rtl-llm/chisel-verilog-pairs · Datasets at Hugging Face

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Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerShiftReg_w1_d3_i0_138( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_238 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /* Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_42( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [2:0] io_in_b_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_b_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_b_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_b_bits_data, // @[Monitor.scala:20:14] input io_in_b_bits_corrupt, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input [63:0] io_in_c_bits_data, // @[Monitor.scala:20:14] input io_in_c_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_ready, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7] wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_b_bits_opcode_0 = io_in_b_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_b_bits_size_0 = io_in_b_bits_size; // @[Monitor.scala:36:7] wire [1:0] io_in_b_bits_source_0 = io_in_b_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_b_bits_mask_0 = io_in_b_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_b_bits_data_0 = io_in_b_bits_data; // @[Monitor.scala:36:7] wire io_in_b_bits_corrupt_0 = io_in_b_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7] wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7] wire [1:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7] wire [63:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7] wire io_in_c_bits_corrupt_0 = io_in_c_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_e_ready_0 = io_in_e_ready; // @[Monitor.scala:36:7] wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [8:0] b_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] b_first_count = 9'h0; // @[Edges.scala:234:25] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire sink_ok_1 = 1'h1; // @[Monitor.scala:367:31] wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire b_first_last = 1'h1; // @[Edges.scala:232:33] wire _legal_source_T_3 = 1'h0; // @[Mux.scala:30:73] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [3:0] _mask_sizeOH_T_3 = io_in_b_bits_size_0; // @[Misc.scala:202:34] wire [31:0] _address_ok_T = io_in_b_bits_address_0; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_70 = io_in_c_bits_address_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 2'h0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire _source_ok_T_1 = io_in_a_bits_source_0 == 2'h1; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1 = _source_ok_T_1; // @[Parameters.scala:1138:31] wire _source_ok_T_2 = io_in_a_bits_source_0 == 2'h2; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2 = _source_ok_T_2; // @[Parameters.scala:1138:31] wire _source_ok_T_3 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_3 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire _source_ok_T_4 = io_in_d_bits_source_0 == 2'h0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_4; // @[Parameters.scala:1138:31] wire _source_ok_T_5 = io_in_d_bits_source_0 == 2'h1; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_1 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire _source_ok_T_6 = io_in_d_bits_source_0 == 2'h2; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_2 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire _source_ok_T_7 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_7 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _legal_source_T = io_in_b_bits_source_0 == 2'h0; // @[Monitor.scala:36:7] wire _legal_source_T_1 = io_in_b_bits_source_0 == 2'h1; // @[Monitor.scala:36:7] wire _legal_source_T_2 = io_in_b_bits_source_0 == 2'h2; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46] wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_5 = {io_in_b_bits_address_0[31:13], io_in_b_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46] wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1 = _address_ok_T_9; // @[Parameters.scala:612:40] wire [13:0] _GEN_0 = io_in_b_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_10 = {io_in_b_bits_address_0[31:14], _GEN_0}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46] wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_2 = _address_ok_T_14; // @[Parameters.scala:612:40] wire [16:0] _GEN_1 = io_in_b_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_15 = {io_in_b_bits_address_0[31:17], _GEN_1}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46] wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_3 = _address_ok_T_19; // @[Parameters.scala:612:40] wire [20:0] _GEN_2 = io_in_b_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_20 = {io_in_b_bits_address_0[31:21], _GEN_2}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_21 = {1'h0, _address_ok_T_20}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_22 = _address_ok_T_21 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_23 = _address_ok_T_22; // @[Parameters.scala:137:46] wire _address_ok_T_24 = _address_ok_T_23 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_4 = _address_ok_T_24; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_25 = {io_in_b_bits_address_0[31:21], io_in_b_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_26 = {1'h0, _address_ok_T_25}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_27 = _address_ok_T_26 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_28 = _address_ok_T_27; // @[Parameters.scala:137:46] wire _address_ok_T_29 = _address_ok_T_28 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_5 = _address_ok_T_29; // @[Parameters.scala:612:40] wire [25:0] _GEN_3 = io_in_b_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_30 = {io_in_b_bits_address_0[31:26], _GEN_3}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_31 = {1'h0, _address_ok_T_30}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_32 = _address_ok_T_31 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_33 = _address_ok_T_32; // @[Parameters.scala:137:46] wire _address_ok_T_34 = _address_ok_T_33 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_6 = _address_ok_T_34; // @[Parameters.scala:612:40] wire [25:0] _GEN_4 = io_in_b_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_35 = {io_in_b_bits_address_0[31:26], _GEN_4}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_36 = {1'h0, _address_ok_T_35}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_37 = _address_ok_T_36 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_38 = _address_ok_T_37; // @[Parameters.scala:137:46] wire _address_ok_T_39 = _address_ok_T_38 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_7 = _address_ok_T_39; // @[Parameters.scala:612:40] wire [27:0] _GEN_5 = io_in_b_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_40 = {io_in_b_bits_address_0[31:28], _GEN_5}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_41 = {1'h0, _address_ok_T_40}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_42 = _address_ok_T_41 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_43 = _address_ok_T_42; // @[Parameters.scala:137:46] wire _address_ok_T_44 = _address_ok_T_43 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_8 = _address_ok_T_44; // @[Parameters.scala:612:40] wire [27:0] _GEN_6 = io_in_b_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_45 = {io_in_b_bits_address_0[31:28], _GEN_6}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_46 = {1'h0, _address_ok_T_45}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_47 = _address_ok_T_46 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_48 = _address_ok_T_47; // @[Parameters.scala:137:46] wire _address_ok_T_49 = _address_ok_T_48 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_9 = _address_ok_T_49; // @[Parameters.scala:612:40] wire [28:0] _GEN_7 = io_in_b_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_50 = {io_in_b_bits_address_0[31:29], _GEN_7}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_51 = {1'h0, _address_ok_T_50}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_52 = _address_ok_T_51 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_53 = _address_ok_T_52; // @[Parameters.scala:137:46] wire _address_ok_T_54 = _address_ok_T_53 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_10 = _address_ok_T_54; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_55 = io_in_b_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_56 = {1'h0, _address_ok_T_55}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_57 = _address_ok_T_56 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_58 = _address_ok_T_57; // @[Parameters.scala:137:46] wire _address_ok_T_59 = _address_ok_T_58 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_11 = _address_ok_T_59; // @[Parameters.scala:612:40] wire _address_ok_T_60 = _address_ok_WIRE_0 \| _address_ok_WIRE_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_61 = _address_ok_T_60 \| _address_ok_WIRE_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_62 = _address_ok_T_61 \| _address_ok_WIRE_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_63 = _address_ok_T_62 \| _address_ok_WIRE_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_64 = _address_ok_T_63 \| _address_ok_WIRE_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_65 = _address_ok_T_64 \| _address_ok_WIRE_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_66 = _address_ok_T_65 \| _address_ok_WIRE_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_67 = _address_ok_T_66 \| _address_ok_WIRE_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_68 = _address_ok_T_67 \| _address_ok_WIRE_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_69 = _address_ok_T_68 \| _address_ok_WIRE_10; // @[Parameters.scala:612:40, :636:64] wire address_ok = _address_ok_T_69 \| _address_ok_WIRE_11; // @[Parameters.scala:612:40, :636:64] wire [26:0] _GEN_8 = 27'hFFF << io_in_b_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_2; // @[package.scala:243:71] assign _is_aligned_mask_T_2 = _GEN_8; // @[package.scala:243:71] wire [26:0] _b_first_beats1_decode_T; // @[package.scala:243:71] assign _b_first_beats1_decode_T = _GEN_8; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_3 = _is_aligned_mask_T_2[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_1 = ~_is_aligned_mask_T_3; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_1 = {20'h0, io_in_b_bits_address_0[11:0] & is_aligned_mask_1}; // @[package.scala:243:46] wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount_1 = _mask_sizeOH_T_3[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_4 = 4'h1 << mask_sizeOH_shiftAmount_1; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_5 = _mask_sizeOH_T_4[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH_1 = {_mask_sizeOH_T_5[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1_1 = io_in_b_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size_1 = mask_sizeOH_1[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2_1 = mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2_1 = mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size_1 & mask_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1_1 = mask_sub_sub_sub_0_1_1 \| _mask_sub_sub_acc_T_2; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size_1 & mask_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1_1 = mask_sub_sub_sub_0_1_1 \| _mask_sub_sub_acc_T_3; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size_1 = mask_sizeOH_1[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_4 = mask_sub_size_1 & mask_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1_1 = mask_sub_sub_0_1_1 \| _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_5 = mask_sub_size_1 & mask_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1_1 = mask_sub_sub_0_1_1 \| _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_6 = mask_sub_size_1 & mask_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1_1 = mask_sub_sub_1_1_1 \| _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_7 = mask_sub_size_1 & mask_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1_1 = mask_sub_sub_1_1_1 \| _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_size_1 = mask_sizeOH_1[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_eq_8 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_size_1 & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_8 = mask_sub_0_1_1 \| _mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_eq_9 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_size_1 & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_9 = mask_sub_0_1_1 \| _mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_eq_10 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_size_1 & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_10 = mask_sub_1_1_1 \| _mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_eq_11 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_size_1 & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_11 = mask_sub_1_1_1 \| _mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_eq_12 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_size_1 & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_12 = mask_sub_2_1_1 \| _mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_eq_13 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_size_1 & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_13 = mask_sub_2_1_1 \| _mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_eq_14 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_size_1 & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_14 = mask_sub_3_1_1 \| _mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_eq_15 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_size_1 & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_15 = mask_sub_3_1_1 \| _mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo_1 = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_1 = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_1 = {mask_lo_hi_1, mask_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_1 = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_1 = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_1 = {mask_hi_hi_1, mask_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] mask_1 = {mask_hi_1, mask_lo_1}; // @[Misc.scala:222:10] wire _legal_source_WIRE_0 = _legal_source_T; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_1 = _legal_source_T_1; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_2 = _legal_source_T_2; // @[Parameters.scala:1138:31] wire _legal_source_T_4 = _legal_source_WIRE_1; // @[Mux.scala:30:73] wire _legal_source_T_6 = _legal_source_T_4; // @[Mux.scala:30:73] wire [1:0] _legal_source_T_5 = {_legal_source_WIRE_2, 1'h0}; // @[Mux.scala:30:73] wire [1:0] _legal_source_T_7 = {1'h0, _legal_source_T_6} \| _legal_source_T_5; // @[Mux.scala:30:73] wire [1:0] _legal_source_WIRE_1_0 = _legal_source_T_7; // @[Mux.scala:30:73] wire legal_source = _legal_source_WIRE_1_0 == io_in_b_bits_source_0; // @[Mux.scala:30:73] wire _source_ok_T_8 = io_in_c_bits_source_0 == 2'h0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_0 = _source_ok_T_8; // @[Parameters.scala:1138:31] wire _source_ok_T_9 = io_in_c_bits_source_0 == 2'h1; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_1 = _source_ok_T_9; // @[Parameters.scala:1138:31] wire _source_ok_T_10 = io_in_c_bits_source_0 == 2'h2; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_2 = _source_ok_T_10; // @[Parameters.scala:1138:31] wire _source_ok_T_11 = _source_ok_WIRE_2_0 \| _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_2 = _source_ok_T_11 \| _source_ok_WIRE_2_2; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN_9 = 27'hFFF << io_in_c_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_4; // @[package.scala:243:71] assign _is_aligned_mask_T_4 = _GEN_9; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T; // @[package.scala:243:71] assign _c_first_beats1_decode_T = _GEN_9; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71] assign _c_first_beats1_decode_T_3 = _GEN_9; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_2 = {20'h0, io_in_c_bits_address_0[11:0] & is_aligned_mask_2}; // @[package.scala:243:46] wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}] wire [32:0] _address_ok_T_71 = {1'h0, _address_ok_T_70}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_72 = _address_ok_T_71 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_73 = _address_ok_T_72; // @[Parameters.scala:137:46] wire _address_ok_T_74 = _address_ok_T_73 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_0 = _address_ok_T_74; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_75 = {io_in_c_bits_address_0[31:13], io_in_c_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_76 = {1'h0, _address_ok_T_75}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_77 = _address_ok_T_76 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_78 = _address_ok_T_77; // @[Parameters.scala:137:46] wire _address_ok_T_79 = _address_ok_T_78 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_1 = _address_ok_T_79; // @[Parameters.scala:612:40] wire [13:0] _GEN_10 = io_in_c_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_80 = {io_in_c_bits_address_0[31:14], _GEN_10}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_81 = {1'h0, _address_ok_T_80}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_82 = _address_ok_T_81 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_83 = _address_ok_T_82; // @[Parameters.scala:137:46] wire _address_ok_T_84 = _address_ok_T_83 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_2 = _address_ok_T_84; // @[Parameters.scala:612:40] wire [16:0] _GEN_11 = io_in_c_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_85 = {io_in_c_bits_address_0[31:17], _GEN_11}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_86 = {1'h0, _address_ok_T_85}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_87 = _address_ok_T_86 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_88 = _address_ok_T_87; // @[Parameters.scala:137:46] wire _address_ok_T_89 = _address_ok_T_88 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_3 = _address_ok_T_89; // @[Parameters.scala:612:40] wire [20:0] _GEN_12 = io_in_c_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_90 = {io_in_c_bits_address_0[31:21], _GEN_12}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_91 = {1'h0, _address_ok_T_90}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_92 = _address_ok_T_91 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_93 = _address_ok_T_92; // @[Parameters.scala:137:46] wire _address_ok_T_94 = _address_ok_T_93 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_4 = _address_ok_T_94; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_95 = {io_in_c_bits_address_0[31:21], io_in_c_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_96 = {1'h0, _address_ok_T_95}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_97 = _address_ok_T_96 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_98 = _address_ok_T_97; // @[Parameters.scala:137:46] wire _address_ok_T_99 = _address_ok_T_98 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_5 = _address_ok_T_99; // @[Parameters.scala:612:40] wire [25:0] _GEN_13 = io_in_c_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_100 = {io_in_c_bits_address_0[31:26], _GEN_13}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_101 = {1'h0, _address_ok_T_100}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_102 = _address_ok_T_101 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_103 = _address_ok_T_102; // @[Parameters.scala:137:46] wire _address_ok_T_104 = _address_ok_T_103 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_6 = _address_ok_T_104; // @[Parameters.scala:612:40] wire [25:0] _GEN_14 = io_in_c_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_105 = {io_in_c_bits_address_0[31:26], _GEN_14}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_106 = {1'h0, _address_ok_T_105}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_107 = _address_ok_T_106 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_108 = _address_ok_T_107; // @[Parameters.scala:137:46] wire _address_ok_T_109 = _address_ok_T_108 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_7 = _address_ok_T_109; // @[Parameters.scala:612:40] wire [27:0] _GEN_15 = io_in_c_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_110 = {io_in_c_bits_address_0[31:28], _GEN_15}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_111 = {1'h0, _address_ok_T_110}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_112 = _address_ok_T_111 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_113 = _address_ok_T_112; // @[Parameters.scala:137:46] wire _address_ok_T_114 = _address_ok_T_113 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_8 = _address_ok_T_114; // @[Parameters.scala:612:40] wire [27:0] _GEN_16 = io_in_c_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_115 = {io_in_c_bits_address_0[31:28], _GEN_16}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_116 = {1'h0, _address_ok_T_115}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_117 = _address_ok_T_116 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_118 = _address_ok_T_117; // @[Parameters.scala:137:46] wire _address_ok_T_119 = _address_ok_T_118 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_9 = _address_ok_T_119; // @[Parameters.scala:612:40] wire [28:0] _GEN_17 = io_in_c_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_120 = {io_in_c_bits_address_0[31:29], _GEN_17}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_121 = {1'h0, _address_ok_T_120}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_122 = _address_ok_T_121 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_123 = _address_ok_T_122; // @[Parameters.scala:137:46] wire _address_ok_T_124 = _address_ok_T_123 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_10 = _address_ok_T_124; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_125 = io_in_c_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_126 = {1'h0, _address_ok_T_125}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_127 = _address_ok_T_126 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_128 = _address_ok_T_127; // @[Parameters.scala:137:46] wire _address_ok_T_129 = _address_ok_T_128 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_11 = _address_ok_T_129; // @[Parameters.scala:612:40] wire _address_ok_T_130 = _address_ok_WIRE_1_0 \| _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_131 = _address_ok_T_130 \| _address_ok_WIRE_1_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_132 = _address_ok_T_131 \| _address_ok_WIRE_1_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_133 = _address_ok_T_132 \| _address_ok_WIRE_1_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_134 = _address_ok_T_133 \| _address_ok_WIRE_1_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_135 = _address_ok_T_134 \| _address_ok_WIRE_1_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_136 = _address_ok_T_135 \| _address_ok_WIRE_1_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_137 = _address_ok_T_136 \| _address_ok_WIRE_1_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_138 = _address_ok_T_137 \| _address_ok_WIRE_1_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_139 = _address_ok_T_138 \| _address_ok_WIRE_1_10; // @[Parameters.scala:612:40, :636:64] wire address_ok_1 = _address_ok_T_139 \| _address_ok_WIRE_1_11; // @[Parameters.scala:612:40, :636:64] wire _T_2451 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_2451; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_2451; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [1:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_2525 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_2525; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_2525; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_2525; // @[Decoupled.scala:51:35] wire _d_first_T_3; // @[Decoupled.scala:51:35] assign _d_first_T_3 = _T_2525; // @[Decoupled.scala:51:35] wire [26:0] _GEN_18 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71] assign _d_first_beats1_decode_T_9 = _GEN_18; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [1:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35] wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35] wire [11:0] _b_first_beats1_decode_T_1 = _b_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _b_first_beats1_decode_T_2 = ~_b_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] b_first_beats1_decode = _b_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _b_first_beats1_opdata_T = io_in_b_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire b_first_beats1_opdata = ~_b_first_beats1_opdata_T; // @[Edges.scala:97:{28,37}] reg [8:0] b_first_counter; // @[Edges.scala:229:27] wire [9:0] _b_first_counter1_T = {1'h0, b_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] b_first_counter1 = _b_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire b_first = b_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _b_first_last_T = b_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire [8:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] _b_first_counter_T = b_first ? 9'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_2; // @[Monitor.scala:410:22] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [3:0] size_2; // @[Monitor.scala:412:22] reg [1:0] source_2; // @[Monitor.scala:413:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _T_2522 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35] wire _c_first_T; // @[Decoupled.scala:51:35] assign _c_first_T = _T_2522; // @[Decoupled.scala:51:35] wire _c_first_T_1; // @[Decoupled.scala:51:35] assign _c_first_T_1 = _T_2522; // @[Decoupled.scala:51:35] wire [11:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [8:0] c_first_counter; // @[Edges.scala:229:27] wire [9:0] _c_first_counter1_T = {1'h0, c_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] c_first_counter1 = _c_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire c_first = c_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T = c_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_1 = c_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last = _c_first_last_T \| _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35] wire [8:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [3:0] size_3; // @[Monitor.scala:517:22] reg [1:0] source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [2:0] inflight; // @[Monitor.scala:614:27] reg [11:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [23:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [2:0] a_set; // @[Monitor.scala:626:34] wire [2:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [11:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [23:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [4:0] _GEN_19 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [4:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_19; // @[Monitor.scala:637:69] wire [4:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_19; // @[Monitor.scala:637:69, :680:101] wire [4:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_19; // @[Monitor.scala:637:69, :749:69] wire [4:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_19; // @[Monitor.scala:637:69, :790:101] wire [11:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [15:0] _a_opcode_lookup_T_6 = {4'h0, _a_opcode_lookup_T_1 & 12'hF}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [4:0] _GEN_20 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [4:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_20; // @[Monitor.scala:641:65] wire [4:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_20; // @[Monitor.scala:641:65, :681:99] wire [4:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_20; // @[Monitor.scala:641:65, :750:67] wire [4:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_20; // @[Monitor.scala:641:65, :791:99] wire [23:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [23:0] _a_size_lookup_T_6 = {16'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [23:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[23:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [3:0] _GEN_21 = 4'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [3:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_21; // @[OneHot.scala:58:35] wire [3:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_21; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire _T_2377 = _T_2451 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_2377 ? _a_set_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_2377 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_2377 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [4:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [34:0] _a_opcodes_set_T_1 = {31'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_2377 ? _a_opcodes_set_T_1[11:0] : 12'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [4:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [35:0] _a_sizes_set_T_1 = {31'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_2377 ? _a_sizes_set_T_1[23:0] : 24'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [2:0] d_clr; // @[Monitor.scala:664:34] wire [2:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [11:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [23:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_22 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_22; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_22; // @[Monitor.scala:673:46, :783:46] wire _T_2423 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [3:0] _GEN_23 = 4'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [3:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_23; // @[OneHot.scala:58:35] wire [3:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_23; // @[OneHot.scala:58:35] wire [3:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_23; // @[OneHot.scala:58:35] wire [3:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_23; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_2423 & ~d_release_ack ? _d_clr_wo_ready_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire _T_2392 = _T_2525 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_2392 ? _d_clr_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire [46:0] _d_opcodes_clr_T_5 = 47'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_2392 ? _d_opcodes_clr_T_5[11:0] : 12'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [46:0] _d_sizes_clr_T_5 = 47'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_2392 ? _d_sizes_clr_T_5[23:0] : 24'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [2:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [2:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [2:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [11:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [11:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [11:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [23:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [23:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [23:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [2:0] inflight_1; // @[Monitor.scala:726:35] reg [11:0] inflight_opcodes_1; // @[Monitor.scala:727:35] reg [23:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [11:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [8:0] c_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] c_first_counter1_1 = _c_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire c_first_1 = c_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T_2 = c_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_3 = c_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last_1 = _c_first_last_T_2 \| _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [2:0] c_set; // @[Monitor.scala:738:34] wire [2:0] c_set_wo_ready; // @[Monitor.scala:739:34] wire [11:0] c_opcodes_set; // @[Monitor.scala:740:34] wire [23:0] c_sizes_set; // @[Monitor.scala:741:34] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [11:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [15:0] _c_opcode_lookup_T_6 = {4'h0, _c_opcode_lookup_T_1 & 12'hF}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [23:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [23:0] _c_size_lookup_T_6 = {16'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [23:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[23:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40] wire [4:0] c_sizes_set_interm; // @[Monitor.scala:755:40] wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44] wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7] wire [3:0] _GEN_24 = 4'h1 << io_in_c_bits_source_0; // @[OneHot.scala:58:35] wire [3:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35] assign _c_set_wo_ready_T = _GEN_24; // @[OneHot.scala:58:35] wire [3:0] _c_set_T; // @[OneHot.scala:58:35] assign _c_set_T = _GEN_24; // @[OneHot.scala:58:35] assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire _T_2464 = _T_2522 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35] assign c_set = _T_2464 ? _c_set_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53] wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}] assign c_opcodes_set_interm = _T_2464 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}] wire [4:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51] wire [4:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:766:{51,59}] assign c_sizes_set_interm = _T_2464 ? _c_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}] wire [4:0] _c_opcodes_set_T = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79] wire [34:0] _c_opcodes_set_T_1 = {31'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:659:54, :754:40, :767:{54,79}] assign c_opcodes_set = _T_2464 ? _c_opcodes_set_T_1[11:0] : 12'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}] wire [4:0] _c_sizes_set_T = {io_in_c_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :768:77] wire [35:0] _c_sizes_set_T_1 = {31'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:659:54, :755:40, :768:{52,77}] assign c_sizes_set = _T_2464 ? _c_sizes_set_T_1[23:0] : 24'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}] wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47] wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95] wire c_probe_ack = _c_probe_ack_T \| _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}] wire [2:0] d_clr_1; // @[Monitor.scala:774:34] wire [2:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [11:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [23:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_2495 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_2495 & d_release_ack_1 ? _d_clr_wo_ready_T_1[2:0] : 3'h0; // @[OneHot.scala:58:35] wire _T_2477 = _T_2525 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_2477 ? _d_clr_T_1[2:0] : 3'h0; // @[OneHot.scala:58:35] wire [46:0] _d_opcodes_clr_T_11 = 47'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_2477 ? _d_opcodes_clr_T_11[11:0] : 12'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [46:0] _d_sizes_clr_T_11 = 47'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_2477 ? _d_sizes_clr_T_11[23:0] : 24'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}] wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}] wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}] wire [2:0] _inflight_T_3 = inflight_1 \| c_set; // @[Monitor.scala:726:35, :738:34, :814:35] wire [2:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [2:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [11:0] _inflight_opcodes_T_3 = inflight_opcodes_1 \| c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43] wire [11:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [11:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [23:0] _inflight_sizes_T_3 = inflight_sizes_1 \| c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41] wire [23:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [23:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26] wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26] reg [7:0] inflight_2; // @[Monitor.scala:828:27] wire [11:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_3; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_3 = _d_first_counter1_T_3[8:0]; // @[Edges.scala:230:28] wire d_first_3 = d_first_counter_3 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_6 = d_first_counter_3 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_7 = d_first_beats1_3 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_3 = _d_first_last_T_6 \| _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}] wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [7:0] d_set; // @[Monitor.scala:833:25] wire _T_2531 = _T_2525 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35] wire [7:0] _GEN_25 = {5'h0, io_in_d_bits_sink_0}; // @[OneHot.scala:58:35] wire [7:0] _d_set_T = 8'h1 << _GEN_25; // @[OneHot.scala:58:35] assign d_set = _T_2531 ? _d_set_T : 8'h0; // @[OneHot.scala:58:35] wire [7:0] e_clr; // @[Monitor.scala:839:25] wire _T_2540 = io_in_e_ready_0 & io_in_e_valid_0; // @[Decoupled.scala:51:35] wire [7:0] _GEN_26 = {5'h0, io_in_e_bits_sink_0}; // @[OneHot.scala:58:35] wire [7:0] _e_clr_T = 8'h1 << _GEN_26; // @[OneHot.scala:58:35] assign e_clr = _T_2540 ? _e_clr_T : 8'h0; // @[OneHot.scala:58:35]
Generate the Verilog code corresponding to the following Chisel files. File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File RocketCore.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import chisel3.withClock import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.tile._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property import scala.collection.mutable.ArrayBuffer case class RocketCoreParams( xLen: Int = 64, pgLevels: Int = 3, // sv39 default bootFreqHz: BigInt = 0, useVM: Boolean = true, useUser: Boolean = false, useSupervisor: Boolean = false, useHypervisor: Boolean = false, useDebug: Boolean = true, useAtomics: Boolean = true, useAtomicsOnlyForIO: Boolean = false, useCompressed: Boolean = true, useRVE: Boolean = false, useConditionalZero: Boolean = false, useZba: Boolean = false, useZbb: Boolean = false, useZbs: Boolean = false, nLocalInterrupts: Int = 0, useNMI: Boolean = false, nBreakpoints: Int = 1, useBPWatch: Boolean = false, mcontextWidth: Int = 0, scontextWidth: Int = 0, nPMPs: Int = 8, nPerfCounters: Int = 0, haveBasicCounters: Boolean = true, haveCFlush: Boolean = false, misaWritable: Boolean = true, nL2TLBEntries: Int = 0, nL2TLBWays: Int = 1, nPTECacheEntries: Int = 8, mtvecInit: Option[BigInt] = Some(BigInt(0)), mtvecWritable: Boolean = true, fastLoadWord: Boolean = true, fastLoadByte: Boolean = false, branchPredictionModeCSR: Boolean = false, clockGate: Boolean = false, mvendorid: Int = 0, // 0 means non-commercial implementation mimpid: Int = 0x20181004, // release date in BCD mulDiv: Option[MulDivParams] = Some(MulDivParams()), fpu: Option[FPUParams] = Some(FPUParams()), debugROB: Option[DebugROBParams] = None, // if size < 1, SW ROB, else HW ROB haveCease: Boolean = true, // non-standard CEASE instruction haveSimTimeout: Boolean = true, // add plusarg for simulation timeout vector: Option[RocketCoreVectorParams] = None ) extends CoreParams { val lgPauseCycles = 5 val haveFSDirty = false val pmpGranularity: Int = if (useHypervisor) 4096 else 4 val fetchWidth: Int = if (useCompressed) 2 else 1 // fetchWidth doubled, but coreInstBytes halved, for RVC: val decodeWidth: Int = fetchWidth / (if (useCompressed) 2 else 1) val retireWidth: Int = 1 val instBits: Int = if (useCompressed) 16 else 32 val lrscCycles: Int = 80 // worst case is 14 mispredicted branches + slop val traceHasWdata: Boolean = debugROB.isDefined // ooo wb, so no wdata in trace override val useVector = vector.isDefined override val vectorUseDCache = vector.map(_.useDCache).getOrElse(false) override def vLen = vector.map(_.vLen).getOrElse(0) override def eLen = vector.map(_.eLen).getOrElse(0) override def vfLen = vector.map(_.vfLen).getOrElse(0) override def vfh = vector.map(_.vfh).getOrElse(false) override def vExts = vector.map(_.vExts).getOrElse(Nil) override def vMemDataBits = vector.map(_.vMemDataBits).getOrElse(0) override val customIsaExt = Option.when(haveCease)("xrocket") // CEASE instruction override def minFLen: Int = fpu.map(_.minFLen).getOrElse(32) override def customCSRs(implicit p: Parameters) = new RocketCustomCSRs } trait HasRocketCoreParameters extends HasCoreParameters { lazy val rocketParams: RocketCoreParams = tileParams.core.asInstanceOf[RocketCoreParams] val fastLoadWord = rocketParams.fastLoadWord val fastLoadByte = rocketParams.fastLoadByte val mulDivParams = rocketParams.mulDiv.getOrElse(MulDivParams()) // TODO ask andrew about this require(!fastLoadByte \|\| fastLoadWord) require(!rocketParams.haveFSDirty, "rocket doesn't support setting fs dirty from outside, please disable haveFSDirty") } class RocketCustomCSRs(implicit p: Parameters) extends CustomCSRs with HasRocketCoreParameters { override def bpmCSR = { rocketParams.branchPredictionModeCSR.option(CustomCSR(bpmCSRId, BigInt(1), Some(BigInt(0)))) } private def haveDCache = tileParams.dcache.get.scratch.isEmpty override def chickenCSR = { val mask = BigInt( tileParams.dcache.get.clockGate.toInt << 0 \| rocketParams.clockGate.toInt << 1 \| rocketParams.clockGate.toInt << 2 \| 1 << 3 \| // disableSpeculativeICacheRefill haveDCache.toInt << 9 \| // suppressCorruptOnGrantData tileParams.icache.get.prefetch.toInt << 17 ) Some(CustomCSR(chickenCSRId, mask, Some(mask))) } def disableICachePrefetch = getOrElse(chickenCSR, _.value(17), true.B) def marchid = CustomCSR.constant(CSRs.marchid, BigInt(1)) def mvendorid = CustomCSR.constant(CSRs.mvendorid, BigInt(rocketParams.mvendorid)) // mimpid encodes a release version in the form of a BCD-encoded datestamp. def mimpid = CustomCSR.constant(CSRs.mimpid, BigInt(rocketParams.mimpid)) override def decls = super.decls :+ marchid :+ mvendorid :+ mimpid } class CoreInterrupts(val hasBeu: Boolean)(implicit p: Parameters) extends TileInterrupts()(p) { val buserror = Option.when(hasBeu)(Bool()) } trait HasRocketCoreIO extends HasRocketCoreParameters { implicit val p: Parameters def nTotalRoCCCSRs: Int val io = IO(new CoreBundle()(p) { val hartid = Input(UInt(hartIdLen.W)) val reset_vector = Input(UInt(resetVectorLen.W)) val interrupts = Input(new CoreInterrupts(tileParams.asInstanceOf[RocketTileParams].beuAddr.isDefined)) val imem = new FrontendIO val dmem = new HellaCacheIO val ptw = Flipped(new DatapathPTWIO()) val fpu = Flipped(new FPUCoreIO()) val rocc = Flipped(new RoCCCoreIO(nTotalRoCCCSRs)) val trace = Output(new TraceBundle) val bpwatch = Output(Vec(coreParams.nBreakpoints, new BPWatch(coreParams.retireWidth))) val cease = Output(Bool()) val wfi = Output(Bool()) val traceStall = Input(Bool()) val vector = if (usingVector) Some(Flipped(new VectorCoreIO)) else None }) } class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p) with HasRocketCoreParameters with HasRocketCoreIO { def nTotalRoCCCSRs = tile.roccCSRs.flatten.size import ALU._ val clock_en_reg = RegInit(true.B) val long_latency_stall = Reg(Bool()) val id_reg_pause = Reg(Bool()) val imem_might_request_reg = Reg(Bool()) val clock_en = WireDefault(true.B) val gated_clock = if (!rocketParams.clockGate) clock else ClockGate(clock, clock_en, "rocket_clock_gate") class RocketImpl { // entering gated-clock domain // performance counters def pipelineIDToWB[T <: Data](x: T): T = RegEnable(RegEnable(RegEnable(x, !ctrl_killd), ex_pc_valid), mem_pc_valid) val perfEvents = new EventSets(Seq( new EventSet((mask, hits) => Mux(wb_xcpt, mask(0), wb_valid && pipelineIDToWB((mask & hits).orR)), Seq( ("exception", () => false.B), ("load", () => id_ctrl.mem && id_ctrl.mem_cmd === M_XRD && !id_ctrl.fp), ("store", () => id_ctrl.mem && id_ctrl.mem_cmd === M_XWR && !id_ctrl.fp), ("amo", () => usingAtomics.B && id_ctrl.mem && (isAMO(id_ctrl.mem_cmd) \|\| id_ctrl.mem_cmd.isOneOf(M_XLR, M_XSC))), ("system", () => id_ctrl.csr =/= CSR.N), ("arith", () => id_ctrl.wxd && !(id_ctrl.jal \|\| id_ctrl.jalr \|\| id_ctrl.mem \|\| id_ctrl.fp \|\| id_ctrl.mul \|\| id_ctrl.div \|\| id_ctrl.csr =/= CSR.N)), ("branch", () => id_ctrl.branch), ("jal", () => id_ctrl.jal), ("jalr", () => id_ctrl.jalr)) ++ (if (!usingMulDiv) Seq() else Seq( ("mul", () => if (pipelinedMul) id_ctrl.mul else id_ctrl.div && (id_ctrl.alu_fn & FN_DIV) =/= FN_DIV), ("div", () => if (pipelinedMul) id_ctrl.div else id_ctrl.div && (id_ctrl.alu_fn & FN_DIV) === FN_DIV))) ++ (if (!usingFPU) Seq() else Seq( ("fp load", () => id_ctrl.fp && io.fpu.dec.ldst && io.fpu.dec.wen), ("fp store", () => id_ctrl.fp && io.fpu.dec.ldst && !io.fpu.dec.wen), ("fp add", () => id_ctrl.fp && io.fpu.dec.fma && io.fpu.dec.swap23), ("fp mul", () => id_ctrl.fp && io.fpu.dec.fma && !io.fpu.dec.swap23 && !io.fpu.dec.ren3), ("fp mul-add", () => id_ctrl.fp && io.fpu.dec.fma && io.fpu.dec.ren3), ("fp div/sqrt", () => id_ctrl.fp && (io.fpu.dec.div \|\| io.fpu.dec.sqrt)), ("fp other", () => id_ctrl.fp && !(io.fpu.dec.ldst \|\| io.fpu.dec.fma \|\| io.fpu.dec.div \|\| io.fpu.dec.sqrt))))), new EventSet((mask, hits) => (mask & hits).orR, Seq( ("load-use interlock", () => id_ex_hazard && ex_ctrl.mem \|\| id_mem_hazard && mem_ctrl.mem \|\| id_wb_hazard && wb_ctrl.mem), ("long-latency interlock", () => id_sboard_hazard), ("csr interlock", () => id_ex_hazard && ex_ctrl.csr =/= CSR.N \|\| id_mem_hazard && mem_ctrl.csr =/= CSR.N \|\| id_wb_hazard && wb_ctrl.csr =/= CSR.N), ("I$ blocked", () => icache_blocked), ("D$ blocked", () => id_ctrl.mem && dcache_blocked), ("branch misprediction", () => take_pc_mem && mem_direction_misprediction), ("control-flow target misprediction", () => take_pc_mem && mem_misprediction && mem_cfi && !mem_direction_misprediction && !icache_blocked), ("flush", () => wb_reg_flush_pipe), ("replay", () => replay_wb)) ++ (if (!usingMulDiv) Seq() else Seq( ("mul/div interlock", () => id_ex_hazard && (ex_ctrl.mul \|\| ex_ctrl.div) \|\| id_mem_hazard && (mem_ctrl.mul \|\| mem_ctrl.div) \|\| id_wb_hazard && wb_ctrl.div))) ++ (if (!usingFPU) Seq() else Seq( ("fp interlock", () => id_ex_hazard && ex_ctrl.fp \|\| id_mem_hazard && mem_ctrl.fp \|\| id_wb_hazard && wb_ctrl.fp \|\| id_ctrl.fp && id_stall_fpu)))), new EventSet((mask, hits) => (mask & hits).orR, Seq( ("I$ miss", () => io.imem.perf.acquire), ("D$ miss", () => io.dmem.perf.acquire), ("D$ release", () => io.dmem.perf.release), ("ITLB miss", () => io.imem.perf.tlbMiss), ("DTLB miss", () => io.dmem.perf.tlbMiss), ("L2 TLB miss", () => io.ptw.perf.l2miss))))) val pipelinedMul = usingMulDiv && mulDivParams.mulUnroll == xLen val decode_table = { (if (usingMulDiv) new MDecode(pipelinedMul) +: (xLen > 32).option(new M64Decode(pipelinedMul)).toSeq else Nil) ++: (if (usingAtomics) new ADecode +: (xLen > 32).option(new A64Decode).toSeq else Nil) ++: (if (fLen >= 32) new FDecode +: (xLen > 32).option(new F64Decode).toSeq else Nil) ++: (if (fLen >= 64) new DDecode +: (xLen > 32).option(new D64Decode).toSeq else Nil) ++: (if (minFLen == 16) new HDecode +: (xLen > 32).option(new H64Decode).toSeq ++: (fLen >= 64).option(new HDDecode).toSeq else Nil) ++: (usingRoCC.option(new RoCCDecode)) ++: (if (xLen == 32) new I32Decode else new I64Decode) +: (usingVM.option(new SVMDecode)) ++: (usingSupervisor.option(new SDecode)) ++: (usingHypervisor.option(new HypervisorDecode)) ++: ((usingHypervisor && (xLen == 64)).option(new Hypervisor64Decode)) ++: (usingDebug.option(new DebugDecode)) ++: (usingNMI.option(new NMIDecode)) ++: (usingConditionalZero.option(new ConditionalZeroDecode)) ++: Seq(new FenceIDecode(tile.dcache.flushOnFenceI)) ++: coreParams.haveCFlush.option(new CFlushDecode(tile.dcache.canSupportCFlushLine)) ++: rocketParams.haveCease.option(new CeaseDecode) ++: usingVector.option(new VCFGDecode) ++: (if (coreParams.useZba) new ZbaDecode +: (xLen > 32).option(new Zba64Decode).toSeq else Nil) ++: (if (coreParams.useZbb) Seq(new ZbbDecode, if (xLen == 32) new Zbb32Decode else new Zbb64Decode) else Nil) ++: coreParams.useZbs.option(new ZbsDecode) ++: Seq(new IDecode) } flatMap(_.table) val ex_ctrl = Reg(new IntCtrlSigs) val mem_ctrl = Reg(new IntCtrlSigs) val wb_ctrl = Reg(new IntCtrlSigs) val ex_reg_xcpt_interrupt = Reg(Bool()) val ex_reg_valid = Reg(Bool()) val ex_reg_rvc = Reg(Bool()) val ex_reg_btb_resp = Reg(new BTBResp) val ex_reg_xcpt = Reg(Bool()) val ex_reg_flush_pipe = Reg(Bool()) val ex_reg_load_use = Reg(Bool()) val ex_reg_cause = Reg(UInt()) val ex_reg_replay = Reg(Bool()) val ex_reg_pc = Reg(UInt()) val ex_reg_mem_size = Reg(UInt()) val ex_reg_hls = Reg(Bool()) val ex_reg_inst = Reg(Bits()) val ex_reg_raw_inst = Reg(UInt()) val ex_reg_wphit = Reg(Vec(nBreakpoints, Bool())) val ex_reg_set_vconfig = Reg(Bool()) val mem_reg_xcpt_interrupt = Reg(Bool()) val mem_reg_valid = Reg(Bool()) val mem_reg_rvc = Reg(Bool()) val mem_reg_btb_resp = Reg(new BTBResp) val mem_reg_xcpt = Reg(Bool()) val mem_reg_replay = Reg(Bool()) val mem_reg_flush_pipe = Reg(Bool()) val mem_reg_cause = Reg(UInt()) val mem_reg_slow_bypass = Reg(Bool()) val mem_reg_load = Reg(Bool()) val mem_reg_store = Reg(Bool()) val mem_reg_set_vconfig = Reg(Bool()) val mem_reg_sfence = Reg(Bool()) val mem_reg_pc = Reg(UInt()) val mem_reg_inst = Reg(Bits()) val mem_reg_mem_size = Reg(UInt()) val mem_reg_hls_or_dv = Reg(Bool()) val mem_reg_raw_inst = Reg(UInt()) val mem_reg_wdata = Reg(Bits()) val mem_reg_rs2 = Reg(Bits()) val mem_br_taken = Reg(Bool()) val take_pc_mem = Wire(Bool()) val mem_reg_wphit = Reg(Vec(nBreakpoints, Bool())) val wb_reg_valid = Reg(Bool()) val wb_reg_xcpt = Reg(Bool()) val wb_reg_replay = Reg(Bool()) val wb_reg_flush_pipe = Reg(Bool()) val wb_reg_cause = Reg(UInt()) val wb_reg_set_vconfig = Reg(Bool()) val wb_reg_sfence = Reg(Bool()) val wb_reg_pc = Reg(UInt()) val wb_reg_mem_size = Reg(UInt()) val wb_reg_hls_or_dv = Reg(Bool()) val wb_reg_hfence_v = Reg(Bool()) val wb_reg_hfence_g = Reg(Bool()) val wb_reg_inst = Reg(Bits()) val wb_reg_raw_inst = Reg(UInt()) val wb_reg_wdata = Reg(Bits()) val wb_reg_rs2 = Reg(Bits()) val take_pc_wb = Wire(Bool()) val wb_reg_wphit = Reg(Vec(nBreakpoints, Bool())) val take_pc_mem_wb = take_pc_wb \|\| take_pc_mem val take_pc = take_pc_mem_wb // decode stage val ibuf = Module(new IBuf) val id_expanded_inst = ibuf.io.inst.map(_.bits.inst) val id_raw_inst = ibuf.io.inst.map(_.bits.raw) val id_inst = id_expanded_inst.map(_.bits) ibuf.io.imem <> io.imem.resp ibuf.io.kill := take_pc require(decodeWidth == 1 /* TODO / && retireWidth == decodeWidth) require(!(coreParams.useRVE && coreParams.fpu.nonEmpty), "Can't select both RVE and floating-point") require(!(coreParams.useRVE && coreParams.useHypervisor), "Can't select both RVE and Hypervisor") val id_ctrl = Wire(new IntCtrlSigs).decode(id_inst(0), decode_table) val lgNXRegs = if (coreParams.useRVE) 4 else 5 val regAddrMask = (1 << lgNXRegs) - 1 def decodeReg(x: UInt) = (x.extract(x.getWidth-1, lgNXRegs).asBool, x(lgNXRegs-1, 0)) val (id_raddr3_illegal, id_raddr3) = decodeReg(id_expanded_inst(0).rs3) val (id_raddr2_illegal, id_raddr2) = decodeReg(id_expanded_inst(0).rs2) val (id_raddr1_illegal, id_raddr1) = decodeReg(id_expanded_inst(0).rs1) val (id_waddr_illegal, id_waddr) = decodeReg(id_expanded_inst(0).rd) val id_load_use = Wire(Bool()) val id_reg_fence = RegInit(false.B) val id_ren = IndexedSeq(id_ctrl.rxs1, id_ctrl.rxs2) val id_raddr = IndexedSeq(id_raddr1, id_raddr2) val rf = new RegFile(regAddrMask, xLen) val id_rs = id_raddr.map(rf.read _) val ctrl_killd = Wire(Bool()) val id_npc = (ibuf.io.pc.asSInt + ImmGen(IMM_UJ, id_inst(0))).asUInt val csr = Module(new CSRFile(perfEvents, coreParams.customCSRs.decls, tile.roccCSRs.flatten, tile.rocketParams.beuAddr.isDefined)) val id_csr_en = id_ctrl.csr.isOneOf(CSR.S, CSR.C, CSR.W) val id_system_insn = id_ctrl.csr === CSR.I val id_csr_ren = id_ctrl.csr.isOneOf(CSR.S, CSR.C) && id_expanded_inst(0).rs1 === 0.U val id_csr = Mux(id_system_insn && id_ctrl.mem, CSR.N, Mux(id_csr_ren, CSR.R, id_ctrl.csr)) val id_csr_flush = id_system_insn \|\| (id_csr_en && !id_csr_ren && csr.io.decode(0).write_flush) val id_set_vconfig = Seq(Instructions.VSETVLI, Instructions.VSETIVLI, Instructions.VSETVL).map(_ === id_inst(0)).orR && usingVector.B id_ctrl.vec := false.B if (usingVector) { val v_decode = rocketParams.vector.get.decoder(p) v_decode.io.inst := id_inst(0) v_decode.io.vconfig := csr.io.vector.get.vconfig when (v_decode.io.legal) { id_ctrl.legal := !csr.io.vector.get.vconfig.vtype.vill id_ctrl.fp := v_decode.io.fp id_ctrl.rocc := false.B id_ctrl.branch := false.B id_ctrl.jal := false.B id_ctrl.jalr := false.B id_ctrl.rxs2 := v_decode.io.read_rs2 id_ctrl.rxs1 := v_decode.io.read_rs1 id_ctrl.mem := false.B id_ctrl.rfs1 := v_decode.io.read_frs1 id_ctrl.rfs2 := false.B id_ctrl.rfs3 := false.B id_ctrl.wfd := v_decode.io.write_frd id_ctrl.mul := false.B id_ctrl.div := false.B id_ctrl.wxd := v_decode.io.write_rd id_ctrl.csr := CSR.N id_ctrl.fence_i := false.B id_ctrl.fence := false.B id_ctrl.amo := false.B id_ctrl.dp := false.B id_ctrl.vec := true.B } } val id_illegal_insn = !id_ctrl.legal \|\| (id_ctrl.mul \|\| id_ctrl.div) && !csr.io.status.isa('m'-'a') \|\| id_ctrl.amo && !csr.io.status.isa('a'-'a') \|\| id_ctrl.fp && (csr.io.decode(0).fp_illegal \|\| (io.fpu.illegal_rm && !id_ctrl.vec)) \|\| (id_ctrl.vec) && (csr.io.decode(0).vector_illegal \|\| csr.io.vector.map(_.vconfig.vtype.vill).getOrElse(false.B)) \|\| id_ctrl.dp && !csr.io.status.isa('d'-'a') \|\| ibuf.io.inst(0).bits.rvc && !csr.io.status.isa('c'-'a') \|\| id_raddr2_illegal && id_ctrl.rxs2 \|\| id_raddr1_illegal && id_ctrl.rxs1 \|\| id_waddr_illegal && id_ctrl.wxd \|\| id_ctrl.rocc && csr.io.decode(0).rocc_illegal \|\| id_csr_en && (csr.io.decode(0).read_illegal \|\| !id_csr_ren && csr.io.decode(0).write_illegal) \|\| !ibuf.io.inst(0).bits.rvc && (id_system_insn && csr.io.decode(0).system_illegal) val id_virtual_insn = id_ctrl.legal && ((id_csr_en && !(!id_csr_ren && csr.io.decode(0).write_illegal) && csr.io.decode(0).virtual_access_illegal) \|\| (!ibuf.io.inst(0).bits.rvc && id_system_insn && csr.io.decode(0).virtual_system_illegal)) // stall decode for fences (now, for AMO.rl; later, for AMO.aq and FENCE) val id_amo_aq = id_inst(0)(26) val id_amo_rl = id_inst(0)(25) val id_fence_pred = id_inst(0)(27,24) val id_fence_succ = id_inst(0)(23,20) val id_fence_next = id_ctrl.fence \|\| id_ctrl.amo && id_amo_aq val id_mem_busy = !io.dmem.ordered \|\| io.dmem.req.valid when (!id_mem_busy) { id_reg_fence := false.B } val id_rocc_busy = usingRoCC.B && (io.rocc.busy \|\| ex_reg_valid && ex_ctrl.rocc \|\| mem_reg_valid && mem_ctrl.rocc \|\| wb_reg_valid && wb_ctrl.rocc) val id_csr_rocc_write = tile.roccCSRs.flatten.map(_.id.U === id_inst(0)(31,20)).orR && id_csr_en && !id_csr_ren val id_vec_busy = io.vector.map(v => v.backend_busy \|\| v.trap_check_busy).getOrElse(false.B) val id_do_fence = WireDefault(id_rocc_busy && (id_ctrl.fence \|\| id_csr_rocc_write) \|\| id_vec_busy && id_ctrl.fence \|\| id_mem_busy && (id_ctrl.amo && id_amo_rl \|\| id_ctrl.fence_i \|\| id_reg_fence && (id_ctrl.mem \|\| id_ctrl.rocc))) val bpu = Module(new BreakpointUnit(nBreakpoints)) bpu.io.status := csr.io.status bpu.io.bp := csr.io.bp bpu.io.pc := ibuf.io.pc bpu.io.ea := mem_reg_wdata bpu.io.mcontext := csr.io.mcontext bpu.io.scontext := csr.io.scontext val id_xcpt0 = ibuf.io.inst(0).bits.xcpt0 val id_xcpt1 = ibuf.io.inst(0).bits.xcpt1 val (id_xcpt, id_cause) = checkExceptions(List( (csr.io.interrupt, csr.io.interrupt_cause), (bpu.io.debug_if, CSR.debugTriggerCause.U), (bpu.io.xcpt_if, Causes.breakpoint.U), (id_xcpt0.pf.inst, Causes.fetch_page_fault.U), (id_xcpt0.gf.inst, Causes.fetch_guest_page_fault.U), (id_xcpt0.ae.inst, Causes.fetch_access.U), (id_xcpt1.pf.inst, Causes.fetch_page_fault.U), (id_xcpt1.gf.inst, Causes.fetch_guest_page_fault.U), (id_xcpt1.ae.inst, Causes.fetch_access.U), (id_virtual_insn, Causes.virtual_instruction.U), (id_illegal_insn, Causes.illegal_instruction.U))) val idCoverCauses = List( (CSR.debugTriggerCause, "DEBUG_TRIGGER"), (Causes.breakpoint, "BREAKPOINT"), (Causes.fetch_access, "FETCH_ACCESS"), (Causes.illegal_instruction, "ILLEGAL_INSTRUCTION") ) ++ (if (usingVM) List( (Causes.fetch_page_fault, "FETCH_PAGE_FAULT") ) else Nil) coverExceptions(id_xcpt, id_cause, "DECODE", idCoverCauses) val dcache_bypass_data = if (fastLoadByte) io.dmem.resp.bits.data(xLen-1, 0) else if (fastLoadWord) io.dmem.resp.bits.data_word_bypass(xLen-1, 0) else wb_reg_wdata // detect bypass opportunities val ex_waddr = ex_reg_inst(11,7) & regAddrMask.U val mem_waddr = mem_reg_inst(11,7) & regAddrMask.U val wb_waddr = wb_reg_inst(11,7) & regAddrMask.U val bypass_sources = IndexedSeq( (true.B, 0.U, 0.U), // treat reading x0 as a bypass (ex_reg_valid && ex_ctrl.wxd, ex_waddr, mem_reg_wdata), (mem_reg_valid && mem_ctrl.wxd && !mem_ctrl.mem, mem_waddr, wb_reg_wdata), (mem_reg_valid && mem_ctrl.wxd, mem_waddr, dcache_bypass_data)) val id_bypass_src = id_raddr.map(raddr => bypass_sources.map(s => s._1 && s._2 === raddr)) // execute stage val bypass_mux = bypass_sources.map(_._3) val ex_reg_rs_bypass = Reg(Vec(id_raddr.size, Bool())) val ex_reg_rs_lsb = Reg(Vec(id_raddr.size, UInt(log2Ceil(bypass_sources.size).W))) val ex_reg_rs_msb = Reg(Vec(id_raddr.size, UInt())) val ex_rs = for (i <- 0 until id_raddr.size) yield Mux(ex_reg_rs_bypass(i), bypass_mux(ex_reg_rs_lsb(i)), Cat(ex_reg_rs_msb(i), ex_reg_rs_lsb(i))) val ex_imm = ImmGen(ex_ctrl.sel_imm, ex_reg_inst) val ex_rs1shl = Mux(ex_reg_inst(3), ex_rs(0)(31,0), ex_rs(0)) << ex_reg_inst(14,13) val ex_op1 = MuxLookup(ex_ctrl.sel_alu1, 0.S)(Seq( A1_RS1 -> ex_rs(0).asSInt, A1_PC -> ex_reg_pc.asSInt, A1_RS1SHL -> (if (rocketParams.useZba) ex_rs1shl.asSInt else 0.S) )) val ex_op2_oh = UIntToOH(Mux(ex_ctrl.sel_alu2(0), (ex_reg_inst >> 20).asUInt, ex_rs(1))(log2Ceil(xLen)-1,0)).asSInt val ex_op2 = MuxLookup(ex_ctrl.sel_alu2, 0.S)(Seq( A2_RS2 -> ex_rs(1).asSInt, A2_IMM -> ex_imm, A2_SIZE -> Mux(ex_reg_rvc, 2.S, 4.S), ) ++ (if (coreParams.useZbs) Seq( A2_RS2OH -> ex_op2_oh, A2_IMMOH -> ex_op2_oh, ) else Nil)) val (ex_new_vl, ex_new_vconfig) = if (usingVector) { val ex_new_vtype = VType.fromUInt(MuxCase(ex_rs(1), Seq( ex_reg_inst(31,30).andR -> ex_reg_inst(29,20), !ex_reg_inst(31) -> ex_reg_inst(30,20)))) val ex_avl = Mux(ex_ctrl.rxs1, Mux(ex_reg_inst(19,15) === 0.U, Mux(ex_reg_inst(11,7) === 0.U, csr.io.vector.get.vconfig.vl, ex_new_vtype.vlMax), ex_rs(0) ), ex_reg_inst(19,15)) val ex_new_vl = ex_new_vtype.vl(ex_avl, csr.io.vector.get.vconfig.vl, false.B, false.B, false.B) val ex_new_vconfig = Wire(new VConfig) ex_new_vconfig.vtype := ex_new_vtype ex_new_vconfig.vl := ex_new_vl (Some(ex_new_vl), Some(ex_new_vconfig)) } else { (None, None) } val alu = Module(new ALU) alu.io.dw := ex_ctrl.alu_dw alu.io.fn := ex_ctrl.alu_fn alu.io.in2 := ex_op2.asUInt alu.io.in1 := ex_op1.asUInt // multiplier and divider val div = Module(new MulDiv(if (pipelinedMul) mulDivParams.copy(mulUnroll = 0) else mulDivParams, width = xLen)) div.io.req.valid := ex_reg_valid && ex_ctrl.div div.io.req.bits.dw := ex_ctrl.alu_dw div.io.req.bits.fn := ex_ctrl.alu_fn div.io.req.bits.in1 := ex_rs(0) div.io.req.bits.in2 := ex_rs(1) div.io.req.bits.tag := ex_waddr val mul = pipelinedMul.option { val m = Module(new PipelinedMultiplier(xLen, 2)) m.io.req.valid := ex_reg_valid && ex_ctrl.mul m.io.req.bits := div.io.req.bits m } ex_reg_valid := !ctrl_killd ex_reg_replay := !take_pc && ibuf.io.inst(0).valid && ibuf.io.inst(0).bits.replay ex_reg_xcpt := !ctrl_killd && id_xcpt ex_reg_xcpt_interrupt := !take_pc && ibuf.io.inst(0).valid && csr.io.interrupt when (!ctrl_killd) { ex_ctrl := id_ctrl ex_reg_rvc := ibuf.io.inst(0).bits.rvc ex_ctrl.csr := id_csr when (id_ctrl.fence && id_fence_succ === 0.U) { id_reg_pause := true.B } when (id_fence_next) { id_reg_fence := true.B } when (id_xcpt) { // pass PC down ALU writeback pipeline for badaddr ex_ctrl.alu_fn := FN_ADD ex_ctrl.alu_dw := DW_XPR ex_ctrl.sel_alu1 := A1_RS1 // badaddr := instruction ex_ctrl.sel_alu2 := A2_ZERO when (id_xcpt1.asUInt.orR) { // badaddr := PC+2 ex_ctrl.sel_alu1 := A1_PC ex_ctrl.sel_alu2 := A2_SIZE ex_reg_rvc := true.B } when (bpu.io.xcpt_if \|\| id_xcpt0.asUInt.orR) { // badaddr := PC ex_ctrl.sel_alu1 := A1_PC ex_ctrl.sel_alu2 := A2_ZERO } } ex_reg_flush_pipe := id_ctrl.fence_i \|\| id_csr_flush ex_reg_load_use := id_load_use ex_reg_hls := usingHypervisor.B && id_system_insn && id_ctrl.mem_cmd.isOneOf(M_XRD, M_XWR, M_HLVX) ex_reg_mem_size := Mux(usingHypervisor.B && id_system_insn, id_inst(0)(27, 26), id_inst(0)(13, 12)) when (id_ctrl.mem_cmd.isOneOf(M_SFENCE, M_HFENCEV, M_HFENCEG, M_FLUSH_ALL)) { ex_reg_mem_size := Cat(id_raddr2 =/= 0.U, id_raddr1 =/= 0.U) } when (id_ctrl.mem_cmd === M_SFENCE && csr.io.status.v) { ex_ctrl.mem_cmd := M_HFENCEV } if (tile.dcache.flushOnFenceI) { when (id_ctrl.fence_i) { ex_reg_mem_size := 0.U } } for (i <- 0 until id_raddr.size) { val do_bypass = id_bypass_src(i).reduce(_\|\|_) val bypass_src = PriorityEncoder(id_bypass_src(i)) ex_reg_rs_bypass(i) := do_bypass ex_reg_rs_lsb(i) := bypass_src when (id_ren(i) && !do_bypass) { ex_reg_rs_lsb(i) := id_rs(i)(log2Ceil(bypass_sources.size)-1, 0) ex_reg_rs_msb(i) := id_rs(i) >> log2Ceil(bypass_sources.size) } } when (id_illegal_insn \|\| id_virtual_insn) { val inst = Mux(ibuf.io.inst(0).bits.rvc, id_raw_inst(0)(15, 0), id_raw_inst(0)) ex_reg_rs_bypass(0) := false.B ex_reg_rs_lsb(0) := inst(log2Ceil(bypass_sources.size)-1, 0) ex_reg_rs_msb(0) := inst >> log2Ceil(bypass_sources.size) } } when (!ctrl_killd \|\| csr.io.interrupt \|\| ibuf.io.inst(0).bits.replay) { ex_reg_cause := id_cause ex_reg_inst := id_inst(0) ex_reg_raw_inst := id_raw_inst(0) ex_reg_pc := ibuf.io.pc ex_reg_btb_resp := ibuf.io.btb_resp ex_reg_wphit := bpu.io.bpwatch.map { bpw => bpw.ivalid(0) } ex_reg_set_vconfig := id_set_vconfig && !id_xcpt } // replay inst in ex stage? val ex_pc_valid = ex_reg_valid \|\| ex_reg_replay \|\| ex_reg_xcpt_interrupt val wb_dcache_miss = wb_ctrl.mem && !io.dmem.resp.valid val replay_ex_structural = ex_ctrl.mem && !io.dmem.req.ready \|\| ex_ctrl.div && !div.io.req.ready \|\| ex_ctrl.vec && !io.vector.map(_.ex.ready).getOrElse(true.B) val replay_ex_load_use = wb_dcache_miss && ex_reg_load_use val replay_ex = ex_reg_replay \|\| (ex_reg_valid && (replay_ex_structural \|\| replay_ex_load_use)) val ctrl_killx = take_pc_mem_wb \|\| replay_ex \|\| !ex_reg_valid // detect 2-cycle load-use delay for LB/LH/SC val ex_slow_bypass = ex_ctrl.mem_cmd === M_XSC \|\| ex_reg_mem_size < 2.U val ex_sfence = usingVM.B && ex_ctrl.mem && (ex_ctrl.mem_cmd === M_SFENCE \|\| ex_ctrl.mem_cmd === M_HFENCEV \|\| ex_ctrl.mem_cmd === M_HFENCEG) val (ex_xcpt, ex_cause) = checkExceptions(List( (ex_reg_xcpt_interrupt \|\| ex_reg_xcpt, ex_reg_cause))) val exCoverCauses = idCoverCauses coverExceptions(ex_xcpt, ex_cause, "EXECUTE", exCoverCauses) // memory stage val mem_pc_valid = mem_reg_valid \|\| mem_reg_replay \|\| mem_reg_xcpt_interrupt val mem_br_target = mem_reg_pc.asSInt + Mux(mem_ctrl.branch && mem_br_taken, ImmGen(IMM_SB, mem_reg_inst), Mux(mem_ctrl.jal, ImmGen(IMM_UJ, mem_reg_inst), Mux(mem_reg_rvc, 2.S, 4.S))) val mem_npc = (Mux(mem_ctrl.jalr \|\| mem_reg_sfence, encodeVirtualAddress(mem_reg_wdata, mem_reg_wdata).asSInt, mem_br_target) & (-2).S).asUInt val mem_wrong_npc = Mux(ex_pc_valid, mem_npc =/= ex_reg_pc, Mux(ibuf.io.inst(0).valid \|\| ibuf.io.imem.valid, mem_npc =/= ibuf.io.pc, true.B)) val mem_npc_misaligned = !csr.io.status.isa('c'-'a') && mem_npc(1) && !mem_reg_sfence val mem_int_wdata = Mux(!mem_reg_xcpt && (mem_ctrl.jalr ^ mem_npc_misaligned), mem_br_target, mem_reg_wdata.asSInt).asUInt val mem_cfi = mem_ctrl.branch \|\| mem_ctrl.jalr \|\| mem_ctrl.jal val mem_cfi_taken = (mem_ctrl.branch && mem_br_taken) \|\| mem_ctrl.jalr \|\| mem_ctrl.jal val mem_direction_misprediction = mem_ctrl.branch && mem_br_taken =/= (usingBTB.B && mem_reg_btb_resp.taken) val mem_misprediction = if (usingBTB) mem_wrong_npc else mem_cfi_taken take_pc_mem := mem_reg_valid && !mem_reg_xcpt && (mem_misprediction \|\| mem_reg_sfence) mem_reg_valid := !ctrl_killx mem_reg_replay := !take_pc_mem_wb && replay_ex mem_reg_xcpt := !ctrl_killx && ex_xcpt mem_reg_xcpt_interrupt := !take_pc_mem_wb && ex_reg_xcpt_interrupt // on pipeline flushes, cause mem_npc to hold the sequential npc, which // will drive the W-stage npc mux when (mem_reg_valid && mem_reg_flush_pipe) { mem_reg_sfence := false.B }.elsewhen (ex_pc_valid) { mem_ctrl := ex_ctrl mem_reg_rvc := ex_reg_rvc mem_reg_load := ex_ctrl.mem && isRead(ex_ctrl.mem_cmd) mem_reg_store := ex_ctrl.mem && isWrite(ex_ctrl.mem_cmd) mem_reg_sfence := ex_sfence mem_reg_btb_resp := ex_reg_btb_resp mem_reg_flush_pipe := ex_reg_flush_pipe mem_reg_slow_bypass := ex_slow_bypass mem_reg_wphit := ex_reg_wphit mem_reg_set_vconfig := ex_reg_set_vconfig mem_reg_cause := ex_cause mem_reg_inst := ex_reg_inst mem_reg_raw_inst := ex_reg_raw_inst mem_reg_mem_size := ex_reg_mem_size mem_reg_hls_or_dv := io.dmem.req.bits.dv mem_reg_pc := ex_reg_pc // IDecode ensured they are 1H mem_reg_wdata := Mux(ex_reg_set_vconfig, ex_new_vl.getOrElse(alu.io.out), alu.io.out) mem_br_taken := alu.io.cmp_out when (ex_ctrl.rxs2 && (ex_ctrl.mem \|\| ex_ctrl.rocc \|\| ex_sfence)) { val size = Mux(ex_ctrl.rocc, log2Ceil(xLen/8).U, ex_reg_mem_size) mem_reg_rs2 := new StoreGen(size, 0.U, ex_rs(1), coreDataBytes).data } if (usingVector) { when (ex_reg_set_vconfig) { mem_reg_rs2 := ex_new_vconfig.get.asUInt } } when (ex_ctrl.jalr && csr.io.status.debug) { // flush I$ on D-mode JALR to effect uncached fetch without D$ flush mem_ctrl.fence_i := true.B mem_reg_flush_pipe := true.B } } val mem_breakpoint = (mem_reg_load && bpu.io.xcpt_ld) \|\| (mem_reg_store && bpu.io.xcpt_st) val mem_debug_breakpoint = (mem_reg_load && bpu.io.debug_ld) \|\| (mem_reg_store && bpu.io.debug_st) val (mem_ldst_xcpt, mem_ldst_cause) = checkExceptions(List( (mem_debug_breakpoint, CSR.debugTriggerCause.U), (mem_breakpoint, Causes.breakpoint.U))) val (mem_xcpt, mem_cause) = checkExceptions(List( (mem_reg_xcpt_interrupt \|\| mem_reg_xcpt, mem_reg_cause), (mem_reg_valid && mem_npc_misaligned, Causes.misaligned_fetch.U), (mem_reg_valid && mem_ldst_xcpt, mem_ldst_cause))) val memCoverCauses = (exCoverCauses ++ List( (CSR.debugTriggerCause, "DEBUG_TRIGGER"), (Causes.breakpoint, "BREAKPOINT"), (Causes.misaligned_fetch, "MISALIGNED_FETCH") )).distinct coverExceptions(mem_xcpt, mem_cause, "MEMORY", memCoverCauses) val dcache_kill_mem = mem_reg_valid && mem_ctrl.wxd && io.dmem.replay_next // structural hazard on writeback port val fpu_kill_mem = mem_reg_valid && mem_ctrl.fp && io.fpu.nack_mem val vec_kill_mem = mem_reg_valid && mem_ctrl.mem && io.vector.map(_.mem.block_mem).getOrElse(false.B) val vec_kill_all = mem_reg_valid && io.vector.map(_.mem.block_all).getOrElse(false.B) val replay_mem = dcache_kill_mem \|\| mem_reg_replay \|\| fpu_kill_mem \|\| vec_kill_mem \|\| vec_kill_all val killm_common = dcache_kill_mem \|\| take_pc_wb \|\| mem_reg_xcpt \|\| !mem_reg_valid div.io.kill := killm_common && RegNext(div.io.req.fire) val ctrl_killm = killm_common \|\| mem_xcpt \|\| fpu_kill_mem \|\| vec_kill_mem // writeback stage wb_reg_valid := !ctrl_killm wb_reg_replay := replay_mem && !take_pc_wb wb_reg_xcpt := mem_xcpt && !take_pc_wb && !io.vector.map(_.mem.block_all).getOrElse(false.B) wb_reg_flush_pipe := !ctrl_killm && mem_reg_flush_pipe when (mem_pc_valid) { wb_ctrl := mem_ctrl wb_reg_sfence := mem_reg_sfence wb_reg_wdata := Mux(!mem_reg_xcpt && mem_ctrl.fp && mem_ctrl.wxd, io.fpu.toint_data, mem_int_wdata) when (mem_ctrl.rocc \|\| mem_reg_sfence \|\| mem_reg_set_vconfig) { wb_reg_rs2 := mem_reg_rs2 } wb_reg_cause := mem_cause wb_reg_inst := mem_reg_inst wb_reg_raw_inst := mem_reg_raw_inst wb_reg_mem_size := mem_reg_mem_size wb_reg_hls_or_dv := mem_reg_hls_or_dv wb_reg_hfence_v := mem_ctrl.mem_cmd === M_HFENCEV wb_reg_hfence_g := mem_ctrl.mem_cmd === M_HFENCEG wb_reg_pc := mem_reg_pc wb_reg_wphit := mem_reg_wphit \| bpu.io.bpwatch.map { bpw => (bpw.rvalid(0) && mem_reg_load) \|\| (bpw.wvalid(0) && mem_reg_store) } wb_reg_set_vconfig := mem_reg_set_vconfig } val (wb_xcpt, wb_cause) = checkExceptions(List( (wb_reg_xcpt, wb_reg_cause), (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.pf.st, Causes.store_page_fault.U), (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.pf.ld, Causes.load_page_fault.U), (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.gf.st, Causes.store_guest_page_fault.U), (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.gf.ld, Causes.load_guest_page_fault.U), (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.ae.st, Causes.store_access.U), (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.ae.ld, Causes.load_access.U), (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.ma.st, Causes.misaligned_store.U), (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.ma.ld, Causes.misaligned_load.U) )) val wbCoverCauses = List( (Causes.misaligned_store, "MISALIGNED_STORE"), (Causes.misaligned_load, "MISALIGNED_LOAD"), (Causes.store_access, "STORE_ACCESS"), (Causes.load_access, "LOAD_ACCESS") ) ++ (if(usingVM) List( (Causes.store_page_fault, "STORE_PAGE_FAULT"), (Causes.load_page_fault, "LOAD_PAGE_FAULT") ) else Nil) ++ (if (usingHypervisor) List( (Causes.store_guest_page_fault, "STORE_GUEST_PAGE_FAULT"), (Causes.load_guest_page_fault, "LOAD_GUEST_PAGE_FAULT"), ) else Nil) coverExceptions(wb_xcpt, wb_cause, "WRITEBACK", wbCoverCauses) val wb_pc_valid = wb_reg_valid \|\| wb_reg_replay \|\| wb_reg_xcpt val wb_wxd = wb_reg_valid && wb_ctrl.wxd val wb_set_sboard = wb_ctrl.div \|\| wb_dcache_miss \|\| wb_ctrl.rocc \|\| wb_ctrl.vec val replay_wb_common = io.dmem.s2_nack \|\| wb_reg_replay val replay_wb_rocc = wb_reg_valid && wb_ctrl.rocc && !io.rocc.cmd.ready val replay_wb_csr: Bool = wb_reg_valid && csr.io.rw_stall val replay_wb_vec = wb_reg_valid && io.vector.map(_.wb.replay).getOrElse(false.B) val replay_wb = replay_wb_common \|\| replay_wb_rocc \|\| replay_wb_csr \|\| replay_wb_vec take_pc_wb := replay_wb \|\| wb_xcpt \|\| csr.io.eret \|\| wb_reg_flush_pipe // writeback arbitration val dmem_resp_xpu = !io.dmem.resp.bits.tag(0).asBool val dmem_resp_fpu = io.dmem.resp.bits.tag(0).asBool val dmem_resp_waddr = io.dmem.resp.bits.tag(5, 1) val dmem_resp_valid = io.dmem.resp.valid && io.dmem.resp.bits.has_data val dmem_resp_replay = dmem_resp_valid && io.dmem.resp.bits.replay class LLWB extends Bundle { val data = UInt(xLen.W) val tag = UInt(5.W) } val ll_arb = Module(new Arbiter(new LLWB, 3)) // div, rocc, vec ll_arb.io.in.foreach(_.valid := false.B) ll_arb.io.in.foreach(_.bits := DontCare) val ll_wdata = WireInit(ll_arb.io.out.bits.data) val ll_waddr = WireInit(ll_arb.io.out.bits.tag) val ll_wen = WireInit(ll_arb.io.out.fire) ll_arb.io.out.ready := !wb_wxd div.io.resp.ready := ll_arb.io.in(0).ready ll_arb.io.in(0).valid := div.io.resp.valid ll_arb.io.in(0).bits.data := div.io.resp.bits.data ll_arb.io.in(0).bits.tag := div.io.resp.bits.tag if (usingRoCC) { io.rocc.resp.ready := ll_arb.io.in(1).ready ll_arb.io.in(1).valid := io.rocc.resp.valid ll_arb.io.in(1).bits.data := io.rocc.resp.bits.data ll_arb.io.in(1).bits.tag := io.rocc.resp.bits.rd } else { // tie off RoCC io.rocc.resp.ready := false.B io.rocc.mem.req.ready := false.B } io.vector.map { v => v.resp.ready := Mux(v.resp.bits.fp, !(dmem_resp_valid && dmem_resp_fpu), ll_arb.io.in(2).ready) ll_arb.io.in(2).valid := v.resp.valid && !v.resp.bits.fp ll_arb.io.in(2).bits.data := v.resp.bits.data ll_arb.io.in(2).bits.tag := v.resp.bits.rd } // Dont care mem since not all RoCC need accessing memory io.rocc.mem := DontCare when (dmem_resp_replay && dmem_resp_xpu) { ll_arb.io.out.ready := false.B ll_waddr := dmem_resp_waddr ll_wen := true.B } val wb_valid = wb_reg_valid && !replay_wb && !wb_xcpt val wb_wen = wb_valid && wb_ctrl.wxd val rf_wen = wb_wen \|\| ll_wen val rf_waddr = Mux(ll_wen, ll_waddr, wb_waddr) val rf_wdata = Mux(dmem_resp_valid && dmem_resp_xpu, io.dmem.resp.bits.data(xLen-1, 0), Mux(ll_wen, ll_wdata, Mux(wb_ctrl.csr =/= CSR.N, csr.io.rw.rdata, Mux(wb_ctrl.mul, mul.map(_.io.resp.bits.data).getOrElse(wb_reg_wdata), wb_reg_wdata)))) when (rf_wen) { rf.write(rf_waddr, rf_wdata) } // hook up control/status regfile csr.io.ungated_clock := clock csr.io.decode(0).inst := id_inst(0) csr.io.exception := wb_xcpt csr.io.cause := wb_cause csr.io.retire := wb_valid csr.io.inst(0) := (if (usingCompressed) Cat(Mux(wb_reg_raw_inst(1, 0).andR, wb_reg_inst >> 16, 0.U), wb_reg_raw_inst(15, 0)) else wb_reg_inst) csr.io.interrupts := io.interrupts csr.io.hartid := io.hartid io.fpu.fcsr_rm := csr.io.fcsr_rm val vector_fcsr_flags = io.vector.map(_.set_fflags.bits).getOrElse(0.U(5.W)) val vector_fcsr_flags_valid = io.vector.map(_.set_fflags.valid).getOrElse(false.B) csr.io.fcsr_flags.valid := io.fpu.fcsr_flags.valid \| vector_fcsr_flags_valid csr.io.fcsr_flags.bits := (io.fpu.fcsr_flags.bits & Fill(5, io.fpu.fcsr_flags.valid)) \| (vector_fcsr_flags & Fill(5, vector_fcsr_flags_valid)) io.fpu.time := csr.io.time(31,0) io.fpu.hartid := io.hartid csr.io.rocc_interrupt := io.rocc.interrupt csr.io.pc := wb_reg_pc val tval_dmem_addr = !wb_reg_xcpt val tval_any_addr = tval_dmem_addr \|\| wb_reg_cause.isOneOf(Causes.breakpoint.U, Causes.fetch_access.U, Causes.fetch_page_fault.U, Causes.fetch_guest_page_fault.U) val tval_inst = wb_reg_cause === Causes.illegal_instruction.U val tval_valid = wb_xcpt && (tval_any_addr \|\| tval_inst) csr.io.gva := wb_xcpt && (tval_any_addr && csr.io.status.v \|\| tval_dmem_addr && wb_reg_hls_or_dv) csr.io.tval := Mux(tval_valid, encodeVirtualAddress(wb_reg_wdata, wb_reg_wdata), 0.U) val (htval, mhtinst_read_pseudo) = { val htval_valid_imem = wb_reg_xcpt && wb_reg_cause === Causes.fetch_guest_page_fault.U val htval_imem = Mux(htval_valid_imem, io.imem.gpa.bits, 0.U) assert(!htval_valid_imem \|\| io.imem.gpa.valid) val htval_valid_dmem = wb_xcpt && tval_dmem_addr && io.dmem.s2_xcpt.gf.asUInt.orR && !io.dmem.s2_xcpt.pf.asUInt.orR val htval_dmem = Mux(htval_valid_dmem, io.dmem.s2_gpa, 0.U) val htval = (htval_dmem \| htval_imem) >> hypervisorExtraAddrBits // read pseudoinstruction if a guest-page fault is caused by an implicit memory access for VS-stage address translation val mhtinst_read_pseudo = (io.imem.gpa_is_pte && htval_valid_imem) \|\| (io.dmem.s2_gpa_is_pte && htval_valid_dmem) (htval, mhtinst_read_pseudo) } csr.io.vector.foreach { v => v.set_vconfig.valid := wb_reg_set_vconfig && wb_reg_valid v.set_vconfig.bits := wb_reg_rs2.asTypeOf(new VConfig) v.set_vs_dirty := wb_valid && wb_ctrl.vec v.set_vstart.valid := wb_valid && wb_reg_set_vconfig v.set_vstart.bits := 0.U } io.vector.foreach { v => when (v.wb.retire \|\| v.wb.xcpt \|\| wb_ctrl.vec) { csr.io.pc := v.wb.pc csr.io.retire := v.wb.retire csr.io.inst(0) := v.wb.inst when (v.wb.xcpt && !wb_reg_xcpt) { wb_xcpt := true.B wb_cause := v.wb.cause csr.io.tval := v.wb.tval } } v.wb.store_pending := io.dmem.store_pending v.wb.vxrm := csr.io.vector.get.vxrm v.wb.frm := csr.io.fcsr_rm csr.io.vector.get.set_vxsat := v.set_vxsat when (v.set_vconfig.valid) { csr.io.vector.get.set_vconfig.valid := true.B csr.io.vector.get.set_vconfig.bits := v.set_vconfig.bits } when (v.set_vstart.valid) { csr.io.vector.get.set_vstart.valid := true.B csr.io.vector.get.set_vstart.bits := v.set_vstart.bits } } csr.io.htval := htval csr.io.mhtinst_read_pseudo := mhtinst_read_pseudo io.ptw.ptbr := csr.io.ptbr io.ptw.hgatp := csr.io.hgatp io.ptw.vsatp := csr.io.vsatp (io.ptw.customCSRs.csrs zip csr.io.customCSRs).map { case (lhs, rhs) => lhs <> rhs } io.ptw.status := csr.io.status io.ptw.hstatus := csr.io.hstatus io.ptw.gstatus := csr.io.gstatus io.ptw.pmp := csr.io.pmp csr.io.rw.addr := wb_reg_inst(31,20) csr.io.rw.cmd := CSR.maskCmd(wb_reg_valid, wb_ctrl.csr) csr.io.rw.wdata := wb_reg_wdata io.rocc.csrs <> csr.io.roccCSRs io.trace.time := csr.io.time io.trace.insns := csr.io.trace if (rocketParams.debugROB.isDefined) { val sz = rocketParams.debugROB.get.size if (sz < 1) { // use unsynthesizable ROB val csr_trace_with_wdata = WireInit(csr.io.trace(0)) csr_trace_with_wdata.wdata.get := rf_wdata val should_wb = WireInit((wb_ctrl.wfd \|\| (wb_ctrl.wxd && wb_waddr =/= 0.U)) && !csr.io.trace(0).exception) val has_wb = WireInit(wb_ctrl.wxd && wb_wen && !wb_set_sboard) val wb_addr = WireInit(wb_waddr + Mux(wb_ctrl.wfd, 32.U, 0.U)) io.vector.foreach { v => when (v.wb.retire) { should_wb := v.wb.rob_should_wb has_wb := false.B wb_addr := Cat(v.wb.rob_should_wb_fp, csr_trace_with_wdata.insn(11,7)) }} DebugROB.pushTrace(clock, reset, io.hartid, csr_trace_with_wdata, should_wb, has_wb, wb_addr) io.trace.insns(0) := DebugROB.popTrace(clock, reset, io.hartid) DebugROB.pushWb(clock, reset, io.hartid, ll_wen, rf_waddr, rf_wdata) } else { // synthesizable ROB (no FPRs) require(!usingVector, "Synthesizable ROB does not support vector implementations") val csr_trace_with_wdata = WireInit(csr.io.trace(0)) csr_trace_with_wdata.wdata.get := rf_wdata val debug_rob = Module(new HardDebugROB(sz, 32)) debug_rob.io.i_insn := csr_trace_with_wdata debug_rob.io.should_wb := (wb_ctrl.wfd \|\| (wb_ctrl.wxd && wb_waddr =/= 0.U)) && !csr.io.trace(0).exception debug_rob.io.has_wb := wb_ctrl.wxd && wb_wen && !wb_set_sboard debug_rob.io.tag := wb_waddr + Mux(wb_ctrl.wfd, 32.U, 0.U) debug_rob.io.wb_val := ll_wen debug_rob.io.wb_tag := rf_waddr debug_rob.io.wb_data := rf_wdata io.trace.insns(0) := debug_rob.io.o_insn } } else { io.trace.insns := csr.io.trace } for (((iobpw, wphit), bp) <- io.bpwatch zip wb_reg_wphit zip csr.io.bp) { iobpw.valid(0) := wphit iobpw.action := bp.control.action // tie off bpwatch valids iobpw.rvalid.foreach(_ := false.B) iobpw.wvalid.foreach(_ := false.B) iobpw.ivalid.foreach(_ := false.B) } val hazard_targets = Seq((id_ctrl.rxs1 && id_raddr1 =/= 0.U, id_raddr1), (id_ctrl.rxs2 && id_raddr2 =/= 0.U, id_raddr2), (id_ctrl.wxd && id_waddr =/= 0.U, id_waddr)) val fp_hazard_targets = Seq((io.fpu.dec.ren1, id_raddr1), (io.fpu.dec.ren2, id_raddr2), (io.fpu.dec.ren3, id_raddr3), (io.fpu.dec.wen, id_waddr)) val sboard = new Scoreboard(32, true) sboard.clear(ll_wen, ll_waddr) def id_sboard_clear_bypass(r: UInt) = { // ll_waddr arrives late when D$ has ECC, so reshuffle the hazard check if (!tileParams.dcache.get.dataECC.isDefined) ll_wen && ll_waddr === r else div.io.resp.fire && div.io.resp.bits.tag === r \|\| dmem_resp_replay && dmem_resp_xpu && dmem_resp_waddr === r } val id_sboard_hazard = checkHazards(hazard_targets, rd => sboard.read(rd) && !id_sboard_clear_bypass(rd)) sboard.set(wb_set_sboard && wb_wen, wb_waddr) // stall for RAW/WAW hazards on CSRs, loads, AMOs, and mul/div in execute stage. val ex_cannot_bypass = ex_ctrl.csr =/= CSR.N \|\| ex_ctrl.jalr \|\| ex_ctrl.mem \|\| ex_ctrl.mul \|\| ex_ctrl.div \|\| ex_ctrl.fp \|\| ex_ctrl.rocc \|\| ex_ctrl.vec val data_hazard_ex = ex_ctrl.wxd && checkHazards(hazard_targets, _ === ex_waddr) val fp_data_hazard_ex = id_ctrl.fp && ex_ctrl.wfd && checkHazards(fp_hazard_targets, _ === ex_waddr) val id_ex_hazard = ex_reg_valid && (data_hazard_ex && ex_cannot_bypass \|\| fp_data_hazard_ex) // stall for RAW/WAW hazards on CSRs, LB/LH, and mul/div in memory stage. val mem_mem_cmd_bh = if (fastLoadWord) (!fastLoadByte).B && mem_reg_slow_bypass else true.B val mem_cannot_bypass = mem_ctrl.csr =/= CSR.N \|\| mem_ctrl.mem && mem_mem_cmd_bh \|\| mem_ctrl.mul \|\| mem_ctrl.div \|\| mem_ctrl.fp \|\| mem_ctrl.rocc \|\| mem_ctrl.vec val data_hazard_mem = mem_ctrl.wxd && checkHazards(hazard_targets, _ === mem_waddr) val fp_data_hazard_mem = id_ctrl.fp && mem_ctrl.wfd && checkHazards(fp_hazard_targets, _ === mem_waddr) val id_mem_hazard = mem_reg_valid && (data_hazard_mem && mem_cannot_bypass \|\| fp_data_hazard_mem) id_load_use := mem_reg_valid && data_hazard_mem && mem_ctrl.mem val id_vconfig_hazard = id_ctrl.vec && ( (ex_reg_valid && ex_reg_set_vconfig) \|\| (mem_reg_valid && mem_reg_set_vconfig) \|\| (wb_reg_valid && wb_reg_set_vconfig)) // stall for RAW/WAW hazards on load/AMO misses and mul/div in writeback. val data_hazard_wb = wb_ctrl.wxd && checkHazards(hazard_targets, _ === wb_waddr) val fp_data_hazard_wb = id_ctrl.fp && wb_ctrl.wfd && checkHazards(fp_hazard_targets, _ === wb_waddr) val id_wb_hazard = wb_reg_valid && (data_hazard_wb && wb_set_sboard \|\| fp_data_hazard_wb) val id_stall_fpu = if (usingFPU) { val fp_sboard = new Scoreboard(32) fp_sboard.set(((wb_dcache_miss \|\| wb_ctrl.vec) && wb_ctrl.wfd \|\| io.fpu.sboard_set) && wb_valid, wb_waddr) val v_ll = io.vector.map(v => v.resp.fire && v.resp.bits.fp).getOrElse(false.B) fp_sboard.clear((dmem_resp_replay && dmem_resp_fpu) \|\| v_ll, io.fpu.ll_resp_tag) fp_sboard.clear(io.fpu.sboard_clr, io.fpu.sboard_clra) checkHazards(fp_hazard_targets, fp_sboard.read _) } else false.B val dcache_blocked = { // speculate that a blocked D$ will unblock the cycle after a Grant val blocked = Reg(Bool()) blocked := !io.dmem.req.ready && io.dmem.clock_enabled && !io.dmem.perf.grant && (blocked \|\| io.dmem.req.valid \|\| io.dmem.s2_nack) blocked && !io.dmem.perf.grant } val rocc_blocked = Reg(Bool()) rocc_blocked := !wb_xcpt && !io.rocc.cmd.ready && (io.rocc.cmd.valid \|\| rocc_blocked) val ctrl_stalld = id_ex_hazard \|\| id_mem_hazard \|\| id_wb_hazard \|\| id_sboard_hazard \|\| id_vconfig_hazard \|\| csr.io.singleStep && (ex_reg_valid \|\| mem_reg_valid \|\| wb_reg_valid) \|\| id_csr_en && csr.io.decode(0).fp_csr && !io.fpu.fcsr_rdy \|\| id_csr_en && csr.io.decode(0).vector_csr && id_vec_busy \|\| id_ctrl.fp && id_stall_fpu \|\| id_ctrl.mem && dcache_blocked \|\| // reduce activity during D$ misses id_ctrl.rocc && rocc_blocked \|\| // reduce activity while RoCC is busy id_ctrl.div && (!(div.io.req.ready \|\| (div.io.resp.valid && !wb_wxd)) \|\| div.io.req.valid) \|\| // reduce odds of replay !clock_en \|\| id_do_fence \|\| csr.io.csr_stall \|\| id_reg_pause \|\| io.traceStall ctrl_killd := !ibuf.io.inst(0).valid \|\| ibuf.io.inst(0).bits.replay \|\| take_pc_mem_wb \|\| ctrl_stalld \|\| csr.io.interrupt io.imem.req.valid := take_pc io.imem.req.bits.speculative := !take_pc_wb io.imem.req.bits.pc := Mux(wb_xcpt \|\| csr.io.eret, csr.io.evec, // exception or [m\|s]ret Mux(replay_wb, wb_reg_pc, // replay mem_npc)) // flush or branch misprediction io.imem.flush_icache := wb_reg_valid && wb_ctrl.fence_i && !io.dmem.s2_nack io.imem.might_request := { imem_might_request_reg := ex_pc_valid \|\| mem_pc_valid \|\| io.ptw.customCSRs.disableICacheClockGate \|\| io.vector.map(_.trap_check_busy).getOrElse(false.B) imem_might_request_reg } io.imem.progress := RegNext(wb_reg_valid && !replay_wb_common) io.imem.sfence.valid := wb_reg_valid && wb_reg_sfence io.imem.sfence.bits.rs1 := wb_reg_mem_size(0) io.imem.sfence.bits.rs2 := wb_reg_mem_size(1) io.imem.sfence.bits.addr := wb_reg_wdata io.imem.sfence.bits.asid := wb_reg_rs2 io.imem.sfence.bits.hv := wb_reg_hfence_v io.imem.sfence.bits.hg := wb_reg_hfence_g io.ptw.sfence := io.imem.sfence ibuf.io.inst(0).ready := !ctrl_stalld io.imem.btb_update.valid := mem_reg_valid && !take_pc_wb && mem_wrong_npc && (!mem_cfi \|\| mem_cfi_taken) io.imem.btb_update.bits.isValid := mem_cfi io.imem.btb_update.bits.cfiType := Mux((mem_ctrl.jal \|\| mem_ctrl.jalr) && mem_waddr(0), CFIType.call, Mux(mem_ctrl.jalr && (mem_reg_inst(19,15) & regAddrMask.U) === BitPat("b00?01"), CFIType.ret, Mux(mem_ctrl.jal \|\| mem_ctrl.jalr, CFIType.jump, CFIType.branch))) io.imem.btb_update.bits.target := io.imem.req.bits.pc io.imem.btb_update.bits.br_pc := (if (usingCompressed) mem_reg_pc + Mux(mem_reg_rvc, 0.U, 2.U) else mem_reg_pc) io.imem.btb_update.bits.pc := ~(~io.imem.btb_update.bits.br_pc \| (coreInstBytesfetchWidth-1).U) io.imem.btb_update.bits.prediction := mem_reg_btb_resp io.imem.btb_update.bits.taken := DontCare io.imem.bht_update.valid := mem_reg_valid && !take_pc_wb io.imem.bht_update.bits.pc := io.imem.btb_update.bits.pc io.imem.bht_update.bits.taken := mem_br_taken io.imem.bht_update.bits.mispredict := mem_wrong_npc io.imem.bht_update.bits.branch := mem_ctrl.branch io.imem.bht_update.bits.prediction := mem_reg_btb_resp.bht // Connect RAS in Frontend io.imem.ras_update := DontCare io.fpu.valid := !ctrl_killd && id_ctrl.fp io.fpu.killx := ctrl_killx io.fpu.killm := killm_common io.fpu.inst := id_inst(0) io.fpu.fromint_data := ex_rs(0) io.fpu.ll_resp_val := dmem_resp_valid && dmem_resp_fpu io.fpu.ll_resp_data := (if (minFLen == 32) io.dmem.resp.bits.data_word_bypass else io.dmem.resp.bits.data) io.fpu.ll_resp_type := io.dmem.resp.bits.size io.fpu.ll_resp_tag := dmem_resp_waddr io.fpu.keep_clock_enabled := io.ptw.customCSRs.disableCoreClockGate io.fpu.v_sew := csr.io.vector.map(_.vconfig.vtype.vsew).getOrElse(0.U) io.vector.map { v => when (!(dmem_resp_valid && dmem_resp_fpu)) { io.fpu.ll_resp_val := v.resp.valid && v.resp.bits.fp io.fpu.ll_resp_data := v.resp.bits.data io.fpu.ll_resp_type := v.resp.bits.size io.fpu.ll_resp_tag := v.resp.bits.rd } } io.vector.foreach { v => v.ex.valid := ex_reg_valid && (ex_ctrl.vec \|\| rocketParams.vector.get.issueVConfig.B && ex_reg_set_vconfig) && !ctrl_killx v.ex.inst := ex_reg_inst v.ex.vconfig := csr.io.vector.get.vconfig v.ex.vstart := Mux(mem_reg_valid && mem_ctrl.vec \|\| wb_reg_valid && wb_ctrl.vec, 0.U, csr.io.vector.get.vstart) v.ex.rs1 := ex_rs(0) v.ex.rs2 := ex_rs(1) v.ex.pc := ex_reg_pc v.mem.frs1 := io.fpu.store_data v.killm := killm_common v.status := csr.io.status } io.dmem.req.valid := ex_reg_valid && ex_ctrl.mem val ex_dcache_tag = Cat(ex_waddr, ex_ctrl.fp) require(coreParams.dcacheReqTagBits >= ex_dcache_tag.getWidth) io.dmem.req.bits.tag := ex_dcache_tag io.dmem.req.bits.cmd := ex_ctrl.mem_cmd io.dmem.req.bits.size := ex_reg_mem_size io.dmem.req.bits.signed := !Mux(ex_reg_hls, ex_reg_inst(20), ex_reg_inst(14)) io.dmem.req.bits.phys := false.B io.dmem.req.bits.addr := encodeVirtualAddress(ex_rs(0), alu.io.adder_out) io.dmem.req.bits.idx.foreach(_ := io.dmem.req.bits.addr) io.dmem.req.bits.dprv := Mux(ex_reg_hls, csr.io.hstatus.spvp, csr.io.status.dprv) io.dmem.req.bits.dv := ex_reg_hls \|\| csr.io.status.dv io.dmem.req.bits.no_resp := !isRead(ex_ctrl.mem_cmd) \|\| (!ex_ctrl.fp && ex_waddr === 0.U) io.dmem.req.bits.no_alloc := DontCare io.dmem.req.bits.no_xcpt := DontCare io.dmem.req.bits.data := DontCare io.dmem.req.bits.mask := DontCare io.dmem.s1_data.data := (if (fLen == 0) mem_reg_rs2 else Mux(mem_ctrl.fp, Fill(coreDataBits / fLen, io.fpu.store_data), mem_reg_rs2)) io.dmem.s1_data.mask := DontCare io.dmem.s1_kill := killm_common \|\| mem_ldst_xcpt \|\| fpu_kill_mem \|\| vec_kill_mem io.dmem.s2_kill := false.B // don't let D$ go to sleep if we're probably going to use it soon io.dmem.keep_clock_enabled := ibuf.io.inst(0).valid && id_ctrl.mem && !csr.io.csr_stall io.rocc.cmd.valid := wb_reg_valid && wb_ctrl.rocc && !replay_wb_common io.rocc.exception := wb_xcpt && csr.io.status.xs.orR io.rocc.cmd.bits.status := csr.io.status io.rocc.cmd.bits.inst := wb_reg_inst.asTypeOf(new RoCCInstruction()) io.rocc.cmd.bits.rs1 := wb_reg_wdata io.rocc.cmd.bits.rs2 := wb_reg_rs2 // gate the clock val unpause = csr.io.time(rocketParams.lgPauseCycles-1, 0) === 0.U \|\| csr.io.inhibit_cycle \|\| io.dmem.perf.release \|\| take_pc when (unpause) { id_reg_pause := false.B } io.cease := csr.io.status.cease && !clock_en_reg io.wfi := csr.io.status.wfi if (rocketParams.clockGate) { long_latency_stall := csr.io.csr_stall \|\| io.dmem.perf.blocked \|\| id_reg_pause && !unpause clock_en := clock_en_reg \|\| ex_pc_valid \|\| (!long_latency_stall && io.imem.resp.valid) clock_en_reg := ex_pc_valid \|\| mem_pc_valid \|\| wb_pc_valid \|\| // instruction in flight io.ptw.customCSRs.disableCoreClockGate \|\| // chicken bit !div.io.req.ready \|\| // mul/div in flight usingFPU.B && !io.fpu.fcsr_rdy \|\| // long-latency FPU in flight io.dmem.replay_next \|\| // long-latency load replaying (!long_latency_stall && (ibuf.io.inst(0).valid \|\| io.imem.resp.valid)) // instruction pending assert(!(ex_pc_valid \|\| mem_pc_valid \|\| wb_pc_valid) \|\| clock_en) } // evaluate performance counters val icache_blocked = !(io.imem.resp.valid \|\| RegNext(io.imem.resp.valid)) csr.io.counters foreach { c => c.inc := RegNext(perfEvents.evaluate(c.eventSel)) } val coreMonitorBundle = Wire(new CoreMonitorBundle(xLen, fLen)) coreMonitorBundle.clock := clock coreMonitorBundle.reset := reset coreMonitorBundle.hartid := io.hartid coreMonitorBundle.timer := csr.io.time(31,0) coreMonitorBundle.valid := csr.io.trace(0).valid && !csr.io.trace(0).exception coreMonitorBundle.pc := csr.io.trace(0).iaddr(vaddrBitsExtended-1, 0).sextTo(xLen) coreMonitorBundle.wrenx := wb_wen && !wb_set_sboard coreMonitorBundle.wrenf := false.B coreMonitorBundle.wrdst := wb_waddr coreMonitorBundle.wrdata := rf_wdata coreMonitorBundle.rd0src := wb_reg_inst(19,15) coreMonitorBundle.rd0val := RegNext(RegNext(ex_rs(0))) coreMonitorBundle.rd1src := wb_reg_inst(24,20) coreMonitorBundle.rd1val := RegNext(RegNext(ex_rs(1))) coreMonitorBundle.inst := csr.io.trace(0).insn coreMonitorBundle.excpt := csr.io.trace(0).exception coreMonitorBundle.priv_mode := csr.io.trace(0).priv if (enableCommitLog) { val t = csr.io.trace(0) val rd = wb_waddr val wfd = wb_ctrl.wfd val wxd = wb_ctrl.wxd val has_data = wb_wen && !wb_set_sboard when (t.valid && !t.exception) { when (wfd) { printf ("%d 0x%x (0x%x) f%d p%d 0xXXXXXXXXXXXXXXXX\n", t.priv, t.iaddr, t.insn, rd, rd+32.U) } .elsewhen (wxd && rd =/= 0.U && has_data) { printf ("%d 0x%x (0x%x) x%d 0x%x\n", t.priv, t.iaddr, t.insn, rd, rf_wdata) } .elsewhen (wxd && rd =/= 0.U && !has_data) { printf ("%d 0x%x (0x%x) x%d p%d 0xXXXXXXXXXXXXXXXX\n", t.priv, t.iaddr, t.insn, rd, rd) } .otherwise { printf ("%d 0x%x (0x%x)\n", t.priv, t.iaddr, t.insn) } } when (ll_wen && rf_waddr =/= 0.U) { printf ("x%d p%d 0x%x\n", rf_waddr, rf_waddr, rf_wdata) } } else { when (csr.io.trace(0).valid) { printf("C%d: %d [%d] pc=[%x] W[r%d=%x][%d] R[r%d=%x] R[r%d=%x] inst=[%x] DASM(%x)\n", io.hartid, coreMonitorBundle.timer, coreMonitorBundle.valid, coreMonitorBundle.pc, Mux(wb_ctrl.wxd \|\| wb_ctrl.wfd, coreMonitorBundle.wrdst, 0.U), Mux(coreMonitorBundle.wrenx, coreMonitorBundle.wrdata, 0.U), coreMonitorBundle.wrenx, Mux(wb_ctrl.rxs1 \|\| wb_ctrl.rfs1, coreMonitorBundle.rd0src, 0.U), Mux(wb_ctrl.rxs1 \|\| wb_ctrl.rfs1, coreMonitorBundle.rd0val, 0.U), Mux(wb_ctrl.rxs2 \|\| wb_ctrl.rfs2, coreMonitorBundle.rd1src, 0.U), Mux(wb_ctrl.rxs2 \|\| wb_ctrl.rfs2, coreMonitorBundle.rd1val, 0.U), coreMonitorBundle.inst, coreMonitorBundle.inst) } } // CoreMonitorBundle for late latency writes val xrfWriteBundle = Wire(new CoreMonitorBundle(xLen, fLen)) xrfWriteBundle.clock := clock xrfWriteBundle.reset := reset xrfWriteBundle.hartid := io.hartid xrfWriteBundle.timer := csr.io.time(31,0) xrfWriteBundle.valid := false.B xrfWriteBundle.pc := 0.U xrfWriteBundle.wrdst := rf_waddr xrfWriteBundle.wrenx := rf_wen && !(csr.io.trace(0).valid && wb_wen && (wb_waddr === rf_waddr)) xrfWriteBundle.wrenf := false.B xrfWriteBundle.wrdata := rf_wdata xrfWriteBundle.rd0src := 0.U xrfWriteBundle.rd0val := 0.U xrfWriteBundle.rd1src := 0.U xrfWriteBundle.rd1val := 0.U xrfWriteBundle.inst := 0.U xrfWriteBundle.excpt := false.B xrfWriteBundle.priv_mode := csr.io.trace(0).priv if (rocketParams.haveSimTimeout) PlusArg.timeout( name = "max_core_cycles", docstring = "Kill the emulation after INT rdtime cycles. Off if 0." )(csr.io.time) } // leaving gated-clock domain val rocketImpl = withClock (gated_clock) { new RocketImpl } def checkExceptions(x: Seq[(Bool, UInt)]) = (WireInit(x.map(_._1).reduce(_\|\|_)), WireInit(PriorityMux(x))) def coverExceptions(exceptionValid: Bool, cause: UInt, labelPrefix: String, coverCausesLabels: Seq[(Int, String)]): Unit = { for ((coverCause, label) <- coverCausesLabels) { property.cover(exceptionValid && (cause === coverCause.U), s"${labelPrefix}_${label}") } } def checkHazards(targets: Seq[(Bool, UInt)], cond: UInt => Bool) = targets.map(h => h._1 && cond(h._2)).reduce(_\|\|_) def encodeVirtualAddress(a0: UInt, ea: UInt) = if (vaddrBitsExtended == vaddrBits) ea else { // efficient means to compress 64-bit VA into vaddrBits+1 bits // (VA is bad if VA(vaddrBits) != VA(vaddrBits-1)) val b = vaddrBitsExtended-1 val a = (a0 >> b).asSInt val msb = Mux(a === 0.S \|\| a === -1.S, ea(b), !ea(b-1)) Cat(msb, ea(b-1, 0)) } class Scoreboard(n: Int, zero: Boolean = false) { def set(en: Bool, addr: UInt): Unit = update(en, _next \| mask(en, addr)) def clear(en: Bool, addr: UInt): Unit = update(en, _next & ~mask(en, addr)) def read(addr: UInt): Bool = r(addr) def readBypassed(addr: UInt): Bool = _next(addr) private val _r = RegInit(0.U(n.W)) private val r = if (zero) (_r >> 1 << 1) else _r private var _next = r private var ens = false.B private def mask(en: Bool, addr: UInt) = Mux(en, 1.U << addr, 0.U) private def update(en: Bool, update: UInt) = { _next = update ens = ens \|\| en when (ens) { _r := _next } } } } class RegFile(n: Int, w: Int, zero: Boolean = false) { val rf = Mem(n, UInt(w.W)) private def access(addr: UInt) = rf(~addr(log2Up(n)-1,0)) private val reads = ArrayBuffer[(UInt,UInt)]() private var canRead = true def read(addr: UInt) = { require(canRead) reads += addr -> Wire(UInt()) reads.last._2 := Mux(zero.B && addr === 0.U, 0.U, access(addr)) reads.last._2 } def write(addr: UInt, data: UInt) = { canRead = false when (addr =/= 0.U) { access(addr) := data for ((raddr, rdata) <- reads) when (addr === raddr) { rdata := data } } } } object ImmGen { def apply(sel: UInt, inst: UInt) = { val sign = Mux(sel === IMM_Z, 0.S, inst(31).asSInt) val b30_20 = Mux(sel === IMM_U, inst(30,20).asSInt, sign) val b19_12 = Mux(sel =/= IMM_U && sel =/= IMM_UJ, sign, inst(19,12).asSInt) val b11 = Mux(sel === IMM_U \|\| sel === IMM_Z, 0.S, Mux(sel === IMM_UJ, inst(20).asSInt, Mux(sel === IMM_SB, inst(7).asSInt, sign))) val b10_5 = Mux(sel === IMM_U \|\| sel === IMM_Z, 0.U, inst(30,25)) val b4_1 = Mux(sel === IMM_U, 0.U, Mux(sel === IMM_S \|\| sel === IMM_SB, inst(11,8), Mux(sel === IMM_Z, inst(19,16), inst(24,21)))) val b0 = Mux(sel === IMM_S, inst(7), Mux(sel === IMM_I, inst(20), Mux(sel === IMM_Z, inst(15), 0.U))) Cat(sign, b30_20, b19_12, b11, b10_5, b4_1, b0).asSInt } }	module Rocket( // @[RocketCore.scala:153:7] input clock, // @[RocketCore.scala:153:7] input reset, // @[RocketCore.scala:153:7] input [1:0] io_hartid, // @[RocketCore.scala:134:14] input io_interrupts_debug, // @[RocketCore.scala:134:14] input io_interrupts_mtip, // @[RocketCore.scala:134:14] input io_interrupts_msip, // @[RocketCore.scala:134:14] input io_interrupts_meip, // @[RocketCore.scala:134:14] input io_interrupts_seip, // @[RocketCore.scala:134:14] output io_imem_might_request, // @[RocketCore.scala:134:14] output io_imem_req_valid, // @[RocketCore.scala:134:14] output [39:0] io_imem_req_bits_pc, // @[RocketCore.scala:134:14] output io_imem_req_bits_speculative, // @[RocketCore.scala:134:14] output io_imem_sfence_valid, // @[RocketCore.scala:134:14] output io_imem_sfence_bits_rs1, // @[RocketCore.scala:134:14] output io_imem_sfence_bits_rs2, // @[RocketCore.scala:134:14] output [38:0] io_imem_sfence_bits_addr, // @[RocketCore.scala:134:14] output io_imem_resp_ready, // @[RocketCore.scala:134:14] input io_imem_resp_valid, // @[RocketCore.scala:134:14] input io_imem_resp_bits_btb_taken, // @[RocketCore.scala:134:14] input io_imem_resp_bits_btb_bridx, // @[RocketCore.scala:134:14] input [4:0] io_imem_resp_bits_btb_entry, // @[RocketCore.scala:134:14] input [7:0] io_imem_resp_bits_btb_bht_history, // @[RocketCore.scala:134:14] input [39:0] io_imem_resp_bits_pc, // @[RocketCore.scala:134:14] input [31:0] io_imem_resp_bits_data, // @[RocketCore.scala:134:14] input io_imem_resp_bits_xcpt_pf_inst, // @[RocketCore.scala:134:14] input io_imem_resp_bits_xcpt_gf_inst, // @[RocketCore.scala:134:14] input io_imem_resp_bits_xcpt_ae_inst, // @[RocketCore.scala:134:14] input io_imem_resp_bits_replay, // @[RocketCore.scala:134:14] output io_imem_btb_update_valid, // @[RocketCore.scala:134:14] output [4:0] io_imem_btb_update_bits_prediction_entry, // @[RocketCore.scala:134:14] output [38:0] io_imem_btb_update_bits_pc, // @[RocketCore.scala:134:14] output io_imem_btb_update_bits_isValid, // @[RocketCore.scala:134:14] output [38:0] io_imem_btb_update_bits_br_pc, // @[RocketCore.scala:134:14] output [1:0] io_imem_btb_update_bits_cfiType, // @[RocketCore.scala:134:14] output io_imem_bht_update_valid, // @[RocketCore.scala:134:14] output [7:0] io_imem_bht_update_bits_prediction_history, // @[RocketCore.scala:134:14] output [38:0] io_imem_bht_update_bits_pc, // @[RocketCore.scala:134:14] output io_imem_bht_update_bits_branch, // @[RocketCore.scala:134:14] output io_imem_bht_update_bits_taken, // @[RocketCore.scala:134:14] output io_imem_bht_update_bits_mispredict, // @[RocketCore.scala:134:14] output io_imem_flush_icache, // @[RocketCore.scala:134:14] output io_imem_progress, // @[RocketCore.scala:134:14] input io_dmem_req_ready, // @[RocketCore.scala:134:14] output io_dmem_req_valid, // @[RocketCore.scala:134:14] output [39:0] io_dmem_req_bits_addr, // @[RocketCore.scala:134:14] output [6:0] io_dmem_req_bits_tag, // @[RocketCore.scala:134:14] output [4:0] io_dmem_req_bits_cmd, // @[RocketCore.scala:134:14] output [1:0] io_dmem_req_bits_size, // @[RocketCore.scala:134:14] output io_dmem_req_bits_signed, // @[RocketCore.scala:134:14] output [1:0] io_dmem_req_bits_dprv, // @[RocketCore.scala:134:14] output io_dmem_req_bits_dv, // @[RocketCore.scala:134:14] output io_dmem_s1_kill, // @[RocketCore.scala:134:14] output [63:0] io_dmem_s1_data_data, // @[RocketCore.scala:134:14] input io_dmem_s2_nack, // @[RocketCore.scala:134:14] input io_dmem_resp_valid, // @[RocketCore.scala:134:14] input [6:0] io_dmem_resp_bits_tag, // @[RocketCore.scala:134:14] input [1:0] io_dmem_resp_bits_size, // @[RocketCore.scala:134:14] input [63:0] io_dmem_resp_bits_data, // @[RocketCore.scala:134:14] input io_dmem_resp_bits_replay, // @[RocketCore.scala:134:14] input io_dmem_resp_bits_has_data, // @[RocketCore.scala:134:14] input [63:0] io_dmem_resp_bits_data_word_bypass, // @[RocketCore.scala:134:14] input io_dmem_replay_next, // @[RocketCore.scala:134:14] input io_dmem_s2_xcpt_ma_ld, // @[RocketCore.scala:134:14] input io_dmem_s2_xcpt_ma_st, // @[RocketCore.scala:134:14] input io_dmem_s2_xcpt_pf_ld, // @[RocketCore.scala:134:14] input io_dmem_s2_xcpt_pf_st, // @[RocketCore.scala:134:14] input io_dmem_s2_xcpt_ae_ld, // @[RocketCore.scala:134:14] input io_dmem_s2_xcpt_ae_st, // @[RocketCore.scala:134:14] input io_dmem_ordered, // @[RocketCore.scala:134:14] input io_dmem_perf_release, // @[RocketCore.scala:134:14] input io_dmem_perf_grant, // @[RocketCore.scala:134:14] output [3:0] io_ptw_ptbr_mode, // @[RocketCore.scala:134:14] output [43:0] io_ptw_ptbr_ppn, // @[RocketCore.scala:134:14] output io_ptw_sfence_valid, // @[RocketCore.scala:134:14] output io_ptw_sfence_bits_rs1, // @[RocketCore.scala:134:14] output io_ptw_status_debug, // @[RocketCore.scala:134:14] output [1:0] io_ptw_status_prv, // @[RocketCore.scala:134:14] output io_ptw_status_mxr, // @[RocketCore.scala:134:14] output io_ptw_status_sum, // @[RocketCore.scala:134:14] output io_ptw_pmp_0_cfg_l, // @[RocketCore.scala:134:14] output [1:0] io_ptw_pmp_0_cfg_a, // @[RocketCore.scala:134:14] output io_ptw_pmp_0_cfg_x, // @[RocketCore.scala:134:14] output io_ptw_pmp_0_cfg_w, // @[RocketCore.scala:134:14] output io_ptw_pmp_0_cfg_r, // @[RocketCore.scala:134:14] output [29:0] io_ptw_pmp_0_addr, // @[RocketCore.scala:134:14] output [31:0] io_ptw_pmp_0_mask, // @[RocketCore.scala:134:14] output io_ptw_pmp_1_cfg_l, // @[RocketCore.scala:134:14] output [1:0] io_ptw_pmp_1_cfg_a, // @[RocketCore.scala:134:14] output io_ptw_pmp_1_cfg_x, // @[RocketCore.scala:134:14] output io_ptw_pmp_1_cfg_w, // @[RocketCore.scala:134:14] output io_ptw_pmp_1_cfg_r, // @[RocketCore.scala:134:14] output [29:0] io_ptw_pmp_1_addr, // @[RocketCore.scala:134:14] output [31:0] io_ptw_pmp_1_mask, // @[RocketCore.scala:134:14] output io_ptw_pmp_2_cfg_l, // @[RocketCore.scala:134:14] output [1:0] io_ptw_pmp_2_cfg_a, // @[RocketCore.scala:134:14] output io_ptw_pmp_2_cfg_x, // @[RocketCore.scala:134:14] output io_ptw_pmp_2_cfg_w, // @[RocketCore.scala:134:14] output io_ptw_pmp_2_cfg_r, // @[RocketCore.scala:134:14] output [29:0] io_ptw_pmp_2_addr, // @[RocketCore.scala:134:14] output [31:0] io_ptw_pmp_2_mask, // @[RocketCore.scala:134:14] output io_ptw_pmp_3_cfg_l, // @[RocketCore.scala:134:14] output [1:0] io_ptw_pmp_3_cfg_a, // @[RocketCore.scala:134:14] output io_ptw_pmp_3_cfg_x, // @[RocketCore.scala:134:14] output io_ptw_pmp_3_cfg_w, // @[RocketCore.scala:134:14] output io_ptw_pmp_3_cfg_r, // @[RocketCore.scala:134:14] output [29:0] io_ptw_pmp_3_addr, // @[RocketCore.scala:134:14] output [31:0] io_ptw_pmp_3_mask, // @[RocketCore.scala:134:14] output io_ptw_pmp_4_cfg_l, // @[RocketCore.scala:134:14] output [1:0] io_ptw_pmp_4_cfg_a, // @[RocketCore.scala:134:14] output io_ptw_pmp_4_cfg_x, // @[RocketCore.scala:134:14] output io_ptw_pmp_4_cfg_w, // @[RocketCore.scala:134:14] output io_ptw_pmp_4_cfg_r, // @[RocketCore.scala:134:14] output [29:0] io_ptw_pmp_4_addr, // @[RocketCore.scala:134:14] output [31:0] io_ptw_pmp_4_mask, // @[RocketCore.scala:134:14] output io_ptw_pmp_5_cfg_l, // @[RocketCore.scala:134:14] output [1:0] io_ptw_pmp_5_cfg_a, // @[RocketCore.scala:134:14] output io_ptw_pmp_5_cfg_x, // @[RocketCore.scala:134:14] output io_ptw_pmp_5_cfg_w, // @[RocketCore.scala:134:14] output io_ptw_pmp_5_cfg_r, // @[RocketCore.scala:134:14] output [29:0] io_ptw_pmp_5_addr, // @[RocketCore.scala:134:14] output [31:0] io_ptw_pmp_5_mask, // @[RocketCore.scala:134:14] output io_ptw_pmp_6_cfg_l, // @[RocketCore.scala:134:14] output [1:0] io_ptw_pmp_6_cfg_a, // @[RocketCore.scala:134:14] output io_ptw_pmp_6_cfg_x, // @[RocketCore.scala:134:14] output io_ptw_pmp_6_cfg_w, // @[RocketCore.scala:134:14] output io_ptw_pmp_6_cfg_r, // @[RocketCore.scala:134:14] output [29:0] io_ptw_pmp_6_addr, // @[RocketCore.scala:134:14] output [31:0] io_ptw_pmp_6_mask, // @[RocketCore.scala:134:14] output io_ptw_pmp_7_cfg_l, // @[RocketCore.scala:134:14] output [1:0] io_ptw_pmp_7_cfg_a, // @[RocketCore.scala:134:14] output io_ptw_pmp_7_cfg_x, // @[RocketCore.scala:134:14] output io_ptw_pmp_7_cfg_w, // @[RocketCore.scala:134:14] output io_ptw_pmp_7_cfg_r, // @[RocketCore.scala:134:14] output [29:0] io_ptw_pmp_7_addr, // @[RocketCore.scala:134:14] output [31:0] io_ptw_pmp_7_mask, // @[RocketCore.scala:134:14] output [63:0] io_ptw_customCSRs_csrs_0_value, // @[RocketCore.scala:134:14] output [31:0] io_fpu_inst, // @[RocketCore.scala:134:14] output [63:0] io_fpu_fromint_data, // @[RocketCore.scala:134:14] output [2:0] io_fpu_fcsr_rm, // @[RocketCore.scala:134:14] input io_fpu_fcsr_flags_valid, // @[RocketCore.scala:134:14] input [4:0] io_fpu_fcsr_flags_bits, // @[RocketCore.scala:134:14] input [63:0] io_fpu_store_data, // @[RocketCore.scala:134:14] input [63:0] io_fpu_toint_data, // @[RocketCore.scala:134:14] output io_fpu_ll_resp_val, // @[RocketCore.scala:134:14] output [2:0] io_fpu_ll_resp_type, // @[RocketCore.scala:134:14] output [4:0] io_fpu_ll_resp_tag, // @[RocketCore.scala:134:14] output [63:0] io_fpu_ll_resp_data, // @[RocketCore.scala:134:14] output io_fpu_valid, // @[RocketCore.scala:134:14] input io_fpu_fcsr_rdy, // @[RocketCore.scala:134:14] input io_fpu_nack_mem, // @[RocketCore.scala:134:14] input io_fpu_illegal_rm, // @[RocketCore.scala:134:14] output io_fpu_killx, // @[RocketCore.scala:134:14] output io_fpu_killm, // @[RocketCore.scala:134:14] input io_fpu_dec_wen, // @[RocketCore.scala:134:14] input io_fpu_dec_ren1, // @[RocketCore.scala:134:14] input io_fpu_dec_ren2, // @[RocketCore.scala:134:14] input io_fpu_dec_ren3, // @[RocketCore.scala:134:14] input io_fpu_sboard_set, // @[RocketCore.scala:134:14] input io_fpu_sboard_clr, // @[RocketCore.scala:134:14] input [4:0] io_fpu_sboard_clra, // @[RocketCore.scala:134:14] output io_wfi // @[RocketCore.scala:134:14] ); wire io_dmem_req_valid_0; // @[RocketCore.scala:1130:41] wire ll_arb_io_out_ready; // @[RocketCore.scala:782:23, :809:44, :810:25] wire take_pc_wb; // @[RocketCore.scala:762:{27,38,53}] wire take_pc_mem; // @[RocketCore.scala:629:{32,49}] wire _ll_arb_io_in_0_ready; // @[RocketCore.scala:776:22] wire _ll_arb_io_out_valid; // @[RocketCore.scala:776:22] wire [63:0] _ll_arb_io_out_bits_data; // @[RocketCore.scala:776:22] wire [4:0] _ll_arb_io_out_bits_tag; // @[RocketCore.scala:776:22] wire _div_io_req_ready; // @[RocketCore.scala:511:19] wire _div_io_resp_valid; // @[RocketCore.scala:511:19] wire [63:0] _div_io_resp_bits_data; // @[RocketCore.scala:511:19] wire [4:0] _div_io_resp_bits_tag; // @[RocketCore.scala:511:19] wire [63:0] _alu_io_out; // @[RocketCore.scala:504:19] wire [63:0] _alu_io_adder_out; // @[RocketCore.scala:504:19] wire _alu_io_cmp_out; // @[RocketCore.scala:504:19] wire _bpu_io_xcpt_if; // @[RocketCore.scala:414:19] wire _bpu_io_xcpt_ld; // @[RocketCore.scala:414:19] wire _bpu_io_xcpt_st; // @[RocketCore.scala:414:19] wire _bpu_io_debug_if; // @[RocketCore.scala:414:19] wire _bpu_io_debug_ld; // @[RocketCore.scala:414:19] wire _bpu_io_debug_st; // @[RocketCore.scala:414:19] wire [63:0] _csr_io_rw_rdata; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_fp_illegal; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_fp_csr; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_read_illegal; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_write_illegal; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_write_flush; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_system_illegal; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_virtual_access_illegal; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_virtual_system_illegal; // @[RocketCore.scala:341:19] wire _csr_io_csr_stall; // @[RocketCore.scala:341:19] wire _csr_io_eret; // @[RocketCore.scala:341:19] wire _csr_io_singleStep; // @[RocketCore.scala:341:19] wire _csr_io_status_debug; // @[RocketCore.scala:341:19] wire [31:0] _csr_io_status_isa; // @[RocketCore.scala:341:19] wire _csr_io_status_dv; // @[RocketCore.scala:341:19] wire [1:0] _csr_io_status_prv; // @[RocketCore.scala:341:19] wire _csr_io_status_v; // @[RocketCore.scala:341:19] wire [39:0] _csr_io_evec; // @[RocketCore.scala:341:19] wire [63:0] _csr_io_time; // @[RocketCore.scala:341:19] wire _csr_io_interrupt; // @[RocketCore.scala:341:19] wire [63:0] _csr_io_interrupt_cause; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_control_action; // @[RocketCore.scala:341:19] wire [1:0] _csr_io_bp_0_control_tmatch; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_control_m; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_control_s; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_control_u; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_control_x; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_control_w; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_control_r; // @[RocketCore.scala:341:19] wire [38:0] _csr_io_bp_0_address; // @[RocketCore.scala:341:19] wire _csr_io_inhibit_cycle; // @[RocketCore.scala:341:19] wire _csr_io_trace_0_valid; // @[RocketCore.scala:341:19] wire [39:0] _csr_io_trace_0_iaddr; // @[RocketCore.scala:341:19] wire [31:0] _csr_io_trace_0_insn; // @[RocketCore.scala:341:19] wire _csr_io_trace_0_exception; // @[RocketCore.scala:341:19] wire [63:0] _csr_io_customCSRs_0_value; // @[RocketCore.scala:341:19] wire [63:0] _rf_ext_R0_data; // @[RocketCore.scala:1319:15] wire [63:0] _rf_ext_R1_data; // @[RocketCore.scala:1319:15] wire [39:0] _ibuf_io_pc; // @[RocketCore.scala:311:20] wire [4:0] _ibuf_io_btb_resp_entry; // @[RocketCore.scala:311:20] wire [7:0] _ibuf_io_btb_resp_bht_history; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_valid; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_bits_xcpt0_pf_inst; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_bits_xcpt0_gf_inst; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_bits_xcpt0_ae_inst; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_bits_xcpt1_pf_inst; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_bits_xcpt1_gf_inst; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_bits_xcpt1_ae_inst; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_bits_replay; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_bits_rvc; // @[RocketCore.scala:311:20] wire [31:0] _ibuf_io_inst_0_bits_inst_bits; // @[RocketCore.scala:311:20] wire [4:0] _ibuf_io_inst_0_bits_inst_rd; // @[RocketCore.scala:311:20] wire [4:0] _ibuf_io_inst_0_bits_inst_rs1; // @[RocketCore.scala:311:20] wire [4:0] _ibuf_io_inst_0_bits_inst_rs2; // @[RocketCore.scala:311:20] wire [4:0] _ibuf_io_inst_0_bits_inst_rs3; // @[RocketCore.scala:311:20] wire [31:0] _ibuf_io_inst_0_bits_raw; // @[RocketCore.scala:311:20] reg id_reg_pause; // @[RocketCore.scala:161:25] reg imem_might_request_reg; // @[RocketCore.scala:162:35] reg ex_ctrl_fp; // @[RocketCore.scala:243:20] reg ex_ctrl_rocc; // @[RocketCore.scala:243:20] reg ex_ctrl_branch; // @[RocketCore.scala:243:20] reg ex_ctrl_jal; // @[RocketCore.scala:243:20] reg ex_ctrl_jalr; // @[RocketCore.scala:243:20] reg ex_ctrl_rxs2; // @[RocketCore.scala:243:20] reg ex_ctrl_rxs1; // @[RocketCore.scala:243:20] reg [2:0] ex_ctrl_sel_alu2; // @[RocketCore.scala:243:20] reg [1:0] ex_ctrl_sel_alu1; // @[RocketCore.scala:243:20] reg [2:0] ex_ctrl_sel_imm; // @[RocketCore.scala:243:20] reg ex_ctrl_alu_dw; // @[RocketCore.scala:243:20] reg [4:0] ex_ctrl_alu_fn; // @[RocketCore.scala:243:20] reg ex_ctrl_mem; // @[RocketCore.scala:243:20] reg [4:0] ex_ctrl_mem_cmd; // @[RocketCore.scala:243:20] reg ex_ctrl_rfs1; // @[RocketCore.scala:243:20] reg ex_ctrl_rfs2; // @[RocketCore.scala:243:20] reg ex_ctrl_wfd; // @[RocketCore.scala:243:20] reg ex_ctrl_mul; // @[RocketCore.scala:243:20] reg ex_ctrl_div; // @[RocketCore.scala:243:20] reg ex_ctrl_wxd; // @[RocketCore.scala:243:20] reg [2:0] ex_ctrl_csr; // @[RocketCore.scala:243:20] reg ex_ctrl_fence_i; // @[RocketCore.scala:243:20] reg mem_ctrl_fp; // @[RocketCore.scala:244:21] reg mem_ctrl_rocc; // @[RocketCore.scala:244:21] reg mem_ctrl_branch; // @[RocketCore.scala:244:21] reg mem_ctrl_jal; // @[RocketCore.scala:244:21] reg mem_ctrl_jalr; // @[RocketCore.scala:244:21] reg mem_ctrl_rxs2; // @[RocketCore.scala:244:21] reg mem_ctrl_rxs1; // @[RocketCore.scala:244:21] reg mem_ctrl_mem; // @[RocketCore.scala:244:21] reg mem_ctrl_rfs1; // @[RocketCore.scala:244:21] reg mem_ctrl_rfs2; // @[RocketCore.scala:244:21] reg mem_ctrl_wfd; // @[RocketCore.scala:244:21] reg mem_ctrl_mul; // @[RocketCore.scala:244:21] reg mem_ctrl_div; // @[RocketCore.scala:244:21] reg mem_ctrl_wxd; // @[RocketCore.scala:244:21] reg [2:0] mem_ctrl_csr; // @[RocketCore.scala:244:21] reg mem_ctrl_fence_i; // @[RocketCore.scala:244:21] reg mem_ctrl_vec; // @[RocketCore.scala:244:21] reg wb_ctrl_rocc; // @[RocketCore.scala:245:20] reg wb_ctrl_rxs2; // @[RocketCore.scala:245:20] reg wb_ctrl_rxs1; // @[RocketCore.scala:245:20] reg wb_ctrl_mem; // @[RocketCore.scala:245:20] reg wb_ctrl_rfs1; // @[RocketCore.scala:245:20] reg wb_ctrl_rfs2; // @[RocketCore.scala:245:20] reg wb_ctrl_wfd; // @[RocketCore.scala:245:20] reg wb_ctrl_div; // @[RocketCore.scala:245:20] reg wb_ctrl_wxd; // @[RocketCore.scala:245:20] reg [2:0] wb_ctrl_csr; // @[RocketCore.scala:245:20] reg wb_ctrl_fence_i; // @[RocketCore.scala:245:20] reg wb_ctrl_vec; // @[RocketCore.scala:245:20] reg ex_reg_xcpt_interrupt; // @[RocketCore.scala:247:35] reg ex_reg_valid; // @[RocketCore.scala:248:35] reg ex_reg_rvc; // @[RocketCore.scala:249:35] reg [4:0] ex_reg_btb_resp_entry; // @[RocketCore.scala:250:35] reg [7:0] ex_reg_btb_resp_bht_history; // @[RocketCore.scala:250:35] reg ex_reg_xcpt; // @[RocketCore.scala:251:35] reg ex_reg_flush_pipe; // @[RocketCore.scala:252:35] reg ex_reg_load_use; // @[RocketCore.scala:253:35] reg [63:0] ex_reg_cause; // @[RocketCore.scala:254:35] reg ex_reg_replay; // @[RocketCore.scala:255:26] reg [39:0] ex_reg_pc; // @[RocketCore.scala:256:22] reg [1:0] ex_reg_mem_size; // @[RocketCore.scala:257:28] reg [31:0] ex_reg_inst; // @[RocketCore.scala:259:24] reg [31:0] ex_reg_raw_inst; // @[RocketCore.scala:260:28] reg mem_reg_xcpt_interrupt; // @[RocketCore.scala:264:36] reg mem_reg_valid; // @[RocketCore.scala:265:36] reg mem_reg_rvc; // @[RocketCore.scala:266:36] reg [4:0] mem_reg_btb_resp_entry; // @[RocketCore.scala:267:36] reg [7:0] mem_reg_btb_resp_bht_history; // @[RocketCore.scala:267:36] reg mem_reg_xcpt; // @[RocketCore.scala:268:36] reg mem_reg_replay; // @[RocketCore.scala:269:36] reg mem_reg_flush_pipe; // @[RocketCore.scala:270:36] reg [63:0] mem_reg_cause; // @[RocketCore.scala:271:36] reg mem_mem_cmd_bh; // @[RocketCore.scala:272:36] reg mem_reg_load; // @[RocketCore.scala:273:36] reg mem_reg_store; // @[RocketCore.scala:274:36] reg mem_reg_sfence; // @[RocketCore.scala:276:27] reg [39:0] mem_reg_pc; // @[RocketCore.scala:277:23] reg [31:0] mem_reg_inst; // @[RocketCore.scala:278:25] reg [1:0] mem_reg_mem_size; // @[RocketCore.scala:279:29] reg mem_reg_hls_or_dv; // @[RocketCore.scala:280:30] reg [31:0] mem_reg_raw_inst; // @[RocketCore.scala:281:29] reg [63:0] mem_reg_wdata; // @[RocketCore.scala:282:26] reg [63:0] mem_reg_rs2; // @[RocketCore.scala:283:24] reg mem_br_taken; // @[RocketCore.scala:284:25] reg wb_reg_valid; // @[RocketCore.scala:288:35] reg wb_reg_xcpt; // @[RocketCore.scala:289:35] reg wb_reg_replay; // @[RocketCore.scala:290:35] reg wb_reg_flush_pipe; // @[RocketCore.scala:291:35] reg [63:0] wb_reg_cause; // @[RocketCore.scala:292:35] reg wb_reg_sfence; // @[RocketCore.scala:294:26] reg [39:0] wb_reg_pc; // @[RocketCore.scala:295:22] reg [1:0] wb_reg_mem_size; // @[RocketCore.scala:296:28] reg wb_reg_hls_or_dv; // @[RocketCore.scala:297:29] reg [31:0] wb_reg_inst; // @[RocketCore.scala:300:24] reg [31:0] wb_reg_raw_inst; // @[RocketCore.scala:301:28] reg [63:0] wb_reg_wdata; // @[RocketCore.scala:302:25] wire ibuf_io_kill = take_pc_wb \| take_pc_mem; // @[RocketCore.scala:307:35, :629:{32,49}, :762:{27,38,53}] wire [29:0] id_ctrl_decoder_decoded_invInputs = ~(_ibuf_io_inst_0_bits_inst_bits[31:2]); // @[pla.scala:78:21] wire [6:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], id_ctrl_decoder_decoded_invInputs[3], id_ctrl_decoder_decoded_invInputs[4], id_ctrl_decoder_decoded_invInputs[10]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_2 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], id_ctrl_decoder_decoded_invInputs[2], id_ctrl_decoder_decoded_invInputs[3], id_ctrl_decoder_decoded_invInputs[4], id_ctrl_decoder_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [6:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_3 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], id_ctrl_decoder_decoded_invInputs[2], id_ctrl_decoder_decoded_invInputs[4], id_ctrl_decoder_decoded_invInputs[12]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_6 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], id_ctrl_decoder_decoded_invInputs[4], id_ctrl_decoder_decoded_invInputs[10], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [5:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_7 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], _ibuf_io_inst_0_bits_inst_bits[2], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[4]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_9 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], id_ctrl_decoder_decoded_invInputs[2], _ibuf_io_inst_0_bits_inst_bits[5], id_ctrl_decoder_decoded_invInputs[4], id_ctrl_decoder_decoded_invInputs[12]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_12 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], _ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], id_ctrl_decoder_decoded_invInputs[4], id_ctrl_decoder_decoded_invInputs[10], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], id_ctrl_decoder_decoded_invInputs[27], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [12:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_13 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], id_ctrl_decoder_decoded_invInputs[4], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], id_ctrl_decoder_decoded_invInputs[27], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_14 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], _ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], id_ctrl_decoder_decoded_invInputs[4], id_ctrl_decoder_decoded_invInputs[10], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], id_ctrl_decoder_decoded_invInputs[27], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_16 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], _ibuf_io_inst_0_bits_inst_bits[3], _ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], id_ctrl_decoder_decoded_invInputs[4], id_ctrl_decoder_decoded_invInputs[10], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[26], id_ctrl_decoder_decoded_invInputs[27], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [4:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_17 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[2], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [10:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_20 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[27], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [10:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_21 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[27], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_24 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[1], id_ctrl_decoder_decoded_invInputs[2], _ibuf_io_inst_0_bits_inst_bits[5], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[10], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [9:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_25 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], _ibuf_io_inst_0_bits_inst_bits[2], id_ctrl_decoder_decoded_invInputs[1], id_ctrl_decoder_decoded_invInputs[2], _ibuf_io_inst_0_bits_inst_bits[5], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[10], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [6:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_26 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], _ibuf_io_inst_0_bits_inst_bits[2], _ibuf_io_inst_0_bits_inst_bits[3], id_ctrl_decoder_decoded_invInputs[2], _ibuf_io_inst_0_bits_inst_bits[5], _ibuf_io_inst_0_bits_inst_bits[6]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [6:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_29 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[1], id_ctrl_decoder_decoded_invInputs[2], id_ctrl_decoder_decoded_invInputs[4], _ibuf_io_inst_0_bits_inst_bits[12], id_ctrl_decoder_decoded_invInputs[12]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [9:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_33 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], _ibuf_io_inst_0_bits_inst_bits[2], _ibuf_io_inst_0_bits_inst_bits[3], id_ctrl_decoder_decoded_invInputs[2], id_ctrl_decoder_decoded_invInputs[3], id_ctrl_decoder_decoded_invInputs[4], _ibuf_io_inst_0_bits_inst_bits[12], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_34 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[4], _ibuf_io_inst_0_bits_inst_bits[12], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], id_ctrl_decoder_decoded_invInputs[27], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_36 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], _ibuf_io_inst_0_bits_inst_bits[3], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[4], _ibuf_io_inst_0_bits_inst_bits[12], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], id_ctrl_decoder_decoded_invInputs[27], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_42 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[5], _ibuf_io_inst_0_bits_inst_bits[6], _ibuf_io_inst_0_bits_inst_bits[12], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_43 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], _ibuf_io_inst_0_bits_inst_bits[6], _ibuf_io_inst_0_bits_inst_bits[12]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [6:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_44 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[1], id_ctrl_decoder_decoded_invInputs[2], id_ctrl_decoder_decoded_invInputs[4], _ibuf_io_inst_0_bits_inst_bits[13], id_ctrl_decoder_decoded_invInputs[12]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_48 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], id_ctrl_decoder_decoded_invInputs[4], _ibuf_io_inst_0_bits_inst_bits[13]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [10:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_52 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], _ibuf_io_inst_0_bits_inst_bits[2], _ibuf_io_inst_0_bits_inst_bits[3], id_ctrl_decoder_decoded_invInputs[2], _ibuf_io_inst_0_bits_inst_bits[5], id_ctrl_decoder_decoded_invInputs[4], _ibuf_io_inst_0_bits_inst_bits[13], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_55 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], _ibuf_io_inst_0_bits_inst_bits[6], _ibuf_io_inst_0_bits_inst_bits[13]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_56 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], _ibuf_io_inst_0_bits_inst_bits[6], _ibuf_io_inst_0_bits_inst_bits[13], id_ctrl_decoder_decoded_invInputs[12]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_61 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], id_ctrl_decoder_decoded_invInputs[4], _ibuf_io_inst_0_bits_inst_bits[14], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], id_ctrl_decoder_decoded_invInputs[27], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_63 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], id_ctrl_decoder_decoded_invInputs[2], _ibuf_io_inst_0_bits_inst_bits[5], _ibuf_io_inst_0_bits_inst_bits[6], _ibuf_io_inst_0_bits_inst_bits[14]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_84 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], id_ctrl_decoder_decoded_invInputs[4], _ibuf_io_inst_0_bits_inst_bits[14], _ibuf_io_inst_0_bits_inst_bits[25], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[26], id_ctrl_decoder_decoded_invInputs[27], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_85 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], _ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], id_ctrl_decoder_decoded_invInputs[4], _ibuf_io_inst_0_bits_inst_bits[14], _ibuf_io_inst_0_bits_inst_bits[25], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], id_ctrl_decoder_decoded_invInputs[27], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_89 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], _ibuf_io_inst_0_bits_inst_bits[3], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], id_ctrl_decoder_decoded_invInputs[4], _ibuf_io_inst_0_bits_inst_bits[12], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[24], _ibuf_io_inst_0_bits_inst_bits[27], id_ctrl_decoder_decoded_invInputs[26], id_ctrl_decoder_decoded_invInputs[27], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [12:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_90 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], _ibuf_io_inst_0_bits_inst_bits[2], _ibuf_io_inst_0_bits_inst_bits[3], id_ctrl_decoder_decoded_invInputs[2], _ibuf_io_inst_0_bits_inst_bits[5], id_ctrl_decoder_decoded_invInputs[4], _ibuf_io_inst_0_bits_inst_bits[13], id_ctrl_decoder_decoded_invInputs[12], _ibuf_io_inst_0_bits_inst_bits[27], id_ctrl_decoder_decoded_invInputs[27], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [21:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_91 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], _ibuf_io_inst_0_bits_inst_bits[3], _ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], id_ctrl_decoder_decoded_invInputs[4], id_ctrl_decoder_decoded_invInputs[10], id_ctrl_decoder_decoded_invInputs[11], _ibuf_io_inst_0_bits_inst_bits[14], id_ctrl_decoder_decoded_invInputs[18], id_ctrl_decoder_decoded_invInputs[19], id_ctrl_decoder_decoded_invInputs[20], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[24], _ibuf_io_inst_0_bits_inst_bits[27], id_ctrl_decoder_decoded_invInputs[26], id_ctrl_decoder_decoded_invInputs[27], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_95 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], _ibuf_io_inst_0_bits_inst_bits[2], _ibuf_io_inst_0_bits_inst_bits[3], id_ctrl_decoder_decoded_invInputs[2], _ibuf_io_inst_0_bits_inst_bits[5], id_ctrl_decoder_decoded_invInputs[4], id_ctrl_decoder_decoded_invInputs[18], id_ctrl_decoder_decoded_invInputs[19], id_ctrl_decoder_decoded_invInputs[20], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[25], _ibuf_io_inst_0_bits_inst_bits[28], id_ctrl_decoder_decoded_invInputs[27], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [18:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_96 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], _ibuf_io_inst_0_bits_inst_bits[2], _ibuf_io_inst_0_bits_inst_bits[3], id_ctrl_decoder_decoded_invInputs[2], _ibuf_io_inst_0_bits_inst_bits[5], id_ctrl_decoder_decoded_invInputs[4], _ibuf_io_inst_0_bits_inst_bits[13], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[18], id_ctrl_decoder_decoded_invInputs[19], id_ctrl_decoder_decoded_invInputs[20], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[25], _ibuf_io_inst_0_bits_inst_bits[28], id_ctrl_decoder_decoded_invInputs[27], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_101 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[5], id_ctrl_decoder_decoded_invInputs[6], id_ctrl_decoder_decoded_invInputs[7], _ibuf_io_inst_0_bits_inst_bits[25], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], _ibuf_io_inst_0_bits_inst_bits[28], id_ctrl_decoder_decoded_invInputs[27], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [17:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_102 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[5], id_ctrl_decoder_decoded_invInputs[6], id_ctrl_decoder_decoded_invInputs[7], id_ctrl_decoder_decoded_invInputs[12], _ibuf_io_inst_0_bits_inst_bits[25], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], _ibuf_io_inst_0_bits_inst_bits[28], id_ctrl_decoder_decoded_invInputs[27], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [21:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_104 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[5], id_ctrl_decoder_decoded_invInputs[6], id_ctrl_decoder_decoded_invInputs[7], id_ctrl_decoder_decoded_invInputs[8], id_ctrl_decoder_decoded_invInputs[9], id_ctrl_decoder_decoded_invInputs[10], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12], _ibuf_io_inst_0_bits_inst_bits[25], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], _ibuf_io_inst_0_bits_inst_bits[28], id_ctrl_decoder_decoded_invInputs[27], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_106 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[10], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], _ibuf_io_inst_0_bits_inst_bits[29], id_ctrl_decoder_decoded_invInputs[28]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_107 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], _ibuf_io_inst_0_bits_inst_bits[29], id_ctrl_decoder_decoded_invInputs[28]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_108 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[10], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], _ibuf_io_inst_0_bits_inst_bits[29], id_ctrl_decoder_decoded_invInputs[28]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_109 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], _ibuf_io_inst_0_bits_inst_bits[29], id_ctrl_decoder_decoded_invInputs[28]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_110 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[26], _ibuf_io_inst_0_bits_inst_bits[29], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_111 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[26], _ibuf_io_inst_0_bits_inst_bits[29], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_115 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], _ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], id_ctrl_decoder_decoded_invInputs[4], id_ctrl_decoder_decoded_invInputs[10], _ibuf_io_inst_0_bits_inst_bits[13], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], _ibuf_io_inst_0_bits_inst_bits[29], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_116 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], _ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], id_ctrl_decoder_decoded_invInputs[4], id_ctrl_decoder_decoded_invInputs[10], _ibuf_io_inst_0_bits_inst_bits[14], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], _ibuf_io_inst_0_bits_inst_bits[29], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_120 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], id_ctrl_decoder_decoded_invInputs[4], _ibuf_io_inst_0_bits_inst_bits[12], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[24], _ibuf_io_inst_0_bits_inst_bits[27], id_ctrl_decoder_decoded_invInputs[26], _ibuf_io_inst_0_bits_inst_bits[29], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_122 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], id_ctrl_decoder_decoded_invInputs[4], _ibuf_io_inst_0_bits_inst_bits[12], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[24], _ibuf_io_inst_0_bits_inst_bits[27], id_ctrl_decoder_decoded_invInputs[26], _ibuf_io_inst_0_bits_inst_bits[29], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [21:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_124 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], id_ctrl_decoder_decoded_invInputs[4], _ibuf_io_inst_0_bits_inst_bits[12], id_ctrl_decoder_decoded_invInputs[11], _ibuf_io_inst_0_bits_inst_bits[14], _ibuf_io_inst_0_bits_inst_bits[20], _ibuf_io_inst_0_bits_inst_bits[21], _ibuf_io_inst_0_bits_inst_bits[22], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[24], _ibuf_io_inst_0_bits_inst_bits[27], id_ctrl_decoder_decoded_invInputs[26], _ibuf_io_inst_0_bits_inst_bits[29], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_130 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], id_ctrl_decoder_decoded_invInputs[4], _ibuf_io_inst_0_bits_inst_bits[12], id_ctrl_decoder_decoded_invInputs[11], _ibuf_io_inst_0_bits_inst_bits[14], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], _ibuf_io_inst_0_bits_inst_bits[30], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_133 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], _ibuf_io_inst_0_bits_inst_bits[3], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[4], _ibuf_io_inst_0_bits_inst_bits[12], id_ctrl_decoder_decoded_invInputs[11], _ibuf_io_inst_0_bits_inst_bits[14], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], _ibuf_io_inst_0_bits_inst_bits[30], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_140 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], _ibuf_io_inst_0_bits_inst_bits[20], id_ctrl_decoder_decoded_invInputs[19], id_ctrl_decoder_decoded_invInputs[20], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], id_ctrl_decoder_decoded_invInputs[27], _ibuf_io_inst_0_bits_inst_bits[30]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_142 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[18], _ibuf_io_inst_0_bits_inst_bits[21], id_ctrl_decoder_decoded_invInputs[20], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], id_ctrl_decoder_decoded_invInputs[27], _ibuf_io_inst_0_bits_inst_bits[30]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_144 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[18], id_ctrl_decoder_decoded_invInputs[20], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], _ibuf_io_inst_0_bits_inst_bits[25], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], id_ctrl_decoder_decoded_invInputs[27], _ibuf_io_inst_0_bits_inst_bits[30]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_146 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[19], id_ctrl_decoder_decoded_invInputs[20], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[23], _ibuf_io_inst_0_bits_inst_bits[26], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], id_ctrl_decoder_decoded_invInputs[27], _ibuf_io_inst_0_bits_inst_bits[30]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_149 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], id_ctrl_decoder_decoded_invInputs[4], _ibuf_io_inst_0_bits_inst_bits[12], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[24], _ibuf_io_inst_0_bits_inst_bits[27], id_ctrl_decoder_decoded_invInputs[26], id_ctrl_decoder_decoded_invInputs[27], _ibuf_io_inst_0_bits_inst_bits[30], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_152 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], id_ctrl_decoder_decoded_invInputs[4], _ibuf_io_inst_0_bits_inst_bits[12], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[24], _ibuf_io_inst_0_bits_inst_bits[27], id_ctrl_decoder_decoded_invInputs[26], id_ctrl_decoder_decoded_invInputs[27], _ibuf_io_inst_0_bits_inst_bits[30], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [17:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_154 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[18], id_ctrl_decoder_decoded_invInputs[19], id_ctrl_decoder_decoded_invInputs[20], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[23], _ibuf_io_inst_0_bits_inst_bits[27], _ibuf_io_inst_0_bits_inst_bits[28], id_ctrl_decoder_decoded_invInputs[27], _ibuf_io_inst_0_bits_inst_bits[30], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [17:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_155 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[18], id_ctrl_decoder_decoded_invInputs[19], id_ctrl_decoder_decoded_invInputs[20], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[24], _ibuf_io_inst_0_bits_inst_bits[27], _ibuf_io_inst_0_bits_inst_bits[28], id_ctrl_decoder_decoded_invInputs[27], _ibuf_io_inst_0_bits_inst_bits[30], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_157 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], id_ctrl_decoder_decoded_invInputs[4], id_ctrl_decoder_decoded_invInputs[19], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], _ibuf_io_inst_0_bits_inst_bits[29], _ibuf_io_inst_0_bits_inst_bits[30], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_158 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], id_ctrl_decoder_decoded_invInputs[4], id_ctrl_decoder_decoded_invInputs[18], id_ctrl_decoder_decoded_invInputs[20], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], _ibuf_io_inst_0_bits_inst_bits[29], _ibuf_io_inst_0_bits_inst_bits[30], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_159 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], id_ctrl_decoder_decoded_invInputs[4], id_ctrl_decoder_decoded_invInputs[19], id_ctrl_decoder_decoded_invInputs[20], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], _ibuf_io_inst_0_bits_inst_bits[29], _ibuf_io_inst_0_bits_inst_bits[30], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_164 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], _ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], id_ctrl_decoder_decoded_invInputs[4], _ibuf_io_inst_0_bits_inst_bits[12], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], _ibuf_io_inst_0_bits_inst_bits[29], _ibuf_io_inst_0_bits_inst_bits[30], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [21:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_169 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], id_ctrl_decoder_decoded_invInputs[4], _ibuf_io_inst_0_bits_inst_bits[12], id_ctrl_decoder_decoded_invInputs[11], _ibuf_io_inst_0_bits_inst_bits[14], id_ctrl_decoder_decoded_invInputs[18], id_ctrl_decoder_decoded_invInputs[19], id_ctrl_decoder_decoded_invInputs[20], _ibuf_io_inst_0_bits_inst_bits[23], _ibuf_io_inst_0_bits_inst_bits[24], _ibuf_io_inst_0_bits_inst_bits[25], id_ctrl_decoder_decoded_invInputs[24], _ibuf_io_inst_0_bits_inst_bits[27], id_ctrl_decoder_decoded_invInputs[26], _ibuf_io_inst_0_bits_inst_bits[29], _ibuf_io_inst_0_bits_inst_bits[30], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_179 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[20], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[27], _ibuf_io_inst_0_bits_inst_bits[30], _ibuf_io_inst_0_bits_inst_bits[31]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_180 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[20], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[27], _ibuf_io_inst_0_bits_inst_bits[30], _ibuf_io_inst_0_bits_inst_bits[31]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_181 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[20], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], id_ctrl_decoder_decoded_invInputs[27], _ibuf_io_inst_0_bits_inst_bits[30], _ibuf_io_inst_0_bits_inst_bits[31]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_182 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[20], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], id_ctrl_decoder_decoded_invInputs[27], _ibuf_io_inst_0_bits_inst_bits[30], _ibuf_io_inst_0_bits_inst_bits[31]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_184 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[20], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[25], _ibuf_io_inst_0_bits_inst_bits[28], id_ctrl_decoder_decoded_invInputs[27], _ibuf_io_inst_0_bits_inst_bits[30], _ibuf_io_inst_0_bits_inst_bits[31]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_185 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[20], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], _ibuf_io_inst_0_bits_inst_bits[28], id_ctrl_decoder_decoded_invInputs[27], _ibuf_io_inst_0_bits_inst_bits[30], _ibuf_io_inst_0_bits_inst_bits[31]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [19:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_188 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[18], id_ctrl_decoder_decoded_invInputs[19], id_ctrl_decoder_decoded_invInputs[20], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], _ibuf_io_inst_0_bits_inst_bits[29], _ibuf_io_inst_0_bits_inst_bits[30], _ibuf_io_inst_0_bits_inst_bits[31]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [19:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_189 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[18], id_ctrl_decoder_decoded_invInputs[19], id_ctrl_decoder_decoded_invInputs[20], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], _ibuf_io_inst_0_bits_inst_bits[29], _ibuf_io_inst_0_bits_inst_bits[30], _ibuf_io_inst_0_bits_inst_bits[31]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [20:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_192 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[10], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[18], id_ctrl_decoder_decoded_invInputs[19], id_ctrl_decoder_decoded_invInputs[20], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[25], _ibuf_io_inst_0_bits_inst_bits[28], _ibuf_io_inst_0_bits_inst_bits[29], _ibuf_io_inst_0_bits_inst_bits[30], _ibuf_io_inst_0_bits_inst_bits[31]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [20:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_193 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[10], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[18], id_ctrl_decoder_decoded_invInputs[19], id_ctrl_decoder_decoded_invInputs[20], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], _ibuf_io_inst_0_bits_inst_bits[28], _ibuf_io_inst_0_bits_inst_bits[29], _ibuf_io_inst_0_bits_inst_bits[30], _ibuf_io_inst_0_bits_inst_bits[31]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [2:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_2 = {&_id_ctrl_decoder_decoded_andMatrixOutputs_T_52, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_90, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_95}; // @[pla.scala:98:{53,70}, :114:19] wire [45:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_10 = {&_id_ctrl_decoder_decoded_andMatrixOutputs_T, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_2, &{_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], id_ctrl_decoder_decoded_invInputs[2], id_ctrl_decoder_decoded_invInputs[3], id_ctrl_decoder_decoded_invInputs[4], id_ctrl_decoder_decoded_invInputs[12]}, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_6, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_7, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_12, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_13, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_14, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_16, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_25, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_26, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_34, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_36, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_43, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_48, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_52, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_55, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_61, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_84, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_85, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_89, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_90, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_91, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_95, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_115, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_116, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_120, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_122, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_124, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_130, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_133, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_149, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_152, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_157, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_158, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_159, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_164, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_169, &{_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[10], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], _ibuf_io_inst_0_bits_inst_bits[29], id_ctrl_decoder_decoded_invInputs[28], _ibuf_io_inst_0_bits_inst_bits[31]}, &{_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], _ibuf_io_inst_0_bits_inst_bits[29], id_ctrl_decoder_decoded_invInputs[28], _ibuf_io_inst_0_bits_inst_bits[31]}, &{_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[10], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], _ibuf_io_inst_0_bits_inst_bits[29], id_ctrl_decoder_decoded_invInputs[28], _ibuf_io_inst_0_bits_inst_bits[31]}, &{_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], _ibuf_io_inst_0_bits_inst_bits[29], id_ctrl_decoder_decoded_invInputs[28], _ibuf_io_inst_0_bits_inst_bits[31]}, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_181, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_182, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_188, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_189}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:19] wire [2:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_12 = {&{_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], id_ctrl_decoder_decoded_invInputs[4], _ibuf_io_inst_0_bits_inst_bits[25], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], id_ctrl_decoder_decoded_invInputs[27], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}, &{_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], _ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], id_ctrl_decoder_decoded_invInputs[4], id_ctrl_decoder_decoded_invInputs[10], id_ctrl_decoder_decoded_invInputs[11], _ibuf_io_inst_0_bits_inst_bits[25], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], id_ctrl_decoder_decoded_invInputs[27], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_85}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:19] wire [8:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_29 = {&{_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], id_ctrl_decoder_decoded_invInputs[2], id_ctrl_decoder_decoded_invInputs[3], id_ctrl_decoder_decoded_invInputs[4], id_ctrl_decoder_decoded_invInputs[10]}, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_2, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_3, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_29, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_44, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_52, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_90, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_96, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_104}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:19] wire [43:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_59 = {&_id_ctrl_decoder_decoded_andMatrixOutputs_T, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_2, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_3, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_6, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_12, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_13, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_14, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_16, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_24, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_29, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_34, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_36, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_42, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_44, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_48, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_52, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_56, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_61, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_63, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_84, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_85, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_89, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_90, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_91, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_95, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_102, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_115, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_116, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_120, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_122, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_124, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_130, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_133, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_149, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_152, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_157, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_158, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_159, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_164, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_169, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_184, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_185, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_192, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_193}; // @[pla.scala:98:{53,70}, :114:19] wire [21:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_61 = {&_id_ctrl_decoder_decoded_andMatrixOutputs_T_9, &{_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], id_ctrl_decoder_decoded_invInputs[2], _ibuf_io_inst_0_bits_inst_bits[5], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12]}, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_12, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_13, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_14, &{_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], _ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], id_ctrl_decoder_decoded_invInputs[4], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], id_ctrl_decoder_decoded_invInputs[27], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_16, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_52, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_61, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_63, &{_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], _ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], id_ctrl_decoder_decoded_invInputs[4], _ibuf_io_inst_0_bits_inst_bits[12], id_ctrl_decoder_decoded_invInputs[11], _ibuf_io_inst_0_bits_inst_bits[14], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], id_ctrl_decoder_decoded_invInputs[27], id_ctrl_decoder_decoded_invInputs[29]}, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_84, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_85, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_89, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_90, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_95, &{_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[5], id_ctrl_decoder_decoded_invInputs[6], id_ctrl_decoder_decoded_invInputs[7], id_ctrl_decoder_decoded_invInputs[10], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12], _ibuf_io_inst_0_bits_inst_bits[25], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], _ibuf_io_inst_0_bits_inst_bits[28], id_ctrl_decoder_decoded_invInputs[27], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_115, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_116, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_122, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_152, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_164}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:19] wire [20:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_67 = {&_id_ctrl_decoder_decoded_andMatrixOutputs_T_17, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_20, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_21, &{_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], _ibuf_io_inst_0_bits_inst_bits[2], id_ctrl_decoder_decoded_invInputs[1], id_ctrl_decoder_decoded_invInputs[2], id_ctrl_decoder_decoded_invInputs[4], _ibuf_io_inst_0_bits_inst_bits[12], id_ctrl_decoder_decoded_invInputs[12]}, &{_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], _ibuf_io_inst_0_bits_inst_bits[2], id_ctrl_decoder_decoded_invInputs[1], id_ctrl_decoder_decoded_invInputs[2], id_ctrl_decoder_decoded_invInputs[4], _ibuf_io_inst_0_bits_inst_bits[13], id_ctrl_decoder_decoded_invInputs[12]}, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_106, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_107, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_108, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_109, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_110, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_111, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_140, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_142, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_144, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_146, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_154, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_155, &{_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[18], id_ctrl_decoder_decoded_invInputs[19], id_ctrl_decoder_decoded_invInputs[20], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[25], _ibuf_io_inst_0_bits_inst_bits[30], _ibuf_io_inst_0_bits_inst_bits[31]}, &{_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[18], id_ctrl_decoder_decoded_invInputs[19], id_ctrl_decoder_decoded_invInputs[20], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], _ibuf_io_inst_0_bits_inst_bits[30], _ibuf_io_inst_0_bits_inst_bits[31]}, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_179, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_180}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:19] wire [2:0] id_ctrl_csr = {\|{&{_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[5], id_ctrl_decoder_decoded_invInputs[6], id_ctrl_decoder_decoded_invInputs[7], id_ctrl_decoder_decoded_invInputs[8], id_ctrl_decoder_decoded_invInputs[9], id_ctrl_decoder_decoded_invInputs[10], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[13], id_ctrl_decoder_decoded_invInputs[14], id_ctrl_decoder_decoded_invInputs[15], id_ctrl_decoder_decoded_invInputs[16], id_ctrl_decoder_decoded_invInputs[17], id_ctrl_decoder_decoded_invInputs[19], id_ctrl_decoder_decoded_invInputs[20], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], id_ctrl_decoder_decoded_invInputs[27], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_43, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_55, &{_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[5], id_ctrl_decoder_decoded_invInputs[6], id_ctrl_decoder_decoded_invInputs[7], id_ctrl_decoder_decoded_invInputs[8], id_ctrl_decoder_decoded_invInputs[9], id_ctrl_decoder_decoded_invInputs[10], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[13], id_ctrl_decoder_decoded_invInputs[14], id_ctrl_decoder_decoded_invInputs[15], id_ctrl_decoder_decoded_invInputs[16], id_ctrl_decoder_decoded_invInputs[17], id_ctrl_decoder_decoded_invInputs[18], _ibuf_io_inst_0_bits_inst_bits[21], id_ctrl_decoder_decoded_invInputs[20], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], _ibuf_io_inst_0_bits_inst_bits[28], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}, &{_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[5], id_ctrl_decoder_decoded_invInputs[6], id_ctrl_decoder_decoded_invInputs[7], id_ctrl_decoder_decoded_invInputs[8], id_ctrl_decoder_decoded_invInputs[9], id_ctrl_decoder_decoded_invInputs[10], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[13], id_ctrl_decoder_decoded_invInputs[14], id_ctrl_decoder_decoded_invInputs[15], id_ctrl_decoder_decoded_invInputs[16], id_ctrl_decoder_decoded_invInputs[17], _ibuf_io_inst_0_bits_inst_bits[20], id_ctrl_decoder_decoded_invInputs[19], _ibuf_io_inst_0_bits_inst_bits[22], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], _ibuf_io_inst_0_bits_inst_bits[28], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_101, &{_ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[5], id_ctrl_decoder_decoded_invInputs[6], id_ctrl_decoder_decoded_invInputs[7], id_ctrl_decoder_decoded_invInputs[8], id_ctrl_decoder_decoded_invInputs[9], id_ctrl_decoder_decoded_invInputs[10], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[13], id_ctrl_decoder_decoded_invInputs[14], id_ctrl_decoder_decoded_invInputs[15], id_ctrl_decoder_decoded_invInputs[16], id_ctrl_decoder_decoded_invInputs[17], id_ctrl_decoder_decoded_invInputs[18], _ibuf_io_inst_0_bits_inst_bits[21], id_ctrl_decoder_decoded_invInputs[20], id_ctrl_decoder_decoded_invInputs[21], _ibuf_io_inst_0_bits_inst_bits[24], _ibuf_io_inst_0_bits_inst_bits[25], id_ctrl_decoder_decoded_invInputs[24], _ibuf_io_inst_0_bits_inst_bits[27], _ibuf_io_inst_0_bits_inst_bits[28], _ibuf_io_inst_0_bits_inst_bits[29], _ibuf_io_inst_0_bits_inst_bits[30], id_ctrl_decoder_decoded_invInputs[29]}}, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_55, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_43}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] reg id_reg_fence; // @[RocketCore.scala:333:29] wire _id_csr_ren_T = id_ctrl_csr == 3'h6; // @[package.scala:16:47] wire id_csr_en = _id_csr_ren_T \| (&id_ctrl_csr) \| id_ctrl_csr == 3'h5; // @[package.scala:16:47, :81:59] wire id_mem_busy = ~io_dmem_ordered \| io_dmem_req_valid_0; // @[RocketCore.scala:403:{21,38}, :1130:41] wire _io_rocc_cmd_valid_T = wb_reg_valid & wb_ctrl_rocc; // @[RocketCore.scala:245:20, :288:35, :407:53] wire bypass_sources_3_1 = mem_reg_valid & mem_ctrl_wxd; // @[RocketCore.scala:244:21, :265:36, :459:20] wire _fp_data_hazard_ex_T_1 = ex_reg_inst[11:7] == _ibuf_io_inst_0_bits_inst_rs1; // @[RocketCore.scala:259:24, :311:20, :453:29, :461:82] wire _fp_data_hazard_mem_T_1 = mem_reg_inst[11:7] == _ibuf_io_inst_0_bits_inst_rs1; // @[RocketCore.scala:278:25, :311:20, :454:31, :461:82] wire _fp_data_hazard_ex_T_3 = ex_reg_inst[11:7] == _ibuf_io_inst_0_bits_inst_rs2; // @[RocketCore.scala:259:24, :311:20, :453:29, :461:82] wire _fp_data_hazard_mem_T_3 = mem_reg_inst[11:7] == _ibuf_io_inst_0_bits_inst_rs2; // @[RocketCore.scala:278:25, :311:20, :454:31, :461:82] reg ex_reg_rs_bypass_0; // @[RocketCore.scala:465:29] reg ex_reg_rs_bypass_1; // @[RocketCore.scala:465:29] reg [1:0] ex_reg_rs_lsb_0; // @[RocketCore.scala:466:26] reg [1:0] ex_reg_rs_lsb_1; // @[RocketCore.scala:466:26] reg [61:0] ex_reg_rs_msb_0; // @[RocketCore.scala:467:26] reg [61:0] ex_reg_rs_msb_1; // @[RocketCore.scala:467:26] wire [3:0][63:0] _GEN = {{io_dmem_resp_bits_data_word_bypass}, {wb_reg_wdata}, {mem_reg_wdata}, {64'h0}}; // @[package.scala:39:{76,86}] wire [63:0] ex_rs_0 = ex_reg_rs_bypass_0 ? _GEN[ex_reg_rs_lsb_0] : {ex_reg_rs_msb_0, ex_reg_rs_lsb_0}; // @[package.scala:39:{76,86}] wire [63:0] ex_rs_1 = ex_reg_rs_bypass_1 ? _GEN[ex_reg_rs_lsb_1] : {ex_reg_rs_msb_1, ex_reg_rs_lsb_1}; // @[package.scala:39:{76,86}] wire _ex_imm_b0_T_4 = ex_ctrl_sel_imm == 3'h5; // @[RocketCore.scala:243:20, :1341:24] wire ex_imm_sign = ~_ex_imm_b0_T_4 & ex_reg_inst[31]; // @[RocketCore.scala:259:24, :1341:{19,24,44}] wire _ex_imm_b4_1_T = ex_ctrl_sel_imm == 3'h2; // @[RocketCore.scala:243:20, :1342:26] wire _ex_imm_b4_1_T_2 = ex_ctrl_sel_imm == 3'h1; // @[RocketCore.scala:243:20, :1346:23] wire _ex_imm_b0_T = ex_ctrl_sel_imm == 3'h0; // @[RocketCore.scala:243:20, :1349:24] wire [66:0] ex_rs1shl = {3'h0, ex_reg_inst[3] ? {32'h0, ex_rs_0[31:0]} : ex_rs_0} << ex_reg_inst[14:13]; // @[RocketCore.scala:259:24, :469:14, :471:{22,34,47,65,79}] wire [3:0][63:0] _GEN_0 = {{ex_rs1shl[63:0]}, {{{24{ex_reg_pc[39]}}, ex_reg_pc}}, {ex_rs_0}, {64'h0}}; // @[RocketCore.scala:256:22, :469:14, :471:65, :472:48] wire [3:0] _ex_op2_T_1 = ex_reg_rvc ? 4'h2 : 4'h4; // @[RocketCore.scala:249:35, :481:19] wire div_io_req_valid = ex_reg_valid & ex_ctrl_div; // @[RocketCore.scala:243:20, :248:35, :512:36] wire ex_pc_valid = ex_reg_valid \| ex_reg_replay \| ex_reg_xcpt_interrupt; // @[RocketCore.scala:247:35, :248:35, :255:26, :595:{34,51}] wire wb_dcache_miss = wb_ctrl_mem & ~io_dmem_resp_valid; // @[RocketCore.scala:245:20, :596:{36,39}] wire replay_ex = ex_reg_replay \| ex_reg_valid & (ex_ctrl_mem & ~io_dmem_req_ready \| ex_ctrl_div & ~_div_io_req_ready \| wb_dcache_miss & ex_reg_load_use); // @[RocketCore.scala:243:20, :248:35, :253:35, :255:26, :511:19, :596:36, :597:{42,45,64}, :598:{42,45}, :600:43, :601:{33,50,75}] wire ctrl_killx = ibuf_io_kill \| replay_ex \| ~ex_reg_valid; // @[RocketCore.scala:248:35, :307:35, :601:33, :602:{35,48,51}] wire _mem_cfi_taken_T = mem_ctrl_branch & mem_br_taken; // @[RocketCore.scala:244:21, :284:25, :616:25] wire [3:0] _mem_br_target_T_6 = mem_reg_rvc ? 4'h2 : 4'h4; // @[RocketCore.scala:266:36, :618:8] wire [31:0] _mem_br_target_T_8 = _mem_cfi_taken_T ? {{20{mem_reg_inst[31]}}, mem_reg_inst[7], mem_reg_inst[30:25], mem_reg_inst[11:8], 1'h0} : mem_ctrl_jal ? {{12{mem_reg_inst[31]}}, mem_reg_inst[19:12], mem_reg_inst[20], mem_reg_inst[30:21], 1'h0} : {{28{_mem_br_target_T_6[3]}}, _mem_br_target_T_6}; // @[RocketCore.scala:244:21, :278:25, :616:{8,25}, :617:8, :618:8, :1341:44, :1343:65, :1345:39, :1346:39, :1347:62, :1349:57, :1355:8] wire [39:0] _mem_br_target_T_9 = mem_reg_pc + {{8{_mem_br_target_T_8[31]}}, _mem_br_target_T_8}; // @[RocketCore.scala:277:23, :615:41, :616:8] wire [39:0] _mem_npc_T_4 = mem_ctrl_jalr \| mem_reg_sfence ? {mem_reg_wdata[63:39] == 25'h0 \| (&(mem_reg_wdata[63:39])) ? mem_reg_wdata[39] : ~(mem_reg_wdata[38]), mem_reg_wdata[38:0]} : _mem_br_target_T_9; // @[RocketCore.scala:244:21, :276:27, :282:26, :615:41, :619:{21,36}, :1293:{17,23}, :1294:{18,21,29,34,46,51,54}, :1295:{8,16}] wire [39:0] mem_npc = _mem_npc_T_4 & 40'hFFFFFFFFFE; // @[RocketCore.scala:619:{21,129}] wire mem_wrong_npc = ex_pc_valid ? mem_npc != ex_reg_pc : ~(_ibuf_io_inst_0_valid \| io_imem_resp_valid) \| mem_npc != _ibuf_io_pc; // @[RocketCore.scala:256:22, :311:20, :595:{34,51}, :619:129, :621:{8,30}, :622:{8,31,62}] wire mem_cfi = mem_ctrl_branch \| mem_ctrl_jalr \| mem_ctrl_jal; // @[RocketCore.scala:244:21, :625:{33,50}] assign take_pc_mem = mem_reg_valid & ~mem_reg_xcpt & (mem_wrong_npc \| mem_reg_sfence); // @[RocketCore.scala:265:36, :268:36, :276:27, :621:8, :624:27, :629:{32,49,71}] wire mem_debug_breakpoint = mem_reg_load & _bpu_io_debug_ld \| mem_reg_store & _bpu_io_debug_st; // @[RocketCore.scala:273:36, :274:36, :414:19, :678:{44,64,82}] wire mem_ldst_xcpt = mem_debug_breakpoint \| mem_reg_load & _bpu_io_xcpt_ld \| mem_reg_store & _bpu_io_xcpt_st; // @[RocketCore.scala:273:36, :274:36, :414:19, :677:{38,57,75}, :678:64, :1278:35] wire dcache_kill_mem = bypass_sources_3_1 & io_dmem_replay_next; // @[RocketCore.scala:459:20, :695:55] wire fpu_kill_mem = mem_reg_valid & mem_ctrl_fp & io_fpu_nack_mem; // @[RocketCore.scala:244:21, :265:36, :696:{36,51}] wire killm_common = dcache_kill_mem \| take_pc_wb \| mem_reg_xcpt \| ~mem_reg_valid; // @[RocketCore.scala:265:36, :268:36, :695:55, :700:{38,52,68,71}, :762:{27,38,53}] reg div_io_kill_REG; // @[RocketCore.scala:701:41] wire _GEN_1 = wb_reg_valid & wb_ctrl_mem; // @[RocketCore.scala:245:20, :288:35, :730:19] wire _GEN_2 = _GEN_1 & io_dmem_s2_xcpt_pf_st; // @[RocketCore.scala:730:{19,34}] wire _GEN_3 = _GEN_1 & io_dmem_s2_xcpt_pf_ld; // @[RocketCore.scala:730:19, :731:34] wire _GEN_4 = _GEN_1 & io_dmem_s2_xcpt_ae_st; // @[RocketCore.scala:730:19, :734:34] wire _GEN_5 = _GEN_1 & io_dmem_s2_xcpt_ae_ld; // @[RocketCore.scala:730:19, :735:34] wire _GEN_6 = _GEN_1 & io_dmem_s2_xcpt_ma_st; // @[RocketCore.scala:730:19, :736:34] wire wb_xcpt = wb_reg_xcpt \| _GEN_2 \| _GEN_3 \| _GEN_4 \| _GEN_5 \| _GEN_6 \| _GEN_1 & io_dmem_s2_xcpt_ma_ld; // @[RocketCore.scala:289:35, :730:{19,34}, :731:34, :734:34, :735:34, :736:34, :737:34, :1278:35] wire wb_wxd = wb_reg_valid & wb_ctrl_wxd; // @[RocketCore.scala:245:20, :288:35, :755:29] wire wb_set_sboard = wb_ctrl_div \| wb_dcache_miss \| wb_ctrl_rocc \| wb_ctrl_vec; // @[RocketCore.scala:245:20, :596:36, :756:{35,53,69}] wire replay_wb_common = io_dmem_s2_nack \| wb_reg_replay; // @[RocketCore.scala:290:35, :757:42] wire _replay_wb_T = replay_wb_common \| _io_rocc_cmd_valid_T; // @[RocketCore.scala:407:53, :757:42, :761:36] assign take_pc_wb = _replay_wb_T \| wb_xcpt \| _csr_io_eret \| wb_reg_flush_pipe; // @[RocketCore.scala:291:35, :341:19, :761:36, :762:{27,38,53}, :1278:35] wire dmem_resp_valid = io_dmem_resp_valid & io_dmem_resp_bits_has_data; // @[RocketCore.scala:768:44] wire dmem_resp_replay = dmem_resp_valid & io_dmem_resp_bits_replay; // @[RocketCore.scala:768:44, :769:42] wire _GEN_7 = dmem_resp_replay & ~(io_dmem_resp_bits_tag[0]); // @[RocketCore.scala:765:{23,45}, :769:42, :809:26] assign ll_arb_io_out_ready = ~_GEN_7 & ~wb_wxd; // @[RocketCore.scala:755:29, :782:{23,26}, :809:{26,44}, :810:25] wire [4:0] ll_waddr = _GEN_7 ? io_dmem_resp_bits_tag[5:1] : _ll_arb_io_out_bits_tag; // @[RocketCore.scala:767:46, :776:22, :780:26, :809:{26,44}, :811:14] wire ll_wen = _GEN_7 \| ll_arb_io_out_ready & _ll_arb_io_out_valid; // @[Decoupled.scala:51:35] wire wb_valid = wb_reg_valid & ~_replay_wb_T & ~wb_xcpt; // @[RocketCore.scala:288:35, :761:36, :815:{31,34,45,48}, :1278:35] wire wb_wen = wb_valid & wb_ctrl_wxd; // @[RocketCore.scala:245:20, :815:{31,45}, :816:25] wire rf_wen = wb_wen \| ll_wen; // @[RocketCore.scala:781:24, :809:44, :812:12, :816:25, :817:23] wire [4:0] rf_waddr = ll_wen ? ll_waddr : wb_reg_inst[11:7]; // @[RocketCore.scala:300:24, :455:29, :780:26, :781:24, :809:44, :811:14, :812:12, :818:21] wire [63:0] rf_wdata = dmem_resp_valid & ~(io_dmem_resp_bits_tag[0]) ? io_dmem_resp_bits_data : ll_wen ? _ll_arb_io_out_bits_data : (\|wb_ctrl_csr) ? _csr_io_rw_rdata : wb_reg_wdata; // @[RocketCore.scala:245:20, :302:25, :341:19, :765:{23,45}, :768:44, :776:22, :781:24, :809:44, :812:12, :819:{21,38}, :820:21, :821:{21,34}] wire [63:0] id_rs_0 = rf_wen & (\|rf_waddr) & rf_waddr == _ibuf_io_inst_0_bits_inst_rs1 ? rf_wdata : _rf_ext_R1_data; // @[RocketCore.scala:311:20, :817:23, :818:21, :819:21, :824:17, :1319:15, :1326:19, :1331:{16,25}, :1334:{20,31,39}] wire [63:0] id_rs_1 = rf_wen & (\|rf_waddr) & rf_waddr == _ibuf_io_inst_0_bits_inst_rs2 ? rf_wdata : _rf_ext_R0_data; // @[RocketCore.scala:311:20, :817:23, :818:21, :819:21, :824:17, :1319:15, :1326:19, :1331:{16,25}, :1334:{20,31,39}] wire _htval_valid_imem_T = wb_reg_cause == 64'h14; // @[package.scala:16:47] wire tval_any_addr = ~wb_reg_xcpt \| wb_reg_cause == 64'h3 \| wb_reg_cause == 64'h1 \| wb_reg_cause == 64'hC \| _htval_valid_imem_T; // @[package.scala:16:47, :81:59] wire hazard_targets_0_1 = (\|_id_ctrl_decoder_decoded_orMatrixOutputs_T_59) & (\|_ibuf_io_inst_0_bits_inst_rs1); // @[pla.scala:114:{19,36}] wire hazard_targets_1_1 = (\|_id_ctrl_decoder_decoded_orMatrixOutputs_T_61) & (\|_ibuf_io_inst_0_bits_inst_rs2); // @[pla.scala:114:{19,36}] wire hazard_targets_2_1 = (\|_id_ctrl_decoder_decoded_orMatrixOutputs_T_10) & (\|_ibuf_io_inst_0_bits_inst_rd); // @[pla.scala:114:{19,36}] reg [31:0] _r; // @[RocketCore.scala:1305:29] wire [31:0] r = {_r[31:1], 1'h0}; // @[RocketCore.scala:1305:29, :1306:{35,40}] wire [31:0] _GEN_8 = {27'h0, _ibuf_io_inst_0_bits_inst_rs1}; // @[RocketCore.scala:311:20, :1302:35, :1309:58] wire [31:0] _id_sboard_hazard_T = r >> _GEN_8; // @[RocketCore.scala:1302:35, :1306:40] wire [31:0] _GEN_9 = {27'h0, _ibuf_io_inst_0_bits_inst_rs2}; // @[RocketCore.scala:311:20, :1302:35, :1309:58] wire [31:0] _id_sboard_hazard_T_7 = r >> _GEN_9; // @[RocketCore.scala:1302:35, :1306:40] wire [31:0] _GEN_10 = {27'h0, _ibuf_io_inst_0_bits_inst_rd}; // @[RocketCore.scala:311:20, :1302:35, :1309:58] wire [31:0] _id_sboard_hazard_T_14 = r >> _GEN_10; // @[RocketCore.scala:1302:35, :1306:40] wire _fp_data_hazard_ex_T_7 = _ibuf_io_inst_0_bits_inst_rd == ex_reg_inst[11:7]; // @[RocketCore.scala:259:24, :311:20, :453:29, :989:70] wire _fp_data_hazard_mem_T_7 = _ibuf_io_inst_0_bits_inst_rd == mem_reg_inst[11:7]; // @[RocketCore.scala:278:25, :311:20, :454:31, :998:72] wire data_hazard_mem = mem_ctrl_wxd & (hazard_targets_0_1 & _fp_data_hazard_mem_T_1 \| hazard_targets_1_1 & _fp_data_hazard_mem_T_3 \| hazard_targets_2_1 & _fp_data_hazard_mem_T_7); // @[RocketCore.scala:244:21, :461:82, :969:42, :970:42, :971:42, :998:{38,72}, :1287:{27,50}] wire _fp_data_hazard_wb_T_1 = _ibuf_io_inst_0_bits_inst_rs1 == wb_reg_inst[11:7]; // @[RocketCore.scala:300:24, :311:20, :455:29, :1008:70] wire _fp_data_hazard_wb_T_3 = _ibuf_io_inst_0_bits_inst_rs2 == wb_reg_inst[11:7]; // @[RocketCore.scala:300:24, :311:20, :455:29, :1008:70] wire _fp_data_hazard_wb_T_7 = _ibuf_io_inst_0_bits_inst_rd == wb_reg_inst[11:7]; // @[RocketCore.scala:300:24, :311:20, :455:29, :1008:70] reg [31:0] _id_stall_fpu_r; // @[RocketCore.scala:1305:29] wire [31:0] _id_stall_fpu_T_20 = _id_stall_fpu_r >> _GEN_8; // @[RocketCore.scala:1302:35, :1305:29] wire [31:0] _id_stall_fpu_T_23 = _id_stall_fpu_r >> _GEN_9; // @[RocketCore.scala:1302:35, :1305:29] wire [31:0] _id_stall_fpu_T_26 = _id_stall_fpu_r >> _ibuf_io_inst_0_bits_inst_rs3; // @[RocketCore.scala:311:20, :1302:35, :1305:29] wire [31:0] _id_stall_fpu_T_29 = _id_stall_fpu_r >> _GEN_10; // @[RocketCore.scala:1302:35, :1305:29] reg dcache_blocked_blocked; // @[RocketCore.scala:1024:22] reg rocc_blocked; // @[RocketCore.scala:1028:25] wire _ctrl_stalld_T_32 = ex_reg_valid & (ex_ctrl_wxd & (hazard_targets_0_1 & _fp_data_hazard_ex_T_1 \| hazard_targets_1_1 & _fp_data_hazard_ex_T_3 \| hazard_targets_2_1 & _fp_data_hazard_ex_T_7) & ((\|ex_ctrl_csr) \| ex_ctrl_jalr \| ex_ctrl_mem \| ex_ctrl_mul \| ex_ctrl_div \| ex_ctrl_fp \| ex_ctrl_rocc) \| (\|_id_ctrl_decoder_decoded_orMatrixOutputs_T_67) & ex_ctrl_wfd & (io_fpu_dec_ren1 & _fp_data_hazard_ex_T_1 \| io_fpu_dec_ren2 & _fp_data_hazard_ex_T_3 \| io_fpu_dec_ren3 & _ibuf_io_inst_0_bits_inst_rs3 == ex_reg_inst[11:7] \| io_fpu_dec_wen & _fp_data_hazard_ex_T_7)) \| mem_reg_valid & (data_hazard_mem & ((\|mem_ctrl_csr) \| mem_ctrl_mem & mem_mem_cmd_bh \| mem_ctrl_mul \| mem_ctrl_div \| mem_ctrl_fp \| mem_ctrl_rocc \| mem_ctrl_vec) \| (\|_id_ctrl_decoder_decoded_orMatrixOutputs_T_67) & mem_ctrl_wfd & (io_fpu_dec_ren1 & _fp_data_hazard_mem_T_1 \| io_fpu_dec_ren2 & _fp_data_hazard_mem_T_3 \| io_fpu_dec_ren3 & _ibuf_io_inst_0_bits_inst_rs3 == mem_reg_inst[11:7] \| io_fpu_dec_wen & _fp_data_hazard_mem_T_7)) \| wb_reg_valid & (wb_ctrl_wxd & (hazard_targets_0_1 & _fp_data_hazard_wb_T_1 \| hazard_targets_1_1 & _fp_data_hazard_wb_T_3 \| hazard_targets_2_1 & _fp_data_hazard_wb_T_7) & wb_set_sboard \| (\|_id_ctrl_decoder_decoded_orMatrixOutputs_T_67) & wb_ctrl_wfd & (io_fpu_dec_ren1 & _fp_data_hazard_wb_T_1 \| io_fpu_dec_ren2 & _fp_data_hazard_wb_T_3 \| io_fpu_dec_ren3 & _ibuf_io_inst_0_bits_inst_rs3 == wb_reg_inst[11:7] \| io_fpu_dec_wen & _fp_data_hazard_wb_T_7)) \| hazard_targets_0_1 & _id_sboard_hazard_T[0] & ~(ll_wen & ll_waddr == _ibuf_io_inst_0_bits_inst_rs1) \| hazard_targets_1_1 & _id_sboard_hazard_T_7[0] & ~(ll_wen & ll_waddr == _ibuf_io_inst_0_bits_inst_rs2) \| hazard_targets_2_1 & _id_sboard_hazard_T_14[0] & ~(ll_wen & ll_waddr == _ibuf_io_inst_0_bits_inst_rd) \| _csr_io_singleStep & (ex_reg_valid \| mem_reg_valid \| wb_reg_valid) \| id_csr_en & _csr_io_decode_0_fp_csr & ~io_fpu_fcsr_rdy \| (\|_id_ctrl_decoder_decoded_orMatrixOutputs_T_67) & (io_fpu_dec_ren1 & _id_stall_fpu_T_20[0] \| io_fpu_dec_ren2 & _id_stall_fpu_T_23[0] \| io_fpu_dec_ren3 & _id_stall_fpu_T_26[0] \| io_fpu_dec_wen & _id_stall_fpu_T_29[0]) \| (\|_id_ctrl_decoder_decoded_orMatrixOutputs_T_29) & dcache_blocked_blocked & ~io_dmem_perf_grant \| (\|_id_ctrl_decoder_decoded_orMatrixOutputs_T_12) & (~(_div_io_req_ready \| _div_io_resp_valid & ~wb_wxd) \| div_io_req_valid) \| id_mem_busy & ((\|_id_ctrl_decoder_decoded_orMatrixOutputs_T_2) & _ibuf_io_inst_0_bits_inst_bits[25] \| (&_id_ctrl_decoder_decoded_andMatrixOutputs_T_33) \| id_reg_fence & (\|_id_ctrl_decoder_decoded_orMatrixOutputs_T_29)) \| _csr_io_csr_stall \| id_reg_pause; // @[pla.scala:98:{53,70}, :114:{19,36}] wire ctrl_killd = ~_ibuf_io_inst_0_valid \| _ibuf_io_inst_0_bits_replay \| ibuf_io_kill \| _ctrl_stalld_T_32 \| _csr_io_interrupt; // @[RocketCore.scala:307:35, :311:20, :341:19, :1032:{18,35,51}, :1033:23, :1034:74, :1036:61, :1037:32, :1039:34, :1041:15, :1042:17, :1043:22, :1046:{17,40,71,89,104}, :1287:50] reg io_imem_progress_REG; // @[RocketCore.scala:1059:30] wire io_ptw_sfence_valid_0 = wb_reg_valid & wb_reg_sfence; // @[RocketCore.scala:288:35, :294:26, :1060:40] wire _io_imem_btb_update_bits_cfiType_T_9 = mem_ctrl_jal \| mem_ctrl_jalr; // @[RocketCore.scala:244:21, :1074:23] wire [38:0] _io_imem_btb_update_bits_br_pc_T_1 = mem_reg_pc[38:0] + {37'h0, ~mem_reg_rvc, 1'h0}; // @[RocketCore.scala:266:36, :277:23, :1079:{69,74}] wire [38:0] io_imem_bht_update_bits_pc_0 = {_io_imem_btb_update_bits_br_pc_T_1[38:2], 2'h0}; // @[RocketCore.scala:1079:69, :1080:66] assign io_dmem_req_valid_0 = ex_reg_valid & ex_ctrl_mem; // @[RocketCore.scala:243:20, :248:35, :1130:41] reg [63:0] coreMonitorBundle_rd0val_REG; // @[RocketCore.scala:1199:46] reg [63:0] coreMonitorBundle_rd0val_REG_1; // @[RocketCore.scala:1199:38] reg [63:0] coreMonitorBundle_rd1val_REG; // @[RocketCore.scala:1201:46] reg [63:0] coreMonitorBundle_rd1val_REG_1; // @[RocketCore.scala:1201:38]
Generate the Verilog code corresponding to the following Chisel files. File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module ClockCrossingReg_w43( // @[SynchronizerReg.scala:191:7] input clock, // @[SynchronizerReg.scala:191:7] input reset, // @[SynchronizerReg.scala:191:7] input [42:0] io_d, // @[SynchronizerReg.scala:195:14] output [42:0] io_q, // @[SynchronizerReg.scala:195:14] input io_en // @[SynchronizerReg.scala:195:14] ); wire [42:0] io_d_0 = io_d; // @[SynchronizerReg.scala:191:7] wire io_en_0 = io_en; // @[SynchronizerReg.scala:191:7] wire [42:0] io_q_0; // @[SynchronizerReg.scala:191:7] reg [42:0] cdc_reg; // @[SynchronizerReg.scala:201:76] assign io_q_0 = cdc_reg; // @[SynchronizerReg.scala:191:7, :201:76] always @(posedge clock) begin // @[SynchronizerReg.scala:191:7] if (io_en_0) // @[SynchronizerReg.scala:191:7] cdc_reg <= io_d_0; // @[SynchronizerReg.scala:191:7, :201:76] always @(posedge) assign io_q = io_q_0; // @[SynchronizerReg.scala:191:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File WidthWidget.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.AddressSet import freechips.rocketchip.util.{Repeater, UIntToOH1} // innBeatBytes => the new client-facing bus width class TLWidthWidget(innerBeatBytes: Int)(implicit p: Parameters) extends LazyModule { private def noChangeRequired(manager: TLManagerPortParameters) = manager.beatBytes == innerBeatBytes val node = new TLAdapterNode( clientFn = { case c => c }, managerFn = { case m => m.v1copy(beatBytes = innerBeatBytes) }){ override def circuitIdentity = edges.out.map(_.manager).forall(noChangeRequired) } override lazy val desiredName = s"TLWidthWidget$innerBeatBytes" lazy val module = new Impl class Impl extends LazyModuleImp(this) { def merge[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T]) = { val inBytes = edgeIn.manager.beatBytes val outBytes = edgeOut.manager.beatBytes val ratio = outBytes / inBytes val keepBits = log2Ceil(outBytes) val dropBits = log2Ceil(inBytes) val countBits = log2Ceil(ratio) val size = edgeIn.size(in.bits) val hasData = edgeIn.hasData(in.bits) val limit = UIntToOH1(size, keepBits) >> dropBits val count = RegInit(0.U(countBits.W)) val first = count === 0.U val last = count === limit \|\| !hasData val enable = Seq.tabulate(ratio) { i => !((count ^ i.U) & limit).orR } val corrupt_reg = RegInit(false.B) val corrupt_in = edgeIn.corrupt(in.bits) val corrupt_out = corrupt_in \|\| corrupt_reg when (in.fire) { count := count + 1.U corrupt_reg := corrupt_out when (last) { count := 0.U corrupt_reg := false.B } } def helper(idata: UInt): UInt = { // rdata is X until the first time a multi-beat write occurs. // Prevent the X from leaking outside by jamming the mux control until // the first time rdata is written (and hence no longer X). val rdata_written_once = RegInit(false.B) val masked_enable = enable.map(_ \|\| !rdata_written_once) val odata = Seq.fill(ratio) { WireInit(idata) } val rdata = Reg(Vec(ratio-1, chiselTypeOf(idata))) val pdata = rdata :+ idata val mdata = (masked_enable zip (odata zip pdata)) map { case (e, (o, p)) => Mux(e, o, p) } when (in.fire && !last) { rdata_written_once := true.B (rdata zip mdata) foreach { case (r, m) => r := m } } Cat(mdata.reverse) } in.ready := out.ready \|\| !last out.valid := in.valid && last out.bits := in.bits // Don't put down hardware if we never carry data edgeOut.data(out.bits) := (if (edgeIn.staticHasData(in.bits) == Some(false)) 0.U else helper(edgeIn.data(in.bits))) edgeOut.corrupt(out.bits) := corrupt_out (out.bits, in.bits) match { case (o: TLBundleA, i: TLBundleA) => o.mask := edgeOut.mask(o.address, o.size) & Mux(hasData, helper(i.mask), ~0.U(outBytes.W)) case (o: TLBundleB, i: TLBundleB) => o.mask := edgeOut.mask(o.address, o.size) & Mux(hasData, helper(i.mask), ~0.U(outBytes.W)) case (o: TLBundleC, i: TLBundleC) => () case (o: TLBundleD, i: TLBundleD) => () case _ => require(false, "Impossible bundle combination in WidthWidget") } } def split[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T], sourceMap: UInt => UInt) = { val inBytes = edgeIn.manager.beatBytes val outBytes = edgeOut.manager.beatBytes val ratio = inBytes / outBytes val keepBits = log2Ceil(inBytes) val dropBits = log2Ceil(outBytes) val countBits = log2Ceil(ratio) val size = edgeIn.size(in.bits) val hasData = edgeIn.hasData(in.bits) val limit = UIntToOH1(size, keepBits) >> dropBits val count = RegInit(0.U(countBits.W)) val first = count === 0.U val last = count === limit \|\| !hasData when (out.fire) { count := count + 1.U when (last) { count := 0.U } } // For sub-beat transfer, extract which part matters val sel = in.bits match { case a: TLBundleA => a.address(keepBits-1, dropBits) case b: TLBundleB => b.address(keepBits-1, dropBits) case c: TLBundleC => c.address(keepBits-1, dropBits) case d: TLBundleD => { val sel = sourceMap(d.source) val hold = Mux(first, sel, RegEnable(sel, first)) // a_first is not for whole xfer hold & ~limit // if more than one a_first/xfer, the address must be aligned anyway } } val index = sel \| count def helper(idata: UInt, width: Int): UInt = { val mux = VecInit.tabulate(ratio) { i => idata((i+1)outByteswidth-1, ioutByteswidth) } mux(index) } out.bits := in.bits out.valid := in.valid in.ready := out.ready // Don't put down hardware if we never carry data edgeOut.data(out.bits) := (if (edgeIn.staticHasData(in.bits) == Some(false)) 0.U else helper(edgeIn.data(in.bits), 8)) (out.bits, in.bits) match { case (o: TLBundleA, i: TLBundleA) => o.mask := helper(i.mask, 1) case (o: TLBundleB, i: TLBundleB) => o.mask := helper(i.mask, 1) case (o: TLBundleC, i: TLBundleC) => () // replicating corrupt to all beats is ok case (o: TLBundleD, i: TLBundleD) => () case _ => require(false, "Impossbile bundle combination in WidthWidget") } // Repeat the input if we're not last !last } def splice[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T], sourceMap: UInt => UInt) = { if (edgeIn.manager.beatBytes == edgeOut.manager.beatBytes) { // nothing to do; pass it through out.bits := in.bits out.valid := in.valid in.ready := out.ready } else if (edgeIn.manager.beatBytes > edgeOut.manager.beatBytes) { // split input to output val repeat = Wire(Bool()) val repeated = Repeater(in, repeat) val cated = Wire(chiselTypeOf(repeated)) cated <> repeated edgeIn.data(cated.bits) := Cat( edgeIn.data(repeated.bits)(edgeIn.manager.beatBytes8-1, edgeOut.manager.beatBytes8), edgeIn.data(in.bits)(edgeOut.manager.beatBytes8-1, 0)) repeat := split(edgeIn, cated, edgeOut, out, sourceMap) } else { // merge input to output merge(edgeIn, in, edgeOut, out) } } (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => // If the master is narrower than the slave, the D channel must be narrowed. // This is tricky, because the D channel has no address data. // Thus, you don't know which part of a sub-beat transfer to extract. // To fix this, we record the relevant address bits for all sources. // The assumption is that this sort of situation happens only where // you connect a narrow master to the system bus, so there are few sources. def sourceMap(source_bits: UInt) = { val source = if (edgeIn.client.endSourceId == 1) 0.U(0.W) else source_bits require (edgeOut.manager.beatBytes > edgeIn.manager.beatBytes) val keepBits = log2Ceil(edgeOut.manager.beatBytes) val dropBits = log2Ceil(edgeIn.manager.beatBytes) val sources = Reg(Vec(edgeIn.client.endSourceId, UInt((keepBits-dropBits).W))) val a_sel = in.a.bits.address(keepBits-1, dropBits) when (in.a.fire) { if (edgeIn.client.endSourceId == 1) { // avoid extraction-index-width warning sources(0) := a_sel } else { sources(in.a.bits.source) := a_sel } } // depopulate unused source registers: edgeIn.client.unusedSources.foreach { id => sources(id) := 0.U } val bypass = in.a.valid && in.a.bits.source === source if (edgeIn.manager.minLatency > 0) sources(source) else Mux(bypass, a_sel, sources(source)) } splice(edgeIn, in.a, edgeOut, out.a, sourceMap) splice(edgeOut, out.d, edgeIn, in.d, sourceMap) if (edgeOut.manager.anySupportAcquireB && edgeIn.client.anySupportProbe) { splice(edgeOut, out.b, edgeIn, in.b, sourceMap) splice(edgeIn, in.c, edgeOut, out.c, sourceMap) out.e.valid := in.e.valid out.e.bits := in.e.bits in.e.ready := out.e.ready } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLWidthWidget { def apply(innerBeatBytes: Int)(implicit p: Parameters): TLNode = { val widget = LazyModule(new TLWidthWidget(innerBeatBytes)) widget.node } def apply(wrapper: TLBusWrapper)(implicit p: Parameters): TLNode = apply(wrapper.beatBytes) } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMWidthWidget(first: Int, second: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("WidthWidget")) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff))) (ram.node := TLDelayer(0.1) := TLFragmenter(4, 256) := TLWidthWidget(second) := TLWidthWidget(first) := TLDelayer(0.1) := model.node := fuzz.node) lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMWidthWidgetTest(little: Int, big: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMWidthWidget(little,big,txns)).module) dut.io.start := DontCare io.finished := dut.io.finished } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /* Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } }	module TLInterconnectCoupler_sbus_to_bus_named_cbus( // @[LazyModuleImp.scala:138:7] input clock, // @[LazyModuleImp.scala:138:7] input reset, // @[LazyModuleImp.scala:138:7] output auto_widget_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_widget_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_widget_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_widget_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_widget_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_widget_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [28:0] auto_widget_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [15:0] auto_widget_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [127:0] auto_widget_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_widget_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_widget_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_widget_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_widget_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_widget_anon_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_widget_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_widget_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_widget_anon_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_widget_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [127:0] auto_widget_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_widget_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_bus_xing_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_bus_xing_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_bus_xing_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_bus_xing_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [28:0] auto_bus_xing_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_bus_xing_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_bus_xing_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_bus_xing_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_bus_xing_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_bus_xing_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_bus_xing_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire auto_widget_anon_in_a_valid_0 = auto_widget_anon_in_a_valid; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_widget_anon_in_a_bits_opcode_0 = auto_widget_anon_in_a_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_widget_anon_in_a_bits_param_0 = auto_widget_anon_in_a_bits_param; // @[LazyModuleImp.scala:138:7] wire [3:0] auto_widget_anon_in_a_bits_size_0 = auto_widget_anon_in_a_bits_size; // @[LazyModuleImp.scala:138:7] wire [5:0] auto_widget_anon_in_a_bits_source_0 = auto_widget_anon_in_a_bits_source; // @[LazyModuleImp.scala:138:7] wire [28:0] auto_widget_anon_in_a_bits_address_0 = auto_widget_anon_in_a_bits_address; // @[LazyModuleImp.scala:138:7] wire [15:0] auto_widget_anon_in_a_bits_mask_0 = auto_widget_anon_in_a_bits_mask; // @[LazyModuleImp.scala:138:7] wire [127:0] auto_widget_anon_in_a_bits_data_0 = auto_widget_anon_in_a_bits_data; // @[LazyModuleImp.scala:138:7] wire auto_widget_anon_in_a_bits_corrupt_0 = auto_widget_anon_in_a_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire auto_widget_anon_in_d_ready_0 = auto_widget_anon_in_d_ready; // @[LazyModuleImp.scala:138:7] wire auto_bus_xing_out_a_ready_0 = auto_bus_xing_out_a_ready; // @[LazyModuleImp.scala:138:7] wire auto_bus_xing_out_d_valid_0 = auto_bus_xing_out_d_valid; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_bus_xing_out_d_bits_opcode_0 = auto_bus_xing_out_d_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [1:0] auto_bus_xing_out_d_bits_param_0 = auto_bus_xing_out_d_bits_param; // @[LazyModuleImp.scala:138:7] wire [3:0] auto_bus_xing_out_d_bits_size_0 = auto_bus_xing_out_d_bits_size; // @[LazyModuleImp.scala:138:7] wire [5:0] auto_bus_xing_out_d_bits_source_0 = auto_bus_xing_out_d_bits_source; // @[LazyModuleImp.scala:138:7] wire auto_bus_xing_out_d_bits_sink_0 = auto_bus_xing_out_d_bits_sink; // @[LazyModuleImp.scala:138:7] wire auto_bus_xing_out_d_bits_denied_0 = auto_bus_xing_out_d_bits_denied; // @[LazyModuleImp.scala:138:7] wire [63:0] auto_bus_xing_out_d_bits_data_0 = auto_bus_xing_out_d_bits_data; // @[LazyModuleImp.scala:138:7] wire auto_bus_xing_out_d_bits_corrupt_0 = auto_bus_xing_out_d_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire bus_xingOut_a_ready = auto_bus_xing_out_a_ready_0; // @[MixedNode.scala:542:17] wire bus_xingOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] bus_xingOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] bus_xingOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] bus_xingOut_a_bits_size; // @[MixedNode.scala:542:17] wire [5:0] bus_xingOut_a_bits_source; // @[MixedNode.scala:542:17] wire [28:0] bus_xingOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] bus_xingOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] bus_xingOut_a_bits_data; // @[MixedNode.scala:542:17] wire bus_xingOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire bus_xingOut_d_ready; // @[MixedNode.scala:542:17] wire bus_xingOut_d_valid = auto_bus_xing_out_d_valid_0; // @[MixedNode.scala:542:17] wire [2:0] bus_xingOut_d_bits_opcode = auto_bus_xing_out_d_bits_opcode_0; // @[MixedNode.scala:542:17] wire [1:0] bus_xingOut_d_bits_param = auto_bus_xing_out_d_bits_param_0; // @[MixedNode.scala:542:17] wire [3:0] bus_xingOut_d_bits_size = auto_bus_xing_out_d_bits_size_0; // @[MixedNode.scala:542:17] wire [5:0] bus_xingOut_d_bits_source = auto_bus_xing_out_d_bits_source_0; // @[MixedNode.scala:542:17] wire bus_xingOut_d_bits_sink = auto_bus_xing_out_d_bits_sink_0; // @[MixedNode.scala:542:17] wire bus_xingOut_d_bits_denied = auto_bus_xing_out_d_bits_denied_0; // @[MixedNode.scala:542:17] wire [63:0] bus_xingOut_d_bits_data = auto_bus_xing_out_d_bits_data_0; // @[MixedNode.scala:542:17] wire bus_xingOut_d_bits_corrupt = auto_bus_xing_out_d_bits_corrupt_0; // @[MixedNode.scala:542:17] wire auto_widget_anon_in_a_ready_0; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_widget_anon_in_d_bits_opcode_0; // @[LazyModuleImp.scala:138:7] wire [1:0] auto_widget_anon_in_d_bits_param_0; // @[LazyModuleImp.scala:138:7] wire [3:0] auto_widget_anon_in_d_bits_size_0; // @[LazyModuleImp.scala:138:7] wire [5:0] auto_widget_anon_in_d_bits_source_0; // @[LazyModuleImp.scala:138:7] wire auto_widget_anon_in_d_bits_sink_0; // @[LazyModuleImp.scala:138:7] wire auto_widget_anon_in_d_bits_denied_0; // @[LazyModuleImp.scala:138:7] wire [127:0] auto_widget_anon_in_d_bits_data_0; // @[LazyModuleImp.scala:138:7] wire auto_widget_anon_in_d_bits_corrupt_0; // @[LazyModuleImp.scala:138:7] wire auto_widget_anon_in_d_valid_0; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_bus_xing_out_a_bits_opcode_0; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_bus_xing_out_a_bits_param_0; // @[LazyModuleImp.scala:138:7] wire [3:0] auto_bus_xing_out_a_bits_size_0; // @[LazyModuleImp.scala:138:7] wire [5:0] auto_bus_xing_out_a_bits_source_0; // @[LazyModuleImp.scala:138:7] wire [28:0] auto_bus_xing_out_a_bits_address_0; // @[LazyModuleImp.scala:138:7] wire [7:0] auto_bus_xing_out_a_bits_mask_0; // @[LazyModuleImp.scala:138:7] wire [63:0] auto_bus_xing_out_a_bits_data_0; // @[LazyModuleImp.scala:138:7] wire auto_bus_xing_out_a_bits_corrupt_0; // @[LazyModuleImp.scala:138:7] wire auto_bus_xing_out_a_valid_0; // @[LazyModuleImp.scala:138:7] wire auto_bus_xing_out_d_ready_0; // @[LazyModuleImp.scala:138:7] wire bus_xingIn_a_ready = bus_xingOut_a_ready; // @[MixedNode.scala:542:17, :551:17] wire bus_xingIn_a_valid; // @[MixedNode.scala:551:17] assign auto_bus_xing_out_a_valid_0 = bus_xingOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] bus_xingIn_a_bits_opcode; // @[MixedNode.scala:551:17] assign auto_bus_xing_out_a_bits_opcode_0 = bus_xingOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] bus_xingIn_a_bits_param; // @[MixedNode.scala:551:17] assign auto_bus_xing_out_a_bits_param_0 = bus_xingOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] bus_xingIn_a_bits_size; // @[MixedNode.scala:551:17] assign auto_bus_xing_out_a_bits_size_0 = bus_xingOut_a_bits_size; // @[MixedNode.scala:542:17] wire [5:0] bus_xingIn_a_bits_source; // @[MixedNode.scala:551:17] assign auto_bus_xing_out_a_bits_source_0 = bus_xingOut_a_bits_source; // @[MixedNode.scala:542:17] wire [28:0] bus_xingIn_a_bits_address; // @[MixedNode.scala:551:17] assign auto_bus_xing_out_a_bits_address_0 = bus_xingOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] bus_xingIn_a_bits_mask; // @[MixedNode.scala:551:17] assign auto_bus_xing_out_a_bits_mask_0 = bus_xingOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] bus_xingIn_a_bits_data; // @[MixedNode.scala:551:17] assign auto_bus_xing_out_a_bits_data_0 = bus_xingOut_a_bits_data; // @[MixedNode.scala:542:17] wire bus_xingIn_a_bits_corrupt; // @[MixedNode.scala:551:17] assign auto_bus_xing_out_a_bits_corrupt_0 = bus_xingOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire bus_xingIn_d_ready; // @[MixedNode.scala:551:17] assign auto_bus_xing_out_d_ready_0 = bus_xingOut_d_ready; // @[MixedNode.scala:542:17] wire bus_xingIn_d_valid = bus_xingOut_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] bus_xingIn_d_bits_opcode = bus_xingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] bus_xingIn_d_bits_param = bus_xingOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] bus_xingIn_d_bits_size = bus_xingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [5:0] bus_xingIn_d_bits_source = bus_xingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire bus_xingIn_d_bits_sink = bus_xingOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire bus_xingIn_d_bits_denied = bus_xingOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] bus_xingIn_d_bits_data = bus_xingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire bus_xingIn_d_bits_corrupt = bus_xingOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_valid = bus_xingIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_opcode = bus_xingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_param = bus_xingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_size = bus_xingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_source = bus_xingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_address = bus_xingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_mask = bus_xingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_data = bus_xingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_corrupt = bus_xingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_d_ready = bus_xingIn_d_ready; // @[MixedNode.scala:542:17, :551:17] TLWidthWidget16 widget ( // @[WidthWidget.scala:230:28] .clock (clock), .reset (reset), .auto_anon_in_a_ready (auto_widget_anon_in_a_ready_0), .auto_anon_in_a_valid (auto_widget_anon_in_a_valid_0), // @[LazyModuleImp.scala:138:7] .auto_anon_in_a_bits_opcode (auto_widget_anon_in_a_bits_opcode_0), // @[LazyModuleImp.scala:138:7] .auto_anon_in_a_bits_param (auto_widget_anon_in_a_bits_param_0), // @[LazyModuleImp.scala:138:7] .auto_anon_in_a_bits_size (auto_widget_anon_in_a_bits_size_0), // @[LazyModuleImp.scala:138:7] .auto_anon_in_a_bits_source (auto_widget_anon_in_a_bits_source_0), // @[LazyModuleImp.scala:138:7] .auto_anon_in_a_bits_address (auto_widget_anon_in_a_bits_address_0), // @[LazyModuleImp.scala:138:7] .auto_anon_in_a_bits_mask (auto_widget_anon_in_a_bits_mask_0), // @[LazyModuleImp.scala:138:7] .auto_anon_in_a_bits_data (auto_widget_anon_in_a_bits_data_0), // @[LazyModuleImp.scala:138:7] .auto_anon_in_a_bits_corrupt (auto_widget_anon_in_a_bits_corrupt_0), // @[LazyModuleImp.scala:138:7] .auto_anon_in_d_ready (auto_widget_anon_in_d_ready_0), // @[LazyModuleImp.scala:138:7] .auto_anon_in_d_valid (auto_widget_anon_in_d_valid_0), .auto_anon_in_d_bits_opcode (auto_widget_anon_in_d_bits_opcode_0), .auto_anon_in_d_bits_param (auto_widget_anon_in_d_bits_param_0), .auto_anon_in_d_bits_size (auto_widget_anon_in_d_bits_size_0), .auto_anon_in_d_bits_source (auto_widget_anon_in_d_bits_source_0), .auto_anon_in_d_bits_sink (auto_widget_anon_in_d_bits_sink_0), .auto_anon_in_d_bits_denied (auto_widget_anon_in_d_bits_denied_0), .auto_anon_in_d_bits_data (auto_widget_anon_in_d_bits_data_0), .auto_anon_in_d_bits_corrupt (auto_widget_anon_in_d_bits_corrupt_0), .auto_anon_out_a_ready (bus_xingIn_a_ready), // @[MixedNode.scala:551:17] .auto_anon_out_a_valid (bus_xingIn_a_valid), .auto_anon_out_a_bits_opcode (bus_xingIn_a_bits_opcode), .auto_anon_out_a_bits_param (bus_xingIn_a_bits_param), .auto_anon_out_a_bits_size (bus_xingIn_a_bits_size), .auto_anon_out_a_bits_source (bus_xingIn_a_bits_source), .auto_anon_out_a_bits_address (bus_xingIn_a_bits_address), .auto_anon_out_a_bits_mask (bus_xingIn_a_bits_mask), .auto_anon_out_a_bits_data (bus_xingIn_a_bits_data), .auto_anon_out_a_bits_corrupt (bus_xingIn_a_bits_corrupt), .auto_anon_out_d_ready (bus_xingIn_d_ready), .auto_anon_out_d_valid (bus_xingIn_d_valid), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_opcode (bus_xingIn_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_param (bus_xingIn_d_bits_param), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_size (bus_xingIn_d_bits_size), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_source (bus_xingIn_d_bits_source), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_sink (bus_xingIn_d_bits_sink), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_denied (bus_xingIn_d_bits_denied), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_data (bus_xingIn_d_bits_data), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_corrupt (bus_xingIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[WidthWidget.scala:230:28] assign auto_widget_anon_in_a_ready = auto_widget_anon_in_a_ready_0; // @[LazyModuleImp.scala:138:7] assign auto_widget_anon_in_d_valid = auto_widget_anon_in_d_valid_0; // @[LazyModuleImp.scala:138:7] assign auto_widget_anon_in_d_bits_opcode = auto_widget_anon_in_d_bits_opcode_0; // @[LazyModuleImp.scala:138:7] assign auto_widget_anon_in_d_bits_param = auto_widget_anon_in_d_bits_param_0; // @[LazyModuleImp.scala:138:7] assign auto_widget_anon_in_d_bits_size = auto_widget_anon_in_d_bits_size_0; // @[LazyModuleImp.scala:138:7] assign auto_widget_anon_in_d_bits_source = auto_widget_anon_in_d_bits_source_0; // @[LazyModuleImp.scala:138:7] assign auto_widget_anon_in_d_bits_sink = auto_widget_anon_in_d_bits_sink_0; // @[LazyModuleImp.scala:138:7] assign auto_widget_anon_in_d_bits_denied = auto_widget_anon_in_d_bits_denied_0; // @[LazyModuleImp.scala:138:7] assign auto_widget_anon_in_d_bits_data = auto_widget_anon_in_d_bits_data_0; // @[LazyModuleImp.scala:138:7] assign auto_widget_anon_in_d_bits_corrupt = auto_widget_anon_in_d_bits_corrupt_0; // @[LazyModuleImp.scala:138:7] assign auto_bus_xing_out_a_valid = auto_bus_xing_out_a_valid_0; // @[LazyModuleImp.scala:138:7] assign auto_bus_xing_out_a_bits_opcode = auto_bus_xing_out_a_bits_opcode_0; // @[LazyModuleImp.scala:138:7] assign auto_bus_xing_out_a_bits_param = auto_bus_xing_out_a_bits_param_0; // @[LazyModuleImp.scala:138:7] assign auto_bus_xing_out_a_bits_size = auto_bus_xing_out_a_bits_size_0; // @[LazyModuleImp.scala:138:7] assign auto_bus_xing_out_a_bits_source = auto_bus_xing_out_a_bits_source_0; // @[LazyModuleImp.scala:138:7] assign auto_bus_xing_out_a_bits_address = auto_bus_xing_out_a_bits_address_0; // @[LazyModuleImp.scala:138:7] assign auto_bus_xing_out_a_bits_mask = auto_bus_xing_out_a_bits_mask_0; // @[LazyModuleImp.scala:138:7] assign auto_bus_xing_out_a_bits_data = auto_bus_xing_out_a_bits_data_0; // @[LazyModuleImp.scala:138:7] assign auto_bus_xing_out_a_bits_corrupt = auto_bus_xing_out_a_bits_corrupt_0; // @[LazyModuleImp.scala:138:7] assign auto_bus_xing_out_d_ready = auto_bus_xing_out_d_ready_0; // @[LazyModuleImp.scala:138:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{ AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry, IdRange, RegionType, TransferSizes } import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions} import freechips.rocketchip.util.{ AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase, CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct } import scala.math.max //These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel case class TLMasterToSlaveTransferSizes( // Supports both Acquire+Release of the following two sizes: acquireT: TransferSizes = TransferSizes.none, acquireB: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none) extends TLCommonTransferSizes { def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .intersect(rhs.acquireT), acquireB = acquireB .intersect(rhs.acquireB), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint)) def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .mincover(rhs.acquireT), acquireB = acquireB .mincover(rhs.acquireB), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint)) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(acquireT, "T"), str(acquireB, "B"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""acquireT = ${acquireT} \|acquireB = ${acquireB} \|arithmetic = ${arithmetic} \|logical = ${logical} \|get = ${get} \|putFull = ${putFull} \|putPartial = ${putPartial} \|hint = ${hint} \| \|""".stripMargin } } object TLMasterToSlaveTransferSizes { def unknownEmits = TLMasterToSlaveTransferSizes( acquireT = TransferSizes(1, 4096), acquireB = TransferSizes(1, 4096), arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096)) def unknownSupports = TLMasterToSlaveTransferSizes() } //These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel case class TLSlaveToMasterTransferSizes( probe: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none ) extends TLCommonTransferSizes { def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .intersect(rhs.probe), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint) ) def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .mincover(rhs.probe), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint) ) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(probe, "P"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""probe = ${probe} \|arithmetic = ${arithmetic} \|logical = ${logical} \|get = ${get} \|putFull = ${putFull} \|putPartial = ${putPartial} \|hint = ${hint} \| \|""".stripMargin } } object TLSlaveToMasterTransferSizes { def unknownEmits = TLSlaveToMasterTransferSizes( arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096), probe = TransferSizes(1, 4096)) def unknownSupports = TLSlaveToMasterTransferSizes() } trait TLCommonTransferSizes { def arithmetic: TransferSizes def logical: TransferSizes def get: TransferSizes def putFull: TransferSizes def putPartial: TransferSizes def hint: TransferSizes } class TLSlaveParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], setName: Option[String], val address: Seq[AddressSet], val regionType: RegionType.T, val executable: Boolean, val fifoId: Option[Int], val supports: TLMasterToSlaveTransferSizes, val emits: TLSlaveToMasterTransferSizes, // By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation) val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData // If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order // Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck // ReleaseAck may NEVER be denied extends SimpleProduct { def sortedAddress = address.sorted override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters] override def productPrefix = "TLSlaveParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 11 def productElement(n: Int): Any = n match { case 0 => name case 1 => address case 2 => resources case 3 => regionType case 4 => executable case 5 => fifoId case 6 => supports case 7 => emits case 8 => alwaysGrantsT case 9 => mayDenyGet case 10 => mayDenyPut case _ => throw new IndexOutOfBoundsException(n.toString) } def supportsAcquireT: TransferSizes = supports.acquireT def supportsAcquireB: TransferSizes = supports.acquireB def supportsArithmetic: TransferSizes = supports.arithmetic def supportsLogical: TransferSizes = supports.logical def supportsGet: TransferSizes = supports.get def supportsPutFull: TransferSizes = supports.putFull def supportsPutPartial: TransferSizes = supports.putPartial def supportsHint: TransferSizes = supports.hint require (!address.isEmpty, "Address cannot be empty") address.foreach { a => require (a.finite, "Address must be finite") } address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)") require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)") require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)") require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)") require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)") require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)") require (!alwaysGrantsT \|\| supportsAcquireT, s"Must supportAcquireT if promising to always grantT") // Make sure that the regionType agrees with the capabilities require (!supportsAcquireB \|\| regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached require (regionType <= RegionType.UNCACHED \|\| supportsAcquireB) // tracked, cached -> acquire require (regionType != RegionType.UNCACHED \|\| supportsGet) // uncached -> supportsGet val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected") val maxTransfer = List( // Largest supported transfer of all types supportsAcquireT.max, supportsAcquireB.max, supportsArithmetic.max, supportsLogical.max, supportsGet.max, supportsPutFull.max, supportsPutPartial.max).max val maxAddress = address.map(_.max).max val minAlignment = address.map(_.alignment).min // The device had better not support a transfer larger than its alignment require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)") def toResource: ResourceAddress = { ResourceAddress(address, ResourcePermissions( r = supportsAcquireB \|\| supportsGet, w = supportsAcquireT \|\| supportsPutFull, x = executable, c = supportsAcquireB, a = supportsArithmetic && supportsLogical)) } def findTreeViolation() = nodePath.find { case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false case _: SinkNode[_, _, _, _, _] => false case node => node.inputs.size != 1 } def isTree = findTreeViolation() == None def infoString = { s"""Slave Name = ${name} \|Slave Address = ${address} \|supports = ${supports.infoString} \| \|""".stripMargin } def v1copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { new TLSlaveParameters( setName = setName, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = emits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: Option[String] = setName, address: Seq[AddressSet] = address, regionType: RegionType.T = regionType, executable: Boolean = executable, fifoId: Option[Int] = fifoId, supports: TLMasterToSlaveTransferSizes = supports, emits: TLSlaveToMasterTransferSizes = emits, alwaysGrantsT: Boolean = alwaysGrantsT, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } @deprecated("Use v1copy instead of copy","") def copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { v1copy( address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supportsAcquireT = supportsAcquireT, supportsAcquireB = supportsAcquireB, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } } object TLSlaveParameters { def v1( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = { new TLSlaveParameters( setName = None, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLSlaveToMasterTransferSizes.unknownEmits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2( address: Seq[AddressSet], nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Seq(), name: Option[String] = None, regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, fifoId: Option[Int] = None, supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports, emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits, alwaysGrantsT: Boolean = false, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } } object TLManagerParameters { @deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","") def apply( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = TLSlaveParameters.v1( address, resources, regionType, executable, nodePath, supportsAcquireT, supportsAcquireB, supportsArithmetic, supportsLogical, supportsGet, supportsPutFull, supportsPutPartial, supportsHint, mayDenyGet, mayDenyPut, alwaysGrantsT, fifoId, ) } case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int]) { def members = Seq(a, b, c, d) members.collect { case Some(beatBytes) => require (isPow2(beatBytes), "Data channel width must be a power of 2") } } object TLChannelBeatBytes{ def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes( Some(beatBytes), Some(beatBytes), Some(beatBytes), Some(beatBytes)) def apply(): TLChannelBeatBytes = TLChannelBeatBytes( None, None, None, None) } class TLSlavePortParameters private( val slaves: Seq[TLSlaveParameters], val channelBytes: TLChannelBeatBytes, val endSinkId: Int, val minLatency: Int, val responseFields: Seq[BundleFieldBase], val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct { def sortedSlaves = slaves.sortBy(_.sortedAddress.head) override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters] override def productPrefix = "TLSlavePortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => slaves case 1 => channelBytes case 2 => endSinkId case 3 => minLatency case 4 => responseFields case 5 => requestKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!slaves.isEmpty, "Slave ports must have slaves") require (endSinkId >= 0, "Sink ids cannot be negative") require (minLatency >= 0, "Minimum required latency cannot be negative") // Using this API implies you cannot handle mixed-width busses def beatBytes = { channelBytes.members.foreach { width => require (width.isDefined && width == channelBytes.a) } channelBytes.a.get } // TODO this should be deprecated def managers = slaves def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = { val relevant = slaves.filter(m => policy(m)) relevant.foreach { m => require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ") } } // Bounds on required sizes def maxAddress = slaves.map(_.maxAddress).max def maxTransfer = slaves.map(_.maxTransfer).max def mayDenyGet = slaves.exists(_.mayDenyGet) def mayDenyPut = slaves.exists(_.mayDenyPut) // Diplomatically determined operation sizes emitted by all outward Slaves // as opposed to emits which generate circuitry to check which specific addresses val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _) // Operation Emitted by at least one outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _) val allSupportAcquireT = allSupportClaims.acquireT val allSupportAcquireB = allSupportClaims.acquireB val allSupportArithmetic = allSupportClaims.arithmetic val allSupportLogical = allSupportClaims.logical val allSupportGet = allSupportClaims.get val allSupportPutFull = allSupportClaims.putFull val allSupportPutPartial = allSupportClaims.putPartial val allSupportHint = allSupportClaims.hint // Operation supported by at least one outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _) val anySupportAcquireT = !anySupportClaims.acquireT.none val anySupportAcquireB = !anySupportClaims.acquireB.none val anySupportArithmetic = !anySupportClaims.arithmetic.none val anySupportLogical = !anySupportClaims.logical.none val anySupportGet = !anySupportClaims.get.none val anySupportPutFull = !anySupportClaims.putFull.none val anySupportPutPartial = !anySupportClaims.putPartial.none val anySupportHint = !anySupportClaims.hint.none // Supporting Acquire means being routable for GrantAck require ((endSinkId == 0) == !anySupportAcquireB) // These return Option[TLSlaveParameters] for your convenience def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address))) // The safe version will check the entire address def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ \|\| _))) // The fast version assumes the address is valid (you probably want fastProperty instead of this function) def findFast(address: UInt) = { val routingMask = AddressDecoder(slaves.map(_.address)) VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ \|\| _))) } // Compute the simplest AddressSets that decide a key def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = { val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) => k -> vs.flatMap(_._2) } val reductionMask = AddressDecoder(groups.map(_._2)) groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) } } // Select a property def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D = Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_\|\|_), d(v)) }) // Note: returns the actual fifoId + 1 or 0 if None def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U) def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B) // Does this Port manage this ID/address? def containsSafe(address: UInt) = findSafe(address).reduce(_ \|\| _) private def addressHelper( // setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity safe: Boolean, // member filters out the sizes being checked based on the opcode being emitted or supported member: TLSlaveParameters => TransferSizes, address: UInt, lgSize: UInt, // range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity range: Option[TransferSizes]): Bool = { // trim reduces circuit complexity by intersecting checked sizes with the range argument def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x) // groupBy returns an unordered map, convert back to Seq and sort the result for determinism // groupByIntoSeq is turning slaves into trimmed membership sizes // We are grouping all the slaves by their transfer size where // if they support the trimmed size then // member is the type of transfer that you are looking for (What you are trying to filter on) // When you consider membership, you are trimming the sizes to only the ones that you care about // you are filtering the slaves based on both whether they support a particular opcode and the size // Grouping the slaves based on the actual transfer size range they support // intersecting the range and checking their membership // FOR SUPPORTCASES instead of returning the list of slaves, // you are returning a map from transfer size to the set of // address sets that are supported for that transfer size // find all the slaves that support a certain type of operation and then group their addresses by the supported size // for every size there could be multiple address ranges // safety is a trade off between checking between all possible addresses vs only the addresses // that are known to have supported sizes // the trade off is 'checking all addresses is a more expensive circuit but will always give you // the right answer even if you give it an illegal address' // the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer // fast presumes address legality // This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies. // In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size. val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) => k -> vs.flatMap(_.address) } // safe produces a circuit that compares against all possible addresses, // whereas fast presumes that the address is legal but uses an efficient address decoder val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2)) // Simplified creates the most concise possible representation of each cases' address sets based on the mask. val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) } simplified.map { case (s, a) => // s is a size, you are checking for this size either the size of the operation is in s // We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire. ((Some(s) == range).B \|\| s.containsLg(lgSize)) && a.map(_.contains(address)).reduce(_\|\|_) }.foldLeft(false.B)(_\|\|_) } def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range) def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range) def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range) def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range) def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range) def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range) def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range) def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range) def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range) def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range) def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range) def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range) def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range) def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range) def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range) def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range) def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range) def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range) def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range) def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range) def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range) def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range) def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range) def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption def isTree = !slaves.exists(!_.isTree) def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString def v1copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = managers, channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } def v2copy( slaves: Seq[TLSlaveParameters] = slaves, channelBytes: TLChannelBeatBytes = channelBytes, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = slaves, channelBytes = channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } @deprecated("Use v1copy instead of copy","") def copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { v1copy( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } object TLSlavePortParameters { def v1( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { new TLSlavePortParameters( slaves = managers, channelBytes = TLChannelBeatBytes(beatBytes), endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } } object TLManagerPortParameters { @deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","") def apply( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { TLSlavePortParameters.v1( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } class TLMasterParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], val name: String, val visibility: Seq[AddressSet], val unusedRegionTypes: Set[RegionType.T], val executesOnly: Boolean, val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C. val supports: TLSlaveToMasterTransferSizes, val emits: TLMasterToSlaveTransferSizes, val neverReleasesData: Boolean, val sourceId: IdRange) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters] override def productPrefix = "TLMasterParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 10 def productElement(n: Int): Any = n match { case 0 => name case 1 => sourceId case 2 => resources case 3 => visibility case 4 => unusedRegionTypes case 5 => executesOnly case 6 => requestFifo case 7 => supports case 8 => emits case 9 => neverReleasesData case _ => throw new IndexOutOfBoundsException(n.toString) } require (!sourceId.isEmpty) require (!visibility.isEmpty) require (supports.putFull.contains(supports.putPartial)) // We only support these operations if we support Probe (ie: we're a cache) require (supports.probe.contains(supports.arithmetic)) require (supports.probe.contains(supports.logical)) require (supports.probe.contains(supports.get)) require (supports.probe.contains(supports.putFull)) require (supports.probe.contains(supports.putPartial)) require (supports.probe.contains(supports.hint)) visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } val maxTransfer = List( supports.probe.max, supports.arithmetic.max, supports.logical.max, supports.get.max, supports.putFull.max, supports.putPartial.max).max def infoString = { s"""Master Name = ${name} \|visibility = ${visibility} \|emits = ${emits.infoString} \|sourceId = ${sourceId} \| \|""".stripMargin } def v1copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { new TLMasterParameters( nodePath = nodePath, resources = this.resources, name = name, visibility = visibility, unusedRegionTypes = this.unusedRegionTypes, executesOnly = this.executesOnly, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = this.emits, neverReleasesData = this.neverReleasesData, sourceId = sourceId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: String = name, visibility: Seq[AddressSet] = visibility, unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes, executesOnly: Boolean = executesOnly, requestFifo: Boolean = requestFifo, supports: TLSlaveToMasterTransferSizes = supports, emits: TLMasterToSlaveTransferSizes = emits, neverReleasesData: Boolean = neverReleasesData, sourceId: IdRange = sourceId) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } @deprecated("Use v1copy instead of copy","") def copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { v1copy( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } object TLMasterParameters { def v1( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { new TLMasterParameters( nodePath = nodePath, resources = Nil, name = name, visibility = visibility, unusedRegionTypes = Set(), executesOnly = false, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData = false, sourceId = sourceId) } def v2( nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Nil, name: String, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), unusedRegionTypes: Set[RegionType.T] = Set(), executesOnly: Boolean = false, requestFifo: Boolean = false, supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports, emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData: Boolean = false, sourceId: IdRange = IdRange(0,1)) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } } object TLClientParameters { @deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","") def apply( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet.everything), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { TLMasterParameters.v1( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } class TLMasterPortParameters private( val masters: Seq[TLMasterParameters], val channelBytes: TLChannelBeatBytes, val minLatency: Int, val echoFields: Seq[BundleFieldBase], val requestFields: Seq[BundleFieldBase], val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters] override def productPrefix = "TLMasterPortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => masters case 1 => channelBytes case 2 => minLatency case 3 => echoFields case 4 => requestFields case 5 => responseKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!masters.isEmpty) require (minLatency >= 0) def clients = masters // Require disjoint ranges for Ids IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) => require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}") } // Bounds on required sizes def endSourceId = masters.map(_.sourceId.end).max def maxTransfer = masters.map(_.maxTransfer).max // The unused sources < endSourceId def unusedSources: Seq[Int] = { val usedSources = masters.map(_.sourceId).sortBy(_.start) ((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) => end until start } } // Diplomatically determined operation sizes emitted by all inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = masters.map(_.emits).reduce( _ intersect _) // Diplomatically determined operation sizes Emitted by at least one inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all inward Masters // as opposed to supports* which generate circuitry to check which specific addresses val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _) val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _) val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _) val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _) val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _) val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _) val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _) // Diplomatically determined operation sizes supported by at least one master // as opposed to supports* which generate circuitry to check which specific addresses val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ \|\| _) val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ \|\| _) val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ \|\| _) val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ \|\| _) val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ \|\| _) val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ \|\| _) val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ \|\| _) // These return Option[TLMasterParameters] for your convenience def find(id: Int) = masters.find(_.sourceId.contains(id)) // Synthesizable lookup methods def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id))) def contains(id: UInt) = find(id).reduce(_ \|\| _) def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B)) // Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = { val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _) // this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version; // the case where there is only one group. if (allSame) member(masters(0)).containsLg(lgSize) else { // Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize Mux1H(find(id), masters.map(member(_).containsLg(lgSize))) } } // Check for support of a given operation at a specific id val supportsProbe = sourceIdHelper(_.supports.probe) _ val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _ val supportsLogical = sourceIdHelper(_.supports.logical) _ val supportsGet = sourceIdHelper(_.supports.get) _ val supportsPutFull = sourceIdHelper(_.supports.putFull) _ val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _ val supportsHint = sourceIdHelper(_.supports.hint) _ // TODO: Merge sourceIdHelper2 with sourceIdHelper private def sourceIdHelper2( member: TLMasterParameters => TransferSizes, sourceId: UInt, lgSize: UInt): Bool = { // Because sourceIds are uniquely owned by each master, we use them to group the // cases that have to be checked. val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) => k -> vs.map(_.sourceId) } emitCases.map { case (s, a) => (s.containsLg(lgSize)) && a.map(_.contains(sourceId)).reduce(_\|\|_) }.foldLeft(false.B)(_\|\|_) } // Check for emit of a given operation at a specific id def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize) def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize) def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize) def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize) def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize) def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize) def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize) def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize) def infoString = masters.map(_.infoString).mkString def v1copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = clients, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2copy( masters: Seq[TLMasterParameters] = masters, channelBytes: TLChannelBeatBytes = channelBytes, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } @deprecated("Use v1copy instead of copy","") def copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { v1copy( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLClientPortParameters { @deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","") def apply( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { TLMasterPortParameters.v1( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLMasterPortParameters { def v1( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = clients, channelBytes = TLChannelBeatBytes(), minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2( masters: Seq[TLMasterParameters], channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(), minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } } case class TLBundleParameters( addressBits: Int, dataBits: Int, sourceBits: Int, sinkBits: Int, sizeBits: Int, echoFields: Seq[BundleFieldBase], requestFields: Seq[BundleFieldBase], responseFields: Seq[BundleFieldBase], hasBCE: Boolean) { // Chisel has issues with 0-width wires require (addressBits >= 1) require (dataBits >= 8) require (sourceBits >= 1) require (sinkBits >= 1) require (sizeBits >= 1) require (isPow2(dataBits)) echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") } val addrLoBits = log2Up(dataBits/8) // Used to uniquify bus IP names def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u") def union(x: TLBundleParameters) = TLBundleParameters( max(addressBits, x.addressBits), max(dataBits, x.dataBits), max(sourceBits, x.sourceBits), max(sinkBits, x.sinkBits), max(sizeBits, x.sizeBits), echoFields = BundleField.union(echoFields ++ x.echoFields), requestFields = BundleField.union(requestFields ++ x.requestFields), responseFields = BundleField.union(responseFields ++ x.responseFields), hasBCE \|\| x.hasBCE) } object TLBundleParameters { val emptyBundleParams = TLBundleParameters( addressBits = 1, dataBits = 8, sourceBits = 1, sinkBits = 1, sizeBits = 1, echoFields = Nil, requestFields = Nil, responseFields = Nil, hasBCE = false) def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y)) def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) = new TLBundleParameters( addressBits = log2Up(slave.maxAddress + 1), dataBits = slave.beatBytes * 8, sourceBits = log2Up(master.endSourceId), sinkBits = log2Up(slave.endSinkId), sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1), echoFields = master.echoFields, requestFields = BundleField.accept(master.requestFields, slave.requestKeys), responseFields = BundleField.accept(slave.responseFields, master.responseKeys), hasBCE = master.anySupportProbe && slave.anySupportAcquireB) } case class TLEdgeParameters( master: TLMasterPortParameters, slave: TLSlavePortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { // legacy names: def manager = slave def client = master val maxTransfer = max(master.maxTransfer, slave.maxTransfer) val maxLgSize = log2Ceil(maxTransfer) // Sanity check the link... require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})") def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims) val bundle = TLBundleParameters(master, slave) def formatEdge = master.infoString + "\n" + slave.infoString } case class TLCreditedDelay( a: CreditedDelay, b: CreditedDelay, c: CreditedDelay, d: CreditedDelay, e: CreditedDelay) { def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay( a = a + that.a, b = b + that.b, c = c + that.c, d = d + that.d, e = e + that.e) override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})" } object TLCreditedDelay { def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay) } case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString} case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val delay = client.delay + manager.delay val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters) case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base)) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } // To be unified, devices must agree on all of these terms case class ManagerUnificationKey( resources: Seq[Resource], regionType: RegionType.T, executable: Boolean, supportsAcquireT: TransferSizes, supportsAcquireB: TransferSizes, supportsArithmetic: TransferSizes, supportsLogical: TransferSizes, supportsGet: TransferSizes, supportsPutFull: TransferSizes, supportsPutPartial: TransferSizes, supportsHint: TransferSizes) object ManagerUnificationKey { def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey( resources = x.resources, regionType = x.regionType, executable = x.executable, supportsAcquireT = x.supportsAcquireT, supportsAcquireB = x.supportsAcquireB, supportsArithmetic = x.supportsArithmetic, supportsLogical = x.supportsLogical, supportsGet = x.supportsGet, supportsPutFull = x.supportsPutFull, supportsPutPartial = x.supportsPutPartial, supportsHint = x.supportsHint) } object ManagerUnification { def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = { slaves.groupBy(ManagerUnificationKey.apply).values.map { seq => val agree = seq.forall(_.fifoId == seq.head.fifoId) seq(0).v1copy( address = AddressSet.unify(seq.flatMap(_.address)), fifoId = if (agree) seq(0).fifoId else None) }.toList } } case class TLBufferParams( a: BufferParams = BufferParams.none, b: BufferParams = BufferParams.none, c: BufferParams = BufferParams.none, d: BufferParams = BufferParams.none, e: BufferParams = BufferParams.none ) extends DirectedBuffers[TLBufferParams] { def copyIn(x: BufferParams) = this.copy(b = x, d = x) def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x) def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x) } /** Pretty printing of TL source id maps / class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] { private val tlDigits = String.valueOf(tl.endSourceId-1).length() protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s" private val sorted = tl.masters.sortBy(_.sourceId) val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c => TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo) } } case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean) extends IdMapEntry { val from = tlId val to = tlId val maxTransactionsInFlight = Some(tlId.size) } File mshrs.scala: //***************************************************************************** // Ported from Rocket-Chip // See LICENSE.Berkeley and LICENSE.SiFive in Rocket-Chip for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.lsu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.tile._ import freechips.rocketchip.util._ import freechips.rocketchip.rocket._ import boom.v3.common._ import boom.v3.exu.BrUpdateInfo import boom.v3.util.{IsKilledByBranch, GetNewBrMask, BranchKillableQueue, IsOlder, UpdateBrMask, AgePriorityEncoder, WrapInc} class BoomDCacheReqInternal(implicit p: Parameters) extends BoomDCacheReq()(p) with HasL1HellaCacheParameters { // miss info val tag_match = Bool() val old_meta = new L1Metadata val way_en = UInt(nWays.W) // Used in the MSHRs val sdq_id = UInt(log2Ceil(cfg.nSDQ).W) } class BoomMSHR(implicit edge: TLEdgeOut, p: Parameters) extends BoomModule()(p) with HasL1HellaCacheParameters { val io = IO(new Bundle { val id = Input(UInt()) val req_pri_val = Input(Bool()) val req_pri_rdy = Output(Bool()) val req_sec_val = Input(Bool()) val req_sec_rdy = Output(Bool()) val clear_prefetch = Input(Bool()) val brupdate = Input(new BrUpdateInfo) val exception = Input(Bool()) val rob_pnr_idx = Input(UInt(robAddrSz.W)) val rob_head_idx = Input(UInt(robAddrSz.W)) val req = Input(new BoomDCacheReqInternal) val req_is_probe = Input(Bool()) val idx = Output(Valid(UInt())) val way = Output(Valid(UInt())) val tag = Output(Valid(UInt())) val mem_acquire = Decoupled(new TLBundleA(edge.bundle)) val mem_grant = Flipped(Decoupled(new TLBundleD(edge.bundle))) val mem_finish = Decoupled(new TLBundleE(edge.bundle)) val prober_state = Input(Valid(UInt(coreMaxAddrBits.W))) val refill = Decoupled(new L1DataWriteReq) val meta_write = Decoupled(new L1MetaWriteReq) val meta_read = Decoupled(new L1MetaReadReq) val meta_resp = Input(Valid(new L1Metadata)) val wb_req = Decoupled(new WritebackReq(edge.bundle)) // To inform the prefetcher when we are commiting the fetch of this line val commit_val = Output(Bool()) val commit_addr = Output(UInt(coreMaxAddrBits.W)) val commit_coh = Output(new ClientMetadata) // Reading from the line buffer val lb_read = Decoupled(new LineBufferReadReq) val lb_resp = Input(UInt(encRowBits.W)) val lb_write = Decoupled(new LineBufferWriteReq) // Replays go through the cache pipeline again val replay = Decoupled(new BoomDCacheReqInternal) // Resp go straight out to the core val resp = Decoupled(new BoomDCacheResp) // Writeback unit tells us when it is done processing our wb val wb_resp = Input(Bool()) val probe_rdy = Output(Bool()) }) // TODO: Optimize this. We don't want to mess with cache during speculation // s_refill_req : Make a request for a new cache line // s_refill_resp : Store the refill response into our buffer // s_drain_rpq_loads : Drain out loads from the rpq // : If miss was misspeculated, go to s_invalid // s_wb_req : Write back the evicted cache line // s_wb_resp : Finish writing back the evicted cache line // s_meta_write_req : Write the metadata for new cache lne // s_meta_write_resp : val s_invalid :: s_refill_req :: s_refill_resp :: s_drain_rpq_loads :: s_meta_read :: s_meta_resp_1 :: s_meta_resp_2 :: s_meta_clear :: s_wb_meta_read :: s_wb_req :: s_wb_resp :: s_commit_line :: s_drain_rpq :: s_meta_write_req :: s_mem_finish_1 :: s_mem_finish_2 :: s_prefetched :: s_prefetch :: Nil = Enum(18) val state = RegInit(s_invalid) val req = Reg(new BoomDCacheReqInternal) val req_idx = req.addr(untagBits-1, blockOffBits) val req_tag = req.addr >> untagBits val req_block_addr = (req.addr >> blockOffBits) << blockOffBits val req_needs_wb = RegInit(false.B) val new_coh = RegInit(ClientMetadata.onReset) val (_, shrink_param, coh_on_clear) = req.old_meta.coh.onCacheControl(M_FLUSH) val grow_param = new_coh.onAccess(req.uop.mem_cmd)._2 val coh_on_grant = new_coh.onGrant(req.uop.mem_cmd, io.mem_grant.bits.param) // We only accept secondary misses if the original request had sufficient permissions val (cmd_requires_second_acquire, is_hit_again, _, dirtier_coh, dirtier_cmd) = new_coh.onSecondaryAccess(req.uop.mem_cmd, io.req.uop.mem_cmd) val (_, _, refill_done, refill_address_inc) = edge.addr_inc(io.mem_grant) val sec_rdy = (!cmd_requires_second_acquire && !io.req_is_probe && !state.isOneOf(s_invalid, s_meta_write_req, s_mem_finish_1, s_mem_finish_2))// Always accept secondary misses val rpq = Module(new BranchKillableQueue(new BoomDCacheReqInternal, cfg.nRPQ, u => u.uses_ldq, false)) rpq.io.brupdate := io.brupdate rpq.io.flush := io.exception assert(!(state === s_invalid && !rpq.io.empty)) rpq.io.enq.valid := ((io.req_pri_val && io.req_pri_rdy) \|\| (io.req_sec_val && io.req_sec_rdy)) && !isPrefetch(io.req.uop.mem_cmd) rpq.io.enq.bits := io.req rpq.io.deq.ready := false.B val grantack = Reg(Valid(new TLBundleE(edge.bundle))) val refill_ctr = Reg(UInt(log2Ceil(cacheDataBeats).W)) val commit_line = Reg(Bool()) val grant_had_data = Reg(Bool()) val finish_to_prefetch = Reg(Bool()) // Block probes if a tag write we started is still in the pipeline val meta_hazard = RegInit(0.U(2.W)) when (meta_hazard =/= 0.U) { meta_hazard := meta_hazard + 1.U } when (io.meta_write.fire) { meta_hazard := 1.U } io.probe_rdy := (meta_hazard === 0.U && (state.isOneOf(s_invalid, s_refill_req, s_refill_resp, s_drain_rpq_loads) \|\| (state === s_meta_read && grantack.valid))) io.idx.valid := state =/= s_invalid io.tag.valid := state =/= s_invalid io.way.valid := !state.isOneOf(s_invalid, s_prefetch) io.idx.bits := req_idx io.tag.bits := req_tag io.way.bits := req.way_en io.meta_write.valid := false.B io.meta_write.bits := DontCare io.req_pri_rdy := false.B io.req_sec_rdy := sec_rdy && rpq.io.enq.ready io.mem_acquire.valid := false.B io.mem_acquire.bits := DontCare io.refill.valid := false.B io.refill.bits := DontCare io.replay.valid := false.B io.replay.bits := DontCare io.wb_req.valid := false.B io.wb_req.bits := DontCare io.resp.valid := false.B io.resp.bits := DontCare io.commit_val := false.B io.commit_addr := req.addr io.commit_coh := coh_on_grant io.meta_read.valid := false.B io.meta_read.bits := DontCare io.mem_finish.valid := false.B io.mem_finish.bits := DontCare io.lb_write.valid := false.B io.lb_write.bits := DontCare io.lb_read.valid := false.B io.lb_read.bits := DontCare io.mem_grant.ready := false.B when (io.req_sec_val && io.req_sec_rdy) { req.uop.mem_cmd := dirtier_cmd when (is_hit_again) { new_coh := dirtier_coh } } def handle_pri_req(old_state: UInt): UInt = { val new_state = WireInit(old_state) grantack.valid := false.B refill_ctr := 0.U assert(rpq.io.enq.ready) req := io.req val old_coh = io.req.old_meta.coh req_needs_wb := old_coh.onCacheControl(M_FLUSH)._1 // does the line we are evicting need to be written back when (io.req.tag_match) { val (is_hit, _, coh_on_hit) = old_coh.onAccess(io.req.uop.mem_cmd) when (is_hit) { // set dirty bit assert(isWrite(io.req.uop.mem_cmd)) new_coh := coh_on_hit new_state := s_drain_rpq } .otherwise { // upgrade permissions new_coh := old_coh new_state := s_refill_req } } .otherwise { // refill and writeback if necessary new_coh := ClientMetadata.onReset new_state := s_refill_req } new_state } when (state === s_invalid) { io.req_pri_rdy := true.B grant_had_data := false.B when (io.req_pri_val && io.req_pri_rdy) { state := handle_pri_req(state) } } .elsewhen (state === s_refill_req) { io.mem_acquire.valid := true.B // TODO: Use AcquirePerm if just doing permissions acquire io.mem_acquire.bits := edge.AcquireBlock( fromSource = io.id, toAddress = Cat(req_tag, req_idx) << blockOffBits, lgSize = lgCacheBlockBytes.U, growPermissions = grow_param)._2 when (io.mem_acquire.fire) { state := s_refill_resp } } .elsewhen (state === s_refill_resp) { when (edge.hasData(io.mem_grant.bits)) { io.mem_grant.ready := io.lb_write.ready io.lb_write.valid := io.mem_grant.valid io.lb_write.bits.id := io.id io.lb_write.bits.offset := refill_address_inc >> rowOffBits io.lb_write.bits.data := io.mem_grant.bits.data } .otherwise { io.mem_grant.ready := true.B } when (io.mem_grant.fire) { grant_had_data := edge.hasData(io.mem_grant.bits) } when (refill_done) { grantack.valid := edge.isRequest(io.mem_grant.bits) grantack.bits := edge.GrantAck(io.mem_grant.bits) state := Mux(grant_had_data, s_drain_rpq_loads, s_drain_rpq) assert(!(!grant_had_data && req_needs_wb)) commit_line := false.B new_coh := coh_on_grant } } .elsewhen (state === s_drain_rpq_loads) { val drain_load = (isRead(rpq.io.deq.bits.uop.mem_cmd) && !isWrite(rpq.io.deq.bits.uop.mem_cmd) && (rpq.io.deq.bits.uop.mem_cmd =/= M_XLR)) // LR should go through replay // drain all loads for now val rp_addr = Cat(req_tag, req_idx, rpq.io.deq.bits.addr(blockOffBits-1,0)) val word_idx = if (rowWords == 1) 0.U else rp_addr(log2Up(rowWordscoreDataBytes)-1, log2Up(wordBytes)) val data = io.lb_resp val data_word = data >> Cat(word_idx, 0.U(log2Up(coreDataBits).W)) val loadgen = new LoadGen(rpq.io.deq.bits.uop.mem_size, rpq.io.deq.bits.uop.mem_signed, Cat(req_tag, req_idx, rpq.io.deq.bits.addr(blockOffBits-1,0)), data_word, false.B, wordBytes) rpq.io.deq.ready := io.resp.ready && io.lb_read.ready && drain_load io.lb_read.valid := rpq.io.deq.valid && drain_load io.lb_read.bits.id := io.id io.lb_read.bits.offset := rpq.io.deq.bits.addr >> rowOffBits io.resp.valid := rpq.io.deq.valid && io.lb_read.fire && drain_load io.resp.bits.uop := rpq.io.deq.bits.uop io.resp.bits.data := loadgen.data io.resp.bits.is_hella := rpq.io.deq.bits.is_hella when (rpq.io.deq.fire) { commit_line := true.B } .elsewhen (rpq.io.empty && !commit_line) { when (!rpq.io.enq.fire) { state := s_mem_finish_1 finish_to_prefetch := enablePrefetching.B } } .elsewhen (rpq.io.empty \|\| (rpq.io.deq.valid && !drain_load)) { // io.commit_val is for the prefetcher. it tells the prefetcher that this line was correctly acquired // The prefetcher should consider fetching the next line io.commit_val := true.B state := s_meta_read } } .elsewhen (state === s_meta_read) { io.meta_read.valid := !io.prober_state.valid \|\| !grantack.valid \|\| (io.prober_state.bits(untagBits-1,blockOffBits) =/= req_idx) io.meta_read.bits.idx := req_idx io.meta_read.bits.tag := req_tag io.meta_read.bits.way_en := req.way_en when (io.meta_read.fire) { state := s_meta_resp_1 } } .elsewhen (state === s_meta_resp_1) { state := s_meta_resp_2 } .elsewhen (state === s_meta_resp_2) { val needs_wb = io.meta_resp.bits.coh.onCacheControl(M_FLUSH)._1 state := Mux(!io.meta_resp.valid, s_meta_read, // Prober could have nack'd this read Mux(needs_wb, s_meta_clear, s_commit_line)) } .elsewhen (state === s_meta_clear) { io.meta_write.valid := true.B io.meta_write.bits.idx := req_idx io.meta_write.bits.data.coh := coh_on_clear io.meta_write.bits.data.tag := req_tag io.meta_write.bits.way_en := req.way_en when (io.meta_write.fire) { state := s_wb_req } } .elsewhen (state === s_wb_req) { io.wb_req.valid := true.B io.wb_req.bits.tag := req.old_meta.tag io.wb_req.bits.idx := req_idx io.wb_req.bits.param := shrink_param io.wb_req.bits.way_en := req.way_en io.wb_req.bits.source := io.id io.wb_req.bits.voluntary := true.B when (io.wb_req.fire) { state := s_wb_resp } } .elsewhen (state === s_wb_resp) { when (io.wb_resp) { state := s_commit_line } } .elsewhen (state === s_commit_line) { io.lb_read.valid := true.B io.lb_read.bits.id := io.id io.lb_read.bits.offset := refill_ctr io.refill.valid := io.lb_read.fire io.refill.bits.addr := req_block_addr \| (refill_ctr << rowOffBits) io.refill.bits.way_en := req.way_en io.refill.bits.wmask := ~(0.U(rowWords.W)) io.refill.bits.data := io.lb_resp when (io.refill.fire) { refill_ctr := refill_ctr + 1.U when (refill_ctr === (cacheDataBeats - 1).U) { state := s_drain_rpq } } } .elsewhen (state === s_drain_rpq) { io.replay <> rpq.io.deq io.replay.bits.way_en := req.way_en io.replay.bits.addr := Cat(req_tag, req_idx, rpq.io.deq.bits.addr(blockOffBits-1,0)) when (io.replay.fire && isWrite(rpq.io.deq.bits.uop.mem_cmd)) { // Set dirty bit val (is_hit, _, coh_on_hit) = new_coh.onAccess(rpq.io.deq.bits.uop.mem_cmd) assert(is_hit, "We still don't have permissions for this store") new_coh := coh_on_hit } when (rpq.io.empty && !rpq.io.enq.valid) { state := s_meta_write_req } } .elsewhen (state === s_meta_write_req) { io.meta_write.valid := true.B io.meta_write.bits.idx := req_idx io.meta_write.bits.data.coh := new_coh io.meta_write.bits.data.tag := req_tag io.meta_write.bits.way_en := req.way_en when (io.meta_write.fire) { state := s_mem_finish_1 finish_to_prefetch := false.B } } .elsewhen (state === s_mem_finish_1) { io.mem_finish.valid := grantack.valid io.mem_finish.bits := grantack.bits when (io.mem_finish.fire \|\| !grantack.valid) { grantack.valid := false.B state := s_mem_finish_2 } } .elsewhen (state === s_mem_finish_2) { state := Mux(finish_to_prefetch, s_prefetch, s_invalid) } .elsewhen (state === s_prefetch) { io.req_pri_rdy := true.B when ((io.req_sec_val && !io.req_sec_rdy) \|\| io.clear_prefetch) { state := s_invalid } .elsewhen (io.req_sec_val && io.req_sec_rdy) { val (is_hit, _, coh_on_hit) = new_coh.onAccess(io.req.uop.mem_cmd) when (is_hit) { // Proceed with refill new_coh := coh_on_hit state := s_meta_read } .otherwise { // Reacquire this line new_coh := ClientMetadata.onReset state := s_refill_req } } .elsewhen (io.req_pri_val && io.req_pri_rdy) { grant_had_data := false.B state := handle_pri_req(state) } } } class BoomIOMSHR(id: Int)(implicit edge: TLEdgeOut, p: Parameters) extends BoomModule()(p) with HasL1HellaCacheParameters { val io = IO(new Bundle { val req = Flipped(Decoupled(new BoomDCacheReq)) val resp = Decoupled(new BoomDCacheResp) val mem_access = Decoupled(new TLBundleA(edge.bundle)) val mem_ack = Flipped(Valid(new TLBundleD(edge.bundle))) // We don't need brupdate in here because uncacheable operations are guaranteed non-speculative }) def beatOffset(addr: UInt) = addr.extract(beatOffBits-1, wordOffBits) def wordFromBeat(addr: UInt, dat: UInt) = { val shift = Cat(beatOffset(addr), 0.U((wordOffBits+log2Ceil(wordBytes)).W)) (dat >> shift)(wordBits-1, 0) } val req = Reg(new BoomDCacheReq) val grant_word = Reg(UInt(wordBits.W)) val s_idle :: s_mem_access :: s_mem_ack :: s_resp :: Nil = Enum(4) val state = RegInit(s_idle) io.req.ready := state === s_idle val loadgen = new LoadGen(req.uop.mem_size, req.uop.mem_signed, req.addr, grant_word, false.B, wordBytes) val a_source = id.U val a_address = req.addr val a_size = req.uop.mem_size val a_data = Fill(beatWords, req.data) val get = edge.Get(a_source, a_address, a_size)._2 val put = edge.Put(a_source, a_address, a_size, a_data)._2 val atomics = if (edge.manager.anySupportLogical) { MuxLookup(req.uop.mem_cmd, (0.U).asTypeOf(new TLBundleA(edge.bundle)))(Array( M_XA_SWAP -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.SWAP)._2, M_XA_XOR -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.XOR) ._2, M_XA_OR -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.OR) ._2, M_XA_AND -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.AND) ._2, M_XA_ADD -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.ADD)._2, M_XA_MIN -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.MIN)._2, M_XA_MAX -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.MAX)._2, M_XA_MINU -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.MINU)._2, M_XA_MAXU -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.MAXU)._2)) } else { // If no managers support atomics, assert fail if processor asks for them assert(state === s_idle \|\| !isAMO(req.uop.mem_cmd)) (0.U).asTypeOf(new TLBundleA(edge.bundle)) } assert(state === s_idle \|\| req.uop.mem_cmd =/= M_XSC) io.mem_access.valid := state === s_mem_access io.mem_access.bits := Mux(isAMO(req.uop.mem_cmd), atomics, Mux(isRead(req.uop.mem_cmd), get, put)) val send_resp = isRead(req.uop.mem_cmd) io.resp.valid := (state === s_resp) && send_resp io.resp.bits.is_hella := req.is_hella io.resp.bits.uop := req.uop io.resp.bits.data := loadgen.data when (io.req.fire) { req := io.req.bits state := s_mem_access } when (io.mem_access.fire) { state := s_mem_ack } when (state === s_mem_ack && io.mem_ack.valid) { state := s_resp when (isRead(req.uop.mem_cmd)) { grant_word := wordFromBeat(req.addr, io.mem_ack.bits.data) } } when (state === s_resp) { when (!send_resp \|\| io.resp.fire) { state := s_idle } } } class LineBufferReadReq(implicit p: Parameters) extends BoomBundle()(p) with HasL1HellaCacheParameters { val id = UInt(log2Ceil(nLBEntries).W) val offset = UInt(log2Ceil(cacheDataBeats).W) def lb_addr = Cat(id, offset) } class LineBufferWriteReq(implicit p: Parameters) extends LineBufferReadReq()(p) { val data = UInt(encRowBits.W) } class LineBufferMetaWriteReq(implicit p: Parameters) extends BoomBundle()(p) { val id = UInt(log2Ceil(nLBEntries).W) val coh = new ClientMetadata val addr = UInt(coreMaxAddrBits.W) } class LineBufferMeta(implicit p: Parameters) extends BoomBundle()(p) with HasL1HellaCacheParameters { val coh = new ClientMetadata val addr = UInt(coreMaxAddrBits.W) } class BoomMSHRFile(implicit edge: TLEdgeOut, p: Parameters) extends BoomModule()(p) with HasL1HellaCacheParameters { val io = IO(new Bundle { val req = Flipped(Vec(memWidth, Decoupled(new BoomDCacheReqInternal))) // Req from s2 of DCache pipe val req_is_probe = Input(Vec(memWidth, Bool())) val resp = Decoupled(new BoomDCacheResp) val secondary_miss = Output(Vec(memWidth, Bool())) val block_hit = Output(Vec(memWidth, Bool())) val brupdate = Input(new BrUpdateInfo) val exception = Input(Bool()) val rob_pnr_idx = Input(UInt(robAddrSz.W)) val rob_head_idx = Input(UInt(robAddrSz.W)) val mem_acquire = Decoupled(new TLBundleA(edge.bundle)) val mem_grant = Flipped(Decoupled(new TLBundleD(edge.bundle))) val mem_finish = Decoupled(new TLBundleE(edge.bundle)) val refill = Decoupled(new L1DataWriteReq) val meta_write = Decoupled(new L1MetaWriteReq) val meta_read = Decoupled(new L1MetaReadReq) val meta_resp = Input(Valid(new L1Metadata)) val replay = Decoupled(new BoomDCacheReqInternal) val prefetch = Decoupled(new BoomDCacheReq) val wb_req = Decoupled(new WritebackReq(edge.bundle)) val prober_state = Input(Valid(UInt(coreMaxAddrBits.W))) val clear_all = Input(Bool()) // Clears all uncommitted MSHRs to prepare for fence val wb_resp = Input(Bool()) val fence_rdy = Output(Bool()) val probe_rdy = Output(Bool()) }) val req_idx = OHToUInt(io.req.map(_.valid)) val req = io.req(req_idx) val req_is_probe = io.req_is_probe(0) for (w <- 0 until memWidth) io.req(w).ready := false.B val prefetcher: DataPrefetcher = if (enablePrefetching) Module(new NLPrefetcher) else Module(new NullPrefetcher) io.prefetch <> prefetcher.io.prefetch val cacheable = edge.manager.supportsAcquireBFast(req.bits.addr, lgCacheBlockBytes.U) // -------------------- // The MSHR SDQ val sdq_val = RegInit(0.U(cfg.nSDQ.W)) val sdq_alloc_id = PriorityEncoder(~sdq_val(cfg.nSDQ-1,0)) val sdq_rdy = !sdq_val.andR val sdq_enq = req.fire && cacheable && isWrite(req.bits.uop.mem_cmd) val sdq = Mem(cfg.nSDQ, UInt(coreDataBits.W)) when (sdq_enq) { sdq(sdq_alloc_id) := req.bits.data } // -------------------- // The LineBuffer Data // Holds refilling lines, prefetched lines val lb = Mem(nLBEntries cacheDataBeats, UInt(encRowBits.W)) val lb_read_arb = Module(new Arbiter(new LineBufferReadReq, cfg.nMSHRs)) val lb_write_arb = Module(new Arbiter(new LineBufferWriteReq, cfg.nMSHRs)) lb_read_arb.io.out.ready := false.B lb_write_arb.io.out.ready := true.B val lb_read_data = WireInit(0.U(encRowBits.W)) when (lb_write_arb.io.out.fire) { lb.write(lb_write_arb.io.out.bits.lb_addr, lb_write_arb.io.out.bits.data) } .otherwise { lb_read_arb.io.out.ready := true.B when (lb_read_arb.io.out.fire) { lb_read_data := lb.read(lb_read_arb.io.out.bits.lb_addr) } } def widthMap[T <: Data](f: Int => T) = VecInit((0 until memWidth).map(f)) val idx_matches = Wire(Vec(memWidth, Vec(cfg.nMSHRs, Bool()))) val tag_matches = Wire(Vec(memWidth, Vec(cfg.nMSHRs, Bool()))) val way_matches = Wire(Vec(memWidth, Vec(cfg.nMSHRs, Bool()))) val tag_match = widthMap(w => Mux1H(idx_matches(w), tag_matches(w))) val idx_match = widthMap(w => idx_matches(w).reduce(_\|\|_)) val way_match = widthMap(w => Mux1H(idx_matches(w), way_matches(w))) val wb_tag_list = Wire(Vec(cfg.nMSHRs, UInt(tagBits.W))) val meta_write_arb = Module(new Arbiter(new L1MetaWriteReq , cfg.nMSHRs)) val meta_read_arb = Module(new Arbiter(new L1MetaReadReq , cfg.nMSHRs)) val wb_req_arb = Module(new Arbiter(new WritebackReq(edge.bundle), cfg.nMSHRs)) val replay_arb = Module(new Arbiter(new BoomDCacheReqInternal , cfg.nMSHRs)) val resp_arb = Module(new Arbiter(new BoomDCacheResp , cfg.nMSHRs + nIOMSHRs)) val refill_arb = Module(new Arbiter(new L1DataWriteReq , cfg.nMSHRs)) val commit_vals = Wire(Vec(cfg.nMSHRs, Bool())) val commit_addrs = Wire(Vec(cfg.nMSHRs, UInt(coreMaxAddrBits.W))) val commit_cohs = Wire(Vec(cfg.nMSHRs, new ClientMetadata)) var sec_rdy = false.B io.fence_rdy := true.B io.probe_rdy := true.B io.mem_grant.ready := false.B val mshr_alloc_idx = Wire(UInt()) val pri_rdy = WireInit(false.B) val pri_val = req.valid && sdq_rdy && cacheable && !idx_match(req_idx) val mshrs = (0 until cfg.nMSHRs) map { i => val mshr = Module(new BoomMSHR) mshr.io.id := i.U(log2Ceil(cfg.nMSHRs).W) for (w <- 0 until memWidth) { idx_matches(w)(i) := mshr.io.idx.valid && mshr.io.idx.bits === io.req(w).bits.addr(untagBits-1,blockOffBits) tag_matches(w)(i) := mshr.io.tag.valid && mshr.io.tag.bits === io.req(w).bits.addr >> untagBits way_matches(w)(i) := mshr.io.way.valid && mshr.io.way.bits === io.req(w).bits.way_en } wb_tag_list(i) := mshr.io.wb_req.bits.tag mshr.io.req_pri_val := (i.U === mshr_alloc_idx) && pri_val when (i.U === mshr_alloc_idx) { pri_rdy := mshr.io.req_pri_rdy } mshr.io.req_sec_val := req.valid && sdq_rdy && tag_match(req_idx) && idx_matches(req_idx)(i) && cacheable mshr.io.req := req.bits mshr.io.req_is_probe := req_is_probe mshr.io.req.sdq_id := sdq_alloc_id // Clear because of a FENCE, a request to the same idx as a prefetched line, // a probe to that prefetched line, all mshrs are in use mshr.io.clear_prefetch := ((io.clear_all && !req.valid)\|\| (req.valid && idx_matches(req_idx)(i) && cacheable && !tag_match(req_idx)) \|\| (req_is_probe && idx_matches(req_idx)(i))) mshr.io.brupdate := io.brupdate mshr.io.exception := io.exception mshr.io.rob_pnr_idx := io.rob_pnr_idx mshr.io.rob_head_idx := io.rob_head_idx mshr.io.prober_state := io.prober_state mshr.io.wb_resp := io.wb_resp meta_write_arb.io.in(i) <> mshr.io.meta_write meta_read_arb.io.in(i) <> mshr.io.meta_read mshr.io.meta_resp := io.meta_resp wb_req_arb.io.in(i) <> mshr.io.wb_req replay_arb.io.in(i) <> mshr.io.replay refill_arb.io.in(i) <> mshr.io.refill lb_read_arb.io.in(i) <> mshr.io.lb_read mshr.io.lb_resp := lb_read_data lb_write_arb.io.in(i) <> mshr.io.lb_write commit_vals(i) := mshr.io.commit_val commit_addrs(i) := mshr.io.commit_addr commit_cohs(i) := mshr.io.commit_coh mshr.io.mem_grant.valid := false.B mshr.io.mem_grant.bits := DontCare when (io.mem_grant.bits.source === i.U) { mshr.io.mem_grant <> io.mem_grant } sec_rdy = sec_rdy \|\| (mshr.io.req_sec_rdy && mshr.io.req_sec_val) resp_arb.io.in(i) <> mshr.io.resp when (!mshr.io.req_pri_rdy) { io.fence_rdy := false.B } for (w <- 0 until memWidth) { when (!mshr.io.probe_rdy && idx_matches(w)(i) && io.req_is_probe(w)) { io.probe_rdy := false.B } } mshr } // Try to round-robin the MSHRs val mshr_head = RegInit(0.U(log2Ceil(cfg.nMSHRs).W)) mshr_alloc_idx := RegNext(AgePriorityEncoder(mshrs.map(m=>m.io.req_pri_rdy), mshr_head)) when (pri_rdy && pri_val) { mshr_head := WrapInc(mshr_head, cfg.nMSHRs) } io.meta_write <> meta_write_arb.io.out io.meta_read <> meta_read_arb.io.out io.wb_req <> wb_req_arb.io.out val mmio_alloc_arb = Module(new Arbiter(Bool(), nIOMSHRs)) var mmio_rdy = false.B val mmios = (0 until nIOMSHRs) map { i => val id = cfg.nMSHRs + 1 + i // +1 for wb unit val mshr = Module(new BoomIOMSHR(id)) mmio_alloc_arb.io.in(i).valid := mshr.io.req.ready mmio_alloc_arb.io.in(i).bits := DontCare mshr.io.req.valid := mmio_alloc_arb.io.in(i).ready mshr.io.req.bits := req.bits mmio_rdy = mmio_rdy \|\| mshr.io.req.ready mshr.io.mem_ack.bits := io.mem_grant.bits mshr.io.mem_ack.valid := io.mem_grant.valid && io.mem_grant.bits.source === id.U when (io.mem_grant.bits.source === id.U) { io.mem_grant.ready := true.B } resp_arb.io.in(cfg.nMSHRs + i) <> mshr.io.resp when (!mshr.io.req.ready) { io.fence_rdy := false.B } mshr } mmio_alloc_arb.io.out.ready := req.valid && !cacheable TLArbiter.lowestFromSeq(edge, io.mem_acquire, mshrs.map(_.io.mem_acquire) ++ mmios.map(_.io.mem_access)) TLArbiter.lowestFromSeq(edge, io.mem_finish, mshrs.map(_.io.mem_finish)) val respq = Module(new BranchKillableQueue(new BoomDCacheResp, 4, u => u.uses_ldq, flow = false)) respq.io.brupdate := io.brupdate respq.io.flush := io.exception respq.io.enq <> resp_arb.io.out io.resp <> respq.io.deq for (w <- 0 until memWidth) { io.req(w).ready := (w.U === req_idx) && Mux(!cacheable, mmio_rdy, sdq_rdy && Mux(idx_match(w), tag_match(w) && sec_rdy, pri_rdy)) io.secondary_miss(w) := idx_match(w) && way_match(w) && !tag_match(w) io.block_hit(w) := idx_match(w) && tag_match(w) } io.refill <> refill_arb.io.out val free_sdq = io.replay.fire && isWrite(io.replay.bits.uop.mem_cmd) io.replay <> replay_arb.io.out io.replay.bits.data := sdq(replay_arb.io.out.bits.sdq_id) when (io.replay.valid \|\| sdq_enq) { sdq_val := sdq_val & ~(UIntToOH(replay_arb.io.out.bits.sdq_id) & Fill(cfg.nSDQ, free_sdq)) \| PriorityEncoderOH(~sdq_val(cfg.nSDQ-1,0)) & Fill(cfg.nSDQ, sdq_enq) } prefetcher.io.mshr_avail := RegNext(pri_rdy) prefetcher.io.req_val := RegNext(commit_vals.reduce(_\|\|_)) prefetcher.io.req_addr := RegNext(Mux1H(commit_vals, commit_addrs)) prefetcher.io.req_coh := RegNext(Mux1H(commit_vals, commit_cohs)) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } } File AMOALU.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters class StoreGen(typ: UInt, addr: UInt, dat: UInt, maxSize: Int) { val size = Wire(UInt(log2Up(log2Up(maxSize)+1).W)) size := typ val dat_padded = dat.pad(maxSize8) def misaligned: Bool = (addr & ((1.U << size) - 1.U)(log2Up(maxSize)-1,0)).orR def mask = { var res = 1.U for (i <- 0 until log2Up(maxSize)) { val upper = Mux(addr(i), res, 0.U) \| Mux(size >= (i+1).U, ((BigInt(1) << (1 << i))-1).U, 0.U) val lower = Mux(addr(i), 0.U, res) res = Cat(upper, lower) } res } protected def genData(i: Int): UInt = if (i >= log2Up(maxSize)) dat_padded else Mux(size === i.U, Fill(1 << (log2Up(maxSize)-i), dat_padded((8 << i)-1,0)), genData(i+1)) def data = genData(0) def wordData = genData(2) } class LoadGen(typ: UInt, signed: Bool, addr: UInt, dat: UInt, zero: Bool, maxSize: Int) { private val size = new StoreGen(typ, addr, dat, maxSize).size private def genData(logMinSize: Int): UInt = { var res = dat for (i <- log2Up(maxSize)-1 to logMinSize by -1) { val pos = 8 << i val shifted = Mux(addr(i), res(2pos-1,pos), res(pos-1,0)) val doZero = (i == 0).B && zero val zeroed = Mux(doZero, 0.U, shifted) res = Cat(Mux(size === i.U \|\| doZero, Fill(8maxSize-pos, signed && zeroed(pos-1)), res(8*maxSize-1,pos)), zeroed) } res } def wordData = genData(2) def data = genData(0) } class AMOALU(operandBits: Int)(implicit p: Parameters) extends Module { val minXLen = 32 val widths = (0 to log2Ceil(operandBits / minXLen)).map(minXLen << _) val io = IO(new Bundle { val mask = Input(UInt((operandBits / 8).W)) val cmd = Input(UInt(M_SZ.W)) val lhs = Input(UInt(operandBits.W)) val rhs = Input(UInt(operandBits.W)) val out = Output(UInt(operandBits.W)) val out_unmasked = Output(UInt(operandBits.W)) }) val max = io.cmd === M_XA_MAX \|\| io.cmd === M_XA_MAXU val min = io.cmd === M_XA_MIN \|\| io.cmd === M_XA_MINU val add = io.cmd === M_XA_ADD val logic_and = io.cmd === M_XA_OR \|\| io.cmd === M_XA_AND val logic_xor = io.cmd === M_XA_XOR \|\| io.cmd === M_XA_OR val adder_out = { // partition the carry chain to support sub-xLen addition val mask = ~(0.U(operandBits.W) +: widths.init.map(w => !io.mask(w/8-1) << (w-1))).reduce(_\|_) (io.lhs & mask) + (io.rhs & mask) } val less = { // break up the comparator so the lower parts will be CSE'd def isLessUnsigned(x: UInt, y: UInt, n: Int): Bool = { if (n == minXLen) x(n-1, 0) < y(n-1, 0) else x(n-1, n/2) < y(n-1, n/2) \|\| x(n-1, n/2) === y(n-1, n/2) && isLessUnsigned(x, y, n/2) } def isLess(x: UInt, y: UInt, n: Int): Bool = { val signed = { val mask = M_XA_MIN ^ M_XA_MINU (io.cmd & mask) === (M_XA_MIN & mask) } Mux(x(n-1) === y(n-1), isLessUnsigned(x, y, n), Mux(signed, x(n-1), y(n-1))) } PriorityMux(widths.reverse.map(w => (io.mask(w/8/2), isLess(io.lhs, io.rhs, w)))) } val minmax = Mux(Mux(less, min, max), io.lhs, io.rhs) val logic = Mux(logic_and, io.lhs & io.rhs, 0.U) \| Mux(logic_xor, io.lhs ^ io.rhs, 0.U) val out = Mux(add, adder_out, Mux(logic_and \|\| logic_xor, logic, minmax)) val wmask = FillInterleaved(8, io.mask) io.out := wmask & out \| ~wmask & io.lhs io.out_unmasked := out }	module BoomIOMSHR_1( // @[mshrs.scala:402:7] input clock, // @[mshrs.scala:402:7] input reset, // @[mshrs.scala:402:7] output io_req_ready, // @[mshrs.scala:405:14] input io_req_valid, // @[mshrs.scala:405:14] input [6:0] io_req_bits_uop_uopc, // @[mshrs.scala:405:14] input [31:0] io_req_bits_uop_inst, // @[mshrs.scala:405:14] input [31:0] io_req_bits_uop_debug_inst, // @[mshrs.scala:405:14] input io_req_bits_uop_is_rvc, // @[mshrs.scala:405:14] input [33:0] io_req_bits_uop_debug_pc, // @[mshrs.scala:405:14] input [2:0] io_req_bits_uop_iq_type, // @[mshrs.scala:405:14] input [9:0] io_req_bits_uop_fu_code, // @[mshrs.scala:405:14] input [3:0] io_req_bits_uop_ctrl_br_type, // @[mshrs.scala:405:14] input [1:0] io_req_bits_uop_ctrl_op1_sel, // @[mshrs.scala:405:14] input [2:0] io_req_bits_uop_ctrl_op2_sel, // @[mshrs.scala:405:14] input [2:0] io_req_bits_uop_ctrl_imm_sel, // @[mshrs.scala:405:14] input [4:0] io_req_bits_uop_ctrl_op_fcn, // @[mshrs.scala:405:14] input io_req_bits_uop_ctrl_fcn_dw, // @[mshrs.scala:405:14] input [2:0] io_req_bits_uop_ctrl_csr_cmd, // @[mshrs.scala:405:14] input io_req_bits_uop_ctrl_is_load, // @[mshrs.scala:405:14] input io_req_bits_uop_ctrl_is_sta, // @[mshrs.scala:405:14] input io_req_bits_uop_ctrl_is_std, // @[mshrs.scala:405:14] input [1:0] io_req_bits_uop_iw_state, // @[mshrs.scala:405:14] input io_req_bits_uop_iw_p1_poisoned, // @[mshrs.scala:405:14] input io_req_bits_uop_iw_p2_poisoned, // @[mshrs.scala:405:14] input io_req_bits_uop_is_br, // @[mshrs.scala:405:14] input io_req_bits_uop_is_jalr, // @[mshrs.scala:405:14] input io_req_bits_uop_is_jal, // @[mshrs.scala:405:14] input io_req_bits_uop_is_sfb, // @[mshrs.scala:405:14] input [3:0] io_req_bits_uop_br_mask, // @[mshrs.scala:405:14] input [1:0] io_req_bits_uop_br_tag, // @[mshrs.scala:405:14] input [3:0] io_req_bits_uop_ftq_idx, // @[mshrs.scala:405:14] input io_req_bits_uop_edge_inst, // @[mshrs.scala:405:14] input [5:0] io_req_bits_uop_pc_lob, // @[mshrs.scala:405:14] input io_req_bits_uop_taken, // @[mshrs.scala:405:14] input [19:0] io_req_bits_uop_imm_packed, // @[mshrs.scala:405:14] input [11:0] io_req_bits_uop_csr_addr, // @[mshrs.scala:405:14] input [5:0] io_req_bits_uop_rob_idx, // @[mshrs.scala:405:14] input [3:0] io_req_bits_uop_ldq_idx, // @[mshrs.scala:405:14] input [3:0] io_req_bits_uop_stq_idx, // @[mshrs.scala:405:14] input [1:0] io_req_bits_uop_rxq_idx, // @[mshrs.scala:405:14] input [6:0] io_req_bits_uop_pdst, // @[mshrs.scala:405:14] input [6:0] io_req_bits_uop_prs1, // @[mshrs.scala:405:14] input [6:0] io_req_bits_uop_prs2, // @[mshrs.scala:405:14] input [6:0] io_req_bits_uop_prs3, // @[mshrs.scala:405:14] input [3:0] io_req_bits_uop_ppred, // @[mshrs.scala:405:14] input io_req_bits_uop_prs1_busy, // @[mshrs.scala:405:14] input io_req_bits_uop_prs2_busy, // @[mshrs.scala:405:14] input io_req_bits_uop_prs3_busy, // @[mshrs.scala:405:14] input io_req_bits_uop_ppred_busy, // @[mshrs.scala:405:14] input [6:0] io_req_bits_uop_stale_pdst, // @[mshrs.scala:405:14] input io_req_bits_uop_exception, // @[mshrs.scala:405:14] input [63:0] io_req_bits_uop_exc_cause, // @[mshrs.scala:405:14] input io_req_bits_uop_bypassable, // @[mshrs.scala:405:14] input [4:0] io_req_bits_uop_mem_cmd, // @[mshrs.scala:405:14] input [1:0] io_req_bits_uop_mem_size, // @[mshrs.scala:405:14] input io_req_bits_uop_mem_signed, // @[mshrs.scala:405:14] input io_req_bits_uop_is_fence, // @[mshrs.scala:405:14] input io_req_bits_uop_is_fencei, // @[mshrs.scala:405:14] input io_req_bits_uop_is_amo, // @[mshrs.scala:405:14] input io_req_bits_uop_uses_ldq, // @[mshrs.scala:405:14] input io_req_bits_uop_uses_stq, // @[mshrs.scala:405:14] input io_req_bits_uop_is_sys_pc2epc, // @[mshrs.scala:405:14] input io_req_bits_uop_is_unique, // @[mshrs.scala:405:14] input io_req_bits_uop_flush_on_commit, // @[mshrs.scala:405:14] input io_req_bits_uop_ldst_is_rs1, // @[mshrs.scala:405:14] input [5:0] io_req_bits_uop_ldst, // @[mshrs.scala:405:14] input [5:0] io_req_bits_uop_lrs1, // @[mshrs.scala:405:14] input [5:0] io_req_bits_uop_lrs2, // @[mshrs.scala:405:14] input [5:0] io_req_bits_uop_lrs3, // @[mshrs.scala:405:14] input io_req_bits_uop_ldst_val, // @[mshrs.scala:405:14] input [1:0] io_req_bits_uop_dst_rtype, // @[mshrs.scala:405:14] input [1:0] io_req_bits_uop_lrs1_rtype, // @[mshrs.scala:405:14] input [1:0] io_req_bits_uop_lrs2_rtype, // @[mshrs.scala:405:14] input io_req_bits_uop_frs3_en, // @[mshrs.scala:405:14] input io_req_bits_uop_fp_val, // @[mshrs.scala:405:14] input io_req_bits_uop_fp_single, // @[mshrs.scala:405:14] input io_req_bits_uop_xcpt_pf_if, // @[mshrs.scala:405:14] input io_req_bits_uop_xcpt_ae_if, // @[mshrs.scala:405:14] input io_req_bits_uop_xcpt_ma_if, // @[mshrs.scala:405:14] input io_req_bits_uop_bp_debug_if, // @[mshrs.scala:405:14] input io_req_bits_uop_bp_xcpt_if, // @[mshrs.scala:405:14] input [1:0] io_req_bits_uop_debug_fsrc, // @[mshrs.scala:405:14] input [1:0] io_req_bits_uop_debug_tsrc, // @[mshrs.scala:405:14] input [33:0] io_req_bits_addr, // @[mshrs.scala:405:14] input [63:0] io_req_bits_data, // @[mshrs.scala:405:14] input io_req_bits_is_hella, // @[mshrs.scala:405:14] input io_resp_ready, // @[mshrs.scala:405:14] output io_resp_valid, // @[mshrs.scala:405:14] output [6:0] io_resp_bits_uop_uopc, // @[mshrs.scala:405:14] output [31:0] io_resp_bits_uop_inst, // @[mshrs.scala:405:14] output [31:0] io_resp_bits_uop_debug_inst, // @[mshrs.scala:405:14] output io_resp_bits_uop_is_rvc, // @[mshrs.scala:405:14] output [33:0] io_resp_bits_uop_debug_pc, // @[mshrs.scala:405:14] output [2:0] io_resp_bits_uop_iq_type, // @[mshrs.scala:405:14] output [9:0] io_resp_bits_uop_fu_code, // @[mshrs.scala:405:14] output [3:0] io_resp_bits_uop_ctrl_br_type, // @[mshrs.scala:405:14] output [1:0] io_resp_bits_uop_ctrl_op1_sel, // @[mshrs.scala:405:14] output [2:0] io_resp_bits_uop_ctrl_op2_sel, // @[mshrs.scala:405:14] output [2:0] io_resp_bits_uop_ctrl_imm_sel, // @[mshrs.scala:405:14] output [4:0] io_resp_bits_uop_ctrl_op_fcn, // @[mshrs.scala:405:14] output io_resp_bits_uop_ctrl_fcn_dw, // @[mshrs.scala:405:14] output [2:0] io_resp_bits_uop_ctrl_csr_cmd, // @[mshrs.scala:405:14] output io_resp_bits_uop_ctrl_is_load, // @[mshrs.scala:405:14] output io_resp_bits_uop_ctrl_is_sta, // @[mshrs.scala:405:14] output io_resp_bits_uop_ctrl_is_std, // @[mshrs.scala:405:14] output [1:0] io_resp_bits_uop_iw_state, // @[mshrs.scala:405:14] output io_resp_bits_uop_iw_p1_poisoned, // @[mshrs.scala:405:14] output io_resp_bits_uop_iw_p2_poisoned, // @[mshrs.scala:405:14] output io_resp_bits_uop_is_br, // @[mshrs.scala:405:14] output io_resp_bits_uop_is_jalr, // @[mshrs.scala:405:14] output io_resp_bits_uop_is_jal, // @[mshrs.scala:405:14] output io_resp_bits_uop_is_sfb, // @[mshrs.scala:405:14] output [3:0] io_resp_bits_uop_br_mask, // @[mshrs.scala:405:14] output [1:0] io_resp_bits_uop_br_tag, // @[mshrs.scala:405:14] output [3:0] io_resp_bits_uop_ftq_idx, // @[mshrs.scala:405:14] output io_resp_bits_uop_edge_inst, // @[mshrs.scala:405:14] output [5:0] io_resp_bits_uop_pc_lob, // @[mshrs.scala:405:14] output io_resp_bits_uop_taken, // @[mshrs.scala:405:14] output [19:0] io_resp_bits_uop_imm_packed, // @[mshrs.scala:405:14] output [11:0] io_resp_bits_uop_csr_addr, // @[mshrs.scala:405:14] output [5:0] io_resp_bits_uop_rob_idx, // @[mshrs.scala:405:14] output [3:0] io_resp_bits_uop_ldq_idx, // @[mshrs.scala:405:14] output [3:0] io_resp_bits_uop_stq_idx, // @[mshrs.scala:405:14] output [1:0] io_resp_bits_uop_rxq_idx, // @[mshrs.scala:405:14] output [6:0] io_resp_bits_uop_pdst, // @[mshrs.scala:405:14] output [6:0] io_resp_bits_uop_prs1, // @[mshrs.scala:405:14] output [6:0] io_resp_bits_uop_prs2, // @[mshrs.scala:405:14] output [6:0] io_resp_bits_uop_prs3, // @[mshrs.scala:405:14] output [3:0] io_resp_bits_uop_ppred, // @[mshrs.scala:405:14] output io_resp_bits_uop_prs1_busy, // @[mshrs.scala:405:14] output io_resp_bits_uop_prs2_busy, // @[mshrs.scala:405:14] output io_resp_bits_uop_prs3_busy, // @[mshrs.scala:405:14] output io_resp_bits_uop_ppred_busy, // @[mshrs.scala:405:14] output [6:0] io_resp_bits_uop_stale_pdst, // @[mshrs.scala:405:14] output io_resp_bits_uop_exception, // @[mshrs.scala:405:14] output [63:0] io_resp_bits_uop_exc_cause, // @[mshrs.scala:405:14] output io_resp_bits_uop_bypassable, // @[mshrs.scala:405:14] output [4:0] io_resp_bits_uop_mem_cmd, // @[mshrs.scala:405:14] output [1:0] io_resp_bits_uop_mem_size, // @[mshrs.scala:405:14] output io_resp_bits_uop_mem_signed, // @[mshrs.scala:405:14] output io_resp_bits_uop_is_fence, // @[mshrs.scala:405:14] output io_resp_bits_uop_is_fencei, // @[mshrs.scala:405:14] output io_resp_bits_uop_is_amo, // @[mshrs.scala:405:14] output io_resp_bits_uop_uses_ldq, // @[mshrs.scala:405:14] output io_resp_bits_uop_uses_stq, // @[mshrs.scala:405:14] output io_resp_bits_uop_is_sys_pc2epc, // @[mshrs.scala:405:14] output io_resp_bits_uop_is_unique, // @[mshrs.scala:405:14] output io_resp_bits_uop_flush_on_commit, // @[mshrs.scala:405:14] output io_resp_bits_uop_ldst_is_rs1, // @[mshrs.scala:405:14] output [5:0] io_resp_bits_uop_ldst, // @[mshrs.scala:405:14] output [5:0] io_resp_bits_uop_lrs1, // @[mshrs.scala:405:14] output [5:0] io_resp_bits_uop_lrs2, // @[mshrs.scala:405:14] output [5:0] io_resp_bits_uop_lrs3, // @[mshrs.scala:405:14] output io_resp_bits_uop_ldst_val, // @[mshrs.scala:405:14] output [1:0] io_resp_bits_uop_dst_rtype, // @[mshrs.scala:405:14] output [1:0] io_resp_bits_uop_lrs1_rtype, // @[mshrs.scala:405:14] output [1:0] io_resp_bits_uop_lrs2_rtype, // @[mshrs.scala:405:14] output io_resp_bits_uop_frs3_en, // @[mshrs.scala:405:14] output io_resp_bits_uop_fp_val, // @[mshrs.scala:405:14] output io_resp_bits_uop_fp_single, // @[mshrs.scala:405:14] output io_resp_bits_uop_xcpt_pf_if, // @[mshrs.scala:405:14] output io_resp_bits_uop_xcpt_ae_if, // @[mshrs.scala:405:14] output io_resp_bits_uop_xcpt_ma_if, // @[mshrs.scala:405:14] output io_resp_bits_uop_bp_debug_if, // @[mshrs.scala:405:14] output io_resp_bits_uop_bp_xcpt_if, // @[mshrs.scala:405:14] output [1:0] io_resp_bits_uop_debug_fsrc, // @[mshrs.scala:405:14] output [1:0] io_resp_bits_uop_debug_tsrc, // @[mshrs.scala:405:14] output [63:0] io_resp_bits_data, // @[mshrs.scala:405:14] output io_resp_bits_is_hella, // @[mshrs.scala:405:14] input io_mem_access_ready, // @[mshrs.scala:405:14] output io_mem_access_valid, // @[mshrs.scala:405:14] output [2:0] io_mem_access_bits_opcode, // @[mshrs.scala:405:14] output [2:0] io_mem_access_bits_param, // @[mshrs.scala:405:14] output [3:0] io_mem_access_bits_size, // @[mshrs.scala:405:14] output [3:0] io_mem_access_bits_source, // @[mshrs.scala:405:14] output [31:0] io_mem_access_bits_address, // @[mshrs.scala:405:14] output [7:0] io_mem_access_bits_mask, // @[mshrs.scala:405:14] output [63:0] io_mem_access_bits_data, // @[mshrs.scala:405:14] input io_mem_ack_valid, // @[mshrs.scala:405:14] input [2:0] io_mem_ack_bits_opcode, // @[mshrs.scala:405:14] input [1:0] io_mem_ack_bits_param, // @[mshrs.scala:405:14] input [3:0] io_mem_ack_bits_size, // @[mshrs.scala:405:14] input [3:0] io_mem_ack_bits_source, // @[mshrs.scala:405:14] input [2:0] io_mem_ack_bits_sink, // @[mshrs.scala:405:14] input io_mem_ack_bits_denied, // @[mshrs.scala:405:14] input [63:0] io_mem_ack_bits_data, // @[mshrs.scala:405:14] input io_mem_ack_bits_corrupt // @[mshrs.scala:405:14] ); wire io_req_valid_0 = io_req_valid; // @[mshrs.scala:402:7] wire [6:0] io_req_bits_uop_uopc_0 = io_req_bits_uop_uopc; // @[mshrs.scala:402:7] wire [31:0] io_req_bits_uop_inst_0 = io_req_bits_uop_inst; // @[mshrs.scala:402:7] wire [31:0] io_req_bits_uop_debug_inst_0 = io_req_bits_uop_debug_inst; // @[mshrs.scala:402:7] wire io_req_bits_uop_is_rvc_0 = io_req_bits_uop_is_rvc; // @[mshrs.scala:402:7] wire [33:0] io_req_bits_uop_debug_pc_0 = io_req_bits_uop_debug_pc; // @[mshrs.scala:402:7] wire [2:0] io_req_bits_uop_iq_type_0 = io_req_bits_uop_iq_type; // @[mshrs.scala:402:7] wire [9:0] io_req_bits_uop_fu_code_0 = io_req_bits_uop_fu_code; // @[mshrs.scala:402:7] wire [3:0] io_req_bits_uop_ctrl_br_type_0 = io_req_bits_uop_ctrl_br_type; // @[mshrs.scala:402:7] wire [1:0] io_req_bits_uop_ctrl_op1_sel_0 = io_req_bits_uop_ctrl_op1_sel; // @[mshrs.scala:402:7] wire [2:0] io_req_bits_uop_ctrl_op2_sel_0 = io_req_bits_uop_ctrl_op2_sel; // @[mshrs.scala:402:7] wire [2:0] io_req_bits_uop_ctrl_imm_sel_0 = io_req_bits_uop_ctrl_imm_sel; // @[mshrs.scala:402:7] wire [4:0] io_req_bits_uop_ctrl_op_fcn_0 = io_req_bits_uop_ctrl_op_fcn; // @[mshrs.scala:402:7] wire io_req_bits_uop_ctrl_fcn_dw_0 = io_req_bits_uop_ctrl_fcn_dw; // @[mshrs.scala:402:7] wire [2:0] io_req_bits_uop_ctrl_csr_cmd_0 = io_req_bits_uop_ctrl_csr_cmd; // @[mshrs.scala:402:7] wire io_req_bits_uop_ctrl_is_load_0 = io_req_bits_uop_ctrl_is_load; // @[mshrs.scala:402:7] wire io_req_bits_uop_ctrl_is_sta_0 = io_req_bits_uop_ctrl_is_sta; // @[mshrs.scala:402:7] wire io_req_bits_uop_ctrl_is_std_0 = io_req_bits_uop_ctrl_is_std; // @[mshrs.scala:402:7] wire [1:0] io_req_bits_uop_iw_state_0 = io_req_bits_uop_iw_state; // @[mshrs.scala:402:7] wire io_req_bits_uop_iw_p1_poisoned_0 = io_req_bits_uop_iw_p1_poisoned; // @[mshrs.scala:402:7] wire io_req_bits_uop_iw_p2_poisoned_0 = io_req_bits_uop_iw_p2_poisoned; // @[mshrs.scala:402:7] wire io_req_bits_uop_is_br_0 = io_req_bits_uop_is_br; // @[mshrs.scala:402:7] wire io_req_bits_uop_is_jalr_0 = io_req_bits_uop_is_jalr; // @[mshrs.scala:402:7] wire io_req_bits_uop_is_jal_0 = io_req_bits_uop_is_jal; // @[mshrs.scala:402:7] wire io_req_bits_uop_is_sfb_0 = io_req_bits_uop_is_sfb; // @[mshrs.scala:402:7] wire [3:0] io_req_bits_uop_br_mask_0 = io_req_bits_uop_br_mask; // @[mshrs.scala:402:7] wire [1:0] io_req_bits_uop_br_tag_0 = io_req_bits_uop_br_tag; // @[mshrs.scala:402:7] wire [3:0] io_req_bits_uop_ftq_idx_0 = io_req_bits_uop_ftq_idx; // @[mshrs.scala:402:7] wire io_req_bits_uop_edge_inst_0 = io_req_bits_uop_edge_inst; // @[mshrs.scala:402:7] wire [5:0] io_req_bits_uop_pc_lob_0 = io_req_bits_uop_pc_lob; // @[mshrs.scala:402:7] wire io_req_bits_uop_taken_0 = io_req_bits_uop_taken; // @[mshrs.scala:402:7] wire [19:0] io_req_bits_uop_imm_packed_0 = io_req_bits_uop_imm_packed; // @[mshrs.scala:402:7] wire [11:0] io_req_bits_uop_csr_addr_0 = io_req_bits_uop_csr_addr; // @[mshrs.scala:402:7] wire [5:0] io_req_bits_uop_rob_idx_0 = io_req_bits_uop_rob_idx; // @[mshrs.scala:402:7] wire [3:0] io_req_bits_uop_ldq_idx_0 = io_req_bits_uop_ldq_idx; // @[mshrs.scala:402:7] wire [3:0] io_req_bits_uop_stq_idx_0 = io_req_bits_uop_stq_idx; // @[mshrs.scala:402:7] wire [1:0] io_req_bits_uop_rxq_idx_0 = io_req_bits_uop_rxq_idx; // @[mshrs.scala:402:7] wire [6:0] io_req_bits_uop_pdst_0 = io_req_bits_uop_pdst; // @[mshrs.scala:402:7] wire [6:0] io_req_bits_uop_prs1_0 = io_req_bits_uop_prs1; // @[mshrs.scala:402:7] wire [6:0] io_req_bits_uop_prs2_0 = io_req_bits_uop_prs2; // @[mshrs.scala:402:7] wire [6:0] io_req_bits_uop_prs3_0 = io_req_bits_uop_prs3; // @[mshrs.scala:402:7] wire [3:0] io_req_bits_uop_ppred_0 = io_req_bits_uop_ppred; // @[mshrs.scala:402:7] wire io_req_bits_uop_prs1_busy_0 = io_req_bits_uop_prs1_busy; // @[mshrs.scala:402:7] wire io_req_bits_uop_prs2_busy_0 = io_req_bits_uop_prs2_busy; // @[mshrs.scala:402:7] wire io_req_bits_uop_prs3_busy_0 = io_req_bits_uop_prs3_busy; // @[mshrs.scala:402:7] wire io_req_bits_uop_ppred_busy_0 = io_req_bits_uop_ppred_busy; // @[mshrs.scala:402:7] wire [6:0] io_req_bits_uop_stale_pdst_0 = io_req_bits_uop_stale_pdst; // @[mshrs.scala:402:7] wire io_req_bits_uop_exception_0 = io_req_bits_uop_exception; // @[mshrs.scala:402:7] wire [63:0] io_req_bits_uop_exc_cause_0 = io_req_bits_uop_exc_cause; // @[mshrs.scala:402:7] wire io_req_bits_uop_bypassable_0 = io_req_bits_uop_bypassable; // @[mshrs.scala:402:7] wire [4:0] io_req_bits_uop_mem_cmd_0 = io_req_bits_uop_mem_cmd; // @[mshrs.scala:402:7] wire [1:0] io_req_bits_uop_mem_size_0 = io_req_bits_uop_mem_size; // @[mshrs.scala:402:7] wire io_req_bits_uop_mem_signed_0 = io_req_bits_uop_mem_signed; // @[mshrs.scala:402:7] wire io_req_bits_uop_is_fence_0 = io_req_bits_uop_is_fence; // @[mshrs.scala:402:7] wire io_req_bits_uop_is_fencei_0 = io_req_bits_uop_is_fencei; // @[mshrs.scala:402:7] wire io_req_bits_uop_is_amo_0 = io_req_bits_uop_is_amo; // @[mshrs.scala:402:7] wire io_req_bits_uop_uses_ldq_0 = io_req_bits_uop_uses_ldq; // @[mshrs.scala:402:7] wire io_req_bits_uop_uses_stq_0 = io_req_bits_uop_uses_stq; // @[mshrs.scala:402:7] wire io_req_bits_uop_is_sys_pc2epc_0 = io_req_bits_uop_is_sys_pc2epc; // @[mshrs.scala:402:7] wire io_req_bits_uop_is_unique_0 = io_req_bits_uop_is_unique; // @[mshrs.scala:402:7] wire io_req_bits_uop_flush_on_commit_0 = io_req_bits_uop_flush_on_commit; // @[mshrs.scala:402:7] wire io_req_bits_uop_ldst_is_rs1_0 = io_req_bits_uop_ldst_is_rs1; // @[mshrs.scala:402:7] wire [5:0] io_req_bits_uop_ldst_0 = io_req_bits_uop_ldst; // @[mshrs.scala:402:7] wire [5:0] io_req_bits_uop_lrs1_0 = io_req_bits_uop_lrs1; // @[mshrs.scala:402:7] wire [5:0] io_req_bits_uop_lrs2_0 = io_req_bits_uop_lrs2; // @[mshrs.scala:402:7] wire [5:0] io_req_bits_uop_lrs3_0 = io_req_bits_uop_lrs3; // @[mshrs.scala:402:7] wire io_req_bits_uop_ldst_val_0 = io_req_bits_uop_ldst_val; // @[mshrs.scala:402:7] wire [1:0] io_req_bits_uop_dst_rtype_0 = io_req_bits_uop_dst_rtype; // @[mshrs.scala:402:7] wire [1:0] io_req_bits_uop_lrs1_rtype_0 = io_req_bits_uop_lrs1_rtype; // @[mshrs.scala:402:7] wire [1:0] io_req_bits_uop_lrs2_rtype_0 = io_req_bits_uop_lrs2_rtype; // @[mshrs.scala:402:7] wire io_req_bits_uop_frs3_en_0 = io_req_bits_uop_frs3_en; // @[mshrs.scala:402:7] wire io_req_bits_uop_fp_val_0 = io_req_bits_uop_fp_val; // @[mshrs.scala:402:7] wire io_req_bits_uop_fp_single_0 = io_req_bits_uop_fp_single; // @[mshrs.scala:402:7] wire io_req_bits_uop_xcpt_pf_if_0 = io_req_bits_uop_xcpt_pf_if; // @[mshrs.scala:402:7] wire io_req_bits_uop_xcpt_ae_if_0 = io_req_bits_uop_xcpt_ae_if; // @[mshrs.scala:402:7] wire io_req_bits_uop_xcpt_ma_if_0 = io_req_bits_uop_xcpt_ma_if; // @[mshrs.scala:402:7] wire io_req_bits_uop_bp_debug_if_0 = io_req_bits_uop_bp_debug_if; // @[mshrs.scala:402:7] wire io_req_bits_uop_bp_xcpt_if_0 = io_req_bits_uop_bp_xcpt_if; // @[mshrs.scala:402:7] wire [1:0] io_req_bits_uop_debug_fsrc_0 = io_req_bits_uop_debug_fsrc; // @[mshrs.scala:402:7] wire [1:0] io_req_bits_uop_debug_tsrc_0 = io_req_bits_uop_debug_tsrc; // @[mshrs.scala:402:7] wire [33:0] io_req_bits_addr_0 = io_req_bits_addr; // @[mshrs.scala:402:7] wire [63:0] io_req_bits_data_0 = io_req_bits_data; // @[mshrs.scala:402:7] wire io_req_bits_is_hella_0 = io_req_bits_is_hella; // @[mshrs.scala:402:7] wire io_resp_ready_0 = io_resp_ready; // @[mshrs.scala:402:7] wire io_mem_access_ready_0 = io_mem_access_ready; // @[mshrs.scala:402:7] wire io_mem_ack_valid_0 = io_mem_ack_valid; // @[mshrs.scala:402:7] wire [2:0] io_mem_ack_bits_opcode_0 = io_mem_ack_bits_opcode; // @[mshrs.scala:402:7] wire [1:0] io_mem_ack_bits_param_0 = io_mem_ack_bits_param; // @[mshrs.scala:402:7] wire [3:0] io_mem_ack_bits_size_0 = io_mem_ack_bits_size; // @[mshrs.scala:402:7] wire [3:0] io_mem_ack_bits_source_0 = io_mem_ack_bits_source; // @[mshrs.scala:402:7] wire [2:0] io_mem_ack_bits_sink_0 = io_mem_ack_bits_sink; // @[mshrs.scala:402:7] wire io_mem_ack_bits_denied_0 = io_mem_ack_bits_denied; // @[mshrs.scala:402:7] wire [63:0] io_mem_ack_bits_data_0 = io_mem_ack_bits_data; // @[mshrs.scala:402:7] wire io_mem_ack_bits_corrupt_0 = io_mem_ack_bits_corrupt; // @[mshrs.scala:402:7] wire io_mem_access_bits_corrupt = 1'h0; // @[mshrs.scala:402:7] wire get_corrupt = 1'h0; // @[Edges.scala:460:17] wire put_corrupt = 1'h0; // @[Edges.scala:480:17] wire _atomics_WIRE_corrupt = 1'h0; // @[mshrs.scala:439:46] wire atomics_a_corrupt = 1'h0; // @[Edges.scala:534:17] wire atomics_a_1_corrupt = 1'h0; // @[Edges.scala:534:17] wire atomics_a_2_corrupt = 1'h0; // @[Edges.scala:534:17] wire atomics_a_3_corrupt = 1'h0; // @[Edges.scala:534:17] wire atomics_a_4_corrupt = 1'h0; // @[Edges.scala:517:17] wire atomics_a_5_corrupt = 1'h0; // @[Edges.scala:517:17] wire atomics_a_6_corrupt = 1'h0; // @[Edges.scala:517:17] wire atomics_a_7_corrupt = 1'h0; // @[Edges.scala:517:17] wire atomics_a_8_corrupt = 1'h0; // @[Edges.scala:517:17] wire _atomics_T_1_corrupt = 1'h0; // @[mshrs.scala:439:75] wire _atomics_T_3_corrupt = 1'h0; // @[mshrs.scala:439:75] wire _atomics_T_5_corrupt = 1'h0; // @[mshrs.scala:439:75] wire _atomics_T_7_corrupt = 1'h0; // @[mshrs.scala:439:75] wire _atomics_T_9_corrupt = 1'h0; // @[mshrs.scala:439:75] wire _atomics_T_11_corrupt = 1'h0; // @[mshrs.scala:439:75] wire _atomics_T_13_corrupt = 1'h0; // @[mshrs.scala:439:75] wire _atomics_T_15_corrupt = 1'h0; // @[mshrs.scala:439:75] wire atomics_corrupt = 1'h0; // @[mshrs.scala:439:75] wire _io_mem_access_bits_T_42_corrupt = 1'h0; // @[mshrs.scala:457:66] wire _io_mem_access_bits_T_43_corrupt = 1'h0; // @[mshrs.scala:457:29] wire io_resp_bits_data_doZero = 1'h0; // @[AMOALU.scala:43:31] wire io_resp_bits_data_doZero_1 = 1'h0; // @[AMOALU.scala:43:31] wire io_resp_bits_data_doZero_2 = 1'h0; // @[AMOALU.scala:43:31] wire [6:0] grant_word_shift = 7'h0; // @[mshrs.scala:417:20] wire [3:0] get_source = 4'h9; // @[Edges.scala:460:17] wire [3:0] put_source = 4'h9; // @[Edges.scala:480:17] wire [3:0] atomics_a_source = 4'h9; // @[Edges.scala:534:17] wire [3:0] atomics_a_1_source = 4'h9; // @[Edges.scala:534:17] wire [3:0] atomics_a_2_source = 4'h9; // @[Edges.scala:534:17] wire [3:0] atomics_a_3_source = 4'h9; // @[Edges.scala:534:17] wire [3:0] atomics_a_4_source = 4'h9; // @[Edges.scala:517:17] wire [3:0] atomics_a_5_source = 4'h9; // @[Edges.scala:517:17] wire [3:0] atomics_a_6_source = 4'h9; // @[Edges.scala:517:17] wire [3:0] atomics_a_7_source = 4'h9; // @[Edges.scala:517:17] wire [3:0] atomics_a_8_source = 4'h9; // @[Edges.scala:517:17] wire [3:0] _io_mem_access_bits_T_42_source = 4'h9; // @[mshrs.scala:457:66] wire [2:0] get_param = 3'h0; // @[Edges.scala:460:17] wire [2:0] put_opcode = 3'h0; // @[Edges.scala:480:17] wire [2:0] put_param = 3'h0; // @[Edges.scala:480:17] wire [2:0] _atomics_WIRE_opcode = 3'h0; // @[mshrs.scala:439:46] wire [2:0] _atomics_WIRE_param = 3'h0; // @[mshrs.scala:439:46] wire [2:0] atomics_a_1_param = 3'h0; // @[Edges.scala:534:17] wire [2:0] atomics_a_5_param = 3'h0; // @[Edges.scala:517:17] wire [2:0] _io_mem_access_bits_T_42_param = 3'h0; // @[mshrs.scala:457:66] wire [2:0] atomics_a_opcode = 3'h3; // @[Edges.scala:534:17] wire [2:0] atomics_a_param = 3'h3; // @[Edges.scala:534:17] wire [2:0] atomics_a_1_opcode = 3'h3; // @[Edges.scala:534:17] wire [2:0] atomics_a_2_opcode = 3'h3; // @[Edges.scala:534:17] wire [2:0] atomics_a_3_opcode = 3'h3; // @[Edges.scala:534:17] wire [2:0] atomics_a_8_param = 3'h3; // @[Edges.scala:517:17] wire [2:0] atomics_a_3_param = 3'h2; // @[Edges.scala:534:17] wire [2:0] atomics_a_4_opcode = 3'h2; // @[Edges.scala:517:17] wire [2:0] atomics_a_5_opcode = 3'h2; // @[Edges.scala:517:17] wire [2:0] atomics_a_6_opcode = 3'h2; // @[Edges.scala:517:17] wire [2:0] atomics_a_7_opcode = 3'h2; // @[Edges.scala:517:17] wire [2:0] atomics_a_7_param = 3'h2; // @[Edges.scala:517:17] wire [2:0] atomics_a_8_opcode = 3'h2; // @[Edges.scala:517:17] wire _get_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _get_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _get_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _get_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _get_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _get_legal_T_11 = 1'h1; // @[Parameters.scala:92:38] wire _get_legal_T_12 = 1'h1; // @[Parameters.scala:92:33] wire _get_legal_T_13 = 1'h1; // @[Parameters.scala:684:29] wire _put_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _put_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _put_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _put_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _put_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _put_legal_T_11 = 1'h1; // @[Parameters.scala:92:38] wire _put_legal_T_12 = 1'h1; // @[Parameters.scala:92:33] wire _put_legal_T_13 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_8 = 1'h1; // @[Parameters.scala:137:59] wire _atomics_legal_T_9 = 1'h1; // @[Parameters.scala:684:54] wire atomics_legal = 1'h1; // @[Parameters.scala:686:26] wire _atomics_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_11 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_12 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_13 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_18 = 1'h1; // @[Parameters.scala:137:59] wire _atomics_legal_T_19 = 1'h1; // @[Parameters.scala:684:54] wire atomics_legal_1 = 1'h1; // @[Parameters.scala:686:26] wire _atomics_legal_T_20 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_21 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_22 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_23 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_28 = 1'h1; // @[Parameters.scala:137:59] wire _atomics_legal_T_29 = 1'h1; // @[Parameters.scala:684:54] wire atomics_legal_2 = 1'h1; // @[Parameters.scala:686:26] wire _atomics_legal_T_30 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_31 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_32 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_33 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_38 = 1'h1; // @[Parameters.scala:137:59] wire _atomics_legal_T_39 = 1'h1; // @[Parameters.scala:684:54] wire atomics_legal_3 = 1'h1; // @[Parameters.scala:686:26] wire _atomics_legal_T_40 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_41 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_42 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_43 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_48 = 1'h1; // @[Parameters.scala:137:59] wire _atomics_legal_T_49 = 1'h1; // @[Parameters.scala:684:54] wire atomics_legal_4 = 1'h1; // @[Parameters.scala:686:26] wire _atomics_legal_T_50 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_51 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_52 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_53 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_58 = 1'h1; // @[Parameters.scala:137:59] wire _atomics_legal_T_59 = 1'h1; // @[Parameters.scala:684:54] wire atomics_legal_5 = 1'h1; // @[Parameters.scala:686:26] wire _atomics_legal_T_60 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_61 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_62 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_63 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_68 = 1'h1; // @[Parameters.scala:137:59] wire _atomics_legal_T_69 = 1'h1; // @[Parameters.scala:684:54] wire atomics_legal_6 = 1'h1; // @[Parameters.scala:686:26] wire _atomics_legal_T_70 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_71 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_72 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_73 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_78 = 1'h1; // @[Parameters.scala:137:59] wire _atomics_legal_T_79 = 1'h1; // @[Parameters.scala:684:54] wire atomics_legal_7 = 1'h1; // @[Parameters.scala:686:26] wire _atomics_legal_T_80 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_81 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_82 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_83 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_88 = 1'h1; // @[Parameters.scala:137:59] wire _atomics_legal_T_89 = 1'h1; // @[Parameters.scala:684:54] wire atomics_legal_8 = 1'h1; // @[Parameters.scala:686:26] wire [34:0] _atomics_legal_T_6 = 35'h0; // @[Parameters.scala:137:46] wire [34:0] _atomics_legal_T_7 = 35'h0; // @[Parameters.scala:137:46] wire [34:0] _atomics_legal_T_16 = 35'h0; // @[Parameters.scala:137:46] wire [34:0] _atomics_legal_T_17 = 35'h0; // @[Parameters.scala:137:46] wire [34:0] _atomics_legal_T_26 = 35'h0; // @[Parameters.scala:137:46] wire [34:0] _atomics_legal_T_27 = 35'h0; // @[Parameters.scala:137:46] wire [34:0] _atomics_legal_T_36 = 35'h0; // @[Parameters.scala:137:46] wire [34:0] _atomics_legal_T_37 = 35'h0; // @[Parameters.scala:137:46] wire [34:0] _atomics_legal_T_46 = 35'h0; // @[Parameters.scala:137:46] wire [34:0] _atomics_legal_T_47 = 35'h0; // @[Parameters.scala:137:46] wire [34:0] _atomics_legal_T_56 = 35'h0; // @[Parameters.scala:137:46] wire [34:0] _atomics_legal_T_57 = 35'h0; // @[Parameters.scala:137:46] wire [34:0] _atomics_legal_T_66 = 35'h0; // @[Parameters.scala:137:46] wire [34:0] _atomics_legal_T_67 = 35'h0; // @[Parameters.scala:137:46] wire [34:0] _atomics_legal_T_76 = 35'h0; // @[Parameters.scala:137:46] wire [34:0] _atomics_legal_T_77 = 35'h0; // @[Parameters.scala:137:46] wire [34:0] _atomics_legal_T_86 = 35'h0; // @[Parameters.scala:137:46] wire [34:0] _atomics_legal_T_87 = 35'h0; // @[Parameters.scala:137:46] wire [2:0] atomics_a_2_param = 3'h1; // @[Edges.scala:534:17] wire [2:0] atomics_a_6_param = 3'h1; // @[Edges.scala:517:17] wire [2:0] get_opcode = 3'h4; // @[Edges.scala:460:17] wire [2:0] atomics_a_4_param = 3'h4; // @[Edges.scala:517:17] wire [63:0] get_data = 64'h0; // @[Edges.scala:460:17] wire [63:0] _atomics_WIRE_data = 64'h0; // @[mshrs.scala:439:46] wire [7:0] _atomics_WIRE_mask = 8'h0; // @[mshrs.scala:439:46] wire [31:0] _atomics_WIRE_address = 32'h0; // @[mshrs.scala:439:46] wire [3:0] _atomics_WIRE_size = 4'h0; // @[mshrs.scala:439:46] wire [3:0] _atomics_WIRE_source = 4'h0; // @[mshrs.scala:439:46] wire _io_req_ready_T; // @[mshrs.scala:427:25] wire _io_resp_valid_T_1; // @[mshrs.scala:461:43] wire [63:0] _io_resp_bits_data_T_23; // @[AMOALU.scala:45:16] wire _io_mem_access_valid_T; // @[mshrs.scala:456:32] wire [2:0] _io_mem_access_bits_T_43_opcode; // @[mshrs.scala:457:29] wire [2:0] _io_mem_access_bits_T_43_param; // @[mshrs.scala:457:29] wire [3:0] _io_mem_access_bits_T_43_size; // @[mshrs.scala:457:29] wire [3:0] _io_mem_access_bits_T_43_source; // @[mshrs.scala:457:29] wire [31:0] _io_mem_access_bits_T_43_address; // @[mshrs.scala:457:29] wire [7:0] _io_mem_access_bits_T_43_mask; // @[mshrs.scala:457:29] wire [63:0] _io_mem_access_bits_T_43_data; // @[mshrs.scala:457:29] wire [63:0] _grant_word_T = io_mem_ack_bits_data_0; // @[mshrs.scala:402:7, :418:10] wire io_req_ready_0; // @[mshrs.scala:402:7] wire [3:0] io_resp_bits_uop_ctrl_br_type_0; // @[mshrs.scala:402:7] wire [1:0] io_resp_bits_uop_ctrl_op1_sel_0; // @[mshrs.scala:402:7] wire [2:0] io_resp_bits_uop_ctrl_op2_sel_0; // @[mshrs.scala:402:7] wire [2:0] io_resp_bits_uop_ctrl_imm_sel_0; // @[mshrs.scala:402:7] wire [4:0] io_resp_bits_uop_ctrl_op_fcn_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_ctrl_fcn_dw_0; // @[mshrs.scala:402:7] wire [2:0] io_resp_bits_uop_ctrl_csr_cmd_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_ctrl_is_load_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_ctrl_is_sta_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_ctrl_is_std_0; // @[mshrs.scala:402:7] wire [6:0] io_resp_bits_uop_uopc_0; // @[mshrs.scala:402:7] wire [31:0] io_resp_bits_uop_inst_0; // @[mshrs.scala:402:7] wire [31:0] io_resp_bits_uop_debug_inst_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_is_rvc_0; // @[mshrs.scala:402:7] wire [33:0] io_resp_bits_uop_debug_pc_0; // @[mshrs.scala:402:7] wire [2:0] io_resp_bits_uop_iq_type_0; // @[mshrs.scala:402:7] wire [9:0] io_resp_bits_uop_fu_code_0; // @[mshrs.scala:402:7] wire [1:0] io_resp_bits_uop_iw_state_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_iw_p1_poisoned_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_iw_p2_poisoned_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_is_br_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_is_jalr_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_is_jal_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_is_sfb_0; // @[mshrs.scala:402:7] wire [3:0] io_resp_bits_uop_br_mask_0; // @[mshrs.scala:402:7] wire [1:0] io_resp_bits_uop_br_tag_0; // @[mshrs.scala:402:7] wire [3:0] io_resp_bits_uop_ftq_idx_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_edge_inst_0; // @[mshrs.scala:402:7] wire [5:0] io_resp_bits_uop_pc_lob_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_taken_0; // @[mshrs.scala:402:7] wire [19:0] io_resp_bits_uop_imm_packed_0; // @[mshrs.scala:402:7] wire [11:0] io_resp_bits_uop_csr_addr_0; // @[mshrs.scala:402:7] wire [5:0] io_resp_bits_uop_rob_idx_0; // @[mshrs.scala:402:7] wire [3:0] io_resp_bits_uop_ldq_idx_0; // @[mshrs.scala:402:7] wire [3:0] io_resp_bits_uop_stq_idx_0; // @[mshrs.scala:402:7] wire [1:0] io_resp_bits_uop_rxq_idx_0; // @[mshrs.scala:402:7] wire [6:0] io_resp_bits_uop_pdst_0; // @[mshrs.scala:402:7] wire [6:0] io_resp_bits_uop_prs1_0; // @[mshrs.scala:402:7] wire [6:0] io_resp_bits_uop_prs2_0; // @[mshrs.scala:402:7] wire [6:0] io_resp_bits_uop_prs3_0; // @[mshrs.scala:402:7] wire [3:0] io_resp_bits_uop_ppred_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_prs1_busy_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_prs2_busy_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_prs3_busy_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_ppred_busy_0; // @[mshrs.scala:402:7] wire [6:0] io_resp_bits_uop_stale_pdst_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_exception_0; // @[mshrs.scala:402:7] wire [63:0] io_resp_bits_uop_exc_cause_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_bypassable_0; // @[mshrs.scala:402:7] wire [4:0] io_resp_bits_uop_mem_cmd_0; // @[mshrs.scala:402:7] wire [1:0] io_resp_bits_uop_mem_size_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_mem_signed_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_is_fence_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_is_fencei_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_is_amo_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_uses_ldq_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_uses_stq_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_is_sys_pc2epc_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_is_unique_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_flush_on_commit_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_ldst_is_rs1_0; // @[mshrs.scala:402:7] wire [5:0] io_resp_bits_uop_ldst_0; // @[mshrs.scala:402:7] wire [5:0] io_resp_bits_uop_lrs1_0; // @[mshrs.scala:402:7] wire [5:0] io_resp_bits_uop_lrs2_0; // @[mshrs.scala:402:7] wire [5:0] io_resp_bits_uop_lrs3_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_ldst_val_0; // @[mshrs.scala:402:7] wire [1:0] io_resp_bits_uop_dst_rtype_0; // @[mshrs.scala:402:7] wire [1:0] io_resp_bits_uop_lrs1_rtype_0; // @[mshrs.scala:402:7] wire [1:0] io_resp_bits_uop_lrs2_rtype_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_frs3_en_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_fp_val_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_fp_single_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_xcpt_pf_if_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_xcpt_ae_if_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_xcpt_ma_if_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_bp_debug_if_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_bp_xcpt_if_0; // @[mshrs.scala:402:7] wire [1:0] io_resp_bits_uop_debug_fsrc_0; // @[mshrs.scala:402:7] wire [1:0] io_resp_bits_uop_debug_tsrc_0; // @[mshrs.scala:402:7] wire [63:0] io_resp_bits_data_0; // @[mshrs.scala:402:7] wire io_resp_bits_is_hella_0; // @[mshrs.scala:402:7] wire io_resp_valid_0; // @[mshrs.scala:402:7] wire [2:0] io_mem_access_bits_opcode_0; // @[mshrs.scala:402:7] wire [2:0] io_mem_access_bits_param_0; // @[mshrs.scala:402:7] wire [3:0] io_mem_access_bits_size_0; // @[mshrs.scala:402:7] wire [3:0] io_mem_access_bits_source_0; // @[mshrs.scala:402:7] wire [31:0] io_mem_access_bits_address_0; // @[mshrs.scala:402:7] wire [7:0] io_mem_access_bits_mask_0; // @[mshrs.scala:402:7] wire [63:0] io_mem_access_bits_data_0; // @[mshrs.scala:402:7] wire io_mem_access_valid_0; // @[mshrs.scala:402:7] reg [6:0] req_uop_uopc; // @[mshrs.scala:421:16] assign io_resp_bits_uop_uopc_0 = req_uop_uopc; // @[mshrs.scala:402:7, :421:16] reg [31:0] req_uop_inst; // @[mshrs.scala:421:16] assign io_resp_bits_uop_inst_0 = req_uop_inst; // @[mshrs.scala:402:7, :421:16] reg [31:0] req_uop_debug_inst; // @[mshrs.scala:421:16] assign io_resp_bits_uop_debug_inst_0 = req_uop_debug_inst; // @[mshrs.scala:402:7, :421:16] reg req_uop_is_rvc; // @[mshrs.scala:421:16] assign io_resp_bits_uop_is_rvc_0 = req_uop_is_rvc; // @[mshrs.scala:402:7, :421:16] reg [33:0] req_uop_debug_pc; // @[mshrs.scala:421:16] assign io_resp_bits_uop_debug_pc_0 = req_uop_debug_pc; // @[mshrs.scala:402:7, :421:16] reg [2:0] req_uop_iq_type; // @[mshrs.scala:421:16] assign io_resp_bits_uop_iq_type_0 = req_uop_iq_type; // @[mshrs.scala:402:7, :421:16] reg [9:0] req_uop_fu_code; // @[mshrs.scala:421:16] assign io_resp_bits_uop_fu_code_0 = req_uop_fu_code; // @[mshrs.scala:402:7, :421:16] reg [3:0] req_uop_ctrl_br_type; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ctrl_br_type_0 = req_uop_ctrl_br_type; // @[mshrs.scala:402:7, :421:16] reg [1:0] req_uop_ctrl_op1_sel; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ctrl_op1_sel_0 = req_uop_ctrl_op1_sel; // @[mshrs.scala:402:7, :421:16] reg [2:0] req_uop_ctrl_op2_sel; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ctrl_op2_sel_0 = req_uop_ctrl_op2_sel; // @[mshrs.scala:402:7, :421:16] reg [2:0] req_uop_ctrl_imm_sel; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ctrl_imm_sel_0 = req_uop_ctrl_imm_sel; // @[mshrs.scala:402:7, :421:16] reg [4:0] req_uop_ctrl_op_fcn; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ctrl_op_fcn_0 = req_uop_ctrl_op_fcn; // @[mshrs.scala:402:7, :421:16] reg req_uop_ctrl_fcn_dw; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ctrl_fcn_dw_0 = req_uop_ctrl_fcn_dw; // @[mshrs.scala:402:7, :421:16] reg [2:0] req_uop_ctrl_csr_cmd; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ctrl_csr_cmd_0 = req_uop_ctrl_csr_cmd; // @[mshrs.scala:402:7, :421:16] reg req_uop_ctrl_is_load; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ctrl_is_load_0 = req_uop_ctrl_is_load; // @[mshrs.scala:402:7, :421:16] reg req_uop_ctrl_is_sta; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ctrl_is_sta_0 = req_uop_ctrl_is_sta; // @[mshrs.scala:402:7, :421:16] reg req_uop_ctrl_is_std; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ctrl_is_std_0 = req_uop_ctrl_is_std; // @[mshrs.scala:402:7, :421:16] reg [1:0] req_uop_iw_state; // @[mshrs.scala:421:16] assign io_resp_bits_uop_iw_state_0 = req_uop_iw_state; // @[mshrs.scala:402:7, :421:16] reg req_uop_iw_p1_poisoned; // @[mshrs.scala:421:16] assign io_resp_bits_uop_iw_p1_poisoned_0 = req_uop_iw_p1_poisoned; // @[mshrs.scala:402:7, :421:16] reg req_uop_iw_p2_poisoned; // @[mshrs.scala:421:16] assign io_resp_bits_uop_iw_p2_poisoned_0 = req_uop_iw_p2_poisoned; // @[mshrs.scala:402:7, :421:16] reg req_uop_is_br; // @[mshrs.scala:421:16] assign io_resp_bits_uop_is_br_0 = req_uop_is_br; // @[mshrs.scala:402:7, :421:16] reg req_uop_is_jalr; // @[mshrs.scala:421:16] assign io_resp_bits_uop_is_jalr_0 = req_uop_is_jalr; // @[mshrs.scala:402:7, :421:16] reg req_uop_is_jal; // @[mshrs.scala:421:16] assign io_resp_bits_uop_is_jal_0 = req_uop_is_jal; // @[mshrs.scala:402:7, :421:16] reg req_uop_is_sfb; // @[mshrs.scala:421:16] assign io_resp_bits_uop_is_sfb_0 = req_uop_is_sfb; // @[mshrs.scala:402:7, :421:16] reg [3:0] req_uop_br_mask; // @[mshrs.scala:421:16] assign io_resp_bits_uop_br_mask_0 = req_uop_br_mask; // @[mshrs.scala:402:7, :421:16] reg [1:0] req_uop_br_tag; // @[mshrs.scala:421:16] assign io_resp_bits_uop_br_tag_0 = req_uop_br_tag; // @[mshrs.scala:402:7, :421:16] reg [3:0] req_uop_ftq_idx; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ftq_idx_0 = req_uop_ftq_idx; // @[mshrs.scala:402:7, :421:16] reg req_uop_edge_inst; // @[mshrs.scala:421:16] assign io_resp_bits_uop_edge_inst_0 = req_uop_edge_inst; // @[mshrs.scala:402:7, :421:16] reg [5:0] req_uop_pc_lob; // @[mshrs.scala:421:16] assign io_resp_bits_uop_pc_lob_0 = req_uop_pc_lob; // @[mshrs.scala:402:7, :421:16] reg req_uop_taken; // @[mshrs.scala:421:16] assign io_resp_bits_uop_taken_0 = req_uop_taken; // @[mshrs.scala:402:7, :421:16] reg [19:0] req_uop_imm_packed; // @[mshrs.scala:421:16] assign io_resp_bits_uop_imm_packed_0 = req_uop_imm_packed; // @[mshrs.scala:402:7, :421:16] reg [11:0] req_uop_csr_addr; // @[mshrs.scala:421:16] assign io_resp_bits_uop_csr_addr_0 = req_uop_csr_addr; // @[mshrs.scala:402:7, :421:16] reg [5:0] req_uop_rob_idx; // @[mshrs.scala:421:16] assign io_resp_bits_uop_rob_idx_0 = req_uop_rob_idx; // @[mshrs.scala:402:7, :421:16] reg [3:0] req_uop_ldq_idx; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ldq_idx_0 = req_uop_ldq_idx; // @[mshrs.scala:402:7, :421:16] reg [3:0] req_uop_stq_idx; // @[mshrs.scala:421:16] assign io_resp_bits_uop_stq_idx_0 = req_uop_stq_idx; // @[mshrs.scala:402:7, :421:16] reg [1:0] req_uop_rxq_idx; // @[mshrs.scala:421:16] assign io_resp_bits_uop_rxq_idx_0 = req_uop_rxq_idx; // @[mshrs.scala:402:7, :421:16] reg [6:0] req_uop_pdst; // @[mshrs.scala:421:16] assign io_resp_bits_uop_pdst_0 = req_uop_pdst; // @[mshrs.scala:402:7, :421:16] reg [6:0] req_uop_prs1; // @[mshrs.scala:421:16] assign io_resp_bits_uop_prs1_0 = req_uop_prs1; // @[mshrs.scala:402:7, :421:16] reg [6:0] req_uop_prs2; // @[mshrs.scala:421:16] assign io_resp_bits_uop_prs2_0 = req_uop_prs2; // @[mshrs.scala:402:7, :421:16] reg [6:0] req_uop_prs3; // @[mshrs.scala:421:16] assign io_resp_bits_uop_prs3_0 = req_uop_prs3; // @[mshrs.scala:402:7, :421:16] reg [3:0] req_uop_ppred; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ppred_0 = req_uop_ppred; // @[mshrs.scala:402:7, :421:16] reg req_uop_prs1_busy; // @[mshrs.scala:421:16] assign io_resp_bits_uop_prs1_busy_0 = req_uop_prs1_busy; // @[mshrs.scala:402:7, :421:16] reg req_uop_prs2_busy; // @[mshrs.scala:421:16] assign io_resp_bits_uop_prs2_busy_0 = req_uop_prs2_busy; // @[mshrs.scala:402:7, :421:16] reg req_uop_prs3_busy; // @[mshrs.scala:421:16] assign io_resp_bits_uop_prs3_busy_0 = req_uop_prs3_busy; // @[mshrs.scala:402:7, :421:16] reg req_uop_ppred_busy; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ppred_busy_0 = req_uop_ppred_busy; // @[mshrs.scala:402:7, :421:16] reg [6:0] req_uop_stale_pdst; // @[mshrs.scala:421:16] assign io_resp_bits_uop_stale_pdst_0 = req_uop_stale_pdst; // @[mshrs.scala:402:7, :421:16] reg req_uop_exception; // @[mshrs.scala:421:16] assign io_resp_bits_uop_exception_0 = req_uop_exception; // @[mshrs.scala:402:7, :421:16] reg [63:0] req_uop_exc_cause; // @[mshrs.scala:421:16] assign io_resp_bits_uop_exc_cause_0 = req_uop_exc_cause; // @[mshrs.scala:402:7, :421:16] reg req_uop_bypassable; // @[mshrs.scala:421:16] assign io_resp_bits_uop_bypassable_0 = req_uop_bypassable; // @[mshrs.scala:402:7, :421:16] reg [4:0] req_uop_mem_cmd; // @[mshrs.scala:421:16] assign io_resp_bits_uop_mem_cmd_0 = req_uop_mem_cmd; // @[mshrs.scala:402:7, :421:16] reg [1:0] req_uop_mem_size; // @[mshrs.scala:421:16] assign io_resp_bits_uop_mem_size_0 = req_uop_mem_size; // @[mshrs.scala:402:7, :421:16] wire [1:0] size = req_uop_mem_size; // @[AMOALU.scala:11:18] reg req_uop_mem_signed; // @[mshrs.scala:421:16] assign io_resp_bits_uop_mem_signed_0 = req_uop_mem_signed; // @[mshrs.scala:402:7, :421:16] reg req_uop_is_fence; // @[mshrs.scala:421:16] assign io_resp_bits_uop_is_fence_0 = req_uop_is_fence; // @[mshrs.scala:402:7, :421:16] reg req_uop_is_fencei; // @[mshrs.scala:421:16] assign io_resp_bits_uop_is_fencei_0 = req_uop_is_fencei; // @[mshrs.scala:402:7, :421:16] reg req_uop_is_amo; // @[mshrs.scala:421:16] assign io_resp_bits_uop_is_amo_0 = req_uop_is_amo; // @[mshrs.scala:402:7, :421:16] reg req_uop_uses_ldq; // @[mshrs.scala:421:16] assign io_resp_bits_uop_uses_ldq_0 = req_uop_uses_ldq; // @[mshrs.scala:402:7, :421:16] reg req_uop_uses_stq; // @[mshrs.scala:421:16] assign io_resp_bits_uop_uses_stq_0 = req_uop_uses_stq; // @[mshrs.scala:402:7, :421:16] reg req_uop_is_sys_pc2epc; // @[mshrs.scala:421:16] assign io_resp_bits_uop_is_sys_pc2epc_0 = req_uop_is_sys_pc2epc; // @[mshrs.scala:402:7, :421:16] reg req_uop_is_unique; // @[mshrs.scala:421:16] assign io_resp_bits_uop_is_unique_0 = req_uop_is_unique; // @[mshrs.scala:402:7, :421:16] reg req_uop_flush_on_commit; // @[mshrs.scala:421:16] assign io_resp_bits_uop_flush_on_commit_0 = req_uop_flush_on_commit; // @[mshrs.scala:402:7, :421:16] reg req_uop_ldst_is_rs1; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ldst_is_rs1_0 = req_uop_ldst_is_rs1; // @[mshrs.scala:402:7, :421:16] reg [5:0] req_uop_ldst; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ldst_0 = req_uop_ldst; // @[mshrs.scala:402:7, :421:16] reg [5:0] req_uop_lrs1; // @[mshrs.scala:421:16] assign io_resp_bits_uop_lrs1_0 = req_uop_lrs1; // @[mshrs.scala:402:7, :421:16] reg [5:0] req_uop_lrs2; // @[mshrs.scala:421:16] assign io_resp_bits_uop_lrs2_0 = req_uop_lrs2; // @[mshrs.scala:402:7, :421:16] reg [5:0] req_uop_lrs3; // @[mshrs.scala:421:16] assign io_resp_bits_uop_lrs3_0 = req_uop_lrs3; // @[mshrs.scala:402:7, :421:16] reg req_uop_ldst_val; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ldst_val_0 = req_uop_ldst_val; // @[mshrs.scala:402:7, :421:16] reg [1:0] req_uop_dst_rtype; // @[mshrs.scala:421:16] assign io_resp_bits_uop_dst_rtype_0 = req_uop_dst_rtype; // @[mshrs.scala:402:7, :421:16] reg [1:0] req_uop_lrs1_rtype; // @[mshrs.scala:421:16] assign io_resp_bits_uop_lrs1_rtype_0 = req_uop_lrs1_rtype; // @[mshrs.scala:402:7, :421:16] reg [1:0] req_uop_lrs2_rtype; // @[mshrs.scala:421:16] assign io_resp_bits_uop_lrs2_rtype_0 = req_uop_lrs2_rtype; // @[mshrs.scala:402:7, :421:16] reg req_uop_frs3_en; // @[mshrs.scala:421:16] assign io_resp_bits_uop_frs3_en_0 = req_uop_frs3_en; // @[mshrs.scala:402:7, :421:16] reg req_uop_fp_val; // @[mshrs.scala:421:16] assign io_resp_bits_uop_fp_val_0 = req_uop_fp_val; // @[mshrs.scala:402:7, :421:16] reg req_uop_fp_single; // @[mshrs.scala:421:16] assign io_resp_bits_uop_fp_single_0 = req_uop_fp_single; // @[mshrs.scala:402:7, :421:16] reg req_uop_xcpt_pf_if; // @[mshrs.scala:421:16] assign io_resp_bits_uop_xcpt_pf_if_0 = req_uop_xcpt_pf_if; // @[mshrs.scala:402:7, :421:16] reg req_uop_xcpt_ae_if; // @[mshrs.scala:421:16] assign io_resp_bits_uop_xcpt_ae_if_0 = req_uop_xcpt_ae_if; // @[mshrs.scala:402:7, :421:16] reg req_uop_xcpt_ma_if; // @[mshrs.scala:421:16] assign io_resp_bits_uop_xcpt_ma_if_0 = req_uop_xcpt_ma_if; // @[mshrs.scala:402:7, :421:16] reg req_uop_bp_debug_if; // @[mshrs.scala:421:16] assign io_resp_bits_uop_bp_debug_if_0 = req_uop_bp_debug_if; // @[mshrs.scala:402:7, :421:16] reg req_uop_bp_xcpt_if; // @[mshrs.scala:421:16] assign io_resp_bits_uop_bp_xcpt_if_0 = req_uop_bp_xcpt_if; // @[mshrs.scala:402:7, :421:16] reg [1:0] req_uop_debug_fsrc; // @[mshrs.scala:421:16] assign io_resp_bits_uop_debug_fsrc_0 = req_uop_debug_fsrc; // @[mshrs.scala:402:7, :421:16] reg [1:0] req_uop_debug_tsrc; // @[mshrs.scala:421:16] assign io_resp_bits_uop_debug_tsrc_0 = req_uop_debug_tsrc; // @[mshrs.scala:402:7, :421:16] reg [33:0] req_addr; // @[mshrs.scala:421:16] wire [33:0] _get_legal_T_4 = req_addr; // @[Parameters.scala:137:31] wire [33:0] _put_legal_T_4 = req_addr; // @[Parameters.scala:137:31] wire [33:0] _atomics_legal_T_4 = req_addr; // @[Parameters.scala:137:31] wire [33:0] _atomics_legal_T_14 = req_addr; // @[Parameters.scala:137:31] wire [33:0] _atomics_legal_T_24 = req_addr; // @[Parameters.scala:137:31] wire [33:0] _atomics_legal_T_34 = req_addr; // @[Parameters.scala:137:31] wire [33:0] _atomics_legal_T_44 = req_addr; // @[Parameters.scala:137:31] wire [33:0] _atomics_legal_T_54 = req_addr; // @[Parameters.scala:137:31] wire [33:0] _atomics_legal_T_64 = req_addr; // @[Parameters.scala:137:31] wire [33:0] _atomics_legal_T_74 = req_addr; // @[Parameters.scala:137:31] wire [33:0] _atomics_legal_T_84 = req_addr; // @[Parameters.scala:137:31] reg [63:0] req_data; // @[mshrs.scala:421:16] wire [63:0] put_data = req_data; // @[Edges.scala:480:17] wire [63:0] atomics_a_data = req_data; // @[Edges.scala:534:17] wire [63:0] atomics_a_1_data = req_data; // @[Edges.scala:534:17] wire [63:0] atomics_a_2_data = req_data; // @[Edges.scala:534:17] wire [63:0] atomics_a_3_data = req_data; // @[Edges.scala:534:17] wire [63:0] atomics_a_4_data = req_data; // @[Edges.scala:517:17] wire [63:0] atomics_a_5_data = req_data; // @[Edges.scala:517:17] wire [63:0] atomics_a_6_data = req_data; // @[Edges.scala:517:17] wire [63:0] atomics_a_7_data = req_data; // @[Edges.scala:517:17] wire [63:0] atomics_a_8_data = req_data; // @[Edges.scala:517:17] reg req_is_hella; // @[mshrs.scala:421:16] assign io_resp_bits_is_hella_0 = req_is_hella; // @[mshrs.scala:402:7, :421:16] reg [63:0] grant_word; // @[mshrs.scala:422:23] reg [1:0] state; // @[mshrs.scala:426:22] assign _io_req_ready_T = state == 2'h0; // @[mshrs.scala:426:22, :427:25] assign io_req_ready_0 = _io_req_ready_T; // @[mshrs.scala:402:7, :427:25] wire [34:0] _get_legal_T_5 = {1'h0, _get_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [34:0] _get_legal_T_6 = _get_legal_T_5 & 35'h80110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _get_legal_T_7 = _get_legal_T_6; // @[Parameters.scala:137:46] wire _get_legal_T_8 = _get_legal_T_7 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _get_legal_T_9 = _get_legal_T_8; // @[Parameters.scala:684:54] wire _get_legal_T_32 = _get_legal_T_9; // @[Parameters.scala:684:54, :686:26] wire [33:0] _GEN = {req_addr[33:17], req_addr[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31] wire [33:0] _get_legal_T_14; // @[Parameters.scala:137:31] assign _get_legal_T_14 = _GEN; // @[Parameters.scala:137:31] wire [33:0] _put_legal_T_14; // @[Parameters.scala:137:31] assign _put_legal_T_14 = _GEN; // @[Parameters.scala:137:31] wire [34:0] _get_legal_T_15 = {1'h0, _get_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [34:0] _get_legal_T_16 = _get_legal_T_15 & 35'h80110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _get_legal_T_17 = _get_legal_T_16; // @[Parameters.scala:137:46] wire _get_legal_T_18 = _get_legal_T_17 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [33:0] _GEN_0 = {req_addr[33:21], req_addr[20:0] ^ 21'h100000}; // @[Parameters.scala:137:31] wire [33:0] _get_legal_T_19; // @[Parameters.scala:137:31] assign _get_legal_T_19 = _GEN_0; // @[Parameters.scala:137:31] wire [33:0] _put_legal_T_19; // @[Parameters.scala:137:31] assign _put_legal_T_19 = _GEN_0; // @[Parameters.scala:137:31] wire [34:0] _get_legal_T_20 = {1'h0, _get_legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [34:0] _get_legal_T_21 = _get_legal_T_20 & 35'h80100000; // @[Parameters.scala:137:{41,46}] wire [34:0] _get_legal_T_22 = _get_legal_T_21; // @[Parameters.scala:137:46] wire _get_legal_T_23 = _get_legal_T_22 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] get_address = req_addr[31:0]; // @[Edges.scala:460:17] wire [31:0] put_address = req_addr[31:0]; // @[Edges.scala:480:17] wire [31:0] atomics_a_address = req_addr[31:0]; // @[Edges.scala:534:17] wire [31:0] atomics_a_1_address = req_addr[31:0]; // @[Edges.scala:534:17] wire [31:0] atomics_a_2_address = req_addr[31:0]; // @[Edges.scala:534:17] wire [31:0] atomics_a_3_address = req_addr[31:0]; // @[Edges.scala:534:17] wire [31:0] atomics_a_4_address = req_addr[31:0]; // @[Edges.scala:517:17] wire [31:0] atomics_a_5_address = req_addr[31:0]; // @[Edges.scala:517:17] wire [31:0] atomics_a_6_address = req_addr[31:0]; // @[Edges.scala:517:17] wire [31:0] atomics_a_7_address = req_addr[31:0]; // @[Edges.scala:517:17] wire [31:0] atomics_a_8_address = req_addr[31:0]; // @[Edges.scala:517:17] wire [33:0] _GEN_1 = {req_addr[33:32], req_addr[31:0] ^ 32'h80000000}; // @[Parameters.scala:137:31] wire [33:0] _get_legal_T_24; // @[Parameters.scala:137:31] assign _get_legal_T_24 = _GEN_1; // @[Parameters.scala:137:31] wire [33:0] _put_legal_T_24; // @[Parameters.scala:137:31] assign _put_legal_T_24 = _GEN_1; // @[Parameters.scala:137:31] wire [34:0] _get_legal_T_25 = {1'h0, _get_legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [34:0] _get_legal_T_26 = _get_legal_T_25 & 35'h80000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _get_legal_T_27 = _get_legal_T_26; // @[Parameters.scala:137:46] wire _get_legal_T_28 = _get_legal_T_27 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _get_legal_T_29 = _get_legal_T_18 \| _get_legal_T_23; // @[Parameters.scala:685:42] wire _get_legal_T_30 = _get_legal_T_29 \| _get_legal_T_28; // @[Parameters.scala:685:42] wire _get_legal_T_31 = _get_legal_T_30; // @[Parameters.scala:684:54, :685:42] wire get_legal = _get_legal_T_32 \| _get_legal_T_31; // @[Parameters.scala:684:54, :686:26] wire [7:0] _get_a_mask_T; // @[Misc.scala:222:10] wire [3:0] get_size; // @[Edges.scala:460:17] wire [7:0] get_mask; // @[Edges.scala:460:17] wire [3:0] _GEN_2 = {2'h0, req_uop_mem_size}; // @[Edges.scala:463:15] assign get_size = _GEN_2; // @[Edges.scala:460:17, :463:15] wire [3:0] put_size; // @[Edges.scala:480:17] assign put_size = _GEN_2; // @[Edges.scala:463:15, :480:17] wire [3:0] atomics_a_size; // @[Edges.scala:534:17] assign atomics_a_size = _GEN_2; // @[Edges.scala:463:15, :534:17] wire [3:0] atomics_a_1_size; // @[Edges.scala:534:17] assign atomics_a_1_size = _GEN_2; // @[Edges.scala:463:15, :534:17] wire [3:0] atomics_a_2_size; // @[Edges.scala:534:17] assign atomics_a_2_size = _GEN_2; // @[Edges.scala:463:15, :534:17] wire [3:0] atomics_a_3_size; // @[Edges.scala:534:17] assign atomics_a_3_size = _GEN_2; // @[Edges.scala:463:15, :534:17] wire [3:0] atomics_a_4_size; // @[Edges.scala:517:17] assign atomics_a_4_size = _GEN_2; // @[Edges.scala:463:15, :517:17] wire [3:0] atomics_a_5_size; // @[Edges.scala:517:17] assign atomics_a_5_size = _GEN_2; // @[Edges.scala:463:15, :517:17] wire [3:0] atomics_a_6_size; // @[Edges.scala:517:17] assign atomics_a_6_size = _GEN_2; // @[Edges.scala:463:15, :517:17] wire [3:0] atomics_a_7_size; // @[Edges.scala:517:17] assign atomics_a_7_size = _GEN_2; // @[Edges.scala:463:15, :517:17] wire [3:0] atomics_a_8_size; // @[Edges.scala:517:17] assign atomics_a_8_size = _GEN_2; // @[Edges.scala:463:15, :517:17] wire [2:0] _GEN_3 = {1'h0, req_uop_mem_size}; // @[Misc.scala:202:34] wire [2:0] _get_a_mask_sizeOH_T; // @[Misc.scala:202:34] assign _get_a_mask_sizeOH_T = _GEN_3; // @[Misc.scala:202:34] wire [2:0] _put_a_mask_sizeOH_T; // @[Misc.scala:202:34] assign _put_a_mask_sizeOH_T = _GEN_3; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T = _GEN_3; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T_3; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_3 = _GEN_3; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T_6; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_6 = _GEN_3; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T_9; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_9 = _GEN_3; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T_12; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_12 = _GEN_3; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T_15; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_15 = _GEN_3; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T_18; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_18 = _GEN_3; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T_21; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_21 = _GEN_3; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T_24; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_24 = _GEN_3; // @[Misc.scala:202:34] wire [1:0] get_a_mask_sizeOH_shiftAmount = _get_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _get_a_mask_sizeOH_T_1 = 4'h1 << get_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _get_a_mask_sizeOH_T_2 = _get_a_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] get_a_mask_sizeOH = {_get_a_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire get_a_mask_sub_sub_sub_0_1 = &req_uop_mem_size; // @[Misc.scala:206:21] wire get_a_mask_sub_sub_size = get_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire get_a_mask_sub_sub_bit = req_addr[2]; // @[Misc.scala:210:26] wire put_a_mask_sub_sub_bit = req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit = req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_1 = req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_2 = req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_3 = req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_4 = req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_5 = req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_6 = req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_7 = req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_8 = req_addr[2]; // @[Misc.scala:210:26] wire _io_resp_bits_data_shifted_T = req_addr[2]; // @[Misc.scala:210:26] wire get_a_mask_sub_sub_1_2 = get_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire get_a_mask_sub_sub_nbit = ~get_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire get_a_mask_sub_sub_0_2 = get_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_sub_sub_acc_T = get_a_mask_sub_sub_size & get_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_sub_0_1 = get_a_mask_sub_sub_sub_0_1 \| _get_a_mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _get_a_mask_sub_sub_acc_T_1 = get_a_mask_sub_sub_size & get_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_sub_1_1 = get_a_mask_sub_sub_sub_0_1 \| _get_a_mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire get_a_mask_sub_size = get_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire get_a_mask_sub_bit = req_addr[1]; // @[Misc.scala:210:26] wire put_a_mask_sub_bit = req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit = req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_1 = req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_2 = req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_3 = req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_4 = req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_5 = req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_6 = req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_7 = req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_8 = req_addr[1]; // @[Misc.scala:210:26] wire _io_resp_bits_data_shifted_T_3 = req_addr[1]; // @[Misc.scala:210:26] wire get_a_mask_sub_nbit = ~get_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire get_a_mask_sub_0_2 = get_a_mask_sub_sub_0_2 & get_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_sub_acc_T = get_a_mask_sub_size & get_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_0_1 = get_a_mask_sub_sub_0_1 \| _get_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_1_2 = get_a_mask_sub_sub_0_2 & get_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_sub_acc_T_1 = get_a_mask_sub_size & get_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_1_1 = get_a_mask_sub_sub_0_1 \| _get_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_2_2 = get_a_mask_sub_sub_1_2 & get_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_sub_acc_T_2 = get_a_mask_sub_size & get_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_2_1 = get_a_mask_sub_sub_1_1 \| _get_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_3_2 = get_a_mask_sub_sub_1_2 & get_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_sub_acc_T_3 = get_a_mask_sub_size & get_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_3_1 = get_a_mask_sub_sub_1_1 \| _get_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire get_a_mask_size = get_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire get_a_mask_bit = req_addr[0]; // @[Misc.scala:210:26] wire put_a_mask_bit = req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit = req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_1 = req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_2 = req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_3 = req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_4 = req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_5 = req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_6 = req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_7 = req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_8 = req_addr[0]; // @[Misc.scala:210:26] wire _io_resp_bits_data_shifted_T_6 = req_addr[0]; // @[Misc.scala:210:26] wire get_a_mask_nbit = ~get_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire get_a_mask_eq = get_a_mask_sub_0_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T = get_a_mask_size & get_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc = get_a_mask_sub_0_1 \| _get_a_mask_acc_T; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_1 = get_a_mask_sub_0_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_1 = get_a_mask_size & get_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_1 = get_a_mask_sub_0_1 \| _get_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_2 = get_a_mask_sub_1_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T_2 = get_a_mask_size & get_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_2 = get_a_mask_sub_1_1 \| _get_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_3 = get_a_mask_sub_1_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_3 = get_a_mask_size & get_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_3 = get_a_mask_sub_1_1 \| _get_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_4 = get_a_mask_sub_2_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T_4 = get_a_mask_size & get_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_4 = get_a_mask_sub_2_1 \| _get_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_5 = get_a_mask_sub_2_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_5 = get_a_mask_size & get_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_5 = get_a_mask_sub_2_1 \| _get_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_6 = get_a_mask_sub_3_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T_6 = get_a_mask_size & get_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_6 = get_a_mask_sub_3_1 \| _get_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_7 = get_a_mask_sub_3_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_7 = get_a_mask_size & get_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_7 = get_a_mask_sub_3_1 \| _get_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] get_a_mask_lo_lo = {get_a_mask_acc_1, get_a_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] get_a_mask_lo_hi = {get_a_mask_acc_3, get_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] get_a_mask_lo = {get_a_mask_lo_hi, get_a_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] get_a_mask_hi_lo = {get_a_mask_acc_5, get_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] get_a_mask_hi_hi = {get_a_mask_acc_7, get_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] get_a_mask_hi = {get_a_mask_hi_hi, get_a_mask_hi_lo}; // @[Misc.scala:222:10] assign _get_a_mask_T = {get_a_mask_hi, get_a_mask_lo}; // @[Misc.scala:222:10] assign get_mask = _get_a_mask_T; // @[Misc.scala:222:10] wire [34:0] _put_legal_T_5 = {1'h0, _put_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [34:0] _put_legal_T_6 = _put_legal_T_5 & 35'h80110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _put_legal_T_7 = _put_legal_T_6; // @[Parameters.scala:137:46] wire _put_legal_T_8 = _put_legal_T_7 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _put_legal_T_9 = _put_legal_T_8; // @[Parameters.scala:684:54] wire _put_legal_T_32 = _put_legal_T_9; // @[Parameters.scala:684:54, :686:26] wire [34:0] _put_legal_T_15 = {1'h0, _put_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [34:0] _put_legal_T_16 = _put_legal_T_15 & 35'h80110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _put_legal_T_17 = _put_legal_T_16; // @[Parameters.scala:137:46] wire _put_legal_T_18 = _put_legal_T_17 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _put_legal_T_20 = {1'h0, _put_legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [34:0] _put_legal_T_21 = _put_legal_T_20 & 35'h80100000; // @[Parameters.scala:137:{41,46}] wire [34:0] _put_legal_T_22 = _put_legal_T_21; // @[Parameters.scala:137:46] wire _put_legal_T_23 = _put_legal_T_22 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _put_legal_T_25 = {1'h0, _put_legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [34:0] _put_legal_T_26 = _put_legal_T_25 & 35'h80000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _put_legal_T_27 = _put_legal_T_26; // @[Parameters.scala:137:46] wire _put_legal_T_28 = _put_legal_T_27 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _put_legal_T_29 = _put_legal_T_18 \| _put_legal_T_23; // @[Parameters.scala:685:42] wire _put_legal_T_30 = _put_legal_T_29 \| _put_legal_T_28; // @[Parameters.scala:685:42] wire _put_legal_T_31 = _put_legal_T_30; // @[Parameters.scala:684:54, :685:42] wire put_legal = _put_legal_T_32 \| _put_legal_T_31; // @[Parameters.scala:684:54, :686:26] wire [7:0] _put_a_mask_T; // @[Misc.scala:222:10] wire [7:0] put_mask; // @[Edges.scala:480:17] wire [1:0] put_a_mask_sizeOH_shiftAmount = _put_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _put_a_mask_sizeOH_T_1 = 4'h1 << put_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _put_a_mask_sizeOH_T_2 = _put_a_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] put_a_mask_sizeOH = {_put_a_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire put_a_mask_sub_sub_sub_0_1 = &req_uop_mem_size; // @[Misc.scala:206:21] wire put_a_mask_sub_sub_size = put_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire put_a_mask_sub_sub_1_2 = put_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire put_a_mask_sub_sub_nbit = ~put_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire put_a_mask_sub_sub_0_2 = put_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_sub_sub_acc_T = put_a_mask_sub_sub_size & put_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_sub_0_1 = put_a_mask_sub_sub_sub_0_1 \| _put_a_mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _put_a_mask_sub_sub_acc_T_1 = put_a_mask_sub_sub_size & put_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_sub_1_1 = put_a_mask_sub_sub_sub_0_1 \| _put_a_mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire put_a_mask_sub_size = put_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire put_a_mask_sub_nbit = ~put_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire put_a_mask_sub_0_2 = put_a_mask_sub_sub_0_2 & put_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_sub_acc_T = put_a_mask_sub_size & put_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_0_1 = put_a_mask_sub_sub_0_1 \| _put_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_1_2 = put_a_mask_sub_sub_0_2 & put_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_sub_acc_T_1 = put_a_mask_sub_size & put_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_1_1 = put_a_mask_sub_sub_0_1 \| _put_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_2_2 = put_a_mask_sub_sub_1_2 & put_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_sub_acc_T_2 = put_a_mask_sub_size & put_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_2_1 = put_a_mask_sub_sub_1_1 \| _put_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_3_2 = put_a_mask_sub_sub_1_2 & put_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_sub_acc_T_3 = put_a_mask_sub_size & put_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_3_1 = put_a_mask_sub_sub_1_1 \| _put_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire put_a_mask_size = put_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire put_a_mask_nbit = ~put_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire put_a_mask_eq = put_a_mask_sub_0_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T = put_a_mask_size & put_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc = put_a_mask_sub_0_1 \| _put_a_mask_acc_T; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_1 = put_a_mask_sub_0_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_1 = put_a_mask_size & put_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_1 = put_a_mask_sub_0_1 \| _put_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_2 = put_a_mask_sub_1_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T_2 = put_a_mask_size & put_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_2 = put_a_mask_sub_1_1 \| _put_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_3 = put_a_mask_sub_1_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_3 = put_a_mask_size & put_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_3 = put_a_mask_sub_1_1 \| _put_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_4 = put_a_mask_sub_2_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T_4 = put_a_mask_size & put_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_4 = put_a_mask_sub_2_1 \| _put_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_5 = put_a_mask_sub_2_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_5 = put_a_mask_size & put_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_5 = put_a_mask_sub_2_1 \| _put_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_6 = put_a_mask_sub_3_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T_6 = put_a_mask_size & put_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_6 = put_a_mask_sub_3_1 \| _put_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_7 = put_a_mask_sub_3_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_7 = put_a_mask_size & put_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_7 = put_a_mask_sub_3_1 \| _put_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] put_a_mask_lo_lo = {put_a_mask_acc_1, put_a_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] put_a_mask_lo_hi = {put_a_mask_acc_3, put_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] put_a_mask_lo = {put_a_mask_lo_hi, put_a_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] put_a_mask_hi_lo = {put_a_mask_acc_5, put_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] put_a_mask_hi_hi = {put_a_mask_acc_7, put_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] put_a_mask_hi = {put_a_mask_hi_hi, put_a_mask_hi_lo}; // @[Misc.scala:222:10] assign _put_a_mask_T = {put_a_mask_hi, put_a_mask_lo}; // @[Misc.scala:222:10] assign put_mask = _put_a_mask_T; // @[Misc.scala:222:10] wire [34:0] _atomics_legal_T_5 = {1'h0, _atomics_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [7:0] _atomics_a_mask_T; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask; // @[Edges.scala:534:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount = _atomics_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_1 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_2 = _atomics_a_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH = {_atomics_a_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1 = &req_uop_mem_size; // @[Misc.scala:206:21] wire atomics_a_mask_sub_sub_size = atomics_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2 = atomics_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit = ~atomics_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2 = atomics_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T = atomics_a_mask_sub_sub_size & atomics_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1 = atomics_a_mask_sub_sub_sub_0_1 \| _atomics_a_mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_1 = atomics_a_mask_sub_sub_size & atomics_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1 = atomics_a_mask_sub_sub_sub_0_1 \| _atomics_a_mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size = atomics_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit = ~atomics_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2 = atomics_a_mask_sub_sub_0_2 & atomics_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T = atomics_a_mask_sub_size & atomics_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1 = atomics_a_mask_sub_sub_0_1 \| _atomics_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2 = atomics_a_mask_sub_sub_0_2 & atomics_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_1 = atomics_a_mask_sub_size & atomics_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1 = atomics_a_mask_sub_sub_0_1 \| _atomics_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2 = atomics_a_mask_sub_sub_1_2 & atomics_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_2 = atomics_a_mask_sub_size & atomics_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1 = atomics_a_mask_sub_sub_1_1 \| _atomics_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2 = atomics_a_mask_sub_sub_1_2 & atomics_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_3 = atomics_a_mask_sub_size & atomics_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1 = atomics_a_mask_sub_sub_1_1 \| _atomics_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size = atomics_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit = ~atomics_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq = atomics_a_mask_sub_0_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T = atomics_a_mask_size & atomics_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc = atomics_a_mask_sub_0_1 \| _atomics_a_mask_acc_T; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_1 = atomics_a_mask_sub_0_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_1 = atomics_a_mask_size & atomics_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_1 = atomics_a_mask_sub_0_1 \| _atomics_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_2 = atomics_a_mask_sub_1_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_2 = atomics_a_mask_size & atomics_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_2 = atomics_a_mask_sub_1_1 \| _atomics_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_3 = atomics_a_mask_sub_1_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_3 = atomics_a_mask_size & atomics_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_3 = atomics_a_mask_sub_1_1 \| _atomics_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_4 = atomics_a_mask_sub_2_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_4 = atomics_a_mask_size & atomics_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_4 = atomics_a_mask_sub_2_1 \| _atomics_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_5 = atomics_a_mask_sub_2_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_5 = atomics_a_mask_size & atomics_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_5 = atomics_a_mask_sub_2_1 \| _atomics_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_6 = atomics_a_mask_sub_3_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_6 = atomics_a_mask_size & atomics_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_6 = atomics_a_mask_sub_3_1 \| _atomics_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_7 = atomics_a_mask_sub_3_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_7 = atomics_a_mask_size & atomics_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_7 = atomics_a_mask_sub_3_1 \| _atomics_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo = {atomics_a_mask_acc_1, atomics_a_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi = {atomics_a_mask_acc_3, atomics_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo = {atomics_a_mask_lo_hi, atomics_a_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo = {atomics_a_mask_acc_5, atomics_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi = {atomics_a_mask_acc_7, atomics_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi = {atomics_a_mask_hi_hi, atomics_a_mask_hi_lo}; // @[Misc.scala:222:10] assign _atomics_a_mask_T = {atomics_a_mask_hi, atomics_a_mask_lo}; // @[Misc.scala:222:10] assign atomics_a_mask = _atomics_a_mask_T; // @[Misc.scala:222:10] wire [34:0] _atomics_legal_T_15 = {1'h0, _atomics_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [7:0] _atomics_a_mask_T_1; // @[Misc.scala:222:10] wire [7:0] atomics_a_1_mask; // @[Edges.scala:534:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_1 = _atomics_a_mask_sizeOH_T_3[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_4 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_1; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_5 = _atomics_a_mask_sizeOH_T_4[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH_1 = {_atomics_a_mask_sizeOH_T_5[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1_1 = &req_uop_mem_size; // @[Misc.scala:206:21] wire atomics_a_mask_sub_sub_size_1 = atomics_a_mask_sizeOH_1[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2_1 = atomics_a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit_1 = ~atomics_a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_1 = atomics_a_mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_2 = atomics_a_mask_sub_sub_size_1 & atomics_a_mask_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_1 = atomics_a_mask_sub_sub_sub_0_1_1 \| _atomics_a_mask_sub_sub_acc_T_2; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_3 = atomics_a_mask_sub_sub_size_1 & atomics_a_mask_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_1 = atomics_a_mask_sub_sub_sub_0_1_1 \| _atomics_a_mask_sub_sub_acc_T_3; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size_1 = atomics_a_mask_sizeOH_1[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_1 = ~atomics_a_mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_1 = atomics_a_mask_sub_sub_0_2_1 & atomics_a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_4 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_1 = atomics_a_mask_sub_sub_0_1_1 \| _atomics_a_mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_1 = atomics_a_mask_sub_sub_0_2_1 & atomics_a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_5 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_1 = atomics_a_mask_sub_sub_0_1_1 \| _atomics_a_mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_1 = atomics_a_mask_sub_sub_1_2_1 & atomics_a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_6 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_1 = atomics_a_mask_sub_sub_1_1_1 \| _atomics_a_mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_1 = atomics_a_mask_sub_sub_1_2_1 & atomics_a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_7 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_1 = atomics_a_mask_sub_sub_1_1_1 \| _atomics_a_mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_1 = atomics_a_mask_sizeOH_1[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_1 = ~atomics_a_mask_bit_1; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_8 = atomics_a_mask_sub_0_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_8 = atomics_a_mask_size_1 & atomics_a_mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_8 = atomics_a_mask_sub_0_1_1 \| _atomics_a_mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_9 = atomics_a_mask_sub_0_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_9 = atomics_a_mask_size_1 & atomics_a_mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_9 = atomics_a_mask_sub_0_1_1 \| _atomics_a_mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_10 = atomics_a_mask_sub_1_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_10 = atomics_a_mask_size_1 & atomics_a_mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_10 = atomics_a_mask_sub_1_1_1 \| _atomics_a_mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_11 = atomics_a_mask_sub_1_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_11 = atomics_a_mask_size_1 & atomics_a_mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_11 = atomics_a_mask_sub_1_1_1 \| _atomics_a_mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_12 = atomics_a_mask_sub_2_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_12 = atomics_a_mask_size_1 & atomics_a_mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_12 = atomics_a_mask_sub_2_1_1 \| _atomics_a_mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_13 = atomics_a_mask_sub_2_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_13 = atomics_a_mask_size_1 & atomics_a_mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_13 = atomics_a_mask_sub_2_1_1 \| _atomics_a_mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_14 = atomics_a_mask_sub_3_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_14 = atomics_a_mask_size_1 & atomics_a_mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_14 = atomics_a_mask_sub_3_1_1 \| _atomics_a_mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_15 = atomics_a_mask_sub_3_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_15 = atomics_a_mask_size_1 & atomics_a_mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_15 = atomics_a_mask_sub_3_1_1 \| _atomics_a_mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_1 = {atomics_a_mask_acc_9, atomics_a_mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_1 = {atomics_a_mask_acc_11, atomics_a_mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_1 = {atomics_a_mask_lo_hi_1, atomics_a_mask_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_1 = {atomics_a_mask_acc_13, atomics_a_mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_1 = {atomics_a_mask_acc_15, atomics_a_mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_1 = {atomics_a_mask_hi_hi_1, atomics_a_mask_hi_lo_1}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_1 = {atomics_a_mask_hi_1, atomics_a_mask_lo_1}; // @[Misc.scala:222:10] assign atomics_a_1_mask = _atomics_a_mask_T_1; // @[Misc.scala:222:10] wire [34:0] _atomics_legal_T_25 = {1'h0, _atomics_legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [7:0] _atomics_a_mask_T_2; // @[Misc.scala:222:10] wire [7:0] atomics_a_2_mask; // @[Edges.scala:534:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_2 = _atomics_a_mask_sizeOH_T_6[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_7 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_2; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_8 = _atomics_a_mask_sizeOH_T_7[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH_2 = {_atomics_a_mask_sizeOH_T_8[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1_2 = &req_uop_mem_size; // @[Misc.scala:206:21] wire atomics_a_mask_sub_sub_size_2 = atomics_a_mask_sizeOH_2[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2_2 = atomics_a_mask_sub_sub_bit_2; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit_2 = ~atomics_a_mask_sub_sub_bit_2; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_2 = atomics_a_mask_sub_sub_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_4 = atomics_a_mask_sub_sub_size_2 & atomics_a_mask_sub_sub_0_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_2 = atomics_a_mask_sub_sub_sub_0_1_2 \| _atomics_a_mask_sub_sub_acc_T_4; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_5 = atomics_a_mask_sub_sub_size_2 & atomics_a_mask_sub_sub_1_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_2 = atomics_a_mask_sub_sub_sub_0_1_2 \| _atomics_a_mask_sub_sub_acc_T_5; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size_2 = atomics_a_mask_sizeOH_2[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_2 = ~atomics_a_mask_sub_bit_2; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_2 = atomics_a_mask_sub_sub_0_2_2 & atomics_a_mask_sub_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_8 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_0_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_2 = atomics_a_mask_sub_sub_0_1_2 \| _atomics_a_mask_sub_acc_T_8; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_2 = atomics_a_mask_sub_sub_0_2_2 & atomics_a_mask_sub_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_9 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_1_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_2 = atomics_a_mask_sub_sub_0_1_2 \| _atomics_a_mask_sub_acc_T_9; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_2 = atomics_a_mask_sub_sub_1_2_2 & atomics_a_mask_sub_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_10 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_2_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_2 = atomics_a_mask_sub_sub_1_1_2 \| _atomics_a_mask_sub_acc_T_10; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_2 = atomics_a_mask_sub_sub_1_2_2 & atomics_a_mask_sub_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_11 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_3_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_2 = atomics_a_mask_sub_sub_1_1_2 \| _atomics_a_mask_sub_acc_T_11; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_2 = atomics_a_mask_sizeOH_2[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_2 = ~atomics_a_mask_bit_2; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_16 = atomics_a_mask_sub_0_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_16 = atomics_a_mask_size_2 & atomics_a_mask_eq_16; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_16 = atomics_a_mask_sub_0_1_2 \| _atomics_a_mask_acc_T_16; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_17 = atomics_a_mask_sub_0_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_17 = atomics_a_mask_size_2 & atomics_a_mask_eq_17; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_17 = atomics_a_mask_sub_0_1_2 \| _atomics_a_mask_acc_T_17; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_18 = atomics_a_mask_sub_1_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_18 = atomics_a_mask_size_2 & atomics_a_mask_eq_18; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_18 = atomics_a_mask_sub_1_1_2 \| _atomics_a_mask_acc_T_18; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_19 = atomics_a_mask_sub_1_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_19 = atomics_a_mask_size_2 & atomics_a_mask_eq_19; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_19 = atomics_a_mask_sub_1_1_2 \| _atomics_a_mask_acc_T_19; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_20 = atomics_a_mask_sub_2_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_20 = atomics_a_mask_size_2 & atomics_a_mask_eq_20; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_20 = atomics_a_mask_sub_2_1_2 \| _atomics_a_mask_acc_T_20; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_21 = atomics_a_mask_sub_2_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_21 = atomics_a_mask_size_2 & atomics_a_mask_eq_21; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_21 = atomics_a_mask_sub_2_1_2 \| _atomics_a_mask_acc_T_21; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_22 = atomics_a_mask_sub_3_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_22 = atomics_a_mask_size_2 & atomics_a_mask_eq_22; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_22 = atomics_a_mask_sub_3_1_2 \| _atomics_a_mask_acc_T_22; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_23 = atomics_a_mask_sub_3_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_23 = atomics_a_mask_size_2 & atomics_a_mask_eq_23; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_23 = atomics_a_mask_sub_3_1_2 \| _atomics_a_mask_acc_T_23; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_2 = {atomics_a_mask_acc_17, atomics_a_mask_acc_16}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_2 = {atomics_a_mask_acc_19, atomics_a_mask_acc_18}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_2 = {atomics_a_mask_lo_hi_2, atomics_a_mask_lo_lo_2}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_2 = {atomics_a_mask_acc_21, atomics_a_mask_acc_20}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_2 = {atomics_a_mask_acc_23, atomics_a_mask_acc_22}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_2 = {atomics_a_mask_hi_hi_2, atomics_a_mask_hi_lo_2}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_2 = {atomics_a_mask_hi_2, atomics_a_mask_lo_2}; // @[Misc.scala:222:10] assign atomics_a_2_mask = _atomics_a_mask_T_2; // @[Misc.scala:222:10] wire [34:0] _atomics_legal_T_35 = {1'h0, _atomics_legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [7:0] _atomics_a_mask_T_3; // @[Misc.scala:222:10] wire [7:0] atomics_a_3_mask; // @[Edges.scala:534:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_3 = _atomics_a_mask_sizeOH_T_9[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_10 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_3; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_11 = _atomics_a_mask_sizeOH_T_10[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH_3 = {_atomics_a_mask_sizeOH_T_11[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1_3 = &req_uop_mem_size; // @[Misc.scala:206:21] wire atomics_a_mask_sub_sub_size_3 = atomics_a_mask_sizeOH_3[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2_3 = atomics_a_mask_sub_sub_bit_3; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit_3 = ~atomics_a_mask_sub_sub_bit_3; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_3 = atomics_a_mask_sub_sub_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_6 = atomics_a_mask_sub_sub_size_3 & atomics_a_mask_sub_sub_0_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_3 = atomics_a_mask_sub_sub_sub_0_1_3 \| _atomics_a_mask_sub_sub_acc_T_6; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_7 = atomics_a_mask_sub_sub_size_3 & atomics_a_mask_sub_sub_1_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_3 = atomics_a_mask_sub_sub_sub_0_1_3 \| _atomics_a_mask_sub_sub_acc_T_7; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size_3 = atomics_a_mask_sizeOH_3[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_3 = ~atomics_a_mask_sub_bit_3; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_3 = atomics_a_mask_sub_sub_0_2_3 & atomics_a_mask_sub_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_12 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_0_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_3 = atomics_a_mask_sub_sub_0_1_3 \| _atomics_a_mask_sub_acc_T_12; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_3 = atomics_a_mask_sub_sub_0_2_3 & atomics_a_mask_sub_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_13 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_1_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_3 = atomics_a_mask_sub_sub_0_1_3 \| _atomics_a_mask_sub_acc_T_13; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_3 = atomics_a_mask_sub_sub_1_2_3 & atomics_a_mask_sub_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_14 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_2_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_3 = atomics_a_mask_sub_sub_1_1_3 \| _atomics_a_mask_sub_acc_T_14; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_3 = atomics_a_mask_sub_sub_1_2_3 & atomics_a_mask_sub_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_15 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_3_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_3 = atomics_a_mask_sub_sub_1_1_3 \| _atomics_a_mask_sub_acc_T_15; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_3 = atomics_a_mask_sizeOH_3[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_3 = ~atomics_a_mask_bit_3; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_24 = atomics_a_mask_sub_0_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_24 = atomics_a_mask_size_3 & atomics_a_mask_eq_24; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_24 = atomics_a_mask_sub_0_1_3 \| _atomics_a_mask_acc_T_24; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_25 = atomics_a_mask_sub_0_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_25 = atomics_a_mask_size_3 & atomics_a_mask_eq_25; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_25 = atomics_a_mask_sub_0_1_3 \| _atomics_a_mask_acc_T_25; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_26 = atomics_a_mask_sub_1_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_26 = atomics_a_mask_size_3 & atomics_a_mask_eq_26; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_26 = atomics_a_mask_sub_1_1_3 \| _atomics_a_mask_acc_T_26; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_27 = atomics_a_mask_sub_1_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_27 = atomics_a_mask_size_3 & atomics_a_mask_eq_27; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_27 = atomics_a_mask_sub_1_1_3 \| _atomics_a_mask_acc_T_27; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_28 = atomics_a_mask_sub_2_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_28 = atomics_a_mask_size_3 & atomics_a_mask_eq_28; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_28 = atomics_a_mask_sub_2_1_3 \| _atomics_a_mask_acc_T_28; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_29 = atomics_a_mask_sub_2_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_29 = atomics_a_mask_size_3 & atomics_a_mask_eq_29; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_29 = atomics_a_mask_sub_2_1_3 \| _atomics_a_mask_acc_T_29; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_30 = atomics_a_mask_sub_3_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_30 = atomics_a_mask_size_3 & atomics_a_mask_eq_30; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_30 = atomics_a_mask_sub_3_1_3 \| _atomics_a_mask_acc_T_30; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_31 = atomics_a_mask_sub_3_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_31 = atomics_a_mask_size_3 & atomics_a_mask_eq_31; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_31 = atomics_a_mask_sub_3_1_3 \| _atomics_a_mask_acc_T_31; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_3 = {atomics_a_mask_acc_25, atomics_a_mask_acc_24}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_3 = {atomics_a_mask_acc_27, atomics_a_mask_acc_26}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_3 = {atomics_a_mask_lo_hi_3, atomics_a_mask_lo_lo_3}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_3 = {atomics_a_mask_acc_29, atomics_a_mask_acc_28}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_3 = {atomics_a_mask_acc_31, atomics_a_mask_acc_30}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_3 = {atomics_a_mask_hi_hi_3, atomics_a_mask_hi_lo_3}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_3 = {atomics_a_mask_hi_3, atomics_a_mask_lo_3}; // @[Misc.scala:222:10] assign atomics_a_3_mask = _atomics_a_mask_T_3; // @[Misc.scala:222:10] wire [34:0] _atomics_legal_T_45 = {1'h0, _atomics_legal_T_44}; // @[Parameters.scala:137:{31,41}] wire [7:0] _atomics_a_mask_T_4; // @[Misc.scala:222:10] wire [7:0] atomics_a_4_mask; // @[Edges.scala:517:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_4 = _atomics_a_mask_sizeOH_T_12[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_13 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_4; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_14 = _atomics_a_mask_sizeOH_T_13[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH_4 = {_atomics_a_mask_sizeOH_T_14[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1_4 = &req_uop_mem_size; // @[Misc.scala:206:21] wire atomics_a_mask_sub_sub_size_4 = atomics_a_mask_sizeOH_4[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2_4 = atomics_a_mask_sub_sub_bit_4; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit_4 = ~atomics_a_mask_sub_sub_bit_4; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_4 = atomics_a_mask_sub_sub_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_8 = atomics_a_mask_sub_sub_size_4 & atomics_a_mask_sub_sub_0_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_4 = atomics_a_mask_sub_sub_sub_0_1_4 \| _atomics_a_mask_sub_sub_acc_T_8; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_9 = atomics_a_mask_sub_sub_size_4 & atomics_a_mask_sub_sub_1_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_4 = atomics_a_mask_sub_sub_sub_0_1_4 \| _atomics_a_mask_sub_sub_acc_T_9; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size_4 = atomics_a_mask_sizeOH_4[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_4 = ~atomics_a_mask_sub_bit_4; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_4 = atomics_a_mask_sub_sub_0_2_4 & atomics_a_mask_sub_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_16 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_0_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_4 = atomics_a_mask_sub_sub_0_1_4 \| _atomics_a_mask_sub_acc_T_16; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_4 = atomics_a_mask_sub_sub_0_2_4 & atomics_a_mask_sub_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_17 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_1_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_4 = atomics_a_mask_sub_sub_0_1_4 \| _atomics_a_mask_sub_acc_T_17; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_4 = atomics_a_mask_sub_sub_1_2_4 & atomics_a_mask_sub_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_18 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_2_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_4 = atomics_a_mask_sub_sub_1_1_4 \| _atomics_a_mask_sub_acc_T_18; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_4 = atomics_a_mask_sub_sub_1_2_4 & atomics_a_mask_sub_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_19 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_3_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_4 = atomics_a_mask_sub_sub_1_1_4 \| _atomics_a_mask_sub_acc_T_19; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_4 = atomics_a_mask_sizeOH_4[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_4 = ~atomics_a_mask_bit_4; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_32 = atomics_a_mask_sub_0_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_32 = atomics_a_mask_size_4 & atomics_a_mask_eq_32; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_32 = atomics_a_mask_sub_0_1_4 \| _atomics_a_mask_acc_T_32; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_33 = atomics_a_mask_sub_0_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_33 = atomics_a_mask_size_4 & atomics_a_mask_eq_33; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_33 = atomics_a_mask_sub_0_1_4 \| _atomics_a_mask_acc_T_33; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_34 = atomics_a_mask_sub_1_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_34 = atomics_a_mask_size_4 & atomics_a_mask_eq_34; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_34 = atomics_a_mask_sub_1_1_4 \| _atomics_a_mask_acc_T_34; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_35 = atomics_a_mask_sub_1_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_35 = atomics_a_mask_size_4 & atomics_a_mask_eq_35; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_35 = atomics_a_mask_sub_1_1_4 \| _atomics_a_mask_acc_T_35; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_36 = atomics_a_mask_sub_2_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_36 = atomics_a_mask_size_4 & atomics_a_mask_eq_36; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_36 = atomics_a_mask_sub_2_1_4 \| _atomics_a_mask_acc_T_36; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_37 = atomics_a_mask_sub_2_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_37 = atomics_a_mask_size_4 & atomics_a_mask_eq_37; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_37 = atomics_a_mask_sub_2_1_4 \| _atomics_a_mask_acc_T_37; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_38 = atomics_a_mask_sub_3_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_38 = atomics_a_mask_size_4 & atomics_a_mask_eq_38; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_38 = atomics_a_mask_sub_3_1_4 \| _atomics_a_mask_acc_T_38; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_39 = atomics_a_mask_sub_3_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_39 = atomics_a_mask_size_4 & atomics_a_mask_eq_39; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_39 = atomics_a_mask_sub_3_1_4 \| _atomics_a_mask_acc_T_39; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_4 = {atomics_a_mask_acc_33, atomics_a_mask_acc_32}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_4 = {atomics_a_mask_acc_35, atomics_a_mask_acc_34}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_4 = {atomics_a_mask_lo_hi_4, atomics_a_mask_lo_lo_4}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_4 = {atomics_a_mask_acc_37, atomics_a_mask_acc_36}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_4 = {atomics_a_mask_acc_39, atomics_a_mask_acc_38}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_4 = {atomics_a_mask_hi_hi_4, atomics_a_mask_hi_lo_4}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_4 = {atomics_a_mask_hi_4, atomics_a_mask_lo_4}; // @[Misc.scala:222:10] assign atomics_a_4_mask = _atomics_a_mask_T_4; // @[Misc.scala:222:10] wire [34:0] _atomics_legal_T_55 = {1'h0, _atomics_legal_T_54}; // @[Parameters.scala:137:{31,41}] wire [7:0] _atomics_a_mask_T_5; // @[Misc.scala:222:10] wire [7:0] atomics_a_5_mask; // @[Edges.scala:517:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_5 = _atomics_a_mask_sizeOH_T_15[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_16 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_5; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_17 = _atomics_a_mask_sizeOH_T_16[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH_5 = {_atomics_a_mask_sizeOH_T_17[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1_5 = &req_uop_mem_size; // @[Misc.scala:206:21] wire atomics_a_mask_sub_sub_size_5 = atomics_a_mask_sizeOH_5[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2_5 = atomics_a_mask_sub_sub_bit_5; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit_5 = ~atomics_a_mask_sub_sub_bit_5; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_5 = atomics_a_mask_sub_sub_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_10 = atomics_a_mask_sub_sub_size_5 & atomics_a_mask_sub_sub_0_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_5 = atomics_a_mask_sub_sub_sub_0_1_5 \| _atomics_a_mask_sub_sub_acc_T_10; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_11 = atomics_a_mask_sub_sub_size_5 & atomics_a_mask_sub_sub_1_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_5 = atomics_a_mask_sub_sub_sub_0_1_5 \| _atomics_a_mask_sub_sub_acc_T_11; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size_5 = atomics_a_mask_sizeOH_5[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_5 = ~atomics_a_mask_sub_bit_5; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_5 = atomics_a_mask_sub_sub_0_2_5 & atomics_a_mask_sub_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_20 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_0_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_5 = atomics_a_mask_sub_sub_0_1_5 \| _atomics_a_mask_sub_acc_T_20; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_5 = atomics_a_mask_sub_sub_0_2_5 & atomics_a_mask_sub_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_21 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_1_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_5 = atomics_a_mask_sub_sub_0_1_5 \| _atomics_a_mask_sub_acc_T_21; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_5 = atomics_a_mask_sub_sub_1_2_5 & atomics_a_mask_sub_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_22 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_2_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_5 = atomics_a_mask_sub_sub_1_1_5 \| _atomics_a_mask_sub_acc_T_22; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_5 = atomics_a_mask_sub_sub_1_2_5 & atomics_a_mask_sub_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_23 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_3_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_5 = atomics_a_mask_sub_sub_1_1_5 \| _atomics_a_mask_sub_acc_T_23; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_5 = atomics_a_mask_sizeOH_5[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_5 = ~atomics_a_mask_bit_5; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_40 = atomics_a_mask_sub_0_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_40 = atomics_a_mask_size_5 & atomics_a_mask_eq_40; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_40 = atomics_a_mask_sub_0_1_5 \| _atomics_a_mask_acc_T_40; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_41 = atomics_a_mask_sub_0_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_41 = atomics_a_mask_size_5 & atomics_a_mask_eq_41; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_41 = atomics_a_mask_sub_0_1_5 \| _atomics_a_mask_acc_T_41; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_42 = atomics_a_mask_sub_1_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_42 = atomics_a_mask_size_5 & atomics_a_mask_eq_42; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_42 = atomics_a_mask_sub_1_1_5 \| _atomics_a_mask_acc_T_42; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_43 = atomics_a_mask_sub_1_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_43 = atomics_a_mask_size_5 & atomics_a_mask_eq_43; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_43 = atomics_a_mask_sub_1_1_5 \| _atomics_a_mask_acc_T_43; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_44 = atomics_a_mask_sub_2_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_44 = atomics_a_mask_size_5 & atomics_a_mask_eq_44; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_44 = atomics_a_mask_sub_2_1_5 \| _atomics_a_mask_acc_T_44; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_45 = atomics_a_mask_sub_2_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_45 = atomics_a_mask_size_5 & atomics_a_mask_eq_45; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_45 = atomics_a_mask_sub_2_1_5 \| _atomics_a_mask_acc_T_45; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_46 = atomics_a_mask_sub_3_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_46 = atomics_a_mask_size_5 & atomics_a_mask_eq_46; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_46 = atomics_a_mask_sub_3_1_5 \| _atomics_a_mask_acc_T_46; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_47 = atomics_a_mask_sub_3_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_47 = atomics_a_mask_size_5 & atomics_a_mask_eq_47; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_47 = atomics_a_mask_sub_3_1_5 \| _atomics_a_mask_acc_T_47; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_5 = {atomics_a_mask_acc_41, atomics_a_mask_acc_40}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_5 = {atomics_a_mask_acc_43, atomics_a_mask_acc_42}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_5 = {atomics_a_mask_lo_hi_5, atomics_a_mask_lo_lo_5}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_5 = {atomics_a_mask_acc_45, atomics_a_mask_acc_44}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_5 = {atomics_a_mask_acc_47, atomics_a_mask_acc_46}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_5 = {atomics_a_mask_hi_hi_5, atomics_a_mask_hi_lo_5}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_5 = {atomics_a_mask_hi_5, atomics_a_mask_lo_5}; // @[Misc.scala:222:10] assign atomics_a_5_mask = _atomics_a_mask_T_5; // @[Misc.scala:222:10] wire [34:0] _atomics_legal_T_65 = {1'h0, _atomics_legal_T_64}; // @[Parameters.scala:137:{31,41}] wire [7:0] _atomics_a_mask_T_6; // @[Misc.scala:222:10] wire [7:0] atomics_a_6_mask; // @[Edges.scala:517:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_6 = _atomics_a_mask_sizeOH_T_18[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_19 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_6; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_20 = _atomics_a_mask_sizeOH_T_19[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH_6 = {_atomics_a_mask_sizeOH_T_20[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1_6 = &req_uop_mem_size; // @[Misc.scala:206:21] wire atomics_a_mask_sub_sub_size_6 = atomics_a_mask_sizeOH_6[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2_6 = atomics_a_mask_sub_sub_bit_6; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit_6 = ~atomics_a_mask_sub_sub_bit_6; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_6 = atomics_a_mask_sub_sub_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_12 = atomics_a_mask_sub_sub_size_6 & atomics_a_mask_sub_sub_0_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_6 = atomics_a_mask_sub_sub_sub_0_1_6 \| _atomics_a_mask_sub_sub_acc_T_12; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_13 = atomics_a_mask_sub_sub_size_6 & atomics_a_mask_sub_sub_1_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_6 = atomics_a_mask_sub_sub_sub_0_1_6 \| _atomics_a_mask_sub_sub_acc_T_13; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size_6 = atomics_a_mask_sizeOH_6[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_6 = ~atomics_a_mask_sub_bit_6; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_6 = atomics_a_mask_sub_sub_0_2_6 & atomics_a_mask_sub_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_24 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_0_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_6 = atomics_a_mask_sub_sub_0_1_6 \| _atomics_a_mask_sub_acc_T_24; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_6 = atomics_a_mask_sub_sub_0_2_6 & atomics_a_mask_sub_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_25 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_1_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_6 = atomics_a_mask_sub_sub_0_1_6 \| _atomics_a_mask_sub_acc_T_25; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_6 = atomics_a_mask_sub_sub_1_2_6 & atomics_a_mask_sub_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_26 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_2_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_6 = atomics_a_mask_sub_sub_1_1_6 \| _atomics_a_mask_sub_acc_T_26; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_6 = atomics_a_mask_sub_sub_1_2_6 & atomics_a_mask_sub_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_27 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_3_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_6 = atomics_a_mask_sub_sub_1_1_6 \| _atomics_a_mask_sub_acc_T_27; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_6 = atomics_a_mask_sizeOH_6[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_6 = ~atomics_a_mask_bit_6; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_48 = atomics_a_mask_sub_0_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_48 = atomics_a_mask_size_6 & atomics_a_mask_eq_48; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_48 = atomics_a_mask_sub_0_1_6 \| _atomics_a_mask_acc_T_48; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_49 = atomics_a_mask_sub_0_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_49 = atomics_a_mask_size_6 & atomics_a_mask_eq_49; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_49 = atomics_a_mask_sub_0_1_6 \| _atomics_a_mask_acc_T_49; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_50 = atomics_a_mask_sub_1_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_50 = atomics_a_mask_size_6 & atomics_a_mask_eq_50; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_50 = atomics_a_mask_sub_1_1_6 \| _atomics_a_mask_acc_T_50; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_51 = atomics_a_mask_sub_1_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_51 = atomics_a_mask_size_6 & atomics_a_mask_eq_51; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_51 = atomics_a_mask_sub_1_1_6 \| _atomics_a_mask_acc_T_51; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_52 = atomics_a_mask_sub_2_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_52 = atomics_a_mask_size_6 & atomics_a_mask_eq_52; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_52 = atomics_a_mask_sub_2_1_6 \| _atomics_a_mask_acc_T_52; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_53 = atomics_a_mask_sub_2_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_53 = atomics_a_mask_size_6 & atomics_a_mask_eq_53; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_53 = atomics_a_mask_sub_2_1_6 \| _atomics_a_mask_acc_T_53; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_54 = atomics_a_mask_sub_3_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_54 = atomics_a_mask_size_6 & atomics_a_mask_eq_54; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_54 = atomics_a_mask_sub_3_1_6 \| _atomics_a_mask_acc_T_54; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_55 = atomics_a_mask_sub_3_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_55 = atomics_a_mask_size_6 & atomics_a_mask_eq_55; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_55 = atomics_a_mask_sub_3_1_6 \| _atomics_a_mask_acc_T_55; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_6 = {atomics_a_mask_acc_49, atomics_a_mask_acc_48}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_6 = {atomics_a_mask_acc_51, atomics_a_mask_acc_50}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_6 = {atomics_a_mask_lo_hi_6, atomics_a_mask_lo_lo_6}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_6 = {atomics_a_mask_acc_53, atomics_a_mask_acc_52}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_6 = {atomics_a_mask_acc_55, atomics_a_mask_acc_54}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_6 = {atomics_a_mask_hi_hi_6, atomics_a_mask_hi_lo_6}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_6 = {atomics_a_mask_hi_6, atomics_a_mask_lo_6}; // @[Misc.scala:222:10] assign atomics_a_6_mask = _atomics_a_mask_T_6; // @[Misc.scala:222:10] wire [34:0] _atomics_legal_T_75 = {1'h0, _atomics_legal_T_74}; // @[Parameters.scala:137:{31,41}] wire [7:0] _atomics_a_mask_T_7; // @[Misc.scala:222:10] wire [7:0] atomics_a_7_mask; // @[Edges.scala:517:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_7 = _atomics_a_mask_sizeOH_T_21[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_22 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_7; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_23 = _atomics_a_mask_sizeOH_T_22[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH_7 = {_atomics_a_mask_sizeOH_T_23[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1_7 = &req_uop_mem_size; // @[Misc.scala:206:21] wire atomics_a_mask_sub_sub_size_7 = atomics_a_mask_sizeOH_7[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2_7 = atomics_a_mask_sub_sub_bit_7; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit_7 = ~atomics_a_mask_sub_sub_bit_7; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_7 = atomics_a_mask_sub_sub_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_14 = atomics_a_mask_sub_sub_size_7 & atomics_a_mask_sub_sub_0_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_7 = atomics_a_mask_sub_sub_sub_0_1_7 \| _atomics_a_mask_sub_sub_acc_T_14; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_15 = atomics_a_mask_sub_sub_size_7 & atomics_a_mask_sub_sub_1_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_7 = atomics_a_mask_sub_sub_sub_0_1_7 \| _atomics_a_mask_sub_sub_acc_T_15; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size_7 = atomics_a_mask_sizeOH_7[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_7 = ~atomics_a_mask_sub_bit_7; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_7 = atomics_a_mask_sub_sub_0_2_7 & atomics_a_mask_sub_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_28 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_0_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_7 = atomics_a_mask_sub_sub_0_1_7 \| _atomics_a_mask_sub_acc_T_28; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_7 = atomics_a_mask_sub_sub_0_2_7 & atomics_a_mask_sub_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_29 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_1_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_7 = atomics_a_mask_sub_sub_0_1_7 \| _atomics_a_mask_sub_acc_T_29; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_7 = atomics_a_mask_sub_sub_1_2_7 & atomics_a_mask_sub_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_30 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_2_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_7 = atomics_a_mask_sub_sub_1_1_7 \| _atomics_a_mask_sub_acc_T_30; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_7 = atomics_a_mask_sub_sub_1_2_7 & atomics_a_mask_sub_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_31 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_3_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_7 = atomics_a_mask_sub_sub_1_1_7 \| _atomics_a_mask_sub_acc_T_31; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_7 = atomics_a_mask_sizeOH_7[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_7 = ~atomics_a_mask_bit_7; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_56 = atomics_a_mask_sub_0_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_56 = atomics_a_mask_size_7 & atomics_a_mask_eq_56; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_56 = atomics_a_mask_sub_0_1_7 \| _atomics_a_mask_acc_T_56; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_57 = atomics_a_mask_sub_0_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_57 = atomics_a_mask_size_7 & atomics_a_mask_eq_57; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_57 = atomics_a_mask_sub_0_1_7 \| _atomics_a_mask_acc_T_57; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_58 = atomics_a_mask_sub_1_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_58 = atomics_a_mask_size_7 & atomics_a_mask_eq_58; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_58 = atomics_a_mask_sub_1_1_7 \| _atomics_a_mask_acc_T_58; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_59 = atomics_a_mask_sub_1_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_59 = atomics_a_mask_size_7 & atomics_a_mask_eq_59; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_59 = atomics_a_mask_sub_1_1_7 \| _atomics_a_mask_acc_T_59; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_60 = atomics_a_mask_sub_2_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_60 = atomics_a_mask_size_7 & atomics_a_mask_eq_60; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_60 = atomics_a_mask_sub_2_1_7 \| _atomics_a_mask_acc_T_60; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_61 = atomics_a_mask_sub_2_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_61 = atomics_a_mask_size_7 & atomics_a_mask_eq_61; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_61 = atomics_a_mask_sub_2_1_7 \| _atomics_a_mask_acc_T_61; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_62 = atomics_a_mask_sub_3_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_62 = atomics_a_mask_size_7 & atomics_a_mask_eq_62; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_62 = atomics_a_mask_sub_3_1_7 \| _atomics_a_mask_acc_T_62; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_63 = atomics_a_mask_sub_3_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_63 = atomics_a_mask_size_7 & atomics_a_mask_eq_63; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_63 = atomics_a_mask_sub_3_1_7 \| _atomics_a_mask_acc_T_63; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_7 = {atomics_a_mask_acc_57, atomics_a_mask_acc_56}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_7 = {atomics_a_mask_acc_59, atomics_a_mask_acc_58}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_7 = {atomics_a_mask_lo_hi_7, atomics_a_mask_lo_lo_7}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_7 = {atomics_a_mask_acc_61, atomics_a_mask_acc_60}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_7 = {atomics_a_mask_acc_63, atomics_a_mask_acc_62}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_7 = {atomics_a_mask_hi_hi_7, atomics_a_mask_hi_lo_7}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_7 = {atomics_a_mask_hi_7, atomics_a_mask_lo_7}; // @[Misc.scala:222:10] assign atomics_a_7_mask = _atomics_a_mask_T_7; // @[Misc.scala:222:10] wire [34:0] _atomics_legal_T_85 = {1'h0, _atomics_legal_T_84}; // @[Parameters.scala:137:{31,41}] wire [7:0] _atomics_a_mask_T_8; // @[Misc.scala:222:10] wire [7:0] atomics_a_8_mask; // @[Edges.scala:517:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_8 = _atomics_a_mask_sizeOH_T_24[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_25 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_8; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_26 = _atomics_a_mask_sizeOH_T_25[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH_8 = {_atomics_a_mask_sizeOH_T_26[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1_8 = &req_uop_mem_size; // @[Misc.scala:206:21] wire atomics_a_mask_sub_sub_size_8 = atomics_a_mask_sizeOH_8[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2_8 = atomics_a_mask_sub_sub_bit_8; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit_8 = ~atomics_a_mask_sub_sub_bit_8; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_8 = atomics_a_mask_sub_sub_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_16 = atomics_a_mask_sub_sub_size_8 & atomics_a_mask_sub_sub_0_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_8 = atomics_a_mask_sub_sub_sub_0_1_8 \| _atomics_a_mask_sub_sub_acc_T_16; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_17 = atomics_a_mask_sub_sub_size_8 & atomics_a_mask_sub_sub_1_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_8 = atomics_a_mask_sub_sub_sub_0_1_8 \| _atomics_a_mask_sub_sub_acc_T_17; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size_8 = atomics_a_mask_sizeOH_8[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_8 = ~atomics_a_mask_sub_bit_8; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_8 = atomics_a_mask_sub_sub_0_2_8 & atomics_a_mask_sub_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_32 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_0_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_8 = atomics_a_mask_sub_sub_0_1_8 \| _atomics_a_mask_sub_acc_T_32; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_8 = atomics_a_mask_sub_sub_0_2_8 & atomics_a_mask_sub_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_33 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_1_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_8 = atomics_a_mask_sub_sub_0_1_8 \| _atomics_a_mask_sub_acc_T_33; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_8 = atomics_a_mask_sub_sub_1_2_8 & atomics_a_mask_sub_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_34 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_2_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_8 = atomics_a_mask_sub_sub_1_1_8 \| _atomics_a_mask_sub_acc_T_34; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_8 = atomics_a_mask_sub_sub_1_2_8 & atomics_a_mask_sub_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_35 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_3_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_8 = atomics_a_mask_sub_sub_1_1_8 \| _atomics_a_mask_sub_acc_T_35; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_8 = atomics_a_mask_sizeOH_8[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_8 = ~atomics_a_mask_bit_8; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_64 = atomics_a_mask_sub_0_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_64 = atomics_a_mask_size_8 & atomics_a_mask_eq_64; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_64 = atomics_a_mask_sub_0_1_8 \| _atomics_a_mask_acc_T_64; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_65 = atomics_a_mask_sub_0_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_65 = atomics_a_mask_size_8 & atomics_a_mask_eq_65; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_65 = atomics_a_mask_sub_0_1_8 \| _atomics_a_mask_acc_T_65; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_66 = atomics_a_mask_sub_1_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_66 = atomics_a_mask_size_8 & atomics_a_mask_eq_66; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_66 = atomics_a_mask_sub_1_1_8 \| _atomics_a_mask_acc_T_66; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_67 = atomics_a_mask_sub_1_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_67 = atomics_a_mask_size_8 & atomics_a_mask_eq_67; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_67 = atomics_a_mask_sub_1_1_8 \| _atomics_a_mask_acc_T_67; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_68 = atomics_a_mask_sub_2_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_68 = atomics_a_mask_size_8 & atomics_a_mask_eq_68; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_68 = atomics_a_mask_sub_2_1_8 \| _atomics_a_mask_acc_T_68; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_69 = atomics_a_mask_sub_2_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_69 = atomics_a_mask_size_8 & atomics_a_mask_eq_69; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_69 = atomics_a_mask_sub_2_1_8 \| _atomics_a_mask_acc_T_69; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_70 = atomics_a_mask_sub_3_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_70 = atomics_a_mask_size_8 & atomics_a_mask_eq_70; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_70 = atomics_a_mask_sub_3_1_8 \| _atomics_a_mask_acc_T_70; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_71 = atomics_a_mask_sub_3_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_71 = atomics_a_mask_size_8 & atomics_a_mask_eq_71; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_71 = atomics_a_mask_sub_3_1_8 \| _atomics_a_mask_acc_T_71; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_8 = {atomics_a_mask_acc_65, atomics_a_mask_acc_64}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_8 = {atomics_a_mask_acc_67, atomics_a_mask_acc_66}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_8 = {atomics_a_mask_lo_hi_8, atomics_a_mask_lo_lo_8}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_8 = {atomics_a_mask_acc_69, atomics_a_mask_acc_68}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_8 = {atomics_a_mask_acc_71, atomics_a_mask_acc_70}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_8 = {atomics_a_mask_hi_hi_8, atomics_a_mask_hi_lo_8}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_8 = {atomics_a_mask_hi_8, atomics_a_mask_lo_8}; // @[Misc.scala:222:10] assign atomics_a_8_mask = _atomics_a_mask_T_8; // @[Misc.scala:222:10] wire _T_17 = req_uop_mem_cmd == 5'h4; // @[mshrs.scala:421:16, :439:75] wire _atomics_T; // @[mshrs.scala:439:75] assign _atomics_T = _T_17; // @[mshrs.scala:439:75] wire _io_mem_access_bits_T; // @[package.scala:16:47] assign _io_mem_access_bits_T = _T_17; // @[package.scala:16:47] wire _io_mem_access_bits_T_24; // @[package.scala:16:47] assign _io_mem_access_bits_T_24 = _T_17; // @[package.scala:16:47] wire _send_resp_T_7; // @[package.scala:16:47] assign _send_resp_T_7 = _T_17; // @[package.scala:16:47] wire [2:0] _GEN_4 = _atomics_T ? 3'h3 : 3'h0; // @[mshrs.scala:439:75] wire [2:0] _atomics_T_1_opcode; // @[mshrs.scala:439:75] assign _atomics_T_1_opcode = _GEN_4; // @[mshrs.scala:439:75] wire [2:0] _atomics_T_1_param; // @[mshrs.scala:439:75] assign _atomics_T_1_param = _GEN_4; // @[mshrs.scala:439:75] wire [3:0] _atomics_T_1_size = _atomics_T ? atomics_a_size : 4'h0; // @[Edges.scala:534:17] wire [3:0] _atomics_T_1_source = _atomics_T ? 4'h9 : 4'h0; // @[mshrs.scala:439:75] wire [31:0] _atomics_T_1_address = _atomics_T ? atomics_a_address : 32'h0; // @[Edges.scala:534:17] wire [7:0] _atomics_T_1_mask = _atomics_T ? atomics_a_mask : 8'h0; // @[Edges.scala:534:17] wire [63:0] _atomics_T_1_data = _atomics_T ? atomics_a_data : 64'h0; // @[Edges.scala:534:17] wire _T_18 = req_uop_mem_cmd == 5'h9; // @[mshrs.scala:421:16, :439:75] wire _atomics_T_2; // @[mshrs.scala:439:75] assign _atomics_T_2 = _T_18; // @[mshrs.scala:439:75] wire _io_mem_access_bits_T_1; // @[package.scala:16:47] assign _io_mem_access_bits_T_1 = _T_18; // @[package.scala:16:47] wire _io_mem_access_bits_T_25; // @[package.scala:16:47] assign _io_mem_access_bits_T_25 = _T_18; // @[package.scala:16:47] wire _send_resp_T_8; // @[package.scala:16:47] assign _send_resp_T_8 = _T_18; // @[package.scala:16:47] wire [2:0] _atomics_T_3_opcode = _atomics_T_2 ? 3'h3 : _atomics_T_1_opcode; // @[mshrs.scala:439:75] wire [2:0] _atomics_T_3_param = _atomics_T_2 ? 3'h0 : _atomics_T_1_param; // @[mshrs.scala:439:75] wire [3:0] _atomics_T_3_size = _atomics_T_2 ? atomics_a_1_size : _atomics_T_1_size; // @[Edges.scala:534:17] wire [3:0] _atomics_T_3_source = _atomics_T_2 ? 4'h9 : _atomics_T_1_source; // @[mshrs.scala:439:75] wire [31:0] _atomics_T_3_address = _atomics_T_2 ? atomics_a_1_address : _atomics_T_1_address; // @[Edges.scala:534:17] wire [7:0] _atomics_T_3_mask = _atomics_T_2 ? atomics_a_1_mask : _atomics_T_1_mask; // @[Edges.scala:534:17] wire [63:0] _atomics_T_3_data = _atomics_T_2 ? atomics_a_1_data : _atomics_T_1_data; // @[Edges.scala:534:17] wire _T_19 = req_uop_mem_cmd == 5'hA; // @[mshrs.scala:421:16, :439:75] wire _atomics_T_4; // @[mshrs.scala:439:75] assign _atomics_T_4 = _T_19; // @[mshrs.scala:439:75] wire _io_mem_access_bits_T_2; // @[package.scala:16:47] assign _io_mem_access_bits_T_2 = _T_19; // @[package.scala:16:47] wire _io_mem_access_bits_T_26; // @[package.scala:16:47] assign _io_mem_access_bits_T_26 = _T_19; // @[package.scala:16:47] wire _send_resp_T_9; // @[package.scala:16:47] assign _send_resp_T_9 = _T_19; // @[package.scala:16:47] wire [2:0] _atomics_T_5_opcode = _atomics_T_4 ? 3'h3 : _atomics_T_3_opcode; // @[mshrs.scala:439:75] wire [2:0] _atomics_T_5_param = _atomics_T_4 ? 3'h1 : _atomics_T_3_param; // @[mshrs.scala:439:75] wire [3:0] _atomics_T_5_size = _atomics_T_4 ? atomics_a_2_size : _atomics_T_3_size; // @[Edges.scala:534:17] wire [3:0] _atomics_T_5_source = _atomics_T_4 ? 4'h9 : _atomics_T_3_source; // @[mshrs.scala:439:75] wire [31:0] _atomics_T_5_address = _atomics_T_4 ? atomics_a_2_address : _atomics_T_3_address; // @[Edges.scala:534:17] wire [7:0] _atomics_T_5_mask = _atomics_T_4 ? atomics_a_2_mask : _atomics_T_3_mask; // @[Edges.scala:534:17] wire [63:0] _atomics_T_5_data = _atomics_T_4 ? atomics_a_2_data : _atomics_T_3_data; // @[Edges.scala:534:17] wire _T_20 = req_uop_mem_cmd == 5'hB; // @[mshrs.scala:421:16, :439:75] wire _atomics_T_6; // @[mshrs.scala:439:75] assign _atomics_T_6 = _T_20; // @[mshrs.scala:439:75] wire _io_mem_access_bits_T_3; // @[package.scala:16:47] assign _io_mem_access_bits_T_3 = _T_20; // @[package.scala:16:47] wire _io_mem_access_bits_T_27; // @[package.scala:16:47] assign _io_mem_access_bits_T_27 = _T_20; // @[package.scala:16:47] wire _send_resp_T_10; // @[package.scala:16:47] assign _send_resp_T_10 = _T_20; // @[package.scala:16:47] wire [2:0] _atomics_T_7_opcode = _atomics_T_6 ? 3'h3 : _atomics_T_5_opcode; // @[mshrs.scala:439:75] wire [2:0] _atomics_T_7_param = _atomics_T_6 ? 3'h2 : _atomics_T_5_param; // @[mshrs.scala:439:75] wire [3:0] _atomics_T_7_size = _atomics_T_6 ? atomics_a_3_size : _atomics_T_5_size; // @[Edges.scala:534:17] wire [3:0] _atomics_T_7_source = _atomics_T_6 ? 4'h9 : _atomics_T_5_source; // @[mshrs.scala:439:75] wire [31:0] _atomics_T_7_address = _atomics_T_6 ? atomics_a_3_address : _atomics_T_5_address; // @[Edges.scala:534:17] wire [7:0] _atomics_T_7_mask = _atomics_T_6 ? atomics_a_3_mask : _atomics_T_5_mask; // @[Edges.scala:534:17] wire [63:0] _atomics_T_7_data = _atomics_T_6 ? atomics_a_3_data : _atomics_T_5_data; // @[Edges.scala:534:17] wire _T_24 = req_uop_mem_cmd == 5'h8; // @[mshrs.scala:421:16, :439:75] wire _atomics_T_8; // @[mshrs.scala:439:75] assign _atomics_T_8 = _T_24; // @[mshrs.scala:439:75] wire _io_mem_access_bits_T_7; // @[package.scala:16:47] assign _io_mem_access_bits_T_7 = _T_24; // @[package.scala:16:47] wire _io_mem_access_bits_T_31; // @[package.scala:16:47] assign _io_mem_access_bits_T_31 = _T_24; // @[package.scala:16:47] wire _send_resp_T_14; // @[package.scala:16:47] assign _send_resp_T_14 = _T_24; // @[package.scala:16:47] wire [2:0] _atomics_T_9_opcode = _atomics_T_8 ? 3'h2 : _atomics_T_7_opcode; // @[mshrs.scala:439:75] wire [2:0] _atomics_T_9_param = _atomics_T_8 ? 3'h4 : _atomics_T_7_param; // @[mshrs.scala:439:75] wire [3:0] _atomics_T_9_size = _atomics_T_8 ? atomics_a_4_size : _atomics_T_7_size; // @[Edges.scala:517:17] wire [3:0] _atomics_T_9_source = _atomics_T_8 ? 4'h9 : _atomics_T_7_source; // @[mshrs.scala:439:75] wire [31:0] _atomics_T_9_address = _atomics_T_8 ? atomics_a_4_address : _atomics_T_7_address; // @[Edges.scala:517:17] wire [7:0] _atomics_T_9_mask = _atomics_T_8 ? atomics_a_4_mask : _atomics_T_7_mask; // @[Edges.scala:517:17] wire [63:0] _atomics_T_9_data = _atomics_T_8 ? atomics_a_4_data : _atomics_T_7_data; // @[Edges.scala:517:17] wire _T_25 = req_uop_mem_cmd == 5'hC; // @[mshrs.scala:421:16, :439:75] wire _atomics_T_10; // @[mshrs.scala:439:75] assign _atomics_T_10 = _T_25; // @[mshrs.scala:439:75] wire _io_mem_access_bits_T_8; // @[package.scala:16:47] assign _io_mem_access_bits_T_8 = _T_25; // @[package.scala:16:47] wire _io_mem_access_bits_T_32; // @[package.scala:16:47] assign _io_mem_access_bits_T_32 = _T_25; // @[package.scala:16:47] wire _send_resp_T_15; // @[package.scala:16:47] assign _send_resp_T_15 = _T_25; // @[package.scala:16:47] wire [2:0] _atomics_T_11_opcode = _atomics_T_10 ? 3'h2 : _atomics_T_9_opcode; // @[mshrs.scala:439:75] wire [2:0] _atomics_T_11_param = _atomics_T_10 ? 3'h0 : _atomics_T_9_param; // @[mshrs.scala:439:75] wire [3:0] _atomics_T_11_size = _atomics_T_10 ? atomics_a_5_size : _atomics_T_9_size; // @[Edges.scala:517:17] wire [3:0] _atomics_T_11_source = _atomics_T_10 ? 4'h9 : _atomics_T_9_source; // @[mshrs.scala:439:75] wire [31:0] _atomics_T_11_address = _atomics_T_10 ? atomics_a_5_address : _atomics_T_9_address; // @[Edges.scala:517:17] wire [7:0] _atomics_T_11_mask = _atomics_T_10 ? atomics_a_5_mask : _atomics_T_9_mask; // @[Edges.scala:517:17] wire [63:0] _atomics_T_11_data = _atomics_T_10 ? atomics_a_5_data : _atomics_T_9_data; // @[Edges.scala:517:17] wire _T_26 = req_uop_mem_cmd == 5'hD; // @[mshrs.scala:421:16, :439:75] wire _atomics_T_12; // @[mshrs.scala:439:75] assign _atomics_T_12 = _T_26; // @[mshrs.scala:439:75] wire _io_mem_access_bits_T_9; // @[package.scala:16:47] assign _io_mem_access_bits_T_9 = _T_26; // @[package.scala:16:47] wire _io_mem_access_bits_T_33; // @[package.scala:16:47] assign _io_mem_access_bits_T_33 = _T_26; // @[package.scala:16:47] wire _send_resp_T_16; // @[package.scala:16:47] assign _send_resp_T_16 = _T_26; // @[package.scala:16:47] wire [2:0] _atomics_T_13_opcode = _atomics_T_12 ? 3'h2 : _atomics_T_11_opcode; // @[mshrs.scala:439:75] wire [2:0] _atomics_T_13_param = _atomics_T_12 ? 3'h1 : _atomics_T_11_param; // @[mshrs.scala:439:75] wire [3:0] _atomics_T_13_size = _atomics_T_12 ? atomics_a_6_size : _atomics_T_11_size; // @[Edges.scala:517:17] wire [3:0] _atomics_T_13_source = _atomics_T_12 ? 4'h9 : _atomics_T_11_source; // @[mshrs.scala:439:75] wire [31:0] _atomics_T_13_address = _atomics_T_12 ? atomics_a_6_address : _atomics_T_11_address; // @[Edges.scala:517:17] wire [7:0] _atomics_T_13_mask = _atomics_T_12 ? atomics_a_6_mask : _atomics_T_11_mask; // @[Edges.scala:517:17] wire [63:0] _atomics_T_13_data = _atomics_T_12 ? atomics_a_6_data : _atomics_T_11_data; // @[Edges.scala:517:17] wire _T_27 = req_uop_mem_cmd == 5'hE; // @[mshrs.scala:421:16, :439:75] wire _atomics_T_14; // @[mshrs.scala:439:75] assign _atomics_T_14 = _T_27; // @[mshrs.scala:439:75] wire _io_mem_access_bits_T_10; // @[package.scala:16:47] assign _io_mem_access_bits_T_10 = _T_27; // @[package.scala:16:47] wire _io_mem_access_bits_T_34; // @[package.scala:16:47] assign _io_mem_access_bits_T_34 = _T_27; // @[package.scala:16:47] wire _send_resp_T_17; // @[package.scala:16:47] assign _send_resp_T_17 = _T_27; // @[package.scala:16:47] wire [2:0] _atomics_T_15_opcode = _atomics_T_14 ? 3'h2 : _atomics_T_13_opcode; // @[mshrs.scala:439:75] wire [2:0] _atomics_T_15_param = _atomics_T_14 ? 3'h2 : _atomics_T_13_param; // @[mshrs.scala:439:75] wire [3:0] _atomics_T_15_size = _atomics_T_14 ? atomics_a_7_size : _atomics_T_13_size; // @[Edges.scala:517:17] wire [3:0] _atomics_T_15_source = _atomics_T_14 ? 4'h9 : _atomics_T_13_source; // @[mshrs.scala:439:75] wire [31:0] _atomics_T_15_address = _atomics_T_14 ? atomics_a_7_address : _atomics_T_13_address; // @[Edges.scala:517:17] wire [7:0] _atomics_T_15_mask = _atomics_T_14 ? atomics_a_7_mask : _atomics_T_13_mask; // @[Edges.scala:517:17] wire [63:0] _atomics_T_15_data = _atomics_T_14 ? atomics_a_7_data : _atomics_T_13_data; // @[Edges.scala:517:17] wire _T_28 = req_uop_mem_cmd == 5'hF; // @[mshrs.scala:421:16, :439:75] wire _atomics_T_16; // @[mshrs.scala:439:75] assign _atomics_T_16 = _T_28; // @[mshrs.scala:439:75] wire _io_mem_access_bits_T_11; // @[package.scala:16:47] assign _io_mem_access_bits_T_11 = _T_28; // @[package.scala:16:47] wire _io_mem_access_bits_T_35; // @[package.scala:16:47] assign _io_mem_access_bits_T_35 = _T_28; // @[package.scala:16:47] wire _send_resp_T_18; // @[package.scala:16:47] assign _send_resp_T_18 = _T_28; // @[package.scala:16:47] wire [2:0] atomics_opcode = _atomics_T_16 ? 3'h2 : _atomics_T_15_opcode; // @[mshrs.scala:439:75] wire [2:0] atomics_param = _atomics_T_16 ? 3'h3 : _atomics_T_15_param; // @[mshrs.scala:439:75] wire [3:0] atomics_size = _atomics_T_16 ? atomics_a_8_size : _atomics_T_15_size; // @[Edges.scala:517:17] wire [3:0] atomics_source = _atomics_T_16 ? 4'h9 : _atomics_T_15_source; // @[mshrs.scala:439:75] wire [31:0] atomics_address = _atomics_T_16 ? atomics_a_8_address : _atomics_T_15_address; // @[Edges.scala:517:17] wire [7:0] atomics_mask = _atomics_T_16 ? atomics_a_8_mask : _atomics_T_15_mask; // @[Edges.scala:517:17] wire [63:0] atomics_data = _atomics_T_16 ? atomics_a_8_data : _atomics_T_15_data; // @[Edges.scala:517:17]
Generate the Verilog code corresponding to the following Chisel files. File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" / black /, label = (ei.manager.beatBytes 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red /, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" / green /) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" / yellow /, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /* Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /* Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph / def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File CacheCork.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{IdRange, RegionType, TransferSizes} import freechips.rocketchip.tilelink.TLMessages.{ AcquireBlock, AcquirePerm, Get, PutFullData, PutPartialData, Release, ReleaseData, Grant, GrantData, AccessAck, AccessAckData, ReleaseAck } import freechips.rocketchip.util.IDPool import freechips.rocketchip.util.DataToAugmentedData case class TLCacheCorkParams( unsafe: Boolean = false, sinkIds: Int = 8) class TLCacheCork(params: TLCacheCorkParams = TLCacheCorkParams())(implicit p: Parameters) extends LazyModule { val unsafe = params.unsafe val sinkIds = params.sinkIds val node = TLAdapterNode( clientFn = { case cp => cp.v1copy(clients = cp.clients.map { c => c.v1copy( supportsProbe = TransferSizes.none, sourceId = IdRange(c.sourceId.start2, c.sourceId.end2))})}, managerFn = { case mp => mp.v1copy( endSinkId = if (mp.managers.exists(_.regionType == RegionType.UNCACHED)) sinkIds else 0, managers = mp.managers.map { m => m.v1copy( supportsAcquireB = if (m.regionType == RegionType.UNCACHED) m.supportsGet else m.supportsAcquireB, supportsAcquireT = if (m.regionType == RegionType.UNCACHED) m.supportsPutFull.intersect(m.supportsGet) else m.supportsAcquireT, alwaysGrantsT = if (m.regionType == RegionType.UNCACHED) m.supportsPutFull else m.alwaysGrantsT)})}) lazy val module = new Impl class Impl extends LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => // If this adapter does not need to do anything, toss all the above work and just directly connect if (!edgeIn.manager.anySupportAcquireB) { out <> in } else { val clients = edgeIn.client.clients val caches = clients.filter(_.supports.probe) require (clients.size == 1 \|\| caches.size == 0 \|\| unsafe, s"Only one client can safely use a TLCacheCork; ${clients.map(_.name)}") require (caches.size <= 1 \|\| unsafe, s"Only one caching client allowed; ${clients.map(_.name)}") edgeOut.manager.managers.foreach { case m => require (!m.supportsAcquireB \|\| unsafe, s"Cannot support caches beyond the Cork; ${m.name}") require (m.regionType <= RegionType.UNCACHED) } // The Cork turns [Acquire=>Get] => [AccessAckData=>GrantData] // and [ReleaseData=>PutFullData] => [AccessAck=>ReleaseAck] // We need to encode information sufficient to reverse the transformation in output. // A caveat is that we get Acquire+Release with the same source and must keep the // source unique after transformation onto the A channel. // The coding scheme is: // Release, AcquireBlock.BtoT, AcquirePerm => instant response // Put{Full,Partial}Data: 1, ReleaseData: 0 => AccessAck // {Arithmetic,Logical}Data,Get: 0, Acquire: 1 => AccessAckData // Hint:0 => HintAck // The CacheCork can potentially send the same source twice if a client sends // simultaneous Release and AMO/Get with the same source. It will still correctly // decode the messages based on the D.opcode, but the double use violates the spec. // Fortunately, no masters we know of behave this way! // Take requests from A to A or D (if BtoT Acquire) val a_a = Wire(chiselTypeOf(out.a)) val a_d = Wire(chiselTypeOf(in.d)) val isPut = in.a.bits.opcode === PutFullData \|\| in.a.bits.opcode === PutPartialData val toD = (in.a.bits.opcode === AcquireBlock && in.a.bits.param === TLPermissions.BtoT) \|\| (in.a.bits.opcode === AcquirePerm) in.a.ready := Mux(toD, a_d.ready, a_a.ready) a_a.valid := in.a.valid && !toD a_a.bits := in.a.bits a_a.bits.source := in.a.bits.source << 1 \| Mux(isPut, 1.U, 0.U) // Transform Acquire into Get when (in.a.bits.opcode === AcquireBlock \|\| in.a.bits.opcode === AcquirePerm) { a_a.bits.opcode := Get a_a.bits.param := 0.U a_a.bits.source := in.a.bits.source << 1 \| 1.U } // Upgrades are instantly successful a_d.valid := in.a.valid && toD a_d.bits := edgeIn.Grant( fromSink = 0.U, toSource = in.a.bits.source, lgSize = in.a.bits.size, capPermissions = TLPermissions.toT) // Take ReleaseData from C to A; Release from C to D val c_a = Wire(chiselTypeOf(out.a)) c_a.valid := in.c.valid && in.c.bits.opcode === ReleaseData c_a.bits := edgeOut.Put( fromSource = in.c.bits.source << 1, toAddress = in.c.bits.address, lgSize = in.c.bits.size, data = in.c.bits.data, corrupt = in.c.bits.corrupt)._2 c_a.bits.user :<= in.c.bits.user // Releases without Data succeed instantly val c_d = Wire(chiselTypeOf(in.d)) c_d.valid := in.c.valid && in.c.bits.opcode === Release c_d.bits := edgeIn.ReleaseAck(in.c.bits) assert (!in.c.valid \|\| in.c.bits.opcode === Release \|\| in.c.bits.opcode === ReleaseData) in.c.ready := Mux(in.c.bits.opcode === Release, c_d.ready, c_a.ready) // Discard E in.e.ready := true.B // Block B; should never happen out.b.ready := false.B assert (!out.b.valid) // Track in-flight sinkIds val pool = Module(new IDPool(sinkIds)) pool.io.free.valid := in.e.fire pool.io.free.bits := in.e.bits.sink val in_d = Wire(chiselTypeOf(in.d)) val d_first = edgeOut.first(in_d) val d_grant = in_d.bits.opcode === GrantData \|\| in_d.bits.opcode === Grant pool.io.alloc.ready := in.d.fire && d_first && d_grant in.d.valid := in_d.valid && (pool.io.alloc.valid \|\| !d_first \|\| !d_grant) in_d.ready := in.d.ready && (pool.io.alloc.valid \|\| !d_first \|\| !d_grant) in.d.bits := in_d.bits in.d.bits.sink := pool.io.alloc.bits holdUnless d_first // Take responses from D and transform them val d_d = Wire(chiselTypeOf(in.d)) d_d <> out.d d_d.bits.source := out.d.bits.source >> 1 // Record if a target was writable and auto-promote toT if it was // This is structured so that the vector can be constant prop'd away val wSourceVec = Reg(Vec(edgeIn.client.endSourceId, Bool())) val aWOk = edgeIn.manager.fastProperty(in.a.bits.address, !_.supportsPutFull.none, (b:Boolean) => b.B) val dWOk = wSourceVec(d_d.bits.source) val bypass = (edgeIn.manager.minLatency == 0).B && in.a.valid && in.a.bits.source === d_d.bits.source val dWHeld = Mux(bypass, aWOk, dWOk) holdUnless d_first when (in.a.fire) { wSourceVec(in.a.bits.source) := aWOk } // Wipe out any unused registers edgeIn.client.unusedSources.foreach { id => wSourceVec(id) := edgeIn.manager.anySupportPutFull.B } when (out.d.bits.opcode === AccessAckData && out.d.bits.source(0)) { d_d.bits.opcode := GrantData d_d.bits.param := Mux(dWHeld, TLPermissions.toT, TLPermissions.toB) } when (out.d.bits.opcode === AccessAck && !out.d.bits.source(0)) { d_d.bits.opcode := ReleaseAck } // Combine the sources of messages into the channels TLArbiter(TLArbiter.lowestIndexFirst)(out.a, (edgeOut.numBeats1(c_a.bits), c_a), (edgeOut.numBeats1(a_a.bits), a_a)) TLArbiter(TLArbiter.lowestIndexFirst)(in_d, (edgeIn .numBeats1(d_d.bits), d_d), (0.U, Queue(c_d, 2)), (0.U, Queue(a_d, 2))) // Tie off unused ports in.b.valid := false.B out.c.valid := false.B out.e.valid := false.B } } } } object TLCacheCork { def apply(params: TLCacheCorkParams)(implicit p: Parameters): TLNode = { val cork = LazyModule(new TLCacheCork(params)) cork.node } def apply(unsafe: Boolean = false, sinkIds: Int = 8)(implicit p: Parameters): TLNode = { apply(TLCacheCorkParams(unsafe, sinkIds)) } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } } File Arbiter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ object TLArbiter { // (valids, select) => readys type Policy = (Integer, UInt, Bool) => UInt val lowestIndexFirst: Policy = (width, valids, select) => ~(leftOR(valids) << 1)(width-1, 0) val highestIndexFirst: Policy = (width, valids, select) => ~((rightOR(valids) >> 1).pad(width)) val roundRobin: Policy = (width, valids, select) => if (width == 1) 1.U(1.W) else { val valid = valids(width-1, 0) assert (valid === valids) val mask = RegInit(((BigInt(1) << width)-1).U(width-1,0)) val filter = Cat(valid & ~mask, valid) val unready = (rightOR(filter, width2, width) >> 1) \| (mask << width) val readys = ~((unready >> width) & unready(width-1, 0)) when (select && valid.orR) { mask := leftOR(readys & valid, width) } readys(width-1, 0) } def lowestFromSeq[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: Seq[DecoupledIO[T]]): Unit = { apply(lowestIndexFirst)(sink, sources.map(s => (edge.numBeats1(s.bits), s)):_) } def lowest[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]): Unit = { apply(lowestIndexFirst)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_) } def highest[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]): Unit = { apply(highestIndexFirst)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_) } def robin[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]): Unit = { apply(roundRobin)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_) } def apply[T <: Data](policy: Policy)(sink: DecoupledIO[T], sources: (UInt, DecoupledIO[T])): Unit = { if (sources.isEmpty) { sink.bits := DontCare } else if (sources.size == 1) { sink :<>= sources.head._2 } else { val pairs = sources.toList val beatsIn = pairs.map(_._1) val sourcesIn = pairs.map(_._2) // The number of beats which remain to be sent val beatsLeft = RegInit(0.U) val idle = beatsLeft === 0.U val latch = idle && sink.ready // winner (if any) claims sink // Who wants access to the sink? val valids = sourcesIn.map(_.valid) // Arbitrate amongst the requests val readys = VecInit(policy(valids.size, Cat(valids.reverse), latch).asBools) // Which request wins arbitration? val winner = VecInit((readys zip valids) map { case (r,v) => r&&v }) // Confirm the policy works properly require (readys.size == valids.size) // Never two winners val prefixOR = winner.scanLeft(false.B)(_\|\|_).init assert((prefixOR zip winner) map { case (p,w) => !p \|\| !w } reduce {_ && _}) // If there was any request, there is a winner assert (!valids.reduce(_\|\|_) \|\| winner.reduce(_\|\|_)) // Track remaining beats val maskedBeats = (winner zip beatsIn) map { case (w,b) => Mux(w, b, 0.U) } val initBeats = maskedBeats.reduce(_ \| _) // no winner => 0 beats beatsLeft := Mux(latch, initBeats, beatsLeft - sink.fire) // The one-hot source granted access in the previous cycle val state = RegInit(VecInit(Seq.fill(sources.size)(false.B))) val muxState = Mux(idle, winner, state) state := muxState val allowed = Mux(idle, readys, state) (sourcesIn zip allowed) foreach { case (s, r) => s.ready := sink.ready && r } sink.valid := Mux(idle, valids.reduce(_\|\|_), Mux1H(state, valids)) sink.bits :<= Mux1H(muxState, sourcesIn.map(_.bits)) } } } // Synthesizable unit tests import freechips.rocketchip.unittest._ abstract class DecoupledArbiterTest( policy: TLArbiter.Policy, txns: Int, timeout: Int, val numSources: Int, beatsLeftFromIdx: Int => UInt) (implicit p: Parameters) extends UnitTest(timeout) { val sources = Wire(Vec(numSources, DecoupledIO(UInt(log2Ceil(numSources).W)))) dontTouch(sources.suggestName("sources")) val sink = Wire(DecoupledIO(UInt(log2Ceil(numSources).W))) dontTouch(sink.suggestName("sink")) val count = RegInit(0.U(log2Ceil(txns).W)) val lfsr = LFSR(16, true.B) sources.zipWithIndex.map { case (z, i) => z.bits := i.U } TLArbiter(policy)(sink, sources.zipWithIndex.map { case (z, i) => (beatsLeftFromIdx(i), z) }:_) count := count + 1.U io.finished := count >= txns.U } /** This tests that when a specific pattern of source valids are driven, * a new index from amongst that pattern is always selected, * unless one of those sources takes multiple beats, * in which case the same index should be selected until the arbiter goes idle. / class TLDecoupledArbiterRobinTest(txns: Int = 128, timeout: Int = 500000, print: Boolean = false) (implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.roundRobin, txns, timeout, 6, i => i.U) { val lastWinner = RegInit((numSources+1).U) val beatsLeft = RegInit(0.U(log2Ceil(numSources).W)) val first = lastWinner > numSources.U val valid = lfsr(0) val ready = lfsr(15) sink.ready := ready sources.zipWithIndex.map { // pattern: every even-indexed valid is driven the same random way case (s, i) => s.valid := (if (i % 2 == 1) false.B else valid) } when (sink.fire) { if (print) { printf("TestRobin: %d\n", sink.bits) } when (beatsLeft === 0.U) { assert(lastWinner =/= sink.bits, "Round robin did not pick a new idx despite one being valid.") lastWinner := sink.bits beatsLeft := sink.bits } .otherwise { assert(lastWinner === sink.bits, "Round robin did not pick the same index over multiple beats") beatsLeft := beatsLeft - 1.U } } if (print) { when (!sink.fire) { printf("TestRobin: idle (%d %d)\n", valid, ready) } } } /* This tests that the lowest index is always selected across random single cycle transactions. / class TLDecoupledArbiterLowestTest(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.lowestIndexFirst, txns, timeout, 15, _ => 0.U) { def assertLowest(id: Int): Unit = { when (sources(id).valid) { assert((numSources-1 until id by -1).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a higher valid source was granted ready.") } } sources.zipWithIndex.map { case (s, i) => s.valid := lfsr(i) } sink.ready := lfsr(15) when (sink.fire) { (0 until numSources).foreach(assertLowest(_)) } } /* This tests that the highest index is always selected across random single cycle transactions. */ class TLDecoupledArbiterHighestTest(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.highestIndexFirst, txns, timeout, 15, _ => 0.U) { def assertHighest(id: Int): Unit = { when (sources(id).valid) { assert((0 until id).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a lower valid source was granted ready.") } } sources.zipWithIndex.map { case (s, i) => s.valid := lfsr(i) } sink.ready := lfsr(15) when (sink.fire) { (0 until numSources).foreach(assertHighest(_)) } }	module TLCacheCork( // @[CacheCork.scala:42:9] input clock, // @[CacheCork.scala:42:9] input reset, // @[CacheCork.scala:42:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_in_c_ready, // @[LazyModuleImp.scala:107:25] input auto_in_c_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_in_c_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_c_bits_address, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_c_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_e_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_e_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire _q_1_io_deq_valid; // @[Decoupled.scala:362:21] wire [2:0] _q_1_io_deq_bits_opcode; // @[Decoupled.scala:362:21] wire [1:0] _q_1_io_deq_bits_param; // @[Decoupled.scala:362:21] wire [2:0] _q_1_io_deq_bits_size; // @[Decoupled.scala:362:21] wire [4:0] _q_1_io_deq_bits_source; // @[Decoupled.scala:362:21] wire [2:0] _q_1_io_deq_bits_sink; // @[Decoupled.scala:362:21] wire _q_1_io_deq_bits_denied; // @[Decoupled.scala:362:21] wire [63:0] _q_1_io_deq_bits_data; // @[Decoupled.scala:362:21] wire _q_1_io_deq_bits_corrupt; // @[Decoupled.scala:362:21] wire _q_io_deq_valid; // @[Decoupled.scala:362:21] wire [2:0] _q_io_deq_bits_opcode; // @[Decoupled.scala:362:21] wire [1:0] _q_io_deq_bits_param; // @[Decoupled.scala:362:21] wire [2:0] _q_io_deq_bits_size; // @[Decoupled.scala:362:21] wire [4:0] _q_io_deq_bits_source; // @[Decoupled.scala:362:21] wire [2:0] _q_io_deq_bits_sink; // @[Decoupled.scala:362:21] wire _q_io_deq_bits_denied; // @[Decoupled.scala:362:21] wire [63:0] _q_io_deq_bits_data; // @[Decoupled.scala:362:21] wire _q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21] wire _pool_io_alloc_valid; // @[CacheCork.scala:127:26] wire [2:0] _pool_io_alloc_bits; // @[CacheCork.scala:127:26] wire auto_in_a_valid_0 = auto_in_a_valid; // @[CacheCork.scala:42:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[CacheCork.scala:42:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[CacheCork.scala:42:9] wire [2:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[CacheCork.scala:42:9] wire [4:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[CacheCork.scala:42:9] wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[CacheCork.scala:42:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[CacheCork.scala:42:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[CacheCork.scala:42:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[CacheCork.scala:42:9] wire auto_in_c_valid_0 = auto_in_c_valid; // @[CacheCork.scala:42:9] wire [2:0] auto_in_c_bits_opcode_0 = auto_in_c_bits_opcode; // @[CacheCork.scala:42:9] wire [2:0] auto_in_c_bits_param_0 = auto_in_c_bits_param; // @[CacheCork.scala:42:9] wire [2:0] auto_in_c_bits_size_0 = auto_in_c_bits_size; // @[CacheCork.scala:42:9] wire [4:0] auto_in_c_bits_source_0 = auto_in_c_bits_source; // @[CacheCork.scala:42:9] wire [31:0] auto_in_c_bits_address_0 = auto_in_c_bits_address; // @[CacheCork.scala:42:9] wire [63:0] auto_in_c_bits_data_0 = auto_in_c_bits_data; // @[CacheCork.scala:42:9] wire auto_in_c_bits_corrupt_0 = auto_in_c_bits_corrupt; // @[CacheCork.scala:42:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[CacheCork.scala:42:9] wire auto_in_e_valid_0 = auto_in_e_valid; // @[CacheCork.scala:42:9] wire [2:0] auto_in_e_bits_sink_0 = auto_in_e_bits_sink; // @[CacheCork.scala:42:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[CacheCork.scala:42:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[CacheCork.scala:42:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[CacheCork.scala:42:9] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[CacheCork.scala:42:9] wire [2:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[CacheCork.scala:42:9] wire [5:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[CacheCork.scala:42:9] wire auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[CacheCork.scala:42:9] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[CacheCork.scala:42:9] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[CacheCork.scala:42:9] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[CacheCork.scala:42:9] wire auto_in_b_ready = 1'h1; // @[CacheCork.scala:42:9] wire auto_in_e_ready = 1'h1; // @[CacheCork.scala:42:9] wire nodeIn_b_ready = 1'h1; // @[MixedNode.scala:551:17] wire nodeIn_e_ready = 1'h1; // @[MixedNode.scala:551:17] wire _c_a_bits_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _c_a_bits_legal_T_8 = 1'h1; // @[Parameters.scala:137:59] wire _aWOk_T_4 = 1'h1; // @[Parameters.scala:137:59] wire _dWHeld_T = 1'h1; // @[CacheCork.scala:151:25] wire opdata = 1'h1; // @[Edges.scala:92:28] wire auto_in_b_valid = 1'h0; // @[CacheCork.scala:42:9] wire auto_in_b_bits_corrupt = 1'h0; // @[CacheCork.scala:42:9] wire nodeIn_b_valid = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_b_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire a_d_bits_denied = 1'h0; // @[CacheCork.scala:75:23] wire a_d_bits_corrupt = 1'h0; // @[CacheCork.scala:75:23] wire a_d_bits_d_denied = 1'h0; // @[Edges.scala:645:17] wire a_d_bits_d_corrupt = 1'h0; // @[Edges.scala:645:17] wire c_d_bits_denied = 1'h0; // @[CacheCork.scala:112:23] wire c_d_bits_corrupt = 1'h0; // @[CacheCork.scala:112:23] wire c_d_bits_d_denied = 1'h0; // @[Edges.scala:677:17] wire c_d_bits_d_corrupt = 1'h0; // @[Edges.scala:677:17] wire _bypass_T = 1'h0; // @[CacheCork.scala:150:57] wire bypass = 1'h0; // @[CacheCork.scala:150:71] wire _opdata_T = 1'h0; // @[Edges.scala:92:37] wire _state_WIRE_0 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_1 = 1'h0; // @[Arbiter.scala:88:34] wire maskedBeats_1_1 = 1'h0; // @[Arbiter.scala:82:69] wire maskedBeats_2 = 1'h0; // @[Arbiter.scala:82:69] wire _state_WIRE_1_0 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_1_1 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_1_2 = 1'h0; // @[Arbiter.scala:88:34] wire [2:0] auto_in_b_bits_opcode = 3'h0; // @[CacheCork.scala:42:9] wire [2:0] auto_in_b_bits_size = 3'h0; // @[CacheCork.scala:42:9] wire [2:0] nodeIn_b_bits_opcode = 3'h0; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_b_bits_size = 3'h0; // @[MixedNode.scala:551:17] wire [2:0] a_d_bits_sink = 3'h0; // @[CacheCork.scala:75:23] wire [2:0] a_d_bits_d_sink = 3'h0; // @[Edges.scala:645:17] wire [2:0] c_a_bits_opcode = 3'h0; // @[CacheCork.scala:101:23] wire [2:0] c_a_bits_param = 3'h0; // @[CacheCork.scala:101:23] wire [2:0] c_a_bits_a_opcode = 3'h0; // @[Edges.scala:480:17] wire [2:0] c_a_bits_a_param = 3'h0; // @[Edges.scala:480:17] wire [2:0] c_d_bits_sink = 3'h0; // @[CacheCork.scala:112:23] wire [2:0] c_d_bits_d_sink = 3'h0; // @[Edges.scala:677:17] wire [2:0] _nodeOut_a_bits_T_18 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _nodeOut_a_bits_T_21 = 3'h0; // @[Mux.scala:30:73] wire [1:0] auto_in_b_bits_param = 2'h0; // @[CacheCork.scala:42:9] wire [1:0] nodeIn_b_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] a_d_bits_param = 2'h0; // @[CacheCork.scala:75:23] wire [1:0] a_d_bits_d_param = 2'h0; // @[Edges.scala:645:17] wire [1:0] c_d_bits_param = 2'h0; // @[CacheCork.scala:112:23] wire [1:0] c_d_bits_d_param = 2'h0; // @[Edges.scala:677:17] wire [4:0] auto_in_b_bits_source = 5'h0; // @[CacheCork.scala:42:9] wire [4:0] nodeIn_b_bits_source = 5'h0; // @[MixedNode.scala:551:17] wire [31:0] auto_in_b_bits_address = 32'h0; // @[CacheCork.scala:42:9] wire [31:0] nodeIn_b_bits_address = 32'h0; // @[MixedNode.scala:551:17] wire [7:0] auto_in_b_bits_mask = 8'h0; // @[CacheCork.scala:42:9] wire [7:0] nodeIn_b_bits_mask = 8'h0; // @[MixedNode.scala:551:17] wire [63:0] auto_in_b_bits_data = 64'h0; // @[CacheCork.scala:42:9] wire [63:0] nodeIn_b_bits_data = 64'h0; // @[MixedNode.scala:551:17] wire [63:0] a_d_bits_data = 64'h0; // @[CacheCork.scala:75:23] wire [63:0] a_d_bits_d_data = 64'h0; // @[Edges.scala:645:17] wire [63:0] c_d_bits_data = 64'h0; // @[CacheCork.scala:112:23] wire [63:0] c_d_bits_d_data = 64'h0; // @[Edges.scala:677:17] wire [2:0] a_d_bits_opcode = 3'h4; // @[CacheCork.scala:75:23] wire [2:0] a_d_bits_d_opcode = 3'h4; // @[Edges.scala:645:17] wire [2:0] c_d_bits_opcode = 3'h6; // @[CacheCork.scala:112:23] wire [2:0] c_d_bits_d_opcode = 3'h6; // @[Edges.scala:677:17] wire [32:0] _c_a_bits_legal_T_6 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _c_a_bits_legal_T_7 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _aWOk_T_2 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _aWOk_T_3 = 33'h0; // @[Parameters.scala:137:46] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[CacheCork.scala:42:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[CacheCork.scala:42:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[CacheCork.scala:42:9] wire [2:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[CacheCork.scala:42:9] wire [4:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[CacheCork.scala:42:9] wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[CacheCork.scala:42:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[CacheCork.scala:42:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[CacheCork.scala:42:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[CacheCork.scala:42:9] wire nodeIn_c_ready; // @[MixedNode.scala:551:17] wire nodeIn_c_valid = auto_in_c_valid_0; // @[CacheCork.scala:42:9] wire [2:0] nodeIn_c_bits_opcode = auto_in_c_bits_opcode_0; // @[CacheCork.scala:42:9] wire [2:0] nodeIn_c_bits_param = auto_in_c_bits_param_0; // @[CacheCork.scala:42:9] wire [2:0] nodeIn_c_bits_size = auto_in_c_bits_size_0; // @[CacheCork.scala:42:9] wire [4:0] nodeIn_c_bits_source = auto_in_c_bits_source_0; // @[CacheCork.scala:42:9] wire [31:0] nodeIn_c_bits_address = auto_in_c_bits_address_0; // @[CacheCork.scala:42:9] wire [63:0] nodeIn_c_bits_data = auto_in_c_bits_data_0; // @[CacheCork.scala:42:9] wire nodeIn_c_bits_corrupt = auto_in_c_bits_corrupt_0; // @[CacheCork.scala:42:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[CacheCork.scala:42:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [4:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeIn_e_valid = auto_in_e_valid_0; // @[CacheCork.scala:42:9] wire [2:0] nodeIn_e_bits_sink = auto_in_e_bits_sink_0; // @[CacheCork.scala:42:9] wire nodeOut_a_ready = auto_out_a_ready_0; // @[CacheCork.scala:42:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [5:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[CacheCork.scala:42:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[CacheCork.scala:42:9] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[CacheCork.scala:42:9] wire [2:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[CacheCork.scala:42:9] wire [5:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[CacheCork.scala:42:9] wire nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[CacheCork.scala:42:9] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[CacheCork.scala:42:9] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[CacheCork.scala:42:9] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[CacheCork.scala:42:9] wire auto_in_a_ready_0; // @[CacheCork.scala:42:9] wire auto_in_c_ready_0; // @[CacheCork.scala:42:9] wire [2:0] auto_in_d_bits_opcode_0; // @[CacheCork.scala:42:9] wire [1:0] auto_in_d_bits_param_0; // @[CacheCork.scala:42:9] wire [2:0] auto_in_d_bits_size_0; // @[CacheCork.scala:42:9] wire [4:0] auto_in_d_bits_source_0; // @[CacheCork.scala:42:9] wire [2:0] auto_in_d_bits_sink_0; // @[CacheCork.scala:42:9] wire auto_in_d_bits_denied_0; // @[CacheCork.scala:42:9] wire [63:0] auto_in_d_bits_data_0; // @[CacheCork.scala:42:9] wire auto_in_d_bits_corrupt_0; // @[CacheCork.scala:42:9] wire auto_in_d_valid_0; // @[CacheCork.scala:42:9] wire [2:0] auto_out_a_bits_opcode_0; // @[CacheCork.scala:42:9] wire [2:0] auto_out_a_bits_param_0; // @[CacheCork.scala:42:9] wire [2:0] auto_out_a_bits_size_0; // @[CacheCork.scala:42:9] wire [5:0] auto_out_a_bits_source_0; // @[CacheCork.scala:42:9] wire [31:0] auto_out_a_bits_address_0; // @[CacheCork.scala:42:9] wire [7:0] auto_out_a_bits_mask_0; // @[CacheCork.scala:42:9] wire [63:0] auto_out_a_bits_data_0; // @[CacheCork.scala:42:9] wire auto_out_a_bits_corrupt_0; // @[CacheCork.scala:42:9] wire auto_out_a_valid_0; // @[CacheCork.scala:42:9] wire auto_out_d_ready_0; // @[CacheCork.scala:42:9] wire _nodeIn_a_ready_T; // @[CacheCork.scala:79:26] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[CacheCork.scala:42:9] wire [2:0] a_a_bits_size = nodeIn_a_bits_size; // @[CacheCork.scala:74:23] wire [2:0] a_d_bits_d_size = nodeIn_a_bits_size; // @[Edges.scala:645:17] wire [4:0] a_d_bits_d_source = nodeIn_a_bits_source; // @[Edges.scala:645:17] wire [31:0] a_a_bits_address = nodeIn_a_bits_address; // @[CacheCork.scala:74:23] wire [31:0] _aWOk_T = nodeIn_a_bits_address; // @[Parameters.scala:137:31] wire [7:0] a_a_bits_mask = nodeIn_a_bits_mask; // @[CacheCork.scala:74:23] wire [63:0] a_a_bits_data = nodeIn_a_bits_data; // @[CacheCork.scala:74:23] wire a_a_bits_corrupt = nodeIn_a_bits_corrupt; // @[CacheCork.scala:74:23] wire _nodeIn_c_ready_T_1; // @[CacheCork.scala:117:26] assign auto_in_c_ready_0 = nodeIn_c_ready; // @[CacheCork.scala:42:9] wire [2:0] c_a_bits_a_size = nodeIn_c_bits_size; // @[Edges.scala:480:17] wire [2:0] _c_a_bits_a_mask_sizeOH_T = nodeIn_c_bits_size; // @[Misc.scala:202:34] wire [2:0] c_d_bits_d_size = nodeIn_c_bits_size; // @[Edges.scala:677:17] wire [4:0] c_d_bits_d_source = nodeIn_c_bits_source; // @[Edges.scala:677:17] wire [31:0] _c_a_bits_legal_T_4 = nodeIn_c_bits_address; // @[Parameters.scala:137:31] wire [31:0] c_a_bits_a_address = nodeIn_c_bits_address; // @[Edges.scala:480:17] wire [63:0] c_a_bits_a_data = nodeIn_c_bits_data; // @[Edges.scala:480:17] wire c_a_bits_a_corrupt = nodeIn_c_bits_corrupt; // @[Edges.scala:480:17] wire _nodeIn_d_valid_T_4; // @[CacheCork.scala:135:34] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[CacheCork.scala:42:9] wire [2:0] in_d_bits_opcode; // @[CacheCork.scala:131:24] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[CacheCork.scala:42:9] wire [1:0] in_d_bits_param; // @[CacheCork.scala:131:24] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[CacheCork.scala:42:9] wire [2:0] in_d_bits_size; // @[CacheCork.scala:131:24] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[CacheCork.scala:42:9] wire [4:0] in_d_bits_source; // @[CacheCork.scala:131:24] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[CacheCork.scala:42:9] wire [2:0] _nodeIn_d_bits_sink_T; // @[package.scala:88:42] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[CacheCork.scala:42:9] wire in_d_bits_denied; // @[CacheCork.scala:131:24] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[CacheCork.scala:42:9] wire [63:0] in_d_bits_data; // @[CacheCork.scala:131:24] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[CacheCork.scala:42:9] wire in_d_bits_corrupt; // @[CacheCork.scala:131:24] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[CacheCork.scala:42:9] wire _pool_io_free_valid_T = nodeIn_e_valid; // @[Decoupled.scala:51:35] wire _nodeOut_a_valid_T_4; // @[Arbiter.scala:96:24] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[CacheCork.scala:42:9] wire [2:0] _nodeOut_a_bits_WIRE_opcode; // @[Mux.scala:30:73] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[CacheCork.scala:42:9] wire [2:0] _nodeOut_a_bits_WIRE_param; // @[Mux.scala:30:73] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[CacheCork.scala:42:9] wire [2:0] _nodeOut_a_bits_WIRE_size; // @[Mux.scala:30:73] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[CacheCork.scala:42:9] wire [5:0] _nodeOut_a_bits_WIRE_source; // @[Mux.scala:30:73] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[CacheCork.scala:42:9] wire [31:0] _nodeOut_a_bits_WIRE_address; // @[Mux.scala:30:73] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[CacheCork.scala:42:9] wire [7:0] _nodeOut_a_bits_WIRE_mask; // @[Mux.scala:30:73] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[CacheCork.scala:42:9] wire [63:0] _nodeOut_a_bits_WIRE_data; // @[Mux.scala:30:73] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[CacheCork.scala:42:9] wire _nodeOut_a_bits_WIRE_corrupt; // @[Mux.scala:30:73] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[CacheCork.scala:42:9] wire d_d_ready; // @[CacheCork.scala:141:23] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[CacheCork.scala:42:9] wire d_d_valid = nodeOut_d_valid; // @[CacheCork.scala:141:23] wire [2:0] d_d_bits_size = nodeOut_d_bits_size; // @[CacheCork.scala:141:23] wire d_d_bits_denied = nodeOut_d_bits_denied; // @[CacheCork.scala:141:23] wire [63:0] d_d_bits_data = nodeOut_d_bits_data; // @[CacheCork.scala:141:23] wire d_d_bits_corrupt = nodeOut_d_bits_corrupt; // @[CacheCork.scala:141:23] wire _a_a_ready_T; // @[Arbiter.scala:94:31] wire _a_a_valid_T_1; // @[CacheCork.scala:81:33] wire [2:0] a_a_bits_opcode; // @[CacheCork.scala:74:23] wire [2:0] a_a_bits_param; // @[CacheCork.scala:74:23] wire [5:0] a_a_bits_source; // @[CacheCork.scala:74:23] wire a_a_ready; // @[CacheCork.scala:74:23] wire a_a_valid; // @[CacheCork.scala:74:23] wire _a_d_valid_T; // @[CacheCork.scala:93:33] wire [2:0] a_d_bits_size; // @[CacheCork.scala:75:23] wire [4:0] a_d_bits_source; // @[CacheCork.scala:75:23] wire a_d_ready; // @[CacheCork.scala:75:23] wire a_d_valid; // @[CacheCork.scala:75:23] wire _isPut_T = nodeIn_a_bits_opcode == 3'h0; // @[CacheCork.scala:76:38] wire _isPut_T_1 = nodeIn_a_bits_opcode == 3'h1; // @[CacheCork.scala:76:74] wire isPut = _isPut_T \| _isPut_T_1; // @[CacheCork.scala:76:{38,54,74}] wire _a_a_bits_source_T_1 = isPut; // @[CacheCork.scala:76:54, :83:55] wire _toD_T = nodeIn_a_bits_opcode == 3'h6; // @[CacheCork.scala:77:37] wire _toD_T_1 = nodeIn_a_bits_param == 3'h2; // @[CacheCork.scala:77:73] wire _toD_T_2 = _toD_T & _toD_T_1; // @[CacheCork.scala:77:{37,54,73}] wire _toD_T_3 = &nodeIn_a_bits_opcode; // @[CacheCork.scala:78:37] wire toD = _toD_T_2 \| _toD_T_3; // @[CacheCork.scala:77:{54,97}, :78:37] assign _nodeIn_a_ready_T = toD ? a_d_ready : a_a_ready; // @[CacheCork.scala:74:23, :75:23, :77:97, :79:26] assign nodeIn_a_ready = _nodeIn_a_ready_T; // @[CacheCork.scala:79:26] wire _a_a_valid_T = ~toD; // @[CacheCork.scala:77:97, :81:36] assign _a_a_valid_T_1 = nodeIn_a_valid & _a_a_valid_T; // @[CacheCork.scala:81:{33,36}] assign a_a_valid = _a_a_valid_T_1; // @[CacheCork.scala:74:23, :81:33] wire [5:0] _GEN = {nodeIn_a_bits_source, 1'h0}; // @[CacheCork.scala:83:45] wire [5:0] _a_a_bits_source_T; // @[CacheCork.scala:83:45] assign _a_a_bits_source_T = _GEN; // @[CacheCork.scala:83:45] wire [5:0] _a_a_bits_source_T_3; // @[CacheCork.scala:89:47] assign _a_a_bits_source_T_3 = _GEN; // @[CacheCork.scala:83:45, :89:47] wire [5:0] _a_a_bits_source_T_2 = {_a_a_bits_source_T[5:1], _a_a_bits_source_T[0] \| _a_a_bits_source_T_1}; // @[CacheCork.scala:83:{45,50,55}] wire _T_2 = _toD_T \| (&nodeIn_a_bits_opcode); // @[CacheCork.scala:77:37, :78:37, :86:49] assign a_a_bits_opcode = _T_2 ? 3'h4 : nodeIn_a_bits_opcode; // @[CacheCork.scala:74:23, :82:18, :86:{49,86}, :87:27] assign a_a_bits_param = _T_2 ? 3'h0 : nodeIn_a_bits_param; // @[CacheCork.scala:74:23, :82:18, :86:{49,86}, :88:27] wire [5:0] _a_a_bits_source_T_4 = {_a_a_bits_source_T_3[5:1], 1'h1}; // @[CacheCork.scala:89:{47,52}] assign a_a_bits_source = _T_2 ? _a_a_bits_source_T_4 : _a_a_bits_source_T_2; // @[CacheCork.scala:74:23, :83:{25,50}, :86:{49,86}, :89:{27,52}] assign _a_d_valid_T = nodeIn_a_valid & toD; // @[CacheCork.scala:77:97, :93:33] assign a_d_valid = _a_d_valid_T; // @[CacheCork.scala:75:23, :93:33] assign a_d_bits_size = a_d_bits_d_size; // @[Edges.scala:645:17] assign a_d_bits_source = a_d_bits_d_source; // @[Edges.scala:645:17] wire _c_a_ready_T; // @[Arbiter.scala:94:31] wire _c_a_valid_T_1; // @[CacheCork.scala:102:33] wire [5:0] c_a_bits_a_source; // @[Edges.scala:480:17] wire [7:0] c_a_bits_a_mask; // @[Edges.scala:480:17] wire [2:0] c_a_bits_size; // @[CacheCork.scala:101:23] wire [5:0] c_a_bits_source; // @[CacheCork.scala:101:23] wire [31:0] c_a_bits_address; // @[CacheCork.scala:101:23] wire [7:0] c_a_bits_mask; // @[CacheCork.scala:101:23] wire [63:0] c_a_bits_data; // @[CacheCork.scala:101:23] wire c_a_bits_corrupt; // @[CacheCork.scala:101:23] wire c_a_ready; // @[CacheCork.scala:101:23] wire c_a_valid; // @[CacheCork.scala:101:23] wire _c_a_valid_T = &nodeIn_c_bits_opcode; // @[CacheCork.scala:102:53] assign _c_a_valid_T_1 = nodeIn_c_valid & _c_a_valid_T; // @[CacheCork.scala:102:{33,53}] assign c_a_valid = _c_a_valid_T_1; // @[CacheCork.scala:101:23, :102:33] wire [5:0] _c_a_bits_T = {nodeIn_c_bits_source, 1'h0}; // @[CacheCork.scala:104:41] assign c_a_bits_a_source = _c_a_bits_T; // @[Edges.scala:480:17] wire _c_a_bits_legal_T_1 = nodeIn_c_bits_size != 3'h7; // @[Parameters.scala:92:38] wire _c_a_bits_legal_T_2 = _c_a_bits_legal_T_1; // @[Parameters.scala:92:{33,38}] wire _c_a_bits_legal_T_3 = _c_a_bits_legal_T_2; // @[Parameters.scala:684:29] wire _c_a_bits_legal_T_9 = _c_a_bits_legal_T_3; // @[Parameters.scala:684:{29,54}] wire [32:0] _c_a_bits_legal_T_5 = {1'h0, _c_a_bits_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire c_a_bits_legal = _c_a_bits_legal_T_9; // @[Parameters.scala:684:54, :686:26] assign c_a_bits_size = c_a_bits_a_size; // @[Edges.scala:480:17] assign c_a_bits_source = c_a_bits_a_source; // @[Edges.scala:480:17] assign c_a_bits_address = c_a_bits_a_address; // @[Edges.scala:480:17] wire [7:0] _c_a_bits_a_mask_T; // @[Misc.scala:222:10] assign c_a_bits_mask = c_a_bits_a_mask; // @[Edges.scala:480:17] assign c_a_bits_data = c_a_bits_a_data; // @[Edges.scala:480:17] assign c_a_bits_corrupt = c_a_bits_a_corrupt; // @[Edges.scala:480:17] wire [1:0] c_a_bits_a_mask_sizeOH_shiftAmount = _c_a_bits_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _c_a_bits_a_mask_sizeOH_T_1 = 4'h1 << c_a_bits_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _c_a_bits_a_mask_sizeOH_T_2 = _c_a_bits_a_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] c_a_bits_a_mask_sizeOH = {_c_a_bits_a_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire c_a_bits_a_mask_sub_sub_sub_0_1 = nodeIn_c_bits_size > 3'h2; // @[Misc.scala:206:21] wire c_a_bits_a_mask_sub_sub_size = c_a_bits_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire c_a_bits_a_mask_sub_sub_bit = nodeIn_c_bits_address[2]; // @[Misc.scala:210:26] wire c_a_bits_a_mask_sub_sub_1_2 = c_a_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire c_a_bits_a_mask_sub_sub_nbit = ~c_a_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire c_a_bits_a_mask_sub_sub_0_2 = c_a_bits_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _c_a_bits_a_mask_sub_sub_acc_T = c_a_bits_a_mask_sub_sub_size & c_a_bits_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire c_a_bits_a_mask_sub_sub_0_1 = c_a_bits_a_mask_sub_sub_sub_0_1 \| _c_a_bits_a_mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _c_a_bits_a_mask_sub_sub_acc_T_1 = c_a_bits_a_mask_sub_sub_size & c_a_bits_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire c_a_bits_a_mask_sub_sub_1_1 = c_a_bits_a_mask_sub_sub_sub_0_1 \| _c_a_bits_a_mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire c_a_bits_a_mask_sub_size = c_a_bits_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire c_a_bits_a_mask_sub_bit = nodeIn_c_bits_address[1]; // @[Misc.scala:210:26] wire c_a_bits_a_mask_sub_nbit = ~c_a_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire c_a_bits_a_mask_sub_0_2 = c_a_bits_a_mask_sub_sub_0_2 & c_a_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _c_a_bits_a_mask_sub_acc_T = c_a_bits_a_mask_sub_size & c_a_bits_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire c_a_bits_a_mask_sub_0_1 = c_a_bits_a_mask_sub_sub_0_1 \| _c_a_bits_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire c_a_bits_a_mask_sub_1_2 = c_a_bits_a_mask_sub_sub_0_2 & c_a_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _c_a_bits_a_mask_sub_acc_T_1 = c_a_bits_a_mask_sub_size & c_a_bits_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire c_a_bits_a_mask_sub_1_1 = c_a_bits_a_mask_sub_sub_0_1 \| _c_a_bits_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire c_a_bits_a_mask_sub_2_2 = c_a_bits_a_mask_sub_sub_1_2 & c_a_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _c_a_bits_a_mask_sub_acc_T_2 = c_a_bits_a_mask_sub_size & c_a_bits_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire c_a_bits_a_mask_sub_2_1 = c_a_bits_a_mask_sub_sub_1_1 \| _c_a_bits_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire c_a_bits_a_mask_sub_3_2 = c_a_bits_a_mask_sub_sub_1_2 & c_a_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _c_a_bits_a_mask_sub_acc_T_3 = c_a_bits_a_mask_sub_size & c_a_bits_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire c_a_bits_a_mask_sub_3_1 = c_a_bits_a_mask_sub_sub_1_1 \| _c_a_bits_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire c_a_bits_a_mask_size = c_a_bits_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire c_a_bits_a_mask_bit = nodeIn_c_bits_address[0]; // @[Misc.scala:210:26] wire c_a_bits_a_mask_nbit = ~c_a_bits_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire c_a_bits_a_mask_eq = c_a_bits_a_mask_sub_0_2 & c_a_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _c_a_bits_a_mask_acc_T = c_a_bits_a_mask_size & c_a_bits_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire c_a_bits_a_mask_acc = c_a_bits_a_mask_sub_0_1 \| _c_a_bits_a_mask_acc_T; // @[Misc.scala:215:{29,38}] wire c_a_bits_a_mask_eq_1 = c_a_bits_a_mask_sub_0_2 & c_a_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _c_a_bits_a_mask_acc_T_1 = c_a_bits_a_mask_size & c_a_bits_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire c_a_bits_a_mask_acc_1 = c_a_bits_a_mask_sub_0_1 \| _c_a_bits_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire c_a_bits_a_mask_eq_2 = c_a_bits_a_mask_sub_1_2 & c_a_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _c_a_bits_a_mask_acc_T_2 = c_a_bits_a_mask_size & c_a_bits_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire c_a_bits_a_mask_acc_2 = c_a_bits_a_mask_sub_1_1 \| _c_a_bits_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire c_a_bits_a_mask_eq_3 = c_a_bits_a_mask_sub_1_2 & c_a_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _c_a_bits_a_mask_acc_T_3 = c_a_bits_a_mask_size & c_a_bits_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire c_a_bits_a_mask_acc_3 = c_a_bits_a_mask_sub_1_1 \| _c_a_bits_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire c_a_bits_a_mask_eq_4 = c_a_bits_a_mask_sub_2_2 & c_a_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _c_a_bits_a_mask_acc_T_4 = c_a_bits_a_mask_size & c_a_bits_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire c_a_bits_a_mask_acc_4 = c_a_bits_a_mask_sub_2_1 \| _c_a_bits_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire c_a_bits_a_mask_eq_5 = c_a_bits_a_mask_sub_2_2 & c_a_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _c_a_bits_a_mask_acc_T_5 = c_a_bits_a_mask_size & c_a_bits_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire c_a_bits_a_mask_acc_5 = c_a_bits_a_mask_sub_2_1 \| _c_a_bits_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire c_a_bits_a_mask_eq_6 = c_a_bits_a_mask_sub_3_2 & c_a_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _c_a_bits_a_mask_acc_T_6 = c_a_bits_a_mask_size & c_a_bits_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire c_a_bits_a_mask_acc_6 = c_a_bits_a_mask_sub_3_1 \| _c_a_bits_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire c_a_bits_a_mask_eq_7 = c_a_bits_a_mask_sub_3_2 & c_a_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _c_a_bits_a_mask_acc_T_7 = c_a_bits_a_mask_size & c_a_bits_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire c_a_bits_a_mask_acc_7 = c_a_bits_a_mask_sub_3_1 \| _c_a_bits_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] c_a_bits_a_mask_lo_lo = {c_a_bits_a_mask_acc_1, c_a_bits_a_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] c_a_bits_a_mask_lo_hi = {c_a_bits_a_mask_acc_3, c_a_bits_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] c_a_bits_a_mask_lo = {c_a_bits_a_mask_lo_hi, c_a_bits_a_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] c_a_bits_a_mask_hi_lo = {c_a_bits_a_mask_acc_5, c_a_bits_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] c_a_bits_a_mask_hi_hi = {c_a_bits_a_mask_acc_7, c_a_bits_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] c_a_bits_a_mask_hi = {c_a_bits_a_mask_hi_hi, c_a_bits_a_mask_hi_lo}; // @[Misc.scala:222:10] assign _c_a_bits_a_mask_T = {c_a_bits_a_mask_hi, c_a_bits_a_mask_lo}; // @[Misc.scala:222:10] assign c_a_bits_a_mask = _c_a_bits_a_mask_T; // @[Misc.scala:222:10] wire _c_d_valid_T_1; // @[CacheCork.scala:113:33] wire [2:0] c_d_bits_size; // @[CacheCork.scala:112:23] wire [4:0] c_d_bits_source; // @[CacheCork.scala:112:23] wire c_d_ready; // @[CacheCork.scala:112:23] wire c_d_valid; // @[CacheCork.scala:112:23] wire _T_4 = nodeIn_c_bits_opcode == 3'h6; // @[CacheCork.scala:113:53] wire _c_d_valid_T; // @[CacheCork.scala:113:53] assign _c_d_valid_T = _T_4; // @[CacheCork.scala:113:53] wire _nodeIn_c_ready_T; // @[CacheCork.scala:117:44] assign _nodeIn_c_ready_T = _T_4; // @[CacheCork.scala:113:53, :117:44] assign _c_d_valid_T_1 = nodeIn_c_valid & _c_d_valid_T; // @[CacheCork.scala:113:{33,53}] assign c_d_valid = _c_d_valid_T_1; // @[CacheCork.scala:112:23, :113:33] assign c_d_bits_size = c_d_bits_d_size; // @[Edges.scala:677:17] assign c_d_bits_source = c_d_bits_d_source; // @[Edges.scala:677:17] assign _nodeIn_c_ready_T_1 = _nodeIn_c_ready_T ? c_d_ready : c_a_ready; // @[CacheCork.scala:101:23, :112:23, :117:{26,44}] assign nodeIn_c_ready = _nodeIn_c_ready_T_1; // @[CacheCork.scala:117:26] wire _in_d_ready_T_4; // @[CacheCork.scala:136:34] wire _in_d_valid_T_7; // @[Arbiter.scala:96:24] wire [2:0] _in_d_bits_WIRE_opcode; // @[Mux.scala:30:73] assign nodeIn_d_bits_opcode = in_d_bits_opcode; // @[CacheCork.scala:131:24] wire [1:0] _in_d_bits_WIRE_param; // @[Mux.scala:30:73] assign nodeIn_d_bits_param = in_d_bits_param; // @[CacheCork.scala:131:24] wire [2:0] _in_d_bits_WIRE_size; // @[Mux.scala:30:73] assign nodeIn_d_bits_size = in_d_bits_size; // @[CacheCork.scala:131:24] wire [4:0] _in_d_bits_WIRE_source; // @[Mux.scala:30:73] assign nodeIn_d_bits_source = in_d_bits_source; // @[CacheCork.scala:131:24] wire [2:0] _in_d_bits_WIRE_sink; // @[Mux.scala:30:73] wire _in_d_bits_WIRE_denied; // @[Mux.scala:30:73] assign nodeIn_d_bits_denied = in_d_bits_denied; // @[CacheCork.scala:131:24] wire [63:0] _in_d_bits_WIRE_data; // @[Mux.scala:30:73] assign nodeIn_d_bits_data = in_d_bits_data; // @[CacheCork.scala:131:24] wire _in_d_bits_WIRE_corrupt; // @[Mux.scala:30:73] assign nodeIn_d_bits_corrupt = in_d_bits_corrupt; // @[CacheCork.scala:131:24] wire [2:0] in_d_bits_sink; // @[CacheCork.scala:131:24] wire in_d_ready; // @[CacheCork.scala:131:24] wire in_d_valid; // @[CacheCork.scala:131:24] wire _GEN_0 = in_d_ready & in_d_valid; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _GEN_0; // @[Decoupled.scala:51:35] wire _beatsLeft_T_4; // @[Decoupled.scala:51:35] assign _beatsLeft_T_4 = _GEN_0; // @[Decoupled.scala:51:35] wire [12:0] _d_first_beats1_decode_T = 13'h3F << in_d_bits_size; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = in_d_bits_opcode[0]; // @[Edges.scala:106:36] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire _d_grant_T = in_d_bits_opcode == 3'h5; // @[CacheCork.scala:131:24, :133:40] wire _d_grant_T_1 = in_d_bits_opcode == 3'h4; // @[CacheCork.scala:131:24, :133:74] wire d_grant = _d_grant_T \| _d_grant_T_1; // @[CacheCork.scala:133:{40,54,74}] wire _pool_io_alloc_ready_T = nodeIn_d_ready & nodeIn_d_valid; // @[Decoupled.scala:51:35] wire _pool_io_alloc_ready_T_1 = _pool_io_alloc_ready_T & d_first; // @[Decoupled.scala:51:35] wire _pool_io_alloc_ready_T_2 = _pool_io_alloc_ready_T_1 & d_grant; // @[CacheCork.scala:133:54, :134:{42,53}] wire _nodeIn_d_valid_T = ~d_first; // @[Edges.scala:231:25] wire _nodeIn_d_valid_T_1 = _pool_io_alloc_valid \| _nodeIn_d_valid_T; // @[CacheCork.scala:127:26, :135:{58,61}] wire _nodeIn_d_valid_T_2 = ~d_grant; // @[CacheCork.scala:133:54, :135:73] wire _nodeIn_d_valid_T_3 = _nodeIn_d_valid_T_1 \| _nodeIn_d_valid_T_2; // @[CacheCork.scala:135:{58,70,73}] assign _nodeIn_d_valid_T_4 = in_d_valid & _nodeIn_d_valid_T_3; // @[CacheCork.scala:131:24, :135:{34,70}] assign nodeIn_d_valid = _nodeIn_d_valid_T_4; // @[CacheCork.scala:135:34] wire _in_d_ready_T = ~d_first; // @[Edges.scala:231:25] wire _in_d_ready_T_1 = _pool_io_alloc_valid \| _in_d_ready_T; // @[CacheCork.scala:127:26, :136:{58,61}] wire _in_d_ready_T_2 = ~d_grant; // @[CacheCork.scala:133:54, :135:73, :136:73] wire _in_d_ready_T_3 = _in_d_ready_T_1 \| _in_d_ready_T_2; // @[CacheCork.scala:136:{58,70,73}] assign _in_d_ready_T_4 = nodeIn_d_ready & _in_d_ready_T_3; // @[CacheCork.scala:136:{34,70}] assign in_d_ready = _in_d_ready_T_4; // @[CacheCork.scala:131:24, :136:34] reg [2:0] nodeIn_d_bits_sink_r; // @[package.scala:88:63] assign _nodeIn_d_bits_sink_T = d_first ? _pool_io_alloc_bits : nodeIn_d_bits_sink_r; // @[package.scala:88:{42,63}] assign nodeIn_d_bits_sink = _nodeIn_d_bits_sink_T; // @[package.scala:88:42] wire _d_d_ready_T; // @[Arbiter.scala:94:31] assign nodeOut_d_ready = d_d_ready; // @[CacheCork.scala:141:23] wire [4:0] _d_d_bits_source_T; // @[CacheCork.scala:143:46] wire [2:0] d_d_bits_opcode; // @[CacheCork.scala:141:23] wire [1:0] d_d_bits_param; // @[CacheCork.scala:141:23] wire [4:0] d_d_bits_source; // @[CacheCork.scala:141:23] wire [2:0] d_d_bits_sink; // @[CacheCork.scala:141:23] assign d_d_bits_sink = {2'h0, nodeOut_d_bits_sink}; // @[CacheCork.scala:141:23, :142:13] assign _d_d_bits_source_T = nodeOut_d_bits_source[5:1]; // @[CacheCork.scala:143:46] assign d_d_bits_source = _d_d_bits_source_T; // @[CacheCork.scala:141:23, :143:46] wire [32:0] _aWOk_T_1 = {1'h0, _aWOk_T}; // @[Parameters.scala:137:{31,41}] wire _bypass_T_1 = nodeIn_a_bits_source == d_d_bits_source; // @[CacheCork.scala:141:23, :150:91] reg dWHeld_r; // @[package.scala:88:63] wire dWHeld = d_first ? _dWHeld_T : dWHeld_r; // @[package.scala:88:{42,63}] wire _T_18 = nodeOut_d_bits_opcode == 3'h1 & nodeOut_d_bits_source[0]; // @[CacheCork.scala:162:{33,51,71}] wire [1:0] _d_d_bits_param_T = {1'h0, ~dWHeld}; // @[package.scala:88:42] assign d_d_bits_param = _T_18 ? _d_d_bits_param_T : nodeOut_d_bits_param; // @[CacheCork.scala:141:23, :142:13, :162:{51,76}, :164:{26,32}] assign d_d_bits_opcode = nodeOut_d_bits_opcode == 3'h0 & ~(nodeOut_d_bits_source[0]) ? 3'h6 : _T_18 ? 3'h5 : nodeOut_d_bits_opcode; // @[CacheCork.scala:141:23, :142:13, :162:{51,71,76}, :163:27, :166:{33,47,50,73}, :167:27] wire [12:0] _decode_T = 13'h3F << c_a_bits_size; // @[package.scala:243:71] wire [5:0] _decode_T_1 = _decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _decode_T_2 = ~_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] decode = _decode_T_2[5:3]; // @[package.scala:243:46] wire [12:0] _decode_T_3 = 13'h3F << a_a_bits_size; // @[package.scala:243:71] wire [5:0] _decode_T_4 = _decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _decode_T_5 = ~_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] decode_1 = _decode_T_5[5:3]; // @[package.scala:243:46] wire _opdata_T_1 = a_a_bits_opcode[2]; // @[Edges.scala:92:37] wire opdata_1 = ~_opdata_T_1; // @[Edges.scala:92:{28,37}] reg [2:0] beatsLeft; // @[Arbiter.scala:60:30] wire idle = beatsLeft == 3'h0; // @[Arbiter.scala:60:30, :61:28] wire latch = idle & nodeOut_a_ready; // @[Arbiter.scala:61:28, :62:24] wire [1:0] _readys_T = {a_a_valid, c_a_valid}; // @[CacheCork.scala:74:23, :101:23] wire [2:0] _readys_T_1 = {_readys_T, 1'h0}; // @[package.scala:253:48] wire [1:0] _readys_T_2 = _readys_T_1[1:0]; // @[package.scala:253:{48,53}] wire [1:0] _readys_T_3 = _readys_T \| _readys_T_2; // @[package.scala:253:{43,53}] wire [1:0] _readys_T_4 = _readys_T_3; // @[package.scala:253:43, :254:17] wire [2:0] _readys_T_5 = {_readys_T_4, 1'h0}; // @[package.scala:254:17] wire [1:0] _readys_T_6 = _readys_T_5[1:0]; // @[Arbiter.scala:16:{78,83}] wire [1:0] _readys_T_7 = ~_readys_T_6; // @[Arbiter.scala:16:{61,83}] wire _readys_T_8 = _readys_T_7[0]; // @[Arbiter.scala:16:61, :68:76] wire readys_0 = _readys_T_8; // @[Arbiter.scala:68:{27,76}] wire _readys_T_9 = _readys_T_7[1]; // @[Arbiter.scala:16:61, :68:76] wire readys_1 = _readys_T_9; // @[Arbiter.scala:68:{27,76}] wire _winner_T = readys_0 & c_a_valid; // @[CacheCork.scala:101:23] wire winner_0 = _winner_T; // @[Arbiter.scala:71:{27,69}] wire _winner_T_1 = readys_1 & a_a_valid; // @[CacheCork.scala:74:23] wire winner_1 = _winner_T_1; // @[Arbiter.scala:71:{27,69}] wire prefixOR_1 = winner_0; // @[Arbiter.scala:71:27, :76:48] wire _prefixOR_T = prefixOR_1 \| winner_1; // @[Arbiter.scala:71:27, :76:48] wire _nodeOut_a_valid_T = c_a_valid \| a_a_valid; // @[CacheCork.scala:74:23, :101:23] wire [2:0] maskedBeats_0 = winner_0 ? decode : 3'h0; // @[Edges.scala:220:59, :221:14] wire [2:0] maskedBeats_1 = winner_1 & opdata_1 ? decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] wire [2:0] initBeats = maskedBeats_0 \| maskedBeats_1; // @[Arbiter.scala:82:69, :84:44] wire _beatsLeft_T = nodeOut_a_ready & nodeOut_a_valid; // @[Decoupled.scala:51:35] wire [3:0] _beatsLeft_T_1 = {1'h0, beatsLeft} - {3'h0, _beatsLeft_T}; // @[Decoupled.scala:51:35] wire [2:0] _beatsLeft_T_2 = _beatsLeft_T_1[2:0]; // @[Arbiter.scala:85:52] wire [2:0] _beatsLeft_T_3 = latch ? initBeats : _beatsLeft_T_2; // @[Arbiter.scala:62:24, :84:44, :85:{23,52}] reg state_0; // @[Arbiter.scala:88:26] reg state_1; // @[Arbiter.scala:88:26] wire muxState_0 = idle ? winner_0 : state_0; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire muxState_1 = idle ? winner_1 : state_1; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire allowed_0 = idle ? readys_0 : state_0; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] wire allowed_1 = idle ? readys_1 : state_1; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] assign _c_a_ready_T = nodeOut_a_ready & allowed_0; // @[Arbiter.scala:92:24, :94:31] assign c_a_ready = _c_a_ready_T; // @[CacheCork.scala:101:23] assign _a_a_ready_T = nodeOut_a_ready & allowed_1; // @[Arbiter.scala:92:24, :94:31] assign a_a_ready = _a_a_ready_T; // @[CacheCork.scala:74:23] wire _nodeOut_a_valid_T_1 = state_0 & c_a_valid; // @[Mux.scala:30:73] wire _nodeOut_a_valid_T_2 = state_1 & a_a_valid; // @[Mux.scala:30:73] wire _nodeOut_a_valid_T_3 = _nodeOut_a_valid_T_1 \| _nodeOut_a_valid_T_2; // @[Mux.scala:30:73] wire _nodeOut_a_valid_WIRE = _nodeOut_a_valid_T_3; // @[Mux.scala:30:73] assign _nodeOut_a_valid_T_4 = idle ? _nodeOut_a_valid_T : _nodeOut_a_valid_WIRE; // @[Mux.scala:30:73] assign nodeOut_a_valid = _nodeOut_a_valid_T_4; // @[Arbiter.scala:96:24] wire [2:0] _nodeOut_a_bits_WIRE_10; // @[Mux.scala:30:73] assign nodeOut_a_bits_opcode = _nodeOut_a_bits_WIRE_opcode; // @[Mux.scala:30:73] wire [2:0] _nodeOut_a_bits_WIRE_9; // @[Mux.scala:30:73] assign nodeOut_a_bits_param = _nodeOut_a_bits_WIRE_param; // @[Mux.scala:30:73] wire [2:0] _nodeOut_a_bits_WIRE_8; // @[Mux.scala:30:73] assign nodeOut_a_bits_size = _nodeOut_a_bits_WIRE_size; // @[Mux.scala:30:73] wire [5:0] _nodeOut_a_bits_WIRE_7; // @[Mux.scala:30:73] assign nodeOut_a_bits_source = _nodeOut_a_bits_WIRE_source; // @[Mux.scala:30:73] wire [31:0] _nodeOut_a_bits_WIRE_6; // @[Mux.scala:30:73] assign nodeOut_a_bits_address = _nodeOut_a_bits_WIRE_address; // @[Mux.scala:30:73] wire [7:0] _nodeOut_a_bits_WIRE_3; // @[Mux.scala:30:73] assign nodeOut_a_bits_mask = _nodeOut_a_bits_WIRE_mask; // @[Mux.scala:30:73] wire [63:0] _nodeOut_a_bits_WIRE_2; // @[Mux.scala:30:73] assign nodeOut_a_bits_data = _nodeOut_a_bits_WIRE_data; // @[Mux.scala:30:73] wire _nodeOut_a_bits_WIRE_1; // @[Mux.scala:30:73] assign nodeOut_a_bits_corrupt = _nodeOut_a_bits_WIRE_corrupt; // @[Mux.scala:30:73] wire _nodeOut_a_bits_T = muxState_0 & c_a_bits_corrupt; // @[Mux.scala:30:73] wire _nodeOut_a_bits_T_1 = muxState_1 & a_a_bits_corrupt; // @[Mux.scala:30:73] wire _nodeOut_a_bits_T_2 = _nodeOut_a_bits_T \| _nodeOut_a_bits_T_1; // @[Mux.scala:30:73] assign _nodeOut_a_bits_WIRE_1 = _nodeOut_a_bits_T_2; // @[Mux.scala:30:73] assign _nodeOut_a_bits_WIRE_corrupt = _nodeOut_a_bits_WIRE_1; // @[Mux.scala:30:73] wire [63:0] _nodeOut_a_bits_T_3 = muxState_0 ? c_a_bits_data : 64'h0; // @[Mux.scala:30:73] wire [63:0] _nodeOut_a_bits_T_4 = muxState_1 ? a_a_bits_data : 64'h0; // @[Mux.scala:30:73] wire [63:0] _nodeOut_a_bits_T_5 = _nodeOut_a_bits_T_3 \| _nodeOut_a_bits_T_4; // @[Mux.scala:30:73] assign _nodeOut_a_bits_WIRE_2 = _nodeOut_a_bits_T_5; // @[Mux.scala:30:73] assign _nodeOut_a_bits_WIRE_data = _nodeOut_a_bits_WIRE_2; // @[Mux.scala:30:73] wire [7:0] _nodeOut_a_bits_T_6 = muxState_0 ? c_a_bits_mask : 8'h0; // @[Mux.scala:30:73] wire [7:0] _nodeOut_a_bits_T_7 = muxState_1 ? a_a_bits_mask : 8'h0; // @[Mux.scala:30:73] wire [7:0] _nodeOut_a_bits_T_8 = _nodeOut_a_bits_T_6 \| _nodeOut_a_bits_T_7; // @[Mux.scala:30:73] assign _nodeOut_a_bits_WIRE_3 = _nodeOut_a_bits_T_8; // @[Mux.scala:30:73] assign _nodeOut_a_bits_WIRE_mask = _nodeOut_a_bits_WIRE_3; // @[Mux.scala:30:73] wire [31:0] _nodeOut_a_bits_T_9 = muxState_0 ? c_a_bits_address : 32'h0; // @[Mux.scala:30:73] wire [31:0] _nodeOut_a_bits_T_10 = muxState_1 ? a_a_bits_address : 32'h0; // @[Mux.scala:30:73] wire [31:0] _nodeOut_a_bits_T_11 = _nodeOut_a_bits_T_9 \| _nodeOut_a_bits_T_10; // @[Mux.scala:30:73] assign _nodeOut_a_bits_WIRE_6 = _nodeOut_a_bits_T_11; // @[Mux.scala:30:73] assign _nodeOut_a_bits_WIRE_address = _nodeOut_a_bits_WIRE_6; // @[Mux.scala:30:73] wire [5:0] _nodeOut_a_bits_T_12 = muxState_0 ? c_a_bits_source : 6'h0; // @[Mux.scala:30:73] wire [5:0] _nodeOut_a_bits_T_13 = muxState_1 ? a_a_bits_source : 6'h0; // @[Mux.scala:30:73] wire [5:0] _nodeOut_a_bits_T_14 = _nodeOut_a_bits_T_12 \| _nodeOut_a_bits_T_13; // @[Mux.scala:30:73] assign _nodeOut_a_bits_WIRE_7 = _nodeOut_a_bits_T_14; // @[Mux.scala:30:73] assign _nodeOut_a_bits_WIRE_source = _nodeOut_a_bits_WIRE_7; // @[Mux.scala:30:73] wire [2:0] _nodeOut_a_bits_T_15 = muxState_0 ? c_a_bits_size : 3'h0; // @[Mux.scala:30:73] wire [2:0] _nodeOut_a_bits_T_16 = muxState_1 ? a_a_bits_size : 3'h0; // @[Mux.scala:30:73] wire [2:0] _nodeOut_a_bits_T_17 = _nodeOut_a_bits_T_15 \| _nodeOut_a_bits_T_16; // @[Mux.scala:30:73] assign _nodeOut_a_bits_WIRE_8 = _nodeOut_a_bits_T_17; // @[Mux.scala:30:73] assign _nodeOut_a_bits_WIRE_size = _nodeOut_a_bits_WIRE_8; // @[Mux.scala:30:73] wire [2:0] _nodeOut_a_bits_T_19 = muxState_1 ? a_a_bits_param : 3'h0; // @[Mux.scala:30:73] wire [2:0] _nodeOut_a_bits_T_20 = _nodeOut_a_bits_T_19; // @[Mux.scala:30:73] assign _nodeOut_a_bits_WIRE_9 = _nodeOut_a_bits_T_20; // @[Mux.scala:30:73] assign _nodeOut_a_bits_WIRE_param = _nodeOut_a_bits_WIRE_9; // @[Mux.scala:30:73] wire [2:0] _nodeOut_a_bits_T_22 = muxState_1 ? a_a_bits_opcode : 3'h0; // @[Mux.scala:30:73] wire [2:0] _nodeOut_a_bits_T_23 = _nodeOut_a_bits_T_22; // @[Mux.scala:30:73] assign _nodeOut_a_bits_WIRE_10 = _nodeOut_a_bits_T_23; // @[Mux.scala:30:73] assign _nodeOut_a_bits_WIRE_opcode = _nodeOut_a_bits_WIRE_10; // @[Mux.scala:30:73] wire [12:0] _decode_T_6 = 13'h3F << d_d_bits_size; // @[package.scala:243:71] wire [5:0] _decode_T_7 = _decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _decode_T_8 = ~_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] decode_2 = _decode_T_8[5:3]; // @[package.scala:243:46] wire opdata_2 = d_d_bits_opcode[0]; // @[Edges.scala:106:36] reg [2:0] beatsLeft_1; // @[Arbiter.scala:60:30] wire idle_1 = beatsLeft_1 == 3'h0; // @[Arbiter.scala:60:30, :61:28] wire latch_1 = idle_1 & in_d_ready; // @[CacheCork.scala:131:24] wire [1:0] readys_hi = {_q_1_io_deq_valid, _q_io_deq_valid}; // @[Decoupled.scala:362:21] wire [2:0] _readys_T_10 = {readys_hi, d_d_valid}; // @[CacheCork.scala:141:23] wire [3:0] _readys_T_11 = {_readys_T_10, 1'h0}; // @[package.scala:253:48] wire [2:0] _readys_T_12 = _readys_T_11[2:0]; // @[package.scala:253:{48,53}] wire [2:0] _readys_T_13 = _readys_T_10 \| _readys_T_12; // @[package.scala:253:{43,53}] wire [4:0] _readys_T_14 = {_readys_T_13, 2'h0}; // @[package.scala:253:{43,48}] wire [2:0] _readys_T_15 = _readys_T_14[2:0]; // @[package.scala:253:{48,53}] wire [2:0] _readys_T_16 = _readys_T_13 \| _readys_T_15; // @[package.scala:253:{43,53}] wire [2:0] _readys_T_17 = _readys_T_16; // @[package.scala:253:43, :254:17] wire [3:0] _readys_T_18 = {_readys_T_17, 1'h0}; // @[package.scala:254:17] wire [2:0] _readys_T_19 = _readys_T_18[2:0]; // @[Arbiter.scala:16:{78,83}] wire [2:0] _readys_T_20 = ~_readys_T_19; // @[Arbiter.scala:16:{61,83}] wire _readys_T_21 = _readys_T_20[0]; // @[Arbiter.scala:16:61, :68:76] wire readys_1_0 = _readys_T_21; // @[Arbiter.scala:68:{27,76}] wire _readys_T_22 = _readys_T_20[1]; // @[Arbiter.scala:16:61, :68:76] wire readys_1_1 = _readys_T_22; // @[Arbiter.scala:68:{27,76}] wire _readys_T_23 = _readys_T_20[2]; // @[Arbiter.scala:16:61, :68:76] wire readys_1_2 = _readys_T_23; // @[Arbiter.scala:68:{27,76}] wire _winner_T_2 = readys_1_0 & d_d_valid; // @[CacheCork.scala:141:23] wire winner_1_0 = _winner_T_2; // @[Arbiter.scala:71:{27,69}] wire _winner_T_3 = readys_1_1 & _q_io_deq_valid; // @[Decoupled.scala:362:21] wire winner_1_1 = _winner_T_3; // @[Arbiter.scala:71:{27,69}] wire _winner_T_4 = readys_1_2 & _q_1_io_deq_valid; // @[Decoupled.scala:362:21] wire winner_1_2 = _winner_T_4; // @[Arbiter.scala:71:{27,69}] wire prefixOR_1_1 = winner_1_0; // @[Arbiter.scala:71:27, :76:48] wire prefixOR_2 = prefixOR_1_1 \| winner_1_1; // @[Arbiter.scala:71:27, :76:48] wire _prefixOR_T_1 = prefixOR_2 \| winner_1_2; // @[Arbiter.scala:71:27, :76:48] wire _in_d_valid_T = d_d_valid \| _q_io_deq_valid; // @[Decoupled.scala:362:21]
Generate the Verilog code corresponding to the following Chisel files. File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File Nodes.scala: package constellation.channel import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Parameters, Field} import freechips.rocketchip.diplomacy._ case class EmptyParams() case class ChannelEdgeParams(cp: ChannelParams, p: Parameters) object ChannelImp extends SimpleNodeImp[EmptyParams, ChannelParams, ChannelEdgeParams, Channel] { def edge(pd: EmptyParams, pu: ChannelParams, p: Parameters, sourceInfo: SourceInfo) = { ChannelEdgeParams(pu, p) } def bundle(e: ChannelEdgeParams) = new Channel(e.cp)(e.p) def render(e: ChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) { RenderedEdge(colour = "ffffff", label = "X") } else { RenderedEdge(colour = "#0000ff", label = e.cp.payloadBits.toString) } override def monitor(bundle: Channel, edge: ChannelEdgeParams): Unit = { val monitor = Module(new NoCMonitor(edge.cp)(edge.p)) monitor.io.in := bundle } // TODO: Add nodepath stuff? override def mixO, override def mixI } case class ChannelSourceNode(val destId: Int)(implicit valName: ValName) extends SourceNode(ChannelImp)(Seq(EmptyParams())) case class ChannelDestNode(val destParams: ChannelParams)(implicit valName: ValName) extends SinkNode(ChannelImp)(Seq(destParams)) case class ChannelAdapterNode( slaveFn: ChannelParams => ChannelParams = { d => d })( implicit valName: ValName) extends AdapterNode(ChannelImp)((e: EmptyParams) => e, slaveFn) case class ChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(ChannelImp)() case class ChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(ChannelImp)() case class IngressChannelEdgeParams(cp: IngressChannelParams, p: Parameters) case class EgressChannelEdgeParams(cp: EgressChannelParams, p: Parameters) object IngressChannelImp extends SimpleNodeImp[EmptyParams, IngressChannelParams, IngressChannelEdgeParams, IngressChannel] { def edge(pd: EmptyParams, pu: IngressChannelParams, p: Parameters, sourceInfo: SourceInfo) = { IngressChannelEdgeParams(pu, p) } def bundle(e: IngressChannelEdgeParams) = new IngressChannel(e.cp)(e.p) def render(e: IngressChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) { RenderedEdge(colour = "ffffff", label = "X") } else { RenderedEdge(colour = "#00ff00", label = e.cp.payloadBits.toString) } } object EgressChannelImp extends SimpleNodeImp[EmptyParams, EgressChannelParams, EgressChannelEdgeParams, EgressChannel] { def edge(pd: EmptyParams, pu: EgressChannelParams, p: Parameters, sourceInfo: SourceInfo) = { EgressChannelEdgeParams(pu, p) } def bundle(e: EgressChannelEdgeParams) = new EgressChannel(e.cp)(e.p) def render(e: EgressChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) { RenderedEdge(colour = "ffffff", label = "X") } else { RenderedEdge(colour = "#ff0000", label = e.cp.payloadBits.toString) } } case class IngressChannelSourceNode(val destId: Int)(implicit valName: ValName) extends SourceNode(IngressChannelImp)(Seq(EmptyParams())) case class IngressChannelDestNode(val destParams: IngressChannelParams)(implicit valName: ValName) extends SinkNode(IngressChannelImp)(Seq(destParams)) case class EgressChannelSourceNode(val egressId: Int)(implicit valName: ValName) extends SourceNode(EgressChannelImp)(Seq(EmptyParams())) case class EgressChannelDestNode(val destParams: EgressChannelParams)(implicit valName: ValName) extends SinkNode(EgressChannelImp)(Seq(destParams)) case class IngressChannelAdapterNode( slaveFn: IngressChannelParams => IngressChannelParams = { d => d })( implicit valName: ValName) extends AdapterNode(IngressChannelImp)(m => m, slaveFn) case class EgressChannelAdapterNode( slaveFn: EgressChannelParams => EgressChannelParams = { d => d })( implicit valName: ValName) extends AdapterNode(EgressChannelImp)(m => m, slaveFn) case class IngressChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(IngressChannelImp)() case class EgressChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(EgressChannelImp)() case class IngressChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(IngressChannelImp)() case class EgressChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(EgressChannelImp)() File Router.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{RoutingRelation} import constellation.noc.{HasNoCParams} case class UserRouterParams( // Payload width. Must match payload width on all channels attached to this routing node payloadBits: Int = 64, // Combines SA and ST stages (removes pipeline register) combineSAST: Boolean = false, // Combines RC and VA stages (removes pipeline register) combineRCVA: Boolean = false, // Adds combinational path from SA to VA coupleSAVA: Boolean = false, vcAllocator: VCAllocatorParams => Parameters => VCAllocator = (vP) => (p) => new RotatingSingleVCAllocator(vP)(p) ) case class RouterParams( nodeId: Int, nIngress: Int, nEgress: Int, user: UserRouterParams ) trait HasRouterOutputParams { def outParams: Seq[ChannelParams] def egressParams: Seq[EgressChannelParams] def allOutParams = outParams ++ egressParams def nOutputs = outParams.size def nEgress = egressParams.size def nAllOutputs = allOutParams.size } trait HasRouterInputParams { def inParams: Seq[ChannelParams] def ingressParams: Seq[IngressChannelParams] def allInParams = inParams ++ ingressParams def nInputs = inParams.size def nIngress = ingressParams.size def nAllInputs = allInParams.size } trait HasRouterParams { def routerParams: RouterParams def nodeId = routerParams.nodeId def payloadBits = routerParams.user.payloadBits } class DebugBundle(val nIn: Int) extends Bundle { val va_stall = Vec(nIn, UInt()) val sa_stall = Vec(nIn, UInt()) } class Router( val routerParams: RouterParams, preDiplomaticInParams: Seq[ChannelParams], preDiplomaticIngressParams: Seq[IngressChannelParams], outDests: Seq[Int], egressIds: Seq[Int] )(implicit p: Parameters) extends LazyModule with HasNoCParams with HasRouterParams { val allPreDiplomaticInParams = preDiplomaticInParams ++ preDiplomaticIngressParams val destNodes = preDiplomaticInParams.map(u => ChannelDestNode(u)) val sourceNodes = outDests.map(u => ChannelSourceNode(u)) val ingressNodes = preDiplomaticIngressParams.map(u => IngressChannelDestNode(u)) val egressNodes = egressIds.map(u => EgressChannelSourceNode(u)) val debugNode = BundleBridgeSource(() => new DebugBundle(allPreDiplomaticInParams.size)) val ctrlNode = if (hasCtrl) Some(BundleBridgeSource(() => new RouterCtrlBundle)) else None def inParams = module.inParams def outParams = module.outParams def ingressParams = module.ingressParams def egressParams = module.egressParams lazy val module = new LazyModuleImp(this) with HasRouterInputParams with HasRouterOutputParams { val (io_in, edgesIn) = destNodes.map(_.in(0)).unzip val (io_out, edgesOut) = sourceNodes.map(_.out(0)).unzip val (io_ingress, edgesIngress) = ingressNodes.map(_.in(0)).unzip val (io_egress, edgesEgress) = egressNodes.map(_.out(0)).unzip val io_debug = debugNode.out(0)._1 val inParams = edgesIn.map(_.cp) val outParams = edgesOut.map(_.cp) val ingressParams = edgesIngress.map(_.cp) val egressParams = edgesEgress.map(_.cp) allOutParams.foreach(u => require(u.srcId == nodeId && u.payloadBits == routerParams.user.payloadBits)) allInParams.foreach(u => require(u.destId == nodeId && u.payloadBits == routerParams.user.payloadBits)) require(nIngress == routerParams.nIngress) require(nEgress == routerParams.nEgress) require(nAllInputs >= 1) require(nAllOutputs >= 1) require(nodeId < (1 << nodeIdBits)) val input_units = inParams.zipWithIndex.map { case (u,i) => Module(new InputUnit(u, outParams, egressParams, routerParams.user.combineRCVA, routerParams.user.combineSAST)) .suggestName(s"input_unit_${i}_from_${u.srcId}") } val ingress_units = ingressParams.zipWithIndex.map { case (u,i) => Module(new IngressUnit(i, u, outParams, egressParams, routerParams.user.combineRCVA, routerParams.user.combineSAST)) .suggestName(s"ingress_unit_${i+nInputs}_from_${u.ingressId}") } val all_input_units = input_units ++ ingress_units val output_units = outParams.zipWithIndex.map { case (u,i) => Module(new OutputUnit(inParams, ingressParams, u)) .suggestName(s"output_unit_${i}_to_${u.destId}")} val egress_units = egressParams.zipWithIndex.map { case (u,i) => Module(new EgressUnit(routerParams.user.coupleSAVA && all_input_units.size == 1, routerParams.user.combineSAST, inParams, ingressParams, u)) .suggestName(s"egress_unit_${i+nOutputs}_to_${u.egressId}")} val all_output_units = output_units ++ egress_units val switch = Module(new Switch(routerParams, inParams, outParams, ingressParams, egressParams)) val switch_allocator = Module(new SwitchAllocator(routerParams, inParams, outParams, ingressParams, egressParams)) val vc_allocator = Module(routerParams.user.vcAllocator( VCAllocatorParams(routerParams, inParams, outParams, ingressParams, egressParams) )(p)) val route_computer = Module(new RouteComputer(routerParams, inParams, outParams, ingressParams, egressParams)) val fires_count = WireInit(PopCount(vc_allocator.io.req.map(_.fire))) dontTouch(fires_count) (io_in zip input_units ).foreach { case (i,u) => u.io.in <> i } (io_ingress zip ingress_units).foreach { case (i,u) => u.io.in <> i.flit } (output_units zip io_out ).foreach { case (u,o) => o <> u.io.out } (egress_units zip io_egress).foreach { case (u,o) => o.flit <> u.io.out } (route_computer.io.req zip all_input_units).foreach { case (i,u) => i <> u.io.router_req } (all_input_units zip route_computer.io.resp).foreach { case (u,o) => u.io.router_resp <> o } (vc_allocator.io.req zip all_input_units).foreach { case (i,u) => i <> u.io.vcalloc_req } (all_input_units zip vc_allocator.io.resp).foreach { case (u,o) => u.io.vcalloc_resp <> o } (all_output_units zip vc_allocator.io.out_allocs).foreach { case (u,a) => u.io.allocs <> a } (vc_allocator.io.channel_status zip all_output_units).foreach { case (a,u) => a := u.io.channel_status } all_input_units.foreach(in => all_output_units.zipWithIndex.foreach { case (out,outIdx) => in.io.out_credit_available(outIdx) := out.io.credit_available }) (all_input_units zip switch_allocator.io.req).foreach { case (u,r) => r <> u.io.salloc_req } (all_output_units zip switch_allocator.io.credit_alloc).foreach { case (u,a) => u.io.credit_alloc := a } (switch.io.in zip all_input_units).foreach { case (i,u) => i <> u.io.out } (all_output_units zip switch.io.out).foreach { case (u,o) => u.io.in <> o } switch.io.sel := (if (routerParams.user.combineSAST) { switch_allocator.io.switch_sel } else { RegNext(switch_allocator.io.switch_sel) }) if (hasCtrl) { val io_ctrl = ctrlNode.get.out(0)._1 val ctrl = Module(new RouterControlUnit(routerParams, inParams, outParams, ingressParams, egressParams)) io_ctrl <> ctrl.io.ctrl (all_input_units zip ctrl.io.in_block ).foreach { case (l,r) => l.io.block := r } (all_input_units zip ctrl.io.in_fire ).foreach { case (l,r) => r := l.io.out.map(_.valid) } } else { input_units.foreach(_.io.block := false.B) ingress_units.foreach(_.io.block := false.B) } (io_debug.va_stall zip all_input_units.map(_.io.debug.va_stall)).map { case (l,r) => l := r } (io_debug.sa_stall zip all_input_units.map(_.io.debug.sa_stall)).map { case (l,r) => l := r } val debug_tsc = RegInit(0.U(64.W)) debug_tsc := debug_tsc + 1.U val debug_sample = RegInit(0.U(64.W)) debug_sample := debug_sample + 1.U val sample_rate = PlusArg("noc_util_sample_rate", width=20) when (debug_sample === sample_rate - 1.U) { debug_sample := 0.U } def sample(fire: Bool, s: String) = { val util_ctr = RegInit(0.U(64.W)) val fired = RegInit(false.B) util_ctr := util_ctr + fire fired := fired \|\| fire when (sample_rate =/= 0.U && debug_sample === sample_rate - 1.U && fired) { val fmtStr = s"nocsample %d $s %d\n" printf(fmtStr, debug_tsc, util_ctr); fired := fire } } destNodes.map(_.in(0)).foreach { case (in, edge) => in.flit.map { f => sample(f.fire, s"${edge.cp.srcId} $nodeId") } } ingressNodes.map(_.in(0)).foreach { case (in, edge) => sample(in.flit.fire, s"i${edge.cp.asInstanceOf[IngressChannelParams].ingressId} $nodeId") } egressNodes.map(_.out(0)).foreach { case (out, edge) => sample(out.flit.fire, s"$nodeId e${edge.cp.asInstanceOf[EgressChannelParams].egressId}") } } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } }	module Router_15( // @[Router.scala:89:25] input clock, // @[Router.scala:89:25] input reset, // @[Router.scala:89:25] output [2:0] auto_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_va_stall_3, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_sa_stall_3, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_3_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_3_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_3_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_source_nodes_out_3_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_3_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_3_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_3_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_3_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_3_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_3_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [7:0] auto_source_nodes_out_3_credit_return, // @[LazyModuleImp.scala:107:25] input [7:0] auto_source_nodes_out_3_vc_free, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_2_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_source_nodes_out_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [7:0] auto_source_nodes_out_2_credit_return, // @[LazyModuleImp.scala:107:25] input [7:0] auto_source_nodes_out_2_vc_free, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_source_nodes_out_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [7:0] auto_source_nodes_out_1_credit_return, // @[LazyModuleImp.scala:107:25] input [7:0] auto_source_nodes_out_1_vc_free, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_source_nodes_out_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [7:0] auto_source_nodes_out_0_credit_return, // @[LazyModuleImp.scala:107:25] input [7:0] auto_source_nodes_out_0_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_3_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_3_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_3_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_dest_nodes_in_3_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_3_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_3_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_3_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_3_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_3_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_3_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [7:0] auto_dest_nodes_in_3_credit_return, // @[LazyModuleImp.scala:107:25] output [7:0] auto_dest_nodes_in_3_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_2_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_dest_nodes_in_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [7:0] auto_dest_nodes_in_2_credit_return, // @[LazyModuleImp.scala:107:25] output [7:0] auto_dest_nodes_in_2_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_dest_nodes_in_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [7:0] auto_dest_nodes_in_1_credit_return, // @[LazyModuleImp.scala:107:25] output [7:0] auto_dest_nodes_in_1_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_dest_nodes_in_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [7:0] auto_dest_nodes_in_0_credit_return, // @[LazyModuleImp.scala:107:25] output [7:0] auto_dest_nodes_in_0_vc_free // @[LazyModuleImp.scala:107:25] ); wire [19:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire _route_computer_io_resp_3_vc_sel_2_1; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_2_2; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_2_3; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_2_4; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_2_5; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_2_6; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_2_7; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_1_1; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_1_2; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_1_3; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_1_4; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_1_5; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_1_6; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_1_7; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_0_1; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_0_2; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_0_3; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_0_4; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_0_5; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_0_6; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_0_7; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_3_0; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_3_1; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_3_2; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_3_3; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_3_4; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_3_5; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_3_6; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_3_7; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_1_1; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_1_2; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_1_3; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_1_4; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_1_5; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_1_6; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_1_7; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_1; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_2; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_3; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_4; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_5; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_6; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_7; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_3_4; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_3_5; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_3_6; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_3_7; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_2_4; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_2_5; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_2_6; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_2_7; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_3_0; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_3_1; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_3_2; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_3_3; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_3_4; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_3_5; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_3_6; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_3_7; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_2_0; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_2_1; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_2_2; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_2_3; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_2_4; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_2_5; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_2_6; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_2_7; // @[Router.scala:136:32] wire _vc_allocator_io_req_3_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_2_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_1_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_0_ready; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_2_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_2_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_2_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_2_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_2_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_2_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_2_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_1_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_1_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_1_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_1_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_1_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_1_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_1_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_3_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_3_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_3_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_3_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_3_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_3_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_3_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_3_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_1_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_1_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_1_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_1_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_1_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_1_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_1_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_3_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_3_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_3_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_3_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_2_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_2_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_2_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_2_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_3_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_3_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_3_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_3_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_3_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_3_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_3_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_3_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_2_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_2_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_2_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_2_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_2_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_2_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_2_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_2_7; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_3_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_3_1_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_3_2_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_3_3_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_3_4_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_3_5_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_3_6_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_3_7_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_1_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_2_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_3_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_4_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_5_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_6_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_7_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_1_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_2_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_3_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_4_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_5_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_6_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_7_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_1_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_2_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_3_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_4_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_5_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_6_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_7_alloc; // @[Router.scala:133:30] wire _switch_allocator_io_req_3_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_2_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_1_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_0_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_3_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_3_1_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_3_2_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_3_3_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_3_4_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_3_5_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_3_6_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_3_7_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_1_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_2_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_3_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_4_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_5_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_6_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_7_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_1_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_2_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_3_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_4_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_5_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_6_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_7_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_1_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_2_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_3_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_4_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_5_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_6_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_7_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_3_0_3_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_3_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_3_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_3_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_3_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_3_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_3_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_0_0; // @[Router.scala:132:34] wire _switch_io_out_3_0_valid; // @[Router.scala:131:24] wire _switch_io_out_3_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_3_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_3_0_bits_payload; // @[Router.scala:131:24] wire [2:0] _switch_io_out_3_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_3_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_3_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_3_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_3_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [2:0] _switch_io_out_3_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _switch_io_out_2_0_valid; // @[Router.scala:131:24] wire _switch_io_out_2_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_2_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_2_0_bits_payload; // @[Router.scala:131:24] wire [2:0] _switch_io_out_2_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_2_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_2_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_2_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_2_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [2:0] _switch_io_out_2_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _switch_io_out_1_0_valid; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_1_0_bits_payload; // @[Router.scala:131:24] wire [2:0] _switch_io_out_1_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_1_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_1_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_1_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_1_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [2:0] _switch_io_out_1_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _switch_io_out_0_0_valid; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_0_0_bits_payload; // @[Router.scala:131:24] wire [2:0] _switch_io_out_0_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_0_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_0_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_0_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_0_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [2:0] _switch_io_out_0_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _output_unit_3_to_21_io_credit_available_0; // @[Router.scala:122:13] wire _output_unit_3_to_21_io_credit_available_1; // @[Router.scala:122:13] wire _output_unit_3_to_21_io_credit_available_2; // @[Router.scala:122:13] wire _output_unit_3_to_21_io_credit_available_3; // @[Router.scala:122:13] wire _output_unit_3_to_21_io_credit_available_4; // @[Router.scala:122:13] wire _output_unit_3_to_21_io_credit_available_5; // @[Router.scala:122:13] wire _output_unit_3_to_21_io_credit_available_6; // @[Router.scala:122:13] wire _output_unit_3_to_21_io_credit_available_7; // @[Router.scala:122:13] wire _output_unit_3_to_21_io_channel_status_0_occupied; // @[Router.scala:122:13] wire _output_unit_3_to_21_io_channel_status_1_occupied; // @[Router.scala:122:13] wire _output_unit_3_to_21_io_channel_status_2_occupied; // @[Router.scala:122:13] wire _output_unit_3_to_21_io_channel_status_3_occupied; // @[Router.scala:122:13] wire _output_unit_3_to_21_io_channel_status_4_occupied; // @[Router.scala:122:13] wire _output_unit_3_to_21_io_channel_status_5_occupied; // @[Router.scala:122:13] wire _output_unit_3_to_21_io_channel_status_6_occupied; // @[Router.scala:122:13] wire _output_unit_3_to_21_io_channel_status_7_occupied; // @[Router.scala:122:13] wire _output_unit_2_to_18_io_credit_available_0; // @[Router.scala:122:13] wire _output_unit_2_to_18_io_credit_available_1; // @[Router.scala:122:13] wire _output_unit_2_to_18_io_credit_available_2; // @[Router.scala:122:13] wire _output_unit_2_to_18_io_credit_available_3; // @[Router.scala:122:13] wire _output_unit_2_to_18_io_credit_available_4; // @[Router.scala:122:13] wire _output_unit_2_to_18_io_credit_available_5; // @[Router.scala:122:13] wire _output_unit_2_to_18_io_credit_available_6; // @[Router.scala:122:13] wire _output_unit_2_to_18_io_credit_available_7; // @[Router.scala:122:13] wire _output_unit_2_to_18_io_channel_status_0_occupied; // @[Router.scala:122:13] wire _output_unit_2_to_18_io_channel_status_1_occupied; // @[Router.scala:122:13] wire _output_unit_2_to_18_io_channel_status_2_occupied; // @[Router.scala:122:13] wire _output_unit_2_to_18_io_channel_status_3_occupied; // @[Router.scala:122:13] wire _output_unit_2_to_18_io_channel_status_4_occupied; // @[Router.scala:122:13] wire _output_unit_2_to_18_io_channel_status_5_occupied; // @[Router.scala:122:13] wire _output_unit_2_to_18_io_channel_status_6_occupied; // @[Router.scala:122:13] wire _output_unit_2_to_18_io_channel_status_7_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_16_io_credit_available_1; // @[Router.scala:122:13] wire _output_unit_1_to_16_io_credit_available_2; // @[Router.scala:122:13] wire _output_unit_1_to_16_io_credit_available_3; // @[Router.scala:122:13] wire _output_unit_1_to_16_io_credit_available_4; // @[Router.scala:122:13] wire _output_unit_1_to_16_io_credit_available_5; // @[Router.scala:122:13] wire _output_unit_1_to_16_io_credit_available_6; // @[Router.scala:122:13] wire _output_unit_1_to_16_io_credit_available_7; // @[Router.scala:122:13] wire _output_unit_1_to_16_io_channel_status_1_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_16_io_channel_status_2_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_16_io_channel_status_3_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_16_io_channel_status_4_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_16_io_channel_status_5_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_16_io_channel_status_6_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_16_io_channel_status_7_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_1_io_credit_available_1; // @[Router.scala:122:13] wire _output_unit_0_to_1_io_credit_available_2; // @[Router.scala:122:13] wire _output_unit_0_to_1_io_credit_available_3; // @[Router.scala:122:13] wire _output_unit_0_to_1_io_credit_available_4; // @[Router.scala:122:13] wire _output_unit_0_to_1_io_credit_available_5; // @[Router.scala:122:13] wire _output_unit_0_to_1_io_credit_available_6; // @[Router.scala:122:13] wire _output_unit_0_to_1_io_credit_available_7; // @[Router.scala:122:13] wire _output_unit_0_to_1_io_channel_status_1_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_1_io_channel_status_2_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_1_io_channel_status_3_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_1_io_channel_status_4_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_1_io_channel_status_5_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_1_io_channel_status_6_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_1_io_channel_status_7_occupied; // @[Router.scala:122:13] wire [2:0] _input_unit_3_from_21_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire [2:0] _input_unit_3_from_21_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [4:0] _input_unit_3_from_21_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_3_from_21_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_3_from_21_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_3_from_21_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_vcalloc_req_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_vcalloc_req_bits_vc_sel_2_2; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_vcalloc_req_bits_vc_sel_2_3; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_vcalloc_req_bits_vc_sel_2_4; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_vcalloc_req_bits_vc_sel_2_5; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_vcalloc_req_bits_vc_sel_2_6; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_vcalloc_req_bits_vc_sel_2_7; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_vcalloc_req_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_vcalloc_req_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_vcalloc_req_bits_vc_sel_1_3; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_vcalloc_req_bits_vc_sel_1_4; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_vcalloc_req_bits_vc_sel_1_5; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_vcalloc_req_bits_vc_sel_1_6; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_vcalloc_req_bits_vc_sel_1_7; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_vcalloc_req_bits_vc_sel_0_4; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_vcalloc_req_bits_vc_sel_0_5; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_vcalloc_req_bits_vc_sel_0_6; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_vcalloc_req_bits_vc_sel_0_7; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_salloc_req_0_bits_vc_sel_3_1; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_salloc_req_0_bits_vc_sel_3_2; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_salloc_req_0_bits_vc_sel_3_3; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_salloc_req_0_bits_vc_sel_3_4; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_salloc_req_0_bits_vc_sel_3_5; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_salloc_req_0_bits_vc_sel_3_6; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_salloc_req_0_bits_vc_sel_3_7; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_salloc_req_0_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_salloc_req_0_bits_vc_sel_2_2; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_salloc_req_0_bits_vc_sel_2_3; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_salloc_req_0_bits_vc_sel_2_4; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_salloc_req_0_bits_vc_sel_2_5; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_salloc_req_0_bits_vc_sel_2_6; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_salloc_req_0_bits_vc_sel_2_7; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_salloc_req_0_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_salloc_req_0_bits_vc_sel_1_3; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_salloc_req_0_bits_vc_sel_1_4; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_salloc_req_0_bits_vc_sel_1_5; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_salloc_req_0_bits_vc_sel_1_6; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_salloc_req_0_bits_vc_sel_1_7; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_salloc_req_0_bits_vc_sel_0_6; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_salloc_req_0_bits_vc_sel_0_7; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [72:0] _input_unit_3_from_21_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [2:0] _input_unit_3_from_21_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [4:0] _input_unit_3_from_21_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_3_from_21_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_3_from_21_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_3_from_21_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [2:0] _input_unit_3_from_21_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [2:0] _input_unit_2_from_18_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire [2:0] _input_unit_2_from_18_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [4:0] _input_unit_2_from_18_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_2_from_18_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_2_from_18_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_2_from_18_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_vcalloc_req_bits_vc_sel_3_1; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_vcalloc_req_bits_vc_sel_3_2; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_vcalloc_req_bits_vc_sel_3_3; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_vcalloc_req_bits_vc_sel_3_4; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_vcalloc_req_bits_vc_sel_3_5; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_vcalloc_req_bits_vc_sel_3_6; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_vcalloc_req_bits_vc_sel_3_7; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_vcalloc_req_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_vcalloc_req_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_vcalloc_req_bits_vc_sel_1_3; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_vcalloc_req_bits_vc_sel_1_4; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_vcalloc_req_bits_vc_sel_1_5; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_vcalloc_req_bits_vc_sel_1_6; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_vcalloc_req_bits_vc_sel_1_7; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_vcalloc_req_bits_vc_sel_0_4; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_vcalloc_req_bits_vc_sel_0_5; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_vcalloc_req_bits_vc_sel_0_6; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_vcalloc_req_bits_vc_sel_0_7; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_salloc_req_0_bits_vc_sel_3_1; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_salloc_req_0_bits_vc_sel_3_2; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_salloc_req_0_bits_vc_sel_3_3; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_salloc_req_0_bits_vc_sel_3_4; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_salloc_req_0_bits_vc_sel_3_5; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_salloc_req_0_bits_vc_sel_3_6; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_salloc_req_0_bits_vc_sel_3_7; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_salloc_req_0_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_salloc_req_0_bits_vc_sel_2_2; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_salloc_req_0_bits_vc_sel_2_3; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_salloc_req_0_bits_vc_sel_2_4; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_salloc_req_0_bits_vc_sel_2_5; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_salloc_req_0_bits_vc_sel_2_6; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_salloc_req_0_bits_vc_sel_2_7; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_salloc_req_0_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_salloc_req_0_bits_vc_sel_1_3; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_salloc_req_0_bits_vc_sel_1_4; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_salloc_req_0_bits_vc_sel_1_5; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_salloc_req_0_bits_vc_sel_1_6; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_salloc_req_0_bits_vc_sel_1_7; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_salloc_req_0_bits_vc_sel_0_6; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_salloc_req_0_bits_vc_sel_0_7; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [72:0] _input_unit_2_from_18_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [2:0] _input_unit_2_from_18_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [4:0] _input_unit_2_from_18_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_2_from_18_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_2_from_18_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_2_from_18_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [2:0] _input_unit_2_from_18_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_16_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_16_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [4:0] _input_unit_1_from_16_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_16_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_1_from_16_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_16_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_vcalloc_req_bits_vc_sel_3_4; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_vcalloc_req_bits_vc_sel_3_5; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_vcalloc_req_bits_vc_sel_3_6; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_vcalloc_req_bits_vc_sel_3_7; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_vcalloc_req_bits_vc_sel_2_4; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_vcalloc_req_bits_vc_sel_2_5; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_vcalloc_req_bits_vc_sel_2_6; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_vcalloc_req_bits_vc_sel_2_7; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_salloc_req_0_bits_vc_sel_3_1; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_salloc_req_0_bits_vc_sel_3_2; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_salloc_req_0_bits_vc_sel_3_3; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_salloc_req_0_bits_vc_sel_3_4; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_salloc_req_0_bits_vc_sel_3_5; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_salloc_req_0_bits_vc_sel_3_6; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_salloc_req_0_bits_vc_sel_3_7; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_salloc_req_0_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_salloc_req_0_bits_vc_sel_2_2; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_salloc_req_0_bits_vc_sel_2_3; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_salloc_req_0_bits_vc_sel_2_4; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_salloc_req_0_bits_vc_sel_2_5; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_salloc_req_0_bits_vc_sel_2_6; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_salloc_req_0_bits_vc_sel_2_7; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_salloc_req_0_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_salloc_req_0_bits_vc_sel_1_3; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_salloc_req_0_bits_vc_sel_1_4; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_salloc_req_0_bits_vc_sel_1_5; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_salloc_req_0_bits_vc_sel_1_6; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_salloc_req_0_bits_vc_sel_1_7; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_salloc_req_0_bits_vc_sel_0_6; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_salloc_req_0_bits_vc_sel_0_7; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [72:0] _input_unit_1_from_16_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_16_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [4:0] _input_unit_1_from_16_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_16_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_1_from_16_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_16_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_16_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_1_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_1_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [4:0] _input_unit_0_from_1_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_1_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_0_from_1_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_1_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_vcalloc_req_bits_vc_sel_3_1; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_vcalloc_req_bits_vc_sel_3_2; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_vcalloc_req_bits_vc_sel_3_3; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_vcalloc_req_bits_vc_sel_3_4; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_vcalloc_req_bits_vc_sel_3_5; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_vcalloc_req_bits_vc_sel_3_6; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_vcalloc_req_bits_vc_sel_3_7; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_vcalloc_req_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_vcalloc_req_bits_vc_sel_2_2; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_vcalloc_req_bits_vc_sel_2_3; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_vcalloc_req_bits_vc_sel_2_4; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_vcalloc_req_bits_vc_sel_2_5; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_vcalloc_req_bits_vc_sel_2_6; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_vcalloc_req_bits_vc_sel_2_7; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_salloc_req_0_bits_vc_sel_3_1; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_salloc_req_0_bits_vc_sel_3_2; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_salloc_req_0_bits_vc_sel_3_3; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_salloc_req_0_bits_vc_sel_3_4; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_salloc_req_0_bits_vc_sel_3_5; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_salloc_req_0_bits_vc_sel_3_6; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_salloc_req_0_bits_vc_sel_3_7; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_salloc_req_0_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_salloc_req_0_bits_vc_sel_2_2; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_salloc_req_0_bits_vc_sel_2_3; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_salloc_req_0_bits_vc_sel_2_4; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_salloc_req_0_bits_vc_sel_2_5; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_salloc_req_0_bits_vc_sel_2_6; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_salloc_req_0_bits_vc_sel_2_7; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_salloc_req_0_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_salloc_req_0_bits_vc_sel_1_3; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_salloc_req_0_bits_vc_sel_1_4; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_salloc_req_0_bits_vc_sel_1_5; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_salloc_req_0_bits_vc_sel_1_6; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_salloc_req_0_bits_vc_sel_1_7; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_salloc_req_0_bits_vc_sel_0_6; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_salloc_req_0_bits_vc_sel_0_7; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [72:0] _input_unit_0_from_1_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_1_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [4:0] _input_unit_0_from_1_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_1_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_0_from_1_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_1_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_1_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [2:0] fires_count = {1'h0, {1'h0, _vc_allocator_io_req_0_ready & _input_unit_0_from_1_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_1_ready & _input_unit_1_from_16_io_vcalloc_req_valid}} + {1'h0, {1'h0, _vc_allocator_io_req_2_ready & _input_unit_2_from_18_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_3_ready & _input_unit_3_from_21_io_vcalloc_req_valid}}; // @[Decoupled.scala:51:35] reg REG_3_0_3_0; // @[Router.scala:178:14] reg REG_3_0_2_0; // @[Router.scala:178:14] reg REG_3_0_1_0; // @[Router.scala:178:14] reg REG_3_0_0_0; // @[Router.scala:178:14] reg REG_2_0_3_0; // @[Router.scala:178:14] reg REG_2_0_2_0; // @[Router.scala:178:14] reg REG_2_0_1_0; // @[Router.scala:178:14] reg REG_2_0_0_0; // @[Router.scala:178:14] reg REG_1_0_3_0; // @[Router.scala:178:14] reg REG_1_0_2_0; // @[Router.scala:178:14] reg REG_1_0_1_0; // @[Router.scala:178:14] reg REG_1_0_0_0; // @[Router.scala:178:14] reg REG_0_0_3_0; // @[Router.scala:178:14] reg REG_0_0_2_0; // @[Router.scala:178:14] reg REG_0_0_1_0; // @[Router.scala:178:14] reg REG_0_0_0_0; // @[Router.scala:178:14] reg [63:0] debug_tsc; // @[Router.scala:195:28] reg [63:0] debug_sample; // @[Router.scala:197:31] wire _GEN = debug_sample == {44'h0, _plusarg_reader_out - 20'h1}; // @[PlusArg.scala:80:11] reg [63:0] util_ctr; // @[Router.scala:203:29] reg fired; // @[Router.scala:204:26] wire _GEN_0 = (\|_plusarg_reader_out) & _GEN; // @[PlusArg.scala:80:11] wire _GEN_1 = _GEN_0 & fired; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_1; // @[Router.scala:203:29] reg fired_1; // @[Router.scala:204:26] wire _GEN_2 = _GEN_0 & fired_1; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_2; // @[Router.scala:203:29] reg fired_2; // @[Router.scala:204:26] wire _GEN_3 = _GEN_0 & fired_2; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_3; // @[Router.scala:203:29] reg fired_3; // @[Router.scala:204:26] wire _GEN_4 = _GEN_0 & fired_3; // @[Router.scala:204:26, :207:{33,71}]
Generate the Verilog code corresponding to the following Chisel files. File RoundAnyRawFNToRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util.Fill import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundAnyRawFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int, options: Int ) extends RawModule { override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(inExpWidth, inSigWidth)) // (allowed exponent range has limits) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0) val effectiveInSigWidth = if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1 val neverUnderflows = ((options & (flRoundOpt_neverUnderflows \| flRoundOpt_subnormsAlwaysExact) ) != 0) \|\| (inExpWidth < outExpWidth) val neverOverflows = ((options & flRoundOpt_neverOverflows) != 0) \|\| (inExpWidth < outExpWidth) val outNaNExp = BigInt(7)<<(outExpWidth - 2) val outInfExp = BigInt(6)<<(outExpWidth - 2) val outMaxFiniteExp = outInfExp - 1 val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2 val outMinNonzeroExp = outMinNormExp - outSigWidth + 1 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_near_even = (io.roundingMode === round_near_even) val roundingMode_minMag = (io.roundingMode === round_minMag) val roundingMode_min = (io.roundingMode === round_min) val roundingMode_max = (io.roundingMode === round_max) val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag) val roundingMode_odd = (io.roundingMode === round_odd) val roundMagUp = (roundingMode_min && io.in.sign) \|\| (roundingMode_max && ! io.in.sign) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sAdjustedExp = if (inExpWidth < outExpWidth) (io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S )(outExpWidth, 0).zext else if (inExpWidth == outExpWidth) io.in.sExp else io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S val adjustedSig = if (inSigWidth <= outSigWidth + 2) io.in.sig<<(outSigWidth - inSigWidth + 2) else (io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ## io.in.sig(inSigWidth - outSigWidth - 2, 0).orR ) val doShiftSigDown1 = if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2) val common_expOut = Wire(UInt((outExpWidth + 1).W)) val common_fractOut = Wire(UInt((outSigWidth - 1).W)) val common_overflow = Wire(Bool()) val common_totalUnderflow = Wire(Bool()) val common_underflow = Wire(Bool()) val common_inexact = Wire(Bool()) if ( neverOverflows && neverUnderflows && (effectiveInSigWidth <= outSigWidth) ) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1 common_fractOut := Mux(doShiftSigDown1, adjustedSig(outSigWidth + 1, 3), adjustedSig(outSigWidth, 2) ) common_overflow := false.B common_totalUnderflow := false.B common_underflow := false.B common_inexact := false.B } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundMask = if (neverUnderflows) 0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W) else (lowMask( sAdjustedExp(outExpWidth, 0), outMinNormExp - outSigWidth - 1, outMinNormExp ) \| doShiftSigDown1) ## 3.U(2.W) val shiftedRoundMask = 0.U(1.W) ## roundMask>>1 val roundPosMask = ~shiftedRoundMask & roundMask val roundPosBit = (adjustedSig & roundPosMask).orR val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR val anyRound = roundPosBit \|\| anyRoundExtra val roundIncr = ((roundingMode_near_even \|\| roundingMode_near_maxMag) && roundPosBit) \|\| (roundMagUp && anyRound) val roundedSig: Bits = Mux(roundIncr, (((adjustedSig \| roundMask)>>2) +& 1.U) & ~Mux(roundingMode_near_even && roundPosBit && ! anyRoundExtra, roundMask>>1, 0.U((outSigWidth + 2).W) ), (adjustedSig & ~roundMask)>>2 \| Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U) ) //* IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //* M.S. BIT OF SUBNORMAL SIG? val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext common_expOut := sRoundedExp(outExpWidth, 0) common_fractOut := Mux(doShiftSigDown1, roundedSig(outSigWidth - 1, 1), roundedSig(outSigWidth - 2, 0) ) common_overflow := (if (neverOverflows) false.B else //* REWRITE BASED ON BEFORE-ROUNDING EXPONENT?: (sRoundedExp>>(outExpWidth - 1) >= 3.S)) common_totalUnderflow := (if (neverUnderflows) false.B else //* WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?: (sRoundedExp < outMinNonzeroExp.S)) val unboundedRange_roundPosBit = Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1)) val unboundedRange_anyRound = (doShiftSigDown1 && adjustedSig(2)) \|\| adjustedSig(1, 0).orR val unboundedRange_roundIncr = ((roundingMode_near_even \|\| roundingMode_near_maxMag) && unboundedRange_roundPosBit) \|\| (roundMagUp && unboundedRange_anyRound) val roundCarry = Mux(doShiftSigDown1, roundedSig(outSigWidth + 1), roundedSig(outSigWidth) ) common_underflow := (if (neverUnderflows) false.B else common_totalUnderflow \|\| //* IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //* M.S. BIT OF SUBNORMAL SIG? (anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) && Mux(doShiftSigDown1, roundMask(3), roundMask(2)) && ! ((io.detectTininess === tininess_afterRounding) && ! Mux(doShiftSigDown1, roundMask(4), roundMask(3) ) && roundCarry && roundPosBit && unboundedRange_roundIncr))) common_inexact := common_totalUnderflow \|\| anyRound } //------------------------------------------------------------------------ //------------------------------------------------------------------------ val isNaNOut = io.invalidExc \|\| io.in.isNaN val notNaN_isSpecialInfOut = io.infiniteExc \|\| io.in.isInf val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero val overflow = commonCase && common_overflow val underflow = commonCase && common_underflow val inexact = overflow \|\| (commonCase && common_inexact) val overflow_roundMagUp = roundingMode_near_even \|\| roundingMode_near_maxMag \|\| roundMagUp val pegMinNonzeroMagOut = commonCase && common_totalUnderflow && (roundMagUp \|\| roundingMode_odd) val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp val notNaN_isInfOut = notNaN_isSpecialInfOut \|\| (overflow && overflow_roundMagUp) val signOut = Mux(isNaNOut, false.B, io.in.sign) val expOut = (common_expOut & ~Mux(io.in.isZero \|\| common_totalUnderflow, (BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMinNonzeroMagOut, ~outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMaxFiniteMagOut, (BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W), 0.U ) & ~Mux(notNaN_isInfOut, (BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U )) \| Mux(pegMinNonzeroMagOut, outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) \| Mux(pegMaxFiniteMagOut, outMaxFiniteExp.U((outExpWidth + 1).W), 0.U ) \| Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) \| Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U) val fractOut = Mux(isNaNOut \|\| io.in.isZero \|\| common_totalUnderflow, Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U), common_fractOut ) \| Fill(outSigWidth - 1, pegMaxFiniteMagOut) io.out := signOut ## expOut ## fractOut io.exceptionFlags := io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int) extends RawModule { override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(expWidth, sigWidth + 2)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( expWidth, sigWidth + 2, expWidth, sigWidth, options)) roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc roundAnyRawFNToRecFN.io.in := io.in roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags }	module RoundRawFNToRecFN_e8_s24_62( // @[RoundAnyRawFNToRecFN.scala:295:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_62 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15] .io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[RoundAnyRawFNToRecFN.scala:310:15] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{ AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry, IdRange, RegionType, TransferSizes } import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions} import freechips.rocketchip.util.{ AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase, CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct } import scala.math.max //These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel case class TLMasterToSlaveTransferSizes( // Supports both Acquire+Release of the following two sizes: acquireT: TransferSizes = TransferSizes.none, acquireB: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none) extends TLCommonTransferSizes { def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .intersect(rhs.acquireT), acquireB = acquireB .intersect(rhs.acquireB), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint)) def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .mincover(rhs.acquireT), acquireB = acquireB .mincover(rhs.acquireB), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint)) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(acquireT, "T"), str(acquireB, "B"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""acquireT = ${acquireT} \|acquireB = ${acquireB} \|arithmetic = ${arithmetic} \|logical = ${logical} \|get = ${get} \|putFull = ${putFull} \|putPartial = ${putPartial} \|hint = ${hint} \| \|""".stripMargin } } object TLMasterToSlaveTransferSizes { def unknownEmits = TLMasterToSlaveTransferSizes( acquireT = TransferSizes(1, 4096), acquireB = TransferSizes(1, 4096), arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096)) def unknownSupports = TLMasterToSlaveTransferSizes() } //These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel case class TLSlaveToMasterTransferSizes( probe: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none ) extends TLCommonTransferSizes { def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .intersect(rhs.probe), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint) ) def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .mincover(rhs.probe), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint) ) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(probe, "P"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""probe = ${probe} \|arithmetic = ${arithmetic} \|logical = ${logical} \|get = ${get} \|putFull = ${putFull} \|putPartial = ${putPartial} \|hint = ${hint} \| \|""".stripMargin } } object TLSlaveToMasterTransferSizes { def unknownEmits = TLSlaveToMasterTransferSizes( arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096), probe = TransferSizes(1, 4096)) def unknownSupports = TLSlaveToMasterTransferSizes() } trait TLCommonTransferSizes { def arithmetic: TransferSizes def logical: TransferSizes def get: TransferSizes def putFull: TransferSizes def putPartial: TransferSizes def hint: TransferSizes } class TLSlaveParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], setName: Option[String], val address: Seq[AddressSet], val regionType: RegionType.T, val executable: Boolean, val fifoId: Option[Int], val supports: TLMasterToSlaveTransferSizes, val emits: TLSlaveToMasterTransferSizes, // By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation) val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData // If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order // Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck // ReleaseAck may NEVER be denied extends SimpleProduct { def sortedAddress = address.sorted override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters] override def productPrefix = "TLSlaveParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 11 def productElement(n: Int): Any = n match { case 0 => name case 1 => address case 2 => resources case 3 => regionType case 4 => executable case 5 => fifoId case 6 => supports case 7 => emits case 8 => alwaysGrantsT case 9 => mayDenyGet case 10 => mayDenyPut case _ => throw new IndexOutOfBoundsException(n.toString) } def supportsAcquireT: TransferSizes = supports.acquireT def supportsAcquireB: TransferSizes = supports.acquireB def supportsArithmetic: TransferSizes = supports.arithmetic def supportsLogical: TransferSizes = supports.logical def supportsGet: TransferSizes = supports.get def supportsPutFull: TransferSizes = supports.putFull def supportsPutPartial: TransferSizes = supports.putPartial def supportsHint: TransferSizes = supports.hint require (!address.isEmpty, "Address cannot be empty") address.foreach { a => require (a.finite, "Address must be finite") } address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)") require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)") require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)") require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)") require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)") require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)") require (!alwaysGrantsT \|\| supportsAcquireT, s"Must supportAcquireT if promising to always grantT") // Make sure that the regionType agrees with the capabilities require (!supportsAcquireB \|\| regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached require (regionType <= RegionType.UNCACHED \|\| supportsAcquireB) // tracked, cached -> acquire require (regionType != RegionType.UNCACHED \|\| supportsGet) // uncached -> supportsGet val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected") val maxTransfer = List( // Largest supported transfer of all types supportsAcquireT.max, supportsAcquireB.max, supportsArithmetic.max, supportsLogical.max, supportsGet.max, supportsPutFull.max, supportsPutPartial.max).max val maxAddress = address.map(_.max).max val minAlignment = address.map(_.alignment).min // The device had better not support a transfer larger than its alignment require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)") def toResource: ResourceAddress = { ResourceAddress(address, ResourcePermissions( r = supportsAcquireB \|\| supportsGet, w = supportsAcquireT \|\| supportsPutFull, x = executable, c = supportsAcquireB, a = supportsArithmetic && supportsLogical)) } def findTreeViolation() = nodePath.find { case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false case _: SinkNode[_, _, _, _, _] => false case node => node.inputs.size != 1 } def isTree = findTreeViolation() == None def infoString = { s"""Slave Name = ${name} \|Slave Address = ${address} \|supports = ${supports.infoString} \| \|""".stripMargin } def v1copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { new TLSlaveParameters( setName = setName, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = emits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: Option[String] = setName, address: Seq[AddressSet] = address, regionType: RegionType.T = regionType, executable: Boolean = executable, fifoId: Option[Int] = fifoId, supports: TLMasterToSlaveTransferSizes = supports, emits: TLSlaveToMasterTransferSizes = emits, alwaysGrantsT: Boolean = alwaysGrantsT, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } @deprecated("Use v1copy instead of copy","") def copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { v1copy( address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supportsAcquireT = supportsAcquireT, supportsAcquireB = supportsAcquireB, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } } object TLSlaveParameters { def v1( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = { new TLSlaveParameters( setName = None, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLSlaveToMasterTransferSizes.unknownEmits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2( address: Seq[AddressSet], nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Seq(), name: Option[String] = None, regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, fifoId: Option[Int] = None, supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports, emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits, alwaysGrantsT: Boolean = false, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } } object TLManagerParameters { @deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","") def apply( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = TLSlaveParameters.v1( address, resources, regionType, executable, nodePath, supportsAcquireT, supportsAcquireB, supportsArithmetic, supportsLogical, supportsGet, supportsPutFull, supportsPutPartial, supportsHint, mayDenyGet, mayDenyPut, alwaysGrantsT, fifoId, ) } case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int]) { def members = Seq(a, b, c, d) members.collect { case Some(beatBytes) => require (isPow2(beatBytes), "Data channel width must be a power of 2") } } object TLChannelBeatBytes{ def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes( Some(beatBytes), Some(beatBytes), Some(beatBytes), Some(beatBytes)) def apply(): TLChannelBeatBytes = TLChannelBeatBytes( None, None, None, None) } class TLSlavePortParameters private( val slaves: Seq[TLSlaveParameters], val channelBytes: TLChannelBeatBytes, val endSinkId: Int, val minLatency: Int, val responseFields: Seq[BundleFieldBase], val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct { def sortedSlaves = slaves.sortBy(_.sortedAddress.head) override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters] override def productPrefix = "TLSlavePortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => slaves case 1 => channelBytes case 2 => endSinkId case 3 => minLatency case 4 => responseFields case 5 => requestKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!slaves.isEmpty, "Slave ports must have slaves") require (endSinkId >= 0, "Sink ids cannot be negative") require (minLatency >= 0, "Minimum required latency cannot be negative") // Using this API implies you cannot handle mixed-width busses def beatBytes = { channelBytes.members.foreach { width => require (width.isDefined && width == channelBytes.a) } channelBytes.a.get } // TODO this should be deprecated def managers = slaves def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = { val relevant = slaves.filter(m => policy(m)) relevant.foreach { m => require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ") } } // Bounds on required sizes def maxAddress = slaves.map(_.maxAddress).max def maxTransfer = slaves.map(_.maxTransfer).max def mayDenyGet = slaves.exists(_.mayDenyGet) def mayDenyPut = slaves.exists(_.mayDenyPut) // Diplomatically determined operation sizes emitted by all outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _) // Operation Emitted by at least one outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _) val allSupportAcquireT = allSupportClaims.acquireT val allSupportAcquireB = allSupportClaims.acquireB val allSupportArithmetic = allSupportClaims.arithmetic val allSupportLogical = allSupportClaims.logical val allSupportGet = allSupportClaims.get val allSupportPutFull = allSupportClaims.putFull val allSupportPutPartial = allSupportClaims.putPartial val allSupportHint = allSupportClaims.hint // Operation supported by at least one outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _) val anySupportAcquireT = !anySupportClaims.acquireT.none val anySupportAcquireB = !anySupportClaims.acquireB.none val anySupportArithmetic = !anySupportClaims.arithmetic.none val anySupportLogical = !anySupportClaims.logical.none val anySupportGet = !anySupportClaims.get.none val anySupportPutFull = !anySupportClaims.putFull.none val anySupportPutPartial = !anySupportClaims.putPartial.none val anySupportHint = !anySupportClaims.hint.none // Supporting Acquire means being routable for GrantAck require ((endSinkId == 0) == !anySupportAcquireB) // These return Option[TLSlaveParameters] for your convenience def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address))) // The safe version will check the entire address def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ \|\| _))) // The fast version assumes the address is valid (you probably want fastProperty instead of this function) def findFast(address: UInt) = { val routingMask = AddressDecoder(slaves.map(_.address)) VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ \|\| _))) } // Compute the simplest AddressSets that decide a key def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = { val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) => k -> vs.flatMap(_._2) } val reductionMask = AddressDecoder(groups.map(_._2)) groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) } } // Select a property def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D = Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_\|\|_), d(v)) }) // Note: returns the actual fifoId + 1 or 0 if None def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U) def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B) // Does this Port manage this ID/address? def containsSafe(address: UInt) = findSafe(address).reduce(_ \|\| _) private def addressHelper( // setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity safe: Boolean, // member filters out the sizes being checked based on the opcode being emitted or supported member: TLSlaveParameters => TransferSizes, address: UInt, lgSize: UInt, // range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity range: Option[TransferSizes]): Bool = { // trim reduces circuit complexity by intersecting checked sizes with the range argument def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x) // groupBy returns an unordered map, convert back to Seq and sort the result for determinism // groupByIntoSeq is turning slaves into trimmed membership sizes // We are grouping all the slaves by their transfer size where // if they support the trimmed size then // member is the type of transfer that you are looking for (What you are trying to filter on) // When you consider membership, you are trimming the sizes to only the ones that you care about // you are filtering the slaves based on both whether they support a particular opcode and the size // Grouping the slaves based on the actual transfer size range they support // intersecting the range and checking their membership // FOR SUPPORTCASES instead of returning the list of slaves, // you are returning a map from transfer size to the set of // address sets that are supported for that transfer size // find all the slaves that support a certain type of operation and then group their addresses by the supported size // for every size there could be multiple address ranges // safety is a trade off between checking between all possible addresses vs only the addresses // that are known to have supported sizes // the trade off is 'checking all addresses is a more expensive circuit but will always give you // the right answer even if you give it an illegal address' // the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer // fast presumes address legality // This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies. // In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size. val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) => k -> vs.flatMap(_.address) } // safe produces a circuit that compares against all possible addresses, // whereas fast presumes that the address is legal but uses an efficient address decoder val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2)) // Simplified creates the most concise possible representation of each cases' address sets based on the mask. val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) } simplified.map { case (s, a) => // s is a size, you are checking for this size either the size of the operation is in s // We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire. ((Some(s) == range).B \|\| s.containsLg(lgSize)) && a.map(_.contains(address)).reduce(_\|\|_) }.foldLeft(false.B)(_\|\|_) } def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range) def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range) def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range) def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range) def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range) def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range) def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range) def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range) def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range) def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range) def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range) def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range) def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range) def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range) def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range) def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range) def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range) def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range) def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range) def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range) def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range) def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range) def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range) def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption def isTree = !slaves.exists(!_.isTree) def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString def v1copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = managers, channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } def v2copy( slaves: Seq[TLSlaveParameters] = slaves, channelBytes: TLChannelBeatBytes = channelBytes, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = slaves, channelBytes = channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } @deprecated("Use v1copy instead of copy","") def copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { v1copy( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } object TLSlavePortParameters { def v1( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { new TLSlavePortParameters( slaves = managers, channelBytes = TLChannelBeatBytes(beatBytes), endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } } object TLManagerPortParameters { @deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","") def apply( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { TLSlavePortParameters.v1( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } class TLMasterParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], val name: String, val visibility: Seq[AddressSet], val unusedRegionTypes: Set[RegionType.T], val executesOnly: Boolean, val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C. val supports: TLSlaveToMasterTransferSizes, val emits: TLMasterToSlaveTransferSizes, val neverReleasesData: Boolean, val sourceId: IdRange) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters] override def productPrefix = "TLMasterParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 10 def productElement(n: Int): Any = n match { case 0 => name case 1 => sourceId case 2 => resources case 3 => visibility case 4 => unusedRegionTypes case 5 => executesOnly case 6 => requestFifo case 7 => supports case 8 => emits case 9 => neverReleasesData case _ => throw new IndexOutOfBoundsException(n.toString) } require (!sourceId.isEmpty) require (!visibility.isEmpty) require (supports.putFull.contains(supports.putPartial)) // We only support these operations if we support Probe (ie: we're a cache) require (supports.probe.contains(supports.arithmetic)) require (supports.probe.contains(supports.logical)) require (supports.probe.contains(supports.get)) require (supports.probe.contains(supports.putFull)) require (supports.probe.contains(supports.putPartial)) require (supports.probe.contains(supports.hint)) visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } val maxTransfer = List( supports.probe.max, supports.arithmetic.max, supports.logical.max, supports.get.max, supports.putFull.max, supports.putPartial.max).max def infoString = { s"""Master Name = ${name} \|visibility = ${visibility} \|emits = ${emits.infoString} \|sourceId = ${sourceId} \| \|""".stripMargin } def v1copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { new TLMasterParameters( nodePath = nodePath, resources = this.resources, name = name, visibility = visibility, unusedRegionTypes = this.unusedRegionTypes, executesOnly = this.executesOnly, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = this.emits, neverReleasesData = this.neverReleasesData, sourceId = sourceId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: String = name, visibility: Seq[AddressSet] = visibility, unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes, executesOnly: Boolean = executesOnly, requestFifo: Boolean = requestFifo, supports: TLSlaveToMasterTransferSizes = supports, emits: TLMasterToSlaveTransferSizes = emits, neverReleasesData: Boolean = neverReleasesData, sourceId: IdRange = sourceId) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } @deprecated("Use v1copy instead of copy","") def copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { v1copy( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } object TLMasterParameters { def v1( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { new TLMasterParameters( nodePath = nodePath, resources = Nil, name = name, visibility = visibility, unusedRegionTypes = Set(), executesOnly = false, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData = false, sourceId = sourceId) } def v2( nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Nil, name: String, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), unusedRegionTypes: Set[RegionType.T] = Set(), executesOnly: Boolean = false, requestFifo: Boolean = false, supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports, emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData: Boolean = false, sourceId: IdRange = IdRange(0,1)) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } } object TLClientParameters { @deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","") def apply( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet.everything), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { TLMasterParameters.v1( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } class TLMasterPortParameters private( val masters: Seq[TLMasterParameters], val channelBytes: TLChannelBeatBytes, val minLatency: Int, val echoFields: Seq[BundleFieldBase], val requestFields: Seq[BundleFieldBase], val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters] override def productPrefix = "TLMasterPortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => masters case 1 => channelBytes case 2 => minLatency case 3 => echoFields case 4 => requestFields case 5 => responseKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!masters.isEmpty) require (minLatency >= 0) def clients = masters // Require disjoint ranges for Ids IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) => require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}") } // Bounds on required sizes def endSourceId = masters.map(_.sourceId.end).max def maxTransfer = masters.map(_.maxTransfer).max // The unused sources < endSourceId def unusedSources: Seq[Int] = { val usedSources = masters.map(_.sourceId).sortBy(_.start) ((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) => end until start } } // Diplomatically determined operation sizes emitted by all inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = masters.map(_.emits).reduce( _ intersect _) // Diplomatically determined operation sizes Emitted by at least one inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all inward Masters // as opposed to supports* which generate circuitry to check which specific addresses val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _) val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _) val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _) val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _) val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _) val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _) val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _) // Diplomatically determined operation sizes supported by at least one master // as opposed to supports* which generate circuitry to check which specific addresses val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ \|\| _) val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ \|\| _) val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ \|\| _) val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ \|\| _) val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ \|\| _) val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ \|\| _) val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ \|\| _) // These return Option[TLMasterParameters] for your convenience def find(id: Int) = masters.find(_.sourceId.contains(id)) // Synthesizable lookup methods def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id))) def contains(id: UInt) = find(id).reduce(_ \|\| _) def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B)) // Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = { val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _) // this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version; // the case where there is only one group. if (allSame) member(masters(0)).containsLg(lgSize) else { // Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize Mux1H(find(id), masters.map(member(_).containsLg(lgSize))) } } // Check for support of a given operation at a specific id val supportsProbe = sourceIdHelper(_.supports.probe) _ val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _ val supportsLogical = sourceIdHelper(_.supports.logical) _ val supportsGet = sourceIdHelper(_.supports.get) _ val supportsPutFull = sourceIdHelper(_.supports.putFull) _ val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _ val supportsHint = sourceIdHelper(_.supports.hint) _ // TODO: Merge sourceIdHelper2 with sourceIdHelper private def sourceIdHelper2( member: TLMasterParameters => TransferSizes, sourceId: UInt, lgSize: UInt): Bool = { // Because sourceIds are uniquely owned by each master, we use them to group the // cases that have to be checked. val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) => k -> vs.map(_.sourceId) } emitCases.map { case (s, a) => (s.containsLg(lgSize)) && a.map(_.contains(sourceId)).reduce(_\|\|_) }.foldLeft(false.B)(_\|\|_) } // Check for emit of a given operation at a specific id def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize) def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize) def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize) def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize) def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize) def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize) def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize) def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize) def infoString = masters.map(_.infoString).mkString def v1copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = clients, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2copy( masters: Seq[TLMasterParameters] = masters, channelBytes: TLChannelBeatBytes = channelBytes, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } @deprecated("Use v1copy instead of copy","") def copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { v1copy( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLClientPortParameters { @deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","") def apply( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { TLMasterPortParameters.v1( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLMasterPortParameters { def v1( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = clients, channelBytes = TLChannelBeatBytes(), minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2( masters: Seq[TLMasterParameters], channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(), minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } } case class TLBundleParameters( addressBits: Int, dataBits: Int, sourceBits: Int, sinkBits: Int, sizeBits: Int, echoFields: Seq[BundleFieldBase], requestFields: Seq[BundleFieldBase], responseFields: Seq[BundleFieldBase], hasBCE: Boolean) { // Chisel has issues with 0-width wires require (addressBits >= 1) require (dataBits >= 8) require (sourceBits >= 1) require (sinkBits >= 1) require (sizeBits >= 1) require (isPow2(dataBits)) echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") } val addrLoBits = log2Up(dataBits/8) // Used to uniquify bus IP names def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u") def union(x: TLBundleParameters) = TLBundleParameters( max(addressBits, x.addressBits), max(dataBits, x.dataBits), max(sourceBits, x.sourceBits), max(sinkBits, x.sinkBits), max(sizeBits, x.sizeBits), echoFields = BundleField.union(echoFields ++ x.echoFields), requestFields = BundleField.union(requestFields ++ x.requestFields), responseFields = BundleField.union(responseFields ++ x.responseFields), hasBCE \|\| x.hasBCE) } object TLBundleParameters { val emptyBundleParams = TLBundleParameters( addressBits = 1, dataBits = 8, sourceBits = 1, sinkBits = 1, sizeBits = 1, echoFields = Nil, requestFields = Nil, responseFields = Nil, hasBCE = false) def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y)) def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) = new TLBundleParameters( addressBits = log2Up(slave.maxAddress + 1), dataBits = slave.beatBytes * 8, sourceBits = log2Up(master.endSourceId), sinkBits = log2Up(slave.endSinkId), sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1), echoFields = master.echoFields, requestFields = BundleField.accept(master.requestFields, slave.requestKeys), responseFields = BundleField.accept(slave.responseFields, master.responseKeys), hasBCE = master.anySupportProbe && slave.anySupportAcquireB) } case class TLEdgeParameters( master: TLMasterPortParameters, slave: TLSlavePortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { // legacy names: def manager = slave def client = master val maxTransfer = max(master.maxTransfer, slave.maxTransfer) val maxLgSize = log2Ceil(maxTransfer) // Sanity check the link... require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})") def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims) val bundle = TLBundleParameters(master, slave) def formatEdge = master.infoString + "\n" + slave.infoString } case class TLCreditedDelay( a: CreditedDelay, b: CreditedDelay, c: CreditedDelay, d: CreditedDelay, e: CreditedDelay) { def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay( a = a + that.a, b = b + that.b, c = c + that.c, d = d + that.d, e = e + that.e) override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})" } object TLCreditedDelay { def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay) } case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString} case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val delay = client.delay + manager.delay val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters) case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base)) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } // To be unified, devices must agree on all of these terms case class ManagerUnificationKey( resources: Seq[Resource], regionType: RegionType.T, executable: Boolean, supportsAcquireT: TransferSizes, supportsAcquireB: TransferSizes, supportsArithmetic: TransferSizes, supportsLogical: TransferSizes, supportsGet: TransferSizes, supportsPutFull: TransferSizes, supportsPutPartial: TransferSizes, supportsHint: TransferSizes) object ManagerUnificationKey { def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey( resources = x.resources, regionType = x.regionType, executable = x.executable, supportsAcquireT = x.supportsAcquireT, supportsAcquireB = x.supportsAcquireB, supportsArithmetic = x.supportsArithmetic, supportsLogical = x.supportsLogical, supportsGet = x.supportsGet, supportsPutFull = x.supportsPutFull, supportsPutPartial = x.supportsPutPartial, supportsHint = x.supportsHint) } object ManagerUnification { def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = { slaves.groupBy(ManagerUnificationKey.apply).values.map { seq => val agree = seq.forall(_.fifoId == seq.head.fifoId) seq(0).v1copy( address = AddressSet.unify(seq.flatMap(_.address)), fifoId = if (agree) seq(0).fifoId else None) }.toList } } case class TLBufferParams( a: BufferParams = BufferParams.none, b: BufferParams = BufferParams.none, c: BufferParams = BufferParams.none, d: BufferParams = BufferParams.none, e: BufferParams = BufferParams.none ) extends DirectedBuffers[TLBufferParams] { def copyIn(x: BufferParams) = this.copy(b = x, d = x) def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x) def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x) } /** Pretty printing of TL source id maps / class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] { private val tlDigits = String.valueOf(tl.endSourceId-1).length() protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s" private val sorted = tl.masters.sortBy(_.sourceId) val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c => TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo) } } case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean) extends IdMapEntry { val from = tlId val to = tlId val maxTransactionsInFlight = Some(tlId.size) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_46( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [15:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [127:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [127:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [5:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [15:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [127:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [5:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [127:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [7:0] c_first_beats1_decode = 8'h0; // @[Edges.scala:220:59] wire [7:0] c_first_beats1 = 8'h0; // @[Edges.scala:221:14] wire [7:0] _c_first_count_T = 8'h0; // @[Edges.scala:234:27] wire [7:0] c_first_count = 8'h0; // @[Edges.scala:234:25] wire [7:0] _c_first_counter_T = 8'h0; // @[Edges.scala:236:21] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_4 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:56:48] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_10 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:56:48] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [7:0] c_first_counter1 = 8'hFF; // @[Edges.scala:230:28] wire [8:0] _c_first_counter1_T = 9'h1FF; // @[Edges.scala:230:28] wire [127:0] _c_first_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_first_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_first_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_first_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_set_wo_ready_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_set_wo_ready_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_opcodes_set_interm_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_opcodes_set_interm_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_sizes_set_interm_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_sizes_set_interm_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_opcodes_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_opcodes_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_sizes_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_sizes_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_probe_ack_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_probe_ack_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_probe_ack_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_probe_ack_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_4_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_5_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [5:0] _c_first_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_first_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_first_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_first_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_set_wo_ready_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_set_wo_ready_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_set_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_set_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_opcodes_set_interm_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_opcodes_set_interm_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_sizes_set_interm_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_sizes_set_interm_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_opcodes_set_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_opcodes_set_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_sizes_set_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_sizes_set_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_probe_ack_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_probe_ack_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_probe_ack_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_probe_ack_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _same_cycle_resp_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _same_cycle_resp_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _same_cycle_resp_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _same_cycle_resp_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _same_cycle_resp_WIRE_4_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _same_cycle_resp_WIRE_5_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [515:0] _c_sizes_set_T_1 = 516'h0; // @[Monitor.scala:768:52] wire [8:0] _c_opcodes_set_T = 9'h0; // @[Monitor.scala:767:79] wire [8:0] _c_sizes_set_T = 9'h0; // @[Monitor.scala:768:77] wire [514:0] _c_opcodes_set_T_1 = 515'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [63:0] _c_set_wo_ready_T = 64'h1; // @[OneHot.scala:58:35] wire [63:0] _c_set_T = 64'h1; // @[OneHot.scala:58:35] wire [511:0] c_sizes_set = 512'h0; // @[Monitor.scala:741:34] wire [255:0] c_opcodes_set = 256'h0; // @[Monitor.scala:740:34] wire [63:0] c_set = 64'h0; // @[Monitor.scala:738:34] wire [63:0] c_set_wo_ready = 64'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [5:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire [3:0] mask_sizeOH = {_mask_sizeOH_T_2[3:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_sub_0_1 = \|(io_in_a_bits_size_0[3:2]); // @[Misc.scala:206:21] wire mask_sub_sub_sub_size = mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_sub_bit = io_in_a_bits_address_0[3]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_1_2 = mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_nbit = ~mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_0_2 = mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_acc_T = mask_sub_sub_sub_size & mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_0_1 \| _mask_sub_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_size & mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_0_1 \| _mask_sub_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_1_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_2_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size & mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_2_1 = mask_sub_sub_sub_1_1 \| _mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_3_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size & mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_3_1 = mask_sub_sub_sub_1_1 \| _mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_4_2 = mask_sub_sub_2_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_4 = mask_sub_size & mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_4_1 = mask_sub_sub_2_1 \| _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_5_2 = mask_sub_sub_2_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_5 = mask_sub_size & mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_5_1 = mask_sub_sub_2_1 \| _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_6_2 = mask_sub_sub_3_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_6 = mask_sub_size & mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_6_1 = mask_sub_sub_3_1 \| _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_7_2 = mask_sub_sub_3_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_7 = mask_sub_size & mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_7_1 = mask_sub_sub_3_1 \| _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_eq_8 = mask_sub_4_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_size & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_8 = mask_sub_4_1 \| _mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_eq_9 = mask_sub_4_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_size & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_9 = mask_sub_4_1 \| _mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_eq_10 = mask_sub_5_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_size & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_10 = mask_sub_5_1 \| _mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_eq_11 = mask_sub_5_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_size & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_11 = mask_sub_5_1 \| _mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_eq_12 = mask_sub_6_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_size & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_12 = mask_sub_6_1 \| _mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_eq_13 = mask_sub_6_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_size & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_13 = mask_sub_6_1 \| _mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_eq_14 = mask_sub_7_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_size & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_14 = mask_sub_7_1 \| _mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_eq_15 = mask_sub_7_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_size & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_15 = mask_sub_7_1 \| _mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_lo = {mask_lo_lo_hi, mask_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_hi = {mask_lo_hi_hi, mask_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_lo_hi = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_lo = {mask_hi_lo_hi, mask_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_hi = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_hi = {mask_hi_hi_hi, mask_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [15:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [5:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [5:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _T_1267 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1267; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1267; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [7:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [7:0] a_first_counter; // @[Edges.scala:229:27] wire [8:0] _a_first_counter1_T = {1'h0, a_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] a_first_counter1 = _a_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [7:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [5:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1340 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1340; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1340; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1340; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [7:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T = {1'h0, d_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1 = _d_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [5:0] source_1; // @[Monitor.scala:541:22] reg [3:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [63:0] inflight; // @[Monitor.scala:614:27] reg [255:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [511:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [7:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [7:0] a_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] a_first_counter1_1 = _a_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [7:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_1 = _d_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [63:0] a_set; // @[Monitor.scala:626:34] wire [63:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [255:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [511:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [8:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [8:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [8:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [8:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [8:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [255:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [255:0] _a_opcode_lookup_T_6 = {252'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [255:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[255:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [8:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [8:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [8:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [8:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [8:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [511:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [511:0] _a_size_lookup_T_6 = {504'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [511:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[511:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [63:0] _GEN_3 = {58'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35] wire [63:0] _GEN_4 = 64'h1 << _GEN_3; // @[OneHot.scala:58:35] wire [63:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35] wire [63:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 64'h0; // @[OneHot.scala:58:35] wire _T_1193 = _T_1267 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1193 ? _a_set_T : 64'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1193 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1193 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [8:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [514:0] _a_opcodes_set_T_1 = {511'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1193 ? _a_opcodes_set_T_1[255:0] : 256'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [8:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [515:0] _a_sizes_set_T_1 = {511'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1193 ? _a_sizes_set_T_1[511:0] : 512'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [63:0] d_clr; // @[Monitor.scala:664:34] wire [63:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [255:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [511:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46] wire _T_1239 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [63:0] _GEN_6 = {58'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [63:0] _GEN_7 = 64'h1 << _GEN_6; // @[OneHot.scala:58:35] wire [63:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35] wire [63:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35] wire [63:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35] wire [63:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1239 & ~d_release_ack ? _d_clr_wo_ready_T : 64'h0; // @[OneHot.scala:58:35] wire _T_1208 = _T_1340 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1208 ? _d_clr_T : 64'h0; // @[OneHot.scala:58:35] wire [526:0] _d_opcodes_clr_T_5 = 527'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1208 ? _d_opcodes_clr_T_5[255:0] : 256'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [526:0] _d_sizes_clr_T_5 = 527'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1208 ? _d_sizes_clr_T_5[511:0] : 512'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [63:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [63:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [63:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [255:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [255:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [255:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [511:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [511:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [511:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [63:0] inflight_1; // @[Monitor.scala:726:35] wire [63:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [255:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [255:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [511:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [511:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_2; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_2 = _d_first_counter1_T_2[7:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [255:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [255:0] _c_opcode_lookup_T_6 = {252'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [255:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[255:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [511:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [511:0] _c_size_lookup_T_6 = {504'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [511:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[511:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [63:0] d_clr_1; // @[Monitor.scala:774:34] wire [63:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [255:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [511:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1311 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1311 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 64'h0; // @[OneHot.scala:58:35] wire _T_1293 = _T_1340 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1293 ? _d_clr_T_1 : 64'h0; // @[OneHot.scala:58:35] wire [526:0] _d_opcodes_clr_T_11 = 527'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1293 ? _d_opcodes_clr_T_11[255:0] : 256'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [526:0] _d_sizes_clr_T_11 = 527'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1293 ? _d_sizes_clr_T_11[511:0] : 512'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 6'h0; // @[Monitor.scala:36:7, :795:113] wire [63:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [63:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [255:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [255:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [511:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [511:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_40( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [20:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_37 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_43 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_49 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_wo_ready_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_wo_ready_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_4_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_5_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire _source_ok_T_27 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31] wire _source_ok_T_28 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_29 = _source_ok_T_28 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_30 = _source_ok_T_29 \| _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_31 = _source_ok_T_30 \| _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_32 = _source_ok_T_31 \| _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_33 = _source_ok_T_32 \| _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_33 \| _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [20:0] _is_aligned_T = {15'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 21'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_34 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_34; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_35 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_41 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_47 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_53 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_36 = _source_ok_T_35 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_38 = _source_ok_T_36; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_40; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_42 = _source_ok_T_41 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_44 = _source_ok_T_42; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_46; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_48 = _source_ok_T_47 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_50 = _source_ok_T_48; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_52; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_54 = _source_ok_T_53 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_58; // @[Parameters.scala:1138:31] wire _source_ok_T_59 = io_in_d_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_59; // @[Parameters.scala:1138:31] wire _source_ok_T_60 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_60; // @[Parameters.scala:1138:31] wire _source_ok_T_61 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_61; // @[Parameters.scala:1138:31] wire _source_ok_T_62 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_63 = _source_ok_T_62 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_64 = _source_ok_T_63 \| _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_65 = _source_ok_T_64 \| _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_66 = _source_ok_T_65 \| _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_67 = _source_ok_T_66 \| _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_67 \| _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _T_975 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_975; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_975; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [20:0] address; // @[Monitor.scala:391:22] wire _T_1043 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1043; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1043; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1043; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [259:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [259:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_908 = _T_975 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_908 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_908 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_908 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_908 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_908 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_954 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_954 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_923 = _T_1043 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_923 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_923 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_923 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [259:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1019 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1019 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1001 = _T_1043 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1001 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1001 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1001 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands / class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B \|\| ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B \|\| ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def (t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def (t: UInt) = self t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros \| ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def (t: SInt) = self t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros \| ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid \|\| output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid \|\| output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid \|\| output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def (t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def (t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }	module PE_478( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = \|_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros \| io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = \|_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 \| io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 \| io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_222 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Metadata.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.constants.MemoryOpConstants import freechips.rocketchip.util._ object ClientStates { val width = 2 def Nothing = 0.U(width.W) def Branch = 1.U(width.W) def Trunk = 2.U(width.W) def Dirty = 3.U(width.W) def hasReadPermission(state: UInt): Bool = state > Nothing def hasWritePermission(state: UInt): Bool = state > Branch } object MemoryOpCategories extends MemoryOpConstants { def wr = Cat(true.B, true.B) // Op actually writes def wi = Cat(false.B, true.B) // Future op will write def rd = Cat(false.B, false.B) // Op only reads def categorize(cmd: UInt): UInt = { val cat = Cat(isWrite(cmd), isWriteIntent(cmd)) //assert(cat.isOneOf(wr,wi,rd), "Could not categorize command.") cat } } /* Stores the client-side coherence information, * such as permissions on the data and whether the data is dirty. * Its API can be used to make TileLink messages in response to * memory operations, cache control oeprations, or Probe messages. / class ClientMetadata extends Bundle { /* Actual state information stored in this bundle / val state = UInt(ClientStates.width.W) /* Metadata equality / def ===(rhs: UInt): Bool = state === rhs def ===(rhs: ClientMetadata): Bool = state === rhs.state def =/=(rhs: ClientMetadata): Bool = !this.===(rhs) /* Is the block's data present in this cache / def isValid(dummy: Int = 0): Bool = state > ClientStates.Nothing /* Determine whether this cmd misses, and the new state (on hit) or param to be sent (on miss) / private def growStarter(cmd: UInt): (Bool, UInt) = { import MemoryOpCategories._ import TLPermissions._ import ClientStates._ val c = categorize(cmd) MuxTLookup(Cat(c, state), (false.B, 0.U), Seq( //(effect, am now) -> (was a hit, next) Cat(rd, Dirty) -> (true.B, Dirty), Cat(rd, Trunk) -> (true.B, Trunk), Cat(rd, Branch) -> (true.B, Branch), Cat(wi, Dirty) -> (true.B, Dirty), Cat(wi, Trunk) -> (true.B, Trunk), Cat(wr, Dirty) -> (true.B, Dirty), Cat(wr, Trunk) -> (true.B, Dirty), //(effect, am now) -> (was a miss, param) Cat(rd, Nothing) -> (false.B, NtoB), Cat(wi, Branch) -> (false.B, BtoT), Cat(wi, Nothing) -> (false.B, NtoT), Cat(wr, Branch) -> (false.B, BtoT), Cat(wr, Nothing) -> (false.B, NtoT))) } /* Determine what state to go to after miss based on Grant param * For now, doesn't depend on state (which may have been Probed). / private def growFinisher(cmd: UInt, param: UInt): UInt = { import MemoryOpCategories._ import TLPermissions._ import ClientStates._ val c = categorize(cmd) //assert(c === rd \|\| param === toT, "Client was expecting trunk permissions.") MuxLookup(Cat(c, param), Nothing)(Seq( //(effect param) -> (next) Cat(rd, toB) -> Branch, Cat(rd, toT) -> Trunk, Cat(wi, toT) -> Trunk, Cat(wr, toT) -> Dirty)) } /* Does this cache have permissions on this block sufficient to perform op, * and what to do next (Acquire message param or updated metadata). / def onAccess(cmd: UInt): (Bool, UInt, ClientMetadata) = { val r = growStarter(cmd) (r._1, r._2, ClientMetadata(r._2)) } /* Does a secondary miss on the block require another Acquire message / def onSecondaryAccess(first_cmd: UInt, second_cmd: UInt): (Bool, Bool, UInt, ClientMetadata, UInt) = { import MemoryOpCategories._ val r1 = growStarter(first_cmd) val r2 = growStarter(second_cmd) val needs_second_acq = isWriteIntent(second_cmd) && !isWriteIntent(first_cmd) val hit_again = r1._1 && r2._1 val dirties = categorize(second_cmd) === wr val biggest_grow_param = Mux(dirties, r2._2, r1._2) val dirtiest_state = ClientMetadata(biggest_grow_param) val dirtiest_cmd = Mux(dirties, second_cmd, first_cmd) (needs_second_acq, hit_again, biggest_grow_param, dirtiest_state, dirtiest_cmd) } /* Metadata change on a returned Grant / def onGrant(cmd: UInt, param: UInt): ClientMetadata = ClientMetadata(growFinisher(cmd, param)) /* Determine what state to go to based on Probe param / private def shrinkHelper(param: UInt): (Bool, UInt, UInt) = { import ClientStates._ import TLPermissions._ MuxTLookup(Cat(param, state), (false.B, 0.U, 0.U), Seq( //(wanted, am now) -> (hasDirtyData resp, next) Cat(toT, Dirty) -> (true.B, TtoT, Trunk), Cat(toT, Trunk) -> (false.B, TtoT, Trunk), Cat(toT, Branch) -> (false.B, BtoB, Branch), Cat(toT, Nothing) -> (false.B, NtoN, Nothing), Cat(toB, Dirty) -> (true.B, TtoB, Branch), Cat(toB, Trunk) -> (false.B, TtoB, Branch), // Policy: Don't notify on clean downgrade Cat(toB, Branch) -> (false.B, BtoB, Branch), Cat(toB, Nothing) -> (false.B, NtoN, Nothing), Cat(toN, Dirty) -> (true.B, TtoN, Nothing), Cat(toN, Trunk) -> (false.B, TtoN, Nothing), // Policy: Don't notify on clean downgrade Cat(toN, Branch) -> (false.B, BtoN, Nothing), // Policy: Don't notify on clean downgrade Cat(toN, Nothing) -> (false.B, NtoN, Nothing))) } /* Translate cache control cmds into Probe param / private def cmdToPermCap(cmd: UInt): UInt = { import MemoryOpCategories._ import TLPermissions._ MuxLookup(cmd, toN)(Seq( M_FLUSH -> toN, M_PRODUCE -> toB, M_CLEAN -> toT)) } def onCacheControl(cmd: UInt): (Bool, UInt, ClientMetadata) = { val r = shrinkHelper(cmdToPermCap(cmd)) (r._1, r._2, ClientMetadata(r._3)) } def onProbe(param: UInt): (Bool, UInt, ClientMetadata) = { val r = shrinkHelper(param) (r._1, r._2, ClientMetadata(r._3)) } } /* Factories for ClientMetadata, including on reset / object ClientMetadata { def apply(perm: UInt) = { val meta = Wire(new ClientMetadata) meta.state := perm meta } def onReset = ClientMetadata(ClientStates.Nothing) def maximum = ClientMetadata(ClientStates.Dirty) } File Consts.scala: // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket.constants import chisel3._ import chisel3.util._ import freechips.rocketchip.util._ trait ScalarOpConstants { val SZ_BR = 3 def BR_X = BitPat("b???") def BR_EQ = 0.U(3.W) def BR_NE = 1.U(3.W) def BR_J = 2.U(3.W) def BR_N = 3.U(3.W) def BR_LT = 4.U(3.W) def BR_GE = 5.U(3.W) def BR_LTU = 6.U(3.W) def BR_GEU = 7.U(3.W) def A1_X = BitPat("b??") def A1_ZERO = 0.U(2.W) def A1_RS1 = 1.U(2.W) def A1_PC = 2.U(2.W) def A1_RS1SHL = 3.U(2.W) def IMM_X = BitPat("b???") def IMM_S = 0.U(3.W) def IMM_SB = 1.U(3.W) def IMM_U = 2.U(3.W) def IMM_UJ = 3.U(3.W) def IMM_I = 4.U(3.W) def IMM_Z = 5.U(3.W) def A2_X = BitPat("b???") def A2_ZERO = 0.U(3.W) def A2_SIZE = 1.U(3.W) def A2_RS2 = 2.U(3.W) def A2_IMM = 3.U(3.W) def A2_RS2OH = 4.U(3.W) def A2_IMMOH = 5.U(3.W) def X = BitPat("b?") def N = BitPat("b0") def Y = BitPat("b1") val SZ_DW = 1 def DW_X = X def DW_32 = false.B def DW_64 = true.B def DW_XPR = DW_64 } trait MemoryOpConstants { val NUM_XA_OPS = 9 val M_SZ = 5 def M_X = BitPat("b?????"); def M_XRD = "b00000".U; // int load def M_XWR = "b00001".U; // int store def M_PFR = "b00010".U; // prefetch with intent to read def M_PFW = "b00011".U; // prefetch with intent to write def M_XA_SWAP = "b00100".U def M_FLUSH_ALL = "b00101".U // flush all lines def M_XLR = "b00110".U def M_XSC = "b00111".U def M_XA_ADD = "b01000".U def M_XA_XOR = "b01001".U def M_XA_OR = "b01010".U def M_XA_AND = "b01011".U def M_XA_MIN = "b01100".U def M_XA_MAX = "b01101".U def M_XA_MINU = "b01110".U def M_XA_MAXU = "b01111".U def M_FLUSH = "b10000".U // write back dirty data and cede R/W permissions def M_PWR = "b10001".U // partial (masked) store def M_PRODUCE = "b10010".U // write back dirty data and cede W permissions def M_CLEAN = "b10011".U // write back dirty data and retain R/W permissions def M_SFENCE = "b10100".U // SFENCE.VMA def M_HFENCEV = "b10101".U // HFENCE.VVMA def M_HFENCEG = "b10110".U // HFENCE.GVMA def M_WOK = "b10111".U // check write permissions but don't perform a write def M_HLVX = "b10000".U // HLVX instruction def isAMOLogical(cmd: UInt) = cmd.isOneOf(M_XA_SWAP, M_XA_XOR, M_XA_OR, M_XA_AND) def isAMOArithmetic(cmd: UInt) = cmd.isOneOf(M_XA_ADD, M_XA_MIN, M_XA_MAX, M_XA_MINU, M_XA_MAXU) def isAMO(cmd: UInt) = isAMOLogical(cmd) \|\| isAMOArithmetic(cmd) def isPrefetch(cmd: UInt) = cmd === M_PFR \|\| cmd === M_PFW def isRead(cmd: UInt) = cmd.isOneOf(M_XRD, M_HLVX, M_XLR, M_XSC) \|\| isAMO(cmd) def isWrite(cmd: UInt) = cmd === M_XWR \|\| cmd === M_PWR \|\| cmd === M_XSC \|\| isAMO(cmd) def isWriteIntent(cmd: UInt) = isWrite(cmd) \|\| cmd === M_PFW \|\| cmd === M_XLR } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /* Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File mshrs.scala: //***************************************************************************** // Ported from Rocket-Chip // See LICENSE.Berkeley and LICENSE.SiFive in Rocket-Chip for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.lsu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.tile._ import freechips.rocketchip.util._ import freechips.rocketchip.rocket._ import boom.v3.common._ import boom.v3.exu.BrUpdateInfo import boom.v3.util.{IsKilledByBranch, GetNewBrMask, BranchKillableQueue, IsOlder, UpdateBrMask, AgePriorityEncoder, WrapInc} class BoomDCacheReqInternal(implicit p: Parameters) extends BoomDCacheReq()(p) with HasL1HellaCacheParameters { // miss info val tag_match = Bool() val old_meta = new L1Metadata val way_en = UInt(nWays.W) // Used in the MSHRs val sdq_id = UInt(log2Ceil(cfg.nSDQ).W) } class BoomMSHR(implicit edge: TLEdgeOut, p: Parameters) extends BoomModule()(p) with HasL1HellaCacheParameters { val io = IO(new Bundle { val id = Input(UInt()) val req_pri_val = Input(Bool()) val req_pri_rdy = Output(Bool()) val req_sec_val = Input(Bool()) val req_sec_rdy = Output(Bool()) val clear_prefetch = Input(Bool()) val brupdate = Input(new BrUpdateInfo) val exception = Input(Bool()) val rob_pnr_idx = Input(UInt(robAddrSz.W)) val rob_head_idx = Input(UInt(robAddrSz.W)) val req = Input(new BoomDCacheReqInternal) val req_is_probe = Input(Bool()) val idx = Output(Valid(UInt())) val way = Output(Valid(UInt())) val tag = Output(Valid(UInt())) val mem_acquire = Decoupled(new TLBundleA(edge.bundle)) val mem_grant = Flipped(Decoupled(new TLBundleD(edge.bundle))) val mem_finish = Decoupled(new TLBundleE(edge.bundle)) val prober_state = Input(Valid(UInt(coreMaxAddrBits.W))) val refill = Decoupled(new L1DataWriteReq) val meta_write = Decoupled(new L1MetaWriteReq) val meta_read = Decoupled(new L1MetaReadReq) val meta_resp = Input(Valid(new L1Metadata)) val wb_req = Decoupled(new WritebackReq(edge.bundle)) // To inform the prefetcher when we are commiting the fetch of this line val commit_val = Output(Bool()) val commit_addr = Output(UInt(coreMaxAddrBits.W)) val commit_coh = Output(new ClientMetadata) // Reading from the line buffer val lb_read = Decoupled(new LineBufferReadReq) val lb_resp = Input(UInt(encRowBits.W)) val lb_write = Decoupled(new LineBufferWriteReq) // Replays go through the cache pipeline again val replay = Decoupled(new BoomDCacheReqInternal) // Resp go straight out to the core val resp = Decoupled(new BoomDCacheResp) // Writeback unit tells us when it is done processing our wb val wb_resp = Input(Bool()) val probe_rdy = Output(Bool()) }) // TODO: Optimize this. We don't want to mess with cache during speculation // s_refill_req : Make a request for a new cache line // s_refill_resp : Store the refill response into our buffer // s_drain_rpq_loads : Drain out loads from the rpq // : If miss was misspeculated, go to s_invalid // s_wb_req : Write back the evicted cache line // s_wb_resp : Finish writing back the evicted cache line // s_meta_write_req : Write the metadata for new cache lne // s_meta_write_resp : val s_invalid :: s_refill_req :: s_refill_resp :: s_drain_rpq_loads :: s_meta_read :: s_meta_resp_1 :: s_meta_resp_2 :: s_meta_clear :: s_wb_meta_read :: s_wb_req :: s_wb_resp :: s_commit_line :: s_drain_rpq :: s_meta_write_req :: s_mem_finish_1 :: s_mem_finish_2 :: s_prefetched :: s_prefetch :: Nil = Enum(18) val state = RegInit(s_invalid) val req = Reg(new BoomDCacheReqInternal) val req_idx = req.addr(untagBits-1, blockOffBits) val req_tag = req.addr >> untagBits val req_block_addr = (req.addr >> blockOffBits) << blockOffBits val req_needs_wb = RegInit(false.B) val new_coh = RegInit(ClientMetadata.onReset) val (_, shrink_param, coh_on_clear) = req.old_meta.coh.onCacheControl(M_FLUSH) val grow_param = new_coh.onAccess(req.uop.mem_cmd)._2 val coh_on_grant = new_coh.onGrant(req.uop.mem_cmd, io.mem_grant.bits.param) // We only accept secondary misses if the original request had sufficient permissions val (cmd_requires_second_acquire, is_hit_again, _, dirtier_coh, dirtier_cmd) = new_coh.onSecondaryAccess(req.uop.mem_cmd, io.req.uop.mem_cmd) val (_, _, refill_done, refill_address_inc) = edge.addr_inc(io.mem_grant) val sec_rdy = (!cmd_requires_second_acquire && !io.req_is_probe && !state.isOneOf(s_invalid, s_meta_write_req, s_mem_finish_1, s_mem_finish_2))// Always accept secondary misses val rpq = Module(new BranchKillableQueue(new BoomDCacheReqInternal, cfg.nRPQ, u => u.uses_ldq, false)) rpq.io.brupdate := io.brupdate rpq.io.flush := io.exception assert(!(state === s_invalid && !rpq.io.empty)) rpq.io.enq.valid := ((io.req_pri_val && io.req_pri_rdy) \|\| (io.req_sec_val && io.req_sec_rdy)) && !isPrefetch(io.req.uop.mem_cmd) rpq.io.enq.bits := io.req rpq.io.deq.ready := false.B val grantack = Reg(Valid(new TLBundleE(edge.bundle))) val refill_ctr = Reg(UInt(log2Ceil(cacheDataBeats).W)) val commit_line = Reg(Bool()) val grant_had_data = Reg(Bool()) val finish_to_prefetch = Reg(Bool()) // Block probes if a tag write we started is still in the pipeline val meta_hazard = RegInit(0.U(2.W)) when (meta_hazard =/= 0.U) { meta_hazard := meta_hazard + 1.U } when (io.meta_write.fire) { meta_hazard := 1.U } io.probe_rdy := (meta_hazard === 0.U && (state.isOneOf(s_invalid, s_refill_req, s_refill_resp, s_drain_rpq_loads) \|\| (state === s_meta_read && grantack.valid))) io.idx.valid := state =/= s_invalid io.tag.valid := state =/= s_invalid io.way.valid := !state.isOneOf(s_invalid, s_prefetch) io.idx.bits := req_idx io.tag.bits := req_tag io.way.bits := req.way_en io.meta_write.valid := false.B io.meta_write.bits := DontCare io.req_pri_rdy := false.B io.req_sec_rdy := sec_rdy && rpq.io.enq.ready io.mem_acquire.valid := false.B io.mem_acquire.bits := DontCare io.refill.valid := false.B io.refill.bits := DontCare io.replay.valid := false.B io.replay.bits := DontCare io.wb_req.valid := false.B io.wb_req.bits := DontCare io.resp.valid := false.B io.resp.bits := DontCare io.commit_val := false.B io.commit_addr := req.addr io.commit_coh := coh_on_grant io.meta_read.valid := false.B io.meta_read.bits := DontCare io.mem_finish.valid := false.B io.mem_finish.bits := DontCare io.lb_write.valid := false.B io.lb_write.bits := DontCare io.lb_read.valid := false.B io.lb_read.bits := DontCare io.mem_grant.ready := false.B when (io.req_sec_val && io.req_sec_rdy) { req.uop.mem_cmd := dirtier_cmd when (is_hit_again) { new_coh := dirtier_coh } } def handle_pri_req(old_state: UInt): UInt = { val new_state = WireInit(old_state) grantack.valid := false.B refill_ctr := 0.U assert(rpq.io.enq.ready) req := io.req val old_coh = io.req.old_meta.coh req_needs_wb := old_coh.onCacheControl(M_FLUSH)._1 // does the line we are evicting need to be written back when (io.req.tag_match) { val (is_hit, _, coh_on_hit) = old_coh.onAccess(io.req.uop.mem_cmd) when (is_hit) { // set dirty bit assert(isWrite(io.req.uop.mem_cmd)) new_coh := coh_on_hit new_state := s_drain_rpq } .otherwise { // upgrade permissions new_coh := old_coh new_state := s_refill_req } } .otherwise { // refill and writeback if necessary new_coh := ClientMetadata.onReset new_state := s_refill_req } new_state } when (state === s_invalid) { io.req_pri_rdy := true.B grant_had_data := false.B when (io.req_pri_val && io.req_pri_rdy) { state := handle_pri_req(state) } } .elsewhen (state === s_refill_req) { io.mem_acquire.valid := true.B // TODO: Use AcquirePerm if just doing permissions acquire io.mem_acquire.bits := edge.AcquireBlock( fromSource = io.id, toAddress = Cat(req_tag, req_idx) << blockOffBits, lgSize = lgCacheBlockBytes.U, growPermissions = grow_param)._2 when (io.mem_acquire.fire) { state := s_refill_resp } } .elsewhen (state === s_refill_resp) { when (edge.hasData(io.mem_grant.bits)) { io.mem_grant.ready := io.lb_write.ready io.lb_write.valid := io.mem_grant.valid io.lb_write.bits.id := io.id io.lb_write.bits.offset := refill_address_inc >> rowOffBits io.lb_write.bits.data := io.mem_grant.bits.data } .otherwise { io.mem_grant.ready := true.B } when (io.mem_grant.fire) { grant_had_data := edge.hasData(io.mem_grant.bits) } when (refill_done) { grantack.valid := edge.isRequest(io.mem_grant.bits) grantack.bits := edge.GrantAck(io.mem_grant.bits) state := Mux(grant_had_data, s_drain_rpq_loads, s_drain_rpq) assert(!(!grant_had_data && req_needs_wb)) commit_line := false.B new_coh := coh_on_grant } } .elsewhen (state === s_drain_rpq_loads) { val drain_load = (isRead(rpq.io.deq.bits.uop.mem_cmd) && !isWrite(rpq.io.deq.bits.uop.mem_cmd) && (rpq.io.deq.bits.uop.mem_cmd =/= M_XLR)) // LR should go through replay // drain all loads for now val rp_addr = Cat(req_tag, req_idx, rpq.io.deq.bits.addr(blockOffBits-1,0)) val word_idx = if (rowWords == 1) 0.U else rp_addr(log2Up(rowWordscoreDataBytes)-1, log2Up(wordBytes)) val data = io.lb_resp val data_word = data >> Cat(word_idx, 0.U(log2Up(coreDataBits).W)) val loadgen = new LoadGen(rpq.io.deq.bits.uop.mem_size, rpq.io.deq.bits.uop.mem_signed, Cat(req_tag, req_idx, rpq.io.deq.bits.addr(blockOffBits-1,0)), data_word, false.B, wordBytes) rpq.io.deq.ready := io.resp.ready && io.lb_read.ready && drain_load io.lb_read.valid := rpq.io.deq.valid && drain_load io.lb_read.bits.id := io.id io.lb_read.bits.offset := rpq.io.deq.bits.addr >> rowOffBits io.resp.valid := rpq.io.deq.valid && io.lb_read.fire && drain_load io.resp.bits.uop := rpq.io.deq.bits.uop io.resp.bits.data := loadgen.data io.resp.bits.is_hella := rpq.io.deq.bits.is_hella when (rpq.io.deq.fire) { commit_line := true.B } .elsewhen (rpq.io.empty && !commit_line) { when (!rpq.io.enq.fire) { state := s_mem_finish_1 finish_to_prefetch := enablePrefetching.B } } .elsewhen (rpq.io.empty \|\| (rpq.io.deq.valid && !drain_load)) { // io.commit_val is for the prefetcher. it tells the prefetcher that this line was correctly acquired // The prefetcher should consider fetching the next line io.commit_val := true.B state := s_meta_read } } .elsewhen (state === s_meta_read) { io.meta_read.valid := !io.prober_state.valid \|\| !grantack.valid \|\| (io.prober_state.bits(untagBits-1,blockOffBits) =/= req_idx) io.meta_read.bits.idx := req_idx io.meta_read.bits.tag := req_tag io.meta_read.bits.way_en := req.way_en when (io.meta_read.fire) { state := s_meta_resp_1 } } .elsewhen (state === s_meta_resp_1) { state := s_meta_resp_2 } .elsewhen (state === s_meta_resp_2) { val needs_wb = io.meta_resp.bits.coh.onCacheControl(M_FLUSH)._1 state := Mux(!io.meta_resp.valid, s_meta_read, // Prober could have nack'd this read Mux(needs_wb, s_meta_clear, s_commit_line)) } .elsewhen (state === s_meta_clear) { io.meta_write.valid := true.B io.meta_write.bits.idx := req_idx io.meta_write.bits.data.coh := coh_on_clear io.meta_write.bits.data.tag := req_tag io.meta_write.bits.way_en := req.way_en when (io.meta_write.fire) { state := s_wb_req } } .elsewhen (state === s_wb_req) { io.wb_req.valid := true.B io.wb_req.bits.tag := req.old_meta.tag io.wb_req.bits.idx := req_idx io.wb_req.bits.param := shrink_param io.wb_req.bits.way_en := req.way_en io.wb_req.bits.source := io.id io.wb_req.bits.voluntary := true.B when (io.wb_req.fire) { state := s_wb_resp } } .elsewhen (state === s_wb_resp) { when (io.wb_resp) { state := s_commit_line } } .elsewhen (state === s_commit_line) { io.lb_read.valid := true.B io.lb_read.bits.id := io.id io.lb_read.bits.offset := refill_ctr io.refill.valid := io.lb_read.fire io.refill.bits.addr := req_block_addr \| (refill_ctr << rowOffBits) io.refill.bits.way_en := req.way_en io.refill.bits.wmask := ~(0.U(rowWords.W)) io.refill.bits.data := io.lb_resp when (io.refill.fire) { refill_ctr := refill_ctr + 1.U when (refill_ctr === (cacheDataBeats - 1).U) { state := s_drain_rpq } } } .elsewhen (state === s_drain_rpq) { io.replay <> rpq.io.deq io.replay.bits.way_en := req.way_en io.replay.bits.addr := Cat(req_tag, req_idx, rpq.io.deq.bits.addr(blockOffBits-1,0)) when (io.replay.fire && isWrite(rpq.io.deq.bits.uop.mem_cmd)) { // Set dirty bit val (is_hit, _, coh_on_hit) = new_coh.onAccess(rpq.io.deq.bits.uop.mem_cmd) assert(is_hit, "We still don't have permissions for this store") new_coh := coh_on_hit } when (rpq.io.empty && !rpq.io.enq.valid) { state := s_meta_write_req } } .elsewhen (state === s_meta_write_req) { io.meta_write.valid := true.B io.meta_write.bits.idx := req_idx io.meta_write.bits.data.coh := new_coh io.meta_write.bits.data.tag := req_tag io.meta_write.bits.way_en := req.way_en when (io.meta_write.fire) { state := s_mem_finish_1 finish_to_prefetch := false.B } } .elsewhen (state === s_mem_finish_1) { io.mem_finish.valid := grantack.valid io.mem_finish.bits := grantack.bits when (io.mem_finish.fire \|\| !grantack.valid) { grantack.valid := false.B state := s_mem_finish_2 } } .elsewhen (state === s_mem_finish_2) { state := Mux(finish_to_prefetch, s_prefetch, s_invalid) } .elsewhen (state === s_prefetch) { io.req_pri_rdy := true.B when ((io.req_sec_val && !io.req_sec_rdy) \|\| io.clear_prefetch) { state := s_invalid } .elsewhen (io.req_sec_val && io.req_sec_rdy) { val (is_hit, _, coh_on_hit) = new_coh.onAccess(io.req.uop.mem_cmd) when (is_hit) { // Proceed with refill new_coh := coh_on_hit state := s_meta_read } .otherwise { // Reacquire this line new_coh := ClientMetadata.onReset state := s_refill_req } } .elsewhen (io.req_pri_val && io.req_pri_rdy) { grant_had_data := false.B state := handle_pri_req(state) } } } class BoomIOMSHR(id: Int)(implicit edge: TLEdgeOut, p: Parameters) extends BoomModule()(p) with HasL1HellaCacheParameters { val io = IO(new Bundle { val req = Flipped(Decoupled(new BoomDCacheReq)) val resp = Decoupled(new BoomDCacheResp) val mem_access = Decoupled(new TLBundleA(edge.bundle)) val mem_ack = Flipped(Valid(new TLBundleD(edge.bundle))) // We don't need brupdate in here because uncacheable operations are guaranteed non-speculative }) def beatOffset(addr: UInt) = addr.extract(beatOffBits-1, wordOffBits) def wordFromBeat(addr: UInt, dat: UInt) = { val shift = Cat(beatOffset(addr), 0.U((wordOffBits+log2Ceil(wordBytes)).W)) (dat >> shift)(wordBits-1, 0) } val req = Reg(new BoomDCacheReq) val grant_word = Reg(UInt(wordBits.W)) val s_idle :: s_mem_access :: s_mem_ack :: s_resp :: Nil = Enum(4) val state = RegInit(s_idle) io.req.ready := state === s_idle val loadgen = new LoadGen(req.uop.mem_size, req.uop.mem_signed, req.addr, grant_word, false.B, wordBytes) val a_source = id.U val a_address = req.addr val a_size = req.uop.mem_size val a_data = Fill(beatWords, req.data) val get = edge.Get(a_source, a_address, a_size)._2 val put = edge.Put(a_source, a_address, a_size, a_data)._2 val atomics = if (edge.manager.anySupportLogical) { MuxLookup(req.uop.mem_cmd, (0.U).asTypeOf(new TLBundleA(edge.bundle)))(Array( M_XA_SWAP -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.SWAP)._2, M_XA_XOR -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.XOR) ._2, M_XA_OR -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.OR) ._2, M_XA_AND -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.AND) ._2, M_XA_ADD -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.ADD)._2, M_XA_MIN -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.MIN)._2, M_XA_MAX -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.MAX)._2, M_XA_MINU -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.MINU)._2, M_XA_MAXU -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.MAXU)._2)) } else { // If no managers support atomics, assert fail if processor asks for them assert(state === s_idle \|\| !isAMO(req.uop.mem_cmd)) (0.U).asTypeOf(new TLBundleA(edge.bundle)) } assert(state === s_idle \|\| req.uop.mem_cmd =/= M_XSC) io.mem_access.valid := state === s_mem_access io.mem_access.bits := Mux(isAMO(req.uop.mem_cmd), atomics, Mux(isRead(req.uop.mem_cmd), get, put)) val send_resp = isRead(req.uop.mem_cmd) io.resp.valid := (state === s_resp) && send_resp io.resp.bits.is_hella := req.is_hella io.resp.bits.uop := req.uop io.resp.bits.data := loadgen.data when (io.req.fire) { req := io.req.bits state := s_mem_access } when (io.mem_access.fire) { state := s_mem_ack } when (state === s_mem_ack && io.mem_ack.valid) { state := s_resp when (isRead(req.uop.mem_cmd)) { grant_word := wordFromBeat(req.addr, io.mem_ack.bits.data) } } when (state === s_resp) { when (!send_resp \|\| io.resp.fire) { state := s_idle } } } class LineBufferReadReq(implicit p: Parameters) extends BoomBundle()(p) with HasL1HellaCacheParameters { val id = UInt(log2Ceil(nLBEntries).W) val offset = UInt(log2Ceil(cacheDataBeats).W) def lb_addr = Cat(id, offset) } class LineBufferWriteReq(implicit p: Parameters) extends LineBufferReadReq()(p) { val data = UInt(encRowBits.W) } class LineBufferMetaWriteReq(implicit p: Parameters) extends BoomBundle()(p) { val id = UInt(log2Ceil(nLBEntries).W) val coh = new ClientMetadata val addr = UInt(coreMaxAddrBits.W) } class LineBufferMeta(implicit p: Parameters) extends BoomBundle()(p) with HasL1HellaCacheParameters { val coh = new ClientMetadata val addr = UInt(coreMaxAddrBits.W) } class BoomMSHRFile(implicit edge: TLEdgeOut, p: Parameters) extends BoomModule()(p) with HasL1HellaCacheParameters { val io = IO(new Bundle { val req = Flipped(Vec(memWidth, Decoupled(new BoomDCacheReqInternal))) // Req from s2 of DCache pipe val req_is_probe = Input(Vec(memWidth, Bool())) val resp = Decoupled(new BoomDCacheResp) val secondary_miss = Output(Vec(memWidth, Bool())) val block_hit = Output(Vec(memWidth, Bool())) val brupdate = Input(new BrUpdateInfo) val exception = Input(Bool()) val rob_pnr_idx = Input(UInt(robAddrSz.W)) val rob_head_idx = Input(UInt(robAddrSz.W)) val mem_acquire = Decoupled(new TLBundleA(edge.bundle)) val mem_grant = Flipped(Decoupled(new TLBundleD(edge.bundle))) val mem_finish = Decoupled(new TLBundleE(edge.bundle)) val refill = Decoupled(new L1DataWriteReq) val meta_write = Decoupled(new L1MetaWriteReq) val meta_read = Decoupled(new L1MetaReadReq) val meta_resp = Input(Valid(new L1Metadata)) val replay = Decoupled(new BoomDCacheReqInternal) val prefetch = Decoupled(new BoomDCacheReq) val wb_req = Decoupled(new WritebackReq(edge.bundle)) val prober_state = Input(Valid(UInt(coreMaxAddrBits.W))) val clear_all = Input(Bool()) // Clears all uncommitted MSHRs to prepare for fence val wb_resp = Input(Bool()) val fence_rdy = Output(Bool()) val probe_rdy = Output(Bool()) }) val req_idx = OHToUInt(io.req.map(_.valid)) val req = io.req(req_idx) val req_is_probe = io.req_is_probe(0) for (w <- 0 until memWidth) io.req(w).ready := false.B val prefetcher: DataPrefetcher = if (enablePrefetching) Module(new NLPrefetcher) else Module(new NullPrefetcher) io.prefetch <> prefetcher.io.prefetch val cacheable = edge.manager.supportsAcquireBFast(req.bits.addr, lgCacheBlockBytes.U) // -------------------- // The MSHR SDQ val sdq_val = RegInit(0.U(cfg.nSDQ.W)) val sdq_alloc_id = PriorityEncoder(~sdq_val(cfg.nSDQ-1,0)) val sdq_rdy = !sdq_val.andR val sdq_enq = req.fire && cacheable && isWrite(req.bits.uop.mem_cmd) val sdq = Mem(cfg.nSDQ, UInt(coreDataBits.W)) when (sdq_enq) { sdq(sdq_alloc_id) := req.bits.data } // -------------------- // The LineBuffer Data // Holds refilling lines, prefetched lines val lb = Mem(nLBEntries cacheDataBeats, UInt(encRowBits.W)) val lb_read_arb = Module(new Arbiter(new LineBufferReadReq, cfg.nMSHRs)) val lb_write_arb = Module(new Arbiter(new LineBufferWriteReq, cfg.nMSHRs)) lb_read_arb.io.out.ready := false.B lb_write_arb.io.out.ready := true.B val lb_read_data = WireInit(0.U(encRowBits.W)) when (lb_write_arb.io.out.fire) { lb.write(lb_write_arb.io.out.bits.lb_addr, lb_write_arb.io.out.bits.data) } .otherwise { lb_read_arb.io.out.ready := true.B when (lb_read_arb.io.out.fire) { lb_read_data := lb.read(lb_read_arb.io.out.bits.lb_addr) } } def widthMap[T <: Data](f: Int => T) = VecInit((0 until memWidth).map(f)) val idx_matches = Wire(Vec(memWidth, Vec(cfg.nMSHRs, Bool()))) val tag_matches = Wire(Vec(memWidth, Vec(cfg.nMSHRs, Bool()))) val way_matches = Wire(Vec(memWidth, Vec(cfg.nMSHRs, Bool()))) val tag_match = widthMap(w => Mux1H(idx_matches(w), tag_matches(w))) val idx_match = widthMap(w => idx_matches(w).reduce(_\|\|_)) val way_match = widthMap(w => Mux1H(idx_matches(w), way_matches(w))) val wb_tag_list = Wire(Vec(cfg.nMSHRs, UInt(tagBits.W))) val meta_write_arb = Module(new Arbiter(new L1MetaWriteReq , cfg.nMSHRs)) val meta_read_arb = Module(new Arbiter(new L1MetaReadReq , cfg.nMSHRs)) val wb_req_arb = Module(new Arbiter(new WritebackReq(edge.bundle), cfg.nMSHRs)) val replay_arb = Module(new Arbiter(new BoomDCacheReqInternal , cfg.nMSHRs)) val resp_arb = Module(new Arbiter(new BoomDCacheResp , cfg.nMSHRs + nIOMSHRs)) val refill_arb = Module(new Arbiter(new L1DataWriteReq , cfg.nMSHRs)) val commit_vals = Wire(Vec(cfg.nMSHRs, Bool())) val commit_addrs = Wire(Vec(cfg.nMSHRs, UInt(coreMaxAddrBits.W))) val commit_cohs = Wire(Vec(cfg.nMSHRs, new ClientMetadata)) var sec_rdy = false.B io.fence_rdy := true.B io.probe_rdy := true.B io.mem_grant.ready := false.B val mshr_alloc_idx = Wire(UInt()) val pri_rdy = WireInit(false.B) val pri_val = req.valid && sdq_rdy && cacheable && !idx_match(req_idx) val mshrs = (0 until cfg.nMSHRs) map { i => val mshr = Module(new BoomMSHR) mshr.io.id := i.U(log2Ceil(cfg.nMSHRs).W) for (w <- 0 until memWidth) { idx_matches(w)(i) := mshr.io.idx.valid && mshr.io.idx.bits === io.req(w).bits.addr(untagBits-1,blockOffBits) tag_matches(w)(i) := mshr.io.tag.valid && mshr.io.tag.bits === io.req(w).bits.addr >> untagBits way_matches(w)(i) := mshr.io.way.valid && mshr.io.way.bits === io.req(w).bits.way_en } wb_tag_list(i) := mshr.io.wb_req.bits.tag mshr.io.req_pri_val := (i.U === mshr_alloc_idx) && pri_val when (i.U === mshr_alloc_idx) { pri_rdy := mshr.io.req_pri_rdy } mshr.io.req_sec_val := req.valid && sdq_rdy && tag_match(req_idx) && idx_matches(req_idx)(i) && cacheable mshr.io.req := req.bits mshr.io.req_is_probe := req_is_probe mshr.io.req.sdq_id := sdq_alloc_id // Clear because of a FENCE, a request to the same idx as a prefetched line, // a probe to that prefetched line, all mshrs are in use mshr.io.clear_prefetch := ((io.clear_all && !req.valid)\|\| (req.valid && idx_matches(req_idx)(i) && cacheable && !tag_match(req_idx)) \|\| (req_is_probe && idx_matches(req_idx)(i))) mshr.io.brupdate := io.brupdate mshr.io.exception := io.exception mshr.io.rob_pnr_idx := io.rob_pnr_idx mshr.io.rob_head_idx := io.rob_head_idx mshr.io.prober_state := io.prober_state mshr.io.wb_resp := io.wb_resp meta_write_arb.io.in(i) <> mshr.io.meta_write meta_read_arb.io.in(i) <> mshr.io.meta_read mshr.io.meta_resp := io.meta_resp wb_req_arb.io.in(i) <> mshr.io.wb_req replay_arb.io.in(i) <> mshr.io.replay refill_arb.io.in(i) <> mshr.io.refill lb_read_arb.io.in(i) <> mshr.io.lb_read mshr.io.lb_resp := lb_read_data lb_write_arb.io.in(i) <> mshr.io.lb_write commit_vals(i) := mshr.io.commit_val commit_addrs(i) := mshr.io.commit_addr commit_cohs(i) := mshr.io.commit_coh mshr.io.mem_grant.valid := false.B mshr.io.mem_grant.bits := DontCare when (io.mem_grant.bits.source === i.U) { mshr.io.mem_grant <> io.mem_grant } sec_rdy = sec_rdy \|\| (mshr.io.req_sec_rdy && mshr.io.req_sec_val) resp_arb.io.in(i) <> mshr.io.resp when (!mshr.io.req_pri_rdy) { io.fence_rdy := false.B } for (w <- 0 until memWidth) { when (!mshr.io.probe_rdy && idx_matches(w)(i) && io.req_is_probe(w)) { io.probe_rdy := false.B } } mshr } // Try to round-robin the MSHRs val mshr_head = RegInit(0.U(log2Ceil(cfg.nMSHRs).W)) mshr_alloc_idx := RegNext(AgePriorityEncoder(mshrs.map(m=>m.io.req_pri_rdy), mshr_head)) when (pri_rdy && pri_val) { mshr_head := WrapInc(mshr_head, cfg.nMSHRs) } io.meta_write <> meta_write_arb.io.out io.meta_read <> meta_read_arb.io.out io.wb_req <> wb_req_arb.io.out val mmio_alloc_arb = Module(new Arbiter(Bool(), nIOMSHRs)) var mmio_rdy = false.B val mmios = (0 until nIOMSHRs) map { i => val id = cfg.nMSHRs + 1 + i // +1 for wb unit val mshr = Module(new BoomIOMSHR(id)) mmio_alloc_arb.io.in(i).valid := mshr.io.req.ready mmio_alloc_arb.io.in(i).bits := DontCare mshr.io.req.valid := mmio_alloc_arb.io.in(i).ready mshr.io.req.bits := req.bits mmio_rdy = mmio_rdy \|\| mshr.io.req.ready mshr.io.mem_ack.bits := io.mem_grant.bits mshr.io.mem_ack.valid := io.mem_grant.valid && io.mem_grant.bits.source === id.U when (io.mem_grant.bits.source === id.U) { io.mem_grant.ready := true.B } resp_arb.io.in(cfg.nMSHRs + i) <> mshr.io.resp when (!mshr.io.req.ready) { io.fence_rdy := false.B } mshr } mmio_alloc_arb.io.out.ready := req.valid && !cacheable TLArbiter.lowestFromSeq(edge, io.mem_acquire, mshrs.map(_.io.mem_acquire) ++ mmios.map(_.io.mem_access)) TLArbiter.lowestFromSeq(edge, io.mem_finish, mshrs.map(_.io.mem_finish)) val respq = Module(new BranchKillableQueue(new BoomDCacheResp, 4, u => u.uses_ldq, flow = false)) respq.io.brupdate := io.brupdate respq.io.flush := io.exception respq.io.enq <> resp_arb.io.out io.resp <> respq.io.deq for (w <- 0 until memWidth) { io.req(w).ready := (w.U === req_idx) && Mux(!cacheable, mmio_rdy, sdq_rdy && Mux(idx_match(w), tag_match(w) && sec_rdy, pri_rdy)) io.secondary_miss(w) := idx_match(w) && way_match(w) && !tag_match(w) io.block_hit(w) := idx_match(w) && tag_match(w) } io.refill <> refill_arb.io.out val free_sdq = io.replay.fire && isWrite(io.replay.bits.uop.mem_cmd) io.replay <> replay_arb.io.out io.replay.bits.data := sdq(replay_arb.io.out.bits.sdq_id) when (io.replay.valid \|\| sdq_enq) { sdq_val := sdq_val & ~(UIntToOH(replay_arb.io.out.bits.sdq_id) & Fill(cfg.nSDQ, free_sdq)) \| PriorityEncoderOH(~sdq_val(cfg.nSDQ-1,0)) & Fill(cfg.nSDQ, sdq_enq) } prefetcher.io.mshr_avail := RegNext(pri_rdy) prefetcher.io.req_val := RegNext(commit_vals.reduce(_\|\|_)) prefetcher.io.req_addr := RegNext(Mux1H(commit_vals, commit_addrs)) prefetcher.io.req_coh := RegNext(Mux1H(commit_vals, commit_cohs)) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } } File AMOALU.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters class StoreGen(typ: UInt, addr: UInt, dat: UInt, maxSize: Int) { val size = Wire(UInt(log2Up(log2Up(maxSize)+1).W)) size := typ val dat_padded = dat.pad(maxSize8) def misaligned: Bool = (addr & ((1.U << size) - 1.U)(log2Up(maxSize)-1,0)).orR def mask = { var res = 1.U for (i <- 0 until log2Up(maxSize)) { val upper = Mux(addr(i), res, 0.U) \| Mux(size >= (i+1).U, ((BigInt(1) << (1 << i))-1).U, 0.U) val lower = Mux(addr(i), 0.U, res) res = Cat(upper, lower) } res } protected def genData(i: Int): UInt = if (i >= log2Up(maxSize)) dat_padded else Mux(size === i.U, Fill(1 << (log2Up(maxSize)-i), dat_padded((8 << i)-1,0)), genData(i+1)) def data = genData(0) def wordData = genData(2) } class LoadGen(typ: UInt, signed: Bool, addr: UInt, dat: UInt, zero: Bool, maxSize: Int) { private val size = new StoreGen(typ, addr, dat, maxSize).size private def genData(logMinSize: Int): UInt = { var res = dat for (i <- log2Up(maxSize)-1 to logMinSize by -1) { val pos = 8 << i val shifted = Mux(addr(i), res(2pos-1,pos), res(pos-1,0)) val doZero = (i == 0).B && zero val zeroed = Mux(doZero, 0.U, shifted) res = Cat(Mux(size === i.U \|\| doZero, Fill(8maxSize-pos, signed && zeroed(pos-1)), res(8*maxSize-1,pos)), zeroed) } res } def wordData = genData(2) def data = genData(0) } class AMOALU(operandBits: Int)(implicit p: Parameters) extends Module { val minXLen = 32 val widths = (0 to log2Ceil(operandBits / minXLen)).map(minXLen << _) val io = IO(new Bundle { val mask = Input(UInt((operandBits / 8).W)) val cmd = Input(UInt(M_SZ.W)) val lhs = Input(UInt(operandBits.W)) val rhs = Input(UInt(operandBits.W)) val out = Output(UInt(operandBits.W)) val out_unmasked = Output(UInt(operandBits.W)) }) val max = io.cmd === M_XA_MAX \|\| io.cmd === M_XA_MAXU val min = io.cmd === M_XA_MIN \|\| io.cmd === M_XA_MINU val add = io.cmd === M_XA_ADD val logic_and = io.cmd === M_XA_OR \|\| io.cmd === M_XA_AND val logic_xor = io.cmd === M_XA_XOR \|\| io.cmd === M_XA_OR val adder_out = { // partition the carry chain to support sub-xLen addition val mask = ~(0.U(operandBits.W) +: widths.init.map(w => !io.mask(w/8-1) << (w-1))).reduce(_\|_) (io.lhs & mask) + (io.rhs & mask) } val less = { // break up the comparator so the lower parts will be CSE'd def isLessUnsigned(x: UInt, y: UInt, n: Int): Bool = { if (n == minXLen) x(n-1, 0) < y(n-1, 0) else x(n-1, n/2) < y(n-1, n/2) \|\| x(n-1, n/2) === y(n-1, n/2) && isLessUnsigned(x, y, n/2) } def isLess(x: UInt, y: UInt, n: Int): Bool = { val signed = { val mask = M_XA_MIN ^ M_XA_MINU (io.cmd & mask) === (M_XA_MIN & mask) } Mux(x(n-1) === y(n-1), isLessUnsigned(x, y, n), Mux(signed, x(n-1), y(n-1))) } PriorityMux(widths.reverse.map(w => (io.mask(w/8/2), isLess(io.lhs, io.rhs, w)))) } val minmax = Mux(Mux(less, min, max), io.lhs, io.rhs) val logic = Mux(logic_and, io.lhs & io.rhs, 0.U) \| Mux(logic_xor, io.lhs ^ io.rhs, 0.U) val out = Mux(add, adder_out, Mux(logic_and \|\| logic_xor, logic, minmax)) val wmask = FillInterleaved(8, io.mask) io.out := wmask & out \| ~wmask & io.lhs io.out_unmasked := out }	module BoomMSHR_5( // @[mshrs.scala:36:7] input clock, // @[mshrs.scala:36:7] input reset, // @[mshrs.scala:36:7] input io_req_pri_val, // @[mshrs.scala:39:14] output io_req_pri_rdy, // @[mshrs.scala:39:14] input io_req_sec_val, // @[mshrs.scala:39:14] output io_req_sec_rdy, // @[mshrs.scala:39:14] input io_clear_prefetch, // @[mshrs.scala:39:14] input [15:0] io_brupdate_b1_resolve_mask, // @[mshrs.scala:39:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[mshrs.scala:39:14] input [6:0] io_brupdate_b2_uop_uopc, // @[mshrs.scala:39:14] input [31:0] io_brupdate_b2_uop_inst, // @[mshrs.scala:39:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_is_rvc, // @[mshrs.scala:39:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[mshrs.scala:39:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[mshrs.scala:39:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[mshrs.scala:39:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[mshrs.scala:39:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[mshrs.scala:39:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[mshrs.scala:39:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[mshrs.scala:39:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[mshrs.scala:39:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_ctrl_is_load, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_ctrl_is_std, // @[mshrs.scala:39:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_is_br, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_is_jalr, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_is_jal, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_is_sfb, // @[mshrs.scala:39:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[mshrs.scala:39:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[mshrs.scala:39:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_edge_inst, // @[mshrs.scala:39:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_taken, // @[mshrs.scala:39:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[mshrs.scala:39:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[mshrs.scala:39:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[mshrs.scala:39:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[mshrs.scala:39:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[mshrs.scala:39:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[mshrs.scala:39:14] input [6:0] io_brupdate_b2_uop_pdst, // @[mshrs.scala:39:14] input [6:0] io_brupdate_b2_uop_prs1, // @[mshrs.scala:39:14] input [6:0] io_brupdate_b2_uop_prs2, // @[mshrs.scala:39:14] input [6:0] io_brupdate_b2_uop_prs3, // @[mshrs.scala:39:14] input [4:0] io_brupdate_b2_uop_ppred, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_prs1_busy, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_prs2_busy, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_prs3_busy, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_ppred_busy, // @[mshrs.scala:39:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_exception, // @[mshrs.scala:39:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_bypassable, // @[mshrs.scala:39:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[mshrs.scala:39:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_mem_signed, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_is_fence, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_is_fencei, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_is_amo, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_uses_ldq, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_uses_stq, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_is_unique, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_flush_on_commit, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[mshrs.scala:39:14] input [5:0] io_brupdate_b2_uop_ldst, // @[mshrs.scala:39:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[mshrs.scala:39:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[mshrs.scala:39:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_ldst_val, // @[mshrs.scala:39:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[mshrs.scala:39:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[mshrs.scala:39:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_frs3_en, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_fp_val, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_fp_single, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_bp_debug_if, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[mshrs.scala:39:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[mshrs.scala:39:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[mshrs.scala:39:14] input io_brupdate_b2_valid, // @[mshrs.scala:39:14] input io_brupdate_b2_mispredict, // @[mshrs.scala:39:14] input io_brupdate_b2_taken, // @[mshrs.scala:39:14] input [2:0] io_brupdate_b2_cfi_type, // @[mshrs.scala:39:14] input [1:0] io_brupdate_b2_pc_sel, // @[mshrs.scala:39:14] input [39:0] io_brupdate_b2_jalr_target, // @[mshrs.scala:39:14] input [20:0] io_brupdate_b2_target_offset, // @[mshrs.scala:39:14] input io_exception, // @[mshrs.scala:39:14] input [6:0] io_rob_pnr_idx, // @[mshrs.scala:39:14] input [6:0] io_rob_head_idx, // @[mshrs.scala:39:14] input [6:0] io_req_uop_uopc, // @[mshrs.scala:39:14] input [31:0] io_req_uop_inst, // @[mshrs.scala:39:14] input [31:0] io_req_uop_debug_inst, // @[mshrs.scala:39:14] input io_req_uop_is_rvc, // @[mshrs.scala:39:14] input [39:0] io_req_uop_debug_pc, // @[mshrs.scala:39:14] input [2:0] io_req_uop_iq_type, // @[mshrs.scala:39:14] input [9:0] io_req_uop_fu_code, // @[mshrs.scala:39:14] input [3:0] io_req_uop_ctrl_br_type, // @[mshrs.scala:39:14] input [1:0] io_req_uop_ctrl_op1_sel, // @[mshrs.scala:39:14] input [2:0] io_req_uop_ctrl_op2_sel, // @[mshrs.scala:39:14] input [2:0] io_req_uop_ctrl_imm_sel, // @[mshrs.scala:39:14] input [4:0] io_req_uop_ctrl_op_fcn, // @[mshrs.scala:39:14] input io_req_uop_ctrl_fcn_dw, // @[mshrs.scala:39:14] input [2:0] io_req_uop_ctrl_csr_cmd, // @[mshrs.scala:39:14] input io_req_uop_ctrl_is_load, // @[mshrs.scala:39:14] input io_req_uop_ctrl_is_sta, // @[mshrs.scala:39:14] input io_req_uop_ctrl_is_std, // @[mshrs.scala:39:14] input [1:0] io_req_uop_iw_state, // @[mshrs.scala:39:14] input io_req_uop_iw_p1_poisoned, // @[mshrs.scala:39:14] input io_req_uop_iw_p2_poisoned, // @[mshrs.scala:39:14] input io_req_uop_is_br, // @[mshrs.scala:39:14] input io_req_uop_is_jalr, // @[mshrs.scala:39:14] input io_req_uop_is_jal, // @[mshrs.scala:39:14] input io_req_uop_is_sfb, // @[mshrs.scala:39:14] input [15:0] io_req_uop_br_mask, // @[mshrs.scala:39:14] input [3:0] io_req_uop_br_tag, // @[mshrs.scala:39:14] input [4:0] io_req_uop_ftq_idx, // @[mshrs.scala:39:14] input io_req_uop_edge_inst, // @[mshrs.scala:39:14] input [5:0] io_req_uop_pc_lob, // @[mshrs.scala:39:14] input io_req_uop_taken, // @[mshrs.scala:39:14] input [19:0] io_req_uop_imm_packed, // @[mshrs.scala:39:14] input [11:0] io_req_uop_csr_addr, // @[mshrs.scala:39:14] input [6:0] io_req_uop_rob_idx, // @[mshrs.scala:39:14] input [4:0] io_req_uop_ldq_idx, // @[mshrs.scala:39:14] input [4:0] io_req_uop_stq_idx, // @[mshrs.scala:39:14] input [1:0] io_req_uop_rxq_idx, // @[mshrs.scala:39:14] input [6:0] io_req_uop_pdst, // @[mshrs.scala:39:14] input [6:0] io_req_uop_prs1, // @[mshrs.scala:39:14] input [6:0] io_req_uop_prs2, // @[mshrs.scala:39:14] input [6:0] io_req_uop_prs3, // @[mshrs.scala:39:14] input [4:0] io_req_uop_ppred, // @[mshrs.scala:39:14] input io_req_uop_prs1_busy, // @[mshrs.scala:39:14] input io_req_uop_prs2_busy, // @[mshrs.scala:39:14] input io_req_uop_prs3_busy, // @[mshrs.scala:39:14] input io_req_uop_ppred_busy, // @[mshrs.scala:39:14] input [6:0] io_req_uop_stale_pdst, // @[mshrs.scala:39:14] input io_req_uop_exception, // @[mshrs.scala:39:14] input [63:0] io_req_uop_exc_cause, // @[mshrs.scala:39:14] input io_req_uop_bypassable, // @[mshrs.scala:39:14] input [4:0] io_req_uop_mem_cmd, // @[mshrs.scala:39:14] input [1:0] io_req_uop_mem_size, // @[mshrs.scala:39:14] input io_req_uop_mem_signed, // @[mshrs.scala:39:14] input io_req_uop_is_fence, // @[mshrs.scala:39:14] input io_req_uop_is_fencei, // @[mshrs.scala:39:14] input io_req_uop_is_amo, // @[mshrs.scala:39:14] input io_req_uop_uses_ldq, // @[mshrs.scala:39:14] input io_req_uop_uses_stq, // @[mshrs.scala:39:14] input io_req_uop_is_sys_pc2epc, // @[mshrs.scala:39:14] input io_req_uop_is_unique, // @[mshrs.scala:39:14] input io_req_uop_flush_on_commit, // @[mshrs.scala:39:14] input io_req_uop_ldst_is_rs1, // @[mshrs.scala:39:14] input [5:0] io_req_uop_ldst, // @[mshrs.scala:39:14] input [5:0] io_req_uop_lrs1, // @[mshrs.scala:39:14] input [5:0] io_req_uop_lrs2, // @[mshrs.scala:39:14] input [5:0] io_req_uop_lrs3, // @[mshrs.scala:39:14] input io_req_uop_ldst_val, // @[mshrs.scala:39:14] input [1:0] io_req_uop_dst_rtype, // @[mshrs.scala:39:14] input [1:0] io_req_uop_lrs1_rtype, // @[mshrs.scala:39:14] input [1:0] io_req_uop_lrs2_rtype, // @[mshrs.scala:39:14] input io_req_uop_frs3_en, // @[mshrs.scala:39:14] input io_req_uop_fp_val, // @[mshrs.scala:39:14] input io_req_uop_fp_single, // @[mshrs.scala:39:14] input io_req_uop_xcpt_pf_if, // @[mshrs.scala:39:14] input io_req_uop_xcpt_ae_if, // @[mshrs.scala:39:14] input io_req_uop_xcpt_ma_if, // @[mshrs.scala:39:14] input io_req_uop_bp_debug_if, // @[mshrs.scala:39:14] input io_req_uop_bp_xcpt_if, // @[mshrs.scala:39:14] input [1:0] io_req_uop_debug_fsrc, // @[mshrs.scala:39:14] input [1:0] io_req_uop_debug_tsrc, // @[mshrs.scala:39:14] input [39:0] io_req_addr, // @[mshrs.scala:39:14] input [63:0] io_req_data, // @[mshrs.scala:39:14] input io_req_is_hella, // @[mshrs.scala:39:14] input io_req_tag_match, // @[mshrs.scala:39:14] input [1:0] io_req_old_meta_coh_state, // @[mshrs.scala:39:14] input [19:0] io_req_old_meta_tag, // @[mshrs.scala:39:14] input [7:0] io_req_way_en, // @[mshrs.scala:39:14] input [4:0] io_req_sdq_id, // @[mshrs.scala:39:14] input io_req_is_probe, // @[mshrs.scala:39:14] output io_idx_valid, // @[mshrs.scala:39:14] output [5:0] io_idx_bits, // @[mshrs.scala:39:14] output io_way_valid, // @[mshrs.scala:39:14] output [7:0] io_way_bits, // @[mshrs.scala:39:14] output io_tag_valid, // @[mshrs.scala:39:14] output [27:0] io_tag_bits, // @[mshrs.scala:39:14] input io_mem_acquire_ready, // @[mshrs.scala:39:14] output io_mem_acquire_valid, // @[mshrs.scala:39:14] output [2:0] io_mem_acquire_bits_param, // @[mshrs.scala:39:14] output [31:0] io_mem_acquire_bits_address, // @[mshrs.scala:39:14] output io_mem_grant_ready, // @[mshrs.scala:39:14] input io_mem_grant_valid, // @[mshrs.scala:39:14] input [2:0] io_mem_grant_bits_opcode, // @[mshrs.scala:39:14] input [1:0] io_mem_grant_bits_param, // @[mshrs.scala:39:14] input [3:0] io_mem_grant_bits_size, // @[mshrs.scala:39:14] input [2:0] io_mem_grant_bits_source, // @[mshrs.scala:39:14] input [3:0] io_mem_grant_bits_sink, // @[mshrs.scala:39:14] input io_mem_grant_bits_denied, // @[mshrs.scala:39:14] input [127:0] io_mem_grant_bits_data, // @[mshrs.scala:39:14] input io_mem_grant_bits_corrupt, // @[mshrs.scala:39:14] input io_mem_finish_ready, // @[mshrs.scala:39:14] output io_mem_finish_valid, // @[mshrs.scala:39:14] output [3:0] io_mem_finish_bits_sink, // @[mshrs.scala:39:14] input io_prober_state_valid, // @[mshrs.scala:39:14] input [39:0] io_prober_state_bits, // @[mshrs.scala:39:14] input io_refill_ready, // @[mshrs.scala:39:14] output io_refill_valid, // @[mshrs.scala:39:14] output [7:0] io_refill_bits_way_en, // @[mshrs.scala:39:14] output [11:0] io_refill_bits_addr, // @[mshrs.scala:39:14] output [127:0] io_refill_bits_data, // @[mshrs.scala:39:14] input io_meta_write_ready, // @[mshrs.scala:39:14] output io_meta_write_valid, // @[mshrs.scala:39:14] output [5:0] io_meta_write_bits_idx, // @[mshrs.scala:39:14] output [7:0] io_meta_write_bits_way_en, // @[mshrs.scala:39:14] output [1:0] io_meta_write_bits_data_coh_state, // @[mshrs.scala:39:14] output [19:0] io_meta_write_bits_data_tag, // @[mshrs.scala:39:14] input io_meta_read_ready, // @[mshrs.scala:39:14] output io_meta_read_valid, // @[mshrs.scala:39:14] output [5:0] io_meta_read_bits_idx, // @[mshrs.scala:39:14] output [7:0] io_meta_read_bits_way_en, // @[mshrs.scala:39:14] output [19:0] io_meta_read_bits_tag, // @[mshrs.scala:39:14] input io_meta_resp_valid, // @[mshrs.scala:39:14] input [1:0] io_meta_resp_bits_coh_state, // @[mshrs.scala:39:14] input [19:0] io_meta_resp_bits_tag, // @[mshrs.scala:39:14] input io_wb_req_ready, // @[mshrs.scala:39:14] output io_wb_req_valid, // @[mshrs.scala:39:14] output [19:0] io_wb_req_bits_tag, // @[mshrs.scala:39:14] output [5:0] io_wb_req_bits_idx, // @[mshrs.scala:39:14] output [2:0] io_wb_req_bits_param, // @[mshrs.scala:39:14] output [7:0] io_wb_req_bits_way_en, // @[mshrs.scala:39:14] output io_commit_val, // @[mshrs.scala:39:14] output [39:0] io_commit_addr, // @[mshrs.scala:39:14] output [1:0] io_commit_coh_state, // @[mshrs.scala:39:14] input io_lb_read_ready, // @[mshrs.scala:39:14] output io_lb_read_valid, // @[mshrs.scala:39:14] output [1:0] io_lb_read_bits_offset, // @[mshrs.scala:39:14] input [127:0] io_lb_resp, // @[mshrs.scala:39:14] input io_lb_write_ready, // @[mshrs.scala:39:14] output io_lb_write_valid, // @[mshrs.scala:39:14] output [1:0] io_lb_write_bits_offset, // @[mshrs.scala:39:14] output [127:0] io_lb_write_bits_data, // @[mshrs.scala:39:14] input io_replay_ready, // @[mshrs.scala:39:14] output io_replay_valid, // @[mshrs.scala:39:14] output [6:0] io_replay_bits_uop_uopc, // @[mshrs.scala:39:14] output [31:0] io_replay_bits_uop_inst, // @[mshrs.scala:39:14] output [31:0] io_replay_bits_uop_debug_inst, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_rvc, // @[mshrs.scala:39:14] output [39:0] io_replay_bits_uop_debug_pc, // @[mshrs.scala:39:14] output [2:0] io_replay_bits_uop_iq_type, // @[mshrs.scala:39:14] output [9:0] io_replay_bits_uop_fu_code, // @[mshrs.scala:39:14] output [3:0] io_replay_bits_uop_ctrl_br_type, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_ctrl_op1_sel, // @[mshrs.scala:39:14] output [2:0] io_replay_bits_uop_ctrl_op2_sel, // @[mshrs.scala:39:14] output [2:0] io_replay_bits_uop_ctrl_imm_sel, // @[mshrs.scala:39:14] output [4:0] io_replay_bits_uop_ctrl_op_fcn, // @[mshrs.scala:39:14] output io_replay_bits_uop_ctrl_fcn_dw, // @[mshrs.scala:39:14] output [2:0] io_replay_bits_uop_ctrl_csr_cmd, // @[mshrs.scala:39:14] output io_replay_bits_uop_ctrl_is_load, // @[mshrs.scala:39:14] output io_replay_bits_uop_ctrl_is_sta, // @[mshrs.scala:39:14] output io_replay_bits_uop_ctrl_is_std, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_iw_state, // @[mshrs.scala:39:14] output io_replay_bits_uop_iw_p1_poisoned, // @[mshrs.scala:39:14] output io_replay_bits_uop_iw_p2_poisoned, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_br, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_jalr, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_jal, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_sfb, // @[mshrs.scala:39:14] output [15:0] io_replay_bits_uop_br_mask, // @[mshrs.scala:39:14] output [3:0] io_replay_bits_uop_br_tag, // @[mshrs.scala:39:14] output [4:0] io_replay_bits_uop_ftq_idx, // @[mshrs.scala:39:14] output io_replay_bits_uop_edge_inst, // @[mshrs.scala:39:14] output [5:0] io_replay_bits_uop_pc_lob, // @[mshrs.scala:39:14] output io_replay_bits_uop_taken, // @[mshrs.scala:39:14] output [19:0] io_replay_bits_uop_imm_packed, // @[mshrs.scala:39:14] output [11:0] io_replay_bits_uop_csr_addr, // @[mshrs.scala:39:14] output [6:0] io_replay_bits_uop_rob_idx, // @[mshrs.scala:39:14] output [4:0] io_replay_bits_uop_ldq_idx, // @[mshrs.scala:39:14] output [4:0] io_replay_bits_uop_stq_idx, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_rxq_idx, // @[mshrs.scala:39:14] output [6:0] io_replay_bits_uop_pdst, // @[mshrs.scala:39:14] output [6:0] io_replay_bits_uop_prs1, // @[mshrs.scala:39:14] output [6:0] io_replay_bits_uop_prs2, // @[mshrs.scala:39:14] output [6:0] io_replay_bits_uop_prs3, // @[mshrs.scala:39:14] output [4:0] io_replay_bits_uop_ppred, // @[mshrs.scala:39:14] output io_replay_bits_uop_prs1_busy, // @[mshrs.scala:39:14] output io_replay_bits_uop_prs2_busy, // @[mshrs.scala:39:14] output io_replay_bits_uop_prs3_busy, // @[mshrs.scala:39:14] output io_replay_bits_uop_ppred_busy, // @[mshrs.scala:39:14] output [6:0] io_replay_bits_uop_stale_pdst, // @[mshrs.scala:39:14] output io_replay_bits_uop_exception, // @[mshrs.scala:39:14] output [63:0] io_replay_bits_uop_exc_cause, // @[mshrs.scala:39:14] output io_replay_bits_uop_bypassable, // @[mshrs.scala:39:14] output [4:0] io_replay_bits_uop_mem_cmd, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_mem_size, // @[mshrs.scala:39:14] output io_replay_bits_uop_mem_signed, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_fence, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_fencei, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_amo, // @[mshrs.scala:39:14] output io_replay_bits_uop_uses_ldq, // @[mshrs.scala:39:14] output io_replay_bits_uop_uses_stq, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_sys_pc2epc, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_unique, // @[mshrs.scala:39:14] output io_replay_bits_uop_flush_on_commit, // @[mshrs.scala:39:14] output io_replay_bits_uop_ldst_is_rs1, // @[mshrs.scala:39:14] output [5:0] io_replay_bits_uop_ldst, // @[mshrs.scala:39:14] output [5:0] io_replay_bits_uop_lrs1, // @[mshrs.scala:39:14] output [5:0] io_replay_bits_uop_lrs2, // @[mshrs.scala:39:14] output [5:0] io_replay_bits_uop_lrs3, // @[mshrs.scala:39:14] output io_replay_bits_uop_ldst_val, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_dst_rtype, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_lrs1_rtype, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_lrs2_rtype, // @[mshrs.scala:39:14] output io_replay_bits_uop_frs3_en, // @[mshrs.scala:39:14] output io_replay_bits_uop_fp_val, // @[mshrs.scala:39:14] output io_replay_bits_uop_fp_single, // @[mshrs.scala:39:14] output io_replay_bits_uop_xcpt_pf_if, // @[mshrs.scala:39:14] output io_replay_bits_uop_xcpt_ae_if, // @[mshrs.scala:39:14] output io_replay_bits_uop_xcpt_ma_if, // @[mshrs.scala:39:14] output io_replay_bits_uop_bp_debug_if, // @[mshrs.scala:39:14] output io_replay_bits_uop_bp_xcpt_if, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_debug_fsrc, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_debug_tsrc, // @[mshrs.scala:39:14] output [39:0] io_replay_bits_addr, // @[mshrs.scala:39:14] output [63:0] io_replay_bits_data, // @[mshrs.scala:39:14] output io_replay_bits_is_hella, // @[mshrs.scala:39:14] output io_replay_bits_tag_match, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_old_meta_coh_state, // @[mshrs.scala:39:14] output [19:0] io_replay_bits_old_meta_tag, // @[mshrs.scala:39:14] output [7:0] io_replay_bits_way_en, // @[mshrs.scala:39:14] output [4:0] io_replay_bits_sdq_id, // @[mshrs.scala:39:14] input io_resp_ready, // @[mshrs.scala:39:14] output io_resp_valid, // @[mshrs.scala:39:14] output [6:0] io_resp_bits_uop_uopc, // @[mshrs.scala:39:14] output [31:0] io_resp_bits_uop_inst, // @[mshrs.scala:39:14] output [31:0] io_resp_bits_uop_debug_inst, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_rvc, // @[mshrs.scala:39:14] output [39:0] io_resp_bits_uop_debug_pc, // @[mshrs.scala:39:14] output [2:0] io_resp_bits_uop_iq_type, // @[mshrs.scala:39:14] output [9:0] io_resp_bits_uop_fu_code, // @[mshrs.scala:39:14] output [3:0] io_resp_bits_uop_ctrl_br_type, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_ctrl_op1_sel, // @[mshrs.scala:39:14] output [2:0] io_resp_bits_uop_ctrl_op2_sel, // @[mshrs.scala:39:14] output [2:0] io_resp_bits_uop_ctrl_imm_sel, // @[mshrs.scala:39:14] output [4:0] io_resp_bits_uop_ctrl_op_fcn, // @[mshrs.scala:39:14] output io_resp_bits_uop_ctrl_fcn_dw, // @[mshrs.scala:39:14] output [2:0] io_resp_bits_uop_ctrl_csr_cmd, // @[mshrs.scala:39:14] output io_resp_bits_uop_ctrl_is_load, // @[mshrs.scala:39:14] output io_resp_bits_uop_ctrl_is_sta, // @[mshrs.scala:39:14] output io_resp_bits_uop_ctrl_is_std, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_iw_state, // @[mshrs.scala:39:14] output io_resp_bits_uop_iw_p1_poisoned, // @[mshrs.scala:39:14] output io_resp_bits_uop_iw_p2_poisoned, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_br, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_jalr, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_jal, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_sfb, // @[mshrs.scala:39:14] output [15:0] io_resp_bits_uop_br_mask, // @[mshrs.scala:39:14] output [3:0] io_resp_bits_uop_br_tag, // @[mshrs.scala:39:14] output [4:0] io_resp_bits_uop_ftq_idx, // @[mshrs.scala:39:14] output io_resp_bits_uop_edge_inst, // @[mshrs.scala:39:14] output [5:0] io_resp_bits_uop_pc_lob, // @[mshrs.scala:39:14] output io_resp_bits_uop_taken, // @[mshrs.scala:39:14] output [19:0] io_resp_bits_uop_imm_packed, // @[mshrs.scala:39:14] output [11:0] io_resp_bits_uop_csr_addr, // @[mshrs.scala:39:14] output [6:0] io_resp_bits_uop_rob_idx, // @[mshrs.scala:39:14] output [4:0] io_resp_bits_uop_ldq_idx, // @[mshrs.scala:39:14] output [4:0] io_resp_bits_uop_stq_idx, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_rxq_idx, // @[mshrs.scala:39:14] output [6:0] io_resp_bits_uop_pdst, // @[mshrs.scala:39:14] output [6:0] io_resp_bits_uop_prs1, // @[mshrs.scala:39:14] output [6:0] io_resp_bits_uop_prs2, // @[mshrs.scala:39:14] output [6:0] io_resp_bits_uop_prs3, // @[mshrs.scala:39:14] output [4:0] io_resp_bits_uop_ppred, // @[mshrs.scala:39:14] output io_resp_bits_uop_prs1_busy, // @[mshrs.scala:39:14] output io_resp_bits_uop_prs2_busy, // @[mshrs.scala:39:14] output io_resp_bits_uop_prs3_busy, // @[mshrs.scala:39:14] output io_resp_bits_uop_ppred_busy, // @[mshrs.scala:39:14] output [6:0] io_resp_bits_uop_stale_pdst, // @[mshrs.scala:39:14] output io_resp_bits_uop_exception, // @[mshrs.scala:39:14] output [63:0] io_resp_bits_uop_exc_cause, // @[mshrs.scala:39:14] output io_resp_bits_uop_bypassable, // @[mshrs.scala:39:14] output [4:0] io_resp_bits_uop_mem_cmd, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_mem_size, // @[mshrs.scala:39:14] output io_resp_bits_uop_mem_signed, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_fence, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_fencei, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_amo, // @[mshrs.scala:39:14] output io_resp_bits_uop_uses_ldq, // @[mshrs.scala:39:14] output io_resp_bits_uop_uses_stq, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_sys_pc2epc, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_unique, // @[mshrs.scala:39:14] output io_resp_bits_uop_flush_on_commit, // @[mshrs.scala:39:14] output io_resp_bits_uop_ldst_is_rs1, // @[mshrs.scala:39:14] output [5:0] io_resp_bits_uop_ldst, // @[mshrs.scala:39:14] output [5:0] io_resp_bits_uop_lrs1, // @[mshrs.scala:39:14] output [5:0] io_resp_bits_uop_lrs2, // @[mshrs.scala:39:14] output [5:0] io_resp_bits_uop_lrs3, // @[mshrs.scala:39:14] output io_resp_bits_uop_ldst_val, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_dst_rtype, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_lrs1_rtype, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_lrs2_rtype, // @[mshrs.scala:39:14] output io_resp_bits_uop_frs3_en, // @[mshrs.scala:39:14] output io_resp_bits_uop_fp_val, // @[mshrs.scala:39:14] output io_resp_bits_uop_fp_single, // @[mshrs.scala:39:14] output io_resp_bits_uop_xcpt_pf_if, // @[mshrs.scala:39:14] output io_resp_bits_uop_xcpt_ae_if, // @[mshrs.scala:39:14] output io_resp_bits_uop_xcpt_ma_if, // @[mshrs.scala:39:14] output io_resp_bits_uop_bp_debug_if, // @[mshrs.scala:39:14] output io_resp_bits_uop_bp_xcpt_if, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_debug_fsrc, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_debug_tsrc, // @[mshrs.scala:39:14] output [63:0] io_resp_bits_data, // @[mshrs.scala:39:14] output io_resp_bits_is_hella, // @[mshrs.scala:39:14] input io_wb_resp, // @[mshrs.scala:39:14] output io_probe_rdy // @[mshrs.scala:39:14] ); wire rpq_io_deq_ready; // @[mshrs.scala:135:20, :215:30, :222:40, :233:41, :256:45] wire _rpq_io_enq_ready; // @[mshrs.scala:128:19] wire _rpq_io_deq_valid; // @[mshrs.scala:128:19] wire [6:0] _rpq_io_deq_bits_uop_uopc; // @[mshrs.scala:128:19] wire [31:0] _rpq_io_deq_bits_uop_inst; // @[mshrs.scala:128:19] wire [31:0] _rpq_io_deq_bits_uop_debug_inst; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_rvc; // @[mshrs.scala:128:19] wire [39:0] _rpq_io_deq_bits_uop_debug_pc; // @[mshrs.scala:128:19] wire [2:0] _rpq_io_deq_bits_uop_iq_type; // @[mshrs.scala:128:19] wire [9:0] _rpq_io_deq_bits_uop_fu_code; // @[mshrs.scala:128:19] wire [3:0] _rpq_io_deq_bits_uop_ctrl_br_type; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_ctrl_op1_sel; // @[mshrs.scala:128:19] wire [2:0] _rpq_io_deq_bits_uop_ctrl_op2_sel; // @[mshrs.scala:128:19] wire [2:0] _rpq_io_deq_bits_uop_ctrl_imm_sel; // @[mshrs.scala:128:19] wire [4:0] _rpq_io_deq_bits_uop_ctrl_op_fcn; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_ctrl_fcn_dw; // @[mshrs.scala:128:19] wire [2:0] _rpq_io_deq_bits_uop_ctrl_csr_cmd; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_ctrl_is_load; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_ctrl_is_sta; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_ctrl_is_std; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_iw_state; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_iw_p1_poisoned; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_iw_p2_poisoned; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_br; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_jalr; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_jal; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_sfb; // @[mshrs.scala:128:19] wire [15:0] _rpq_io_deq_bits_uop_br_mask; // @[mshrs.scala:128:19] wire [3:0] _rpq_io_deq_bits_uop_br_tag; // @[mshrs.scala:128:19] wire [4:0] _rpq_io_deq_bits_uop_ftq_idx; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_edge_inst; // @[mshrs.scala:128:19] wire [5:0] _rpq_io_deq_bits_uop_pc_lob; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_taken; // @[mshrs.scala:128:19] wire [19:0] _rpq_io_deq_bits_uop_imm_packed; // @[mshrs.scala:128:19] wire [11:0] _rpq_io_deq_bits_uop_csr_addr; // @[mshrs.scala:128:19] wire [6:0] _rpq_io_deq_bits_uop_rob_idx; // @[mshrs.scala:128:19] wire [4:0] _rpq_io_deq_bits_uop_ldq_idx; // @[mshrs.scala:128:19] wire [4:0] _rpq_io_deq_bits_uop_stq_idx; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_rxq_idx; // @[mshrs.scala:128:19] wire [6:0] _rpq_io_deq_bits_uop_pdst; // @[mshrs.scala:128:19] wire [6:0] _rpq_io_deq_bits_uop_prs1; // @[mshrs.scala:128:19] wire [6:0] _rpq_io_deq_bits_uop_prs2; // @[mshrs.scala:128:19] wire [6:0] _rpq_io_deq_bits_uop_prs3; // @[mshrs.scala:128:19] wire [4:0] _rpq_io_deq_bits_uop_ppred; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_prs1_busy; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_prs2_busy; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_prs3_busy; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_ppred_busy; // @[mshrs.scala:128:19] wire [6:0] _rpq_io_deq_bits_uop_stale_pdst; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_exception; // @[mshrs.scala:128:19] wire [63:0] _rpq_io_deq_bits_uop_exc_cause; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_bypassable; // @[mshrs.scala:128:19] wire [4:0] _rpq_io_deq_bits_uop_mem_cmd; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_mem_size; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_mem_signed; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_fence; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_fencei; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_amo; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_uses_ldq; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_uses_stq; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_sys_pc2epc; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_unique; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_flush_on_commit; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_ldst_is_rs1; // @[mshrs.scala:128:19] wire [5:0] _rpq_io_deq_bits_uop_ldst; // @[mshrs.scala:128:19] wire [5:0] _rpq_io_deq_bits_uop_lrs1; // @[mshrs.scala:128:19] wire [5:0] _rpq_io_deq_bits_uop_lrs2; // @[mshrs.scala:128:19] wire [5:0] _rpq_io_deq_bits_uop_lrs3; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_ldst_val; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_dst_rtype; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_lrs1_rtype; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_lrs2_rtype; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_frs3_en; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fp_val; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fp_single; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_xcpt_pf_if; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_xcpt_ae_if; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_xcpt_ma_if; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_bp_debug_if; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_bp_xcpt_if; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_debug_fsrc; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_debug_tsrc; // @[mshrs.scala:128:19] wire [39:0] _rpq_io_deq_bits_addr; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_is_hella; // @[mshrs.scala:128:19] wire _rpq_io_empty; // @[mshrs.scala:128:19] wire io_req_pri_val_0 = io_req_pri_val; // @[mshrs.scala:36:7] wire io_req_sec_val_0 = io_req_sec_val; // @[mshrs.scala:36:7] wire io_clear_prefetch_0 = io_clear_prefetch; // @[mshrs.scala:36:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[mshrs.scala:36:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[mshrs.scala:36:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[mshrs.scala:36:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[mshrs.scala:36:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[mshrs.scala:36:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[mshrs.scala:36:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[mshrs.scala:36:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[mshrs.scala:36:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[mshrs.scala:36:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[mshrs.scala:36:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[mshrs.scala:36:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[mshrs.scala:36:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[mshrs.scala:36:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[mshrs.scala:36:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[mshrs.scala:36:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[mshrs.scala:36:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[mshrs.scala:36:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[mshrs.scala:36:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[mshrs.scala:36:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[mshrs.scala:36:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[mshrs.scala:36:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[mshrs.scala:36:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[mshrs.scala:36:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[mshrs.scala:36:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[mshrs.scala:36:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[mshrs.scala:36:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[mshrs.scala:36:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[mshrs.scala:36:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[mshrs.scala:36:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[mshrs.scala:36:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[mshrs.scala:36:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[mshrs.scala:36:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[mshrs.scala:36:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[mshrs.scala:36:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[mshrs.scala:36:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[mshrs.scala:36:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[mshrs.scala:36:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[mshrs.scala:36:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[mshrs.scala:36:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[mshrs.scala:36:7] wire io_exception_0 = io_exception; // @[mshrs.scala:36:7] wire [6:0] io_rob_pnr_idx_0 = io_rob_pnr_idx; // @[mshrs.scala:36:7] wire [6:0] io_rob_head_idx_0 = io_rob_head_idx; // @[mshrs.scala:36:7] wire [6:0] io_req_uop_uopc_0 = io_req_uop_uopc; // @[mshrs.scala:36:7] wire [31:0] io_req_uop_inst_0 = io_req_uop_inst; // @[mshrs.scala:36:7] wire [31:0] io_req_uop_debug_inst_0 = io_req_uop_debug_inst; // @[mshrs.scala:36:7] wire io_req_uop_is_rvc_0 = io_req_uop_is_rvc; // @[mshrs.scala:36:7] wire [39:0] io_req_uop_debug_pc_0 = io_req_uop_debug_pc; // @[mshrs.scala:36:7] wire [2:0] io_req_uop_iq_type_0 = io_req_uop_iq_type; // @[mshrs.scala:36:7] wire [9:0] io_req_uop_fu_code_0 = io_req_uop_fu_code; // @[mshrs.scala:36:7] wire [3:0] io_req_uop_ctrl_br_type_0 = io_req_uop_ctrl_br_type; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_ctrl_op1_sel_0 = io_req_uop_ctrl_op1_sel; // @[mshrs.scala:36:7] wire [2:0] io_req_uop_ctrl_op2_sel_0 = io_req_uop_ctrl_op2_sel; // @[mshrs.scala:36:7] wire [2:0] io_req_uop_ctrl_imm_sel_0 = io_req_uop_ctrl_imm_sel; // @[mshrs.scala:36:7] wire [4:0] io_req_uop_ctrl_op_fcn_0 = io_req_uop_ctrl_op_fcn; // @[mshrs.scala:36:7] wire io_req_uop_ctrl_fcn_dw_0 = io_req_uop_ctrl_fcn_dw; // @[mshrs.scala:36:7] wire [2:0] io_req_uop_ctrl_csr_cmd_0 = io_req_uop_ctrl_csr_cmd; // @[mshrs.scala:36:7] wire io_req_uop_ctrl_is_load_0 = io_req_uop_ctrl_is_load; // @[mshrs.scala:36:7] wire io_req_uop_ctrl_is_sta_0 = io_req_uop_ctrl_is_sta; // @[mshrs.scala:36:7] wire io_req_uop_ctrl_is_std_0 = io_req_uop_ctrl_is_std; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_iw_state_0 = io_req_uop_iw_state; // @[mshrs.scala:36:7] wire io_req_uop_iw_p1_poisoned_0 = io_req_uop_iw_p1_poisoned; // @[mshrs.scala:36:7] wire io_req_uop_iw_p2_poisoned_0 = io_req_uop_iw_p2_poisoned; // @[mshrs.scala:36:7] wire io_req_uop_is_br_0 = io_req_uop_is_br; // @[mshrs.scala:36:7] wire io_req_uop_is_jalr_0 = io_req_uop_is_jalr; // @[mshrs.scala:36:7] wire io_req_uop_is_jal_0 = io_req_uop_is_jal; // @[mshrs.scala:36:7] wire io_req_uop_is_sfb_0 = io_req_uop_is_sfb; // @[mshrs.scala:36:7] wire [15:0] io_req_uop_br_mask_0 = io_req_uop_br_mask; // @[mshrs.scala:36:7] wire [3:0] io_req_uop_br_tag_0 = io_req_uop_br_tag; // @[mshrs.scala:36:7] wire [4:0] io_req_uop_ftq_idx_0 = io_req_uop_ftq_idx; // @[mshrs.scala:36:7] wire io_req_uop_edge_inst_0 = io_req_uop_edge_inst; // @[mshrs.scala:36:7] wire [5:0] io_req_uop_pc_lob_0 = io_req_uop_pc_lob; // @[mshrs.scala:36:7] wire io_req_uop_taken_0 = io_req_uop_taken; // @[mshrs.scala:36:7] wire [19:0] io_req_uop_imm_packed_0 = io_req_uop_imm_packed; // @[mshrs.scala:36:7] wire [11:0] io_req_uop_csr_addr_0 = io_req_uop_csr_addr; // @[mshrs.scala:36:7] wire [6:0] io_req_uop_rob_idx_0 = io_req_uop_rob_idx; // @[mshrs.scala:36:7] wire [4:0] io_req_uop_ldq_idx_0 = io_req_uop_ldq_idx; // @[mshrs.scala:36:7] wire [4:0] io_req_uop_stq_idx_0 = io_req_uop_stq_idx; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_rxq_idx_0 = io_req_uop_rxq_idx; // @[mshrs.scala:36:7] wire [6:0] io_req_uop_pdst_0 = io_req_uop_pdst; // @[mshrs.scala:36:7] wire [6:0] io_req_uop_prs1_0 = io_req_uop_prs1; // @[mshrs.scala:36:7] wire [6:0] io_req_uop_prs2_0 = io_req_uop_prs2; // @[mshrs.scala:36:7] wire [6:0] io_req_uop_prs3_0 = io_req_uop_prs3; // @[mshrs.scala:36:7] wire [4:0] io_req_uop_ppred_0 = io_req_uop_ppred; // @[mshrs.scala:36:7] wire io_req_uop_prs1_busy_0 = io_req_uop_prs1_busy; // @[mshrs.scala:36:7] wire io_req_uop_prs2_busy_0 = io_req_uop_prs2_busy; // @[mshrs.scala:36:7] wire io_req_uop_prs3_busy_0 = io_req_uop_prs3_busy; // @[mshrs.scala:36:7] wire io_req_uop_ppred_busy_0 = io_req_uop_ppred_busy; // @[mshrs.scala:36:7] wire [6:0] io_req_uop_stale_pdst_0 = io_req_uop_stale_pdst; // @[mshrs.scala:36:7] wire io_req_uop_exception_0 = io_req_uop_exception; // @[mshrs.scala:36:7] wire [63:0] io_req_uop_exc_cause_0 = io_req_uop_exc_cause; // @[mshrs.scala:36:7] wire io_req_uop_bypassable_0 = io_req_uop_bypassable; // @[mshrs.scala:36:7] wire [4:0] io_req_uop_mem_cmd_0 = io_req_uop_mem_cmd; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_mem_size_0 = io_req_uop_mem_size; // @[mshrs.scala:36:7] wire io_req_uop_mem_signed_0 = io_req_uop_mem_signed; // @[mshrs.scala:36:7] wire io_req_uop_is_fence_0 = io_req_uop_is_fence; // @[mshrs.scala:36:7] wire io_req_uop_is_fencei_0 = io_req_uop_is_fencei; // @[mshrs.scala:36:7] wire io_req_uop_is_amo_0 = io_req_uop_is_amo; // @[mshrs.scala:36:7] wire io_req_uop_uses_ldq_0 = io_req_uop_uses_ldq; // @[mshrs.scala:36:7] wire io_req_uop_uses_stq_0 = io_req_uop_uses_stq; // @[mshrs.scala:36:7] wire io_req_uop_is_sys_pc2epc_0 = io_req_uop_is_sys_pc2epc; // @[mshrs.scala:36:7] wire io_req_uop_is_unique_0 = io_req_uop_is_unique; // @[mshrs.scala:36:7] wire io_req_uop_flush_on_commit_0 = io_req_uop_flush_on_commit; // @[mshrs.scala:36:7] wire io_req_uop_ldst_is_rs1_0 = io_req_uop_ldst_is_rs1; // @[mshrs.scala:36:7] wire [5:0] io_req_uop_ldst_0 = io_req_uop_ldst; // @[mshrs.scala:36:7] wire [5:0] io_req_uop_lrs1_0 = io_req_uop_lrs1; // @[mshrs.scala:36:7] wire [5:0] io_req_uop_lrs2_0 = io_req_uop_lrs2; // @[mshrs.scala:36:7] wire [5:0] io_req_uop_lrs3_0 = io_req_uop_lrs3; // @[mshrs.scala:36:7] wire io_req_uop_ldst_val_0 = io_req_uop_ldst_val; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_dst_rtype_0 = io_req_uop_dst_rtype; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_lrs1_rtype_0 = io_req_uop_lrs1_rtype; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_lrs2_rtype_0 = io_req_uop_lrs2_rtype; // @[mshrs.scala:36:7] wire io_req_uop_frs3_en_0 = io_req_uop_frs3_en; // @[mshrs.scala:36:7] wire io_req_uop_fp_val_0 = io_req_uop_fp_val; // @[mshrs.scala:36:7] wire io_req_uop_fp_single_0 = io_req_uop_fp_single; // @[mshrs.scala:36:7] wire io_req_uop_xcpt_pf_if_0 = io_req_uop_xcpt_pf_if; // @[mshrs.scala:36:7] wire io_req_uop_xcpt_ae_if_0 = io_req_uop_xcpt_ae_if; // @[mshrs.scala:36:7] wire io_req_uop_xcpt_ma_if_0 = io_req_uop_xcpt_ma_if; // @[mshrs.scala:36:7] wire io_req_uop_bp_debug_if_0 = io_req_uop_bp_debug_if; // @[mshrs.scala:36:7] wire io_req_uop_bp_xcpt_if_0 = io_req_uop_bp_xcpt_if; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_debug_fsrc_0 = io_req_uop_debug_fsrc; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_debug_tsrc_0 = io_req_uop_debug_tsrc; // @[mshrs.scala:36:7] wire [39:0] io_req_addr_0 = io_req_addr; // @[mshrs.scala:36:7] wire [63:0] io_req_data_0 = io_req_data; // @[mshrs.scala:36:7] wire io_req_is_hella_0 = io_req_is_hella; // @[mshrs.scala:36:7] wire io_req_tag_match_0 = io_req_tag_match; // @[mshrs.scala:36:7] wire [1:0] io_req_old_meta_coh_state_0 = io_req_old_meta_coh_state; // @[mshrs.scala:36:7] wire [19:0] io_req_old_meta_tag_0 = io_req_old_meta_tag; // @[mshrs.scala:36:7] wire [7:0] io_req_way_en_0 = io_req_way_en; // @[mshrs.scala:36:7] wire [4:0] io_req_sdq_id_0 = io_req_sdq_id; // @[mshrs.scala:36:7] wire io_req_is_probe_0 = io_req_is_probe; // @[mshrs.scala:36:7] wire io_mem_acquire_ready_0 = io_mem_acquire_ready; // @[mshrs.scala:36:7] wire io_mem_grant_valid_0 = io_mem_grant_valid; // @[mshrs.scala:36:7] wire [2:0] io_mem_grant_bits_opcode_0 = io_mem_grant_bits_opcode; // @[mshrs.scala:36:7] wire [1:0] io_mem_grant_bits_param_0 = io_mem_grant_bits_param; // @[mshrs.scala:36:7] wire [3:0] io_mem_grant_bits_size_0 = io_mem_grant_bits_size; // @[mshrs.scala:36:7] wire [2:0] io_mem_grant_bits_source_0 = io_mem_grant_bits_source; // @[mshrs.scala:36:7] wire [3:0] io_mem_grant_bits_sink_0 = io_mem_grant_bits_sink; // @[mshrs.scala:36:7] wire io_mem_grant_bits_denied_0 = io_mem_grant_bits_denied; // @[mshrs.scala:36:7] wire [127:0] io_mem_grant_bits_data_0 = io_mem_grant_bits_data; // @[mshrs.scala:36:7] wire io_mem_grant_bits_corrupt_0 = io_mem_grant_bits_corrupt; // @[mshrs.scala:36:7] wire io_mem_finish_ready_0 = io_mem_finish_ready; // @[mshrs.scala:36:7] wire io_prober_state_valid_0 = io_prober_state_valid; // @[mshrs.scala:36:7] wire [39:0] io_prober_state_bits_0 = io_prober_state_bits; // @[mshrs.scala:36:7] wire io_refill_ready_0 = io_refill_ready; // @[mshrs.scala:36:7] wire io_meta_write_ready_0 = io_meta_write_ready; // @[mshrs.scala:36:7] wire io_meta_read_ready_0 = io_meta_read_ready; // @[mshrs.scala:36:7] wire io_meta_resp_valid_0 = io_meta_resp_valid; // @[mshrs.scala:36:7] wire [1:0] io_meta_resp_bits_coh_state_0 = io_meta_resp_bits_coh_state; // @[mshrs.scala:36:7] wire [19:0] io_meta_resp_bits_tag_0 = io_meta_resp_bits_tag; // @[mshrs.scala:36:7] wire io_wb_req_ready_0 = io_wb_req_ready; // @[mshrs.scala:36:7] wire io_lb_read_ready_0 = io_lb_read_ready; // @[mshrs.scala:36:7] wire [127:0] io_lb_resp_0 = io_lb_resp; // @[mshrs.scala:36:7] wire io_lb_write_ready_0 = io_lb_write_ready; // @[mshrs.scala:36:7] wire io_replay_ready_0 = io_replay_ready; // @[mshrs.scala:36:7] wire io_resp_ready_0 = io_resp_ready; // @[mshrs.scala:36:7] wire io_wb_resp_0 = io_wb_resp; // @[mshrs.scala:36:7] wire _state_T = reset; // @[mshrs.scala:194:11] wire _state_T_26 = reset; // @[mshrs.scala:201:15] wire _state_T_34 = reset; // @[mshrs.scala:194:11] wire _state_T_60 = reset; // @[mshrs.scala:201:15] wire [1:0] io_id = 2'h1; // @[mshrs.scala:36:7] wire [1:0] io_lb_read_bits_id = 2'h1; // @[mshrs.scala:36:7] wire [1:0] io_lb_write_bits_id = 2'h1; // @[mshrs.scala:36:7] wire [1:0] _grow_param_r_T_7 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _grow_param_r_T_9 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _grow_param_r_T_17 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _grow_param_r_T_19 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _coh_on_grant_T_5 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r1_T_7 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r1_T_9 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r1_T_17 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r1_T_19 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r2_T_7 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r2_T_9 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r2_T_17 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r2_T_19 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_7 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_9 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_17 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_19 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_71 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_73 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_81 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_83 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_130 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_132 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_140 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_142 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_66 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_68 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_76 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_78 = 2'h1; // @[Metadata.scala:25:15] wire [2:0] io_mem_acquire_bits_opcode = 3'h6; // @[mshrs.scala:36:7] wire [2:0] io_mem_acquire_bits_a_opcode = 3'h6; // @[Edges.scala:346:17] wire [3:0] io_mem_acquire_bits_size = 4'h6; // @[mshrs.scala:36:7] wire [3:0] _r_T_12 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] _grow_param_r_T_10 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _r1_T_10 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _r2_T_10 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _state_req_needs_wb_r_T_12 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] _state_r_T_10 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] io_mem_acquire_bits_a_size = 4'h6; // @[Edges.scala:346:17] wire [3:0] _io_mem_acquire_bits_a_mask_sizeOH_T = 4'h6; // @[Misc.scala:202:34] wire [3:0] _needs_wb_r_T_12 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] _r_T_74 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _r_T_133 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _state_req_needs_wb_r_T_76 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] _state_r_T_69 = 4'h6; // @[Metadata.scala:64:10] wire [2:0] io_mem_acquire_bits_source = 3'h1; // @[mshrs.scala:36:7] wire [2:0] io_wb_req_bits_source = 3'h1; // @[mshrs.scala:36:7] wire [2:0] io_mem_acquire_bits_a_source = 3'h1; // @[Edges.scala:346:17] wire [15:0] io_mem_acquire_bits_mask = 16'hFFFF; // @[mshrs.scala:36:7] wire [15:0] io_mem_acquire_bits_a_mask = 16'hFFFF; // @[Edges.scala:346:17] wire [15:0] _io_mem_acquire_bits_a_mask_T = 16'hFFFF; // @[Misc.scala:222:10] wire [127:0] io_mem_acquire_bits_data = 128'h0; // @[mshrs.scala:36:7] wire [127:0] io_mem_acquire_bits_a_data = 128'h0; // @[Edges.scala:346:17] wire io_mem_acquire_bits_corrupt = 1'h0; // @[mshrs.scala:36:7] wire _r_T_2 = 1'h0; // @[Metadata.scala:140:24] wire _r_T_4 = 1'h0; // @[Metadata.scala:140:24] wire _r_T_20 = 1'h0; // @[Misc.scala:38:9] wire _r_T_24 = 1'h0; // @[Misc.scala:38:9] wire _r_T_28 = 1'h0; // @[Misc.scala:38:9] wire _grow_param_r_T_26 = 1'h0; // @[Misc.scala:35:9] wire _grow_param_r_T_29 = 1'h0; // @[Misc.scala:35:9] wire _grow_param_r_T_32 = 1'h0; // @[Misc.scala:35:9] wire _grow_param_r_T_35 = 1'h0; // @[Misc.scala:35:9] wire _grow_param_r_T_38 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_26 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_29 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_32 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_35 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_38 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_26 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_29 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_32 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_35 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_38 = 1'h0; // @[Misc.scala:35:9] wire _state_req_needs_wb_r_T_2 = 1'h0; // @[Metadata.scala:140:24] wire _state_req_needs_wb_r_T_4 = 1'h0; // @[Metadata.scala:140:24] wire _state_req_needs_wb_r_T_20 = 1'h0; // @[Misc.scala:38:9] wire _state_req_needs_wb_r_T_24 = 1'h0; // @[Misc.scala:38:9] wire _state_req_needs_wb_r_T_28 = 1'h0; // @[Misc.scala:38:9] wire _state_r_T_26 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_29 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_32 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_35 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_38 = 1'h0; // @[Misc.scala:35:9] wire _io_mem_acquire_bits_legal_T = 1'h0; // @[Parameters.scala:684:29] wire _io_mem_acquire_bits_legal_T_18 = 1'h0; // @[Parameters.scala:684:54] wire _io_mem_acquire_bits_legal_T_33 = 1'h0; // @[Parameters.scala:686:26] wire io_mem_acquire_bits_a_corrupt = 1'h0; // @[Edges.scala:346:17] wire io_mem_acquire_bits_a_mask_sub_sub_sub_size = 1'h0; // @[Misc.scala:209:26] wire _io_mem_acquire_bits_a_mask_sub_sub_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_sub_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire io_mem_acquire_bits_a_mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _io_mem_acquire_bits_a_mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38] wire io_resp_bits_data_doZero = 1'h0; // @[AMOALU.scala:43:31] wire io_resp_bits_data_doZero_1 = 1'h0; // @[AMOALU.scala:43:31] wire io_resp_bits_data_doZero_2 = 1'h0; // @[AMOALU.scala:43:31] wire _needs_wb_r_T_2 = 1'h0; // @[Metadata.scala:140:24] wire _needs_wb_r_T_4 = 1'h0; // @[Metadata.scala:140:24] wire _needs_wb_r_T_20 = 1'h0; // @[Misc.scala:38:9] wire _needs_wb_r_T_24 = 1'h0; // @[Misc.scala:38:9] wire _needs_wb_r_T_28 = 1'h0; // @[Misc.scala:38:9] wire _r_T_90 = 1'h0; // @[Misc.scala:35:9] wire _r_T_93 = 1'h0; // @[Misc.scala:35:9] wire _r_T_96 = 1'h0; // @[Misc.scala:35:9] wire _r_T_99 = 1'h0; // @[Misc.scala:35:9] wire _r_T_102 = 1'h0; // @[Misc.scala:35:9] wire _r_T_149 = 1'h0; // @[Misc.scala:35:9] wire _r_T_152 = 1'h0; // @[Misc.scala:35:9] wire _r_T_155 = 1'h0; // @[Misc.scala:35:9] wire _r_T_158 = 1'h0; // @[Misc.scala:35:9] wire _r_T_161 = 1'h0; // @[Misc.scala:35:9] wire _state_req_needs_wb_r_T_66 = 1'h0; // @[Metadata.scala:140:24] wire _state_req_needs_wb_r_T_68 = 1'h0; // @[Metadata.scala:140:24] wire _state_req_needs_wb_r_T_84 = 1'h0; // @[Misc.scala:38:9] wire _state_req_needs_wb_r_T_88 = 1'h0; // @[Misc.scala:38:9] wire _state_req_needs_wb_r_T_92 = 1'h0; // @[Misc.scala:38:9] wire _state_r_T_85 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_88 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_91 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_94 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_97 = 1'h0; // @[Misc.scala:35:9] wire [1:0] io_refill_bits_wmask = 2'h3; // @[mshrs.scala:36:7] wire [1:0] _grow_param_r_T_11 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _grow_param_r_T_13 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _grow_param_r_T_21 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _grow_param_r_T_23 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _coh_on_grant_T_7 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r1_T_11 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r1_T_13 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r1_T_21 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r1_T_23 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r2_T_11 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r2_T_13 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r2_T_21 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r2_T_23 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _dirties_T = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_11 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_13 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_21 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_23 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] io_mem_acquire_bits_a_mask_lo_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_lo_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_lo_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_lo_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_hi_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_hi_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_hi_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_hi_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] _io_refill_bits_wmask_T = 2'h3; // @[mshrs.scala:342:30] wire [1:0] _r_T_75 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_77 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_85 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_87 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_134 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_136 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_144 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_146 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_70 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_72 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_80 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_82 = 2'h3; // @[Metadata.scala:24:15] wire [19:0] io_meta_write_bits_tag = 20'h0; // @[mshrs.scala:36:7] wire io_wb_req_bits_voluntary = 1'h1; // @[mshrs.scala:36:7] wire _r_T = 1'h1; // @[Metadata.scala:140:24] wire _state_req_needs_wb_r_T = 1'h1; // @[Metadata.scala:140:24] wire _io_mem_acquire_bits_legal_T_19 = 1'h1; // @[Parameters.scala:91:44] wire _io_mem_acquire_bits_legal_T_20 = 1'h1; // @[Parameters.scala:684:29] wire io_mem_acquire_bits_a_mask_sub_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire io_mem_acquire_bits_a_mask_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_sub_size = 1'h1; // @[Misc.scala:209:26] wire io_mem_acquire_bits_a_mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_sub_2_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_sub_3_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_2_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_3_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_4_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_5_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_6_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_7_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_size = 1'h1; // @[Misc.scala:209:26] wire io_mem_acquire_bits_a_mask_acc = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_4 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_5 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_6 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_7 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_8 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_9 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_10 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_11 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_12 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_13 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_14 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_15 = 1'h1; // @[Misc.scala:215:29] wire _needs_wb_r_T = 1'h1; // @[Metadata.scala:140:24] wire _state_req_needs_wb_r_T_64 = 1'h1; // @[Metadata.scala:140:24] wire [1:0] new_coh_meta_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] _r_T_22 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_26 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_30 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_34 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_38 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _grow_param_r_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _grow_param_r_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _grow_param_r_T_5 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _grow_param_r_T_15 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _coh_on_grant_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _coh_on_grant_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r1_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r1_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r1_T_5 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r1_T_15 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r2_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r2_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r2_T_5 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r2_T_15 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_req_needs_wb_r_T_22 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_26 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_30 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_34 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_38 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_r_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_r_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_r_T_5 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_r_T_15 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] state_new_coh_meta_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] _needs_wb_r_T_22 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _needs_wb_r_T_26 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _needs_wb_r_T_30 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _needs_wb_r_T_34 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _needs_wb_r_T_38 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_65 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_67 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_69 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_79 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_124 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_126 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_128 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_138 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] new_coh_meta_1_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] _state_req_needs_wb_r_T_86 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_90 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_94 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_98 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_102 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_r_T_60 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_r_T_62 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_r_T_64 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_r_T_74 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] state_new_coh_meta_1_state = 2'h0; // @[Metadata.scala:160:20] wire [3:0] _grow_param_r_T_24 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _coh_on_grant_T_8 = 4'hC; // @[Metadata.scala:89:10] wire [3:0] _r1_T_24 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _r2_T_24 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _state_r_T_24 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _r_T_88 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _r_T_147 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _state_r_T_83 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _grow_param_r_T_22 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r1_T_22 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r2_T_22 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _state_r_T_22 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r_T_86 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r_T_145 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _state_r_T_81 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r_T_14 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _grow_param_r_T_20 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _coh_on_grant_T_6 = 4'h4; // @[Metadata.scala:88:10] wire [3:0] _r1_T_20 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _r2_T_20 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _state_req_needs_wb_r_T_14 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _state_r_T_20 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _io_mem_acquire_bits_a_mask_sizeOH_T_1 = 4'h4; // @[OneHot.scala:65:12] wire [3:0] _io_mem_acquire_bits_a_mask_sizeOH_T_2 = 4'h4; // @[OneHot.scala:65:27] wire [3:0] _needs_wb_r_T_14 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _r_T_84 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _r_T_143 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _state_req_needs_wb_r_T_78 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _state_r_T_79 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _r_T_13 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] _grow_param_r_T_18 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _r1_T_18 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _r2_T_18 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _state_req_needs_wb_r_T_13 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] _state_r_T_18 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] io_mem_acquire_bits_a_mask_sizeOH = 4'h5; // @[Misc.scala:202:81] wire [3:0] _needs_wb_r_T_13 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] _r_T_82 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _r_T_141 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _state_req_needs_wb_r_T_77 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] _state_r_T_77 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _r_T_10 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _grow_param_r_T_16 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _coh_on_grant_T_4 = 4'h0; // @[Metadata.scala:87:10] wire [3:0] _r1_T_16 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _r2_T_16 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _state_req_needs_wb_r_T_10 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _state_r_T_16 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _needs_wb_r_T_10 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _r_T_80 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _r_T_139 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _state_req_needs_wb_r_T_74 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _state_r_T_75 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _grow_param_r_T_14 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _r1_T_14 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _r2_T_14 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _state_r_T_14 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _r_T_78 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _r_T_137 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _state_r_T_73 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _grow_param_r_T_12 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _r1_T_12 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _r2_T_12 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _state_r_T_12 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] io_mem_acquire_bits_a_mask_lo_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] io_mem_acquire_bits_a_mask_lo_hi = 4'hF; // @[Misc.scala:222:10] wire [3:0] io_mem_acquire_bits_a_mask_hi_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] io_mem_acquire_bits_a_mask_hi_hi = 4'hF; // @[Misc.scala:222:10] wire [3:0] _r_T_76 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _r_T_135 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _state_r_T_71 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _r_T_11 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _grow_param_r_T_8 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _r1_T_8 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _r2_T_8 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _state_req_needs_wb_r_T_11 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _state_r_T_8 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _needs_wb_r_T_11 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _r_T_72 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _r_T_131 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _state_req_needs_wb_r_T_75 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _state_r_T_67 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _r_T_9 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _grow_param_r_T_6 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _coh_on_grant_T_2 = 4'h1; // @[Metadata.scala:86:10] wire [3:0] _r1_T_6 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _r2_T_6 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _state_req_needs_wb_r_T_9 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _state_r_T_6 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _needs_wb_r_T_9 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _r_T_70 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _r_T_129 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _state_req_needs_wb_r_T_73 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _state_r_T_65 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _r_T_8 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _grow_param_r_T_4 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _r1_T_4 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _r2_T_4 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _state_req_needs_wb_r_T_8 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _state_r_T_4 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _needs_wb_r_T_8 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _r_T_68 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _r_T_127 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _state_req_needs_wb_r_T_72 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _state_r_T_63 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _r_T_7 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _grow_param_r_T_2 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _r1_T_2 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _r2_T_2 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _state_req_needs_wb_r_T_7 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _state_r_T_2 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _needs_wb_r_T_7 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _r_T_66 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _r_T_125 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _state_req_needs_wb_r_T_71 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _state_r_T_61 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _r_T_18 = 4'h8; // @[Metadata.scala:133:10] wire [3:0] _state_req_needs_wb_r_T_18 = 4'h8; // @[Metadata.scala:133:10] wire [3:0] _needs_wb_r_T_18 = 4'h8; // @[Metadata.scala:133:10] wire [3:0] _state_req_needs_wb_r_T_82 = 4'h8; // @[Metadata.scala:133:10] wire [3:0] _r_T_17 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _state_req_needs_wb_r_T_17 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _needs_wb_r_T_17 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _state_req_needs_wb_r_T_81 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _r_T_16 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _state_req_needs_wb_r_T_16 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _needs_wb_r_T_16 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _state_req_needs_wb_r_T_80 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _r_T_15 = 4'hB; // @[Metadata.scala:130:10] wire [3:0] _state_req_needs_wb_r_T_15 = 4'hB; // @[Metadata.scala:130:10] wire [3:0] _needs_wb_r_T_15 = 4'hB; // @[Metadata.scala:130:10] wire [3:0] _state_req_needs_wb_r_T_79 = 4'hB; // @[Metadata.scala:130:10] wire [1:0] _r_T_1 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _r_T_3 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _r_T_5 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _state_req_needs_wb_r_T_1 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _state_req_needs_wb_r_T_3 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _state_req_needs_wb_r_T_5 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] io_mem_acquire_bits_a_mask_sizeOH_shiftAmount = 2'h2; // @[OneHot.scala:64:49] wire [1:0] _needs_wb_r_T_1 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _needs_wb_r_T_3 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _needs_wb_r_T_5 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _state_req_needs_wb_r_T_65 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _state_req_needs_wb_r_T_67 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _state_req_needs_wb_r_T_69 = 2'h2; // @[Metadata.scala:140:24] wire [7:0] io_mem_acquire_bits_a_mask_lo = 8'hFF; // @[Misc.scala:222:10] wire [7:0] io_mem_acquire_bits_a_mask_hi = 8'hFF; // @[Misc.scala:222:10] wire _io_req_sec_rdy_T; // @[mshrs.scala:159:37] wire _io_idx_valid_T; // @[mshrs.scala:149:25] wire [5:0] req_idx; // @[mshrs.scala:110:25] wire _io_way_valid_T_3; // @[mshrs.scala:151:19] wire _io_tag_valid_T; // @[mshrs.scala:150:25] wire [27:0] req_tag; // @[mshrs.scala:111:26] wire [2:0] io_mem_acquire_bits_a_param; // @[Edges.scala:346:17] wire [31:0] io_mem_acquire_bits_a_address; // @[Edges.scala:346:17] wire [3:0] grantack_bits_e_sink = io_mem_grant_bits_sink_0; // @[Edges.scala:451:17] wire [127:0] io_lb_write_bits_data_0 = io_mem_grant_bits_data_0; // @[mshrs.scala:36:7] wire [2:0] shrink_param; // @[Misc.scala:38:36] wire [1:0] coh_on_grant_state; // @[Metadata.scala:160:20] wire [127:0] io_refill_bits_data_0 = io_lb_resp_0; // @[mshrs.scala:36:7] wire [39:0] _io_replay_bits_addr_T_1; // @[mshrs.scala:353:31] wire [63:0] _io_resp_bits_data_T_23; // @[AMOALU.scala:45:16] wire _io_probe_rdy_T_11; // @[mshrs.scala:148:42] wire io_idx_valid_0; // @[mshrs.scala:36:7] wire [5:0] io_idx_bits_0; // @[mshrs.scala:36:7] wire io_way_valid_0; // @[mshrs.scala:36:7] wire [7:0] io_way_bits_0; // @[mshrs.scala:36:7] wire io_tag_valid_0; // @[mshrs.scala:36:7] wire [27:0] io_tag_bits_0; // @[mshrs.scala:36:7] wire [2:0] io_mem_acquire_bits_param_0; // @[mshrs.scala:36:7] wire [31:0] io_mem_acquire_bits_address_0; // @[mshrs.scala:36:7] wire io_mem_acquire_valid_0; // @[mshrs.scala:36:7] wire io_mem_grant_ready_0; // @[mshrs.scala:36:7] wire [3:0] io_mem_finish_bits_sink_0; // @[mshrs.scala:36:7] wire io_mem_finish_valid_0; // @[mshrs.scala:36:7] wire [7:0] io_refill_bits_way_en_0; // @[mshrs.scala:36:7] wire [11:0] io_refill_bits_addr_0; // @[mshrs.scala:36:7] wire io_refill_valid_0; // @[mshrs.scala:36:7] wire [1:0] io_meta_write_bits_data_coh_state_0; // @[mshrs.scala:36:7] wire [19:0] io_meta_write_bits_data_tag_0; // @[mshrs.scala:36:7] wire [5:0] io_meta_write_bits_idx_0; // @[mshrs.scala:36:7] wire [7:0] io_meta_write_bits_way_en_0; // @[mshrs.scala:36:7] wire io_meta_write_valid_0; // @[mshrs.scala:36:7] wire [5:0] io_meta_read_bits_idx_0; // @[mshrs.scala:36:7] wire [7:0] io_meta_read_bits_way_en_0; // @[mshrs.scala:36:7] wire [19:0] io_meta_read_bits_tag_0; // @[mshrs.scala:36:7] wire io_meta_read_valid_0; // @[mshrs.scala:36:7] wire [19:0] io_wb_req_bits_tag_0; // @[mshrs.scala:36:7] wire [5:0] io_wb_req_bits_idx_0; // @[mshrs.scala:36:7] wire [2:0] io_wb_req_bits_param_0; // @[mshrs.scala:36:7] wire [7:0] io_wb_req_bits_way_en_0; // @[mshrs.scala:36:7] wire io_wb_req_valid_0; // @[mshrs.scala:36:7] wire [1:0] io_commit_coh_state_0; // @[mshrs.scala:36:7] wire [1:0] io_lb_read_bits_offset_0; // @[mshrs.scala:36:7] wire io_lb_read_valid_0; // @[mshrs.scala:36:7] wire [1:0] io_lb_write_bits_offset_0; // @[mshrs.scala:36:7] wire io_lb_write_valid_0; // @[mshrs.scala:36:7] wire [3:0] io_replay_bits_uop_ctrl_br_type_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_ctrl_op1_sel_0; // @[mshrs.scala:36:7] wire [2:0] io_replay_bits_uop_ctrl_op2_sel_0; // @[mshrs.scala:36:7] wire [2:0] io_replay_bits_uop_ctrl_imm_sel_0; // @[mshrs.scala:36:7] wire [4:0] io_replay_bits_uop_ctrl_op_fcn_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_ctrl_fcn_dw_0; // @[mshrs.scala:36:7] wire [2:0] io_replay_bits_uop_ctrl_csr_cmd_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_ctrl_is_load_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_ctrl_is_sta_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_ctrl_is_std_0; // @[mshrs.scala:36:7] wire [6:0] io_replay_bits_uop_uopc_0; // @[mshrs.scala:36:7] wire [31:0] io_replay_bits_uop_inst_0; // @[mshrs.scala:36:7] wire [31:0] io_replay_bits_uop_debug_inst_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_rvc_0; // @[mshrs.scala:36:7] wire [39:0] io_replay_bits_uop_debug_pc_0; // @[mshrs.scala:36:7] wire [2:0] io_replay_bits_uop_iq_type_0; // @[mshrs.scala:36:7] wire [9:0] io_replay_bits_uop_fu_code_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_iw_state_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_iw_p1_poisoned_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_iw_p2_poisoned_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_br_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_jalr_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_jal_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_sfb_0; // @[mshrs.scala:36:7] wire [15:0] io_replay_bits_uop_br_mask_0; // @[mshrs.scala:36:7] wire [3:0] io_replay_bits_uop_br_tag_0; // @[mshrs.scala:36:7] wire [4:0] io_replay_bits_uop_ftq_idx_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_edge_inst_0; // @[mshrs.scala:36:7] wire [5:0] io_replay_bits_uop_pc_lob_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_taken_0; // @[mshrs.scala:36:7] wire [19:0] io_replay_bits_uop_imm_packed_0; // @[mshrs.scala:36:7] wire [11:0] io_replay_bits_uop_csr_addr_0; // @[mshrs.scala:36:7] wire [6:0] io_replay_bits_uop_rob_idx_0; // @[mshrs.scala:36:7] wire [4:0] io_replay_bits_uop_ldq_idx_0; // @[mshrs.scala:36:7] wire [4:0] io_replay_bits_uop_stq_idx_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_rxq_idx_0; // @[mshrs.scala:36:7] wire [6:0] io_replay_bits_uop_pdst_0; // @[mshrs.scala:36:7] wire [6:0] io_replay_bits_uop_prs1_0; // @[mshrs.scala:36:7] wire [6:0] io_replay_bits_uop_prs2_0; // @[mshrs.scala:36:7] wire [6:0] io_replay_bits_uop_prs3_0; // @[mshrs.scala:36:7] wire [4:0] io_replay_bits_uop_ppred_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_prs1_busy_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_prs2_busy_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_prs3_busy_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_ppred_busy_0; // @[mshrs.scala:36:7] wire [6:0] io_replay_bits_uop_stale_pdst_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_exception_0; // @[mshrs.scala:36:7] wire [63:0] io_replay_bits_uop_exc_cause_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_bypassable_0; // @[mshrs.scala:36:7] wire [4:0] io_replay_bits_uop_mem_cmd_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_mem_size_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_mem_signed_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_fence_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_fencei_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_amo_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_uses_ldq_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_uses_stq_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_sys_pc2epc_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_unique_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_flush_on_commit_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_ldst_is_rs1_0; // @[mshrs.scala:36:7] wire [5:0] io_replay_bits_uop_ldst_0; // @[mshrs.scala:36:7] wire [5:0] io_replay_bits_uop_lrs1_0; // @[mshrs.scala:36:7] wire [5:0] io_replay_bits_uop_lrs2_0; // @[mshrs.scala:36:7] wire [5:0] io_replay_bits_uop_lrs3_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_ldst_val_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_dst_rtype_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_lrs1_rtype_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_lrs2_rtype_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_frs3_en_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fp_val_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fp_single_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_xcpt_pf_if_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_xcpt_ae_if_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_xcpt_ma_if_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_bp_debug_if_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_bp_xcpt_if_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_debug_fsrc_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_debug_tsrc_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_old_meta_coh_state_0; // @[mshrs.scala:36:7] wire [19:0] io_replay_bits_old_meta_tag_0; // @[mshrs.scala:36:7] wire [39:0] io_replay_bits_addr_0; // @[mshrs.scala:36:7] wire [63:0] io_replay_bits_data_0; // @[mshrs.scala:36:7] wire io_replay_bits_is_hella_0; // @[mshrs.scala:36:7] wire io_replay_bits_tag_match_0; // @[mshrs.scala:36:7] wire [7:0] io_replay_bits_way_en_0; // @[mshrs.scala:36:7] wire [4:0] io_replay_bits_sdq_id_0; // @[mshrs.scala:36:7] wire io_replay_valid_0; // @[mshrs.scala:36:7] wire [3:0] io_resp_bits_uop_ctrl_br_type_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_ctrl_op1_sel_0; // @[mshrs.scala:36:7] wire [2:0] io_resp_bits_uop_ctrl_op2_sel_0; // @[mshrs.scala:36:7] wire [2:0] io_resp_bits_uop_ctrl_imm_sel_0; // @[mshrs.scala:36:7] wire [4:0] io_resp_bits_uop_ctrl_op_fcn_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_ctrl_fcn_dw_0; // @[mshrs.scala:36:7] wire [2:0] io_resp_bits_uop_ctrl_csr_cmd_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_ctrl_is_load_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_ctrl_is_sta_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_ctrl_is_std_0; // @[mshrs.scala:36:7] wire [6:0] io_resp_bits_uop_uopc_0; // @[mshrs.scala:36:7] wire [31:0] io_resp_bits_uop_inst_0; // @[mshrs.scala:36:7] wire [31:0] io_resp_bits_uop_debug_inst_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_rvc_0; // @[mshrs.scala:36:7] wire [39:0] io_resp_bits_uop_debug_pc_0; // @[mshrs.scala:36:7] wire [2:0] io_resp_bits_uop_iq_type_0; // @[mshrs.scala:36:7] wire [9:0] io_resp_bits_uop_fu_code_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_iw_state_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_iw_p1_poisoned_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_iw_p2_poisoned_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_br_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_jalr_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_jal_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_sfb_0; // @[mshrs.scala:36:7] wire [15:0] io_resp_bits_uop_br_mask_0; // @[mshrs.scala:36:7] wire [3:0] io_resp_bits_uop_br_tag_0; // @[mshrs.scala:36:7] wire [4:0] io_resp_bits_uop_ftq_idx_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_edge_inst_0; // @[mshrs.scala:36:7] wire [5:0] io_resp_bits_uop_pc_lob_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_taken_0; // @[mshrs.scala:36:7] wire [19:0] io_resp_bits_uop_imm_packed_0; // @[mshrs.scala:36:7] wire [11:0] io_resp_bits_uop_csr_addr_0; // @[mshrs.scala:36:7] wire [6:0] io_resp_bits_uop_rob_idx_0; // @[mshrs.scala:36:7] wire [4:0] io_resp_bits_uop_ldq_idx_0; // @[mshrs.scala:36:7] wire [4:0] io_resp_bits_uop_stq_idx_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_rxq_idx_0; // @[mshrs.scala:36:7] wire [6:0] io_resp_bits_uop_pdst_0; // @[mshrs.scala:36:7] wire [6:0] io_resp_bits_uop_prs1_0; // @[mshrs.scala:36:7] wire [6:0] io_resp_bits_uop_prs2_0; // @[mshrs.scala:36:7] wire [6:0] io_resp_bits_uop_prs3_0; // @[mshrs.scala:36:7] wire [4:0] io_resp_bits_uop_ppred_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_prs1_busy_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_prs2_busy_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_prs3_busy_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_ppred_busy_0; // @[mshrs.scala:36:7] wire [6:0] io_resp_bits_uop_stale_pdst_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_exception_0; // @[mshrs.scala:36:7] wire [63:0] io_resp_bits_uop_exc_cause_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_bypassable_0; // @[mshrs.scala:36:7] wire [4:0] io_resp_bits_uop_mem_cmd_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_mem_size_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_mem_signed_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_fence_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_fencei_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_amo_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_uses_ldq_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_uses_stq_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_sys_pc2epc_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_unique_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_flush_on_commit_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_ldst_is_rs1_0; // @[mshrs.scala:36:7] wire [5:0] io_resp_bits_uop_ldst_0; // @[mshrs.scala:36:7] wire [5:0] io_resp_bits_uop_lrs1_0; // @[mshrs.scala:36:7] wire [5:0] io_resp_bits_uop_lrs2_0; // @[mshrs.scala:36:7] wire [5:0] io_resp_bits_uop_lrs3_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_ldst_val_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_dst_rtype_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_lrs1_rtype_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_lrs2_rtype_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_frs3_en_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fp_val_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fp_single_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_xcpt_pf_if_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_xcpt_ae_if_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_xcpt_ma_if_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_bp_debug_if_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_bp_xcpt_if_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_debug_fsrc_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_debug_tsrc_0; // @[mshrs.scala:36:7] wire [63:0] io_resp_bits_data_0; // @[mshrs.scala:36:7] wire io_resp_bits_is_hella_0; // @[mshrs.scala:36:7] wire io_resp_valid_0; // @[mshrs.scala:36:7] wire io_req_pri_rdy_0; // @[mshrs.scala:36:7] wire io_req_sec_rdy_0; // @[mshrs.scala:36:7] wire io_commit_val_0; // @[mshrs.scala:36:7] wire [39:0] io_commit_addr_0; // @[mshrs.scala:36:7] wire io_probe_rdy_0; // @[mshrs.scala:36:7] reg [4:0] state; // @[mshrs.scala:107:22] reg [6:0] req_uop_uopc; // @[mshrs.scala:109:20] reg [31:0] req_uop_inst; // @[mshrs.scala:109:20] reg [31:0] req_uop_debug_inst; // @[mshrs.scala:109:20] reg req_uop_is_rvc; // @[mshrs.scala:109:20] reg [39:0] req_uop_debug_pc; // @[mshrs.scala:109:20] reg [2:0] req_uop_iq_type; // @[mshrs.scala:109:20] reg [9:0] req_uop_fu_code; // @[mshrs.scala:109:20] reg [3:0] req_uop_ctrl_br_type; // @[mshrs.scala:109:20] reg [1:0] req_uop_ctrl_op1_sel; // @[mshrs.scala:109:20] reg [2:0] req_uop_ctrl_op2_sel; // @[mshrs.scala:109:20] reg [2:0] req_uop_ctrl_imm_sel; // @[mshrs.scala:109:20] reg [4:0] req_uop_ctrl_op_fcn; // @[mshrs.scala:109:20] reg req_uop_ctrl_fcn_dw; // @[mshrs.scala:109:20] reg [2:0] req_uop_ctrl_csr_cmd; // @[mshrs.scala:109:20] reg req_uop_ctrl_is_load; // @[mshrs.scala:109:20] reg req_uop_ctrl_is_sta; // @[mshrs.scala:109:20] reg req_uop_ctrl_is_std; // @[mshrs.scala:109:20] reg [1:0] req_uop_iw_state; // @[mshrs.scala:109:20] reg req_uop_iw_p1_poisoned; // @[mshrs.scala:109:20] reg req_uop_iw_p2_poisoned; // @[mshrs.scala:109:20] reg req_uop_is_br; // @[mshrs.scala:109:20] reg req_uop_is_jalr; // @[mshrs.scala:109:20] reg req_uop_is_jal; // @[mshrs.scala:109:20] reg req_uop_is_sfb; // @[mshrs.scala:109:20] reg [15:0] req_uop_br_mask; // @[mshrs.scala:109:20] reg [3:0] req_uop_br_tag; // @[mshrs.scala:109:20] reg [4:0] req_uop_ftq_idx; // @[mshrs.scala:109:20] reg req_uop_edge_inst; // @[mshrs.scala:109:20] reg [5:0] req_uop_pc_lob; // @[mshrs.scala:109:20] reg req_uop_taken; // @[mshrs.scala:109:20] reg [19:0] req_uop_imm_packed; // @[mshrs.scala:109:20] reg [11:0] req_uop_csr_addr; // @[mshrs.scala:109:20] reg [6:0] req_uop_rob_idx; // @[mshrs.scala:109:20] reg [4:0] req_uop_ldq_idx; // @[mshrs.scala:109:20] reg [4:0] req_uop_stq_idx; // @[mshrs.scala:109:20] reg [1:0] req_uop_rxq_idx; // @[mshrs.scala:109:20] reg [6:0] req_uop_pdst; // @[mshrs.scala:109:20] reg [6:0] req_uop_prs1; // @[mshrs.scala:109:20] reg [6:0] req_uop_prs2; // @[mshrs.scala:109:20] reg [6:0] req_uop_prs3; // @[mshrs.scala:109:20] reg [4:0] req_uop_ppred; // @[mshrs.scala:109:20] reg req_uop_prs1_busy; // @[mshrs.scala:109:20] reg req_uop_prs2_busy; // @[mshrs.scala:109:20] reg req_uop_prs3_busy; // @[mshrs.scala:109:20] reg req_uop_ppred_busy; // @[mshrs.scala:109:20] reg [6:0] req_uop_stale_pdst; // @[mshrs.scala:109:20] reg req_uop_exception; // @[mshrs.scala:109:20] reg [63:0] req_uop_exc_cause; // @[mshrs.scala:109:20] reg req_uop_bypassable; // @[mshrs.scala:109:20] reg [4:0] req_uop_mem_cmd; // @[mshrs.scala:109:20] reg [1:0] req_uop_mem_size; // @[mshrs.scala:109:20] reg req_uop_mem_signed; // @[mshrs.scala:109:20] reg req_uop_is_fence; // @[mshrs.scala:109:20] reg req_uop_is_fencei; // @[mshrs.scala:109:20] reg req_uop_is_amo; // @[mshrs.scala:109:20] reg req_uop_uses_ldq; // @[mshrs.scala:109:20] reg req_uop_uses_stq; // @[mshrs.scala:109:20] reg req_uop_is_sys_pc2epc; // @[mshrs.scala:109:20] reg req_uop_is_unique; // @[mshrs.scala:109:20] reg req_uop_flush_on_commit; // @[mshrs.scala:109:20] reg req_uop_ldst_is_rs1; // @[mshrs.scala:109:20] reg [5:0] req_uop_ldst; // @[mshrs.scala:109:20] reg [5:0] req_uop_lrs1; // @[mshrs.scala:109:20] reg [5:0] req_uop_lrs2; // @[mshrs.scala:109:20] reg [5:0] req_uop_lrs3; // @[mshrs.scala:109:20] reg req_uop_ldst_val; // @[mshrs.scala:109:20] reg [1:0] req_uop_dst_rtype; // @[mshrs.scala:109:20] reg [1:0] req_uop_lrs1_rtype; // @[mshrs.scala:109:20] reg [1:0] req_uop_lrs2_rtype; // @[mshrs.scala:109:20] reg req_uop_frs3_en; // @[mshrs.scala:109:20] reg req_uop_fp_val; // @[mshrs.scala:109:20] reg req_uop_fp_single; // @[mshrs.scala:109:20] reg req_uop_xcpt_pf_if; // @[mshrs.scala:109:20] reg req_uop_xcpt_ae_if; // @[mshrs.scala:109:20] reg req_uop_xcpt_ma_if; // @[mshrs.scala:109:20] reg req_uop_bp_debug_if; // @[mshrs.scala:109:20] reg req_uop_bp_xcpt_if; // @[mshrs.scala:109:20] reg [1:0] req_uop_debug_fsrc; // @[mshrs.scala:109:20] reg [1:0] req_uop_debug_tsrc; // @[mshrs.scala:109:20] reg [39:0] req_addr; // @[mshrs.scala:109:20] assign io_commit_addr_0 = req_addr; // @[mshrs.scala:36:7, :109:20] reg [63:0] req_data; // @[mshrs.scala:109:20] reg req_is_hella; // @[mshrs.scala:109:20] reg req_tag_match; // @[mshrs.scala:109:20] reg [1:0] req_old_meta_coh_state; // @[mshrs.scala:109:20] reg [19:0] req_old_meta_tag; // @[mshrs.scala:109:20] assign io_wb_req_bits_tag_0 = req_old_meta_tag; // @[mshrs.scala:36:7, :109:20] reg [7:0] req_way_en; // @[mshrs.scala:109:20] assign io_way_bits_0 = req_way_en; // @[mshrs.scala:36:7, :109:20] assign io_refill_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20] assign io_meta_write_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20] assign io_meta_read_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20] assign io_wb_req_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20] assign io_replay_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20] reg [4:0] req_sdq_id; // @[mshrs.scala:109:20] assign req_idx = req_addr[11:6]; // @[mshrs.scala:109:20, :110:25] assign io_idx_bits_0 = req_idx; // @[mshrs.scala:36:7, :110:25] assign io_meta_write_bits_idx_0 = req_idx; // @[mshrs.scala:36:7, :110:25] assign io_meta_read_bits_idx_0 = req_idx; // @[mshrs.scala:36:7, :110:25] assign io_wb_req_bits_idx_0 = req_idx; // @[mshrs.scala:36:7, :110:25] assign req_tag = req_addr[39:12]; // @[mshrs.scala:109:20, :111:26] assign io_tag_bits_0 = req_tag; // @[mshrs.scala:36:7, :111:26] wire [33:0] _req_block_addr_T = req_addr[39:6]; // @[mshrs.scala:109:20, :112:34] wire [39:0] req_block_addr = {_req_block_addr_T, 6'h0}; // @[mshrs.scala:112:{34,51}] reg req_needs_wb; // @[mshrs.scala:113:29] reg [1:0] new_coh_state; // @[mshrs.scala:115:24] wire [3:0] _r_T_6 = {2'h2, req_old_meta_coh_state}; // @[Metadata.scala:120:19] wire _r_T_19 = _r_T_6 == 4'h8; // @[Misc.scala:56:20] wire [2:0] _r_T_21 = _r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _r_T_23 = _r_T_6 == 4'h9; // @[Misc.scala:56:20] wire [2:0] _r_T_25 = _r_T_23 ? 3'h2 : _r_T_21; // @[Misc.scala:38:36, :56:20] wire _r_T_27 = _r_T_6 == 4'hA; // @[Misc.scala:56:20] wire [2:0] _r_T_29 = _r_T_27 ? 3'h1 : _r_T_25; // @[Misc.scala:38:36, :56:20] wire _r_T_31 = _r_T_6 == 4'hB; // @[Misc.scala:56:20] wire _r_T_32 = _r_T_31; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_33 = _r_T_31 ? 3'h1 : _r_T_29; // @[Misc.scala:38:36, :56:20] wire _r_T_35 = _r_T_6 == 4'h4; // @[Misc.scala:56:20] wire _r_T_36 = ~_r_T_35 & _r_T_32; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_37 = _r_T_35 ? 3'h5 : _r_T_33; // @[Misc.scala:38:36, :56:20] wire _r_T_39 = _r_T_6 == 4'h5; // @[Misc.scala:56:20] wire _r_T_40 = ~_r_T_39 & _r_T_36; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_41 = _r_T_39 ? 3'h4 : _r_T_37; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_42 = {1'h0, _r_T_39}; // @[Misc.scala:38:63, :56:20] wire _r_T_43 = _r_T_6 == 4'h6; // @[Misc.scala:56:20] wire _r_T_44 = ~_r_T_43 & _r_T_40; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_45 = _r_T_43 ? 3'h0 : _r_T_41; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_46 = _r_T_43 ? 2'h1 : _r_T_42; // @[Misc.scala:38:63, :56:20] wire _r_T_47 = _r_T_6 == 4'h7; // @[Misc.scala:56:20] wire _r_T_48 = _r_T_47 \| _r_T_44; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_49 = _r_T_47 ? 3'h0 : _r_T_45; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_50 = _r_T_47 ? 2'h1 : _r_T_46; // @[Misc.scala:38:63, :56:20] wire _r_T_51 = _r_T_6 == 4'h0; // @[Misc.scala:56:20] wire _r_T_52 = ~_r_T_51 & _r_T_48; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_53 = _r_T_51 ? 3'h5 : _r_T_49; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_54 = _r_T_51 ? 2'h0 : _r_T_50; // @[Misc.scala:38:63, :56:20] wire _r_T_55 = _r_T_6 == 4'h1; // @[Misc.scala:56:20] wire _r_T_56 = ~_r_T_55 & _r_T_52; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_57 = _r_T_55 ? 3'h4 : _r_T_53; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_58 = _r_T_55 ? 2'h1 : _r_T_54; // @[Misc.scala:38:63, :56:20] wire _r_T_59 = _r_T_6 == 4'h2; // @[Misc.scala:56:20] wire _r_T_60 = ~_r_T_59 & _r_T_56; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_61 = _r_T_59 ? 3'h3 : _r_T_57; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_62 = _r_T_59 ? 2'h2 : _r_T_58; // @[Misc.scala:38:63, :56:20] wire _r_T_63 = _r_T_6 == 4'h3; // @[Misc.scala:56:20] wire r_1 = _r_T_63 \| _r_T_60; // @[Misc.scala:38:9, :56:20] assign shrink_param = _r_T_63 ? 3'h3 : _r_T_61; // @[Misc.scala:38:36, :56:20] assign io_wb_req_bits_param_0 = shrink_param; // @[Misc.scala:38:36] wire [1:0] r_3 = _r_T_63 ? 2'h2 : _r_T_62; // @[Misc.scala:38:63, :56:20] wire [1:0] coh_on_clear_state = r_3; // @[Misc.scala:38:63] wire _GEN = req_uop_mem_cmd == 5'h1; // @[Consts.scala:90:32] wire _grow_param_r_c_cat_T; // @[Consts.scala:90:32] assign _grow_param_r_c_cat_T = _GEN; // @[Consts.scala:90:32] wire _grow_param_r_c_cat_T_23; // @[Consts.scala:90:32] assign _grow_param_r_c_cat_T_23 = _GEN; // @[Consts.scala:90:32] wire _coh_on_grant_c_cat_T; // @[Consts.scala:90:32] assign _coh_on_grant_c_cat_T = _GEN; // @[Consts.scala:90:32] wire _coh_on_grant_c_cat_T_23; // @[Consts.scala:90:32] assign _coh_on_grant_c_cat_T_23 = _GEN; // @[Consts.scala:90:32] wire _r1_c_cat_T; // @[Consts.scala:90:32] assign _r1_c_cat_T = _GEN; // @[Consts.scala:90:32] wire _r1_c_cat_T_23; // @[Consts.scala:90:32] assign _r1_c_cat_T_23 = _GEN; // @[Consts.scala:90:32] wire _needs_second_acq_T_27; // @[Consts.scala:90:32] assign _needs_second_acq_T_27 = _GEN; // @[Consts.scala:90:32] wire _GEN_0 = req_uop_mem_cmd == 5'h11; // @[Consts.scala:90:49] wire _grow_param_r_c_cat_T_1; // @[Consts.scala:90:49] assign _grow_param_r_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49] wire _grow_param_r_c_cat_T_24; // @[Consts.scala:90:49] assign _grow_param_r_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49] wire _coh_on_grant_c_cat_T_1; // @[Consts.scala:90:49] assign _coh_on_grant_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49] wire _coh_on_grant_c_cat_T_24; // @[Consts.scala:90:49] assign _coh_on_grant_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49] wire _r1_c_cat_T_1; // @[Consts.scala:90:49] assign _r1_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49] wire _r1_c_cat_T_24; // @[Consts.scala:90:49] assign _r1_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49] wire _needs_second_acq_T_28; // @[Consts.scala:90:49] assign _needs_second_acq_T_28 = _GEN_0; // @[Consts.scala:90:49] wire _grow_param_r_c_cat_T_2 = _grow_param_r_c_cat_T \| _grow_param_r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _GEN_1 = req_uop_mem_cmd == 5'h7; // @[Consts.scala:90:66] wire _grow_param_r_c_cat_T_3; // @[Consts.scala:90:66] assign _grow_param_r_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66] wire _grow_param_r_c_cat_T_26; // @[Consts.scala:90:66] assign _grow_param_r_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66] wire _coh_on_grant_c_cat_T_3; // @[Consts.scala:90:66] assign _coh_on_grant_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66] wire _coh_on_grant_c_cat_T_26; // @[Consts.scala:90:66] assign _coh_on_grant_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66] wire _r1_c_cat_T_3; // @[Consts.scala:90:66] assign _r1_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66] wire _r1_c_cat_T_26; // @[Consts.scala:90:66] assign _r1_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66] wire _needs_second_acq_T_30; // @[Consts.scala:90:66] assign _needs_second_acq_T_30 = _GEN_1; // @[Consts.scala:90:66] wire _grow_param_r_c_cat_T_4 = _grow_param_r_c_cat_T_2 \| _grow_param_r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _GEN_2 = req_uop_mem_cmd == 5'h4; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_5; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_5 = _GEN_2; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_28; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_28 = _GEN_2; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_5; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_5 = _GEN_2; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_28; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_28 = _GEN_2; // @[package.scala:16:47] wire _r1_c_cat_T_5; // @[package.scala:16:47] assign _r1_c_cat_T_5 = _GEN_2; // @[package.scala:16:47] wire _r1_c_cat_T_28; // @[package.scala:16:47] assign _r1_c_cat_T_28 = _GEN_2; // @[package.scala:16:47] wire _needs_second_acq_T_32; // @[package.scala:16:47] assign _needs_second_acq_T_32 = _GEN_2; // @[package.scala:16:47] wire _GEN_3 = req_uop_mem_cmd == 5'h9; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_6; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_6 = _GEN_3; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_29; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_29 = _GEN_3; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_6; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_6 = _GEN_3; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_29; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_29 = _GEN_3; // @[package.scala:16:47] wire _r1_c_cat_T_6; // @[package.scala:16:47] assign _r1_c_cat_T_6 = _GEN_3; // @[package.scala:16:47] wire _r1_c_cat_T_29; // @[package.scala:16:47] assign _r1_c_cat_T_29 = _GEN_3; // @[package.scala:16:47] wire _needs_second_acq_T_33; // @[package.scala:16:47] assign _needs_second_acq_T_33 = _GEN_3; // @[package.scala:16:47] wire _GEN_4 = req_uop_mem_cmd == 5'hA; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_7; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_7 = _GEN_4; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_30; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_30 = _GEN_4; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_7; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_7 = _GEN_4; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_30; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_30 = _GEN_4; // @[package.scala:16:47] wire _r1_c_cat_T_7; // @[package.scala:16:47] assign _r1_c_cat_T_7 = _GEN_4; // @[package.scala:16:47] wire _r1_c_cat_T_30; // @[package.scala:16:47] assign _r1_c_cat_T_30 = _GEN_4; // @[package.scala:16:47] wire _needs_second_acq_T_34; // @[package.scala:16:47] assign _needs_second_acq_T_34 = _GEN_4; // @[package.scala:16:47] wire _GEN_5 = req_uop_mem_cmd == 5'hB; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_8; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_8 = _GEN_5; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_31; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_31 = _GEN_5; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_8; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_8 = _GEN_5; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_31; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_31 = _GEN_5; // @[package.scala:16:47] wire _r1_c_cat_T_8; // @[package.scala:16:47] assign _r1_c_cat_T_8 = _GEN_5; // @[package.scala:16:47] wire _r1_c_cat_T_31; // @[package.scala:16:47] assign _r1_c_cat_T_31 = _GEN_5; // @[package.scala:16:47] wire _needs_second_acq_T_35; // @[package.scala:16:47] assign _needs_second_acq_T_35 = _GEN_5; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_9 = _grow_param_r_c_cat_T_5 \| _grow_param_r_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_10 = _grow_param_r_c_cat_T_9 \| _grow_param_r_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_11 = _grow_param_r_c_cat_T_10 \| _grow_param_r_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _GEN_6 = req_uop_mem_cmd == 5'h8; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_12; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_12 = _GEN_6; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_35; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_35 = _GEN_6; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_12; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_12 = _GEN_6; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_35; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_35 = _GEN_6; // @[package.scala:16:47] wire _r1_c_cat_T_12; // @[package.scala:16:47] assign _r1_c_cat_T_12 = _GEN_6; // @[package.scala:16:47] wire _r1_c_cat_T_35; // @[package.scala:16:47] assign _r1_c_cat_T_35 = _GEN_6; // @[package.scala:16:47] wire _needs_second_acq_T_39; // @[package.scala:16:47] assign _needs_second_acq_T_39 = _GEN_6; // @[package.scala:16:47] wire _GEN_7 = req_uop_mem_cmd == 5'hC; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_13; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_13 = _GEN_7; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_36; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_36 = _GEN_7; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_13; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_13 = _GEN_7; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_36; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_36 = _GEN_7; // @[package.scala:16:47] wire _r1_c_cat_T_13; // @[package.scala:16:47] assign _r1_c_cat_T_13 = _GEN_7; // @[package.scala:16:47] wire _r1_c_cat_T_36; // @[package.scala:16:47] assign _r1_c_cat_T_36 = _GEN_7; // @[package.scala:16:47] wire _needs_second_acq_T_40; // @[package.scala:16:47] assign _needs_second_acq_T_40 = _GEN_7; // @[package.scala:16:47] wire _GEN_8 = req_uop_mem_cmd == 5'hD; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_14; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_14 = _GEN_8; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_37; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_37 = _GEN_8; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_14; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_14 = _GEN_8; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_37; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_37 = _GEN_8; // @[package.scala:16:47] wire _r1_c_cat_T_14; // @[package.scala:16:47] assign _r1_c_cat_T_14 = _GEN_8; // @[package.scala:16:47] wire _r1_c_cat_T_37; // @[package.scala:16:47] assign _r1_c_cat_T_37 = _GEN_8; // @[package.scala:16:47] wire _needs_second_acq_T_41; // @[package.scala:16:47] assign _needs_second_acq_T_41 = _GEN_8; // @[package.scala:16:47] wire _GEN_9 = req_uop_mem_cmd == 5'hE; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_15; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_15 = _GEN_9; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_38; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_38 = _GEN_9; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_15; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_15 = _GEN_9; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_38; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_38 = _GEN_9; // @[package.scala:16:47] wire _r1_c_cat_T_15; // @[package.scala:16:47] assign _r1_c_cat_T_15 = _GEN_9; // @[package.scala:16:47] wire _r1_c_cat_T_38; // @[package.scala:16:47] assign _r1_c_cat_T_38 = _GEN_9; // @[package.scala:16:47] wire _needs_second_acq_T_42; // @[package.scala:16:47] assign _needs_second_acq_T_42 = _GEN_9; // @[package.scala:16:47] wire _GEN_10 = req_uop_mem_cmd == 5'hF; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_16; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_16 = _GEN_10; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_39; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_39 = _GEN_10; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_16; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_16 = _GEN_10; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_39; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_39 = _GEN_10; // @[package.scala:16:47] wire _r1_c_cat_T_16; // @[package.scala:16:47] assign _r1_c_cat_T_16 = _GEN_10; // @[package.scala:16:47] wire _r1_c_cat_T_39; // @[package.scala:16:47] assign _r1_c_cat_T_39 = _GEN_10; // @[package.scala:16:47] wire _needs_second_acq_T_43; // @[package.scala:16:47] assign _needs_second_acq_T_43 = _GEN_10; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_17 = _grow_param_r_c_cat_T_12 \| _grow_param_r_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_18 = _grow_param_r_c_cat_T_17 \| _grow_param_r_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_19 = _grow_param_r_c_cat_T_18 \| _grow_param_r_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_20 = _grow_param_r_c_cat_T_19 \| _grow_param_r_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_21 = _grow_param_r_c_cat_T_11 \| _grow_param_r_c_cat_T_20; // @[package.scala:81:59] wire _grow_param_r_c_cat_T_22 = _grow_param_r_c_cat_T_4 \| _grow_param_r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _grow_param_r_c_cat_T_25 = _grow_param_r_c_cat_T_23 \| _grow_param_r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _grow_param_r_c_cat_T_27 = _grow_param_r_c_cat_T_25 \| _grow_param_r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _grow_param_r_c_cat_T_32 = _grow_param_r_c_cat_T_28 \| _grow_param_r_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_33 = _grow_param_r_c_cat_T_32 \| _grow_param_r_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_34 = _grow_param_r_c_cat_T_33 \| _grow_param_r_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_40 = _grow_param_r_c_cat_T_35 \| _grow_param_r_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_41 = _grow_param_r_c_cat_T_40 \| _grow_param_r_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_42 = _grow_param_r_c_cat_T_41 \| _grow_param_r_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_43 = _grow_param_r_c_cat_T_42 \| _grow_param_r_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_44 = _grow_param_r_c_cat_T_34 \| _grow_param_r_c_cat_T_43; // @[package.scala:81:59] wire _grow_param_r_c_cat_T_45 = _grow_param_r_c_cat_T_27 \| _grow_param_r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _GEN_11 = req_uop_mem_cmd == 5'h3; // @[Consts.scala:91:54] wire _grow_param_r_c_cat_T_46; // @[Consts.scala:91:54] assign _grow_param_r_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54] wire _coh_on_grant_c_cat_T_46; // @[Consts.scala:91:54] assign _coh_on_grant_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54] wire _r1_c_cat_T_46; // @[Consts.scala:91:54] assign _r1_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54] wire _needs_second_acq_T_50; // @[Consts.scala:91:54] assign _needs_second_acq_T_50 = _GEN_11; // @[Consts.scala:91:54] wire _grow_param_r_c_cat_T_47 = _grow_param_r_c_cat_T_45 \| _grow_param_r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _GEN_12 = req_uop_mem_cmd == 5'h6; // @[Consts.scala:91:71] wire _grow_param_r_c_cat_T_48; // @[Consts.scala:91:71] assign _grow_param_r_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71] wire _coh_on_grant_c_cat_T_48; // @[Consts.scala:91:71] assign _coh_on_grant_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71] wire _r1_c_cat_T_48; // @[Consts.scala:91:71] assign _r1_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71] wire _needs_second_acq_T_52; // @[Consts.scala:91:71] assign _needs_second_acq_T_52 = _GEN_12; // @[Consts.scala:91:71] wire _grow_param_r_c_cat_T_49 = _grow_param_r_c_cat_T_47 \| _grow_param_r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] grow_param_r_c = {_grow_param_r_c_cat_T_22, _grow_param_r_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _grow_param_r_T = {grow_param_r_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19] wire _grow_param_r_T_25 = _grow_param_r_T == 4'hC; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_27 = {1'h0, _grow_param_r_T_25}; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_28 = _grow_param_r_T == 4'hD; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_30 = _grow_param_r_T_28 ? 2'h2 : _grow_param_r_T_27; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_31 = _grow_param_r_T == 4'h4; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_33 = _grow_param_r_T_31 ? 2'h1 : _grow_param_r_T_30; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_34 = _grow_param_r_T == 4'h5; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_36 = _grow_param_r_T_34 ? 2'h2 : _grow_param_r_T_33; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_37 = _grow_param_r_T == 4'h0; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_39 = _grow_param_r_T_37 ? 2'h0 : _grow_param_r_T_36; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_40 = _grow_param_r_T == 4'hE; // @[Misc.scala:49:20] wire _grow_param_r_T_41 = _grow_param_r_T_40; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_42 = _grow_param_r_T_40 ? 2'h3 : _grow_param_r_T_39; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_43 = &_grow_param_r_T; // @[Misc.scala:49:20] wire _grow_param_r_T_44 = _grow_param_r_T_43 \| _grow_param_r_T_41; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_45 = _grow_param_r_T_43 ? 2'h3 : _grow_param_r_T_42; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_46 = _grow_param_r_T == 4'h6; // @[Misc.scala:49:20] wire _grow_param_r_T_47 = _grow_param_r_T_46 \| _grow_param_r_T_44; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_48 = _grow_param_r_T_46 ? 2'h2 : _grow_param_r_T_45; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_49 = _grow_param_r_T == 4'h7; // @[Misc.scala:49:20] wire _grow_param_r_T_50 = _grow_param_r_T_49 \| _grow_param_r_T_47; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_51 = _grow_param_r_T_49 ? 2'h3 : _grow_param_r_T_48; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_52 = _grow_param_r_T == 4'h1; // @[Misc.scala:49:20] wire _grow_param_r_T_53 = _grow_param_r_T_52 \| _grow_param_r_T_50; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_54 = _grow_param_r_T_52 ? 2'h1 : _grow_param_r_T_51; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_55 = _grow_param_r_T == 4'h2; // @[Misc.scala:49:20] wire _grow_param_r_T_56 = _grow_param_r_T_55 \| _grow_param_r_T_53; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_57 = _grow_param_r_T_55 ? 2'h2 : _grow_param_r_T_54; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_58 = _grow_param_r_T == 4'h3; // @[Misc.scala:49:20] wire grow_param_r_1 = _grow_param_r_T_58 \| _grow_param_r_T_56; // @[Misc.scala:35:9, :49:20] wire [1:0] grow_param = _grow_param_r_T_58 ? 2'h3 : _grow_param_r_T_57; // @[Misc.scala:35:36, :49:20] wire [1:0] grow_param_meta_state = grow_param; // @[Misc.scala:35:36] wire _coh_on_grant_c_cat_T_2 = _coh_on_grant_c_cat_T \| _coh_on_grant_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _coh_on_grant_c_cat_T_4 = _coh_on_grant_c_cat_T_2 \| _coh_on_grant_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _coh_on_grant_c_cat_T_9 = _coh_on_grant_c_cat_T_5 \| _coh_on_grant_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_10 = _coh_on_grant_c_cat_T_9 \| _coh_on_grant_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_11 = _coh_on_grant_c_cat_T_10 \| _coh_on_grant_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_17 = _coh_on_grant_c_cat_T_12 \| _coh_on_grant_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_18 = _coh_on_grant_c_cat_T_17 \| _coh_on_grant_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_19 = _coh_on_grant_c_cat_T_18 \| _coh_on_grant_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_20 = _coh_on_grant_c_cat_T_19 \| _coh_on_grant_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_21 = _coh_on_grant_c_cat_T_11 \| _coh_on_grant_c_cat_T_20; // @[package.scala:81:59] wire _coh_on_grant_c_cat_T_22 = _coh_on_grant_c_cat_T_4 \| _coh_on_grant_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _coh_on_grant_c_cat_T_25 = _coh_on_grant_c_cat_T_23 \| _coh_on_grant_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _coh_on_grant_c_cat_T_27 = _coh_on_grant_c_cat_T_25 \| _coh_on_grant_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _coh_on_grant_c_cat_T_32 = _coh_on_grant_c_cat_T_28 \| _coh_on_grant_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_33 = _coh_on_grant_c_cat_T_32 \| _coh_on_grant_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_34 = _coh_on_grant_c_cat_T_33 \| _coh_on_grant_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_40 = _coh_on_grant_c_cat_T_35 \| _coh_on_grant_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_41 = _coh_on_grant_c_cat_T_40 \| _coh_on_grant_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_42 = _coh_on_grant_c_cat_T_41 \| _coh_on_grant_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_43 = _coh_on_grant_c_cat_T_42 \| _coh_on_grant_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_44 = _coh_on_grant_c_cat_T_34 \| _coh_on_grant_c_cat_T_43; // @[package.scala:81:59] wire _coh_on_grant_c_cat_T_45 = _coh_on_grant_c_cat_T_27 \| _coh_on_grant_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _coh_on_grant_c_cat_T_47 = _coh_on_grant_c_cat_T_45 \| _coh_on_grant_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _coh_on_grant_c_cat_T_49 = _coh_on_grant_c_cat_T_47 \| _coh_on_grant_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] coh_on_grant_c = {_coh_on_grant_c_cat_T_22, _coh_on_grant_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _coh_on_grant_T = {coh_on_grant_c, io_mem_grant_bits_param_0}; // @[Metadata.scala:29:18, :84:18] wire _coh_on_grant_T_9 = _coh_on_grant_T == 4'h1; // @[Metadata.scala:84:{18,38}] wire [1:0] _coh_on_grant_T_10 = {1'h0, _coh_on_grant_T_9}; // @[Metadata.scala:84:38] wire _coh_on_grant_T_11 = _coh_on_grant_T == 4'h0; // @[Metadata.scala:84:{18,38}] wire [1:0] _coh_on_grant_T_12 = _coh_on_grant_T_11 ? 2'h2 : _coh_on_grant_T_10; // @[Metadata.scala:84:38] wire _coh_on_grant_T_13 = _coh_on_grant_T == 4'h4; // @[Metadata.scala:84:{18,38}] wire [1:0] _coh_on_grant_T_14 = _coh_on_grant_T_13 ? 2'h2 : _coh_on_grant_T_12; // @[Metadata.scala:84:38] wire _coh_on_grant_T_15 = _coh_on_grant_T == 4'hC; // @[Metadata.scala:84:{18,38}] wire [1:0] _coh_on_grant_T_16 = _coh_on_grant_T_15 ? 2'h3 : _coh_on_grant_T_14; // @[Metadata.scala:84:38] assign coh_on_grant_state = _coh_on_grant_T_16; // @[Metadata.scala:84:38, :160:20] assign io_commit_coh_state_0 = coh_on_grant_state; // @[Metadata.scala:160:20] wire _r1_c_cat_T_2 = _r1_c_cat_T \| _r1_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _r1_c_cat_T_4 = _r1_c_cat_T_2 \| _r1_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _r1_c_cat_T_9 = _r1_c_cat_T_5 \| _r1_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_10 = _r1_c_cat_T_9 \| _r1_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_11 = _r1_c_cat_T_10 \| _r1_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_17 = _r1_c_cat_T_12 \| _r1_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_18 = _r1_c_cat_T_17 \| _r1_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_19 = _r1_c_cat_T_18 \| _r1_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_20 = _r1_c_cat_T_19 \| _r1_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_21 = _r1_c_cat_T_11 \| _r1_c_cat_T_20; // @[package.scala:81:59] wire _r1_c_cat_T_22 = _r1_c_cat_T_4 \| _r1_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _r1_c_cat_T_25 = _r1_c_cat_T_23 \| _r1_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _r1_c_cat_T_27 = _r1_c_cat_T_25 \| _r1_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _r1_c_cat_T_32 = _r1_c_cat_T_28 \| _r1_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_33 = _r1_c_cat_T_32 \| _r1_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_34 = _r1_c_cat_T_33 \| _r1_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_40 = _r1_c_cat_T_35 \| _r1_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_41 = _r1_c_cat_T_40 \| _r1_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_42 = _r1_c_cat_T_41 \| _r1_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_43 = _r1_c_cat_T_42 \| _r1_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_44 = _r1_c_cat_T_34 \| _r1_c_cat_T_43; // @[package.scala:81:59] wire _r1_c_cat_T_45 = _r1_c_cat_T_27 \| _r1_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _r1_c_cat_T_47 = _r1_c_cat_T_45 \| _r1_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _r1_c_cat_T_49 = _r1_c_cat_T_47 \| _r1_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] r1_c = {_r1_c_cat_T_22, _r1_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _r1_T = {r1_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19] wire _r1_T_25 = _r1_T == 4'hC; // @[Misc.scala:49:20] wire [1:0] _r1_T_27 = {1'h0, _r1_T_25}; // @[Misc.scala:35:36, :49:20] wire _r1_T_28 = _r1_T == 4'hD; // @[Misc.scala:49:20] wire [1:0] _r1_T_30 = _r1_T_28 ? 2'h2 : _r1_T_27; // @[Misc.scala:35:36, :49:20] wire _r1_T_31 = _r1_T == 4'h4; // @[Misc.scala:49:20] wire [1:0] _r1_T_33 = _r1_T_31 ? 2'h1 : _r1_T_30; // @[Misc.scala:35:36, :49:20] wire _r1_T_34 = _r1_T == 4'h5; // @[Misc.scala:49:20] wire [1:0] _r1_T_36 = _r1_T_34 ? 2'h2 : _r1_T_33; // @[Misc.scala:35:36, :49:20] wire _r1_T_37 = _r1_T == 4'h0; // @[Misc.scala:49:20] wire [1:0] _r1_T_39 = _r1_T_37 ? 2'h0 : _r1_T_36; // @[Misc.scala:35:36, :49:20] wire _r1_T_40 = _r1_T == 4'hE; // @[Misc.scala:49:20] wire _r1_T_41 = _r1_T_40; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_42 = _r1_T_40 ? 2'h3 : _r1_T_39; // @[Misc.scala:35:36, :49:20] wire _r1_T_43 = &_r1_T; // @[Misc.scala:49:20] wire _r1_T_44 = _r1_T_43 \| _r1_T_41; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_45 = _r1_T_43 ? 2'h3 : _r1_T_42; // @[Misc.scala:35:36, :49:20] wire _r1_T_46 = _r1_T == 4'h6; // @[Misc.scala:49:20] wire _r1_T_47 = _r1_T_46 \| _r1_T_44; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_48 = _r1_T_46 ? 2'h2 : _r1_T_45; // @[Misc.scala:35:36, :49:20] wire _r1_T_49 = _r1_T == 4'h7; // @[Misc.scala:49:20] wire _r1_T_50 = _r1_T_49 \| _r1_T_47; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_51 = _r1_T_49 ? 2'h3 : _r1_T_48; // @[Misc.scala:35:36, :49:20] wire _r1_T_52 = _r1_T == 4'h1; // @[Misc.scala:49:20] wire _r1_T_53 = _r1_T_52 \| _r1_T_50; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_54 = _r1_T_52 ? 2'h1 : _r1_T_51; // @[Misc.scala:35:36, :49:20] wire _r1_T_55 = _r1_T == 4'h2; // @[Misc.scala:49:20] wire _r1_T_56 = _r1_T_55 \| _r1_T_53; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_57 = _r1_T_55 ? 2'h2 : _r1_T_54; // @[Misc.scala:35:36, :49:20] wire _r1_T_58 = _r1_T == 4'h3; // @[Misc.scala:49:20] wire r1_1 = _r1_T_58 \| _r1_T_56; // @[Misc.scala:35:9, :49:20] wire [1:0] r1_2 = _r1_T_58 ? 2'h3 : _r1_T_57; // @[Misc.scala:35:36, :49:20] wire _GEN_13 = io_req_uop_mem_cmd_0 == 5'h1; // @[Consts.scala:90:32] wire _r2_c_cat_T; // @[Consts.scala:90:32] assign _r2_c_cat_T = _GEN_13; // @[Consts.scala:90:32] wire _r2_c_cat_T_23; // @[Consts.scala:90:32] assign _r2_c_cat_T_23 = _GEN_13; // @[Consts.scala:90:32] wire _needs_second_acq_T; // @[Consts.scala:90:32] assign _needs_second_acq_T = _GEN_13; // @[Consts.scala:90:32] wire _dirties_cat_T; // @[Consts.scala:90:32] assign _dirties_cat_T = _GEN_13; // @[Consts.scala:90:32] wire _dirties_cat_T_23; // @[Consts.scala:90:32] assign _dirties_cat_T_23 = _GEN_13; // @[Consts.scala:90:32] wire _state_r_c_cat_T; // @[Consts.scala:90:32] assign _state_r_c_cat_T = _GEN_13; // @[Consts.scala:90:32] wire _state_r_c_cat_T_23; // @[Consts.scala:90:32] assign _state_r_c_cat_T_23 = _GEN_13; // @[Consts.scala:90:32] wire _state_T_3; // @[Consts.scala:90:32] assign _state_T_3 = _GEN_13; // @[Consts.scala:90:32] wire _r_c_cat_T_50; // @[Consts.scala:90:32] assign _r_c_cat_T_50 = _GEN_13; // @[Consts.scala:90:32] wire _r_c_cat_T_73; // @[Consts.scala:90:32] assign _r_c_cat_T_73 = _GEN_13; // @[Consts.scala:90:32] wire _state_r_c_cat_T_50; // @[Consts.scala:90:32] assign _state_r_c_cat_T_50 = _GEN_13; // @[Consts.scala:90:32] wire _state_r_c_cat_T_73; // @[Consts.scala:90:32] assign _state_r_c_cat_T_73 = _GEN_13; // @[Consts.scala:90:32] wire _state_T_37; // @[Consts.scala:90:32] assign _state_T_37 = _GEN_13; // @[Consts.scala:90:32] wire _GEN_14 = io_req_uop_mem_cmd_0 == 5'h11; // @[Consts.scala:90:49] wire _r2_c_cat_T_1; // @[Consts.scala:90:49] assign _r2_c_cat_T_1 = _GEN_14; // @[Consts.scala:90:49] wire _r2_c_cat_T_24; // @[Consts.scala:90:49] assign _r2_c_cat_T_24 = _GEN_14; // @[Consts.scala:90:49] wire _needs_second_acq_T_1; // @[Consts.scala:90:49] assign _needs_second_acq_T_1 = _GEN_14; // @[Consts.scala:90:49] wire _dirties_cat_T_1; // @[Consts.scala:90:49] assign _dirties_cat_T_1 = _GEN_14; // @[Consts.scala:90:49] wire _dirties_cat_T_24; // @[Consts.scala:90:49] assign _dirties_cat_T_24 = _GEN_14; // @[Consts.scala:90:49] wire _state_r_c_cat_T_1; // @[Consts.scala:90:49] assign _state_r_c_cat_T_1 = _GEN_14; // @[Consts.scala:90:49] wire _state_r_c_cat_T_24; // @[Consts.scala:90:49] assign _state_r_c_cat_T_24 = _GEN_14; // @[Consts.scala:90:49] wire _state_T_4; // @[Consts.scala:90:49] assign _state_T_4 = _GEN_14; // @[Consts.scala:90:49] wire _r_c_cat_T_51; // @[Consts.scala:90:49] assign _r_c_cat_T_51 = _GEN_14; // @[Consts.scala:90:49] wire _r_c_cat_T_74; // @[Consts.scala:90:49] assign _r_c_cat_T_74 = _GEN_14; // @[Consts.scala:90:49] wire _state_r_c_cat_T_51; // @[Consts.scala:90:49] assign _state_r_c_cat_T_51 = _GEN_14; // @[Consts.scala:90:49] wire _state_r_c_cat_T_74; // @[Consts.scala:90:49] assign _state_r_c_cat_T_74 = _GEN_14; // @[Consts.scala:90:49] wire _state_T_38; // @[Consts.scala:90:49] assign _state_T_38 = _GEN_14; // @[Consts.scala:90:49] wire _r2_c_cat_T_2 = _r2_c_cat_T \| _r2_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _GEN_15 = io_req_uop_mem_cmd_0 == 5'h7; // @[Consts.scala:90:66] wire _r2_c_cat_T_3; // @[Consts.scala:90:66] assign _r2_c_cat_T_3 = _GEN_15; // @[Consts.scala:90:66] wire _r2_c_cat_T_26; // @[Consts.scala:90:66] assign _r2_c_cat_T_26 = _GEN_15; // @[Consts.scala:90:66] wire _needs_second_acq_T_3; // @[Consts.scala:90:66] assign _needs_second_acq_T_3 = _GEN_15; // @[Consts.scala:90:66] wire _dirties_cat_T_3; // @[Consts.scala:90:66] assign _dirties_cat_T_3 = _GEN_15; // @[Consts.scala:90:66] wire _dirties_cat_T_26; // @[Consts.scala:90:66] assign _dirties_cat_T_26 = _GEN_15; // @[Consts.scala:90:66] wire _state_r_c_cat_T_3; // @[Consts.scala:90:66] assign _state_r_c_cat_T_3 = _GEN_15; // @[Consts.scala:90:66] wire _state_r_c_cat_T_26; // @[Consts.scala:90:66] assign _state_r_c_cat_T_26 = _GEN_15; // @[Consts.scala:90:66] wire _state_T_6; // @[Consts.scala:90:66] assign _state_T_6 = _GEN_15; // @[Consts.scala:90:66] wire _r_c_cat_T_53; // @[Consts.scala:90:66] assign _r_c_cat_T_53 = _GEN_15; // @[Consts.scala:90:66] wire _r_c_cat_T_76; // @[Consts.scala:90:66] assign _r_c_cat_T_76 = _GEN_15; // @[Consts.scala:90:66] wire _state_r_c_cat_T_53; // @[Consts.scala:90:66] assign _state_r_c_cat_T_53 = _GEN_15; // @[Consts.scala:90:66] wire _state_r_c_cat_T_76; // @[Consts.scala:90:66] assign _state_r_c_cat_T_76 = _GEN_15; // @[Consts.scala:90:66] wire _state_T_40; // @[Consts.scala:90:66] assign _state_T_40 = _GEN_15; // @[Consts.scala:90:66] wire _r2_c_cat_T_4 = _r2_c_cat_T_2 \| _r2_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _GEN_16 = io_req_uop_mem_cmd_0 == 5'h4; // @[package.scala:16:47] wire _r2_c_cat_T_5; // @[package.scala:16:47] assign _r2_c_cat_T_5 = _GEN_16; // @[package.scala:16:47] wire _r2_c_cat_T_28; // @[package.scala:16:47] assign _r2_c_cat_T_28 = _GEN_16; // @[package.scala:16:47] wire _needs_second_acq_T_5; // @[package.scala:16:47] assign _needs_second_acq_T_5 = _GEN_16; // @[package.scala:16:47] wire _dirties_cat_T_5; // @[package.scala:16:47] assign _dirties_cat_T_5 = _GEN_16; // @[package.scala:16:47] wire _dirties_cat_T_28; // @[package.scala:16:47] assign _dirties_cat_T_28 = _GEN_16; // @[package.scala:16:47] wire _state_r_c_cat_T_5; // @[package.scala:16:47] assign _state_r_c_cat_T_5 = _GEN_16; // @[package.scala:16:47] wire _state_r_c_cat_T_28; // @[package.scala:16:47] assign _state_r_c_cat_T_28 = _GEN_16; // @[package.scala:16:47] wire _state_T_8; // @[package.scala:16:47] assign _state_T_8 = _GEN_16; // @[package.scala:16:47] wire _r_c_cat_T_55; // @[package.scala:16:47] assign _r_c_cat_T_55 = _GEN_16; // @[package.scala:16:47] wire _r_c_cat_T_78; // @[package.scala:16:47] assign _r_c_cat_T_78 = _GEN_16; // @[package.scala:16:47] wire _state_r_c_cat_T_55; // @[package.scala:16:47] assign _state_r_c_cat_T_55 = _GEN_16; // @[package.scala:16:47] wire _state_r_c_cat_T_78; // @[package.scala:16:47] assign _state_r_c_cat_T_78 = _GEN_16; // @[package.scala:16:47] wire _state_T_42; // @[package.scala:16:47] assign _state_T_42 = _GEN_16; // @[package.scala:16:47] wire _GEN_17 = io_req_uop_mem_cmd_0 == 5'h9; // @[package.scala:16:47] wire _r2_c_cat_T_6; // @[package.scala:16:47] assign _r2_c_cat_T_6 = _GEN_17; // @[package.scala:16:47] wire _r2_c_cat_T_29; // @[package.scala:16:47] assign _r2_c_cat_T_29 = _GEN_17; // @[package.scala:16:47] wire _needs_second_acq_T_6; // @[package.scala:16:47] assign _needs_second_acq_T_6 = _GEN_17; // @[package.scala:16:47] wire _dirties_cat_T_6; // @[package.scala:16:47] assign _dirties_cat_T_6 = _GEN_17; // @[package.scala:16:47] wire _dirties_cat_T_29; // @[package.scala:16:47] assign _dirties_cat_T_29 = _GEN_17; // @[package.scala:16:47] wire _state_r_c_cat_T_6; // @[package.scala:16:47] assign _state_r_c_cat_T_6 = _GEN_17; // @[package.scala:16:47] wire _state_r_c_cat_T_29; // @[package.scala:16:47] assign _state_r_c_cat_T_29 = _GEN_17; // @[package.scala:16:47] wire _state_T_9; // @[package.scala:16:47] assign _state_T_9 = _GEN_17; // @[package.scala:16:47] wire _r_c_cat_T_56; // @[package.scala:16:47] assign _r_c_cat_T_56 = _GEN_17; // @[package.scala:16:47] wire _r_c_cat_T_79; // @[package.scala:16:47] assign _r_c_cat_T_79 = _GEN_17; // @[package.scala:16:47] wire _state_r_c_cat_T_56; // @[package.scala:16:47] assign _state_r_c_cat_T_56 = _GEN_17; // @[package.scala:16:47] wire _state_r_c_cat_T_79; // @[package.scala:16:47] assign _state_r_c_cat_T_79 = _GEN_17; // @[package.scala:16:47] wire _state_T_43; // @[package.scala:16:47] assign _state_T_43 = _GEN_17; // @[package.scala:16:47] wire _GEN_18 = io_req_uop_mem_cmd_0 == 5'hA; // @[package.scala:16:47] wire _r2_c_cat_T_7; // @[package.scala:16:47] assign _r2_c_cat_T_7 = _GEN_18; // @[package.scala:16:47] wire _r2_c_cat_T_30; // @[package.scala:16:47] assign _r2_c_cat_T_30 = _GEN_18; // @[package.scala:16:47] wire _needs_second_acq_T_7; // @[package.scala:16:47] assign _needs_second_acq_T_7 = _GEN_18; // @[package.scala:16:47] wire _dirties_cat_T_7; // @[package.scala:16:47] assign _dirties_cat_T_7 = _GEN_18; // @[package.scala:16:47] wire _dirties_cat_T_30; // @[package.scala:16:47] assign _dirties_cat_T_30 = _GEN_18; // @[package.scala:16:47] wire _state_r_c_cat_T_7; // @[package.scala:16:47] assign _state_r_c_cat_T_7 = _GEN_18; // @[package.scala:16:47] wire _state_r_c_cat_T_30; // @[package.scala:16:47] assign _state_r_c_cat_T_30 = _GEN_18; // @[package.scala:16:47] wire _state_T_10; // @[package.scala:16:47] assign _state_T_10 = _GEN_18; // @[package.scala:16:47] wire _r_c_cat_T_57; // @[package.scala:16:47] assign _r_c_cat_T_57 = _GEN_18; // @[package.scala:16:47] wire _r_c_cat_T_80; // @[package.scala:16:47] assign _r_c_cat_T_80 = _GEN_18; // @[package.scala:16:47] wire _state_r_c_cat_T_57; // @[package.scala:16:47] assign _state_r_c_cat_T_57 = _GEN_18; // @[package.scala:16:47] wire _state_r_c_cat_T_80; // @[package.scala:16:47] assign _state_r_c_cat_T_80 = _GEN_18; // @[package.scala:16:47] wire _state_T_44; // @[package.scala:16:47] assign _state_T_44 = _GEN_18; // @[package.scala:16:47] wire _GEN_19 = io_req_uop_mem_cmd_0 == 5'hB; // @[package.scala:16:47] wire _r2_c_cat_T_8; // @[package.scala:16:47] assign _r2_c_cat_T_8 = _GEN_19; // @[package.scala:16:47] wire _r2_c_cat_T_31; // @[package.scala:16:47] assign _r2_c_cat_T_31 = _GEN_19; // @[package.scala:16:47] wire _needs_second_acq_T_8; // @[package.scala:16:47] assign _needs_second_acq_T_8 = _GEN_19; // @[package.scala:16:47] wire _dirties_cat_T_8; // @[package.scala:16:47] assign _dirties_cat_T_8 = _GEN_19; // @[package.scala:16:47] wire _dirties_cat_T_31; // @[package.scala:16:47] assign _dirties_cat_T_31 = _GEN_19; // @[package.scala:16:47] wire _state_r_c_cat_T_8; // @[package.scala:16:47] assign _state_r_c_cat_T_8 = _GEN_19; // @[package.scala:16:47] wire _state_r_c_cat_T_31; // @[package.scala:16:47] assign _state_r_c_cat_T_31 = _GEN_19; // @[package.scala:16:47] wire _state_T_11; // @[package.scala:16:47] assign _state_T_11 = _GEN_19; // @[package.scala:16:47] wire _r_c_cat_T_58; // @[package.scala:16:47] assign _r_c_cat_T_58 = _GEN_19; // @[package.scala:16:47] wire _r_c_cat_T_81; // @[package.scala:16:47] assign _r_c_cat_T_81 = _GEN_19; // @[package.scala:16:47] wire _state_r_c_cat_T_58; // @[package.scala:16:47] assign _state_r_c_cat_T_58 = _GEN_19; // @[package.scala:16:47] wire _state_r_c_cat_T_81; // @[package.scala:16:47] assign _state_r_c_cat_T_81 = _GEN_19; // @[package.scala:16:47] wire _state_T_45; // @[package.scala:16:47] assign _state_T_45 = _GEN_19; // @[package.scala:16:47] wire _r2_c_cat_T_9 = _r2_c_cat_T_5 \| _r2_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_10 = _r2_c_cat_T_9 \| _r2_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_11 = _r2_c_cat_T_10 \| _r2_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _GEN_20 = io_req_uop_mem_cmd_0 == 5'h8; // @[package.scala:16:47] wire _r2_c_cat_T_12; // @[package.scala:16:47] assign _r2_c_cat_T_12 = _GEN_20; // @[package.scala:16:47] wire _r2_c_cat_T_35; // @[package.scala:16:47] assign _r2_c_cat_T_35 = _GEN_20; // @[package.scala:16:47] wire _needs_second_acq_T_12; // @[package.scala:16:47] assign _needs_second_acq_T_12 = _GEN_20; // @[package.scala:16:47] wire _dirties_cat_T_12; // @[package.scala:16:47] assign _dirties_cat_T_12 = _GEN_20; // @[package.scala:16:47] wire _dirties_cat_T_35; // @[package.scala:16:47] assign _dirties_cat_T_35 = _GEN_20; // @[package.scala:16:47] wire _state_r_c_cat_T_12; // @[package.scala:16:47] assign _state_r_c_cat_T_12 = _GEN_20; // @[package.scala:16:47] wire _state_r_c_cat_T_35; // @[package.scala:16:47] assign _state_r_c_cat_T_35 = _GEN_20; // @[package.scala:16:47] wire _state_T_15; // @[package.scala:16:47] assign _state_T_15 = _GEN_20; // @[package.scala:16:47] wire _r_c_cat_T_62; // @[package.scala:16:47] assign _r_c_cat_T_62 = _GEN_20; // @[package.scala:16:47] wire _r_c_cat_T_85; // @[package.scala:16:47] assign _r_c_cat_T_85 = _GEN_20; // @[package.scala:16:47] wire _state_r_c_cat_T_62; // @[package.scala:16:47] assign _state_r_c_cat_T_62 = _GEN_20; // @[package.scala:16:47] wire _state_r_c_cat_T_85; // @[package.scala:16:47] assign _state_r_c_cat_T_85 = _GEN_20; // @[package.scala:16:47] wire _state_T_49; // @[package.scala:16:47] assign _state_T_49 = _GEN_20; // @[package.scala:16:47] wire _GEN_21 = io_req_uop_mem_cmd_0 == 5'hC; // @[package.scala:16:47] wire _r2_c_cat_T_13; // @[package.scala:16:47] assign _r2_c_cat_T_13 = _GEN_21; // @[package.scala:16:47] wire _r2_c_cat_T_36; // @[package.scala:16:47] assign _r2_c_cat_T_36 = _GEN_21; // @[package.scala:16:47] wire _needs_second_acq_T_13; // @[package.scala:16:47] assign _needs_second_acq_T_13 = _GEN_21; // @[package.scala:16:47] wire _dirties_cat_T_13; // @[package.scala:16:47] assign _dirties_cat_T_13 = _GEN_21; // @[package.scala:16:47] wire _dirties_cat_T_36; // @[package.scala:16:47] assign _dirties_cat_T_36 = _GEN_21; // @[package.scala:16:47] wire _state_r_c_cat_T_13; // @[package.scala:16:47] assign _state_r_c_cat_T_13 = _GEN_21; // @[package.scala:16:47] wire _state_r_c_cat_T_36; // @[package.scala:16:47] assign _state_r_c_cat_T_36 = _GEN_21; // @[package.scala:16:47] wire _state_T_16; // @[package.scala:16:47] assign _state_T_16 = _GEN_21; // @[package.scala:16:47] wire _r_c_cat_T_63; // @[package.scala:16:47] assign _r_c_cat_T_63 = _GEN_21; // @[package.scala:16:47] wire _r_c_cat_T_86; // @[package.scala:16:47] assign _r_c_cat_T_86 = _GEN_21; // @[package.scala:16:47] wire _state_r_c_cat_T_63; // @[package.scala:16:47] assign _state_r_c_cat_T_63 = _GEN_21; // @[package.scala:16:47] wire _state_r_c_cat_T_86; // @[package.scala:16:47] assign _state_r_c_cat_T_86 = _GEN_21; // @[package.scala:16:47] wire _state_T_50; // @[package.scala:16:47] assign _state_T_50 = _GEN_21; // @[package.scala:16:47] wire _GEN_22 = io_req_uop_mem_cmd_0 == 5'hD; // @[package.scala:16:47] wire _r2_c_cat_T_14; // @[package.scala:16:47] assign _r2_c_cat_T_14 = _GEN_22; // @[package.scala:16:47] wire _r2_c_cat_T_37; // @[package.scala:16:47] assign _r2_c_cat_T_37 = _GEN_22; // @[package.scala:16:47] wire _needs_second_acq_T_14; // @[package.scala:16:47] assign _needs_second_acq_T_14 = _GEN_22; // @[package.scala:16:47] wire _dirties_cat_T_14; // @[package.scala:16:47] assign _dirties_cat_T_14 = _GEN_22; // @[package.scala:16:47] wire _dirties_cat_T_37; // @[package.scala:16:47] assign _dirties_cat_T_37 = _GEN_22; // @[package.scala:16:47] wire _state_r_c_cat_T_14; // @[package.scala:16:47] assign _state_r_c_cat_T_14 = _GEN_22; // @[package.scala:16:47] wire _state_r_c_cat_T_37; // @[package.scala:16:47] assign _state_r_c_cat_T_37 = _GEN_22; // @[package.scala:16:47] wire _state_T_17; // @[package.scala:16:47] assign _state_T_17 = _GEN_22; // @[package.scala:16:47] wire _r_c_cat_T_64; // @[package.scala:16:47] assign _r_c_cat_T_64 = _GEN_22; // @[package.scala:16:47] wire _r_c_cat_T_87; // @[package.scala:16:47] assign _r_c_cat_T_87 = _GEN_22; // @[package.scala:16:47] wire _state_r_c_cat_T_64; // @[package.scala:16:47] assign _state_r_c_cat_T_64 = _GEN_22; // @[package.scala:16:47] wire _state_r_c_cat_T_87; // @[package.scala:16:47] assign _state_r_c_cat_T_87 = _GEN_22; // @[package.scala:16:47] wire _state_T_51; // @[package.scala:16:47] assign _state_T_51 = _GEN_22; // @[package.scala:16:47] wire _GEN_23 = io_req_uop_mem_cmd_0 == 5'hE; // @[package.scala:16:47] wire _r2_c_cat_T_15; // @[package.scala:16:47] assign _r2_c_cat_T_15 = _GEN_23; // @[package.scala:16:47] wire _r2_c_cat_T_38; // @[package.scala:16:47] assign _r2_c_cat_T_38 = _GEN_23; // @[package.scala:16:47] wire _needs_second_acq_T_15; // @[package.scala:16:47] assign _needs_second_acq_T_15 = _GEN_23; // @[package.scala:16:47] wire _dirties_cat_T_15; // @[package.scala:16:47] assign _dirties_cat_T_15 = _GEN_23; // @[package.scala:16:47] wire _dirties_cat_T_38; // @[package.scala:16:47] assign _dirties_cat_T_38 = _GEN_23; // @[package.scala:16:47] wire _state_r_c_cat_T_15; // @[package.scala:16:47] assign _state_r_c_cat_T_15 = _GEN_23; // @[package.scala:16:47] wire _state_r_c_cat_T_38; // @[package.scala:16:47] assign _state_r_c_cat_T_38 = _GEN_23; // @[package.scala:16:47] wire _state_T_18; // @[package.scala:16:47] assign _state_T_18 = _GEN_23; // @[package.scala:16:47] wire _r_c_cat_T_65; // @[package.scala:16:47] assign _r_c_cat_T_65 = _GEN_23; // @[package.scala:16:47] wire _r_c_cat_T_88; // @[package.scala:16:47] assign _r_c_cat_T_88 = _GEN_23; // @[package.scala:16:47] wire _state_r_c_cat_T_65; // @[package.scala:16:47] assign _state_r_c_cat_T_65 = _GEN_23; // @[package.scala:16:47] wire _state_r_c_cat_T_88; // @[package.scala:16:47] assign _state_r_c_cat_T_88 = _GEN_23; // @[package.scala:16:47] wire _state_T_52; // @[package.scala:16:47] assign _state_T_52 = _GEN_23; // @[package.scala:16:47] wire _GEN_24 = io_req_uop_mem_cmd_0 == 5'hF; // @[package.scala:16:47] wire _r2_c_cat_T_16; // @[package.scala:16:47] assign _r2_c_cat_T_16 = _GEN_24; // @[package.scala:16:47] wire _r2_c_cat_T_39; // @[package.scala:16:47] assign _r2_c_cat_T_39 = _GEN_24; // @[package.scala:16:47] wire _needs_second_acq_T_16; // @[package.scala:16:47] assign _needs_second_acq_T_16 = _GEN_24; // @[package.scala:16:47] wire _dirties_cat_T_16; // @[package.scala:16:47] assign _dirties_cat_T_16 = _GEN_24; // @[package.scala:16:47] wire _dirties_cat_T_39; // @[package.scala:16:47] assign _dirties_cat_T_39 = _GEN_24; // @[package.scala:16:47] wire _state_r_c_cat_T_16; // @[package.scala:16:47] assign _state_r_c_cat_T_16 = _GEN_24; // @[package.scala:16:47] wire _state_r_c_cat_T_39; // @[package.scala:16:47] assign _state_r_c_cat_T_39 = _GEN_24; // @[package.scala:16:47] wire _state_T_19; // @[package.scala:16:47] assign _state_T_19 = _GEN_24; // @[package.scala:16:47] wire _r_c_cat_T_66; // @[package.scala:16:47] assign _r_c_cat_T_66 = _GEN_24; // @[package.scala:16:47] wire _r_c_cat_T_89; // @[package.scala:16:47] assign _r_c_cat_T_89 = _GEN_24; // @[package.scala:16:47] wire _state_r_c_cat_T_66; // @[package.scala:16:47] assign _state_r_c_cat_T_66 = _GEN_24; // @[package.scala:16:47] wire _state_r_c_cat_T_89; // @[package.scala:16:47] assign _state_r_c_cat_T_89 = _GEN_24; // @[package.scala:16:47] wire _state_T_53; // @[package.scala:16:47] assign _state_T_53 = _GEN_24; // @[package.scala:16:47] wire _r2_c_cat_T_17 = _r2_c_cat_T_12 \| _r2_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_18 = _r2_c_cat_T_17 \| _r2_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_19 = _r2_c_cat_T_18 \| _r2_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_20 = _r2_c_cat_T_19 \| _r2_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_21 = _r2_c_cat_T_11 \| _r2_c_cat_T_20; // @[package.scala:81:59] wire _r2_c_cat_T_22 = _r2_c_cat_T_4 \| _r2_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _r2_c_cat_T_25 = _r2_c_cat_T_23 \| _r2_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _r2_c_cat_T_27 = _r2_c_cat_T_25 \| _r2_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _r2_c_cat_T_32 = _r2_c_cat_T_28 \| _r2_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_33 = _r2_c_cat_T_32 \| _r2_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_34 = _r2_c_cat_T_33 \| _r2_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_40 = _r2_c_cat_T_35 \| _r2_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_41 = _r2_c_cat_T_40 \| _r2_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_42 = _r2_c_cat_T_41 \| _r2_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_43 = _r2_c_cat_T_42 \| _r2_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_44 = _r2_c_cat_T_34 \| _r2_c_cat_T_43; // @[package.scala:81:59] wire _r2_c_cat_T_45 = _r2_c_cat_T_27 \| _r2_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _GEN_25 = io_req_uop_mem_cmd_0 == 5'h3; // @[Consts.scala:91:54] wire _r2_c_cat_T_46; // @[Consts.scala:91:54] assign _r2_c_cat_T_46 = _GEN_25; // @[Consts.scala:91:54] wire _needs_second_acq_T_23; // @[Consts.scala:91:54] assign _needs_second_acq_T_23 = _GEN_25; // @[Consts.scala:91:54] wire _dirties_cat_T_46; // @[Consts.scala:91:54] assign _dirties_cat_T_46 = _GEN_25; // @[Consts.scala:91:54] wire _rpq_io_enq_valid_T_4; // @[Consts.scala:88:52] assign _rpq_io_enq_valid_T_4 = _GEN_25; // @[Consts.scala:88:52, :91:54] wire _state_r_c_cat_T_46; // @[Consts.scala:91:54] assign _state_r_c_cat_T_46 = _GEN_25; // @[Consts.scala:91:54] wire _r_c_cat_T_96; // @[Consts.scala:91:54] assign _r_c_cat_T_96 = _GEN_25; // @[Consts.scala:91:54] wire _state_r_c_cat_T_96; // @[Consts.scala:91:54] assign _state_r_c_cat_T_96 = _GEN_25; // @[Consts.scala:91:54] wire _r2_c_cat_T_47 = _r2_c_cat_T_45 \| _r2_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _GEN_26 = io_req_uop_mem_cmd_0 == 5'h6; // @[Consts.scala:91:71] wire _r2_c_cat_T_48; // @[Consts.scala:91:71] assign _r2_c_cat_T_48 = _GEN_26; // @[Consts.scala:91:71] wire _needs_second_acq_T_25; // @[Consts.scala:91:71] assign _needs_second_acq_T_25 = _GEN_26; // @[Consts.scala:91:71] wire _dirties_cat_T_48; // @[Consts.scala:91:71] assign _dirties_cat_T_48 = _GEN_26; // @[Consts.scala:91:71] wire _state_r_c_cat_T_48; // @[Consts.scala:91:71] assign _state_r_c_cat_T_48 = _GEN_26; // @[Consts.scala:91:71] wire _r_c_cat_T_98; // @[Consts.scala:91:71] assign _r_c_cat_T_98 = _GEN_26; // @[Consts.scala:91:71] wire _state_r_c_cat_T_98; // @[Consts.scala:91:71] assign _state_r_c_cat_T_98 = _GEN_26; // @[Consts.scala:91:71] wire _r2_c_cat_T_49 = _r2_c_cat_T_47 \| _r2_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] r2_c = {_r2_c_cat_T_22, _r2_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _r2_T = {r2_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19] wire _r2_T_25 = _r2_T == 4'hC; // @[Misc.scala:49:20] wire [1:0] _r2_T_27 = {1'h0, _r2_T_25}; // @[Misc.scala:35:36, :49:20] wire _r2_T_28 = _r2_T == 4'hD; // @[Misc.scala:49:20] wire [1:0] _r2_T_30 = _r2_T_28 ? 2'h2 : _r2_T_27; // @[Misc.scala:35:36, :49:20] wire _r2_T_31 = _r2_T == 4'h4; // @[Misc.scala:49:20] wire [1:0] _r2_T_33 = _r2_T_31 ? 2'h1 : _r2_T_30; // @[Misc.scala:35:36, :49:20] wire _r2_T_34 = _r2_T == 4'h5; // @[Misc.scala:49:20] wire [1:0] _r2_T_36 = _r2_T_34 ? 2'h2 : _r2_T_33; // @[Misc.scala:35:36, :49:20] wire _r2_T_37 = _r2_T == 4'h0; // @[Misc.scala:49:20] wire [1:0] _r2_T_39 = _r2_T_37 ? 2'h0 : _r2_T_36; // @[Misc.scala:35:36, :49:20] wire _r2_T_40 = _r2_T == 4'hE; // @[Misc.scala:49:20] wire _r2_T_41 = _r2_T_40; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_42 = _r2_T_40 ? 2'h3 : _r2_T_39; // @[Misc.scala:35:36, :49:20] wire _r2_T_43 = &_r2_T; // @[Misc.scala:49:20] wire _r2_T_44 = _r2_T_43 \| _r2_T_41; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_45 = _r2_T_43 ? 2'h3 : _r2_T_42; // @[Misc.scala:35:36, :49:20] wire _r2_T_46 = _r2_T == 4'h6; // @[Misc.scala:49:20] wire _r2_T_47 = _r2_T_46 \| _r2_T_44; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_48 = _r2_T_46 ? 2'h2 : _r2_T_45; // @[Misc.scala:35:36, :49:20] wire _r2_T_49 = _r2_T == 4'h7; // @[Misc.scala:49:20] wire _r2_T_50 = _r2_T_49 \| _r2_T_47; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_51 = _r2_T_49 ? 2'h3 : _r2_T_48; // @[Misc.scala:35:36, :49:20] wire _r2_T_52 = _r2_T == 4'h1; // @[Misc.scala:49:20] wire _r2_T_53 = _r2_T_52 \| _r2_T_50; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_54 = _r2_T_52 ? 2'h1 : _r2_T_51; // @[Misc.scala:35:36, :49:20] wire _r2_T_55 = _r2_T == 4'h2; // @[Misc.scala:49:20] wire _r2_T_56 = _r2_T_55 \| _r2_T_53; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_57 = _r2_T_55 ? 2'h2 : _r2_T_54; // @[Misc.scala:35:36, :49:20] wire _r2_T_58 = _r2_T == 4'h3; // @[Misc.scala:49:20] wire r2_1 = _r2_T_58 \| _r2_T_56; // @[Misc.scala:35:9, :49:20] wire [1:0] r2_2 = _r2_T_58 ? 2'h3 : _r2_T_57; // @[Misc.scala:35:36, :49:20] wire _needs_second_acq_T_2 = _needs_second_acq_T \| _needs_second_acq_T_1; // @[Consts.scala:90:{32,42,49}] wire _needs_second_acq_T_4 = _needs_second_acq_T_2 \| _needs_second_acq_T_3; // @[Consts.scala:90:{42,59,66}] wire _needs_second_acq_T_9 = _needs_second_acq_T_5 \| _needs_second_acq_T_6; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_10 = _needs_second_acq_T_9 \| _needs_second_acq_T_7; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_11 = _needs_second_acq_T_10 \| _needs_second_acq_T_8; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_17 = _needs_second_acq_T_12 \| _needs_second_acq_T_13; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_18 = _needs_second_acq_T_17 \| _needs_second_acq_T_14; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_19 = _needs_second_acq_T_18 \| _needs_second_acq_T_15; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_20 = _needs_second_acq_T_19 \| _needs_second_acq_T_16; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_21 = _needs_second_acq_T_11 \| _needs_second_acq_T_20; // @[package.scala:81:59] wire _needs_second_acq_T_22 = _needs_second_acq_T_4 \| _needs_second_acq_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _needs_second_acq_T_24 = _needs_second_acq_T_22 \| _needs_second_acq_T_23; // @[Consts.scala:90:76, :91:{47,54}] wire _needs_second_acq_T_26 = _needs_second_acq_T_24 \| _needs_second_acq_T_25; // @[Consts.scala:91:{47,64,71}] wire _needs_second_acq_T_29 = _needs_second_acq_T_27 \| _needs_second_acq_T_28; // @[Consts.scala:90:{32,42,49}] wire _needs_second_acq_T_31 = _needs_second_acq_T_29 \| _needs_second_acq_T_30; // @[Consts.scala:90:{42,59,66}] wire _needs_second_acq_T_36 = _needs_second_acq_T_32 \| _needs_second_acq_T_33; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_37 = _needs_second_acq_T_36 \| _needs_second_acq_T_34; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_38 = _needs_second_acq_T_37 \| _needs_second_acq_T_35; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_44 = _needs_second_acq_T_39 \| _needs_second_acq_T_40; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_45 = _needs_second_acq_T_44 \| _needs_second_acq_T_41; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_46 = _needs_second_acq_T_45 \| _needs_second_acq_T_42; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_47 = _needs_second_acq_T_46 \| _needs_second_acq_T_43; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_48 = _needs_second_acq_T_38 \| _needs_second_acq_T_47; // @[package.scala:81:59] wire _needs_second_acq_T_49 = _needs_second_acq_T_31 \| _needs_second_acq_T_48; // @[Consts.scala:87:44, :90:{59,76}] wire _needs_second_acq_T_51 = _needs_second_acq_T_49 \| _needs_second_acq_T_50; // @[Consts.scala:90:76, :91:{47,54}] wire _needs_second_acq_T_53 = _needs_second_acq_T_51 \| _needs_second_acq_T_52; // @[Consts.scala:91:{47,64,71}] wire _needs_second_acq_T_54 = ~_needs_second_acq_T_53; // @[Metadata.scala:104:57] wire cmd_requires_second_acquire = _needs_second_acq_T_26 & _needs_second_acq_T_54; // @[Metadata.scala:104:{54,57}] wire is_hit_again = r1_1 & r2_1; // @[Misc.scala:35:9] wire _dirties_cat_T_2 = _dirties_cat_T \| _dirties_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _dirties_cat_T_4 = _dirties_cat_T_2 \| _dirties_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _dirties_cat_T_9 = _dirties_cat_T_5 \| _dirties_cat_T_6; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_10 = _dirties_cat_T_9 \| _dirties_cat_T_7; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_11 = _dirties_cat_T_10 \| _dirties_cat_T_8; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_17 = _dirties_cat_T_12 \| _dirties_cat_T_13; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_18 = _dirties_cat_T_17 \| _dirties_cat_T_14; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_19 = _dirties_cat_T_18 \| _dirties_cat_T_15; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_20 = _dirties_cat_T_19 \| _dirties_cat_T_16; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_21 = _dirties_cat_T_11 \| _dirties_cat_T_20; // @[package.scala:81:59] wire _dirties_cat_T_22 = _dirties_cat_T_4 \| _dirties_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _dirties_cat_T_25 = _dirties_cat_T_23 \| _dirties_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _dirties_cat_T_27 = _dirties_cat_T_25 \| _dirties_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _dirties_cat_T_32 = _dirties_cat_T_28 \| _dirties_cat_T_29; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_33 = _dirties_cat_T_32 \| _dirties_cat_T_30; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_34 = _dirties_cat_T_33 \| _dirties_cat_T_31; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_40 = _dirties_cat_T_35 \| _dirties_cat_T_36; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_41 = _dirties_cat_T_40 \| _dirties_cat_T_37; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_42 = _dirties_cat_T_41 \| _dirties_cat_T_38; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_43 = _dirties_cat_T_42 \| _dirties_cat_T_39; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_44 = _dirties_cat_T_34 \| _dirties_cat_T_43; // @[package.scala:81:59] wire _dirties_cat_T_45 = _dirties_cat_T_27 \| _dirties_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _dirties_cat_T_47 = _dirties_cat_T_45 \| _dirties_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _dirties_cat_T_49 = _dirties_cat_T_47 \| _dirties_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] dirties_cat = {_dirties_cat_T_22, _dirties_cat_T_49}; // @[Metadata.scala:29:18] wire dirties = &dirties_cat; // @[Metadata.scala:29:18, :106:42] wire [1:0] biggest_grow_param = dirties ? r2_2 : r1_2; // @[Misc.scala:35:36] wire [1:0] dirtier_coh_state = biggest_grow_param; // @[Metadata.scala:107:33, :160:20] wire [4:0] dirtier_cmd = dirties ? io_req_uop_mem_cmd_0 : req_uop_mem_cmd; // @[Metadata.scala:106:42, :109:27] wire _T_16 = io_mem_grant_ready_0 & io_mem_grant_valid_0; // @[Decoupled.scala:51:35] wire [26:0] _r_beats1_decode_T = 27'hFFF << io_mem_grant_bits_size_0; // @[package.scala:243:71] wire [11:0] _r_beats1_decode_T_1 = _r_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _r_beats1_decode_T_2 = ~_r_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] r_beats1_decode = _r_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire r_beats1_opdata = io_mem_grant_bits_opcode_0[0]; // @[Edges.scala:106:36] wire opdata = io_mem_grant_bits_opcode_0[0]; // @[Edges.scala:106:36] wire grant_had_data_opdata = io_mem_grant_bits_opcode_0[0]; // @[Edges.scala:106:36] wire [7:0] r_beats1 = r_beats1_opdata ? r_beats1_decode : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] r_counter; // @[Edges.scala:229:27] wire [8:0] _r_counter1_T = {1'h0, r_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] r_counter1 = _r_counter1_T[7:0]; // @[Edges.scala:230:28] wire r_1_1 = r_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _r_last_T = r_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _r_last_T_1 = r_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire r_2 = _r_last_T \| _r_last_T_1; // @[Edges.scala:232:{25,33,43}] wire refill_done = r_2 & _T_16; // @[Decoupled.scala:51:35] wire [7:0] _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] r_4 = r_beats1 & _r_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _r_counter_T = r_1_1 ? r_beats1 : r_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] refill_address_inc = {r_4, 4'h0}; // @[Edges.scala:234:25, :269:29] wire _sec_rdy_T = ~cmd_requires_second_acquire; // @[Metadata.scala:104:54] wire _sec_rdy_T_1 = ~io_req_is_probe_0; // @[mshrs.scala:36:7, :125:50] wire _sec_rdy_T_2 = _sec_rdy_T & _sec_rdy_T_1; // @[mshrs.scala:125:{18,47,50}] wire _sec_rdy_T_3 = ~(\|state); // @[package.scala:16:47] wire _sec_rdy_T_4 = state == 5'hD; // @[package.scala:16:47] wire _sec_rdy_T_5 = state == 5'hE; // @[package.scala:16:47] wire _sec_rdy_T_6 = state == 5'hF; // @[package.scala:16:47] wire _sec_rdy_T_7 = _sec_rdy_T_3 \| _sec_rdy_T_4; // @[package.scala:16:47, :81:59] wire _sec_rdy_T_8 = _sec_rdy_T_7 \| _sec_rdy_T_5; // @[package.scala:16:47, :81:59] wire _sec_rdy_T_9 = _sec_rdy_T_8 \| _sec_rdy_T_6; // @[package.scala:16:47, :81:59] wire _sec_rdy_T_10 = ~_sec_rdy_T_9; // @[package.scala:81:59] wire sec_rdy = _sec_rdy_T_2 & _sec_rdy_T_10; // @[mshrs.scala:125:{47,67}, :126:18] wire _rpq_io_enq_valid_T = io_req_pri_val_0 & io_req_pri_rdy_0; // @[mshrs.scala:36:7, :133:40] wire _rpq_io_enq_valid_T_1 = io_req_sec_val_0 & io_req_sec_rdy_0; // @[mshrs.scala:36:7, :133:78] wire _rpq_io_enq_valid_T_2 = _rpq_io_enq_valid_T \| _rpq_io_enq_valid_T_1; // @[mshrs.scala:133:{40,59,78}] wire _rpq_io_enq_valid_T_3 = io_req_uop_mem_cmd_0 == 5'h2; // @[Consts.scala:88:35] wire _rpq_io_enq_valid_T_5 = _rpq_io_enq_valid_T_3 \| _rpq_io_enq_valid_T_4; // @[Consts.scala:88:{35,45,52}] wire _rpq_io_enq_valid_T_6 = ~_rpq_io_enq_valid_T_5; // @[Consts.scala:88:45] wire _rpq_io_enq_valid_T_7 = _rpq_io_enq_valid_T_2 & _rpq_io_enq_valid_T_6; // @[mshrs.scala:133:{59,98,101}] reg grantack_valid; // @[mshrs.scala:138:21] reg [3:0] grantack_bits_sink; // @[mshrs.scala:138:21] assign io_mem_finish_bits_sink_0 = grantack_bits_sink; // @[mshrs.scala:36:7, :138:21] reg [1:0] refill_ctr; // @[mshrs.scala:139:24] reg commit_line; // @[mshrs.scala:140:24] reg grant_had_data; // @[mshrs.scala:141:27] reg finish_to_prefetch; // @[mshrs.scala:142:31] reg [1:0] meta_hazard; // @[mshrs.scala:145:28] wire [2:0] _meta_hazard_T = {1'h0, meta_hazard} + 3'h1; // @[mshrs.scala:145:28, :146:59] wire [1:0] _meta_hazard_T_1 = _meta_hazard_T[1:0]; // @[mshrs.scala:146:59] wire _io_probe_rdy_T = meta_hazard == 2'h0; // @[mshrs.scala:145:28, :148:34] wire _io_probe_rdy_T_1 = ~(\|state); // @[package.scala:16:47] wire _io_probe_rdy_T_2 = state == 5'h1; // @[package.scala:16:47] wire _io_probe_rdy_T_3 = state == 5'h2; // @[package.scala:16:47] wire _io_probe_rdy_T_4 = state == 5'h3; // @[package.scala:16:47] wire _io_probe_rdy_T_5 = _io_probe_rdy_T_1 \| _io_probe_rdy_T_2; // @[package.scala:16:47, :81:59] wire _io_probe_rdy_T_6 = _io_probe_rdy_T_5 \| _io_probe_rdy_T_3; // @[package.scala:16:47, :81:59] wire _io_probe_rdy_T_7 = _io_probe_rdy_T_6 \| _io_probe_rdy_T_4; // @[package.scala:16:47, :81:59] wire _io_probe_rdy_T_8 = state == 5'h4; // @[mshrs.scala:107:22, :148:129] wire _io_probe_rdy_T_9 = _io_probe_rdy_T_8 & grantack_valid; // @[mshrs.scala:138:21, :148:{129,145}] wire _io_probe_rdy_T_10 = _io_probe_rdy_T_7 \| _io_probe_rdy_T_9; // @[package.scala:81:59] assign _io_probe_rdy_T_11 = _io_probe_rdy_T & _io_probe_rdy_T_10; // @[mshrs.scala:148:{34,42,119}] assign io_probe_rdy_0 = _io_probe_rdy_T_11; // @[mshrs.scala:36:7, :148:42] assign _io_idx_valid_T = \|state; // @[package.scala:16:47] assign io_idx_valid_0 = _io_idx_valid_T; // @[mshrs.scala:36:7, :149:25] assign _io_tag_valid_T = \|state; // @[package.scala:16:47] assign io_tag_valid_0 = _io_tag_valid_T; // @[mshrs.scala:36:7, :150:25] wire _io_way_valid_T = ~(\|state); // @[package.scala:16:47] wire _io_way_valid_T_1 = state == 5'h11; // @[package.scala:16:47] wire _io_way_valid_T_2 = _io_way_valid_T \| _io_way_valid_T_1; // @[package.scala:16:47, :81:59] assign _io_way_valid_T_3 = ~_io_way_valid_T_2; // @[package.scala:81:59] assign io_way_valid_0 = _io_way_valid_T_3; // @[mshrs.scala:36:7, :151:19] assign _io_req_sec_rdy_T = sec_rdy & _rpq_io_enq_ready; // @[mshrs.scala:125:67, :128:19, :159:37] assign io_req_sec_rdy_0 = _io_req_sec_rdy_T; // @[mshrs.scala:36:7, :159:37] wire [4:0] state_new_state; // @[mshrs.scala:191:29] wire _state_T_1 = ~_state_T; // @[mshrs.scala:194:11] wire _state_T_2 = ~_rpq_io_enq_ready; // @[mshrs.scala:128:19, :194:11] wire [3:0] _GEN_27 = {2'h2, io_req_old_meta_coh_state_0}; // @[Metadata.scala:120:19] wire [3:0] _state_req_needs_wb_r_T_6; // @[Metadata.scala:120:19] assign _state_req_needs_wb_r_T_6 = _GEN_27; // @[Metadata.scala:120:19] wire [3:0] _state_req_needs_wb_r_T_70; // @[Metadata.scala:120:19] assign _state_req_needs_wb_r_T_70 = _GEN_27; // @[Metadata.scala:120:19] wire _state_req_needs_wb_r_T_19 = _state_req_needs_wb_r_T_6 == 4'h8; // @[Misc.scala:56:20] wire [2:0] _state_req_needs_wb_r_T_21 = _state_req_needs_wb_r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_23 = _state_req_needs_wb_r_T_6 == 4'h9; // @[Misc.scala:56:20] wire [2:0] _state_req_needs_wb_r_T_25 = _state_req_needs_wb_r_T_23 ? 3'h2 : _state_req_needs_wb_r_T_21; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_27 = _state_req_needs_wb_r_T_6 == 4'hA; // @[Misc.scala:56:20] wire [2:0] _state_req_needs_wb_r_T_29 = _state_req_needs_wb_r_T_27 ? 3'h1 : _state_req_needs_wb_r_T_25; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_31 = _state_req_needs_wb_r_T_6 == 4'hB; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_32 = _state_req_needs_wb_r_T_31; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_33 = _state_req_needs_wb_r_T_31 ? 3'h1 : _state_req_needs_wb_r_T_29; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_35 = _state_req_needs_wb_r_T_6 == 4'h4; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_36 = ~_state_req_needs_wb_r_T_35 & _state_req_needs_wb_r_T_32; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_37 = _state_req_needs_wb_r_T_35 ? 3'h5 : _state_req_needs_wb_r_T_33; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_39 = _state_req_needs_wb_r_T_6 == 4'h5; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_40 = ~_state_req_needs_wb_r_T_39 & _state_req_needs_wb_r_T_36; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_41 = _state_req_needs_wb_r_T_39 ? 3'h4 : _state_req_needs_wb_r_T_37; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_42 = {1'h0, _state_req_needs_wb_r_T_39}; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_43 = _state_req_needs_wb_r_T_6 == 4'h6; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_44 = ~_state_req_needs_wb_r_T_43 & _state_req_needs_wb_r_T_40; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_45 = _state_req_needs_wb_r_T_43 ? 3'h0 : _state_req_needs_wb_r_T_41; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_46 = _state_req_needs_wb_r_T_43 ? 2'h1 : _state_req_needs_wb_r_T_42; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_47 = _state_req_needs_wb_r_T_6 == 4'h7; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_48 = _state_req_needs_wb_r_T_47 \| _state_req_needs_wb_r_T_44; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_49 = _state_req_needs_wb_r_T_47 ? 3'h0 : _state_req_needs_wb_r_T_45; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_50 = _state_req_needs_wb_r_T_47 ? 2'h1 : _state_req_needs_wb_r_T_46; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_51 = _state_req_needs_wb_r_T_6 == 4'h0; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_52 = ~_state_req_needs_wb_r_T_51 & _state_req_needs_wb_r_T_48; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_53 = _state_req_needs_wb_r_T_51 ? 3'h5 : _state_req_needs_wb_r_T_49; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_54 = _state_req_needs_wb_r_T_51 ? 2'h0 : _state_req_needs_wb_r_T_50; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_55 = _state_req_needs_wb_r_T_6 == 4'h1; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_56 = ~_state_req_needs_wb_r_T_55 & _state_req_needs_wb_r_T_52; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_57 = _state_req_needs_wb_r_T_55 ? 3'h4 : _state_req_needs_wb_r_T_53; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_58 = _state_req_needs_wb_r_T_55 ? 2'h1 : _state_req_needs_wb_r_T_54; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_59 = _state_req_needs_wb_r_T_6 == 4'h2; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_60 = ~_state_req_needs_wb_r_T_59 & _state_req_needs_wb_r_T_56; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_61 = _state_req_needs_wb_r_T_59 ? 3'h3 : _state_req_needs_wb_r_T_57; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_62 = _state_req_needs_wb_r_T_59 ? 2'h2 : _state_req_needs_wb_r_T_58; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_63 = _state_req_needs_wb_r_T_6 == 4'h3; // @[Misc.scala:56:20] wire state_req_needs_wb_r_1 = _state_req_needs_wb_r_T_63 \| _state_req_needs_wb_r_T_60; // @[Misc.scala:38:9, :56:20] wire [2:0] state_req_needs_wb_r_2 = _state_req_needs_wb_r_T_63 ? 3'h3 : _state_req_needs_wb_r_T_61; // @[Misc.scala:38:36, :56:20] wire [1:0] state_req_needs_wb_r_3 = _state_req_needs_wb_r_T_63 ? 2'h2 : _state_req_needs_wb_r_T_62; // @[Misc.scala:38:63, :56:20] wire [1:0] state_req_needs_wb_meta_state = state_req_needs_wb_r_3; // @[Misc.scala:38:63] wire _state_r_c_cat_T_2 = _state_r_c_cat_T \| _state_r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _state_r_c_cat_T_4 = _state_r_c_cat_T_2 \| _state_r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _state_r_c_cat_T_9 = _state_r_c_cat_T_5 \| _state_r_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_10 = _state_r_c_cat_T_9 \| _state_r_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_11 = _state_r_c_cat_T_10 \| _state_r_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_17 = _state_r_c_cat_T_12 \| _state_r_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_18 = _state_r_c_cat_T_17 \| _state_r_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_19 = _state_r_c_cat_T_18 \| _state_r_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_20 = _state_r_c_cat_T_19 \| _state_r_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_21 = _state_r_c_cat_T_11 \| _state_r_c_cat_T_20; // @[package.scala:81:59] wire _state_r_c_cat_T_22 = _state_r_c_cat_T_4 \| _state_r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _state_r_c_cat_T_25 = _state_r_c_cat_T_23 \| _state_r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _state_r_c_cat_T_27 = _state_r_c_cat_T_25 \| _state_r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _state_r_c_cat_T_32 = _state_r_c_cat_T_28 \| _state_r_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_33 = _state_r_c_cat_T_32 \| _state_r_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_34 = _state_r_c_cat_T_33 \| _state_r_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_40 = _state_r_c_cat_T_35 \| _state_r_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_41 = _state_r_c_cat_T_40 \| _state_r_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_42 = _state_r_c_cat_T_41 \| _state_r_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_43 = _state_r_c_cat_T_42 \| _state_r_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_44 = _state_r_c_cat_T_34 \| _state_r_c_cat_T_43; // @[package.scala:81:59] wire _state_r_c_cat_T_45 = _state_r_c_cat_T_27 \| _state_r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _state_r_c_cat_T_47 = _state_r_c_cat_T_45 \| _state_r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _state_r_c_cat_T_49 = _state_r_c_cat_T_47 \| _state_r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] state_r_c = {_state_r_c_cat_T_22, _state_r_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _state_r_T = {state_r_c, io_req_old_meta_coh_state_0}; // @[Metadata.scala:29:18, :58:19] wire _state_r_T_25 = _state_r_T == 4'hC; // @[Misc.scala:49:20] wire [1:0] _state_r_T_27 = {1'h0, _state_r_T_25}; // @[Misc.scala:35:36, :49:20] wire _state_r_T_28 = _state_r_T == 4'hD; // @[Misc.scala:49:20] wire [1:0] _state_r_T_30 = _state_r_T_28 ? 2'h2 : _state_r_T_27; // @[Misc.scala:35:36, :49:20] wire _state_r_T_31 = _state_r_T == 4'h4; // @[Misc.scala:49:20] wire [1:0] _state_r_T_33 = _state_r_T_31 ? 2'h1 : _state_r_T_30; // @[Misc.scala:35:36, :49:20] wire _state_r_T_34 = _state_r_T == 4'h5; // @[Misc.scala:49:20] wire [1:0] _state_r_T_36 = _state_r_T_34 ? 2'h2 : _state_r_T_33; // @[Misc.scala:35:36, :49:20] wire _state_r_T_37 = _state_r_T == 4'h0; // @[Misc.scala:49:20] wire [1:0] _state_r_T_39 = _state_r_T_37 ? 2'h0 : _state_r_T_36; // @[Misc.scala:35:36, :49:20] wire _state_r_T_40 = _state_r_T == 4'hE; // @[Misc.scala:49:20] wire _state_r_T_41 = _state_r_T_40; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_42 = _state_r_T_40 ? 2'h3 : _state_r_T_39; // @[Misc.scala:35:36, :49:20] wire _state_r_T_43 = &_state_r_T; // @[Misc.scala:49:20] wire _state_r_T_44 = _state_r_T_43 \| _state_r_T_41; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_45 = _state_r_T_43 ? 2'h3 : _state_r_T_42; // @[Misc.scala:35:36, :49:20] wire _state_r_T_46 = _state_r_T == 4'h6; // @[Misc.scala:49:20] wire _state_r_T_47 = _state_r_T_46 \| _state_r_T_44; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_48 = _state_r_T_46 ? 2'h2 : _state_r_T_45; // @[Misc.scala:35:36, :49:20] wire _state_r_T_49 = _state_r_T == 4'h7; // @[Misc.scala:49:20] wire _state_r_T_50 = _state_r_T_49 \| _state_r_T_47; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_51 = _state_r_T_49 ? 2'h3 : _state_r_T_48; // @[Misc.scala:35:36, :49:20] wire _state_r_T_52 = _state_r_T == 4'h1; // @[Misc.scala:49:20] wire _state_r_T_53 = _state_r_T_52 \| _state_r_T_50; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_54 = _state_r_T_52 ? 2'h1 : _state_r_T_51; // @[Misc.scala:35:36, :49:20] wire _state_r_T_55 = _state_r_T == 4'h2; // @[Misc.scala:49:20] wire _state_r_T_56 = _state_r_T_55 \| _state_r_T_53; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_57 = _state_r_T_55 ? 2'h2 : _state_r_T_54; // @[Misc.scala:35:36, :49:20] wire _state_r_T_58 = _state_r_T == 4'h3; // @[Misc.scala:49:20] wire state_is_hit = _state_r_T_58 \| _state_r_T_56; // @[Misc.scala:35:9, :49:20] wire [1:0] state_r_2 = _state_r_T_58 ? 2'h3 : _state_r_T_57; // @[Misc.scala:35:36, :49:20] wire [1:0] state_coh_on_hit_state = state_r_2; // @[Misc.scala:35:36] wire _state_T_5 = _state_T_3 \| _state_T_4; // @[Consts.scala:90:{32,42,49}] wire _state_T_7 = _state_T_5 \| _state_T_6; // @[Consts.scala:90:{42,59,66}] wire _state_T_12 = _state_T_8 \| _state_T_9; // @[package.scala:16:47, :81:59] wire _state_T_13 = _state_T_12 \| _state_T_10; // @[package.scala:16:47, :81:59] wire _state_T_14 = _state_T_13 \| _state_T_11; // @[package.scala:16:47, :81:59] wire _state_T_20 = _state_T_15 \| _state_T_16; // @[package.scala:16:47, :81:59] wire _state_T_21 = _state_T_20 \| _state_T_17; // @[package.scala:16:47, :81:59] wire _state_T_22 = _state_T_21 \| _state_T_18; // @[package.scala:16:47, :81:59] wire _state_T_23 = _state_T_22 \| _state_T_19; // @[package.scala:16:47, :81:59] wire _state_T_24 = _state_T_14 \| _state_T_23; // @[package.scala:81:59] wire _state_T_25 = _state_T_7 \| _state_T_24; // @[Consts.scala:87:44, :90:{59,76}] wire _state_T_27 = ~_state_T_26; // @[mshrs.scala:201:15] wire _state_T_28 = ~_state_T_25; // @[Consts.scala:90:76] assign state_new_state = io_req_tag_match_0 & state_is_hit ? 5'hC : 5'h1; // @[Misc.scala:35:9] assign io_mem_acquire_valid_0 = (\|state) & _io_probe_rdy_T_2; // @[package.scala:16:47] wire [33:0] _GEN_28 = {req_tag, req_idx}; // @[mshrs.scala:110:25, :111:26, :227:28] wire [33:0] _io_mem_acquire_bits_T; // @[mshrs.scala:227:28] assign _io_mem_acquire_bits_T = _GEN_28; // @[mshrs.scala:227:28] wire [33:0] rp_addr_hi; // @[mshrs.scala:261:22] assign rp_addr_hi = _GEN_28; // @[mshrs.scala:227:28, :261:22] wire [33:0] hi; // @[mshrs.scala:266:10] assign hi = _GEN_28; // @[mshrs.scala:227:28, :266:10] wire [33:0] io_replay_bits_addr_hi; // @[mshrs.scala:353:31] assign io_replay_bits_addr_hi = _GEN_28; // @[mshrs.scala:227:28, :353:31] wire [39:0] _io_mem_acquire_bits_T_1 = {_io_mem_acquire_bits_T, 6'h0}; // @[mshrs.scala:227:{28,47}] wire [39:0] _io_mem_acquire_bits_legal_T_1 = _io_mem_acquire_bits_T_1; // @[Parameters.scala:137:31] wire [40:0] _io_mem_acquire_bits_legal_T_2 = {1'h0, _io_mem_acquire_bits_legal_T_1}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_mem_acquire_bits_legal_T_3 = _io_mem_acquire_bits_legal_T_2 & 41'h8C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_mem_acquire_bits_legal_T_4 = _io_mem_acquire_bits_legal_T_3; // @[Parameters.scala:137:46] wire _io_mem_acquire_bits_legal_T_5 = _io_mem_acquire_bits_legal_T_4 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _io_mem_acquire_bits_legal_T_6 = {_io_mem_acquire_bits_T_1[39:17], _io_mem_acquire_bits_T_1[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31] wire [40:0] _io_mem_acquire_bits_legal_T_7 = {1'h0, _io_mem_acquire_bits_legal_T_6}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_mem_acquire_bits_legal_T_8 = _io_mem_acquire_bits_legal_T_7 & 41'h8C011000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_mem_acquire_bits_legal_T_9 = _io_mem_acquire_bits_legal_T_8; // @[Parameters.scala:137:46] wire _io_mem_acquire_bits_legal_T_10 = _io_mem_acquire_bits_legal_T_9 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _io_mem_acquire_bits_legal_T_11 = {_io_mem_acquire_bits_T_1[39:28], _io_mem_acquire_bits_T_1[27:0] ^ 28'hC000000}; // @[Parameters.scala:137:31] wire [40:0] _io_mem_acquire_bits_legal_T_12 = {1'h0, _io_mem_acquire_bits_legal_T_11}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_mem_acquire_bits_legal_T_13 = _io_mem_acquire_bits_legal_T_12 & 41'h8C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_mem_acquire_bits_legal_T_14 = _io_mem_acquire_bits_legal_T_13; // @[Parameters.scala:137:46] wire _io_mem_acquire_bits_legal_T_15 = _io_mem_acquire_bits_legal_T_14 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_mem_acquire_bits_legal_T_16 = _io_mem_acquire_bits_legal_T_5 \| _io_mem_acquire_bits_legal_T_10; // @[Parameters.scala:685:42] wire _io_mem_acquire_bits_legal_T_17 = _io_mem_acquire_bits_legal_T_16 \| _io_mem_acquire_bits_legal_T_15; // @[Parameters.scala:685:42] wire [39:0] _io_mem_acquire_bits_legal_T_21 = {_io_mem_acquire_bits_T_1[39:28], _io_mem_acquire_bits_T_1[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31] wire [40:0] _io_mem_acquire_bits_legal_T_22 = {1'h0, _io_mem_acquire_bits_legal_T_21}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_mem_acquire_bits_legal_T_23 = _io_mem_acquire_bits_legal_T_22 & 41'h8C010000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_mem_acquire_bits_legal_T_24 = _io_mem_acquire_bits_legal_T_23; // @[Parameters.scala:137:46] wire _io_mem_acquire_bits_legal_T_25 = _io_mem_acquire_bits_legal_T_24 == 41'h0; // @[Parameters.scala:137:{46,59}] assign io_mem_acquire_bits_a_address = _io_mem_acquire_bits_T_1[31:0]; // @[Edges.scala:346:17] wire [39:0] _io_mem_acquire_bits_legal_T_26 = {_io_mem_acquire_bits_T_1[39:32], io_mem_acquire_bits_a_address ^ 32'h80000000}; // @[Edges.scala:346:17] wire [40:0] _io_mem_acquire_bits_legal_T_27 = {1'h0, _io_mem_acquire_bits_legal_T_26}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_mem_acquire_bits_legal_T_28 = _io_mem_acquire_bits_legal_T_27 & 41'h80000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_mem_acquire_bits_legal_T_29 = _io_mem_acquire_bits_legal_T_28; // @[Parameters.scala:137:46] wire _io_mem_acquire_bits_legal_T_30 = _io_mem_acquire_bits_legal_T_29 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_mem_acquire_bits_legal_T_31 = _io_mem_acquire_bits_legal_T_25 \| _io_mem_acquire_bits_legal_T_30; // @[Parameters.scala:685:42] wire _io_mem_acquire_bits_legal_T_32 = _io_mem_acquire_bits_legal_T_31; // @[Parameters.scala:684:54, :685:42] wire io_mem_acquire_bits_legal = _io_mem_acquire_bits_legal_T_32; // @[Parameters.scala:684:54, :686:26] assign io_mem_acquire_bits_param_0 = io_mem_acquire_bits_a_param; // @[Edges.scala:346:17] assign io_mem_acquire_bits_address_0 = io_mem_acquire_bits_a_address; // @[Edges.scala:346:17] assign io_mem_acquire_bits_a_param = {1'h0, grow_param}; // @[Misc.scala:35:36] wire io_mem_acquire_bits_a_mask_sub_sub_sub_bit = _io_mem_acquire_bits_T_1[3]; // @[Misc.scala:210:26] wire io_mem_acquire_bits_a_mask_sub_sub_sub_1_2 = io_mem_acquire_bits_a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire io_mem_acquire_bits_a_mask_sub_sub_sub_nbit = ~io_mem_acquire_bits_a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire io_mem_acquire_bits_a_mask_sub_sub_sub_0_2 = io_mem_acquire_bits_a_mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire io_mem_acquire_bits_a_mask_sub_sub_bit = _io_mem_acquire_bits_T_1[2]; // @[Misc.scala:210:26] wire io_mem_acquire_bits_a_mask_sub_sub_nbit = ~io_mem_acquire_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire io_mem_acquire_bits_a_mask_sub_sub_0_2 = io_mem_acquire_bits_a_mask_sub_sub_sub_0_2 & io_mem_acquire_bits_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_sub_sub_acc_T = io_mem_acquire_bits_a_mask_sub_sub_0_2; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_sub_sub_1_2 = io_mem_acquire_bits_a_mask_sub_sub_sub_0_2 & io_mem_acquire_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_sub_sub_acc_T_1 = io_mem_acquire_bits_a_mask_sub_sub_1_2; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_sub_sub_2_2 = io_mem_acquire_bits_a_mask_sub_sub_sub_1_2 & io_mem_acquire_bits_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_sub_sub_acc_T_2 = io_mem_acquire_bits_a_mask_sub_sub_2_2; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_sub_sub_3_2 = io_mem_acquire_bits_a_mask_sub_sub_sub_1_2 & io_mem_acquire_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_sub_sub_acc_T_3 = io_mem_acquire_bits_a_mask_sub_sub_3_2; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_sub_bit = _io_mem_acquire_bits_T_1[1]; // @[Misc.scala:210:26] wire io_mem_acquire_bits_a_mask_sub_nbit = ~io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire io_mem_acquire_bits_a_mask_sub_0_2 = io_mem_acquire_bits_a_mask_sub_sub_0_2 & io_mem_acquire_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire io_mem_acquire_bits_a_mask_sub_1_2 = io_mem_acquire_bits_a_mask_sub_sub_0_2 & io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire io_mem_acquire_bits_a_mask_sub_2_2 = io_mem_acquire_bits_a_mask_sub_sub_1_2 & io_mem_acquire_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire io_mem_acquire_bits_a_mask_sub_3_2 = io_mem_acquire_bits_a_mask_sub_sub_1_2 & io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire io_mem_acquire_bits_a_mask_sub_4_2 = io_mem_acquire_bits_a_mask_sub_sub_2_2 & io_mem_acquire_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire io_mem_acquire_bits_a_mask_sub_5_2 = io_mem_acquire_bits_a_mask_sub_sub_2_2 & io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire io_mem_acquire_bits_a_mask_sub_6_2 = io_mem_acquire_bits_a_mask_sub_sub_3_2 & io_mem_acquire_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire io_mem_acquire_bits_a_mask_sub_7_2 = io_mem_acquire_bits_a_mask_sub_sub_3_2 & io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire io_mem_acquire_bits_a_mask_bit = _io_mem_acquire_bits_T_1[0]; // @[Misc.scala:210:26] wire io_mem_acquire_bits_a_mask_nbit = ~io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire io_mem_acquire_bits_a_mask_eq = io_mem_acquire_bits_a_mask_sub_0_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T = io_mem_acquire_bits_a_mask_eq; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_1 = io_mem_acquire_bits_a_mask_sub_0_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_1 = io_mem_acquire_bits_a_mask_eq_1; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_2 = io_mem_acquire_bits_a_mask_sub_1_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_2 = io_mem_acquire_bits_a_mask_eq_2; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_3 = io_mem_acquire_bits_a_mask_sub_1_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_3 = io_mem_acquire_bits_a_mask_eq_3; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_4 = io_mem_acquire_bits_a_mask_sub_2_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_4 = io_mem_acquire_bits_a_mask_eq_4; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_5 = io_mem_acquire_bits_a_mask_sub_2_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_5 = io_mem_acquire_bits_a_mask_eq_5; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_6 = io_mem_acquire_bits_a_mask_sub_3_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_6 = io_mem_acquire_bits_a_mask_eq_6; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_7 = io_mem_acquire_bits_a_mask_sub_3_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_7 = io_mem_acquire_bits_a_mask_eq_7; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_8 = io_mem_acquire_bits_a_mask_sub_4_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_8 = io_mem_acquire_bits_a_mask_eq_8; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_9 = io_mem_acquire_bits_a_mask_sub_4_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_9 = io_mem_acquire_bits_a_mask_eq_9; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_10 = io_mem_acquire_bits_a_mask_sub_5_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_10 = io_mem_acquire_bits_a_mask_eq_10; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_11 = io_mem_acquire_bits_a_mask_sub_5_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_11 = io_mem_acquire_bits_a_mask_eq_11; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_12 = io_mem_acquire_bits_a_mask_sub_6_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_12 = io_mem_acquire_bits_a_mask_eq_12; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_13 = io_mem_acquire_bits_a_mask_sub_6_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_13 = io_mem_acquire_bits_a_mask_eq_13; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_14 = io_mem_acquire_bits_a_mask_sub_7_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_14 = io_mem_acquire_bits_a_mask_eq_14; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_15 = io_mem_acquire_bits_a_mask_sub_7_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_15 = io_mem_acquire_bits_a_mask_eq_15; // @[Misc.scala:214:27, :215:38] wire _GEN_29 = ~(\|state) \| _io_probe_rdy_T_2; // @[package.scala:16:47] assign io_lb_write_valid_0 = ~_GEN_29 & _io_probe_rdy_T_3 & opdata & io_mem_grant_valid_0; // @[package.scala:16:47] wire [7:0] _io_lb_write_bits_offset_T = refill_address_inc[11:4]; // @[Edges.scala:269:29] assign io_lb_write_bits_offset_0 = _io_lb_write_bits_offset_T[1:0]; // @[mshrs.scala:36:7, :238:{31,53}] assign io_mem_grant_ready_0 = ~_GEN_29 & _io_probe_rdy_T_3 & (~opdata \| io_lb_write_ready_0); // @[package.scala:16:47] wire _grantack_valid_T = io_mem_grant_bits_opcode_0[2]; // @[Edges.scala:71:36] wire _grantack_valid_T_1 = io_mem_grant_bits_opcode_0[1]; // @[Edges.scala:71:52] wire _grantack_valid_T_2 = ~_grantack_valid_T_1; // @[Edges.scala:71:{43,52}] wire _grantack_valid_T_3 = _grantack_valid_T & _grantack_valid_T_2; // @[Edges.scala:71:{36,40,43}] wire [4:0] _state_T_29 = grant_had_data ? 5'h3 : 5'hC; // @[mshrs.scala:141:27, :250:19] wire _drain_load_T = _rpq_io_deq_bits_uop_mem_cmd == 5'h0; // @[package.scala:16:47] wire _drain_load_T_1 = _rpq_io_deq_bits_uop_mem_cmd == 5'h10; // @[package.scala:16:47] wire _GEN_30 = _rpq_io_deq_bits_uop_mem_cmd == 5'h6; // @[package.scala:16:47] wire _drain_load_T_2; // @[package.scala:16:47] assign _drain_load_T_2 = _GEN_30; // @[package.scala:16:47] wire _r_c_cat_T_48; // @[Consts.scala:91:71] assign _r_c_cat_T_48 = _GEN_30; // @[package.scala:16:47] wire _GEN_31 = _rpq_io_deq_bits_uop_mem_cmd == 5'h7; // @[package.scala:16:47] wire _drain_load_T_3; // @[package.scala:16:47] assign _drain_load_T_3 = _GEN_31; // @[package.scala:16:47] wire _drain_load_T_28; // @[Consts.scala:90:66] assign _drain_load_T_28 = _GEN_31; // @[package.scala:16:47] wire _drain_load_T_4 = _drain_load_T \| _drain_load_T_1; // @[package.scala:16:47, :81:59] wire _drain_load_T_5 = _drain_load_T_4 \| _drain_load_T_2; // @[package.scala:16:47, :81:59] wire _drain_load_T_6 = _drain_load_T_5 \| _drain_load_T_3; // @[package.scala:16:47, :81:59] wire _GEN_32 = _rpq_io_deq_bits_uop_mem_cmd == 5'h4; // @[package.scala:16:47] wire _drain_load_T_7; // @[package.scala:16:47] assign _drain_load_T_7 = _GEN_32; // @[package.scala:16:47] wire _drain_load_T_30; // @[package.scala:16:47] assign _drain_load_T_30 = _GEN_32; // @[package.scala:16:47] wire _GEN_33 = _rpq_io_deq_bits_uop_mem_cmd == 5'h9; // @[package.scala:16:47] wire _drain_load_T_8; // @[package.scala:16:47] assign _drain_load_T_8 = _GEN_33; // @[package.scala:16:47] wire _drain_load_T_31; // @[package.scala:16:47] assign _drain_load_T_31 = _GEN_33; // @[package.scala:16:47] wire _GEN_34 = _rpq_io_deq_bits_uop_mem_cmd == 5'hA; // @[package.scala:16:47] wire _drain_load_T_9; // @[package.scala:16:47] assign _drain_load_T_9 = _GEN_34; // @[package.scala:16:47] wire _drain_load_T_32; // @[package.scala:16:47] assign _drain_load_T_32 = _GEN_34; // @[package.scala:16:47] wire _GEN_35 = _rpq_io_deq_bits_uop_mem_cmd == 5'hB; // @[package.scala:16:47] wire _drain_load_T_10; // @[package.scala:16:47] assign _drain_load_T_10 = _GEN_35; // @[package.scala:16:47] wire _drain_load_T_33; // @[package.scala:16:47] assign _drain_load_T_33 = _GEN_35; // @[package.scala:16:47] wire _drain_load_T_11 = _drain_load_T_7 \| _drain_load_T_8; // @[package.scala:16:47, :81:59] wire _drain_load_T_12 = _drain_load_T_11 \| _drain_load_T_9; // @[package.scala:16:47, :81:59] wire _drain_load_T_13 = _drain_load_T_12 \| _drain_load_T_10; // @[package.scala:16:47, :81:59] wire _GEN_36 = _rpq_io_deq_bits_uop_mem_cmd == 5'h8; // @[package.scala:16:47] wire _drain_load_T_14; // @[package.scala:16:47] assign _drain_load_T_14 = _GEN_36; // @[package.scala:16:47] wire _drain_load_T_37; // @[package.scala:16:47] assign _drain_load_T_37 = _GEN_36; // @[package.scala:16:47] wire _GEN_37 = _rpq_io_deq_bits_uop_mem_cmd == 5'hC; // @[package.scala:16:47] wire _drain_load_T_15; // @[package.scala:16:47] assign _drain_load_T_15 = _GEN_37; // @[package.scala:16:47] wire _drain_load_T_38; // @[package.scala:16:47] assign _drain_load_T_38 = _GEN_37; // @[package.scala:16:47] wire _GEN_38 = _rpq_io_deq_bits_uop_mem_cmd == 5'hD; // @[package.scala:16:47] wire _drain_load_T_16; // @[package.scala:16:47] assign _drain_load_T_16 = _GEN_38; // @[package.scala:16:47] wire _drain_load_T_39; // @[package.scala:16:47] assign _drain_load_T_39 = _GEN_38; // @[package.scala:16:47] wire _GEN_39 = _rpq_io_deq_bits_uop_mem_cmd == 5'hE; // @[package.scala:16:47] wire _drain_load_T_17; // @[package.scala:16:47] assign _drain_load_T_17 = _GEN_39; // @[package.scala:16:47] wire _drain_load_T_40; // @[package.scala:16:47] assign _drain_load_T_40 = _GEN_39; // @[package.scala:16:47] wire _GEN_40 = _rpq_io_deq_bits_uop_mem_cmd == 5'hF; // @[package.scala:16:47] wire _drain_load_T_18; // @[package.scala:16:47] assign _drain_load_T_18 = _GEN_40; // @[package.scala:16:47] wire _drain_load_T_41; // @[package.scala:16:47] assign _drain_load_T_41 = _GEN_40; // @[package.scala:16:47] wire _drain_load_T_19 = _drain_load_T_14 \| _drain_load_T_15; // @[package.scala:16:47, :81:59] wire _drain_load_T_20 = _drain_load_T_19 \| _drain_load_T_16; // @[package.scala:16:47, :81:59] wire _drain_load_T_21 = _drain_load_T_20 \| _drain_load_T_17; // @[package.scala:16:47, :81:59] wire _drain_load_T_22 = _drain_load_T_21 \| _drain_load_T_18; // @[package.scala:16:47, :81:59] wire _drain_load_T_23 = _drain_load_T_13 \| _drain_load_T_22; // @[package.scala:81:59] wire _drain_load_T_24 = _drain_load_T_6 \| _drain_load_T_23; // @[package.scala:81:59] wire _drain_load_T_25 = _rpq_io_deq_bits_uop_mem_cmd == 5'h1; // @[Consts.scala:90:32] wire _drain_load_T_26 = _rpq_io_deq_bits_uop_mem_cmd == 5'h11; // @[Consts.scala:90:49] wire _drain_load_T_27 = _drain_load_T_25 \| _drain_load_T_26; // @[Consts.scala:90:{32,42,49}] wire _drain_load_T_29 = _drain_load_T_27 \| _drain_load_T_28; // @[Consts.scala:90:{42,59,66}] wire _drain_load_T_34 = _drain_load_T_30 \| _drain_load_T_31; // @[package.scala:16:47, :81:59] wire _drain_load_T_35 = _drain_load_T_34 \| _drain_load_T_32; // @[package.scala:16:47, :81:59] wire _drain_load_T_36 = _drain_load_T_35 \| _drain_load_T_33; // @[package.scala:16:47, :81:59] wire _drain_load_T_42 = _drain_load_T_37 \| _drain_load_T_38; // @[package.scala:16:47, :81:59] wire _drain_load_T_43 = _drain_load_T_42 \| _drain_load_T_39; // @[package.scala:16:47, :81:59] wire _drain_load_T_44 = _drain_load_T_43 \| _drain_load_T_40; // @[package.scala:16:47, :81:59] wire _drain_load_T_45 = _drain_load_T_44 \| _drain_load_T_41; // @[package.scala:16:47, :81:59] wire _drain_load_T_46 = _drain_load_T_36 \| _drain_load_T_45; // @[package.scala:81:59] wire _drain_load_T_47 = _drain_load_T_29 \| _drain_load_T_46; // @[Consts.scala:87:44, :90:{59,76}] wire _drain_load_T_48 = ~_drain_load_T_47; // @[Consts.scala:90:76] wire _drain_load_T_49 = _drain_load_T_24 & _drain_load_T_48; // @[Consts.scala:89:68] wire _drain_load_T_50 = _rpq_io_deq_bits_uop_mem_cmd != 5'h6; // @[mshrs.scala:128:19, :259:51] wire drain_load = _drain_load_T_49 & _drain_load_T_50; // @[mshrs.scala:257:59, :258:60, :259:51] wire [5:0] _rp_addr_T = _rpq_io_deq_bits_addr[5:0]; // @[mshrs.scala:128:19, :261:61] wire [39:0] rp_addr = {rp_addr_hi, _rp_addr_T}; // @[mshrs.scala:261:{22,61}] wire word_idx = rp_addr[3]; // @[mshrs.scala:261:22, :262:56] wire [6:0] _data_word_T = {word_idx, 6'h0}; // @[mshrs.scala:262:56, :264:32] wire [127:0] data_word = io_lb_resp_0 >> _data_word_T; // @[mshrs.scala:36:7, :264:{26,32}] wire [1:0] size; // @[AMOALU.scala:11:18] wire _rpq_io_deq_ready_T = io_resp_ready_0 & io_lb_read_ready_0; // @[mshrs.scala:36:7, :270:45] wire _rpq_io_deq_ready_T_1 = _rpq_io_deq_ready_T & drain_load; // @[mshrs.scala:258:60, :270:{45,65}] wire _io_lb_read_valid_T = _rpq_io_deq_valid & drain_load; // @[mshrs.scala:128:19, :258:60, :271:48] wire [35:0] _io_lb_read_bits_offset_T = _rpq_io_deq_bits_addr[39:4]; // @[mshrs.scala:128:19, :273:52] wire _GEN_41 = io_lb_read_ready_0 & io_lb_read_valid_0; // @[Decoupled.scala:51:35] wire _io_resp_valid_T; // @[Decoupled.scala:51:35] assign _io_resp_valid_T = _GEN_41; // @[Decoupled.scala:51:35] wire _io_refill_valid_T; // @[Decoupled.scala:51:35] assign _io_refill_valid_T = _GEN_41; // @[Decoupled.scala:51:35] wire _io_resp_valid_T_1 = _rpq_io_deq_valid & _io_resp_valid_T; // @[Decoupled.scala:51:35] wire _io_resp_valid_T_2 = _io_resp_valid_T_1 & drain_load; // @[mshrs.scala:258:60, :275:{43,62}] wire _GEN_42 = ~(\|state) \| _io_probe_rdy_T_2 \| _io_probe_rdy_T_3; // @[package.scala:16:47] assign io_resp_valid_0 = ~_GEN_42 & _io_probe_rdy_T_4 & _io_resp_valid_T_2; // @[package.scala:16:47] wire _io_resp_bits_data_shifted_T = _rpq_io_deq_bits_addr[2]; // @[AMOALU.scala:42:29] wire [31:0] _io_resp_bits_data_shifted_T_1 = data_word[63:32]; // @[AMOALU.scala:42:37] wire [31:0] _io_resp_bits_data_T_5 = data_word[63:32]; // @[AMOALU.scala:42:37, :45:94] wire [31:0] _io_resp_bits_data_shifted_T_2 = data_word[31:0]; // @[AMOALU.scala:42:55] wire [31:0] io_resp_bits_data_shifted = _io_resp_bits_data_shifted_T ? _io_resp_bits_data_shifted_T_1 : _io_resp_bits_data_shifted_T_2; // @[AMOALU.scala:42:{24,29,37,55}] wire [31:0] io_resp_bits_data_zeroed = io_resp_bits_data_shifted; // @[AMOALU.scala:42:24, :44:23] wire _io_resp_bits_data_T = size == 2'h2; // @[AMOALU.scala:11:18, :45:26] wire _io_resp_bits_data_T_1 = _io_resp_bits_data_T; // @[AMOALU.scala:45:{26,34}] wire _io_resp_bits_data_T_2 = io_resp_bits_data_zeroed[31]; // @[AMOALU.scala:44:23, :45:81] wire _io_resp_bits_data_T_3 = _rpq_io_deq_bits_uop_mem_signed & _io_resp_bits_data_T_2; // @[AMOALU.scala:45:{72,81}] wire [31:0] _io_resp_bits_data_T_4 = {32{_io_resp_bits_data_T_3}}; // @[AMOALU.scala:45:{49,72}] wire [31:0] _io_resp_bits_data_T_6 = _io_resp_bits_data_T_1 ? _io_resp_bits_data_T_4 : _io_resp_bits_data_T_5; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _io_resp_bits_data_T_7 = {_io_resp_bits_data_T_6, io_resp_bits_data_zeroed}; // @[AMOALU.scala:44:23, :45:{16,20}] wire _io_resp_bits_data_shifted_T_3 = _rpq_io_deq_bits_addr[1]; // @[AMOALU.scala:42:29] wire [15:0] _io_resp_bits_data_shifted_T_4 = _io_resp_bits_data_T_7[31:16]; // @[AMOALU.scala:42:37, :45:16] wire [15:0] _io_resp_bits_data_shifted_T_5 = _io_resp_bits_data_T_7[15:0]; // @[AMOALU.scala:42:55, :45:16] wire [15:0] io_resp_bits_data_shifted_1 = _io_resp_bits_data_shifted_T_3 ? _io_resp_bits_data_shifted_T_4 : _io_resp_bits_data_shifted_T_5; // @[AMOALU.scala:42:{24,29,37,55}] wire [15:0] io_resp_bits_data_zeroed_1 = io_resp_bits_data_shifted_1; // @[AMOALU.scala:42:24, :44:23] wire _io_resp_bits_data_T_8 = size == 2'h1; // @[AMOALU.scala:11:18, :45:26] wire _io_resp_bits_data_T_9 = _io_resp_bits_data_T_8; // @[AMOALU.scala:45:{26,34}] wire _io_resp_bits_data_T_10 = io_resp_bits_data_zeroed_1[15]; // @[AMOALU.scala:44:23, :45:81] wire _io_resp_bits_data_T_11 = _rpq_io_deq_bits_uop_mem_signed & _io_resp_bits_data_T_10; // @[AMOALU.scala:45:{72,81}] wire [47:0] _io_resp_bits_data_T_12 = {48{_io_resp_bits_data_T_11}}; // @[AMOALU.scala:45:{49,72}] wire [47:0] _io_resp_bits_data_T_13 = _io_resp_bits_data_T_7[63:16]; // @[AMOALU.scala:45:{16,94}] wire [47:0] _io_resp_bits_data_T_14 = _io_resp_bits_data_T_9 ? _io_resp_bits_data_T_12 : _io_resp_bits_data_T_13; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _io_resp_bits_data_T_15 = {_io_resp_bits_data_T_14, io_resp_bits_data_zeroed_1}; // @[AMOALU.scala:44:23, :45:{16,20}] wire _io_resp_bits_data_shifted_T_6 = _rpq_io_deq_bits_addr[0]; // @[AMOALU.scala:42:29] wire [7:0] _io_resp_bits_data_shifted_T_7 = _io_resp_bits_data_T_15[15:8]; // @[AMOALU.scala:42:37, :45:16] wire [7:0] _io_resp_bits_data_shifted_T_8 = _io_resp_bits_data_T_15[7:0]; // @[AMOALU.scala:42:55, :45:16] wire [7:0] io_resp_bits_data_shifted_2 = _io_resp_bits_data_shifted_T_6 ? _io_resp_bits_data_shifted_T_7 : _io_resp_bits_data_shifted_T_8; // @[AMOALU.scala:42:{24,29,37,55}] wire [7:0] io_resp_bits_data_zeroed_2 = io_resp_bits_data_shifted_2; // @[AMOALU.scala:42:24, :44:23] wire _io_resp_bits_data_T_16 = size == 2'h0; // @[AMOALU.scala:11:18, :45:26] wire _io_resp_bits_data_T_17 = _io_resp_bits_data_T_16; // @[AMOALU.scala:45:{26,34}] wire _io_resp_bits_data_T_18 = io_resp_bits_data_zeroed_2[7]; // @[AMOALU.scala:44:23, :45:81] wire _io_resp_bits_data_T_19 = _rpq_io_deq_bits_uop_mem_signed & _io_resp_bits_data_T_18; // @[AMOALU.scala:45:{72,81}] wire [55:0] _io_resp_bits_data_T_20 = {56{_io_resp_bits_data_T_19}}; // @[AMOALU.scala:45:{49,72}] wire [55:0] _io_resp_bits_data_T_21 = _io_resp_bits_data_T_15[63:8]; // @[AMOALU.scala:45:{16,94}] wire [55:0] _io_resp_bits_data_T_22 = _io_resp_bits_data_T_17 ? _io_resp_bits_data_T_20 : _io_resp_bits_data_T_21; // @[AMOALU.scala:45:{20,34,49,94}] assign _io_resp_bits_data_T_23 = {_io_resp_bits_data_T_22, io_resp_bits_data_zeroed_2}; // @[AMOALU.scala:44:23, :45:{16,20}] assign io_resp_bits_data_0 = _io_resp_bits_data_T_23; // @[AMOALU.scala:45:16] wire _T_26 = rpq_io_deq_ready & _rpq_io_deq_valid; // @[Decoupled.scala:51:35] wire _T_28 = _rpq_io_empty & ~commit_line; // @[mshrs.scala:128:19, :140:24, :282:{31,34}] wire _T_33 = _rpq_io_empty \| _rpq_io_deq_valid & ~drain_load; // @[mshrs.scala:128:19, :258:60, :288:{31,52,55}] assign io_commit_val_0 = ~_GEN_42 & _io_probe_rdy_T_4 & ~(_T_26 \| _T_28) & _T_33; // @[Decoupled.scala:51:35] wire _io_meta_read_valid_T = ~io_prober_state_valid_0; // @[mshrs.scala:36:7, :295:27] wire _io_meta_read_valid_T_1 = ~grantack_valid; // @[mshrs.scala:138:21, :295:53] wire _io_meta_read_valid_T_2 = _io_meta_read_valid_T \| _io_meta_read_valid_T_1; // @[mshrs.scala:295:{27,50,53}] wire [5:0] _io_meta_read_valid_T_3 = io_prober_state_bits_0[11:6]; // @[mshrs.scala:36:7, :295:93] wire _io_meta_read_valid_T_4 = _io_meta_read_valid_T_3 != req_idx; // @[mshrs.scala:110:25, :295:{93,120}] wire _io_meta_read_valid_T_5 = _io_meta_read_valid_T_2 \| _io_meta_read_valid_T_4; // @[mshrs.scala:295:{50,69,120}] assign io_meta_read_valid_0 = ~(~(\|state) \| _io_probe_rdy_T_2 \| _io_probe_rdy_T_3 \| _io_probe_rdy_T_4) & _io_probe_rdy_T_8 & _io_meta_read_valid_T_5; // @[package.scala:16:47] assign io_meta_write_bits_data_tag_0 = req_tag[19:0]; // @[mshrs.scala:36:7, :111:26, :297:27] assign io_meta_read_bits_tag_0 = req_tag[19:0]; // @[mshrs.scala:36:7, :111:26, :297:27] wire _T_36 = state == 5'h5; // @[mshrs.scala:107:22, :302:22] wire _T_37 = state == 5'h6; // @[mshrs.scala:107:22, :304:22] wire [3:0] _needs_wb_r_T_6 = {2'h2, io_meta_resp_bits_coh_state_0}; // @[Metadata.scala:120:19] wire _needs_wb_r_T_19 = _needs_wb_r_T_6 == 4'h8; // @[Misc.scala:56:20] wire [2:0] _needs_wb_r_T_21 = _needs_wb_r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_23 = _needs_wb_r_T_6 == 4'h9; // @[Misc.scala:56:20] wire [2:0] _needs_wb_r_T_25 = _needs_wb_r_T_23 ? 3'h2 : _needs_wb_r_T_21; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_27 = _needs_wb_r_T_6 == 4'hA; // @[Misc.scala:56:20] wire [2:0] _needs_wb_r_T_29 = _needs_wb_r_T_27 ? 3'h1 : _needs_wb_r_T_25; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_31 = _needs_wb_r_T_6 == 4'hB; // @[Misc.scala:56:20] wire _needs_wb_r_T_32 = _needs_wb_r_T_31; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_33 = _needs_wb_r_T_31 ? 3'h1 : _needs_wb_r_T_29; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_35 = _needs_wb_r_T_6 == 4'h4; // @[Misc.scala:56:20] wire _needs_wb_r_T_36 = ~_needs_wb_r_T_35 & _needs_wb_r_T_32; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_37 = _needs_wb_r_T_35 ? 3'h5 : _needs_wb_r_T_33; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_39 = _needs_wb_r_T_6 == 4'h5; // @[Misc.scala:56:20] wire _needs_wb_r_T_40 = ~_needs_wb_r_T_39 & _needs_wb_r_T_36; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_41 = _needs_wb_r_T_39 ? 3'h4 : _needs_wb_r_T_37; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_42 = {1'h0, _needs_wb_r_T_39}; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_43 = _needs_wb_r_T_6 == 4'h6; // @[Misc.scala:56:20] wire _needs_wb_r_T_44 = ~_needs_wb_r_T_43 & _needs_wb_r_T_40; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_45 = _needs_wb_r_T_43 ? 3'h0 : _needs_wb_r_T_41; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_46 = _needs_wb_r_T_43 ? 2'h1 : _needs_wb_r_T_42; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_47 = _needs_wb_r_T_6 == 4'h7; // @[Misc.scala:56:20] wire _needs_wb_r_T_48 = _needs_wb_r_T_47 \| _needs_wb_r_T_44; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_49 = _needs_wb_r_T_47 ? 3'h0 : _needs_wb_r_T_45; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_50 = _needs_wb_r_T_47 ? 2'h1 : _needs_wb_r_T_46; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_51 = _needs_wb_r_T_6 == 4'h0; // @[Misc.scala:56:20] wire _needs_wb_r_T_52 = ~_needs_wb_r_T_51 & _needs_wb_r_T_48; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_53 = _needs_wb_r_T_51 ? 3'h5 : _needs_wb_r_T_49; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_54 = _needs_wb_r_T_51 ? 2'h0 : _needs_wb_r_T_50; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_55 = _needs_wb_r_T_6 == 4'h1; // @[Misc.scala:56:20] wire _needs_wb_r_T_56 = ~_needs_wb_r_T_55 & _needs_wb_r_T_52; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_57 = _needs_wb_r_T_55 ? 3'h4 : _needs_wb_r_T_53; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_58 = _needs_wb_r_T_55 ? 2'h1 : _needs_wb_r_T_54; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_59 = _needs_wb_r_T_6 == 4'h2; // @[Misc.scala:56:20] wire _needs_wb_r_T_60 = ~_needs_wb_r_T_59 & _needs_wb_r_T_56; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_61 = _needs_wb_r_T_59 ? 3'h3 : _needs_wb_r_T_57; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_62 = _needs_wb_r_T_59 ? 2'h2 : _needs_wb_r_T_58; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_63 = _needs_wb_r_T_6 == 4'h3; // @[Misc.scala:56:20] wire needs_wb = _needs_wb_r_T_63 \| _needs_wb_r_T_60; // @[Misc.scala:38:9, :56:20] wire [2:0] needs_wb_r_2 = _needs_wb_r_T_63 ? 3'h3 : _needs_wb_r_T_61; // @[Misc.scala:38:36, :56:20] wire [1:0] needs_wb_r_3 = _needs_wb_r_T_63 ? 2'h2 : _needs_wb_r_T_62; // @[Misc.scala:38:63, :56:20] wire [1:0] needs_wb_meta_state = needs_wb_r_3; // @[Misc.scala:38:63] wire _state_T_30 = ~io_meta_resp_valid_0; // @[mshrs.scala:36:7, :306:18] wire [4:0] _state_T_31 = needs_wb ? 5'h7 : 5'hB; // @[Misc.scala:38:9] wire [4:0] _state_T_32 = _state_T_30 ? 5'h4 : _state_T_31; // @[mshrs.scala:306:{17,18}, :307:17] wire _T_38 = state == 5'h7; // @[mshrs.scala:107:22, :308:22] wire _T_40 = state == 5'h9; // @[mshrs.scala:107:22, :318:22] assign io_wb_req_valid_0 = ~(~(\|state) \| _io_probe_rdy_T_2 \| _io_probe_rdy_T_3 \| _io_probe_rdy_T_4 \| _io_probe_rdy_T_8 \| _T_36 \| _T_37 \| _T_38) & _T_40; // @[package.scala:16:47] wire _T_42 = state == 5'hA; // @[mshrs.scala:107:22, :330:22] wire _T_43 = state == 5'hB; // @[mshrs.scala:107:22, :334:22] wire _GEN_43 = _io_probe_rdy_T_8 \| _T_36 \| _T_37 \| _T_38 \| _T_40 \| _T_42; // @[mshrs.scala:148:129, :179:26, :294:39, :302:{22,41}, :304:{22,41}, :308:{22,40}, :318:{22,36}, :330:{22,37}, :334:41] assign io_lb_read_valid_0 = ~_GEN_42 & (_io_probe_rdy_T_4 ? _io_lb_read_valid_T : ~_GEN_43 & _T_43); // @[package.scala:16:47] assign io_lb_read_bits_offset_0 = _io_probe_rdy_T_4 ? _io_lb_read_bits_offset_T[1:0] : refill_ctr; // @[package.scala:16:47] wire _GEN_44 = _io_probe_rdy_T_2 \| _io_probe_rdy_T_3 \| _io_probe_rdy_T_4 \| _GEN_43; // @[package.scala:16:47] assign io_refill_valid_0 = ~(~(\|state) \| _GEN_44) & _T_43 & _io_refill_valid_T; // @[Decoupled.scala:51:35] wire [5:0] _io_refill_bits_addr_T = {refill_ctr, 4'h0}; // @[mshrs.scala:139:24, :340:59] wire [39:0] _io_refill_bits_addr_T_1 = {req_block_addr[39:6], req_block_addr[5:0] \| _io_refill_bits_addr_T}; // @[mshrs.scala:112:51, :340:{45,59}] assign io_refill_bits_addr_0 = _io_refill_bits_addr_T_1[11:0]; // @[mshrs.scala:36:7, :340:{27,45}] wire [2:0] _refill_ctr_T = {1'h0, refill_ctr} + 3'h1; // @[mshrs.scala:139:24, :345:32] wire [1:0] _refill_ctr_T_1 = _refill_ctr_T[1:0]; // @[mshrs.scala:345:32] wire _T_46 = state == 5'hC; // @[mshrs.scala:107:22, :350:22] wire _GEN_45 = _io_probe_rdy_T_8 \| _T_36 \| _T_37 \| _T_38 \| _T_40 \| _T_42 \| _T_43; // @[mshrs.scala:148:129, :164:26, :294:39, :302:{22,41}, :304:{22,41}, :308:{22,40}, :318:{22,36}, :330:{22,37}, :334:{22,41}, :350:39] wire _GEN_46 = _io_probe_rdy_T_4 \| _GEN_45; // @[package.scala:16:47] assign io_replay_valid_0 = ~(~(\|state) \| _io_probe_rdy_T_2 \| _io_probe_rdy_T_3 \| _GEN_46) & _T_46 & _rpq_io_deq_valid; // @[package.scala:16:47] assign rpq_io_deq_ready = ~_GEN_42 & (_io_probe_rdy_T_4 ? _rpq_io_deq_ready_T_1 : ~_GEN_45 & _T_46 & io_replay_ready_0); // @[package.scala:16:47] wire [5:0] _io_replay_bits_addr_T = _rpq_io_deq_bits_addr[5:0]; // @[mshrs.scala:128:19, :353:70] assign _io_replay_bits_addr_T_1 = {io_replay_bits_addr_hi, _io_replay_bits_addr_T}; // @[mshrs.scala:353:{31,70}] assign io_replay_bits_addr_0 = _io_replay_bits_addr_T_1; // @[mshrs.scala:36:7, :353:31] wire _T_48 = _rpq_io_deq_bits_uop_mem_cmd == 5'h1; // @[Consts.scala:90:32] wire _r_c_cat_T; // @[Consts.scala:90:32] assign _r_c_cat_T = _T_48; // @[Consts.scala:90:32] wire _r_c_cat_T_23; // @[Consts.scala:90:32] assign _r_c_cat_T_23 = _T_48; // @[Consts.scala:90:32] wire _T_49 = _rpq_io_deq_bits_uop_mem_cmd == 5'h11; // @[Consts.scala:90:49] wire _r_c_cat_T_1; // @[Consts.scala:90:49] assign _r_c_cat_T_1 = _T_49; // @[Consts.scala:90:49] wire _r_c_cat_T_24; // @[Consts.scala:90:49] assign _r_c_cat_T_24 = _T_49; // @[Consts.scala:90:49] wire _T_51 = _rpq_io_deq_bits_uop_mem_cmd == 5'h7; // @[Consts.scala:90:66] wire _r_c_cat_T_3; // @[Consts.scala:90:66] assign _r_c_cat_T_3 = _T_51; // @[Consts.scala:90:66] wire _r_c_cat_T_26; // @[Consts.scala:90:66] assign _r_c_cat_T_26 = _T_51; // @[Consts.scala:90:66] wire _T_53 = _rpq_io_deq_bits_uop_mem_cmd == 5'h4; // @[package.scala:16:47] wire _r_c_cat_T_5; // @[package.scala:16:47] assign _r_c_cat_T_5 = _T_53; // @[package.scala:16:47] wire _r_c_cat_T_28; // @[package.scala:16:47] assign _r_c_cat_T_28 = _T_53; // @[package.scala:16:47] wire _T_54 = _rpq_io_deq_bits_uop_mem_cmd == 5'h9; // @[package.scala:16:47] wire _r_c_cat_T_6; // @[package.scala:16:47] assign _r_c_cat_T_6 = _T_54; // @[package.scala:16:47] wire _r_c_cat_T_29; // @[package.scala:16:47] assign _r_c_cat_T_29 = _T_54; // @[package.scala:16:47] wire _T_55 = _rpq_io_deq_bits_uop_mem_cmd == 5'hA; // @[package.scala:16:47] wire _r_c_cat_T_7; // @[package.scala:16:47] assign _r_c_cat_T_7 = _T_55; // @[package.scala:16:47] wire _r_c_cat_T_30; // @[package.scala:16:47] assign _r_c_cat_T_30 = _T_55; // @[package.scala:16:47] wire _T_56 = _rpq_io_deq_bits_uop_mem_cmd == 5'hB; // @[package.scala:16:47] wire _r_c_cat_T_8; // @[package.scala:16:47] assign _r_c_cat_T_8 = _T_56; // @[package.scala:16:47] wire _r_c_cat_T_31; // @[package.scala:16:47] assign _r_c_cat_T_31 = _T_56; // @[package.scala:16:47] wire _T_60 = _rpq_io_deq_bits_uop_mem_cmd == 5'h8; // @[package.scala:16:47] wire _r_c_cat_T_12; // @[package.scala:16:47] assign _r_c_cat_T_12 = _T_60; // @[package.scala:16:47] wire _r_c_cat_T_35; // @[package.scala:16:47] assign _r_c_cat_T_35 = _T_60; // @[package.scala:16:47] wire _T_61 = _rpq_io_deq_bits_uop_mem_cmd == 5'hC; // @[package.scala:16:47] wire _r_c_cat_T_13; // @[package.scala:16:47] assign _r_c_cat_T_13 = _T_61; // @[package.scala:16:47] wire _r_c_cat_T_36; // @[package.scala:16:47] assign _r_c_cat_T_36 = _T_61; // @[package.scala:16:47] wire _T_62 = _rpq_io_deq_bits_uop_mem_cmd == 5'hD; // @[package.scala:16:47] wire _r_c_cat_T_14; // @[package.scala:16:47] assign _r_c_cat_T_14 = _T_62; // @[package.scala:16:47] wire _r_c_cat_T_37; // @[package.scala:16:47] assign _r_c_cat_T_37 = _T_62; // @[package.scala:16:47] wire _T_63 = _rpq_io_deq_bits_uop_mem_cmd == 5'hE; // @[package.scala:16:47] wire _r_c_cat_T_15; // @[package.scala:16:47] assign _r_c_cat_T_15 = _T_63; // @[package.scala:16:47] wire _r_c_cat_T_38; // @[package.scala:16:47] assign _r_c_cat_T_38 = _T_63; // @[package.scala:16:47] wire _T_64 = _rpq_io_deq_bits_uop_mem_cmd == 5'hF; // @[package.scala:16:47] wire _r_c_cat_T_16; // @[package.scala:16:47] assign _r_c_cat_T_16 = _T_64; // @[package.scala:16:47] wire _r_c_cat_T_39; // @[package.scala:16:47] assign _r_c_cat_T_39 = _T_64; // @[package.scala:16:47] wire _T_71 = io_replay_ready_0 & io_replay_valid_0 & (_T_48 \| _T_49 \| _T_51 \| _T_53 \| _T_54 \| _T_55 \| _T_56 \| _T_60 \| _T_61 \| _T_62 \| _T_63 \| _T_64); // @[Decoupled.scala:51:35] wire _r_c_cat_T_2 = _r_c_cat_T \| _r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _r_c_cat_T_4 = _r_c_cat_T_2 \| _r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _r_c_cat_T_9 = _r_c_cat_T_5 \| _r_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_10 = _r_c_cat_T_9 \| _r_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_11 = _r_c_cat_T_10 \| _r_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_17 = _r_c_cat_T_12 \| _r_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_18 = _r_c_cat_T_17 \| _r_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_19 = _r_c_cat_T_18 \| _r_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_20 = _r_c_cat_T_19 \| _r_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_21 = _r_c_cat_T_11 \| _r_c_cat_T_20; // @[package.scala:81:59] wire _r_c_cat_T_22 = _r_c_cat_T_4 \| _r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _r_c_cat_T_25 = _r_c_cat_T_23 \| _r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _r_c_cat_T_27 = _r_c_cat_T_25 \| _r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _r_c_cat_T_32 = _r_c_cat_T_28 \| _r_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_33 = _r_c_cat_T_32 \| _r_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_34 = _r_c_cat_T_33 \| _r_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_40 = _r_c_cat_T_35 \| _r_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_41 = _r_c_cat_T_40 \| _r_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_42 = _r_c_cat_T_41 \| _r_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_43 = _r_c_cat_T_42 \| _r_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_44 = _r_c_cat_T_34 \| _r_c_cat_T_43; // @[package.scala:81:59] wire _r_c_cat_T_45 = _r_c_cat_T_27 \| _r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _r_c_cat_T_46 = _rpq_io_deq_bits_uop_mem_cmd == 5'h3; // @[Consts.scala:91:54] wire _r_c_cat_T_47 = _r_c_cat_T_45 \| _r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _r_c_cat_T_49 = _r_c_cat_T_47 \| _r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] r_c = {_r_c_cat_T_22, _r_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _r_T_64 = {r_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19] wire _r_T_89 = _r_T_64 == 4'hC; // @[Misc.scala:49:20] wire [1:0] _r_T_91 = {1'h0, _r_T_89}; // @[Misc.scala:35:36, :49:20] wire _r_T_92 = _r_T_64 == 4'hD; // @[Misc.scala:49:20] wire [1:0] _r_T_94 = _r_T_92 ? 2'h2 : _r_T_91; // @[Misc.scala:35:36, :49:20] wire _r_T_95 = _r_T_64 == 4'h4; // @[Misc.scala:49:20] wire [1:0] _r_T_97 = _r_T_95 ? 2'h1 : _r_T_94; // @[Misc.scala:35:36, :49:20] wire _r_T_98 = _r_T_64 == 4'h5; // @[Misc.scala:49:20] wire [1:0] _r_T_100 = _r_T_98 ? 2'h2 : _r_T_97; // @[Misc.scala:35:36, :49:20] wire _r_T_101 = _r_T_64 == 4'h0; // @[Misc.scala:49:20] wire [1:0] _r_T_103 = _r_T_101 ? 2'h0 : _r_T_100; // @[Misc.scala:35:36, :49:20] wire _r_T_104 = _r_T_64 == 4'hE; // @[Misc.scala:49:20] wire _r_T_105 = _r_T_104; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_106 = _r_T_104 ? 2'h3 : _r_T_103; // @[Misc.scala:35:36, :49:20] wire _r_T_107 = &_r_T_64; // @[Misc.scala:49:20] wire _r_T_108 = _r_T_107 \| _r_T_105; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_109 = _r_T_107 ? 2'h3 : _r_T_106; // @[Misc.scala:35:36, :49:20] wire _r_T_110 = _r_T_64 == 4'h6; // @[Misc.scala:49:20] wire _r_T_111 = _r_T_110 \| _r_T_108; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_112 = _r_T_110 ? 2'h2 : _r_T_109; // @[Misc.scala:35:36, :49:20] wire _r_T_113 = _r_T_64 == 4'h7; // @[Misc.scala:49:20] wire _r_T_114 = _r_T_113 \| _r_T_111; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_115 = _r_T_113 ? 2'h3 : _r_T_112; // @[Misc.scala:35:36, :49:20] wire _r_T_116 = _r_T_64 == 4'h1; // @[Misc.scala:49:20] wire _r_T_117 = _r_T_116 \| _r_T_114; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_118 = _r_T_116 ? 2'h1 : _r_T_115; // @[Misc.scala:35:36, :49:20] wire _r_T_119 = _r_T_64 == 4'h2; // @[Misc.scala:49:20] wire _r_T_120 = _r_T_119 \| _r_T_117; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_121 = _r_T_119 ? 2'h2 : _r_T_118; // @[Misc.scala:35:36, :49:20] wire _r_T_122 = _r_T_64 == 4'h3; // @[Misc.scala:49:20] wire is_hit = _r_T_122 \| _r_T_120; // @[Misc.scala:35:9, :49:20] wire [1:0] r_2_1 = _r_T_122 ? 2'h3 : _r_T_121; // @[Misc.scala:35:36, :49:20] wire [1:0] coh_on_hit_state = r_2_1; // @[Misc.scala:35:36] wire _GEN_47 = _T_40 \| _T_42 \| _T_43 \| _T_46; // @[mshrs.scala:156:26, :318:{22,36}, :330:{22,37}, :334:{22,41}, :350:{22,39}, :363:44] assign io_meta_write_valid_0 = ~(~(\|state) \| _io_probe_rdy_T_2 \| _io_probe_rdy_T_3 \| _io_probe_rdy_T_4 \| _io_probe_rdy_T_8 \| _T_36 \| _T_37) & (_T_38 \| ~_GEN_47 & _sec_rdy_T_4); // @[package.scala:16:47] assign io_meta_write_bits_data_coh_state_0 = _T_38 ? coh_on_clear_state : new_coh_state; // @[Metadata.scala:160:20] wire _GEN_48 = _io_probe_rdy_T_4 \| _io_probe_rdy_T_8 \| _T_36 \| _T_37 \| _T_38 \| _T_40 \| _T_42 \| _T_43 \| _T_46 \| _sec_rdy_T_4; // @[package.scala:16:47] assign io_mem_finish_valid_0 = ~(~(\|state) \| _io_probe_rdy_T_2 \| _io_probe_rdy_T_3 \| _GEN_48) & _sec_rdy_T_5 & grantack_valid; // @[package.scala:16:47] wire [4:0] _state_T_33 = finish_to_prefetch ? 5'h11 : 5'h0; // @[mshrs.scala:142:31, :381:17] wire _GEN_49 = _sec_rdy_T_4 \| _sec_rdy_T_5 \| _sec_rdy_T_6; // @[package.scala:16:47] wire _GEN_50 = _T_46 \| _GEN_49; // @[mshrs.scala:158:26, :350:{22,39}, :363:44, :373:42, :380:42, :382:38] wire _GEN_51 = _io_probe_rdy_T_4 \| _io_probe_rdy_T_8 \| _T_36 \| _T_37 \| _T_38 \| _T_40 \| _T_42 \| _T_43 \| _GEN_50; // @[package.scala:16:47] wire _GEN_52 = _io_probe_rdy_T_2 \| _io_probe_rdy_T_3 \| _GEN_51; // @[package.scala:16:47] assign io_req_pri_rdy_0 = ~(\|state) \| ~_GEN_52 & _io_way_valid_T_1; // @[package.scala:16:47] wire _T_87 = io_req_sec_val_0 & ~io_req_sec_rdy_0 \| io_clear_prefetch_0; // @[mshrs.scala:36:7, :384:{27,30,47}] wire _r_c_cat_T_52 = _r_c_cat_T_50 \| _r_c_cat_T_51; // @[Consts.scala:90:{32,42,49}] wire _r_c_cat_T_54 = _r_c_cat_T_52 \| _r_c_cat_T_53; // @[Consts.scala:90:{42,59,66}] wire _r_c_cat_T_59 = _r_c_cat_T_55 \| _r_c_cat_T_56; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_60 = _r_c_cat_T_59 \| _r_c_cat_T_57; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_61 = _r_c_cat_T_60 \| _r_c_cat_T_58; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_67 = _r_c_cat_T_62 \| _r_c_cat_T_63; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_68 = _r_c_cat_T_67 \| _r_c_cat_T_64; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_69 = _r_c_cat_T_68 \| _r_c_cat_T_65; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_70 = _r_c_cat_T_69 \| _r_c_cat_T_66; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_71 = _r_c_cat_T_61 \| _r_c_cat_T_70; // @[package.scala:81:59] wire _r_c_cat_T_72 = _r_c_cat_T_54 \| _r_c_cat_T_71; // @[Consts.scala:87:44, :90:{59,76}] wire _r_c_cat_T_75 = _r_c_cat_T_73 \| _r_c_cat_T_74; // @[Consts.scala:90:{32,42,49}] wire _r_c_cat_T_77 = _r_c_cat_T_75 \| _r_c_cat_T_76; // @[Consts.scala:90:{42,59,66}] wire _r_c_cat_T_82 = _r_c_cat_T_78 \| _r_c_cat_T_79; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_83 = _r_c_cat_T_82 \| _r_c_cat_T_80; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_84 = _r_c_cat_T_83 \| _r_c_cat_T_81; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_90 = _r_c_cat_T_85 \| _r_c_cat_T_86; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_91 = _r_c_cat_T_90 \| _r_c_cat_T_87; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_92 = _r_c_cat_T_91 \| _r_c_cat_T_88; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_93 = _r_c_cat_T_92 \| _r_c_cat_T_89; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_94 = _r_c_cat_T_84 \| _r_c_cat_T_93; // @[package.scala:81:59] wire _r_c_cat_T_95 = _r_c_cat_T_77 \| _r_c_cat_T_94; // @[Consts.scala:87:44, :90:{59,76}] wire _r_c_cat_T_97 = _r_c_cat_T_95 \| _r_c_cat_T_96; // @[Consts.scala:90:76, :91:{47,54}] wire _r_c_cat_T_99 = _r_c_cat_T_97 \| _r_c_cat_T_98; // @[Consts.scala:91:{47,64,71}] wire [1:0] r_c_1 = {_r_c_cat_T_72, _r_c_cat_T_99}; // @[Metadata.scala:29:18] wire [3:0] _r_T_123 = {r_c_1, new_coh_state}; // @[Metadata.scala:29:18, :58:19] wire _r_T_148 = _r_T_123 == 4'hC; // @[Misc.scala:49:20] wire [1:0] _r_T_150 = {1'h0, _r_T_148}; // @[Misc.scala:35:36, :49:20] wire _r_T_151 = _r_T_123 == 4'hD; // @[Misc.scala:49:20] wire [1:0] _r_T_153 = _r_T_151 ? 2'h2 : _r_T_150; // @[Misc.scala:35:36, :49:20] wire _r_T_154 = _r_T_123 == 4'h4; // @[Misc.scala:49:20] wire [1:0] _r_T_156 = _r_T_154 ? 2'h1 : _r_T_153; // @[Misc.scala:35:36, :49:20] wire _r_T_157 = _r_T_123 == 4'h5; // @[Misc.scala:49:20] wire [1:0] _r_T_159 = _r_T_157 ? 2'h2 : _r_T_156; // @[Misc.scala:35:36, :49:20] wire _r_T_160 = _r_T_123 == 4'h0; // @[Misc.scala:49:20] wire [1:0] _r_T_162 = _r_T_160 ? 2'h0 : _r_T_159; // @[Misc.scala:35:36, :49:20] wire _r_T_163 = _r_T_123 == 4'hE; // @[Misc.scala:49:20] wire _r_T_164 = _r_T_163; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_165 = _r_T_163 ? 2'h3 : _r_T_162; // @[Misc.scala:35:36, :49:20] wire _r_T_166 = &_r_T_123; // @[Misc.scala:49:20] wire _r_T_167 = _r_T_166 \| _r_T_164; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_168 = _r_T_166 ? 2'h3 : _r_T_165; // @[Misc.scala:35:36, :49:20] wire _r_T_169 = _r_T_123 == 4'h6; // @[Misc.scala:49:20] wire _r_T_170 = _r_T_169 \| _r_T_167; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_171 = _r_T_169 ? 2'h2 : _r_T_168; // @[Misc.scala:35:36, :49:20] wire _r_T_172 = _r_T_123 == 4'h7; // @[Misc.scala:49:20] wire _r_T_173 = _r_T_172 \| _r_T_170; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_174 = _r_T_172 ? 2'h3 : _r_T_171; // @[Misc.scala:35:36, :49:20] wire _r_T_175 = _r_T_123 == 4'h1; // @[Misc.scala:49:20] wire _r_T_176 = _r_T_175 \| _r_T_173; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_177 = _r_T_175 ? 2'h1 : _r_T_174; // @[Misc.scala:35:36, :49:20] wire _r_T_178 = _r_T_123 == 4'h2; // @[Misc.scala:49:20] wire _r_T_179 = _r_T_178 \| _r_T_176; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_180 = _r_T_178 ? 2'h2 : _r_T_177; // @[Misc.scala:35:36, :49:20] wire _r_T_181 = _r_T_123 == 4'h3; // @[Misc.scala:49:20] wire is_hit_1 = _r_T_181 \| _r_T_179; // @[Misc.scala:35:9, :49:20] wire [1:0] r_2_2 = _r_T_181 ? 2'h3 : _r_T_180; // @[Misc.scala:35:36, :49:20] wire [1:0] coh_on_hit_1_state = r_2_2; // @[Misc.scala:35:36] wire [4:0] state_new_state_1; // @[mshrs.scala:191:29] wire _state_T_35 = ~_state_T_34; // @[mshrs.scala:194:11] wire _state_T_36 = ~_rpq_io_enq_ready; // @[mshrs.scala:128:19, :194:11] wire _state_req_needs_wb_r_T_83 = _state_req_needs_wb_r_T_70 == 4'h8; // @[Misc.scala:56:20] wire [2:0] _state_req_needs_wb_r_T_85 = _state_req_needs_wb_r_T_83 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_87 = _state_req_needs_wb_r_T_70 == 4'h9; // @[Misc.scala:56:20] wire [2:0] _state_req_needs_wb_r_T_89 = _state_req_needs_wb_r_T_87 ? 3'h2 : _state_req_needs_wb_r_T_85; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_91 = _state_req_needs_wb_r_T_70 == 4'hA; // @[Misc.scala:56:20] wire [2:0] _state_req_needs_wb_r_T_93 = _state_req_needs_wb_r_T_91 ? 3'h1 : _state_req_needs_wb_r_T_89; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_95 = _state_req_needs_wb_r_T_70 == 4'hB; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_96 = _state_req_needs_wb_r_T_95; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_97 = _state_req_needs_wb_r_T_95 ? 3'h1 : _state_req_needs_wb_r_T_93; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_99 = _state_req_needs_wb_r_T_70 == 4'h4; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_100 = ~_state_req_needs_wb_r_T_99 & _state_req_needs_wb_r_T_96; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_101 = _state_req_needs_wb_r_T_99 ? 3'h5 : _state_req_needs_wb_r_T_97; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_103 = _state_req_needs_wb_r_T_70 == 4'h5; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_104 = ~_state_req_needs_wb_r_T_103 & _state_req_needs_wb_r_T_100; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_105 = _state_req_needs_wb_r_T_103 ? 3'h4 : _state_req_needs_wb_r_T_101; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_106 = {1'h0, _state_req_needs_wb_r_T_103}; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_107 = _state_req_needs_wb_r_T_70 == 4'h6; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_108 = ~_state_req_needs_wb_r_T_107 & _state_req_needs_wb_r_T_104; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_109 = _state_req_needs_wb_r_T_107 ? 3'h0 : _state_req_needs_wb_r_T_105; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_110 = _state_req_needs_wb_r_T_107 ? 2'h1 : _state_req_needs_wb_r_T_106; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_111 = _state_req_needs_wb_r_T_70 == 4'h7; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_112 = _state_req_needs_wb_r_T_111 \| _state_req_needs_wb_r_T_108; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_113 = _state_req_needs_wb_r_T_111 ? 3'h0 : _state_req_needs_wb_r_T_109; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_114 = _state_req_needs_wb_r_T_111 ? 2'h1 : _state_req_needs_wb_r_T_110; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_115 = _state_req_needs_wb_r_T_70 == 4'h0; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_116 = ~_state_req_needs_wb_r_T_115 & _state_req_needs_wb_r_T_112; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_117 = _state_req_needs_wb_r_T_115 ? 3'h5 : _state_req_needs_wb_r_T_113; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_118 = _state_req_needs_wb_r_T_115 ? 2'h0 : _state_req_needs_wb_r_T_114; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_119 = _state_req_needs_wb_r_T_70 == 4'h1; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_120 = ~_state_req_needs_wb_r_T_119 & _state_req_needs_wb_r_T_116; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_121 = _state_req_needs_wb_r_T_119 ? 3'h4 : _state_req_needs_wb_r_T_117; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_122 = _state_req_needs_wb_r_T_119 ? 2'h1 : _state_req_needs_wb_r_T_118; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_123 = _state_req_needs_wb_r_T_70 == 4'h2; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_124 = ~_state_req_needs_wb_r_T_123 & _state_req_needs_wb_r_T_120; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_125 = _state_req_needs_wb_r_T_123 ? 3'h3 : _state_req_needs_wb_r_T_121; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_126 = _state_req_needs_wb_r_T_123 ? 2'h2 : _state_req_needs_wb_r_T_122; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_127 = _state_req_needs_wb_r_T_70 == 4'h3; // @[Misc.scala:56:20] wire state_req_needs_wb_r_1_1 = _state_req_needs_wb_r_T_127 \| _state_req_needs_wb_r_T_124; // @[Misc.scala:38:9, :56:20] wire [2:0] state_req_needs_wb_r_2_1 = _state_req_needs_wb_r_T_127 ? 3'h3 : _state_req_needs_wb_r_T_125; // @[Misc.scala:38:36, :56:20] wire [1:0] state_req_needs_wb_r_3_1 = _state_req_needs_wb_r_T_127 ? 2'h2 : _state_req_needs_wb_r_T_126; // @[Misc.scala:38:63, :56:20] wire [1:0] state_req_needs_wb_meta_1_state = state_req_needs_wb_r_3_1; // @[Misc.scala:38:63] wire _state_r_c_cat_T_52 = _state_r_c_cat_T_50 \| _state_r_c_cat_T_51; // @[Consts.scala:90:{32,42,49}] wire _state_r_c_cat_T_54 = _state_r_c_cat_T_52 \| _state_r_c_cat_T_53; // @[Consts.scala:90:{42,59,66}] wire _state_r_c_cat_T_59 = _state_r_c_cat_T_55 \| _state_r_c_cat_T_56; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_60 = _state_r_c_cat_T_59 \| _state_r_c_cat_T_57; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_61 = _state_r_c_cat_T_60 \| _state_r_c_cat_T_58; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_67 = _state_r_c_cat_T_62 \| _state_r_c_cat_T_63; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_68 = _state_r_c_cat_T_67 \| _state_r_c_cat_T_64; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_69 = _state_r_c_cat_T_68 \| _state_r_c_cat_T_65; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_70 = _state_r_c_cat_T_69 \| _state_r_c_cat_T_66; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_71 = _state_r_c_cat_T_61 \| _state_r_c_cat_T_70; // @[package.scala:81:59] wire _state_r_c_cat_T_72 = _state_r_c_cat_T_54 \| _state_r_c_cat_T_71; // @[Consts.scala:87:44, :90:{59,76}] wire _state_r_c_cat_T_75 = _state_r_c_cat_T_73 \| _state_r_c_cat_T_74; // @[Consts.scala:90:{32,42,49}] wire _state_r_c_cat_T_77 = _state_r_c_cat_T_75 \| _state_r_c_cat_T_76; // @[Consts.scala:90:{42,59,66}] wire _state_r_c_cat_T_82 = _state_r_c_cat_T_78 \| _state_r_c_cat_T_79; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_83 = _state_r_c_cat_T_82 \| _state_r_c_cat_T_80; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_84 = _state_r_c_cat_T_83 \| _state_r_c_cat_T_81; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_90 = _state_r_c_cat_T_85 \| _state_r_c_cat_T_86; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_91 = _state_r_c_cat_T_90 \| _state_r_c_cat_T_87; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_92 = _state_r_c_cat_T_91 \| _state_r_c_cat_T_88; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_93 = _state_r_c_cat_T_92 \| _state_r_c_cat_T_89; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_94 = _state_r_c_cat_T_84 \| _state_r_c_cat_T_93; // @[package.scala:81:59] wire _state_r_c_cat_T_95 = _state_r_c_cat_T_77 \| _state_r_c_cat_T_94; // @[Consts.scala:87:44, :90:{59,76}] wire _state_r_c_cat_T_97 = _state_r_c_cat_T_95 \| _state_r_c_cat_T_96; // @[Consts.scala:90:76, :91:{47,54}] wire _state_r_c_cat_T_99 = _state_r_c_cat_T_97 \| _state_r_c_cat_T_98; // @[Consts.scala:91:{47,64,71}] wire [1:0] state_r_c_1 = {_state_r_c_cat_T_72, _state_r_c_cat_T_99}; // @[Metadata.scala:29:18] wire [3:0] _state_r_T_59 = {state_r_c_1, io_req_old_meta_coh_state_0}; // @[Metadata.scala:29:18, :58:19] wire _state_r_T_84 = _state_r_T_59 == 4'hC; // @[Misc.scala:49:20] wire [1:0] _state_r_T_86 = {1'h0, _state_r_T_84}; // @[Misc.scala:35:36, :49:20] wire _state_r_T_87 = _state_r_T_59 == 4'hD; // @[Misc.scala:49:20] wire [1:0] _state_r_T_89 = _state_r_T_87 ? 2'h2 : _state_r_T_86; // @[Misc.scala:35:36, :49:20] wire _state_r_T_90 = _state_r_T_59 == 4'h4; // @[Misc.scala:49:20] wire [1:0] _state_r_T_92 = _state_r_T_90 ? 2'h1 : _state_r_T_89; // @[Misc.scala:35:36, :49:20] wire _state_r_T_93 = _state_r_T_59 == 4'h5; // @[Misc.scala:49:20] wire [1:0] _state_r_T_95 = _state_r_T_93 ? 2'h2 : _state_r_T_92; // @[Misc.scala:35:36, :49:20] wire _state_r_T_96 = _state_r_T_59 == 4'h0; // @[Misc.scala:49:20] wire [1:0] _state_r_T_98 = _state_r_T_96 ? 2'h0 : _state_r_T_95; // @[Misc.scala:35:36, :49:20] wire _state_r_T_99 = _state_r_T_59 == 4'hE; // @[Misc.scala:49:20] wire _state_r_T_100 = _state_r_T_99; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_101 = _state_r_T_99 ? 2'h3 : _state_r_T_98; // @[Misc.scala:35:36, :49:20] wire _state_r_T_102 = &_state_r_T_59; // @[Misc.scala:49:20] wire _state_r_T_103 = _state_r_T_102 \| _state_r_T_100; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_104 = _state_r_T_102 ? 2'h3 : _state_r_T_101; // @[Misc.scala:35:36, :49:20] wire _state_r_T_105 = _state_r_T_59 == 4'h6; // @[Misc.scala:49:20] wire _state_r_T_106 = _state_r_T_105 \| _state_r_T_103; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_107 = _state_r_T_105 ? 2'h2 : _state_r_T_104; // @[Misc.scala:35:36, :49:20] wire _state_r_T_108 = _state_r_T_59 == 4'h7; // @[Misc.scala:49:20] wire _state_r_T_109 = _state_r_T_108 \| _state_r_T_106; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_110 = _state_r_T_108 ? 2'h3 : _state_r_T_107; // @[Misc.scala:35:36, :49:20] wire _state_r_T_111 = _state_r_T_59 == 4'h1; // @[Misc.scala:49:20] wire _state_r_T_112 = _state_r_T_111 \| _state_r_T_109; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_113 = _state_r_T_111 ? 2'h1 : _state_r_T_110; // @[Misc.scala:35:36, :49:20] wire _state_r_T_114 = _state_r_T_59 == 4'h2; // @[Misc.scala:49:20] wire _state_r_T_115 = _state_r_T_114 \| _state_r_T_112; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_116 = _state_r_T_114 ? 2'h2 : _state_r_T_113; // @[Misc.scala:35:36, :49:20] wire _state_r_T_117 = _state_r_T_59 == 4'h3; // @[Misc.scala:49:20] wire state_is_hit_1 = _state_r_T_117 \| _state_r_T_115; // @[Misc.scala:35:9, :49:20] wire [1:0] state_r_2_1 = _state_r_T_117 ? 2'h3 : _state_r_T_116; // @[Misc.scala:35:36, :49:20] wire [1:0] state_coh_on_hit_1_state = state_r_2_1; // @[Misc.scala:35:36] wire _state_T_39 = _state_T_37 \| _state_T_38; // @[Consts.scala:90:{32,42,49}] wire _state_T_41 = _state_T_39 \| _state_T_40; // @[Consts.scala:90:{42,59,66}] wire _state_T_46 = _state_T_42 \| _state_T_43; // @[package.scala:16:47, :81:59] wire _state_T_47 = _state_T_46 \| _state_T_44; // @[package.scala:16:47, :81:59] wire _state_T_48 = _state_T_47 \| _state_T_45; // @[package.scala:16:47, :81:59] wire _state_T_54 = _state_T_49 \| _state_T_50; // @[package.scala:16:47, :81:59] wire _state_T_55 = _state_T_54 \| _state_T_51; // @[package.scala:16:47, :81:59] wire _state_T_56 = _state_T_55 \| _state_T_52; // @[package.scala:16:47, :81:59] wire _state_T_57 = _state_T_56 \| _state_T_53; // @[package.scala:16:47, :81:59] wire _state_T_58 = _state_T_48 \| _state_T_57; // @[package.scala:81:59] wire _state_T_59 = _state_T_41 \| _state_T_58; // @[Consts.scala:87:44, :90:{59,76}] wire _state_T_61 = ~_state_T_60; // @[mshrs.scala:201:15] wire _state_T_62 = ~_state_T_59; // @[Consts.scala:90:76]
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth \| params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset \|\| !sio.sink_reset_n) \|\| !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise \|\| prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready \|\| !sio.source_reset_n \|\| reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise \|\| prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }	module AsyncValidSync_13( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_13 io_out_source_valid_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File bim.scala: package boom.v4.ifu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import boom.v4.common._ import boom.v4.util.{BoomCoreStringPrefix, WrapInc} import scala.math.min class BIMMeta(implicit p: Parameters) extends BoomBundle()(p) with HasBoomFrontendParameters { val bims = Vec(bankWidth, UInt(2.W)) } case class BoomBIMParams( nSets: Int = 2048, nCols: Int = 8, singlePorted: Boolean = true, useFlops: Boolean = false, slow: Boolean = false ) class BIMBranchPredictorBank(params: BoomBIMParams = BoomBIMParams())(implicit p: Parameters) extends BranchPredictorBank()(p) { override val nSets = params.nSets val nCols = params.nCols val nSetsPerCol = nSets / nCols require(isPow2(nSets)) require(isPow2(nCols)) require(nCols < nSets) require(nCols > 1) val nWrBypassEntries = 2 def bimWrite(v: UInt, taken: Bool): UInt = { val old_bim_sat_taken = v === 3.U val old_bim_sat_ntaken = v === 0.U Mux(old_bim_sat_taken && taken, 3.U, Mux(old_bim_sat_ntaken && !taken, 0.U, Mux(taken, v + 1.U, v - 1.U))) } val s2_meta = Wire(new BIMMeta) override val metaSz = s2_meta.asUInt.getWidth val doing_reset = RegInit(true.B) val reset_idx = RegInit(0.U(log2Ceil(nSetsPerCol).W)) reset_idx := reset_idx + doing_reset when (reset_idx === (nSetsPerCol-1).U) { doing_reset := false.B } val mems = (0 until nCols) map {c => (f"bim_col$c", nSetsPerCol, bankWidth * 2)} val s0_col_mask = UIntToOH(s0_idx(log2Ceil(nCols)-1,0)) & Fill(nCols, s0_valid) val s1_col_mask = RegNext(s0_col_mask) val s0_col_idx = s0_idx >> log2Ceil(nCols) val s1_col_idx = RegNext(s0_col_idx) val s2_req_rdata_all = Wire(Vec(nCols, Vec(bankWidth, UInt(2.W)))) val s2_req_rdata = Mux1H(RegNext(s1_col_mask), s2_req_rdata_all) val s2_resp = Wire(Vec(bankWidth, Bool())) for (w <- 0 until bankWidth) { s2_resp(w) := s2_valid && s2_req_rdata(w)(1) && !doing_reset s2_meta.bims(w) := s2_req_rdata(w) if (!params.slow) { io.resp.f2(w).taken := s2_resp(w) } io.resp.f3(w).taken := RegNext(s2_resp(w)) } io.f3_meta := RegNext(s2_meta.asUInt) val s1_update_wdata = Wire(Vec(bankWidth, UInt(2.W))) val s1_update_wmask = Wire(Vec(bankWidth, Bool())) val s1_update_meta = s1_update.bits.meta.asTypeOf(new BIMMeta) val s1_update_col_mask = UIntToOH(s1_update_idx(log2Ceil(nCols)-1,0)) val s1_update_col_idx = s1_update_idx >> log2Ceil(nCols) val wrbypass_idxs = Reg(Vec(nWrBypassEntries, UInt(log2Ceil(nSets).W))) val wrbypass = Reg(Vec(nWrBypassEntries, Vec(bankWidth, UInt(2.W)))) val wrbypass_enq_idx = RegInit(0.U(log2Ceil(nWrBypassEntries).W)) val wrbypass_hits = VecInit((0 until nWrBypassEntries) map { i => !doing_reset && wrbypass_idxs(i) === s1_update_idx(log2Ceil(nSets)-1,0) }) val wrbypass_hit = wrbypass_hits.reduce(_\|\|_) val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits) for (w <- 0 until bankWidth) { s1_update_wmask(w) := false.B s1_update_wdata(w) := DontCare val update_pc = s1_update.bits.pc + (w << 1).U when (s1_update.bits.br_mask(w) \|\| (s1_update.bits.cfi_idx.valid && s1_update.bits.cfi_idx.bits === w.U)) { val was_taken = ( s1_update.bits.cfi_idx.valid && (s1_update.bits.cfi_idx.bits === w.U) && ( (s1_update.bits.cfi_is_br && s1_update.bits.br_mask(w) && s1_update.bits.cfi_taken) \|\| s1_update.bits.cfi_is_jal ) ) val old_bim_value = Mux(wrbypass_hit, wrbypass(wrbypass_hit_idx)(w), s1_update_meta.bims(w)) s1_update_wmask(w) := true.B s1_update_wdata(w) := bimWrite(old_bim_value, was_taken) } } for (c <- 0 until nCols) { val rdata = Wire(Vec(bankWidth, UInt(2.W))) rdata := DontCare val (ren, ridx) = if (params.slow) (s1_col_mask(c), s1_col_idx) else (s0_col_mask(c), s0_col_idx) val wen = WireInit(doing_reset \|\| (s1_update.valid && s1_update.bits.is_commit_update && s1_update_col_mask(c) && !ren)) if (params.slow) { s2_req_rdata_all(c) := rdata } else { s2_req_rdata_all(c) := RegNext(rdata) } if (params.useFlops) { val data = Reg(Vec(nSetsPerCol, Vec(bankWidth, UInt(2.W)))) when (wen && doing_reset) { data(reset_idx) := VecInit(Seq.fill(bankWidth) { 2.U }) } .elsewhen (wen) { for (i <- 0 until bankWidth) { when (s1_update_wmask(i)) { data(s1_update_col_idx)(i) := s1_update_wdata(i) } } } when (RegNext(ren) && !(wen && params.singlePorted.B)) { rdata := data(RegNext(ridx)) } } else { val data = SyncReadMem(nSetsPerCol, Vec(bankWidth, UInt(2.W))) data.suggestName(s"bim_col_${c}") val r = if (params.singlePorted) data.read(ridx, ren && !wen) else data.read(ridx, ren) rdata := r when (wen) { val widx = Mux(doing_reset, reset_idx, s1_update_col_idx) val wdata = Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 2.U }), s1_update_wdata) val wmask = Mux(doing_reset, (~(0.U(bankWidth.W))), s1_update_wmask.asUInt) data.write(widx, wdata, wmask.asBools) } } } when (s1_update_wmask.reduce(_\|\|_) && s1_update.valid && s1_update.bits.is_commit_update) { when (wrbypass_hit) { wrbypass(wrbypass_hit_idx) := s1_update_wdata } .otherwise { wrbypass(wrbypass_enq_idx) := s1_update_wdata wrbypass_idxs(wrbypass_enq_idx) := s1_update_idx wrbypass_enq_idx := WrapInc(wrbypass_enq_idx, nWrBypassEntries) } } }	module bim_col_2_0( // @[bim.scala:157:29] input [7:0] RW0_addr, input RW0_en, input RW0_clk, input RW0_wmode, input [7:0] RW0_wdata, output [7:0] RW0_rdata, input [3:0] RW0_wmask ); bim_col_0_ext bim_col_0_ext ( // @[bim.scala:157:29] .RW0_addr (RW0_addr), .RW0_en (RW0_en), .RW0_clk (RW0_clk), .RW0_wmode (RW0_wmode), .RW0_wdata (RW0_wdata), .RW0_rdata (RW0_rdata), .RW0_wmask (RW0_wmask) ); // @[bim.scala:157:29] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftRegisterPriorityQueue.scala: package compressacc import chisel3._ import chisel3.util._ import chisel3.util._ // TODO : support enq & deq at the same cycle class PriorityQueueStageIO(keyWidth: Int, value: ValueInfo) extends Bundle { val output_prev = KeyValue(keyWidth, value) val output_nxt = KeyValue(keyWidth, value) val input_prev = Flipped(KeyValue(keyWidth, value)) val input_nxt = Flipped(KeyValue(keyWidth, value)) val cmd = Flipped(Valid(UInt(1.W))) val insert_here = Input(Bool()) val cur_input_keyval = Flipped(KeyValue(keyWidth, value)) val cur_output_keyval = KeyValue(keyWidth, value) } class PriorityQueueStage(keyWidth: Int, value: ValueInfo) extends Module { val io = IO(new PriorityQueueStageIO(keyWidth, value)) dontTouch(io) val CMD_DEQ = 0.U val CMD_ENQ = 1.U val MAX_VALUE = (1 << keyWidth) - 1 val key_reg = RegInit(MAX_VALUE.U(keyWidth.W)) val value_reg = Reg(value) io.output_prev.key := key_reg io.output_prev.value := value_reg io.output_nxt.key := key_reg io.output_nxt.value := value_reg io.cur_output_keyval.key := key_reg io.cur_output_keyval.value := value_reg when (io.cmd.valid) { switch (io.cmd.bits) { is (CMD_DEQ) { key_reg := io.input_nxt.key value_reg := io.input_nxt.value } is (CMD_ENQ) { when (io.insert_here) { key_reg := io.cur_input_keyval.key value_reg := io.cur_input_keyval.value } .elsewhen (key_reg >= io.cur_input_keyval.key) { key_reg := io.input_prev.key value_reg := io.input_prev.value } .otherwise { // do nothing } } } } } object PriorityQueueStage { def apply(keyWidth: Int, v: ValueInfo): PriorityQueueStage = new PriorityQueueStage(keyWidth, v) } // TODO // - This design is not scalable as the enqued_keyval is broadcasted to all the stages // - Add pipeline registers later class PriorityQueueIO(queSize: Int, keyWidth: Int, value: ValueInfo) extends Bundle { val cnt_bits = log2Ceil(queSize+1) val counter = Output(UInt(cnt_bits.W)) val enq = Flipped(Decoupled(KeyValue(keyWidth, value))) val deq = Decoupled(KeyValue(keyWidth, value)) } class PriorityQueue(queSize: Int, keyWidth: Int, value: ValueInfo) extends Module { val keyWidthInternal = keyWidth + 1 val CMD_DEQ = 0.U val CMD_ENQ = 1.U val io = IO(new PriorityQueueIO(queSize, keyWidthInternal, value)) dontTouch(io) val MAX_VALUE = ((1 << keyWidthInternal) - 1).U val cnt_bits = log2Ceil(queSize+1) // do not consider cases where we are inserting more entries then the queSize val counter = RegInit(0.U(cnt_bits.W)) io.counter := counter val full = (counter === queSize.U) val empty = (counter === 0.U) io.deq.valid := !empty io.enq.ready := !full when (io.enq.fire) { counter := counter + 1.U } when (io.deq.fire) { counter := counter - 1.U } val cmd_valid = io.enq.valid \|\| io.deq.ready val cmd = Mux(io.enq.valid, CMD_ENQ, CMD_DEQ) assert(!(io.enq.valid && io.deq.ready)) val stages = Seq.fill(queSize)(Module(new PriorityQueueStage(keyWidthInternal, value))) for (i <- 0 until (queSize - 1)) { stages(i+1).io.input_prev <> stages(i).io.output_nxt stages(i).io.input_nxt <> stages(i+1).io.output_prev } stages(queSize-1).io.input_nxt.key := MAX_VALUE // stages(queSize-1).io.input_nxt.value := stages(queSize-1).io.input_nxt.value.symbol := 0.U // stages(queSize-1).io.input_nxt.value.child(0) := 0.U // stages(queSize-1).io.input_nxt.value.child(1) := 0.U stages(0).io.input_prev.key := io.enq.bits.key stages(0).io.input_prev.value <> io.enq.bits.value for (i <- 0 until queSize) { stages(i).io.cmd.valid := cmd_valid stages(i).io.cmd.bits := cmd stages(i).io.cur_input_keyval <> io.enq.bits } val is_large_or_equal = WireInit(VecInit(Seq.fill(queSize)(false.B))) for (i <- 0 until queSize) { is_large_or_equal(i) := (stages(i).io.cur_output_keyval.key >= io.enq.bits.key) } val is_large_or_equal_cat = Wire(UInt(queSize.W)) is_large_or_equal_cat := Cat(is_large_or_equal.reverse) val insert_here_idx = PriorityEncoder(is_large_or_equal_cat) for (i <- 0 until queSize) { when (i.U === insert_here_idx) { stages(i).io.insert_here := true.B } .otherwise { stages(i).io.insert_here := false.B } } io.deq.bits <> stages(0).io.output_prev }	module PriorityQueueStage_54( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: package constellation.channel import chisel3._ import chisel3.util._ import freechips.rocketchip.diplomacy._ import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.util._ import constellation.noc.{HasNoCParams} class NoCMonitor(val cParam: ChannelParams)(implicit val p: Parameters) extends Module with HasNoCParams { val io = IO(new Bundle { val in = Input(new Channel(cParam)) }) val in_flight = RegInit(VecInit(Seq.fill(cParam.nVirtualChannels) { false.B })) for (i <- 0 until cParam.srcSpeedup) { val flit = io.in.flit(i) when (flit.valid) { when (flit.bits.head) { in_flight(flit.bits.virt_channel_id) := true.B assert (!in_flight(flit.bits.virt_channel_id), "Flit head/tail sequencing is broken") } when (flit.bits.tail) { in_flight(flit.bits.virt_channel_id) := false.B } } val possibleFlows = cParam.possibleFlows when (flit.valid && flit.bits.head) { cParam match { case n: ChannelParams => n.virtualChannelParams.zipWithIndex.foreach { case (v,i) => assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR) } case _ => assert(cParam.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR) } } } } File Types.scala: package constellation.routing import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Parameters} import constellation.noc.{HasNoCParams} import constellation.channel.{Flit} /** A representation for 1 specific virtual channel in wormhole routing * * @param src the source node * @param vc ID for the virtual channel * @param dst the destination node * @param n_vc the number of virtual channels / // BEGIN: ChannelRoutingInfo case class ChannelRoutingInfo( src: Int, dst: Int, vc: Int, n_vc: Int ) { // END: ChannelRoutingInfo require (src >= -1 && dst >= -1 && vc >= 0, s"Illegal $this") require (!(src == -1 && dst == -1), s"Illegal $this") require (vc < n_vc, s"Illegal $this") val isIngress = src == -1 val isEgress = dst == -1 } /* Represents the properties of a packet that are relevant for routing * ingressId and egressId uniquely identify a flow, but vnet and dst are used here * to simplify the implementation of routingrelations * * @param ingressId packet's source ingress point * @param egressId packet's destination egress point * @param vNet virtual subnetwork identifier * @param dst packet's destination node ID */ // BEGIN: FlowRoutingInfo case class FlowRoutingInfo( ingressId: Int, egressId: Int, vNetId: Int, ingressNode: Int, ingressNodeId: Int, egressNode: Int, egressNodeId: Int, fifo: Boolean ) { // END: FlowRoutingInfo def isFlow(f: FlowRoutingBundle): Bool = { (f.ingress_node === ingressNode.U && f.egress_node === egressNode.U && f.ingress_node_id === ingressNodeId.U && f.egress_node_id === egressNodeId.U) } def asLiteral(b: FlowRoutingBundle): BigInt = { Seq( (vNetId , b.vnet_id), (ingressNode , b.ingress_node), (ingressNodeId , b.ingress_node_id), (egressNode , b.egress_node), (egressNodeId , b.egress_node_id) ).foldLeft(0)((l, t) => { (l << t._2.getWidth) \| t._1 }) } } class FlowRoutingBundle(implicit val p: Parameters) extends Bundle with HasNoCParams { // Instead of tracking ingress/egress ID, track the physical destination id and the offset at the destination // This simplifies the routing tables val vnet_id = UInt(log2Ceil(nVirtualNetworks).W) val ingress_node = UInt(log2Ceil(nNodes).W) val ingress_node_id = UInt(log2Ceil(maxIngressesAtNode).W) val egress_node = UInt(log2Ceil(nNodes).W) val egress_node_id = UInt(log2Ceil(maxEgressesAtNode).W) }	module NoCMonitor_55( // @[Monitor.scala:11:7] input clock, // @[Monitor.scala:11:7] input reset, // @[Monitor.scala:11:7] input io_in_flit_0_valid, // @[Monitor.scala:12:14] input io_in_flit_0_bits_head, // @[Monitor.scala:12:14] input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14] input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14] input [4:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14] input [2:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14] ); reg in_flight_0; // @[Monitor.scala:16:26] reg in_flight_1; // @[Monitor.scala:16:26] reg in_flight_2; // @[Monitor.scala:16:26] reg in_flight_3; // @[Monitor.scala:16:26] reg in_flight_4; // @[Monitor.scala:16:26] reg in_flight_5; // @[Monitor.scala:16:26] reg in_flight_6; // @[Monitor.scala:16:26] reg in_flight_7; // @[Monitor.scala:16:26]
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_53( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input io_in_a_bits_source, // @[Monitor.scala:20:14] input [8:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [8:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_beats1_decode_T_1 = 2'h3; // @[package.scala:243:76] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_beats1_decode_T_2 = 2'h0; // @[package.scala:243:46] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [8:0] _c_first_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_first_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_first_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_first_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_set_wo_ready_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_set_wo_ready_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_opcodes_set_interm_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_opcodes_set_interm_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_sizes_set_interm_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_sizes_set_interm_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_opcodes_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_opcodes_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_sizes_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_sizes_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_probe_ack_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_probe_ack_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_probe_ack_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_probe_ack_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_4_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_5_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [17:0] _c_sizes_set_T_1 = 18'h0; // @[Monitor.scala:768:52] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] c_sizes_set = 4'h0; // @[Monitor.scala:741:34] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [4:0] _c_first_beats1_decode_T = 5'h3; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [1:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire _source_ok_T = ~io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [4:0] _GEN = 5'h3 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [4:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [4:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [4:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [1:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[1:0]; // @[package.scala:243:{71,76}] wire [1:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [8:0] _is_aligned_T = {7'h0, io_in_a_bits_address_0[1:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 9'h0; // @[Edges.scala:21:{16,24}] wire mask_sizeOH_shiftAmount = _mask_sizeOH_T[0]; // @[OneHot.scala:64:49] wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [1:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire [1:0] mask_sizeOH = {_mask_sizeOH_T_2[1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_0_1 = io_in_a_bits_size_0[1]; // @[Misc.scala:206:21] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_1_2 = mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire _source_ok_T_1 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_1; // @[Parameters.scala:1138:31] wire _T_898 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_898; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_898; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [1:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg source; // @[Monitor.scala:390:22] reg [8:0] address; // @[Monitor.scala:391:22] wire _T_966 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_966; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_966; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_966; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [4:0] _GEN_0 = 5'h3 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [1:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg source_1; // @[Monitor.scala:541:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [3:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [1:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [1:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [3:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [3:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [3:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [3:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [3:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [3:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [3:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [3:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [3:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [3:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [3:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [15:0] _a_size_lookup_T_6 = {12'h0, _a_size_lookup_T_1}; // @[Monitor.scala:637:97, :641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [1:0] _GEN_2 = {1'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_3 = 2'h1 << _GEN_2; // @[OneHot.scala:58:35] wire [1:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [1:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T & _a_set_wo_ready_T[0]; // @[OneHot.scala:58:35] wire _T_831 = _T_898 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_831 & _a_set_T[0]; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_831 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_831 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [3:0] _GEN_4 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [3:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_4; // @[Monitor.scala:659:79] wire [3:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_4; // @[Monitor.scala:659:79, :660:77] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_831 ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [17:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_831 ? _a_sizes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [3:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46] wire _T_877 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [1:0] _GEN_6 = {1'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_7 = 2'h1 << _GEN_6; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_877 & ~d_release_ack & _d_clr_wo_ready_T[0]; // @[OneHot.scala:58:35] wire _T_846 = _T_966 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_846 & _d_clr_T[0]; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_5 = 31'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_846 ? _d_opcodes_clr_T_5[3:0] : 4'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [30:0] _d_sizes_clr_T_5 = 31'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_846 ? _d_sizes_clr_T_5[3:0] : 4'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1:0] _inflight_T = {inflight[1], inflight[0] \| a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [3:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [3:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [3:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [3:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [1:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:637:97, :749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [3:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [15:0] _c_size_lookup_T_6 = {12'h0, _c_size_lookup_T_1}; // @[Monitor.scala:637:97, :750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [3:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_942 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_942 & d_release_ack_1 & _d_clr_wo_ready_T_1[0]; // @[OneHot.scala:58:35] wire _T_924 = _T_966 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_924 & _d_clr_T_1[0]; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_11 = 31'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_924 ? _d_opcodes_clr_T_11[3:0] : 4'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [30:0] _d_sizes_clr_T_11 = 31'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_924 ? _d_sizes_clr_T_11[3:0] : 4'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [3:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [3:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_3( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_44 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_46 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_50 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_52 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_56 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_58 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_62 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_64 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_68 = 1'h1; // @[Parameters.scala:56:32] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_25 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_26 = _source_ok_T_25 == 5'h8; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_29 = source_ok_uncommonBits_4 != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_30 = _source_ok_T_28 & _source_ok_T_29; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire _source_ok_T_31 = io_in_a_bits_source_0 == 7'h23; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_31; // @[Parameters.scala:1138:31] wire _source_ok_T_32 = io_in_a_bits_source_0 == 7'h24; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_32; // @[Parameters.scala:1138:31] wire _source_ok_T_33 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_33; // @[Parameters.scala:1138:31] wire _source_ok_T_34 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_35 = _source_ok_T_34 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_36 = _source_ok_T_35 \| _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_37 = _source_ok_T_36 \| _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_38 = _source_ok_T_37 \| _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_39 = _source_ok_T_38 \| _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_40 = _source_ok_T_39 \| _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_40 \| _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [28:0] _is_aligned_T = {23'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_46 = _uncommonBits_T_46[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_47 = _uncommonBits_T_47[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_53 = _uncommonBits_T_53[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_41 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_41; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_42 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_48 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_54 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_60 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_66 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_43 = _source_ok_T_42 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_45 = _source_ok_T_43; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_47 = _source_ok_T_45; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_47; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_49 = _source_ok_T_48 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_51 = _source_ok_T_49; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_53 = _source_ok_T_51; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_53; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_55 = _source_ok_T_54 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_57 = _source_ok_T_55; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_59 = _source_ok_T_57; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_59; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_61 = _source_ok_T_60 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_63 = _source_ok_T_61; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_65 = _source_ok_T_63; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_65; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_67 = _source_ok_T_66 == 5'h8; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_69 = _source_ok_T_67; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_70 = source_ok_uncommonBits_9 != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_71 = _source_ok_T_69 & _source_ok_T_70; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_5 = _source_ok_T_71; // @[Parameters.scala:1138:31] wire _source_ok_T_72 = io_in_d_bits_source_0 == 7'h23; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_72; // @[Parameters.scala:1138:31] wire _source_ok_T_73 = io_in_d_bits_source_0 == 7'h24; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_73; // @[Parameters.scala:1138:31] wire _source_ok_T_74 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_74; // @[Parameters.scala:1138:31] wire _source_ok_T_75 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_76 = _source_ok_T_75 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_77 = _source_ok_T_76 \| _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_78 = _source_ok_T_77 \| _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_79 = _source_ok_T_78 \| _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_80 = _source_ok_T_79 \| _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_81 = _source_ok_T_80 \| _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_81 \| _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _T_1216 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1216; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1216; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [28:0] address; // @[Monitor.scala:391:22] wire _T_1289 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1289; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1289; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1289; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [259:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [259:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1142 = _T_1216 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1142 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1142 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1142 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1142 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1142 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1188 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1188 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1157 = _T_1289 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1157 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1157 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1157 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [259:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1260 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1260 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1242 = _T_1289 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1242 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1242 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1242 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Metadata.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.constants.MemoryOpConstants import freechips.rocketchip.util._ object ClientStates { val width = 2 def Nothing = 0.U(width.W) def Branch = 1.U(width.W) def Trunk = 2.U(width.W) def Dirty = 3.U(width.W) def hasReadPermission(state: UInt): Bool = state > Nothing def hasWritePermission(state: UInt): Bool = state > Branch } object MemoryOpCategories extends MemoryOpConstants { def wr = Cat(true.B, true.B) // Op actually writes def wi = Cat(false.B, true.B) // Future op will write def rd = Cat(false.B, false.B) // Op only reads def categorize(cmd: UInt): UInt = { val cat = Cat(isWrite(cmd), isWriteIntent(cmd)) //assert(cat.isOneOf(wr,wi,rd), "Could not categorize command.") cat } } /* Stores the client-side coherence information, * such as permissions on the data and whether the data is dirty. * Its API can be used to make TileLink messages in response to * memory operations, cache control oeprations, or Probe messages. / class ClientMetadata extends Bundle { /* Actual state information stored in this bundle / val state = UInt(ClientStates.width.W) /* Metadata equality / def ===(rhs: UInt): Bool = state === rhs def ===(rhs: ClientMetadata): Bool = state === rhs.state def =/=(rhs: ClientMetadata): Bool = !this.===(rhs) /* Is the block's data present in this cache / def isValid(dummy: Int = 0): Bool = state > ClientStates.Nothing /* Determine whether this cmd misses, and the new state (on hit) or param to be sent (on miss) / private def growStarter(cmd: UInt): (Bool, UInt) = { import MemoryOpCategories._ import TLPermissions._ import ClientStates._ val c = categorize(cmd) MuxTLookup(Cat(c, state), (false.B, 0.U), Seq( //(effect, am now) -> (was a hit, next) Cat(rd, Dirty) -> (true.B, Dirty), Cat(rd, Trunk) -> (true.B, Trunk), Cat(rd, Branch) -> (true.B, Branch), Cat(wi, Dirty) -> (true.B, Dirty), Cat(wi, Trunk) -> (true.B, Trunk), Cat(wr, Dirty) -> (true.B, Dirty), Cat(wr, Trunk) -> (true.B, Dirty), //(effect, am now) -> (was a miss, param) Cat(rd, Nothing) -> (false.B, NtoB), Cat(wi, Branch) -> (false.B, BtoT), Cat(wi, Nothing) -> (false.B, NtoT), Cat(wr, Branch) -> (false.B, BtoT), Cat(wr, Nothing) -> (false.B, NtoT))) } /* Determine what state to go to after miss based on Grant param * For now, doesn't depend on state (which may have been Probed). / private def growFinisher(cmd: UInt, param: UInt): UInt = { import MemoryOpCategories._ import TLPermissions._ import ClientStates._ val c = categorize(cmd) //assert(c === rd \|\| param === toT, "Client was expecting trunk permissions.") MuxLookup(Cat(c, param), Nothing)(Seq( //(effect param) -> (next) Cat(rd, toB) -> Branch, Cat(rd, toT) -> Trunk, Cat(wi, toT) -> Trunk, Cat(wr, toT) -> Dirty)) } /* Does this cache have permissions on this block sufficient to perform op, * and what to do next (Acquire message param or updated metadata). / def onAccess(cmd: UInt): (Bool, UInt, ClientMetadata) = { val r = growStarter(cmd) (r._1, r._2, ClientMetadata(r._2)) } /* Does a secondary miss on the block require another Acquire message / def onSecondaryAccess(first_cmd: UInt, second_cmd: UInt): (Bool, Bool, UInt, ClientMetadata, UInt) = { import MemoryOpCategories._ val r1 = growStarter(first_cmd) val r2 = growStarter(second_cmd) val needs_second_acq = isWriteIntent(second_cmd) && !isWriteIntent(first_cmd) val hit_again = r1._1 && r2._1 val dirties = categorize(second_cmd) === wr val biggest_grow_param = Mux(dirties, r2._2, r1._2) val dirtiest_state = ClientMetadata(biggest_grow_param) val dirtiest_cmd = Mux(dirties, second_cmd, first_cmd) (needs_second_acq, hit_again, biggest_grow_param, dirtiest_state, dirtiest_cmd) } /* Metadata change on a returned Grant / def onGrant(cmd: UInt, param: UInt): ClientMetadata = ClientMetadata(growFinisher(cmd, param)) /* Determine what state to go to based on Probe param / private def shrinkHelper(param: UInt): (Bool, UInt, UInt) = { import ClientStates._ import TLPermissions._ MuxTLookup(Cat(param, state), (false.B, 0.U, 0.U), Seq( //(wanted, am now) -> (hasDirtyData resp, next) Cat(toT, Dirty) -> (true.B, TtoT, Trunk), Cat(toT, Trunk) -> (false.B, TtoT, Trunk), Cat(toT, Branch) -> (false.B, BtoB, Branch), Cat(toT, Nothing) -> (false.B, NtoN, Nothing), Cat(toB, Dirty) -> (true.B, TtoB, Branch), Cat(toB, Trunk) -> (false.B, TtoB, Branch), // Policy: Don't notify on clean downgrade Cat(toB, Branch) -> (false.B, BtoB, Branch), Cat(toB, Nothing) -> (false.B, NtoN, Nothing), Cat(toN, Dirty) -> (true.B, TtoN, Nothing), Cat(toN, Trunk) -> (false.B, TtoN, Nothing), // Policy: Don't notify on clean downgrade Cat(toN, Branch) -> (false.B, BtoN, Nothing), // Policy: Don't notify on clean downgrade Cat(toN, Nothing) -> (false.B, NtoN, Nothing))) } /* Translate cache control cmds into Probe param / private def cmdToPermCap(cmd: UInt): UInt = { import MemoryOpCategories._ import TLPermissions._ MuxLookup(cmd, toN)(Seq( M_FLUSH -> toN, M_PRODUCE -> toB, M_CLEAN -> toT)) } def onCacheControl(cmd: UInt): (Bool, UInt, ClientMetadata) = { val r = shrinkHelper(cmdToPermCap(cmd)) (r._1, r._2, ClientMetadata(r._3)) } def onProbe(param: UInt): (Bool, UInt, ClientMetadata) = { val r = shrinkHelper(param) (r._1, r._2, ClientMetadata(r._3)) } } /* Factories for ClientMetadata, including on reset / object ClientMetadata { def apply(perm: UInt) = { val meta = Wire(new ClientMetadata) meta.state := perm meta } def onReset = ClientMetadata(ClientStates.Nothing) def maximum = ClientMetadata(ClientStates.Dirty) } File MSHR.scala: package shuttle.dmem import chisel3._ import chisel3.util._ import chisel3.experimental.dataview._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import freechips.rocketchip.rocket._ class ShuttleDCacheMSHR(id: Int)(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCacheModule()(p) { val io = IO(new Bundle { val req_pri_val = Input(Bool()) val req_pri_rdy = Output(Bool()) val req_sec_val = Input(Bool()) val req_sec_rdy = Output(Bool()) val req_bits = Input(new ShuttleMSHRReq()) val probe_addr = Input(UInt(paddrBits.W)) val idx_match = Output(Bool()) val tag = Output(Bits(tagBits.W)) val mem_acquire = Decoupled(new TLBundleA(edge.bundle)) val mem_grant = Flipped(Valid(new TLBundleD(edge.bundle))) val mem_finish = Decoupled(new TLBundleE(edge.bundle)) val refill = Output(new L1RefillReq()) // Data is bypassed val meta_write = Decoupled(new L1MetaWriteReq) val replay = Decoupled(new ShuttleMSHRReq) val wb_req = Decoupled(new WritebackReq(edge.bundle)) val probe_rdy = Output(Bool()) }) val s_invalid :: s_wb_req :: s_wb_resp :: s_meta_clear :: s_refill_req :: s_refill_resp :: s_meta_write_req :: s_meta_write_resp :: s_drain_rpq :: Nil = Enum(9) val state = RegInit(s_invalid) val req = Reg(new ShuttleMSHRReq) val req_idx = req.addr(untagBits-1,blockOffBits) val req_tag = req.addr >> untagBits val req_block_addr = (req.addr >> blockOffBits) << blockOffBits val idx_match = req_idx === io.req_bits.addr(untagBits-1,blockOffBits) val probe_idx_match = req_idx === io.probe_addr(untagBits-1,blockOffBits) val new_coh = RegInit(ClientMetadata.onReset) val (_, shrink_param, coh_on_clear) = req.old_meta.coh.onCacheControl(M_FLUSH) val grow_param = new_coh.onAccess(req.cmd)._2 val coh_on_grant = new_coh.onGrant(req.cmd, io.mem_grant.bits.param) // We only accept secondary misses if we haven't yet sent an Acquire to outer memory // or if the Acquire that was sent will obtain a Grant with sufficient permissions // to let us replay this new request. I.e. we don't handle multiple outstanding // Acquires on the same block for now. val (cmd_requires_second_acquire, is_hit_again, _, dirtier_coh, dirtier_cmd) = new_coh.onSecondaryAccess(req.cmd, io.req_bits.cmd) val states_before_refill = Seq(s_wb_req, s_wb_resp, s_meta_clear) val (_, _, refill_done, refill_address_inc) = edge.addr_inc(io.mem_grant) val sec_rdy = idx_match && (state.isOneOf(states_before_refill) \|\| (state.isOneOf(s_refill_req, s_refill_resp) && !cmd_requires_second_acquire && !refill_done)) val rpq = Module(new Queue(new ShuttleMSHRReq, cfg.nRPQ)) rpq.io.enq.valid := (io.req_pri_val && io.req_pri_rdy \|\| io.req_sec_val && sec_rdy) && !isPrefetch(io.req_bits.cmd) rpq.io.enq.bits := io.req_bits rpq.io.deq.ready := (io.replay.ready && state === s_drain_rpq) \|\| state === s_invalid val acked = Reg(Bool()) when (io.mem_grant.valid) { acked := true.B } when (state === s_drain_rpq && !rpq.io.deq.valid) { state := s_invalid } when (state === s_meta_write_resp) { // this wait state allows us to catch RAW hazards on the tags via nack_victim state := s_drain_rpq } when (state === s_meta_write_req && io.meta_write.ready) { state := s_meta_write_resp } when (state === s_refill_resp && refill_done) { new_coh := coh_on_grant state := s_meta_write_req } when (io.mem_acquire.fire) { // s_refill_req state := s_refill_resp } when (state === s_meta_clear && io.meta_write.ready) { state := s_refill_req } when (state === s_wb_resp && io.wb_req.ready && acked) { state := s_meta_clear } when (io.wb_req.fire) { // s_wb_req state := s_wb_resp } when (io.req_sec_val && io.req_sec_rdy) { // s_wb_req, s_wb_resp, s_refill_req //If we get a secondary miss that needs more permissions before we've sent // out the primary miss's Acquire, we can upgrade the permissions we're // going to ask for in s_refill_req req.cmd := dirtier_cmd when (is_hit_again) { new_coh := dirtier_coh } } when (io.req_pri_val && io.req_pri_rdy) { req := io.req_bits acked := false.B val old_coh = io.req_bits.old_meta.coh val needs_wb = old_coh.onCacheControl(M_FLUSH)._1 val (is_hit, _, coh_on_hit) = old_coh.onAccess(io.req_bits.cmd) when (io.req_bits.tag_match) { when (is_hit) { // set dirty bit new_coh := coh_on_hit state := s_meta_write_req }.otherwise { // upgrade permissions new_coh := old_coh state := s_refill_req } }.otherwise { // writback if necessary and refill new_coh := ClientMetadata.onReset state := Mux(needs_wb, s_wb_req, s_meta_clear) } } val grantackq = Module(new Queue(new TLBundleE(edge.bundle), 1)) val can_finish = state.isOneOf(s_invalid, s_refill_req) grantackq.io.enq.valid := refill_done && edge.isRequest(io.mem_grant.bits) grantackq.io.enq.bits := edge.GrantAck(io.mem_grant.bits) io.mem_finish.valid := grantackq.io.deq.valid && can_finish io.mem_finish.bits := grantackq.io.deq.bits grantackq.io.deq.ready := io.mem_finish.ready && can_finish io.idx_match := (state =/= s_invalid) && idx_match io.refill.way_en := req.way_en io.refill.addr := req_block_addr \| refill_address_inc io.tag := req_tag io.req_pri_rdy := state === s_invalid io.req_sec_rdy := sec_rdy && rpq.io.enq.ready val meta_hazard = RegInit(0.U(2.W)) when (meta_hazard =/= 0.U) { meta_hazard := meta_hazard + 1.U } when (io.meta_write.fire) { meta_hazard := 1.U } io.probe_rdy := !(state =/= s_invalid && probe_idx_match) \|\| (!state.isOneOf(states_before_refill) && meta_hazard === 0.U) io.meta_write.valid := state.isOneOf(s_meta_write_req, s_meta_clear) io.meta_write.bits.idx := req_idx io.meta_write.bits.tag := io.tag io.meta_write.bits.data.coh := Mux(state === s_meta_clear, coh_on_clear, new_coh) io.meta_write.bits.data.tag := io.tag io.meta_write.bits.way_en := req.way_en io.wb_req.valid := state === s_wb_req io.wb_req.bits.source := id.U io.wb_req.bits.tag := req.old_meta.tag io.wb_req.bits.idx := req_idx io.wb_req.bits.param := shrink_param io.wb_req.bits.way_en := req.way_en io.wb_req.bits.voluntary := true.B io.mem_acquire.valid := state === s_refill_req && grantackq.io.enq.ready io.mem_acquire.bits := edge.AcquireBlock( fromSource = id.U, toAddress = Cat(io.tag, req_idx) << blockOffBits, lgSize = lgCacheBlockBytes.U, growPermissions = grow_param)._2 io.replay.valid := state === s_drain_rpq && rpq.io.deq.valid io.replay.bits := rpq.io.deq.bits io.replay.bits.addr := Cat(io.tag, req_idx, rpq.io.deq.bits.addr(blockOffBits-1,0)) io.replay.bits.cmd := rpq.io.deq.bits.cmd when (state === s_drain_rpq && !rpq.io.deq.valid) { state := Mux(RegNext(!rpq.io.deq.valid), s_invalid, state) } rpq.io.deq.ready := io.replay.ready && state === s_drain_rpq } File Consts.scala: // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket.constants import chisel3._ import chisel3.util._ import freechips.rocketchip.util._ trait ScalarOpConstants { val SZ_BR = 3 def BR_X = BitPat("b???") def BR_EQ = 0.U(3.W) def BR_NE = 1.U(3.W) def BR_J = 2.U(3.W) def BR_N = 3.U(3.W) def BR_LT = 4.U(3.W) def BR_GE = 5.U(3.W) def BR_LTU = 6.U(3.W) def BR_GEU = 7.U(3.W) def A1_X = BitPat("b??") def A1_ZERO = 0.U(2.W) def A1_RS1 = 1.U(2.W) def A1_PC = 2.U(2.W) def A1_RS1SHL = 3.U(2.W) def IMM_X = BitPat("b???") def IMM_S = 0.U(3.W) def IMM_SB = 1.U(3.W) def IMM_U = 2.U(3.W) def IMM_UJ = 3.U(3.W) def IMM_I = 4.U(3.W) def IMM_Z = 5.U(3.W) def A2_X = BitPat("b???") def A2_ZERO = 0.U(3.W) def A2_SIZE = 1.U(3.W) def A2_RS2 = 2.U(3.W) def A2_IMM = 3.U(3.W) def A2_RS2OH = 4.U(3.W) def A2_IMMOH = 5.U(3.W) def X = BitPat("b?") def N = BitPat("b0") def Y = BitPat("b1") val SZ_DW = 1 def DW_X = X def DW_32 = false.B def DW_64 = true.B def DW_XPR = DW_64 } trait MemoryOpConstants { val NUM_XA_OPS = 9 val M_SZ = 5 def M_X = BitPat("b?????"); def M_XRD = "b00000".U; // int load def M_XWR = "b00001".U; // int store def M_PFR = "b00010".U; // prefetch with intent to read def M_PFW = "b00011".U; // prefetch with intent to write def M_XA_SWAP = "b00100".U def M_FLUSH_ALL = "b00101".U // flush all lines def M_XLR = "b00110".U def M_XSC = "b00111".U def M_XA_ADD = "b01000".U def M_XA_XOR = "b01001".U def M_XA_OR = "b01010".U def M_XA_AND = "b01011".U def M_XA_MIN = "b01100".U def M_XA_MAX = "b01101".U def M_XA_MINU = "b01110".U def M_XA_MAXU = "b01111".U def M_FLUSH = "b10000".U // write back dirty data and cede R/W permissions def M_PWR = "b10001".U // partial (masked) store def M_PRODUCE = "b10010".U // write back dirty data and cede W permissions def M_CLEAN = "b10011".U // write back dirty data and retain R/W permissions def M_SFENCE = "b10100".U // SFENCE.VMA def M_HFENCEV = "b10101".U // HFENCE.VVMA def M_HFENCEG = "b10110".U // HFENCE.GVMA def M_WOK = "b10111".U // check write permissions but don't perform a write def M_HLVX = "b10000".U // HLVX instruction def isAMOLogical(cmd: UInt) = cmd.isOneOf(M_XA_SWAP, M_XA_XOR, M_XA_OR, M_XA_AND) def isAMOArithmetic(cmd: UInt) = cmd.isOneOf(M_XA_ADD, M_XA_MIN, M_XA_MAX, M_XA_MINU, M_XA_MAXU) def isAMO(cmd: UInt) = isAMOLogical(cmd) \|\| isAMOArithmetic(cmd) def isPrefetch(cmd: UInt) = cmd === M_PFR \|\| cmd === M_PFW def isRead(cmd: UInt) = cmd.isOneOf(M_XRD, M_HLVX, M_XLR, M_XSC) \|\| isAMO(cmd) def isWrite(cmd: UInt) = cmd === M_XWR \|\| cmd === M_PWR \|\| cmd === M_XSC \|\| isAMO(cmd) def isWriteIntent(cmd: UInt) = isWrite(cmd) \|\| cmd === M_PFW \|\| cmd === M_XLR } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{ AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry, IdRange, RegionType, TransferSizes } import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions} import freechips.rocketchip.util.{ AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase, CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct } import scala.math.max //These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel case class TLMasterToSlaveTransferSizes( // Supports both Acquire+Release of the following two sizes: acquireT: TransferSizes = TransferSizes.none, acquireB: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none) extends TLCommonTransferSizes { def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .intersect(rhs.acquireT), acquireB = acquireB .intersect(rhs.acquireB), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint)) def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .mincover(rhs.acquireT), acquireB = acquireB .mincover(rhs.acquireB), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint)) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(acquireT, "T"), str(acquireB, "B"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""acquireT = ${acquireT} \|acquireB = ${acquireB} \|arithmetic = ${arithmetic} \|logical = ${logical} \|get = ${get} \|putFull = ${putFull} \|putPartial = ${putPartial} \|hint = ${hint} \| \|""".stripMargin } } object TLMasterToSlaveTransferSizes { def unknownEmits = TLMasterToSlaveTransferSizes( acquireT = TransferSizes(1, 4096), acquireB = TransferSizes(1, 4096), arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096)) def unknownSupports = TLMasterToSlaveTransferSizes() } //These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel case class TLSlaveToMasterTransferSizes( probe: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none ) extends TLCommonTransferSizes { def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .intersect(rhs.probe), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint) ) def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .mincover(rhs.probe), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint) ) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(probe, "P"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""probe = ${probe} \|arithmetic = ${arithmetic} \|logical = ${logical} \|get = ${get} \|putFull = ${putFull} \|putPartial = ${putPartial} \|hint = ${hint} \| \|""".stripMargin } } object TLSlaveToMasterTransferSizes { def unknownEmits = TLSlaveToMasterTransferSizes( arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096), probe = TransferSizes(1, 4096)) def unknownSupports = TLSlaveToMasterTransferSizes() } trait TLCommonTransferSizes { def arithmetic: TransferSizes def logical: TransferSizes def get: TransferSizes def putFull: TransferSizes def putPartial: TransferSizes def hint: TransferSizes } class TLSlaveParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], setName: Option[String], val address: Seq[AddressSet], val regionType: RegionType.T, val executable: Boolean, val fifoId: Option[Int], val supports: TLMasterToSlaveTransferSizes, val emits: TLSlaveToMasterTransferSizes, // By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation) val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData // If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order // Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck // ReleaseAck may NEVER be denied extends SimpleProduct { def sortedAddress = address.sorted override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters] override def productPrefix = "TLSlaveParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 11 def productElement(n: Int): Any = n match { case 0 => name case 1 => address case 2 => resources case 3 => regionType case 4 => executable case 5 => fifoId case 6 => supports case 7 => emits case 8 => alwaysGrantsT case 9 => mayDenyGet case 10 => mayDenyPut case _ => throw new IndexOutOfBoundsException(n.toString) } def supportsAcquireT: TransferSizes = supports.acquireT def supportsAcquireB: TransferSizes = supports.acquireB def supportsArithmetic: TransferSizes = supports.arithmetic def supportsLogical: TransferSizes = supports.logical def supportsGet: TransferSizes = supports.get def supportsPutFull: TransferSizes = supports.putFull def supportsPutPartial: TransferSizes = supports.putPartial def supportsHint: TransferSizes = supports.hint require (!address.isEmpty, "Address cannot be empty") address.foreach { a => require (a.finite, "Address must be finite") } address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)") require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)") require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)") require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)") require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)") require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)") require (!alwaysGrantsT \|\| supportsAcquireT, s"Must supportAcquireT if promising to always grantT") // Make sure that the regionType agrees with the capabilities require (!supportsAcquireB \|\| regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached require (regionType <= RegionType.UNCACHED \|\| supportsAcquireB) // tracked, cached -> acquire require (regionType != RegionType.UNCACHED \|\| supportsGet) // uncached -> supportsGet val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected") val maxTransfer = List( // Largest supported transfer of all types supportsAcquireT.max, supportsAcquireB.max, supportsArithmetic.max, supportsLogical.max, supportsGet.max, supportsPutFull.max, supportsPutPartial.max).max val maxAddress = address.map(_.max).max val minAlignment = address.map(_.alignment).min // The device had better not support a transfer larger than its alignment require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)") def toResource: ResourceAddress = { ResourceAddress(address, ResourcePermissions( r = supportsAcquireB \|\| supportsGet, w = supportsAcquireT \|\| supportsPutFull, x = executable, c = supportsAcquireB, a = supportsArithmetic && supportsLogical)) } def findTreeViolation() = nodePath.find { case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false case _: SinkNode[_, _, _, _, _] => false case node => node.inputs.size != 1 } def isTree = findTreeViolation() == None def infoString = { s"""Slave Name = ${name} \|Slave Address = ${address} \|supports = ${supports.infoString} \| \|""".stripMargin } def v1copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { new TLSlaveParameters( setName = setName, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = emits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: Option[String] = setName, address: Seq[AddressSet] = address, regionType: RegionType.T = regionType, executable: Boolean = executable, fifoId: Option[Int] = fifoId, supports: TLMasterToSlaveTransferSizes = supports, emits: TLSlaveToMasterTransferSizes = emits, alwaysGrantsT: Boolean = alwaysGrantsT, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } @deprecated("Use v1copy instead of copy","") def copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { v1copy( address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supportsAcquireT = supportsAcquireT, supportsAcquireB = supportsAcquireB, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } } object TLSlaveParameters { def v1( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = { new TLSlaveParameters( setName = None, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLSlaveToMasterTransferSizes.unknownEmits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2( address: Seq[AddressSet], nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Seq(), name: Option[String] = None, regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, fifoId: Option[Int] = None, supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports, emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits, alwaysGrantsT: Boolean = false, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } } object TLManagerParameters { @deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","") def apply( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = TLSlaveParameters.v1( address, resources, regionType, executable, nodePath, supportsAcquireT, supportsAcquireB, supportsArithmetic, supportsLogical, supportsGet, supportsPutFull, supportsPutPartial, supportsHint, mayDenyGet, mayDenyPut, alwaysGrantsT, fifoId, ) } case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int]) { def members = Seq(a, b, c, d) members.collect { case Some(beatBytes) => require (isPow2(beatBytes), "Data channel width must be a power of 2") } } object TLChannelBeatBytes{ def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes( Some(beatBytes), Some(beatBytes), Some(beatBytes), Some(beatBytes)) def apply(): TLChannelBeatBytes = TLChannelBeatBytes( None, None, None, None) } class TLSlavePortParameters private( val slaves: Seq[TLSlaveParameters], val channelBytes: TLChannelBeatBytes, val endSinkId: Int, val minLatency: Int, val responseFields: Seq[BundleFieldBase], val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct { def sortedSlaves = slaves.sortBy(_.sortedAddress.head) override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters] override def productPrefix = "TLSlavePortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => slaves case 1 => channelBytes case 2 => endSinkId case 3 => minLatency case 4 => responseFields case 5 => requestKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!slaves.isEmpty, "Slave ports must have slaves") require (endSinkId >= 0, "Sink ids cannot be negative") require (minLatency >= 0, "Minimum required latency cannot be negative") // Using this API implies you cannot handle mixed-width busses def beatBytes = { channelBytes.members.foreach { width => require (width.isDefined && width == channelBytes.a) } channelBytes.a.get } // TODO this should be deprecated def managers = slaves def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = { val relevant = slaves.filter(m => policy(m)) relevant.foreach { m => require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ") } } // Bounds on required sizes def maxAddress = slaves.map(_.maxAddress).max def maxTransfer = slaves.map(_.maxTransfer).max def mayDenyGet = slaves.exists(_.mayDenyGet) def mayDenyPut = slaves.exists(_.mayDenyPut) // Diplomatically determined operation sizes emitted by all outward Slaves // as opposed to emits which generate circuitry to check which specific addresses val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _) // Operation Emitted by at least one outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _) val allSupportAcquireT = allSupportClaims.acquireT val allSupportAcquireB = allSupportClaims.acquireB val allSupportArithmetic = allSupportClaims.arithmetic val allSupportLogical = allSupportClaims.logical val allSupportGet = allSupportClaims.get val allSupportPutFull = allSupportClaims.putFull val allSupportPutPartial = allSupportClaims.putPartial val allSupportHint = allSupportClaims.hint // Operation supported by at least one outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _) val anySupportAcquireT = !anySupportClaims.acquireT.none val anySupportAcquireB = !anySupportClaims.acquireB.none val anySupportArithmetic = !anySupportClaims.arithmetic.none val anySupportLogical = !anySupportClaims.logical.none val anySupportGet = !anySupportClaims.get.none val anySupportPutFull = !anySupportClaims.putFull.none val anySupportPutPartial = !anySupportClaims.putPartial.none val anySupportHint = !anySupportClaims.hint.none // Supporting Acquire means being routable for GrantAck require ((endSinkId == 0) == !anySupportAcquireB) // These return Option[TLSlaveParameters] for your convenience def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address))) // The safe version will check the entire address def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ \|\| _))) // The fast version assumes the address is valid (you probably want fastProperty instead of this function) def findFast(address: UInt) = { val routingMask = AddressDecoder(slaves.map(_.address)) VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ \|\| _))) } // Compute the simplest AddressSets that decide a key def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = { val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) => k -> vs.flatMap(_._2) } val reductionMask = AddressDecoder(groups.map(_._2)) groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) } } // Select a property def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D = Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_\|\|_), d(v)) }) // Note: returns the actual fifoId + 1 or 0 if None def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U) def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B) // Does this Port manage this ID/address? def containsSafe(address: UInt) = findSafe(address).reduce(_ \|\| _) private def addressHelper( // setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity safe: Boolean, // member filters out the sizes being checked based on the opcode being emitted or supported member: TLSlaveParameters => TransferSizes, address: UInt, lgSize: UInt, // range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity range: Option[TransferSizes]): Bool = { // trim reduces circuit complexity by intersecting checked sizes with the range argument def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x) // groupBy returns an unordered map, convert back to Seq and sort the result for determinism // groupByIntoSeq is turning slaves into trimmed membership sizes // We are grouping all the slaves by their transfer size where // if they support the trimmed size then // member is the type of transfer that you are looking for (What you are trying to filter on) // When you consider membership, you are trimming the sizes to only the ones that you care about // you are filtering the slaves based on both whether they support a particular opcode and the size // Grouping the slaves based on the actual transfer size range they support // intersecting the range and checking their membership // FOR SUPPORTCASES instead of returning the list of slaves, // you are returning a map from transfer size to the set of // address sets that are supported for that transfer size // find all the slaves that support a certain type of operation and then group their addresses by the supported size // for every size there could be multiple address ranges // safety is a trade off between checking between all possible addresses vs only the addresses // that are known to have supported sizes // the trade off is 'checking all addresses is a more expensive circuit but will always give you // the right answer even if you give it an illegal address' // the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer // fast presumes address legality // This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies. // In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size. val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) => k -> vs.flatMap(_.address) } // safe produces a circuit that compares against all possible addresses, // whereas fast presumes that the address is legal but uses an efficient address decoder val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2)) // Simplified creates the most concise possible representation of each cases' address sets based on the mask. val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) } simplified.map { case (s, a) => // s is a size, you are checking for this size either the size of the operation is in s // We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire. ((Some(s) == range).B \|\| s.containsLg(lgSize)) && a.map(_.contains(address)).reduce(_\|\|_) }.foldLeft(false.B)(_\|\|_) } def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range) def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range) def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range) def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range) def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range) def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range) def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range) def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range) def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range) def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range) def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range) def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range) def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range) def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range) def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range) def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range) def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range) def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range) def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range) def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range) def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range) def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range) def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range) def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption def isTree = !slaves.exists(!_.isTree) def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString def v1copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = managers, channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } def v2copy( slaves: Seq[TLSlaveParameters] = slaves, channelBytes: TLChannelBeatBytes = channelBytes, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = slaves, channelBytes = channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } @deprecated("Use v1copy instead of copy","") def copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { v1copy( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } object TLSlavePortParameters { def v1( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { new TLSlavePortParameters( slaves = managers, channelBytes = TLChannelBeatBytes(beatBytes), endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } } object TLManagerPortParameters { @deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","") def apply( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { TLSlavePortParameters.v1( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } class TLMasterParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], val name: String, val visibility: Seq[AddressSet], val unusedRegionTypes: Set[RegionType.T], val executesOnly: Boolean, val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C. val supports: TLSlaveToMasterTransferSizes, val emits: TLMasterToSlaveTransferSizes, val neverReleasesData: Boolean, val sourceId: IdRange) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters] override def productPrefix = "TLMasterParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 10 def productElement(n: Int): Any = n match { case 0 => name case 1 => sourceId case 2 => resources case 3 => visibility case 4 => unusedRegionTypes case 5 => executesOnly case 6 => requestFifo case 7 => supports case 8 => emits case 9 => neverReleasesData case _ => throw new IndexOutOfBoundsException(n.toString) } require (!sourceId.isEmpty) require (!visibility.isEmpty) require (supports.putFull.contains(supports.putPartial)) // We only support these operations if we support Probe (ie: we're a cache) require (supports.probe.contains(supports.arithmetic)) require (supports.probe.contains(supports.logical)) require (supports.probe.contains(supports.get)) require (supports.probe.contains(supports.putFull)) require (supports.probe.contains(supports.putPartial)) require (supports.probe.contains(supports.hint)) visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } val maxTransfer = List( supports.probe.max, supports.arithmetic.max, supports.logical.max, supports.get.max, supports.putFull.max, supports.putPartial.max).max def infoString = { s"""Master Name = ${name} \|visibility = ${visibility} \|emits = ${emits.infoString} \|sourceId = ${sourceId} \| \|""".stripMargin } def v1copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { new TLMasterParameters( nodePath = nodePath, resources = this.resources, name = name, visibility = visibility, unusedRegionTypes = this.unusedRegionTypes, executesOnly = this.executesOnly, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = this.emits, neverReleasesData = this.neverReleasesData, sourceId = sourceId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: String = name, visibility: Seq[AddressSet] = visibility, unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes, executesOnly: Boolean = executesOnly, requestFifo: Boolean = requestFifo, supports: TLSlaveToMasterTransferSizes = supports, emits: TLMasterToSlaveTransferSizes = emits, neverReleasesData: Boolean = neverReleasesData, sourceId: IdRange = sourceId) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } @deprecated("Use v1copy instead of copy","") def copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { v1copy( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } object TLMasterParameters { def v1( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { new TLMasterParameters( nodePath = nodePath, resources = Nil, name = name, visibility = visibility, unusedRegionTypes = Set(), executesOnly = false, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData = false, sourceId = sourceId) } def v2( nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Nil, name: String, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), unusedRegionTypes: Set[RegionType.T] = Set(), executesOnly: Boolean = false, requestFifo: Boolean = false, supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports, emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData: Boolean = false, sourceId: IdRange = IdRange(0,1)) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } } object TLClientParameters { @deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","") def apply( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet.everything), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { TLMasterParameters.v1( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } class TLMasterPortParameters private( val masters: Seq[TLMasterParameters], val channelBytes: TLChannelBeatBytes, val minLatency: Int, val echoFields: Seq[BundleFieldBase], val requestFields: Seq[BundleFieldBase], val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters] override def productPrefix = "TLMasterPortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => masters case 1 => channelBytes case 2 => minLatency case 3 => echoFields case 4 => requestFields case 5 => responseKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!masters.isEmpty) require (minLatency >= 0) def clients = masters // Require disjoint ranges for Ids IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) => require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}") } // Bounds on required sizes def endSourceId = masters.map(_.sourceId.end).max def maxTransfer = masters.map(_.maxTransfer).max // The unused sources < endSourceId def unusedSources: Seq[Int] = { val usedSources = masters.map(_.sourceId).sortBy(_.start) ((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) => end until start } } // Diplomatically determined operation sizes emitted by all inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = masters.map(_.emits).reduce( _ intersect _) // Diplomatically determined operation sizes Emitted by at least one inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all inward Masters // as opposed to supports* which generate circuitry to check which specific addresses val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _) val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _) val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _) val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _) val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _) val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _) val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _) // Diplomatically determined operation sizes supported by at least one master // as opposed to supports* which generate circuitry to check which specific addresses val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ \|\| _) val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ \|\| _) val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ \|\| _) val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ \|\| _) val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ \|\| _) val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ \|\| _) val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ \|\| _) // These return Option[TLMasterParameters] for your convenience def find(id: Int) = masters.find(_.sourceId.contains(id)) // Synthesizable lookup methods def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id))) def contains(id: UInt) = find(id).reduce(_ \|\| _) def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B)) // Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = { val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _) // this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version; // the case where there is only one group. if (allSame) member(masters(0)).containsLg(lgSize) else { // Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize Mux1H(find(id), masters.map(member(_).containsLg(lgSize))) } } // Check for support of a given operation at a specific id val supportsProbe = sourceIdHelper(_.supports.probe) _ val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _ val supportsLogical = sourceIdHelper(_.supports.logical) _ val supportsGet = sourceIdHelper(_.supports.get) _ val supportsPutFull = sourceIdHelper(_.supports.putFull) _ val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _ val supportsHint = sourceIdHelper(_.supports.hint) _ // TODO: Merge sourceIdHelper2 with sourceIdHelper private def sourceIdHelper2( member: TLMasterParameters => TransferSizes, sourceId: UInt, lgSize: UInt): Bool = { // Because sourceIds are uniquely owned by each master, we use them to group the // cases that have to be checked. val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) => k -> vs.map(_.sourceId) } emitCases.map { case (s, a) => (s.containsLg(lgSize)) && a.map(_.contains(sourceId)).reduce(_\|\|_) }.foldLeft(false.B)(_\|\|_) } // Check for emit of a given operation at a specific id def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize) def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize) def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize) def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize) def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize) def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize) def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize) def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize) def infoString = masters.map(_.infoString).mkString def v1copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = clients, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2copy( masters: Seq[TLMasterParameters] = masters, channelBytes: TLChannelBeatBytes = channelBytes, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } @deprecated("Use v1copy instead of copy","") def copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { v1copy( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLClientPortParameters { @deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","") def apply( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { TLMasterPortParameters.v1( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLMasterPortParameters { def v1( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = clients, channelBytes = TLChannelBeatBytes(), minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2( masters: Seq[TLMasterParameters], channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(), minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } } case class TLBundleParameters( addressBits: Int, dataBits: Int, sourceBits: Int, sinkBits: Int, sizeBits: Int, echoFields: Seq[BundleFieldBase], requestFields: Seq[BundleFieldBase], responseFields: Seq[BundleFieldBase], hasBCE: Boolean) { // Chisel has issues with 0-width wires require (addressBits >= 1) require (dataBits >= 8) require (sourceBits >= 1) require (sinkBits >= 1) require (sizeBits >= 1) require (isPow2(dataBits)) echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") } val addrLoBits = log2Up(dataBits/8) // Used to uniquify bus IP names def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u") def union(x: TLBundleParameters) = TLBundleParameters( max(addressBits, x.addressBits), max(dataBits, x.dataBits), max(sourceBits, x.sourceBits), max(sinkBits, x.sinkBits), max(sizeBits, x.sizeBits), echoFields = BundleField.union(echoFields ++ x.echoFields), requestFields = BundleField.union(requestFields ++ x.requestFields), responseFields = BundleField.union(responseFields ++ x.responseFields), hasBCE \|\| x.hasBCE) } object TLBundleParameters { val emptyBundleParams = TLBundleParameters( addressBits = 1, dataBits = 8, sourceBits = 1, sinkBits = 1, sizeBits = 1, echoFields = Nil, requestFields = Nil, responseFields = Nil, hasBCE = false) def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y)) def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) = new TLBundleParameters( addressBits = log2Up(slave.maxAddress + 1), dataBits = slave.beatBytes * 8, sourceBits = log2Up(master.endSourceId), sinkBits = log2Up(slave.endSinkId), sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1), echoFields = master.echoFields, requestFields = BundleField.accept(master.requestFields, slave.requestKeys), responseFields = BundleField.accept(slave.responseFields, master.responseKeys), hasBCE = master.anySupportProbe && slave.anySupportAcquireB) } case class TLEdgeParameters( master: TLMasterPortParameters, slave: TLSlavePortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { // legacy names: def manager = slave def client = master val maxTransfer = max(master.maxTransfer, slave.maxTransfer) val maxLgSize = log2Ceil(maxTransfer) // Sanity check the link... require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})") def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims) val bundle = TLBundleParameters(master, slave) def formatEdge = master.infoString + "\n" + slave.infoString } case class TLCreditedDelay( a: CreditedDelay, b: CreditedDelay, c: CreditedDelay, d: CreditedDelay, e: CreditedDelay) { def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay( a = a + that.a, b = b + that.b, c = c + that.c, d = d + that.d, e = e + that.e) override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})" } object TLCreditedDelay { def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay) } case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString} case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val delay = client.delay + manager.delay val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters) case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base)) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } // To be unified, devices must agree on all of these terms case class ManagerUnificationKey( resources: Seq[Resource], regionType: RegionType.T, executable: Boolean, supportsAcquireT: TransferSizes, supportsAcquireB: TransferSizes, supportsArithmetic: TransferSizes, supportsLogical: TransferSizes, supportsGet: TransferSizes, supportsPutFull: TransferSizes, supportsPutPartial: TransferSizes, supportsHint: TransferSizes) object ManagerUnificationKey { def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey( resources = x.resources, regionType = x.regionType, executable = x.executable, supportsAcquireT = x.supportsAcquireT, supportsAcquireB = x.supportsAcquireB, supportsArithmetic = x.supportsArithmetic, supportsLogical = x.supportsLogical, supportsGet = x.supportsGet, supportsPutFull = x.supportsPutFull, supportsPutPartial = x.supportsPutPartial, supportsHint = x.supportsHint) } object ManagerUnification { def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = { slaves.groupBy(ManagerUnificationKey.apply).values.map { seq => val agree = seq.forall(_.fifoId == seq.head.fifoId) seq(0).v1copy( address = AddressSet.unify(seq.flatMap(_.address)), fifoId = if (agree) seq(0).fifoId else None) }.toList } } case class TLBufferParams( a: BufferParams = BufferParams.none, b: BufferParams = BufferParams.none, c: BufferParams = BufferParams.none, d: BufferParams = BufferParams.none, e: BufferParams = BufferParams.none ) extends DirectedBuffers[TLBufferParams] { def copyIn(x: BufferParams) = this.copy(b = x, d = x) def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x) def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x) } /** Pretty printing of TL source id maps / class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] { private val tlDigits = String.valueOf(tl.endSourceId-1).length() protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s" private val sorted = tl.masters.sortBy(_.sourceId) val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c => TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo) } } case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean) extends IdMapEntry { val from = tlId val to = tlId val maxTransactionsInFlight = Some(tlId.size) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module ShuttleDCacheMSHR_3( // @[MSHR.scala:12:7] input clock, // @[MSHR.scala:12:7] input reset, // @[MSHR.scala:12:7] input io_req_pri_val, // @[MSHR.scala:13:14] output io_req_pri_rdy, // @[MSHR.scala:13:14] input io_req_sec_val, // @[MSHR.scala:13:14] output io_req_sec_rdy, // @[MSHR.scala:13:14] input [39:0] io_req_bits_addr, // @[MSHR.scala:13:14] input [6:0] io_req_bits_tag, // @[MSHR.scala:13:14] input [4:0] io_req_bits_cmd, // @[MSHR.scala:13:14] input [1:0] io_req_bits_size, // @[MSHR.scala:13:14] input io_req_bits_signed, // @[MSHR.scala:13:14] input [63:0] io_req_bits_data, // @[MSHR.scala:13:14] input [7:0] io_req_bits_mask, // @[MSHR.scala:13:14] input io_req_bits_tag_match, // @[MSHR.scala:13:14] input [1:0] io_req_bits_old_meta_coh_state, // @[MSHR.scala:13:14] input [19:0] io_req_bits_old_meta_tag, // @[MSHR.scala:13:14] input [3:0] io_req_bits_way_en, // @[MSHR.scala:13:14] input [4:0] io_req_bits_sdq_id, // @[MSHR.scala:13:14] input [31:0] io_probe_addr, // @[MSHR.scala:13:14] output io_idx_match, // @[MSHR.scala:13:14] output [19:0] io_tag, // @[MSHR.scala:13:14] input io_mem_acquire_ready, // @[MSHR.scala:13:14] output io_mem_acquire_valid, // @[MSHR.scala:13:14] output [2:0] io_mem_acquire_bits_param, // @[MSHR.scala:13:14] output [31:0] io_mem_acquire_bits_address, // @[MSHR.scala:13:14] input io_mem_grant_valid, // @[MSHR.scala:13:14] input [2:0] io_mem_grant_bits_opcode, // @[MSHR.scala:13:14] input [1:0] io_mem_grant_bits_param, // @[MSHR.scala:13:14] input [3:0] io_mem_grant_bits_size, // @[MSHR.scala:13:14] input [2:0] io_mem_grant_bits_source, // @[MSHR.scala:13:14] input [2:0] io_mem_grant_bits_sink, // @[MSHR.scala:13:14] input io_mem_grant_bits_denied, // @[MSHR.scala:13:14] input [63:0] io_mem_grant_bits_data, // @[MSHR.scala:13:14] input io_mem_grant_bits_corrupt, // @[MSHR.scala:13:14] input io_mem_finish_ready, // @[MSHR.scala:13:14] output io_mem_finish_valid, // @[MSHR.scala:13:14] output [2:0] io_mem_finish_bits_sink, // @[MSHR.scala:13:14] output [3:0] io_refill_way_en, // @[MSHR.scala:13:14] output [11:0] io_refill_addr, // @[MSHR.scala:13:14] input io_meta_write_ready, // @[MSHR.scala:13:14] output io_meta_write_valid, // @[MSHR.scala:13:14] output [5:0] io_meta_write_bits_idx, // @[MSHR.scala:13:14] output [3:0] io_meta_write_bits_way_en, // @[MSHR.scala:13:14] output [19:0] io_meta_write_bits_tag, // @[MSHR.scala:13:14] output [1:0] io_meta_write_bits_data_coh_state, // @[MSHR.scala:13:14] output [19:0] io_meta_write_bits_data_tag, // @[MSHR.scala:13:14] input io_replay_ready, // @[MSHR.scala:13:14] output io_replay_valid, // @[MSHR.scala:13:14] output [39:0] io_replay_bits_addr, // @[MSHR.scala:13:14] output [6:0] io_replay_bits_tag, // @[MSHR.scala:13:14] output [4:0] io_replay_bits_cmd, // @[MSHR.scala:13:14] output [1:0] io_replay_bits_size, // @[MSHR.scala:13:14] output io_replay_bits_signed, // @[MSHR.scala:13:14] output [63:0] io_replay_bits_data, // @[MSHR.scala:13:14] output [7:0] io_replay_bits_mask, // @[MSHR.scala:13:14] output io_replay_bits_tag_match, // @[MSHR.scala:13:14] output [1:0] io_replay_bits_old_meta_coh_state, // @[MSHR.scala:13:14] output [19:0] io_replay_bits_old_meta_tag, // @[MSHR.scala:13:14] output [3:0] io_replay_bits_way_en, // @[MSHR.scala:13:14] output [4:0] io_replay_bits_sdq_id, // @[MSHR.scala:13:14] input io_wb_req_ready, // @[MSHR.scala:13:14] output io_wb_req_valid, // @[MSHR.scala:13:14] output [19:0] io_wb_req_bits_tag, // @[MSHR.scala:13:14] output [5:0] io_wb_req_bits_idx, // @[MSHR.scala:13:14] output [2:0] io_wb_req_bits_param, // @[MSHR.scala:13:14] output [3:0] io_wb_req_bits_way_en, // @[MSHR.scala:13:14] output io_probe_rdy // @[MSHR.scala:13:14] ); wire [19:0] io_tag_0; // @[MSHR.scala:12:7] wire _grantackq_io_enq_ready; // @[MSHR.scala:126:25] wire _grantackq_io_deq_valid; // @[MSHR.scala:126:25] wire _rpq_io_enq_ready; // @[MSHR.scala:63:19] wire _rpq_io_deq_valid; // @[MSHR.scala:63:19] wire [39:0] _rpq_io_deq_bits_addr; // @[MSHR.scala:63:19] wire io_req_pri_val_0 = io_req_pri_val; // @[MSHR.scala:12:7] wire io_req_sec_val_0 = io_req_sec_val; // @[MSHR.scala:12:7] wire [39:0] io_req_bits_addr_0 = io_req_bits_addr; // @[MSHR.scala:12:7] wire [6:0] io_req_bits_tag_0 = io_req_bits_tag; // @[MSHR.scala:12:7] wire [4:0] io_req_bits_cmd_0 = io_req_bits_cmd; // @[MSHR.scala:12:7] wire [1:0] io_req_bits_size_0 = io_req_bits_size; // @[MSHR.scala:12:7] wire io_req_bits_signed_0 = io_req_bits_signed; // @[MSHR.scala:12:7] wire [63:0] io_req_bits_data_0 = io_req_bits_data; // @[MSHR.scala:12:7] wire [7:0] io_req_bits_mask_0 = io_req_bits_mask; // @[MSHR.scala:12:7] wire io_req_bits_tag_match_0 = io_req_bits_tag_match; // @[MSHR.scala:12:7] wire [1:0] io_req_bits_old_meta_coh_state_0 = io_req_bits_old_meta_coh_state; // @[MSHR.scala:12:7] wire [19:0] io_req_bits_old_meta_tag_0 = io_req_bits_old_meta_tag; // @[MSHR.scala:12:7] wire [3:0] io_req_bits_way_en_0 = io_req_bits_way_en; // @[MSHR.scala:12:7] wire [4:0] io_req_bits_sdq_id_0 = io_req_bits_sdq_id; // @[MSHR.scala:12:7] wire [31:0] io_probe_addr_0 = io_probe_addr; // @[MSHR.scala:12:7] wire io_mem_acquire_ready_0 = io_mem_acquire_ready; // @[MSHR.scala:12:7] wire io_mem_grant_valid_0 = io_mem_grant_valid; // @[MSHR.scala:12:7] wire [2:0] io_mem_grant_bits_opcode_0 = io_mem_grant_bits_opcode; // @[MSHR.scala:12:7] wire [1:0] io_mem_grant_bits_param_0 = io_mem_grant_bits_param; // @[MSHR.scala:12:7] wire [3:0] io_mem_grant_bits_size_0 = io_mem_grant_bits_size; // @[MSHR.scala:12:7] wire [2:0] io_mem_grant_bits_source_0 = io_mem_grant_bits_source; // @[MSHR.scala:12:7] wire [2:0] io_mem_grant_bits_sink_0 = io_mem_grant_bits_sink; // @[MSHR.scala:12:7] wire io_mem_grant_bits_denied_0 = io_mem_grant_bits_denied; // @[MSHR.scala:12:7] wire [63:0] io_mem_grant_bits_data_0 = io_mem_grant_bits_data; // @[MSHR.scala:12:7] wire io_mem_grant_bits_corrupt_0 = io_mem_grant_bits_corrupt; // @[MSHR.scala:12:7] wire io_mem_finish_ready_0 = io_mem_finish_ready; // @[MSHR.scala:12:7] wire io_meta_write_ready_0 = io_meta_write_ready; // @[MSHR.scala:12:7] wire io_replay_ready_0 = io_replay_ready; // @[MSHR.scala:12:7] wire io_wb_req_ready_0 = io_wb_req_ready; // @[MSHR.scala:12:7] wire [1:0] _grow_param_r_T_7 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _grow_param_r_T_9 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _grow_param_r_T_17 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _grow_param_r_T_19 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _coh_on_grant_T_5 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r1_T_7 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r1_T_9 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r1_T_17 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r1_T_19 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r2_T_7 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r2_T_9 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r2_T_17 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r2_T_19 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_71 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_73 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_81 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_83 = 2'h1; // @[Metadata.scala:25:15] wire [3:0] _r_T_15 = 4'hB; // @[Metadata.scala:130:10] wire [3:0] _needs_wb_r_T_15 = 4'hB; // @[Metadata.scala:130:10] wire [3:0] _r_T_16 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _needs_wb_r_T_16 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _r_T_17 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _needs_wb_r_T_17 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _r_T_18 = 4'h8; // @[Metadata.scala:133:10] wire [3:0] _needs_wb_r_T_18 = 4'h8; // @[Metadata.scala:133:10] wire [3:0] _r_T_7 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _grow_param_r_T_2 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _r1_T_2 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _r2_T_2 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _needs_wb_r_T_7 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _r_T_66 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _r_T_8 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _grow_param_r_T_4 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _r1_T_4 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _r2_T_4 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _needs_wb_r_T_8 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _r_T_68 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _r_T_9 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _grow_param_r_T_6 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _coh_on_grant_T_2 = 4'h1; // @[Metadata.scala:86:10] wire [3:0] _r1_T_6 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _r2_T_6 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _needs_wb_r_T_9 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _r_T_70 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _r_T_11 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _grow_param_r_T_8 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _r1_T_8 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _r2_T_8 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _needs_wb_r_T_11 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _r_T_72 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _grow_param_r_T_14 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _r1_T_14 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _r2_T_14 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _r_T_78 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _r_T_10 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _grow_param_r_T_16 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _coh_on_grant_T_4 = 4'h0; // @[Metadata.scala:87:10] wire [3:0] _r1_T_16 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _r2_T_16 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _needs_wb_r_T_10 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _r_T_80 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _r_T_13 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] _grow_param_r_T_18 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _r1_T_18 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _r2_T_18 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _needs_wb_r_T_13 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] _r_T_82 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _grow_param_r_T_22 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r1_T_22 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r2_T_22 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r_T_86 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _grow_param_r_T_24 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _coh_on_grant_T_8 = 4'hC; // @[Metadata.scala:89:10] wire [3:0] _r1_T_24 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _r2_T_24 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _r_T_88 = 4'hC; // @[Metadata.scala:72:10] wire [1:0] new_coh_meta_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] _r_T_22 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_26 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_30 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_34 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_38 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _grow_param_r_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _grow_param_r_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _grow_param_r_T_5 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _grow_param_r_T_15 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _coh_on_grant_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _coh_on_grant_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r1_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r1_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r1_T_5 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r1_T_15 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r2_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r2_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r2_T_5 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r2_T_15 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _needs_wb_r_T_22 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _needs_wb_r_T_26 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _needs_wb_r_T_30 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _needs_wb_r_T_34 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _needs_wb_r_T_38 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_65 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_67 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_69 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_79 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] new_coh_meta_1_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] _r_T_1 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _r_T_3 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _r_T_5 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _needs_wb_r_T_1 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _needs_wb_r_T_3 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _needs_wb_r_T_5 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] io_mem_acquire_bits_a_mask_sizeOH_shiftAmount = 2'h2; // @[OneHot.scala:64:49] wire [3:0] _r_T_14 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _grow_param_r_T_20 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _coh_on_grant_T_6 = 4'h4; // @[Metadata.scala:88:10] wire [3:0] _r1_T_20 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _r2_T_20 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _needs_wb_r_T_14 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _r_T_84 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _io_mem_acquire_bits_a_mask_sizeOH_T_1 = 4'h4; // @[OneHot.scala:65:12] wire [2:0] _io_mem_acquire_bits_a_mask_sizeOH_T_2 = 3'h4; // @[OneHot.scala:65:27] wire [2:0] io_mem_acquire_bits_a_mask_sizeOH = 3'h5; // @[Misc.scala:202:81] wire [1:0] _grow_param_r_T_11 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _grow_param_r_T_13 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _grow_param_r_T_21 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _grow_param_r_T_23 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _coh_on_grant_T_7 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r1_T_11 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r1_T_13 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r1_T_21 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r1_T_23 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r2_T_11 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r2_T_13 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r2_T_21 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r2_T_23 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _dirties_T = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_75 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_77 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_85 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_87 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] io_mem_acquire_bits_a_mask_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [3:0] _grow_param_r_T_12 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _r1_T_12 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _r2_T_12 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _r_T_76 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] io_mem_acquire_bits_a_mask_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] io_mem_acquire_bits_a_mask_hi = 4'hF; // @[Misc.scala:222:10] wire io_wb_req_bits_voluntary = 1'h1; // @[MSHR.scala:12:7] wire _r_T = 1'h1; // @[Metadata.scala:140:24] wire _needs_wb_r_T = 1'h1; // @[Metadata.scala:140:24] wire _io_mem_acquire_bits_legal_T_19 = 1'h1; // @[Parameters.scala:91:44] wire _io_mem_acquire_bits_legal_T_20 = 1'h1; // @[Parameters.scala:684:29] wire io_mem_acquire_bits_a_mask_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire io_mem_acquire_bits_a_mask_sub_sub_size = 1'h1; // @[Misc.scala:209:26] wire io_mem_acquire_bits_a_mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_2_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_3_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_size = 1'h1; // @[Misc.scala:209:26] wire io_mem_acquire_bits_a_mask_acc = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_4 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_5 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_6 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_7 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_corrupt = 1'h0; // @[MSHR.scala:12:7] wire _r_T_2 = 1'h0; // @[Metadata.scala:140:24] wire _r_T_4 = 1'h0; // @[Metadata.scala:140:24] wire _r_T_20 = 1'h0; // @[Misc.scala:38:9] wire _r_T_24 = 1'h0; // @[Misc.scala:38:9] wire _r_T_28 = 1'h0; // @[Misc.scala:38:9] wire _grow_param_r_T_26 = 1'h0; // @[Misc.scala:35:9] wire _grow_param_r_T_29 = 1'h0; // @[Misc.scala:35:9] wire _grow_param_r_T_32 = 1'h0; // @[Misc.scala:35:9] wire _grow_param_r_T_35 = 1'h0; // @[Misc.scala:35:9] wire _grow_param_r_T_38 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_26 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_29 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_32 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_35 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_38 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_26 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_29 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_32 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_35 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_38 = 1'h0; // @[Misc.scala:35:9] wire _needs_wb_r_T_2 = 1'h0; // @[Metadata.scala:140:24] wire _needs_wb_r_T_4 = 1'h0; // @[Metadata.scala:140:24] wire _needs_wb_r_T_20 = 1'h0; // @[Misc.scala:38:9] wire _needs_wb_r_T_24 = 1'h0; // @[Misc.scala:38:9] wire _needs_wb_r_T_28 = 1'h0; // @[Misc.scala:38:9] wire _r_T_90 = 1'h0; // @[Misc.scala:35:9] wire _r_T_93 = 1'h0; // @[Misc.scala:35:9] wire _r_T_96 = 1'h0; // @[Misc.scala:35:9] wire _r_T_99 = 1'h0; // @[Misc.scala:35:9] wire _r_T_102 = 1'h0; // @[Misc.scala:35:9] wire _io_mem_acquire_bits_legal_T = 1'h0; // @[Parameters.scala:684:29] wire _io_mem_acquire_bits_legal_T_18 = 1'h0; // @[Parameters.scala:684:54] wire _io_mem_acquire_bits_legal_T_33 = 1'h0; // @[Parameters.scala:686:26] wire io_mem_acquire_bits_a_corrupt = 1'h0; // @[Edges.scala:346:17] wire io_mem_acquire_bits_a_mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _io_mem_acquire_bits_a_mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire [63:0] io_mem_acquire_bits_data = 64'h0; // @[MSHR.scala:12:7] wire [63:0] io_mem_acquire_bits_a_data = 64'h0; // @[Edges.scala:346:17] wire [7:0] io_mem_acquire_bits_mask = 8'hFF; // @[MSHR.scala:12:7, :13:14] wire [7:0] io_mem_acquire_bits_a_mask = 8'hFF; // @[MSHR.scala:12:7, :13:14] wire [7:0] _io_mem_acquire_bits_a_mask_T = 8'hFF; // @[MSHR.scala:12:7, :13:14] wire [2:0] io_mem_acquire_bits_source = 3'h3; // @[MSHR.scala:12:7] wire [2:0] io_wb_req_bits_source = 3'h3; // @[MSHR.scala:12:7] wire [2:0] io_mem_acquire_bits_a_source = 3'h3; // @[Edges.scala:346:17] wire [3:0] io_mem_acquire_bits_size = 4'h6; // @[MSHR.scala:12:7] wire [3:0] _r_T_12 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] _grow_param_r_T_10 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _r1_T_10 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _r2_T_10 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _needs_wb_r_T_12 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] _r_T_74 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] io_mem_acquire_bits_a_size = 4'h6; // @[Edges.scala:346:17] wire [2:0] io_mem_acquire_bits_opcode = 3'h6; // @[MSHR.scala:12:7] wire [2:0] io_mem_acquire_bits_a_opcode = 3'h6; // @[Edges.scala:346:17] wire [2:0] _io_mem_acquire_bits_a_mask_sizeOH_T = 3'h6; // @[Misc.scala:202:34] wire _io_req_pri_rdy_T; // @[MSHR.scala:138:27] wire _io_req_sec_rdy_T; // @[MSHR.scala:139:29] wire _io_idx_match_T_1; // @[MSHR.scala:134:41] wire [19:0] io_meta_write_bits_tag_0 = io_tag_0; // @[MSHR.scala:12:7] wire [19:0] io_meta_write_bits_data_tag_0 = io_tag_0; // @[MSHR.scala:12:7] wire _io_mem_acquire_valid_T_1; // @[MSHR.scala:161:50] wire [2:0] io_mem_acquire_bits_a_param; // @[Edges.scala:346:17] wire [31:0] io_mem_acquire_bits_a_address; // @[Edges.scala:346:17] wire [2:0] grantackq_io_enq_bits_e_sink = io_mem_grant_bits_sink_0; // @[MSHR.scala:12:7] wire _io_mem_finish_valid_T; // @[MSHR.scala:130:49] wire _io_meta_write_valid_T_2; // @[package.scala:81:59] wire [5:0] req_idx; // @[MSHR.scala:39:25] wire [1:0] _io_meta_write_bits_data_coh_T_1_state; // @[MSHR.scala:149:37] wire _io_replay_valid_T_1; // @[MSHR.scala:168:44] wire _io_wb_req_valid_T; // @[MSHR.scala:153:28] wire [2:0] shrink_param; // @[Misc.scala:38:36] wire _io_probe_rdy_T_11; // @[MSHR.scala:144:61] wire [2:0] io_mem_acquire_bits_param_0; // @[MSHR.scala:12:7] wire [31:0] io_mem_acquire_bits_address_0; // @[MSHR.scala:12:7] wire io_mem_acquire_valid_0; // @[MSHR.scala:12:7] wire [2:0] io_mem_finish_bits_sink_0; // @[MSHR.scala:12:7] wire io_mem_finish_valid_0; // @[MSHR.scala:12:7] wire [3:0] io_refill_way_en_0; // @[MSHR.scala:12:7] wire [11:0] io_refill_addr_0; // @[MSHR.scala:12:7] wire [1:0] io_meta_write_bits_data_coh_state_0; // @[MSHR.scala:12:7] wire [5:0] io_meta_write_bits_idx_0; // @[MSHR.scala:12:7] wire [3:0] io_meta_write_bits_way_en_0; // @[MSHR.scala:12:7] wire io_meta_write_valid_0; // @[MSHR.scala:12:7] wire [1:0] io_replay_bits_old_meta_coh_state_0; // @[MSHR.scala:12:7] wire [19:0] io_replay_bits_old_meta_tag_0; // @[MSHR.scala:12:7] wire [39:0] io_replay_bits_addr_0; // @[MSHR.scala:12:7] wire [6:0] io_replay_bits_tag_0; // @[MSHR.scala:12:7] wire [4:0] io_replay_bits_cmd_0; // @[MSHR.scala:12:7] wire [1:0] io_replay_bits_size_0; // @[MSHR.scala:12:7] wire io_replay_bits_signed_0; // @[MSHR.scala:12:7] wire [63:0] io_replay_bits_data_0; // @[MSHR.scala:12:7] wire [7:0] io_replay_bits_mask_0; // @[MSHR.scala:12:7] wire io_replay_bits_tag_match_0; // @[MSHR.scala:12:7] wire [3:0] io_replay_bits_way_en_0; // @[MSHR.scala:12:7] wire [4:0] io_replay_bits_sdq_id_0; // @[MSHR.scala:12:7] wire io_replay_valid_0; // @[MSHR.scala:12:7] wire [19:0] io_wb_req_bits_tag_0; // @[MSHR.scala:12:7] wire [5:0] io_wb_req_bits_idx_0; // @[MSHR.scala:12:7] wire [2:0] io_wb_req_bits_param_0; // @[MSHR.scala:12:7] wire [3:0] io_wb_req_bits_way_en_0; // @[MSHR.scala:12:7] wire io_wb_req_valid_0; // @[MSHR.scala:12:7] wire io_req_pri_rdy_0; // @[MSHR.scala:12:7] wire io_req_sec_rdy_0; // @[MSHR.scala:12:7] wire io_idx_match_0; // @[MSHR.scala:12:7] wire io_probe_rdy_0; // @[MSHR.scala:12:7] reg [3:0] state; // @[MSHR.scala:36:22] reg [39:0] req_addr; // @[MSHR.scala:38:16] reg [6:0] req_tag; // @[MSHR.scala:38:16] reg [4:0] req_cmd; // @[MSHR.scala:38:16] reg [1:0] req_size; // @[MSHR.scala:38:16] reg req_signed; // @[MSHR.scala:38:16] reg [63:0] req_data; // @[MSHR.scala:38:16] reg [7:0] req_mask; // @[MSHR.scala:38:16] reg req_tag_match; // @[MSHR.scala:38:16] reg [1:0] req_old_meta_coh_state; // @[MSHR.scala:38:16] reg [19:0] req_old_meta_tag; // @[MSHR.scala:38:16] assign io_wb_req_bits_tag_0 = req_old_meta_tag; // @[MSHR.scala:12:7, :38:16] reg [3:0] req_way_en; // @[MSHR.scala:38:16] assign io_refill_way_en_0 = req_way_en; // @[MSHR.scala:12:7, :38:16] assign io_meta_write_bits_way_en_0 = req_way_en; // @[MSHR.scala:12:7, :38:16] assign io_wb_req_bits_way_en_0 = req_way_en; // @[MSHR.scala:12:7, :38:16] reg [4:0] req_sdq_id; // @[MSHR.scala:38:16] assign req_idx = req_addr[11:6]; // @[MSHR.scala:38:16, :39:25] assign io_meta_write_bits_idx_0 = req_idx; // @[MSHR.scala:12:7, :39:25] assign io_wb_req_bits_idx_0 = req_idx; // @[MSHR.scala:12:7, :39:25] wire [27:0] req_tag_0 = req_addr[39:12]; // @[MSHR.scala:38:16, :40:26] wire [33:0] _req_block_addr_T = req_addr[39:6]; // @[MSHR.scala:38:16, :41:34] wire [39:0] req_block_addr = {_req_block_addr_T, 6'h0}; // @[MSHR.scala:41:{34,51}] wire [5:0] _idx_match_T = io_req_bits_addr_0[11:6]; // @[MSHR.scala:12:7, :42:47] wire idx_match = req_idx == _idx_match_T; // @[MSHR.scala:39:25, :42:{27,47}] wire [5:0] _probe_idx_match_T = io_probe_addr_0[11:6]; // @[MSHR.scala:12:7, :43:50] wire probe_idx_match = req_idx == _probe_idx_match_T; // @[MSHR.scala:39:25, :43:{33,50}] reg [1:0] new_coh_state; // @[MSHR.scala:45:24] wire [3:0] _r_T_6 = {2'h2, req_old_meta_coh_state}; // @[MSHR.scala:38:16] wire _r_T_19 = _r_T_6 == 4'h8; // @[Misc.scala:56:20] wire [2:0] _r_T_21 = _r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _r_T_23 = _r_T_6 == 4'h9; // @[Misc.scala:56:20] wire [2:0] _r_T_25 = _r_T_23 ? 3'h2 : _r_T_21; // @[Misc.scala:38:36, :56:20] wire _r_T_27 = _r_T_6 == 4'hA; // @[Misc.scala:56:20] wire [2:0] _r_T_29 = _r_T_27 ? 3'h1 : _r_T_25; // @[MSHR.scala:142:59] wire _r_T_31 = _r_T_6 == 4'hB; // @[Misc.scala:56:20] wire _r_T_32 = _r_T_31; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_33 = _r_T_31 ? 3'h1 : _r_T_29; // @[MSHR.scala:142:59] wire _r_T_35 = _r_T_6 == 4'h4; // @[Misc.scala:56:20] wire _r_T_36 = ~_r_T_35 & _r_T_32; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_37 = _r_T_35 ? 3'h5 : _r_T_33; // @[Misc.scala:38:36, :56:20] wire _r_T_39 = _r_T_6 == 4'h5; // @[Misc.scala:56:20] wire _r_T_40 = ~_r_T_39 & _r_T_36; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_41 = _r_T_39 ? 3'h4 : _r_T_37; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_42 = {1'h0, _r_T_39}; // @[Misc.scala:38:63, :56:20] wire _r_T_43 = _r_T_6 == 4'h6; // @[Misc.scala:56:20] wire _r_T_44 = ~_r_T_43 & _r_T_40; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_45 = _r_T_43 ? 3'h0 : _r_T_41; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_46 = _r_T_43 ? 2'h1 : _r_T_42; // @[Misc.scala:38:63, :56:20] wire _r_T_47 = _r_T_6 == 4'h7; // @[Misc.scala:56:20] wire _r_T_48 = _r_T_47 \| _r_T_44; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_49 = _r_T_47 ? 3'h0 : _r_T_45; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_50 = _r_T_47 ? 2'h1 : _r_T_46; // @[Misc.scala:38:63, :56:20] wire _r_T_51 = _r_T_6 == 4'h0; // @[Misc.scala:56:20] wire _r_T_52 = ~_r_T_51 & _r_T_48; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_53 = _r_T_51 ? 3'h5 : _r_T_49; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_54 = _r_T_51 ? 2'h0 : _r_T_50; // @[Misc.scala:38:63, :56:20] wire _r_T_55 = _r_T_6 == 4'h1; // @[Misc.scala:56:20] wire _r_T_56 = ~_r_T_55 & _r_T_52; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_57 = _r_T_55 ? 3'h4 : _r_T_53; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_58 = _r_T_55 ? 2'h1 : _r_T_54; // @[Misc.scala:38:63, :56:20] wire _r_T_59 = _r_T_6 == 4'h2; // @[Misc.scala:56:20] wire _r_T_60 = ~_r_T_59 & _r_T_56; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_61 = _r_T_59 ? 3'h3 : _r_T_57; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_62 = _r_T_59 ? 2'h2 : _r_T_58; // @[Misc.scala:38:63, :56:20] wire _r_T_63 = _r_T_6 == 4'h3; // @[Misc.scala:56:20] wire r_1 = _r_T_63 \| _r_T_60; // @[Misc.scala:38:9, :56:20] assign shrink_param = _r_T_63 ? 3'h3 : _r_T_61; // @[Misc.scala:38:36, :56:20] assign io_wb_req_bits_param_0 = shrink_param; // @[MSHR.scala:12:7] wire [1:0] r_3 = _r_T_63 ? 2'h2 : _r_T_62; // @[Misc.scala:38:63, :56:20] wire [1:0] coh_on_clear_state = r_3; // @[Misc.scala:38:63] wire _GEN = req_cmd == 5'h1; // @[MSHR.scala:38:16] wire _grow_param_r_c_cat_T; // @[Consts.scala:90:32] assign _grow_param_r_c_cat_T = _GEN; // @[Consts.scala:90:32] wire _grow_param_r_c_cat_T_23; // @[Consts.scala:90:32] assign _grow_param_r_c_cat_T_23 = _GEN; // @[Consts.scala:90:32] wire _coh_on_grant_c_cat_T; // @[Consts.scala:90:32] assign _coh_on_grant_c_cat_T = _GEN; // @[Consts.scala:90:32] wire _coh_on_grant_c_cat_T_23; // @[Consts.scala:90:32] assign _coh_on_grant_c_cat_T_23 = _GEN; // @[Consts.scala:90:32] wire _r1_c_cat_T; // @[Consts.scala:90:32] assign _r1_c_cat_T = _GEN; // @[Consts.scala:90:32] wire _r1_c_cat_T_23; // @[Consts.scala:90:32] assign _r1_c_cat_T_23 = _GEN; // @[Consts.scala:90:32] wire _needs_second_acq_T_27; // @[Consts.scala:90:32] assign _needs_second_acq_T_27 = _GEN; // @[Consts.scala:90:32] wire _GEN_0 = req_cmd == 5'h11; // @[MSHR.scala:38:16] wire _grow_param_r_c_cat_T_1; // @[Consts.scala:90:49] assign _grow_param_r_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49] wire _grow_param_r_c_cat_T_24; // @[Consts.scala:90:49] assign _grow_param_r_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49] wire _coh_on_grant_c_cat_T_1; // @[Consts.scala:90:49] assign _coh_on_grant_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49] wire _coh_on_grant_c_cat_T_24; // @[Consts.scala:90:49] assign _coh_on_grant_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49] wire _r1_c_cat_T_1; // @[Consts.scala:90:49] assign _r1_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49] wire _r1_c_cat_T_24; // @[Consts.scala:90:49] assign _r1_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49] wire _needs_second_acq_T_28; // @[Consts.scala:90:49] assign _needs_second_acq_T_28 = _GEN_0; // @[Consts.scala:90:49] wire _grow_param_r_c_cat_T_2 = _grow_param_r_c_cat_T \| _grow_param_r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _GEN_1 = req_cmd == 5'h7; // @[MSHR.scala:38:16] wire _grow_param_r_c_cat_T_3; // @[Consts.scala:90:66] assign _grow_param_r_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66] wire _grow_param_r_c_cat_T_26; // @[Consts.scala:90:66] assign _grow_param_r_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66] wire _coh_on_grant_c_cat_T_3; // @[Consts.scala:90:66] assign _coh_on_grant_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66] wire _coh_on_grant_c_cat_T_26; // @[Consts.scala:90:66] assign _coh_on_grant_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66] wire _r1_c_cat_T_3; // @[Consts.scala:90:66] assign _r1_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66] wire _r1_c_cat_T_26; // @[Consts.scala:90:66] assign _r1_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66] wire _needs_second_acq_T_30; // @[Consts.scala:90:66] assign _needs_second_acq_T_30 = _GEN_1; // @[Consts.scala:90:66] wire _grow_param_r_c_cat_T_4 = _grow_param_r_c_cat_T_2 \| _grow_param_r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _GEN_2 = req_cmd == 5'h4; // @[MSHR.scala:38:16] wire _grow_param_r_c_cat_T_5; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_5 = _GEN_2; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_28; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_28 = _GEN_2; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_5; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_5 = _GEN_2; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_28; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_28 = _GEN_2; // @[package.scala:16:47] wire _r1_c_cat_T_5; // @[package.scala:16:47] assign _r1_c_cat_T_5 = _GEN_2; // @[package.scala:16:47] wire _r1_c_cat_T_28; // @[package.scala:16:47] assign _r1_c_cat_T_28 = _GEN_2; // @[package.scala:16:47] wire _needs_second_acq_T_32; // @[package.scala:16:47] assign _needs_second_acq_T_32 = _GEN_2; // @[package.scala:16:47] wire _GEN_3 = req_cmd == 5'h9; // @[MSHR.scala:38:16] wire _grow_param_r_c_cat_T_6; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_6 = _GEN_3; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_29; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_29 = _GEN_3; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_6; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_6 = _GEN_3; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_29; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_29 = _GEN_3; // @[package.scala:16:47] wire _r1_c_cat_T_6; // @[package.scala:16:47] assign _r1_c_cat_T_6 = _GEN_3; // @[package.scala:16:47] wire _r1_c_cat_T_29; // @[package.scala:16:47] assign _r1_c_cat_T_29 = _GEN_3; // @[package.scala:16:47] wire _needs_second_acq_T_33; // @[package.scala:16:47] assign _needs_second_acq_T_33 = _GEN_3; // @[package.scala:16:47] wire _GEN_4 = req_cmd == 5'hA; // @[MSHR.scala:38:16] wire _grow_param_r_c_cat_T_7; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_7 = _GEN_4; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_30; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_30 = _GEN_4; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_7; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_7 = _GEN_4; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_30; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_30 = _GEN_4; // @[package.scala:16:47] wire _r1_c_cat_T_7; // @[package.scala:16:47] assign _r1_c_cat_T_7 = _GEN_4; // @[package.scala:16:47] wire _r1_c_cat_T_30; // @[package.scala:16:47] assign _r1_c_cat_T_30 = _GEN_4; // @[package.scala:16:47] wire _needs_second_acq_T_34; // @[package.scala:16:47] assign _needs_second_acq_T_34 = _GEN_4; // @[package.scala:16:47] wire _GEN_5 = req_cmd == 5'hB; // @[MSHR.scala:38:16] wire _grow_param_r_c_cat_T_8; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_8 = _GEN_5; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_31; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_31 = _GEN_5; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_8; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_8 = _GEN_5; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_31; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_31 = _GEN_5; // @[package.scala:16:47] wire _r1_c_cat_T_8; // @[package.scala:16:47] assign _r1_c_cat_T_8 = _GEN_5; // @[package.scala:16:47] wire _r1_c_cat_T_31; // @[package.scala:16:47] assign _r1_c_cat_T_31 = _GEN_5; // @[package.scala:16:47] wire _needs_second_acq_T_35; // @[package.scala:16:47] assign _needs_second_acq_T_35 = _GEN_5; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_9 = _grow_param_r_c_cat_T_5 \| _grow_param_r_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_10 = _grow_param_r_c_cat_T_9 \| _grow_param_r_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_11 = _grow_param_r_c_cat_T_10 \| _grow_param_r_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _GEN_6 = req_cmd == 5'h8; // @[MSHR.scala:38:16] wire _grow_param_r_c_cat_T_12; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_12 = _GEN_6; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_35; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_35 = _GEN_6; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_12; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_12 = _GEN_6; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_35; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_35 = _GEN_6; // @[package.scala:16:47] wire _r1_c_cat_T_12; // @[package.scala:16:47] assign _r1_c_cat_T_12 = _GEN_6; // @[package.scala:16:47] wire _r1_c_cat_T_35; // @[package.scala:16:47] assign _r1_c_cat_T_35 = _GEN_6; // @[package.scala:16:47] wire _needs_second_acq_T_39; // @[package.scala:16:47] assign _needs_second_acq_T_39 = _GEN_6; // @[package.scala:16:47] wire _GEN_7 = req_cmd == 5'hC; // @[MSHR.scala:38:16] wire _grow_param_r_c_cat_T_13; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_13 = _GEN_7; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_36; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_36 = _GEN_7; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_13; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_13 = _GEN_7; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_36; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_36 = _GEN_7; // @[package.scala:16:47] wire _r1_c_cat_T_13; // @[package.scala:16:47] assign _r1_c_cat_T_13 = _GEN_7; // @[package.scala:16:47] wire _r1_c_cat_T_36; // @[package.scala:16:47] assign _r1_c_cat_T_36 = _GEN_7; // @[package.scala:16:47] wire _needs_second_acq_T_40; // @[package.scala:16:47] assign _needs_second_acq_T_40 = _GEN_7; // @[package.scala:16:47] wire _GEN_8 = req_cmd == 5'hD; // @[MSHR.scala:38:16] wire _grow_param_r_c_cat_T_14; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_14 = _GEN_8; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_37; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_37 = _GEN_8; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_14; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_14 = _GEN_8; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_37; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_37 = _GEN_8; // @[package.scala:16:47] wire _r1_c_cat_T_14; // @[package.scala:16:47] assign _r1_c_cat_T_14 = _GEN_8; // @[package.scala:16:47] wire _r1_c_cat_T_37; // @[package.scala:16:47] assign _r1_c_cat_T_37 = _GEN_8; // @[package.scala:16:47] wire _needs_second_acq_T_41; // @[package.scala:16:47] assign _needs_second_acq_T_41 = _GEN_8; // @[package.scala:16:47] wire _GEN_9 = req_cmd == 5'hE; // @[MSHR.scala:38:16] wire _grow_param_r_c_cat_T_15; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_15 = _GEN_9; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_38; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_38 = _GEN_9; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_15; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_15 = _GEN_9; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_38; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_38 = _GEN_9; // @[package.scala:16:47] wire _r1_c_cat_T_15; // @[package.scala:16:47] assign _r1_c_cat_T_15 = _GEN_9; // @[package.scala:16:47] wire _r1_c_cat_T_38; // @[package.scala:16:47] assign _r1_c_cat_T_38 = _GEN_9; // @[package.scala:16:47] wire _needs_second_acq_T_42; // @[package.scala:16:47] assign _needs_second_acq_T_42 = _GEN_9; // @[package.scala:16:47] wire _GEN_10 = req_cmd == 5'hF; // @[MSHR.scala:38:16] wire _grow_param_r_c_cat_T_16; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_16 = _GEN_10; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_39; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_39 = _GEN_10; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_16; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_16 = _GEN_10; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_39; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_39 = _GEN_10; // @[package.scala:16:47] wire _r1_c_cat_T_16; // @[package.scala:16:47] assign _r1_c_cat_T_16 = _GEN_10; // @[package.scala:16:47] wire _r1_c_cat_T_39; // @[package.scala:16:47] assign _r1_c_cat_T_39 = _GEN_10; // @[package.scala:16:47] wire _needs_second_acq_T_43; // @[package.scala:16:47] assign _needs_second_acq_T_43 = _GEN_10; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_17 = _grow_param_r_c_cat_T_12 \| _grow_param_r_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_18 = _grow_param_r_c_cat_T_17 \| _grow_param_r_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_19 = _grow_param_r_c_cat_T_18 \| _grow_param_r_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_20 = _grow_param_r_c_cat_T_19 \| _grow_param_r_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_21 = _grow_param_r_c_cat_T_11 \| _grow_param_r_c_cat_T_20; // @[package.scala:81:59] wire _grow_param_r_c_cat_T_22 = _grow_param_r_c_cat_T_4 \| _grow_param_r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _grow_param_r_c_cat_T_25 = _grow_param_r_c_cat_T_23 \| _grow_param_r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _grow_param_r_c_cat_T_27 = _grow_param_r_c_cat_T_25 \| _grow_param_r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _grow_param_r_c_cat_T_32 = _grow_param_r_c_cat_T_28 \| _grow_param_r_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_33 = _grow_param_r_c_cat_T_32 \| _grow_param_r_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_34 = _grow_param_r_c_cat_T_33 \| _grow_param_r_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_40 = _grow_param_r_c_cat_T_35 \| _grow_param_r_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_41 = _grow_param_r_c_cat_T_40 \| _grow_param_r_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_42 = _grow_param_r_c_cat_T_41 \| _grow_param_r_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_43 = _grow_param_r_c_cat_T_42 \| _grow_param_r_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_44 = _grow_param_r_c_cat_T_34 \| _grow_param_r_c_cat_T_43; // @[package.scala:81:59] wire _grow_param_r_c_cat_T_45 = _grow_param_r_c_cat_T_27 \| _grow_param_r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _GEN_11 = req_cmd == 5'h3; // @[MSHR.scala:38:16] wire _grow_param_r_c_cat_T_46; // @[Consts.scala:91:54] assign _grow_param_r_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54] wire _coh_on_grant_c_cat_T_46; // @[Consts.scala:91:54] assign _coh_on_grant_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54] wire _r1_c_cat_T_46; // @[Consts.scala:91:54] assign _r1_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54] wire _needs_second_acq_T_50; // @[Consts.scala:91:54] assign _needs_second_acq_T_50 = _GEN_11; // @[Consts.scala:91:54] wire _grow_param_r_c_cat_T_47 = _grow_param_r_c_cat_T_45 \| _grow_param_r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _GEN_12 = req_cmd == 5'h6; // @[MSHR.scala:38:16] wire _grow_param_r_c_cat_T_48; // @[Consts.scala:91:71] assign _grow_param_r_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71] wire _coh_on_grant_c_cat_T_48; // @[Consts.scala:91:71] assign _coh_on_grant_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71] wire _r1_c_cat_T_48; // @[Consts.scala:91:71] assign _r1_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71] wire _needs_second_acq_T_52; // @[Consts.scala:91:71] assign _needs_second_acq_T_52 = _GEN_12; // @[Consts.scala:91:71] wire _grow_param_r_c_cat_T_49 = _grow_param_r_c_cat_T_47 \| _grow_param_r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] grow_param_r_c = {_grow_param_r_c_cat_T_22, _grow_param_r_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _grow_param_r_T = {grow_param_r_c, new_coh_state}; // @[MSHR.scala:45:24] wire _grow_param_r_T_25 = _grow_param_r_T == 4'hC; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_27 = {1'h0, _grow_param_r_T_25}; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_28 = _grow_param_r_T == 4'hD; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_30 = _grow_param_r_T_28 ? 2'h2 : _grow_param_r_T_27; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_31 = _grow_param_r_T == 4'h4; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_33 = _grow_param_r_T_31 ? 2'h1 : _grow_param_r_T_30; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_34 = _grow_param_r_T == 4'h5; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_36 = _grow_param_r_T_34 ? 2'h2 : _grow_param_r_T_33; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_37 = _grow_param_r_T == 4'h0; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_39 = _grow_param_r_T_37 ? 2'h0 : _grow_param_r_T_36; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_40 = _grow_param_r_T == 4'hE; // @[Misc.scala:49:20] wire _grow_param_r_T_41 = _grow_param_r_T_40; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_42 = _grow_param_r_T_40 ? 2'h3 : _grow_param_r_T_39; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_43 = &_grow_param_r_T; // @[Misc.scala:49:20] wire _grow_param_r_T_44 = _grow_param_r_T_43 \| _grow_param_r_T_41; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_45 = _grow_param_r_T_43 ? 2'h3 : _grow_param_r_T_42; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_46 = _grow_param_r_T == 4'h6; // @[Misc.scala:49:20] wire _grow_param_r_T_47 = _grow_param_r_T_46 \| _grow_param_r_T_44; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_48 = _grow_param_r_T_46 ? 2'h2 : _grow_param_r_T_45; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_49 = _grow_param_r_T == 4'h7; // @[Misc.scala:49:20] wire _grow_param_r_T_50 = _grow_param_r_T_49 \| _grow_param_r_T_47; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_51 = _grow_param_r_T_49 ? 2'h3 : _grow_param_r_T_48; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_52 = _grow_param_r_T == 4'h1; // @[Misc.scala:49:20] wire _grow_param_r_T_53 = _grow_param_r_T_52 \| _grow_param_r_T_50; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_54 = _grow_param_r_T_52 ? 2'h1 : _grow_param_r_T_51; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_55 = _grow_param_r_T == 4'h2; // @[Misc.scala:49:20] wire _grow_param_r_T_56 = _grow_param_r_T_55 \| _grow_param_r_T_53; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_57 = _grow_param_r_T_55 ? 2'h2 : _grow_param_r_T_54; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_58 = _grow_param_r_T == 4'h3; // @[Misc.scala:49:20] wire grow_param_r_1 = _grow_param_r_T_58 \| _grow_param_r_T_56; // @[Misc.scala:35:9, :49:20] wire [1:0] grow_param = _grow_param_r_T_58 ? 2'h3 : _grow_param_r_T_57; // @[Misc.scala:35:36, :49:20] wire [1:0] grow_param_meta_state = grow_param; // @[Misc.scala:35:36] wire _coh_on_grant_c_cat_T_2 = _coh_on_grant_c_cat_T \| _coh_on_grant_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _coh_on_grant_c_cat_T_4 = _coh_on_grant_c_cat_T_2 \| _coh_on_grant_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _coh_on_grant_c_cat_T_9 = _coh_on_grant_c_cat_T_5 \| _coh_on_grant_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_10 = _coh_on_grant_c_cat_T_9 \| _coh_on_grant_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_11 = _coh_on_grant_c_cat_T_10 \| _coh_on_grant_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_17 = _coh_on_grant_c_cat_T_12 \| _coh_on_grant_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_18 = _coh_on_grant_c_cat_T_17 \| _coh_on_grant_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_19 = _coh_on_grant_c_cat_T_18 \| _coh_on_grant_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_20 = _coh_on_grant_c_cat_T_19 \| _coh_on_grant_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_21 = _coh_on_grant_c_cat_T_11 \| _coh_on_grant_c_cat_T_20; // @[package.scala:81:59] wire _coh_on_grant_c_cat_T_22 = _coh_on_grant_c_cat_T_4 \| _coh_on_grant_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _coh_on_grant_c_cat_T_25 = _coh_on_grant_c_cat_T_23 \| _coh_on_grant_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _coh_on_grant_c_cat_T_27 = _coh_on_grant_c_cat_T_25 \| _coh_on_grant_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _coh_on_grant_c_cat_T_32 = _coh_on_grant_c_cat_T_28 \| _coh_on_grant_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_33 = _coh_on_grant_c_cat_T_32 \| _coh_on_grant_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_34 = _coh_on_grant_c_cat_T_33 \| _coh_on_grant_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_40 = _coh_on_grant_c_cat_T_35 \| _coh_on_grant_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_41 = _coh_on_grant_c_cat_T_40 \| _coh_on_grant_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_42 = _coh_on_grant_c_cat_T_41 \| _coh_on_grant_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_43 = _coh_on_grant_c_cat_T_42 \| _coh_on_grant_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_44 = _coh_on_grant_c_cat_T_34 \| _coh_on_grant_c_cat_T_43; // @[package.scala:81:59] wire _coh_on_grant_c_cat_T_45 = _coh_on_grant_c_cat_T_27 \| _coh_on_grant_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _coh_on_grant_c_cat_T_47 = _coh_on_grant_c_cat_T_45 \| _coh_on_grant_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _coh_on_grant_c_cat_T_49 = _coh_on_grant_c_cat_T_47 \| _coh_on_grant_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] coh_on_grant_c = {_coh_on_grant_c_cat_T_22, _coh_on_grant_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _coh_on_grant_T = {coh_on_grant_c, io_mem_grant_bits_param_0}; // @[MSHR.scala:12:7] wire _coh_on_grant_T_9 = _coh_on_grant_T == 4'h1; // @[Metadata.scala:84:{18,38}] wire [1:0] _coh_on_grant_T_10 = {1'h0, _coh_on_grant_T_9}; // @[Metadata.scala:84:38] wire _coh_on_grant_T_11 = _coh_on_grant_T == 4'h0; // @[Metadata.scala:84:{18,38}] wire [1:0] _coh_on_grant_T_12 = _coh_on_grant_T_11 ? 2'h2 : _coh_on_grant_T_10; // @[Metadata.scala:84:38] wire _coh_on_grant_T_13 = _coh_on_grant_T == 4'h4; // @[Metadata.scala:84:{18,38}] wire [1:0] _coh_on_grant_T_14 = _coh_on_grant_T_13 ? 2'h2 : _coh_on_grant_T_12; // @[Metadata.scala:84:38] wire _coh_on_grant_T_15 = _coh_on_grant_T == 4'hC; // @[Metadata.scala:84:{18,38}] wire [1:0] _coh_on_grant_T_16 = _coh_on_grant_T_15 ? 2'h3 : _coh_on_grant_T_14; // @[Metadata.scala:84:38] wire [1:0] coh_on_grant_state = _coh_on_grant_T_16; // @[Metadata.scala:84:38, :160:20] wire _r1_c_cat_T_2 = _r1_c_cat_T \| _r1_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _r1_c_cat_T_4 = _r1_c_cat_T_2 \| _r1_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _r1_c_cat_T_9 = _r1_c_cat_T_5 \| _r1_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_10 = _r1_c_cat_T_9 \| _r1_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_11 = _r1_c_cat_T_10 \| _r1_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_17 = _r1_c_cat_T_12 \| _r1_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_18 = _r1_c_cat_T_17 \| _r1_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_19 = _r1_c_cat_T_18 \| _r1_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_20 = _r1_c_cat_T_19 \| _r1_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_21 = _r1_c_cat_T_11 \| _r1_c_cat_T_20; // @[package.scala:81:59] wire _r1_c_cat_T_22 = _r1_c_cat_T_4 \| _r1_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _r1_c_cat_T_25 = _r1_c_cat_T_23 \| _r1_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _r1_c_cat_T_27 = _r1_c_cat_T_25 \| _r1_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _r1_c_cat_T_32 = _r1_c_cat_T_28 \| _r1_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_33 = _r1_c_cat_T_32 \| _r1_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_34 = _r1_c_cat_T_33 \| _r1_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_40 = _r1_c_cat_T_35 \| _r1_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_41 = _r1_c_cat_T_40 \| _r1_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_42 = _r1_c_cat_T_41 \| _r1_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_43 = _r1_c_cat_T_42 \| _r1_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_44 = _r1_c_cat_T_34 \| _r1_c_cat_T_43; // @[package.scala:81:59] wire _r1_c_cat_T_45 = _r1_c_cat_T_27 \| _r1_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _r1_c_cat_T_47 = _r1_c_cat_T_45 \| _r1_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _r1_c_cat_T_49 = _r1_c_cat_T_47 \| _r1_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] r1_c = {_r1_c_cat_T_22, _r1_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _r1_T = {r1_c, new_coh_state}; // @[MSHR.scala:45:24] wire _r1_T_25 = _r1_T == 4'hC; // @[Misc.scala:49:20] wire [1:0] _r1_T_27 = {1'h0, _r1_T_25}; // @[Misc.scala:35:36, :49:20] wire _r1_T_28 = _r1_T == 4'hD; // @[Misc.scala:49:20] wire [1:0] _r1_T_30 = _r1_T_28 ? 2'h2 : _r1_T_27; // @[Misc.scala:35:36, :49:20] wire _r1_T_31 = _r1_T == 4'h4; // @[Misc.scala:49:20] wire [1:0] _r1_T_33 = _r1_T_31 ? 2'h1 : _r1_T_30; // @[Misc.scala:35:36, :49:20] wire _r1_T_34 = _r1_T == 4'h5; // @[Misc.scala:49:20] wire [1:0] _r1_T_36 = _r1_T_34 ? 2'h2 : _r1_T_33; // @[Misc.scala:35:36, :49:20] wire _r1_T_37 = _r1_T == 4'h0; // @[Misc.scala:49:20] wire [1:0] _r1_T_39 = _r1_T_37 ? 2'h0 : _r1_T_36; // @[Misc.scala:35:36, :49:20] wire _r1_T_40 = _r1_T == 4'hE; // @[Misc.scala:49:20] wire _r1_T_41 = _r1_T_40; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_42 = _r1_T_40 ? 2'h3 : _r1_T_39; // @[Misc.scala:35:36, :49:20] wire _r1_T_43 = &_r1_T; // @[Misc.scala:49:20] wire _r1_T_44 = _r1_T_43 \| _r1_T_41; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_45 = _r1_T_43 ? 2'h3 : _r1_T_42; // @[Misc.scala:35:36, :49:20] wire _r1_T_46 = _r1_T == 4'h6; // @[Misc.scala:49:20] wire _r1_T_47 = _r1_T_46 \| _r1_T_44; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_48 = _r1_T_46 ? 2'h2 : _r1_T_45; // @[Misc.scala:35:36, :49:20] wire _r1_T_49 = _r1_T == 4'h7; // @[Misc.scala:49:20] wire _r1_T_50 = _r1_T_49 \| _r1_T_47; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_51 = _r1_T_49 ? 2'h3 : _r1_T_48; // @[Misc.scala:35:36, :49:20] wire _r1_T_52 = _r1_T == 4'h1; // @[Misc.scala:49:20] wire _r1_T_53 = _r1_T_52 \| _r1_T_50; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_54 = _r1_T_52 ? 2'h1 : _r1_T_51; // @[Misc.scala:35:36, :49:20] wire _r1_T_55 = _r1_T == 4'h2; // @[Misc.scala:49:20] wire _r1_T_56 = _r1_T_55 \| _r1_T_53; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_57 = _r1_T_55 ? 2'h2 : _r1_T_54; // @[Misc.scala:35:36, :49:20] wire _r1_T_58 = _r1_T == 4'h3; // @[Misc.scala:49:20] wire r1_1 = _r1_T_58 \| _r1_T_56; // @[Misc.scala:35:9, :49:20] wire [1:0] r1_2 = _r1_T_58 ? 2'h3 : _r1_T_57; // @[Misc.scala:35:36, :49:20] wire _GEN_13 = io_req_bits_cmd_0 == 5'h1; // @[MSHR.scala:12:7] wire _r2_c_cat_T; // @[Consts.scala:90:32] assign _r2_c_cat_T = _GEN_13; // @[Consts.scala:90:32] wire _r2_c_cat_T_23; // @[Consts.scala:90:32] assign _r2_c_cat_T_23 = _GEN_13; // @[Consts.scala:90:32] wire _needs_second_acq_T; // @[Consts.scala:90:32] assign _needs_second_acq_T = _GEN_13; // @[Consts.scala:90:32] wire _dirties_cat_T; // @[Consts.scala:90:32] assign _dirties_cat_T = _GEN_13; // @[Consts.scala:90:32] wire _dirties_cat_T_23; // @[Consts.scala:90:32] assign _dirties_cat_T_23 = _GEN_13; // @[Consts.scala:90:32] wire _r_c_cat_T; // @[Consts.scala:90:32] assign _r_c_cat_T = _GEN_13; // @[Consts.scala:90:32] wire _r_c_cat_T_23; // @[Consts.scala:90:32] assign _r_c_cat_T_23 = _GEN_13; // @[Consts.scala:90:32] wire _GEN_14 = io_req_bits_cmd_0 == 5'h11; // @[MSHR.scala:12:7] wire _r2_c_cat_T_1; // @[Consts.scala:90:49] assign _r2_c_cat_T_1 = _GEN_14; // @[Consts.scala:90:49] wire _r2_c_cat_T_24; // @[Consts.scala:90:49] assign _r2_c_cat_T_24 = _GEN_14; // @[Consts.scala:90:49] wire _needs_second_acq_T_1; // @[Consts.scala:90:49] assign _needs_second_acq_T_1 = _GEN_14; // @[Consts.scala:90:49] wire _dirties_cat_T_1; // @[Consts.scala:90:49] assign _dirties_cat_T_1 = _GEN_14; // @[Consts.scala:90:49] wire _dirties_cat_T_24; // @[Consts.scala:90:49] assign _dirties_cat_T_24 = _GEN_14; // @[Consts.scala:90:49] wire _r_c_cat_T_1; // @[Consts.scala:90:49] assign _r_c_cat_T_1 = _GEN_14; // @[Consts.scala:90:49] wire _r_c_cat_T_24; // @[Consts.scala:90:49] assign _r_c_cat_T_24 = _GEN_14; // @[Consts.scala:90:49] wire _r2_c_cat_T_2 = _r2_c_cat_T \| _r2_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _GEN_15 = io_req_bits_cmd_0 == 5'h7; // @[MSHR.scala:12:7] wire _r2_c_cat_T_3; // @[Consts.scala:90:66] assign _r2_c_cat_T_3 = _GEN_15; // @[Consts.scala:90:66] wire _r2_c_cat_T_26; // @[Consts.scala:90:66] assign _r2_c_cat_T_26 = _GEN_15; // @[Consts.scala:90:66] wire _needs_second_acq_T_3; // @[Consts.scala:90:66] assign _needs_second_acq_T_3 = _GEN_15; // @[Consts.scala:90:66] wire _dirties_cat_T_3; // @[Consts.scala:90:66] assign _dirties_cat_T_3 = _GEN_15; // @[Consts.scala:90:66] wire _dirties_cat_T_26; // @[Consts.scala:90:66] assign _dirties_cat_T_26 = _GEN_15; // @[Consts.scala:90:66] wire _r_c_cat_T_3; // @[Consts.scala:90:66] assign _r_c_cat_T_3 = _GEN_15; // @[Consts.scala:90:66] wire _r_c_cat_T_26; // @[Consts.scala:90:66] assign _r_c_cat_T_26 = _GEN_15; // @[Consts.scala:90:66] wire _r2_c_cat_T_4 = _r2_c_cat_T_2 \| _r2_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _GEN_16 = io_req_bits_cmd_0 == 5'h4; // @[MSHR.scala:12:7] wire _r2_c_cat_T_5; // @[package.scala:16:47] assign _r2_c_cat_T_5 = _GEN_16; // @[package.scala:16:47] wire _r2_c_cat_T_28; // @[package.scala:16:47] assign _r2_c_cat_T_28 = _GEN_16; // @[package.scala:16:47] wire _needs_second_acq_T_5; // @[package.scala:16:47] assign _needs_second_acq_T_5 = _GEN_16; // @[package.scala:16:47] wire _dirties_cat_T_5; // @[package.scala:16:47] assign _dirties_cat_T_5 = _GEN_16; // @[package.scala:16:47] wire _dirties_cat_T_28; // @[package.scala:16:47] assign _dirties_cat_T_28 = _GEN_16; // @[package.scala:16:47] wire _r_c_cat_T_5; // @[package.scala:16:47] assign _r_c_cat_T_5 = _GEN_16; // @[package.scala:16:47] wire _r_c_cat_T_28; // @[package.scala:16:47] assign _r_c_cat_T_28 = _GEN_16; // @[package.scala:16:47] wire _GEN_17 = io_req_bits_cmd_0 == 5'h9; // @[MSHR.scala:12:7] wire _r2_c_cat_T_6; // @[package.scala:16:47] assign _r2_c_cat_T_6 = _GEN_17; // @[package.scala:16:47] wire _r2_c_cat_T_29; // @[package.scala:16:47] assign _r2_c_cat_T_29 = _GEN_17; // @[package.scala:16:47] wire _needs_second_acq_T_6; // @[package.scala:16:47] assign _needs_second_acq_T_6 = _GEN_17; // @[package.scala:16:47] wire _dirties_cat_T_6; // @[package.scala:16:47] assign _dirties_cat_T_6 = _GEN_17; // @[package.scala:16:47] wire _dirties_cat_T_29; // @[package.scala:16:47] assign _dirties_cat_T_29 = _GEN_17; // @[package.scala:16:47] wire _r_c_cat_T_6; // @[package.scala:16:47] assign _r_c_cat_T_6 = _GEN_17; // @[package.scala:16:47] wire _r_c_cat_T_29; // @[package.scala:16:47] assign _r_c_cat_T_29 = _GEN_17; // @[package.scala:16:47] wire _GEN_18 = io_req_bits_cmd_0 == 5'hA; // @[MSHR.scala:12:7] wire _r2_c_cat_T_7; // @[package.scala:16:47] assign _r2_c_cat_T_7 = _GEN_18; // @[package.scala:16:47] wire _r2_c_cat_T_30; // @[package.scala:16:47] assign _r2_c_cat_T_30 = _GEN_18; // @[package.scala:16:47] wire _needs_second_acq_T_7; // @[package.scala:16:47] assign _needs_second_acq_T_7 = _GEN_18; // @[package.scala:16:47] wire _dirties_cat_T_7; // @[package.scala:16:47] assign _dirties_cat_T_7 = _GEN_18; // @[package.scala:16:47] wire _dirties_cat_T_30; // @[package.scala:16:47] assign _dirties_cat_T_30 = _GEN_18; // @[package.scala:16:47] wire _r_c_cat_T_7; // @[package.scala:16:47] assign _r_c_cat_T_7 = _GEN_18; // @[package.scala:16:47] wire _r_c_cat_T_30; // @[package.scala:16:47] assign _r_c_cat_T_30 = _GEN_18; // @[package.scala:16:47] wire _GEN_19 = io_req_bits_cmd_0 == 5'hB; // @[MSHR.scala:12:7] wire _r2_c_cat_T_8; // @[package.scala:16:47] assign _r2_c_cat_T_8 = _GEN_19; // @[package.scala:16:47] wire _r2_c_cat_T_31; // @[package.scala:16:47] assign _r2_c_cat_T_31 = _GEN_19; // @[package.scala:16:47] wire _needs_second_acq_T_8; // @[package.scala:16:47] assign _needs_second_acq_T_8 = _GEN_19; // @[package.scala:16:47] wire _dirties_cat_T_8; // @[package.scala:16:47] assign _dirties_cat_T_8 = _GEN_19; // @[package.scala:16:47] wire _dirties_cat_T_31; // @[package.scala:16:47] assign _dirties_cat_T_31 = _GEN_19; // @[package.scala:16:47] wire _r_c_cat_T_8; // @[package.scala:16:47] assign _r_c_cat_T_8 = _GEN_19; // @[package.scala:16:47] wire _r_c_cat_T_31; // @[package.scala:16:47] assign _r_c_cat_T_31 = _GEN_19; // @[package.scala:16:47] wire _r2_c_cat_T_9 = _r2_c_cat_T_5 \| _r2_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_10 = _r2_c_cat_T_9 \| _r2_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_11 = _r2_c_cat_T_10 \| _r2_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _GEN_20 = io_req_bits_cmd_0 == 5'h8; // @[MSHR.scala:12:7] wire _r2_c_cat_T_12; // @[package.scala:16:47] assign _r2_c_cat_T_12 = _GEN_20; // @[package.scala:16:47] wire _r2_c_cat_T_35; // @[package.scala:16:47] assign _r2_c_cat_T_35 = _GEN_20; // @[package.scala:16:47] wire _needs_second_acq_T_12; // @[package.scala:16:47] assign _needs_second_acq_T_12 = _GEN_20; // @[package.scala:16:47] wire _dirties_cat_T_12; // @[package.scala:16:47] assign _dirties_cat_T_12 = _GEN_20; // @[package.scala:16:47] wire _dirties_cat_T_35; // @[package.scala:16:47] assign _dirties_cat_T_35 = _GEN_20; // @[package.scala:16:47] wire _r_c_cat_T_12; // @[package.scala:16:47] assign _r_c_cat_T_12 = _GEN_20; // @[package.scala:16:47] wire _r_c_cat_T_35; // @[package.scala:16:47] assign _r_c_cat_T_35 = _GEN_20; // @[package.scala:16:47] wire _GEN_21 = io_req_bits_cmd_0 == 5'hC; // @[MSHR.scala:12:7] wire _r2_c_cat_T_13; // @[package.scala:16:47] assign _r2_c_cat_T_13 = _GEN_21; // @[package.scala:16:47] wire _r2_c_cat_T_36; // @[package.scala:16:47] assign _r2_c_cat_T_36 = _GEN_21; // @[package.scala:16:47] wire _needs_second_acq_T_13; // @[package.scala:16:47] assign _needs_second_acq_T_13 = _GEN_21; // @[package.scala:16:47] wire _dirties_cat_T_13; // @[package.scala:16:47] assign _dirties_cat_T_13 = _GEN_21; // @[package.scala:16:47] wire _dirties_cat_T_36; // @[package.scala:16:47] assign _dirties_cat_T_36 = _GEN_21; // @[package.scala:16:47] wire _r_c_cat_T_13; // @[package.scala:16:47] assign _r_c_cat_T_13 = _GEN_21; // @[package.scala:16:47] wire _r_c_cat_T_36; // @[package.scala:16:47] assign _r_c_cat_T_36 = _GEN_21; // @[package.scala:16:47] wire _GEN_22 = io_req_bits_cmd_0 == 5'hD; // @[MSHR.scala:12:7] wire _r2_c_cat_T_14; // @[package.scala:16:47] assign _r2_c_cat_T_14 = _GEN_22; // @[package.scala:16:47] wire _r2_c_cat_T_37; // @[package.scala:16:47] assign _r2_c_cat_T_37 = _GEN_22; // @[package.scala:16:47] wire _needs_second_acq_T_14; // @[package.scala:16:47] assign _needs_second_acq_T_14 = _GEN_22; // @[package.scala:16:47] wire _dirties_cat_T_14; // @[package.scala:16:47] assign _dirties_cat_T_14 = _GEN_22; // @[package.scala:16:47] wire _dirties_cat_T_37; // @[package.scala:16:47] assign _dirties_cat_T_37 = _GEN_22; // @[package.scala:16:47] wire _r_c_cat_T_14; // @[package.scala:16:47] assign _r_c_cat_T_14 = _GEN_22; // @[package.scala:16:47] wire _r_c_cat_T_37; // @[package.scala:16:47] assign _r_c_cat_T_37 = _GEN_22; // @[package.scala:16:47] wire _GEN_23 = io_req_bits_cmd_0 == 5'hE; // @[MSHR.scala:12:7] wire _r2_c_cat_T_15; // @[package.scala:16:47] assign _r2_c_cat_T_15 = _GEN_23; // @[package.scala:16:47] wire _r2_c_cat_T_38; // @[package.scala:16:47] assign _r2_c_cat_T_38 = _GEN_23; // @[package.scala:16:47] wire _needs_second_acq_T_15; // @[package.scala:16:47] assign _needs_second_acq_T_15 = _GEN_23; // @[package.scala:16:47] wire _dirties_cat_T_15; // @[package.scala:16:47] assign _dirties_cat_T_15 = _GEN_23; // @[package.scala:16:47] wire _dirties_cat_T_38; // @[package.scala:16:47] assign _dirties_cat_T_38 = _GEN_23; // @[package.scala:16:47] wire _r_c_cat_T_15; // @[package.scala:16:47] assign _r_c_cat_T_15 = _GEN_23; // @[package.scala:16:47] wire _r_c_cat_T_38; // @[package.scala:16:47] assign _r_c_cat_T_38 = _GEN_23; // @[package.scala:16:47] wire _GEN_24 = io_req_bits_cmd_0 == 5'hF; // @[MSHR.scala:12:7] wire _r2_c_cat_T_16; // @[package.scala:16:47] assign _r2_c_cat_T_16 = _GEN_24; // @[package.scala:16:47] wire _r2_c_cat_T_39; // @[package.scala:16:47] assign _r2_c_cat_T_39 = _GEN_24; // @[package.scala:16:47] wire _needs_second_acq_T_16; // @[package.scala:16:47] assign _needs_second_acq_T_16 = _GEN_24; // @[package.scala:16:47] wire _dirties_cat_T_16; // @[package.scala:16:47] assign _dirties_cat_T_16 = _GEN_24; // @[package.scala:16:47] wire _dirties_cat_T_39; // @[package.scala:16:47] assign _dirties_cat_T_39 = _GEN_24; // @[package.scala:16:47] wire _r_c_cat_T_16; // @[package.scala:16:47] assign _r_c_cat_T_16 = _GEN_24; // @[package.scala:16:47] wire _r_c_cat_T_39; // @[package.scala:16:47] assign _r_c_cat_T_39 = _GEN_24; // @[package.scala:16:47] wire _r2_c_cat_T_17 = _r2_c_cat_T_12 \| _r2_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_18 = _r2_c_cat_T_17 \| _r2_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_19 = _r2_c_cat_T_18 \| _r2_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_20 = _r2_c_cat_T_19 \| _r2_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_21 = _r2_c_cat_T_11 \| _r2_c_cat_T_20; // @[package.scala:81:59] wire _r2_c_cat_T_22 = _r2_c_cat_T_4 \| _r2_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _r2_c_cat_T_25 = _r2_c_cat_T_23 \| _r2_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _r2_c_cat_T_27 = _r2_c_cat_T_25 \| _r2_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _r2_c_cat_T_32 = _r2_c_cat_T_28 \| _r2_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_33 = _r2_c_cat_T_32 \| _r2_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_34 = _r2_c_cat_T_33 \| _r2_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_40 = _r2_c_cat_T_35 \| _r2_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_41 = _r2_c_cat_T_40 \| _r2_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_42 = _r2_c_cat_T_41 \| _r2_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_43 = _r2_c_cat_T_42 \| _r2_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_44 = _r2_c_cat_T_34 \| _r2_c_cat_T_43; // @[package.scala:81:59] wire _r2_c_cat_T_45 = _r2_c_cat_T_27 \| _r2_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _GEN_25 = io_req_bits_cmd_0 == 5'h3; // @[MSHR.scala:12:7] wire _r2_c_cat_T_46; // @[Consts.scala:91:54] assign _r2_c_cat_T_46 = _GEN_25; // @[Consts.scala:91:54] wire _needs_second_acq_T_23; // @[Consts.scala:91:54] assign _needs_second_acq_T_23 = _GEN_25; // @[Consts.scala:91:54] wire _dirties_cat_T_46; // @[Consts.scala:91:54] assign _dirties_cat_T_46 = _GEN_25; // @[Consts.scala:91:54] wire _rpq_io_enq_valid_T_4; // @[Consts.scala:88:52] assign _rpq_io_enq_valid_T_4 = _GEN_25; // @[Consts.scala:88:52, :91:54] wire _r_c_cat_T_46; // @[Consts.scala:91:54] assign _r_c_cat_T_46 = _GEN_25; // @[Consts.scala:91:54] wire _r2_c_cat_T_47 = _r2_c_cat_T_45 \| _r2_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _GEN_26 = io_req_bits_cmd_0 == 5'h6; // @[MSHR.scala:12:7] wire _r2_c_cat_T_48; // @[Consts.scala:91:71] assign _r2_c_cat_T_48 = _GEN_26; // @[Consts.scala:91:71] wire _needs_second_acq_T_25; // @[Consts.scala:91:71] assign _needs_second_acq_T_25 = _GEN_26; // @[Consts.scala:91:71] wire _dirties_cat_T_48; // @[Consts.scala:91:71] assign _dirties_cat_T_48 = _GEN_26; // @[Consts.scala:91:71] wire _r_c_cat_T_48; // @[Consts.scala:91:71] assign _r_c_cat_T_48 = _GEN_26; // @[Consts.scala:91:71] wire _r2_c_cat_T_49 = _r2_c_cat_T_47 \| _r2_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] r2_c = {_r2_c_cat_T_22, _r2_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _r2_T = {r2_c, new_coh_state}; // @[MSHR.scala:45:24] wire _r2_T_25 = _r2_T == 4'hC; // @[Misc.scala:49:20] wire [1:0] _r2_T_27 = {1'h0, _r2_T_25}; // @[Misc.scala:35:36, :49:20] wire _r2_T_28 = _r2_T == 4'hD; // @[Misc.scala:49:20] wire [1:0] _r2_T_30 = _r2_T_28 ? 2'h2 : _r2_T_27; // @[Misc.scala:35:36, :49:20] wire _r2_T_31 = _r2_T == 4'h4; // @[Misc.scala:49:20] wire [1:0] _r2_T_33 = _r2_T_31 ? 2'h1 : _r2_T_30; // @[Misc.scala:35:36, :49:20] wire _r2_T_34 = _r2_T == 4'h5; // @[Misc.scala:49:20] wire [1:0] _r2_T_36 = _r2_T_34 ? 2'h2 : _r2_T_33; // @[Misc.scala:35:36, :49:20] wire _r2_T_37 = _r2_T == 4'h0; // @[Misc.scala:49:20] wire [1:0] _r2_T_39 = _r2_T_37 ? 2'h0 : _r2_T_36; // @[Misc.scala:35:36, :49:20] wire _r2_T_40 = _r2_T == 4'hE; // @[Misc.scala:49:20] wire _r2_T_41 = _r2_T_40; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_42 = _r2_T_40 ? 2'h3 : _r2_T_39; // @[Misc.scala:35:36, :49:20] wire _r2_T_43 = &_r2_T; // @[Misc.scala:49:20] wire _r2_T_44 = _r2_T_43 \| _r2_T_41; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_45 = _r2_T_43 ? 2'h3 : _r2_T_42; // @[Misc.scala:35:36, :49:20] wire _r2_T_46 = _r2_T == 4'h6; // @[Misc.scala:49:20] wire _r2_T_47 = _r2_T_46 \| _r2_T_44; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_48 = _r2_T_46 ? 2'h2 : _r2_T_45; // @[Misc.scala:35:36, :49:20] wire _r2_T_49 = _r2_T == 4'h7; // @[Misc.scala:49:20] wire _r2_T_50 = _r2_T_49 \| _r2_T_47; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_51 = _r2_T_49 ? 2'h3 : _r2_T_48; // @[Misc.scala:35:36, :49:20] wire _r2_T_52 = _r2_T == 4'h1; // @[Misc.scala:49:20] wire _r2_T_53 = _r2_T_52 \| _r2_T_50; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_54 = _r2_T_52 ? 2'h1 : _r2_T_51; // @[Misc.scala:35:36, :49:20] wire _r2_T_55 = _r2_T == 4'h2; // @[Misc.scala:49:20] wire _r2_T_56 = _r2_T_55 \| _r2_T_53; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_57 = _r2_T_55 ? 2'h2 : _r2_T_54; // @[Misc.scala:35:36, :49:20] wire _r2_T_58 = _r2_T == 4'h3; // @[Misc.scala:49:20] wire r2_1 = _r2_T_58 \| _r2_T_56; // @[Misc.scala:35:9, :49:20] wire [1:0] r2_2 = _r2_T_58 ? 2'h3 : _r2_T_57; // @[Misc.scala:35:36, :49:20] wire _needs_second_acq_T_2 = _needs_second_acq_T \| _needs_second_acq_T_1; // @[Consts.scala:90:{32,42,49}] wire _needs_second_acq_T_4 = _needs_second_acq_T_2 \| _needs_second_acq_T_3; // @[Consts.scala:90:{42,59,66}] wire _needs_second_acq_T_9 = _needs_second_acq_T_5 \| _needs_second_acq_T_6; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_10 = _needs_second_acq_T_9 \| _needs_second_acq_T_7; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_11 = _needs_second_acq_T_10 \| _needs_second_acq_T_8; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_17 = _needs_second_acq_T_12 \| _needs_second_acq_T_13; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_18 = _needs_second_acq_T_17 \| _needs_second_acq_T_14; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_19 = _needs_second_acq_T_18 \| _needs_second_acq_T_15; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_20 = _needs_second_acq_T_19 \| _needs_second_acq_T_16; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_21 = _needs_second_acq_T_11 \| _needs_second_acq_T_20; // @[package.scala:81:59] wire _needs_second_acq_T_22 = _needs_second_acq_T_4 \| _needs_second_acq_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _needs_second_acq_T_24 = _needs_second_acq_T_22 \| _needs_second_acq_T_23; // @[Consts.scala:90:76, :91:{47,54}] wire _needs_second_acq_T_26 = _needs_second_acq_T_24 \| _needs_second_acq_T_25; // @[Consts.scala:91:{47,64,71}] wire _needs_second_acq_T_29 = _needs_second_acq_T_27 \| _needs_second_acq_T_28; // @[Consts.scala:90:{32,42,49}] wire _needs_second_acq_T_31 = _needs_second_acq_T_29 \| _needs_second_acq_T_30; // @[Consts.scala:90:{42,59,66}] wire _needs_second_acq_T_36 = _needs_second_acq_T_32 \| _needs_second_acq_T_33; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_37 = _needs_second_acq_T_36 \| _needs_second_acq_T_34; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_38 = _needs_second_acq_T_37 \| _needs_second_acq_T_35; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_44 = _needs_second_acq_T_39 \| _needs_second_acq_T_40; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_45 = _needs_second_acq_T_44 \| _needs_second_acq_T_41; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_46 = _needs_second_acq_T_45 \| _needs_second_acq_T_42; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_47 = _needs_second_acq_T_46 \| _needs_second_acq_T_43; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_48 = _needs_second_acq_T_38 \| _needs_second_acq_T_47; // @[package.scala:81:59] wire _needs_second_acq_T_49 = _needs_second_acq_T_31 \| _needs_second_acq_T_48; // @[Consts.scala:87:44, :90:{59,76}] wire _needs_second_acq_T_51 = _needs_second_acq_T_49 \| _needs_second_acq_T_50; // @[Consts.scala:90:76, :91:{47,54}] wire _needs_second_acq_T_53 = _needs_second_acq_T_51 \| _needs_second_acq_T_52; // @[Consts.scala:91:{47,64,71}] wire _needs_second_acq_T_54 = ~_needs_second_acq_T_53; // @[Metadata.scala:104:57] wire cmd_requires_second_acquire = _needs_second_acq_T_26 & _needs_second_acq_T_54; // @[Metadata.scala:104:{54,57}] wire is_hit_again = r1_1 & r2_1; // @[Misc.scala:35:9] wire _dirties_cat_T_2 = _dirties_cat_T \| _dirties_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _dirties_cat_T_4 = _dirties_cat_T_2 \| _dirties_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _dirties_cat_T_9 = _dirties_cat_T_5 \| _dirties_cat_T_6; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_10 = _dirties_cat_T_9 \| _dirties_cat_T_7; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_11 = _dirties_cat_T_10 \| _dirties_cat_T_8; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_17 = _dirties_cat_T_12 \| _dirties_cat_T_13; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_18 = _dirties_cat_T_17 \| _dirties_cat_T_14; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_19 = _dirties_cat_T_18 \| _dirties_cat_T_15; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_20 = _dirties_cat_T_19 \| _dirties_cat_T_16; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_21 = _dirties_cat_T_11 \| _dirties_cat_T_20; // @[package.scala:81:59] wire _dirties_cat_T_22 = _dirties_cat_T_4 \| _dirties_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _dirties_cat_T_25 = _dirties_cat_T_23 \| _dirties_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _dirties_cat_T_27 = _dirties_cat_T_25 \| _dirties_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _dirties_cat_T_32 = _dirties_cat_T_28 \| _dirties_cat_T_29; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_33 = _dirties_cat_T_32 \| _dirties_cat_T_30; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_34 = _dirties_cat_T_33 \| _dirties_cat_T_31; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_40 = _dirties_cat_T_35 \| _dirties_cat_T_36; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_41 = _dirties_cat_T_40 \| _dirties_cat_T_37; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_42 = _dirties_cat_T_41 \| _dirties_cat_T_38; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_43 = _dirties_cat_T_42 \| _dirties_cat_T_39; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_44 = _dirties_cat_T_34 \| _dirties_cat_T_43; // @[package.scala:81:59] wire _dirties_cat_T_45 = _dirties_cat_T_27 \| _dirties_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _dirties_cat_T_47 = _dirties_cat_T_45 \| _dirties_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _dirties_cat_T_49 = _dirties_cat_T_47 \| _dirties_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] dirties_cat = {_dirties_cat_T_22, _dirties_cat_T_49}; // @[Metadata.scala:29:18] wire dirties = &dirties_cat; // @[Metadata.scala:29:18, :106:42] wire [1:0] biggest_grow_param = dirties ? r2_2 : r1_2; // @[Misc.scala:35:36] wire [1:0] dirtier_coh_state = biggest_grow_param; // @[Metadata.scala:107:33, :160:20] wire [4:0] dirtier_cmd = dirties ? io_req_bits_cmd_0 : req_cmd; // @[MSHR.scala:12:7, :38:16] wire [26:0] _r_beats1_decode_T = 27'hFFF << io_mem_grant_bits_size_0; // @[MSHR.scala:12:7] wire [11:0] _r_beats1_decode_T_1 = _r_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _r_beats1_decode_T_2 = ~_r_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] r_beats1_decode = _r_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire r_beats1_opdata = io_mem_grant_bits_opcode_0[0]; // @[MSHR.scala:12:7] wire [8:0] r_beats1 = r_beats1_opdata ? r_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] r_counter; // @[Edges.scala:229:27] wire [9:0] _r_counter1_T = {1'h0, r_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] r_counter1 = _r_counter1_T[8:0]; // @[Edges.scala:230:28] wire r_1_1 = r_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _r_last_T = r_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _r_last_T_1 = r_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire r_2 = _r_last_T \| _r_last_T_1; // @[Edges.scala:232:{25,33,43}] wire refill_done = r_2 & io_mem_grant_valid_0; // @[MSHR.scala:12:7] wire [8:0] _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] r_4 = r_beats1 & _r_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _r_counter_T = r_1_1 ? r_beats1 : r_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] refill_address_inc = {r_4, 3'h0}; // @[Edges.scala:234:25, :269:29] wire _GEN_27 = state == 4'h1; // @[MSHR.scala:36:22] wire _sec_rdy_T; // @[package.scala:16:47] assign _sec_rdy_T = _GEN_27; // @[package.scala:16:47] wire _io_probe_rdy_T_3; // @[package.scala:16:47] assign _io_probe_rdy_T_3 = _GEN_27; // @[package.scala:16:47] assign _io_wb_req_valid_T = _GEN_27; // @[MSHR.scala:153:28] wire _T_11 = state == 4'h2; // @[MSHR.scala:36:22] wire _sec_rdy_T_1; // @[package.scala:16:47] assign _sec_rdy_T_1 = _T_11; // @[package.scala:16:47] wire _io_probe_rdy_T_4; // @[package.scala:16:47] assign _io_probe_rdy_T_4 = _T_11; // @[package.scala:16:47] wire _T_9 = state == 4'h3; // @[MSHR.scala:36:22] wire _sec_rdy_T_2; // @[package.scala:16:47] assign _sec_rdy_T_2 = _T_9; // @[package.scala:16:47] wire _io_probe_rdy_T_5; // @[package.scala:16:47] assign _io_probe_rdy_T_5 = _T_9; // @[package.scala:16:47] wire _io_meta_write_valid_T_1; // @[package.scala:16:47] assign _io_meta_write_valid_T_1 = _T_9; // @[package.scala:16:47] wire _io_meta_write_bits_data_coh_T; // @[MSHR.scala:149:44] assign _io_meta_write_bits_data_coh_T = _T_9; // @[MSHR.scala:149:44] wire _sec_rdy_T_3 = _sec_rdy_T \| _sec_rdy_T_1; // @[package.scala:16:47, :81:59] wire _sec_rdy_T_4 = _sec_rdy_T_3 \| _sec_rdy_T_2; // @[package.scala:16:47, :81:59] wire _GEN_28 = state == 4'h4; // @[MSHR.scala:36:22] wire _sec_rdy_T_5; // @[package.scala:16:47] assign _sec_rdy_T_5 = _GEN_28; // @[package.scala:16:47] wire _can_finish_T_1; // @[package.scala:16:47] assign _can_finish_T_1 = _GEN_28; // @[package.scala:16:47] wire _io_mem_acquire_valid_T; // @[MSHR.scala:161:33] assign _io_mem_acquire_valid_T = _GEN_28; // @[MSHR.scala:161:33] wire _sec_rdy_T_6 = state == 4'h5; // @[MSHR.scala:36:22] wire _sec_rdy_T_7 = _sec_rdy_T_5 \| _sec_rdy_T_6; // @[package.scala:16:47, :81:59] wire _sec_rdy_T_8 = ~cmd_requires_second_acquire; // @[MSHR.scala:61:23] wire _sec_rdy_T_9 = _sec_rdy_T_7 & _sec_rdy_T_8; // @[MSHR.scala:60:65, :61:23] wire _sec_rdy_T_10 = ~refill_done; // @[MSHR.scala:61:55] wire _sec_rdy_T_11 = _sec_rdy_T_9 & _sec_rdy_T_10; // @[MSHR.scala:60:65, :61:{52,55}] wire _sec_rdy_T_12 = _sec_rdy_T_4 \| _sec_rdy_T_11; // @[MSHR.scala:59:56, :61:52] wire sec_rdy = idx_match & _sec_rdy_T_12; // @[MSHR.scala:42:27, :58:27, :59:56] wire _rpq_io_enq_valid_T = io_req_pri_val_0 & io_req_pri_rdy_0; // @[MSHR.scala:12:7, :64:39] wire _rpq_io_enq_valid_T_1 = io_req_sec_val_0 & sec_rdy; // @[MSHR.scala:12:7, :58:27, :64:75] wire _rpq_io_enq_valid_T_2 = _rpq_io_enq_valid_T \| _rpq_io_enq_valid_T_1; // @[MSHR.scala:64:{39,57,75}] wire _rpq_io_enq_valid_T_3 = io_req_bits_cmd_0 == 5'h2; // @[MSHR.scala:12:7] wire _rpq_io_enq_valid_T_5 = _rpq_io_enq_valid_T_3 \| _rpq_io_enq_valid_T_4; // @[Consts.scala:88:{35,45,52}] wire _rpq_io_enq_valid_T_6 = ~_rpq_io_enq_valid_T_5; // @[MSHR.scala:64:90] wire _rpq_io_enq_valid_T_7 = _rpq_io_enq_valid_T_2 & _rpq_io_enq_valid_T_6; // @[MSHR.scala:64:{57,87,90}] wire _T_19 = state == 4'h8; // @[MSHR.scala:36:22, :66:49] wire _rpq_io_deq_ready_T; // @[MSHR.scala:66:49] assign _rpq_io_deq_ready_T = _T_19; // @[MSHR.scala:66:49] wire _io_replay_valid_T; // @[MSHR.scala:168:28] assign _io_replay_valid_T = _T_19; // @[MSHR.scala:66:49, :168:28] wire _rpq_io_deq_ready_T_4; // @[MSHR.scala:176:48] assign _rpq_io_deq_ready_T_4 = _T_19; // @[MSHR.scala:66:49, :176:48] wire _rpq_io_deq_ready_T_1 = io_replay_ready_0 & _rpq_io_deq_ready_T; // @[MSHR.scala:12:7, :66:{40,49}] wire _rpq_io_deq_ready_T_2 = ~(\|state); // @[MSHR.scala:36:22, :66:75] wire _rpq_io_deq_ready_T_3 = _rpq_io_deq_ready_T_1 \| _rpq_io_deq_ready_T_2; // @[MSHR.scala:66:{40,66,75}] reg acked; // @[MSHR.scala:68:18] wire _io_meta_write_valid_T = state == 4'h6; // @[MSHR.scala:36:22, :78:15] wire [3:0] _needs_wb_r_T_6 = {2'h2, io_req_bits_old_meta_coh_state_0}; // @[MSHR.scala:12:7] wire _needs_wb_r_T_19 = _needs_wb_r_T_6 == 4'h8; // @[Misc.scala:56:20] wire [2:0] _needs_wb_r_T_21 = _needs_wb_r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_23 = _needs_wb_r_T_6 == 4'h9; // @[Misc.scala:56:20] wire [2:0] _needs_wb_r_T_25 = _needs_wb_r_T_23 ? 3'h2 : _needs_wb_r_T_21; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_27 = _needs_wb_r_T_6 == 4'hA; // @[Misc.scala:56:20] wire [2:0] _needs_wb_r_T_29 = _needs_wb_r_T_27 ? 3'h1 : _needs_wb_r_T_25; // @[MSHR.scala:142:59] wire _needs_wb_r_T_31 = _needs_wb_r_T_6 == 4'hB; // @[Misc.scala:56:20] wire _needs_wb_r_T_32 = _needs_wb_r_T_31; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_33 = _needs_wb_r_T_31 ? 3'h1 : _needs_wb_r_T_29; // @[MSHR.scala:142:59] wire _needs_wb_r_T_35 = _needs_wb_r_T_6 == 4'h4; // @[Misc.scala:56:20] wire _needs_wb_r_T_36 = ~_needs_wb_r_T_35 & _needs_wb_r_T_32; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_37 = _needs_wb_r_T_35 ? 3'h5 : _needs_wb_r_T_33; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_39 = _needs_wb_r_T_6 == 4'h5; // @[Misc.scala:56:20] wire _needs_wb_r_T_40 = ~_needs_wb_r_T_39 & _needs_wb_r_T_36; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_41 = _needs_wb_r_T_39 ? 3'h4 : _needs_wb_r_T_37; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_42 = {1'h0, _needs_wb_r_T_39}; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_43 = _needs_wb_r_T_6 == 4'h6; // @[Misc.scala:56:20] wire _needs_wb_r_T_44 = ~_needs_wb_r_T_43 & _needs_wb_r_T_40; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_45 = _needs_wb_r_T_43 ? 3'h0 : _needs_wb_r_T_41; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_46 = _needs_wb_r_T_43 ? 2'h1 : _needs_wb_r_T_42; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_47 = _needs_wb_r_T_6 == 4'h7; // @[Misc.scala:56:20] wire _needs_wb_r_T_48 = _needs_wb_r_T_47 \| _needs_wb_r_T_44; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_49 = _needs_wb_r_T_47 ? 3'h0 : _needs_wb_r_T_45; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_50 = _needs_wb_r_T_47 ? 2'h1 : _needs_wb_r_T_46; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_51 = _needs_wb_r_T_6 == 4'h0; // @[Misc.scala:56:20] wire _needs_wb_r_T_52 = ~_needs_wb_r_T_51 & _needs_wb_r_T_48; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_53 = _needs_wb_r_T_51 ? 3'h5 : _needs_wb_r_T_49; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_54 = _needs_wb_r_T_51 ? 2'h0 : _needs_wb_r_T_50; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_55 = _needs_wb_r_T_6 == 4'h1; // @[Misc.scala:56:20] wire _needs_wb_r_T_56 = ~_needs_wb_r_T_55 & _needs_wb_r_T_52; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_57 = _needs_wb_r_T_55 ? 3'h4 : _needs_wb_r_T_53; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_58 = _needs_wb_r_T_55 ? 2'h1 : _needs_wb_r_T_54; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_59 = _needs_wb_r_T_6 == 4'h2; // @[Misc.scala:56:20] wire _needs_wb_r_T_60 = ~_needs_wb_r_T_59 & _needs_wb_r_T_56; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_61 = _needs_wb_r_T_59 ? 3'h3 : _needs_wb_r_T_57; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_62 = _needs_wb_r_T_59 ? 2'h2 : _needs_wb_r_T_58; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_63 = _needs_wb_r_T_6 == 4'h3; // @[Misc.scala:56:20] wire needs_wb = _needs_wb_r_T_63 \| _needs_wb_r_T_60; // @[Misc.scala:38:9, :56:20] wire [2:0] needs_wb_r_2 = _needs_wb_r_T_63 ? 3'h3 : _needs_wb_r_T_61; // @[Misc.scala:38:36, :56:20] wire [1:0] needs_wb_r_3 = _needs_wb_r_T_63 ? 2'h2 : _needs_wb_r_T_62; // @[Misc.scala:38:63, :56:20] wire [1:0] needs_wb_meta_state = needs_wb_r_3; // @[Misc.scala:38:63] wire _r_c_cat_T_2 = _r_c_cat_T \| _r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _r_c_cat_T_4 = _r_c_cat_T_2 \| _r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _r_c_cat_T_9 = _r_c_cat_T_5 \| _r_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_10 = _r_c_cat_T_9 \| _r_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_11 = _r_c_cat_T_10 \| _r_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_17 = _r_c_cat_T_12 \| _r_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_18 = _r_c_cat_T_17 \| _r_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_19 = _r_c_cat_T_18 \| _r_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_20 = _r_c_cat_T_19 \| _r_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_21 = _r_c_cat_T_11 \| _r_c_cat_T_20; // @[package.scala:81:59] wire _r_c_cat_T_22 = _r_c_cat_T_4 \| _r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _r_c_cat_T_25 = _r_c_cat_T_23 \| _r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _r_c_cat_T_27 = _r_c_cat_T_25 \| _r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _r_c_cat_T_32 = _r_c_cat_T_28 \| _r_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_33 = _r_c_cat_T_32 \| _r_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_34 = _r_c_cat_T_33 \| _r_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_40 = _r_c_cat_T_35 \| _r_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_41 = _r_c_cat_T_40 \| _r_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_42 = _r_c_cat_T_41 \| _r_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_43 = _r_c_cat_T_42 \| _r_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_44 = _r_c_cat_T_34 \| _r_c_cat_T_43; // @[package.scala:81:59] wire _r_c_cat_T_45 = _r_c_cat_T_27 \| _r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _r_c_cat_T_47 = _r_c_cat_T_45 \| _r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _r_c_cat_T_49 = _r_c_cat_T_47 \| _r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] r_c = {_r_c_cat_T_22, _r_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _r_T_64 = {r_c, io_req_bits_old_meta_coh_state_0}; // @[MSHR.scala:12:7] wire _r_T_89 = _r_T_64 == 4'hC; // @[Misc.scala:49:20] wire [1:0] _r_T_91 = {1'h0, _r_T_89}; // @[Misc.scala:35:36, :49:20] wire _r_T_92 = _r_T_64 == 4'hD; // @[Misc.scala:49:20] wire [1:0] _r_T_94 = _r_T_92 ? 2'h2 : _r_T_91; // @[Misc.scala:35:36, :49:20] wire _r_T_95 = _r_T_64 == 4'h4; // @[Misc.scala:49:20] wire [1:0] _r_T_97 = _r_T_95 ? 2'h1 : _r_T_94; // @[Misc.scala:35:36, :49:20] wire _r_T_98 = _r_T_64 == 4'h5; // @[Misc.scala:49:20] wire [1:0] _r_T_100 = _r_T_98 ? 2'h2 : _r_T_97; // @[Misc.scala:35:36, :49:20] wire _r_T_101 = _r_T_64 == 4'h0; // @[Misc.scala:49:20] wire [1:0] _r_T_103 = _r_T_101 ? 2'h0 : _r_T_100; // @[Misc.scala:35:36, :49:20] wire _r_T_104 = _r_T_64 == 4'hE; // @[Misc.scala:49:20] wire _r_T_105 = _r_T_104; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_106 = _r_T_104 ? 2'h3 : _r_T_103; // @[Misc.scala:35:36, :49:20] wire _r_T_107 = &_r_T_64; // @[Misc.scala:49:20] wire _r_T_108 = _r_T_107 \| _r_T_105; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_109 = _r_T_107 ? 2'h3 : _r_T_106; // @[Misc.scala:35:36, :49:20] wire _r_T_110 = _r_T_64 == 4'h6; // @[Misc.scala:49:20] wire _r_T_111 = _r_T_110 \| _r_T_108; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_112 = _r_T_110 ? 2'h2 : _r_T_109; // @[Misc.scala:35:36, :49:20] wire _r_T_113 = _r_T_64 == 4'h7; // @[Misc.scala:49:20] wire _r_T_114 = _r_T_113 \| _r_T_111; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_115 = _r_T_113 ? 2'h3 : _r_T_112; // @[Misc.scala:35:36, :49:20] wire _r_T_116 = _r_T_64 == 4'h1; // @[Misc.scala:49:20] wire _r_T_117 = _r_T_116 \| _r_T_114; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_118 = _r_T_116 ? 2'h1 : _r_T_115; // @[Misc.scala:35:36, :49:20] wire _r_T_119 = _r_T_64 == 4'h2; // @[Misc.scala:49:20] wire _r_T_120 = _r_T_119 \| _r_T_117; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_121 = _r_T_119 ? 2'h2 : _r_T_118; // @[Misc.scala:35:36, :49:20] wire _r_T_122 = _r_T_64 == 4'h3; // @[Misc.scala:49:20] wire is_hit = _r_T_122 \| _r_T_120; // @[Misc.scala:35:9, :49:20] wire [1:0] r_2_1 = _r_T_122 ? 2'h3 : _r_T_121; // @[Misc.scala:35:36, :49:20] wire [1:0] coh_on_hit_state = r_2_1; // @[Misc.scala:35:36] wire [3:0] _state_T = {2'h0, ~needs_wb, 1'h1}; // @[MSHR.scala:122:19] wire _can_finish_T = ~(\|state); // @[MSHR.scala:36:22, :66:75] wire can_finish = _can_finish_T \| _can_finish_T_1; // @[package.scala:16:47, :81:59] wire _grantackq_io_enq_valid_T = io_mem_grant_bits_opcode_0[2]; // @[MSHR.scala:12:7] wire _grantackq_io_enq_valid_T_1 = io_mem_grant_bits_opcode_0[1]; // @[MSHR.scala:12:7] wire _grantackq_io_enq_valid_T_2 = ~_grantackq_io_enq_valid_T_1; // @[Edges.scala:71:{43,52}] wire _grantackq_io_enq_valid_T_3 = _grantackq_io_enq_valid_T & _grantackq_io_enq_valid_T_2; // @[Edges.scala:71:{36,40,43}] wire _grantackq_io_enq_valid_T_4 = refill_done & _grantackq_io_enq_valid_T_3; // @[MSHR.scala:128:41] assign _io_mem_finish_valid_T = _grantackq_io_deq_valid & can_finish; // @[MSHR.scala:126:25, :130:49] assign io_mem_finish_valid_0 = _io_mem_finish_valid_T; // @[MSHR.scala:12:7, :130:49] wire _grantackq_io_deq_ready_T = io_mem_finish_ready_0 & can_finish; // @[MSHR.scala:12:7, :132:49] wire _io_idx_match_T = \|state; // @[MSHR.scala:36:22, :66:75, :134:26] assign _io_idx_match_T_1 = _io_idx_match_T & idx_match; // @[MSHR.scala:42:27, :134:{26,41}] assign io_idx_match_0 = _io_idx_match_T_1; // @[MSHR.scala:12:7, :134:41] wire [39:0] _io_refill_addr_T = {req_block_addr[39:12], req_block_addr[11:0] \| refill_address_inc}; // @[MSHR.scala:41:51, :136:36] assign io_refill_addr_0 = _io_refill_addr_T[11:0]; // @[MSHR.scala:12:7, :136:{18,36}] assign io_tag_0 = req_tag_0[19:0]; // @[MSHR.scala:12:7, :40:26, :137:10] assign _io_req_pri_rdy_T = ~(\|state); // @[MSHR.scala:36:22, :66:75, :138:27] assign io_req_pri_rdy_0 = _io_req_pri_rdy_T; // @[MSHR.scala:12:7, :138:27] assign _io_req_sec_rdy_T = sec_rdy & _rpq_io_enq_ready; // @[MSHR.scala:58:27, :63:19, :139:29] assign io_req_sec_rdy_0 = _io_req_sec_rdy_T; // @[MSHR.scala:12:7, :139:29] reg [1:0] meta_hazard; // @[MSHR.scala:141:28] wire [2:0] _meta_hazard_T = {1'h0, meta_hazard} + 3'h1; // @[MSHR.scala:141:28, :142:59] wire [1:0] _meta_hazard_T_1 = _meta_hazard_T[1:0]; // @[MSHR.scala:142:59] wire _io_probe_rdy_T = \|state; // @[MSHR.scala:36:22, :66:75, :144:27] wire _io_probe_rdy_T_1 = _io_probe_rdy_T & probe_idx_match; // @[MSHR.scala:43:33, :144:{27,41}] wire _io_probe_rdy_T_2 = ~_io_probe_rdy_T_1; // @[MSHR.scala:144:{19,41}] wire _io_probe_rdy_T_6 = _io_probe_rdy_T_3 \| _io_probe_rdy_T_4; // @[package.scala:16:47, :81:59] wire _io_probe_rdy_T_7 = _io_probe_rdy_T_6 \| _io_probe_rdy_T_5; // @[package.scala:16:47, :81:59] wire _io_probe_rdy_T_8 = ~_io_probe_rdy_T_7; // @[MSHR.scala:144:65] wire _io_probe_rdy_T_9 = meta_hazard == 2'h0; // @[MSHR.scala:141:28, :144:117] wire _io_probe_rdy_T_10 = _io_probe_rdy_T_8 & _io_probe_rdy_T_9; // @[MSHR.scala:144:{65,102,117}] assign _io_probe_rdy_T_11 = _io_probe_rdy_T_2 \| _io_probe_rdy_T_10; // @[MSHR.scala:144:{19,61,102}] assign io_probe_rdy_0 = _io_probe_rdy_T_11; // @[MSHR.scala:12:7, :144:61] assign _io_meta_write_valid_T_2 = _io_meta_write_valid_T \| _io_meta_write_valid_T_1; // @[package.scala:16:47, :81:59] assign io_meta_write_valid_0 = _io_meta_write_valid_T_2; // @[MSHR.scala:12:7] assign _io_meta_write_bits_data_coh_T_1_state = _io_meta_write_bits_data_coh_T ? coh_on_clear_state : new_coh_state; // @[MSHR.scala:45:24, :149:{37,44}] assign io_meta_write_bits_data_coh_state_0 = _io_meta_write_bits_data_coh_T_1_state; // @[MSHR.scala:12:7, :149:37] assign io_wb_req_valid_0 = _io_wb_req_valid_T; // @[MSHR.scala:12:7, :153:28] assign _io_mem_acquire_valid_T_1 = _io_mem_acquire_valid_T & _grantackq_io_enq_ready; // @[MSHR.scala:126:25, :161:{33,50}] assign io_mem_acquire_valid_0 = _io_mem_acquire_valid_T_1; // @[MSHR.scala:12:7, :161:50] wire [25:0] _GEN_29 = {io_tag_0, req_idx}; // @[MSHR.scala:12:7, :39:25, :164:48] wire [25:0] _io_mem_acquire_bits_T; // @[MSHR.scala:164:48] assign _io_mem_acquire_bits_T = _GEN_29; // @[MSHR.scala:164:48] wire [25:0] io_replay_bits_addr_hi; // @[MSHR.scala:170:29] assign io_replay_bits_addr_hi = _GEN_29; // @[MSHR.scala:164:48, :170:29] wire [31:0] _io_mem_acquire_bits_T_1 = {_io_mem_acquire_bits_T, 6'h0}; // @[MSHR.scala:41:51, :164:{48,66}] wire [31:0] _io_mem_acquire_bits_legal_T_1 = _io_mem_acquire_bits_T_1; // @[MSHR.scala:164:66] assign io_mem_acquire_bits_a_address = _io_mem_acquire_bits_T_1; // @[MSHR.scala:164:66] wire [32:0] _io_mem_acquire_bits_legal_T_2 = {1'h0, _io_mem_acquire_bits_legal_T_1}; // @[Parameters.scala:137:{31,41}] wire [32:0] _io_mem_acquire_bits_legal_T_3 = _io_mem_acquire_bits_legal_T_2 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _io_mem_acquire_bits_legal_T_4 = _io_mem_acquire_bits_legal_T_3; // @[Parameters.scala:137:46] wire _io_mem_acquire_bits_legal_T_5 = _io_mem_acquire_bits_legal_T_4 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _io_mem_acquire_bits_legal_T_6 = {_io_mem_acquire_bits_T_1[31:17], _io_mem_acquire_bits_T_1[16:0] ^ 17'h10000}; // @[MSHR.scala:164:66] wire [32:0] _io_mem_acquire_bits_legal_T_7 = {1'h0, _io_mem_acquire_bits_legal_T_6}; // @[Parameters.scala:137:{31,41}] wire [32:0] _io_mem_acquire_bits_legal_T_8 = _io_mem_acquire_bits_legal_T_7 & 33'h8C011000; // @[Parameters.scala:137:{41,46}] wire [32:0] _io_mem_acquire_bits_legal_T_9 = _io_mem_acquire_bits_legal_T_8; // @[Parameters.scala:137:46] wire _io_mem_acquire_bits_legal_T_10 = _io_mem_acquire_bits_legal_T_9 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _io_mem_acquire_bits_legal_T_11 = {_io_mem_acquire_bits_T_1[31:28], _io_mem_acquire_bits_T_1[27:0] ^ 28'hC000000}; // @[MSHR.scala:164:66] wire [32:0] _io_mem_acquire_bits_legal_T_12 = {1'h0, _io_mem_acquire_bits_legal_T_11}; // @[Parameters.scala:137:{31,41}] wire [32:0] _io_mem_acquire_bits_legal_T_13 = _io_mem_acquire_bits_legal_T_12 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _io_mem_acquire_bits_legal_T_14 = _io_mem_acquire_bits_legal_T_13; // @[Parameters.scala:137:46] wire _io_mem_acquire_bits_legal_T_15 = _io_mem_acquire_bits_legal_T_14 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _io_mem_acquire_bits_legal_T_16 = _io_mem_acquire_bits_legal_T_5 \| _io_mem_acquire_bits_legal_T_10; // @[Parameters.scala:685:42] wire _io_mem_acquire_bits_legal_T_17 = _io_mem_acquire_bits_legal_T_16 \| _io_mem_acquire_bits_legal_T_15; // @[Parameters.scala:685:42] wire [31:0] _io_mem_acquire_bits_legal_T_21 = {_io_mem_acquire_bits_T_1[31:28], _io_mem_acquire_bits_T_1[27:0] ^ 28'h8000000}; // @[MSHR.scala:164:66] wire [32:0] _io_mem_acquire_bits_legal_T_22 = {1'h0, _io_mem_acquire_bits_legal_T_21}; // @[Parameters.scala:137:{31,41}] wire [32:0] _io_mem_acquire_bits_legal_T_23 = _io_mem_acquire_bits_legal_T_22 & 33'h8C010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _io_mem_acquire_bits_legal_T_24 = _io_mem_acquire_bits_legal_T_23; // @[Parameters.scala:137:46] wire _io_mem_acquire_bits_legal_T_25 = _io_mem_acquire_bits_legal_T_24 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _io_mem_acquire_bits_legal_T_26 = _io_mem_acquire_bits_T_1 ^ 32'h80000000; // @[MSHR.scala:164:66] wire [32:0] _io_mem_acquire_bits_legal_T_27 = {1'h0, _io_mem_acquire_bits_legal_T_26}; // @[Parameters.scala:137:{31,41}] wire [32:0] _io_mem_acquire_bits_legal_T_28 = _io_mem_acquire_bits_legal_T_27 & 33'h80000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _io_mem_acquire_bits_legal_T_29 = _io_mem_acquire_bits_legal_T_28; // @[Parameters.scala:137:46] wire _io_mem_acquire_bits_legal_T_30 = _io_mem_acquire_bits_legal_T_29 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _io_mem_acquire_bits_legal_T_31 = _io_mem_acquire_bits_legal_T_25 \| _io_mem_acquire_bits_legal_T_30; // @[Parameters.scala:685:42] wire _io_mem_acquire_bits_legal_T_32 = _io_mem_acquire_bits_legal_T_31; // @[Parameters.scala:684:54, :685:42] wire io_mem_acquire_bits_legal = _io_mem_acquire_bits_legal_T_32; // @[Parameters.scala:684:54, :686:26] assign io_mem_acquire_bits_param_0 = io_mem_acquire_bits_a_param; // @[MSHR.scala:12:7] assign io_mem_acquire_bits_address_0 = io_mem_acquire_bits_a_address; // @[MSHR.scala:12:7] assign io_mem_acquire_bits_a_param = {1'h0, grow_param}; // @[Misc.scala:35:36] wire io_mem_acquire_bits_a_mask_sub_sub_bit = _io_mem_acquire_bits_T_1[2]; // @[MSHR.scala:164:66] wire io_mem_acquire_bits_a_mask_sub_sub_1_2 = io_mem_acquire_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire io_mem_acquire_bits_a_mask_sub_sub_nbit = ~io_mem_acquire_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire io_mem_acquire_bits_a_mask_sub_sub_0_2 = io_mem_acquire_bits_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_sub_sub_acc_T = io_mem_acquire_bits_a_mask_sub_sub_0_2; // @[Misc.scala:214:27, :215:38] wire _io_mem_acquire_bits_a_mask_sub_sub_acc_T_1 = io_mem_acquire_bits_a_mask_sub_sub_1_2; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_sub_bit = _io_mem_acquire_bits_T_1[1]; // @[MSHR.scala:164:66] wire io_mem_acquire_bits_a_mask_sub_nbit = ~io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire io_mem_acquire_bits_a_mask_sub_0_2 = io_mem_acquire_bits_a_mask_sub_sub_0_2 & io_mem_acquire_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire io_mem_acquire_bits_a_mask_sub_1_2 = io_mem_acquire_bits_a_mask_sub_sub_0_2 & io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire io_mem_acquire_bits_a_mask_sub_2_2 = io_mem_acquire_bits_a_mask_sub_sub_1_2 & io_mem_acquire_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire io_mem_acquire_bits_a_mask_sub_3_2 = io_mem_acquire_bits_a_mask_sub_sub_1_2 & io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire io_mem_acquire_bits_a_mask_bit = _io_mem_acquire_bits_T_1[0]; // @[MSHR.scala:164:66] wire io_mem_acquire_bits_a_mask_nbit = ~io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire io_mem_acquire_bits_a_mask_eq = io_mem_acquire_bits_a_mask_sub_0_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T = io_mem_acquire_bits_a_mask_eq; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_1 = io_mem_acquire_bits_a_mask_sub_0_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_1 = io_mem_acquire_bits_a_mask_eq_1; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_2 = io_mem_acquire_bits_a_mask_sub_1_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_2 = io_mem_acquire_bits_a_mask_eq_2; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_3 = io_mem_acquire_bits_a_mask_sub_1_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_3 = io_mem_acquire_bits_a_mask_eq_3; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_4 = io_mem_acquire_bits_a_mask_sub_2_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_4 = io_mem_acquire_bits_a_mask_eq_4; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_5 = io_mem_acquire_bits_a_mask_sub_2_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_5 = io_mem_acquire_bits_a_mask_eq_5; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_6 = io_mem_acquire_bits_a_mask_sub_3_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_6 = io_mem_acquire_bits_a_mask_eq_6; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_7 = io_mem_acquire_bits_a_mask_sub_3_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_7 = io_mem_acquire_bits_a_mask_eq_7; // @[Misc.scala:214:27, :215:38] assign _io_replay_valid_T_1 = _io_replay_valid_T & _rpq_io_deq_valid; // @[MSHR.scala:63:19, :168:{28,44}] assign io_replay_valid_0 = _io_replay_valid_T_1; // @[MSHR.scala:12:7, :168:44] wire [5:0] _io_replay_bits_addr_T = _rpq_io_deq_bits_addr[5:0]; // @[MSHR.scala:63:19, :170:67] wire [31:0] _io_replay_bits_addr_T_1 = {io_replay_bits_addr_hi, _io_replay_bits_addr_T}; // @[MSHR.scala:170:{29,67}] assign io_replay_bits_addr_0 = {8'h0, _io_replay_bits_addr_T_1}; // @[MSHR.scala:12:7, :170:{23,29}] wire _state_T_1 = ~_rpq_io_deq_valid; // @[MSHR.scala:63:19, :71:34, :174:26] reg state_REG; // @[MSHR.scala:174:25] wire [3:0] _state_T_2 = state_REG ? 4'h0 : state; // @[MSHR.scala:36:22, :174:{17,25}] wire _rpq_io_deq_ready_T_5 = io_replay_ready_0 & _rpq_io_deq_ready_T_4; // @[MSHR.scala:12:7, :176:{39,48}] wire _T_7 = _sec_rdy_T_6 & refill_done; // @[MSHR.scala:81:33] wire _T_15 = io_req_sec_val_0 & io_req_sec_rdy_0; // @[MSHR.scala:12:7, :97:24] always @(posedge clock) begin // @[MSHR.scala:12:7] if (reset) begin // @[MSHR.scala:12:7] state <= 4'h0; // @[MSHR.scala:36:22] new_coh_state <= 2'h0; // @[MSHR.scala:45:24] r_counter <= 9'h0; // @[Edges.scala:229:27] meta_hazard <= 2'h0; // @[MSHR.scala:141:28] end else begin // @[MSHR.scala:12:7] if (_T_19 & ~_rpq_io_deq_valid) // @[MSHR.scala:63:19, :66:49, :71:34, :173:31] state <= _state_T_2; // @[MSHR.scala:36:22, :174:17] else if (_rpq_io_enq_valid_T) // @[MSHR.scala:64:39] state <= io_req_bits_tag_match_0 ? {2'h1, is_hit, 1'h0} : _state_T; // @[MSHR.scala:12:7, :36:22, :112:34, :113:21, :115:15, :118:15, :122:{13,19}] else if (io_wb_req_ready_0 & io_wb_req_valid_0) // @[Decoupled.scala:51:35] state <= 4'h2; // @[MSHR.scala:36:22] else if (_T_11 & io_wb_req_ready_0 & acked) // @[MSHR.scala:12:7, :68:18, :91:{29,48}] state <= 4'h3; // @[MSHR.scala:36:22] else if (_T_9 & io_meta_write_ready_0) // @[MSHR.scala:12:7, :88:32] state <= 4'h4; // @[MSHR.scala:36:22] else if (io_mem_acquire_ready_0 & io_mem_acquire_valid_0) // @[Decoupled.scala:51:35] state <= 4'h5; // @[MSHR.scala:36:22] else if (_T_7) // @[MSHR.scala:81:33] state <= 4'h6; // @[MSHR.scala:36:22] else if (_io_meta_write_valid_T & io_meta_write_ready_0) // @[MSHR.scala:12:7, :78:36] state <= 4'h7; // @[MSHR.scala:36:22] else if (state == 4'h7) // @[MSHR.scala:36:22, :74:15] state <= 4'h8; // @[MSHR.scala:36:22] else if (_T_19 & ~_rpq_io_deq_valid) // @[MSHR.scala:63:19, :66:49, :71:{31,34}] state <= 4'h0; // @[MSHR.scala:36:22] if (_rpq_io_enq_valid_T) // @[MSHR.scala:64:39] new_coh_state <= io_req_bits_tag_match_0 ? (is_hit ? coh_on_hit_state : io_req_bits_old_meta_coh_state_0) : 2'h0; // @[MSHR.scala:12:7, :45:24, :112:34, :113:21, :114:17, :117:17, :121:15] else if (_T_15 & is_hit_again) // @[MSHR.scala:81:49, :97:{24,43}, :102:25, :103:15] new_coh_state <= dirtier_coh_state; // @[MSHR.scala:45:24] else if (_T_7) // @[MSHR.scala:81:33] new_coh_state <= coh_on_grant_state; // @[MSHR.scala:45:24] if (io_mem_grant_valid_0) // @[MSHR.scala:12:7] r_counter <= _r_counter_T; // @[Edges.scala:229:27, :236:21] if (io_meta_write_ready_0 & io_meta_write_valid_0) // @[Decoupled.scala:51:35] meta_hazard <= 2'h1; // @[MSHR.scala:141:28] else if (\|meta_hazard) // @[MSHR.scala:141:28, :142:21] meta_hazard <= _meta_hazard_T_1; // @[MSHR.scala:141:28, :142:59] end if (_rpq_io_enq_valid_T) begin // @[MSHR.scala:64:39] req_addr <= io_req_bits_addr_0; // @[MSHR.scala:12:7, :38:16] req_tag <= io_req_bits_tag_0; // @[MSHR.scala:12:7, :38:16] req_cmd <= io_req_bits_cmd_0; // @[MSHR.scala:12:7, :38:16] req_size <= io_req_bits_size_0; // @[MSHR.scala:12:7, :38:16] req_signed <= io_req_bits_signed_0; // @[MSHR.scala:12:7, :38:16] req_data <= io_req_bits_data_0; // @[MSHR.scala:12:7, :38:16] req_mask <= io_req_bits_mask_0; // @[MSHR.scala:12:7, :38:16] req_tag_match <= io_req_bits_tag_match_0; // @[MSHR.scala:12:7, :38:16] req_old_meta_coh_state <= io_req_bits_old_meta_coh_state_0; // @[MSHR.scala:12:7, :38:16] req_old_meta_tag <= io_req_bits_old_meta_tag_0; // @[MSHR.scala:12:7, :38:16] req_way_en <= io_req_bits_way_en_0; // @[MSHR.scala:12:7, :38:16] req_sdq_id <= io_req_bits_sdq_id_0; // @[MSHR.scala:12:7, :38:16] end else if (_T_15) // @[MSHR.scala:97:24] req_cmd <= dirtier_cmd; // @[MSHR.scala:38:16] acked <= ~_rpq_io_enq_valid_T & (io_mem_grant_valid_0 \| acked); // @[MSHR.scala:12:7, :64:39, :68:18, :69:{29,37}, :106:43, :108:11] state_REG <= _state_T_1; // @[MSHR.scala:174:{25,26}] always @(posedge) Queue16_ShuttleMSHRReq_3 rpq ( // @[MSHR.scala:63:19] .clock (clock), .reset (reset), .io_enq_ready (_rpq_io_enq_ready), .io_enq_valid (_rpq_io_enq_valid_T_7), // @[MSHR.scala:64:87] .io_enq_bits_addr (io_req_bits_addr_0), // @[MSHR.scala:12:7] .io_enq_bits_tag (io_req_bits_tag_0), // @[MSHR.scala:12:7] .io_enq_bits_cmd (io_req_bits_cmd_0), // @[MSHR.scala:12:7] .io_enq_bits_size (io_req_bits_size_0), // @[MSHR.scala:12:7] .io_enq_bits_signed (io_req_bits_signed_0), // @[MSHR.scala:12:7] .io_enq_bits_data (io_req_bits_data_0), // @[MSHR.scala:12:7] .io_enq_bits_mask (io_req_bits_mask_0), // @[MSHR.scala:12:7] .io_enq_bits_tag_match (io_req_bits_tag_match_0), // @[MSHR.scala:12:7] .io_enq_bits_old_meta_coh_state (io_req_bits_old_meta_coh_state_0), // @[MSHR.scala:12:7] .io_enq_bits_old_meta_tag (io_req_bits_old_meta_tag_0), // @[MSHR.scala:12:7] .io_enq_bits_way_en (io_req_bits_way_en_0), // @[MSHR.scala:12:7] .io_enq_bits_sdq_id (io_req_bits_sdq_id_0), // @[MSHR.scala:12:7] .io_deq_ready (_rpq_io_deq_ready_T_5), // @[MSHR.scala:176:39] .io_deq_valid (_rpq_io_deq_valid), .io_deq_bits_addr (_rpq_io_deq_bits_addr), .io_deq_bits_tag (io_replay_bits_tag_0), .io_deq_bits_cmd (io_replay_bits_cmd_0), .io_deq_bits_size (io_replay_bits_size_0), .io_deq_bits_signed (io_replay_bits_signed_0), .io_deq_bits_data (io_replay_bits_data_0), .io_deq_bits_mask (io_replay_bits_mask_0), .io_deq_bits_tag_match (io_replay_bits_tag_match_0), .io_deq_bits_old_meta_coh_state (io_replay_bits_old_meta_coh_state_0), .io_deq_bits_old_meta_tag (io_replay_bits_old_meta_tag_0), .io_deq_bits_way_en (io_replay_bits_way_en_0), .io_deq_bits_sdq_id (io_replay_bits_sdq_id_0) ); // @[MSHR.scala:63:19] Queue1_TLBundleE_a32d64s3k3z4c_3 grantackq ( // @[MSHR.scala:126:25] .clock (clock), .reset (reset), .io_enq_ready (_grantackq_io_enq_ready), .io_enq_valid (_grantackq_io_enq_valid_T_4), // @[MSHR.scala:128:41] .io_enq_bits_sink (grantackq_io_enq_bits_e_sink), // @[Edges.scala:451:17] .io_deq_ready (_grantackq_io_deq_ready_T), // @[MSHR.scala:132:49] .io_deq_valid (_grantackq_io_deq_valid), .io_deq_bits_sink (io_mem_finish_bits_sink_0) ); // @[MSHR.scala:126:25] assign io_req_pri_rdy = io_req_pri_rdy_0; // @[MSHR.scala:12:7] assign io_req_sec_rdy = io_req_sec_rdy_0; // @[MSHR.scala:12:7] assign io_idx_match = io_idx_match_0; // @[MSHR.scala:12:7] assign io_tag = io_tag_0; // @[MSHR.scala:12:7] assign io_mem_acquire_valid = io_mem_acquire_valid_0; // @[MSHR.scala:12:7] assign io_mem_acquire_bits_param = io_mem_acquire_bits_param_0; // @[MSHR.scala:12:7] assign io_mem_acquire_bits_address = io_mem_acquire_bits_address_0; // @[MSHR.scala:12:7] assign io_mem_finish_valid = io_mem_finish_valid_0; // @[MSHR.scala:12:7] assign io_mem_finish_bits_sink = io_mem_finish_bits_sink_0; // @[MSHR.scala:12:7] assign io_refill_way_en = io_refill_way_en_0; // @[MSHR.scala:12:7] assign io_refill_addr = io_refill_addr_0; // @[MSHR.scala:12:7] assign io_meta_write_valid = io_meta_write_valid_0; // @[MSHR.scala:12:7] assign io_meta_write_bits_idx = io_meta_write_bits_idx_0; // @[MSHR.scala:12:7] assign io_meta_write_bits_way_en = io_meta_write_bits_way_en_0; // @[MSHR.scala:12:7] assign io_meta_write_bits_tag = io_meta_write_bits_tag_0; // @[MSHR.scala:12:7] assign io_meta_write_bits_data_coh_state = io_meta_write_bits_data_coh_state_0; // @[MSHR.scala:12:7] assign io_meta_write_bits_data_tag = io_meta_write_bits_data_tag_0; // @[MSHR.scala:12:7] assign io_replay_valid = io_replay_valid_0; // @[MSHR.scala:12:7] assign io_replay_bits_addr = io_replay_bits_addr_0; // @[MSHR.scala:12:7] assign io_replay_bits_tag = io_replay_bits_tag_0; // @[MSHR.scala:12:7] assign io_replay_bits_cmd = io_replay_bits_cmd_0; // @[MSHR.scala:12:7] assign io_replay_bits_size = io_replay_bits_size_0; // @[MSHR.scala:12:7] assign io_replay_bits_signed = io_replay_bits_signed_0; // @[MSHR.scala:12:7] assign io_replay_bits_data = io_replay_bits_data_0; // @[MSHR.scala:12:7] assign io_replay_bits_mask = io_replay_bits_mask_0; // @[MSHR.scala:12:7] assign io_replay_bits_tag_match = io_replay_bits_tag_match_0; // @[MSHR.scala:12:7] assign io_replay_bits_old_meta_coh_state = io_replay_bits_old_meta_coh_state_0; // @[MSHR.scala:12:7] assign io_replay_bits_old_meta_tag = io_replay_bits_old_meta_tag_0; // @[MSHR.scala:12:7] assign io_replay_bits_way_en = io_replay_bits_way_en_0; // @[MSHR.scala:12:7] assign io_replay_bits_sdq_id = io_replay_bits_sdq_id_0; // @[MSHR.scala:12:7] assign io_wb_req_valid = io_wb_req_valid_0; // @[MSHR.scala:12:7] assign io_wb_req_bits_tag = io_wb_req_bits_tag_0; // @[MSHR.scala:12:7] assign io_wb_req_bits_idx = io_wb_req_bits_idx_0; // @[MSHR.scala:12:7] assign io_wb_req_bits_param = io_wb_req_bits_param_0; // @[MSHR.scala:12:7] assign io_wb_req_bits_way_en = io_wb_req_bits_way_en_0; // @[MSHR.scala:12:7] assign io_probe_rdy = io_probe_rdy_0; // @[MSHR.scala:12:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_40( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File FPU.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.tile import chisel3._ import chisel3.util._ import chisel3.{DontCare, WireInit, withClock, withReset} import chisel3.experimental.SourceInfo import chisel3.experimental.dataview._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.rocket._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property case class FPUParams( minFLen: Int = 32, fLen: Int = 64, divSqrt: Boolean = true, sfmaLatency: Int = 3, dfmaLatency: Int = 4, fpmuLatency: Int = 2, ifpuLatency: Int = 2 ) object FPConstants { val RM_SZ = 3 val FLAGS_SZ = 5 } trait HasFPUCtrlSigs { val ldst = Bool() val wen = Bool() val ren1 = Bool() val ren2 = Bool() val ren3 = Bool() val swap12 = Bool() val swap23 = Bool() val typeTagIn = UInt(2.W) val typeTagOut = UInt(2.W) val fromint = Bool() val toint = Bool() val fastpipe = Bool() val fma = Bool() val div = Bool() val sqrt = Bool() val wflags = Bool() val vec = Bool() } class FPUCtrlSigs extends Bundle with HasFPUCtrlSigs class FPUDecoder(implicit p: Parameters) extends FPUModule()(p) { val io = IO(new Bundle { val inst = Input(Bits(32.W)) val sigs = Output(new FPUCtrlSigs()) }) private val X2 = BitPat.dontCare(2) val default = List(X,X,X,X,X,X,X,X2,X2,X,X,X,X,X,X,X,N) val h: Array[(BitPat, List[BitPat])] = Array(FLH -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N), FSH -> List(Y,N,N,Y,N,Y,X, I, H,N,Y,N,N,N,N,N,N), FMV_H_X -> List(N,Y,N,N,N,X,X, H, I,Y,N,N,N,N,N,N,N), FCVT_H_W -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FCVT_H_WU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FCVT_H_L -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FCVT_H_LU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FMV_X_H -> List(N,N,Y,N,N,N,X, I, H,N,Y,N,N,N,N,N,N), FCLASS_H -> List(N,N,Y,N,N,N,X, H, H,N,Y,N,N,N,N,N,N), FCVT_W_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_WU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_L_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_LU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_S_H -> List(N,Y,Y,N,N,N,X, H, S,N,N,Y,N,N,N,Y,N), FCVT_H_S -> List(N,Y,Y,N,N,N,X, S, H,N,N,Y,N,N,N,Y,N), FEQ_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N), FLT_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N), FLE_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N), FSGNJ_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N), FSGNJN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N), FSGNJX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N), FMIN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N), FMAX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N), FADD_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N), FSUB_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N), FMUL_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,Y,N,N,Y,N), FMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FNMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FNMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FDIV_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,N,Y,N,Y,N), FSQRT_H -> List(N,Y,Y,N,N,N,X, H, H,N,N,N,N,N,Y,Y,N)) val f: Array[(BitPat, List[BitPat])] = Array(FLW -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N), FSW -> List(Y,N,N,Y,N,Y,X, I, S,N,Y,N,N,N,N,N,N), FMV_W_X -> List(N,Y,N,N,N,X,X, S, I,Y,N,N,N,N,N,N,N), FCVT_S_W -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FCVT_S_WU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FCVT_S_L -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FCVT_S_LU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FMV_X_W -> List(N,N,Y,N,N,N,X, I, S,N,Y,N,N,N,N,N,N), FCLASS_S -> List(N,N,Y,N,N,N,X, S, S,N,Y,N,N,N,N,N,N), FCVT_W_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FCVT_WU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FCVT_L_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FCVT_LU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FEQ_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N), FLT_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N), FLE_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N), FSGNJ_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N), FSGNJN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N), FSGNJX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N), FMIN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N), FMAX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N), FADD_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N), FSUB_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N), FMUL_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,Y,N,N,Y,N), FMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FNMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FNMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FDIV_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,N,Y,N,Y,N), FSQRT_S -> List(N,Y,Y,N,N,N,X, S, S,N,N,N,N,N,Y,Y,N)) val d: Array[(BitPat, List[BitPat])] = Array(FLD -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N), FSD -> List(Y,N,N,Y,N,Y,X, I, D,N,Y,N,N,N,N,N,N), FMV_D_X -> List(N,Y,N,N,N,X,X, D, I,Y,N,N,N,N,N,N,N), FCVT_D_W -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FCVT_D_WU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FCVT_D_L -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FCVT_D_LU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FMV_X_D -> List(N,N,Y,N,N,N,X, I, D,N,Y,N,N,N,N,N,N), FCLASS_D -> List(N,N,Y,N,N,N,X, D, D,N,Y,N,N,N,N,N,N), FCVT_W_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_WU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_L_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_LU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_S_D -> List(N,Y,Y,N,N,N,X, D, S,N,N,Y,N,N,N,Y,N), FCVT_D_S -> List(N,Y,Y,N,N,N,X, S, D,N,N,Y,N,N,N,Y,N), FEQ_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N), FLT_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N), FLE_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N), FSGNJ_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N), FSGNJN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N), FSGNJX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N), FMIN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N), FMAX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N), FADD_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N), FSUB_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N), FMUL_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,Y,N,N,Y,N), FMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FNMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FNMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FDIV_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,N,Y,N,Y,N), FSQRT_D -> List(N,Y,Y,N,N,N,X, D, D,N,N,N,N,N,Y,Y,N)) val fcvt_hd: Array[(BitPat, List[BitPat])] = Array(FCVT_H_D -> List(N,Y,Y,N,N,N,X, D, H,N,N,Y,N,N,N,Y,N), FCVT_D_H -> List(N,Y,Y,N,N,N,X, H, D,N,N,Y,N,N,N,Y,N)) val vfmv_f_s: Array[(BitPat, List[BitPat])] = Array(VFMV_F_S -> List(N,Y,N,N,N,N,X,X2,X2,N,N,N,N,N,N,N,Y)) val insns = ((minFLen, fLen) match { case (32, 32) => f case (16, 32) => h ++ f case (32, 64) => f ++ d case (16, 64) => h ++ f ++ d ++ fcvt_hd case other => throw new Exception(s"minFLen = ${minFLen} & fLen = ${fLen} is an unsupported configuration") }) ++ (if (usingVector) vfmv_f_s else Array[(BitPat, List[BitPat])]()) val decoder = DecodeLogic(io.inst, default, insns) val s = io.sigs val sigs = Seq(s.ldst, s.wen, s.ren1, s.ren2, s.ren3, s.swap12, s.swap23, s.typeTagIn, s.typeTagOut, s.fromint, s.toint, s.fastpipe, s.fma, s.div, s.sqrt, s.wflags, s.vec) sigs zip decoder map {case(s,d) => s := d} } class FPUCoreIO(implicit p: Parameters) extends CoreBundle()(p) { val hartid = Input(UInt(hartIdLen.W)) val time = Input(UInt(xLen.W)) val inst = Input(Bits(32.W)) val fromint_data = Input(Bits(xLen.W)) val fcsr_rm = Input(Bits(FPConstants.RM_SZ.W)) val fcsr_flags = Valid(Bits(FPConstants.FLAGS_SZ.W)) val v_sew = Input(UInt(3.W)) val store_data = Output(Bits(fLen.W)) val toint_data = Output(Bits(xLen.W)) val ll_resp_val = Input(Bool()) val ll_resp_type = Input(Bits(3.W)) val ll_resp_tag = Input(UInt(5.W)) val ll_resp_data = Input(Bits(fLen.W)) val valid = Input(Bool()) val fcsr_rdy = Output(Bool()) val nack_mem = Output(Bool()) val illegal_rm = Output(Bool()) val killx = Input(Bool()) val killm = Input(Bool()) val dec = Output(new FPUCtrlSigs()) val sboard_set = Output(Bool()) val sboard_clr = Output(Bool()) val sboard_clra = Output(UInt(5.W)) val keep_clock_enabled = Input(Bool()) } class FPUIO(implicit p: Parameters) extends FPUCoreIO ()(p) { val cp_req = Flipped(Decoupled(new FPInput())) //cp doesn't pay attn to kill sigs val cp_resp = Decoupled(new FPResult()) } class FPResult(implicit p: Parameters) extends CoreBundle()(p) { val data = Bits((fLen+1).W) val exc = Bits(FPConstants.FLAGS_SZ.W) } class IntToFPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs { val rm = Bits(FPConstants.RM_SZ.W) val typ = Bits(2.W) val in1 = Bits(xLen.W) } class FPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs { val rm = Bits(FPConstants.RM_SZ.W) val fmaCmd = Bits(2.W) val typ = Bits(2.W) val fmt = Bits(2.W) val in1 = Bits((fLen+1).W) val in2 = Bits((fLen+1).W) val in3 = Bits((fLen+1).W) } case class FType(exp: Int, sig: Int) { def ieeeWidth = exp + sig def recodedWidth = ieeeWidth + 1 def ieeeQNaN = ((BigInt(1) << (ieeeWidth - 1)) - (BigInt(1) << (sig - 2))).U(ieeeWidth.W) def qNaN = ((BigInt(7) << (exp + sig - 3)) + (BigInt(1) << (sig - 2))).U(recodedWidth.W) def isNaN(x: UInt) = x(sig + exp - 1, sig + exp - 3).andR def isSNaN(x: UInt) = isNaN(x) && !x(sig - 2) def classify(x: UInt) = { val sign = x(sig + exp) val code = x(exp + sig - 1, exp + sig - 3) val codeHi = code(2, 1) val isSpecial = codeHi === 3.U val isHighSubnormalIn = x(exp + sig - 3, sig - 1) < 2.U val isSubnormal = code === 1.U \|\| codeHi === 1.U && isHighSubnormalIn val isNormal = codeHi === 1.U && !isHighSubnormalIn \|\| codeHi === 2.U val isZero = code === 0.U val isInf = isSpecial && !code(0) val isNaN = code.andR val isSNaN = isNaN && !x(sig-2) val isQNaN = isNaN && x(sig-2) Cat(isQNaN, isSNaN, isInf && !sign, isNormal && !sign, isSubnormal && !sign, isZero && !sign, isZero && sign, isSubnormal && sign, isNormal && sign, isInf && sign) } // convert between formats, ignoring rounding, range, NaN def unsafeConvert(x: UInt, to: FType) = if (this == to) x else { val sign = x(sig + exp) val fractIn = x(sig - 2, 0) val expIn = x(sig + exp - 1, sig - 1) val fractOut = fractIn << to.sig >> sig val expOut = { val expCode = expIn(exp, exp - 2) val commonCase = (expIn + (1 << to.exp).U) - (1 << exp).U Mux(expCode === 0.U \|\| expCode >= 6.U, Cat(expCode, commonCase(to.exp - 3, 0)), commonCase(to.exp, 0)) } Cat(sign, expOut, fractOut) } private def ieeeBundle = { val expWidth = exp class IEEEBundle extends Bundle { val sign = Bool() val exp = UInt(expWidth.W) val sig = UInt((ieeeWidth-expWidth-1).W) } new IEEEBundle } def unpackIEEE(x: UInt) = x.asTypeOf(ieeeBundle) def recode(x: UInt) = hardfloat.recFNFromFN(exp, sig, x) def ieee(x: UInt) = hardfloat.fNFromRecFN(exp, sig, x) } object FType { val H = new FType(5, 11) val S = new FType(8, 24) val D = new FType(11, 53) val all = List(H, S, D) } trait HasFPUParameters { require(fLen == 0 \|\| FType.all.exists(_.ieeeWidth == fLen)) val minFLen: Int val fLen: Int def xLen: Int val minXLen = 32 val nIntTypes = log2Ceil(xLen/minXLen) + 1 def floatTypes = FType.all.filter(t => minFLen <= t.ieeeWidth && t.ieeeWidth <= fLen) def minType = floatTypes.head def maxType = floatTypes.last def prevType(t: FType) = floatTypes(typeTag(t) - 1) def maxExpWidth = maxType.exp def maxSigWidth = maxType.sig def typeTag(t: FType) = floatTypes.indexOf(t) def typeTagWbOffset = (FType.all.indexOf(minType) + 1).U def typeTagGroup(t: FType) = (if (floatTypes.contains(t)) typeTag(t) else typeTag(maxType)).U // typeTag def H = typeTagGroup(FType.H) def S = typeTagGroup(FType.S) def D = typeTagGroup(FType.D) def I = typeTag(maxType).U private def isBox(x: UInt, t: FType): Bool = x(t.sig + t.exp, t.sig + t.exp - 4).andR private def box(x: UInt, xt: FType, y: UInt, yt: FType): UInt = { require(xt.ieeeWidth == 2 yt.ieeeWidth) val swizzledNaN = Cat( x(xt.sig + xt.exp, xt.sig + xt.exp - 3), x(xt.sig - 2, yt.recodedWidth - 1).andR, x(xt.sig + xt.exp - 5, xt.sig), y(yt.recodedWidth - 2), x(xt.sig - 2, yt.recodedWidth - 1), y(yt.recodedWidth - 1), y(yt.recodedWidth - 3, 0)) Mux(xt.isNaN(x), swizzledNaN, x) } // implement NaN unboxing for FU inputs def unbox(x: UInt, tag: UInt, exactType: Option[FType]): UInt = { val outType = exactType.getOrElse(maxType) def helper(x: UInt, t: FType): Seq[(Bool, UInt)] = { val prev = if (t == minType) { Seq() } else { val prevT = prevType(t) val unswizzled = Cat( x(prevT.sig + prevT.exp - 1), x(t.sig - 1), x(prevT.sig + prevT.exp - 2, 0)) val prev = helper(unswizzled, prevT) val isbox = isBox(x, t) prev.map(p => (isbox && p._1, p._2)) } prev :+ (true.B, t.unsafeConvert(x, outType)) } val (oks, floats) = helper(x, maxType).unzip if (exactType.isEmpty \|\| floatTypes.size == 1) { Mux(oks(tag), floats(tag), maxType.qNaN) } else { val t = exactType.get floats(typeTag(t)) \| Mux(oks(typeTag(t)), 0.U, t.qNaN) } } // make sure that the redundant bits in the NaN-boxed encoding are consistent def consistent(x: UInt): Bool = { def helper(x: UInt, t: FType): Bool = if (typeTag(t) == 0) true.B else { val prevT = prevType(t) val unswizzled = Cat( x(prevT.sig + prevT.exp - 1), x(t.sig - 1), x(prevT.sig + prevT.exp - 2, 0)) val prevOK = !isBox(x, t) \|\| helper(unswizzled, prevT) val curOK = !t.isNaN(x) \|\| x(t.sig + t.exp - 4) === x(t.sig - 2, prevT.recodedWidth - 1).andR prevOK && curOK } helper(x, maxType) } // generate a NaN box from an FU result def box(x: UInt, t: FType): UInt = { if (t == maxType) { x } else { val nt = floatTypes(typeTag(t) + 1) val bigger = box(((BigInt(1) << nt.recodedWidth)-1).U, nt, x, t) bigger \| ((BigInt(1) << maxType.recodedWidth) - (BigInt(1) << nt.recodedWidth)).U } } // generate a NaN box from an FU result def box(x: UInt, tag: UInt): UInt = { val opts = floatTypes.map(t => box(x, t)) opts(tag) } // zap bits that hardfloat thinks are don't-cares, but we do care about def sanitizeNaN(x: UInt, t: FType): UInt = { if (typeTag(t) == 0) { x } else { val maskedNaN = x & ~((BigInt(1) << (t.sig-1)) \| (BigInt(1) << (t.sig+t.exp-4))).U(t.recodedWidth.W) Mux(t.isNaN(x), maskedNaN, x) } } // implement NaN boxing and recoding for FL/fmv..x def recode(x: UInt, tag: UInt): UInt = { def helper(x: UInt, t: FType): UInt = { if (typeTag(t) == 0) { t.recode(x) } else { val prevT = prevType(t) box(t.recode(x), t, helper(x, prevT), prevT) } } // fill MSBs of subword loads to emulate a wider load of a NaN-boxed value val boxes = floatTypes.map(t => ((BigInt(1) << maxType.ieeeWidth) - (BigInt(1) << t.ieeeWidth)).U) helper(boxes(tag) \| x, maxType) } // implement NaN unboxing and un-recoding for FS/fmv.x. def ieee(x: UInt, t: FType = maxType): UInt = { if (typeTag(t) == 0) { t.ieee(x) } else { val unrecoded = t.ieee(x) val prevT = prevType(t) val prevRecoded = Cat( x(prevT.recodedWidth-2), x(t.sig-1), x(prevT.recodedWidth-3, 0)) val prevUnrecoded = ieee(prevRecoded, prevT) Cat(unrecoded >> prevT.ieeeWidth, Mux(t.isNaN(x), prevUnrecoded, unrecoded(prevT.ieeeWidth-1, 0))) } } } abstract class FPUModule(implicit val p: Parameters) extends Module with HasCoreParameters with HasFPUParameters class FPToInt(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { class Output extends Bundle { val in = new FPInput val lt = Bool() val store = Bits(fLen.W) val toint = Bits(xLen.W) val exc = Bits(FPConstants.FLAGS_SZ.W) } val io = IO(new Bundle { val in = Flipped(Valid(new FPInput)) val out = Valid(new Output) }) val in = RegEnable(io.in.bits, io.in.valid) val valid = RegNext(io.in.valid) val dcmp = Module(new hardfloat.CompareRecFN(maxExpWidth, maxSigWidth)) dcmp.io.a := in.in1 dcmp.io.b := in.in2 dcmp.io.signaling := !in.rm(1) val tag = in.typeTagOut val toint_ieee = (floatTypes.map(t => if (t == FType.H) Fill(maxType.ieeeWidth / minXLen, ieee(in.in1)(15, 0).sextTo(minXLen)) else Fill(maxType.ieeeWidth / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag) val toint = WireDefault(toint_ieee) val intType = WireDefault(in.fmt(0)) io.out.bits.store := (floatTypes.map(t => Fill(fLen / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag) io.out.bits.toint := ((0 until nIntTypes).map(i => toint((minXLen << i) - 1, 0).sextTo(xLen)): Seq[UInt])(intType) io.out.bits.exc := 0.U when (in.rm(0)) { val classify_out = (floatTypes.map(t => t.classify(maxType.unsafeConvert(in.in1, t))): Seq[UInt])(tag) toint := classify_out \| (toint_ieee >> minXLen << minXLen) intType := false.B } when (in.wflags) { // feq/flt/fle, fcvt toint := (~in.rm & Cat(dcmp.io.lt, dcmp.io.eq)).orR \| (toint_ieee >> minXLen << minXLen) io.out.bits.exc := dcmp.io.exceptionFlags intType := false.B when (!in.ren2) { // fcvt val cvtType = in.typ.extract(log2Ceil(nIntTypes), 1) intType := cvtType val conv = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, xLen)) conv.io.in := in.in1 conv.io.roundingMode := in.rm conv.io.signedOut := ~in.typ(0) toint := conv.io.out io.out.bits.exc := Cat(conv.io.intExceptionFlags(2, 1).orR, 0.U(3.W), conv.io.intExceptionFlags(0)) for (i <- 0 until nIntTypes-1) { val w = minXLen << i when (cvtType === i.U) { val narrow = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, w)) narrow.io.in := in.in1 narrow.io.roundingMode := in.rm narrow.io.signedOut := ~in.typ(0) val excSign = in.in1(maxExpWidth + maxSigWidth) && !maxType.isNaN(in.in1) val excOut = Cat(conv.io.signedOut === excSign, Fill(w-1, !excSign)) val invalid = conv.io.intExceptionFlags(2) \|\| narrow.io.intExceptionFlags(1) when (invalid) { toint := Cat(conv.io.out >> w, excOut) } io.out.bits.exc := Cat(invalid, 0.U(3.W), !invalid && conv.io.intExceptionFlags(0)) } } } } io.out.valid := valid io.out.bits.lt := dcmp.io.lt \|\| (dcmp.io.a.asSInt < 0.S && dcmp.io.b.asSInt >= 0.S) io.out.bits.in := in } class IntToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { val io = IO(new Bundle { val in = Flipped(Valid(new IntToFPInput)) val out = Valid(new FPResult) }) val in = Pipe(io.in) val tag = in.bits.typeTagIn val mux = Wire(new FPResult) mux.exc := 0.U mux.data := recode(in.bits.in1, tag) val intValue = { val res = WireDefault(in.bits.in1.asSInt) for (i <- 0 until nIntTypes-1) { val smallInt = in.bits.in1((minXLen << i) - 1, 0) when (in.bits.typ.extract(log2Ceil(nIntTypes), 1) === i.U) { res := Mux(in.bits.typ(0), smallInt.zext, smallInt.asSInt) } } res.asUInt } when (in.bits.wflags) { // fcvt // could be improved for RVD/RVQ with a single variable-position rounding // unit, rather than N fixed-position ones val i2fResults = for (t <- floatTypes) yield { val i2f = Module(new hardfloat.INToRecFN(xLen, t.exp, t.sig)) i2f.io.signedIn := ~in.bits.typ(0) i2f.io.in := intValue i2f.io.roundingMode := in.bits.rm i2f.io.detectTininess := hardfloat.consts.tininess_afterRounding (sanitizeNaN(i2f.io.out, t), i2f.io.exceptionFlags) } val (data, exc) = i2fResults.unzip val dataPadded = data.init.map(d => Cat(data.last >> d.getWidth, d)) :+ data.last mux.data := dataPadded(tag) mux.exc := exc(tag) } io.out <> Pipe(in.valid, mux, latency-1) } class FPToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { val io = IO(new Bundle { val in = Flipped(Valid(new FPInput)) val out = Valid(new FPResult) val lt = Input(Bool()) // from FPToInt }) val in = Pipe(io.in) val signNum = Mux(in.bits.rm(1), in.bits.in1 ^ in.bits.in2, Mux(in.bits.rm(0), ~in.bits.in2, in.bits.in2)) val fsgnj = Cat(signNum(fLen), in.bits.in1(fLen-1, 0)) val fsgnjMux = Wire(new FPResult) fsgnjMux.exc := 0.U fsgnjMux.data := fsgnj when (in.bits.wflags) { // fmin/fmax val isnan1 = maxType.isNaN(in.bits.in1) val isnan2 = maxType.isNaN(in.bits.in2) val isInvalid = maxType.isSNaN(in.bits.in1) \|\| maxType.isSNaN(in.bits.in2) val isNaNOut = isnan1 && isnan2 val isLHS = isnan2 \|\| in.bits.rm(0) =/= io.lt && !isnan1 fsgnjMux.exc := isInvalid << 4 fsgnjMux.data := Mux(isNaNOut, maxType.qNaN, Mux(isLHS, in.bits.in1, in.bits.in2)) } val inTag = in.bits.typeTagIn val outTag = in.bits.typeTagOut val mux = WireDefault(fsgnjMux) for (t <- floatTypes.init) { when (outTag === typeTag(t).U) { mux.data := Cat(fsgnjMux.data >> t.recodedWidth, maxType.unsafeConvert(fsgnjMux.data, t)) } } when (in.bits.wflags && !in.bits.ren2) { // fcvt if (floatTypes.size > 1) { // widening conversions simply canonicalize NaN operands val widened = Mux(maxType.isNaN(in.bits.in1), maxType.qNaN, in.bits.in1) fsgnjMux.data := widened fsgnjMux.exc := maxType.isSNaN(in.bits.in1) << 4 // narrowing conversions require rounding (for RVQ, this could be // optimized to use a single variable-position rounding unit, rather // than two fixed-position ones) for (outType <- floatTypes.init) when (outTag === typeTag(outType).U && ((typeTag(outType) == 0).B \|\| outTag < inTag)) { val narrower = Module(new hardfloat.RecFNToRecFN(maxType.exp, maxType.sig, outType.exp, outType.sig)) narrower.io.in := in.bits.in1 narrower.io.roundingMode := in.bits.rm narrower.io.detectTininess := hardfloat.consts.tininess_afterRounding val narrowed = sanitizeNaN(narrower.io.out, outType) mux.data := Cat(fsgnjMux.data >> narrowed.getWidth, narrowed) mux.exc := narrower.io.exceptionFlags } } } io.out <> Pipe(in.valid, mux, latency-1) } class MulAddRecFNPipe(latency: Int, expWidth: Int, sigWidth: Int) extends Module { override def desiredName = s"MulAddRecFNPipe_l${latency}_e${expWidth}_s${sigWidth}" require(latency<=2) val io = IO(new Bundle { val validin = Input(Bool()) val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) val validout = Output(Bool()) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val mulAddRecFNToRaw_preMul = Module(new hardfloat.MulAddRecFNToRaw_preMul(expWidth, sigWidth)) val mulAddRecFNToRaw_postMul = Module(new hardfloat.MulAddRecFNToRaw_postMul(expWidth, sigWidth)) mulAddRecFNToRaw_preMul.io.op := io.op mulAddRecFNToRaw_preMul.io.a := io.a mulAddRecFNToRaw_preMul.io.b := io.b mulAddRecFNToRaw_preMul.io.c := io.c val mulAddResult = (mulAddRecFNToRaw_preMul.io.mulAddA * mulAddRecFNToRaw_preMul.io.mulAddB) +& mulAddRecFNToRaw_preMul.io.mulAddC val valid_stage0 = Wire(Bool()) val roundingMode_stage0 = Wire(UInt(3.W)) val detectTininess_stage0 = Wire(UInt(1.W)) val postmul_regs = if(latency>0) 1 else 0 mulAddRecFNToRaw_postMul.io.fromPreMul := Pipe(io.validin, mulAddRecFNToRaw_preMul.io.toPostMul, postmul_regs).bits mulAddRecFNToRaw_postMul.io.mulAddResult := Pipe(io.validin, mulAddResult, postmul_regs).bits mulAddRecFNToRaw_postMul.io.roundingMode := Pipe(io.validin, io.roundingMode, postmul_regs).bits roundingMode_stage0 := Pipe(io.validin, io.roundingMode, postmul_regs).bits detectTininess_stage0 := Pipe(io.validin, io.detectTininess, postmul_regs).bits valid_stage0 := Pipe(io.validin, false.B, postmul_regs).valid //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundRawFNToRecFN = Module(new hardfloat.RoundRawFNToRecFN(expWidth, sigWidth, 0)) val round_regs = if(latency==2) 1 else 0 roundRawFNToRecFN.io.invalidExc := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.invalidExc, round_regs).bits roundRawFNToRecFN.io.in := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.rawOut, round_regs).bits roundRawFNToRecFN.io.roundingMode := Pipe(valid_stage0, roundingMode_stage0, round_regs).bits roundRawFNToRecFN.io.detectTininess := Pipe(valid_stage0, detectTininess_stage0, round_regs).bits io.validout := Pipe(valid_stage0, false.B, round_regs).valid roundRawFNToRecFN.io.infiniteExc := false.B io.out := roundRawFNToRecFN.io.out io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags } class FPUFMAPipe(val latency: Int, val t: FType) (implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { override def desiredName = s"FPUFMAPipe_l${latency}_f${t.ieeeWidth}" require(latency>0) val io = IO(new Bundle { val in = Flipped(Valid(new FPInput)) val out = Valid(new FPResult) }) val valid = RegNext(io.in.valid) val in = Reg(new FPInput) when (io.in.valid) { val one = 1.U << (t.sig + t.exp - 1) val zero = (io.in.bits.in1 ^ io.in.bits.in2) & (1.U << (t.sig + t.exp)) val cmd_fma = io.in.bits.ren3 val cmd_addsub = io.in.bits.swap23 in := io.in.bits when (cmd_addsub) { in.in2 := one } when (!(cmd_fma \|\| cmd_addsub)) { in.in3 := zero } } val fma = Module(new MulAddRecFNPipe((latency-1) min 2, t.exp, t.sig)) fma.io.validin := valid fma.io.op := in.fmaCmd fma.io.roundingMode := in.rm fma.io.detectTininess := hardfloat.consts.tininess_afterRounding fma.io.a := in.in1 fma.io.b := in.in2 fma.io.c := in.in3 val res = Wire(new FPResult) res.data := sanitizeNaN(fma.io.out, t) res.exc := fma.io.exceptionFlags io.out := Pipe(fma.io.validout, res, (latency-3) max 0) } class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) { val io = IO(new FPUIO) val (useClockGating, useDebugROB) = coreParams match { case r: RocketCoreParams => val sz = if (r.debugROB.isDefined) r.debugROB.get.size else 1 (r.clockGate, sz < 1) case _ => (false, false) } val clock_en_reg = Reg(Bool()) val clock_en = clock_en_reg \|\| io.cp_req.valid val gated_clock = if (!useClockGating) clock else ClockGate(clock, clock_en, "fpu_clock_gate") val fp_decoder = Module(new FPUDecoder) fp_decoder.io.inst := io.inst val id_ctrl = WireInit(fp_decoder.io.sigs) coreParams match { case r: RocketCoreParams => r.vector.map(v => { val v_decode = v.decoder(p) // Only need to get ren1 v_decode.io.inst := io.inst v_decode.io.vconfig := DontCare // core deals with this when (v_decode.io.legal && v_decode.io.read_frs1) { id_ctrl.ren1 := true.B id_ctrl.swap12 := false.B id_ctrl.toint := true.B id_ctrl.typeTagIn := I id_ctrl.typeTagOut := Mux(io.v_sew === 3.U, D, S) } when (v_decode.io.write_frd) { id_ctrl.wen := true.B } })} val ex_reg_valid = RegNext(io.valid, false.B) val ex_reg_inst = RegEnable(io.inst, io.valid) val ex_reg_ctrl = RegEnable(id_ctrl, io.valid) val ex_ra = List.fill(3)(Reg(UInt())) // load/vector response val load_wb = RegNext(io.ll_resp_val) val load_wb_typeTag = RegEnable(io.ll_resp_type(1,0) - typeTagWbOffset, io.ll_resp_val) val load_wb_data = RegEnable(io.ll_resp_data, io.ll_resp_val) val load_wb_tag = RegEnable(io.ll_resp_tag, io.ll_resp_val) class FPUImpl { // entering gated-clock domain val req_valid = ex_reg_valid \|\| io.cp_req.valid val ex_cp_valid = io.cp_req.fire val mem_cp_valid = RegNext(ex_cp_valid, false.B) val wb_cp_valid = RegNext(mem_cp_valid, false.B) val mem_reg_valid = RegInit(false.B) val killm = (io.killm \|\| io.nack_mem) && !mem_cp_valid // Kill X-stage instruction if M-stage is killed. This prevents it from // speculatively being sent to the div-sqrt unit, which can cause priority // inversion for two back-to-back divides, the first of which is killed. val killx = io.killx \|\| mem_reg_valid && killm mem_reg_valid := ex_reg_valid && !killx \|\| ex_cp_valid val mem_reg_inst = RegEnable(ex_reg_inst, ex_reg_valid) val wb_reg_valid = RegNext(mem_reg_valid && (!killm \|\| mem_cp_valid), false.B) val cp_ctrl = Wire(new FPUCtrlSigs) cp_ctrl :<>= io.cp_req.bits.viewAsSupertype(new FPUCtrlSigs) io.cp_resp.valid := false.B io.cp_resp.bits.data := 0.U io.cp_resp.bits.exc := DontCare val ex_ctrl = Mux(ex_cp_valid, cp_ctrl, ex_reg_ctrl) val mem_ctrl = RegEnable(ex_ctrl, req_valid) val wb_ctrl = RegEnable(mem_ctrl, mem_reg_valid) // CoreMonitorBundle to monitor fp register file writes val frfWriteBundle = Seq.fill(2)(WireInit(new CoreMonitorBundle(xLen, fLen), DontCare)) frfWriteBundle.foreach { i => i.clock := clock i.reset := reset i.hartid := io.hartid i.timer := io.time(31,0) i.valid := false.B i.wrenx := false.B i.wrenf := false.B i.excpt := false.B } // regfile val regfile = Mem(32, Bits((fLen+1).W)) when (load_wb) { val wdata = recode(load_wb_data, load_wb_typeTag) regfile(load_wb_tag) := wdata assert(consistent(wdata)) if (enableCommitLog) printf("f%d p%d 0x%x\n", load_wb_tag, load_wb_tag + 32.U, ieee(wdata)) if (useDebugROB) DebugROB.pushWb(clock, reset, io.hartid, load_wb, load_wb_tag + 32.U, ieee(wdata)) frfWriteBundle(0).wrdst := load_wb_tag frfWriteBundle(0).wrenf := true.B frfWriteBundle(0).wrdata := ieee(wdata) } val ex_rs = ex_ra.map(a => regfile(a)) when (io.valid) { when (id_ctrl.ren1) { when (!id_ctrl.swap12) { ex_ra(0) := io.inst(19,15) } when (id_ctrl.swap12) { ex_ra(1) := io.inst(19,15) } } when (id_ctrl.ren2) { when (id_ctrl.swap12) { ex_ra(0) := io.inst(24,20) } when (id_ctrl.swap23) { ex_ra(2) := io.inst(24,20) } when (!id_ctrl.swap12 && !id_ctrl.swap23) { ex_ra(1) := io.inst(24,20) } } when (id_ctrl.ren3) { ex_ra(2) := io.inst(31,27) } } val ex_rm = Mux(ex_reg_inst(14,12) === 7.U, io.fcsr_rm, ex_reg_inst(14,12)) def fuInput(minT: Option[FType]): FPInput = { val req = Wire(new FPInput) val tag = ex_ctrl.typeTagIn req.viewAsSupertype(new Bundle with HasFPUCtrlSigs) :#= ex_ctrl.viewAsSupertype(new Bundle with HasFPUCtrlSigs) req.rm := ex_rm req.in1 := unbox(ex_rs(0), tag, minT) req.in2 := unbox(ex_rs(1), tag, minT) req.in3 := unbox(ex_rs(2), tag, minT) req.typ := ex_reg_inst(21,20) req.fmt := ex_reg_inst(26,25) req.fmaCmd := ex_reg_inst(3,2) \| (!ex_ctrl.ren3 && ex_reg_inst(27)) when (ex_cp_valid) { req := io.cp_req.bits when (io.cp_req.bits.swap12) { req.in1 := io.cp_req.bits.in2 req.in2 := io.cp_req.bits.in1 } when (io.cp_req.bits.swap23) { req.in2 := io.cp_req.bits.in3 req.in3 := io.cp_req.bits.in2 } } req } val sfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.S)) sfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === S sfma.io.in.bits := fuInput(Some(sfma.t)) val fpiu = Module(new FPToInt) fpiu.io.in.valid := req_valid && (ex_ctrl.toint \|\| ex_ctrl.div \|\| ex_ctrl.sqrt \|\| (ex_ctrl.fastpipe && ex_ctrl.wflags)) fpiu.io.in.bits := fuInput(None) io.store_data := fpiu.io.out.bits.store io.toint_data := fpiu.io.out.bits.toint when(fpiu.io.out.valid && mem_cp_valid && mem_ctrl.toint){ io.cp_resp.bits.data := fpiu.io.out.bits.toint io.cp_resp.valid := true.B } val ifpu = Module(new IntToFP(cfg.ifpuLatency)) ifpu.io.in.valid := req_valid && ex_ctrl.fromint ifpu.io.in.bits := fpiu.io.in.bits ifpu.io.in.bits.in1 := Mux(ex_cp_valid, io.cp_req.bits.in1, io.fromint_data) val fpmu = Module(new FPToFP(cfg.fpmuLatency)) fpmu.io.in.valid := req_valid && ex_ctrl.fastpipe fpmu.io.in.bits := fpiu.io.in.bits fpmu.io.lt := fpiu.io.out.bits.lt val divSqrt_wen = WireDefault(false.B) val divSqrt_inFlight = WireDefault(false.B) val divSqrt_waddr = Reg(UInt(5.W)) val divSqrt_cp = Reg(Bool()) val divSqrt_typeTag = Wire(UInt(log2Up(floatTypes.size).W)) val divSqrt_wdata = Wire(UInt((fLen+1).W)) val divSqrt_flags = Wire(UInt(FPConstants.FLAGS_SZ.W)) divSqrt_typeTag := DontCare divSqrt_wdata := DontCare divSqrt_flags := DontCare // writeback arbitration case class Pipe(p: Module, lat: Int, cond: (FPUCtrlSigs) => Bool, res: FPResult) val pipes = List( Pipe(fpmu, fpmu.latency, (c: FPUCtrlSigs) => c.fastpipe, fpmu.io.out.bits), Pipe(ifpu, ifpu.latency, (c: FPUCtrlSigs) => c.fromint, ifpu.io.out.bits), Pipe(sfma, sfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === S, sfma.io.out.bits)) ++ (fLen > 32).option({ val dfma = Module(new FPUFMAPipe(cfg.dfmaLatency, FType.D)) dfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === D dfma.io.in.bits := fuInput(Some(dfma.t)) Pipe(dfma, dfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === D, dfma.io.out.bits) }) ++ (minFLen == 16).option({ val hfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.H)) hfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === H hfma.io.in.bits := fuInput(Some(hfma.t)) Pipe(hfma, hfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === H, hfma.io.out.bits) }) def latencyMask(c: FPUCtrlSigs, offset: Int) = { require(pipes.forall(_.lat >= offset)) pipes.map(p => Mux(p.cond(c), (1 << p.lat-offset).U, 0.U)).reduce(_\|_) } def pipeid(c: FPUCtrlSigs) = pipes.zipWithIndex.map(p => Mux(p._1.cond(c), p._2.U, 0.U)).reduce(_\|_) val maxLatency = pipes.map(_.lat).max val memLatencyMask = latencyMask(mem_ctrl, 2) class WBInfo extends Bundle { val rd = UInt(5.W) val typeTag = UInt(log2Up(floatTypes.size).W) val cp = Bool() val pipeid = UInt(log2Ceil(pipes.size).W) } val wen = RegInit(0.U((maxLatency-1).W)) val wbInfo = Reg(Vec(maxLatency-1, new WBInfo)) val mem_wen = mem_reg_valid && (mem_ctrl.fma \|\| mem_ctrl.fastpipe \|\| mem_ctrl.fromint) val write_port_busy = RegEnable(mem_wen && (memLatencyMask & latencyMask(ex_ctrl, 1)).orR \|\| (wen & latencyMask(ex_ctrl, 0)).orR, req_valid) ccover(mem_reg_valid && write_port_busy, "WB_STRUCTURAL", "structural hazard on writeback") for (i <- 0 until maxLatency-2) { when (wen(i+1)) { wbInfo(i) := wbInfo(i+1) } } wen := wen >> 1 when (mem_wen) { when (!killm) { wen := wen >> 1 \| memLatencyMask } for (i <- 0 until maxLatency-1) { when (!write_port_busy && memLatencyMask(i)) { wbInfo(i).cp := mem_cp_valid wbInfo(i).typeTag := mem_ctrl.typeTagOut wbInfo(i).pipeid := pipeid(mem_ctrl) wbInfo(i).rd := mem_reg_inst(11,7) } } } val waddr = Mux(divSqrt_wen, divSqrt_waddr, wbInfo(0).rd) val wb_cp = Mux(divSqrt_wen, divSqrt_cp, wbInfo(0).cp) val wtypeTag = Mux(divSqrt_wen, divSqrt_typeTag, wbInfo(0).typeTag) val wdata = box(Mux(divSqrt_wen, divSqrt_wdata, (pipes.map(_.res.data): Seq[UInt])(wbInfo(0).pipeid)), wtypeTag) val wexc = (pipes.map(_.res.exc): Seq[UInt])(wbInfo(0).pipeid) when ((!wbInfo(0).cp && wen(0)) \|\| divSqrt_wen) { assert(consistent(wdata)) regfile(waddr) := wdata if (enableCommitLog) { printf("f%d p%d 0x%x\n", waddr, waddr + 32.U, ieee(wdata)) } frfWriteBundle(1).wrdst := waddr frfWriteBundle(1).wrenf := true.B frfWriteBundle(1).wrdata := ieee(wdata) } if (useDebugROB) { DebugROB.pushWb(clock, reset, io.hartid, (!wbInfo(0).cp && wen(0)) \|\| divSqrt_wen, waddr + 32.U, ieee(wdata)) } when (wb_cp && (wen(0) \|\| divSqrt_wen)) { io.cp_resp.bits.data := wdata io.cp_resp.valid := true.B } assert(!io.cp_req.valid \|\| pipes.forall(_.lat == pipes.head.lat).B, s"FPU only supports coprocessor if FMA pipes have uniform latency ${pipes.map(_.lat)}") // Avoid structural hazards and nacking of external requests // toint responds in the MEM stage, so an incoming toint can induce a structural hazard against inflight FMAs io.cp_req.ready := !ex_reg_valid && !(cp_ctrl.toint && wen =/= 0.U) && !divSqrt_inFlight val wb_toint_valid = wb_reg_valid && wb_ctrl.toint val wb_toint_exc = RegEnable(fpiu.io.out.bits.exc, mem_ctrl.toint) io.fcsr_flags.valid := wb_toint_valid \|\| divSqrt_wen \|\| wen(0) io.fcsr_flags.bits := Mux(wb_toint_valid, wb_toint_exc, 0.U) \| Mux(divSqrt_wen, divSqrt_flags, 0.U) \| Mux(wen(0), wexc, 0.U) val divSqrt_write_port_busy = (mem_ctrl.div \|\| mem_ctrl.sqrt) && wen.orR io.fcsr_rdy := !(ex_reg_valid && ex_ctrl.wflags \|\| mem_reg_valid && mem_ctrl.wflags \|\| wb_reg_valid && wb_ctrl.toint \|\| wen.orR \|\| divSqrt_inFlight) io.nack_mem := (write_port_busy \|\| divSqrt_write_port_busy \|\| divSqrt_inFlight) && !mem_cp_valid io.dec <> id_ctrl def useScoreboard(f: ((Pipe, Int)) => Bool) = pipes.zipWithIndex.filter(_._1.lat > 3).map(x => f(x)).fold(false.B)(_\|\|_) io.sboard_set := wb_reg_valid && !wb_cp_valid && RegNext(useScoreboard(_._1.cond(mem_ctrl)) \|\| mem_ctrl.div \|\| mem_ctrl.sqrt \|\| mem_ctrl.vec) io.sboard_clr := !wb_cp_valid && (divSqrt_wen \|\| (wen(0) && useScoreboard(x => wbInfo(0).pipeid === x._2.U))) io.sboard_clra := waddr ccover(io.sboard_clr && load_wb, "DUAL_WRITEBACK", "load and FMA writeback on same cycle") // we don't currently support round-max-magnitude (rm=4) io.illegal_rm := io.inst(14,12).isOneOf(5.U, 6.U) \|\| io.inst(14,12) === 7.U && io.fcsr_rm >= 5.U if (cfg.divSqrt) { val divSqrt_inValid = mem_reg_valid && (mem_ctrl.div \|\| mem_ctrl.sqrt) && !divSqrt_inFlight val divSqrt_killed = RegNext(divSqrt_inValid && killm, true.B) when (divSqrt_inValid) { divSqrt_waddr := mem_reg_inst(11,7) divSqrt_cp := mem_cp_valid } ccover(divSqrt_inFlight && divSqrt_killed, "DIV_KILLED", "divide killed after issued to divider") ccover(divSqrt_inFlight && mem_reg_valid && (mem_ctrl.div \|\| mem_ctrl.sqrt), "DIV_BUSY", "divider structural hazard") ccover(mem_reg_valid && divSqrt_write_port_busy, "DIV_WB_STRUCTURAL", "structural hazard on division writeback") for (t <- floatTypes) { val tag = mem_ctrl.typeTagOut val divSqrt = withReset(divSqrt_killed) { Module(new hardfloat.DivSqrtRecFN_small(t.exp, t.sig, 0)) } divSqrt.io.inValid := divSqrt_inValid && tag === typeTag(t).U divSqrt.io.sqrtOp := mem_ctrl.sqrt divSqrt.io.a := maxType.unsafeConvert(fpiu.io.out.bits.in.in1, t) divSqrt.io.b := maxType.unsafeConvert(fpiu.io.out.bits.in.in2, t) divSqrt.io.roundingMode := fpiu.io.out.bits.in.rm divSqrt.io.detectTininess := hardfloat.consts.tininess_afterRounding when (!divSqrt.io.inReady) { divSqrt_inFlight := true.B } // only 1 in flight when (divSqrt.io.outValid_div \|\| divSqrt.io.outValid_sqrt) { divSqrt_wen := !divSqrt_killed divSqrt_wdata := sanitizeNaN(divSqrt.io.out, t) divSqrt_flags := divSqrt.io.exceptionFlags divSqrt_typeTag := typeTag(t).U } } when (divSqrt_killed) { divSqrt_inFlight := false.B } } else { when (id_ctrl.div \|\| id_ctrl.sqrt) { io.illegal_rm := true.B } } // gate the clock clock_en_reg := !useClockGating.B \|\| io.keep_clock_enabled \|\| // chicken bit io.valid \|\| // ID stage req_valid \|\| // EX stage mem_reg_valid \|\| mem_cp_valid \|\| // MEM stage wb_reg_valid \|\| wb_cp_valid \|\| // WB stage wen.orR \|\| divSqrt_inFlight \|\| // post-WB stage io.ll_resp_val // load writeback } // leaving gated-clock domain val fpuImpl = withClock (gated_clock) { new FPUImpl } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = property.cover(cond, s"FPU_$label", "Core;;" + desc) } File util.scala: //**************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v3.common.{MicroOp} import boom.v3.exu.{BrUpdateInfo} / * Object to XOR fold a input register of fullLength into a compressedLength. / object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /* * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks / object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask) } def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) } } /* * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. / object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /* * Object to return a BR mask given a MicroOp mask and old BR mask. / object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask) out } } /* * Object to check if at least 1 bit matches in two masks / object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /* * Object to clear one bit in a mask given an index / object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /* * Object to shift a register over by one bit and concat a new one / object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /* * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. / object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /* * Object to increment an input value, wrapping it if * necessary. / object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /* * Object to decrement an input value, wrapping it if * necessary. / object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /* * Object to increment an input value, wrapping it if * necessary. / object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /* * Object to decrement an input value, wrapping it if * necessary. / object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /* * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. / object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc \| (b-1).U) } } /* * Object to rotate a signal left by one / object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /* * Object to sext a value to a particular length. / object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /* * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. / object ImmGen { import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U} def apply(ip: UInt, isel: UInt): SInt = { val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U \|\| isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J \|\| isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S \|\| isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt } } /* * Object to get the FP rounding mode out of a packed immediate. / object ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } } /* * Object to get the FP function fype from a packed immediate. * Note: only works if !(IS_B or IS_S) / object ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } } /* * Object to see if an instruction is a JALR. / object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /* * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). / object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /* * Object to return the lowest bit position after the head. / object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /* * Object to determine whether queue * index i0 is older than index i1. / object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } /* * Set all bits at or below the highest order '1'. / object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_\|_) } } /* * Set all bits at or above the lowest order '1'. / object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_\|_) } } /* * Transpose a matrix of Chisel Vecs. / object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /* * N-wide one-hot priority encoder. / object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /* * Connect the first k of n valid input interfaces to k output interfaces. / class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_\|\|_)) val out_valids = sels map (col => col.reduce(_\|\|_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /* * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). / class BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v3.common.BoomModule()(p) with boom.v3.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire) val do_deq = WireInit((io.deq.ready \|\| !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop) uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop)) io.deq.bits := out io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop) // For flow queue behavior. if (flow) { when (io.empty) { io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop) io.deq.bits := io.enq.bits io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) do_deq := false.B when (io.deq.ready) { do_enq := false.B } } } private val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /* * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" / def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) / def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) / def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) / def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /* * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) / def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /* * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) / def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /* * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line / def apply(strs: String)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } File functional-unit.scala: //**************************************************************************** // Copyright (c) 2013 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Functional Units //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // // If regfile bypassing is disabled, then the functional unit must do its own // bypassing in here on the WB stage (i.e., bypassing the io.resp.data) // // TODO: explore possibility of conditional IO fields? if a branch unit... how to add extra to IO in subclass? package boom.v3.exu import chisel3._ import chisel3.util._ import chisel3.experimental.dataview._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ import freechips.rocketchip.tile import freechips.rocketchip.rocket.{PipelinedMultiplier,BP,BreakpointUnit,Causes,CSR} import boom.v3.common._ import boom.v3.ifu._ import boom.v3.util._ /t * Functional unit constants / object FUConstants { // bit mask, since a given execution pipeline may support multiple functional units val FUC_SZ = 10 val FU_X = BitPat.dontCare(FUC_SZ) val FU_ALU = 1.U(FUC_SZ.W) val FU_JMP = 2.U(FUC_SZ.W) val FU_MEM = 4.U(FUC_SZ.W) val FU_MUL = 8.U(FUC_SZ.W) val FU_DIV = 16.U(FUC_SZ.W) val FU_CSR = 32.U(FUC_SZ.W) val FU_FPU = 64.U(FUC_SZ.W) val FU_FDV = 128.U(FUC_SZ.W) val FU_I2F = 256.U(FUC_SZ.W) val FU_F2I = 512.U(FUC_SZ.W) // FP stores generate data through FP F2I, and generate address through MemAddrCalc val FU_F2IMEM = 516.U(FUC_SZ.W) } import FUConstants._ /* * Class to tell the FUDecoders what units it needs to support * * @param alu support alu unit? * @param bru support br unit? * @param mem support mem unit? * @param muld support multiple div unit? * @param fpu support FP unit? * @param csr support csr writing unit? * @param fdiv support FP div unit? * @param ifpu support int to FP unit? / class SupportedFuncUnits( val alu: Boolean = false, val jmp: Boolean = false, val mem: Boolean = false, val muld: Boolean = false, val fpu: Boolean = false, val csr: Boolean = false, val fdiv: Boolean = false, val ifpu: Boolean = false) { } /* * Bundle for signals sent to the functional unit * * @param dataWidth width of the data sent to the functional unit / class FuncUnitReq(val dataWidth: Int)(implicit p: Parameters) extends BoomBundle with HasBoomUOP { val numOperands = 3 val rs1_data = UInt(dataWidth.W) val rs2_data = UInt(dataWidth.W) val rs3_data = UInt(dataWidth.W) // only used for FMA units val pred_data = Bool() val kill = Bool() // kill everything } /* * Bundle for the signals sent out of the function unit * * @param dataWidth data sent from the functional unit / class FuncUnitResp(val dataWidth: Int)(implicit p: Parameters) extends BoomBundle with HasBoomUOP { val predicated = Bool() // Was this response from a predicated-off instruction val data = UInt(dataWidth.W) val fflags = new ValidIO(new FFlagsResp) val addr = UInt((vaddrBits+1).W) // only for maddr -> LSU val mxcpt = new ValidIO(UInt((freechips.rocketchip.rocket.Causes.all.max+2).W)) //only for maddr->LSU val sfence = Valid(new freechips.rocketchip.rocket.SFenceReq) // only for mcalc } /* * Branch resolution information given from the branch unit / class BrResolutionInfo(implicit p: Parameters) extends BoomBundle { val uop = new MicroOp val valid = Bool() val mispredict = Bool() val taken = Bool() // which direction did the branch go? val cfi_type = UInt(CFI_SZ.W) // Info for recalculating the pc for this branch val pc_sel = UInt(2.W) val jalr_target = UInt(vaddrBitsExtended.W) val target_offset = SInt() } class BrUpdateInfo(implicit p: Parameters) extends BoomBundle { // On the first cycle we get masks to kill registers val b1 = new BrUpdateMasks // On the second cycle we get indices to reset pointers val b2 = new BrResolutionInfo } class BrUpdateMasks(implicit p: Parameters) extends BoomBundle { val resolve_mask = UInt(maxBrCount.W) val mispredict_mask = UInt(maxBrCount.W) } /* * Abstract top level functional unit class that wraps a lower level hand made functional unit * * @param isPipelined is the functional unit pipelined? * @param numStages how many pipeline stages does the functional unit have * @param numBypassStages how many bypass stages does the function unit have * @param dataWidth width of the data being operated on in the functional unit * @param hasBranchUnit does this functional unit have a branch unit? / abstract class FunctionalUnit( val isPipelined: Boolean, val numStages: Int, val numBypassStages: Int, val dataWidth: Int, val isJmpUnit: Boolean = false, val isAluUnit: Boolean = false, val isMemAddrCalcUnit: Boolean = false, val needsFcsr: Boolean = false) (implicit p: Parameters) extends BoomModule { val io = IO(new Bundle { val req = Flipped(new DecoupledIO(new FuncUnitReq(dataWidth))) val resp = (new DecoupledIO(new FuncUnitResp(dataWidth))) val brupdate = Input(new BrUpdateInfo()) val bypass = Output(Vec(numBypassStages, Valid(new ExeUnitResp(dataWidth)))) // only used by the fpu unit val fcsr_rm = if (needsFcsr) Input(UInt(tile.FPConstants.RM_SZ.W)) else null // only used by branch unit val brinfo = if (isAluUnit) Output(new BrResolutionInfo()) else null val get_ftq_pc = if (isJmpUnit) Flipped(new GetPCFromFtqIO()) else null val status = if (isMemAddrCalcUnit) Input(new freechips.rocketchip.rocket.MStatus()) else null // only used by memaddr calc unit val bp = if (isMemAddrCalcUnit) Input(Vec(nBreakpoints, new BP)) else null val mcontext = if (isMemAddrCalcUnit) Input(UInt(coreParams.mcontextWidth.W)) else null val scontext = if (isMemAddrCalcUnit) Input(UInt(coreParams.scontextWidth.W)) else null }) io.bypass.foreach { b => b.valid := false.B; b.bits := DontCare } io.resp.valid := false.B io.resp.bits := DontCare if (isJmpUnit) { io.get_ftq_pc.ftq_idx := DontCare } } /* * Abstract top level pipelined functional unit * * Note: this helps track which uops get killed while in intermediate stages, * but it is the job of the consumer to check for kills on the same cycle as consumption!!! * * @param numStages how many pipeline stages does the functional unit have * @param numBypassStages how many bypass stages does the function unit have * @param earliestBypassStage first stage that you can start bypassing from * @param dataWidth width of the data being operated on in the functional unit * @param hasBranchUnit does this functional unit have a branch unit? / abstract class PipelinedFunctionalUnit( numStages: Int, numBypassStages: Int, earliestBypassStage: Int, dataWidth: Int, isJmpUnit: Boolean = false, isAluUnit: Boolean = false, isMemAddrCalcUnit: Boolean = false, needsFcsr: Boolean = false )(implicit p: Parameters) extends FunctionalUnit( isPipelined = true, numStages = numStages, numBypassStages = numBypassStages, dataWidth = dataWidth, isJmpUnit = isJmpUnit, isAluUnit = isAluUnit, isMemAddrCalcUnit = isMemAddrCalcUnit, needsFcsr = needsFcsr) { // Pipelined functional unit is always ready. io.req.ready := true.B if (numStages > 0) { val r_valids = RegInit(VecInit(Seq.fill(numStages) { false.B })) val r_uops = Reg(Vec(numStages, new MicroOp())) // handle incoming request r_valids(0) := io.req.valid && !IsKilledByBranch(io.brupdate, io.req.bits.uop) && !io.req.bits.kill r_uops(0) := io.req.bits.uop r_uops(0).br_mask := GetNewBrMask(io.brupdate, io.req.bits.uop) // handle middle of the pipeline for (i <- 1 until numStages) { r_valids(i) := r_valids(i-1) && !IsKilledByBranch(io.brupdate, r_uops(i-1)) && !io.req.bits.kill r_uops(i) := r_uops(i-1) r_uops(i).br_mask := GetNewBrMask(io.brupdate, r_uops(i-1)) if (numBypassStages > 0) { io.bypass(i-1).bits.uop := r_uops(i-1) } } // handle outgoing (branch could still kill it) // consumer must also check for pipeline flushes (kills) io.resp.valid := r_valids(numStages-1) && !IsKilledByBranch(io.brupdate, r_uops(numStages-1)) io.resp.bits.predicated := false.B io.resp.bits.uop := r_uops(numStages-1) io.resp.bits.uop.br_mask := GetNewBrMask(io.brupdate, r_uops(numStages-1)) // bypassing (TODO allow bypass vector to have a different size from numStages) if (numBypassStages > 0 && earliestBypassStage == 0) { io.bypass(0).bits.uop := io.req.bits.uop for (i <- 1 until numBypassStages) { io.bypass(i).bits.uop := r_uops(i-1) } } } else { require (numStages == 0) // pass req straight through to response // valid doesn't check kill signals, let consumer deal with it. // The LSU already handles it and this hurts critical path. io.resp.valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.req.bits.uop) io.resp.bits.predicated := false.B io.resp.bits.uop := io.req.bits.uop io.resp.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.req.bits.uop) } } /* * Functional unit that wraps RocketChips ALU * * @param isBranchUnit is this a branch unit? * @param numStages how many pipeline stages does the functional unit have * @param dataWidth width of the data being operated on in the functional unit / class ALUUnit(isJmpUnit: Boolean = false, numStages: Int = 1, dataWidth: Int)(implicit p: Parameters) extends PipelinedFunctionalUnit( numStages = numStages, numBypassStages = numStages, isAluUnit = true, earliestBypassStage = 0, dataWidth = dataWidth, isJmpUnit = isJmpUnit) with boom.v3.ifu.HasBoomFrontendParameters { val uop = io.req.bits.uop // immediate generation val imm_xprlen = ImmGen(uop.imm_packed, uop.ctrl.imm_sel) // operand 1 select var op1_data: UInt = null if (isJmpUnit) { // Get the uop PC for jumps val block_pc = AlignPCToBoundary(io.get_ftq_pc.pc, icBlockBytes) val uop_pc = (block_pc \| uop.pc_lob) - Mux(uop.edge_inst, 2.U, 0.U) op1_data = Mux(uop.ctrl.op1_sel.asUInt === OP1_RS1 , io.req.bits.rs1_data, Mux(uop.ctrl.op1_sel.asUInt === OP1_PC , Sext(uop_pc, xLen), 0.U)) } else { op1_data = Mux(uop.ctrl.op1_sel.asUInt === OP1_RS1 , io.req.bits.rs1_data, 0.U) } // operand 2 select val op2_data = Mux(uop.ctrl.op2_sel === OP2_IMM, Sext(imm_xprlen.asUInt, xLen), Mux(uop.ctrl.op2_sel === OP2_IMMC, io.req.bits.uop.prs1(4,0), Mux(uop.ctrl.op2_sel === OP2_RS2 , io.req.bits.rs2_data, Mux(uop.ctrl.op2_sel === OP2_NEXT, Mux(uop.is_rvc, 2.U, 4.U), 0.U)))) val alu = Module(new freechips.rocketchip.rocket.ALU()) alu.io.in1 := op1_data.asUInt alu.io.in2 := op2_data.asUInt alu.io.fn := uop.ctrl.op_fcn alu.io.dw := uop.ctrl.fcn_dw // Did I just get killed by the previous cycle's branch, // or by a flush pipeline? val killed = WireInit(false.B) when (io.req.bits.kill \|\| IsKilledByBranch(io.brupdate, uop)) { killed := true.B } val rs1 = io.req.bits.rs1_data val rs2 = io.req.bits.rs2_data val br_eq = (rs1 === rs2) val br_ltu = (rs1.asUInt < rs2.asUInt) val br_lt = (~(rs1(xLen-1) ^ rs2(xLen-1)) & br_ltu \| rs1(xLen-1) & ~rs2(xLen-1)).asBool val pc_sel = MuxLookup(uop.ctrl.br_type, PC_PLUS4)( Seq( BR_N -> PC_PLUS4, BR_NE -> Mux(!br_eq, PC_BRJMP, PC_PLUS4), BR_EQ -> Mux( br_eq, PC_BRJMP, PC_PLUS4), BR_GE -> Mux(!br_lt, PC_BRJMP, PC_PLUS4), BR_GEU -> Mux(!br_ltu, PC_BRJMP, PC_PLUS4), BR_LT -> Mux( br_lt, PC_BRJMP, PC_PLUS4), BR_LTU -> Mux( br_ltu, PC_BRJMP, PC_PLUS4), BR_J -> PC_BRJMP, BR_JR -> PC_JALR )) val is_taken = io.req.valid && !killed && (uop.is_br \|\| uop.is_jalr \|\| uop.is_jal) && (pc_sel =/= PC_PLUS4) // "mispredict" means that a branch has been resolved and it must be killed val mispredict = WireInit(false.B) val is_br = io.req.valid && !killed && uop.is_br && !uop.is_sfb val is_jal = io.req.valid && !killed && uop.is_jal val is_jalr = io.req.valid && !killed && uop.is_jalr when (is_br \|\| is_jalr) { if (!isJmpUnit) { assert (pc_sel =/= PC_JALR) } when (pc_sel === PC_PLUS4) { mispredict := uop.taken } when (pc_sel === PC_BRJMP) { mispredict := !uop.taken } } val brinfo = Wire(new BrResolutionInfo) // note: jal doesn't allocate a branch-mask, so don't clear a br-mask bit brinfo.valid := is_br \|\| is_jalr brinfo.mispredict := mispredict brinfo.uop := uop brinfo.cfi_type := Mux(is_jalr, CFI_JALR, Mux(is_br , CFI_BR, CFI_X)) brinfo.taken := is_taken brinfo.pc_sel := pc_sel brinfo.jalr_target := DontCare // Branch/Jump Target Calculation // For jumps we read the FTQ, and can calculate the target // For branches we emit the offset for the core to redirect if necessary val target_offset = imm_xprlen(20,0).asSInt brinfo.jalr_target := DontCare if (isJmpUnit) { def encodeVirtualAddress(a0: UInt, ea: UInt) = if (vaddrBitsExtended == vaddrBits) { ea } else { // Efficient means to compress 64-bit VA into vaddrBits+1 bits. // (VA is bad if VA(vaddrBits) != VA(vaddrBits-1)). val a = a0.asSInt >> vaddrBits val msb = Mux(a === 0.S \|\| a === -1.S, ea(vaddrBits), !ea(vaddrBits-1)) Cat(msb, ea(vaddrBits-1,0)) } val jalr_target_base = io.req.bits.rs1_data.asSInt val jalr_target_xlen = Wire(UInt(xLen.W)) jalr_target_xlen := (jalr_target_base + target_offset).asUInt val jalr_target = (encodeVirtualAddress(jalr_target_xlen, jalr_target_xlen).asSInt & -2.S).asUInt brinfo.jalr_target := jalr_target val cfi_idx = ((uop.pc_lob ^ Mux(io.get_ftq_pc.entry.start_bank === 1.U, 1.U << log2Ceil(bankBytes), 0.U)))(log2Ceil(fetchWidth),1) when (pc_sel === PC_JALR) { mispredict := !io.get_ftq_pc.next_val \|\| (io.get_ftq_pc.next_pc =/= jalr_target) \|\| !io.get_ftq_pc.entry.cfi_idx.valid \|\| (io.get_ftq_pc.entry.cfi_idx.bits =/= cfi_idx) } } brinfo.target_offset := target_offset io.brinfo := brinfo // Response // TODO add clock gate on resp bits from functional units // io.resp.bits.data := RegEnable(alu.io.out, io.req.valid) // val reg_data = Reg(outType = Bits(width = xLen)) // reg_data := alu.io.out // io.resp.bits.data := reg_data val r_val = RegInit(VecInit(Seq.fill(numStages) { false.B })) val r_data = Reg(Vec(numStages, UInt(xLen.W))) val r_pred = Reg(Vec(numStages, Bool())) val alu_out = Mux(io.req.bits.uop.is_sfb_shadow && io.req.bits.pred_data, Mux(io.req.bits.uop.ldst_is_rs1, io.req.bits.rs1_data, io.req.bits.rs2_data), Mux(io.req.bits.uop.uopc === uopMOV, io.req.bits.rs2_data, alu.io.out)) r_val (0) := io.req.valid r_data(0) := Mux(io.req.bits.uop.is_sfb_br, pc_sel === PC_BRJMP, alu_out) r_pred(0) := io.req.bits.uop.is_sfb_shadow && io.req.bits.pred_data for (i <- 1 until numStages) { r_val(i) := r_val(i-1) r_data(i) := r_data(i-1) r_pred(i) := r_pred(i-1) } io.resp.bits.data := r_data(numStages-1) io.resp.bits.predicated := r_pred(numStages-1) // Bypass // for the ALU, we can bypass same cycle as compute require (numStages >= 1) require (numBypassStages >= 1) io.bypass(0).valid := io.req.valid io.bypass(0).bits.data := Mux(io.req.bits.uop.is_sfb_br, pc_sel === PC_BRJMP, alu_out) for (i <- 1 until numStages) { io.bypass(i).valid := r_val(i-1) io.bypass(i).bits.data := r_data(i-1) } // Exceptions io.resp.bits.fflags.valid := false.B } /* * Functional unit that passes in base+imm to calculate addresses, and passes store data * to the LSU. * For floating point, 65bit FP store-data needs to be decoded into 64bit FP form / class MemAddrCalcUnit(implicit p: Parameters) extends PipelinedFunctionalUnit( numStages = 0, numBypassStages = 0, earliestBypassStage = 0, dataWidth = 65, // TODO enable this only if FP is enabled? isMemAddrCalcUnit = true) with freechips.rocketchip.rocket.constants.MemoryOpConstants with freechips.rocketchip.rocket.constants.ScalarOpConstants { // perform address calculation val sum = (io.req.bits.rs1_data.asSInt + io.req.bits.uop.imm_packed(19,8).asSInt).asUInt val ea_sign = Mux(sum(vaddrBits-1), ~sum(63,vaddrBits) === 0.U, sum(63,vaddrBits) =/= 0.U) val effective_address = Cat(ea_sign, sum(vaddrBits-1,0)).asUInt val store_data = io.req.bits.rs2_data io.resp.bits.addr := effective_address io.resp.bits.data := store_data if (dataWidth > 63) { assert (!(io.req.valid && io.req.bits.uop.ctrl.is_std && io.resp.bits.data(64).asBool === true.B), "65th bit set in MemAddrCalcUnit.") assert (!(io.req.valid && io.req.bits.uop.ctrl.is_std && io.req.bits.uop.fp_val), "FP store-data should now be going through a different unit.") } assert (!(io.req.bits.uop.fp_val && io.req.valid && io.req.bits.uop.uopc =/= uopLD && io.req.bits.uop.uopc =/= uopSTA), "[maddrcalc] assert we never get store data in here.") // Handle misaligned exceptions val size = io.req.bits.uop.mem_size val misaligned = (size === 1.U && (effective_address(0) =/= 0.U)) \|\| (size === 2.U && (effective_address(1,0) =/= 0.U)) \|\| (size === 3.U && (effective_address(2,0) =/= 0.U)) val bkptu = Module(new BreakpointUnit(nBreakpoints)) bkptu.io.status := io.status bkptu.io.bp := io.bp bkptu.io.pc := DontCare bkptu.io.ea := effective_address bkptu.io.mcontext := io.mcontext bkptu.io.scontext := io.scontext val ma_ld = io.req.valid && io.req.bits.uop.uopc === uopLD && misaligned val ma_st = io.req.valid && (io.req.bits.uop.uopc === uopSTA \|\| io.req.bits.uop.uopc === uopAMO_AG) && misaligned val dbg_bp = io.req.valid && ((io.req.bits.uop.uopc === uopLD && bkptu.io.debug_ld) \|\| (io.req.bits.uop.uopc === uopSTA && bkptu.io.debug_st)) val bp = io.req.valid && ((io.req.bits.uop.uopc === uopLD && bkptu.io.xcpt_ld) \|\| (io.req.bits.uop.uopc === uopSTA && bkptu.io.xcpt_st)) def checkExceptions(x: Seq[(Bool, UInt)]) = (x.map(_._1).reduce(_\|\|_), PriorityMux(x)) val (xcpt_val, xcpt_cause) = checkExceptions(List( (ma_ld, (Causes.misaligned_load).U), (ma_st, (Causes.misaligned_store).U), (dbg_bp, (CSR.debugTriggerCause).U), (bp, (Causes.breakpoint).U))) io.resp.bits.mxcpt.valid := xcpt_val io.resp.bits.mxcpt.bits := xcpt_cause assert (!(ma_ld && ma_st), "Mutually-exclusive exceptions are firing.") io.resp.bits.sfence.valid := io.req.valid && io.req.bits.uop.mem_cmd === M_SFENCE io.resp.bits.sfence.bits.rs1 := io.req.bits.uop.mem_size(0) io.resp.bits.sfence.bits.rs2 := io.req.bits.uop.mem_size(1) io.resp.bits.sfence.bits.addr := io.req.bits.rs1_data io.resp.bits.sfence.bits.asid := io.req.bits.rs2_data } /* * Functional unit to wrap lower level FPU * * Currently, bypassing is unsupported! * All FP instructions are padded out to the max latency unit for easy * write-port scheduling. / class FPUUnit(implicit p: Parameters) extends PipelinedFunctionalUnit( numStages = p(tile.TileKey).core.fpu.get.dfmaLatency, numBypassStages = 0, earliestBypassStage = 0, dataWidth = 65, needsFcsr = true) { val fpu = Module(new FPU()) fpu.io.req.valid := io.req.valid fpu.io.req.bits.uop := io.req.bits.uop fpu.io.req.bits.rs1_data := io.req.bits.rs1_data fpu.io.req.bits.rs2_data := io.req.bits.rs2_data fpu.io.req.bits.rs3_data := io.req.bits.rs3_data fpu.io.req.bits.fcsr_rm := io.fcsr_rm io.resp.bits.data := fpu.io.resp.bits.data io.resp.bits.fflags.valid := fpu.io.resp.bits.fflags.valid io.resp.bits.fflags.bits.uop := io.resp.bits.uop io.resp.bits.fflags.bits.flags := fpu.io.resp.bits.fflags.bits.flags // kill me now } /* * Int to FP conversion functional unit * * @param latency the amount of stages to delay by / class IntToFPUnit(latency: Int)(implicit p: Parameters) extends PipelinedFunctionalUnit( numStages = latency, numBypassStages = 0, earliestBypassStage = 0, dataWidth = 65, needsFcsr = true) with tile.HasFPUParameters { val fp_decoder = Module(new UOPCodeFPUDecoder) // TODO use a simpler decoder val io_req = io.req.bits fp_decoder.io.uopc := io_req.uop.uopc val fp_ctrl = fp_decoder.io.sigs val fp_rm = Mux(ImmGenRm(io_req.uop.imm_packed) === 7.U, io.fcsr_rm, ImmGenRm(io_req.uop.imm_packed)) val req = Wire(new tile.FPInput) val tag = fp_ctrl.typeTagIn req.viewAsSupertype(new tile.FPUCtrlSigs) := fp_ctrl req.rm := fp_rm req.in1 := unbox(io_req.rs1_data, tag, None) req.in2 := unbox(io_req.rs2_data, tag, None) req.in3 := DontCare req.typ := ImmGenTyp(io_req.uop.imm_packed) req.fmt := DontCare // FIXME: this may not be the right thing to do here req.fmaCmd := DontCare assert (!(io.req.valid && fp_ctrl.fromint && req.in1(xLen).asBool), "[func] IntToFP integer input has 65th high-order bit set!") assert (!(io.req.valid && !fp_ctrl.fromint), "[func] Only support fromInt micro-ops.") val ifpu = Module(new tile.IntToFP(intToFpLatency)) ifpu.io.in.valid := io.req.valid ifpu.io.in.bits := req ifpu.io.in.bits.in1 := io_req.rs1_data val out_double = Pipe(io.req.valid, fp_ctrl.typeTagOut === D, intToFpLatency).bits //io.resp.bits.data := box(ifpu.io.out.bits.data, !io.resp.bits.uop.fp_single) io.resp.bits.data := box(ifpu.io.out.bits.data, out_double) io.resp.bits.fflags.valid := ifpu.io.out.valid io.resp.bits.fflags.bits.uop := io.resp.bits.uop io.resp.bits.fflags.bits.flags := ifpu.io.out.bits.exc } /* * Iterative/unpipelined functional unit, can only hold a single MicroOp at a time * assumes at least one register between request and response * * TODO allow up to N micro-ops simultaneously. * * @param dataWidth width of the data to be passed into the functional unit / abstract class IterativeFunctionalUnit(dataWidth: Int)(implicit p: Parameters) extends FunctionalUnit( isPipelined = false, numStages = 1, numBypassStages = 0, dataWidth = dataWidth) { val r_uop = Reg(new MicroOp()) val do_kill = Wire(Bool()) do_kill := io.req.bits.kill // irrelevant default when (io.req.fire) { // update incoming uop do_kill := IsKilledByBranch(io.brupdate, io.req.bits.uop) \|\| io.req.bits.kill r_uop := io.req.bits.uop r_uop.br_mask := GetNewBrMask(io.brupdate, io.req.bits.uop) } .otherwise { do_kill := IsKilledByBranch(io.brupdate, r_uop) \|\| io.req.bits.kill r_uop.br_mask := GetNewBrMask(io.brupdate, r_uop) } // assumes at least one pipeline register between request and response io.resp.bits.uop := r_uop } /* * Divide functional unit. * * @param dataWidth data to be passed into the functional unit / class DivUnit(dataWidth: Int)(implicit p: Parameters) extends IterativeFunctionalUnit(dataWidth) { // We don't use the iterative multiply functionality here. // Instead we use the PipelinedMultiplier val div = Module(new freechips.rocketchip.rocket.MulDiv(mulDivParams, width = dataWidth)) // request div.io.req.valid := io.req.valid && !this.do_kill div.io.req.bits.dw := io.req.bits.uop.ctrl.fcn_dw div.io.req.bits.fn := io.req.bits.uop.ctrl.op_fcn div.io.req.bits.in1 := io.req.bits.rs1_data div.io.req.bits.in2 := io.req.bits.rs2_data div.io.req.bits.tag := DontCare io.req.ready := div.io.req.ready // handle pipeline kills and branch misspeculations div.io.kill := this.do_kill // response io.resp.valid := div.io.resp.valid && !this.do_kill div.io.resp.ready := io.resp.ready io.resp.bits.data := div.io.resp.bits.data } /* * Pipelined multiplier functional unit that wraps around the RocketChip pipelined multiplier * * @param numStages number of pipeline stages * @param dataWidth size of the data being passed into the functional unit */ class PipelinedMulUnit(numStages: Int, dataWidth: Int)(implicit p: Parameters) extends PipelinedFunctionalUnit( numStages = numStages, numBypassStages = 0, earliestBypassStage = 0, dataWidth = dataWidth) { val imul = Module(new PipelinedMultiplier(xLen, numStages)) // request imul.io.req.valid := io.req.valid imul.io.req.bits.fn := io.req.bits.uop.ctrl.op_fcn imul.io.req.bits.dw := io.req.bits.uop.ctrl.fcn_dw imul.io.req.bits.in1 := io.req.bits.rs1_data imul.io.req.bits.in2 := io.req.bits.rs2_data imul.io.req.bits.tag := DontCare // response io.resp.bits.data := imul.io.resp.bits.data }	module IntToFPUnit( // @[functional-unit.scala:591:7] input clock, // @[functional-unit.scala:591:7] input reset, // @[functional-unit.scala:591:7] input io_req_valid, // @[functional-unit.scala:168:14] input [6:0] io_req_bits_uop_uopc, // @[functional-unit.scala:168:14] input [31:0] io_req_bits_uop_inst, // @[functional-unit.scala:168:14] input [31:0] io_req_bits_uop_debug_inst, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_rvc, // @[functional-unit.scala:168:14] input [39:0] io_req_bits_uop_debug_pc, // @[functional-unit.scala:168:14] input [2:0] io_req_bits_uop_iq_type, // @[functional-unit.scala:168:14] input [9:0] io_req_bits_uop_fu_code, // @[functional-unit.scala:168:14] input [3:0] io_req_bits_uop_ctrl_br_type, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14] input [2:0] io_req_bits_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14] input [2:0] io_req_bits_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14] input [4:0] io_req_bits_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14] input io_req_bits_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14] input [2:0] io_req_bits_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14] input io_req_bits_uop_ctrl_is_load, // @[functional-unit.scala:168:14] input io_req_bits_uop_ctrl_is_sta, // @[functional-unit.scala:168:14] input io_req_bits_uop_ctrl_is_std, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_iw_state, // @[functional-unit.scala:168:14] input io_req_bits_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14] input io_req_bits_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_br, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_jalr, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_jal, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_sfb, // @[functional-unit.scala:168:14] input [7:0] io_req_bits_uop_br_mask, // @[functional-unit.scala:168:14] input [2:0] io_req_bits_uop_br_tag, // @[functional-unit.scala:168:14] input [3:0] io_req_bits_uop_ftq_idx, // @[functional-unit.scala:168:14] input io_req_bits_uop_edge_inst, // @[functional-unit.scala:168:14] input [5:0] io_req_bits_uop_pc_lob, // @[functional-unit.scala:168:14] input io_req_bits_uop_taken, // @[functional-unit.scala:168:14] input [19:0] io_req_bits_uop_imm_packed, // @[functional-unit.scala:168:14] input [11:0] io_req_bits_uop_csr_addr, // @[functional-unit.scala:168:14] input [4:0] io_req_bits_uop_rob_idx, // @[functional-unit.scala:168:14] input [2:0] io_req_bits_uop_ldq_idx, // @[functional-unit.scala:168:14] input [2:0] io_req_bits_uop_stq_idx, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_rxq_idx, // @[functional-unit.scala:168:14] input [5:0] io_req_bits_uop_pdst, // @[functional-unit.scala:168:14] input [5:0] io_req_bits_uop_prs1, // @[functional-unit.scala:168:14] input [5:0] io_req_bits_uop_prs2, // @[functional-unit.scala:168:14] input [5:0] io_req_bits_uop_prs3, // @[functional-unit.scala:168:14] input [3:0] io_req_bits_uop_ppred, // @[functional-unit.scala:168:14] input io_req_bits_uop_prs1_busy, // @[functional-unit.scala:168:14] input io_req_bits_uop_prs2_busy, // @[functional-unit.scala:168:14] input io_req_bits_uop_prs3_busy, // @[functional-unit.scala:168:14] input io_req_bits_uop_ppred_busy, // @[functional-unit.scala:168:14] input [5:0] io_req_bits_uop_stale_pdst, // @[functional-unit.scala:168:14] input io_req_bits_uop_exception, // @[functional-unit.scala:168:14] input [63:0] io_req_bits_uop_exc_cause, // @[functional-unit.scala:168:14] input io_req_bits_uop_bypassable, // @[functional-unit.scala:168:14] input [4:0] io_req_bits_uop_mem_cmd, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_mem_size, // @[functional-unit.scala:168:14] input io_req_bits_uop_mem_signed, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_fence, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_fencei, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_amo, // @[functional-unit.scala:168:14] input io_req_bits_uop_uses_ldq, // @[functional-unit.scala:168:14] input io_req_bits_uop_uses_stq, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_unique, // @[functional-unit.scala:168:14] input io_req_bits_uop_flush_on_commit, // @[functional-unit.scala:168:14] input io_req_bits_uop_ldst_is_rs1, // @[functional-unit.scala:168:14] input [5:0] io_req_bits_uop_ldst, // @[functional-unit.scala:168:14] input [5:0] io_req_bits_uop_lrs1, // @[functional-unit.scala:168:14] input [5:0] io_req_bits_uop_lrs2, // @[functional-unit.scala:168:14] input [5:0] io_req_bits_uop_lrs3, // @[functional-unit.scala:168:14] input io_req_bits_uop_ldst_val, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_dst_rtype, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_lrs1_rtype, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_lrs2_rtype, // @[functional-unit.scala:168:14] input io_req_bits_uop_frs3_en, // @[functional-unit.scala:168:14] input io_req_bits_uop_fp_val, // @[functional-unit.scala:168:14] input io_req_bits_uop_fp_single, // @[functional-unit.scala:168:14] input io_req_bits_uop_xcpt_pf_if, // @[functional-unit.scala:168:14] input io_req_bits_uop_xcpt_ae_if, // @[functional-unit.scala:168:14] input io_req_bits_uop_xcpt_ma_if, // @[functional-unit.scala:168:14] input io_req_bits_uop_bp_debug_if, // @[functional-unit.scala:168:14] input io_req_bits_uop_bp_xcpt_if, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_debug_fsrc, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_debug_tsrc, // @[functional-unit.scala:168:14] input [64:0] io_req_bits_rs1_data, // @[functional-unit.scala:168:14] input [64:0] io_req_bits_rs2_data, // @[functional-unit.scala:168:14] input io_req_bits_kill, // @[functional-unit.scala:168:14] output io_resp_valid, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_uop_uopc, // @[functional-unit.scala:168:14] output [31:0] io_resp_bits_uop_inst, // @[functional-unit.scala:168:14] output [31:0] io_resp_bits_uop_debug_inst, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_rvc, // @[functional-unit.scala:168:14] output [39:0] io_resp_bits_uop_debug_pc, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_uop_iq_type, // @[functional-unit.scala:168:14] output [9:0] io_resp_bits_uop_fu_code, // @[functional-unit.scala:168:14] output [3:0] io_resp_bits_uop_ctrl_br_type, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14] output io_resp_bits_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14] output io_resp_bits_uop_ctrl_is_load, // @[functional-unit.scala:168:14] output io_resp_bits_uop_ctrl_is_sta, // @[functional-unit.scala:168:14] output io_resp_bits_uop_ctrl_is_std, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_iw_state, // @[functional-unit.scala:168:14] output io_resp_bits_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14] output io_resp_bits_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_br, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_jalr, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_jal, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_sfb, // @[functional-unit.scala:168:14] output [7:0] io_resp_bits_uop_br_mask, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_uop_br_tag, // @[functional-unit.scala:168:14] output [3:0] io_resp_bits_uop_ftq_idx, // @[functional-unit.scala:168:14] output io_resp_bits_uop_edge_inst, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_uop_pc_lob, // @[functional-unit.scala:168:14] output io_resp_bits_uop_taken, // @[functional-unit.scala:168:14] output [19:0] io_resp_bits_uop_imm_packed, // @[functional-unit.scala:168:14] output [11:0] io_resp_bits_uop_csr_addr, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_uop_rob_idx, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_uop_ldq_idx, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_uop_stq_idx, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_rxq_idx, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_uop_pdst, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_uop_prs1, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_uop_prs2, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_uop_prs3, // @[functional-unit.scala:168:14] output [3:0] io_resp_bits_uop_ppred, // @[functional-unit.scala:168:14] output io_resp_bits_uop_prs1_busy, // @[functional-unit.scala:168:14] output io_resp_bits_uop_prs2_busy, // @[functional-unit.scala:168:14] output io_resp_bits_uop_prs3_busy, // @[functional-unit.scala:168:14] output io_resp_bits_uop_ppred_busy, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_uop_stale_pdst, // @[functional-unit.scala:168:14] output io_resp_bits_uop_exception, // @[functional-unit.scala:168:14] output [63:0] io_resp_bits_uop_exc_cause, // @[functional-unit.scala:168:14] output io_resp_bits_uop_bypassable, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_uop_mem_cmd, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_mem_size, // @[functional-unit.scala:168:14] output io_resp_bits_uop_mem_signed, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_fence, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_fencei, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_amo, // @[functional-unit.scala:168:14] output io_resp_bits_uop_uses_ldq, // @[functional-unit.scala:168:14] output io_resp_bits_uop_uses_stq, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_unique, // @[functional-unit.scala:168:14] output io_resp_bits_uop_flush_on_commit, // @[functional-unit.scala:168:14] output io_resp_bits_uop_ldst_is_rs1, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_uop_ldst, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_uop_lrs1, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_uop_lrs2, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_uop_lrs3, // @[functional-unit.scala:168:14] output io_resp_bits_uop_ldst_val, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_dst_rtype, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_lrs1_rtype, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_lrs2_rtype, // @[functional-unit.scala:168:14] output io_resp_bits_uop_frs3_en, // @[functional-unit.scala:168:14] output io_resp_bits_uop_fp_val, // @[functional-unit.scala:168:14] output io_resp_bits_uop_fp_single, // @[functional-unit.scala:168:14] output io_resp_bits_uop_xcpt_pf_if, // @[functional-unit.scala:168:14] output io_resp_bits_uop_xcpt_ae_if, // @[functional-unit.scala:168:14] output io_resp_bits_uop_xcpt_ma_if, // @[functional-unit.scala:168:14] output io_resp_bits_uop_bp_debug_if, // @[functional-unit.scala:168:14] output io_resp_bits_uop_bp_xcpt_if, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_debug_fsrc, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_debug_tsrc, // @[functional-unit.scala:168:14] output [64:0] io_resp_bits_data, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_valid, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_fflags_bits_uop_uopc, // @[functional-unit.scala:168:14] output [31:0] io_resp_bits_fflags_bits_uop_inst, // @[functional-unit.scala:168:14] output [31:0] io_resp_bits_fflags_bits_uop_debug_inst, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_rvc, // @[functional-unit.scala:168:14] output [39:0] io_resp_bits_fflags_bits_uop_debug_pc, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_fflags_bits_uop_iq_type, // @[functional-unit.scala:168:14] output [9:0] io_resp_bits_fflags_bits_uop_fu_code, // @[functional-unit.scala:168:14] output [3:0] io_resp_bits_fflags_bits_uop_ctrl_br_type, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_fflags_bits_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_fflags_bits_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_fflags_bits_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_fflags_bits_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_ctrl_is_load, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_ctrl_is_sta, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_ctrl_is_std, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_iw_state, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_br, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_jalr, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_jal, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_sfb, // @[functional-unit.scala:168:14] output [7:0] io_resp_bits_fflags_bits_uop_br_mask, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_fflags_bits_uop_br_tag, // @[functional-unit.scala:168:14] output [3:0] io_resp_bits_fflags_bits_uop_ftq_idx, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_edge_inst, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_fflags_bits_uop_pc_lob, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_taken, // @[functional-unit.scala:168:14] output [19:0] io_resp_bits_fflags_bits_uop_imm_packed, // @[functional-unit.scala:168:14] output [11:0] io_resp_bits_fflags_bits_uop_csr_addr, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_fflags_bits_uop_rob_idx, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_fflags_bits_uop_ldq_idx, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_fflags_bits_uop_stq_idx, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_rxq_idx, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_fflags_bits_uop_pdst, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_fflags_bits_uop_prs1, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_fflags_bits_uop_prs2, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_fflags_bits_uop_prs3, // @[functional-unit.scala:168:14] output [3:0] io_resp_bits_fflags_bits_uop_ppred, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_prs1_busy, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_prs2_busy, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_prs3_busy, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_ppred_busy, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_fflags_bits_uop_stale_pdst, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_exception, // @[functional-unit.scala:168:14] output [63:0] io_resp_bits_fflags_bits_uop_exc_cause, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_bypassable, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_fflags_bits_uop_mem_cmd, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_mem_size, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_mem_signed, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_fence, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_fencei, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_amo, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_uses_ldq, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_uses_stq, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_unique, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_flush_on_commit, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_ldst_is_rs1, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_fflags_bits_uop_ldst, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_fflags_bits_uop_lrs1, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_fflags_bits_uop_lrs2, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_fflags_bits_uop_lrs3, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_ldst_val, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_dst_rtype, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_lrs1_rtype, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_lrs2_rtype, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_frs3_en, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_fp_val, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_fp_single, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_xcpt_pf_if, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_xcpt_ae_if, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_xcpt_ma_if, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_bp_debug_if, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_bp_xcpt_if, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_debug_fsrc, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_debug_tsrc, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_fflags_bits_flags, // @[functional-unit.scala:168:14] input [7:0] io_brupdate_b1_resolve_mask, // @[functional-unit.scala:168:14] input [7:0] io_brupdate_b1_mispredict_mask, // @[functional-unit.scala:168:14] input [6:0] io_brupdate_b2_uop_uopc, // @[functional-unit.scala:168:14] input [31:0] io_brupdate_b2_uop_inst, // @[functional-unit.scala:168:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_rvc, // @[functional-unit.scala:168:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[functional-unit.scala:168:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[functional-unit.scala:168:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[functional-unit.scala:168:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_ctrl_is_load, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_ctrl_is_std, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_br, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_jalr, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_jal, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_sfb, // @[functional-unit.scala:168:14] input [7:0] io_brupdate_b2_uop_br_mask, // @[functional-unit.scala:168:14] input [2:0] io_brupdate_b2_uop_br_tag, // @[functional-unit.scala:168:14] input [3:0] io_brupdate_b2_uop_ftq_idx, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_edge_inst, // @[functional-unit.scala:168:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_taken, // @[functional-unit.scala:168:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[functional-unit.scala:168:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[functional-unit.scala:168:14] input [4:0] io_brupdate_b2_uop_rob_idx, // @[functional-unit.scala:168:14] input [2:0] io_brupdate_b2_uop_ldq_idx, // @[functional-unit.scala:168:14] input [2:0] io_brupdate_b2_uop_stq_idx, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[functional-unit.scala:168:14] input [5:0] io_brupdate_b2_uop_pdst, // @[functional-unit.scala:168:14] input [5:0] io_brupdate_b2_uop_prs1, // @[functional-unit.scala:168:14] input [5:0] io_brupdate_b2_uop_prs2, // @[functional-unit.scala:168:14] input [5:0] io_brupdate_b2_uop_prs3, // @[functional-unit.scala:168:14] input [3:0] io_brupdate_b2_uop_ppred, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_prs1_busy, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_prs2_busy, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_prs3_busy, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_ppred_busy, // @[functional-unit.scala:168:14] input [5:0] io_brupdate_b2_uop_stale_pdst, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_exception, // @[functional-unit.scala:168:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_bypassable, // @[functional-unit.scala:168:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_mem_signed, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_fence, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_fencei, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_amo, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_uses_ldq, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_uses_stq, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_unique, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_flush_on_commit, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[functional-unit.scala:168:14] input [5:0] io_brupdate_b2_uop_ldst, // @[functional-unit.scala:168:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[functional-unit.scala:168:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[functional-unit.scala:168:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_ldst_val, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_frs3_en, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_fp_val, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_fp_single, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_bp_debug_if, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[functional-unit.scala:168:14] input io_brupdate_b2_valid, // @[functional-unit.scala:168:14] input io_brupdate_b2_mispredict, // @[functional-unit.scala:168:14] input io_brupdate_b2_taken, // @[functional-unit.scala:168:14] input [2:0] io_brupdate_b2_cfi_type, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_pc_sel, // @[functional-unit.scala:168:14] input [39:0] io_brupdate_b2_jalr_target, // @[functional-unit.scala:168:14] input [20:0] io_brupdate_b2_target_offset, // @[functional-unit.scala:168:14] input [2:0] io_fcsr_rm // @[functional-unit.scala:168:14] ); wire [1:0] io_resp_bits_uop_debug_tsrc_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_uop_debug_fsrc_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_bp_xcpt_if_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_bp_debug_if_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_xcpt_ma_if_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_xcpt_ae_if_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_xcpt_pf_if_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_fp_single_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_fp_val_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_frs3_en_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_uop_lrs2_rtype_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_uop_lrs1_rtype_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_uop_dst_rtype_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_ldst_val_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_uop_lrs3_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_uop_lrs2_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_uop_lrs1_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_uop_ldst_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_ldst_is_rs1_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_flush_on_commit_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_is_unique_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_is_sys_pc2epc_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_uses_stq_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_uses_ldq_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_is_amo_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_is_fencei_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_is_fence_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_mem_signed_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_uop_mem_size_0; // @[functional-unit.scala:591:7] wire [4:0] io_resp_bits_uop_mem_cmd_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_bypassable_0; // @[functional-unit.scala:591:7] wire [63:0] io_resp_bits_uop_exc_cause_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_exception_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_uop_stale_pdst_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_ppred_busy_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_prs3_busy_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_prs2_busy_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_prs1_busy_0; // @[functional-unit.scala:591:7] wire [3:0] io_resp_bits_uop_ppred_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_uop_prs3_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_uop_prs2_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_uop_prs1_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_uop_pdst_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_uop_rxq_idx_0; // @[functional-unit.scala:591:7] wire [2:0] io_resp_bits_uop_stq_idx_0; // @[functional-unit.scala:591:7] wire [2:0] io_resp_bits_uop_ldq_idx_0; // @[functional-unit.scala:591:7] wire [4:0] io_resp_bits_uop_rob_idx_0; // @[functional-unit.scala:591:7] wire [11:0] io_resp_bits_uop_csr_addr_0; // @[functional-unit.scala:591:7] wire [19:0] io_resp_bits_uop_imm_packed_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_taken_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_uop_pc_lob_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_edge_inst_0; // @[functional-unit.scala:591:7] wire [3:0] io_resp_bits_uop_ftq_idx_0; // @[functional-unit.scala:591:7] wire [2:0] io_resp_bits_uop_br_tag_0; // @[functional-unit.scala:591:7] wire [7:0] io_resp_bits_uop_br_mask_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_is_sfb_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_is_jal_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_is_jalr_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_is_br_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_iw_p2_poisoned_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_iw_p1_poisoned_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_uop_iw_state_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_ctrl_is_std_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_ctrl_is_sta_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_ctrl_is_load_0; // @[functional-unit.scala:591:7] wire [2:0] io_resp_bits_uop_ctrl_csr_cmd_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_ctrl_fcn_dw_0; // @[functional-unit.scala:591:7] wire [4:0] io_resp_bits_uop_ctrl_op_fcn_0; // @[functional-unit.scala:591:7] wire [2:0] io_resp_bits_uop_ctrl_imm_sel_0; // @[functional-unit.scala:591:7] wire [2:0] io_resp_bits_uop_ctrl_op2_sel_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_uop_ctrl_op1_sel_0; // @[functional-unit.scala:591:7] wire [3:0] io_resp_bits_uop_ctrl_br_type_0; // @[functional-unit.scala:591:7] wire [9:0] io_resp_bits_uop_fu_code_0; // @[functional-unit.scala:591:7] wire [2:0] io_resp_bits_uop_iq_type_0; // @[functional-unit.scala:591:7] wire [39:0] io_resp_bits_uop_debug_pc_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_is_rvc_0; // @[functional-unit.scala:591:7] wire [31:0] io_resp_bits_uop_debug_inst_0; // @[functional-unit.scala:591:7] wire [31:0] io_resp_bits_uop_inst_0; // @[functional-unit.scala:591:7] wire [6:0] io_resp_bits_uop_uopc_0; // @[functional-unit.scala:591:7] wire [64:0] _ifpu_io_out_bits_data; // @[functional-unit.scala:624:20] wire [1:0] _fp_decoder_io_sigs_typeTagIn; // @[functional-unit.scala:600:26] wire [1:0] _fp_decoder_io_sigs_typeTagOut; // @[functional-unit.scala:600:26] wire _fp_decoder_io_sigs_fromint; // @[functional-unit.scala:600:26] wire io_req_valid_0 = io_req_valid; // @[functional-unit.scala:591:7] wire [6:0] io_req_bits_uop_uopc_0 = io_req_bits_uop_uopc; // @[functional-unit.scala:591:7] wire [31:0] io_req_bits_uop_inst_0 = io_req_bits_uop_inst; // @[functional-unit.scala:591:7] wire [31:0] io_req_bits_uop_debug_inst_0 = io_req_bits_uop_debug_inst; // @[functional-unit.scala:591:7] wire io_req_bits_uop_is_rvc_0 = io_req_bits_uop_is_rvc; // @[functional-unit.scala:591:7] wire [39:0] io_req_bits_uop_debug_pc_0 = io_req_bits_uop_debug_pc; // @[functional-unit.scala:591:7] wire [2:0] io_req_bits_uop_iq_type_0 = io_req_bits_uop_iq_type; // @[functional-unit.scala:591:7] wire [9:0] io_req_bits_uop_fu_code_0 = io_req_bits_uop_fu_code; // @[functional-unit.scala:591:7] wire [3:0] io_req_bits_uop_ctrl_br_type_0 = io_req_bits_uop_ctrl_br_type; // @[functional-unit.scala:591:7] wire [1:0] io_req_bits_uop_ctrl_op1_sel_0 = io_req_bits_uop_ctrl_op1_sel; // @[functional-unit.scala:591:7] wire [2:0] io_req_bits_uop_ctrl_op2_sel_0 = io_req_bits_uop_ctrl_op2_sel; // @[functional-unit.scala:591:7] wire [2:0] io_req_bits_uop_ctrl_imm_sel_0 = io_req_bits_uop_ctrl_imm_sel; // @[functional-unit.scala:591:7] wire [4:0] io_req_bits_uop_ctrl_op_fcn_0 = io_req_bits_uop_ctrl_op_fcn; // @[functional-unit.scala:591:7] wire io_req_bits_uop_ctrl_fcn_dw_0 = io_req_bits_uop_ctrl_fcn_dw; // @[functional-unit.scala:591:7] wire [2:0] io_req_bits_uop_ctrl_csr_cmd_0 = io_req_bits_uop_ctrl_csr_cmd; // @[functional-unit.scala:591:7] wire io_req_bits_uop_ctrl_is_load_0 = io_req_bits_uop_ctrl_is_load; // @[functional-unit.scala:591:7] wire io_req_bits_uop_ctrl_is_sta_0 = io_req_bits_uop_ctrl_is_sta; // @[functional-unit.scala:591:7] wire io_req_bits_uop_ctrl_is_std_0 = io_req_bits_uop_ctrl_is_std; // @[functional-unit.scala:591:7] wire [1:0] io_req_bits_uop_iw_state_0 = io_req_bits_uop_iw_state; // @[functional-unit.scala:591:7] wire io_req_bits_uop_iw_p1_poisoned_0 = io_req_bits_uop_iw_p1_poisoned; // @[functional-unit.scala:591:7] wire io_req_bits_uop_iw_p2_poisoned_0 = io_req_bits_uop_iw_p2_poisoned; // @[functional-unit.scala:591:7] wire io_req_bits_uop_is_br_0 = io_req_bits_uop_is_br; // @[functional-unit.scala:591:7] wire io_req_bits_uop_is_jalr_0 = io_req_bits_uop_is_jalr; // @[functional-unit.scala:591:7] wire io_req_bits_uop_is_jal_0 = io_req_bits_uop_is_jal; // @[functional-unit.scala:591:7] wire io_req_bits_uop_is_sfb_0 = io_req_bits_uop_is_sfb; // @[functional-unit.scala:591:7] wire [7:0] io_req_bits_uop_br_mask_0 = io_req_bits_uop_br_mask; // @[functional-unit.scala:591:7] wire [2:0] io_req_bits_uop_br_tag_0 = io_req_bits_uop_br_tag; // @[functional-unit.scala:591:7] wire [3:0] io_req_bits_uop_ftq_idx_0 = io_req_bits_uop_ftq_idx; // @[functional-unit.scala:591:7] wire io_req_bits_uop_edge_inst_0 = io_req_bits_uop_edge_inst; // @[functional-unit.scala:591:7] wire [5:0] io_req_bits_uop_pc_lob_0 = io_req_bits_uop_pc_lob; // @[functional-unit.scala:591:7] wire io_req_bits_uop_taken_0 = io_req_bits_uop_taken; // @[functional-unit.scala:591:7] wire [19:0] io_req_bits_uop_imm_packed_0 = io_req_bits_uop_imm_packed; // @[functional-unit.scala:591:7] wire [11:0] io_req_bits_uop_csr_addr_0 = io_req_bits_uop_csr_addr; // @[functional-unit.scala:591:7] wire [4:0] io_req_bits_uop_rob_idx_0 = io_req_bits_uop_rob_idx; // @[functional-unit.scala:591:7] wire [2:0] io_req_bits_uop_ldq_idx_0 = io_req_bits_uop_ldq_idx; // @[functional-unit.scala:591:7] wire [2:0] io_req_bits_uop_stq_idx_0 = io_req_bits_uop_stq_idx; // @[functional-unit.scala:591:7] wire [1:0] io_req_bits_uop_rxq_idx_0 = io_req_bits_uop_rxq_idx; // @[functional-unit.scala:591:7] wire [5:0] io_req_bits_uop_pdst_0 = io_req_bits_uop_pdst; // @[functional-unit.scala:591:7] wire [5:0] io_req_bits_uop_prs1_0 = io_req_bits_uop_prs1; // @[functional-unit.scala:591:7] wire [5:0] io_req_bits_uop_prs2_0 = io_req_bits_uop_prs2; // @[functional-unit.scala:591:7] wire [5:0] io_req_bits_uop_prs3_0 = io_req_bits_uop_prs3; // @[functional-unit.scala:591:7] wire [3:0] io_req_bits_uop_ppred_0 = io_req_bits_uop_ppred; // @[functional-unit.scala:591:7] wire io_req_bits_uop_prs1_busy_0 = io_req_bits_uop_prs1_busy; // @[functional-unit.scala:591:7] wire io_req_bits_uop_prs2_busy_0 = io_req_bits_uop_prs2_busy; // @[functional-unit.scala:591:7] wire io_req_bits_uop_prs3_busy_0 = io_req_bits_uop_prs3_busy; // @[functional-unit.scala:591:7] wire io_req_bits_uop_ppred_busy_0 = io_req_bits_uop_ppred_busy; // @[functional-unit.scala:591:7] wire [5:0] io_req_bits_uop_stale_pdst_0 = io_req_bits_uop_stale_pdst; // @[functional-unit.scala:591:7] wire io_req_bits_uop_exception_0 = io_req_bits_uop_exception; // @[functional-unit.scala:591:7] wire [63:0] io_req_bits_uop_exc_cause_0 = io_req_bits_uop_exc_cause; // @[functional-unit.scala:591:7] wire io_req_bits_uop_bypassable_0 = io_req_bits_uop_bypassable; // @[functional-unit.scala:591:7] wire [4:0] io_req_bits_uop_mem_cmd_0 = io_req_bits_uop_mem_cmd; // @[functional-unit.scala:591:7] wire [1:0] io_req_bits_uop_mem_size_0 = io_req_bits_uop_mem_size; // @[functional-unit.scala:591:7] wire io_req_bits_uop_mem_signed_0 = io_req_bits_uop_mem_signed; // @[functional-unit.scala:591:7] wire io_req_bits_uop_is_fence_0 = io_req_bits_uop_is_fence; // @[functional-unit.scala:591:7] wire io_req_bits_uop_is_fencei_0 = io_req_bits_uop_is_fencei; // @[functional-unit.scala:591:7] wire io_req_bits_uop_is_amo_0 = io_req_bits_uop_is_amo; // @[functional-unit.scala:591:7] wire io_req_bits_uop_uses_ldq_0 = io_req_bits_uop_uses_ldq; // @[functional-unit.scala:591:7] wire io_req_bits_uop_uses_stq_0 = io_req_bits_uop_uses_stq; // @[functional-unit.scala:591:7] wire io_req_bits_uop_is_sys_pc2epc_0 = io_req_bits_uop_is_sys_pc2epc; // @[functional-unit.scala:591:7] wire io_req_bits_uop_is_unique_0 = io_req_bits_uop_is_unique; // @[functional-unit.scala:591:7] wire io_req_bits_uop_flush_on_commit_0 = io_req_bits_uop_flush_on_commit; // @[functional-unit.scala:591:7] wire io_req_bits_uop_ldst_is_rs1_0 = io_req_bits_uop_ldst_is_rs1; // @[functional-unit.scala:591:7] wire [5:0] io_req_bits_uop_ldst_0 = io_req_bits_uop_ldst; // @[functional-unit.scala:591:7] wire [5:0] io_req_bits_uop_lrs1_0 = io_req_bits_uop_lrs1; // @[functional-unit.scala:591:7] wire [5:0] io_req_bits_uop_lrs2_0 = io_req_bits_uop_lrs2; // @[functional-unit.scala:591:7] wire [5:0] io_req_bits_uop_lrs3_0 = io_req_bits_uop_lrs3; // @[functional-unit.scala:591:7] wire io_req_bits_uop_ldst_val_0 = io_req_bits_uop_ldst_val; // @[functional-unit.scala:591:7] wire [1:0] io_req_bits_uop_dst_rtype_0 = io_req_bits_uop_dst_rtype; // @[functional-unit.scala:591:7] wire [1:0] io_req_bits_uop_lrs1_rtype_0 = io_req_bits_uop_lrs1_rtype; // @[functional-unit.scala:591:7] wire [1:0] io_req_bits_uop_lrs2_rtype_0 = io_req_bits_uop_lrs2_rtype; // @[functional-unit.scala:591:7] wire io_req_bits_uop_frs3_en_0 = io_req_bits_uop_frs3_en; // @[functional-unit.scala:591:7] wire io_req_bits_uop_fp_val_0 = io_req_bits_uop_fp_val; // @[functional-unit.scala:591:7] wire io_req_bits_uop_fp_single_0 = io_req_bits_uop_fp_single; // @[functional-unit.scala:591:7] wire io_req_bits_uop_xcpt_pf_if_0 = io_req_bits_uop_xcpt_pf_if; // @[functional-unit.scala:591:7] wire io_req_bits_uop_xcpt_ae_if_0 = io_req_bits_uop_xcpt_ae_if; // @[functional-unit.scala:591:7] wire io_req_bits_uop_xcpt_ma_if_0 = io_req_bits_uop_xcpt_ma_if; // @[functional-unit.scala:591:7] wire io_req_bits_uop_bp_debug_if_0 = io_req_bits_uop_bp_debug_if; // @[functional-unit.scala:591:7] wire io_req_bits_uop_bp_xcpt_if_0 = io_req_bits_uop_bp_xcpt_if; // @[functional-unit.scala:591:7] wire [1:0] io_req_bits_uop_debug_fsrc_0 = io_req_bits_uop_debug_fsrc; // @[functional-unit.scala:591:7] wire [1:0] io_req_bits_uop_debug_tsrc_0 = io_req_bits_uop_debug_tsrc; // @[functional-unit.scala:591:7] wire [64:0] io_req_bits_rs1_data_0 = io_req_bits_rs1_data; // @[functional-unit.scala:591:7] wire [64:0] io_req_bits_rs2_data_0 = io_req_bits_rs2_data; // @[functional-unit.scala:591:7] wire io_req_bits_kill_0 = io_req_bits_kill; // @[functional-unit.scala:591:7] wire [7:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[functional-unit.scala:591:7] wire [7:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[functional-unit.scala:591:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[functional-unit.scala:591:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[functional-unit.scala:591:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[functional-unit.scala:591:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[functional-unit.scala:591:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[functional-unit.scala:591:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[functional-unit.scala:591:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[functional-unit.scala:591:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[functional-unit.scala:591:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[functional-unit.scala:591:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[functional-unit.scala:591:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[functional-unit.scala:591:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[functional-unit.scala:591:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[functional-unit.scala:591:7] wire [7:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[functional-unit.scala:591:7] wire [2:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[functional-unit.scala:591:7] wire [3:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[functional-unit.scala:591:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[functional-unit.scala:591:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[functional-unit.scala:591:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[functional-unit.scala:591:7] wire [4:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[functional-unit.scala:591:7] wire [2:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[functional-unit.scala:591:7] wire [2:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[functional-unit.scala:591:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[functional-unit.scala:591:7] wire [5:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[functional-unit.scala:591:7] wire [5:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[functional-unit.scala:591:7] wire [5:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[functional-unit.scala:591:7] wire [5:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[functional-unit.scala:591:7] wire [3:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[functional-unit.scala:591:7] wire [5:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[functional-unit.scala:591:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[functional-unit.scala:591:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[functional-unit.scala:591:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[functional-unit.scala:591:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[functional-unit.scala:591:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[functional-unit.scala:591:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[functional-unit.scala:591:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[functional-unit.scala:591:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[functional-unit.scala:591:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[functional-unit.scala:591:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[functional-unit.scala:591:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[functional-unit.scala:591:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[functional-unit.scala:591:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[functional-unit.scala:591:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[functional-unit.scala:591:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[functional-unit.scala:591:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[functional-unit.scala:591:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[functional-unit.scala:591:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[functional-unit.scala:591:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[functional-unit.scala:591:7] wire [2:0] io_fcsr_rm_0 = io_fcsr_rm; // @[functional-unit.scala:591:7] wire io_req_ready = 1'h1; // @[functional-unit.scala:591:7] wire _io_resp_bits_data_opts_bigger_swizzledNaN_T = 1'h1; // @[FPU.scala:338:42] wire _io_resp_bits_data_opts_bigger_T = 1'h1; // @[FPU.scala:249:56] wire [64:0] io_req_bits_rs3_data = 65'h0; // @[functional-unit.scala:591:7] wire [64:0] req_in3 = 65'h0; // @[functional-unit.scala:605:17] wire io_req_bits_pred_data = 1'h0; // @[functional-unit.scala:591:7] wire io_resp_ready = 1'h0; // @[functional-unit.scala:591:7] wire io_resp_bits_predicated = 1'h0; // @[functional-unit.scala:591:7] wire io_resp_bits_mxcpt_valid = 1'h0; // @[functional-unit.scala:591:7] wire io_resp_bits_sfence_valid = 1'h0; // @[functional-unit.scala:591:7] wire io_resp_bits_sfence_bits_rs1 = 1'h0; // @[functional-unit.scala:591:7] wire io_resp_bits_sfence_bits_rs2 = 1'h0; // @[functional-unit.scala:591:7] wire io_resp_bits_sfence_bits_asid = 1'h0; // @[functional-unit.scala:591:7] wire io_resp_bits_sfence_bits_hv = 1'h0; // @[functional-unit.scala:591:7] wire io_resp_bits_sfence_bits_hg = 1'h0; // @[functional-unit.scala:591:7] wire _r_valids_WIRE_0 = 1'h0; // @[functional-unit.scala:236:35] wire _r_valids_WIRE_1 = 1'h0; // @[functional-unit.scala:236:35] wire req_vec = 1'h0; // @[functional-unit.scala:605:17] wire [39:0] io_resp_bits_addr = 40'h0; // @[functional-unit.scala:591:7] wire [24:0] io_resp_bits_mxcpt_bits = 25'h0; // @[functional-unit.scala:591:7] wire [38:0] io_resp_bits_sfence_bits_addr = 39'h0; // @[functional-unit.scala:591:7] wire [4:0] io_resp_bits_data_opts_bigger_swizzledNaN_hi_hi = 5'h1F; // @[FPU.scala:336:26] wire [1:0] req_fmaCmd = 2'h0; // @[functional-unit.scala:605:17] wire [1:0] req_fmt = 2'h0; // @[functional-unit.scala:605:17] wire _io_resp_valid_T_3; // @[functional-unit.scala:257:47] wire [6:0] io_resp_bits_fflags_bits_uop_uopc_0 = io_resp_bits_uop_uopc_0; // @[functional-unit.scala:591:7] wire [31:0] io_resp_bits_fflags_bits_uop_inst_0 = io_resp_bits_uop_inst_0; // @[functional-unit.scala:591:7] wire [31:0] io_resp_bits_fflags_bits_uop_debug_inst_0 = io_resp_bits_uop_debug_inst_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_is_rvc_0 = io_resp_bits_uop_is_rvc_0; // @[functional-unit.scala:591:7] wire [39:0] io_resp_bits_fflags_bits_uop_debug_pc_0 = io_resp_bits_uop_debug_pc_0; // @[functional-unit.scala:591:7] wire [2:0] io_resp_bits_fflags_bits_uop_iq_type_0 = io_resp_bits_uop_iq_type_0; // @[functional-unit.scala:591:7] wire [9:0] io_resp_bits_fflags_bits_uop_fu_code_0 = io_resp_bits_uop_fu_code_0; // @[functional-unit.scala:591:7] wire [3:0] io_resp_bits_fflags_bits_uop_ctrl_br_type_0 = io_resp_bits_uop_ctrl_br_type_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_fflags_bits_uop_ctrl_op1_sel_0 = io_resp_bits_uop_ctrl_op1_sel_0; // @[functional-unit.scala:591:7] wire [2:0] io_resp_bits_fflags_bits_uop_ctrl_op2_sel_0 = io_resp_bits_uop_ctrl_op2_sel_0; // @[functional-unit.scala:591:7] wire [2:0] io_resp_bits_fflags_bits_uop_ctrl_imm_sel_0 = io_resp_bits_uop_ctrl_imm_sel_0; // @[functional-unit.scala:591:7] wire [4:0] io_resp_bits_fflags_bits_uop_ctrl_op_fcn_0 = io_resp_bits_uop_ctrl_op_fcn_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_ctrl_fcn_dw_0 = io_resp_bits_uop_ctrl_fcn_dw_0; // @[functional-unit.scala:591:7] wire [2:0] io_resp_bits_fflags_bits_uop_ctrl_csr_cmd_0 = io_resp_bits_uop_ctrl_csr_cmd_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_ctrl_is_load_0 = io_resp_bits_uop_ctrl_is_load_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_ctrl_is_sta_0 = io_resp_bits_uop_ctrl_is_sta_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_ctrl_is_std_0 = io_resp_bits_uop_ctrl_is_std_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_fflags_bits_uop_iw_state_0 = io_resp_bits_uop_iw_state_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_iw_p1_poisoned_0 = io_resp_bits_uop_iw_p1_poisoned_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_iw_p2_poisoned_0 = io_resp_bits_uop_iw_p2_poisoned_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_is_br_0 = io_resp_bits_uop_is_br_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_is_jalr_0 = io_resp_bits_uop_is_jalr_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_is_jal_0 = io_resp_bits_uop_is_jal_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_is_sfb_0 = io_resp_bits_uop_is_sfb_0; // @[functional-unit.scala:591:7] wire [7:0] _io_resp_bits_uop_br_mask_T_1; // @[util.scala:85:25] wire [7:0] io_resp_bits_fflags_bits_uop_br_mask_0 = io_resp_bits_uop_br_mask_0; // @[functional-unit.scala:591:7] wire [2:0] io_resp_bits_fflags_bits_uop_br_tag_0 = io_resp_bits_uop_br_tag_0; // @[functional-unit.scala:591:7] wire [3:0] io_resp_bits_fflags_bits_uop_ftq_idx_0 = io_resp_bits_uop_ftq_idx_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_edge_inst_0 = io_resp_bits_uop_edge_inst_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_fflags_bits_uop_pc_lob_0 = io_resp_bits_uop_pc_lob_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_taken_0 = io_resp_bits_uop_taken_0; // @[functional-unit.scala:591:7] wire [19:0] io_resp_bits_fflags_bits_uop_imm_packed_0 = io_resp_bits_uop_imm_packed_0; // @[functional-unit.scala:591:7] wire [11:0] io_resp_bits_fflags_bits_uop_csr_addr_0 = io_resp_bits_uop_csr_addr_0; // @[functional-unit.scala:591:7] wire [4:0] io_resp_bits_fflags_bits_uop_rob_idx_0 = io_resp_bits_uop_rob_idx_0; // @[functional-unit.scala:591:7] wire [2:0] io_resp_bits_fflags_bits_uop_ldq_idx_0 = io_resp_bits_uop_ldq_idx_0; // @[functional-unit.scala:591:7] wire [2:0] io_resp_bits_fflags_bits_uop_stq_idx_0 = io_resp_bits_uop_stq_idx_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_fflags_bits_uop_rxq_idx_0 = io_resp_bits_uop_rxq_idx_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_fflags_bits_uop_pdst_0 = io_resp_bits_uop_pdst_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_fflags_bits_uop_prs1_0 = io_resp_bits_uop_prs1_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_fflags_bits_uop_prs2_0 = io_resp_bits_uop_prs2_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_fflags_bits_uop_prs3_0 = io_resp_bits_uop_prs3_0; // @[functional-unit.scala:591:7] wire [3:0] io_resp_bits_fflags_bits_uop_ppred_0 = io_resp_bits_uop_ppred_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_prs1_busy_0 = io_resp_bits_uop_prs1_busy_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_prs2_busy_0 = io_resp_bits_uop_prs2_busy_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_prs3_busy_0 = io_resp_bits_uop_prs3_busy_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_ppred_busy_0 = io_resp_bits_uop_ppred_busy_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_fflags_bits_uop_stale_pdst_0 = io_resp_bits_uop_stale_pdst_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_exception_0 = io_resp_bits_uop_exception_0; // @[functional-unit.scala:591:7] wire [63:0] io_resp_bits_fflags_bits_uop_exc_cause_0 = io_resp_bits_uop_exc_cause_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_bypassable_0 = io_resp_bits_uop_bypassable_0; // @[functional-unit.scala:591:7] wire [4:0] io_resp_bits_fflags_bits_uop_mem_cmd_0 = io_resp_bits_uop_mem_cmd_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_fflags_bits_uop_mem_size_0 = io_resp_bits_uop_mem_size_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_mem_signed_0 = io_resp_bits_uop_mem_signed_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_is_fence_0 = io_resp_bits_uop_is_fence_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_is_fencei_0 = io_resp_bits_uop_is_fencei_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_is_amo_0 = io_resp_bits_uop_is_amo_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_uses_ldq_0 = io_resp_bits_uop_uses_ldq_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_uses_stq_0 = io_resp_bits_uop_uses_stq_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_is_sys_pc2epc_0 = io_resp_bits_uop_is_sys_pc2epc_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_is_unique_0 = io_resp_bits_uop_is_unique_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_flush_on_commit_0 = io_resp_bits_uop_flush_on_commit_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_ldst_is_rs1_0 = io_resp_bits_uop_ldst_is_rs1_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_fflags_bits_uop_ldst_0 = io_resp_bits_uop_ldst_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_fflags_bits_uop_lrs1_0 = io_resp_bits_uop_lrs1_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_fflags_bits_uop_lrs2_0 = io_resp_bits_uop_lrs2_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_fflags_bits_uop_lrs3_0 = io_resp_bits_uop_lrs3_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_ldst_val_0 = io_resp_bits_uop_ldst_val_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_fflags_bits_uop_dst_rtype_0 = io_resp_bits_uop_dst_rtype_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_fflags_bits_uop_lrs1_rtype_0 = io_resp_bits_uop_lrs1_rtype_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_fflags_bits_uop_lrs2_rtype_0 = io_resp_bits_uop_lrs2_rtype_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_frs3_en_0 = io_resp_bits_uop_frs3_en_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_fp_val_0 = io_resp_bits_uop_fp_val_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_fp_single_0 = io_resp_bits_uop_fp_single_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_xcpt_pf_if_0 = io_resp_bits_uop_xcpt_pf_if_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_xcpt_ae_if_0 = io_resp_bits_uop_xcpt_ae_if_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_xcpt_ma_if_0 = io_resp_bits_uop_xcpt_ma_if_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_bp_debug_if_0 = io_resp_bits_uop_bp_debug_if_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_bp_xcpt_if_0 = io_resp_bits_uop_bp_xcpt_if_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_fflags_bits_uop_debug_fsrc_0 = io_resp_bits_uop_debug_fsrc_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_fflags_bits_uop_debug_tsrc_0 = io_resp_bits_uop_debug_tsrc_0; // @[functional-unit.scala:591:7] wire [64:0] _io_resp_bits_data_T_1; // @[package.scala:39:76] wire [4:0] io_resp_bits_fflags_bits_flags_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_valid_0; // @[functional-unit.scala:591:7] wire [64:0] io_resp_bits_data_0; // @[functional-unit.scala:591:7] wire io_resp_valid_0; // @[functional-unit.scala:591:7] reg r_valids_0; // @[functional-unit.scala:236:27] reg r_valids_1; // @[functional-unit.scala:236:27] reg [6:0] r_uops_0_uopc; // @[functional-unit.scala:237:23] reg [31:0] r_uops_0_inst; // @[functional-unit.scala:237:23] reg [31:0] r_uops_0_debug_inst; // @[functional-unit.scala:237:23] reg r_uops_0_is_rvc; // @[functional-unit.scala:237:23] reg [39:0] r_uops_0_debug_pc; // @[functional-unit.scala:237:23] reg [2:0] r_uops_0_iq_type; // @[functional-unit.scala:237:23] reg [9:0] r_uops_0_fu_code; // @[functional-unit.scala:237:23] reg [3:0] r_uops_0_ctrl_br_type; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_ctrl_op1_sel; // @[functional-unit.scala:237:23] reg [2:0] r_uops_0_ctrl_op2_sel; // @[functional-unit.scala:237:23] reg [2:0] r_uops_0_ctrl_imm_sel; // @[functional-unit.scala:237:23] reg [4:0] r_uops_0_ctrl_op_fcn; // @[functional-unit.scala:237:23] reg r_uops_0_ctrl_fcn_dw; // @[functional-unit.scala:237:23] reg [2:0] r_uops_0_ctrl_csr_cmd; // @[functional-unit.scala:237:23] reg r_uops_0_ctrl_is_load; // @[functional-unit.scala:237:23] reg r_uops_0_ctrl_is_sta; // @[functional-unit.scala:237:23] reg r_uops_0_ctrl_is_std; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_iw_state; // @[functional-unit.scala:237:23] reg r_uops_0_iw_p1_poisoned; // @[functional-unit.scala:237:23] reg r_uops_0_iw_p2_poisoned; // @[functional-unit.scala:237:23] reg r_uops_0_is_br; // @[functional-unit.scala:237:23] reg r_uops_0_is_jalr; // @[functional-unit.scala:237:23] reg r_uops_0_is_jal; // @[functional-unit.scala:237:23] reg r_uops_0_is_sfb; // @[functional-unit.scala:237:23] reg [7:0] r_uops_0_br_mask; // @[functional-unit.scala:237:23] reg [2:0] r_uops_0_br_tag; // @[functional-unit.scala:237:23] reg [3:0] r_uops_0_ftq_idx; // @[functional-unit.scala:237:23] reg r_uops_0_edge_inst; // @[functional-unit.scala:237:23] reg [5:0] r_uops_0_pc_lob; // @[functional-unit.scala:237:23] reg r_uops_0_taken; // @[functional-unit.scala:237:23] reg [19:0] r_uops_0_imm_packed; // @[functional-unit.scala:237:23] reg [11:0] r_uops_0_csr_addr; // @[functional-unit.scala:237:23] reg [4:0] r_uops_0_rob_idx; // @[functional-unit.scala:237:23] reg [2:0] r_uops_0_ldq_idx; // @[functional-unit.scala:237:23] reg [2:0] r_uops_0_stq_idx; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_rxq_idx; // @[functional-unit.scala:237:23] reg [5:0] r_uops_0_pdst; // @[functional-unit.scala:237:23] reg [5:0] r_uops_0_prs1; // @[functional-unit.scala:237:23] reg [5:0] r_uops_0_prs2; // @[functional-unit.scala:237:23] reg [5:0] r_uops_0_prs3; // @[functional-unit.scala:237:23] reg [3:0] r_uops_0_ppred; // @[functional-unit.scala:237:23] reg r_uops_0_prs1_busy; // @[functional-unit.scala:237:23] reg r_uops_0_prs2_busy; // @[functional-unit.scala:237:23] reg r_uops_0_prs3_busy; // @[functional-unit.scala:237:23] reg r_uops_0_ppred_busy; // @[functional-unit.scala:237:23] reg [5:0] r_uops_0_stale_pdst; // @[functional-unit.scala:237:23] reg r_uops_0_exception; // @[functional-unit.scala:237:23] reg [63:0] r_uops_0_exc_cause; // @[functional-unit.scala:237:23] reg r_uops_0_bypassable; // @[functional-unit.scala:237:23] reg [4:0] r_uops_0_mem_cmd; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_mem_size; // @[functional-unit.scala:237:23] reg r_uops_0_mem_signed; // @[functional-unit.scala:237:23] reg r_uops_0_is_fence; // @[functional-unit.scala:237:23] reg r_uops_0_is_fencei; // @[functional-unit.scala:237:23] reg r_uops_0_is_amo; // @[functional-unit.scala:237:23] reg r_uops_0_uses_ldq; // @[functional-unit.scala:237:23] reg r_uops_0_uses_stq; // @[functional-unit.scala:237:23] reg r_uops_0_is_sys_pc2epc; // @[functional-unit.scala:237:23] reg r_uops_0_is_unique; // @[functional-unit.scala:237:23] reg r_uops_0_flush_on_commit; // @[functional-unit.scala:237:23] reg r_uops_0_ldst_is_rs1; // @[functional-unit.scala:237:23] reg [5:0] r_uops_0_ldst; // @[functional-unit.scala:237:23] reg [5:0] r_uops_0_lrs1; // @[functional-unit.scala:237:23] reg [5:0] r_uops_0_lrs2; // @[functional-unit.scala:237:23] reg [5:0] r_uops_0_lrs3; // @[functional-unit.scala:237:23] reg r_uops_0_ldst_val; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_dst_rtype; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_lrs1_rtype; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_lrs2_rtype; // @[functional-unit.scala:237:23] reg r_uops_0_frs3_en; // @[functional-unit.scala:237:23] reg r_uops_0_fp_val; // @[functional-unit.scala:237:23] reg r_uops_0_fp_single; // @[functional-unit.scala:237:23] reg r_uops_0_xcpt_pf_if; // @[functional-unit.scala:237:23] reg r_uops_0_xcpt_ae_if; // @[functional-unit.scala:237:23] reg r_uops_0_xcpt_ma_if; // @[functional-unit.scala:237:23] reg r_uops_0_bp_debug_if; // @[functional-unit.scala:237:23] reg r_uops_0_bp_xcpt_if; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_debug_fsrc; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_debug_tsrc; // @[functional-unit.scala:237:23] reg [6:0] r_uops_1_uopc; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_uopc_0 = r_uops_1_uopc; // @[functional-unit.scala:237:23, :591:7] reg [31:0] r_uops_1_inst; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_inst_0 = r_uops_1_inst; // @[functional-unit.scala:237:23, :591:7] reg [31:0] r_uops_1_debug_inst; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_debug_inst_0 = r_uops_1_debug_inst; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_is_rvc; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_rvc_0 = r_uops_1_is_rvc; // @[functional-unit.scala:237:23, :591:7] reg [39:0] r_uops_1_debug_pc; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_debug_pc_0 = r_uops_1_debug_pc; // @[functional-unit.scala:237:23, :591:7] reg [2:0] r_uops_1_iq_type; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_iq_type_0 = r_uops_1_iq_type; // @[functional-unit.scala:237:23, :591:7] reg [9:0] r_uops_1_fu_code; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_fu_code_0 = r_uops_1_fu_code; // @[functional-unit.scala:237:23, :591:7] reg [3:0] r_uops_1_ctrl_br_type; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_br_type_0 = r_uops_1_ctrl_br_type; // @[functional-unit.scala:237:23, :591:7] reg [1:0] r_uops_1_ctrl_op1_sel; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_op1_sel_0 = r_uops_1_ctrl_op1_sel; // @[functional-unit.scala:237:23, :591:7] reg [2:0] r_uops_1_ctrl_op2_sel; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_op2_sel_0 = r_uops_1_ctrl_op2_sel; // @[functional-unit.scala:237:23, :591:7] reg [2:0] r_uops_1_ctrl_imm_sel; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_imm_sel_0 = r_uops_1_ctrl_imm_sel; // @[functional-unit.scala:237:23, :591:7] reg [4:0] r_uops_1_ctrl_op_fcn; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_op_fcn_0 = r_uops_1_ctrl_op_fcn; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_ctrl_fcn_dw; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_fcn_dw_0 = r_uops_1_ctrl_fcn_dw; // @[functional-unit.scala:237:23, :591:7] reg [2:0] r_uops_1_ctrl_csr_cmd; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_csr_cmd_0 = r_uops_1_ctrl_csr_cmd; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_ctrl_is_load; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_is_load_0 = r_uops_1_ctrl_is_load; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_ctrl_is_sta; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_is_sta_0 = r_uops_1_ctrl_is_sta; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_ctrl_is_std; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_is_std_0 = r_uops_1_ctrl_is_std; // @[functional-unit.scala:237:23, :591:7] reg [1:0] r_uops_1_iw_state; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_iw_state_0 = r_uops_1_iw_state; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_iw_p1_poisoned; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_iw_p1_poisoned_0 = r_uops_1_iw_p1_poisoned; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_iw_p2_poisoned; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_iw_p2_poisoned_0 = r_uops_1_iw_p2_poisoned; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_is_br; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_br_0 = r_uops_1_is_br; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_is_jalr; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_jalr_0 = r_uops_1_is_jalr; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_is_jal; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_jal_0 = r_uops_1_is_jal; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_is_sfb; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_sfb_0 = r_uops_1_is_sfb; // @[functional-unit.scala:237:23, :591:7] reg [7:0] r_uops_1_br_mask; // @[functional-unit.scala:237:23] reg [2:0] r_uops_1_br_tag; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_br_tag_0 = r_uops_1_br_tag; // @[functional-unit.scala:237:23, :591:7] reg [3:0] r_uops_1_ftq_idx; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ftq_idx_0 = r_uops_1_ftq_idx; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_edge_inst; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_edge_inst_0 = r_uops_1_edge_inst; // @[functional-unit.scala:237:23, :591:7] reg [5:0] r_uops_1_pc_lob; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_pc_lob_0 = r_uops_1_pc_lob; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_taken; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_taken_0 = r_uops_1_taken; // @[functional-unit.scala:237:23, :591:7] reg [19:0] r_uops_1_imm_packed; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_imm_packed_0 = r_uops_1_imm_packed; // @[functional-unit.scala:237:23, :591:7] reg [11:0] r_uops_1_csr_addr; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_csr_addr_0 = r_uops_1_csr_addr; // @[functional-unit.scala:237:23, :591:7] reg [4:0] r_uops_1_rob_idx; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_rob_idx_0 = r_uops_1_rob_idx; // @[functional-unit.scala:237:23, :591:7] reg [2:0] r_uops_1_ldq_idx; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ldq_idx_0 = r_uops_1_ldq_idx; // @[functional-unit.scala:237:23, :591:7] reg [2:0] r_uops_1_stq_idx; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_stq_idx_0 = r_uops_1_stq_idx; // @[functional-unit.scala:237:23, :591:7] reg [1:0] r_uops_1_rxq_idx; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_rxq_idx_0 = r_uops_1_rxq_idx; // @[functional-unit.scala:237:23, :591:7] reg [5:0] r_uops_1_pdst; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_pdst_0 = r_uops_1_pdst; // @[functional-unit.scala:237:23, :591:7] reg [5:0] r_uops_1_prs1; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_prs1_0 = r_uops_1_prs1; // @[functional-unit.scala:237:23, :591:7] reg [5:0] r_uops_1_prs2; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_prs2_0 = r_uops_1_prs2; // @[functional-unit.scala:237:23, :591:7] reg [5:0] r_uops_1_prs3; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_prs3_0 = r_uops_1_prs3; // @[functional-unit.scala:237:23, :591:7] reg [3:0] r_uops_1_ppred; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ppred_0 = r_uops_1_ppred; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_prs1_busy; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_prs1_busy_0 = r_uops_1_prs1_busy; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_prs2_busy; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_prs2_busy_0 = r_uops_1_prs2_busy; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_prs3_busy; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_prs3_busy_0 = r_uops_1_prs3_busy; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_ppred_busy; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ppred_busy_0 = r_uops_1_ppred_busy; // @[functional-unit.scala:237:23, :591:7] reg [5:0] r_uops_1_stale_pdst; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_stale_pdst_0 = r_uops_1_stale_pdst; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_exception; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_exception_0 = r_uops_1_exception; // @[functional-unit.scala:237:23, :591:7] reg [63:0] r_uops_1_exc_cause; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_exc_cause_0 = r_uops_1_exc_cause; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_bypassable; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_bypassable_0 = r_uops_1_bypassable; // @[functional-unit.scala:237:23, :591:7] reg [4:0] r_uops_1_mem_cmd; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_mem_cmd_0 = r_uops_1_mem_cmd; // @[functional-unit.scala:237:23, :591:7] reg [1:0] r_uops_1_mem_size; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_mem_size_0 = r_uops_1_mem_size; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_mem_signed; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_mem_signed_0 = r_uops_1_mem_signed; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_is_fence; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_fence_0 = r_uops_1_is_fence; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_is_fencei; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_fencei_0 = r_uops_1_is_fencei; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_is_amo; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_amo_0 = r_uops_1_is_amo; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_uses_ldq; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_uses_ldq_0 = r_uops_1_uses_ldq; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_uses_stq; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_uses_stq_0 = r_uops_1_uses_stq; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_is_sys_pc2epc; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_sys_pc2epc_0 = r_uops_1_is_sys_pc2epc; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_is_unique; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_unique_0 = r_uops_1_is_unique; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_flush_on_commit; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_flush_on_commit_0 = r_uops_1_flush_on_commit; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_ldst_is_rs1; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ldst_is_rs1_0 = r_uops_1_ldst_is_rs1; // @[functional-unit.scala:237:23, :591:7] reg [5:0] r_uops_1_ldst; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ldst_0 = r_uops_1_ldst; // @[functional-unit.scala:237:23, :591:7] reg [5:0] r_uops_1_lrs1; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_lrs1_0 = r_uops_1_lrs1; // @[functional-unit.scala:237:23, :591:7] reg [5:0] r_uops_1_lrs2; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_lrs2_0 = r_uops_1_lrs2; // @[functional-unit.scala:237:23, :591:7] reg [5:0] r_uops_1_lrs3; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_lrs3_0 = r_uops_1_lrs3; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_ldst_val; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ldst_val_0 = r_uops_1_ldst_val; // @[functional-unit.scala:237:23, :591:7] reg [1:0] r_uops_1_dst_rtype; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_dst_rtype_0 = r_uops_1_dst_rtype; // @[functional-unit.scala:237:23, :591:7] reg [1:0] r_uops_1_lrs1_rtype; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_lrs1_rtype_0 = r_uops_1_lrs1_rtype; // @[functional-unit.scala:237:23, :591:7] reg [1:0] r_uops_1_lrs2_rtype; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_lrs2_rtype_0 = r_uops_1_lrs2_rtype; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_frs3_en; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_frs3_en_0 = r_uops_1_frs3_en; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_fp_val; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_fp_val_0 = r_uops_1_fp_val; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_fp_single; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_fp_single_0 = r_uops_1_fp_single; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_xcpt_pf_if; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_xcpt_pf_if_0 = r_uops_1_xcpt_pf_if; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_xcpt_ae_if; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_xcpt_ae_if_0 = r_uops_1_xcpt_ae_if; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_xcpt_ma_if; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_xcpt_ma_if_0 = r_uops_1_xcpt_ma_if; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_bp_debug_if; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_bp_debug_if_0 = r_uops_1_bp_debug_if; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_bp_xcpt_if; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_bp_xcpt_if_0 = r_uops_1_bp_xcpt_if; // @[functional-unit.scala:237:23, :591:7] reg [1:0] r_uops_1_debug_fsrc; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_debug_fsrc_0 = r_uops_1_debug_fsrc; // @[functional-unit.scala:237:23, :591:7] reg [1:0] r_uops_1_debug_tsrc; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_debug_tsrc_0 = r_uops_1_debug_tsrc; // @[functional-unit.scala:237:23, :591:7] wire [7:0] _r_valids_0_T = io_brupdate_b1_mispredict_mask_0 & io_req_bits_uop_br_mask_0; // @[util.scala:118:51] wire _r_valids_0_T_1 = \|_r_valids_0_T; // @[util.scala:118:{51,59}] wire _r_valids_0_T_2 = ~_r_valids_0_T_1; // @[util.scala:118:59] wire _r_valids_0_T_3 = io_req_valid_0 & _r_valids_0_T_2; // @[functional-unit.scala:240:{33,36}, :591:7] wire _r_valids_0_T_4 = ~io_req_bits_kill_0; // @[functional-unit.scala:240:87, :591:7] wire _r_valids_0_T_5 = _r_valids_0_T_3 & _r_valids_0_T_4; // @[functional-unit.scala:240:{33,84,87}] wire [7:0] _r_uops_0_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27] wire [7:0] _r_uops_0_br_mask_T_1 = io_req_bits_uop_br_mask_0 & _r_uops_0_br_mask_T; // @[util.scala:85:{25,27}] wire [7:0] _r_valids_1_T = io_brupdate_b1_mispredict_mask_0 & r_uops_0_br_mask; // @[util.scala:118:51] wire _r_valids_1_T_1 = \|_r_valids_1_T; // @[util.scala:118:{51,59}] wire _r_valids_1_T_2 = ~_r_valids_1_T_1; // @[util.scala:118:59] wire _r_valids_1_T_3 = r_valids_0 & _r_valids_1_T_2; // @[functional-unit.scala:236:27, :246:{36,39}] wire _r_valids_1_T_4 = ~io_req_bits_kill_0; // @[functional-unit.scala:240:87, :246:86, :591:7] wire _r_valids_1_T_5 = _r_valids_1_T_3 & _r_valids_1_T_4; // @[functional-unit.scala:246:{36,83,86}] wire [7:0] _r_uops_1_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27] wire [7:0] _r_uops_1_br_mask_T_1 = r_uops_0_br_mask & _r_uops_1_br_mask_T; // @[util.scala:85:{25,27}] wire [7:0] _io_resp_valid_T = io_brupdate_b1_mispredict_mask_0 & r_uops_1_br_mask; // @[util.scala:118:51] wire _io_resp_valid_T_1 = \|_io_resp_valid_T; // @[util.scala:118:{51,59}] wire _io_resp_valid_T_2 = ~_io_resp_valid_T_1; // @[util.scala:118:59] assign _io_resp_valid_T_3 = r_valids_1 & _io_resp_valid_T_2; // @[functional-unit.scala:236:27, :257:{47,50}] assign io_resp_valid_0 = _io_resp_valid_T_3; // @[functional-unit.scala:257:47, :591:7] wire [7:0] _io_resp_bits_uop_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27] assign _io_resp_bits_uop_br_mask_T_1 = r_uops_1_br_mask & _io_resp_bits_uop_br_mask_T; // @[util.scala:85:{25,27}] assign io_resp_bits_uop_br_mask_0 = _io_resp_bits_uop_br_mask_T_1; // @[util.scala:85:25] wire [2:0] _fp_rm_T = io_req_bits_uop_imm_packed_0[2:0]; // @[util.scala:289:58] wire [2:0] _fp_rm_T_2 = io_req_bits_uop_imm_packed_0[2:0]; // @[util.scala:289:58] wire _fp_rm_T_1 = &_fp_rm_T; // @[util.scala:289:58] wire [2:0] fp_rm = _fp_rm_T_1 ? io_fcsr_rm_0 : _fp_rm_T_2; // @[util.scala:289:58] wire [2:0] req_rm = fp_rm; // @[functional-unit.scala:604:18, :605:17] wire [1:0] _req_typ_T; // @[util.scala:295:59] wire [64:0] _req_in1_T_4; // @[FPU.scala:369:10] wire [64:0] _req_in2_T_4; // @[FPU.scala:369:10] wire req_ldst; // @[functional-unit.scala:605:17] wire req_wen; // @[functional-unit.scala:605:17] wire req_ren1; // @[functional-unit.scala:605:17] wire req_ren2; // @[functional-unit.scala:605:17] wire req_ren3; // @[functional-unit.scala:605:17] wire req_swap12; // @[functional-unit.scala:605:17] wire req_swap23; // @[functional-unit.scala:605:17] wire [1:0] req_typeTagIn; // @[functional-unit.scala:605:17] wire [1:0] req_typeTagOut; // @[functional-unit.scala:605:17] wire req_fromint; // @[functional-unit.scala:605:17] wire req_toint; // @[functional-unit.scala:605:17] wire req_fastpipe; // @[functional-unit.scala:605:17] wire req_fma; // @[functional-unit.scala:605:17] wire req_div; // @[functional-unit.scala:605:17] wire req_sqrt; // @[functional-unit.scala:605:17] wire req_wflags; // @[functional-unit.scala:605:17] wire [1:0] req_typ; // @[functional-unit.scala:605:17] wire [64:0] req_in1; // @[functional-unit.scala:605:17] wire [64:0] req_in2; // @[functional-unit.scala:605:17] wire _req_in1_prev_unswizzled_T = io_req_bits_rs1_data_0[31]; // @[FPU.scala:357:14] wire _req_in1_prev_unswizzled_T_1 = io_req_bits_rs1_data_0[52]; // @[FPU.scala:358:14] wire [30:0] _req_in1_prev_unswizzled_T_2 = io_req_bits_rs1_data_0[30:0]; // @[FPU.scala:359:14] wire [1:0] req_in1_prev_unswizzled_hi = {_req_in1_prev_unswizzled_T, _req_in1_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] req_in1_prev_unswizzled = {req_in1_prev_unswizzled_hi, _req_in1_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire req_in1_prev_prev_sign = req_in1_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31] wire [22:0] req_in1_prev_prev_fractIn = req_in1_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31] wire [8:0] req_in1_prev_prev_expIn = req_in1_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31] wire [75:0] _req_in1_prev_prev_fractOut_T = {req_in1_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] req_in1_prev_prev_fractOut = _req_in1_prev_prev_fractOut_T[75:24]; // @[FPU.scala:277:{28,38}] wire [2:0] req_in1_prev_prev_expOut_expCode = req_in1_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26] wire [12:0] _req_in1_prev_prev_expOut_commonCase_T = {4'h0, req_in1_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _req_in1_prev_prev_expOut_commonCase_T_1 = _req_in1_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _req_in1_prev_prev_expOut_commonCase_T_2 = {1'h0, _req_in1_prev_prev_expOut_commonCase_T_1} - 13'h100; // @[FPU.scala:280:{31,50}] wire [11:0] req_in1_prev_prev_expOut_commonCase = _req_in1_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _req_in1_prev_prev_expOut_T_5 = req_in1_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _req_in1_prev_prev_expOut_T = req_in1_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _req_in1_prev_prev_expOut_T_1 = req_in1_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _req_in1_prev_prev_expOut_T_2 = _req_in1_prev_prev_expOut_T \| _req_in1_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _req_in1_prev_prev_expOut_T_3 = req_in1_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _req_in1_prev_prev_expOut_T_4 = {req_in1_prev_prev_expOut_expCode, _req_in1_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] req_in1_prev_prev_expOut = _req_in1_prev_prev_expOut_T_2 ? _req_in1_prev_prev_expOut_T_4 : _req_in1_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] req_in1_prev_prev_hi = {req_in1_prev_prev_sign, req_in1_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] req_in1_floats_0 = {req_in1_prev_prev_hi, req_in1_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire [4:0] _req_in1_prev_isbox_T = io_req_bits_rs1_data_0[64:60]; // @[FPU.scala:332:49] wire req_in1_prev_isbox = &_req_in1_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire req_in1_oks_0 = req_in1_prev_isbox; // @[FPU.scala:332:84, :362:32] wire [1:0] _req_in1_truncIdx_T; // @[package.scala:38:21] wire req_in1_truncIdx = _req_in1_truncIdx_T[0]; // @[package.scala:38:{21,47}] wire _req_in1_T = req_in1_truncIdx; // @[package.scala:38:47, :39:86] wire _req_in1_T_1 = _req_in1_T \| req_in1_oks_0; // @[package.scala:39:{76,86}] wire [1:0] _req_in1_truncIdx_T_1; // @[package.scala:38:21] wire req_in1_truncIdx_1 = _req_in1_truncIdx_T_1[0]; // @[package.scala:38:{21,47}] wire _req_in1_T_2 = req_in1_truncIdx_1; // @[package.scala:38:47, :39:86] wire [64:0] _req_in1_T_3 = _req_in1_T_2 ? io_req_bits_rs1_data_0 : req_in1_floats_0; // @[package.scala:39:{76,86}] assign _req_in1_T_4 = _req_in1_T_1 ? _req_in1_T_3 : 65'hE008000000000000; // @[package.scala:39:76] assign req_in1 = _req_in1_T_4; // @[FPU.scala:369:10] wire _req_in2_prev_unswizzled_T = io_req_bits_rs2_data_0[31]; // @[FPU.scala:357:14] wire _req_in2_prev_unswizzled_T_1 = io_req_bits_rs2_data_0[52]; // @[FPU.scala:358:14] wire [30:0] _req_in2_prev_unswizzled_T_2 = io_req_bits_rs2_data_0[30:0]; // @[FPU.scala:359:14] wire [1:0] req_in2_prev_unswizzled_hi = {_req_in2_prev_unswizzled_T, _req_in2_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] req_in2_prev_unswizzled = {req_in2_prev_unswizzled_hi, _req_in2_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire req_in2_prev_prev_sign = req_in2_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31] wire [22:0] req_in2_prev_prev_fractIn = req_in2_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31] wire [8:0] req_in2_prev_prev_expIn = req_in2_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31] wire [75:0] _req_in2_prev_prev_fractOut_T = {req_in2_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] req_in2_prev_prev_fractOut = _req_in2_prev_prev_fractOut_T[75:24]; // @[FPU.scala:277:{28,38}] wire [2:0] req_in2_prev_prev_expOut_expCode = req_in2_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26] wire [12:0] _req_in2_prev_prev_expOut_commonCase_T = {4'h0, req_in2_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _req_in2_prev_prev_expOut_commonCase_T_1 = _req_in2_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _req_in2_prev_prev_expOut_commonCase_T_2 = {1'h0, _req_in2_prev_prev_expOut_commonCase_T_1} - 13'h100; // @[FPU.scala:280:{31,50}] wire [11:0] req_in2_prev_prev_expOut_commonCase = _req_in2_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _req_in2_prev_prev_expOut_T_5 = req_in2_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _req_in2_prev_prev_expOut_T = req_in2_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _req_in2_prev_prev_expOut_T_1 = req_in2_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _req_in2_prev_prev_expOut_T_2 = _req_in2_prev_prev_expOut_T \| _req_in2_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _req_in2_prev_prev_expOut_T_3 = req_in2_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _req_in2_prev_prev_expOut_T_4 = {req_in2_prev_prev_expOut_expCode, _req_in2_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] req_in2_prev_prev_expOut = _req_in2_prev_prev_expOut_T_2 ? _req_in2_prev_prev_expOut_T_4 : _req_in2_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] req_in2_prev_prev_hi = {req_in2_prev_prev_sign, req_in2_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] req_in2_floats_0 = {req_in2_prev_prev_hi, req_in2_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire [4:0] _req_in2_prev_isbox_T = io_req_bits_rs2_data_0[64:60]; // @[FPU.scala:332:49] wire req_in2_prev_isbox = &_req_in2_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire req_in2_oks_0 = req_in2_prev_isbox; // @[FPU.scala:332:84, :362:32] wire [1:0] _req_in2_truncIdx_T; // @[package.scala:38:21] wire req_in2_truncIdx = _req_in2_truncIdx_T[0]; // @[package.scala:38:{21,47}] wire _req_in2_T = req_in2_truncIdx; // @[package.scala:38:47, :39:86] wire _req_in2_T_1 = _req_in2_T \| req_in2_oks_0; // @[package.scala:39:{76,86}] wire [1:0] _req_in2_truncIdx_T_1; // @[package.scala:38:21] wire req_in2_truncIdx_1 = _req_in2_truncIdx_T_1[0]; // @[package.scala:38:{21,47}] wire _req_in2_T_2 = req_in2_truncIdx_1; // @[package.scala:38:47, :39:86] wire [64:0] _req_in2_T_3 = _req_in2_T_2 ? io_req_bits_rs2_data_0 : req_in2_floats_0; // @[package.scala:39:{76,86}] assign _req_in2_T_4 = _req_in2_T_1 ? _req_in2_T_3 : 65'hE008000000000000; // @[package.scala:39:76] assign req_in2 = _req_in2_T_4; // @[FPU.scala:369:10] assign _req_typ_T = io_req_bits_uop_imm_packed_0[9:8]; // @[util.scala:295:59] assign req_typ = _req_typ_T; // @[util.scala:295:59]
Generate the Verilog code corresponding to the following Chisel files. File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Metadata.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.constants.MemoryOpConstants import freechips.rocketchip.util._ object ClientStates { val width = 2 def Nothing = 0.U(width.W) def Branch = 1.U(width.W) def Trunk = 2.U(width.W) def Dirty = 3.U(width.W) def hasReadPermission(state: UInt): Bool = state > Nothing def hasWritePermission(state: UInt): Bool = state > Branch } object MemoryOpCategories extends MemoryOpConstants { def wr = Cat(true.B, true.B) // Op actually writes def wi = Cat(false.B, true.B) // Future op will write def rd = Cat(false.B, false.B) // Op only reads def categorize(cmd: UInt): UInt = { val cat = Cat(isWrite(cmd), isWriteIntent(cmd)) //assert(cat.isOneOf(wr,wi,rd), "Could not categorize command.") cat } } /* Stores the client-side coherence information, * such as permissions on the data and whether the data is dirty. * Its API can be used to make TileLink messages in response to * memory operations, cache control oeprations, or Probe messages. / class ClientMetadata extends Bundle { /* Actual state information stored in this bundle / val state = UInt(ClientStates.width.W) /* Metadata equality / def ===(rhs: UInt): Bool = state === rhs def ===(rhs: ClientMetadata): Bool = state === rhs.state def =/=(rhs: ClientMetadata): Bool = !this.===(rhs) /* Is the block's data present in this cache / def isValid(dummy: Int = 0): Bool = state > ClientStates.Nothing /* Determine whether this cmd misses, and the new state (on hit) or param to be sent (on miss) / private def growStarter(cmd: UInt): (Bool, UInt) = { import MemoryOpCategories._ import TLPermissions._ import ClientStates._ val c = categorize(cmd) MuxTLookup(Cat(c, state), (false.B, 0.U), Seq( //(effect, am now) -> (was a hit, next) Cat(rd, Dirty) -> (true.B, Dirty), Cat(rd, Trunk) -> (true.B, Trunk), Cat(rd, Branch) -> (true.B, Branch), Cat(wi, Dirty) -> (true.B, Dirty), Cat(wi, Trunk) -> (true.B, Trunk), Cat(wr, Dirty) -> (true.B, Dirty), Cat(wr, Trunk) -> (true.B, Dirty), //(effect, am now) -> (was a miss, param) Cat(rd, Nothing) -> (false.B, NtoB), Cat(wi, Branch) -> (false.B, BtoT), Cat(wi, Nothing) -> (false.B, NtoT), Cat(wr, Branch) -> (false.B, BtoT), Cat(wr, Nothing) -> (false.B, NtoT))) } /* Determine what state to go to after miss based on Grant param * For now, doesn't depend on state (which may have been Probed). / private def growFinisher(cmd: UInt, param: UInt): UInt = { import MemoryOpCategories._ import TLPermissions._ import ClientStates._ val c = categorize(cmd) //assert(c === rd \|\| param === toT, "Client was expecting trunk permissions.") MuxLookup(Cat(c, param), Nothing)(Seq( //(effect param) -> (next) Cat(rd, toB) -> Branch, Cat(rd, toT) -> Trunk, Cat(wi, toT) -> Trunk, Cat(wr, toT) -> Dirty)) } /* Does this cache have permissions on this block sufficient to perform op, * and what to do next (Acquire message param or updated metadata). / def onAccess(cmd: UInt): (Bool, UInt, ClientMetadata) = { val r = growStarter(cmd) (r._1, r._2, ClientMetadata(r._2)) } /* Does a secondary miss on the block require another Acquire message / def onSecondaryAccess(first_cmd: UInt, second_cmd: UInt): (Bool, Bool, UInt, ClientMetadata, UInt) = { import MemoryOpCategories._ val r1 = growStarter(first_cmd) val r2 = growStarter(second_cmd) val needs_second_acq = isWriteIntent(second_cmd) && !isWriteIntent(first_cmd) val hit_again = r1._1 && r2._1 val dirties = categorize(second_cmd) === wr val biggest_grow_param = Mux(dirties, r2._2, r1._2) val dirtiest_state = ClientMetadata(biggest_grow_param) val dirtiest_cmd = Mux(dirties, second_cmd, first_cmd) (needs_second_acq, hit_again, biggest_grow_param, dirtiest_state, dirtiest_cmd) } /* Metadata change on a returned Grant / def onGrant(cmd: UInt, param: UInt): ClientMetadata = ClientMetadata(growFinisher(cmd, param)) /* Determine what state to go to based on Probe param / private def shrinkHelper(param: UInt): (Bool, UInt, UInt) = { import ClientStates._ import TLPermissions._ MuxTLookup(Cat(param, state), (false.B, 0.U, 0.U), Seq( //(wanted, am now) -> (hasDirtyData resp, next) Cat(toT, Dirty) -> (true.B, TtoT, Trunk), Cat(toT, Trunk) -> (false.B, TtoT, Trunk), Cat(toT, Branch) -> (false.B, BtoB, Branch), Cat(toT, Nothing) -> (false.B, NtoN, Nothing), Cat(toB, Dirty) -> (true.B, TtoB, Branch), Cat(toB, Trunk) -> (false.B, TtoB, Branch), // Policy: Don't notify on clean downgrade Cat(toB, Branch) -> (false.B, BtoB, Branch), Cat(toB, Nothing) -> (false.B, NtoN, Nothing), Cat(toN, Dirty) -> (true.B, TtoN, Nothing), Cat(toN, Trunk) -> (false.B, TtoN, Nothing), // Policy: Don't notify on clean downgrade Cat(toN, Branch) -> (false.B, BtoN, Nothing), // Policy: Don't notify on clean downgrade Cat(toN, Nothing) -> (false.B, NtoN, Nothing))) } /* Translate cache control cmds into Probe param / private def cmdToPermCap(cmd: UInt): UInt = { import MemoryOpCategories._ import TLPermissions._ MuxLookup(cmd, toN)(Seq( M_FLUSH -> toN, M_PRODUCE -> toB, M_CLEAN -> toT)) } def onCacheControl(cmd: UInt): (Bool, UInt, ClientMetadata) = { val r = shrinkHelper(cmdToPermCap(cmd)) (r._1, r._2, ClientMetadata(r._3)) } def onProbe(param: UInt): (Bool, UInt, ClientMetadata) = { val r = shrinkHelper(param) (r._1, r._2, ClientMetadata(r._3)) } } /* Factories for ClientMetadata, including on reset / object ClientMetadata { def apply(perm: UInt) = { val meta = Wire(new ClientMetadata) meta.state := perm meta } def onReset = ClientMetadata(ClientStates.Nothing) def maximum = ClientMetadata(ClientStates.Dirty) } File Replacement.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import freechips.rocketchip.util.property.cover abstract class ReplacementPolicy { def nBits: Int def perSet: Boolean def way: UInt def miss: Unit def hit: Unit def access(touch_way: UInt): Unit def access(touch_ways: Seq[Valid[UInt]]): Unit def state_read: UInt def get_next_state(state: UInt, touch_way: UInt): UInt def get_next_state(state: UInt, touch_ways: Seq[Valid[UInt]]): UInt = { touch_ways.foldLeft(state)((prev, touch_way) => Mux(touch_way.valid, get_next_state(prev, touch_way.bits), prev)) } def get_replace_way(state: UInt): UInt } object ReplacementPolicy { def fromString(s: String, n_ways: Int): ReplacementPolicy = s.toLowerCase match { case "random" => new RandomReplacement(n_ways) case "lru" => new TrueLRU(n_ways) case "plru" => new PseudoLRU(n_ways) case t => throw new IllegalArgumentException(s"unknown Replacement Policy type $t") } } class RandomReplacement(n_ways: Int) extends ReplacementPolicy { private val replace = Wire(Bool()) replace := false.B def nBits = 16 def perSet = false private val lfsr = LFSR(nBits, replace) def state_read = WireDefault(lfsr) def way = Random(n_ways, lfsr) def miss = replace := true.B def hit = {} def access(touch_way: UInt) = {} def access(touch_ways: Seq[Valid[UInt]]) = {} def get_next_state(state: UInt, touch_way: UInt) = 0.U //DontCare def get_replace_way(state: UInt) = way } abstract class SeqReplacementPolicy { def access(set: UInt): Unit def update(valid: Bool, hit: Bool, set: UInt, way: UInt): Unit def way: UInt } abstract class SetAssocReplacementPolicy { def access(set: UInt, touch_way: UInt): Unit def access(sets: Seq[UInt], touch_ways: Seq[Valid[UInt]]): Unit def way(set: UInt): UInt } class SeqRandom(n_ways: Int) extends SeqReplacementPolicy { val logic = new RandomReplacement(n_ways) def access(set: UInt) = { } def update(valid: Bool, hit: Bool, set: UInt, way: UInt) = { when (valid && !hit) { logic.miss } } def way = logic.way } class TrueLRU(n_ways: Int) extends ReplacementPolicy { // True LRU replacement policy, using a triangular matrix to track which sets are more recently used than others. // The matrix is packed into a single UInt (or Bits). Example 4-way (6-bits): // [5] - 3 more recent than 2 // [4] - 3 more recent than 1 // [3] - 2 more recent than 1 // [2] - 3 more recent than 0 // [1] - 2 more recent than 0 // [0] - 1 more recent than 0 def nBits = (n_ways (n_ways-1)) / 2 def perSet = true private val state_reg = RegInit(0.U(nBits.W)) def state_read = WireDefault(state_reg) private def extractMRUVec(state: UInt): Seq[UInt] = { // Extract per-way information about which higher-indexed ways are more recently used val moreRecentVec = Wire(Vec(n_ways-1, UInt(n_ways.W))) var lsb = 0 for (i <- 0 until n_ways-1) { moreRecentVec(i) := Cat(state(lsb+n_ways-i-2,lsb), 0.U((i+1).W)) lsb = lsb + (n_ways - i - 1) } moreRecentVec } def get_next_state(state: UInt, touch_way: UInt): UInt = { val nextState = Wire(Vec(n_ways-1, UInt(n_ways.W))) val moreRecentVec = extractMRUVec(state) // reconstruct lower triangular matrix val wayDec = UIntToOH(touch_way, n_ways) // Compute next value of triangular matrix // set the touched way as more recent than every other way nextState.zipWithIndex.map { case (e, i) => e := Mux(i.U === touch_way, 0.U(n_ways.W), moreRecentVec(i) \| wayDec) } nextState.zipWithIndex.tail.foldLeft((nextState.head.apply(n_ways-1,1),0)) { case ((pe,pi),(ce,ci)) => (Cat(ce.apply(n_ways-1,ci+1), pe), ci) }._1 } def access(touch_way: UInt): Unit = { state_reg := get_next_state(state_reg, touch_way) } def access(touch_ways: Seq[Valid[UInt]]): Unit = { when (touch_ways.map(_.valid).orR) { state_reg := get_next_state(state_reg, touch_ways) } for (i <- 1 until touch_ways.size) { cover(PopCount(touch_ways.map(_.valid)) === i.U, s"LRU_UpdateCount$i", s"LRU Update $i simultaneous") } } def get_replace_way(state: UInt): UInt = { val moreRecentVec = extractMRUVec(state) // reconstruct lower triangular matrix // For each way, determine if all other ways are more recent val mruWayDec = (0 until n_ways).map { i => val upperMoreRecent = (if (i == n_ways-1) true.B else moreRecentVec(i).apply(n_ways-1,i+1).andR) val lowerMoreRecent = (if (i == 0) true.B else moreRecentVec.map(e => !e(i)).reduce(_ && _)) upperMoreRecent && lowerMoreRecent } OHToUInt(mruWayDec) } def way = get_replace_way(state_reg) def miss = access(way) def hit = {} @deprecated("replace 'replace' with 'way' from abstract class ReplacementPolicy","Rocket Chip 2020.05") def replace: UInt = way } class PseudoLRU(n_ways: Int) extends ReplacementPolicy { // Pseudo-LRU tree algorithm: https://en.wikipedia.org/wiki/Pseudo-LRU#Tree-PLRU // // // - bits storage example for 4-way PLRU binary tree: // bit[2]: ways 3+2 older than ways 1+0 // / \ // bit[1]: way 3 older than way 2 bit[0]: way 1 older than way 0 // // // - bits storage example for 3-way PLRU binary tree: // bit[1]: way 2 older than ways 1+0 // \ // bit[0]: way 1 older than way 0 // // // - bits storage example for 8-way PLRU binary tree: // bit[6]: ways 7-4 older than ways 3-0 // / \ // bit[5]: ways 7+6 > 5+4 bit[2]: ways 3+2 > 1+0 // / \ / \ // bit[4]: way 7>6 bit[3]: way 5>4 bit[1]: way 3>2 bit[0]: way 1>0 def nBits = n_ways - 1 def perSet = true private val state_reg = if (nBits == 0) Reg(UInt(0.W)) else RegInit(0.U(nBits.W)) def state_read = WireDefault(state_reg) def access(touch_way: UInt): Unit = { state_reg := get_next_state(state_reg, touch_way) } def access(touch_ways: Seq[Valid[UInt]]): Unit = { when (touch_ways.map(_.valid).orR) { state_reg := get_next_state(state_reg, touch_ways) } for (i <- 1 until touch_ways.size) { cover(PopCount(touch_ways.map(_.valid)) === i.U, s"PLRU_UpdateCount$i", s"PLRU Update $i simultaneous") } } /** @param state state_reg bits for this sub-tree * @param touch_way touched way encoded value bits for this sub-tree * @param tree_nways number of ways in this sub-tree / def get_next_state(state: UInt, touch_way: UInt, tree_nways: Int): UInt = { require(state.getWidth == (tree_nways-1), s"wrong state bits width ${state.getWidth} for $tree_nways ways") require(touch_way.getWidth == (log2Ceil(tree_nways) max 1), s"wrong encoded way width ${touch_way.getWidth} for $tree_nways ways") if (tree_nways > 2) { // we are at a branching node in the tree, so recurse val right_nways: Int = 1 << (log2Ceil(tree_nways) - 1) // number of ways in the right sub-tree val left_nways: Int = tree_nways - right_nways // number of ways in the left sub-tree val set_left_older = !touch_way(log2Ceil(tree_nways)-1) val left_subtree_state = state.extract(tree_nways-3, right_nways-1) val right_subtree_state = state(right_nways-2, 0) if (left_nways > 1) { // we are at a branching node in the tree with both left and right sub-trees, so recurse both sub-trees Cat(set_left_older, Mux(set_left_older, left_subtree_state, // if setting left sub-tree as older, do NOT recurse into left sub-tree get_next_state(left_subtree_state, touch_way.extract(log2Ceil(left_nways)-1,0), left_nways)), // recurse left if newer Mux(set_left_older, get_next_state(right_subtree_state, touch_way(log2Ceil(right_nways)-1,0), right_nways), // recurse right if newer right_subtree_state)) // if setting right sub-tree as older, do NOT recurse into right sub-tree } else { // we are at a branching node in the tree with only a right sub-tree, so recurse only right sub-tree Cat(set_left_older, Mux(set_left_older, get_next_state(right_subtree_state, touch_way(log2Ceil(right_nways)-1,0), right_nways), // recurse right if newer right_subtree_state)) // if setting right sub-tree as older, do NOT recurse into right sub-tree } } else if (tree_nways == 2) { // we are at a leaf node at the end of the tree, so set the single state bit opposite of the lsb of the touched way encoded value !touch_way(0) } else { // tree_nways <= 1 // we are at an empty node in an empty tree for 1 way, so return single zero bit for Chisel (no zero-width wires) 0.U(1.W) } } def get_next_state(state: UInt, touch_way: UInt): UInt = { val touch_way_sized = if (touch_way.getWidth < log2Ceil(n_ways)) touch_way.padTo (log2Ceil(n_ways)) else touch_way.extract(log2Ceil(n_ways)-1,0) get_next_state(state, touch_way_sized, n_ways) } /* @param state state_reg bits for this sub-tree * @param tree_nways number of ways in this sub-tree / def get_replace_way(state: UInt, tree_nways: Int): UInt = { require(state.getWidth == (tree_nways-1), s"wrong state bits width ${state.getWidth} for $tree_nways ways") // this algorithm recursively descends the binary tree, filling in the way-to-replace encoded value from msb to lsb if (tree_nways > 2) { // we are at a branching node in the tree, so recurse val right_nways: Int = 1 << (log2Ceil(tree_nways) - 1) // number of ways in the right sub-tree val left_nways: Int = tree_nways - right_nways // number of ways in the left sub-tree val left_subtree_older = state(tree_nways-2) val left_subtree_state = state.extract(tree_nways-3, right_nways-1) val right_subtree_state = state(right_nways-2, 0) if (left_nways > 1) { // we are at a branching node in the tree with both left and right sub-trees, so recurse both sub-trees Cat(left_subtree_older, // return the top state bit (current tree node) as msb of the way-to-replace encoded value Mux(left_subtree_older, // if left sub-tree is older, recurse left, else recurse right get_replace_way(left_subtree_state, left_nways), // recurse left get_replace_way(right_subtree_state, right_nways))) // recurse right } else { // we are at a branching node in the tree with only a right sub-tree, so recurse only right sub-tree Cat(left_subtree_older, // return the top state bit (current tree node) as msb of the way-to-replace encoded value Mux(left_subtree_older, // if left sub-tree is older, return and do not recurse right 0.U(1.W), get_replace_way(right_subtree_state, right_nways))) // recurse right } } else if (tree_nways == 2) { // we are at a leaf node at the end of the tree, so just return the single state bit as lsb of the way-to-replace encoded value state(0) } else { // tree_nways <= 1 // we are at an empty node in an unbalanced tree for non-power-of-2 ways, so return single zero bit as lsb of the way-to-replace encoded value 0.U(1.W) } } def get_replace_way(state: UInt): UInt = get_replace_way(state, n_ways) def way = get_replace_way(state_reg) def miss = access(way) def hit = {} } class SeqPLRU(n_sets: Int, n_ways: Int) extends SeqReplacementPolicy { val logic = new PseudoLRU(n_ways) val state = SyncReadMem(n_sets, UInt(logic.nBits.W)) val current_state = Wire(UInt(logic.nBits.W)) val next_state = Wire(UInt(logic.nBits.W)) val plru_way = logic.get_replace_way(current_state) def access(set: UInt) = { current_state := state.read(set) } def update(valid: Bool, hit: Bool, set: UInt, way: UInt) = { val update_way = Mux(hit, way, plru_way) next_state := logic.get_next_state(current_state, update_way) when (valid) { state.write(set, next_state) } } def way = plru_way } class SetAssocLRU(n_sets: Int, n_ways: Int, policy: String) extends SetAssocReplacementPolicy { val logic = policy.toLowerCase match { case "plru" => new PseudoLRU(n_ways) case "lru" => new TrueLRU(n_ways) case t => throw new IllegalArgumentException(s"unknown Replacement Policy type $t") } val state_vec = if (logic.nBits == 0) Reg(Vec(n_sets, UInt(logic.nBits.W))) // Work around elaboration error on following line else RegInit(VecInit(Seq.fill(n_sets)(0.U(logic.nBits.W)))) def access(set: UInt, touch_way: UInt) = { state_vec(set) := logic.get_next_state(state_vec(set), touch_way) } def access(sets: Seq[UInt], touch_ways: Seq[Valid[UInt]]) = { require(sets.size == touch_ways.size, "internal consistency check: should be same number of simultaneous updates for sets and touch_ways") for (set <- 0 until n_sets) { val set_touch_ways = (sets zip touch_ways).map { case (touch_set, touch_way) => Pipe(touch_way.valid && (touch_set === set.U), touch_way.bits, 0)} when (set_touch_ways.map(_.valid).orR) { state_vec(set) := logic.get_next_state(state_vec(set), set_touch_ways) } } } def way(set: UInt) = logic.get_replace_way(state_vec(set)) } // Synthesizable unit tests import freechips.rocketchip.unittest._ class PLRUTest(n_ways: Int, timeout: Int = 500) extends UnitTest(timeout) { val plru = new PseudoLRU(n_ways) // step io.finished := RegNext(true.B, false.B) val get_replace_ways = (0 until (1 << (n_ways-1))).map(state => plru.get_replace_way(state = state.U((n_ways-1).W))) val get_next_states = (0 until (1 << (n_ways-1))).map(state => (0 until n_ways).map(way => plru.get_next_state (state = state.U((n_ways-1).W), touch_way = way.U(log2Ceil(n_ways).W)))) n_ways match { case 2 => { assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0)) assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1)) assert(get_next_states(0)(0) === 1.U(plru.nBits.W), s"get_next_state state=0 way=0: expected=1 actual=%d", get_next_states(0)(0)) assert(get_next_states(0)(1) === 0.U(plru.nBits.W), s"get_next_state state=0 way=1: expected=0 actual=%d", get_next_states(0)(1)) assert(get_next_states(1)(0) === 1.U(plru.nBits.W), s"get_next_state state=1 way=0: expected=1 actual=%d", get_next_states(1)(0)) assert(get_next_states(1)(1) === 0.U(plru.nBits.W), s"get_next_state state=1 way=1: expected=0 actual=%d", get_next_states(1)(1)) } case 3 => { assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0)) assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1)) assert(get_replace_ways(2) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=2: expected=2 actual=%d", get_replace_ways(2)) assert(get_replace_ways(3) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=3: expected=2 actual=%d", get_replace_ways(3)) assert(get_next_states(0)(0) === 3.U(plru.nBits.W), s"get_next_state state=0 way=0: expected=3 actual=%d", get_next_states(0)(0)) assert(get_next_states(0)(1) === 2.U(plru.nBits.W), s"get_next_state state=0 way=1: expected=2 actual=%d", get_next_states(0)(1)) assert(get_next_states(0)(2) === 0.U(plru.nBits.W), s"get_next_state state=0 way=2: expected=0 actual=%d", get_next_states(0)(2)) assert(get_next_states(1)(0) === 3.U(plru.nBits.W), s"get_next_state state=1 way=0: expected=3 actual=%d", get_next_states(1)(0)) assert(get_next_states(1)(1) === 2.U(plru.nBits.W), s"get_next_state state=1 way=1: expected=2 actual=%d", get_next_states(1)(1)) assert(get_next_states(1)(2) === 1.U(plru.nBits.W), s"get_next_state state=1 way=2: expected=1 actual=%d", get_next_states(1)(2)) assert(get_next_states(2)(0) === 3.U(plru.nBits.W), s"get_next_state state=2 way=0: expected=3 actual=%d", get_next_states(2)(0)) assert(get_next_states(2)(1) === 2.U(plru.nBits.W), s"get_next_state state=2 way=1: expected=2 actual=%d", get_next_states(2)(1)) assert(get_next_states(2)(2) === 0.U(plru.nBits.W), s"get_next_state state=2 way=2: expected=0 actual=%d", get_next_states(2)(2)) assert(get_next_states(3)(0) === 3.U(plru.nBits.W), s"get_next_state state=3 way=0: expected=3 actual=%d", get_next_states(3)(0)) assert(get_next_states(3)(1) === 2.U(plru.nBits.W), s"get_next_state state=3 way=1: expected=2 actual=%d", get_next_states(3)(1)) assert(get_next_states(3)(2) === 1.U(plru.nBits.W), s"get_next_state state=3 way=2: expected=1 actual=%d", get_next_states(3)(2)) } case 4 => { assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0)) assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1)) assert(get_replace_ways(2) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=2: expected=0 actual=%d", get_replace_ways(2)) assert(get_replace_ways(3) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=3: expected=1 actual=%d", get_replace_ways(3)) assert(get_replace_ways(4) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=4: expected=2 actual=%d", get_replace_ways(4)) assert(get_replace_ways(5) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=5: expected=2 actual=%d", get_replace_ways(5)) assert(get_replace_ways(6) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=6: expected=3 actual=%d", get_replace_ways(6)) assert(get_replace_ways(7) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=7: expected=3 actual=%d", get_replace_ways(7)) assert(get_next_states(0)(0) === 5.U(plru.nBits.W), s"get_next_state state=0 way=0: expected=5 actual=%d", get_next_states(0)(0)) assert(get_next_states(0)(1) === 4.U(plru.nBits.W), s"get_next_state state=0 way=1: expected=4 actual=%d", get_next_states(0)(1)) assert(get_next_states(0)(2) === 2.U(plru.nBits.W), s"get_next_state state=0 way=2: expected=2 actual=%d", get_next_states(0)(2)) assert(get_next_states(0)(3) === 0.U(plru.nBits.W), s"get_next_state state=0 way=3: expected=0 actual=%d", get_next_states(0)(3)) assert(get_next_states(1)(0) === 5.U(plru.nBits.W), s"get_next_state state=1 way=0: expected=5 actual=%d", get_next_states(1)(0)) assert(get_next_states(1)(1) === 4.U(plru.nBits.W), s"get_next_state state=1 way=1: expected=4 actual=%d", get_next_states(1)(1)) assert(get_next_states(1)(2) === 3.U(plru.nBits.W), s"get_next_state state=1 way=2: expected=3 actual=%d", get_next_states(1)(2)) assert(get_next_states(1)(3) === 1.U(plru.nBits.W), s"get_next_state state=1 way=3: expected=1 actual=%d", get_next_states(1)(3)) assert(get_next_states(2)(0) === 7.U(plru.nBits.W), s"get_next_state state=2 way=0: expected=7 actual=%d", get_next_states(2)(0)) assert(get_next_states(2)(1) === 6.U(plru.nBits.W), s"get_next_state state=2 way=1: expected=6 actual=%d", get_next_states(2)(1)) assert(get_next_states(2)(2) === 2.U(plru.nBits.W), s"get_next_state state=2 way=2: expected=2 actual=%d", get_next_states(2)(2)) assert(get_next_states(2)(3) === 0.U(plru.nBits.W), s"get_next_state state=2 way=3: expected=0 actual=%d", get_next_states(2)(3)) assert(get_next_states(3)(0) === 7.U(plru.nBits.W), s"get_next_state state=3 way=0: expected=7 actual=%d", get_next_states(3)(0)) assert(get_next_states(3)(1) === 6.U(plru.nBits.W), s"get_next_state state=3 way=1: expected=6 actual=%d", get_next_states(3)(1)) assert(get_next_states(3)(2) === 3.U(plru.nBits.W), s"get_next_state state=3 way=2: expected=3 actual=%d", get_next_states(3)(2)) assert(get_next_states(3)(3) === 1.U(plru.nBits.W), s"get_next_state state=3 way=3: expected=1 actual=%d", get_next_states(3)(3)) assert(get_next_states(4)(0) === 5.U(plru.nBits.W), s"get_next_state state=4 way=0: expected=5 actual=%d", get_next_states(4)(0)) assert(get_next_states(4)(1) === 4.U(plru.nBits.W), s"get_next_state state=4 way=1: expected=4 actual=%d", get_next_states(4)(1)) assert(get_next_states(4)(2) === 2.U(plru.nBits.W), s"get_next_state state=4 way=2: expected=2 actual=%d", get_next_states(4)(2)) assert(get_next_states(4)(3) === 0.U(plru.nBits.W), s"get_next_state state=4 way=3: expected=0 actual=%d", get_next_states(4)(3)) assert(get_next_states(5)(0) === 5.U(plru.nBits.W), s"get_next_state state=5 way=0: expected=5 actual=%d", get_next_states(5)(0)) assert(get_next_states(5)(1) === 4.U(plru.nBits.W), s"get_next_state state=5 way=1: expected=4 actual=%d", get_next_states(5)(1)) assert(get_next_states(5)(2) === 3.U(plru.nBits.W), s"get_next_state state=5 way=2: expected=3 actual=%d", get_next_states(5)(2)) assert(get_next_states(5)(3) === 1.U(plru.nBits.W), s"get_next_state state=5 way=3: expected=1 actual=%d", get_next_states(5)(3)) assert(get_next_states(6)(0) === 7.U(plru.nBits.W), s"get_next_state state=6 way=0: expected=7 actual=%d", get_next_states(6)(0)) assert(get_next_states(6)(1) === 6.U(plru.nBits.W), s"get_next_state state=6 way=1: expected=6 actual=%d", get_next_states(6)(1)) assert(get_next_states(6)(2) === 2.U(plru.nBits.W), s"get_next_state state=6 way=2: expected=2 actual=%d", get_next_states(6)(2)) assert(get_next_states(6)(3) === 0.U(plru.nBits.W), s"get_next_state state=6 way=3: expected=0 actual=%d", get_next_states(6)(3)) assert(get_next_states(7)(0) === 7.U(plru.nBits.W), s"get_next_state state=7 way=0: expected=7 actual=%d", get_next_states(7)(0)) assert(get_next_states(7)(1) === 6.U(plru.nBits.W), s"get_next_state state=7 way=5: expected=6 actual=%d", get_next_states(7)(1)) assert(get_next_states(7)(2) === 3.U(plru.nBits.W), s"get_next_state state=7 way=2: expected=3 actual=%d", get_next_states(7)(2)) assert(get_next_states(7)(3) === 1.U(plru.nBits.W), s"get_next_state state=7 way=3: expected=1 actual=%d", get_next_states(7)(3)) } case 5 => { assert(get_replace_ways( 0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=00: expected=0 actual=%d", get_replace_ways( 0)) assert(get_replace_ways( 1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=01: expected=1 actual=%d", get_replace_ways( 1)) assert(get_replace_ways( 2) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=02: expected=0 actual=%d", get_replace_ways( 2)) assert(get_replace_ways( 3) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=03: expected=1 actual=%d", get_replace_ways( 3)) assert(get_replace_ways( 4) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=04: expected=2 actual=%d", get_replace_ways( 4)) assert(get_replace_ways( 5) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=05: expected=2 actual=%d", get_replace_ways( 5)) assert(get_replace_ways( 6) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=06: expected=3 actual=%d", get_replace_ways( 6)) assert(get_replace_ways( 7) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=07: expected=3 actual=%d", get_replace_ways( 7)) assert(get_replace_ways( 8) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=08: expected=4 actual=%d", get_replace_ways( 8)) assert(get_replace_ways( 9) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=09: expected=4 actual=%d", get_replace_ways( 9)) assert(get_replace_ways(10) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=10: expected=4 actual=%d", get_replace_ways(10)) assert(get_replace_ways(11) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=11: expected=4 actual=%d", get_replace_ways(11)) assert(get_replace_ways(12) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=12: expected=4 actual=%d", get_replace_ways(12)) assert(get_replace_ways(13) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=13: expected=4 actual=%d", get_replace_ways(13)) assert(get_replace_ways(14) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=14: expected=4 actual=%d", get_replace_ways(14)) assert(get_replace_ways(15) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=15: expected=4 actual=%d", get_replace_ways(15)) assert(get_next_states( 0)(0) === 13.U(plru.nBits.W), s"get_next_state state=00 way=0: expected=13 actual=%d", get_next_states( 0)(0)) assert(get_next_states( 0)(1) === 12.U(plru.nBits.W), s"get_next_state state=00 way=1: expected=12 actual=%d", get_next_states( 0)(1)) assert(get_next_states( 0)(2) === 10.U(plru.nBits.W), s"get_next_state state=00 way=2: expected=10 actual=%d", get_next_states( 0)(2)) assert(get_next_states( 0)(3) === 8.U(plru.nBits.W), s"get_next_state state=00 way=3: expected=08 actual=%d", get_next_states( 0)(3)) assert(get_next_states( 0)(4) === 0.U(plru.nBits.W), s"get_next_state state=00 way=4: expected=00 actual=%d", get_next_states( 0)(4)) assert(get_next_states( 1)(0) === 13.U(plru.nBits.W), s"get_next_state state=01 way=0: expected=13 actual=%d", get_next_states( 1)(0)) assert(get_next_states( 1)(1) === 12.U(plru.nBits.W), s"get_next_state state=01 way=1: expected=12 actual=%d", get_next_states( 1)(1)) assert(get_next_states( 1)(2) === 11.U(plru.nBits.W), s"get_next_state state=01 way=2: expected=11 actual=%d", get_next_states( 1)(2)) assert(get_next_states( 1)(3) === 9.U(plru.nBits.W), s"get_next_state state=01 way=3: expected=09 actual=%d", get_next_states( 1)(3)) assert(get_next_states( 1)(4) === 1.U(plru.nBits.W), s"get_next_state state=01 way=4: expected=01 actual=%d", get_next_states( 1)(4)) assert(get_next_states( 2)(0) === 15.U(plru.nBits.W), s"get_next_state state=02 way=0: expected=15 actual=%d", get_next_states( 2)(0)) assert(get_next_states( 2)(1) === 14.U(plru.nBits.W), s"get_next_state state=02 way=1: expected=14 actual=%d", get_next_states( 2)(1)) assert(get_next_states( 2)(2) === 10.U(plru.nBits.W), s"get_next_state state=02 way=2: expected=10 actual=%d", get_next_states( 2)(2)) assert(get_next_states( 2)(3) === 8.U(plru.nBits.W), s"get_next_state state=02 way=3: expected=08 actual=%d", get_next_states( 2)(3)) assert(get_next_states( 2)(4) === 2.U(plru.nBits.W), s"get_next_state state=02 way=4: expected=02 actual=%d", get_next_states( 2)(4)) assert(get_next_states( 3)(0) === 15.U(plru.nBits.W), s"get_next_state state=03 way=0: expected=15 actual=%d", get_next_states( 3)(0)) assert(get_next_states( 3)(1) === 14.U(plru.nBits.W), s"get_next_state state=03 way=1: expected=14 actual=%d", get_next_states( 3)(1)) assert(get_next_states( 3)(2) === 11.U(plru.nBits.W), s"get_next_state state=03 way=2: expected=11 actual=%d", get_next_states( 3)(2)) assert(get_next_states( 3)(3) === 9.U(plru.nBits.W), s"get_next_state state=03 way=3: expected=09 actual=%d", get_next_states( 3)(3)) assert(get_next_states( 3)(4) === 3.U(plru.nBits.W), s"get_next_state state=03 way=4: expected=03 actual=%d", get_next_states( 3)(4)) assert(get_next_states( 4)(0) === 13.U(plru.nBits.W), s"get_next_state state=04 way=0: expected=13 actual=%d", get_next_states( 4)(0)) assert(get_next_states( 4)(1) === 12.U(plru.nBits.W), s"get_next_state state=04 way=1: expected=12 actual=%d", get_next_states( 4)(1)) assert(get_next_states( 4)(2) === 10.U(plru.nBits.W), s"get_next_state state=04 way=2: expected=10 actual=%d", get_next_states( 4)(2)) assert(get_next_states( 4)(3) === 8.U(plru.nBits.W), s"get_next_state state=04 way=3: expected=08 actual=%d", get_next_states( 4)(3)) assert(get_next_states( 4)(4) === 4.U(plru.nBits.W), s"get_next_state state=04 way=4: expected=04 actual=%d", get_next_states( 4)(4)) assert(get_next_states( 5)(0) === 13.U(plru.nBits.W), s"get_next_state state=05 way=0: expected=13 actual=%d", get_next_states( 5)(0)) assert(get_next_states( 5)(1) === 12.U(plru.nBits.W), s"get_next_state state=05 way=1: expected=12 actual=%d", get_next_states( 5)(1)) assert(get_next_states( 5)(2) === 11.U(plru.nBits.W), s"get_next_state state=05 way=2: expected=11 actual=%d", get_next_states( 5)(2)) assert(get_next_states( 5)(3) === 9.U(plru.nBits.W), s"get_next_state state=05 way=3: expected=09 actual=%d", get_next_states( 5)(3)) assert(get_next_states( 5)(4) === 5.U(plru.nBits.W), s"get_next_state state=05 way=4: expected=05 actual=%d", get_next_states( 5)(4)) assert(get_next_states( 6)(0) === 15.U(plru.nBits.W), s"get_next_state state=06 way=0: expected=15 actual=%d", get_next_states( 6)(0)) assert(get_next_states( 6)(1) === 14.U(plru.nBits.W), s"get_next_state state=06 way=1: expected=14 actual=%d", get_next_states( 6)(1)) assert(get_next_states( 6)(2) === 10.U(plru.nBits.W), s"get_next_state state=06 way=2: expected=10 actual=%d", get_next_states( 6)(2)) assert(get_next_states( 6)(3) === 8.U(plru.nBits.W), s"get_next_state state=06 way=3: expected=08 actual=%d", get_next_states( 6)(3)) assert(get_next_states( 6)(4) === 6.U(plru.nBits.W), s"get_next_state state=06 way=4: expected=06 actual=%d", get_next_states( 6)(4)) assert(get_next_states( 7)(0) === 15.U(plru.nBits.W), s"get_next_state state=07 way=0: expected=15 actual=%d", get_next_states( 7)(0)) assert(get_next_states( 7)(1) === 14.U(plru.nBits.W), s"get_next_state state=07 way=5: expected=14 actual=%d", get_next_states( 7)(1)) assert(get_next_states( 7)(2) === 11.U(plru.nBits.W), s"get_next_state state=07 way=2: expected=11 actual=%d", get_next_states( 7)(2)) assert(get_next_states( 7)(3) === 9.U(plru.nBits.W), s"get_next_state state=07 way=3: expected=09 actual=%d", get_next_states( 7)(3)) assert(get_next_states( 7)(4) === 7.U(plru.nBits.W), s"get_next_state state=07 way=4: expected=07 actual=%d", get_next_states( 7)(4)) assert(get_next_states( 8)(0) === 13.U(plru.nBits.W), s"get_next_state state=08 way=0: expected=13 actual=%d", get_next_states( 8)(0)) assert(get_next_states( 8)(1) === 12.U(plru.nBits.W), s"get_next_state state=08 way=1: expected=12 actual=%d", get_next_states( 8)(1)) assert(get_next_states( 8)(2) === 10.U(plru.nBits.W), s"get_next_state state=08 way=2: expected=10 actual=%d", get_next_states( 8)(2)) assert(get_next_states( 8)(3) === 8.U(plru.nBits.W), s"get_next_state state=08 way=3: expected=08 actual=%d", get_next_states( 8)(3)) assert(get_next_states( 8)(4) === 0.U(plru.nBits.W), s"get_next_state state=08 way=4: expected=00 actual=%d", get_next_states( 8)(4)) assert(get_next_states( 9)(0) === 13.U(plru.nBits.W), s"get_next_state state=09 way=0: expected=13 actual=%d", get_next_states( 9)(0)) assert(get_next_states( 9)(1) === 12.U(plru.nBits.W), s"get_next_state state=09 way=1: expected=12 actual=%d", get_next_states( 9)(1)) assert(get_next_states( 9)(2) === 11.U(plru.nBits.W), s"get_next_state state=09 way=2: expected=11 actual=%d", get_next_states( 9)(2)) assert(get_next_states( 9)(3) === 9.U(plru.nBits.W), s"get_next_state state=09 way=3: expected=09 actual=%d", get_next_states( 9)(3)) assert(get_next_states( 9)(4) === 1.U(plru.nBits.W), s"get_next_state state=09 way=4: expected=01 actual=%d", get_next_states( 9)(4)) assert(get_next_states(10)(0) === 15.U(plru.nBits.W), s"get_next_state state=10 way=0: expected=15 actual=%d", get_next_states(10)(0)) assert(get_next_states(10)(1) === 14.U(plru.nBits.W), s"get_next_state state=10 way=1: expected=14 actual=%d", get_next_states(10)(1)) assert(get_next_states(10)(2) === 10.U(plru.nBits.W), s"get_next_state state=10 way=2: expected=10 actual=%d", get_next_states(10)(2)) assert(get_next_states(10)(3) === 8.U(plru.nBits.W), s"get_next_state state=10 way=3: expected=08 actual=%d", get_next_states(10)(3)) assert(get_next_states(10)(4) === 2.U(plru.nBits.W), s"get_next_state state=10 way=4: expected=02 actual=%d", get_next_states(10)(4)) assert(get_next_states(11)(0) === 15.U(plru.nBits.W), s"get_next_state state=11 way=0: expected=15 actual=%d", get_next_states(11)(0)) assert(get_next_states(11)(1) === 14.U(plru.nBits.W), s"get_next_state state=11 way=1: expected=14 actual=%d", get_next_states(11)(1)) assert(get_next_states(11)(2) === 11.U(plru.nBits.W), s"get_next_state state=11 way=2: expected=11 actual=%d", get_next_states(11)(2)) assert(get_next_states(11)(3) === 9.U(plru.nBits.W), s"get_next_state state=11 way=3: expected=09 actual=%d", get_next_states(11)(3)) assert(get_next_states(11)(4) === 3.U(plru.nBits.W), s"get_next_state state=11 way=4: expected=03 actual=%d", get_next_states(11)(4)) assert(get_next_states(12)(0) === 13.U(plru.nBits.W), s"get_next_state state=12 way=0: expected=13 actual=%d", get_next_states(12)(0)) assert(get_next_states(12)(1) === 12.U(plru.nBits.W), s"get_next_state state=12 way=1: expected=12 actual=%d", get_next_states(12)(1)) assert(get_next_states(12)(2) === 10.U(plru.nBits.W), s"get_next_state state=12 way=2: expected=10 actual=%d", get_next_states(12)(2)) assert(get_next_states(12)(3) === 8.U(plru.nBits.W), s"get_next_state state=12 way=3: expected=08 actual=%d", get_next_states(12)(3)) assert(get_next_states(12)(4) === 4.U(plru.nBits.W), s"get_next_state state=12 way=4: expected=04 actual=%d", get_next_states(12)(4)) assert(get_next_states(13)(0) === 13.U(plru.nBits.W), s"get_next_state state=13 way=0: expected=13 actual=%d", get_next_states(13)(0)) assert(get_next_states(13)(1) === 12.U(plru.nBits.W), s"get_next_state state=13 way=1: expected=12 actual=%d", get_next_states(13)(1)) assert(get_next_states(13)(2) === 11.U(plru.nBits.W), s"get_next_state state=13 way=2: expected=11 actual=%d", get_next_states(13)(2)) assert(get_next_states(13)(3) === 9.U(plru.nBits.W), s"get_next_state state=13 way=3: expected=09 actual=%d", get_next_states(13)(3)) assert(get_next_states(13)(4) === 5.U(plru.nBits.W), s"get_next_state state=13 way=4: expected=05 actual=%d", get_next_states(13)(4)) assert(get_next_states(14)(0) === 15.U(plru.nBits.W), s"get_next_state state=14 way=0: expected=15 actual=%d", get_next_states(14)(0)) assert(get_next_states(14)(1) === 14.U(plru.nBits.W), s"get_next_state state=14 way=1: expected=14 actual=%d", get_next_states(14)(1)) assert(get_next_states(14)(2) === 10.U(plru.nBits.W), s"get_next_state state=14 way=2: expected=10 actual=%d", get_next_states(14)(2)) assert(get_next_states(14)(3) === 8.U(plru.nBits.W), s"get_next_state state=14 way=3: expected=08 actual=%d", get_next_states(14)(3)) assert(get_next_states(14)(4) === 6.U(plru.nBits.W), s"get_next_state state=14 way=4: expected=06 actual=%d", get_next_states(14)(4)) assert(get_next_states(15)(0) === 15.U(plru.nBits.W), s"get_next_state state=15 way=0: expected=15 actual=%d", get_next_states(15)(0)) assert(get_next_states(15)(1) === 14.U(plru.nBits.W), s"get_next_state state=15 way=5: expected=14 actual=%d", get_next_states(15)(1)) assert(get_next_states(15)(2) === 11.U(plru.nBits.W), s"get_next_state state=15 way=2: expected=11 actual=%d", get_next_states(15)(2)) assert(get_next_states(15)(3) === 9.U(plru.nBits.W), s"get_next_state state=15 way=3: expected=09 actual=%d", get_next_states(15)(3)) assert(get_next_states(15)(4) === 7.U(plru.nBits.W), s"get_next_state state=15 way=4: expected=07 actual=%d", get_next_states(15)(4)) } case 6 => { assert(get_replace_ways( 0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=00: expected=0 actual=%d", get_replace_ways( 0)) assert(get_replace_ways( 1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=01: expected=1 actual=%d", get_replace_ways( 1)) assert(get_replace_ways( 2) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=02: expected=0 actual=%d", get_replace_ways( 2)) assert(get_replace_ways( 3) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=03: expected=1 actual=%d", get_replace_ways( 3)) assert(get_replace_ways( 4) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=04: expected=2 actual=%d", get_replace_ways( 4)) assert(get_replace_ways( 5) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=05: expected=2 actual=%d", get_replace_ways( 5)) assert(get_replace_ways( 6) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=06: expected=3 actual=%d", get_replace_ways( 6)) assert(get_replace_ways( 7) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=07: expected=3 actual=%d", get_replace_ways( 7)) assert(get_replace_ways( 8) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=08: expected=0 actual=%d", get_replace_ways( 8)) assert(get_replace_ways( 9) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=09: expected=1 actual=%d", get_replace_ways( 9)) assert(get_replace_ways(10) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=10: expected=0 actual=%d", get_replace_ways(10)) assert(get_replace_ways(11) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=11: expected=1 actual=%d", get_replace_ways(11)) assert(get_replace_ways(12) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=12: expected=2 actual=%d", get_replace_ways(12)) assert(get_replace_ways(13) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=13: expected=2 actual=%d", get_replace_ways(13)) assert(get_replace_ways(14) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=14: expected=3 actual=%d", get_replace_ways(14)) assert(get_replace_ways(15) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=15: expected=3 actual=%d", get_replace_ways(15)) assert(get_replace_ways(16) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=16: expected=4 actual=%d", get_replace_ways(16)) assert(get_replace_ways(17) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=17: expected=4 actual=%d", get_replace_ways(17)) assert(get_replace_ways(18) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=18: expected=4 actual=%d", get_replace_ways(18)) assert(get_replace_ways(19) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=19: expected=4 actual=%d", get_replace_ways(19)) assert(get_replace_ways(20) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=20: expected=4 actual=%d", get_replace_ways(20)) assert(get_replace_ways(21) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=21: expected=4 actual=%d", get_replace_ways(21)) assert(get_replace_ways(22) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=22: expected=4 actual=%d", get_replace_ways(22)) assert(get_replace_ways(23) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=23: expected=4 actual=%d", get_replace_ways(23)) assert(get_replace_ways(24) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=24: expected=5 actual=%d", get_replace_ways(24)) assert(get_replace_ways(25) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=25: expected=5 actual=%d", get_replace_ways(25)) assert(get_replace_ways(26) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=26: expected=5 actual=%d", get_replace_ways(26)) assert(get_replace_ways(27) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=27: expected=5 actual=%d", get_replace_ways(27)) assert(get_replace_ways(28) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=28: expected=5 actual=%d", get_replace_ways(28)) assert(get_replace_ways(29) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=29: expected=5 actual=%d", get_replace_ways(29)) assert(get_replace_ways(30) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=30: expected=5 actual=%d", get_replace_ways(30)) assert(get_replace_ways(31) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=31: expected=5 actual=%d", get_replace_ways(31)) } case _ => throw new IllegalArgumentException(s"no test pattern found for n_ways=$n_ways") } } File HellaCache.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3.{dontTouch, _} import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.bundlebridge._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.amba.AMBAProtField import freechips.rocketchip.diplomacy.{IdRange, TransferSizes, RegionType} import freechips.rocketchip.tile.{L1CacheParams, HasL1CacheParameters, HasCoreParameters, CoreBundle, HasNonDiplomaticTileParameters, BaseTile, HasTileParameters} import freechips.rocketchip.tilelink.{TLMasterParameters, TLClientNode, TLMasterPortParameters, TLEdgeOut, TLWidthWidget, TLFIFOFixer, ClientMetadata} import freechips.rocketchip.util.{Code, RandomReplacement, ParameterizedBundle} import freechips.rocketchip.util.{BooleanToAugmentedBoolean, IntToAugmentedInt} import scala.collection.mutable.ListBuffer case class DCacheParams( nSets: Int = 64, nWays: Int = 4, rowBits: Int = 64, subWordBits: Option[Int] = None, replacementPolicy: String = "random", nTLBSets: Int = 1, nTLBWays: Int = 32, nTLBBasePageSectors: Int = 4, nTLBSuperpages: Int = 4, tagECC: Option[String] = None, dataECC: Option[String] = None, dataECCBytes: Int = 1, nMSHRs: Int = 1, nSDQ: Int = 17, nRPQ: Int = 16, nMMIOs: Int = 1, blockBytes: Int = 64, separateUncachedResp: Boolean = false, acquireBeforeRelease: Boolean = false, pipelineWayMux: Boolean = false, clockGate: Boolean = false, scratch: Option[BigInt] = None) extends L1CacheParams { def tagCode: Code = Code.fromString(tagECC) def dataCode: Code = Code.fromString(dataECC) def dataScratchpadBytes: Int = scratch.map(_ => nSetsblockBytes).getOrElse(0) def replacement = new RandomReplacement(nWays) def silentDrop: Boolean = !acquireBeforeRelease require((!scratch.isDefined \|\| nWays == 1), "Scratchpad only allowed in direct-mapped cache.") require((!scratch.isDefined \|\| nMSHRs == 0), "Scratchpad only allowed in blocking cache.") if (scratch.isEmpty) require(isPow2(nSets), s"nSets($nSets) must be pow2") } trait HasL1HellaCacheParameters extends HasL1CacheParameters with HasCoreParameters { val cacheParams = tileParams.dcache.get val cfg = cacheParams def wordBits = coreDataBits def wordBytes = coreDataBytes def subWordBits = cacheParams.subWordBits.getOrElse(wordBits) def subWordBytes = subWordBits / 8 def wordOffBits = log2Up(wordBytes) def beatBytes = cacheBlockBytes / cacheDataBeats def beatWords = beatBytes / wordBytes def beatOffBits = log2Up(beatBytes) def idxMSB = untagBits-1 def idxLSB = blockOffBits def offsetmsb = idxLSB-1 def offsetlsb = wordOffBits def rowWords = rowBits/wordBits def doNarrowRead = coreDataBits * nWays % rowBits == 0 def eccBytes = cacheParams.dataECCBytes val eccBits = cacheParams.dataECCBytes * 8 val encBits = cacheParams.dataCode.width(eccBits) val encWordBits = encBits * (wordBits / eccBits) def encDataBits = cacheParams.dataCode.width(coreDataBits) // NBDCache only def encRowBits = encDataBitsrowWords def lrscCycles = coreParams.lrscCycles // ISA requires 16-insn LRSC sequences to succeed def lrscBackoff = 3 // disallow LRSC reacquisition briefly def blockProbeAfterGrantCycles = 8 // give the processor some time to issue a request after a grant def nIOMSHRs = cacheParams.nMMIOs def maxUncachedInFlight = cacheParams.nMMIOs def dataScratchpadSize = cacheParams.dataScratchpadBytes require(rowBits >= coreDataBits, s"rowBits($rowBits) < coreDataBits($coreDataBits)") if (!usingDataScratchpad) require(rowBits == cacheDataBits, s"rowBits($rowBits) != cacheDataBits($cacheDataBits)") // would need offset addr for puts if data width < xlen require(xLen <= cacheDataBits, s"xLen($xLen) > cacheDataBits($cacheDataBits)") } abstract class L1HellaCacheModule(implicit val p: Parameters) extends Module with HasL1HellaCacheParameters abstract class L1HellaCacheBundle(implicit val p: Parameters) extends ParameterizedBundle()(p) with HasL1HellaCacheParameters /* Bundle definitions for HellaCache interfaces / trait HasCoreMemOp extends HasL1HellaCacheParameters { val addr = UInt(coreMaxAddrBits.W) val idx = (usingVM && untagBits > pgIdxBits).option(UInt(coreMaxAddrBits.W)) val tag = UInt((coreParams.dcacheReqTagBits + log2Ceil(dcacheArbPorts)).W) val cmd = UInt(M_SZ.W) val size = UInt(log2Ceil(coreDataBytes.log2 + 1).W) val signed = Bool() val dprv = UInt(PRV.SZ.W) val dv = Bool() } trait HasCoreData extends HasCoreParameters { val data = UInt(coreDataBits.W) val mask = UInt(coreDataBytes.W) } class HellaCacheReqInternal(implicit p: Parameters) extends CoreBundle()(p) with HasCoreMemOp { val phys = Bool() val no_resp = Bool() // The dcache may omit generating a response for this request val no_alloc = Bool() val no_xcpt = Bool() } class HellaCacheReq(implicit p: Parameters) extends HellaCacheReqInternal()(p) with HasCoreData class HellaCacheResp(implicit p: Parameters) extends CoreBundle()(p) with HasCoreMemOp with HasCoreData { val replay = Bool() val has_data = Bool() val data_word_bypass = UInt(coreDataBits.W) val data_raw = UInt(coreDataBits.W) val store_data = UInt(coreDataBits.W) } class AlignmentExceptions extends Bundle { val ld = Bool() val st = Bool() } class HellaCacheExceptions extends Bundle { val ma = new AlignmentExceptions val pf = new AlignmentExceptions val gf = new AlignmentExceptions val ae = new AlignmentExceptions } class HellaCacheWriteData(implicit p: Parameters) extends CoreBundle()(p) with HasCoreData class HellaCachePerfEvents extends Bundle { val acquire = Bool() val release = Bool() val grant = Bool() val tlbMiss = Bool() val blocked = Bool() val canAcceptStoreThenLoad = Bool() val canAcceptStoreThenRMW = Bool() val canAcceptLoadThenLoad = Bool() val storeBufferEmptyAfterLoad = Bool() val storeBufferEmptyAfterStore = Bool() } // interface between D$ and processor/DTLB class HellaCacheIO(implicit p: Parameters) extends CoreBundle()(p) { val req = Decoupled(new HellaCacheReq) val s1_kill = Output(Bool()) // kill previous cycle's req val s1_data = Output(new HellaCacheWriteData()) // data for previous cycle's req val s2_nack = Input(Bool()) // req from two cycles ago is rejected val s2_nack_cause_raw = Input(Bool()) // reason for nack is store-load RAW hazard (performance hint) val s2_kill = Output(Bool()) // kill req from two cycles ago val s2_uncached = Input(Bool()) // advisory signal that the access is MMIO val s2_paddr = Input(UInt(paddrBits.W)) // translated address val resp = Flipped(Valid(new HellaCacheResp)) val replay_next = Input(Bool()) val s2_xcpt = Input(new HellaCacheExceptions) val s2_gpa = Input(UInt(vaddrBitsExtended.W)) val s2_gpa_is_pte = Input(Bool()) val uncached_resp = tileParams.dcache.get.separateUncachedResp.option(Flipped(Decoupled(new HellaCacheResp))) val ordered = Input(Bool()) val store_pending = Input(Bool()) // there is a store in a store buffer somewhere val perf = Input(new HellaCachePerfEvents()) val keep_clock_enabled = Output(Bool()) // should D$ avoid clock-gating itself? val clock_enabled = Input(Bool()) // is D$ currently being clocked? } /* Base classes for Diplomatic TL2 HellaCaches / abstract class HellaCache(tileId: Int)(implicit p: Parameters) extends LazyModule with HasNonDiplomaticTileParameters { protected val cfg = tileParams.dcache.get protected def cacheClientParameters = cfg.scratch.map(x => Seq()).getOrElse(Seq(TLMasterParameters.v1( name = s"Core ${tileId} DCache", sourceId = IdRange(0, 1 max cfg.nMSHRs), supportsProbe = TransferSizes(cfg.blockBytes, cfg.blockBytes)))) protected def mmioClientParameters = Seq(TLMasterParameters.v1( name = s"Core ${tileId} DCache MMIO", sourceId = IdRange(firstMMIO, firstMMIO + cfg.nMMIOs), requestFifo = true)) def firstMMIO = (cacheClientParameters.map(_.sourceId.end) :+ 0).max val node = TLClientNode(Seq(TLMasterPortParameters.v1( clients = cacheClientParameters ++ mmioClientParameters, minLatency = 1, requestFields = tileParams.core.useVM.option(Seq()).getOrElse(Seq(AMBAProtField()))))) val hartIdSinkNodeOpt = cfg.scratch.map(_ => BundleBridgeSink[UInt]()) val mmioAddressPrefixSinkNodeOpt = cfg.scratch.map(_ => BundleBridgeSink[UInt]()) val module: HellaCacheModule def flushOnFenceI = cfg.scratch.isEmpty && !node.edges.out(0).manager.managers.forall(m => !m.supportsAcquireB \|\| !m.executable \|\| m.regionType >= RegionType.TRACKED \|\| m.regionType <= RegionType.IDEMPOTENT) def canSupportCFlushLine = !usingVM \|\| cfg.blockBytes cfg.nSets <= (1 << pgIdxBits) require(!tileParams.core.haveCFlush \|\| cfg.scratch.isEmpty, "CFLUSH_D_L1 instruction requires a D$") } class HellaCacheBundle(implicit p: Parameters) extends CoreBundle()(p) { val cpu = Flipped(new HellaCacheIO) val ptw = new TLBPTWIO() val errors = new DCacheErrors val tlb_port = new DCacheTLBPort } class HellaCacheModule(outer: HellaCache) extends LazyModuleImp(outer) with HasL1HellaCacheParameters { implicit val edge: TLEdgeOut = outer.node.edges.out(0) val (tl_out, _) = outer.node.out(0) val io = IO(new HellaCacheBundle) val io_hartid = outer.hartIdSinkNodeOpt.map(_.bundle) val io_mmio_address_prefix = outer.mmioAddressPrefixSinkNodeOpt.map(_.bundle) dontTouch(io.cpu.resp) // Users like to monitor these fields even if the core ignores some signals dontTouch(io.cpu.s1_data) require(rowBits == edge.bundle.dataBits) private val fifoManagers = edge.manager.managers.filter(TLFIFOFixer.allVolatile) fifoManagers.foreach { m => require (m.fifoId == fifoManagers.head.fifoId, s"IOMSHRs must be FIFO for all regions with effects, but HellaCache sees\n"+ s"${m.nodePath.map(_.name)}\nversus\n${fifoManagers.head.nodePath.map(_.name)}") } } /** Support overriding which HellaCache is instantiated / case object BuildHellaCache extends Field[BaseTile => Parameters => HellaCache](HellaCacheFactory.apply) object HellaCacheFactory { def apply(tile: BaseTile)(p: Parameters): HellaCache = { if (tile.tileParams.dcache.get.nMSHRs == 0) new DCache(tile.tileId, tile.crossing)(p) else new NonBlockingDCache(tile.tileId)(p) } } /* Mix-ins for constructing tiles that have a HellaCache / trait HasHellaCache { this: BaseTile => val module: HasHellaCacheModule implicit val p: Parameters var nDCachePorts = 0 lazy val dcache: HellaCache = LazyModule(p(BuildHellaCache)(this)(p)) tlMasterXbar.node := TLWidthWidget(tileParams.dcache.get.rowBits/8) := dcache.node dcache.hartIdSinkNodeOpt.map { _ := hartIdNexusNode } dcache.mmioAddressPrefixSinkNodeOpt.map { _ := mmioAddressPrefixNexusNode } InModuleBody { dcache.module.io.tlb_port := DontCare } } trait HasHellaCacheModule { val outer: HasHellaCache with HasTileParameters implicit val p: Parameters val dcachePorts = ListBuffer[HellaCacheIO]() val dcacheArb = Module(new HellaCacheArbiter(outer.nDCachePorts)(outer.p)) outer.dcache.module.io.cpu <> dcacheArb.io.mem } /* Metadata array used for all HellaCaches / class L1Metadata(implicit p: Parameters) extends L1HellaCacheBundle()(p) { val coh = new ClientMetadata val tag = UInt(tagBits.W) } object L1Metadata { def apply(tag: Bits, coh: ClientMetadata)(implicit p: Parameters) = { val meta = Wire(new L1Metadata) meta.tag := tag meta.coh := coh meta } } class L1MetaReadReq(implicit p: Parameters) extends L1HellaCacheBundle()(p) { val idx = UInt(idxBits.W) val way_en = UInt(nWays.W) val tag = UInt(tagBits.W) } class L1MetaWriteReq(implicit p: Parameters) extends L1MetaReadReq()(p) { val data = new L1Metadata } class L1MetadataArray[T <: L1Metadata](onReset: () => T)(implicit p: Parameters) extends L1HellaCacheModule()(p) { val rstVal = onReset() val io = IO(new Bundle { val read = Flipped(Decoupled(new L1MetaReadReq)) val write = Flipped(Decoupled(new L1MetaWriteReq)) val resp = Output(Vec(nWays, rstVal.cloneType)) }) val rst_cnt = RegInit(0.U(log2Up(nSets+1).W)) val rst = rst_cnt < nSets.U val waddr = Mux(rst, rst_cnt, io.write.bits.idx) val wdata = Mux(rst, rstVal, io.write.bits.data).asUInt val wmask = Mux(rst \|\| (nWays == 1).B, (-1).S, io.write.bits.way_en.asSInt).asBools val rmask = Mux(rst \|\| (nWays == 1).B, (-1).S, io.read.bits.way_en.asSInt).asBools when (rst) { rst_cnt := rst_cnt+1.U } val metabits = rstVal.getWidth val tag_array = SyncReadMem(nSets, Vec(nWays, UInt(metabits.W))) val wen = rst \|\| io.write.valid when (wen) { tag_array.write(waddr, VecInit.fill(nWays)(wdata), wmask) } io.resp := tag_array.read(io.read.bits.idx, io.read.fire).map(_.asTypeOf(chiselTypeOf(rstVal))) io.read.ready := !wen // so really this could be a 6T RAM io.write.ready := !rst } File ECC.scala: // See LICENSE.Berkeley for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR abstract class Decoding { def uncorrected: UInt def corrected: UInt def correctable: Bool def uncorrectable: Bool // If true, correctable should be ignored def error = correctable \|\| uncorrectable } abstract class Code { def canDetect: Boolean def canCorrect: Boolean def width(w0: Int): Int /* Takes the unencoded width and returns a list of indices indicating which * bits of the encoded value will be used for ecc / def eccIndices(width: Int): Seq[Int] /* Encode x to a codeword suitable for decode. * If poison is true, the decoded value will report uncorrectable * error despite uncorrected == corrected == x. / def encode(x: UInt, poison: Bool = false.B): UInt def decode(x: UInt): Decoding /* Copy the bits in x to the right bit positions in an encoded word, * so that x === decode(swizzle(x)).uncorrected; but don't generate * the other code bits, so decode(swizzle(x)).error might be true. * For codes for which this operation is not trivial, throw an * UnsupportedOperationException. / def swizzle(x: UInt): UInt } class IdentityCode extends Code { def canDetect = false def canCorrect = false def width(w0: Int) = w0 def eccIndices(width: Int) = Seq.empty[Int] def encode(x: UInt, poison: Bool = false.B) = { require (poison.isLit && poison.litValue == 0, "IdentityCode can not be poisoned") x } def swizzle(x: UInt) = x def decode(y: UInt) = new Decoding { def uncorrected = y def corrected = y def correctable = false.B def uncorrectable = false.B } } class ParityCode extends Code { def canDetect = true def canCorrect = false def width(w0: Int) = w0+1 def eccIndices(w0: Int) = Seq(w0) def encode(x: UInt, poison: Bool = false.B) = Cat(x.xorR ^ poison, x) def swizzle(x: UInt) = Cat(false.B, x) def decode(y: UInt) = new Decoding { val uncorrected = y(y.getWidth-2,0) val corrected = uncorrected val correctable = false.B val uncorrectable = y.xorR } } class SECCode extends Code { def canDetect = true def canCorrect = true // SEC codes may or may not be poisonous depending on the length // If the code is perfect, every non-codeword is correctable def poisonous(n: Int) = !isPow2(n+1) def width(k: Int) = { val m = log2Floor(k) + 1 k + m + (if((1 << m) < m+k+1) 1 else 0) } def eccIndices(w0: Int) = { (0 until width(w0)).collect { case i if i >= w0 => i } } def swizzle(x: UInt) = { val k = x.getWidth val n = width(k) Cat(0.U((n-k).W), x) } // An (n=16, k=11) Hamming code is naturally encoded as: // PPxPxxxPxxxxxxxP where P are parity bits and x are data // Indexes typically start at 1, because then the P are on powers of two // In systematic coding, you put all the data in the front: // xxxxxxxxxxxPPPPP // Indexes typically start at 0, because Computer Science // For sanity when reading SRAMs, you want systematic form. private def impl(n: Int, k: Int) = { require (n >= 3 && k >= 1 && !isPow2(n)) val hamm2sys = IndexedSeq.tabulate(n+1) { i => if (i == 0) { n / undefined / } else if (isPow2(i)) { k + log2Ceil(i) } else { i - 1 - log2Ceil(i) } } val sys2hamm = hamm2sys.zipWithIndex.sortBy(_._1).map(_._2).toIndexedSeq def syndrome(j: Int) = { val bit = 1 << j ("b" + Seq.tabulate(n) { i => if ((sys2hamm(i) & bit) != 0) "1" else "0" }.reverse.mkString).U } (hamm2sys, sys2hamm, syndrome _) } def encode(x: UInt, poison: Bool = false.B) = { val k = x.getWidth val n = width(k) val (_, _, syndrome) = impl(n, k) require ((poison.isLit && poison.litValue == 0) \|\| poisonous(n), s"SEC code of length ${n} cannot be poisoned") / By setting the entire syndrome on poison, the corrected bit falls off the end of the code / val syndromeUInt = VecInit.tabulate(n-k) { j => (syndrome(j)(k-1, 0) & x).xorR ^ poison }.asUInt Cat(syndromeUInt, x) } def decode(y: UInt) = new Decoding { val n = y.getWidth val k = n - log2Ceil(n) val (_, sys2hamm, syndrome) = impl(n, k) val syndromeUInt = VecInit.tabulate(n-k) { j => (syndrome(j) & y).xorR }.asUInt val hammBadBitOH = UIntToOH(syndromeUInt, n+1) val sysBadBitOH = VecInit.tabulate(k) { i => hammBadBitOH(sys2hamm(i)) }.asUInt val uncorrected = y(k-1, 0) val corrected = uncorrected ^ sysBadBitOH val correctable = syndromeUInt.orR val uncorrectable = if (poisonous(n)) { syndromeUInt > n.U } else { false.B } } } class SECDEDCode extends Code { def canDetect = true def canCorrect = true private val sec = new SECCode private val par = new ParityCode def width(k: Int) = sec.width(k)+1 def eccIndices(w0: Int) = { (0 until width(w0)).collect { case i if i >= w0 => i } } def encode(x: UInt, poison: Bool = false.B) = { // toggling two bits ensures the error is uncorrectable // to ensure corrected == uncorrected, we pick one redundant // bit from SEC (the highest); correcting it does not affect // corrected == uncorrected. the second toggled bit is the // parity bit, which also does not appear in the decoding val toggle_lo = Cat(poison.asUInt, poison.asUInt) val toggle_hi = toggle_lo << (sec.width(x.getWidth)-1) par.encode(sec.encode(x)) ^ toggle_hi } def swizzle(x: UInt) = par.swizzle(sec.swizzle(x)) def decode(x: UInt) = new Decoding { val secdec = sec.decode(x(x.getWidth-2,0)) val pardec = par.decode(x) val uncorrected = secdec.uncorrected val corrected = secdec.corrected val correctable = pardec.uncorrectable val uncorrectable = !pardec.uncorrectable && secdec.correctable } } object ErrGen { // generate a 1-bit error with approximate probability 2^-f def apply(width: Int, f: Int): UInt = { require(width > 0 && f >= 0 && log2Up(width) + f <= 16) UIntToOH(LFSR(16)(log2Up(width)+f-1,0))(width-1,0) } def apply(x: UInt, f: Int): UInt = x ^ apply(x.getWidth, f) } trait CanHaveErrors extends Bundle { val correctable: Option[ValidIO[UInt]] val uncorrectable: Option[ValidIO[UInt]] } case class ECCParams( bytes: Int = 1, code: Code = new IdentityCode, notifyErrors: Boolean = false, ) object Code { def fromString(s: Option[String]): Code = fromString(s.getOrElse("none")) def fromString(s: String): Code = s.toLowerCase match { case "none" => new IdentityCode case "identity" => new IdentityCode case "parity" => new ParityCode case "sec" => new SECCode case "secded" => new SECDEDCode case _ => throw new IllegalArgumentException("Unknown ECC type") } } // Synthesizable unit tests import freechips.rocketchip.unittest._ class ECCTest(k: Int, timeout: Int = 500000) extends UnitTest(timeout) { val code = new SECDEDCode val n = code.width(k) // Brute force the decode space val test = RegInit(0.U((n+1).W)) val last = test(n) test := test + !last io.finished := RegNext(last, false.B) // Confirm the decoding matches the encoding val decoded = code.decode(test(n-1, 0)) val recoded = code.encode(decoded.corrected) val distance = PopCount(recoded ^ test) // Count the cases val correct = RegInit(0.U(n.W)) val correctable = RegInit(0.U(n.W)) val uncorrectable = RegInit(0.U(n.W)) when (!last) { when (decoded.uncorrectable) { assert (distance >= 2.U) // uncorrectable uncorrectable := uncorrectable + 1.U } .elsewhen (decoded.correctable) { assert (distance(0)) // correctable => odd bit errors correctable := correctable + 1.U } .otherwise { assert (distance === 0.U) // correct assert (decoded.uncorrected === decoded.corrected) correct := correct + 1.U } } // Expected number of each case val nCodes = BigInt(1) << n val nCorrect = BigInt(1) << k val nCorrectable = nCodes / 2 val nUncorrectable = nCodes - nCorrectable - nCorrect when (last) { assert (correct === nCorrect.U) assert (correctable === nCorrectable.U) assert (uncorrectable === nUncorrectable.U) } } File Consts.scala: // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket.constants import chisel3._ import chisel3.util._ import freechips.rocketchip.util._ trait ScalarOpConstants { val SZ_BR = 3 def BR_X = BitPat("b???") def BR_EQ = 0.U(3.W) def BR_NE = 1.U(3.W) def BR_J = 2.U(3.W) def BR_N = 3.U(3.W) def BR_LT = 4.U(3.W) def BR_GE = 5.U(3.W) def BR_LTU = 6.U(3.W) def BR_GEU = 7.U(3.W) def A1_X = BitPat("b??") def A1_ZERO = 0.U(2.W) def A1_RS1 = 1.U(2.W) def A1_PC = 2.U(2.W) def A1_RS1SHL = 3.U(2.W) def IMM_X = BitPat("b???") def IMM_S = 0.U(3.W) def IMM_SB = 1.U(3.W) def IMM_U = 2.U(3.W) def IMM_UJ = 3.U(3.W) def IMM_I = 4.U(3.W) def IMM_Z = 5.U(3.W) def A2_X = BitPat("b???") def A2_ZERO = 0.U(3.W) def A2_SIZE = 1.U(3.W) def A2_RS2 = 2.U(3.W) def A2_IMM = 3.U(3.W) def A2_RS2OH = 4.U(3.W) def A2_IMMOH = 5.U(3.W) def X = BitPat("b?") def N = BitPat("b0") def Y = BitPat("b1") val SZ_DW = 1 def DW_X = X def DW_32 = false.B def DW_64 = true.B def DW_XPR = DW_64 } trait MemoryOpConstants { val NUM_XA_OPS = 9 val M_SZ = 5 def M_X = BitPat("b?????"); def M_XRD = "b00000".U; // int load def M_XWR = "b00001".U; // int store def M_PFR = "b00010".U; // prefetch with intent to read def M_PFW = "b00011".U; // prefetch with intent to write def M_XA_SWAP = "b00100".U def M_FLUSH_ALL = "b00101".U // flush all lines def M_XLR = "b00110".U def M_XSC = "b00111".U def M_XA_ADD = "b01000".U def M_XA_XOR = "b01001".U def M_XA_OR = "b01010".U def M_XA_AND = "b01011".U def M_XA_MIN = "b01100".U def M_XA_MAX = "b01101".U def M_XA_MINU = "b01110".U def M_XA_MAXU = "b01111".U def M_FLUSH = "b10000".U // write back dirty data and cede R/W permissions def M_PWR = "b10001".U // partial (masked) store def M_PRODUCE = "b10010".U // write back dirty data and cede W permissions def M_CLEAN = "b10011".U // write back dirty data and retain R/W permissions def M_SFENCE = "b10100".U // SFENCE.VMA def M_HFENCEV = "b10101".U // HFENCE.VVMA def M_HFENCEG = "b10110".U // HFENCE.GVMA def M_WOK = "b10111".U // check write permissions but don't perform a write def M_HLVX = "b10000".U // HLVX instruction def isAMOLogical(cmd: UInt) = cmd.isOneOf(M_XA_SWAP, M_XA_XOR, M_XA_OR, M_XA_AND) def isAMOArithmetic(cmd: UInt) = cmd.isOneOf(M_XA_ADD, M_XA_MIN, M_XA_MAX, M_XA_MINU, M_XA_MAXU) def isAMO(cmd: UInt) = isAMOLogical(cmd) \|\| isAMOArithmetic(cmd) def isPrefetch(cmd: UInt) = cmd === M_PFR \|\| cmd === M_PFW def isRead(cmd: UInt) = cmd.isOneOf(M_XRD, M_HLVX, M_XLR, M_XSC) \|\| isAMO(cmd) def isWrite(cmd: UInt) = cmd === M_XWR \|\| cmd === M_PWR \|\| cmd === M_XSC \|\| isAMO(cmd) def isWriteIntent(cmd: UInt) = isWrite(cmd) \|\| cmd === M_PFW \|\| cmd === M_XLR } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File TLB.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import freechips.rocketchip.devices.debug.DebugModuleKey import freechips.rocketchip.diplomacy.RegionType import freechips.rocketchip.subsystem.CacheBlockBytes import freechips.rocketchip.tile.{CoreModule, CoreBundle} import freechips.rocketchip.tilelink._ import freechips.rocketchip.util.{OptimizationBarrier, SetAssocLRU, PseudoLRU, PopCountAtLeast, property} import freechips.rocketchip.util.BooleanToAugmentedBoolean import freechips.rocketchip.util.IntToAugmentedInt import freechips.rocketchip.util.UIntToAugmentedUInt import freechips.rocketchip.util.UIntIsOneOf import freechips.rocketchip.util.SeqToAugmentedSeq import freechips.rocketchip.util.SeqBoolBitwiseOps case object ASIdBits extends Field[Int](0) case object VMIdBits extends Field[Int](0) /* =SFENCE= * rs1 rs2 * {{{ * 0 0 -> flush All * 0 1 -> flush by ASID * 1 1 -> flush by ADDR * 1 0 -> flush by ADDR and ASID * }}} * {{{ * If rs1=x0 and rs2=x0, the fence orders all reads and writes made to any level of the page tables, for all address spaces. * If rs1=x0 and rs2!=x0, the fence orders all reads and writes made to any level of the page tables, but only for the address space identified by integer register rs2. Accesses to global mappings (see Section 4.3.1) are not ordered. * If rs1!=x0 and rs2=x0, the fence orders only reads and writes made to the leaf page table entry corresponding to the virtual address in rs1, for all address spaces. * If rs1!=x0 and rs2!=x0, the fence orders only reads and writes made to the leaf page table entry corresponding to the virtual address in rs1, for the address space identified by integer register rs2. Accesses to global mappings are not ordered. * }}} / class SFenceReq(implicit p: Parameters) extends CoreBundle()(p) { val rs1 = Bool() val rs2 = Bool() val addr = UInt(vaddrBits.W) val asid = UInt((asIdBits max 1).W) // TODO zero-width val hv = Bool() val hg = Bool() } class TLBReq(lgMaxSize: Int)(implicit p: Parameters) extends CoreBundle()(p) { /* request address from CPU. / val vaddr = UInt(vaddrBitsExtended.W) /* don't lookup TLB, bypass vaddr as paddr / val passthrough = Bool() /* granularity / val size = UInt(log2Ceil(lgMaxSize + 1).W) /* memory command. / val cmd = Bits(M_SZ.W) val prv = UInt(PRV.SZ.W) /* virtualization mode / val v = Bool() } class TLBExceptions extends Bundle { val ld = Bool() val st = Bool() val inst = Bool() } class TLBResp(lgMaxSize: Int = 3)(implicit p: Parameters) extends CoreBundle()(p) { // lookup responses val miss = Bool() /* physical address / val paddr = UInt(paddrBits.W) val gpa = UInt(vaddrBitsExtended.W) val gpa_is_pte = Bool() /* page fault exception / val pf = new TLBExceptions /* guest page fault exception / val gf = new TLBExceptions /* access exception / val ae = new TLBExceptions /* misaligned access exception / val ma = new TLBExceptions /* if this address is cacheable / val cacheable = Bool() /* if caches must allocate this address / val must_alloc = Bool() /* if this address is prefetchable for caches/ val prefetchable = Bool() /* size/cmd of request that generated this response/ val size = UInt(log2Ceil(lgMaxSize + 1).W) val cmd = UInt(M_SZ.W) } class TLBEntryData(implicit p: Parameters) extends CoreBundle()(p) { val ppn = UInt(ppnBits.W) /* pte.u user / val u = Bool() /* pte.g global / val g = Bool() /* access exception. * D$ -> PTW -> TLB AE * Alignment failed. / val ae_ptw = Bool() val ae_final = Bool() val ae_stage2 = Bool() /* page fault / val pf = Bool() /* guest page fault / val gf = Bool() /* supervisor write / val sw = Bool() /* supervisor execute / val sx = Bool() /* supervisor read / val sr = Bool() /* hypervisor write / val hw = Bool() /* hypervisor excute / val hx = Bool() /* hypervisor read / val hr = Bool() /* prot_w / val pw = Bool() /* prot_x / val px = Bool() /* prot_r / val pr = Bool() /* PutPartial / val ppp = Bool() /* AMO logical / val pal = Bool() /* AMO arithmetic / val paa = Bool() /* get/put effects / val eff = Bool() /* cacheable / val c = Bool() /* fragmented_superpage support / val fragmented_superpage = Bool() } /* basic cell for TLB data / class TLBEntry(val nSectors: Int, val superpage: Boolean, val superpageOnly: Boolean)(implicit p: Parameters) extends CoreBundle()(p) { require(nSectors == 1 \|\| !superpage) require(!superpageOnly \|\| superpage) val level = UInt(log2Ceil(pgLevels).W) /* use vpn as tag / val tag_vpn = UInt(vpnBits.W) /* tag in vitualization mode / val tag_v = Bool() /* entry data / val data = Vec(nSectors, UInt(new TLBEntryData().getWidth.W)) /* valid bit / val valid = Vec(nSectors, Bool()) /* returns all entry data in this entry / def entry_data = data.map(_.asTypeOf(new TLBEntryData)) /* returns the index of sector / private def sectorIdx(vpn: UInt) = vpn.extract(nSectors.log2-1, 0) /* returns the entry data matched with this vpn/ def getData(vpn: UInt) = OptimizationBarrier(data(sectorIdx(vpn)).asTypeOf(new TLBEntryData)) /* returns whether a sector hits / def sectorHit(vpn: UInt, virtual: Bool) = valid.orR && sectorTagMatch(vpn, virtual) /* returns whether tag matches vpn / def sectorTagMatch(vpn: UInt, virtual: Bool) = (((tag_vpn ^ vpn) >> nSectors.log2) === 0.U) && (tag_v === virtual) /* returns hit signal / def hit(vpn: UInt, virtual: Bool): Bool = { if (superpage && usingVM) { var tagMatch = valid.head && (tag_v === virtual) for (j <- 0 until pgLevels) { val base = (pgLevels - 1 - j) pgLevelBits val n = pgLevelBits + (if (j == 0) hypervisorExtraAddrBits else 0) val ignore = level < j.U \|\| (superpageOnly && j == pgLevels - 1).B tagMatch = tagMatch && (ignore \|\| (tag_vpn ^ vpn)(base + n - 1, base) === 0.U) } tagMatch } else { val idx = sectorIdx(vpn) valid(idx) && sectorTagMatch(vpn, virtual) } } /** returns the ppn of the input TLBEntryData / def ppn(vpn: UInt, data: TLBEntryData) = { val supervisorVPNBits = pgLevels pgLevelBits if (superpage && usingVM) { var res = data.ppn >> pgLevelBits(pgLevels - 1) for (j <- 1 until pgLevels) { val ignore = level < j.U \|\| (superpageOnly && j == pgLevels - 1).B res = Cat(res, (Mux(ignore, vpn, 0.U) \| data.ppn)(supervisorVPNBits - jpgLevelBits - 1, supervisorVPNBits - (j + 1)pgLevelBits)) } res } else { data.ppn } } /* does the refill * * find the target entry with vpn tag * and replace the target entry with the input entry data / def insert(vpn: UInt, virtual: Bool, level: UInt, entry: TLBEntryData): Unit = { this.tag_vpn := vpn this.tag_v := virtual this.level := level.extract(log2Ceil(pgLevels - superpageOnly.toInt)-1, 0) val idx = sectorIdx(vpn) valid(idx) := true.B data(idx) := entry.asUInt } def invalidate(): Unit = { valid.foreach(_ := false.B) } def invalidate(virtual: Bool): Unit = { for ((v, e) <- valid zip entry_data) when (tag_v === virtual) { v := false.B } } def invalidateVPN(vpn: UInt, virtual: Bool): Unit = { if (superpage) { when (hit(vpn, virtual)) { invalidate() } } else { when (sectorTagMatch(vpn, virtual)) { for (((v, e), i) <- (valid zip entry_data).zipWithIndex) when (tag_v === virtual && i.U === sectorIdx(vpn)) { v := false.B } } } // For fragmented superpage mappings, we assume the worst (largest) // case, and zap entries whose most-significant VPNs match when (((tag_vpn ^ vpn) >> (pgLevelBits (pgLevels - 1))) === 0.U) { for ((v, e) <- valid zip entry_data) when (tag_v === virtual && e.fragmented_superpage) { v := false.B } } } def invalidateNonGlobal(virtual: Bool): Unit = { for ((v, e) <- valid zip entry_data) when (tag_v === virtual && !e.g) { v := false.B } } } /** TLB config * * @param nSets the number of sets of PTE, follow [[ICacheParams.nSets]] * @param nWays the total number of wayss of PTE, follow [[ICacheParams.nWays]] * @param nSectors the number of ways in a single PTE TLBEntry * @param nSuperpageEntries the number of SuperpageEntries / case class TLBConfig( nSets: Int, nWays: Int, nSectors: Int = 4, nSuperpageEntries: Int = 4) /* =Overview= * [[TLB]] is a TLB template which contains PMA logic and PMP checker. * * TLB caches PTE and accelerates the address translation process. * When tlb miss happens, ask PTW(L2TLB) for Page Table Walk. * Perform PMP and PMA check during the translation and throw exception if there were any. * * ==Cache Structure== * - Sectored Entry (PTE) * - set-associative or direct-mapped * - nsets = [[TLBConfig.nSets]] * - nways = [[TLBConfig.nWays]] / [[TLBConfig.nSectors]] * - PTEEntry( sectors = [[TLBConfig.nSectors]] ) * - LRU(if set-associative) * * - Superpage Entry(superpage PTE) * - fully associative * - nsets = [[TLBConfig.nSuperpageEntries]] * - PTEEntry(sectors = 1) * - PseudoLRU * * - Special Entry(PTE across PMP) * - nsets = 1 * - PTEEntry(sectors = 1) * * ==Address structure== * {{{ * \|vaddr \| * \|ppn/vpn \| pgIndex \| * \| \| \| * \| \|nSets \|nSector \| \|}}} * * ==State Machine== * {{{ * s_ready: ready to accept request from CPU. * s_request: when L1TLB(this) miss, send request to PTW(L2TLB), . * s_wait: wait for PTW to refill L1TLB. * s_wait_invalidate: L1TLB is waiting for respond from PTW, but L1TLB will invalidate respond from PTW.}}} * * ==PMP== * pmp check * - special_entry: always check * - other entry: check on refill * * ==Note== * PMA consume diplomacy parameter generate physical memory address checking logic * * Boom use Rocket ITLB, and its own DTLB. * * Accelerators:{{{ * sha3: DTLB * gemmini: DTLB * hwacha: DTLB2+ITLB}}} @param instruction true for ITLB, false for DTLB * @param lgMaxSize @todo seems granularity * @param cfg [[TLBConfig]] * @param edge collect SoC metadata. / class TLB(instruction: Boolean, lgMaxSize: Int, cfg: TLBConfig)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(p) { override def desiredName = if (instruction) "ITLB" else "DTLB" val io = IO(new Bundle { /* request from Core / val req = Flipped(Decoupled(new TLBReq(lgMaxSize))) /* response to Core / val resp = Output(new TLBResp(lgMaxSize)) /* SFence Input / val sfence = Flipped(Valid(new SFenceReq)) /* IO to PTW / val ptw = new TLBPTWIO /* suppress a TLB refill, one cycle after a miss / val kill = Input(Bool()) }) io.ptw.customCSRs := DontCare val pageGranularityPMPs = pmpGranularity >= (1 << pgIdxBits) val vpn = io.req.bits.vaddr(vaddrBits-1, pgIdxBits) /* index for sectored_Entry / val memIdx = vpn.extract(cfg.nSectors.log2 + cfg.nSets.log2 - 1, cfg.nSectors.log2) /* TLB Entry / val sectored_entries = Reg(Vec(cfg.nSets, Vec(cfg.nWays / cfg.nSectors, new TLBEntry(cfg.nSectors, false, false)))) /* Superpage Entry / val superpage_entries = Reg(Vec(cfg.nSuperpageEntries, new TLBEntry(1, true, true))) /* Special Entry * * If PMP granularity is less than page size, thus need additional "special" entry manage PMP. / val special_entry = (!pageGranularityPMPs).option(Reg(new TLBEntry(1, true, false))) def ordinary_entries = sectored_entries(memIdx) ++ superpage_entries def all_entries = ordinary_entries ++ special_entry def all_real_entries = sectored_entries.flatten ++ superpage_entries ++ special_entry val s_ready :: s_request :: s_wait :: s_wait_invalidate :: Nil = Enum(4) val state = RegInit(s_ready) // use vpn as refill_tag val r_refill_tag = Reg(UInt(vpnBits.W)) val r_superpage_repl_addr = Reg(UInt(log2Ceil(superpage_entries.size).W)) val r_sectored_repl_addr = Reg(UInt(log2Ceil(sectored_entries.head.size).W)) val r_sectored_hit = Reg(Valid(UInt(log2Ceil(sectored_entries.head.size).W))) val r_superpage_hit = Reg(Valid(UInt(log2Ceil(superpage_entries.size).W))) val r_vstage1_en = Reg(Bool()) val r_stage2_en = Reg(Bool()) val r_need_gpa = Reg(Bool()) val r_gpa_valid = Reg(Bool()) val r_gpa = Reg(UInt(vaddrBits.W)) val r_gpa_vpn = Reg(UInt(vpnBits.W)) val r_gpa_is_pte = Reg(Bool()) /* privilege mode / val priv = io.req.bits.prv val priv_v = usingHypervisor.B && io.req.bits.v val priv_s = priv(0) // user mode and supervisor mode val priv_uses_vm = priv <= PRV.S.U val satp = Mux(priv_v, io.ptw.vsatp, io.ptw.ptbr) val stage1_en = usingVM.B && satp.mode(satp.mode.getWidth-1) /* VS-stage translation enable / val vstage1_en = usingHypervisor.B && priv_v && io.ptw.vsatp.mode(io.ptw.vsatp.mode.getWidth-1) /* G-stage translation enable / val stage2_en = usingHypervisor.B && priv_v && io.ptw.hgatp.mode(io.ptw.hgatp.mode.getWidth-1) /* Enable Virtual Memory when: * 1. statically configured * 1. satp highest bits enabled * i. RV32: * - 0 -> Bare * - 1 -> SV32 * i. RV64: * - 0000 -> Bare * - 1000 -> SV39 * - 1001 -> SV48 * - 1010 -> SV57 * - 1011 -> SV64 * 1. In virtualization mode, vsatp highest bits enabled * 1. priv mode in U and S. * 1. in H & M mode, disable VM. * 1. no passthrough(micro-arch defined.) * * @see RV-priv spec 4.1.11 Supervisor Address Translation and Protection (satp) Register * @see RV-priv spec 8.2.18 Virtual Supervisor Address Translation and Protection Register (vsatp) / val vm_enabled = (stage1_en \|\| stage2_en) && priv_uses_vm && !io.req.bits.passthrough // flush guest entries on vsatp.MODE Bare <-> SvXX transitions val v_entries_use_stage1 = RegInit(false.B) val vsatp_mode_mismatch = priv_v && (vstage1_en =/= v_entries_use_stage1) && !io.req.bits.passthrough // share a single physical memory attribute checker (unshare if critical path) val refill_ppn = io.ptw.resp.bits.pte.ppn(ppnBits-1, 0) /* refill signal / val do_refill = usingVM.B && io.ptw.resp.valid /* sfence invalidate refill / val invalidate_refill = state.isOneOf(s_request / don't care /, s_wait_invalidate) \|\| io.sfence.valid // PMP val mpu_ppn = Mux(do_refill, refill_ppn, Mux(vm_enabled && special_entry.nonEmpty.B, special_entry.map(e => e.ppn(vpn, e.getData(vpn))).getOrElse(0.U), io.req.bits.vaddr >> pgIdxBits)) val mpu_physaddr = Cat(mpu_ppn, io.req.bits.vaddr(pgIdxBits-1, 0)) val mpu_priv = Mux[UInt](usingVM.B && (do_refill \|\| io.req.bits.passthrough / PTW /), PRV.S.U, Cat(io.ptw.status.debug, priv)) val pmp = Module(new PMPChecker(lgMaxSize)) pmp.io.addr := mpu_physaddr pmp.io.size := io.req.bits.size pmp.io.pmp := (io.ptw.pmp: Seq[PMP]) pmp.io.prv := mpu_priv val pma = Module(new PMAChecker(edge.manager)(p)) pma.io.paddr := mpu_physaddr // todo: using DataScratchpad doesn't support cacheable. val cacheable = pma.io.resp.cacheable && (instruction \|\| !usingDataScratchpad).B val homogeneous = TLBPageLookup(edge.manager.managers, xLen, p(CacheBlockBytes), BigInt(1) << pgIdxBits, 1 << lgMaxSize)(mpu_physaddr).homogeneous // In M mode, if access DM address(debug module program buffer) val deny_access_to_debug = mpu_priv <= PRV.M.U && p(DebugModuleKey).map(dmp => dmp.address.contains(mpu_physaddr)).getOrElse(false.B) val prot_r = pma.io.resp.r && !deny_access_to_debug && pmp.io.r val prot_w = pma.io.resp.w && !deny_access_to_debug && pmp.io.w val prot_pp = pma.io.resp.pp val prot_al = pma.io.resp.al val prot_aa = pma.io.resp.aa val prot_x = pma.io.resp.x && !deny_access_to_debug && pmp.io.x val prot_eff = pma.io.resp.eff // hit check val sector_hits = sectored_entries(memIdx).map(_.sectorHit(vpn, priv_v)) val superpage_hits = superpage_entries.map(_.hit(vpn, priv_v)) val hitsVec = all_entries.map(vm_enabled && _.hit(vpn, priv_v)) val real_hits = hitsVec.asUInt val hits = Cat(!vm_enabled, real_hits) // use ptw response to refill // permission bit arrays when (do_refill) { val pte = io.ptw.resp.bits.pte val refill_v = r_vstage1_en \|\| r_stage2_en val newEntry = Wire(new TLBEntryData) newEntry.ppn := pte.ppn newEntry.c := cacheable newEntry.u := pte.u newEntry.g := pte.g && pte.v newEntry.ae_ptw := io.ptw.resp.bits.ae_ptw newEntry.ae_final := io.ptw.resp.bits.ae_final newEntry.ae_stage2 := io.ptw.resp.bits.ae_final && io.ptw.resp.bits.gpa_is_pte && r_stage2_en newEntry.pf := io.ptw.resp.bits.pf newEntry.gf := io.ptw.resp.bits.gf newEntry.hr := io.ptw.resp.bits.hr newEntry.hw := io.ptw.resp.bits.hw newEntry.hx := io.ptw.resp.bits.hx newEntry.sr := pte.sr() newEntry.sw := pte.sw() newEntry.sx := pte.sx() newEntry.pr := prot_r newEntry.pw := prot_w newEntry.px := prot_x newEntry.ppp := prot_pp newEntry.pal := prot_al newEntry.paa := prot_aa newEntry.eff := prot_eff newEntry.fragmented_superpage := io.ptw.resp.bits.fragmented_superpage // refill special_entry when (special_entry.nonEmpty.B && !io.ptw.resp.bits.homogeneous) { special_entry.foreach(_.insert(r_refill_tag, refill_v, io.ptw.resp.bits.level, newEntry)) }.elsewhen (io.ptw.resp.bits.level < (pgLevels-1).U) { val waddr = Mux(r_superpage_hit.valid && usingHypervisor.B, r_superpage_hit.bits, r_superpage_repl_addr) for ((e, i) <- superpage_entries.zipWithIndex) when (r_superpage_repl_addr === i.U) { e.insert(r_refill_tag, refill_v, io.ptw.resp.bits.level, newEntry) when (invalidate_refill) { e.invalidate() } } // refill sectored_hit }.otherwise { val r_memIdx = r_refill_tag.extract(cfg.nSectors.log2 + cfg.nSets.log2 - 1, cfg.nSectors.log2) val waddr = Mux(r_sectored_hit.valid, r_sectored_hit.bits, r_sectored_repl_addr) for ((e, i) <- sectored_entries(r_memIdx).zipWithIndex) when (waddr === i.U) { when (!r_sectored_hit.valid) { e.invalidate() } e.insert(r_refill_tag, refill_v, 0.U, newEntry) when (invalidate_refill) { e.invalidate() } } } r_gpa_valid := io.ptw.resp.bits.gpa.valid r_gpa := io.ptw.resp.bits.gpa.bits r_gpa_is_pte := io.ptw.resp.bits.gpa_is_pte } // get all entries data. val entries = all_entries.map(_.getData(vpn)) val normal_entries = entries.take(ordinary_entries.size) // parallel query PPN from [[all_entries]], if VM not enabled return VPN instead val ppn = Mux1H(hitsVec :+ !vm_enabled, (all_entries zip entries).map{ case (entry, data) => entry.ppn(vpn, data) } :+ vpn(ppnBits-1, 0)) val nPhysicalEntries = 1 + special_entry.size // generally PTW misaligned load exception. val ptw_ae_array = Cat(false.B, entries.map(_.ae_ptw).asUInt) val final_ae_array = Cat(false.B, entries.map(_.ae_final).asUInt) val ptw_pf_array = Cat(false.B, entries.map(_.pf).asUInt) val ptw_gf_array = Cat(false.B, entries.map(_.gf).asUInt) val sum = Mux(priv_v, io.ptw.gstatus.sum, io.ptw.status.sum) // if in hypervisor/machine mode, cannot read/write user entries. // if in superviosr/user mode, "If the SUM bit in the sstatus register is set, supervisor mode software may also access pages with U=1.(from spec)" val priv_rw_ok = Mux(!priv_s \|\| sum, entries.map(_.u).asUInt, 0.U) \| Mux(priv_s, ~entries.map(_.u).asUInt, 0.U) // if in hypervisor/machine mode, other than user pages, all pages are executable. // if in superviosr/user mode, only user page can execute. val priv_x_ok = Mux(priv_s, ~entries.map(_.u).asUInt, entries.map(_.u).asUInt) val stage1_bypass = Fill(entries.size, usingHypervisor.B) & (Fill(entries.size, !stage1_en) \| entries.map(_.ae_stage2).asUInt) val mxr = io.ptw.status.mxr \| Mux(priv_v, io.ptw.gstatus.mxr, false.B) // "The vsstatus field MXR, which makes execute-only pages readable, only overrides VS-stage page protection.(from spec)" val r_array = Cat(true.B, (priv_rw_ok & (entries.map(_.sr).asUInt \| Mux(mxr, entries.map(_.sx).asUInt, 0.U))) \| stage1_bypass) val w_array = Cat(true.B, (priv_rw_ok & entries.map(_.sw).asUInt) \| stage1_bypass) val x_array = Cat(true.B, (priv_x_ok & entries.map(_.sx).asUInt) \| stage1_bypass) val stage2_bypass = Fill(entries.size, !stage2_en) val hr_array = Cat(true.B, entries.map(_.hr).asUInt \| Mux(io.ptw.status.mxr, entries.map(_.hx).asUInt, 0.U) \| stage2_bypass) val hw_array = Cat(true.B, entries.map(_.hw).asUInt \| stage2_bypass) val hx_array = Cat(true.B, entries.map(_.hx).asUInt \| stage2_bypass) // These array is for each TLB entries. // user mode can read: PMA OK, TLB OK, AE OK val pr_array = Cat(Fill(nPhysicalEntries, prot_r), normal_entries.map(_.pr).asUInt) & ~(ptw_ae_array \| final_ae_array) // user mode can write: PMA OK, TLB OK, AE OK val pw_array = Cat(Fill(nPhysicalEntries, prot_w), normal_entries.map(_.pw).asUInt) & ~(ptw_ae_array \| final_ae_array) // user mode can write: PMA OK, TLB OK, AE OK val px_array = Cat(Fill(nPhysicalEntries, prot_x), normal_entries.map(_.px).asUInt) & ~(ptw_ae_array \| final_ae_array) // put effect val eff_array = Cat(Fill(nPhysicalEntries, prot_eff), normal_entries.map(_.eff).asUInt) // cacheable val c_array = Cat(Fill(nPhysicalEntries, cacheable), normal_entries.map(_.c).asUInt) // put partial val ppp_array = Cat(Fill(nPhysicalEntries, prot_pp), normal_entries.map(_.ppp).asUInt) // atomic arithmetic val paa_array = Cat(Fill(nPhysicalEntries, prot_aa), normal_entries.map(_.paa).asUInt) // atomic logic val pal_array = Cat(Fill(nPhysicalEntries, prot_al), normal_entries.map(_.pal).asUInt) val ppp_array_if_cached = ppp_array \| c_array val paa_array_if_cached = paa_array \| (if(usingAtomicsInCache) c_array else 0.U) val pal_array_if_cached = pal_array \| (if(usingAtomicsInCache) c_array else 0.U) val prefetchable_array = Cat((cacheable && homogeneous) << (nPhysicalEntries-1), normal_entries.map(_.c).asUInt) // vaddr misaligned: vaddr[1:0]=b00 val misaligned = (io.req.bits.vaddr & (UIntToOH(io.req.bits.size) - 1.U)).orR def badVA(guestPA: Boolean): Bool = { val additionalPgLevels = (if (guestPA) io.ptw.hgatp else satp).additionalPgLevels val extraBits = if (guestPA) hypervisorExtraAddrBits else 0 val signed = !guestPA val nPgLevelChoices = pgLevels - minPgLevels + 1 val minVAddrBits = pgIdxBits + minPgLevels pgLevelBits + extraBits (for (i <- 0 until nPgLevelChoices) yield { val mask = ((BigInt(1) << vaddrBitsExtended) - (BigInt(1) << (minVAddrBits + i * pgLevelBits - signed.toInt))).U val maskedVAddr = io.req.bits.vaddr & mask additionalPgLevels === i.U && !(maskedVAddr === 0.U \|\| signed.B && maskedVAddr === mask) }).orR } val bad_gpa = if (!usingHypervisor) false.B else vm_enabled && !stage1_en && badVA(true) val bad_va = if (!usingVM \|\| (minPgLevels == pgLevels && vaddrBits == vaddrBitsExtended)) false.B else vm_enabled && stage1_en && badVA(false) val cmd_lrsc = usingAtomics.B && io.req.bits.cmd.isOneOf(M_XLR, M_XSC) val cmd_amo_logical = usingAtomics.B && isAMOLogical(io.req.bits.cmd) val cmd_amo_arithmetic = usingAtomics.B && isAMOArithmetic(io.req.bits.cmd) val cmd_put_partial = io.req.bits.cmd === M_PWR val cmd_read = isRead(io.req.bits.cmd) val cmd_readx = usingHypervisor.B && io.req.bits.cmd === M_HLVX val cmd_write = isWrite(io.req.bits.cmd) val cmd_write_perms = cmd_write \|\| io.req.bits.cmd.isOneOf(M_FLUSH_ALL, M_WOK) // not a write, but needs write permissions val lrscAllowed = Mux((usingDataScratchpad \|\| usingAtomicsOnlyForIO).B, 0.U, c_array) val ae_array = Mux(misaligned, eff_array, 0.U) \| Mux(cmd_lrsc, ~lrscAllowed, 0.U) // access exception needs SoC information from PMA val ae_ld_array = Mux(cmd_read, ae_array \| ~pr_array, 0.U) val ae_st_array = Mux(cmd_write_perms, ae_array \| ~pw_array, 0.U) \| Mux(cmd_put_partial, ~ppp_array_if_cached, 0.U) \| Mux(cmd_amo_logical, ~pal_array_if_cached, 0.U) \| Mux(cmd_amo_arithmetic, ~paa_array_if_cached, 0.U) val must_alloc_array = Mux(cmd_put_partial, ~ppp_array, 0.U) \| Mux(cmd_amo_logical, ~pal_array, 0.U) \| Mux(cmd_amo_arithmetic, ~paa_array, 0.U) \| Mux(cmd_lrsc, ~0.U(pal_array.getWidth.W), 0.U) val pf_ld_array = Mux(cmd_read, ((~Mux(cmd_readx, x_array, r_array) & ~ptw_ae_array) \| ptw_pf_array) & ~ptw_gf_array, 0.U) val pf_st_array = Mux(cmd_write_perms, ((~w_array & ~ptw_ae_array) \| ptw_pf_array) & ~ptw_gf_array, 0.U) val pf_inst_array = ((~x_array & ~ptw_ae_array) \| ptw_pf_array) & ~ptw_gf_array val gf_ld_array = Mux(priv_v && cmd_read, (~Mux(cmd_readx, hx_array, hr_array) \| ptw_gf_array) & ~ptw_ae_array, 0.U) val gf_st_array = Mux(priv_v && cmd_write_perms, (~hw_array \| ptw_gf_array) & ~ptw_ae_array, 0.U) val gf_inst_array = Mux(priv_v, (~hx_array \| ptw_gf_array) & ~ptw_ae_array, 0.U) val gpa_hits = { val need_gpa_mask = if (instruction) gf_inst_array else gf_ld_array \| gf_st_array val hit_mask = Fill(ordinary_entries.size, r_gpa_valid && r_gpa_vpn === vpn) \| Fill(all_entries.size, !vstage1_en) hit_mask \| ~need_gpa_mask(all_entries.size-1, 0) } val tlb_hit_if_not_gpa_miss = real_hits.orR val tlb_hit = (real_hits & gpa_hits).orR // leads to s_request val tlb_miss = vm_enabled && !vsatp_mode_mismatch && !bad_va && !tlb_hit val sectored_plru = new SetAssocLRU(cfg.nSets, sectored_entries.head.size, "plru") val superpage_plru = new PseudoLRU(superpage_entries.size) when (io.req.valid && vm_enabled) { // replace when (sector_hits.orR) { sectored_plru.access(memIdx, OHToUInt(sector_hits)) } when (superpage_hits.orR) { superpage_plru.access(OHToUInt(superpage_hits)) } } // Superpages create the possibility that two entries in the TLB may match. // This corresponds to a software bug, but we can't return complete garbage; // we must return either the old translation or the new translation. This // isn't compatible with the Mux1H approach. So, flush the TLB and report // a miss on duplicate entries. val multipleHits = PopCountAtLeast(real_hits, 2) // only pull up req.ready when this is s_ready state. io.req.ready := state === s_ready // page fault io.resp.pf.ld := (bad_va && cmd_read) \|\| (pf_ld_array & hits).orR io.resp.pf.st := (bad_va && cmd_write_perms) \|\| (pf_st_array & hits).orR io.resp.pf.inst := bad_va \|\| (pf_inst_array & hits).orR // guest page fault io.resp.gf.ld := (bad_gpa && cmd_read) \|\| (gf_ld_array & hits).orR io.resp.gf.st := (bad_gpa && cmd_write_perms) \|\| (gf_st_array & hits).orR io.resp.gf.inst := bad_gpa \|\| (gf_inst_array & hits).orR // access exception io.resp.ae.ld := (ae_ld_array & hits).orR io.resp.ae.st := (ae_st_array & hits).orR io.resp.ae.inst := (~px_array & hits).orR // misaligned io.resp.ma.ld := misaligned && cmd_read io.resp.ma.st := misaligned && cmd_write io.resp.ma.inst := false.B // this is up to the pipeline to figure out io.resp.cacheable := (c_array & hits).orR io.resp.must_alloc := (must_alloc_array & hits).orR io.resp.prefetchable := (prefetchable_array & hits).orR && edge.manager.managers.forall(m => !m.supportsAcquireB \|\| m.supportsHint).B io.resp.miss := do_refill \|\| vsatp_mode_mismatch \|\| tlb_miss \|\| multipleHits io.resp.paddr := Cat(ppn, io.req.bits.vaddr(pgIdxBits-1, 0)) io.resp.size := io.req.bits.size io.resp.cmd := io.req.bits.cmd io.resp.gpa_is_pte := vstage1_en && r_gpa_is_pte io.resp.gpa := { val page = Mux(!vstage1_en, Cat(bad_gpa, vpn), r_gpa >> pgIdxBits) val offset = Mux(io.resp.gpa_is_pte, r_gpa(pgIdxBits-1, 0), io.req.bits.vaddr(pgIdxBits-1, 0)) Cat(page, offset) } io.ptw.req.valid := state === s_request io.ptw.req.bits.valid := !io.kill io.ptw.req.bits.bits.addr := r_refill_tag io.ptw.req.bits.bits.vstage1 := r_vstage1_en io.ptw.req.bits.bits.stage2 := r_stage2_en io.ptw.req.bits.bits.need_gpa := r_need_gpa if (usingVM) { when(io.ptw.req.fire && io.ptw.req.bits.valid) { r_gpa_valid := false.B r_gpa_vpn := r_refill_tag } val sfence = io.sfence.valid // this is [[s_ready]] // handle miss/hit at the first cycle. // if miss, request PTW(L2TLB). when (io.req.fire && tlb_miss) { state := s_request r_refill_tag := vpn r_need_gpa := tlb_hit_if_not_gpa_miss r_vstage1_en := vstage1_en r_stage2_en := stage2_en r_superpage_repl_addr := replacementEntry(superpage_entries, superpage_plru.way) r_sectored_repl_addr := replacementEntry(sectored_entries(memIdx), sectored_plru.way(memIdx)) r_sectored_hit.valid := sector_hits.orR r_sectored_hit.bits := OHToUInt(sector_hits) r_superpage_hit.valid := superpage_hits.orR r_superpage_hit.bits := OHToUInt(superpage_hits) } // Handle SFENCE.VMA when send request to PTW. // SFENCE.VMA io.ptw.req.ready kill // ? ? 1 // 0 0 0 // 0 1 0 -> s_wait // 1 0 0 -> s_wait_invalidate // 1 0 0 -> s_ready when (state === s_request) { // SFENCE.VMA will kill TLB entries based on rs1 and rs2. It will take 1 cycle. when (sfence) { state := s_ready } // here should be io.ptw.req.fire, but assert(io.ptw.req.ready === true.B) // fire -> s_wait when (io.ptw.req.ready) { state := Mux(sfence, s_wait_invalidate, s_wait) } // If CPU kills request(frontend.s2_redirect) when (io.kill) { state := s_ready } } // sfence in refill will results in invalidate when (state === s_wait && sfence) { state := s_wait_invalidate } // after CPU acquire response, go back to s_ready. when (io.ptw.resp.valid) { state := s_ready } // SFENCE processing logic. when (sfence) { assert(!io.sfence.bits.rs1 \|\| (io.sfence.bits.addr >> pgIdxBits) === vpn) for (e <- all_real_entries) { val hv = usingHypervisor.B && io.sfence.bits.hv val hg = usingHypervisor.B && io.sfence.bits.hg when (!hg && io.sfence.bits.rs1) { e.invalidateVPN(vpn, hv) } .elsewhen (!hg && io.sfence.bits.rs2) { e.invalidateNonGlobal(hv) } .otherwise { e.invalidate(hv \|\| hg) } } } when(io.req.fire && vsatp_mode_mismatch) { all_real_entries.foreach(_.invalidate(true.B)) v_entries_use_stage1 := vstage1_en } when (multipleHits \|\| reset.asBool) { all_real_entries.foreach(_.invalidate()) } ccover(io.ptw.req.fire, "MISS", "TLB miss") ccover(io.ptw.req.valid && !io.ptw.req.ready, "PTW_STALL", "TLB miss, but PTW busy") ccover(state === s_wait_invalidate, "SFENCE_DURING_REFILL", "flush TLB during TLB refill") ccover(sfence && !io.sfence.bits.rs1 && !io.sfence.bits.rs2, "SFENCE_ALL", "flush TLB") ccover(sfence && !io.sfence.bits.rs1 && io.sfence.bits.rs2, "SFENCE_ASID", "flush TLB ASID") ccover(sfence && io.sfence.bits.rs1 && !io.sfence.bits.rs2, "SFENCE_LINE", "flush TLB line") ccover(sfence && io.sfence.bits.rs1 && io.sfence.bits.rs2, "SFENCE_LINE_ASID", "flush TLB line/ASID") ccover(multipleHits, "MULTIPLE_HITS", "Two matching translations in TLB") } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = property.cover(cond, s"${if (instruction) "I" else "D"}TLB_$label", "MemorySystem;;" + desc) /** Decides which entry to be replaced * * If there is a invalid entry, replace it with priorityencoder; * if not, replace the alt entry * * @return mask for TLBEntry replacement / def replacementEntry(set: Seq[TLBEntry], alt: UInt) = { val valids = set.map(_.valid.orR).asUInt Mux(valids.andR, alt, PriorityEncoder(~valids)) } } File TLBPermissions.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes, RegionType, AddressDecoder} import freechips.rocketchip.tilelink.TLManagerParameters case class TLBPermissions( homogeneous: Bool, // if false, the below are undefined r: Bool, // readable w: Bool, // writeable x: Bool, // executable c: Bool, // cacheable a: Bool, // arithmetic ops l: Bool) // logical ops object TLBPageLookup { private case class TLBFixedPermissions( e: Boolean, // get-/put-effects r: Boolean, // readable w: Boolean, // writeable x: Boolean, // executable c: Boolean, // cacheable a: Boolean, // arithmetic ops l: Boolean) { // logical ops val useful = r \|\| w \|\| x \|\| c \|\| a \|\| l } private def groupRegions(managers: Seq[TLManagerParameters]): Map[TLBFixedPermissions, Seq[AddressSet]] = { val permissions = managers.map { m => (m.address, TLBFixedPermissions( e = Seq(RegionType.PUT_EFFECTS, RegionType.GET_EFFECTS) contains m.regionType, r = m.supportsGet \|\| m.supportsAcquireB, // if cached, never uses Get w = m.supportsPutFull \|\| m.supportsAcquireT, // if cached, never uses Put x = m.executable, c = m.supportsAcquireB, a = m.supportsArithmetic, l = m.supportsLogical)) } permissions .filter(_._2.useful) // get rid of no-permission devices .groupBy(_._2) // group by permission type .mapValues(seq => AddressSet.unify(seq.flatMap(_._1))) // coalesce same-permission regions .toMap } // Unmapped memory is considered to be inhomogeneous def apply(managers: Seq[TLManagerParameters], xLen: Int, cacheBlockBytes: Int, pageSize: BigInt, maxRequestBytes: Int): UInt => TLBPermissions = { require (isPow2(xLen) && xLen >= 8) require (isPow2(cacheBlockBytes) && cacheBlockBytes >= xLen/8) require (isPow2(pageSize) && pageSize >= cacheBlockBytes) val xferSizes = TransferSizes(cacheBlockBytes, cacheBlockBytes) val allSizes = TransferSizes(1, maxRequestBytes) val amoSizes = TransferSizes(4, xLen/8) val permissions = managers.foreach { m => require (!m.supportsGet \|\| m.supportsGet .contains(allSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsGet} Get, but must support ${allSizes}") require (!m.supportsPutFull \|\| m.supportsPutFull .contains(allSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsPutFull} PutFull, but must support ${allSizes}") require (!m.supportsPutPartial \|\| m.supportsPutPartial.contains(allSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsPutPartial} PutPartial, but must support ${allSizes}") require (!m.supportsAcquireB \|\| m.supportsAcquireB .contains(xferSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsAcquireB} AcquireB, but must support ${xferSizes}") require (!m.supportsAcquireT \|\| m.supportsAcquireT .contains(xferSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsAcquireT} AcquireT, but must support ${xferSizes}") require (!m.supportsLogical \|\| m.supportsLogical .contains(amoSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsLogical} Logical, but must support ${amoSizes}") require (!m.supportsArithmetic \|\| m.supportsArithmetic.contains(amoSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsArithmetic} Arithmetic, but must support ${amoSizes}") require (!(m.supportsAcquireB && m.supportsPutFull && !m.supportsAcquireT), s"Memory region '${m.name}' supports AcquireB (cached read) and PutFull (un-cached write) but not AcquireT (cached write)") } val grouped = groupRegions(managers) .mapValues(_.filter(_.alignment >= pageSize)) // discard any region that's not big enough def lowCostProperty(prop: TLBFixedPermissions => Boolean): UInt => Bool = { val (yesm, nom) = grouped.partition { case (k, eq) => prop(k) } val (yes, no) = (yesm.values.flatten.toList, nom.values.flatten.toList) // Find the minimal bits needed to distinguish between yes and no val decisionMask = AddressDecoder(Seq(yes, no)) def simplify(x: Seq[AddressSet]) = AddressSet.unify(x.map(_.widen(~decisionMask)).distinct) val (yesf, nof) = (simplify(yes), simplify(no)) if (yesf.size < no.size) { (x: UInt) => yesf.map(_.contains(x)).foldLeft(false.B)(_ \|\| _) } else { (x: UInt) => !nof.map(_.contains(x)).foldLeft(false.B)(_ \|\| _) } } // Derive simplified property circuits (don't care when !homo) val rfn = lowCostProperty(_.r) val wfn = lowCostProperty(_.w) val xfn = lowCostProperty(_.x) val cfn = lowCostProperty(_.c) val afn = lowCostProperty(_.a) val lfn = lowCostProperty(_.l) val homo = AddressSet.unify(grouped.values.flatten.toList) (x: UInt) => TLBPermissions( homogeneous = homo.map(_.contains(x)).foldLeft(false.B)(_ \|\| _), r = rfn(x), w = wfn(x), x = xfn(x), c = cfn(x), a = afn(x), l = lfn(x)) } // Are all pageSize intervals of mapped regions homogeneous? def homogeneous(managers: Seq[TLManagerParameters], pageSize: BigInt): Boolean = { groupRegions(managers).values.forall(_.forall(_.alignment >= pageSize)) } } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /* Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File PTW.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.{Arbiter, Cat, Decoupled, Enum, Mux1H, OHToUInt, PopCount, PriorityEncoder, PriorityEncoderOH, RegEnable, UIntToOH, Valid, is, isPow2, log2Ceil, switch} import chisel3.withClock import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.subsystem.CacheBlockBytes import freechips.rocketchip.tile._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property import scala.collection.mutable.ListBuffer /* PTE request from TLB to PTW * * TLB send a PTE request to PTW when L1TLB miss / class PTWReq(implicit p: Parameters) extends CoreBundle()(p) { val addr = UInt(vpnBits.W) val need_gpa = Bool() val vstage1 = Bool() val stage2 = Bool() } /* PTE info from L2TLB to TLB * * containing: target PTE, exceptions, two-satge tanslation info / class PTWResp(implicit p: Parameters) extends CoreBundle()(p) { /* ptw access exception / val ae_ptw = Bool() /* final access exception / val ae_final = Bool() /* page fault / val pf = Bool() /* guest page fault / val gf = Bool() /* hypervisor read / val hr = Bool() /* hypervisor write / val hw = Bool() /* hypervisor execute / val hx = Bool() /* PTE to refill L1TLB * * source: L2TLB / val pte = new PTE /* pte pglevel / val level = UInt(log2Ceil(pgLevels).W) /* fragmented_superpage support / val fragmented_superpage = Bool() /* homogeneous for both pma and pmp / val homogeneous = Bool() val gpa = Valid(UInt(vaddrBits.W)) val gpa_is_pte = Bool() } /* IO between TLB and PTW * * PTW receives : * - PTE request * - CSRs info * - pmp results from PMP(in TLB) / class TLBPTWIO(implicit p: Parameters) extends CoreBundle()(p) with HasCoreParameters { val req = Decoupled(Valid(new PTWReq)) val resp = Flipped(Valid(new PTWResp)) val ptbr = Input(new PTBR()) val hgatp = Input(new PTBR()) val vsatp = Input(new PTBR()) val status = Input(new MStatus()) val hstatus = Input(new HStatus()) val gstatus = Input(new MStatus()) val pmp = Input(Vec(nPMPs, new PMP)) val customCSRs = Flipped(coreParams.customCSRs) } /* PTW performance statistics / class PTWPerfEvents extends Bundle { val l2miss = Bool() val l2hit = Bool() val pte_miss = Bool() val pte_hit = Bool() } /* Datapath IO between PTW and Core * * PTW receives CSRs info, pmp checks, sfence instruction info * * PTW sends its performance statistics to core / class DatapathPTWIO(implicit p: Parameters) extends CoreBundle()(p) with HasCoreParameters { val ptbr = Input(new PTBR()) val hgatp = Input(new PTBR()) val vsatp = Input(new PTBR()) val sfence = Flipped(Valid(new SFenceReq)) val status = Input(new MStatus()) val hstatus = Input(new HStatus()) val gstatus = Input(new MStatus()) val pmp = Input(Vec(nPMPs, new PMP)) val perf = Output(new PTWPerfEvents()) val customCSRs = Flipped(coreParams.customCSRs) /* enable clock generated by ptw / val clock_enabled = Output(Bool()) } /* PTE template for transmission * * contains useful methods to check PTE attributes * @see RV-priv spec 4.3.1 for pgae table entry format / class PTE(implicit p: Parameters) extends CoreBundle()(p) { val reserved_for_future = UInt(10.W) val ppn = UInt(44.W) val reserved_for_software = Bits(2.W) /* dirty bit / val d = Bool() /* access bit / val a = Bool() /* global mapping / val g = Bool() /* user mode accessible / val u = Bool() /* whether the page is executable / val x = Bool() /* whether the page is writable / val w = Bool() /* whether the page is readable / val r = Bool() /* valid bit / val v = Bool() /* return true if find a pointer to next level page table / def table(dummy: Int = 0) = v && !r && !w && !x && !d && !a && !u && reserved_for_future === 0.U /* return true if find a leaf PTE / def leaf(dummy: Int = 0) = v && (r \|\| (x && !w)) && a /* user read / def ur(dummy: Int = 0) = sr() && u /* user write/ def uw(dummy: Int = 0) = sw() && u /* user execute / def ux(dummy: Int = 0) = sx() && u /* supervisor read / def sr(dummy: Int = 0) = leaf() && r /* supervisor write / def sw(dummy: Int = 0) = leaf() && w && d /* supervisor execute / def sx(dummy: Int = 0) = leaf() && x /* full permission: writable and executable in user mode / def isFullPerm(dummy: Int = 0) = uw() && ux() } /* L2TLB PTE template * * contains tag bits * @param nSets number of sets in L2TLB * @see RV-priv spec 4.3.1 for page table entry format / class L2TLBEntry(nSets: Int)(implicit p: Parameters) extends CoreBundle()(p) with HasCoreParameters { val idxBits = log2Ceil(nSets) val tagBits = maxSVAddrBits - pgIdxBits - idxBits + (if (usingHypervisor) 1 else 0) val tag = UInt(tagBits.W) val ppn = UInt(ppnBits.W) /* dirty bit / val d = Bool() /* access bit / val a = Bool() /* user mode accessible / val u = Bool() /* whether the page is executable / val x = Bool() /* whether the page is writable / val w = Bool() /* whether the page is readable / val r = Bool() } /* PTW contains L2TLB, and performs page table walk for high level TLB, and cache queries from L1 TLBs(I$, D$, RoCC) * * It performs hierarchy page table query to mem for the desired leaf PTE and cache them in l2tlb. * Besides leaf PTEs, it also caches non-leaf PTEs in pte_cache to accerlerate the process. * * ==Structure== * - l2tlb : for leaf PTEs * - set-associative (configurable with [[CoreParams.nL2TLBEntries]]and [[CoreParams.nL2TLBWays]])) * - PLRU * - pte_cache: for non-leaf PTEs * - set-associative * - LRU * - s2_pte_cache: for non-leaf PTEs in 2-stage translation * - set-associative * - PLRU * * l2tlb Pipeline: 3 stage * {{{ * stage 0 : read * stage 1 : decode * stage 2 : hit check * }}} * ==State Machine== * s_ready: ready to reveive request from TLB * s_req: request mem; pte_cache hit judge * s_wait1: deal with l2tlb error * s_wait2: final hit judge * s_wait3: receive mem response * s_fragment_superpage: for superpage PTE * * @note l2tlb hit happens in s_req or s_wait1 * @see RV-priv spec 4.3-4.6 for Virtual-Memory System * @see RV-priv spec 8.5 for Two-Stage Address Translation * @todo details in two-stage translation / class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(p) { val io = IO(new Bundle { /* to n TLB / val requestor = Flipped(Vec(n, new TLBPTWIO)) /* to HellaCache / val mem = new HellaCacheIO /* to Core * * contains CSRs info and performance statistics / val dpath = new DatapathPTWIO }) val s_ready :: s_req :: s_wait1 :: s_dummy1 :: s_wait2 :: s_wait3 :: s_dummy2 :: s_fragment_superpage :: Nil = Enum(8) val state = RegInit(s_ready) val l2_refill_wire = Wire(Bool()) /* Arbiter to arbite request from n TLB / val arb = Module(new Arbiter(Valid(new PTWReq), n)) // use TLB req as arbitor's input arb.io.in <> io.requestor.map(_.req) // receive req only when s_ready and not in refill arb.io.out.ready := (state === s_ready) && !l2_refill_wire val resp_valid = RegNext(VecInit(Seq.fill(io.requestor.size)(false.B))) val clock_en = state =/= s_ready \|\| l2_refill_wire \|\| arb.io.out.valid \|\| io.dpath.sfence.valid \|\| io.dpath.customCSRs.disableDCacheClockGate io.dpath.clock_enabled := usingVM.B && clock_en val gated_clock = if (!usingVM \|\| !tileParams.dcache.get.clockGate) clock else ClockGate(clock, clock_en, "ptw_clock_gate") withClock (gated_clock) { // entering gated-clock domain val invalidated = Reg(Bool()) /* current PTE level * {{{ * 0 <= count <= pgLevel-1 * count = pgLevel - 1 : leaf PTE * count < pgLevel - 1 : non-leaf PTE * }}} / val count = Reg(UInt(log2Ceil(pgLevels).W)) val resp_ae_ptw = Reg(Bool()) val resp_ae_final = Reg(Bool()) val resp_pf = Reg(Bool()) val resp_gf = Reg(Bool()) val resp_hr = Reg(Bool()) val resp_hw = Reg(Bool()) val resp_hx = Reg(Bool()) val resp_fragmented_superpage = Reg(Bool()) /* tlb request / val r_req = Reg(new PTWReq) /* current selected way in arbitor / val r_req_dest = Reg(Bits()) // to respond to L1TLB : l2_hit // to construct mem.req.addr val r_pte = Reg(new PTE) val r_hgatp = Reg(new PTBR) // 2-stage pageLevel val aux_count = Reg(UInt(log2Ceil(pgLevels).W)) /* pte for 2-stage translation / val aux_pte = Reg(new PTE) val gpa_pgoff = Reg(UInt(pgIdxBits.W)) // only valid in resp_gf case val stage2 = Reg(Bool()) val stage2_final = Reg(Bool()) val satp = Mux(arb.io.out.bits.bits.vstage1, io.dpath.vsatp, io.dpath.ptbr) val r_hgatp_initial_count = pgLevels.U - minPgLevels.U - r_hgatp.additionalPgLevels /* 2-stage translation both enable / val do_both_stages = r_req.vstage1 && r_req.stage2 val max_count = count max aux_count val vpn = Mux(r_req.vstage1 && stage2, aux_pte.ppn, r_req.addr) val mem_resp_valid = RegNext(io.mem.resp.valid) val mem_resp_data = RegNext(io.mem.resp.bits.data) io.mem.uncached_resp.map { resp => assert(!(resp.valid && io.mem.resp.valid)) resp.ready := true.B when (resp.valid) { mem_resp_valid := true.B mem_resp_data := resp.bits.data } } // construct pte from mem.resp val (pte, invalid_paddr, invalid_gpa) = { val tmp = mem_resp_data.asTypeOf(new PTE()) val res = WireDefault(tmp) res.ppn := Mux(do_both_stages && !stage2, tmp.ppn(vpnBits.min(tmp.ppn.getWidth)-1, 0), tmp.ppn(ppnBits-1, 0)) when (tmp.r \|\| tmp.w \|\| tmp.x) { // for superpage mappings, make sure PPN LSBs are zero for (i <- 0 until pgLevels-1) when (count <= i.U && tmp.ppn((pgLevels-1-i)pgLevelBits-1, (pgLevels-2-i)pgLevelBits) =/= 0.U) { res.v := false.B } } (res, Mux(do_both_stages && !stage2, (tmp.ppn >> vpnBits) =/= 0.U, (tmp.ppn >> ppnBits) =/= 0.U), do_both_stages && !stage2 && checkInvalidHypervisorGPA(r_hgatp, tmp.ppn)) } // find non-leaf PTE, need traverse val traverse = pte.table() && !invalid_paddr && !invalid_gpa && count < (pgLevels-1).U /* address send to mem for enquerry / val pte_addr = if (!usingVM) 0.U else { val vpn_idxs = (0 until pgLevels).map { i => val width = pgLevelBits + (if (i <= pgLevels - minPgLevels) hypervisorExtraAddrBits else 0) (vpn >> (pgLevels - i - 1) pgLevelBits)(width - 1, 0) } val mask = Mux(stage2 && count === r_hgatp_initial_count, ((1 << (hypervisorExtraAddrBits + pgLevelBits)) - 1).U, ((1 << pgLevelBits) - 1).U) val vpn_idx = vpn_idxs(count) & mask val raw_pte_addr = ((r_pte.ppn << pgLevelBits) \| vpn_idx) << log2Ceil(xLen / 8) val size = if (usingHypervisor) vaddrBits else paddrBits //use r_pte.ppn as page table base address //use vpn slice as offset raw_pte_addr.apply(size.min(raw_pte_addr.getWidth) - 1, 0) } /** stage2_pte_cache input addr / val stage2_pte_cache_addr = if (!usingHypervisor) 0.U else { val vpn_idxs = (0 until pgLevels - 1).map { i => (r_req.addr >> (pgLevels - i - 1) pgLevelBits)(pgLevelBits - 1, 0) } val vpn_idx = vpn_idxs(aux_count) val raw_s2_pte_cache_addr = Cat(aux_pte.ppn, vpn_idx) << log2Ceil(xLen / 8) raw_s2_pte_cache_addr(vaddrBits.min(raw_s2_pte_cache_addr.getWidth) - 1, 0) } def makeFragmentedSuperpagePPN(ppn: UInt): Seq[UInt] = { (pgLevels-1 until 0 by -1).map(i => Cat(ppn >> (pgLevelBitsi), r_req.addr(((pgLevelBitsi) min vpnBits)-1, 0).padTo(pgLevelBitsi))) } /* PTECache caches non-leaf PTE * @param s2 true: 2-stage address translation / def makePTECache(s2: Boolean): (Bool, UInt) = if (coreParams.nPTECacheEntries == 0) { (false.B, 0.U) } else { val plru = new PseudoLRU(coreParams.nPTECacheEntries) val valid = RegInit(0.U(coreParams.nPTECacheEntries.W)) val tags = Reg(Vec(coreParams.nPTECacheEntries, UInt((if (usingHypervisor) 1 + vaddrBits else paddrBits).W))) // not include full pte, only ppn val data = Reg(Vec(coreParams.nPTECacheEntries, UInt((if (usingHypervisor && s2) vpnBits else ppnBits).W))) val can_hit = if (s2) count === r_hgatp_initial_count && aux_count < (pgLevels-1).U && r_req.vstage1 && stage2 && !stage2_final else count < (pgLevels-1).U && Mux(r_req.vstage1, stage2, !r_req.stage2) val can_refill = if (s2) do_both_stages && !stage2 && !stage2_final else can_hit val tag = if (s2) Cat(true.B, stage2_pte_cache_addr.padTo(vaddrBits)) else Cat(r_req.vstage1, pte_addr.padTo(if (usingHypervisor) vaddrBits else paddrBits)) val hits = tags.map(_ === tag).asUInt & valid val hit = hits.orR && can_hit // refill with mem response when (mem_resp_valid && traverse && can_refill && !hits.orR && !invalidated) { val r = Mux(valid.andR, plru.way, PriorityEncoder(~valid)) valid := valid \| UIntToOH(r) tags(r) := tag data(r) := pte.ppn plru.access(r) } // replace when (hit && state === s_req) { plru.access(OHToUInt(hits)) } when (io.dpath.sfence.valid && (!io.dpath.sfence.bits.rs1 \|\| usingHypervisor.B && io.dpath.sfence.bits.hg)) { valid := 0.U } val lcount = if (s2) aux_count else count for (i <- 0 until pgLevels-1) { ccover(hit && state === s_req && lcount === i.U, s"PTE_CACHE_HIT_L$i", s"PTE cache hit, level $i") } (hit, Mux1H(hits, data)) } // generate pte_cache val (pte_cache_hit, pte_cache_data) = makePTECache(false) // generate pte_cache with 2-stage translation val (stage2_pte_cache_hit, stage2_pte_cache_data) = makePTECache(true) // pte_cache hit or 2-stage pte_cache hit val pte_hit = RegNext(false.B) io.dpath.perf.pte_miss := false.B io.dpath.perf.pte_hit := pte_hit && (state === s_req) && !io.dpath.perf.l2hit assert(!(io.dpath.perf.l2hit && (io.dpath.perf.pte_miss \|\| io.dpath.perf.pte_hit)), "PTE Cache Hit/Miss Performance Monitor Events are lower priority than L2TLB Hit event") // l2_refill happens when find the leaf pte val l2_refill = RegNext(false.B) l2_refill_wire := l2_refill io.dpath.perf.l2miss := false.B io.dpath.perf.l2hit := false.B // l2tlb val (l2_hit, l2_error, l2_pte, l2_tlb_ram) = if (coreParams.nL2TLBEntries == 0) (false.B, false.B, WireDefault(0.U.asTypeOf(new PTE)), None) else { val code = new ParityCode require(isPow2(coreParams.nL2TLBEntries)) require(isPow2(coreParams.nL2TLBWays)) require(coreParams.nL2TLBEntries >= coreParams.nL2TLBWays) val nL2TLBSets = coreParams.nL2TLBEntries / coreParams.nL2TLBWays require(isPow2(nL2TLBSets)) val idxBits = log2Ceil(nL2TLBSets) val l2_plru = new SetAssocLRU(nL2TLBSets, coreParams.nL2TLBWays, "plru") val ram = DescribedSRAM( name = "l2_tlb_ram", desc = "L2 TLB", size = nL2TLBSets, data = Vec(coreParams.nL2TLBWays, UInt(code.width(new L2TLBEntry(nL2TLBSets).getWidth).W)) ) val g = Reg(Vec(coreParams.nL2TLBWays, UInt(nL2TLBSets.W))) val valid = RegInit(VecInit(Seq.fill(coreParams.nL2TLBWays)(0.U(nL2TLBSets.W)))) // use r_req to construct tag val (r_tag, r_idx) = Split(Cat(r_req.vstage1, r_req.addr(maxSVAddrBits-pgIdxBits-1, 0)), idxBits) /* the valid vec for the selected set(including n ways) / val r_valid_vec = valid.map(_(r_idx)).asUInt val r_valid_vec_q = Reg(UInt(coreParams.nL2TLBWays.W)) val r_l2_plru_way = Reg(UInt(log2Ceil(coreParams.nL2TLBWays max 1).W)) r_valid_vec_q := r_valid_vec // replacement way r_l2_plru_way := (if (coreParams.nL2TLBWays > 1) l2_plru.way(r_idx) else 0.U) // refill with r_pte(leaf pte) when (l2_refill && !invalidated) { val entry = Wire(new L2TLBEntry(nL2TLBSets)) entry.ppn := r_pte.ppn entry.d := r_pte.d entry.a := r_pte.a entry.u := r_pte.u entry.x := r_pte.x entry.w := r_pte.w entry.r := r_pte.r entry.tag := r_tag // if all the way are valid, use plru to select one way to be replaced, // otherwise use PriorityEncoderOH to select one val wmask = if (coreParams.nL2TLBWays > 1) Mux(r_valid_vec_q.andR, UIntToOH(r_l2_plru_way, coreParams.nL2TLBWays), PriorityEncoderOH(~r_valid_vec_q)) else 1.U(1.W) ram.write(r_idx, VecInit(Seq.fill(coreParams.nL2TLBWays)(code.encode(entry.asUInt))), wmask.asBools) val mask = UIntToOH(r_idx) for (way <- 0 until coreParams.nL2TLBWays) { when (wmask(way)) { valid(way) := valid(way) \| mask g(way) := Mux(r_pte.g, g(way) \| mask, g(way) & ~mask) } } } // sfence happens when (io.dpath.sfence.valid) { val hg = usingHypervisor.B && io.dpath.sfence.bits.hg for (way <- 0 until coreParams.nL2TLBWays) { valid(way) := Mux(!hg && io.dpath.sfence.bits.rs1, valid(way) & ~UIntToOH(io.dpath.sfence.bits.addr(idxBits+pgIdxBits-1, pgIdxBits)), Mux(!hg && io.dpath.sfence.bits.rs2, valid(way) & g(way), 0.U)) } } val s0_valid = !l2_refill && arb.io.out.fire val s0_suitable = arb.io.out.bits.bits.vstage1 === arb.io.out.bits.bits.stage2 && !arb.io.out.bits.bits.need_gpa val s1_valid = RegNext(s0_valid && s0_suitable && arb.io.out.bits.valid) val s2_valid = RegNext(s1_valid) // read from tlb idx val s1_rdata = ram.read(arb.io.out.bits.bits.addr(idxBits-1, 0), s0_valid) val s2_rdata = s1_rdata.map(s1_rdway => code.decode(RegEnable(s1_rdway, s1_valid))) val s2_valid_vec = RegEnable(r_valid_vec, s1_valid) val s2_g_vec = RegEnable(VecInit(g.map(_(r_idx))), s1_valid) val s2_error = (0 until coreParams.nL2TLBWays).map(way => s2_valid_vec(way) && s2_rdata(way).error).orR when (s2_valid && s2_error) { valid.foreach { _ := 0.U }} // decode val s2_entry_vec = s2_rdata.map(_.uncorrected.asTypeOf(new L2TLBEntry(nL2TLBSets))) val s2_hit_vec = (0 until coreParams.nL2TLBWays).map(way => s2_valid_vec(way) && (r_tag === s2_entry_vec(way).tag)) val s2_hit = s2_valid && s2_hit_vec.orR io.dpath.perf.l2miss := s2_valid && !(s2_hit_vec.orR) io.dpath.perf.l2hit := s2_hit when (s2_hit) { l2_plru.access(r_idx, OHToUInt(s2_hit_vec)) assert((PopCount(s2_hit_vec) === 1.U) \|\| s2_error, "L2 TLB multi-hit") } val s2_pte = Wire(new PTE) val s2_hit_entry = Mux1H(s2_hit_vec, s2_entry_vec) s2_pte.ppn := s2_hit_entry.ppn s2_pte.d := s2_hit_entry.d s2_pte.a := s2_hit_entry.a s2_pte.g := Mux1H(s2_hit_vec, s2_g_vec) s2_pte.u := s2_hit_entry.u s2_pte.x := s2_hit_entry.x s2_pte.w := s2_hit_entry.w s2_pte.r := s2_hit_entry.r s2_pte.v := true.B s2_pte.reserved_for_future := 0.U s2_pte.reserved_for_software := 0.U for (way <- 0 until coreParams.nL2TLBWays) { ccover(s2_hit && s2_hit_vec(way), s"L2_TLB_HIT_WAY$way", s"L2 TLB hit way$way") } (s2_hit, s2_error, s2_pte, Some(ram)) } // if SFENCE occurs during walk, don't refill PTE cache or L2 TLB until next walk invalidated := io.dpath.sfence.valid \|\| (invalidated && state =/= s_ready) // mem request io.mem.keep_clock_enabled := false.B io.mem.req.valid := state === s_req \|\| state === s_dummy1 io.mem.req.bits.phys := true.B io.mem.req.bits.cmd := M_XRD io.mem.req.bits.size := log2Ceil(xLen/8).U io.mem.req.bits.signed := false.B io.mem.req.bits.addr := pte_addr io.mem.req.bits.idx.foreach(_ := pte_addr) io.mem.req.bits.dprv := PRV.S.U // PTW accesses are S-mode by definition io.mem.req.bits.dv := do_both_stages && !stage2 io.mem.req.bits.tag := DontCare io.mem.req.bits.no_resp := false.B io.mem.req.bits.no_alloc := DontCare io.mem.req.bits.no_xcpt := DontCare io.mem.req.bits.data := DontCare io.mem.req.bits.mask := DontCare io.mem.s1_kill := l2_hit \|\| (state =/= s_wait1) \|\| resp_gf io.mem.s1_data := DontCare io.mem.s2_kill := false.B val pageGranularityPMPs = pmpGranularity >= (1 << pgIdxBits) require(!usingHypervisor \|\| pageGranularityPMPs, s"hypervisor requires pmpGranularity >= ${1<<pgIdxBits}") val pmaPgLevelHomogeneous = (0 until pgLevels) map { i => val pgSize = BigInt(1) << (pgIdxBits + ((pgLevels - 1 - i) pgLevelBits)) if (pageGranularityPMPs && i == pgLevels - 1) { require(TLBPageLookup.homogeneous(edge.manager.managers, pgSize), s"All memory regions must be $pgSize-byte aligned") true.B } else { TLBPageLookup(edge.manager.managers, xLen, p(CacheBlockBytes), pgSize, xLen/8)(r_pte.ppn << pgIdxBits).homogeneous } } val pmaHomogeneous = pmaPgLevelHomogeneous(count) val pmpHomogeneous = new PMPHomogeneityChecker(io.dpath.pmp).apply(r_pte.ppn << pgIdxBits, count) val homogeneous = pmaHomogeneous && pmpHomogeneous // response to tlb for (i <- 0 until io.requestor.size) { io.requestor(i).resp.valid := resp_valid(i) io.requestor(i).resp.bits.ae_ptw := resp_ae_ptw io.requestor(i).resp.bits.ae_final := resp_ae_final io.requestor(i).resp.bits.pf := resp_pf io.requestor(i).resp.bits.gf := resp_gf io.requestor(i).resp.bits.hr := resp_hr io.requestor(i).resp.bits.hw := resp_hw io.requestor(i).resp.bits.hx := resp_hx io.requestor(i).resp.bits.pte := r_pte io.requestor(i).resp.bits.level := max_count io.requestor(i).resp.bits.homogeneous := homogeneous \|\| pageGranularityPMPs.B io.requestor(i).resp.bits.fragmented_superpage := resp_fragmented_superpage && pageGranularityPMPs.B io.requestor(i).resp.bits.gpa.valid := r_req.need_gpa io.requestor(i).resp.bits.gpa.bits := Cat(Mux(!stage2_final \|\| !r_req.vstage1 \|\| aux_count === (pgLevels - 1).U, aux_pte.ppn, makeFragmentedSuperpagePPN(aux_pte.ppn)(aux_count)), gpa_pgoff) io.requestor(i).resp.bits.gpa_is_pte := !stage2_final io.requestor(i).ptbr := io.dpath.ptbr io.requestor(i).hgatp := io.dpath.hgatp io.requestor(i).vsatp := io.dpath.vsatp io.requestor(i).customCSRs <> io.dpath.customCSRs io.requestor(i).status := io.dpath.status io.requestor(i).hstatus := io.dpath.hstatus io.requestor(i).gstatus := io.dpath.gstatus io.requestor(i).pmp := io.dpath.pmp } // control state machine val next_state = WireDefault(state) state := OptimizationBarrier(next_state) val do_switch = WireDefault(false.B) switch (state) { is (s_ready) { when (arb.io.out.fire) { val satp_initial_count = pgLevels.U - minPgLevels.U - satp.additionalPgLevels val vsatp_initial_count = pgLevels.U - minPgLevels.U - io.dpath.vsatp.additionalPgLevels val hgatp_initial_count = pgLevels.U - minPgLevels.U - io.dpath.hgatp.additionalPgLevels val aux_ppn = Mux(arb.io.out.bits.bits.vstage1, io.dpath.vsatp.ppn, arb.io.out.bits.bits.addr) r_req := arb.io.out.bits.bits r_req_dest := arb.io.chosen next_state := Mux(arb.io.out.bits.valid, s_req, s_ready) stage2 := arb.io.out.bits.bits.stage2 stage2_final := arb.io.out.bits.bits.stage2 && !arb.io.out.bits.bits.vstage1 count := Mux(arb.io.out.bits.bits.stage2, hgatp_initial_count, satp_initial_count) aux_count := Mux(arb.io.out.bits.bits.vstage1, vsatp_initial_count, 0.U) aux_pte.ppn := aux_ppn aux_pte.reserved_for_future := 0.U resp_ae_ptw := false.B resp_ae_final := false.B resp_pf := false.B resp_gf := checkInvalidHypervisorGPA(io.dpath.hgatp, aux_ppn) && arb.io.out.bits.bits.stage2 resp_hr := true.B resp_hw := true.B resp_hx := true.B resp_fragmented_superpage := false.B r_hgatp := io.dpath.hgatp assert(!arb.io.out.bits.bits.need_gpa \|\| arb.io.out.bits.bits.stage2) } } is (s_req) { when(stage2 && count === r_hgatp_initial_count) { gpa_pgoff := Mux(aux_count === (pgLevels-1).U, r_req.addr << (xLen/8).log2, stage2_pte_cache_addr) } // pte_cache hit when (stage2_pte_cache_hit) { aux_count := aux_count + 1.U aux_pte.ppn := stage2_pte_cache_data aux_pte.reserved_for_future := 0.U pte_hit := true.B }.elsewhen (pte_cache_hit) { count := count + 1.U pte_hit := true.B }.otherwise { next_state := Mux(io.mem.req.ready, s_wait1, s_req) } when(resp_gf) { next_state := s_ready resp_valid(r_req_dest) := true.B } } is (s_wait1) { // This Mux is for the l2_error case; the l2_hit && !l2_error case is overriden below next_state := Mux(l2_hit, s_req, s_wait2) } is (s_wait2) { next_state := s_wait3 io.dpath.perf.pte_miss := count < (pgLevels-1).U when (io.mem.s2_xcpt.ae.ld) { resp_ae_ptw := true.B next_state := s_ready resp_valid(r_req_dest) := true.B } } is (s_fragment_superpage) { next_state := s_ready resp_valid(r_req_dest) := true.B when (!homogeneous) { count := (pgLevels-1).U resp_fragmented_superpage := true.B } when (do_both_stages) { resp_fragmented_superpage := true.B } } } val merged_pte = { val superpage_masks = (0 until pgLevels).map(i => ((BigInt(1) << pte.ppn.getWidth) - (BigInt(1) << (pgLevels-1-i)pgLevelBits)).U) val superpage_mask = superpage_masks(Mux(stage2_final, max_count, (pgLevels-1).U)) val stage1_ppns = (0 until pgLevels-1).map(i => Cat(pte.ppn(pte.ppn.getWidth-1, (pgLevels-i-1)pgLevelBits), aux_pte.ppn((pgLevels-i-1)pgLevelBits-1,0))) :+ pte.ppn val stage1_ppn = stage1_ppns(count) makePTE(stage1_ppn & superpage_mask, aux_pte) } r_pte := OptimizationBarrier( // l2tlb hit->find a leaf PTE(l2_pte), respond to L1TLB Mux(l2_hit && !l2_error && !resp_gf, l2_pte, // S2 PTE cache hit -> proceed to the next level of walking, update the r_pte with hgatp Mux(state === s_req && stage2_pte_cache_hit, makeHypervisorRootPTE(r_hgatp, stage2_pte_cache_data, l2_pte), // pte cache hit->find a non-leaf PTE(pte_cache),continue to request mem Mux(state === s_req && pte_cache_hit, makePTE(pte_cache_data, l2_pte), // 2-stage translation Mux(do_switch, makeHypervisorRootPTE(r_hgatp, pte.ppn, r_pte), // when mem respond, store mem.resp.pte Mux(mem_resp_valid, Mux(!traverse && r_req.vstage1 && stage2, merged_pte, pte), // fragment_superpage Mux(state === s_fragment_superpage && !homogeneous && count =/= (pgLevels - 1).U, makePTE(makeFragmentedSuperpagePPN(r_pte.ppn)(count), r_pte), // when tlb request come->request mem, use root address in satp(or vsatp,hgatp) Mux(arb.io.out.fire, Mux(arb.io.out.bits.bits.stage2, makeHypervisorRootPTE(io.dpath.hgatp, io.dpath.vsatp.ppn, r_pte), makePTE(satp.ppn, r_pte)), r_pte)))))))) when (l2_hit && !l2_error && !resp_gf) { assert(state === s_req \|\| state === s_wait1) next_state := s_ready resp_valid(r_req_dest) := true.B count := (pgLevels-1).U } when (mem_resp_valid) { assert(state === s_wait3) next_state := s_req when (traverse) { when (do_both_stages && !stage2) { do_switch := true.B } count := count + 1.U }.otherwise { val gf = (stage2 && !stage2_final && !pte.ur()) \|\| (pte.leaf() && pte.reserved_for_future === 0.U && invalid_gpa) val ae = pte.v && invalid_paddr val pf = pte.v && pte.reserved_for_future =/= 0.U val success = pte.v && !ae && !pf && !gf when (do_both_stages && !stage2_final && success) { when (stage2) { stage2 := false.B count := aux_count }.otherwise { stage2_final := true.B do_switch := true.B } }.otherwise { // find a leaf pte, start l2 refill l2_refill := success && count === (pgLevels-1).U && !r_req.need_gpa && (!r_req.vstage1 && !r_req.stage2 \|\| do_both_stages && aux_count === (pgLevels-1).U && pte.isFullPerm()) count := max_count when (pageGranularityPMPs.B && !(count === (pgLevels-1).U && (!do_both_stages \|\| aux_count === (pgLevels-1).U))) { next_state := s_fragment_superpage }.otherwise { next_state := s_ready resp_valid(r_req_dest) := true.B } resp_ae_ptw := ae && count < (pgLevels-1).U && pte.table() resp_ae_final := ae && pte.leaf() resp_pf := pf && !stage2 resp_gf := gf \|\| (pf && stage2) resp_hr := !stage2 \|\| (!pf && !gf && pte.ur()) resp_hw := !stage2 \|\| (!pf && !gf && pte.uw()) resp_hx := !stage2 \|\| (!pf && !gf && pte.ux()) } } } when (io.mem.s2_nack) { assert(state === s_wait2) next_state := s_req } when (do_switch) { aux_count := Mux(traverse, count + 1.U, count) count := r_hgatp_initial_count aux_pte := Mux(traverse, pte, { val s1_ppns = (0 until pgLevels-1).map(i => Cat(pte.ppn(pte.ppn.getWidth-1, (pgLevels-i-1)pgLevelBits), r_req.addr(((pgLevels-i-1)pgLevelBits min vpnBits)-1,0).padTo((pgLevels-i-1)pgLevelBits))) :+ pte.ppn makePTE(s1_ppns(count), pte) }) stage2 := true.B } for (i <- 0 until pgLevels) { val leaf = mem_resp_valid && !traverse && count === i.U ccover(leaf && pte.v && !invalid_paddr && !invalid_gpa && pte.reserved_for_future === 0.U, s"L$i", s"successful page-table access, level $i") ccover(leaf && pte.v && invalid_paddr, s"L${i}_BAD_PPN_MSB", s"PPN too large, level $i") ccover(leaf && pte.v && invalid_gpa, s"L${i}_BAD_GPA_MSB", s"GPA too large, level $i") ccover(leaf && pte.v && pte.reserved_for_future =/= 0.U, s"L${i}_BAD_RSV_MSB", s"reserved MSBs set, level $i") ccover(leaf && !mem_resp_data(0), s"L${i}_INVALID_PTE", s"page not present, level $i") if (i != pgLevels-1) ccover(leaf && !pte.v && mem_resp_data(0), s"L${i}_BAD_PPN_LSB", s"PPN LSBs not zero, level $i") } ccover(mem_resp_valid && count === (pgLevels-1).U && pte.table(), s"TOO_DEEP", s"page table too deep") ccover(io.mem.s2_nack, "NACK", "D$ nacked page-table access") ccover(state === s_wait2 && io.mem.s2_xcpt.ae.ld, "AE", "access exception while walking page table") } // leaving gated-clock domain private def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = if (usingVM) property.cover(cond, s"PTW_$label", "MemorySystem;;" + desc) /** Relace PTE.ppn with ppn / private def makePTE(ppn: UInt, default: PTE) = { val pte = WireDefault(default) pte.ppn := ppn pte } /* use hgatp and vpn to construct a new ppn / private def makeHypervisorRootPTE(hgatp: PTBR, vpn: UInt, default: PTE) = { val count = pgLevels.U - minPgLevels.U - hgatp.additionalPgLevels val idxs = (0 to pgLevels-minPgLevels).map(i => (vpn >> (pgLevels-i)pgLevelBits)) val lsbs = WireDefault(UInt(maxHypervisorExtraAddrBits.W), idxs(count)) val pte = WireDefault(default) pte.ppn := Cat(hgatp.ppn >> maxHypervisorExtraAddrBits, lsbs) pte } /** use hgatp and vpn to check for gpa out of range / private def checkInvalidHypervisorGPA(hgatp: PTBR, vpn: UInt) = { val count = pgLevels.U - minPgLevels.U - hgatp.additionalPgLevels val idxs = (0 to pgLevels-minPgLevels).map(i => (vpn >> ((pgLevels-i)pgLevelBits)+maxHypervisorExtraAddrBits)) idxs.extract(count) =/= 0.U } } /** Mix-ins for constructing tiles that might have a PTW / trait CanHavePTW extends HasTileParameters with HasHellaCache { this: BaseTile => val module: CanHavePTWModule var nPTWPorts = 1 nDCachePorts += usingPTW.toInt } trait CanHavePTWModule extends HasHellaCacheModule { val outer: CanHavePTW val ptwPorts = ListBuffer(outer.dcache.module.io.ptw) val ptw = Module(new PTW(outer.nPTWPorts)(outer.dcache.node.edges.out(0), outer.p)) ptw.io.mem <> DontCare if (outer.usingPTW) { dcachePorts += ptw.io.mem } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph / def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File DCache.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import freechips.rocketchip.amba.AMBAProt import freechips.rocketchip.diplomacy.{BufferParams} import freechips.rocketchip.prci.{ClockCrossingType, RationalCrossing, SynchronousCrossing, AsynchronousCrossing, CreditedCrossing} import freechips.rocketchip.tile.{CoreBundle, LookupByHartId} import freechips.rocketchip.tilelink.{TLFIFOFixer,ClientMetadata, TLBundleA, TLAtomics, TLBundleB, TLPermissions} import freechips.rocketchip.tilelink.TLMessages.{AccessAck, HintAck, AccessAckData, Grant, GrantData, ReleaseAck} import freechips.rocketchip.util.{CanHaveErrors, ClockGate, IdentityCode, ReplacementPolicy, DescribedSRAM, property} import freechips.rocketchip.util.BooleanToAugmentedBoolean import freechips.rocketchip.util.UIntToAugmentedUInt import freechips.rocketchip.util.UIntIsOneOf import freechips.rocketchip.util.IntToAugmentedInt import freechips.rocketchip.util.SeqToAugmentedSeq import freechips.rocketchip.util.SeqBoolBitwiseOps // TODO: delete this trait once deduplication is smart enough to avoid globally inlining matching circuits trait InlineInstance { self: chisel3.experimental.BaseModule => chisel3.experimental.annotate( new chisel3.experimental.ChiselAnnotation { def toFirrtl: firrtl.annotations.Annotation = firrtl.passes.InlineAnnotation(self.toNamed) } ) } class DCacheErrors(implicit p: Parameters) extends L1HellaCacheBundle()(p) with CanHaveErrors { val correctable = (cacheParams.tagCode.canCorrect \|\| cacheParams.dataCode.canCorrect).option(Valid(UInt(paddrBits.W))) val uncorrectable = (cacheParams.tagCode.canDetect \|\| cacheParams.dataCode.canDetect).option(Valid(UInt(paddrBits.W))) val bus = Valid(UInt(paddrBits.W)) } class DCacheDataReq(implicit p: Parameters) extends L1HellaCacheBundle()(p) { val addr = UInt(untagBits.W) val write = Bool() val wdata = UInt((encBits rowBytes / eccBytes).W) val wordMask = UInt((rowBytes / subWordBytes).W) val eccMask = UInt((wordBytes / eccBytes).W) val way_en = UInt(nWays.W) } class DCacheDataArray(implicit p: Parameters) extends L1HellaCacheModule()(p) { val io = IO(new Bundle { val req = Flipped(Valid(new DCacheDataReq)) val resp = Output(Vec(nWays, UInt((req.bits.wdata.getWidth).W))) }) require(rowBits % subWordBits == 0, "rowBits must be a multiple of subWordBits") val eccMask = if (eccBits == subWordBits) Seq(true.B) else io.req.bits.eccMask.asBools val wMask = if (nWays == 1) eccMask else (0 until nWays).flatMap(i => eccMask.map(_ && io.req.bits.way_en(i))) val wWords = io.req.bits.wdata.grouped(encBits * (subWordBits / eccBits)) val addr = io.req.bits.addr >> rowOffBits val data_arrays = Seq.tabulate(rowBits / subWordBits) { i => DescribedSRAM( name = s"${tileParams.baseName}_dcache_data_arrays_${i}", desc = "DCache Data Array", size = nSets * cacheBlockBytes / rowBytes, data = Vec(nWays * (subWordBits / eccBits), UInt(encBits.W)) ) } val rdata = for ((array , i) <- data_arrays.zipWithIndex) yield { val valid = io.req.valid && ((data_arrays.size == 1).B \|\| io.req.bits.wordMask(i)) when (valid && io.req.bits.write) { val wMaskSlice = (0 until wMask.size).filter(j => i % (wordBits/subWordBits) == (j % (wordBytes/eccBytes)) / (subWordBytes/eccBytes)).map(wMask(_)) val wData = wWords(i).grouped(encBits) array.write(addr, VecInit((0 until nWays).flatMap(i => wData)), wMaskSlice) } val data = array.read(addr, valid && !io.req.bits.write) data.grouped(subWordBits / eccBits).map(_.asUInt).toSeq } (io.resp zip rdata.transpose).foreach { case (resp, data) => resp := data.asUInt } } class DCacheMetadataReq(implicit p: Parameters) extends L1HellaCacheBundle()(p) { val write = Bool() val addr = UInt(vaddrBitsExtended.W) val idx = UInt(idxBits.W) val way_en = UInt(nWays.W) val data = UInt(cacheParams.tagCode.width(new L1Metadata().getWidth).W) } class DCache(staticIdForMetadataUseOnly: Int, val crossing: ClockCrossingType)(implicit p: Parameters) extends HellaCache(staticIdForMetadataUseOnly)(p) { override lazy val module = new DCacheModule(this) } class DCacheTLBPort(implicit p: Parameters) extends CoreBundle()(p) { val req = Flipped(Decoupled(new TLBReq(coreDataBytes.log2))) val s1_resp = Output(new TLBResp(coreDataBytes.log2)) val s2_kill = Input(Bool()) } class DCacheModule(outer: DCache) extends HellaCacheModule(outer) { val tECC = cacheParams.tagCode val dECC = cacheParams.dataCode require(subWordBits % eccBits == 0, "subWordBits must be a multiple of eccBits") require(eccBytes == 1 \|\| !dECC.isInstanceOf[IdentityCode]) require(cacheParams.silentDrop \|\| cacheParams.acquireBeforeRelease, "!silentDrop requires acquireBeforeRelease") val usingRMW = eccBytes > 1 \|\| usingAtomicsInCache val mmioOffset = outer.firstMMIO edge.manager.requireFifo(TLFIFOFixer.allVolatile) // TileLink pipelining MMIO requests val clock_en_reg = Reg(Bool()) io.cpu.clock_enabled := clock_en_reg val gated_clock = if (!cacheParams.clockGate) clock else ClockGate(clock, clock_en_reg, "dcache_clock_gate") class DCacheModuleImpl { // entering gated-clock domain val tlb = Module(new TLB(false, log2Ceil(coreDataBytes), TLBConfig(nTLBSets, nTLBWays, cacheParams.nTLBBasePageSectors, cacheParams.nTLBSuperpages))) val pma_checker = Module(new TLB(false, log2Ceil(coreDataBytes), TLBConfig(nTLBSets, nTLBWays, cacheParams.nTLBBasePageSectors, cacheParams.nTLBSuperpages)) with InlineInstance) // tags val replacer = ReplacementPolicy.fromString(cacheParams.replacementPolicy, nWays) /** Metadata Arbiter: * 0: Tag update on reset * 1: Tag update on ECC error * 2: Tag update on hit * 3: Tag update on refill * 4: Tag update on release * 5: Tag update on flush * 6: Tag update on probe * 7: Tag update on CPU request / val metaArb = Module(new Arbiter(new DCacheMetadataReq, 8) with InlineInstance) val tag_array = DescribedSRAM( name = s"${tileParams.baseName}_dcache_tag_array", desc = "DCache Tag Array", size = nSets, data = Vec(nWays, chiselTypeOf(metaArb.io.out.bits.data)) ) // data val data = Module(new DCacheDataArray) /* Data Arbiter * 0: data from pending store buffer * 1: data from TL-D refill * 2: release to TL-A * 3: hit path to CPU / val dataArb = Module(new Arbiter(new DCacheDataReq, 4) with InlineInstance) dataArb.io.in.tail.foreach(_.bits.wdata := dataArb.io.in.head.bits.wdata) // tie off write ports by default data.io.req.bits <> dataArb.io.out.bits data.io.req.valid := dataArb.io.out.valid dataArb.io.out.ready := true.B metaArb.io.out.ready := clock_en_reg val tl_out_a = Wire(chiselTypeOf(tl_out.a)) tl_out.a <> { val a_queue_depth = outer.crossing match { case RationalCrossing(_) => // TODO make this depend on the actual ratio? if (cacheParams.separateUncachedResp) (maxUncachedInFlight + 1) / 2 else 2 min maxUncachedInFlight-1 case SynchronousCrossing(BufferParams.none) => 1 // Need some buffering to guarantee livelock freedom case SynchronousCrossing(_) => 0 // Adequate buffering within the crossing case _: AsynchronousCrossing => 0 // Adequate buffering within the crossing case _: CreditedCrossing => 0 // Adequate buffering within the crossing } Queue(tl_out_a, a_queue_depth, flow = true) } val (tl_out_c, release_queue_empty) = if (cacheParams.acquireBeforeRelease) { val q = Module(new Queue(chiselTypeOf(tl_out.c.bits), cacheDataBeats, flow = true)) tl_out.c <> q.io.deq (q.io.enq, q.io.count === 0.U) } else { (tl_out.c, true.B) } val s1_valid = RegNext(io.cpu.req.fire, false.B) val s1_probe = RegNext(tl_out.b.fire, false.B) val probe_bits = RegEnable(tl_out.b.bits, tl_out.b.fire) // TODO has data now :( val s1_nack = WireDefault(false.B) val s1_valid_masked = s1_valid && !io.cpu.s1_kill val s1_valid_not_nacked = s1_valid && !s1_nack val s1_tlb_req_valid = RegNext(io.tlb_port.req.fire, false.B) val s2_tlb_req_valid = RegNext(s1_tlb_req_valid, false.B) val s0_clk_en = metaArb.io.out.valid && !metaArb.io.out.bits.write val s0_req = WireInit(io.cpu.req.bits) s0_req.addr := Cat(metaArb.io.out.bits.addr >> blockOffBits, io.cpu.req.bits.addr(blockOffBits-1,0)) s0_req.idx.foreach(_ := Cat(metaArb.io.out.bits.idx, s0_req.addr(blockOffBits-1, 0))) when (!metaArb.io.in(7).ready) { s0_req.phys := true.B } val s1_req = RegEnable(s0_req, s0_clk_en) val s1_vaddr = Cat(s1_req.idx.getOrElse(s1_req.addr) >> tagLSB, s1_req.addr(tagLSB-1, 0)) val s0_tlb_req = WireInit(io.tlb_port.req.bits) when (!io.tlb_port.req.fire) { s0_tlb_req.passthrough := s0_req.phys s0_tlb_req.vaddr := s0_req.addr s0_tlb_req.size := s0_req.size s0_tlb_req.cmd := s0_req.cmd s0_tlb_req.prv := s0_req.dprv s0_tlb_req.v := s0_req.dv } val s1_tlb_req = RegEnable(s0_tlb_req, s0_clk_en \|\| io.tlb_port.req.valid) val s1_read = isRead(s1_req.cmd) val s1_write = isWrite(s1_req.cmd) val s1_readwrite = s1_read \|\| s1_write val s1_sfence = s1_req.cmd === M_SFENCE \|\| s1_req.cmd === M_HFENCEV \|\| s1_req.cmd === M_HFENCEG val s1_flush_line = s1_req.cmd === M_FLUSH_ALL && s1_req.size(0) val s1_flush_valid = Reg(Bool()) val s1_waw_hazard = Wire(Bool()) val s_ready :: s_voluntary_writeback :: s_probe_rep_dirty :: s_probe_rep_clean :: s_probe_retry :: s_probe_rep_miss :: s_voluntary_write_meta :: s_probe_write_meta :: s_dummy :: s_voluntary_release :: Nil = Enum(10) val supports_flush = outer.flushOnFenceI \|\| coreParams.haveCFlush val flushed = RegInit(true.B) val flushing = RegInit(false.B) val flushing_req = Reg(chiselTypeOf(s1_req)) val cached_grant_wait = RegInit(false.B) val resetting = RegInit(false.B) val flushCounter = RegInit((nSets (nWays-1)).U(log2Ceil(nSets * nWays).W)) val release_ack_wait = RegInit(false.B) val release_ack_addr = Reg(UInt(paddrBits.W)) val release_state = RegInit(s_ready) val refill_way = Reg(UInt()) val any_pstore_valid = Wire(Bool()) val inWriteback = release_state.isOneOf(s_voluntary_writeback, s_probe_rep_dirty) val releaseWay = Wire(UInt()) io.cpu.req.ready := (release_state === s_ready) && !cached_grant_wait && !s1_nack // I/O MSHRs val uncachedInFlight = RegInit(VecInit(Seq.fill(maxUncachedInFlight)(false.B))) val uncachedReqs = Reg(Vec(maxUncachedInFlight, new HellaCacheReq)) val uncachedResp = WireInit(new HellaCacheReq, DontCare) // hit initiation path val s0_read = isRead(io.cpu.req.bits.cmd) dataArb.io.in(3).valid := io.cpu.req.valid && likelyNeedsRead(io.cpu.req.bits) dataArb.io.in(3).bits := dataArb.io.in(1).bits dataArb.io.in(3).bits.write := false.B dataArb.io.in(3).bits.addr := Cat(io.cpu.req.bits.idx.getOrElse(io.cpu.req.bits.addr) >> tagLSB, io.cpu.req.bits.addr(tagLSB-1, 0)) dataArb.io.in(3).bits.wordMask := { val mask = (subWordBytes.log2 until rowOffBits).foldLeft(1.U) { case (in, i) => val upper_mask = Mux((i >= wordBytes.log2).B \|\| io.cpu.req.bits.size <= i.U, 0.U, ((BigInt(1) << (1 << (i - subWordBytes.log2)))-1).U) val upper = Mux(io.cpu.req.bits.addr(i), in, 0.U) \| upper_mask val lower = Mux(io.cpu.req.bits.addr(i), 0.U, in) upper ## lower } Fill(subWordBytes / eccBytes, mask) } dataArb.io.in(3).bits.eccMask := ~0.U((wordBytes / eccBytes).W) dataArb.io.in(3).bits.way_en := ~0.U(nWays.W) when (!dataArb.io.in(3).ready && s0_read) { io.cpu.req.ready := false.B } val s1_did_read = RegEnable(dataArb.io.in(3).ready && (io.cpu.req.valid && needsRead(io.cpu.req.bits)), s0_clk_en) val s1_read_mask = RegEnable(dataArb.io.in(3).bits.wordMask, s0_clk_en) metaArb.io.in(7).valid := io.cpu.req.valid metaArb.io.in(7).bits.write := false.B metaArb.io.in(7).bits.idx := dataArb.io.in(3).bits.addr(idxMSB, idxLSB) metaArb.io.in(7).bits.addr := io.cpu.req.bits.addr metaArb.io.in(7).bits.way_en := metaArb.io.in(4).bits.way_en metaArb.io.in(7).bits.data := metaArb.io.in(4).bits.data when (!metaArb.io.in(7).ready) { io.cpu.req.ready := false.B } // address translation val s1_cmd_uses_tlb = s1_readwrite \|\| s1_flush_line \|\| s1_req.cmd === M_WOK io.ptw <> tlb.io.ptw tlb.io.kill := io.cpu.s2_kill \|\| s2_tlb_req_valid && io.tlb_port.s2_kill tlb.io.req.valid := s1_tlb_req_valid \|\| s1_valid && !io.cpu.s1_kill && s1_cmd_uses_tlb tlb.io.req.bits := s1_tlb_req when (!tlb.io.req.ready && !tlb.io.ptw.resp.valid && !io.cpu.req.bits.phys) { io.cpu.req.ready := false.B } when (!s1_tlb_req_valid && s1_valid && s1_cmd_uses_tlb && tlb.io.resp.miss) { s1_nack := true.B } tlb.io.sfence.valid := s1_valid && !io.cpu.s1_kill && s1_sfence tlb.io.sfence.bits.rs1 := s1_req.size(0) tlb.io.sfence.bits.rs2 := s1_req.size(1) tlb.io.sfence.bits.asid := io.cpu.s1_data.data tlb.io.sfence.bits.addr := s1_req.addr tlb.io.sfence.bits.hv := s1_req.cmd === M_HFENCEV tlb.io.sfence.bits.hg := s1_req.cmd === M_HFENCEG io.tlb_port.req.ready := clock_en_reg io.tlb_port.s1_resp := tlb.io.resp when (s1_tlb_req_valid && s1_valid && !(s1_req.phys && s1_req.no_xcpt)) { s1_nack := true.B } pma_checker.io <> DontCare pma_checker.io.req.bits.passthrough := true.B pma_checker.io.req.bits.vaddr := s1_req.addr pma_checker.io.req.bits.size := s1_req.size pma_checker.io.req.bits.cmd := s1_req.cmd pma_checker.io.req.bits.prv := s1_req.dprv pma_checker.io.req.bits.v := s1_req.dv val s1_paddr = Cat(Mux(s1_tlb_req_valid, s1_req.addr(paddrBits-1, pgIdxBits), tlb.io.resp.paddr >> pgIdxBits), s1_req.addr(pgIdxBits-1, 0)) val s1_victim_way = Wire(UInt()) val (s1_hit_way, s1_hit_state, s1_meta) = if (usingDataScratchpad) { val baseAddr = p(LookupByHartId)(_.dcache.flatMap(_.scratch.map(_.U)), io_hartid.get) \| io_mmio_address_prefix.get val inScratchpad = s1_paddr >= baseAddr && s1_paddr < baseAddr + (nSets * cacheBlockBytes).U val hitState = Mux(inScratchpad, ClientMetadata.maximum, ClientMetadata.onReset) val dummyMeta = L1Metadata(0.U, ClientMetadata.onReset) (inScratchpad, hitState, Seq(tECC.encode(dummyMeta.asUInt))) } else { val metaReq = metaArb.io.out val metaIdx = metaReq.bits.idx when (metaReq.valid && metaReq.bits.write) { val wmask = if (nWays == 1) Seq(true.B) else metaReq.bits.way_en.asBools tag_array.write(metaIdx, VecInit(Seq.fill(nWays)(metaReq.bits.data)), wmask) } val s1_meta = tag_array.read(metaIdx, metaReq.valid && !metaReq.bits.write) val s1_meta_uncorrected = s1_meta.map(tECC.decode(_).uncorrected.asTypeOf(new L1Metadata)) val s1_tag = s1_paddr >> tagLSB val s1_meta_hit_way = s1_meta_uncorrected.map(r => r.coh.isValid() && r.tag === s1_tag).asUInt val s1_meta_hit_state = ( s1_meta_uncorrected.map(r => Mux(r.tag === s1_tag && !s1_flush_valid, r.coh.asUInt, 0.U)) .reduce (_\|_)).asTypeOf(chiselTypeOf(ClientMetadata.onReset)) (s1_meta_hit_way, s1_meta_hit_state, s1_meta) } val s1_data_way = WireDefault(if (nWays == 1) 1.U else Mux(inWriteback, releaseWay, s1_hit_way)) val tl_d_data_encoded = Wire(chiselTypeOf(encodeData(tl_out.d.bits.data, false.B))) val s1_all_data_ways = VecInit(data.io.resp ++ (!cacheParams.separateUncachedResp).option(tl_d_data_encoded)) val s1_mask_xwr = new StoreGen(s1_req.size, s1_req.addr, 0.U, wordBytes).mask val s1_mask = Mux(s1_req.cmd === M_PWR, io.cpu.s1_data.mask, s1_mask_xwr) // for partial writes, s1_data.mask must be a subset of s1_mask_xwr assert(!(s1_valid_masked && s1_req.cmd === M_PWR) \|\| (s1_mask_xwr \| ~io.cpu.s1_data.mask).andR) val s2_valid = RegNext(s1_valid_masked && !s1_sfence, init=false.B) val s2_valid_no_xcpt = s2_valid && !io.cpu.s2_xcpt.asUInt.orR val s2_probe = RegNext(s1_probe, init=false.B) val releaseInFlight = s1_probe \|\| s2_probe \|\| release_state =/= s_ready val s2_not_nacked_in_s1 = RegNext(!s1_nack) val s2_valid_not_nacked_in_s1 = s2_valid && s2_not_nacked_in_s1 val s2_valid_masked = s2_valid_no_xcpt && s2_not_nacked_in_s1 val s2_valid_not_killed = s2_valid_masked && !io.cpu.s2_kill val s2_req = Reg(chiselTypeOf(io.cpu.req.bits)) val s2_cmd_flush_all = s2_req.cmd === M_FLUSH_ALL && !s2_req.size(0) val s2_cmd_flush_line = s2_req.cmd === M_FLUSH_ALL && s2_req.size(0) val s2_tlb_xcpt = Reg(chiselTypeOf(tlb.io.resp)) val s2_pma = Reg(chiselTypeOf(tlb.io.resp)) val s2_uncached_resp_addr = Reg(chiselTypeOf(s2_req.addr)) // should be DCE'd in synthesis when (s1_valid_not_nacked \|\| s1_flush_valid) { s2_req := s1_req s2_req.addr := s1_paddr s2_tlb_xcpt := tlb.io.resp s2_pma := Mux(s1_tlb_req_valid, pma_checker.io.resp, tlb.io.resp) } val s2_vaddr = Cat(RegEnable(s1_vaddr, s1_valid_not_nacked \|\| s1_flush_valid) >> tagLSB, s2_req.addr(tagLSB-1, 0)) val s2_read = isRead(s2_req.cmd) val s2_write = isWrite(s2_req.cmd) val s2_readwrite = s2_read \|\| s2_write val s2_flush_valid_pre_tag_ecc = RegNext(s1_flush_valid) val s1_meta_decoded = s1_meta.map(tECC.decode(_)) val s1_meta_clk_en = s1_valid_not_nacked \|\| s1_flush_valid \|\| s1_probe val s2_meta_correctable_errors = s1_meta_decoded.map(m => RegEnable(m.correctable, s1_meta_clk_en)).asUInt val s2_meta_uncorrectable_errors = s1_meta_decoded.map(m => RegEnable(m.uncorrectable, s1_meta_clk_en)).asUInt val s2_meta_error_uncorrectable = s2_meta_uncorrectable_errors.orR val s2_meta_corrected = s1_meta_decoded.map(m => RegEnable(m.corrected, s1_meta_clk_en).asTypeOf(new L1Metadata)) val s2_meta_error = (s2_meta_uncorrectable_errors \| s2_meta_correctable_errors).orR val s2_flush_valid = s2_flush_valid_pre_tag_ecc && !s2_meta_error val s2_data = { val wordsPerRow = rowBits / subWordBits val en = s1_valid \|\| inWriteback \|\| io.cpu.replay_next val word_en = Mux(inWriteback, Fill(wordsPerRow, 1.U), Mux(s1_did_read, s1_read_mask, 0.U)) val s1_way_words = s1_all_data_ways.map(_.grouped(dECC.width(eccBits) * (subWordBits / eccBits))) if (cacheParams.pipelineWayMux) { val s1_word_en = Mux(io.cpu.replay_next, 0.U, word_en) (for (i <- 0 until wordsPerRow) yield { val s2_way_en = RegEnable(Mux(s1_word_en(i), s1_data_way, 0.U), en) val s2_way_words = (0 until nWays).map(j => RegEnable(s1_way_words(j)(i), en && word_en(i))) (0 until nWays).map(j => Mux(s2_way_en(j), s2_way_words(j), 0.U)).reduce(_\|_) }).asUInt } else { val s1_word_en = Mux(!io.cpu.replay_next, word_en, UIntToOH(uncachedResp.addr.extract(log2Up(rowBits/8)-1, log2Up(wordBytes)), wordsPerRow)) (for (i <- 0 until wordsPerRow) yield { RegEnable(Mux1H(Mux(s1_word_en(i), s1_data_way, 0.U), s1_way_words.map(_(i))), en) }).asUInt } } val s2_probe_way = RegEnable(s1_hit_way, s1_probe) val s2_probe_state = RegEnable(s1_hit_state, s1_probe) val s2_hit_way = RegEnable(s1_hit_way, s1_valid_not_nacked) val s2_hit_state = RegEnable(s1_hit_state, s1_valid_not_nacked \|\| s1_flush_valid) val s2_waw_hazard = RegEnable(s1_waw_hazard, s1_valid_not_nacked) val s2_store_merge = Wire(Bool()) val s2_hit_valid = s2_hit_state.isValid() val (s2_hit, s2_grow_param, s2_new_hit_state) = s2_hit_state.onAccess(s2_req.cmd) val s2_data_decoded = decodeData(s2_data) val s2_word_idx = s2_req.addr.extract(log2Up(rowBits/8)-1, log2Up(wordBytes)) val s2_data_error = s2_data_decoded.map(_.error).orR val s2_data_error_uncorrectable = s2_data_decoded.map(_.uncorrectable).orR val s2_data_corrected = (s2_data_decoded.map(_.corrected): Seq[UInt]).asUInt val s2_data_uncorrected = (s2_data_decoded.map(_.uncorrected): Seq[UInt]).asUInt val s2_valid_hit_maybe_flush_pre_data_ecc_and_waw = s2_valid_masked && !s2_meta_error && s2_hit val s2_no_alloc_hazard = if (!usingVM \|\| pgIdxBits >= untagBits) false.B else { // make sure that any in-flight non-allocating accesses are ordered before // any allocating accesses. this can only happen if aliasing is possible. val any_no_alloc_in_flight = Reg(Bool()) when (!uncachedInFlight.asUInt.orR) { any_no_alloc_in_flight := false.B } when (s2_valid && s2_req.no_alloc) { any_no_alloc_in_flight := true.B } val s1_need_check = any_no_alloc_in_flight \|\| s2_valid && s2_req.no_alloc val concerns = (uncachedInFlight zip uncachedReqs) :+ (s2_valid && s2_req.no_alloc, s2_req) val s1_uncached_hits = concerns.map { c => val concern_wmask = new StoreGen(c._2.size, c._2.addr, 0.U, wordBytes).mask val addr_match = (c._2.addr ^ s1_paddr)(pgIdxBits+pgLevelBits-1, wordBytes.log2) === 0.U val mask_match = (concern_wmask & s1_mask_xwr).orR \|\| c._2.cmd === M_PWR \|\| s1_req.cmd === M_PWR val cmd_match = isWrite(c._2.cmd) \|\| isWrite(s1_req.cmd) c._1 && s1_need_check && cmd_match && addr_match && mask_match } val s2_uncached_hits = RegEnable(s1_uncached_hits.asUInt, s1_valid_not_nacked) s2_uncached_hits.orR } val s2_valid_hit_pre_data_ecc_and_waw = s2_valid_hit_maybe_flush_pre_data_ecc_and_waw && s2_readwrite && !s2_no_alloc_hazard val s2_valid_flush_line = s2_valid_hit_maybe_flush_pre_data_ecc_and_waw && s2_cmd_flush_line val s2_valid_hit_pre_data_ecc = s2_valid_hit_pre_data_ecc_and_waw && (!s2_waw_hazard \|\| s2_store_merge) val s2_valid_data_error = s2_valid_hit_pre_data_ecc_and_waw && s2_data_error val s2_valid_hit = s2_valid_hit_pre_data_ecc && !s2_data_error val s2_valid_miss = s2_valid_masked && s2_readwrite && !s2_meta_error && !s2_hit val s2_uncached = !s2_pma.cacheable \|\| s2_req.no_alloc && !s2_pma.must_alloc && !s2_hit_valid val s2_valid_cached_miss = s2_valid_miss && !s2_uncached && !uncachedInFlight.asUInt.orR dontTouch(s2_valid_cached_miss) val s2_want_victimize = (!usingDataScratchpad).B && (s2_valid_cached_miss \|\| s2_valid_flush_line \|\| s2_valid_data_error \|\| s2_flush_valid) val s2_cannot_victimize = !s2_flush_valid && io.cpu.s2_kill val s2_victimize = s2_want_victimize && !s2_cannot_victimize val s2_valid_uncached_pending = s2_valid_miss && s2_uncached && !uncachedInFlight.asUInt.andR val s2_victim_way = UIntToOH(RegEnable(s1_victim_way, s1_valid_not_nacked \|\| s1_flush_valid)) val s2_victim_or_hit_way = Mux(s2_hit_valid, s2_hit_way, s2_victim_way) val s2_victim_tag = Mux(s2_valid_data_error \|\| s2_valid_flush_line, s2_req.addr(paddrBits-1, tagLSB), Mux1H(s2_victim_way, s2_meta_corrected).tag) val s2_victim_state = Mux(s2_hit_valid, s2_hit_state, Mux1H(s2_victim_way, s2_meta_corrected).coh) val (s2_prb_ack_data, s2_report_param, probeNewCoh)= s2_probe_state.onProbe(probe_bits.param) val (s2_victim_dirty, s2_shrink_param, voluntaryNewCoh) = s2_victim_state.onCacheControl(M_FLUSH) dontTouch(s2_victim_dirty) val s2_update_meta = s2_hit_state =/= s2_new_hit_state val s2_dont_nack_uncached = s2_valid_uncached_pending && tl_out_a.ready val s2_dont_nack_misc = s2_valid_masked && !s2_meta_error && (supports_flush.B && s2_cmd_flush_all && flushed && !flushing \|\| supports_flush.B && s2_cmd_flush_line && !s2_hit \|\| s2_req.cmd === M_WOK) io.cpu.s2_nack := s2_valid_no_xcpt && !s2_dont_nack_uncached && !s2_dont_nack_misc && !s2_valid_hit when (io.cpu.s2_nack \|\| (s2_valid_hit_pre_data_ecc_and_waw && s2_update_meta)) { s1_nack := true.B } // tag updates on ECC errors val s2_first_meta_corrected = PriorityMux(s2_meta_correctable_errors, s2_meta_corrected) metaArb.io.in(1).valid := s2_meta_error && (s2_valid_masked \|\| s2_flush_valid_pre_tag_ecc \|\| s2_probe) metaArb.io.in(1).bits.write := true.B metaArb.io.in(1).bits.way_en := s2_meta_uncorrectable_errors \| Mux(s2_meta_error_uncorrectable, 0.U, PriorityEncoderOH(s2_meta_correctable_errors)) metaArb.io.in(1).bits.idx := Mux(s2_probe, probeIdx(probe_bits), s2_vaddr(idxMSB, idxLSB)) metaArb.io.in(1).bits.addr := Cat(io.cpu.req.bits.addr >> untagBits, metaArb.io.in(1).bits.idx << blockOffBits) metaArb.io.in(1).bits.data := tECC.encode { val new_meta = WireDefault(s2_first_meta_corrected) when (s2_meta_error_uncorrectable) { new_meta.coh := ClientMetadata.onReset } new_meta.asUInt } // tag updates on hit metaArb.io.in(2).valid := s2_valid_hit_pre_data_ecc_and_waw && s2_update_meta metaArb.io.in(2).bits.write := !io.cpu.s2_kill metaArb.io.in(2).bits.way_en := s2_victim_or_hit_way metaArb.io.in(2).bits.idx := s2_vaddr(idxMSB, idxLSB) metaArb.io.in(2).bits.addr := Cat(io.cpu.req.bits.addr >> untagBits, s2_vaddr(idxMSB, 0)) metaArb.io.in(2).bits.data := tECC.encode(L1Metadata(s2_req.addr >> tagLSB, s2_new_hit_state).asUInt) // load reservations and TL error reporting val s2_lr = (usingAtomics && !usingDataScratchpad).B && s2_req.cmd === M_XLR val s2_sc = (usingAtomics && !usingDataScratchpad).B && s2_req.cmd === M_XSC val lrscCount = RegInit(0.U) val lrscValid = lrscCount > lrscBackoff.U val lrscBackingOff = lrscCount > 0.U && !lrscValid val lrscAddr = Reg(UInt()) val lrscAddrMatch = lrscAddr === (s2_req.addr >> blockOffBits) val s2_sc_fail = s2_sc && !(lrscValid && lrscAddrMatch) when ((s2_valid_hit && s2_lr && !cached_grant_wait \|\| s2_valid_cached_miss) && !io.cpu.s2_kill) { lrscCount := Mux(s2_hit, (lrscCycles - 1).U, 0.U) lrscAddr := s2_req.addr >> blockOffBits } when (lrscCount > 0.U) { lrscCount := lrscCount - 1.U } when (s2_valid_not_killed && lrscValid) { lrscCount := lrscBackoff.U } when (s1_probe) { lrscCount := 0.U } // don't perform data correction if it might clobber a recent store val s2_correct = s2_data_error && !any_pstore_valid && !RegNext(any_pstore_valid \|\| s2_valid) && usingDataScratchpad.B // pending store buffer val s2_valid_correct = s2_valid_hit_pre_data_ecc_and_waw && s2_correct && !io.cpu.s2_kill def s2_store_valid_pre_kill = s2_valid_hit && s2_write && !s2_sc_fail def s2_store_valid = s2_store_valid_pre_kill && !io.cpu.s2_kill val pstore1_cmd = RegEnable(s1_req.cmd, s1_valid_not_nacked && s1_write) val pstore1_addr = RegEnable(s1_vaddr, s1_valid_not_nacked && s1_write) val pstore1_data = RegEnable(io.cpu.s1_data.data, s1_valid_not_nacked && s1_write) val pstore1_way = RegEnable(s1_hit_way, s1_valid_not_nacked && s1_write) val pstore1_mask = RegEnable(s1_mask, s1_valid_not_nacked && s1_write) val pstore1_storegen_data = WireDefault(pstore1_data) val pstore1_rmw = usingRMW.B && RegEnable(needsRead(s1_req), s1_valid_not_nacked && s1_write) val pstore1_merge_likely = s2_valid_not_nacked_in_s1 && s2_write && s2_store_merge val pstore1_merge = s2_store_valid && s2_store_merge val pstore2_valid = RegInit(false.B) val pstore_drain_opportunistic = !(io.cpu.req.valid && likelyNeedsRead(io.cpu.req.bits)) && !(s1_valid && s1_waw_hazard) val pstore_drain_on_miss = releaseInFlight \|\| RegNext(io.cpu.s2_nack) val pstore1_held = RegInit(false.B) val pstore1_valid_likely = s2_valid && s2_write \|\| pstore1_held def pstore1_valid_not_rmw(s2_kill: Bool) = s2_valid_hit_pre_data_ecc && s2_write && !s2_kill \|\| pstore1_held val pstore1_valid = s2_store_valid \|\| pstore1_held any_pstore_valid := pstore1_held \|\| pstore2_valid val pstore_drain_structural = pstore1_valid_likely && pstore2_valid && ((s1_valid && s1_write) \|\| pstore1_rmw) assert(pstore1_rmw \|\| pstore1_valid_not_rmw(io.cpu.s2_kill) === pstore1_valid) ccover(pstore_drain_structural, "STORE_STRUCTURAL_HAZARD", "D$ read-modify-write structural hazard") ccover(pstore1_valid && pstore_drain_on_miss, "STORE_DRAIN_ON_MISS", "D$ store buffer drain on miss") ccover(s1_valid_not_nacked && s1_waw_hazard, "WAW_HAZARD", "D$ write-after-write hazard") def should_pstore_drain(truly: Bool) = { val s2_kill = truly && io.cpu.s2_kill !pstore1_merge_likely && (usingRMW.B && pstore_drain_structural \|\| (((pstore1_valid_not_rmw(s2_kill) && !pstore1_rmw) \|\| pstore2_valid) && (pstore_drain_opportunistic \|\| pstore_drain_on_miss))) } val pstore_drain = should_pstore_drain(true.B) pstore1_held := (s2_store_valid && !s2_store_merge \|\| pstore1_held) && pstore2_valid && !pstore_drain val advance_pstore1 = (pstore1_valid \|\| s2_valid_correct) && (pstore2_valid === pstore_drain) pstore2_valid := pstore2_valid && !pstore_drain \|\| advance_pstore1 val pstore2_addr = RegEnable(Mux(s2_correct, s2_vaddr, pstore1_addr), advance_pstore1) val pstore2_way = RegEnable(Mux(s2_correct, s2_hit_way, pstore1_way), advance_pstore1) val pstore2_storegen_data = { for (i <- 0 until wordBytes) yield RegEnable(pstore1_storegen_data(8(i+1)-1, 8i), advance_pstore1 \|\| pstore1_merge && pstore1_mask(i)) }.asUInt val pstore2_storegen_mask = { val mask = Reg(UInt(wordBytes.W)) when (advance_pstore1 \|\| pstore1_merge) { val mergedMask = pstore1_mask \| Mux(pstore1_merge, mask, 0.U) mask := ~Mux(s2_correct, 0.U, ~mergedMask) } mask } s2_store_merge := (if (eccBytes == 1) false.B else { ccover(pstore1_merge, "STORE_MERGED", "D$ store merged") // only merge stores to ECC granules that are already stored-to, to avoid // WAW hazards val wordMatch = (eccMask(pstore2_storegen_mask) \| ~eccMask(pstore1_mask)).andR val idxMatch = s2_vaddr(untagBits-1, log2Ceil(wordBytes)) === pstore2_addr(untagBits-1, log2Ceil(wordBytes)) val tagMatch = (s2_hit_way & pstore2_way).orR pstore2_valid && wordMatch && idxMatch && tagMatch }) dataArb.io.in(0).valid := should_pstore_drain(false.B) dataArb.io.in(0).bits.write := pstore_drain dataArb.io.in(0).bits.addr := Mux(pstore2_valid, pstore2_addr, pstore1_addr) dataArb.io.in(0).bits.way_en := Mux(pstore2_valid, pstore2_way, pstore1_way) dataArb.io.in(0).bits.wdata := encodeData(Fill(rowWords, Mux(pstore2_valid, pstore2_storegen_data, pstore1_data)), false.B) dataArb.io.in(0).bits.wordMask := { val eccMask = dataArb.io.in(0).bits.eccMask.asBools.grouped(subWordBytes/eccBytes).map(_.orR).toSeq.asUInt val wordMask = UIntToOH(Mux(pstore2_valid, pstore2_addr, pstore1_addr).extract(rowOffBits-1, wordBytes.log2)) FillInterleaved(wordBytes/subWordBytes, wordMask) & Fill(rowBytes/wordBytes, eccMask) } dataArb.io.in(0).bits.eccMask := eccMask(Mux(pstore2_valid, pstore2_storegen_mask, pstore1_mask)) // store->load RAW hazard detection def s1Depends(addr: UInt, mask: UInt) = addr(idxMSB, wordOffBits) === s1_vaddr(idxMSB, wordOffBits) && Mux(s1_write, (eccByteMask(mask) & eccByteMask(s1_mask_xwr)).orR, (mask & s1_mask_xwr).orR) val s1_hazard = (pstore1_valid_likely && s1Depends(pstore1_addr, pstore1_mask)) \|\| (pstore2_valid && s1Depends(pstore2_addr, pstore2_storegen_mask)) val s1_raw_hazard = s1_read && s1_hazard s1_waw_hazard := (if (eccBytes == 1) false.B else { ccover(s1_valid_not_nacked && s1_waw_hazard, "WAW_HAZARD", "D$ write-after-write hazard") s1_write && (s1_hazard \|\| needsRead(s1_req) && !s1_did_read) }) when (s1_valid && s1_raw_hazard) { s1_nack := true.B } // performance hints to processor io.cpu.s2_nack_cause_raw := RegNext(s1_raw_hazard) \|\| !(!s2_waw_hazard \|\| s2_store_merge) // Prepare a TileLink request message that initiates a transaction val a_source = PriorityEncoder(~uncachedInFlight.asUInt << mmioOffset) // skip the MSHR val acquire_address = (s2_req.addr >> idxLSB) << idxLSB val access_address = s2_req.addr val a_size = s2_req.size val a_data = Fill(beatWords, pstore1_data) val a_mask = pstore1_mask << (access_address.extract(beatBytes.log2-1, wordBytes.log2) << 3) val get = edge.Get(a_source, access_address, a_size)._2 val put = edge.Put(a_source, access_address, a_size, a_data)._2 val putpartial = edge.Put(a_source, access_address, a_size, a_data, a_mask)._2 val atomics = if (edge.manager.anySupportLogical) { MuxLookup(s2_req.cmd, WireDefault(0.U.asTypeOf(new TLBundleA(edge.bundle))))(Array( M_XA_SWAP -> edge.Logical(a_source, access_address, a_size, a_data, TLAtomics.SWAP)._2, M_XA_XOR -> edge.Logical(a_source, access_address, a_size, a_data, TLAtomics.XOR) ._2, M_XA_OR -> edge.Logical(a_source, access_address, a_size, a_data, TLAtomics.OR) ._2, M_XA_AND -> edge.Logical(a_source, access_address, a_size, a_data, TLAtomics.AND) ._2, M_XA_ADD -> edge.Arithmetic(a_source, access_address, a_size, a_data, TLAtomics.ADD)._2, M_XA_MIN -> edge.Arithmetic(a_source, access_address, a_size, a_data, TLAtomics.MIN)._2, M_XA_MAX -> edge.Arithmetic(a_source, access_address, a_size, a_data, TLAtomics.MAX)._2, M_XA_MINU -> edge.Arithmetic(a_source, access_address, a_size, a_data, TLAtomics.MINU)._2, M_XA_MAXU -> edge.Arithmetic(a_source, access_address, a_size, a_data, TLAtomics.MAXU)._2)) } else { // If no managers support atomics, assert fail if processor asks for them assert (!(tl_out_a.valid && s2_read && s2_write && s2_uncached)) WireDefault(new TLBundleA(edge.bundle), DontCare) } tl_out_a.valid := !io.cpu.s2_kill && (s2_valid_uncached_pending \|\| (s2_valid_cached_miss && !(release_ack_wait && (s2_req.addr ^ release_ack_addr)(((pgIdxBits + pgLevelBits) min paddrBits) - 1, idxLSB) === 0.U) && (cacheParams.acquireBeforeRelease.B && !release_ack_wait && release_queue_empty \|\| !s2_victim_dirty))) tl_out_a.bits := Mux(!s2_uncached, acquire(s2_vaddr, s2_req.addr, s2_grow_param), Mux(!s2_write, get, Mux(s2_req.cmd === M_PWR, putpartial, Mux(!s2_read, put, atomics)))) // Drive APROT Bits tl_out_a.bits.user.lift(AMBAProt).foreach { x => val user_bit_cacheable = s2_pma.cacheable x.privileged := s2_req.dprv === PRV.M.U \|\| user_bit_cacheable // if the address is cacheable, enable outer caches x.bufferable := user_bit_cacheable x.modifiable := user_bit_cacheable x.readalloc := user_bit_cacheable x.writealloc := user_bit_cacheable // Following are always tied off x.fetch := false.B x.secure := true.B } // Set pending bits for outstanding TileLink transaction val a_sel = UIntToOH(a_source, maxUncachedInFlight+mmioOffset) >> mmioOffset when (tl_out_a.fire) { when (s2_uncached) { (a_sel.asBools zip (uncachedInFlight zip uncachedReqs)) foreach { case (s, (f, r)) => when (s) { f := true.B r := s2_req r.cmd := Mux(s2_write, Mux(s2_req.cmd === M_PWR, M_PWR, M_XWR), M_XRD) } } }.otherwise { cached_grant_wait := true.B refill_way := s2_victim_or_hit_way } } // grant val (d_first, d_last, d_done, d_address_inc) = edge.addr_inc(tl_out.d) val (d_opc, grantIsUncached, grantIsUncachedData) = { val uncachedGrantOpcodesSansData = Seq(AccessAck, HintAck) val uncachedGrantOpcodesWithData = Seq(AccessAckData) val uncachedGrantOpcodes = uncachedGrantOpcodesWithData ++ uncachedGrantOpcodesSansData val whole_opc = tl_out.d.bits.opcode if (usingDataScratchpad) { assert(!tl_out.d.valid \|\| whole_opc.isOneOf(uncachedGrantOpcodes)) // the only valid TL-D messages are uncached, so we can do some pruning val opc = whole_opc(uncachedGrantOpcodes.map(_.getWidth).max - 1, 0) val data = DecodeLogic(opc, uncachedGrantOpcodesWithData, uncachedGrantOpcodesSansData) (opc, true.B, data) } else { (whole_opc, whole_opc.isOneOf(uncachedGrantOpcodes), whole_opc.isOneOf(uncachedGrantOpcodesWithData)) } } tl_d_data_encoded := encodeData(tl_out.d.bits.data, tl_out.d.bits.corrupt && !io.ptw.customCSRs.suppressCorruptOnGrantData && !grantIsUncached) val grantIsCached = d_opc.isOneOf(Grant, GrantData) val grantIsVoluntary = d_opc === ReleaseAck // Clears a different pending bit val grantIsRefill = d_opc === GrantData // Writes the data array val grantInProgress = RegInit(false.B) val blockProbeAfterGrantCount = RegInit(0.U) when (blockProbeAfterGrantCount > 0.U) { blockProbeAfterGrantCount := blockProbeAfterGrantCount - 1.U } val canAcceptCachedGrant = !release_state.isOneOf(s_voluntary_writeback, s_voluntary_write_meta, s_voluntary_release) tl_out.d.ready := Mux(grantIsCached, (!d_first \|\| tl_out.e.ready) && canAcceptCachedGrant, true.B) val uncachedRespIdxOH = UIntToOH(tl_out.d.bits.source, maxUncachedInFlight+mmioOffset) >> mmioOffset uncachedResp := Mux1H(uncachedRespIdxOH, uncachedReqs) when (tl_out.d.fire) { when (grantIsCached) { grantInProgress := true.B assert(cached_grant_wait, "A GrantData was unexpected by the dcache.") when(d_last) { cached_grant_wait := false.B grantInProgress := false.B blockProbeAfterGrantCount := (blockProbeAfterGrantCycles - 1).U replacer.miss } } .elsewhen (grantIsUncached) { (uncachedRespIdxOH.asBools zip uncachedInFlight) foreach { case (s, f) => when (s && d_last) { assert(f, "An AccessAck was unexpected by the dcache.") // TODO must handle Ack coming back on same cycle! f := false.B } } when (grantIsUncachedData) { if (!cacheParams.separateUncachedResp) { if (!cacheParams.pipelineWayMux) s1_data_way := 1.U << nWays s2_req.cmd := M_XRD s2_req.size := uncachedResp.size s2_req.signed := uncachedResp.signed s2_req.tag := uncachedResp.tag s2_req.addr := { require(rowOffBits >= beatOffBits) val dontCareBits = s1_paddr >> rowOffBits << rowOffBits dontCareBits \| uncachedResp.addr(beatOffBits-1, 0) } s2_uncached_resp_addr := uncachedResp.addr } } } .elsewhen (grantIsVoluntary) { assert(release_ack_wait, "A ReleaseAck was unexpected by the dcache.") // TODO should handle Ack coming back on same cycle! release_ack_wait := false.B } } // Finish TileLink transaction by issuing a GrantAck tl_out.e.valid := tl_out.d.valid && d_first && grantIsCached && canAcceptCachedGrant tl_out.e.bits := edge.GrantAck(tl_out.d.bits) assert(tl_out.e.fire === (tl_out.d.fire && d_first && grantIsCached)) // data refill // note this ready-valid signaling ignores E-channel backpressure, which // benignly means the data RAM might occasionally be redundantly written dataArb.io.in(1).valid := tl_out.d.valid && grantIsRefill && canAcceptCachedGrant when (grantIsRefill && !dataArb.io.in(1).ready) { tl_out.e.valid := false.B tl_out.d.ready := false.B } if (!usingDataScratchpad) { dataArb.io.in(1).bits.write := true.B dataArb.io.in(1).bits.addr := (s2_vaddr >> idxLSB) << idxLSB \| d_address_inc dataArb.io.in(1).bits.way_en := refill_way dataArb.io.in(1).bits.wdata := tl_d_data_encoded dataArb.io.in(1).bits.wordMask := ~0.U((rowBytes / subWordBytes).W) dataArb.io.in(1).bits.eccMask := ~0.U((wordBytes / eccBytes).W) } else { dataArb.io.in(1).bits := dataArb.io.in(0).bits } // tag updates on refill // ignore backpressure from metaArb, which can only be caused by tag ECC // errors on hit-under-miss. failing to write the new tag will leave the // line invalid, so we'll simply request the line again later. metaArb.io.in(3).valid := grantIsCached && d_done && !tl_out.d.bits.denied metaArb.io.in(3).bits.write := true.B metaArb.io.in(3).bits.way_en := refill_way metaArb.io.in(3).bits.idx := s2_vaddr(idxMSB, idxLSB) metaArb.io.in(3).bits.addr := Cat(io.cpu.req.bits.addr >> untagBits, s2_vaddr(idxMSB, 0)) metaArb.io.in(3).bits.data := tECC.encode(L1Metadata(s2_req.addr >> tagLSB, s2_hit_state.onGrant(s2_req.cmd, tl_out.d.bits.param)).asUInt) if (!cacheParams.separateUncachedResp) { // don't accept uncached grants if there's a structural hazard on s2_data... val blockUncachedGrant = Reg(Bool()) blockUncachedGrant := dataArb.io.out.valid when (grantIsUncachedData && (blockUncachedGrant \|\| s1_valid)) { tl_out.d.ready := false.B // ...but insert bubble to guarantee grant's eventual forward progress when (tl_out.d.valid) { io.cpu.req.ready := false.B dataArb.io.in(1).valid := true.B dataArb.io.in(1).bits.write := false.B blockUncachedGrant := !dataArb.io.in(1).ready } } } ccover(tl_out.d.valid && !tl_out.d.ready, "BLOCK_D", "D$ D-channel blocked") // Handle an incoming TileLink Probe message val block_probe_for_core_progress = blockProbeAfterGrantCount > 0.U \|\| lrscValid val block_probe_for_pending_release_ack = release_ack_wait && (tl_out.b.bits.address ^ release_ack_addr)(((pgIdxBits + pgLevelBits) min paddrBits) - 1, idxLSB) === 0.U val block_probe_for_ordering = releaseInFlight \|\| block_probe_for_pending_release_ack \|\| grantInProgress metaArb.io.in(6).valid := tl_out.b.valid && (!block_probe_for_core_progress \|\| lrscBackingOff) tl_out.b.ready := metaArb.io.in(6).ready && !(block_probe_for_core_progress \|\| block_probe_for_ordering \|\| s1_valid \|\| s2_valid) metaArb.io.in(6).bits.write := false.B metaArb.io.in(6).bits.idx := probeIdx(tl_out.b.bits) metaArb.io.in(6).bits.addr := Cat(io.cpu.req.bits.addr >> paddrBits, tl_out.b.bits.address) metaArb.io.in(6).bits.way_en := metaArb.io.in(4).bits.way_en metaArb.io.in(6).bits.data := metaArb.io.in(4).bits.data // replacement policy s1_victim_way := (if (replacer.perSet && nWays > 1) { val repl_array = Mem(nSets, UInt(replacer.nBits.W)) val s1_repl_idx = s1_req.addr(idxBits+blockOffBits-1, blockOffBits) val s2_repl_idx = s2_vaddr(idxBits+blockOffBits-1, blockOffBits) val s2_repl_state = Reg(UInt(replacer.nBits.W)) val s2_new_repl_state = replacer.get_next_state(s2_repl_state, OHToUInt(s2_hit_way)) val s2_repl_wen = s2_valid_masked && s2_hit_way.orR && s2_repl_state =/= s2_new_repl_state val s1_repl_state = Mux(s2_repl_wen && s2_repl_idx === s1_repl_idx, s2_new_repl_state, repl_array(s1_repl_idx)) when (s1_valid_not_nacked) { s2_repl_state := s1_repl_state } val waddr = Mux(resetting, flushCounter(idxBits-1, 0), s2_repl_idx) val wdata = Mux(resetting, 0.U, s2_new_repl_state) val wen = resetting \|\| s2_repl_wen when (wen) { repl_array(waddr) := wdata } replacer.get_replace_way(s1_repl_state) } else { replacer.way }) // release val (c_first, c_last, releaseDone, c_count) = edge.count(tl_out_c) val releaseRejected = Wire(Bool()) val s1_release_data_valid = RegNext(dataArb.io.in(2).fire) val s2_release_data_valid = RegNext(s1_release_data_valid && !releaseRejected) releaseRejected := s2_release_data_valid && !tl_out_c.fire val releaseDataBeat = Cat(0.U, c_count) + Mux(releaseRejected, 0.U, s1_release_data_valid + Cat(0.U, s2_release_data_valid)) val nackResponseMessage = edge.ProbeAck(b = probe_bits, reportPermissions = TLPermissions.NtoN) val cleanReleaseMessage = edge.ProbeAck(b = probe_bits, reportPermissions = s2_report_param) val dirtyReleaseMessage = edge.ProbeAck(b = probe_bits, reportPermissions = s2_report_param, data = 0.U) tl_out_c.valid := (s2_release_data_valid \|\| (!cacheParams.silentDrop.B && release_state === s_voluntary_release)) && !(c_first && release_ack_wait) tl_out_c.bits := nackResponseMessage val newCoh = WireDefault(probeNewCoh) releaseWay := s2_probe_way if (!usingDataScratchpad) { when (s2_victimize) { assert(s2_valid_flush_line \|\| s2_flush_valid \|\| io.cpu.s2_nack) val discard_line = s2_valid_flush_line && s2_req.size(1) \|\| s2_flush_valid && flushing_req.size(1) release_state := Mux(s2_victim_dirty && !discard_line, s_voluntary_writeback, Mux(!cacheParams.silentDrop.B && !release_ack_wait && release_queue_empty && s2_victim_state.isValid() && (s2_valid_flush_line \|\| s2_flush_valid \|\| s2_readwrite && !s2_hit_valid), s_voluntary_release, s_voluntary_write_meta)) probe_bits := addressToProbe(s2_vaddr, Cat(s2_victim_tag, s2_req.addr(tagLSB-1, idxLSB)) << idxLSB) } when (s2_probe) { val probeNack = WireDefault(true.B) when (s2_meta_error) { release_state := s_probe_retry }.elsewhen (s2_prb_ack_data) { release_state := s_probe_rep_dirty }.elsewhen (s2_probe_state.isValid()) { tl_out_c.valid := true.B tl_out_c.bits := cleanReleaseMessage release_state := Mux(releaseDone, s_probe_write_meta, s_probe_rep_clean) }.otherwise { tl_out_c.valid := true.B probeNack := !releaseDone release_state := Mux(releaseDone, s_ready, s_probe_rep_miss) } when (probeNack) { s1_nack := true.B } } when (release_state === s_probe_retry) { metaArb.io.in(6).valid := true.B metaArb.io.in(6).bits.idx := probeIdx(probe_bits) metaArb.io.in(6).bits.addr := Cat(io.cpu.req.bits.addr >> paddrBits, probe_bits.address) when (metaArb.io.in(6).ready) { release_state := s_ready s1_probe := true.B } } when (release_state === s_probe_rep_miss) { tl_out_c.valid := true.B when (releaseDone) { release_state := s_ready } } when (release_state === s_probe_rep_clean) { tl_out_c.valid := true.B tl_out_c.bits := cleanReleaseMessage when (releaseDone) { release_state := s_probe_write_meta } } when (release_state === s_probe_rep_dirty) { tl_out_c.bits := dirtyReleaseMessage when (releaseDone) { release_state := s_probe_write_meta } } when (release_state.isOneOf(s_voluntary_writeback, s_voluntary_write_meta, s_voluntary_release)) { when (release_state === s_voluntary_release) { tl_out_c.bits := edge.Release(fromSource = 0.U, toAddress = 0.U, lgSize = lgCacheBlockBytes.U, shrinkPermissions = s2_shrink_param)._2 }.otherwise { tl_out_c.bits := edge.Release(fromSource = 0.U, toAddress = 0.U, lgSize = lgCacheBlockBytes.U, shrinkPermissions = s2_shrink_param, data = 0.U)._2 } newCoh := voluntaryNewCoh releaseWay := s2_victim_or_hit_way when (releaseDone) { release_state := s_voluntary_write_meta } when (tl_out_c.fire && c_first) { release_ack_wait := true.B release_ack_addr := probe_bits.address } } tl_out_c.bits.source := probe_bits.source tl_out_c.bits.address := probe_bits.address tl_out_c.bits.data := s2_data_corrected tl_out_c.bits.corrupt := inWriteback && s2_data_error_uncorrectable } tl_out_c.bits.user.lift(AMBAProt).foreach { x => x.fetch := false.B x.secure := true.B x.privileged := true.B x.bufferable := true.B x.modifiable := true.B x.readalloc := true.B x.writealloc := true.B } dataArb.io.in(2).valid := inWriteback && releaseDataBeat < refillCycles.U dataArb.io.in(2).bits := dataArb.io.in(1).bits dataArb.io.in(2).bits.write := false.B dataArb.io.in(2).bits.addr := (probeIdx(probe_bits) << blockOffBits) \| (releaseDataBeat(log2Up(refillCycles)-1,0) << rowOffBits) dataArb.io.in(2).bits.wordMask := ~0.U((rowBytes / subWordBytes).W) dataArb.io.in(2).bits.eccMask := ~0.U((wordBytes / eccBytes).W) dataArb.io.in(2).bits.way_en := ~0.U(nWays.W) metaArb.io.in(4).valid := release_state.isOneOf(s_voluntary_write_meta, s_probe_write_meta) metaArb.io.in(4).bits.write := true.B metaArb.io.in(4).bits.way_en := releaseWay metaArb.io.in(4).bits.idx := probeIdx(probe_bits) metaArb.io.in(4).bits.addr := Cat(io.cpu.req.bits.addr >> untagBits, probe_bits.address(idxMSB, 0)) metaArb.io.in(4).bits.data := tECC.encode(L1Metadata(tl_out_c.bits.address >> tagLSB, newCoh).asUInt) when (metaArb.io.in(4).fire) { release_state := s_ready } // cached response (io.cpu.resp.bits: Data).waiveAll :<>= (s2_req: Data).waiveAll io.cpu.resp.bits.has_data := s2_read io.cpu.resp.bits.replay := false.B io.cpu.s2_uncached := s2_uncached && !s2_hit io.cpu.s2_paddr := s2_req.addr io.cpu.s2_gpa := s2_tlb_xcpt.gpa io.cpu.s2_gpa_is_pte := s2_tlb_xcpt.gpa_is_pte // report whether there are any outstanding accesses. disregard any // slave-port accesses, since they don't affect local memory ordering. val s1_isSlavePortAccess = s1_req.no_xcpt val s2_isSlavePortAccess = s2_req.no_xcpt io.cpu.ordered := !(s1_valid && !s1_isSlavePortAccess \|\| s2_valid && !s2_isSlavePortAccess \|\| cached_grant_wait \|\| uncachedInFlight.asUInt.orR) io.cpu.store_pending := (cached_grant_wait && isWrite(s2_req.cmd)) \|\| uncachedInFlight.asUInt.orR val s1_xcpt_valid = tlb.io.req.valid && !s1_isSlavePortAccess && !s1_nack io.cpu.s2_xcpt := Mux(RegNext(s1_xcpt_valid), s2_tlb_xcpt, 0.U.asTypeOf(s2_tlb_xcpt)) if (usingDataScratchpad) { assert(!(s2_valid_masked && s2_req.cmd.isOneOf(M_XLR, M_XSC))) } else { ccover(tl_out.b.valid && !tl_out.b.ready, "BLOCK_B", "D$ B-channel blocked") } // uncached response val s1_uncached_data_word = { val word_idx = uncachedResp.addr.extract(log2Up(rowBits/8)-1, log2Up(wordBytes)) val words = tl_out.d.bits.data.grouped(wordBits) words(word_idx) } val s2_uncached_data_word = RegEnable(s1_uncached_data_word, io.cpu.replay_next) val doUncachedResp = RegNext(io.cpu.replay_next) io.cpu.resp.valid := (s2_valid_hit_pre_data_ecc \|\| doUncachedResp) && !s2_data_error io.cpu.replay_next := tl_out.d.fire && grantIsUncachedData && !cacheParams.separateUncachedResp.B when (doUncachedResp) { assert(!s2_valid_hit) io.cpu.resp.bits.replay := true.B io.cpu.resp.bits.addr := s2_uncached_resp_addr } io.cpu.uncached_resp.map { resp => resp.valid := tl_out.d.valid && grantIsUncachedData resp.bits.tag := uncachedResp.tag resp.bits.size := uncachedResp.size resp.bits.signed := uncachedResp.signed resp.bits.data := new LoadGen(uncachedResp.size, uncachedResp.signed, uncachedResp.addr, s1_uncached_data_word, false.B, wordBytes).data resp.bits.data_raw := s1_uncached_data_word when (grantIsUncachedData && !resp.ready) { tl_out.d.ready := false.B } } // load data subword mux/sign extension val s2_data_word = (0 until rowBits by wordBits).map(i => s2_data_uncorrected(wordBits+i-1,i)).reduce(_\|_) val s2_data_word_corrected = (0 until rowBits by wordBits).map(i => s2_data_corrected(wordBits+i-1,i)).reduce(_\|_) val s2_data_word_possibly_uncached = Mux(cacheParams.pipelineWayMux.B && doUncachedResp, s2_uncached_data_word, 0.U) \| s2_data_word val loadgen = new LoadGen(s2_req.size, s2_req.signed, s2_req.addr, s2_data_word_possibly_uncached, s2_sc, wordBytes) io.cpu.resp.bits.data := loadgen.data \| s2_sc_fail io.cpu.resp.bits.data_word_bypass := loadgen.wordData io.cpu.resp.bits.data_raw := s2_data_word io.cpu.resp.bits.store_data := pstore1_data // AMOs if (usingRMW) { val amoalus = (0 until coreDataBits / xLen).map { i => val amoalu = Module(new AMOALU(xLen)) amoalu.io.mask := pstore1_mask >> (i * xBytes) amoalu.io.cmd := (if (usingAtomicsInCache) pstore1_cmd else M_XWR) amoalu.io.lhs := s2_data_word >> (i * xLen) amoalu.io.rhs := pstore1_data >> (i * xLen) amoalu } pstore1_storegen_data := (if (!usingDataScratchpad) amoalus.map(_.io.out).asUInt else { val mask = FillInterleaved(8, Mux(s2_correct, 0.U, pstore1_mask)) amoalus.map(_.io.out_unmasked).asUInt & mask \| s2_data_word_corrected & ~mask }) } else if (!usingAtomics) { assert(!(s1_valid_masked && s1_read && s1_write), "unsupported D$ operation") } if (coreParams.useVector) { edge.manager.managers.foreach { m => // Statically ensure that no-allocate accesses are permitted. // We could consider turning some of these into dynamic PMA checks. require(!m.supportsAcquireB \|\| m.supportsGet, "With a vector unit, cacheable memory must support Get") require(!m.supportsAcquireT \|\| m.supportsPutPartial, "With a vector unit, cacheable memory must support PutPartial") } } // flushes if (!usingDataScratchpad) when (RegNext(reset.asBool)) { resetting := true.B } val flushCounterNext = flushCounter +& 1.U val flushDone = (flushCounterNext >> log2Ceil(nSets)) === nWays.U val flushCounterWrap = flushCounterNext(log2Ceil(nSets)-1, 0) ccover(s2_valid_masked && s2_cmd_flush_all && s2_meta_error, "TAG_ECC_ERROR_DURING_FENCE_I", "D$ ECC error in tag array during cache flush") ccover(s2_valid_masked && s2_cmd_flush_all && s2_data_error, "DATA_ECC_ERROR_DURING_FENCE_I", "D$ ECC error in data array during cache flush") s1_flush_valid := metaArb.io.in(5).fire && !s1_flush_valid && !s2_flush_valid_pre_tag_ecc && release_state === s_ready && !release_ack_wait metaArb.io.in(5).valid := flushing && !flushed metaArb.io.in(5).bits.write := false.B metaArb.io.in(5).bits.idx := flushCounter(idxBits-1, 0) metaArb.io.in(5).bits.addr := Cat(io.cpu.req.bits.addr >> untagBits, metaArb.io.in(5).bits.idx << blockOffBits) metaArb.io.in(5).bits.way_en := metaArb.io.in(4).bits.way_en metaArb.io.in(5).bits.data := metaArb.io.in(4).bits.data // Only flush D$ on FENCE.I if some cached executable regions are untracked. if (supports_flush) { when (s2_valid_masked && s2_cmd_flush_all) { when (!flushed && !io.cpu.s2_kill && !release_ack_wait && !uncachedInFlight.asUInt.orR) { flushing := true.B flushing_req := s2_req } } when (tl_out_a.fire && !s2_uncached) { flushed := false.B } when (flushing) { s1_victim_way := flushCounter >> log2Up(nSets) when (s2_flush_valid) { flushCounter := flushCounterNext when (flushDone) { flushed := true.B if (!isPow2(nWays)) flushCounter := flushCounterWrap } } when (flushed && release_state === s_ready && !release_ack_wait) { flushing := false.B } } } metaArb.io.in(0).valid := resetting metaArb.io.in(0).bits := metaArb.io.in(5).bits metaArb.io.in(0).bits.write := true.B metaArb.io.in(0).bits.way_en := ~0.U(nWays.W) metaArb.io.in(0).bits.data := tECC.encode(L1Metadata(0.U, ClientMetadata.onReset).asUInt) when (resetting) { flushCounter := flushCounterNext when (flushDone) { resetting := false.B if (!isPow2(nWays)) flushCounter := flushCounterWrap } } // gate the clock clock_en_reg := !cacheParams.clockGate.B \|\| io.ptw.customCSRs.disableDCacheClockGate \|\| io.cpu.keep_clock_enabled \|\| metaArb.io.out.valid \|\| // subsumes resetting \|\| flushing s1_probe \|\| s2_probe \|\| s1_valid \|\| s2_valid \|\| io.tlb_port.req.valid \|\| s1_tlb_req_valid \|\| s2_tlb_req_valid \|\| pstore1_held \|\| pstore2_valid \|\| release_state =/= s_ready \|\| release_ack_wait \|\| !release_queue_empty \|\| !tlb.io.req.ready \|\| cached_grant_wait \|\| uncachedInFlight.asUInt.orR \|\| lrscCount > 0.U \|\| blockProbeAfterGrantCount > 0.U // performance events io.cpu.perf.acquire := edge.done(tl_out_a) io.cpu.perf.release := edge.done(tl_out_c) io.cpu.perf.grant := tl_out.d.valid && d_last io.cpu.perf.tlbMiss := io.ptw.req.fire io.cpu.perf.storeBufferEmptyAfterLoad := !( (s1_valid && s1_write) \|\| ((s2_valid && s2_write && !s2_waw_hazard) \|\| pstore1_held) \|\| pstore2_valid) io.cpu.perf.storeBufferEmptyAfterStore := !( (s1_valid && s1_write) \|\| (s2_valid && s2_write && pstore1_rmw) \|\| ((s2_valid && s2_write && !s2_waw_hazard \|\| pstore1_held) && pstore2_valid)) io.cpu.perf.canAcceptStoreThenLoad := !( ((s2_valid && s2_write && pstore1_rmw) && (s1_valid && s1_write && !s1_waw_hazard)) \|\| (pstore2_valid && pstore1_valid_likely && (s1_valid && s1_write))) io.cpu.perf.canAcceptStoreThenRMW := io.cpu.perf.canAcceptStoreThenLoad && !pstore2_valid io.cpu.perf.canAcceptLoadThenLoad := !((s1_valid && s1_write && needsRead(s1_req)) && ((s2_valid && s2_write && !s2_waw_hazard \|\| pstore1_held) \|\| pstore2_valid)) io.cpu.perf.blocked := { // stop reporting blocked just before unblocking to avoid overly conservative stalling val beatsBeforeEnd = outer.crossing match { case SynchronousCrossing(_) => 2 case RationalCrossing(_) => 1 // assumes 1 < ratio <= 2; need more bookkeeping for optimal handling of >2 case _: AsynchronousCrossing => 1 // likewise case _: CreditedCrossing => 1 // likewise } val near_end_of_refill = if (cacheBlockBytes / beatBytes <= beatsBeforeEnd) tl_out.d.valid else { val refill_count = RegInit(0.U((cacheBlockBytes / beatBytes).log2.W)) when (tl_out.d.fire && grantIsRefill) { refill_count := refill_count + 1.U } refill_count >= (cacheBlockBytes / beatBytes - beatsBeforeEnd).U } cached_grant_wait && !near_end_of_refill } // report errors val (data_error, data_error_uncorrectable, data_error_addr) = if (usingDataScratchpad) (s2_valid_data_error, s2_data_error_uncorrectable, s2_req.addr) else { (RegNext(tl_out_c.fire && inWriteback && s2_data_error), RegNext(s2_data_error_uncorrectable), probe_bits.address) // This is stable for a cycle after tl_out_c.fire, so don't need a register } { val error_addr = Mux(metaArb.io.in(1).valid, Cat(s2_first_meta_corrected.tag, metaArb.io.in(1).bits.addr(tagLSB-1, idxLSB)), data_error_addr >> idxLSB) << idxLSB io.errors.uncorrectable.foreach { u => u.valid := metaArb.io.in(1).valid && s2_meta_error_uncorrectable \|\| data_error && data_error_uncorrectable u.bits := error_addr } io.errors.correctable.foreach { c => c.valid := metaArb.io.in(1).valid \|\| data_error c.bits := error_addr io.errors.uncorrectable.foreach { u => when (u.valid) { c.valid := false.B } } } io.errors.bus.valid := tl_out.d.fire && (tl_out.d.bits.denied \|\| tl_out.d.bits.corrupt) io.errors.bus.bits := Mux(grantIsCached, s2_req.addr >> idxLSB << idxLSB, 0.U) ccoverNotScratchpad(io.errors.bus.valid && grantIsCached, "D_ERROR_CACHED", "D$ D-channel error, cached") ccover(io.errors.bus.valid && !grantIsCached, "D_ERROR_UNCACHED", "D$ D-channel error, uncached") } if (usingDataScratchpad) { val data_error_cover = Seq( property.CoverBoolean(!data_error, Seq("no_data_error")), property.CoverBoolean(data_error && !data_error_uncorrectable, Seq("data_correctable_error")), property.CoverBoolean(data_error && data_error_uncorrectable, Seq("data_uncorrectable_error"))) val request_source = Seq( property.CoverBoolean(s2_isSlavePortAccess, Seq("from_TL")), property.CoverBoolean(!s2_isSlavePortAccess, Seq("from_CPU"))) property.cover(new property.CrossProperty( Seq(data_error_cover, request_source), Seq(), "MemorySystem;;Scratchpad Memory Bit Flip Cross Covers")) } else { val data_error_type = Seq( property.CoverBoolean(!s2_valid_data_error, Seq("no_data_error")), property.CoverBoolean(s2_valid_data_error && !s2_data_error_uncorrectable, Seq("data_correctable_error")), property.CoverBoolean(s2_valid_data_error && s2_data_error_uncorrectable, Seq("data_uncorrectable_error"))) val data_error_dirty = Seq( property.CoverBoolean(!s2_victim_dirty, Seq("data_clean")), property.CoverBoolean(s2_victim_dirty, Seq("data_dirty"))) val request_source = if (supports_flush) { Seq( property.CoverBoolean(!flushing, Seq("access")), property.CoverBoolean(flushing, Seq("during_flush"))) } else { Seq(property.CoverBoolean(true.B, Seq("never_flush"))) } val tag_error_cover = Seq( property.CoverBoolean( !s2_meta_error, Seq("no_tag_error")), property.CoverBoolean( s2_meta_error && !s2_meta_error_uncorrectable, Seq("tag_correctable_error")), property.CoverBoolean( s2_meta_error && s2_meta_error_uncorrectable, Seq("tag_uncorrectable_error"))) property.cover(new property.CrossProperty( Seq(data_error_type, data_error_dirty, request_source, tag_error_cover), Seq(), "MemorySystem;;Cache Memory Bit Flip Cross Covers")) } } // leaving gated-clock domain val dcacheImpl = withClock (gated_clock) { new DCacheModuleImpl } def encodeData(x: UInt, poison: Bool) = x.grouped(eccBits).map(dECC.encode(_, if (dECC.canDetect) poison else false.B)).asUInt def dummyEncodeData(x: UInt) = x.grouped(eccBits).map(dECC.swizzle(_)).asUInt def decodeData(x: UInt) = x.grouped(dECC.width(eccBits)).map(dECC.decode(_)) def eccMask(byteMask: UInt) = byteMask.grouped(eccBytes).map(_.orR).asUInt def eccByteMask(byteMask: UInt) = FillInterleaved(eccBytes, eccMask(byteMask)) def likelyNeedsRead(req: HellaCacheReq) = { val res = !req.cmd.isOneOf(M_XWR, M_PFW) \|\| req.size < log2Ceil(eccBytes).U assert(!needsRead(req) \|\| res) res } def needsRead(req: HellaCacheReq) = isRead(req.cmd) \|\| (isWrite(req.cmd) && (req.cmd === M_PWR \|\| req.size < log2Ceil(eccBytes).U)) def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = property.cover(cond, s"DCACHE_$label", "MemorySystem;;" + desc) def ccoverNotScratchpad(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = if (!usingDataScratchpad) ccover(cond, label, desc) require(!usingVM \|\| tagLSB <= pgIdxBits, s"D$$ set size must not exceed ${1<<(pgIdxBits-10)} KiB; got ${(nSets * cacheBlockBytes)>>10} KiB") def tagLSB: Int = untagBits def probeIdx(b: TLBundleB): UInt = b.address(idxMSB, idxLSB) def addressToProbe(vaddr: UInt, paddr: UInt): TLBundleB = { val res = Wire(new TLBundleB(edge.bundle)) res :#= DontCare res.address := paddr res.source := (mmioOffset - 1).U res } def acquire(vaddr: UInt, paddr: UInt, param: UInt): TLBundleA = { if (!edge.manager.anySupportAcquireB) WireDefault(0.U.asTypeOf(new TLBundleA(edge.bundle))) else edge.AcquireBlock(0.U, paddr >> lgCacheBlockBytes << lgCacheBlockBytes, lgCacheBlockBytes.U, param)._2 } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } } File AMOALU.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters class StoreGen(typ: UInt, addr: UInt, dat: UInt, maxSize: Int) { val size = Wire(UInt(log2Up(log2Up(maxSize)+1).W)) size := typ val dat_padded = dat.pad(maxSize8) def misaligned: Bool = (addr & ((1.U << size) - 1.U)(log2Up(maxSize)-1,0)).orR def mask = { var res = 1.U for (i <- 0 until log2Up(maxSize)) { val upper = Mux(addr(i), res, 0.U) \| Mux(size >= (i+1).U, ((BigInt(1) << (1 << i))-1).U, 0.U) val lower = Mux(addr(i), 0.U, res) res = Cat(upper, lower) } res } protected def genData(i: Int): UInt = if (i >= log2Up(maxSize)) dat_padded else Mux(size === i.U, Fill(1 << (log2Up(maxSize)-i), dat_padded((8 << i)-1,0)), genData(i+1)) def data = genData(0) def wordData = genData(2) } class LoadGen(typ: UInt, signed: Bool, addr: UInt, dat: UInt, zero: Bool, maxSize: Int) { private val size = new StoreGen(typ, addr, dat, maxSize).size private def genData(logMinSize: Int): UInt = { var res = dat for (i <- log2Up(maxSize)-1 to logMinSize by -1) { val pos = 8 << i val shifted = Mux(addr(i), res(2pos-1,pos), res(pos-1,0)) val doZero = (i == 0).B && zero val zeroed = Mux(doZero, 0.U, shifted) res = Cat(Mux(size === i.U \|\| doZero, Fill(8maxSize-pos, signed && zeroed(pos-1)), res(8*maxSize-1,pos)), zeroed) } res } def wordData = genData(2) def data = genData(0) } class AMOALU(operandBits: Int)(implicit p: Parameters) extends Module { val minXLen = 32 val widths = (0 to log2Ceil(operandBits / minXLen)).map(minXLen << _) val io = IO(new Bundle { val mask = Input(UInt((operandBits / 8).W)) val cmd = Input(UInt(M_SZ.W)) val lhs = Input(UInt(operandBits.W)) val rhs = Input(UInt(operandBits.W)) val out = Output(UInt(operandBits.W)) val out_unmasked = Output(UInt(operandBits.W)) }) val max = io.cmd === M_XA_MAX \|\| io.cmd === M_XA_MAXU val min = io.cmd === M_XA_MIN \|\| io.cmd === M_XA_MINU val add = io.cmd === M_XA_ADD val logic_and = io.cmd === M_XA_OR \|\| io.cmd === M_XA_AND val logic_xor = io.cmd === M_XA_XOR \|\| io.cmd === M_XA_OR val adder_out = { // partition the carry chain to support sub-xLen addition val mask = ~(0.U(operandBits.W) +: widths.init.map(w => !io.mask(w/8-1) << (w-1))).reduce(_\|_) (io.lhs & mask) + (io.rhs & mask) } val less = { // break up the comparator so the lower parts will be CSE'd def isLessUnsigned(x: UInt, y: UInt, n: Int): Bool = { if (n == minXLen) x(n-1, 0) < y(n-1, 0) else x(n-1, n/2) < y(n-1, n/2) \|\| x(n-1, n/2) === y(n-1, n/2) && isLessUnsigned(x, y, n/2) } def isLess(x: UInt, y: UInt, n: Int): Bool = { val signed = { val mask = M_XA_MIN ^ M_XA_MINU (io.cmd & mask) === (M_XA_MIN & mask) } Mux(x(n-1) === y(n-1), isLessUnsigned(x, y, n), Mux(signed, x(n-1), y(n-1))) } PriorityMux(widths.reverse.map(w => (io.mask(w/8/2), isLess(io.lhs, io.rhs, w)))) } val minmax = Mux(Mux(less, min, max), io.lhs, io.rhs) val logic = Mux(logic_and, io.lhs & io.rhs, 0.U) \| Mux(logic_xor, io.lhs ^ io.rhs, 0.U) val out = Mux(add, adder_out, Mux(logic_and \|\| logic_xor, logic, minmax)) val wmask = FillInterleaved(8, io.mask) io.out := wmask & out \| ~wmask & io.lhs io.out_unmasked := out }	module DCache( // @[DCache.scala:101:7] input clock, // @[DCache.scala:101:7] input reset, // @[DCache.scala:101:7] input auto_hart_id_sink_in, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output io_cpu_req_ready, // @[HellaCache.scala:243:14] input io_cpu_req_valid, // @[HellaCache.scala:243:14] input [33:0] io_cpu_req_bits_addr, // @[HellaCache.scala:243:14] input [6:0] io_cpu_req_bits_tag, // @[HellaCache.scala:243:14] input [4:0] io_cpu_req_bits_cmd, // @[HellaCache.scala:243:14] input [1:0] io_cpu_req_bits_size, // @[HellaCache.scala:243:14] input io_cpu_req_bits_signed, // @[HellaCache.scala:243:14] input [1:0] io_cpu_req_bits_dprv, // @[HellaCache.scala:243:14] input io_cpu_req_bits_dv, // @[HellaCache.scala:243:14] input io_cpu_req_bits_phys, // @[HellaCache.scala:243:14] input io_cpu_req_bits_no_resp, // @[HellaCache.scala:243:14] input io_cpu_req_bits_no_xcpt, // @[HellaCache.scala:243:14] input io_cpu_s1_kill, // @[HellaCache.scala:243:14] input [63:0] io_cpu_s1_data_data, // @[HellaCache.scala:243:14] input [7:0] io_cpu_s1_data_mask, // @[HellaCache.scala:243:14] output io_cpu_s2_nack, // @[HellaCache.scala:243:14] output io_cpu_s2_nack_cause_raw, // @[HellaCache.scala:243:14] output io_cpu_s2_uncached, // @[HellaCache.scala:243:14] output [31:0] io_cpu_s2_paddr, // @[HellaCache.scala:243:14] output io_cpu_resp_valid, // @[HellaCache.scala:243:14] output [33:0] io_cpu_resp_bits_addr, // @[HellaCache.scala:243:14] output [6:0] io_cpu_resp_bits_tag, // @[HellaCache.scala:243:14] output [4:0] io_cpu_resp_bits_cmd, // @[HellaCache.scala:243:14] output [1:0] io_cpu_resp_bits_size, // @[HellaCache.scala:243:14] output io_cpu_resp_bits_signed, // @[HellaCache.scala:243:14] output [1:0] io_cpu_resp_bits_dprv, // @[HellaCache.scala:243:14] output io_cpu_resp_bits_dv, // @[HellaCache.scala:243:14] output [63:0] io_cpu_resp_bits_data, // @[HellaCache.scala:243:14] output [7:0] io_cpu_resp_bits_mask, // @[HellaCache.scala:243:14] output io_cpu_resp_bits_replay, // @[HellaCache.scala:243:14] output io_cpu_resp_bits_has_data, // @[HellaCache.scala:243:14] output [63:0] io_cpu_resp_bits_data_word_bypass, // @[HellaCache.scala:243:14] output [63:0] io_cpu_resp_bits_data_raw, // @[HellaCache.scala:243:14] output [63:0] io_cpu_resp_bits_store_data, // @[HellaCache.scala:243:14] output io_cpu_replay_next, // @[HellaCache.scala:243:14] output io_cpu_s2_xcpt_ma_ld, // @[HellaCache.scala:243:14] output io_cpu_s2_xcpt_ma_st, // @[HellaCache.scala:243:14] output io_cpu_s2_xcpt_pf_ld, // @[HellaCache.scala:243:14] output io_cpu_s2_xcpt_pf_st, // @[HellaCache.scala:243:14] output io_cpu_s2_xcpt_ae_ld, // @[HellaCache.scala:243:14] output io_cpu_s2_xcpt_ae_st, // @[HellaCache.scala:243:14] output [33:0] io_cpu_s2_gpa, // @[HellaCache.scala:243:14] output io_cpu_ordered, // @[HellaCache.scala:243:14] output io_cpu_store_pending, // @[HellaCache.scala:243:14] output io_cpu_perf_acquire, // @[HellaCache.scala:243:14] output io_cpu_perf_grant, // @[HellaCache.scala:243:14] output io_cpu_perf_blocked, // @[HellaCache.scala:243:14] output io_cpu_perf_canAcceptStoreThenLoad, // @[HellaCache.scala:243:14] output io_cpu_perf_canAcceptStoreThenRMW, // @[HellaCache.scala:243:14] output io_cpu_perf_canAcceptLoadThenLoad, // @[HellaCache.scala:243:14] output io_cpu_perf_storeBufferEmptyAfterLoad, // @[HellaCache.scala:243:14] output io_cpu_perf_storeBufferEmptyAfterStore, // @[HellaCache.scala:243:14] input io_cpu_keep_clock_enabled, // @[HellaCache.scala:243:14] input io_ptw_req_ready, // @[HellaCache.scala:243:14] output [20:0] io_ptw_req_bits_bits_addr, // @[HellaCache.scala:243:14] output io_ptw_req_bits_bits_need_gpa, // @[HellaCache.scala:243:14] output io_ptw_req_bits_bits_vstage1, // @[HellaCache.scala:243:14] output io_ptw_req_bits_bits_stage2, // @[HellaCache.scala:243:14] input io_ptw_resp_valid, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_ae_ptw, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_ae_final, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_pf, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_gf, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_hr, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_hw, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_hx, // @[HellaCache.scala:243:14] input [9:0] io_ptw_resp_bits_pte_reserved_for_future, // @[HellaCache.scala:243:14] input [43:0] io_ptw_resp_bits_pte_ppn, // @[HellaCache.scala:243:14] input [1:0] io_ptw_resp_bits_pte_reserved_for_software, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_pte_d, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_pte_a, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_pte_g, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_pte_u, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_pte_x, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_pte_w, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_pte_r, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_pte_v, // @[HellaCache.scala:243:14] input [1:0] io_ptw_resp_bits_level, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_homogeneous, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_gpa_valid, // @[HellaCache.scala:243:14] input [32:0] io_ptw_resp_bits_gpa_bits, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_gpa_is_pte, // @[HellaCache.scala:243:14] input io_ptw_status_debug, // @[HellaCache.scala:243:14] input io_ptw_status_cease, // @[HellaCache.scala:243:14] input io_ptw_status_wfi, // @[HellaCache.scala:243:14] input [31:0] io_ptw_status_isa, // @[HellaCache.scala:243:14] input io_ptw_status_dv, // @[HellaCache.scala:243:14] input io_ptw_status_v, // @[HellaCache.scala:243:14] input io_ptw_status_sd, // @[HellaCache.scala:243:14] input io_ptw_status_mpv, // @[HellaCache.scala:243:14] input io_ptw_status_gva, // @[HellaCache.scala:243:14] input [1:0] io_ptw_status_fs, // @[HellaCache.scala:243:14] input [1:0] io_ptw_status_mpp, // @[HellaCache.scala:243:14] input io_ptw_status_mpie, // @[HellaCache.scala:243:14] input io_ptw_status_mie, // @[HellaCache.scala:243:14] input io_ptw_gstatus_debug, // @[HellaCache.scala:243:14] input io_ptw_gstatus_cease, // @[HellaCache.scala:243:14] input io_ptw_gstatus_wfi, // @[HellaCache.scala:243:14] input [31:0] io_ptw_gstatus_isa, // @[HellaCache.scala:243:14] input [1:0] io_ptw_gstatus_dprv, // @[HellaCache.scala:243:14] input io_ptw_gstatus_dv, // @[HellaCache.scala:243:14] input [1:0] io_ptw_gstatus_prv, // @[HellaCache.scala:243:14] input io_ptw_gstatus_v, // @[HellaCache.scala:243:14] input io_ptw_gstatus_sd, // @[HellaCache.scala:243:14] input [22:0] io_ptw_gstatus_zero2, // @[HellaCache.scala:243:14] input io_ptw_gstatus_mpv, // @[HellaCache.scala:243:14] input io_ptw_gstatus_gva, // @[HellaCache.scala:243:14] input io_ptw_gstatus_mbe, // @[HellaCache.scala:243:14] input io_ptw_gstatus_sbe, // @[HellaCache.scala:243:14] input [1:0] io_ptw_gstatus_sxl, // @[HellaCache.scala:243:14] input [7:0] io_ptw_gstatus_zero1, // @[HellaCache.scala:243:14] input io_ptw_gstatus_tsr, // @[HellaCache.scala:243:14] input io_ptw_gstatus_tw, // @[HellaCache.scala:243:14] input io_ptw_gstatus_tvm, // @[HellaCache.scala:243:14] input io_ptw_gstatus_mxr, // @[HellaCache.scala:243:14] input io_ptw_gstatus_sum, // @[HellaCache.scala:243:14] input io_ptw_gstatus_mprv, // @[HellaCache.scala:243:14] input [1:0] io_ptw_gstatus_fs, // @[HellaCache.scala:243:14] input [1:0] io_ptw_gstatus_mpp, // @[HellaCache.scala:243:14] input [1:0] io_ptw_gstatus_vs, // @[HellaCache.scala:243:14] input io_ptw_gstatus_spp, // @[HellaCache.scala:243:14] input io_ptw_gstatus_mpie, // @[HellaCache.scala:243:14] input io_ptw_gstatus_ube, // @[HellaCache.scala:243:14] input io_ptw_gstatus_spie, // @[HellaCache.scala:243:14] input io_ptw_gstatus_upie, // @[HellaCache.scala:243:14] input io_ptw_gstatus_mie, // @[HellaCache.scala:243:14] input io_ptw_gstatus_hie, // @[HellaCache.scala:243:14] input io_ptw_gstatus_sie, // @[HellaCache.scala:243:14] input io_ptw_gstatus_uie, // @[HellaCache.scala:243:14] input io_ptw_pmp_0_cfg_l, // @[HellaCache.scala:243:14] input [1:0] io_ptw_pmp_0_cfg_a, // @[HellaCache.scala:243:14] input io_ptw_pmp_0_cfg_x, // @[HellaCache.scala:243:14] input io_ptw_pmp_0_cfg_w, // @[HellaCache.scala:243:14] input io_ptw_pmp_0_cfg_r, // @[HellaCache.scala:243:14] input [29:0] io_ptw_pmp_0_addr, // @[HellaCache.scala:243:14] input [31:0] io_ptw_pmp_0_mask, // @[HellaCache.scala:243:14] input io_ptw_pmp_1_cfg_l, // @[HellaCache.scala:243:14] input [1:0] io_ptw_pmp_1_cfg_a, // @[HellaCache.scala:243:14] input io_ptw_pmp_1_cfg_x, // @[HellaCache.scala:243:14] input io_ptw_pmp_1_cfg_w, // @[HellaCache.scala:243:14] input io_ptw_pmp_1_cfg_r, // @[HellaCache.scala:243:14] input [29:0] io_ptw_pmp_1_addr, // @[HellaCache.scala:243:14] input [31:0] io_ptw_pmp_1_mask, // @[HellaCache.scala:243:14] input io_ptw_pmp_2_cfg_l, // @[HellaCache.scala:243:14] input [1:0] io_ptw_pmp_2_cfg_a, // @[HellaCache.scala:243:14] input io_ptw_pmp_2_cfg_x, // @[HellaCache.scala:243:14] input io_ptw_pmp_2_cfg_w, // @[HellaCache.scala:243:14] input io_ptw_pmp_2_cfg_r, // @[HellaCache.scala:243:14] input [29:0] io_ptw_pmp_2_addr, // @[HellaCache.scala:243:14] input [31:0] io_ptw_pmp_2_mask, // @[HellaCache.scala:243:14] input io_ptw_pmp_3_cfg_l, // @[HellaCache.scala:243:14] input [1:0] io_ptw_pmp_3_cfg_a, // @[HellaCache.scala:243:14] input io_ptw_pmp_3_cfg_x, // @[HellaCache.scala:243:14] input io_ptw_pmp_3_cfg_w, // @[HellaCache.scala:243:14] input io_ptw_pmp_3_cfg_r, // @[HellaCache.scala:243:14] input [29:0] io_ptw_pmp_3_addr, // @[HellaCache.scala:243:14] input [31:0] io_ptw_pmp_3_mask, // @[HellaCache.scala:243:14] input io_ptw_pmp_4_cfg_l, // @[HellaCache.scala:243:14] input [1:0] io_ptw_pmp_4_cfg_a, // @[HellaCache.scala:243:14] input io_ptw_pmp_4_cfg_x, // @[HellaCache.scala:243:14] input io_ptw_pmp_4_cfg_w, // @[HellaCache.scala:243:14] input io_ptw_pmp_4_cfg_r, // @[HellaCache.scala:243:14] input [29:0] io_ptw_pmp_4_addr, // @[HellaCache.scala:243:14] input [31:0] io_ptw_pmp_4_mask, // @[HellaCache.scala:243:14] input io_ptw_pmp_5_cfg_l, // @[HellaCache.scala:243:14] input [1:0] io_ptw_pmp_5_cfg_a, // @[HellaCache.scala:243:14] input io_ptw_pmp_5_cfg_x, // @[HellaCache.scala:243:14] input io_ptw_pmp_5_cfg_w, // @[HellaCache.scala:243:14] input io_ptw_pmp_5_cfg_r, // @[HellaCache.scala:243:14] input [29:0] io_ptw_pmp_5_addr, // @[HellaCache.scala:243:14] input [31:0] io_ptw_pmp_5_mask, // @[HellaCache.scala:243:14] input io_ptw_pmp_6_cfg_l, // @[HellaCache.scala:243:14] input [1:0] io_ptw_pmp_6_cfg_a, // @[HellaCache.scala:243:14] input io_ptw_pmp_6_cfg_x, // @[HellaCache.scala:243:14] input io_ptw_pmp_6_cfg_w, // @[HellaCache.scala:243:14] input io_ptw_pmp_6_cfg_r, // @[HellaCache.scala:243:14] input [29:0] io_ptw_pmp_6_addr, // @[HellaCache.scala:243:14] input [31:0] io_ptw_pmp_6_mask, // @[HellaCache.scala:243:14] input io_ptw_pmp_7_cfg_l, // @[HellaCache.scala:243:14] input [1:0] io_ptw_pmp_7_cfg_a, // @[HellaCache.scala:243:14] input io_ptw_pmp_7_cfg_x, // @[HellaCache.scala:243:14] input io_ptw_pmp_7_cfg_w, // @[HellaCache.scala:243:14] input io_ptw_pmp_7_cfg_r, // @[HellaCache.scala:243:14] input [29:0] io_ptw_pmp_7_addr, // @[HellaCache.scala:243:14] input [31:0] io_ptw_pmp_7_mask, // @[HellaCache.scala:243:14] input io_ptw_customCSRs_csrs_0_ren, // @[HellaCache.scala:243:14] input io_ptw_customCSRs_csrs_0_wen, // @[HellaCache.scala:243:14] input [63:0] io_ptw_customCSRs_csrs_0_wdata, // @[HellaCache.scala:243:14] input [63:0] io_ptw_customCSRs_csrs_0_value, // @[HellaCache.scala:243:14] input io_ptw_customCSRs_csrs_1_ren, // @[HellaCache.scala:243:14] input io_ptw_customCSRs_csrs_1_wen, // @[HellaCache.scala:243:14] input [63:0] io_ptw_customCSRs_csrs_1_wdata, // @[HellaCache.scala:243:14] input [63:0] io_ptw_customCSRs_csrs_1_value, // @[HellaCache.scala:243:14] input io_ptw_customCSRs_csrs_2_ren, // @[HellaCache.scala:243:14] input io_ptw_customCSRs_csrs_2_wen, // @[HellaCache.scala:243:14] input [63:0] io_ptw_customCSRs_csrs_2_wdata, // @[HellaCache.scala:243:14] input [63:0] io_ptw_customCSRs_csrs_2_value, // @[HellaCache.scala:243:14] input io_ptw_customCSRs_csrs_3_ren, // @[HellaCache.scala:243:14] input io_ptw_customCSRs_csrs_3_wen, // @[HellaCache.scala:243:14] input [63:0] io_ptw_customCSRs_csrs_3_wdata, // @[HellaCache.scala:243:14] input [63:0] io_ptw_customCSRs_csrs_3_value // @[HellaCache.scala:243:14] ); wire [63:0] s1_all_data_ways_0; // @[DCache.scala:325:33] wire s0_req_phys; // @[DCache.scala:192:24] wire [33:0] s0_req_addr; // @[DCache.scala:192:24] wire tl_out_a_valid; // @[DCache.scala:159:22] wire [63:0] tl_out_a_bits_data; // @[DCache.scala:159:22] wire [7:0] tl_out_a_bits_mask; // @[DCache.scala:159:22] wire [31:0] tl_out_a_bits_address; // @[DCache.scala:159:22] wire [3:0] tl_out_a_bits_size; // @[DCache.scala:159:22] wire [2:0] tl_out_a_bits_param; // @[DCache.scala:159:22] wire [2:0] tl_out_a_bits_opcode; // @[DCache.scala:159:22] wire metaArb_io_in_2_valid; // @[DCache.scala:135:28] wire [4:0] pma_checker_io_req_bits_cmd; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_req_bits_size; // @[DCache.scala:120:32] wire [63:0] _amoalus_0_io_out_unmasked; // @[DCache.scala:982:26] wire _lfsr_prng_io_out_0; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_1; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_2; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_3; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_4; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_5; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_6; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_7; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_8; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_9; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_10; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_11; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_12; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_13; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_14; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_15; // @[PRNG.scala:91:22] wire _pma_checker_entries_barrier_12_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_c; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_c; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_c; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_c; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_c; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_c; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_c; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_c; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_c; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_c; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_c; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_c; // @[package.scala:267:25] wire _pma_checker_pma_io_resp_r; // @[TLB.scala:422:19] wire _pma_checker_pma_io_resp_w; // @[TLB.scala:422:19] wire _pma_checker_pma_io_resp_pp; // @[TLB.scala:422:19] wire _pma_checker_pma_io_resp_al; // @[TLB.scala:422:19] wire _pma_checker_pma_io_resp_aa; // @[TLB.scala:422:19] wire _pma_checker_pma_io_resp_x; // @[TLB.scala:422:19] wire _pma_checker_pma_io_resp_eff; // @[TLB.scala:422:19] wire _pma_checker_pmp_io_r; // @[TLB.scala:416:19] wire _pma_checker_pmp_io_w; // @[TLB.scala:416:19] wire _pma_checker_pmp_io_x; // @[TLB.scala:416:19] wire [31:0] _tlb_io_resp_paddr; // @[DCache.scala:119:19] wire [33:0] _tlb_io_resp_gpa; // @[DCache.scala:119:19] wire _tlb_io_resp_pf_ld; // @[DCache.scala:119:19] wire _tlb_io_resp_pf_st; // @[DCache.scala:119:19] wire _tlb_io_resp_pf_inst; // @[DCache.scala:119:19] wire _tlb_io_resp_ae_ld; // @[DCache.scala:119:19] wire _tlb_io_resp_ae_st; // @[DCache.scala:119:19] wire _tlb_io_resp_ae_inst; // @[DCache.scala:119:19] wire _tlb_io_resp_ma_ld; // @[DCache.scala:119:19] wire _tlb_io_resp_ma_st; // @[DCache.scala:119:19] wire _tlb_io_resp_cacheable; // @[DCache.scala:119:19] wire _tlb_io_resp_must_alloc; // @[DCache.scala:119:19] wire _tlb_io_resp_prefetchable; // @[DCache.scala:119:19] wire [1:0] _tlb_io_resp_size; // @[DCache.scala:119:19] wire [4:0] _tlb_io_resp_cmd; // @[DCache.scala:119:19] wire auto_hart_id_sink_in_0 = auto_hart_id_sink_in; // @[DCache.scala:101:7] wire auto_out_a_ready_0 = auto_out_a_ready; // @[DCache.scala:101:7] wire auto_out_d_valid_0 = auto_out_d_valid; // @[DCache.scala:101:7] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[DCache.scala:101:7] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[DCache.scala:101:7] wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[DCache.scala:101:7] wire auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[DCache.scala:101:7] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[DCache.scala:101:7] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[DCache.scala:101:7] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[DCache.scala:101:7] wire io_cpu_req_valid_0 = io_cpu_req_valid; // @[DCache.scala:101:7] wire [33:0] io_cpu_req_bits_addr_0 = io_cpu_req_bits_addr; // @[DCache.scala:101:7] wire [6:0] io_cpu_req_bits_tag_0 = io_cpu_req_bits_tag; // @[DCache.scala:101:7] wire [4:0] io_cpu_req_bits_cmd_0 = io_cpu_req_bits_cmd; // @[DCache.scala:101:7] wire [1:0] io_cpu_req_bits_size_0 = io_cpu_req_bits_size; // @[DCache.scala:101:7] wire io_cpu_req_bits_signed_0 = io_cpu_req_bits_signed; // @[DCache.scala:101:7] wire [1:0] io_cpu_req_bits_dprv_0 = io_cpu_req_bits_dprv; // @[DCache.scala:101:7] wire io_cpu_req_bits_dv_0 = io_cpu_req_bits_dv; // @[DCache.scala:101:7] wire io_cpu_req_bits_phys_0 = io_cpu_req_bits_phys; // @[DCache.scala:101:7] wire io_cpu_req_bits_no_resp_0 = io_cpu_req_bits_no_resp; // @[DCache.scala:101:7] wire io_cpu_req_bits_no_xcpt_0 = io_cpu_req_bits_no_xcpt; // @[DCache.scala:101:7] wire io_cpu_s1_kill_0 = io_cpu_s1_kill; // @[DCache.scala:101:7] wire [63:0] io_cpu_s1_data_data_0 = io_cpu_s1_data_data; // @[DCache.scala:101:7] wire [7:0] io_cpu_s1_data_mask_0 = io_cpu_s1_data_mask; // @[DCache.scala:101:7] wire io_cpu_keep_clock_enabled_0 = io_cpu_keep_clock_enabled; // @[DCache.scala:101:7] wire io_ptw_req_ready_0 = io_ptw_req_ready; // @[DCache.scala:101:7] wire io_ptw_resp_valid_0 = io_ptw_resp_valid; // @[DCache.scala:101:7] wire io_ptw_resp_bits_ae_ptw_0 = io_ptw_resp_bits_ae_ptw; // @[DCache.scala:101:7] wire io_ptw_resp_bits_ae_final_0 = io_ptw_resp_bits_ae_final; // @[DCache.scala:101:7] wire io_ptw_resp_bits_pf_0 = io_ptw_resp_bits_pf; // @[DCache.scala:101:7] wire io_ptw_resp_bits_gf_0 = io_ptw_resp_bits_gf; // @[DCache.scala:101:7] wire io_ptw_resp_bits_hr_0 = io_ptw_resp_bits_hr; // @[DCache.scala:101:7] wire io_ptw_resp_bits_hw_0 = io_ptw_resp_bits_hw; // @[DCache.scala:101:7] wire io_ptw_resp_bits_hx_0 = io_ptw_resp_bits_hx; // @[DCache.scala:101:7] wire [9:0] io_ptw_resp_bits_pte_reserved_for_future_0 = io_ptw_resp_bits_pte_reserved_for_future; // @[DCache.scala:101:7] wire [43:0] io_ptw_resp_bits_pte_ppn_0 = io_ptw_resp_bits_pte_ppn; // @[DCache.scala:101:7] wire [1:0] io_ptw_resp_bits_pte_reserved_for_software_0 = io_ptw_resp_bits_pte_reserved_for_software; // @[DCache.scala:101:7] wire io_ptw_resp_bits_pte_d_0 = io_ptw_resp_bits_pte_d; // @[DCache.scala:101:7] wire io_ptw_resp_bits_pte_a_0 = io_ptw_resp_bits_pte_a; // @[DCache.scala:101:7] wire io_ptw_resp_bits_pte_g_0 = io_ptw_resp_bits_pte_g; // @[DCache.scala:101:7] wire io_ptw_resp_bits_pte_u_0 = io_ptw_resp_bits_pte_u; // @[DCache.scala:101:7] wire io_ptw_resp_bits_pte_x_0 = io_ptw_resp_bits_pte_x; // @[DCache.scala:101:7] wire io_ptw_resp_bits_pte_w_0 = io_ptw_resp_bits_pte_w; // @[DCache.scala:101:7] wire io_ptw_resp_bits_pte_r_0 = io_ptw_resp_bits_pte_r; // @[DCache.scala:101:7] wire io_ptw_resp_bits_pte_v_0 = io_ptw_resp_bits_pte_v; // @[DCache.scala:101:7] wire [1:0] io_ptw_resp_bits_level_0 = io_ptw_resp_bits_level; // @[DCache.scala:101:7] wire io_ptw_resp_bits_homogeneous_0 = io_ptw_resp_bits_homogeneous; // @[DCache.scala:101:7] wire io_ptw_resp_bits_gpa_valid_0 = io_ptw_resp_bits_gpa_valid; // @[DCache.scala:101:7] wire [32:0] io_ptw_resp_bits_gpa_bits_0 = io_ptw_resp_bits_gpa_bits; // @[DCache.scala:101:7] wire io_ptw_resp_bits_gpa_is_pte_0 = io_ptw_resp_bits_gpa_is_pte; // @[DCache.scala:101:7] wire io_ptw_status_debug_0 = io_ptw_status_debug; // @[DCache.scala:101:7] wire io_ptw_status_cease_0 = io_ptw_status_cease; // @[DCache.scala:101:7] wire io_ptw_status_wfi_0 = io_ptw_status_wfi; // @[DCache.scala:101:7] wire [31:0] io_ptw_status_isa_0 = io_ptw_status_isa; // @[DCache.scala:101:7] wire io_ptw_status_dv_0 = io_ptw_status_dv; // @[DCache.scala:101:7] wire io_ptw_status_v_0 = io_ptw_status_v; // @[DCache.scala:101:7] wire io_ptw_status_sd_0 = io_ptw_status_sd; // @[DCache.scala:101:7] wire io_ptw_status_mpv_0 = io_ptw_status_mpv; // @[DCache.scala:101:7] wire io_ptw_status_gva_0 = io_ptw_status_gva; // @[DCache.scala:101:7] wire [1:0] io_ptw_status_fs_0 = io_ptw_status_fs; // @[DCache.scala:101:7] wire [1:0] io_ptw_status_mpp_0 = io_ptw_status_mpp; // @[DCache.scala:101:7] wire io_ptw_status_mpie_0 = io_ptw_status_mpie; // @[DCache.scala:101:7] wire io_ptw_status_mie_0 = io_ptw_status_mie; // @[DCache.scala:101:7] wire io_ptw_gstatus_debug_0 = io_ptw_gstatus_debug; // @[DCache.scala:101:7] wire io_ptw_gstatus_cease_0 = io_ptw_gstatus_cease; // @[DCache.scala:101:7] wire io_ptw_gstatus_wfi_0 = io_ptw_gstatus_wfi; // @[DCache.scala:101:7] wire [31:0] io_ptw_gstatus_isa_0 = io_ptw_gstatus_isa; // @[DCache.scala:101:7] wire [1:0] io_ptw_gstatus_dprv_0 = io_ptw_gstatus_dprv; // @[DCache.scala:101:7] wire io_ptw_gstatus_dv_0 = io_ptw_gstatus_dv; // @[DCache.scala:101:7] wire [1:0] io_ptw_gstatus_prv_0 = io_ptw_gstatus_prv; // @[DCache.scala:101:7] wire io_ptw_gstatus_v_0 = io_ptw_gstatus_v; // @[DCache.scala:101:7] wire io_ptw_gstatus_sd_0 = io_ptw_gstatus_sd; // @[DCache.scala:101:7] wire [22:0] io_ptw_gstatus_zero2_0 = io_ptw_gstatus_zero2; // @[DCache.scala:101:7] wire io_ptw_gstatus_mpv_0 = io_ptw_gstatus_mpv; // @[DCache.scala:101:7] wire io_ptw_gstatus_gva_0 = io_ptw_gstatus_gva; // @[DCache.scala:101:7] wire io_ptw_gstatus_mbe_0 = io_ptw_gstatus_mbe; // @[DCache.scala:101:7] wire io_ptw_gstatus_sbe_0 = io_ptw_gstatus_sbe; // @[DCache.scala:101:7] wire [1:0] io_ptw_gstatus_sxl_0 = io_ptw_gstatus_sxl; // @[DCache.scala:101:7] wire [7:0] io_ptw_gstatus_zero1_0 = io_ptw_gstatus_zero1; // @[DCache.scala:101:7] wire io_ptw_gstatus_tsr_0 = io_ptw_gstatus_tsr; // @[DCache.scala:101:7] wire io_ptw_gstatus_tw_0 = io_ptw_gstatus_tw; // @[DCache.scala:101:7] wire io_ptw_gstatus_tvm_0 = io_ptw_gstatus_tvm; // @[DCache.scala:101:7] wire io_ptw_gstatus_mxr_0 = io_ptw_gstatus_mxr; // @[DCache.scala:101:7] wire io_ptw_gstatus_sum_0 = io_ptw_gstatus_sum; // @[DCache.scala:101:7] wire io_ptw_gstatus_mprv_0 = io_ptw_gstatus_mprv; // @[DCache.scala:101:7] wire [1:0] io_ptw_gstatus_fs_0 = io_ptw_gstatus_fs; // @[DCache.scala:101:7] wire [1:0] io_ptw_gstatus_mpp_0 = io_ptw_gstatus_mpp; // @[DCache.scala:101:7] wire [1:0] io_ptw_gstatus_vs_0 = io_ptw_gstatus_vs; // @[DCache.scala:101:7] wire io_ptw_gstatus_spp_0 = io_ptw_gstatus_spp; // @[DCache.scala:101:7] wire io_ptw_gstatus_mpie_0 = io_ptw_gstatus_mpie; // @[DCache.scala:101:7] wire io_ptw_gstatus_ube_0 = io_ptw_gstatus_ube; // @[DCache.scala:101:7] wire io_ptw_gstatus_spie_0 = io_ptw_gstatus_spie; // @[DCache.scala:101:7] wire io_ptw_gstatus_upie_0 = io_ptw_gstatus_upie; // @[DCache.scala:101:7] wire io_ptw_gstatus_mie_0 = io_ptw_gstatus_mie; // @[DCache.scala:101:7] wire io_ptw_gstatus_hie_0 = io_ptw_gstatus_hie; // @[DCache.scala:101:7] wire io_ptw_gstatus_sie_0 = io_ptw_gstatus_sie; // @[DCache.scala:101:7] wire io_ptw_gstatus_uie_0 = io_ptw_gstatus_uie; // @[DCache.scala:101:7] wire io_ptw_pmp_0_cfg_l_0 = io_ptw_pmp_0_cfg_l; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_0_cfg_a_0 = io_ptw_pmp_0_cfg_a; // @[DCache.scala:101:7] wire io_ptw_pmp_0_cfg_x_0 = io_ptw_pmp_0_cfg_x; // @[DCache.scala:101:7] wire io_ptw_pmp_0_cfg_w_0 = io_ptw_pmp_0_cfg_w; // @[DCache.scala:101:7] wire io_ptw_pmp_0_cfg_r_0 = io_ptw_pmp_0_cfg_r; // @[DCache.scala:101:7] wire [29:0] io_ptw_pmp_0_addr_0 = io_ptw_pmp_0_addr; // @[DCache.scala:101:7] wire [31:0] io_ptw_pmp_0_mask_0 = io_ptw_pmp_0_mask; // @[DCache.scala:101:7] wire io_ptw_pmp_1_cfg_l_0 = io_ptw_pmp_1_cfg_l; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_1_cfg_a_0 = io_ptw_pmp_1_cfg_a; // @[DCache.scala:101:7] wire io_ptw_pmp_1_cfg_x_0 = io_ptw_pmp_1_cfg_x; // @[DCache.scala:101:7] wire io_ptw_pmp_1_cfg_w_0 = io_ptw_pmp_1_cfg_w; // @[DCache.scala:101:7] wire io_ptw_pmp_1_cfg_r_0 = io_ptw_pmp_1_cfg_r; // @[DCache.scala:101:7] wire [29:0] io_ptw_pmp_1_addr_0 = io_ptw_pmp_1_addr; // @[DCache.scala:101:7] wire [31:0] io_ptw_pmp_1_mask_0 = io_ptw_pmp_1_mask; // @[DCache.scala:101:7] wire io_ptw_pmp_2_cfg_l_0 = io_ptw_pmp_2_cfg_l; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_2_cfg_a_0 = io_ptw_pmp_2_cfg_a; // @[DCache.scala:101:7] wire io_ptw_pmp_2_cfg_x_0 = io_ptw_pmp_2_cfg_x; // @[DCache.scala:101:7] wire io_ptw_pmp_2_cfg_w_0 = io_ptw_pmp_2_cfg_w; // @[DCache.scala:101:7] wire io_ptw_pmp_2_cfg_r_0 = io_ptw_pmp_2_cfg_r; // @[DCache.scala:101:7] wire [29:0] io_ptw_pmp_2_addr_0 = io_ptw_pmp_2_addr; // @[DCache.scala:101:7] wire [31:0] io_ptw_pmp_2_mask_0 = io_ptw_pmp_2_mask; // @[DCache.scala:101:7] wire io_ptw_pmp_3_cfg_l_0 = io_ptw_pmp_3_cfg_l; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_3_cfg_a_0 = io_ptw_pmp_3_cfg_a; // @[DCache.scala:101:7] wire io_ptw_pmp_3_cfg_x_0 = io_ptw_pmp_3_cfg_x; // @[DCache.scala:101:7] wire io_ptw_pmp_3_cfg_w_0 = io_ptw_pmp_3_cfg_w; // @[DCache.scala:101:7] wire io_ptw_pmp_3_cfg_r_0 = io_ptw_pmp_3_cfg_r; // @[DCache.scala:101:7] wire [29:0] io_ptw_pmp_3_addr_0 = io_ptw_pmp_3_addr; // @[DCache.scala:101:7] wire [31:0] io_ptw_pmp_3_mask_0 = io_ptw_pmp_3_mask; // @[DCache.scala:101:7] wire io_ptw_pmp_4_cfg_l_0 = io_ptw_pmp_4_cfg_l; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_4_cfg_a_0 = io_ptw_pmp_4_cfg_a; // @[DCache.scala:101:7] wire io_ptw_pmp_4_cfg_x_0 = io_ptw_pmp_4_cfg_x; // @[DCache.scala:101:7] wire io_ptw_pmp_4_cfg_w_0 = io_ptw_pmp_4_cfg_w; // @[DCache.scala:101:7] wire io_ptw_pmp_4_cfg_r_0 = io_ptw_pmp_4_cfg_r; // @[DCache.scala:101:7] wire [29:0] io_ptw_pmp_4_addr_0 = io_ptw_pmp_4_addr; // @[DCache.scala:101:7] wire [31:0] io_ptw_pmp_4_mask_0 = io_ptw_pmp_4_mask; // @[DCache.scala:101:7] wire io_ptw_pmp_5_cfg_l_0 = io_ptw_pmp_5_cfg_l; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_5_cfg_a_0 = io_ptw_pmp_5_cfg_a; // @[DCache.scala:101:7] wire io_ptw_pmp_5_cfg_x_0 = io_ptw_pmp_5_cfg_x; // @[DCache.scala:101:7] wire io_ptw_pmp_5_cfg_w_0 = io_ptw_pmp_5_cfg_w; // @[DCache.scala:101:7] wire io_ptw_pmp_5_cfg_r_0 = io_ptw_pmp_5_cfg_r; // @[DCache.scala:101:7] wire [29:0] io_ptw_pmp_5_addr_0 = io_ptw_pmp_5_addr; // @[DCache.scala:101:7] wire [31:0] io_ptw_pmp_5_mask_0 = io_ptw_pmp_5_mask; // @[DCache.scala:101:7] wire io_ptw_pmp_6_cfg_l_0 = io_ptw_pmp_6_cfg_l; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_6_cfg_a_0 = io_ptw_pmp_6_cfg_a; // @[DCache.scala:101:7] wire io_ptw_pmp_6_cfg_x_0 = io_ptw_pmp_6_cfg_x; // @[DCache.scala:101:7] wire io_ptw_pmp_6_cfg_w_0 = io_ptw_pmp_6_cfg_w; // @[DCache.scala:101:7] wire io_ptw_pmp_6_cfg_r_0 = io_ptw_pmp_6_cfg_r; // @[DCache.scala:101:7] wire [29:0] io_ptw_pmp_6_addr_0 = io_ptw_pmp_6_addr; // @[DCache.scala:101:7] wire [31:0] io_ptw_pmp_6_mask_0 = io_ptw_pmp_6_mask; // @[DCache.scala:101:7] wire io_ptw_pmp_7_cfg_l_0 = io_ptw_pmp_7_cfg_l; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_7_cfg_a_0 = io_ptw_pmp_7_cfg_a; // @[DCache.scala:101:7] wire io_ptw_pmp_7_cfg_x_0 = io_ptw_pmp_7_cfg_x; // @[DCache.scala:101:7] wire io_ptw_pmp_7_cfg_w_0 = io_ptw_pmp_7_cfg_w; // @[DCache.scala:101:7] wire io_ptw_pmp_7_cfg_r_0 = io_ptw_pmp_7_cfg_r; // @[DCache.scala:101:7] wire [29:0] io_ptw_pmp_7_addr_0 = io_ptw_pmp_7_addr; // @[DCache.scala:101:7] wire [31:0] io_ptw_pmp_7_mask_0 = io_ptw_pmp_7_mask; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_0_ren_0 = io_ptw_customCSRs_csrs_0_ren; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_0_wen_0 = io_ptw_customCSRs_csrs_0_wen; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_0_wdata_0 = io_ptw_customCSRs_csrs_0_wdata; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_0_value_0 = io_ptw_customCSRs_csrs_0_value; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_1_ren_0 = io_ptw_customCSRs_csrs_1_ren; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_1_wen_0 = io_ptw_customCSRs_csrs_1_wen; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_1_wdata_0 = io_ptw_customCSRs_csrs_1_wdata; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_1_value_0 = io_ptw_customCSRs_csrs_1_value; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_2_ren_0 = io_ptw_customCSRs_csrs_2_ren; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_2_wen_0 = io_ptw_customCSRs_csrs_2_wen; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_2_wdata_0 = io_ptw_customCSRs_csrs_2_wdata; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_2_value_0 = io_ptw_customCSRs_csrs_2_value; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_3_ren_0 = io_ptw_customCSRs_csrs_3_ren; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_3_wen_0 = io_ptw_customCSRs_csrs_3_wen; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_3_wdata_0 = io_ptw_customCSRs_csrs_3_wdata; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_3_value_0 = io_ptw_customCSRs_csrs_3_value; // @[DCache.scala:101:7] wire _dataArb_io_in_3_valid_T_55 = reset; // @[DCache.scala:1186:11] wire _pstore_drain_opportunistic_T_55 = reset; // @[DCache.scala:1186:11] wire auto_mmio_address_prefix_sink_in = 1'h0; // @[DCache.scala:101:7] wire auto_out_a_bits_source = 1'h0; // @[DCache.scala:101:7] wire auto_out_a_bits_corrupt = 1'h0; // @[DCache.scala:101:7] wire auto_out_d_bits_source = 1'h0; // @[DCache.scala:101:7] wire io_cpu_req_bits_no_alloc = 1'h0; // @[DCache.scala:101:7] wire io_cpu_s2_kill = 1'h0; // @[DCache.scala:101:7] wire io_cpu_s2_xcpt_gf_ld = 1'h0; // @[DCache.scala:101:7] wire io_cpu_s2_xcpt_gf_st = 1'h0; // @[DCache.scala:101:7] wire io_cpu_s2_gpa_is_pte = 1'h0; // @[DCache.scala:101:7] wire io_cpu_perf_release = 1'h0; // @[DCache.scala:101:7] wire io_cpu_perf_tlbMiss = 1'h0; // @[DCache.scala:101:7] wire io_ptw_req_valid = 1'h0; // @[DCache.scala:101:7] wire io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[DCache.scala:101:7] wire io_ptw_status_mbe = 1'h0; // @[DCache.scala:101:7] wire io_ptw_status_sbe = 1'h0; // @[DCache.scala:101:7] wire io_ptw_status_sd_rv32 = 1'h0; // @[DCache.scala:101:7] wire io_ptw_status_tsr = 1'h0; // @[DCache.scala:101:7] wire io_ptw_status_tw = 1'h0; // @[DCache.scala:101:7] wire io_ptw_status_tvm = 1'h0; // @[DCache.scala:101:7] wire io_ptw_status_mxr = 1'h0; // @[DCache.scala:101:7] wire io_ptw_status_sum = 1'h0; // @[DCache.scala:101:7] wire io_ptw_status_mprv = 1'h0; // @[DCache.scala:101:7] wire io_ptw_status_spp = 1'h0; // @[DCache.scala:101:7] wire io_ptw_status_ube = 1'h0; // @[DCache.scala:101:7] wire io_ptw_status_spie = 1'h0; // @[DCache.scala:101:7] wire io_ptw_status_upie = 1'h0; // @[DCache.scala:101:7] wire io_ptw_status_hie = 1'h0; // @[DCache.scala:101:7] wire io_ptw_status_sie = 1'h0; // @[DCache.scala:101:7] wire io_ptw_status_uie = 1'h0; // @[DCache.scala:101:7] wire io_ptw_hstatus_vtsr = 1'h0; // @[DCache.scala:101:7] wire io_ptw_hstatus_vtw = 1'h0; // @[DCache.scala:101:7] wire io_ptw_hstatus_vtvm = 1'h0; // @[DCache.scala:101:7] wire io_ptw_hstatus_hu = 1'h0; // @[DCache.scala:101:7] wire io_ptw_hstatus_spvp = 1'h0; // @[DCache.scala:101:7] wire io_ptw_hstatus_spv = 1'h0; // @[DCache.scala:101:7] wire io_ptw_hstatus_gva = 1'h0; // @[DCache.scala:101:7] wire io_ptw_hstatus_vsbe = 1'h0; // @[DCache.scala:101:7] wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_2_stall = 1'h0; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_2_set = 1'h0; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_3_stall = 1'h0; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_3_set = 1'h0; // @[DCache.scala:101:7] wire io_tlb_port_req_valid = 1'h0; // @[DCache.scala:101:7] wire io_tlb_port_req_bits_passthrough = 1'h0; // @[DCache.scala:101:7] wire io_tlb_port_req_bits_v = 1'h0; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_miss = 1'h0; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_gpa_is_pte = 1'h0; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_gf_ld = 1'h0; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_gf_st = 1'h0; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_gf_inst = 1'h0; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_ma_inst = 1'h0; // @[DCache.scala:101:7] wire io_tlb_port_s2_kill = 1'h0; // @[DCache.scala:101:7] wire nodeOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_d_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire mmioAddressPrefixSinkNodeOptIn = 1'h0; // @[MixedNode.scala:551:17] wire pma_checker_io_req_valid = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_resp_miss = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_resp_gpa_is_pte = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_resp_gf_ld = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_resp_gf_st = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_resp_gf_inst = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_resp_ma_inst = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_sfence_valid = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_sfence_bits_rs1 = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_sfence_bits_rs2 = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_sfence_bits_asid = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_sfence_bits_hv = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_sfence_bits_hg = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_req_ready = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_req_valid = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_req_bits_bits_need_gpa = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_req_bits_bits_vstage1 = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_req_bits_bits_stage2 = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_valid = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_ae_ptw = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_ae_final = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_pf = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_gf = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_hr = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_hw = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_hx = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_pte_d = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_pte_a = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_pte_g = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_pte_u = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_pte_x = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_pte_w = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_pte_r = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_pte_v = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_homogeneous = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_gpa_valid = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_gpa_is_pte = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_debug = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_cease = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_wfi = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_dv = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_v = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_sd = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_mpv = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_gva = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_mbe = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_sbe = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_sd_rv32 = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_tsr = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_tw = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_tvm = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_mxr = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_sum = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_mprv = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_spp = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_mpie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_ube = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_spie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_upie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_mie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_hie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_sie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_uie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_hstatus_vtsr = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_hstatus_vtw = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_hstatus_vtvm = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_hstatus_hu = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_hstatus_spvp = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_hstatus_spv = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_hstatus_gva = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_hstatus_vsbe = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_debug = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_cease = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_wfi = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_dv = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_v = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_sd = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_mpv = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_gva = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_mbe = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_sbe = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_sd_rv32 = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_tsr = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_tw = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_tvm = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_mxr = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_sum = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_mprv = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_spp = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_mpie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_ube = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_spie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_upie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_mie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_hie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_sie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_uie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_0_cfg_l = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_0_cfg_x = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_0_cfg_w = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_0_cfg_r = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_1_cfg_l = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_1_cfg_x = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_1_cfg_w = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_1_cfg_r = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_2_cfg_l = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_2_cfg_x = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_2_cfg_w = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_2_cfg_r = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_3_cfg_l = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_3_cfg_x = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_3_cfg_w = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_3_cfg_r = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_4_cfg_l = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_4_cfg_x = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_4_cfg_w = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_4_cfg_r = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_5_cfg_l = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_5_cfg_x = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_5_cfg_w = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_5_cfg_r = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_6_cfg_l = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_6_cfg_x = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_6_cfg_w = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_6_cfg_r = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_7_cfg_l = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_7_cfg_x = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_7_cfg_w = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_7_cfg_r = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_0_ren = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_0_wen = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_0_set = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_1_ren = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_1_wen = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_1_set = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_2_ren = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_2_wen = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_2_stall = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_2_set = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_3_ren = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_3_wen = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_3_stall = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_3_set = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_kill = 1'h0; // @[DCache.scala:120:32] wire pma_checker_priv_v = 1'h0; // @[TLB.scala:369:34] wire pma_checker__stage1_en_T = 1'h0; // @[TLB.scala:374:41] wire pma_checker_stage1_en = 1'h0; // @[TLB.scala:374:29] wire pma_checker__vstage1_en_T = 1'h0; // @[TLB.scala:376:38] wire pma_checker__vstage1_en_T_1 = 1'h0; // @[TLB.scala:376:68] wire pma_checker_vstage1_en = 1'h0; // @[TLB.scala:376:48] wire pma_checker__stage2_en_T = 1'h0; // @[TLB.scala:378:38] wire pma_checker__stage2_en_T_1 = 1'h0; // @[TLB.scala:378:68] wire pma_checker_stage2_en = 1'h0; // @[TLB.scala:378:48] wire pma_checker__vm_enabled_T = 1'h0; // @[TLB.scala:399:31] wire pma_checker__vm_enabled_T_1 = 1'h0; // @[TLB.scala:399:45] wire pma_checker__vm_enabled_T_2 = 1'h0; // @[TLB.scala:399:64] wire pma_checker_vm_enabled = 1'h0; // @[TLB.scala:399:61] wire pma_checker__vsatp_mode_mismatch_T = 1'h0; // @[TLB.scala:403:52] wire pma_checker__vsatp_mode_mismatch_T_1 = 1'h0; // @[TLB.scala:403:37] wire pma_checker__vsatp_mode_mismatch_T_2 = 1'h0; // @[TLB.scala:403:81] wire pma_checker_vsatp_mode_mismatch = 1'h0; // @[TLB.scala:403:78] wire pma_checker_do_refill = 1'h0; // @[TLB.scala:408:29] wire pma_checker__invalidate_refill_T = 1'h0; // @[package.scala:16:47] wire pma_checker__invalidate_refill_T_1 = 1'h0; // @[package.scala:16:47] wire pma_checker__invalidate_refill_T_2 = 1'h0; // @[package.scala:81:59] wire pma_checker_invalidate_refill = 1'h0; // @[TLB.scala:410:88] wire pma_checker__mpu_ppn_T = 1'h0; // @[TLB.scala:413:32] wire pma_checker__mpu_priv_T_1 = 1'h0; // @[TLB.scala:415:38] wire pma_checker_cacheable = 1'h0; // @[TLB.scala:425:41] wire pma_checker__sector_hits_T = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_8 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_16 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_24 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_32 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_40 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_48 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_56 = 1'h0; // @[package.scala:81:59] wire pma_checker_superpage_hits_0 = 1'h0; // @[TLB.scala:188:18] wire pma_checker_superpage_hits_1 = 1'h0; // @[TLB.scala:188:18] wire pma_checker_superpage_hits_2 = 1'h0; // @[TLB.scala:188:18] wire pma_checker_superpage_hits_3 = 1'h0; // @[TLB.scala:188:18] wire pma_checker__hitsVec_T_5 = 1'h0; // @[TLB.scala:188:18] wire pma_checker_hitsVec_0 = 1'h0; // @[TLB.scala:440:44] wire pma_checker__hitsVec_T_11 = 1'h0; // @[TLB.scala:188:18] wire pma_checker_hitsVec_1 = 1'h0; // @[TLB.scala:440:44] wire pma_checker__hitsVec_T_17 = 1'h0; // @[TLB.scala:188:18] wire pma_checker_hitsVec_2 = 1'h0; // @[TLB.scala:440:44] wire pma_checker__hitsVec_T_23 = 1'h0; // @[TLB.scala:188:18] wire pma_checker_hitsVec_3 = 1'h0; // @[TLB.scala:440:44] wire pma_checker__hitsVec_T_29 = 1'h0; // @[TLB.scala:188:18] wire pma_checker_hitsVec_4 = 1'h0; // @[TLB.scala:440:44] wire pma_checker__hitsVec_T_35 = 1'h0; // @[TLB.scala:188:18] wire pma_checker_hitsVec_5 = 1'h0; // @[TLB.scala:440:44] wire pma_checker__hitsVec_T_41 = 1'h0; // @[TLB.scala:188:18] wire pma_checker_hitsVec_6 = 1'h0; // @[TLB.scala:440:44] wire pma_checker__hitsVec_T_47 = 1'h0; // @[TLB.scala:188:18] wire pma_checker_hitsVec_7 = 1'h0; // @[TLB.scala:440:44] wire pma_checker__hitsVec_T_53 = 1'h0; // @[TLB.scala:188:18] wire pma_checker_hitsVec_8 = 1'h0; // @[TLB.scala:440:44] wire pma_checker__hitsVec_T_59 = 1'h0; // @[TLB.scala:188:18] wire pma_checker_hitsVec_9 = 1'h0; // @[TLB.scala:440:44] wire pma_checker__hitsVec_T_65 = 1'h0; // @[TLB.scala:188:18] wire pma_checker_hitsVec_10 = 1'h0; // @[TLB.scala:440:44] wire pma_checker__hitsVec_T_71 = 1'h0; // @[TLB.scala:188:18] wire pma_checker_hitsVec_11 = 1'h0; // @[TLB.scala:440:44] wire pma_checker_hitsVec_12 = 1'h0; // @[TLB.scala:440:44] wire pma_checker_refill_v = 1'h0; // @[TLB.scala:448:33] wire pma_checker_newEntry_u = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_g = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_ae_ptw = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_ae_final = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_ae_stage2 = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_pf = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_gf = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_sw = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_sx = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_sr = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_hw = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_hx = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_hr = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_c = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_fragmented_superpage = 1'h0; // @[TLB.scala:449:24] wire pma_checker__newEntry_g_T = 1'h0; // @[TLB.scala:453:25] wire pma_checker__newEntry_ae_stage2_T = 1'h0; // @[TLB.scala:456:53] wire pma_checker__newEntry_ae_stage2_T_1 = 1'h0; // @[TLB.scala:456:84] wire pma_checker__newEntry_sr_T_1 = 1'h0; // @[PTW.scala:141:44] wire pma_checker__newEntry_sr_T_2 = 1'h0; // @[PTW.scala:141:38] wire pma_checker__newEntry_sr_T_3 = 1'h0; // @[PTW.scala:141:32] wire pma_checker__newEntry_sr_T_4 = 1'h0; // @[PTW.scala:141:52] wire pma_checker__newEntry_sr_T_5 = 1'h0; // @[PTW.scala:149:35] wire pma_checker__newEntry_sw_T_1 = 1'h0; // @[PTW.scala:141:44] wire pma_checker__newEntry_sw_T_2 = 1'h0; // @[PTW.scala:141:38] wire pma_checker__newEntry_sw_T_3 = 1'h0; // @[PTW.scala:141:32] wire pma_checker__newEntry_sw_T_4 = 1'h0; // @[PTW.scala:141:52] wire pma_checker__newEntry_sw_T_5 = 1'h0; // @[PTW.scala:151:35] wire pma_checker__newEntry_sw_T_6 = 1'h0; // @[PTW.scala:151:40] wire pma_checker__newEntry_sx_T_1 = 1'h0; // @[PTW.scala:141:44] wire pma_checker__newEntry_sx_T_2 = 1'h0; // @[PTW.scala:141:38] wire pma_checker__newEntry_sx_T_3 = 1'h0; // @[PTW.scala:141:32] wire pma_checker__newEntry_sx_T_4 = 1'h0; // @[PTW.scala:141:52] wire pma_checker__newEntry_sx_T_5 = 1'h0; // @[PTW.scala:153:35] wire pma_checker__waddr_T = 1'h0; // @[TLB.scala:477:45] wire pma_checker__superpage_entries_0_level_T = 1'h0; // @[package.scala:163:13] wire pma_checker__superpage_entries_1_level_T = 1'h0; // @[package.scala:163:13] wire pma_checker__superpage_entries_2_level_T = 1'h0; // @[package.scala:163:13] wire pma_checker__superpage_entries_3_level_T = 1'h0; // @[package.scala:163:13] wire pma_checker_sum = 1'h0; // @[TLB.scala:510:16] wire pma_checker__mxr_T = 1'h0; // @[TLB.scala:518:36] wire pma_checker_mxr = 1'h0; // @[TLB.scala:518:31] wire pma_checker__prefetchable_array_T = 1'h0; // @[TLB.scala:547:43] wire pma_checker_cmd_readx = 1'h0; // @[TLB.scala:575:37] wire pma_checker__gf_ld_array_T = 1'h0; // @[TLB.scala:600:32] wire pma_checker__gf_st_array_T = 1'h0; // @[TLB.scala:601:32] wire pma_checker__gpa_hits_hit_mask_T_1 = 1'h0; // @[TLB.scala:606:60] wire pma_checker_tlb_hit_if_not_gpa_miss = 1'h0; // @[TLB.scala:610:43] wire pma_checker_tlb_hit = 1'h0; // @[TLB.scala:611:40] wire pma_checker__tlb_miss_T_1 = 1'h0; // @[TLB.scala:613:29] wire pma_checker__tlb_miss_T_3 = 1'h0; // @[TLB.scala:613:53] wire pma_checker_tlb_miss = 1'h0; // @[TLB.scala:613:64] wire pma_checker_state_vec_0_left_subtree_state_1 = 1'h0; // @[package.scala:163:13] wire pma_checker_state_vec_0_right_subtree_state_1 = 1'h0; // @[Replacement.scala:198:38] wire pma_checker_state_vec_0_left_subtree_state_2 = 1'h0; // @[package.scala:163:13] wire pma_checker_state_vec_0_right_subtree_state_2 = 1'h0; // @[Replacement.scala:198:38] wire pma_checker_state_reg_left_subtree_state = 1'h0; // @[package.scala:163:13] wire pma_checker_state_reg_right_subtree_state = 1'h0; // @[Replacement.scala:198:38] wire pma_checker__multipleHits_T_2 = 1'h0; // @[Misc.scala:181:37] wire pma_checker_multipleHits_leftOne = 1'h0; // @[Misc.scala:178:18] wire pma_checker__multipleHits_T_4 = 1'h0; // @[Misc.scala:181:37] wire pma_checker_multipleHits_leftOne_1 = 1'h0; // @[Misc.scala:178:18] wire pma_checker__multipleHits_T_5 = 1'h0; // @[Misc.scala:182:39] wire pma_checker_multipleHits_rightOne = 1'h0; // @[Misc.scala:178:18] wire pma_checker_multipleHits_rightOne_1 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_6 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_7 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits_rightTwo = 1'h0; // @[Misc.scala:183:49] wire pma_checker_multipleHits_leftOne_2 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_8 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_9 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits_leftTwo = 1'h0; // @[Misc.scala:183:49] wire pma_checker__multipleHits_T_11 = 1'h0; // @[Misc.scala:181:37] wire pma_checker_multipleHits_leftOne_3 = 1'h0; // @[Misc.scala:178:18] wire pma_checker__multipleHits_T_13 = 1'h0; // @[Misc.scala:181:37] wire pma_checker_multipleHits_leftOne_4 = 1'h0; // @[Misc.scala:178:18] wire pma_checker__multipleHits_T_14 = 1'h0; // @[Misc.scala:182:39] wire pma_checker_multipleHits_rightOne_2 = 1'h0; // @[Misc.scala:178:18] wire pma_checker_multipleHits_rightOne_3 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_15 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_16 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits_rightTwo_1 = 1'h0; // @[Misc.scala:183:49] wire pma_checker_multipleHits_rightOne_4 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_17 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_18 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits_rightTwo_2 = 1'h0; // @[Misc.scala:183:49] wire pma_checker_multipleHits_leftOne_5 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_19 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_20 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits_leftTwo_1 = 1'h0; // @[Misc.scala:183:49] wire pma_checker__multipleHits_T_23 = 1'h0; // @[Misc.scala:181:37] wire pma_checker_multipleHits_leftOne_6 = 1'h0; // @[Misc.scala:178:18] wire pma_checker__multipleHits_T_25 = 1'h0; // @[Misc.scala:181:37] wire pma_checker_multipleHits_leftOne_7 = 1'h0; // @[Misc.scala:178:18] wire pma_checker__multipleHits_T_26 = 1'h0; // @[Misc.scala:182:39] wire pma_checker_multipleHits_rightOne_5 = 1'h0; // @[Misc.scala:178:18] wire pma_checker_multipleHits_rightOne_6 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_27 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_28 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits_rightTwo_3 = 1'h0; // @[Misc.scala:183:49] wire pma_checker_multipleHits_leftOne_8 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_29 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_30 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits_leftTwo_2 = 1'h0; // @[Misc.scala:183:49] wire pma_checker__multipleHits_T_33 = 1'h0; // @[Misc.scala:181:37] wire pma_checker_multipleHits_leftOne_9 = 1'h0; // @[Misc.scala:178:18] wire pma_checker__multipleHits_T_34 = 1'h0; // @[Misc.scala:182:39] wire pma_checker_multipleHits_rightOne_7 = 1'h0; // @[Misc.scala:178:18] wire pma_checker_multipleHits_leftOne_10 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_35 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_36 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits_leftTwo_3 = 1'h0; // @[Misc.scala:183:49] wire pma_checker__multipleHits_T_38 = 1'h0; // @[Misc.scala:181:37] wire pma_checker_multipleHits_leftOne_11 = 1'h0; // @[Misc.scala:178:18] wire pma_checker__multipleHits_T_39 = 1'h0; // @[Misc.scala:182:39] wire pma_checker_multipleHits_rightOne_8 = 1'h0; // @[Misc.scala:178:18] wire pma_checker_multipleHits_rightOne_9 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_40 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_41 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits_rightTwo_4 = 1'h0; // @[Misc.scala:183:49] wire pma_checker_multipleHits_rightOne_10 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_42 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_43 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits_rightTwo_5 = 1'h0; // @[Misc.scala:183:49] wire pma_checker_multipleHits_rightOne_11 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_44 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_45 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits_rightTwo_6 = 1'h0; // @[Misc.scala:183:49] wire pma_checker__multipleHits_T_46 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_47 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_48 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits = 1'h0; // @[Misc.scala:183:49] wire pma_checker__io_resp_pf_ld_T = 1'h0; // @[TLB.scala:633:28] wire pma_checker__io_resp_pf_st_T = 1'h0; // @[TLB.scala:634:28] wire pma_checker__io_resp_gf_ld_T = 1'h0; // @[TLB.scala:637:29] wire pma_checker__io_resp_gf_ld_T_2 = 1'h0; // @[TLB.scala:637:66] wire pma_checker__io_resp_gf_ld_T_3 = 1'h0; // @[TLB.scala:637:42] wire pma_checker__io_resp_gf_st_T = 1'h0; // @[TLB.scala:638:29] wire pma_checker__io_resp_gf_st_T_2 = 1'h0; // @[TLB.scala:638:73] wire pma_checker__io_resp_gf_st_T_3 = 1'h0; // @[TLB.scala:638:49] wire pma_checker__io_resp_gf_inst_T_1 = 1'h0; // @[TLB.scala:639:56] wire pma_checker__io_resp_gf_inst_T_2 = 1'h0; // @[TLB.scala:639:30] wire pma_checker__io_resp_miss_T = 1'h0; // @[TLB.scala:651:29] wire pma_checker__io_resp_miss_T_1 = 1'h0; // @[TLB.scala:651:52] wire pma_checker__io_resp_miss_T_2 = 1'h0; // @[TLB.scala:651:64] wire pma_checker__io_resp_gpa_is_pte_T = 1'h0; // @[TLB.scala:655:36] wire pma_checker__io_ptw_req_valid_T = 1'h0; // @[TLB.scala:662:29] wire metaArb_io_in_0_valid = 1'h0; // @[DCache.scala:135:28] wire metaArb_io_in_1_valid = 1'h0; // @[DCache.scala:135:28] wire metaArb_io_in_1_bits_way_en = 1'h0; // @[DCache.scala:135:28] wire metaArb_io_in_4_valid = 1'h0; // @[DCache.scala:135:28] wire metaArb_io_in_5_valid = 1'h0; // @[DCache.scala:135:28] wire metaArb_io_in_5_bits_write = 1'h0; // @[DCache.scala:135:28] wire metaArb_io_in_6_valid = 1'h0; // @[DCache.scala:135:28] wire metaArb_io_in_6_bits_write = 1'h0; // @[DCache.scala:135:28] wire metaArb_io_in_7_bits_write = 1'h0; // @[DCache.scala:135:28] wire metaArb__grant_T = 1'h0; // @[Arbiter.scala:45:68] wire dataArb_io_in_2_valid = 1'h0; // @[DCache.scala:152:28] wire dataArb_io_in_2_bits_write = 1'h0; // @[DCache.scala:152:28] wire dataArb_io_in_3_bits_write = 1'h0; // @[DCache.scala:152:28] wire tl_out_a_bits_source = 1'h0; // @[DCache.scala:159:22] wire tl_out_a_bits_corrupt = 1'h0; // @[DCache.scala:159:22] wire nodeOut_a_deq_bits_source = 1'h0; // @[Decoupled.scala:356:21] wire nodeOut_a_deq_bits_corrupt = 1'h0; // @[Decoupled.scala:356:21] wire tl_out_c_ready = 1'h0; // @[Bundles.scala:265:61] wire tl_out_c_bits_source = 1'h0; // @[Bundles.scala:265:61] wire tl_out_c_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _s1_probe_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _s1_probe_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _s1_probe_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74] wire _s1_probe_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _s1_probe_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _s1_probe_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _s1_probe_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:264:61] wire _s1_probe_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _s1_probe_T = 1'h0; // @[Decoupled.scala:51:35] wire _probe_bits_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _probe_bits_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _probe_bits_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74] wire _probe_bits_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _probe_bits_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _probe_bits_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _probe_bits_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:264:61] wire _probe_bits_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _probe_bits_WIRE_2_ready = 1'h0; // @[Bundles.scala:264:74] wire _probe_bits_WIRE_2_valid = 1'h0; // @[Bundles.scala:264:74] wire _probe_bits_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:264:74] wire _probe_bits_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _probe_bits_WIRE_3_ready = 1'h0; // @[Bundles.scala:264:61] wire _probe_bits_WIRE_3_valid = 1'h0; // @[Bundles.scala:264:61] wire _probe_bits_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:264:61] wire _probe_bits_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _probe_bits_T = 1'h0; // @[Decoupled.scala:51:35] wire _s1_tlb_req_valid_T = 1'h0; // @[Decoupled.scala:51:35] wire s0_req_no_alloc = 1'h0; // @[DCache.scala:192:24] wire s1_waw_hazard = 1'h0; // @[DCache.scala:216:27] wire _inWriteback_T = 1'h0; // @[package.scala:16:47] wire _inWriteback_T_1 = 1'h0; // @[package.scala:16:47] wire inWriteback = 1'h0; // @[package.scala:81:59] wire _uncachedInFlight_WIRE_0 = 1'h0; // @[DCache.scala:236:41] wire _dataArb_io_in_3_valid_res_T_4 = 1'h0; // @[DCache.scala:1185:58] wire _dataArb_io_in_3_valid_T_49 = 1'h0; // @[DCache.scala:1191:57] wire _s1_did_read_T_49 = 1'h0; // @[DCache.scala:1191:57] wire _tlb_io_kill_T = 1'h0; // @[DCache.scala:272:53] wire _tlb_io_kill_T_1 = 1'h0; // @[DCache.scala:272:33] wire s1_victim_way = 1'h0; // @[DCache.scala:299:27] wire _releaseInFlight_T = 1'h0; // @[DCache.scala:334:34] wire _releaseInFlight_T_1 = 1'h0; // @[DCache.scala:334:63] wire releaseInFlight = 1'h0; // @[DCache.scala:334:46] wire _s2_pma_T_miss = 1'h0; // @[DCache.scala:349:18] wire _s2_pma_T_gpa_is_pte = 1'h0; // @[DCache.scala:349:18] wire _s2_pma_T_gf_ld = 1'h0; // @[DCache.scala:349:18] wire _s2_pma_T_gf_st = 1'h0; // @[DCache.scala:349:18] wire _s2_pma_T_gf_inst = 1'h0; // @[DCache.scala:349:18] wire _s2_pma_T_ma_inst = 1'h0; // @[DCache.scala:349:18] wire s2_meta_error_uncorrectable = 1'h0; // @[DCache.scala:360:66] wire _s2_meta_error_T = 1'h0; // @[DCache.scala:362:53] wire s2_meta_error = 1'h0; // @[DCache.scala:362:83] wire s2_store_merge = 1'h0; // @[DCache.scala:388:28] wire _r_T_26 = 1'h0; // @[Misc.scala:35:9] wire _r_T_29 = 1'h0; // @[Misc.scala:35:9] wire _r_T_32 = 1'h0; // @[Misc.scala:35:9] wire _r_T_35 = 1'h0; // @[Misc.scala:35:9] wire _r_T_38 = 1'h0; // @[Misc.scala:35:9] wire _s2_data_error_T = 1'h0; // @[ECC.scala:15:27] wire _s2_data_error_T_1 = 1'h0; // @[ECC.scala:15:27] wire _s2_data_error_T_2 = 1'h0; // @[ECC.scala:15:27] wire _s2_data_error_T_3 = 1'h0; // @[ECC.scala:15:27] wire _s2_data_error_T_4 = 1'h0; // @[ECC.scala:15:27] wire _s2_data_error_T_5 = 1'h0; // @[ECC.scala:15:27] wire _s2_data_error_T_6 = 1'h0; // @[ECC.scala:15:27] wire _s2_data_error_T_7 = 1'h0; // @[ECC.scala:15:27] wire _s2_data_error_T_8 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_T_9 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_T_10 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_T_11 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_T_12 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_T_13 = 1'h0; // @[package.scala:81:59] wire s2_data_error = 1'h0; // @[package.scala:81:59] wire _s2_data_error_uncorrectable_T = 1'h0; // @[package.scala:81:59] wire _s2_data_error_uncorrectable_T_1 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_uncorrectable_T_2 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_uncorrectable_T_3 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_uncorrectable_T_4 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_uncorrectable_T_5 = 1'h0; // @[package.scala:81:59] wire s2_data_error_uncorrectable = 1'h0; // @[package.scala:81:59] wire s2_valid_data_error = 1'h0; // @[DCache.scala:421:63] wire s2_want_victimize = 1'h0; // @[DCache.scala:427:52] wire s2_cannot_victimize = 1'h0; // @[DCache.scala:428:45] wire s2_victimize = 1'h0; // @[DCache.scala:429:40] wire _r_T_73 = 1'h0; // @[Misc.scala:38:9] wire _r_T_77 = 1'h0; // @[Misc.scala:38:9] wire _r_T_81 = 1'h0; // @[Misc.scala:38:9] wire _r_T_119 = 1'h0; // @[Metadata.scala:140:24] wire _r_T_121 = 1'h0; // @[Metadata.scala:140:24] wire _r_T_137 = 1'h0; // @[Misc.scala:38:9] wire _r_T_141 = 1'h0; // @[Misc.scala:38:9] wire _r_T_145 = 1'h0; // @[Misc.scala:38:9] wire _s2_dont_nack_misc_T_2 = 1'h0; // @[DCache.scala:442:23] wire _s2_dont_nack_misc_T_3 = 1'h0; // @[DCache.scala:442:43] wire _s2_dont_nack_misc_T_5 = 1'h0; // @[DCache.scala:442:54] wire _s2_dont_nack_misc_T_6 = 1'h0; // @[DCache.scala:443:23] wire _s2_dont_nack_misc_T_8 = 1'h0; // @[DCache.scala:443:44] wire _s2_dont_nack_misc_T_9 = 1'h0; // @[DCache.scala:442:67] wire _s2_first_meta_corrected_T = 1'h0; // @[Mux.scala:52:83] wire _metaArb_io_in_1_valid_T_2 = 1'h0; // @[DCache.scala:450:43] wire _metaArb_io_in_1_bits_way_en_T = 1'h0; // @[OneHot.scala:85:71] wire _metaArb_io_in_1_bits_way_en_T_1 = 1'h0; // @[Mux.scala:50:70] wire _metaArb_io_in_1_bits_way_en_T_2 = 1'h0; // @[DCache.scala:452:69] wire _metaArb_io_in_1_bits_way_en_T_3 = 1'h0; // @[DCache.scala:452:64] wire s2_lr = 1'h0; // @[DCache.scala:470:56] wire s2_sc = 1'h0; // @[DCache.scala:471:56] wire s2_sc_fail = 1'h0; // @[DCache.scala:477:26] wire _s2_correct_T_1 = 1'h0; // @[DCache.scala:487:34] wire _s2_correct_T_4 = 1'h0; // @[DCache.scala:487:55] wire s2_correct = 1'h0; // @[DCache.scala:487:97] wire _s2_valid_correct_T = 1'h0; // @[DCache.scala:489:60] wire s2_valid_correct = 1'h0; // @[DCache.scala:489:74] wire _pstore1_rmw_T_49 = 1'h0; // @[DCache.scala:1191:57] wire pstore1_merge_likely = 1'h0; // @[DCache.scala:499:68] wire pstore1_merge = 1'h0; // @[DCache.scala:500:38] wire _pstore_drain_opportunistic_res_T_4 = 1'h0; // @[DCache.scala:1185:58] wire _pstore_drain_opportunistic_T_49 = 1'h0; // @[DCache.scala:1191:57] wire _pstore_drain_opportunistic_T_60 = 1'h0; // @[DCache.scala:502:106] wire pstore_drain_s2_kill = 1'h0; // @[DCache.scala:515:25] wire _pstore2_storegen_data_T_2 = 1'h0; // @[DCache.scala:528:95] wire _pstore2_storegen_data_T_6 = 1'h0; // @[DCache.scala:528:95] wire _pstore2_storegen_data_T_10 = 1'h0; // @[DCache.scala:528:95] wire _pstore2_storegen_data_T_14 = 1'h0; // @[DCache.scala:528:95] wire _pstore2_storegen_data_T_18 = 1'h0; // @[DCache.scala:528:95] wire _pstore2_storegen_data_T_22 = 1'h0; // @[DCache.scala:528:95] wire _pstore2_storegen_data_T_26 = 1'h0; // @[DCache.scala:528:95] wire _pstore2_storegen_data_T_30 = 1'h0; // @[DCache.scala:528:95] wire dataArb_io_in_0_valid_s2_kill = 1'h0; // @[DCache.scala:515:25] wire _dataArb_io_in_0_bits_wordMask_T_1 = 1'h0; // @[DCache.scala:555:20] wire _io_cpu_s2_nack_cause_raw_T_2 = 1'h0; // @[DCache.scala:574:57] wire get_source = 1'h0; // @[Edges.scala:460:17] wire get_corrupt = 1'h0; // @[Edges.scala:460:17] wire _put_legal_T_44 = 1'h0; // @[Parameters.scala:684:29] wire _put_legal_T_50 = 1'h0; // @[Parameters.scala:684:54] wire put_source = 1'h0; // @[Edges.scala:480:17] wire put_corrupt = 1'h0; // @[Edges.scala:480:17] wire _putpartial_legal_T_44 = 1'h0; // @[Parameters.scala:684:29] wire _putpartial_legal_T_50 = 1'h0; // @[Parameters.scala:684:54] wire putpartial_source = 1'h0; // @[Edges.scala:500:17] wire putpartial_corrupt = 1'h0; // @[Edges.scala:500:17] wire _atomics_WIRE_source = 1'h0; // @[DCache.scala:587:51] wire _atomics_WIRE_corrupt = 1'h0; // @[DCache.scala:587:51] wire _atomics_WIRE_1_source = 1'h0; // @[DCache.scala:587:38] wire _atomics_WIRE_1_corrupt = 1'h0; // @[DCache.scala:587:38] wire _atomics_legal_T_22 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_28 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_source = 1'h0; // @[Edges.scala:534:17] wire atomics_a_corrupt = 1'h0; // @[Edges.scala:534:17] wire _atomics_legal_T_52 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_58 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_1_source = 1'h0; // @[Edges.scala:534:17] wire atomics_a_1_corrupt = 1'h0; // @[Edges.scala:534:17] wire _atomics_legal_T_82 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_88 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_2_source = 1'h0; // @[Edges.scala:534:17] wire atomics_a_2_corrupt = 1'h0; // @[Edges.scala:534:17] wire _atomics_legal_T_112 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_118 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_3_source = 1'h0; // @[Edges.scala:534:17] wire atomics_a_3_corrupt = 1'h0; // @[Edges.scala:534:17] wire _atomics_legal_T_142 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_148 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_4_source = 1'h0; // @[Edges.scala:517:17] wire atomics_a_4_corrupt = 1'h0; // @[Edges.scala:517:17] wire _atomics_legal_T_172 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_178 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_5_source = 1'h0; // @[Edges.scala:517:17] wire atomics_a_5_corrupt = 1'h0; // @[Edges.scala:517:17] wire _atomics_legal_T_202 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_208 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_6_source = 1'h0; // @[Edges.scala:517:17] wire atomics_a_6_corrupt = 1'h0; // @[Edges.scala:517:17] wire _atomics_legal_T_232 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_238 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_7_source = 1'h0; // @[Edges.scala:517:17] wire atomics_a_7_corrupt = 1'h0; // @[Edges.scala:517:17] wire _atomics_legal_T_262 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_268 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_8_source = 1'h0; // @[Edges.scala:517:17] wire atomics_a_8_corrupt = 1'h0; // @[Edges.scala:517:17] wire _atomics_T_1_source = 1'h0; // @[DCache.scala:587:81] wire _atomics_T_1_corrupt = 1'h0; // @[DCache.scala:587:81] wire _atomics_T_3_source = 1'h0; // @[DCache.scala:587:81] wire _atomics_T_3_corrupt = 1'h0; // @[DCache.scala:587:81] wire _atomics_T_5_source = 1'h0; // @[DCache.scala:587:81] wire _atomics_T_5_corrupt = 1'h0; // @[DCache.scala:587:81] wire _atomics_T_7_source = 1'h0; // @[DCache.scala:587:81] wire _atomics_T_7_corrupt = 1'h0; // @[DCache.scala:587:81] wire _atomics_T_9_source = 1'h0; // @[DCache.scala:587:81] wire _atomics_T_9_corrupt = 1'h0; // @[DCache.scala:587:81] wire _atomics_T_11_source = 1'h0; // @[DCache.scala:587:81] wire _atomics_T_11_corrupt = 1'h0; // @[DCache.scala:587:81] wire _atomics_T_13_source = 1'h0; // @[DCache.scala:587:81] wire _atomics_T_13_corrupt = 1'h0; // @[DCache.scala:587:81] wire _atomics_T_15_source = 1'h0; // @[DCache.scala:587:81] wire _atomics_T_15_corrupt = 1'h0; // @[DCache.scala:587:81] wire atomics_source = 1'h0; // @[DCache.scala:587:81] wire atomics_corrupt = 1'h0; // @[DCache.scala:587:81] wire _tl_out_a_valid_T_4 = 1'h0; // @[DCache.scala:606:27] wire _tl_out_a_valid_T_8 = 1'h0; // @[DCache.scala:607:44] wire _tl_out_a_valid_T_9 = 1'h0; // @[DCache.scala:607:65] wire _tl_out_a_bits_WIRE_source = 1'h0; // @[DCache.scala:1209:67] wire _tl_out_a_bits_WIRE_corrupt = 1'h0; // @[DCache.scala:1209:67] wire _tl_out_a_bits_WIRE_1_source = 1'h0; // @[DCache.scala:1209:54] wire _tl_out_a_bits_WIRE_1_corrupt = 1'h0; // @[DCache.scala:1209:54] wire _tl_out_a_bits_T_4_source = 1'h0; // @[DCache.scala:611:8] wire _tl_out_a_bits_T_4_corrupt = 1'h0; // @[DCache.scala:611:8] wire _tl_out_a_bits_T_5_source = 1'h0; // @[DCache.scala:610:8] wire _tl_out_a_bits_T_5_corrupt = 1'h0; // @[DCache.scala:610:8] wire _tl_out_a_bits_T_6_source = 1'h0; // @[DCache.scala:609:8] wire _tl_out_a_bits_T_6_corrupt = 1'h0; // @[DCache.scala:609:8] wire _tl_out_a_bits_T_7_source = 1'h0; // @[DCache.scala:608:23] wire _tl_out_a_bits_T_7_corrupt = 1'h0; // @[DCache.scala:608:23] wire _tl_d_data_encoded_T_12 = 1'h0; // @[DCache.scala:663:129] wire _tl_d_data_encoded_T_13 = 1'h0; // @[DCache.scala:663:126] wire _grantIsCached_T = 1'h0; // @[package.scala:16:47] wire _grantIsCached_T_1 = 1'h0; // @[package.scala:16:47] wire grantIsVoluntary = 1'h0; // @[DCache.scala:665:32] wire grantIsRefill = 1'h0; // @[DCache.scala:666:29] wire _canAcceptCachedGrant_T = 1'h0; // @[package.scala:16:47] wire _canAcceptCachedGrant_T_1 = 1'h0; // @[package.scala:16:47] wire _canAcceptCachedGrant_T_2 = 1'h0; // @[package.scala:16:47] wire _canAcceptCachedGrant_T_3 = 1'h0; // @[package.scala:81:59] wire _canAcceptCachedGrant_T_4 = 1'h0; // @[package.scala:81:59] wire _nodeOut_d_ready_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _nodeOut_d_ready_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _nodeOut_d_ready_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _nodeOut_d_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _nodeOut_d_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _nodeOut_d_ready_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _block_probe_for_pending_release_ack_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _block_probe_for_pending_release_ack_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _block_probe_for_pending_release_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74] wire _block_probe_for_pending_release_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _block_probe_for_pending_release_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _block_probe_for_pending_release_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _block_probe_for_pending_release_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:264:61] wire _block_probe_for_pending_release_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire block_probe_for_pending_release_ack = 1'h0; // @[DCache.scala:767:62] wire _block_probe_for_ordering_T = 1'h0; // @[DCache.scala:768:50] wire _metaArb_io_in_6_valid_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _metaArb_io_in_6_valid_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _metaArb_io_in_6_valid_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74] wire _metaArb_io_in_6_valid_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _metaArb_io_in_6_valid_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _metaArb_io_in_6_valid_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _metaArb_io_in_6_valid_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:264:61] wire _metaArb_io_in_6_valid_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _metaArb_io_in_6_valid_T_2 = 1'h0; // @[DCache.scala:769:44] wire _metaArb_io_in_6_bits_idx_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _metaArb_io_in_6_bits_idx_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _metaArb_io_in_6_bits_idx_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74] wire _metaArb_io_in_6_bits_idx_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _metaArb_io_in_6_bits_idx_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _metaArb_io_in_6_bits_idx_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _metaArb_io_in_6_bits_idx_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:264:61] wire _metaArb_io_in_6_bits_idx_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _metaArb_io_in_6_bits_addr_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _metaArb_io_in_6_bits_addr_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _metaArb_io_in_6_bits_addr_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74] wire _metaArb_io_in_6_bits_addr_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _metaArb_io_in_6_bits_addr_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _metaArb_io_in_6_bits_addr_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _metaArb_io_in_6_bits_addr_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:264:61] wire _metaArb_io_in_6_bits_addr_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire r_beats1_opdata_1 = 1'h0; // @[Edges.scala:102:36] wire _r_last_T_2 = 1'h0; // @[Edges.scala:232:25] wire releaseDone = 1'h0; // @[Edges.scala:233:22] wire _s1_release_data_valid_T = 1'h0; // @[Decoupled.scala:51:35] wire _s2_release_data_valid_T_1 = 1'h0; // @[DCache.scala:802:61] wire _releaseRejected_T = 1'h0; // @[Decoupled.scala:51:35] wire nackResponseMessage_source = 1'h0; // @[Edges.scala:416:17] wire nackResponseMessage_corrupt = 1'h0; // @[Edges.scala:416:17] wire cleanReleaseMessage_source = 1'h0; // @[Edges.scala:416:17] wire cleanReleaseMessage_corrupt = 1'h0; // @[Edges.scala:416:17] wire dirtyReleaseMessage_source = 1'h0; // @[Edges.scala:433:17] wire dirtyReleaseMessage_corrupt = 1'h0; // @[Edges.scala:433:17] wire _tl_out_c_valid_T = 1'h0; // @[DCache.scala:810:48] wire _tl_out_c_valid_T_1 = 1'h0; // @[DCache.scala:810:91] wire _tl_out_c_valid_T_2 = 1'h0; // @[DCache.scala:810:74] wire _tl_out_c_valid_T_4 = 1'h0; // @[DCache.scala:810:130] wire _dataArb_io_in_2_valid_T_1 = 1'h0; // @[DCache.scala:900:41] wire _metaArb_io_in_4_valid_T = 1'h0; // @[package.scala:16:47] wire _metaArb_io_in_4_valid_T_1 = 1'h0; // @[package.scala:16:47] wire _metaArb_io_in_4_valid_T_2 = 1'h0; // @[package.scala:81:59] wire _io_cpu_s2_xcpt_WIRE_miss = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_gpa_is_pte = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_pf_ld = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_pf_st = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_pf_inst = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_gf_ld = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_gf_st = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_gf_inst = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_ae_ld = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_ae_st = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_ae_inst = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_ma_ld = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_ma_st = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_ma_inst = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_cacheable = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_must_alloc = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_prefetchable = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_T_miss = 1'h0; // @[DCache.scala:933:24] wire _io_cpu_s2_xcpt_T_gpa_is_pte = 1'h0; // @[DCache.scala:933:24] wire _io_cpu_s2_xcpt_T_gf_ld = 1'h0; // @[DCache.scala:933:24] wire _io_cpu_s2_xcpt_T_gf_st = 1'h0; // @[DCache.scala:933:24] wire _io_cpu_s2_xcpt_T_gf_inst = 1'h0; // @[DCache.scala:933:24] wire _io_cpu_s2_xcpt_T_ma_inst = 1'h0; // @[DCache.scala:933:24] wire _s2_data_word_possibly_uncached_T = 1'h0; // @[DCache.scala:972:73] wire io_cpu_resp_bits_data_doZero = 1'h0; // @[AMOALU.scala:43:31] wire io_cpu_resp_bits_data_doZero_1 = 1'h0; // @[AMOALU.scala:43:31] wire io_cpu_resp_bits_data_doZero_2 = 1'h0; // @[AMOALU.scala:43:31] wire io_cpu_resp_bits_data_word_bypass_doZero = 1'h0; // @[AMOALU.scala:43:31] wire _flushDone_T = 1'h0; // @[DCache.scala:1010:37] wire flushDone = 1'h0; // @[DCache.scala:1010:57] wire _s1_flush_valid_T = 1'h0; // @[Decoupled.scala:51:35] wire _s1_flush_valid_T_2 = 1'h0; // @[DCache.scala:1014:43] wire _s1_flush_valid_T_4 = 1'h0; // @[DCache.scala:1014:62] wire _s1_flush_valid_T_6 = 1'h0; // @[DCache.scala:1014:93] wire _s1_flush_valid_T_8 = 1'h0; // @[DCache.scala:1014:122] wire _metaArb_io_in_5_valid_T = 1'h0; // @[DCache.scala:1015:41] wire _metaArb_io_in_5_valid_T_1 = 1'h0; // @[DCache.scala:1015:38] wire _clock_en_reg_T_14 = 1'h0; // @[DCache.scala:1069:19] wire _clock_en_reg_T_17 = 1'h0; // @[DCache.scala:1070:25] wire _clock_en_reg_T_19 = 1'h0; // @[DCache.scala:1071:5] wire _io_cpu_perf_release_T = 1'h0; // @[Decoupled.scala:51:35] wire io_cpu_perf_release_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _io_cpu_perf_release_last_T = 1'h0; // @[Edges.scala:232:25] wire io_cpu_perf_release_done = 1'h0; // @[Edges.scala:233:22] wire _io_cpu_perf_tlbMiss_T = 1'h0; // @[Decoupled.scala:51:35] wire _io_cpu_perf_canAcceptLoadThenLoad_T_50 = 1'h0; // @[DCache.scala:1191:57] wire io_cpu_clock_enabled = 1'h1; // @[DCache.scala:101:7] wire io_ptw_req_bits_valid = 1'h1; // @[DCache.scala:101:7] wire io_tlb_port_req_ready = 1'h1; // @[DCache.scala:101:7] wire pma_checker_io_req_ready = 1'h1; // @[DCache.scala:120:32] wire pma_checker_io_req_bits_passthrough = 1'h1; // @[DCache.scala:120:32] wire pma_checker_io_ptw_req_bits_valid = 1'h1; // @[DCache.scala:120:32] wire pma_checker__mpu_priv_T = 1'h1; // @[TLB.scala:415:52] wire pma_checker__homogeneous_T_47 = 1'h1; // @[TLBPermissions.scala:87:22] wire pma_checker__sector_hits_T_6 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__sector_hits_T_14 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__sector_hits_T_22 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__sector_hits_T_30 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__sector_hits_T_38 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__sector_hits_T_46 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__sector_hits_T_54 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__sector_hits_T_62 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__superpage_hits_T_3 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__superpage_hits_T_8 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__superpage_hits_T_13 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__superpage_hits_T_18 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__hitsVec_T_3 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__hitsVec_T_9 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__hitsVec_T_15 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__hitsVec_T_21 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__hitsVec_T_27 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__hitsVec_T_33 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__hitsVec_T_39 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__hitsVec_T_45 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__hitsVec_T_51 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__hitsVec_T_57 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__hitsVec_T_63 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__hitsVec_T_69 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__hitsVec_T_75 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__hits_T = 1'h1; // @[TLB.scala:442:18] wire pma_checker__newEntry_sr_T = 1'h1; // @[PTW.scala:141:47] wire pma_checker__newEntry_sw_T = 1'h1; // @[PTW.scala:141:47] wire pma_checker__newEntry_sx_T = 1'h1; // @[PTW.scala:141:47] wire pma_checker__ppn_T = 1'h1; // @[TLB.scala:502:30] wire pma_checker__stage1_bypass_T_1 = 1'h1; // @[TLB.scala:517:83] wire pma_checker__stage2_bypass_T = 1'h1; // @[TLB.scala:523:42] wire pma_checker__gpa_hits_hit_mask_T_3 = 1'h1; // @[TLB.scala:606:107] wire pma_checker__tlb_miss_T = 1'h1; // @[TLB.scala:613:32] wire pma_checker__tlb_miss_T_2 = 1'h1; // @[TLB.scala:613:56] wire pma_checker__tlb_miss_T_4 = 1'h1; // @[TLB.scala:613:67] wire pma_checker__io_req_ready_T = 1'h1; // @[TLB.scala:631:25] wire pma_checker__io_resp_gpa_page_T = 1'h1; // @[TLB.scala:657:20] wire pma_checker__io_ptw_req_bits_valid_T = 1'h1; // @[TLB.scala:663:28] wire metaArb_io_in_0_ready = 1'h1; // @[DCache.scala:135:28] wire metaArb_io_in_0_bits_write = 1'h1; // @[DCache.scala:135:28] wire metaArb_io_in_0_bits_way_en = 1'h1; // @[DCache.scala:135:28] wire metaArb_io_in_1_ready = 1'h1; // @[DCache.scala:135:28] wire metaArb_io_in_1_bits_write = 1'h1; // @[DCache.scala:135:28] wire metaArb_io_in_2_ready = 1'h1; // @[DCache.scala:135:28] wire metaArb_io_in_2_bits_write = 1'h1; // @[DCache.scala:135:28] wire metaArb_io_in_3_bits_write = 1'h1; // @[DCache.scala:135:28] wire metaArb_io_in_4_bits_write = 1'h1; // @[DCache.scala:135:28] wire metaArb_io_out_ready = 1'h1; // @[DCache.scala:135:28] wire metaArb_grant_1 = 1'h1; // @[Arbiter.scala:45:78] wire metaArb_grant_2 = 1'h1; // @[Arbiter.scala:45:78] wire metaArb__io_in_0_ready_T = 1'h1; // @[Arbiter.scala:153:19] wire metaArb__io_in_1_ready_T = 1'h1; // @[Arbiter.scala:153:19] wire metaArb__io_in_2_ready_T = 1'h1; // @[Arbiter.scala:153:19] wire dataArb_io_in_0_ready = 1'h1; // @[DCache.scala:152:28] wire dataArb_io_in_2_bits_wordMask = 1'h1; // @[DCache.scala:152:28] wire dataArb_io_in_2_bits_way_en = 1'h1; // @[DCache.scala:152:28] wire dataArb_io_in_3_bits_wordMask = 1'h1; // @[DCache.scala:152:28] wire dataArb_io_in_3_bits_way_en = 1'h1; // @[DCache.scala:152:28] wire dataArb_io_out_ready = 1'h1; // @[DCache.scala:152:28] wire dataArb__io_in_0_ready_T = 1'h1; // @[Arbiter.scala:153:19] wire _io_cpu_req_ready_T = 1'h1; // @[DCache.scala:233:38] wire _dataArb_io_in_3_bits_way_en_T = 1'h1; // @[DCache.scala:257:35] wire _s2_valid_not_killed_T = 1'h1; // @[DCache.scala:338:48] wire _s2_flush_valid_T = 1'h1; // @[DCache.scala:363:54] wire _s2_valid_hit_maybe_flush_pre_data_ecc_and_waw_T = 1'h1; // @[DCache.scala:397:74] wire _s2_valid_hit_pre_data_ecc_and_waw_T_1 = 1'h1; // @[DCache.scala:418:108] wire _s2_valid_hit_pre_data_ecc_T = 1'h1; // @[DCache.scala:420:73] wire _s2_valid_hit_pre_data_ecc_T_1 = 1'h1; // @[DCache.scala:420:88] wire _s2_valid_hit_T = 1'h1; // @[DCache.scala:422:51] wire _s2_valid_miss_T_1 = 1'h1; // @[DCache.scala:423:58] wire _s2_victimize_T = 1'h1; // @[DCache.scala:429:43] wire _s2_victim_tag_T_2 = 1'h1; // @[Mux.scala:32:36] wire _s2_victim_state_T = 1'h1; // @[Mux.scala:32:36] wire _r_T_117 = 1'h1; // @[Metadata.scala:140:24] wire _s2_dont_nack_misc_T = 1'h1; // @[DCache.scala:441:46] wire _s2_dont_nack_misc_T_4 = 1'h1; // @[DCache.scala:442:57] wire _metaArb_io_in_2_bits_write_T = 1'h1; // @[DCache.scala:463:34] wire _s2_valid_correct_T_1 = 1'h1; // @[DCache.scala:489:77] wire _pstore1_merge_T_1 = 1'h1; // @[DCache.scala:490:61] wire _pstore1_merge_T_3 = 1'h1; // @[DCache.scala:491:51] wire _pstore_drain_opportunistic_T_61 = 1'h1; // @[DCache.scala:502:95] wire _pstore1_valid_T_1 = 1'h1; // @[DCache.scala:490:61] wire _pstore1_valid_T_3 = 1'h1; // @[DCache.scala:491:51] wire _pstore_drain_T = 1'h1; // @[DCache.scala:516:5] wire _pstore_drain_T_3 = 1'h1; // @[DCache.scala:506:87] wire _pstore1_held_T_1 = 1'h1; // @[DCache.scala:490:61] wire _pstore1_held_T_3 = 1'h1; // @[DCache.scala:491:51] wire _pstore1_held_T_5 = 1'h1; // @[DCache.scala:521:38] wire _dataArb_io_in_0_valid_T = 1'h1; // @[DCache.scala:516:5] wire _dataArb_io_in_0_valid_T_3 = 1'h1; // @[DCache.scala:506:87] wire _dataArb_io_in_0_bits_wordMask_T = 1'h1; // @[DCache.scala:555:20] wire _io_cpu_s2_nack_cause_raw_T = 1'h1; // @[DCache.scala:574:59] wire _io_cpu_s2_nack_cause_raw_T_1 = 1'h1; // @[DCache.scala:574:74] wire _get_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _get_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _get_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _get_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _get_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _get_legal_T_11 = 1'h1; // @[Parameters.scala:92:38] wire _get_legal_T_12 = 1'h1; // @[Parameters.scala:92:33] wire _get_legal_T_13 = 1'h1; // @[Parameters.scala:684:29] wire _put_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _put_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _put_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _put_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _put_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _put_legal_T_11 = 1'h1; // @[Parameters.scala:92:38] wire _put_legal_T_12 = 1'h1; // @[Parameters.scala:92:33] wire _put_legal_T_13 = 1'h1; // @[Parameters.scala:684:29] wire _putpartial_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _putpartial_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _putpartial_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _putpartial_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _putpartial_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _putpartial_legal_T_11 = 1'h1; // @[Parameters.scala:92:38] wire _putpartial_legal_T_12 = 1'h1; // @[Parameters.scala:92:33] wire _putpartial_legal_T_13 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_30 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_31 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_32 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_33 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_60 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_61 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_62 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_63 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_90 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_91 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_92 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_93 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_120 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_121 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_122 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_123 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_150 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_151 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_152 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_153 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_180 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_181 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_182 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_183 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_210 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_211 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_212 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_213 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_240 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_241 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_242 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_243 = 1'h1; // @[Parameters.scala:684:29] wire _tl_out_a_valid_T = 1'h1; // @[DCache.scala:603:21] wire _tl_out_a_valid_T_5 = 1'h1; // @[DCache.scala:606:8] wire _tl_out_a_valid_T_7 = 1'h1; // @[DCache.scala:607:47] wire a_sel = 1'h1; // @[DCache.scala:630:66] wire canAcceptCachedGrant = 1'h1; // @[DCache.scala:670:30] wire uncachedRespIdxOH = 1'h1; // @[DCache.scala:672:90] wire _uncachedResp_T = 1'h1; // @[Mux.scala:32:36] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _r_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire c_last = 1'h1; // @[Edges.scala:232:33] wire _releaseRejected_T_1 = 1'h1; // @[DCache.scala:803:47] wire _tl_out_c_valid_T_5 = 1'h1; // @[DCache.scala:810:120] wire _dataArb_io_in_2_bits_wordMask_T = 1'h1; // @[DCache.scala:904:37] wire _dataArb_io_in_2_bits_way_en_T = 1'h1; // @[DCache.scala:906:35] wire _io_cpu_resp_valid_T_1 = 1'h1; // @[DCache.scala:949:73] wire _io_cpu_replay_next_T_2 = 1'h1; // @[DCache.scala:950:65] wire _s1_flush_valid_T_5 = 1'h1; // @[DCache.scala:1014:110] wire _s1_flush_valid_T_7 = 1'h1; // @[DCache.scala:1014:125] wire _metaArb_io_in_0_bits_way_en_T = 1'h1; // @[DCache.scala:1049:35] wire _clock_en_reg_T = 1'h1; // @[DCache.scala:1060:19] wire _clock_en_reg_T_2 = 1'h1; // @[DCache.scala:1060:44] wire _clock_en_reg_T_3 = 1'h1; // @[DCache.scala:1061:46] wire _clock_en_reg_T_4 = 1'h1; // @[DCache.scala:1062:31] wire _clock_en_reg_T_5 = 1'h1; // @[DCache.scala:1063:26] wire _clock_en_reg_T_6 = 1'h1; // @[DCache.scala:1064:14] wire _clock_en_reg_T_7 = 1'h1; // @[DCache.scala:1064:26] wire _clock_en_reg_T_8 = 1'h1; // @[DCache.scala:1065:14] wire _clock_en_reg_T_9 = 1'h1; // @[DCache.scala:1065:26] wire _clock_en_reg_T_10 = 1'h1; // @[DCache.scala:1066:27] wire _clock_en_reg_T_11 = 1'h1; // @[DCache.scala:1067:22] wire _clock_en_reg_T_12 = 1'h1; // @[DCache.scala:1067:42] wire _clock_en_reg_T_13 = 1'h1; // @[DCache.scala:1068:18] wire _clock_en_reg_T_15 = 1'h1; // @[DCache.scala:1068:35] wire _clock_en_reg_T_16 = 1'h1; // @[DCache.scala:1069:31] wire _clock_en_reg_T_18 = 1'h1; // @[DCache.scala:1070:22] wire _clock_en_reg_T_20 = 1'h1; // @[DCache.scala:1070:46] wire _clock_en_reg_T_21 = 1'h1; // @[DCache.scala:1071:23] wire _clock_en_reg_T_23 = 1'h1; // @[DCache.scala:1072:23] wire _clock_en_reg_T_25 = 1'h1; // @[DCache.scala:1072:54] wire _clock_en_reg_T_27 = 1'h1; // @[DCache.scala:1073:21] wire io_cpu_perf_release_first = 1'h1; // @[Edges.scala:231:25] wire _io_cpu_perf_release_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire io_cpu_perf_release_last = 1'h1; // @[Edges.scala:232:33] wire _io_cpu_perf_storeBufferEmptyAfterLoad_T_2 = 1'h1; // @[DCache.scala:1082:31] wire _io_cpu_perf_storeBufferEmptyAfterStore_T_5 = 1'h1; // @[DCache.scala:1087:31] wire _io_cpu_perf_canAcceptStoreThenLoad_T_3 = 1'h1; // @[DCache.scala:1089:72] wire _io_cpu_perf_canAcceptLoadThenLoad_T_56 = 1'h1; // @[DCache.scala:1092:115] wire [3:0] io_ptw_ptbr_mode = 4'h0; // @[DCache.scala:101:7] wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[DCache.scala:101:7] wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[DCache.scala:101:7] wire [3:0] pma_checker_io_ptw_ptbr_mode = 4'h0; // @[DCache.scala:120:32] wire [3:0] pma_checker_io_ptw_hgatp_mode = 4'h0; // @[DCache.scala:120:32] wire [3:0] pma_checker_io_ptw_vsatp_mode = 4'h0; // @[DCache.scala:120:32] wire [3:0] pma_checker_satp_mode = 4'h0; // @[TLB.scala:373:17] wire [3:0] pma_checker_real_hits_hi_hi = 4'h0; // @[package.scala:45:27] wire [3:0] pma_checker__multipleHits_T_31 = 4'h0; // @[Misc.scala:182:39] wire [3:0] tl_out_c_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _s1_probe_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _s1_probe_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _probe_bits_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _probe_bits_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _probe_bits_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _probe_bits_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _r_T_16 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _r_T_63 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _r_T_127 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _a_mask_T = 4'h0; // @[DCache.scala:582:90] wire [3:0] _atomics_WIRE_size = 4'h0; // @[DCache.scala:587:51] wire [3:0] _atomics_WIRE_1_size = 4'h0; // @[DCache.scala:587:38] wire [3:0] _tl_out_a_bits_WIRE_size = 4'h0; // @[DCache.scala:1209:67] wire [3:0] _tl_out_a_bits_WIRE_1_size = 4'h0; // @[DCache.scala:1209:54] wire [3:0] _metaArb_io_in_3_bits_data_T_5 = 4'h0; // @[Metadata.scala:87:10] wire [3:0] _block_probe_for_pending_release_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _block_probe_for_pending_release_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _metaArb_io_in_6_valid_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _metaArb_io_in_6_valid_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _metaArb_io_in_6_bits_idx_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _metaArb_io_in_6_bits_idx_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _metaArb_io_in_6_bits_addr_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _metaArb_io_in_6_bits_addr_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] nackResponseMessage_size = 4'h0; // @[Edges.scala:416:17] wire [3:0] cleanReleaseMessage_size = 4'h0; // @[Edges.scala:416:17] wire [3:0] dirtyReleaseMessage_size = 4'h0; // @[Edges.scala:433:17] wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[DCache.scala:101:7] wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[DCache.scala:101:7] wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[DCache.scala:101:7] wire [15:0] pma_checker_io_ptw_ptbr_asid = 16'h0; // @[DCache.scala:120:32] wire [15:0] pma_checker_io_ptw_hgatp_asid = 16'h0; // @[DCache.scala:120:32] wire [15:0] pma_checker_io_ptw_vsatp_asid = 16'h0; // @[DCache.scala:120:32] wire [15:0] pma_checker_satp_asid = 16'h0; // @[TLB.scala:373:17] wire [43:0] io_ptw_ptbr_ppn = 44'h0; // @[DCache.scala:101:7] wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[DCache.scala:101:7] wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[DCache.scala:101:7] wire [43:0] pma_checker_io_ptw_resp_bits_pte_ppn = 44'h0; // @[DCache.scala:120:32] wire [43:0] pma_checker_io_ptw_ptbr_ppn = 44'h0; // @[DCache.scala:120:32] wire [43:0] pma_checker_io_ptw_hgatp_ppn = 44'h0; // @[DCache.scala:120:32] wire [43:0] pma_checker_io_ptw_vsatp_ppn = 44'h0; // @[DCache.scala:120:32] wire [43:0] pma_checker_satp_ppn = 44'h0; // @[TLB.scala:373:17] wire [1:0] io_ptw_status_dprv = 2'h3; // @[DCache.scala:101:7] wire [1:0] io_ptw_status_prv = 2'h3; // @[DCache.scala:101:7] wire [1:0] hitState_meta_state = 2'h3; // @[Metadata.scala:160:20] wire [1:0] _r_T_11 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_13 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_21 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_23 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _metaArb_io_in_3_bits_data_T_8 = 2'h3; // @[Metadata.scala:24:15] wire [22:0] io_ptw_status_zero2 = 23'h0; // @[DCache.scala:101:7] wire [22:0] pma_checker_io_ptw_status_zero2 = 23'h0; // @[DCache.scala:120:32] wire [22:0] pma_checker_io_ptw_gstatus_zero2 = 23'h0; // @[DCache.scala:120:32] wire [7:0] io_cpu_req_bits_mask = 8'h0; // @[DCache.scala:101:7] wire [7:0] io_ptw_status_zero1 = 8'h0; // @[DCache.scala:101:7] wire [7:0] pma_checker_io_ptw_status_zero1 = 8'h0; // @[DCache.scala:120:32] wire [7:0] pma_checker_io_ptw_gstatus_zero1 = 8'h0; // @[DCache.scala:120:32] wire [7:0] metaArb_io_in_0_bits_idx = 8'h0; // @[DCache.scala:135:28] wire [7:0] metaArb_io_in_4_bits_idx = 8'h0; // @[DCache.scala:135:28] wire [7:0] metaArb_io_in_5_bits_idx = 8'h0; // @[DCache.scala:135:28] wire [7:0] metaArb_io_in_6_bits_idx = 8'h0; // @[DCache.scala:135:28] wire [7:0] _s1_probe_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _s1_probe_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _probe_bits_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _probe_bits_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _probe_bits_WIRE_2_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _probe_bits_WIRE_3_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] s0_req_mask = 8'h0; // @[DCache.scala:192:24] wire [7:0] _metaArb_io_in_1_bits_idx_T = 8'h0; // @[DCache.scala:1200:47] wire [7:0] _pstore2_storegen_mask_mergedMask_T = 8'h0; // @[DCache.scala:533:42] wire [7:0] _atomics_WIRE_mask = 8'h0; // @[DCache.scala:587:51] wire [7:0] _atomics_WIRE_1_mask = 8'h0; // @[DCache.scala:587:38] wire [7:0] _tl_out_a_bits_WIRE_mask = 8'h0; // @[DCache.scala:1209:67] wire [7:0] _tl_out_a_bits_WIRE_1_mask = 8'h0; // @[DCache.scala:1209:54] wire [7:0] _block_probe_for_pending_release_ack_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _block_probe_for_pending_release_ack_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _metaArb_io_in_6_valid_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _metaArb_io_in_6_valid_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _metaArb_io_in_6_bits_idx_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _metaArb_io_in_6_bits_idx_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _metaArb_io_in_6_bits_idx_T = 8'h0; // @[DCache.scala:1200:47] wire [7:0] _metaArb_io_in_6_bits_addr_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _metaArb_io_in_6_bits_addr_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _dataArb_io_in_2_bits_addr_T = 8'h0; // @[DCache.scala:1200:47] wire [7:0] _metaArb_io_in_4_bits_idx_T = 8'h0; // @[DCache.scala:1200:47] wire [7:0] _metaArb_io_in_5_bits_idx_T = 8'h0; // @[DCache.scala:1017:44] wire [1:0] io_ptw_status_sxl = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_status_uxl = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_status_xs = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_status_vs = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_hstatus_vsxl = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_gstatus_uxl = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_gstatus_xs = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_0_cfg_res = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_1_cfg_res = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_2_cfg_res = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_3_cfg_res = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_4_cfg_res = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_5_cfg_res = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_6_cfg_res = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_7_cfg_res = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_tlb_port_req_bits_size = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_tlb_port_req_bits_prv = 2'h0; // @[DCache.scala:101:7] wire [1:0] pma_checker_io_ptw_resp_bits_pte_reserved_for_software = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_resp_bits_level = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_status_dprv = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_status_prv = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_status_sxl = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_status_uxl = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_status_xs = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_status_fs = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_status_mpp = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_status_vs = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_hstatus_vsxl = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_hstatus_zero3 = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_hstatus_zero2 = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_gstatus_dprv = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_gstatus_prv = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_gstatus_sxl = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_gstatus_uxl = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_gstatus_xs = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_gstatus_fs = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_gstatus_mpp = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_gstatus_vs = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_0_cfg_res = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_0_cfg_a = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_1_cfg_res = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_1_cfg_a = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_2_cfg_res = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_2_cfg_a = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_3_cfg_res = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_3_cfg_a = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_4_cfg_res = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_4_cfg_a = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_5_cfg_res = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_5_cfg_a = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_6_cfg_res = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_6_cfg_a = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_7_cfg_res = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_7_cfg_a = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_real_hits_lo_lo_hi = 2'h0; // @[package.scala:45:27] wire [1:0] pma_checker_real_hits_lo_hi_hi = 2'h0; // @[package.scala:45:27] wire [1:0] pma_checker_real_hits_hi_lo_hi = 2'h0; // @[package.scala:45:27] wire [1:0] pma_checker_real_hits_hi_hi_lo = 2'h0; // @[package.scala:45:27] wire [1:0] pma_checker_real_hits_hi_hi_hi = 2'h0; // @[package.scala:45:27] wire [1:0] pma_checker__special_entry_level_T = 2'h0; // @[package.scala:163:13] wire [1:0] pma_checker_special_entry_data_0_lo_lo_lo = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_special_entry_data_0_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_special_entry_data_0_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_special_entry_data_0_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_special_entry_data_0_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_waddr = 2'h0; // @[TLB.scala:477:22] wire [1:0] pma_checker_superpage_entries_0_data_0_lo_lo_lo = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_0_data_0_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_0_data_0_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_0_data_0_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_0_data_0_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_1_data_0_lo_lo_lo = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_1_data_0_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_1_data_0_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_1_data_0_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_1_data_0_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_2_data_0_lo_lo_lo = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_2_data_0_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_2_data_0_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_2_data_0_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_2_data_0_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_3_data_0_lo_lo_lo = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_3_data_0_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_3_data_0_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_3_data_0_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_3_data_0_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_idx = 2'h0; // @[package.scala:163:13] wire [1:0] pma_checker_sectored_entries_0_0_data_lo_lo_lo = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_0_data_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_0_data_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_0_data_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_0_data_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_idx_1 = 2'h0; // @[package.scala:163:13] wire [1:0] pma_checker_sectored_entries_0_1_data_lo_lo_lo = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_1_data_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_1_data_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_1_data_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_1_data_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_idx_2 = 2'h0; // @[package.scala:163:13] wire [1:0] pma_checker_sectored_entries_0_2_data_lo_lo_lo = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_2_data_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_2_data_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_2_data_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_2_data_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_idx_3 = 2'h0; // @[package.scala:163:13] wire [1:0] pma_checker_sectored_entries_0_3_data_lo_lo_lo = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_3_data_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_3_data_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_3_data_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_3_data_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_idx_4 = 2'h0; // @[package.scala:163:13] wire [1:0] pma_checker_sectored_entries_0_4_data_lo_lo_lo = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_4_data_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_4_data_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_4_data_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_4_data_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_idx_5 = 2'h0; // @[package.scala:163:13] wire [1:0] pma_checker_sectored_entries_0_5_data_lo_lo_lo = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_5_data_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_5_data_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_5_data_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_5_data_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_idx_6 = 2'h0; // @[package.scala:163:13] wire [1:0] pma_checker_sectored_entries_0_6_data_lo_lo_lo = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_6_data_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_6_data_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_6_data_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_6_data_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_idx_7 = 2'h0; // @[package.scala:163:13] wire [1:0] pma_checker_sectored_entries_0_7_data_lo_lo_lo = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_7_data_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_7_data_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_7_data_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_7_data_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker__c_array_T = 2'h0; // @[TLB.scala:537:25] wire [1:0] pma_checker__prefetchable_array_T_1 = 2'h0; // @[TLB.scala:547:59] wire [1:0] pma_checker__multipleHits_T_3 = 2'h0; // @[Misc.scala:182:39] wire [1:0] pma_checker__multipleHits_T_12 = 2'h0; // @[Misc.scala:182:39] wire [1:0] pma_checker__multipleHits_T_24 = 2'h0; // @[Misc.scala:182:39] wire [1:0] pma_checker__multipleHits_T_32 = 2'h0; // @[Misc.scala:181:37] wire [1:0] pma_checker__multipleHits_T_37 = 2'h0; // @[Misc.scala:182:39] wire [1:0] _s1_probe_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _s1_probe_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _probe_bits_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _probe_bits_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _probe_bits_WIRE_2_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _probe_bits_WIRE_3_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] hitState_meta_1_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] dummyMeta_meta_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] dummyMeta_coh_state = 2'h0; // @[HellaCache.scala:305:20] wire [1:0] _s2_valid_no_xcpt_T_1 = 2'h0; // @[DCache.scala:332:54] wire [1:0] s2_meta_corrected_0_coh_state = 2'h0; // @[DCache.scala:361:99] wire [1:0] _s2_meta_corrected_T_1 = 2'h0; // @[DCache.scala:361:99] wire [1:0] _r_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_5 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_15 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_75 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_79 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_83 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_87 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_91 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_139 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_143 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_147 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_151 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_155 = 2'h0; // @[Misc.scala:38:63] wire [1:0] metaArb_io_in_1_bits_data_new_meta_coh_state = 2'h0; // @[DCache.scala:456:31] wire [1:0] metaArb_io_in_1_bits_data_new_meta_coh_meta_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] _metaArb_io_in_3_bits_data_T_2 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _metaArb_io_in_3_bits_data_T_4 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _block_probe_for_pending_release_ack_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _block_probe_for_pending_release_ack_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _metaArb_io_in_6_valid_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _metaArb_io_in_6_valid_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _metaArb_io_in_6_bits_idx_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _metaArb_io_in_6_bits_idx_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _metaArb_io_in_6_bits_addr_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _metaArb_io_in_6_bits_addr_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _io_cpu_s2_xcpt_WIRE_size = 2'h0; // @[DCache.scala:933:74] wire [1:0] metaArb_io_in_0_bits_data_meta_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] metaArb_io_in_0_bits_data_meta_1_coh_state = 2'h0; // @[HellaCache.scala:305:20] wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[DCache.scala:101:7] wire [29:0] pma_checker_io_ptw_hstatus_zero6 = 30'h0; // @[DCache.scala:120:32] wire [29:0] pma_checker_io_ptw_pmp_0_addr = 30'h0; // @[DCache.scala:120:32] wire [29:0] pma_checker_io_ptw_pmp_1_addr = 30'h0; // @[DCache.scala:120:32] wire [29:0] pma_checker_io_ptw_pmp_2_addr = 30'h0; // @[DCache.scala:120:32] wire [29:0] pma_checker_io_ptw_pmp_3_addr = 30'h0; // @[DCache.scala:120:32] wire [29:0] pma_checker_io_ptw_pmp_4_addr = 30'h0; // @[DCache.scala:120:32] wire [29:0] pma_checker_io_ptw_pmp_5_addr = 30'h0; // @[DCache.scala:120:32] wire [29:0] pma_checker_io_ptw_pmp_6_addr = 30'h0; // @[DCache.scala:120:32] wire [29:0] pma_checker_io_ptw_pmp_7_addr = 30'h0; // @[DCache.scala:120:32] wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[DCache.scala:101:7] wire [8:0] pma_checker_io_ptw_hstatus_zero5 = 9'h0; // @[DCache.scala:120:32] wire [8:0] r_beats1_decode_1 = 9'h0; // @[Edges.scala:220:59] wire [8:0] r_beats1_1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _r_count_T_1 = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _r_counter_T_1 = 9'h0; // @[Edges.scala:236:21] wire [8:0] io_cpu_perf_release_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] io_cpu_perf_release_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _io_cpu_perf_release_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] io_cpu_perf_release_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _io_cpu_perf_release_counter_T = 9'h0; // @[Edges.scala:236:21] wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[DCache.scala:101:7] wire [5:0] pma_checker_io_ptw_hstatus_vgein = 6'h0; // @[DCache.scala:120:32] wire [5:0] pma_checker_real_hits_lo = 6'h0; // @[package.scala:45:27] wire [5:0] pma_checker_special_entry_data_0_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_superpage_entries_0_data_0_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_superpage_entries_1_data_0_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_superpage_entries_2_data_0_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_superpage_entries_3_data_0_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_0_data_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_1_data_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_2_data_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_3_data_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_4_data_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_5_data_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_6_data_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_7_data_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker__multipleHits_T = 6'h0; // @[Misc.scala:181:37] wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[DCache.scala:101:7] wire [4:0] io_tlb_port_req_bits_cmd = 5'h0; // @[DCache.scala:101:7] wire [4:0] pma_checker_io_ptw_hstatus_zero1 = 5'h0; // @[DCache.scala:120:32] wire [4:0] _io_cpu_s2_xcpt_WIRE_cmd = 5'h0; // @[DCache.scala:933:74] wire [8:0] r_counter1_1 = 9'h1FF; // @[Edges.scala:230:28] wire [8:0] io_cpu_perf_release_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _r_counter1_T_1 = 10'h3FF; // @[Edges.scala:230:28] wire [9:0] _io_cpu_perf_release_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [11:0] pma_checker__gpa_hits_hit_mask_T_2 = 12'h0; // @[TLB.scala:606:24] wire [11:0] pma_checker__io_resp_gpa_offset_T = 12'h0; // @[TLB.scala:658:47] wire [11:0] _r_beats1_decode_T_5 = 12'h0; // @[package.scala:243:46] wire [11:0] _io_cpu_perf_release_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _r_beats1_decode_T_4 = 12'hFFF; // @[package.scala:243:76] wire [11:0] _io_cpu_perf_release_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _r_beats1_decode_T_3 = 27'hFFF; // @[package.scala:243:71] wire [26:0] _io_cpu_perf_release_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [19:0] pma_checker_refill_ppn = 20'h0; // @[TLB.scala:406:44] wire [19:0] pma_checker_newEntry_ppn = 20'h0; // @[TLB.scala:449:24] wire [19:0] pma_checker__ppn_T_2 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_3 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_4 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_5 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_6 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_7 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_8 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_9 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_10 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_11 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_12 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_13 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_14 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_16 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_17 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_18 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_19 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_20 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_21 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_22 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_23 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_24 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_25 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_26 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_27 = 20'h0; // @[Mux.scala:30:73] wire [19:0] metaArb_io_in_0_bits_data = 20'h0; // @[DCache.scala:135:28] wire [19:0] metaArb_io_in_1_bits_data = 20'h0; // @[DCache.scala:135:28] wire [19:0] s1_meta_0 = 20'h0; // @[DCache.scala:306:58] wire [19:0] _s2_meta_corrected_WIRE = 20'h0; // @[DCache.scala:361:99] wire [19:0] _metaArb_io_in_1_bits_data_T = 20'h0; // @[DCache.scala:458:14] wire [19:0] _metaArb_io_in_0_bits_data_T = 20'h0; // @[DCache.scala:1050:85] wire [17:0] dummyMeta_tag = 18'h0; // @[HellaCache.scala:305:20] wire [17:0] s2_meta_corrected_0_tag = 18'h0; // @[DCache.scala:361:99] wire [17:0] _s2_meta_corrected_T = 18'h0; // @[DCache.scala:361:99] wire [17:0] metaArb_io_in_1_bits_data_new_meta_tag = 18'h0; // @[DCache.scala:456:31] wire [17:0] _metaArb_io_in_4_bits_data_T = 18'h0; // @[DCache.scala:913:78] wire [17:0] metaArb_io_in_4_bits_data_meta_tag = 18'h0; // @[HellaCache.scala:305:20] wire [17:0] metaArb_io_in_0_bits_data_meta_1_tag = 18'h0; // @[HellaCache.scala:305:20] wire [13:0] pma_checker_lrscAllowed = 14'h0; // @[TLB.scala:580:24] wire [13:0] pma_checker__gf_ld_array_T_2 = 14'h0; // @[TLB.scala:600:46] wire [13:0] pma_checker_gf_ld_array = 14'h0; // @[TLB.scala:600:24] wire [13:0] pma_checker__gf_st_array_T_1 = 14'h0; // @[TLB.scala:601:53] wire [13:0] pma_checker_gf_st_array = 14'h0; // @[TLB.scala:601:24] wire [13:0] pma_checker__gf_inst_array_T = 14'h0; // @[TLB.scala:602:36] wire [13:0] pma_checker_gf_inst_array = 14'h0; // @[TLB.scala:602:26] wire [13:0] pma_checker_gpa_hits_need_gpa_mask = 14'h0; // @[TLB.scala:605:73] wire [13:0] pma_checker__io_resp_gf_ld_T_1 = 14'h0; // @[TLB.scala:637:58] wire [13:0] pma_checker__io_resp_gf_st_T_1 = 14'h0; // @[TLB.scala:638:65] wire [13:0] pma_checker__io_resp_gf_inst_T = 14'h0; // @[TLB.scala:639:48] wire [13:0] _dataArb_io_in_2_bits_addr_T_1 = 14'h0; // @[DCache.scala:903:55] wire [13:0] _metaArb_io_in_4_bits_addr_T_1 = 14'h0; // @[DCache.scala:912:90] wire [13:0] _metaArb_io_in_5_bits_addr_T_1 = 14'h0; // @[DCache.scala:1018:98] wire [7:0] flushCounterWrap = 8'h1; // @[DCache.scala:1011:42] wire [8:0] flushCounterNext = 9'h1; // @[DCache.scala:1009:39] wire [31:0] pma_checker_io_ptw_status_isa = 32'h0; // @[DCache.scala:120:32] wire [31:0] pma_checker_io_ptw_gstatus_isa = 32'h0; // @[DCache.scala:120:32] wire [31:0] pma_checker_io_ptw_pmp_0_mask = 32'h0; // @[DCache.scala:120:32] wire [31:0] pma_checker_io_ptw_pmp_1_mask = 32'h0; // @[DCache.scala:120:32] wire [31:0] pma_checker_io_ptw_pmp_2_mask = 32'h0; // @[DCache.scala:120:32] wire [31:0] pma_checker_io_ptw_pmp_3_mask = 32'h0; // @[DCache.scala:120:32] wire [31:0] pma_checker_io_ptw_pmp_4_mask = 32'h0; // @[DCache.scala:120:32] wire [31:0] pma_checker_io_ptw_pmp_5_mask = 32'h0; // @[DCache.scala:120:32] wire [31:0] pma_checker_io_ptw_pmp_6_mask = 32'h0; // @[DCache.scala:120:32] wire [31:0] pma_checker_io_ptw_pmp_7_mask = 32'h0; // @[DCache.scala:120:32] wire [31:0] tl_out_c_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _s1_probe_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _s1_probe_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _probe_bits_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _probe_bits_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _probe_bits_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _probe_bits_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _atomics_WIRE_address = 32'h0; // @[DCache.scala:587:51] wire [31:0] _atomics_WIRE_1_address = 32'h0; // @[DCache.scala:587:38] wire [31:0] _tl_out_a_bits_WIRE_address = 32'h0; // @[DCache.scala:1209:67] wire [31:0] _tl_out_a_bits_WIRE_1_address = 32'h0; // @[DCache.scala:1209:54] wire [31:0] _block_probe_for_pending_release_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _block_probe_for_pending_release_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _block_probe_for_pending_release_ack_T = 32'h0; // @[DCache.scala:767:88] wire [31:0] _metaArb_io_in_6_valid_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _metaArb_io_in_6_valid_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _metaArb_io_in_6_bits_idx_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _metaArb_io_in_6_bits_idx_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _metaArb_io_in_6_bits_addr_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _metaArb_io_in_6_bits_addr_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] nackResponseMessage_address = 32'h0; // @[Edges.scala:416:17] wire [31:0] cleanReleaseMessage_address = 32'h0; // @[Edges.scala:416:17] wire [31:0] dirtyReleaseMessage_address = 32'h0; // @[Edges.scala:433:17] wire [31:0] _io_cpu_s2_xcpt_WIRE_paddr = 32'h0; // @[DCache.scala:933:74] wire [2:0] pma_checker_real_hits_lo_lo = 3'h0; // @[package.scala:45:27] wire [2:0] pma_checker_real_hits_lo_hi = 3'h0; // @[package.scala:45:27] wire [2:0] pma_checker_real_hits_hi_lo = 3'h0; // @[package.scala:45:27] wire [2:0] pma_checker_special_entry_data_0_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_special_entry_data_0_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_special_entry_data_0_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_0_data_0_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_0_data_0_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_0_data_0_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_1_data_0_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_1_data_0_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_1_data_0_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_2_data_0_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_2_data_0_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_2_data_0_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_3_data_0_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_3_data_0_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_3_data_0_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_waddr_1 = 3'h0; // @[TLB.scala:485:22] wire [2:0] pma_checker_sectored_entries_0_0_data_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_0_data_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_0_data_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_1_data_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_1_data_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_1_data_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_2_data_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_2_data_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_2_data_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_3_data_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_3_data_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_3_data_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_4_data_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_4_data_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_4_data_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_5_data_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_5_data_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_5_data_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_6_data_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_6_data_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_6_data_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_7_data_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_7_data_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_7_data_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_state_vec_0_left_subtree_state = 3'h0; // @[package.scala:163:13] wire [2:0] pma_checker_state_vec_0_right_subtree_state = 3'h0; // @[Replacement.scala:198:38] wire [2:0] pma_checker__multipleHits_T_1 = 3'h0; // @[Misc.scala:181:37] wire [2:0] pma_checker__multipleHits_T_10 = 3'h0; // @[Misc.scala:182:39] wire [2:0] pma_checker__multipleHits_T_22 = 3'h0; // @[Misc.scala:181:37] wire [2:0] _s1_probe_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _s1_probe_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _probe_bits_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _probe_bits_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _probe_bits_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _probe_bits_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] get_param = 3'h0; // @[Edges.scala:460:17] wire [2:0] put_opcode = 3'h0; // @[Edges.scala:480:17] wire [2:0] put_param = 3'h0; // @[Edges.scala:480:17] wire [2:0] putpartial_param = 3'h0; // @[Edges.scala:500:17] wire [2:0] _atomics_WIRE_opcode = 3'h0; // @[DCache.scala:587:51] wire [2:0] _atomics_WIRE_param = 3'h0; // @[DCache.scala:587:51] wire [2:0] _atomics_WIRE_1_opcode = 3'h0; // @[DCache.scala:587:38] wire [2:0] _atomics_WIRE_1_param = 3'h0; // @[DCache.scala:587:38] wire [2:0] atomics_a_1_param = 3'h0; // @[Edges.scala:534:17] wire [2:0] atomics_a_5_param = 3'h0; // @[Edges.scala:517:17] wire [2:0] _tl_out_a_bits_WIRE_opcode = 3'h0; // @[DCache.scala:1209:67] wire [2:0] _tl_out_a_bits_WIRE_param = 3'h0; // @[DCache.scala:1209:67] wire [2:0] _tl_out_a_bits_WIRE_1_opcode = 3'h0; // @[DCache.scala:1209:54] wire [2:0] _tl_out_a_bits_WIRE_1_param = 3'h0; // @[DCache.scala:1209:54] wire [2:0] _block_probe_for_pending_release_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _block_probe_for_pending_release_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _metaArb_io_in_6_valid_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _metaArb_io_in_6_valid_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _metaArb_io_in_6_bits_idx_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _metaArb_io_in_6_bits_idx_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _metaArb_io_in_6_bits_addr_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _metaArb_io_in_6_bits_addr_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [1:0] _r_T_7 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_9 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_17 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_19 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] s2_victim_way = 2'h1; // @[OneHot.scala:58:35] wire [1:0] dataArb_io_in_0_bits_wordMask_wordMask = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _dataArb_io_in_0_bits_wordMask_T_2 = 2'h1; // @[DCache.scala:555:20] wire [1:0] _metaArb_io_in_3_bits_data_T_6 = 2'h1; // @[Metadata.scala:25:15] wire [20:0] pma_checker_io_ptw_req_bits_bits_addr = 21'h0; // @[DCache.scala:120:32] wire [20:0] pma_checker_special_entry_data_0_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_superpage_entries_0_data_0_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_superpage_entries_1_data_0_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_superpage_entries_2_data_0_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_superpage_entries_3_data_0_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_sectored_entries_0_0_data_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_sectored_entries_0_1_data_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_sectored_entries_0_2_data_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_sectored_entries_0_3_data_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_sectored_entries_0_4_data_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_sectored_entries_0_5_data_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_sectored_entries_0_6_data_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_sectored_entries_0_7_data_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker__io_resp_gpa_page_T_2 = 21'h0; // @[TLB.scala:657:58] wire [63:0] io_cpu_req_bits_data = 64'h0; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_2_sdata = 64'h0; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_3_sdata = 64'h0; // @[DCache.scala:101:7] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_0_wdata = 64'h0; // @[DCache.scala:120:32] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_0_value = 64'h0; // @[DCache.scala:120:32] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[DCache.scala:120:32] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_1_wdata = 64'h0; // @[DCache.scala:120:32] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_1_value = 64'h0; // @[DCache.scala:120:32] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[DCache.scala:120:32] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_2_wdata = 64'h0; // @[DCache.scala:120:32] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_2_value = 64'h0; // @[DCache.scala:120:32] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_2_sdata = 64'h0; // @[DCache.scala:120:32] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_3_wdata = 64'h0; // @[DCache.scala:120:32] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_3_value = 64'h0; // @[DCache.scala:120:32] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_3_sdata = 64'h0; // @[DCache.scala:120:32] wire [63:0] tl_out_c_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _s1_probe_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _s1_probe_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _probe_bits_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _probe_bits_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _probe_bits_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _probe_bits_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] s0_req_data = 64'h0; // @[DCache.scala:192:24] wire [63:0] get_data = 64'h0; // @[Edges.scala:460:17] wire [63:0] _atomics_WIRE_data = 64'h0; // @[DCache.scala:587:51] wire [63:0] _atomics_WIRE_1_data = 64'h0; // @[DCache.scala:587:38] wire [63:0] _tl_out_a_bits_WIRE_data = 64'h0; // @[DCache.scala:1209:67] wire [63:0] _tl_out_a_bits_WIRE_1_data = 64'h0; // @[DCache.scala:1209:54] wire [63:0] _block_probe_for_pending_release_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _block_probe_for_pending_release_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _metaArb_io_in_6_valid_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _metaArb_io_in_6_valid_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _metaArb_io_in_6_bits_idx_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _metaArb_io_in_6_bits_idx_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _metaArb_io_in_6_bits_addr_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _metaArb_io_in_6_bits_addr_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] nackResponseMessage_data = 64'h0; // @[Edges.scala:416:17] wire [63:0] cleanReleaseMessage_data = 64'h0; // @[Edges.scala:416:17] wire [63:0] dirtyReleaseMessage_data = 64'h0; // @[Edges.scala:433:17] wire [63:0] _s2_data_word_possibly_uncached_T_1 = 64'h0; // @[DCache.scala:972:43] wire [32:0] pma_checker_io_sfence_bits_addr = 33'h0; // @[DCache.scala:120:32] wire [32:0] pma_checker_io_ptw_resp_bits_gpa_bits = 33'h0; // @[DCache.scala:120:32] wire [33:0] io_tlb_port_req_bits_vaddr = 34'h0; // @[DCache.scala:101:7] wire [33:0] _io_cpu_s2_xcpt_WIRE_gpa = 34'h0; // @[DCache.scala:933:74] wire [7:0] dataArb_io_in_2_bits_eccMask = 8'hFF; // @[DCache.scala:152:28] wire [7:0] dataArb_io_in_3_bits_eccMask = 8'hFF; // @[DCache.scala:152:28] wire [7:0] _dataArb_io_in_3_bits_wordMask_T = 8'hFF; // @[DCache.scala:254:9] wire [7:0] _dataArb_io_in_3_bits_eccMask_T = 8'hFF; // @[DCache.scala:256:36] wire [7:0] _dataArb_io_in_2_bits_eccMask_T = 8'hFF; // @[DCache.scala:905:36] wire [2:0] tl_out_c_bits_param = 3'h5; // @[Bundles.scala:265:61] wire [2:0] nackResponseMessage_param = 3'h5; // @[Edges.scala:416:17] wire [2:0] dirtyReleaseMessage_opcode = 3'h5; // @[Edges.scala:433:17] wire [2:0] tl_out_c_bits_opcode = 3'h4; // @[Bundles.scala:265:61] wire [2:0] get_opcode = 3'h4; // @[Edges.scala:460:17] wire [2:0] atomics_a_4_param = 3'h4; // @[Edges.scala:517:17] wire [2:0] nackResponseMessage_opcode = 3'h4; // @[Edges.scala:416:17] wire [2:0] cleanReleaseMessage_opcode = 3'h4; // @[Edges.scala:416:17] wire [9:0] pma_checker_io_ptw_resp_bits_pte_reserved_for_future = 10'h0; // @[DCache.scala:120:32] wire [9:0] _releaseDataBeat_T = 10'h0; // @[DCache.scala:804:28] wire [3:0] _r_T_24 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _metaArb_io_in_3_bits_data_T_9 = 4'hC; // @[Metadata.scala:89:10] wire [3:0] _r_T_20 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _r_T_67 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _r_T_131 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _metaArb_io_in_3_bits_data_T_7 = 4'h4; // @[Metadata.scala:88:10] wire [3:0] _r_T_6 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _r_T_62 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _r_T_126 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _metaArb_io_in_3_bits_data_T_3 = 4'h1; // @[Metadata.scala:86:10] wire [1:0] _r_T_118 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _r_T_120 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _r_T_122 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _s1_data_way_T = 2'h2; // @[DCache.scala:694:32] wire [2:0] atomics_a_opcode = 3'h3; // @[Edges.scala:534:17] wire [2:0] atomics_a_param = 3'h3; // @[Edges.scala:534:17] wire [2:0] atomics_a_1_opcode = 3'h3; // @[Edges.scala:534:17] wire [2:0] atomics_a_2_opcode = 3'h3; // @[Edges.scala:534:17] wire [2:0] atomics_a_3_opcode = 3'h3; // @[Edges.scala:534:17] wire [2:0] atomics_a_8_param = 3'h3; // @[Edges.scala:517:17] wire [2:0] atomics_a_3_param = 3'h2; // @[Edges.scala:534:17] wire [2:0] atomics_a_4_opcode = 3'h2; // @[Edges.scala:517:17] wire [2:0] atomics_a_5_opcode = 3'h2; // @[Edges.scala:517:17] wire [2:0] atomics_a_6_opcode = 3'h2; // @[Edges.scala:517:17] wire [2:0] atomics_a_7_opcode = 3'h2; // @[Edges.scala:517:17] wire [2:0] atomics_a_7_param = 3'h2; // @[Edges.scala:517:17] wire [2:0] atomics_a_8_opcode = 3'h2; // @[Edges.scala:517:17] wire [2:0] putpartial_opcode = 3'h1; // @[Edges.scala:500:17] wire [2:0] atomics_a_2_param = 3'h1; // @[Edges.scala:534:17] wire [2:0] atomics_a_6_param = 3'h1; // @[Edges.scala:517:17] wire [3:0] _r_T_71 = 4'h8; // @[Metadata.scala:133:10] wire [3:0] _r_T_135 = 4'h8; // @[Metadata.scala:133:10] wire [3:0] _r_T_70 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _r_T_134 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _r_T_69 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _r_T_133 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _r_T_68 = 4'hB; // @[Metadata.scala:130:10] wire [3:0] _r_T_132 = 4'hB; // @[Metadata.scala:130:10] wire [3:0] _r_T_18 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _r_T_66 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] _r_T_130 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] _r_T_10 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _r_T_65 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] _r_T_129 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] _r_T_8 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _r_T_64 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _r_T_128 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _r_T_4 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _r_T_61 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _r_T_125 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _r_T_2 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _r_T_60 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _r_T_124 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _r_T_22 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r_T_14 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _r_T_12 = 4'hF; // @[Metadata.scala:65:10] wire [31:0] _inScratchpad_T_2 = 32'h80004000; // @[DCache.scala:303:70] wire [32:0] _inScratchpad_T_1 = 33'h80004000; // @[DCache.scala:303:70] wire [31:0] baseAddr = 32'h80000000; // @[DCache.scala:302:93] wire [6:0] pma_checker_real_hits_hi = 7'h0; // @[package.scala:45:27] wire [6:0] pma_checker__state_vec_WIRE_0 = 7'h0; // @[Replacement.scala:305:25] wire [6:0] pma_checker__multipleHits_T_21 = 7'h0; // @[Misc.scala:182:39] wire [12:0] pma_checker_real_hits = 13'h0; // @[package.scala:45:27] wire [12:0] pma_checker__stage1_bypass_T = 13'h0; // @[TLB.scala:517:27] wire [12:0] pma_checker_stage1_bypass = 13'h0; // @[TLB.scala:517:61] wire [12:0] pma_checker__r_array_T_2 = 13'h0; // @[TLB.scala:520:74] wire [12:0] pma_checker__hr_array_T_2 = 13'h0; // @[TLB.scala:524:60] wire [12:0] pma_checker__gpa_hits_T = 13'h0; // @[TLB.scala:607:30] wire [12:0] pma_checker__tlb_hit_T = 13'h0; // @[TLB.scala:611:28] wire [12:0] pma_checker__stage1_bypass_T_2 = 13'h1FFF; // @[TLB.scala:517:68] wire [12:0] pma_checker__stage1_bypass_T_4 = 13'h1FFF; // @[TLB.scala:517:95] wire [12:0] pma_checker_stage2_bypass = 13'h1FFF; // @[TLB.scala:523:27] wire [12:0] pma_checker__hr_array_T_4 = 13'h1FFF; // @[TLB.scala:524:111] wire [12:0] pma_checker__hw_array_T_1 = 13'h1FFF; // @[TLB.scala:525:55] wire [12:0] pma_checker__hx_array_T_1 = 13'h1FFF; // @[TLB.scala:526:55] wire [12:0] pma_checker__gpa_hits_hit_mask_T_4 = 13'h1FFF; // @[TLB.scala:606:88] wire [12:0] pma_checker_gpa_hits_hit_mask = 13'h1FFF; // @[TLB.scala:606:82] wire [12:0] pma_checker__gpa_hits_T_1 = 13'h1FFF; // @[TLB.scala:607:16] wire [12:0] pma_checker_gpa_hits = 13'h1FFF; // @[TLB.scala:607:14] wire [13:0] pma_checker_hr_array = 14'h3FFF; // @[TLB.scala:524:21] wire [13:0] pma_checker_hw_array = 14'h3FFF; // @[TLB.scala:525:21] wire [13:0] pma_checker_hx_array = 14'h3FFF; // @[TLB.scala:526:21] wire [13:0] pma_checker__ae_array_T_1 = 14'h3FFF; // @[TLB.scala:583:19] wire [13:0] pma_checker__must_alloc_array_T_8 = 14'h3FFF; // @[TLB.scala:596:19] wire [13:0] pma_checker__gf_ld_array_T_1 = 14'h3FFF; // @[TLB.scala:600:50] wire [30:0] pma_checker_special_entry_data_0_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_superpage_entries_0_data_0_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_superpage_entries_1_data_0_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_superpage_entries_2_data_0_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_superpage_entries_3_data_0_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_sectored_entries_0_0_data_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_sectored_entries_0_1_data_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_sectored_entries_0_2_data_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_sectored_entries_0_3_data_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_sectored_entries_0_4_data_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_sectored_entries_0_5_data_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_sectored_entries_0_6_data_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_sectored_entries_0_7_data_hi = 31'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_special_entry_data_0_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_superpage_entries_0_data_0_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_superpage_entries_1_data_0_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_superpage_entries_2_data_0_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_superpage_entries_3_data_0_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_sectored_entries_0_0_data_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_sectored_entries_0_1_data_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_sectored_entries_0_2_data_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_sectored_entries_0_3_data_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_sectored_entries_0_4_data_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_sectored_entries_0_5_data_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_sectored_entries_0_6_data_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_sectored_entries_0_7_data_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_special_entry_data_0_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_superpage_entries_0_data_0_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_superpage_entries_1_data_0_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_superpage_entries_2_data_0_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_superpage_entries_3_data_0_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_sectored_entries_0_0_data_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_sectored_entries_0_1_data_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_sectored_entries_0_2_data_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_sectored_entries_0_3_data_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_sectored_entries_0_4_data_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_sectored_entries_0_5_data_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_sectored_entries_0_6_data_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_sectored_entries_0_7_data_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [13:0] pma_checker_hits = 14'h2000; // @[TLB.scala:442:17] wire [41:0] pma_checker__mpu_ppn_WIRE_1 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_1 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_3 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_5 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_7 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_9 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_11 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_13 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_15 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_17 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_19 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_21 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_23 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_25 = 42'h0; // @[TLB.scala:170:77] wire hartIdSinkNodeOptIn = auto_hart_id_sink_in_0; // @[DCache.scala:101:7] wire nodeOut_a_ready = auto_out_a_ready_0; // @[DCache.scala:101:7] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[DCache.scala:101:7] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[DCache.scala:101:7] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[DCache.scala:101:7] wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[DCache.scala:101:7] wire nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[DCache.scala:101:7] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[DCache.scala:101:7] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[DCache.scala:101:7] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[DCache.scala:101:7] wire metaArb_io_in_7_valid = io_cpu_req_valid_0; // @[DCache.scala:101:7, :135:28] wire [33:0] metaArb_io_in_7_bits_addr = io_cpu_req_bits_addr_0; // @[DCache.scala:101:7, :135:28] wire [6:0] s0_req_tag = io_cpu_req_bits_tag_0; // @[DCache.scala:101:7, :192:24] wire [4:0] s0_req_cmd = io_cpu_req_bits_cmd_0; // @[DCache.scala:101:7, :192:24] wire [1:0] s0_req_size = io_cpu_req_bits_size_0; // @[DCache.scala:101:7, :192:24] wire s0_req_signed = io_cpu_req_bits_signed_0; // @[DCache.scala:101:7, :192:24] wire [1:0] s0_req_dprv = io_cpu_req_bits_dprv_0; // @[DCache.scala:101:7, :192:24] wire s0_req_dv = io_cpu_req_bits_dv_0; // @[DCache.scala:101:7, :192:24] wire s0_req_no_resp = io_cpu_req_bits_no_resp_0; // @[DCache.scala:101:7, :192:24] wire s0_req_no_xcpt = io_cpu_req_bits_no_xcpt_0; // @[DCache.scala:101:7, :192:24] wire _io_cpu_s2_nack_T_5; // @[DCache.scala:445:86] wire _io_cpu_s2_nack_cause_raw_T_3; // @[DCache.scala:574:54] wire _io_cpu_s2_uncached_T_1; // @[DCache.scala:920:37] wire _io_cpu_resp_valid_T_2; // @[DCache.scala:949:70] wire [63:0] _io_cpu_resp_bits_data_T_24; // @[DCache.scala:974:41] wire s2_read; // @[Consts.scala:89:68] wire [63:0] _io_cpu_resp_bits_data_word_bypass_T_7; // @[AMOALU.scala:45:16] wire [63:0] s2_data_word; // @[DCache.scala:970:80] wire _io_cpu_replay_next_T_3; // @[DCache.scala:950:62] wire _io_cpu_s2_xcpt_T_ma_ld; // @[DCache.scala:933:24] wire _io_cpu_s2_xcpt_T_ma_st; // @[DCache.scala:933:24] wire _io_cpu_s2_xcpt_T_pf_ld; // @[DCache.scala:933:24] wire _io_cpu_s2_xcpt_T_pf_st; // @[DCache.scala:933:24] wire _io_cpu_s2_xcpt_T_ae_ld; // @[DCache.scala:933:24] wire _io_cpu_s2_xcpt_T_ae_st; // @[DCache.scala:933:24] wire _io_cpu_ordered_T_8; // @[DCache.scala:929:21] wire _io_cpu_store_pending_T_25; // @[DCache.scala:930:70] wire io_cpu_perf_acquire_done; // @[Edges.scala:233:22] wire _io_cpu_perf_grant_T; // @[DCache.scala:1078:39] wire _io_cpu_perf_blocked_T_1; // @[DCache.scala:1106:23] wire _io_cpu_perf_canAcceptStoreThenLoad_T_10; // @[DCache.scala:1088:41] wire _io_cpu_perf_canAcceptStoreThenRMW_T_1; // @[DCache.scala:1091:75] wire _io_cpu_perf_canAcceptLoadThenLoad_T_61; // @[DCache.scala:1092:40] wire _io_cpu_perf_storeBufferEmptyAfterLoad_T_7; // @[DCache.scala:1080:44] wire _io_cpu_perf_storeBufferEmptyAfterStore_T_10; // @[DCache.scala:1084:45] wire _io_errors_bus_valid_T_2; // @[DCache.scala:1129:42] wire [2:0] auto_out_a_bits_opcode_0; // @[DCache.scala:101:7] wire [2:0] auto_out_a_bits_param_0; // @[DCache.scala:101:7] wire [3:0] auto_out_a_bits_size_0; // @[DCache.scala:101:7] wire [31:0] auto_out_a_bits_address_0; // @[DCache.scala:101:7] wire [7:0] auto_out_a_bits_mask_0; // @[DCache.scala:101:7] wire [63:0] auto_out_a_bits_data_0; // @[DCache.scala:101:7] wire auto_out_a_valid_0; // @[DCache.scala:101:7] wire auto_out_d_ready_0; // @[DCache.scala:101:7] wire io_cpu_req_ready_0; // @[DCache.scala:101:7] wire [33:0] io_cpu_resp_bits_addr_0; // @[DCache.scala:101:7] wire [6:0] io_cpu_resp_bits_tag_0; // @[DCache.scala:101:7] wire [4:0] io_cpu_resp_bits_cmd_0; // @[DCache.scala:101:7] wire [1:0] io_cpu_resp_bits_size_0; // @[DCache.scala:101:7] wire io_cpu_resp_bits_signed_0; // @[DCache.scala:101:7] wire [1:0] io_cpu_resp_bits_dprv_0; // @[DCache.scala:101:7] wire io_cpu_resp_bits_dv_0; // @[DCache.scala:101:7] wire [63:0] io_cpu_resp_bits_data_0; // @[DCache.scala:101:7] wire [7:0] io_cpu_resp_bits_mask_0; // @[DCache.scala:101:7] wire io_cpu_resp_bits_replay_0; // @[DCache.scala:101:7] wire io_cpu_resp_bits_has_data_0; // @[DCache.scala:101:7] wire [63:0] io_cpu_resp_bits_data_word_bypass_0; // @[DCache.scala:101:7] wire [63:0] io_cpu_resp_bits_data_raw_0; // @[DCache.scala:101:7] wire [63:0] io_cpu_resp_bits_store_data_0; // @[DCache.scala:101:7] wire io_cpu_resp_valid_0; // @[DCache.scala:101:7] wire io_cpu_s2_xcpt_ma_ld_0; // @[DCache.scala:101:7] wire io_cpu_s2_xcpt_ma_st_0; // @[DCache.scala:101:7] wire io_cpu_s2_xcpt_pf_ld_0; // @[DCache.scala:101:7] wire io_cpu_s2_xcpt_pf_st_0; // @[DCache.scala:101:7] wire io_cpu_s2_xcpt_ae_ld_0; // @[DCache.scala:101:7] wire io_cpu_s2_xcpt_ae_st_0; // @[DCache.scala:101:7] wire io_cpu_perf_acquire_0; // @[DCache.scala:101:7] wire io_cpu_perf_grant_0; // @[DCache.scala:101:7] wire io_cpu_perf_blocked_0; // @[DCache.scala:101:7] wire io_cpu_perf_canAcceptStoreThenLoad_0; // @[DCache.scala:101:7] wire io_cpu_perf_canAcceptStoreThenRMW_0; // @[DCache.scala:101:7] wire io_cpu_perf_canAcceptLoadThenLoad_0; // @[DCache.scala:101:7] wire io_cpu_perf_storeBufferEmptyAfterLoad_0; // @[DCache.scala:101:7] wire io_cpu_perf_storeBufferEmptyAfterStore_0; // @[DCache.scala:101:7] wire io_cpu_s2_nack_0; // @[DCache.scala:101:7] wire io_cpu_s2_nack_cause_raw_0; // @[DCache.scala:101:7] wire io_cpu_s2_uncached_0; // @[DCache.scala:101:7] wire [31:0] io_cpu_s2_paddr_0; // @[DCache.scala:101:7] wire io_cpu_replay_next_0; // @[DCache.scala:101:7] wire [33:0] io_cpu_s2_gpa_0; // @[DCache.scala:101:7] wire io_cpu_ordered_0; // @[DCache.scala:101:7] wire io_cpu_store_pending_0; // @[DCache.scala:101:7] wire [20:0] io_ptw_req_bits_bits_addr_0; // @[DCache.scala:101:7] wire io_ptw_req_bits_bits_need_gpa_0; // @[DCache.scala:101:7] wire io_ptw_req_bits_bits_vstage1_0; // @[DCache.scala:101:7] wire io_ptw_req_bits_bits_stage2_0; // @[DCache.scala:101:7] wire io_errors_bus_valid; // @[DCache.scala:101:7] wire [31:0] io_errors_bus_bits; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_pf_ld; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_pf_st; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_pf_inst; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_ae_ld; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_ae_st; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_ae_inst; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_ma_ld; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_ma_st; // @[DCache.scala:101:7] wire [31:0] io_tlb_port_s1_resp_paddr; // @[DCache.scala:101:7] wire [33:0] io_tlb_port_s1_resp_gpa; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_cacheable; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_must_alloc; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_prefetchable; // @[DCache.scala:101:7] wire [1:0] io_tlb_port_s1_resp_size; // @[DCache.scala:101:7] wire [4:0] io_tlb_port_s1_resp_cmd; // @[DCache.scala:101:7] wire nodeOut_a_deq_ready = nodeOut_a_ready; // @[Decoupled.scala:356:21] wire nodeOut_a_deq_valid; // @[Decoupled.scala:356:21] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[DCache.scala:101:7] wire [2:0] nodeOut_a_deq_bits_opcode; // @[Decoupled.scala:356:21] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[DCache.scala:101:7] wire [2:0] nodeOut_a_deq_bits_param; // @[Decoupled.scala:356:21] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[DCache.scala:101:7] wire [3:0] nodeOut_a_deq_bits_size; // @[Decoupled.scala:356:21] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[DCache.scala:101:7] wire [31:0] nodeOut_a_deq_bits_address; // @[Decoupled.scala:356:21] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[DCache.scala:101:7] wire [7:0] nodeOut_a_deq_bits_mask; // @[Decoupled.scala:356:21] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[DCache.scala:101:7] wire [63:0] nodeOut_a_deq_bits_data; // @[Decoupled.scala:356:21] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[DCache.scala:101:7] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[DCache.scala:101:7] wire e_sink = nodeOut_d_bits_sink; // @[Edges.scala:451:17] wire [63:0] s1_uncached_data_word = nodeOut_d_bits_data; // @[package.scala:211:50] wire [1:0] pma_checker_io_resp_size = pma_checker_io_req_bits_size; // @[DCache.scala:120:32] wire [4:0] pma_checker_io_resp_cmd = pma_checker_io_req_bits_cmd; // @[DCache.scala:120:32] wire [31:0] pma_checker__io_resp_paddr_T_1; // @[TLB.scala:652:23] wire [33:0] pma_checker__io_resp_gpa_T; // @[TLB.scala:659:8] wire pma_checker__io_resp_pf_ld_T_3; // @[TLB.scala:633:41] wire pma_checker__io_resp_pf_st_T_3; // @[TLB.scala:634:48] wire pma_checker__io_resp_pf_inst_T_2; // @[TLB.scala:635:29] wire pma_checker__io_resp_ae_ld_T_1; // @[TLB.scala:641:41] wire pma_checker__io_resp_ae_st_T_1; // @[TLB.scala:642:41] wire pma_checker__io_resp_ae_inst_T_2; // @[TLB.scala:643:41] wire pma_checker__io_resp_ma_ld_T; // @[TLB.scala:645:31] wire pma_checker__io_resp_ma_st_T; // @[TLB.scala:646:31] wire pma_checker__io_resp_cacheable_T_1; // @[TLB.scala:648:41] wire pma_checker__io_resp_must_alloc_T_1; // @[TLB.scala:649:51] wire pma_checker__io_resp_prefetchable_T_2; // @[TLB.scala:650:59] wire [33:0] pma_checker_io_req_bits_vaddr; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_req_bits_prv; // @[DCache.scala:120:32] wire pma_checker_io_req_bits_v; // @[DCache.scala:120:32] wire pma_checker_io_resp_pf_ld; // @[DCache.scala:120:32] wire pma_checker_io_resp_pf_st; // @[DCache.scala:120:32] wire pma_checker_io_resp_pf_inst; // @[DCache.scala:120:32] wire pma_checker_io_resp_ae_ld; // @[DCache.scala:120:32] wire pma_checker_io_resp_ae_st; // @[DCache.scala:120:32] wire pma_checker_io_resp_ae_inst; // @[DCache.scala:120:32] wire pma_checker_io_resp_ma_ld; // @[DCache.scala:120:32] wire pma_checker_io_resp_ma_st; // @[DCache.scala:120:32] wire [31:0] pma_checker_io_resp_paddr; // @[DCache.scala:120:32] wire [33:0] pma_checker_io_resp_gpa; // @[DCache.scala:120:32] wire pma_checker_io_resp_cacheable; // @[DCache.scala:120:32] wire pma_checker_io_resp_must_alloc; // @[DCache.scala:120:32] wire pma_checker_io_resp_prefetchable; // @[DCache.scala:120:32] wire [20:0] pma_checker_vpn = pma_checker_io_req_bits_vaddr[32:12]; // @[TLB.scala:335:30] wire [20:0] pma_checker__sector_hits_T_3 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [20:0] pma_checker__sector_hits_T_11 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [20:0] pma_checker__sector_hits_T_19 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [20:0] pma_checker__sector_hits_T_27 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [20:0] pma_checker__sector_hits_T_35 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [20:0] pma_checker__sector_hits_T_43 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [20:0] pma_checker__sector_hits_T_51 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [20:0] pma_checker__sector_hits_T_59 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [20:0] pma_checker__superpage_hits_T = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [20:0] pma_checker__superpage_hits_T_5 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [20:0] pma_checker__superpage_hits_T_10 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [20:0] pma_checker__superpage_hits_T_15 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [20:0] pma_checker__hitsVec_T = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [20:0] pma_checker__hitsVec_T_6 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [20:0] pma_checker__hitsVec_T_12 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [20:0] pma_checker__hitsVec_T_18 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [20:0] pma_checker__hitsVec_T_24 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [20:0] pma_checker__hitsVec_T_30 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [20:0] pma_checker__hitsVec_T_36 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [20:0] pma_checker__hitsVec_T_42 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [20:0] pma_checker__hitsVec_T_48 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [20:0] pma_checker__hitsVec_T_54 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [20:0] pma_checker__hitsVec_T_60 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [20:0] pma_checker__hitsVec_T_66 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [20:0] pma_checker__hitsVec_T_72 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire pma_checker_priv_s = pma_checker_io_req_bits_prv[0]; // @[TLB.scala:370:20] wire pma_checker_priv_uses_vm = ~(pma_checker_io_req_bits_prv[1]); // @[TLB.scala:372:27] wire [19:0] pma_checker__mpu_ppn_T_23; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_22; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_21; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_20; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_19; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_18; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_17; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_16; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_15; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_14; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_13; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_12; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_11; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_10; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_9; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_8; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_7; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_6; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_5; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_4; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_3; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_2; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_1; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_1 = pma_checker__mpu_ppn_WIRE_1[0]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_fragmented_superpage = pma_checker__mpu_ppn_T_1; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_2 = pma_checker__mpu_ppn_WIRE_1[1]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_c = pma_checker__mpu_ppn_T_2; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_3 = pma_checker__mpu_ppn_WIRE_1[2]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_eff = pma_checker__mpu_ppn_T_3; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_4 = pma_checker__mpu_ppn_WIRE_1[3]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_paa = pma_checker__mpu_ppn_T_4; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_5 = pma_checker__mpu_ppn_WIRE_1[4]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_pal = pma_checker__mpu_ppn_T_5; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_6 = pma_checker__mpu_ppn_WIRE_1[5]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_ppp = pma_checker__mpu_ppn_T_6; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_7 = pma_checker__mpu_ppn_WIRE_1[6]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_pr = pma_checker__mpu_ppn_T_7; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_8 = pma_checker__mpu_ppn_WIRE_1[7]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_px = pma_checker__mpu_ppn_T_8; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_9 = pma_checker__mpu_ppn_WIRE_1[8]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_pw = pma_checker__mpu_ppn_T_9; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_10 = pma_checker__mpu_ppn_WIRE_1[9]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_hr = pma_checker__mpu_ppn_T_10; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_11 = pma_checker__mpu_ppn_WIRE_1[10]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_hx = pma_checker__mpu_ppn_T_11; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_12 = pma_checker__mpu_ppn_WIRE_1[11]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_hw = pma_checker__mpu_ppn_T_12; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_13 = pma_checker__mpu_ppn_WIRE_1[12]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_sr = pma_checker__mpu_ppn_T_13; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_14 = pma_checker__mpu_ppn_WIRE_1[13]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_sx = pma_checker__mpu_ppn_T_14; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_15 = pma_checker__mpu_ppn_WIRE_1[14]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_sw = pma_checker__mpu_ppn_T_15; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_16 = pma_checker__mpu_ppn_WIRE_1[15]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_gf = pma_checker__mpu_ppn_T_16; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_17 = pma_checker__mpu_ppn_WIRE_1[16]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_pf = pma_checker__mpu_ppn_T_17; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_18 = pma_checker__mpu_ppn_WIRE_1[17]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_ae_stage2 = pma_checker__mpu_ppn_T_18; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_19 = pma_checker__mpu_ppn_WIRE_1[18]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_ae_final = pma_checker__mpu_ppn_T_19; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_20 = pma_checker__mpu_ppn_WIRE_1[19]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_ae_ptw = pma_checker__mpu_ppn_T_20; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_21 = pma_checker__mpu_ppn_WIRE_1[20]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_g = pma_checker__mpu_ppn_T_21; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_22 = pma_checker__mpu_ppn_WIRE_1[21]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_u = pma_checker__mpu_ppn_T_22; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_23 = pma_checker__mpu_ppn_WIRE_1[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__mpu_ppn_WIRE_ppn = pma_checker__mpu_ppn_T_23; // @[TLB.scala:170:77] wire [21:0] pma_checker__mpu_ppn_T_24 = pma_checker_io_req_bits_vaddr[33:12]; // @[TLB.scala:413:146] wire [21:0] pma_checker__mpu_ppn_T_25 = pma_checker__mpu_ppn_T_24; // @[TLB.scala:413:{20,146}] wire [21:0] pma_checker_mpu_ppn = pma_checker__mpu_ppn_T_25; // @[TLB.scala:412:20, :413:20] wire [11:0] pma_checker__mpu_physaddr_T = pma_checker_io_req_bits_vaddr[11:0]; // @[TLB.scala:414:52] wire [11:0] pma_checker__io_resp_paddr_T = pma_checker_io_req_bits_vaddr[11:0]; // @[TLB.scala:414:52, :652:46] wire [11:0] pma_checker__io_resp_gpa_offset_T_1 = pma_checker_io_req_bits_vaddr[11:0]; // @[TLB.scala:414:52, :658:82] wire [33:0] pma_checker_mpu_physaddr = {pma_checker_mpu_ppn, pma_checker__mpu_physaddr_T}; // @[TLB.scala:412:20, :414:{25,52}] wire [33:0] pma_checker__homogeneous_T = pma_checker_mpu_physaddr; // @[TLB.scala:414:25] wire [33:0] pma_checker__homogeneous_T_55 = pma_checker_mpu_physaddr; // @[TLB.scala:414:25] wire [33:0] pma_checker__deny_access_to_debug_T_1 = pma_checker_mpu_physaddr; // @[TLB.scala:414:25] wire [2:0] pma_checker__mpu_priv_T_2 = {1'h0, pma_checker_io_req_bits_prv}; // @[TLB.scala:415:103] wire [2:0] pma_checker_mpu_priv = pma_checker__mpu_priv_T_2; // @[TLB.scala:415:{27,103}] wire [34:0] pma_checker__homogeneous_T_1 = {1'h0, pma_checker__homogeneous_T}; // @[Parameters.scala:137:{31,41}] wire [34:0] pma_checker__homogeneous_T_2 = pma_checker__homogeneous_T_1 & 35'h7FFFFE000; // @[Parameters.scala:137:{41,46}] wire [34:0] pma_checker__homogeneous_T_3 = pma_checker__homogeneous_T_2; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_4 = pma_checker__homogeneous_T_3 == 35'h0; // @[Parameters.scala:137:{46,59}] wire pma_checker__homogeneous_T_40 = pma_checker__homogeneous_T_4; // @[TLBPermissions.scala:101:65] wire [33:0] _GEN = {pma_checker_mpu_physaddr[33:14], pma_checker_mpu_physaddr[13:0] ^ 14'h3000}; // @[TLB.scala:414:25] wire [33:0] pma_checker__homogeneous_T_5; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_5 = _GEN; // @[Parameters.scala:137:31] wire [33:0] pma_checker__homogeneous_T_60; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_60 = _GEN; // @[Parameters.scala:137:31] wire [34:0] pma_checker__homogeneous_T_6 = {1'h0, pma_checker__homogeneous_T_5}; // @[Parameters.scala:137:{31,41}] wire [34:0] pma_checker__homogeneous_T_7 = pma_checker__homogeneous_T_6 & 35'h7FFFFF000; // @[Parameters.scala:137:{41,46}] wire [34:0] pma_checker__homogeneous_T_8 = pma_checker__homogeneous_T_7; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_9 = pma_checker__homogeneous_T_8 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [33:0] _GEN_0 = {pma_checker_mpu_physaddr[33:17], pma_checker_mpu_physaddr[16:0] ^ 17'h10000}; // @[TLB.scala:414:25] wire [33:0] pma_checker__homogeneous_T_10; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_10 = _GEN_0; // @[Parameters.scala:137:31] wire [33:0] pma_checker__homogeneous_T_48; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_48 = _GEN_0; // @[Parameters.scala:137:31] wire [33:0] pma_checker__homogeneous_T_65; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_65 = _GEN_0; // @[Parameters.scala:137:31] wire [33:0] pma_checker__homogeneous_T_79; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_79 = _GEN_0; // @[Parameters.scala:137:31] wire [33:0] pma_checker__homogeneous_T_86; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_86 = _GEN_0; // @[Parameters.scala:137:31] wire [34:0] pma_checker__homogeneous_T_11 = {1'h0, pma_checker__homogeneous_T_10}; // @[Parameters.scala:137:{31,41}] wire [34:0] pma_checker__homogeneous_T_12 = pma_checker__homogeneous_T_11 & 35'h7FFFF0000; // @[Parameters.scala:137:{41,46}] wire [34:0] pma_checker__homogeneous_T_13 = pma_checker__homogeneous_T_12; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_14 = pma_checker__homogeneous_T_13 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [33:0] pma_checker__homogeneous_T_15 = {pma_checker_mpu_physaddr[33:21], pma_checker_mpu_physaddr[20:0] ^ 21'h100000}; // @[TLB.scala:414:25] wire [34:0] pma_checker__homogeneous_T_16 = {1'h0, pma_checker__homogeneous_T_15}; // @[Parameters.scala:137:{31,41}] wire [34:0] pma_checker__homogeneous_T_17 = pma_checker__homogeneous_T_16 & 35'h7FFFEF000; // @[Parameters.scala:137:{41,46}] wire [34:0] pma_checker__homogeneous_T_18 = pma_checker__homogeneous_T_17; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_19 = pma_checker__homogeneous_T_18 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [33:0] pma_checker__homogeneous_T_20 = {pma_checker_mpu_physaddr[33:26], pma_checker_mpu_physaddr[25:0] ^ 26'h2000000}; // @[TLB.scala:414:25] wire [34:0] pma_checker__homogeneous_T_21 = {1'h0, pma_checker__homogeneous_T_20}; // @[Parameters.scala:137:{31,41}] wire [34:0] pma_checker__homogeneous_T_22 = pma_checker__homogeneous_T_21 & 35'h7FFFF0000; // @[Parameters.scala:137:{41,46}] wire [34:0] pma_checker__homogeneous_T_23 = pma_checker__homogeneous_T_22; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_24 = pma_checker__homogeneous_T_23 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [33:0] pma_checker__homogeneous_T_25 = {pma_checker_mpu_physaddr[33:28], pma_checker_mpu_physaddr[27:0] ^ 28'hC000000}; // @[TLB.scala:414:25] wire [34:0] pma_checker__homogeneous_T_26 = {1'h0, pma_checker__homogeneous_T_25}; // @[Parameters.scala:137:{31,41}] wire [34:0] pma_checker__homogeneous_T_27 = pma_checker__homogeneous_T_26 & 35'h7FC000000; // @[Parameters.scala:137:{41,46}] wire [34:0] pma_checker__homogeneous_T_28 = pma_checker__homogeneous_T_27; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_29 = pma_checker__homogeneous_T_28 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [33:0] pma_checker__homogeneous_T_30 = {pma_checker_mpu_physaddr[33:29], pma_checker_mpu_physaddr[28:0] ^ 29'h10020000}; // @[TLB.scala:414:25] wire [34:0] pma_checker__homogeneous_T_31 = {1'h0, pma_checker__homogeneous_T_30}; // @[Parameters.scala:137:{31,41}] wire [34:0] pma_checker__homogeneous_T_32 = pma_checker__homogeneous_T_31 & 35'h7FFFFF000; // @[Parameters.scala:137:{41,46}] wire [34:0] pma_checker__homogeneous_T_33 = pma_checker__homogeneous_T_32; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_34 = pma_checker__homogeneous_T_33 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [33:0] _GEN_1 = {pma_checker_mpu_physaddr[33:32], pma_checker_mpu_physaddr[31:0] ^ 32'h80000000}; // @[TLB.scala:414:25, :417:15] wire [33:0] pma_checker__homogeneous_T_35; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_35 = _GEN_1; // @[Parameters.scala:137:31] wire [33:0] pma_checker__homogeneous_T_70; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_70 = _GEN_1; // @[Parameters.scala:137:31] wire [34:0] pma_checker__homogeneous_T_36 = {1'h0, pma_checker__homogeneous_T_35}; // @[Parameters.scala:137:{31,41}] wire [34:0] pma_checker__homogeneous_T_37 = pma_checker__homogeneous_T_36 & 35'h7FFFFC000; // @[Parameters.scala:137:{41,46}] wire [34:0] pma_checker__homogeneous_T_38 = pma_checker__homogeneous_T_37; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_39 = pma_checker__homogeneous_T_38 == 35'h0; // @[Parameters.scala:137:{46,59}] wire pma_checker__homogeneous_T_41 = pma_checker__homogeneous_T_40 \| pma_checker__homogeneous_T_9; // @[TLBPermissions.scala:101:65] wire pma_checker__homogeneous_T_42 = pma_checker__homogeneous_T_41 \| pma_checker__homogeneous_T_14; // @[TLBPermissions.scala:101:65] wire pma_checker__homogeneous_T_43 = pma_checker__homogeneous_T_42 \| pma_checker__homogeneous_T_19; // @[TLBPermissions.scala:101:65] wire pma_checker__homogeneous_T_44 = pma_checker__homogeneous_T_43 \| pma_checker__homogeneous_T_24; // @[TLBPermissions.scala:101:65] wire pma_checker__homogeneous_T_45 = pma_checker__homogeneous_T_44 \| pma_checker__homogeneous_T_29; // @[TLBPermissions.scala:101:65] wire pma_checker__homogeneous_T_46 = pma_checker__homogeneous_T_45 \| pma_checker__homogeneous_T_34; // @[TLBPermissions.scala:101:65] wire pma_checker_homogeneous = pma_checker__homogeneous_T_46 \| pma_checker__homogeneous_T_39; // @[TLBPermissions.scala:101:65] wire [34:0] pma_checker__homogeneous_T_49 = {1'h0, pma_checker__homogeneous_T_48}; // @[Parameters.scala:137:{31,41}] wire [34:0] pma_checker__homogeneous_T_50 = pma_checker__homogeneous_T_49 & 35'h98110000; // @[Parameters.scala:137:{41,46}] wire [34:0] pma_checker__homogeneous_T_51 = pma_checker__homogeneous_T_50; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_52 = pma_checker__homogeneous_T_51 == 35'h0; // @[Parameters.scala:137:{46,59}] wire pma_checker__homogeneous_T_53 = pma_checker__homogeneous_T_52; // @[TLBPermissions.scala:87:66] wire pma_checker__homogeneous_T_54 = ~pma_checker__homogeneous_T_53; // @[TLBPermissions.scala:87:{22,66}] wire [34:0] pma_checker__homogeneous_T_56 = {1'h0, pma_checker__homogeneous_T_55}; // @[Parameters.scala:137:{31,41}] wire [34:0] pma_checker__homogeneous_T_57 = pma_checker__homogeneous_T_56 & 35'h9A113000; // @[Parameters.scala:137:{41,46}] wire [34:0] pma_checker__homogeneous_T_58 = pma_checker__homogeneous_T_57; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_59 = pma_checker__homogeneous_T_58 == 35'h0; // @[Parameters.scala:137:{46,59}] wire pma_checker__homogeneous_T_75 = pma_checker__homogeneous_T_59; // @[TLBPermissions.scala:85:66] wire [34:0] pma_checker__homogeneous_T_61 = {1'h0, pma_checker__homogeneous_T_60}; // @[Parameters.scala:137:{31,41}] wire [34:0] pma_checker__homogeneous_T_62 = pma_checker__homogeneous_T_61 & 35'h9A113000; // @[Parameters.scala:137:{41,46}] wire [34:0] pma_checker__homogeneous_T_63 = pma_checker__homogeneous_T_62; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_64 = pma_checker__homogeneous_T_63 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] pma_checker__homogeneous_T_66 = {1'h0, pma_checker__homogeneous_T_65}; // @[Parameters.scala:137:{31,41}] wire [34:0] pma_checker__homogeneous_T_67 = pma_checker__homogeneous_T_66 & 35'h9A110000; // @[Parameters.scala:137:{41,46}] wire [34:0] pma_checker__homogeneous_T_68 = pma_checker__homogeneous_T_67; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_69 = pma_checker__homogeneous_T_68 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] pma_checker__homogeneous_T_71 = {1'h0, pma_checker__homogeneous_T_70}; // @[Parameters.scala:137:{31,41}] wire [34:0] pma_checker__homogeneous_T_72 = pma_checker__homogeneous_T_71 & 35'h9A110000; // @[Parameters.scala:137:{41,46}] wire [34:0] pma_checker__homogeneous_T_73 = pma_checker__homogeneous_T_72; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_74 = pma_checker__homogeneous_T_73 == 35'h0; // @[Parameters.scala:137:{46,59}] wire pma_checker__homogeneous_T_76 = pma_checker__homogeneous_T_75 \| pma_checker__homogeneous_T_64; // @[TLBPermissions.scala:85:66] wire pma_checker__homogeneous_T_77 = pma_checker__homogeneous_T_76 \| pma_checker__homogeneous_T_69; // @[TLBPermissions.scala:85:66] wire pma_checker__homogeneous_T_78 = pma_checker__homogeneous_T_77 \| pma_checker__homogeneous_T_74; // @[TLBPermissions.scala:85:66] wire [34:0] pma_checker__homogeneous_T_80 = {1'h0, pma_checker__homogeneous_T_79}; // @[Parameters.scala:137:{31,41}] wire [34:0] pma_checker__homogeneous_T_81 = pma_checker__homogeneous_T_80 & 35'h98110000; // @[Parameters.scala:137:{41,46}] wire [34:0] pma_checker__homogeneous_T_82 = pma_checker__homogeneous_T_81; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_83 = pma_checker__homogeneous_T_82 == 35'h0; // @[Parameters.scala:137:{46,59}] wire pma_checker__homogeneous_T_84 = pma_checker__homogeneous_T_83; // @[TLBPermissions.scala:87:66] wire pma_checker__homogeneous_T_85 = ~pma_checker__homogeneous_T_84; // @[TLBPermissions.scala:87:{22,66}] wire [34:0] pma_checker__homogeneous_T_87 = {1'h0, pma_checker__homogeneous_T_86}; // @[Parameters.scala:137:{31,41}] wire [34:0] pma_checker__homogeneous_T_88 = pma_checker__homogeneous_T_87 & 35'h98110000; // @[Parameters.scala:137:{41,46}] wire [34:0] pma_checker__homogeneous_T_89 = pma_checker__homogeneous_T_88; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_90 = pma_checker__homogeneous_T_89 == 35'h0; // @[Parameters.scala:137:{46,59}] wire pma_checker__homogeneous_T_91 = pma_checker__homogeneous_T_90; // @[TLBPermissions.scala:87:66] wire pma_checker__homogeneous_T_92 = ~pma_checker__homogeneous_T_91; // @[TLBPermissions.scala:87:{22,66}] wire pma_checker__deny_access_to_debug_T = ~(pma_checker_mpu_priv[2]); // @[TLB.scala:415:27, :428:39] wire [34:0] pma_checker__deny_access_to_debug_T_2 = {1'h0, pma_checker__deny_access_to_debug_T_1}; // @[Parameters.scala:137:{31,41}] wire [34:0] pma_checker__deny_access_to_debug_T_3 = pma_checker__deny_access_to_debug_T_2 & 35'h7FFFFF000; // @[Parameters.scala:137:{41,46}] wire [34:0] pma_checker__deny_access_to_debug_T_4 = pma_checker__deny_access_to_debug_T_3; // @[Parameters.scala:137:46] wire pma_checker__deny_access_to_debug_T_5 = pma_checker__deny_access_to_debug_T_4 == 35'h0; // @[Parameters.scala:137:{46,59}] wire pma_checker_deny_access_to_debug = pma_checker__deny_access_to_debug_T & pma_checker__deny_access_to_debug_T_5; // @[TLB.scala:428:{39,50}] wire pma_checker__prot_r_T = ~pma_checker_deny_access_to_debug; // @[TLB.scala:428:50, :429:33] wire pma_checker__prot_r_T_1 = _pma_checker_pma_io_resp_r & pma_checker__prot_r_T; // @[TLB.scala:422:19, :429:{30,33}] wire pma_checker_prot_r = pma_checker__prot_r_T_1 & _pma_checker_pmp_io_r; // @[TLB.scala:416:19, :429:{30,55}] wire pma_checker_newEntry_pr = pma_checker_prot_r; // @[TLB.scala:429:55, :449:24] wire pma_checker__prot_w_T = ~pma_checker_deny_access_to_debug; // @[TLB.scala:428:50, :429:33, :430:33] wire pma_checker__prot_w_T_1 = _pma_checker_pma_io_resp_w & pma_checker__prot_w_T; // @[TLB.scala:422:19, :430:{30,33}] wire pma_checker_prot_w = pma_checker__prot_w_T_1 & _pma_checker_pmp_io_w; // @[TLB.scala:416:19, :430:{30,55}] wire pma_checker_newEntry_pw = pma_checker_prot_w; // @[TLB.scala:430:55, :449:24] wire pma_checker__prot_x_T = ~pma_checker_deny_access_to_debug; // @[TLB.scala:428:50, :429:33, :434:33] wire pma_checker__prot_x_T_1 = _pma_checker_pma_io_resp_x & pma_checker__prot_x_T; // @[TLB.scala:422:19, :434:{30,33}] wire pma_checker_prot_x = pma_checker__prot_x_T_1 & _pma_checker_pmp_io_x; // @[TLB.scala:416:19, :434:{30,55}] wire pma_checker_newEntry_px = pma_checker_prot_x; // @[TLB.scala:434:55, :449:24] wire pma_checker__sector_hits_T_1 = pma_checker__sector_hits_T; // @[package.scala:81:59] wire pma_checker__sector_hits_T_2 = pma_checker__sector_hits_T_1; // @[package.scala:81:59] wire [18:0] pma_checker__sector_hits_T_4 = pma_checker__sector_hits_T_3[20:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__sector_hits_T_5 = pma_checker__sector_hits_T_4 == 19'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__sector_hits_T_7 = pma_checker__sector_hits_T_5 & pma_checker__sector_hits_T_6; // @[TLB.scala:174:{86,95,105}] wire pma_checker_sector_hits_0 = pma_checker__sector_hits_T_2 & pma_checker__sector_hits_T_7; // @[package.scala:81:59] wire pma_checker__sector_hits_T_9 = pma_checker__sector_hits_T_8; // @[package.scala:81:59] wire pma_checker__sector_hits_T_10 = pma_checker__sector_hits_T_9; // @[package.scala:81:59] wire [18:0] pma_checker__sector_hits_T_12 = pma_checker__sector_hits_T_11[20:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__sector_hits_T_13 = pma_checker__sector_hits_T_12 == 19'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__sector_hits_T_15 = pma_checker__sector_hits_T_13 & pma_checker__sector_hits_T_14; // @[TLB.scala:174:{86,95,105}] wire pma_checker_sector_hits_1 = pma_checker__sector_hits_T_10 & pma_checker__sector_hits_T_15; // @[package.scala:81:59] wire pma_checker__sector_hits_T_17 = pma_checker__sector_hits_T_16; // @[package.scala:81:59] wire pma_checker__sector_hits_T_18 = pma_checker__sector_hits_T_17; // @[package.scala:81:59] wire [18:0] pma_checker__sector_hits_T_20 = pma_checker__sector_hits_T_19[20:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__sector_hits_T_21 = pma_checker__sector_hits_T_20 == 19'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__sector_hits_T_23 = pma_checker__sector_hits_T_21 & pma_checker__sector_hits_T_22; // @[TLB.scala:174:{86,95,105}] wire pma_checker_sector_hits_2 = pma_checker__sector_hits_T_18 & pma_checker__sector_hits_T_23; // @[package.scala:81:59] wire pma_checker__sector_hits_T_25 = pma_checker__sector_hits_T_24; // @[package.scala:81:59] wire pma_checker__sector_hits_T_26 = pma_checker__sector_hits_T_25; // @[package.scala:81:59] wire [18:0] pma_checker__sector_hits_T_28 = pma_checker__sector_hits_T_27[20:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__sector_hits_T_29 = pma_checker__sector_hits_T_28 == 19'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__sector_hits_T_31 = pma_checker__sector_hits_T_29 & pma_checker__sector_hits_T_30; // @[TLB.scala:174:{86,95,105}] wire pma_checker_sector_hits_3 = pma_checker__sector_hits_T_26 & pma_checker__sector_hits_T_31; // @[package.scala:81:59] wire pma_checker__sector_hits_T_33 = pma_checker__sector_hits_T_32; // @[package.scala:81:59] wire pma_checker__sector_hits_T_34 = pma_checker__sector_hits_T_33; // @[package.scala:81:59] wire [18:0] pma_checker__sector_hits_T_36 = pma_checker__sector_hits_T_35[20:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__sector_hits_T_37 = pma_checker__sector_hits_T_36 == 19'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__sector_hits_T_39 = pma_checker__sector_hits_T_37 & pma_checker__sector_hits_T_38; // @[TLB.scala:174:{86,95,105}] wire pma_checker_sector_hits_4 = pma_checker__sector_hits_T_34 & pma_checker__sector_hits_T_39; // @[package.scala:81:59] wire pma_checker__sector_hits_T_41 = pma_checker__sector_hits_T_40; // @[package.scala:81:59] wire pma_checker__sector_hits_T_42 = pma_checker__sector_hits_T_41; // @[package.scala:81:59] wire [18:0] pma_checker__sector_hits_T_44 = pma_checker__sector_hits_T_43[20:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__sector_hits_T_45 = pma_checker__sector_hits_T_44 == 19'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__sector_hits_T_47 = pma_checker__sector_hits_T_45 & pma_checker__sector_hits_T_46; // @[TLB.scala:174:{86,95,105}] wire pma_checker_sector_hits_5 = pma_checker__sector_hits_T_42 & pma_checker__sector_hits_T_47; // @[package.scala:81:59] wire pma_checker__sector_hits_T_49 = pma_checker__sector_hits_T_48; // @[package.scala:81:59] wire pma_checker__sector_hits_T_50 = pma_checker__sector_hits_T_49; // @[package.scala:81:59] wire [18:0] pma_checker__sector_hits_T_52 = pma_checker__sector_hits_T_51[20:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__sector_hits_T_53 = pma_checker__sector_hits_T_52 == 19'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__sector_hits_T_55 = pma_checker__sector_hits_T_53 & pma_checker__sector_hits_T_54; // @[TLB.scala:174:{86,95,105}] wire pma_checker_sector_hits_6 = pma_checker__sector_hits_T_50 & pma_checker__sector_hits_T_55; // @[package.scala:81:59] wire pma_checker__sector_hits_T_57 = pma_checker__sector_hits_T_56; // @[package.scala:81:59] wire pma_checker__sector_hits_T_58 = pma_checker__sector_hits_T_57; // @[package.scala:81:59] wire [18:0] pma_checker__sector_hits_T_60 = pma_checker__sector_hits_T_59[20:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__sector_hits_T_61 = pma_checker__sector_hits_T_60 == 19'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__sector_hits_T_63 = pma_checker__sector_hits_T_61 & pma_checker__sector_hits_T_62; // @[TLB.scala:174:{86,95,105}] wire pma_checker_sector_hits_7 = pma_checker__sector_hits_T_58 & pma_checker__sector_hits_T_63; // @[package.scala:81:59] wire [20:0] pma_checker__superpage_hits_T_1 = pma_checker__superpage_hits_T; // @[TLB.scala:174:{61,68}] wire pma_checker__superpage_hits_T_2 = pma_checker__superpage_hits_T_1 == 21'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__superpage_hits_T_4 = pma_checker__superpage_hits_T_2 & pma_checker__superpage_hits_T_3; // @[TLB.scala:174:{86,95,105}] wire [20:0] pma_checker__superpage_hits_T_6 = pma_checker__superpage_hits_T_5; // @[TLB.scala:174:{61,68}] wire pma_checker__superpage_hits_T_7 = pma_checker__superpage_hits_T_6 == 21'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__superpage_hits_T_9 = pma_checker__superpage_hits_T_7 & pma_checker__superpage_hits_T_8; // @[TLB.scala:174:{86,95,105}] wire [20:0] pma_checker__superpage_hits_T_11 = pma_checker__superpage_hits_T_10; // @[TLB.scala:174:{61,68}] wire pma_checker__superpage_hits_T_12 = pma_checker__superpage_hits_T_11 == 21'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__superpage_hits_T_14 = pma_checker__superpage_hits_T_12 & pma_checker__superpage_hits_T_13; // @[TLB.scala:174:{86,95,105}] wire [20:0] pma_checker__superpage_hits_T_16 = pma_checker__superpage_hits_T_15; // @[TLB.scala:174:{61,68}] wire pma_checker__superpage_hits_T_17 = pma_checker__superpage_hits_T_16 == 21'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__superpage_hits_T_19 = pma_checker__superpage_hits_T_17 & pma_checker__superpage_hits_T_18; // @[TLB.scala:174:{86,95,105}] wire [1:0] pma_checker_hitsVec_idx = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker_hitsVec_idx_1 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker_hitsVec_idx_2 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker_hitsVec_idx_3 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker_hitsVec_idx_4 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker_hitsVec_idx_5 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker_hitsVec_idx_6 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker_hitsVec_idx_7 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker__entries_T = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker__entries_T_24 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker__entries_T_48 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker__entries_T_72 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker__entries_T_96 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker__entries_T_120 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker__entries_T_144 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker__entries_T_168 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [18:0] pma_checker__hitsVec_T_1 = pma_checker__hitsVec_T[20:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__hitsVec_T_2 = pma_checker__hitsVec_T_1 == 19'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__hitsVec_T_4 = pma_checker__hitsVec_T_2 & pma_checker__hitsVec_T_3; // @[TLB.scala:174:{86,95,105}] wire [18:0] pma_checker__hitsVec_T_7 = pma_checker__hitsVec_T_6[20:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__hitsVec_T_8 = pma_checker__hitsVec_T_7 == 19'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__hitsVec_T_10 = pma_checker__hitsVec_T_8 & pma_checker__hitsVec_T_9; // @[TLB.scala:174:{86,95,105}] wire [18:0] pma_checker__hitsVec_T_13 = pma_checker__hitsVec_T_12[20:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__hitsVec_T_14 = pma_checker__hitsVec_T_13 == 19'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__hitsVec_T_16 = pma_checker__hitsVec_T_14 & pma_checker__hitsVec_T_15; // @[TLB.scala:174:{86,95,105}] wire [18:0] pma_checker__hitsVec_T_19 = pma_checker__hitsVec_T_18[20:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__hitsVec_T_20 = pma_checker__hitsVec_T_19 == 19'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__hitsVec_T_22 = pma_checker__hitsVec_T_20 & pma_checker__hitsVec_T_21; // @[TLB.scala:174:{86,95,105}] wire [18:0] pma_checker__hitsVec_T_25 = pma_checker__hitsVec_T_24[20:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__hitsVec_T_26 = pma_checker__hitsVec_T_25 == 19'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__hitsVec_T_28 = pma_checker__hitsVec_T_26 & pma_checker__hitsVec_T_27; // @[TLB.scala:174:{86,95,105}] wire [18:0] pma_checker__hitsVec_T_31 = pma_checker__hitsVec_T_30[20:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__hitsVec_T_32 = pma_checker__hitsVec_T_31 == 19'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__hitsVec_T_34 = pma_checker__hitsVec_T_32 & pma_checker__hitsVec_T_33; // @[TLB.scala:174:{86,95,105}] wire [18:0] pma_checker__hitsVec_T_37 = pma_checker__hitsVec_T_36[20:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__hitsVec_T_38 = pma_checker__hitsVec_T_37 == 19'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__hitsVec_T_40 = pma_checker__hitsVec_T_38 & pma_checker__hitsVec_T_39; // @[TLB.scala:174:{86,95,105}] wire [18:0] pma_checker__hitsVec_T_43 = pma_checker__hitsVec_T_42[20:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__hitsVec_T_44 = pma_checker__hitsVec_T_43 == 19'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__hitsVec_T_46 = pma_checker__hitsVec_T_44 & pma_checker__hitsVec_T_45; // @[TLB.scala:174:{86,95,105}] wire [20:0] pma_checker__hitsVec_T_49 = pma_checker__hitsVec_T_48; // @[TLB.scala:174:{61,68}] wire pma_checker__hitsVec_T_50 = pma_checker__hitsVec_T_49 == 21'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__hitsVec_T_52 = pma_checker__hitsVec_T_50 & pma_checker__hitsVec_T_51; // @[TLB.scala:174:{86,95,105}] wire [20:0] pma_checker__hitsVec_T_55 = pma_checker__hitsVec_T_54; // @[TLB.scala:174:{61,68}] wire pma_checker__hitsVec_T_56 = pma_checker__hitsVec_T_55 == 21'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__hitsVec_T_58 = pma_checker__hitsVec_T_56 & pma_checker__hitsVec_T_57; // @[TLB.scala:174:{86,95,105}] wire [20:0] pma_checker__hitsVec_T_61 = pma_checker__hitsVec_T_60; // @[TLB.scala:174:{61,68}] wire pma_checker__hitsVec_T_62 = pma_checker__hitsVec_T_61 == 21'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__hitsVec_T_64 = pma_checker__hitsVec_T_62 & pma_checker__hitsVec_T_63; // @[TLB.scala:174:{86,95,105}] wire [20:0] pma_checker__hitsVec_T_67 = pma_checker__hitsVec_T_66; // @[TLB.scala:174:{61,68}] wire pma_checker__hitsVec_T_68 = pma_checker__hitsVec_T_67 == 21'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__hitsVec_T_70 = pma_checker__hitsVec_T_68 & pma_checker__hitsVec_T_69; // @[TLB.scala:174:{86,95,105}] wire [20:0] pma_checker__hitsVec_T_73 = pma_checker__hitsVec_T_72; // @[TLB.scala:174:{61,68}] wire pma_checker__hitsVec_T_74 = pma_checker__hitsVec_T_73 == 21'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__hitsVec_T_76 = pma_checker__hitsVec_T_74 & pma_checker__hitsVec_T_75; // @[TLB.scala:174:{86,95,105}] wire pma_checker__hitsVec_T_77 = pma_checker__hitsVec_T_76; // @[TLB.scala:174:95, :188:18] wire pma_checker_newEntry_ppp; // @[TLB.scala:449:24] wire pma_checker_newEntry_pal; // @[TLB.scala:449:24] wire pma_checker_newEntry_paa; // @[TLB.scala:449:24] wire pma_checker_newEntry_eff; // @[TLB.scala:449:24] wire [1:0] _GEN_2 = {pma_checker_newEntry_pal, pma_checker_newEntry_paa}; // @[TLB.scala:217:24, :449:24] wire [1:0] pma_checker_special_entry_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_special_entry_data_0_lo_lo_hi_hi = _GEN_2; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_0_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_0_data_0_lo_lo_hi_hi = _GEN_2; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_1_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_1_data_0_lo_lo_hi_hi = _GEN_2; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_2_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_2_data_0_lo_lo_hi_hi = _GEN_2; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_3_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_3_data_0_lo_lo_hi_hi = _GEN_2; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_0_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_0_data_lo_lo_hi_hi = _GEN_2; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_1_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_1_data_lo_lo_hi_hi = _GEN_2; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_2_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_2_data_lo_lo_hi_hi = _GEN_2; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_3_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_3_data_lo_lo_hi_hi = _GEN_2; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_4_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_4_data_lo_lo_hi_hi = _GEN_2; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_5_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_5_data_lo_lo_hi_hi = _GEN_2; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_6_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_6_data_lo_lo_hi_hi = _GEN_2; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_7_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_7_data_lo_lo_hi_hi = _GEN_2; // @[TLB.scala:217:24] wire [2:0] pma_checker_special_entry_data_0_lo_lo_hi = {pma_checker_special_entry_data_0_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_special_entry_data_0_lo_lo = {pma_checker_special_entry_data_0_lo_lo_hi, 2'h0}; // @[TLB.scala:217:24] wire [1:0] _GEN_3 = {pma_checker_newEntry_px, pma_checker_newEntry_pr}; // @[TLB.scala:217:24, :449:24] wire [1:0] pma_checker_special_entry_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign pma_checker_special_entry_data_0_lo_hi_lo_hi = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_0_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_0_data_0_lo_hi_lo_hi = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_1_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_1_data_0_lo_hi_lo_hi = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_2_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_2_data_0_lo_hi_lo_hi = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_3_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_3_data_0_lo_hi_lo_hi = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_0_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_0_data_lo_hi_lo_hi = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_1_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_1_data_lo_hi_lo_hi = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_2_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_2_data_lo_hi_lo_hi = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_3_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_3_data_lo_hi_lo_hi = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_4_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_4_data_lo_hi_lo_hi = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_5_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_5_data_lo_hi_lo_hi = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_6_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_6_data_lo_hi_lo_hi = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_7_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_7_data_lo_hi_lo_hi = _GEN_3; // @[TLB.scala:217:24] wire [2:0] pma_checker_special_entry_data_0_lo_hi_lo = {pma_checker_special_entry_data_0_lo_hi_lo_hi, pma_checker_newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] _GEN_4 = {2'h0, pma_checker_newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [2:0] pma_checker_special_entry_data_0_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_special_entry_data_0_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_0_data_0_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_0_data_0_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_1_data_0_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_1_data_0_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_2_data_0_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_2_data_0_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_3_data_0_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_3_data_0_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_0_data_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_0_data_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_1_data_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_1_data_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_2_data_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_2_data_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_3_data_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_3_data_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_4_data_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_4_data_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_5_data_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_5_data_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_6_data_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_6_data_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_7_data_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_7_data_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [5:0] pma_checker_special_entry_data_0_lo_hi = {pma_checker_special_entry_data_0_lo_hi_hi, pma_checker_special_entry_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_special_entry_data_0_lo = {pma_checker_special_entry_data_0_lo_hi, pma_checker_special_entry_data_0_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__special_entry_data_0_T = {31'h0, pma_checker_special_entry_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_0_data_0_lo_lo_hi = {pma_checker_superpage_entries_0_data_0_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_superpage_entries_0_data_0_lo_lo = {pma_checker_superpage_entries_0_data_0_lo_lo_hi, 2'h0}; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_0_data_0_lo_hi_lo = {pma_checker_superpage_entries_0_data_0_lo_hi_lo_hi, pma_checker_newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [5:0] pma_checker_superpage_entries_0_data_0_lo_hi = {pma_checker_superpage_entries_0_data_0_lo_hi_hi, pma_checker_superpage_entries_0_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_superpage_entries_0_data_0_lo = {pma_checker_superpage_entries_0_data_0_lo_hi, pma_checker_superpage_entries_0_data_0_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__superpage_entries_0_data_0_T = {31'h0, pma_checker_superpage_entries_0_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_1_data_0_lo_lo_hi = {pma_checker_superpage_entries_1_data_0_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_superpage_entries_1_data_0_lo_lo = {pma_checker_superpage_entries_1_data_0_lo_lo_hi, 2'h0}; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_1_data_0_lo_hi_lo = {pma_checker_superpage_entries_1_data_0_lo_hi_lo_hi, pma_checker_newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [5:0] pma_checker_superpage_entries_1_data_0_lo_hi = {pma_checker_superpage_entries_1_data_0_lo_hi_hi, pma_checker_superpage_entries_1_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_superpage_entries_1_data_0_lo = {pma_checker_superpage_entries_1_data_0_lo_hi, pma_checker_superpage_entries_1_data_0_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__superpage_entries_1_data_0_T = {31'h0, pma_checker_superpage_entries_1_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_2_data_0_lo_lo_hi = {pma_checker_superpage_entries_2_data_0_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_superpage_entries_2_data_0_lo_lo = {pma_checker_superpage_entries_2_data_0_lo_lo_hi, 2'h0}; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_2_data_0_lo_hi_lo = {pma_checker_superpage_entries_2_data_0_lo_hi_lo_hi, pma_checker_newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [5:0] pma_checker_superpage_entries_2_data_0_lo_hi = {pma_checker_superpage_entries_2_data_0_lo_hi_hi, pma_checker_superpage_entries_2_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_superpage_entries_2_data_0_lo = {pma_checker_superpage_entries_2_data_0_lo_hi, pma_checker_superpage_entries_2_data_0_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__superpage_entries_2_data_0_T = {31'h0, pma_checker_superpage_entries_2_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_3_data_0_lo_lo_hi = {pma_checker_superpage_entries_3_data_0_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_superpage_entries_3_data_0_lo_lo = {pma_checker_superpage_entries_3_data_0_lo_lo_hi, 2'h0}; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_3_data_0_lo_hi_lo = {pma_checker_superpage_entries_3_data_0_lo_hi_lo_hi, pma_checker_newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [5:0] pma_checker_superpage_entries_3_data_0_lo_hi = {pma_checker_superpage_entries_3_data_0_lo_hi_hi, pma_checker_superpage_entries_3_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_superpage_entries_3_data_0_lo = {pma_checker_superpage_entries_3_data_0_lo_hi, pma_checker_superpage_entries_3_data_0_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__superpage_entries_3_data_0_T = {31'h0, pma_checker_superpage_entries_3_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_0_data_lo_lo_hi = {pma_checker_sectored_entries_0_0_data_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_sectored_entries_0_0_data_lo_lo = {pma_checker_sectored_entries_0_0_data_lo_lo_hi, 2'h0}; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_0_data_lo_hi_lo = {pma_checker_sectored_entries_0_0_data_lo_hi_lo_hi, pma_checker_newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [5:0] pma_checker_sectored_entries_0_0_data_lo_hi = {pma_checker_sectored_entries_0_0_data_lo_hi_hi, pma_checker_sectored_entries_0_0_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_sectored_entries_0_0_data_lo = {pma_checker_sectored_entries_0_0_data_lo_hi, pma_checker_sectored_entries_0_0_data_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__sectored_entries_0_0_data_T = {31'h0, pma_checker_sectored_entries_0_0_data_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_1_data_lo_lo_hi = {pma_checker_sectored_entries_0_1_data_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_sectored_entries_0_1_data_lo_lo = {pma_checker_sectored_entries_0_1_data_lo_lo_hi, 2'h0}; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_1_data_lo_hi_lo = {pma_checker_sectored_entries_0_1_data_lo_hi_lo_hi, pma_checker_newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [5:0] pma_checker_sectored_entries_0_1_data_lo_hi = {pma_checker_sectored_entries_0_1_data_lo_hi_hi, pma_checker_sectored_entries_0_1_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_sectored_entries_0_1_data_lo = {pma_checker_sectored_entries_0_1_data_lo_hi, pma_checker_sectored_entries_0_1_data_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__sectored_entries_0_1_data_T = {31'h0, pma_checker_sectored_entries_0_1_data_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_2_data_lo_lo_hi = {pma_checker_sectored_entries_0_2_data_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_sectored_entries_0_2_data_lo_lo = {pma_checker_sectored_entries_0_2_data_lo_lo_hi, 2'h0}; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_2_data_lo_hi_lo = {pma_checker_sectored_entries_0_2_data_lo_hi_lo_hi, pma_checker_newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [5:0] pma_checker_sectored_entries_0_2_data_lo_hi = {pma_checker_sectored_entries_0_2_data_lo_hi_hi, pma_checker_sectored_entries_0_2_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_sectored_entries_0_2_data_lo = {pma_checker_sectored_entries_0_2_data_lo_hi, pma_checker_sectored_entries_0_2_data_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__sectored_entries_0_2_data_T = {31'h0, pma_checker_sectored_entries_0_2_data_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_3_data_lo_lo_hi = {pma_checker_sectored_entries_0_3_data_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_sectored_entries_0_3_data_lo_lo = {pma_checker_sectored_entries_0_3_data_lo_lo_hi, 2'h0}; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_3_data_lo_hi_lo = {pma_checker_sectored_entries_0_3_data_lo_hi_lo_hi, pma_checker_newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [5:0] pma_checker_sectored_entries_0_3_data_lo_hi = {pma_checker_sectored_entries_0_3_data_lo_hi_hi, pma_checker_sectored_entries_0_3_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_sectored_entries_0_3_data_lo = {pma_checker_sectored_entries_0_3_data_lo_hi, pma_checker_sectored_entries_0_3_data_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__sectored_entries_0_3_data_T = {31'h0, pma_checker_sectored_entries_0_3_data_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_4_data_lo_lo_hi = {pma_checker_sectored_entries_0_4_data_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_sectored_entries_0_4_data_lo_lo = {pma_checker_sectored_entries_0_4_data_lo_lo_hi, 2'h0}; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_4_data_lo_hi_lo = {pma_checker_sectored_entries_0_4_data_lo_hi_lo_hi, pma_checker_newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [5:0] pma_checker_sectored_entries_0_4_data_lo_hi = {pma_checker_sectored_entries_0_4_data_lo_hi_hi, pma_checker_sectored_entries_0_4_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_sectored_entries_0_4_data_lo = {pma_checker_sectored_entries_0_4_data_lo_hi, pma_checker_sectored_entries_0_4_data_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__sectored_entries_0_4_data_T = {31'h0, pma_checker_sectored_entries_0_4_data_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_5_data_lo_lo_hi = {pma_checker_sectored_entries_0_5_data_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_sectored_entries_0_5_data_lo_lo = {pma_checker_sectored_entries_0_5_data_lo_lo_hi, 2'h0}; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_5_data_lo_hi_lo = {pma_checker_sectored_entries_0_5_data_lo_hi_lo_hi, pma_checker_newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [5:0] pma_checker_sectored_entries_0_5_data_lo_hi = {pma_checker_sectored_entries_0_5_data_lo_hi_hi, pma_checker_sectored_entries_0_5_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_sectored_entries_0_5_data_lo = {pma_checker_sectored_entries_0_5_data_lo_hi, pma_checker_sectored_entries_0_5_data_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__sectored_entries_0_5_data_T = {31'h0, pma_checker_sectored_entries_0_5_data_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_6_data_lo_lo_hi = {pma_checker_sectored_entries_0_6_data_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_sectored_entries_0_6_data_lo_lo = {pma_checker_sectored_entries_0_6_data_lo_lo_hi, 2'h0}; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_6_data_lo_hi_lo = {pma_checker_sectored_entries_0_6_data_lo_hi_lo_hi, pma_checker_newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [5:0] pma_checker_sectored_entries_0_6_data_lo_hi = {pma_checker_sectored_entries_0_6_data_lo_hi_hi, pma_checker_sectored_entries_0_6_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_sectored_entries_0_6_data_lo = {pma_checker_sectored_entries_0_6_data_lo_hi, pma_checker_sectored_entries_0_6_data_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__sectored_entries_0_6_data_T = {31'h0, pma_checker_sectored_entries_0_6_data_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_7_data_lo_lo_hi = {pma_checker_sectored_entries_0_7_data_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_sectored_entries_0_7_data_lo_lo = {pma_checker_sectored_entries_0_7_data_lo_lo_hi, 2'h0}; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_7_data_lo_hi_lo = {pma_checker_sectored_entries_0_7_data_lo_hi_lo_hi, pma_checker_newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [5:0] pma_checker_sectored_entries_0_7_data_lo_hi = {pma_checker_sectored_entries_0_7_data_lo_hi_hi, pma_checker_sectored_entries_0_7_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_sectored_entries_0_7_data_lo = {pma_checker_sectored_entries_0_7_data_lo_hi, pma_checker_sectored_entries_0_7_data_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__sectored_entries_0_7_data_T = {31'h0, pma_checker_sectored_entries_0_7_data_lo}; // @[TLB.scala:217:24] wire [19:0] pma_checker__entries_T_23; // @[TLB.scala:170:77] wire pma_checker__entries_T_22; // @[TLB.scala:170:77] wire pma_checker__entries_T_21; // @[TLB.scala:170:77] wire pma_checker__entries_T_20; // @[TLB.scala:170:77] wire pma_checker__entries_T_19; // @[TLB.scala:170:77] wire pma_checker__entries_T_18; // @[TLB.scala:170:77] wire pma_checker__entries_T_17; // @[TLB.scala:170:77] wire pma_checker__entries_T_16; // @[TLB.scala:170:77] wire pma_checker__entries_T_15; // @[TLB.scala:170:77] wire pma_checker__entries_T_14; // @[TLB.scala:170:77] wire pma_checker__entries_T_13; // @[TLB.scala:170:77] wire pma_checker__entries_T_12; // @[TLB.scala:170:77] wire pma_checker__entries_T_11; // @[TLB.scala:170:77] wire pma_checker__entries_T_10; // @[TLB.scala:170:77] wire pma_checker__entries_T_9; // @[TLB.scala:170:77] wire pma_checker__entries_T_8; // @[TLB.scala:170:77] wire pma_checker__entries_T_7; // @[TLB.scala:170:77] wire pma_checker__entries_T_6; // @[TLB.scala:170:77] wire pma_checker__entries_T_5; // @[TLB.scala:170:77] wire pma_checker__entries_T_4; // @[TLB.scala:170:77] wire pma_checker__entries_T_3; // @[TLB.scala:170:77] wire pma_checker__entries_T_2; // @[TLB.scala:170:77] wire pma_checker__entries_T_1; // @[TLB.scala:170:77] assign pma_checker__entries_T_1 = pma_checker__entries_WIRE_1[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_fragmented_superpage = pma_checker__entries_T_1; // @[TLB.scala:170:77] assign pma_checker__entries_T_2 = pma_checker__entries_WIRE_1[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_c = pma_checker__entries_T_2; // @[TLB.scala:170:77] assign pma_checker__entries_T_3 = pma_checker__entries_WIRE_1[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_eff = pma_checker__entries_T_3; // @[TLB.scala:170:77] assign pma_checker__entries_T_4 = pma_checker__entries_WIRE_1[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_paa = pma_checker__entries_T_4; // @[TLB.scala:170:77] assign pma_checker__entries_T_5 = pma_checker__entries_WIRE_1[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_pal = pma_checker__entries_T_5; // @[TLB.scala:170:77] assign pma_checker__entries_T_6 = pma_checker__entries_WIRE_1[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_ppp = pma_checker__entries_T_6; // @[TLB.scala:170:77] assign pma_checker__entries_T_7 = pma_checker__entries_WIRE_1[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_pr = pma_checker__entries_T_7; // @[TLB.scala:170:77] assign pma_checker__entries_T_8 = pma_checker__entries_WIRE_1[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_px = pma_checker__entries_T_8; // @[TLB.scala:170:77] assign pma_checker__entries_T_9 = pma_checker__entries_WIRE_1[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_pw = pma_checker__entries_T_9; // @[TLB.scala:170:77] assign pma_checker__entries_T_10 = pma_checker__entries_WIRE_1[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_hr = pma_checker__entries_T_10; // @[TLB.scala:170:77] assign pma_checker__entries_T_11 = pma_checker__entries_WIRE_1[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_hx = pma_checker__entries_T_11; // @[TLB.scala:170:77] assign pma_checker__entries_T_12 = pma_checker__entries_WIRE_1[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_hw = pma_checker__entries_T_12; // @[TLB.scala:170:77] assign pma_checker__entries_T_13 = pma_checker__entries_WIRE_1[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_sr = pma_checker__entries_T_13; // @[TLB.scala:170:77] assign pma_checker__entries_T_14 = pma_checker__entries_WIRE_1[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_sx = pma_checker__entries_T_14; // @[TLB.scala:170:77] assign pma_checker__entries_T_15 = pma_checker__entries_WIRE_1[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_sw = pma_checker__entries_T_15; // @[TLB.scala:170:77] assign pma_checker__entries_T_16 = pma_checker__entries_WIRE_1[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_gf = pma_checker__entries_T_16; // @[TLB.scala:170:77] assign pma_checker__entries_T_17 = pma_checker__entries_WIRE_1[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_pf = pma_checker__entries_T_17; // @[TLB.scala:170:77] assign pma_checker__entries_T_18 = pma_checker__entries_WIRE_1[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_ae_stage2 = pma_checker__entries_T_18; // @[TLB.scala:170:77] assign pma_checker__entries_T_19 = pma_checker__entries_WIRE_1[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_ae_final = pma_checker__entries_T_19; // @[TLB.scala:170:77] assign pma_checker__entries_T_20 = pma_checker__entries_WIRE_1[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_ae_ptw = pma_checker__entries_T_20; // @[TLB.scala:170:77] assign pma_checker__entries_T_21 = pma_checker__entries_WIRE_1[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_g = pma_checker__entries_T_21; // @[TLB.scala:170:77] assign pma_checker__entries_T_22 = pma_checker__entries_WIRE_1[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_u = pma_checker__entries_T_22; // @[TLB.scala:170:77] assign pma_checker__entries_T_23 = pma_checker__entries_WIRE_1[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_ppn = pma_checker__entries_T_23; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_47; // @[TLB.scala:170:77] wire pma_checker__entries_T_46; // @[TLB.scala:170:77] wire pma_checker__entries_T_45; // @[TLB.scala:170:77] wire pma_checker__entries_T_44; // @[TLB.scala:170:77] wire pma_checker__entries_T_43; // @[TLB.scala:170:77] wire pma_checker__entries_T_42; // @[TLB.scala:170:77] wire pma_checker__entries_T_41; // @[TLB.scala:170:77] wire pma_checker__entries_T_40; // @[TLB.scala:170:77] wire pma_checker__entries_T_39; // @[TLB.scala:170:77] wire pma_checker__entries_T_38; // @[TLB.scala:170:77] wire pma_checker__entries_T_37; // @[TLB.scala:170:77] wire pma_checker__entries_T_36; // @[TLB.scala:170:77] wire pma_checker__entries_T_35; // @[TLB.scala:170:77] wire pma_checker__entries_T_34; // @[TLB.scala:170:77] wire pma_checker__entries_T_33; // @[TLB.scala:170:77] wire pma_checker__entries_T_32; // @[TLB.scala:170:77] wire pma_checker__entries_T_31; // @[TLB.scala:170:77] wire pma_checker__entries_T_30; // @[TLB.scala:170:77] wire pma_checker__entries_T_29; // @[TLB.scala:170:77] wire pma_checker__entries_T_28; // @[TLB.scala:170:77] wire pma_checker__entries_T_27; // @[TLB.scala:170:77] wire pma_checker__entries_T_26; // @[TLB.scala:170:77] wire pma_checker__entries_T_25; // @[TLB.scala:170:77] assign pma_checker__entries_T_25 = pma_checker__entries_WIRE_3[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_fragmented_superpage = pma_checker__entries_T_25; // @[TLB.scala:170:77] assign pma_checker__entries_T_26 = pma_checker__entries_WIRE_3[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_c = pma_checker__entries_T_26; // @[TLB.scala:170:77] assign pma_checker__entries_T_27 = pma_checker__entries_WIRE_3[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_eff = pma_checker__entries_T_27; // @[TLB.scala:170:77] assign pma_checker__entries_T_28 = pma_checker__entries_WIRE_3[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_paa = pma_checker__entries_T_28; // @[TLB.scala:170:77] assign pma_checker__entries_T_29 = pma_checker__entries_WIRE_3[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_pal = pma_checker__entries_T_29; // @[TLB.scala:170:77] assign pma_checker__entries_T_30 = pma_checker__entries_WIRE_3[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_ppp = pma_checker__entries_T_30; // @[TLB.scala:170:77] assign pma_checker__entries_T_31 = pma_checker__entries_WIRE_3[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_pr = pma_checker__entries_T_31; // @[TLB.scala:170:77] assign pma_checker__entries_T_32 = pma_checker__entries_WIRE_3[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_px = pma_checker__entries_T_32; // @[TLB.scala:170:77] assign pma_checker__entries_T_33 = pma_checker__entries_WIRE_3[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_pw = pma_checker__entries_T_33; // @[TLB.scala:170:77] assign pma_checker__entries_T_34 = pma_checker__entries_WIRE_3[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_hr = pma_checker__entries_T_34; // @[TLB.scala:170:77] assign pma_checker__entries_T_35 = pma_checker__entries_WIRE_3[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_hx = pma_checker__entries_T_35; // @[TLB.scala:170:77] assign pma_checker__entries_T_36 = pma_checker__entries_WIRE_3[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_hw = pma_checker__entries_T_36; // @[TLB.scala:170:77] assign pma_checker__entries_T_37 = pma_checker__entries_WIRE_3[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_sr = pma_checker__entries_T_37; // @[TLB.scala:170:77] assign pma_checker__entries_T_38 = pma_checker__entries_WIRE_3[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_sx = pma_checker__entries_T_38; // @[TLB.scala:170:77] assign pma_checker__entries_T_39 = pma_checker__entries_WIRE_3[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_sw = pma_checker__entries_T_39; // @[TLB.scala:170:77] assign pma_checker__entries_T_40 = pma_checker__entries_WIRE_3[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_gf = pma_checker__entries_T_40; // @[TLB.scala:170:77] assign pma_checker__entries_T_41 = pma_checker__entries_WIRE_3[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_pf = pma_checker__entries_T_41; // @[TLB.scala:170:77] assign pma_checker__entries_T_42 = pma_checker__entries_WIRE_3[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_ae_stage2 = pma_checker__entries_T_42; // @[TLB.scala:170:77] assign pma_checker__entries_T_43 = pma_checker__entries_WIRE_3[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_ae_final = pma_checker__entries_T_43; // @[TLB.scala:170:77] assign pma_checker__entries_T_44 = pma_checker__entries_WIRE_3[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_ae_ptw = pma_checker__entries_T_44; // @[TLB.scala:170:77] assign pma_checker__entries_T_45 = pma_checker__entries_WIRE_3[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_g = pma_checker__entries_T_45; // @[TLB.scala:170:77] assign pma_checker__entries_T_46 = pma_checker__entries_WIRE_3[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_u = pma_checker__entries_T_46; // @[TLB.scala:170:77] assign pma_checker__entries_T_47 = pma_checker__entries_WIRE_3[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_2_ppn = pma_checker__entries_T_47; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_71; // @[TLB.scala:170:77] wire pma_checker__entries_T_70; // @[TLB.scala:170:77] wire pma_checker__entries_T_69; // @[TLB.scala:170:77] wire pma_checker__entries_T_68; // @[TLB.scala:170:77] wire pma_checker__entries_T_67; // @[TLB.scala:170:77] wire pma_checker__entries_T_66; // @[TLB.scala:170:77] wire pma_checker__entries_T_65; // @[TLB.scala:170:77] wire pma_checker__entries_T_64; // @[TLB.scala:170:77] wire pma_checker__entries_T_63; // @[TLB.scala:170:77] wire pma_checker__entries_T_62; // @[TLB.scala:170:77] wire pma_checker__entries_T_61; // @[TLB.scala:170:77] wire pma_checker__entries_T_60; // @[TLB.scala:170:77] wire pma_checker__entries_T_59; // @[TLB.scala:170:77] wire pma_checker__entries_T_58; // @[TLB.scala:170:77] wire pma_checker__entries_T_57; // @[TLB.scala:170:77] wire pma_checker__entries_T_56; // @[TLB.scala:170:77] wire pma_checker__entries_T_55; // @[TLB.scala:170:77] wire pma_checker__entries_T_54; // @[TLB.scala:170:77] wire pma_checker__entries_T_53; // @[TLB.scala:170:77] wire pma_checker__entries_T_52; // @[TLB.scala:170:77] wire pma_checker__entries_T_51; // @[TLB.scala:170:77] wire pma_checker__entries_T_50; // @[TLB.scala:170:77] wire pma_checker__entries_T_49; // @[TLB.scala:170:77] assign pma_checker__entries_T_49 = pma_checker__entries_WIRE_5[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_fragmented_superpage = pma_checker__entries_T_49; // @[TLB.scala:170:77] assign pma_checker__entries_T_50 = pma_checker__entries_WIRE_5[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_c = pma_checker__entries_T_50; // @[TLB.scala:170:77] assign pma_checker__entries_T_51 = pma_checker__entries_WIRE_5[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_eff = pma_checker__entries_T_51; // @[TLB.scala:170:77] assign pma_checker__entries_T_52 = pma_checker__entries_WIRE_5[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_paa = pma_checker__entries_T_52; // @[TLB.scala:170:77] assign pma_checker__entries_T_53 = pma_checker__entries_WIRE_5[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_pal = pma_checker__entries_T_53; // @[TLB.scala:170:77] assign pma_checker__entries_T_54 = pma_checker__entries_WIRE_5[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_ppp = pma_checker__entries_T_54; // @[TLB.scala:170:77] assign pma_checker__entries_T_55 = pma_checker__entries_WIRE_5[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_pr = pma_checker__entries_T_55; // @[TLB.scala:170:77] assign pma_checker__entries_T_56 = pma_checker__entries_WIRE_5[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_px = pma_checker__entries_T_56; // @[TLB.scala:170:77] assign pma_checker__entries_T_57 = pma_checker__entries_WIRE_5[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_pw = pma_checker__entries_T_57; // @[TLB.scala:170:77] assign pma_checker__entries_T_58 = pma_checker__entries_WIRE_5[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_hr = pma_checker__entries_T_58; // @[TLB.scala:170:77] assign pma_checker__entries_T_59 = pma_checker__entries_WIRE_5[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_hx = pma_checker__entries_T_59; // @[TLB.scala:170:77] assign pma_checker__entries_T_60 = pma_checker__entries_WIRE_5[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_hw = pma_checker__entries_T_60; // @[TLB.scala:170:77] assign pma_checker__entries_T_61 = pma_checker__entries_WIRE_5[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_sr = pma_checker__entries_T_61; // @[TLB.scala:170:77] assign pma_checker__entries_T_62 = pma_checker__entries_WIRE_5[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_sx = pma_checker__entries_T_62; // @[TLB.scala:170:77] assign pma_checker__entries_T_63 = pma_checker__entries_WIRE_5[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_sw = pma_checker__entries_T_63; // @[TLB.scala:170:77] assign pma_checker__entries_T_64 = pma_checker__entries_WIRE_5[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_gf = pma_checker__entries_T_64; // @[TLB.scala:170:77] assign pma_checker__entries_T_65 = pma_checker__entries_WIRE_5[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_pf = pma_checker__entries_T_65; // @[TLB.scala:170:77] assign pma_checker__entries_T_66 = pma_checker__entries_WIRE_5[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_ae_stage2 = pma_checker__entries_T_66; // @[TLB.scala:170:77] assign pma_checker__entries_T_67 = pma_checker__entries_WIRE_5[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_ae_final = pma_checker__entries_T_67; // @[TLB.scala:170:77] assign pma_checker__entries_T_68 = pma_checker__entries_WIRE_5[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_ae_ptw = pma_checker__entries_T_68; // @[TLB.scala:170:77] assign pma_checker__entries_T_69 = pma_checker__entries_WIRE_5[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_g = pma_checker__entries_T_69; // @[TLB.scala:170:77] assign pma_checker__entries_T_70 = pma_checker__entries_WIRE_5[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_u = pma_checker__entries_T_70; // @[TLB.scala:170:77] assign pma_checker__entries_T_71 = pma_checker__entries_WIRE_5[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_4_ppn = pma_checker__entries_T_71; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_95; // @[TLB.scala:170:77] wire pma_checker__entries_T_94; // @[TLB.scala:170:77] wire pma_checker__entries_T_93; // @[TLB.scala:170:77] wire pma_checker__entries_T_92; // @[TLB.scala:170:77] wire pma_checker__entries_T_91; // @[TLB.scala:170:77] wire pma_checker__entries_T_90; // @[TLB.scala:170:77] wire pma_checker__entries_T_89; // @[TLB.scala:170:77] wire pma_checker__entries_T_88; // @[TLB.scala:170:77] wire pma_checker__entries_T_87; // @[TLB.scala:170:77] wire pma_checker__entries_T_86; // @[TLB.scala:170:77] wire pma_checker__entries_T_85; // @[TLB.scala:170:77] wire pma_checker__entries_T_84; // @[TLB.scala:170:77] wire pma_checker__entries_T_83; // @[TLB.scala:170:77] wire pma_checker__entries_T_82; // @[TLB.scala:170:77] wire pma_checker__entries_T_81; // @[TLB.scala:170:77] wire pma_checker__entries_T_80; // @[TLB.scala:170:77] wire pma_checker__entries_T_79; // @[TLB.scala:170:77] wire pma_checker__entries_T_78; // @[TLB.scala:170:77] wire pma_checker__entries_T_77; // @[TLB.scala:170:77] wire pma_checker__entries_T_76; // @[TLB.scala:170:77] wire pma_checker__entries_T_75; // @[TLB.scala:170:77] wire pma_checker__entries_T_74; // @[TLB.scala:170:77] wire pma_checker__entries_T_73; // @[TLB.scala:170:77] assign pma_checker__entries_T_73 = pma_checker__entries_WIRE_7[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_fragmented_superpage = pma_checker__entries_T_73; // @[TLB.scala:170:77] assign pma_checker__entries_T_74 = pma_checker__entries_WIRE_7[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_c = pma_checker__entries_T_74; // @[TLB.scala:170:77] assign pma_checker__entries_T_75 = pma_checker__entries_WIRE_7[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_eff = pma_checker__entries_T_75; // @[TLB.scala:170:77] assign pma_checker__entries_T_76 = pma_checker__entries_WIRE_7[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_paa = pma_checker__entries_T_76; // @[TLB.scala:170:77] assign pma_checker__entries_T_77 = pma_checker__entries_WIRE_7[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_pal = pma_checker__entries_T_77; // @[TLB.scala:170:77] assign pma_checker__entries_T_78 = pma_checker__entries_WIRE_7[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_ppp = pma_checker__entries_T_78; // @[TLB.scala:170:77] assign pma_checker__entries_T_79 = pma_checker__entries_WIRE_7[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_pr = pma_checker__entries_T_79; // @[TLB.scala:170:77] assign pma_checker__entries_T_80 = pma_checker__entries_WIRE_7[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_px = pma_checker__entries_T_80; // @[TLB.scala:170:77] assign pma_checker__entries_T_81 = pma_checker__entries_WIRE_7[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_pw = pma_checker__entries_T_81; // @[TLB.scala:170:77] assign pma_checker__entries_T_82 = pma_checker__entries_WIRE_7[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_hr = pma_checker__entries_T_82; // @[TLB.scala:170:77] assign pma_checker__entries_T_83 = pma_checker__entries_WIRE_7[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_hx = pma_checker__entries_T_83; // @[TLB.scala:170:77] assign pma_checker__entries_T_84 = pma_checker__entries_WIRE_7[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_hw = pma_checker__entries_T_84; // @[TLB.scala:170:77] assign pma_checker__entries_T_85 = pma_checker__entries_WIRE_7[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_sr = pma_checker__entries_T_85; // @[TLB.scala:170:77] assign pma_checker__entries_T_86 = pma_checker__entries_WIRE_7[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_sx = pma_checker__entries_T_86; // @[TLB.scala:170:77] assign pma_checker__entries_T_87 = pma_checker__entries_WIRE_7[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_sw = pma_checker__entries_T_87; // @[TLB.scala:170:77] assign pma_checker__entries_T_88 = pma_checker__entries_WIRE_7[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_gf = pma_checker__entries_T_88; // @[TLB.scala:170:77] assign pma_checker__entries_T_89 = pma_checker__entries_WIRE_7[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_pf = pma_checker__entries_T_89; // @[TLB.scala:170:77] assign pma_checker__entries_T_90 = pma_checker__entries_WIRE_7[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_ae_stage2 = pma_checker__entries_T_90; // @[TLB.scala:170:77] assign pma_checker__entries_T_91 = pma_checker__entries_WIRE_7[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_ae_final = pma_checker__entries_T_91; // @[TLB.scala:170:77] assign pma_checker__entries_T_92 = pma_checker__entries_WIRE_7[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_ae_ptw = pma_checker__entries_T_92; // @[TLB.scala:170:77] assign pma_checker__entries_T_93 = pma_checker__entries_WIRE_7[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_g = pma_checker__entries_T_93; // @[TLB.scala:170:77] assign pma_checker__entries_T_94 = pma_checker__entries_WIRE_7[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_u = pma_checker__entries_T_94; // @[TLB.scala:170:77] assign pma_checker__entries_T_95 = pma_checker__entries_WIRE_7[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_6_ppn = pma_checker__entries_T_95; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_119; // @[TLB.scala:170:77] wire pma_checker__entries_T_118; // @[TLB.scala:170:77] wire pma_checker__entries_T_117; // @[TLB.scala:170:77] wire pma_checker__entries_T_116; // @[TLB.scala:170:77] wire pma_checker__entries_T_115; // @[TLB.scala:170:77] wire pma_checker__entries_T_114; // @[TLB.scala:170:77] wire pma_checker__entries_T_113; // @[TLB.scala:170:77] wire pma_checker__entries_T_112; // @[TLB.scala:170:77] wire pma_checker__entries_T_111; // @[TLB.scala:170:77] wire pma_checker__entries_T_110; // @[TLB.scala:170:77] wire pma_checker__entries_T_109; // @[TLB.scala:170:77] wire pma_checker__entries_T_108; // @[TLB.scala:170:77] wire pma_checker__entries_T_107; // @[TLB.scala:170:77] wire pma_checker__entries_T_106; // @[TLB.scala:170:77] wire pma_checker__entries_T_105; // @[TLB.scala:170:77] wire pma_checker__entries_T_104; // @[TLB.scala:170:77] wire pma_checker__entries_T_103; // @[TLB.scala:170:77] wire pma_checker__entries_T_102; // @[TLB.scala:170:77] wire pma_checker__entries_T_101; // @[TLB.scala:170:77] wire pma_checker__entries_T_100; // @[TLB.scala:170:77] wire pma_checker__entries_T_99; // @[TLB.scala:170:77] wire pma_checker__entries_T_98; // @[TLB.scala:170:77] wire pma_checker__entries_T_97; // @[TLB.scala:170:77] assign pma_checker__entries_T_97 = pma_checker__entries_WIRE_9[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_fragmented_superpage = pma_checker__entries_T_97; // @[TLB.scala:170:77] assign pma_checker__entries_T_98 = pma_checker__entries_WIRE_9[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_c = pma_checker__entries_T_98; // @[TLB.scala:170:77] assign pma_checker__entries_T_99 = pma_checker__entries_WIRE_9[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_eff = pma_checker__entries_T_99; // @[TLB.scala:170:77] assign pma_checker__entries_T_100 = pma_checker__entries_WIRE_9[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_paa = pma_checker__entries_T_100; // @[TLB.scala:170:77] assign pma_checker__entries_T_101 = pma_checker__entries_WIRE_9[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_pal = pma_checker__entries_T_101; // @[TLB.scala:170:77] assign pma_checker__entries_T_102 = pma_checker__entries_WIRE_9[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_ppp = pma_checker__entries_T_102; // @[TLB.scala:170:77] assign pma_checker__entries_T_103 = pma_checker__entries_WIRE_9[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_pr = pma_checker__entries_T_103; // @[TLB.scala:170:77] assign pma_checker__entries_T_104 = pma_checker__entries_WIRE_9[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_px = pma_checker__entries_T_104; // @[TLB.scala:170:77] assign pma_checker__entries_T_105 = pma_checker__entries_WIRE_9[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_pw = pma_checker__entries_T_105; // @[TLB.scala:170:77] assign pma_checker__entries_T_106 = pma_checker__entries_WIRE_9[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_hr = pma_checker__entries_T_106; // @[TLB.scala:170:77] assign pma_checker__entries_T_107 = pma_checker__entries_WIRE_9[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_hx = pma_checker__entries_T_107; // @[TLB.scala:170:77] assign pma_checker__entries_T_108 = pma_checker__entries_WIRE_9[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_hw = pma_checker__entries_T_108; // @[TLB.scala:170:77] assign pma_checker__entries_T_109 = pma_checker__entries_WIRE_9[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_sr = pma_checker__entries_T_109; // @[TLB.scala:170:77] assign pma_checker__entries_T_110 = pma_checker__entries_WIRE_9[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_sx = pma_checker__entries_T_110; // @[TLB.scala:170:77] assign pma_checker__entries_T_111 = pma_checker__entries_WIRE_9[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_sw = pma_checker__entries_T_111; // @[TLB.scala:170:77] assign pma_checker__entries_T_112 = pma_checker__entries_WIRE_9[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_gf = pma_checker__entries_T_112; // @[TLB.scala:170:77] assign pma_checker__entries_T_113 = pma_checker__entries_WIRE_9[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_pf = pma_checker__entries_T_113; // @[TLB.scala:170:77] assign pma_checker__entries_T_114 = pma_checker__entries_WIRE_9[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_ae_stage2 = pma_checker__entries_T_114; // @[TLB.scala:170:77] assign pma_checker__entries_T_115 = pma_checker__entries_WIRE_9[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_ae_final = pma_checker__entries_T_115; // @[TLB.scala:170:77] assign pma_checker__entries_T_116 = pma_checker__entries_WIRE_9[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_ae_ptw = pma_checker__entries_T_116; // @[TLB.scala:170:77] assign pma_checker__entries_T_117 = pma_checker__entries_WIRE_9[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_g = pma_checker__entries_T_117; // @[TLB.scala:170:77] assign pma_checker__entries_T_118 = pma_checker__entries_WIRE_9[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_u = pma_checker__entries_T_118; // @[TLB.scala:170:77] assign pma_checker__entries_T_119 = pma_checker__entries_WIRE_9[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_8_ppn = pma_checker__entries_T_119; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_143; // @[TLB.scala:170:77] wire pma_checker__entries_T_142; // @[TLB.scala:170:77] wire pma_checker__entries_T_141; // @[TLB.scala:170:77] wire pma_checker__entries_T_140; // @[TLB.scala:170:77] wire pma_checker__entries_T_139; // @[TLB.scala:170:77] wire pma_checker__entries_T_138; // @[TLB.scala:170:77] wire pma_checker__entries_T_137; // @[TLB.scala:170:77] wire pma_checker__entries_T_136; // @[TLB.scala:170:77] wire pma_checker__entries_T_135; // @[TLB.scala:170:77] wire pma_checker__entries_T_134; // @[TLB.scala:170:77] wire pma_checker__entries_T_133; // @[TLB.scala:170:77] wire pma_checker__entries_T_132; // @[TLB.scala:170:77] wire pma_checker__entries_T_131; // @[TLB.scala:170:77] wire pma_checker__entries_T_130; // @[TLB.scala:170:77] wire pma_checker__entries_T_129; // @[TLB.scala:170:77] wire pma_checker__entries_T_128; // @[TLB.scala:170:77] wire pma_checker__entries_T_127; // @[TLB.scala:170:77] wire pma_checker__entries_T_126; // @[TLB.scala:170:77] wire pma_checker__entries_T_125; // @[TLB.scala:170:77] wire pma_checker__entries_T_124; // @[TLB.scala:170:77] wire pma_checker__entries_T_123; // @[TLB.scala:170:77] wire pma_checker__entries_T_122; // @[TLB.scala:170:77] wire pma_checker__entries_T_121; // @[TLB.scala:170:77] assign pma_checker__entries_T_121 = pma_checker__entries_WIRE_11[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_fragmented_superpage = pma_checker__entries_T_121; // @[TLB.scala:170:77] assign pma_checker__entries_T_122 = pma_checker__entries_WIRE_11[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_c = pma_checker__entries_T_122; // @[TLB.scala:170:77] assign pma_checker__entries_T_123 = pma_checker__entries_WIRE_11[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_eff = pma_checker__entries_T_123; // @[TLB.scala:170:77] assign pma_checker__entries_T_124 = pma_checker__entries_WIRE_11[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_paa = pma_checker__entries_T_124; // @[TLB.scala:170:77] assign pma_checker__entries_T_125 = pma_checker__entries_WIRE_11[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_pal = pma_checker__entries_T_125; // @[TLB.scala:170:77] assign pma_checker__entries_T_126 = pma_checker__entries_WIRE_11[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_ppp = pma_checker__entries_T_126; // @[TLB.scala:170:77] assign pma_checker__entries_T_127 = pma_checker__entries_WIRE_11[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_pr = pma_checker__entries_T_127; // @[TLB.scala:170:77] assign pma_checker__entries_T_128 = pma_checker__entries_WIRE_11[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_px = pma_checker__entries_T_128; // @[TLB.scala:170:77] assign pma_checker__entries_T_129 = pma_checker__entries_WIRE_11[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_pw = pma_checker__entries_T_129; // @[TLB.scala:170:77] assign pma_checker__entries_T_130 = pma_checker__entries_WIRE_11[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_hr = pma_checker__entries_T_130; // @[TLB.scala:170:77] assign pma_checker__entries_T_131 = pma_checker__entries_WIRE_11[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_hx = pma_checker__entries_T_131; // @[TLB.scala:170:77] assign pma_checker__entries_T_132 = pma_checker__entries_WIRE_11[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_hw = pma_checker__entries_T_132; // @[TLB.scala:170:77] assign pma_checker__entries_T_133 = pma_checker__entries_WIRE_11[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_sr = pma_checker__entries_T_133; // @[TLB.scala:170:77] assign pma_checker__entries_T_134 = pma_checker__entries_WIRE_11[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_sx = pma_checker__entries_T_134; // @[TLB.scala:170:77] assign pma_checker__entries_T_135 = pma_checker__entries_WIRE_11[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_sw = pma_checker__entries_T_135; // @[TLB.scala:170:77] assign pma_checker__entries_T_136 = pma_checker__entries_WIRE_11[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_gf = pma_checker__entries_T_136; // @[TLB.scala:170:77] assign pma_checker__entries_T_137 = pma_checker__entries_WIRE_11[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_pf = pma_checker__entries_T_137; // @[TLB.scala:170:77] assign pma_checker__entries_T_138 = pma_checker__entries_WIRE_11[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_ae_stage2 = pma_checker__entries_T_138; // @[TLB.scala:170:77] assign pma_checker__entries_T_139 = pma_checker__entries_WIRE_11[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_ae_final = pma_checker__entries_T_139; // @[TLB.scala:170:77] assign pma_checker__entries_T_140 = pma_checker__entries_WIRE_11[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_ae_ptw = pma_checker__entries_T_140; // @[TLB.scala:170:77] assign pma_checker__entries_T_141 = pma_checker__entries_WIRE_11[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_g = pma_checker__entries_T_141; // @[TLB.scala:170:77] assign pma_checker__entries_T_142 = pma_checker__entries_WIRE_11[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_u = pma_checker__entries_T_142; // @[TLB.scala:170:77] assign pma_checker__entries_T_143 = pma_checker__entries_WIRE_11[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_10_ppn = pma_checker__entries_T_143; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_167; // @[TLB.scala:170:77] wire pma_checker__entries_T_166; // @[TLB.scala:170:77] wire pma_checker__entries_T_165; // @[TLB.scala:170:77] wire pma_checker__entries_T_164; // @[TLB.scala:170:77] wire pma_checker__entries_T_163; // @[TLB.scala:170:77] wire pma_checker__entries_T_162; // @[TLB.scala:170:77] wire pma_checker__entries_T_161; // @[TLB.scala:170:77] wire pma_checker__entries_T_160; // @[TLB.scala:170:77] wire pma_checker__entries_T_159; // @[TLB.scala:170:77] wire pma_checker__entries_T_158; // @[TLB.scala:170:77] wire pma_checker__entries_T_157; // @[TLB.scala:170:77] wire pma_checker__entries_T_156; // @[TLB.scala:170:77] wire pma_checker__entries_T_155; // @[TLB.scala:170:77] wire pma_checker__entries_T_154; // @[TLB.scala:170:77] wire pma_checker__entries_T_153; // @[TLB.scala:170:77] wire pma_checker__entries_T_152; // @[TLB.scala:170:77] wire pma_checker__entries_T_151; // @[TLB.scala:170:77] wire pma_checker__entries_T_150; // @[TLB.scala:170:77] wire pma_checker__entries_T_149; // @[TLB.scala:170:77] wire pma_checker__entries_T_148; // @[TLB.scala:170:77] wire pma_checker__entries_T_147; // @[TLB.scala:170:77] wire pma_checker__entries_T_146; // @[TLB.scala:170:77] wire pma_checker__entries_T_145; // @[TLB.scala:170:77] assign pma_checker__entries_T_145 = pma_checker__entries_WIRE_13[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_fragmented_superpage = pma_checker__entries_T_145; // @[TLB.scala:170:77] assign pma_checker__entries_T_146 = pma_checker__entries_WIRE_13[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_c = pma_checker__entries_T_146; // @[TLB.scala:170:77] assign pma_checker__entries_T_147 = pma_checker__entries_WIRE_13[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_eff = pma_checker__entries_T_147; // @[TLB.scala:170:77] assign pma_checker__entries_T_148 = pma_checker__entries_WIRE_13[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_paa = pma_checker__entries_T_148; // @[TLB.scala:170:77] assign pma_checker__entries_T_149 = pma_checker__entries_WIRE_13[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_pal = pma_checker__entries_T_149; // @[TLB.scala:170:77] assign pma_checker__entries_T_150 = pma_checker__entries_WIRE_13[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_ppp = pma_checker__entries_T_150; // @[TLB.scala:170:77] assign pma_checker__entries_T_151 = pma_checker__entries_WIRE_13[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_pr = pma_checker__entries_T_151; // @[TLB.scala:170:77] assign pma_checker__entries_T_152 = pma_checker__entries_WIRE_13[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_px = pma_checker__entries_T_152; // @[TLB.scala:170:77] assign pma_checker__entries_T_153 = pma_checker__entries_WIRE_13[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_pw = pma_checker__entries_T_153; // @[TLB.scala:170:77] assign pma_checker__entries_T_154 = pma_checker__entries_WIRE_13[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_hr = pma_checker__entries_T_154; // @[TLB.scala:170:77] assign pma_checker__entries_T_155 = pma_checker__entries_WIRE_13[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_hx = pma_checker__entries_T_155; // @[TLB.scala:170:77] assign pma_checker__entries_T_156 = pma_checker__entries_WIRE_13[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_hw = pma_checker__entries_T_156; // @[TLB.scala:170:77] assign pma_checker__entries_T_157 = pma_checker__entries_WIRE_13[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_sr = pma_checker__entries_T_157; // @[TLB.scala:170:77] assign pma_checker__entries_T_158 = pma_checker__entries_WIRE_13[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_sx = pma_checker__entries_T_158; // @[TLB.scala:170:77] assign pma_checker__entries_T_159 = pma_checker__entries_WIRE_13[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_sw = pma_checker__entries_T_159; // @[TLB.scala:170:77] assign pma_checker__entries_T_160 = pma_checker__entries_WIRE_13[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_gf = pma_checker__entries_T_160; // @[TLB.scala:170:77] assign pma_checker__entries_T_161 = pma_checker__entries_WIRE_13[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_pf = pma_checker__entries_T_161; // @[TLB.scala:170:77] assign pma_checker__entries_T_162 = pma_checker__entries_WIRE_13[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_ae_stage2 = pma_checker__entries_T_162; // @[TLB.scala:170:77] assign pma_checker__entries_T_163 = pma_checker__entries_WIRE_13[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_ae_final = pma_checker__entries_T_163; // @[TLB.scala:170:77] assign pma_checker__entries_T_164 = pma_checker__entries_WIRE_13[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_ae_ptw = pma_checker__entries_T_164; // @[TLB.scala:170:77] assign pma_checker__entries_T_165 = pma_checker__entries_WIRE_13[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_g = pma_checker__entries_T_165; // @[TLB.scala:170:77] assign pma_checker__entries_T_166 = pma_checker__entries_WIRE_13[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_u = pma_checker__entries_T_166; // @[TLB.scala:170:77] assign pma_checker__entries_T_167 = pma_checker__entries_WIRE_13[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_12_ppn = pma_checker__entries_T_167; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_191; // @[TLB.scala:170:77] wire pma_checker__entries_T_190; // @[TLB.scala:170:77] wire pma_checker__entries_T_189; // @[TLB.scala:170:77] wire pma_checker__entries_T_188; // @[TLB.scala:170:77] wire pma_checker__entries_T_187; // @[TLB.scala:170:77] wire pma_checker__entries_T_186; // @[TLB.scala:170:77] wire pma_checker__entries_T_185; // @[TLB.scala:170:77] wire pma_checker__entries_T_184; // @[TLB.scala:170:77] wire pma_checker__entries_T_183; // @[TLB.scala:170:77] wire pma_checker__entries_T_182; // @[TLB.scala:170:77] wire pma_checker__entries_T_181; // @[TLB.scala:170:77] wire pma_checker__entries_T_180; // @[TLB.scala:170:77] wire pma_checker__entries_T_179; // @[TLB.scala:170:77] wire pma_checker__entries_T_178; // @[TLB.scala:170:77] wire pma_checker__entries_T_177; // @[TLB.scala:170:77] wire pma_checker__entries_T_176; // @[TLB.scala:170:77] wire pma_checker__entries_T_175; // @[TLB.scala:170:77] wire pma_checker__entries_T_174; // @[TLB.scala:170:77] wire pma_checker__entries_T_173; // @[TLB.scala:170:77] wire pma_checker__entries_T_172; // @[TLB.scala:170:77] wire pma_checker__entries_T_171; // @[TLB.scala:170:77] wire pma_checker__entries_T_170; // @[TLB.scala:170:77] wire pma_checker__entries_T_169; // @[TLB.scala:170:77] assign pma_checker__entries_T_169 = pma_checker__entries_WIRE_15[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_fragmented_superpage = pma_checker__entries_T_169; // @[TLB.scala:170:77] assign pma_checker__entries_T_170 = pma_checker__entries_WIRE_15[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_c = pma_checker__entries_T_170; // @[TLB.scala:170:77] assign pma_checker__entries_T_171 = pma_checker__entries_WIRE_15[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_eff = pma_checker__entries_T_171; // @[TLB.scala:170:77] assign pma_checker__entries_T_172 = pma_checker__entries_WIRE_15[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_paa = pma_checker__entries_T_172; // @[TLB.scala:170:77] assign pma_checker__entries_T_173 = pma_checker__entries_WIRE_15[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_pal = pma_checker__entries_T_173; // @[TLB.scala:170:77] assign pma_checker__entries_T_174 = pma_checker__entries_WIRE_15[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_ppp = pma_checker__entries_T_174; // @[TLB.scala:170:77] assign pma_checker__entries_T_175 = pma_checker__entries_WIRE_15[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_pr = pma_checker__entries_T_175; // @[TLB.scala:170:77] assign pma_checker__entries_T_176 = pma_checker__entries_WIRE_15[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_px = pma_checker__entries_T_176; // @[TLB.scala:170:77] assign pma_checker__entries_T_177 = pma_checker__entries_WIRE_15[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_pw = pma_checker__entries_T_177; // @[TLB.scala:170:77] assign pma_checker__entries_T_178 = pma_checker__entries_WIRE_15[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_hr = pma_checker__entries_T_178; // @[TLB.scala:170:77] assign pma_checker__entries_T_179 = pma_checker__entries_WIRE_15[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_hx = pma_checker__entries_T_179; // @[TLB.scala:170:77] assign pma_checker__entries_T_180 = pma_checker__entries_WIRE_15[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_hw = pma_checker__entries_T_180; // @[TLB.scala:170:77] assign pma_checker__entries_T_181 = pma_checker__entries_WIRE_15[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_sr = pma_checker__entries_T_181; // @[TLB.scala:170:77] assign pma_checker__entries_T_182 = pma_checker__entries_WIRE_15[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_sx = pma_checker__entries_T_182; // @[TLB.scala:170:77] assign pma_checker__entries_T_183 = pma_checker__entries_WIRE_15[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_sw = pma_checker__entries_T_183; // @[TLB.scala:170:77] assign pma_checker__entries_T_184 = pma_checker__entries_WIRE_15[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_gf = pma_checker__entries_T_184; // @[TLB.scala:170:77] assign pma_checker__entries_T_185 = pma_checker__entries_WIRE_15[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_pf = pma_checker__entries_T_185; // @[TLB.scala:170:77] assign pma_checker__entries_T_186 = pma_checker__entries_WIRE_15[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_ae_stage2 = pma_checker__entries_T_186; // @[TLB.scala:170:77] assign pma_checker__entries_T_187 = pma_checker__entries_WIRE_15[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_ae_final = pma_checker__entries_T_187; // @[TLB.scala:170:77] assign pma_checker__entries_T_188 = pma_checker__entries_WIRE_15[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_ae_ptw = pma_checker__entries_T_188; // @[TLB.scala:170:77] assign pma_checker__entries_T_189 = pma_checker__entries_WIRE_15[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_g = pma_checker__entries_T_189; // @[TLB.scala:170:77] assign pma_checker__entries_T_190 = pma_checker__entries_WIRE_15[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_u = pma_checker__entries_T_190; // @[TLB.scala:170:77] assign pma_checker__entries_T_191 = pma_checker__entries_WIRE_15[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_14_ppn = pma_checker__entries_T_191; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_214; // @[TLB.scala:170:77] wire pma_checker__entries_T_213; // @[TLB.scala:170:77] wire pma_checker__entries_T_212; // @[TLB.scala:170:77] wire pma_checker__entries_T_211; // @[TLB.scala:170:77] wire pma_checker__entries_T_210; // @[TLB.scala:170:77] wire pma_checker__entries_T_209; // @[TLB.scala:170:77] wire pma_checker__entries_T_208; // @[TLB.scala:170:77] wire pma_checker__entries_T_207; // @[TLB.scala:170:77] wire pma_checker__entries_T_206; // @[TLB.scala:170:77] wire pma_checker__entries_T_205; // @[TLB.scala:170:77] wire pma_checker__entries_T_204; // @[TLB.scala:170:77] wire pma_checker__entries_T_203; // @[TLB.scala:170:77] wire pma_checker__entries_T_202; // @[TLB.scala:170:77] wire pma_checker__entries_T_201; // @[TLB.scala:170:77] wire pma_checker__entries_T_200; // @[TLB.scala:170:77] wire pma_checker__entries_T_199; // @[TLB.scala:170:77] wire pma_checker__entries_T_198; // @[TLB.scala:170:77] wire pma_checker__entries_T_197; // @[TLB.scala:170:77] wire pma_checker__entries_T_196; // @[TLB.scala:170:77] wire pma_checker__entries_T_195; // @[TLB.scala:170:77] wire pma_checker__entries_T_194; // @[TLB.scala:170:77] wire pma_checker__entries_T_193; // @[TLB.scala:170:77] wire pma_checker__entries_T_192; // @[TLB.scala:170:77] assign pma_checker__entries_T_192 = pma_checker__entries_WIRE_17[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_fragmented_superpage = pma_checker__entries_T_192; // @[TLB.scala:170:77] assign pma_checker__entries_T_193 = pma_checker__entries_WIRE_17[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_c = pma_checker__entries_T_193; // @[TLB.scala:170:77] assign pma_checker__entries_T_194 = pma_checker__entries_WIRE_17[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_eff = pma_checker__entries_T_194; // @[TLB.scala:170:77] assign pma_checker__entries_T_195 = pma_checker__entries_WIRE_17[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_paa = pma_checker__entries_T_195; // @[TLB.scala:170:77] assign pma_checker__entries_T_196 = pma_checker__entries_WIRE_17[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_pal = pma_checker__entries_T_196; // @[TLB.scala:170:77] assign pma_checker__entries_T_197 = pma_checker__entries_WIRE_17[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_ppp = pma_checker__entries_T_197; // @[TLB.scala:170:77] assign pma_checker__entries_T_198 = pma_checker__entries_WIRE_17[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_pr = pma_checker__entries_T_198; // @[TLB.scala:170:77] assign pma_checker__entries_T_199 = pma_checker__entries_WIRE_17[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_px = pma_checker__entries_T_199; // @[TLB.scala:170:77] assign pma_checker__entries_T_200 = pma_checker__entries_WIRE_17[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_pw = pma_checker__entries_T_200; // @[TLB.scala:170:77] assign pma_checker__entries_T_201 = pma_checker__entries_WIRE_17[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_hr = pma_checker__entries_T_201; // @[TLB.scala:170:77] assign pma_checker__entries_T_202 = pma_checker__entries_WIRE_17[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_hx = pma_checker__entries_T_202; // @[TLB.scala:170:77] assign pma_checker__entries_T_203 = pma_checker__entries_WIRE_17[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_hw = pma_checker__entries_T_203; // @[TLB.scala:170:77] assign pma_checker__entries_T_204 = pma_checker__entries_WIRE_17[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_sr = pma_checker__entries_T_204; // @[TLB.scala:170:77] assign pma_checker__entries_T_205 = pma_checker__entries_WIRE_17[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_sx = pma_checker__entries_T_205; // @[TLB.scala:170:77] assign pma_checker__entries_T_206 = pma_checker__entries_WIRE_17[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_sw = pma_checker__entries_T_206; // @[TLB.scala:170:77] assign pma_checker__entries_T_207 = pma_checker__entries_WIRE_17[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_gf = pma_checker__entries_T_207; // @[TLB.scala:170:77] assign pma_checker__entries_T_208 = pma_checker__entries_WIRE_17[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_pf = pma_checker__entries_T_208; // @[TLB.scala:170:77] assign pma_checker__entries_T_209 = pma_checker__entries_WIRE_17[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_ae_stage2 = pma_checker__entries_T_209; // @[TLB.scala:170:77] assign pma_checker__entries_T_210 = pma_checker__entries_WIRE_17[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_ae_final = pma_checker__entries_T_210; // @[TLB.scala:170:77] assign pma_checker__entries_T_211 = pma_checker__entries_WIRE_17[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_ae_ptw = pma_checker__entries_T_211; // @[TLB.scala:170:77] assign pma_checker__entries_T_212 = pma_checker__entries_WIRE_17[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_g = pma_checker__entries_T_212; // @[TLB.scala:170:77] assign pma_checker__entries_T_213 = pma_checker__entries_WIRE_17[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_u = pma_checker__entries_T_213; // @[TLB.scala:170:77] assign pma_checker__entries_T_214 = pma_checker__entries_WIRE_17[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_16_ppn = pma_checker__entries_T_214; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_237; // @[TLB.scala:170:77] wire pma_checker__entries_T_236; // @[TLB.scala:170:77] wire pma_checker__entries_T_235; // @[TLB.scala:170:77] wire pma_checker__entries_T_234; // @[TLB.scala:170:77] wire pma_checker__entries_T_233; // @[TLB.scala:170:77] wire pma_checker__entries_T_232; // @[TLB.scala:170:77] wire pma_checker__entries_T_231; // @[TLB.scala:170:77] wire pma_checker__entries_T_230; // @[TLB.scala:170:77] wire pma_checker__entries_T_229; // @[TLB.scala:170:77] wire pma_checker__entries_T_228; // @[TLB.scala:170:77] wire pma_checker__entries_T_227; // @[TLB.scala:170:77] wire pma_checker__entries_T_226; // @[TLB.scala:170:77] wire pma_checker__entries_T_225; // @[TLB.scala:170:77] wire pma_checker__entries_T_224; // @[TLB.scala:170:77] wire pma_checker__entries_T_223; // @[TLB.scala:170:77] wire pma_checker__entries_T_222; // @[TLB.scala:170:77] wire pma_checker__entries_T_221; // @[TLB.scala:170:77] wire pma_checker__entries_T_220; // @[TLB.scala:170:77] wire pma_checker__entries_T_219; // @[TLB.scala:170:77] wire pma_checker__entries_T_218; // @[TLB.scala:170:77] wire pma_checker__entries_T_217; // @[TLB.scala:170:77] wire pma_checker__entries_T_216; // @[TLB.scala:170:77] wire pma_checker__entries_T_215; // @[TLB.scala:170:77] assign pma_checker__entries_T_215 = pma_checker__entries_WIRE_19[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_fragmented_superpage = pma_checker__entries_T_215; // @[TLB.scala:170:77] assign pma_checker__entries_T_216 = pma_checker__entries_WIRE_19[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_c = pma_checker__entries_T_216; // @[TLB.scala:170:77] assign pma_checker__entries_T_217 = pma_checker__entries_WIRE_19[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_eff = pma_checker__entries_T_217; // @[TLB.scala:170:77] assign pma_checker__entries_T_218 = pma_checker__entries_WIRE_19[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_paa = pma_checker__entries_T_218; // @[TLB.scala:170:77] assign pma_checker__entries_T_219 = pma_checker__entries_WIRE_19[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_pal = pma_checker__entries_T_219; // @[TLB.scala:170:77] assign pma_checker__entries_T_220 = pma_checker__entries_WIRE_19[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_ppp = pma_checker__entries_T_220; // @[TLB.scala:170:77] assign pma_checker__entries_T_221 = pma_checker__entries_WIRE_19[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_pr = pma_checker__entries_T_221; // @[TLB.scala:170:77] assign pma_checker__entries_T_222 = pma_checker__entries_WIRE_19[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_px = pma_checker__entries_T_222; // @[TLB.scala:170:77] assign pma_checker__entries_T_223 = pma_checker__entries_WIRE_19[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_pw = pma_checker__entries_T_223; // @[TLB.scala:170:77] assign pma_checker__entries_T_224 = pma_checker__entries_WIRE_19[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_hr = pma_checker__entries_T_224; // @[TLB.scala:170:77] assign pma_checker__entries_T_225 = pma_checker__entries_WIRE_19[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_hx = pma_checker__entries_T_225; // @[TLB.scala:170:77] assign pma_checker__entries_T_226 = pma_checker__entries_WIRE_19[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_hw = pma_checker__entries_T_226; // @[TLB.scala:170:77] assign pma_checker__entries_T_227 = pma_checker__entries_WIRE_19[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_sr = pma_checker__entries_T_227; // @[TLB.scala:170:77] assign pma_checker__entries_T_228 = pma_checker__entries_WIRE_19[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_sx = pma_checker__entries_T_228; // @[TLB.scala:170:77] assign pma_checker__entries_T_229 = pma_checker__entries_WIRE_19[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_sw = pma_checker__entries_T_229; // @[TLB.scala:170:77] assign pma_checker__entries_T_230 = pma_checker__entries_WIRE_19[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_gf = pma_checker__entries_T_230; // @[TLB.scala:170:77] assign pma_checker__entries_T_231 = pma_checker__entries_WIRE_19[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_pf = pma_checker__entries_T_231; // @[TLB.scala:170:77] assign pma_checker__entries_T_232 = pma_checker__entries_WIRE_19[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_ae_stage2 = pma_checker__entries_T_232; // @[TLB.scala:170:77] assign pma_checker__entries_T_233 = pma_checker__entries_WIRE_19[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_ae_final = pma_checker__entries_T_233; // @[TLB.scala:170:77] assign pma_checker__entries_T_234 = pma_checker__entries_WIRE_19[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_ae_ptw = pma_checker__entries_T_234; // @[TLB.scala:170:77] assign pma_checker__entries_T_235 = pma_checker__entries_WIRE_19[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_g = pma_checker__entries_T_235; // @[TLB.scala:170:77] assign pma_checker__entries_T_236 = pma_checker__entries_WIRE_19[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_u = pma_checker__entries_T_236; // @[TLB.scala:170:77] assign pma_checker__entries_T_237 = pma_checker__entries_WIRE_19[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_18_ppn = pma_checker__entries_T_237; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_260; // @[TLB.scala:170:77] wire pma_checker__entries_T_259; // @[TLB.scala:170:77] wire pma_checker__entries_T_258; // @[TLB.scala:170:77] wire pma_checker__entries_T_257; // @[TLB.scala:170:77] wire pma_checker__entries_T_256; // @[TLB.scala:170:77] wire pma_checker__entries_T_255; // @[TLB.scala:170:77] wire pma_checker__entries_T_254; // @[TLB.scala:170:77] wire pma_checker__entries_T_253; // @[TLB.scala:170:77] wire pma_checker__entries_T_252; // @[TLB.scala:170:77] wire pma_checker__entries_T_251; // @[TLB.scala:170:77] wire pma_checker__entries_T_250; // @[TLB.scala:170:77] wire pma_checker__entries_T_249; // @[TLB.scala:170:77] wire pma_checker__entries_T_248; // @[TLB.scala:170:77] wire pma_checker__entries_T_247; // @[TLB.scala:170:77] wire pma_checker__entries_T_246; // @[TLB.scala:170:77] wire pma_checker__entries_T_245; // @[TLB.scala:170:77] wire pma_checker__entries_T_244; // @[TLB.scala:170:77] wire pma_checker__entries_T_243; // @[TLB.scala:170:77] wire pma_checker__entries_T_242; // @[TLB.scala:170:77] wire pma_checker__entries_T_241; // @[TLB.scala:170:77] wire pma_checker__entries_T_240; // @[TLB.scala:170:77] wire pma_checker__entries_T_239; // @[TLB.scala:170:77] wire pma_checker__entries_T_238; // @[TLB.scala:170:77] assign pma_checker__entries_T_238 = pma_checker__entries_WIRE_21[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_fragmented_superpage = pma_checker__entries_T_238; // @[TLB.scala:170:77] assign pma_checker__entries_T_239 = pma_checker__entries_WIRE_21[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_c = pma_checker__entries_T_239; // @[TLB.scala:170:77] assign pma_checker__entries_T_240 = pma_checker__entries_WIRE_21[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_eff = pma_checker__entries_T_240; // @[TLB.scala:170:77] assign pma_checker__entries_T_241 = pma_checker__entries_WIRE_21[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_paa = pma_checker__entries_T_241; // @[TLB.scala:170:77] assign pma_checker__entries_T_242 = pma_checker__entries_WIRE_21[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_pal = pma_checker__entries_T_242; // @[TLB.scala:170:77] assign pma_checker__entries_T_243 = pma_checker__entries_WIRE_21[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_ppp = pma_checker__entries_T_243; // @[TLB.scala:170:77] assign pma_checker__entries_T_244 = pma_checker__entries_WIRE_21[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_pr = pma_checker__entries_T_244; // @[TLB.scala:170:77] assign pma_checker__entries_T_245 = pma_checker__entries_WIRE_21[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_px = pma_checker__entries_T_245; // @[TLB.scala:170:77] assign pma_checker__entries_T_246 = pma_checker__entries_WIRE_21[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_pw = pma_checker__entries_T_246; // @[TLB.scala:170:77] assign pma_checker__entries_T_247 = pma_checker__entries_WIRE_21[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_hr = pma_checker__entries_T_247; // @[TLB.scala:170:77] assign pma_checker__entries_T_248 = pma_checker__entries_WIRE_21[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_hx = pma_checker__entries_T_248; // @[TLB.scala:170:77] assign pma_checker__entries_T_249 = pma_checker__entries_WIRE_21[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_hw = pma_checker__entries_T_249; // @[TLB.scala:170:77] assign pma_checker__entries_T_250 = pma_checker__entries_WIRE_21[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_sr = pma_checker__entries_T_250; // @[TLB.scala:170:77] assign pma_checker__entries_T_251 = pma_checker__entries_WIRE_21[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_sx = pma_checker__entries_T_251; // @[TLB.scala:170:77] assign pma_checker__entries_T_252 = pma_checker__entries_WIRE_21[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_sw = pma_checker__entries_T_252; // @[TLB.scala:170:77] assign pma_checker__entries_T_253 = pma_checker__entries_WIRE_21[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_gf = pma_checker__entries_T_253; // @[TLB.scala:170:77] assign pma_checker__entries_T_254 = pma_checker__entries_WIRE_21[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_pf = pma_checker__entries_T_254; // @[TLB.scala:170:77] assign pma_checker__entries_T_255 = pma_checker__entries_WIRE_21[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_ae_stage2 = pma_checker__entries_T_255; // @[TLB.scala:170:77] assign pma_checker__entries_T_256 = pma_checker__entries_WIRE_21[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_ae_final = pma_checker__entries_T_256; // @[TLB.scala:170:77] assign pma_checker__entries_T_257 = pma_checker__entries_WIRE_21[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_ae_ptw = pma_checker__entries_T_257; // @[TLB.scala:170:77] assign pma_checker__entries_T_258 = pma_checker__entries_WIRE_21[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_g = pma_checker__entries_T_258; // @[TLB.scala:170:77] assign pma_checker__entries_T_259 = pma_checker__entries_WIRE_21[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_u = pma_checker__entries_T_259; // @[TLB.scala:170:77] assign pma_checker__entries_T_260 = pma_checker__entries_WIRE_21[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_20_ppn = pma_checker__entries_T_260; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_283; // @[TLB.scala:170:77] wire pma_checker__entries_T_282; // @[TLB.scala:170:77] wire pma_checker__entries_T_281; // @[TLB.scala:170:77] wire pma_checker__entries_T_280; // @[TLB.scala:170:77] wire pma_checker__entries_T_279; // @[TLB.scala:170:77] wire pma_checker__entries_T_278; // @[TLB.scala:170:77] wire pma_checker__entries_T_277; // @[TLB.scala:170:77] wire pma_checker__entries_T_276; // @[TLB.scala:170:77] wire pma_checker__entries_T_275; // @[TLB.scala:170:77] wire pma_checker__entries_T_274; // @[TLB.scala:170:77] wire pma_checker__entries_T_273; // @[TLB.scala:170:77] wire pma_checker__entries_T_272; // @[TLB.scala:170:77] wire pma_checker__entries_T_271; // @[TLB.scala:170:77] wire pma_checker__entries_T_270; // @[TLB.scala:170:77] wire pma_checker__entries_T_269; // @[TLB.scala:170:77] wire pma_checker__entries_T_268; // @[TLB.scala:170:77] wire pma_checker__entries_T_267; // @[TLB.scala:170:77] wire pma_checker__entries_T_266; // @[TLB.scala:170:77] wire pma_checker__entries_T_265; // @[TLB.scala:170:77] wire pma_checker__entries_T_264; // @[TLB.scala:170:77] wire pma_checker__entries_T_263; // @[TLB.scala:170:77] wire pma_checker__entries_T_262; // @[TLB.scala:170:77] wire pma_checker__entries_T_261; // @[TLB.scala:170:77] assign pma_checker__entries_T_261 = pma_checker__entries_WIRE_23[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_fragmented_superpage = pma_checker__entries_T_261; // @[TLB.scala:170:77] assign pma_checker__entries_T_262 = pma_checker__entries_WIRE_23[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_c = pma_checker__entries_T_262; // @[TLB.scala:170:77] assign pma_checker__entries_T_263 = pma_checker__entries_WIRE_23[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_eff = pma_checker__entries_T_263; // @[TLB.scala:170:77] assign pma_checker__entries_T_264 = pma_checker__entries_WIRE_23[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_paa = pma_checker__entries_T_264; // @[TLB.scala:170:77] assign pma_checker__entries_T_265 = pma_checker__entries_WIRE_23[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_pal = pma_checker__entries_T_265; // @[TLB.scala:170:77] assign pma_checker__entries_T_266 = pma_checker__entries_WIRE_23[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_ppp = pma_checker__entries_T_266; // @[TLB.scala:170:77] assign pma_checker__entries_T_267 = pma_checker__entries_WIRE_23[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_pr = pma_checker__entries_T_267; // @[TLB.scala:170:77] assign pma_checker__entries_T_268 = pma_checker__entries_WIRE_23[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_px = pma_checker__entries_T_268; // @[TLB.scala:170:77] assign pma_checker__entries_T_269 = pma_checker__entries_WIRE_23[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_pw = pma_checker__entries_T_269; // @[TLB.scala:170:77] assign pma_checker__entries_T_270 = pma_checker__entries_WIRE_23[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_hr = pma_checker__entries_T_270; // @[TLB.scala:170:77] assign pma_checker__entries_T_271 = pma_checker__entries_WIRE_23[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_hx = pma_checker__entries_T_271; // @[TLB.scala:170:77] assign pma_checker__entries_T_272 = pma_checker__entries_WIRE_23[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_hw = pma_checker__entries_T_272; // @[TLB.scala:170:77] assign pma_checker__entries_T_273 = pma_checker__entries_WIRE_23[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_sr = pma_checker__entries_T_273; // @[TLB.scala:170:77] assign pma_checker__entries_T_274 = pma_checker__entries_WIRE_23[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_sx = pma_checker__entries_T_274; // @[TLB.scala:170:77] assign pma_checker__entries_T_275 = pma_checker__entries_WIRE_23[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_sw = pma_checker__entries_T_275; // @[TLB.scala:170:77] assign pma_checker__entries_T_276 = pma_checker__entries_WIRE_23[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_gf = pma_checker__entries_T_276; // @[TLB.scala:170:77] assign pma_checker__entries_T_277 = pma_checker__entries_WIRE_23[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_pf = pma_checker__entries_T_277; // @[TLB.scala:170:77] assign pma_checker__entries_T_278 = pma_checker__entries_WIRE_23[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_ae_stage2 = pma_checker__entries_T_278; // @[TLB.scala:170:77] assign pma_checker__entries_T_279 = pma_checker__entries_WIRE_23[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_ae_final = pma_checker__entries_T_279; // @[TLB.scala:170:77] assign pma_checker__entries_T_280 = pma_checker__entries_WIRE_23[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_ae_ptw = pma_checker__entries_T_280; // @[TLB.scala:170:77] assign pma_checker__entries_T_281 = pma_checker__entries_WIRE_23[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_g = pma_checker__entries_T_281; // @[TLB.scala:170:77] assign pma_checker__entries_T_282 = pma_checker__entries_WIRE_23[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_u = pma_checker__entries_T_282; // @[TLB.scala:170:77] assign pma_checker__entries_T_283 = pma_checker__entries_WIRE_23[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_22_ppn = pma_checker__entries_T_283; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_306; // @[TLB.scala:170:77] wire pma_checker__entries_T_305; // @[TLB.scala:170:77] wire pma_checker__entries_T_304; // @[TLB.scala:170:77] wire pma_checker__entries_T_303; // @[TLB.scala:170:77] wire pma_checker__entries_T_302; // @[TLB.scala:170:77] wire pma_checker__entries_T_301; // @[TLB.scala:170:77] wire pma_checker__entries_T_300; // @[TLB.scala:170:77] wire pma_checker__entries_T_299; // @[TLB.scala:170:77] wire pma_checker__entries_T_298; // @[TLB.scala:170:77] wire pma_checker__entries_T_297; // @[TLB.scala:170:77] wire pma_checker__entries_T_296; // @[TLB.scala:170:77] wire pma_checker__entries_T_295; // @[TLB.scala:170:77] wire pma_checker__entries_T_294; // @[TLB.scala:170:77] wire pma_checker__entries_T_293; // @[TLB.scala:170:77] wire pma_checker__entries_T_292; // @[TLB.scala:170:77] wire pma_checker__entries_T_291; // @[TLB.scala:170:77] wire pma_checker__entries_T_290; // @[TLB.scala:170:77] wire pma_checker__entries_T_289; // @[TLB.scala:170:77] wire pma_checker__entries_T_288; // @[TLB.scala:170:77] wire pma_checker__entries_T_287; // @[TLB.scala:170:77] wire pma_checker__entries_T_286; // @[TLB.scala:170:77] wire pma_checker__entries_T_285; // @[TLB.scala:170:77] wire pma_checker__entries_T_284; // @[TLB.scala:170:77] assign pma_checker__entries_T_284 = pma_checker__entries_WIRE_25[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_fragmented_superpage = pma_checker__entries_T_284; // @[TLB.scala:170:77] assign pma_checker__entries_T_285 = pma_checker__entries_WIRE_25[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_c = pma_checker__entries_T_285; // @[TLB.scala:170:77] assign pma_checker__entries_T_286 = pma_checker__entries_WIRE_25[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_eff = pma_checker__entries_T_286; // @[TLB.scala:170:77] assign pma_checker__entries_T_287 = pma_checker__entries_WIRE_25[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_paa = pma_checker__entries_T_287; // @[TLB.scala:170:77] assign pma_checker__entries_T_288 = pma_checker__entries_WIRE_25[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_pal = pma_checker__entries_T_288; // @[TLB.scala:170:77] assign pma_checker__entries_T_289 = pma_checker__entries_WIRE_25[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_ppp = pma_checker__entries_T_289; // @[TLB.scala:170:77] assign pma_checker__entries_T_290 = pma_checker__entries_WIRE_25[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_pr = pma_checker__entries_T_290; // @[TLB.scala:170:77] assign pma_checker__entries_T_291 = pma_checker__entries_WIRE_25[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_px = pma_checker__entries_T_291; // @[TLB.scala:170:77] assign pma_checker__entries_T_292 = pma_checker__entries_WIRE_25[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_pw = pma_checker__entries_T_292; // @[TLB.scala:170:77] assign pma_checker__entries_T_293 = pma_checker__entries_WIRE_25[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_hr = pma_checker__entries_T_293; // @[TLB.scala:170:77] assign pma_checker__entries_T_294 = pma_checker__entries_WIRE_25[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_hx = pma_checker__entries_T_294; // @[TLB.scala:170:77] assign pma_checker__entries_T_295 = pma_checker__entries_WIRE_25[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_hw = pma_checker__entries_T_295; // @[TLB.scala:170:77] assign pma_checker__entries_T_296 = pma_checker__entries_WIRE_25[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_sr = pma_checker__entries_T_296; // @[TLB.scala:170:77] assign pma_checker__entries_T_297 = pma_checker__entries_WIRE_25[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_sx = pma_checker__entries_T_297; // @[TLB.scala:170:77] assign pma_checker__entries_T_298 = pma_checker__entries_WIRE_25[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_sw = pma_checker__entries_T_298; // @[TLB.scala:170:77] assign pma_checker__entries_T_299 = pma_checker__entries_WIRE_25[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_gf = pma_checker__entries_T_299; // @[TLB.scala:170:77] assign pma_checker__entries_T_300 = pma_checker__entries_WIRE_25[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_pf = pma_checker__entries_T_300; // @[TLB.scala:170:77] assign pma_checker__entries_T_301 = pma_checker__entries_WIRE_25[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_ae_stage2 = pma_checker__entries_T_301; // @[TLB.scala:170:77] assign pma_checker__entries_T_302 = pma_checker__entries_WIRE_25[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_ae_final = pma_checker__entries_T_302; // @[TLB.scala:170:77] assign pma_checker__entries_T_303 = pma_checker__entries_WIRE_25[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_ae_ptw = pma_checker__entries_T_303; // @[TLB.scala:170:77] assign pma_checker__entries_T_304 = pma_checker__entries_WIRE_25[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_g = pma_checker__entries_T_304; // @[TLB.scala:170:77] assign pma_checker__entries_T_305 = pma_checker__entries_WIRE_25[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_u = pma_checker__entries_T_305; // @[TLB.scala:170:77] assign pma_checker__entries_T_306 = pma_checker__entries_WIRE_25[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_24_ppn = pma_checker__entries_T_306; // @[TLB.scala:170:77] wire [19:0] pma_checker__ppn_T_1 = pma_checker_vpn[19:0]; // @[TLB.scala:335:30, :502:125] wire [19:0] pma_checker__ppn_T_15 = pma_checker__ppn_T_1; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_28 = pma_checker__ppn_T_15; // @[Mux.scala:30:73] wire [19:0] pma_checker_ppn = pma_checker__ppn_T_28; // @[Mux.scala:30:73] wire [1:0] pma_checker_ptw_ae_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_ae_ptw, _pma_checker_entries_barrier_1_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ptw_ae_array_lo_lo = {pma_checker_ptw_ae_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_ptw_ae_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_ae_ptw, _pma_checker_entries_barrier_4_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ptw_ae_array_lo_hi = {pma_checker_ptw_ae_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_ptw_ae_array_lo = {pma_checker_ptw_ae_array_lo_hi, pma_checker_ptw_ae_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_ptw_ae_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_ae_ptw, _pma_checker_entries_barrier_7_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ptw_ae_array_hi_lo = {pma_checker_ptw_ae_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_ptw_ae_array_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_ae_ptw, _pma_checker_entries_barrier_9_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_ptw_ae_array_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_ae_ptw, _pma_checker_entries_barrier_11_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_ptw_ae_array_hi_hi = {pma_checker_ptw_ae_array_hi_hi_hi, pma_checker_ptw_ae_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_ptw_ae_array_hi = {pma_checker_ptw_ae_array_hi_hi, pma_checker_ptw_ae_array_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__ptw_ae_array_T = {pma_checker_ptw_ae_array_hi, pma_checker_ptw_ae_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker_ptw_ae_array = {1'h0, pma_checker__ptw_ae_array_T}; // @[package.scala:45:27] wire [1:0] pma_checker_final_ae_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_ae_final, _pma_checker_entries_barrier_1_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_final_ae_array_lo_lo = {pma_checker_final_ae_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_final_ae_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_ae_final, _pma_checker_entries_barrier_4_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_final_ae_array_lo_hi = {pma_checker_final_ae_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_final_ae_array_lo = {pma_checker_final_ae_array_lo_hi, pma_checker_final_ae_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_final_ae_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_ae_final, _pma_checker_entries_barrier_7_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_final_ae_array_hi_lo = {pma_checker_final_ae_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_final_ae_array_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_ae_final, _pma_checker_entries_barrier_9_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_final_ae_array_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_ae_final, _pma_checker_entries_barrier_11_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_final_ae_array_hi_hi = {pma_checker_final_ae_array_hi_hi_hi, pma_checker_final_ae_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_final_ae_array_hi = {pma_checker_final_ae_array_hi_hi, pma_checker_final_ae_array_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__final_ae_array_T = {pma_checker_final_ae_array_hi, pma_checker_final_ae_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker_final_ae_array = {1'h0, pma_checker__final_ae_array_T}; // @[package.scala:45:27] wire [1:0] pma_checker_ptw_pf_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_pf, _pma_checker_entries_barrier_1_io_y_pf}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ptw_pf_array_lo_lo = {pma_checker_ptw_pf_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_pf}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_ptw_pf_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_pf, _pma_checker_entries_barrier_4_io_y_pf}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ptw_pf_array_lo_hi = {pma_checker_ptw_pf_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_pf}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_ptw_pf_array_lo = {pma_checker_ptw_pf_array_lo_hi, pma_checker_ptw_pf_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_ptw_pf_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_pf, _pma_checker_entries_barrier_7_io_y_pf}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ptw_pf_array_hi_lo = {pma_checker_ptw_pf_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_pf}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_ptw_pf_array_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_pf, _pma_checker_entries_barrier_9_io_y_pf}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_ptw_pf_array_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_pf, _pma_checker_entries_barrier_11_io_y_pf}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_ptw_pf_array_hi_hi = {pma_checker_ptw_pf_array_hi_hi_hi, pma_checker_ptw_pf_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_ptw_pf_array_hi = {pma_checker_ptw_pf_array_hi_hi, pma_checker_ptw_pf_array_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__ptw_pf_array_T = {pma_checker_ptw_pf_array_hi, pma_checker_ptw_pf_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker_ptw_pf_array = {1'h0, pma_checker__ptw_pf_array_T}; // @[package.scala:45:27] wire [1:0] pma_checker_ptw_gf_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_gf, _pma_checker_entries_barrier_1_io_y_gf}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ptw_gf_array_lo_lo = {pma_checker_ptw_gf_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_gf}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_ptw_gf_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_gf, _pma_checker_entries_barrier_4_io_y_gf}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ptw_gf_array_lo_hi = {pma_checker_ptw_gf_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_gf}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_ptw_gf_array_lo = {pma_checker_ptw_gf_array_lo_hi, pma_checker_ptw_gf_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_ptw_gf_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_gf, _pma_checker_entries_barrier_7_io_y_gf}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ptw_gf_array_hi_lo = {pma_checker_ptw_gf_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_gf}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_ptw_gf_array_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_gf, _pma_checker_entries_barrier_9_io_y_gf}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_ptw_gf_array_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_gf, _pma_checker_entries_barrier_11_io_y_gf}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_ptw_gf_array_hi_hi = {pma_checker_ptw_gf_array_hi_hi_hi, pma_checker_ptw_gf_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_ptw_gf_array_hi = {pma_checker_ptw_gf_array_hi_hi, pma_checker_ptw_gf_array_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__ptw_gf_array_T = {pma_checker_ptw_gf_array_hi, pma_checker_ptw_gf_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker_ptw_gf_array = {1'h0, pma_checker__ptw_gf_array_T}; // @[package.scala:45:27] wire [13:0] pma_checker__gf_ld_array_T_3 = pma_checker_ptw_gf_array; // @[TLB.scala:509:25, :600:82] wire [13:0] pma_checker__gf_st_array_T_2 = pma_checker_ptw_gf_array; // @[TLB.scala:509:25, :601:63] wire [13:0] pma_checker__gf_inst_array_T_1 = pma_checker_ptw_gf_array; // @[TLB.scala:509:25, :602:46] wire pma_checker__priv_rw_ok_T = ~pma_checker_priv_s; // @[TLB.scala:370:20, :513:24] wire pma_checker__priv_rw_ok_T_1 = pma_checker__priv_rw_ok_T; // @[TLB.scala:513:{24,32}] wire [1:0] _GEN_5 = {_pma_checker_entries_barrier_2_io_y_u, _pma_checker_entries_barrier_1_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_priv_rw_ok_lo_lo_hi; // @[package.scala:45:27] assign pma_checker_priv_rw_ok_lo_lo_hi = _GEN_5; // @[package.scala:45:27] wire [1:0] pma_checker_priv_rw_ok_lo_lo_hi_1; // @[package.scala:45:27] assign pma_checker_priv_rw_ok_lo_lo_hi_1 = _GEN_5; // @[package.scala:45:27] wire [1:0] pma_checker_priv_x_ok_lo_lo_hi; // @[package.scala:45:27] assign pma_checker_priv_x_ok_lo_lo_hi = _GEN_5; // @[package.scala:45:27] wire [1:0] pma_checker_priv_x_ok_lo_lo_hi_1; // @[package.scala:45:27] assign pma_checker_priv_x_ok_lo_lo_hi_1 = _GEN_5; // @[package.scala:45:27] wire [2:0] pma_checker_priv_rw_ok_lo_lo = {pma_checker_priv_rw_ok_lo_lo_hi, _pma_checker_entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_6 = {_pma_checker_entries_barrier_5_io_y_u, _pma_checker_entries_barrier_4_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_priv_rw_ok_lo_hi_hi; // @[package.scala:45:27] assign pma_checker_priv_rw_ok_lo_hi_hi = _GEN_6; // @[package.scala:45:27] wire [1:0] pma_checker_priv_rw_ok_lo_hi_hi_1; // @[package.scala:45:27] assign pma_checker_priv_rw_ok_lo_hi_hi_1 = _GEN_6; // @[package.scala:45:27] wire [1:0] pma_checker_priv_x_ok_lo_hi_hi; // @[package.scala:45:27] assign pma_checker_priv_x_ok_lo_hi_hi = _GEN_6; // @[package.scala:45:27] wire [1:0] pma_checker_priv_x_ok_lo_hi_hi_1; // @[package.scala:45:27] assign pma_checker_priv_x_ok_lo_hi_hi_1 = _GEN_6; // @[package.scala:45:27] wire [2:0] pma_checker_priv_rw_ok_lo_hi = {pma_checker_priv_rw_ok_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_priv_rw_ok_lo = {pma_checker_priv_rw_ok_lo_hi, pma_checker_priv_rw_ok_lo_lo}; // @[package.scala:45:27] wire [1:0] _GEN_7 = {_pma_checker_entries_barrier_8_io_y_u, _pma_checker_entries_barrier_7_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_priv_rw_ok_hi_lo_hi; // @[package.scala:45:27] assign pma_checker_priv_rw_ok_hi_lo_hi = _GEN_7; // @[package.scala:45:27] wire [1:0] pma_checker_priv_rw_ok_hi_lo_hi_1; // @[package.scala:45:27] assign pma_checker_priv_rw_ok_hi_lo_hi_1 = _GEN_7; // @[package.scala:45:27] wire [1:0] pma_checker_priv_x_ok_hi_lo_hi; // @[package.scala:45:27] assign pma_checker_priv_x_ok_hi_lo_hi = _GEN_7; // @[package.scala:45:27] wire [1:0] pma_checker_priv_x_ok_hi_lo_hi_1; // @[package.scala:45:27] assign pma_checker_priv_x_ok_hi_lo_hi_1 = _GEN_7; // @[package.scala:45:27] wire [2:0] pma_checker_priv_rw_ok_hi_lo = {pma_checker_priv_rw_ok_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_8 = {_pma_checker_entries_barrier_10_io_y_u, _pma_checker_entries_barrier_9_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_priv_rw_ok_hi_hi_lo; // @[package.scala:45:27] assign pma_checker_priv_rw_ok_hi_hi_lo = _GEN_8; // @[package.scala:45:27] wire [1:0] pma_checker_priv_rw_ok_hi_hi_lo_1; // @[package.scala:45:27] assign pma_checker_priv_rw_ok_hi_hi_lo_1 = _GEN_8; // @[package.scala:45:27] wire [1:0] pma_checker_priv_x_ok_hi_hi_lo; // @[package.scala:45:27] assign pma_checker_priv_x_ok_hi_hi_lo = _GEN_8; // @[package.scala:45:27] wire [1:0] pma_checker_priv_x_ok_hi_hi_lo_1; // @[package.scala:45:27] assign pma_checker_priv_x_ok_hi_hi_lo_1 = _GEN_8; // @[package.scala:45:27] wire [1:0] _GEN_9 = {_pma_checker_entries_barrier_12_io_y_u, _pma_checker_entries_barrier_11_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_priv_rw_ok_hi_hi_hi; // @[package.scala:45:27] assign pma_checker_priv_rw_ok_hi_hi_hi = _GEN_9; // @[package.scala:45:27] wire [1:0] pma_checker_priv_rw_ok_hi_hi_hi_1; // @[package.scala:45:27] assign pma_checker_priv_rw_ok_hi_hi_hi_1 = _GEN_9; // @[package.scala:45:27] wire [1:0] pma_checker_priv_x_ok_hi_hi_hi; // @[package.scala:45:27] assign pma_checker_priv_x_ok_hi_hi_hi = _GEN_9; // @[package.scala:45:27] wire [1:0] pma_checker_priv_x_ok_hi_hi_hi_1; // @[package.scala:45:27] assign pma_checker_priv_x_ok_hi_hi_hi_1 = _GEN_9; // @[package.scala:45:27] wire [3:0] pma_checker_priv_rw_ok_hi_hi = {pma_checker_priv_rw_ok_hi_hi_hi, pma_checker_priv_rw_ok_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_priv_rw_ok_hi = {pma_checker_priv_rw_ok_hi_hi, pma_checker_priv_rw_ok_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__priv_rw_ok_T_2 = {pma_checker_priv_rw_ok_hi, pma_checker_priv_rw_ok_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__priv_rw_ok_T_3 = pma_checker__priv_rw_ok_T_1 ? pma_checker__priv_rw_ok_T_2 : 13'h0; // @[package.scala:45:27] wire [2:0] pma_checker_priv_rw_ok_lo_lo_1 = {pma_checker_priv_rw_ok_lo_lo_hi_1, _pma_checker_entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_priv_rw_ok_lo_hi_1 = {pma_checker_priv_rw_ok_lo_hi_hi_1, _pma_checker_entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_priv_rw_ok_lo_1 = {pma_checker_priv_rw_ok_lo_hi_1, pma_checker_priv_rw_ok_lo_lo_1}; // @[package.scala:45:27] wire [2:0] pma_checker_priv_rw_ok_hi_lo_1 = {pma_checker_priv_rw_ok_hi_lo_hi_1, _pma_checker_entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_priv_rw_ok_hi_hi_1 = {pma_checker_priv_rw_ok_hi_hi_hi_1, pma_checker_priv_rw_ok_hi_hi_lo_1}; // @[package.scala:45:27] wire [6:0] pma_checker_priv_rw_ok_hi_1 = {pma_checker_priv_rw_ok_hi_hi_1, pma_checker_priv_rw_ok_hi_lo_1}; // @[package.scala:45:27] wire [12:0] pma_checker__priv_rw_ok_T_4 = {pma_checker_priv_rw_ok_hi_1, pma_checker_priv_rw_ok_lo_1}; // @[package.scala:45:27] wire [12:0] pma_checker__priv_rw_ok_T_5 = ~pma_checker__priv_rw_ok_T_4; // @[package.scala:45:27] wire [12:0] pma_checker__priv_rw_ok_T_6 = pma_checker_priv_s ? pma_checker__priv_rw_ok_T_5 : 13'h0; // @[TLB.scala:370:20, :513:{75,84}] wire [12:0] pma_checker_priv_rw_ok = pma_checker__priv_rw_ok_T_3 \| pma_checker__priv_rw_ok_T_6; // @[TLB.scala:513:{23,70,75}] wire [2:0] pma_checker_priv_x_ok_lo_lo = {pma_checker_priv_x_ok_lo_lo_hi, _pma_checker_entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_priv_x_ok_lo_hi = {pma_checker_priv_x_ok_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_priv_x_ok_lo = {pma_checker_priv_x_ok_lo_hi, pma_checker_priv_x_ok_lo_lo}; // @[package.scala:45:27] wire [2:0] pma_checker_priv_x_ok_hi_lo = {pma_checker_priv_x_ok_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_priv_x_ok_hi_hi = {pma_checker_priv_x_ok_hi_hi_hi, pma_checker_priv_x_ok_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_priv_x_ok_hi = {pma_checker_priv_x_ok_hi_hi, pma_checker_priv_x_ok_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__priv_x_ok_T = {pma_checker_priv_x_ok_hi, pma_checker_priv_x_ok_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__priv_x_ok_T_1 = ~pma_checker__priv_x_ok_T; // @[package.scala:45:27] wire [2:0] pma_checker_priv_x_ok_lo_lo_1 = {pma_checker_priv_x_ok_lo_lo_hi_1, _pma_checker_entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_priv_x_ok_lo_hi_1 = {pma_checker_priv_x_ok_lo_hi_hi_1, _pma_checker_entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_priv_x_ok_lo_1 = {pma_checker_priv_x_ok_lo_hi_1, pma_checker_priv_x_ok_lo_lo_1}; // @[package.scala:45:27] wire [2:0] pma_checker_priv_x_ok_hi_lo_1 = {pma_checker_priv_x_ok_hi_lo_hi_1, _pma_checker_entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_priv_x_ok_hi_hi_1 = {pma_checker_priv_x_ok_hi_hi_hi_1, pma_checker_priv_x_ok_hi_hi_lo_1}; // @[package.scala:45:27] wire [6:0] pma_checker_priv_x_ok_hi_1 = {pma_checker_priv_x_ok_hi_hi_1, pma_checker_priv_x_ok_hi_lo_1}; // @[package.scala:45:27] wire [12:0] pma_checker__priv_x_ok_T_2 = {pma_checker_priv_x_ok_hi_1, pma_checker_priv_x_ok_lo_1}; // @[package.scala:45:27] wire [12:0] pma_checker_priv_x_ok = pma_checker_priv_s ? pma_checker__priv_x_ok_T_1 : pma_checker__priv_x_ok_T_2; // @[package.scala:45:27] wire [1:0] pma_checker_stage1_bypass_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_ae_stage2, _pma_checker_entries_barrier_1_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_stage1_bypass_lo_lo = {pma_checker_stage1_bypass_lo_lo_hi, _pma_checker_entries_barrier_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_stage1_bypass_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_ae_stage2, _pma_checker_entries_barrier_4_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_stage1_bypass_lo_hi = {pma_checker_stage1_bypass_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_stage1_bypass_lo = {pma_checker_stage1_bypass_lo_hi, pma_checker_stage1_bypass_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_stage1_bypass_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_ae_stage2, _pma_checker_entries_barrier_7_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_stage1_bypass_hi_lo = {pma_checker_stage1_bypass_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_stage1_bypass_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_ae_stage2, _pma_checker_entries_barrier_9_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_stage1_bypass_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_ae_stage2, _pma_checker_entries_barrier_11_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_stage1_bypass_hi_hi = {pma_checker_stage1_bypass_hi_hi_hi, pma_checker_stage1_bypass_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_stage1_bypass_hi = {pma_checker_stage1_bypass_hi_hi, pma_checker_stage1_bypass_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__stage1_bypass_T_3 = {pma_checker_stage1_bypass_hi, pma_checker_stage1_bypass_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_r_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_sr, _pma_checker_entries_barrier_1_io_y_sr}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_r_array_lo_lo = {pma_checker_r_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_sr}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_r_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_sr, _pma_checker_entries_barrier_4_io_y_sr}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_r_array_lo_hi = {pma_checker_r_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_sr}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_r_array_lo = {pma_checker_r_array_lo_hi, pma_checker_r_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_r_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_sr, _pma_checker_entries_barrier_7_io_y_sr}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_r_array_hi_lo = {pma_checker_r_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_sr}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_r_array_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_sr, _pma_checker_entries_barrier_9_io_y_sr}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_r_array_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_sr, _pma_checker_entries_barrier_11_io_y_sr}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_r_array_hi_hi = {pma_checker_r_array_hi_hi_hi, pma_checker_r_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_r_array_hi = {pma_checker_r_array_hi_hi, pma_checker_r_array_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__r_array_T = {pma_checker_r_array_hi, pma_checker_r_array_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__r_array_T_3 = pma_checker__r_array_T; // @[package.scala:45:27] wire [1:0] _GEN_10 = {_pma_checker_entries_barrier_2_io_y_sx, _pma_checker_entries_barrier_1_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_r_array_lo_lo_hi_1; // @[package.scala:45:27] assign pma_checker_r_array_lo_lo_hi_1 = _GEN_10; // @[package.scala:45:27] wire [1:0] pma_checker_x_array_lo_lo_hi; // @[package.scala:45:27] assign pma_checker_x_array_lo_lo_hi = _GEN_10; // @[package.scala:45:27] wire [2:0] pma_checker_r_array_lo_lo_1 = {pma_checker_r_array_lo_lo_hi_1, _pma_checker_entries_barrier_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_11 = {_pma_checker_entries_barrier_5_io_y_sx, _pma_checker_entries_barrier_4_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_r_array_lo_hi_hi_1; // @[package.scala:45:27] assign pma_checker_r_array_lo_hi_hi_1 = _GEN_11; // @[package.scala:45:27] wire [1:0] pma_checker_x_array_lo_hi_hi; // @[package.scala:45:27] assign pma_checker_x_array_lo_hi_hi = _GEN_11; // @[package.scala:45:27] wire [2:0] pma_checker_r_array_lo_hi_1 = {pma_checker_r_array_lo_hi_hi_1, _pma_checker_entries_barrier_3_io_y_sx}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_r_array_lo_1 = {pma_checker_r_array_lo_hi_1, pma_checker_r_array_lo_lo_1}; // @[package.scala:45:27] wire [1:0] _GEN_12 = {_pma_checker_entries_barrier_8_io_y_sx, _pma_checker_entries_barrier_7_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_r_array_hi_lo_hi_1; // @[package.scala:45:27] assign pma_checker_r_array_hi_lo_hi_1 = _GEN_12; // @[package.scala:45:27] wire [1:0] pma_checker_x_array_hi_lo_hi; // @[package.scala:45:27] assign pma_checker_x_array_hi_lo_hi = _GEN_12; // @[package.scala:45:27] wire [2:0] pma_checker_r_array_hi_lo_1 = {pma_checker_r_array_hi_lo_hi_1, _pma_checker_entries_barrier_6_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_13 = {_pma_checker_entries_barrier_10_io_y_sx, _pma_checker_entries_barrier_9_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_r_array_hi_hi_lo_1; // @[package.scala:45:27] assign pma_checker_r_array_hi_hi_lo_1 = _GEN_13; // @[package.scala:45:27] wire [1:0] pma_checker_x_array_hi_hi_lo; // @[package.scala:45:27] assign pma_checker_x_array_hi_hi_lo = _GEN_13; // @[package.scala:45:27] wire [1:0] _GEN_14 = {_pma_checker_entries_barrier_12_io_y_sx, _pma_checker_entries_barrier_11_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_r_array_hi_hi_hi_1; // @[package.scala:45:27] assign pma_checker_r_array_hi_hi_hi_1 = _GEN_14; // @[package.scala:45:27] wire [1:0] pma_checker_x_array_hi_hi_hi; // @[package.scala:45:27] assign pma_checker_x_array_hi_hi_hi = _GEN_14; // @[package.scala:45:27] wire [3:0] pma_checker_r_array_hi_hi_1 = {pma_checker_r_array_hi_hi_hi_1, pma_checker_r_array_hi_hi_lo_1}; // @[package.scala:45:27] wire [6:0] pma_checker_r_array_hi_1 = {pma_checker_r_array_hi_hi_1, pma_checker_r_array_hi_lo_1}; // @[package.scala:45:27] wire [12:0] pma_checker__r_array_T_1 = {pma_checker_r_array_hi_1, pma_checker_r_array_lo_1}; // @[package.scala:45:27] wire [12:0] pma_checker__r_array_T_4 = pma_checker_priv_rw_ok & pma_checker__r_array_T_3; // @[TLB.scala:513:70, :520:{41,69}] wire [12:0] pma_checker__r_array_T_5 = pma_checker__r_array_T_4; // @[TLB.scala:520:{41,113}] wire [13:0] pma_checker_r_array = {1'h1, pma_checker__r_array_T_5}; // @[TLB.scala:520:{20,113}] wire [13:0] pma_checker__pf_ld_array_T = pma_checker_r_array; // @[TLB.scala:520:20, :597:41] wire [1:0] pma_checker_w_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_sw, _pma_checker_entries_barrier_1_io_y_sw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_w_array_lo_lo = {pma_checker_w_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_sw}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_w_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_sw, _pma_checker_entries_barrier_4_io_y_sw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_w_array_lo_hi = {pma_checker_w_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_sw}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_w_array_lo = {pma_checker_w_array_lo_hi, pma_checker_w_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_w_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_sw, _pma_checker_entries_barrier_7_io_y_sw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_w_array_hi_lo = {pma_checker_w_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_sw}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_w_array_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_sw, _pma_checker_entries_barrier_9_io_y_sw}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_w_array_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_sw, _pma_checker_entries_barrier_11_io_y_sw}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_w_array_hi_hi = {pma_checker_w_array_hi_hi_hi, pma_checker_w_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_w_array_hi = {pma_checker_w_array_hi_hi, pma_checker_w_array_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__w_array_T = {pma_checker_w_array_hi, pma_checker_w_array_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__w_array_T_1 = pma_checker_priv_rw_ok & pma_checker__w_array_T; // @[package.scala:45:27] wire [12:0] pma_checker__w_array_T_2 = pma_checker__w_array_T_1; // @[TLB.scala:521:{41,69}] wire [13:0] pma_checker_w_array = {1'h1, pma_checker__w_array_T_2}; // @[TLB.scala:521:{20,69}] wire [2:0] pma_checker_x_array_lo_lo = {pma_checker_x_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_sx}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_x_array_lo_hi = {pma_checker_x_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_sx}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_x_array_lo = {pma_checker_x_array_lo_hi, pma_checker_x_array_lo_lo}; // @[package.scala:45:27] wire [2:0] pma_checker_x_array_hi_lo = {pma_checker_x_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_sx}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_x_array_hi_hi = {pma_checker_x_array_hi_hi_hi, pma_checker_x_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_x_array_hi = {pma_checker_x_array_hi_hi, pma_checker_x_array_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__x_array_T = {pma_checker_x_array_hi, pma_checker_x_array_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__x_array_T_1 = pma_checker_priv_x_ok & pma_checker__x_array_T; // @[package.scala:45:27] wire [12:0] pma_checker__x_array_T_2 = pma_checker__x_array_T_1; // @[TLB.scala:522:{40,68}] wire [13:0] pma_checker_x_array = {1'h1, pma_checker__x_array_T_2}; // @[TLB.scala:522:{20,68}] wire [1:0] pma_checker_hr_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_hr, _pma_checker_entries_barrier_1_io_y_hr}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_hr_array_lo_lo = {pma_checker_hr_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_hr}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_hr_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_hr, _pma_checker_entries_barrier_4_io_y_hr}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_hr_array_lo_hi = {pma_checker_hr_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_hr}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_hr_array_lo = {pma_checker_hr_array_lo_hi, pma_checker_hr_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_hr_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_hr, _pma_checker_entries_barrier_7_io_y_hr}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_hr_array_hi_lo = {pma_checker_hr_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_hr}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_hr_array_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_hr, _pma_checker_entries_barrier_9_io_y_hr}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_hr_array_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_hr, _pma_checker_entries_barrier_11_io_y_hr}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_hr_array_hi_hi = {pma_checker_hr_array_hi_hi_hi, pma_checker_hr_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_hr_array_hi = {pma_checker_hr_array_hi_hi, pma_checker_hr_array_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__hr_array_T = {pma_checker_hr_array_hi, pma_checker_hr_array_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__hr_array_T_3 = pma_checker__hr_array_T; // @[package.scala:45:27] wire [1:0] _GEN_15 = {_pma_checker_entries_barrier_2_io_y_hx, _pma_checker_entries_barrier_1_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_hr_array_lo_lo_hi_1; // @[package.scala:45:27] assign pma_checker_hr_array_lo_lo_hi_1 = _GEN_15; // @[package.scala:45:27] wire [1:0] pma_checker_hx_array_lo_lo_hi; // @[package.scala:45:27] assign pma_checker_hx_array_lo_lo_hi = _GEN_15; // @[package.scala:45:27] wire [2:0] pma_checker_hr_array_lo_lo_1 = {pma_checker_hr_array_lo_lo_hi_1, _pma_checker_entries_barrier_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_16 = {_pma_checker_entries_barrier_5_io_y_hx, _pma_checker_entries_barrier_4_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_hr_array_lo_hi_hi_1; // @[package.scala:45:27] assign pma_checker_hr_array_lo_hi_hi_1 = _GEN_16; // @[package.scala:45:27] wire [1:0] pma_checker_hx_array_lo_hi_hi; // @[package.scala:45:27] assign pma_checker_hx_array_lo_hi_hi = _GEN_16; // @[package.scala:45:27] wire [2:0] pma_checker_hr_array_lo_hi_1 = {pma_checker_hr_array_lo_hi_hi_1, _pma_checker_entries_barrier_3_io_y_hx}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_hr_array_lo_1 = {pma_checker_hr_array_lo_hi_1, pma_checker_hr_array_lo_lo_1}; // @[package.scala:45:27] wire [1:0] _GEN_17 = {_pma_checker_entries_barrier_8_io_y_hx, _pma_checker_entries_barrier_7_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_hr_array_hi_lo_hi_1; // @[package.scala:45:27] assign pma_checker_hr_array_hi_lo_hi_1 = _GEN_17; // @[package.scala:45:27] wire [1:0] pma_checker_hx_array_hi_lo_hi; // @[package.scala:45:27] assign pma_checker_hx_array_hi_lo_hi = _GEN_17; // @[package.scala:45:27] wire [2:0] pma_checker_hr_array_hi_lo_1 = {pma_checker_hr_array_hi_lo_hi_1, _pma_checker_entries_barrier_6_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_18 = {_pma_checker_entries_barrier_10_io_y_hx, _pma_checker_entries_barrier_9_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_hr_array_hi_hi_lo_1; // @[package.scala:45:27] assign pma_checker_hr_array_hi_hi_lo_1 = _GEN_18; // @[package.scala:45:27] wire [1:0] pma_checker_hx_array_hi_hi_lo; // @[package.scala:45:27] assign pma_checker_hx_array_hi_hi_lo = _GEN_18; // @[package.scala:45:27] wire [1:0] _GEN_19 = {_pma_checker_entries_barrier_12_io_y_hx, _pma_checker_entries_barrier_11_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_hr_array_hi_hi_hi_1; // @[package.scala:45:27] assign pma_checker_hr_array_hi_hi_hi_1 = _GEN_19; // @[package.scala:45:27] wire [1:0] pma_checker_hx_array_hi_hi_hi; // @[package.scala:45:27] assign pma_checker_hx_array_hi_hi_hi = _GEN_19; // @[package.scala:45:27] wire [3:0] pma_checker_hr_array_hi_hi_1 = {pma_checker_hr_array_hi_hi_hi_1, pma_checker_hr_array_hi_hi_lo_1}; // @[package.scala:45:27] wire [6:0] pma_checker_hr_array_hi_1 = {pma_checker_hr_array_hi_hi_1, pma_checker_hr_array_hi_lo_1}; // @[package.scala:45:27] wire [12:0] pma_checker__hr_array_T_1 = {pma_checker_hr_array_hi_1, pma_checker_hr_array_lo_1}; // @[package.scala:45:27] wire [1:0] pma_checker_hw_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_hw, _pma_checker_entries_barrier_1_io_y_hw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_hw_array_lo_lo = {pma_checker_hw_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_hw}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_hw_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_hw, _pma_checker_entries_barrier_4_io_y_hw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_hw_array_lo_hi = {pma_checker_hw_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_hw}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_hw_array_lo = {pma_checker_hw_array_lo_hi, pma_checker_hw_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_hw_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_hw, _pma_checker_entries_barrier_7_io_y_hw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_hw_array_hi_lo = {pma_checker_hw_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_hw}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_hw_array_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_hw, _pma_checker_entries_barrier_9_io_y_hw}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_hw_array_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_hw, _pma_checker_entries_barrier_11_io_y_hw}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_hw_array_hi_hi = {pma_checker_hw_array_hi_hi_hi, pma_checker_hw_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_hw_array_hi = {pma_checker_hw_array_hi_hi, pma_checker_hw_array_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__hw_array_T = {pma_checker_hw_array_hi, pma_checker_hw_array_lo}; // @[package.scala:45:27] wire [2:0] pma_checker_hx_array_lo_lo = {pma_checker_hx_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_hx}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_hx_array_lo_hi = {pma_checker_hx_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_hx}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_hx_array_lo = {pma_checker_hx_array_lo_hi, pma_checker_hx_array_lo_lo}; // @[package.scala:45:27] wire [2:0] pma_checker_hx_array_hi_lo = {pma_checker_hx_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_hx}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_hx_array_hi_hi = {pma_checker_hx_array_hi_hi_hi, pma_checker_hx_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_hx_array_hi = {pma_checker_hx_array_hi_hi, pma_checker_hx_array_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__hx_array_T = {pma_checker_hx_array_hi, pma_checker_hx_array_lo}; // @[package.scala:45:27] wire [1:0] pma_checker__pr_array_T = {2{pma_checker_prot_r}}; // @[TLB.scala:429:55, :529:26] wire [1:0] pma_checker_pr_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_pr, _pma_checker_entries_barrier_1_io_y_pr}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pr_array_lo_lo = {pma_checker_pr_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_pr}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_pr_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_pr, _pma_checker_entries_barrier_4_io_y_pr}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pr_array_lo_hi = {pma_checker_pr_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_pr}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_pr_array_lo = {pma_checker_pr_array_lo_hi, pma_checker_pr_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_pr_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_pr, _pma_checker_entries_barrier_7_io_y_pr}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pr_array_hi_lo = {pma_checker_pr_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_pr}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_pr_array_hi_hi_hi = {_pma_checker_entries_barrier_11_io_y_pr, _pma_checker_entries_barrier_10_io_y_pr}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pr_array_hi_hi = {pma_checker_pr_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_pr}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_pr_array_hi = {pma_checker_pr_array_hi_hi, pma_checker_pr_array_hi_lo}; // @[package.scala:45:27] wire [11:0] pma_checker__pr_array_T_1 = {pma_checker_pr_array_hi, pma_checker_pr_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker__pr_array_T_2 = {pma_checker__pr_array_T, pma_checker__pr_array_T_1}; // @[package.scala:45:27] wire [13:0] _GEN_20 = pma_checker_ptw_ae_array \| pma_checker_final_ae_array; // @[TLB.scala:506:25, :507:27, :529:104] wire [13:0] pma_checker__pr_array_T_3; // @[TLB.scala:529:104] assign pma_checker__pr_array_T_3 = _GEN_20; // @[TLB.scala:529:104] wire [13:0] pma_checker__pw_array_T_3; // @[TLB.scala:531:104] assign pma_checker__pw_array_T_3 = _GEN_20; // @[TLB.scala:529:104, :531:104] wire [13:0] pma_checker__px_array_T_3; // @[TLB.scala:533:104] assign pma_checker__px_array_T_3 = _GEN_20; // @[TLB.scala:529:104, :533:104] wire [13:0] pma_checker__pr_array_T_4 = ~pma_checker__pr_array_T_3; // @[TLB.scala:529:{89,104}] wire [13:0] pma_checker_pr_array = pma_checker__pr_array_T_2 & pma_checker__pr_array_T_4; // @[TLB.scala:529:{21,87,89}] wire [1:0] pma_checker__pw_array_T = {2{pma_checker_prot_w}}; // @[TLB.scala:430:55, :531:26] wire [1:0] pma_checker_pw_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_pw, _pma_checker_entries_barrier_1_io_y_pw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pw_array_lo_lo = {pma_checker_pw_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_pw}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_pw_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_pw, _pma_checker_entries_barrier_4_io_y_pw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pw_array_lo_hi = {pma_checker_pw_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_pw}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_pw_array_lo = {pma_checker_pw_array_lo_hi, pma_checker_pw_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_pw_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_pw, _pma_checker_entries_barrier_7_io_y_pw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pw_array_hi_lo = {pma_checker_pw_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_pw}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_pw_array_hi_hi_hi = {_pma_checker_entries_barrier_11_io_y_pw, _pma_checker_entries_barrier_10_io_y_pw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pw_array_hi_hi = {pma_checker_pw_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_pw}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_pw_array_hi = {pma_checker_pw_array_hi_hi, pma_checker_pw_array_hi_lo}; // @[package.scala:45:27] wire [11:0] pma_checker__pw_array_T_1 = {pma_checker_pw_array_hi, pma_checker_pw_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker__pw_array_T_2 = {pma_checker__pw_array_T, pma_checker__pw_array_T_1}; // @[package.scala:45:27] wire [13:0] pma_checker__pw_array_T_4 = ~pma_checker__pw_array_T_3; // @[TLB.scala:531:{89,104}] wire [13:0] pma_checker_pw_array = pma_checker__pw_array_T_2 & pma_checker__pw_array_T_4; // @[TLB.scala:531:{21,87,89}] wire [1:0] pma_checker__px_array_T = {2{pma_checker_prot_x}}; // @[TLB.scala:434:55, :533:26] wire [1:0] pma_checker_px_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_px, _pma_checker_entries_barrier_1_io_y_px}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_px_array_lo_lo = {pma_checker_px_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_px}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_px_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_px, _pma_checker_entries_barrier_4_io_y_px}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_px_array_lo_hi = {pma_checker_px_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_px}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_px_array_lo = {pma_checker_px_array_lo_hi, pma_checker_px_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_px_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_px, _pma_checker_entries_barrier_7_io_y_px}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_px_array_hi_lo = {pma_checker_px_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_px}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_px_array_hi_hi_hi = {_pma_checker_entries_barrier_11_io_y_px, _pma_checker_entries_barrier_10_io_y_px}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_px_array_hi_hi = {pma_checker_px_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_px}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_px_array_hi = {pma_checker_px_array_hi_hi, pma_checker_px_array_hi_lo}; // @[package.scala:45:27] wire [11:0] pma_checker__px_array_T_1 = {pma_checker_px_array_hi, pma_checker_px_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker__px_array_T_2 = {pma_checker__px_array_T, pma_checker__px_array_T_1}; // @[package.scala:45:27] wire [13:0] pma_checker__px_array_T_4 = ~pma_checker__px_array_T_3; // @[TLB.scala:533:{89,104}] wire [13:0] pma_checker_px_array = pma_checker__px_array_T_2 & pma_checker__px_array_T_4; // @[TLB.scala:533:{21,87,89}] wire [1:0] pma_checker__eff_array_T = {2{_pma_checker_pma_io_resp_eff}}; // @[TLB.scala:422:19, :535:27] wire [1:0] pma_checker_eff_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_eff, _pma_checker_entries_barrier_1_io_y_eff}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_eff_array_lo_lo = {pma_checker_eff_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_eff}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_eff_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_eff, _pma_checker_entries_barrier_4_io_y_eff}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_eff_array_lo_hi = {pma_checker_eff_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_eff}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_eff_array_lo = {pma_checker_eff_array_lo_hi, pma_checker_eff_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_eff_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_eff, _pma_checker_entries_barrier_7_io_y_eff}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_eff_array_hi_lo = {pma_checker_eff_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_eff}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_eff_array_hi_hi_hi = {_pma_checker_entries_barrier_11_io_y_eff, _pma_checker_entries_barrier_10_io_y_eff}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_eff_array_hi_hi = {pma_checker_eff_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_eff}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_eff_array_hi = {pma_checker_eff_array_hi_hi, pma_checker_eff_array_hi_lo}; // @[package.scala:45:27] wire [11:0] pma_checker__eff_array_T_1 = {pma_checker_eff_array_hi, pma_checker_eff_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker_eff_array = {pma_checker__eff_array_T, pma_checker__eff_array_T_1}; // @[package.scala:45:27] wire [1:0] _GEN_21 = {_pma_checker_entries_barrier_2_io_y_c, _pma_checker_entries_barrier_1_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_c_array_lo_lo_hi; // @[package.scala:45:27] assign pma_checker_c_array_lo_lo_hi = _GEN_21; // @[package.scala:45:27] wire [1:0] pma_checker_prefetchable_array_lo_lo_hi; // @[package.scala:45:27] assign pma_checker_prefetchable_array_lo_lo_hi = _GEN_21; // @[package.scala:45:27] wire [2:0] pma_checker_c_array_lo_lo = {pma_checker_c_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_22 = {_pma_checker_entries_barrier_5_io_y_c, _pma_checker_entries_barrier_4_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_c_array_lo_hi_hi; // @[package.scala:45:27] assign pma_checker_c_array_lo_hi_hi = _GEN_22; // @[package.scala:45:27] wire [1:0] pma_checker_prefetchable_array_lo_hi_hi; // @[package.scala:45:27] assign pma_checker_prefetchable_array_lo_hi_hi = _GEN_22; // @[package.scala:45:27] wire [2:0] pma_checker_c_array_lo_hi = {pma_checker_c_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_c}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_c_array_lo = {pma_checker_c_array_lo_hi, pma_checker_c_array_lo_lo}; // @[package.scala:45:27] wire [1:0] _GEN_23 = {_pma_checker_entries_barrier_8_io_y_c, _pma_checker_entries_barrier_7_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_c_array_hi_lo_hi; // @[package.scala:45:27] assign pma_checker_c_array_hi_lo_hi = _GEN_23; // @[package.scala:45:27] wire [1:0] pma_checker_prefetchable_array_hi_lo_hi; // @[package.scala:45:27] assign pma_checker_prefetchable_array_hi_lo_hi = _GEN_23; // @[package.scala:45:27] wire [2:0] pma_checker_c_array_hi_lo = {pma_checker_c_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_24 = {_pma_checker_entries_barrier_11_io_y_c, _pma_checker_entries_barrier_10_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_c_array_hi_hi_hi; // @[package.scala:45:27] assign pma_checker_c_array_hi_hi_hi = _GEN_24; // @[package.scala:45:27] wire [1:0] pma_checker_prefetchable_array_hi_hi_hi; // @[package.scala:45:27] assign pma_checker_prefetchable_array_hi_hi_hi = _GEN_24; // @[package.scala:45:27] wire [2:0] pma_checker_c_array_hi_hi = {pma_checker_c_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_c}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_c_array_hi = {pma_checker_c_array_hi_hi, pma_checker_c_array_hi_lo}; // @[package.scala:45:27] wire [11:0] pma_checker__c_array_T_1 = {pma_checker_c_array_hi, pma_checker_c_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker_c_array = {2'h0, pma_checker__c_array_T_1}; // @[package.scala:45:27] wire [1:0] pma_checker__ppp_array_T = {2{_pma_checker_pma_io_resp_pp}}; // @[TLB.scala:422:19, :539:27] wire [1:0] pma_checker_ppp_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_ppp, _pma_checker_entries_barrier_1_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ppp_array_lo_lo = {pma_checker_ppp_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_ppp_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_ppp, _pma_checker_entries_barrier_4_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ppp_array_lo_hi = {pma_checker_ppp_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_ppp_array_lo = {pma_checker_ppp_array_lo_hi, pma_checker_ppp_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_ppp_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_ppp, _pma_checker_entries_barrier_7_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ppp_array_hi_lo = {pma_checker_ppp_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_ppp_array_hi_hi_hi = {_pma_checker_entries_barrier_11_io_y_ppp, _pma_checker_entries_barrier_10_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ppp_array_hi_hi = {pma_checker_ppp_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_ppp_array_hi = {pma_checker_ppp_array_hi_hi, pma_checker_ppp_array_hi_lo}; // @[package.scala:45:27] wire [11:0] pma_checker__ppp_array_T_1 = {pma_checker_ppp_array_hi, pma_checker_ppp_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker_ppp_array = {pma_checker__ppp_array_T, pma_checker__ppp_array_T_1}; // @[package.scala:45:27] wire [1:0] pma_checker__paa_array_T = {2{_pma_checker_pma_io_resp_aa}}; // @[TLB.scala:422:19, :541:27] wire [1:0] pma_checker_paa_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_paa, _pma_checker_entries_barrier_1_io_y_paa}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_paa_array_lo_lo = {pma_checker_paa_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_paa}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_paa_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_paa, _pma_checker_entries_barrier_4_io_y_paa}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_paa_array_lo_hi = {pma_checker_paa_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_paa}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_paa_array_lo = {pma_checker_paa_array_lo_hi, pma_checker_paa_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_paa_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_paa, _pma_checker_entries_barrier_7_io_y_paa}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_paa_array_hi_lo = {pma_checker_paa_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_paa}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_paa_array_hi_hi_hi = {_pma_checker_entries_barrier_11_io_y_paa, _pma_checker_entries_barrier_10_io_y_paa}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_paa_array_hi_hi = {pma_checker_paa_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_paa}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_paa_array_hi = {pma_checker_paa_array_hi_hi, pma_checker_paa_array_hi_lo}; // @[package.scala:45:27] wire [11:0] pma_checker__paa_array_T_1 = {pma_checker_paa_array_hi, pma_checker_paa_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker_paa_array = {pma_checker__paa_array_T, pma_checker__paa_array_T_1}; // @[package.scala:45:27] wire [1:0] pma_checker__pal_array_T = {2{_pma_checker_pma_io_resp_al}}; // @[TLB.scala:422:19, :543:27] wire [1:0] pma_checker_pal_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_pal, _pma_checker_entries_barrier_1_io_y_pal}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pal_array_lo_lo = {pma_checker_pal_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_pal}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_pal_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_pal, _pma_checker_entries_barrier_4_io_y_pal}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pal_array_lo_hi = {pma_checker_pal_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_pal}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_pal_array_lo = {pma_checker_pal_array_lo_hi, pma_checker_pal_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_pal_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_pal, _pma_checker_entries_barrier_7_io_y_pal}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pal_array_hi_lo = {pma_checker_pal_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_pal}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_pal_array_hi_hi_hi = {_pma_checker_entries_barrier_11_io_y_pal, _pma_checker_entries_barrier_10_io_y_pal}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pal_array_hi_hi = {pma_checker_pal_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_pal}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_pal_array_hi = {pma_checker_pal_array_hi_hi, pma_checker_pal_array_hi_lo}; // @[package.scala:45:27] wire [11:0] pma_checker__pal_array_T_1 = {pma_checker_pal_array_hi, pma_checker_pal_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker_pal_array = {pma_checker__pal_array_T, pma_checker__pal_array_T_1}; // @[package.scala:45:27] wire [13:0] pma_checker_ppp_array_if_cached = pma_checker_ppp_array \| pma_checker_c_array; // @[TLB.scala:537:20, :539:22, :544:39] wire [13:0] pma_checker_paa_array_if_cached = pma_checker_paa_array \| pma_checker_c_array; // @[TLB.scala:537:20, :541:22, :545:39] wire [13:0] pma_checker_pal_array_if_cached = pma_checker_pal_array \| pma_checker_c_array; // @[TLB.scala:537:20, :543:22, :546:39] wire [2:0] pma_checker_prefetchable_array_lo_lo = {pma_checker_prefetchable_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_c}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_prefetchable_array_lo_hi = {pma_checker_prefetchable_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_c}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_prefetchable_array_lo = {pma_checker_prefetchable_array_lo_hi, pma_checker_prefetchable_array_lo_lo}; // @[package.scala:45:27] wire [2:0] pma_checker_prefetchable_array_hi_lo = {pma_checker_prefetchable_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_c}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_prefetchable_array_hi_hi = {pma_checker_prefetchable_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_c}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_prefetchable_array_hi = {pma_checker_prefetchable_array_hi_hi, pma_checker_prefetchable_array_hi_lo}; // @[package.scala:45:27] wire [11:0] pma_checker__prefetchable_array_T_2 = {pma_checker_prefetchable_array_hi, pma_checker_prefetchable_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker_prefetchable_array = {2'h0, pma_checker__prefetchable_array_T_2}; // @[package.scala:45:27] wire [3:0] pma_checker__misaligned_T = 4'h1 << pma_checker_io_req_bits_size; // @[OneHot.scala:58:35] wire [4:0] pma_checker__misaligned_T_1 = {1'h0, pma_checker__misaligned_T} - 5'h1; // @[OneHot.scala:58:35] wire [3:0] pma_checker__misaligned_T_2 = pma_checker__misaligned_T_1[3:0]; // @[TLB.scala:550:69] wire [33:0] pma_checker__misaligned_T_3 = {30'h0, pma_checker_io_req_bits_vaddr[3:0] & pma_checker__misaligned_T_2}; // @[TLB.scala:550:{39,69}] wire pma_checker_misaligned = \|pma_checker__misaligned_T_3; // @[TLB.scala:550:{39,77}] wire _GEN_25 = pma_checker_io_req_bits_cmd == 5'h6; // @[package.scala:16:47] wire pma_checker__cmd_lrsc_T; // @[package.scala:16:47] assign pma_checker__cmd_lrsc_T = _GEN_25; // @[package.scala:16:47] wire pma_checker__cmd_read_T_2; // @[package.scala:16:47] assign pma_checker__cmd_read_T_2 = _GEN_25; // @[package.scala:16:47] wire _GEN_26 = pma_checker_io_req_bits_cmd == 5'h7; // @[package.scala:16:47] wire pma_checker__cmd_lrsc_T_1; // @[package.scala:16:47] assign pma_checker__cmd_lrsc_T_1 = _GEN_26; // @[package.scala:16:47] wire pma_checker__cmd_read_T_3; // @[package.scala:16:47] assign pma_checker__cmd_read_T_3 = _GEN_26; // @[package.scala:16:47] wire pma_checker__cmd_write_T_3; // @[Consts.scala:90:66] assign pma_checker__cmd_write_T_3 = _GEN_26; // @[package.scala:16:47] wire pma_checker__cmd_lrsc_T_2 = pma_checker__cmd_lrsc_T \| pma_checker__cmd_lrsc_T_1; // @[package.scala:16:47, :81:59] wire pma_checker_cmd_lrsc = pma_checker__cmd_lrsc_T_2; // @[package.scala:81:59] wire _GEN_27 = pma_checker_io_req_bits_cmd == 5'h4; // @[package.scala:16:47] wire pma_checker__cmd_amo_logical_T; // @[package.scala:16:47] assign pma_checker__cmd_amo_logical_T = _GEN_27; // @[package.scala:16:47] wire pma_checker__cmd_read_T_7; // @[package.scala:16:47] assign pma_checker__cmd_read_T_7 = _GEN_27; // @[package.scala:16:47] wire pma_checker__cmd_write_T_5; // @[package.scala:16:47] assign pma_checker__cmd_write_T_5 = _GEN_27; // @[package.scala:16:47] wire _GEN_28 = pma_checker_io_req_bits_cmd == 5'h9; // @[package.scala:16:47] wire pma_checker__cmd_amo_logical_T_1; // @[package.scala:16:47] assign pma_checker__cmd_amo_logical_T_1 = _GEN_28; // @[package.scala:16:47] wire pma_checker__cmd_read_T_8; // @[package.scala:16:47] assign pma_checker__cmd_read_T_8 = _GEN_28; // @[package.scala:16:47] wire pma_checker__cmd_write_T_6; // @[package.scala:16:47] assign pma_checker__cmd_write_T_6 = _GEN_28; // @[package.scala:16:47] wire _GEN_29 = pma_checker_io_req_bits_cmd == 5'hA; // @[package.scala:16:47] wire pma_checker__cmd_amo_logical_T_2; // @[package.scala:16:47] assign pma_checker__cmd_amo_logical_T_2 = _GEN_29; // @[package.scala:16:47] wire pma_checker__cmd_read_T_9; // @[package.scala:16:47] assign pma_checker__cmd_read_T_9 = _GEN_29; // @[package.scala:16:47] wire pma_checker__cmd_write_T_7; // @[package.scala:16:47] assign pma_checker__cmd_write_T_7 = _GEN_29; // @[package.scala:16:47] wire _GEN_30 = pma_checker_io_req_bits_cmd == 5'hB; // @[package.scala:16:47] wire pma_checker__cmd_amo_logical_T_3; // @[package.scala:16:47] assign pma_checker__cmd_amo_logical_T_3 = _GEN_30; // @[package.scala:16:47] wire pma_checker__cmd_read_T_10; // @[package.scala:16:47] assign pma_checker__cmd_read_T_10 = _GEN_30; // @[package.scala:16:47] wire pma_checker__cmd_write_T_8; // @[package.scala:16:47] assign pma_checker__cmd_write_T_8 = _GEN_30; // @[package.scala:16:47] wire pma_checker__cmd_amo_logical_T_4 = pma_checker__cmd_amo_logical_T \| pma_checker__cmd_amo_logical_T_1; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_amo_logical_T_5 = pma_checker__cmd_amo_logical_T_4 \| pma_checker__cmd_amo_logical_T_2; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_amo_logical_T_6 = pma_checker__cmd_amo_logical_T_5 \| pma_checker__cmd_amo_logical_T_3; // @[package.scala:16:47, :81:59] wire pma_checker_cmd_amo_logical = pma_checker__cmd_amo_logical_T_6; // @[package.scala:81:59] wire _GEN_31 = pma_checker_io_req_bits_cmd == 5'h8; // @[package.scala:16:47] wire pma_checker__cmd_amo_arithmetic_T; // @[package.scala:16:47] assign pma_checker__cmd_amo_arithmetic_T = _GEN_31; // @[package.scala:16:47] wire pma_checker__cmd_read_T_14; // @[package.scala:16:47] assign pma_checker__cmd_read_T_14 = _GEN_31; // @[package.scala:16:47] wire pma_checker__cmd_write_T_12; // @[package.scala:16:47] assign pma_checker__cmd_write_T_12 = _GEN_31; // @[package.scala:16:47] wire _GEN_32 = pma_checker_io_req_bits_cmd == 5'hC; // @[package.scala:16:47] wire pma_checker__cmd_amo_arithmetic_T_1; // @[package.scala:16:47] assign pma_checker__cmd_amo_arithmetic_T_1 = _GEN_32; // @[package.scala:16:47] wire pma_checker__cmd_read_T_15; // @[package.scala:16:47] assign pma_checker__cmd_read_T_15 = _GEN_32; // @[package.scala:16:47] wire pma_checker__cmd_write_T_13; // @[package.scala:16:47] assign pma_checker__cmd_write_T_13 = _GEN_32; // @[package.scala:16:47] wire _GEN_33 = pma_checker_io_req_bits_cmd == 5'hD; // @[package.scala:16:47] wire pma_checker__cmd_amo_arithmetic_T_2; // @[package.scala:16:47] assign pma_checker__cmd_amo_arithmetic_T_2 = _GEN_33; // @[package.scala:16:47] wire pma_checker__cmd_read_T_16; // @[package.scala:16:47] assign pma_checker__cmd_read_T_16 = _GEN_33; // @[package.scala:16:47] wire pma_checker__cmd_write_T_14; // @[package.scala:16:47] assign pma_checker__cmd_write_T_14 = _GEN_33; // @[package.scala:16:47] wire _GEN_34 = pma_checker_io_req_bits_cmd == 5'hE; // @[package.scala:16:47] wire pma_checker__cmd_amo_arithmetic_T_3; // @[package.scala:16:47] assign pma_checker__cmd_amo_arithmetic_T_3 = _GEN_34; // @[package.scala:16:47] wire pma_checker__cmd_read_T_17; // @[package.scala:16:47] assign pma_checker__cmd_read_T_17 = _GEN_34; // @[package.scala:16:47] wire pma_checker__cmd_write_T_15; // @[package.scala:16:47] assign pma_checker__cmd_write_T_15 = _GEN_34; // @[package.scala:16:47] wire _GEN_35 = pma_checker_io_req_bits_cmd == 5'hF; // @[package.scala:16:47] wire pma_checker__cmd_amo_arithmetic_T_4; // @[package.scala:16:47] assign pma_checker__cmd_amo_arithmetic_T_4 = _GEN_35; // @[package.scala:16:47] wire pma_checker__cmd_read_T_18; // @[package.scala:16:47] assign pma_checker__cmd_read_T_18 = _GEN_35; // @[package.scala:16:47] wire pma_checker__cmd_write_T_16; // @[package.scala:16:47] assign pma_checker__cmd_write_T_16 = _GEN_35; // @[package.scala:16:47] wire pma_checker__cmd_amo_arithmetic_T_5 = pma_checker__cmd_amo_arithmetic_T \| pma_checker__cmd_amo_arithmetic_T_1; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_amo_arithmetic_T_6 = pma_checker__cmd_amo_arithmetic_T_5 \| pma_checker__cmd_amo_arithmetic_T_2; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_amo_arithmetic_T_7 = pma_checker__cmd_amo_arithmetic_T_6 \| pma_checker__cmd_amo_arithmetic_T_3; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_amo_arithmetic_T_8 = pma_checker__cmd_amo_arithmetic_T_7 \| pma_checker__cmd_amo_arithmetic_T_4; // @[package.scala:16:47, :81:59] wire pma_checker_cmd_amo_arithmetic = pma_checker__cmd_amo_arithmetic_T_8; // @[package.scala:81:59] wire _GEN_36 = pma_checker_io_req_bits_cmd == 5'h11; // @[TLB.scala:573:41] wire pma_checker_cmd_put_partial; // @[TLB.scala:573:41] assign pma_checker_cmd_put_partial = _GEN_36; // @[TLB.scala:573:41] wire pma_checker__cmd_write_T_1; // @[Consts.scala:90:49] assign pma_checker__cmd_write_T_1 = _GEN_36; // @[TLB.scala:573:41] wire pma_checker__cmd_read_T = pma_checker_io_req_bits_cmd == 5'h0; // @[package.scala:16:47] wire _GEN_37 = pma_checker_io_req_bits_cmd == 5'h10; // @[package.scala:16:47] wire pma_checker__cmd_read_T_1; // @[package.scala:16:47] assign pma_checker__cmd_read_T_1 = _GEN_37; // @[package.scala:16:47] wire pma_checker__cmd_readx_T; // @[TLB.scala:575:56] assign pma_checker__cmd_readx_T = _GEN_37; // @[package.scala:16:47] wire pma_checker__cmd_read_T_4 = pma_checker__cmd_read_T \| pma_checker__cmd_read_T_1; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_read_T_5 = pma_checker__cmd_read_T_4 \| pma_checker__cmd_read_T_2; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_read_T_6 = pma_checker__cmd_read_T_5 \| pma_checker__cmd_read_T_3; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_read_T_11 = pma_checker__cmd_read_T_7 \| pma_checker__cmd_read_T_8; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_read_T_12 = pma_checker__cmd_read_T_11 \| pma_checker__cmd_read_T_9; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_read_T_13 = pma_checker__cmd_read_T_12 \| pma_checker__cmd_read_T_10; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_read_T_19 = pma_checker__cmd_read_T_14 \| pma_checker__cmd_read_T_15; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_read_T_20 = pma_checker__cmd_read_T_19 \| pma_checker__cmd_read_T_16; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_read_T_21 = pma_checker__cmd_read_T_20 \| pma_checker__cmd_read_T_17; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_read_T_22 = pma_checker__cmd_read_T_21 \| pma_checker__cmd_read_T_18; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_read_T_23 = pma_checker__cmd_read_T_13 \| pma_checker__cmd_read_T_22; // @[package.scala:81:59] wire pma_checker_cmd_read = pma_checker__cmd_read_T_6 \| pma_checker__cmd_read_T_23; // @[package.scala:81:59] wire pma_checker__cmd_write_T = pma_checker_io_req_bits_cmd == 5'h1; // @[DCache.scala:120:32] wire pma_checker__cmd_write_T_2 = pma_checker__cmd_write_T \| pma_checker__cmd_write_T_1; // @[Consts.scala:90:{32,42,49}] wire pma_checker__cmd_write_T_4 = pma_checker__cmd_write_T_2 \| pma_checker__cmd_write_T_3; // @[Consts.scala:90:{42,59,66}] wire pma_checker__cmd_write_T_9 = pma_checker__cmd_write_T_5 \| pma_checker__cmd_write_T_6; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_write_T_10 = pma_checker__cmd_write_T_9 \| pma_checker__cmd_write_T_7; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_write_T_11 = pma_checker__cmd_write_T_10 \| pma_checker__cmd_write_T_8; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_write_T_17 = pma_checker__cmd_write_T_12 \| pma_checker__cmd_write_T_13; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_write_T_18 = pma_checker__cmd_write_T_17 \| pma_checker__cmd_write_T_14; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_write_T_19 = pma_checker__cmd_write_T_18 \| pma_checker__cmd_write_T_15; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_write_T_20 = pma_checker__cmd_write_T_19 \| pma_checker__cmd_write_T_16; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_write_T_21 = pma_checker__cmd_write_T_11 \| pma_checker__cmd_write_T_20; // @[package.scala:81:59] wire pma_checker_cmd_write = pma_checker__cmd_write_T_4 \| pma_checker__cmd_write_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire pma_checker__cmd_write_perms_T = pma_checker_io_req_bits_cmd == 5'h5; // @[package.scala:16:47] wire pma_checker__cmd_write_perms_T_1 = pma_checker_io_req_bits_cmd == 5'h17; // @[package.scala:16:47] wire pma_checker__cmd_write_perms_T_2 = pma_checker__cmd_write_perms_T \| pma_checker__cmd_write_perms_T_1; // @[package.scala:16:47, :81:59] wire pma_checker_cmd_write_perms = pma_checker_cmd_write \| pma_checker__cmd_write_perms_T_2; // @[package.scala:81:59] wire [13:0] pma_checker__ae_array_T = pma_checker_misaligned ? pma_checker_eff_array : 14'h0; // @[TLB.scala:535:22, :550:77, :582:8] wire [13:0] _GEN_38 = {14{pma_checker_cmd_lrsc}}; // @[TLB.scala:570:33, :583:8] wire [13:0] pma_checker__ae_array_T_2; // @[TLB.scala:583:8] assign pma_checker__ae_array_T_2 = _GEN_38; // @[TLB.scala:583:8] wire [13:0] pma_checker__must_alloc_array_T_9; // @[TLB.scala:596:8] assign pma_checker__must_alloc_array_T_9 = _GEN_38; // @[TLB.scala:583:8, :596:8] wire [13:0] pma_checker_ae_array = pma_checker__ae_array_T \| pma_checker__ae_array_T_2; // @[TLB.scala:582:{8,37}, :583:8] wire [13:0] pma_checker__ae_ld_array_T = ~pma_checker_pr_array; // @[TLB.scala:529:87, :586:46] wire [13:0] pma_checker__ae_ld_array_T_1 = pma_checker_ae_array \| pma_checker__ae_ld_array_T; // @[TLB.scala:582:37, :586:{44,46}] wire [13:0] pma_checker_ae_ld_array = pma_checker_cmd_read ? pma_checker__ae_ld_array_T_1 : 14'h0; // @[TLB.scala:586:{24,44}] wire [13:0] pma_checker__ae_st_array_T = ~pma_checker_pw_array; // @[TLB.scala:531:87, :588:37] wire [13:0] pma_checker__ae_st_array_T_1 = pma_checker_ae_array \| pma_checker__ae_st_array_T; // @[TLB.scala:582:37, :588:{35,37}] wire [13:0] pma_checker__ae_st_array_T_2 = pma_checker_cmd_write_perms ? pma_checker__ae_st_array_T_1 : 14'h0; // @[TLB.scala:577:35, :588:{8,35}] wire [13:0] pma_checker__ae_st_array_T_3 = ~pma_checker_ppp_array_if_cached; // @[TLB.scala:544:39, :589:26] wire [13:0] pma_checker__ae_st_array_T_4 = pma_checker_cmd_put_partial ? pma_checker__ae_st_array_T_3 : 14'h0; // @[TLB.scala:573:41, :589:{8,26}] wire [13:0] pma_checker__ae_st_array_T_5 = pma_checker__ae_st_array_T_2 \| pma_checker__ae_st_array_T_4; // @[TLB.scala:588:{8,53}, :589:8] wire [13:0] pma_checker__ae_st_array_T_6 = ~pma_checker_pal_array_if_cached; // @[TLB.scala:546:39, :590:26] wire [13:0] pma_checker__ae_st_array_T_7 = pma_checker_cmd_amo_logical ? pma_checker__ae_st_array_T_6 : 14'h0; // @[TLB.scala:571:40, :590:{8,26}] wire [13:0] pma_checker__ae_st_array_T_8 = pma_checker__ae_st_array_T_5 \| pma_checker__ae_st_array_T_7; // @[TLB.scala:588:53, :589:53, :590:8] wire [13:0] pma_checker__ae_st_array_T_9 = ~pma_checker_paa_array_if_cached; // @[TLB.scala:545:39, :591:29] wire [13:0] pma_checker__ae_st_array_T_10 = pma_checker_cmd_amo_arithmetic ? pma_checker__ae_st_array_T_9 : 14'h0; // @[TLB.scala:572:43, :591:{8,29}] wire [13:0] pma_checker_ae_st_array = pma_checker__ae_st_array_T_8 \| pma_checker__ae_st_array_T_10; // @[TLB.scala:589:53, :590:53, :591:8] wire [13:0] pma_checker__must_alloc_array_T = ~pma_checker_ppp_array; // @[TLB.scala:539:22, :593:26] wire [13:0] pma_checker__must_alloc_array_T_1 = pma_checker_cmd_put_partial ? pma_checker__must_alloc_array_T : 14'h0; // @[TLB.scala:573:41, :593:{8,26}] wire [13:0] pma_checker__must_alloc_array_T_2 = ~pma_checker_pal_array; // @[TLB.scala:543:22, :594:26] wire [13:0] pma_checker__must_alloc_array_T_3 = pma_checker_cmd_amo_logical ? pma_checker__must_alloc_array_T_2 : 14'h0; // @[TLB.scala:571:40, :594:{8,26}] wire [13:0] pma_checker__must_alloc_array_T_4 = pma_checker__must_alloc_array_T_1 \| pma_checker__must_alloc_array_T_3; // @[TLB.scala:593:{8,43}, :594:8] wire [13:0] pma_checker__must_alloc_array_T_5 = ~pma_checker_paa_array; // @[TLB.scala:541:22, :595:29] wire [13:0] pma_checker__must_alloc_array_T_6 = pma_checker_cmd_amo_arithmetic ? pma_checker__must_alloc_array_T_5 : 14'h0; // @[TLB.scala:572:43, :595:{8,29}] wire [13:0] pma_checker__must_alloc_array_T_7 = pma_checker__must_alloc_array_T_4 \| pma_checker__must_alloc_array_T_6; // @[TLB.scala:593:43, :594:43, :595:8] wire [13:0] pma_checker_must_alloc_array = pma_checker__must_alloc_array_T_7 \| pma_checker__must_alloc_array_T_9; // @[TLB.scala:594:43, :595:46, :596:8] wire [13:0] pma_checker__pf_ld_array_T_1 = ~pma_checker__pf_ld_array_T; // @[TLB.scala:597:{37,41}] wire [13:0] pma_checker__pf_ld_array_T_2 = ~pma_checker_ptw_ae_array; // @[TLB.scala:506:25, :597:73] wire [13:0] pma_checker__pf_ld_array_T_3 = pma_checker__pf_ld_array_T_1 & pma_checker__pf_ld_array_T_2; // @[TLB.scala:597:{37,71,73}] wire [13:0] pma_checker__pf_ld_array_T_4 = pma_checker__pf_ld_array_T_3 \| pma_checker_ptw_pf_array; // @[TLB.scala:508:25, :597:{71,88}] wire [13:0] pma_checker__pf_ld_array_T_5 = ~pma_checker_ptw_gf_array; // @[TLB.scala:509:25, :597:106] wire [13:0] pma_checker__pf_ld_array_T_6 = pma_checker__pf_ld_array_T_4 & pma_checker__pf_ld_array_T_5; // @[TLB.scala:597:{88,104,106}] wire [13:0] pma_checker_pf_ld_array = pma_checker_cmd_read ? pma_checker__pf_ld_array_T_6 : 14'h0; // @[TLB.scala:597:{24,104}] wire [13:0] pma_checker__pf_st_array_T = ~pma_checker_w_array; // @[TLB.scala:521:20, :598:44] wire [13:0] pma_checker__pf_st_array_T_1 = ~pma_checker_ptw_ae_array; // @[TLB.scala:506:25, :597:73, :598:55] wire [13:0] pma_checker__pf_st_array_T_2 = pma_checker__pf_st_array_T & pma_checker__pf_st_array_T_1; // @[TLB.scala:598:{44,53,55}] wire [13:0] pma_checker__pf_st_array_T_3 = pma_checker__pf_st_array_T_2 \| pma_checker_ptw_pf_array; // @[TLB.scala:508:25, :598:{53,70}] wire [13:0] pma_checker__pf_st_array_T_4 = ~pma_checker_ptw_gf_array; // @[TLB.scala:509:25, :597:106, :598:88] wire [13:0] pma_checker__pf_st_array_T_5 = pma_checker__pf_st_array_T_3 & pma_checker__pf_st_array_T_4; // @[TLB.scala:598:{70,86,88}] wire [13:0] pma_checker_pf_st_array = pma_checker_cmd_write_perms ? pma_checker__pf_st_array_T_5 : 14'h0; // @[TLB.scala:577:35, :598:{24,86}] wire [13:0] pma_checker__pf_inst_array_T = ~pma_checker_x_array; // @[TLB.scala:522:20, :599:25] wire [13:0] pma_checker__pf_inst_array_T_1 = ~pma_checker_ptw_ae_array; // @[TLB.scala:506:25, :597:73, :599:36] wire [13:0] pma_checker__pf_inst_array_T_2 = pma_checker__pf_inst_array_T & pma_checker__pf_inst_array_T_1; // @[TLB.scala:599:{25,34,36}] wire [13:0] pma_checker__pf_inst_array_T_3 = pma_checker__pf_inst_array_T_2 \| pma_checker_ptw_pf_array; // @[TLB.scala:508:25, :599:{34,51}] wire [13:0] pma_checker__pf_inst_array_T_4 = ~pma_checker_ptw_gf_array; // @[TLB.scala:509:25, :597:106, :599:69] wire [13:0] pma_checker_pf_inst_array = pma_checker__pf_inst_array_T_3 & pma_checker__pf_inst_array_T_4; // @[TLB.scala:599:{51,67,69}] wire [13:0] pma_checker__gf_ld_array_T_4 = ~pma_checker_ptw_ae_array; // @[TLB.scala:506:25, :597:73, :600:100] wire [13:0] pma_checker__gf_ld_array_T_5 = pma_checker__gf_ld_array_T_3 & pma_checker__gf_ld_array_T_4; // @[TLB.scala:600:{82,98,100}] wire [13:0] pma_checker__gf_st_array_T_3 = ~pma_checker_ptw_ae_array; // @[TLB.scala:506:25, :597:73, :601:81] wire [13:0] pma_checker__gf_st_array_T_4 = pma_checker__gf_st_array_T_2 & pma_checker__gf_st_array_T_3; // @[TLB.scala:601:{63,79,81}] wire [13:0] pma_checker__gf_inst_array_T_2 = ~pma_checker_ptw_ae_array; // @[TLB.scala:506:25, :597:73, :602:64] wire [13:0] pma_checker__gf_inst_array_T_3 = pma_checker__gf_inst_array_T_1 & pma_checker__gf_inst_array_T_2; // @[TLB.scala:602:{46,62,64}] wire pma_checker__gpa_hits_hit_mask_T = pma_checker_vpn == 21'h0; // @[TLB.scala:335:30, :606:73] wire [1:0] pma_checker_lo_lo = {pma_checker_sector_hits_1, pma_checker_sector_hits_0}; // @[OneHot.scala:21:45] wire [1:0] pma_checker_lo_hi = {pma_checker_sector_hits_3, pma_checker_sector_hits_2}; // @[OneHot.scala:21:45] wire [3:0] pma_checker_lo = {pma_checker_lo_hi, pma_checker_lo_lo}; // @[OneHot.scala:21:45] wire [3:0] pma_checker_lo_1 = pma_checker_lo; // @[OneHot.scala:21:45, :31:18] wire [1:0] pma_checker_hi_lo = {pma_checker_sector_hits_5, pma_checker_sector_hits_4}; // @[OneHot.scala:21:45] wire [1:0] pma_checker_hi_hi = {pma_checker_sector_hits_7, pma_checker_sector_hits_6}; // @[OneHot.scala:21:45] wire [3:0] pma_checker_hi = {pma_checker_hi_hi, pma_checker_hi_lo}; // @[OneHot.scala:21:45] wire [3:0] pma_checker_hi_1 = pma_checker_hi; // @[OneHot.scala:21:45, :30:18] wire [3:0] pma_checker__T_33 = pma_checker_hi_1 \| pma_checker_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] pma_checker_hi_2 = pma_checker__T_33[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] pma_checker_lo_2 = pma_checker__T_33[1:0]; // @[OneHot.scala:31:18, :32:28] wire [2:0] pma_checker_state_vec_0_touch_way_sized = {\|pma_checker_hi_1, \|pma_checker_hi_2, pma_checker_hi_2[1] \| pma_checker_lo_2[1]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}] wire pma_checker__state_vec_0_set_left_older_T = pma_checker_state_vec_0_touch_way_sized[2]; // @[package.scala:163:13] wire pma_checker_state_vec_0_set_left_older = ~pma_checker__state_vec_0_set_left_older_T; // @[Replacement.scala:196:{33,43}] wire [1:0] pma_checker__state_vec_0_T = pma_checker_state_vec_0_touch_way_sized[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker__state_vec_0_T_11 = pma_checker_state_vec_0_touch_way_sized[1:0]; // @[package.scala:163:13] wire pma_checker__state_vec_0_set_left_older_T_1 = pma_checker__state_vec_0_T[1]; // @[package.scala:163:13] wire pma_checker_state_vec_0_set_left_older_1 = ~pma_checker__state_vec_0_set_left_older_T_1; // @[Replacement.scala:196:{33,43}] wire pma_checker__state_vec_0_T_1 = pma_checker__state_vec_0_T[0]; // @[package.scala:163:13] wire pma_checker__state_vec_0_T_5 = pma_checker__state_vec_0_T[0]; // @[package.scala:163:13] wire pma_checker__state_vec_0_T_2 = pma_checker__state_vec_0_T_1; // @[package.scala:163:13] wire pma_checker__state_vec_0_T_3 = ~pma_checker__state_vec_0_T_2; // @[Replacement.scala:218:{7,17}] wire pma_checker__state_vec_0_T_4 = ~pma_checker_state_vec_0_set_left_older_1 & pma_checker__state_vec_0_T_3; // @[Replacement.scala:196:33, :203:16, :218:7] wire pma_checker__state_vec_0_T_6 = pma_checker__state_vec_0_T_5; // @[Replacement.scala:207:62, :218:17] wire pma_checker__state_vec_0_T_7 = ~pma_checker__state_vec_0_T_6; // @[Replacement.scala:218:{7,17}] wire pma_checker__state_vec_0_T_8 = pma_checker_state_vec_0_set_left_older_1 & pma_checker__state_vec_0_T_7; // @[Replacement.scala:196:33, :206:16, :218:7] wire [1:0] pma_checker_state_vec_0_hi = {pma_checker_state_vec_0_set_left_older_1, pma_checker__state_vec_0_T_4}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] pma_checker__state_vec_0_T_9 = {pma_checker_state_vec_0_hi, pma_checker__state_vec_0_T_8}; // @[Replacement.scala:202:12, :206:16] wire [2:0] pma_checker__state_vec_0_T_10 = pma_checker_state_vec_0_set_left_older ? 3'h0 : pma_checker__state_vec_0_T_9; // @[Replacement.scala:196:33, :202:12, :203:16] wire pma_checker__state_vec_0_set_left_older_T_2 = pma_checker__state_vec_0_T_11[1]; // @[Replacement.scala:196:43, :207:62] wire pma_checker_state_vec_0_set_left_older_2 = ~pma_checker__state_vec_0_set_left_older_T_2; // @[Replacement.scala:196:{33,43}] wire pma_checker__state_vec_0_T_12 = pma_checker__state_vec_0_T_11[0]; // @[package.scala:163:13] wire pma_checker__state_vec_0_T_16 = pma_checker__state_vec_0_T_11[0]; // @[package.scala:163:13] wire pma_checker__state_vec_0_T_13 = pma_checker__state_vec_0_T_12; // @[package.scala:163:13] wire pma_checker__state_vec_0_T_14 = ~pma_checker__state_vec_0_T_13; // @[Replacement.scala:218:{7,17}] wire pma_checker__state_vec_0_T_15 = ~pma_checker_state_vec_0_set_left_older_2 & pma_checker__state_vec_0_T_14; // @[Replacement.scala:196:33, :203:16, :218:7] wire pma_checker__state_vec_0_T_17 = pma_checker__state_vec_0_T_16; // @[Replacement.scala:207:62, :218:17] wire pma_checker__state_vec_0_T_18 = ~pma_checker__state_vec_0_T_17; // @[Replacement.scala:218:{7,17}] wire pma_checker__state_vec_0_T_19 = pma_checker_state_vec_0_set_left_older_2 & pma_checker__state_vec_0_T_18; // @[Replacement.scala:196:33, :206:16, :218:7] wire [1:0] pma_checker_state_vec_0_hi_1 = {pma_checker_state_vec_0_set_left_older_2, pma_checker__state_vec_0_T_15}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] pma_checker__state_vec_0_T_20 = {pma_checker_state_vec_0_hi_1, pma_checker__state_vec_0_T_19}; // @[Replacement.scala:202:12, :206:16] wire [2:0] pma_checker__state_vec_0_T_21 = pma_checker_state_vec_0_set_left_older ? pma_checker__state_vec_0_T_20 : 3'h0; // @[Replacement.scala:196:33, :202:12, :206:16] wire [3:0] pma_checker_state_vec_0_hi_2 = {pma_checker_state_vec_0_set_left_older, pma_checker__state_vec_0_T_10}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [6:0] pma_checker__state_vec_0_T_22 = {pma_checker_state_vec_0_hi_2, pma_checker__state_vec_0_T_21}; // @[Replacement.scala:202:12, :206:16] wire [1:0] pma_checker_lo_3 = {pma_checker_superpage_hits_1, pma_checker_superpage_hits_0}; // @[OneHot.scala:21:45] wire [1:0] pma_checker_lo_4 = pma_checker_lo_3; // @[OneHot.scala:21:45, :31:18] wire [1:0] pma_checker_hi_3 = {pma_checker_superpage_hits_3, pma_checker_superpage_hits_2}; // @[OneHot.scala:21:45] wire [1:0] pma_checker_hi_4 = pma_checker_hi_3; // @[OneHot.scala:21:45, :30:18] wire [1:0] pma_checker_state_reg_touch_way_sized = {\|pma_checker_hi_4, pma_checker_hi_4[1] \| pma_checker_lo_4[1]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}] wire pma_checker__state_reg_set_left_older_T = pma_checker_state_reg_touch_way_sized[1]; // @[package.scala:163:13] wire pma_checker_state_reg_set_left_older = ~pma_checker__state_reg_set_left_older_T; // @[Replacement.scala:196:{33,43}] wire pma_checker__state_reg_T = pma_checker_state_reg_touch_way_sized[0]; // @[package.scala:163:13] wire pma_checker__state_reg_T_4 = pma_checker_state_reg_touch_way_sized[0]; // @[package.scala:163:13] wire pma_checker__state_reg_T_1 = pma_checker__state_reg_T; // @[package.scala:163:13] wire pma_checker__state_reg_T_2 = ~pma_checker__state_reg_T_1; // @[Replacement.scala:218:{7,17}] wire pma_checker__state_reg_T_3 = ~pma_checker_state_reg_set_left_older & pma_checker__state_reg_T_2; // @[Replacement.scala:196:33, :203:16, :218:7] wire pma_checker__state_reg_T_5 = pma_checker__state_reg_T_4; // @[Replacement.scala:207:62, :218:17] wire pma_checker__state_reg_T_6 = ~pma_checker__state_reg_T_5; // @[Replacement.scala:218:{7,17}] wire pma_checker__state_reg_T_7 = pma_checker_state_reg_set_left_older & pma_checker__state_reg_T_6; // @[Replacement.scala:196:33, :206:16, :218:7] wire [1:0] pma_checker_state_reg_hi = {pma_checker_state_reg_set_left_older, pma_checker__state_reg_T_3}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] pma_checker__state_reg_T_8 = {pma_checker_state_reg_hi, pma_checker__state_reg_T_7}; // @[Replacement.scala:202:12, :206:16] wire [13:0] pma_checker__io_resp_pf_ld_T_1 = pma_checker_pf_ld_array & 14'h2000; // @[TLB.scala:597:24, :633:57] wire pma_checker__io_resp_pf_ld_T_2 = \|pma_checker__io_resp_pf_ld_T_1; // @[TLB.scala:633:{57,65}] assign pma_checker__io_resp_pf_ld_T_3 = pma_checker__io_resp_pf_ld_T_2; // @[TLB.scala:633:{41,65}] assign pma_checker_io_resp_pf_ld = pma_checker__io_resp_pf_ld_T_3; // @[TLB.scala:633:41] wire [13:0] pma_checker__io_resp_pf_st_T_1 = pma_checker_pf_st_array & 14'h2000; // @[TLB.scala:598:24, :634:64] wire pma_checker__io_resp_pf_st_T_2 = \|pma_checker__io_resp_pf_st_T_1; // @[TLB.scala:634:{64,72}] assign pma_checker__io_resp_pf_st_T_3 = pma_checker__io_resp_pf_st_T_2; // @[TLB.scala:634:{48,72}] assign pma_checker_io_resp_pf_st = pma_checker__io_resp_pf_st_T_3; // @[TLB.scala:634:48] wire [13:0] pma_checker__io_resp_pf_inst_T = pma_checker_pf_inst_array & 14'h2000; // @[TLB.scala:599:67, :635:47] wire pma_checker__io_resp_pf_inst_T_1 = \|pma_checker__io_resp_pf_inst_T; // @[TLB.scala:635:{47,55}] assign pma_checker__io_resp_pf_inst_T_2 = pma_checker__io_resp_pf_inst_T_1; // @[TLB.scala:635:{29,55}] assign pma_checker_io_resp_pf_inst = pma_checker__io_resp_pf_inst_T_2; // @[TLB.scala:635:29] wire [13:0] pma_checker__io_resp_ae_ld_T = pma_checker_ae_ld_array & 14'h2000; // @[TLB.scala:586:24, :641:33] assign pma_checker__io_resp_ae_ld_T_1 = \|pma_checker__io_resp_ae_ld_T; // @[TLB.scala:641:{33,41}] assign pma_checker_io_resp_ae_ld = pma_checker__io_resp_ae_ld_T_1; // @[TLB.scala:641:41] wire [13:0] pma_checker__io_resp_ae_st_T = pma_checker_ae_st_array & 14'h2000; // @[TLB.scala:590:53, :642:33] assign pma_checker__io_resp_ae_st_T_1 = \|pma_checker__io_resp_ae_st_T; // @[TLB.scala:642:{33,41}] assign pma_checker_io_resp_ae_st = pma_checker__io_resp_ae_st_T_1; // @[TLB.scala:642:41] wire [13:0] pma_checker__io_resp_ae_inst_T = ~pma_checker_px_array; // @[TLB.scala:533:87, :643:23] wire [13:0] pma_checker__io_resp_ae_inst_T_1 = pma_checker__io_resp_ae_inst_T & 14'h2000; // @[TLB.scala:643:{23,33}] assign pma_checker__io_resp_ae_inst_T_2 = \|pma_checker__io_resp_ae_inst_T_1; // @[TLB.scala:643:{33,41}] assign pma_checker_io_resp_ae_inst = pma_checker__io_resp_ae_inst_T_2; // @[TLB.scala:643:41] assign pma_checker__io_resp_ma_ld_T = pma_checker_misaligned & pma_checker_cmd_read; // @[TLB.scala:550:77, :645:31] assign pma_checker_io_resp_ma_ld = pma_checker__io_resp_ma_ld_T; // @[TLB.scala:645:31] assign pma_checker__io_resp_ma_st_T = pma_checker_misaligned & pma_checker_cmd_write; // @[TLB.scala:550:77, :646:31] assign pma_checker_io_resp_ma_st = pma_checker__io_resp_ma_st_T; // @[TLB.scala:646:31] wire [13:0] pma_checker__io_resp_cacheable_T = pma_checker_c_array & 14'h2000; // @[TLB.scala:537:20, :648:33] assign pma_checker__io_resp_cacheable_T_1 = \|pma_checker__io_resp_cacheable_T; // @[TLB.scala:648:{33,41}] assign pma_checker_io_resp_cacheable = pma_checker__io_resp_cacheable_T_1; // @[TLB.scala:648:41] wire [13:0] pma_checker__io_resp_must_alloc_T = pma_checker_must_alloc_array & 14'h2000; // @[TLB.scala:595:46, :649:43] assign pma_checker__io_resp_must_alloc_T_1 = \|pma_checker__io_resp_must_alloc_T; // @[TLB.scala:649:{43,51}] assign pma_checker_io_resp_must_alloc = pma_checker__io_resp_must_alloc_T_1; // @[TLB.scala:649:51] wire [13:0] pma_checker__io_resp_prefetchable_T = pma_checker_prefetchable_array & 14'h2000; // @[TLB.scala:547:31, :650:47] wire pma_checker__io_resp_prefetchable_T_1 = \|pma_checker__io_resp_prefetchable_T; // @[TLB.scala:650:{47,55}] assign pma_checker__io_resp_prefetchable_T_2 = pma_checker__io_resp_prefetchable_T_1; // @[TLB.scala:650:{55,59}] assign pma_checker_io_resp_prefetchable = pma_checker__io_resp_prefetchable_T_2; // @[TLB.scala:650:59] assign pma_checker__io_resp_paddr_T_1 = {pma_checker_ppn, pma_checker__io_resp_paddr_T}; // @[Mux.scala:30:73] assign pma_checker_io_resp_paddr = pma_checker__io_resp_paddr_T_1; // @[TLB.scala:652:23] wire [21:0] pma_checker__io_resp_gpa_page_T_1 = {1'h0, pma_checker_vpn}; // @[TLB.scala:335:30, :657:36] wire [21:0] pma_checker_io_resp_gpa_page = pma_checker__io_resp_gpa_page_T_1; // @[TLB.scala:657:{19,36}] wire [11:0] pma_checker_io_resp_gpa_offset = pma_checker__io_resp_gpa_offset_T_1; // @[TLB.scala:658:{21,82}] assign pma_checker__io_resp_gpa_T = {pma_checker_io_resp_gpa_page, pma_checker_io_resp_gpa_offset}; // @[TLB.scala:657:19, :658:21, :659:8] assign pma_checker_io_resp_gpa = pma_checker__io_resp_gpa_T; // @[TLB.scala:659:8] wire replace; // @[Replacement.scala:37:29] wire [1:0] lfsr_lo_lo_lo = {_lfsr_prng_io_out_1, _lfsr_prng_io_out_0}; // @[PRNG.scala:91:22, :95:17] wire [1:0] lfsr_lo_lo_hi = {_lfsr_prng_io_out_3, _lfsr_prng_io_out_2}; // @[PRNG.scala:91:22, :95:17] wire [3:0] lfsr_lo_lo = {lfsr_lo_lo_hi, lfsr_lo_lo_lo}; // @[PRNG.scala:95:17] wire [1:0] lfsr_lo_hi_lo = {_lfsr_prng_io_out_5, _lfsr_prng_io_out_4}; // @[PRNG.scala:91:22, :95:17] wire [1:0] lfsr_lo_hi_hi = {_lfsr_prng_io_out_7, _lfsr_prng_io_out_6}; // @[PRNG.scala:91:22, :95:17] wire [3:0] lfsr_lo_hi = {lfsr_lo_hi_hi, lfsr_lo_hi_lo}; // @[PRNG.scala:95:17] wire [7:0] lfsr_lo = {lfsr_lo_hi, lfsr_lo_lo}; // @[PRNG.scala:95:17] wire [1:0] lfsr_hi_lo_lo = {_lfsr_prng_io_out_9, _lfsr_prng_io_out_8}; // @[PRNG.scala:91:22, :95:17] wire [1:0] lfsr_hi_lo_hi = {_lfsr_prng_io_out_11, _lfsr_prng_io_out_10}; // @[PRNG.scala:91:22, :95:17] wire [3:0] lfsr_hi_lo = {lfsr_hi_lo_hi, lfsr_hi_lo_lo}; // @[PRNG.scala:95:17] wire [1:0] lfsr_hi_hi_lo = {_lfsr_prng_io_out_13, _lfsr_prng_io_out_12}; // @[PRNG.scala:91:22, :95:17] wire [1:0] lfsr_hi_hi_hi = {_lfsr_prng_io_out_15, _lfsr_prng_io_out_14}; // @[PRNG.scala:91:22, :95:17] wire [3:0] lfsr_hi_hi = {lfsr_hi_hi_hi, lfsr_hi_hi_lo}; // @[PRNG.scala:95:17] wire [7:0] lfsr_hi = {lfsr_hi_hi, lfsr_hi_lo}; // @[PRNG.scala:95:17] wire [15:0] lfsr = {lfsr_hi, lfsr_lo}; // @[PRNG.scala:95:17] wire [33:0] _metaArb_io_in_5_bits_addr_T_2; // @[DCache.scala:1018:36] wire [33:0] _metaArb_io_in_1_bits_addr_T_2; // @[DCache.scala:454:36] wire [7:0] _metaArb_io_in_1_bits_idx_T_2; // @[DCache.scala:453:35] wire _metaArb_io_in_2_valid_T; // @[DCache.scala:462:63] wire metaArb__grant_T_1 = metaArb_io_in_2_valid; // @[Arbiter.scala:45:68] wire [33:0] _metaArb_io_in_2_bits_addr_T_2; // @[DCache.scala:466:36] wire [7:0] _metaArb_io_in_2_bits_idx_T; // @[DCache.scala:465:40] wire [19:0] _metaArb_io_in_2_bits_data_T_1; // @[DCache.scala:467:97] wire metaArb__io_in_3_ready_T; // @[Arbiter.scala:153:19] wire _metaArb_io_in_3_valid_T_2; // @[DCache.scala:741:53] wire [33:0] _metaArb_io_in_3_bits_addr_T_2; // @[DCache.scala:745:36] wire [7:0] _metaArb_io_in_3_bits_idx_T; // @[DCache.scala:744:40] wire [19:0] _metaArb_io_in_3_bits_data_T_18; // @[DCache.scala:746:134] wire metaArb__io_in_4_ready_T; // @[Arbiter.scala:153:19] wire [33:0] _metaArb_io_in_4_bits_addr_T_2; // @[DCache.scala:912:36] wire releaseWay; // @[DCache.scala:232:24] wire [19:0] _metaArb_io_in_4_bits_data_T_1; // @[DCache.scala:913:97] wire metaArb__io_in_5_ready_T; // @[Arbiter.scala:153:19] wire metaArb__io_in_6_ready_T; // @[Arbiter.scala:153:19] wire [33:0] _metaArb_io_in_6_bits_addr_T_1; // @[DCache.scala:773:36] wire metaArb__io_in_7_ready_T; // @[Arbiter.scala:153:19] wire [7:0] _metaArb_io_in_7_bits_idx_T; // @[DCache.scala:263:58] wire metaArb__io_out_valid_T_1; // @[Arbiter.scala:154:31] wire [33:0] metaArb_io_in_0_bits_addr; // @[DCache.scala:135:28] wire [33:0] metaArb_io_in_1_bits_addr; // @[DCache.scala:135:28] wire [7:0] metaArb_io_in_1_bits_idx; // @[DCache.scala:135:28] wire [33:0] metaArb_io_in_2_bits_addr; // @[DCache.scala:135:28] wire [7:0] metaArb_io_in_2_bits_idx; // @[DCache.scala:135:28] wire metaArb_io_in_2_bits_way_en; // @[DCache.scala:135:28] wire [19:0] metaArb_io_in_2_bits_data; // @[DCache.scala:135:28] wire [33:0] metaArb_io_in_3_bits_addr; // @[DCache.scala:135:28] wire [7:0] metaArb_io_in_3_bits_idx; // @[DCache.scala:135:28] wire metaArb_io_in_3_bits_way_en; // @[DCache.scala:135:28] wire [19:0] metaArb_io_in_3_bits_data; // @[DCache.scala:135:28] wire metaArb_io_in_3_ready; // @[DCache.scala:135:28] wire metaArb_io_in_3_valid; // @[DCache.scala:135:28] wire [33:0] metaArb_io_in_4_bits_addr; // @[DCache.scala:135:28] wire metaArb_io_in_4_bits_way_en; // @[DCache.scala:135:28] wire [19:0] metaArb_io_in_4_bits_data; // @[DCache.scala:135:28] wire metaArb_io_in_4_ready; // @[DCache.scala:135:28] wire [33:0] metaArb_io_in_5_bits_addr; // @[DCache.scala:135:28] wire metaArb_io_in_5_bits_way_en; // @[DCache.scala:135:28] wire [19:0] metaArb_io_in_5_bits_data; // @[DCache.scala:135:28] wire metaArb_io_in_5_ready; // @[DCache.scala:135:28] wire [33:0] metaArb_io_in_6_bits_addr; // @[DCache.scala:135:28] wire metaArb_io_in_6_bits_way_en; // @[DCache.scala:135:28] wire [19:0] metaArb_io_in_6_bits_data; // @[DCache.scala:135:28] wire metaArb_io_in_6_ready; // @[DCache.scala:135:28] wire [7:0] metaArb_io_in_7_bits_idx; // @[DCache.scala:135:28] wire metaArb_io_in_7_bits_way_en; // @[DCache.scala:135:28] wire [19:0] metaArb_io_in_7_bits_data; // @[DCache.scala:135:28] wire metaArb_io_in_7_ready; // @[DCache.scala:135:28] wire metaArb_io_out_bits_write; // @[DCache.scala:135:28] wire [33:0] metaArb_io_out_bits_addr; // @[DCache.scala:135:28] wire [7:0] metaArb_io_out_bits_idx; // @[DCache.scala:135:28] wire metaArb_io_out_bits_way_en; // @[DCache.scala:135:28] wire [19:0] metaArb_io_out_bits_data; // @[DCache.scala:135:28] wire metaArb_io_out_valid; // @[DCache.scala:135:28] wire [2:0] metaArb_io_chosen; // @[DCache.scala:135:28] assign metaArb_io_chosen = metaArb_io_in_2_valid ? 3'h2 : {~metaArb_io_in_3_valid, 2'h3}; // @[Arbiter.scala:145:26, :146:17] assign metaArb_io_out_bits_addr = metaArb_io_in_2_valid ? metaArb_io_in_2_bits_addr : metaArb_io_in_3_valid ? metaArb_io_in_3_bits_addr : metaArb_io_in_7_bits_addr; // @[Arbiter.scala:145:26, :147:19] assign metaArb_io_out_bits_idx = metaArb_io_in_2_valid ? metaArb_io_in_2_bits_idx : metaArb_io_in_3_valid ? metaArb_io_in_3_bits_idx : metaArb_io_in_7_bits_idx; // @[Arbiter.scala:145:26, :147:19] assign metaArb_io_out_bits_way_en = metaArb_io_in_2_valid ? metaArb_io_in_2_bits_way_en : metaArb_io_in_3_valid ? metaArb_io_in_3_bits_way_en : metaArb_io_in_7_bits_way_en; // @[Arbiter.scala:145:26, :147:19] assign metaArb_io_out_bits_data = metaArb_io_in_2_valid ? metaArb_io_in_2_bits_data : metaArb_io_in_3_valid ? metaArb_io_in_3_bits_data : metaArb_io_in_7_bits_data; // @[Arbiter.scala:145:26, :147:19] assign metaArb_io_out_bits_write = metaArb_io_in_2_valid \| metaArb_io_in_3_valid; // @[Arbiter.scala:145:26, :147:19] wire metaArb__grant_T_2 = metaArb__grant_T_1 \| metaArb_io_in_3_valid; // @[Arbiter.scala:45:68] wire metaArb__grant_T_3 = metaArb__grant_T_2; // @[Arbiter.scala:45:68] wire metaArb__grant_T_4 = metaArb__grant_T_3; // @[Arbiter.scala:45:68] wire metaArb__grant_T_5 = metaArb__grant_T_4; // @[Arbiter.scala:45:68] wire metaArb_grant_3 = ~metaArb__grant_T_1; // @[Arbiter.scala:45:{68,78}] assign metaArb__io_in_3_ready_T = metaArb_grant_3; // @[Arbiter.scala:45:78, :153:19] wire metaArb_grant_4 = ~metaArb__grant_T_2; // @[Arbiter.scala:45:{68,78}] assign metaArb__io_in_4_ready_T = metaArb_grant_4; // @[Arbiter.scala:45:78, :153:19] wire metaArb_grant_5 = ~metaArb__grant_T_3; // @[Arbiter.scala:45:{68,78}] assign metaArb__io_in_5_ready_T = metaArb_grant_5; // @[Arbiter.scala:45:78, :153:19] wire metaArb_grant_6 = ~metaArb__grant_T_4; // @[Arbiter.scala:45:{68,78}] assign metaArb__io_in_6_ready_T = metaArb_grant_6; // @[Arbiter.scala:45:78, :153:19] wire metaArb_grant_7 = ~metaArb__grant_T_5; // @[Arbiter.scala:45:{68,78}] assign metaArb__io_in_7_ready_T = metaArb_grant_7; // @[Arbiter.scala:45:78, :153:19] assign metaArb_io_in_3_ready = metaArb__io_in_3_ready_T; // @[Arbiter.scala:153:19] assign metaArb_io_in_4_ready = metaArb__io_in_4_ready_T; // @[Arbiter.scala:153:19] assign metaArb_io_in_5_ready = metaArb__io_in_5_ready_T; // @[Arbiter.scala:153:19] assign metaArb_io_in_6_ready = metaArb__io_in_6_ready_T; // @[Arbiter.scala:153:19] assign metaArb_io_in_7_ready = metaArb__io_in_7_ready_T; // @[Arbiter.scala:153:19] wire metaArb__io_out_valid_T = ~metaArb_grant_7; // @[Arbiter.scala:45:78, :154:19] assign metaArb__io_out_valid_T_1 = metaArb__io_out_valid_T \| metaArb_io_in_7_valid; // @[Arbiter.scala:154:{19,31}] assign metaArb_io_out_valid = metaArb__io_out_valid_T_1; // @[Arbiter.scala:154:31] wire _dataArb_io_in_0_valid_T_12; // @[DCache.scala:516:27] wire pstore_drain; // @[DCache.scala:516:27] wire [63:0] _dataArb_io_in_0_bits_wdata_T_9; // @[package.scala:45:27] wire [7:0] _dataArb_io_in_0_bits_eccMask_T_17; // @[package.scala:45:27] wire _dataArb_io_in_0_bits_way_en_T; // @[DCache.scala:550:38] wire dataArb__io_in_1_ready_T; // @[Arbiter.scala:153:19] wire dataArb__io_in_2_ready_T; // @[Arbiter.scala:153:19] wire [13:0] _dataArb_io_in_2_bits_addr_T_4; // @[DCache.scala:903:72] wire dataArb__io_in_3_ready_T; // @[Arbiter.scala:153:19] wire _dataArb_io_in_3_valid_T_58; // @[DCache.scala:242:46] wire dataArb__io_out_valid_T_1; // @[Arbiter.scala:154:31] wire [13:0] dataArb_io_in_0_bits_addr; // @[DCache.scala:152:28] wire dataArb_io_in_0_bits_write; // @[DCache.scala:152:28] wire [63:0] dataArb_io_in_0_bits_wdata; // @[DCache.scala:152:28] wire dataArb_io_in_0_bits_wordMask; // @[DCache.scala:152:28] wire [7:0] dataArb_io_in_0_bits_eccMask; // @[DCache.scala:152:28] wire dataArb_io_in_0_bits_way_en; // @[DCache.scala:152:28] wire dataArb_io_in_0_valid; // @[DCache.scala:152:28] wire [13:0] dataArb_io_in_1_bits_addr; // @[DCache.scala:152:28] wire dataArb_io_in_1_bits_write; // @[DCache.scala:152:28] wire [63:0] dataArb_io_in_1_bits_wdata; // @[DCache.scala:152:28] wire dataArb_io_in_1_bits_wordMask; // @[DCache.scala:152:28] wire [7:0] dataArb_io_in_1_bits_eccMask; // @[DCache.scala:152:28] wire dataArb_io_in_1_bits_way_en; // @[DCache.scala:152:28] wire dataArb_io_in_1_ready; // @[DCache.scala:152:28] wire dataArb_io_in_1_valid; // @[DCache.scala:152:28] wire [13:0] dataArb_io_in_2_bits_addr; // @[DCache.scala:152:28] wire [63:0] dataArb_io_in_2_bits_wdata; // @[DCache.scala:152:28] wire dataArb_io_in_2_ready; // @[DCache.scala:152:28] wire [13:0] dataArb_io_in_3_bits_addr; // @[DCache.scala:152:28] wire [63:0] dataArb_io_in_3_bits_wdata; // @[DCache.scala:152:28] wire dataArb_io_in_3_ready; // @[DCache.scala:152:28] wire dataArb_io_in_3_valid; // @[DCache.scala:152:28] wire [13:0] dataArb_io_out_bits_addr; // @[DCache.scala:152:28] wire dataArb_io_out_bits_write; // @[DCache.scala:152:28] wire [63:0] dataArb_io_out_bits_wdata; // @[DCache.scala:152:28] wire dataArb_io_out_bits_wordMask; // @[DCache.scala:152:28] wire [7:0] dataArb_io_out_bits_eccMask; // @[DCache.scala:152:28] wire dataArb_io_out_bits_way_en; // @[DCache.scala:152:28] wire dataArb_io_out_valid; // @[DCache.scala:152:28] wire [1:0] dataArb_io_chosen; // @[DCache.scala:152:28] assign dataArb_io_chosen = dataArb_io_in_0_valid ? 2'h0 : {~dataArb_io_in_1_valid, 1'h1}; // @[Arbiter.scala:145:26, :146:17] assign dataArb_io_out_bits_addr = dataArb_io_in_0_valid ? dataArb_io_in_0_bits_addr : dataArb_io_in_1_valid ? dataArb_io_in_1_bits_addr : dataArb_io_in_3_bits_addr; // @[Arbiter.scala:145:26, :147:19] assign dataArb_io_out_bits_write = dataArb_io_in_0_valid ? dataArb_io_in_0_bits_write : dataArb_io_in_1_valid & dataArb_io_in_1_bits_write; // @[Arbiter.scala:145:26, :147:19] assign dataArb_io_out_bits_wdata = dataArb_io_in_0_valid ? dataArb_io_in_0_bits_wdata : dataArb_io_in_1_valid ? dataArb_io_in_1_bits_wdata : dataArb_io_in_3_bits_wdata; // @[Arbiter.scala:145:26, :147:19] assign dataArb_io_out_bits_wordMask = dataArb_io_in_0_valid ? dataArb_io_in_0_bits_wordMask : ~dataArb_io_in_1_valid \| dataArb_io_in_1_bits_wordMask; // @[Arbiter.scala:145:26, :146:17, :147:19] assign dataArb_io_out_bits_eccMask = dataArb_io_in_0_valid ? dataArb_io_in_0_bits_eccMask : dataArb_io_in_1_valid ? dataArb_io_in_1_bits_eccMask : 8'hFF; // @[Arbiter.scala:145:26, :147:19] assign dataArb_io_out_bits_way_en = dataArb_io_in_0_valid ? dataArb_io_in_0_bits_way_en : ~dataArb_io_in_1_valid \| dataArb_io_in_1_bits_way_en; // @[Arbiter.scala:145:26, :146:17, :147:19] wire dataArb__grant_T = dataArb_io_in_0_valid \| dataArb_io_in_1_valid; // @[Arbiter.scala:45:68] wire dataArb__grant_T_1 = dataArb__grant_T; // @[Arbiter.scala:45:68] wire dataArb_grant_1 = ~dataArb_io_in_0_valid; // @[Arbiter.scala:45:78] assign dataArb__io_in_1_ready_T = dataArb_grant_1; // @[Arbiter.scala:45:78, :153:19] wire dataArb_grant_2 = ~dataArb__grant_T; // @[Arbiter.scala:45:{68,78}] assign dataArb__io_in_2_ready_T = dataArb_grant_2; // @[Arbiter.scala:45:78, :153:19] wire dataArb_grant_3 = ~dataArb__grant_T_1; // @[Arbiter.scala:45:{68,78}] assign dataArb__io_in_3_ready_T = dataArb_grant_3; // @[Arbiter.scala:45:78, :153:19] assign dataArb_io_in_1_ready = dataArb__io_in_1_ready_T; // @[Arbiter.scala:153:19] assign dataArb_io_in_2_ready = dataArb__io_in_2_ready_T; // @[Arbiter.scala:153:19] assign dataArb_io_in_3_ready = dataArb__io_in_3_ready_T; // @[Arbiter.scala:153:19] wire dataArb__io_out_valid_T = ~dataArb_grant_3; // @[Arbiter.scala:45:78, :154:19] assign dataArb__io_out_valid_T_1 = dataArb__io_out_valid_T \| dataArb_io_in_3_valid; // @[Arbiter.scala:154:{19,31}] assign dataArb_io_out_valid = dataArb__io_out_valid_T_1; // @[Arbiter.scala:154:31] wire _tl_out_a_valid_T_14; // @[DCache.scala:603:37] assign nodeOut_a_deq_valid = tl_out_a_valid; // @[Decoupled.scala:356:21] wire [2:0] _tl_out_a_bits_T_7_opcode; // @[DCache.scala:608:23] assign nodeOut_a_deq_bits_opcode = tl_out_a_bits_opcode; // @[Decoupled.scala:356:21] wire [2:0] _tl_out_a_bits_T_7_param; // @[DCache.scala:608:23] assign nodeOut_a_deq_bits_param = tl_out_a_bits_param; // @[Decoupled.scala:356:21] wire [3:0] _tl_out_a_bits_T_7_size; // @[DCache.scala:608:23] assign nodeOut_a_deq_bits_size = tl_out_a_bits_size; // @[Decoupled.scala:356:21] wire [31:0] _tl_out_a_bits_T_7_address; // @[DCache.scala:608:23] assign nodeOut_a_deq_bits_address = tl_out_a_bits_address; // @[Decoupled.scala:356:21] wire [7:0] _tl_out_a_bits_T_7_mask; // @[DCache.scala:608:23] assign nodeOut_a_deq_bits_mask = tl_out_a_bits_mask; // @[Decoupled.scala:356:21] wire [63:0] _tl_out_a_bits_T_7_data; // @[DCache.scala:608:23] assign nodeOut_a_deq_bits_data = tl_out_a_bits_data; // @[Decoupled.scala:356:21] wire tl_out_a_ready; // @[DCache.scala:159:22] assign tl_out_a_ready = nodeOut_a_deq_ready; // @[Decoupled.scala:356:21] assign nodeOut_a_valid = nodeOut_a_deq_valid; // @[Decoupled.scala:356:21] assign nodeOut_a_bits_opcode = nodeOut_a_deq_bits_opcode; // @[Decoupled.scala:356:21] assign nodeOut_a_bits_param = nodeOut_a_deq_bits_param; // @[Decoupled.scala:356:21] assign nodeOut_a_bits_size = nodeOut_a_deq_bits_size; // @[Decoupled.scala:356:21] assign nodeOut_a_bits_address = nodeOut_a_deq_bits_address; // @[Decoupled.scala:356:21] assign nodeOut_a_bits_mask = nodeOut_a_deq_bits_mask; // @[Decoupled.scala:356:21] assign nodeOut_a_bits_data = nodeOut_a_deq_bits_data; // @[Decoupled.scala:356:21] wire _tl_out_c_valid_T_6; // @[DCache.scala:810:117] wire tl_out_c_valid; // @[Bundles.scala:265:61] wire _s1_valid_T = io_cpu_req_ready_0 & io_cpu_req_valid_0; // @[Decoupled.scala:51:35] reg s1_valid; // @[DCache.scala:182:25] wire _s2_data_en_T = s1_valid; // @[DCache.scala:182:25, :366:23] wire s1_nack; // @[DCache.scala:185:28] wire _s1_valid_masked_T = ~io_cpu_s1_kill_0; // @[DCache.scala:101:7, :186:37] wire s1_valid_masked = s1_valid & _s1_valid_masked_T; // @[DCache.scala:182:25, :186:{34,37}] wire _s1_valid_not_nacked_T = ~s1_nack; // @[DCache.scala:185:28, :187:41] wire s1_valid_not_nacked = s1_valid & _s1_valid_not_nacked_T; // @[DCache.scala:182:25, :187:{38,41}] wire _s0_clk_en_T = ~metaArb_io_out_bits_write; // @[DCache.scala:135:28, :190:43] wire s0_clk_en = metaArb_io_out_valid & _s0_clk_en_T; // @[DCache.scala:135:28, :190:{40,43}] wire _s1_tlb_req_T = s0_clk_en; // @[DCache.scala:190:40, :208:52] wire [33:0] _s0_req_addr_T_2; // @[DCache.scala:193:21] wire [33:0] s0_tlb_req_vaddr = s0_req_addr; // @[DCache.scala:192:24, :199:28] wire [4:0] s0_tlb_req_cmd = s0_req_cmd; // @[DCache.scala:192:24, :199:28] wire [1:0] s0_tlb_req_size = s0_req_size; // @[DCache.scala:192:24, :199:28] wire [1:0] s0_tlb_req_prv = s0_req_dprv; // @[DCache.scala:192:24, :199:28] wire s0_tlb_req_v = s0_req_dv; // @[DCache.scala:192:24, :199:28] wire s0_tlb_req_passthrough = s0_req_phys; // @[DCache.scala:192:24, :199:28] wire [27:0] _s0_req_addr_T = metaArb_io_out_bits_addr[33:6]; // @[DCache.scala:135:28, :193:47] wire [5:0] _s0_req_addr_T_1 = io_cpu_req_bits_addr_0[5:0]; // @[DCache.scala:101:7, :193:84] assign _s0_req_addr_T_2 = {_s0_req_addr_T, _s0_req_addr_T_1}; // @[DCache.scala:193:{21,47,84}] assign s0_req_addr = _s0_req_addr_T_2; // @[DCache.scala:192:24, :193:21] assign s0_req_phys = ~metaArb_io_in_7_ready \| io_cpu_req_bits_phys_0; // @[DCache.scala:101:7, :135:28, :192:24, :195:{9,34,48}] reg [33:0] s1_req_addr; // @[DCache.scala:196:25] assign pma_checker_io_req_bits_vaddr = s1_req_addr; // @[DCache.scala:120:32, :196:25] reg [6:0] s1_req_tag; // @[DCache.scala:196:25] reg [4:0] s1_req_cmd; // @[DCache.scala:196:25] assign pma_checker_io_req_bits_cmd = s1_req_cmd; // @[DCache.scala:120:32, :196:25] reg [1:0] s1_req_size; // @[DCache.scala:196:25] assign pma_checker_io_req_bits_size = s1_req_size; // @[DCache.scala:120:32, :196:25] wire [1:0] s1_mask_xwr_size = s1_req_size; // @[DCache.scala:196:25] reg s1_req_signed; // @[DCache.scala:196:25] reg [1:0] s1_req_dprv; // @[DCache.scala:196:25] assign pma_checker_io_req_bits_prv = s1_req_dprv; // @[DCache.scala:120:32, :196:25] reg s1_req_dv; // @[DCache.scala:196:25] assign pma_checker_io_req_bits_v = s1_req_dv; // @[DCache.scala:120:32, :196:25] reg s1_req_phys; // @[DCache.scala:196:25] reg s1_req_no_resp; // @[DCache.scala:196:25] reg s1_req_no_xcpt; // @[DCache.scala:196:25] wire [19:0] _s1_vaddr_T = s1_req_addr[33:14]; // @[DCache.scala:196:25, :197:56] wire [13:0] _s1_vaddr_T_1 = s1_req_addr[13:0]; // @[DCache.scala:196:25, :197:78] wire [33:0] s1_vaddr = {_s1_vaddr_T, _s1_vaddr_T_1}; // @[DCache.scala:197:{21,56,78}] reg [33:0] s1_tlb_req_vaddr; // @[DCache.scala:208:29] reg s1_tlb_req_passthrough; // @[DCache.scala:208:29] reg [1:0] s1_tlb_req_size; // @[DCache.scala:208:29] reg [4:0] s1_tlb_req_cmd; // @[DCache.scala:208:29] reg [1:0] s1_tlb_req_prv; // @[DCache.scala:208:29] reg s1_tlb_req_v; // @[DCache.scala:208:29] wire _GEN_39 = s1_req_cmd == 5'h0; // @[package.scala:16:47] wire _s1_read_T; // @[package.scala:16:47] assign _s1_read_T = _GEN_39; // @[package.scala:16:47] wire _pstore1_rmw_T; // @[package.scala:16:47] assign _pstore1_rmw_T = _GEN_39; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_1; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_1 = _GEN_39; // @[package.scala:16:47] wire _GEN_40 = s1_req_cmd == 5'h10; // @[package.scala:16:47] wire _s1_read_T_1; // @[package.scala:16:47] assign _s1_read_T_1 = _GEN_40; // @[package.scala:16:47] wire _pstore1_rmw_T_1; // @[package.scala:16:47] assign _pstore1_rmw_T_1 = _GEN_40; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_2; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_2 = _GEN_40; // @[package.scala:16:47] wire _GEN_41 = s1_req_cmd == 5'h6; // @[package.scala:16:47] wire _s1_read_T_2; // @[package.scala:16:47] assign _s1_read_T_2 = _GEN_41; // @[package.scala:16:47] wire _pstore1_rmw_T_2; // @[package.scala:16:47] assign _pstore1_rmw_T_2 = _GEN_41; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_3; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_3 = _GEN_41; // @[package.scala:16:47] wire _GEN_42 = s1_req_cmd == 5'h7; // @[package.scala:16:47] wire _s1_read_T_3; // @[package.scala:16:47] assign _s1_read_T_3 = _GEN_42; // @[package.scala:16:47] wire _s1_write_T_3; // @[Consts.scala:90:66] assign _s1_write_T_3 = _GEN_42; // @[package.scala:16:47] wire _pstore1_rmw_T_3; // @[package.scala:16:47] assign _pstore1_rmw_T_3 = _GEN_42; // @[package.scala:16:47] wire _pstore1_rmw_T_28; // @[Consts.scala:90:66] assign _pstore1_rmw_T_28 = _GEN_42; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_4; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_4 = _GEN_42; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_29; // @[Consts.scala:90:66] assign _io_cpu_perf_canAcceptLoadThenLoad_T_29 = _GEN_42; // @[package.scala:16:47] wire _s1_read_T_4 = _s1_read_T \| _s1_read_T_1; // @[package.scala:16:47, :81:59] wire _s1_read_T_5 = _s1_read_T_4 \| _s1_read_T_2; // @[package.scala:16:47, :81:59] wire _s1_read_T_6 = _s1_read_T_5 \| _s1_read_T_3; // @[package.scala:16:47, :81:59] wire _GEN_43 = s1_req_cmd == 5'h4; // @[package.scala:16:47] wire _s1_read_T_7; // @[package.scala:16:47] assign _s1_read_T_7 = _GEN_43; // @[package.scala:16:47] wire _s1_write_T_5; // @[package.scala:16:47] assign _s1_write_T_5 = _GEN_43; // @[package.scala:16:47] wire _pstore1_rmw_T_7; // @[package.scala:16:47] assign _pstore1_rmw_T_7 = _GEN_43; // @[package.scala:16:47] wire _pstore1_rmw_T_30; // @[package.scala:16:47] assign _pstore1_rmw_T_30 = _GEN_43; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_8; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_8 = _GEN_43; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_31; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_31 = _GEN_43; // @[package.scala:16:47] wire _GEN_44 = s1_req_cmd == 5'h9; // @[package.scala:16:47] wire _s1_read_T_8; // @[package.scala:16:47] assign _s1_read_T_8 = _GEN_44; // @[package.scala:16:47] wire _s1_write_T_6; // @[package.scala:16:47] assign _s1_write_T_6 = _GEN_44; // @[package.scala:16:47] wire _pstore1_rmw_T_8; // @[package.scala:16:47] assign _pstore1_rmw_T_8 = _GEN_44; // @[package.scala:16:47] wire _pstore1_rmw_T_31; // @[package.scala:16:47] assign _pstore1_rmw_T_31 = _GEN_44; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_9; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_9 = _GEN_44; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_32; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_32 = _GEN_44; // @[package.scala:16:47] wire _GEN_45 = s1_req_cmd == 5'hA; // @[package.scala:16:47] wire _s1_read_T_9; // @[package.scala:16:47] assign _s1_read_T_9 = _GEN_45; // @[package.scala:16:47] wire _s1_write_T_7; // @[package.scala:16:47] assign _s1_write_T_7 = _GEN_45; // @[package.scala:16:47] wire _pstore1_rmw_T_9; // @[package.scala:16:47] assign _pstore1_rmw_T_9 = _GEN_45; // @[package.scala:16:47] wire _pstore1_rmw_T_32; // @[package.scala:16:47] assign _pstore1_rmw_T_32 = _GEN_45; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_10; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_10 = _GEN_45; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_33; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_33 = _GEN_45; // @[package.scala:16:47] wire _GEN_46 = s1_req_cmd == 5'hB; // @[package.scala:16:47] wire _s1_read_T_10; // @[package.scala:16:47] assign _s1_read_T_10 = _GEN_46; // @[package.scala:16:47] wire _s1_write_T_8; // @[package.scala:16:47] assign _s1_write_T_8 = _GEN_46; // @[package.scala:16:47] wire _pstore1_rmw_T_10; // @[package.scala:16:47] assign _pstore1_rmw_T_10 = _GEN_46; // @[package.scala:16:47] wire _pstore1_rmw_T_33; // @[package.scala:16:47] assign _pstore1_rmw_T_33 = _GEN_46; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_11; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_11 = _GEN_46; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_34; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_34 = _GEN_46; // @[package.scala:16:47] wire _s1_read_T_11 = _s1_read_T_7 \| _s1_read_T_8; // @[package.scala:16:47, :81:59] wire _s1_read_T_12 = _s1_read_T_11 \| _s1_read_T_9; // @[package.scala:16:47, :81:59] wire _s1_read_T_13 = _s1_read_T_12 \| _s1_read_T_10; // @[package.scala:16:47, :81:59] wire _GEN_47 = s1_req_cmd == 5'h8; // @[package.scala:16:47] wire _s1_read_T_14; // @[package.scala:16:47] assign _s1_read_T_14 = _GEN_47; // @[package.scala:16:47] wire _s1_write_T_12; // @[package.scala:16:47] assign _s1_write_T_12 = _GEN_47; // @[package.scala:16:47] wire _pstore1_rmw_T_14; // @[package.scala:16:47] assign _pstore1_rmw_T_14 = _GEN_47; // @[package.scala:16:47] wire _pstore1_rmw_T_37; // @[package.scala:16:47] assign _pstore1_rmw_T_37 = _GEN_47; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_15; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_15 = _GEN_47; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_38; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_38 = _GEN_47; // @[package.scala:16:47] wire _GEN_48 = s1_req_cmd == 5'hC; // @[package.scala:16:47] wire _s1_read_T_15; // @[package.scala:16:47] assign _s1_read_T_15 = _GEN_48; // @[package.scala:16:47] wire _s1_write_T_13; // @[package.scala:16:47] assign _s1_write_T_13 = _GEN_48; // @[package.scala:16:47] wire _pstore1_rmw_T_15; // @[package.scala:16:47] assign _pstore1_rmw_T_15 = _GEN_48; // @[package.scala:16:47] wire _pstore1_rmw_T_38; // @[package.scala:16:47] assign _pstore1_rmw_T_38 = _GEN_48; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_16; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_16 = _GEN_48; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_39; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_39 = _GEN_48; // @[package.scala:16:47] wire _GEN_49 = s1_req_cmd == 5'hD; // @[package.scala:16:47] wire _s1_read_T_16; // @[package.scala:16:47] assign _s1_read_T_16 = _GEN_49; // @[package.scala:16:47] wire _s1_write_T_14; // @[package.scala:16:47] assign _s1_write_T_14 = _GEN_49; // @[package.scala:16:47] wire _pstore1_rmw_T_16; // @[package.scala:16:47] assign _pstore1_rmw_T_16 = _GEN_49; // @[package.scala:16:47] wire _pstore1_rmw_T_39; // @[package.scala:16:47] assign _pstore1_rmw_T_39 = _GEN_49; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_17; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_17 = _GEN_49; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_40; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_40 = _GEN_49; // @[package.scala:16:47] wire _GEN_50 = s1_req_cmd == 5'hE; // @[package.scala:16:47] wire _s1_read_T_17; // @[package.scala:16:47] assign _s1_read_T_17 = _GEN_50; // @[package.scala:16:47] wire _s1_write_T_15; // @[package.scala:16:47] assign _s1_write_T_15 = _GEN_50; // @[package.scala:16:47] wire _pstore1_rmw_T_17; // @[package.scala:16:47] assign _pstore1_rmw_T_17 = _GEN_50; // @[package.scala:16:47] wire _pstore1_rmw_T_40; // @[package.scala:16:47] assign _pstore1_rmw_T_40 = _GEN_50; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_18; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_18 = _GEN_50; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_41; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_41 = _GEN_50; // @[package.scala:16:47] wire _GEN_51 = s1_req_cmd == 5'hF; // @[package.scala:16:47] wire _s1_read_T_18; // @[package.scala:16:47] assign _s1_read_T_18 = _GEN_51; // @[package.scala:16:47] wire _s1_write_T_16; // @[package.scala:16:47] assign _s1_write_T_16 = _GEN_51; // @[package.scala:16:47] wire _pstore1_rmw_T_18; // @[package.scala:16:47] assign _pstore1_rmw_T_18 = _GEN_51; // @[package.scala:16:47] wire _pstore1_rmw_T_41; // @[package.scala:16:47] assign _pstore1_rmw_T_41 = _GEN_51; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_19; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_19 = _GEN_51; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_42; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_42 = _GEN_51; // @[package.scala:16:47] wire _s1_read_T_19 = _s1_read_T_14 \| _s1_read_T_15; // @[package.scala:16:47, :81:59] wire _s1_read_T_20 = _s1_read_T_19 \| _s1_read_T_16; // @[package.scala:16:47, :81:59] wire _s1_read_T_21 = _s1_read_T_20 \| _s1_read_T_17; // @[package.scala:16:47, :81:59] wire _s1_read_T_22 = _s1_read_T_21 \| _s1_read_T_18; // @[package.scala:16:47, :81:59] wire _s1_read_T_23 = _s1_read_T_13 \| _s1_read_T_22; // @[package.scala:81:59] wire s1_read = _s1_read_T_6 \| _s1_read_T_23; // @[package.scala:81:59] wire _GEN_52 = s1_req_cmd == 5'h1; // @[DCache.scala:196:25] wire _s1_write_T; // @[Consts.scala:90:32] assign _s1_write_T = _GEN_52; // @[Consts.scala:90:32] wire _pstore1_rmw_T_25; // @[Consts.scala:90:32] assign _pstore1_rmw_T_25 = _GEN_52; // @[Consts.scala:90:32] wire _io_cpu_perf_canAcceptLoadThenLoad_T_26; // @[Consts.scala:90:32] assign _io_cpu_perf_canAcceptLoadThenLoad_T_26 = _GEN_52; // @[Consts.scala:90:32] wire _T_19 = s1_req_cmd == 5'h11; // @[DCache.scala:196:25] wire _s1_write_T_1; // @[Consts.scala:90:49] assign _s1_write_T_1 = _T_19; // @[Consts.scala:90:49] wire _s1_mask_T; // @[DCache.scala:327:32] assign _s1_mask_T = _T_19; // @[DCache.scala:327:32] wire _pstore1_rmw_T_26; // @[Consts.scala:90:49] assign _pstore1_rmw_T_26 = _T_19; // @[Consts.scala:90:49] wire _pstore1_rmw_T_48; // @[DCache.scala:1191:35] assign _pstore1_rmw_T_48 = _T_19; // @[DCache.scala:1191:35] wire _io_cpu_perf_canAcceptLoadThenLoad_T_27; // @[Consts.scala:90:49] assign _io_cpu_perf_canAcceptLoadThenLoad_T_27 = _T_19; // @[Consts.scala:90:49] wire _io_cpu_perf_canAcceptLoadThenLoad_T_49; // @[DCache.scala:1191:35] assign _io_cpu_perf_canAcceptLoadThenLoad_T_49 = _T_19; // @[DCache.scala:1191:35] wire _s1_write_T_2 = _s1_write_T \| _s1_write_T_1; // @[Consts.scala:90:{32,42,49}] wire _s1_write_T_4 = _s1_write_T_2 \| _s1_write_T_3; // @[Consts.scala:90:{42,59,66}] wire _s1_write_T_9 = _s1_write_T_5 \| _s1_write_T_6; // @[package.scala:16:47, :81:59] wire _s1_write_T_10 = _s1_write_T_9 \| _s1_write_T_7; // @[package.scala:16:47, :81:59] wire _s1_write_T_11 = _s1_write_T_10 \| _s1_write_T_8; // @[package.scala:16:47, :81:59] wire _s1_write_T_17 = _s1_write_T_12 \| _s1_write_T_13; // @[package.scala:16:47, :81:59] wire _s1_write_T_18 = _s1_write_T_17 \| _s1_write_T_14; // @[package.scala:16:47, :81:59] wire _s1_write_T_19 = _s1_write_T_18 \| _s1_write_T_15; // @[package.scala:16:47, :81:59] wire _s1_write_T_20 = _s1_write_T_19 \| _s1_write_T_16; // @[package.scala:16:47, :81:59] wire _s1_write_T_21 = _s1_write_T_11 \| _s1_write_T_20; // @[package.scala:81:59] wire s1_write = _s1_write_T_4 \| _s1_write_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire s1_readwrite = s1_read \| s1_write; // @[DCache.scala:212:30] wire _s1_sfence_T = s1_req_cmd == 5'h14; // @[DCache.scala:196:25, :213:30] wire _GEN_53 = s1_req_cmd == 5'h15; // @[DCache.scala:196:25, :213:57] wire _s1_sfence_T_1; // @[DCache.scala:213:57] assign _s1_sfence_T_1 = _GEN_53; // @[DCache.scala:213:57] wire _tlb_io_sfence_bits_hv_T; // @[DCache.scala:283:39] assign _tlb_io_sfence_bits_hv_T = _GEN_53; // @[DCache.scala:213:57, :283:39] wire _s1_sfence_T_2 = _s1_sfence_T \| _s1_sfence_T_1; // @[DCache.scala:213:{30,43,57}] wire _GEN_54 = s1_req_cmd == 5'h16; // @[DCache.scala:196:25, :213:85] wire _s1_sfence_T_3; // @[DCache.scala:213:85] assign _s1_sfence_T_3 = _GEN_54; // @[DCache.scala:213:85] wire _tlb_io_sfence_bits_hg_T; // @[DCache.scala:284:39] assign _tlb_io_sfence_bits_hg_T = _GEN_54; // @[DCache.scala:213:85, :284:39] wire s1_sfence = _s1_sfence_T_2 \| _s1_sfence_T_3; // @[DCache.scala:213:{43,71,85}] wire _s1_flush_line_T = s1_req_cmd == 5'h5; // @[DCache.scala:196:25, :214:34] wire _s1_flush_line_T_1 = s1_req_size[0]; // @[DCache.scala:196:25, :214:64] wire _tlb_io_sfence_bits_rs1_T = s1_req_size[0]; // @[DCache.scala:196:25, :214:64, :279:40] wire s1_flush_line = _s1_flush_line_T & _s1_flush_line_T_1; // @[DCache.scala:214:{34,50,64}] reg s1_flush_valid; // @[DCache.scala:215:27] reg cached_grant_wait; // @[DCache.scala:223:34] reg [1:0] refill_way; // @[DCache.scala:229:23] wire _any_pstore_valid_T; // @[DCache.scala:508:36] wire any_pstore_valid; // @[DCache.scala:230:30] assign metaArb_io_in_4_bits_way_en = releaseWay; // @[DCache.scala:135:28, :232:24] assign metaArb_io_in_5_bits_way_en = releaseWay; // @[DCache.scala:135:28, :232:24] assign metaArb_io_in_6_bits_way_en = releaseWay; // @[DCache.scala:135:28, :232:24] assign metaArb_io_in_7_bits_way_en = releaseWay; // @[DCache.scala:135:28, :232:24] wire _io_cpu_req_ready_T_1 = ~cached_grant_wait; // @[DCache.scala:223:34, :233:54] wire _io_cpu_req_ready_T_2 = _io_cpu_req_ready_T_1; // @[DCache.scala:233:{51,54}] wire _io_cpu_req_ready_T_3 = ~s1_nack; // @[DCache.scala:185:28, :187:41, :233:76] wire _io_cpu_req_ready_T_4 = _io_cpu_req_ready_T_2 & _io_cpu_req_ready_T_3; // @[DCache.scala:233:{51,73,76}] reg uncachedInFlight_0; // @[DCache.scala:236:33] wire _s2_valid_cached_miss_T_2 = uncachedInFlight_0; // @[DCache.scala:236:33, :425:88] wire _s2_valid_uncached_pending_T_1 = uncachedInFlight_0; // @[DCache.scala:236:33, :430:92] wire _io_cpu_ordered_T_6 = uncachedInFlight_0; // @[DCache.scala:236:33, :929:142] wire _io_cpu_store_pending_T_24 = uncachedInFlight_0; // @[DCache.scala:236:33, :930:97] wire _clock_en_reg_T_22 = uncachedInFlight_0; // @[DCache.scala:236:33, :1072:50] reg [33:0] uncachedReqs_0_addr; // @[DCache.scala:237:25] wire [33:0] uncachedResp_addr = uncachedReqs_0_addr; // @[DCache.scala:237:25, :238:30] reg [6:0] uncachedReqs_0_tag; // @[DCache.scala:237:25] wire [6:0] uncachedResp_tag = uncachedReqs_0_tag; // @[DCache.scala:237:25, :238:30] reg [4:0] uncachedReqs_0_cmd; // @[DCache.scala:237:25] wire [4:0] uncachedResp_cmd = uncachedReqs_0_cmd; // @[DCache.scala:237:25, :238:30] reg [1:0] uncachedReqs_0_size; // @[DCache.scala:237:25] wire [1:0] uncachedResp_size = uncachedReqs_0_size; // @[DCache.scala:237:25, :238:30] reg uncachedReqs_0_signed; // @[DCache.scala:237:25] wire uncachedResp_signed = uncachedReqs_0_signed; // @[DCache.scala:237:25, :238:30] reg [1:0] uncachedReqs_0_dprv; // @[DCache.scala:237:25] wire [1:0] uncachedResp_dprv = uncachedReqs_0_dprv; // @[DCache.scala:237:25, :238:30] reg uncachedReqs_0_dv; // @[DCache.scala:237:25] wire uncachedResp_dv = uncachedReqs_0_dv; // @[DCache.scala:237:25, :238:30] reg uncachedReqs_0_phys; // @[DCache.scala:237:25] wire uncachedResp_phys = uncachedReqs_0_phys; // @[DCache.scala:237:25, :238:30] reg uncachedReqs_0_no_resp; // @[DCache.scala:237:25] wire uncachedResp_no_resp = uncachedReqs_0_no_resp; // @[DCache.scala:237:25, :238:30] reg uncachedReqs_0_no_alloc; // @[DCache.scala:237:25] wire uncachedResp_no_alloc = uncachedReqs_0_no_alloc; // @[DCache.scala:237:25, :238:30] reg uncachedReqs_0_no_xcpt; // @[DCache.scala:237:25] wire uncachedResp_no_xcpt = uncachedReqs_0_no_xcpt; // @[DCache.scala:237:25, :238:30] reg [63:0] uncachedReqs_0_data; // @[DCache.scala:237:25] wire [63:0] uncachedResp_data = uncachedReqs_0_data; // @[DCache.scala:237:25, :238:30] reg [7:0] uncachedReqs_0_mask; // @[DCache.scala:237:25] wire [7:0] uncachedResp_mask = uncachedReqs_0_mask; // @[DCache.scala:237:25, :238:30] wire _GEN_55 = io_cpu_req_bits_cmd_0 == 5'h0; // @[package.scala:16:47] wire _s0_read_T; // @[package.scala:16:47] assign _s0_read_T = _GEN_55; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T = _GEN_55; // @[package.scala:16:47] wire _s1_did_read_T; // @[package.scala:16:47] assign _s1_did_read_T = _GEN_55; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T = _GEN_55; // @[package.scala:16:47] wire _GEN_56 = io_cpu_req_bits_cmd_0 == 5'h10; // @[package.scala:16:47] wire _s0_read_T_1; // @[package.scala:16:47] assign _s0_read_T_1 = _GEN_56; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_1; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_1 = _GEN_56; // @[package.scala:16:47] wire _s1_did_read_T_1; // @[package.scala:16:47] assign _s1_did_read_T_1 = _GEN_56; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_1; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_1 = _GEN_56; // @[package.scala:16:47] wire _GEN_57 = io_cpu_req_bits_cmd_0 == 5'h6; // @[package.scala:16:47] wire _s0_read_T_2; // @[package.scala:16:47] assign _s0_read_T_2 = _GEN_57; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_2; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_2 = _GEN_57; // @[package.scala:16:47] wire _s1_did_read_T_2; // @[package.scala:16:47] assign _s1_did_read_T_2 = _GEN_57; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_2; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_2 = _GEN_57; // @[package.scala:16:47] wire _GEN_58 = io_cpu_req_bits_cmd_0 == 5'h7; // @[package.scala:16:47] wire _s0_read_T_3; // @[package.scala:16:47] assign _s0_read_T_3 = _GEN_58; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_3; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_3 = _GEN_58; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_28; // @[Consts.scala:90:66] assign _dataArb_io_in_3_valid_T_28 = _GEN_58; // @[package.scala:16:47] wire _s1_did_read_T_3; // @[package.scala:16:47] assign _s1_did_read_T_3 = _GEN_58; // @[package.scala:16:47] wire _s1_did_read_T_28; // @[Consts.scala:90:66] assign _s1_did_read_T_28 = _GEN_58; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_3; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_3 = _GEN_58; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_28; // @[Consts.scala:90:66] assign _pstore_drain_opportunistic_T_28 = _GEN_58; // @[package.scala:16:47] wire _s0_read_T_4 = _s0_read_T \| _s0_read_T_1; // @[package.scala:16:47, :81:59] wire _s0_read_T_5 = _s0_read_T_4 \| _s0_read_T_2; // @[package.scala:16:47, :81:59] wire _s0_read_T_6 = _s0_read_T_5 \| _s0_read_T_3; // @[package.scala:16:47, :81:59] wire _GEN_59 = io_cpu_req_bits_cmd_0 == 5'h4; // @[package.scala:16:47] wire _s0_read_T_7; // @[package.scala:16:47] assign _s0_read_T_7 = _GEN_59; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_7; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_7 = _GEN_59; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_30; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_30 = _GEN_59; // @[package.scala:16:47] wire _s1_did_read_T_7; // @[package.scala:16:47] assign _s1_did_read_T_7 = _GEN_59; // @[package.scala:16:47] wire _s1_did_read_T_30; // @[package.scala:16:47] assign _s1_did_read_T_30 = _GEN_59; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_7; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_7 = _GEN_59; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_30; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_30 = _GEN_59; // @[package.scala:16:47] wire _GEN_60 = io_cpu_req_bits_cmd_0 == 5'h9; // @[package.scala:16:47] wire _s0_read_T_8; // @[package.scala:16:47] assign _s0_read_T_8 = _GEN_60; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_8; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_8 = _GEN_60; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_31; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_31 = _GEN_60; // @[package.scala:16:47] wire _s1_did_read_T_8; // @[package.scala:16:47] assign _s1_did_read_T_8 = _GEN_60; // @[package.scala:16:47] wire _s1_did_read_T_31; // @[package.scala:16:47] assign _s1_did_read_T_31 = _GEN_60; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_8; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_8 = _GEN_60; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_31; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_31 = _GEN_60; // @[package.scala:16:47] wire _GEN_61 = io_cpu_req_bits_cmd_0 == 5'hA; // @[package.scala:16:47] wire _s0_read_T_9; // @[package.scala:16:47] assign _s0_read_T_9 = _GEN_61; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_9; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_9 = _GEN_61; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_32; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_32 = _GEN_61; // @[package.scala:16:47] wire _s1_did_read_T_9; // @[package.scala:16:47] assign _s1_did_read_T_9 = _GEN_61; // @[package.scala:16:47] wire _s1_did_read_T_32; // @[package.scala:16:47] assign _s1_did_read_T_32 = _GEN_61; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_9; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_9 = _GEN_61; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_32; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_32 = _GEN_61; // @[package.scala:16:47] wire _GEN_62 = io_cpu_req_bits_cmd_0 == 5'hB; // @[package.scala:16:47] wire _s0_read_T_10; // @[package.scala:16:47] assign _s0_read_T_10 = _GEN_62; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_10; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_10 = _GEN_62; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_33; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_33 = _GEN_62; // @[package.scala:16:47] wire _s1_did_read_T_10; // @[package.scala:16:47] assign _s1_did_read_T_10 = _GEN_62; // @[package.scala:16:47] wire _s1_did_read_T_33; // @[package.scala:16:47] assign _s1_did_read_T_33 = _GEN_62; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_10; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_10 = _GEN_62; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_33; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_33 = _GEN_62; // @[package.scala:16:47] wire _s0_read_T_11 = _s0_read_T_7 \| _s0_read_T_8; // @[package.scala:16:47, :81:59] wire _s0_read_T_12 = _s0_read_T_11 \| _s0_read_T_9; // @[package.scala:16:47, :81:59] wire _s0_read_T_13 = _s0_read_T_12 \| _s0_read_T_10; // @[package.scala:16:47, :81:59] wire _GEN_63 = io_cpu_req_bits_cmd_0 == 5'h8; // @[package.scala:16:47] wire _s0_read_T_14; // @[package.scala:16:47] assign _s0_read_T_14 = _GEN_63; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_14; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_14 = _GEN_63; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_37; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_37 = _GEN_63; // @[package.scala:16:47] wire _s1_did_read_T_14; // @[package.scala:16:47] assign _s1_did_read_T_14 = _GEN_63; // @[package.scala:16:47] wire _s1_did_read_T_37; // @[package.scala:16:47] assign _s1_did_read_T_37 = _GEN_63; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_14; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_14 = _GEN_63; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_37; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_37 = _GEN_63; // @[package.scala:16:47] wire _GEN_64 = io_cpu_req_bits_cmd_0 == 5'hC; // @[package.scala:16:47] wire _s0_read_T_15; // @[package.scala:16:47] assign _s0_read_T_15 = _GEN_64; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_15; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_15 = _GEN_64; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_38; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_38 = _GEN_64; // @[package.scala:16:47] wire _s1_did_read_T_15; // @[package.scala:16:47] assign _s1_did_read_T_15 = _GEN_64; // @[package.scala:16:47] wire _s1_did_read_T_38; // @[package.scala:16:47] assign _s1_did_read_T_38 = _GEN_64; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_15; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_15 = _GEN_64; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_38; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_38 = _GEN_64; // @[package.scala:16:47] wire _GEN_65 = io_cpu_req_bits_cmd_0 == 5'hD; // @[package.scala:16:47] wire _s0_read_T_16; // @[package.scala:16:47] assign _s0_read_T_16 = _GEN_65; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_16; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_16 = _GEN_65; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_39; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_39 = _GEN_65; // @[package.scala:16:47] wire _s1_did_read_T_16; // @[package.scala:16:47] assign _s1_did_read_T_16 = _GEN_65; // @[package.scala:16:47] wire _s1_did_read_T_39; // @[package.scala:16:47] assign _s1_did_read_T_39 = _GEN_65; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_16; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_16 = _GEN_65; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_39; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_39 = _GEN_65; // @[package.scala:16:47] wire _GEN_66 = io_cpu_req_bits_cmd_0 == 5'hE; // @[package.scala:16:47] wire _s0_read_T_17; // @[package.scala:16:47] assign _s0_read_T_17 = _GEN_66; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_17; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_17 = _GEN_66; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_40; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_40 = _GEN_66; // @[package.scala:16:47] wire _s1_did_read_T_17; // @[package.scala:16:47] assign _s1_did_read_T_17 = _GEN_66; // @[package.scala:16:47] wire _s1_did_read_T_40; // @[package.scala:16:47] assign _s1_did_read_T_40 = _GEN_66; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_17; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_17 = _GEN_66; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_40; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_40 = _GEN_66; // @[package.scala:16:47] wire _GEN_67 = io_cpu_req_bits_cmd_0 == 5'hF; // @[package.scala:16:47] wire _s0_read_T_18; // @[package.scala:16:47] assign _s0_read_T_18 = _GEN_67; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_18; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_18 = _GEN_67; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_41; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_41 = _GEN_67; // @[package.scala:16:47] wire _s1_did_read_T_18; // @[package.scala:16:47] assign _s1_did_read_T_18 = _GEN_67; // @[package.scala:16:47] wire _s1_did_read_T_41; // @[package.scala:16:47] assign _s1_did_read_T_41 = _GEN_67; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_18; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_18 = _GEN_67; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_41; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_41 = _GEN_67; // @[package.scala:16:47] wire _s0_read_T_19 = _s0_read_T_14 \| _s0_read_T_15; // @[package.scala:16:47, :81:59] wire _s0_read_T_20 = _s0_read_T_19 \| _s0_read_T_16; // @[package.scala:16:47, :81:59] wire _s0_read_T_21 = _s0_read_T_20 \| _s0_read_T_17; // @[package.scala:16:47, :81:59] wire _s0_read_T_22 = _s0_read_T_21 \| _s0_read_T_18; // @[package.scala:16:47, :81:59] wire _s0_read_T_23 = _s0_read_T_13 \| _s0_read_T_22; // @[package.scala:81:59] wire s0_read = _s0_read_T_6 \| _s0_read_T_23; // @[package.scala:81:59] wire _GEN_68 = io_cpu_req_bits_cmd_0 == 5'h1; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_res_T; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_res_T = _GEN_68; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_25; // @[Consts.scala:90:32] assign _dataArb_io_in_3_valid_T_25 = _GEN_68; // @[package.scala:16:47] wire _s1_did_read_T_25; // @[Consts.scala:90:32] assign _s1_did_read_T_25 = _GEN_68; // @[package.scala:16:47] wire _pstore_drain_opportunistic_res_T; // @[package.scala:16:47] assign _pstore_drain_opportunistic_res_T = _GEN_68; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_25; // @[Consts.scala:90:32] assign _pstore_drain_opportunistic_T_25 = _GEN_68; // @[package.scala:16:47] wire _GEN_69 = io_cpu_req_bits_cmd_0 == 5'h3; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_res_T_1; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_res_T_1 = _GEN_69; // @[package.scala:16:47] wire _pstore_drain_opportunistic_res_T_1; // @[package.scala:16:47] assign _pstore_drain_opportunistic_res_T_1 = _GEN_69; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_res_T_2 = _dataArb_io_in_3_valid_res_T \| _dataArb_io_in_3_valid_res_T_1; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_res_T_3 = ~_dataArb_io_in_3_valid_res_T_2; // @[package.scala:81:59] wire dataArb_io_in_3_valid_res = _dataArb_io_in_3_valid_res_T_3; // @[DCache.scala:1185:{15,46}] wire _dataArb_io_in_3_valid_T_4 = _dataArb_io_in_3_valid_T \| _dataArb_io_in_3_valid_T_1; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_5 = _dataArb_io_in_3_valid_T_4 \| _dataArb_io_in_3_valid_T_2; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_6 = _dataArb_io_in_3_valid_T_5 \| _dataArb_io_in_3_valid_T_3; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_11 = _dataArb_io_in_3_valid_T_7 \| _dataArb_io_in_3_valid_T_8; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_12 = _dataArb_io_in_3_valid_T_11 \| _dataArb_io_in_3_valid_T_9; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_13 = _dataArb_io_in_3_valid_T_12 \| _dataArb_io_in_3_valid_T_10; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_19 = _dataArb_io_in_3_valid_T_14 \| _dataArb_io_in_3_valid_T_15; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_20 = _dataArb_io_in_3_valid_T_19 \| _dataArb_io_in_3_valid_T_16; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_21 = _dataArb_io_in_3_valid_T_20 \| _dataArb_io_in_3_valid_T_17; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_22 = _dataArb_io_in_3_valid_T_21 \| _dataArb_io_in_3_valid_T_18; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_23 = _dataArb_io_in_3_valid_T_13 \| _dataArb_io_in_3_valid_T_22; // @[package.scala:81:59] wire _dataArb_io_in_3_valid_T_24 = _dataArb_io_in_3_valid_T_6 \| _dataArb_io_in_3_valid_T_23; // @[package.scala:81:59] wire _GEN_70 = io_cpu_req_bits_cmd_0 == 5'h11; // @[DCache.scala:101:7] wire _dataArb_io_in_3_valid_T_26; // @[Consts.scala:90:49] assign _dataArb_io_in_3_valid_T_26 = _GEN_70; // @[Consts.scala:90:49] wire _dataArb_io_in_3_valid_T_48; // @[DCache.scala:1191:35] assign _dataArb_io_in_3_valid_T_48 = _GEN_70; // @[DCache.scala:1191:35] wire _s1_did_read_T_26; // @[Consts.scala:90:49] assign _s1_did_read_T_26 = _GEN_70; // @[Consts.scala:90:49] wire _s1_did_read_T_48; // @[DCache.scala:1191:35] assign _s1_did_read_T_48 = _GEN_70; // @[DCache.scala:1191:35] wire _pstore_drain_opportunistic_T_26; // @[Consts.scala:90:49] assign _pstore_drain_opportunistic_T_26 = _GEN_70; // @[Consts.scala:90:49] wire _pstore_drain_opportunistic_T_48; // @[DCache.scala:1191:35] assign _pstore_drain_opportunistic_T_48 = _GEN_70; // @[DCache.scala:1191:35] wire _dataArb_io_in_3_valid_T_27 = _dataArb_io_in_3_valid_T_25 \| _dataArb_io_in_3_valid_T_26; // @[Consts.scala:90:{32,42,49}] wire _dataArb_io_in_3_valid_T_29 = _dataArb_io_in_3_valid_T_27 \| _dataArb_io_in_3_valid_T_28; // @[Consts.scala:90:{42,59,66}] wire _dataArb_io_in_3_valid_T_34 = _dataArb_io_in_3_valid_T_30 \| _dataArb_io_in_3_valid_T_31; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_35 = _dataArb_io_in_3_valid_T_34 \| _dataArb_io_in_3_valid_T_32; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_36 = _dataArb_io_in_3_valid_T_35 \| _dataArb_io_in_3_valid_T_33; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_42 = _dataArb_io_in_3_valid_T_37 \| _dataArb_io_in_3_valid_T_38; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_43 = _dataArb_io_in_3_valid_T_42 \| _dataArb_io_in_3_valid_T_39; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_44 = _dataArb_io_in_3_valid_T_43 \| _dataArb_io_in_3_valid_T_40; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_45 = _dataArb_io_in_3_valid_T_44 \| _dataArb_io_in_3_valid_T_41; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_46 = _dataArb_io_in_3_valid_T_36 \| _dataArb_io_in_3_valid_T_45; // @[package.scala:81:59] wire _dataArb_io_in_3_valid_T_47 = _dataArb_io_in_3_valid_T_29 \| _dataArb_io_in_3_valid_T_46; // @[Consts.scala:87:44, :90:{59,76}] wire _dataArb_io_in_3_valid_T_50 = _dataArb_io_in_3_valid_T_48; // @[DCache.scala:1191:{35,45}] wire _dataArb_io_in_3_valid_T_51 = _dataArb_io_in_3_valid_T_47 & _dataArb_io_in_3_valid_T_50; // @[DCache.scala:1191:{23,45}] wire _dataArb_io_in_3_valid_T_52 = _dataArb_io_in_3_valid_T_24 \| _dataArb_io_in_3_valid_T_51; // @[DCache.scala:1190:21, :1191:23] wire _dataArb_io_in_3_valid_T_53 = ~_dataArb_io_in_3_valid_T_52; // @[DCache.scala:1186:12, :1190:21] wire _dataArb_io_in_3_valid_T_54 = _dataArb_io_in_3_valid_T_53 \| dataArb_io_in_3_valid_res; // @[DCache.scala:1185:46, :1186:{12,28}] wire _dataArb_io_in_3_valid_T_56 = ~_dataArb_io_in_3_valid_T_55; // @[DCache.scala:1186:11] wire _dataArb_io_in_3_valid_T_57 = ~_dataArb_io_in_3_valid_T_54; // @[DCache.scala:1186:{11,28}] assign _dataArb_io_in_3_valid_T_58 = io_cpu_req_valid_0 & dataArb_io_in_3_valid_res; // @[DCache.scala:101:7, :242:46, :1185:46] assign dataArb_io_in_3_valid = _dataArb_io_in_3_valid_T_58; // @[DCache.scala:152:28, :242:46] wire [19:0] _dataArb_io_in_3_bits_addr_T = io_cpu_req_bits_addr_0[33:14]; // @[DCache.scala:101:7, :245:89] wire [19:0] _metaArb_io_in_1_bits_addr_T = io_cpu_req_bits_addr_0[33:14]; // @[DCache.scala:101:7, :245:89, :454:58] wire [19:0] _metaArb_io_in_2_bits_addr_T = io_cpu_req_bits_addr_0[33:14]; // @[DCache.scala:101:7, :245:89, :466:58] wire [19:0] _metaArb_io_in_3_bits_addr_T = io_cpu_req_bits_addr_0[33:14]; // @[DCache.scala:101:7, :245:89, :745:58] wire [19:0] _metaArb_io_in_4_bits_addr_T = io_cpu_req_bits_addr_0[33:14]; // @[DCache.scala:101:7, :245:89, :912:58] wire [19:0] _metaArb_io_in_5_bits_addr_T = io_cpu_req_bits_addr_0[33:14]; // @[DCache.scala:101:7, :245:89, :1018:58] wire [13:0] _dataArb_io_in_3_bits_addr_T_1 = io_cpu_req_bits_addr_0[13:0]; // @[DCache.scala:101:7, :245:120] wire [33:0] _dataArb_io_in_3_bits_addr_T_2 = {_dataArb_io_in_3_bits_addr_T, _dataArb_io_in_3_bits_addr_T_1}; // @[DCache.scala:245:{36,89,120}] assign dataArb_io_in_3_bits_addr = _dataArb_io_in_3_bits_addr_T_2[13:0]; // @[DCache.scala:152:28, :245:{30,36}] wire _T_4 = ~dataArb_io_in_3_ready & s0_read; // @[DCache.scala:152:28, :258:{9,33}] wire _s1_did_read_T_4 = _s1_did_read_T \| _s1_did_read_T_1; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_5 = _s1_did_read_T_4 \| _s1_did_read_T_2; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_6 = _s1_did_read_T_5 \| _s1_did_read_T_3; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_11 = _s1_did_read_T_7 \| _s1_did_read_T_8; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_12 = _s1_did_read_T_11 \| _s1_did_read_T_9; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_13 = _s1_did_read_T_12 \| _s1_did_read_T_10; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_19 = _s1_did_read_T_14 \| _s1_did_read_T_15; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_20 = _s1_did_read_T_19 \| _s1_did_read_T_16; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_21 = _s1_did_read_T_20 \| _s1_did_read_T_17; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_22 = _s1_did_read_T_21 \| _s1_did_read_T_18; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_23 = _s1_did_read_T_13 \| _s1_did_read_T_22; // @[package.scala:81:59] wire _s1_did_read_T_24 = _s1_did_read_T_6 \| _s1_did_read_T_23; // @[package.scala:81:59] wire _s1_did_read_T_27 = _s1_did_read_T_25 \| _s1_did_read_T_26; // @[Consts.scala:90:{32,42,49}] wire _s1_did_read_T_29 = _s1_did_read_T_27 \| _s1_did_read_T_28; // @[Consts.scala:90:{42,59,66}] wire _s1_did_read_T_34 = _s1_did_read_T_30 \| _s1_did_read_T_31; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_35 = _s1_did_read_T_34 \| _s1_did_read_T_32; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_36 = _s1_did_read_T_35 \| _s1_did_read_T_33; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_42 = _s1_did_read_T_37 \| _s1_did_read_T_38; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_43 = _s1_did_read_T_42 \| _s1_did_read_T_39; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_44 = _s1_did_read_T_43 \| _s1_did_read_T_40; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_45 = _s1_did_read_T_44 \| _s1_did_read_T_41; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_46 = _s1_did_read_T_36 \| _s1_did_read_T_45; // @[package.scala:81:59] wire _s1_did_read_T_47 = _s1_did_read_T_29 \| _s1_did_read_T_46; // @[Consts.scala:87:44, :90:{59,76}] wire _s1_did_read_T_50 = _s1_did_read_T_48; // @[DCache.scala:1191:{35,45}] wire _s1_did_read_T_51 = _s1_did_read_T_47 & _s1_did_read_T_50; // @[DCache.scala:1191:{23,45}] wire _s1_did_read_T_52 = _s1_did_read_T_24 \| _s1_did_read_T_51; // @[DCache.scala:1190:21, :1191:23] wire _s1_did_read_T_53 = io_cpu_req_valid_0 & _s1_did_read_T_52; // @[DCache.scala:101:7, :259:75, :1190:21] wire _s1_did_read_T_54 = dataArb_io_in_3_ready & _s1_did_read_T_53; // @[DCache.scala:152:28, :259:{54,75}] reg s1_did_read; // @[DCache.scala:259:30] wire _s2_data_word_en_T = s1_did_read; // @[DCache.scala:259:30, :367:63] assign _metaArb_io_in_7_bits_idx_T = _dataArb_io_in_3_bits_addr_T_2[13:6]; // @[DCache.scala:245:36, :263:58] assign metaArb_io_in_7_bits_idx = _metaArb_io_in_7_bits_idx_T; // @[DCache.scala:135:28, :263:58] wire _s1_cmd_uses_tlb_T = s1_readwrite \| s1_flush_line; // @[DCache.scala:212:30, :214:50, :270:38] wire _s1_cmd_uses_tlb_T_1 = s1_req_cmd == 5'h17; // @[DCache.scala:196:25, :270:69] wire s1_cmd_uses_tlb = _s1_cmd_uses_tlb_T \| _s1_cmd_uses_tlb_T_1; // @[DCache.scala:270:{38,55,69}] wire _tlb_io_req_valid_T = ~io_cpu_s1_kill_0; // @[DCache.scala:101:7, :186:37, :273:55] wire _tlb_io_req_valid_T_1 = s1_valid & _tlb_io_req_valid_T; // @[DCache.scala:182:25, :273:{52,55}] wire _tlb_io_req_valid_T_2 = _tlb_io_req_valid_T_1 & s1_cmd_uses_tlb; // @[DCache.scala:270:55, :273:{52,71}] wire _tlb_io_req_valid_T_3 = _tlb_io_req_valid_T_2; // @[DCache.scala:273:{40,71}] wire _tlb_io_sfence_valid_T = ~io_cpu_s1_kill_0; // @[DCache.scala:101:7, :186:37, :278:38] wire _tlb_io_sfence_valid_T_1 = s1_valid & _tlb_io_sfence_valid_T; // @[DCache.scala:182:25, :278:{35,38}] wire _tlb_io_sfence_valid_T_2 = _tlb_io_sfence_valid_T_1 & s1_sfence; // @[DCache.scala:213:71, :278:{35,54}] wire _tlb_io_sfence_bits_rs2_T = s1_req_size[1]; // @[DCache.scala:196:25, :280:40] wire [19:0] _s1_paddr_T = s1_req_addr[31:12]; // @[DCache.scala:196:25, :298:55] wire [19:0] _s1_paddr_T_1 = _tlb_io_resp_paddr[31:12]; // @[DCache.scala:119:19, :298:99] wire [19:0] _s1_paddr_T_2 = _s1_paddr_T_1; // @[DCache.scala:298:{25,99}] wire [11:0] _s1_paddr_T_3 = s1_req_addr[11:0]; // @[DCache.scala:196:25, :298:125] wire [31:0] s1_paddr = {_s1_paddr_T_2, _s1_paddr_T_3}; // @[DCache.scala:298:{21,25,125}] wire _baseAddr_T = ~hartIdSinkNodeOptIn; // @[LookupByHartId.scala:18:71] wire _inScratchpad_T = s1_paddr[31]; // @[DCache.scala:298:21, :303:35] wire _inScratchpad_T_3 = s1_paddr < 32'h80004000; // @[DCache.scala:298:21, :303:59] wire s1_hit_way = _inScratchpad_T & _inScratchpad_T_3; // @[DCache.scala:303:{35,47,59}] wire [1:0] s1_hit_state_state = {2{s1_hit_way}}; // @[DCache.scala:303:47, :304:25] wire [1:0] s1_data_way; // @[DCache.scala:323:32] wire [7:0] _tl_d_data_encoded_T = nodeOut_d_bits_data[7:0]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_14 = nodeOut_d_bits_data[7:0]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_1 = nodeOut_d_bits_data[15:8]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_15 = nodeOut_d_bits_data[15:8]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_2 = nodeOut_d_bits_data[23:16]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_16 = nodeOut_d_bits_data[23:16]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_3 = nodeOut_d_bits_data[31:24]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_17 = nodeOut_d_bits_data[31:24]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_4 = nodeOut_d_bits_data[39:32]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_18 = nodeOut_d_bits_data[39:32]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_5 = nodeOut_d_bits_data[47:40]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_19 = nodeOut_d_bits_data[47:40]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_6 = nodeOut_d_bits_data[55:48]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_20 = nodeOut_d_bits_data[55:48]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_7 = nodeOut_d_bits_data[63:56]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_21 = nodeOut_d_bits_data[63:56]; // @[package.scala:211:50] wire [15:0] tl_d_data_encoded_lo_lo = {_tl_d_data_encoded_T_1, _tl_d_data_encoded_T}; // @[package.scala:45:27, :211:50] wire [15:0] tl_d_data_encoded_lo_hi = {_tl_d_data_encoded_T_3, _tl_d_data_encoded_T_2}; // @[package.scala:45:27, :211:50] wire [31:0] tl_d_data_encoded_lo = {tl_d_data_encoded_lo_hi, tl_d_data_encoded_lo_lo}; // @[package.scala:45:27] wire [15:0] tl_d_data_encoded_hi_lo = {_tl_d_data_encoded_T_5, _tl_d_data_encoded_T_4}; // @[package.scala:45:27, :211:50] wire [15:0] tl_d_data_encoded_hi_hi = {_tl_d_data_encoded_T_7, _tl_d_data_encoded_T_6}; // @[package.scala:45:27, :211:50] wire [31:0] tl_d_data_encoded_hi = {tl_d_data_encoded_hi_hi, tl_d_data_encoded_hi_lo}; // @[package.scala:45:27] wire [63:0] _tl_d_data_encoded_T_8 = {tl_d_data_encoded_hi, tl_d_data_encoded_lo}; // @[package.scala:45:27] wire [63:0] _tl_d_data_encoded_T_22; // @[package.scala:45:27] wire [63:0] tl_d_data_encoded; // @[DCache.scala:324:31] wire [63:0] s1_all_data_ways_1 = tl_d_data_encoded; // @[DCache.scala:324:31, :325:33] wire [63:0] s2_data_s1_way_words_0_0 = s1_all_data_ways_0; // @[package.scala:211:50] wire [63:0] s2_data_s1_way_words_1_0 = s1_all_data_ways_1; // @[package.scala:211:50] wire _s1_mask_xwr_upper_T = s1_req_addr[0]; // @[DCache.scala:196:25] wire _s1_mask_xwr_lower_T = s1_req_addr[0]; // @[DCache.scala:196:25] wire _s1_mask_xwr_upper_T_1 = _s1_mask_xwr_upper_T; // @[AMOALU.scala:20:{22,27}] wire _s1_mask_xwr_upper_T_2 = \|s1_mask_xwr_size; // @[AMOALU.scala:11:18, :20:53] wire _s1_mask_xwr_upper_T_3 = _s1_mask_xwr_upper_T_2; // @[AMOALU.scala:20:{47,53}] wire s1_mask_xwr_upper = _s1_mask_xwr_upper_T_1 \| _s1_mask_xwr_upper_T_3; // @[AMOALU.scala:20:{22,42,47}] wire s1_mask_xwr_lower = ~_s1_mask_xwr_lower_T; // @[AMOALU.scala:21:{22,27}] wire [1:0] _s1_mask_xwr_T = {s1_mask_xwr_upper, s1_mask_xwr_lower}; // @[AMOALU.scala:20:42, :21:22, :22:16] wire _s1_mask_xwr_upper_T_4 = s1_req_addr[1]; // @[DCache.scala:196:25] wire _s1_mask_xwr_lower_T_1 = s1_req_addr[1]; // @[DCache.scala:196:25] wire [1:0] _s1_mask_xwr_upper_T_5 = _s1_mask_xwr_upper_T_4 ? _s1_mask_xwr_T : 2'h0; // @[AMOALU.scala:20:{22,27}, :22:16] wire _s1_mask_xwr_upper_T_6 = s1_mask_xwr_size[1]; // @[AMOALU.scala:11:18, :20:53] wire [1:0] _s1_mask_xwr_upper_T_7 = {2{_s1_mask_xwr_upper_T_6}}; // @[AMOALU.scala:20:{47,53}] wire [1:0] s1_mask_xwr_upper_1 = _s1_mask_xwr_upper_T_5 \| _s1_mask_xwr_upper_T_7; // @[AMOALU.scala:20:{22,42,47}] wire [1:0] s1_mask_xwr_lower_1 = _s1_mask_xwr_lower_T_1 ? 2'h0 : _s1_mask_xwr_T; // @[AMOALU.scala:21:{22,27}, :22:16] wire [3:0] _s1_mask_xwr_T_1 = {s1_mask_xwr_upper_1, s1_mask_xwr_lower_1}; // @[AMOALU.scala:20:42, :21:22, :22:16] wire _s1_mask_xwr_upper_T_8 = s1_req_addr[2]; // @[DCache.scala:196:25] wire _s1_mask_xwr_lower_T_2 = s1_req_addr[2]; // @[DCache.scala:196:25] wire [3:0] _s1_mask_xwr_upper_T_9 = _s1_mask_xwr_upper_T_8 ? _s1_mask_xwr_T_1 : 4'h0; // @[AMOALU.scala:20:{22,27}, :22:16] wire _s1_mask_xwr_upper_T_10 = &s1_mask_xwr_size; // @[AMOALU.scala:11:18, :20:53] wire [3:0] _s1_mask_xwr_upper_T_11 = {4{_s1_mask_xwr_upper_T_10}}; // @[AMOALU.scala:20:{47,53}] wire [3:0] s1_mask_xwr_upper_2 = _s1_mask_xwr_upper_T_9 \| _s1_mask_xwr_upper_T_11; // @[AMOALU.scala:20:{22,42,47}] wire [3:0] s1_mask_xwr_lower_2 = _s1_mask_xwr_lower_T_2 ? 4'h0 : _s1_mask_xwr_T_1; // @[AMOALU.scala:21:{22,27}, :22:16] wire [7:0] s1_mask_xwr = {s1_mask_xwr_upper_2, s1_mask_xwr_lower_2}; // @[AMOALU.scala:20:42, :21:22, :22:16] wire [7:0] s1_mask = _s1_mask_T ? io_cpu_s1_data_mask_0 : s1_mask_xwr; // @[DCache.scala:101:7, :327:{20,32}] wire _s2_valid_T = ~s1_sfence; // @[DCache.scala:213:71, :331:45] wire _s2_valid_T_1 = s1_valid_masked & _s2_valid_T; // @[DCache.scala:186:34, :331:{42,45}] reg s2_valid; // @[DCache.scala:331:25] wire [1:0] _s2_valid_no_xcpt_T = {io_cpu_s2_xcpt_ae_ld_0, io_cpu_s2_xcpt_ae_st_0}; // @[DCache.scala:101:7, :332:54] wire [1:0] _s2_valid_no_xcpt_T_2 = {io_cpu_s2_xcpt_pf_ld_0, io_cpu_s2_xcpt_pf_st_0}; // @[DCache.scala:101:7, :332:54] wire [1:0] _s2_valid_no_xcpt_T_3 = {io_cpu_s2_xcpt_ma_ld_0, io_cpu_s2_xcpt_ma_st_0}; // @[DCache.scala:101:7, :332:54] wire [3:0] s2_valid_no_xcpt_lo = {2'h0, _s2_valid_no_xcpt_T}; // @[DCache.scala:332:54] wire [3:0] s2_valid_no_xcpt_hi = {_s2_valid_no_xcpt_T_3, _s2_valid_no_xcpt_T_2}; // @[DCache.scala:332:54] wire [7:0] _s2_valid_no_xcpt_T_4 = {s2_valid_no_xcpt_hi, s2_valid_no_xcpt_lo}; // @[DCache.scala:332:54] wire _s2_valid_no_xcpt_T_5 = \|_s2_valid_no_xcpt_T_4; // @[DCache.scala:332:{54,61}] wire _s2_valid_no_xcpt_T_6 = ~_s2_valid_no_xcpt_T_5; // @[DCache.scala:332:{38,61}] wire s2_valid_no_xcpt = s2_valid & _s2_valid_no_xcpt_T_6; // @[DCache.scala:331:25, :332:{35,38}] wire _s2_not_nacked_in_s1_T = ~s1_nack; // @[DCache.scala:185:28, :187:41, :335:37] reg s2_not_nacked_in_s1; // @[DCache.scala:335:36] wire s2_valid_not_nacked_in_s1 = s2_valid & s2_not_nacked_in_s1; // @[DCache.scala:331:25, :335:36, :336:44] wire s2_valid_masked = s2_valid_no_xcpt & s2_not_nacked_in_s1; // @[DCache.scala:332:35, :335:36, :337:42] wire s2_valid_not_killed = s2_valid_masked; // @[DCache.scala:337:42, :338:45] wire _s2_valid_hit_maybe_flush_pre_data_ecc_and_waw_T_1 = s2_valid_masked; // @[DCache.scala:337:42, :397:71] wire _s2_dont_nack_misc_T_1 = s2_valid_masked; // @[DCache.scala:337:42, :441:43] reg [33:0] s2_req_addr; // @[DCache.scala:339:19] wire [33:0] _get_legal_T_14 = s2_req_addr; // @[DCache.scala:339:19] wire [33:0] _put_legal_T_14 = s2_req_addr; // @[DCache.scala:339:19] wire [33:0] _putpartial_legal_T_14 = s2_req_addr; // @[DCache.scala:339:19] wire [33:0] _atomics_legal_T_4 = s2_req_addr; // @[DCache.scala:339:19] wire [33:0] _atomics_legal_T_34 = s2_req_addr; // @[DCache.scala:339:19] wire [33:0] _atomics_legal_T_64 = s2_req_addr; // @[DCache.scala:339:19] wire [33:0] _atomics_legal_T_94 = s2_req_addr; // @[DCache.scala:339:19] wire [33:0] _atomics_legal_T_124 = s2_req_addr; // @[DCache.scala:339:19] wire [33:0] _atomics_legal_T_154 = s2_req_addr; // @[DCache.scala:339:19] wire [33:0] _atomics_legal_T_184 = s2_req_addr; // @[DCache.scala:339:19] wire [33:0] _atomics_legal_T_214 = s2_req_addr; // @[DCache.scala:339:19] wire [33:0] _atomics_legal_T_244 = s2_req_addr; // @[DCache.scala:339:19] wire [33:0] _tl_out_a_valid_T_1 = s2_req_addr; // @[DCache.scala:339:19, :606:43] reg [6:0] s2_req_tag; // @[DCache.scala:339:19] assign io_cpu_resp_bits_tag_0 = s2_req_tag; // @[DCache.scala:101:7, :339:19] reg [4:0] s2_req_cmd; // @[DCache.scala:339:19] assign io_cpu_resp_bits_cmd_0 = s2_req_cmd; // @[DCache.scala:101:7, :339:19] reg [1:0] s2_req_size; // @[DCache.scala:339:19] assign io_cpu_resp_bits_size_0 = s2_req_size; // @[DCache.scala:101:7, :339:19] wire [1:0] size = s2_req_size; // @[DCache.scala:339:19] reg s2_req_signed; // @[DCache.scala:339:19] assign io_cpu_resp_bits_signed_0 = s2_req_signed; // @[DCache.scala:101:7, :339:19] reg [1:0] s2_req_dprv; // @[DCache.scala:339:19] assign io_cpu_resp_bits_dprv_0 = s2_req_dprv; // @[DCache.scala:101:7, :339:19] reg s2_req_dv; // @[DCache.scala:339:19] assign io_cpu_resp_bits_dv_0 = s2_req_dv; // @[DCache.scala:101:7, :339:19] reg s2_req_phys; // @[DCache.scala:339:19] reg s2_req_no_resp; // @[DCache.scala:339:19] reg s2_req_no_alloc; // @[DCache.scala:339:19] reg s2_req_no_xcpt; // @[DCache.scala:339:19] reg [63:0] s2_req_data; // @[DCache.scala:339:19] reg [7:0] s2_req_mask; // @[DCache.scala:339:19] assign io_cpu_resp_bits_mask_0 = s2_req_mask; // @[DCache.scala:101:7, :339:19] wire _GEN_71 = s2_req_cmd == 5'h5; // @[DCache.scala:339:19, :340:37] wire _s2_cmd_flush_all_T; // @[DCache.scala:340:37] assign _s2_cmd_flush_all_T = _GEN_71; // @[DCache.scala:340:37] wire _s2_cmd_flush_line_T; // @[DCache.scala:341:38] assign _s2_cmd_flush_line_T = _GEN_71; // @[DCache.scala:340:37, :341:38] wire _s2_cmd_flush_all_T_1 = s2_req_size[0]; // @[DCache.scala:339:19, :340:68] wire _s2_cmd_flush_line_T_1 = s2_req_size[0]; // @[DCache.scala:339:19, :340:68, :341:68] wire _s2_cmd_flush_all_T_2 = ~_s2_cmd_flush_all_T_1; // @[DCache.scala:340:{56,68}] wire s2_cmd_flush_all = _s2_cmd_flush_all_T & _s2_cmd_flush_all_T_2; // @[DCache.scala:340:{37,53,56}] wire s2_cmd_flush_line = _s2_cmd_flush_line_T & _s2_cmd_flush_line_T_1; // @[DCache.scala:341:{38,54,68}] reg [31:0] s2_tlb_xcpt_paddr; // @[DCache.scala:342:24] reg [33:0] s2_tlb_xcpt_gpa; // @[DCache.scala:342:24] assign io_cpu_s2_gpa_0 = s2_tlb_xcpt_gpa; // @[DCache.scala:101:7, :342:24] reg s2_tlb_xcpt_pf_ld; // @[DCache.scala:342:24] reg s2_tlb_xcpt_pf_st; // @[DCache.scala:342:24] reg s2_tlb_xcpt_pf_inst; // @[DCache.scala:342:24] reg s2_tlb_xcpt_ae_ld; // @[DCache.scala:342:24] reg s2_tlb_xcpt_ae_st; // @[DCache.scala:342:24] reg s2_tlb_xcpt_ae_inst; // @[DCache.scala:342:24] reg s2_tlb_xcpt_ma_ld; // @[DCache.scala:342:24] reg s2_tlb_xcpt_ma_st; // @[DCache.scala:342:24] reg s2_tlb_xcpt_cacheable; // @[DCache.scala:342:24] reg s2_tlb_xcpt_must_alloc; // @[DCache.scala:342:24] reg s2_tlb_xcpt_prefetchable; // @[DCache.scala:342:24] reg [1:0] s2_tlb_xcpt_size; // @[DCache.scala:342:24] reg [4:0] s2_tlb_xcpt_cmd; // @[DCache.scala:342:24] reg [31:0] s2_pma_paddr; // @[DCache.scala:343:19] reg [33:0] s2_pma_gpa; // @[DCache.scala:343:19] reg s2_pma_pf_ld; // @[DCache.scala:343:19] reg s2_pma_pf_st; // @[DCache.scala:343:19] reg s2_pma_pf_inst; // @[DCache.scala:343:19] reg s2_pma_ae_ld; // @[DCache.scala:343:19] reg s2_pma_ae_st; // @[DCache.scala:343:19] reg s2_pma_ae_inst; // @[DCache.scala:343:19] reg s2_pma_ma_ld; // @[DCache.scala:343:19] reg s2_pma_ma_st; // @[DCache.scala:343:19] reg s2_pma_cacheable; // @[DCache.scala:343:19] reg s2_pma_must_alloc; // @[DCache.scala:343:19] reg s2_pma_prefetchable; // @[DCache.scala:343:19] reg [1:0] s2_pma_size; // @[DCache.scala:343:19] reg [4:0] s2_pma_cmd; // @[DCache.scala:343:19] reg [33:0] s2_uncached_resp_addr; // @[DCache.scala:344:34] wire _T_29 = s1_valid_not_nacked \| s1_flush_valid; // @[DCache.scala:187:38, :215:27, :345:29] wire _s2_vaddr_T; // @[DCache.scala:351:62] assign _s2_vaddr_T = _T_29; // @[DCache.scala:345:29, :351:62] wire _s1_meta_clk_en_T; // @[DCache.scala:357:44] assign _s1_meta_clk_en_T = _T_29; // @[DCache.scala:345:29, :357:44] wire _s2_hit_state_T; // @[DCache.scala:386:66] assign _s2_hit_state_T = _T_29; // @[DCache.scala:345:29, :386:66] wire _s2_victim_way_T; // @[DCache.scala:431:77] assign _s2_victim_way_T = _T_29; // @[DCache.scala:345:29, :431:77] reg [33:0] s2_vaddr_r; // @[DCache.scala:351:31] wire [19:0] _s2_vaddr_T_1 = s2_vaddr_r[33:14]; // @[DCache.scala:351:{31,81}] wire [13:0] _s2_vaddr_T_2 = s2_req_addr[13:0]; // @[DCache.scala:339:19, :351:103] wire [33:0] s2_vaddr = {_s2_vaddr_T_1, _s2_vaddr_T_2}; // @[DCache.scala:351:{21,81,103}] wire _s2_read_T = s2_req_cmd == 5'h0; // @[package.scala:16:47] wire _s2_read_T_1 = s2_req_cmd == 5'h10; // @[package.scala:16:47] wire _T_110 = s2_req_cmd == 5'h6; // @[package.scala:16:47] wire _s2_read_T_2; // @[package.scala:16:47] assign _s2_read_T_2 = _T_110; // @[package.scala:16:47] wire _r_c_cat_T_48; // @[Consts.scala:91:71] assign _r_c_cat_T_48 = _T_110; // @[package.scala:16:47] wire _s2_lr_T; // @[DCache.scala:470:70] assign _s2_lr_T = _T_110; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_48; // @[Consts.scala:91:71] assign _metaArb_io_in_3_bits_data_c_cat_T_48 = _T_110; // @[package.scala:16:47] wire _T_111 = s2_req_cmd == 5'h7; // @[package.scala:16:47] wire _s2_read_T_3; // @[package.scala:16:47] assign _s2_read_T_3 = _T_111; // @[package.scala:16:47] wire _s2_write_T_3; // @[Consts.scala:90:66] assign _s2_write_T_3 = _T_111; // @[package.scala:16:47] wire _r_c_cat_T_3; // @[Consts.scala:90:66] assign _r_c_cat_T_3 = _T_111; // @[package.scala:16:47] wire _r_c_cat_T_26; // @[Consts.scala:90:66] assign _r_c_cat_T_26 = _T_111; // @[package.scala:16:47] wire _s2_sc_T; // @[DCache.scala:471:70] assign _s2_sc_T = _T_111; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_3; // @[Consts.scala:90:66] assign _metaArb_io_in_3_bits_data_c_cat_T_3 = _T_111; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_26; // @[Consts.scala:90:66] assign _metaArb_io_in_3_bits_data_c_cat_T_26 = _T_111; // @[package.scala:16:47] wire _io_cpu_store_pending_T_3; // @[Consts.scala:90:66] assign _io_cpu_store_pending_T_3 = _T_111; // @[package.scala:16:47] wire _s2_read_T_4 = _s2_read_T \| _s2_read_T_1; // @[package.scala:16:47, :81:59] wire _s2_read_T_5 = _s2_read_T_4 \| _s2_read_T_2; // @[package.scala:16:47, :81:59] wire _s2_read_T_6 = _s2_read_T_5 \| _s2_read_T_3; // @[package.scala:16:47, :81:59] wire _GEN_72 = s2_req_cmd == 5'h4; // @[package.scala:16:47] wire _s2_read_T_7; // @[package.scala:16:47] assign _s2_read_T_7 = _GEN_72; // @[package.scala:16:47] wire _s2_write_T_5; // @[package.scala:16:47] assign _s2_write_T_5 = _GEN_72; // @[package.scala:16:47] wire _r_c_cat_T_5; // @[package.scala:16:47] assign _r_c_cat_T_5 = _GEN_72; // @[package.scala:16:47] wire _r_c_cat_T_28; // @[package.scala:16:47] assign _r_c_cat_T_28 = _GEN_72; // @[package.scala:16:47] wire _atomics_T; // @[DCache.scala:587:81] assign _atomics_T = _GEN_72; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_5; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_5 = _GEN_72; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_28; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_28 = _GEN_72; // @[package.scala:16:47] wire _io_cpu_store_pending_T_5; // @[package.scala:16:47] assign _io_cpu_store_pending_T_5 = _GEN_72; // @[package.scala:16:47] wire _GEN_73 = s2_req_cmd == 5'h9; // @[package.scala:16:47] wire _s2_read_T_8; // @[package.scala:16:47] assign _s2_read_T_8 = _GEN_73; // @[package.scala:16:47] wire _s2_write_T_6; // @[package.scala:16:47] assign _s2_write_T_6 = _GEN_73; // @[package.scala:16:47] wire _r_c_cat_T_6; // @[package.scala:16:47] assign _r_c_cat_T_6 = _GEN_73; // @[package.scala:16:47] wire _r_c_cat_T_29; // @[package.scala:16:47] assign _r_c_cat_T_29 = _GEN_73; // @[package.scala:16:47] wire _atomics_T_2; // @[DCache.scala:587:81] assign _atomics_T_2 = _GEN_73; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_6; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_6 = _GEN_73; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_29; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_29 = _GEN_73; // @[package.scala:16:47] wire _io_cpu_store_pending_T_6; // @[package.scala:16:47] assign _io_cpu_store_pending_T_6 = _GEN_73; // @[package.scala:16:47] wire _GEN_74 = s2_req_cmd == 5'hA; // @[package.scala:16:47] wire _s2_read_T_9; // @[package.scala:16:47] assign _s2_read_T_9 = _GEN_74; // @[package.scala:16:47] wire _s2_write_T_7; // @[package.scala:16:47] assign _s2_write_T_7 = _GEN_74; // @[package.scala:16:47] wire _r_c_cat_T_7; // @[package.scala:16:47] assign _r_c_cat_T_7 = _GEN_74; // @[package.scala:16:47] wire _r_c_cat_T_30; // @[package.scala:16:47] assign _r_c_cat_T_30 = _GEN_74; // @[package.scala:16:47] wire _atomics_T_4; // @[DCache.scala:587:81] assign _atomics_T_4 = _GEN_74; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_7; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_7 = _GEN_74; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_30; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_30 = _GEN_74; // @[package.scala:16:47] wire _io_cpu_store_pending_T_7; // @[package.scala:16:47] assign _io_cpu_store_pending_T_7 = _GEN_74; // @[package.scala:16:47] wire _GEN_75 = s2_req_cmd == 5'hB; // @[package.scala:16:47] wire _s2_read_T_10; // @[package.scala:16:47] assign _s2_read_T_10 = _GEN_75; // @[package.scala:16:47] wire _s2_write_T_8; // @[package.scala:16:47] assign _s2_write_T_8 = _GEN_75; // @[package.scala:16:47] wire _r_c_cat_T_8; // @[package.scala:16:47] assign _r_c_cat_T_8 = _GEN_75; // @[package.scala:16:47] wire _r_c_cat_T_31; // @[package.scala:16:47] assign _r_c_cat_T_31 = _GEN_75; // @[package.scala:16:47] wire _atomics_T_6; // @[DCache.scala:587:81] assign _atomics_T_6 = _GEN_75; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_8; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_8 = _GEN_75; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_31; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_31 = _GEN_75; // @[package.scala:16:47] wire _io_cpu_store_pending_T_8; // @[package.scala:16:47] assign _io_cpu_store_pending_T_8 = _GEN_75; // @[package.scala:16:47] wire _s2_read_T_11 = _s2_read_T_7 \| _s2_read_T_8; // @[package.scala:16:47, :81:59] wire _s2_read_T_12 = _s2_read_T_11 \| _s2_read_T_9; // @[package.scala:16:47, :81:59] wire _s2_read_T_13 = _s2_read_T_12 \| _s2_read_T_10; // @[package.scala:16:47, :81:59] wire _GEN_76 = s2_req_cmd == 5'h8; // @[package.scala:16:47] wire _s2_read_T_14; // @[package.scala:16:47] assign _s2_read_T_14 = _GEN_76; // @[package.scala:16:47] wire _s2_write_T_12; // @[package.scala:16:47] assign _s2_write_T_12 = _GEN_76; // @[package.scala:16:47] wire _r_c_cat_T_12; // @[package.scala:16:47] assign _r_c_cat_T_12 = _GEN_76; // @[package.scala:16:47] wire _r_c_cat_T_35; // @[package.scala:16:47] assign _r_c_cat_T_35 = _GEN_76; // @[package.scala:16:47] wire _atomics_T_8; // @[DCache.scala:587:81] assign _atomics_T_8 = _GEN_76; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_12; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_12 = _GEN_76; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_35; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_35 = _GEN_76; // @[package.scala:16:47] wire _io_cpu_store_pending_T_12; // @[package.scala:16:47] assign _io_cpu_store_pending_T_12 = _GEN_76; // @[package.scala:16:47] wire _GEN_77 = s2_req_cmd == 5'hC; // @[package.scala:16:47] wire _s2_read_T_15; // @[package.scala:16:47] assign _s2_read_T_15 = _GEN_77; // @[package.scala:16:47] wire _s2_write_T_13; // @[package.scala:16:47] assign _s2_write_T_13 = _GEN_77; // @[package.scala:16:47] wire _r_c_cat_T_13; // @[package.scala:16:47] assign _r_c_cat_T_13 = _GEN_77; // @[package.scala:16:47] wire _r_c_cat_T_36; // @[package.scala:16:47] assign _r_c_cat_T_36 = _GEN_77; // @[package.scala:16:47] wire _atomics_T_10; // @[DCache.scala:587:81] assign _atomics_T_10 = _GEN_77; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_13; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_13 = _GEN_77; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_36; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_36 = _GEN_77; // @[package.scala:16:47] wire _io_cpu_store_pending_T_13; // @[package.scala:16:47] assign _io_cpu_store_pending_T_13 = _GEN_77; // @[package.scala:16:47] wire _GEN_78 = s2_req_cmd == 5'hD; // @[package.scala:16:47] wire _s2_read_T_16; // @[package.scala:16:47] assign _s2_read_T_16 = _GEN_78; // @[package.scala:16:47] wire _s2_write_T_14; // @[package.scala:16:47] assign _s2_write_T_14 = _GEN_78; // @[package.scala:16:47] wire _r_c_cat_T_14; // @[package.scala:16:47] assign _r_c_cat_T_14 = _GEN_78; // @[package.scala:16:47] wire _r_c_cat_T_37; // @[package.scala:16:47] assign _r_c_cat_T_37 = _GEN_78; // @[package.scala:16:47] wire _atomics_T_12; // @[DCache.scala:587:81] assign _atomics_T_12 = _GEN_78; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_14; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_14 = _GEN_78; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_37; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_37 = _GEN_78; // @[package.scala:16:47] wire _io_cpu_store_pending_T_14; // @[package.scala:16:47] assign _io_cpu_store_pending_T_14 = _GEN_78; // @[package.scala:16:47] wire _GEN_79 = s2_req_cmd == 5'hE; // @[package.scala:16:47] wire _s2_read_T_17; // @[package.scala:16:47] assign _s2_read_T_17 = _GEN_79; // @[package.scala:16:47] wire _s2_write_T_15; // @[package.scala:16:47] assign _s2_write_T_15 = _GEN_79; // @[package.scala:16:47] wire _r_c_cat_T_15; // @[package.scala:16:47] assign _r_c_cat_T_15 = _GEN_79; // @[package.scala:16:47] wire _r_c_cat_T_38; // @[package.scala:16:47] assign _r_c_cat_T_38 = _GEN_79; // @[package.scala:16:47] wire _atomics_T_14; // @[DCache.scala:587:81] assign _atomics_T_14 = _GEN_79; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_15; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_15 = _GEN_79; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_38; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_38 = _GEN_79; // @[package.scala:16:47] wire _io_cpu_store_pending_T_15; // @[package.scala:16:47] assign _io_cpu_store_pending_T_15 = _GEN_79; // @[package.scala:16:47] wire _GEN_80 = s2_req_cmd == 5'hF; // @[package.scala:16:47] wire _s2_read_T_18; // @[package.scala:16:47] assign _s2_read_T_18 = _GEN_80; // @[package.scala:16:47] wire _s2_write_T_16; // @[package.scala:16:47] assign _s2_write_T_16 = _GEN_80; // @[package.scala:16:47] wire _r_c_cat_T_16; // @[package.scala:16:47] assign _r_c_cat_T_16 = _GEN_80; // @[package.scala:16:47] wire _r_c_cat_T_39; // @[package.scala:16:47] assign _r_c_cat_T_39 = _GEN_80; // @[package.scala:16:47] wire _atomics_T_16; // @[DCache.scala:587:81] assign _atomics_T_16 = _GEN_80; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_16; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_16 = _GEN_80; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_39; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_39 = _GEN_80; // @[package.scala:16:47] wire _io_cpu_store_pending_T_16; // @[package.scala:16:47] assign _io_cpu_store_pending_T_16 = _GEN_80; // @[package.scala:16:47] wire _s2_read_T_19 = _s2_read_T_14 \| _s2_read_T_15; // @[package.scala:16:47, :81:59] wire _s2_read_T_20 = _s2_read_T_19 \| _s2_read_T_16; // @[package.scala:16:47, :81:59] wire _s2_read_T_21 = _s2_read_T_20 \| _s2_read_T_17; // @[package.scala:16:47, :81:59] wire _s2_read_T_22 = _s2_read_T_21 \| _s2_read_T_18; // @[package.scala:16:47, :81:59] wire _s2_read_T_23 = _s2_read_T_13 \| _s2_read_T_22; // @[package.scala:81:59] assign s2_read = _s2_read_T_6 \| _s2_read_T_23; // @[package.scala:81:59] assign io_cpu_resp_bits_has_data_0 = s2_read; // @[DCache.scala:101:7] wire _GEN_81 = s2_req_cmd == 5'h1; // @[DCache.scala:339:19] wire _s2_write_T; // @[Consts.scala:90:32] assign _s2_write_T = _GEN_81; // @[Consts.scala:90:32] wire _r_c_cat_T; // @[Consts.scala:90:32] assign _r_c_cat_T = _GEN_81; // @[Consts.scala:90:32] wire _r_c_cat_T_23; // @[Consts.scala:90:32] assign _r_c_cat_T_23 = _GEN_81; // @[Consts.scala:90:32] wire _metaArb_io_in_3_bits_data_c_cat_T; // @[Consts.scala:90:32] assign _metaArb_io_in_3_bits_data_c_cat_T = _GEN_81; // @[Consts.scala:90:32] wire _metaArb_io_in_3_bits_data_c_cat_T_23; // @[Consts.scala:90:32] assign _metaArb_io_in_3_bits_data_c_cat_T_23 = _GEN_81; // @[Consts.scala:90:32] wire _io_cpu_store_pending_T; // @[Consts.scala:90:32] assign _io_cpu_store_pending_T = _GEN_81; // @[Consts.scala:90:32] wire _GEN_82 = s2_req_cmd == 5'h11; // @[DCache.scala:339:19] wire _s2_write_T_1; // @[Consts.scala:90:49] assign _s2_write_T_1 = _GEN_82; // @[Consts.scala:90:49] wire _r_c_cat_T_1; // @[Consts.scala:90:49] assign _r_c_cat_T_1 = _GEN_82; // @[Consts.scala:90:49] wire _r_c_cat_T_24; // @[Consts.scala:90:49] assign _r_c_cat_T_24 = _GEN_82; // @[Consts.scala:90:49] wire _tl_out_a_bits_T_2; // @[DCache.scala:610:20] assign _tl_out_a_bits_T_2 = _GEN_82; // @[DCache.scala:610:20] wire _uncachedReqs_0_cmd_T; // @[DCache.scala:637:49] assign _uncachedReqs_0_cmd_T = _GEN_82; // @[DCache.scala:637:49] wire _metaArb_io_in_3_bits_data_c_cat_T_1; // @[Consts.scala:90:49] assign _metaArb_io_in_3_bits_data_c_cat_T_1 = _GEN_82; // @[Consts.scala:90:49] wire _metaArb_io_in_3_bits_data_c_cat_T_24; // @[Consts.scala:90:49] assign _metaArb_io_in_3_bits_data_c_cat_T_24 = _GEN_82; // @[Consts.scala:90:49] wire _io_cpu_store_pending_T_1; // @[Consts.scala:90:49] assign _io_cpu_store_pending_T_1 = _GEN_82; // @[Consts.scala:90:49] wire _s2_write_T_2 = _s2_write_T \| _s2_write_T_1; // @[Consts.scala:90:{32,42,49}] wire _s2_write_T_4 = _s2_write_T_2 \| _s2_write_T_3; // @[Consts.scala:90:{42,59,66}] wire _s2_write_T_9 = _s2_write_T_5 \| _s2_write_T_6; // @[package.scala:16:47, :81:59] wire _s2_write_T_10 = _s2_write_T_9 \| _s2_write_T_7; // @[package.scala:16:47, :81:59] wire _s2_write_T_11 = _s2_write_T_10 \| _s2_write_T_8; // @[package.scala:16:47, :81:59] wire _s2_write_T_17 = _s2_write_T_12 \| _s2_write_T_13; // @[package.scala:16:47, :81:59] wire _s2_write_T_18 = _s2_write_T_17 \| _s2_write_T_14; // @[package.scala:16:47, :81:59] wire _s2_write_T_19 = _s2_write_T_18 \| _s2_write_T_15; // @[package.scala:16:47, :81:59] wire _s2_write_T_20 = _s2_write_T_19 \| _s2_write_T_16; // @[package.scala:16:47, :81:59] wire _s2_write_T_21 = _s2_write_T_11 \| _s2_write_T_20; // @[package.scala:81:59] wire s2_write = _s2_write_T_4 \| _s2_write_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire s2_readwrite = s2_read \| s2_write; // @[DCache.scala:354:30] reg s2_flush_valid_pre_tag_ecc; // @[DCache.scala:355:43] wire s2_flush_valid = s2_flush_valid_pre_tag_ecc; // @[DCache.scala:355:43, :363:51] wire s1_meta_clk_en = _s1_meta_clk_en_T; // @[DCache.scala:357:{44,62}] wire s2_data_en = _s2_data_en_T \| io_cpu_replay_next_0; // @[DCache.scala:101:7, :366:{23,38}] wire s2_data_word_en = _s2_data_word_en_T; // @[DCache.scala:367:{22,63}] wire _s2_data_s1_word_en_T = ~io_cpu_replay_next_0; // @[DCache.scala:101:7, :377:28] wire s2_data_s1_word_en = ~_s2_data_s1_word_en_T \| s2_data_word_en; // @[DCache.scala:367:22, :377:{27,28}] wire _s2_data_T = s2_data_s1_word_en; // @[DCache.scala:377:27, :379:39] wire [1:0] _s2_data_T_1 = _s2_data_T ? s1_data_way : 2'h0; // @[DCache.scala:323:32, :379:{28,39}] wire _s2_data_T_2 = _s2_data_T_1[0]; // @[Mux.scala:32:36] wire _s2_data_T_3 = _s2_data_T_1[1]; // @[Mux.scala:32:36] wire [63:0] _s2_data_T_4 = _s2_data_T_2 ? s2_data_s1_way_words_0_0 : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _s2_data_T_5 = _s2_data_T_3 ? s2_data_s1_way_words_1_0 : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _s2_data_T_6 = _s2_data_T_4 \| _s2_data_T_5; // @[Mux.scala:30:73] wire [63:0] _s2_data_WIRE = _s2_data_T_6; // @[Mux.scala:30:73] reg [63:0] s2_data; // @[DCache.scala:379:18] reg s2_probe_way; // @[DCache.scala:383:31] assign releaseWay = s2_probe_way; // @[DCache.scala:232:24, :383:31] reg [1:0] s2_probe_state_state; // @[DCache.scala:384:33] reg s2_hit_way; // @[DCache.scala:385:29] reg [1:0] s2_hit_state_state; // @[DCache.scala:386:31] wire s2_hit_valid = \|s2_hit_state_state; // @[Metadata.scala:50:45] wire _r_c_cat_T_2 = _r_c_cat_T \| _r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _r_c_cat_T_4 = _r_c_cat_T_2 \| _r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _r_c_cat_T_9 = _r_c_cat_T_5 \| _r_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_10 = _r_c_cat_T_9 \| _r_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_11 = _r_c_cat_T_10 \| _r_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_17 = _r_c_cat_T_12 \| _r_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_18 = _r_c_cat_T_17 \| _r_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_19 = _r_c_cat_T_18 \| _r_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_20 = _r_c_cat_T_19 \| _r_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_21 = _r_c_cat_T_11 \| _r_c_cat_T_20; // @[package.scala:81:59] wire _r_c_cat_T_22 = _r_c_cat_T_4 \| _r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _r_c_cat_T_25 = _r_c_cat_T_23 \| _r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _r_c_cat_T_27 = _r_c_cat_T_25 \| _r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _r_c_cat_T_32 = _r_c_cat_T_28 \| _r_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_33 = _r_c_cat_T_32 \| _r_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_34 = _r_c_cat_T_33 \| _r_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_40 = _r_c_cat_T_35 \| _r_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_41 = _r_c_cat_T_40 \| _r_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_42 = _r_c_cat_T_41 \| _r_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_43 = _r_c_cat_T_42 \| _r_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_44 = _r_c_cat_T_34 \| _r_c_cat_T_43; // @[package.scala:81:59] wire _r_c_cat_T_45 = _r_c_cat_T_27 \| _r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _GEN_83 = s2_req_cmd == 5'h3; // @[DCache.scala:339:19] wire _r_c_cat_T_46; // @[Consts.scala:91:54] assign _r_c_cat_T_46 = _GEN_83; // @[Consts.scala:91:54] wire _metaArb_io_in_3_bits_data_c_cat_T_46; // @[Consts.scala:91:54] assign _metaArb_io_in_3_bits_data_c_cat_T_46 = _GEN_83; // @[Consts.scala:91:54] wire _r_c_cat_T_47 = _r_c_cat_T_45 \| _r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _r_c_cat_T_49 = _r_c_cat_T_47 \| _r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] r_c = {_r_c_cat_T_22, _r_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _r_T = {r_c, s2_hit_state_state}; // @[Metadata.scala:29:18, :58:19] wire _r_T_25 = _r_T == 4'hC; // @[Misc.scala:49:20] wire [1:0] _r_T_27 = {1'h0, _r_T_25}; // @[Misc.scala:35:36, :49:20] wire _r_T_28 = _r_T == 4'hD; // @[Misc.scala:49:20] wire [1:0] _r_T_30 = _r_T_28 ? 2'h2 : _r_T_27; // @[Misc.scala:35:36, :49:20] wire _r_T_31 = _r_T == 4'h4; // @[Misc.scala:49:20] wire [1:0] _r_T_33 = _r_T_31 ? 2'h1 : _r_T_30; // @[Misc.scala:35:36, :49:20] wire _r_T_34 = _r_T == 4'h5; // @[Misc.scala:49:20] wire [1:0] _r_T_36 = _r_T_34 ? 2'h2 : _r_T_33; // @[Misc.scala:35:36, :49:20] wire _r_T_37 = _r_T == 4'h0; // @[Misc.scala:49:20] wire [1:0] _r_T_39 = _r_T_37 ? 2'h0 : _r_T_36; // @[Misc.scala:35:36, :49:20] wire _r_T_40 = _r_T == 4'hE; // @[Misc.scala:49:20] wire _r_T_41 = _r_T_40; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_42 = _r_T_40 ? 2'h3 : _r_T_39; // @[Misc.scala:35:36, :49:20] wire _r_T_43 = &_r_T; // @[Misc.scala:49:20] wire _r_T_44 = _r_T_43 \| _r_T_41; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_45 = _r_T_43 ? 2'h3 : _r_T_42; // @[Misc.scala:35:36, :49:20] wire _r_T_46 = _r_T == 4'h6; // @[Misc.scala:49:20] wire _r_T_47 = _r_T_46 \| _r_T_44; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_48 = _r_T_46 ? 2'h2 : _r_T_45; // @[Misc.scala:35:36, :49:20] wire _r_T_49 = _r_T == 4'h7; // @[Misc.scala:49:20] wire _r_T_50 = _r_T_49 \| _r_T_47; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_51 = _r_T_49 ? 2'h3 : _r_T_48; // @[Misc.scala:35:36, :49:20] wire _r_T_52 = _r_T == 4'h1; // @[Misc.scala:49:20] wire _r_T_53 = _r_T_52 \| _r_T_50; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_54 = _r_T_52 ? 2'h1 : _r_T_51; // @[Misc.scala:35:36, :49:20] wire _r_T_55 = _r_T == 4'h2; // @[Misc.scala:49:20] wire _r_T_56 = _r_T_55 \| _r_T_53; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_57 = _r_T_55 ? 2'h2 : _r_T_54; // @[Misc.scala:35:36, :49:20] wire _r_T_58 = _r_T == 4'h3; // @[Misc.scala:49:20] wire s2_hit = _r_T_58 \| _r_T_56; // @[Misc.scala:35:9, :49:20] wire [1:0] s2_grow_param = _r_T_58 ? 2'h3 : _r_T_57; // @[Misc.scala:35:36, :49:20] wire [1:0] s2_new_hit_state_state = s2_grow_param; // @[Misc.scala:35:36] wire [1:0] metaArb_io_in_2_bits_data_meta_coh_state = s2_new_hit_state_state; // @[Metadata.scala:160:20] wire [15:0] s2_data_corrected_lo_lo = s2_data[15:0]; // @[package.scala:45:27] wire [15:0] s2_data_uncorrected_lo_lo = s2_data[15:0]; // @[package.scala:45:27] wire [15:0] s2_data_corrected_lo_hi = s2_data[31:16]; // @[package.scala:45:27] wire [15:0] s2_data_uncorrected_lo_hi = s2_data[31:16]; // @[package.scala:45:27] wire [31:0] s2_data_corrected_lo = {s2_data_corrected_lo_hi, s2_data_corrected_lo_lo}; // @[package.scala:45:27] wire [15:0] s2_data_corrected_hi_lo = s2_data[47:32]; // @[package.scala:45:27] wire [15:0] s2_data_uncorrected_hi_lo = s2_data[47:32]; // @[package.scala:45:27] wire [15:0] s2_data_corrected_hi_hi = s2_data[63:48]; // @[package.scala:45:27] wire [15:0] s2_data_uncorrected_hi_hi = s2_data[63:48]; // @[package.scala:45:27] wire [31:0] s2_data_corrected_hi = {s2_data_corrected_hi_hi, s2_data_corrected_hi_lo}; // @[package.scala:45:27] wire [63:0] s2_data_corrected = {s2_data_corrected_hi, s2_data_corrected_lo}; // @[package.scala:45:27] wire [63:0] s2_data_word_corrected = s2_data_corrected; // @[package.scala:45:27] wire [31:0] s2_data_uncorrected_lo = {s2_data_uncorrected_lo_hi, s2_data_uncorrected_lo_lo}; // @[package.scala:45:27] wire [31:0] s2_data_uncorrected_hi = {s2_data_uncorrected_hi_hi, s2_data_uncorrected_hi_lo}; // @[package.scala:45:27] wire [63:0] s2_data_uncorrected = {s2_data_uncorrected_hi, s2_data_uncorrected_lo}; // @[package.scala:45:27] assign s2_data_word = s2_data_uncorrected; // @[package.scala:45:27] wire s2_valid_hit_maybe_flush_pre_data_ecc_and_waw = _s2_valid_hit_maybe_flush_pre_data_ecc_and_waw_T_1 & s2_hit; // @[Misc.scala:35:9] wire _s2_valid_hit_pre_data_ecc_and_waw_T = s2_valid_hit_maybe_flush_pre_data_ecc_and_waw & s2_readwrite; // @[DCache.scala:354:30, :397:89, :418:89] wire s2_valid_hit_pre_data_ecc_and_waw = _s2_valid_hit_pre_data_ecc_and_waw_T; // @[DCache.scala:418:{89,105}] wire s2_valid_hit_pre_data_ecc = s2_valid_hit_pre_data_ecc_and_waw; // @[DCache.scala:418:105, :420:69] wire s2_valid_flush_line = s2_valid_hit_maybe_flush_pre_data_ecc_and_waw & s2_cmd_flush_line; // @[DCache.scala:341:54, :397:89, :419:75] wire _s2_victim_tag_T = s2_valid_flush_line; // @[DCache.scala:419:75, :433:47] wire s2_valid_hit = s2_valid_hit_pre_data_ecc; // @[DCache.scala:420:69, :422:48] wire _s2_valid_miss_T = s2_valid_masked & s2_readwrite; // @[DCache.scala:337:42, :354:30, :423:39] wire _s2_valid_miss_T_2 = _s2_valid_miss_T; // @[DCache.scala:423:{39,55}] wire _s2_valid_miss_T_3 = ~s2_hit; // @[Misc.scala:35:9] wire s2_valid_miss = _s2_valid_miss_T_2 & _s2_valid_miss_T_3; // @[DCache.scala:423:{55,73,76}] wire _s2_uncached_T = ~s2_pma_cacheable; // @[DCache.scala:343:19, :424:21] wire _s2_uncached_T_1 = ~s2_pma_must_alloc; // @[DCache.scala:343:19, :424:61] wire _s2_uncached_T_2 = s2_req_no_alloc & _s2_uncached_T_1; // @[DCache.scala:339:19, :424:{58,61}] wire _s2_uncached_T_3 = ~s2_hit_valid; // @[Metadata.scala:50:45] wire _s2_uncached_T_4 = _s2_uncached_T_2 & _s2_uncached_T_3; // @[DCache.scala:424:{58,80,83}] wire s2_uncached = _s2_uncached_T \| _s2_uncached_T_4; // @[DCache.scala:424:{21,39,80}] wire _s2_valid_cached_miss_T = ~s2_uncached; // @[DCache.scala:424:39, :425:47] wire _s2_valid_cached_miss_T_1 = s2_valid_miss & _s2_valid_cached_miss_T; // @[DCache.scala:423:73, :425:{44,47}] wire _s2_valid_cached_miss_T_3 = ~_s2_valid_cached_miss_T_2; // @[DCache.scala:425:{63,88}] wire s2_valid_cached_miss = _s2_valid_cached_miss_T_1 & _s2_valid_cached_miss_T_3; // @[DCache.scala:425:{44,60,63}] wire _tl_out_a_valid_T_6 = s2_valid_cached_miss; // @[DCache.scala:425:60, :605:29] wire _s2_want_victimize_T = s2_valid_cached_miss \| s2_valid_flush_line; // @[DCache.scala:419:75, :425:60, :427:77] wire _s2_want_victimize_T_1 = _s2_want_victimize_T; // @[DCache.scala:427:{77,100}] wire _s2_want_victimize_T_2 = _s2_want_victimize_T_1 \| s2_flush_valid; // @[DCache.scala:363:51, :427:{100,123}] wire _s2_cannot_victimize_T = ~s2_flush_valid; // @[DCache.scala:363:51, :428:29] wire _s2_valid_uncached_pending_T = s2_valid_miss & s2_uncached; // @[DCache.scala:423:73, :424:39, :430:49] wire _s2_valid_uncached_pending_T_2 = ~_s2_valid_uncached_pending_T_1; // @[DCache.scala:430:{67,92}] wire s2_valid_uncached_pending = _s2_valid_uncached_pending_T & _s2_valid_uncached_pending_T_2; // @[DCache.scala:430:{49,64,67}] wire [1:0] s2_victim_or_hit_way = s2_hit_valid ? {1'h0, s2_hit_way} : 2'h1; // @[Metadata.scala:50:45] wire [17:0] _s2_victim_tag_T_1 = s2_req_addr[31:14]; // @[DCache.scala:339:19, :433:82] wire [17:0] s2_victim_tag = _s2_victim_tag_T ? _s2_victim_tag_T_1 : 18'h0; // @[DCache.scala:433:{26,47,82}] wire [1:0] s2_victim_state_state = s2_hit_valid ? s2_hit_state_state : 2'h0; // @[Metadata.scala:50:45] wire [3:0] _r_T_59 = {2'h0, s2_probe_state_state}; // @[Metadata.scala:120:19] wire _r_T_72 = _r_T_59 == 4'h8; // @[Misc.scala:56:20] wire [2:0] _r_T_74 = _r_T_72 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _r_T_76 = _r_T_59 == 4'h9; // @[Misc.scala:56:20] wire [2:0] _r_T_78 = _r_T_76 ? 3'h2 : _r_T_74; // @[Misc.scala:38:36, :56:20] wire _r_T_80 = _r_T_59 == 4'hA; // @[Misc.scala:56:20] wire [2:0] _r_T_82 = _r_T_80 ? 3'h1 : _r_T_78; // @[Misc.scala:38:36, :56:20] wire _r_T_84 = _r_T_59 == 4'hB; // @[Misc.scala:56:20] wire _r_T_85 = _r_T_84; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_86 = _r_T_84 ? 3'h1 : _r_T_82; // @[Misc.scala:38:36, :56:20] wire _r_T_88 = _r_T_59 == 4'h4; // @[Misc.scala:56:20] wire _r_T_89 = ~_r_T_88 & _r_T_85; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_90 = _r_T_88 ? 3'h5 : _r_T_86; // @[Misc.scala:38:36, :56:20] wire _r_T_92 = _r_T_59 == 4'h5; // @[Misc.scala:56:20] wire _r_T_93 = ~_r_T_92 & _r_T_89; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_94 = _r_T_92 ? 3'h4 : _r_T_90; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_95 = {1'h0, _r_T_92}; // @[Misc.scala:38:63, :56:20] wire _r_T_96 = _r_T_59 == 4'h6; // @[Misc.scala:56:20] wire _r_T_97 = ~_r_T_96 & _r_T_93; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_98 = _r_T_96 ? 3'h0 : _r_T_94; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_99 = _r_T_96 ? 2'h1 : _r_T_95; // @[Misc.scala:38:63, :56:20] wire _r_T_100 = _r_T_59 == 4'h7; // @[Misc.scala:56:20] wire _r_T_101 = _r_T_100 \| _r_T_97; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_102 = _r_T_100 ? 3'h0 : _r_T_98; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_103 = _r_T_100 ? 2'h1 : _r_T_99; // @[Misc.scala:38:63, :56:20] wire _r_T_104 = _r_T_59 == 4'h0; // @[Misc.scala:56:20] wire _r_T_105 = ~_r_T_104 & _r_T_101; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_106 = _r_T_104 ? 3'h5 : _r_T_102; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_107 = _r_T_104 ? 2'h0 : _r_T_103; // @[Misc.scala:38:63, :56:20] wire _r_T_108 = _r_T_59 == 4'h1; // @[Misc.scala:56:20] wire _r_T_109 = ~_r_T_108 & _r_T_105; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_110 = _r_T_108 ? 3'h4 : _r_T_106; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_111 = _r_T_108 ? 2'h1 : _r_T_107; // @[Misc.scala:38:63, :56:20] wire _r_T_112 = _r_T_59 == 4'h2; // @[Misc.scala:56:20] wire _r_T_113 = ~_r_T_112 & _r_T_109; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_114 = _r_T_112 ? 3'h3 : _r_T_110; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_115 = _r_T_112 ? 2'h2 : _r_T_111; // @[Misc.scala:38:63, :56:20] wire _r_T_116 = _r_T_59 == 4'h3; // @[Misc.scala:56:20] wire s2_prb_ack_data = _r_T_116 \| _r_T_113; // @[Misc.scala:38:9, :56:20] wire [2:0] s2_report_param = _r_T_116 ? 3'h3 : _r_T_114; // @[Misc.scala:38:36, :56:20] wire [2:0] cleanReleaseMessage_param = s2_report_param; // @[Misc.scala:38:36] wire [2:0] dirtyReleaseMessage_param = s2_report_param; // @[Misc.scala:38:36] wire [1:0] r_3 = _r_T_116 ? 2'h2 : _r_T_115; // @[Misc.scala:38:63, :56:20] wire [1:0] probeNewCoh_state = r_3; // @[Misc.scala:38:63] wire [1:0] newCoh_state = probeNewCoh_state; // @[Metadata.scala:160:20] wire [3:0] _r_T_123 = {2'h2, s2_victim_state_state}; // @[Metadata.scala:120:19] wire _r_T_136 = _r_T_123 == 4'h8; // @[Misc.scala:56:20] wire [2:0] _r_T_138 = _r_T_136 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _r_T_140 = _r_T_123 == 4'h9; // @[Misc.scala:56:20] wire [2:0] _r_T_142 = _r_T_140 ? 3'h2 : _r_T_138; // @[Misc.scala:38:36, :56:20] wire _r_T_144 = _r_T_123 == 4'hA; // @[Misc.scala:56:20] wire [2:0] _r_T_146 = _r_T_144 ? 3'h1 : _r_T_142; // @[Misc.scala:38:36, :56:20] wire _r_T_148 = _r_T_123 == 4'hB; // @[Misc.scala:56:20] wire _r_T_149 = _r_T_148; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_150 = _r_T_148 ? 3'h1 : _r_T_146; // @[Misc.scala:38:36, :56:20] wire _r_T_152 = _r_T_123 == 4'h4; // @[Misc.scala:56:20] wire _r_T_153 = ~_r_T_152 & _r_T_149; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_154 = _r_T_152 ? 3'h5 : _r_T_150; // @[Misc.scala:38:36, :56:20] wire _r_T_156 = _r_T_123 == 4'h5; // @[Misc.scala:56:20] wire _r_T_157 = ~_r_T_156 & _r_T_153; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_158 = _r_T_156 ? 3'h4 : _r_T_154; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_159 = {1'h0, _r_T_156}; // @[Misc.scala:38:63, :56:20] wire _r_T_160 = _r_T_123 == 4'h6; // @[Misc.scala:56:20] wire _r_T_161 = ~_r_T_160 & _r_T_157; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_162 = _r_T_160 ? 3'h0 : _r_T_158; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_163 = _r_T_160 ? 2'h1 : _r_T_159; // @[Misc.scala:38:63, :56:20] wire _r_T_164 = _r_T_123 == 4'h7; // @[Misc.scala:56:20] wire _r_T_165 = _r_T_164 \| _r_T_161; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_166 = _r_T_164 ? 3'h0 : _r_T_162; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_167 = _r_T_164 ? 2'h1 : _r_T_163; // @[Misc.scala:38:63, :56:20] wire _r_T_168 = _r_T_123 == 4'h0; // @[Misc.scala:56:20] wire _r_T_169 = ~_r_T_168 & _r_T_165; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_170 = _r_T_168 ? 3'h5 : _r_T_166; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_171 = _r_T_168 ? 2'h0 : _r_T_167; // @[Misc.scala:38:63, :56:20] wire _r_T_172 = _r_T_123 == 4'h1; // @[Misc.scala:56:20] wire _r_T_173 = ~_r_T_172 & _r_T_169; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_174 = _r_T_172 ? 3'h4 : _r_T_170; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_175 = _r_T_172 ? 2'h1 : _r_T_171; // @[Misc.scala:38:63, :56:20] wire _r_T_176 = _r_T_123 == 4'h2; // @[Misc.scala:56:20] wire _r_T_177 = ~_r_T_176 & _r_T_173; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_178 = _r_T_176 ? 3'h3 : _r_T_174; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_179 = _r_T_176 ? 2'h2 : _r_T_175; // @[Misc.scala:38:63, :56:20] wire _r_T_180 = _r_T_123 == 4'h3; // @[Misc.scala:56:20] wire s2_victim_dirty = _r_T_180 \| _r_T_177; // @[Misc.scala:38:9, :56:20] wire [2:0] s2_shrink_param = _r_T_180 ? 3'h3 : _r_T_178; // @[Misc.scala:38:36, :56:20] wire [1:0] r_3_1 = _r_T_180 ? 2'h2 : _r_T_179; // @[Misc.scala:38:63, :56:20] wire [1:0] voluntaryNewCoh_state = r_3_1; // @[Misc.scala:38:63] wire _s2_update_meta_T = s2_hit_state_state == s2_new_hit_state_state; // @[Metadata.scala:46:46, :160:20] wire s2_update_meta = ~_s2_update_meta_T; // @[Metadata.scala:46:46, :47:40] wire s2_dont_nack_uncached = s2_valid_uncached_pending & tl_out_a_ready; // @[DCache.scala:159:22, :430:64, :440:57] wire _s2_dont_nack_misc_T_7 = ~s2_hit; // @[Misc.scala:35:9] wire _s2_dont_nack_misc_T_10 = s2_req_cmd == 5'h17; // @[DCache.scala:339:19, :444:17] wire _s2_dont_nack_misc_T_11 = _s2_dont_nack_misc_T_10; // @[DCache.scala:443:55, :444:17] wire s2_dont_nack_misc = _s2_dont_nack_misc_T_1 & _s2_dont_nack_misc_T_11; // @[DCache.scala:441:{43,61}, :443:55] wire _io_cpu_s2_nack_T = ~s2_dont_nack_uncached; // @[DCache.scala:440:57, :445:41] wire _io_cpu_s2_nack_T_1 = s2_valid_no_xcpt & _io_cpu_s2_nack_T; // @[DCache.scala:332:35, :445:{38,41}] wire _io_cpu_s2_nack_T_2 = ~s2_dont_nack_misc; // @[DCache.scala:441:61, :445:67] wire _io_cpu_s2_nack_T_3 = _io_cpu_s2_nack_T_1 & _io_cpu_s2_nack_T_2; // @[DCache.scala:445:{38,64,67}] wire _io_cpu_s2_nack_T_4 = ~s2_valid_hit; // @[DCache.scala:422:48, :445:89] assign _io_cpu_s2_nack_T_5 = _io_cpu_s2_nack_T_3 & _io_cpu_s2_nack_T_4; // @[DCache.scala:445:{64,86,89}] assign io_cpu_s2_nack_0 = _io_cpu_s2_nack_T_5; // @[DCache.scala:101:7, :445:86] assign _metaArb_io_in_2_valid_T = s2_valid_hit_pre_data_ecc_and_waw & s2_update_meta; // @[Metadata.scala:47:40] wire _metaArb_io_in_1_valid_T = s2_valid_masked \| s2_flush_valid_pre_tag_ecc; // @[DCache.scala:337:42, :355:43, :450:63] wire _metaArb_io_in_1_valid_T_1 = _metaArb_io_in_1_valid_T; // @[DCache.scala:450:{63,93}] wire [7:0] _metaArb_io_in_1_bits_idx_T_1 = s2_vaddr[13:6]; // @[DCache.scala:351:21, :453:76] assign _metaArb_io_in_2_bits_idx_T = s2_vaddr[13:6]; // @[DCache.scala:351:21, :453:76, :465:40] assign _metaArb_io_in_3_bits_idx_T = s2_vaddr[13:6]; // @[DCache.scala:351:21, :453:76, :744:40] assign _metaArb_io_in_1_bits_idx_T_2 = _metaArb_io_in_1_bits_idx_T_1; // @[DCache.scala:453:{35,76}] assign metaArb_io_in_1_bits_idx = _metaArb_io_in_1_bits_idx_T_2; // @[DCache.scala:135:28, :453:35] wire [13:0] _metaArb_io_in_1_bits_addr_T_1 = {_metaArb_io_in_1_bits_idx_T_2, 6'h0}; // @[DCache.scala:453:35, :454:98] assign _metaArb_io_in_1_bits_addr_T_2 = {_metaArb_io_in_1_bits_addr_T, _metaArb_io_in_1_bits_addr_T_1}; // @[DCache.scala:454:{36,58,98}] assign metaArb_io_in_1_bits_addr = _metaArb_io_in_1_bits_addr_T_2; // @[DCache.scala:135:28, :454:36] assign metaArb_io_in_2_valid = _metaArb_io_in_2_valid_T; // @[DCache.scala:135:28, :462:63] assign metaArb_io_in_2_bits_way_en = s2_victim_or_hit_way[0]; // @[DCache.scala:135:28, :432:33, :464:32] assign metaArb_io_in_2_bits_idx = _metaArb_io_in_2_bits_idx_T; // @[DCache.scala:135:28, :465:40] wire [13:0] _metaArb_io_in_2_bits_addr_T_1 = s2_vaddr[13:0]; // @[DCache.scala:351:21, :466:80] wire [13:0] _metaArb_io_in_3_bits_addr_T_1 = s2_vaddr[13:0]; // @[DCache.scala:351:21, :466:80, :745:80] assign _metaArb_io_in_2_bits_addr_T_2 = {_metaArb_io_in_2_bits_addr_T, _metaArb_io_in_2_bits_addr_T_1}; // @[DCache.scala:466:{36,58,80}] assign metaArb_io_in_2_bits_addr = _metaArb_io_in_2_bits_addr_T_2; // @[DCache.scala:135:28, :466:36] wire [19:0] _metaArb_io_in_2_bits_data_T = s2_req_addr[33:14]; // @[DCache.scala:339:19, :467:68] wire [19:0] _metaArb_io_in_3_bits_data_T = s2_req_addr[33:14]; // @[DCache.scala:339:19, :467:68, :746:68] wire [17:0] metaArb_io_in_2_bits_data_meta_tag; // @[HellaCache.scala:305:20] assign metaArb_io_in_2_bits_data_meta_tag = _metaArb_io_in_2_bits_data_T[17:0]; // @[HellaCache.scala:305:20, :306:14] assign _metaArb_io_in_2_bits_data_T_1 = {metaArb_io_in_2_bits_data_meta_coh_state, metaArb_io_in_2_bits_data_meta_tag}; // @[HellaCache.scala:305:20] assign metaArb_io_in_2_bits_data = _metaArb_io_in_2_bits_data_T_1; // @[DCache.scala:135:28, :467:97] reg [6:0] lrscCount; // @[DCache.scala:472:26] wire lrscValid = \|(lrscCount[6:2]); // @[DCache.scala:472:26, :473:29] wire _lrscBackingOff_T = \|lrscCount; // @[DCache.scala:472:26, :474:34] wire _lrscBackingOff_T_1 = ~lrscValid; // @[DCache.scala:473:29, :474:43] wire lrscBackingOff = _lrscBackingOff_T & _lrscBackingOff_T_1; // @[DCache.scala:474:{34,40,43}] reg [27:0] lrscAddr; // @[DCache.scala:475:21] wire [27:0] _lrscAddrMatch_T = s2_req_addr[33:6]; // @[DCache.scala:339:19, :476:49] wire [27:0] _lrscAddr_T = s2_req_addr[33:6]; // @[DCache.scala:339:19, :476:49, :480:29] wire [27:0] _acquire_address_T = s2_req_addr[33:6]; // @[DCache.scala:339:19, :476:49, :578:38] wire [27:0] _error_addr_T_2 = s2_req_addr[33:6]; // @[DCache.scala:339:19, :476:49, :1119:27] wire [27:0] _io_errors_bus_bits_T = s2_req_addr[33:6]; // @[DCache.scala:339:19, :476:49, :1130:58] wire lrscAddrMatch = lrscAddr == _lrscAddrMatch_T; // @[DCache.scala:475:21, :476:{32,49}] wire _s2_sc_fail_T = lrscValid & lrscAddrMatch; // @[DCache.scala:473:29, :476:32, :477:41] wire _s2_sc_fail_T_1 = ~_s2_sc_fail_T; // @[DCache.scala:477:{29,41}] wire [6:0] _lrscCount_T = s2_hit ? 7'h4F : 7'h0; // @[Misc.scala:35:9] wire [7:0] _lrscCount_T_1 = {1'h0, lrscCount} - 8'h1; // @[DCache.scala:472:26, :482:51] wire [6:0] _lrscCount_T_2 = _lrscCount_T_1[6:0]; // @[DCache.scala:482:51] wire _s2_correct_T = ~any_pstore_valid; // @[DCache.scala:230:30, :487:37] wire _s2_correct_T_2 = any_pstore_valid \| s2_valid; // @[DCache.scala:230:30, :331:25, :487:84] reg s2_correct_REG; // @[DCache.scala:487:66] wire _s2_correct_T_3 = ~s2_correct_REG; // @[DCache.scala:487:{58,66}] wire _GEN_84 = s1_valid_not_nacked & s1_write; // @[DCache.scala:187:38, :492:63] wire _pstore1_cmd_T; // @[DCache.scala:492:63] assign _pstore1_cmd_T = _GEN_84; // @[DCache.scala:492:63] wire _pstore1_addr_T; // @[DCache.scala:493:62] assign _pstore1_addr_T = _GEN_84; // @[DCache.scala:492:63, :493:62] wire _pstore1_data_T; // @[DCache.scala:494:73] assign _pstore1_data_T = _GEN_84; // @[DCache.scala:492:63, :494:73] wire _pstore1_way_T; // @[DCache.scala:495:63] assign _pstore1_way_T = _GEN_84; // @[DCache.scala:492:63, :495:63] wire _pstore1_mask_T; // @[DCache.scala:496:61] assign _pstore1_mask_T = _GEN_84; // @[DCache.scala:492:63, :496:61] wire _pstore1_rmw_T_53; // @[DCache.scala:498:84] assign _pstore1_rmw_T_53 = _GEN_84; // @[DCache.scala:492:63, :498:84] reg [4:0] pstore1_cmd; // @[DCache.scala:492:30] reg [33:0] pstore1_addr; // @[DCache.scala:493:31] wire [33:0] _pstore2_addr_T = pstore1_addr; // @[DCache.scala:493:31, :524:35] reg [63:0] pstore1_data; // @[DCache.scala:494:31] assign io_cpu_resp_bits_store_data_0 = pstore1_data; // @[DCache.scala:101:7, :494:31] wire [63:0] put_data = pstore1_data; // @[Edges.scala:480:17] wire [63:0] putpartial_data = pstore1_data; // @[Edges.scala:500:17] wire [63:0] atomics_a_data = pstore1_data; // @[Edges.scala:534:17] wire [63:0] atomics_a_1_data = pstore1_data; // @[Edges.scala:534:17] wire [63:0] atomics_a_2_data = pstore1_data; // @[Edges.scala:534:17] wire [63:0] atomics_a_3_data = pstore1_data; // @[Edges.scala:534:17] wire [63:0] atomics_a_4_data = pstore1_data; // @[Edges.scala:517:17] wire [63:0] atomics_a_5_data = pstore1_data; // @[Edges.scala:517:17] wire [63:0] atomics_a_6_data = pstore1_data; // @[Edges.scala:517:17] wire [63:0] atomics_a_7_data = pstore1_data; // @[Edges.scala:517:17] wire [63:0] atomics_a_8_data = pstore1_data; // @[Edges.scala:517:17] wire [63:0] _amoalu_io_rhs_T = pstore1_data; // @[DCache.scala:494:31, :986:37] reg pstore1_way; // @[DCache.scala:495:30] wire _pstore2_way_T = pstore1_way; // @[DCache.scala:495:30, :525:34] reg [7:0] pstore1_mask; // @[DCache.scala:496:31] wire [7:0] pstore2_storegen_mask_mergedMask = pstore1_mask; // @[DCache.scala:496:31, :533:37] wire [7:0] _amoalu_io_mask_T = pstore1_mask; // @[DCache.scala:496:31, :983:38] wire [7:0] _pstore1_storegen_data_mask_T = pstore1_mask; // @[DCache.scala:496:31, :990:40] wire [63:0] _pstore1_storegen_data_T_3; // @[DCache.scala:991:52] wire [63:0] pstore1_storegen_data; // @[DCache.scala:497:42] wire _pstore1_rmw_T_4 = _pstore1_rmw_T \| _pstore1_rmw_T_1; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_5 = _pstore1_rmw_T_4 \| _pstore1_rmw_T_2; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_6 = _pstore1_rmw_T_5 \| _pstore1_rmw_T_3; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_11 = _pstore1_rmw_T_7 \| _pstore1_rmw_T_8; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_12 = _pstore1_rmw_T_11 \| _pstore1_rmw_T_9; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_13 = _pstore1_rmw_T_12 \| _pstore1_rmw_T_10; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_19 = _pstore1_rmw_T_14 \| _pstore1_rmw_T_15; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_20 = _pstore1_rmw_T_19 \| _pstore1_rmw_T_16; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_21 = _pstore1_rmw_T_20 \| _pstore1_rmw_T_17; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_22 = _pstore1_rmw_T_21 \| _pstore1_rmw_T_18; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_23 = _pstore1_rmw_T_13 \| _pstore1_rmw_T_22; // @[package.scala:81:59] wire _pstore1_rmw_T_24 = _pstore1_rmw_T_6 \| _pstore1_rmw_T_23; // @[package.scala:81:59] wire _pstore1_rmw_T_27 = _pstore1_rmw_T_25 \| _pstore1_rmw_T_26; // @[Consts.scala:90:{32,42,49}] wire _pstore1_rmw_T_29 = _pstore1_rmw_T_27 \| _pstore1_rmw_T_28; // @[Consts.scala:90:{42,59,66}] wire _pstore1_rmw_T_34 = _pstore1_rmw_T_30 \| _pstore1_rmw_T_31; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_35 = _pstore1_rmw_T_34 \| _pstore1_rmw_T_32; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_36 = _pstore1_rmw_T_35 \| _pstore1_rmw_T_33; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_42 = _pstore1_rmw_T_37 \| _pstore1_rmw_T_38; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_43 = _pstore1_rmw_T_42 \| _pstore1_rmw_T_39; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_44 = _pstore1_rmw_T_43 \| _pstore1_rmw_T_40; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_45 = _pstore1_rmw_T_44 \| _pstore1_rmw_T_41; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_46 = _pstore1_rmw_T_36 \| _pstore1_rmw_T_45; // @[package.scala:81:59] wire _pstore1_rmw_T_47 = _pstore1_rmw_T_29 \| _pstore1_rmw_T_46; // @[Consts.scala:87:44, :90:{59,76}] wire _pstore1_rmw_T_50 = _pstore1_rmw_T_48; // @[DCache.scala:1191:{35,45}] wire _pstore1_rmw_T_51 = _pstore1_rmw_T_47 & _pstore1_rmw_T_50; // @[DCache.scala:1191:{23,45}] wire _pstore1_rmw_T_52 = _pstore1_rmw_T_24 \| _pstore1_rmw_T_51; // @[DCache.scala:1190:21, :1191:23] reg pstore1_rmw_r; // @[DCache.scala:498:44] wire pstore1_rmw = pstore1_rmw_r; // @[DCache.scala:498:{32,44}] wire _pstore1_merge_likely_T = s2_valid_not_nacked_in_s1 & s2_write; // @[DCache.scala:336:44, :499:56] wire _GEN_85 = s2_valid_hit & s2_write; // @[DCache.scala:422:48, :490:46] wire _pstore1_merge_T; // @[DCache.scala:490:46] assign _pstore1_merge_T = _GEN_85; // @[DCache.scala:490:46] wire _pstore1_valid_T; // @[DCache.scala:490:46] assign _pstore1_valid_T = _GEN_85; // @[DCache.scala:490:46] wire _pstore1_held_T; // @[DCache.scala:490:46] assign _pstore1_held_T = _GEN_85; // @[DCache.scala:490:46] wire _pstore1_merge_T_2 = _pstore1_merge_T; // @[DCache.scala:490:{46,58}] wire _pstore1_merge_T_4 = _pstore1_merge_T_2; // @[DCache.scala:490:58, :491:48] reg pstore2_valid; // @[DCache.scala:501:30] wire _pstore_drain_opportunistic_res_T_2 = _pstore_drain_opportunistic_res_T \| _pstore_drain_opportunistic_res_T_1; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_res_T_3 = ~_pstore_drain_opportunistic_res_T_2; // @[package.scala:81:59] wire pstore_drain_opportunistic_res = _pstore_drain_opportunistic_res_T_3; // @[DCache.scala:1185:{15,46}] wire _pstore_drain_opportunistic_T_4 = _pstore_drain_opportunistic_T \| _pstore_drain_opportunistic_T_1; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_5 = _pstore_drain_opportunistic_T_4 \| _pstore_drain_opportunistic_T_2; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_6 = _pstore_drain_opportunistic_T_5 \| _pstore_drain_opportunistic_T_3; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_11 = _pstore_drain_opportunistic_T_7 \| _pstore_drain_opportunistic_T_8; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_12 = _pstore_drain_opportunistic_T_11 \| _pstore_drain_opportunistic_T_9; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_13 = _pstore_drain_opportunistic_T_12 \| _pstore_drain_opportunistic_T_10; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_19 = _pstore_drain_opportunistic_T_14 \| _pstore_drain_opportunistic_T_15; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_20 = _pstore_drain_opportunistic_T_19 \| _pstore_drain_opportunistic_T_16; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_21 = _pstore_drain_opportunistic_T_20 \| _pstore_drain_opportunistic_T_17; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_22 = _pstore_drain_opportunistic_T_21 \| _pstore_drain_opportunistic_T_18; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_23 = _pstore_drain_opportunistic_T_13 \| _pstore_drain_opportunistic_T_22; // @[package.scala:81:59] wire _pstore_drain_opportunistic_T_24 = _pstore_drain_opportunistic_T_6 \| _pstore_drain_opportunistic_T_23; // @[package.scala:81:59] wire _pstore_drain_opportunistic_T_27 = _pstore_drain_opportunistic_T_25 \| _pstore_drain_opportunistic_T_26; // @[Consts.scala:90:{32,42,49}] wire _pstore_drain_opportunistic_T_29 = _pstore_drain_opportunistic_T_27 \| _pstore_drain_opportunistic_T_28; // @[Consts.scala:90:{42,59,66}] wire _pstore_drain_opportunistic_T_34 = _pstore_drain_opportunistic_T_30 \| _pstore_drain_opportunistic_T_31; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_35 = _pstore_drain_opportunistic_T_34 \| _pstore_drain_opportunistic_T_32; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_36 = _pstore_drain_opportunistic_T_35 \| _pstore_drain_opportunistic_T_33; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_42 = _pstore_drain_opportunistic_T_37 \| _pstore_drain_opportunistic_T_38; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_43 = _pstore_drain_opportunistic_T_42 \| _pstore_drain_opportunistic_T_39; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_44 = _pstore_drain_opportunistic_T_43 \| _pstore_drain_opportunistic_T_40; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_45 = _pstore_drain_opportunistic_T_44 \| _pstore_drain_opportunistic_T_41; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_46 = _pstore_drain_opportunistic_T_36 \| _pstore_drain_opportunistic_T_45; // @[package.scala:81:59] wire _pstore_drain_opportunistic_T_47 = _pstore_drain_opportunistic_T_29 \| _pstore_drain_opportunistic_T_46; // @[Consts.scala:87:44, :90:{59,76}] wire _pstore_drain_opportunistic_T_50 = _pstore_drain_opportunistic_T_48; // @[DCache.scala:1191:{35,45}] wire _pstore_drain_opportunistic_T_51 = _pstore_drain_opportunistic_T_47 & _pstore_drain_opportunistic_T_50; // @[DCache.scala:1191:{23,45}] wire _pstore_drain_opportunistic_T_52 = _pstore_drain_opportunistic_T_24 \| _pstore_drain_opportunistic_T_51; // @[DCache.scala:1190:21, :1191:23] wire _pstore_drain_opportunistic_T_53 = ~_pstore_drain_opportunistic_T_52; // @[DCache.scala:1186:12, :1190:21] wire _pstore_drain_opportunistic_T_54 = _pstore_drain_opportunistic_T_53 \| pstore_drain_opportunistic_res; // @[DCache.scala:1185:46, :1186:{12,28}] wire _pstore_drain_opportunistic_T_56 = ~_pstore_drain_opportunistic_T_55; // @[DCache.scala:1186:11] wire _pstore_drain_opportunistic_T_57 = ~_pstore_drain_opportunistic_T_54; // @[DCache.scala:1186:{11,28}] wire _pstore_drain_opportunistic_T_58 = io_cpu_req_valid_0 & pstore_drain_opportunistic_res; // @[DCache.scala:101:7, :502:55, :1185:46] wire _pstore_drain_opportunistic_T_59 = ~_pstore_drain_opportunistic_T_58; // @[DCache.scala:502:{36,55}] wire pstore_drain_opportunistic = _pstore_drain_opportunistic_T_59; // @[DCache.scala:502:{36,92}] reg pstore_drain_on_miss_REG; // @[DCache.scala:503:56] wire pstore_drain_on_miss = pstore_drain_on_miss_REG; // @[DCache.scala:503:{46,56}] reg pstore1_held; // @[DCache.scala:504:29] wire _GEN_86 = s2_valid & s2_write; // @[DCache.scala:331:25, :505:39] wire _pstore1_valid_likely_T; // @[DCache.scala:505:39] assign _pstore1_valid_likely_T = _GEN_86; // @[DCache.scala:505:39] wire _io_cpu_perf_storeBufferEmptyAfterLoad_T_1; // @[DCache.scala:1082:16] assign _io_cpu_perf_storeBufferEmptyAfterLoad_T_1 = _GEN_86; // @[DCache.scala:505:39, :1082:16] wire _io_cpu_perf_storeBufferEmptyAfterStore_T_1; // @[DCache.scala:1086:15] assign _io_cpu_perf_storeBufferEmptyAfterStore_T_1 = _GEN_86; // @[DCache.scala:505:39, :1086:15] wire _io_cpu_perf_storeBufferEmptyAfterStore_T_4; // @[DCache.scala:1087:16] assign _io_cpu_perf_storeBufferEmptyAfterStore_T_4 = _GEN_86; // @[DCache.scala:505:39, :1087:16] wire _io_cpu_perf_canAcceptStoreThenLoad_T; // @[DCache.scala:1089:16] assign _io_cpu_perf_canAcceptStoreThenLoad_T = _GEN_86; // @[DCache.scala:505:39, :1089:16] wire _io_cpu_perf_canAcceptLoadThenLoad_T_55; // @[DCache.scala:1092:100] assign _io_cpu_perf_canAcceptLoadThenLoad_T_55 = _GEN_86; // @[DCache.scala:505:39, :1092:100] wire pstore1_valid_likely = _pstore1_valid_likely_T \| pstore1_held; // @[DCache.scala:504:29, :505:{39,51}] wire _pstore1_valid_T_2 = _pstore1_valid_T; // @[DCache.scala:490:{46,58}] wire _pstore1_valid_T_4 = _pstore1_valid_T_2; // @[DCache.scala:490:58, :491:48] wire pstore1_valid = _pstore1_valid_T_4 \| pstore1_held; // @[DCache.scala:491:48, :504:29, :507:38] wire _advance_pstore1_T = pstore1_valid; // @[DCache.scala:507:38, :522:40] assign _any_pstore_valid_T = pstore1_held \| pstore2_valid; // @[DCache.scala:501:30, :504:29, :508:36] assign any_pstore_valid = _any_pstore_valid_T; // @[DCache.scala:230:30, :508:36] wire _GEN_87 = pstore1_valid_likely & pstore2_valid; // @[DCache.scala:501:30, :505:51, :509:54] wire _pstore_drain_structural_T; // @[DCache.scala:509:54] assign _pstore_drain_structural_T = _GEN_87; // @[DCache.scala:509:54] wire _io_cpu_perf_canAcceptStoreThenLoad_T_6; // @[DCache.scala:1090:20] assign _io_cpu_perf_canAcceptStoreThenLoad_T_6 = _GEN_87; // @[DCache.scala:509:54, :1090:20] wire _GEN_88 = s1_valid & s1_write; // @[DCache.scala:182:25, :509:85] wire _pstore_drain_structural_T_1; // @[DCache.scala:509:85] assign _pstore_drain_structural_T_1 = _GEN_88; // @[DCache.scala:509:85] wire _io_cpu_perf_storeBufferEmptyAfterLoad_T; // @[DCache.scala:1081:15] assign _io_cpu_perf_storeBufferEmptyAfterLoad_T = _GEN_88; // @[DCache.scala:509:85, :1081:15] wire _io_cpu_perf_storeBufferEmptyAfterStore_T; // @[DCache.scala:1085:15] assign _io_cpu_perf_storeBufferEmptyAfterStore_T = _GEN_88; // @[DCache.scala:509:85, :1085:15] wire _io_cpu_perf_canAcceptStoreThenLoad_T_2; // @[DCache.scala:1089:57] assign _io_cpu_perf_canAcceptStoreThenLoad_T_2 = _GEN_88; // @[DCache.scala:509:85, :1089:57] wire _io_cpu_perf_canAcceptStoreThenLoad_T_7; // @[DCache.scala:1090:57] assign _io_cpu_perf_canAcceptStoreThenLoad_T_7 = _GEN_88; // @[DCache.scala:509:85, :1090:57] wire _io_cpu_perf_canAcceptLoadThenLoad_T; // @[DCache.scala:1092:52] assign _io_cpu_perf_canAcceptLoadThenLoad_T = _GEN_88; // @[DCache.scala:509:85, :1092:52] wire _pstore_drain_structural_T_2 = _pstore_drain_structural_T_1 \| pstore1_rmw; // @[DCache.scala:498:32, :509:{85,98}] wire pstore_drain_structural = _pstore_drain_structural_T & _pstore_drain_structural_T_2; // @[DCache.scala:509:{54,71,98}] wire _pstore_drain_T_1 = pstore_drain_structural; // @[DCache.scala:509:71, :517:17] wire _dataArb_io_in_0_valid_T_1 = pstore_drain_structural; // @[DCache.scala:509:71, :517:17] wire _T_48 = s2_valid_hit_pre_data_ecc & s2_write; // @[DCache.scala:420:69, :506:72] wire _pstore_drain_T_2; // @[DCache.scala:506:72] assign _pstore_drain_T_2 = _T_48; // @[DCache.scala:506:72] wire _dataArb_io_in_0_valid_T_2; // @[DCache.scala:506:72] assign _dataArb_io_in_0_valid_T_2 = _T_48; // @[DCache.scala:506:72] wire _pstore_drain_T_4 = _pstore_drain_T_2; // @[DCache.scala:506:{72,84}] wire _pstore_drain_T_5 = _pstore_drain_T_4 \| pstore1_held; // @[DCache.scala:504:29, :506:{84,96}] wire _pstore_drain_T_6 = ~pstore1_rmw; // @[DCache.scala:498:32, :518:44] wire _pstore_drain_T_7 = _pstore_drain_T_5 & _pstore_drain_T_6; // @[DCache.scala:506:96, :518:{41,44}] wire _pstore_drain_T_8 = _pstore_drain_T_7 \| pstore2_valid; // @[DCache.scala:501:30, :518:{41,58}] wire _GEN_89 = pstore_drain_opportunistic \| pstore_drain_on_miss; // @[DCache.scala:502:92, :503:46, :518:107] wire _pstore_drain_T_9; // @[DCache.scala:518:107] assign _pstore_drain_T_9 = _GEN_89; // @[DCache.scala:518:107] wire _dataArb_io_in_0_valid_T_9; // @[DCache.scala:518:107] assign _dataArb_io_in_0_valid_T_9 = _GEN_89; // @[DCache.scala:518:107] wire _pstore_drain_T_10 = _pstore_drain_T_8 & _pstore_drain_T_9; // @[DCache.scala:518:{58,76,107}] wire _pstore_drain_T_11 = _pstore_drain_T_1 \| _pstore_drain_T_10; // @[DCache.scala:517:{17,44}, :518:76] assign pstore_drain = _pstore_drain_T_11; // @[DCache.scala:516:27, :517:44] assign dataArb_io_in_0_bits_write = pstore_drain; // @[DCache.scala:152:28, :516:27] wire _pstore1_held_T_2 = _pstore1_held_T; // @[DCache.scala:490:{46,58}] wire _pstore1_held_T_4 = _pstore1_held_T_2; // @[DCache.scala:490:58, :491:48] wire _pstore1_held_T_6 = _pstore1_held_T_4; // @[DCache.scala:491:48, :521:35] wire _pstore1_held_T_7 = _pstore1_held_T_6 \| pstore1_held; // @[DCache.scala:504:29, :521:{35,54}] wire _pstore1_held_T_8 = _pstore1_held_T_7 & pstore2_valid; // @[DCache.scala:501:30, :521:{54,71}] wire _pstore1_held_T_9 = ~pstore_drain; // @[DCache.scala:516:27, :521:91] wire _pstore1_held_T_10 = _pstore1_held_T_8 & _pstore1_held_T_9; // @[DCache.scala:521:{71,88,91}] wire _advance_pstore1_T_1 = pstore2_valid == pstore_drain; // @[DCache.scala:501:30, :516:27, :522:79] wire advance_pstore1 = _advance_pstore1_T & _advance_pstore1_T_1; // @[DCache.scala:522:{40,61,79}] wire _pstore2_storegen_data_T_3 = advance_pstore1; // @[DCache.scala:522:61, :528:78] wire _pstore2_storegen_data_T_7 = advance_pstore1; // @[DCache.scala:522:61, :528:78] wire _pstore2_storegen_data_T_11 = advance_pstore1; // @[DCache.scala:522:61, :528:78] wire _pstore2_storegen_data_T_15 = advance_pstore1; // @[DCache.scala:522:61, :528:78] wire _pstore2_storegen_data_T_19 = advance_pstore1; // @[DCache.scala:522:61, :528:78] wire _pstore2_storegen_data_T_23 = advance_pstore1; // @[DCache.scala:522:61, :528:78] wire _pstore2_storegen_data_T_27 = advance_pstore1; // @[DCache.scala:522:61, :528:78] wire _pstore2_storegen_data_T_31 = advance_pstore1; // @[DCache.scala:522:61, :528:78] wire _pstore2_storegen_mask_T = advance_pstore1; // @[DCache.scala:522:61, :532:27] wire _pstore2_valid_T = ~pstore_drain; // @[DCache.scala:516:27, :521:91, :523:37] wire _pstore2_valid_T_1 = pstore2_valid & _pstore2_valid_T; // @[DCache.scala:501:30, :523:{34,37}] wire _pstore2_valid_T_2 = _pstore2_valid_T_1 \| advance_pstore1; // @[DCache.scala:522:61, :523:{34,51}] reg [33:0] pstore2_addr; // @[DCache.scala:524:31] reg pstore2_way; // @[DCache.scala:525:30] wire [7:0] _pstore2_storegen_data_T = pstore1_storegen_data[7:0]; // @[DCache.scala:497:42, :528:44] wire _pstore2_storegen_data_T_1 = pstore1_mask[0]; // @[DCache.scala:496:31, :528:110] wire _s1_hazard_T_3 = pstore1_mask[0]; // @[package.scala:211:50] reg [7:0] pstore2_storegen_data_r; // @[DCache.scala:528:22] wire [7:0] _pstore2_storegen_data_T_4 = pstore1_storegen_data[15:8]; // @[DCache.scala:497:42, :528:44] wire _pstore2_storegen_data_T_5 = pstore1_mask[1]; // @[DCache.scala:496:31, :528:110] wire _s1_hazard_T_4 = pstore1_mask[1]; // @[package.scala:211:50] reg [7:0] pstore2_storegen_data_r_1; // @[DCache.scala:528:22] wire [7:0] _pstore2_storegen_data_T_8 = pstore1_storegen_data[23:16]; // @[DCache.scala:497:42, :528:44] wire _pstore2_storegen_data_T_9 = pstore1_mask[2]; // @[DCache.scala:496:31, :528:110] wire _s1_hazard_T_5 = pstore1_mask[2]; // @[package.scala:211:50] reg [7:0] pstore2_storegen_data_r_2; // @[DCache.scala:528:22] wire [7:0] _pstore2_storegen_data_T_12 = pstore1_storegen_data[31:24]; // @[DCache.scala:497:42, :528:44] wire _pstore2_storegen_data_T_13 = pstore1_mask[3]; // @[DCache.scala:496:31, :528:110] wire _s1_hazard_T_6 = pstore1_mask[3]; // @[package.scala:211:50] reg [7:0] pstore2_storegen_data_r_3; // @[DCache.scala:528:22] wire [7:0] _pstore2_storegen_data_T_16 = pstore1_storegen_data[39:32]; // @[DCache.scala:497:42, :528:44] wire _pstore2_storegen_data_T_17 = pstore1_mask[4]; // @[DCache.scala:496:31, :528:110] wire _s1_hazard_T_7 = pstore1_mask[4]; // @[package.scala:211:50] reg [7:0] pstore2_storegen_data_r_4; // @[DCache.scala:528:22] wire [7:0] _pstore2_storegen_data_T_20 = pstore1_storegen_data[47:40]; // @[DCache.scala:497:42, :528:44] wire _pstore2_storegen_data_T_21 = pstore1_mask[5]; // @[DCache.scala:496:31, :528:110] wire _s1_hazard_T_8 = pstore1_mask[5]; // @[package.scala:211:50] reg [7:0] pstore2_storegen_data_r_5; // @[DCache.scala:528:22] wire [7:0] _pstore2_storegen_data_T_24 = pstore1_storegen_data[55:48]; // @[DCache.scala:497:42, :528:44] wire _pstore2_storegen_data_T_25 = pstore1_mask[6]; // @[DCache.scala:496:31, :528:110] wire _s1_hazard_T_9 = pstore1_mask[6]; // @[package.scala:211:50] reg [7:0] pstore2_storegen_data_r_6; // @[DCache.scala:528:22] wire [7:0] _pstore2_storegen_data_T_28 = pstore1_storegen_data[63:56]; // @[DCache.scala:497:42, :528:44] wire _pstore2_storegen_data_T_29 = pstore1_mask[7]; // @[DCache.scala:496:31, :528:110] wire _s1_hazard_T_10 = pstore1_mask[7]; // @[package.scala:211:50] reg [7:0] pstore2_storegen_data_r_7; // @[DCache.scala:528:22] wire [15:0] pstore2_storegen_data_lo_lo = {pstore2_storegen_data_r_1, pstore2_storegen_data_r}; // @[package.scala:45:27] wire [15:0] pstore2_storegen_data_lo_hi = {pstore2_storegen_data_r_3, pstore2_storegen_data_r_2}; // @[package.scala:45:27] wire [31:0] pstore2_storegen_data_lo = {pstore2_storegen_data_lo_hi, pstore2_storegen_data_lo_lo}; // @[package.scala:45:27] wire [15:0] pstore2_storegen_data_hi_lo = {pstore2_storegen_data_r_5, pstore2_storegen_data_r_4}; // @[package.scala:45:27] wire [15:0] pstore2_storegen_data_hi_hi = {pstore2_storegen_data_r_7, pstore2_storegen_data_r_6}; // @[package.scala:45:27] wire [31:0] pstore2_storegen_data_hi = {pstore2_storegen_data_hi_hi, pstore2_storegen_data_hi_lo}; // @[package.scala:45:27] wire [63:0] pstore2_storegen_data = {pstore2_storegen_data_hi, pstore2_storegen_data_lo}; // @[package.scala:45:27] reg [7:0] pstore2_storegen_mask; // @[DCache.scala:531:19] wire [7:0] _pstore2_storegen_mask_mask_T = ~pstore2_storegen_mask_mergedMask; // @[DCache.scala:533:37, :534:37] wire [7:0] _pstore2_storegen_mask_mask_T_1 = _pstore2_storegen_mask_mask_T; // @[DCache.scala:534:{19,37}] wire [7:0] _pstore2_storegen_mask_mask_T_2 = ~_pstore2_storegen_mask_mask_T_1; // @[DCache.scala:534:{15,19}] wire _dataArb_io_in_0_valid_T_4 = _dataArb_io_in_0_valid_T_2; // @[DCache.scala:506:{72,84}] wire _dataArb_io_in_0_valid_T_5 = _dataArb_io_in_0_valid_T_4 \| pstore1_held; // @[DCache.scala:504:29, :506:{84,96}] wire _dataArb_io_in_0_valid_T_6 = ~pstore1_rmw; // @[DCache.scala:498:32, :518:44] wire _dataArb_io_in_0_valid_T_7 = _dataArb_io_in_0_valid_T_5 & _dataArb_io_in_0_valid_T_6; // @[DCache.scala:506:96, :518:{41,44}] wire _dataArb_io_in_0_valid_T_8 = _dataArb_io_in_0_valid_T_7 \| pstore2_valid; // @[DCache.scala:501:30, :518:{41,58}] wire _dataArb_io_in_0_valid_T_10 = _dataArb_io_in_0_valid_T_8 & _dataArb_io_in_0_valid_T_9; // @[DCache.scala:518:{58,76,107}] wire _dataArb_io_in_0_valid_T_11 = _dataArb_io_in_0_valid_T_1 \| _dataArb_io_in_0_valid_T_10; // @[DCache.scala:517:{17,44}, :518:76] assign _dataArb_io_in_0_valid_T_12 = _dataArb_io_in_0_valid_T_11; // @[DCache.scala:516:27, :517:44] assign dataArb_io_in_0_valid = _dataArb_io_in_0_valid_T_12; // @[DCache.scala:152:28, :516:27] wire [33:0] _GEN_90 = pstore2_valid ? pstore2_addr : pstore1_addr; // @[DCache.scala:493:31, :501:30, :524:31, :549:36] wire [33:0] _dataArb_io_in_0_bits_addr_T; // @[DCache.scala:549:36] assign _dataArb_io_in_0_bits_addr_T = _GEN_90; // @[DCache.scala:549:36] wire [33:0] _dataArb_io_in_0_bits_wordMask_wordMask_T; // @[DCache.scala:554:32] assign _dataArb_io_in_0_bits_wordMask_wordMask_T = _GEN_90; // @[DCache.scala:549:36, :554:32] assign dataArb_io_in_0_bits_addr = _dataArb_io_in_0_bits_addr_T[13:0]; // @[DCache.scala:152:28, :549:{30,36}] assign dataArb_io_in_1_bits_addr = _dataArb_io_in_0_bits_addr_T[13:0]; // @[DCache.scala:152:28, :549:{30,36}] assign _dataArb_io_in_0_bits_way_en_T = pstore2_valid ? pstore2_way : pstore1_way; // @[DCache.scala:495:30, :501:30, :525:30, :550:38] assign dataArb_io_in_0_bits_way_en = _dataArb_io_in_0_bits_way_en_T; // @[DCache.scala:152:28, :550:38] assign dataArb_io_in_1_bits_way_en = _dataArb_io_in_0_bits_way_en_T; // @[DCache.scala:152:28, :550:38] wire [63:0] _dataArb_io_in_0_bits_wdata_T = pstore2_valid ? pstore2_storegen_data : pstore1_data; // @[package.scala:45:27] wire [7:0] _dataArb_io_in_0_bits_wdata_T_1 = _dataArb_io_in_0_bits_wdata_T[7:0]; // @[package.scala:211:50] wire [7:0] _dataArb_io_in_0_bits_wdata_T_2 = _dataArb_io_in_0_bits_wdata_T[15:8]; // @[package.scala:211:50] wire [7:0] _dataArb_io_in_0_bits_wdata_T_3 = _dataArb_io_in_0_bits_wdata_T[23:16]; // @[package.scala:211:50] wire [7:0] _dataArb_io_in_0_bits_wdata_T_4 = _dataArb_io_in_0_bits_wdata_T[31:24]; // @[package.scala:211:50] wire [7:0] _dataArb_io_in_0_bits_wdata_T_5 = _dataArb_io_in_0_bits_wdata_T[39:32]; // @[package.scala:211:50] wire [7:0] _dataArb_io_in_0_bits_wdata_T_6 = _dataArb_io_in_0_bits_wdata_T[47:40]; // @[package.scala:211:50] wire [7:0] _dataArb_io_in_0_bits_wdata_T_7 = _dataArb_io_in_0_bits_wdata_T[55:48]; // @[package.scala:211:50] wire [7:0] _dataArb_io_in_0_bits_wdata_T_8 = _dataArb_io_in_0_bits_wdata_T[63:56]; // @[package.scala:211:50] wire [15:0] dataArb_io_in_0_bits_wdata_lo_lo = {_dataArb_io_in_0_bits_wdata_T_2, _dataArb_io_in_0_bits_wdata_T_1}; // @[package.scala:45:27, :211:50] wire [15:0] dataArb_io_in_0_bits_wdata_lo_hi = {_dataArb_io_in_0_bits_wdata_T_4, _dataArb_io_in_0_bits_wdata_T_3}; // @[package.scala:45:27, :211:50] wire [31:0] dataArb_io_in_0_bits_wdata_lo = {dataArb_io_in_0_bits_wdata_lo_hi, dataArb_io_in_0_bits_wdata_lo_lo}; // @[package.scala:45:27] wire [15:0] dataArb_io_in_0_bits_wdata_hi_lo = {_dataArb_io_in_0_bits_wdata_T_6, _dataArb_io_in_0_bits_wdata_T_5}; // @[package.scala:45:27, :211:50] wire [15:0] dataArb_io_in_0_bits_wdata_hi_hi = {_dataArb_io_in_0_bits_wdata_T_8, _dataArb_io_in_0_bits_wdata_T_7}; // @[package.scala:45:27, :211:50] wire [31:0] dataArb_io_in_0_bits_wdata_hi = {dataArb_io_in_0_bits_wdata_hi_hi, dataArb_io_in_0_bits_wdata_hi_lo}; // @[package.scala:45:27] assign _dataArb_io_in_0_bits_wdata_T_9 = {dataArb_io_in_0_bits_wdata_hi, dataArb_io_in_0_bits_wdata_lo}; // @[package.scala:45:27] assign dataArb_io_in_0_bits_wdata = _dataArb_io_in_0_bits_wdata_T_9; // @[package.scala:45:27] assign dataArb_io_in_1_bits_wdata = _dataArb_io_in_0_bits_wdata_T_9; // @[package.scala:45:27] assign dataArb_io_in_2_bits_wdata = _dataArb_io_in_0_bits_wdata_T_9; // @[package.scala:45:27] assign dataArb_io_in_3_bits_wdata = _dataArb_io_in_0_bits_wdata_T_9; // @[package.scala:45:27] wire _dataArb_io_in_0_bits_wordMask_eccMask_T = _dataArb_io_in_0_bits_eccMask_T_17[0]; // @[package.scala:45:27] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_1 = _dataArb_io_in_0_bits_eccMask_T_17[1]; // @[package.scala:45:27] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_2 = _dataArb_io_in_0_bits_eccMask_T_17[2]; // @[package.scala:45:27] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_3 = _dataArb_io_in_0_bits_eccMask_T_17[3]; // @[package.scala:45:27] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_4 = _dataArb_io_in_0_bits_eccMask_T_17[4]; // @[package.scala:45:27] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_5 = _dataArb_io_in_0_bits_eccMask_T_17[5]; // @[package.scala:45:27] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_6 = _dataArb_io_in_0_bits_eccMask_T_17[6]; // @[package.scala:45:27] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_7 = _dataArb_io_in_0_bits_eccMask_T_17[7]; // @[package.scala:45:27] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_8 = _dataArb_io_in_0_bits_wordMask_eccMask_T \| _dataArb_io_in_0_bits_wordMask_eccMask_T_1; // @[package.scala:81:59] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_9 = _dataArb_io_in_0_bits_wordMask_eccMask_T_8 \| _dataArb_io_in_0_bits_wordMask_eccMask_T_2; // @[package.scala:81:59] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_10 = _dataArb_io_in_0_bits_wordMask_eccMask_T_9 \| _dataArb_io_in_0_bits_wordMask_eccMask_T_3; // @[package.scala:81:59] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_11 = _dataArb_io_in_0_bits_wordMask_eccMask_T_10 \| _dataArb_io_in_0_bits_wordMask_eccMask_T_4; // @[package.scala:81:59] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_12 = _dataArb_io_in_0_bits_wordMask_eccMask_T_11 \| _dataArb_io_in_0_bits_wordMask_eccMask_T_5; // @[package.scala:81:59] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_13 = _dataArb_io_in_0_bits_wordMask_eccMask_T_12 \| _dataArb_io_in_0_bits_wordMask_eccMask_T_6; // @[package.scala:81:59] wire dataArb_io_in_0_bits_wordMask_eccMask = _dataArb_io_in_0_bits_wordMask_eccMask_T_13 \| _dataArb_io_in_0_bits_wordMask_eccMask_T_7; // @[package.scala:81:59] wire [1:0] _dataArb_io_in_0_bits_wordMask_T_3 = {1'h0, dataArb_io_in_0_bits_wordMask_eccMask}; // @[package.scala:81:59] assign dataArb_io_in_0_bits_wordMask = _dataArb_io_in_0_bits_wordMask_T_3[0]; // @[DCache.scala:152:28, :552:34, :555:55] assign dataArb_io_in_1_bits_wordMask = _dataArb_io_in_0_bits_wordMask_T_3[0]; // @[DCache.scala:152:28, :552:34, :555:55] wire [7:0] _dataArb_io_in_0_bits_eccMask_T = pstore2_valid ? pstore2_storegen_mask : pstore1_mask; // @[DCache.scala:496:31, :501:30, :531:19, :557:47] wire _dataArb_io_in_0_bits_eccMask_T_1 = _dataArb_io_in_0_bits_eccMask_T[0]; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_9 = _dataArb_io_in_0_bits_eccMask_T_1; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_2 = _dataArb_io_in_0_bits_eccMask_T[1]; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_10 = _dataArb_io_in_0_bits_eccMask_T_2; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_3 = _dataArb_io_in_0_bits_eccMask_T[2]; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_11 = _dataArb_io_in_0_bits_eccMask_T_3; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_4 = _dataArb_io_in_0_bits_eccMask_T[3]; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_12 = _dataArb_io_in_0_bits_eccMask_T_4; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_5 = _dataArb_io_in_0_bits_eccMask_T[4]; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_13 = _dataArb_io_in_0_bits_eccMask_T_5; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_6 = _dataArb_io_in_0_bits_eccMask_T[5]; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_14 = _dataArb_io_in_0_bits_eccMask_T_6; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_7 = _dataArb_io_in_0_bits_eccMask_T[6]; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_15 = _dataArb_io_in_0_bits_eccMask_T_7; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_8 = _dataArb_io_in_0_bits_eccMask_T[7]; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_16 = _dataArb_io_in_0_bits_eccMask_T_8; // @[package.scala:211:50] wire [1:0] dataArb_io_in_0_bits_eccMask_lo_lo = {_dataArb_io_in_0_bits_eccMask_T_10, _dataArb_io_in_0_bits_eccMask_T_9}; // @[package.scala:45:27] wire [1:0] dataArb_io_in_0_bits_eccMask_lo_hi = {_dataArb_io_in_0_bits_eccMask_T_12, _dataArb_io_in_0_bits_eccMask_T_11}; // @[package.scala:45:27] wire [3:0] dataArb_io_in_0_bits_eccMask_lo = {dataArb_io_in_0_bits_eccMask_lo_hi, dataArb_io_in_0_bits_eccMask_lo_lo}; // @[package.scala:45:27] wire [1:0] dataArb_io_in_0_bits_eccMask_hi_lo = {_dataArb_io_in_0_bits_eccMask_T_14, _dataArb_io_in_0_bits_eccMask_T_13}; // @[package.scala:45:27] wire [1:0] dataArb_io_in_0_bits_eccMask_hi_hi = {_dataArb_io_in_0_bits_eccMask_T_16, _dataArb_io_in_0_bits_eccMask_T_15}; // @[package.scala:45:27] wire [3:0] dataArb_io_in_0_bits_eccMask_hi = {dataArb_io_in_0_bits_eccMask_hi_hi, dataArb_io_in_0_bits_eccMask_hi_lo}; // @[package.scala:45:27] assign _dataArb_io_in_0_bits_eccMask_T_17 = {dataArb_io_in_0_bits_eccMask_hi, dataArb_io_in_0_bits_eccMask_lo}; // @[package.scala:45:27] assign dataArb_io_in_0_bits_eccMask = _dataArb_io_in_0_bits_eccMask_T_17; // @[package.scala:45:27] assign dataArb_io_in_1_bits_eccMask = _dataArb_io_in_0_bits_eccMask_T_17; // @[package.scala:45:27] wire [10:0] _s1_hazard_T = pstore1_addr[13:3]; // @[DCache.scala:493:31, :561:9] wire [10:0] _s1_hazard_T_1 = s1_vaddr[13:3]; // @[DCache.scala:197:21, :561:43] wire [10:0] _s1_hazard_T_63 = s1_vaddr[13:3]; // @[DCache.scala:197:21, :561:43] wire _s1_hazard_T_2 = _s1_hazard_T == _s1_hazard_T_1; // @[DCache.scala:561:{9,31,43}] wire _s1_hazard_T_11 = _s1_hazard_T_3; // @[package.scala:211:50] wire _s1_hazard_T_12 = _s1_hazard_T_4; // @[package.scala:211:50] wire _s1_hazard_T_13 = _s1_hazard_T_5; // @[package.scala:211:50] wire _s1_hazard_T_14 = _s1_hazard_T_6; // @[package.scala:211:50] wire _s1_hazard_T_15 = _s1_hazard_T_7; // @[package.scala:211:50] wire _s1_hazard_T_16 = _s1_hazard_T_8; // @[package.scala:211:50] wire _s1_hazard_T_17 = _s1_hazard_T_9; // @[package.scala:211:50] wire _s1_hazard_T_18 = _s1_hazard_T_10; // @[package.scala:211:50] wire [1:0] s1_hazard_lo_lo = {_s1_hazard_T_12, _s1_hazard_T_11}; // @[package.scala:45:27] wire [1:0] s1_hazard_lo_hi = {_s1_hazard_T_14, _s1_hazard_T_13}; // @[package.scala:45:27] wire [3:0] s1_hazard_lo = {s1_hazard_lo_hi, s1_hazard_lo_lo}; // @[package.scala:45:27] wire [1:0] s1_hazard_hi_lo = {_s1_hazard_T_16, _s1_hazard_T_15}; // @[package.scala:45:27] wire [1:0] s1_hazard_hi_hi = {_s1_hazard_T_18, _s1_hazard_T_17}; // @[package.scala:45:27] wire [3:0] s1_hazard_hi = {s1_hazard_hi_hi, s1_hazard_hi_lo}; // @[package.scala:45:27] wire [7:0] _s1_hazard_T_19 = {s1_hazard_hi, s1_hazard_lo}; // @[package.scala:45:27] wire _s1_hazard_T_20 = _s1_hazard_T_19[0]; // @[package.scala:45:27] wire _s1_hazard_T_21 = _s1_hazard_T_19[1]; // @[package.scala:45:27] wire _s1_hazard_T_22 = _s1_hazard_T_19[2]; // @[package.scala:45:27] wire _s1_hazard_T_23 = _s1_hazard_T_19[3]; // @[package.scala:45:27] wire _s1_hazard_T_24 = _s1_hazard_T_19[4]; // @[package.scala:45:27] wire _s1_hazard_T_25 = _s1_hazard_T_19[5]; // @[package.scala:45:27] wire _s1_hazard_T_26 = _s1_hazard_T_19[6]; // @[package.scala:45:27] wire _s1_hazard_T_27 = _s1_hazard_T_19[7]; // @[package.scala:45:27] wire [1:0] s1_hazard_lo_lo_1 = {_s1_hazard_T_21, _s1_hazard_T_20}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_lo_hi_1 = {_s1_hazard_T_23, _s1_hazard_T_22}; // @[DCache.scala:1182:52] wire [3:0] s1_hazard_lo_1 = {s1_hazard_lo_hi_1, s1_hazard_lo_lo_1}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_hi_lo_1 = {_s1_hazard_T_25, _s1_hazard_T_24}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_hi_hi_1 = {_s1_hazard_T_27, _s1_hazard_T_26}; // @[DCache.scala:1182:52] wire [3:0] s1_hazard_hi_1 = {s1_hazard_hi_hi_1, s1_hazard_hi_lo_1}; // @[DCache.scala:1182:52] wire [7:0] _s1_hazard_T_28 = {s1_hazard_hi_1, s1_hazard_lo_1}; // @[DCache.scala:1182:52] wire _s1_hazard_T_29 = s1_mask_xwr[0]; // @[package.scala:211:50] wire _s1_hazard_T_91 = s1_mask_xwr[0]; // @[package.scala:211:50] wire _s1_hazard_T_37 = _s1_hazard_T_29; // @[package.scala:211:50] wire _s1_hazard_T_30 = s1_mask_xwr[1]; // @[package.scala:211:50] wire _s1_hazard_T_92 = s1_mask_xwr[1]; // @[package.scala:211:50] wire _s1_hazard_T_38 = _s1_hazard_T_30; // @[package.scala:211:50] wire _s1_hazard_T_31 = s1_mask_xwr[2]; // @[package.scala:211:50] wire _s1_hazard_T_93 = s1_mask_xwr[2]; // @[package.scala:211:50] wire _s1_hazard_T_39 = _s1_hazard_T_31; // @[package.scala:211:50] wire _s1_hazard_T_32 = s1_mask_xwr[3]; // @[package.scala:211:50] wire _s1_hazard_T_94 = s1_mask_xwr[3]; // @[package.scala:211:50] wire _s1_hazard_T_40 = _s1_hazard_T_32; // @[package.scala:211:50] wire _s1_hazard_T_33 = s1_mask_xwr[4]; // @[package.scala:211:50] wire _s1_hazard_T_95 = s1_mask_xwr[4]; // @[package.scala:211:50] wire _s1_hazard_T_41 = _s1_hazard_T_33; // @[package.scala:211:50] wire _s1_hazard_T_34 = s1_mask_xwr[5]; // @[package.scala:211:50] wire _s1_hazard_T_96 = s1_mask_xwr[5]; // @[package.scala:211:50] wire _s1_hazard_T_42 = _s1_hazard_T_34; // @[package.scala:211:50] wire _s1_hazard_T_35 = s1_mask_xwr[6]; // @[package.scala:211:50] wire _s1_hazard_T_97 = s1_mask_xwr[6]; // @[package.scala:211:50] wire _s1_hazard_T_43 = _s1_hazard_T_35; // @[package.scala:211:50] wire _s1_hazard_T_36 = s1_mask_xwr[7]; // @[package.scala:211:50] wire _s1_hazard_T_98 = s1_mask_xwr[7]; // @[package.scala:211:50] wire _s1_hazard_T_44 = _s1_hazard_T_36; // @[package.scala:211:50] wire [1:0] s1_hazard_lo_lo_2 = {_s1_hazard_T_38, _s1_hazard_T_37}; // @[package.scala:45:27] wire [1:0] s1_hazard_lo_hi_2 = {_s1_hazard_T_40, _s1_hazard_T_39}; // @[package.scala:45:27] wire [3:0] s1_hazard_lo_2 = {s1_hazard_lo_hi_2, s1_hazard_lo_lo_2}; // @[package.scala:45:27] wire [1:0] s1_hazard_hi_lo_2 = {_s1_hazard_T_42, _s1_hazard_T_41}; // @[package.scala:45:27] wire [1:0] s1_hazard_hi_hi_2 = {_s1_hazard_T_44, _s1_hazard_T_43}; // @[package.scala:45:27] wire [3:0] s1_hazard_hi_2 = {s1_hazard_hi_hi_2, s1_hazard_hi_lo_2}; // @[package.scala:45:27] wire [7:0] _s1_hazard_T_45 = {s1_hazard_hi_2, s1_hazard_lo_2}; // @[package.scala:45:27] wire _s1_hazard_T_46 = _s1_hazard_T_45[0]; // @[package.scala:45:27] wire _s1_hazard_T_47 = _s1_hazard_T_45[1]; // @[package.scala:45:27] wire _s1_hazard_T_48 = _s1_hazard_T_45[2]; // @[package.scala:45:27] wire _s1_hazard_T_49 = _s1_hazard_T_45[3]; // @[package.scala:45:27] wire _s1_hazard_T_50 = _s1_hazard_T_45[4]; // @[package.scala:45:27] wire _s1_hazard_T_51 = _s1_hazard_T_45[5]; // @[package.scala:45:27] wire _s1_hazard_T_52 = _s1_hazard_T_45[6]; // @[package.scala:45:27] wire _s1_hazard_T_53 = _s1_hazard_T_45[7]; // @[package.scala:45:27] wire [1:0] s1_hazard_lo_lo_3 = {_s1_hazard_T_47, _s1_hazard_T_46}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_lo_hi_3 = {_s1_hazard_T_49, _s1_hazard_T_48}; // @[DCache.scala:1182:52] wire [3:0] s1_hazard_lo_3 = {s1_hazard_lo_hi_3, s1_hazard_lo_lo_3}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_hi_lo_3 = {_s1_hazard_T_51, _s1_hazard_T_50}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_hi_hi_3 = {_s1_hazard_T_53, _s1_hazard_T_52}; // @[DCache.scala:1182:52] wire [3:0] s1_hazard_hi_3 = {s1_hazard_hi_hi_3, s1_hazard_hi_lo_3}; // @[DCache.scala:1182:52] wire [7:0] _s1_hazard_T_54 = {s1_hazard_hi_3, s1_hazard_lo_3}; // @[DCache.scala:1182:52] wire [7:0] _s1_hazard_T_55 = _s1_hazard_T_28 & _s1_hazard_T_54; // @[DCache.scala:562:38, :1182:52] wire _s1_hazard_T_56 = \|_s1_hazard_T_55; // @[DCache.scala:562:{38,66}] wire [7:0] _s1_hazard_T_57 = pstore1_mask & s1_mask_xwr; // @[DCache.scala:496:31, :562:77] wire _s1_hazard_T_58 = \|_s1_hazard_T_57; // @[DCache.scala:562:{77,92}] wire _s1_hazard_T_59 = s1_write ? _s1_hazard_T_56 : _s1_hazard_T_58; // @[DCache.scala:562:{8,66,92}] wire _s1_hazard_T_60 = _s1_hazard_T_2 & _s1_hazard_T_59; // @[DCache.scala:561:{31,65}, :562:8] wire _s1_hazard_T_61 = pstore1_valid_likely & _s1_hazard_T_60; // @[DCache.scala:505:51, :561:65, :564:27] wire [10:0] _s1_hazard_T_62 = pstore2_addr[13:3]; // @[DCache.scala:524:31, :561:9] wire _s1_hazard_T_64 = _s1_hazard_T_62 == _s1_hazard_T_63; // @[DCache.scala:561:{9,31,43}] wire _s1_hazard_T_65 = pstore2_storegen_mask[0]; // @[package.scala:211:50] wire _s1_hazard_T_73 = _s1_hazard_T_65; // @[package.scala:211:50] wire _s1_hazard_T_66 = pstore2_storegen_mask[1]; // @[package.scala:211:50] wire _s1_hazard_T_74 = _s1_hazard_T_66; // @[package.scala:211:50] wire _s1_hazard_T_67 = pstore2_storegen_mask[2]; // @[package.scala:211:50] wire _s1_hazard_T_75 = _s1_hazard_T_67; // @[package.scala:211:50] wire _s1_hazard_T_68 = pstore2_storegen_mask[3]; // @[package.scala:211:50] wire _s1_hazard_T_76 = _s1_hazard_T_68; // @[package.scala:211:50] wire _s1_hazard_T_69 = pstore2_storegen_mask[4]; // @[package.scala:211:50] wire _s1_hazard_T_77 = _s1_hazard_T_69; // @[package.scala:211:50] wire _s1_hazard_T_70 = pstore2_storegen_mask[5]; // @[package.scala:211:50] wire _s1_hazard_T_78 = _s1_hazard_T_70; // @[package.scala:211:50] wire _s1_hazard_T_71 = pstore2_storegen_mask[6]; // @[package.scala:211:50] wire _s1_hazard_T_79 = _s1_hazard_T_71; // @[package.scala:211:50] wire _s1_hazard_T_72 = pstore2_storegen_mask[7]; // @[package.scala:211:50] wire _s1_hazard_T_80 = _s1_hazard_T_72; // @[package.scala:211:50] wire [1:0] s1_hazard_lo_lo_4 = {_s1_hazard_T_74, _s1_hazard_T_73}; // @[package.scala:45:27] wire [1:0] s1_hazard_lo_hi_4 = {_s1_hazard_T_76, _s1_hazard_T_75}; // @[package.scala:45:27] wire [3:0] s1_hazard_lo_4 = {s1_hazard_lo_hi_4, s1_hazard_lo_lo_4}; // @[package.scala:45:27] wire [1:0] s1_hazard_hi_lo_4 = {_s1_hazard_T_78, _s1_hazard_T_77}; // @[package.scala:45:27] wire [1:0] s1_hazard_hi_hi_4 = {_s1_hazard_T_80, _s1_hazard_T_79}; // @[package.scala:45:27] wire [3:0] s1_hazard_hi_4 = {s1_hazard_hi_hi_4, s1_hazard_hi_lo_4}; // @[package.scala:45:27] wire [7:0] _s1_hazard_T_81 = {s1_hazard_hi_4, s1_hazard_lo_4}; // @[package.scala:45:27] wire _s1_hazard_T_82 = _s1_hazard_T_81[0]; // @[package.scala:45:27] wire _s1_hazard_T_83 = _s1_hazard_T_81[1]; // @[package.scala:45:27] wire _s1_hazard_T_84 = _s1_hazard_T_81[2]; // @[package.scala:45:27] wire _s1_hazard_T_85 = _s1_hazard_T_81[3]; // @[package.scala:45:27] wire _s1_hazard_T_86 = _s1_hazard_T_81[4]; // @[package.scala:45:27] wire _s1_hazard_T_87 = _s1_hazard_T_81[5]; // @[package.scala:45:27] wire _s1_hazard_T_88 = _s1_hazard_T_81[6]; // @[package.scala:45:27] wire _s1_hazard_T_89 = _s1_hazard_T_81[7]; // @[package.scala:45:27] wire [1:0] s1_hazard_lo_lo_5 = {_s1_hazard_T_83, _s1_hazard_T_82}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_lo_hi_5 = {_s1_hazard_T_85, _s1_hazard_T_84}; // @[DCache.scala:1182:52] wire [3:0] s1_hazard_lo_5 = {s1_hazard_lo_hi_5, s1_hazard_lo_lo_5}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_hi_lo_5 = {_s1_hazard_T_87, _s1_hazard_T_86}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_hi_hi_5 = {_s1_hazard_T_89, _s1_hazard_T_88}; // @[DCache.scala:1182:52] wire [3:0] s1_hazard_hi_5 = {s1_hazard_hi_hi_5, s1_hazard_hi_lo_5}; // @[DCache.scala:1182:52] wire [7:0] _s1_hazard_T_90 = {s1_hazard_hi_5, s1_hazard_lo_5}; // @[DCache.scala:1182:52] wire _s1_hazard_T_99 = _s1_hazard_T_91; // @[package.scala:211:50] wire _s1_hazard_T_100 = _s1_hazard_T_92; // @[package.scala:211:50] wire _s1_hazard_T_101 = _s1_hazard_T_93; // @[package.scala:211:50] wire _s1_hazard_T_102 = _s1_hazard_T_94; // @[package.scala:211:50] wire _s1_hazard_T_103 = _s1_hazard_T_95; // @[package.scala:211:50] wire _s1_hazard_T_104 = _s1_hazard_T_96; // @[package.scala:211:50] wire _s1_hazard_T_105 = _s1_hazard_T_97; // @[package.scala:211:50] wire _s1_hazard_T_106 = _s1_hazard_T_98; // @[package.scala:211:50] wire [1:0] s1_hazard_lo_lo_6 = {_s1_hazard_T_100, _s1_hazard_T_99}; // @[package.scala:45:27] wire [1:0] s1_hazard_lo_hi_6 = {_s1_hazard_T_102, _s1_hazard_T_101}; // @[package.scala:45:27] wire [3:0] s1_hazard_lo_6 = {s1_hazard_lo_hi_6, s1_hazard_lo_lo_6}; // @[package.scala:45:27] wire [1:0] s1_hazard_hi_lo_6 = {_s1_hazard_T_104, _s1_hazard_T_103}; // @[package.scala:45:27] wire [1:0] s1_hazard_hi_hi_6 = {_s1_hazard_T_106, _s1_hazard_T_105}; // @[package.scala:45:27] wire [3:0] s1_hazard_hi_6 = {s1_hazard_hi_hi_6, s1_hazard_hi_lo_6}; // @[package.scala:45:27] wire [7:0] _s1_hazard_T_107 = {s1_hazard_hi_6, s1_hazard_lo_6}; // @[package.scala:45:27] wire _s1_hazard_T_108 = _s1_hazard_T_107[0]; // @[package.scala:45:27] wire _s1_hazard_T_109 = _s1_hazard_T_107[1]; // @[package.scala:45:27] wire _s1_hazard_T_110 = _s1_hazard_T_107[2]; // @[package.scala:45:27] wire _s1_hazard_T_111 = _s1_hazard_T_107[3]; // @[package.scala:45:27] wire _s1_hazard_T_112 = _s1_hazard_T_107[4]; // @[package.scala:45:27] wire _s1_hazard_T_113 = _s1_hazard_T_107[5]; // @[package.scala:45:27] wire _s1_hazard_T_114 = _s1_hazard_T_107[6]; // @[package.scala:45:27] wire _s1_hazard_T_115 = _s1_hazard_T_107[7]; // @[package.scala:45:27] wire [1:0] s1_hazard_lo_lo_7 = {_s1_hazard_T_109, _s1_hazard_T_108}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_lo_hi_7 = {_s1_hazard_T_111, _s1_hazard_T_110}; // @[DCache.scala:1182:52] wire [3:0] s1_hazard_lo_7 = {s1_hazard_lo_hi_7, s1_hazard_lo_lo_7}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_hi_lo_7 = {_s1_hazard_T_113, _s1_hazard_T_112}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_hi_hi_7 = {_s1_hazard_T_115, _s1_hazard_T_114}; // @[DCache.scala:1182:52] wire [3:0] s1_hazard_hi_7 = {s1_hazard_hi_hi_7, s1_hazard_hi_lo_7}; // @[DCache.scala:1182:52] wire [7:0] _s1_hazard_T_116 = {s1_hazard_hi_7, s1_hazard_lo_7}; // @[DCache.scala:1182:52] wire [7:0] _s1_hazard_T_117 = _s1_hazard_T_90 & _s1_hazard_T_116; // @[DCache.scala:562:38, :1182:52] wire _s1_hazard_T_118 = \|_s1_hazard_T_117; // @[DCache.scala:562:{38,66}] wire [7:0] _s1_hazard_T_119 = pstore2_storegen_mask & s1_mask_xwr; // @[DCache.scala:531:19, :562:77] wire _s1_hazard_T_120 = \|_s1_hazard_T_119; // @[DCache.scala:562:{77,92}] wire _s1_hazard_T_121 = s1_write ? _s1_hazard_T_118 : _s1_hazard_T_120; // @[DCache.scala:562:{8,66,92}] wire _s1_hazard_T_122 = _s1_hazard_T_64 & _s1_hazard_T_121; // @[DCache.scala:561:{31,65}, :562:8] wire _s1_hazard_T_123 = pstore2_valid & _s1_hazard_T_122; // @[DCache.scala:501:30, :561:65, :565:21] wire s1_hazard = _s1_hazard_T_61 \| _s1_hazard_T_123; // @[DCache.scala:564:{27,69}, :565:21] wire s1_raw_hazard = s1_read & s1_hazard; // @[DCache.scala:564:69, :566:31] assign s1_nack = s1_valid & s1_raw_hazard \| io_cpu_s2_nack_0 \| _metaArb_io_in_2_valid_T; // @[DCache.scala:101:7, :182:25, :185:28, :288:75, :446:{24,82,92}, :462:63, :566:31, :571:{18,36,46}] reg io_cpu_s2_nack_cause_raw_REG; // @[DCache.scala:574:38] assign _io_cpu_s2_nack_cause_raw_T_3 = io_cpu_s2_nack_cause_raw_REG; // @[DCache.scala:574:{38,54}] assign io_cpu_s2_nack_cause_raw_0 = _io_cpu_s2_nack_cause_raw_T_3; // @[DCache.scala:101:7, :574:54] wire _a_source_T = ~uncachedInFlight_0; // @[DCache.scala:236:33, :577:34] wire _a_source_T_1 = _a_source_T; // @[DCache.scala:577:{34,59}] wire _a_source_T_2 = _a_source_T_1; // @[OneHot.scala:48:45] wire [33:0] acquire_address = {_acquire_address_T, 6'h0}; // @[DCache.scala:578:{38,49}] wire [22:0] a_mask = {15'h0, pstore1_mask}; // @[DCache.scala:496:31, :582:29] wire [33:0] _GEN_91 = {s2_req_addr[33:14], _s2_vaddr_T_2 ^ 14'h3000}; // @[DCache.scala:339:19, :351:103, :467:68] wire [33:0] _get_legal_T_4; // @[Parameters.scala:137:31] assign _get_legal_T_4 = _GEN_91; // @[Parameters.scala:137:31] wire [33:0] _put_legal_T_4; // @[Parameters.scala:137:31] assign _put_legal_T_4 = _GEN_91; // @[Parameters.scala:137:31] wire [33:0] _putpartial_legal_T_4; // @[Parameters.scala:137:31] assign _putpartial_legal_T_4 = _GEN_91; // @[Parameters.scala:137:31] wire [34:0] _get_legal_T_5 = {1'h0, _get_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [34:0] _get_legal_T_6 = _get_legal_T_5 & 35'h8A113000; // @[Parameters.scala:137:{41,46}] wire [34:0] _get_legal_T_7 = _get_legal_T_6; // @[Parameters.scala:137:46] wire _get_legal_T_8 = _get_legal_T_7 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _get_legal_T_9 = _get_legal_T_8; // @[Parameters.scala:684:54] wire _get_legal_T_50 = _get_legal_T_9; // @[Parameters.scala:684:54, :686:26] wire [34:0] _get_legal_T_15 = {1'h0, _get_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [34:0] _get_legal_T_16 = _get_legal_T_15 & 35'h8A112000; // @[Parameters.scala:137:{41,46}] wire [34:0] _get_legal_T_17 = _get_legal_T_16; // @[Parameters.scala:137:46] wire _get_legal_T_18 = _get_legal_T_17 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [33:0] _GEN_92 = {s2_req_addr[33:17], s2_req_addr[16:0] ^ 17'h10000}; // @[DCache.scala:339:19] wire [33:0] _get_legal_T_19; // @[Parameters.scala:137:31] assign _get_legal_T_19 = _GEN_92; // @[Parameters.scala:137:31] wire [33:0] _put_legal_T_45; // @[Parameters.scala:137:31] assign _put_legal_T_45 = _GEN_92; // @[Parameters.scala:137:31] wire [33:0] _putpartial_legal_T_45; // @[Parameters.scala:137:31] assign _putpartial_legal_T_45 = _GEN_92; // @[Parameters.scala:137:31] wire [33:0] _atomics_legal_T_23; // @[Parameters.scala:137:31] assign _atomics_legal_T_23 = _GEN_92; // @[Parameters.scala:137:31] wire [33:0] _atomics_legal_T_53; // @[Parameters.scala:137:31] assign _atomics_legal_T_53 = _GEN_92; // @[Parameters.scala:137:31] wire [33:0] _atomics_legal_T_83; // @[Parameters.scala:137:31] assign _atomics_legal_T_83 = _GEN_92; // @[Parameters.scala:137:31] wire [33:0] _atomics_legal_T_113; // @[Parameters.scala:137:31] assign _atomics_legal_T_113 = _GEN_92; // @[Parameters.scala:137:31] wire [33:0] _atomics_legal_T_143; // @[Parameters.scala:137:31] assign _atomics_legal_T_143 = _GEN_92; // @[Parameters.scala:137:31] wire [33:0] _atomics_legal_T_173; // @[Parameters.scala:137:31] assign _atomics_legal_T_173 = _GEN_92; // @[Parameters.scala:137:31] wire [33:0] _atomics_legal_T_203; // @[Parameters.scala:137:31] assign _atomics_legal_T_203 = _GEN_92; // @[Parameters.scala:137:31] wire [33:0] _atomics_legal_T_233; // @[Parameters.scala:137:31] assign _atomics_legal_T_233 = _GEN_92; // @[Parameters.scala:137:31] wire [33:0] _atomics_legal_T_263; // @[Parameters.scala:137:31] assign _atomics_legal_T_263 = _GEN_92; // @[Parameters.scala:137:31] wire [34:0] _get_legal_T_20 = {1'h0, _get_legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [34:0] _get_legal_T_21 = _get_legal_T_20 & 35'h8A110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _get_legal_T_22 = _get_legal_T_21; // @[Parameters.scala:137:46] wire _get_legal_T_23 = _get_legal_T_22 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [33:0] _GEN_93 = {s2_req_addr[33:21], s2_req_addr[20:0] ^ 21'h100000}; // @[DCache.scala:339:19] wire [33:0] _get_legal_T_24; // @[Parameters.scala:137:31] assign _get_legal_T_24 = _GEN_93; // @[Parameters.scala:137:31] wire [33:0] _put_legal_T_19; // @[Parameters.scala:137:31] assign _put_legal_T_19 = _GEN_93; // @[Parameters.scala:137:31] wire [33:0] _putpartial_legal_T_19; // @[Parameters.scala:137:31] assign _putpartial_legal_T_19 = _GEN_93; // @[Parameters.scala:137:31] wire [33:0] _atomics_legal_T_9; // @[Parameters.scala:137:31] assign _atomics_legal_T_9 = _GEN_93; // @[Parameters.scala:137:31] wire [33:0] _atomics_legal_T_39; // @[Parameters.scala:137:31] assign _atomics_legal_T_39 = _GEN_93; // @[Parameters.scala:137:31] wire [33:0] _atomics_legal_T_69; // @[Parameters.scala:137:31] assign _atomics_legal_T_69 = _GEN_93; // @[Parameters.scala:137:31] wire [33:0] _atomics_legal_T_99; // @[Parameters.scala:137:31] assign _atomics_legal_T_99 = _GEN_93; // @[Parameters.scala:137:31] wire [33:0] _atomics_legal_T_129; // @[Parameters.scala:137:31] assign _atomics_legal_T_129 = _GEN_93; // @[Parameters.scala:137:31] wire [33:0] _atomics_legal_T_159; // @[Parameters.scala:137:31] assign _atomics_legal_T_159 = _GEN_93; // @[Parameters.scala:137:31] wire [33:0] _atomics_legal_T_189; // @[Parameters.scala:137:31] assign _atomics_legal_T_189 = _GEN_93; // @[Parameters.scala:137:31] wire [33:0] _atomics_legal_T_219; // @[Parameters.scala:137:31] assign _atomics_legal_T_219 = _GEN_93; // @[Parameters.scala:137:31] wire [33:0] _atomics_legal_T_249; // @[Parameters.scala:137:31] assign _atomics_legal_T_249 = _GEN_93; // @[Parameters.scala:137:31] wire [34:0] _get_legal_T_25 = {1'h0, _get_legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [34:0] _get_legal_T_26 = _get_legal_T_25 & 35'h8A103000; // @[Parameters.scala:137:{41,46}] wire [34:0] _get_legal_T_27 = _get_legal_T_26; // @[Parameters.scala:137:46] wire _get_legal_T_28 = _get_legal_T_27 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [33:0] _GEN_94 = {s2_req_addr[33:26], s2_req_addr[25:0] ^ 26'h2000000}; // @[DCache.scala:339:19] wire [33:0] _get_legal_T_29; // @[Parameters.scala:137:31] assign _get_legal_T_29 = _GEN_94; // @[Parameters.scala:137:31] wire [33:0] _put_legal_T_24; // @[Parameters.scala:137:31] assign _put_legal_T_24 = _GEN_94; // @[Parameters.scala:137:31] wire [33:0] _putpartial_legal_T_24; // @[Parameters.scala:137:31] assign _putpartial_legal_T_24 = _GEN_94; // @[Parameters.scala:137:31] wire [34:0] _get_legal_T_30 = {1'h0, _get_legal_T_29}; // @[Parameters.scala:137:{31,41}] wire [34:0] _get_legal_T_31 = _get_legal_T_30 & 35'h8A110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _get_legal_T_32 = _get_legal_T_31; // @[Parameters.scala:137:46] wire _get_legal_T_33 = _get_legal_T_32 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [33:0] _GEN_95 = {s2_req_addr[33:28], s2_req_addr[27:0] ^ 28'h8000000}; // @[DCache.scala:339:19] wire [33:0] _get_legal_T_34; // @[Parameters.scala:137:31] assign _get_legal_T_34 = _GEN_95; // @[Parameters.scala:137:31] wire [33:0] _put_legal_T_29; // @[Parameters.scala:137:31] assign _put_legal_T_29 = _GEN_95; // @[Parameters.scala:137:31] wire [33:0] _putpartial_legal_T_29; // @[Parameters.scala:137:31] assign _putpartial_legal_T_29 = _GEN_95; // @[Parameters.scala:137:31] wire [33:0] _atomics_legal_T_14; // @[Parameters.scala:137:31] assign _atomics_legal_T_14 = _GEN_95; // @[Parameters.scala:137:31] wire [33:0] _atomics_legal_T_44; // @[Parameters.scala:137:31] assign _atomics_legal_T_44 = _GEN_95; // @[Parameters.scala:137:31] wire [33:0] _atomics_legal_T_74; // @[Parameters.scala:137:31] assign _atomics_legal_T_74 = _GEN_95; // @[Parameters.scala:137:31] wire [33:0] _atomics_legal_T_104; // @[Parameters.scala:137:31] assign _atomics_legal_T_104 = _GEN_95; // @[Parameters.scala:137:31] wire [33:0] _atomics_legal_T_134; // @[Parameters.scala:137:31] assign _atomics_legal_T_134 = _GEN_95; // @[Parameters.scala:137:31] wire [33:0] _atomics_legal_T_164; // @[Parameters.scala:137:31] assign _atomics_legal_T_164 = _GEN_95; // @[Parameters.scala:137:31] wire [33:0] _atomics_legal_T_194; // @[Parameters.scala:137:31] assign _atomics_legal_T_194 = _GEN_95; // @[Parameters.scala:137:31] wire [33:0] _atomics_legal_T_224; // @[Parameters.scala:137:31] assign _atomics_legal_T_224 = _GEN_95; // @[Parameters.scala:137:31] wire [33:0] _atomics_legal_T_254; // @[Parameters.scala:137:31] assign _atomics_legal_T_254 = _GEN_95; // @[Parameters.scala:137:31] wire [34:0] _get_legal_T_35 = {1'h0, _get_legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [34:0] _get_legal_T_36 = _get_legal_T_35 & 35'h88000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _get_legal_T_37 = _get_legal_T_36; // @[Parameters.scala:137:46] wire _get_legal_T_38 = _get_legal_T_37 == 35'h0; // @[Parameters.scala:137:{46,59}] assign io_cpu_s2_paddr_0 = s2_req_addr[31:0]; // @[DCache.scala:101:7, :339:19] wire [31:0] get_address = s2_req_addr[31:0]; // @[Edges.scala:460:17] wire [31:0] put_address = s2_req_addr[31:0]; // @[Edges.scala:480:17] wire [31:0] putpartial_address = s2_req_addr[31:0]; // @[Edges.scala:500:17] wire [31:0] atomics_a_address = s2_req_addr[31:0]; // @[Edges.scala:534:17] wire [31:0] atomics_a_1_address = s2_req_addr[31:0]; // @[Edges.scala:534:17] wire [31:0] atomics_a_2_address = s2_req_addr[31:0]; // @[Edges.scala:534:17] wire [31:0] atomics_a_3_address = s2_req_addr[31:0]; // @[Edges.scala:534:17] wire [31:0] atomics_a_4_address = s2_req_addr[31:0]; // @[Edges.scala:517:17] wire [31:0] atomics_a_5_address = s2_req_addr[31:0]; // @[Edges.scala:517:17] wire [31:0] atomics_a_6_address = s2_req_addr[31:0]; // @[Edges.scala:517:17] wire [31:0] atomics_a_7_address = s2_req_addr[31:0]; // @[Edges.scala:517:17] wire [31:0] atomics_a_8_address = s2_req_addr[31:0]; // @[Edges.scala:517:17] wire [33:0] _GEN_96 = {s2_req_addr[33:32], s2_req_addr[31:0] ^ 32'h80000000}; // @[DCache.scala:339:19] wire [33:0] _get_legal_T_39; // @[Parameters.scala:137:31] assign _get_legal_T_39 = _GEN_96; // @[Parameters.scala:137:31] wire [33:0] _put_legal_T_34; // @[Parameters.scala:137:31] assign _put_legal_T_34 = _GEN_96; // @[Parameters.scala:137:31] wire [33:0] _putpartial_legal_T_34; // @[Parameters.scala:137:31] assign _putpartial_legal_T_34 = _GEN_96; // @[Parameters.scala:137:31] wire [34:0] _get_legal_T_40 = {1'h0, _get_legal_T_39}; // @[Parameters.scala:137:{31,41}] wire [34:0] _get_legal_T_41 = _get_legal_T_40 & 35'h8A110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _get_legal_T_42 = _get_legal_T_41; // @[Parameters.scala:137:46] wire _get_legal_T_43 = _get_legal_T_42 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _get_legal_T_44 = _get_legal_T_18 \| _get_legal_T_23; // @[Parameters.scala:685:42] wire _get_legal_T_45 = _get_legal_T_44 \| _get_legal_T_28; // @[Parameters.scala:685:42] wire _get_legal_T_46 = _get_legal_T_45 \| _get_legal_T_33; // @[Parameters.scala:685:42] wire _get_legal_T_47 = _get_legal_T_46 \| _get_legal_T_38; // @[Parameters.scala:685:42] wire _get_legal_T_48 = _get_legal_T_47 \| _get_legal_T_43; // @[Parameters.scala:685:42] wire _get_legal_T_49 = _get_legal_T_48; // @[Parameters.scala:684:54, :685:42] wire get_legal = _get_legal_T_50 \| _get_legal_T_49; // @[Parameters.scala:684:54, :686:26] wire [7:0] _get_a_mask_T; // @[Misc.scala:222:10] wire [3:0] get_size; // @[Edges.scala:460:17] wire [7:0] get_mask; // @[Edges.scala:460:17] wire [3:0] _GEN_97 = {2'h0, s2_req_size}; // @[Edges.scala:463:15] assign get_size = _GEN_97; // @[Edges.scala:460:17, :463:15] wire [3:0] put_size; // @[Edges.scala:480:17] assign put_size = _GEN_97; // @[Edges.scala:463:15, :480:17] wire [3:0] putpartial_size; // @[Edges.scala:500:17] assign putpartial_size = _GEN_97; // @[Edges.scala:463:15, :500:17] wire [3:0] atomics_a_size; // @[Edges.scala:534:17] assign atomics_a_size = _GEN_97; // @[Edges.scala:463:15, :534:17] wire [3:0] atomics_a_1_size; // @[Edges.scala:534:17] assign atomics_a_1_size = _GEN_97; // @[Edges.scala:463:15, :534:17] wire [3:0] atomics_a_2_size; // @[Edges.scala:534:17] assign atomics_a_2_size = _GEN_97; // @[Edges.scala:463:15, :534:17] wire [3:0] atomics_a_3_size; // @[Edges.scala:534:17] assign atomics_a_3_size = _GEN_97; // @[Edges.scala:463:15, :534:17] wire [3:0] atomics_a_4_size; // @[Edges.scala:517:17] assign atomics_a_4_size = _GEN_97; // @[Edges.scala:463:15, :517:17] wire [3:0] atomics_a_5_size; // @[Edges.scala:517:17] assign atomics_a_5_size = _GEN_97; // @[Edges.scala:463:15, :517:17] wire [3:0] atomics_a_6_size; // @[Edges.scala:517:17] assign atomics_a_6_size = _GEN_97; // @[Edges.scala:463:15, :517:17] wire [3:0] atomics_a_7_size; // @[Edges.scala:517:17] assign atomics_a_7_size = _GEN_97; // @[Edges.scala:463:15, :517:17] wire [3:0] atomics_a_8_size; // @[Edges.scala:517:17] assign atomics_a_8_size = _GEN_97; // @[Edges.scala:463:15, :517:17] wire [2:0] _GEN_98 = {1'h0, s2_req_size}; // @[Misc.scala:202:34] wire [2:0] _get_a_mask_sizeOH_T; // @[Misc.scala:202:34] assign _get_a_mask_sizeOH_T = _GEN_98; // @[Misc.scala:202:34] wire [2:0] _put_a_mask_sizeOH_T; // @[Misc.scala:202:34] assign _put_a_mask_sizeOH_T = _GEN_98; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T = _GEN_98; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T_3; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_3 = _GEN_98; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T_6; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_6 = _GEN_98; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T_9; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_9 = _GEN_98; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T_12; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_12 = _GEN_98; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T_15; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_15 = _GEN_98; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T_18; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_18 = _GEN_98; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T_21; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_21 = _GEN_98; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T_24; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_24 = _GEN_98; // @[Misc.scala:202:34] wire [1:0] get_a_mask_sizeOH_shiftAmount = _get_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _get_a_mask_sizeOH_T_1 = 4'h1 << get_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _get_a_mask_sizeOH_T_2 = _get_a_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] get_a_mask_sizeOH = {_get_a_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire get_a_mask_sub_sub_sub_0_1 = &s2_req_size; // @[Misc.scala:206:21] wire get_a_mask_sub_sub_size = get_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire get_a_mask_sub_sub_bit = s2_req_addr[2]; // @[Misc.scala:210:26] wire put_a_mask_sub_sub_bit = s2_req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit = s2_req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_1 = s2_req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_2 = s2_req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_3 = s2_req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_4 = s2_req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_5 = s2_req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_6 = s2_req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_7 = s2_req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_8 = s2_req_addr[2]; // @[Misc.scala:210:26] wire _io_cpu_resp_bits_data_shifted_T = s2_req_addr[2]; // @[Misc.scala:210:26] wire _io_cpu_resp_bits_data_word_bypass_shifted_T = s2_req_addr[2]; // @[Misc.scala:210:26] wire get_a_mask_sub_sub_1_2 = get_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire get_a_mask_sub_sub_nbit = ~get_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire get_a_mask_sub_sub_0_2 = get_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_sub_sub_acc_T = get_a_mask_sub_sub_size & get_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_sub_0_1 = get_a_mask_sub_sub_sub_0_1 \| _get_a_mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _get_a_mask_sub_sub_acc_T_1 = get_a_mask_sub_sub_size & get_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_sub_1_1 = get_a_mask_sub_sub_sub_0_1 \| _get_a_mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire get_a_mask_sub_size = get_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire get_a_mask_sub_bit = s2_req_addr[1]; // @[Misc.scala:210:26] wire put_a_mask_sub_bit = s2_req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit = s2_req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_1 = s2_req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_2 = s2_req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_3 = s2_req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_4 = s2_req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_5 = s2_req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_6 = s2_req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_7 = s2_req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_8 = s2_req_addr[1]; // @[Misc.scala:210:26] wire _io_cpu_resp_bits_data_shifted_T_3 = s2_req_addr[1]; // @[Misc.scala:210:26] wire get_a_mask_sub_nbit = ~get_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire get_a_mask_sub_0_2 = get_a_mask_sub_sub_0_2 & get_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_sub_acc_T = get_a_mask_sub_size & get_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_0_1 = get_a_mask_sub_sub_0_1 \| _get_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_1_2 = get_a_mask_sub_sub_0_2 & get_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_sub_acc_T_1 = get_a_mask_sub_size & get_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_1_1 = get_a_mask_sub_sub_0_1 \| _get_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_2_2 = get_a_mask_sub_sub_1_2 & get_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_sub_acc_T_2 = get_a_mask_sub_size & get_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_2_1 = get_a_mask_sub_sub_1_1 \| _get_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_3_2 = get_a_mask_sub_sub_1_2 & get_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_sub_acc_T_3 = get_a_mask_sub_size & get_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_3_1 = get_a_mask_sub_sub_1_1 \| _get_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire get_a_mask_size = get_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire get_a_mask_bit = s2_req_addr[0]; // @[Misc.scala:210:26] wire put_a_mask_bit = s2_req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit = s2_req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_1 = s2_req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_2 = s2_req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_3 = s2_req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_4 = s2_req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_5 = s2_req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_6 = s2_req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_7 = s2_req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_8 = s2_req_addr[0]; // @[Misc.scala:210:26] wire _io_cpu_resp_bits_data_shifted_T_6 = s2_req_addr[0]; // @[Misc.scala:210:26] wire get_a_mask_nbit = ~get_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire get_a_mask_eq = get_a_mask_sub_0_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T = get_a_mask_size & get_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc = get_a_mask_sub_0_1 \| _get_a_mask_acc_T; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_1 = get_a_mask_sub_0_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_1 = get_a_mask_size & get_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_1 = get_a_mask_sub_0_1 \| _get_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_2 = get_a_mask_sub_1_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T_2 = get_a_mask_size & get_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_2 = get_a_mask_sub_1_1 \| _get_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_3 = get_a_mask_sub_1_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_3 = get_a_mask_size & get_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_3 = get_a_mask_sub_1_1 \| _get_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_4 = get_a_mask_sub_2_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T_4 = get_a_mask_size & get_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_4 = get_a_mask_sub_2_1 \| _get_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_5 = get_a_mask_sub_2_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_5 = get_a_mask_size & get_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_5 = get_a_mask_sub_2_1 \| _get_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_6 = get_a_mask_sub_3_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T_6 = get_a_mask_size & get_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_6 = get_a_mask_sub_3_1 \| _get_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_7 = get_a_mask_sub_3_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_7 = get_a_mask_size & get_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_7 = get_a_mask_sub_3_1 \| _get_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] get_a_mask_lo_lo = {get_a_mask_acc_1, get_a_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] get_a_mask_lo_hi = {get_a_mask_acc_3, get_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] get_a_mask_lo = {get_a_mask_lo_hi, get_a_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] get_a_mask_hi_lo = {get_a_mask_acc_5, get_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] get_a_mask_hi_hi = {get_a_mask_acc_7, get_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] get_a_mask_hi = {get_a_mask_hi_hi, get_a_mask_hi_lo}; // @[Misc.scala:222:10] assign _get_a_mask_T = {get_a_mask_hi, get_a_mask_lo}; // @[Misc.scala:222:10] assign get_mask = _get_a_mask_T; // @[Misc.scala:222:10] wire [34:0] _put_legal_T_5 = {1'h0, _put_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [34:0] _put_legal_T_6 = _put_legal_T_5 & 35'h8A113000; // @[Parameters.scala:137:{41,46}] wire [34:0] _put_legal_T_7 = _put_legal_T_6; // @[Parameters.scala:137:46] wire _put_legal_T_8 = _put_legal_T_7 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _put_legal_T_9 = _put_legal_T_8; // @[Parameters.scala:684:54] wire _put_legal_T_51 = _put_legal_T_9; // @[Parameters.scala:684:54, :686:26] wire [34:0] _put_legal_T_15 = {1'h0, _put_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [34:0] _put_legal_T_16 = _put_legal_T_15 & 35'h8A112000; // @[Parameters.scala:137:{41,46}] wire [34:0] _put_legal_T_17 = _put_legal_T_16; // @[Parameters.scala:137:46] wire _put_legal_T_18 = _put_legal_T_17 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _put_legal_T_20 = {1'h0, _put_legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [34:0] _put_legal_T_21 = _put_legal_T_20 & 35'h8A103000; // @[Parameters.scala:137:{41,46}] wire [34:0] _put_legal_T_22 = _put_legal_T_21; // @[Parameters.scala:137:46] wire _put_legal_T_23 = _put_legal_T_22 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _put_legal_T_25 = {1'h0, _put_legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [34:0] _put_legal_T_26 = _put_legal_T_25 & 35'h8A110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _put_legal_T_27 = _put_legal_T_26; // @[Parameters.scala:137:46] wire _put_legal_T_28 = _put_legal_T_27 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _put_legal_T_30 = {1'h0, _put_legal_T_29}; // @[Parameters.scala:137:{31,41}] wire [34:0] _put_legal_T_31 = _put_legal_T_30 & 35'h88000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _put_legal_T_32 = _put_legal_T_31; // @[Parameters.scala:137:46] wire _put_legal_T_33 = _put_legal_T_32 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _put_legal_T_35 = {1'h0, _put_legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [34:0] _put_legal_T_36 = _put_legal_T_35 & 35'h8A110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _put_legal_T_37 = _put_legal_T_36; // @[Parameters.scala:137:46] wire _put_legal_T_38 = _put_legal_T_37 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _put_legal_T_39 = _put_legal_T_18 \| _put_legal_T_23; // @[Parameters.scala:685:42] wire _put_legal_T_40 = _put_legal_T_39 \| _put_legal_T_28; // @[Parameters.scala:685:42] wire _put_legal_T_41 = _put_legal_T_40 \| _put_legal_T_33; // @[Parameters.scala:685:42] wire _put_legal_T_42 = _put_legal_T_41 \| _put_legal_T_38; // @[Parameters.scala:685:42] wire _put_legal_T_43 = _put_legal_T_42; // @[Parameters.scala:684:54, :685:42] wire [34:0] _put_legal_T_46 = {1'h0, _put_legal_T_45}; // @[Parameters.scala:137:{31,41}] wire [34:0] _put_legal_T_47 = _put_legal_T_46 & 35'h8A110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _put_legal_T_48 = _put_legal_T_47; // @[Parameters.scala:137:46] wire _put_legal_T_49 = _put_legal_T_48 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _put_legal_T_52 = _put_legal_T_51 \| _put_legal_T_43; // @[Parameters.scala:684:54, :686:26] wire put_legal = _put_legal_T_52; // @[Parameters.scala:686:26] wire [7:0] _put_a_mask_T; // @[Misc.scala:222:10] wire [7:0] put_mask; // @[Edges.scala:480:17] wire [1:0] put_a_mask_sizeOH_shiftAmount = _put_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _put_a_mask_sizeOH_T_1 = 4'h1 << put_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _put_a_mask_sizeOH_T_2 = _put_a_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] put_a_mask_sizeOH = {_put_a_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire put_a_mask_sub_sub_sub_0_1 = &s2_req_size; // @[Misc.scala:206:21] wire put_a_mask_sub_sub_size = put_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire put_a_mask_sub_sub_1_2 = put_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire put_a_mask_sub_sub_nbit = ~put_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire put_a_mask_sub_sub_0_2 = put_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_sub_sub_acc_T = put_a_mask_sub_sub_size & put_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_sub_0_1 = put_a_mask_sub_sub_sub_0_1 \| _put_a_mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _put_a_mask_sub_sub_acc_T_1 = put_a_mask_sub_sub_size & put_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_sub_1_1 = put_a_mask_sub_sub_sub_0_1 \| _put_a_mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire put_a_mask_sub_size = put_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire put_a_mask_sub_nbit = ~put_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire put_a_mask_sub_0_2 = put_a_mask_sub_sub_0_2 & put_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_sub_acc_T = put_a_mask_sub_size & put_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_0_1 = put_a_mask_sub_sub_0_1 \| _put_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_1_2 = put_a_mask_sub_sub_0_2 & put_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_sub_acc_T_1 = put_a_mask_sub_size & put_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_1_1 = put_a_mask_sub_sub_0_1 \| _put_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_2_2 = put_a_mask_sub_sub_1_2 & put_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_sub_acc_T_2 = put_a_mask_sub_size & put_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_2_1 = put_a_mask_sub_sub_1_1 \| _put_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_3_2 = put_a_mask_sub_sub_1_2 & put_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_sub_acc_T_3 = put_a_mask_sub_size & put_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_3_1 = put_a_mask_sub_sub_1_1 \| _put_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire put_a_mask_size = put_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire put_a_mask_nbit = ~put_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire put_a_mask_eq = put_a_mask_sub_0_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T = put_a_mask_size & put_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc = put_a_mask_sub_0_1 \| _put_a_mask_acc_T; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_1 = put_a_mask_sub_0_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_1 = put_a_mask_size & put_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_1 = put_a_mask_sub_0_1 \| _put_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_2 = put_a_mask_sub_1_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T_2 = put_a_mask_size & put_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_2 = put_a_mask_sub_1_1 \| _put_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_3 = put_a_mask_sub_1_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_3 = put_a_mask_size & put_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_3 = put_a_mask_sub_1_1 \| _put_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_4 = put_a_mask_sub_2_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T_4 = put_a_mask_size & put_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_4 = put_a_mask_sub_2_1 \| _put_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_5 = put_a_mask_sub_2_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_5 = put_a_mask_size & put_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_5 = put_a_mask_sub_2_1 \| _put_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_6 = put_a_mask_sub_3_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T_6 = put_a_mask_size & put_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_6 = put_a_mask_sub_3_1 \| _put_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_7 = put_a_mask_sub_3_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_7 = put_a_mask_size & put_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_7 = put_a_mask_sub_3_1 \| _put_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] put_a_mask_lo_lo = {put_a_mask_acc_1, put_a_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] put_a_mask_lo_hi = {put_a_mask_acc_3, put_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] put_a_mask_lo = {put_a_mask_lo_hi, put_a_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] put_a_mask_hi_lo = {put_a_mask_acc_5, put_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] put_a_mask_hi_hi = {put_a_mask_acc_7, put_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] put_a_mask_hi = {put_a_mask_hi_hi, put_a_mask_hi_lo}; // @[Misc.scala:222:10] assign _put_a_mask_T = {put_a_mask_hi, put_a_mask_lo}; // @[Misc.scala:222:10] assign put_mask = _put_a_mask_T; // @[Misc.scala:222:10] wire [34:0] _putpartial_legal_T_5 = {1'h0, _putpartial_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [34:0] _putpartial_legal_T_6 = _putpartial_legal_T_5 & 35'h8A113000; // @[Parameters.scala:137:{41,46}] wire [34:0] _putpartial_legal_T_7 = _putpartial_legal_T_6; // @[Parameters.scala:137:46] wire _putpartial_legal_T_8 = _putpartial_legal_T_7 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _putpartial_legal_T_9 = _putpartial_legal_T_8; // @[Parameters.scala:684:54] wire _putpartial_legal_T_51 = _putpartial_legal_T_9; // @[Parameters.scala:684:54, :686:26] wire [34:0] _putpartial_legal_T_15 = {1'h0, _putpartial_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [34:0] _putpartial_legal_T_16 = _putpartial_legal_T_15 & 35'h8A112000; // @[Parameters.scala:137:{41,46}] wire [34:0] _putpartial_legal_T_17 = _putpartial_legal_T_16; // @[Parameters.scala:137:46] wire _putpartial_legal_T_18 = _putpartial_legal_T_17 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _putpartial_legal_T_20 = {1'h0, _putpartial_legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [34:0] _putpartial_legal_T_21 = _putpartial_legal_T_20 & 35'h8A103000; // @[Parameters.scala:137:{41,46}] wire [34:0] _putpartial_legal_T_22 = _putpartial_legal_T_21; // @[Parameters.scala:137:46] wire _putpartial_legal_T_23 = _putpartial_legal_T_22 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _putpartial_legal_T_25 = {1'h0, _putpartial_legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [34:0] _putpartial_legal_T_26 = _putpartial_legal_T_25 & 35'h8A110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _putpartial_legal_T_27 = _putpartial_legal_T_26; // @[Parameters.scala:137:46] wire _putpartial_legal_T_28 = _putpartial_legal_T_27 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _putpartial_legal_T_30 = {1'h0, _putpartial_legal_T_29}; // @[Parameters.scala:137:{31,41}] wire [34:0] _putpartial_legal_T_31 = _putpartial_legal_T_30 & 35'h88000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _putpartial_legal_T_32 = _putpartial_legal_T_31; // @[Parameters.scala:137:46] wire _putpartial_legal_T_33 = _putpartial_legal_T_32 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _putpartial_legal_T_35 = {1'h0, _putpartial_legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [34:0] _putpartial_legal_T_36 = _putpartial_legal_T_35 & 35'h8A110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _putpartial_legal_T_37 = _putpartial_legal_T_36; // @[Parameters.scala:137:46] wire _putpartial_legal_T_38 = _putpartial_legal_T_37 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _putpartial_legal_T_39 = _putpartial_legal_T_18 \| _putpartial_legal_T_23; // @[Parameters.scala:685:42] wire _putpartial_legal_T_40 = _putpartial_legal_T_39 \| _putpartial_legal_T_28; // @[Parameters.scala:685:42] wire _putpartial_legal_T_41 = _putpartial_legal_T_40 \| _putpartial_legal_T_33; // @[Parameters.scala:685:42] wire _putpartial_legal_T_42 = _putpartial_legal_T_41 \| _putpartial_legal_T_38; // @[Parameters.scala:685:42] wire _putpartial_legal_T_43 = _putpartial_legal_T_42; // @[Parameters.scala:684:54, :685:42] wire [34:0] _putpartial_legal_T_46 = {1'h0, _putpartial_legal_T_45}; // @[Parameters.scala:137:{31,41}] wire [34:0] _putpartial_legal_T_47 = _putpartial_legal_T_46 & 35'h8A110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _putpartial_legal_T_48 = _putpartial_legal_T_47; // @[Parameters.scala:137:46] wire _putpartial_legal_T_49 = _putpartial_legal_T_48 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _putpartial_legal_T_52 = _putpartial_legal_T_51 \| _putpartial_legal_T_43; // @[Parameters.scala:684:54, :686:26] wire putpartial_legal = _putpartial_legal_T_52; // @[Parameters.scala:686:26] wire [7:0] putpartial_mask; // @[Edges.scala:500:17] assign putpartial_mask = a_mask[7:0]; // @[Edges.scala:500:17, :508:15] wire [34:0] _atomics_legal_T_5 = {1'h0, _atomics_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [34:0] _atomics_legal_T_6 = _atomics_legal_T_5 & 35'h8110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _atomics_legal_T_7 = _atomics_legal_T_6; // @[Parameters.scala:137:46] wire _atomics_legal_T_8 = _atomics_legal_T_7 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _atomics_legal_T_10 = {1'h0, _atomics_legal_T_9}; // @[Parameters.scala:137:{31,41}] wire [34:0] _atomics_legal_T_11 = _atomics_legal_T_10 & 35'h8101000; // @[Parameters.scala:137:{41,46}] wire [34:0] _atomics_legal_T_12 = _atomics_legal_T_11; // @[Parameters.scala:137:46] wire _atomics_legal_T_13 = _atomics_legal_T_12 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _atomics_legal_T_15 = {1'h0, _atomics_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [34:0] _atomics_legal_T_16 = _atomics_legal_T_15 & 35'h8000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _atomics_legal_T_17 = _atomics_legal_T_16; // @[Parameters.scala:137:46] wire _atomics_legal_T_18 = _atomics_legal_T_17 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_19 = _atomics_legal_T_8 \| _atomics_legal_T_13; // @[Parameters.scala:685:42] wire _atomics_legal_T_20 = _atomics_legal_T_19 \| _atomics_legal_T_18; // @[Parameters.scala:685:42] wire _atomics_legal_T_21 = _atomics_legal_T_20; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_29 = _atomics_legal_T_21; // @[Parameters.scala:684:54, :686:26] wire [34:0] _atomics_legal_T_24 = {1'h0, _atomics_legal_T_23}; // @[Parameters.scala:137:{31,41}] wire [34:0] _atomics_legal_T_25 = _atomics_legal_T_24 & 35'h8110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _atomics_legal_T_26 = _atomics_legal_T_25; // @[Parameters.scala:137:46] wire _atomics_legal_T_27 = _atomics_legal_T_26 == 35'h0; // @[Parameters.scala:137:{46,59}] wire atomics_legal = _atomics_legal_T_29; // @[Parameters.scala:686:26] wire [7:0] _atomics_a_mask_T; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask; // @[Edges.scala:534:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount = _atomics_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_1 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_2 = _atomics_a_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH = {_atomics_a_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1 = &s2_req_size; // @[Misc.scala:206:21] wire atomics_a_mask_sub_sub_size = atomics_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2 = atomics_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit = ~atomics_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2 = atomics_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T = atomics_a_mask_sub_sub_size & atomics_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1 = atomics_a_mask_sub_sub_sub_0_1 \| _atomics_a_mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_1 = atomics_a_mask_sub_sub_size & atomics_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1 = atomics_a_mask_sub_sub_sub_0_1 \| _atomics_a_mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size = atomics_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit = ~atomics_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2 = atomics_a_mask_sub_sub_0_2 & atomics_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T = atomics_a_mask_sub_size & atomics_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1 = atomics_a_mask_sub_sub_0_1 \| _atomics_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2 = atomics_a_mask_sub_sub_0_2 & atomics_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_1 = atomics_a_mask_sub_size & atomics_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1 = atomics_a_mask_sub_sub_0_1 \| _atomics_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2 = atomics_a_mask_sub_sub_1_2 & atomics_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_2 = atomics_a_mask_sub_size & atomics_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1 = atomics_a_mask_sub_sub_1_1 \| _atomics_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2 = atomics_a_mask_sub_sub_1_2 & atomics_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_3 = atomics_a_mask_sub_size & atomics_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1 = atomics_a_mask_sub_sub_1_1 \| _atomics_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size = atomics_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit = ~atomics_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq = atomics_a_mask_sub_0_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T = atomics_a_mask_size & atomics_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc = atomics_a_mask_sub_0_1 \| _atomics_a_mask_acc_T; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_1 = atomics_a_mask_sub_0_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_1 = atomics_a_mask_size & atomics_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_1 = atomics_a_mask_sub_0_1 \| _atomics_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_2 = atomics_a_mask_sub_1_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_2 = atomics_a_mask_size & atomics_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_2 = atomics_a_mask_sub_1_1 \| _atomics_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_3 = atomics_a_mask_sub_1_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_3 = atomics_a_mask_size & atomics_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_3 = atomics_a_mask_sub_1_1 \| _atomics_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_4 = atomics_a_mask_sub_2_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_4 = atomics_a_mask_size & atomics_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_4 = atomics_a_mask_sub_2_1 \| _atomics_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_5 = atomics_a_mask_sub_2_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_5 = atomics_a_mask_size & atomics_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_5 = atomics_a_mask_sub_2_1 \| _atomics_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_6 = atomics_a_mask_sub_3_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_6 = atomics_a_mask_size & atomics_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_6 = atomics_a_mask_sub_3_1 \| _atomics_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_7 = atomics_a_mask_sub_3_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_7 = atomics_a_mask_size & atomics_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_7 = atomics_a_mask_sub_3_1 \| _atomics_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo = {atomics_a_mask_acc_1, atomics_a_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi = {atomics_a_mask_acc_3, atomics_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo = {atomics_a_mask_lo_hi, atomics_a_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo = {atomics_a_mask_acc_5, atomics_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi = {atomics_a_mask_acc_7, atomics_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi = {atomics_a_mask_hi_hi, atomics_a_mask_hi_lo}; // @[Misc.scala:222:10] assign _atomics_a_mask_T = {atomics_a_mask_hi, atomics_a_mask_lo}; // @[Misc.scala:222:10] assign atomics_a_mask = _atomics_a_mask_T; // @[Misc.scala:222:10] wire [34:0] _atomics_legal_T_35 = {1'h0, _atomics_legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [34:0] _atomics_legal_T_36 = _atomics_legal_T_35 & 35'h8110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _atomics_legal_T_37 = _atomics_legal_T_36; // @[Parameters.scala:137:46] wire _atomics_legal_T_38 = _atomics_legal_T_37 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _atomics_legal_T_40 = {1'h0, _atomics_legal_T_39}; // @[Parameters.scala:137:{31,41}] wire [34:0] _atomics_legal_T_41 = _atomics_legal_T_40 & 35'h8101000; // @[Parameters.scala:137:{41,46}] wire [34:0] _atomics_legal_T_42 = _atomics_legal_T_41; // @[Parameters.scala:137:46] wire _atomics_legal_T_43 = _atomics_legal_T_42 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _atomics_legal_T_45 = {1'h0, _atomics_legal_T_44}; // @[Parameters.scala:137:{31,41}] wire [34:0] _atomics_legal_T_46 = _atomics_legal_T_45 & 35'h8000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _atomics_legal_T_47 = _atomics_legal_T_46; // @[Parameters.scala:137:46] wire _atomics_legal_T_48 = _atomics_legal_T_47 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_49 = _atomics_legal_T_38 \| _atomics_legal_T_43; // @[Parameters.scala:685:42] wire _atomics_legal_T_50 = _atomics_legal_T_49 \| _atomics_legal_T_48; // @[Parameters.scala:685:42] wire _atomics_legal_T_51 = _atomics_legal_T_50; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_59 = _atomics_legal_T_51; // @[Parameters.scala:684:54, :686:26] wire [34:0] _atomics_legal_T_54 = {1'h0, _atomics_legal_T_53}; // @[Parameters.scala:137:{31,41}] wire [34:0] _atomics_legal_T_55 = _atomics_legal_T_54 & 35'h8110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _atomics_legal_T_56 = _atomics_legal_T_55; // @[Parameters.scala:137:46] wire _atomics_legal_T_57 = _atomics_legal_T_56 == 35'h0; // @[Parameters.scala:137:{46,59}] wire atomics_legal_1 = _atomics_legal_T_59; // @[Parameters.scala:686:26] wire [7:0] _atomics_a_mask_T_1; // @[Misc.scala:222:10] wire [7:0] atomics_a_1_mask; // @[Edges.scala:534:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_1 = _atomics_a_mask_sizeOH_T_3[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_4 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_1; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_5 = _atomics_a_mask_sizeOH_T_4[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH_1 = {_atomics_a_mask_sizeOH_T_5[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1_1 = &s2_req_size; // @[Misc.scala:206:21] wire atomics_a_mask_sub_sub_size_1 = atomics_a_mask_sizeOH_1[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2_1 = atomics_a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit_1 = ~atomics_a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_1 = atomics_a_mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_2 = atomics_a_mask_sub_sub_size_1 & atomics_a_mask_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_1 = atomics_a_mask_sub_sub_sub_0_1_1 \| _atomics_a_mask_sub_sub_acc_T_2; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_3 = atomics_a_mask_sub_sub_size_1 & atomics_a_mask_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_1 = atomics_a_mask_sub_sub_sub_0_1_1 \| _atomics_a_mask_sub_sub_acc_T_3; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size_1 = atomics_a_mask_sizeOH_1[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_1 = ~atomics_a_mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_1 = atomics_a_mask_sub_sub_0_2_1 & atomics_a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_4 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_1 = atomics_a_mask_sub_sub_0_1_1 \| _atomics_a_mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_1 = atomics_a_mask_sub_sub_0_2_1 & atomics_a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_5 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_1 = atomics_a_mask_sub_sub_0_1_1 \| _atomics_a_mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_1 = atomics_a_mask_sub_sub_1_2_1 & atomics_a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_6 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_1 = atomics_a_mask_sub_sub_1_1_1 \| _atomics_a_mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_1 = atomics_a_mask_sub_sub_1_2_1 & atomics_a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_7 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_1 = atomics_a_mask_sub_sub_1_1_1 \| _atomics_a_mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_1 = atomics_a_mask_sizeOH_1[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_1 = ~atomics_a_mask_bit_1; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_8 = atomics_a_mask_sub_0_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_8 = atomics_a_mask_size_1 & atomics_a_mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_8 = atomics_a_mask_sub_0_1_1 \| _atomics_a_mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_9 = atomics_a_mask_sub_0_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_9 = atomics_a_mask_size_1 & atomics_a_mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_9 = atomics_a_mask_sub_0_1_1 \| _atomics_a_mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_10 = atomics_a_mask_sub_1_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_10 = atomics_a_mask_size_1 & atomics_a_mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_10 = atomics_a_mask_sub_1_1_1 \| _atomics_a_mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_11 = atomics_a_mask_sub_1_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_11 = atomics_a_mask_size_1 & atomics_a_mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_11 = atomics_a_mask_sub_1_1_1 \| _atomics_a_mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_12 = atomics_a_mask_sub_2_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_12 = atomics_a_mask_size_1 & atomics_a_mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_12 = atomics_a_mask_sub_2_1_1 \| _atomics_a_mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_13 = atomics_a_mask_sub_2_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_13 = atomics_a_mask_size_1 & atomics_a_mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_13 = atomics_a_mask_sub_2_1_1 \| _atomics_a_mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_14 = atomics_a_mask_sub_3_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_14 = atomics_a_mask_size_1 & atomics_a_mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_14 = atomics_a_mask_sub_3_1_1 \| _atomics_a_mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_15 = atomics_a_mask_sub_3_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_15 = atomics_a_mask_size_1 & atomics_a_mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_15 = atomics_a_mask_sub_3_1_1 \| _atomics_a_mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_1 = {atomics_a_mask_acc_9, atomics_a_mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_1 = {atomics_a_mask_acc_11, atomics_a_mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_1 = {atomics_a_mask_lo_hi_1, atomics_a_mask_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_1 = {atomics_a_mask_acc_13, atomics_a_mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_1 = {atomics_a_mask_acc_15, atomics_a_mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_1 = {atomics_a_mask_hi_hi_1, atomics_a_mask_hi_lo_1}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_1 = {atomics_a_mask_hi_1, atomics_a_mask_lo_1}; // @[Misc.scala:222:10] assign atomics_a_1_mask = _atomics_a_mask_T_1; // @[Misc.scala:222:10] wire [34:0] _atomics_legal_T_65 = {1'h0, _atomics_legal_T_64}; // @[Parameters.scala:137:{31,41}] wire [34:0] _atomics_legal_T_66 = _atomics_legal_T_65 & 35'h8110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _atomics_legal_T_67 = _atomics_legal_T_66; // @[Parameters.scala:137:46] wire _atomics_legal_T_68 = _atomics_legal_T_67 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _atomics_legal_T_70 = {1'h0, _atomics_legal_T_69}; // @[Parameters.scala:137:{31,41}] wire [34:0] _atomics_legal_T_71 = _atomics_legal_T_70 & 35'h8101000; // @[Parameters.scala:137:{41,46}] wire [34:0] _atomics_legal_T_72 = _atomics_legal_T_71; // @[Parameters.scala:137:46] wire _atomics_legal_T_73 = _atomics_legal_T_72 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _atomics_legal_T_75 = {1'h0, _atomics_legal_T_74}; // @[Parameters.scala:137:{31,41}] wire [34:0] _atomics_legal_T_76 = _atomics_legal_T_75 & 35'h8000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _atomics_legal_T_77 = _atomics_legal_T_76; // @[Parameters.scala:137:46] wire _atomics_legal_T_78 = _atomics_legal_T_77 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_79 = _atomics_legal_T_68 \| _atomics_legal_T_73; // @[Parameters.scala:685:42] wire _atomics_legal_T_80 = _atomics_legal_T_79 \| _atomics_legal_T_78; // @[Parameters.scala:685:42] wire _atomics_legal_T_81 = _atomics_legal_T_80; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_89 = _atomics_legal_T_81; // @[Parameters.scala:684:54, :686:26] wire [34:0] _atomics_legal_T_84 = {1'h0, _atomics_legal_T_83}; // @[Parameters.scala:137:{31,41}] wire [34:0] _atomics_legal_T_85 = _atomics_legal_T_84 & 35'h8110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _atomics_legal_T_86 = _atomics_legal_T_85; // @[Parameters.scala:137:46] wire _atomics_legal_T_87 = _atomics_legal_T_86 == 35'h0; // @[Parameters.scala:137:{46,59}] wire atomics_legal_2 = _atomics_legal_T_89; // @[Parameters.scala:686:26] wire [7:0] _atomics_a_mask_T_2; // @[Misc.scala:222:10] wire [7:0] atomics_a_2_mask; // @[Edges.scala:534:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_2 = _atomics_a_mask_sizeOH_T_6[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_7 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_2; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_8 = _atomics_a_mask_sizeOH_T_7[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH_2 = {_atomics_a_mask_sizeOH_T_8[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1_2 = &s2_req_size; // @[Misc.scala:206:21] wire atomics_a_mask_sub_sub_size_2 = atomics_a_mask_sizeOH_2[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2_2 = atomics_a_mask_sub_sub_bit_2; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit_2 = ~atomics_a_mask_sub_sub_bit_2; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_2 = atomics_a_mask_sub_sub_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_4 = atomics_a_mask_sub_sub_size_2 & atomics_a_mask_sub_sub_0_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_2 = atomics_a_mask_sub_sub_sub_0_1_2 \| _atomics_a_mask_sub_sub_acc_T_4; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_5 = atomics_a_mask_sub_sub_size_2 & atomics_a_mask_sub_sub_1_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_2 = atomics_a_mask_sub_sub_sub_0_1_2 \| _atomics_a_mask_sub_sub_acc_T_5; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size_2 = atomics_a_mask_sizeOH_2[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_2 = ~atomics_a_mask_sub_bit_2; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_2 = atomics_a_mask_sub_sub_0_2_2 & atomics_a_mask_sub_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_8 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_0_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_2 = atomics_a_mask_sub_sub_0_1_2 \| _atomics_a_mask_sub_acc_T_8; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_2 = atomics_a_mask_sub_sub_0_2_2 & atomics_a_mask_sub_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_9 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_1_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_2 = atomics_a_mask_sub_sub_0_1_2 \| _atomics_a_mask_sub_acc_T_9; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_2 = atomics_a_mask_sub_sub_1_2_2 & atomics_a_mask_sub_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_10 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_2_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_2 = atomics_a_mask_sub_sub_1_1_2 \| _atomics_a_mask_sub_acc_T_10; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_2 = atomics_a_mask_sub_sub_1_2_2 & atomics_a_mask_sub_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_11 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_3_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_2 = atomics_a_mask_sub_sub_1_1_2 \| _atomics_a_mask_sub_acc_T_11; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_2 = atomics_a_mask_sizeOH_2[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_2 = ~atomics_a_mask_bit_2; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_16 = atomics_a_mask_sub_0_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_16 = atomics_a_mask_size_2 & atomics_a_mask_eq_16; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_16 = atomics_a_mask_sub_0_1_2 \| _atomics_a_mask_acc_T_16; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_17 = atomics_a_mask_sub_0_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_17 = atomics_a_mask_size_2 & atomics_a_mask_eq_17; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_17 = atomics_a_mask_sub_0_1_2 \| _atomics_a_mask_acc_T_17; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_18 = atomics_a_mask_sub_1_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_18 = atomics_a_mask_size_2 & atomics_a_mask_eq_18; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_18 = atomics_a_mask_sub_1_1_2 \| _atomics_a_mask_acc_T_18; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_19 = atomics_a_mask_sub_1_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_19 = atomics_a_mask_size_2 & atomics_a_mask_eq_19; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_19 = atomics_a_mask_sub_1_1_2 \| _atomics_a_mask_acc_T_19; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_20 = atomics_a_mask_sub_2_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_20 = atomics_a_mask_size_2 & atomics_a_mask_eq_20; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_20 = atomics_a_mask_sub_2_1_2 \| _atomics_a_mask_acc_T_20; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_21 = atomics_a_mask_sub_2_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_21 = atomics_a_mask_size_2 & atomics_a_mask_eq_21; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_21 = atomics_a_mask_sub_2_1_2 \| _atomics_a_mask_acc_T_21; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_22 = atomics_a_mask_sub_3_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_22 = atomics_a_mask_size_2 & atomics_a_mask_eq_22; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_22 = atomics_a_mask_sub_3_1_2 \| _atomics_a_mask_acc_T_22; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_23 = atomics_a_mask_sub_3_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_23 = atomics_a_mask_size_2 & atomics_a_mask_eq_23; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_23 = atomics_a_mask_sub_3_1_2 \| _atomics_a_mask_acc_T_23; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_2 = {atomics_a_mask_acc_17, atomics_a_mask_acc_16}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_2 = {atomics_a_mask_acc_19, atomics_a_mask_acc_18}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_2 = {atomics_a_mask_lo_hi_2, atomics_a_mask_lo_lo_2}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_2 = {atomics_a_mask_acc_21, atomics_a_mask_acc_20}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_2 = {atomics_a_mask_acc_23, atomics_a_mask_acc_22}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_2 = {atomics_a_mask_hi_hi_2, atomics_a_mask_hi_lo_2}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_2 = {atomics_a_mask_hi_2, atomics_a_mask_lo_2}; // @[Misc.scala:222:10] assign atomics_a_2_mask = _atomics_a_mask_T_2; // @[Misc.scala:222:10] wire [34:0] _atomics_legal_T_95 = {1'h0, _atomics_legal_T_94}; // @[Parameters.scala:137:{31,41}] wire [34:0] _atomics_legal_T_96 = _atomics_legal_T_95 & 35'h8110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _atomics_legal_T_97 = _atomics_legal_T_96; // @[Parameters.scala:137:46] wire _atomics_legal_T_98 = _atomics_legal_T_97 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _atomics_legal_T_100 = {1'h0, _atomics_legal_T_99}; // @[Parameters.scala:137:{31,41}] wire [34:0] _atomics_legal_T_101 = _atomics_legal_T_100 & 35'h8101000; // @[Parameters.scala:137:{41,46}] wire [34:0] _atomics_legal_T_102 = _atomics_legal_T_101; // @[Parameters.scala:137:46] wire _atomics_legal_T_103 = _atomics_legal_T_102 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _atomics_legal_T_105 = {1'h0, _atomics_legal_T_104}; // @[Parameters.scala:137:{31,41}] wire [34:0] _atomics_legal_T_106 = _atomics_legal_T_105 & 35'h8000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _atomics_legal_T_107 = _atomics_legal_T_106; // @[Parameters.scala:137:46] wire _atomics_legal_T_108 = _atomics_legal_T_107 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_109 = _atomics_legal_T_98 \| _atomics_legal_T_103; // @[Parameters.scala:685:42] wire _atomics_legal_T_110 = _atomics_legal_T_109 \| _atomics_legal_T_108; // @[Parameters.scala:685:42] wire _atomics_legal_T_111 = _atomics_legal_T_110; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_119 = _atomics_legal_T_111; // @[Parameters.scala:684:54, :686:26] wire [34:0] _atomics_legal_T_114 = {1'h0, _atomics_legal_T_113}; // @[Parameters.scala:137:{31,41}] wire [34:0] _atomics_legal_T_115 = _atomics_legal_T_114 & 35'h8110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _atomics_legal_T_116 = _atomics_legal_T_115; // @[Parameters.scala:137:46] wire _atomics_legal_T_117 = _atomics_legal_T_116 == 35'h0; // @[Parameters.scala:137:{46,59}] wire atomics_legal_3 = _atomics_legal_T_119; // @[Parameters.scala:686:26] wire [7:0] _atomics_a_mask_T_3; // @[Misc.scala:222:10] wire [7:0] atomics_a_3_mask; // @[Edges.scala:534:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_3 = _atomics_a_mask_sizeOH_T_9[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_10 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_3; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_11 = _atomics_a_mask_sizeOH_T_10[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH_3 = {_atomics_a_mask_sizeOH_T_11[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1_3 = &s2_req_size; // @[Misc.scala:206:21] wire atomics_a_mask_sub_sub_size_3 = atomics_a_mask_sizeOH_3[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2_3 = atomics_a_mask_sub_sub_bit_3; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit_3 = ~atomics_a_mask_sub_sub_bit_3; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_3 = atomics_a_mask_sub_sub_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_6 = atomics_a_mask_sub_sub_size_3 & atomics_a_mask_sub_sub_0_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_3 = atomics_a_mask_sub_sub_sub_0_1_3 \| _atomics_a_mask_sub_sub_acc_T_6; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_7 = atomics_a_mask_sub_sub_size_3 & atomics_a_mask_sub_sub_1_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_3 = atomics_a_mask_sub_sub_sub_0_1_3 \| _atomics_a_mask_sub_sub_acc_T_7; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size_3 = atomics_a_mask_sizeOH_3[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_3 = ~atomics_a_mask_sub_bit_3; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_3 = atomics_a_mask_sub_sub_0_2_3 & atomics_a_mask_sub_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_12 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_0_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_3 = atomics_a_mask_sub_sub_0_1_3 \| _atomics_a_mask_sub_acc_T_12; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_3 = atomics_a_mask_sub_sub_0_2_3 & atomics_a_mask_sub_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_13 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_1_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_3 = atomics_a_mask_sub_sub_0_1_3 \| _atomics_a_mask_sub_acc_T_13; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_3 = atomics_a_mask_sub_sub_1_2_3 & atomics_a_mask_sub_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_14 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_2_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_3 = atomics_a_mask_sub_sub_1_1_3 \| _atomics_a_mask_sub_acc_T_14; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_3 = atomics_a_mask_sub_sub_1_2_3 & atomics_a_mask_sub_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_15 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_3_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_3 = atomics_a_mask_sub_sub_1_1_3 \| _atomics_a_mask_sub_acc_T_15; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_3 = atomics_a_mask_sizeOH_3[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_3 = ~atomics_a_mask_bit_3; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_24 = atomics_a_mask_sub_0_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_24 = atomics_a_mask_size_3 & atomics_a_mask_eq_24; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_24 = atomics_a_mask_sub_0_1_3 \| _atomics_a_mask_acc_T_24; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_25 = atomics_a_mask_sub_0_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_25 = atomics_a_mask_size_3 & atomics_a_mask_eq_25; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_25 = atomics_a_mask_sub_0_1_3 \| _atomics_a_mask_acc_T_25; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_26 = atomics_a_mask_sub_1_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_26 = atomics_a_mask_size_3 & atomics_a_mask_eq_26; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_26 = atomics_a_mask_sub_1_1_3 \| _atomics_a_mask_acc_T_26; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_27 = atomics_a_mask_sub_1_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_27 = atomics_a_mask_size_3 & atomics_a_mask_eq_27; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_27 = atomics_a_mask_sub_1_1_3 \| _atomics_a_mask_acc_T_27; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_28 = atomics_a_mask_sub_2_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_28 = atomics_a_mask_size_3 & atomics_a_mask_eq_28; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_28 = atomics_a_mask_sub_2_1_3 \| _atomics_a_mask_acc_T_28; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_29 = atomics_a_mask_sub_2_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_29 = atomics_a_mask_size_3 & atomics_a_mask_eq_29; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_29 = atomics_a_mask_sub_2_1_3 \| _atomics_a_mask_acc_T_29; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_30 = atomics_a_mask_sub_3_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_30 = atomics_a_mask_size_3 & atomics_a_mask_eq_30; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_30 = atomics_a_mask_sub_3_1_3 \| _atomics_a_mask_acc_T_30; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_31 = atomics_a_mask_sub_3_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_31 = atomics_a_mask_size_3 & atomics_a_mask_eq_31; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_31 = atomics_a_mask_sub_3_1_3 \| _atomics_a_mask_acc_T_31; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_3 = {atomics_a_mask_acc_25, atomics_a_mask_acc_24}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_3 = {atomics_a_mask_acc_27, atomics_a_mask_acc_26}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_3 = {atomics_a_mask_lo_hi_3, atomics_a_mask_lo_lo_3}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_3 = {atomics_a_mask_acc_29, atomics_a_mask_acc_28}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_3 = {atomics_a_mask_acc_31, atomics_a_mask_acc_30}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_3 = {atomics_a_mask_hi_hi_3, atomics_a_mask_hi_lo_3}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_3 = {atomics_a_mask_hi_3, atomics_a_mask_lo_3}; // @[Misc.scala:222:10] assign atomics_a_3_mask = _atomics_a_mask_T_3; // @[Misc.scala:222:10] wire [34:0] _atomics_legal_T_125 = {1'h0, _atomics_legal_T_124}; // @[Parameters.scala:137:{31,41}] wire [34:0] _atomics_legal_T_126 = _atomics_legal_T_125 & 35'h8110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _atomics_legal_T_127 = _atomics_legal_T_126; // @[Parameters.scala:137:46] wire _atomics_legal_T_128 = _atomics_legal_T_127 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _atomics_legal_T_130 = {1'h0, _atomics_legal_T_129}; // @[Parameters.scala:137:{31,41}] wire [34:0] _atomics_legal_T_131 = _atomics_legal_T_130 & 35'h8101000; // @[Parameters.scala:137:{41,46}] wire [34:0] _atomics_legal_T_132 = _atomics_legal_T_131; // @[Parameters.scala:137:46] wire _atomics_legal_T_133 = _atomics_legal_T_132 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _atomics_legal_T_135 = {1'h0, _atomics_legal_T_134}; // @[Parameters.scala:137:{31,41}] wire [34:0] _atomics_legal_T_136 = _atomics_legal_T_135 & 35'h8000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _atomics_legal_T_137 = _atomics_legal_T_136; // @[Parameters.scala:137:46] wire _atomics_legal_T_138 = _atomics_legal_T_137 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_139 = _atomics_legal_T_128 \| _atomics_legal_T_133; // @[Parameters.scala:685:42] wire _atomics_legal_T_140 = _atomics_legal_T_139 \| _atomics_legal_T_138; // @[Parameters.scala:685:42] wire _atomics_legal_T_141 = _atomics_legal_T_140; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_149 = _atomics_legal_T_141; // @[Parameters.scala:684:54, :686:26] wire [34:0] _atomics_legal_T_144 = {1'h0, _atomics_legal_T_143}; // @[Parameters.scala:137:{31,41}] wire [34:0] _atomics_legal_T_145 = _atomics_legal_T_144 & 35'h8110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _atomics_legal_T_146 = _atomics_legal_T_145; // @[Parameters.scala:137:46] wire _atomics_legal_T_147 = _atomics_legal_T_146 == 35'h0; // @[Parameters.scala:137:{46,59}] wire atomics_legal_4 = _atomics_legal_T_149; // @[Parameters.scala:686:26] wire [7:0] _atomics_a_mask_T_4; // @[Misc.scala:222:10] wire [7:0] atomics_a_4_mask; // @[Edges.scala:517:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_4 = _atomics_a_mask_sizeOH_T_12[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_13 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_4; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_14 = _atomics_a_mask_sizeOH_T_13[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH_4 = {_atomics_a_mask_sizeOH_T_14[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1_4 = &s2_req_size; // @[Misc.scala:206:21] wire atomics_a_mask_sub_sub_size_4 = atomics_a_mask_sizeOH_4[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2_4 = atomics_a_mask_sub_sub_bit_4; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit_4 = ~atomics_a_mask_sub_sub_bit_4; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_4 = atomics_a_mask_sub_sub_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_8 = atomics_a_mask_sub_sub_size_4 & atomics_a_mask_sub_sub_0_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_4 = atomics_a_mask_sub_sub_sub_0_1_4 \| _atomics_a_mask_sub_sub_acc_T_8; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_9 = atomics_a_mask_sub_sub_size_4 & atomics_a_mask_sub_sub_1_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_4 = atomics_a_mask_sub_sub_sub_0_1_4 \| _atomics_a_mask_sub_sub_acc_T_9; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size_4 = atomics_a_mask_sizeOH_4[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_4 = ~atomics_a_mask_sub_bit_4; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_4 = atomics_a_mask_sub_sub_0_2_4 & atomics_a_mask_sub_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_16 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_0_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_4 = atomics_a_mask_sub_sub_0_1_4 \| _atomics_a_mask_sub_acc_T_16; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_4 = atomics_a_mask_sub_sub_0_2_4 & atomics_a_mask_sub_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_17 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_1_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_4 = atomics_a_mask_sub_sub_0_1_4 \| _atomics_a_mask_sub_acc_T_17; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_4 = atomics_a_mask_sub_sub_1_2_4 & atomics_a_mask_sub_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_18 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_2_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_4 = atomics_a_mask_sub_sub_1_1_4 \| _atomics_a_mask_sub_acc_T_18; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_4 = atomics_a_mask_sub_sub_1_2_4 & atomics_a_mask_sub_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_19 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_3_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_4 = atomics_a_mask_sub_sub_1_1_4 \| _atomics_a_mask_sub_acc_T_19; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_4 = atomics_a_mask_sizeOH_4[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_4 = ~atomics_a_mask_bit_4; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_32 = atomics_a_mask_sub_0_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_32 = atomics_a_mask_size_4 & atomics_a_mask_eq_32; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_32 = atomics_a_mask_sub_0_1_4 \| _atomics_a_mask_acc_T_32; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_33 = atomics_a_mask_sub_0_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_33 = atomics_a_mask_size_4 & atomics_a_mask_eq_33; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_33 = atomics_a_mask_sub_0_1_4 \| _atomics_a_mask_acc_T_33; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_34 = atomics_a_mask_sub_1_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_34 = atomics_a_mask_size_4 & atomics_a_mask_eq_34; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_34 = atomics_a_mask_sub_1_1_4 \| _atomics_a_mask_acc_T_34; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_35 = atomics_a_mask_sub_1_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_35 = atomics_a_mask_size_4 & atomics_a_mask_eq_35; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_35 = atomics_a_mask_sub_1_1_4 \| _atomics_a_mask_acc_T_35; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_36 = atomics_a_mask_sub_2_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_36 = atomics_a_mask_size_4 & atomics_a_mask_eq_36; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_36 = atomics_a_mask_sub_2_1_4 \| _atomics_a_mask_acc_T_36; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_37 = atomics_a_mask_sub_2_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_37 = atomics_a_mask_size_4 & atomics_a_mask_eq_37; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_37 = atomics_a_mask_sub_2_1_4 \| _atomics_a_mask_acc_T_37; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_38 = atomics_a_mask_sub_3_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_38 = atomics_a_mask_size_4 & atomics_a_mask_eq_38; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_38 = atomics_a_mask_sub_3_1_4 \| _atomics_a_mask_acc_T_38; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_39 = atomics_a_mask_sub_3_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_39 = atomics_a_mask_size_4 & atomics_a_mask_eq_39; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_39 = atomics_a_mask_sub_3_1_4 \| _atomics_a_mask_acc_T_39; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_4 = {atomics_a_mask_acc_33, atomics_a_mask_acc_32}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_4 = {atomics_a_mask_acc_35, atomics_a_mask_acc_34}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_4 = {atomics_a_mask_lo_hi_4, atomics_a_mask_lo_lo_4}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_4 = {atomics_a_mask_acc_37, atomics_a_mask_acc_36}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_4 = {atomics_a_mask_acc_39, atomics_a_mask_acc_38}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_4 = {atomics_a_mask_hi_hi_4, atomics_a_mask_hi_lo_4}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_4 = {atomics_a_mask_hi_4, atomics_a_mask_lo_4}; // @[Misc.scala:222:10] assign atomics_a_4_mask = _atomics_a_mask_T_4; // @[Misc.scala:222:10] wire [34:0] _atomics_legal_T_155 = {1'h0, _atomics_legal_T_154}; // @[Parameters.scala:137:{31,41}] wire [34:0] _atomics_legal_T_156 = _atomics_legal_T_155 & 35'h8110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _atomics_legal_T_157 = _atomics_legal_T_156; // @[Parameters.scala:137:46] wire _atomics_legal_T_158 = _atomics_legal_T_157 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _atomics_legal_T_160 = {1'h0, _atomics_legal_T_159}; // @[Parameters.scala:137:{31,41}] wire [34:0] _atomics_legal_T_161 = _atomics_legal_T_160 & 35'h8101000; // @[Parameters.scala:137:{41,46}] wire [34:0] _atomics_legal_T_162 = _atomics_legal_T_161; // @[Parameters.scala:137:46] wire _atomics_legal_T_163 = _atomics_legal_T_162 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _atomics_legal_T_165 = {1'h0, _atomics_legal_T_164}; // @[Parameters.scala:137:{31,41}] wire [34:0] _atomics_legal_T_166 = _atomics_legal_T_165 & 35'h8000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _atomics_legal_T_167 = _atomics_legal_T_166; // @[Parameters.scala:137:46] wire _atomics_legal_T_168 = _atomics_legal_T_167 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_169 = _atomics_legal_T_158 \| _atomics_legal_T_163; // @[Parameters.scala:685:42] wire _atomics_legal_T_170 = _atomics_legal_T_169 \| _atomics_legal_T_168; // @[Parameters.scala:685:42] wire _atomics_legal_T_171 = _atomics_legal_T_170; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_179 = _atomics_legal_T_171; // @[Parameters.scala:684:54, :686:26] wire [34:0] _atomics_legal_T_174 = {1'h0, _atomics_legal_T_173}; // @[Parameters.scala:137:{31,41}] wire [34:0] _atomics_legal_T_175 = _atomics_legal_T_174 & 35'h8110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _atomics_legal_T_176 = _atomics_legal_T_175; // @[Parameters.scala:137:46] wire _atomics_legal_T_177 = _atomics_legal_T_176 == 35'h0; // @[Parameters.scala:137:{46,59}] wire atomics_legal_5 = _atomics_legal_T_179; // @[Parameters.scala:686:26] wire [7:0] _atomics_a_mask_T_5; // @[Misc.scala:222:10] wire [7:0] atomics_a_5_mask; // @[Edges.scala:517:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_5 = _atomics_a_mask_sizeOH_T_15[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_16 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_5; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_17 = _atomics_a_mask_sizeOH_T_16[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH_5 = {_atomics_a_mask_sizeOH_T_17[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1_5 = &s2_req_size; // @[Misc.scala:206:21] wire atomics_a_mask_sub_sub_size_5 = atomics_a_mask_sizeOH_5[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2_5 = atomics_a_mask_sub_sub_bit_5; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit_5 = ~atomics_a_mask_sub_sub_bit_5; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_5 = atomics_a_mask_sub_sub_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_10 = atomics_a_mask_sub_sub_size_5 & atomics_a_mask_sub_sub_0_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_5 = atomics_a_mask_sub_sub_sub_0_1_5 \| _atomics_a_mask_sub_sub_acc_T_10; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_11 = atomics_a_mask_sub_sub_size_5 & atomics_a_mask_sub_sub_1_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_5 = atomics_a_mask_sub_sub_sub_0_1_5 \| _atomics_a_mask_sub_sub_acc_T_11; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size_5 = atomics_a_mask_sizeOH_5[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_5 = ~atomics_a_mask_sub_bit_5; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_5 = atomics_a_mask_sub_sub_0_2_5 & atomics_a_mask_sub_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_20 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_0_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_5 = atomics_a_mask_sub_sub_0_1_5 \| _atomics_a_mask_sub_acc_T_20; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_5 = atomics_a_mask_sub_sub_0_2_5 & atomics_a_mask_sub_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_21 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_1_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_5 = atomics_a_mask_sub_sub_0_1_5 \| _atomics_a_mask_sub_acc_T_21; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_5 = atomics_a_mask_sub_sub_1_2_5 & atomics_a_mask_sub_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_22 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_2_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_5 = atomics_a_mask_sub_sub_1_1_5 \| _atomics_a_mask_sub_acc_T_22; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_5 = atomics_a_mask_sub_sub_1_2_5 & atomics_a_mask_sub_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_23 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_3_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_5 = atomics_a_mask_sub_sub_1_1_5 \| _atomics_a_mask_sub_acc_T_23; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_5 = atomics_a_mask_sizeOH_5[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_5 = ~atomics_a_mask_bit_5; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_40 = atomics_a_mask_sub_0_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_40 = atomics_a_mask_size_5 & atomics_a_mask_eq_40; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_40 = atomics_a_mask_sub_0_1_5 \| _atomics_a_mask_acc_T_40; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_41 = atomics_a_mask_sub_0_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_41 = atomics_a_mask_size_5 & atomics_a_mask_eq_41; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_41 = atomics_a_mask_sub_0_1_5 \| _atomics_a_mask_acc_T_41; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_42 = atomics_a_mask_sub_1_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_42 = atomics_a_mask_size_5 & atomics_a_mask_eq_42; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_42 = atomics_a_mask_sub_1_1_5 \| _atomics_a_mask_acc_T_42; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_43 = atomics_a_mask_sub_1_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_43 = atomics_a_mask_size_5 & atomics_a_mask_eq_43; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_43 = atomics_a_mask_sub_1_1_5 \| _atomics_a_mask_acc_T_43; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_44 = atomics_a_mask_sub_2_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_44 = atomics_a_mask_size_5 & atomics_a_mask_eq_44; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_44 = atomics_a_mask_sub_2_1_5 \| _atomics_a_mask_acc_T_44; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_45 = atomics_a_mask_sub_2_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_45 = atomics_a_mask_size_5 & atomics_a_mask_eq_45; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_45 = atomics_a_mask_sub_2_1_5 \| _atomics_a_mask_acc_T_45; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_46 = atomics_a_mask_sub_3_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_46 = atomics_a_mask_size_5 & atomics_a_mask_eq_46; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_46 = atomics_a_mask_sub_3_1_5 \| _atomics_a_mask_acc_T_46; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_47 = atomics_a_mask_sub_3_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_47 = atomics_a_mask_size_5 & atomics_a_mask_eq_47; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_47 = atomics_a_mask_sub_3_1_5 \| _atomics_a_mask_acc_T_47; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_5 = {atomics_a_mask_acc_41, atomics_a_mask_acc_40}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_5 = {atomics_a_mask_acc_43, atomics_a_mask_acc_42}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_5 = {atomics_a_mask_lo_hi_5, atomics_a_mask_lo_lo_5}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_5 = {atomics_a_mask_acc_45, atomics_a_mask_acc_44}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_5 = {atomics_a_mask_acc_47, atomics_a_mask_acc_46}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_5 = {atomics_a_mask_hi_hi_5, atomics_a_mask_hi_lo_5}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_5 = {atomics_a_mask_hi_5, atomics_a_mask_lo_5}; // @[Misc.scala:222:10] assign atomics_a_5_mask = _atomics_a_mask_T_5; // @[Misc.scala:222:10] wire [34:0] _atomics_legal_T_185 = {1'h0, _atomics_legal_T_184}; // @[Parameters.scala:137:{31,41}] wire [34:0] _atomics_legal_T_186 = _atomics_legal_T_185 & 35'h8110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _atomics_legal_T_187 = _atomics_legal_T_186; // @[Parameters.scala:137:46] wire _atomics_legal_T_188 = _atomics_legal_T_187 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _atomics_legal_T_190 = {1'h0, _atomics_legal_T_189}; // @[Parameters.scala:137:{31,41}] wire [34:0] _atomics_legal_T_191 = _atomics_legal_T_190 & 35'h8101000; // @[Parameters.scala:137:{41,46}] wire [34:0] _atomics_legal_T_192 = _atomics_legal_T_191; // @[Parameters.scala:137:46] wire _atomics_legal_T_193 = _atomics_legal_T_192 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _atomics_legal_T_195 = {1'h0, _atomics_legal_T_194}; // @[Parameters.scala:137:{31,41}] wire [34:0] _atomics_legal_T_196 = _atomics_legal_T_195 & 35'h8000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _atomics_legal_T_197 = _atomics_legal_T_196; // @[Parameters.scala:137:46] wire _atomics_legal_T_198 = _atomics_legal_T_197 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_199 = _atomics_legal_T_188 \| _atomics_legal_T_193; // @[Parameters.scala:685:42] wire _atomics_legal_T_200 = _atomics_legal_T_199 \| _atomics_legal_T_198; // @[Parameters.scala:685:42] wire _atomics_legal_T_201 = _atomics_legal_T_200; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_209 = _atomics_legal_T_201; // @[Parameters.scala:684:54, :686:26] wire [34:0] _atomics_legal_T_204 = {1'h0, _atomics_legal_T_203}; // @[Parameters.scala:137:{31,41}] wire [34:0] _atomics_legal_T_205 = _atomics_legal_T_204 & 35'h8110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _atomics_legal_T_206 = _atomics_legal_T_205; // @[Parameters.scala:137:46] wire _atomics_legal_T_207 = _atomics_legal_T_206 == 35'h0; // @[Parameters.scala:137:{46,59}] wire atomics_legal_6 = _atomics_legal_T_209; // @[Parameters.scala:686:26] wire [7:0] _atomics_a_mask_T_6; // @[Misc.scala:222:10] wire [7:0] atomics_a_6_mask; // @[Edges.scala:517:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_6 = _atomics_a_mask_sizeOH_T_18[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_19 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_6; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_20 = _atomics_a_mask_sizeOH_T_19[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH_6 = {_atomics_a_mask_sizeOH_T_20[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1_6 = &s2_req_size; // @[Misc.scala:206:21] wire atomics_a_mask_sub_sub_size_6 = atomics_a_mask_sizeOH_6[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2_6 = atomics_a_mask_sub_sub_bit_6; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit_6 = ~atomics_a_mask_sub_sub_bit_6; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_6 = atomics_a_mask_sub_sub_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_12 = atomics_a_mask_sub_sub_size_6 & atomics_a_mask_sub_sub_0_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_6 = atomics_a_mask_sub_sub_sub_0_1_6 \| _atomics_a_mask_sub_sub_acc_T_12; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_13 = atomics_a_mask_sub_sub_size_6 & atomics_a_mask_sub_sub_1_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_6 = atomics_a_mask_sub_sub_sub_0_1_6 \| _atomics_a_mask_sub_sub_acc_T_13; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size_6 = atomics_a_mask_sizeOH_6[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_6 = ~atomics_a_mask_sub_bit_6; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_6 = atomics_a_mask_sub_sub_0_2_6 & atomics_a_mask_sub_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_24 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_0_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_6 = atomics_a_mask_sub_sub_0_1_6 \| _atomics_a_mask_sub_acc_T_24; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_6 = atomics_a_mask_sub_sub_0_2_6 & atomics_a_mask_sub_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_25 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_1_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_6 = atomics_a_mask_sub_sub_0_1_6 \| _atomics_a_mask_sub_acc_T_25; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_6 = atomics_a_mask_sub_sub_1_2_6 & atomics_a_mask_sub_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_26 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_2_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_6 = atomics_a_mask_sub_sub_1_1_6 \| _atomics_a_mask_sub_acc_T_26; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_6 = atomics_a_mask_sub_sub_1_2_6 & atomics_a_mask_sub_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_27 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_3_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_6 = atomics_a_mask_sub_sub_1_1_6 \| _atomics_a_mask_sub_acc_T_27; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_6 = atomics_a_mask_sizeOH_6[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_6 = ~atomics_a_mask_bit_6; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_48 = atomics_a_mask_sub_0_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_48 = atomics_a_mask_size_6 & atomics_a_mask_eq_48; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_48 = atomics_a_mask_sub_0_1_6 \| _atomics_a_mask_acc_T_48; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_49 = atomics_a_mask_sub_0_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_49 = atomics_a_mask_size_6 & atomics_a_mask_eq_49; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_49 = atomics_a_mask_sub_0_1_6 \| _atomics_a_mask_acc_T_49; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_50 = atomics_a_mask_sub_1_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_50 = atomics_a_mask_size_6 & atomics_a_mask_eq_50; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_50 = atomics_a_mask_sub_1_1_6 \| _atomics_a_mask_acc_T_50; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_51 = atomics_a_mask_sub_1_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_51 = atomics_a_mask_size_6 & atomics_a_mask_eq_51; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_51 = atomics_a_mask_sub_1_1_6 \| _atomics_a_mask_acc_T_51; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_52 = atomics_a_mask_sub_2_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_52 = atomics_a_mask_size_6 & atomics_a_mask_eq_52; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_52 = atomics_a_mask_sub_2_1_6 \| _atomics_a_mask_acc_T_52; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_53 = atomics_a_mask_sub_2_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_53 = atomics_a_mask_size_6 & atomics_a_mask_eq_53; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_53 = atomics_a_mask_sub_2_1_6 \| _atomics_a_mask_acc_T_53; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_54 = atomics_a_mask_sub_3_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_54 = atomics_a_mask_size_6 & atomics_a_mask_eq_54; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_54 = atomics_a_mask_sub_3_1_6 \| _atomics_a_mask_acc_T_54; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_55 = atomics_a_mask_sub_3_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_55 = atomics_a_mask_size_6 & atomics_a_mask_eq_55; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_55 = atomics_a_mask_sub_3_1_6 \| _atomics_a_mask_acc_T_55; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_6 = {atomics_a_mask_acc_49, atomics_a_mask_acc_48}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_6 = {atomics_a_mask_acc_51, atomics_a_mask_acc_50}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_6 = {atomics_a_mask_lo_hi_6, atomics_a_mask_lo_lo_6}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_6 = {atomics_a_mask_acc_53, atomics_a_mask_acc_52}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_6 = {atomics_a_mask_acc_55, atomics_a_mask_acc_54}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_6 = {atomics_a_mask_hi_hi_6, atomics_a_mask_hi_lo_6}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_6 = {atomics_a_mask_hi_6, atomics_a_mask_lo_6}; // @[Misc.scala:222:10] assign atomics_a_6_mask = _atomics_a_mask_T_6; // @[Misc.scala:222:10] wire [34:0] _atomics_legal_T_215 = {1'h0, _atomics_legal_T_214}; // @[Parameters.scala:137:{31,41}] wire [34:0] _atomics_legal_T_216 = _atomics_legal_T_215 & 35'h8110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _atomics_legal_T_217 = _atomics_legal_T_216; // @[Parameters.scala:137:46] wire _atomics_legal_T_218 = _atomics_legal_T_217 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _atomics_legal_T_220 = {1'h0, _atomics_legal_T_219}; // @[Parameters.scala:137:{31,41}] wire [34:0] _atomics_legal_T_221 = _atomics_legal_T_220 & 35'h8101000; // @[Parameters.scala:137:{41,46}] wire [34:0] _atomics_legal_T_222 = _atomics_legal_T_221; // @[Parameters.scala:137:46] wire _atomics_legal_T_223 = _atomics_legal_T_222 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _atomics_legal_T_225 = {1'h0, _atomics_legal_T_224}; // @[Parameters.scala:137:{31,41}] wire [34:0] _atomics_legal_T_226 = _atomics_legal_T_225 & 35'h8000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _atomics_legal_T_227 = _atomics_legal_T_226; // @[Parameters.scala:137:46] wire _atomics_legal_T_228 = _atomics_legal_T_227 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_229 = _atomics_legal_T_218 \| _atomics_legal_T_223; // @[Parameters.scala:685:42] wire _atomics_legal_T_230 = _atomics_legal_T_229 \| _atomics_legal_T_228; // @[Parameters.scala:685:42] wire _atomics_legal_T_231 = _atomics_legal_T_230; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_239 = _atomics_legal_T_231; // @[Parameters.scala:684:54, :686:26] wire [34:0] _atomics_legal_T_234 = {1'h0, _atomics_legal_T_233}; // @[Parameters.scala:137:{31,41}] wire [34:0] _atomics_legal_T_235 = _atomics_legal_T_234 & 35'h8110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _atomics_legal_T_236 = _atomics_legal_T_235; // @[Parameters.scala:137:46] wire _atomics_legal_T_237 = _atomics_legal_T_236 == 35'h0; // @[Parameters.scala:137:{46,59}] wire atomics_legal_7 = _atomics_legal_T_239; // @[Parameters.scala:686:26] wire [7:0] _atomics_a_mask_T_7; // @[Misc.scala:222:10] wire [7:0] atomics_a_7_mask; // @[Edges.scala:517:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_7 = _atomics_a_mask_sizeOH_T_21[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_22 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_7; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_23 = _atomics_a_mask_sizeOH_T_22[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH_7 = {_atomics_a_mask_sizeOH_T_23[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1_7 = &s2_req_size; // @[Misc.scala:206:21] wire atomics_a_mask_sub_sub_size_7 = atomics_a_mask_sizeOH_7[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2_7 = atomics_a_mask_sub_sub_bit_7; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit_7 = ~atomics_a_mask_sub_sub_bit_7; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_7 = atomics_a_mask_sub_sub_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_14 = atomics_a_mask_sub_sub_size_7 & atomics_a_mask_sub_sub_0_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_7 = atomics_a_mask_sub_sub_sub_0_1_7 \| _atomics_a_mask_sub_sub_acc_T_14; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_15 = atomics_a_mask_sub_sub_size_7 & atomics_a_mask_sub_sub_1_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_7 = atomics_a_mask_sub_sub_sub_0_1_7 \| _atomics_a_mask_sub_sub_acc_T_15; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size_7 = atomics_a_mask_sizeOH_7[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_7 = ~atomics_a_mask_sub_bit_7; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_7 = atomics_a_mask_sub_sub_0_2_7 & atomics_a_mask_sub_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_28 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_0_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_7 = atomics_a_mask_sub_sub_0_1_7 \| _atomics_a_mask_sub_acc_T_28; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_7 = atomics_a_mask_sub_sub_0_2_7 & atomics_a_mask_sub_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_29 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_1_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_7 = atomics_a_mask_sub_sub_0_1_7 \| _atomics_a_mask_sub_acc_T_29; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_7 = atomics_a_mask_sub_sub_1_2_7 & atomics_a_mask_sub_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_30 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_2_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_7 = atomics_a_mask_sub_sub_1_1_7 \| _atomics_a_mask_sub_acc_T_30; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_7 = atomics_a_mask_sub_sub_1_2_7 & atomics_a_mask_sub_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_31 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_3_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_7 = atomics_a_mask_sub_sub_1_1_7 \| _atomics_a_mask_sub_acc_T_31; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_7 = atomics_a_mask_sizeOH_7[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_7 = ~atomics_a_mask_bit_7; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_56 = atomics_a_mask_sub_0_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_56 = atomics_a_mask_size_7 & atomics_a_mask_eq_56; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_56 = atomics_a_mask_sub_0_1_7 \| _atomics_a_mask_acc_T_56; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_57 = atomics_a_mask_sub_0_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_57 = atomics_a_mask_size_7 & atomics_a_mask_eq_57; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_57 = atomics_a_mask_sub_0_1_7 \| _atomics_a_mask_acc_T_57; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_58 = atomics_a_mask_sub_1_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_58 = atomics_a_mask_size_7 & atomics_a_mask_eq_58; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_58 = atomics_a_mask_sub_1_1_7 \| _atomics_a_mask_acc_T_58; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_59 = atomics_a_mask_sub_1_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_59 = atomics_a_mask_size_7 & atomics_a_mask_eq_59; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_59 = atomics_a_mask_sub_1_1_7 \| _atomics_a_mask_acc_T_59; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_60 = atomics_a_mask_sub_2_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_60 = atomics_a_mask_size_7 & atomics_a_mask_eq_60; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_60 = atomics_a_mask_sub_2_1_7 \| _atomics_a_mask_acc_T_60; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_61 = atomics_a_mask_sub_2_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_61 = atomics_a_mask_size_7 & atomics_a_mask_eq_61; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_61 = atomics_a_mask_sub_2_1_7 \| _atomics_a_mask_acc_T_61; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_62 = atomics_a_mask_sub_3_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_62 = atomics_a_mask_size_7 & atomics_a_mask_eq_62; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_62 = atomics_a_mask_sub_3_1_7 \| _atomics_a_mask_acc_T_62; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_63 = atomics_a_mask_sub_3_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_63 = atomics_a_mask_size_7 & atomics_a_mask_eq_63; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_63 = atomics_a_mask_sub_3_1_7 \| _atomics_a_mask_acc_T_63; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_7 = {atomics_a_mask_acc_57, atomics_a_mask_acc_56}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_7 = {atomics_a_mask_acc_59, atomics_a_mask_acc_58}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_7 = {atomics_a_mask_lo_hi_7, atomics_a_mask_lo_lo_7}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_7 = {atomics_a_mask_acc_61, atomics_a_mask_acc_60}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_7 = {atomics_a_mask_acc_63, atomics_a_mask_acc_62}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_7 = {atomics_a_mask_hi_hi_7, atomics_a_mask_hi_lo_7}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_7 = {atomics_a_mask_hi_7, atomics_a_mask_lo_7}; // @[Misc.scala:222:10] assign atomics_a_7_mask = _atomics_a_mask_T_7; // @[Misc.scala:222:10] wire [34:0] _atomics_legal_T_245 = {1'h0, _atomics_legal_T_244}; // @[Parameters.scala:137:{31,41}] wire [34:0] _atomics_legal_T_246 = _atomics_legal_T_245 & 35'h8110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _atomics_legal_T_247 = _atomics_legal_T_246; // @[Parameters.scala:137:46] wire _atomics_legal_T_248 = _atomics_legal_T_247 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _atomics_legal_T_250 = {1'h0, _atomics_legal_T_249}; // @[Parameters.scala:137:{31,41}] wire [34:0] _atomics_legal_T_251 = _atomics_legal_T_250 & 35'h8101000; // @[Parameters.scala:137:{41,46}] wire [34:0] _atomics_legal_T_252 = _atomics_legal_T_251; // @[Parameters.scala:137:46] wire _atomics_legal_T_253 = _atomics_legal_T_252 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _atomics_legal_T_255 = {1'h0, _atomics_legal_T_254}; // @[Parameters.scala:137:{31,41}] wire [34:0] _atomics_legal_T_256 = _atomics_legal_T_255 & 35'h8000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _atomics_legal_T_257 = _atomics_legal_T_256; // @[Parameters.scala:137:46] wire _atomics_legal_T_258 = _atomics_legal_T_257 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_259 = _atomics_legal_T_248 \| _atomics_legal_T_253; // @[Parameters.scala:685:42] wire _atomics_legal_T_260 = _atomics_legal_T_259 \| _atomics_legal_T_258; // @[Parameters.scala:685:42] wire _atomics_legal_T_261 = _atomics_legal_T_260; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_269 = _atomics_legal_T_261; // @[Parameters.scala:684:54, :686:26] wire [34:0] _atomics_legal_T_264 = {1'h0, _atomics_legal_T_263}; // @[Parameters.scala:137:{31,41}] wire [34:0] _atomics_legal_T_265 = _atomics_legal_T_264 & 35'h8110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _atomics_legal_T_266 = _atomics_legal_T_265; // @[Parameters.scala:137:46] wire _atomics_legal_T_267 = _atomics_legal_T_266 == 35'h0; // @[Parameters.scala:137:{46,59}] wire atomics_legal_8 = _atomics_legal_T_269; // @[Parameters.scala:686:26] wire [7:0] _atomics_a_mask_T_8; // @[Misc.scala:222:10] wire [7:0] atomics_a_8_mask; // @[Edges.scala:517:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_8 = _atomics_a_mask_sizeOH_T_24[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_25 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_8; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_26 = _atomics_a_mask_sizeOH_T_25[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH_8 = {_atomics_a_mask_sizeOH_T_26[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1_8 = &s2_req_size; // @[Misc.scala:206:21] wire atomics_a_mask_sub_sub_size_8 = atomics_a_mask_sizeOH_8[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2_8 = atomics_a_mask_sub_sub_bit_8; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit_8 = ~atomics_a_mask_sub_sub_bit_8; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_8 = atomics_a_mask_sub_sub_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_16 = atomics_a_mask_sub_sub_size_8 & atomics_a_mask_sub_sub_0_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_8 = atomics_a_mask_sub_sub_sub_0_1_8 \| _atomics_a_mask_sub_sub_acc_T_16; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_17 = atomics_a_mask_sub_sub_size_8 & atomics_a_mask_sub_sub_1_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_8 = atomics_a_mask_sub_sub_sub_0_1_8 \| _atomics_a_mask_sub_sub_acc_T_17; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size_8 = atomics_a_mask_sizeOH_8[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_8 = ~atomics_a_mask_sub_bit_8; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_8 = atomics_a_mask_sub_sub_0_2_8 & atomics_a_mask_sub_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_32 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_0_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_8 = atomics_a_mask_sub_sub_0_1_8 \| _atomics_a_mask_sub_acc_T_32; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_8 = atomics_a_mask_sub_sub_0_2_8 & atomics_a_mask_sub_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_33 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_1_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_8 = atomics_a_mask_sub_sub_0_1_8 \| _atomics_a_mask_sub_acc_T_33; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_8 = atomics_a_mask_sub_sub_1_2_8 & atomics_a_mask_sub_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_34 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_2_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_8 = atomics_a_mask_sub_sub_1_1_8 \| _atomics_a_mask_sub_acc_T_34; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_8 = atomics_a_mask_sub_sub_1_2_8 & atomics_a_mask_sub_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_35 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_3_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_8 = atomics_a_mask_sub_sub_1_1_8 \| _atomics_a_mask_sub_acc_T_35; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_8 = atomics_a_mask_sizeOH_8[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_8 = ~atomics_a_mask_bit_8; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_64 = atomics_a_mask_sub_0_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_64 = atomics_a_mask_size_8 & atomics_a_mask_eq_64; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_64 = atomics_a_mask_sub_0_1_8 \| _atomics_a_mask_acc_T_64; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_65 = atomics_a_mask_sub_0_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_65 = atomics_a_mask_size_8 & atomics_a_mask_eq_65; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_65 = atomics_a_mask_sub_0_1_8 \| _atomics_a_mask_acc_T_65; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_66 = atomics_a_mask_sub_1_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_66 = atomics_a_mask_size_8 & atomics_a_mask_eq_66; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_66 = atomics_a_mask_sub_1_1_8 \| _atomics_a_mask_acc_T_66; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_67 = atomics_a_mask_sub_1_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_67 = atomics_a_mask_size_8 & atomics_a_mask_eq_67; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_67 = atomics_a_mask_sub_1_1_8 \| _atomics_a_mask_acc_T_67; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_68 = atomics_a_mask_sub_2_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_68 = atomics_a_mask_size_8 & atomics_a_mask_eq_68; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_68 = atomics_a_mask_sub_2_1_8 \| _atomics_a_mask_acc_T_68; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_69 = atomics_a_mask_sub_2_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_69 = atomics_a_mask_size_8 & atomics_a_mask_eq_69; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_69 = atomics_a_mask_sub_2_1_8 \| _atomics_a_mask_acc_T_69; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_70 = atomics_a_mask_sub_3_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_70 = atomics_a_mask_size_8 & atomics_a_mask_eq_70; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_70 = atomics_a_mask_sub_3_1_8 \| _atomics_a_mask_acc_T_70; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_71 = atomics_a_mask_sub_3_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_71 = atomics_a_mask_size_8 & atomics_a_mask_eq_71; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_71 = atomics_a_mask_sub_3_1_8 \| _atomics_a_mask_acc_T_71; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_8 = {atomics_a_mask_acc_65, atomics_a_mask_acc_64}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_8 = {atomics_a_mask_acc_67, atomics_a_mask_acc_66}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_8 = {atomics_a_mask_lo_hi_8, atomics_a_mask_lo_lo_8}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_8 = {atomics_a_mask_acc_69, atomics_a_mask_acc_68}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_8 = {atomics_a_mask_acc_71, atomics_a_mask_acc_70}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_8 = {atomics_a_mask_hi_hi_8, atomics_a_mask_hi_lo_8}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_8 = {atomics_a_mask_hi_8, atomics_a_mask_lo_8}; // @[Misc.scala:222:10] assign atomics_a_8_mask = _atomics_a_mask_T_8; // @[Misc.scala:222:10] wire [2:0] _GEN_99 = _atomics_T ? 3'h3 : 3'h0; // @[DCache.scala:587:81] wire [2:0] _atomics_T_1_opcode; // @[DCache.scala:587:81] assign _atomics_T_1_opcode = _GEN_99; // @[DCache.scala:587:81] wire [2:0] _atomics_T_1_param; // @[DCache.scala:587:81] assign _atomics_T_1_param = _GEN_99; // @[DCache.scala:587:81] wire [3:0] _atomics_T_1_size = _atomics_T ? atomics_a_size : 4'h0; // @[Edges.scala:534:17] wire [31:0] _atomics_T_1_address = _atomics_T ? atomics_a_address : 32'h0; // @[Edges.scala:534:17] wire [7:0] _atomics_T_1_mask = _atomics_T ? atomics_a_mask : 8'h0; // @[Edges.scala:534:17] wire [63:0] _atomics_T_1_data = _atomics_T ? atomics_a_data : 64'h0; // @[Edges.scala:534:17] wire [2:0] _atomics_T_3_opcode = _atomics_T_2 ? 3'h3 : _atomics_T_1_opcode; // @[DCache.scala:587:81] wire [2:0] _atomics_T_3_param = _atomics_T_2 ? 3'h0 : _atomics_T_1_param; // @[DCache.scala:587:81] wire [3:0] _atomics_T_3_size = _atomics_T_2 ? atomics_a_1_size : _atomics_T_1_size; // @[Edges.scala:534:17] wire [31:0] _atomics_T_3_address = _atomics_T_2 ? atomics_a_1_address : _atomics_T_1_address; // @[Edges.scala:534:17] wire [7:0] _atomics_T_3_mask = _atomics_T_2 ? atomics_a_1_mask : _atomics_T_1_mask; // @[Edges.scala:534:17] wire [63:0] _atomics_T_3_data = _atomics_T_2 ? atomics_a_1_data : _atomics_T_1_data; // @[Edges.scala:534:17] wire [2:0] _atomics_T_5_opcode = _atomics_T_4 ? 3'h3 : _atomics_T_3_opcode; // @[DCache.scala:587:81] wire [2:0] _atomics_T_5_param = _atomics_T_4 ? 3'h1 : _atomics_T_3_param; // @[DCache.scala:587:81] wire [3:0] _atomics_T_5_size = _atomics_T_4 ? atomics_a_2_size : _atomics_T_3_size; // @[Edges.scala:534:17] wire [31:0] _atomics_T_5_address = _atomics_T_4 ? atomics_a_2_address : _atomics_T_3_address; // @[Edges.scala:534:17] wire [7:0] _atomics_T_5_mask = _atomics_T_4 ? atomics_a_2_mask : _atomics_T_3_mask; // @[Edges.scala:534:17] wire [63:0] _atomics_T_5_data = _atomics_T_4 ? atomics_a_2_data : _atomics_T_3_data; // @[Edges.scala:534:17] wire [2:0] _atomics_T_7_opcode = _atomics_T_6 ? 3'h3 : _atomics_T_5_opcode; // @[DCache.scala:587:81] wire [2:0] _atomics_T_7_param = _atomics_T_6 ? 3'h2 : _atomics_T_5_param; // @[DCache.scala:587:81] wire [3:0] _atomics_T_7_size = _atomics_T_6 ? atomics_a_3_size : _atomics_T_5_size; // @[Edges.scala:534:17] wire [31:0] _atomics_T_7_address = _atomics_T_6 ? atomics_a_3_address : _atomics_T_5_address; // @[Edges.scala:534:17] wire [7:0] _atomics_T_7_mask = _atomics_T_6 ? atomics_a_3_mask : _atomics_T_5_mask; // @[Edges.scala:534:17] wire [63:0] _atomics_T_7_data = _atomics_T_6 ? atomics_a_3_data : _atomics_T_5_data; // @[Edges.scala:534:17] wire [2:0] _atomics_T_9_opcode = _atomics_T_8 ? 3'h2 : _atomics_T_7_opcode; // @[DCache.scala:587:81] wire [2:0] _atomics_T_9_param = _atomics_T_8 ? 3'h4 : _atomics_T_7_param; // @[DCache.scala:587:81] wire [3:0] _atomics_T_9_size = _atomics_T_8 ? atomics_a_4_size : _atomics_T_7_size; // @[Edges.scala:517:17] wire [31:0] _atomics_T_9_address = _atomics_T_8 ? atomics_a_4_address : _atomics_T_7_address; // @[Edges.scala:517:17] wire [7:0] _atomics_T_9_mask = _atomics_T_8 ? atomics_a_4_mask : _atomics_T_7_mask; // @[Edges.scala:517:17] wire [63:0] _atomics_T_9_data = _atomics_T_8 ? atomics_a_4_data : _atomics_T_7_data; // @[Edges.scala:517:17] wire [2:0] _atomics_T_11_opcode = _atomics_T_10 ? 3'h2 : _atomics_T_9_opcode; // @[DCache.scala:587:81] wire [2:0] _atomics_T_11_param = _atomics_T_10 ? 3'h0 : _atomics_T_9_param; // @[DCache.scala:587:81] wire [3:0] _atomics_T_11_size = _atomics_T_10 ? atomics_a_5_size : _atomics_T_9_size; // @[Edges.scala:517:17] wire [31:0] _atomics_T_11_address = _atomics_T_10 ? atomics_a_5_address : _atomics_T_9_address; // @[Edges.scala:517:17] wire [7:0] _atomics_T_11_mask = _atomics_T_10 ? atomics_a_5_mask : _atomics_T_9_mask; // @[Edges.scala:517:17] wire [63:0] _atomics_T_11_data = _atomics_T_10 ? atomics_a_5_data : _atomics_T_9_data; // @[Edges.scala:517:17] wire [2:0] _atomics_T_13_opcode = _atomics_T_12 ? 3'h2 : _atomics_T_11_opcode; // @[DCache.scala:587:81] wire [2:0] _atomics_T_13_param = _atomics_T_12 ? 3'h1 : _atomics_T_11_param; // @[DCache.scala:587:81] wire [3:0] _atomics_T_13_size = _atomics_T_12 ? atomics_a_6_size : _atomics_T_11_size; // @[Edges.scala:517:17] wire [31:0] _atomics_T_13_address = _atomics_T_12 ? atomics_a_6_address : _atomics_T_11_address; // @[Edges.scala:517:17] wire [7:0] _atomics_T_13_mask = _atomics_T_12 ? atomics_a_6_mask : _atomics_T_11_mask; // @[Edges.scala:517:17] wire [63:0] _atomics_T_13_data = _atomics_T_12 ? atomics_a_6_data : _atomics_T_11_data; // @[Edges.scala:517:17] wire [2:0] _atomics_T_15_opcode = _atomics_T_14 ? 3'h2 : _atomics_T_13_opcode; // @[DCache.scala:587:81] wire [2:0] _atomics_T_15_param = _atomics_T_14 ? 3'h2 : _atomics_T_13_param; // @[DCache.scala:587:81] wire [3:0] _atomics_T_15_size = _atomics_T_14 ? atomics_a_7_size : _atomics_T_13_size; // @[Edges.scala:517:17] wire [31:0] _atomics_T_15_address = _atomics_T_14 ? atomics_a_7_address : _atomics_T_13_address; // @[Edges.scala:517:17] wire [7:0] _atomics_T_15_mask = _atomics_T_14 ? atomics_a_7_mask : _atomics_T_13_mask; // @[Edges.scala:517:17] wire [63:0] _atomics_T_15_data = _atomics_T_14 ? atomics_a_7_data : _atomics_T_13_data; // @[Edges.scala:517:17] wire [2:0] atomics_opcode = _atomics_T_16 ? 3'h2 : _atomics_T_15_opcode; // @[DCache.scala:587:81] wire [2:0] atomics_param = _atomics_T_16 ? 3'h3 : _atomics_T_15_param; // @[DCache.scala:587:81] wire [3:0] atomics_size = _atomics_T_16 ? atomics_a_8_size : _atomics_T_15_size; // @[Edges.scala:517:17] wire [31:0] atomics_address = _atomics_T_16 ? atomics_a_8_address : _atomics_T_15_address; // @[Edges.scala:517:17] wire [7:0] atomics_mask = _atomics_T_16 ? atomics_a_8_mask : _atomics_T_15_mask; // @[Edges.scala:517:17] wire [63:0] atomics_data = _atomics_T_16 ? atomics_a_8_data : _atomics_T_15_data; // @[Edges.scala:517:17] wire [14:0] _tl_out_a_valid_T_2 = _tl_out_a_valid_T_1[20:6]; // @[DCache.scala:606:{43,62}] wire _tl_out_a_valid_T_3 = _tl_out_a_valid_T_2 == 15'h0; // @[DCache.scala:582:29, :606:{62,118}] wire _tl_out_a_valid_T_10 = ~s2_victim_dirty; // @[Misc.scala:38:9] wire _tl_out_a_valid_T_11 = _tl_out_a_valid_T_10; // @[DCache.scala:607:{88,91}] wire _tl_out_a_valid_T_12 = _tl_out_a_valid_T_6 & _tl_out_a_valid_T_11; // @[DCache.scala:605:29, :606:127, :607:88] wire _tl_out_a_valid_T_13 = s2_valid_uncached_pending \| _tl_out_a_valid_T_12; // @[DCache.scala:430:64, :604:32, :606:127] assign _tl_out_a_valid_T_14 = _tl_out_a_valid_T_13; // @[DCache.scala:603:37, :604:32] assign tl_out_a_valid = _tl_out_a_valid_T_14; // @[DCache.scala:159:22, :603:37] wire _tl_out_a_bits_T = ~s2_uncached; // @[DCache.scala:424:39, :425:47, :608:24] wire _tl_out_a_bits_T_1 = ~s2_write; // @[DCache.scala:609:9] wire _tl_out_a_bits_T_3 = ~s2_read; // @[DCache.scala:611:9] wire [2:0] _tl_out_a_bits_T_4_opcode = _tl_out_a_bits_T_3 ? 3'h0 : atomics_opcode; // @[DCache.scala:587:81, :611:{8,9}] wire [2:0] _tl_out_a_bits_T_4_param = _tl_out_a_bits_T_3 ? 3'h0 : atomics_param; // @[DCache.scala:587:81, :611:{8,9}] wire [3:0] _tl_out_a_bits_T_4_size = _tl_out_a_bits_T_3 ? put_size : atomics_size; // @[Edges.scala:480:17] wire [31:0] _tl_out_a_bits_T_4_address = _tl_out_a_bits_T_3 ? put_address : atomics_address; // @[Edges.scala:480:17] wire [7:0] _tl_out_a_bits_T_4_mask = _tl_out_a_bits_T_3 ? put_mask : atomics_mask; // @[Edges.scala:480:17] wire [63:0] _tl_out_a_bits_T_4_data = _tl_out_a_bits_T_3 ? put_data : atomics_data; // @[Edges.scala:480:17] wire [2:0] _tl_out_a_bits_T_5_opcode = _tl_out_a_bits_T_2 ? 3'h1 : _tl_out_a_bits_T_4_opcode; // @[DCache.scala:610:{8,20}, :611:8] wire [2:0] _tl_out_a_bits_T_5_param = _tl_out_a_bits_T_2 ? 3'h0 : _tl_out_a_bits_T_4_param; // @[DCache.scala:610:{8,20}, :611:8] wire [3:0] _tl_out_a_bits_T_5_size = _tl_out_a_bits_T_2 ? putpartial_size : _tl_out_a_bits_T_4_size; // @[Edges.scala:500:17] wire [31:0] _tl_out_a_bits_T_5_address = _tl_out_a_bits_T_2 ? putpartial_address : _tl_out_a_bits_T_4_address; // @[Edges.scala:500:17] wire [7:0] _tl_out_a_bits_T_5_mask = _tl_out_a_bits_T_2 ? putpartial_mask : _tl_out_a_bits_T_4_mask; // @[Edges.scala:500:17] wire [63:0] _tl_out_a_bits_T_5_data = _tl_out_a_bits_T_2 ? putpartial_data : _tl_out_a_bits_T_4_data; // @[Edges.scala:500:17] wire [2:0] _tl_out_a_bits_T_6_opcode = _tl_out_a_bits_T_1 ? 3'h4 : _tl_out_a_bits_T_5_opcode; // @[DCache.scala:609:{8,9}, :610:8] wire [2:0] _tl_out_a_bits_T_6_param = _tl_out_a_bits_T_1 ? 3'h0 : _tl_out_a_bits_T_5_param; // @[DCache.scala:609:{8,9}, :610:8] wire [3:0] _tl_out_a_bits_T_6_size = _tl_out_a_bits_T_1 ? get_size : _tl_out_a_bits_T_5_size; // @[Edges.scala:460:17] wire [31:0] _tl_out_a_bits_T_6_address = _tl_out_a_bits_T_1 ? get_address : _tl_out_a_bits_T_5_address; // @[Edges.scala:460:17] wire [7:0] _tl_out_a_bits_T_6_mask = _tl_out_a_bits_T_1 ? get_mask : _tl_out_a_bits_T_5_mask; // @[Edges.scala:460:17] wire [63:0] _tl_out_a_bits_T_6_data = _tl_out_a_bits_T_1 ? 64'h0 : _tl_out_a_bits_T_5_data; // @[DCache.scala:609:{8,9}, :610:8] assign _tl_out_a_bits_T_7_opcode = _tl_out_a_bits_T ? 3'h0 : _tl_out_a_bits_T_6_opcode; // @[DCache.scala:608:{23,24}, :609:8] assign _tl_out_a_bits_T_7_param = _tl_out_a_bits_T ? 3'h0 : _tl_out_a_bits_T_6_param; // @[DCache.scala:608:{23,24}, :609:8] assign _tl_out_a_bits_T_7_size = _tl_out_a_bits_T ? 4'h0 : _tl_out_a_bits_T_6_size; // @[DCache.scala:608:{23,24}, :609:8] assign _tl_out_a_bits_T_7_address = _tl_out_a_bits_T ? 32'h0 : _tl_out_a_bits_T_6_address; // @[DCache.scala:608:{23,24}, :609:8] assign _tl_out_a_bits_T_7_mask = _tl_out_a_bits_T ? 8'h0 : _tl_out_a_bits_T_6_mask; // @[DCache.scala:608:{23,24}, :609:8] assign _tl_out_a_bits_T_7_data = _tl_out_a_bits_T ? 64'h0 : _tl_out_a_bits_T_6_data; // @[DCache.scala:608:{23,24}, :609:8] assign tl_out_a_bits_opcode = _tl_out_a_bits_T_7_opcode; // @[DCache.scala:159:22, :608:23] assign tl_out_a_bits_param = _tl_out_a_bits_T_7_param; // @[DCache.scala:159:22, :608:23] assign tl_out_a_bits_size = _tl_out_a_bits_T_7_size; // @[DCache.scala:159:22, :608:23] assign tl_out_a_bits_address = _tl_out_a_bits_T_7_address; // @[DCache.scala:159:22, :608:23] assign tl_out_a_bits_mask = _tl_out_a_bits_T_7_mask; // @[DCache.scala:159:22, :608:23] assign tl_out_a_bits_data = _tl_out_a_bits_T_7_data; // @[DCache.scala:159:22, :608:23] wire _io_cpu_perf_acquire_T = tl_out_a_ready & tl_out_a_valid; // @[Decoupled.scala:51:35] wire [4:0] _uncachedReqs_0_cmd_T_1 = {_uncachedReqs_0_cmd_T, 4'h1}; // @[DCache.scala:637:{37,49}] wire [4:0] _uncachedReqs_0_cmd_T_2 = s2_write ? _uncachedReqs_0_cmd_T_1 : 5'h0; // @[DCache.scala:637:{23,37}] wire _T_90 = nodeOut_d_ready & nodeOut_d_valid; // @[Decoupled.scala:51:35] wire _io_cpu_replay_next_T; // @[Decoupled.scala:51:35] assign _io_cpu_replay_next_T = _T_90; // @[Decoupled.scala:51:35] wire _io_cpu_perf_blocked_near_end_of_refill_T; // @[Decoupled.scala:51:35] assign _io_cpu_perf_blocked_near_end_of_refill_T = _T_90; // @[Decoupled.scala:51:35] wire _io_errors_bus_valid_T; // @[Decoupled.scala:51:35] assign _io_errors_bus_valid_T = _T_90; // @[Decoupled.scala:51:35] wire [26:0] _r_beats1_decode_T = 27'hFFF << nodeOut_d_bits_size; // @[package.scala:243:71] wire [11:0] _r_beats1_decode_T_1 = _r_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _r_beats1_decode_T_2 = ~_r_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] r_beats1_decode = _r_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire r_beats1_opdata = nodeOut_d_bits_opcode[0]; // @[Edges.scala:106:36] wire [8:0] r_beats1 = r_beats1_opdata ? r_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] r_counter; // @[Edges.scala:229:27] wire [9:0] _r_counter1_T = {1'h0, r_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] r_counter1 = _r_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = r_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _r_last_T = r_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _r_last_T_1 = r_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_last = _r_last_T \| _r_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_done = d_last & _T_90; // @[Decoupled.scala:51:35] wire [8:0] _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] r_4 = r_beats1 & _r_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _r_counter_T = d_first ? r_beats1 : r_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] d_address_inc = {r_4, 3'h0}; // @[Edges.scala:234:25, :269:29] wire [1:0] d_opc = nodeOut_d_bits_opcode[1:0]; // @[DCache.scala:656:26] wire [1:0] data_plaInput = d_opc; // @[pla.scala:77:22] wire [1:0] data_invInputs = ~data_plaInput; // @[pla.scala:77:22, :78:21] wire data_invMatrixOutputs; // @[pla.scala:124:31] wire data_plaOutput; // @[pla.scala:81:23] wire grantIsUncachedData = data_plaOutput; // @[pla.scala:81:23] wire data_andMatrixOutputs_andMatrixInput_0 = data_plaInput[0]; // @[pla.scala:77:22, :90:45] wire data_andMatrixOutputs_andMatrixInput_1 = data_invInputs[1]; // @[pla.scala:78:21, :91:29] wire [1:0] _data_andMatrixOutputs_T = {data_andMatrixOutputs_andMatrixInput_0, data_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:90:45, :91:29, :98:53] wire data_andMatrixOutputs_0_2 = &_data_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] wire data_orMatrixOutputs = data_andMatrixOutputs_0_2; // @[pla.scala:98:70, :114:36] assign data_invMatrixOutputs = data_orMatrixOutputs; // @[pla.scala:114:36, :124:31] assign data_plaOutput = data_invMatrixOutputs; // @[pla.scala:81:23, :124:31] wire _tl_d_data_encoded_T_9 = io_ptw_customCSRs_csrs_0_value_0[9]; // @[CustomCSRs.scala:47:65] wire _tl_d_data_encoded_T_10 = ~_tl_d_data_encoded_T_9; // @[CustomCSRs.scala:47:65] wire _tl_d_data_encoded_T_11 = nodeOut_d_bits_corrupt & _tl_d_data_encoded_T_10; // @[DCache.scala:663:{77,80}] wire [15:0] tl_d_data_encoded_lo_lo_1 = {_tl_d_data_encoded_T_15, _tl_d_data_encoded_T_14}; // @[package.scala:45:27, :211:50] wire [15:0] tl_d_data_encoded_lo_hi_1 = {_tl_d_data_encoded_T_17, _tl_d_data_encoded_T_16}; // @[package.scala:45:27, :211:50] wire [31:0] tl_d_data_encoded_lo_1 = {tl_d_data_encoded_lo_hi_1, tl_d_data_encoded_lo_lo_1}; // @[package.scala:45:27] wire [15:0] tl_d_data_encoded_hi_lo_1 = {_tl_d_data_encoded_T_19, _tl_d_data_encoded_T_18}; // @[package.scala:45:27, :211:50] wire [15:0] tl_d_data_encoded_hi_hi_1 = {_tl_d_data_encoded_T_21, _tl_d_data_encoded_T_20}; // @[package.scala:45:27, :211:50] wire [31:0] tl_d_data_encoded_hi_1 = {tl_d_data_encoded_hi_hi_1, tl_d_data_encoded_hi_lo_1}; // @[package.scala:45:27] assign _tl_d_data_encoded_T_22 = {tl_d_data_encoded_hi_1, tl_d_data_encoded_lo_1}; // @[package.scala:45:27] assign tl_d_data_encoded = _tl_d_data_encoded_T_22; // @[package.scala:45:27] wire grantIsCached = _grantIsCached_T \| _grantIsCached_T_1; // @[package.scala:16:47, :81:59] reg grantInProgress; // @[DCache.scala:667:32] wire block_probe_for_ordering = grantInProgress; // @[DCache.scala:667:32, :768:89] reg [2:0] blockProbeAfterGrantCount; // @[DCache.scala:668:42] wire [3:0] _blockProbeAfterGrantCount_T = {1'h0, blockProbeAfterGrantCount} - 4'h1; // @[DCache.scala:668:42, :669:99] wire [2:0] _blockProbeAfterGrantCount_T_1 = _blockProbeAfterGrantCount_T[2:0]; // @[DCache.scala:669:99] wire _nodeOut_d_ready_T = ~d_first; // @[Edges.scala:231:25] wire _nodeOut_d_ready_T_1 = _nodeOut_d_ready_T; // @[DCache.scala:671:{41,50}] wire _nodeOut_d_ready_T_2 = _nodeOut_d_ready_T_1; // @[DCache.scala:671:{50,69}] wire _nodeOut_d_ready_T_3 = ~grantIsCached \| _nodeOut_d_ready_T_2; // @[package.scala:81:59] wire _GEN_100 = _T_90 & grantIsCached; // @[Decoupled.scala:51:35] assign replace = _GEN_100 & d_last; // @[Replacement.scala:37:29, :38:11] wire _GEN_101 = ~_T_90 \| grantIsCached \| ~grantIsUncachedData; // @[Decoupled.scala:51:35] assign s1_data_way = _GEN_101 ? 2'h1 : 2'h2; // @[DCache.scala:323:32, :674:24, :675:26, :684:35] wire [28:0] _s2_req_addr_dontCareBits_T = s1_paddr[31:3]; // @[DCache.scala:298:21, :701:41] wire [31:0] s2_req_addr_dontCareBits = {_s2_req_addr_dontCareBits_T, 3'h0}; // @[DCache.scala:701:{41,55}] wire [2:0] _s2_req_addr_T = uncachedResp_addr[2:0]; // @[DCache.scala:238:30, :702:45] wire [31:0] _s2_req_addr_T_1 = {s2_req_addr_dontCareBits[31:3], s2_req_addr_dontCareBits[2:0] \| _s2_req_addr_T}; // @[DCache.scala:701:55, :702:{26,45}] wire _dataArb_io_in_1_valid_T = nodeOut_d_valid & grantIsRefill; // @[DCache.scala:666:29, :721:44] wire _dataArb_io_in_1_valid_T_1 = _dataArb_io_in_1_valid_T; // @[DCache.scala:721:{44,61}] wire _metaArb_io_in_3_valid_T = grantIsCached & d_done; // @[package.scala:81:59] wire _metaArb_io_in_3_valid_T_1 = ~nodeOut_d_bits_denied; // @[DCache.scala:741:56] assign _metaArb_io_in_3_valid_T_2 = _metaArb_io_in_3_valid_T & _metaArb_io_in_3_valid_T_1; // @[DCache.scala:741:{43,53,56}] assign metaArb_io_in_3_valid = _metaArb_io_in_3_valid_T_2; // @[DCache.scala:135:28, :741:53] assign metaArb_io_in_3_bits_way_en = refill_way[0]; // @[DCache.scala:135:28, :229:23, :743:32] assign metaArb_io_in_3_bits_idx = _metaArb_io_in_3_bits_idx_T; // @[DCache.scala:135:28, :744:40] assign _metaArb_io_in_3_bits_addr_T_2 = {_metaArb_io_in_3_bits_addr_T, _metaArb_io_in_3_bits_addr_T_1}; // @[DCache.scala:745:{36,58,80}] assign metaArb_io_in_3_bits_addr = _metaArb_io_in_3_bits_addr_T_2; // @[DCache.scala:135:28, :745:36] wire _metaArb_io_in_3_bits_data_c_cat_T_2 = _metaArb_io_in_3_bits_data_c_cat_T \| _metaArb_io_in_3_bits_data_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _metaArb_io_in_3_bits_data_c_cat_T_4 = _metaArb_io_in_3_bits_data_c_cat_T_2 \| _metaArb_io_in_3_bits_data_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _metaArb_io_in_3_bits_data_c_cat_T_9 = _metaArb_io_in_3_bits_data_c_cat_T_5 \| _metaArb_io_in_3_bits_data_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_10 = _metaArb_io_in_3_bits_data_c_cat_T_9 \| _metaArb_io_in_3_bits_data_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_11 = _metaArb_io_in_3_bits_data_c_cat_T_10 \| _metaArb_io_in_3_bits_data_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_17 = _metaArb_io_in_3_bits_data_c_cat_T_12 \| _metaArb_io_in_3_bits_data_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_18 = _metaArb_io_in_3_bits_data_c_cat_T_17 \| _metaArb_io_in_3_bits_data_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_19 = _metaArb_io_in_3_bits_data_c_cat_T_18 \| _metaArb_io_in_3_bits_data_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_20 = _metaArb_io_in_3_bits_data_c_cat_T_19 \| _metaArb_io_in_3_bits_data_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_21 = _metaArb_io_in_3_bits_data_c_cat_T_11 \| _metaArb_io_in_3_bits_data_c_cat_T_20; // @[package.scala:81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_22 = _metaArb_io_in_3_bits_data_c_cat_T_4 \| _metaArb_io_in_3_bits_data_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _metaArb_io_in_3_bits_data_c_cat_T_25 = _metaArb_io_in_3_bits_data_c_cat_T_23 \| _metaArb_io_in_3_bits_data_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _metaArb_io_in_3_bits_data_c_cat_T_27 = _metaArb_io_in_3_bits_data_c_cat_T_25 \| _metaArb_io_in_3_bits_data_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _metaArb_io_in_3_bits_data_c_cat_T_32 = _metaArb_io_in_3_bits_data_c_cat_T_28 \| _metaArb_io_in_3_bits_data_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_33 = _metaArb_io_in_3_bits_data_c_cat_T_32 \| _metaArb_io_in_3_bits_data_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_34 = _metaArb_io_in_3_bits_data_c_cat_T_33 \| _metaArb_io_in_3_bits_data_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_40 = _metaArb_io_in_3_bits_data_c_cat_T_35 \| _metaArb_io_in_3_bits_data_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_41 = _metaArb_io_in_3_bits_data_c_cat_T_40 \| _metaArb_io_in_3_bits_data_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_42 = _metaArb_io_in_3_bits_data_c_cat_T_41 \| _metaArb_io_in_3_bits_data_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_43 = _metaArb_io_in_3_bits_data_c_cat_T_42 \| _metaArb_io_in_3_bits_data_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_44 = _metaArb_io_in_3_bits_data_c_cat_T_34 \| _metaArb_io_in_3_bits_data_c_cat_T_43; // @[package.scala:81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_45 = _metaArb_io_in_3_bits_data_c_cat_T_27 \| _metaArb_io_in_3_bits_data_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _metaArb_io_in_3_bits_data_c_cat_T_47 = _metaArb_io_in_3_bits_data_c_cat_T_45 \| _metaArb_io_in_3_bits_data_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _metaArb_io_in_3_bits_data_c_cat_T_49 = _metaArb_io_in_3_bits_data_c_cat_T_47 \| _metaArb_io_in_3_bits_data_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] metaArb_io_in_3_bits_data_c = {_metaArb_io_in_3_bits_data_c_cat_T_22, _metaArb_io_in_3_bits_data_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _metaArb_io_in_3_bits_data_T_1 = {metaArb_io_in_3_bits_data_c, nodeOut_d_bits_param}; // @[Metadata.scala:29:18, :84:18] wire _metaArb_io_in_3_bits_data_T_10 = _metaArb_io_in_3_bits_data_T_1 == 4'h1; // @[Metadata.scala:84:{18,38}] wire [1:0] _metaArb_io_in_3_bits_data_T_11 = {1'h0, _metaArb_io_in_3_bits_data_T_10}; // @[Metadata.scala:84:38] wire _metaArb_io_in_3_bits_data_T_12 = _metaArb_io_in_3_bits_data_T_1 == 4'h0; // @[Metadata.scala:84:{18,38}] wire [1:0] _metaArb_io_in_3_bits_data_T_13 = _metaArb_io_in_3_bits_data_T_12 ? 2'h2 : _metaArb_io_in_3_bits_data_T_11; // @[Metadata.scala:84:38] wire _metaArb_io_in_3_bits_data_T_14 = _metaArb_io_in_3_bits_data_T_1 == 4'h4; // @[Metadata.scala:84:{18,38}] wire [1:0] _metaArb_io_in_3_bits_data_T_15 = _metaArb_io_in_3_bits_data_T_14 ? 2'h2 : _metaArb_io_in_3_bits_data_T_13; // @[Metadata.scala:84:38] wire _metaArb_io_in_3_bits_data_T_16 = _metaArb_io_in_3_bits_data_T_1 == 4'hC; // @[Metadata.scala:84:{18,38}] wire [1:0] _metaArb_io_in_3_bits_data_T_17 = _metaArb_io_in_3_bits_data_T_16 ? 2'h3 : _metaArb_io_in_3_bits_data_T_15; // @[Metadata.scala:84:38] wire [1:0] metaArb_io_in_3_bits_data_meta_state = _metaArb_io_in_3_bits_data_T_17; // @[Metadata.scala:84:38, :160:20] wire [1:0] metaArb_io_in_3_bits_data_meta_1_coh_state = metaArb_io_in_3_bits_data_meta_state; // @[Metadata.scala:160:20] wire [17:0] metaArb_io_in_3_bits_data_meta_1_tag; // @[HellaCache.scala:305:20] assign metaArb_io_in_3_bits_data_meta_1_tag = _metaArb_io_in_3_bits_data_T[17:0]; // @[HellaCache.scala:305:20, :306:14] assign _metaArb_io_in_3_bits_data_T_18 = {metaArb_io_in_3_bits_data_meta_1_coh_state, metaArb_io_in_3_bits_data_meta_1_tag}; // @[HellaCache.scala:305:20] assign metaArb_io_in_3_bits_data = _metaArb_io_in_3_bits_data_T_18; // @[DCache.scala:135:28, :746:134] reg blockUncachedGrant; // @[DCache.scala:750:33] wire _T_100 = grantIsUncachedData & (blockUncachedGrant \| s1_valid); // @[Decode.scala:55:116] assign nodeOut_d_ready = ~(_T_100 \| grantIsRefill & ~dataArb_io_in_1_ready) & _nodeOut_d_ready_T_3; // @[DCache.scala:152:28, :666:29, :671:{18,24}, :722:{23,26,51}, :724:20, :752:{31,68}, :753:22] assign io_cpu_req_ready_0 = _T_100 ? ~(nodeOut_d_valid \| ~metaArb_io_in_7_ready \| _T_4) & _io_cpu_req_ready_T_4 : ~(~metaArb_io_in_7_ready \| _T_4) & _io_cpu_req_ready_T_4; // @[DCache.scala:101:7, :135:28, :195:9, :233:{20,73}, :258:{33,45,64}, :267:{34,53}, :275:{79,98}, :752:{31,68}, :755:29, :756:26] wire _GEN_102 = _T_100 & nodeOut_d_valid; // @[DCache.scala:721:26, :752:{31,68}, :755:29, :757:32] assign dataArb_io_in_1_valid = _GEN_102 \| _dataArb_io_in_1_valid_T_1; // @[DCache.scala:152:28, :721:{26,61}, :752:68, :755:29, :757:32] assign dataArb_io_in_1_bits_write = ~_GEN_102 & pstore_drain; // @[DCache.scala:152:28, :516:27, :721:26, :734:27, :752:68, :755:29, :757:32, :758:37] wire _blockUncachedGrant_T = ~dataArb_io_in_1_ready; // @[DCache.scala:152:28, :722:26, :759:31] wire _block_probe_for_core_progress_T = \|blockProbeAfterGrantCount; // @[DCache.scala:668:42, :669:35, :766:65] wire block_probe_for_core_progress = _block_probe_for_core_progress_T \| lrscValid; // @[DCache.scala:473:29, :766:{65,71}] wire [14:0] _block_probe_for_pending_release_ack_T_1 = _block_probe_for_pending_release_ack_T[20:6]; // @[DCache.scala:767:{88,107}] wire _block_probe_for_pending_release_ack_T_2 = _block_probe_for_pending_release_ack_T_1 == 15'h0; // @[DCache.scala:582:29, :767:{107,163}] wire _metaArb_io_in_6_valid_T = ~block_probe_for_core_progress; // @[DCache.scala:766:71, :769:48] wire _metaArb_io_in_6_valid_T_1 = _metaArb_io_in_6_valid_T \| lrscBackingOff; // @[DCache.scala:474:40, :769:{48,79}] wire [1:0] _metaArb_io_in_6_bits_addr_T = io_cpu_req_bits_addr_0[33:32]; // @[DCache.scala:101:7, :773:58] assign _metaArb_io_in_6_bits_addr_T_1 = {_metaArb_io_in_6_bits_addr_T, 32'h0}; // @[DCache.scala:773:{36,58}] assign metaArb_io_in_6_bits_addr = _metaArb_io_in_6_bits_addr_T_1; // @[DCache.scala:135:28, :773:36] wire _releaseRejected_T_2; // @[DCache.scala:803:44] wire releaseRejected; // @[DCache.scala:800:29] wire _s2_release_data_valid_T = ~releaseRejected; // @[DCache.scala:800:29, :802:64] reg s2_release_data_valid; // @[DCache.scala:802:38] assign _releaseRejected_T_2 = s2_release_data_valid; // @[DCache.scala:802:38, :803:44] wire _tl_out_c_valid_T_3 = s2_release_data_valid; // @[DCache.scala:802:38, :810:44] assign releaseRejected = _releaseRejected_T_2; // @[DCache.scala:800:29, :803:44] wire [1:0] _releaseDataBeat_T_1 = {1'h0, s2_release_data_valid}; // @[DCache.scala:802:38, :804:98] wire [2:0] _releaseDataBeat_T_2 = {1'h0, _releaseDataBeat_T_1}; // @[DCache.scala:804:{93,98}] wire [1:0] _releaseDataBeat_T_3 = _releaseDataBeat_T_2[1:0]; // @[DCache.scala:804:93] wire [1:0] _releaseDataBeat_T_4 = releaseRejected ? 2'h0 : _releaseDataBeat_T_3; // @[DCache.scala:800:29, :804:{48,93}] wire [10:0] _releaseDataBeat_T_5 = {9'h0, _releaseDataBeat_T_4}; // @[DCache.scala:804:{43,48}] wire [9:0] releaseDataBeat = _releaseDataBeat_T_5[9:0]; // @[DCache.scala:804:43] assign _tl_out_c_valid_T_6 = _tl_out_c_valid_T_3; // @[DCache.scala:810:{44,117}] assign tl_out_c_valid = _tl_out_c_valid_T_6; // @[Bundles.scala:265:61] wire [1:0] metaArb_io_in_4_bits_data_meta_coh_state = newCoh_state; // @[HellaCache.scala:305:20] wire _dataArb_io_in_2_valid_T = releaseDataBeat < 10'h8; // @[DCache.scala:804:43, :900:60] wire [2:0] _dataArb_io_in_2_bits_addr_T_2 = releaseDataBeat[2:0]; // @[DCache.scala:804:43, :903:90] wire [5:0] _dataArb_io_in_2_bits_addr_T_3 = {_dataArb_io_in_2_bits_addr_T_2, 3'h0}; // @[DCache.scala:903:{90,117}] assign _dataArb_io_in_2_bits_addr_T_4 = {8'h0, _dataArb_io_in_2_bits_addr_T_3}; // @[DCache.scala:903:{72,117}] assign dataArb_io_in_2_bits_addr = _dataArb_io_in_2_bits_addr_T_4; // @[DCache.scala:152:28, :903:72] assign _metaArb_io_in_4_bits_addr_T_2 = {_metaArb_io_in_4_bits_addr_T, 14'h0}; // @[DCache.scala:912:{36,58}] assign metaArb_io_in_4_bits_addr = _metaArb_io_in_4_bits_addr_T_2; // @[DCache.scala:135:28, :912:36] assign _metaArb_io_in_4_bits_data_T_1 = {metaArb_io_in_4_bits_data_meta_coh_state, 18'h0}; // @[HellaCache.scala:305:20] assign metaArb_io_in_4_bits_data = _metaArb_io_in_4_bits_data_T_1; // @[DCache.scala:135:28, :913:97] assign metaArb_io_in_5_bits_data = _metaArb_io_in_4_bits_data_T_1; // @[DCache.scala:135:28, :913:97] assign metaArb_io_in_6_bits_data = _metaArb_io_in_4_bits_data_T_1; // @[DCache.scala:135:28, :913:97] assign metaArb_io_in_7_bits_data = _metaArb_io_in_4_bits_data_T_1; // @[DCache.scala:135:28, :913:97] wire _io_cpu_s2_uncached_T = ~s2_hit; // @[Misc.scala:35:9] assign _io_cpu_s2_uncached_T_1 = s2_uncached & _io_cpu_s2_uncached_T; // @[DCache.scala:424:39, :920:{37,40}] assign io_cpu_s2_uncached_0 = _io_cpu_s2_uncached_T_1; // @[DCache.scala:101:7, :920:37] wire _io_cpu_ordered_T = ~s1_req_no_xcpt; // @[DCache.scala:196:25, :929:35] wire _io_cpu_ordered_T_1 = s1_valid & _io_cpu_ordered_T; // @[DCache.scala:182:25, :929:{32,35}] wire _io_cpu_ordered_T_2 = ~s2_req_no_xcpt; // @[DCache.scala:339:19, :929:72] wire _io_cpu_ordered_T_3 = s2_valid & _io_cpu_ordered_T_2; // @[DCache.scala:331:25, :929:{69,72}] wire _io_cpu_ordered_T_4 = _io_cpu_ordered_T_1 \| _io_cpu_ordered_T_3; // @[DCache.scala:929:{32,57,69}] wire _io_cpu_ordered_T_5 = _io_cpu_ordered_T_4 \| cached_grant_wait; // @[DCache.scala:223:34, :929:{57,94}] wire _io_cpu_ordered_T_7 = _io_cpu_ordered_T_5 \| _io_cpu_ordered_T_6; // @[DCache.scala:929:{94,115,142}] assign _io_cpu_ordered_T_8 = ~_io_cpu_ordered_T_7; // @[DCache.scala:929:{21,115}] assign io_cpu_ordered_0 = _io_cpu_ordered_T_8; // @[DCache.scala:101:7, :929:21] wire _io_cpu_store_pending_T_2 = _io_cpu_store_pending_T \| _io_cpu_store_pending_T_1; // @[Consts.scala:90:{32,42,49}] wire _io_cpu_store_pending_T_4 = _io_cpu_store_pending_T_2 \| _io_cpu_store_pending_T_3; // @[Consts.scala:90:{42,59,66}] wire _io_cpu_store_pending_T_9 = _io_cpu_store_pending_T_5 \| _io_cpu_store_pending_T_6; // @[package.scala:16:47, :81:59] wire _io_cpu_store_pending_T_10 = _io_cpu_store_pending_T_9 \| _io_cpu_store_pending_T_7; // @[package.scala:16:47, :81:59] wire _io_cpu_store_pending_T_11 = _io_cpu_store_pending_T_10 \| _io_cpu_store_pending_T_8; // @[package.scala:16:47, :81:59] wire _io_cpu_store_pending_T_17 = _io_cpu_store_pending_T_12 \| _io_cpu_store_pending_T_13; // @[package.scala:16:47, :81:59] wire _io_cpu_store_pending_T_18 = _io_cpu_store_pending_T_17 \| _io_cpu_store_pending_T_14; // @[package.scala:16:47, :81:59] wire _io_cpu_store_pending_T_19 = _io_cpu_store_pending_T_18 \| _io_cpu_store_pending_T_15; // @[package.scala:16:47, :81:59] wire _io_cpu_store_pending_T_20 = _io_cpu_store_pending_T_19 \| _io_cpu_store_pending_T_16; // @[package.scala:16:47, :81:59] wire _io_cpu_store_pending_T_21 = _io_cpu_store_pending_T_11 \| _io_cpu_store_pending_T_20; // @[package.scala:81:59] wire _io_cpu_store_pending_T_22 = _io_cpu_store_pending_T_4 \| _io_cpu_store_pending_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _io_cpu_store_pending_T_23 = cached_grant_wait & _io_cpu_store_pending_T_22; // @[DCache.scala:223:34, :930:46] assign _io_cpu_store_pending_T_25 = _io_cpu_store_pending_T_23 \| _io_cpu_store_pending_T_24; // @[DCache.scala:930:{46,70,97}] assign io_cpu_store_pending_0 = _io_cpu_store_pending_T_25; // @[DCache.scala:101:7, :930:70] wire _s1_xcpt_valid_T = ~s1_req_no_xcpt; // @[DCache.scala:196:25, :929:35, :932:43] wire _s1_xcpt_valid_T_1 = _tlb_io_req_valid_T_3 & _s1_xcpt_valid_T; // @[DCache.scala:273:40, :932:{40,43}] wire _s1_xcpt_valid_T_2 = ~s1_nack; // @[DCache.scala:185:28, :187:41, :932:68] wire s1_xcpt_valid = _s1_xcpt_valid_T_1 & _s1_xcpt_valid_T_2; // @[DCache.scala:932:{40,65,68}] reg io_cpu_s2_xcpt_REG; // @[DCache.scala:933:32] wire [31:0] _io_cpu_s2_xcpt_T_paddr = io_cpu_s2_xcpt_REG ? s2_tlb_xcpt_paddr : 32'h0; // @[DCache.scala:342:24, :933:{24,32}] wire [33:0] _io_cpu_s2_xcpt_T_gpa = io_cpu_s2_xcpt_REG ? s2_tlb_xcpt_gpa : 34'h0; // @[DCache.scala:342:24, :933:{24,32}] assign _io_cpu_s2_xcpt_T_pf_ld = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_pf_ld; // @[DCache.scala:342:24, :933:{24,32}] assign _io_cpu_s2_xcpt_T_pf_st = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_pf_st; // @[DCache.scala:342:24, :933:{24,32}] wire _io_cpu_s2_xcpt_T_pf_inst = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_pf_inst; // @[DCache.scala:342:24, :933:{24,32}] assign _io_cpu_s2_xcpt_T_ae_ld = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_ae_ld; // @[DCache.scala:342:24, :933:{24,32}] assign _io_cpu_s2_xcpt_T_ae_st = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_ae_st; // @[DCache.scala:342:24, :933:{24,32}] wire _io_cpu_s2_xcpt_T_ae_inst = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_ae_inst; // @[DCache.scala:342:24, :933:{24,32}] assign _io_cpu_s2_xcpt_T_ma_ld = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_ma_ld; // @[DCache.scala:342:24, :933:{24,32}] assign _io_cpu_s2_xcpt_T_ma_st = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_ma_st; // @[DCache.scala:342:24, :933:{24,32}] wire _io_cpu_s2_xcpt_T_cacheable = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_cacheable; // @[DCache.scala:342:24, :933:{24,32}] wire _io_cpu_s2_xcpt_T_must_alloc = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_must_alloc; // @[DCache.scala:342:24, :933:{24,32}] wire _io_cpu_s2_xcpt_T_prefetchable = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_prefetchable; // @[DCache.scala:342:24, :933:{24,32}] wire [1:0] _io_cpu_s2_xcpt_T_size = io_cpu_s2_xcpt_REG ? s2_tlb_xcpt_size : 2'h0; // @[DCache.scala:342:24, :933:{24,32}] wire [4:0] _io_cpu_s2_xcpt_T_cmd = io_cpu_s2_xcpt_REG ? s2_tlb_xcpt_cmd : 5'h0; // @[DCache.scala:342:24, :933:{24,32}] assign io_cpu_s2_xcpt_pf_ld_0 = _io_cpu_s2_xcpt_T_pf_ld; // @[DCache.scala:101:7, :933:24] assign io_cpu_s2_xcpt_pf_st_0 = _io_cpu_s2_xcpt_T_pf_st; // @[DCache.scala:101:7, :933:24] assign io_cpu_s2_xcpt_ae_ld_0 = _io_cpu_s2_xcpt_T_ae_ld; // @[DCache.scala:101:7, :933:24] assign io_cpu_s2_xcpt_ae_st_0 = _io_cpu_s2_xcpt_T_ae_st; // @[DCache.scala:101:7, :933:24] assign io_cpu_s2_xcpt_ma_ld_0 = _io_cpu_s2_xcpt_T_ma_ld; // @[DCache.scala:101:7, :933:24] assign io_cpu_s2_xcpt_ma_st_0 = _io_cpu_s2_xcpt_T_ma_st; // @[DCache.scala:101:7, :933:24] reg [63:0] s2_uncached_data_word; // @[DCache.scala:947:40] reg doUncachedResp; // @[DCache.scala:948:31] assign io_cpu_resp_bits_replay_0 = doUncachedResp; // @[DCache.scala:101:7, :948:31] wire _io_cpu_resp_valid_T = s2_valid_hit_pre_data_ecc \| doUncachedResp; // @[DCache.scala:420:69, :948:31, :949:51] assign _io_cpu_resp_valid_T_2 = _io_cpu_resp_valid_T; // @[DCache.scala:949:{51,70}] assign io_cpu_resp_valid_0 = _io_cpu_resp_valid_T_2; // @[DCache.scala:101:7, :949:70] wire _io_cpu_replay_next_T_1 = _io_cpu_replay_next_T & grantIsUncachedData; // @[Decoupled.scala:51:35] assign _io_cpu_replay_next_T_3 = _io_cpu_replay_next_T_1; // @[DCache.scala:950:{39,62}] assign io_cpu_replay_next_0 = _io_cpu_replay_next_T_3; // @[DCache.scala:101:7, :950:62]
Generate the Verilog code corresponding to the following Chisel files. File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File Nodes.scala: package constellation.channel import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Parameters, Field} import freechips.rocketchip.diplomacy._ case class EmptyParams() case class ChannelEdgeParams(cp: ChannelParams, p: Parameters) object ChannelImp extends SimpleNodeImp[EmptyParams, ChannelParams, ChannelEdgeParams, Channel] { def edge(pd: EmptyParams, pu: ChannelParams, p: Parameters, sourceInfo: SourceInfo) = { ChannelEdgeParams(pu, p) } def bundle(e: ChannelEdgeParams) = new Channel(e.cp)(e.p) def render(e: ChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) { RenderedEdge(colour = "ffffff", label = "X") } else { RenderedEdge(colour = "#0000ff", label = e.cp.payloadBits.toString) } override def monitor(bundle: Channel, edge: ChannelEdgeParams): Unit = { val monitor = Module(new NoCMonitor(edge.cp)(edge.p)) monitor.io.in := bundle } // TODO: Add nodepath stuff? override def mixO, override def mixI } case class ChannelSourceNode(val destId: Int)(implicit valName: ValName) extends SourceNode(ChannelImp)(Seq(EmptyParams())) case class ChannelDestNode(val destParams: ChannelParams)(implicit valName: ValName) extends SinkNode(ChannelImp)(Seq(destParams)) case class ChannelAdapterNode( slaveFn: ChannelParams => ChannelParams = { d => d })( implicit valName: ValName) extends AdapterNode(ChannelImp)((e: EmptyParams) => e, slaveFn) case class ChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(ChannelImp)() case class ChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(ChannelImp)() case class IngressChannelEdgeParams(cp: IngressChannelParams, p: Parameters) case class EgressChannelEdgeParams(cp: EgressChannelParams, p: Parameters) object IngressChannelImp extends SimpleNodeImp[EmptyParams, IngressChannelParams, IngressChannelEdgeParams, IngressChannel] { def edge(pd: EmptyParams, pu: IngressChannelParams, p: Parameters, sourceInfo: SourceInfo) = { IngressChannelEdgeParams(pu, p) } def bundle(e: IngressChannelEdgeParams) = new IngressChannel(e.cp)(e.p) def render(e: IngressChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) { RenderedEdge(colour = "ffffff", label = "X") } else { RenderedEdge(colour = "#00ff00", label = e.cp.payloadBits.toString) } } object EgressChannelImp extends SimpleNodeImp[EmptyParams, EgressChannelParams, EgressChannelEdgeParams, EgressChannel] { def edge(pd: EmptyParams, pu: EgressChannelParams, p: Parameters, sourceInfo: SourceInfo) = { EgressChannelEdgeParams(pu, p) } def bundle(e: EgressChannelEdgeParams) = new EgressChannel(e.cp)(e.p) def render(e: EgressChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) { RenderedEdge(colour = "ffffff", label = "X") } else { RenderedEdge(colour = "#ff0000", label = e.cp.payloadBits.toString) } } case class IngressChannelSourceNode(val destId: Int)(implicit valName: ValName) extends SourceNode(IngressChannelImp)(Seq(EmptyParams())) case class IngressChannelDestNode(val destParams: IngressChannelParams)(implicit valName: ValName) extends SinkNode(IngressChannelImp)(Seq(destParams)) case class EgressChannelSourceNode(val egressId: Int)(implicit valName: ValName) extends SourceNode(EgressChannelImp)(Seq(EmptyParams())) case class EgressChannelDestNode(val destParams: EgressChannelParams)(implicit valName: ValName) extends SinkNode(EgressChannelImp)(Seq(destParams)) case class IngressChannelAdapterNode( slaveFn: IngressChannelParams => IngressChannelParams = { d => d })( implicit valName: ValName) extends AdapterNode(IngressChannelImp)(m => m, slaveFn) case class EgressChannelAdapterNode( slaveFn: EgressChannelParams => EgressChannelParams = { d => d })( implicit valName: ValName) extends AdapterNode(EgressChannelImp)(m => m, slaveFn) case class IngressChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(IngressChannelImp)() case class EgressChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(EgressChannelImp)() case class IngressChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(IngressChannelImp)() case class EgressChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(EgressChannelImp)() File Router.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{RoutingRelation} import constellation.noc.{HasNoCParams} case class UserRouterParams( // Payload width. Must match payload width on all channels attached to this routing node payloadBits: Int = 64, // Combines SA and ST stages (removes pipeline register) combineSAST: Boolean = false, // Combines RC and VA stages (removes pipeline register) combineRCVA: Boolean = false, // Adds combinational path from SA to VA coupleSAVA: Boolean = false, vcAllocator: VCAllocatorParams => Parameters => VCAllocator = (vP) => (p) => new RotatingSingleVCAllocator(vP)(p) ) case class RouterParams( nodeId: Int, nIngress: Int, nEgress: Int, user: UserRouterParams ) trait HasRouterOutputParams { def outParams: Seq[ChannelParams] def egressParams: Seq[EgressChannelParams] def allOutParams = outParams ++ egressParams def nOutputs = outParams.size def nEgress = egressParams.size def nAllOutputs = allOutParams.size } trait HasRouterInputParams { def inParams: Seq[ChannelParams] def ingressParams: Seq[IngressChannelParams] def allInParams = inParams ++ ingressParams def nInputs = inParams.size def nIngress = ingressParams.size def nAllInputs = allInParams.size } trait HasRouterParams { def routerParams: RouterParams def nodeId = routerParams.nodeId def payloadBits = routerParams.user.payloadBits } class DebugBundle(val nIn: Int) extends Bundle { val va_stall = Vec(nIn, UInt()) val sa_stall = Vec(nIn, UInt()) } class Router( val routerParams: RouterParams, preDiplomaticInParams: Seq[ChannelParams], preDiplomaticIngressParams: Seq[IngressChannelParams], outDests: Seq[Int], egressIds: Seq[Int] )(implicit p: Parameters) extends LazyModule with HasNoCParams with HasRouterParams { val allPreDiplomaticInParams = preDiplomaticInParams ++ preDiplomaticIngressParams val destNodes = preDiplomaticInParams.map(u => ChannelDestNode(u)) val sourceNodes = outDests.map(u => ChannelSourceNode(u)) val ingressNodes = preDiplomaticIngressParams.map(u => IngressChannelDestNode(u)) val egressNodes = egressIds.map(u => EgressChannelSourceNode(u)) val debugNode = BundleBridgeSource(() => new DebugBundle(allPreDiplomaticInParams.size)) val ctrlNode = if (hasCtrl) Some(BundleBridgeSource(() => new RouterCtrlBundle)) else None def inParams = module.inParams def outParams = module.outParams def ingressParams = module.ingressParams def egressParams = module.egressParams lazy val module = new LazyModuleImp(this) with HasRouterInputParams with HasRouterOutputParams { val (io_in, edgesIn) = destNodes.map(_.in(0)).unzip val (io_out, edgesOut) = sourceNodes.map(_.out(0)).unzip val (io_ingress, edgesIngress) = ingressNodes.map(_.in(0)).unzip val (io_egress, edgesEgress) = egressNodes.map(_.out(0)).unzip val io_debug = debugNode.out(0)._1 val inParams = edgesIn.map(_.cp) val outParams = edgesOut.map(_.cp) val ingressParams = edgesIngress.map(_.cp) val egressParams = edgesEgress.map(_.cp) allOutParams.foreach(u => require(u.srcId == nodeId && u.payloadBits == routerParams.user.payloadBits)) allInParams.foreach(u => require(u.destId == nodeId && u.payloadBits == routerParams.user.payloadBits)) require(nIngress == routerParams.nIngress) require(nEgress == routerParams.nEgress) require(nAllInputs >= 1) require(nAllOutputs >= 1) require(nodeId < (1 << nodeIdBits)) val input_units = inParams.zipWithIndex.map { case (u,i) => Module(new InputUnit(u, outParams, egressParams, routerParams.user.combineRCVA, routerParams.user.combineSAST)) .suggestName(s"input_unit_${i}_from_${u.srcId}") } val ingress_units = ingressParams.zipWithIndex.map { case (u,i) => Module(new IngressUnit(i, u, outParams, egressParams, routerParams.user.combineRCVA, routerParams.user.combineSAST)) .suggestName(s"ingress_unit_${i+nInputs}_from_${u.ingressId}") } val all_input_units = input_units ++ ingress_units val output_units = outParams.zipWithIndex.map { case (u,i) => Module(new OutputUnit(inParams, ingressParams, u)) .suggestName(s"output_unit_${i}_to_${u.destId}")} val egress_units = egressParams.zipWithIndex.map { case (u,i) => Module(new EgressUnit(routerParams.user.coupleSAVA && all_input_units.size == 1, routerParams.user.combineSAST, inParams, ingressParams, u)) .suggestName(s"egress_unit_${i+nOutputs}_to_${u.egressId}")} val all_output_units = output_units ++ egress_units val switch = Module(new Switch(routerParams, inParams, outParams, ingressParams, egressParams)) val switch_allocator = Module(new SwitchAllocator(routerParams, inParams, outParams, ingressParams, egressParams)) val vc_allocator = Module(routerParams.user.vcAllocator( VCAllocatorParams(routerParams, inParams, outParams, ingressParams, egressParams) )(p)) val route_computer = Module(new RouteComputer(routerParams, inParams, outParams, ingressParams, egressParams)) val fires_count = WireInit(PopCount(vc_allocator.io.req.map(_.fire))) dontTouch(fires_count) (io_in zip input_units ).foreach { case (i,u) => u.io.in <> i } (io_ingress zip ingress_units).foreach { case (i,u) => u.io.in <> i.flit } (output_units zip io_out ).foreach { case (u,o) => o <> u.io.out } (egress_units zip io_egress).foreach { case (u,o) => o.flit <> u.io.out } (route_computer.io.req zip all_input_units).foreach { case (i,u) => i <> u.io.router_req } (all_input_units zip route_computer.io.resp).foreach { case (u,o) => u.io.router_resp <> o } (vc_allocator.io.req zip all_input_units).foreach { case (i,u) => i <> u.io.vcalloc_req } (all_input_units zip vc_allocator.io.resp).foreach { case (u,o) => u.io.vcalloc_resp <> o } (all_output_units zip vc_allocator.io.out_allocs).foreach { case (u,a) => u.io.allocs <> a } (vc_allocator.io.channel_status zip all_output_units).foreach { case (a,u) => a := u.io.channel_status } all_input_units.foreach(in => all_output_units.zipWithIndex.foreach { case (out,outIdx) => in.io.out_credit_available(outIdx) := out.io.credit_available }) (all_input_units zip switch_allocator.io.req).foreach { case (u,r) => r <> u.io.salloc_req } (all_output_units zip switch_allocator.io.credit_alloc).foreach { case (u,a) => u.io.credit_alloc := a } (switch.io.in zip all_input_units).foreach { case (i,u) => i <> u.io.out } (all_output_units zip switch.io.out).foreach { case (u,o) => u.io.in <> o } switch.io.sel := (if (routerParams.user.combineSAST) { switch_allocator.io.switch_sel } else { RegNext(switch_allocator.io.switch_sel) }) if (hasCtrl) { val io_ctrl = ctrlNode.get.out(0)._1 val ctrl = Module(new RouterControlUnit(routerParams, inParams, outParams, ingressParams, egressParams)) io_ctrl <> ctrl.io.ctrl (all_input_units zip ctrl.io.in_block ).foreach { case (l,r) => l.io.block := r } (all_input_units zip ctrl.io.in_fire ).foreach { case (l,r) => r := l.io.out.map(_.valid) } } else { input_units.foreach(_.io.block := false.B) ingress_units.foreach(_.io.block := false.B) } (io_debug.va_stall zip all_input_units.map(_.io.debug.va_stall)).map { case (l,r) => l := r } (io_debug.sa_stall zip all_input_units.map(_.io.debug.sa_stall)).map { case (l,r) => l := r } val debug_tsc = RegInit(0.U(64.W)) debug_tsc := debug_tsc + 1.U val debug_sample = RegInit(0.U(64.W)) debug_sample := debug_sample + 1.U val sample_rate = PlusArg("noc_util_sample_rate", width=20) when (debug_sample === sample_rate - 1.U) { debug_sample := 0.U } def sample(fire: Bool, s: String) = { val util_ctr = RegInit(0.U(64.W)) val fired = RegInit(false.B) util_ctr := util_ctr + fire fired := fired \|\| fire when (sample_rate =/= 0.U && debug_sample === sample_rate - 1.U && fired) { val fmtStr = s"nocsample %d $s %d\n" printf(fmtStr, debug_tsc, util_ctr); fired := fire } } destNodes.map(_.in(0)).foreach { case (in, edge) => in.flit.map { f => sample(f.fire, s"${edge.cp.srcId} $nodeId") } } ingressNodes.map(_.in(0)).foreach { case (in, edge) => sample(in.flit.fire, s"i${edge.cp.asInstanceOf[IngressChannelParams].ingressId} $nodeId") } egressNodes.map(_.out(0)).foreach { case (out, edge) => sample(out.flit.fire, s"$nodeId e${edge.cp.asInstanceOf[EgressChannelParams].egressId}") } } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } }	module Router_24( // @[Router.scala:89:25] input clock, // @[Router.scala:89:25] input reset, // @[Router.scala:89:25] output [4:0] auto_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25] output [4:0] auto_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25] output [4:0] auto_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25] output [4:0] auto_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_source_nodes_out_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [5:0] auto_source_nodes_out_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [5:0] auto_source_nodes_out_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [21:0] auto_source_nodes_out_1_credit_return, // @[LazyModuleImp.scala:107:25] input [21:0] auto_source_nodes_out_1_vc_free, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_source_nodes_out_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [5:0] auto_source_nodes_out_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [5:0] auto_source_nodes_out_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [21:0] auto_source_nodes_out_0_credit_return, // @[LazyModuleImp.scala:107:25] input [21:0] auto_source_nodes_out_0_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_dest_nodes_in_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [5:0] auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [5:0] auto_dest_nodes_in_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [21:0] auto_dest_nodes_in_1_credit_return, // @[LazyModuleImp.scala:107:25] output [21:0] auto_dest_nodes_in_1_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_dest_nodes_in_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [5:0] auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [5:0] auto_dest_nodes_in_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [21:0] auto_dest_nodes_in_0_credit_return, // @[LazyModuleImp.scala:107:25] output [21:0] auto_dest_nodes_in_0_vc_free // @[LazyModuleImp.scala:107:25] ); wire [19:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire _route_computer_io_resp_1_vc_sel_1_2; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_1_3; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_1_8; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_1_9; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_1_10; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_1_11; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_1_12; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_1_13; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_1_14; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_1_15; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_1_16; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_1_17; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_1_18; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_1_19; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_1_20; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_8; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_9; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_12; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_13; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_20; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_21; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_3; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_19; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_20; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_21; // @[Router.scala:136:32] wire _vc_allocator_io_req_1_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_0_ready; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_1_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_1_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_1_8; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_1_9; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_1_10; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_1_11; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_1_12; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_1_13; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_1_14; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_1_15; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_1_16; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_1_17; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_1_18; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_1_19; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_1_20; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_8; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_9; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_12; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_13; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_20; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_21; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_19; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_20; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_21; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_2_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_3_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_8_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_9_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_10_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_11_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_12_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_13_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_14_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_15_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_16_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_17_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_18_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_19_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_20_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_21_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_8_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_9_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_12_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_13_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_20_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_21_alloc; // @[Router.scala:133:30] wire _switch_allocator_io_req_1_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_0_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_2_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_3_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_8_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_9_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_10_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_11_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_12_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_13_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_14_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_15_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_16_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_17_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_18_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_19_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_20_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_21_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_8_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_9_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_12_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_13_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_20_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_21_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_0_0; // @[Router.scala:132:34] wire _switch_io_out_1_0_valid; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_1_0_bits_payload; // @[Router.scala:131:24] wire [3:0] _switch_io_out_1_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [5:0] _switch_io_out_1_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [2:0] _switch_io_out_1_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [5:0] _switch_io_out_1_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [2:0] _switch_io_out_1_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_1_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _switch_io_out_0_0_valid; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_0_0_bits_payload; // @[Router.scala:131:24] wire [3:0] _switch_io_out_0_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [5:0] _switch_io_out_0_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [2:0] _switch_io_out_0_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [5:0] _switch_io_out_0_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [2:0] _switch_io_out_0_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_0_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _output_unit_1_to_20_io_credit_available_2; // @[Router.scala:122:13] wire _output_unit_1_to_20_io_credit_available_3; // @[Router.scala:122:13] wire _output_unit_1_to_20_io_credit_available_8; // @[Router.scala:122:13] wire _output_unit_1_to_20_io_credit_available_9; // @[Router.scala:122:13] wire _output_unit_1_to_20_io_credit_available_10; // @[Router.scala:122:13] wire _output_unit_1_to_20_io_credit_available_11; // @[Router.scala:122:13] wire _output_unit_1_to_20_io_credit_available_12; // @[Router.scala:122:13] wire _output_unit_1_to_20_io_credit_available_13; // @[Router.scala:122:13] wire _output_unit_1_to_20_io_credit_available_14; // @[Router.scala:122:13] wire _output_unit_1_to_20_io_credit_available_15; // @[Router.scala:122:13] wire _output_unit_1_to_20_io_credit_available_16; // @[Router.scala:122:13] wire _output_unit_1_to_20_io_credit_available_17; // @[Router.scala:122:13] wire _output_unit_1_to_20_io_credit_available_18; // @[Router.scala:122:13] wire _output_unit_1_to_20_io_credit_available_19; // @[Router.scala:122:13] wire _output_unit_1_to_20_io_credit_available_20; // @[Router.scala:122:13] wire _output_unit_1_to_20_io_credit_available_21; // @[Router.scala:122:13] wire _output_unit_1_to_20_io_channel_status_2_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_20_io_channel_status_3_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_20_io_channel_status_8_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_20_io_channel_status_9_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_20_io_channel_status_10_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_20_io_channel_status_11_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_20_io_channel_status_12_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_20_io_channel_status_13_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_20_io_channel_status_14_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_20_io_channel_status_15_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_20_io_channel_status_16_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_20_io_channel_status_17_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_20_io_channel_status_18_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_20_io_channel_status_19_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_20_io_channel_status_20_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_20_io_channel_status_21_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_9_io_credit_available_8; // @[Router.scala:122:13] wire _output_unit_0_to_9_io_credit_available_9; // @[Router.scala:122:13] wire _output_unit_0_to_9_io_credit_available_12; // @[Router.scala:122:13] wire _output_unit_0_to_9_io_credit_available_13; // @[Router.scala:122:13] wire _output_unit_0_to_9_io_credit_available_20; // @[Router.scala:122:13] wire _output_unit_0_to_9_io_credit_available_21; // @[Router.scala:122:13] wire _output_unit_0_to_9_io_channel_status_8_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_9_io_channel_status_9_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_9_io_channel_status_12_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_9_io_channel_status_13_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_9_io_channel_status_20_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_9_io_channel_status_21_occupied; // @[Router.scala:122:13] wire [4:0] _input_unit_1_from_28_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire [3:0] _input_unit_1_from_28_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [5:0] _input_unit_1_from_28_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_28_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [5:0] _input_unit_1_from_28_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_28_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_vcalloc_req_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_vcalloc_req_bits_vc_sel_1_3; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_vcalloc_req_bits_vc_sel_1_8; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_vcalloc_req_bits_vc_sel_1_9; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_vcalloc_req_bits_vc_sel_1_10; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_vcalloc_req_bits_vc_sel_1_11; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_vcalloc_req_bits_vc_sel_1_12; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_vcalloc_req_bits_vc_sel_1_13; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_vcalloc_req_bits_vc_sel_1_14; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_vcalloc_req_bits_vc_sel_1_15; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_vcalloc_req_bits_vc_sel_1_16; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_vcalloc_req_bits_vc_sel_1_17; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_vcalloc_req_bits_vc_sel_1_18; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_vcalloc_req_bits_vc_sel_1_19; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_vcalloc_req_bits_vc_sel_1_20; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_vcalloc_req_bits_vc_sel_0_8; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_vcalloc_req_bits_vc_sel_0_9; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_vcalloc_req_bits_vc_sel_0_12; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_vcalloc_req_bits_vc_sel_0_13; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_vcalloc_req_bits_vc_sel_0_20; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_vcalloc_req_bits_vc_sel_0_21; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_salloc_req_0_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_salloc_req_0_bits_vc_sel_1_3; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_salloc_req_0_bits_vc_sel_1_8; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_salloc_req_0_bits_vc_sel_1_9; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_salloc_req_0_bits_vc_sel_1_10; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_salloc_req_0_bits_vc_sel_1_11; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_salloc_req_0_bits_vc_sel_1_12; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_salloc_req_0_bits_vc_sel_1_13; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_salloc_req_0_bits_vc_sel_1_14; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_salloc_req_0_bits_vc_sel_1_15; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_salloc_req_0_bits_vc_sel_1_16; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_salloc_req_0_bits_vc_sel_1_17; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_salloc_req_0_bits_vc_sel_1_18; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_salloc_req_0_bits_vc_sel_1_19; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_salloc_req_0_bits_vc_sel_1_20; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_salloc_req_0_bits_vc_sel_1_21; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_salloc_req_0_bits_vc_sel_0_8; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_salloc_req_0_bits_vc_sel_0_9; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_salloc_req_0_bits_vc_sel_0_10; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_salloc_req_0_bits_vc_sel_0_11; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_salloc_req_0_bits_vc_sel_0_12; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_salloc_req_0_bits_vc_sel_0_13; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_salloc_req_0_bits_vc_sel_0_14; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_salloc_req_0_bits_vc_sel_0_15; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_salloc_req_0_bits_vc_sel_0_16; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_salloc_req_0_bits_vc_sel_0_17; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_salloc_req_0_bits_vc_sel_0_18; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_salloc_req_0_bits_vc_sel_0_19; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_salloc_req_0_bits_vc_sel_0_20; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_salloc_req_0_bits_vc_sel_0_21; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [72:0] _input_unit_1_from_28_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [3:0] _input_unit_1_from_28_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [5:0] _input_unit_1_from_28_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_28_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [5:0] _input_unit_1_from_28_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_28_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_1_from_28_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [4:0] _input_unit_0_from_9_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_9_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [5:0] _input_unit_0_from_9_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_9_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [5:0] _input_unit_0_from_9_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_9_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_vcalloc_req_bits_vc_sel_1_3; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_vcalloc_req_bits_vc_sel_1_19; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_vcalloc_req_bits_vc_sel_1_20; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_vcalloc_req_bits_vc_sel_1_21; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_salloc_req_0_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_salloc_req_0_bits_vc_sel_1_3; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_salloc_req_0_bits_vc_sel_1_8; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_salloc_req_0_bits_vc_sel_1_9; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_salloc_req_0_bits_vc_sel_1_10; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_salloc_req_0_bits_vc_sel_1_11; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_salloc_req_0_bits_vc_sel_1_12; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_salloc_req_0_bits_vc_sel_1_13; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_salloc_req_0_bits_vc_sel_1_14; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_salloc_req_0_bits_vc_sel_1_15; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_salloc_req_0_bits_vc_sel_1_16; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_salloc_req_0_bits_vc_sel_1_17; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_salloc_req_0_bits_vc_sel_1_18; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_salloc_req_0_bits_vc_sel_1_19; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_salloc_req_0_bits_vc_sel_1_20; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_salloc_req_0_bits_vc_sel_1_21; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_salloc_req_0_bits_vc_sel_0_8; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_salloc_req_0_bits_vc_sel_0_9; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_salloc_req_0_bits_vc_sel_0_10; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_salloc_req_0_bits_vc_sel_0_11; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_salloc_req_0_bits_vc_sel_0_12; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_salloc_req_0_bits_vc_sel_0_13; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_salloc_req_0_bits_vc_sel_0_14; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_salloc_req_0_bits_vc_sel_0_15; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_salloc_req_0_bits_vc_sel_0_16; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_salloc_req_0_bits_vc_sel_0_17; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_salloc_req_0_bits_vc_sel_0_18; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_salloc_req_0_bits_vc_sel_0_19; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_salloc_req_0_bits_vc_sel_0_20; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_salloc_req_0_bits_vc_sel_0_21; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [72:0] _input_unit_0_from_9_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_9_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [5:0] _input_unit_0_from_9_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_9_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [5:0] _input_unit_0_from_9_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_9_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_0_from_9_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [1:0] fires_count = {1'h0, _vc_allocator_io_req_0_ready & _input_unit_0_from_9_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_1_ready & _input_unit_1_from_28_io_vcalloc_req_valid}; // @[Decoupled.scala:51:35] reg REG_1_0_1_0; // @[Router.scala:178:14] reg REG_1_0_0_0; // @[Router.scala:178:14] reg REG_0_0_1_0; // @[Router.scala:178:14] reg REG_0_0_0_0; // @[Router.scala:178:14] reg [63:0] debug_tsc; // @[Router.scala:195:28] reg [63:0] debug_sample; // @[Router.scala:197:31] wire _GEN = debug_sample == {44'h0, _plusarg_reader_out - 20'h1}; // @[PlusArg.scala:80:11] reg [63:0] util_ctr; // @[Router.scala:203:29] reg fired; // @[Router.scala:204:26] wire _GEN_0 = (\|_plusarg_reader_out) & _GEN; // @[PlusArg.scala:80:11] wire _GEN_1 = _GEN_0 & fired; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_1; // @[Router.scala:203:29] reg fired_1; // @[Router.scala:204:26] wire _GEN_2 = _GEN_0 & fired_1; // @[Router.scala:204:26, :207:{33,71}]
Generate the Verilog code corresponding to the following Chisel files. File decode.scala: //**************************************************************************** // Copyright (c) 2015 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ package boom.v3.exu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket.Instructions32 import freechips.rocketchip.rocket.CustomInstructions._ import freechips.rocketchip.rocket.RVCExpander import freechips.rocketchip.rocket.{CSR,Causes} import freechips.rocketchip.util.{uintToBitPat,UIntIsOneOf} import FUConstants._ import boom.v3.common._ import boom.v3.util._ // scalastyle:off / * Abstract trait giving defaults and other relevant values to different Decode constants/ / abstract trait DecodeConstants extends freechips.rocketchip.rocket.constants.ScalarOpConstants with freechips.rocketchip.rocket.constants.MemoryOpConstants { val xpr64 = Y // TODO inform this from xLen val DC2 = BitPat.dontCare(2) // Makes the listing below more readable def decode_default: List[BitPat] = // frs3_en wakeup_delay // is val inst? \| imm sel \| bypassable (aka, known/fixed latency) // \| is fp inst? \| \| uses_ldq \| \| is_br // \| \| is single-prec? rs1 regtype \| \| \| uses_stq \| \| \| // \| \| \| micro-code \| rs2 type\| \| \| \| is_amo \| \| \| // \| \| \| \| iq-type func unit \| \| \| \| \| \| \| is_fence \| \| \| // \| \| \| \| \| \| \| \| \| \| \| \| \| \| is_fencei \| \| \| is breakpoint or ecall? // \| \| \| \| \| \| dst \| \| \| \| \| \| \| \| \| mem \| \| \| \| is unique? (clear pipeline for it) // \| \| \| \| \| \| regtype \| \| \| \| \| \| \| \| \| cmd \| \| \| \| \| flush on commit // \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| csr cmd // \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| List(N, N, X, uopX , IQT_INT, FU_X , RT_X , DC2 ,DC2 ,X, IS_X, X, X, X, X, N, M_X, DC2, X, X, N, N, X, CSR.X) val table: Array[(BitPat, List[BitPat])] } // scalastyle:on /* * Decoded control signals / class CtrlSigs extends Bundle { val legal = Bool() val fp_val = Bool() val fp_single = Bool() val uopc = UInt(UOPC_SZ.W) val iq_type = UInt(IQT_SZ.W) val fu_code = UInt(FUC_SZ.W) val dst_type = UInt(2.W) val rs1_type = UInt(2.W) val rs2_type = UInt(2.W) val frs3_en = Bool() val imm_sel = UInt(IS_X.getWidth.W) val uses_ldq = Bool() val uses_stq = Bool() val is_amo = Bool() val is_fence = Bool() val is_fencei = Bool() val mem_cmd = UInt(freechips.rocketchip.rocket.M_SZ.W) val wakeup_delay = UInt(2.W) val bypassable = Bool() val is_br = Bool() val is_sys_pc2epc = Bool() val inst_unique = Bool() val flush_on_commit = Bool() val csr_cmd = UInt(freechips.rocketchip.rocket.CSR.SZ.W) val rocc = Bool() def decode(inst: UInt, table: Iterable[(BitPat, List[BitPat])]) = { val decoder = freechips.rocketchip.rocket.DecodeLogic(inst, XDecode.decode_default, table) val sigs = Seq(legal, fp_val, fp_single, uopc, iq_type, fu_code, dst_type, rs1_type, rs2_type, frs3_en, imm_sel, uses_ldq, uses_stq, is_amo, is_fence, is_fencei, mem_cmd, wakeup_delay, bypassable, is_br, is_sys_pc2epc, inst_unique, flush_on_commit, csr_cmd) sigs zip decoder map {case(s,d) => s := d} rocc := false.B this } } // scalastyle:off /* * Decode constants for RV32 / object X32Decode extends DecodeConstants { // frs3_en wakeup_delay // is val inst? \| imm sel \| bypassable (aka, known/fixed latency) // \| is fp inst? \| \| uses_ldq \| \| is_br // \| \| is single-prec? rs1 regtype \| \| \| uses_stq \| \| \| // \| \| \| micro-code \| rs2 type\| \| \| \| is_amo \| \| \| // \| \| \| \| iq-type func unit \| \| \| \| \| \| \| is_fence \| \| \| // \| \| \| \| \| \| \| \| \| \| \| \| \| \| is_fencei \| \| \| is breakpoint or ecall? // \| \| \| \| \| \| dst \| \| \| \| \| \| \| \| \| mem \| \| \| \| is unique? (clear pipeline for it) // \| \| \| \| \| \| regtype \| \| \| \| \| \| \| \| \| cmd \| \| \| \| \| flush on commit // \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| csr cmd val table: Array[(BitPat, List[BitPat])] = Array(// \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| Instructions32.SLLI -> List(Y, N, X, uopSLLI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), Instructions32.SRLI -> List(Y, N, X, uopSRLI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), Instructions32.SRAI -> List(Y, N, X, uopSRAI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N) ) } /* * Decode constants for RV64 / object X64Decode extends DecodeConstants { // frs3_en wakeup_delay // is val inst? \| imm sel \| bypassable (aka, known/fixed latency) // \| is fp inst? \| \| uses_ldq \| \| is_br // \| \| is single-prec? rs1 regtype \| \| \| uses_stq \| \| \| // \| \| \| micro-code \| rs2 type\| \| \| \| is_amo \| \| \| // \| \| \| \| iq-type func unit \| \| \| \| \| \| \| is_fence \| \| \| // \| \| \| \| \| \| \| \| \| \| \| \| \| \| is_fencei \| \| \| is breakpoint or ecall? // \| \| \| \| \| \| dst \| \| \| \| \| \| \| \| \| mem \| \| \| \| is unique? (clear pipeline for it) // \| \| \| \| \| \| regtype \| \| \| \| \| \| \| \| \| cmd \| \| \| \| \| flush on commit // \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| csr cmd val table: Array[(BitPat, List[BitPat])] = Array(// \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| LD -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM , RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 3.U, N, N, N, N, N, CSR.N), LWU -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM , RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 3.U, N, N, N, N, N, CSR.N), SD -> List(Y, N, X, uopSTA , IQT_MEM, FU_MEM , RT_X , RT_FIX, RT_FIX, N, IS_S, N, Y, N, N, N, M_XWR, 0.U, N, N, N, N, N, CSR.N), SLLI -> List(Y, N, X, uopSLLI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), SRLI -> List(Y, N, X, uopSRLI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), SRAI -> List(Y, N, X, uopSRAI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), ADDIW -> List(Y, N, X, uopADDIW, IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), SLLIW -> List(Y, N, X, uopSLLIW, IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), SRAIW -> List(Y, N, X, uopSRAIW, IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), SRLIW -> List(Y, N, X, uopSRLIW, IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), ADDW -> List(Y, N, X, uopADDW , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), SUBW -> List(Y, N, X, uopSUBW , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), SLLW -> List(Y, N, X, uopSLLW , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), SRAW -> List(Y, N, X, uopSRAW , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), SRLW -> List(Y, N, X, uopSRLW , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N) ) } /* * Overall Decode constants / object XDecode extends DecodeConstants { // frs3_en wakeup_delay // is val inst? \| imm sel \| bypassable (aka, known/fixed latency) // \| is fp inst? \| \| uses_ldq \| \| is_br // \| \| is single-prec? rs1 regtype \| \| \| uses_stq \| \| \| // \| \| \| micro-code \| rs2 type\| \| \| \| is_amo \| \| \| // \| \| \| \| iq-type func unit \| \| \| \| \| \| \| is_fence \| \| \| // \| \| \| \| \| \| \| \| \| \| \| \| \| \| is_fencei \| \| \| is breakpoint or ecall? // \| \| \| \| \| \| dst \| \| \| \| \| \| \| \| \| mem \| \| \| \| is unique? (clear pipeline for it) // \| \| \| \| \| \| regtype \| \| \| \| \| \| \| \| \| cmd \| \| \| \| \| flush on commit // \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| csr cmd val table: Array[(BitPat, List[BitPat])] = Array(// \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| LW -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM , RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 3.U, N, N, N, N, N, CSR.N), LH -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM , RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 3.U, N, N, N, N, N, CSR.N), LHU -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM , RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 3.U, N, N, N, N, N, CSR.N), LB -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM , RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 3.U, N, N, N, N, N, CSR.N), LBU -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM , RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 3.U, N, N, N, N, N, CSR.N), SW -> List(Y, N, X, uopSTA , IQT_MEM, FU_MEM , RT_X , RT_FIX, RT_FIX, N, IS_S, N, Y, N, N, N, M_XWR, 0.U, N, N, N, N, N, CSR.N), SH -> List(Y, N, X, uopSTA , IQT_MEM, FU_MEM , RT_X , RT_FIX, RT_FIX, N, IS_S, N, Y, N, N, N, M_XWR, 0.U, N, N, N, N, N, CSR.N), SB -> List(Y, N, X, uopSTA , IQT_MEM, FU_MEM , RT_X , RT_FIX, RT_FIX, N, IS_S, N, Y, N, N, N, M_XWR, 0.U, N, N, N, N, N, CSR.N), LUI -> List(Y, N, X, uopLUI , IQT_INT, FU_ALU , RT_FIX, RT_X , RT_X , N, IS_U, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), ADDI -> List(Y, N, X, uopADDI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), ANDI -> List(Y, N, X, uopANDI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), ORI -> List(Y, N, X, uopORI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), XORI -> List(Y, N, X, uopXORI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), SLTI -> List(Y, N, X, uopSLTI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), SLTIU -> List(Y, N, X, uopSLTIU, IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), SLL -> List(Y, N, X, uopSLL , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), ADD -> List(Y, N, X, uopADD , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), SUB -> List(Y, N, X, uopSUB , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), SLT -> List(Y, N, X, uopSLT , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), SLTU -> List(Y, N, X, uopSLTU , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), AND -> List(Y, N, X, uopAND , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), OR -> List(Y, N, X, uopOR , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), XOR -> List(Y, N, X, uopXOR , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), SRA -> List(Y, N, X, uopSRA , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), SRL -> List(Y, N, X, uopSRL , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), MUL -> List(Y, N, X, uopMUL , IQT_INT, FU_MUL , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), MULH -> List(Y, N, X, uopMULH , IQT_INT, FU_MUL , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), MULHU -> List(Y, N, X, uopMULHU, IQT_INT, FU_MUL , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), MULHSU -> List(Y, N, X, uopMULHSU,IQT_INT, FU_MUL , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), MULW -> List(Y, N, X, uopMULW , IQT_INT, FU_MUL , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), DIV -> List(Y, N, X, uopDIV , IQT_INT, FU_DIV , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), DIVU -> List(Y, N, X, uopDIVU , IQT_INT, FU_DIV , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), REM -> List(Y, N, X, uopREM , IQT_INT, FU_DIV , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), REMU -> List(Y, N, X, uopREMU , IQT_INT, FU_DIV , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), DIVW -> List(Y, N, X, uopDIVW , IQT_INT, FU_DIV , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), DIVUW -> List(Y, N, X, uopDIVUW, IQT_INT, FU_DIV , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), REMW -> List(Y, N, X, uopREMW , IQT_INT, FU_DIV , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), REMUW -> List(Y, N, X, uopREMUW, IQT_INT, FU_DIV , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), AUIPC -> List(Y, N, X, uopAUIPC, IQT_INT, FU_JMP , RT_FIX, RT_X , RT_X , N, IS_U, N, N, N, N, N, M_X , 1.U, N, N, N, N, N, CSR.N), // use BRU for the PC read JAL -> List(Y, N, X, uopJAL , IQT_INT, FU_JMP , RT_FIX, RT_X , RT_X , N, IS_J, N, N, N, N, N, M_X , 1.U, N, N, N, N, N, CSR.N), JALR -> List(Y, N, X, uopJALR , IQT_INT, FU_JMP , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, N, N, N, N, N, CSR.N), BEQ -> List(Y, N, X, uopBEQ , IQT_INT, FU_ALU , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, N, N, M_X , 0.U, N, Y, N, N, N, CSR.N), BNE -> List(Y, N, X, uopBNE , IQT_INT, FU_ALU , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, N, N, M_X , 0.U, N, Y, N, N, N, CSR.N), BGE -> List(Y, N, X, uopBGE , IQT_INT, FU_ALU , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, N, N, M_X , 0.U, N, Y, N, N, N, CSR.N), BGEU -> List(Y, N, X, uopBGEU , IQT_INT, FU_ALU , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, N, N, M_X , 0.U, N, Y, N, N, N, CSR.N), BLT -> List(Y, N, X, uopBLT , IQT_INT, FU_ALU , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, N, N, M_X , 0.U, N, Y, N, N, N, CSR.N), BLTU -> List(Y, N, X, uopBLTU , IQT_INT, FU_ALU , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, N, N, M_X , 0.U, N, Y, N, N, N, CSR.N), // I-type, the immediate12 holds the CSR register. CSRRW -> List(Y, N, X, uopCSRRW, IQT_INT, FU_CSR , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.W), CSRRS -> List(Y, N, X, uopCSRRS, IQT_INT, FU_CSR , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.S), CSRRC -> List(Y, N, X, uopCSRRC, IQT_INT, FU_CSR , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.C), CSRRWI -> List(Y, N, X, uopCSRRWI,IQT_INT, FU_CSR , RT_FIX, RT_PAS, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.W), CSRRSI -> List(Y, N, X, uopCSRRSI,IQT_INT, FU_CSR , RT_FIX, RT_PAS, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.S), CSRRCI -> List(Y, N, X, uopCSRRCI,IQT_INT, FU_CSR , RT_FIX, RT_PAS, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.C), SFENCE_VMA->List(Y,N, X, uopSFENCE,IQT_MEM, FU_MEM , RT_X , RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N,M_SFENCE,0.U,N, N, N, Y, Y, CSR.N), ECALL -> List(Y, N, X, uopERET ,IQT_INT, FU_CSR , RT_X , RT_X , RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, Y, Y, Y, CSR.I), EBREAK -> List(Y, N, X, uopERET ,IQT_INT, FU_CSR , RT_X , RT_X , RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, Y, Y, Y, CSR.I), SRET -> List(Y, N, X, uopERET ,IQT_INT, FU_CSR , RT_X , RT_X , RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.I), MRET -> List(Y, N, X, uopERET ,IQT_INT, FU_CSR , RT_X , RT_X , RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.I), DRET -> List(Y, N, X, uopERET ,IQT_INT, FU_CSR , RT_X , RT_X , RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.I), WFI -> List(Y, N, X, uopWFI ,IQT_INT, FU_CSR , RT_X , RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.I), FENCE_I -> List(Y, N, X, uopNOP , IQT_INT, FU_X , RT_X , RT_X , RT_X , N, IS_X, N, N, N, N, Y, M_X , 0.U, N, N, N, Y, Y, CSR.N), FENCE -> List(Y, N, X, uopFENCE, IQT_INT, FU_MEM , RT_X , RT_X , RT_X , N, IS_X, N, Y, N, Y, N, M_X , 0.U, N, N, N, Y, Y, CSR.N), // TODO PERF make fence higher performance // currently serializes pipeline // frs3_en wakeup_delay // is val inst? \| imm sel \| bypassable (aka, known/fixed latency) // \| is fp inst? \| \| uses_ldq \| \| is_br // \| \| is single-prec? rs1 regtype \| \| \| uses_stq \| \| \| // \| \| \| micro-code \| rs2 type\| \| \| \| is_amo \| \| \| // \| \| \| \| iq-type func unit \| \| \| \| \| \| \| is_fence \| \| \| // \| \| \| \| \| \| \| \| \| \| \| \| \| \| is_fencei \| \| \| is breakpoint or ecall? // \| \| \| \| \| \| dst \| \| \| \| \| \| \| \| \| mem \| \| \| \| is unique? (clear pipeline for it) // \| \| \| \| \| \| regtype \| \| \| \| \| \| \| \| \| cmd \| \| \| \| \| flush on commit // \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| csr cmd // A-type \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| AMOADD_W-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_ADD, 0.U,N, N, N, Y, Y, CSR.N), // TODO make AMOs higherperformance AMOXOR_W-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_XOR, 0.U,N, N, N, Y, Y, CSR.N), AMOSWAP_W->List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_SWAP,0.U,N, N, N, Y, Y, CSR.N), AMOAND_W-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_AND, 0.U,N, N, N, Y, Y, CSR.N), AMOOR_W -> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_OR, 0.U,N, N, N, Y, Y, CSR.N), AMOMIN_W-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_MIN, 0.U,N, N, N, Y, Y, CSR.N), AMOMINU_W->List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_MINU,0.U,N, N, N, Y, Y, CSR.N), AMOMAX_W-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_MAX, 0.U,N, N, N, Y, Y, CSR.N), AMOMAXU_W->List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_MAXU,0.U,N, N, N, Y, Y, CSR.N), AMOADD_D-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_ADD, 0.U,N, N, N, Y, Y, CSR.N), AMOXOR_D-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_XOR, 0.U,N, N, N, Y, Y, CSR.N), AMOSWAP_D->List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_SWAP,0.U,N, N, N, Y, Y, CSR.N), AMOAND_D-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_AND, 0.U,N, N, N, Y, Y, CSR.N), AMOOR_D -> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_OR, 0.U,N, N, N, Y, Y, CSR.N), AMOMIN_D-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_MIN, 0.U,N, N, N, Y, Y, CSR.N), AMOMINU_D->List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_MINU,0.U,N, N, N, Y, Y, CSR.N), AMOMAX_D-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_MAX, 0.U,N, N, N, Y, Y, CSR.N), AMOMAXU_D->List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_MAXU,0.U,N, N, N, Y, Y, CSR.N), LR_W -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_X , N, IS_X, Y, N, N, N, N, M_XLR , 0.U,N, N, N, Y, Y, CSR.N), LR_D -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_X , N, IS_X, Y, N, N, N, N, M_XLR , 0.U,N, N, N, Y, Y, CSR.N), SC_W -> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XSC , 0.U,N, N, N, Y, Y, CSR.N), SC_D -> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XSC , 0.U,N, N, N, Y, Y, CSR.N) ) } /* * FP Decode constants / object FDecode extends DecodeConstants { val table: Array[(BitPat, List[BitPat])] = Array( // frs3_en wakeup_delay // \| imm sel \| bypassable (aka, known/fixed latency) // \| \| uses_ldq \| \| is_br // is val inst? rs1 regtype \| \| \| uses_stq \| \| \| // \| is fp inst? \| rs2 type\| \| \| \| is_amo \| \| \| // \| \| is dst single-prec? \| \| \| \| \| \| \| is_fence \| \| \| // \| \| \| micro-opcode \| \| \| \| \| \| \| \| is_fencei \| \| \| is breakpoint or ecall // \| \| \| \| iq_type func dst \| \| \| \| \| \| \| \| \| mem \| \| \| \| is unique? (clear pipeline for it) // \| \| \| \| \| unit regtype \| \| \| \| \| \| \| \| \| cmd \| \| \| \| \| flush on commit // \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| csr cmd FLW -> List(Y, Y, Y, uopLD , IQT_MEM, FU_MEM, RT_FLT, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 0.U, N, N, N, N, N, CSR.N), FLD -> List(Y, Y, N, uopLD , IQT_MEM, FU_MEM, RT_FLT, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 0.U, N, N, N, N, N, CSR.N), FSW -> List(Y, Y, Y, uopSTA , IQT_MFP,FU_F2IMEM,RT_X , RT_FIX, RT_FLT, N, IS_S, N, Y, N, N, N, M_XWR, 0.U, N, N, N, N, N, CSR.N), // sort of a lie; broken into two micro-ops FSD -> List(Y, Y, N, uopSTA , IQT_MFP,FU_F2IMEM,RT_X , RT_FIX, RT_FLT, N, IS_S, N, Y, N, N, N, M_XWR, 0.U, N, N, N, N, N, CSR.N), FCLASS_S-> List(Y, Y, Y, uopFCLASS_S,IQT_FP , FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FCLASS_D-> List(Y, Y, N, uopFCLASS_D,IQT_FP , FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FMV_W_X -> List(Y, Y, Y, uopFMV_W_X, IQT_INT, FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FMV_D_X -> List(Y, Y, N, uopFMV_D_X, IQT_INT, FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FMV_X_W -> List(Y, Y, Y, uopFMV_X_W, IQT_FP , FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FMV_X_D -> List(Y, Y, N, uopFMV_X_D, IQT_FP , FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FSGNJ_S -> List(Y, Y, Y, uopFSGNJ_S, IQT_FP , FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FSGNJ_D -> List(Y, Y, N, uopFSGNJ_D, IQT_FP , FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FSGNJX_S-> List(Y, Y, Y, uopFSGNJ_S, IQT_FP , FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FSGNJX_D-> List(Y, Y, N, uopFSGNJ_D, IQT_FP , FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FSGNJN_S-> List(Y, Y, Y, uopFSGNJ_S, IQT_FP , FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FSGNJN_D-> List(Y, Y, N, uopFSGNJ_D, IQT_FP , FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), // FP to FP FCVT_S_D-> List(Y, Y, Y, uopFCVT_S_D,IQT_FP , FU_FPU, RT_FLT, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FCVT_D_S-> List(Y, Y, N, uopFCVT_D_S,IQT_FP , FU_FPU, RT_FLT, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), // Int to FP FCVT_S_W-> List(Y, Y, Y, uopFCVT_S_X, IQT_INT,FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FCVT_S_WU->List(Y, Y, Y, uopFCVT_S_X, IQT_INT,FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FCVT_S_L-> List(Y, Y, Y, uopFCVT_S_X, IQT_INT,FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FCVT_S_LU->List(Y, Y, Y, uopFCVT_S_X, IQT_INT,FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FCVT_D_W-> List(Y, Y, N, uopFCVT_D_X, IQT_INT,FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FCVT_D_WU->List(Y, Y, N, uopFCVT_D_X, IQT_INT,FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FCVT_D_L-> List(Y, Y, N, uopFCVT_D_X, IQT_INT,FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FCVT_D_LU->List(Y, Y, N, uopFCVT_D_X, IQT_INT,FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), // FP to Int FCVT_W_S-> List(Y, Y, Y, uopFCVT_X_S, IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FCVT_WU_S->List(Y, Y, Y, uopFCVT_X_S, IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FCVT_L_S-> List(Y, Y, Y, uopFCVT_X_S, IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FCVT_LU_S->List(Y, Y, Y, uopFCVT_X_S, IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FCVT_W_D-> List(Y, Y, N, uopFCVT_X_D, IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FCVT_WU_D->List(Y, Y, N, uopFCVT_X_D, IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FCVT_L_D-> List(Y, Y, N, uopFCVT_X_D, IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FCVT_LU_D->List(Y, Y, N, uopFCVT_X_D, IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), // "fp_single" is used for wb_data formatting (and debugging) FEQ_S ->List(Y, Y, Y, uopCMPR_S , IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FLT_S ->List(Y, Y, Y, uopCMPR_S , IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FLE_S ->List(Y, Y, Y, uopCMPR_S , IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FEQ_D ->List(Y, Y, N, uopCMPR_D , IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FLT_D ->List(Y, Y, N, uopCMPR_D , IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FLE_D ->List(Y, Y, N, uopCMPR_D , IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FMIN_S ->List(Y, Y, Y,uopFMINMAX_S,IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FMAX_S ->List(Y, Y, Y,uopFMINMAX_S,IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FMIN_D ->List(Y, Y, N,uopFMINMAX_D,IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FMAX_D ->List(Y, Y, N,uopFMINMAX_D,IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FADD_S ->List(Y, Y, Y, uopFADD_S , IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FSUB_S ->List(Y, Y, Y, uopFSUB_S , IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FMUL_S ->List(Y, Y, Y, uopFMUL_S , IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FADD_D ->List(Y, Y, N, uopFADD_D , IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FSUB_D ->List(Y, Y, N, uopFSUB_D , IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FMUL_D ->List(Y, Y, N, uopFMUL_D , IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FMADD_S ->List(Y, Y, Y, uopFMADD_S, IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, Y, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FMSUB_S ->List(Y, Y, Y, uopFMSUB_S, IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, Y, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FNMADD_S ->List(Y, Y, Y, uopFNMADD_S,IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, Y, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FNMSUB_S ->List(Y, Y, Y, uopFNMSUB_S,IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, Y, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FMADD_D ->List(Y, Y, N, uopFMADD_D, IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, Y, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FMSUB_D ->List(Y, Y, N, uopFMSUB_D, IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, Y, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FNMADD_D ->List(Y, Y, N, uopFNMADD_D,IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, Y, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FNMSUB_D ->List(Y, Y, N, uopFNMSUB_D,IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, Y, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N) ) } /* * FP Divide SquareRoot Constants / object FDivSqrtDecode extends DecodeConstants { val table: Array[(BitPat, List[BitPat])] = Array( // frs3_en wakeup_delay // \| imm sel \| bypassable (aka, known/fixed latency) // \| \| uses_ldq \| \| is_br // is val inst? rs1 regtype \| \| \| uses_stq \| \| \| // \| is fp inst? \| rs2 type\| \| \| \| is_amo \| \| \| // \| \| is dst single-prec? \| \| \| \| \| \| \| is_fence \| \| \| // \| \| \| micro-opcode \| \| \| \| \| \| \| \| is_fencei \| \| \| is breakpoint or ecall // \| \| \| \| iq-type func dst \| \| \| \| \| \| \| \| \| mem \| \| \| \| is unique? (clear pipeline for it) // \| \| \| \| \| unit regtype \| \| \| \| \| \| \| \| \| cmd \| \| \| \| \| flush on commit // \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| csr cmd FDIV_S ->List(Y, Y, Y, uopFDIV_S , IQT_FP, FU_FDV, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FDIV_D ->List(Y, Y, N, uopFDIV_D , IQT_FP, FU_FDV, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FSQRT_S ->List(Y, Y, Y, uopFSQRT_S, IQT_FP, FU_FDV, RT_FLT, RT_FLT, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FSQRT_D ->List(Y, Y, N, uopFSQRT_D, IQT_FP, FU_FDV, RT_FLT, RT_FLT, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N) ) } //scalastyle:on /* * RoCC initial decode / object RoCCDecode extends DecodeConstants { // Note: We use FU_CSR since CSR instructions cannot co-execute with RoCC instructions // frs3_en wakeup_delay // is val inst? \| imm sel \| bypassable (aka, known/fixed latency) // \| is fp inst? \| \| uses_ldq \| \| is_br // \| \| is single-prec rs1 regtype \| \| \| uses_stq \| \| \| // \| \| \| \| rs2 type\| \| \| \| is_amo \| \| \| // \| \| \| micro-code func unit \| \| \| \| \| \| \| is_fence \| \| \| // \| \| \| \| iq-type \| \| \| \| \| \| \| \| \| is_fencei \| \| \| is breakpoint or ecall? // \| \| \| \| \| \| dst \| \| \| \| \| \| \| \| \| mem \| \| \| \| is unique? (clear pipeline for it) // \| \| \| \| \| \| regtype \| \| \| \| \| \| \| \| \| cmd \| \| \| \| \| flush on commit // \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| csr cmd // \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| val table: Array[(BitPat, List[BitPat])] = Array(// \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| CUSTOM0 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM0_RS1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_FIX, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM0_RS1_RS2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM0_RD ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM0_RD_RS1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_FIX, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM0_RD_RS1_RS2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM1_RS1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_FIX, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM1_RS1_RS2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM1_RD ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM1_RD_RS1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_FIX, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM1_RD_RS1_RS2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM2_RS1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_FIX, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM2_RS1_RS2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM2_RD ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM2_RD_RS1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_FIX, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM2_RD_RS1_RS2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM3 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM3_RS1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_FIX, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM3_RS1_RS2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM3_RD ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM3_RD_RS1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_FIX, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM3_RD_RS1_RS2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N) ) } /* * IO bundle for the Decode unit / class DecodeUnitIo(implicit p: Parameters) extends BoomBundle { val enq = new Bundle { val uop = Input(new MicroOp()) } val deq = new Bundle { val uop = Output(new MicroOp()) } // from CSRFile val status = Input(new freechips.rocketchip.rocket.MStatus()) val csr_decode = Flipped(new freechips.rocketchip.rocket.CSRDecodeIO) val interrupt = Input(Bool()) val interrupt_cause = Input(UInt(xLen.W)) } /* * Decode unit that takes in a single instruction and generates a MicroOp. / class DecodeUnit(implicit p: Parameters) extends BoomModule with freechips.rocketchip.rocket.constants.MemoryOpConstants { val io = IO(new DecodeUnitIo) val uop = Wire(new MicroOp()) uop := io.enq.uop var decode_table = XDecode.table if (usingFPU) decode_table ++= FDecode.table if (usingFPU && usingFDivSqrt) decode_table ++= FDivSqrtDecode.table if (usingRoCC) decode_table ++= RoCCDecode.table decode_table ++= (if (xLen == 64) X64Decode.table else X32Decode.table) val inst = uop.inst val cs = Wire(new CtrlSigs()).decode(inst, decode_table) // Exception Handling io.csr_decode.inst := inst val csr_en = cs.csr_cmd.isOneOf(CSR.S, CSR.C, CSR.W) val csr_ren = cs.csr_cmd.isOneOf(CSR.S, CSR.C) && uop.lrs1 === 0.U val system_insn = cs.csr_cmd === CSR.I val sfence = cs.uopc === uopSFENCE val cs_legal = cs.legal // dontTouch(cs_legal) val id_illegal_insn = !cs_legal \|\| cs.fp_val && io.csr_decode.fp_illegal \|\| // TODO check for illegal rm mode: (io.fpu.illegal_rm) cs.rocc && io.csr_decode.rocc_illegal \|\| cs.is_amo && !io.status.isa('a'-'a') \|\| (cs.fp_val && !cs.fp_single) && !io.status.isa('d'-'a') \|\| csr_en && (io.csr_decode.read_illegal \|\| !csr_ren && io.csr_decode.write_illegal) \|\| ((sfence \|\| system_insn) && io.csr_decode.system_illegal) // cs.div && !csr.io.status.isa('m'-'a') \|\| TODO check for illegal div instructions def checkExceptions(x: Seq[(Bool, UInt)]) = (x.map(_._1).reduce(_\|\|_), PriorityMux(x)) val (xcpt_valid, xcpt_cause) = checkExceptions(List( (io.interrupt && !io.enq.uop.is_sfb, io.interrupt_cause), // Disallow interrupts while we are handling a SFB (uop.bp_debug_if, (CSR.debugTriggerCause).U), (uop.bp_xcpt_if, (Causes.breakpoint).U), (uop.xcpt_pf_if, (Causes.fetch_page_fault).U), (uop.xcpt_ae_if, (Causes.fetch_access).U), (id_illegal_insn, (Causes.illegal_instruction).U))) uop.exception := xcpt_valid uop.exc_cause := xcpt_cause //------------------------------------------------------------- uop.uopc := cs.uopc uop.iq_type := cs.iq_type uop.fu_code := cs.fu_code // x-registers placed in 0-31, f-registers placed in 32-63. // This allows us to straight-up compare register specifiers and not need to // verify the rtypes (e.g., bypassing in rename). uop.ldst := inst(RD_MSB,RD_LSB) uop.lrs1 := inst(RS1_MSB,RS1_LSB) uop.lrs2 := inst(RS2_MSB,RS2_LSB) uop.lrs3 := inst(RS3_MSB,RS3_LSB) uop.ldst_val := cs.dst_type =/= RT_X && !(uop.ldst === 0.U && uop.dst_rtype === RT_FIX) uop.dst_rtype := cs.dst_type uop.lrs1_rtype := cs.rs1_type uop.lrs2_rtype := cs.rs2_type uop.frs3_en := cs.frs3_en uop.ldst_is_rs1 := uop.is_sfb_shadow // SFB optimization when (uop.is_sfb_shadow && cs.rs2_type === RT_X) { uop.lrs2_rtype := RT_FIX uop.lrs2 := inst(RD_MSB,RD_LSB) uop.ldst_is_rs1 := false.B } .elsewhen (uop.is_sfb_shadow && cs.uopc === uopADD && inst(RS1_MSB,RS1_LSB) === 0.U) { uop.uopc := uopMOV uop.lrs1 := inst(RD_MSB, RD_LSB) uop.ldst_is_rs1 := true.B } when (uop.is_sfb_br) { uop.fu_code := FU_JMP } uop.fp_val := cs.fp_val uop.fp_single := cs.fp_single // TODO use this signal instead of the FPU decode's table signal? uop.mem_cmd := cs.mem_cmd uop.mem_size := Mux(cs.mem_cmd.isOneOf(M_SFENCE, M_FLUSH_ALL), Cat(uop.lrs2 =/= 0.U, uop.lrs1 =/= 0.U), inst(13,12)) uop.mem_signed := !inst(14) uop.uses_ldq := cs.uses_ldq uop.uses_stq := cs.uses_stq uop.is_amo := cs.is_amo uop.is_fence := cs.is_fence uop.is_fencei := cs.is_fencei uop.is_sys_pc2epc := cs.is_sys_pc2epc uop.is_unique := cs.inst_unique uop.flush_on_commit := cs.flush_on_commit \|\| (csr_en && !csr_ren && io.csr_decode.write_flush) uop.bypassable := cs.bypassable //------------------------------------------------------------- // immediates // repackage the immediate, and then pass the fewest number of bits around val di24_20 = Mux(cs.imm_sel === IS_B \|\| cs.imm_sel === IS_S, inst(11,7), inst(24,20)) uop.imm_packed := Cat(inst(31,25), di24_20, inst(19,12)) //------------------------------------------------------------- uop.is_br := cs.is_br uop.is_jal := (uop.uopc === uopJAL) uop.is_jalr := (uop.uopc === uopJALR) // uop.is_jump := cs.is_jal \|\| (uop.uopc === uopJALR) // uop.is_ret := (uop.uopc === uopJALR) && // (uop.ldst === X0) && // (uop.lrs1 === RA) // uop.is_call := (uop.uopc === uopJALR \|\| uop.uopc === uopJAL) && // (uop.ldst === RA) //------------------------------------------------------------- io.deq.uop := uop } /* * Smaller Decode unit for the Frontend to decode different * branches. * Accepts EXPANDED RVC instructions / class BranchDecodeSignals(implicit p: Parameters) extends BoomBundle { val is_ret = Bool() val is_call = Bool() val target = UInt(vaddrBitsExtended.W) val cfi_type = UInt(CFI_SZ.W) // Is this branch a short forwards jump? val sfb_offset = Valid(UInt(log2Ceil(icBlockBytes).W)) // Is this instruction allowed to be inside a sfb? val shadowable = Bool() } class BranchDecode(implicit p: Parameters) extends BoomModule { val io = IO(new Bundle { val inst = Input(UInt(32.W)) val pc = Input(UInt(vaddrBitsExtended.W)) val out = Output(new BranchDecodeSignals) }) val bpd_csignals = freechips.rocketchip.rocket.DecodeLogic(io.inst, List[BitPat](N, N, N, N, X), //// is br? //// \| is jal? //// \| \| is jalr? //// \| \| \| //// \| \| \| shadowable //// \| \| \| \| has_rs2 //// \| \| \| \| \| Array[(BitPat, List[BitPat])]( JAL -> List(N, Y, N, N, X), JALR -> List(N, N, Y, N, X), BEQ -> List(Y, N, N, N, X), BNE -> List(Y, N, N, N, X), BGE -> List(Y, N, N, N, X), BGEU -> List(Y, N, N, N, X), BLT -> List(Y, N, N, N, X), BLTU -> List(Y, N, N, N, X), SLLI -> List(N, N, N, Y, N), SRLI -> List(N, N, N, Y, N), SRAI -> List(N, N, N, Y, N), ADDIW -> List(N, N, N, Y, N), SLLIW -> List(N, N, N, Y, N), SRAIW -> List(N, N, N, Y, N), SRLIW -> List(N, N, N, Y, N), ADDW -> List(N, N, N, Y, Y), SUBW -> List(N, N, N, Y, Y), SLLW -> List(N, N, N, Y, Y), SRAW -> List(N, N, N, Y, Y), SRLW -> List(N, N, N, Y, Y), LUI -> List(N, N, N, Y, N), ADDI -> List(N, N, N, Y, N), ANDI -> List(N, N, N, Y, N), ORI -> List(N, N, N, Y, N), XORI -> List(N, N, N, Y, N), SLTI -> List(N, N, N, Y, N), SLTIU -> List(N, N, N, Y, N), SLL -> List(N, N, N, Y, Y), ADD -> List(N, N, N, Y, Y), SUB -> List(N, N, N, Y, Y), SLT -> List(N, N, N, Y, Y), SLTU -> List(N, N, N, Y, Y), AND -> List(N, N, N, Y, Y), OR -> List(N, N, N, Y, Y), XOR -> List(N, N, N, Y, Y), SRA -> List(N, N, N, Y, Y), SRL -> List(N, N, N, Y, Y) )) val cs_is_br = bpd_csignals(0)(0) val cs_is_jal = bpd_csignals(1)(0) val cs_is_jalr = bpd_csignals(2)(0) val cs_is_shadowable = bpd_csignals(3)(0) val cs_has_rs2 = bpd_csignals(4)(0) io.out.is_call := (cs_is_jal \|\| cs_is_jalr) && GetRd(io.inst) === RA io.out.is_ret := cs_is_jalr && GetRs1(io.inst) === BitPat("b00?01") && GetRd(io.inst) === X0 io.out.target := Mux(cs_is_br, ComputeBranchTarget(io.pc, io.inst, xLen), ComputeJALTarget(io.pc, io.inst, xLen)) io.out.cfi_type := Mux(cs_is_jalr, CFI_JALR, Mux(cs_is_jal, CFI_JAL, Mux(cs_is_br, CFI_BR, CFI_X))) val br_offset = Cat(io.inst(7), io.inst(30,25), io.inst(11,8), 0.U(1.W)) // Is a sfb if it points forwards (offset is positive) io.out.sfb_offset.valid := cs_is_br && !io.inst(31) && br_offset =/= 0.U && (br_offset >> log2Ceil(icBlockBytes)) === 0.U io.out.sfb_offset.bits := br_offset io.out.shadowable := cs_is_shadowable && ( !cs_has_rs2 \|\| (GetRs1(io.inst) === GetRd(io.inst)) \|\| (io.inst === ADD && GetRs1(io.inst) === X0) ) } /* * Track the current "branch mask", and give out the branch mask to each micro-op in Decode * (each micro-op in the machine has a branch mask which says which branches it * is being speculated under). * * @param pl_width pipeline width for the processor / class BranchMaskGenerationLogic(val pl_width: Int)(implicit p: Parameters) extends BoomModule { val io = IO(new Bundle { // guess if the uop is a branch (we'll catch this later) val is_branch = Input(Vec(pl_width, Bool())) // lock in that it's actually a branch and will fire, so we update // the branch_masks. val will_fire = Input(Vec(pl_width, Bool())) // give out tag immediately (needed in rename) // mask can come later in the cycle val br_tag = Output(Vec(pl_width, UInt(brTagSz.W))) val br_mask = Output(Vec(pl_width, UInt(maxBrCount.W))) // tell decoders the branch mask has filled up, but on the granularity // of an individual micro-op (so some micro-ops can go through) val is_full = Output(Vec(pl_width, Bool())) val brupdate = Input(new BrUpdateInfo()) val flush_pipeline = Input(Bool()) val debug_branch_mask = Output(UInt(maxBrCount.W)) }) val branch_mask = RegInit(0.U(maxBrCount.W)) //------------------------------------------------------------- // Give out the branch tag to each branch micro-op var allocate_mask = branch_mask val tag_masks = Wire(Vec(pl_width, UInt(maxBrCount.W))) for (w <- 0 until pl_width) { // TODO this is a loss of performance as we're blocking branches based on potentially fake branches io.is_full(w) := (allocate_mask === ~(0.U(maxBrCount.W))) && io.is_branch(w) // find br_tag and compute next br_mask val new_br_tag = Wire(UInt(brTagSz.W)) new_br_tag := 0.U tag_masks(w) := 0.U for (i <- maxBrCount-1 to 0 by -1) { when (~allocate_mask(i)) { new_br_tag := i.U tag_masks(w) := (1.U << i.U) } } io.br_tag(w) := new_br_tag allocate_mask = Mux(io.is_branch(w), tag_masks(w) \| allocate_mask, allocate_mask) } //------------------------------------------------------------- // Give out the branch mask to each micro-op // (kill off the bits that corresponded to branches that aren't going to fire) var curr_mask = branch_mask for (w <- 0 until pl_width) { io.br_mask(w) := GetNewBrMask(io.brupdate, curr_mask) curr_mask = Mux(io.will_fire(w), tag_masks(w) \| curr_mask, curr_mask) } //------------------------------------------------------------- // Update the current branch_mask when (io.flush_pipeline) { branch_mask := 0.U } .otherwise { val mask = Mux(io.brupdate.b2.mispredict, io.brupdate.b2.uop.br_mask, ~(0.U(maxBrCount.W))) branch_mask := GetNewBrMask(io.brupdate, curr_mask) & mask } io.debug_branch_mask := branch_mask } File consts.scala: //*************************************************************************** // Copyright (c) 2011 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Constants //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.common.constants import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util.Str import freechips.rocketchip.rocket.RVCExpander / * Mixin for issue queue types / trait IQType { val IQT_SZ = 3 val IQT_INT = 1.U(IQT_SZ.W) val IQT_MEM = 2.U(IQT_SZ.W) val IQT_FP = 4.U(IQT_SZ.W) val IQT_MFP = 6.U(IQT_SZ.W) } /* * Mixin for scalar operation constants / trait ScalarOpConstants { val X = BitPat("b?") val Y = BitPat("b1") val N = BitPat("b0") //********************************* // Extra Constants // Which branch predictor predicted us val BSRC_SZ = 2 val BSRC_1 = 0.U(BSRC_SZ.W) // 1-cycle branch pred val BSRC_2 = 1.U(BSRC_SZ.W) // 2-cycle branch pred val BSRC_3 = 2.U(BSRC_SZ.W) // 3-cycle branch pred val BSRC_C = 3.U(BSRC_SZ.W) // core branch resolution //******************************** // Control Signals // CFI types val CFI_SZ = 3 val CFI_X = 0.U(CFI_SZ.W) // Not a CFI instruction val CFI_BR = 1.U(CFI_SZ.W) // Branch val CFI_JAL = 2.U(CFI_SZ.W) // JAL val CFI_JALR = 3.U(CFI_SZ.W) // JALR // PC Select Signal val PC_PLUS4 = 0.U(2.W) // PC + 4 val PC_BRJMP = 1.U(2.W) // brjmp_target val PC_JALR = 2.U(2.W) // jump_reg_target // Branch Type val BR_N = 0.U(4.W) // Next val BR_NE = 1.U(4.W) // Branch on NotEqual val BR_EQ = 2.U(4.W) // Branch on Equal val BR_GE = 3.U(4.W) // Branch on Greater/Equal val BR_GEU = 4.U(4.W) // Branch on Greater/Equal Unsigned val BR_LT = 5.U(4.W) // Branch on Less Than val BR_LTU = 6.U(4.W) // Branch on Less Than Unsigned val BR_J = 7.U(4.W) // Jump val BR_JR = 8.U(4.W) // Jump Register // RS1 Operand Select Signal val OP1_RS1 = 0.U(2.W) // Register Source #1 val OP1_ZERO= 1.U(2.W) val OP1_PC = 2.U(2.W) val OP1_X = BitPat("b??") // RS2 Operand Select Signal val OP2_RS2 = 0.U(3.W) // Register Source #2 val OP2_IMM = 1.U(3.W) // immediate val OP2_ZERO= 2.U(3.W) // constant 0 val OP2_NEXT= 3.U(3.W) // constant 2/4 (for PC+2/4) val OP2_IMMC= 4.U(3.W) // for CSR imm found in RS1 val OP2_X = BitPat("b???") // Register File Write Enable Signal val REN_0 = false.B val REN_1 = true.B // Is 32b Word or 64b Doubldword? val SZ_DW = 1 val DW_X = true.B // Bool(xLen==64) val DW_32 = false.B val DW_64 = true.B val DW_XPR = true.B // Bool(xLen==64) // Memory Enable Signal val MEN_0 = false.B val MEN_1 = true.B val MEN_X = false.B // Immediate Extend Select val IS_I = 0.U(3.W) // I-Type (LD,ALU) val IS_S = 1.U(3.W) // S-Type (ST) val IS_B = 2.U(3.W) // SB-Type (BR) val IS_U = 3.U(3.W) // U-Type (LUI/AUIPC) val IS_J = 4.U(3.W) // UJ-Type (J/JAL) val IS_X = BitPat("b???") // Decode Stage Control Signals val RT_FIX = 0.U(2.W) val RT_FLT = 1.U(2.W) val RT_PAS = 3.U(2.W) // pass-through (prs1 := lrs1, etc) val RT_X = 2.U(2.W) // not-a-register (but shouldn't get a busy-bit, etc.) // TODO rename RT_NAR // Micro-op opcodes // TODO change micro-op opcodes into using enum val UOPC_SZ = 7 val uopX = BitPat.dontCare(UOPC_SZ) val uopNOP = 0.U(UOPC_SZ.W) val uopLD = 1.U(UOPC_SZ.W) val uopSTA = 2.U(UOPC_SZ.W) // store address generation val uopSTD = 3.U(UOPC_SZ.W) // store data generation val uopLUI = 4.U(UOPC_SZ.W) val uopADDI = 5.U(UOPC_SZ.W) val uopANDI = 6.U(UOPC_SZ.W) val uopORI = 7.U(UOPC_SZ.W) val uopXORI = 8.U(UOPC_SZ.W) val uopSLTI = 9.U(UOPC_SZ.W) val uopSLTIU= 10.U(UOPC_SZ.W) val uopSLLI = 11.U(UOPC_SZ.W) val uopSRAI = 12.U(UOPC_SZ.W) val uopSRLI = 13.U(UOPC_SZ.W) val uopSLL = 14.U(UOPC_SZ.W) val uopADD = 15.U(UOPC_SZ.W) val uopSUB = 16.U(UOPC_SZ.W) val uopSLT = 17.U(UOPC_SZ.W) val uopSLTU = 18.U(UOPC_SZ.W) val uopAND = 19.U(UOPC_SZ.W) val uopOR = 20.U(UOPC_SZ.W) val uopXOR = 21.U(UOPC_SZ.W) val uopSRA = 22.U(UOPC_SZ.W) val uopSRL = 23.U(UOPC_SZ.W) val uopBEQ = 24.U(UOPC_SZ.W) val uopBNE = 25.U(UOPC_SZ.W) val uopBGE = 26.U(UOPC_SZ.W) val uopBGEU = 27.U(UOPC_SZ.W) val uopBLT = 28.U(UOPC_SZ.W) val uopBLTU = 29.U(UOPC_SZ.W) val uopCSRRW= 30.U(UOPC_SZ.W) val uopCSRRS= 31.U(UOPC_SZ.W) val uopCSRRC= 32.U(UOPC_SZ.W) val uopCSRRWI=33.U(UOPC_SZ.W) val uopCSRRSI=34.U(UOPC_SZ.W) val uopCSRRCI=35.U(UOPC_SZ.W) val uopJ = 36.U(UOPC_SZ.W) val uopJAL = 37.U(UOPC_SZ.W) val uopJALR = 38.U(UOPC_SZ.W) val uopAUIPC= 39.U(UOPC_SZ.W) //val uopSRET = 40.U(UOPC_SZ.W) val uopCFLSH= 41.U(UOPC_SZ.W) val uopFENCE= 42.U(UOPC_SZ.W) val uopADDIW= 43.U(UOPC_SZ.W) val uopADDW = 44.U(UOPC_SZ.W) val uopSUBW = 45.U(UOPC_SZ.W) val uopSLLIW= 46.U(UOPC_SZ.W) val uopSLLW = 47.U(UOPC_SZ.W) val uopSRAIW= 48.U(UOPC_SZ.W) val uopSRAW = 49.U(UOPC_SZ.W) val uopSRLIW= 50.U(UOPC_SZ.W) val uopSRLW = 51.U(UOPC_SZ.W) val uopMUL = 52.U(UOPC_SZ.W) val uopMULH = 53.U(UOPC_SZ.W) val uopMULHU= 54.U(UOPC_SZ.W) val uopMULHSU=55.U(UOPC_SZ.W) val uopMULW = 56.U(UOPC_SZ.W) val uopDIV = 57.U(UOPC_SZ.W) val uopDIVU = 58.U(UOPC_SZ.W) val uopREM = 59.U(UOPC_SZ.W) val uopREMU = 60.U(UOPC_SZ.W) val uopDIVW = 61.U(UOPC_SZ.W) val uopDIVUW= 62.U(UOPC_SZ.W) val uopREMW = 63.U(UOPC_SZ.W) val uopREMUW= 64.U(UOPC_SZ.W) val uopFENCEI = 65.U(UOPC_SZ.W) // = 66.U(UOPC_SZ.W) val uopAMO_AG = 67.U(UOPC_SZ.W) // AMO-address gen (use normal STD for datagen) val uopFMV_W_X = 68.U(UOPC_SZ.W) val uopFMV_D_X = 69.U(UOPC_SZ.W) val uopFMV_X_W = 70.U(UOPC_SZ.W) val uopFMV_X_D = 71.U(UOPC_SZ.W) val uopFSGNJ_S = 72.U(UOPC_SZ.W) val uopFSGNJ_D = 73.U(UOPC_SZ.W) val uopFCVT_S_D = 74.U(UOPC_SZ.W) val uopFCVT_D_S = 75.U(UOPC_SZ.W) val uopFCVT_S_X = 76.U(UOPC_SZ.W) val uopFCVT_D_X = 77.U(UOPC_SZ.W) val uopFCVT_X_S = 78.U(UOPC_SZ.W) val uopFCVT_X_D = 79.U(UOPC_SZ.W) val uopCMPR_S = 80.U(UOPC_SZ.W) val uopCMPR_D = 81.U(UOPC_SZ.W) val uopFCLASS_S = 82.U(UOPC_SZ.W) val uopFCLASS_D = 83.U(UOPC_SZ.W) val uopFMINMAX_S = 84.U(UOPC_SZ.W) val uopFMINMAX_D = 85.U(UOPC_SZ.W) // = 86.U(UOPC_SZ.W) val uopFADD_S = 87.U(UOPC_SZ.W) val uopFSUB_S = 88.U(UOPC_SZ.W) val uopFMUL_S = 89.U(UOPC_SZ.W) val uopFADD_D = 90.U(UOPC_SZ.W) val uopFSUB_D = 91.U(UOPC_SZ.W) val uopFMUL_D = 92.U(UOPC_SZ.W) val uopFMADD_S = 93.U(UOPC_SZ.W) val uopFMSUB_S = 94.U(UOPC_SZ.W) val uopFNMADD_S = 95.U(UOPC_SZ.W) val uopFNMSUB_S = 96.U(UOPC_SZ.W) val uopFMADD_D = 97.U(UOPC_SZ.W) val uopFMSUB_D = 98.U(UOPC_SZ.W) val uopFNMADD_D = 99.U(UOPC_SZ.W) val uopFNMSUB_D = 100.U(UOPC_SZ.W) val uopFDIV_S = 101.U(UOPC_SZ.W) val uopFDIV_D = 102.U(UOPC_SZ.W) val uopFSQRT_S = 103.U(UOPC_SZ.W) val uopFSQRT_D = 104.U(UOPC_SZ.W) val uopWFI = 105.U(UOPC_SZ.W) // pass uop down the CSR pipeline val uopERET = 106.U(UOPC_SZ.W) // pass uop down the CSR pipeline, also is ERET val uopSFENCE = 107.U(UOPC_SZ.W) val uopROCC = 108.U(UOPC_SZ.W) val uopMOV = 109.U(UOPC_SZ.W) // conditional mov decoded from "add rd, x0, rs2" // The Bubble Instruction (Machine generated NOP) // Insert (XOR x0,x0,x0) which is different from software compiler // generated NOPs which are (ADDI x0, x0, 0). // Reasoning for this is to let visualizers and stat-trackers differentiate // between software NOPs and machine-generated Bubbles in the pipeline. val BUBBLE = (0x4033).U(32.W) def NullMicroOp()(implicit p: Parameters): boom.v3.common.MicroOp = { val uop = Wire(new boom.v3.common.MicroOp) uop := DontCare // Overridden in the following lines uop.uopc := uopNOP // maybe not required, but helps on asserts that try to catch spurious behavior uop.bypassable := false.B uop.fp_val := false.B uop.uses_stq := false.B uop.uses_ldq := false.B uop.pdst := 0.U uop.dst_rtype := RT_X val cs = Wire(new boom.v3.common.CtrlSignals()) cs := DontCare // Overridden in the following lines cs.br_type := BR_N cs.csr_cmd := freechips.rocketchip.rocket.CSR.N cs.is_load := false.B cs.is_sta := false.B cs.is_std := false.B uop.ctrl := cs uop } } / * Mixin for RISCV constants / trait RISCVConstants { // abstract out instruction decode magic numbers val RD_MSB = 11 val RD_LSB = 7 val RS1_MSB = 19 val RS1_LSB = 15 val RS2_MSB = 24 val RS2_LSB = 20 val RS3_MSB = 31 val RS3_LSB = 27 val CSR_ADDR_MSB = 31 val CSR_ADDR_LSB = 20 val CSR_ADDR_SZ = 12 // location of the fifth bit in the shamt (for checking for illegal ops for SRAIW,etc.) val SHAMT_5_BIT = 25 val LONGEST_IMM_SZ = 20 val X0 = 0.U val RA = 1.U // return address register // memory consistency model // The C/C++ atomics MCM requires that two loads to the same address maintain program order. // The Cortex A9 does NOT enforce load/load ordering (which leads to buggy behavior). val MCM_ORDER_DEPENDENT_LOADS = true val jal_opc = (0x6f).U val jalr_opc = (0x67).U def GetUop(inst: UInt): UInt = inst(6,0) def GetRd (inst: UInt): UInt = inst(RD_MSB,RD_LSB) def GetRs1(inst: UInt): UInt = inst(RS1_MSB,RS1_LSB) def ExpandRVC(inst: UInt)(implicit p: Parameters): UInt = { val rvc_exp = Module(new RVCExpander) rvc_exp.io.in := inst Mux(rvc_exp.io.rvc, rvc_exp.io.out.bits, inst) } // Note: Accepts only EXPANDED rvc instructions def ComputeBranchTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = { val b_imm32 = Cat(Fill(20,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) ((pc.asSInt + b_imm32.asSInt).asSInt & (-2).S).asUInt } // Note: Accepts only EXPANDED rvc instructions def ComputeJALTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = { val j_imm32 = Cat(Fill(12,inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) ((pc.asSInt + j_imm32.asSInt).asSInt & (-2).S).asUInt } // Note: Accepts only EXPANDED rvc instructions def GetCfiType(inst: UInt)(implicit p: Parameters): UInt = { val bdecode = Module(new boom.v3.exu.BranchDecode) bdecode.io.inst := inst bdecode.io.pc := 0.U bdecode.io.out.cfi_type } } /* * Mixin for exception cause constants */ trait ExcCauseConstants { // a memory disambigious misspeculation occurred val MINI_EXCEPTION_MEM_ORDERING = 16.U val MINI_EXCEPTION_CSR_REPLAY = 17.U require (!freechips.rocketchip.rocket.Causes.all.contains(16)) require (!freechips.rocketchip.rocket.Causes.all.contains(17)) }	module BranchDecode_9( // @[decode.scala:623:7] input clock, // @[decode.scala:623:7] input reset, // @[decode.scala:623:7] input [31:0] io_inst, // @[decode.scala:625:14] input [39:0] io_pc, // @[decode.scala:625:14] output io_out_is_ret, // @[decode.scala:625:14] output io_out_is_call, // @[decode.scala:625:14] output [39:0] io_out_target, // @[decode.scala:625:14] output [2:0] io_out_cfi_type, // @[decode.scala:625:14] output io_out_sfb_offset_valid, // @[decode.scala:625:14] output [5:0] io_out_sfb_offset_bits, // @[decode.scala:625:14] output io_out_shadowable // @[decode.scala:625:14] ); wire [31:0] io_inst_0 = io_inst; // @[decode.scala:623:7] wire [39:0] io_pc_0 = io_pc; // @[decode.scala:623:7] wire [31:0] bpd_csignals_decoded_plaInput = io_inst_0; // @[pla.scala:77:22] wire _io_out_is_ret_T_6; // @[decode.scala:695:72] wire [39:0] _io_out_target_T = io_pc_0; // @[decode.scala:623:7] wire [39:0] _io_out_target_T_8 = io_pc_0; // @[decode.scala:623:7] wire _io_out_is_call_T_3; // @[decode.scala:694:47] wire [39:0] _io_out_target_T_16; // @[decode.scala:697:23] wire [2:0] _io_out_cfi_type_T_2; // @[decode.scala:700:8] wire _io_out_sfb_offset_valid_T_7; // @[decode.scala:710:76] wire _io_out_shadowable_T_11; // @[decode.scala:712:41] wire io_out_sfb_offset_valid_0; // @[decode.scala:623:7] wire [5:0] io_out_sfb_offset_bits_0; // @[decode.scala:623:7] wire io_out_is_ret_0; // @[decode.scala:623:7] wire io_out_is_call_0; // @[decode.scala:623:7] wire [39:0] io_out_target_0; // @[decode.scala:623:7] wire [2:0] io_out_cfi_type_0; // @[decode.scala:623:7] wire io_out_shadowable_0; // @[decode.scala:623:7] wire [31:0] bpd_csignals_decoded_invInputs = ~bpd_csignals_decoded_plaInput; // @[pla.scala:77:22, :78:21] wire [4:0] bpd_csignals_decoded_invMatrixOutputs; // @[pla.scala:120:37] wire [4:0] bpd_csignals_decoded; // @[pla.scala:81:23] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_1 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_2 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_3 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_4 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_5 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_6 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_7 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_8 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_9 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_10 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_11 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_12 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_13 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_14 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_15 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_1 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_2 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_3 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_4 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_5 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_6 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_7 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_8 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_9 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_10 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_11 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_12 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_13 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_14 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_15 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_1 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_2 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_3 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_4 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_6 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_9 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_10 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_11 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_12 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_13 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_14 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_15 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_3 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_5 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_6 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_7 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_9 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_11 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_12 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_13 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_1 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_2 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_3 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_4 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_5 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_9 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_10 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_11 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_13 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_14 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_15 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5 = bpd_csignals_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_1 = bpd_csignals_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_9 = bpd_csignals_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_11 = bpd_csignals_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_13 = bpd_csignals_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_1 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_2 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_3 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_4 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_5 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_9 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_10 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_11 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_13 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_14 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_15 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7 = bpd_csignals_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_1 = bpd_csignals_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_2 = bpd_csignals_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_6 = bpd_csignals_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo = {bpd_csignals_decoded_andMatrixOutputs_lo_hi, bpd_csignals_decoded_andMatrixOutputs_lo_lo}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi = {bpd_csignals_decoded_andMatrixOutputs_hi_hi, bpd_csignals_decoded_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53] wire [7:0] _bpd_csignals_decoded_andMatrixOutputs_T = {bpd_csignals_decoded_andMatrixOutputs_hi, bpd_csignals_decoded_andMatrixOutputs_lo}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_5_2 = &_bpd_csignals_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_1 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_2 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_4 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_5 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_4 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_5 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_8 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_7 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_12 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_13 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8 = bpd_csignals_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_1 = bpd_csignals_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_4 = bpd_csignals_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_3 = bpd_csignals_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_1}; // @[pla.scala:91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_1 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_1, bpd_csignals_decoded_andMatrixOutputs_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_1}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_1}; // @[pla.scala:90:45, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_1 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_1}; // @[pla.scala:91:29, :98:53] wire [4:0] bpd_csignals_decoded_andMatrixOutputs_hi_1 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_1, bpd_csignals_decoded_andMatrixOutputs_hi_lo_1}; // @[pla.scala:98:53] wire [8:0] _bpd_csignals_decoded_andMatrixOutputs_T_1 = {bpd_csignals_decoded_andMatrixOutputs_hi_1, bpd_csignals_decoded_andMatrixOutputs_lo_1}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_9_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_1; // @[pla.scala:98:{53,70}] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_2 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_3 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_4 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_5 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_6 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_7 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_8 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_12 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_15 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9 = bpd_csignals_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_3 = bpd_csignals_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_3 = bpd_csignals_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_6 = bpd_csignals_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_7 = bpd_csignals_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_8 = bpd_csignals_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10 = bpd_csignals_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_2 = bpd_csignals_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_2 = bpd_csignals_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_4 = bpd_csignals_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_5 = bpd_csignals_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_5 = bpd_csignals_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_6 = bpd_csignals_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_7 = bpd_csignals_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11 = bpd_csignals_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_1 = bpd_csignals_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_2 = bpd_csignals_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_3 = bpd_csignals_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_4 = bpd_csignals_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_5 = bpd_csignals_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_6 = bpd_csignals_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_7 = bpd_csignals_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12 = bpd_csignals_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_1 = bpd_csignals_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_2 = bpd_csignals_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_3 = bpd_csignals_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_4 = bpd_csignals_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_5 = bpd_csignals_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_6 = bpd_csignals_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_7 = bpd_csignals_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13 = bpd_csignals_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_1 = bpd_csignals_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_2 = bpd_csignals_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_3 = bpd_csignals_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_4 = bpd_csignals_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_5 = bpd_csignals_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_6 = bpd_csignals_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_7 = bpd_csignals_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14 = bpd_csignals_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_1 = bpd_csignals_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_1 = bpd_csignals_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_2 = bpd_csignals_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_3 = bpd_csignals_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_4 = bpd_csignals_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_5 = bpd_csignals_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_6 = bpd_csignals_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13}; // @[pla.scala:91:29, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_2 = {bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9}; // @[pla.scala:91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_2 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo}; // @[pla.scala:98:53] wire [6:0] bpd_csignals_decoded_andMatrixOutputs_lo_2 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_2, bpd_csignals_decoded_andMatrixOutputs_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_2}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_2 = {bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_2}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_2 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_1, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo}; // @[pla.scala:98:53] wire [7:0] bpd_csignals_decoded_andMatrixOutputs_hi_2 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_2, bpd_csignals_decoded_andMatrixOutputs_hi_lo_2}; // @[pla.scala:98:53] wire [14:0] _bpd_csignals_decoded_andMatrixOutputs_T_2 = {bpd_csignals_decoded_andMatrixOutputs_hi_2, bpd_csignals_decoded_andMatrixOutputs_lo_2}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_14_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_2; // @[pla.scala:98:{53,70}] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_1 = bpd_csignals_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_2 = bpd_csignals_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_3 = bpd_csignals_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_4 = bpd_csignals_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_1}; // @[pla.scala:91:29, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_3 = {bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_1}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_1}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_2}; // @[pla.scala:91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_3 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_1, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_1}; // @[pla.scala:98:53] wire [6:0] bpd_csignals_decoded_andMatrixOutputs_lo_3 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_3, bpd_csignals_decoded_andMatrixOutputs_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_3}; // @[pla.scala:90:45, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_3 = {bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_3}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_3}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_2 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_3}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_3 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_2, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_1}; // @[pla.scala:98:53] wire [6:0] bpd_csignals_decoded_andMatrixOutputs_hi_3 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_3, bpd_csignals_decoded_andMatrixOutputs_hi_lo_3}; // @[pla.scala:98:53] wire [13:0] _bpd_csignals_decoded_andMatrixOutputs_T_3 = {bpd_csignals_decoded_andMatrixOutputs_hi_3, bpd_csignals_decoded_andMatrixOutputs_lo_3}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_0_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_3; // @[pla.scala:98:{53,70}] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_2 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_2}; // @[pla.scala:91:29, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_4 = {bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_1}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_2 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_2}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_2 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_2}; // @[pla.scala:91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_4 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_2, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] bpd_csignals_decoded_andMatrixOutputs_lo_4 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_4, bpd_csignals_decoded_andMatrixOutputs_lo_lo_4}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_4}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_2 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_4}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_4 = {bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_2, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_2 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_4}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_3 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_4}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_4 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_3, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_2}; // @[pla.scala:98:53] wire [7:0] bpd_csignals_decoded_andMatrixOutputs_hi_4 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_4, bpd_csignals_decoded_andMatrixOutputs_hi_lo_4}; // @[pla.scala:98:53] wire [14:0] _bpd_csignals_decoded_andMatrixOutputs_T_4 = {bpd_csignals_decoded_andMatrixOutputs_hi_4, bpd_csignals_decoded_andMatrixOutputs_lo_4}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_2_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_4; // @[pla.scala:98:{53,70}] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_5 = bpd_csignals_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_7 = bpd_csignals_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_8 = bpd_csignals_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_5}; // @[pla.scala:90:45, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_5 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_5}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_5}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_5 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_5, bpd_csignals_decoded_andMatrixOutputs_hi_lo_5}; // @[pla.scala:98:53] wire [6:0] _bpd_csignals_decoded_andMatrixOutputs_T_5 = {bpd_csignals_decoded_andMatrixOutputs_hi_5, bpd_csignals_decoded_andMatrixOutputs_lo_5}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_12_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_5; // @[pla.scala:98:{53,70}] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_6 = bpd_csignals_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_7 = bpd_csignals_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_8 = bpd_csignals_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_12 = bpd_csignals_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_6 = bpd_csignals_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_7 = bpd_csignals_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_8 = bpd_csignals_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_12 = bpd_csignals_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_6 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_6, bpd_csignals_decoded_andMatrixOutputs_lo_lo_5}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_6}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_6}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_6 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_6, bpd_csignals_decoded_andMatrixOutputs_hi_lo_6}; // @[pla.scala:98:53] wire [7:0] _bpd_csignals_decoded_andMatrixOutputs_T_6 = {bpd_csignals_decoded_andMatrixOutputs_hi_6, bpd_csignals_decoded_andMatrixOutputs_lo_6}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_6_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_6; // @[pla.scala:98:{53,70}] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_3}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_3 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_7}; // @[pla.scala:90:45, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_7 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_6}; // @[pla.scala:91:29, :98:53] wire [4:0] bpd_csignals_decoded_andMatrixOutputs_lo_7 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_7, bpd_csignals_decoded_andMatrixOutputs_lo_lo_6}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_7 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_7}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_4 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_7}; // @[pla.scala:90:45, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_7 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_7}; // @[pla.scala:90:45, :98:53] wire [4:0] bpd_csignals_decoded_andMatrixOutputs_hi_7 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_7, bpd_csignals_decoded_andMatrixOutputs_hi_lo_7}; // @[pla.scala:98:53] wire [9:0] _bpd_csignals_decoded_andMatrixOutputs_T_7 = {bpd_csignals_decoded_andMatrixOutputs_hi_7, bpd_csignals_decoded_andMatrixOutputs_lo_7}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_15_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_7; // @[pla.scala:98:{53,70}] wire _bpd_csignals_decoded_orMatrixOutputs_T_4 = bpd_csignals_decoded_andMatrixOutputs_15_2; // @[pla.scala:98:70, :114:36] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_8 = bpd_csignals_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_10 = bpd_csignals_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_14 = bpd_csignals_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_8 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_8, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_8 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_8, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_8}; // @[pla.scala:90:45, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_8 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_8, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_8}; // @[pla.scala:90:45, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_8 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_8, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_8}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_8 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_8, bpd_csignals_decoded_andMatrixOutputs_hi_lo_8}; // @[pla.scala:98:53] wire [6:0] _bpd_csignals_decoded_andMatrixOutputs_T_8 = {bpd_csignals_decoded_andMatrixOutputs_hi_8, bpd_csignals_decoded_andMatrixOutputs_lo_8}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_11_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_8; // @[pla.scala:98:{53,70}] wire _bpd_csignals_decoded_orMatrixOutputs_T_5 = bpd_csignals_decoded_andMatrixOutputs_11_2; // @[pla.scala:98:70, :114:36] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_7 = bpd_csignals_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_10 = bpd_csignals_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_11 = bpd_csignals_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_14 = bpd_csignals_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_15 = bpd_csignals_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_3 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_3}; // @[pla.scala:91:29, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_7 = {bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_2}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_3 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_3}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_4 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_4}; // @[pla.scala:91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_9 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_4, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_3}; // @[pla.scala:98:53] wire [6:0] bpd_csignals_decoded_andMatrixOutputs_lo_9 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_9, bpd_csignals_decoded_andMatrixOutputs_lo_lo_7}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_2 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_9, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_3 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_9, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_9 = {bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_3, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_3 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_9, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_9}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_9, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_9}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_9 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_5, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_3}; // @[pla.scala:98:53] wire [7:0] bpd_csignals_decoded_andMatrixOutputs_hi_9 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_9, bpd_csignals_decoded_andMatrixOutputs_hi_lo_9}; // @[pla.scala:98:53] wire [14:0] _bpd_csignals_decoded_andMatrixOutputs_T_9 = {bpd_csignals_decoded_andMatrixOutputs_hi_9, bpd_csignals_decoded_andMatrixOutputs_lo_9}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_3_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_9; // @[pla.scala:98:{53,70}] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_4 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_4}; // @[pla.scala:91:29, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_8 = {bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_3}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_4 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_4}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_5}; // @[pla.scala:91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_10 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_5, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_4}; // @[pla.scala:98:53] wire [6:0] bpd_csignals_decoded_andMatrixOutputs_lo_10 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_10, bpd_csignals_decoded_andMatrixOutputs_lo_lo_8}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_3 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_10, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_4 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_10, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_10 = {bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_4, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_4 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_10, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_10, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_10}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_10 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_6, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_4}; // @[pla.scala:98:53] wire [7:0] bpd_csignals_decoded_andMatrixOutputs_hi_10 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_10, bpd_csignals_decoded_andMatrixOutputs_hi_lo_10}; // @[pla.scala:98:53] wire [14:0] _bpd_csignals_decoded_andMatrixOutputs_T_10 = {bpd_csignals_decoded_andMatrixOutputs_hi_10, bpd_csignals_decoded_andMatrixOutputs_lo_10}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_7_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_10; // @[pla.scala:98:{53,70}] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_9 = bpd_csignals_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_9 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_11, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_11 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_11, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_11 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_11, bpd_csignals_decoded_andMatrixOutputs_lo_lo_9}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_11 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_11, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_11}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_11 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_11, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_11}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_11 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_11, bpd_csignals_decoded_andMatrixOutputs_hi_lo_11}; // @[pla.scala:98:53] wire [7:0] _bpd_csignals_decoded_andMatrixOutputs_T_11 = {bpd_csignals_decoded_andMatrixOutputs_hi_11, bpd_csignals_decoded_andMatrixOutputs_lo_11}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_1_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_11; // @[pla.scala:98:{53,70}] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_10 = bpd_csignals_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_6 = bpd_csignals_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_8 = bpd_csignals_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_9 = bpd_csignals_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_10 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_12, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_10}; // @[pla.scala:90:45, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_12 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_12, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_12 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_12, bpd_csignals_decoded_andMatrixOutputs_lo_lo_10}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_12 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_12, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_12}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_12 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_12, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_12}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_12 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_12, bpd_csignals_decoded_andMatrixOutputs_hi_lo_12}; // @[pla.scala:98:53] wire [7:0] _bpd_csignals_decoded_andMatrixOutputs_T_12 = {bpd_csignals_decoded_andMatrixOutputs_hi_12, bpd_csignals_decoded_andMatrixOutputs_lo_12}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_13_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_12; // @[pla.scala:98:{53,70}] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_5}; // @[pla.scala:91:29, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_11 = {bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_4}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_5}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_13 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_6, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_5}; // @[pla.scala:98:53] wire [6:0] bpd_csignals_decoded_andMatrixOutputs_lo_13 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_13, bpd_csignals_decoded_andMatrixOutputs_lo_lo_11}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_4 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_13, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_13, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_13 = {bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_5, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_4}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_13, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_13}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_7 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_13, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_13}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_13 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_7, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_5}; // @[pla.scala:98:53] wire [7:0] bpd_csignals_decoded_andMatrixOutputs_hi_13 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_13, bpd_csignals_decoded_andMatrixOutputs_hi_lo_13}; // @[pla.scala:98:53] wire [14:0] _bpd_csignals_decoded_andMatrixOutputs_T_13 = {bpd_csignals_decoded_andMatrixOutputs_hi_13, bpd_csignals_decoded_andMatrixOutputs_lo_13}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_4_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_13; // @[pla.scala:98:{53,70}] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_6}; // @[pla.scala:91:29, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_12 = {bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_5}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_6}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_7 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_8, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_14 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_7, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_6}; // @[pla.scala:98:53] wire [6:0] bpd_csignals_decoded_andMatrixOutputs_lo_14 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_14, bpd_csignals_decoded_andMatrixOutputs_lo_lo_12}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_14, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_14, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_14 = {bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_6, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_5}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_14, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_8 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_14, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_14}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_14 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_8, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_6}; // @[pla.scala:98:53] wire [7:0] bpd_csignals_decoded_andMatrixOutputs_hi_14 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_14, bpd_csignals_decoded_andMatrixOutputs_hi_lo_14}; // @[pla.scala:98:53] wire [14:0] _bpd_csignals_decoded_andMatrixOutputs_T_14 = {bpd_csignals_decoded_andMatrixOutputs_hi_14, bpd_csignals_decoded_andMatrixOutputs_lo_14}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_8_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_14; // @[pla.scala:98:{53,70}] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_7 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_7}; // @[pla.scala:91:29, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_13 = {bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_6}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_7 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_7}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_8 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_9, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_15 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_8, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_7}; // @[pla.scala:98:53] wire [6:0] bpd_csignals_decoded_andMatrixOutputs_lo_15 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_15, bpd_csignals_decoded_andMatrixOutputs_lo_lo_13}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_15, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_7 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_15, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_15 = {bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_7, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_6}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_7 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_15, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_9 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_15, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_15}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_15 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_9, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_7}; // @[pla.scala:98:53] wire [7:0] bpd_csignals_decoded_andMatrixOutputs_hi_15 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_15, bpd_csignals_decoded_andMatrixOutputs_hi_lo_15}; // @[pla.scala:98:53] wire [14:0] _bpd_csignals_decoded_andMatrixOutputs_T_15 = {bpd_csignals_decoded_andMatrixOutputs_hi_15, bpd_csignals_decoded_andMatrixOutputs_lo_15}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_10_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_15; // @[pla.scala:98:{53,70}] wire [1:0] bpd_csignals_decoded_orMatrixOutputs_lo = {bpd_csignals_decoded_andMatrixOutputs_2_2, bpd_csignals_decoded_andMatrixOutputs_10_2}; // @[pla.scala:98:70, :114:19] wire [1:0] bpd_csignals_decoded_orMatrixOutputs_hi = {bpd_csignals_decoded_andMatrixOutputs_14_2, bpd_csignals_decoded_andMatrixOutputs_0_2}; // @[pla.scala:98:70, :114:19] wire [3:0] _bpd_csignals_decoded_orMatrixOutputs_T = {bpd_csignals_decoded_orMatrixOutputs_hi, bpd_csignals_decoded_orMatrixOutputs_lo}; // @[pla.scala:114:19] wire _bpd_csignals_decoded_orMatrixOutputs_T_1 = \|_bpd_csignals_decoded_orMatrixOutputs_T; // @[pla.scala:114:{19,36}] wire [1:0] bpd_csignals_decoded_orMatrixOutputs_lo_lo = {bpd_csignals_decoded_andMatrixOutputs_8_2, bpd_csignals_decoded_andMatrixOutputs_10_2}; // @[pla.scala:98:70, :114:19] wire [1:0] bpd_csignals_decoded_orMatrixOutputs_lo_hi_hi = {bpd_csignals_decoded_andMatrixOutputs_7_2, bpd_csignals_decoded_andMatrixOutputs_1_2}; // @[pla.scala:98:70, :114:19] wire [2:0] bpd_csignals_decoded_orMatrixOutputs_lo_hi = {bpd_csignals_decoded_orMatrixOutputs_lo_hi_hi, bpd_csignals_decoded_andMatrixOutputs_4_2}; // @[pla.scala:98:70, :114:19] wire [4:0] bpd_csignals_decoded_orMatrixOutputs_lo_1 = {bpd_csignals_decoded_orMatrixOutputs_lo_hi, bpd_csignals_decoded_orMatrixOutputs_lo_lo}; // @[pla.scala:114:19] wire [1:0] bpd_csignals_decoded_orMatrixOutputs_hi_lo_hi = {bpd_csignals_decoded_andMatrixOutputs_0_2, bpd_csignals_decoded_andMatrixOutputs_12_2}; // @[pla.scala:98:70, :114:19] wire [2:0] bpd_csignals_decoded_orMatrixOutputs_hi_lo = {bpd_csignals_decoded_orMatrixOutputs_hi_lo_hi, bpd_csignals_decoded_andMatrixOutputs_3_2}; // @[pla.scala:98:70, :114:19] wire [1:0] bpd_csignals_decoded_orMatrixOutputs_hi_hi_hi = {bpd_csignals_decoded_andMatrixOutputs_5_2, bpd_csignals_decoded_andMatrixOutputs_9_2}; // @[pla.scala:98:70, :114:19] wire [2:0] bpd_csignals_decoded_orMatrixOutputs_hi_hi = {bpd_csignals_decoded_orMatrixOutputs_hi_hi_hi, bpd_csignals_decoded_andMatrixOutputs_14_2}; // @[pla.scala:98:70, :114:19] wire [5:0] bpd_csignals_decoded_orMatrixOutputs_hi_1 = {bpd_csignals_decoded_orMatrixOutputs_hi_hi, bpd_csignals_decoded_orMatrixOutputs_hi_lo}; // @[pla.scala:114:19] wire [10:0] _bpd_csignals_decoded_orMatrixOutputs_T_2 = {bpd_csignals_decoded_orMatrixOutputs_hi_1, bpd_csignals_decoded_orMatrixOutputs_lo_1}; // @[pla.scala:114:19] wire _bpd_csignals_decoded_orMatrixOutputs_T_3 = \|_bpd_csignals_decoded_orMatrixOutputs_T_2; // @[pla.scala:114:{19,36}] wire [1:0] _bpd_csignals_decoded_orMatrixOutputs_T_6 = {bpd_csignals_decoded_andMatrixOutputs_6_2, bpd_csignals_decoded_andMatrixOutputs_13_2}; // @[pla.scala:98:70, :114:19] wire _bpd_csignals_decoded_orMatrixOutputs_T_7 = \|_bpd_csignals_decoded_orMatrixOutputs_T_6; // @[pla.scala:114:{19,36}] wire [1:0] bpd_csignals_decoded_orMatrixOutputs_lo_2 = {_bpd_csignals_decoded_orMatrixOutputs_T_3, _bpd_csignals_decoded_orMatrixOutputs_T_1}; // @[pla.scala:102:36, :114:36] wire [1:0] bpd_csignals_decoded_orMatrixOutputs_hi_hi_1 = {_bpd_csignals_decoded_orMatrixOutputs_T_7, _bpd_csignals_decoded_orMatrixOutputs_T_5}; // @[pla.scala:102:36, :114:36] wire [2:0] bpd_csignals_decoded_orMatrixOutputs_hi_2 = {bpd_csignals_decoded_orMatrixOutputs_hi_hi_1, _bpd_csignals_decoded_orMatrixOutputs_T_4}; // @[pla.scala:102:36, :114:36] wire [4:0] bpd_csignals_decoded_orMatrixOutputs = {bpd_csignals_decoded_orMatrixOutputs_hi_2, bpd_csignals_decoded_orMatrixOutputs_lo_2}; // @[pla.scala:102:36] wire _bpd_csignals_decoded_invMatrixOutputs_T = bpd_csignals_decoded_orMatrixOutputs[0]; // @[pla.scala:102:36, :124:31] wire _bpd_csignals_decoded_invMatrixOutputs_T_1 = bpd_csignals_decoded_orMatrixOutputs[1]; // @[pla.scala:102:36, :124:31] wire _bpd_csignals_decoded_invMatrixOutputs_T_2 = bpd_csignals_decoded_orMatrixOutputs[2]; // @[pla.scala:102:36, :124:31] wire _bpd_csignals_decoded_invMatrixOutputs_T_3 = bpd_csignals_decoded_orMatrixOutputs[3]; // @[pla.scala:102:36, :124:31] wire _bpd_csignals_decoded_invMatrixOutputs_T_4 = bpd_csignals_decoded_orMatrixOutputs[4]; // @[pla.scala:102:36, :124:31] wire [1:0] bpd_csignals_decoded_invMatrixOutputs_lo = {_bpd_csignals_decoded_invMatrixOutputs_T_1, _bpd_csignals_decoded_invMatrixOutputs_T}; // @[pla.scala:120:37, :124:31] wire [1:0] bpd_csignals_decoded_invMatrixOutputs_hi_hi = {_bpd_csignals_decoded_invMatrixOutputs_T_4, _bpd_csignals_decoded_invMatrixOutputs_T_3}; // @[pla.scala:120:37, :124:31] wire [2:0] bpd_csignals_decoded_invMatrixOutputs_hi = {bpd_csignals_decoded_invMatrixOutputs_hi_hi, _bpd_csignals_decoded_invMatrixOutputs_T_2}; // @[pla.scala:120:37, :124:31] assign bpd_csignals_decoded_invMatrixOutputs = {bpd_csignals_decoded_invMatrixOutputs_hi, bpd_csignals_decoded_invMatrixOutputs_lo}; // @[pla.scala:120:37] assign bpd_csignals_decoded = bpd_csignals_decoded_invMatrixOutputs; // @[pla.scala:81:23, :120:37] wire bpd_csignals_0 = bpd_csignals_decoded[4]; // @[pla.scala:81:23] wire cs_is_br = bpd_csignals_0; // @[Decode.scala:50:77] wire bpd_csignals_1 = bpd_csignals_decoded[3]; // @[pla.scala:81:23] wire cs_is_jal = bpd_csignals_1; // @[Decode.scala:50:77] wire bpd_csignals_2 = bpd_csignals_decoded[2]; // @[pla.scala:81:23] wire cs_is_jalr = bpd_csignals_2; // @[Decode.scala:50:77] wire bpd_csignals_3 = bpd_csignals_decoded[1]; // @[pla.scala:81:23] wire cs_is_shadowable = bpd_csignals_3; // @[Decode.scala:50:77] wire bpd_csignals_4 = bpd_csignals_decoded[0]; // @[pla.scala:81:23] wire cs_has_rs2 = bpd_csignals_4; // @[Decode.scala:50:77] wire _io_out_is_call_T = cs_is_jal \| cs_is_jalr; // @[decode.scala:689:34, :690:35, :694:32] wire [4:0] _io_out_is_call_T_1 = io_inst_0[11:7]; // @[decode.scala:623:7] wire [4:0] _io_out_is_ret_T_4 = io_inst_0[11:7]; // @[decode.scala:623:7] wire [4:0] _io_out_shadowable_T_2 = io_inst_0[11:7]; // @[decode.scala:623:7] wire _io_out_is_call_T_2 = _io_out_is_call_T_1 == 5'h1; // @[decode.scala:694:65] assign _io_out_is_call_T_3 = _io_out_is_call_T & _io_out_is_call_T_2; // @[decode.scala:694:{32,47,65}] assign io_out_is_call_0 = _io_out_is_call_T_3; // @[decode.scala:623:7, :694:47] wire [4:0] _io_out_is_ret_T = io_inst_0[19:15]; // @[decode.scala:623:7] wire [4:0] _io_out_shadowable_T_1 = io_inst_0[19:15]; // @[decode.scala:623:7] wire [4:0] _io_out_shadowable_T_7 = io_inst_0[19:15]; // @[decode.scala:623:7] wire [4:0] _io_out_is_ret_T_1 = _io_out_is_ret_T & 5'h1B; // @[decode.scala:695:51] wire _io_out_is_ret_T_2 = _io_out_is_ret_T_1 == 5'h1; // @[decode.scala:695:51] wire _io_out_is_ret_T_3 = cs_is_jalr & _io_out_is_ret_T_2; // @[decode.scala:690:35, :695:{32,51}] wire _io_out_is_ret_T_5 = _io_out_is_ret_T_4 == 5'h0; // @[decode.scala:695:90] assign _io_out_is_ret_T_6 = _io_out_is_ret_T_3 & _io_out_is_ret_T_5; // @[decode.scala:695:{32,72,90}] assign io_out_is_ret_0 = _io_out_is_ret_T_6; // @[decode.scala:623:7, :695:72] wire _io_out_target_b_imm32_T = io_inst_0[31]; // @[decode.scala:623:7] wire _io_out_target_j_imm32_T = io_inst_0[31]; // @[decode.scala:623:7] wire _io_out_sfb_offset_valid_T = io_inst_0[31]; // @[decode.scala:623:7, :710:50] wire [19:0] _io_out_target_b_imm32_T_1 = {20{_io_out_target_b_imm32_T}}; // @[consts.scala:337:{27,35}] wire _io_out_target_b_imm32_T_2 = io_inst_0[7]; // @[decode.scala:623:7] wire _br_offset_T = io_inst_0[7]; // @[decode.scala:623:7, :708:30] wire [5:0] _io_out_target_b_imm32_T_3 = io_inst_0[30:25]; // @[decode.scala:623:7] wire [5:0] _io_out_target_j_imm32_T_4 = io_inst_0[30:25]; // @[decode.scala:623:7] wire [5:0] _br_offset_T_1 = io_inst_0[30:25]; // @[decode.scala:623:7, :708:42] wire [3:0] _io_out_target_b_imm32_T_4 = io_inst_0[11:8]; // @[decode.scala:623:7] wire [3:0] _br_offset_T_2 = io_inst_0[11:8]; // @[decode.scala:623:7, :708:58] wire [4:0] io_out_target_b_imm32_lo = {_io_out_target_b_imm32_T_4, 1'h0}; // @[consts.scala:337:{22,68}] wire [20:0] io_out_target_b_imm32_hi_hi = {_io_out_target_b_imm32_T_1, _io_out_target_b_imm32_T_2}; // @[consts.scala:337:{22,27,46}] wire [26:0] io_out_target_b_imm32_hi = {io_out_target_b_imm32_hi_hi, _io_out_target_b_imm32_T_3}; // @[consts.scala:337:{22,55}] wire [31:0] io_out_target_b_imm32 = {io_out_target_b_imm32_hi, io_out_target_b_imm32_lo}; // @[consts.scala:337:22] wire [31:0] _io_out_target_T_1 = io_out_target_b_imm32; // @[consts.scala:337:22, :338:27] wire [40:0] _io_out_target_T_2 = {_io_out_target_T[39], _io_out_target_T} + {{9{_io_out_target_T_1[31]}}, _io_out_target_T_1}; // @[consts.scala:338:{10,17,27}] wire [39:0] _io_out_target_T_3 = _io_out_target_T_2[39:0]; // @[consts.scala:338:17] wire [39:0] _io_out_target_T_4 = _io_out_target_T_3; // @[consts.scala:338:17] wire [39:0] _io_out_target_T_5 = _io_out_target_T_4 & 40'hFFFFFFFFFE; // @[consts.scala:338:{17,42}] wire [39:0] _io_out_target_T_6 = _io_out_target_T_5; // @[consts.scala:338:42] wire [39:0] _io_out_target_T_7 = _io_out_target_T_6; // @[consts.scala:338:{42,52}] wire [11:0] _io_out_target_j_imm32_T_1 = {12{_io_out_target_j_imm32_T}}; // @[consts.scala:343:{27,35}] wire [7:0] _io_out_target_j_imm32_T_2 = io_inst_0[19:12]; // @[decode.scala:623:7] wire _io_out_target_j_imm32_T_3 = io_inst_0[20]; // @[decode.scala:623:7] wire [3:0] _io_out_target_j_imm32_T_5 = io_inst_0[24:21]; // @[decode.scala:623:7] wire [9:0] io_out_target_j_imm32_lo_hi = {_io_out_target_j_imm32_T_4, _io_out_target_j_imm32_T_5}; // @[consts.scala:343:{22,69,82}] wire [10:0] io_out_target_j_imm32_lo = {io_out_target_j_imm32_lo_hi, 1'h0}; // @[consts.scala:343:22] wire [19:0] io_out_target_j_imm32_hi_hi = {_io_out_target_j_imm32_T_1, _io_out_target_j_imm32_T_2}; // @[consts.scala:343:{22,27,46}] wire [20:0] io_out_target_j_imm32_hi = {io_out_target_j_imm32_hi_hi, _io_out_target_j_imm32_T_3}; // @[consts.scala:343:{22,59}] wire [31:0] io_out_target_j_imm32 = {io_out_target_j_imm32_hi, io_out_target_j_imm32_lo}; // @[consts.scala:343:22] wire [31:0] _io_out_target_T_9 = io_out_target_j_imm32; // @[consts.scala:343:22, :344:27] wire [40:0] _io_out_target_T_10 = {_io_out_target_T_8[39], _io_out_target_T_8} + {{9{_io_out_target_T_9[31]}}, _io_out_target_T_9}; // @[consts.scala:344:{10,17,27}] wire [39:0] _io_out_target_T_11 = _io_out_target_T_10[39:0]; // @[consts.scala:344:17] wire [39:0] _io_out_target_T_12 = _io_out_target_T_11; // @[consts.scala:344:17] wire [39:0] _io_out_target_T_13 = _io_out_target_T_12 & 40'hFFFFFFFFFE; // @[consts.scala:344:{17,42}] wire [39:0] _io_out_target_T_14 = _io_out_target_T_13; // @[consts.scala:344:42] wire [39:0] _io_out_target_T_15 = _io_out_target_T_14; // @[consts.scala:344:{42,52}] assign _io_out_target_T_16 = cs_is_br ? _io_out_target_T_7 : _io_out_target_T_15; // @[decode.scala:688:33, :697:23] assign io_out_target_0 = _io_out_target_T_16; // @[decode.scala:623:7, :697:23] wire [2:0] _io_out_cfi_type_T = {2'h0, cs_is_br}; // @[decode.scala:688:33, :704:8] wire [2:0] _io_out_cfi_type_T_1 = cs_is_jal ? 3'h2 : _io_out_cfi_type_T; // @[decode.scala:689:34, :702:8, :704:8] assign _io_out_cfi_type_T_2 = cs_is_jalr ? 3'h3 : _io_out_cfi_type_T_1; // @[decode.scala:690:35, :700:8, :702:8] assign io_out_cfi_type_0 = _io_out_cfi_type_T_2; // @[decode.scala:623:7, :700:8] wire [4:0] br_offset_lo = {_br_offset_T_2, 1'h0}; // @[decode.scala:708:{22,58}] wire [6:0] br_offset_hi = {_br_offset_T, _br_offset_T_1}; // @[decode.scala:708:{22,30,42}] wire [11:0] br_offset = {br_offset_hi, br_offset_lo}; // @[decode.scala:708:22] wire _io_out_sfb_offset_valid_T_1 = ~_io_out_sfb_offset_valid_T; // @[decode.scala:710:{42,50}] wire _io_out_sfb_offset_valid_T_2 = cs_is_br & _io_out_sfb_offset_valid_T_1; // @[decode.scala:688:33, :710:{39,42}] wire _io_out_sfb_offset_valid_T_3 = \|br_offset; // @[decode.scala:708:22, :710:68] wire _io_out_sfb_offset_valid_T_4 = _io_out_sfb_offset_valid_T_2 & _io_out_sfb_offset_valid_T_3; // @[decode.scala:710:{39,55,68}] wire [5:0] _io_out_sfb_offset_valid_T_5 = br_offset[11:6]; // @[decode.scala:708:22, :710:90] wire _io_out_sfb_offset_valid_T_6 = _io_out_sfb_offset_valid_T_5 == 6'h0; // @[decode.scala:710:{90,117}] assign _io_out_sfb_offset_valid_T_7 = _io_out_sfb_offset_valid_T_4 & _io_out_sfb_offset_valid_T_6; // @[decode.scala:710:{55,76,117}] assign io_out_sfb_offset_valid_0 = _io_out_sfb_offset_valid_T_7; // @[decode.scala:623:7, :710:76] assign io_out_sfb_offset_bits_0 = br_offset[5:0]; // @[decode.scala:623:7, :708:22, :711:27] wire _io_out_shadowable_T = ~cs_has_rs2; // @[decode.scala:692:35, :713:5] wire _io_out_shadowable_T_3 = _io_out_shadowable_T_1 == _io_out_shadowable_T_2; // @[decode.scala:714:22] wire _io_out_shadowable_T_4 = _io_out_shadowable_T \| _io_out_shadowable_T_3; // @[decode.scala:713:{5,17}, :714:22] wire [31:0] _io_out_shadowable_T_5 = io_inst_0 & 32'hFE00707F; // @[decode.scala:623:7, :715:14] wire _io_out_shadowable_T_6 = _io_out_shadowable_T_5 == 32'h33; // @[decode.scala:715:14] wire _io_out_shadowable_T_8 = _io_out_shadowable_T_7 == 5'h0; // @[decode.scala:695:90, :715:41] wire _io_out_shadowable_T_9 = _io_out_shadowable_T_6 & _io_out_shadowable_T_8; // @[decode.scala:715:{14,22,41}] wire _io_out_shadowable_T_10 = _io_out_shadowable_T_4 \| _io_out_shadowable_T_9; // @[decode.scala:713:17, :714:42, :715:22] assign _io_out_shadowable_T_11 = cs_is_shadowable & _io_out_shadowable_T_10; // @[decode.scala:691:41, :712:41, :714:42] assign io_out_shadowable_0 = _io_out_shadowable_T_11; // @[decode.scala:623:7, :712:41] assign io_out_is_ret = io_out_is_ret_0; // @[decode.scala:623:7] assign io_out_is_call = io_out_is_call_0; // @[decode.scala:623:7] assign io_out_target = io_out_target_0; // @[decode.scala:623:7] assign io_out_cfi_type = io_out_cfi_type_0; // @[decode.scala:623:7] assign io_out_sfb_offset_valid = io_out_sfb_offset_valid_0; // @[decode.scala:623:7] assign io_out_sfb_offset_bits = io_out_sfb_offset_bits_0; // @[decode.scala:623:7] assign io_out_shadowable = io_out_shadowable_0; // @[decode.scala:623:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Tile.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ import Util._ /** * A Tile is a purely combinational 2D array of passThrough PEs. * a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs * @param width The data width of each PE in bits * @param rows Number of PEs on each row * @param columns Number of PEs on each column */ class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module { val io = IO(new Bundle { val in_a = Input(Vec(rows, inputType)) val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it val in_d = Input(Vec(columns, outputType)) val in_control = Input(Vec(columns, new PEControl(accType))) val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val in_last = Input(Vec(columns, Bool())) val out_a = Output(Vec(rows, inputType)) val out_c = Output(Vec(columns, outputType)) val out_b = Output(Vec(columns, outputType)) val out_control = Output(Vec(columns, new PEControl(accType))) val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val out_last = Output(Vec(columns, Bool())) val in_valid = Input(Vec(columns, Bool())) val out_valid = Output(Vec(columns, Bool())) val bad_dataflow = Output(Bool()) }) import ev._ val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls))) val tileT = tile.transpose // TODO: abstract hori/vert broadcast, all these connections look the same // Broadcast 'a' horizontally across the Tile for (r <- 0 until rows) { tile(r).foldLeft(io.in_a(r)) { case (in_a, pe) => pe.io.in_a := in_a pe.io.out_a } } // Broadcast 'b' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_b(c)) { case (in_b, pe) => pe.io.in_b := (if (tree_reduction) in_b.zero else in_b) pe.io.out_b } } // Broadcast 'd' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_d(c)) { case (in_d, pe) => pe.io.in_d := in_d pe.io.out_c } } // Broadcast 'control' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_control(c)) { case (in_ctrl, pe) => pe.io.in_control := in_ctrl pe.io.out_control } } // Broadcast 'garbage' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_valid(c)) { case (v, pe) => pe.io.in_valid := v pe.io.out_valid } } // Broadcast 'id' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_id(c)) { case (id, pe) => pe.io.in_id := id pe.io.out_id } } // Broadcast 'last' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_last(c)) { case (last, pe) => pe.io.in_last := last pe.io.out_last } } // Drive the Tile's bottom IO for (c <- 0 until columns) { io.out_c(c) := tile(rows-1)(c).io.out_c io.out_control(c) := tile(rows-1)(c).io.out_control io.out_id(c) := tile(rows-1)(c).io.out_id io.out_last(c) := tile(rows-1)(c).io.out_last io.out_valid(c) := tile(rows-1)(c).io.out_valid io.out_b(c) := { if (tree_reduction) { val prods = tileT(c).map(_.io.out_b) accumulateTree(prods :+ io.in_b(c)) } else { tile(rows - 1)(c).io.out_b } } } io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_\|\|_)).reduce(_\|\|_) // Drive the Tile's right IO for (r <- 0 until rows) { io.out_a(r) := tile(r)(columns-1).io.out_a } }	module Tile_59( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0 // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] PE_315 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Crossing.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.interrupts import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg} @deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2") class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val intnode = IntAdapterNode() lazy val module = new Impl class Impl extends LazyModuleImp(this) { (intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) => out := SynchronizerShiftReg(in, sync) } } } object IntSyncCrossingSource { def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) = { val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered)) intsource.node } } class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule { val node = IntSyncSourceNode(alreadyRegistered) lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl) class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := AsyncResetReg(Cat(in.reverse)).asBools } } class ImplRegistered extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}_Registered" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := in } } } object IntSyncCrossingSink { @deprecated("IntSyncCrossingSink which used the `sync` parameter to determine crossing type is deprecated. Use IntSyncAsyncCrossingSink, IntSyncRationalCrossingSink, or IntSyncSyncCrossingSink instead for > 1, 1, and 0 sync values respectively", "rocket-chip 1.2") def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncAsyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(sync) lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = s"IntSyncAsyncCrossingSink_n${node.out.size}x${node.out.head._1.size}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := SynchronizerShiftReg(in.sync, sync) } } } object IntSyncAsyncCrossingSink { def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncSyncCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(0) lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncSyncCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := in.sync } } } object IntSyncSyncCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncSyncCrossingSink()) intsink.node } } class IntSyncRationalCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(1) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncRationalCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := RegNext(in.sync) } } } object IntSyncRationalCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncRationalCrossingSink()) intsink.node } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph / def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File AsyncResetReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ /* This black-boxes an Async Reset * (or Set) * Register. * * Because Chisel doesn't support * parameterized black boxes, * we unfortunately have to * instantiate a number of these. * * We also have to hard-code the set/ * reset behavior. * * Do not confuse an asynchronous * reset signal with an asynchronously * reset reg. You should still * properly synchronize your reset * deassertion. * * @param d Data input * @param q Data Output * @param clk Clock Input * @param rst Reset Input * @param en Write Enable Input * */ class AsyncResetReg(resetValue: Int = 0) extends RawModule { val io = IO(new Bundle { val d = Input(Bool()) val q = Output(Bool()) val en = Input(Bool()) val clk = Input(Clock()) val rst = Input(Reset()) }) val reg = withClockAndReset(io.clk, io.rst.asAsyncReset)(RegInit(resetValue.U(1.W))) when (io.en) { reg := io.d } io.q := reg } class SimpleRegIO(val w: Int) extends Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) } class AsyncResetRegVec(val w: Int, val init: BigInt) extends Module { override def desiredName = s"AsyncResetRegVec_w${w}_i${init}" val io = IO(new SimpleRegIO(w)) val reg = withReset(reset.asAsyncReset)(RegInit(init.U(w.W))) when (io.en) { reg := io.d } io.q := reg } object AsyncResetReg { // Create Single Registers def apply(d: Bool, clk: Clock, rst: Bool, init: Boolean, name: Option[String]): Bool = { val reg = Module(new AsyncResetReg(if (init) 1 else 0)) reg.io.d := d reg.io.clk := clk reg.io.rst := rst reg.io.en := true.B name.foreach(reg.suggestName(_)) reg.io.q } def apply(d: Bool, clk: Clock, rst: Bool): Bool = apply(d, clk, rst, false, None) def apply(d: Bool, clk: Clock, rst: Bool, name: String): Bool = apply(d, clk, rst, false, Some(name)) // Create Vectors of Registers def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: Option[String] = None): UInt = { val w = updateData.getWidth max resetData.bitLength val reg = Module(new AsyncResetRegVec(w, resetData)) name.foreach(reg.suggestName(_)) reg.io.d := updateData reg.io.en := enable reg.io.q } def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: String): UInt = apply(updateData, resetData, enable, Some(name)) def apply(updateData: UInt, resetData: BigInt): UInt = apply(updateData, resetData, enable = true.B) def apply(updateData: UInt, resetData: BigInt, name: String): UInt = apply(updateData, resetData, enable = true.B, Some(name)) def apply(updateData: UInt, enable: Bool): UInt = apply(updateData, resetData=BigInt(0), enable) def apply(updateData: UInt, enable: Bool, name: String): UInt = apply(updateData, resetData = BigInt(0), enable, Some(name)) def apply(updateData: UInt): UInt = apply(updateData, resetData = BigInt(0), enable = true.B) def apply(updateData: UInt, name:String): UInt = apply(updateData, resetData = BigInt(0), enable = true.B, Some(name)) }	module IntSyncCrossingSource_n1x1_36( // @[Crossing.scala:41:9] input clock, // @[Crossing.scala:41:9] input reset, // @[Crossing.scala:41:9] input auto_in_0, // @[LazyModuleImp.scala:107:25] output auto_out_sync_0 // @[LazyModuleImp.scala:107:25] ); wire auto_in_0_0 = auto_in_0; // @[Crossing.scala:41:9] wire nodeIn_0 = auto_in_0_0; // @[Crossing.scala:41:9] wire nodeOut_sync_0; // @[MixedNode.scala:542:17] wire auto_out_sync_0_0; // @[Crossing.scala:41:9] assign auto_out_sync_0_0 = nodeOut_sync_0; // @[Crossing.scala:41:9] AsyncResetRegVec_w1_i0_36 reg_0 ( // @[AsyncResetReg.scala:86:21] .clock (clock), .reset (reset), .io_d (nodeIn_0), // @[MixedNode.scala:551:17] .io_q (nodeOut_sync_0) ); // @[AsyncResetReg.scala:86:21] assign auto_out_sync_0 = auto_out_sync_0_0; // @[Crossing.scala:41:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black /, label = (ei.manager.beatBytes 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red /, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" / green /) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" / yellow /, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File RegisterRouter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes} import freechips.rocketchip.resources.{Device, Resource, ResourceBindings} import freechips.rocketchip.prci.{NoCrossing} import freechips.rocketchip.regmapper.{RegField, RegMapper, RegMapperParams, RegMapperInput, RegisterRouter} import freechips.rocketchip.util.{BundleField, ControlKey, ElaborationArtefacts, GenRegDescsAnno} import scala.math.min class TLRegisterRouterExtraBundle(val sourceBits: Int, val sizeBits: Int) extends Bundle { val source = UInt((sourceBits max 1).W) val size = UInt((sizeBits max 1).W) } case object TLRegisterRouterExtra extends ControlKey[TLRegisterRouterExtraBundle]("tlrr_extra") case class TLRegisterRouterExtraField(sourceBits: Int, sizeBits: Int) extends BundleField[TLRegisterRouterExtraBundle](TLRegisterRouterExtra, Output(new TLRegisterRouterExtraBundle(sourceBits, sizeBits)), x => { x.size := 0.U x.source := 0.U }) /* TLRegisterNode is a specialized TL SinkNode that encapsulates MMIO registers. * It provides functionality for describing and outputting metdata about the registers in several formats. * It also provides a concrete implementation of a regmap function that will be used * to wire a map of internal registers associated with this node to the node's interconnect port. / case class TLRegisterNode( address: Seq[AddressSet], device: Device, deviceKey: String = "reg/control", concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false)( implicit valName: ValName) extends SinkNode(TLImp)(Seq(TLSlavePortParameters.v1( Seq(TLSlaveParameters.v1( address = address, resources = Seq(Resource(device, deviceKey)), executable = executable, supportsGet = TransferSizes(1, beatBytes), supportsPutPartial = TransferSizes(1, beatBytes), supportsPutFull = TransferSizes(1, beatBytes), fifoId = Some(0))), // requests are handled in order beatBytes = beatBytes, minLatency = min(concurrency, 1)))) with TLFormatNode // the Queue adds at most one cycle { val size = 1 << log2Ceil(1 + address.map(_.max).max - address.map(_.base).min) require (size >= beatBytes) address.foreach { case a => require (a.widen(size-1).base == address.head.widen(size-1).base, s"TLRegisterNode addresses (${address}) must be aligned to its size ${size}") } // Calling this method causes the matching TL2 bundle to be // configured to route all requests to the listed RegFields. def regmap(mapping: RegField.Map) = { val (bundleIn, edge) = this.in(0) val a = bundleIn.a val d = bundleIn.d val fields = TLRegisterRouterExtraField(edge.bundle.sourceBits, edge.bundle.sizeBits) +: a.bits.params.echoFields val params = RegMapperParams(log2Up(size/beatBytes), beatBytes, fields) val in = Wire(Decoupled(new RegMapperInput(params))) in.bits.read := a.bits.opcode === TLMessages.Get in.bits.index := edge.addr_hi(a.bits) in.bits.data := a.bits.data in.bits.mask := a.bits.mask Connectable.waiveUnmatched(in.bits.extra, a.bits.echo) match { case (lhs, rhs) => lhs :<= rhs } val a_extra = in.bits.extra(TLRegisterRouterExtra) a_extra.source := a.bits.source a_extra.size := a.bits.size // Invoke the register map builder val out = RegMapper(beatBytes, concurrency, undefZero, in, mapping:_) // No flow control needed in.valid := a.valid a.ready := in.ready d.valid := out.valid out.ready := d.ready // We must restore the size to enable width adapters to work val d_extra = out.bits.extra(TLRegisterRouterExtra) d.bits := edge.AccessAck(toSource = d_extra.source, lgSize = d_extra.size) // avoid a Mux on the data bus by manually overriding two fields d.bits.data := out.bits.data Connectable.waiveUnmatched(d.bits.echo, out.bits.extra) match { case (lhs, rhs) => lhs :<= rhs } d.bits.opcode := Mux(out.bits.read, TLMessages.AccessAckData, TLMessages.AccessAck) // Tie off unused channels bundleIn.b.valid := false.B bundleIn.c.ready := true.B bundleIn.e.ready := true.B genRegDescsJson(mapping:_) } def genRegDescsJson(mapping: RegField.Map): Unit = { // Dump out the register map for documentation purposes. val base = address.head.base val baseHex = s"0x${base.toInt.toHexString}" val name = s"${device.describe(ResourceBindings()).name}.At${baseHex}" val json = GenRegDescsAnno.serialize(base, name, mapping:_) var suffix = 0 while( ElaborationArtefacts.contains(s"${baseHex}.${suffix}.regmap.json")) { suffix = suffix + 1 } ElaborationArtefacts.add(s"${baseHex}.${suffix}.regmap.json", json) val module = Module.currentModule.get.asInstanceOf[RawModule] GenRegDescsAnno.anno( module, base, mapping:_) } } /* Mix HasTLControlRegMap into any subclass of RegisterRouter to gain helper functions for attaching a device control register map to TileLink. * - The intended use case is that controlNode will diplomatically publish a SW-visible device's memory-mapped control registers. * - Use the clock crossing helper controlXing to externally connect controlNode to a TileLink interconnect. * - Use the mapping helper function regmap to internally fill out the space of device control registers. / trait HasTLControlRegMap { this: RegisterRouter => protected val controlNode = TLRegisterNode( address = address, device = device, deviceKey = "reg/control", concurrency = concurrency, beatBytes = beatBytes, undefZero = undefZero, executable = executable) // Externally, this helper should be used to connect the register control port to a bus val controlXing: TLInwardClockCrossingHelper = this.crossIn(controlNode) // Backwards-compatibility default node accessor with no clock crossing lazy val node: TLInwardNode = controlXing(NoCrossing) // Internally, this function should be used to populate the control port with registers protected def regmap(mapping: RegField.Map): Unit = { controlNode.regmap(mapping:_) } } File MuxLiteral.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.log2Ceil import scala.reflect.ClassTag / MuxLiteral creates a lookup table from a key to a list of values. * Unlike MuxLookup, the table keys must be exclusive literals. / object MuxLiteral { def apply[T <: Data:ClassTag](index: UInt, default: T, first: (UInt, T), rest: (UInt, T)): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[(UInt, T)]): T = MuxTable(index, default, cases.map { case (k, v) => (k.litValue, v) }) } object MuxSeq { def apply[T <: Data:ClassTag](index: UInt, default: T, first: T, rest: T): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[T]): T = MuxTable(index, default, cases.zipWithIndex.map { case (v, i) => (BigInt(i), v) }) } object MuxTable { def apply[T <: Data:ClassTag](index: UInt, default: T, first: (BigInt, T), rest: (BigInt, T)): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[(BigInt, T)]): T = { /* All keys must be >= 0 and distinct / cases.foreach { case (k, _) => require (k >= 0) } require (cases.map(_._1).distinct.size == cases.size) / Filter out any cases identical to the default / val simple = cases.filter { case (k, v) => !default.isLit \|\| !v.isLit \|\| v.litValue != default.litValue } val maxKey = (BigInt(0) +: simple.map(_._1)).max val endIndex = BigInt(1) << log2Ceil(maxKey+1) if (simple.isEmpty) { default } else if (endIndex <= 2simple.size) { /* The dense encoding case uses a Vec / val table = Array.fill(endIndex.toInt) { default } simple.foreach { case (k, v) => table(k.toInt) = v } Mux(index >= endIndex.U, default, VecInit(table)(index)) } else { / The sparse encoding case uses switch / val out = WireDefault(default) simple.foldLeft(new chisel3.util.SwitchContext(index, None, Set.empty)) { case (acc, (k, v)) => acc.is (k.U) { out := v } } out } } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /* Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph / def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File Control.scala: / * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. / package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.regmapper._ import freechips.rocketchip.tilelink._ class InclusiveCacheControl(outer: InclusiveCache, control: InclusiveCacheControlParameters)(implicit p: Parameters) extends LazyModule()(p) { val ctrlnode = TLRegisterNode( address = Seq(AddressSet(control.address, InclusiveCacheParameters.L2ControlSize-1)), device = outer.device, concurrency = 1, // Only one flush at a time (else need to track who answers) beatBytes = control.beatBytes) lazy val module = new Impl class Impl extends LazyModuleImp(this) { val io = IO(new Bundle { val flush_match = Input(Bool()) val flush_req = Decoupled(UInt(64.W)) val flush_resp = Input(Bool()) }) // Flush directive val flushInValid = RegInit(false.B) val flushInAddress = Reg(UInt(64.W)) val flushOutValid = RegInit(false.B) val flushOutReady = WireInit(init = false.B) when (flushOutReady) { flushOutValid := false.B } when (io.flush_resp) { flushOutValid := true.B } when (io.flush_req.ready) { flushInValid := false.B } io.flush_req.valid := flushInValid io.flush_req.bits := flushInAddress when (!io.flush_match && flushInValid) { flushInValid := false.B flushOutValid := true.B } val flush32 = RegField.w(32, RegWriteFn((ivalid, oready, data) => { when (oready) { flushOutReady := true.B } when (ivalid) { flushInValid := true.B } when (ivalid && !flushInValid) { flushInAddress := data << 4 } (!flushInValid, flushOutValid) }), RegFieldDesc("Flush32", "Flush the physical address equal to the 32-bit written data << 4 from the cache")) val flush64 = RegField.w(64, RegWriteFn((ivalid, oready, data) => { when (oready) { flushOutReady := true.B } when (ivalid) { flushInValid := true.B } when (ivalid && !flushInValid) { flushInAddress := data } (!flushInValid, flushOutValid) }), RegFieldDesc("Flush64", "Flush the phsyical address equal to the 64-bit written data from the cache")) // Information about the cache configuration val banksR = RegField.r(8, outer.node.edges.in.size.U, RegFieldDesc("Banks", "Number of banks in the cache", reset=Some(outer.node.edges.in.size))) val waysR = RegField.r(8, outer.cache.ways.U, RegFieldDesc("Ways", "Number of ways per bank", reset=Some(outer.cache.ways))) val lgSetsR = RegField.r(8, log2Ceil(outer.cache.sets).U, RegFieldDesc("lgSets", "Base-2 logarithm of the sets per bank", reset=Some(log2Ceil(outer.cache.sets)))) val lgBlockBytesR = RegField.r(8, log2Ceil(outer.cache.blockBytes).U, RegFieldDesc("lgBlockBytes", "Base-2 logarithm of the bytes per cache block", reset=Some(log2Ceil(outer.cache.blockBytes)))) val regmap = ctrlnode.regmap( 0x000 -> RegFieldGroup("Config", Some("Information about the Cache Configuration"), Seq(banksR, waysR, lgSetsR, lgBlockBytesR)), 0x200 -> (if (control.beatBytes >= 8) Seq(flush64) else Nil), 0x240 -> Seq(flush32) ) } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module InclusiveCacheControl( // @[Control.scala:38:9] input clock, // @[Control.scala:38:9] input reset, // @[Control.scala:38:9] output auto_ctrl_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_ctrl_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_ctrl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_ctrl_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_ctrl_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_ctrl_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [25:0] auto_ctrl_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_ctrl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_ctrl_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_ctrl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_ctrl_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_ctrl_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_ctrl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_ctrl_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_ctrl_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_ctrl_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input io_flush_match, // @[Control.scala:39:16] input io_flush_req_ready, // @[Control.scala:39:16] output io_flush_req_valid, // @[Control.scala:39:16] output [63:0] io_flush_req_bits, // @[Control.scala:39:16] input io_flush_resp // @[Control.scala:39:16] ); wire out_bits_read; // @[RegisterRouter.scala:87:24] wire [10:0] out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [8:0] in_bits_index; // @[RegisterRouter.scala:73:18] wire in_bits_read; // @[RegisterRouter.scala:73:18] wire _out_back_front_q_io_deq_valid; // @[RegisterRouter.scala:87:24] wire _out_back_front_q_io_deq_bits_read; // @[RegisterRouter.scala:87:24] wire [8:0] _out_back_front_q_io_deq_bits_index; // @[RegisterRouter.scala:87:24] wire [63:0] _out_back_front_q_io_deq_bits_data; // @[RegisterRouter.scala:87:24] wire [7:0] _out_back_front_q_io_deq_bits_mask; // @[RegisterRouter.scala:87:24] wire auto_ctrl_in_a_valid_0 = auto_ctrl_in_a_valid; // @[Control.scala:38:9] wire [2:0] auto_ctrl_in_a_bits_opcode_0 = auto_ctrl_in_a_bits_opcode; // @[Control.scala:38:9] wire [2:0] auto_ctrl_in_a_bits_param_0 = auto_ctrl_in_a_bits_param; // @[Control.scala:38:9] wire [1:0] auto_ctrl_in_a_bits_size_0 = auto_ctrl_in_a_bits_size; // @[Control.scala:38:9] wire [10:0] auto_ctrl_in_a_bits_source_0 = auto_ctrl_in_a_bits_source; // @[Control.scala:38:9] wire [25:0] auto_ctrl_in_a_bits_address_0 = auto_ctrl_in_a_bits_address; // @[Control.scala:38:9] wire [7:0] auto_ctrl_in_a_bits_mask_0 = auto_ctrl_in_a_bits_mask; // @[Control.scala:38:9] wire [63:0] auto_ctrl_in_a_bits_data_0 = auto_ctrl_in_a_bits_data; // @[Control.scala:38:9] wire auto_ctrl_in_a_bits_corrupt_0 = auto_ctrl_in_a_bits_corrupt; // @[Control.scala:38:9] wire auto_ctrl_in_d_ready_0 = auto_ctrl_in_d_ready; // @[Control.scala:38:9] wire io_flush_match_0 = io_flush_match; // @[Control.scala:38:9] wire io_flush_req_ready_0 = io_flush_req_ready; // @[Control.scala:38:9] wire io_flush_resp_0 = io_flush_resp; // @[Control.scala:38:9] wire [3:0][63:0] _GEN = '{64'h0, 64'h0, 64'h0, 64'h60A0801}; wire [8:0] out_maskMatch = 9'h1B7; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_13 = 8'h1; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_14 = 8'h1; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T = 8'h1; // @[RegisterRouter.scala:87:24] wire [11:0] out_prepend = 12'h801; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_22 = 16'h801; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_23 = 16'h801; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1 = 16'h801; // @[RegisterRouter.scala:87:24] wire [19:0] out_prepend_1 = 20'hA0801; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_31 = 24'hA0801; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_32 = 24'hA0801; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_2 = 24'hA0801; // @[RegisterRouter.scala:87:24] wire [26:0] out_prepend_2 = 27'h60A0801; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_40 = 32'h60A0801; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_41 = 32'h60A0801; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_66 = 32'h0; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_67 = 32'h0; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_1_0 = 64'h60A0801; // @[MuxLiteral.scala:49:48] wire [2:0] ctrlnodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17] wire [63:0] _out_T_53 = 64'h0; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_54 = 64'h0; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_1_1 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_1_2 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_1_3 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] ctrlnodeIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17] wire auto_ctrl_in_d_bits_sink = 1'h0; // @[Control.scala:38:9] wire auto_ctrl_in_d_bits_denied = 1'h0; // @[Control.scala:38:9] wire auto_ctrl_in_d_bits_corrupt = 1'h0; // @[Control.scala:38:9] wire ctrlnodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire ctrlnodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire ctrlnodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire _out_rifireMux_T_8 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_18 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wifireMux_T_9 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_19 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_rofireMux_T_8 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_18 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wofireMux_T_9 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_19 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T_2 = 1'h0; // @[MuxLiteral.scala:49:17] wire ctrlnodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17] wire ctrlnodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17] wire ctrlnodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17] wire [1:0] auto_ctrl_in_d_bits_param = 2'h0; // @[Control.scala:38:9] wire [1:0] ctrlnodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] ctrlnodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17] wire ctrlnodeIn_a_ready; // @[MixedNode.scala:551:17] wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire ctrlnodeIn_a_valid = auto_ctrl_in_a_valid_0; // @[Control.scala:38:9] wire [2:0] ctrlnodeIn_a_bits_opcode = auto_ctrl_in_a_bits_opcode_0; // @[Control.scala:38:9] wire [2:0] ctrlnodeIn_a_bits_param = auto_ctrl_in_a_bits_param_0; // @[Control.scala:38:9] wire [1:0] ctrlnodeIn_a_bits_size = auto_ctrl_in_a_bits_size_0; // @[Control.scala:38:9] wire [10:0] ctrlnodeIn_a_bits_source = auto_ctrl_in_a_bits_source_0; // @[Control.scala:38:9] wire [25:0] ctrlnodeIn_a_bits_address = auto_ctrl_in_a_bits_address_0; // @[Control.scala:38:9] wire [7:0] ctrlnodeIn_a_bits_mask = auto_ctrl_in_a_bits_mask_0; // @[Control.scala:38:9] wire [63:0] ctrlnodeIn_a_bits_data = auto_ctrl_in_a_bits_data_0; // @[Control.scala:38:9] wire ctrlnodeIn_a_bits_corrupt = auto_ctrl_in_a_bits_corrupt_0; // @[Control.scala:38:9] wire ctrlnodeIn_d_ready = auto_ctrl_in_d_ready_0; // @[Control.scala:38:9] wire ctrlnodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] ctrlnodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] ctrlnodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [10:0] ctrlnodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] ctrlnodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire auto_ctrl_in_a_ready_0; // @[Control.scala:38:9] wire [2:0] auto_ctrl_in_d_bits_opcode_0; // @[Control.scala:38:9] wire [1:0] auto_ctrl_in_d_bits_size_0; // @[Control.scala:38:9] wire [10:0] auto_ctrl_in_d_bits_source_0; // @[Control.scala:38:9] wire [63:0] auto_ctrl_in_d_bits_data_0; // @[Control.scala:38:9] wire auto_ctrl_in_d_valid_0; // @[Control.scala:38:9] wire io_flush_req_valid_0; // @[Control.scala:38:9] wire [63:0] io_flush_req_bits_0; // @[Control.scala:38:9] wire in_ready; // @[RegisterRouter.scala:73:18] assign auto_ctrl_in_a_ready_0 = ctrlnodeIn_a_ready; // @[Control.scala:38:9] wire in_valid = ctrlnodeIn_a_valid; // @[RegisterRouter.scala:73:18] wire [1:0] in_bits_extra_tlrr_extra_size = ctrlnodeIn_a_bits_size; // @[RegisterRouter.scala:73:18] wire [10:0] in_bits_extra_tlrr_extra_source = ctrlnodeIn_a_bits_source; // @[RegisterRouter.scala:73:18] wire [7:0] in_bits_mask = ctrlnodeIn_a_bits_mask; // @[RegisterRouter.scala:73:18] wire [63:0] in_bits_data = ctrlnodeIn_a_bits_data; // @[RegisterRouter.scala:73:18] wire out_ready = ctrlnodeIn_d_ready; // @[RegisterRouter.scala:87:24] wire out_valid; // @[RegisterRouter.scala:87:24] assign auto_ctrl_in_d_valid_0 = ctrlnodeIn_d_valid; // @[Control.scala:38:9] assign auto_ctrl_in_d_bits_opcode_0 = ctrlnodeIn_d_bits_opcode; // @[Control.scala:38:9] wire [1:0] ctrlnodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign auto_ctrl_in_d_bits_size_0 = ctrlnodeIn_d_bits_size; // @[Control.scala:38:9] wire [10:0] ctrlnodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign auto_ctrl_in_d_bits_source_0 = ctrlnodeIn_d_bits_source; // @[Control.scala:38:9] wire [63:0] out_bits_data; // @[RegisterRouter.scala:87:24] assign auto_ctrl_in_d_bits_data_0 = ctrlnodeIn_d_bits_data; // @[Control.scala:38:9] reg flushInValid; // @[Control.scala:45:33] assign io_flush_req_valid_0 = flushInValid; // @[Control.scala:38:9, :45:33] reg [63:0] flushInAddress; // @[Control.scala:46:29] assign io_flush_req_bits_0 = flushInAddress; // @[Control.scala:38:9, :46:29] reg flushOutValid; // @[Control.scala:47:33] wire flushOutReady; // @[Control.scala:48:34] wire _out_in_ready_T; // @[RegisterRouter.scala:87:24] assign ctrlnodeIn_a_ready = in_ready; // @[RegisterRouter.scala:73:18] wire _in_bits_read_T; // @[RegisterRouter.scala:74:36] wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24] wire [8:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24] wire [63:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24] wire [7:0] out_front_bits_mask = in_bits_mask; // @[RegisterRouter.scala:73:18, :87:24] wire [10:0] out_front_bits_extra_tlrr_extra_source = in_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24] wire [1:0] out_front_bits_extra_tlrr_extra_size = in_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24] assign _in_bits_read_T = ctrlnodeIn_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36] wire [22:0] _in_bits_index_T = ctrlnodeIn_a_bits_address[25:3]; // @[Edges.scala:192:34] assign in_bits_index = _in_bits_index_T[8:0]; // @[RegisterRouter.scala:73:18, :75:19] wire _out_out_valid_T; // @[RegisterRouter.scala:87:24] assign ctrlnodeIn_d_valid = out_valid; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24] wire _ctrlnodeIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25] assign ctrlnodeIn_d_bits_data = out_bits_data; // @[RegisterRouter.scala:87:24] assign ctrlnodeIn_d_bits_d_source = out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [1:0] out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign ctrlnodeIn_d_bits_d_size = out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] wire _out_front_valid_T; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_42 = out_front_bits_data; // @[RegisterRouter.scala:87:24] wire out_front_ready; // @[RegisterRouter.scala:87:24] wire out_front_valid; // @[RegisterRouter.scala:87:24] wire [8:0] out_findex = out_front_bits_index & 9'h1B7; // @[RegisterRouter.scala:87:24] wire [8:0] out_bindex = _out_back_front_q_io_deq_bits_index & 9'h1B7; // @[RegisterRouter.scala:87:24] wire _GEN_0 = out_findex == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_T; // @[RegisterRouter.scala:87:24] assign _out_T = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_T_2; // @[RegisterRouter.scala:87:24] assign _out_T_2 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_T_4; // @[RegisterRouter.scala:87:24] assign _out_T_4 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _GEN_1 = out_bindex == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_T_1; // @[RegisterRouter.scala:87:24] assign _out_T_1 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_T_3; // @[RegisterRouter.scala:87:24] assign _out_T_3 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_T_5; // @[RegisterRouter.scala:87:24] assign _out_T_5 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_0 = _out_T_1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2 = _out_T_3; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_3 = _out_T_5; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_15; // @[RegisterRouter.scala:87:24] wire out_rivalid_0; // @[RegisterRouter.scala:87:24] wire out_rivalid_1; // @[RegisterRouter.scala:87:24] wire out_rivalid_2; // @[RegisterRouter.scala:87:24] wire out_rivalid_3; // @[RegisterRouter.scala:87:24] wire out_rivalid_4; // @[RegisterRouter.scala:87:24] wire out_rivalid_5; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_16; // @[RegisterRouter.scala:87:24] wire out_wivalid_0; // @[RegisterRouter.scala:87:24] wire out_wivalid_1; // @[RegisterRouter.scala:87:24] wire out_wivalid_2; // @[RegisterRouter.scala:87:24] wire out_wivalid_3; // @[RegisterRouter.scala:87:24] wire out_wivalid_4; // @[RegisterRouter.scala:87:24] wire out_wivalid_5; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_15; // @[RegisterRouter.scala:87:24] wire out_roready_0; // @[RegisterRouter.scala:87:24] wire out_roready_1; // @[RegisterRouter.scala:87:24] wire out_roready_2; // @[RegisterRouter.scala:87:24] wire out_roready_3; // @[RegisterRouter.scala:87:24] wire out_roready_4; // @[RegisterRouter.scala:87:24] wire out_roready_5; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_16; // @[RegisterRouter.scala:87:24] wire out_woready_0; // @[RegisterRouter.scala:87:24] wire out_woready_1; // @[RegisterRouter.scala:87:24] wire out_woready_2; // @[RegisterRouter.scala:87:24] wire out_woready_3; // @[RegisterRouter.scala:87:24] wire out_woready_4; // @[RegisterRouter.scala:87:24] wire out_woready_5; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_8 = {8{_out_frontMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_9 = {8{_out_frontMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_10 = {8{_out_frontMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_11 = {8{_out_frontMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_12 = {8{_out_frontMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_13 = {8{_out_frontMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_14 = {8{_out_frontMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_15 = {8{_out_frontMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_lo = {_out_frontMask_T_9, _out_frontMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_hi = {_out_frontMask_T_11, _out_frontMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_lo = {out_frontMask_lo_hi, out_frontMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_lo = {_out_frontMask_T_13, _out_frontMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_hi = {_out_frontMask_T_15, _out_frontMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_hi = {out_frontMask_hi_hi, out_frontMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_frontMask = {out_frontMask_hi, out_frontMask_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_rimask_T_4 = out_frontMask; // @[RegisterRouter.scala:87:24] wire [63:0] _out_wimask_T_4 = out_frontMask; // @[RegisterRouter.scala:87:24] wire _out_backMask_T = _out_back_front_q_io_deq_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_1 = _out_back_front_q_io_deq_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_2 = _out_back_front_q_io_deq_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_3 = _out_back_front_q_io_deq_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_4 = _out_back_front_q_io_deq_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_5 = _out_back_front_q_io_deq_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_6 = _out_back_front_q_io_deq_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_7 = _out_back_front_q_io_deq_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_8 = {8{_out_backMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_9 = {8{_out_backMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_10 = {8{_out_backMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_11 = {8{_out_backMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_12 = {8{_out_backMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_13 = {8{_out_backMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_14 = {8{_out_backMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_15 = {8{_out_backMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_lo = {_out_backMask_T_9, _out_backMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_hi = {_out_backMask_T_11, _out_backMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_lo = {out_backMask_lo_hi, out_backMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_lo = {_out_backMask_T_13, _out_backMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_hi = {_out_backMask_T_15, _out_backMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_hi = {out_backMask_hi_hi, out_backMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_backMask = {out_backMask_hi, out_backMask_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_romask_T_4 = out_backMask; // @[RegisterRouter.scala:87:24] wire [63:0] _out_womask_T_4 = out_backMask; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire out_rimask = \|_out_rimask_T; // @[RegisterRouter.scala:87:24] wire out_wimask = &_out_wimask_T; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire out_romask = \|_out_romask_T; // @[RegisterRouter.scala:87:24] wire out_womask = &_out_womask_T; // @[RegisterRouter.scala:87:24] wire out_f_rivalid = out_rivalid_0 & out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_7 = out_f_rivalid; // @[RegisterRouter.scala:87:24] wire out_f_roready = out_roready_0 & out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_8 = out_f_roready; // @[RegisterRouter.scala:87:24] wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala:87:24] wire out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6 = _out_back_front_q_io_deq_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire _out_T_9 = ~out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_10 = ~out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_11 = ~out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_12 = ~out_womask; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire out_rimask_1 = \|_out_rimask_T_1; // @[RegisterRouter.scala:87:24] wire out_wimask_1 = &_out_wimask_T_1; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire out_romask_1 = \|_out_romask_T_1; // @[RegisterRouter.scala:87:24] wire out_womask_1 = &_out_womask_T_1; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1 = out_rivalid_1 & out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_16 = out_f_rivalid_1; // @[RegisterRouter.scala:87:24] wire out_f_roready_1 = out_roready_1 & out_romask_1; // @[RegisterRouter.scala:87:24] wire _out_T_17 = out_f_roready_1; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1 = out_wivalid_1 & out_wimask_1; // @[RegisterRouter.scala:87:24] wire out_f_woready_1 = out_woready_1 & out_womask_1; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_15 = _out_back_front_q_io_deq_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire _out_T_18 = ~out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_19 = ~out_wimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_20 = ~out_romask_1; // @[RegisterRouter.scala:87:24] wire _out_T_21 = ~out_womask_1; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_2 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_2 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire out_rimask_2 = \|_out_rimask_T_2; // @[RegisterRouter.scala:87:24] wire out_wimask_2 = &_out_wimask_T_2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_2 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_2 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire out_romask_2 = \|_out_romask_T_2; // @[RegisterRouter.scala:87:24] wire out_womask_2 = &_out_womask_T_2; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_2 = out_rivalid_2 & out_rimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_25 = out_f_rivalid_2; // @[RegisterRouter.scala:87:24] wire out_f_roready_2 = out_roready_2 & out_romask_2; // @[RegisterRouter.scala:87:24] wire _out_T_26 = out_f_roready_2; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_2 = out_wivalid_2 & out_wimask_2; // @[RegisterRouter.scala:87:24] wire out_f_woready_2 = out_woready_2 & out_womask_2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_24 = _out_back_front_q_io_deq_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire _out_T_27 = ~out_rimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_28 = ~out_wimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_29 = ~out_romask_2; // @[RegisterRouter.scala:87:24] wire _out_T_30 = ~out_womask_2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_3 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_3 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire out_rimask_3 = \|_out_rimask_T_3; // @[RegisterRouter.scala:87:24] wire out_wimask_3 = &_out_wimask_T_3; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_3 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_3 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire out_romask_3 = \|_out_romask_T_3; // @[RegisterRouter.scala:87:24] wire out_womask_3 = &_out_womask_T_3; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_3 = out_rivalid_3 & out_rimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_34 = out_f_rivalid_3; // @[RegisterRouter.scala:87:24] wire out_f_roready_3 = out_roready_3 & out_romask_3; // @[RegisterRouter.scala:87:24] wire _out_T_35 = out_f_roready_3; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_3 = out_wivalid_3 & out_wimask_3; // @[RegisterRouter.scala:87:24] wire out_f_woready_3 = out_woready_3 & out_womask_3; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_33 = _out_back_front_q_io_deq_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire _out_T_36 = ~out_rimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_37 = ~out_wimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_38 = ~out_romask_3; // @[RegisterRouter.scala:87:24] wire _out_T_39 = ~out_womask_3; // @[RegisterRouter.scala:87:24] wire out_rimask_4 = \|_out_rimask_T_4; // @[RegisterRouter.scala:87:24] wire out_wimask_4 = &_out_wimask_T_4; // @[RegisterRouter.scala:87:24] wire out_romask_4 = \|_out_romask_T_4; // @[RegisterRouter.scala:87:24] wire out_womask_4 = &_out_womask_T_4; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_4 = out_rivalid_4 & out_rimask_4; // @[RegisterRouter.scala:87:24] wire out_f_roready_4 = out_roready_4 & out_romask_4; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_4 = out_wivalid_4 & out_wimask_4; // @[RegisterRouter.scala:87:24] wire out_f_woready_4 = out_woready_4 & out_womask_4; // @[RegisterRouter.scala:87:24] wire _out_T_43 = ~flushInValid; // @[Control.scala:45:33, :71:23] wire _out_T_44 = out_f_wivalid_4 & _out_T_43; // @[RegisterRouter.scala:87:24] wire out_f_wiready = ~flushInValid; // @[Control.scala:45:33, :71:23, :72:8] wire _out_T_45 = out_f_wivalid_4 & out_f_wiready; // @[RegisterRouter.scala:87:24] wire _out_T_46 = flushOutValid & out_f_woready_4; // @[RegisterRouter.scala:87:24] wire _out_T_47 = ~out_rimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_48 = ~out_wimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_49 = out_f_wiready \| _out_T_48; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_2 = _out_T_49; // @[RegisterRouter.scala:87:24] wire _out_T_50 = ~out_romask_4; // @[RegisterRouter.scala:87:24] wire _out_T_51 = ~out_womask_4; // @[RegisterRouter.scala:87:24] wire _out_T_52 = flushOutValid \| _out_T_51; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_2 = _out_T_52; // @[RegisterRouter.scala:87:24] wire [31:0] _out_rimask_T_5 = out_frontMask[31:0]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_wimask_T_5 = out_frontMask[31:0]; // @[RegisterRouter.scala:87:24] wire out_rimask_5 = \|_out_rimask_T_5; // @[RegisterRouter.scala:87:24] wire out_wimask_5 = &_out_wimask_T_5; // @[RegisterRouter.scala:87:24] wire [31:0] _out_romask_T_5 = out_backMask[31:0]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_womask_T_5 = out_backMask[31:0]; // @[RegisterRouter.scala:87:24] wire out_romask_5 = \|_out_romask_T_5; // @[RegisterRouter.scala:87:24] wire out_womask_5 = &_out_womask_T_5; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_5 = out_rivalid_5 & out_rimask_5; // @[RegisterRouter.scala:87:24] wire out_f_roready_5 = out_roready_5 & out_romask_5; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_5 = out_wivalid_5 & out_wimask_5; // @[RegisterRouter.scala:87:24] wire out_f_woready_5 = out_woready_5 & out_womask_5; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_55 = out_front_bits_data[31:0]; // @[RegisterRouter.scala:87:24] assign flushOutReady = out_f_woready_5 \| out_f_woready_4; // @[RegisterRouter.scala:87:24] wire _out_T_56 = ~flushInValid; // @[Control.scala:45:33, :64:23, :71:23] wire _out_T_57 = out_f_wivalid_5 & _out_T_56; // @[RegisterRouter.scala:87:24] wire [35:0] _out_flushInAddress_T = {_out_T_55, 4'h0}; // @[RegisterRouter.scala:87:24] wire out_f_wiready_1 = ~flushInValid; // @[Control.scala:45:33, :65:8, :71:23] wire _out_T_58 = out_f_wivalid_5 & out_f_wiready_1; // @[RegisterRouter.scala:87:24] wire _out_T_59 = flushOutValid & out_f_woready_5; // @[RegisterRouter.scala:87:24] wire _out_T_60 = ~out_rimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_61 = ~out_wimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_62 = out_f_wiready_1 \| _out_T_61; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_3 = _out_T_62; // @[RegisterRouter.scala:87:24] wire _out_T_63 = ~out_romask_5; // @[RegisterRouter.scala:87:24] wire _out_T_64 = ~out_womask_5; // @[RegisterRouter.scala:87:24] wire _out_T_65 = flushOutValid \| _out_T_64; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_3 = _out_T_65; // @[RegisterRouter.scala:87:24] wire _out_iindex_T = out_front_bits_index[0]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_1 = out_front_bits_index[1]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_2 = out_front_bits_index[2]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_3 = out_front_bits_index[3]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_4 = out_front_bits_index[4]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_5 = out_front_bits_index[5]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_6 = out_front_bits_index[6]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_7 = out_front_bits_index[7]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_8 = out_front_bits_index[8]; // @[RegisterRouter.scala:87:24] wire [1:0] out_iindex = {_out_iindex_T_6, _out_iindex_T_3}; // @[RegisterRouter.scala:87:24] wire _out_oindex_T = _out_back_front_q_io_deq_bits_index[0]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_1 = _out_back_front_q_io_deq_bits_index[1]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_2 = _out_back_front_q_io_deq_bits_index[2]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_3 = _out_back_front_q_io_deq_bits_index[3]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_4 = _out_back_front_q_io_deq_bits_index[4]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_5 = _out_back_front_q_io_deq_bits_index[5]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_6 = _out_back_front_q_io_deq_bits_index[6]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_7 = _out_back_front_q_io_deq_bits_index[7]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_8 = _out_back_front_q_io_deq_bits_index[8]; // @[RegisterRouter.scala:87:24] wire [1:0] out_oindex = {_out_oindex_T_6, _out_oindex_T_3}; // @[RegisterRouter.scala:87:24] wire [3:0] _out_frontSel_T = 4'h1 << out_iindex; // @[OneHot.scala:58:35] wire out_frontSel_0 = _out_frontSel_T[0]; // @[OneHot.scala:58:35] wire out_frontSel_1 = _out_frontSel_T[1]; // @[OneHot.scala:58:35] wire out_frontSel_2 = _out_frontSel_T[2]; // @[OneHot.scala:58:35] wire out_frontSel_3 = _out_frontSel_T[3]; // @[OneHot.scala:58:35] wire [3:0] _out_backSel_T = 4'h1 << out_oindex; // @[OneHot.scala:58:35] wire out_backSel_0 = _out_backSel_T[0]; // @[OneHot.scala:58:35] wire out_backSel_1 = _out_backSel_T[1]; // @[OneHot.scala:58:35] wire out_backSel_2 = _out_backSel_T[2]; // @[OneHot.scala:58:35] wire out_backSel_3 = _out_backSel_T[3]; // @[OneHot.scala:58:35] wire _GEN_2 = in_valid & out_front_ready; // @[RegisterRouter.scala:73:18, :87:24] wire _out_rifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T = _GEN_2; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T = _GEN_2; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1 = _out_rifireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_2 = _out_rifireMux_T_1 & out_frontSel_0; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_3 = _out_rifireMux_T_2 & _out_T; // @[RegisterRouter.scala:87:24] assign out_rivalid_0 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_1 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_2 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_3 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_4 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_6 = _out_rifireMux_T_1 & out_frontSel_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_7 = _out_rifireMux_T_6; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_10 = _out_rifireMux_T_1 & out_frontSel_2; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_11 = _out_rifireMux_T_10 & _out_T_2; // @[RegisterRouter.scala:87:24] assign out_rivalid_4 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_12 = ~_out_T_2; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_14 = _out_rifireMux_T_1 & out_frontSel_3; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_15 = _out_rifireMux_T_14 & _out_T_4; // @[RegisterRouter.scala:87:24] assign out_rivalid_5 = _out_rifireMux_T_15; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_16 = ~_out_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_2 = _out_wifireMux_T & _out_wifireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_3 = _out_wifireMux_T_2 & out_frontSel_0; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_4 = _out_wifireMux_T_3 & _out_T; // @[RegisterRouter.scala:87:24] assign out_wivalid_0 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_1 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_2 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_3 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_5 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_7 = _out_wifireMux_T_2 & out_frontSel_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_8 = _out_wifireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_11 = _out_wifireMux_T_2 & out_frontSel_2; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_12 = _out_wifireMux_T_11 & _out_T_2; // @[RegisterRouter.scala:87:24] assign out_wivalid_4 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] wire out_wifireMux_all = _out_wifireMux_T_12 & _out_T_49; // @[ReduceOthers.scala:47:21] wire _out_wifireMux_T_13 = ~_out_T_2; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_14 = out_wifireMux_out_2 \| _out_wifireMux_T_13; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_WIRE_2 = _out_wifireMux_T_14; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_T_15 = _out_wifireMux_T_2 & out_frontSel_3; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_16 = _out_wifireMux_T_15 & _out_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_5 = _out_wifireMux_T_16; // @[RegisterRouter.scala:87:24] wire out_wifireMux_all_1 = _out_wifireMux_T_16 & _out_T_62; // @[ReduceOthers.scala:47:21] wire _out_wifireMux_T_17 = ~_out_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_18 = out_wifireMux_out_3 \| _out_wifireMux_T_17; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_WIRE_3 = _out_wifireMux_T_18; // @[MuxLiteral.scala:49:48] wire [3:0] _GEN_3 = {{_out_wifireMux_WIRE_3}, {_out_wifireMux_WIRE_2}, {1'h1}, {1'h1}}; // @[MuxLiteral.scala:49:{10,48}] wire out_wifireMux = _GEN_3[out_iindex]; // @[MuxLiteral.scala:49:10] wire _GEN_4 = _out_back_front_q_io_deq_valid & out_ready; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T = _GEN_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T = _GEN_4; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1 = _out_rofireMux_T & _out_back_front_q_io_deq_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_2 = _out_rofireMux_T_1 & out_backSel_0; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_3 = _out_rofireMux_T_2 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_roready_0 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_1 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_2 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_3 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_4 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_6 = _out_rofireMux_T_1 & out_backSel_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_7 = _out_rofireMux_T_6; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_10 = _out_rofireMux_T_1 & out_backSel_2; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_11 = _out_rofireMux_T_10 & _out_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_4 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_12 = ~_out_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_14 = _out_rofireMux_T_1 & out_backSel_3; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_15 = _out_rofireMux_T_14 & _out_T_5; // @[RegisterRouter.scala:87:24] assign out_roready_5 = _out_rofireMux_T_15; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_16 = ~_out_T_5; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1 = ~_out_back_front_q_io_deq_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_2 = _out_wofireMux_T & _out_wofireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_3 = _out_wofireMux_T_2 & out_backSel_0; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_4 = _out_wofireMux_T_3 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_woready_0 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_1 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_2 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_3 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_5 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_7 = _out_wofireMux_T_2 & out_backSel_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_8 = _out_wofireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_11 = _out_wofireMux_T_2 & out_backSel_2; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_12 = _out_wofireMux_T_11 & _out_T_3; // @[RegisterRouter.scala:87:24] assign out_woready_4 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] wire out_wofireMux_all = _out_wofireMux_T_12 & _out_T_52; // @[ReduceOthers.scala:47:21] wire _out_wofireMux_T_13 = ~_out_T_3; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_14 = out_wofireMux_out_2 \| _out_wofireMux_T_13; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_2 = _out_wofireMux_T_14; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_T_15 = _out_wofireMux_T_2 & out_backSel_3; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_16 = _out_wofireMux_T_15 & _out_T_5; // @[RegisterRouter.scala:87:24] assign out_woready_5 = _out_wofireMux_T_16; // @[RegisterRouter.scala:87:24] wire out_wofireMux_all_1 = _out_wofireMux_T_16 & _out_T_65; // @[ReduceOthers.scala:47:21] wire _out_wofireMux_T_17 = ~_out_T_5; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_18 = out_wofireMux_out_3 \| _out_wofireMux_T_17; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_3 = _out_wofireMux_T_18; // @[MuxLiteral.scala:49:48] wire [3:0] _GEN_5 = {{_out_wofireMux_WIRE_3}, {_out_wofireMux_WIRE_2}, {1'h1}, {1'h1}}; // @[MuxLiteral.scala:49:{10,48}] wire out_wofireMux = _GEN_5[out_oindex]; // @[MuxLiteral.scala:49:10] wire out_iready = out_front_bits_read \| out_wifireMux; // @[MuxLiteral.scala:49:10] wire out_oready = _out_back_front_q_io_deq_bits_read \| out_wofireMux; // @[MuxLiteral.scala:49:10] assign _out_in_ready_T = out_front_ready & out_iready; // @[RegisterRouter.scala:87:24] assign in_ready = _out_in_ready_T; // @[RegisterRouter.scala:73:18, :87:24] assign _out_front_valid_T = in_valid & out_iready; // @[RegisterRouter.scala:73:18, :87:24] assign out_front_valid = _out_front_valid_T; // @[RegisterRouter.scala:87:24] wire _out_front_q_io_deq_ready_T = out_ready & out_oready; // @[RegisterRouter.scala:87:24] assign _out_out_valid_T = _out_back_front_q_io_deq_valid & out_oready; // @[RegisterRouter.scala:87:24] assign out_valid = _out_out_valid_T; // @[RegisterRouter.scala:87:24] wire [3:0] _GEN_6 = {{_out_out_bits_data_WIRE_3}, {_out_out_bits_data_WIRE_2}, {1'h1}, {_out_out_bits_data_WIRE_0}}; // @[MuxLiteral.scala:49:{10,48}] wire _out_out_bits_data_T_1 = _GEN_6[out_oindex]; // @[MuxLiteral.scala:49:10] wire [63:0] _out_out_bits_data_T_3 = _GEN[out_oindex]; // @[MuxLiteral.scala:49:10] assign _out_out_bits_data_T_4 = _out_out_bits_data_T_1 ? _out_out_bits_data_T_3 : 64'h0; // @[MuxLiteral.scala:49:10] assign out_bits_data = _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24] assign ctrlnodeIn_d_bits_size = ctrlnodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign ctrlnodeIn_d_bits_source = ctrlnodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign ctrlnodeIn_d_bits_opcode = {2'h0, _ctrlnodeIn_d_bits_opcode_T}; // @[RegisterRouter.scala:105:{19,25}] wire _T_1 = ~io_flush_match_0 & flushInValid; // @[Control.scala:38:9, :45:33, :56:{11,27}] always @(posedge clock) begin // @[Control.scala:38:9] if (reset) begin // @[Control.scala:38:9] flushInValid <= 1'h0; // @[Control.scala:45:33] flushOutValid <= 1'h0; // @[Control.scala:47:33] end else begin // @[Control.scala:38:9] flushInValid <= out_f_wivalid_5 \| out_f_wivalid_4 \| ~(_T_1 \| io_flush_req_ready_0) & flushInValid; // @[RegisterRouter.scala:87:24] flushOutValid <= _T_1 \| io_flush_resp_0 \| ~flushOutReady & flushOutValid; // @[Control.scala:38:9, :47:33, :48:34, :50:{26,42}, :51:{26,42}, :56:{27,44}, :58:21] end if (_out_T_57) // @[Control.scala:64:20] flushInAddress <= {28'h0, _out_flushInAddress_T}; // @[Control.scala:46:29, :64:{55,63}] else if (_out_T_44) // @[Control.scala:71:20] flushInAddress <= _out_T_42; // @[RegisterRouter.scala:87:24] always @(posedge) TLMonitor_35 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (ctrlnodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (ctrlnodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (ctrlnodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (ctrlnodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (ctrlnodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (ctrlnodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (ctrlnodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (ctrlnodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (ctrlnodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (ctrlnodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (ctrlnodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (ctrlnodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (ctrlnodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_size (ctrlnodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (ctrlnodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_data (ctrlnodeIn_d_bits_data) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue1_RegMapperInput_i9_m8 out_back_front_q ( // @[RegisterRouter.scala:87:24] .clock (clock), .reset (reset), .io_enq_ready (out_front_ready), .io_enq_valid (out_front_valid), // @[RegisterRouter.scala:87:24] .io_enq_bits_read (out_front_bits_read), // @[RegisterRouter.scala:87:24] .io_enq_bits_index (out_front_bits_index), // @[RegisterRouter.scala:87:24] .io_enq_bits_data (out_front_bits_data), // @[RegisterRouter.scala:87:24] .io_enq_bits_mask (out_front_bits_mask), // @[RegisterRouter.scala:87:24] .io_enq_bits_extra_tlrr_extra_source (out_front_bits_extra_tlrr_extra_source), // @[RegisterRouter.scala:87:24] .io_enq_bits_extra_tlrr_extra_size (out_front_bits_extra_tlrr_extra_size), // @[RegisterRouter.scala:87:24] .io_deq_ready (_out_front_q_io_deq_ready_T), // @[RegisterRouter.scala:87:24] .io_deq_valid (_out_back_front_q_io_deq_valid), .io_deq_bits_read (_out_back_front_q_io_deq_bits_read), .io_deq_bits_index (_out_back_front_q_io_deq_bits_index), .io_deq_bits_data (_out_back_front_q_io_deq_bits_data), .io_deq_bits_mask (_out_back_front_q_io_deq_bits_mask), .io_deq_bits_extra_tlrr_extra_source (out_bits_extra_tlrr_extra_source), .io_deq_bits_extra_tlrr_extra_size (out_bits_extra_tlrr_extra_size) ); // @[RegisterRouter.scala:87:24] assign out_bits_read = _out_back_front_q_io_deq_bits_read; // @[RegisterRouter.scala:87:24] assign auto_ctrl_in_a_ready = auto_ctrl_in_a_ready_0; // @[Control.scala:38:9] assign auto_ctrl_in_d_valid = auto_ctrl_in_d_valid_0; // @[Control.scala:38:9] assign auto_ctrl_in_d_bits_opcode = auto_ctrl_in_d_bits_opcode_0; // @[Control.scala:38:9] assign auto_ctrl_in_d_bits_size = auto_ctrl_in_d_bits_size_0; // @[Control.scala:38:9] assign auto_ctrl_in_d_bits_source = auto_ctrl_in_d_bits_source_0; // @[Control.scala:38:9] assign auto_ctrl_in_d_bits_data = auto_ctrl_in_d_bits_data_0; // @[Control.scala:38:9] assign io_flush_req_valid = io_flush_req_valid_0; // @[Control.scala:38:9] assign io_flush_req_bits = io_flush_req_bits_0; // @[Control.scala:38:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth \| params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset \|\| !sio.sink_reset_n) \|\| !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise \|\| prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready \|\| !sio.source_reset_n \|\| reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise \|\| prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }	module AsyncValidSync_96( // @[AsyncQueue.scala:58:7] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in = 1'h1; // @[ShiftReg.scala:45:23] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_109 io_out_source_valid_0 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File MulAddRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util._ import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFN_interIo(expWidth: Int, sigWidth: Int) extends Bundle { //*** ENCODE SOME OF THESE CASES IN FEWER BITS?: val isSigNaNAny = Bool() val isNaNAOrB = Bool() val isInfA = Bool() val isZeroA = Bool() val isInfB = Bool() val isZeroB = Bool() val signProd = Bool() val isNaNC = Bool() val isInfC = Bool() val isZeroC = Bool() val sExpSum = SInt((expWidth + 2).W) val doSubMags = Bool() val CIsDominant = Bool() val CDom_CAlignDist = UInt(log2Ceil(sigWidth + 1).W) val highAlignedSigC = UInt((sigWidth + 2).W) val bit0AlignedSigC = UInt(1.W) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFNToRaw_preMul(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFNToRaw_preMul_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val mulAddA = Output(UInt(sigWidth.W)) val mulAddB = Output(UInt(sigWidth.W)) val mulAddC = Output(UInt((sigWidth * 2).W)) val toPostMul = Output(new MulAddRecFN_interIo(expWidth, sigWidth)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ //* POSSIBLE TO REDUCE THIS BY 1 OR 2 BITS? (CURRENTLY 2 BITS BETWEEN //* UNSHIFTED C AND PRODUCT): val sigSumWidth = sigWidth * 3 + 3 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val rawA = rawFloatFromRecFN(expWidth, sigWidth, io.a) val rawB = rawFloatFromRecFN(expWidth, sigWidth, io.b) val rawC = rawFloatFromRecFN(expWidth, sigWidth, io.c) val signProd = rawA.sign ^ rawB.sign ^ io.op(1) //* REVIEW THE BIAS FOR 'sExpAlignedProd': val sExpAlignedProd = rawA.sExp +& rawB.sExp + (-(BigInt(1)<<expWidth) + sigWidth + 3).S val doSubMags = signProd ^ rawC.sign ^ io.op(0) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sNatCAlignDist = sExpAlignedProd - rawC.sExp val posNatCAlignDist = sNatCAlignDist(expWidth + 1, 0) val isMinCAlign = rawA.isZero \|\| rawB.isZero \|\| (sNatCAlignDist < 0.S) val CIsDominant = ! rawC.isZero && (isMinCAlign \|\| (posNatCAlignDist <= sigWidth.U)) val CAlignDist = Mux(isMinCAlign, 0.U, Mux(posNatCAlignDist < (sigSumWidth - 1).U, posNatCAlignDist(log2Ceil(sigSumWidth) - 1, 0), (sigSumWidth - 1).U ) ) val mainAlignedSigC = (Mux(doSubMags, ~rawC.sig, rawC.sig) ## Fill(sigSumWidth - sigWidth + 2, doSubMags)).asSInt>>CAlignDist val reduced4CExtra = (orReduceBy4(rawC.sig<<((sigSumWidth - sigWidth - 1) & 3)) & lowMask( CAlignDist>>2, //* NOT NEEDED?: // (sigSumWidth + 2)>>2, (sigSumWidth - 1)>>2, (sigSumWidth - sigWidth - 1)>>2 ) ).orR val alignedSigC = Cat(mainAlignedSigC>>3, Mux(doSubMags, mainAlignedSigC(2, 0).andR && ! reduced4CExtra, mainAlignedSigC(2, 0).orR \|\| reduced4CExtra ) ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ io.mulAddA := rawA.sig io.mulAddB := rawB.sig io.mulAddC := alignedSigC(sigWidth * 2, 1) io.toPostMul.isSigNaNAny := isSigNaNRawFloat(rawA) \|\| isSigNaNRawFloat(rawB) \|\| isSigNaNRawFloat(rawC) io.toPostMul.isNaNAOrB := rawA.isNaN \|\| rawB.isNaN io.toPostMul.isInfA := rawA.isInf io.toPostMul.isZeroA := rawA.isZero io.toPostMul.isInfB := rawB.isInf io.toPostMul.isZeroB := rawB.isZero io.toPostMul.signProd := signProd io.toPostMul.isNaNC := rawC.isNaN io.toPostMul.isInfC := rawC.isInf io.toPostMul.isZeroC := rawC.isZero io.toPostMul.sExpSum := Mux(CIsDominant, rawC.sExp, sExpAlignedProd - sigWidth.S) io.toPostMul.doSubMags := doSubMags io.toPostMul.CIsDominant := CIsDominant io.toPostMul.CDom_CAlignDist := CAlignDist(log2Ceil(sigWidth + 1) - 1, 0) io.toPostMul.highAlignedSigC := alignedSigC(sigSumWidth - 1, sigWidth * 2 + 1) io.toPostMul.bit0AlignedSigC := alignedSigC(0) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFNToRaw_postMul(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFNToRaw_postMul_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val fromPreMul = Input(new MulAddRecFN_interIo(expWidth, sigWidth)) val mulAddResult = Input(UInt((sigWidth * 2 + 1).W)) val roundingMode = Input(UInt(3.W)) val invalidExc = Output(Bool()) val rawOut = Output(new RawFloat(expWidth, sigWidth + 2)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigSumWidth = sigWidth * 3 + 3 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_min = (io.roundingMode === round_min) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val opSignC = io.fromPreMul.signProd ^ io.fromPreMul.doSubMags val sigSum = Cat(Mux(io.mulAddResult(sigWidth * 2), io.fromPreMul.highAlignedSigC + 1.U, io.fromPreMul.highAlignedSigC ), io.mulAddResult(sigWidth * 2 - 1, 0), io.fromPreMul.bit0AlignedSigC ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val CDom_sign = opSignC val CDom_sExp = io.fromPreMul.sExpSum - io.fromPreMul.doSubMags.zext val CDom_absSigSum = Mux(io.fromPreMul.doSubMags, ~sigSum(sigSumWidth - 1, sigWidth + 1), 0.U(1.W) ## //*** IF GAP IS REDUCED TO 1 BIT, MUST REDUCE THIS COMPONENT TO 1 BIT TOO: io.fromPreMul.highAlignedSigC(sigWidth + 1, sigWidth) ## sigSum(sigSumWidth - 3, sigWidth + 2) ) val CDom_absSigSumExtra = Mux(io.fromPreMul.doSubMags, (~sigSum(sigWidth, 1)).orR, sigSum(sigWidth + 1, 1).orR ) val CDom_mainSig = (CDom_absSigSum<<io.fromPreMul.CDom_CAlignDist)( sigWidth * 2 + 1, sigWidth - 3) val CDom_reduced4SigExtra = (orReduceBy4(CDom_absSigSum(sigWidth - 1, 0)<<(~sigWidth & 3)) & lowMask(io.fromPreMul.CDom_CAlignDist>>2, 0, sigWidth>>2)).orR val CDom_sig = Cat(CDom_mainSig>>3, CDom_mainSig(2, 0).orR \|\| CDom_reduced4SigExtra \|\| CDom_absSigSumExtra ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val notCDom_signSigSum = sigSum(sigWidth * 2 + 3) val notCDom_absSigSum = Mux(notCDom_signSigSum, ~sigSum(sigWidth * 2 + 2, 0), sigSum(sigWidth * 2 + 2, 0) + io.fromPreMul.doSubMags ) val notCDom_reduced2AbsSigSum = orReduceBy2(notCDom_absSigSum) val notCDom_normDistReduced2 = countLeadingZeros(notCDom_reduced2AbsSigSum) val notCDom_nearNormDist = notCDom_normDistReduced2<<1 val notCDom_sExp = io.fromPreMul.sExpSum - notCDom_nearNormDist.asUInt.zext val notCDom_mainSig = (notCDom_absSigSum<<notCDom_nearNormDist)( sigWidth * 2 + 3, sigWidth - 1) val notCDom_reduced4SigExtra = (orReduceBy2( notCDom_reduced2AbsSigSum(sigWidth>>1, 0)<<((sigWidth>>1) & 1)) & lowMask(notCDom_normDistReduced2>>1, 0, (sigWidth + 2)>>2) ).orR val notCDom_sig = Cat(notCDom_mainSig>>3, notCDom_mainSig(2, 0).orR \|\| notCDom_reduced4SigExtra ) val notCDom_completeCancellation = (notCDom_sig(sigWidth + 2, sigWidth + 1) === 0.U) val notCDom_sign = Mux(notCDom_completeCancellation, roundingMode_min, io.fromPreMul.signProd ^ notCDom_signSigSum ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val notNaN_isInfProd = io.fromPreMul.isInfA \|\| io.fromPreMul.isInfB val notNaN_isInfOut = notNaN_isInfProd \|\| io.fromPreMul.isInfC val notNaN_addZeros = (io.fromPreMul.isZeroA \|\| io.fromPreMul.isZeroB) && io.fromPreMul.isZeroC io.invalidExc := io.fromPreMul.isSigNaNAny \|\| (io.fromPreMul.isInfA && io.fromPreMul.isZeroB) \|\| (io.fromPreMul.isZeroA && io.fromPreMul.isInfB) \|\| (! io.fromPreMul.isNaNAOrB && (io.fromPreMul.isInfA \|\| io.fromPreMul.isInfB) && io.fromPreMul.isInfC && io.fromPreMul.doSubMags) io.rawOut.isNaN := io.fromPreMul.isNaNAOrB \|\| io.fromPreMul.isNaNC io.rawOut.isInf := notNaN_isInfOut //*** IMPROVE?: io.rawOut.isZero := notNaN_addZeros \|\| (! io.fromPreMul.CIsDominant && notCDom_completeCancellation) io.rawOut.sign := (notNaN_isInfProd && io.fromPreMul.signProd) \|\| (io.fromPreMul.isInfC && opSignC) \|\| (notNaN_addZeros && ! roundingMode_min && io.fromPreMul.signProd && opSignC) \|\| (notNaN_addZeros && roundingMode_min && (io.fromPreMul.signProd \|\| opSignC)) \|\| (! notNaN_isInfOut && ! notNaN_addZeros && Mux(io.fromPreMul.CIsDominant, CDom_sign, notCDom_sign)) io.rawOut.sExp := Mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp) io.rawOut.sig := Mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFN(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val mulAddRecFNToRaw_preMul = Module(new MulAddRecFNToRaw_preMul(expWidth, sigWidth)) val mulAddRecFNToRaw_postMul = Module(new MulAddRecFNToRaw_postMul(expWidth, sigWidth)) mulAddRecFNToRaw_preMul.io.op := io.op mulAddRecFNToRaw_preMul.io.a := io.a mulAddRecFNToRaw_preMul.io.b := io.b mulAddRecFNToRaw_preMul.io.c := io.c val mulAddResult = (mulAddRecFNToRaw_preMul.io.mulAddA * mulAddRecFNToRaw_preMul.io.mulAddB) +& mulAddRecFNToRaw_preMul.io.mulAddC mulAddRecFNToRaw_postMul.io.fromPreMul := mulAddRecFNToRaw_preMul.io.toPostMul mulAddRecFNToRaw_postMul.io.mulAddResult := mulAddResult mulAddRecFNToRaw_postMul.io.roundingMode := io.roundingMode //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundRawFNToRecFN = Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0)) roundRawFNToRecFN.io.invalidExc := mulAddRecFNToRaw_postMul.io.invalidExc roundRawFNToRecFN.io.infiniteExc := false.B roundRawFNToRecFN.io.in := mulAddRecFNToRaw_postMul.io.rawOut roundRawFNToRecFN.io.roundingMode := io.roundingMode roundRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundRawFNToRecFN.io.out io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags }	module MulAddRecFN_e8_s24_11( // @[MulAddRecFN.scala:300:7] input [32:0] io_a, // @[MulAddRecFN.scala:303:16] input [32:0] io_b, // @[MulAddRecFN.scala:303:16] output [32:0] io_out // @[MulAddRecFN.scala:303:16] ); wire _mulAddRecFNToRaw_postMul_io_invalidExc; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_isInf; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_isZero; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_sign; // @[MulAddRecFN.scala:319:15] wire [9:0] _mulAddRecFNToRaw_postMul_io_rawOut_sExp; // @[MulAddRecFN.scala:319:15] wire [26:0] _mulAddRecFNToRaw_postMul_io_rawOut_sig; // @[MulAddRecFN.scala:319:15] wire [23:0] _mulAddRecFNToRaw_preMul_io_mulAddA; // @[MulAddRecFN.scala:317:15] wire [23:0] _mulAddRecFNToRaw_preMul_io_mulAddB; // @[MulAddRecFN.scala:317:15] wire [47:0] _mulAddRecFNToRaw_preMul_io_mulAddC; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfB; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_signProd; // @[MulAddRecFN.scala:317:15] wire [9:0] _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; // @[MulAddRecFN.scala:317:15] wire [4:0] _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist; // @[MulAddRecFN.scala:317:15] wire [25:0] _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; // @[MulAddRecFN.scala:317:15] wire [32:0] io_a_0 = io_a; // @[MulAddRecFN.scala:300:7] wire [32:0] io_b_0 = io_b; // @[MulAddRecFN.scala:300:7] wire io_detectTininess = 1'h1; // @[MulAddRecFN.scala:300:7, :303:16, :317:15, :319:15, :339:15] wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:300:7, :303:16, :319:15, :339:15] wire [32:0] io_c = 33'h0; // @[MulAddRecFN.scala:300:7, :303:16, :317:15] wire [1:0] io_op = 2'h0; // @[MulAddRecFN.scala:300:7, :303:16, :317:15] wire [32:0] io_out_0; // @[MulAddRecFN.scala:300:7] wire [4:0] io_exceptionFlags; // @[MulAddRecFN.scala:300:7] wire [47:0] _mulAddResult_T = {24'h0, _mulAddRecFNToRaw_preMul_io_mulAddA} * {24'h0, _mulAddRecFNToRaw_preMul_io_mulAddB}; // @[MulAddRecFN.scala:317:15, :327:45] wire [48:0] mulAddResult = {1'h0, _mulAddResult_T} + {1'h0, _mulAddRecFNToRaw_preMul_io_mulAddC}; // @[MulAddRecFN.scala:317:15, :327:45, :328:50] MulAddRecFNToRaw_preMul_e8_s24_11 mulAddRecFNToRaw_preMul ( // @[MulAddRecFN.scala:317:15] .io_a (io_a_0), // @[MulAddRecFN.scala:300:7] .io_b (io_b_0), // @[MulAddRecFN.scala:300:7] .io_mulAddA (_mulAddRecFNToRaw_preMul_io_mulAddA), .io_mulAddB (_mulAddRecFNToRaw_preMul_io_mulAddB), .io_mulAddC (_mulAddRecFNToRaw_preMul_io_mulAddC), .io_toPostMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny), .io_toPostMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB), .io_toPostMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA), .io_toPostMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA), .io_toPostMul_isInfB (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfB), .io_toPostMul_isZeroB (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB), .io_toPostMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd), .io_toPostMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum), .io_toPostMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags), .io_toPostMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist), .io_toPostMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC), .io_toPostMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC) ); // @[MulAddRecFN.scala:317:15] MulAddRecFNToRaw_postMul_e8_s24_11 mulAddRecFNToRaw_postMul ( // @[MulAddRecFN.scala:319:15] .io_fromPreMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isInfB (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfB), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isZeroB (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC), // @[MulAddRecFN.scala:317:15] .io_mulAddResult (mulAddResult), // @[MulAddRecFN.scala:328:50] .io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc), .io_rawOut_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN), .io_rawOut_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf), .io_rawOut_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero), .io_rawOut_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign), .io_rawOut_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp), .io_rawOut_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig) ); // @[MulAddRecFN.scala:319:15] RoundRawFNToRecFN_e8_s24_11 roundRawFNToRecFN ( // @[MulAddRecFN.scala:339:15] .io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc), // @[MulAddRecFN.scala:319:15] .io_in_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN), // @[MulAddRecFN.scala:319:15] .io_in_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf), // @[MulAddRecFN.scala:319:15] .io_in_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero), // @[MulAddRecFN.scala:319:15] .io_in_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign), // @[MulAddRecFN.scala:319:15] .io_in_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp), // @[MulAddRecFN.scala:319:15] .io_in_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig), // @[MulAddRecFN.scala:319:15] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags) ); // @[MulAddRecFN.scala:339:15] assign io_out = io_out_0; // @[MulAddRecFN.scala:300:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftRegisterPriorityQueue.scala: package compressacc import chisel3._ import chisel3.util._ import chisel3.util._ // TODO : support enq & deq at the same cycle class PriorityQueueStageIO(keyWidth: Int, value: ValueInfo) extends Bundle { val output_prev = KeyValue(keyWidth, value) val output_nxt = KeyValue(keyWidth, value) val input_prev = Flipped(KeyValue(keyWidth, value)) val input_nxt = Flipped(KeyValue(keyWidth, value)) val cmd = Flipped(Valid(UInt(1.W))) val insert_here = Input(Bool()) val cur_input_keyval = Flipped(KeyValue(keyWidth, value)) val cur_output_keyval = KeyValue(keyWidth, value) } class PriorityQueueStage(keyWidth: Int, value: ValueInfo) extends Module { val io = IO(new PriorityQueueStageIO(keyWidth, value)) dontTouch(io) val CMD_DEQ = 0.U val CMD_ENQ = 1.U val MAX_VALUE = (1 << keyWidth) - 1 val key_reg = RegInit(MAX_VALUE.U(keyWidth.W)) val value_reg = Reg(value) io.output_prev.key := key_reg io.output_prev.value := value_reg io.output_nxt.key := key_reg io.output_nxt.value := value_reg io.cur_output_keyval.key := key_reg io.cur_output_keyval.value := value_reg when (io.cmd.valid) { switch (io.cmd.bits) { is (CMD_DEQ) { key_reg := io.input_nxt.key value_reg := io.input_nxt.value } is (CMD_ENQ) { when (io.insert_here) { key_reg := io.cur_input_keyval.key value_reg := io.cur_input_keyval.value } .elsewhen (key_reg >= io.cur_input_keyval.key) { key_reg := io.input_prev.key value_reg := io.input_prev.value } .otherwise { // do nothing } } } } } object PriorityQueueStage { def apply(keyWidth: Int, v: ValueInfo): PriorityQueueStage = new PriorityQueueStage(keyWidth, v) } // TODO // - This design is not scalable as the enqued_keyval is broadcasted to all the stages // - Add pipeline registers later class PriorityQueueIO(queSize: Int, keyWidth: Int, value: ValueInfo) extends Bundle { val cnt_bits = log2Ceil(queSize+1) val counter = Output(UInt(cnt_bits.W)) val enq = Flipped(Decoupled(KeyValue(keyWidth, value))) val deq = Decoupled(KeyValue(keyWidth, value)) } class PriorityQueue(queSize: Int, keyWidth: Int, value: ValueInfo) extends Module { val keyWidthInternal = keyWidth + 1 val CMD_DEQ = 0.U val CMD_ENQ = 1.U val io = IO(new PriorityQueueIO(queSize, keyWidthInternal, value)) dontTouch(io) val MAX_VALUE = ((1 << keyWidthInternal) - 1).U val cnt_bits = log2Ceil(queSize+1) // do not consider cases where we are inserting more entries then the queSize val counter = RegInit(0.U(cnt_bits.W)) io.counter := counter val full = (counter === queSize.U) val empty = (counter === 0.U) io.deq.valid := !empty io.enq.ready := !full when (io.enq.fire) { counter := counter + 1.U } when (io.deq.fire) { counter := counter - 1.U } val cmd_valid = io.enq.valid \|\| io.deq.ready val cmd = Mux(io.enq.valid, CMD_ENQ, CMD_DEQ) assert(!(io.enq.valid && io.deq.ready)) val stages = Seq.fill(queSize)(Module(new PriorityQueueStage(keyWidthInternal, value))) for (i <- 0 until (queSize - 1)) { stages(i+1).io.input_prev <> stages(i).io.output_nxt stages(i).io.input_nxt <> stages(i+1).io.output_prev } stages(queSize-1).io.input_nxt.key := MAX_VALUE // stages(queSize-1).io.input_nxt.value := stages(queSize-1).io.input_nxt.value.symbol := 0.U // stages(queSize-1).io.input_nxt.value.child(0) := 0.U // stages(queSize-1).io.input_nxt.value.child(1) := 0.U stages(0).io.input_prev.key := io.enq.bits.key stages(0).io.input_prev.value <> io.enq.bits.value for (i <- 0 until queSize) { stages(i).io.cmd.valid := cmd_valid stages(i).io.cmd.bits := cmd stages(i).io.cur_input_keyval <> io.enq.bits } val is_large_or_equal = WireInit(VecInit(Seq.fill(queSize)(false.B))) for (i <- 0 until queSize) { is_large_or_equal(i) := (stages(i).io.cur_output_keyval.key >= io.enq.bits.key) } val is_large_or_equal_cat = Wire(UInt(queSize.W)) is_large_or_equal_cat := Cat(is_large_or_equal.reverse) val insert_here_idx = PriorityEncoder(is_large_or_equal_cat) for (i <- 0 until queSize) { when (i.U === insert_here_idx) { stages(i).io.insert_here := true.B } .otherwise { stages(i).io.insert_here := false.B } } io.deq.bits <> stages(0).io.output_prev }	module PriorityQueueStage_219( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black /, label = (ei.manager.beatBytes 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red /, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" / green /) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" / yellow /, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth \| params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset \|\| !sio.sink_reset_n) \|\| !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise \|\| prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready \|\| !sio.source_reset_n \|\| reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise \|\| prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async } File AsyncCrossing.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet, NodeHandle} import freechips.rocketchip.prci.{AsynchronousCrossing} import freechips.rocketchip.subsystem.CrossingWrapper import freechips.rocketchip.util.{AsyncQueueParams, ToAsyncBundle, FromAsyncBundle, Pow2ClockDivider, property} class TLAsyncCrossingSource(sync: Option[Int])(implicit p: Parameters) extends LazyModule { def this(x: Int)(implicit p: Parameters) = this(Some(x)) def this()(implicit p: Parameters) = this(None) val node = TLAsyncSourceNode(sync) lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = (Seq("TLAsyncCrossingSource") ++ node.in.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => val bce = edgeIn.manager.anySupportAcquireB && edgeIn.client.anySupportProbe val psync = sync.getOrElse(edgeOut.manager.async.sync) val params = edgeOut.manager.async.copy(sync = psync) out.a <> ToAsyncBundle(in.a, params) in.d <> FromAsyncBundle(out.d, psync) property.cover(in.a, "TL_ASYNC_CROSSING_SOURCE_A", "MemorySystem;;TLAsyncCrossingSource Channel A") property.cover(in.d, "TL_ASYNC_CROSSING_SOURCE_D", "MemorySystem;;TLAsyncCrossingSource Channel D") if (bce) { in.b <> FromAsyncBundle(out.b, psync) out.c <> ToAsyncBundle(in.c, params) out.e <> ToAsyncBundle(in.e, params) property.cover(in.b, "TL_ASYNC_CROSSING_SOURCE_B", "MemorySystem;;TLAsyncCrossingSource Channel B") property.cover(in.c, "TL_ASYNC_CROSSING_SOURCE_C", "MemorySystem;;TLAsyncCrossingSource Channel C") property.cover(in.e, "TL_ASYNC_CROSSING_SOURCE_E", "MemorySystem;;TLAsyncCrossingSource Channel E") } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ridx := 0.U out.c.widx := 0.U out.e.widx := 0.U } } } } class TLAsyncCrossingSink(params: AsyncQueueParams = AsyncQueueParams())(implicit p: Parameters) extends LazyModule { val node = TLAsyncSinkNode(params) lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = (Seq("TLAsyncCrossingSink") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => val bce = edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe out.a <> FromAsyncBundle(in.a, params.sync) in.d <> ToAsyncBundle(out.d, params) property.cover(out.a, "TL_ASYNC_CROSSING_SINK_A", "MemorySystem;;TLAsyncCrossingSink Channel A") property.cover(out.d, "TL_ASYNC_CROSSING_SINK_D", "MemorySystem;;TLAsyncCrossingSink Channel D") if (bce) { in.b <> ToAsyncBundle(out.b, params) out.c <> FromAsyncBundle(in.c, params.sync) out.e <> FromAsyncBundle(in.e, params.sync) property.cover(out.b, "TL_ASYNC_CROSSING_SINK_B", "MemorySystem;;TLAsyncCrossingSinkChannel B") property.cover(out.c, "TL_ASYNC_CROSSING_SINK_C", "MemorySystem;;TLAsyncCrossingSink Channel C") property.cover(out.e, "TL_ASYNC_CROSSING_SINK_E", "MemorySystem;;TLAsyncCrossingSink Channel E") } else { in.b.widx := 0.U in.c.ridx := 0.U in.e.ridx := 0.U out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLAsyncCrossingSource { def apply()(implicit p: Parameters): TLAsyncSourceNode = apply(None) def apply(sync: Int)(implicit p: Parameters): TLAsyncSourceNode = apply(Some(sync)) def apply(sync: Option[Int])(implicit p: Parameters): TLAsyncSourceNode = { val asource = LazyModule(new TLAsyncCrossingSource(sync)) asource.node } } object TLAsyncCrossingSink { def apply(params: AsyncQueueParams = AsyncQueueParams())(implicit p: Parameters) = { val asink = LazyModule(new TLAsyncCrossingSink(params)) asink.node } } @deprecated("TLAsyncCrossing is fragile. Use TLAsyncCrossingSource and TLAsyncCrossingSink", "rocket-chip 1.2") class TLAsyncCrossing(params: AsyncQueueParams = AsyncQueueParams())(implicit p: Parameters) extends LazyModule { val source = LazyModule(new TLAsyncCrossingSource()) val sink = LazyModule(new TLAsyncCrossingSink(params)) val node = NodeHandle(source.node, sink.node) sink.node := source.node lazy val module = new Impl class Impl extends LazyModuleImp(this) { val io = IO(new Bundle { val in_clock = Input(Clock()) val in_reset = Input(Bool()) val out_clock = Input(Clock()) val out_reset = Input(Bool()) }) source.module.clock := io.in_clock source.module.reset := io.in_reset sink.module.clock := io.out_clock sink.module.reset := io.out_reset } } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMAsyncCrossing(txns: Int, params: AsynchronousCrossing = AsynchronousCrossing())(implicit p: Parameters) extends LazyModule { val model = LazyModule(new TLRAMModel("AsyncCrossing")) val fuzz = LazyModule(new TLFuzzer(txns)) val island = LazyModule(new CrossingWrapper(params)) val ram = island { LazyModule(new TLRAM(AddressSet(0x0, 0x3ff))) } island.crossTLIn(ram.node) := TLFragmenter(4, 256) := TLDelayer(0.1) := model.node := fuzz.node lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished // Shove the RAM into another clock domain val clocks = Module(new Pow2ClockDivider(2)) island.module.clock := clocks.io.clock_out } } class TLRAMAsyncCrossingTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut_wide = Module(LazyModule(new TLRAMAsyncCrossing(txns)).module) val dut_narrow = Module(LazyModule(new TLRAMAsyncCrossing(txns, AsynchronousCrossing(safe = false, narrow = true))).module) io.finished := dut_wide.io.finished && dut_narrow.io.finished dut_wide.io.start := io.start dut_narrow.io.start := io.start } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /* Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } }	module TLAsyncCrossingSource_a9d32s1k1z2u( // @[AsyncCrossing.scala:23:9] input clock, // @[AsyncCrossing.scala:23:9] input reset, // @[AsyncCrossing.scala:23:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [8:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [31:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_mem_0_opcode, // @[LazyModuleImp.scala:107:25] output [8:0] auto_out_a_mem_0_address, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_mem_0_data, // @[LazyModuleImp.scala:107:25] input auto_out_a_ridx, // @[LazyModuleImp.scala:107:25] output auto_out_a_widx, // @[LazyModuleImp.scala:107:25] input auto_out_a_safe_ridx_valid, // @[LazyModuleImp.scala:107:25] output auto_out_a_safe_widx_valid, // @[LazyModuleImp.scala:107:25] output auto_out_a_safe_source_reset_n, // @[LazyModuleImp.scala:107:25] input auto_out_a_safe_sink_reset_n, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_mem_0_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_mem_0_size, // @[LazyModuleImp.scala:107:25] input auto_out_d_mem_0_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_out_d_mem_0_data, // @[LazyModuleImp.scala:107:25] output auto_out_d_ridx, // @[LazyModuleImp.scala:107:25] input auto_out_d_widx, // @[LazyModuleImp.scala:107:25] output auto_out_d_safe_ridx_valid, // @[LazyModuleImp.scala:107:25] input auto_out_d_safe_widx_valid, // @[LazyModuleImp.scala:107:25] input auto_out_d_safe_source_reset_n, // @[LazyModuleImp.scala:107:25] output auto_out_d_safe_sink_reset_n // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[AsyncCrossing.scala:23:9] wire [8:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[AsyncCrossing.scala:23:9] wire [31:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[AsyncCrossing.scala:23:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[AsyncCrossing.scala:23:9] wire auto_out_a_ridx_0 = auto_out_a_ridx; // @[AsyncCrossing.scala:23:9] wire auto_out_a_safe_ridx_valid_0 = auto_out_a_safe_ridx_valid; // @[AsyncCrossing.scala:23:9] wire auto_out_a_safe_sink_reset_n_0 = auto_out_a_safe_sink_reset_n; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_out_d_mem_0_opcode_0 = auto_out_d_mem_0_opcode; // @[AsyncCrossing.scala:23:9] wire [1:0] auto_out_d_mem_0_size_0 = auto_out_d_mem_0_size; // @[AsyncCrossing.scala:23:9] wire auto_out_d_mem_0_source_0 = auto_out_d_mem_0_source; // @[AsyncCrossing.scala:23:9] wire [31:0] auto_out_d_mem_0_data_0 = auto_out_d_mem_0_data; // @[AsyncCrossing.scala:23:9] wire auto_out_d_widx_0 = auto_out_d_widx; // @[AsyncCrossing.scala:23:9] wire auto_out_d_safe_widx_valid_0 = auto_out_d_safe_widx_valid; // @[AsyncCrossing.scala:23:9] wire auto_out_d_safe_source_reset_n_0 = auto_out_d_safe_source_reset_n; // @[AsyncCrossing.scala:23:9] wire [31:0] auto_out_b_mem_0_data = 32'h0; // @[AsyncCrossing.scala:23:9] wire [31:0] auto_out_c_mem_0_data = 32'h0; // @[AsyncCrossing.scala:23:9] wire [31:0] nodeOut_b_mem_0_data = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_c_mem_0_data = 32'h0; // @[MixedNode.scala:542:17] wire [3:0] auto_out_b_mem_0_mask = 4'h0; // @[AsyncCrossing.scala:23:9] wire [3:0] nodeOut_b_mem_0_mask = 4'h0; // @[AsyncCrossing.scala:23:9] wire [8:0] auto_out_b_mem_0_address = 9'h0; // @[AsyncCrossing.scala:23:9] wire [8:0] auto_out_c_mem_0_address = 9'h0; // @[AsyncCrossing.scala:23:9] wire [8:0] nodeOut_b_mem_0_address = 9'h0; // @[MixedNode.scala:542:17] wire [8:0] nodeOut_c_mem_0_address = 9'h0; // @[MixedNode.scala:542:17] wire [1:0] auto_out_b_mem_0_param = 2'h0; // @[AsyncCrossing.scala:23:9] wire [1:0] auto_out_b_mem_0_size = 2'h0; // @[AsyncCrossing.scala:23:9] wire [1:0] auto_out_c_mem_0_size = 2'h0; // @[AsyncCrossing.scala:23:9] wire [1:0] auto_out_d_mem_0_param = 2'h0; // @[AsyncCrossing.scala:23:9] wire [1:0] nodeOut_b_mem_0_param = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_b_mem_0_size = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_c_mem_0_size = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_d_mem_0_param = 2'h0; // @[MixedNode.scala:542:17] wire [3:0] auto_in_a_bits_mask = 4'hF; // @[AsyncCrossing.scala:23:9] wire [3:0] auto_out_a_mem_0_mask = 4'hF; // @[AsyncCrossing.scala:23:9] wire [3:0] nodeIn_a_bits_mask = 4'hF; // @[MixedNode.scala:551:17] wire [3:0] nodeOut_a_mem_0_mask = 4'hF; // @[MixedNode.scala:542:17] wire auto_in_a_bits_source = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_in_a_bits_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_a_mem_0_source = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_a_mem_0_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_mem_0_source = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_mem_0_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_ridx = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_widx = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_safe_ridx_valid = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_safe_widx_valid = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_safe_source_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_safe_sink_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_mem_0_source = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_mem_0_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_ridx = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_widx = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_safe_ridx_valid = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_safe_widx_valid = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_safe_source_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_safe_sink_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_d_mem_0_sink = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_d_mem_0_denied = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_d_mem_0_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_e_mem_0_sink = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_e_ridx = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_e_widx = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_e_safe_ridx_valid = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_e_safe_widx_valid = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_e_safe_source_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_e_safe_sink_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9] wire nodeIn_a_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire nodeOut_a_mem_0_source = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_a_mem_0_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_mem_0_source = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_mem_0_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_ridx = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_widx = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_safe_ridx_valid = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_safe_widx_valid = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_safe_source_reset_n = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_safe_sink_reset_n = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_mem_0_source = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_mem_0_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_ridx = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_widx = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_safe_ridx_valid = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_safe_widx_valid = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_safe_source_reset_n = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_safe_sink_reset_n = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_d_mem_0_sink = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_d_mem_0_denied = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_d_mem_0_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_e_mem_0_sink = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_e_ridx = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_e_widx = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_e_safe_ridx_valid = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_e_safe_widx_valid = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_e_safe_source_reset_n = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_e_safe_sink_reset_n = 1'h0; // @[MixedNode.scala:542:17] wire [1:0] auto_in_a_bits_size = 2'h2; // @[AsyncCrossing.scala:23:9] wire [1:0] auto_out_a_mem_0_size = 2'h2; // @[AsyncCrossing.scala:23:9] wire [1:0] nodeIn_a_bits_size = 2'h2; // @[MixedNode.scala:551:17] wire [1:0] nodeOut_a_mem_0_size = 2'h2; // @[MixedNode.scala:542:17] wire [2:0] auto_in_a_bits_param = 3'h0; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_out_a_mem_0_param = 3'h0; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_out_b_mem_0_opcode = 3'h0; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_out_c_mem_0_opcode = 3'h0; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_out_c_mem_0_param = 3'h0; // @[AsyncCrossing.scala:23:9] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_a_bits_param = 3'h0; // @[MixedNode.scala:551:17] wire [2:0] nodeOut_a_mem_0_param = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_b_mem_0_opcode = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_mem_0_opcode = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_mem_0_param = 3'h0; // @[MixedNode.scala:542:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[AsyncCrossing.scala:23:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[AsyncCrossing.scala:23:9] wire [8:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[AsyncCrossing.scala:23:9] wire [31:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[AsyncCrossing.scala:23:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[AsyncCrossing.scala:23:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [31:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [2:0] nodeOut_a_mem_0_opcode; // @[MixedNode.scala:542:17] wire [8:0] nodeOut_a_mem_0_address; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_mem_0_data; // @[MixedNode.scala:542:17] wire nodeOut_a_ridx = auto_out_a_ridx_0; // @[AsyncCrossing.scala:23:9] wire nodeOut_a_widx; // @[MixedNode.scala:542:17] wire nodeOut_a_safe_ridx_valid = auto_out_a_safe_ridx_valid_0; // @[AsyncCrossing.scala:23:9] wire nodeOut_a_safe_widx_valid; // @[MixedNode.scala:542:17] wire nodeOut_a_safe_source_reset_n; // @[MixedNode.scala:542:17] wire nodeOut_a_safe_sink_reset_n = auto_out_a_safe_sink_reset_n_0; // @[AsyncCrossing.scala:23:9] wire [2:0] nodeOut_d_mem_0_opcode = auto_out_d_mem_0_opcode_0; // @[AsyncCrossing.scala:23:9] wire [1:0] nodeOut_d_mem_0_size = auto_out_d_mem_0_size_0; // @[AsyncCrossing.scala:23:9] wire nodeOut_d_mem_0_source = auto_out_d_mem_0_source_0; // @[AsyncCrossing.scala:23:9] wire [31:0] nodeOut_d_mem_0_data = auto_out_d_mem_0_data_0; // @[AsyncCrossing.scala:23:9] wire nodeOut_d_ridx; // @[MixedNode.scala:542:17] wire nodeOut_d_widx = auto_out_d_widx_0; // @[AsyncCrossing.scala:23:9] wire nodeOut_d_safe_ridx_valid; // @[MixedNode.scala:542:17] wire nodeOut_d_safe_widx_valid = auto_out_d_safe_widx_valid_0; // @[AsyncCrossing.scala:23:9] wire nodeOut_d_safe_source_reset_n = auto_out_d_safe_source_reset_n_0; // @[AsyncCrossing.scala:23:9] wire nodeOut_d_safe_sink_reset_n; // @[MixedNode.scala:542:17] wire auto_in_a_ready_0; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_in_d_bits_opcode_0; // @[AsyncCrossing.scala:23:9] wire [1:0] auto_in_d_bits_param_0; // @[AsyncCrossing.scala:23:9] wire [1:0] auto_in_d_bits_size_0; // @[AsyncCrossing.scala:23:9] wire auto_in_d_bits_source_0; // @[AsyncCrossing.scala:23:9] wire auto_in_d_bits_sink_0; // @[AsyncCrossing.scala:23:9] wire auto_in_d_bits_denied_0; // @[AsyncCrossing.scala:23:9] wire [31:0] auto_in_d_bits_data_0; // @[AsyncCrossing.scala:23:9] wire auto_in_d_bits_corrupt_0; // @[AsyncCrossing.scala:23:9] wire auto_in_d_valid_0; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_out_a_mem_0_opcode_0; // @[AsyncCrossing.scala:23:9] wire [8:0] auto_out_a_mem_0_address_0; // @[AsyncCrossing.scala:23:9] wire [31:0] auto_out_a_mem_0_data_0; // @[AsyncCrossing.scala:23:9] wire auto_out_a_safe_widx_valid_0; // @[AsyncCrossing.scala:23:9] wire auto_out_a_safe_source_reset_n_0; // @[AsyncCrossing.scala:23:9] wire auto_out_a_widx_0; // @[AsyncCrossing.scala:23:9] wire auto_out_d_safe_ridx_valid_0; // @[AsyncCrossing.scala:23:9] wire auto_out_d_safe_sink_reset_n_0; // @[AsyncCrossing.scala:23:9] wire auto_out_d_ridx_0; // @[AsyncCrossing.scala:23:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[AsyncCrossing.scala:23:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[AsyncCrossing.scala:23:9] assign auto_out_a_mem_0_opcode_0 = nodeOut_a_mem_0_opcode; // @[AsyncCrossing.scala:23:9] assign auto_out_a_mem_0_address_0 = nodeOut_a_mem_0_address; // @[AsyncCrossing.scala:23:9] assign auto_out_a_mem_0_data_0 = nodeOut_a_mem_0_data; // @[AsyncCrossing.scala:23:9] assign auto_out_a_widx_0 = nodeOut_a_widx; // @[AsyncCrossing.scala:23:9] assign auto_out_a_safe_widx_valid_0 = nodeOut_a_safe_widx_valid; // @[AsyncCrossing.scala:23:9] assign auto_out_a_safe_source_reset_n_0 = nodeOut_a_safe_source_reset_n; // @[AsyncCrossing.scala:23:9] assign auto_out_d_ridx_0 = nodeOut_d_ridx; // @[AsyncCrossing.scala:23:9] assign auto_out_d_safe_ridx_valid_0 = nodeOut_d_safe_ridx_valid; // @[AsyncCrossing.scala:23:9] assign auto_out_d_safe_sink_reset_n_0 = nodeOut_d_safe_sink_reset_n; // @[AsyncCrossing.scala:23:9] TLMonitor_52 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] AsyncQueueSource_TLBundleA_a9d32s1k1z2u nodeOut_a_source ( // @[AsyncQueue.scala:220:24] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_async_mem_0_opcode (nodeOut_a_mem_0_opcode), .io_async_mem_0_address (nodeOut_a_mem_0_address), .io_async_mem_0_data (nodeOut_a_mem_0_data), .io_async_ridx (nodeOut_a_ridx), // @[MixedNode.scala:542:17] .io_async_widx (nodeOut_a_widx), .io_async_safe_ridx_valid (nodeOut_a_safe_ridx_valid), // @[MixedNode.scala:542:17] .io_async_safe_widx_valid (nodeOut_a_safe_widx_valid), .io_async_safe_source_reset_n (nodeOut_a_safe_source_reset_n), .io_async_safe_sink_reset_n (nodeOut_a_safe_sink_reset_n) // @[MixedNode.scala:542:17] ); // @[AsyncQueue.scala:220:24] AsyncQueueSink_TLBundleD_a9d32s1k1z2u nodeIn_d_sink ( // @[AsyncQueue.scala:211:22] .clock (clock), .reset (reset), .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt), .io_async_mem_0_opcode (nodeOut_d_mem_0_opcode), // @[MixedNode.scala:542:17] .io_async_mem_0_size (nodeOut_d_mem_0_size), // @[MixedNode.scala:542:17] .io_async_mem_0_source (nodeOut_d_mem_0_source), // @[MixedNode.scala:542:17] .io_async_mem_0_data (nodeOut_d_mem_0_data), // @[MixedNode.scala:542:17] .io_async_ridx (nodeOut_d_ridx), .io_async_widx (nodeOut_d_widx), // @[MixedNode.scala:542:17] .io_async_safe_ridx_valid (nodeOut_d_safe_ridx_valid), .io_async_safe_widx_valid (nodeOut_d_safe_widx_valid), // @[MixedNode.scala:542:17] .io_async_safe_source_reset_n (nodeOut_d_safe_source_reset_n), // @[MixedNode.scala:542:17] .io_async_safe_sink_reset_n (nodeOut_d_safe_sink_reset_n) ); // @[AsyncQueue.scala:211:22] assign auto_in_a_ready = auto_in_a_ready_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[AsyncCrossing.scala:23:9] assign auto_out_a_mem_0_opcode = auto_out_a_mem_0_opcode_0; // @[AsyncCrossing.scala:23:9] assign auto_out_a_mem_0_address = auto_out_a_mem_0_address_0; // @[AsyncCrossing.scala:23:9] assign auto_out_a_mem_0_data = auto_out_a_mem_0_data_0; // @[AsyncCrossing.scala:23:9] assign auto_out_a_widx = auto_out_a_widx_0; // @[AsyncCrossing.scala:23:9] assign auto_out_a_safe_widx_valid = auto_out_a_safe_widx_valid_0; // @[AsyncCrossing.scala:23:9] assign auto_out_a_safe_source_reset_n = auto_out_a_safe_source_reset_n_0; // @[AsyncCrossing.scala:23:9] assign auto_out_d_ridx = auto_out_d_ridx_0; // @[AsyncCrossing.scala:23:9] assign auto_out_d_safe_ridx_valid = auto_out_d_safe_ridx_valid_0; // @[AsyncCrossing.scala:23:9] assign auto_out_d_safe_sink_reset_n = auto_out_d_safe_sink_reset_n_0; // @[AsyncCrossing.scala:23:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File primitives.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object lowMask { def apply(in: UInt, topBound: BigInt, bottomBound: BigInt): UInt = { require(topBound != bottomBound) val numInVals = BigInt(1)<<in.getWidth if (topBound < bottomBound) { lowMask(~in, numInVals - 1 - topBound, numInVals - 1 - bottomBound) } else if (numInVals > 64 /* Empirical /) { // For simulation performance, we should avoid generating // exteremely wide shifters, so we divide and conquer. // Empirically, this does not impact synthesis QoR. val mid = numInVals / 2 val msb = in(in.getWidth - 1) val lsbs = in(in.getWidth - 2, 0) if (mid < topBound) { if (mid <= bottomBound) { Mux(msb, lowMask(lsbs, topBound - mid, bottomBound - mid), 0.U ) } else { Mux(msb, lowMask(lsbs, topBound - mid, 0) ## ((BigInt(1)<<(mid - bottomBound).toInt) - 1).U, lowMask(lsbs, mid, bottomBound) ) } } else { ~Mux(msb, 0.U, ~lowMask(lsbs, topBound, bottomBound)) } } else { val shift = (BigInt(-1)<<numInVals.toInt).S>>in Reverse( shift( (numInVals - 1 - bottomBound).toInt, (numInVals - topBound).toInt ) ) } } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object countLeadingZeros { def apply(in: UInt): UInt = PriorityEncoder(in.asBools.reverse) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy2 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 1)>>1 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix 2 + 1, ix * 2).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 2).orR reducedVec.asUInt } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy4 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 3)>>2 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 4 + 3, ix * 4).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 4).orR reducedVec.asUInt } } File MulAddRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util._ import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFN_interIo(expWidth: Int, sigWidth: Int) extends Bundle { //*** ENCODE SOME OF THESE CASES IN FEWER BITS?: val isSigNaNAny = Bool() val isNaNAOrB = Bool() val isInfA = Bool() val isZeroA = Bool() val isInfB = Bool() val isZeroB = Bool() val signProd = Bool() val isNaNC = Bool() val isInfC = Bool() val isZeroC = Bool() val sExpSum = SInt((expWidth + 2).W) val doSubMags = Bool() val CIsDominant = Bool() val CDom_CAlignDist = UInt(log2Ceil(sigWidth + 1).W) val highAlignedSigC = UInt((sigWidth + 2).W) val bit0AlignedSigC = UInt(1.W) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFNToRaw_preMul(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFNToRaw_preMul_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val mulAddA = Output(UInt(sigWidth.W)) val mulAddB = Output(UInt(sigWidth.W)) val mulAddC = Output(UInt((sigWidth * 2).W)) val toPostMul = Output(new MulAddRecFN_interIo(expWidth, sigWidth)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ //* POSSIBLE TO REDUCE THIS BY 1 OR 2 BITS? (CURRENTLY 2 BITS BETWEEN //* UNSHIFTED C AND PRODUCT): val sigSumWidth = sigWidth * 3 + 3 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val rawA = rawFloatFromRecFN(expWidth, sigWidth, io.a) val rawB = rawFloatFromRecFN(expWidth, sigWidth, io.b) val rawC = rawFloatFromRecFN(expWidth, sigWidth, io.c) val signProd = rawA.sign ^ rawB.sign ^ io.op(1) //* REVIEW THE BIAS FOR 'sExpAlignedProd': val sExpAlignedProd = rawA.sExp +& rawB.sExp + (-(BigInt(1)<<expWidth) + sigWidth + 3).S val doSubMags = signProd ^ rawC.sign ^ io.op(0) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sNatCAlignDist = sExpAlignedProd - rawC.sExp val posNatCAlignDist = sNatCAlignDist(expWidth + 1, 0) val isMinCAlign = rawA.isZero \|\| rawB.isZero \|\| (sNatCAlignDist < 0.S) val CIsDominant = ! rawC.isZero && (isMinCAlign \|\| (posNatCAlignDist <= sigWidth.U)) val CAlignDist = Mux(isMinCAlign, 0.U, Mux(posNatCAlignDist < (sigSumWidth - 1).U, posNatCAlignDist(log2Ceil(sigSumWidth) - 1, 0), (sigSumWidth - 1).U ) ) val mainAlignedSigC = (Mux(doSubMags, ~rawC.sig, rawC.sig) ## Fill(sigSumWidth - sigWidth + 2, doSubMags)).asSInt>>CAlignDist val reduced4CExtra = (orReduceBy4(rawC.sig<<((sigSumWidth - sigWidth - 1) & 3)) & lowMask( CAlignDist>>2, //* NOT NEEDED?: // (sigSumWidth + 2)>>2, (sigSumWidth - 1)>>2, (sigSumWidth - sigWidth - 1)>>2 ) ).orR val alignedSigC = Cat(mainAlignedSigC>>3, Mux(doSubMags, mainAlignedSigC(2, 0).andR && ! reduced4CExtra, mainAlignedSigC(2, 0).orR \|\| reduced4CExtra ) ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ io.mulAddA := rawA.sig io.mulAddB := rawB.sig io.mulAddC := alignedSigC(sigWidth * 2, 1) io.toPostMul.isSigNaNAny := isSigNaNRawFloat(rawA) \|\| isSigNaNRawFloat(rawB) \|\| isSigNaNRawFloat(rawC) io.toPostMul.isNaNAOrB := rawA.isNaN \|\| rawB.isNaN io.toPostMul.isInfA := rawA.isInf io.toPostMul.isZeroA := rawA.isZero io.toPostMul.isInfB := rawB.isInf io.toPostMul.isZeroB := rawB.isZero io.toPostMul.signProd := signProd io.toPostMul.isNaNC := rawC.isNaN io.toPostMul.isInfC := rawC.isInf io.toPostMul.isZeroC := rawC.isZero io.toPostMul.sExpSum := Mux(CIsDominant, rawC.sExp, sExpAlignedProd - sigWidth.S) io.toPostMul.doSubMags := doSubMags io.toPostMul.CIsDominant := CIsDominant io.toPostMul.CDom_CAlignDist := CAlignDist(log2Ceil(sigWidth + 1) - 1, 0) io.toPostMul.highAlignedSigC := alignedSigC(sigSumWidth - 1, sigWidth * 2 + 1) io.toPostMul.bit0AlignedSigC := alignedSigC(0) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFNToRaw_postMul(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFNToRaw_postMul_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val fromPreMul = Input(new MulAddRecFN_interIo(expWidth, sigWidth)) val mulAddResult = Input(UInt((sigWidth * 2 + 1).W)) val roundingMode = Input(UInt(3.W)) val invalidExc = Output(Bool()) val rawOut = Output(new RawFloat(expWidth, sigWidth + 2)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigSumWidth = sigWidth * 3 + 3 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_min = (io.roundingMode === round_min) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val opSignC = io.fromPreMul.signProd ^ io.fromPreMul.doSubMags val sigSum = Cat(Mux(io.mulAddResult(sigWidth * 2), io.fromPreMul.highAlignedSigC + 1.U, io.fromPreMul.highAlignedSigC ), io.mulAddResult(sigWidth * 2 - 1, 0), io.fromPreMul.bit0AlignedSigC ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val CDom_sign = opSignC val CDom_sExp = io.fromPreMul.sExpSum - io.fromPreMul.doSubMags.zext val CDom_absSigSum = Mux(io.fromPreMul.doSubMags, ~sigSum(sigSumWidth - 1, sigWidth + 1), 0.U(1.W) ## //*** IF GAP IS REDUCED TO 1 BIT, MUST REDUCE THIS COMPONENT TO 1 BIT TOO: io.fromPreMul.highAlignedSigC(sigWidth + 1, sigWidth) ## sigSum(sigSumWidth - 3, sigWidth + 2) ) val CDom_absSigSumExtra = Mux(io.fromPreMul.doSubMags, (~sigSum(sigWidth, 1)).orR, sigSum(sigWidth + 1, 1).orR ) val CDom_mainSig = (CDom_absSigSum<<io.fromPreMul.CDom_CAlignDist)( sigWidth * 2 + 1, sigWidth - 3) val CDom_reduced4SigExtra = (orReduceBy4(CDom_absSigSum(sigWidth - 1, 0)<<(~sigWidth & 3)) & lowMask(io.fromPreMul.CDom_CAlignDist>>2, 0, sigWidth>>2)).orR val CDom_sig = Cat(CDom_mainSig>>3, CDom_mainSig(2, 0).orR \|\| CDom_reduced4SigExtra \|\| CDom_absSigSumExtra ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val notCDom_signSigSum = sigSum(sigWidth * 2 + 3) val notCDom_absSigSum = Mux(notCDom_signSigSum, ~sigSum(sigWidth * 2 + 2, 0), sigSum(sigWidth * 2 + 2, 0) + io.fromPreMul.doSubMags ) val notCDom_reduced2AbsSigSum = orReduceBy2(notCDom_absSigSum) val notCDom_normDistReduced2 = countLeadingZeros(notCDom_reduced2AbsSigSum) val notCDom_nearNormDist = notCDom_normDistReduced2<<1 val notCDom_sExp = io.fromPreMul.sExpSum - notCDom_nearNormDist.asUInt.zext val notCDom_mainSig = (notCDom_absSigSum<<notCDom_nearNormDist)( sigWidth * 2 + 3, sigWidth - 1) val notCDom_reduced4SigExtra = (orReduceBy2( notCDom_reduced2AbsSigSum(sigWidth>>1, 0)<<((sigWidth>>1) & 1)) & lowMask(notCDom_normDistReduced2>>1, 0, (sigWidth + 2)>>2) ).orR val notCDom_sig = Cat(notCDom_mainSig>>3, notCDom_mainSig(2, 0).orR \|\| notCDom_reduced4SigExtra ) val notCDom_completeCancellation = (notCDom_sig(sigWidth + 2, sigWidth + 1) === 0.U) val notCDom_sign = Mux(notCDom_completeCancellation, roundingMode_min, io.fromPreMul.signProd ^ notCDom_signSigSum ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val notNaN_isInfProd = io.fromPreMul.isInfA \|\| io.fromPreMul.isInfB val notNaN_isInfOut = notNaN_isInfProd \|\| io.fromPreMul.isInfC val notNaN_addZeros = (io.fromPreMul.isZeroA \|\| io.fromPreMul.isZeroB) && io.fromPreMul.isZeroC io.invalidExc := io.fromPreMul.isSigNaNAny \|\| (io.fromPreMul.isInfA && io.fromPreMul.isZeroB) \|\| (io.fromPreMul.isZeroA && io.fromPreMul.isInfB) \|\| (! io.fromPreMul.isNaNAOrB && (io.fromPreMul.isInfA \|\| io.fromPreMul.isInfB) && io.fromPreMul.isInfC && io.fromPreMul.doSubMags) io.rawOut.isNaN := io.fromPreMul.isNaNAOrB \|\| io.fromPreMul.isNaNC io.rawOut.isInf := notNaN_isInfOut //*** IMPROVE?: io.rawOut.isZero := notNaN_addZeros \|\| (! io.fromPreMul.CIsDominant && notCDom_completeCancellation) io.rawOut.sign := (notNaN_isInfProd && io.fromPreMul.signProd) \|\| (io.fromPreMul.isInfC && opSignC) \|\| (notNaN_addZeros && ! roundingMode_min && io.fromPreMul.signProd && opSignC) \|\| (notNaN_addZeros && roundingMode_min && (io.fromPreMul.signProd \|\| opSignC)) \|\| (! notNaN_isInfOut && ! notNaN_addZeros && Mux(io.fromPreMul.CIsDominant, CDom_sign, notCDom_sign)) io.rawOut.sExp := Mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp) io.rawOut.sig := Mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFN(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val mulAddRecFNToRaw_preMul = Module(new MulAddRecFNToRaw_preMul(expWidth, sigWidth)) val mulAddRecFNToRaw_postMul = Module(new MulAddRecFNToRaw_postMul(expWidth, sigWidth)) mulAddRecFNToRaw_preMul.io.op := io.op mulAddRecFNToRaw_preMul.io.a := io.a mulAddRecFNToRaw_preMul.io.b := io.b mulAddRecFNToRaw_preMul.io.c := io.c val mulAddResult = (mulAddRecFNToRaw_preMul.io.mulAddA * mulAddRecFNToRaw_preMul.io.mulAddB) +& mulAddRecFNToRaw_preMul.io.mulAddC mulAddRecFNToRaw_postMul.io.fromPreMul := mulAddRecFNToRaw_preMul.io.toPostMul mulAddRecFNToRaw_postMul.io.mulAddResult := mulAddResult mulAddRecFNToRaw_postMul.io.roundingMode := io.roundingMode //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundRawFNToRecFN = Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0)) roundRawFNToRecFN.io.invalidExc := mulAddRecFNToRaw_postMul.io.invalidExc roundRawFNToRecFN.io.infiniteExc := false.B roundRawFNToRecFN.io.in := mulAddRecFNToRaw_postMul.io.rawOut roundRawFNToRecFN.io.roundingMode := io.roundingMode roundRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundRawFNToRecFN.io.out io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags }	module MulAddRecFNToRaw_postMul_e8_s24_79( // @[MulAddRecFN.scala:169:7] input io_fromPreMul_isSigNaNAny, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isNaNAOrB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfA, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroA, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_signProd, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isNaNC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroC, // @[MulAddRecFN.scala:172:16] input [9:0] io_fromPreMul_sExpSum, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_doSubMags, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_CIsDominant, // @[MulAddRecFN.scala:172:16] input [4:0] io_fromPreMul_CDom_CAlignDist, // @[MulAddRecFN.scala:172:16] input [25:0] io_fromPreMul_highAlignedSigC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_bit0AlignedSigC, // @[MulAddRecFN.scala:172:16] input [48:0] io_mulAddResult, // @[MulAddRecFN.scala:172:16] output io_invalidExc, // @[MulAddRecFN.scala:172:16] output io_rawOut_isNaN, // @[MulAddRecFN.scala:172:16] output io_rawOut_isInf, // @[MulAddRecFN.scala:172:16] output io_rawOut_isZero, // @[MulAddRecFN.scala:172:16] output io_rawOut_sign, // @[MulAddRecFN.scala:172:16] output [9:0] io_rawOut_sExp, // @[MulAddRecFN.scala:172:16] output [26:0] io_rawOut_sig // @[MulAddRecFN.scala:172:16] ); wire io_fromPreMul_isSigNaNAny_0 = io_fromPreMul_isSigNaNAny; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isNaNAOrB_0 = io_fromPreMul_isNaNAOrB; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfA_0 = io_fromPreMul_isInfA; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroA_0 = io_fromPreMul_isZeroA; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfB_0 = io_fromPreMul_isInfB; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroB_0 = io_fromPreMul_isZeroB; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_signProd_0 = io_fromPreMul_signProd; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isNaNC_0 = io_fromPreMul_isNaNC; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfC_0 = io_fromPreMul_isInfC; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroC_0 = io_fromPreMul_isZeroC; // @[MulAddRecFN.scala:169:7] wire [9:0] io_fromPreMul_sExpSum_0 = io_fromPreMul_sExpSum; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_doSubMags_0 = io_fromPreMul_doSubMags; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_CIsDominant_0 = io_fromPreMul_CIsDominant; // @[MulAddRecFN.scala:169:7] wire [4:0] io_fromPreMul_CDom_CAlignDist_0 = io_fromPreMul_CDom_CAlignDist; // @[MulAddRecFN.scala:169:7] wire [25:0] io_fromPreMul_highAlignedSigC_0 = io_fromPreMul_highAlignedSigC; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_bit0AlignedSigC_0 = io_fromPreMul_bit0AlignedSigC; // @[MulAddRecFN.scala:169:7] wire [48:0] io_mulAddResult_0 = io_mulAddResult; // @[MulAddRecFN.scala:169:7] wire _io_rawOut_sign_T_3 = 1'h1; // @[MulAddRecFN.scala:287:29] wire roundingMode_min = 1'h0; // @[MulAddRecFN.scala:186:45] wire _io_rawOut_sign_T_8 = 1'h0; // @[MulAddRecFN.scala:289:26] wire _io_rawOut_sign_T_10 = 1'h0; // @[MulAddRecFN.scala:289:46] wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:169:7, :172:16] wire _io_invalidExc_T_9; // @[MulAddRecFN.scala:273:57] wire _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:278:48] wire notNaN_isInfOut; // @[MulAddRecFN.scala:265:44] wire _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:282:25] wire _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:290:50] wire [9:0] _io_rawOut_sExp_T; // @[MulAddRecFN.scala:293:26] wire [26:0] _io_rawOut_sig_T; // @[MulAddRecFN.scala:294:25] wire io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7] wire [9:0] io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7] wire [26:0] io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7] wire io_invalidExc_0; // @[MulAddRecFN.scala:169:7] wire opSignC = io_fromPreMul_signProd_0 ^ io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :190:42] wire _sigSum_T = io_mulAddResult_0[48]; // @[MulAddRecFN.scala:169:7, :192:32] wire [26:0] _sigSum_T_1 = {1'h0, io_fromPreMul_highAlignedSigC_0} + 27'h1; // @[MulAddRecFN.scala:169:7, :193:47] wire [25:0] _sigSum_T_2 = _sigSum_T_1[25:0]; // @[MulAddRecFN.scala:193:47] wire [25:0] _sigSum_T_3 = _sigSum_T ? _sigSum_T_2 : io_fromPreMul_highAlignedSigC_0; // @[MulAddRecFN.scala:169:7, :192:{16,32}, :193:47] wire [47:0] _sigSum_T_4 = io_mulAddResult_0[47:0]; // @[MulAddRecFN.scala:169:7, :196:28] wire [73:0] sigSum_hi = {_sigSum_T_3, _sigSum_T_4}; // @[MulAddRecFN.scala:192:{12,16}, :196:28] wire [74:0] sigSum = {sigSum_hi, io_fromPreMul_bit0AlignedSigC_0}; // @[MulAddRecFN.scala:169:7, :192:12] wire [1:0] _CDom_sExp_T = {1'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :203:69] wire [10:0] _GEN = {io_fromPreMul_sExpSum_0[9], io_fromPreMul_sExpSum_0}; // @[MulAddRecFN.scala:169:7, :203:43] wire [10:0] _CDom_sExp_T_1 = _GEN - {{9{_CDom_sExp_T[1]}}, _CDom_sExp_T}; // @[MulAddRecFN.scala:203:{43,69}] wire [9:0] _CDom_sExp_T_2 = _CDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:203:43] wire [9:0] CDom_sExp = _CDom_sExp_T_2; // @[MulAddRecFN.scala:203:43] wire [49:0] _CDom_absSigSum_T = sigSum[74:25]; // @[MulAddRecFN.scala:192:12, :206:20] wire [49:0] _CDom_absSigSum_T_1 = ~_CDom_absSigSum_T; // @[MulAddRecFN.scala:206:{13,20}] wire [1:0] _CDom_absSigSum_T_2 = io_fromPreMul_highAlignedSigC_0[25:24]; // @[MulAddRecFN.scala:169:7, :209:46] wire [2:0] _CDom_absSigSum_T_3 = {1'h0, _CDom_absSigSum_T_2}; // @[MulAddRecFN.scala:207:22, :209:46] wire [46:0] _CDom_absSigSum_T_4 = sigSum[72:26]; // @[MulAddRecFN.scala:192:12, :210:23] wire [49:0] _CDom_absSigSum_T_5 = {_CDom_absSigSum_T_3, _CDom_absSigSum_T_4}; // @[MulAddRecFN.scala:207:22, :209:71, :210:23] wire [49:0] CDom_absSigSum = io_fromPreMul_doSubMags_0 ? _CDom_absSigSum_T_1 : _CDom_absSigSum_T_5; // @[MulAddRecFN.scala:169:7, :205:12, :206:13, :209:71] wire [23:0] _CDom_absSigSumExtra_T = sigSum[24:1]; // @[MulAddRecFN.scala:192:12, :215:21] wire [23:0] _CDom_absSigSumExtra_T_1 = ~_CDom_absSigSumExtra_T; // @[MulAddRecFN.scala:215:{14,21}] wire _CDom_absSigSumExtra_T_2 = \|_CDom_absSigSumExtra_T_1; // @[MulAddRecFN.scala:215:{14,36}] wire [24:0] _CDom_absSigSumExtra_T_3 = sigSum[25:1]; // @[MulAddRecFN.scala:192:12, :216:19] wire _CDom_absSigSumExtra_T_4 = \|_CDom_absSigSumExtra_T_3; // @[MulAddRecFN.scala:216:{19,37}] wire CDom_absSigSumExtra = io_fromPreMul_doSubMags_0 ? _CDom_absSigSumExtra_T_2 : _CDom_absSigSumExtra_T_4; // @[MulAddRecFN.scala:169:7, :214:12, :215:36, :216:37] wire [80:0] _CDom_mainSig_T = {31'h0, CDom_absSigSum} << io_fromPreMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:169:7, :205:12, :219:24] wire [28:0] CDom_mainSig = _CDom_mainSig_T[49:21]; // @[MulAddRecFN.scala:219:{24,56}] wire [23:0] _CDom_reduced4SigExtra_T = CDom_absSigSum[23:0]; // @[MulAddRecFN.scala:205:12, :222:36] wire [26:0] _CDom_reduced4SigExtra_T_1 = {_CDom_reduced4SigExtra_T, 3'h0}; // @[MulAddRecFN.scala:169:7, :172:16, :222:{36,53}] wire _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:123:57] wire CDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:118:30] wire [3:0] _CDom_reduced4SigExtra_reducedVec_0_T = _CDom_reduced4SigExtra_T_1[3:0]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_0_T_1 = \|_CDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_0 = _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_1_T = _CDom_reduced4SigExtra_T_1[7:4]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_1_T_1 = \|_CDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_1 = _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_2_T = _CDom_reduced4SigExtra_T_1[11:8]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_2_T_1 = \|_CDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_2 = _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_3_T = _CDom_reduced4SigExtra_T_1[15:12]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_3_T_1 = \|_CDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_3 = _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_4_T = _CDom_reduced4SigExtra_T_1[19:16]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_4_T_1 = \|_CDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_4 = _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_5_T = _CDom_reduced4SigExtra_T_1[23:20]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_5_T_1 = \|_CDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_5 = _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54] wire [2:0] _CDom_reduced4SigExtra_reducedVec_6_T = _CDom_reduced4SigExtra_T_1[26:24]; // @[primitives.scala:123:15] assign _CDom_reduced4SigExtra_reducedVec_6_T_1 = \|_CDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:123:{15,57}] assign CDom_reduced4SigExtra_reducedVec_6 = _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :123:57] wire [1:0] CDom_reduced4SigExtra_lo_hi = {CDom_reduced4SigExtra_reducedVec_2, CDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20] wire [2:0] CDom_reduced4SigExtra_lo = {CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20] wire [1:0] CDom_reduced4SigExtra_hi_lo = {CDom_reduced4SigExtra_reducedVec_4, CDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20] wire [1:0] CDom_reduced4SigExtra_hi_hi = {CDom_reduced4SigExtra_reducedVec_6, CDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20] wire [3:0] CDom_reduced4SigExtra_hi = {CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:124:20] wire [6:0] _CDom_reduced4SigExtra_T_2 = {CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo}; // @[primitives.scala:124:20] wire [2:0] _CDom_reduced4SigExtra_T_3 = io_fromPreMul_CDom_CAlignDist_0[4:2]; // @[MulAddRecFN.scala:169:7, :223:51] wire [2:0] _CDom_reduced4SigExtra_T_4 = ~_CDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21] wire [8:0] CDom_reduced4SigExtra_shift = $signed(9'sh100 >>> _CDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56] wire [5:0] _CDom_reduced4SigExtra_T_5 = CDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22] wire [3:0] _CDom_reduced4SigExtra_T_6 = _CDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22] wire [1:0] _CDom_reduced4SigExtra_T_7 = _CDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_8 = _CDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_9 = _CDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_10 = {_CDom_reduced4SigExtra_T_8, _CDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_11 = _CDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_12 = _CDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_13 = _CDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_14 = {_CDom_reduced4SigExtra_T_12, _CDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20] wire [3:0] _CDom_reduced4SigExtra_T_15 = {_CDom_reduced4SigExtra_T_10, _CDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_16 = _CDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22] wire _CDom_reduced4SigExtra_T_17 = _CDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_18 = _CDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_19 = {_CDom_reduced4SigExtra_T_17, _CDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20] wire [5:0] _CDom_reduced4SigExtra_T_20 = {_CDom_reduced4SigExtra_T_15, _CDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20] wire [6:0] _CDom_reduced4SigExtra_T_21 = {1'h0, _CDom_reduced4SigExtra_T_2[5:0] & _CDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :124:20] wire CDom_reduced4SigExtra = \|_CDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:222:72, :223:73] wire [25:0] _CDom_sig_T = CDom_mainSig[28:3]; // @[MulAddRecFN.scala:219:56, :225:25] wire [2:0] _CDom_sig_T_1 = CDom_mainSig[2:0]; // @[MulAddRecFN.scala:219:56, :226:25] wire _CDom_sig_T_2 = \|_CDom_sig_T_1; // @[MulAddRecFN.scala:226:{25,32}] wire _CDom_sig_T_3 = _CDom_sig_T_2 \| CDom_reduced4SigExtra; // @[MulAddRecFN.scala:223:73, :226:{32,36}] wire _CDom_sig_T_4 = _CDom_sig_T_3 \| CDom_absSigSumExtra; // @[MulAddRecFN.scala:214:12, :226:{36,61}] wire [26:0] CDom_sig = {_CDom_sig_T, _CDom_sig_T_4}; // @[MulAddRecFN.scala:225:{12,25}, :226:61] wire notCDom_signSigSum = sigSum[51]; // @[MulAddRecFN.scala:192:12, :232:36] wire [50:0] _notCDom_absSigSum_T = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20] wire [50:0] _notCDom_absSigSum_T_2 = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20, :236:19] wire [50:0] _notCDom_absSigSum_T_1 = ~_notCDom_absSigSum_T; // @[MulAddRecFN.scala:235:{13,20}] wire [51:0] _notCDom_absSigSum_T_3 = {1'h0, _notCDom_absSigSum_T_2} + {51'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :236:{19,41}] wire [50:0] _notCDom_absSigSum_T_4 = _notCDom_absSigSum_T_3[50:0]; // @[MulAddRecFN.scala:236:41] wire [50:0] notCDom_absSigSum = notCDom_signSigSum ? _notCDom_absSigSum_T_1 : _notCDom_absSigSum_T_4; // @[MulAddRecFN.scala:232:36, :234:12, :235:13, :236:41] wire _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:106:57] wire notCDom_reduced2AbsSigSum_reducedVec_0; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_1; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_2; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_3; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_4; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_5; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_6; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_7; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_8; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_9; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_10; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_11; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_12; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_13; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_14; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_15; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_16; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_17; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_18; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_19; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_20; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_21; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_22; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_23; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_24; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_25; // @[primitives.scala:101:30] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_0_T = notCDom_absSigSum[1:0]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_0_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_0 = _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_1_T = notCDom_absSigSum[3:2]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_1_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_1 = _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_2_T = notCDom_absSigSum[5:4]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_2_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_2 = _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_3_T = notCDom_absSigSum[7:6]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_3_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_3 = _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_4_T = notCDom_absSigSum[9:8]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_4_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_4 = _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_5_T = notCDom_absSigSum[11:10]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_5_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_5 = _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_6_T = notCDom_absSigSum[13:12]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_6_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_6 = _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_7_T = notCDom_absSigSum[15:14]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_7_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_7 = _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_8_T = notCDom_absSigSum[17:16]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_8_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_8 = _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_9_T = notCDom_absSigSum[19:18]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_9_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_9 = _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_10_T = notCDom_absSigSum[21:20]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_10_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_10 = _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_11_T = notCDom_absSigSum[23:22]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_11_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_11 = _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_12_T = notCDom_absSigSum[25:24]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_12_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_12 = _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_13_T = notCDom_absSigSum[27:26]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_13_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_13 = _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_14_T = notCDom_absSigSum[29:28]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_14_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_14 = _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_15_T = notCDom_absSigSum[31:30]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_15_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_15 = _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_16_T = notCDom_absSigSum[33:32]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_16_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_16 = _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_17_T = notCDom_absSigSum[35:34]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_17_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_17 = _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_18_T = notCDom_absSigSum[37:36]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_18_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_18 = _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_19_T = notCDom_absSigSum[39:38]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_19_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_19 = _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_20_T = notCDom_absSigSum[41:40]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_20_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_20 = _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_21_T = notCDom_absSigSum[43:42]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_21_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_21 = _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_22_T = notCDom_absSigSum[45:44]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_22_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_22 = _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_23_T = notCDom_absSigSum[47:46]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_23_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_23 = _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_24_T = notCDom_absSigSum[49:48]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_24_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_24 = _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:101:30, :103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_25_T = notCDom_absSigSum[50]; // @[primitives.scala:106:15] assign _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = _notCDom_reduced2AbsSigSum_reducedVec_25_T; // @[primitives.scala:106:{15,57}] assign notCDom_reduced2AbsSigSum_reducedVec_25 = _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:101:30, :106:57] wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_2, notCDom_reduced2AbsSigSum_reducedVec_1}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_0}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_5, notCDom_reduced2AbsSigSum_reducedVec_4}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_hi = {notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_3}; // @[primitives.scala:101:30, :107:20] wire [5:0] notCDom_reduced2AbsSigSum_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_8, notCDom_reduced2AbsSigSum_reducedVec_7}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_hi_lo = {notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_6}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_10, notCDom_reduced2AbsSigSum_reducedVec_9}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_12, notCDom_reduced2AbsSigSum_reducedVec_11}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced2AbsSigSum_lo_hi_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo}; // @[primitives.scala:107:20] wire [6:0] notCDom_reduced2AbsSigSum_lo_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo}; // @[primitives.scala:107:20] wire [12:0] notCDom_reduced2AbsSigSum_lo = {notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_15, notCDom_reduced2AbsSigSum_reducedVec_14}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_lo = {notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_13}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_18, notCDom_reduced2AbsSigSum_reducedVec_17}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_hi = {notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_16}; // @[primitives.scala:101:30, :107:20] wire [5:0] notCDom_reduced2AbsSigSum_hi_lo = {notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_21, notCDom_reduced2AbsSigSum_reducedVec_20}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_hi_lo = {notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_19}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_23, notCDom_reduced2AbsSigSum_reducedVec_22}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_25, notCDom_reduced2AbsSigSum_reducedVec_24}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced2AbsSigSum_hi_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo}; // @[primitives.scala:107:20] wire [6:0] notCDom_reduced2AbsSigSum_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo}; // @[primitives.scala:107:20] wire [12:0] notCDom_reduced2AbsSigSum_hi = {notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo}; // @[primitives.scala:107:20] wire [25:0] notCDom_reduced2AbsSigSum = {notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo}; // @[primitives.scala:107:20] wire _notCDom_normDistReduced2_T = notCDom_reduced2AbsSigSum[0]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_1 = notCDom_reduced2AbsSigSum[1]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_2 = notCDom_reduced2AbsSigSum[2]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_3 = notCDom_reduced2AbsSigSum[3]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_4 = notCDom_reduced2AbsSigSum[4]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_5 = notCDom_reduced2AbsSigSum[5]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_6 = notCDom_reduced2AbsSigSum[6]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_7 = notCDom_reduced2AbsSigSum[7]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_8 = notCDom_reduced2AbsSigSum[8]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_9 = notCDom_reduced2AbsSigSum[9]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_10 = notCDom_reduced2AbsSigSum[10]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_11 = notCDom_reduced2AbsSigSum[11]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_12 = notCDom_reduced2AbsSigSum[12]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_13 = notCDom_reduced2AbsSigSum[13]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_14 = notCDom_reduced2AbsSigSum[14]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_15 = notCDom_reduced2AbsSigSum[15]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_16 = notCDom_reduced2AbsSigSum[16]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_17 = notCDom_reduced2AbsSigSum[17]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_18 = notCDom_reduced2AbsSigSum[18]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_19 = notCDom_reduced2AbsSigSum[19]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_20 = notCDom_reduced2AbsSigSum[20]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_21 = notCDom_reduced2AbsSigSum[21]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_22 = notCDom_reduced2AbsSigSum[22]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_23 = notCDom_reduced2AbsSigSum[23]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_24 = notCDom_reduced2AbsSigSum[24]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_25 = notCDom_reduced2AbsSigSum[25]; // @[primitives.scala:91:52, :107:20] wire [4:0] _notCDom_normDistReduced2_T_26 = {4'hC, ~_notCDom_normDistReduced2_T_1}; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_27 = _notCDom_normDistReduced2_T_2 ? 5'h17 : _notCDom_normDistReduced2_T_26; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_28 = _notCDom_normDistReduced2_T_3 ? 5'h16 : _notCDom_normDistReduced2_T_27; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_29 = _notCDom_normDistReduced2_T_4 ? 5'h15 : _notCDom_normDistReduced2_T_28; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_30 = _notCDom_normDistReduced2_T_5 ? 5'h14 : _notCDom_normDistReduced2_T_29; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_31 = _notCDom_normDistReduced2_T_6 ? 5'h13 : _notCDom_normDistReduced2_T_30; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_32 = _notCDom_normDistReduced2_T_7 ? 5'h12 : _notCDom_normDistReduced2_T_31; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_33 = _notCDom_normDistReduced2_T_8 ? 5'h11 : _notCDom_normDistReduced2_T_32; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_34 = _notCDom_normDistReduced2_T_9 ? 5'h10 : _notCDom_normDistReduced2_T_33; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_35 = _notCDom_normDistReduced2_T_10 ? 5'hF : _notCDom_normDistReduced2_T_34; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_36 = _notCDom_normDistReduced2_T_11 ? 5'hE : _notCDom_normDistReduced2_T_35; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_37 = _notCDom_normDistReduced2_T_12 ? 5'hD : _notCDom_normDistReduced2_T_36; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_38 = _notCDom_normDistReduced2_T_13 ? 5'hC : _notCDom_normDistReduced2_T_37; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_39 = _notCDom_normDistReduced2_T_14 ? 5'hB : _notCDom_normDistReduced2_T_38; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_40 = _notCDom_normDistReduced2_T_15 ? 5'hA : _notCDom_normDistReduced2_T_39; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_41 = _notCDom_normDistReduced2_T_16 ? 5'h9 : _notCDom_normDistReduced2_T_40; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_42 = _notCDom_normDistReduced2_T_17 ? 5'h8 : _notCDom_normDistReduced2_T_41; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_43 = _notCDom_normDistReduced2_T_18 ? 5'h7 : _notCDom_normDistReduced2_T_42; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_44 = _notCDom_normDistReduced2_T_19 ? 5'h6 : _notCDom_normDistReduced2_T_43; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_45 = _notCDom_normDistReduced2_T_20 ? 5'h5 : _notCDom_normDistReduced2_T_44; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_46 = _notCDom_normDistReduced2_T_21 ? 5'h4 : _notCDom_normDistReduced2_T_45; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_47 = _notCDom_normDistReduced2_T_22 ? 5'h3 : _notCDom_normDistReduced2_T_46; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_48 = _notCDom_normDistReduced2_T_23 ? 5'h2 : _notCDom_normDistReduced2_T_47; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_49 = _notCDom_normDistReduced2_T_24 ? 5'h1 : _notCDom_normDistReduced2_T_48; // @[Mux.scala:50:70] wire [4:0] notCDom_normDistReduced2 = _notCDom_normDistReduced2_T_25 ? 5'h0 : _notCDom_normDistReduced2_T_49; // @[Mux.scala:50:70] wire [5:0] notCDom_nearNormDist = {notCDom_normDistReduced2, 1'h0}; // @[Mux.scala:50:70] wire [6:0] _notCDom_sExp_T = {1'h0, notCDom_nearNormDist}; // @[MulAddRecFN.scala:240:56, :241:76] wire [10:0] _notCDom_sExp_T_1 = _GEN - {{4{_notCDom_sExp_T[6]}}, _notCDom_sExp_T}; // @[MulAddRecFN.scala:203:43, :241:{46,76}] wire [9:0] _notCDom_sExp_T_2 = _notCDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:241:46] wire [9:0] notCDom_sExp = _notCDom_sExp_T_2; // @[MulAddRecFN.scala:241:46] wire [113:0] _notCDom_mainSig_T = {63'h0, notCDom_absSigSum} << notCDom_nearNormDist; // @[MulAddRecFN.scala:234:12, :240:56, :243:27] wire [28:0] notCDom_mainSig = _notCDom_mainSig_T[51:23]; // @[MulAddRecFN.scala:243:{27,50}] wire [12:0] _notCDom_reduced4SigExtra_T = notCDom_reduced2AbsSigSum[12:0]; // @[primitives.scala:107:20] wire [12:0] _notCDom_reduced4SigExtra_T_1 = _notCDom_reduced4SigExtra_T; // @[MulAddRecFN.scala:247:{39,55}] wire _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:106:57] wire notCDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:101:30] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_0_T = _notCDom_reduced4SigExtra_T_1[1:0]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_0_T_1 = \|_notCDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_0 = _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_1_T = _notCDom_reduced4SigExtra_T_1[3:2]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_1_T_1 = \|_notCDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_1 = _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_2_T = _notCDom_reduced4SigExtra_T_1[5:4]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_2_T_1 = \|_notCDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_2 = _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_3_T = _notCDom_reduced4SigExtra_T_1[7:6]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_3_T_1 = \|_notCDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_3 = _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_4_T = _notCDom_reduced4SigExtra_T_1[9:8]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_4_T_1 = \|_notCDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_4 = _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_5_T = _notCDom_reduced4SigExtra_T_1[11:10]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_5_T_1 = \|_notCDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_5 = _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54] wire _notCDom_reduced4SigExtra_reducedVec_6_T = _notCDom_reduced4SigExtra_T_1[12]; // @[primitives.scala:106:15] assign _notCDom_reduced4SigExtra_reducedVec_6_T_1 = _notCDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:106:{15,57}] assign notCDom_reduced4SigExtra_reducedVec_6 = _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:101:30, :106:57] wire [1:0] notCDom_reduced4SigExtra_lo_hi = {notCDom_reduced4SigExtra_reducedVec_2, notCDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced4SigExtra_lo = {notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced4SigExtra_hi_lo = {notCDom_reduced4SigExtra_reducedVec_4, notCDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced4SigExtra_hi_hi = {notCDom_reduced4SigExtra_reducedVec_6, notCDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced4SigExtra_hi = {notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:107:20] wire [6:0] _notCDom_reduced4SigExtra_T_2 = {notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo}; // @[primitives.scala:107:20] wire [3:0] _notCDom_reduced4SigExtra_T_3 = notCDom_normDistReduced2[4:1]; // @[Mux.scala:50:70] wire [3:0] _notCDom_reduced4SigExtra_T_4 = ~_notCDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21] wire [16:0] notCDom_reduced4SigExtra_shift = $signed(17'sh10000 >>> _notCDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56] wire [5:0] _notCDom_reduced4SigExtra_T_5 = notCDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22] wire [3:0] _notCDom_reduced4SigExtra_T_6 = _notCDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22] wire [1:0] _notCDom_reduced4SigExtra_T_7 = _notCDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_8 = _notCDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_9 = _notCDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_10 = {_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_11 = _notCDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_12 = _notCDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_13 = _notCDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_14 = {_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20] wire [3:0] _notCDom_reduced4SigExtra_T_15 = {_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_16 = _notCDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22] wire _notCDom_reduced4SigExtra_T_17 = _notCDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_18 = _notCDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_19 = {_notCDom_reduced4SigExtra_T_17, _notCDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20] wire [5:0] _notCDom_reduced4SigExtra_T_20 = {_notCDom_reduced4SigExtra_T_15, _notCDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20] wire [6:0] _notCDom_reduced4SigExtra_T_21 = {1'h0, _notCDom_reduced4SigExtra_T_2[5:0] & _notCDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :107:20] wire notCDom_reduced4SigExtra = \|_notCDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:247:78, :249:11] wire [25:0] _notCDom_sig_T = notCDom_mainSig[28:3]; // @[MulAddRecFN.scala:243:50, :251:28] wire [2:0] _notCDom_sig_T_1 = notCDom_mainSig[2:0]; // @[MulAddRecFN.scala:243:50, :252:28] wire _notCDom_sig_T_2 = \|_notCDom_sig_T_1; // @[MulAddRecFN.scala:252:{28,35}] wire _notCDom_sig_T_3 = _notCDom_sig_T_2 \| notCDom_reduced4SigExtra; // @[MulAddRecFN.scala:249:11, :252:{35,39}] wire [26:0] notCDom_sig = {_notCDom_sig_T, _notCDom_sig_T_3}; // @[MulAddRecFN.scala:251:{12,28}, :252:39] wire [1:0] _notCDom_completeCancellation_T = notCDom_sig[26:25]; // @[MulAddRecFN.scala:251:12, :255:21] wire notCDom_completeCancellation = _notCDom_completeCancellation_T == 2'h0; // @[primitives.scala:103:54] wire _notCDom_sign_T = io_fromPreMul_signProd_0 ^ notCDom_signSigSum; // @[MulAddRecFN.scala:169:7, :232:36, :259:36] wire notCDom_sign = ~notCDom_completeCancellation & _notCDom_sign_T; // @[MulAddRecFN.scala:255:50, :257:12, :259:36] wire _GEN_0 = io_fromPreMul_isInfA_0 \| io_fromPreMul_isInfB_0; // @[MulAddRecFN.scala:169:7, :264:49] wire notNaN_isInfProd; // @[MulAddRecFN.scala:264:49] assign notNaN_isInfProd = _GEN_0; // @[MulAddRecFN.scala:264:49] wire _io_invalidExc_T_5; // @[MulAddRecFN.scala:275:36] assign _io_invalidExc_T_5 = _GEN_0; // @[MulAddRecFN.scala:264:49, :275:36] assign notNaN_isInfOut = notNaN_isInfProd \| io_fromPreMul_isInfC_0; // @[MulAddRecFN.scala:169:7, :264:49, :265:44] assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulAddRecFN.scala:169:7, :265:44] wire _notNaN_addZeros_T = io_fromPreMul_isZeroA_0 \| io_fromPreMul_isZeroB_0; // @[MulAddRecFN.scala:169:7, :267:32] wire notNaN_addZeros = _notNaN_addZeros_T & io_fromPreMul_isZeroC_0; // @[MulAddRecFN.scala:169:7, :267:{32,58}] wire _io_rawOut_sign_T_4 = notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :287:26] wire _io_invalidExc_T = io_fromPreMul_isInfA_0 & io_fromPreMul_isZeroB_0; // @[MulAddRecFN.scala:169:7, :272:31] wire _io_invalidExc_T_1 = io_fromPreMul_isSigNaNAny_0 \| _io_invalidExc_T; // @[MulAddRecFN.scala:169:7, :271:35, :272:31] wire _io_invalidExc_T_2 = io_fromPreMul_isZeroA_0 & io_fromPreMul_isInfB_0; // @[MulAddRecFN.scala:169:7, :273:32] wire _io_invalidExc_T_3 = _io_invalidExc_T_1 \| _io_invalidExc_T_2; // @[MulAddRecFN.scala:271:35, :272:57, :273:32] wire _io_invalidExc_T_4 = ~io_fromPreMul_isNaNAOrB_0; // @[MulAddRecFN.scala:169:7, :274:10] wire _io_invalidExc_T_6 = _io_invalidExc_T_4 & _io_invalidExc_T_5; // @[MulAddRecFN.scala:274:{10,36}, :275:36] wire _io_invalidExc_T_7 = _io_invalidExc_T_6 & io_fromPreMul_isInfC_0; // @[MulAddRecFN.scala:169:7, :274:36, :275:61] wire _io_invalidExc_T_8 = _io_invalidExc_T_7 & io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :275:61, :276:35] assign _io_invalidExc_T_9 = _io_invalidExc_T_3 \| _io_invalidExc_T_8; // @[MulAddRecFN.scala:272:57, :273:57, :276:35] assign io_invalidExc_0 = _io_invalidExc_T_9; // @[MulAddRecFN.scala:169:7, :273:57] assign _io_rawOut_isNaN_T = io_fromPreMul_isNaNAOrB_0 \| io_fromPreMul_isNaNC_0; // @[MulAddRecFN.scala:169:7, :278:48] assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:169:7, :278:48] wire _io_rawOut_isZero_T = ~io_fromPreMul_CIsDominant_0; // @[MulAddRecFN.scala:169:7, :283:14] wire _io_rawOut_isZero_T_1 = _io_rawOut_isZero_T & notCDom_completeCancellation; // @[MulAddRecFN.scala:255:50, :283:{14,42}] assign _io_rawOut_isZero_T_2 = notNaN_addZeros \| _io_rawOut_isZero_T_1; // @[MulAddRecFN.scala:267:58, :282:25, :283:42] assign io_rawOut_isZero_0 = _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:169:7, :282:25] wire _io_rawOut_sign_T = notNaN_isInfProd & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :264:49, :285:27] wire _io_rawOut_sign_T_1 = io_fromPreMul_isInfC_0 & opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :286:31] wire _io_rawOut_sign_T_2 = _io_rawOut_sign_T \| _io_rawOut_sign_T_1; // @[MulAddRecFN.scala:285:{27,54}, :286:31] wire _io_rawOut_sign_T_5 = _io_rawOut_sign_T_4 & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :287:{26,48}] wire _io_rawOut_sign_T_6 = _io_rawOut_sign_T_5 & opSignC; // @[MulAddRecFN.scala:190:42, :287:48, :288:36] wire _io_rawOut_sign_T_7 = _io_rawOut_sign_T_2 \| _io_rawOut_sign_T_6; // @[MulAddRecFN.scala:285:54, :286:43, :288:36] wire _io_rawOut_sign_T_11 = _io_rawOut_sign_T_7; // @[MulAddRecFN.scala:286:43, :288:48] wire _io_rawOut_sign_T_9 = io_fromPreMul_signProd_0 \| opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :290:37] wire _io_rawOut_sign_T_12 = ~notNaN_isInfOut; // @[MulAddRecFN.scala:265:44, :291:10] wire _io_rawOut_sign_T_13 = ~notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :291:31] wire _io_rawOut_sign_T_14 = _io_rawOut_sign_T_12 & _io_rawOut_sign_T_13; // @[MulAddRecFN.scala:291:{10,28,31}] wire _io_rawOut_sign_T_15 = io_fromPreMul_CIsDominant_0 ? opSignC : notCDom_sign; // @[MulAddRecFN.scala:169:7, :190:42, :257:12, :292:17] wire _io_rawOut_sign_T_16 = _io_rawOut_sign_T_14 & _io_rawOut_sign_T_15; // @[MulAddRecFN.scala:291:{28,49}, :292:17] assign _io_rawOut_sign_T_17 = _io_rawOut_sign_T_11 \| _io_rawOut_sign_T_16; // @[MulAddRecFN.scala:288:48, :290:50, :291:49] assign io_rawOut_sign_0 = _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:169:7, :290:50] assign _io_rawOut_sExp_T = io_fromPreMul_CIsDominant_0 ? CDom_sExp : notCDom_sExp; // @[MulAddRecFN.scala:169:7, :203:43, :241:46, :293:26] assign io_rawOut_sExp_0 = _io_rawOut_sExp_T; // @[MulAddRecFN.scala:169:7, :293:26] assign _io_rawOut_sig_T = io_fromPreMul_CIsDominant_0 ? CDom_sig : notCDom_sig; // @[MulAddRecFN.scala:169:7, :225:12, :251:12, :294:25] assign io_rawOut_sig_0 = _io_rawOut_sig_T; // @[MulAddRecFN.scala:169:7, :294:25] assign io_invalidExc = io_invalidExc_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sign = io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sig = io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File RegisterFile.scala: package saturn.backend import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import freechips.rocketchip.tile.{CoreModule} import freechips.rocketchip.util._ import saturn.common._ class OldestRRArbiter(val n: Int)(implicit p: Parameters) extends Module { val io = IO(new ArbiterIO(new VectorReadReq, n)) val arb = Module(new RRArbiter(new VectorReadReq, n)) io <> arb.io val oldest_oh = io.in.map(i => i.valid && i.bits.oldest) //assert(PopCount(oldest_oh) <= 1.U) when (oldest_oh.orR) { io.chosen := VecInit(oldest_oh).asUInt io.out.valid := true.B io.out.bits := Mux1H(oldest_oh, io.in.map(_.bits)) for (i <- 0 until n) { io.in(i).ready := oldest_oh(i) && io.out.ready } } } class RegisterReadXbar(n: Int, banks: Int)(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams { val io = IO(new Bundle { val in = Vec(n, Flipped(new VectorReadIO)) val out = Vec(banks, new VectorReadIO) }) val arbs = Seq.fill(banks) { Module(new OldestRRArbiter(n)) } for (i <- 0 until banks) { io.out(i).req <> arbs(i).io.out } val bankOffset = log2Ceil(banks) for (i <- 0 until n) { val bank_sel = if (bankOffset == 0) true.B else UIntToOH(io.in(i).req.bits.eg(bankOffset-1,0)) for (j <- 0 until banks) { arbs(j).io.in(i).valid := io.in(i).req.valid && bank_sel(j) arbs(j).io.in(i).bits.eg := io.in(i).req.bits.eg >> bankOffset arbs(j).io.in(i).bits.oldest := io.in(i).req.bits.oldest } io.in(i).req.ready := Mux1H(bank_sel, arbs.map(_.io.in(i).ready)) io.in(i).resp := Mux1H(bank_sel, io.out.map(_.resp)) } } class RegisterFileBank(reads: Int, maskReads: Int, rows: Int, maskRows: Int)(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams { val io = IO(new Bundle { val read = Vec(reads, Flipped(new VectorReadIO)) val mask_read = Vec(maskReads, Flipped(new VectorReadIO)) val write = Input(Valid(new VectorWrite(dLen))) val ll_write = Flipped(Decoupled(new VectorWrite(dLen))) }) val ll_write_valid = RegInit(false.B) val ll_write_bits = Reg(new VectorWrite(dLen)) val vrf = Mem(rows, Vec(dLen, Bool())) val v0_mask = Mem(maskRows, Vec(dLen, Bool())) for (read <- io.read) { read.req.ready := !(ll_write_valid && read.req.bits.eg === ll_write_bits.eg) read.resp := DontCare when (read.req.valid) { read.resp := vrf.read(read.req.bits.eg).asUInt } } for (mask_read <- io.mask_read) { mask_read.req.ready := !(ll_write_valid && mask_read.req.bits.eg === ll_write_bits.eg) mask_read.resp := DontCare when (mask_read.req.valid) { mask_read.resp := v0_mask.read(mask_read.req.bits.eg).asUInt } } val write = WireInit(io.write) io.ll_write.ready := false.B if (vParams.vrfHiccupBuffer) { when (!io.write.valid) { // drain hiccup buffer write.valid := ll_write_valid \|\| io.ll_write.valid write.bits := Mux(ll_write_valid, ll_write_bits, io.ll_write.bits) ll_write_valid := false.B when (io.ll_write.valid && ll_write_valid) { ll_write_valid := true.B ll_write_bits := io.ll_write.bits } io.ll_write.ready := true.B } .elsewhen (!ll_write_valid) { // fill hiccup buffer when (io.ll_write.valid) { ll_write_valid := true.B ll_write_bits := io.ll_write.bits } io.ll_write.ready := true.B } } else { when (!io.write.valid) { io.ll_write.ready := true.B write.valid := io.ll_write.valid write.bits := io.ll_write.bits } } when (write.valid) { vrf.write( write.bits.eg, VecInit(write.bits.data.asBools), write.bits.mask.asBools) when (write.bits.eg < maskRows.U) { v0_mask.write( write.bits.eg, VecInit(write.bits.data.asBools), write.bits.mask.asBools) } } } class RegisterFile(reads: Seq[Int], maskReads: Seq[Int], pipeWrites: Int, llWrites: Int)(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams { val nBanks = vParams.vrfBanking // Support 1, 2, and 4 banks for the VRF require(nBanks == 1 \|\| nBanks == 2 \|\| nBanks == 4) val io = IO(new Bundle { val read = MixedVec(reads.map(rc => Vec(rc, Flipped(new VectorReadIO)))) val mask_read = MixedVec(maskReads.map(rc => Vec(rc, Flipped(new VectorReadIO)))) val pipe_writes = Vec(pipeWrites, Input(Valid(new VectorWrite(dLen)))) val ll_writes = Vec(llWrites, Flipped(Decoupled(new VectorWrite(dLen)))) }) val vrf = Seq.fill(nBanks) { Module(new RegisterFileBank(reads.size, maskReads.size, egsTotal/nBanks, if (egsPerVReg < nBanks) 1 else egsPerVReg / nBanks)) } reads.zipWithIndex.foreach { case (rc, i) => val xbar = Module(new RegisterReadXbar(rc, nBanks)) vrf.zipWithIndex.foreach { case (bank, j) => bank.io.read(i) <> xbar.io.out(j) } xbar.io.in <> io.read(i) } maskReads.zipWithIndex.foreach { case (rc, i) => val mask_xbar = Module(new RegisterReadXbar(rc, nBanks)) vrf.zipWithIndex.foreach { case (bank, j) => bank.io.mask_read(i) <> mask_xbar.io.out(j) } mask_xbar.io.in <> io.mask_read(i) } io.ll_writes.foreach(_.ready := false.B) vrf.zipWithIndex.foreach { case (rf, i) => val bank_match = io.pipe_writes.map { w => (w.bits.bankId === i.U) && w.valid } val bank_write_data = Mux1H(bank_match, io.pipe_writes.map(_.bits.data)) val bank_write_mask = Mux1H(bank_match, io.pipe_writes.map(_.bits.mask)) val bank_write_eg = Mux1H(bank_match, io.pipe_writes.map(_.bits.eg)) val bank_write_valid = bank_match.orR rf.io.write.valid := bank_write_valid rf.io.write.bits.data := bank_write_data rf.io.write.bits.mask := bank_write_mask rf.io.write.bits.eg := bank_write_eg >> vrfBankBits when (bank_write_valid) { PopCount(bank_match) === 1.U } val ll_arb = Module(new Arbiter(new VectorWrite(dLen), llWrites)) rf.io.ll_write <> ll_arb.io.out io.ll_writes.zipWithIndex.foreach { case (w, j) => ll_arb.io.in(j).valid := w.valid && w.bits.bankId === i.U ll_arb.io.in(j).bits.eg := w.bits.eg >> vrfBankBits ll_arb.io.in(j).bits.data := w.bits.data ll_arb.io.in(j).bits.mask := w.bits.mask when (ll_arb.io.in(j).ready && w.bits.bankId === i.U) { w.ready := true.B } } } }	module RegisterReadXbar( // @[RegisterFile.scala:27:7] input clock, // @[RegisterFile.scala:27:7] output io_in_0_req_ready, // @[RegisterFile.scala:28:14] input io_in_0_req_valid, // @[RegisterFile.scala:28:14] input [4:0] io_in_0_req_bits_eg, // @[RegisterFile.scala:28:14] input io_in_0_req_bits_oldest, // @[RegisterFile.scala:28:14] output [127:0] io_in_0_resp, // @[RegisterFile.scala:28:14] output io_in_1_req_ready, // @[RegisterFile.scala:28:14] input io_in_1_req_valid, // @[RegisterFile.scala:28:14] input [4:0] io_in_1_req_bits_eg, // @[RegisterFile.scala:28:14] input io_in_1_req_bits_oldest, // @[RegisterFile.scala:28:14] output [127:0] io_in_1_resp, // @[RegisterFile.scala:28:14] output io_in_2_req_ready, // @[RegisterFile.scala:28:14] input io_in_2_req_valid, // @[RegisterFile.scala:28:14] input [4:0] io_in_2_req_bits_eg, // @[RegisterFile.scala:28:14] output [127:0] io_in_2_resp, // @[RegisterFile.scala:28:14] input io_out_0_req_ready, // @[RegisterFile.scala:28:14] output io_out_0_req_valid, // @[RegisterFile.scala:28:14] output [4:0] io_out_0_req_bits_eg, // @[RegisterFile.scala:28:14] input [127:0] io_out_0_resp, // @[RegisterFile.scala:28:14] input io_out_1_req_ready, // @[RegisterFile.scala:28:14] output io_out_1_req_valid, // @[RegisterFile.scala:28:14] output [4:0] io_out_1_req_bits_eg, // @[RegisterFile.scala:28:14] input [127:0] io_out_1_resp, // @[RegisterFile.scala:28:14] input io_out_2_req_ready, // @[RegisterFile.scala:28:14] output io_out_2_req_valid, // @[RegisterFile.scala:28:14] output [4:0] io_out_2_req_bits_eg, // @[RegisterFile.scala:28:14] input [127:0] io_out_2_resp, // @[RegisterFile.scala:28:14] input io_out_3_req_ready, // @[RegisterFile.scala:28:14] output io_out_3_req_valid, // @[RegisterFile.scala:28:14] output [4:0] io_out_3_req_bits_eg, // @[RegisterFile.scala:28:14] input [127:0] io_out_3_resp // @[RegisterFile.scala:28:14] ); wire _arbs_3_io_in_0_ready; // @[RegisterFile.scala:33:38] wire _arbs_3_io_in_1_ready; // @[RegisterFile.scala:33:38] wire _arbs_3_io_in_2_ready; // @[RegisterFile.scala:33:38] wire _arbs_2_io_in_0_ready; // @[RegisterFile.scala:33:38] wire _arbs_2_io_in_1_ready; // @[RegisterFile.scala:33:38] wire _arbs_2_io_in_2_ready; // @[RegisterFile.scala:33:38] wire _arbs_1_io_in_0_ready; // @[RegisterFile.scala:33:38] wire _arbs_1_io_in_1_ready; // @[RegisterFile.scala:33:38] wire _arbs_1_io_in_2_ready; // @[RegisterFile.scala:33:38] wire _arbs_0_io_in_0_ready; // @[RegisterFile.scala:33:38] wire _arbs_0_io_in_1_ready; // @[RegisterFile.scala:33:38] wire _arbs_0_io_in_2_ready; // @[RegisterFile.scala:33:38] wire _io_in_0_resp_T = io_in_0_req_bits_eg[1:0] == 2'h0; // @[RegisterFile.scala:41:82, :43:63] wire [4:0] arbs_3_io_in_0_bits_eg = {2'h0, io_in_0_req_bits_eg[4:2]}; // @[RegisterFile.scala:44:{32,56}] wire _io_in_0_resp_T_1 = io_in_0_req_bits_eg[1:0] == 2'h1; // @[RegisterFile.scala:41:82, :43:63] wire _io_in_0_resp_T_2 = io_in_0_req_bits_eg[1:0] == 2'h2; // @[RegisterFile.scala:41:82, :43:63] wire _io_in_1_resp_T = io_in_1_req_bits_eg[1:0] == 2'h0; // @[RegisterFile.scala:41:82, :43:63] wire [4:0] arbs_3_io_in_1_bits_eg = {2'h0, io_in_1_req_bits_eg[4:2]}; // @[RegisterFile.scala:44:{32,56}] wire _io_in_1_resp_T_1 = io_in_1_req_bits_eg[1:0] == 2'h1; // @[RegisterFile.scala:41:82, :43:63] wire _io_in_1_resp_T_2 = io_in_1_req_bits_eg[1:0] == 2'h2; // @[RegisterFile.scala:41:82, :43:63] wire _io_in_2_resp_T = io_in_2_req_bits_eg[1:0] == 2'h0; // @[RegisterFile.scala:41:82, :43:63] wire [4:0] arbs_3_io_in_2_bits_eg = {2'h0, io_in_2_req_bits_eg[4:2]}; // @[RegisterFile.scala:44:{32,56}] wire _io_in_2_resp_T_1 = io_in_2_req_bits_eg[1:0] == 2'h1; // @[RegisterFile.scala:41:82, :43:63] wire _io_in_2_resp_T_2 = io_in_2_req_bits_eg[1:0] == 2'h2; // @[RegisterFile.scala:41:82, :43:63] OldestRRArbiter arbs_0 ( // @[RegisterFile.scala:33:38] .clock (clock), .io_in_0_ready (_arbs_0_io_in_0_ready), .io_in_0_valid (io_in_0_req_valid & _io_in_0_resp_T), // @[RegisterFile.scala:43:{52,63}] .io_in_0_bits_eg (arbs_3_io_in_0_bits_eg), // @[RegisterFile.scala:44:32] .io_in_0_bits_oldest (io_in_0_req_bits_oldest), .io_in_1_ready (_arbs_0_io_in_1_ready), .io_in_1_valid (io_in_1_req_valid & _io_in_1_resp_T), // @[RegisterFile.scala:43:{52,63}] .io_in_1_bits_eg (arbs_3_io_in_1_bits_eg), // @[RegisterFile.scala:44:32] .io_in_1_bits_oldest (io_in_1_req_bits_oldest), .io_in_2_ready (_arbs_0_io_in_2_ready), .io_in_2_valid (io_in_2_req_valid & _io_in_2_resp_T), // @[RegisterFile.scala:43:{52,63}] .io_in_2_bits_eg (arbs_3_io_in_2_bits_eg), // @[RegisterFile.scala:44:32] .io_out_ready (io_out_0_req_ready), .io_out_valid (io_out_0_req_valid), .io_out_bits_eg (io_out_0_req_bits_eg) ); // @[RegisterFile.scala:33:38] OldestRRArbiter arbs_1 ( // @[RegisterFile.scala:33:38] .clock (clock), .io_in_0_ready (_arbs_1_io_in_0_ready), .io_in_0_valid (io_in_0_req_valid & _io_in_0_resp_T_1), // @[RegisterFile.scala:43:{52,63}] .io_in_0_bits_eg (arbs_3_io_in_0_bits_eg), // @[RegisterFile.scala:44:32] .io_in_0_bits_oldest (io_in_0_req_bits_oldest), .io_in_1_ready (_arbs_1_io_in_1_ready), .io_in_1_valid (io_in_1_req_valid & _io_in_1_resp_T_1), // @[RegisterFile.scala:43:{52,63}] .io_in_1_bits_eg (arbs_3_io_in_1_bits_eg), // @[RegisterFile.scala:44:32] .io_in_1_bits_oldest (io_in_1_req_bits_oldest), .io_in_2_ready (_arbs_1_io_in_2_ready), .io_in_2_valid (io_in_2_req_valid & _io_in_2_resp_T_1), // @[RegisterFile.scala:43:{52,63}] .io_in_2_bits_eg (arbs_3_io_in_2_bits_eg), // @[RegisterFile.scala:44:32] .io_out_ready (io_out_1_req_ready), .io_out_valid (io_out_1_req_valid), .io_out_bits_eg (io_out_1_req_bits_eg) ); // @[RegisterFile.scala:33:38] OldestRRArbiter arbs_2 ( // @[RegisterFile.scala:33:38] .clock (clock), .io_in_0_ready (_arbs_2_io_in_0_ready), .io_in_0_valid (io_in_0_req_valid & _io_in_0_resp_T_2), // @[RegisterFile.scala:43:{52,63}] .io_in_0_bits_eg (arbs_3_io_in_0_bits_eg), // @[RegisterFile.scala:44:32] .io_in_0_bits_oldest (io_in_0_req_bits_oldest), .io_in_1_ready (_arbs_2_io_in_1_ready), .io_in_1_valid (io_in_1_req_valid & _io_in_1_resp_T_2), // @[RegisterFile.scala:43:{52,63}] .io_in_1_bits_eg (arbs_3_io_in_1_bits_eg), // @[RegisterFile.scala:44:32] .io_in_1_bits_oldest (io_in_1_req_bits_oldest), .io_in_2_ready (_arbs_2_io_in_2_ready), .io_in_2_valid (io_in_2_req_valid & _io_in_2_resp_T_2), // @[RegisterFile.scala:43:{52,63}] .io_in_2_bits_eg (arbs_3_io_in_2_bits_eg), // @[RegisterFile.scala:44:32] .io_out_ready (io_out_2_req_ready), .io_out_valid (io_out_2_req_valid), .io_out_bits_eg (io_out_2_req_bits_eg) ); // @[RegisterFile.scala:33:38] OldestRRArbiter arbs_3 ( // @[RegisterFile.scala:33:38] .clock (clock), .io_in_0_ready (_arbs_3_io_in_0_ready), .io_in_0_valid (io_in_0_req_valid & (&(io_in_0_req_bits_eg[1:0]))), // @[RegisterFile.scala:41:82, :43:{52,63}] .io_in_0_bits_eg (arbs_3_io_in_0_bits_eg), // @[RegisterFile.scala:44:32] .io_in_0_bits_oldest (io_in_0_req_bits_oldest), .io_in_1_ready (_arbs_3_io_in_1_ready), .io_in_1_valid (io_in_1_req_valid & (&(io_in_1_req_bits_eg[1:0]))), // @[RegisterFile.scala:41:82, :43:{52,63}] .io_in_1_bits_eg (arbs_3_io_in_1_bits_eg), // @[RegisterFile.scala:44:32] .io_in_1_bits_oldest (io_in_1_req_bits_oldest), .io_in_2_ready (_arbs_3_io_in_2_ready), .io_in_2_valid (io_in_2_req_valid & (&(io_in_2_req_bits_eg[1:0]))), // @[RegisterFile.scala:41:82, :43:{52,63}] .io_in_2_bits_eg (arbs_3_io_in_2_bits_eg), // @[RegisterFile.scala:44:32] .io_out_ready (io_out_3_req_ready), .io_out_valid (io_out_3_req_valid), .io_out_bits_eg (io_out_3_req_bits_eg) ); // @[RegisterFile.scala:33:38] assign io_in_0_req_ready = _io_in_0_resp_T & _arbs_0_io_in_0_ready \| _io_in_0_resp_T_1 & _arbs_1_io_in_0_ready \| _io_in_0_resp_T_2 & _arbs_2_io_in_0_ready \| (&(io_in_0_req_bits_eg[1:0])) & _arbs_3_io_in_0_ready; // @[Mux.scala:30:73] assign io_in_0_resp = (_io_in_0_resp_T ? io_out_0_resp : 128'h0) \| (_io_in_0_resp_T_1 ? io_out_1_resp : 128'h0) \| (_io_in_0_resp_T_2 ? io_out_2_resp : 128'h0) \| ((&(io_in_0_req_bits_eg[1:0])) ? io_out_3_resp : 128'h0); // @[Mux.scala:30:73] assign io_in_1_req_ready = _io_in_1_resp_T & _arbs_0_io_in_1_ready \| _io_in_1_resp_T_1 & _arbs_1_io_in_1_ready \| _io_in_1_resp_T_2 & _arbs_2_io_in_1_ready \| (&(io_in_1_req_bits_eg[1:0])) & _arbs_3_io_in_1_ready; // @[Mux.scala:30:73] assign io_in_1_resp = (_io_in_1_resp_T ? io_out_0_resp : 128'h0) \| (_io_in_1_resp_T_1 ? io_out_1_resp : 128'h0) \| (_io_in_1_resp_T_2 ? io_out_2_resp : 128'h0) \| ((&(io_in_1_req_bits_eg[1:0])) ? io_out_3_resp : 128'h0); // @[Mux.scala:30:73] assign io_in_2_req_ready = _io_in_2_resp_T & _arbs_0_io_in_2_ready \| _io_in_2_resp_T_1 & _arbs_1_io_in_2_ready \| _io_in_2_resp_T_2 & _arbs_2_io_in_2_ready \| (&(io_in_2_req_bits_eg[1:0])) & _arbs_3_io_in_2_ready; // @[Mux.scala:30:73] assign io_in_2_resp = (_io_in_2_resp_T ? io_out_0_resp : 128'h0) \| (_io_in_2_resp_T_1 ? io_out_1_resp : 128'h0) \| (_io_in_2_resp_T_2 ? io_out_2_resp : 128'h0) \| ((&(io_in_2_req_bits_eg[1:0])) ? io_out_3_resp : 128'h0); // @[Mux.scala:30:73] endmodule
Generate the Verilog code corresponding to the following Chisel files. File FFT.scala: //**************************************************************************** // Copyright (c) 2021-2022, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE for license details. //------------------------------------------------------------------------------ package fftgenerator import chisel3.util._ import chisel3._ import craft._ import dsptools._ import dsptools.numbers._ import dsptools.numbers.implicits._ import dspjunctions._ import dspblocks._ import scala.math._ import fixedpoint._ import fixedpoint.{fromIntToBinaryPoint} class DirectFFTIO[T<:Data:Real](genMid: DspComplex[T], genOut: DspComplex[T], lanes: Int) extends Bundle { val in = Input(ValidWithSync(Vec(lanes, genMid))) val out = Output(ValidWithSync(Vec(lanes, genOut))) } / * fast fourier transform - cooley-tukey algorithm, decimation-in-time * direct form version * note, this is always a p-point FFT, though the twiddle factors will be different if p < n * @tparam T / class DirectFFT[T<:Data:Real](params: FFTConfig[T], genMid: DspComplex[T], genTwiddle: DspComplex[T], genOutFull: DspComplex[T]) extends Module { val io = IO(new DirectFFTIO[T](genMid, genOutFull, params.lanes)) // synchronize val valid_delay = RegNext(io.in.valid) val sync = CounterWithReset(true.B, params.bp, io.in.sync, ~valid_delay & io.in.valid)._1 io.out.sync := ShiftRegisterWithReset(io.in.valid && sync === (params.bp-1).U, params.direct_pipe, 0.U) // should valid keep sync from propagating? io.out.valid := ShiftRegisterWithReset(io.in.valid, params.direct_pipe, 0.U) // wire up twiddles val genTwiddleReal = genTwiddle.real val genTwiddleImag = genTwiddle.imag val twiddle_rom = VecInit(params.twiddle.map( x => { val real = Wire(genTwiddleReal.cloneType) val imag = Wire(genTwiddleImag.cloneType) real := Real[T].fromDouble(x(0), genTwiddleReal) imag := Real[T].fromDouble(x(1), genTwiddleImag) val twiddle = Wire(DspComplex(genTwiddleReal, genTwiddleImag)) twiddle.real := real twiddle.imag := imag twiddle })) val indices_rom = VecInit(params.dindices.map(x => x.U)) val start = sync(params.lanes-1).U val twiddle = Wire(Vec(params.lanes-1, genTwiddle.cloneType)) // special case when n = 4, because the pattern breaks down if (params.n == 4) { twiddle := VecInit((0 until params.lanes-1).map(x => { val true_branch = Wire(genTwiddle) true_branch := twiddle_rom(0).divj() val false_branch = Wire(genTwiddle) false_branch := twiddle_rom(0) Mux( indices_rom(start+x.U)(log2Ceil(params.n/4)), true_branch, false_branch ) })) } else { twiddle.zipWithIndex.foreach { case (t, x) => t := { val true_branch = twiddle_rom(indices_rom(start+x.U)(log2Ceil(params.n/4)-1, 0)).divj().asTypeOf(genTwiddle) val false_branch = twiddle_rom(indices_rom(start+x.U)).asTypeOf(genTwiddle) val index = indices_rom(start+x.U) Mux(index(log2Ceil(params.n/4)), true_branch, false_branch ) } } } // p-point decimation-in-time direct form FFT with inputs in normal order // (outputs bit reversed) val stage_outputs = List.fill(log2Ceil(params.lanes)+1)(List.fill(params.lanes)(Wire(genOutFull))) io.in.bits.zip(stage_outputs(0)).foreach { case(in, out) => out := in } // indices to the twiddle Vec var indices = List(List(0,1),List(0,2)) for (i <- 0 until log2Ceil(params.lanes)-2) { indices = indices.map(x => x.map(y => y+1)) val indices_max = indices.foldLeft(0)((b,a) => max(b,a.reduceLeft((d,c) => max(c,d)))) indices = indices ++ indices.map(x => x.map(y => y+indices_max)) indices = indices.map(x => 0 +: x) } // create the FFT hardware for (i <- 0 until log2Ceil(params.lanes)) { for (j <- 0 until params.lanes/2) { val skip = pow(2,log2Ceil(params.n/2)-(i+log2Ceil(params.bp))).toInt val start = ((j % skip) + floor(j/skip) * skip2).toInt // hook it up val outputs = List(stage_outputs(i+1)(start), stage_outputs(i+1)(start+skip)) val shr_delay = params.pipe.drop(log2Ceil(params.bp)).dropRight(log2Ceil(params.lanes)-i).foldLeft(0)(_+_) val shr = ShiftRegisterMem[DspComplex[T]](twiddle(indices(j)(i)), shr_delay, name = this.name + s"_${i}_${j}_twiddle_sram") val butterfly_outputs = Butterfly[T](Seq(stage_outputs(i)(start), stage_outputs(i)(start+skip)), shr) outputs.zip(butterfly_outputs).foreach { x => x._1 := ShiftRegisterMem(x._2, params.pipe(i+log2Ceil(params.bp)), name = this.name + s"_${i}_${j}_pipeline_sram") } } } // wire up top-level outputs // note, truncation happens here! io.out.bits := stage_outputs(log2Ceil(params.lanes)) } class BiplexFFTIO[T<:Data:Real](lanes: Int, genIn: DspComplex[T], genMid: DspComplex[T]) extends Bundle { val in = Input(ValidWithSync(Vec(lanes, genIn))) val out = Output(ValidWithSync(Vec(lanes, genMid))) } /* * fast fourier transform - cooley-tukey algorithm, decimation-in-time * biplex pipelined version * note, this is always a bp-point FFT * @tparam T / class BiplexFFT[T<:Data:Real](params: FFTConfig[T], genMid: DspComplex[T], genTwiddle: DspComplex[T]) extends Module { val io = IO(new BiplexFFTIO[T](params.lanes, params.genIn, genMid)) // synchronize val stage_delays = (0 until log2Ceil(params.bp)+1).map(x => { if (x == log2Ceil(params.bp)) params.bp/2 else (params.bp/pow(2,x+1)).toInt }) val sync = List.fill(log2Ceil(params.bp)+1)(Wire(UInt(width=log2Ceil(params.bp).W))) val valid_delay = RegNext(io.in.valid) sync(0) := CounterWithReset(true.B, params.bp, io.in.sync, ~valid_delay & io.in.valid)._1 sync.drop(1).zip(sync).zip(stage_delays).foreach { case ((next, prev), delay) => next := ShiftRegisterWithReset(prev, delay, 0.U) } io.out.sync := sync(log2Ceil(params.bp)) === ((params.bp/2-1+params.biplex_pipe)%params.bp).U io.out.valid := ShiftRegisterWithReset(io.in.valid, stage_delays.reduce(_+_) + params.biplex_pipe, 0.U) // wire up twiddles val genTwiddleReal = genTwiddle.real val genTwiddleImag = genTwiddle.imag val twiddle_rom = VecInit(params.twiddle.map(x => { val real = Wire(genTwiddleReal.cloneType) val imag = Wire(genTwiddleImag.cloneType) real := Real[T].fromDouble(x(0), genTwiddleReal) imag := Real[T].fromDouble(x(1), genTwiddleImag) val twiddle = Wire(DspComplex(genTwiddleReal, genTwiddleImag)) twiddle.real := real twiddle.imag := imag twiddle })) val indices_rom = VecInit(params.bindices.map(x => x.U)) val indices = (0 until log2Ceil(params.bp)).map(x => indices_rom((pow(2,x)-1).toInt.U +& { if (x == 0) 0.U else ShiftRegisterMem(sync(x+1), params.pipe.dropRight(log2Ceil(params.n)-x).reduceRight(_+_), name = this.name + s"_twiddle_sram")(log2Ceil(params.bp)-2,log2Ceil(params.bp)-1-x) })) val twiddle = Wire(Vec(log2Ceil(params.bp), genTwiddle)) // special cases if (params.n == 4) { twiddle := VecInit((0 until log2Ceil(params.bp)).map(x => { val true_branch = Wire(genTwiddle) val false_branch = Wire(genTwiddle) true_branch := twiddle_rom(0).divj() false_branch := twiddle_rom(0) Mux(indices(x)(log2Ceil(params.n/4)), true_branch, false_branch) })) } else if (params.bp == 2) { twiddle := VecInit((0 until log2Ceil(params.bp)).map(x => twiddle_rom(indices(x)) )) } else { twiddle := VecInit((0 until log2Ceil(params.bp)).map(x => { val true_branch = Wire(genTwiddle) val false_branch = Wire(genTwiddle) true_branch := twiddle_rom(indices(x)(log2Ceil(params.n/4)-1, 0)).divj() false_branch := twiddle_rom(indices(x)) Mux(indices(x)(log2Ceil(params.n/4)), true_branch, false_branch) })) } // bp-point decimation-in-time biplex pipelined FFT with outputs in bit-reversed order // up-scale to genMid immediately for simplicity val stage_outputs = List.fill(log2Ceil(params.bp)+2)(List.fill(params.lanes)(Wire(genMid))) io.in.bits.zip(stage_outputs(0)).foreach { case(in, out) => out := in } // create the FFT hardware for (i <- 0 until log2Ceil(params.bp)+1) { for (j <- 0 until params.lanes/2) { val skip = 1 val start = j2 // hook it up // last stage just has one extra permutation, no butterfly val mux_out = BarrelShifter(VecInit(stage_outputs(i)(start), ShiftRegisterMem(stage_outputs(i)(start+skip), stage_delays(i), name = this.name + s"_${i}_${j}_mux1_sram")), ShiftRegisterMem(sync(i)(log2Ceil(params.bp)-1 - { if (i == log2Ceil(params.bp)) 0 else i }), {if (i == 0) 0 else params.pipe.dropRight(log2Ceil(params.n)-i).reduceRight(_+_)}, name = this.name + s"_${i}_${j}_mux1_sram")) if (i == log2Ceil(params.bp)) { Seq(stage_outputs(i+1)(start), stage_outputs(i+1)(start+skip)).zip(Seq(ShiftRegisterMem(mux_out(0), stage_delays(i), name = this.name + s"_${i}_${j}_last_sram" ), mux_out(1))).foreach { x => x._1 := x._2 } } else { Seq(stage_outputs(i+1)(start), stage_outputs(i+1)(start+skip)).zip(Butterfly(Seq(ShiftRegisterMem(mux_out(0), stage_delays(i), name = this.name + s"_${i}_${j}_pipeline0_sram"), mux_out(1)), twiddle(i))).foreach { x => x._1 := ShiftRegisterMem(x._2, params.pipe(i), name = this.name + s"_${i}_${j}_pipeline1_sram") } } } } // wire up top-level outputs io.out.bits := stage_outputs(log2Ceil(params.bp)+1) } /** * IO Bundle for FFT * @tparam T / class FFTIO[T<:Data:Real](lanes: Int, genIn: DspComplex[T], genOut: DspComplex[T]) extends Bundle { val in = Input(ValidWithSync(Vec(lanes, genIn))) val out = Output(ValidWithSync(Vec(lanes, genOut))) } /* * fast fourier transform - cooley-tukey algorithm, decimation-in-time * mixed version * note, this is always an n-point FFT * @tparam T */ class FFT[T<:Data:Real](val params: FFTConfig[T]) extends Module { require(params.lanes >= 2, "Must have at least 2 parallel inputs") require(isPow2(params.lanes), "FFT parallelism must be a power of 2") require(params.lanes <= params.n, "An n-point FFT cannot have more than n inputs (p must be less than or equal to n)") val io = IO(new FFTIO(params.lanes, params.genIn, params.genOut)) // calculate direct FFT input bitwidth // this is just the input total width + growth of 1 bit per biplex stage val genMid: DspComplex[T] = { if (params.bp == 1) { params.genIn } else { val growth = log2Ceil(params.bp) params.genIn.underlyingType() match { case "fixed" => params.genIn.real.asInstanceOf[FixedPoint].binaryPoint match { case KnownBinaryPoint(binaryPoint) => val totalBits = params.genIn.real.getWidth + growth DspComplex(FixedPoint(totalBits.W, binaryPoint.BP), FixedPoint(totalBits.W, binaryPoint.BP)).asInstanceOf[DspComplex[T]] case _ => throw new DspException("Error: unknown binary point when calculating FFT bitwdiths") } case "sint" => { val totalBits = params.genIn.real.getWidth + growth DspComplex(SInt(totalBits.W), SInt(totalBits.W)).asInstanceOf[DspComplex[T]] } case _ => throw new DspException("Error: unknown type when calculating FFT bitwidths") } } } // calculate twiddle factor bitwidth // total input bits val genTwiddleBiplex: DspComplex[T] = { val growth = log2Ceil(params.bp) params.genIn.asInstanceOf[DspComplex[T]].underlyingType() match { case "fixed" => params.genIn.asInstanceOf[DspComplex[T]].real.asInstanceOf[FixedPoint].binaryPoint match { case KnownBinaryPoint(binaryPoint) => val totalBits = params.genIn.asInstanceOf[DspComplex[T]].real.getWidth + growth DspComplex(FixedPoint(totalBits.W, (totalBits-2).BP), FixedPoint(totalBits.W, (totalBits-2).BP)).asInstanceOf[DspComplex[T]] case _ => throw new DspException("Error: unknown binary point when calculating FFT bitwdiths") } case "sint" => { val totalBits = params.genIn.asInstanceOf[DspComplex[T]].real.getWidth + growth DspComplex(SInt(totalBits.W), SInt(totalBits.W)).asInstanceOf[DspComplex[T]] } case _ => throw new DspException("Error: unknown type when calculating FFT bitwidths") } } val genTwiddleDirect: DspComplex[T] = { val growth = log2Ceil(params.n) params.genIn.asInstanceOf[DspComplex[T]].underlyingType() match { case "fixed" => params.genIn.asInstanceOf[DspComplex[T]].real.asInstanceOf[FixedPoint].binaryPoint match { case KnownBinaryPoint(binaryPoint) => val totalBits = params.genIn.asInstanceOf[DspComplex[T]].real.getWidth + growth DspComplex(FixedPoint(totalBits.W, (totalBits-2).BP), FixedPoint(totalBits.W, (totalBits-2).BP)).asInstanceOf[DspComplex[T]] case _ => throw new DspException("Error: unknown binary point when calculating FFT bitwdiths") } case "sint" => { val totalBits = params.genIn.asInstanceOf[DspComplex[T]].real.getWidth + growth DspComplex(SInt(totalBits.W), SInt(totalBits.W)).asInstanceOf[DspComplex[T]] } case _ => throw new DspException("Error: unknown type when calculating FFT bitwidths") } } // calculate direct FFT output bitwidth // this is just the input total width + growth of 1 bit per FFT stage val genOutDirect: DspComplex[T] = { if (params.bp == 1) { params.genIn } else { val growth = log2Ceil(params.n) params.genIn.asInstanceOf[DspComplex[T]].underlyingType() match { case "fixed" => params.genIn.asInstanceOf[DspComplex[T]].real.asInstanceOf[FixedPoint].binaryPoint match { case KnownBinaryPoint(binaryPoint) => val totalBits = params.genIn.asInstanceOf[DspComplex[T]].real.getWidth + growth DspComplex(FixedPoint(totalBits.W, binaryPoint.BP), FixedPoint(totalBits.W, binaryPoint.BP)).asInstanceOf[DspComplex[T]] case _ => throw new DspException("Error: unknown binary point when calculating FFT bitwdiths") } case "sint" => { val totalBits = params.genIn.asInstanceOf[DspComplex[T]].real.getWidth + growth DspComplex(SInt(totalBits.W), SInt(totalBits.W)).asInstanceOf[DspComplex[T]] } case _ => throw new DspException("Error: unknown type when calculating FFT bitwidths") } } } // feed in zeros when invalid val in = Wire(ValidWithSync(Vec(params.lanes, params.genIn))) when (io.in.valid) { in.bits := io.in.bits } .otherwise { in.bits.foreach { case b => b.real := Real[T].zero b.imag := Real[T].zero } } in.valid := io.in.valid in.sync := io.in.sync // instantiate sub-FFTs val direct = Module(new DirectFFT[T]( params = params, genMid = genMid, genTwiddle = genTwiddleDirect, genOutFull = genOutDirect )) io.out <> direct.io.out if (params.n != params.lanes) { val biplex = Module(new BiplexFFT[T](params, genMid, genTwiddleBiplex)) direct.io.in := biplex.io.out biplex.io.in <> in } else { direct.io.in <> in } }	module FFT( // @[FFT.scala:230:7] input io_in_valid, // @[FFT.scala:236:14] input [15:0] io_in_bits_0_real, // @[FFT.scala:236:14] input [15:0] io_in_bits_0_imag, // @[FFT.scala:236:14] input [15:0] io_in_bits_1_real, // @[FFT.scala:236:14] input [15:0] io_in_bits_1_imag, // @[FFT.scala:236:14] input [15:0] io_in_bits_2_real, // @[FFT.scala:236:14] input [15:0] io_in_bits_2_imag, // @[FFT.scala:236:14] input [15:0] io_in_bits_3_real, // @[FFT.scala:236:14] input [15:0] io_in_bits_3_imag, // @[FFT.scala:236:14] input [15:0] io_in_bits_4_real, // @[FFT.scala:236:14] input [15:0] io_in_bits_4_imag, // @[FFT.scala:236:14] input [15:0] io_in_bits_5_real, // @[FFT.scala:236:14] input [15:0] io_in_bits_5_imag, // @[FFT.scala:236:14] input [15:0] io_in_bits_6_real, // @[FFT.scala:236:14] input [15:0] io_in_bits_6_imag, // @[FFT.scala:236:14] input [15:0] io_in_bits_7_real, // @[FFT.scala:236:14] input [15:0] io_in_bits_7_imag, // @[FFT.scala:236:14] output io_out_valid, // @[FFT.scala:236:14] output [15:0] io_out_bits_0_real, // @[FFT.scala:236:14] output [15:0] io_out_bits_0_imag, // @[FFT.scala:236:14] output [15:0] io_out_bits_1_real, // @[FFT.scala:236:14] output [15:0] io_out_bits_1_imag, // @[FFT.scala:236:14] output [15:0] io_out_bits_2_real, // @[FFT.scala:236:14] output [15:0] io_out_bits_2_imag, // @[FFT.scala:236:14] output [15:0] io_out_bits_3_real, // @[FFT.scala:236:14] output [15:0] io_out_bits_3_imag, // @[FFT.scala:236:14] output [15:0] io_out_bits_4_real, // @[FFT.scala:236:14] output [15:0] io_out_bits_4_imag, // @[FFT.scala:236:14] output [15:0] io_out_bits_5_real, // @[FFT.scala:236:14] output [15:0] io_out_bits_5_imag, // @[FFT.scala:236:14] output [15:0] io_out_bits_6_real, // @[FFT.scala:236:14] output [15:0] io_out_bits_6_imag, // @[FFT.scala:236:14] output [15:0] io_out_bits_7_real, // @[FFT.scala:236:14] output [15:0] io_out_bits_7_imag // @[FFT.scala:236:14] ); DirectFFT direct ( // @[FFT.scala:336:22] .io_in_valid (io_in_valid), .io_in_bits_0_real (io_in_valid ? io_in_bits_0_real : 16'h0), // @[FFT.scala:324:22, :325:13, :328:14] .io_in_bits_0_imag (io_in_valid ? io_in_bits_0_imag : 16'h0), // @[FFT.scala:324:22, :325:13, :329:14] .io_in_bits_1_real (io_in_valid ? io_in_bits_1_real : 16'h0), // @[FFT.scala:324:22, :325:13, :328:14] .io_in_bits_1_imag (io_in_valid ? io_in_bits_1_imag : 16'h0), // @[FFT.scala:324:22, :325:13, :329:14] .io_in_bits_2_real (io_in_valid ? io_in_bits_2_real : 16'h0), // @[FFT.scala:324:22, :325:13, :328:14] .io_in_bits_2_imag (io_in_valid ? io_in_bits_2_imag : 16'h0), // @[FFT.scala:324:22, :325:13, :329:14] .io_in_bits_3_real (io_in_valid ? io_in_bits_3_real : 16'h0), // @[FFT.scala:324:22, :325:13, :328:14] .io_in_bits_3_imag (io_in_valid ? io_in_bits_3_imag : 16'h0), // @[FFT.scala:324:22, :325:13, :329:14] .io_in_bits_4_real (io_in_valid ? io_in_bits_4_real : 16'h0), // @[FFT.scala:324:22, :325:13, :328:14] .io_in_bits_4_imag (io_in_valid ? io_in_bits_4_imag : 16'h0), // @[FFT.scala:324:22, :325:13, :329:14] .io_in_bits_5_real (io_in_valid ? io_in_bits_5_real : 16'h0), // @[FFT.scala:324:22, :325:13, :328:14] .io_in_bits_5_imag (io_in_valid ? io_in_bits_5_imag : 16'h0), // @[FFT.scala:324:22, :325:13, :329:14] .io_in_bits_6_real (io_in_valid ? io_in_bits_6_real : 16'h0), // @[FFT.scala:324:22, :325:13, :328:14] .io_in_bits_6_imag (io_in_valid ? io_in_bits_6_imag : 16'h0), // @[FFT.scala:324:22, :325:13, :329:14] .io_in_bits_7_real (io_in_valid ? io_in_bits_7_real : 16'h0), // @[FFT.scala:324:22, :325:13, :328:14] .io_in_bits_7_imag (io_in_valid ? io_in_bits_7_imag : 16'h0), // @[FFT.scala:324:22, :325:13, :329:14] .io_out_valid (io_out_valid), .io_out_bits_0_real (io_out_bits_0_real), .io_out_bits_0_imag (io_out_bits_0_imag), .io_out_bits_1_real (io_out_bits_1_real), .io_out_bits_1_imag (io_out_bits_1_imag), .io_out_bits_2_real (io_out_bits_2_real), .io_out_bits_2_imag (io_out_bits_2_imag), .io_out_bits_3_real (io_out_bits_3_real), .io_out_bits_3_imag (io_out_bits_3_imag), .io_out_bits_4_real (io_out_bits_4_real), .io_out_bits_4_imag (io_out_bits_4_imag), .io_out_bits_5_real (io_out_bits_5_real), .io_out_bits_5_imag (io_out_bits_5_imag), .io_out_bits_6_real (io_out_bits_6_real), .io_out_bits_6_imag (io_out_bits_6_imag), .io_out_bits_7_real (io_out_bits_7_real), .io_out_bits_7_imag (io_out_bits_7_imag) ); // @[FFT.scala:336:22] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Decode.scala: // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.BitPat import chisel3.util.experimental.decode._ object DecodeLogic { // TODO This should be a method on BitPat private def hasDontCare(bp: BitPat): Boolean = bp.mask.bitCount != bp.width // Pads BitPats that are safe to pad (no don't cares), errors otherwise private def padBP(bp: BitPat, width: Int): BitPat = { if (bp.width == width) bp else { require(!hasDontCare(bp), s"Cannot pad '$bp' to '$width' bits because it has don't cares") val diff = width - bp.width require(diff > 0, s"Cannot pad '$bp' to '$width' because it is already '${bp.width}' bits wide!") BitPat(0.U(diff.W)) ## bp } } def apply(addr: UInt, default: BitPat, mapping: Iterable[(BitPat, BitPat)]): UInt = chisel3.util.experimental.decode.decoder(QMCMinimizer, addr, TruthTable(mapping, default)) def apply(addr: UInt, default: Seq[BitPat], mappingIn: Iterable[(BitPat, Seq[BitPat])]): Seq[UInt] = { val nElts = default.size require(mappingIn.forall(_._2.size == nElts), s"All Seq[BitPat] must be of the same length, got $nElts vs. ${mappingIn.find(_._2.size != nElts).get}" ) val elementsGrouped = mappingIn.map(_._2).transpose val elementWidths = elementsGrouped.zip(default).map { case (elts, default) => (default :: elts.toList).map(_.getWidth).max } val resultWidth = elementWidths.sum val elementIndices = elementWidths.scan(resultWidth - 1) { case (l, r) => l - r } // All BitPats that correspond to a given element in the result must have the same width in the // chisel3 decoder. We will zero pad any BitPats that are too small so long as they dont have // any don't cares. If there are don't cares, it is an error and the user needs to pad the // BitPat themselves val defaultsPadded = default.zip(elementWidths).map { case (bp, w) => padBP(bp, w) } val mappingInPadded = mappingIn.map { case (in, elts) => in -> elts.zip(elementWidths).map { case (bp, w) => padBP(bp, w) } } val decoded = apply(addr, defaultsPadded.reduce(_ ## _), mappingInPadded.map { case (in, out) => (in, out.reduce(_ ## _)) }) elementIndices.zip(elementIndices.tail).map { case (msb, lsb) => decoded(msb, lsb + 1) }.toList } def apply(addr: UInt, default: Seq[BitPat], mappingIn: List[(UInt, Seq[BitPat])]): Seq[UInt] = apply(addr, default, mappingIn.map(m => (BitPat(m._1), m._2)).asInstanceOf[Iterable[(BitPat, Seq[BitPat])]]) def apply(addr: UInt, trues: Iterable[UInt], falses: Iterable[UInt]): Bool = apply(addr, BitPat.dontCare(1), trues.map(BitPat(_) -> BitPat("b1")) ++ falses.map(BitPat(_) -> BitPat("b0"))).asBool } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File util.scala: //*************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v4.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v4.common.{MicroOp} import boom.v4.exu.{BrUpdateInfo} / * Object to XOR fold a input register of fullLength into a compressedLength. / object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /* * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks / object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, flush: Bool, uop: MicroOp): Bool = { return apply(brupdate, flush, uop.br_mask) } def apply(brupdate: BrUpdateInfo, flush: Bool, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) \|\| flush } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: T): Bool = { return apply(brupdate, flush, bundle.uop) } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Bool = { return apply(brupdate, flush, bundle.bits) } } /* * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. / object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /* * Object to return a BR mask given a MicroOp mask and old BR mask. / object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, flush, bundle.bits.uop.br_mask) out } } /* * Object to check if at least 1 bit matches in two masks / object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /* * Object to clear one bit in a mask given an index / object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /* * Object to shift a register over by one bit and concat a new one / object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /* * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. / object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /* * Object to increment an input value, wrapping it if * necessary. / object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /* * Object to decrement an input value, wrapping it if * necessary. / object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /* * Object to increment an input value, wrapping it if * necessary. / object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /* * Object to decrement an input value, wrapping it if * necessary. / object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /* * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. / object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc \| (b-1).U) } } /* * Object to rotate a signal left by one / object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /* * Object to sext a value to a particular length. / object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /* * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. / object ImmGen { import boom.v4.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U, IS_N} def apply(i: UInt, isel: UInt): UInt = { val ip = Mux(isel === IS_N, 0.U(LONGEST_IMM_SZ.W), i) val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U \|\| isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J \|\| isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S \|\| isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0) } } /* * Object to see if an instruction is a JALR. / object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /* * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). / object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /* * Object to return the lowest bit position after the head. / object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /* * Object to determine whether queue * index i0 is older than index i1. / object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } object IsYoungerMask { def apply(i: UInt, head: UInt, n: Integer): UInt = { val hi_mask = ~MaskLower(UIntToOH(i)(n-1,0)) val lo_mask = ~MaskUpper(UIntToOH(head)(n-1,0)) Mux(i < head, hi_mask & lo_mask, hi_mask \| lo_mask)(n-1,0) } } /* * Set all bits at or below the highest order '1'. / object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_\|_) } } /* * Set all bits at or above the lowest order '1'. / object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_\|_) } } /* * Transpose a matrix of Chisel Vecs. / object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /* * N-wide one-hot priority encoder. / object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /* * Connect the first k of n valid input interfaces to k output interfaces. / class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_\|\|_)) val out_valids = sels map (col => col.reduce(_\|\|_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /* * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). / class BranchKillableQueue[T <: boom.v4.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v4.common.MicroOp => Bool = u => true.B, fastDeq: Boolean = false) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) if (fastDeq && entries > 1) { // Pipeline dequeue selection so the mux gets an entire cycle val main = Module(new BranchKillableQueue(gen, entries-1, flush_fn, false)) val out_reg = Reg(gen) val out_valid = RegInit(false.B) val out_uop = Reg(new MicroOp) main.io.enq <> io.enq main.io.brupdate := io.brupdate main.io.flush := io.flush io.empty := main.io.empty && !out_valid io.count := main.io.count + out_valid io.deq.valid := out_valid io.deq.bits := out_reg io.deq.bits.uop := out_uop out_uop := UpdateBrMask(io.brupdate, out_uop) out_valid := out_valid && !IsKilledByBranch(io.brupdate, false.B, out_uop) && !(io.flush && flush_fn(out_uop)) main.io.deq.ready := false.B when (io.deq.fire \|\| !out_valid) { out_valid := main.io.deq.valid && !IsKilledByBranch(io.brupdate, false.B, main.io.deq.bits.uop) && !(io.flush && flush_fn(main.io.deq.bits.uop)) out_reg := main.io.deq.bits out_uop := UpdateBrMask(io.brupdate, main.io.deq.bits.uop) main.io.deq.ready := true.B } } else { val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire && !IsKilledByBranch(io.brupdate, false.B, io.enq.bits.uop) && !(io.flush && flush_fn(io.enq.bits.uop))) val do_deq = WireInit((io.deq.ready \|\| !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, false.B, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) io.deq.bits := out val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /* * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" / def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) / def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) / def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) / def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /* * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) / def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /* * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) / def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /* * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line / def apply(strs: String)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } class BranchKillablePipeline[T <: boom.v4.common.HasBoomUOP](gen: T, stages: Int) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val req = Input(Valid(gen)) val flush = Input(Bool()) val brupdate = Input(new BrUpdateInfo) val resp = Output(Vec(stages, Valid(gen))) }) require(stages > 0) val uops = Reg(Vec(stages, Valid(gen))) uops(0).valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.flush, io.req.bits) uops(0).bits := UpdateBrMask(io.brupdate, io.req.bits) for (i <- 1 until stages) { uops(i).valid := uops(i-1).valid && !IsKilledByBranch(io.brupdate, io.flush, uops(i-1).bits) uops(i).bits := UpdateBrMask(io.brupdate, uops(i-1).bits) } for (i <- 0 until stages) { when (reset.asBool) { uops(i).valid := false.B } } io.resp := uops } File decode.scala: //**************************************************************************** // Copyright (c) 2015 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ package boom.v4.exu import chisel3._ import chisel3.util._ import freechips.rocketchip.tile.FPConstants import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket.Instructions32 import freechips.rocketchip.rocket.CustomInstructions._ import freechips.rocketchip.rocket.RVCExpander import freechips.rocketchip.rocket.ALU._ import freechips.rocketchip.rocket.{CSR, Causes, DecodeLogic} import freechips.rocketchip.util._ import boom.v4.common._ import boom.v4.util._ // scalastyle:off / * Abstract trait giving defaults and other relevant values to different Decode constants/ / object DecodeTables extends freechips.rocketchip.rocket.constants.ScalarOpConstants with freechips.rocketchip.rocket.constants.MemoryOpConstants with freechips.rocketchip.tile.HasFPUParameters { lazy val fLen = 64 lazy val minFLen = 32 def xLen = 64 def xpr64 = Y // TODO inform this from xLen def DC(i: Int) = BitPat.dontCare(i) def fc2oh(fc: Int): UInt = (1 << fc).U(FC_SZ.W) // FP stores generate data through FP F2I, and generate address through MemAddrCalc def FCOH_F2IMEM = ((1 << FC_AGEN) \| (1 << FC_F2I )).U(FC_SZ.W) def FCOH_STORE = ((1 << FC_AGEN) \| (1 << FC_DGEN)).U(FC_SZ.W) def FN_00 = BitPat("b???00") def FN_01 = BitPat("b???01") def FN_10 = BitPat("b???10") def FN_11 = BitPat("b???11") def decode_default: List[BitPat] = // frs3_en // is val inst? \| imm sel // \| is fp inst? \| \| uses_ldq // \| \| rs1 regtype \| \| \| uses_stq is unique? (clear pipeline for it) // \| \| \| rs2 type\| \| \| \| is_amo \| flush on commit // \| \| func unit \| \| \| \| \| \| \| \| \| csr cmd // \| \| \| \| \| \| \| \| \| \| \| \| \| fcn_dw swap12 fma // \| \| \| dst \| \| \| \| \| \| \| mem \| \| \| \| fcn_op \| swap32 \| div // \| \| \| regtype \| \| \| \| \| \| \| cmd \| \| \| \| \| \| \| typeTagIn \| \| sqrt // \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| ldst \| \| \| typeTagOut \| \| wflags // \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| wen \| \| \| \| from_int \| \| \| // \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| ren1 \| \| \| \| \| to_int \| \| \| // \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| ren2 \| \| \| \| \| \| fast \| \| \| // \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| ren3 \| \| \| \| \| \| \| \| \| \| // \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| List(N, N, DC(FC_SZ) , RT_X , DC(2) , DC(2) , X, IS_N, X, X, X, M_X, N, X, CSR.X, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X) def X32_table: Seq[(BitPat, List[BitPat])] = { import Instructions32._; Seq( SLLI -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_SL , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SRLI -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_SR , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SRAI -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_SRA , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X) ) } def X64_table: Seq[(BitPat, List[BitPat])] = Seq( LD -> List(Y, N, fc2oh(FC_AGEN), RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, M_XRD , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), LWU -> List(Y, N, fc2oh(FC_AGEN), RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, M_XRD , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SD -> List(Y, N, FCOH_STORE , RT_X , RT_FIX, RT_FIX, N, IS_S, N, Y, N, M_XWR , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SLLI -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_SL , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SRLI -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_SR , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SRAI -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_SRA , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), ADDIW -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_32 , FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SLLIW -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_32 , FN_SL , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SRAIW -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_32 , FN_SRA , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SRLIW -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_32 , FN_SR , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), ADDW -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_32 , FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SUBW -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_32 , FN_SUB , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SLLW -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_32 , FN_SL , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SRAW -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_32 , FN_SRA , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SRLW -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_32 , FN_SR , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X) ) def X_table: Seq[(BitPat, List[BitPat])] = Seq( LW -> List(Y, N, fc2oh(FC_AGEN), RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, M_XRD , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), LH -> List(Y, N, fc2oh(FC_AGEN), RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, M_XRD , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), LHU -> List(Y, N, fc2oh(FC_AGEN), RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, M_XRD , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), LB -> List(Y, N, fc2oh(FC_AGEN), RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, M_XRD , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), LBU -> List(Y, N, fc2oh(FC_AGEN), RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, M_XRD , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SW -> List(Y, N, FCOH_STORE , RT_X , RT_FIX, RT_FIX, N, IS_S, N, Y, N, M_XWR , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SH -> List(Y, N, FCOH_STORE , RT_X , RT_FIX, RT_FIX, N, IS_S, N, Y, N, M_XWR , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SB -> List(Y, N, FCOH_STORE , RT_X , RT_FIX, RT_FIX, N, IS_S, N, Y, N, M_XWR , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), LUI -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_X , RT_X , N, IS_U, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), ADDI -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), ANDI -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_AND , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), ORI -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_OR , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), XORI -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_XOR , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SLTI -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_SLT , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SLTIU -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_SLTU, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SLL -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_SL , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), ADD -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SUB -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_SUB , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SLT -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_SLT , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SLTU -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_SLTU, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), AND -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_AND , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), OR -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_OR , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), XOR -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_XOR , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SRA -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_SRA , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SRL -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_SR , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), MUL -> List(Y, N, fc2oh(FC_MUL) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_MUL , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), MULH -> List(Y, N, fc2oh(FC_MUL) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_MULH, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), MULHU -> List(Y, N, fc2oh(FC_MUL) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_MULHU, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), MULHSU -> List(Y, N, fc2oh(FC_MUL) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_MULHSU, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), MULW -> List(Y, N, fc2oh(FC_MUL) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_32 , FN_MUL , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), DIV -> List(Y, N, fc2oh(FC_DIV) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_DIV , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), DIVU -> List(Y, N, fc2oh(FC_DIV) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_DIVU, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), REM -> List(Y, N, fc2oh(FC_DIV) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_REM , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), REMU -> List(Y, N, fc2oh(FC_DIV) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_REMU, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), DIVW -> List(Y, N, fc2oh(FC_DIV) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_32 , FN_DIV , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), DIVUW -> List(Y, N, fc2oh(FC_DIV) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_32 , FN_DIVU, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), REMW -> List(Y, N, fc2oh(FC_DIV) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_32 , FN_REM , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), REMUW -> List(Y, N, fc2oh(FC_DIV) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_32 , FN_REMU, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), AUIPC -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_X , RT_X , N, IS_U, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), // use BRU for the PC read JAL -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_X , RT_X , N, IS_J, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), JALR -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), BEQ -> List(Y, N, fc2oh(FC_ALU) , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_SUB , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), BNE -> List(Y, N, fc2oh(FC_ALU) , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_SUB , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), BGE -> List(Y, N, fc2oh(FC_ALU) , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_SLT , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), BGEU -> List(Y, N, fc2oh(FC_ALU) , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_SLTU, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), BLT -> List(Y, N, fc2oh(FC_ALU) , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_SLT , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), BLTU -> List(Y, N, fc2oh(FC_ALU) , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_SLTU, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), // I-type, the immedia2 holds the CSR regi ster. CSRRW -> List(Y, N, fc2oh(FC_CSR) , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , Y, Y, CSR.W, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CSRRS -> List(Y, N, fc2oh(FC_CSR) , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , Y, Y, CSR.S, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CSRRC -> List(Y, N, fc2oh(FC_CSR) , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , Y, Y, CSR.C, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CSRRWI -> List(Y, N, fc2oh(FC_CSR) , RT_FIX, RT_X , RT_X , N, IS_I, N, N, N, M_X , Y, Y, CSR.W, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CSRRSI -> List(Y, N, fc2oh(FC_CSR) , RT_FIX, RT_X , RT_X , N, IS_I, N, N, N, M_X , Y, Y, CSR.S, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CSRRCI -> List(Y, N, fc2oh(FC_CSR) , RT_FIX, RT_X , RT_X , N, IS_I, N, N, N, M_X , Y, Y, CSR.C, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SFENCE_VMA ->List(Y, N, fc2oh(FC_CSR) , RT_X , RT_FIX, RT_FIX, N, IS_N, N, N, N,M_SFENCE , Y, Y, CSR.R, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), ECALL -> List(Y, N, fc2oh(FC_CSR) , RT_X , RT_X , RT_X , N, IS_I, N, N, N, M_X , Y, Y, CSR.I, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), EBREAK -> List(Y, N, fc2oh(FC_CSR) , RT_X , RT_X , RT_X , N, IS_I, N, N, N, M_X , Y, Y, CSR.I, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SRET -> List(Y, N, fc2oh(FC_CSR) , RT_X , RT_X , RT_X , N, IS_I, N, N, N, M_X , Y, Y, CSR.I, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), MRET -> List(Y, N, fc2oh(FC_CSR) , RT_X , RT_X , RT_X , N, IS_I, N, N, N, M_X , Y, Y, CSR.I, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), DRET -> List(Y, N, fc2oh(FC_CSR) , RT_X , RT_X , RT_X , N, IS_I, N, N, N, M_X , Y, Y, CSR.I, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), WFI -> List(Y, N, fc2oh(FC_CSR) , RT_X , RT_X , RT_X , N, IS_I, N, N, N, M_X , Y, Y, CSR.I, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), FENCE_I -> List(Y, N, 0.U(FC_SZ.W) , RT_X , RT_X , RT_X , N, IS_N, N, N, N, M_X , Y, Y, CSR.N, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), FENCE -> List(Y, N, 0.U(FC_SZ.W) , RT_X , RT_X , RT_X , N, IS_N, N, Y, N, M_X , Y, Y, CSR.N, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), // TODO PERF make fence higher performance // currently serializes pipeline // A-type AMOADD_W -> List(Y, N, FCOH_STORE , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, Y, Y, M_XA_ADD, Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), // TODO make AMOs higherperformance AMOXOR_W -> List(Y, N, FCOH_STORE , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, Y, Y, M_XA_XOR, Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), AMOSWAP_W -> List(Y, N, FCOH_STORE , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, Y, Y, M_XA_SWAP,Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), AMOAND_W -> List(Y, N, FCOH_STORE , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, Y, Y, M_XA_AND, Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), AMOOR_W -> List(Y, N, FCOH_STORE , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, Y, Y, M_XA_OR, Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), AMOMIN_W -> List(Y, N, FCOH_STORE , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, Y, Y, M_XA_MIN, Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), AMOMINU_W -> List(Y, N, FCOH_STORE , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, Y, Y, M_XA_MINU,Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), AMOMAX_W -> List(Y, N, FCOH_STORE , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, Y, Y, M_XA_MAX, Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), AMOMAXU_W -> List(Y, N, FCOH_STORE , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, Y, Y, M_XA_MAXU,Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), AMOADD_D -> List(Y, N, FCOH_STORE , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, Y, Y, M_XA_ADD, Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), AMOXOR_D -> List(Y, N, FCOH_STORE , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, Y, Y, M_XA_XOR, Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), AMOSWAP_D -> List(Y, N, FCOH_STORE , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, Y, Y, M_XA_SWAP,Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), AMOAND_D -> List(Y, N, FCOH_STORE , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, Y, Y, M_XA_AND, Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), AMOOR_D -> List(Y, N, FCOH_STORE , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, Y, Y, M_XA_OR, Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), AMOMIN_D -> List(Y, N, FCOH_STORE , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, Y, Y, M_XA_MIN, Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), AMOMINU_D -> List(Y, N, FCOH_STORE , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, Y, Y, M_XA_MINU,Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), AMOMAX_D -> List(Y, N, FCOH_STORE , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, Y, Y, M_XA_MAX, Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), AMOMAXU_D -> List(Y, N, FCOH_STORE , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, Y, Y, M_XA_MAXU,Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), LR_W -> List(Y, N, fc2oh(FC_AGEN), RT_FIX, RT_FIX, RT_X , N, IS_N, Y, N, N, M_XLR , Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), LR_D -> List(Y, N, fc2oh(FC_AGEN), RT_FIX, RT_FIX, RT_X , N, IS_N, Y, N, N, M_XLR , Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SC_W -> List(Y, N, FCOH_STORE , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, Y, Y, M_XSC , Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SC_D -> List(Y, N, FCOH_STORE , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, Y, Y, M_XSC , Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X) ) def F_table: Seq[(BitPat, List[BitPat])] = Seq( FLW -> List(Y, Y, fc2oh(FC_AGEN), RT_FLT, RT_FIX, RT_X , N, IS_I, Y, N, N, M_XRD , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), FLD -> List(Y, Y, fc2oh(FC_AGEN), RT_FLT, RT_FIX, RT_X , N, IS_I, Y, N, N, M_XRD , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), FSW -> List(Y, Y, FCOH_F2IMEM , RT_X , RT_FIX, RT_FLT, N, IS_S, N, Y, N, M_XWR , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), // sort of a lie; broken into two micro-ops FSD -> List(Y, Y, FCOH_F2IMEM , RT_X , RT_FIX, RT_FLT, N, IS_S, N, Y, N, M_XWR , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), FCLASS_S -> List(Y, Y, fc2oh(FC_F2I) , RT_FIX, RT_FLT, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,N,N, N,X,S,S,N,Y,N, N,N,N,N), FCLASS_D -> List(Y, Y, fc2oh(FC_F2I) , RT_FIX, RT_FLT, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,N,N, N,X,D,D,N,Y,N, N,N,N,N), FMV_W_X -> List(Y, Y, fc2oh(FC_I2F) , RT_FLT, RT_FIX, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,N,N,N, X,X,S,D,Y,N,N, N,N,N,N), FMV_D_X -> List(Y, Y, fc2oh(FC_I2F) , RT_FLT, RT_FIX, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,N,N,N, X,X,D,D,Y,N,N, N,N,N,N), FMV_X_W -> List(Y, Y, fc2oh(FC_F2I) , RT_FIX, RT_FLT, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,N,N, N,X,D,S,N,Y,N, N,N,N,N), FMV_X_D -> List(Y, Y, fc2oh(FC_F2I) , RT_FIX, RT_FLT, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,N,N, N,X,D,D,N,Y,N, N,N,N,N), FSGNJ_S -> List(Y, Y, fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,Y,N, N,N,S,S,N,N,Y, N,N,N,N), FSGNJ_D -> List(Y, Y, fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,Y,N, N,N,D,D,N,N,Y, N,N,N,N), FSGNJX_S -> List(Y, Y, fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,Y,N, N,N,S,S,N,N,Y, N,N,N,N), FSGNJX_D -> List(Y, Y, fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,Y,N, N,N,D,D,N,N,Y, N,N,N,N), FSGNJN_S -> List(Y, Y, fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,Y,N, N,N,S,S,N,N,Y, N,N,N,N), FSGNJN_D -> List(Y, Y, fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,Y,N, N,N,D,D,N,N,Y, N,N,N,N), // FP to FP FCVT_S_D -> List(Y, Y,fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,N,N, N,X,D,S,N,N,Y, N,N,N,Y), FCVT_D_S -> List(Y, Y,fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,N,N, N,X,S,D,N,N,Y, N,N,N,Y), // Int to FP FCVT_S_W -> List(Y, Y,fc2oh(FC_I2F) , RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,N,N,N, X,X,S,S,Y,N,N, N,N,N,Y), FCVT_S_WU -> List(Y, Y,fc2oh(FC_I2F) , RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,N,N,N, X,X,S,S,Y,N,N, N,N,N,Y), FCVT_S_L -> List(Y, Y,fc2oh(FC_I2F) , RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,N,N,N, X,X,S,S,Y,N,N, N,N,N,Y), FCVT_S_LU -> List(Y, Y,fc2oh(FC_I2F) , RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,N,N,N, X,X,S,S,Y,N,N, N,N,N,Y), FCVT_D_W -> List(Y, Y,fc2oh(FC_I2F) , RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,N,N,N, X,X,D,D,Y,N,N, N,N,N,Y), FCVT_D_WU -> List(Y, Y,fc2oh(FC_I2F) , RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,N,N,N, X,X,D,D,Y,N,N, N,N,N,Y), FCVT_D_L -> List(Y, Y,fc2oh(FC_I2F) , RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,N,N,N, X,X,D,D,Y,N,N, N,N,N,Y), FCVT_D_LU -> List(Y, Y,fc2oh(FC_I2F) , RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,N,N,N, X,X,D,D,Y,N,N, N,N,N,Y), // FP to Int FCVT_W_S -> List(Y, Y,fc2oh(FC_F2I) , RT_FIX, RT_FLT, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,N,N, N,X,S,S,N,Y,N, N,N,N,Y), FCVT_WU_S -> List(Y, Y,fc2oh(FC_F2I) , RT_FIX, RT_FLT, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,N,N, N,X,S,S,N,Y,N, N,N,N,Y), FCVT_L_S -> List(Y, Y,fc2oh(FC_F2I) , RT_FIX, RT_FLT, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,N,N, N,X,S,S,N,Y,N, N,N,N,Y), FCVT_LU_S -> List(Y, Y,fc2oh(FC_F2I) , RT_FIX, RT_FLT, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,N,N, N,X,S,S,N,Y,N, N,N,N,Y), FCVT_W_D -> List(Y, Y,fc2oh(FC_F2I) , RT_FIX, RT_FLT, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,N,N, N,X,D,D,N,Y,N, N,N,N,Y), FCVT_WU_D -> List(Y, Y,fc2oh(FC_F2I) , RT_FIX, RT_FLT, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,N,N, N,X,D,D,N,Y,N, N,N,N,Y), FCVT_L_D -> List(Y, Y,fc2oh(FC_F2I) , RT_FIX, RT_FLT, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,N,N, N,X,D,D,N,Y,N, N,N,N,Y), FCVT_LU_D -> List(Y, Y,fc2oh(FC_F2I) , RT_FIX, RT_FLT, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,N,N, N,X,D,D,N,Y,N, N,N,N,Y), FEQ_S -> List(Y, Y, fc2oh(FC_F2I) , RT_FIX, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,Y,N, N,N,S,S,N,Y,N, N,N,N,Y), FLT_S -> List(Y, Y, fc2oh(FC_F2I) , RT_FIX, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,Y,N, N,N,S,S,N,Y,N, N,N,N,Y), FLE_S -> List(Y, Y, fc2oh(FC_F2I) , RT_FIX, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,Y,N, N,N,S,S,N,Y,N, N,N,N,Y), FEQ_D -> List(Y, Y, fc2oh(FC_F2I) , RT_FIX, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,Y,N, N,N,D,D,N,Y,N, N,N,N,Y), FLT_D -> List(Y, Y, fc2oh(FC_F2I) , RT_FIX, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,Y,N, N,N,D,D,N,Y,N, N,N,N,Y), FLE_D -> List(Y, Y, fc2oh(FC_F2I) , RT_FIX, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,Y,N, N,N,D,D,N,Y,N, N,N,N,Y), FMIN_S -> List(Y, Y,fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,Y,N, N,N,S,S,N,N,Y, N,N,N,Y), FMAX_S -> List(Y, Y,fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,Y,N, N,N,S,S,N,N,Y, N,N,N,Y), FMIN_D -> List(Y, Y,fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,Y,N, N,N,D,D,N,N,Y, N,N,N,Y), FMAX_D -> List(Y, Y,fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,Y,N, N,N,D,D,N,N,Y, N,N,N,Y), FADD_S -> List(Y, Y,fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_00 ,X,X,Y,Y,N, N,Y,S,S,N,N,N, Y,N,N,Y), FSUB_S -> List(Y, Y,fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_01 ,X,X,Y,Y,N, N,Y,S,S,N,N,N, Y,N,N,Y), FMUL_S -> List(Y, Y,fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_00 ,X,X,Y,Y,N, N,N,S,S,N,N,N, Y,N,N,Y), FADD_D -> List(Y, Y,fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_00 ,X,X,Y,Y,N, N,Y,D,D,N,N,N, Y,N,N,Y), FSUB_D -> List(Y, Y,fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_01 ,X,X,Y,Y,N, N,Y,D,D,N,N,N, Y,N,N,Y), FMUL_D -> List(Y, Y,fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_00 ,X,X,Y,Y,N, N,N,D,D,N,N,N, Y,N,N,Y), FMADD_S -> List(Y, Y,fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, Y, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_00 ,X,X,Y,Y,Y, N,N,S,S,N,N,N, Y,N,N,Y), FMSUB_S -> List(Y, Y,fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, Y, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_01 ,X,X,Y,Y,Y, N,N,S,S,N,N,N, Y,N,N,Y), FNMADD_S -> List(Y, Y,fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, Y, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_11 ,X,X,Y,Y,Y, N,N,S,S,N,N,N, Y,N,N,Y), FNMSUB_S -> List(Y, Y,fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, Y, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_10 ,X,X,Y,Y,Y, N,N,S,S,N,N,N, Y,N,N,Y), FMADD_D -> List(Y, Y,fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, Y, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_00 ,X,X,Y,Y,Y, N,N,D,D,N,N,N, Y,N,N,Y), FMSUB_D -> List(Y, Y,fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, Y, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_01 ,X,X,Y,Y,Y, N,N,D,D,N,N,N, Y,N,N,Y), FNMADD_D -> List(Y, Y,fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, Y, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_11 ,X,X,Y,Y,Y, N,N,D,D,N,N,N, Y,N,N,Y), FNMSUB_D -> List(Y, Y,fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, Y, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_10 ,X,X,Y,Y,Y, N,N,D,D,N,N,N, Y,N,N,Y) ) def FDivSqrt_table: Seq[(BitPat, List[BitPat])] = Seq( FDIV_S -> List(Y, Y, fc2oh(FC_FDV) , RT_FLT, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,Y,X, X,X,S,S,X,X,X, X,Y,N,Y), FDIV_D -> List(Y, Y, fc2oh(FC_FDV) , RT_FLT, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,Y,X, X,X,D,D,X,X,X, X,Y,N,Y), FSQRT_S -> List(Y, Y, fc2oh(FC_FDV) , RT_FLT, RT_FLT, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,N,X, X,X,S,S,X,X,X, X,N,Y,Y), FSQRT_D -> List(Y, Y, fc2oh(FC_FDV) , RT_FLT, RT_FLT, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,N,X, X,X,D,D,X,X,X, X,N,Y,Y), ) def B_table: Seq[(BitPat, List[BitPat])] = Seq( SH1ADD -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_F3,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SH2ADD -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_F3,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SH3ADD -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_F3,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SH1ADD_UW -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_F3,N, N, N, M_X , N, N, CSR.N, DW_32 , FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SH2ADD_UW -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_F3,N, N, N, M_X , N, N, CSR.N, DW_32 , FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SH3ADD_UW -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_F3,N, N, N, M_X , N, N, CSR.N, DW_32 , FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), ADD_UW -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_F3,N, N, N, M_X , N, N, CSR.N, DW_32 , FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SLLI_UW -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_I ,N, N, N, M_X , N, N, CSR.N, DW_32 , FN_SL , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), ANDN -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N ,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_ANDN, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), ORN -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N ,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_ORN , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), XNOR -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N ,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_XNOR, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), MAX -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N ,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_MAX , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), MAXU -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N ,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_MAXU, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), MIN -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N ,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_MIN , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), MINU -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N ,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_MINU, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), ROL -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N ,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_ROL , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), ROR -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N ,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_ROR , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), RORI -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I ,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_ROR , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CLZ -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I ,N, N, N, M_X , N, N, CSR.N, DW_XPR,FN_UNARY, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CTZ -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I ,N, N, N, M_X , N, N, CSR.N, DW_XPR,FN_UNARY, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CPOP -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I ,N, N, N, M_X , N, N, CSR.N, DW_XPR,FN_UNARY, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), ORC_B -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I ,N, N, N, M_X , N, N, CSR.N, DW_XPR,FN_UNARY, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SEXT_B -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I ,N, N, N, M_X , N, N, CSR.N, DW_XPR,FN_UNARY, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SEXT_H -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I ,N, N, N, M_X , N, N, CSR.N, DW_XPR,FN_UNARY, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), ZEXT_H -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I ,N, N, N, M_X , N, N, CSR.N, DW_XPR,FN_UNARY, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), REV8 -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I ,N, N, N, M_X , N, N, CSR.N, DW_XPR,FN_UNARY, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), ROLW -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N ,N, N, N, M_X , N, N, CSR.N, DW_32 , FN_ROL , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), RORW -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N ,N, N, N, M_X , N, N, CSR.N, DW_32 , FN_ROR , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), RORIW -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I ,N, N, N, M_X , N, N, CSR.N, DW_32 , FN_ROR , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CLZW -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I ,N, N, N, M_X , N, N, CSR.N, DW_32 ,FN_UNARY, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CTZW -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I ,N, N, N, M_X , N, N, CSR.N, DW_32 ,FN_UNARY, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CPOPW -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I ,N, N, N, M_X , N, N, CSR.N, DW_32 ,FN_UNARY, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), BCLR -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N ,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_ANDN, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), BCLRI -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I ,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_ANDN, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), BINV -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N ,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_XOR , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), BINVI -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I ,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_XOR , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), BSET -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N ,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_OR , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), BSETI -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I ,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_OR , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), BEXT -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N ,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_BEXT, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), BEXTI -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I ,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_BEXT, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), ) def RoCC_table: Seq[(BitPat, List[BitPat])] = Seq( // Note: We use fc2oh(FC_CSR) since CSR instructions cannot co-execute with RoCC instructions CUSTOM0 -> List(Y, N, fc2oh(FC_CSR) , RT_X , RT_X , RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM0_RS1 -> List(Y, N, fc2oh(FC_CSR) , RT_X , RT_FIX, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM0_RS1_RS2 -> List(Y, N, fc2oh(FC_CSR) , RT_X , RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM0_RD -> List(Y, N, fc2oh(FC_CSR) , RT_FIX, RT_X , RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM0_RD_RS1 -> List(Y, N, fc2oh(FC_CSR) , RT_FIX, RT_FIX, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM0_RD_RS1_RS2 -> List(Y, N, fc2oh(FC_CSR) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM1 -> List(Y, N, fc2oh(FC_CSR) , RT_X , RT_X , RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM1_RS1 -> List(Y, N, fc2oh(FC_CSR) , RT_X , RT_FIX, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM1_RS1_RS2 -> List(Y, N, fc2oh(FC_CSR) , RT_X , RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM1_RD -> List(Y, N, fc2oh(FC_CSR) , RT_FIX, RT_X , RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM1_RD_RS1 -> List(Y, N, fc2oh(FC_CSR) , RT_FIX, RT_FIX, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM1_RD_RS1_RS2 -> List(Y, N, fc2oh(FC_CSR) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM2 -> List(Y, N, fc2oh(FC_CSR) , RT_X , RT_X , RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM2_RS1 -> List(Y, N, fc2oh(FC_CSR) , RT_X , RT_FIX, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM2_RS1_RS2 -> List(Y, N, fc2oh(FC_CSR) , RT_X , RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM2_RD -> List(Y, N, fc2oh(FC_CSR) , RT_FIX, RT_X , RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM2_RD_RS1 -> List(Y, N, fc2oh(FC_CSR) , RT_FIX, RT_FIX, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM2_RD_RS1_RS2 -> List(Y, N, fc2oh(FC_CSR) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM3 -> List(Y, N, fc2oh(FC_CSR) , RT_X , RT_X , RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM3_RS1 -> List(Y, N, fc2oh(FC_CSR) , RT_X , RT_FIX, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM3_RS1_RS2 -> List(Y, N, fc2oh(FC_CSR) , RT_X , RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM3_RD -> List(Y, N, fc2oh(FC_CSR) , RT_FIX, RT_X , RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM3_RD_RS1 -> List(Y, N, fc2oh(FC_CSR) , RT_FIX, RT_FIX, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM3_RD_RS1_RS2 -> List(Y, N, fc2oh(FC_CSR) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X) ) } // scalastyle:on /* * Decoded control signals / class CtrlSigs(implicit p: Parameters) extends Bundle { val legal = Bool() val fp_val = Bool() val fu_code = UInt(FC_SZ.W) val dst_type = UInt(2.W) val rs1_type = UInt(2.W) val rs2_type = UInt(2.W) val frs3_en = Bool() val imm_sel = UInt(IS_N.getWidth.W) val uses_ldq = Bool() val uses_stq = Bool() val is_amo = Bool() val mem_cmd = UInt(freechips.rocketchip.rocket.M_SZ.W) val inst_unique = Bool() val flush_on_commit = Bool() val csr_cmd = UInt(freechips.rocketchip.rocket.CSR.SZ.W) val fcn_dw = Bool() val fcn_op = UInt(SZ_ALU_FN.W) val fp = new freechips.rocketchip.tile.FPUCtrlSigs() def decode(inst: UInt, table: Iterable[(BitPat, List[BitPat])]) = { val decoder = freechips.rocketchip.rocket.DecodeLogic(inst, DecodeTables.decode_default, table) val sigs = Seq( legal, fp_val, fu_code, dst_type, rs1_type, rs2_type, frs3_en, imm_sel, uses_ldq, uses_stq, is_amo, mem_cmd, inst_unique, flush_on_commit, csr_cmd, fcn_dw, fcn_op, fp.ldst, fp.wen, fp.ren1, fp.ren2, fp.ren3, fp.swap12, fp.swap23, fp.typeTagIn, fp.typeTagOut, fp.fromint, fp.toint, fp.fastpipe, fp.fma, fp.div, fp.sqrt, fp.wflags ) sigs zip decoder map {case(s,d) => s := d} fp.vec := false.B this } } /* * IO bundle for the Decode unit / class DecodeUnitIo(implicit p: Parameters) extends BoomBundle { val enq = new Bundle { val uop = Input(new MicroOp()) } val deq = new Bundle { val uop = Output(new MicroOp()) } // from CSRFile val status = Input(new freechips.rocketchip.rocket.MStatus()) val csr_decode = Flipped(new freechips.rocketchip.rocket.CSRDecodeIO) val fcsr_rm = Input(UInt(FPConstants.RM_SZ.W)) val interrupt = Input(Bool()) val interrupt_cause = Input(UInt(xLen.W)) } /* * Decode unit that takes in a single instruction and generates a MicroOp. / class DecodeUnit(implicit p: Parameters) extends BoomModule with freechips.rocketchip.rocket.constants.MemoryOpConstants with freechips.rocketchip.rocket.constants.ScalarOpConstants { val io = IO(new DecodeUnitIo) val uop = Wire(new MicroOp()) uop := io.enq.uop val decode_table = ( DecodeTables.X_table ++ DecodeTables.F_table ++ DecodeTables.FDivSqrt_table ++ DecodeTables.X64_table ++ DecodeTables.B_table ++ (if (usingRoCC) DecodeTables.RoCC_table else Nil) ) val inst = uop.inst val LDST = inst(RD_MSB,RD_LSB) val LRS1 = inst(RS1_MSB,RS1_LSB) val LRS2 = inst(RS2_MSB,RS2_LSB) val LRS3 = inst(RS3_MSB,RS3_LSB) val cs = Wire(new CtrlSigs()).decode(inst, decode_table) // Exception Handling io.csr_decode.inst := inst val csr_en = cs.csr_cmd.isOneOf(CSR.S, CSR.C, CSR.W) val csr_ren = cs.csr_cmd.isOneOf(CSR.S, CSR.C) && uop.lrs1 === 0.U val system_insn = cs.csr_cmd === CSR.I val sfence = inst === SFENCE_VMA val cs_legal = cs.legal // dontTouch(cs_legal) require (fLen >= 64) val illegal_rm = inst(14,12).isOneOf(5.U,6.U) \|\| (inst(14,12) === 7.U && io.fcsr_rm >= 5.U) val id_illegal_insn = (!cs_legal \|\| (cs.fp_val && (io.csr_decode.fp_illegal \|\| illegal_rm)) \|\| (uop.is_rocc && io.csr_decode.rocc_illegal) \|\| (cs.is_amo && !io.status.isa('a'-'a')) \|\| (csr_en && (io.csr_decode.read_illegal \|\| !csr_ren && io.csr_decode.write_illegal)) \|\| ((sfence \|\| system_insn) && io.csr_decode.system_illegal)) // cs.div && !csr.io.status.isa('m'-'a') \|\| TODO check for illegal div instructions def checkExceptions(x: Seq[(Bool, UInt)]) = (x.map(_._1).reduce(_\|\|_), PriorityMux(x)) val (xcpt_valid, xcpt_cause) = checkExceptions(List( (io.interrupt && !io.enq.uop.is_sfb, io.interrupt_cause), // Disallow interrupts while we are handling a SFB (uop.bp_debug_if, (CSR.debugTriggerCause).U), (uop.bp_xcpt_if, (Causes.breakpoint).U), (uop.xcpt_pf_if, (Causes.fetch_page_fault).U), (uop.xcpt_ae_if, (Causes.fetch_access).U), (id_illegal_insn, (Causes.illegal_instruction).U))) uop.exception := xcpt_valid uop.exc_cause := xcpt_cause //------------------------------------------------------------- uop.is_mov := inst === ADD && LRS1 === 0.U uop.iq_type(IQ_UNQ) := Seq(FC_MUL , FC_DIV, FC_CSR, FC_I2F).map { c => cs.fu_code(c) }.reduce(_\|\|_) uop.iq_type(IQ_ALU) := Seq(FC_ALU ).map { c => cs.fu_code(c) }.reduce(_\|\|_) uop.iq_type(IQ_MEM) := Seq(FC_AGEN, FC_DGEN ).map { c => cs.fu_code(c) }.reduce(_\|\|_) uop.iq_type(IQ_FP ) := Seq(FC_FPU , FC_FDV, FC_F2I ).map { c => cs.fu_code(c) }.reduce(_\|\|_) uop.fu_code := cs.fu_code.asBools uop.ldst := LDST uop.lrs1 := LRS1 uop.lrs2 := LRS2 uop.lrs3 := LRS3 uop.dst_rtype := cs.dst_type uop.lrs1_rtype := Mux(cs.rs1_type === RT_FIX && LRS1 === 0.U, RT_ZERO, cs.rs1_type) uop.lrs2_rtype := Mux(cs.rs2_type === RT_FIX && LRS2 === 0.U, RT_ZERO, cs.rs2_type) uop.frs3_en := cs.frs3_en uop.ldst_is_rs1 := uop.is_sfb_shadow // SFB optimization when (uop.is_sfb_shadow && cs.rs2_type === RT_X) { uop.lrs2_rtype := Mux(LDST === 0.U, RT_ZERO, RT_FIX) uop.lrs2 := LDST uop.ldst_is_rs1 := false.B } .elsewhen (uop.is_sfb_shadow && uop.is_mov) { uop.lrs1 := LDST uop.lrs1_rtype := Mux(LDST === 0.U, RT_ZERO, RT_FIX) uop.ldst_is_rs1 := true.B } uop.fp_val := cs.fp_val uop.fp_ctrl := cs.fp uop.mem_cmd := cs.mem_cmd uop.mem_size := Mux(cs.mem_cmd.isOneOf(M_SFENCE, M_FLUSH_ALL), Cat(LRS2 =/= 0.U, LRS1 =/= 0.U), inst(13,12)) uop.mem_signed := !inst(14) uop.uses_ldq := cs.uses_ldq uop.uses_stq := cs.uses_stq uop.is_amo := cs.is_amo uop.is_fence := inst === FENCE uop.is_fencei := inst === FENCE_I uop.is_sfence := inst === SFENCE_VMA uop.is_sys_pc2epc := inst === EBREAK \|\| inst === ECALL uop.is_eret := inst === ECALL \|\| inst === EBREAK \|\| inst === SRET \|\| inst === MRET \|\| inst === DRET uop.is_unique := cs.inst_unique uop.is_rocc := inst(6,0).isOneOf("b0001011".U, "b0101011".U, "b1111011".U) && inst(14,12).isOneOf(0.U, 2.U, 3.U, 4.U, 6.U, 7.U) uop.flush_on_commit := cs.flush_on_commit \|\| (csr_en && !csr_ren && io.csr_decode.write_flush) //------------------------------------------------------------- // immediates // repackage the immediate, and then pass the fewest number of bits around val di24_20 = Mux(cs.imm_sel === IS_B \|\| cs.imm_sel === IS_S, inst(11,7), inst(24,20)) val imm_packed = Cat(inst(31,25), di24_20, inst(19,12)) val imm = ImmGen(imm_packed, cs.imm_sel) val imm_hi = imm >> (immPregSz-1) val imm_lo = imm(immPregSz-1, 0) val short_imm = imm_hi === 0.U \|\| ~imm_hi === 0.U \|\| cs.imm_sel === IS_F3 uop.imm_rename := cs.imm_sel =/= IS_N && cs.imm_sel =/= IS_F3 uop.imm_packed := imm_packed uop.imm_sel := cs.imm_sel when (short_imm) { uop.imm_rename := false.B uop.imm_sel := IS_SH uop.pimm := Mux(cs.imm_sel === IS_F3, inst(14,12), imm_lo) } uop.fp_rm := Mux(inst(14,12) === 7.U, io.fcsr_rm, inst(14,12)) uop.fp_typ := inst(21,20) //------------------------------------------------------------- uop.csr_cmd := cs.csr_cmd when ((cs.csr_cmd === CSR.S \|\| cs.csr_cmd === CSR.C) && LRS1 === 0.U) { uop.csr_cmd := CSR.R } uop.fcn_dw := cs.fcn_dw uop.fcn_op := cs.fcn_op uop.op1_sel := OP1_RS1 when (inst === LUI \|\| inst === CSRRWI \|\| inst === CSRRSI \|\| inst === CSRRCI \|\| inst === WFI \|\| inst === SRET \|\| inst === MRET \|\| inst === DRET) { uop.op1_sel := OP1_ZERO } .elsewhen (inst === JAL \|\| inst === JALR \|\| inst === AUIPC) { uop.op1_sel := OP1_PC } .elsewhen (Seq(SH1ADD, SH2ADD, SH3ADD, SH1ADD_UW, SH2ADD_UW, SH3ADD_UW, ADD_UW, SLLI_UW).map(_ === inst).orR) { uop.op1_sel := OP1_RS1SHL } uop.op2_sel := OP2_RS2 when (cs.is_amo \|\| inst === CSRRW \|\| inst === CSRRS \|\| inst === CSRRC) { uop.op2_sel := OP2_ZERO } .elsewhen (inst === CSRRWI \|\| inst === CSRRSI \|\| inst === CSRRCI \|\| inst === WFI \|\| inst === SRET \|\| inst === DRET \|\| inst === MRET) { uop.op2_sel := OP2_IMMC } .elsewhen (inst === JAL \|\| inst === JALR) { uop.op2_sel := OP2_NEXT } .elsewhen (Seq(BCLR, BCLRI, BINV, BINVI, BSET, BSETI).map(_ === inst).orR) { uop.op2_sel := Mux(uop.lrs2_rtype === RT_FIX, OP2_RS2OH, OP2_IMMOH) } .elsewhen (cs.imm_sel === IS_U \|\| cs.imm_sel === IS_I \|\| cs.imm_sel === IS_S) { uop.op2_sel := OP2_IMM } uop.br_type := Seq( (BEQ , B_EQ ), (BNE , B_NE ), (BGE , B_GE ), (BGEU , B_GEU), (BLT , B_LT ), (BLTU , B_LTU), (JAL , B_J ), (JALR , B_JR ) ) .map { case (c, b) => Mux(inst === c, b, 0.U) } .reduce(_\|_) io.deq.uop := uop } /* * Smaller Decode unit for the Frontend to decode different * branches. * Accepts EXPANDED RVC instructions / class BranchDecodeSignals(implicit p: Parameters) extends BoomBundle { val is_ret = Bool() val is_call = Bool() val target = UInt(vaddrBitsExtended.W) val cfi_type = UInt(CFI_SZ.W) // Is this branch a short forwards jump? val sfb_offset = Valid(UInt(log2Ceil(icBlockBytes).W)) // Is this instruction allowed to be inside a sfb? val shadowable = Bool() } class BranchDecode(implicit p: Parameters) extends BoomModule { val io = IO(new Bundle { val inst = Input(UInt(32.W)) val pc = Input(UInt(vaddrBitsExtended.W)) val out = Output(new BranchDecodeSignals) }) val bpd_csignals = freechips.rocketchip.rocket.DecodeLogic(io.inst, List[BitPat](N, N, N, N, X), //// is br? //// \| is jal? //// \| \| is jalr? //// \| \| \| //// \| \| \| shadowable //// \| \| \| \| has_rs2 //// \| \| \| \| \| Seq[(BitPat, List[BitPat])]( JAL -> List(N, Y, N, N, X), JALR -> List(N, N, Y, N, X), BEQ -> List(Y, N, N, N, X), BNE -> List(Y, N, N, N, X), BGE -> List(Y, N, N, N, X), BGEU -> List(Y, N, N, N, X), BLT -> List(Y, N, N, N, X), BLTU -> List(Y, N, N, N, X), SLLI -> List(N, N, N, Y, N), SRLI -> List(N, N, N, Y, N), SRAI -> List(N, N, N, Y, N), ADDIW -> List(N, N, N, Y, N), SLLIW -> List(N, N, N, Y, N), SRAIW -> List(N, N, N, Y, N), SRLIW -> List(N, N, N, Y, N), ADDW -> List(N, N, N, Y, Y), SUBW -> List(N, N, N, Y, Y), SLLW -> List(N, N, N, Y, Y), SRAW -> List(N, N, N, Y, Y), SRLW -> List(N, N, N, Y, Y), LUI -> List(N, N, N, Y, N), ADDI -> List(N, N, N, Y, N), ANDI -> List(N, N, N, Y, N), ORI -> List(N, N, N, Y, N), XORI -> List(N, N, N, Y, N), SLTI -> List(N, N, N, Y, N), SLTIU -> List(N, N, N, Y, N), SLL -> List(N, N, N, Y, Y), ADD -> List(N, N, N, Y, Y), SUB -> List(N, N, N, Y, Y), SLT -> List(N, N, N, Y, Y), SLTU -> List(N, N, N, Y, Y), AND -> List(N, N, N, Y, Y), OR -> List(N, N, N, Y, Y), XOR -> List(N, N, N, Y, Y), SRA -> List(N, N, N, Y, Y), SRL -> List(N, N, N, Y, Y) )) val cs_is_br = bpd_csignals(0)(0) val cs_is_jal = bpd_csignals(1)(0) val cs_is_jalr = bpd_csignals(2)(0) val cs_is_shadowable = bpd_csignals(3)(0) val cs_has_rs2 = bpd_csignals(4)(0) io.out.is_call := (cs_is_jal \|\| cs_is_jalr) && GetRd(io.inst) === RA io.out.is_ret := cs_is_jalr && GetRs1(io.inst) === BitPat("b00?01") && GetRd(io.inst) === X0 io.out.target := Mux(cs_is_br, ComputeBranchTarget(io.pc, io.inst, xLen), ComputeJALTarget(io.pc, io.inst, xLen)) io.out.cfi_type := Mux(cs_is_jalr, CFI_JALR, Mux(cs_is_jal, CFI_JAL, Mux(cs_is_br, CFI_BR, CFI_X))) val br_offset = Cat(io.inst(7), io.inst(30,25), io.inst(11,8), 0.U(1.W)) // Is a sfb if it points forwards (offset is positive) io.out.sfb_offset.valid := cs_is_br && !io.inst(31) && br_offset =/= 0.U && (br_offset >> log2Ceil(icBlockBytes)) === 0.U io.out.sfb_offset.bits := br_offset io.out.shadowable := cs_is_shadowable && ( !cs_has_rs2 \|\| (GetRs1(io.inst) === GetRd(io.inst)) \|\| (io.inst === ADD && GetRs1(io.inst) === X0) ) } /* * Track the current "branch mask", and give out the branch mask to each micro-op in Decode * (each micro-op in the machine has a branch mask which says which branches it * is being speculated under). * * @param pl_width pipeline width for the processor */ class BranchMaskGenerationLogic(val pl_width: Int)(implicit p: Parameters) extends BoomModule { val io = IO(new Bundle { // guess if the uop is a branch (we'll catch this later) val is_branch = Input(Vec(pl_width, Bool())) // lock in that it's actually a branch and will fire, so we update // the branch_masks. val will_fire = Input(Vec(pl_width, Bool())) // give out tag immediately (needed in rename) // mask can come later in the cycle val br_tag = Output(Vec(pl_width, UInt(brTagSz.W))) val br_mask = Output(Vec(pl_width, UInt(maxBrCount.W))) // tell decoders the branch mask has filled up, but on the granularity // of an individual micro-op (so some micro-ops can go through) val is_full = Output(Vec(pl_width, Bool())) val brupdate = Input(new BrUpdateInfo()) val flush_pipeline = Input(Bool()) val debug_branch_mask = Output(UInt(maxBrCount.W)) }) val branch_mask = RegInit(0.U(maxBrCount.W)) //------------------------------------------------------------- // Give out the branch tag to each branch micro-op var allocate_mask = branch_mask val tag_masks = Wire(Vec(pl_width, UInt(maxBrCount.W))) for (w <- 0 until pl_width) { // TODO this is a loss of performance as we're blocking branches based on potentially fake branches io.is_full(w) := (allocate_mask === ~(0.U(maxBrCount.W))) && io.is_branch(w) // find br_tag and compute next br_mask val new_br_tag = Wire(UInt(brTagSz.W)) new_br_tag := 0.U tag_masks(w) := 0.U for (i <- maxBrCount-1 to 0 by -1) { when (~allocate_mask(i)) { new_br_tag := i.U tag_masks(w) := (1.U << i.U) } } io.br_tag(w) := new_br_tag allocate_mask = Mux(io.is_branch(w), tag_masks(w) \| allocate_mask, allocate_mask) } //------------------------------------------------------------- // Give out the branch mask to each micro-op // (kill off the bits that corresponded to branches that aren't going to fire) var curr_mask = branch_mask for (w <- 0 until pl_width) { io.br_mask(w) := GetNewBrMask(io.brupdate, curr_mask) curr_mask = Mux(io.will_fire(w), tag_masks(w) \| curr_mask, curr_mask) } //------------------------------------------------------------- // Update the current branch_mask when (io.flush_pipeline) { branch_mask := 0.U } .otherwise { val mask = Mux(io.brupdate.b2.mispredict, io.brupdate.b2.uop.br_mask, ~(0.U(maxBrCount.W))) branch_mask := GetNewBrMask(io.brupdate, curr_mask) & mask } io.debug_branch_mask := branch_mask }	module DecodeUnit_1( // @[decode.scala:422:7] input clock, // @[decode.scala:422:7] input reset, // @[decode.scala:422:7] input [31:0] io_enq_uop_inst, // @[decode.scala:426:14] input [31:0] io_enq_uop_debug_inst, // @[decode.scala:426:14] input io_enq_uop_is_rvc, // @[decode.scala:426:14] input [39:0] io_enq_uop_debug_pc, // @[decode.scala:426:14] input io_enq_uop_is_sfb, // @[decode.scala:426:14] input [4:0] io_enq_uop_ftq_idx, // @[decode.scala:426:14] input io_enq_uop_edge_inst, // @[decode.scala:426:14] input [5:0] io_enq_uop_pc_lob, // @[decode.scala:426:14] input io_enq_uop_taken, // @[decode.scala:426:14] input io_enq_uop_xcpt_pf_if, // @[decode.scala:426:14] input io_enq_uop_xcpt_ae_if, // @[decode.scala:426:14] input io_enq_uop_bp_debug_if, // @[decode.scala:426:14] input io_enq_uop_bp_xcpt_if, // @[decode.scala:426:14] input [2:0] io_enq_uop_debug_fsrc, // @[decode.scala:426:14] output [31:0] io_deq_uop_inst, // @[decode.scala:426:14] output [31:0] io_deq_uop_debug_inst, // @[decode.scala:426:14] output io_deq_uop_is_rvc, // @[decode.scala:426:14] output [39:0] io_deq_uop_debug_pc, // @[decode.scala:426:14] output io_deq_uop_iq_type_0, // @[decode.scala:426:14] output io_deq_uop_iq_type_1, // @[decode.scala:426:14] output io_deq_uop_iq_type_2, // @[decode.scala:426:14] output io_deq_uop_iq_type_3, // @[decode.scala:426:14] output io_deq_uop_fu_code_0, // @[decode.scala:426:14] output io_deq_uop_fu_code_1, // @[decode.scala:426:14] output io_deq_uop_fu_code_2, // @[decode.scala:426:14] output io_deq_uop_fu_code_3, // @[decode.scala:426:14] output io_deq_uop_fu_code_4, // @[decode.scala:426:14] output io_deq_uop_fu_code_5, // @[decode.scala:426:14] output io_deq_uop_fu_code_6, // @[decode.scala:426:14] output io_deq_uop_fu_code_7, // @[decode.scala:426:14] output io_deq_uop_fu_code_8, // @[decode.scala:426:14] output io_deq_uop_fu_code_9, // @[decode.scala:426:14] output [3:0] io_deq_uop_br_type, // @[decode.scala:426:14] output io_deq_uop_is_sfb, // @[decode.scala:426:14] output io_deq_uop_is_fence, // @[decode.scala:426:14] output io_deq_uop_is_fencei, // @[decode.scala:426:14] output io_deq_uop_is_sfence, // @[decode.scala:426:14] output io_deq_uop_is_amo, // @[decode.scala:426:14] output io_deq_uop_is_eret, // @[decode.scala:426:14] output io_deq_uop_is_sys_pc2epc, // @[decode.scala:426:14] output io_deq_uop_is_rocc, // @[decode.scala:426:14] output io_deq_uop_is_mov, // @[decode.scala:426:14] output [4:0] io_deq_uop_ftq_idx, // @[decode.scala:426:14] output io_deq_uop_edge_inst, // @[decode.scala:426:14] output [5:0] io_deq_uop_pc_lob, // @[decode.scala:426:14] output io_deq_uop_taken, // @[decode.scala:426:14] output io_deq_uop_imm_rename, // @[decode.scala:426:14] output [2:0] io_deq_uop_imm_sel, // @[decode.scala:426:14] output [4:0] io_deq_uop_pimm, // @[decode.scala:426:14] output [19:0] io_deq_uop_imm_packed, // @[decode.scala:426:14] output [1:0] io_deq_uop_op1_sel, // @[decode.scala:426:14] output [2:0] io_deq_uop_op2_sel, // @[decode.scala:426:14] output io_deq_uop_fp_ctrl_ldst, // @[decode.scala:426:14] output io_deq_uop_fp_ctrl_wen, // @[decode.scala:426:14] output io_deq_uop_fp_ctrl_ren1, // @[decode.scala:426:14] output io_deq_uop_fp_ctrl_ren2, // @[decode.scala:426:14] output io_deq_uop_fp_ctrl_ren3, // @[decode.scala:426:14] output io_deq_uop_fp_ctrl_swap12, // @[decode.scala:426:14] output io_deq_uop_fp_ctrl_swap23, // @[decode.scala:426:14] output [1:0] io_deq_uop_fp_ctrl_typeTagIn, // @[decode.scala:426:14] output [1:0] io_deq_uop_fp_ctrl_typeTagOut, // @[decode.scala:426:14] output io_deq_uop_fp_ctrl_fromint, // @[decode.scala:426:14] output io_deq_uop_fp_ctrl_toint, // @[decode.scala:426:14] output io_deq_uop_fp_ctrl_fastpipe, // @[decode.scala:426:14] output io_deq_uop_fp_ctrl_fma, // @[decode.scala:426:14] output io_deq_uop_fp_ctrl_div, // @[decode.scala:426:14] output io_deq_uop_fp_ctrl_sqrt, // @[decode.scala:426:14] output io_deq_uop_fp_ctrl_wflags, // @[decode.scala:426:14] output io_deq_uop_exception, // @[decode.scala:426:14] output [63:0] io_deq_uop_exc_cause, // @[decode.scala:426:14] output [4:0] io_deq_uop_mem_cmd, // @[decode.scala:426:14] output [1:0] io_deq_uop_mem_size, // @[decode.scala:426:14] output io_deq_uop_mem_signed, // @[decode.scala:426:14] output io_deq_uop_uses_ldq, // @[decode.scala:426:14] output io_deq_uop_uses_stq, // @[decode.scala:426:14] output io_deq_uop_is_unique, // @[decode.scala:426:14] output io_deq_uop_flush_on_commit, // @[decode.scala:426:14] output [2:0] io_deq_uop_csr_cmd, // @[decode.scala:426:14] output io_deq_uop_ldst_is_rs1, // @[decode.scala:426:14] output [5:0] io_deq_uop_ldst, // @[decode.scala:426:14] output [5:0] io_deq_uop_lrs1, // @[decode.scala:426:14] output [5:0] io_deq_uop_lrs2, // @[decode.scala:426:14] output [5:0] io_deq_uop_lrs3, // @[decode.scala:426:14] output [1:0] io_deq_uop_dst_rtype, // @[decode.scala:426:14] output [1:0] io_deq_uop_lrs1_rtype, // @[decode.scala:426:14] output [1:0] io_deq_uop_lrs2_rtype, // @[decode.scala:426:14] output io_deq_uop_frs3_en, // @[decode.scala:426:14] output io_deq_uop_fcn_dw, // @[decode.scala:426:14] output [4:0] io_deq_uop_fcn_op, // @[decode.scala:426:14] output io_deq_uop_fp_val, // @[decode.scala:426:14] output [2:0] io_deq_uop_fp_rm, // @[decode.scala:426:14] output [1:0] io_deq_uop_fp_typ, // @[decode.scala:426:14] output io_deq_uop_xcpt_pf_if, // @[decode.scala:426:14] output io_deq_uop_xcpt_ae_if, // @[decode.scala:426:14] output io_deq_uop_bp_debug_if, // @[decode.scala:426:14] output io_deq_uop_bp_xcpt_if, // @[decode.scala:426:14] output [2:0] io_deq_uop_debug_fsrc, // @[decode.scala:426:14] input io_status_debug, // @[decode.scala:426:14] input io_status_cease, // @[decode.scala:426:14] input io_status_wfi, // @[decode.scala:426:14] input [1:0] io_status_dprv, // @[decode.scala:426:14] input io_status_dv, // @[decode.scala:426:14] input [1:0] io_status_prv, // @[decode.scala:426:14] input io_status_v, // @[decode.scala:426:14] input io_status_sd, // @[decode.scala:426:14] input io_status_mpv, // @[decode.scala:426:14] input io_status_gva, // @[decode.scala:426:14] input io_status_tsr, // @[decode.scala:426:14] input io_status_tw, // @[decode.scala:426:14] input io_status_tvm, // @[decode.scala:426:14] input io_status_mxr, // @[decode.scala:426:14] input io_status_sum, // @[decode.scala:426:14] input io_status_mprv, // @[decode.scala:426:14] input [1:0] io_status_fs, // @[decode.scala:426:14] input [1:0] io_status_mpp, // @[decode.scala:426:14] input io_status_spp, // @[decode.scala:426:14] input io_status_mpie, // @[decode.scala:426:14] input io_status_spie, // @[decode.scala:426:14] input io_status_mie, // @[decode.scala:426:14] input io_status_sie, // @[decode.scala:426:14] output [31:0] io_csr_decode_inst, // @[decode.scala:426:14] input io_csr_decode_fp_illegal, // @[decode.scala:426:14] input io_csr_decode_fp_csr, // @[decode.scala:426:14] input io_csr_decode_read_illegal, // @[decode.scala:426:14] input io_csr_decode_write_illegal, // @[decode.scala:426:14] input io_csr_decode_write_flush, // @[decode.scala:426:14] input io_csr_decode_system_illegal, // @[decode.scala:426:14] input io_csr_decode_virtual_access_illegal, // @[decode.scala:426:14] input io_csr_decode_virtual_system_illegal, // @[decode.scala:426:14] input [2:0] io_fcsr_rm, // @[decode.scala:426:14] input io_interrupt, // @[decode.scala:426:14] input [63:0] io_interrupt_cause // @[decode.scala:426:14] ); wire [31:0] io_enq_uop_inst_0 = io_enq_uop_inst; // @[decode.scala:422:7] wire [31:0] io_enq_uop_debug_inst_0 = io_enq_uop_debug_inst; // @[decode.scala:422:7] wire io_enq_uop_is_rvc_0 = io_enq_uop_is_rvc; // @[decode.scala:422:7] wire [39:0] io_enq_uop_debug_pc_0 = io_enq_uop_debug_pc; // @[decode.scala:422:7] wire io_enq_uop_is_sfb_0 = io_enq_uop_is_sfb; // @[decode.scala:422:7] wire [4:0] io_enq_uop_ftq_idx_0 = io_enq_uop_ftq_idx; // @[decode.scala:422:7] wire io_enq_uop_edge_inst_0 = io_enq_uop_edge_inst; // @[decode.scala:422:7] wire [5:0] io_enq_uop_pc_lob_0 = io_enq_uop_pc_lob; // @[decode.scala:422:7] wire io_enq_uop_taken_0 = io_enq_uop_taken; // @[decode.scala:422:7] wire io_enq_uop_xcpt_pf_if_0 = io_enq_uop_xcpt_pf_if; // @[decode.scala:422:7] wire io_enq_uop_xcpt_ae_if_0 = io_enq_uop_xcpt_ae_if; // @[decode.scala:422:7] wire io_enq_uop_bp_debug_if_0 = io_enq_uop_bp_debug_if; // @[decode.scala:422:7] wire io_enq_uop_bp_xcpt_if_0 = io_enq_uop_bp_xcpt_if; // @[decode.scala:422:7] wire [2:0] io_enq_uop_debug_fsrc_0 = io_enq_uop_debug_fsrc; // @[decode.scala:422:7] wire io_status_debug_0 = io_status_debug; // @[decode.scala:422:7] wire io_status_cease_0 = io_status_cease; // @[decode.scala:422:7] wire io_status_wfi_0 = io_status_wfi; // @[decode.scala:422:7] wire [1:0] io_status_dprv_0 = io_status_dprv; // @[decode.scala:422:7] wire io_status_dv_0 = io_status_dv; // @[decode.scala:422:7] wire [1:0] io_status_prv_0 = io_status_prv; // @[decode.scala:422:7] wire io_status_v_0 = io_status_v; // @[decode.scala:422:7] wire io_status_sd_0 = io_status_sd; // @[decode.scala:422:7] wire io_status_mpv_0 = io_status_mpv; // @[decode.scala:422:7] wire io_status_gva_0 = io_status_gva; // @[decode.scala:422:7] wire io_status_tsr_0 = io_status_tsr; // @[decode.scala:422:7] wire io_status_tw_0 = io_status_tw; // @[decode.scala:422:7] wire io_status_tvm_0 = io_status_tvm; // @[decode.scala:422:7] wire io_status_mxr_0 = io_status_mxr; // @[decode.scala:422:7] wire io_status_sum_0 = io_status_sum; // @[decode.scala:422:7] wire io_status_mprv_0 = io_status_mprv; // @[decode.scala:422:7] wire [1:0] io_status_fs_0 = io_status_fs; // @[decode.scala:422:7] wire [1:0] io_status_mpp_0 = io_status_mpp; // @[decode.scala:422:7] wire io_status_spp_0 = io_status_spp; // @[decode.scala:422:7] wire io_status_mpie_0 = io_status_mpie; // @[decode.scala:422:7] wire io_status_spie_0 = io_status_spie; // @[decode.scala:422:7] wire io_status_mie_0 = io_status_mie; // @[decode.scala:422:7] wire io_status_sie_0 = io_status_sie; // @[decode.scala:422:7] wire io_csr_decode_fp_illegal_0 = io_csr_decode_fp_illegal; // @[decode.scala:422:7] wire io_csr_decode_fp_csr_0 = io_csr_decode_fp_csr; // @[decode.scala:422:7] wire io_csr_decode_read_illegal_0 = io_csr_decode_read_illegal; // @[decode.scala:422:7] wire io_csr_decode_write_illegal_0 = io_csr_decode_write_illegal; // @[decode.scala:422:7] wire io_csr_decode_write_flush_0 = io_csr_decode_write_flush; // @[decode.scala:422:7] wire io_csr_decode_system_illegal_0 = io_csr_decode_system_illegal; // @[decode.scala:422:7] wire io_csr_decode_virtual_access_illegal_0 = io_csr_decode_virtual_access_illegal; // @[decode.scala:422:7] wire io_csr_decode_virtual_system_illegal_0 = io_csr_decode_virtual_system_illegal; // @[decode.scala:422:7] wire [2:0] io_fcsr_rm_0 = io_fcsr_rm; // @[decode.scala:422:7] wire io_interrupt_0 = io_interrupt; // @[decode.scala:422:7] wire [63:0] io_interrupt_cause_0 = io_interrupt_cause; // @[decode.scala:422:7] wire [1:0] io_status_sxl = 2'h2; // @[decode.scala:422:7] wire [1:0] io_status_uxl = 2'h2; // @[decode.scala:422:7] wire io_csr_decode_vector_illegal = 1'h1; // @[decode.scala:422:7] wire io_csr_decode_rocc_illegal = 1'h1; // @[decode.scala:422:7] wire _id_illegal_insn_T_6 = 1'h1; // @[decode.scala:464:33] wire [7:0] io_status_zero1 = 8'h0; // @[decode.scala:422:7, :426:14] wire [22:0] io_status_zero2 = 23'h0; // @[decode.scala:422:7, :426:14] wire [31:0] io_status_isa = 32'h14112D; // @[decode.scala:422:7, :426:14] wire [63:0] io_enq_uop_exc_cause = 64'h0; // @[decode.scala:422:7, :426:14] wire [6:0] io_enq_uop_pdst = 7'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [6:0] io_enq_uop_prs1 = 7'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [6:0] io_enq_uop_prs2 = 7'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [6:0] io_enq_uop_prs3 = 7'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [6:0] io_enq_uop_stale_pdst = 7'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [6:0] io_deq_uop_pdst = 7'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [6:0] io_deq_uop_prs1 = 7'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [6:0] io_deq_uop_prs2 = 7'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [6:0] io_deq_uop_prs3 = 7'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [6:0] io_deq_uop_stale_pdst = 7'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [6:0] uop_pdst = 7'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [6:0] uop_prs1 = 7'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [6:0] uop_prs2 = 7'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [6:0] uop_prs3 = 7'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [6:0] uop_stale_pdst = 7'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [5:0] io_enq_uop_rob_idx = 6'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [5:0] io_enq_uop_ldst = 6'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [5:0] io_enq_uop_lrs1 = 6'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [5:0] io_enq_uop_lrs2 = 6'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [5:0] io_enq_uop_lrs3 = 6'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [5:0] io_deq_uop_rob_idx = 6'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [5:0] uop_rob_idx = 6'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [19:0] io_enq_uop_imm_packed = 20'h0; // @[decode.scala:422:7] wire [4:0] io_enq_uop_pimm = 5'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [4:0] io_enq_uop_ppred = 5'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [4:0] io_enq_uop_mem_cmd = 5'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [4:0] io_enq_uop_fcn_op = 5'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [4:0] io_deq_uop_ppred = 5'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [4:0] uop_ppred = 5'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [2:0] io_enq_uop_imm_sel = 3'h0; // @[decode.scala:422:7] wire [2:0] io_enq_uop_op2_sel = 3'h0; // @[decode.scala:422:7] wire [2:0] io_enq_uop_csr_cmd = 3'h0; // @[decode.scala:422:7] wire [2:0] io_enq_uop_fp_rm = 3'h0; // @[decode.scala:422:7] wire [2:0] io_enq_uop_debug_tsrc = 3'h0; // @[decode.scala:422:7] wire [2:0] io_deq_uop_debug_tsrc = 3'h0; // @[decode.scala:422:7] wire [2:0] uop_debug_tsrc = 3'h0; // @[decode.scala:428:17] wire [3:0] io_enq_uop_br_tag = 4'h0; // @[decode.scala:422:7] wire [3:0] io_enq_uop_br_type = 4'h0; // @[decode.scala:422:7] wire [3:0] io_enq_uop_ldq_idx = 4'h0; // @[decode.scala:422:7] wire [3:0] io_enq_uop_stq_idx = 4'h0; // @[decode.scala:422:7] wire [3:0] io_deq_uop_br_tag = 4'h0; // @[decode.scala:422:7] wire [3:0] io_deq_uop_ldq_idx = 4'h0; // @[decode.scala:422:7] wire [3:0] io_deq_uop_stq_idx = 4'h0; // @[decode.scala:422:7] wire [3:0] uop_br_tag = 4'h0; // @[decode.scala:428:17] wire [3:0] uop_ldq_idx = 4'h0; // @[decode.scala:428:17] wire [3:0] uop_stq_idx = 4'h0; // @[decode.scala:428:17] wire [11:0] io_enq_uop_br_mask = 12'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [11:0] io_deq_uop_br_mask = 12'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [11:0] uop_br_mask = 12'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [1:0] io_enq_uop_iw_p1_speculative_child = 2'h0; // @[decode.scala:422:7] wire [1:0] io_enq_uop_iw_p2_speculative_child = 2'h0; // @[decode.scala:422:7] wire [1:0] io_enq_uop_dis_col_sel = 2'h0; // @[decode.scala:422:7] wire [1:0] io_enq_uop_op1_sel = 2'h0; // @[decode.scala:422:7] wire [1:0] io_enq_uop_fp_ctrl_typeTagIn = 2'h0; // @[decode.scala:422:7] wire [1:0] io_enq_uop_fp_ctrl_typeTagOut = 2'h0; // @[decode.scala:422:7] wire [1:0] io_enq_uop_rxq_idx = 2'h0; // @[decode.scala:422:7] wire [1:0] io_enq_uop_mem_size = 2'h0; // @[decode.scala:422:7] wire [1:0] io_enq_uop_dst_rtype = 2'h0; // @[decode.scala:422:7] wire [1:0] io_enq_uop_lrs1_rtype = 2'h0; // @[decode.scala:422:7] wire [1:0] io_enq_uop_lrs2_rtype = 2'h0; // @[decode.scala:422:7] wire [1:0] io_enq_uop_fp_typ = 2'h0; // @[decode.scala:422:7] wire [1:0] io_deq_uop_iw_p1_speculative_child = 2'h0; // @[decode.scala:422:7] wire [1:0] io_deq_uop_iw_p2_speculative_child = 2'h0; // @[decode.scala:422:7] wire [1:0] io_deq_uop_dis_col_sel = 2'h0; // @[decode.scala:422:7] wire [1:0] io_deq_uop_rxq_idx = 2'h0; // @[decode.scala:422:7] wire [1:0] io_status_xs = 2'h0; // @[decode.scala:422:7] wire [1:0] io_status_vs = 2'h0; // @[decode.scala:422:7] wire [1:0] uop_iw_p1_speculative_child = 2'h0; // @[decode.scala:428:17] wire [1:0] uop_iw_p2_speculative_child = 2'h0; // @[decode.scala:428:17] wire [1:0] uop_dis_col_sel = 2'h0; // @[decode.scala:428:17] wire [1:0] uop_rxq_idx = 2'h0; // @[decode.scala:428:17] wire io_enq_uop_iq_type_0 = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_iq_type_1 = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_iq_type_2 = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_iq_type_3 = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fu_code_0 = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fu_code_1 = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fu_code_2 = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fu_code_3 = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fu_code_4 = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fu_code_5 = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fu_code_6 = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fu_code_7 = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fu_code_8 = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fu_code_9 = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_iw_issued = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_iw_issued_partial_agen = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_iw_issued_partial_dgen = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_iw_p1_bypass_hint = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_iw_p2_bypass_hint = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_iw_p3_bypass_hint = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_is_fence = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_is_fencei = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_is_sfence = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_is_amo = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_is_eret = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_is_sys_pc2epc = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_is_rocc = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_is_mov = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_imm_rename = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fp_ctrl_ldst = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fp_ctrl_wen = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fp_ctrl_ren1 = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fp_ctrl_ren2 = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fp_ctrl_ren3 = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fp_ctrl_swap12 = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fp_ctrl_swap23 = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fp_ctrl_fromint = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fp_ctrl_toint = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fp_ctrl_fastpipe = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fp_ctrl_fma = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fp_ctrl_div = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fp_ctrl_sqrt = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fp_ctrl_wflags = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fp_ctrl_vec = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_prs1_busy = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_prs2_busy = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_prs3_busy = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_ppred_busy = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_exception = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_mem_signed = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_uses_ldq = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_uses_stq = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_is_unique = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_flush_on_commit = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_ldst_is_rs1 = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_frs3_en = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fcn_dw = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fp_val = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_xcpt_ma_if = 1'h0; // @[decode.scala:422:7] wire io_deq_uop_iw_issued = 1'h0; // @[decode.scala:422:7] wire io_deq_uop_iw_issued_partial_agen = 1'h0; // @[decode.scala:422:7] wire io_deq_uop_iw_issued_partial_dgen = 1'h0; // @[decode.scala:422:7] wire io_deq_uop_iw_p1_bypass_hint = 1'h0; // @[decode.scala:422:7] wire io_deq_uop_iw_p2_bypass_hint = 1'h0; // @[decode.scala:422:7] wire io_deq_uop_iw_p3_bypass_hint = 1'h0; // @[decode.scala:422:7] wire io_deq_uop_fp_ctrl_vec = 1'h0; // @[decode.scala:422:7] wire io_deq_uop_prs1_busy = 1'h0; // @[decode.scala:422:7] wire io_deq_uop_prs2_busy = 1'h0; // @[decode.scala:422:7] wire io_deq_uop_prs3_busy = 1'h0; // @[decode.scala:422:7] wire io_deq_uop_ppred_busy = 1'h0; // @[decode.scala:422:7] wire io_deq_uop_xcpt_ma_if = 1'h0; // @[decode.scala:422:7] wire io_status_mbe = 1'h0; // @[decode.scala:422:7] wire io_status_sbe = 1'h0; // @[decode.scala:422:7] wire io_status_sd_rv32 = 1'h0; // @[decode.scala:422:7] wire io_status_ube = 1'h0; // @[decode.scala:422:7] wire io_status_upie = 1'h0; // @[decode.scala:422:7] wire io_status_hie = 1'h0; // @[decode.scala:422:7] wire io_status_uie = 1'h0; // @[decode.scala:422:7] wire io_csr_decode_vector_csr = 1'h0; // @[decode.scala:422:7] wire uop_iw_issued = 1'h0; // @[decode.scala:428:17] wire uop_iw_issued_partial_agen = 1'h0; // @[decode.scala:428:17] wire uop_iw_issued_partial_dgen = 1'h0; // @[decode.scala:428:17] wire uop_iw_p1_bypass_hint = 1'h0; // @[decode.scala:428:17] wire uop_iw_p2_bypass_hint = 1'h0; // @[decode.scala:428:17] wire uop_iw_p3_bypass_hint = 1'h0; // @[decode.scala:428:17] wire uop_fp_ctrl_vec = 1'h0; // @[decode.scala:428:17] wire uop_prs1_busy = 1'h0; // @[decode.scala:428:17] wire uop_prs2_busy = 1'h0; // @[decode.scala:428:17] wire uop_prs3_busy = 1'h0; // @[decode.scala:428:17] wire uop_ppred_busy = 1'h0; // @[decode.scala:428:17] wire uop_xcpt_ma_if = 1'h0; // @[decode.scala:428:17] wire cs_fp_vec = 1'h0; // @[decode.scala:447:16] wire _id_illegal_insn_T_7 = 1'h0; // @[decode.scala:464:19] wire _id_illegal_insn_T_8 = 1'h0; // @[decode.scala:464:16] wire [31:0] uop_inst = io_enq_uop_inst_0; // @[decode.scala:422:7, :428:17] wire [31:0] uop_debug_inst = io_enq_uop_debug_inst_0; // @[decode.scala:422:7, :428:17] wire uop_is_rvc = io_enq_uop_is_rvc_0; // @[decode.scala:422:7, :428:17] wire [39:0] uop_debug_pc = io_enq_uop_debug_pc_0; // @[decode.scala:422:7, :428:17] wire uop_is_sfb = io_enq_uop_is_sfb_0; // @[decode.scala:422:7, :428:17] wire [4:0] uop_ftq_idx = io_enq_uop_ftq_idx_0; // @[decode.scala:422:7, :428:17] wire uop_edge_inst = io_enq_uop_edge_inst_0; // @[decode.scala:422:7, :428:17] wire [5:0] uop_pc_lob = io_enq_uop_pc_lob_0; // @[decode.scala:422:7, :428:17] wire uop_taken = io_enq_uop_taken_0; // @[decode.scala:422:7, :428:17] wire uop_xcpt_pf_if = io_enq_uop_xcpt_pf_if_0; // @[decode.scala:422:7, :428:17] wire uop_xcpt_ae_if = io_enq_uop_xcpt_ae_if_0; // @[decode.scala:422:7, :428:17] wire uop_bp_debug_if = io_enq_uop_bp_debug_if_0; // @[decode.scala:422:7, :428:17] wire uop_bp_xcpt_if = io_enq_uop_bp_xcpt_if_0; // @[decode.scala:422:7, :428:17] wire [2:0] uop_debug_fsrc = io_enq_uop_debug_fsrc_0; // @[decode.scala:422:7, :428:17] wire uop_iq_type_0; // @[decode.scala:428:17] wire uop_iq_type_1; // @[decode.scala:428:17] wire uop_iq_type_2; // @[decode.scala:428:17] wire uop_iq_type_3; // @[decode.scala:428:17] wire uop_fu_code_0; // @[decode.scala:428:17] wire uop_fu_code_1; // @[decode.scala:428:17] wire uop_fu_code_2; // @[decode.scala:428:17] wire uop_fu_code_3; // @[decode.scala:428:17] wire uop_fu_code_4; // @[decode.scala:428:17] wire uop_fu_code_5; // @[decode.scala:428:17] wire uop_fu_code_6; // @[decode.scala:428:17] wire uop_fu_code_7; // @[decode.scala:428:17] wire uop_fu_code_8; // @[decode.scala:428:17] wire uop_fu_code_9; // @[decode.scala:428:17] wire [3:0] uop_br_type; // @[decode.scala:428:17] wire uop_is_fence; // @[decode.scala:428:17] wire uop_is_fencei; // @[decode.scala:428:17] wire uop_is_sfence; // @[decode.scala:428:17] wire uop_is_amo; // @[decode.scala:428:17] wire uop_is_eret; // @[decode.scala:428:17] wire uop_is_sys_pc2epc; // @[decode.scala:428:17] wire uop_is_rocc; // @[decode.scala:428:17] wire uop_is_mov; // @[decode.scala:428:17] wire uop_imm_rename; // @[decode.scala:428:17] wire [2:0] uop_imm_sel; // @[decode.scala:428:17] wire [4:0] uop_pimm; // @[decode.scala:428:17] wire [19:0] uop_imm_packed; // @[decode.scala:428:17] wire [1:0] uop_op1_sel; // @[decode.scala:428:17] wire [2:0] uop_op2_sel; // @[decode.scala:428:17] wire uop_fp_ctrl_ldst; // @[decode.scala:428:17] wire uop_fp_ctrl_wen; // @[decode.scala:428:17] wire uop_fp_ctrl_ren1; // @[decode.scala:428:17] wire uop_fp_ctrl_ren2; // @[decode.scala:428:17] wire uop_fp_ctrl_ren3; // @[decode.scala:428:17] wire uop_fp_ctrl_swap12; // @[decode.scala:428:17] wire uop_fp_ctrl_swap23; // @[decode.scala:428:17] wire [1:0] uop_fp_ctrl_typeTagIn; // @[decode.scala:428:17] wire [1:0] uop_fp_ctrl_typeTagOut; // @[decode.scala:428:17] wire uop_fp_ctrl_fromint; // @[decode.scala:428:17] wire uop_fp_ctrl_toint; // @[decode.scala:428:17] wire uop_fp_ctrl_fastpipe; // @[decode.scala:428:17] wire uop_fp_ctrl_fma; // @[decode.scala:428:17] wire uop_fp_ctrl_div; // @[decode.scala:428:17] wire uop_fp_ctrl_sqrt; // @[decode.scala:428:17] wire uop_fp_ctrl_wflags; // @[decode.scala:428:17] wire uop_exception; // @[decode.scala:428:17] wire [63:0] uop_exc_cause; // @[decode.scala:428:17] wire [4:0] uop_mem_cmd; // @[decode.scala:428:17] wire [1:0] uop_mem_size; // @[decode.scala:428:17] wire uop_mem_signed; // @[decode.scala:428:17] wire uop_uses_ldq; // @[decode.scala:428:17] wire uop_uses_stq; // @[decode.scala:428:17] wire uop_is_unique; // @[decode.scala:428:17] wire uop_flush_on_commit; // @[decode.scala:428:17] wire [2:0] uop_csr_cmd; // @[decode.scala:428:17] wire uop_ldst_is_rs1; // @[decode.scala:428:17] wire [5:0] uop_ldst; // @[decode.scala:428:17] wire [5:0] uop_lrs1; // @[decode.scala:428:17] wire [5:0] uop_lrs2; // @[decode.scala:428:17] wire [5:0] uop_lrs3; // @[decode.scala:428:17] wire [1:0] uop_dst_rtype; // @[decode.scala:428:17] wire [1:0] uop_lrs1_rtype; // @[decode.scala:428:17] wire [1:0] uop_lrs2_rtype; // @[decode.scala:428:17] wire uop_frs3_en; // @[decode.scala:428:17] wire uop_fcn_dw; // @[decode.scala:428:17] wire [4:0] uop_fcn_op; // @[decode.scala:428:17] wire uop_fp_val; // @[decode.scala:428:17] wire [2:0] uop_fp_rm; // @[decode.scala:428:17] wire [1:0] uop_fp_typ; // @[decode.scala:428:17] wire io_deq_uop_iq_type_0_0; // @[decode.scala:422:7] wire io_deq_uop_iq_type_1_0; // @[decode.scala:422:7] wire io_deq_uop_iq_type_2_0; // @[decode.scala:422:7] wire io_deq_uop_iq_type_3_0; // @[decode.scala:422:7] wire io_deq_uop_fu_code_0_0; // @[decode.scala:422:7] wire io_deq_uop_fu_code_1_0; // @[decode.scala:422:7] wire io_deq_uop_fu_code_2_0; // @[decode.scala:422:7] wire io_deq_uop_fu_code_3_0; // @[decode.scala:422:7] wire io_deq_uop_fu_code_4_0; // @[decode.scala:422:7] wire io_deq_uop_fu_code_5_0; // @[decode.scala:422:7] wire io_deq_uop_fu_code_6_0; // @[decode.scala:422:7] wire io_deq_uop_fu_code_7_0; // @[decode.scala:422:7] wire io_deq_uop_fu_code_8_0; // @[decode.scala:422:7] wire io_deq_uop_fu_code_9_0; // @[decode.scala:422:7] wire io_deq_uop_fp_ctrl_ldst_0; // @[decode.scala:422:7] wire io_deq_uop_fp_ctrl_wen_0; // @[decode.scala:422:7] wire io_deq_uop_fp_ctrl_ren1_0; // @[decode.scala:422:7] wire io_deq_uop_fp_ctrl_ren2_0; // @[decode.scala:422:7] wire io_deq_uop_fp_ctrl_ren3_0; // @[decode.scala:422:7] wire io_deq_uop_fp_ctrl_swap12_0; // @[decode.scala:422:7] wire io_deq_uop_fp_ctrl_swap23_0; // @[decode.scala:422:7] wire [1:0] io_deq_uop_fp_ctrl_typeTagIn_0; // @[decode.scala:422:7] wire [1:0] io_deq_uop_fp_ctrl_typeTagOut_0; // @[decode.scala:422:7] wire io_deq_uop_fp_ctrl_fromint_0; // @[decode.scala:422:7] wire io_deq_uop_fp_ctrl_toint_0; // @[decode.scala:422:7] wire io_deq_uop_fp_ctrl_fastpipe_0; // @[decode.scala:422:7] wire io_deq_uop_fp_ctrl_fma_0; // @[decode.scala:422:7] wire io_deq_uop_fp_ctrl_div_0; // @[decode.scala:422:7] wire io_deq_uop_fp_ctrl_sqrt_0; // @[decode.scala:422:7] wire io_deq_uop_fp_ctrl_wflags_0; // @[decode.scala:422:7] wire [31:0] io_deq_uop_inst_0; // @[decode.scala:422:7] wire [31:0] io_deq_uop_debug_inst_0; // @[decode.scala:422:7] wire io_deq_uop_is_rvc_0; // @[decode.scala:422:7] wire [39:0] io_deq_uop_debug_pc_0; // @[decode.scala:422:7] wire [3:0] io_deq_uop_br_type_0; // @[decode.scala:422:7] wire io_deq_uop_is_sfb_0; // @[decode.scala:422:7] wire io_deq_uop_is_fence_0; // @[decode.scala:422:7] wire io_deq_uop_is_fencei_0; // @[decode.scala:422:7] wire io_deq_uop_is_sfence_0; // @[decode.scala:422:7] wire io_deq_uop_is_amo_0; // @[decode.scala:422:7] wire io_deq_uop_is_eret_0; // @[decode.scala:422:7] wire io_deq_uop_is_sys_pc2epc_0; // @[decode.scala:422:7] wire io_deq_uop_is_rocc_0; // @[decode.scala:422:7] wire io_deq_uop_is_mov_0; // @[decode.scala:422:7] wire [4:0] io_deq_uop_ftq_idx_0; // @[decode.scala:422:7] wire io_deq_uop_edge_inst_0; // @[decode.scala:422:7] wire [5:0] io_deq_uop_pc_lob_0; // @[decode.scala:422:7] wire io_deq_uop_taken_0; // @[decode.scala:422:7] wire io_deq_uop_imm_rename_0; // @[decode.scala:422:7] wire [2:0] io_deq_uop_imm_sel_0; // @[decode.scala:422:7] wire [4:0] io_deq_uop_pimm_0; // @[decode.scala:422:7] wire [19:0] io_deq_uop_imm_packed_0; // @[decode.scala:422:7] wire [1:0] io_deq_uop_op1_sel_0; // @[decode.scala:422:7] wire [2:0] io_deq_uop_op2_sel_0; // @[decode.scala:422:7] wire io_deq_uop_exception_0; // @[decode.scala:422:7] wire [63:0] io_deq_uop_exc_cause_0; // @[decode.scala:422:7] wire [4:0] io_deq_uop_mem_cmd_0; // @[decode.scala:422:7] wire [1:0] io_deq_uop_mem_size_0; // @[decode.scala:422:7] wire io_deq_uop_mem_signed_0; // @[decode.scala:422:7] wire io_deq_uop_uses_ldq_0; // @[decode.scala:422:7] wire io_deq_uop_uses_stq_0; // @[decode.scala:422:7] wire io_deq_uop_is_unique_0; // @[decode.scala:422:7] wire io_deq_uop_flush_on_commit_0; // @[decode.scala:422:7] wire [2:0] io_deq_uop_csr_cmd_0; // @[decode.scala:422:7] wire io_deq_uop_ldst_is_rs1_0; // @[decode.scala:422:7] wire [5:0] io_deq_uop_ldst_0; // @[decode.scala:422:7] wire [5:0] io_deq_uop_lrs1_0; // @[decode.scala:422:7] wire [5:0] io_deq_uop_lrs2_0; // @[decode.scala:422:7] wire [5:0] io_deq_uop_lrs3_0; // @[decode.scala:422:7] wire [1:0] io_deq_uop_dst_rtype_0; // @[decode.scala:422:7] wire [1:0] io_deq_uop_lrs1_rtype_0; // @[decode.scala:422:7] wire [1:0] io_deq_uop_lrs2_rtype_0; // @[decode.scala:422:7] wire io_deq_uop_frs3_en_0; // @[decode.scala:422:7] wire io_deq_uop_fcn_dw_0; // @[decode.scala:422:7] wire [4:0] io_deq_uop_fcn_op_0; // @[decode.scala:422:7] wire io_deq_uop_fp_val_0; // @[decode.scala:422:7] wire [2:0] io_deq_uop_fp_rm_0; // @[decode.scala:422:7] wire [1:0] io_deq_uop_fp_typ_0; // @[decode.scala:422:7] wire io_deq_uop_xcpt_pf_if_0; // @[decode.scala:422:7] wire io_deq_uop_xcpt_ae_if_0; // @[decode.scala:422:7] wire io_deq_uop_bp_debug_if_0; // @[decode.scala:422:7] wire io_deq_uop_bp_xcpt_if_0; // @[decode.scala:422:7] wire [2:0] io_deq_uop_debug_fsrc_0; // @[decode.scala:422:7] wire [31:0] io_csr_decode_inst_0; // @[decode.scala:422:7] assign io_deq_uop_inst_0 = uop_inst; // @[decode.scala:422:7, :428:17] assign io_csr_decode_inst_0 = uop_inst; // @[decode.scala:422:7, :428:17] wire [31:0] cs_decoder_decoded_plaInput = uop_inst; // @[pla.scala:77:22] wire [31:0] _uop_is_sys_pc2epc_T = uop_inst; // @[decode.scala:428:17, :529:29] wire [31:0] _uop_is_sys_pc2epc_T_2 = uop_inst; // @[decode.scala:428:17, :529:48] wire [31:0] _uop_is_eret_T = uop_inst; // @[decode.scala:428:17, :530:26] wire [31:0] _uop_is_eret_T_2 = uop_inst; // @[decode.scala:428:17, :530:44] wire [31:0] _uop_is_eret_T_5 = uop_inst; // @[decode.scala:428:17, :530:63] wire [31:0] _uop_is_eret_T_8 = uop_inst; // @[decode.scala:428:17, :530:80] wire [31:0] _uop_is_eret_T_11 = uop_inst; // @[decode.scala:428:17, :530:97] assign io_deq_uop_debug_inst_0 = uop_debug_inst; // @[decode.scala:422:7, :428:17] assign io_deq_uop_is_rvc_0 = uop_is_rvc; // @[decode.scala:422:7, :428:17] assign io_deq_uop_debug_pc_0 = uop_debug_pc; // @[decode.scala:422:7, :428:17] wire _uop_iq_type_0_T_2; // @[decode.scala:489:98] assign io_deq_uop_iq_type_0_0 = uop_iq_type_0; // @[decode.scala:422:7, :428:17] wire _uop_iq_type_1_T_6; // @[decode.scala:487:98] assign io_deq_uop_iq_type_1_0 = uop_iq_type_1; // @[decode.scala:422:7, :428:17] wire _uop_iq_type_2_T; // @[decode.scala:488:84] assign io_deq_uop_iq_type_2_0 = uop_iq_type_2; // @[decode.scala:422:7, :428:17] wire _uop_iq_type_3_T_4; // @[decode.scala:490:98] assign io_deq_uop_iq_type_3_0 = uop_iq_type_3; // @[decode.scala:422:7, :428:17] assign io_deq_uop_fu_code_0_0 = uop_fu_code_0; // @[decode.scala:422:7, :428:17] assign io_deq_uop_fu_code_1_0 = uop_fu_code_1; // @[decode.scala:422:7, :428:17] assign io_deq_uop_fu_code_2_0 = uop_fu_code_2; // @[decode.scala:422:7, :428:17] assign io_deq_uop_fu_code_3_0 = uop_fu_code_3; // @[decode.scala:422:7, :428:17] assign io_deq_uop_fu_code_4_0 = uop_fu_code_4; // @[decode.scala:422:7, :428:17] assign io_deq_uop_fu_code_5_0 = uop_fu_code_5; // @[decode.scala:422:7, :428:17] assign io_deq_uop_fu_code_6_0 = uop_fu_code_6; // @[decode.scala:422:7, :428:17] assign io_deq_uop_fu_code_7_0 = uop_fu_code_7; // @[decode.scala:422:7, :428:17] assign io_deq_uop_fu_code_8_0 = uop_fu_code_8; // @[decode.scala:422:7, :428:17] assign io_deq_uop_fu_code_9_0 = uop_fu_code_9; // @[decode.scala:422:7, :428:17] wire [3:0] _uop_br_type_T_30; // @[decode.scala:604:62] assign io_deq_uop_br_type_0 = uop_br_type; // @[decode.scala:422:7, :428:17] assign io_deq_uop_is_sfb_0 = uop_is_sfb; // @[decode.scala:422:7, :428:17] wire _uop_is_fence_T_1; // @[decode.scala:526:26] assign io_deq_uop_is_fence_0 = uop_is_fence; // @[decode.scala:422:7, :428:17] wire _uop_is_fencei_T_1; // @[decode.scala:527:26] assign io_deq_uop_is_fencei_0 = uop_is_fencei; // @[decode.scala:422:7, :428:17] wire _uop_is_sfence_T_1; // @[decode.scala:528:26] assign io_deq_uop_is_sfence_0 = uop_is_sfence; // @[decode.scala:422:7, :428:17] wire cs_is_amo; // @[decode.scala:447:16] assign io_deq_uop_is_amo_0 = uop_is_amo; // @[decode.scala:422:7, :428:17] wire _uop_is_eret_T_13; // @[decode.scala:530:89] assign io_deq_uop_is_eret_0 = uop_is_eret; // @[decode.scala:422:7, :428:17] wire _uop_is_sys_pc2epc_T_4; // @[decode.scala:529:40] assign io_deq_uop_is_sys_pc2epc_0 = uop_is_sys_pc2epc; // @[decode.scala:422:7, :428:17] wire _uop_is_rocc_T_18; // @[decode.scala:532:81] assign io_deq_uop_is_rocc_0 = uop_is_rocc; // @[decode.scala:422:7, :428:17] wire _id_illegal_insn_T_4 = uop_is_rocc; // @[decode.scala:428:17, :463:18] wire _uop_is_mov_T_3; // @[decode.scala:485:34] assign io_deq_uop_is_mov_0 = uop_is_mov; // @[decode.scala:422:7, :428:17] assign io_deq_uop_ftq_idx_0 = uop_ftq_idx; // @[decode.scala:422:7, :428:17] assign io_deq_uop_edge_inst_0 = uop_edge_inst; // @[decode.scala:422:7, :428:17] assign io_deq_uop_pc_lob_0 = uop_pc_lob; // @[decode.scala:422:7, :428:17] assign io_deq_uop_taken_0 = uop_taken; // @[decode.scala:422:7, :428:17] assign io_deq_uop_imm_rename_0 = uop_imm_rename; // @[decode.scala:422:7, :428:17] assign io_deq_uop_imm_sel_0 = uop_imm_sel; // @[decode.scala:422:7, :428:17] assign io_deq_uop_pimm_0 = uop_pimm; // @[decode.scala:422:7, :428:17] wire [19:0] imm_packed; // @[decode.scala:541:23] assign io_deq_uop_imm_packed_0 = uop_imm_packed; // @[decode.scala:422:7, :428:17] assign io_deq_uop_op1_sel_0 = uop_op1_sel; // @[decode.scala:422:7, :428:17] assign io_deq_uop_op2_sel_0 = uop_op2_sel; // @[decode.scala:422:7, :428:17] wire cs_fp_ldst; // @[decode.scala:447:16] assign io_deq_uop_fp_ctrl_ldst_0 = uop_fp_ctrl_ldst; // @[decode.scala:422:7, :428:17] wire cs_fp_wen; // @[decode.scala:447:16] assign io_deq_uop_fp_ctrl_wen_0 = uop_fp_ctrl_wen; // @[decode.scala:422:7, :428:17] wire cs_fp_ren1; // @[decode.scala:447:16] assign io_deq_uop_fp_ctrl_ren1_0 = uop_fp_ctrl_ren1; // @[decode.scala:422:7, :428:17] wire cs_fp_ren2; // @[decode.scala:447:16] assign io_deq_uop_fp_ctrl_ren2_0 = uop_fp_ctrl_ren2; // @[decode.scala:422:7, :428:17] wire cs_fp_ren3; // @[decode.scala:447:16] assign io_deq_uop_fp_ctrl_ren3_0 = uop_fp_ctrl_ren3; // @[decode.scala:422:7, :428:17] wire cs_fp_swap12; // @[decode.scala:447:16] assign io_deq_uop_fp_ctrl_swap12_0 = uop_fp_ctrl_swap12; // @[decode.scala:422:7, :428:17] wire cs_fp_swap23; // @[decode.scala:447:16] assign io_deq_uop_fp_ctrl_swap23_0 = uop_fp_ctrl_swap23; // @[decode.scala:422:7, :428:17] wire [1:0] cs_fp_typeTagIn; // @[decode.scala:447:16] assign io_deq_uop_fp_ctrl_typeTagIn_0 = uop_fp_ctrl_typeTagIn; // @[decode.scala:422:7, :428:17] wire [1:0] cs_fp_typeTagOut; // @[decode.scala:447:16] assign io_deq_uop_fp_ctrl_typeTagOut_0 = uop_fp_ctrl_typeTagOut; // @[decode.scala:422:7, :428:17] wire cs_fp_fromint; // @[decode.scala:447:16] assign io_deq_uop_fp_ctrl_fromint_0 = uop_fp_ctrl_fromint; // @[decode.scala:422:7, :428:17] wire cs_fp_toint; // @[decode.scala:447:16] assign io_deq_uop_fp_ctrl_toint_0 = uop_fp_ctrl_toint; // @[decode.scala:422:7, :428:17] wire cs_fp_fastpipe; // @[decode.scala:447:16] assign io_deq_uop_fp_ctrl_fastpipe_0 = uop_fp_ctrl_fastpipe; // @[decode.scala:422:7, :428:17] wire cs_fp_fma; // @[decode.scala:447:16] assign io_deq_uop_fp_ctrl_fma_0 = uop_fp_ctrl_fma; // @[decode.scala:422:7, :428:17] wire cs_fp_div; // @[decode.scala:447:16] assign io_deq_uop_fp_ctrl_div_0 = uop_fp_ctrl_div; // @[decode.scala:422:7, :428:17] wire cs_fp_sqrt; // @[decode.scala:447:16] assign io_deq_uop_fp_ctrl_sqrt_0 = uop_fp_ctrl_sqrt; // @[decode.scala:422:7, :428:17] wire cs_fp_wflags; // @[decode.scala:447:16] assign io_deq_uop_fp_ctrl_wflags_0 = uop_fp_ctrl_wflags; // @[decode.scala:422:7, :428:17] wire xcpt_valid; // @[decode.scala:470:26] assign io_deq_uop_exception_0 = uop_exception; // @[decode.scala:422:7, :428:17] wire [63:0] xcpt_cause; // @[Mux.scala:50:70] assign io_deq_uop_exc_cause_0 = uop_exc_cause; // @[decode.scala:422:7, :428:17] wire [4:0] cs_mem_cmd; // @[decode.scala:447:16] assign io_deq_uop_mem_cmd_0 = uop_mem_cmd; // @[decode.scala:422:7, :428:17] wire [1:0] _uop_mem_size_T_7; // @[decode.scala:521:24] assign io_deq_uop_mem_size_0 = uop_mem_size; // @[decode.scala:422:7, :428:17] wire _uop_mem_signed_T_1; // @[decode.scala:522:21] assign io_deq_uop_mem_signed_0 = uop_mem_signed; // @[decode.scala:422:7, :428:17] wire cs_uses_ldq; // @[decode.scala:447:16] assign io_deq_uop_uses_ldq_0 = uop_uses_ldq; // @[decode.scala:422:7, :428:17] wire cs_uses_stq; // @[decode.scala:447:16] assign io_deq_uop_uses_stq_0 = uop_uses_stq; // @[decode.scala:422:7, :428:17] wire cs_inst_unique; // @[decode.scala:447:16] assign io_deq_uop_is_unique_0 = uop_is_unique; // @[decode.scala:422:7, :428:17] wire _uop_flush_on_commit_T_3; // @[decode.scala:533:45] assign io_deq_uop_flush_on_commit_0 = uop_flush_on_commit; // @[decode.scala:422:7, :428:17] assign io_deq_uop_csr_cmd_0 = uop_csr_cmd; // @[decode.scala:422:7, :428:17] assign io_deq_uop_ldst_is_rs1_0 = uop_ldst_is_rs1; // @[decode.scala:422:7, :428:17] assign io_deq_uop_ldst_0 = uop_ldst; // @[decode.scala:422:7, :428:17] assign io_deq_uop_lrs1_0 = uop_lrs1; // @[decode.scala:422:7, :428:17] assign io_deq_uop_lrs2_0 = uop_lrs2; // @[decode.scala:422:7, :428:17] assign io_deq_uop_lrs3_0 = uop_lrs3; // @[decode.scala:422:7, :428:17] wire [1:0] cs_dst_type; // @[decode.scala:447:16] assign io_deq_uop_dst_rtype_0 = uop_dst_rtype; // @[decode.scala:422:7, :428:17] assign io_deq_uop_lrs1_rtype_0 = uop_lrs1_rtype; // @[decode.scala:422:7, :428:17] assign io_deq_uop_lrs2_rtype_0 = uop_lrs2_rtype; // @[decode.scala:422:7, :428:17] wire cs_frs3_en; // @[decode.scala:447:16] assign io_deq_uop_frs3_en_0 = uop_frs3_en; // @[decode.scala:422:7, :428:17] wire cs_fcn_dw; // @[decode.scala:447:16] assign io_deq_uop_fcn_dw_0 = uop_fcn_dw; // @[decode.scala:422:7, :428:17] wire [4:0] cs_fcn_op; // @[decode.scala:447:16] assign io_deq_uop_fcn_op_0 = uop_fcn_op; // @[decode.scala:422:7, :428:17] wire cs_fp_val; // @[decode.scala:447:16] assign io_deq_uop_fp_val_0 = uop_fp_val; // @[decode.scala:422:7, :428:17] wire [2:0] _uop_fp_rm_T_3; // @[decode.scala:556:21] assign io_deq_uop_fp_rm_0 = uop_fp_rm; // @[decode.scala:422:7, :428:17] wire [1:0] _uop_fp_typ_T; // @[decode.scala:557:22] assign io_deq_uop_fp_typ_0 = uop_fp_typ; // @[decode.scala:422:7, :428:17] assign io_deq_uop_xcpt_pf_if_0 = uop_xcpt_pf_if; // @[decode.scala:422:7, :428:17] assign io_deq_uop_xcpt_ae_if_0 = uop_xcpt_ae_if; // @[decode.scala:422:7, :428:17] assign io_deq_uop_bp_debug_if_0 = uop_bp_debug_if; // @[decode.scala:422:7, :428:17] assign io_deq_uop_bp_xcpt_if_0 = uop_bp_xcpt_if; // @[decode.scala:422:7, :428:17] assign io_deq_uop_debug_fsrc_0 = uop_debug_fsrc; // @[decode.scala:422:7, :428:17] wire [4:0] LDST = uop_inst[11:7]; // @[decode.scala:428:17, :441:18] wire [4:0] _di24_20_T_3 = uop_inst[11:7]; // @[decode.scala:428:17, :441:18, :540:69] wire [4:0] LRS1 = uop_inst[19:15]; // @[decode.scala:428:17, :442:18] wire [4:0] LRS2 = uop_inst[24:20]; // @[decode.scala:428:17, :443:18] wire [4:0] _di24_20_T_4 = uop_inst[24:20]; // @[decode.scala:428:17, :443:18, :540:81] wire [4:0] LRS3 = uop_inst[31:27]; // @[decode.scala:428:17, :444:18] wire cs_decoder_0; // @[Decode.scala:50:77] wire cs_decoder_1; // @[Decode.scala:50:77] assign uop_fp_val = cs_fp_val; // @[decode.scala:428:17, :447:16] wire [9:0] cs_decoder_2; // @[Decode.scala:50:77] wire [1:0] cs_decoder_3; // @[Decode.scala:50:77] assign uop_dst_rtype = cs_dst_type; // @[decode.scala:428:17, :447:16] wire [1:0] cs_decoder_4; // @[Decode.scala:50:77] wire [1:0] cs_decoder_5; // @[Decode.scala:50:77] wire cs_decoder_6; // @[Decode.scala:50:77] assign uop_frs3_en = cs_frs3_en; // @[decode.scala:428:17, :447:16] wire [2:0] cs_decoder_7; // @[Decode.scala:50:77] wire cs_decoder_8; // @[Decode.scala:50:77] assign uop_uses_ldq = cs_uses_ldq; // @[decode.scala:428:17, :447:16] wire cs_decoder_9; // @[Decode.scala:50:77] assign uop_uses_stq = cs_uses_stq; // @[decode.scala:428:17, :447:16] wire cs_decoder_10; // @[Decode.scala:50:77] assign uop_is_amo = cs_is_amo; // @[decode.scala:428:17, :447:16] wire [4:0] cs_decoder_11; // @[Decode.scala:50:77] assign uop_mem_cmd = cs_mem_cmd; // @[decode.scala:428:17, :447:16] wire cs_decoder_12; // @[Decode.scala:50:77] assign uop_is_unique = cs_inst_unique; // @[decode.scala:428:17, :447:16] wire cs_decoder_13; // @[Decode.scala:50:77] wire [2:0] cs_decoder_14; // @[Decode.scala:50:77] wire cs_decoder_15; // @[Decode.scala:50:77] assign uop_fcn_dw = cs_fcn_dw; // @[decode.scala:428:17, :447:16] wire [4:0] cs_decoder_16; // @[Decode.scala:50:77] assign uop_fcn_op = cs_fcn_op; // @[decode.scala:428:17, :447:16] wire cs_decoder_17; // @[Decode.scala:50:77] assign uop_fp_ctrl_ldst = cs_fp_ldst; // @[decode.scala:428:17, :447:16] wire cs_decoder_18; // @[Decode.scala:50:77] assign uop_fp_ctrl_wen = cs_fp_wen; // @[decode.scala:428:17, :447:16] wire cs_decoder_19; // @[Decode.scala:50:77] assign uop_fp_ctrl_ren1 = cs_fp_ren1; // @[decode.scala:428:17, :447:16] wire cs_decoder_20; // @[Decode.scala:50:77] assign uop_fp_ctrl_ren2 = cs_fp_ren2; // @[decode.scala:428:17, :447:16] wire cs_decoder_21; // @[Decode.scala:50:77] assign uop_fp_ctrl_ren3 = cs_fp_ren3; // @[decode.scala:428:17, :447:16] wire cs_decoder_22; // @[Decode.scala:50:77] assign uop_fp_ctrl_swap12 = cs_fp_swap12; // @[decode.scala:428:17, :447:16] wire cs_decoder_23; // @[Decode.scala:50:77] assign uop_fp_ctrl_swap23 = cs_fp_swap23; // @[decode.scala:428:17, :447:16] assign uop_fp_ctrl_typeTagIn = cs_fp_typeTagIn; // @[decode.scala:428:17, :447:16] assign uop_fp_ctrl_typeTagOut = cs_fp_typeTagOut; // @[decode.scala:428:17, :447:16] wire cs_decoder_26; // @[Decode.scala:50:77] assign uop_fp_ctrl_fromint = cs_fp_fromint; // @[decode.scala:428:17, :447:16] wire cs_decoder_27; // @[Decode.scala:50:77] assign uop_fp_ctrl_toint = cs_fp_toint; // @[decode.scala:428:17, :447:16] wire cs_decoder_28; // @[Decode.scala:50:77] assign uop_fp_ctrl_fastpipe = cs_fp_fastpipe; // @[decode.scala:428:17, :447:16] wire cs_decoder_29; // @[Decode.scala:50:77] assign uop_fp_ctrl_fma = cs_fp_fma; // @[decode.scala:428:17, :447:16] wire cs_decoder_30; // @[Decode.scala:50:77] assign uop_fp_ctrl_div = cs_fp_div; // @[decode.scala:428:17, :447:16] wire cs_decoder_31; // @[Decode.scala:50:77] assign uop_fp_ctrl_sqrt = cs_fp_sqrt; // @[decode.scala:428:17, :447:16] wire cs_decoder_32; // @[Decode.scala:50:77] assign uop_fp_ctrl_wflags = cs_fp_wflags; // @[decode.scala:428:17, :447:16] wire cs_legal; // @[decode.scala:447:16] wire [9:0] cs_fu_code; // @[decode.scala:447:16] wire [1:0] cs_rs1_type; // @[decode.scala:447:16] wire [1:0] cs_rs2_type; // @[decode.scala:447:16] wire [2:0] cs_imm_sel; // @[decode.scala:447:16] wire cs_flush_on_commit; // @[decode.scala:447:16] wire [2:0] cs_csr_cmd; // @[decode.scala:447:16] wire [31:0] cs_decoder_decoded_invInputs = ~cs_decoder_decoded_plaInput; // @[pla.scala:77:22, :78:21] wire [56:0] cs_decoder_decoded_invMatrixOutputs; // @[pla.scala:120:37] wire [56:0] cs_decoder_decoded; // @[pla.scala:81:23] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_1 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_2 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_3 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_4 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_5 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_6 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_7 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_8 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_9 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_10 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_11 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_12 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_13 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_14 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_15 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_16 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_17 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_18 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_19 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_20 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_21 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_22 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_23 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_24 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_25 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_26 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_27 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_28 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_29 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_30 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_31 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_32 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_33 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_34 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_35 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_36 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_37 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_38 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_39 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_40 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_41 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_42 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_43 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_44 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_45 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_46 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_47 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_48 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_49 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_50 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_51 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_52 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_53 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_54 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_55 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_56 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_57 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_58 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_59 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_60 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_61 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_62 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_63 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_64 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_65 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_66 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_67 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_68 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_69 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_70 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_71 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_72 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_73 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_74 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_75 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_76 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_77 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_78 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_79 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_80 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_81 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_82 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_83 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_84 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_85 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_86 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_87 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_88 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_89 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_92 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_93 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_94 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_95 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_96 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_97 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_98 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_99 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_100 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_101 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_102 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_103 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_104 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_105 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_106 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_107 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_108 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_109 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_110 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_111 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_112 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_113 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_114 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_115 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_116 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_117 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_118 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_119 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_120 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_121 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_122 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_123 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_124 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_125 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_126 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_127 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_128 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_129 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_130 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_131 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_132 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_133 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_134 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_135 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_136 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_137 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_138 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_139 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_140 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_141 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_142 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_143 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_144 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_145 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_146 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_147 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_148 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_149 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_150 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_151 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_154 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_155 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_156 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_157 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_158 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_159 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_160 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_161 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_162 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_163 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_164 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_165 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_166 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_167 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_168 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_1 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_2 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_3 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_4 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_5 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_6 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_7 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_8 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_9 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_10 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_11 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_12 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_13 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_14 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_15 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_17 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_18 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_19 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_20 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_21 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_22 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_23 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_24 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_25 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_26 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_27 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_28 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_30 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_31 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_32 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_33 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_34 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_35 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_36 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_37 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_38 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_39 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_40 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_41 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_42 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_43 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_44 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_45 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_46 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_47 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_48 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_49 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_50 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_51 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_52 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_53 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_54 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_55 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_56 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_57 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_58 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_59 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_60 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_61 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_62 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_63 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_64 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_65 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_66 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_67 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_68 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_69 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_70 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_71 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_72 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_73 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_74 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_75 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_76 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_77 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_78 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_79 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_80 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_81 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_82 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_83 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_84 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_85 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_86 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_89 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_92 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_93 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_94 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_95 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_96 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_97 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_98 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_99 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_100 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_101 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_102 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_103 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_104 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_105 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_106 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_107 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_108 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_109 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_110 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_111 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_112 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_113 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_114 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_115 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_116 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_117 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_118 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_119 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_120 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_121 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_122 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_123 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_124 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_125 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_126 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_127 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_128 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_129 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_130 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_131 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_132 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_133 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_134 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_135 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_136 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_137 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_138 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_139 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_140 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_141 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_142 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_143 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_144 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_145 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_146 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_147 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_148 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_149 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_150 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_151 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_154 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_155 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_156 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_157 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_158 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_159 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_160 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_161 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_162 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_163 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_164 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_165 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_166 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_167 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_168 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_1 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_2 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_3 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_6 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_7 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_9 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_10 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_11 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_12 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_13 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_14 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_15 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_21 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_22 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_23 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_24 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_25 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_30 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_31 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_32 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_33 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_34 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_35 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_36 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_41 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_42 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_46 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_47 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_48 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_49 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_50 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_51 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_52 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_53 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_54 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_55 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_56 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_57 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_58 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_59 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_60 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_61 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_62 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_63 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_64 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_65 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_66 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_67 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_68 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_70 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_71 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_72 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_73 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_74 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_75 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_76 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_77 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_78 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_79 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_81 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_82 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_83 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_84 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_89 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_92 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_93 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_94 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_95 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_96 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_98 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_99 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_100 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_101 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_103 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_104 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_105 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_106 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_107 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_108 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_109 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_110 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_111 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_112 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_113 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_114 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_115 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_117 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_118 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_119 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_120 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_121 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_122 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_123 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_124 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_125 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_126 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_127 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_128 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_129 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_130 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_131 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_132 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_133 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_134 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_135 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_136 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_137 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_138 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_139 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_140 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_141 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_142 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_143 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_144 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_145 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_146 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_147 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_148 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_149 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_150 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_151 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_154 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_156 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_157 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_158 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_159 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_160 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_161 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_162 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_163 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_164 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_165 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_166 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_167 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_168 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_1 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_2 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_3 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_6 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_8 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_9 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_10 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_12 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_14 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_21 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_22 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_23 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_24 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_25 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_26 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_27 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_30 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_31 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_32 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_35 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_36 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_37 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_38 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_39 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_40 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_41 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_42 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_43 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_44 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_46 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_47 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_48 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_49 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_50 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_51 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_52 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_53 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_54 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_55 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_56 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_57 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_60 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_61 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_62 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_63 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_64 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_65 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_66 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_67 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_70 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_71 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_72 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_73 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_78 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_82 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_83 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_84 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_89 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_92 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_93 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_94 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_95 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_96 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_98 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_99 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_100 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_101 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_105 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_106 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_107 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_108 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_109 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_110 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_111 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_112 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_113 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_114 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_117 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_118 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_119 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_120 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_121 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_126 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_127 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_128 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_129 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_130 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_131 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_132 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_133 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_134 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_135 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_136 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_137 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_138 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_139 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_142 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_144 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_147 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_149 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_151 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_154 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_156 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_157 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_158 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_159 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_160 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_161 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_162 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_163 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_164 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_165 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_166 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_167 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_168 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_1 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_2 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_4 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_5 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_6 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_7 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_17 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_18 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_19 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_20 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_20 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_21 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_22 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_31 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_33 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_38 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_39 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_40 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_41 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_49 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_51 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_61 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_65 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_69 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_69 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_77 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_78 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_95 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_97 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_98 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_99 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_100 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_104 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_105 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_106 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_107 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_108 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_109 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_112 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_118 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_119 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_120 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_122 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_128 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_129 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_130 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_131 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_132 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_133 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_136 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_137 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_138 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_140 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_141 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_141 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_143 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_143 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_145 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_148 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_150 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_155 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_156 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_157 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_158 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_159 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_160 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_161 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_162 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_163 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_164 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_165 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_166 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_167 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_1 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_2 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_3 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_4 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_5 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_6 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_7 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_8 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_8 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_9 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_11 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_11 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_13 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_13 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_14 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_30 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_29 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_32 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_31 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_37 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_37 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_38 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_37 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_38 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_39 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_42 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_41 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_42 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_43 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_44 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_45 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_47 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_48 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_49 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_50 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_51 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_52 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_56 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_57 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_58 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_57 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_59 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_60 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_63 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_64 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_67 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_68 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_69 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_70 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_73 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_74 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_75 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_74 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_76 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_77 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_78 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_79 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_80 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_81 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_82 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_83 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_94 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_99 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_102 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_103 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_106 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_107 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_108 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_109 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_110 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_111 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_114 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_113 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_114 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_115 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_116 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_117 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_118 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_121 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_120 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_123 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_124 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_123 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_124 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_125 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_130 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_131 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_132 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_133 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_136 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_139 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_140 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_139 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_142 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_141 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_144 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_145 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_144 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_147 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_146 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_149 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_148 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_152 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_3 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_4 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_7 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_7 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_10 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_12 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_12 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_13 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_23 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_20 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_12 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_8 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_37 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_43 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_45 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_65 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_67 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_71 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_77 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_52 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_45 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_87 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_68 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_48 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_55 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_51 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_88 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_91 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_100 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_101 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_95 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_104 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_112 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_108 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_118 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_149 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_130 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_108 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_146 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_153 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_155 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_156 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_158 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo = {cs_decoder_decoded_andMatrixOutputs_lo_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi = {cs_decoder_decoded_andMatrixOutputs_hi_hi, cs_decoder_decoded_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53] wire [6:0] _cs_decoder_decoded_andMatrixOutputs_T = {cs_decoder_decoded_andMatrixOutputs_hi, cs_decoder_decoded_andMatrixOutputs_lo}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_81_2 = &_cs_decoder_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_1 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_2 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_3 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_4 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_5 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_9 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_17 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_18 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_19 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_20 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_24 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_25 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_26 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_27 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_28 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_37 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_38 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_39 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_40 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_43 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_44 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_45 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_56 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_64 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_69 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_80 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_85 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_86 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_97 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_102 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_116 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_155 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_1}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_1 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_lo_lo}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_1}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_1}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_1 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_hi_lo_1}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_1 = {cs_decoder_decoded_andMatrixOutputs_hi_1, cs_decoder_decoded_andMatrixOutputs_lo_1}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_85_2 = &_cs_decoder_decoded_andMatrixOutputs_T_1; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_1 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_2 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_1 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_5 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_3 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_8 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_10 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_8 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_9 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_17 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_18 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_19 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_15 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_10 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_7 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_23 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_19 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_25 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_21 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_27 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_48 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_49 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_50 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_59 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_54 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_56 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_58 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_73 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_64 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_49 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_42 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_80 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_55 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_45 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_53 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_48 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_89 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_90 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_96 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_97 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_98 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_86 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_87 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_88 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_89 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_90 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_91 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_105 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_96 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_97 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_98 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_112 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_100 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_114 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_115 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_103 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_110 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_111 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_112 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_113 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_119 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_133 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_121 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_135 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_136 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_124 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_138 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_126 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_140 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_128 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_142 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_117 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_104 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_147 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_140 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_154 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_142 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_143 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_157 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_145 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_1}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_2}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_2 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_2}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_2}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_2 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_hi_lo_2}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_2 = {cs_decoder_decoded_andMatrixOutputs_hi_2, cs_decoder_decoded_andMatrixOutputs_lo_2}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_10_2 = &_cs_decoder_decoded_andMatrixOutputs_T_2; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_3 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_2 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_6 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_4 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_6 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_6 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_7 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_13 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_14 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_11 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_9 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_6 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_34 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_29 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_30 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_22 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_23 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_34 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_24 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_25 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_28 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_58 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_46 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_41 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_43 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_57 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_63 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_51 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_47 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_36 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_67 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_52 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_39 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_50 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_42 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_74 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_75 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_76 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_77 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_78 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_79 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_82 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_83 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_84 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_85 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_73 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_74 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_75 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_76 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_92 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_93 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_98 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_100 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_106 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_120 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_108 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_122 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_125 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_129 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_114 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_94 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_132 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_133 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_134 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_127 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_141 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_129 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_130 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_144 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_132 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_3}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_3 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_3}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_3}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_3}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_3 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_hi_lo_3}; // @[pla.scala:98:53] wire [6:0] _cs_decoder_decoded_andMatrixOutputs_T_3 = {cs_decoder_decoded_andMatrixOutputs_hi_3, cs_decoder_decoded_andMatrixOutputs_lo_3}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_26_2 = &_cs_decoder_decoded_andMatrixOutputs_T_3; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_4 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_5 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_8 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_19 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_27 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_28 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_39 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_40 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_44 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_45 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_80 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_85 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_86 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_97 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_102 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_116 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_155 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_4 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_5 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_15 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_20 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_28 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_33 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_34 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_45 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_58 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_59 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_77 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_79 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_80 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_81 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_85 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_86 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_97 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_102 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_116 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_122 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_123 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_124 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_150 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_155 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_4}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_4 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_4}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_4}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_4 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_4}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_4 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_4, cs_decoder_decoded_andMatrixOutputs_hi_lo_4}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_4 = {cs_decoder_decoded_andMatrixOutputs_hi_4, cs_decoder_decoded_andMatrixOutputs_lo_4}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_100_2 = &_cs_decoder_decoded_andMatrixOutputs_T_4; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_5}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_3}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_5 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_5}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_5 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_5}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_5 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_hi_lo_5}; // @[pla.scala:98:53] wire [9:0] _cs_decoder_decoded_andMatrixOutputs_T_5 = {cs_decoder_decoded_andMatrixOutputs_hi_5, cs_decoder_decoded_andMatrixOutputs_lo_5}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_88_2 = &_cs_decoder_decoded_andMatrixOutputs_T_5; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_6 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_7 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_8 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_10 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_11 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_12 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_13 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_14 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_15 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_21 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_22 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_23 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_29 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_30 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_31 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_32 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_33 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_34 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_36 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_41 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_42 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_46 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_47 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_48 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_49 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_50 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_51 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_52 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_53 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_54 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_55 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_57 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_58 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_59 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_60 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_61 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_62 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_63 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_65 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_66 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_67 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_68 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_70 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_71 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_72 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_73 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_74 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_75 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_76 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_77 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_78 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_79 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_81 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_82 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_83 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_84 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_88 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_89 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_91 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_92 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_93 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_94 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_95 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_96 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_98 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_99 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_100 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_101 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_103 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_104 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_105 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_106 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_107 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_108 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_109 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_110 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_111 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_112 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_113 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_114 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_115 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_117 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_118 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_119 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_120 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_121 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_122 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_123 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_124 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_125 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_126 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_127 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_128 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_129 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_130 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_131 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_132 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_133 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_134 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_135 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_136 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_137 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_138 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_139 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_140 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_141 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_142 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_143 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_144 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_145 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_146 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_147 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_148 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_149 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_150 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_151 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_153 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_154 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_156 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_157 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_158 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_159 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_160 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_161 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_162 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_163 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_164 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_165 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_166 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_167 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_168 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_4}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_6 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_lo_lo_4}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_6}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_6}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_6 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_hi_lo_6}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_6 = {cs_decoder_decoded_andMatrixOutputs_hi_6, cs_decoder_decoded_andMatrixOutputs_lo_6}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_62_2 = &_cs_decoder_decoded_andMatrixOutputs_T_6; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_2}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_7}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_7 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_lo_lo_5}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_7}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_7 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_7}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_7 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_hi_lo_7}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_7 = {cs_decoder_decoded_andMatrixOutputs_hi_7, cs_decoder_decoded_andMatrixOutputs_lo_7}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_77_2 = &_cs_decoder_decoded_andMatrixOutputs_T_7; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_8 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_8}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_8}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_8 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_8}; // @[pla.scala:90:45, :98:53] wire [5:0] _cs_decoder_decoded_andMatrixOutputs_T_8 = {cs_decoder_decoded_andMatrixOutputs_hi_8, cs_decoder_decoded_andMatrixOutputs_lo_8}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_29_2 = &_cs_decoder_decoded_andMatrixOutputs_T_8; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_9 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_10 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_11 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_12 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_13 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_14 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_15 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_23 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_24 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_26 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_26 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_27 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_29 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_29 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_35 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_35 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_43 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_43 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_44 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_45 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_46 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_47 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_48 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_50 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_52 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_53 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_54 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_55 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_59 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_60 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_62 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_63 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_64 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_66 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_68 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_70 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_71 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_72 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_74 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_75 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_76 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_76 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_79 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_80 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_81 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_82 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_83 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_84 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_85 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_88 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_88 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_91 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_91 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_92 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_93 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_94 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_96 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_101 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_103 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_104 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_110 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_111 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_113 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_115 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_115 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_116 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_117 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_125 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_125 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_126 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_127 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_134 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_135 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_146 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_146 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_148 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_153 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_153 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_154 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_6}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_9 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_9, cs_decoder_decoded_andMatrixOutputs_lo_lo_6}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_9}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_9}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_9 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_hi_lo_8}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_9 = {cs_decoder_decoded_andMatrixOutputs_hi_9, cs_decoder_decoded_andMatrixOutputs_lo_9}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_110_2 = &_cs_decoder_decoded_andMatrixOutputs_T_9; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_1 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_2 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_11 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_5 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_1 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_2 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_20 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_17 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_19 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_27 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_21 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_32 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_24 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_27 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_28 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_38 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_10 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_4 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_4 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_5 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_7 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_8 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_8 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_80 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_81 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_72 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_73 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_27 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_78 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_79 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_94 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_82 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_86 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_84 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_88 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_89 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_87 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_91 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_89 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_83 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_84 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_99 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_97 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_100 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_101 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_102 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_92 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_93 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_84 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_95 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_123 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_111 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_112 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_114 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_1 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_9 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_4 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_7 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_5 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_17 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_16 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_17 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_14 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_15 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_16 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_1 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_2 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_18 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_15 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_16 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_15 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_17 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_20 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_19 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_22 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_23 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_22 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_34 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_26 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_25 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_26 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_29 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_30 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_32 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_30 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_66 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_47 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_35 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_36 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_37 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_51 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_39 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_40 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_36 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_68 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_40 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_4 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_46 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_44 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_45 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_4 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_4 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_3 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_7 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_7 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_5 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_52 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_41 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_15 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_86 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_62 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_63 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_64 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_65 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_67 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_68 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_66 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_67 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_68 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_72 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_70 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_71 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_70 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_71 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_17 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_75 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_76 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_81 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_79 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_80 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_81 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_82 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_83 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_82 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_85 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_86 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_85 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_88 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_87 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_79 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_80 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_81 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_82 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_97 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_95 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_96 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_95 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_91 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_88 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_98 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_99 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_100 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_82 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_83 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_51 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_85 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_110 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_108 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_109 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_110 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_111 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_33 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_14 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_10 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_7 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_120 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_121 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_111 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_120 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_121 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_120 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_123 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_65 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_103 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_67 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_40 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_69 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_70 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_1 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_5 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_3 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_5 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_11 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_1 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_1 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_14 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_13 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_14 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_14 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_18 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_15 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_18 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_17 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_20 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_21 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_20 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_25 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_24 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_23 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_24 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_27 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_28 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_29 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_28 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_32 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_33 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_38 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_36 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_37 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_41 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_33 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_3 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_4 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_3 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_7 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_7 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_5 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_49 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_22 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_12 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_59 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_60 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_62 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_66 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_64 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_65 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_64 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_65 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_73 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_74 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_80 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_78 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_77 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_78 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_80 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_81 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_77 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_83 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_84 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_86 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_82 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_69 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_70 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_71 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_72 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_93 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_94 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_95 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_49 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_50 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_31 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_52 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_107 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_106 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_107 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_108 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_109 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_119 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_117 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_118 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_107 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_118 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_119 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_114 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_121 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_37 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_66 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_39 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_31 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_41 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_42 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_1 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_3 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_3 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_4 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_5 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_12 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_1 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_1 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_12 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_12 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_13 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_12 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_16 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_13 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_16 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_15 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_18 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_19 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_18 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_23 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_22 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_21 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_22 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_25 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_26 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_27 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_26 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_30 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_31 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_34 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_35 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_34 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_35 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_32 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_42 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_35 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_3 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_41 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_39 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_40 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_57 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_58 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_61 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_60 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_63 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_62 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_63 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_60 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_61 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_66 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_67 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_64 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_65 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_62 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_63 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_13 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_69 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_70 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_77 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_76 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_72 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_73 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_79 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_75 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_76 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_73 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_78 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_79 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_80 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_81 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_78 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_37 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_38 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_39 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_40 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_92 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_88 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_89 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_86 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_89 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_90 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_91 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_29 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_30 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_22 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_32 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_105 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_101 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_102 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_103 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_104 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_21 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_116 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_115 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_116 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_113 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_38 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_30 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_32 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_1 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_2 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_3 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_4 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_4 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_10 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_9 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_10 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_1 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_28 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_11 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_10 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_11 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_11 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_14 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_14 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_16 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_17 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_21 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_20 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_20 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_21 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_23 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_24 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_25 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_25 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_34 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_27 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_28 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_32 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_33 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_31 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_32 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_26 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_39 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_33 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_41 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_3 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_38 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_36 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_37 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_32 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_6 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_6 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_7 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_29_2 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_40 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_11 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_11 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_57 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_56 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_65 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_66 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_71 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_68 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_74 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_71 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_74 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_76 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_77 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_68 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_19 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_20 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_21 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_22 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_87 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_84 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_85 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_76 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_44 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_25 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_112 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_109 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_110 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_111 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_1 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_2 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_2 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_3 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_7 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_7 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_8 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_30 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_8 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_7 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_8 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_4 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_10 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_11 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_5 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_13 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_16 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_14 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_18 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_15 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_16 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_6 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_18 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_19 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_20 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_7 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_29 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_22 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_23 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_28 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_29 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_24 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_25 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_3 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_34 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_9 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_36 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_3 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_29 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_11 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_12 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_5 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_4 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_3 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_2 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_30_1 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_6 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_4 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_31 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_13 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_10 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_10 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_52 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_49 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_52 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_43 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_44 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_45 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_48 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_49 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_50 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_24 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_25 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_16 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_11 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_28 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_29 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_57 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_30 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_59 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_60 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_31 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_62 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_32 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_33 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_65 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_34 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_35 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_18 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_14 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_15 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_73 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_41 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_42 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_23 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_18 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_16 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_26 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_27 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_28 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_13 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_14 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_12 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_16 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_86 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_53 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_54 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_55 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_56 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_12 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_9 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_6 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_31_1 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_7 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_1}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_10 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_10 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_10, cs_decoder_decoded_andMatrixOutputs_lo_lo_7}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_7}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_10}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_9 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_10}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_10}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_10 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_10 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_hi_lo_9}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_10 = {cs_decoder_decoded_andMatrixOutputs_hi_10, cs_decoder_decoded_andMatrixOutputs_lo_10}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_61_2 = &_cs_decoder_decoded_andMatrixOutputs_T_10; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_1}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_8 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_1}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_1}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_2}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_11 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_1}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_11 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_11, cs_decoder_decoded_andMatrixOutputs_lo_lo_8}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_8}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_10 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_11}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_11 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_4, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_1}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_11 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_11, cs_decoder_decoded_andMatrixOutputs_hi_lo_10}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_11 = {cs_decoder_decoded_andMatrixOutputs_hi_11, cs_decoder_decoded_andMatrixOutputs_lo_11}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_166_2 = &_cs_decoder_decoded_andMatrixOutputs_T_11; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_2 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_2 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_4 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_3 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_8 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_8 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_9 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_29 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_9 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_9 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_10 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_9 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_12 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_13 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_12 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_15 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_17 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_19 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_19 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_17 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_22 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_23 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_24 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_21 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_31 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_26 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_27 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_29 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_30 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_30 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_31 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_8 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_37 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_27 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_39 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_3 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_35 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_30 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_31 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_13 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_4 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_3 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_2 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_29_1 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_6 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_4 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_30_2 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_21 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_11 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_10 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_55 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_53 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_50 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_51 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_56 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_53 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_54 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_55 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_46 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_47 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_58 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_59 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_51 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_26 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_11 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_105 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_106 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_2}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_9 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_2}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_5}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_12 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_3}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_12 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_12, cs_decoder_decoded_andMatrixOutputs_lo_lo_9}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_12}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_11 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_11}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_12}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_12}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_12 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_12 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_12, cs_decoder_decoded_andMatrixOutputs_hi_lo_11}; // @[pla.scala:98:53] wire [12:0] _cs_decoder_decoded_andMatrixOutputs_T_12 = {cs_decoder_decoded_andMatrixOutputs_hi_12, cs_decoder_decoded_andMatrixOutputs_lo_12}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_8_2 = &_cs_decoder_decoded_andMatrixOutputs_T_12; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_2}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_10 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_2}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_3}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_4}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_13 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_4, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_13 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_13, cs_decoder_decoded_andMatrixOutputs_lo_lo_10}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_10}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_12 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_3, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_13}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_13 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_3}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_13 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_13, cs_decoder_decoded_andMatrixOutputs_hi_lo_12}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_13 = {cs_decoder_decoded_andMatrixOutputs_hi_13, cs_decoder_decoded_andMatrixOutputs_lo_13}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_80_2 = &_cs_decoder_decoded_andMatrixOutputs_T_13; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_4}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_11 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_3}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_4}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_7}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_14 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_3}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_14 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_14, cs_decoder_decoded_andMatrixOutputs_lo_lo_11}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_14}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_13 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_13}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_14}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_14}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_14 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_4}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_14 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_hi_lo_13}; // @[pla.scala:98:53] wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_14 = {cs_decoder_decoded_andMatrixOutputs_hi_14, cs_decoder_decoded_andMatrixOutputs_lo_14}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_14_2 = &_cs_decoder_decoded_andMatrixOutputs_T_14; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_4}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_12 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_5}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_6}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_15 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_4}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_15 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_15, cs_decoder_decoded_andMatrixOutputs_lo_lo_12}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_12}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_15}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_14 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_15}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_15 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_5}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_15 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_hi_lo_14}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_15 = {cs_decoder_decoded_andMatrixOutputs_hi_15, cs_decoder_decoded_andMatrixOutputs_lo_15}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_56_2 = &_cs_decoder_decoded_andMatrixOutputs_T_15; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_16 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_17 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_18 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_18 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_19 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_18 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_19 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_20 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_21 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_22 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_25 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_24 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_25 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_29 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_27 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_34 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_33 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_46 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_53 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_58 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_61 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_62 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_69 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_67 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_75 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_87 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_88 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_86 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_90 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_91 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_89 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_90 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_91 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_92 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_93 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_95 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_96 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_97 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_98 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_102 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_103 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_104 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_105 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_126 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_127 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_128 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_129 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_134 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_135 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_152 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_153 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_151 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_153 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_154 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_155 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_156 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_157 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_158 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_159 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_160 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_161 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_162 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_163 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_164 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_165 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_16 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_29 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_22 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_87 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_88 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_79 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_90 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_91 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_82 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_83 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_84 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_85 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_152 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_153 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_144 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_16 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_28 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_17 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_87 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_87 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_66 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_90 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_91 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_69 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_70 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_71 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_72 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_152 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_153 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_131 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_16 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_26 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_13 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_87 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_85 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_53 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_90 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_90 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_56 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_57 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_58 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_59 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_152 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_152 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_118 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_16 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_21 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_11 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_86 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_78 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_50 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_90 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_88 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_53 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_56 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_152 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_150 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_115 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_15 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_16 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_10 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_84 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_65 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_48 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_89 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_81 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_51 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_54 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_151 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_143 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_113 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_6 = cs_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_7 = cs_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_3 = cs_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_48 = cs_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_44 = cs_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_17 = cs_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_54 = cs_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_50 = cs_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_20 = cs_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_116 = cs_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_112 = cs_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_60 = cs_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_6 = cs_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_6 = cs_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_2 = cs_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_46 = cs_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_41 = cs_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_9 = cs_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_51 = cs_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_47 = cs_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_12 = cs_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_113 = cs_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_107 = cs_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_36 = cs_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_6 = cs_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_5 = cs_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_2 = cs_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_43 = cs_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_35 = cs_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_7 = cs_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_49 = cs_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_44 = cs_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_10 = cs_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_111 = cs_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_103 = cs_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_27 = cs_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_5 = cs_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_2 = cs_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_2 = cs_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_40 = cs_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_16 = cs_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_7 = cs_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_46 = cs_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_38 = cs_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_10 = cs_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_106 = cs_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_93 = cs_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_24 = cs_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_4 = cs_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_1 = cs_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_2 = cs_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_34 = cs_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_8 = cs_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_6 = cs_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_43 = cs_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_19 = cs_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_9 = cs_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_102 = cs_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_59 = cs_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_20 = cs_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_1 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_1 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_2 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_40 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_62 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_47 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_18 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_9 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_9 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_106 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_107 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_108 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_109 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_114 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_115 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_129 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_138 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_103 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_109 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_110 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_135 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_122 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_125 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_124 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_125 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_128 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_127 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_1 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_2 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_37 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_49 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_45 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_5 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_5 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_5 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_93 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_94 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_95 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_96 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_101 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_102 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_130 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_131 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_104 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_103 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_106 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_105 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_34 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_23 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_11 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_122 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_149 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_150 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_151 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_152 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_116 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_123 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_118 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_119 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_126 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_121 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_1 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_2 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_34 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_46 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_42 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_5 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_5 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_5 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_8 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_8 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_8 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_64 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_90 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_91 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_92 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_93 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_98 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_99 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_116 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_117 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_118 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_101 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_102 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_98 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_104 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_25 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_19 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_11 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_119 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_136 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_137 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_138 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_139 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_112 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_117 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_114 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_115 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_120 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_117 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_1 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_2 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_28 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_44 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_39 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_4 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_5 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_5 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_8 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_8 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_8 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_54 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_88 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_89 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_90 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_91 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_96 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_97 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_103 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_104 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_105 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_96 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_97 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_94 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_99 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_117 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_123 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_124 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_125 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_126 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_102 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_113 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_104 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_105 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_116 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_107 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_6 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_13 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_5 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_4}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_7 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_16 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_5}; // @[pla.scala:98:53] wire [12:0] cs_decoder_decoded_andMatrixOutputs_lo_16 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_16, cs_decoder_decoded_andMatrixOutputs_lo_lo_13}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_6}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_4 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_6}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_9}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_6 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_7}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_15 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_4}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_16}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_6 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_15}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_16}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_16}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_9 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_16 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_6}; // @[pla.scala:98:53] wire [12:0] cs_decoder_decoded_andMatrixOutputs_hi_16 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_16, cs_decoder_decoded_andMatrixOutputs_hi_lo_15}; // @[pla.scala:98:53] wire [25:0] _cs_decoder_decoded_andMatrixOutputs_T_16 = {cs_decoder_decoded_andMatrixOutputs_hi_16, cs_decoder_decoded_andMatrixOutputs_lo_16}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_43_2 = &_cs_decoder_decoded_andMatrixOutputs_T_16; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_17}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_17}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_17 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_17}; // @[pla.scala:91:29, :98:53] wire [4:0] _cs_decoder_decoded_andMatrixOutputs_T_17 = {cs_decoder_decoded_andMatrixOutputs_hi_17, cs_decoder_decoded_andMatrixOutputs_lo_17}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_157_2 = &_cs_decoder_decoded_andMatrixOutputs_T_17; // @[pla.scala:98:{53,70}] wire _cs_decoder_decoded_orMatrixOutputs_T_17 = cs_decoder_decoded_andMatrixOutputs_157_2; // @[pla.scala:98:70, :114:36] wire _cs_decoder_decoded_orMatrixOutputs_T_63 = cs_decoder_decoded_andMatrixOutputs_157_2; // @[pla.scala:98:70, :114:36] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_18}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_18 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_17}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_18}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_18 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_18}; // @[pla.scala:91:29, :98:53] wire [5:0] _cs_decoder_decoded_andMatrixOutputs_T_18 = {cs_decoder_decoded_andMatrixOutputs_hi_18, cs_decoder_decoded_andMatrixOutputs_lo_18}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_123_2 = &_cs_decoder_decoded_andMatrixOutputs_T_18; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_18}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_19 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_16}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_19}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_19 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_19, cs_decoder_decoded_andMatrixOutputs_hi_lo_16}; // @[pla.scala:98:53] wire [6:0] _cs_decoder_decoded_andMatrixOutputs_T_19 = {cs_decoder_decoded_andMatrixOutputs_hi_19, cs_decoder_decoded_andMatrixOutputs_lo_19}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_102_2 = &_cs_decoder_decoded_andMatrixOutputs_T_19; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_20 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_17}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_20}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_20}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_20 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_20, cs_decoder_decoded_andMatrixOutputs_hi_lo_17}; // @[pla.scala:98:53] wire [6:0] _cs_decoder_decoded_andMatrixOutputs_T_20 = {cs_decoder_decoded_andMatrixOutputs_hi_20, cs_decoder_decoded_andMatrixOutputs_lo_20}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_140_2 = &_cs_decoder_decoded_andMatrixOutputs_T_20; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_7}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_20 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_10}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_21 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_20, cs_decoder_decoded_andMatrixOutputs_lo_lo_14}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_18 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_20}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_21}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_21 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_21}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_21 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_21, cs_decoder_decoded_andMatrixOutputs_hi_lo_18}; // @[pla.scala:98:53] wire [10:0] _cs_decoder_decoded_andMatrixOutputs_T_21 = {cs_decoder_decoded_andMatrixOutputs_hi_21, cs_decoder_decoded_andMatrixOutputs_lo_21}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_21_2 = &_cs_decoder_decoded_andMatrixOutputs_T_21; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_8}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_15 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_7}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_21 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_11}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_22 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_21, cs_decoder_decoded_andMatrixOutputs_lo_lo_15}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_19 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_21}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_22}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_22 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_22}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_22 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_22, cs_decoder_decoded_andMatrixOutputs_hi_lo_19}; // @[pla.scala:98:53] wire [11:0] _cs_decoder_decoded_andMatrixOutputs_T_22 = {cs_decoder_decoded_andMatrixOutputs_hi_22, cs_decoder_decoded_andMatrixOutputs_lo_22}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_145_2 = &_cs_decoder_decoded_andMatrixOutputs_T_22; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_9}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_16 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_8}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_22 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_12}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_23 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_22, cs_decoder_decoded_andMatrixOutputs_lo_lo_16}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_20 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_22}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_23}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_23 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_23}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_23 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_23, cs_decoder_decoded_andMatrixOutputs_hi_lo_20}; // @[pla.scala:98:53] wire [11:0] _cs_decoder_decoded_andMatrixOutputs_T_23 = {cs_decoder_decoded_andMatrixOutputs_hi_23, cs_decoder_decoded_andMatrixOutputs_lo_23}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_161_2 = &_cs_decoder_decoded_andMatrixOutputs_T_23; // @[pla.scala:98:{53,70}] wire _cs_decoder_decoded_orMatrixOutputs_T_16 = cs_decoder_decoded_andMatrixOutputs_161_2; // @[pla.scala:98:70, :114:36] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_17}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_24 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_23, cs_decoder_decoded_andMatrixOutputs_lo_lo_17}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_24}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_24}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_24 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_24, cs_decoder_decoded_andMatrixOutputs_hi_lo_21}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_24 = {cs_decoder_decoded_andMatrixOutputs_hi_24, cs_decoder_decoded_andMatrixOutputs_lo_24}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_79_2 = &_cs_decoder_decoded_andMatrixOutputs_T_24; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_13}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_22}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_25 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_24, cs_decoder_decoded_andMatrixOutputs_lo_lo_18}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_25}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_25}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_25 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_25}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_25 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_25, cs_decoder_decoded_andMatrixOutputs_hi_lo_22}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_25 = {cs_decoder_decoded_andMatrixOutputs_hi_25, cs_decoder_decoded_andMatrixOutputs_lo_25}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_33_2 = &_cs_decoder_decoded_andMatrixOutputs_T_25; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_14}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_26 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_25, cs_decoder_decoded_andMatrixOutputs_lo_lo_19}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_26}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_26 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_26}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_26 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_26, cs_decoder_decoded_andMatrixOutputs_hi_lo_23}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_26 = {cs_decoder_decoded_andMatrixOutputs_hi_26, cs_decoder_decoded_andMatrixOutputs_lo_26}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_112_2 = &_cs_decoder_decoded_andMatrixOutputs_T_26; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_11}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_24}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_26 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_20}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_27 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_26, cs_decoder_decoded_andMatrixOutputs_lo_lo_20}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_27}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_27}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_27 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_27}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_27 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_27, cs_decoder_decoded_andMatrixOutputs_hi_lo_24}; // @[pla.scala:98:53] wire [9:0] _cs_decoder_decoded_andMatrixOutputs_T_27 = {cs_decoder_decoded_andMatrixOutputs_hi_27, cs_decoder_decoded_andMatrixOutputs_lo_27}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_168_2 = &_cs_decoder_decoded_andMatrixOutputs_T_27; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_27}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_28 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_25}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_28}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_28}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_28 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_28, cs_decoder_decoded_andMatrixOutputs_hi_lo_25}; // @[pla.scala:98:53] wire [6:0] _cs_decoder_decoded_andMatrixOutputs_T_28 = {cs_decoder_decoded_andMatrixOutputs_hi_28, cs_decoder_decoded_andMatrixOutputs_lo_28}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_138_2 = &_cs_decoder_decoded_andMatrixOutputs_T_28; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_2 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_1}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_1}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_9 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_21 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_9, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_1}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_6 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_1}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_1}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_2}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_12 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_1}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_28 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_12, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_6}; // @[pla.scala:98:53] wire [13:0] cs_decoder_decoded_andMatrixOutputs_lo_29 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_28, cs_decoder_decoded_andMatrixOutputs_lo_lo_21}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_7}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_5 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_6}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_10}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_16}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_10 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_26 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_10, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_5}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_28}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_7 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_26}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_29}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_29}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_16 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_1}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_29 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_16, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_7}; // @[pla.scala:98:53] wire [13:0] cs_decoder_decoded_andMatrixOutputs_hi_29 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_29, cs_decoder_decoded_andMatrixOutputs_hi_lo_26}; // @[pla.scala:98:53] wire [27:0] _cs_decoder_decoded_andMatrixOutputs_T_29 = {cs_decoder_decoded_andMatrixOutputs_hi_29, cs_decoder_decoded_andMatrixOutputs_lo_29}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_47_2 = &_cs_decoder_decoded_andMatrixOutputs_T_29; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_29}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_3 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_30}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_1}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_2}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_10 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_1}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_22 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_10, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_2}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_2}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_7 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_2}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_2}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_13 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_2}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_29 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_13, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_7}; // @[pla.scala:98:53] wire [14:0] cs_decoder_decoded_andMatrixOutputs_lo_30 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_29, cs_decoder_decoded_andMatrixOutputs_lo_lo_22}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_3}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_7}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_6 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_10}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_13}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_11 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_1}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_27 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_11, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_6}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_29}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_8 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_30}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_30}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_17 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_2}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_30 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_17, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_8}; // @[pla.scala:98:53] wire [15:0] cs_decoder_decoded_andMatrixOutputs_hi_30 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_30, cs_decoder_decoded_andMatrixOutputs_hi_lo_27}; // @[pla.scala:98:53] wire [30:0] _cs_decoder_decoded_andMatrixOutputs_T_30 = {cs_decoder_decoded_andMatrixOutputs_hi_30, cs_decoder_decoded_andMatrixOutputs_lo_30}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_71_2 = &_cs_decoder_decoded_andMatrixOutputs_T_30; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_28 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_24 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_30 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_26 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_32 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_28 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_41 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_42 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_54 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_55 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_56 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_51 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_52 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_57 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_61 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_72 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_69 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_74 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_99 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_100 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_101 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_102 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_103 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_109 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_110 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_111 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_119 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_113 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_121 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_122 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_116 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_123 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_124 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_125 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_126 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_132 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_140 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_134 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_142 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_143 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_137 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_145 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_139 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_147 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_141 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_9}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_23 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_8}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_12}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_18}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_30 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_8}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_31 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_30, cs_decoder_decoded_andMatrixOutputs_lo_lo_23}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_28 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_28}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_31}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_31}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_31 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_18, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_9}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_31 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_31, cs_decoder_decoded_andMatrixOutputs_hi_lo_28}; // @[pla.scala:98:53] wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_31 = {cs_decoder_decoded_andMatrixOutputs_hi_31, cs_decoder_decoded_andMatrixOutputs_lo_31}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_105_2 = &_cs_decoder_decoded_andMatrixOutputs_T_31; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_9}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_24 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_7}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_12}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_15}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_31 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_9}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_32 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_31, cs_decoder_decoded_andMatrixOutputs_lo_lo_24}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_24}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_29 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_13, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_7}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_32}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_32}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_32 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_19, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_10}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_32 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_32, cs_decoder_decoded_andMatrixOutputs_hi_lo_29}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_32 = {cs_decoder_decoded_andMatrixOutputs_hi_32, cs_decoder_decoded_andMatrixOutputs_lo_32}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_52_2 = &_cs_decoder_decoded_andMatrixOutputs_T_32; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_10}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_25 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_8}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_13}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_16}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_32 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_16, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_10}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_33 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_32, cs_decoder_decoded_andMatrixOutputs_lo_lo_25}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_32}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_30 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_14, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_8}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_33}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_33 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_20, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_11}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_33 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_33, cs_decoder_decoded_andMatrixOutputs_hi_lo_30}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_33 = {cs_decoder_decoded_andMatrixOutputs_hi_33, cs_decoder_decoded_andMatrixOutputs_lo_33}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_86_2 = &_cs_decoder_decoded_andMatrixOutputs_T_33; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_4}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_11}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_26 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_14, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_4}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_14}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_17}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_33 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_17, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_11}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_34 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_33, cs_decoder_decoded_andMatrixOutputs_lo_lo_26}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_34, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_31 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_15, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_9}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_34, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_34, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_34}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_34 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_21, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_12}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_34 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_34, cs_decoder_decoded_andMatrixOutputs_hi_lo_31}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_34 = {cs_decoder_decoded_andMatrixOutputs_hi_34, cs_decoder_decoded_andMatrixOutputs_lo_34}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_0_2 = &_cs_decoder_decoded_andMatrixOutputs_T_34; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_27}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_34 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_34}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_35 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_34, cs_decoder_decoded_andMatrixOutputs_lo_lo_27}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_35}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_35 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_35}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_35 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_35, cs_decoder_decoded_andMatrixOutputs_hi_lo_32}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_35 = {cs_decoder_decoded_andMatrixOutputs_hi_35, cs_decoder_decoded_andMatrixOutputs_lo_35}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_76_2 = &_cs_decoder_decoded_andMatrixOutputs_T_35; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_28}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_35 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_35}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_36 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_35, cs_decoder_decoded_andMatrixOutputs_lo_lo_28}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_36}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_36}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_36 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_36, cs_decoder_decoded_andMatrixOutputs_hi_lo_33}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_36 = {cs_decoder_decoded_andMatrixOutputs_hi_36, cs_decoder_decoded_andMatrixOutputs_lo_36}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_160_2 = &_cs_decoder_decoded_andMatrixOutputs_T_36; // @[pla.scala:98:{53,70}] wire _cs_decoder_decoded_orMatrixOutputs_T_34 = cs_decoder_decoded_andMatrixOutputs_160_2; // @[pla.scala:98:70, :114:36] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_36 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_35 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_36 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_31 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_32 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_33 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_40 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_35 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_36 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_26 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_38 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_39 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_40 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_29 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_30 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_53 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_54 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_55 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_56 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_44 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_62 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_73 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_70 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_76 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_87 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_92 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_93 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_106 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_117 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_105 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_145 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_37 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_34}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_34 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_37}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_37 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_37}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_37 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_37, cs_decoder_decoded_andMatrixOutputs_hi_lo_34}; // @[pla.scala:98:53] wire [6:0] _cs_decoder_decoded_andMatrixOutputs_T_37 = {cs_decoder_decoded_andMatrixOutputs_hi_37, cs_decoder_decoded_andMatrixOutputs_lo_37}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_120_2 = &_cs_decoder_decoded_andMatrixOutputs_T_37; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_37 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_37}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_38 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_37, cs_decoder_decoded_andMatrixOutputs_lo_lo_29}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_35 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_38}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_38 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_38}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_38 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_38, cs_decoder_decoded_andMatrixOutputs_hi_lo_35}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_38 = {cs_decoder_decoded_andMatrixOutputs_hi_38, cs_decoder_decoded_andMatrixOutputs_lo_38}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_45_2 = &_cs_decoder_decoded_andMatrixOutputs_T_38; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_38 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_38}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_39 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_38, cs_decoder_decoded_andMatrixOutputs_lo_lo_30}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_39}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_39}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_39 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_39, cs_decoder_decoded_andMatrixOutputs_hi_lo_36}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_39 = {cs_decoder_decoded_andMatrixOutputs_hi_39, cs_decoder_decoded_andMatrixOutputs_lo_39}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_162_2 = &_cs_decoder_decoded_andMatrixOutputs_T_39; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_37}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_40 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_39, cs_decoder_decoded_andMatrixOutputs_lo_lo_31}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_37 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_40}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_40}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_40 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_40}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_40 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_40, cs_decoder_decoded_andMatrixOutputs_hi_lo_37}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_40 = {cs_decoder_decoded_andMatrixOutputs_hi_40, cs_decoder_decoded_andMatrixOutputs_lo_40}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_73_2 = &_cs_decoder_decoded_andMatrixOutputs_T_40; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_32}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_40}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_41 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_40, cs_decoder_decoded_andMatrixOutputs_lo_lo_32}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_38 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_41}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_41 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_41}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_41 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_41, cs_decoder_decoded_andMatrixOutputs_hi_lo_38}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_41 = {cs_decoder_decoded_andMatrixOutputs_hi_41, cs_decoder_decoded_andMatrixOutputs_lo_41}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_18_2 = &_cs_decoder_decoded_andMatrixOutputs_T_41; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_41 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_39}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_42 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_41, cs_decoder_decoded_andMatrixOutputs_lo_lo_33}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_42, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_42, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_42}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_42 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_42}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_42 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_42, cs_decoder_decoded_andMatrixOutputs_hi_lo_39}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_42 = {cs_decoder_decoded_andMatrixOutputs_hi_42, cs_decoder_decoded_andMatrixOutputs_lo_42}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_111_2 = &_cs_decoder_decoded_andMatrixOutputs_T_42; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_34 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_42 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_43 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_42, cs_decoder_decoded_andMatrixOutputs_lo_lo_34}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_43}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_43 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_43}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_43 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_43, cs_decoder_decoded_andMatrixOutputs_hi_lo_40}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_43 = {cs_decoder_decoded_andMatrixOutputs_hi_43, cs_decoder_decoded_andMatrixOutputs_lo_43}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_153_2 = &_cs_decoder_decoded_andMatrixOutputs_T_43; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_35 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_24}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_43 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_41}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_44 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_43, cs_decoder_decoded_andMatrixOutputs_lo_lo_35}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_41 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_44, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_44}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_44, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_44}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_44 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_44}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_44 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_44, cs_decoder_decoded_andMatrixOutputs_hi_lo_41}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_44 = {cs_decoder_decoded_andMatrixOutputs_hi_44, cs_decoder_decoded_andMatrixOutputs_lo_44}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_107_2 = &_cs_decoder_decoded_andMatrixOutputs_T_44; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_16}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_42, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_44 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_25}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_45 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_44, cs_decoder_decoded_andMatrixOutputs_lo_lo_36}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_45}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_42 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_44}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_45}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_45 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_45}; // @[pla.scala:90:45, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_45 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_45, cs_decoder_decoded_andMatrixOutputs_hi_lo_42}; // @[pla.scala:98:53] wire [10:0] _cs_decoder_decoded_andMatrixOutputs_T_45 = {cs_decoder_decoded_andMatrixOutputs_hi_45, cs_decoder_decoded_andMatrixOutputs_lo_45}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_17_2 = &_cs_decoder_decoded_andMatrixOutputs_T_45; // @[pla.scala:98:{53,70}] wire _cs_decoder_decoded_orMatrixOutputs_T_49 = cs_decoder_decoded_andMatrixOutputs_17_2; // @[pla.scala:98:70, :114:36] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_12}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_37 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_10}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_15}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_45 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_19, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_12}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_46 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_45, cs_decoder_decoded_andMatrixOutputs_lo_lo_37}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_37}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_46, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_45}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_43 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_17, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_10}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_46, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_46}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_46, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_46}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_46 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_26, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_13}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_46 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_46, cs_decoder_decoded_andMatrixOutputs_hi_lo_43}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_46 = {cs_decoder_decoded_andMatrixOutputs_hi_46, cs_decoder_decoded_andMatrixOutputs_lo_46}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_167_2 = &_cs_decoder_decoded_andMatrixOutputs_T_46; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_13}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_38 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_11}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_16}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_20}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_46 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_20, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_13}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_47 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_46, cs_decoder_decoded_andMatrixOutputs_lo_lo_38}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_44, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_46}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_44 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_18, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_11}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_47}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_47}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_47 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_27, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_14}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_47 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_47, cs_decoder_decoded_andMatrixOutputs_hi_lo_44}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_47 = {cs_decoder_decoded_andMatrixOutputs_hi_47, cs_decoder_decoded_andMatrixOutputs_lo_47}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_113_2 = &_cs_decoder_decoded_andMatrixOutputs_T_47; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_5}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_14}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_39 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_17, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_5}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_17}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_21}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_47 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_21, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_14}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_48 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_47, cs_decoder_decoded_andMatrixOutputs_lo_lo_39}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_39}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_47}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_45 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_19, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_12}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_48}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_48}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_48 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_28, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_15}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_48 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_48, cs_decoder_decoded_andMatrixOutputs_hi_lo_45}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_48 = {cs_decoder_decoded_andMatrixOutputs_hi_48, cs_decoder_decoded_andMatrixOutputs_lo_48}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_42_2 = &_cs_decoder_decoded_andMatrixOutputs_T_48; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_46, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_40}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_48 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_49, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_48}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_49 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_48, cs_decoder_decoded_andMatrixOutputs_lo_lo_40}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_46 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_49, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_49}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_49 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_49, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_49}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_49 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_49, cs_decoder_decoded_andMatrixOutputs_hi_lo_46}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_49 = {cs_decoder_decoded_andMatrixOutputs_hi_49, cs_decoder_decoded_andMatrixOutputs_lo_49}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_131_2 = &_cs_decoder_decoded_andMatrixOutputs_T_49; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_41 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_29}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_49 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_49, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_47}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_50 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_49, cs_decoder_decoded_andMatrixOutputs_lo_lo_41}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_47 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_50, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_50}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_50, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_50}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_50 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_50}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_50 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_50, cs_decoder_decoded_andMatrixOutputs_hi_lo_47}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_50 = {cs_decoder_decoded_andMatrixOutputs_hi_50, cs_decoder_decoded_andMatrixOutputs_lo_50}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_1_2 = &_cs_decoder_decoded_andMatrixOutputs_T_50; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_15}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_42 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_13}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_18}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_50 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_22, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_15}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_51 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_50, cs_decoder_decoded_andMatrixOutputs_lo_lo_42}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_51, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_50}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_48 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_20, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_13}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_51, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_51}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_51, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_51}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_51 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_30, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_16}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_51 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_51, cs_decoder_decoded_andMatrixOutputs_hi_lo_48}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_51 = {cs_decoder_decoded_andMatrixOutputs_hi_51, cs_decoder_decoded_andMatrixOutputs_lo_51}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_136_2 = &_cs_decoder_decoded_andMatrixOutputs_T_51; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_31 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_44 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_33 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_46 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_47 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_35 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_36 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_37 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_38 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_39 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_40 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_41 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_42 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_43 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_31 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_63 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_71 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_65 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_66 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_45 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_72 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_60 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_61 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_94 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_77 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_107 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_95 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_83 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_84 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_85 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_99 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_87 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_101 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_102 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_90 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_104 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_92 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_113 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_127 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_115 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_43 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_51 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_51, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_49}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_52 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_51, cs_decoder_decoded_andMatrixOutputs_lo_lo_43}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_49 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_52}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_52}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_52 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_52}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_52 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_52, cs_decoder_decoded_andMatrixOutputs_hi_lo_49}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_52 = {cs_decoder_decoded_andMatrixOutputs_hi_52, cs_decoder_decoded_andMatrixOutputs_lo_52}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_39_2 = &_cs_decoder_decoded_andMatrixOutputs_T_52; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_17}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_44 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_16}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_21}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_44, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_32}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_52 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_23, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_16}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_53 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_52, cs_decoder_decoded_andMatrixOutputs_lo_lo_44}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_53, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_52}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_50 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_50}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_53, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_53}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_53, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_53}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_53 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_32, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_17}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_53 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_53, cs_decoder_decoded_andMatrixOutputs_hi_lo_50}; // @[pla.scala:98:53] wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_53 = {cs_decoder_decoded_andMatrixOutputs_hi_53, cs_decoder_decoded_andMatrixOutputs_lo_53}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_108_2 = &_cs_decoder_decoded_andMatrixOutputs_T_53; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_17}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_45 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_14}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_20}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_24}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_53 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_24, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_17}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_54 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_53, cs_decoder_decoded_andMatrixOutputs_lo_lo_45}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_51, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_45}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_54, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_53}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_51 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_22, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_14}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_54, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_54}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_54, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_54}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_54 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_33, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_18}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_54 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_54, cs_decoder_decoded_andMatrixOutputs_hi_lo_51}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_54 = {cs_decoder_decoded_andMatrixOutputs_hi_54, cs_decoder_decoded_andMatrixOutputs_lo_54}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_165_2 = &_cs_decoder_decoded_andMatrixOutputs_T_54; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_19}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_46 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_18}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_23}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_46, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_54 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_25, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_18}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_55 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_54, cs_decoder_decoded_andMatrixOutputs_lo_lo_46}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_54}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_52 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_52}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_55}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_34 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_55}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_55 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_34, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_19}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_55 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_55, cs_decoder_decoded_andMatrixOutputs_hi_lo_52}; // @[pla.scala:98:53] wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_55 = {cs_decoder_decoded_andMatrixOutputs_hi_55, cs_decoder_decoded_andMatrixOutputs_lo_55}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_127_2 = &_cs_decoder_decoded_andMatrixOutputs_T_55; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_47 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_53, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_47}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_55 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_55}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_56 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_55, cs_decoder_decoded_andMatrixOutputs_lo_lo_47}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_53 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_56}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_56 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_56}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_56 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_56, cs_decoder_decoded_andMatrixOutputs_hi_lo_53}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_56 = {cs_decoder_decoded_andMatrixOutputs_hi_56, cs_decoder_decoded_andMatrixOutputs_lo_56}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_135_2 = &_cs_decoder_decoded_andMatrixOutputs_T_56; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_19}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_48 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_15}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_22}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_56 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_26, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_19}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_57 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_56, cs_decoder_decoded_andMatrixOutputs_lo_lo_48}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_54, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_48}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_54 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_24, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_15}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_57}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_35 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_57}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_57 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_35, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_20}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_57 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_57, cs_decoder_decoded_andMatrixOutputs_hi_lo_54}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_57 = {cs_decoder_decoded_andMatrixOutputs_hi_57, cs_decoder_decoded_andMatrixOutputs_lo_57}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_114_2 = &_cs_decoder_decoded_andMatrixOutputs_T_57; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_20}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_49 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_16}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_23}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_27}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_57 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_27, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_20}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_58 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_57, cs_decoder_decoded_andMatrixOutputs_lo_lo_49}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_49}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_57}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_55 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_25, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_16}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_58}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_58 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_36, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_21}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_58 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_58, cs_decoder_decoded_andMatrixOutputs_hi_lo_55}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_58 = {cs_decoder_decoded_andMatrixOutputs_hi_58, cs_decoder_decoded_andMatrixOutputs_lo_58}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_155_2 = &_cs_decoder_decoded_andMatrixOutputs_T_58; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_6}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_21}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_50 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_24, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_6}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_24}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_58 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_28, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_21}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_59 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_58, cs_decoder_decoded_andMatrixOutputs_lo_lo_50}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_50}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_59, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_56 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_26, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_17}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_59, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_59}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_37 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_59, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_59}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_59 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_37, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_22}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_59 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_59, cs_decoder_decoded_andMatrixOutputs_hi_lo_56}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_59 = {cs_decoder_decoded_andMatrixOutputs_hi_59, cs_decoder_decoded_andMatrixOutputs_lo_59}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_6_2 = &_cs_decoder_decoded_andMatrixOutputs_T_59; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_22}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_51 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_18}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_25}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_59 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_29, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_22}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_60 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_59, cs_decoder_decoded_andMatrixOutputs_lo_lo_51}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_51}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_59}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_57 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_27, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_18}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_60}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_38 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_60}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_60 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_38, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_23}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_60 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_60, cs_decoder_decoded_andMatrixOutputs_hi_lo_57}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_60 = {cs_decoder_decoded_andMatrixOutputs_hi_60, cs_decoder_decoded_andMatrixOutputs_lo_60}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_75_2 = &_cs_decoder_decoded_andMatrixOutputs_T_60; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_52 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_39}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_60 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_58}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_61 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_60, cs_decoder_decoded_andMatrixOutputs_lo_lo_52}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_58 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_61}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_61}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_61 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_61}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_61 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_61, cs_decoder_decoded_andMatrixOutputs_hi_lo_58}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_61 = {cs_decoder_decoded_andMatrixOutputs_hi_61, cs_decoder_decoded_andMatrixOutputs_lo_61}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_72_2 = &_cs_decoder_decoded_andMatrixOutputs_T_61; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_53 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_53, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_40}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_61 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_59}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_62 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_61, cs_decoder_decoded_andMatrixOutputs_lo_lo_53}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_59 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_62, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_62}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_62, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_62}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_62 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_62}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_62 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_62, cs_decoder_decoded_andMatrixOutputs_hi_lo_59}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_62 = {cs_decoder_decoded_andMatrixOutputs_hi_62, cs_decoder_decoded_andMatrixOutputs_lo_62}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_96_2 = &_cs_decoder_decoded_andMatrixOutputs_T_62; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_23}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_54 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_19}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_26}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_62 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_30, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_23}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_63 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_62, cs_decoder_decoded_andMatrixOutputs_lo_lo_54}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_54}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_62}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_60 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_28, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_19}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_63}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_41 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_63}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_63 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_41, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_24}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_63 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_63, cs_decoder_decoded_andMatrixOutputs_hi_lo_60}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_63 = {cs_decoder_decoded_andMatrixOutputs_hi_63, cs_decoder_decoded_andMatrixOutputs_lo_63}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_149_2 = &_cs_decoder_decoded_andMatrixOutputs_T_63; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_55 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_42}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_63 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_61}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_64 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_63, cs_decoder_decoded_andMatrixOutputs_lo_lo_55}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_61 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_64}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_42 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_64}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_64 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_42, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_64}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_64 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_64, cs_decoder_decoded_andMatrixOutputs_hi_lo_61}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_64 = {cs_decoder_decoded_andMatrixOutputs_hi_64, cs_decoder_decoded_andMatrixOutputs_lo_64}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_144_2 = &_cs_decoder_decoded_andMatrixOutputs_T_64; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_56 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_43}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_64 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_62}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_65 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_64, cs_decoder_decoded_andMatrixOutputs_lo_lo_56}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_62 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_65, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_43 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_65, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_65}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_65 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_65}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_65 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_65, cs_decoder_decoded_andMatrixOutputs_hi_lo_62}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_65 = {cs_decoder_decoded_andMatrixOutputs_hi_65, cs_decoder_decoded_andMatrixOutputs_lo_65}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_3_2 = &_cs_decoder_decoded_andMatrixOutputs_T_65; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_57 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_44, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_31}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_65, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_63}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_65 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_57}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_66 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_65, cs_decoder_decoded_andMatrixOutputs_lo_lo_57}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_63 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_66}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_44 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_66}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_66 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_44, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_66}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_66 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_66, cs_decoder_decoded_andMatrixOutputs_hi_lo_63}; // @[pla.scala:98:53] wire [9:0] _cs_decoder_decoded_andMatrixOutputs_T_66 = {cs_decoder_decoded_andMatrixOutputs_hi_66, cs_decoder_decoded_andMatrixOutputs_lo_66}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_13_2 = &_cs_decoder_decoded_andMatrixOutputs_T_66; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_45 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_33 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_68 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_60 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_48 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_49 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_50 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_64 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_52 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_53 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_59 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_47 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_48 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_54 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_47 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_23 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_69 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_70 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_71 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_85 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_86 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_92 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_57 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_18 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_14 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_11 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_122 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_68 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_106 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_24}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_58 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_20}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_27}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_32}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_66 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_32, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_24}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_67 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_66, cs_decoder_decoded_andMatrixOutputs_lo_lo_58}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_58}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_67, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_66}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_64 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_29, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_20}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_67, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_67}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_45 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_67, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_67}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_67 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_45, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_25}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_67 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_67, cs_decoder_decoded_andMatrixOutputs_hi_lo_64}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_67 = {cs_decoder_decoded_andMatrixOutputs_hi_67, cs_decoder_decoded_andMatrixOutputs_lo_67}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_141_2 = &_cs_decoder_decoded_andMatrixOutputs_T_67; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_7}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_25}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_59 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_28, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_7}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_28}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_46, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_67 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_33, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_25}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_68 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_67, cs_decoder_decoded_andMatrixOutputs_lo_lo_59}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_65, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_59}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_68, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_67}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_65 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_30, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_21}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_68, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_68}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_46 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_68, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_68}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_68 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_46, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_26}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_68 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_68, cs_decoder_decoded_andMatrixOutputs_hi_lo_65}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_68 = {cs_decoder_decoded_andMatrixOutputs_hi_68, cs_decoder_decoded_andMatrixOutputs_lo_68}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_93_2 = &_cs_decoder_decoded_andMatrixOutputs_T_68; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_68 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_69, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_68}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_69 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_68, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_66}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_66 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_69, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_69}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_69 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_69, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_69}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_69 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_69, cs_decoder_decoded_andMatrixOutputs_hi_lo_66}; // @[pla.scala:98:53] wire [6:0] _cs_decoder_decoded_andMatrixOutputs_T_69 = {cs_decoder_decoded_andMatrixOutputs_hi_69, cs_decoder_decoded_andMatrixOutputs_lo_69}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_60_2 = &_cs_decoder_decoded_andMatrixOutputs_T_69; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_34, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_31}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_60 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_29}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_34 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_67, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_60}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_69 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_34, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_47}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_70 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_69, cs_decoder_decoded_andMatrixOutputs_lo_lo_60}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_70, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_70}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_67 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_69}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_47 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_70, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_70}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_70 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_70}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_70 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_70, cs_decoder_decoded_andMatrixOutputs_hi_lo_67}; // @[pla.scala:98:53] wire [11:0] _cs_decoder_decoded_andMatrixOutputs_T_70 = {cs_decoder_decoded_andMatrixOutputs_hi_70, cs_decoder_decoded_andMatrixOutputs_lo_70}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_69_2 = &_cs_decoder_decoded_andMatrixOutputs_T_70; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_26}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_61 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_22}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_30}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_35 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_70 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_35, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_26}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_71 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_70, cs_decoder_decoded_andMatrixOutputs_lo_lo_61}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_68, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_61}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_70}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_68 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_32, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_22}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_71}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_48 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_71}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_71 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_48, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_27}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_71 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_71, cs_decoder_decoded_andMatrixOutputs_hi_lo_68}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_71 = {cs_decoder_decoded_andMatrixOutputs_hi_71, cs_decoder_decoded_andMatrixOutputs_lo_71}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_124_2 = &_cs_decoder_decoded_andMatrixOutputs_T_71; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_27}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_62 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_23}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_31}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_49, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_71 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_36, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_27}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_72 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_71, cs_decoder_decoded_andMatrixOutputs_lo_lo_62}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_69, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_62}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_71}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_69 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_33, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_23}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_72}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_49 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_72}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_72 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_49, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_28}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_72 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_72, cs_decoder_decoded_andMatrixOutputs_hi_lo_69}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_72 = {cs_decoder_decoded_andMatrixOutputs_hi_72, cs_decoder_decoded_andMatrixOutputs_lo_72}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_30_2 = &_cs_decoder_decoded_andMatrixOutputs_T_72; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_29}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_63 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_28}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_34}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_37 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_50}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_72 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_37, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_28}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_73 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_72, cs_decoder_decoded_andMatrixOutputs_lo_lo_63}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_34 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_73, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_72}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_70 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_34, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_70}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_73, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_73}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_50 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_73, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_73}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_73 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_50, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_29}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_73 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_73, cs_decoder_decoded_andMatrixOutputs_hi_lo_70}; // @[pla.scala:98:53] wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_73 = {cs_decoder_decoded_andMatrixOutputs_hi_73, cs_decoder_decoded_andMatrixOutputs_lo_73}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_35_2 = &_cs_decoder_decoded_andMatrixOutputs_T_73; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_30}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_64 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_29}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_35}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_38 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_51}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_73 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_38, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_29}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_74 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_73, cs_decoder_decoded_andMatrixOutputs_lo_lo_64}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_35 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_74, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_73}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_71 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_71}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_74, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_74}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_51 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_74, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_74}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_74 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_51, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_30}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_74 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_74, cs_decoder_decoded_andMatrixOutputs_hi_lo_71}; // @[pla.scala:98:53] wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_74 = {cs_decoder_decoded_andMatrixOutputs_hi_74, cs_decoder_decoded_andMatrixOutputs_lo_74}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_9_2 = &_cs_decoder_decoded_andMatrixOutputs_T_74; // @[pla.scala:98:{53,70}] wire _cs_decoder_decoded_orMatrixOutputs_T_84 = cs_decoder_decoded_andMatrixOutputs_9_2; // @[pla.scala:98:70, :114:36] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_34 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_30}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_65 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_34, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_24}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_34}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_39}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_74 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_39, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_30}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_75 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_74, cs_decoder_decoded_andMatrixOutputs_lo_lo_65}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_65}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_74}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_72 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_36, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_24}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_75}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_52 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_75}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_75 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_52, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_31}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_75 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_75, cs_decoder_decoded_andMatrixOutputs_hi_lo_72}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_75 = {cs_decoder_decoded_andMatrixOutputs_hi_75, cs_decoder_decoded_andMatrixOutputs_lo_75}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_89_2 = &_cs_decoder_decoded_andMatrixOutputs_T_75; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_35 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_31}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_66 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_25}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_35}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_53, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_40}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_75 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_40, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_31}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_76 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_75, cs_decoder_decoded_andMatrixOutputs_lo_lo_66}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_73, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_66}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_37 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_75}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_73 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_37, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_25}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_76}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_53 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_76}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_76 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_53, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_32}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_76 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_76, cs_decoder_decoded_andMatrixOutputs_hi_lo_73}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_76 = {cs_decoder_decoded_andMatrixOutputs_hi_76, cs_decoder_decoded_andMatrixOutputs_lo_76}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_57_2 = &_cs_decoder_decoded_andMatrixOutputs_T_76; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_33 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_55 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_38 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_44 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_3 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_43 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_42 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_43 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_73 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_61 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_69 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_68 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_69 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_66 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_67 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_13 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_94 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_93 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_94 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_90 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_87 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_78 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_24 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_13 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_10 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_7 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_3}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_26}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_67 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_36, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_8}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_41 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_38}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_76 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_41, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_32}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_77 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_76, cs_decoder_decoded_andMatrixOutputs_lo_lo_67}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_67, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_54}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_38 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_74}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_74 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_38, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_26}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_77}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_77}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_54 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_77}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_77 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_54, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_33}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_77 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_77, cs_decoder_decoded_andMatrixOutputs_hi_lo_74}; // @[pla.scala:98:53] wire [16:0] _cs_decoder_decoded_andMatrixOutputs_T_77 = {cs_decoder_decoded_andMatrixOutputs_hi_77, cs_decoder_decoded_andMatrixOutputs_lo_77}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_164_2 = &_cs_decoder_decoded_andMatrixOutputs_T_77; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_37 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_37}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_68 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_34}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_42 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_68, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_55}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_77 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_42, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_42}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_78 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_77, cs_decoder_decoded_andMatrixOutputs_lo_lo_68}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_77}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_75 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_75}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_34 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_78}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_55 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_78}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_78 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_55, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_34}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_78 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_78, cs_decoder_decoded_andMatrixOutputs_hi_lo_75}; // @[pla.scala:98:53] wire [12:0] _cs_decoder_decoded_andMatrixOutputs_T_78 = {cs_decoder_decoded_andMatrixOutputs_hi_78, cs_decoder_decoded_andMatrixOutputs_lo_78}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_121_2 = &_cs_decoder_decoded_andMatrixOutputs_T_78; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_9}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_38 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_33}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_69 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_38, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_9}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_43 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_43}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_78 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_43, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_33}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_79 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_78, cs_decoder_decoded_andMatrixOutputs_lo_lo_69}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_69}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_79, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_78}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_76 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_40, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_27}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_35 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_79, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_79}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_56 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_79, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_79}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_79 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_56, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_35}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_79 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_79, cs_decoder_decoded_andMatrixOutputs_hi_lo_76}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_79 = {cs_decoder_decoded_andMatrixOutputs_hi_79, cs_decoder_decoded_andMatrixOutputs_lo_79}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_25_2 = &_cs_decoder_decoded_andMatrixOutputs_T_79; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_39}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_70 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_36}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_44 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_70, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_57}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_79 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_44, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_44}; // @[pla.scala:90:45, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_80 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_79, cs_decoder_decoded_andMatrixOutputs_lo_lo_70}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_41 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_79}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_77 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_77}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_80}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_57 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_80}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_80 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_57, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_36}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_80 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_80, cs_decoder_decoded_andMatrixOutputs_hi_lo_77}; // @[pla.scala:98:53] wire [12:0] _cs_decoder_decoded_andMatrixOutputs_T_80 = {cs_decoder_decoded_andMatrixOutputs_hi_80, cs_decoder_decoded_andMatrixOutputs_lo_80}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_99_2 = &_cs_decoder_decoded_andMatrixOutputs_T_80; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_42 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_75 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_50 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_15 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_6 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_6 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_121 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_122 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_127 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_128 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_137 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_107 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_105 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_112 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_92 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_35 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_16 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_148 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_124 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_128 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_126 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_127 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_131 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_129 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_3}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_3}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_40 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_3}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_71 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_40, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_10}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_10}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_34 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_4}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_37}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_45 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_34}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_80 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_45, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_34}; // @[pla.scala:98:53] wire [10:0] cs_decoder_decoded_andMatrixOutputs_lo_81 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_80, cs_decoder_decoded_andMatrixOutputs_lo_lo_71}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_71}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_42 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_58}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_78 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_42, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_28}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_81}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_37 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_80}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_81}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_58 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_81}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_81 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_58, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_37}; // @[pla.scala:98:53] wire [10:0] cs_decoder_decoded_andMatrixOutputs_hi_81 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_81, cs_decoder_decoded_andMatrixOutputs_hi_lo_78}; // @[pla.scala:98:53] wire [21:0] _cs_decoder_decoded_andMatrixOutputs_T_81 = {cs_decoder_decoded_andMatrixOutputs_hi_81, cs_decoder_decoded_andMatrixOutputs_lo_81}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_51_2 = &_cs_decoder_decoded_andMatrixOutputs_T_81; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_41 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_35}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_72 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_29}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_35 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_41}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_46 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_59, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_46}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_81 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_46, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_35}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_82 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_81, cs_decoder_decoded_andMatrixOutputs_lo_lo_72}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_79, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_72}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_43 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_82, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_81}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_79 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_43, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_29}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_38 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_82, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_82}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_59 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_82, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_82}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_82 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_59, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_38}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_82 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_82, cs_decoder_decoded_andMatrixOutputs_hi_lo_79}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_82 = {cs_decoder_decoded_andMatrixOutputs_hi_82, cs_decoder_decoded_andMatrixOutputs_lo_82}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_37_2 = &_cs_decoder_decoded_andMatrixOutputs_T_82; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_11}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_42 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_36}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_73 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_42, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_11}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_44, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_47 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_47}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_82 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_47, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_36}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_83 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_82, cs_decoder_decoded_andMatrixOutputs_lo_lo_73}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_73}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_44 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_82}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_80 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_44, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_30}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_83}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_60 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_83}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_83 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_60, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_39}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_83 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_83, cs_decoder_decoded_andMatrixOutputs_hi_lo_80}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_83 = {cs_decoder_decoded_andMatrixOutputs_hi_83, cs_decoder_decoded_andMatrixOutputs_lo_83}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_143_2 = &_cs_decoder_decoded_andMatrixOutputs_T_83; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_12}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_43 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_37}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_74 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_43, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_12}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_37 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_43}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_48 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_48}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_83 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_48, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_37}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_84 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_83, cs_decoder_decoded_andMatrixOutputs_lo_lo_74}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_74}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_45 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_83}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_81 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_45, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_31}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_84}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_61 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_84}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_84 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_61, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_40}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_84 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_84, cs_decoder_decoded_andMatrixOutputs_hi_lo_81}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_84 = {cs_decoder_decoded_andMatrixOutputs_hi_84, cs_decoder_decoded_andMatrixOutputs_lo_84}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_137_2 = &_cs_decoder_decoded_andMatrixOutputs_T_84; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_38 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_14 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_3 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_4 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_28_1 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_6 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_7 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_28_2 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_46 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_14 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_12 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_60 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_58 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_77 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_45 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_9 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_10 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_28_3 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_115 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_33 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_5}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_44 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_32}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_75 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_44, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_13}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_38 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_44, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_41}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_49 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_49, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_46}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_84 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_49, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_38}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_85 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_84, cs_decoder_decoded_andMatrixOutputs_lo_lo_75}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_62}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_46 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_82}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_82 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_46, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_32}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_41 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_85, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_85}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_85, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_85}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_62 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_85}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_85 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_62, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_41}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_85 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_85, cs_decoder_decoded_andMatrixOutputs_hi_lo_82}; // @[pla.scala:98:53] wire [16:0] _cs_decoder_decoded_andMatrixOutputs_T_85 = {cs_decoder_decoded_andMatrixOutputs_hi_85, cs_decoder_decoded_andMatrixOutputs_lo_85}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_118_2 = &_cs_decoder_decoded_andMatrixOutputs_T_85; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_4}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_45 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_76 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_45, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_14}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_33}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_45}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_50 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_42}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_85 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_50, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_39}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_lo_86 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_85, cs_decoder_decoded_andMatrixOutputs_lo_lo_76}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_50}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_85, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_83}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_47 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_76}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_83 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_47, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_33}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_42 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_86, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_86}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_86, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_86}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_63 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_86}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_86 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_63, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_42}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_hi_86 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_86, cs_decoder_decoded_andMatrixOutputs_hi_lo_83}; // @[pla.scala:98:53] wire [18:0] _cs_decoder_decoded_andMatrixOutputs_T_86 = {cs_decoder_decoded_andMatrixOutputs_hi_86, cs_decoder_decoded_andMatrixOutputs_lo_86}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_58_2 = &_cs_decoder_decoded_andMatrixOutputs_T_86; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_7 = cs_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_6 = cs_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_6 = cs_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_72 = cs_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_58 = cs_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_26 = cs_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_15 = cs_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_3}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_15 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_3}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_4}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_46 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_3}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_77 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_46, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_15}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_5}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_40 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_4}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_34}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_51 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_3}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_86 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_51, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_40}; // @[pla.scala:98:53] wire [12:0] cs_decoder_decoded_andMatrixOutputs_lo_87 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_86, cs_decoder_decoded_andMatrixOutputs_lo_lo_77}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_46}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_34 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_43}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_64}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_48 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_51}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_84 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_48, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_34}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_87, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_86}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_43 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_84}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_87, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_87}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_87, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_87}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_64 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_3}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_87 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_64, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_43}; // @[pla.scala:98:53] wire [12:0] cs_decoder_decoded_andMatrixOutputs_hi_87 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_87, cs_decoder_decoded_andMatrixOutputs_hi_lo_84}; // @[pla.scala:98:53] wire [25:0] _cs_decoder_decoded_andMatrixOutputs_T_87 = {cs_decoder_decoded_andMatrixOutputs_hi_87, cs_decoder_decoded_andMatrixOutputs_lo_87}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_146_2 = &_cs_decoder_decoded_andMatrixOutputs_T_87; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_16 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_2}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_4}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_4}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_47 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_78 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_47, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_16}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_41 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_5}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_6}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_16}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_52 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_4}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_87 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_52, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_41}; // @[pla.scala:98:53] wire [13:0] cs_decoder_decoded_andMatrixOutputs_lo_88 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_87, cs_decoder_decoded_andMatrixOutputs_lo_lo_78}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_44}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_35 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_41}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_49}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_65}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_49 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_85 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_49, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_35}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_88, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_87}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_44 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_85}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_88, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_88}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_88, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_88}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_65 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_4}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_88 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_65, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_44}; // @[pla.scala:98:53] wire [13:0] cs_decoder_decoded_andMatrixOutputs_hi_88 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_88, cs_decoder_decoded_andMatrixOutputs_hi_lo_85}; // @[pla.scala:98:53] wire [27:0] _cs_decoder_decoded_andMatrixOutputs_T_88 = {cs_decoder_decoded_andMatrixOutputs_hi_88, cs_decoder_decoded_andMatrixOutputs_lo_88}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_50_2 = &_cs_decoder_decoded_andMatrixOutputs_T_88; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_28_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_29_1}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_17 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_30_1}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_3}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_5}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_48 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_3}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_79 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_48, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_17}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_5}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_42 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_6}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_7}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_53 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_5}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_88 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_53, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_42}; // @[pla.scala:98:53] wire [14:0] cs_decoder_decoded_andMatrixOutputs_lo_89 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_88, cs_decoder_decoded_andMatrixOutputs_lo_lo_79}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_17}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_42}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_36 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_50, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_48}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_53}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_50 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_3}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_86 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_50, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_36}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_86, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_79}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_89, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_88}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_45 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_89, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_89}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_89, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_89}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_66 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_5}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_89 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_66, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_45}; // @[pla.scala:98:53] wire [15:0] cs_decoder_decoded_andMatrixOutputs_hi_89 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_89, cs_decoder_decoded_andMatrixOutputs_hi_lo_86}; // @[pla.scala:98:53] wire [30:0] _cs_decoder_decoded_andMatrixOutputs_T_89 = {cs_decoder_decoded_andMatrixOutputs_hi_89, cs_decoder_decoded_andMatrixOutputs_lo_89}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_129_2 = &_cs_decoder_decoded_andMatrixOutputs_T_89; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_37 = cs_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_11 = cs_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_9 = cs_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_74 = cs_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_119 = cs_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_120 = cs_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_10 = cs_decoder_decoded_plaInput[22]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_9 = cs_decoder_decoded_plaInput[22]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_8 = cs_decoder_decoded_plaInput[22]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_68 = cs_decoder_decoded_plaInput[22]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_6}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_18 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_6}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_7}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_49 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_6}; // @[pla.scala:90:45, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_80 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_49, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_18}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_8}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_43 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_7}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_54 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_6}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_89 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_54, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_43}; // @[pla.scala:98:53] wire [12:0] cs_decoder_decoded_andMatrixOutputs_lo_90 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_89, cs_decoder_decoded_andMatrixOutputs_lo_lo_80}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_51, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_49}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_37 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_46}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_67}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_51 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_54}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_87 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_51, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_37}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_90, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_89}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_46 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_87}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_90, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_90}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_90, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_90}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_67 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_6}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_90 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_67, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_46}; // @[pla.scala:98:53] wire [12:0] cs_decoder_decoded_andMatrixOutputs_hi_90 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_90, cs_decoder_decoded_andMatrixOutputs_hi_lo_87}; // @[pla.scala:98:53] wire [25:0] _cs_decoder_decoded_andMatrixOutputs_T_90 = {cs_decoder_decoded_andMatrixOutputs_hi_90, cs_decoder_decoded_andMatrixOutputs_lo_90}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_66_2 = &_cs_decoder_decoded_andMatrixOutputs_T_90; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_4}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_19 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_4}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_7}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_50 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_4}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_81 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_50, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_19}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_44 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_8}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_19}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_55 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_7}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_90 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_55, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_44}; // @[pla.scala:98:53] wire [13:0] cs_decoder_decoded_andMatrixOutputs_lo_91 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_90, cs_decoder_decoded_andMatrixOutputs_lo_lo_81}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_50, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_47}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_38 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_44}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_52}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_68}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_52 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_4}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_88 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_52, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_38}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_90}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_47 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_88}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_91}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_91}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_68 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_11, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_7}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_91 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_68, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_47}; // @[pla.scala:98:53] wire [13:0] cs_decoder_decoded_andMatrixOutputs_hi_91 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_91, cs_decoder_decoded_andMatrixOutputs_hi_lo_88}; // @[pla.scala:98:53] wire [27:0] _cs_decoder_decoded_andMatrixOutputs_T_91 = {cs_decoder_decoded_andMatrixOutputs_hi_91, cs_decoder_decoded_andMatrixOutputs_lo_91}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_134_2 = &_cs_decoder_decoded_andMatrixOutputs_T_91; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_30_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_31}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_28_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_29_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_20 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_8, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_lo}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_5}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_8}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_51 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_5}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_82 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_51, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_20}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_45 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_9, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_9}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_10}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_56 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_8}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_91 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_56, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_45}; // @[pla.scala:98:53] wire [15:0] cs_decoder_decoded_andMatrixOutputs_lo_92 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_91, cs_decoder_decoded_andMatrixOutputs_lo_lo_82}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_20}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_45}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_39 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_8, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_53, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_51}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_69, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_56}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_53 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_5}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_89 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_53, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_39}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_89, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_82}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_92, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_91}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_48 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_9, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_92, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_92}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_92, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_92}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_69 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_12, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_8}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_92 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_69, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_48}; // @[pla.scala:98:53] wire [15:0] cs_decoder_decoded_andMatrixOutputs_hi_92 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_92, cs_decoder_decoded_andMatrixOutputs_hi_lo_89}; // @[pla.scala:98:53] wire [31:0] _cs_decoder_decoded_andMatrixOutputs_T_92 = {cs_decoder_decoded_andMatrixOutputs_hi_92, cs_decoder_decoded_andMatrixOutputs_lo_92}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_97_2 = &_cs_decoder_decoded_andMatrixOutputs_T_92; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_13}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_52 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_46, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_40}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_83 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_52, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_21}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_46 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_49}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_57 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_54}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_92 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_57, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_46}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_93 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_92, cs_decoder_decoded_andMatrixOutputs_lo_lo_83}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_70}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_54 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_92, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_90}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_90 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_54, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_40}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_49 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_93, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_93}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_93, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_93}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_70 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_93}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_93 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_70, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_49}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_93 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_93, cs_decoder_decoded_andMatrixOutputs_hi_lo_90}; // @[pla.scala:98:53] wire [16:0] _cs_decoder_decoded_andMatrixOutputs_T_93 = {cs_decoder_decoded_andMatrixOutputs_hi_93, cs_decoder_decoded_andMatrixOutputs_lo_93}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_65_2 = &_cs_decoder_decoded_andMatrixOutputs_T_93; // @[pla.scala:98:{53,70}] wire _cs_decoder_decoded_orMatrixOutputs_T_50 = cs_decoder_decoded_andMatrixOutputs_65_2; // @[pla.scala:98:70, :114:36] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_10}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_53 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_11}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_84 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_53, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_22}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_47 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_41}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_53}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_58 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_50}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_93 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_58, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_47}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_lo_94 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_93, cs_decoder_decoded_andMatrixOutputs_lo_lo_84}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_41 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_58}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_93, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_91}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_55 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_84}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_91 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_55, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_41}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_50 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_94, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_94}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_94, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_94}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_71 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_94}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_94 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_71, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_50}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_hi_94 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_94, cs_decoder_decoded_andMatrixOutputs_hi_lo_91}; // @[pla.scala:98:53] wire [19:0] _cs_decoder_decoded_andMatrixOutputs_T_94 = {cs_decoder_decoded_andMatrixOutputs_hi_94, cs_decoder_decoded_andMatrixOutputs_lo_94}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_16_2 = &_cs_decoder_decoded_andMatrixOutputs_T_94; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_10}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_54 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_11}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_85 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_54, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_23}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_42, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_48 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_15}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_54, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_51}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_59 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_48}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_94 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_59, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_48}; // @[pla.scala:98:53] wire [10:0] cs_decoder_decoded_andMatrixOutputs_lo_95 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_94, cs_decoder_decoded_andMatrixOutputs_lo_lo_85}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_42 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_59, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_56}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_92, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_85}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_56 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_72}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_92 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_56, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_42}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_95, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_95}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_51 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_94}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_95, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_95}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_72 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_95}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_95 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_72, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_51}; // @[pla.scala:98:53] wire [10:0] cs_decoder_decoded_andMatrixOutputs_hi_95 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_95, cs_decoder_decoded_andMatrixOutputs_hi_lo_92}; // @[pla.scala:98:53] wire [21:0] _cs_decoder_decoded_andMatrixOutputs_T_95 = {cs_decoder_decoded_andMatrixOutputs_hi_95, cs_decoder_decoded_andMatrixOutputs_lo_95}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_95_2 = &_cs_decoder_decoded_andMatrixOutputs_T_95; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_55 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_55}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_86 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_52}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_60 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_86, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_73}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_95 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_60}; // @[pla.scala:90:45, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_96 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_95, cs_decoder_decoded_andMatrixOutputs_lo_lo_86}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_57 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_96, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_95}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_93 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_93}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_52 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_96, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_96}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_73 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_96, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_96}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_96 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_73, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_52}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_96 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_96, cs_decoder_decoded_andMatrixOutputs_hi_lo_93}; // @[pla.scala:98:53] wire [12:0] _cs_decoder_decoded_andMatrixOutputs_T_96 = {cs_decoder_decoded_andMatrixOutputs_hi_96, cs_decoder_decoded_andMatrixOutputs_lo_96}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_82_2 = &_cs_decoder_decoded_andMatrixOutputs_T_96; // @[pla.scala:98:{53,70}] wire _cs_decoder_decoded_orMatrixOutputs_T_3 = cs_decoder_decoded_andMatrixOutputs_82_2; // @[pla.scala:98:70, :114:36] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_56 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_53}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_87 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_49}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_49 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_58}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_61 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_87, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_74}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_96 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_61, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_49}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_97 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_96, cs_decoder_decoded_andMatrixOutputs_lo_lo_87}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_58 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_97, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_96}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_94 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_94}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_53 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_97, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_97}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_74 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_97, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_97}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_97 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_74, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_53}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_97 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_97, cs_decoder_decoded_andMatrixOutputs_hi_lo_94}; // @[pla.scala:98:53] wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_97 = {cs_decoder_decoded_andMatrixOutputs_hi_97, cs_decoder_decoded_andMatrixOutputs_lo_97}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_54_2 = &_cs_decoder_decoded_andMatrixOutputs_T_97; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_54 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_55 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_59 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_57 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_61 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_58 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_59 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_56 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_57 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_62 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_63 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_60 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_61 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_52 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_53 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_12 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_79 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_80 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_81 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_20 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_21 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_19 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_23 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_100 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_97 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_98 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_99 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_100 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_17 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_9 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_10 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_29_3 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_109 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_110 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_28 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_29 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_27 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_28 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_29 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_30 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_57 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_54}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_88 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_50}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_50 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_62, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_59}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_62 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_88, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_75}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_97 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_62, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_50}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_98 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_97, cs_decoder_decoded_andMatrixOutputs_lo_lo_88}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_59 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_98, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_97}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_95 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_59, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_95}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_54 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_98, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_98}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_75 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_98, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_98}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_98 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_75, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_54}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_98 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_98, cs_decoder_decoded_andMatrixOutputs_hi_lo_95}; // @[pla.scala:98:53] wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_98 = {cs_decoder_decoded_andMatrixOutputs_hi_98, cs_decoder_decoded_andMatrixOutputs_lo_98}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_7_2 = &_cs_decoder_decoded_andMatrixOutputs_T_98; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_58 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_55}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_89 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_51}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_51 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_60}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_63 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_89, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_76}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_98 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_63, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_51}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_99 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_98, cs_decoder_decoded_andMatrixOutputs_lo_lo_89}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_60 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_99, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_98}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_96 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_96}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_55 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_99, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_99}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_76 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_99, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_99}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_99 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_76, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_55}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_99 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_99, cs_decoder_decoded_andMatrixOutputs_hi_lo_96}; // @[pla.scala:98:53] wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_99 = {cs_decoder_decoded_andMatrixOutputs_hi_99, cs_decoder_decoded_andMatrixOutputs_lo_99}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_115_2 = &_cs_decoder_decoded_andMatrixOutputs_T_99; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_59 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_59, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_90 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_59, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_52}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_52 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_61}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_64 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_90, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_77}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_99 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_64, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_52}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_100 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_99, cs_decoder_decoded_andMatrixOutputs_lo_lo_90}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_61 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_100, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_99}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_97 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_97}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_56 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_100, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_100}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_77 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_100, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_100}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_100 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_77, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_56}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_100 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_100, cs_decoder_decoded_andMatrixOutputs_hi_lo_97}; // @[pla.scala:98:53] wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_100 = {cs_decoder_decoded_andMatrixOutputs_hi_100, cs_decoder_decoded_andMatrixOutputs_lo_100}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_92_2 = &_cs_decoder_decoded_andMatrixOutputs_T_100; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_60 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_53}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_91 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_43}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_53 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_62, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_60}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_65 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_65}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_100 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_65, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_53}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_101 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_100, cs_decoder_decoded_andMatrixOutputs_lo_lo_91}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_43 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_98, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_91}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_62 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_101, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_100}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_98 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_62, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_43}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_57 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_101, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_101}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_78 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_101, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_101}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_101 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_78, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_57}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_101 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_101, cs_decoder_decoded_andMatrixOutputs_hi_lo_98}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_101 = {cs_decoder_decoded_andMatrixOutputs_hi_101, cs_decoder_decoded_andMatrixOutputs_lo_101}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_40_2 = &_cs_decoder_decoded_andMatrixOutputs_T_101; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_61 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_63}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_92 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_61}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_66 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_99, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_92}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_101 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_79}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_102 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_101, cs_decoder_decoded_andMatrixOutputs_lo_lo_92}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_63 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_102, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_102}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_99 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_101}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_79 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_102, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_102}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_102 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_79, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_102}; // @[pla.scala:90:45, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_102 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_102, cs_decoder_decoded_andMatrixOutputs_hi_lo_99}; // @[pla.scala:98:53] wire [11:0] _cs_decoder_decoded_andMatrixOutputs_T_102 = {cs_decoder_decoded_andMatrixOutputs_hi_102, cs_decoder_decoded_andMatrixOutputs_lo_102}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_63_2 = &_cs_decoder_decoded_andMatrixOutputs_T_102; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_62 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_54}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_93 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_62, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_44}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_54 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_62}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_67 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_67}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_102 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_67, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_54}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_103 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_102, cs_decoder_decoded_andMatrixOutputs_lo_lo_93}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_44 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_100, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_93}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_64 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_103, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_102}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_100 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_64, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_44}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_58 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_103, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_103}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_80 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_103, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_103}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_103 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_80, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_58}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_103 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_103, cs_decoder_decoded_andMatrixOutputs_hi_lo_100}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_103 = {cs_decoder_decoded_andMatrixOutputs_hi_103, cs_decoder_decoded_andMatrixOutputs_lo_103}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_133_2 = &_cs_decoder_decoded_andMatrixOutputs_T_103; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_63 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_59, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_55}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_94 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_45}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_55 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_65, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_63}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_68 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_68}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_103 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_68, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_55}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_104 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_103, cs_decoder_decoded_andMatrixOutputs_lo_lo_94}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_45 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_101, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_94}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_65 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_104, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_103}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_101 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_65, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_45}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_59 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_104, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_104}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_81 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_104, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_104}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_104 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_81, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_59}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_104 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_104, cs_decoder_decoded_andMatrixOutputs_hi_lo_101}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_104 = {cs_decoder_decoded_andMatrixOutputs_hi_104, cs_decoder_decoded_andMatrixOutputs_lo_104}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_28_2 = &_cs_decoder_decoded_andMatrixOutputs_T_104; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_64 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_95 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_46}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_56 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_64}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_69 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_82, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_69}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_104 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_69, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_56}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_105 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_104, cs_decoder_decoded_andMatrixOutputs_lo_lo_95}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_46 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_102, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_95}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_66 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_105, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_104}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_102 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_66, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_46}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_60 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_105, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_105}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_82 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_105, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_105}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_105 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_82, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_60}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_105 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_105, cs_decoder_decoded_andMatrixOutputs_hi_lo_102}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_105 = {cs_decoder_decoded_andMatrixOutputs_hi_105, cs_decoder_decoded_andMatrixOutputs_lo_105}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_68_2 = &_cs_decoder_decoded_andMatrixOutputs_T_105; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_65 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_57}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_96 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_65, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_47}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_57 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_67, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_65}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_70 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_70}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_105 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_70, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_57}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_106 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_105, cs_decoder_decoded_andMatrixOutputs_lo_lo_96}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_47 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_103, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_96}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_67 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_106, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_105}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_103 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_67, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_47}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_61 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_106, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_106}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_83 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_106, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_106}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_106 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_83, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_61}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_106 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_106, cs_decoder_decoded_andMatrixOutputs_hi_lo_103}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_106 = {cs_decoder_decoded_andMatrixOutputs_hi_106, cs_decoder_decoded_andMatrixOutputs_lo_106}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_11_2 = &_cs_decoder_decoded_andMatrixOutputs_T_106; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_66 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_62, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_97 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_48}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_58 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_68, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_66}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_71 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_71}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_106 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_71, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_58}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_107 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_106, cs_decoder_decoded_andMatrixOutputs_lo_lo_97}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_48 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_104, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_97}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_68 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_107, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_106}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_104 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_68, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_48}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_62 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_107, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_107}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_84 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_107, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_107}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_107 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_84, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_62}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_107 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_107, cs_decoder_decoded_andMatrixOutputs_hi_lo_104}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_107 = {cs_decoder_decoded_andMatrixOutputs_hi_107, cs_decoder_decoded_andMatrixOutputs_lo_107}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_74_2 = &_cs_decoder_decoded_andMatrixOutputs_T_107; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_67 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_59}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_98 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_67, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_49}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_59 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_69, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_67}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_72 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_85, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_72}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_107 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_72, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_59}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_108 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_107, cs_decoder_decoded_andMatrixOutputs_lo_lo_98}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_49 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_105, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_98}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_69 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_108, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_107}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_105 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_69, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_49}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_63 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_108, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_108}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_85 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_108, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_108}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_108 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_85, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_63}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_108 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_108, cs_decoder_decoded_andMatrixOutputs_hi_lo_105}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_108 = {cs_decoder_decoded_andMatrixOutputs_hi_108, cs_decoder_decoded_andMatrixOutputs_lo_108}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_139_2 = &_cs_decoder_decoded_andMatrixOutputs_T_108; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_68 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_60}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_99 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_68, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_50}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_60 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_70, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_68}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_73 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_86, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_73}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_108 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_73, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_60}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_109 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_108, cs_decoder_decoded_andMatrixOutputs_lo_lo_99}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_50 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_106, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_99}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_70 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_109, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_108}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_106 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_70, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_50}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_64 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_109, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_109}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_86 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_109, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_109}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_109 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_86, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_64}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_109 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_109, cs_decoder_decoded_andMatrixOutputs_hi_lo_106}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_109 = {cs_decoder_decoded_andMatrixOutputs_hi_109, cs_decoder_decoded_andMatrixOutputs_lo_109}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_156_2 = &_cs_decoder_decoded_andMatrixOutputs_T_109; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_51, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_24}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_69 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_65, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_61}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_100 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_69, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_24}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_61 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_69}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_74 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_87, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_74}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_109 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_74, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_61}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_110 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_109, cs_decoder_decoded_andMatrixOutputs_lo_lo_100}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_51 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_107, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_100}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_71 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_110, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_109}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_107 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_71, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_51}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_65 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_110, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_110}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_87 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_110, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_110}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_110 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_87, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_65}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_110 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_110, cs_decoder_decoded_andMatrixOutputs_hi_lo_107}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_110 = {cs_decoder_decoded_andMatrixOutputs_hi_110, cs_decoder_decoded_andMatrixOutputs_lo_110}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_38_2 = &_cs_decoder_decoded_andMatrixOutputs_T_110; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_70 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_62}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_101 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_70, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_25}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_62 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_70}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_75 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_88, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_75}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_110 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_75, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_62}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_111 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_110, cs_decoder_decoded_andMatrixOutputs_lo_lo_101}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_52 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_108, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_101}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_72 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_111, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_110}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_108 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_72, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_52}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_66 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_111, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_111}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_88 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_111, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_111}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_111 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_88, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_66}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_111 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_111, cs_decoder_decoded_andMatrixOutputs_hi_lo_108}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_111 = {cs_decoder_decoded_andMatrixOutputs_hi_111, cs_decoder_decoded_andMatrixOutputs_lo_111}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_116_2 = &_cs_decoder_decoded_andMatrixOutputs_T_111; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_16}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_71 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_53}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_102 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_71, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_26}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_63 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_67}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_76 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_73}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_111 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_76, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_63}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_112 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_111, cs_decoder_decoded_andMatrixOutputs_lo_lo_102}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_53 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_102, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_89}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_73 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_111, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_109}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_109 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_73, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_53}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_67 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_112, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_112}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_112, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_112}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_89 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_112}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_112 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_89, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_67}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_112 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_112, cs_decoder_decoded_andMatrixOutputs_hi_lo_109}; // @[pla.scala:98:53] wire [16:0] _cs_decoder_decoded_andMatrixOutputs_T_112 = {cs_decoder_decoded_andMatrixOutputs_hi_112, cs_decoder_decoded_andMatrixOutputs_lo_112}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_4_2 = &_cs_decoder_decoded_andMatrixOutputs_T_112; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_11}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_72 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_12}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_103 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_72, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_27}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_54, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_27}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_64 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_17}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_68}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_77 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_64}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_112 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_77, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_64}; // @[pla.scala:98:53] wire [10:0] cs_decoder_decoded_andMatrixOutputs_lo_113 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_112, cs_decoder_decoded_andMatrixOutputs_lo_lo_103}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_54 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_74}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_110, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_103}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_74 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_90}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_110 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_74, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_54}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_113, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_113}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_68 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_112}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_113, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_113}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_90 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_113}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_113 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_90, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_68}; // @[pla.scala:98:53] wire [10:0] cs_decoder_decoded_andMatrixOutputs_hi_113 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_113, cs_decoder_decoded_andMatrixOutputs_hi_lo_110}; // @[pla.scala:98:53] wire [21:0] _cs_decoder_decoded_andMatrixOutputs_T_113 = {cs_decoder_decoded_andMatrixOutputs_hi_113, cs_decoder_decoded_andMatrixOutputs_lo_113}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_163_2 = &_cs_decoder_decoded_andMatrixOutputs_T_113; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_55 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_56 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_75 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_67 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_58 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_69 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_70 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_61 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_72 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_63 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_64 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_75 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_66 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_67 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_36 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_14 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_15 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_16 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_17 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_83 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_74 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_75 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_43 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_24 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_19 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_46 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_47 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_48 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_17 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_18 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_15 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_20 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_96 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_87 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_88 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_89 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_90 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_13 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_9 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_6 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_30_3 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_97 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_108 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_99 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_100 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_101 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_25 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_26 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_23 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_24 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_25 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_26 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_73 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_69, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_65}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_104 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_73, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_28}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_65 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_73}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_78 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_78}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_113 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_78, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_65}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_114 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_113, cs_decoder_decoded_andMatrixOutputs_lo_lo_104}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_55 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_111, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_104}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_75 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_114, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_113}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_111 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_75, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_55}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_69 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_114, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_114}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_91 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_114, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_114}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_114 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_91, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_69}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_114 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_114, cs_decoder_decoded_andMatrixOutputs_hi_lo_111}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_114 = {cs_decoder_decoded_andMatrixOutputs_hi_114, cs_decoder_decoded_andMatrixOutputs_lo_114}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_5_2 = &_cs_decoder_decoded_andMatrixOutputs_T_114; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_74 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_70, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_66}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_105 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_74, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_29}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_66 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_74}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_79 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_92, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_79}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_114 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_79, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_66}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_115 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_114, cs_decoder_decoded_andMatrixOutputs_lo_lo_105}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_56 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_112, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_105}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_76 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_115, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_114}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_112 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_76, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_56}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_70 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_115, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_115}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_92 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_115, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_115}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_115 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_92, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_70}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_115 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_115, cs_decoder_decoded_andMatrixOutputs_hi_lo_112}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_115 = {cs_decoder_decoded_andMatrixOutputs_hi_115, cs_decoder_decoded_andMatrixOutputs_lo_115}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_22_2 = &_cs_decoder_decoded_andMatrixOutputs_T_115; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_75 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_77}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_106 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_75}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_80 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_113, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_106}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_115 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_93}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_116 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_115, cs_decoder_decoded_andMatrixOutputs_lo_lo_106}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_77 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_116, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_116}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_113 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_115}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_93 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_116, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_116}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_116 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_93, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_116}; // @[pla.scala:90:45, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_116 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_116, cs_decoder_decoded_andMatrixOutputs_hi_lo_113}; // @[pla.scala:98:53] wire [11:0] _cs_decoder_decoded_andMatrixOutputs_T_116 = {cs_decoder_decoded_andMatrixOutputs_hi_116, cs_decoder_decoded_andMatrixOutputs_lo_116}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_48_2 = &_cs_decoder_decoded_andMatrixOutputs_T_116; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_76 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_67}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_107 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_57}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_67 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_76}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_81 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_94, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_81}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_116 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_81, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_67}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_117 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_116, cs_decoder_decoded_andMatrixOutputs_lo_lo_107}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_57 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_114, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_107}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_78 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_117, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_116}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_114 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_78, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_57}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_71 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_117, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_117}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_94 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_117, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_117}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_117 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_94, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_71}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_117 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_117, cs_decoder_decoded_andMatrixOutputs_hi_lo_114}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_117 = {cs_decoder_decoded_andMatrixOutputs_hi_117, cs_decoder_decoded_andMatrixOutputs_lo_117}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_125_2 = &_cs_decoder_decoded_andMatrixOutputs_T_117; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_77 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_68}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_108 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_77, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_30}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_68 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_79, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_77}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_82 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_95, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_82}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_117 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_82, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_68}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_118 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_117, cs_decoder_decoded_andMatrixOutputs_lo_lo_108}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_58 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_115, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_108}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_79 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_118, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_117}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_115 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_79, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_58}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_72 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_118, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_118}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_95 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_118, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_118}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_118 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_95, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_72}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_118 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_118, cs_decoder_decoded_andMatrixOutputs_hi_lo_115}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_118 = {cs_decoder_decoded_andMatrixOutputs_hi_118, cs_decoder_decoded_andMatrixOutputs_lo_118}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_24_2 = &_cs_decoder_decoded_andMatrixOutputs_T_118; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_78 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_73, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_69}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_109 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_59}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_69 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_78}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_83 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_96, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_83}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_118 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_83, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_69}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_119 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_118, cs_decoder_decoded_andMatrixOutputs_lo_lo_109}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_59 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_116, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_109}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_80 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_119, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_118}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_116 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_80, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_59}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_73 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_119, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_119}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_96 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_119, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_119}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_119 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_96, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_73}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_119 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_119, cs_decoder_decoded_andMatrixOutputs_hi_lo_116}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_119 = {cs_decoder_decoded_andMatrixOutputs_hi_119, cs_decoder_decoded_andMatrixOutputs_lo_119}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_44_2 = &_cs_decoder_decoded_andMatrixOutputs_T_119; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_79 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_74, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_70}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_110 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_79, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_60}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_70 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_79}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_84 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_97, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_84}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_119 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_84, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_70}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_120 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_119, cs_decoder_decoded_andMatrixOutputs_lo_lo_110}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_60 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_117, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_110}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_81 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_120, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_119}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_117 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_81, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_60}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_74 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_120, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_120}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_97 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_120, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_120}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_120 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_97, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_74}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_120 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_120, cs_decoder_decoded_andMatrixOutputs_hi_lo_117}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_120 = {cs_decoder_decoded_andMatrixOutputs_hi_120, cs_decoder_decoded_andMatrixOutputs_lo_120}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_119_2 = &_cs_decoder_decoded_andMatrixOutputs_T_120; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_80 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_71}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_111 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_80, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_31}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_71 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_82, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_80}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_85 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_98, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_85}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_120 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_85, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_71}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_121 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_120, cs_decoder_decoded_andMatrixOutputs_lo_lo_111}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_61 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_118, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_111}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_82 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_121, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_120}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_118 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_82, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_61}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_75 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_121, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_121}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_98 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_121, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_121}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_121 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_98, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_75}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_121 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_121, cs_decoder_decoded_andMatrixOutputs_hi_lo_118}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_121 = {cs_decoder_decoded_andMatrixOutputs_hi_121, cs_decoder_decoded_andMatrixOutputs_lo_121}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_154_2 = &_cs_decoder_decoded_andMatrixOutputs_T_121; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_81 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_72}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_112 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_62}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_72 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_81}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_86 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_99, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_86}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_121 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_86, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_72}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_122 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_121, cs_decoder_decoded_andMatrixOutputs_lo_lo_112}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_62 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_119, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_112}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_83 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_122, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_121}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_119 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_83, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_62}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_76 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_122, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_122}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_99 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_122, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_122}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_122 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_99, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_76}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_122 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_122, cs_decoder_decoded_andMatrixOutputs_hi_lo_119}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_122 = {cs_decoder_decoded_andMatrixOutputs_hi_122, cs_decoder_decoded_andMatrixOutputs_lo_122}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_151_2 = &_cs_decoder_decoded_andMatrixOutputs_T_122; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_32}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_82 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_73}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_113 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_82, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_32}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_73 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_82}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_87 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_100, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_87}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_122 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_87, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_73}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_123 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_122, cs_decoder_decoded_andMatrixOutputs_lo_lo_113}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_63 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_120, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_113}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_84 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_123, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_122}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_120 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_84, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_63}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_77 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_123, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_123}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_100 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_123, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_123}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_123 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_100, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_77}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_123 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_123, cs_decoder_decoded_andMatrixOutputs_hi_lo_120}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_123 = {cs_decoder_decoded_andMatrixOutputs_hi_123, cs_decoder_decoded_andMatrixOutputs_lo_123}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_104_2 = &_cs_decoder_decoded_andMatrixOutputs_T_123; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_83 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_74}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_114 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_83, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_33}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_74 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_85, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_83}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_88 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_101, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_88}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_123 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_88, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_74}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_124 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_123, cs_decoder_decoded_andMatrixOutputs_lo_lo_114}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_64 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_121, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_114}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_85 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_124, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_123}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_121 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_85, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_64}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_78 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_124, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_124}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_101 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_124, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_124}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_124 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_101, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_78}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_124 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_124, cs_decoder_decoded_andMatrixOutputs_hi_lo_121}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_124 = {cs_decoder_decoded_andMatrixOutputs_hi_124, cs_decoder_decoded_andMatrixOutputs_lo_124}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_20_2 = &_cs_decoder_decoded_andMatrixOutputs_T_124; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_84 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_79, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_75}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_115 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_65}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_75 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_86, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_84}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_89 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_102, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_89}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_124 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_89, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_75}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_125 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_124, cs_decoder_decoded_andMatrixOutputs_lo_lo_115}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_65 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_122, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_115}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_86 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_125, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_124}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_122 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_86, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_65}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_79 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_125, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_125}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_102 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_125, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_125}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_125 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_102, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_79}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_125 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_125, cs_decoder_decoded_andMatrixOutputs_hi_lo_122}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_125 = {cs_decoder_decoded_andMatrixOutputs_hi_125, cs_decoder_decoded_andMatrixOutputs_lo_125}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_49_2 = &_cs_decoder_decoded_andMatrixOutputs_T_125; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_34 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_85 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_76}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_116 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_85, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_34}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_76 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_87, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_85}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_90 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_103, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_90}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_125 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_90, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_76}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_126 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_125, cs_decoder_decoded_andMatrixOutputs_lo_lo_116}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_66 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_123, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_116}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_87 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_126, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_125}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_123 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_87, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_66}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_80 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_126, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_126}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_103 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_126, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_126}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_126 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_103, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_80}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_126 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_126, cs_decoder_decoded_andMatrixOutputs_hi_lo_123}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_126 = {cs_decoder_decoded_andMatrixOutputs_hi_126, cs_decoder_decoded_andMatrixOutputs_lo_126}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_122_2 = &_cs_decoder_decoded_andMatrixOutputs_T_126; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_35 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_67, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_86 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_77}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_117 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_86, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_35}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_77 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_88, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_86}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_91 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_104, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_91}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_126 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_91, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_77}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_127 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_126, cs_decoder_decoded_andMatrixOutputs_lo_lo_117}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_67 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_124, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_117}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_88 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_127, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_126}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_124 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_88, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_67}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_81 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_127, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_127}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_104 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_127, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_127}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_127 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_104, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_81}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_127 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_127, cs_decoder_decoded_andMatrixOutputs_hi_lo_124}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_127 = {cs_decoder_decoded_andMatrixOutputs_hi_127, cs_decoder_decoded_andMatrixOutputs_lo_127}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_12_2 = &_cs_decoder_decoded_andMatrixOutputs_T_127; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_18}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_87 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_68}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_118 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_87, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_36}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_78 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_87, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_82}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_92 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_92, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_89}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_127 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_92, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_78}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_128 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_127, cs_decoder_decoded_andMatrixOutputs_lo_lo_118}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_68 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_118, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_105}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_89 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_127, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_125}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_125 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_89, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_68}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_82 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_128, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_128}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_128, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_128}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_105 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_128}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_128 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_105, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_82}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_128 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_128, cs_decoder_decoded_andMatrixOutputs_hi_lo_125}; // @[pla.scala:98:53] wire [16:0] _cs_decoder_decoded_andMatrixOutputs_T_128 = {cs_decoder_decoded_andMatrixOutputs_hi_128, cs_decoder_decoded_andMatrixOutputs_lo_128}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_41_2 = &_cs_decoder_decoded_andMatrixOutputs_T_128; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_37 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_88 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_69, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_37}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_119 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_88, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_37}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_79 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_79}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_93, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_90}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_93 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_88}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_128 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_93, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_79}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_lo_129 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_128, cs_decoder_decoded_andMatrixOutputs_lo_lo_119}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_69 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_119, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_106}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_90 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_128, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_126}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_126 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_90, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_69}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_83 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_129, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_129}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_129, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_129}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_106 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_129}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_129 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_106, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_83}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_129 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_129, cs_decoder_decoded_andMatrixOutputs_hi_lo_126}; // @[pla.scala:98:53] wire [17:0] _cs_decoder_decoded_andMatrixOutputs_T_129 = {cs_decoder_decoded_andMatrixOutputs_hi_129, cs_decoder_decoded_andMatrixOutputs_lo_129}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_152_2 = &_cs_decoder_decoded_andMatrixOutputs_T_129; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_38 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_89 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_20}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_120 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_89, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_38}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_80 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_70}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_89}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_94 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_84}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_129 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_94, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_80}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_lo_130 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_129, cs_decoder_decoded_andMatrixOutputs_lo_lo_120}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_70 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_107, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_94}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_129, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_127}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_91 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_120}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_127 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_91, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_70}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_84 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_130, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_130}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_130, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_130}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_107 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_130}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_130 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_107, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_84}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_hi_130 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_130, cs_decoder_decoded_andMatrixOutputs_hi_lo_127}; // @[pla.scala:98:53] wire [18:0] _cs_decoder_decoded_andMatrixOutputs_T_130 = {cs_decoder_decoded_andMatrixOutputs_hi_130, cs_decoder_decoded_andMatrixOutputs_lo_130}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_23_2 = &_cs_decoder_decoded_andMatrixOutputs_T_130; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_90 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_39}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_121 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_90, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_39}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_81 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_85, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_81}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_95, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_92}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_95 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_90}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_130 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_95, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_81}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_lo_131 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_130, cs_decoder_decoded_andMatrixOutputs_lo_lo_121}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_71 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_121, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_108}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_92 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_130, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_128}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_128 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_92, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_71}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_85 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_131, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_131}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_131, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_131}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_108 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_131}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_131 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_108, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_85}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_131 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_131, cs_decoder_decoded_andMatrixOutputs_hi_lo_128}; // @[pla.scala:98:53] wire [17:0] _cs_decoder_decoded_andMatrixOutputs_T_131 = {cs_decoder_decoded_andMatrixOutputs_hi_131, cs_decoder_decoded_andMatrixOutputs_lo_131}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_98_2 = &_cs_decoder_decoded_andMatrixOutputs_T_131; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_91 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_22}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_122 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_91, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_40}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_82 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_82, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_72}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_93, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_91}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_96 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_86}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_131 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_96, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_82}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_lo_132 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_131, cs_decoder_decoded_andMatrixOutputs_lo_lo_122}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_72 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_109, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_96}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_131, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_129}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_93 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_122}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_129 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_93, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_72}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_86 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_132, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_132}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_132, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_132}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_109 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_132}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_132 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_109, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_86}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_hi_132 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_132, cs_decoder_decoded_andMatrixOutputs_hi_lo_129}; // @[pla.scala:98:53] wire [18:0] _cs_decoder_decoded_andMatrixOutputs_T_132 = {cs_decoder_decoded_andMatrixOutputs_hi_132, cs_decoder_decoded_andMatrixOutputs_lo_132}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_15_2 = &_cs_decoder_decoded_andMatrixOutputs_T_132; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_92 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_87, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_83}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_123 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_92, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_73}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_83 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_94, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_92}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_97 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_110, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_97}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_132 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_97, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_83}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_133 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_132, cs_decoder_decoded_andMatrixOutputs_lo_lo_123}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_73 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_130, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_123}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_94 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_133, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_132}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_130 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_94, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_73}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_87 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_133, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_133}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_110 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_133, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_133}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_133 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_110, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_87}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_133 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_133, cs_decoder_decoded_andMatrixOutputs_hi_lo_130}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_133 = {cs_decoder_decoded_andMatrixOutputs_hi_133, cs_decoder_decoded_andMatrixOutputs_lo_133}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_36_2 = &_cs_decoder_decoded_andMatrixOutputs_T_133; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_41 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_74, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_41}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_93 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_88, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_84}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_124 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_93, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_41}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_84 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_95, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_93}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_98 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_111, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_98}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_133 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_98, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_84}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_134 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_133, cs_decoder_decoded_andMatrixOutputs_lo_lo_124}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_74 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_131, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_124}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_95 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_134, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_133}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_131 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_95, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_74}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_88 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_134, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_134}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_111 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_134, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_134}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_134 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_111, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_88}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_134 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_134, cs_decoder_decoded_andMatrixOutputs_hi_lo_131}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_134 = {cs_decoder_decoded_andMatrixOutputs_hi_134, cs_decoder_decoded_andMatrixOutputs_lo_134}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_46_2 = &_cs_decoder_decoded_andMatrixOutputs_T_134; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_42 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_94 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_89, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_85}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_125 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_94, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_42}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_85 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_96, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_94}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_99 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_112, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_99}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_134 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_99, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_85}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_135 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_134, cs_decoder_decoded_andMatrixOutputs_lo_lo_125}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_75 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_132, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_125}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_96 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_135, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_134}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_132 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_96, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_75}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_89 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_135, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_135}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_112 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_135, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_135}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_135 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_112, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_89}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_135 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_135, cs_decoder_decoded_andMatrixOutputs_hi_lo_132}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_135 = {cs_decoder_decoded_andMatrixOutputs_hi_135, cs_decoder_decoded_andMatrixOutputs_lo_135}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_55_2 = &_cs_decoder_decoded_andMatrixOutputs_T_135; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_43 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_95 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_86, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_76}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_126 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_95, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_43}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_86 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_95, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_90}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_100 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_100, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_97}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_135 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_100, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_86}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_136 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_135, cs_decoder_decoded_andMatrixOutputs_lo_lo_126}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_76 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_126, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_113}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_97 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_135, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_133}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_133 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_97, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_76}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_90 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_136, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_136}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_136, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_136}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_113 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_136}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_136 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_113, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_90}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_136 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_136, cs_decoder_decoded_andMatrixOutputs_hi_lo_133}; // @[pla.scala:98:53] wire [16:0] _cs_decoder_decoded_andMatrixOutputs_T_136 = {cs_decoder_decoded_andMatrixOutputs_hi_136, cs_decoder_decoded_andMatrixOutputs_lo_136}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_159_2 = &_cs_decoder_decoded_andMatrixOutputs_T_136; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_44 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_18}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_96 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_44}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_127 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_96, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_44}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_87 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_87}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_101, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_98}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_101 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_96}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_136 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_101, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_87}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_lo_137 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_136, cs_decoder_decoded_andMatrixOutputs_lo_lo_127}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_77 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_127, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_114}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_98 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_136, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_134}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_134 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_98, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_77}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_91 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_137, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_137}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_137, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_137}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_114 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_137}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_137 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_114, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_91}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_137 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_137, cs_decoder_decoded_andMatrixOutputs_hi_lo_134}; // @[pla.scala:98:53] wire [17:0] _cs_decoder_decoded_andMatrixOutputs_T_137 = {cs_decoder_decoded_andMatrixOutputs_hi_137, cs_decoder_decoded_andMatrixOutputs_lo_137}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_117_2 = &_cs_decoder_decoded_andMatrixOutputs_T_137; // @[pla.scala:98:{53,70}] wire _cs_decoder_decoded_orMatrixOutputs_T_2 = cs_decoder_decoded_andMatrixOutputs_117_2; // @[pla.scala:98:70, :114:36] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_45 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_97 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_128 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_97, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_45}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_88 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_88, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_78}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_99, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_97}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_102 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_92}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_137 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_102, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_88}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_lo_138 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_137, cs_decoder_decoded_andMatrixOutputs_lo_lo_128}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_78 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_115, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_102}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_137, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_135}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_99 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_128}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_135 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_99, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_78}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_92 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_138, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_138}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_138, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_138}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_115 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_138}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_138 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_115, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_92}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_hi_138 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_138, cs_decoder_decoded_andMatrixOutputs_hi_lo_135}; // @[pla.scala:98:53] wire [18:0] _cs_decoder_decoded_andMatrixOutputs_T_138 = {cs_decoder_decoded_andMatrixOutputs_hi_138, cs_decoder_decoded_andMatrixOutputs_lo_138}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_109_2 = &_cs_decoder_decoded_andMatrixOutputs_T_138; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_46 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_46, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_98 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_89, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_79}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_129 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_98, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_46}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_89 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_98, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_93}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_103 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_103, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_100}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_138 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_103, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_89}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_139 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_138, cs_decoder_decoded_andMatrixOutputs_lo_lo_129}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_79 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_129, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_116}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_100 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_138, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_136}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_136 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_100, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_79}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_93 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_139, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_139}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_139, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_139}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_116 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_139}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_139 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_116, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_93}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_139 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_139, cs_decoder_decoded_andMatrixOutputs_hi_lo_136}; // @[pla.scala:98:53] wire [16:0] _cs_decoder_decoded_andMatrixOutputs_T_139 = {cs_decoder_decoded_andMatrixOutputs_hi_139, cs_decoder_decoded_andMatrixOutputs_lo_139}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_128_2 = &_cs_decoder_decoded_andMatrixOutputs_T_139; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_47 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_27}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_99 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_90, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_80}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_130 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_99, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_47}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_90 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_99, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_94}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_104 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_104, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_101}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_139 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_104, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_90}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_140 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_139, cs_decoder_decoded_andMatrixOutputs_lo_lo_130}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_80 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_130, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_117}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_101 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_139, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_137}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_137 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_101, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_80}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_94 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_140, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_140}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_140, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_140}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_117 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_140}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_140 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_117, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_94}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_140 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_140, cs_decoder_decoded_andMatrixOutputs_hi_lo_137}; // @[pla.scala:98:53] wire [16:0] _cs_decoder_decoded_andMatrixOutputs_T_140 = {cs_decoder_decoded_andMatrixOutputs_hi_140, cs_decoder_decoded_andMatrixOutputs_lo_140}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_2_2 = &_cs_decoder_decoded_andMatrixOutputs_T_140; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_48 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_100 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_81}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_131 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_100, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_48}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_91 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_100, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_95}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_105 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_105, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_102}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_140 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_105, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_91}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_141 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_140, cs_decoder_decoded_andMatrixOutputs_lo_lo_131}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_81 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_131, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_118}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_102 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_140, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_138}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_138 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_102, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_81}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_95 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_141, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_141}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_141, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_141}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_118 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_141}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_141 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_118, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_95}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_141 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_141, cs_decoder_decoded_andMatrixOutputs_hi_lo_138}; // @[pla.scala:98:53] wire [16:0] _cs_decoder_decoded_andMatrixOutputs_T_141 = {cs_decoder_decoded_andMatrixOutputs_hi_141, cs_decoder_decoded_andMatrixOutputs_lo_141}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_83_2 = &_cs_decoder_decoded_andMatrixOutputs_T_141; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_49 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_49, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_29}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_101 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_20}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_132 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_101, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_49}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_92 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_92, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_82}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_103, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_101}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_106 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_96}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_141 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_106, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_92}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_lo_142 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_141, cs_decoder_decoded_andMatrixOutputs_lo_lo_132}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_82 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_119, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_106}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_141, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_139}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_103 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_132}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_139 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_103, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_82}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_96 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_142, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_142}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_142, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_142}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_119 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_142}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_142 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_119, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_96}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_hi_142 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_142, cs_decoder_decoded_andMatrixOutputs_hi_lo_139}; // @[pla.scala:98:53] wire [19:0] _cs_decoder_decoded_andMatrixOutputs_T_142 = {cs_decoder_decoded_andMatrixOutputs_hi_142, cs_decoder_decoded_andMatrixOutputs_lo_142}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_87_2 = &_cs_decoder_decoded_andMatrixOutputs_T_142; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_50 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_50, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_30}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_102 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_21}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_133 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_102, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_50}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_93 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_93, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_83}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_104, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_102}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_107 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_97}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_142 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_107, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_93}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_lo_143 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_142, cs_decoder_decoded_andMatrixOutputs_lo_lo_133}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_83 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_120, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_107}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_142, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_140}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_104 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_133}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_140 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_104, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_83}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_97 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_143, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_143}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_143, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_143}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_120 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_143}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_143 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_120, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_97}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_hi_143 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_143, cs_decoder_decoded_andMatrixOutputs_hi_lo_140}; // @[pla.scala:98:53] wire [19:0] _cs_decoder_decoded_andMatrixOutputs_T_143 = {cs_decoder_decoded_andMatrixOutputs_hi_143, cs_decoder_decoded_andMatrixOutputs_lo_143}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_158_2 = &_cs_decoder_decoded_andMatrixOutputs_T_143; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_51 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_22}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_103 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_19}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_134 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_103, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_51}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_94 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_51}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_103, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_98}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_108 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_94}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_143 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_108, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_94}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_lo_144 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_143, cs_decoder_decoded_andMatrixOutputs_lo_lo_134}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_84 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_108, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_105}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_141, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_134}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_105 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_121}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_141 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_105, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_84}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_144, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_144}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_98 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_143}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_144, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_144}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_121 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_144}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_144 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_121, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_98}; // @[pla.scala:98:53] wire [10:0] cs_decoder_decoded_andMatrixOutputs_hi_144 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_144, cs_decoder_decoded_andMatrixOutputs_hi_lo_141}; // @[pla.scala:98:53] wire [20:0] _cs_decoder_decoded_andMatrixOutputs_T_144 = {cs_decoder_decoded_andMatrixOutputs_hi_144, cs_decoder_decoded_andMatrixOutputs_lo_144}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_19_2 = &_cs_decoder_decoded_andMatrixOutputs_T_144; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_52 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_32}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_104 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_23}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_135 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_104, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_52}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_95 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_95, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_85}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_106, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_104}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_109 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_99}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_144 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_109, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_95}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_lo_145 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_144, cs_decoder_decoded_andMatrixOutputs_lo_lo_135}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_85 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_122, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_109}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_144, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_142}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_106 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_135}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_142 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_106, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_85}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_99 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_145, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_145}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_145, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_145}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_122 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_145}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_145 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_122, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_99}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_hi_145 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_145, cs_decoder_decoded_andMatrixOutputs_hi_lo_142}; // @[pla.scala:98:53] wire [19:0] _cs_decoder_decoded_andMatrixOutputs_T_145 = {cs_decoder_decoded_andMatrixOutputs_hi_145, cs_decoder_decoded_andMatrixOutputs_lo_145}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_91_2 = &_cs_decoder_decoded_andMatrixOutputs_T_145; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_105 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_100, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_96}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_136 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_105, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_86}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_96 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_107, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_105}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_110 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_123, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_110}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_145 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_110, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_96}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_146 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_145, cs_decoder_decoded_andMatrixOutputs_lo_lo_136}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_86 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_143, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_136}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_107 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_146, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_145}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_143 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_107, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_86}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_100 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_146, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_146}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_123 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_146, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_146}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_146 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_123, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_100}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_146 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_146, cs_decoder_decoded_andMatrixOutputs_hi_lo_143}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_146 = {cs_decoder_decoded_andMatrixOutputs_hi_146, cs_decoder_decoded_andMatrixOutputs_lo_146}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_70_2 = &_cs_decoder_decoded_andMatrixOutputs_T_146; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_53 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_87, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_53}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_106 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_101, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_97}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_137 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_106, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_53}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_97 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_108, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_106}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_111 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_124, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_111}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_146 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_111, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_97}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_147 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_146, cs_decoder_decoded_andMatrixOutputs_lo_lo_137}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_87 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_144, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_137}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_108 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_147, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_146}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_144 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_108, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_87}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_101 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_147, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_147}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_124 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_147, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_147}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_147 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_124, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_101}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_147 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_147, cs_decoder_decoded_andMatrixOutputs_hi_lo_144}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_147 = {cs_decoder_decoded_andMatrixOutputs_hi_147, cs_decoder_decoded_andMatrixOutputs_lo_147}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_53_2 = &_cs_decoder_decoded_andMatrixOutputs_T_147; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_54 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_88, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_54}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_107 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_102, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_98}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_138 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_107, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_54}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_98 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_109, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_107}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_112 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_125, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_112}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_147 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_112, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_98}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_148 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_147, cs_decoder_decoded_andMatrixOutputs_lo_lo_138}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_88 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_145, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_138}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_109 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_148, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_147}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_145 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_109, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_88}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_102 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_148, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_148}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_125 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_148, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_148}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_148 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_125, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_102}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_148 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_148, cs_decoder_decoded_andMatrixOutputs_hi_lo_145}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_148 = {cs_decoder_decoded_andMatrixOutputs_hi_148, cs_decoder_decoded_andMatrixOutputs_lo_148}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_126_2 = &_cs_decoder_decoded_andMatrixOutputs_T_148; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_55 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_89, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_55}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_108 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_103, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_99}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_139 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_108, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_55}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_99 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_110, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_108}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_113 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_126, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_113}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_148 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_113, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_99}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_149 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_148, cs_decoder_decoded_andMatrixOutputs_lo_lo_139}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_89 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_146, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_139}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_110 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_149, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_148}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_146 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_110, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_89}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_103 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_149, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_149}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_126 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_149, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_149}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_149 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_126, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_103}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_149 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_149, cs_decoder_decoded_andMatrixOutputs_hi_lo_146}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_149 = {cs_decoder_decoded_andMatrixOutputs_hi_149, cs_decoder_decoded_andMatrixOutputs_lo_149}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_150_2 = &_cs_decoder_decoded_andMatrixOutputs_T_149; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_56 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_90, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_109 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_104, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_100}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_140 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_109, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_56}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_100 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_111, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_109}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_114 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_127, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_114}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_149 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_114, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_100}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_150 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_149, cs_decoder_decoded_andMatrixOutputs_lo_lo_140}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_90 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_147, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_140}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_111 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_150, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_149}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_147 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_111, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_90}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_104 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_150, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_150}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_127 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_150, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_150}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_150 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_127, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_104}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_150 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_150, cs_decoder_decoded_andMatrixOutputs_hi_lo_147}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_150 = {cs_decoder_decoded_andMatrixOutputs_hi_150, cs_decoder_decoded_andMatrixOutputs_lo_150}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_31_2 = &_cs_decoder_decoded_andMatrixOutputs_T_150; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_101 = cs_decoder_decoded_plaInput[23]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_91 = cs_decoder_decoded_plaInput[24]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_22 = cs_decoder_decoded_plaInput[24]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_15 = cs_decoder_decoded_plaInput[24]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_11 = cs_decoder_decoded_plaInput[24]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_57 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_110 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_17}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_141 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_110, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_57}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_57}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_101 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_33}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_110, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_105}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_115 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_101}; // @[pla.scala:90:45, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_150 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_115, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_101}; // @[pla.scala:98:53] wire [10:0] cs_decoder_decoded_andMatrixOutputs_lo_151 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_150, cs_decoder_decoded_andMatrixOutputs_lo_lo_141}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_91 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_115, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_112}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_148, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_141}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_112 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_128}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_148 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_112, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_91}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_151, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_151}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_105 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_150}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_151, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_151}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_128 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_151}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_151 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_128, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_105}; // @[pla.scala:98:53] wire [10:0] cs_decoder_decoded_andMatrixOutputs_hi_151 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_151, cs_decoder_decoded_andMatrixOutputs_hi_lo_148}; // @[pla.scala:98:53] wire [21:0] _cs_decoder_decoded_andMatrixOutputs_T_151 = {cs_decoder_decoded_andMatrixOutputs_hi_151, cs_decoder_decoded_andMatrixOutputs_lo_151}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_106_2 = &_cs_decoder_decoded_andMatrixOutputs_T_151; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_9}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_58 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_9}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_111 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_9}; // @[pla.scala:90:45, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_142 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_111, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_58}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_102 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_18}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_102, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_92}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_116 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_25, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_9}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_151 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_116, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_102}; // @[pla.scala:98:53] wire [12:0] cs_decoder_decoded_andMatrixOutputs_lo_152 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_151, cs_decoder_decoded_andMatrixOutputs_lo_lo_142}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_113, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_111}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_92 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_106}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_142, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_129}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_113 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_116}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_149 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_113, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_92}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_152, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_151}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_106 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_149}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_152, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_152}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_34 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_152, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_152}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_129 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_34, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_9}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_152 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_129, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_106}; // @[pla.scala:98:53] wire [12:0] cs_decoder_decoded_andMatrixOutputs_hi_152 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_152, cs_decoder_decoded_andMatrixOutputs_hi_lo_149}; // @[pla.scala:98:53] wire [25:0] _cs_decoder_decoded_andMatrixOutputs_T_152 = {cs_decoder_decoded_andMatrixOutputs_hi_152, cs_decoder_decoded_andMatrixOutputs_lo_152}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_78_2 = &_cs_decoder_decoded_andMatrixOutputs_T_152; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_6}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_59 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_6}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_10}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_112 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_19, cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_6}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_143 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_112, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_59}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_19}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_103 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_15}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_93, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_59}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_117 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_26, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_10}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_152 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_117, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_103}; // @[pla.scala:98:53] wire [13:0] cs_decoder_decoded_andMatrixOutputs_lo_153 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_152, cs_decoder_decoded_andMatrixOutputs_lo_lo_143}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_112, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_107}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_93 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_103}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_117, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_114}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_143, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_130}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_114 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_23, cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_6}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_150 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_114, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_93}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_153, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_152}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_107 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_150}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_153, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_153}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_35 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_153, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_153}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_130 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_35, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_10}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_153 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_130, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_107}; // @[pla.scala:98:53] wire [13:0] cs_decoder_decoded_andMatrixOutputs_hi_153 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_153, cs_decoder_decoded_andMatrixOutputs_hi_lo_150}; // @[pla.scala:98:53] wire [27:0] _cs_decoder_decoded_andMatrixOutputs_T_153 = {cs_decoder_decoded_andMatrixOutputs_hi_153, cs_decoder_decoded_andMatrixOutputs_lo_153}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_64_2 = &_cs_decoder_decoded_andMatrixOutputs_T_153; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_30_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_31_1}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_28_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_29_3}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_60 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_11, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_11}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_113 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_20, cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_7}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_144 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_113, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_60}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_11}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_104 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_15, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_20}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_27}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_118 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_27, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_11}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_153 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_118, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_104}; // @[pla.scala:98:53] wire [15:0] cs_decoder_decoded_andMatrixOutputs_lo_154 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_153, cs_decoder_decoded_andMatrixOutputs_lo_lo_144}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_94, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_60}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_108, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_104}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_94 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_11, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_115, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_113}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_131, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_118}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_115 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_24, cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_7}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_151 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_115, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_94}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_151, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_144}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_154, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_153}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_108 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_16, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_154, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_154}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_154, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_154}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_131 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_36, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_11}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_154 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_131, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_108}; // @[pla.scala:98:53] wire [15:0] cs_decoder_decoded_andMatrixOutputs_hi_154 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_154, cs_decoder_decoded_andMatrixOutputs_hi_lo_151}; // @[pla.scala:98:53] wire [31:0] _cs_decoder_decoded_andMatrixOutputs_T_154 = {cs_decoder_decoded_andMatrixOutputs_hi_154, cs_decoder_decoded_andMatrixOutputs_lo_154}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_103_2 = &_cs_decoder_decoded_andMatrixOutputs_T_154; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_114 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_95 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_96 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_61 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_98 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_62 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_63 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_64 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_21 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_22 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_17 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_18 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_19 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_20 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_114 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_119, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_116}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_145 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_114, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_114}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_119 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_152, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_145}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_154 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_119, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_132}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_155 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_154, cs_decoder_decoded_andMatrixOutputs_lo_lo_145}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_116 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_155, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_155}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_152 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_116, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_154}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_132 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_155, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_155}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_155 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_132, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_155}; // @[pla.scala:90:45, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_155 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_155, cs_decoder_decoded_andMatrixOutputs_hi_lo_152}; // @[pla.scala:98:53] wire [11:0] _cs_decoder_decoded_andMatrixOutputs_T_155 = {cs_decoder_decoded_andMatrixOutputs_hi_155, cs_decoder_decoded_andMatrixOutputs_lo_155}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_147_2 = &_cs_decoder_decoded_andMatrixOutputs_T_155; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_115 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_109, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_105}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_146 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_115, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_95}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_105 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_117, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_115}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_120 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_133, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_120}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_155 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_120, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_105}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_156 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_155, cs_decoder_decoded_andMatrixOutputs_lo_lo_146}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_95 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_153, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_146}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_117 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_156, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_155}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_153 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_117, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_95}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_109 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_156, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_156}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_133 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_156, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_156}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_156 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_133, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_109}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_156 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_156, cs_decoder_decoded_andMatrixOutputs_hi_lo_153}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_156 = {cs_decoder_decoded_andMatrixOutputs_hi_156, cs_decoder_decoded_andMatrixOutputs_lo_156}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_142_2 = &_cs_decoder_decoded_andMatrixOutputs_T_156; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_116 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_110, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_106}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_147 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_116, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_96}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_106 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_118, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_116}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_121 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_134, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_121}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_156 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_121, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_106}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_157 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_156, cs_decoder_decoded_andMatrixOutputs_lo_lo_147}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_96 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_154, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_147}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_118 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_157, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_156}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_154 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_118, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_96}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_110 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_157, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_157}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_134 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_157, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_157}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_157 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_134, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_110}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_157 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_157, cs_decoder_decoded_andMatrixOutputs_hi_lo_154}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_157 = {cs_decoder_decoded_andMatrixOutputs_hi_157, cs_decoder_decoded_andMatrixOutputs_lo_157}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_130_2 = &_cs_decoder_decoded_andMatrixOutputs_T_157; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_61 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_97, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_61}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_117 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_111, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_107}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_148 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_117, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_61}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_107 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_119, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_117}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_122 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_135, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_122}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_157 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_122, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_107}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_158 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_157, cs_decoder_decoded_andMatrixOutputs_lo_lo_148}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_97 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_155, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_148}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_119 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_158, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_157}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_155 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_119, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_97}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_111 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_158, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_158}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_135 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_158, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_158}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_158 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_135, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_111}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_158 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_158, cs_decoder_decoded_andMatrixOutputs_hi_lo_155}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_158 = {cs_decoder_decoded_andMatrixOutputs_hi_158, cs_decoder_decoded_andMatrixOutputs_lo_158}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_32_2 = &_cs_decoder_decoded_andMatrixOutputs_T_158; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_118 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_112, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_108}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_149 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_118, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_98}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_108 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_120, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_118}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_123 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_136, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_123}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_158 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_123, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_108}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_159 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_158, cs_decoder_decoded_andMatrixOutputs_lo_lo_149}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_98 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_156, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_149}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_120 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_159, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_158}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_156 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_120, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_98}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_112 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_159, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_159}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_136 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_159, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_159}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_159 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_136, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_112}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_159 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_159, cs_decoder_decoded_andMatrixOutputs_hi_lo_156}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_159 = {cs_decoder_decoded_andMatrixOutputs_hi_159, cs_decoder_decoded_andMatrixOutputs_lo_159}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_94_2 = &_cs_decoder_decoded_andMatrixOutputs_T_159; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_62 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_99, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_62}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_119 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_113, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_109}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_150 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_119, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_62}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_109 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_121, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_119}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_124 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_137, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_124}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_159 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_124, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_109}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_160 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_159, cs_decoder_decoded_andMatrixOutputs_lo_lo_150}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_99 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_157, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_150}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_121 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_160, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_159}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_157 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_121, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_99}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_113 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_160, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_160}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_137 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_160, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_160}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_160 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_137, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_113}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_160 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_160, cs_decoder_decoded_andMatrixOutputs_hi_lo_157}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_160 = {cs_decoder_decoded_andMatrixOutputs_hi_160, cs_decoder_decoded_andMatrixOutputs_lo_160}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_84_2 = &_cs_decoder_decoded_andMatrixOutputs_T_160; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_63 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_100, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_63}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_120 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_114, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_110}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_151 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_120, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_63}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_110 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_122, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_120}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_125 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_138, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_125}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_160 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_125, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_110}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_161 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_160, cs_decoder_decoded_andMatrixOutputs_lo_lo_151}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_100 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_158, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_151}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_122 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_161, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_160}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_158 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_122, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_100}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_114 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_161, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_161}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_138 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_161, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_161}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_161 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_138, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_114}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_161 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_161, cs_decoder_decoded_andMatrixOutputs_hi_lo_158}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_161 = {cs_decoder_decoded_andMatrixOutputs_hi_161, cs_decoder_decoded_andMatrixOutputs_lo_161}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_101_2 = &_cs_decoder_decoded_andMatrixOutputs_T_161; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_64 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_101, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_64}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_121 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_115, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_111}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_152 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_121, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_64}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_111 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_123, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_121}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_126 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_139, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_126}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_161 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_126, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_111}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_162 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_161, cs_decoder_decoded_andMatrixOutputs_lo_lo_152}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_101 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_159, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_152}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_123 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_162, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_161}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_159 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_123, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_101}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_115 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_162, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_162}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_139 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_162, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_162}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_162 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_139, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_115}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_162 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_162, cs_decoder_decoded_andMatrixOutputs_hi_lo_159}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_162 = {cs_decoder_decoded_andMatrixOutputs_hi_162, cs_decoder_decoded_andMatrixOutputs_lo_162}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_132_2 = &_cs_decoder_decoded_andMatrixOutputs_T_162; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_65 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_21}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_65, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_37}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_122 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_28}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_153 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_122, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_65}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_112 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_112, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_102}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_124, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_122}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_127 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_116}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_162 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_127, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_112}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_lo_163 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_162, cs_decoder_decoded_andMatrixOutputs_lo_lo_153}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_102 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_140, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_127}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_162, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_160}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_124 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_153}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_160 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_124, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_102}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_116 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_163, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_163}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_37 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_163, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_163}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_140 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_163}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_163 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_140, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_116}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_hi_163 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_163, cs_decoder_decoded_andMatrixOutputs_hi_lo_160}; // @[pla.scala:98:53] wire [19:0] _cs_decoder_decoded_andMatrixOutputs_T_163 = {cs_decoder_decoded_andMatrixOutputs_hi_163, cs_decoder_decoded_andMatrixOutputs_lo_163}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_90_2 = &_cs_decoder_decoded_andMatrixOutputs_T_163; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_66 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_22}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_38}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_123 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_29}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_154 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_123, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_66}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_113 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_113, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_103}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_125, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_123}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_128 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_117}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_163 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_128, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_113}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_lo_164 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_163, cs_decoder_decoded_andMatrixOutputs_lo_lo_154}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_103 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_141, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_128}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_163, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_161}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_125 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_154}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_161 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_125, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_103}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_117 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_164, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_164}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_38 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_164, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_164}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_141 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_164}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_164 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_141, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_117}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_hi_164 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_164, cs_decoder_decoded_andMatrixOutputs_hi_lo_161}; // @[pla.scala:98:53] wire [19:0] _cs_decoder_decoded_andMatrixOutputs_T_164 = {cs_decoder_decoded_andMatrixOutputs_hi_164, cs_decoder_decoded_andMatrixOutputs_lo_164}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_27_2 = &_cs_decoder_decoded_andMatrixOutputs_T_164; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_67 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_17}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_30}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_124 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_27}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_155 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_124, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_67}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_114 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_104, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_67}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_124, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_118}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_129 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_114}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_164 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_129, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_114}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_lo_165 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_164, cs_decoder_decoded_andMatrixOutputs_lo_lo_155}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_104 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_129, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_126}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_162, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_155}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_126 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_142}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_162 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_126, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_104}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_165, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_165}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_118 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_164}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_165, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_165}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_142 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_165}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_165 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_142, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_118}; // @[pla.scala:98:53] wire [10:0] cs_decoder_decoded_andMatrixOutputs_hi_165 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_165, cs_decoder_decoded_andMatrixOutputs_hi_lo_162}; // @[pla.scala:98:53] wire [20:0] _cs_decoder_decoded_andMatrixOutputs_T_165 = {cs_decoder_decoded_andMatrixOutputs_hi_165, cs_decoder_decoded_andMatrixOutputs_lo_165}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_148_2 = &_cs_decoder_decoded_andMatrixOutputs_T_165; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_68 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_18}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_31}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_125 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_28}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_156 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_125, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_68}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_115 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_105, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_68}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_125, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_119}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_130 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_115}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_165 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_130, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_115}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_lo_166 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_165, cs_decoder_decoded_andMatrixOutputs_lo_lo_156}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_105 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_130, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_127}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_163, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_156}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_127 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_143}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_163 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_127, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_105}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_166, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_166}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_119 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_165}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_166, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_166}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_143 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_166}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_166 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_143, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_119}; // @[pla.scala:98:53] wire [10:0] cs_decoder_decoded_andMatrixOutputs_hi_166 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_166, cs_decoder_decoded_andMatrixOutputs_hi_lo_163}; // @[pla.scala:98:53] wire [20:0] _cs_decoder_decoded_andMatrixOutputs_T_166 = {cs_decoder_decoded_andMatrixOutputs_hi_166, cs_decoder_decoded_andMatrixOutputs_lo_166}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_67_2 = &_cs_decoder_decoded_andMatrixOutputs_T_166; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_69 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_19}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_32}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_126 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_29}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_157 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_126, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_69}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_116 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_106, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_69}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_126, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_120}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_131 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_116}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_166 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_131, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_116}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_lo_167 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_166, cs_decoder_decoded_andMatrixOutputs_lo_lo_157}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_106 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_131, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_128}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_164, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_157}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_128 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_144}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_164 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_128, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_106}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_167, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_167}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_120 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_166}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_41 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_167, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_167}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_144 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_167}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_167 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_144, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_120}; // @[pla.scala:98:53] wire [10:0] cs_decoder_decoded_andMatrixOutputs_hi_167 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_167, cs_decoder_decoded_andMatrixOutputs_hi_lo_164}; // @[pla.scala:98:53] wire [20:0] _cs_decoder_decoded_andMatrixOutputs_T_167 = {cs_decoder_decoded_andMatrixOutputs_hi_167, cs_decoder_decoded_andMatrixOutputs_lo_167}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_34_2 = &_cs_decoder_decoded_andMatrixOutputs_T_167; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_70 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_20}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_42, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_127 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_30}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_158 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_127, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_70}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_117 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_107, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_70}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_127, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_121}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_132 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_117}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_167 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_132, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_117}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_lo_168 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_167, cs_decoder_decoded_andMatrixOutputs_lo_lo_158}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_107 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_132, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_129}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_165, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_158}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_129 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_145}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_165 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_129, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_107}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_168, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_168}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_121 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_167}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_42 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_168, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_168}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_145 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_42, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_168}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_168 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_145, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_121}; // @[pla.scala:98:53] wire [10:0] cs_decoder_decoded_andMatrixOutputs_hi_168 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_168, cs_decoder_decoded_andMatrixOutputs_hi_lo_165}; // @[pla.scala:98:53] wire [20:0] _cs_decoder_decoded_andMatrixOutputs_T_168 = {cs_decoder_decoded_andMatrixOutputs_hi_168, cs_decoder_decoded_andMatrixOutputs_lo_168}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_59_2 = &_cs_decoder_decoded_andMatrixOutputs_T_168; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo = {cs_decoder_decoded_andMatrixOutputs_130_2, cs_decoder_decoded_andMatrixOutputs_94_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi = {cs_decoder_decoded_andMatrixOutputs_117_2, cs_decoder_decoded_andMatrixOutputs_142_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo = {cs_decoder_decoded_orMatrixOutputs_lo_hi, cs_decoder_decoded_orMatrixOutputs_lo_lo}; // @[pla.scala:114:19] wire [1:0] _GEN = {cs_decoder_decoded_andMatrixOutputs_152_2, cs_decoder_decoded_andMatrixOutputs_98_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo = _GEN; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_2; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_2 = _GEN; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_14; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_14 = _GEN; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_18; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_18 = _GEN; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_1 = _GEN; // @[pla.scala:114:19] wire [1:0] _GEN_0 = {cs_decoder_decoded_andMatrixOutputs_157_2, cs_decoder_decoded_andMatrixOutputs_21_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi = _GEN_0; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_3; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_3 = _GEN_0; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_3; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_3 = _GEN_0; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_18; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_18 = _GEN_0; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_15; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_15 = _GEN_0; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_139_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi = {cs_decoder_decoded_orMatrixOutputs_hi_hi, cs_decoder_decoded_orMatrixOutputs_hi_lo}; // @[pla.scala:114:19] wire [8:0] _cs_decoder_decoded_orMatrixOutputs_T = {cs_decoder_decoded_orMatrixOutputs_hi, cs_decoder_decoded_orMatrixOutputs_lo}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_1 = \|_cs_decoder_decoded_orMatrixOutputs_T; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_1 = {cs_decoder_decoded_andMatrixOutputs_157_2, cs_decoder_decoded_andMatrixOutputs_145_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_1 = _GEN_1; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_27; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_27 = _GEN_1; // @[pla.scala:114:19] wire [2:0] _cs_decoder_decoded_orMatrixOutputs_T_4 = {cs_decoder_decoded_orMatrixOutputs_hi_1, cs_decoder_decoded_andMatrixOutputs_161_2}; // @[pla.scala:98:70, :114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_5 = \|_cs_decoder_decoded_orMatrixOutputs_T_4; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_2 = {cs_decoder_decoded_andMatrixOutputs_23_2, cs_decoder_decoded_andMatrixOutputs_15_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_1 = _GEN_2; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_15; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_15 = _GEN_2; // @[pla.scala:114:19] wire [1:0] _GEN_3 = {cs_decoder_decoded_andMatrixOutputs_92_2, cs_decoder_decoded_andMatrixOutputs_40_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_2; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_2 = _GEN_3; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_17; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_17 = _GEN_3; // @[pla.scala:114:19] wire [3:0] _cs_decoder_decoded_orMatrixOutputs_T_6 = {cs_decoder_decoded_orMatrixOutputs_hi_2, cs_decoder_decoded_orMatrixOutputs_lo_1}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_7 = \|_cs_decoder_decoded_orMatrixOutputs_T_6; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_4 = {cs_decoder_decoded_andMatrixOutputs_84_2, cs_decoder_decoded_andMatrixOutputs_27_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_2; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_2 = _GEN_4; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_3; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_3 = _GEN_4; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_15; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_15 = _GEN_4; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_33; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_33 = _GEN_4; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_3 = {cs_decoder_decoded_andMatrixOutputs_142_2, cs_decoder_decoded_andMatrixOutputs_130_2}; // @[pla.scala:98:70, :114:19] wire [3:0] _cs_decoder_decoded_orMatrixOutputs_T_8 = {cs_decoder_decoded_orMatrixOutputs_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_2}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_9 = \|_cs_decoder_decoded_orMatrixOutputs_T_8; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_5 = {cs_decoder_decoded_andMatrixOutputs_132_2, cs_decoder_decoded_andMatrixOutputs_59_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _cs_decoder_decoded_orMatrixOutputs_T_10; // @[pla.scala:114:19] assign _cs_decoder_decoded_orMatrixOutputs_T_10 = _GEN_5; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_17; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_17 = _GEN_5; // @[pla.scala:114:19] wire [1:0] _cs_decoder_decoded_orMatrixOutputs_T_91; // @[pla.scala:114:19] assign _cs_decoder_decoded_orMatrixOutputs_T_91 = _GEN_5; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_11 = \|_cs_decoder_decoded_orMatrixOutputs_T_10; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_34_2, cs_decoder_decoded_andMatrixOutputs_59_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi = {cs_decoder_decoded_andMatrixOutputs_98_2, cs_decoder_decoded_andMatrixOutputs_109_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_1 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_101_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_3 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_1, cs_decoder_decoded_orMatrixOutputs_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] _GEN_6 = {cs_decoder_decoded_andMatrixOutputs_11_2, cs_decoder_decoded_andMatrixOutputs_74_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_1 = _GEN_6; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_hi = _GEN_6; // @[pla.scala:114:19] wire [1:0] _GEN_7 = {cs_decoder_decoded_andMatrixOutputs_60_2, cs_decoder_decoded_andMatrixOutputs_69_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_1 = _GEN_7; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_2; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_2 = _GEN_7; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_1 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_68_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_4 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_hi_lo_1}; // @[pla.scala:114:19] wire [9:0] _cs_decoder_decoded_orMatrixOutputs_T_12 = {cs_decoder_decoded_orMatrixOutputs_hi_4, cs_decoder_decoded_orMatrixOutputs_lo_3}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_13 = \|_cs_decoder_decoded_orMatrixOutputs_T_12; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_2 = {cs_decoder_decoded_andMatrixOutputs_67_2, cs_decoder_decoded_andMatrixOutputs_34_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_109_2, cs_decoder_decoded_andMatrixOutputs_101_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_2 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_148_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_4 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_2, cs_decoder_decoded_orMatrixOutputs_lo_lo_2}; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_2 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi, cs_decoder_decoded_andMatrixOutputs_23_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_2 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_68_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_5 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_hi_lo_2}; // @[pla.scala:114:19] wire [10:0] _cs_decoder_decoded_orMatrixOutputs_T_14 = {cs_decoder_decoded_orMatrixOutputs_hi_5, cs_decoder_decoded_orMatrixOutputs_lo_4}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_15 = \|_cs_decoder_decoded_orMatrixOutputs_T_14; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_8 = {cs_decoder_decoded_andMatrixOutputs_115_2, cs_decoder_decoded_andMatrixOutputs_92_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_5; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_5 = _GEN_8; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_3; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_3 = _GEN_8; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_15; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_15 = _GEN_8; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_6 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_7_2}; // @[pla.scala:98:70, :114:19] wire [4:0] _cs_decoder_decoded_orMatrixOutputs_T_18 = {cs_decoder_decoded_orMatrixOutputs_hi_6, cs_decoder_decoded_orMatrixOutputs_lo_5}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_19 = \|_cs_decoder_decoded_orMatrixOutputs_T_18; // @[pla.scala:114:{19,36}] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_3 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_117_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_6 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_lo_3}; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_4 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_7_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_7 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_4, cs_decoder_decoded_orMatrixOutputs_hi_lo_3}; // @[pla.scala:114:19] wire [9:0] _cs_decoder_decoded_orMatrixOutputs_T_20 = {cs_decoder_decoded_orMatrixOutputs_hi_7, cs_decoder_decoded_orMatrixOutputs_lo_6}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_21 = \|_cs_decoder_decoded_orMatrixOutputs_T_20; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi = {cs_decoder_decoded_andMatrixOutputs_122_2, cs_decoder_decoded_andMatrixOutputs_41_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_4 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi, cs_decoder_decoded_andMatrixOutputs_126_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo = {cs_decoder_decoded_andMatrixOutputs_143_2, cs_decoder_decoded_andMatrixOutputs_119_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_121_2, cs_decoder_decoded_andMatrixOutputs_25_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_4 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_lo_7 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_4, cs_decoder_decoded_orMatrixOutputs_lo_lo_4}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo = {cs_decoder_decoded_andMatrixOutputs_124_2, cs_decoder_decoded_andMatrixOutputs_89_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_1 = {cs_decoder_decoded_andMatrixOutputs_75_2, cs_decoder_decoded_andMatrixOutputs_13_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_4 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_1, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo = {cs_decoder_decoded_andMatrixOutputs_86_2, cs_decoder_decoded_andMatrixOutputs_155_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_4 = {cs_decoder_decoded_andMatrixOutputs_102_2, cs_decoder_decoded_andMatrixOutputs_105_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_5 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_4, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo}; // @[pla.scala:114:19] wire [7:0] cs_decoder_decoded_orMatrixOutputs_hi_8 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_5, cs_decoder_decoded_orMatrixOutputs_hi_lo_4}; // @[pla.scala:114:19] wire [14:0] _cs_decoder_decoded_orMatrixOutputs_T_22 = {cs_decoder_decoded_orMatrixOutputs_hi_8, cs_decoder_decoded_orMatrixOutputs_lo_7}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_23 = \|_cs_decoder_decoded_orMatrixOutputs_T_22; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo = {cs_decoder_decoded_andMatrixOutputs_49_2, cs_decoder_decoded_andMatrixOutputs_122_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_1 = {cs_decoder_decoded_andMatrixOutputs_119_2, cs_decoder_decoded_andMatrixOutputs_151_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_5 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_1, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_22_2, cs_decoder_decoded_andMatrixOutputs_44_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi = {cs_decoder_decoded_andMatrixOutputs_38_2, cs_decoder_decoded_andMatrixOutputs_4_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_4 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_5_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_5 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_4, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_1}; // @[pla.scala:114:19] wire [8:0] cs_decoder_decoded_orMatrixOutputs_lo_8 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_5, cs_decoder_decoded_orMatrixOutputs_lo_lo_5}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_57_2, cs_decoder_decoded_andMatrixOutputs_137_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi = {cs_decoder_decoded_andMatrixOutputs_149_2, cs_decoder_decoded_andMatrixOutputs_144_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_2 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_30_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_5 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_2, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_136_2, cs_decoder_decoded_andMatrixOutputs_96_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi = {cs_decoder_decoded_andMatrixOutputs_140_2, cs_decoder_decoded_andMatrixOutputs_33_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_5 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_1_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_6 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_5, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_1}; // @[pla.scala:114:19] wire [9:0] cs_decoder_decoded_orMatrixOutputs_hi_9 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_6, cs_decoder_decoded_orMatrixOutputs_hi_lo_5}; // @[pla.scala:114:19] wire [18:0] _cs_decoder_decoded_orMatrixOutputs_T_24 = {cs_decoder_decoded_orMatrixOutputs_hi_9, cs_decoder_decoded_orMatrixOutputs_lo_8}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_25 = \|_cs_decoder_decoded_orMatrixOutputs_T_24; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_9 = {cs_decoder_decoded_andMatrixOutputs_156_2, cs_decoder_decoded_andMatrixOutputs_116_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_6; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_6 = _GEN_9; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi = _GEN_9; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_lo; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_lo = _GEN_9; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_5 = {cs_decoder_decoded_andMatrixOutputs_6_2, cs_decoder_decoded_andMatrixOutputs_35_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_6 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_9_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_9 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_6, cs_decoder_decoded_orMatrixOutputs_lo_lo_6}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_127_2, cs_decoder_decoded_andMatrixOutputs_135_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_6 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_3, cs_decoder_decoded_andMatrixOutputs_114_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_18_2, cs_decoder_decoded_andMatrixOutputs_113_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_7 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_39_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_10 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_7, cs_decoder_decoded_orMatrixOutputs_hi_lo_6}; // @[pla.scala:114:19] wire [10:0] _cs_decoder_decoded_orMatrixOutputs_T_26 = {cs_decoder_decoded_orMatrixOutputs_hi_10, cs_decoder_decoded_orMatrixOutputs_lo_9}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_27 = \|_cs_decoder_decoded_orMatrixOutputs_T_26; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_7 = {cs_decoder_decoded_andMatrixOutputs_46_2, cs_decoder_decoded_andMatrixOutputs_159_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_125_2, cs_decoder_decoded_andMatrixOutputs_154_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_7 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_20_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_10 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_7, cs_decoder_decoded_orMatrixOutputs_lo_lo_7}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_4 = {cs_decoder_decoded_andMatrixOutputs_135_2, cs_decoder_decoded_andMatrixOutputs_37_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_7 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_22_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_7 = {cs_decoder_decoded_andMatrixOutputs_79_2, cs_decoder_decoded_andMatrixOutputs_111_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_8 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_42_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_11 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_8, cs_decoder_decoded_orMatrixOutputs_hi_lo_7}; // @[pla.scala:114:19] wire [10:0] _cs_decoder_decoded_orMatrixOutputs_T_28 = {cs_decoder_decoded_orMatrixOutputs_hi_11, cs_decoder_decoded_orMatrixOutputs_lo_10}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_29 = \|_cs_decoder_decoded_orMatrixOutputs_T_28; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_150_2, cs_decoder_decoded_andMatrixOutputs_31_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_8 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_106_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_10 = {cs_decoder_decoded_andMatrixOutputs_91_2, cs_decoder_decoded_andMatrixOutputs_70_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_2; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_2 = _GEN_10; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi = _GEN_10; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_1 = _GEN_10; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_7 = {cs_decoder_decoded_andMatrixOutputs_87_2, cs_decoder_decoded_andMatrixOutputs_158_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_8 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_7, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_2}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_lo_11 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_8, cs_decoder_decoded_orMatrixOutputs_lo_lo_8}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_12_2, cs_decoder_decoded_andMatrixOutputs_36_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_8 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_55_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_2 = {cs_decoder_decoded_andMatrixOutputs_163_2, cs_decoder_decoded_andMatrixOutputs_24_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_8 = {cs_decoder_decoded_andMatrixOutputs_51_2, cs_decoder_decoded_andMatrixOutputs_37_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_9 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_8, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_2}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_hi_12 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_9, cs_decoder_decoded_orMatrixOutputs_hi_lo_8}; // @[pla.scala:114:19] wire [13:0] _cs_decoder_decoded_orMatrixOutputs_T_30 = {cs_decoder_decoded_orMatrixOutputs_hi_12, cs_decoder_decoded_orMatrixOutputs_lo_11}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_31 = \|_cs_decoder_decoded_orMatrixOutputs_T_30; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo = {cs_decoder_decoded_andMatrixOutputs_106_2, cs_decoder_decoded_andMatrixOutputs_78_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi = {cs_decoder_decoded_andMatrixOutputs_19_2, cs_decoder_decoded_andMatrixOutputs_53_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_1 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo = {cs_decoder_decoded_andMatrixOutputs_55_2, cs_decoder_decoded_andMatrixOutputs_128_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi = {cs_decoder_decoded_andMatrixOutputs_44_2, cs_decoder_decoded_andMatrixOutputs_36_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_3 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo}; // @[pla.scala:114:19] wire [7:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_9 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] _GEN_11 = {cs_decoder_decoded_andMatrixOutputs_116_2, cs_decoder_decoded_andMatrixOutputs_163_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo = _GEN_11; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_5; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_5 = _GEN_11; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi = {cs_decoder_decoded_andMatrixOutputs_65_2, cs_decoder_decoded_andMatrixOutputs_156_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_3 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo = {cs_decoder_decoded_andMatrixOutputs_146_2, cs_decoder_decoded_andMatrixOutputs_66_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_35_2, cs_decoder_decoded_andMatrixOutputs_51_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_8 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo}; // @[pla.scala:114:19] wire [7:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_9 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_8, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_3}; // @[pla.scala:114:19] wire [15:0] cs_decoder_decoded_orMatrixOutputs_lo_12 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_9, cs_decoder_decoded_orMatrixOutputs_lo_lo_9}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo = {cs_decoder_decoded_andMatrixOutputs_165_2, cs_decoder_decoded_andMatrixOutputs_135_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi = {cs_decoder_decoded_andMatrixOutputs_131_2, cs_decoder_decoded_andMatrixOutputs_108_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_2 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo = {cs_decoder_decoded_andMatrixOutputs_18_2, cs_decoder_decoded_andMatrixOutputs_167_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_105_2, cs_decoder_decoded_andMatrixOutputs_76_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_6 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo}; // @[pla.scala:114:19] wire [7:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_9 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_6, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] _GEN_12 = {cs_decoder_decoded_andMatrixOutputs_112_2, cs_decoder_decoded_andMatrixOutputs_138_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo = _GEN_12; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_1 = _GEN_12; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi = {cs_decoder_decoded_andMatrixOutputs_8_2, cs_decoder_decoded_andMatrixOutputs_43_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_3 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo = {cs_decoder_decoded_andMatrixOutputs_29_2, cs_decoder_decoded_andMatrixOutputs_61_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_100_2, cs_decoder_decoded_andMatrixOutputs_62_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_9 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:114:19] wire [7:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_10 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_9, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_3}; // @[pla.scala:114:19] wire [15:0] cs_decoder_decoded_orMatrixOutputs_hi_13 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_10, cs_decoder_decoded_orMatrixOutputs_hi_lo_9}; // @[pla.scala:114:19] wire [31:0] _cs_decoder_decoded_orMatrixOutputs_T_32 = {cs_decoder_decoded_orMatrixOutputs_hi_13, cs_decoder_decoded_orMatrixOutputs_lo_12}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_33 = \|_cs_decoder_decoded_orMatrixOutputs_T_32; // @[pla.scala:114:{19,36}] wire [1:0] _cs_decoder_decoded_orMatrixOutputs_T_35 = {cs_decoder_decoded_andMatrixOutputs_131_2, cs_decoder_decoded_andMatrixOutputs_16_2}; // @[pla.scala:98:70, :114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_36 = \|_cs_decoder_decoded_orMatrixOutputs_T_35; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_10 = {cs_decoder_decoded_andMatrixOutputs_50_2, cs_decoder_decoded_andMatrixOutputs_134_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_13 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_10, cs_decoder_decoded_andMatrixOutputs_64_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_13 = {cs_decoder_decoded_andMatrixOutputs_47_2, cs_decoder_decoded_andMatrixOutputs_160_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_11; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_11 = _GEN_13; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_26; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_26 = _GEN_13; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_14 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_11, cs_decoder_decoded_andMatrixOutputs_131_2}; // @[pla.scala:98:70, :114:19] wire [5:0] _cs_decoder_decoded_orMatrixOutputs_T_37 = {cs_decoder_decoded_orMatrixOutputs_hi_14, cs_decoder_decoded_orMatrixOutputs_lo_13}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_38 = \|_cs_decoder_decoded_orMatrixOutputs_T_37; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_10 = {cs_decoder_decoded_andMatrixOutputs_65_2, cs_decoder_decoded_andMatrixOutputs_64_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_14 = {cs_decoder_decoded_andMatrixOutputs_118_2, cs_decoder_decoded_andMatrixOutputs_50_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_9; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_9 = _GEN_14; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_1 = _GEN_14; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_11 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_134_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_14 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_11, cs_decoder_decoded_orMatrixOutputs_lo_lo_10}; // @[pla.scala:114:19] wire [1:0] _GEN_15 = {cs_decoder_decoded_andMatrixOutputs_17_2, cs_decoder_decoded_andMatrixOutputs_131_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_7; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_7 = _GEN_15; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_8; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_8 = _GEN_15; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_10 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_99_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_10 = {cs_decoder_decoded_andMatrixOutputs_100_2, cs_decoder_decoded_andMatrixOutputs_47_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_12 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_160_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_15 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_12, cs_decoder_decoded_orMatrixOutputs_hi_lo_10}; // @[pla.scala:114:19] wire [10:0] _cs_decoder_decoded_orMatrixOutputs_T_39 = {cs_decoder_decoded_orMatrixOutputs_hi_15, cs_decoder_decoded_orMatrixOutputs_lo_14}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_40 = \|_cs_decoder_decoded_orMatrixOutputs_T_39; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_11 = {cs_decoder_decoded_andMatrixOutputs_95_2, cs_decoder_decoded_andMatrixOutputs_103_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_16 = {cs_decoder_decoded_andMatrixOutputs_58_2, cs_decoder_decoded_andMatrixOutputs_129_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_10; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_10 = _GEN_16; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_1 = _GEN_16; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_12 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_97_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_15 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_12, cs_decoder_decoded_orMatrixOutputs_lo_lo_11}; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_11 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_8, cs_decoder_decoded_andMatrixOutputs_99_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_11 = {cs_decoder_decoded_andMatrixOutputs_100_2, cs_decoder_decoded_andMatrixOutputs_71_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_13 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_11, cs_decoder_decoded_andMatrixOutputs_160_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_16 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_13, cs_decoder_decoded_orMatrixOutputs_hi_lo_11}; // @[pla.scala:114:19] wire [10:0] _cs_decoder_decoded_orMatrixOutputs_T_41 = {cs_decoder_decoded_orMatrixOutputs_hi_16, cs_decoder_decoded_orMatrixOutputs_lo_15}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_42 = \|_cs_decoder_decoded_orMatrixOutputs_T_41; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_16 = {cs_decoder_decoded_andMatrixOutputs_54_2, cs_decoder_decoded_andMatrixOutputs_63_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_17 = {cs_decoder_decoded_andMatrixOutputs_110_2, cs_decoder_decoded_andMatrixOutputs_153_2}; // @[pla.scala:98:70, :114:19] wire [3:0] _cs_decoder_decoded_orMatrixOutputs_T_43 = {cs_decoder_decoded_orMatrixOutputs_hi_17, cs_decoder_decoded_orMatrixOutputs_lo_16}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_44 = \|_cs_decoder_decoded_orMatrixOutputs_T_43; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_18 = {cs_decoder_decoded_andMatrixOutputs_118_2, cs_decoder_decoded_andMatrixOutputs_54_2}; // @[pla.scala:98:70, :114:19] wire [2:0] _cs_decoder_decoded_orMatrixOutputs_T_45 = {cs_decoder_decoded_orMatrixOutputs_hi_18, cs_decoder_decoded_andMatrixOutputs_48_2}; // @[pla.scala:98:70, :114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_46 = \|_cs_decoder_decoded_orMatrixOutputs_T_45; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_17 = {cs_decoder_decoded_andMatrixOutputs_65_2, cs_decoder_decoded_andMatrixOutputs_147_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_19 = {cs_decoder_decoded_andMatrixOutputs_99_2, cs_decoder_decoded_andMatrixOutputs_118_2}; // @[pla.scala:98:70, :114:19] wire [3:0] _cs_decoder_decoded_orMatrixOutputs_T_47 = {cs_decoder_decoded_orMatrixOutputs_hi_19, cs_decoder_decoded_orMatrixOutputs_lo_17}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_48 = \|_cs_decoder_decoded_orMatrixOutputs_T_47; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_17 = {cs_decoder_decoded_andMatrixOutputs_17_2, cs_decoder_decoded_andMatrixOutputs_99_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _cs_decoder_decoded_orMatrixOutputs_T_51; // @[pla.scala:114:19] assign _cs_decoder_decoded_orMatrixOutputs_T_51 = _GEN_17; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_18; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_18 = _GEN_17; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_23; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_23 = _GEN_17; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_52 = \|_cs_decoder_decoded_orMatrixOutputs_T_51; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_14 = {cs_decoder_decoded_andMatrixOutputs_88_2, cs_decoder_decoded_andMatrixOutputs_110_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_20 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_153_2}; // @[pla.scala:98:70, :114:19] wire [4:0] _cs_decoder_decoded_orMatrixOutputs_T_53 = {cs_decoder_decoded_orMatrixOutputs_hi_20, cs_decoder_decoded_orMatrixOutputs_lo_18}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_54 = \|_cs_decoder_decoded_orMatrixOutputs_T_53; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_19 = {cs_decoder_decoded_andMatrixOutputs_45_2, cs_decoder_decoded_andMatrixOutputs_118_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_18 = {cs_decoder_decoded_andMatrixOutputs_85_2, cs_decoder_decoded_andMatrixOutputs_10_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_21; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_21 = _GEN_18; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_25; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_25 = _GEN_18; // @[pla.scala:114:19] wire [3:0] _cs_decoder_decoded_orMatrixOutputs_T_55 = {cs_decoder_decoded_orMatrixOutputs_hi_21, cs_decoder_decoded_orMatrixOutputs_lo_19}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_56 = \|_cs_decoder_decoded_orMatrixOutputs_T_55; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_13 = {cs_decoder_decoded_andMatrixOutputs_164_2, cs_decoder_decoded_andMatrixOutputs_133_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_20 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_13, cs_decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_15 = {cs_decoder_decoded_andMatrixOutputs_29_2, cs_decoder_decoded_andMatrixOutputs_110_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_22 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_153_2}; // @[pla.scala:98:70, :114:19] wire [5:0] _cs_decoder_decoded_orMatrixOutputs_T_57 = {cs_decoder_decoded_orMatrixOutputs_hi_22, cs_decoder_decoded_orMatrixOutputs_lo_20}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_58 = \|_cs_decoder_decoded_orMatrixOutputs_T_57; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_19 = {cs_decoder_decoded_andMatrixOutputs_106_2, cs_decoder_decoded_andMatrixOutputs_103_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_1 = _GEN_19; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_2; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_2 = _GEN_19; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_lo; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_lo = _GEN_19; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_2 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_132_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_20 = {cs_decoder_decoded_andMatrixOutputs_158_2, cs_decoder_decoded_andMatrixOutputs_91_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_1 = _GEN_20; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_2; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_2 = _GEN_20; // @[pla.scala:114:19] wire [1:0] _GEN_21 = {cs_decoder_decoded_andMatrixOutputs_36_2, cs_decoder_decoded_andMatrixOutputs_87_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_1 = _GEN_21; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_2; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_2 = _GEN_21; // @[pla.scala:114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_4 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_1}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_12 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_4, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] _GEN_22 = {cs_decoder_decoded_andMatrixOutputs_163_2, cs_decoder_decoded_andMatrixOutputs_44_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_1 = _GEN_22; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_2; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_2 = _GEN_22; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_3; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_3 = _GEN_22; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_1 = _GEN_22; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_4 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_104_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_23 = {cs_decoder_decoded_andMatrixOutputs_97_2, cs_decoder_decoded_andMatrixOutputs_156_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_1 = _GEN_23; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_2; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_2 = _GEN_23; // @[pla.scala:114:19] wire [1:0] _GEN_24 = {cs_decoder_decoded_andMatrixOutputs_51_2, cs_decoder_decoded_andMatrixOutputs_129_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_2; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_2 = _GEN_24; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_3; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_3 = _GEN_24; // @[pla.scala:114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_11 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_1}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_14 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_11, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_4}; // @[pla.scala:114:19] wire [13:0] cs_decoder_decoded_orMatrixOutputs_lo_21 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_14, cs_decoder_decoded_orMatrixOutputs_lo_lo_12}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_1 = {cs_decoder_decoded_andMatrixOutputs_18_2, cs_decoder_decoded_andMatrixOutputs_131_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_3 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_25_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_160_2, cs_decoder_decoded_andMatrixOutputs_120_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_2 = {cs_decoder_decoded_andMatrixOutputs_52_2, cs_decoder_decoded_andMatrixOutputs_0_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_9 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_1}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_12 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_9, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] _GEN_25 = {cs_decoder_decoded_andMatrixOutputs_168_2, cs_decoder_decoded_andMatrixOutputs_138_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_1 = _GEN_25; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_3; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_3 = _GEN_25; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi = _GEN_25; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_4 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_71_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_26 = {cs_decoder_decoded_andMatrixOutputs_26_2, cs_decoder_decoded_andMatrixOutputs_77_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_1 = _GEN_26; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_2; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_2 = _GEN_26; // @[pla.scala:114:19] wire [1:0] _GEN_27 = {cs_decoder_decoded_andMatrixOutputs_81_2, cs_decoder_decoded_andMatrixOutputs_10_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_2; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_2 = _GEN_27; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_3; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_3 = _GEN_27; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi = _GEN_27; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_1 = _GEN_27; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_2; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_2 = _GEN_27; // @[pla.scala:114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_12 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_1}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_16 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_12, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_4}; // @[pla.scala:114:19] wire [13:0] cs_decoder_decoded_orMatrixOutputs_hi_23 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_16, cs_decoder_decoded_orMatrixOutputs_hi_lo_12}; // @[pla.scala:114:19] wire [27:0] _cs_decoder_decoded_orMatrixOutputs_T_59 = {cs_decoder_decoded_orMatrixOutputs_hi_23, cs_decoder_decoded_orMatrixOutputs_lo_21}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_60 = \|_cs_decoder_decoded_orMatrixOutputs_T_59; // @[pla.scala:114:{19,36}] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_3 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_132_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_5 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_2}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_13 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_5, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_3}; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_5 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_104_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_12 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_2}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_15 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_12, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_5}; // @[pla.scala:114:19] wire [13:0] cs_decoder_decoded_orMatrixOutputs_lo_22 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_15, cs_decoder_decoded_orMatrixOutputs_lo_lo_13}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_131_2, cs_decoder_decoded_andMatrixOutputs_135_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_4 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_25_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_2 = {cs_decoder_decoded_andMatrixOutputs_120_2, cs_decoder_decoded_andMatrixOutputs_18_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_0_2, cs_decoder_decoded_andMatrixOutputs_76_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_10 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_3, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_2}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_13 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_10, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_4}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_71_2, cs_decoder_decoded_andMatrixOutputs_52_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_29_2, cs_decoder_decoded_andMatrixOutputs_112_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_5 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_2, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_1}; // @[pla.scala:114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_13 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_3, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_2}; // @[pla.scala:114:19] wire [7:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_17 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_13, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_5}; // @[pla.scala:114:19] wire [14:0] cs_decoder_decoded_orMatrixOutputs_hi_24 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_17, cs_decoder_decoded_orMatrixOutputs_hi_lo_13}; // @[pla.scala:114:19] wire [28:0] _cs_decoder_decoded_orMatrixOutputs_T_61 = {cs_decoder_decoded_orMatrixOutputs_hi_24, cs_decoder_decoded_orMatrixOutputs_lo_22}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_62 = \|_cs_decoder_decoded_orMatrixOutputs_T_61; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_28 = {cs_decoder_decoded_andMatrixOutputs_7_2, cs_decoder_decoded_andMatrixOutputs_115_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_16; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_16 = _GEN_28; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_14; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_14 = _GEN_28; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_1 = _GEN_28; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_23 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_16, cs_decoder_decoded_andMatrixOutputs_92_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_25 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_18, cs_decoder_decoded_andMatrixOutputs_107_2}; // @[pla.scala:98:70, :114:19] wire [5:0] _cs_decoder_decoded_orMatrixOutputs_T_64 = {cs_decoder_decoded_orMatrixOutputs_hi_25, cs_decoder_decoded_orMatrixOutputs_lo_23}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_65 = \|_cs_decoder_decoded_orMatrixOutputs_T_64; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_32_2, cs_decoder_decoded_andMatrixOutputs_94_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_106_2, cs_decoder_decoded_andMatrixOutputs_64_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_4 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_2_2, cs_decoder_decoded_andMatrixOutputs_83_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_117_2, cs_decoder_decoded_andMatrixOutputs_128_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_6 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_3}; // @[pla.scala:114:19] wire [7:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_14 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_6, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_4}; // @[pla.scala:114:19] wire [1:0] _GEN_29 = {cs_decoder_decoded_andMatrixOutputs_98_2, cs_decoder_decoded_andMatrixOutputs_36_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_1 = _GEN_29; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi = _GEN_29; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_104_2, cs_decoder_decoded_andMatrixOutputs_152_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_6 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_4 = {cs_decoder_decoded_andMatrixOutputs_134_2, cs_decoder_decoded_andMatrixOutputs_156_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_13 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_4, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_3}; // @[pla.scala:114:19] wire [7:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_17 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_13, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_6}; // @[pla.scala:114:19] wire [15:0] cs_decoder_decoded_orMatrixOutputs_lo_24 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_17, cs_decoder_decoded_orMatrixOutputs_lo_lo_14}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_131_2, cs_decoder_decoded_andMatrixOutputs_51_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_5 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_3, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_45_2, cs_decoder_decoded_andMatrixOutputs_18_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_4 = {cs_decoder_decoded_andMatrixOutputs_0_2, cs_decoder_decoded_andMatrixOutputs_160_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_11 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_4, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_3}; // @[pla.scala:114:19] wire [7:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_14 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_11, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_5}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_2 = {cs_decoder_decoded_andMatrixOutputs_47_2, cs_decoder_decoded_andMatrixOutputs_52_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_6 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_3, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] _GEN_30 = {cs_decoder_decoded_andMatrixOutputs_77_2, cs_decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_3; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_3 = _GEN_30; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_lo; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_lo = _GEN_30; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_1 = _GEN_30; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_4 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_100_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_14 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_4, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_3}; // @[pla.scala:114:19] wire [8:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_19 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_14, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_6}; // @[pla.scala:114:19] wire [16:0] cs_decoder_decoded_orMatrixOutputs_hi_26 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_19, cs_decoder_decoded_orMatrixOutputs_hi_lo_14}; // @[pla.scala:114:19] wire [32:0] _cs_decoder_decoded_orMatrixOutputs_T_66 = {cs_decoder_decoded_orMatrixOutputs_hi_26, cs_decoder_decoded_orMatrixOutputs_lo_24}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_67 = \|_cs_decoder_decoded_orMatrixOutputs_T_66; // @[pla.scala:114:{19,36}] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_18 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_117_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_25 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_18, cs_decoder_decoded_orMatrixOutputs_lo_lo_15}; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_20 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_7_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_27 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_20, cs_decoder_decoded_orMatrixOutputs_hi_lo_15}; // @[pla.scala:114:19] wire [9:0] _cs_decoder_decoded_orMatrixOutputs_T_68 = {cs_decoder_decoded_orMatrixOutputs_hi_27, cs_decoder_decoded_orMatrixOutputs_lo_25}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_69 = \|_cs_decoder_decoded_orMatrixOutputs_T_68; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_16 = {cs_decoder_decoded_andMatrixOutputs_134_2, cs_decoder_decoded_andMatrixOutputs_64_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_19 = {cs_decoder_decoded_andMatrixOutputs_3_2, cs_decoder_decoded_andMatrixOutputs_50_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_26 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_19, cs_decoder_decoded_orMatrixOutputs_lo_lo_16}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_16 = {cs_decoder_decoded_andMatrixOutputs_47_2, cs_decoder_decoded_andMatrixOutputs_72_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_16 = {cs_decoder_decoded_andMatrixOutputs_100_2, cs_decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_21 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_16, cs_decoder_decoded_andMatrixOutputs_138_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_28 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_21, cs_decoder_decoded_orMatrixOutputs_hi_lo_16}; // @[pla.scala:114:19] wire [8:0] _cs_decoder_decoded_orMatrixOutputs_T_70 = {cs_decoder_decoded_orMatrixOutputs_hi_28, cs_decoder_decoded_orMatrixOutputs_lo_26}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_71 = \|_cs_decoder_decoded_orMatrixOutputs_T_70; // @[pla.scala:114:{19,36}] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_20 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_117_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_27 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_20, cs_decoder_decoded_orMatrixOutputs_lo_lo_17}; // @[pla.scala:114:19] wire [1:0] _GEN_31 = {cs_decoder_decoded_andMatrixOutputs_123_2, cs_decoder_decoded_andMatrixOutputs_21_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_17; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_17 = _GEN_31; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_20; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_20 = _GEN_31; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_lo; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_lo = _GEN_31; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_22 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_17, cs_decoder_decoded_andMatrixOutputs_73_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_29 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_22, cs_decoder_decoded_orMatrixOutputs_hi_lo_17}; // @[pla.scala:114:19] wire [9:0] _cs_decoder_decoded_orMatrixOutputs_T_72 = {cs_decoder_decoded_orMatrixOutputs_hi_29, cs_decoder_decoded_orMatrixOutputs_lo_27}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_73 = \|_cs_decoder_decoded_orMatrixOutputs_T_72; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_32 = {cs_decoder_decoded_andMatrixOutputs_94_2, cs_decoder_decoded_andMatrixOutputs_90_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi = _GEN_32; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_9; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_9 = _GEN_32; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_1 = _GEN_32; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_2 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi, cs_decoder_decoded_andMatrixOutputs_27_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_4 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_106_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_5 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_4, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] _GEN_33 = {cs_decoder_decoded_andMatrixOutputs_117_2, cs_decoder_decoded_andMatrixOutputs_87_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi = _GEN_33; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_1 = _GEN_33; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_4 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi, cs_decoder_decoded_andMatrixOutputs_158_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_4 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_55_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_7 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_4, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_4}; // @[pla.scala:114:19] wire [11:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_18 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_7, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_5}; // @[pla.scala:114:19] wire [1:0] _GEN_34 = {cs_decoder_decoded_andMatrixOutputs_44_2, cs_decoder_decoded_andMatrixOutputs_151_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi = _GEN_34; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_3; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_3 = _GEN_34; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_2 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi, cs_decoder_decoded_andMatrixOutputs_152_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_4 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_163_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_7 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_4, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi = {cs_decoder_decoded_andMatrixOutputs_92_2, cs_decoder_decoded_andMatrixOutputs_133_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_4 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi, cs_decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi = {cs_decoder_decoded_andMatrixOutputs_58_2, cs_decoder_decoded_andMatrixOutputs_7_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_5 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_115_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_16 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_5, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_4}; // @[pla.scala:114:19] wire [11:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_21 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_16, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_7}; // @[pla.scala:114:19] wire [23:0] cs_decoder_decoded_orMatrixOutputs_lo_28 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_21, cs_decoder_decoded_orMatrixOutputs_lo_lo_18}; // @[pla.scala:114:19] wire [1:0] _GEN_35 = {cs_decoder_decoded_andMatrixOutputs_25_2, cs_decoder_decoded_andMatrixOutputs_99_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi = _GEN_35; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_1 = _GEN_35; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_2 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi, cs_decoder_decoded_andMatrixOutputs_51_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi = {cs_decoder_decoded_andMatrixOutputs_108_2, cs_decoder_decoded_andMatrixOutputs_35_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_4 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_9_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_6 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_4, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] _GEN_36 = {cs_decoder_decoded_andMatrixOutputs_18_2, cs_decoder_decoded_andMatrixOutputs_17_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi = _GEN_36; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_1 = _GEN_36; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_4 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi, cs_decoder_decoded_andMatrixOutputs_131_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi = {cs_decoder_decoded_andMatrixOutputs_86_2, cs_decoder_decoded_andMatrixOutputs_160_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_5 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_45_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_12 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_5, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_4}; // @[pla.scala:114:19] wire [11:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_18 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_12, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_6}; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_3 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi, cs_decoder_decoded_andMatrixOutputs_105_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi = {cs_decoder_decoded_andMatrixOutputs_56_2, cs_decoder_decoded_andMatrixOutputs_123_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_4 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_21_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_7 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_4, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] _GEN_37 = {cs_decoder_decoded_andMatrixOutputs_166_2, cs_decoder_decoded_andMatrixOutputs_8_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi = _GEN_37; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_lo; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_lo = _GEN_37; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_4 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi, cs_decoder_decoded_andMatrixOutputs_80_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_5 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_lo}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_18 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_5, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_4}; // @[pla.scala:114:19] wire [12:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_23 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_18, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_7}; // @[pla.scala:114:19] wire [24:0] cs_decoder_decoded_orMatrixOutputs_hi_30 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_23, cs_decoder_decoded_orMatrixOutputs_hi_lo_18}; // @[pla.scala:114:19] wire [48:0] _cs_decoder_decoded_orMatrixOutputs_T_74 = {cs_decoder_decoded_orMatrixOutputs_hi_30, cs_decoder_decoded_orMatrixOutputs_lo_28}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_75 = \|_cs_decoder_decoded_orMatrixOutputs_T_74; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_83_2, cs_decoder_decoded_andMatrixOutputs_70_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_6 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_106_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_5 = {cs_decoder_decoded_andMatrixOutputs_128_2, cs_decoder_decoded_andMatrixOutputs_2_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_38 = {cs_decoder_decoded_andMatrixOutputs_36_2, cs_decoder_decoded_andMatrixOutputs_55_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_5; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_5 = _GEN_38; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_lo; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_lo = _GEN_38; // @[pla.scala:114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_8 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_5, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_5}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_19 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_8, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_6}; // @[pla.scala:114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_8 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_5, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_5 = {cs_decoder_decoded_andMatrixOutputs_28_2, cs_decoder_decoded_andMatrixOutputs_156_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_37_2, cs_decoder_decoded_andMatrixOutputs_133_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_17 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_6, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_5}; // @[pla.scala:114:19] wire [7:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_22 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_17, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_8}; // @[pla.scala:114:19] wire [14:0] cs_decoder_decoded_orMatrixOutputs_lo_29 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_22, cs_decoder_decoded_orMatrixOutputs_lo_lo_19}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_3 = {cs_decoder_decoded_andMatrixOutputs_25_2, cs_decoder_decoded_andMatrixOutputs_51_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_39 = {cs_decoder_decoded_andMatrixOutputs_108_2, cs_decoder_decoded_andMatrixOutputs_135_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_5; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_5 = _GEN_39; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_1 = _GEN_39; // @[pla.scala:114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_7 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_5, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_5 = {cs_decoder_decoded_andMatrixOutputs_86_2, cs_decoder_decoded_andMatrixOutputs_18_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_138_2, cs_decoder_decoded_andMatrixOutputs_52_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_13 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_6, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_5}; // @[pla.scala:114:19] wire [7:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_19 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_13, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_7}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_4 = {cs_decoder_decoded_andMatrixOutputs_79_2, cs_decoder_decoded_andMatrixOutputs_112_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_14_2, cs_decoder_decoded_andMatrixOutputs_56_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_8 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_5, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_4}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_5 = {cs_decoder_decoded_andMatrixOutputs_29_2, cs_decoder_decoded_andMatrixOutputs_166_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_62_2, cs_decoder_decoded_andMatrixOutputs_77_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_19 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_6, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_5}; // @[pla.scala:114:19] wire [7:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_24 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_19, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_8}; // @[pla.scala:114:19] wire [15:0] cs_decoder_decoded_orMatrixOutputs_hi_31 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_24, cs_decoder_decoded_orMatrixOutputs_hi_lo_19}; // @[pla.scala:114:19] wire [30:0] _cs_decoder_decoded_orMatrixOutputs_T_76 = {cs_decoder_decoded_orMatrixOutputs_hi_31, cs_decoder_decoded_orMatrixOutputs_lo_29}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_77 = \|_cs_decoder_decoded_orMatrixOutputs_T_76; // @[pla.scala:114:{19,36}] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_30 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_23, cs_decoder_decoded_andMatrixOutputs_118_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_20 = {cs_decoder_decoded_andMatrixOutputs_26_2, cs_decoder_decoded_andMatrixOutputs_120_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_32 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_25, cs_decoder_decoded_orMatrixOutputs_hi_lo_20}; // @[pla.scala:114:19] wire [6:0] _cs_decoder_decoded_orMatrixOutputs_T_78 = {cs_decoder_decoded_orMatrixOutputs_hi_32, cs_decoder_decoded_orMatrixOutputs_lo_30}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_79 = \|_cs_decoder_decoded_orMatrixOutputs_T_78; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_33 = {cs_decoder_decoded_andMatrixOutputs_110_2, cs_decoder_decoded_andMatrixOutputs_17_2}; // @[pla.scala:98:70, :114:19] wire [2:0] _cs_decoder_decoded_orMatrixOutputs_T_80 = {cs_decoder_decoded_orMatrixOutputs_hi_33, cs_decoder_decoded_andMatrixOutputs_99_2}; // @[pla.scala:98:70, :114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_81 = \|_cs_decoder_decoded_orMatrixOutputs_T_80; // @[pla.scala:114:{19,36}] wire [1:0] _cs_decoder_decoded_orMatrixOutputs_T_82 = {cs_decoder_decoded_andMatrixOutputs_141_2, cs_decoder_decoded_andMatrixOutputs_93_2}; // @[pla.scala:98:70, :114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_83 = \|_cs_decoder_decoded_orMatrixOutputs_T_82; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_24 = {cs_decoder_decoded_andMatrixOutputs_134_2, cs_decoder_decoded_andMatrixOutputs_65_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_31 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_24, cs_decoder_decoded_andMatrixOutputs_64_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_21 = {cs_decoder_decoded_andMatrixOutputs_131_2, cs_decoder_decoded_andMatrixOutputs_50_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_34 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_26, cs_decoder_decoded_orMatrixOutputs_hi_lo_21}; // @[pla.scala:114:19] wire [6:0] _cs_decoder_decoded_orMatrixOutputs_T_85 = {cs_decoder_decoded_orMatrixOutputs_hi_34, cs_decoder_decoded_orMatrixOutputs_lo_31}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_86 = \|_cs_decoder_decoded_orMatrixOutputs_T_85; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_25 = {cs_decoder_decoded_andMatrixOutputs_40_2, cs_decoder_decoded_andMatrixOutputs_23_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_32 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_25, cs_decoder_decoded_andMatrixOutputs_15_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_22 = {cs_decoder_decoded_andMatrixOutputs_161_2, cs_decoder_decoded_andMatrixOutputs_92_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_35 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_27, cs_decoder_decoded_orMatrixOutputs_hi_lo_22}; // @[pla.scala:114:19] wire [6:0] _cs_decoder_decoded_orMatrixOutputs_T_87 = {cs_decoder_decoded_orMatrixOutputs_hi_35, cs_decoder_decoded_orMatrixOutputs_lo_32}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_88 = \|_cs_decoder_decoded_orMatrixOutputs_T_87; // @[pla.scala:114:{19,36}] wire [1:0] _cs_decoder_decoded_orMatrixOutputs_T_89 = {cs_decoder_decoded_andMatrixOutputs_82_2, cs_decoder_decoded_andMatrixOutputs_117_2}; // @[pla.scala:98:70, :114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_90 = \|_cs_decoder_decoded_orMatrixOutputs_T_89; // @[pla.scala:114:{19,36}] wire _cs_decoder_decoded_orMatrixOutputs_T_92 = \|_cs_decoder_decoded_orMatrixOutputs_T_91; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_28 = {cs_decoder_decoded_andMatrixOutputs_107_2, cs_decoder_decoded_andMatrixOutputs_142_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_36 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_28, cs_decoder_decoded_andMatrixOutputs_130_2}; // @[pla.scala:98:70, :114:19] wire [4:0] _cs_decoder_decoded_orMatrixOutputs_T_93 = {cs_decoder_decoded_orMatrixOutputs_hi_36, cs_decoder_decoded_orMatrixOutputs_lo_33}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_94 = \|_cs_decoder_decoded_orMatrixOutputs_T_93; // @[pla.scala:114:{19,36}] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_20 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_9, cs_decoder_decoded_andMatrixOutputs_27_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_26 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_18, cs_decoder_decoded_andMatrixOutputs_117_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_lo_34 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_26, cs_decoder_decoded_orMatrixOutputs_lo_lo_20}; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_23 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_14, cs_decoder_decoded_andMatrixOutputs_92_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_29 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_20, cs_decoder_decoded_andMatrixOutputs_162_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_37 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_29, cs_decoder_decoded_orMatrixOutputs_hi_lo_23}; // @[pla.scala:114:19] wire [11:0] _cs_decoder_decoded_orMatrixOutputs_T_95 = {cs_decoder_decoded_orMatrixOutputs_hi_37, cs_decoder_decoded_orMatrixOutputs_lo_34}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_96 = \|_cs_decoder_decoded_orMatrixOutputs_T_95; // @[pla.scala:114:{19,36}] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_3 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_27_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_6 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_lo}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_7 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_6, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_3}; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_6 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_158_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_6 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_lo}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_10 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_6, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_6}; // @[pla.scala:114:19] wire [13:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_21 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_10, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_7}; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_4 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_151_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_133_2, cs_decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_6 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_lo}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_9 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_6, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_4}; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_6 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_92_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_lo = {cs_decoder_decoded_andMatrixOutputs_97_2, cs_decoder_decoded_andMatrixOutputs_95_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_7 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_lo}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_19 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_7, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_6}; // @[pla.scala:114:19] wire [13:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_27 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_19, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_9}; // @[pla.scala:114:19] wire [27:0] cs_decoder_decoded_orMatrixOutputs_lo_35 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_27, cs_decoder_decoded_orMatrixOutputs_lo_lo_21}; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_4 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_51_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_lo = {cs_decoder_decoded_andMatrixOutputs_35_2, cs_decoder_decoded_andMatrixOutputs_9_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_6 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_lo}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_8 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_6, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_4}; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_6 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_131_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_lo = {cs_decoder_decoded_andMatrixOutputs_76_2, cs_decoder_decoded_andMatrixOutputs_120_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_105_2, cs_decoder_decoded_andMatrixOutputs_86_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_7 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_lo}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_15 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_7, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_6}; // @[pla.scala:114:19] wire [13:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_24 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_15, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_8}; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_5 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_71_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_80_2, cs_decoder_decoded_andMatrixOutputs_56_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_6 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_lo}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_9 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_6, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_5}; // @[pla.scala:114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_6 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_1, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_lo}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_26_2, cs_decoder_decoded_andMatrixOutputs_100_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_7 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_1}; // @[pla.scala:114:19] wire [7:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_21 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_7, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_6}; // @[pla.scala:114:19] wire [14:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_30 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_21, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_9}; // @[pla.scala:114:19] wire [28:0] cs_decoder_decoded_orMatrixOutputs_hi_38 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_30, cs_decoder_decoded_orMatrixOutputs_hi_lo_24}; // @[pla.scala:114:19] wire [56:0] _cs_decoder_decoded_orMatrixOutputs_T_97 = {cs_decoder_decoded_orMatrixOutputs_hi_38, cs_decoder_decoded_orMatrixOutputs_lo_35}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_98 = \|_cs_decoder_decoded_orMatrixOutputs_T_97; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_2 = {_cs_decoder_decoded_orMatrixOutputs_T_3, _cs_decoder_decoded_orMatrixOutputs_T_2}; // @[pla.scala:102:36, :114:36] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_4 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_2, _cs_decoder_decoded_orMatrixOutputs_T_1}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_1 = {_cs_decoder_decoded_orMatrixOutputs_T_7, _cs_decoder_decoded_orMatrixOutputs_T_5}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_2 = {_cs_decoder_decoded_orMatrixOutputs_T_11, _cs_decoder_decoded_orMatrixOutputs_T_9}; // @[pla.scala:102:36, :114:36] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_7 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_1}; // @[pla.scala:102:36] wire [6:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_8 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_7, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_4}; // @[pla.scala:102:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_2 = {_cs_decoder_decoded_orMatrixOutputs_T_16, _cs_decoder_decoded_orMatrixOutputs_T_15}; // @[pla.scala:102:36, :114:36] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_7 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_2, _cs_decoder_decoded_orMatrixOutputs_T_13}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_1 = {_cs_decoder_decoded_orMatrixOutputs_T_17, 1'h0}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_2 = {_cs_decoder_decoded_orMatrixOutputs_T_21, _cs_decoder_decoded_orMatrixOutputs_T_19}; // @[pla.scala:102:36, :114:36] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_7 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_1}; // @[pla.scala:102:36] wire [6:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_11 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_7, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_7}; // @[pla.scala:102:36] wire [13:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_22 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_11, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_8}; // @[pla.scala:102:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_2 = {_cs_decoder_decoded_orMatrixOutputs_T_23, 1'h0}; // @[pla.scala:102:36, :114:36] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_5 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_2, 1'h0}; // @[pla.scala:102:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_1 = {_cs_decoder_decoded_orMatrixOutputs_T_27, _cs_decoder_decoded_orMatrixOutputs_T_25}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_2 = {_cs_decoder_decoded_orMatrixOutputs_T_31, _cs_decoder_decoded_orMatrixOutputs_T_29}; // @[pla.scala:102:36, :114:36] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_7 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_1}; // @[pla.scala:102:36] wire [6:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_10 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_7, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_5}; // @[pla.scala:102:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_2 = {_cs_decoder_decoded_orMatrixOutputs_T_36, _cs_decoder_decoded_orMatrixOutputs_T_34}; // @[pla.scala:102:36, :114:36] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_7 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_2, _cs_decoder_decoded_orMatrixOutputs_T_33}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_1 = {_cs_decoder_decoded_orMatrixOutputs_T_40, _cs_decoder_decoded_orMatrixOutputs_T_38}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_2 = {_cs_decoder_decoded_orMatrixOutputs_T_44, _cs_decoder_decoded_orMatrixOutputs_T_42}; // @[pla.scala:102:36, :114:36] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_8 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_1}; // @[pla.scala:102:36] wire [6:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_20 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_8, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_7}; // @[pla.scala:102:36] wire [13:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_28 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_20, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_10}; // @[pla.scala:102:36] wire [27:0] cs_decoder_decoded_orMatrixOutputs_lo_36 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_28, cs_decoder_decoded_orMatrixOutputs_lo_lo_22}; // @[pla.scala:102:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_2 = {_cs_decoder_decoded_orMatrixOutputs_T_49, _cs_decoder_decoded_orMatrixOutputs_T_48}; // @[pla.scala:102:36, :114:36] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_5 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_2, _cs_decoder_decoded_orMatrixOutputs_T_46}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_1 = {_cs_decoder_decoded_orMatrixOutputs_T_52, _cs_decoder_decoded_orMatrixOutputs_T_50}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_2 = {_cs_decoder_decoded_orMatrixOutputs_T_56, _cs_decoder_decoded_orMatrixOutputs_T_54}; // @[pla.scala:102:36, :114:36] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_7 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_1}; // @[pla.scala:102:36] wire [6:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_9 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_7, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_5}; // @[pla.scala:102:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_2 = {_cs_decoder_decoded_orMatrixOutputs_T_62, _cs_decoder_decoded_orMatrixOutputs_T_60}; // @[pla.scala:102:36, :114:36] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_7 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_2, _cs_decoder_decoded_orMatrixOutputs_T_58}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_1 = {_cs_decoder_decoded_orMatrixOutputs_T_65, _cs_decoder_decoded_orMatrixOutputs_T_63}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_2 = {_cs_decoder_decoded_orMatrixOutputs_T_69, _cs_decoder_decoded_orMatrixOutputs_T_67}; // @[pla.scala:102:36, :114:36] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_8 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_1}; // @[pla.scala:102:36] wire [6:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_16 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_8, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_7}; // @[pla.scala:102:36] wire [13:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_25 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_16, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_9}; // @[pla.scala:102:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_2 = {_cs_decoder_decoded_orMatrixOutputs_T_75, _cs_decoder_decoded_orMatrixOutputs_T_73}; // @[pla.scala:102:36, :114:36] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_6 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_2, _cs_decoder_decoded_orMatrixOutputs_T_71}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_1 = {_cs_decoder_decoded_orMatrixOutputs_T_79, _cs_decoder_decoded_orMatrixOutputs_T_77}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_2 = {_cs_decoder_decoded_orMatrixOutputs_T_83, _cs_decoder_decoded_orMatrixOutputs_T_81}; // @[pla.scala:102:36, :114:36] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_7 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_1}; // @[pla.scala:102:36] wire [6:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_10 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_7, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_6}; // @[pla.scala:102:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_1 = {_cs_decoder_decoded_orMatrixOutputs_T_86, _cs_decoder_decoded_orMatrixOutputs_T_84}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_2 = {_cs_decoder_decoded_orMatrixOutputs_T_90, _cs_decoder_decoded_orMatrixOutputs_T_88}; // @[pla.scala:102:36, :114:36] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_7 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_2, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_1}; // @[pla.scala:102:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_2 = {_cs_decoder_decoded_orMatrixOutputs_T_94, _cs_decoder_decoded_orMatrixOutputs_T_92}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_3 = {_cs_decoder_decoded_orMatrixOutputs_T_98, _cs_decoder_decoded_orMatrixOutputs_T_96}; // @[pla.scala:102:36, :114:36] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_8 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_3, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_2}; // @[pla.scala:102:36] wire [7:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_22 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_8, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_7}; // @[pla.scala:102:36] wire [14:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_31 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_22, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_10}; // @[pla.scala:102:36] wire [28:0] cs_decoder_decoded_orMatrixOutputs_hi_39 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_31, cs_decoder_decoded_orMatrixOutputs_hi_lo_25}; // @[pla.scala:102:36] wire [56:0] cs_decoder_decoded_orMatrixOutputs = {cs_decoder_decoded_orMatrixOutputs_hi_39, cs_decoder_decoded_orMatrixOutputs_lo_36}; // @[pla.scala:102:36] wire _cs_decoder_decoded_invMatrixOutputs_T = cs_decoder_decoded_orMatrixOutputs[0]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_1 = cs_decoder_decoded_orMatrixOutputs[1]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_2 = cs_decoder_decoded_orMatrixOutputs[2]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_3 = cs_decoder_decoded_orMatrixOutputs[3]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_4 = cs_decoder_decoded_orMatrixOutputs[4]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_5 = cs_decoder_decoded_orMatrixOutputs[5]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_6 = cs_decoder_decoded_orMatrixOutputs[6]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_7 = cs_decoder_decoded_orMatrixOutputs[7]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_8 = cs_decoder_decoded_orMatrixOutputs[8]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_9 = cs_decoder_decoded_orMatrixOutputs[9]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_10 = cs_decoder_decoded_orMatrixOutputs[10]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_11 = cs_decoder_decoded_orMatrixOutputs[11]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_12 = cs_decoder_decoded_orMatrixOutputs[12]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_13 = cs_decoder_decoded_orMatrixOutputs[13]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_14 = cs_decoder_decoded_orMatrixOutputs[14]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_15 = cs_decoder_decoded_orMatrixOutputs[15]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_16 = cs_decoder_decoded_orMatrixOutputs[16]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_17 = cs_decoder_decoded_orMatrixOutputs[17]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_18 = cs_decoder_decoded_orMatrixOutputs[18]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_19 = cs_decoder_decoded_orMatrixOutputs[19]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_20 = cs_decoder_decoded_orMatrixOutputs[20]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_21 = cs_decoder_decoded_orMatrixOutputs[21]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_22 = cs_decoder_decoded_orMatrixOutputs[22]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_23 = cs_decoder_decoded_orMatrixOutputs[23]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_24 = cs_decoder_decoded_orMatrixOutputs[24]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_25 = cs_decoder_decoded_orMatrixOutputs[25]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_26 = cs_decoder_decoded_orMatrixOutputs[26]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_27 = cs_decoder_decoded_orMatrixOutputs[27]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_28 = cs_decoder_decoded_orMatrixOutputs[28]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_29 = cs_decoder_decoded_orMatrixOutputs[29]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_30 = cs_decoder_decoded_orMatrixOutputs[30]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_31 = cs_decoder_decoded_orMatrixOutputs[31]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_32 = cs_decoder_decoded_orMatrixOutputs[32]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_33 = cs_decoder_decoded_orMatrixOutputs[33]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_34 = cs_decoder_decoded_orMatrixOutputs[34]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_35 = cs_decoder_decoded_orMatrixOutputs[35]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_36 = cs_decoder_decoded_orMatrixOutputs[36]; // @[pla.scala:102:36, :123:56] wire _cs_decoder_decoded_invMatrixOutputs_T_37 = ~_cs_decoder_decoded_invMatrixOutputs_T_36; // @[pla.scala:123:{40,56}] wire _cs_decoder_decoded_invMatrixOutputs_T_38 = cs_decoder_decoded_orMatrixOutputs[37]; // @[pla.scala:102:36, :123:56] wire _cs_decoder_decoded_invMatrixOutputs_T_39 = ~_cs_decoder_decoded_invMatrixOutputs_T_38; // @[pla.scala:123:{40,56}] wire _cs_decoder_decoded_invMatrixOutputs_T_40 = cs_decoder_decoded_orMatrixOutputs[38]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_41 = cs_decoder_decoded_orMatrixOutputs[39]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_42 = cs_decoder_decoded_orMatrixOutputs[40]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_43 = cs_decoder_decoded_orMatrixOutputs[41]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_44 = cs_decoder_decoded_orMatrixOutputs[42]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_45 = cs_decoder_decoded_orMatrixOutputs[43]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_46 = cs_decoder_decoded_orMatrixOutputs[44]; // @[pla.scala:102:36, :123:56] wire _cs_decoder_decoded_invMatrixOutputs_T_47 = ~_cs_decoder_decoded_invMatrixOutputs_T_46; // @[pla.scala:123:{40,56}] wire _cs_decoder_decoded_invMatrixOutputs_T_48 = cs_decoder_decoded_orMatrixOutputs[45]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_49 = cs_decoder_decoded_orMatrixOutputs[46]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_50 = cs_decoder_decoded_orMatrixOutputs[47]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_51 = cs_decoder_decoded_orMatrixOutputs[48]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_52 = cs_decoder_decoded_orMatrixOutputs[49]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_53 = cs_decoder_decoded_orMatrixOutputs[50]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_54 = cs_decoder_decoded_orMatrixOutputs[51]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_55 = cs_decoder_decoded_orMatrixOutputs[52]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_56 = cs_decoder_decoded_orMatrixOutputs[53]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_57 = cs_decoder_decoded_orMatrixOutputs[54]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_58 = cs_decoder_decoded_orMatrixOutputs[55]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_59 = cs_decoder_decoded_orMatrixOutputs[56]; // @[pla.scala:102:36, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_lo_hi = {_cs_decoder_decoded_invMatrixOutputs_T_2, _cs_decoder_decoded_invMatrixOutputs_T_1}; // @[pla.scala:120:37, :124:31] wire [2:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_lo = {cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_lo_hi, _cs_decoder_decoded_invMatrixOutputs_T}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi_lo = {_cs_decoder_decoded_invMatrixOutputs_T_4, _cs_decoder_decoded_invMatrixOutputs_T_3}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi_hi = {_cs_decoder_decoded_invMatrixOutputs_T_6, _cs_decoder_decoded_invMatrixOutputs_T_5}; // @[pla.scala:120:37, :124:31] wire [3:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi = {cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi_hi, cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [6:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_lo = {cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi, cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_lo_hi = {_cs_decoder_decoded_invMatrixOutputs_T_9, _cs_decoder_decoded_invMatrixOutputs_T_8}; // @[pla.scala:120:37, :124:31] wire [2:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_lo = {cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_lo_hi, _cs_decoder_decoded_invMatrixOutputs_T_7}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi_lo = {_cs_decoder_decoded_invMatrixOutputs_T_11, _cs_decoder_decoded_invMatrixOutputs_T_10}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi_hi = {_cs_decoder_decoded_invMatrixOutputs_T_13, _cs_decoder_decoded_invMatrixOutputs_T_12}; // @[pla.scala:120:37, :124:31] wire [3:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi = {cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi_hi, cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [6:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_hi = {cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi, cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [13:0] cs_decoder_decoded_invMatrixOutputs_lo_lo = {cs_decoder_decoded_invMatrixOutputs_lo_lo_hi, cs_decoder_decoded_invMatrixOutputs_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_lo_hi = {_cs_decoder_decoded_invMatrixOutputs_T_16, _cs_decoder_decoded_invMatrixOutputs_T_15}; // @[pla.scala:120:37, :124:31] wire [2:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_lo = {cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_lo_hi, _cs_decoder_decoded_invMatrixOutputs_T_14}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi_lo = {_cs_decoder_decoded_invMatrixOutputs_T_18, _cs_decoder_decoded_invMatrixOutputs_T_17}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi_hi = {_cs_decoder_decoded_invMatrixOutputs_T_20, _cs_decoder_decoded_invMatrixOutputs_T_19}; // @[pla.scala:120:37, :124:31] wire [3:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi = {cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi_hi, cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [6:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_lo = {cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi, cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo_hi = {_cs_decoder_decoded_invMatrixOutputs_T_23, _cs_decoder_decoded_invMatrixOutputs_T_22}; // @[pla.scala:120:37, :124:31] wire [2:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo = {cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo_hi, _cs_decoder_decoded_invMatrixOutputs_T_21}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi_lo = {_cs_decoder_decoded_invMatrixOutputs_T_25, _cs_decoder_decoded_invMatrixOutputs_T_24}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi_hi = {_cs_decoder_decoded_invMatrixOutputs_T_27, _cs_decoder_decoded_invMatrixOutputs_T_26}; // @[pla.scala:120:37, :124:31] wire [3:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi = {cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi_hi, cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [6:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_hi = {cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi, cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [13:0] cs_decoder_decoded_invMatrixOutputs_lo_hi = {cs_decoder_decoded_invMatrixOutputs_lo_hi_hi, cs_decoder_decoded_invMatrixOutputs_lo_hi_lo}; // @[pla.scala:120:37] wire [27:0] cs_decoder_decoded_invMatrixOutputs_lo = {cs_decoder_decoded_invMatrixOutputs_lo_hi, cs_decoder_decoded_invMatrixOutputs_lo_lo}; // @[pla.scala:120:37] wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_lo_hi = {_cs_decoder_decoded_invMatrixOutputs_T_30, _cs_decoder_decoded_invMatrixOutputs_T_29}; // @[pla.scala:120:37, :124:31] wire [2:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_lo = {cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_lo_hi, _cs_decoder_decoded_invMatrixOutputs_T_28}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi_lo = {_cs_decoder_decoded_invMatrixOutputs_T_32, _cs_decoder_decoded_invMatrixOutputs_T_31}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi_hi = {_cs_decoder_decoded_invMatrixOutputs_T_34, _cs_decoder_decoded_invMatrixOutputs_T_33}; // @[pla.scala:120:37, :124:31] wire [3:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi = {cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi_hi, cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [6:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_lo = {cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi, cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_lo_hi = {_cs_decoder_decoded_invMatrixOutputs_T_39, _cs_decoder_decoded_invMatrixOutputs_T_37}; // @[pla.scala:120:37, :123:40] wire [2:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_lo = {cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_lo_hi, _cs_decoder_decoded_invMatrixOutputs_T_35}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi_lo = {_cs_decoder_decoded_invMatrixOutputs_T_41, _cs_decoder_decoded_invMatrixOutputs_T_40}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi_hi = {_cs_decoder_decoded_invMatrixOutputs_T_43, _cs_decoder_decoded_invMatrixOutputs_T_42}; // @[pla.scala:120:37, :124:31] wire [3:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi = {cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi_hi, cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [6:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_hi = {cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi, cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [13:0] cs_decoder_decoded_invMatrixOutputs_hi_lo = {cs_decoder_decoded_invMatrixOutputs_hi_lo_hi, cs_decoder_decoded_invMatrixOutputs_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_lo_hi = {_cs_decoder_decoded_invMatrixOutputs_T_47, _cs_decoder_decoded_invMatrixOutputs_T_45}; // @[pla.scala:120:37, :123:40, :124:31] wire [2:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_lo = {cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_lo_hi, _cs_decoder_decoded_invMatrixOutputs_T_44}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi_lo = {_cs_decoder_decoded_invMatrixOutputs_T_49, _cs_decoder_decoded_invMatrixOutputs_T_48}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi_hi = {_cs_decoder_decoded_invMatrixOutputs_T_51, _cs_decoder_decoded_invMatrixOutputs_T_50}; // @[pla.scala:120:37, :124:31] wire [3:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi = {cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi_hi, cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [6:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_lo = {cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi, cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo_lo = {_cs_decoder_decoded_invMatrixOutputs_T_53, _cs_decoder_decoded_invMatrixOutputs_T_52}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo_hi = {_cs_decoder_decoded_invMatrixOutputs_T_55, _cs_decoder_decoded_invMatrixOutputs_T_54}; // @[pla.scala:120:37, :124:31] wire [3:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo = {cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo_hi, cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi_lo = {_cs_decoder_decoded_invMatrixOutputs_T_57, _cs_decoder_decoded_invMatrixOutputs_T_56}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi_hi = {_cs_decoder_decoded_invMatrixOutputs_T_59, _cs_decoder_decoded_invMatrixOutputs_T_58}; // @[pla.scala:120:37, :124:31] wire [3:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi = {cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi_hi, cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [7:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_hi = {cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi, cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [14:0] cs_decoder_decoded_invMatrixOutputs_hi_hi = {cs_decoder_decoded_invMatrixOutputs_hi_hi_hi, cs_decoder_decoded_invMatrixOutputs_hi_hi_lo}; // @[pla.scala:120:37] wire [28:0] cs_decoder_decoded_invMatrixOutputs_hi = {cs_decoder_decoded_invMatrixOutputs_hi_hi, cs_decoder_decoded_invMatrixOutputs_hi_lo}; // @[pla.scala:120:37] assign cs_decoder_decoded_invMatrixOutputs = {cs_decoder_decoded_invMatrixOutputs_hi, cs_decoder_decoded_invMatrixOutputs_lo}; // @[pla.scala:120:37] assign cs_decoder_decoded = cs_decoder_decoded_invMatrixOutputs; // @[pla.scala:81:23, :120:37] assign cs_decoder_0 = cs_decoder_decoded[56]; // @[pla.scala:81:23] assign cs_legal = cs_decoder_0; // @[Decode.scala:50:77] assign cs_decoder_1 = cs_decoder_decoded[55]; // @[pla.scala:81:23] assign cs_fp_val = cs_decoder_1; // @[Decode.scala:50:77] assign cs_decoder_2 = cs_decoder_decoded[54:45]; // @[pla.scala:81:23] assign cs_fu_code = cs_decoder_2; // @[Decode.scala:50:77] assign cs_decoder_3 = cs_decoder_decoded[44:43]; // @[pla.scala:81:23] assign cs_dst_type = cs_decoder_3; // @[Decode.scala:50:77] assign cs_decoder_4 = cs_decoder_decoded[42:41]; // @[pla.scala:81:23] assign cs_rs1_type = cs_decoder_4; // @[Decode.scala:50:77] assign cs_decoder_5 = cs_decoder_decoded[40:39]; // @[pla.scala:81:23] assign cs_rs2_type = cs_decoder_5; // @[Decode.scala:50:77] assign cs_decoder_6 = cs_decoder_decoded[38]; // @[pla.scala:81:23] assign cs_frs3_en = cs_decoder_6; // @[Decode.scala:50:77] assign cs_decoder_7 = cs_decoder_decoded[37:35]; // @[pla.scala:81:23] assign cs_imm_sel = cs_decoder_7; // @[Decode.scala:50:77] assign cs_decoder_8 = cs_decoder_decoded[34]; // @[pla.scala:81:23] assign cs_uses_ldq = cs_decoder_8; // @[Decode.scala:50:77] assign cs_decoder_9 = cs_decoder_decoded[33]; // @[pla.scala:81:23] assign cs_uses_stq = cs_decoder_9; // @[Decode.scala:50:77] assign cs_decoder_10 = cs_decoder_decoded[32]; // @[pla.scala:81:23] assign cs_is_amo = cs_decoder_10; // @[Decode.scala:50:77] assign cs_decoder_11 = cs_decoder_decoded[31:27]; // @[pla.scala:81:23] assign cs_mem_cmd = cs_decoder_11; // @[Decode.scala:50:77] assign cs_decoder_12 = cs_decoder_decoded[26]; // @[pla.scala:81:23] assign cs_inst_unique = cs_decoder_12; // @[Decode.scala:50:77] assign cs_decoder_13 = cs_decoder_decoded[25]; // @[pla.scala:81:23] assign cs_flush_on_commit = cs_decoder_13; // @[Decode.scala:50:77] assign cs_decoder_14 = cs_decoder_decoded[24:22]; // @[pla.scala:81:23] assign cs_csr_cmd = cs_decoder_14; // @[Decode.scala:50:77] assign cs_decoder_15 = cs_decoder_decoded[21]; // @[pla.scala:81:23] assign cs_fcn_dw = cs_decoder_15; // @[Decode.scala:50:77] assign cs_decoder_16 = cs_decoder_decoded[20:16]; // @[pla.scala:81:23] assign cs_fcn_op = cs_decoder_16; // @[Decode.scala:50:77] assign cs_decoder_17 = cs_decoder_decoded[15]; // @[pla.scala:81:23] assign cs_fp_ldst = cs_decoder_17; // @[Decode.scala:50:77] assign cs_decoder_18 = cs_decoder_decoded[14]; // @[pla.scala:81:23] assign cs_fp_wen = cs_decoder_18; // @[Decode.scala:50:77] assign cs_decoder_19 = cs_decoder_decoded[13]; // @[pla.scala:81:23] assign cs_fp_ren1 = cs_decoder_19; // @[Decode.scala:50:77] assign cs_decoder_20 = cs_decoder_decoded[12]; // @[pla.scala:81:23] assign cs_fp_ren2 = cs_decoder_20; // @[Decode.scala:50:77] assign cs_decoder_21 = cs_decoder_decoded[11]; // @[pla.scala:81:23] assign cs_fp_ren3 = cs_decoder_21; // @[Decode.scala:50:77] assign cs_decoder_22 = cs_decoder_decoded[10]; // @[pla.scala:81:23] assign cs_fp_swap12 = cs_decoder_22; // @[Decode.scala:50:77] assign cs_decoder_23 = cs_decoder_decoded[9]; // @[pla.scala:81:23] assign cs_fp_swap23 = cs_decoder_23; // @[Decode.scala:50:77] wire cs_decoder_24 = cs_decoder_decoded[8]; // @[pla.scala:81:23] wire cs_decoder_25 = cs_decoder_decoded[7]; // @[pla.scala:81:23] assign cs_decoder_26 = cs_decoder_decoded[6]; // @[pla.scala:81:23] assign cs_fp_fromint = cs_decoder_26; // @[Decode.scala:50:77] assign cs_decoder_27 = cs_decoder_decoded[5]; // @[pla.scala:81:23] assign cs_fp_toint = cs_decoder_27; // @[Decode.scala:50:77] assign cs_decoder_28 = cs_decoder_decoded[4]; // @[pla.scala:81:23] assign cs_fp_fastpipe = cs_decoder_28; // @[Decode.scala:50:77] assign cs_decoder_29 = cs_decoder_decoded[3]; // @[pla.scala:81:23] assign cs_fp_fma = cs_decoder_29; // @[Decode.scala:50:77] assign cs_decoder_30 = cs_decoder_decoded[2]; // @[pla.scala:81:23] assign cs_fp_div = cs_decoder_30; // @[Decode.scala:50:77] assign cs_decoder_31 = cs_decoder_decoded[1]; // @[pla.scala:81:23] assign cs_fp_sqrt = cs_decoder_31; // @[Decode.scala:50:77] assign cs_decoder_32 = cs_decoder_decoded[0]; // @[pla.scala:81:23] assign cs_fp_wflags = cs_decoder_32; // @[Decode.scala:50:77] assign cs_fp_typeTagIn = {1'h0, cs_decoder_24}; // @[Decode.scala:50:77] assign cs_fp_typeTagOut = {1'h0, cs_decoder_25}; // @[Decode.scala:50:77] wire _T_29 = cs_csr_cmd == 3'h6; // @[package.scala:16:47] wire _csr_en_T; // @[package.scala:16:47] assign _csr_en_T = _T_29; // @[package.scala:16:47] wire _csr_ren_T; // @[package.scala:16:47] assign _csr_ren_T = _T_29; // @[package.scala:16:47] wire _csr_en_T_1 = &cs_csr_cmd; // @[package.scala:16:47] wire _csr_en_T_2 = cs_csr_cmd == 3'h5; // @[package.scala:16:47] wire _csr_en_T_3 = _csr_en_T \| _csr_en_T_1; // @[package.scala:16:47, :81:59] wire csr_en = _csr_en_T_3 \| _csr_en_T_2; // @[package.scala:16:47, :81:59] wire _csr_ren_T_1 = &cs_csr_cmd; // @[package.scala:16:47] wire _csr_ren_T_2 = _csr_ren_T \| _csr_ren_T_1; // @[package.scala:16:47, :81:59] wire _csr_ren_T_3 = uop_lrs1 == 6'h0; // @[decode.scala:422:7, :426:14, :428:17, :452:62] wire csr_ren = _csr_ren_T_2 & _csr_ren_T_3; // @[package.scala:81:59] wire system_insn = cs_csr_cmd == 3'h4; // @[decode.scala:447:16, :453:32] wire [31:0] _GEN_40 = uop_inst & 32'hFE007FFF; // @[decode.scala:428:17, :454:21] wire [31:0] _sfence_T; // @[decode.scala:454:21] assign _sfence_T = _GEN_40; // @[decode.scala:454:21] wire [31:0] _uop_is_sfence_T; // @[decode.scala:528:26] assign _uop_is_sfence_T = _GEN_40; // @[decode.scala:454:21, :528:26] wire sfence = _sfence_T == 32'h12000073; // @[decode.scala:454:21] wire [2:0] _illegal_rm_T = uop_inst[14:12]; // @[decode.scala:428:17, :460:24] wire [2:0] _illegal_rm_T_4 = uop_inst[14:12]; // @[decode.scala:428:17, :460:{24,57}] wire [2:0] _uop_is_rocc_T_6 = uop_inst[14:12]; // @[decode.scala:428:17, :460:24, :532:88] wire [2:0] _uop_pimm_T_1 = uop_inst[14:12]; // @[decode.scala:428:17, :460:24, :553:47] wire [2:0] _uop_fp_rm_T = uop_inst[14:12]; // @[decode.scala:428:17, :460:24, :556:26] wire [2:0] _uop_fp_rm_T_2 = uop_inst[14:12]; // @[decode.scala:428:17, :460:24, :556:59] wire _illegal_rm_T_1 = _illegal_rm_T == 3'h5; // @[package.scala:16:47] wire _illegal_rm_T_2 = _illegal_rm_T == 3'h6; // @[package.scala:16:47] wire _illegal_rm_T_3 = _illegal_rm_T_1 \| _illegal_rm_T_2; // @[package.scala:16:47, :81:59] wire _illegal_rm_T_5 = &_illegal_rm_T_4; // @[decode.scala:460:{57,65}] wire _illegal_rm_T_6 = io_fcsr_rm_0 > 3'h4; // @[decode.scala:422:7, :460:87] wire _illegal_rm_T_7 = _illegal_rm_T_5 & _illegal_rm_T_6; // @[decode.scala:460:{65,73,87}] wire illegal_rm = _illegal_rm_T_3 \| _illegal_rm_T_7; // @[package.scala:81:59] wire _id_illegal_insn_T = ~cs_legal; // @[decode.scala:447:16, :461:26] wire _id_illegal_insn_T_1 = io_csr_decode_fp_illegal_0 \| illegal_rm; // @[decode.scala:422:7, :460:49, :462:45] wire _id_illegal_insn_T_2 = cs_fp_val & _id_illegal_insn_T_1; // @[decode.scala:447:16, :462:{16,45}] wire _id_illegal_insn_T_3 = _id_illegal_insn_T \| _id_illegal_insn_T_2; // @[decode.scala:461:{26,36}, :462:16] wire _id_illegal_insn_T_5 = _id_illegal_insn_T_3 \| _id_illegal_insn_T_4; // @[decode.scala:461:36, :462:61, :463:18] wire _id_illegal_insn_T_9 = _id_illegal_insn_T_5; // @[decode.scala:462:61, :463:49] wire _id_illegal_insn_T_10 = ~csr_ren; // @[decode.scala:452:50, :465:47] wire _id_illegal_insn_T_11 = _id_illegal_insn_T_10 & io_csr_decode_write_illegal_0; // @[decode.scala:422:7, :465:{47,56}] wire _id_illegal_insn_T_12 = io_csr_decode_read_illegal_0 \| _id_illegal_insn_T_11; // @[decode.scala:422:7, :465:{44,56}] wire _id_illegal_insn_T_13 = csr_en & _id_illegal_insn_T_12; // @[package.scala:81:59] wire _id_illegal_insn_T_14 = _id_illegal_insn_T_9 \| _id_illegal_insn_T_13; // @[decode.scala:463:49, :464:45, :465:13] wire _id_illegal_insn_T_15 = sfence \| system_insn; // @[decode.scala:453:32, :454:21, :466:14] wire _id_illegal_insn_T_16 = _id_illegal_insn_T_15 & io_csr_decode_system_illegal_0; // @[decode.scala:422:7, :466:{14,30}] wire id_illegal_insn = _id_illegal_insn_T_14 \| _id_illegal_insn_T_16; // @[decode.scala:464:45, :465:89, :466:30] wire _T_1 = io_interrupt_0 & ~io_enq_uop_is_sfb_0; // @[decode.scala:422:7, :473:{19,22}] assign xcpt_valid = _T_1 \| uop_bp_debug_if \| uop_bp_xcpt_if \| uop_xcpt_pf_if \| uop_xcpt_ae_if \| id_illegal_insn; // @[decode.scala:428:17, :465:89, :470:26, :473:19] assign uop_exception = xcpt_valid; // @[decode.scala:428:17, :470:26] assign xcpt_cause = _T_1 ? io_interrupt_cause_0 : {60'h0, uop_bp_debug_if ? 4'hE : uop_bp_xcpt_if ? 4'h3 : uop_xcpt_pf_if ? 4'hC : {2'h0, uop_xcpt_ae_if ? 2'h1 : 2'h2}}; // @[Mux.scala:50:70] assign uop_exc_cause = xcpt_cause; // @[Mux.scala:50:70] wire [31:0] _uop_is_mov_T = uop_inst & 32'hFE00707F; // @[decode.scala:428:17, :485:26] wire _uop_is_mov_T_1 = _uop_is_mov_T == 32'h33; // @[decode.scala:485:26] wire _uop_is_mov_T_2 = ~(\|LRS1); // @[decode.scala:442:18, :485:42] assign _uop_is_mov_T_3 = _uop_is_mov_T_1 & _uop_is_mov_T_2; // @[decode.scala:485:{26,34,42}] assign uop_is_mov = _uop_is_mov_T_3; // @[decode.scala:428:17, :485:34] assign uop_fu_code_3 = cs_fu_code[3]; // @[decode.scala:428:17, :447:16, :487:84] wire _uop_iq_type_1_T = cs_fu_code[3]; // @[decode.scala:447:16, :487:84] assign uop_fu_code_4 = cs_fu_code[4]; // @[decode.scala:428:17, :447:16, :487:84] wire _uop_iq_type_1_T_1 = cs_fu_code[4]; // @[decode.scala:447:16, :487:84] assign uop_fu_code_5 = cs_fu_code[5]; // @[decode.scala:428:17, :447:16, :487:84] wire _uop_iq_type_1_T_2 = cs_fu_code[5]; // @[decode.scala:447:16, :487:84] assign uop_fu_code_8 = cs_fu_code[8]; // @[decode.scala:428:17, :447:16, :487:84] wire _uop_iq_type_1_T_3 = cs_fu_code[8]; // @[decode.scala:447:16, :487:84] wire _uop_iq_type_1_T_4 = _uop_iq_type_1_T \| _uop_iq_type_1_T_1; // @[decode.scala:487:{84,98}] wire _uop_iq_type_1_T_5 = _uop_iq_type_1_T_4 \| _uop_iq_type_1_T_2; // @[decode.scala:487:{84,98}] assign _uop_iq_type_1_T_6 = _uop_iq_type_1_T_5 \| _uop_iq_type_1_T_3; // @[decode.scala:487:{84,98}] assign uop_iq_type_1 = _uop_iq_type_1_T_6; // @[decode.scala:428:17, :487:98] assign uop_fu_code_0 = cs_fu_code[0]; // @[decode.scala:428:17, :447:16, :488:84] assign _uop_iq_type_2_T = cs_fu_code[0]; // @[decode.scala:447:16, :488:84] assign uop_iq_type_2 = _uop_iq_type_2_T; // @[decode.scala:428:17, :488:84] assign uop_fu_code_1 = cs_fu_code[1]; // @[decode.scala:428:17, :447:16, :489:84] wire _uop_iq_type_0_T = cs_fu_code[1]; // @[decode.scala:447:16, :489:84] assign uop_fu_code_2 = cs_fu_code[2]; // @[decode.scala:428:17, :447:16, :489:84] wire _uop_iq_type_0_T_1 = cs_fu_code[2]; // @[decode.scala:447:16, :489:84] assign _uop_iq_type_0_T_2 = _uop_iq_type_0_T \| _uop_iq_type_0_T_1; // @[decode.scala:489:{84,98}] assign uop_iq_type_0 = _uop_iq_type_0_T_2; // @[decode.scala:428:17, :489:98] assign uop_fu_code_6 = cs_fu_code[6]; // @[decode.scala:428:17, :447:16, :490:84] wire _uop_iq_type_3_T = cs_fu_code[6]; // @[decode.scala:447:16, :490:84] assign uop_fu_code_7 = cs_fu_code[7]; // @[decode.scala:428:17, :447:16, :490:84] wire _uop_iq_type_3_T_1 = cs_fu_code[7]; // @[decode.scala:447:16, :490:84] assign uop_fu_code_9 = cs_fu_code[9]; // @[decode.scala:428:17, :447:16, :490:84] wire _uop_iq_type_3_T_2 = cs_fu_code[9]; // @[decode.scala:447:16, :490:84] wire _uop_iq_type_3_T_3 = _uop_iq_type_3_T \| _uop_iq_type_3_T_1; // @[decode.scala:490:{84,98}] assign _uop_iq_type_3_T_4 = _uop_iq_type_3_T_3 \| _uop_iq_type_3_T_2; // @[decode.scala:490:{84,98}] assign uop_iq_type_3 = _uop_iq_type_3_T_4; // @[decode.scala:428:17, :490:98] assign uop_ldst = {1'h0, LDST}; // @[decode.scala:428:17, :441:18, :494:18] assign uop_lrs3 = {1'h0, LRS3}; // @[decode.scala:428:17, :444:18, :497:18] wire _uop_lrs1_rtype_T = cs_rs1_type == 2'h0; // @[decode.scala:447:16, :500:37] wire _uop_lrs1_rtype_T_1 = ~(\|LRS1); // @[decode.scala:442:18, :485:42, :500:56] wire _uop_lrs1_rtype_T_2 = _uop_lrs1_rtype_T & _uop_lrs1_rtype_T_1; // @[decode.scala:500:{37,48,56}] wire [1:0] _uop_lrs1_rtype_T_3 = _uop_lrs1_rtype_T_2 ? 2'h3 : cs_rs1_type; // @[decode.scala:447:16, :500:{24,48}] wire _uop_lrs2_rtype_T = cs_rs2_type == 2'h0; // @[decode.scala:447:16, :501:37] wire _uop_lrs2_rtype_T_1 = ~(\|LRS2); // @[decode.scala:443:18, :501:56] wire _uop_lrs2_rtype_T_2 = _uop_lrs2_rtype_T & _uop_lrs2_rtype_T_1; // @[decode.scala:501:{37,48,56}] wire [1:0] _uop_lrs2_rtype_T_3 = _uop_lrs2_rtype_T_2 ? 2'h3 : cs_rs2_type; // @[decode.scala:447:16, :501:{24,48}] wire _uop_ldst_is_rs1_T = uop_br_type == 4'h0; // @[decode.scala:428:17] wire _uop_ldst_is_rs1_T_1 = _uop_ldst_is_rs1_T & uop_is_sfb; // @[decode.scala:428:17] wire _uop_ldst_is_rs1_T_2 = _uop_ldst_is_rs1_T_1; // @[micro-op.scala:121:{42,52}] wire _T_24 = _uop_ldst_is_rs1_T & uop_is_sfb & cs_rs2_type == 2'h2; // @[decode.scala:428:17, :447:16, :506:{27,42}] wire _GEN_41 = LDST == 5'h0; // @[decode.scala:422:7, :426:14, :428:17, :441:18, :507:33] wire _uop_lrs2_rtype_T_4; // @[decode.scala:507:33] assign _uop_lrs2_rtype_T_4 = _GEN_41; // @[decode.scala:507:33] wire _uop_lrs1_rtype_T_4; // @[decode.scala:512:33] assign _uop_lrs1_rtype_T_4 = _GEN_41; // @[decode.scala:507:33, :512:33] wire [1:0] _uop_lrs2_rtype_T_5 = {2{_uop_lrs2_rtype_T_4}}; // @[decode.scala:507:{27,33}] assign uop_lrs2_rtype = _T_24 ? _uop_lrs2_rtype_T_5 : _uop_lrs2_rtype_T_3; // @[decode.scala:428:17, :501:{18,24}, :506:{27,52}, :507:{21,27}] assign uop_lrs2 = {1'h0, _T_24 ? LDST : LRS2}; // @[decode.scala:428:17, :441:18, :443:18, :496:18, :506:{27,52}, :508:21] wire _T_28 = _uop_ldst_is_rs1_T & uop_is_sfb & uop_is_mov; // @[decode.scala:428:17, :510:34] wire _GEN_42 = _T_24 \| ~_T_28; // @[decode.scala:495:18, :506:{27,52}, :510:{34,49}] assign uop_lrs1 = {1'h0, _GEN_42 ? LRS1 : LDST}; // @[decode.scala:428:17, :441:18, :442:18, :495:18, :506:52, :510:49] wire [1:0] _uop_lrs1_rtype_T_5 = {2{_uop_lrs1_rtype_T_4}}; // @[decode.scala:512:{27,33}] assign uop_lrs1_rtype = _GEN_42 ? _uop_lrs1_rtype_T_3 : _uop_lrs1_rtype_T_5; // @[decode.scala:428:17, :495:18, :500:{18,24}, :506:52, :510:49, :512:27] assign uop_ldst_is_rs1 = ~_T_24 & (_T_28 \| _uop_ldst_is_rs1_T_2); // @[decode.scala:428:17, :504:19, :506:{27,52}, :509:21, :510:{34,49}, :513:21] wire _uop_mem_size_T = cs_mem_cmd == 5'h14; // @[package.scala:16:47] wire _uop_mem_size_T_1 = cs_mem_cmd == 5'h5; // @[package.scala:16:47] wire _uop_mem_size_T_2 = _uop_mem_size_T \| _uop_mem_size_T_1; // @[package.scala:16:47, :81:59] wire _uop_mem_size_T_3 = \|LRS2; // @[decode.scala:443:18, :501:56, :521:77] wire _uop_mem_size_T_4 = \|LRS1; // @[decode.scala:442:18, :485:42, :521:91] wire [1:0] _uop_mem_size_T_5 = {_uop_mem_size_T_3, _uop_mem_size_T_4}; // @[decode.scala:521:{71,77,91}] wire [1:0] _uop_mem_size_T_6 = uop_inst[13:12]; // @[decode.scala:428:17, :521:105] assign _uop_mem_size_T_7 = _uop_mem_size_T_2 ? _uop_mem_size_T_5 : _uop_mem_size_T_6; // @[package.scala:81:59] assign uop_mem_size = _uop_mem_size_T_7; // @[decode.scala:428:17, :521:24] wire _uop_mem_signed_T = uop_inst[14]; // @[decode.scala:428:17, :522:26] assign _uop_mem_signed_T_1 = ~_uop_mem_signed_T; // @[decode.scala:522:{21,26}] assign uop_mem_signed = _uop_mem_signed_T_1; // @[decode.scala:428:17, :522:21] wire [31:0] _GEN_43 = {17'h0, uop_inst[14:0] & 15'h707F}; // @[decode.scala:428:17, :526:26] wire [31:0] _uop_is_fence_T; // @[decode.scala:526:26] assign _uop_is_fence_T = _GEN_43; // @[decode.scala:526:26] wire [31:0] _uop_is_fencei_T; // @[decode.scala:527:26] assign _uop_is_fencei_T = _GEN_43; // @[decode.scala:526:26, :527:26] wire [31:0] _uop_br_type_T; // @[decode.scala:604:36] assign _uop_br_type_T = _GEN_43; // @[decode.scala:526:26, :604:36] wire [31:0] _uop_br_type_T_3; // @[decode.scala:604:36] assign _uop_br_type_T_3 = _GEN_43; // @[decode.scala:526:26, :604:36] wire [31:0] _uop_br_type_T_6; // @[decode.scala:604:36] assign _uop_br_type_T_6 = _GEN_43; // @[decode.scala:526:26, :604:36] wire [31:0] _uop_br_type_T_9; // @[decode.scala:604:36] assign _uop_br_type_T_9 = _GEN_43; // @[decode.scala:526:26, :604:36] wire [31:0] _uop_br_type_T_12; // @[decode.scala:604:36] assign _uop_br_type_T_12 = _GEN_43; // @[decode.scala:526:26, :604:36] wire [31:0] _uop_br_type_T_15; // @[decode.scala:604:36] assign _uop_br_type_T_15 = _GEN_43; // @[decode.scala:526:26, :604:36] wire [31:0] _uop_br_type_T_21; // @[decode.scala:604:36] assign _uop_br_type_T_21 = _GEN_43; // @[decode.scala:526:26, :604:36] assign _uop_is_fence_T_1 = _uop_is_fence_T == 32'hF; // @[decode.scala:526:26] assign uop_is_fence = _uop_is_fence_T_1; // @[decode.scala:428:17, :526:26] assign _uop_is_fencei_T_1 = _uop_is_fencei_T == 32'h100F; // @[decode.scala:527:26] assign uop_is_fencei = _uop_is_fencei_T_1; // @[decode.scala:428:17, :527:26] assign _uop_is_sfence_T_1 = _uop_is_sfence_T == 32'h12000073; // @[decode.scala:528:26] assign uop_is_sfence = _uop_is_sfence_T_1; // @[decode.scala:428:17, :528:26] wire _uop_is_sys_pc2epc_T_1 = _uop_is_sys_pc2epc_T == 32'h100073; // @[decode.scala:529:29] wire _uop_is_sys_pc2epc_T_3 = _uop_is_sys_pc2epc_T_2 == 32'h73; // @[decode.scala:529:48] assign _uop_is_sys_pc2epc_T_4 = _uop_is_sys_pc2epc_T_1 \| _uop_is_sys_pc2epc_T_3; // @[decode.scala:529:{29,40,48}] assign uop_is_sys_pc2epc = _uop_is_sys_pc2epc_T_4; // @[decode.scala:428:17, :529:40] wire _uop_is_eret_T_1 = _uop_is_eret_T == 32'h73; // @[decode.scala:530:26] wire _uop_is_eret_T_3 = _uop_is_eret_T_2 == 32'h100073; // @[decode.scala:530:44] wire _uop_is_eret_T_4 = _uop_is_eret_T_1 \| _uop_is_eret_T_3; // @[decode.scala:530:{26,36,44}] wire _uop_is_eret_T_6 = _uop_is_eret_T_5 == 32'h10200073; // @[decode.scala:530:63] wire _uop_is_eret_T_7 = _uop_is_eret_T_4 \| _uop_is_eret_T_6; // @[decode.scala:530:{36,55,63}] wire _uop_is_eret_T_9 = _uop_is_eret_T_8 == 32'h30200073; // @[decode.scala:530:80] wire _uop_is_eret_T_10 = _uop_is_eret_T_7 \| _uop_is_eret_T_9; // @[decode.scala:530:{55,72,80}] wire _uop_is_eret_T_12 = _uop_is_eret_T_11 == 32'h7B200073; // @[decode.scala:530:97] assign _uop_is_eret_T_13 = _uop_is_eret_T_10 \| _uop_is_eret_T_12; // @[decode.scala:530:{72,89,97}] assign uop_is_eret = _uop_is_eret_T_13; // @[decode.scala:428:17, :530:89] wire [6:0] _uop_is_rocc_T = uop_inst[6:0]; // @[decode.scala:428:17, :532:25] wire _uop_is_rocc_T_1 = _uop_is_rocc_T == 7'hB; // @[package.scala:16:47] wire _uop_is_rocc_T_2 = _uop_is_rocc_T == 7'h2B; // @[package.scala:16:47] wire _uop_is_rocc_T_3 = _uop_is_rocc_T == 7'h7B; // @[package.scala:16:47] wire _uop_is_rocc_T_4 = _uop_is_rocc_T_1 \| _uop_is_rocc_T_2; // @[package.scala:16:47, :81:59] wire _uop_is_rocc_T_5 = _uop_is_rocc_T_4 \| _uop_is_rocc_T_3; // @[package.scala:16:47, :81:59] wire _uop_is_rocc_T_7 = _uop_is_rocc_T_6 == 3'h0; // @[package.scala:16:47] wire _uop_is_rocc_T_8 = _uop_is_rocc_T_6 == 3'h2; // @[package.scala:16:47] wire _uop_is_rocc_T_9 = _uop_is_rocc_T_6 == 3'h3; // @[package.scala:16:47] wire _uop_is_rocc_T_10 = _uop_is_rocc_T_6 == 3'h4; // @[package.scala:16:47] wire _uop_is_rocc_T_11 = _uop_is_rocc_T_6 == 3'h6; // @[package.scala:16:47] wire _uop_is_rocc_T_12 = &_uop_is_rocc_T_6; // @[package.scala:16:47] wire _uop_is_rocc_T_13 = _uop_is_rocc_T_7 \| _uop_is_rocc_T_8; // @[package.scala:16:47, :81:59] wire _uop_is_rocc_T_14 = _uop_is_rocc_T_13 \| _uop_is_rocc_T_9; // @[package.scala:16:47, :81:59] wire _uop_is_rocc_T_15 = _uop_is_rocc_T_14 \| _uop_is_rocc_T_10; // @[package.scala:16:47, :81:59] wire _uop_is_rocc_T_16 = _uop_is_rocc_T_15 \| _uop_is_rocc_T_11; // @[package.scala:16:47, :81:59] wire _uop_is_rocc_T_17 = _uop_is_rocc_T_16 \| _uop_is_rocc_T_12; // @[package.scala:16:47, :81:59] assign _uop_is_rocc_T_18 = _uop_is_rocc_T_5 & _uop_is_rocc_T_17; // @[package.scala:81:59] assign uop_is_rocc = _uop_is_rocc_T_18; // @[decode.scala:428:17, :532:81] wire _uop_flush_on_commit_T = ~csr_ren; // @[decode.scala:452:50, :465:47, :533:59] wire _uop_flush_on_commit_T_1 = csr_en & _uop_flush_on_commit_T; // @[package.scala:81:59] wire _uop_flush_on_commit_T_2 = _uop_flush_on_commit_T_1 & io_csr_decode_write_flush_0; // @[decode.scala:422:7, :533:{56,68}] assign _uop_flush_on_commit_T_3 = cs_flush_on_commit \| _uop_flush_on_commit_T_2; // @[decode.scala:447:16, :533:{45,68}] assign uop_flush_on_commit = _uop_flush_on_commit_T_3; // @[decode.scala:428:17, :533:45] wire _GEN_44 = cs_imm_sel == 3'h2; // @[package.scala:16:47] wire _di24_20_T; // @[decode.scala:540:32] assign _di24_20_T = _GEN_44; // @[decode.scala:540:32] wire _imm_i11_T_2; // @[util.scala:288:44] assign _imm_i11_T_2 = _GEN_44; // @[util.scala:288:44] wire _T_142 = cs_imm_sel == 3'h1; // @[decode.scala:447:16, :540:55] wire _di24_20_T_1; // @[decode.scala:540:55] assign _di24_20_T_1 = _T_142; // @[decode.scala:540:55] wire _imm_i0_T; // @[util.scala:291:27] assign _imm_i0_T = _T_142; // @[util.scala:291:27] wire _di24_20_T_2 = _di24_20_T \| _di24_20_T_1; // @[decode.scala:540:{32,41,55}] wire [4:0] di24_20 = _di24_20_T_2 ? _di24_20_T_3 : _di24_20_T_4; // @[decode.scala:540:{20,41,69,81}] wire [6:0] _imm_packed_T = uop_inst[31:25]; // @[decode.scala:428:17, :541:28] wire [7:0] _imm_packed_T_1 = uop_inst[19:12]; // @[decode.scala:428:17, :541:50] wire [11:0] imm_packed_hi = {_imm_packed_T, di24_20}; // @[decode.scala:540:20, :541:{23,28}] assign imm_packed = {imm_packed_hi, _imm_packed_T_1}; // @[decode.scala:541:{23,50}] assign uop_imm_packed = imm_packed; // @[decode.scala:428:17, :541:23] wire _imm_ip_T = cs_imm_sel == 3'h6; // @[util.scala:282:23] wire [19:0] imm_ip = _imm_ip_T ? 20'h0 : imm_packed; // @[util.scala:282:{17,23}] wire _imm_sign_T = imm_ip[19]; // @[util.scala:282:17, :284:18] wire imm_sign = _imm_sign_T; // @[util.scala:284:{18,37}] wire imm_hi_hi_hi = imm_sign; // @[util.scala:284:37, :294:15] wire _T_139 = cs_imm_sel == 3'h3; // @[package.scala:16:47] wire _imm_i30_20_T; // @[util.scala:285:27] assign _imm_i30_20_T = _T_139; // @[util.scala:285:27] wire _imm_i19_12_T; // @[util.scala:286:27] assign _imm_i19_12_T = _T_139; // @[util.scala:285:27, :286:27] wire _imm_i11_T; // @[util.scala:287:27] assign _imm_i11_T = _T_139; // @[util.scala:285:27, :287:27] wire _imm_i10_5_T; // @[util.scala:289:27] assign _imm_i10_5_T = _T_139; // @[util.scala:285:27, :289:27] wire _imm_i4_1_T; // @[util.scala:290:27] assign _imm_i4_1_T = _T_139; // @[util.scala:285:27, :290:27] wire [10:0] _imm_i30_20_T_1 = imm_ip[18:8]; // @[util.scala:282:17, :285:39] wire [10:0] _imm_i30_20_T_2 = _imm_i30_20_T_1; // @[util.scala:285:{39,46}] wire [10:0] imm_i30_20 = _imm_i30_20_T ? _imm_i30_20_T_2 : {11{imm_sign}}; // @[util.scala:284:37, :285:{21,27,46}] wire [10:0] imm_hi_hi_lo = imm_i30_20; // @[util.scala:285:21, :294:15] wire _GEN_45 = cs_imm_sel == 3'h4; // @[util.scala:286:44] wire _imm_i19_12_T_1; // @[util.scala:286:44] assign _imm_i19_12_T_1 = _GEN_45; // @[util.scala:286:44] wire _imm_i11_T_1; // @[util.scala:288:27] assign _imm_i11_T_1 = _GEN_45; // @[util.scala:286:44, :288:27] wire _imm_i19_12_T_2 = _imm_i19_12_T \| _imm_i19_12_T_1; // @[util.scala:286:{27,36,44}] wire [7:0] _imm_i19_12_T_3 = imm_ip[7:0]; // @[util.scala:282:17, :286:56] wire [7:0] _imm_i19_12_T_4 = _imm_i19_12_T_3; // @[util.scala:286:{56,62}] wire [7:0] imm_i19_12 = _imm_i19_12_T_2 ? _imm_i19_12_T_4 : {8{imm_sign}}; // @[util.scala:284:37, :286:{21,36,62}] wire [7:0] imm_hi_lo_hi = imm_i19_12; // @[util.scala:286:21, :294:15] wire _imm_i11_T_3 = _imm_i11_T_1 \| _imm_i11_T_2; // @[util.scala:288:{27,36,44}] wire _imm_i11_T_4 = imm_ip[8]; // @[util.scala:282:17, :288:56] wire _imm_i0_T_3 = imm_ip[8]; // @[util.scala:282:17, :288:56, :291:56] wire _imm_i11_T_5 = _imm_i11_T_4; // @[util.scala:288:{56,60}] wire _imm_i11_T_6 = _imm_i11_T_3 ? _imm_i11_T_5 : imm_sign; // @[util.scala:284:37, :288:{21,36,60}] wire imm_i11 = ~_imm_i11_T & _imm_i11_T_6; // @[util.scala:287:{21,27}, :288:21] wire imm_hi_lo_lo = imm_i11; // @[util.scala:287:21, :294:15] wire [4:0] _imm_i10_5_T_1 = imm_ip[18:14]; // @[util.scala:282:17, :289:44] wire [4:0] _imm_i10_5_T_2 = _imm_i10_5_T_1; // @[util.scala:289:{44,52}] wire [4:0] imm_i10_5 = _imm_i10_5_T ? 5'h0 : _imm_i10_5_T_2; // @[util.scala:289:{21,27,52}] wire [4:0] imm_lo_hi_hi = imm_i10_5; // @[util.scala:289:21, :294:15] wire [4:0] _imm_i4_1_T_1 = imm_ip[13:9]; // @[util.scala:282:17, :290:44] wire [4:0] _imm_i4_1_T_2 = _imm_i4_1_T_1; // @[util.scala:290:{44,51}] wire [4:0] imm_i4_1 = _imm_i4_1_T ? 5'h0 : _imm_i4_1_T_2; // @[util.scala:290:{21,27,51}] wire [4:0] imm_lo_hi_lo = imm_i4_1; // @[util.scala:290:21, :294:15] wire _imm_i0_T_1 = cs_imm_sel == 3'h0; // @[util.scala:291:44] wire _imm_i0_T_2 = _imm_i0_T \| _imm_i0_T_1; // @[util.scala:291:{27,36,44}] wire _imm_i0_T_4 = _imm_i0_T_3; // @[util.scala:291:{56,60}] wire imm_i0 = _imm_i0_T_2 & _imm_i0_T_4; // @[util.scala:291:{21,36,60}] wire imm_lo_lo = imm_i0; // @[util.scala:291:21, :294:15] wire [9:0] imm_lo_hi = {imm_lo_hi_hi, imm_lo_hi_lo}; // @[util.scala:294:15] wire [10:0] imm_lo = {imm_lo_hi, imm_lo_lo}; // @[util.scala:294:15] wire [8:0] imm_hi_lo = {imm_hi_lo_hi, imm_hi_lo_lo}; // @[util.scala:294:15] wire [11:0] imm_hi_hi = {imm_hi_hi_hi, imm_hi_hi_lo}; // @[util.scala:294:15] wire [20:0] imm_hi = {imm_hi_hi, imm_hi_lo}; // @[util.scala:294:15] wire [31:0] imm = {imm_hi, imm_lo}; // @[util.scala:294:15] wire [27:0] imm_hi_1 = imm[31:4]; // @[util.scala:294:15] wire [4:0] imm_lo_1 = imm[4:0]; // @[util.scala:294:15] wire _short_imm_T = imm_hi_1 == 28'h0; // @[pla.scala:114:36] wire [27:0] _short_imm_T_1 = ~imm_hi_1; // @[decode.scala:543:20, :545:37] wire _short_imm_T_2 = _short_imm_T_1 == 28'h0; // @[pla.scala:114:36] wire _short_imm_T_3 = _short_imm_T \| _short_imm_T_2; // @[decode.scala:545:{26,34,45}] wire _short_imm_T_4 = &cs_imm_sel; // @[decode.scala:447:16, :545:67] wire short_imm = _short_imm_T_3 \| _short_imm_T_4; // @[decode.scala:545:{34,53,67}] wire _uop_imm_rename_T = cs_imm_sel != 3'h6; // @[decode.scala:447:16, :547:32] wire _uop_imm_rename_T_1 = ~(&cs_imm_sel); // @[decode.scala:447:16, :545:67, :547:55] wire _uop_imm_rename_T_2 = _uop_imm_rename_T & _uop_imm_rename_T_1; // @[decode.scala:547:{32,41,55}] assign uop_imm_rename = ~short_imm & _uop_imm_rename_T_2; // @[decode.scala:428:17, :545:53, :547:{18,41}, :550:20, :551:20] assign uop_imm_sel = short_imm ? 3'h5 : cs_imm_sel; // @[decode.scala:428:17, :447:16, :545:53, :549:18, :550:20, :552:17] wire _uop_pimm_T = &cs_imm_sel; // @[decode.scala:447:16, :545:67, :553:32] wire [4:0] _uop_pimm_T_2 = _uop_pimm_T ? {2'h0, _uop_pimm_T_1} : imm_lo_1; // @[decode.scala:544:19, :553:{20,32,47}] assign uop_pimm = short_imm ? _uop_pimm_T_2 : 5'h0; // @[decode.scala:422:7, :426:14, :428:17, :429:7, :545:53, :550:20, :553:{14,20}] wire _uop_fp_rm_T_1 = &_uop_fp_rm_T; // @[decode.scala:556:{26,34}] assign _uop_fp_rm_T_3 = _uop_fp_rm_T_1 ? io_fcsr_rm_0 : _uop_fp_rm_T_2; // @[decode.scala:422:7, :556:{21,34,59}] assign uop_fp_rm = _uop_fp_rm_T_3; // @[decode.scala:428:17, :556:21] assign _uop_fp_typ_T = uop_inst[21:20]; // @[decode.scala:428:17, :557:22] assign uop_fp_typ = _uop_fp_typ_T; // @[decode.scala:428:17, :557:22] assign uop_csr_cmd = (_T_29 \| (&cs_csr_cmd)) & ~(\|LRS1) ? 3'h2 : cs_csr_cmd; // @[package.scala:16:47] wire [31:0] _uop_br_type_T_18 = {25'h0, _uop_is_rocc_T}; // @[decode.scala:529:48, :532:25, :572:14, :604:36] wire [9:0] _GEN_46 = {uop_inst[14:12], _uop_is_rocc_T}; // @[decode.scala:428:17, :460:24, :526:26, :532:25] wire [16:0] _GEN_47 = {_imm_packed_T, uop_inst[14:12], _uop_is_rocc_T}; // @[decode.scala:428:17, :460:24, :485:26, :532:25, :541:28] assign uop_op1_sel = _uop_is_rocc_T == 7'h37 \| _GEN_46 == 10'h2F3 \| _GEN_46 == 10'h373 \| _GEN_46 == 10'h3F3 \| uop_inst == 32'h10500073 \| uop_inst == 32'h10200073 \| uop_inst == 32'h30200073 \| uop_inst == 32'h7B200073 ? 2'h1 : _uop_is_rocc_T == 7'h6F \| _GEN_46 == 10'h67 \| _uop_is_rocc_T == 7'h17 ? 2'h2 : {2{_GEN_47 == 17'h4133 \| _GEN_47 == 17'h4233 \| _GEN_47 == 17'h4333 \| _GEN_47 == 17'h413B \| _GEN_47 == 17'h423B \| _GEN_47 == 17'h433B \| _GEN_47 == 17'h103B \| {uop_inst[31:26], uop_inst[14:12], _uop_is_rocc_T} == 16'h89B}}; // @[package.scala:81:59] wire [15:0] _GEN_48 = {uop_inst[31:26], uop_inst[14:12], _uop_is_rocc_T}; // @[decode.scala:428:17, :460:24, :532:25, :589:65] wire _uop_op2_sel_T = uop_lrs2_rtype == 2'h0; // @[decode.scala:428:17, :590:39] wire [2:0] _uop_op2_sel_T_1 = _uop_op2_sel_T ? 3'h5 : 3'h6; // @[decode.scala:590:{23,39}] assign uop_op2_sel = cs_is_amo \| _GEN_46 == 10'hF3 \| _GEN_46 == 10'h173 \| _GEN_46 == 10'h1F3 ? 3'h2 : _GEN_46 == 10'h2F3 \| _GEN_46 == 10'h373 \| _GEN_46 == 10'h3F3 \| uop_inst == 32'h10500073 \| uop_inst == 32'h10200073 \| uop_inst == 32'h7B200073 \| uop_inst == 32'h30200073 ? 3'h4 : _uop_is_rocc_T == 7'h6F \| _GEN_46 == 10'h67 ? 3'h3 : _GEN_47 == 17'h90B3 \| _GEN_48 == 16'h4893 \| _GEN_47 == 17'hD0B3 \| _GEN_48 == 16'h6893 \| _GEN_47 == 17'h50B3 \| {uop_inst[31:26], uop_inst[14:12], _uop_is_rocc_T} == 16'h2893 ? _uop_op2_sel_T_1 : {2'h0, _T_139 \| _imm_i0_T_1 \| _T_142}; // @[package.scala:16:47, :81:59] wire _uop_br_type_T_1 = _uop_br_type_T == 32'h63; // @[decode.scala:604:36] wire [3:0] _uop_br_type_T_2 = {2'h0, _uop_br_type_T_1, 1'h0}; // @[decode.scala:604:{30,36}] wire _uop_br_type_T_4 = _uop_br_type_T_3 == 32'h1063; // @[decode.scala:604:36] wire [3:0] _uop_br_type_T_5 = {3'h0, _uop_br_type_T_4}; // @[decode.scala:604:{30,36}] wire _uop_br_type_T_7 = _uop_br_type_T_6 == 32'h5063; // @[decode.scala:604:36] wire [3:0] _uop_br_type_T_8 = _uop_br_type_T_7 ? 4'h3 : 4'h0; // @[decode.scala:604:{30,36}] wire _uop_br_type_T_10 = _uop_br_type_T_9 == 32'h7063; // @[decode.scala:604:36] wire [3:0] _uop_br_type_T_11 = {1'h0, _uop_br_type_T_10, 2'h0}; // @[decode.scala:604:{30,36}] wire _uop_br_type_T_13 = _uop_br_type_T_12 == 32'h4063; // @[decode.scala:604:36] wire [3:0] _uop_br_type_T_14 = _uop_br_type_T_13 ? 4'h5 : 4'h0; // @[decode.scala:604:{30,36}] wire _uop_br_type_T_16 = _uop_br_type_T_15 == 32'h6063; // @[decode.scala:604:36] wire [3:0] _uop_br_type_T_17 = _uop_br_type_T_16 ? 4'h6 : 4'h0; // @[decode.scala:604:{30,36}] wire _uop_br_type_T_19 = _uop_br_type_T_18 == 32'h6F; // @[decode.scala:604:36] wire [3:0] _uop_br_type_T_20 = _uop_br_type_T_19 ? 4'h7 : 4'h0; // @[decode.scala:604:{30,36}] wire _uop_br_type_T_22 = _uop_br_type_T_21 == 32'h67; // @[decode.scala:604:36] wire [3:0] _uop_br_type_T_23 = {_uop_br_type_T_22, 3'h0}; // @[decode.scala:604:{30,36}] wire [3:0] _uop_br_type_T_24 = _uop_br_type_T_2 \| _uop_br_type_T_5; // @[decode.scala:604:{30,62}] wire [3:0] _uop_br_type_T_25 = _uop_br_type_T_24 \| _uop_br_type_T_8; // @[decode.scala:604:{30,62}] wire [3:0] _uop_br_type_T_26 = _uop_br_type_T_25 \| _uop_br_type_T_11; // @[decode.scala:604:{30,62}] wire [3:0] _uop_br_type_T_27 = _uop_br_type_T_26 \| _uop_br_type_T_14; // @[decode.scala:604:{30,62}] wire [3:0] _uop_br_type_T_28 = _uop_br_type_T_27 \| _uop_br_type_T_17; // @[decode.scala:604:{30,62}] wire [3:0] _uop_br_type_T_29 = _uop_br_type_T_28 \| _uop_br_type_T_20; // @[decode.scala:604:{30,62}] assign _uop_br_type_T_30 = _uop_br_type_T_29 \| _uop_br_type_T_23; // @[decode.scala:604:{30,62}] assign uop_br_type = _uop_br_type_T_30; // @[decode.scala:428:17, :604:62] assign io_deq_uop_inst = io_deq_uop_inst_0; // @[decode.scala:422:7] assign io_deq_uop_debug_inst = io_deq_uop_debug_inst_0; // @[decode.scala:422:7] assign io_deq_uop_is_rvc = io_deq_uop_is_rvc_0; // @[decode.scala:422:7] assign io_deq_uop_debug_pc = io_deq_uop_debug_pc_0; // @[decode.scala:422:7] assign io_deq_uop_iq_type_0 = io_deq_uop_iq_type_0_0; // @[decode.scala:422:7] assign io_deq_uop_iq_type_1 = io_deq_uop_iq_type_1_0; // @[decode.scala:422:7] assign io_deq_uop_iq_type_2 = io_deq_uop_iq_type_2_0; // @[decode.scala:422:7] assign io_deq_uop_iq_type_3 = io_deq_uop_iq_type_3_0; // @[decode.scala:422:7] assign io_deq_uop_fu_code_0 = io_deq_uop_fu_code_0_0; // @[decode.scala:422:7] assign io_deq_uop_fu_code_1 = io_deq_uop_fu_code_1_0; // @[decode.scala:422:7] assign io_deq_uop_fu_code_2 = io_deq_uop_fu_code_2_0; // @[decode.scala:422:7] assign io_deq_uop_fu_code_3 = io_deq_uop_fu_code_3_0; // @[decode.scala:422:7] assign io_deq_uop_fu_code_4 = io_deq_uop_fu_code_4_0; // @[decode.scala:422:7] assign io_deq_uop_fu_code_5 = io_deq_uop_fu_code_5_0; // @[decode.scala:422:7] assign io_deq_uop_fu_code_6 = io_deq_uop_fu_code_6_0; // @[decode.scala:422:7] assign io_deq_uop_fu_code_7 = io_deq_uop_fu_code_7_0; // @[decode.scala:422:7] assign io_deq_uop_fu_code_8 = io_deq_uop_fu_code_8_0; // @[decode.scala:422:7] assign io_deq_uop_fu_code_9 = io_deq_uop_fu_code_9_0; // @[decode.scala:422:7] assign io_deq_uop_br_type = io_deq_uop_br_type_0; // @[decode.scala:422:7] assign io_deq_uop_is_sfb = io_deq_uop_is_sfb_0; // @[decode.scala:422:7] assign io_deq_uop_is_fence = io_deq_uop_is_fence_0; // @[decode.scala:422:7] assign io_deq_uop_is_fencei = io_deq_uop_is_fencei_0; // @[decode.scala:422:7] assign io_deq_uop_is_sfence = io_deq_uop_is_sfence_0; // @[decode.scala:422:7] assign io_deq_uop_is_amo = io_deq_uop_is_amo_0; // @[decode.scala:422:7] assign io_deq_uop_is_eret = io_deq_uop_is_eret_0; // @[decode.scala:422:7] assign io_deq_uop_is_sys_pc2epc = io_deq_uop_is_sys_pc2epc_0; // @[decode.scala:422:7] assign io_deq_uop_is_rocc = io_deq_uop_is_rocc_0; // @[decode.scala:422:7] assign io_deq_uop_is_mov = io_deq_uop_is_mov_0; // @[decode.scala:422:7] assign io_deq_uop_ftq_idx = io_deq_uop_ftq_idx_0; // @[decode.scala:422:7] assign io_deq_uop_edge_inst = io_deq_uop_edge_inst_0; // @[decode.scala:422:7] assign io_deq_uop_pc_lob = io_deq_uop_pc_lob_0; // @[decode.scala:422:7] assign io_deq_uop_taken = io_deq_uop_taken_0; // @[decode.scala:422:7] assign io_deq_uop_imm_rename = io_deq_uop_imm_rename_0; // @[decode.scala:422:7] assign io_deq_uop_imm_sel = io_deq_uop_imm_sel_0; // @[decode.scala:422:7] assign io_deq_uop_pimm = io_deq_uop_pimm_0; // @[decode.scala:422:7] assign io_deq_uop_imm_packed = io_deq_uop_imm_packed_0; // @[decode.scala:422:7] assign io_deq_uop_op1_sel = io_deq_uop_op1_sel_0; // @[decode.scala:422:7] assign io_deq_uop_op2_sel = io_deq_uop_op2_sel_0; // @[decode.scala:422:7] assign io_deq_uop_fp_ctrl_ldst = io_deq_uop_fp_ctrl_ldst_0; // @[decode.scala:422:7] assign io_deq_uop_fp_ctrl_wen = io_deq_uop_fp_ctrl_wen_0; // @[decode.scala:422:7] assign io_deq_uop_fp_ctrl_ren1 = io_deq_uop_fp_ctrl_ren1_0; // @[decode.scala:422:7] assign io_deq_uop_fp_ctrl_ren2 = io_deq_uop_fp_ctrl_ren2_0; // @[decode.scala:422:7] assign io_deq_uop_fp_ctrl_ren3 = io_deq_uop_fp_ctrl_ren3_0; // @[decode.scala:422:7] assign io_deq_uop_fp_ctrl_swap12 = io_deq_uop_fp_ctrl_swap12_0; // @[decode.scala:422:7] assign io_deq_uop_fp_ctrl_swap23 = io_deq_uop_fp_ctrl_swap23_0; // @[decode.scala:422:7] assign io_deq_uop_fp_ctrl_typeTagIn = io_deq_uop_fp_ctrl_typeTagIn_0; // @[decode.scala:422:7] assign io_deq_uop_fp_ctrl_typeTagOut = io_deq_uop_fp_ctrl_typeTagOut_0; // @[decode.scala:422:7] assign io_deq_uop_fp_ctrl_fromint = io_deq_uop_fp_ctrl_fromint_0; // @[decode.scala:422:7] assign io_deq_uop_fp_ctrl_toint = io_deq_uop_fp_ctrl_toint_0; // @[decode.scala:422:7] assign io_deq_uop_fp_ctrl_fastpipe = io_deq_uop_fp_ctrl_fastpipe_0; // @[decode.scala:422:7] assign io_deq_uop_fp_ctrl_fma = io_deq_uop_fp_ctrl_fma_0; // @[decode.scala:422:7] assign io_deq_uop_fp_ctrl_div = io_deq_uop_fp_ctrl_div_0; // @[decode.scala:422:7] assign io_deq_uop_fp_ctrl_sqrt = io_deq_uop_fp_ctrl_sqrt_0; // @[decode.scala:422:7] assign io_deq_uop_fp_ctrl_wflags = io_deq_uop_fp_ctrl_wflags_0; // @[decode.scala:422:7] assign io_deq_uop_exception = io_deq_uop_exception_0; // @[decode.scala:422:7] assign io_deq_uop_exc_cause = io_deq_uop_exc_cause_0; // @[decode.scala:422:7] assign io_deq_uop_mem_cmd = io_deq_uop_mem_cmd_0; // @[decode.scala:422:7] assign io_deq_uop_mem_size = io_deq_uop_mem_size_0; // @[decode.scala:422:7] assign io_deq_uop_mem_signed = io_deq_uop_mem_signed_0; // @[decode.scala:422:7] assign io_deq_uop_uses_ldq = io_deq_uop_uses_ldq_0; // @[decode.scala:422:7] assign io_deq_uop_uses_stq = io_deq_uop_uses_stq_0; // @[decode.scala:422:7] assign io_deq_uop_is_unique = io_deq_uop_is_unique_0; // @[decode.scala:422:7] assign io_deq_uop_flush_on_commit = io_deq_uop_flush_on_commit_0; // @[decode.scala:422:7] assign io_deq_uop_csr_cmd = io_deq_uop_csr_cmd_0; // @[decode.scala:422:7] assign io_deq_uop_ldst_is_rs1 = io_deq_uop_ldst_is_rs1_0; // @[decode.scala:422:7] assign io_deq_uop_ldst = io_deq_uop_ldst_0; // @[decode.scala:422:7] assign io_deq_uop_lrs1 = io_deq_uop_lrs1_0; // @[decode.scala:422:7] assign io_deq_uop_lrs2 = io_deq_uop_lrs2_0; // @[decode.scala:422:7] assign io_deq_uop_lrs3 = io_deq_uop_lrs3_0; // @[decode.scala:422:7] assign io_deq_uop_dst_rtype = io_deq_uop_dst_rtype_0; // @[decode.scala:422:7] assign io_deq_uop_lrs1_rtype = io_deq_uop_lrs1_rtype_0; // @[decode.scala:422:7] assign io_deq_uop_lrs2_rtype = io_deq_uop_lrs2_rtype_0; // @[decode.scala:422:7] assign io_deq_uop_frs3_en = io_deq_uop_frs3_en_0; // @[decode.scala:422:7] assign io_deq_uop_fcn_dw = io_deq_uop_fcn_dw_0; // @[decode.scala:422:7] assign io_deq_uop_fcn_op = io_deq_uop_fcn_op_0; // @[decode.scala:422:7] assign io_deq_uop_fp_val = io_deq_uop_fp_val_0; // @[decode.scala:422:7] assign io_deq_uop_fp_rm = io_deq_uop_fp_rm_0; // @[decode.scala:422:7] assign io_deq_uop_fp_typ = io_deq_uop_fp_typ_0; // @[decode.scala:422:7] assign io_deq_uop_xcpt_pf_if = io_deq_uop_xcpt_pf_if_0; // @[decode.scala:422:7] assign io_deq_uop_xcpt_ae_if = io_deq_uop_xcpt_ae_if_0; // @[decode.scala:422:7] assign io_deq_uop_bp_debug_if = io_deq_uop_bp_debug_if_0; // @[decode.scala:422:7] assign io_deq_uop_bp_xcpt_if = io_deq_uop_bp_xcpt_if_0; // @[decode.scala:422:7] assign io_deq_uop_debug_fsrc = io_deq_uop_debug_fsrc_0; // @[decode.scala:422:7] assign io_csr_decode_inst = io_csr_decode_inst_0; // @[decode.scala:422:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /* Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_66( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_source, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [26:0] _GEN = {23'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] reg [8:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg source_1; // @[Monitor.scala:541:22] reg [3:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [7:0] inflight_sizes; // @[Monitor.scala:618:33] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_0 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:36:7, :673:46] wire _GEN_1 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:36:7, :673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [1:0] inflight_1; // @[Monitor.scala:726:35] reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File Serdes.scala: package testchipip.serdes import chisel3._ import chisel3.util._ import freechips.rocketchip.diplomacy._ import org.chipsalliance.cde.config._ class GenericSerializer[T <: Data](t: T, flitWidth: Int) extends Module { override def desiredName = s"GenericSerializer_${t.typeName}w${t.getWidth}_f${flitWidth}" val io = IO(new Bundle { val in = Flipped(Decoupled(t)) val out = Decoupled(new Flit(flitWidth)) val busy = Output(Bool()) }) val dataBits = t.getWidth.max(flitWidth) val dataBeats = (dataBits - 1) / flitWidth + 1 require(dataBeats >= 1) val data = Reg(Vec(dataBeats, UInt(flitWidth.W))) val beat = RegInit(0.U(log2Ceil(dataBeats).W)) io.in.ready := io.out.ready && beat === 0.U io.out.valid := io.in.valid \|\| beat =/= 0.U io.out.bits.flit := Mux(beat === 0.U, io.in.bits.asUInt, data(beat)) when (io.out.fire) { beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U) when (beat === 0.U) { data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(flitWidth.W))) data(0) := DontCare // unused, DCE this } } io.busy := io.out.valid } class GenericDeserializer[T <: Data](t: T, flitWidth: Int) extends Module { override def desiredName = s"GenericDeserializer_${t.typeName}w${t.getWidth}_f${flitWidth}" val io = IO(new Bundle { val in = Flipped(Decoupled(new Flit(flitWidth))) val out = Decoupled(t) val busy = Output(Bool()) }) val dataBits = t.getWidth.max(flitWidth) val dataBeats = (dataBits - 1) / flitWidth + 1 require(dataBeats >= 1) val data = Reg(Vec(dataBeats-1, UInt(flitWidth.W))) val beat = RegInit(0.U(log2Ceil(dataBeats).W)) io.in.ready := io.out.ready \|\| beat =/= (dataBeats-1).U io.out.valid := io.in.valid && beat === (dataBeats-1).U io.out.bits := (if (dataBeats == 1) { io.in.bits.flit.asTypeOf(t) } else { Cat(io.in.bits.flit, data.asUInt).asTypeOf(t) }) when (io.in.fire) { beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U) if (dataBeats > 1) { when (beat =/= (dataBeats-1).U) { data(beat(log2Ceil(dataBeats-1)-1,0)) := io.in.bits.flit } } } io.busy := beat =/= 0.U } class FlitToPhit(flitWidth: Int, phitWidth: Int) extends Module { override def desiredName = s"FlitToPhit_f${flitWidth}_p${phitWidth}" val io = IO(new Bundle { val in = Flipped(Decoupled(new Flit(flitWidth))) val out = Decoupled(new Phit(phitWidth)) }) require(flitWidth >= phitWidth) val dataBeats = (flitWidth - 1) / phitWidth + 1 val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W))) val beat = RegInit(0.U(log2Ceil(dataBeats).W)) io.in.ready := io.out.ready && beat === 0.U io.out.valid := io.in.valid \|\| beat =/= 0.U io.out.bits.phit := (if (dataBeats == 1) io.in.bits.flit else Mux(beat === 0.U, io.in.bits.flit, data(beat-1.U))) when (io.out.fire) { beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U) when (beat === 0.U) { data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(phitWidth.W))).tail } } } object FlitToPhit { def apply(flit: DecoupledIO[Flit], phitWidth: Int): DecoupledIO[Phit] = { val flit2phit = Module(new FlitToPhit(flit.bits.flitWidth, phitWidth)) flit2phit.io.in <> flit flit2phit.io.out } } class PhitToFlit(flitWidth: Int, phitWidth: Int) extends Module { override def desiredName = s"PhitToFlit_p${phitWidth}_f${flitWidth}" val io = IO(new Bundle { val in = Flipped(Decoupled(new Phit(phitWidth))) val out = Decoupled(new Flit(flitWidth)) }) require(flitWidth >= phitWidth) val dataBeats = (flitWidth - 1) / phitWidth + 1 val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W))) val beat = RegInit(0.U(log2Ceil(dataBeats).W)) io.in.ready := io.out.ready \|\| beat =/= (dataBeats-1).U io.out.valid := io.in.valid && beat === (dataBeats-1).U io.out.bits.flit := (if (dataBeats == 1) io.in.bits.phit else Cat(io.in.bits.phit, data.asUInt)) when (io.in.fire) { beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U) if (dataBeats > 1) { when (beat =/= (dataBeats-1).U) { data(beat) := io.in.bits.phit } } } } object PhitToFlit { def apply(phit: DecoupledIO[Phit], flitWidth: Int): DecoupledIO[Flit] = { val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth)) phit2flit.io.in <> phit phit2flit.io.out } def apply(phit: ValidIO[Phit], flitWidth: Int): ValidIO[Flit] = { val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth)) phit2flit.io.in.valid := phit.valid phit2flit.io.in.bits := phit.bits when (phit.valid) { assert(phit2flit.io.in.ready) } val out = Wire(Valid(new Flit(flitWidth))) out.valid := phit2flit.io.out.valid out.bits := phit2flit.io.out.bits phit2flit.io.out.ready := true.B out } } class PhitArbiter(phitWidth: Int, flitWidth: Int, channels: Int) extends Module { override def desiredName = s"PhitArbiter_p${phitWidth}_f${flitWidth}_n${channels}" val io = IO(new Bundle { val in = Flipped(Vec(channels, Decoupled(new Phit(phitWidth)))) val out = Decoupled(new Phit(phitWidth)) }) if (channels == 1) { io.out <> io.in(0) } else { val headerWidth = log2Ceil(channels) val headerBeats = (headerWidth - 1) / phitWidth + 1 val flitBeats = (flitWidth - 1) / phitWidth + 1 val beats = headerBeats + flitBeats val beat = RegInit(0.U(log2Ceil(beats).W)) val chosen_reg = Reg(UInt(headerWidth.W)) val chosen_prio = PriorityEncoder(io.in.map(_.valid)) val chosen = Mux(beat === 0.U, chosen_prio, chosen_reg) val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0) io.out.valid := VecInit(io.in.map(_.valid))(chosen) io.out.bits.phit := Mux(beat < headerBeats.U, chosen.asTypeOf(Vec(headerBeats, UInt(phitWidth.W)))(header_idx), VecInit(io.in.map(_.bits.phit))(chosen)) for (i <- 0 until channels) { io.in(i).ready := io.out.ready && beat >= headerBeats.U && chosen_reg === i.U } when (io.out.fire) { beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U) when (beat === 0.U) { chosen_reg := chosen_prio } } } } class PhitDemux(phitWidth: Int, flitWidth: Int, channels: Int) extends Module { override def desiredName = s"PhitDemux_p${phitWidth}_f${flitWidth}_n${channels}" val io = IO(new Bundle { val in = Flipped(Decoupled(new Phit(phitWidth))) val out = Vec(channels, Decoupled(new Phit(phitWidth))) }) if (channels == 1) { io.out(0) <> io.in } else { val headerWidth = log2Ceil(channels) val headerBeats = (headerWidth - 1) / phitWidth + 1 val flitBeats = (flitWidth - 1) / phitWidth + 1 val beats = headerBeats + flitBeats val beat = RegInit(0.U(log2Ceil(beats).W)) val channel_vec = Reg(Vec(headerBeats, UInt(phitWidth.W))) val channel = channel_vec.asUInt(log2Ceil(channels)-1,0) val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0) io.in.ready := beat < headerBeats.U \|\| VecInit(io.out.map(_.ready))(channel) for (c <- 0 until channels) { io.out(c).valid := io.in.valid && beat >= headerBeats.U && channel === c.U io.out(c).bits.phit := io.in.bits.phit } when (io.in.fire) { beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U) when (beat < headerBeats.U) { channel_vec(header_idx) := io.in.bits.phit } } } } class DecoupledFlitToCreditedFlit(flitWidth: Int, bufferSz: Int) extends Module { override def desiredName = s"DecoupledFlitToCreditedFlit_f${flitWidth}_b${bufferSz}" val io = IO(new Bundle { val in = Flipped(Decoupled(new Flit(flitWidth))) val out = Decoupled(new Flit(flitWidth)) val credit = Flipped(Decoupled(new Flit(flitWidth))) }) val creditWidth = log2Ceil(bufferSz) require(creditWidth <= flitWidth) val credits = RegInit(0.U((creditWidth+1).W)) val credit_incr = io.out.fire val credit_decr = io.credit.fire when (credit_incr \|\| credit_decr) { credits := credits + credit_incr - Mux(io.credit.valid, io.credit.bits.flit +& 1.U, 0.U) } io.out.valid := io.in.valid && credits < bufferSz.U io.out.bits.flit := io.in.bits.flit io.in.ready := io.out.ready && credits < bufferSz.U io.credit.ready := true.B } class CreditedFlitToDecoupledFlit(flitWidth: Int, bufferSz: Int) extends Module { override def desiredName = s"CreditedFlitToDecoupledFlit_f${flitWidth}_b${bufferSz}" val io = IO(new Bundle { val in = Flipped(Decoupled(new Flit(flitWidth))) val out = Decoupled(new Flit(flitWidth)) val credit = Decoupled(new Flit(flitWidth)) }) val creditWidth = log2Ceil(bufferSz) require(creditWidth <= flitWidth) val buffer = Module(new Queue(new Flit(flitWidth), bufferSz)) val credits = RegInit(0.U((creditWidth+1).W)) val credit_incr = buffer.io.deq.fire val credit_decr = io.credit.fire when (credit_incr \|\| credit_decr) { credits := credit_incr + Mux(credit_decr, 0.U, credits) } buffer.io.enq.valid := io.in.valid buffer.io.enq.bits := io.in.bits io.in.ready := true.B when (io.in.valid) { assert(buffer.io.enq.ready) } io.out <> buffer.io.deq io.credit.valid := credits =/= 0.U io.credit.bits.flit := credits - 1.U }	module GenericSerializer_TLBeatw67_f32( // @[Serdes.scala:8:7] input clock, // @[Serdes.scala:8:7] input reset, // @[Serdes.scala:8:7] output io_in_ready, // @[Serdes.scala:10:14] input io_in_valid, // @[Serdes.scala:10:14] input [64:0] io_in_bits_payload, // @[Serdes.scala:10:14] input io_in_bits_head, // @[Serdes.scala:10:14] input io_in_bits_tail, // @[Serdes.scala:10:14] input io_out_ready, // @[Serdes.scala:10:14] output io_out_valid, // @[Serdes.scala:10:14] output [31:0] io_out_bits_flit, // @[Serdes.scala:10:14] output io_busy // @[Serdes.scala:10:14] ); wire io_out_valid_0; // @[Serdes.scala:8:7] wire io_in_valid_0 = io_in_valid; // @[Serdes.scala:8:7] wire [64:0] io_in_bits_payload_0 = io_in_bits_payload; // @[Serdes.scala:8:7] wire io_in_bits_head_0 = io_in_bits_head; // @[Serdes.scala:8:7] wire io_in_bits_tail_0 = io_in_bits_tail; // @[Serdes.scala:8:7] wire io_out_ready_0 = io_out_ready; // @[Serdes.scala:8:7] wire [0:0][31:0] _GEN = '{32'h0}; wire _io_in_ready_T_1; // @[Serdes.scala:22:31] wire _io_out_valid_T_1; // @[Serdes.scala:23:31] wire io_busy_0 = io_out_valid_0; // @[Serdes.scala:8:7] wire io_in_ready_0; // @[Serdes.scala:8:7] wire [31:0] io_out_bits_flit_0; // @[Serdes.scala:8:7] reg [31:0] data_1; // @[Serdes.scala:19:17] reg [31:0] data_2; // @[Serdes.scala:19:17] reg [1:0] beat; // @[Serdes.scala:20:21] wire _io_in_ready_T = ~(\|beat); // @[Serdes.scala:20:21, :22:39] assign _io_in_ready_T_1 = io_out_ready_0 & _io_in_ready_T; // @[Serdes.scala:8:7, :22:{31,39}] assign io_in_ready_0 = _io_in_ready_T_1; // @[Serdes.scala:8:7, :22:31] wire _io_out_valid_T = \|beat; // @[Serdes.scala:20:21, :22:39, :23:39] assign _io_out_valid_T_1 = io_in_valid_0 \| _io_out_valid_T; // @[Serdes.scala:8:7, :23:{31,39}] assign io_out_valid_0 = _io_out_valid_T_1; // @[Serdes.scala:8:7, :23:31] wire _io_out_bits_flit_T = ~(\|beat); // @[Serdes.scala:20:21, :22:39, :24:32] wire [65:0] _GEN_0 = {io_in_bits_payload_0, io_in_bits_head_0}; // @[Serdes.scala:8:7, :24:52] wire [65:0] io_out_bits_flit_hi; // @[Serdes.scala:24:52] assign io_out_bits_flit_hi = _GEN_0; // @[Serdes.scala:24:52] wire [65:0] hi; // @[Serdes.scala:29:34] assign hi = _GEN_0; // @[Serdes.scala:24:52, :29:34] wire [66:0] _io_out_bits_flit_T_1 = {io_out_bits_flit_hi, io_in_bits_tail_0}; // @[Serdes.scala:8:7, :24:52] wire [3:0][31:0] _GEN_1 = {_GEN, {{data_2}, {data_1}, {32'h0}}}; // @[Serdes.scala:19:17, :24:26] wire [66:0] _io_out_bits_flit_T_2 = _io_out_bits_flit_T ? _io_out_bits_flit_T_1 : {35'h0, _GEN_1[beat]}; // @[Serdes.scala:20:21, :24:{26,32,52}] assign io_out_bits_flit_0 = _io_out_bits_flit_T_2[31:0]; // @[Serdes.scala:8:7, :24:{20,26}] wire _beat_T = beat == 2'h2; // @[Serdes.scala:20:21, :27:22] wire [2:0] _beat_T_1 = {1'h0, beat} + 3'h1; // @[Serdes.scala:20:21, :27:53] wire [1:0] _beat_T_2 = _beat_T_1[1:0]; // @[Serdes.scala:27:53] wire [1:0] _beat_T_3 = _beat_T ? 2'h0 : _beat_T_2; // @[Serdes.scala:27:{16,22,53}] wire _T = io_out_ready_0 & io_out_valid_0; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[Serdes.scala:8:7] if (_T & ~(\|beat)) begin // @[Decoupled.scala:51:35] data_1 <= hi[62:31]; // @[Serdes.scala:19:17, :29:34] data_2 <= {29'h0, hi[65:63]}; // @[Serdes.scala:19:17, :29:34] end if (reset) // @[Serdes.scala:8:7] beat <= 2'h0; // @[Serdes.scala:20:21] else if (_T) // @[Decoupled.scala:51:35] beat <= _beat_T_3; // @[Serdes.scala:20:21, :27:16] always @(posedge) assign io_in_ready = io_in_ready_0; // @[Serdes.scala:8:7] assign io_out_valid = io_out_valid_0; // @[Serdes.scala:8:7] assign io_out_bits_flit = io_out_bits_flit_0; // @[Serdes.scala:8:7] assign io_busy = io_busy_0; // @[Serdes.scala:8:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" / black /, label = (ei.manager.beatBytes 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red /, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" / green /) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" / yellow /, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File RegisterRouter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes} import freechips.rocketchip.resources.{Device, Resource, ResourceBindings} import freechips.rocketchip.prci.{NoCrossing} import freechips.rocketchip.regmapper.{RegField, RegMapper, RegMapperParams, RegMapperInput, RegisterRouter} import freechips.rocketchip.util.{BundleField, ControlKey, ElaborationArtefacts, GenRegDescsAnno} import scala.math.min class TLRegisterRouterExtraBundle(val sourceBits: Int, val sizeBits: Int) extends Bundle { val source = UInt((sourceBits max 1).W) val size = UInt((sizeBits max 1).W) } case object TLRegisterRouterExtra extends ControlKey[TLRegisterRouterExtraBundle]("tlrr_extra") case class TLRegisterRouterExtraField(sourceBits: Int, sizeBits: Int) extends BundleField[TLRegisterRouterExtraBundle](TLRegisterRouterExtra, Output(new TLRegisterRouterExtraBundle(sourceBits, sizeBits)), x => { x.size := 0.U x.source := 0.U }) /* TLRegisterNode is a specialized TL SinkNode that encapsulates MMIO registers. * It provides functionality for describing and outputting metdata about the registers in several formats. * It also provides a concrete implementation of a regmap function that will be used * to wire a map of internal registers associated with this node to the node's interconnect port. / case class TLRegisterNode( address: Seq[AddressSet], device: Device, deviceKey: String = "reg/control", concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false)( implicit valName: ValName) extends SinkNode(TLImp)(Seq(TLSlavePortParameters.v1( Seq(TLSlaveParameters.v1( address = address, resources = Seq(Resource(device, deviceKey)), executable = executable, supportsGet = TransferSizes(1, beatBytes), supportsPutPartial = TransferSizes(1, beatBytes), supportsPutFull = TransferSizes(1, beatBytes), fifoId = Some(0))), // requests are handled in order beatBytes = beatBytes, minLatency = min(concurrency, 1)))) with TLFormatNode // the Queue adds at most one cycle { val size = 1 << log2Ceil(1 + address.map(_.max).max - address.map(_.base).min) require (size >= beatBytes) address.foreach { case a => require (a.widen(size-1).base == address.head.widen(size-1).base, s"TLRegisterNode addresses (${address}) must be aligned to its size ${size}") } // Calling this method causes the matching TL2 bundle to be // configured to route all requests to the listed RegFields. def regmap(mapping: RegField.Map) = { val (bundleIn, edge) = this.in(0) val a = bundleIn.a val d = bundleIn.d val fields = TLRegisterRouterExtraField(edge.bundle.sourceBits, edge.bundle.sizeBits) +: a.bits.params.echoFields val params = RegMapperParams(log2Up(size/beatBytes), beatBytes, fields) val in = Wire(Decoupled(new RegMapperInput(params))) in.bits.read := a.bits.opcode === TLMessages.Get in.bits.index := edge.addr_hi(a.bits) in.bits.data := a.bits.data in.bits.mask := a.bits.mask Connectable.waiveUnmatched(in.bits.extra, a.bits.echo) match { case (lhs, rhs) => lhs :<= rhs } val a_extra = in.bits.extra(TLRegisterRouterExtra) a_extra.source := a.bits.source a_extra.size := a.bits.size // Invoke the register map builder val out = RegMapper(beatBytes, concurrency, undefZero, in, mapping:_) // No flow control needed in.valid := a.valid a.ready := in.ready d.valid := out.valid out.ready := d.ready // We must restore the size to enable width adapters to work val d_extra = out.bits.extra(TLRegisterRouterExtra) d.bits := edge.AccessAck(toSource = d_extra.source, lgSize = d_extra.size) // avoid a Mux on the data bus by manually overriding two fields d.bits.data := out.bits.data Connectable.waiveUnmatched(d.bits.echo, out.bits.extra) match { case (lhs, rhs) => lhs :<= rhs } d.bits.opcode := Mux(out.bits.read, TLMessages.AccessAckData, TLMessages.AccessAck) // Tie off unused channels bundleIn.b.valid := false.B bundleIn.c.ready := true.B bundleIn.e.ready := true.B genRegDescsJson(mapping:_) } def genRegDescsJson(mapping: RegField.Map): Unit = { // Dump out the register map for documentation purposes. val base = address.head.base val baseHex = s"0x${base.toInt.toHexString}" val name = s"${device.describe(ResourceBindings()).name}.At${baseHex}" val json = GenRegDescsAnno.serialize(base, name, mapping:_) var suffix = 0 while( ElaborationArtefacts.contains(s"${baseHex}.${suffix}.regmap.json")) { suffix = suffix + 1 } ElaborationArtefacts.add(s"${baseHex}.${suffix}.regmap.json", json) val module = Module.currentModule.get.asInstanceOf[RawModule] GenRegDescsAnno.anno( module, base, mapping:_) } } /* Mix HasTLControlRegMap into any subclass of RegisterRouter to gain helper functions for attaching a device control register map to TileLink. * - The intended use case is that controlNode will diplomatically publish a SW-visible device's memory-mapped control registers. * - Use the clock crossing helper controlXing to externally connect controlNode to a TileLink interconnect. * - Use the mapping helper function regmap to internally fill out the space of device control registers. / trait HasTLControlRegMap { this: RegisterRouter => protected val controlNode = TLRegisterNode( address = address, device = device, deviceKey = "reg/control", concurrency = concurrency, beatBytes = beatBytes, undefZero = undefZero, executable = executable) // Externally, this helper should be used to connect the register control port to a bus val controlXing: TLInwardClockCrossingHelper = this.crossIn(controlNode) // Backwards-compatibility default node accessor with no clock crossing lazy val node: TLInwardNode = controlXing(NoCrossing) // Internally, this function should be used to populate the control port with registers protected def regmap(mapping: RegField.Map): Unit = { controlNode.regmap(mapping:_) } } File MuxLiteral.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.log2Ceil import scala.reflect.ClassTag / MuxLiteral creates a lookup table from a key to a list of values. * Unlike MuxLookup, the table keys must be exclusive literals. / object MuxLiteral { def apply[T <: Data:ClassTag](index: UInt, default: T, first: (UInt, T), rest: (UInt, T)): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[(UInt, T)]): T = MuxTable(index, default, cases.map { case (k, v) => (k.litValue, v) }) } object MuxSeq { def apply[T <: Data:ClassTag](index: UInt, default: T, first: T, rest: T): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[T]): T = MuxTable(index, default, cases.zipWithIndex.map { case (v, i) => (BigInt(i), v) }) } object MuxTable { def apply[T <: Data:ClassTag](index: UInt, default: T, first: (BigInt, T), rest: (BigInt, T)): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[(BigInt, T)]): T = { /* All keys must be >= 0 and distinct / cases.foreach { case (k, _) => require (k >= 0) } require (cases.map(_._1).distinct.size == cases.size) / Filter out any cases identical to the default / val simple = cases.filter { case (k, v) => !default.isLit \|\| !v.isLit \|\| v.litValue != default.litValue } val maxKey = (BigInt(0) +: simple.map(_._1)).max val endIndex = BigInt(1) << log2Ceil(maxKey+1) if (simple.isEmpty) { default } else if (endIndex <= 2simple.size) { /* The dense encoding case uses a Vec / val table = Array.fill(endIndex.toInt) { default } simple.foreach { case (k, v) => table(k.toInt) = v } Mux(index >= endIndex.U, default, VecInit(table)(index)) } else { / The sparse encoding case uses switch / val out = WireDefault(default) simple.foldLeft(new chisel3.util.SwitchContext(index, None, Set.empty)) { case (acc, (k, v)) => acc.is (k.U) { out := v } } out } } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /* Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Debug.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.devices.debug import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.amba.apb.{APBFanout, APBToTL} import freechips.rocketchip.devices.debug.systembusaccess.{SBToTL, SystemBusAccessModule} import freechips.rocketchip.devices.tilelink.{DevNullParams, TLBusBypass, TLError} import freechips.rocketchip.diplomacy.{AddressSet, BufferParams} import freechips.rocketchip.resources.{Description, Device, Resource, ResourceBindings, ResourceString, SimpleDevice} import freechips.rocketchip.interrupts.{IntNexusNode, IntSinkParameters, IntSinkPortParameters, IntSourceParameters, IntSourcePortParameters, IntSyncCrossingSource, IntSyncIdentityNode} import freechips.rocketchip.regmapper.{RegField, RegFieldAccessType, RegFieldDesc, RegFieldGroup, RegFieldWrType, RegReadFn, RegWriteFn} import freechips.rocketchip.rocket.{CSRs, Instructions} import freechips.rocketchip.tile.MaxHartIdBits import freechips.rocketchip.tilelink.{TLAsyncCrossingSink, TLAsyncCrossingSource, TLBuffer, TLRegisterNode, TLXbar} import freechips.rocketchip.util.{Annotated, AsyncBundle, AsyncQueueParams, AsyncResetSynchronizerShiftReg, FromAsyncBundle, ParameterizedBundle, ResetSynchronizerShiftReg, ToAsyncBundle} import freechips.rocketchip.util.SeqBoolBitwiseOps import freechips.rocketchip.util.SeqToAugmentedSeq import freechips.rocketchip.util.BooleanToAugmentedBoolean object DsbBusConsts { def sbAddrWidth = 12 def sbIdWidth = 10 } object DsbRegAddrs{ // These are used by the ROM. def HALTED = 0x100 def GOING = 0x104 def RESUMING = 0x108 def EXCEPTION = 0x10C def WHERETO = 0x300 // This needs to be aligned for up to lq/sq // This shows up in HartInfo, and needs to be aligned // to enable up to LQ/SQ instructions. def DATA = 0x380 // We want DATA to immediately follow PROGBUF so that we can // use them interchangeably. Leave another slot if there is an // implicit ebreak. def PROGBUF(cfg:DebugModuleParams) = { val tmp = DATA - (cfg.nProgramBufferWords 4) if (cfg.hasImplicitEbreak) (tmp - 4) else tmp } // This is unused if hasImpEbreak is false, and just points to the end of the PROGBUF. def IMPEBREAK(cfg: DebugModuleParams) = { DATA - 4 } // We want abstract to be immediately before PROGBUF // because we auto-generate 2 (or 5) instructions. def ABSTRACT(cfg:DebugModuleParams) = PROGBUF(cfg) - (cfg.nAbstractInstructions * 4) def FLAGS = 0x400 def ROMBASE = 0x800 } /** Enumerations used both in the hardware * and in the configuration specification. / object DebugModuleAccessType extends scala.Enumeration { type DebugModuleAccessType = Value val Access8Bit, Access16Bit, Access32Bit, Access64Bit, Access128Bit = Value } object DebugAbstractCommandError extends scala.Enumeration { type DebugAbstractCommandError = Value val Success, ErrBusy, ErrNotSupported, ErrException, ErrHaltResume = Value } object DebugAbstractCommandType extends scala.Enumeration { type DebugAbstractCommandType = Value val AccessRegister, QuickAccess = Value } /* Parameters exposed to the top-level design, set based on * external requirements, etc. * * This object checks that the parameters conform to the * full specification. The implementation which receives this * object can perform more checks on what that implementation * actually supports. * @param nComponents Number of components to support debugging. * @param baseAddress Base offest for debugEntry and debugException * @param nDMIAddrSize Size of the Debug Bus Address * @param nAbstractDataWords Number of 32-bit words for Abstract Commands * @param nProgamBufferWords Number of 32-bit words for Program Buffer * @param hasBusMaster Whether or not a bus master should be included * @param clockGate Whether or not to use dmactive as the clockgate for debug module * @param maxSupportedSBAccess Maximum transaction size supported by System Bus Access logic. * @param supportQuickAccess Whether or not to support the quick access command. * @param supportHartArray Whether or not to implement the hart array register (if >1 hart). * @param nHaltGroups Number of halt groups * @param nExtTriggers Number of external triggers * @param hasHartResets Feature to reset all the currently selected harts * @param hasImplicitEbreak There is an additional RO program buffer word containing an ebreak * @param crossingHasSafeReset Include "safe" logic in Async Crossings so that only one side needs to be reset. / case class DebugModuleParams ( baseAddress : BigInt = BigInt(0), nDMIAddrSize : Int = 7, nProgramBufferWords: Int = 16, nAbstractDataWords : Int = 4, nScratch : Int = 1, hasBusMaster : Boolean = false, clockGate : Boolean = true, maxSupportedSBAccess : Int = 32, supportQuickAccess : Boolean = false, supportHartArray : Boolean = true, nHaltGroups : Int = 1, nExtTriggers : Int = 0, hasHartResets : Boolean = false, hasImplicitEbreak : Boolean = false, hasAuthentication : Boolean = false, crossingHasSafeReset : Boolean = true ) { require ((nDMIAddrSize >= 7) && (nDMIAddrSize <= 32), s"Legal DMIAddrSize is 7-32, not ${nDMIAddrSize}") require ((nAbstractDataWords > 0) && (nAbstractDataWords <= 16), s"Legal nAbstractDataWords is 0-16, not ${nAbstractDataWords}") require ((nProgramBufferWords >= 0) && (nProgramBufferWords <= 16), s"Legal nProgramBufferWords is 0-16, not ${nProgramBufferWords}") require (nHaltGroups < 32, s"Legal nHaltGroups is 0-31, not ${nHaltGroups}") require (nExtTriggers <= 16, s"Legal nExtTriggers is 0-16, not ${nExtTriggers}") if (supportQuickAccess) { // TODO: Check that quick access requirements are met. } def address = AddressSet(baseAddress, 0xFFF) /* the base address of DM / def atzero = (baseAddress == 0) /* The number of generated instructions * * When the base address is not zero, we need more instruction also, * more dscratch registers) to load/store memory mapped data register * because they may no longer be directly addressible with x0 + 12-bit imm / def nAbstractInstructions = if (atzero) 2 else 5 def debugEntry: BigInt = baseAddress + 0x800 def debugException: BigInt = baseAddress + 0x808 def nDscratch: Int = if (atzero) 1 else 2 } object DefaultDebugModuleParams { def apply(xlen:Int /TODO , val configStringAddr: Int/): DebugModuleParams = { new DebugModuleParams().copy( nAbstractDataWords = (if (xlen == 32) 1 else if (xlen == 64) 2 else 4), maxSupportedSBAccess = xlen ) } } case object DebugModuleKey extends Field[Option[DebugModuleParams]](Some(DebugModuleParams())) /* Functional parameters exposed to the design configuration. * * hartIdToHartSel: For systems where hart ids are not 1:1 with hartsel, provide the mapping. * hartSelToHartId: Provide inverse mapping of the above / case class DebugModuleHartSelFuncs ( hartIdToHartSel : (UInt) => UInt = (x:UInt) => x, hartSelToHartId : (UInt) => UInt = (x:UInt) => x ) case object DebugModuleHartSelKey extends Field(DebugModuleHartSelFuncs()) class DebugExtTriggerOut (val nExtTriggers: Int) extends Bundle { val req = Output(UInt(nExtTriggers.W)) val ack = Input(UInt(nExtTriggers.W)) } class DebugExtTriggerIn (val nExtTriggers: Int) extends Bundle { val req = Input(UInt(nExtTriggers.W)) val ack = Output(UInt(nExtTriggers.W)) } class DebugExtTriggerIO () (implicit val p: Parameters) extends ParameterizedBundle()(p) { val out = new DebugExtTriggerOut(p(DebugModuleKey).get.nExtTriggers) val in = new DebugExtTriggerIn (p(DebugModuleKey).get.nExtTriggers) } class DebugAuthenticationIO () (implicit val p: Parameters) extends ParameterizedBundle()(p) { val dmactive = Output(Bool()) val dmAuthWrite = Output(Bool()) val dmAuthRead = Output(Bool()) val dmAuthWdata = Output(UInt(32.W)) val dmAuthBusy = Input(Bool()) val dmAuthRdata = Input(UInt(32.W)) val dmAuthenticated = Input(Bool()) } // ************************************** // Module Interfaces // // ************************************* / Control signals for Inner, generated in Outer * {{{ * run control: resumreq, ackhavereset, halt-on-reset mask * hart select: hasel, hartsel and the hart array mask * }}} / class DebugInternalBundle (val nComponents: Int)(implicit val p: Parameters) extends ParameterizedBundle()(p) { /* resume request / val resumereq = Bool() /* hart select / val hartsel = UInt(10.W) /* reset acknowledge / val ackhavereset = Bool() /* hart array enable / val hasel = Bool() /* hart array mask / val hamask = Vec(nComponents, Bool()) /* halt-on-reset mask / val hrmask = Vec(nComponents, Bool()) } /* structure for top-level Debug Module signals which aren't the bus interfaces. / class DebugCtrlBundle (nComponents: Int)(implicit val p: Parameters) extends ParameterizedBundle()(p) { /* debug availability status for all harts / val debugUnavail = Input(Vec(nComponents, Bool())) /* reset signal * * for every part of the hardware platform, * including every hart, except for the DM and any * logic required to access the DM / val ndreset = Output(Bool()) /* reset signal for the DM itself / val dmactive = Output(Bool()) /* dmactive acknowlege / val dmactiveAck = Input(Bool()) } // ************************************** // Debug Module // // ************************************* / Parameterized version of the Debug Module defined in the * RISC-V Debug Specification * * DebugModule is a slave to two asynchronous masters: * The Debug Bus (DMI) -- This is driven by an external debugger * * The System Bus -- This services requests from the cores. Generally * this interface should only be active at the request * of the debugger, but the Debug Module may also * provide the default MTVEC since it is mapped * to address 0x0. * * DebugModule is responsible for control registers and RAM, and * Debug ROM. It runs partially off of the dmiClk (e.g. TCK) and * the TL clock. Therefore, it is divided into "Outer" portion (running * off dmiClock and dmiReset) and "Inner" (running off tl_clock and tl_reset). * This allows DMCONTROL.haltreq, hartsel, hasel, hawindowsel, hawindow, dmactive, * and ndreset to be modified even while the Core is in reset or not being clocked. * Not all reads from the Debugger to the Debug Module will actually complete * in these scenarios either, they will just block until tl_clock and tl_reset * allow them to complete. This is not strictly necessary for * proper debugger functionality. / // Local reg mapper function : Notify when written, but give the value as well. object WNotifyWire { def apply(n: Int, value: UInt, set: Bool, name: String, desc: String) : RegField = { RegField(n, 0.U, RegWriteFn((valid, data) => { set := valid value := data true.B }), Some(RegFieldDesc(name = name, desc = desc, access = RegFieldAccessType.W))) } } // Local reg mapper function : Notify when accessed either as read or write. object RWNotify { def apply (n: Int, rVal: UInt, wVal: UInt, rNotify: Bool, wNotify: Bool, desc: Option[RegFieldDesc] = None): RegField = { RegField(n, RegReadFn ((ready) => {rNotify := ready ; (true.B, rVal)}), RegWriteFn((valid, data) => { wNotify := valid when (valid) {wVal := data} true.B } ), desc) } } // Local reg mapper function : Notify with value when written, take read input as presented. // This allows checking or correcting the write value before storing it in the register field. object WNotifyVal { def apply(n: Int, rVal: UInt, wVal: UInt, wNotify: Bool, desc: RegFieldDesc): RegField = { RegField(n, rVal, RegWriteFn((valid, data) => { wNotify := valid wVal := data true.B } ), desc) } } class TLDebugModuleOuter(device: Device)(implicit p: Parameters) extends LazyModule { // For Shorter Register Names import DMI_RegAddrs._ val cfg = p(DebugModuleKey).get val intnode = IntNexusNode( sourceFn = { _ => IntSourcePortParameters(Seq(IntSourceParameters(1, Seq(Resource(device, "int"))))) }, sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) }, outputRequiresInput = false) val dmiNode = TLRegisterNode ( address = AddressSet.misaligned(DMI_DMCONTROL << 2, 4) ++ AddressSet.misaligned(DMI_HARTINFO << 2, 4) ++ AddressSet.misaligned(DMI_HAWINDOWSEL << 2, 4) ++ AddressSet.misaligned(DMI_HAWINDOW << 2, 4), device = device, beatBytes = 4, executable = false ) lazy val module = new Impl class Impl extends LazyModuleImp(this) { require (intnode.edges.in.size == 0, "Debug Module does not accept interrupts") val nComponents = intnode.out.size def getNComponents = () => nComponents val supportHartArray = cfg.supportHartArray && (nComponents > 1) // no hart array if only one hart val io = IO(new Bundle { /* structure for top-level Debug Module signals which aren't the bus interfaces. / val ctrl = (new DebugCtrlBundle(nComponents)) /* control signals for Inner, generated in Outer / val innerCtrl = new DecoupledIO(new DebugInternalBundle(nComponents)) /* debug interruption from Inner to Outer * * contains 2 type of debug interruption causes: * - halt group * - halt-on-reset / val hgDebugInt = Input(Vec(nComponents, Bool())) /* hart reset request to core / val hartResetReq = cfg.hasHartResets.option(Output(Vec(nComponents, Bool()))) /* authentication support / val dmAuthenticated = cfg.hasAuthentication.option(Input(Bool())) }) val omRegMap = withReset(reset.asAsyncReset) { // FIXME: Instead of casting reset to ensure it is Async, assert/require reset.Type == AsyncReset (when this feature is available) val dmAuthenticated = io.dmAuthenticated.map( dma => ResetSynchronizerShiftReg(in=dma, sync=3, name=Some("dmAuthenticated_sync"))).getOrElse(true.B) //----DMCONTROL (The whole point of 'Outer' is to maintain this register on dmiClock (e.g. TCK) domain, so that it // can be written even if 'Inner' is not being clocked or is in reset. This allows halting // harts while the rest of the system is in reset. It doesn't really allow any other // register accesses, which will keep returning 'busy' to the debugger interface. val DMCONTROLReset = WireInit(0.U.asTypeOf(new DMCONTROLFields())) val DMCONTROLNxt = WireInit(0.U.asTypeOf(new DMCONTROLFields())) val DMCONTROLReg = RegNext(next=DMCONTROLNxt, init=0.U.asTypeOf(DMCONTROLNxt)).suggestName("DMCONTROLReg") val hartsel_mask = if (nComponents > 1) ((1 << p(MaxHartIdBits)) - 1).U else 0.U val DMCONTROLWrData = WireInit(0.U.asTypeOf(new DMCONTROLFields())) val dmactiveWrEn = WireInit(false.B) val ndmresetWrEn = WireInit(false.B) val clrresethaltreqWrEn = WireInit(false.B) val setresethaltreqWrEn = WireInit(false.B) val hartselloWrEn = WireInit(false.B) val haselWrEn = WireInit(false.B) val ackhaveresetWrEn = WireInit(false.B) val hartresetWrEn = WireInit(false.B) val resumereqWrEn = WireInit(false.B) val haltreqWrEn = WireInit(false.B) val dmactive = DMCONTROLReg.dmactive DMCONTROLNxt := DMCONTROLReg when (~dmactive) { DMCONTROLNxt := DMCONTROLReset } .otherwise { when (dmAuthenticated && ndmresetWrEn) { DMCONTROLNxt.ndmreset := DMCONTROLWrData.ndmreset } when (dmAuthenticated && hartselloWrEn) { DMCONTROLNxt.hartsello := DMCONTROLWrData.hartsello & hartsel_mask} when (dmAuthenticated && haselWrEn) { DMCONTROLNxt.hasel := DMCONTROLWrData.hasel } when (dmAuthenticated && hartresetWrEn) { DMCONTROLNxt.hartreset := DMCONTROLWrData.hartreset } when (dmAuthenticated && haltreqWrEn) { DMCONTROLNxt.haltreq := DMCONTROLWrData.haltreq } } // Put this last to override its own effects. when (dmactiveWrEn) { DMCONTROLNxt.dmactive := DMCONTROLWrData.dmactive } //----HARTINFO // DATA registers are mapped to memory. The dataaddr field of HARTINFO has only // 12 bits and assumes the DM base is 0. If not at 0, then HARTINFO reads as 0 // (implying nonexistence according to the Debug Spec). val HARTINFORdData = WireInit(0.U.asTypeOf(new HARTINFOFields())) if (cfg.atzero) when (dmAuthenticated) { HARTINFORdData.dataaccess := true.B HARTINFORdData.datasize := cfg.nAbstractDataWords.U HARTINFORdData.dataaddr := DsbRegAddrs.DATA.U HARTINFORdData.nscratch := cfg.nScratch.U } //-------------------------------------------------------------- // Hart array mask and window // hamask is hart array mask(1 bit per component), which doesn't include the hart selected by dmcontrol.hartsello // HAWINDOWSEL selects a 32-bit slice of HAMASK to be visible for read/write in HAWINDOW //-------------------------------------------------------------- val hamask = WireInit(VecInit(Seq.fill(nComponents) {false.B} )) def haWindowSize = 32 // The following need to be declared even if supportHartArray is false due to reference // at compile time by dmiNode.regmap val HAWINDOWSELWrData = WireInit(0.U.asTypeOf(new HAWINDOWSELFields())) val HAWINDOWSELWrEn = WireInit(false.B) val HAWINDOWRdData = WireInit(0.U.asTypeOf(new HAWINDOWFields())) val HAWINDOWWrData = WireInit(0.U.asTypeOf(new HAWINDOWFields())) val HAWINDOWWrEn = WireInit(false.B) /* whether the hart is selected / def hartSelected(hart: Int): Bool = { ((io.innerCtrl.bits.hartsel === hart.U) \|\| (if (supportHartArray) io.innerCtrl.bits.hasel && io.innerCtrl.bits.hamask(hart) else false.B)) } val HAWINDOWSELNxt = WireInit(0.U.asTypeOf(new HAWINDOWSELFields())) val HAWINDOWSELReg = RegNext(next=HAWINDOWSELNxt, init=0.U.asTypeOf(HAWINDOWSELNxt)) if (supportHartArray) { val HAWINDOWSELReset = WireInit(0.U.asTypeOf(new HAWINDOWSELFields())) HAWINDOWSELNxt := HAWINDOWSELReg when (~dmactive \|\| ~dmAuthenticated) { HAWINDOWSELNxt := HAWINDOWSELReset } .otherwise { when (HAWINDOWSELWrEn) { // Unneeded upper bits of HAWINDOWSEL are tied to 0. Entire register is 0 if all harts fit in one window if (nComponents > haWindowSize) { HAWINDOWSELNxt.hawindowsel := HAWINDOWSELWrData.hawindowsel & ((1 << (log2Up(nComponents) - 5)) - 1).U } else { HAWINDOWSELNxt.hawindowsel := 0.U } } } val numHAMASKSlices = ((nComponents - 1)/haWindowSize)+1 HAWINDOWRdData.maskdata := 0.U // default, overridden below // for each slice,use a hamaskReg to store the selection info for (ii <- 0 until numHAMASKSlices) { val sliceMask = if (nComponents > ((iihaWindowSize) + haWindowSize-1)) (BigInt(1) << haWindowSize) - 1 // All harts in this slice exist else (BigInt(1)<<(nComponents - (iihaWindowSize))) - 1 // Partial last slice val HAMASKRst = WireInit(0.U.asTypeOf(new HAWINDOWFields())) val HAMASKNxt = WireInit(0.U.asTypeOf(new HAWINDOWFields())) val HAMASKReg = RegNext(next=HAMASKNxt, init=0.U.asTypeOf(HAMASKNxt)) when (ii.U === HAWINDOWSELReg.hawindowsel) { HAWINDOWRdData.maskdata := HAMASKReg.asUInt & sliceMask.U } HAMASKNxt.maskdata := HAMASKReg.asUInt when (~dmactive \|\| ~dmAuthenticated) { HAMASKNxt := HAMASKRst }.otherwise { when (HAWINDOWWrEn && (ii.U === HAWINDOWSELReg.hawindowsel)) { HAMASKNxt.maskdata := HAWINDOWWrData.maskdata } } // drive each slice of hamask with stored HAMASKReg or with new value being written for (jj <- 0 until haWindowSize) { if (((iihaWindowSize) + jj) < nComponents) { val tempWrData = HAWINDOWWrData.maskdata.asBools val tempMaskReg = HAMASKReg.asUInt.asBools when (HAWINDOWWrEn && (ii.U === HAWINDOWSELReg.hawindowsel)) { hamask(iihaWindowSize + jj) := tempWrData(jj) }.otherwise { hamask(iihaWindowSize + jj) := tempMaskReg(jj) } } } } } //-------------------------------------------------------------- // Halt-on-reset // hrmaskReg is current set of harts that should halt-on-reset // Reset state (dmactive=0) is all zeroes // Bits are set by writing 1 to DMCONTROL.setresethaltreq // Bits are cleared by writing 1 to DMCONTROL.clrresethaltreq // Spec says if both are 1, then clrresethaltreq is executed // hrmask is the halt-on-reset mask which will be sent to inner //-------------------------------------------------------------- val hrmask = Wire(Vec(nComponents, Bool())) val hrmaskNxt = Wire(Vec(nComponents, Bool())) val hrmaskReg = RegNext(next=hrmaskNxt, init=0.U.asTypeOf(hrmaskNxt)).suggestName("hrmaskReg") hrmaskNxt := hrmaskReg for (component <- 0 until nComponents) { when (~dmactive \|\| ~dmAuthenticated) { hrmaskNxt(component) := false.B }.elsewhen (clrresethaltreqWrEn && DMCONTROLWrData.clrresethaltreq && hartSelected(component)) { hrmaskNxt(component) := false.B }.elsewhen (setresethaltreqWrEn && DMCONTROLWrData.setresethaltreq && hartSelected(component)) { hrmaskNxt(component) := true.B } } hrmask := hrmaskNxt val dmControlRegFields = RegFieldGroup("dmcontrol", Some("debug module control register"), Seq( WNotifyVal(1, DMCONTROLReg.dmactive & io.ctrl.dmactiveAck, DMCONTROLWrData.dmactive, dmactiveWrEn, RegFieldDesc("dmactive", "debug module active", reset=Some(0))), WNotifyVal(1, DMCONTROLReg.ndmreset, DMCONTROLWrData.ndmreset, ndmresetWrEn, RegFieldDesc("ndmreset", "debug module reset output", reset=Some(0))), WNotifyVal(1, 0.U, DMCONTROLWrData.clrresethaltreq, clrresethaltreqWrEn, RegFieldDesc("clrresethaltreq", "clear reset halt request", reset=Some(0), access=RegFieldAccessType.W)), WNotifyVal(1, 0.U, DMCONTROLWrData.setresethaltreq, setresethaltreqWrEn, RegFieldDesc("setresethaltreq", "set reset halt request", reset=Some(0), access=RegFieldAccessType.W)), RegField(12), if (nComponents > 1) WNotifyVal(p(MaxHartIdBits), DMCONTROLReg.hartsello, DMCONTROLWrData.hartsello, hartselloWrEn, RegFieldDesc("hartsello", "hart select low", reset=Some(0))) else RegField(1), if (nComponents > 1) RegField(10-p(MaxHartIdBits)) else RegField(9), if (supportHartArray) WNotifyVal(1, DMCONTROLReg.hasel, DMCONTROLWrData.hasel, haselWrEn, RegFieldDesc("hasel", "hart array select", reset=Some(0))) else RegField(1), RegField(1), WNotifyVal(1, 0.U, DMCONTROLWrData.ackhavereset, ackhaveresetWrEn, RegFieldDesc("ackhavereset", "acknowledge reset", reset=Some(0), access=RegFieldAccessType.W)), if (cfg.hasHartResets) WNotifyVal(1, DMCONTROLReg.hartreset, DMCONTROLWrData.hartreset, hartresetWrEn, RegFieldDesc("hartreset", "hart reset request", reset=Some(0))) else RegField(1), WNotifyVal(1, 0.U, DMCONTROLWrData.resumereq, resumereqWrEn, RegFieldDesc("resumereq", "resume request", reset=Some(0), access=RegFieldAccessType.W)), WNotifyVal(1, DMCONTROLReg.haltreq, DMCONTROLWrData.haltreq, haltreqWrEn, // Spec says W, but maintaining previous behavior RegFieldDesc("haltreq", "halt request", reset=Some(0))) )) val hartinfoRegFields = RegFieldGroup("dmi_hartinfo", Some("hart information"), Seq( RegField.r(12, HARTINFORdData.dataaddr, RegFieldDesc("dataaddr", "data address", reset=Some(if (cfg.atzero) DsbRegAddrs.DATA else 0))), RegField.r(4, HARTINFORdData.datasize, RegFieldDesc("datasize", "number of DATA registers", reset=Some(if (cfg.atzero) cfg.nAbstractDataWords else 0))), RegField.r(1, HARTINFORdData.dataaccess, RegFieldDesc("dataaccess", "data access type", reset=Some(if (cfg.atzero) 1 else 0))), RegField(3), RegField.r(4, HARTINFORdData.nscratch, RegFieldDesc("nscratch", "number of scratch registers", reset=Some(if (cfg.atzero) cfg.nScratch else 0))) )) //-------------------------------------------------------------- // DMI register decoder for Outer //-------------------------------------------------------------- // regmap addresses are byte offsets from lowest address def DMI_DMCONTROL_OFFSET = 0 def DMI_HARTINFO_OFFSET = ((DMI_HARTINFO - DMI_DMCONTROL) << 2) def DMI_HAWINDOWSEL_OFFSET = ((DMI_HAWINDOWSEL - DMI_DMCONTROL) << 2) def DMI_HAWINDOW_OFFSET = ((DMI_HAWINDOW - DMI_DMCONTROL) << 2) val omRegMap = dmiNode.regmap( DMI_DMCONTROL_OFFSET -> dmControlRegFields, DMI_HARTINFO_OFFSET -> hartinfoRegFields, DMI_HAWINDOWSEL_OFFSET -> (if (supportHartArray && (nComponents > 32)) Seq( WNotifyVal(log2Up(nComponents)-5, HAWINDOWSELReg.hawindowsel, HAWINDOWSELWrData.hawindowsel, HAWINDOWSELWrEn, RegFieldDesc("hawindowsel", "hart array window select", reset=Some(0)))) else Nil), DMI_HAWINDOW_OFFSET -> (if (supportHartArray) Seq( WNotifyVal(if (nComponents > 31) 32 else nComponents, HAWINDOWRdData.maskdata, HAWINDOWWrData.maskdata, HAWINDOWWrEn, RegFieldDesc("hawindow", "hart array window", reset=Some(0), volatile=(nComponents > 32)))) else Nil) ) //-------------------------------------------------------------- // Interrupt Registers //-------------------------------------------------------------- val debugIntNxt = WireInit(VecInit(Seq.fill(nComponents) {false.B} )) val debugIntRegs = RegNext(next=debugIntNxt, init=0.U.asTypeOf(debugIntNxt)).suggestName("debugIntRegs") debugIntNxt := debugIntRegs val (intnode_out, _) = intnode.out.unzip for (component <- 0 until nComponents) { intnode_out(component)(0) := debugIntRegs(component) \| io.hgDebugInt(component) } // sends debug interruption to Core when dmcs.haltreq is set, for (component <- 0 until nComponents) { when (~dmactive \|\| ~dmAuthenticated) { debugIntNxt(component) := false.B }. otherwise { when (haltreqWrEn && ((DMCONTROLWrData.hartsello === component.U) \|\| (if (supportHartArray) DMCONTROLWrData.hasel && hamask(component) else false.B))) { debugIntNxt(component) := DMCONTROLWrData.haltreq } } } // Halt request registers are set & cleared by writes to DMCONTROL.haltreq // resumereq also causes the core to execute a 'dret', // so resumereq is passed through to Inner. // hartsel/hasel/hamask must also be used by the DebugModule state machine, // so it is passed to Inner. // These registers ensure that requests to dmInner are not lost if inner clock isn't running or requests occur too close together. // If the innerCtrl async queue is not ready, the notification will be posted and held until ready is received. // Additional notifications that occur while one is already waiting update the pending data so that the last value written is sent. // Volatile events resumereq and ackhavereset are registered when they occur and remain pending until ready is received. val innerCtrlValid = Wire(Bool()) val innerCtrlValidReg = RegInit(false.B).suggestName("innerCtrlValidReg") val innerCtrlResumeReqReg = RegInit(false.B).suggestName("innerCtrlResumeReqReg") val innerCtrlAckHaveResetReg = RegInit(false.B).suggestName("innerCtrlAckHaveResetReg") innerCtrlValid := hartselloWrEn \| resumereqWrEn \| ackhaveresetWrEn \| setresethaltreqWrEn \| clrresethaltreqWrEn \| haselWrEn \| (HAWINDOWWrEn & supportHartArray.B) innerCtrlValidReg := io.innerCtrl.valid & ~io.innerCtrl.ready // Hold innerctrl request until the async queue accepts it innerCtrlResumeReqReg := io.innerCtrl.bits.resumereq & ~io.innerCtrl.ready // Hold resumereq until accepted innerCtrlAckHaveResetReg := io.innerCtrl.bits.ackhavereset & ~io.innerCtrl.ready // Hold ackhavereset until accepted io.innerCtrl.valid := innerCtrlValid \| innerCtrlValidReg io.innerCtrl.bits.hartsel := Mux(hartselloWrEn, DMCONTROLWrData.hartsello, DMCONTROLReg.hartsello) io.innerCtrl.bits.resumereq := (resumereqWrEn & DMCONTROLWrData.resumereq) \| innerCtrlResumeReqReg io.innerCtrl.bits.ackhavereset := (ackhaveresetWrEn & DMCONTROLWrData.ackhavereset) \| innerCtrlAckHaveResetReg io.innerCtrl.bits.hrmask := hrmask if (supportHartArray) { io.innerCtrl.bits.hasel := Mux(haselWrEn, DMCONTROLWrData.hasel, DMCONTROLReg.hasel) io.innerCtrl.bits.hamask := hamask } else { io.innerCtrl.bits.hasel := DontCare io.innerCtrl.bits.hamask := DontCare } io.ctrl.ndreset := DMCONTROLReg.ndmreset io.ctrl.dmactive := DMCONTROLReg.dmactive // hart reset mechanism implementation if (cfg.hasHartResets) { val hartResetNxt = Wire(Vec(nComponents, Bool())) val hartResetReg = RegNext(next=hartResetNxt, init=0.U.asTypeOf(hartResetNxt)) for (component <- 0 until nComponents) { hartResetNxt(component) := DMCONTROLReg.hartreset & hartSelected(component) io.hartResetReq.get(component) := hartResetReg(component) } } omRegMap // FIXME: Remove this when withReset is removed }} } // wrap a Outer with a DMIToTL, derived by dmi clock & reset class TLDebugModuleOuterAsync(device: Device)(implicit p: Parameters) extends LazyModule { val cfg = p(DebugModuleKey).get val dmiXbar = LazyModule (new TLXbar(nameSuffix = Some("dmixbar"))) val dmi2tlOpt = (!p(ExportDebug).apb).option({ val dmi2tl = LazyModule(new DMIToTL()) dmiXbar.node := dmi2tl.node dmi2tl }) val apbNodeOpt = p(ExportDebug).apb.option({ val apb2tl = LazyModule(new APBToTL()) val apb2tlBuffer = LazyModule(new TLBuffer(BufferParams.pipe)) val dmTopAddr = (1 << cfg.nDMIAddrSize) << 2 val tlErrorParams = DevNullParams(AddressSet.misaligned(dmTopAddr, APBDebugConsts.apbDebugRegBase-dmTopAddr), maxAtomic=0, maxTransfer=4) val tlError = LazyModule(new TLError(tlErrorParams, buffer=false)) val apbXbar = LazyModule(new APBFanout()) val apbRegs = LazyModule(new APBDebugRegisters()) apbRegs.node := apbXbar.node apb2tl.node := apbXbar.node apb2tlBuffer.node := apb2tl.node dmiXbar.node := apb2tlBuffer.node tlError.node := dmiXbar.node apbXbar.node }) val dmOuter = LazyModule( new TLDebugModuleOuter(device)) val intnode = IntSyncIdentityNode() intnode := IntSyncCrossingSource(alreadyRegistered = true) := dmOuter.intnode val dmiBypass = LazyModule(new TLBusBypass(beatBytes=4, bufferError=false, maxAtomic=0, maxTransfer=4)) val dmiInnerNode = TLAsyncCrossingSource() := dmiBypass.node := dmiXbar.node dmOuter.dmiNode := dmiXbar.node lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { val nComponents = dmOuter.intnode.edges.out.size val io = IO(new Bundle { val dmi_clock = Input(Clock()) val dmi_reset = Input(Reset()) /** Debug Module Interface bewteen DM and DTM * * The DTM provides access to one or more Debug Modules (DMs) using DMI / val dmi = (!p(ExportDebug).apb).option(Flipped(new DMIIO()(p))) // Optional APB Interface is fully diplomatic so is not listed here. val ctrl = new DebugCtrlBundle(nComponents) /* conrol signals for Inner, generated in Outer / val innerCtrl = new AsyncBundle(new DebugInternalBundle(nComponents), AsyncQueueParams.singleton(safe=cfg.crossingHasSafeReset)) /* debug interruption generated in Inner / val hgDebugInt = Input(Vec(nComponents, Bool())) /* hart reset request to core / val hartResetReq = p(DebugModuleKey).get.hasHartResets.option(Output(Vec(nComponents, Bool()))) /* Authentication signal from core / val dmAuthenticated = p(DebugModuleKey).get.hasAuthentication.option(Input(Bool())) }) val rf_reset = IO(Input(Reset())) // RF transform childClock := io.dmi_clock childReset := io.dmi_reset override def provideImplicitClockToLazyChildren = true withClockAndReset(childClock, childReset) { dmi2tlOpt.foreach { _.module.io.dmi <> io.dmi.get } val dmactiveAck = AsyncResetSynchronizerShiftReg(in=io.ctrl.dmactiveAck, sync=3, name=Some("dmactiveAckSync")) dmiBypass.module.io.bypass := ~io.ctrl.dmactive \| ~dmactiveAck io.ctrl <> dmOuter.module.io.ctrl dmOuter.module.io.ctrl.dmactiveAck := dmactiveAck // send synced version down to dmOuter io.innerCtrl <> ToAsyncBundle(dmOuter.module.io.innerCtrl, AsyncQueueParams.singleton(safe=cfg.crossingHasSafeReset)) dmOuter.module.io.hgDebugInt := io.hgDebugInt io.hartResetReq.foreach { x => dmOuter.module.io.hartResetReq.foreach {y => x := y}} io.dmAuthenticated.foreach { x => dmOuter.module.io.dmAuthenticated.foreach { y => y := x}} } } } class TLDebugModuleInner(device: Device, getNComponents: () => Int, beatBytes: Int)(implicit p: Parameters) extends LazyModule { // For Shorter Register Names import DMI_RegAddrs._ val cfg = p(DebugModuleKey).get def getCfg = () => cfg val dmTopAddr = (1 << cfg.nDMIAddrSize) << 2 /* dmiNode address set / val dmiNode = TLRegisterNode( // Address is range 0 to 0x1FF except DMCONTROL, HARTINFO, HAWINDOWSEL, HAWINDOW which are handled by Outer address = AddressSet.misaligned(0, DMI_DMCONTROL << 2) ++ AddressSet.misaligned((DMI_DMCONTROL + 1) << 2, ((DMI_HARTINFO << 2) - ((DMI_DMCONTROL + 1) << 2))) ++ AddressSet.misaligned((DMI_HARTINFO + 1) << 2, ((DMI_HAWINDOWSEL << 2) - ((DMI_HARTINFO + 1) << 2))) ++ AddressSet.misaligned((DMI_HAWINDOW + 1) << 2, (dmTopAddr - ((DMI_HAWINDOW + 1) << 2))), device = device, beatBytes = 4, executable = false ) val tlNode = TLRegisterNode( address=Seq(cfg.address), device=device, beatBytes=beatBytes, executable=true ) val sb2tlOpt = cfg.hasBusMaster.option(LazyModule(new SBToTL())) // If we want to support custom registers read through Abstract Commands, // provide a place to bring them into the debug module. What this connects // to is up to the implementation. val customNode = new DebugCustomSink() lazy val module = new Impl class Impl extends LazyModuleImp(this){ val nComponents = getNComponents() Annotated.params(this, cfg) val supportHartArray = cfg.supportHartArray & (nComponents > 1) val nExtTriggers = cfg.nExtTriggers val nHaltGroups = if ((nComponents > 1) \| (nExtTriggers > 0)) cfg.nHaltGroups else 0 // no halt groups possible if single hart with no external triggers val hartSelFuncs = if (getNComponents() > 1) p(DebugModuleHartSelKey) else DebugModuleHartSelFuncs( hartIdToHartSel = (x) => 0.U, hartSelToHartId = (x) => x ) val io = IO(new Bundle { /* dm reset signal passed in from Outer / val dmactive = Input(Bool()) /* conrol signals for Inner * * it's generated by Outer and comes in / val innerCtrl = Flipped(new DecoupledIO(new DebugInternalBundle(nComponents))) /* debug unavail signal passed in from Outer/ val debugUnavail = Input(Vec(nComponents, Bool())) /* debug interruption from Inner to Outer * * contain 2 type of debug interruption causes: * - halt group * - halt-on-reset / val hgDebugInt = Output(Vec(nComponents, Bool())) /* interface for trigger / val extTrigger = (nExtTriggers > 0).option(new DebugExtTriggerIO()) /* vector to indicate which hart is in reset * * dm receives it from core and sends it to Inner / val hartIsInReset = Input(Vec(nComponents, Bool())) val tl_clock = Input(Clock()) val tl_reset = Input(Reset()) /* Debug Authentication signals from core / val auth = cfg.hasAuthentication.option(new DebugAuthenticationIO()) }) sb2tlOpt.map { sb => sb.module.clock := io.tl_clock sb.module.reset := io.tl_reset sb.module.rf_reset := io.tl_reset } //-------------------------------------------------------------- // Import constants for shorter variable names //-------------------------------------------------------------- import DMI_RegAddrs._ import DsbRegAddrs._ import DsbBusConsts._ //-------------------------------------------------------------- // Sanity Check Configuration For this implementation. //-------------------------------------------------------------- require (cfg.supportQuickAccess == false, "No Quick Access support yet") require ((nHaltGroups > 0) \|\| (nExtTriggers == 0), "External triggers require at least 1 halt group") //-------------------------------------------------------------- // Register & Wire Declarations (which need to be pre-declared) //-------------------------------------------------------------- // run control regs: tracking all the harts // implements: see implementation-specific bits part /* all harts halted status / val haltedBitRegs = Reg(UInt(nComponents.W)) /* all harts resume request status / val resumeReqRegs = Reg(UInt(nComponents.W)) /* all harts have reset status / val haveResetBitRegs = Reg(UInt(nComponents.W)) // default is 1,after resume, resumeAcks get 0 /* all harts resume ack status / val resumeAcks = Wire(UInt(nComponents.W)) // --- regmapper outputs // hart state Id and En // in Hart Bus Access ROM val hartHaltedWrEn = Wire(Bool()) val hartHaltedId = Wire(UInt(sbIdWidth.W)) val hartGoingWrEn = Wire(Bool()) val hartGoingId = Wire(UInt(sbIdWidth.W)) val hartResumingWrEn = Wire(Bool()) val hartResumingId = Wire(UInt(sbIdWidth.W)) val hartExceptionWrEn = Wire(Bool()) val hartExceptionId = Wire(UInt(sbIdWidth.W)) // progbuf and abstract data: byte-addressable control logic // AccessLegal is set only when state = waiting // RdEn and WrEnMaybe : contrl signal drived by DMI bus val dmiProgramBufferRdEn = WireInit(VecInit(Seq.fill(cfg.nProgramBufferWords 4) {false.B} )) val dmiProgramBufferAccessLegal = WireInit(false.B) val dmiProgramBufferWrEnMaybe = WireInit(VecInit(Seq.fill(cfg.nProgramBufferWords * 4) {false.B} )) val dmiAbstractDataRdEn = WireInit(VecInit(Seq.fill(cfg.nAbstractDataWords * 4) {false.B} )) val dmiAbstractDataAccessLegal = WireInit(false.B) val dmiAbstractDataWrEnMaybe = WireInit(VecInit(Seq.fill(cfg.nAbstractDataWords * 4) {false.B} )) //-------------------------------------------------------------- // Registers coming from 'CONTROL' in Outer //-------------------------------------------------------------- val dmAuthenticated = io.auth.map(a => a.dmAuthenticated).getOrElse(true.B) val selectedHartReg = Reg(UInt(p(MaxHartIdBits).W)) // hamaskFull is a vector of all selected harts including hartsel, whether or not supportHartArray is true val hamaskFull = WireInit(VecInit(Seq.fill(nComponents) {false.B} )) if (nComponents > 1) { when (~io.dmactive) { selectedHartReg := 0.U }.elsewhen (io.innerCtrl.fire){ selectedHartReg := io.innerCtrl.bits.hartsel } } if (supportHartArray) { val hamaskZero = WireInit(VecInit(Seq.fill(nComponents) {false.B} )) val hamaskReg = Reg(Vec(nComponents, Bool())) when (~io.dmactive \|\| ~dmAuthenticated) { hamaskReg := hamaskZero }.elsewhen (io.innerCtrl.fire){ hamaskReg := Mux(io.innerCtrl.bits.hasel, io.innerCtrl.bits.hamask, hamaskZero) } hamaskFull := hamaskReg } // Outer.hamask doesn't consider the hart selected by dmcontrol.hartsello, // so append it here when (selectedHartReg < nComponents.U) { hamaskFull(if (nComponents == 1) 0.U(0.W) else selectedHartReg) := true.B } io.innerCtrl.ready := true.B // Construct a Vec from io.innerCtrl fields indicating whether each hart is being selected in this write // A hart may be selected by hartsel field or by hart array val hamaskWrSel = WireInit(VecInit(Seq.fill(nComponents) {false.B} )) for (component <- 0 until nComponents ) { hamaskWrSel(component) := ((io.innerCtrl.bits.hartsel === component.U) \|\| (if (supportHartArray) io.innerCtrl.bits.hasel && io.innerCtrl.bits.hamask(component) else false.B)) } //------------------------------------- // Halt-on-reset logic // hrmask is set in dmOuter and passed in // Debug interrupt is generated when a reset occurs whose corresponding hrmask bit is set // Debug interrupt is maintained until the hart enters halted state //------------------------------------- val hrReset = WireInit(VecInit(Seq.fill(nComponents) { false.B } )) val hrDebugInt = Wire(Vec(nComponents, Bool())) val hrmaskReg = RegInit(hrReset) val hartIsInResetSync = Wire(Vec(nComponents, Bool())) for (component <- 0 until nComponents) { hartIsInResetSync(component) := AsyncResetSynchronizerShiftReg(io.hartIsInReset(component), 3, Some(s"debug_hartReset_$component")) } when (~io.dmactive \|\| ~dmAuthenticated) { hrmaskReg := hrReset }.elsewhen (io.innerCtrl.fire){ hrmaskReg := io.innerCtrl.bits.hrmask } withReset(reset.asAsyncReset) { // ensure interrupt requests are negated at first clock edge val hrDebugIntReg = RegInit(VecInit(Seq.fill(nComponents) { false.B } )) when (~io.dmactive \|\| ~dmAuthenticated) { hrDebugIntReg := hrReset }.otherwise { hrDebugIntReg := hrmaskReg & (hartIsInResetSync \| // set debugInt during reset (hrDebugIntReg & ~(haltedBitRegs.asBools))) // maintain until core halts } hrDebugInt := hrDebugIntReg } //-------------------------------------------------------------- // DMI Registers //-------------------------------------------------------------- //----DMSTATUS val DMSTATUSRdData = WireInit(0.U.asTypeOf(new DMSTATUSFields())) DMSTATUSRdData.authenticated := dmAuthenticated DMSTATUSRdData.version := 2.U // Version 0.13 io.auth.map(a => DMSTATUSRdData.authbusy := a.dmAuthBusy) val resumereq = io.innerCtrl.fire && io.innerCtrl.bits.resumereq when (dmAuthenticated) { DMSTATUSRdData.hasresethaltreq := true.B DMSTATUSRdData.anynonexistent := (selectedHartReg >= nComponents.U) // only hartsel can be nonexistent // all harts nonexistent if hartsel is out of range and there are no harts selected in the hart array DMSTATUSRdData.allnonexistent := (selectedHartReg >= nComponents.U) & (~hamaskFull.reduce(_ \| _)) when (~DMSTATUSRdData.allnonexistent) { // if no existent harts selected, all other status is false DMSTATUSRdData.anyunavail := (io.debugUnavail & hamaskFull).reduce(_ \| _) DMSTATUSRdData.anyhalted := ((~io.debugUnavail & (haltedBitRegs.asBools)) & hamaskFull).reduce(_ \| _) DMSTATUSRdData.anyrunning := ((~io.debugUnavail & ~(haltedBitRegs.asBools)) & hamaskFull).reduce(_ \| _) DMSTATUSRdData.anyhavereset := (haveResetBitRegs.asBools & hamaskFull).reduce(_ \| _) DMSTATUSRdData.anyresumeack := (resumeAcks.asBools & hamaskFull).reduce(_ \| _) when (~DMSTATUSRdData.anynonexistent) { // if one hart is nonexistent, no 'all' status is set DMSTATUSRdData.allunavail := (io.debugUnavail \| ~hamaskFull).reduce(_ & _) DMSTATUSRdData.allhalted := ((~io.debugUnavail & (haltedBitRegs.asBools)) \| ~hamaskFull).reduce(_ & _) DMSTATUSRdData.allrunning := ((~io.debugUnavail & ~(haltedBitRegs.asBools)) \| ~hamaskFull).reduce(_ & _) DMSTATUSRdData.allhavereset := (haveResetBitRegs.asBools \| ~hamaskFull).reduce(_ & _) DMSTATUSRdData.allresumeack := (resumeAcks.asBools \| ~hamaskFull).reduce(_ & _) } } //TODO DMSTATUSRdData.confstrptrvalid := false.B DMSTATUSRdData.impebreak := (cfg.hasImplicitEbreak).B } when(~io.dmactive \|\| ~dmAuthenticated) { haveResetBitRegs := 0.U }.otherwise { when (io.innerCtrl.fire && io.innerCtrl.bits.ackhavereset) { haveResetBitRegs := (haveResetBitRegs & (~(hamaskWrSel.asUInt))) \| hartIsInResetSync.asUInt }.otherwise { haveResetBitRegs := haveResetBitRegs \| hartIsInResetSync.asUInt } } //----DMCS2 (Halt Groups) val DMCS2RdData = WireInit(0.U.asTypeOf(new DMCS2Fields())) val DMCS2WrData = WireInit(0.U.asTypeOf(new DMCS2Fields())) val hgselectWrEn = WireInit(false.B) val hgwriteWrEn = WireInit(false.B) val haltgroupWrEn = WireInit(false.B) val exttriggerWrEn = WireInit(false.B) val hgDebugInt = WireInit(VecInit(Seq.fill(nComponents) {false.B} )) if (nHaltGroups > 0) withReset (reset.asAsyncReset) { // async reset ensures triggers don't falsely fire during startup val hgBits = log2Up(nHaltGroups) // hgParticipate: Each entry indicates which hg that entity belongs to (1 to nHartGroups). 0 means no hg assigned. val hgParticipateHart = RegInit(VecInit(Seq.fill(nComponents)(0.U(hgBits.W)))) val hgParticipateTrig = if (nExtTriggers > 0) RegInit(VecInit(Seq.fill(nExtTriggers)(0.U(hgBits.W)))) else Nil // assign group index to current seledcted harts for (component <- 0 until nComponents) { when (~io.dmactive \|\| ~dmAuthenticated) { hgParticipateHart(component) := 0.U }.otherwise { when (haltgroupWrEn & DMCS2WrData.hgwrite & ~DMCS2WrData.hgselect & hamaskFull(component) & (DMCS2WrData.haltgroup <= nHaltGroups.U)) { hgParticipateHart(component) := DMCS2WrData.haltgroup } } } DMCS2RdData.haltgroup := hgParticipateHart(if (nComponents == 1) 0.U(0.W) else selectedHartReg) if (nExtTriggers > 0) { val hgSelect = Reg(Bool()) when (~io.dmactive \|\| ~dmAuthenticated) { hgSelect := false.B }.otherwise { when (hgselectWrEn) { hgSelect := DMCS2WrData.hgselect } } // assign group index to trigger for (trigger <- 0 until nExtTriggers) { when (~io.dmactive \|\| ~dmAuthenticated) { hgParticipateTrig(trigger) := 0.U }.otherwise { when (haltgroupWrEn & DMCS2WrData.hgwrite & DMCS2WrData.hgselect & (DMCS2WrData.exttrigger === trigger.U) & (DMCS2WrData.haltgroup <= nHaltGroups.U)) { hgParticipateTrig(trigger) := DMCS2WrData.haltgroup } } } DMCS2RdData.hgselect := hgSelect when (hgSelect) { DMCS2RdData.haltgroup := hgParticipateTrig(0) } // If there is only 1 ext trigger, then the exttrigger field is fixed at 0 // Otherwise, instantiate a register with only the number of bits required if (nExtTriggers > 1) { val trigBits = log2Up(nExtTriggers-1) val hgExtTrigger = Reg(UInt(trigBits.W)) when (~io.dmactive \|\| ~dmAuthenticated) { hgExtTrigger := 0.U }.otherwise { when (exttriggerWrEn & (DMCS2WrData.exttrigger < nExtTriggers.U)) { hgExtTrigger := DMCS2WrData.exttrigger } } DMCS2RdData.exttrigger := hgExtTrigger when (hgSelect) { DMCS2RdData.haltgroup := hgParticipateTrig(hgExtTrigger) } } } // Halt group state machine // IDLE: Go to FIRED when any hart in this hg writes to HALTED while its HaltedBitRegs=0 // or when any trigin assigned to this hg occurs // FIRED: Back to IDLE when all harts in this hg have set their haltedBitRegs // and all trig out in this hg have been acknowledged val hgFired = RegInit (VecInit(Seq.fill(nHaltGroups+1) {false.B} )) val hgHartFiring = WireInit(VecInit(Seq.fill(nHaltGroups+1) {false.B} )) // which hg's are firing due to hart halting val hgTrigFiring = WireInit(VecInit(Seq.fill(nHaltGroups+1) {false.B} )) // which hg's are firing due to trig in val hgHartsAllHalted = WireInit(VecInit(Seq.fill(nHaltGroups+1) {false.B} )) // in which hg's have all harts halted val hgTrigsAllAcked = WireInit(VecInit(Seq.fill(nHaltGroups+1) { true.B} )) // in which hg's have all trigouts been acked io.extTrigger.foreach {extTrigger => val extTriggerInReq = Wire(Vec(nExtTriggers, Bool())) val extTriggerOutAck = Wire(Vec(nExtTriggers, Bool())) extTriggerInReq := extTrigger.in.req.asBools extTriggerOutAck := extTrigger.out.ack.asBools val trigInReq = ResetSynchronizerShiftReg(in=extTriggerInReq, sync=3, name=Some("dm_extTriggerInReqSync")) val trigOutAck = ResetSynchronizerShiftReg(in=extTriggerOutAck, sync=3, name=Some("dm_extTriggerOutAckSync")) for (hg <- 1 to nHaltGroups) { hgTrigFiring(hg) := (trigInReq & ~RegNext(trigInReq) & hgParticipateTrig.map(_ === hg.U)).reduce(_ \| _) hgTrigsAllAcked(hg) := (trigOutAck \| hgParticipateTrig.map(_ =/= hg.U)).reduce(_ & _) } extTrigger.in.ack := trigInReq.asUInt } for (hg <- 1 to nHaltGroups) { hgHartFiring(hg) := hartHaltedWrEn & ~haltedBitRegs(hartHaltedId) & (hgParticipateHart(hartSelFuncs.hartIdToHartSel(hartHaltedId)) === hg.U) hgHartsAllHalted(hg) := (haltedBitRegs.asBools \| hgParticipateHart.map(_ =/= hg.U)).reduce(_ & _) when (~io.dmactive \|\| ~dmAuthenticated) { hgFired(hg) := false.B }.elsewhen (~hgFired(hg) & (hgHartFiring(hg) \| hgTrigFiring(hg))) { hgFired(hg) := true.B }.elsewhen ( hgFired(hg) & hgHartsAllHalted(hg) & hgTrigsAllAcked(hg)) { hgFired(hg) := false.B } } // For each hg that has fired, assert debug interrupt to each hart in that hg for (component <- 0 until nComponents) { hgDebugInt(component) := hgFired(hgParticipateHart(component)) } // For each hg that has fired, assert trigger out for all external triggers in that hg io.extTrigger.foreach {extTrigger => val extTriggerOutReq = RegInit(VecInit(Seq.fill(cfg.nExtTriggers) {false.B} )) for (trig <- 0 until nExtTriggers) { extTriggerOutReq(trig) := hgFired(hgParticipateTrig(trig)) } extTrigger.out.req := extTriggerOutReq.asUInt } } io.hgDebugInt := hgDebugInt \| hrDebugInt //----HALTSUM* val numHaltedStatus = ((nComponents - 1) / 32) + 1 val haltedStatus = Wire(Vec(numHaltedStatus, Bits(32.W))) for (ii <- 0 until numHaltedStatus) { when (dmAuthenticated) { haltedStatus(ii) := haltedBitRegs >> (ii32) }.otherwise { haltedStatus(ii) := 0.U } } val haltedSummary = Cat(haltedStatus.map(_.orR).reverse) val HALTSUM1RdData = haltedSummary.asTypeOf(new HALTSUM1Fields()) val selectedHaltedStatus = Mux((selectedHartReg >> 5) > numHaltedStatus.U, 0.U, haltedStatus(selectedHartReg >> 5)) val HALTSUM0RdData = selectedHaltedStatus.asTypeOf(new HALTSUM0Fields()) // Since we only support 1024 harts, we don't implement HALTSUM2 or HALTSUM3 //----ABSTRACTCS val ABSTRACTCSReset = WireInit(0.U.asTypeOf(new ABSTRACTCSFields())) ABSTRACTCSReset.datacount := cfg.nAbstractDataWords.U ABSTRACTCSReset.progbufsize := cfg.nProgramBufferWords.U val ABSTRACTCSReg = Reg(new ABSTRACTCSFields()) val ABSTRACTCSWrData = WireInit(0.U.asTypeOf(new ABSTRACTCSFields())) val ABSTRACTCSRdData = WireInit(ABSTRACTCSReg) val ABSTRACTCSRdEn = WireInit(false.B) val ABSTRACTCSWrEnMaybe = WireInit(false.B) val ABSTRACTCSWrEnLegal = WireInit(false.B) val ABSTRACTCSWrEn = ABSTRACTCSWrEnMaybe && ABSTRACTCSWrEnLegal // multiple error types // find implement in the state machine part val errorBusy = WireInit(false.B) val errorException = WireInit(false.B) val errorUnsupported = WireInit(false.B) val errorHaltResume = WireInit(false.B) when (~io.dmactive \|\| ~dmAuthenticated) { ABSTRACTCSReg := ABSTRACTCSReset }.otherwise { when (errorBusy){ ABSTRACTCSReg.cmderr := DebugAbstractCommandError.ErrBusy.id.U }.elsewhen (errorException) { ABSTRACTCSReg.cmderr := DebugAbstractCommandError.ErrException.id.U }.elsewhen (errorUnsupported) { ABSTRACTCSReg.cmderr := DebugAbstractCommandError.ErrNotSupported.id.U }.elsewhen (errorHaltResume) { ABSTRACTCSReg.cmderr := DebugAbstractCommandError.ErrHaltResume.id.U }.otherwise { //W1C when (ABSTRACTCSWrEn){ ABSTRACTCSReg.cmderr := ABSTRACTCSReg.cmderr & ~(ABSTRACTCSWrData.cmderr); } } } // For busy, see below state machine. val abstractCommandBusy = WireInit(true.B) ABSTRACTCSRdData.busy := abstractCommandBusy when (~dmAuthenticated) { // read value must be 0 when not authenticated ABSTRACTCSRdData.datacount := 0.U ABSTRACTCSRdData.progbufsize := 0.U } //---- ABSTRACTAUTO // It is a mask indicating whether datai/probufi have the autoexcution permisson // this part aims to produce 3 wires : autoexecData,autoexecProg,autoexec // first two specify which reg supports autoexec // autoexec is a control signal, meaning there is at least one enabled autoexec reg // when autoexec is set, generate instructions using COMMAND register val ABSTRACTAUTOReset = WireInit(0.U.asTypeOf(new ABSTRACTAUTOFields())) val ABSTRACTAUTOReg = Reg(new ABSTRACTAUTOFields()) val ABSTRACTAUTOWrData = WireInit(0.U.asTypeOf(new ABSTRACTAUTOFields())) val ABSTRACTAUTORdData = WireInit(ABSTRACTAUTOReg) val ABSTRACTAUTORdEn = WireInit(false.B) val autoexecdataWrEnMaybe = WireInit(false.B) val autoexecprogbufWrEnMaybe = WireInit(false.B) val ABSTRACTAUTOWrEnLegal = WireInit(false.B) when (~io.dmactive \|\| ~dmAuthenticated) { ABSTRACTAUTOReg := ABSTRACTAUTOReset }.otherwise { when (autoexecprogbufWrEnMaybe && ABSTRACTAUTOWrEnLegal) { ABSTRACTAUTOReg.autoexecprogbuf := ABSTRACTAUTOWrData.autoexecprogbuf & ( (1 << cfg.nProgramBufferWords) - 1).U } when (autoexecdataWrEnMaybe && ABSTRACTAUTOWrEnLegal) { ABSTRACTAUTOReg.autoexecdata := ABSTRACTAUTOWrData.autoexecdata & ( (1 << cfg.nAbstractDataWords) - 1).U } } // Abstract Data access vector(byte-addressable) val dmiAbstractDataAccessVec = WireInit(VecInit(Seq.fill(cfg.nAbstractDataWords 4) {false.B} )) dmiAbstractDataAccessVec := (dmiAbstractDataWrEnMaybe zip dmiAbstractDataRdEn).map{ case (r,w) => r \| w} // Program Buffer access vector(byte-addressable) val dmiProgramBufferAccessVec = WireInit(VecInit(Seq.fill(cfg.nProgramBufferWords * 4) {false.B} )) dmiProgramBufferAccessVec := (dmiProgramBufferWrEnMaybe zip dmiProgramBufferRdEn).map{ case (r,w) => r \| w} // at least one word access val dmiAbstractDataAccess = dmiAbstractDataAccessVec.reduce(_ \|\| _ ) val dmiProgramBufferAccess = dmiProgramBufferAccessVec.reduce(_ \|\| _) // This will take the shorter of the lists, which is what we want. val autoexecData = WireInit(VecInit(Seq.fill(cfg.nAbstractDataWords) {false.B} )) val autoexecProg = WireInit(VecInit(Seq.fill(cfg.nProgramBufferWords) {false.B} )) (autoexecData zip ABSTRACTAUTOReg.autoexecdata.asBools).zipWithIndex.foreach {case (t, i) => t._1 := dmiAbstractDataAccessVec(i * 4) && t._2 } (autoexecProg zip ABSTRACTAUTOReg.autoexecprogbuf.asBools).zipWithIndex.foreach {case (t, i) => t._1 := dmiProgramBufferAccessVec(i * 4) && t._2} val autoexec = autoexecData.reduce(_ \|\| _) \|\| autoexecProg.reduce(_ \|\| _) //---- COMMAND val COMMANDReset = WireInit(0.U.asTypeOf(new COMMANDFields())) val COMMANDReg = Reg(new COMMANDFields()) val COMMANDWrDataVal = WireInit(0.U(32.W)) val COMMANDWrData = WireInit(COMMANDWrDataVal.asTypeOf(new COMMANDFields())) val COMMANDWrEnMaybe = WireInit(false.B) val COMMANDWrEnLegal = WireInit(false.B) val COMMANDRdEn = WireInit(false.B) val COMMANDWrEn = COMMANDWrEnMaybe && COMMANDWrEnLegal val COMMANDRdData = COMMANDReg when (~io.dmactive \|\| ~dmAuthenticated) { COMMANDReg := COMMANDReset }.otherwise { when (COMMANDWrEn) { COMMANDReg := COMMANDWrData } } // --- Abstract Data // These are byte addressible, s.t. the Processor can use // byte-addressible instructions to store to them. val abstractDataMem = Reg(Vec(cfg.nAbstractDataWords4, UInt(8.W))) val abstractDataNxt = WireInit(abstractDataMem) // --- Program Buffer // byte-addressible mem val programBufferMem = Reg(Vec(cfg.nProgramBufferWords4, UInt(8.W))) val programBufferNxt = WireInit(programBufferMem) //-------------------------------------------------------------- // These bits are implementation-specific bits set // by harts executing code. //-------------------------------------------------------------- // Run control logic when (~io.dmactive \|\| ~dmAuthenticated) { haltedBitRegs := 0.U resumeReqRegs := 0.U }.otherwise { //remove those harts in reset resumeReqRegs := resumeReqRegs & ~(hartIsInResetSync.asUInt) val hartHaltedIdIndex = UIntToOH(hartSelFuncs.hartIdToHartSel(hartHaltedId)) val hartResumingIdIndex = UIntToOH(hartSelFuncs.hartIdToHartSel(hartResumingId)) val hartselIndex = UIntToOH(io.innerCtrl.bits.hartsel) when (hartHaltedWrEn) { // add those harts halting and remove those in reset haltedBitRegs := (haltedBitRegs \| hartHaltedIdIndex) & ~(hartIsInResetSync.asUInt) }.elsewhen (hartResumingWrEn) { // remove those harts in reset and those in resume haltedBitRegs := (haltedBitRegs & ~(hartResumingIdIndex)) & ~(hartIsInResetSync.asUInt) }.otherwise { // remove those harts in reset haltedBitRegs := haltedBitRegs & ~(hartIsInResetSync.asUInt) } when (hartResumingWrEn) { // remove those harts in resume and those in reset resumeReqRegs := (resumeReqRegs & ~(hartResumingIdIndex)) & ~(hartIsInResetSync.asUInt) } when (resumereq) { // set all sleceted harts to resumeReq, remove those in reset resumeReqRegs := (resumeReqRegs \| hamaskWrSel.asUInt) & ~(hartIsInResetSync.asUInt) } } when (resumereq) { // next cycle resumeAcls will be the negation of next cycle resumeReqRegs resumeAcks := (~resumeReqRegs & ~(hamaskWrSel.asUInt)) }.otherwise { resumeAcks := ~resumeReqRegs } //---- AUTHDATA val authRdEnMaybe = WireInit(false.B) val authWrEnMaybe = WireInit(false.B) io.auth.map { a => a.dmactive := io.dmactive a.dmAuthRead := authRdEnMaybe & ~a.dmAuthBusy a.dmAuthWrite := authWrEnMaybe & ~a.dmAuthBusy } val dmstatusRegFields = RegFieldGroup("dmi_dmstatus", Some("debug module status register"), Seq( RegField.r(4, DMSTATUSRdData.version, RegFieldDesc("version", "version", reset=Some(2))), RegField.r(1, DMSTATUSRdData.confstrptrvalid, RegFieldDesc("confstrptrvalid", "confstrptrvalid", reset=Some(0))), RegField.r(1, DMSTATUSRdData.hasresethaltreq, RegFieldDesc("hasresethaltreq", "hasresethaltreq", reset=Some(1))), RegField.r(1, DMSTATUSRdData.authbusy, RegFieldDesc("authbusy", "authbusy", reset=Some(0))), RegField.r(1, DMSTATUSRdData.authenticated, RegFieldDesc("authenticated", "authenticated", reset=Some(1))), RegField.r(1, DMSTATUSRdData.anyhalted, RegFieldDesc("anyhalted", "anyhalted", reset=Some(0))), RegField.r(1, DMSTATUSRdData.allhalted, RegFieldDesc("allhalted", "allhalted", reset=Some(0))), RegField.r(1, DMSTATUSRdData.anyrunning, RegFieldDesc("anyrunning", "anyrunning", reset=Some(1))), RegField.r(1, DMSTATUSRdData.allrunning, RegFieldDesc("allrunning", "allrunning", reset=Some(1))), RegField.r(1, DMSTATUSRdData.anyunavail, RegFieldDesc("anyunavail", "anyunavail", reset=Some(0))), RegField.r(1, DMSTATUSRdData.allunavail, RegFieldDesc("allunavail", "allunavail", reset=Some(0))), RegField.r(1, DMSTATUSRdData.anynonexistent, RegFieldDesc("anynonexistent", "anynonexistent", reset=Some(0))), RegField.r(1, DMSTATUSRdData.allnonexistent, RegFieldDesc("allnonexistent", "allnonexistent", reset=Some(0))), RegField.r(1, DMSTATUSRdData.anyresumeack, RegFieldDesc("anyresumeack", "anyresumeack", reset=Some(1))), RegField.r(1, DMSTATUSRdData.allresumeack, RegFieldDesc("allresumeack", "allresumeack", reset=Some(1))), RegField.r(1, DMSTATUSRdData.anyhavereset, RegFieldDesc("anyhavereset", "anyhavereset", reset=Some(0))), RegField.r(1, DMSTATUSRdData.allhavereset, RegFieldDesc("allhavereset", "allhavereset", reset=Some(0))), RegField(2), RegField.r(1, DMSTATUSRdData.impebreak, RegFieldDesc("impebreak", "impebreak", reset=Some(if (cfg.hasImplicitEbreak) 1 else 0))) )) val dmcs2RegFields = RegFieldGroup("dmi_dmcs2", Some("debug module control/status register 2"), Seq( WNotifyVal(1, DMCS2RdData.hgselect, DMCS2WrData.hgselect, hgselectWrEn, RegFieldDesc("hgselect", "select halt groups or external triggers", reset=Some(0), volatile=true)), WNotifyVal(1, 0.U, DMCS2WrData.hgwrite, hgwriteWrEn, RegFieldDesc("hgwrite", "write 1 to change halt groups", reset=None, access=RegFieldAccessType.W)), WNotifyVal(5, DMCS2RdData.haltgroup, DMCS2WrData.haltgroup, haltgroupWrEn, RegFieldDesc("haltgroup", "halt group", reset=Some(0), volatile=true)), if (nExtTriggers > 1) WNotifyVal(4, DMCS2RdData.exttrigger, DMCS2WrData.exttrigger, exttriggerWrEn, RegFieldDesc("exttrigger", "external trigger select", reset=Some(0), volatile=true)) else RegField(4) )) val abstractcsRegFields = RegFieldGroup("dmi_abstractcs", Some("abstract command control/status"), Seq( RegField.r(4, ABSTRACTCSRdData.datacount, RegFieldDesc("datacount", "number of DATA registers", reset=Some(cfg.nAbstractDataWords))), RegField(4), WNotifyVal(3, ABSTRACTCSRdData.cmderr, ABSTRACTCSWrData.cmderr, ABSTRACTCSWrEnMaybe, RegFieldDesc("cmderr", "command error", reset=Some(0), wrType=Some(RegFieldWrType.ONE_TO_CLEAR))), RegField(1), RegField.r(1, ABSTRACTCSRdData.busy, RegFieldDesc("busy", "busy", reset=Some(0))), RegField(11), RegField.r(5, ABSTRACTCSRdData.progbufsize, RegFieldDesc("progbufsize", "number of PROGBUF registers", reset=Some(cfg.nProgramBufferWords))) )) val (sbcsFields, sbAddrFields, sbDataFields): (Seq[RegField], Seq[Seq[RegField]], Seq[Seq[RegField]]) = sb2tlOpt.map{ sb2tl => SystemBusAccessModule(sb2tl, io.dmactive, dmAuthenticated)(p) }.getOrElse((Seq.empty[RegField], Seq.fill[Seq[RegField]](4)(Seq.empty[RegField]), Seq.fill[Seq[RegField]](4)(Seq.empty[RegField]))) //-------------------------------------------------------------- // Program Buffer Access (DMI ... System Bus can override) //-------------------------------------------------------------- val omRegMap = dmiNode.regmap( (DMI_DMSTATUS << 2) -> dmstatusRegFields, //TODO (DMI_CFGSTRADDR0 << 2) -> cfgStrAddrFields, (DMI_DMCS2 << 2) -> (if (nHaltGroups > 0) dmcs2RegFields else Nil), (DMI_HALTSUM0 << 2) -> RegFieldGroup("dmi_haltsum0", Some("Halt Summary 0"), Seq(RegField.r(32, HALTSUM0RdData.asUInt, RegFieldDesc("dmi_haltsum0", "halt summary 0")))), (DMI_HALTSUM1 << 2) -> RegFieldGroup("dmi_haltsum1", Some("Halt Summary 1"), Seq(RegField.r(32, HALTSUM1RdData.asUInt, RegFieldDesc("dmi_haltsum1", "halt summary 1")))), (DMI_ABSTRACTCS << 2) -> abstractcsRegFields, (DMI_ABSTRACTAUTO<< 2) -> RegFieldGroup("dmi_abstractauto", Some("abstract command autoexec"), Seq( WNotifyVal(cfg.nAbstractDataWords, ABSTRACTAUTORdData.autoexecdata, ABSTRACTAUTOWrData.autoexecdata, autoexecdataWrEnMaybe, RegFieldDesc("autoexecdata", "abstract command data autoexec", reset=Some(0))), RegField(16-cfg.nAbstractDataWords), WNotifyVal(cfg.nProgramBufferWords, ABSTRACTAUTORdData.autoexecprogbuf, ABSTRACTAUTOWrData.autoexecprogbuf, autoexecprogbufWrEnMaybe, RegFieldDesc("autoexecprogbuf", "abstract command progbuf autoexec", reset=Some(0))))), (DMI_COMMAND << 2) -> RegFieldGroup("dmi_command", Some("Abstract Command Register"), Seq(RWNotify(32, COMMANDRdData.asUInt, COMMANDWrDataVal, COMMANDRdEn, COMMANDWrEnMaybe, Some(RegFieldDesc("dmi_command", "abstract command register", reset=Some(0), volatile=true))))), (DMI_DATA0 << 2) -> RegFieldGroup("dmi_data", Some("abstract command data registers"), abstractDataMem.zipWithIndex.map{case (x, i) => RWNotify(8, Mux(dmAuthenticated, x, 0.U), abstractDataNxt(i), dmiAbstractDataRdEn(i), dmiAbstractDataWrEnMaybe(i), Some(RegFieldDesc(s"dmi_data_$i", s"abstract command data register $i", reset = Some(0), volatile=true)))}, false), (DMI_PROGBUF0 << 2) -> RegFieldGroup("dmi_progbuf", Some("abstract command progbuf registers"), programBufferMem.zipWithIndex.map{case (x, i) => RWNotify(8, Mux(dmAuthenticated, x, 0.U), programBufferNxt(i), dmiProgramBufferRdEn(i), dmiProgramBufferWrEnMaybe(i), Some(RegFieldDesc(s"dmi_progbuf_$i", s"abstract command progbuf register $i", reset = Some(0))))}, false), (DMI_AUTHDATA << 2) -> (if (cfg.hasAuthentication) RegFieldGroup("dmi_authdata", Some("authentication data exchange register"), Seq(RWNotify(32, io.auth.get.dmAuthRdata, io.auth.get.dmAuthWdata, authRdEnMaybe, authWrEnMaybe, Some(RegFieldDesc("authdata", "authentication data exchange", volatile=true))))) else Nil), (DMI_SBCS << 2) -> sbcsFields, (DMI_SBDATA0 << 2) -> sbDataFields(0), (DMI_SBDATA1 << 2) -> sbDataFields(1), (DMI_SBDATA2 << 2) -> sbDataFields(2), (DMI_SBDATA3 << 2) -> sbDataFields(3), (DMI_SBADDRESS0 << 2) -> sbAddrFields(0), (DMI_SBADDRESS1 << 2) -> sbAddrFields(1), (DMI_SBADDRESS2 << 2) -> sbAddrFields(2), (DMI_SBADDRESS3 << 2) -> sbAddrFields(3) ) // Abstract data mem is written by both the tile link interface and DMI... abstractDataMem.zipWithIndex.foreach { case (x, i) => when (dmAuthenticated && dmiAbstractDataWrEnMaybe(i) && dmiAbstractDataAccessLegal) { x := abstractDataNxt(i) } } // ... and also by custom register read (if implemented) val (customs, customParams) = customNode.in.unzip val needCustom = (customs.size > 0) && (customParams.head.addrs.size > 0) def getNeedCustom = () => needCustom if (needCustom) { val (custom, customP) = customNode.in.head require(customP.width % 8 == 0, s"Debug Custom width must be divisible by 8, not ${customP.width}") val custom_data = custom.data.asBools val custom_bytes = Seq.tabulate(customP.width/8){i => custom_data.slice(i8, (i+1)8).asUInt} when (custom.ready && custom.valid) { (abstractDataMem zip custom_bytes).zipWithIndex.foreach {case ((a, b), i) => a := b } } } programBufferMem.zipWithIndex.foreach { case (x, i) => when (dmAuthenticated && dmiProgramBufferWrEnMaybe(i) && dmiProgramBufferAccessLegal) { x := programBufferNxt(i) } } //-------------------------------------------------------------- // "Variable" ROM Generation //-------------------------------------------------------------- val goReg = Reg(Bool()) val goAbstract = WireInit(false.B) val goCustom = WireInit(false.B) val jalAbstract = WireInit(Instructions.JAL.value.U.asTypeOf(new GeneratedUJ())) jalAbstract.setImm(ABSTRACT(cfg) - WHERETO) when (~io.dmactive){ goReg := false.B }.otherwise { when (goAbstract) { goReg := true.B }.elsewhen (hartGoingWrEn){ assert(hartGoingId === 0.U, "Unexpected 'GOING' hart.")//Chisel3 #540 %x, expected %x", hartGoingId, 0.U) goReg := false.B } } class flagBundle extends Bundle { val reserved = UInt(6.W) val resume = Bool() val go = Bool() } val flags = WireInit(VecInit(Seq.fill(1 << selectedHartReg.getWidth) {0.U.asTypeOf(new flagBundle())} )) assert ((hartSelFuncs.hartSelToHartId(selectedHartReg) < flags.size.U), s"HartSel to HartId Mapping is illegal for this Debug Implementation, because HartID must be < ${flags.size} for it to work.") flags(hartSelFuncs.hartSelToHartId(selectedHartReg)).go := goReg for (component <- 0 until nComponents) { val componentSel = WireInit(component.U) flags(hartSelFuncs.hartSelToHartId(componentSel)).resume := resumeReqRegs(component) } //---------------------------- // Abstract Command Decoding & Generation //---------------------------- val accessRegisterCommandWr = WireInit(COMMANDWrData.asUInt.asTypeOf(new ACCESS_REGISTERFields())) /** real COMMAND/ val accessRegisterCommandReg = WireInit(COMMANDReg.asUInt.asTypeOf(new ACCESS_REGISTERFields())) // TODO: Quick Access class GeneratedI extends Bundle { val imm = UInt(12.W) val rs1 = UInt(5.W) val funct3 = UInt(3.W) val rd = UInt(5.W) val opcode = UInt(7.W) } class GeneratedS extends Bundle { val immhi = UInt(7.W) val rs2 = UInt(5.W) val rs1 = UInt(5.W) val funct3 = UInt(3.W) val immlo = UInt(5.W) val opcode = UInt(7.W) } class GeneratedCSR extends Bundle { val imm = UInt(12.W) val rs1 = UInt(5.W) val funct3 = UInt(3.W) val rd = UInt(5.W) val opcode = UInt(7.W) } class GeneratedUJ extends Bundle { val imm3 = UInt(1.W) val imm0 = UInt(10.W) val imm1 = UInt(1.W) val imm2 = UInt(8.W) val rd = UInt(5.W) val opcode = UInt(7.W) def setImm(imm: Int) : Unit = { // TODO: Check bounds of imm. require(imm % 2 == 0, "Immediate must be even for UJ encoding.") val immWire = WireInit(imm.S(21.W)) val immBits = WireInit(VecInit(immWire.asBools)) imm0 := immBits.slice(1, 1 + 10).asUInt imm1 := immBits.slice(11, 11 + 11).asUInt imm2 := immBits.slice(12, 12 + 8).asUInt imm3 := immBits.slice(20, 20 + 1).asUInt } } require((cfg.atzero && cfg.nAbstractInstructions == 2) \|\| (!cfg.atzero && cfg.nAbstractInstructions == 5), "Mismatch between DebugModuleParams atzero and nAbstractInstructions") val abstractGeneratedMem = Reg(Vec(cfg.nAbstractInstructions, (UInt(32.W)))) def abstractGeneratedI(cfg: DebugModuleParams): UInt = { val inst = Wire(new GeneratedI()) val offset = if (cfg.atzero) DATA else (DATA-0x800) & 0xFFF val base = if (cfg.atzero) 0.U else Mux(accessRegisterCommandReg.regno(0), 8.U, 9.U) inst.opcode := (Instructions.LW.value.U.asTypeOf(new GeneratedI())).opcode inst.rd := (accessRegisterCommandReg.regno & 0x1F.U) inst.funct3 := accessRegisterCommandReg.size inst.rs1 := base inst.imm := offset.U inst.asUInt } def abstractGeneratedS(cfg: DebugModuleParams): UInt = { val inst = Wire(new GeneratedS()) val offset = if (cfg.atzero) DATA else (DATA-0x800) & 0xFFF val base = if (cfg.atzero) 0.U else Mux(accessRegisterCommandReg.regno(0), 8.U, 9.U) inst.opcode := (Instructions.SW.value.U.asTypeOf(new GeneratedS())).opcode inst.immlo := (offset & 0x1F).U inst.funct3 := accessRegisterCommandReg.size inst.rs1 := base inst.rs2 := (accessRegisterCommandReg.regno & 0x1F.U) inst.immhi := (offset >> 5).U inst.asUInt } def abstractGeneratedCSR: UInt = { val inst = Wire(new GeneratedCSR()) val base = Mux(accessRegisterCommandReg.regno(0), 8.U, 9.U) // use s0 as base for odd regs, s1 as base for even regs inst := (Instructions.CSRRW.value.U.asTypeOf(new GeneratedCSR())) inst.imm := CSRs.dscratch1.U inst.rs1 := base inst.rd := base inst.asUInt } val nop = Wire(new GeneratedI()) nop := Instructions.ADDI.value.U.asTypeOf(new GeneratedI()) nop.rd := 0.U nop.rs1 := 0.U nop.imm := 0.U val isa = Wire(new GeneratedI()) isa := Instructions.ADDIW.value.U.asTypeOf(new GeneratedI()) isa.rd := 0.U isa.rs1 := 0.U isa.imm := 0.U when (goAbstract) { if (cfg.nAbstractInstructions == 2) { // ABSTRACT(0): Transfer: LW or SW, else NOP // ABSTRACT(1): Postexec: NOP else EBREAK abstractGeneratedMem(0) := Mux(accessRegisterCommandReg.transfer, Mux(accessRegisterCommandReg.write, abstractGeneratedI(cfg), abstractGeneratedS(cfg)), nop.asUInt ) abstractGeneratedMem(1) := Mux(accessRegisterCommandReg.postexec, nop.asUInt, Instructions.EBREAK.value.U) } else { // Entry: All regs in GPRs, dscratch1=offset 0x800 in DM // ABSTRACT(0): CheckISA: ADDW or NOP (exception here if size=3 and not RV64) // ABSTRACT(1): CSRRW s1,dscratch1,s1 or CSRRW s0,dscratch1,s0 // ABSTRACT(2): Transfer: LW, SW, LD, SD else NOP // ABSTRACT(3): CSRRW s1,dscratch1,s1 or CSRRW s0,dscratch1,s0 // ABSTRACT(4): Postexec: NOP else EBREAK abstractGeneratedMem(0) := Mux(accessRegisterCommandReg.transfer && accessRegisterCommandReg.size =/= 2.U, isa.asUInt, nop.asUInt) abstractGeneratedMem(1) := abstractGeneratedCSR abstractGeneratedMem(2) := Mux(accessRegisterCommandReg.transfer, Mux(accessRegisterCommandReg.write, abstractGeneratedI(cfg), abstractGeneratedS(cfg)), nop.asUInt ) abstractGeneratedMem(3) := abstractGeneratedCSR abstractGeneratedMem(4) := Mux(accessRegisterCommandReg.postexec, nop.asUInt, Instructions.EBREAK.value.U) } } //-------------------------------------------------------------- // Drive Custom Access //-------------------------------------------------------------- if (needCustom) { val (custom, customP) = customNode.in.head custom.addr := accessRegisterCommandReg.regno custom.valid := goCustom } //-------------------------------------------------------------- // Hart Bus Access //-------------------------------------------------------------- tlNode.regmap( // This memory is writable. HALTED -> Seq(WNotifyWire(sbIdWidth, hartHaltedId, hartHaltedWrEn, "debug_hart_halted", "Debug ROM Causes hart to write its hartID here when it is in Debug Mode.")), GOING -> Seq(WNotifyWire(sbIdWidth, hartGoingId, hartGoingWrEn, "debug_hart_going", "Debug ROM causes hart to write 0 here when it begins executing Debug Mode instructions.")), RESUMING -> Seq(WNotifyWire(sbIdWidth, hartResumingId, hartResumingWrEn, "debug_hart_resuming", "Debug ROM causes hart to write its hartID here when it leaves Debug Mode.")), EXCEPTION -> Seq(WNotifyWire(sbIdWidth, hartExceptionId, hartExceptionWrEn, "debug_hart_exception", "Debug ROM causes hart to write 0 here if it gets an exception in Debug Mode.")), DATA -> RegFieldGroup("debug_data", Some("Data used to communicate with Debug Module"), abstractDataMem.zipWithIndex.map {case (x, i) => RegField(8, x, RegFieldDesc(s"debug_data_$i", ""))}), PROGBUF(cfg)-> RegFieldGroup("debug_progbuf", Some("Program buffer used to communicate with Debug Module"), programBufferMem.zipWithIndex.map {case (x, i) => RegField(8, x, RegFieldDesc(s"debug_progbuf_$i", ""))}), // These sections are read-only. IMPEBREAK(cfg)-> {if (cfg.hasImplicitEbreak) Seq(RegField.r(32, Instructions.EBREAK.value.U, RegFieldDesc("debug_impebreak", "Debug Implicit EBREAK", reset=Some(Instructions.EBREAK.value)))) else Nil}, WHERETO -> Seq(RegField.r(32, jalAbstract.asUInt, RegFieldDesc("debug_whereto", "Instruction filled in by Debug Module to control hart in Debug Mode", volatile = true))), ABSTRACT(cfg) -> RegFieldGroup("debug_abstract", Some("Instructions generated by Debug Module"), abstractGeneratedMem.zipWithIndex.map{ case (x,i) => RegField.r(32, x, RegFieldDesc(s"debug_abstract_$i", "", volatile=true))}), FLAGS -> RegFieldGroup("debug_flags", Some("Memory region used to control hart going/resuming in Debug Mode"), if (nComponents == 1) { Seq.tabulate(1024) { i => RegField.r(8, flags(0).asUInt, RegFieldDesc(s"debug_flags_$i", "", volatile=true)) } } else { flags.zipWithIndex.map{case(x, i) => RegField.r(8, x.asUInt, RegFieldDesc(s"debug_flags_$i", "", volatile=true))} }), ROMBASE -> RegFieldGroup("debug_rom", Some("Debug ROM"), (if (cfg.atzero) DebugRomContents() else DebugRomNonzeroContents()).zipWithIndex.map{case (x, i) => RegField.r(8, (x & 0xFF).U(8.W), RegFieldDesc(s"debug_rom_$i", "", reset=Some(x)))}) ) // Override System Bus accesses with dmactive reset. when (~io.dmactive){ abstractDataMem.foreach {x => x := 0.U} programBufferMem.foreach {x => x := 0.U} } //-------------------------------------------------------------- // Abstract Command State Machine //-------------------------------------------------------------- object CtrlState extends scala.Enumeration { type CtrlState = Value val Waiting, CheckGenerate, Exec, Custom = Value def apply( t : Value) : UInt = { t.id.U(log2Up(values.size).W) } } import CtrlState._ // This is not an initialization! val ctrlStateReg = Reg(chiselTypeOf(CtrlState(Waiting))) val hartHalted = haltedBitRegs(if (nComponents == 1) 0.U(0.W) else selectedHartReg) val ctrlStateNxt = WireInit(ctrlStateReg) //------------------------ // DMI Register Control and Status abstractCommandBusy := (ctrlStateReg =/= CtrlState(Waiting)) ABSTRACTCSWrEnLegal := (ctrlStateReg === CtrlState(Waiting)) COMMANDWrEnLegal := (ctrlStateReg === CtrlState(Waiting)) ABSTRACTAUTOWrEnLegal := (ctrlStateReg === CtrlState(Waiting)) dmiAbstractDataAccessLegal := (ctrlStateReg === CtrlState(Waiting)) dmiProgramBufferAccessLegal := (ctrlStateReg === CtrlState(Waiting)) errorBusy := (ABSTRACTCSWrEnMaybe && ~ABSTRACTCSWrEnLegal) \|\| (autoexecdataWrEnMaybe && ~ABSTRACTAUTOWrEnLegal) \|\| (autoexecprogbufWrEnMaybe && ~ABSTRACTAUTOWrEnLegal) \|\| (COMMANDWrEnMaybe && ~COMMANDWrEnLegal) \|\| (dmiAbstractDataAccess && ~dmiAbstractDataAccessLegal) \|\| (dmiProgramBufferAccess && ~dmiProgramBufferAccessLegal) // TODO: Maybe Quick Access val commandWrIsAccessRegister = (COMMANDWrData.cmdtype === DebugAbstractCommandType.AccessRegister.id.U) val commandRegIsAccessRegister = (COMMANDReg.cmdtype === DebugAbstractCommandType.AccessRegister.id.U) val commandWrIsUnsupported = COMMANDWrEn && !commandWrIsAccessRegister val commandRegIsUnsupported = WireInit(true.B) val commandRegBadHaltResume = WireInit(false.B) // We only support abstract commands for GPRs and any custom registers, if specified. val accessRegIsLegalSize = (accessRegisterCommandReg.size === 2.U) \|\| (accessRegisterCommandReg.size === 3.U) val accessRegIsGPR = (accessRegisterCommandReg.regno >= 0x1000.U && accessRegisterCommandReg.regno <= 0x101F.U) && accessRegIsLegalSize val accessRegIsCustom = if (needCustom) { val (custom, customP) = customNode.in.head customP.addrs.foldLeft(false.B){ (result, current) => result \|\| (current.U === accessRegisterCommandReg.regno)} } else false.B when (commandRegIsAccessRegister) { when (accessRegIsCustom && accessRegisterCommandReg.transfer && accessRegisterCommandReg.write === false.B) { commandRegIsUnsupported := false.B }.elsewhen (!accessRegisterCommandReg.transfer \|\| accessRegIsGPR) { commandRegIsUnsupported := false.B commandRegBadHaltResume := ~hartHalted } } val wrAccessRegisterCommand = COMMANDWrEn && commandWrIsAccessRegister && (ABSTRACTCSReg.cmderr === 0.U) val regAccessRegisterCommand = autoexec && commandRegIsAccessRegister && (ABSTRACTCSReg.cmderr === 0.U) //------------------------ // Variable ROM STATE MACHINE // ----------------------- when (ctrlStateReg === CtrlState(Waiting)){ when (wrAccessRegisterCommand \|\| regAccessRegisterCommand) { ctrlStateNxt := CtrlState(CheckGenerate) }.elsewhen (commandWrIsUnsupported) { // These checks are really on the command type. errorUnsupported := true.B }.elsewhen (autoexec && commandRegIsUnsupported) { errorUnsupported := true.B } }.elsewhen (ctrlStateReg === CtrlState(CheckGenerate)){ // We use this state to ensure that the COMMAND has been // registered by the time that we need to use it, to avoid // generating it directly from the COMMANDWrData. // This 'commandRegIsUnsupported' is really just checking the // AccessRegisterCommand parameters (regno) when (commandRegIsUnsupported) { errorUnsupported := true.B ctrlStateNxt := CtrlState(Waiting) }.elsewhen (commandRegBadHaltResume){ errorHaltResume := true.B ctrlStateNxt := CtrlState(Waiting) }.otherwise { when(accessRegIsCustom) { ctrlStateNxt := CtrlState(Custom) }.otherwise { ctrlStateNxt := CtrlState(Exec) goAbstract := true.B } } }.elsewhen (ctrlStateReg === CtrlState(Exec)) { // We can't just look at 'hartHalted' here, because // hartHaltedWrEn is overloaded to mean 'got an ebreak' // which may have happened when we were already halted. when(goReg === false.B && hartHaltedWrEn && (hartSelFuncs.hartIdToHartSel(hartHaltedId) === selectedHartReg)){ ctrlStateNxt := CtrlState(Waiting) } when(hartExceptionWrEn) { assert(hartExceptionId === 0.U, "Unexpected 'EXCEPTION' hart")//Chisel3 #540, %x, expected %x", hartExceptionId, 0.U) ctrlStateNxt := CtrlState(Waiting) errorException := true.B } }.elsewhen (ctrlStateReg === CtrlState(Custom)) { assert(needCustom.B, "Should not be in custom state unless we need it.") goCustom := true.B val (custom, customP) = customNode.in.head when (custom.ready && custom.valid) { ctrlStateNxt := CtrlState(Waiting) } } when (~io.dmactive \|\| ~dmAuthenticated) { ctrlStateReg := CtrlState(Waiting) }.otherwise { ctrlStateReg := ctrlStateNxt } assert ((!io.dmactive \|\| !hartExceptionWrEn \|\| ctrlStateReg === CtrlState(Exec)), "Unexpected EXCEPTION write: should only get it in Debug Module EXEC state") } } // Wrapper around TL Debug Module Inner and an Async DMI Sink interface. // Handles the synchronization of dmactive, which is used as a synchronous reset // inside the Inner block. // Also is the Sink side of hartsel & resumereq fields of DMCONTROL. class TLDebugModuleInnerAsync(device: Device, getNComponents: () => Int, beatBytes: Int)(implicit p: Parameters) extends LazyModule{ val cfg = p(DebugModuleKey).get val dmInner = LazyModule(new TLDebugModuleInner(device, getNComponents, beatBytes)) val dmiXing = LazyModule(new TLAsyncCrossingSink(AsyncQueueParams.singleton(safe=cfg.crossingHasSafeReset))) val dmiNode = dmiXing.node val tlNode = dmInner.tlNode dmInner.dmiNode := dmiXing.node // Require that there are no registers in TL interface, so that spurious // processor accesses to the DM don't need to enable the clock. We don't // require this property of the SBA, because the debugger is responsible for // raising dmactive (hence enabling the clock) during these transactions. require(dmInner.tlNode.concurrency == 0) lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { // Clock/reset domains: // debug_clock / debug_reset = Debug inner domain // tl_clock / tl_reset = tilelink domain (External: clock / reset) // val io = IO(new Bundle { val debug_clock = Input(Clock()) val debug_reset = Input(Reset()) val tl_clock = Input(Clock()) val tl_reset = Input(Reset()) // These are all asynchronous and come from Outer /* reset signal for DM / val dmactive = Input(Bool()) /* conrol signals for Inner * * generated in Outer / val innerCtrl = Flipped(new AsyncBundle(new DebugInternalBundle(getNComponents()), AsyncQueueParams.singleton(safe=cfg.crossingHasSafeReset))) // This comes from tlClk domain. /* debug available status / val debugUnavail = Input(Vec(getNComponents(), Bool())) /* debug interruption/ val hgDebugInt = Output(Vec(getNComponents(), Bool())) val extTrigger = (p(DebugModuleKey).get.nExtTriggers > 0).option(new DebugExtTriggerIO()) /* vector to indicate which hart is in reset * * dm receives it from core and sends it to Inner / val hartIsInReset = Input(Vec(getNComponents(), Bool())) /* Debug Authentication signals from core / val auth = p(DebugModuleKey).get.hasAuthentication.option(new DebugAuthenticationIO()) }) val rf_reset = IO(Input(Reset())) // RF transform childClock := io.debug_clock childReset := io.debug_reset override def provideImplicitClockToLazyChildren = true val dmactive_synced = withClockAndReset(childClock, childReset) { val dmactive_synced = AsyncResetSynchronizerShiftReg(in=io.dmactive, sync=3, name=Some("dmactiveSync")) dmInner.module.clock := io.debug_clock dmInner.module.reset := io.debug_reset dmInner.module.io.tl_clock := io.tl_clock dmInner.module.io.tl_reset := io.tl_reset dmInner.module.io.dmactive := dmactive_synced dmInner.module.io.innerCtrl <> FromAsyncBundle(io.innerCtrl) dmInner.module.io.debugUnavail := io.debugUnavail io.hgDebugInt := dmInner.module.io.hgDebugInt io.extTrigger.foreach { x => dmInner.module.io.extTrigger.foreach {y => x <> y}} dmInner.module.io.hartIsInReset := io.hartIsInReset io.auth.foreach { x => dmInner.module.io.auth.foreach {y => x <> y}} dmactive_synced } } } /* Create a version of the TLDebugModule which includes a synchronization interface * internally for the DMI. This is no longer optional outside of this module * because the Clock must run when tl_clock isn't running or tl_reset is asserted. / class TLDebugModule(beatBytes: Int)(implicit p: Parameters) extends LazyModule { val device = new SimpleDevice("debug-controller", Seq("sifive,debug-013","riscv,debug-013")){ override val alwaysExtended = true override def describe(resources: ResourceBindings): Description = { val Description(name, mapping) = super.describe(resources) val attach = Map( "debug-attach" -> ( (if (p(ExportDebug).apb) Seq(ResourceString("apb")) else Seq()) ++ (if (p(ExportDebug).jtag) Seq(ResourceString("jtag")) else Seq()) ++ (if (p(ExportDebug).cjtag) Seq(ResourceString("cjtag")) else Seq()) ++ (if (p(ExportDebug).dmi) Seq(ResourceString("dmi")) else Seq()))) Description(name, mapping ++ attach) } } val dmOuter : TLDebugModuleOuterAsync = LazyModule(new TLDebugModuleOuterAsync(device)(p)) val dmInner : TLDebugModuleInnerAsync = LazyModule(new TLDebugModuleInnerAsync(device, () => {dmOuter.dmOuter.intnode.edges.out.size}, beatBytes)(p)) val node = dmInner.tlNode val intnode = dmOuter.intnode val apbNodeOpt = dmOuter.apbNodeOpt dmInner.dmiNode := dmOuter.dmiInnerNode lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { val nComponents = dmOuter.dmOuter.intnode.edges.out.size // Clock/reset domains: // tl_clock / tl_reset = tilelink domain // debug_clock / debug_reset = Inner debug (synchronous to tl_clock) // apb_clock / apb_reset = Outer debug with APB // dmiClock / dmiReset = Outer debug without APB // val io = IO(new Bundle { val debug_clock = Input(Clock()) val debug_reset = Input(Reset()) val tl_clock = Input(Clock()) val tl_reset = Input(Reset()) /* Debug control signals generated in Outer / val ctrl = new DebugCtrlBundle(nComponents) /* Debug Module Interface bewteen DM and DTM * * The DTM provides access to one or more Debug Modules (DMs) using DMI / val dmi = (!p(ExportDebug).apb).option(Flipped(new ClockedDMIIO())) val apb_clock = p(ExportDebug).apb.option(Input(Clock())) val apb_reset = p(ExportDebug).apb.option(Input(Reset())) val extTrigger = (p(DebugModuleKey).get.nExtTriggers > 0).option(new DebugExtTriggerIO()) /* vector to indicate which hart is in reset * * dm receives it from core and sends it to Inner / val hartIsInReset = Input(Vec(nComponents, Bool())) /* hart reset request generated by hartreset-logic in Outer / val hartResetReq = p(DebugModuleKey).get.hasHartResets.option(Output(Vec(nComponents, Bool()))) /* Debug Authentication signals from core / val auth = p(DebugModuleKey).get.hasAuthentication.option(new DebugAuthenticationIO()) }) childClock := io.tl_clock childReset := io.tl_reset override def provideImplicitClockToLazyChildren = true dmOuter.module.io.dmi.foreach { dmOuterDMI => dmOuterDMI <> io.dmi.get.dmi dmOuter.module.io.dmi_reset := io.dmi.get.dmiReset dmOuter.module.io.dmi_clock := io.dmi.get.dmiClock dmOuter.module.rf_reset := io.dmi.get.dmiReset } (io.apb_clock zip io.apb_reset) foreach { case (c, r) => dmOuter.module.io.dmi_reset := r dmOuter.module.io.dmi_clock := c dmOuter.module.rf_reset := r } dmInner.module.rf_reset := io.debug_reset dmInner.module.io.debug_clock := io.debug_clock dmInner.module.io.debug_reset := io.debug_reset dmInner.module.io.tl_clock := io.tl_clock dmInner.module.io.tl_reset := io.tl_reset dmInner.module.io.innerCtrl <> dmOuter.module.io.innerCtrl dmInner.module.io.dmactive := dmOuter.module.io.ctrl.dmactive dmInner.module.io.debugUnavail := io.ctrl.debugUnavail dmOuter.module.io.hgDebugInt := dmInner.module.io.hgDebugInt io.ctrl <> dmOuter.module.io.ctrl io.extTrigger.foreach { x => dmInner.module.io.extTrigger.foreach {y => x <> y}} dmInner.module.io.hartIsInReset := io.hartIsInReset io.hartResetReq.foreach { x => dmOuter.module.io.hartResetReq.foreach {y => x := y}} io.auth.foreach { x => dmOuter.module.io.dmAuthenticated.get := x.dmAuthenticated } io.auth.foreach { x => dmInner.module.io.auth.foreach {y => x <> y}} } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph / def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File SBA.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.devices.debug.systembusaccess import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.amba.{AMBAProt, AMBAProtField} import freechips.rocketchip.devices.debug.{DebugModuleKey, RWNotify, SBCSFields, WNotifyVal} import freechips.rocketchip.diplomacy.TransferSizes import freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldGroup, RegFieldWrType} import freechips.rocketchip.tilelink.{TLClientNode, TLMasterParameters, TLMasterPortParameters} import freechips.rocketchip.util.property object SystemBusAccessState extends scala.Enumeration { type SystemBusAccessState = Value val Idle, SBReadRequest, SBWriteRequest, SBReadResponse, SBWriteResponse = Value } object SBErrorCode extends scala.Enumeration { type SBErrorCode = Value val NoError = Value(0) val Timeout = Value(1) val BadAddr = Value(2) val AlgnError = Value(3) val BadAccess = Value(4) val OtherError = Value(7) } object SystemBusAccessModule { def apply(sb2tl: SBToTL, dmactive: Bool, dmAuthenticated: Bool)(implicit p: Parameters): (Seq[RegField], Seq[Seq[RegField]], Seq[Seq[RegField]]) = { import SBErrorCode._ val cfg = p(DebugModuleKey).get val anyAddressWrEn = WireInit(false.B).suggestName("anyAddressWrEn") val anyDataRdEn = WireInit(false.B).suggestName("anyDataRdEn") val anyDataWrEn = WireInit(false.B).suggestName("anyDataWrEn") // --- SBCS Status Register --- val SBCSFieldsReg = Reg(new SBCSFields()).suggestName("SBCSFieldsReg") val SBCSFieldsRegReset = WireInit(0.U.asTypeOf(new SBCSFields())) SBCSFieldsRegReset.sbversion := 1.U(1.W) // This code implements a version of the spec after January 1, 2018 SBCSFieldsRegReset.sbbusy := (sb2tl.module.io.sbStateOut =/= SystemBusAccessState.Idle.id.U) SBCSFieldsRegReset.sbaccess := 2.U SBCSFieldsRegReset.sbasize := sb2tl.module.edge.bundle.addressBits.U SBCSFieldsRegReset.sbaccess128 := (cfg.maxSupportedSBAccess == 128).B SBCSFieldsRegReset.sbaccess64 := (cfg.maxSupportedSBAccess >= 64).B SBCSFieldsRegReset.sbaccess32 := (cfg.maxSupportedSBAccess >= 32).B SBCSFieldsRegReset.sbaccess16 := (cfg.maxSupportedSBAccess >= 16).B SBCSFieldsRegReset.sbaccess8 := (cfg.maxSupportedSBAccess >= 8).B val SBCSRdData = WireInit(0.U.asTypeOf(new SBCSFields())).suggestName("SBCSRdData") val SBCSWrDataVal = WireInit(0.U(32.W)) val SBCSWrData = WireInit(SBCSWrDataVal.asTypeOf(new SBCSFields())) val sberrorWrEn = WireInit(false.B) val sbreadondataWrEn = WireInit(false.B) val sbautoincrementWrEn= WireInit(false.B) val sbaccessWrEn = WireInit(false.B) val sbreadonaddrWrEn = WireInit(false.B) val sbbusyerrorWrEn = WireInit(false.B) val sbcsfields = RegFieldGroup("sbcs", Some("system bus access control and status"), Seq( RegField.r(1, SBCSRdData.sbaccess8, RegFieldDesc("sbaccess8", "8-bit accesses supported", reset=Some(if (cfg.maxSupportedSBAccess >= 8) 1 else 0))), RegField.r(1, SBCSRdData.sbaccess16, RegFieldDesc("sbaccess16", "16-bit accesses supported", reset=Some(if (cfg.maxSupportedSBAccess >= 16) 1 else 0))), RegField.r(1, SBCSRdData.sbaccess32, RegFieldDesc("sbaccess32", "32-bit accesses supported", reset=Some(if (cfg.maxSupportedSBAccess >= 32) 1 else 0))), RegField.r(1, SBCSRdData.sbaccess64, RegFieldDesc("sbaccess64", "64-bit accesses supported", reset=Some(if (cfg.maxSupportedSBAccess >= 64) 1 else 0))), RegField.r(1, SBCSRdData.sbaccess128, RegFieldDesc("sbaccess128", "128-bit accesses supported", reset=Some(if (cfg.maxSupportedSBAccess == 128) 1 else 0))), RegField.r(7, SBCSRdData.sbasize, RegFieldDesc("sbasize", "bits in address", reset=Some(sb2tl.module.edge.bundle.addressBits))), WNotifyVal(3, SBCSRdData.sberror, SBCSWrData.sberror, sberrorWrEn, RegFieldDesc("sberror", "system bus error", reset=Some(0), wrType=Some(RegFieldWrType.ONE_TO_CLEAR))), WNotifyVal(1, SBCSRdData.sbreadondata, SBCSWrData.sbreadondata, sbreadondataWrEn, RegFieldDesc("sbreadondata", "system bus read on data", reset=Some(0))), WNotifyVal(1, SBCSRdData.sbautoincrement, SBCSWrData.sbautoincrement, sbautoincrementWrEn, RegFieldDesc("sbautoincrement", "system bus auto-increment address", reset=Some(0))), WNotifyVal(3, SBCSRdData.sbaccess, SBCSWrData.sbaccess, sbaccessWrEn, RegFieldDesc("sbaccess", "system bus access size", reset=Some(2))), WNotifyVal(1, SBCSRdData.sbreadonaddr, SBCSWrData.sbreadonaddr, sbreadonaddrWrEn, RegFieldDesc("sbreadonaddr", "system bus read on data", reset=Some(0))), RegField.r(1, SBCSRdData.sbbusy, RegFieldDesc("sbbusy", "system bus access is busy", reset=Some(0))), WNotifyVal(1, SBCSRdData.sbbusyerror, SBCSWrData.sbbusyerror, sbbusyerrorWrEn, RegFieldDesc("sbbusyerror", "system bus busy error", reset=Some(0), wrType=Some(RegFieldWrType.ONE_TO_CLEAR))), RegField(6), RegField.r(3, SBCSRdData.sbversion, RegFieldDesc("sbversion", "system bus access version", reset=Some(1))), )) // --- System Bus Address Registers --- // ADDR0 Register is required // Instantiate ADDR1-3 registers as needed depending on system bus address width val hasSBAddr1 = (sb2tl.module.edge.bundle.addressBits >= 33) val hasSBAddr2 = (sb2tl.module.edge.bundle.addressBits >= 65) val hasSBAddr3 = (sb2tl.module.edge.bundle.addressBits >= 97) val hasAddr = Seq(true, hasSBAddr1, hasSBAddr2, hasSBAddr3) val SBADDRESSFieldsReg = Reg(Vec(4, UInt(32.W))) SBADDRESSFieldsReg.zipWithIndex.foreach { case(a,i) => a.suggestName("SBADDRESS"+i+"FieldsReg")} val SBADDRESSWrData = WireInit(VecInit(Seq.fill(4) {0.U(32.W)} )) val SBADDRESSRdEn = WireInit(VecInit(Seq.fill(4) {false.B} )) val SBADDRESSWrEn = WireInit(VecInit(Seq.fill(4) {false.B} )) val autoIncrementedAddr = WireInit(0.U(128.W)) autoIncrementedAddr := Cat(SBADDRESSFieldsReg.reverse) + (1.U << SBCSFieldsReg.sbaccess) autoIncrementedAddr.suggestName("autoIncrementedAddr") val sbaddrfields: Seq[Seq[RegField]] = SBADDRESSFieldsReg.zipWithIndex.map { case(a,i) => if(hasAddr(i)) { when (~dmactive \|\| ~dmAuthenticated) { a := 0.U(32.W) }.otherwise { a := Mux(SBADDRESSWrEn(i) && !SBCSRdData.sberror && !SBCSFieldsReg.sbbusy && !SBCSFieldsReg.sbbusyerror, SBADDRESSWrData(i), Mux((sb2tl.module.io.rdDone \|\| sb2tl.module.io.wrDone) && SBCSFieldsReg.sbautoincrement, autoIncrementedAddr(32i+31,32i), a)) } RegFieldGroup("dmi_sbaddr"+i, Some("SBA Address Register"), Seq(RWNotify(32, a, SBADDRESSWrData(i), SBADDRESSRdEn(i), SBADDRESSWrEn(i), Some(RegFieldDesc("dmi_sbaddr"+i, "SBA address register", reset=Some(0), volatile=true))))) } else { a := DontCare Seq.empty[RegField] } } sb2tl.module.io.addrIn := Mux(SBADDRESSWrEn(0), Cat(Cat(SBADDRESSFieldsReg.drop(1).reverse), SBADDRESSWrData(0)), Cat(SBADDRESSFieldsReg.reverse)) anyAddressWrEn := SBADDRESSWrEn.reduce(_ \|\| _) // --- System Bus Data Registers --- // DATA0 Register is required // DATA1-3 Registers may not be needed depending on implementation val hasSBData1 = (cfg.maxSupportedSBAccess > 32) val hasSBData2And3 = (cfg.maxSupportedSBAccess == 128) val hasData = Seq(true, hasSBData1, hasSBData2And3, hasSBData2And3) val SBDATAFieldsReg = Reg(Vec(4, Vec(4, UInt(8.W)))) SBDATAFieldsReg.zipWithIndex.foreach { case(d,i) => d.zipWithIndex.foreach { case(d,j) => d.suggestName("SBDATA"+i+"BYTE"+j) }} val SBDATARdData = WireInit(VecInit(Seq.fill(4) {0.U(32.W)} )) SBDATARdData.zipWithIndex.foreach { case(d,i) => d.suggestName("SBDATARdData"+i) } val SBDATAWrData = WireInit(VecInit(Seq.fill(4) {0.U(32.W)} )) SBDATAWrData.zipWithIndex.foreach { case(d,i) => d.suggestName("SBDATAWrData"+i) } val SBDATARdEn = WireInit(VecInit(Seq.fill(4) {false.B} )) val SBDATAWrEn = WireInit(VecInit(Seq.fill(4) {false.B} )) SBDATAWrEn.zipWithIndex.foreach { case(d,i) => d.suggestName("SBDATAWrEn"+i) } val sbdatafields: Seq[Seq[RegField]] = SBDATAFieldsReg.zipWithIndex.map { case(d,i) => if(hasData(i)) { // For data registers, load enable per-byte for (j <- 0 to 3) { when (~dmactive \|\| ~dmAuthenticated) { d(j) := 0.U(8.W) }.otherwise { d(j) := Mux(SBDATAWrEn(i) && !SBCSFieldsReg.sbbusy && !SBCSFieldsReg.sbbusyerror && !SBCSRdData.sberror, SBDATAWrData(i)(8j+7,8j), Mux(sb2tl.module.io.rdLoad(4i+j), sb2tl.module.io.dataOut, d(j))) } } SBDATARdData(i) := Cat(d.reverse) RegFieldGroup("dmi_sbdata"+i, Some("SBA Data Register"), Seq(RWNotify(32, SBDATARdData(i), SBDATAWrData(i), SBDATARdEn(i), SBDATAWrEn(i), Some(RegFieldDesc("dmi_sbdata"+i, "SBA data register", reset=Some(0), volatile=true))))) } else { for (j <- 0 to 3) { d(j) := DontCare } Seq.empty[RegField] } } sb2tl.module.io.dataIn := Mux(sb2tl.module.io.wrEn,Cat(SBDATAWrData.reverse),Cat(SBDATAFieldsReg.flatten.reverse)) anyDataRdEn := SBDATARdEn.reduce(_ \|\| _) anyDataWrEn := SBDATAWrEn.reduce(_ \|\| _) val tryWrEn = SBDATAWrEn(0) val tryRdEn = (SBADDRESSWrEn(0) && SBCSFieldsReg.sbreadonaddr) \|\| (SBDATARdEn(0) && SBCSFieldsReg.sbreadondata) val sbAccessError = (SBCSFieldsReg.sbaccess === 0.U) && (SBCSFieldsReg.sbaccess8 =/= 1.U) \|\| (SBCSFieldsReg.sbaccess === 1.U) && (SBCSFieldsReg.sbaccess16 =/= 1.U) \|\| (SBCSFieldsReg.sbaccess === 2.U) && (SBCSFieldsReg.sbaccess32 =/= 1.U) \|\| (SBCSFieldsReg.sbaccess === 3.U) && (SBCSFieldsReg.sbaccess64 =/= 1.U) \|\| (SBCSFieldsReg.sbaccess === 4.U) && (SBCSFieldsReg.sbaccess128 =/= 1.U) \|\| (SBCSFieldsReg.sbaccess > 4.U) val compareAddr = Wire(UInt(32.W)) // Need use written or latched address to detect error case depending on how transaction is initiated compareAddr := Mux(SBADDRESSWrEn(0),SBADDRESSWrData(0),SBADDRESSFieldsReg(0)) val sbAlignmentError = (SBCSFieldsReg.sbaccess === 1.U) && (compareAddr(0) =/= 0.U) \|\| (SBCSFieldsReg.sbaccess === 2.U) && (compareAddr(1,0) =/= 0.U) \|\| (SBCSFieldsReg.sbaccess === 3.U) && (compareAddr(2,0) =/= 0.U) \|\| (SBCSFieldsReg.sbaccess === 4.U) && (compareAddr(3,0) =/= 0.U) sbAccessError.suggestName("sbAccessError") sbAlignmentError.suggestName("sbAlignmentError") sb2tl.module.io.wrEn := dmAuthenticated && tryWrEn && !SBCSFieldsReg.sbbusy && !SBCSFieldsReg.sbbusyerror && !SBCSRdData.sberror && !sbAccessError && !sbAlignmentError sb2tl.module.io.rdEn := dmAuthenticated && tryRdEn && !SBCSFieldsReg.sbbusy && !SBCSFieldsReg.sbbusyerror && !SBCSRdData.sberror && !sbAccessError && !sbAlignmentError sb2tl.module.io.sizeIn := SBCSFieldsReg.sbaccess val sbBusy = (sb2tl.module.io.sbStateOut =/= SystemBusAccessState.Idle.id.U) when (~dmactive \|\| ~dmAuthenticated) { SBCSFieldsReg := SBCSFieldsRegReset }.otherwise { SBCSFieldsReg.sbbusyerror := Mux(sbbusyerrorWrEn && SBCSWrData.sbbusyerror, false.B, // W1C Mux(anyAddressWrEn && sbBusy, true.B, // Set if a write to SBADDRESS occurs while busy Mux((anyDataRdEn \|\| anyDataWrEn) && sbBusy, true.B, SBCSFieldsReg.sbbusyerror))) // Set if any access to SBDATA occurs while busy SBCSFieldsReg.sbreadonaddr := Mux(sbreadonaddrWrEn, SBCSWrData.sbreadonaddr , SBCSFieldsReg.sbreadonaddr) SBCSFieldsReg.sbautoincrement := Mux(sbautoincrementWrEn, SBCSWrData.sbautoincrement, SBCSFieldsReg.sbautoincrement) SBCSFieldsReg.sbreadondata := Mux(sbreadondataWrEn, SBCSWrData.sbreadondata , SBCSFieldsReg.sbreadondata) SBCSFieldsReg.sbaccess := Mux(sbaccessWrEn, SBCSWrData.sbaccess, SBCSFieldsReg.sbaccess) SBCSFieldsReg.sbversion := 1.U(1.W) // This code implements a version of the spec after January 1, 2018 } // sbErrorReg has a per-bit load enable since each bit can be individually cleared by writing a 1 to it val sbErrorReg = Reg(Vec(4, UInt(1.W))) when(~dmactive \|\| ~dmAuthenticated) { for (i <- 0 until 3) sbErrorReg(i) := 0.U }.otherwise { for (i <- 0 until 3) sbErrorReg(i) := Mux(sberrorWrEn && SBCSWrData.sberror(i) === 1.U, NoError.id.U.extract(i), // W1C Mux((sb2tl.module.io.wrEn && !sb2tl.module.io.wrLegal) \|\| (sb2tl.module.io.rdEn && !sb2tl.module.io.rdLegal), BadAddr.id.U.extract(i), // Bad address accessed Mux((tryWrEn \|\| tryRdEn) && sbAlignmentError, AlgnError.id.U.extract(i), // Address alignment error Mux((tryWrEn \|\| tryRdEn) && sbAccessError, BadAccess.id.U.extract(i), // Access size error Mux((sb2tl.module.io.rdDone \|\| sb2tl.module.io.wrDone) && sb2tl.module.io.respError, OtherError.id.U.extract(i), sbErrorReg(i)))))) // Response error from TL } SBCSRdData := SBCSFieldsReg SBCSRdData.sbasize := sb2tl.module.edge.bundle.addressBits.U SBCSRdData.sbaccess128 := (cfg.maxSupportedSBAccess == 128).B SBCSRdData.sbaccess64 := (cfg.maxSupportedSBAccess >= 64).B SBCSRdData.sbaccess32 := (cfg.maxSupportedSBAccess >= 32).B SBCSRdData.sbaccess16 := (cfg.maxSupportedSBAccess >= 16).B SBCSRdData.sbaccess8 := (cfg.maxSupportedSBAccess >= 8).B SBCSRdData.sbbusy := sbBusy SBCSRdData.sberror := sbErrorReg.asUInt when (~dmAuthenticated) { // Read value must be 0 if not authenticated SBCSRdData := 0.U.asTypeOf(new SBCSFields()) } property.cover(SBCSFieldsReg.sbbusyerror, "SBCS Cover", "sberror set") property.cover(SBCSFieldsReg.sbbusy === 3.U, "SBCS Cover", "sbbusyerror alignment error") property.cover((sb2tl.module.io.wrEn \|\| sb2tl.module.io.rdEn) && SBCSFieldsReg.sbaccess === 0.U && !sbAccessError && !sbAlignmentError, "SBCS Cover", "8-bit access") property.cover((sb2tl.module.io.wrEn \|\| sb2tl.module.io.rdEn) && SBCSFieldsReg.sbaccess === 1.U && !sbAccessError && !sbAlignmentError, "SBCS Cover", "16-bit access") property.cover((sb2tl.module.io.wrEn \|\| sb2tl.module.io.rdEn) && SBCSFieldsReg.sbaccess === 2.U && !sbAccessError && !sbAlignmentError, "SBCS Cover", "32-bit access") property.cover((sb2tl.module.io.wrEn \|\| sb2tl.module.io.rdEn) && SBCSFieldsReg.sbaccess === 3.U && !sbAccessError && !sbAlignmentError, "SBCS Cover", "64-bit access") property.cover((sb2tl.module.io.wrEn \|\| sb2tl.module.io.rdEn) && SBCSFieldsReg.sbaccess === 4.U && !sbAccessError && !sbAlignmentError, "SBCS Cover", "128-bit access") property.cover(SBCSFieldsReg.sbautoincrement && SBCSFieldsReg.sbbusy, "SBCS Cover", "Access with autoincrement set") property.cover(!SBCSFieldsReg.sbautoincrement && SBCSFieldsReg.sbbusy, "SBCS Cover", "Access without autoincrement set") property.cover((sb2tl.module.io.wrEn \|\| sb2tl.module.io.rdEn) && SBCSFieldsReg.sbaccess > 4.U, "SBCS Cover", "Invalid sbaccess value") (sbcsfields, sbaddrfields, sbdatafields) } } class SBToTL(implicit p: Parameters) extends LazyModule { val cfg = p(DebugModuleKey).get val node = TLClientNode(Seq(TLMasterPortParameters.v1( clients = Seq(TLMasterParameters.v1("debug")), requestFields = Seq(AMBAProtField())))) lazy val module = new Impl class Impl extends LazyModuleImp(this) { val io = IO(new Bundle { val rdEn = Input(Bool()) val wrEn = Input(Bool()) val addrIn = Input(UInt(128.W)) // TODO: Parameterize these widths val dataIn = Input(UInt(128.W)) val sizeIn = Input(UInt(3.W)) val rdLegal = Output(Bool()) val wrLegal = Output(Bool()) val rdDone = Output(Bool()) val wrDone = Output(Bool()) val respError = Output(Bool()) val dataOut = Output(UInt(8.W)) val rdLoad = Output(Vec(cfg.maxSupportedSBAccess/8, Bool())) val sbStateOut = Output(UInt(log2Ceil(SystemBusAccessState.maxId).W)) }) val rf_reset = IO(Input(Reset())) import SystemBusAccessState._ val (tl, edge) = node.out(0) val sbState = RegInit(0.U) // --- Drive payloads on bus to TileLink --- val d = Queue(tl.d, 2) // Add a small buffer since response could arrive on same cycle as request d.ready := (sbState === SBReadResponse.id.U) \|\| (sbState === SBWriteResponse.id.U) val muxedData = WireInit(0.U(8.W)) val requestValid = tl.a.valid val requestReady = tl.a.ready val responseValid = d.valid val responseReady = d.ready val counter = RegInit(0.U((log2Ceil(cfg.maxSupportedSBAccess/8)+1).W)) val vecData = Wire(Vec(cfg.maxSupportedSBAccess/8, UInt(8.W))) vecData.zipWithIndex.map { case (vd, i) => vd := io.dataIn(8i+7,8i) } muxedData := vecData(counter(log2Ceil(vecData.size)-1,0)) // Need an additional check to determine if address is safe for Get/Put val rdLegal_addr = edge.manager.supportsGetSafe(io.addrIn, io.sizeIn, Some(TransferSizes(1,cfg.maxSupportedSBAccess/8))) val wrLegal_addr = edge.manager.supportsPutFullSafe(io.addrIn, io.sizeIn, Some(TransferSizes(1,cfg.maxSupportedSBAccess/8))) val (_, gbits) = edge.Get(0.U, io.addrIn, io.sizeIn) val (_, pfbits) = edge.Put(0.U, io.addrIn, io.sizeIn, muxedData) io.rdLegal := rdLegal_addr io.wrLegal := wrLegal_addr io.sbStateOut := sbState when(sbState === SBReadRequest.id.U) { tl.a.bits := gbits } .otherwise { tl.a.bits := pfbits } tl.a.bits.user.lift(AMBAProt).foreach { x => x.bufferable := false.B x.modifiable := false.B x.readalloc := false.B x.writealloc := false.B x.privileged := true.B x.secure := true.B x.fetch := false.B } val respError = d.bits.denied \|\| d.bits.corrupt io.respError := respError val wrTxValid = sbState === SBWriteRequest.id.U && requestValid && requestReady val rdTxValid = sbState === SBReadResponse.id.U && responseValid && responseReady val txLast = counter === ((1.U << io.sizeIn) - 1.U) counter := Mux((wrTxValid \|\| rdTxValid) && txLast, 0.U, Mux((wrTxValid \|\| rdTxValid) , counter+1.U, counter)) for (i <- 0 until (cfg.maxSupportedSBAccess/8)) { io.rdLoad(i) := rdTxValid && (counter === i.U) } // --- State Machine to interface with TileLink --- when (sbState === Idle.id.U){ sbState := Mux(io.rdEn && io.rdLegal, SBReadRequest.id.U, Mux(io.wrEn && io.wrLegal, SBWriteRequest.id.U, sbState)) }.elsewhen (sbState === SBReadRequest.id.U){ sbState := Mux(requestValid && requestReady, SBReadResponse.id.U, sbState) }.elsewhen (sbState === SBWriteRequest.id.U){ sbState := Mux(wrTxValid && txLast, SBWriteResponse.id.U, sbState) }.elsewhen (sbState === SBReadResponse.id.U){ sbState := Mux(rdTxValid && txLast, Idle.id.U, sbState) }.elsewhen (sbState === SBWriteResponse.id.U){ sbState := Mux(responseValid && responseReady, Idle.id.U, sbState) } io.rdDone := rdTxValid && txLast io.wrDone := (sbState === SBWriteResponse.id.U) && responseValid && responseReady io.dataOut := d.bits.data tl.a.valid := (sbState === SBReadRequest.id.U) \|\| (sbState === SBWriteRequest.id.U) // Tie off unused channels tl.b.ready := false.B tl.c.valid := false.B tl.e.valid := false.B assert (sbState === Idle.id.U \|\| sbState === SBReadRequest.id.U \|\| sbState === SBWriteRequest.id.U \|\| sbState === SBReadResponse.id.U \|\| sbState === SBWriteResponse.id.U, "SBA state machine in undefined state") property.cover (sbState === Idle.id.U, "SBA State Cover", "SBA Access Idle") property.cover (sbState === SBReadRequest.id.U, "SBA State Cover", "SBA Access Read Req") property.cover (sbState === SBWriteRequest.id.U, "SBA State Cover", "SBA Access Write Req") property.cover (sbState === SBReadResponse.id.U, "SBA State Cover", "SBA Access Read Resp") property.cover (sbState === SBWriteResponse.id.U, "SBA State Cover", "SBA Access Write Resp") property.cover (io.rdEn && !io.rdLegal, "SB Legality Cover", "SBA Rd Address Illegal") property.cover (io.wrEn && !io.wrLegal, "SB Legality Cover", "SBA Wr Address Illegal") } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLDebugModuleInner( // @[Debug.scala:790:9] input clock, // @[Debug.scala:790:9] input reset, // @[Debug.scala:790:9] input auto_sb2tlOpt_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_sb2tlOpt_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_sb2tlOpt_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [3:0] auto_sb2tlOpt_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [31:0] auto_sb2tlOpt_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_sb2tlOpt_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_sb2tlOpt_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_sb2tlOpt_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_sb2tlOpt_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_sb2tlOpt_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_sb2tlOpt_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_sb2tlOpt_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_sb2tlOpt_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [7:0] auto_sb2tlOpt_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_sb2tlOpt_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_tl_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_tl_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_tl_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [11:0] auto_tl_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_tl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_tl_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_tl_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_tl_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_tl_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_tl_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_dmi_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_dmi_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dmi_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dmi_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dmi_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input auto_dmi_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [8:0] auto_dmi_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dmi_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [31:0] auto_dmi_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_dmi_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_dmi_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_dmi_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_dmi_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_dmi_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output auto_dmi_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_dmi_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input io_dmactive, // @[Debug.scala:803:16] input io_innerCtrl_valid, // @[Debug.scala:803:16] input io_innerCtrl_bits_resumereq, // @[Debug.scala:803:16] input [9:0] io_innerCtrl_bits_hartsel, // @[Debug.scala:803:16] input io_innerCtrl_bits_ackhavereset, // @[Debug.scala:803:16] input io_innerCtrl_bits_hasel, // @[Debug.scala:803:16] input io_innerCtrl_bits_hamask_0, // @[Debug.scala:803:16] input io_innerCtrl_bits_hrmask_0, // @[Debug.scala:803:16] output io_hgDebugInt_0, // @[Debug.scala:803:16] input io_hartIsInReset_0, // @[Debug.scala:803:16] input io_tl_clock, // @[Debug.scala:803:16] input io_tl_reset // @[Debug.scala:803:16] ); wire out_front_1_valid; // @[RegisterRouter.scala:87:24] wire out_front_1_ready; // @[RegisterRouter.scala:87:24] wire out_1_bits_read; // @[RegisterRouter.scala:87:24] wire [10:0] out_1_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [8:0] in_1_bits_index; // @[RegisterRouter.scala:73:18] wire in_1_bits_read; // @[RegisterRouter.scala:73:18] wire [7:0] _accessRegisterCommandReg_WIRE_cmdtype; // @[Debug.scala:1533:71] wire _accessRegisterCommandReg_WIRE_reserved0; // @[Debug.scala:1533:71] wire [2:0] _accessRegisterCommandReg_WIRE_size; // @[Debug.scala:1533:71] wire _accessRegisterCommandReg_WIRE_reserved1; // @[Debug.scala:1533:71] wire _accessRegisterCommandReg_WIRE_postexec; // @[Debug.scala:1533:71] wire _accessRegisterCommandReg_WIRE_transfer; // @[Debug.scala:1533:71] wire _accessRegisterCommandReg_WIRE_write; // @[Debug.scala:1533:71] wire [15:0] _accessRegisterCommandReg_WIRE_regno; // @[Debug.scala:1533:71] wire [7:0] _accessRegisterCommandWr_WIRE_cmdtype; // @[Debug.scala:1531:74] wire _accessRegisterCommandWr_WIRE_reserved0; // @[Debug.scala:1531:74] wire [2:0] _accessRegisterCommandWr_WIRE_size; // @[Debug.scala:1531:74] wire _accessRegisterCommandWr_WIRE_reserved1; // @[Debug.scala:1531:74] wire _accessRegisterCommandWr_WIRE_postexec; // @[Debug.scala:1531:74] wire _accessRegisterCommandWr_WIRE_transfer; // @[Debug.scala:1531:74] wire _accessRegisterCommandWr_WIRE_write; // @[Debug.scala:1531:74] wire [15:0] _accessRegisterCommandWr_WIRE_regno; // @[Debug.scala:1531:74] wire out_front_valid; // @[RegisterRouter.scala:87:24] wire out_front_ready; // @[RegisterRouter.scala:87:24] wire out_bits_read; // @[RegisterRouter.scala:87:24] wire out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [6:0] in_bits_index; // @[RegisterRouter.scala:73:18] wire in_bits_read; // @[RegisterRouter.scala:73:18] wire SBDATAWrEn_0; // @[SBA.scala:150:35] wire [31:0] SBDATARdData_1; // @[SBA.scala:145:35] wire [31:0] SBDATARdData_0; // @[SBA.scala:145:35] wire SBADDRESSWrEn_0; // @[SBA.scala:108:38] wire [7:0] _COMMANDWrData_WIRE_cmdtype; // @[Debug.scala:1280:65] wire [23:0] _COMMANDWrData_WIRE_control; // @[Debug.scala:1280:65] wire [15:0] ABSTRACTAUTOWrData_autoexecprogbuf; // @[Debug.scala:1236:41] wire [31:0] _HALTSUM1RdData_WIRE; // @[Debug.scala:1170:48] wire _sb2tlOpt_io_rdLegal; // @[Debug.scala:782:52] wire _sb2tlOpt_io_wrLegal; // @[Debug.scala:782:52] wire _sb2tlOpt_io_rdDone; // @[Debug.scala:782:52] wire _sb2tlOpt_io_wrDone; // @[Debug.scala:782:52] wire _sb2tlOpt_io_respError; // @[Debug.scala:782:52] wire [7:0] _sb2tlOpt_io_dataOut; // @[Debug.scala:782:52] wire _sb2tlOpt_io_rdLoad_0; // @[Debug.scala:782:52] wire _sb2tlOpt_io_rdLoad_1; // @[Debug.scala:782:52] wire _sb2tlOpt_io_rdLoad_2; // @[Debug.scala:782:52] wire _sb2tlOpt_io_rdLoad_3; // @[Debug.scala:782:52] wire _sb2tlOpt_io_rdLoad_4; // @[Debug.scala:782:52] wire _sb2tlOpt_io_rdLoad_5; // @[Debug.scala:782:52] wire _sb2tlOpt_io_rdLoad_6; // @[Debug.scala:782:52] wire _sb2tlOpt_io_rdLoad_7; // @[Debug.scala:782:52] wire [2:0] _sb2tlOpt_io_sbStateOut; // @[Debug.scala:782:52] wire auto_sb2tlOpt_out_a_ready_0 = auto_sb2tlOpt_out_a_ready; // @[Debug.scala:790:9] wire auto_sb2tlOpt_out_d_valid_0 = auto_sb2tlOpt_out_d_valid; // @[Debug.scala:790:9] wire [2:0] auto_sb2tlOpt_out_d_bits_opcode_0 = auto_sb2tlOpt_out_d_bits_opcode; // @[Debug.scala:790:9] wire [1:0] auto_sb2tlOpt_out_d_bits_param_0 = auto_sb2tlOpt_out_d_bits_param; // @[Debug.scala:790:9] wire [3:0] auto_sb2tlOpt_out_d_bits_size_0 = auto_sb2tlOpt_out_d_bits_size; // @[Debug.scala:790:9] wire [2:0] auto_sb2tlOpt_out_d_bits_sink_0 = auto_sb2tlOpt_out_d_bits_sink; // @[Debug.scala:790:9] wire auto_sb2tlOpt_out_d_bits_denied_0 = auto_sb2tlOpt_out_d_bits_denied; // @[Debug.scala:790:9] wire [7:0] auto_sb2tlOpt_out_d_bits_data_0 = auto_sb2tlOpt_out_d_bits_data; // @[Debug.scala:790:9] wire auto_sb2tlOpt_out_d_bits_corrupt_0 = auto_sb2tlOpt_out_d_bits_corrupt; // @[Debug.scala:790:9] wire auto_tl_in_a_valid_0 = auto_tl_in_a_valid; // @[Debug.scala:790:9] wire [2:0] auto_tl_in_a_bits_opcode_0 = auto_tl_in_a_bits_opcode; // @[Debug.scala:790:9] wire [2:0] auto_tl_in_a_bits_param_0 = auto_tl_in_a_bits_param; // @[Debug.scala:790:9] wire [1:0] auto_tl_in_a_bits_size_0 = auto_tl_in_a_bits_size; // @[Debug.scala:790:9] wire [10:0] auto_tl_in_a_bits_source_0 = auto_tl_in_a_bits_source; // @[Debug.scala:790:9] wire [11:0] auto_tl_in_a_bits_address_0 = auto_tl_in_a_bits_address; // @[Debug.scala:790:9] wire [7:0] auto_tl_in_a_bits_mask_0 = auto_tl_in_a_bits_mask; // @[Debug.scala:790:9] wire [63:0] auto_tl_in_a_bits_data_0 = auto_tl_in_a_bits_data; // @[Debug.scala:790:9] wire auto_tl_in_a_bits_corrupt_0 = auto_tl_in_a_bits_corrupt; // @[Debug.scala:790:9] wire auto_tl_in_d_ready_0 = auto_tl_in_d_ready; // @[Debug.scala:790:9] wire auto_dmi_in_a_valid_0 = auto_dmi_in_a_valid; // @[Debug.scala:790:9] wire [2:0] auto_dmi_in_a_bits_opcode_0 = auto_dmi_in_a_bits_opcode; // @[Debug.scala:790:9] wire [2:0] auto_dmi_in_a_bits_param_0 = auto_dmi_in_a_bits_param; // @[Debug.scala:790:9] wire [1:0] auto_dmi_in_a_bits_size_0 = auto_dmi_in_a_bits_size; // @[Debug.scala:790:9] wire auto_dmi_in_a_bits_source_0 = auto_dmi_in_a_bits_source; // @[Debug.scala:790:9] wire [8:0] auto_dmi_in_a_bits_address_0 = auto_dmi_in_a_bits_address; // @[Debug.scala:790:9] wire [3:0] auto_dmi_in_a_bits_mask_0 = auto_dmi_in_a_bits_mask; // @[Debug.scala:790:9] wire [31:0] auto_dmi_in_a_bits_data_0 = auto_dmi_in_a_bits_data; // @[Debug.scala:790:9] wire auto_dmi_in_a_bits_corrupt_0 = auto_dmi_in_a_bits_corrupt; // @[Debug.scala:790:9] wire auto_dmi_in_d_ready_0 = auto_dmi_in_d_ready; // @[Debug.scala:790:9] wire io_dmactive_0 = io_dmactive; // @[Debug.scala:790:9] wire io_innerCtrl_valid_0 = io_innerCtrl_valid; // @[Debug.scala:790:9] wire io_innerCtrl_bits_resumereq_0 = io_innerCtrl_bits_resumereq; // @[Debug.scala:790:9] wire [9:0] io_innerCtrl_bits_hartsel_0 = io_innerCtrl_bits_hartsel; // @[Debug.scala:790:9] wire io_innerCtrl_bits_ackhavereset_0 = io_innerCtrl_bits_ackhavereset; // @[Debug.scala:790:9] wire io_innerCtrl_bits_hasel_0 = io_innerCtrl_bits_hasel; // @[Debug.scala:790:9] wire io_innerCtrl_bits_hamask_0_0 = io_innerCtrl_bits_hamask_0; // @[Debug.scala:790:9] wire io_innerCtrl_bits_hrmask_0_0 = io_innerCtrl_bits_hrmask_0; // @[Debug.scala:790:9] wire io_hartIsInReset_0_0 = io_hartIsInReset_0; // @[Debug.scala:790:9] wire io_tl_clock_0 = io_tl_clock; // @[Debug.scala:790:9] wire io_tl_reset_0 = io_tl_reset; // @[Debug.scala:790:9] wire auto_sb2tlOpt_out_a_bits_source = 1'h0; // @[Debug.scala:790:9] wire auto_sb2tlOpt_out_a_bits_corrupt = 1'h0; // @[Debug.scala:790:9] wire auto_sb2tlOpt_out_d_bits_source = 1'h0; // @[Debug.scala:790:9] wire auto_custom_in_addr = 1'h0; // @[Debug.scala:790:9] wire auto_custom_in_ready = 1'h0; // @[Debug.scala:790:9] wire auto_custom_in_valid = 1'h0; // @[Debug.scala:790:9] wire auto_tl_in_d_bits_sink = 1'h0; // @[Debug.scala:790:9] wire auto_tl_in_d_bits_denied = 1'h0; // @[Debug.scala:790:9] wire auto_tl_in_d_bits_corrupt = 1'h0; // @[Debug.scala:790:9] wire auto_dmi_in_d_bits_sink = 1'h0; // @[Debug.scala:790:9] wire auto_dmi_in_d_bits_denied = 1'h0; // @[Debug.scala:790:9] wire auto_dmi_in_d_bits_corrupt = 1'h0; // @[Debug.scala:790:9] wire io_debugUnavail_0 = 1'h0; // @[Debug.scala:790:9] wire dmiNodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire dmiNodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire dmiNodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire tlNodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire tlNodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire tlNodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire customNodeIn_addr = 1'h0; // @[MixedNode.scala:551:17] wire customNodeIn_ready = 1'h0; // @[MixedNode.scala:551:17] wire customNodeIn_valid = 1'h0; // @[MixedNode.scala:551:17] wire _dmiProgramBufferRdEn_WIRE_0 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_1 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_2 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_3 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_4 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_5 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_6 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_7 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_8 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_9 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_10 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_11 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_12 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_13 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_14 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_15 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_16 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_17 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_18 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_19 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_20 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_21 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_22 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_23 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_24 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_25 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_26 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_27 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_28 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_29 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_30 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_31 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_32 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_33 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_34 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_35 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_36 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_37 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_38 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_39 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_40 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_41 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_42 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_43 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_44 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_45 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_46 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_47 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_48 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_49 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_50 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_51 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_52 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_53 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_54 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_55 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_56 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_57 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_58 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_59 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_60 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_61 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_62 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_63 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferWrEnMaybe_WIRE_0 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_1 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_2 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_3 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_4 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_5 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_6 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_7 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_8 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_9 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_10 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_11 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_12 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_13 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_14 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_15 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_16 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_17 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_18 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_19 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_20 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_21 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_22 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_23 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_24 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_25 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_26 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_27 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_28 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_29 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_30 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_31 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_32 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_33 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_34 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_35 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_36 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_37 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_38 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_39 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_40 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_41 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_42 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_43 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_44 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_45 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_46 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_47 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_48 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_49 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_50 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_51 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_52 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_53 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_54 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_55 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_56 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_57 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_58 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_59 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_60 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_61 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_62 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_63 = 1'h0; // @[Debug.scala:889:53] wire _dmiAbstractDataRdEn_WIRE_0 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_1 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_2 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_3 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_4 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_5 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_6 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_7 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_8 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_9 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_10 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_11 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_12 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_13 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_14 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_15 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_16 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_17 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_18 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_19 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_20 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_21 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_22 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_23 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_24 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_25 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_26 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_27 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_28 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_29 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_30 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_31 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataWrEnMaybe_WIRE_0 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_1 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_2 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_3 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_4 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_5 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_6 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_7 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_8 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_9 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_10 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_11 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_12 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_13 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_14 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_15 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_16 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_17 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_18 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_19 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_20 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_21 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_22 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_23 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_24 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_25 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_26 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_27 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_28 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_29 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_30 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_31 = 1'h0; // @[Debug.scala:893:52] wire _hamaskFull_WIRE_0 = 1'h0; // @[Debug.scala:903:38] wire _hamaskWrSel_WIRE_0 = 1'h0; // @[Debug.scala:933:39] wire _hrReset_WIRE_0 = 1'h0; // @[Debug.scala:945:38] wire hrReset_0 = 1'h0; // @[Debug.scala:945:30] wire _hrDebugIntReg_WIRE_0 = 1'h0; // @[Debug.scala:961:42] wire _DMSTATUSRdData_WIRE_impebreak = 1'h0; // @[Debug.scala:978:47] wire _DMSTATUSRdData_WIRE_allhavereset = 1'h0; // @[Debug.scala:978:47] wire _DMSTATUSRdData_WIRE_anyhavereset = 1'h0; // @[Debug.scala:978:47] wire _DMSTATUSRdData_WIRE_allresumeack = 1'h0; // @[Debug.scala:978:47] wire _DMSTATUSRdData_WIRE_anyresumeack = 1'h0; // @[Debug.scala:978:47] wire _DMSTATUSRdData_WIRE_allnonexistent = 1'h0; // @[Debug.scala:978:47] wire _DMSTATUSRdData_WIRE_anynonexistent = 1'h0; // @[Debug.scala:978:47] wire _DMSTATUSRdData_WIRE_allunavail = 1'h0; // @[Debug.scala:978:47] wire _DMSTATUSRdData_WIRE_anyunavail = 1'h0; // @[Debug.scala:978:47] wire _DMSTATUSRdData_WIRE_allrunning = 1'h0; // @[Debug.scala:978:47] wire _DMSTATUSRdData_WIRE_anyrunning = 1'h0; // @[Debug.scala:978:47] wire _DMSTATUSRdData_WIRE_allhalted = 1'h0; // @[Debug.scala:978:47] wire _DMSTATUSRdData_WIRE_anyhalted = 1'h0; // @[Debug.scala:978:47] wire _DMSTATUSRdData_WIRE_authenticated = 1'h0; // @[Debug.scala:978:47] wire _DMSTATUSRdData_WIRE_authbusy = 1'h0; // @[Debug.scala:978:47] wire _DMSTATUSRdData_WIRE_hasresethaltreq = 1'h0; // @[Debug.scala:978:47] wire _DMSTATUSRdData_WIRE_confstrptrvalid = 1'h0; // @[Debug.scala:978:47] wire DMSTATUSRdData_impebreak = 1'h0; // @[Debug.scala:978:34] wire DMSTATUSRdData_anyunavail = 1'h0; // @[Debug.scala:978:34] wire DMSTATUSRdData_authbusy = 1'h0; // @[Debug.scala:978:34] wire DMSTATUSRdData_confstrptrvalid = 1'h0; // @[Debug.scala:978:34] wire _DMSTATUSRdData_anynonexistent_T = 1'h0; // @[Debug.scala:988:57] wire _DMSTATUSRdData_allnonexistent_T = 1'h0; // @[Debug.scala:991:57] wire _DMSTATUSRdData_anyunavail_T = 1'h0; // @[package.scala:74:72] wire _DMCS2RdData_WIRE_hgwrite = 1'h0; // @[Debug.scala:1025:47] wire _DMCS2RdData_WIRE_hgselect = 1'h0; // @[Debug.scala:1025:47] wire DMCS2RdData_hgwrite = 1'h0; // @[Debug.scala:1025:34] wire DMCS2RdData_hgselect = 1'h0; // @[Debug.scala:1025:34] wire _DMCS2WrData_WIRE_hgwrite = 1'h0; // @[Debug.scala:1026:47] wire _DMCS2WrData_WIRE_hgselect = 1'h0; // @[Debug.scala:1026:47] wire DMCS2WrData_hgwrite = 1'h0; // @[Debug.scala:1026:34] wire DMCS2WrData_hgselect = 1'h0; // @[Debug.scala:1026:34] wire hgselectWrEn = 1'h0; // @[Debug.scala:1027:34] wire hgwriteWrEn = 1'h0; // @[Debug.scala:1028:34] wire haltgroupWrEn = 1'h0; // @[Debug.scala:1029:34] wire exttriggerWrEn = 1'h0; // @[Debug.scala:1030:34] wire _hgDebugInt_WIRE_0 = 1'h0; // @[Debug.scala:1031:42] wire hgDebugInt_0 = 1'h0; // @[Debug.scala:1031:34] wire _selectedHaltedStatus_T = 1'h0; // @[Debug.scala:1172:53] wire _selectedHaltedStatus_T_1 = 1'h0; // @[Debug.scala:1172:59] wire _selectedHaltedStatus_T_2 = 1'h0; // @[Debug.scala:1172:114] wire _selectedHaltedStatus_WIRE = 1'h0; wire _ABSTRACTCSReset_WIRE_busy = 1'h0; // @[Debug.scala:1179:48] wire _ABSTRACTCSReset_WIRE_reserved2 = 1'h0; // @[Debug.scala:1179:48] wire ABSTRACTCSReset_busy = 1'h0; // @[Debug.scala:1179:35] wire ABSTRACTCSReset_reserved2 = 1'h0; // @[Debug.scala:1179:35] wire _ABSTRACTCSWrData_WIRE_busy = 1'h0; // @[Debug.scala:1184:52] wire _ABSTRACTCSWrData_WIRE_reserved2 = 1'h0; // @[Debug.scala:1184:52] wire ABSTRACTCSWrData_busy = 1'h0; // @[Debug.scala:1184:39] wire ABSTRACTCSWrData_reserved2 = 1'h0; // @[Debug.scala:1184:39] wire ABSTRACTCSRdData_reserved2 = 1'h0; // @[Debug.scala:1185:39] wire ABSTRACTCSRdEn = 1'h0; // @[Debug.scala:1187:34] wire ABSTRACTAUTORdEn = 1'h0; // @[Debug.scala:1239:36] wire _dmiAbstractDataAccessVec_WIRE_0 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_1 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_2 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_3 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_4 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_5 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_6 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_7 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_8 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_9 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_10 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_11 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_12 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_13 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_14 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_15 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_16 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_17 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_18 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_19 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_20 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_21 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_22 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_23 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_24 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_25 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_26 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_27 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_28 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_29 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_30 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_31 = 1'h0; // @[Debug.scala:1257:53] wire _dmiProgramBufferAccessVec_WIRE_0 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_1 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_2 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_3 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_4 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_5 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_6 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_7 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_8 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_9 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_10 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_11 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_12 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_13 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_14 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_15 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_16 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_17 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_18 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_19 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_20 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_21 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_22 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_23 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_24 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_25 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_26 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_27 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_28 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_29 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_30 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_31 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_32 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_33 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_34 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_35 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_36 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_37 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_38 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_39 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_40 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_41 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_42 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_43 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_44 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_45 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_46 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_47 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_48 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_49 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_50 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_51 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_52 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_53 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_54 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_55 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_56 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_57 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_58 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_59 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_60 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_61 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_62 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_63 = 1'h0; // @[Debug.scala:1260:54] wire _autoexecData_WIRE_0 = 1'h0; // @[Debug.scala:1267:41] wire _autoexecData_WIRE_1 = 1'h0; // @[Debug.scala:1267:41] wire _autoexecData_WIRE_2 = 1'h0; // @[Debug.scala:1267:41] wire _autoexecData_WIRE_3 = 1'h0; // @[Debug.scala:1267:41] wire _autoexecData_WIRE_4 = 1'h0; // @[Debug.scala:1267:41] wire _autoexecData_WIRE_5 = 1'h0; // @[Debug.scala:1267:41] wire _autoexecData_WIRE_6 = 1'h0; // @[Debug.scala:1267:41] wire _autoexecData_WIRE_7 = 1'h0; // @[Debug.scala:1267:41] wire _autoexecProg_WIRE_0 = 1'h0; // @[Debug.scala:1268:41] wire _autoexecProg_WIRE_1 = 1'h0; // @[Debug.scala:1268:41] wire _autoexecProg_WIRE_2 = 1'h0; // @[Debug.scala:1268:41] wire _autoexecProg_WIRE_3 = 1'h0; // @[Debug.scala:1268:41] wire _autoexecProg_WIRE_4 = 1'h0; // @[Debug.scala:1268:41] wire _autoexecProg_WIRE_5 = 1'h0; // @[Debug.scala:1268:41] wire _autoexecProg_WIRE_6 = 1'h0; // @[Debug.scala:1268:41] wire _autoexecProg_WIRE_7 = 1'h0; // @[Debug.scala:1268:41] wire _autoexecProg_WIRE_8 = 1'h0; // @[Debug.scala:1268:41] wire _autoexecProg_WIRE_9 = 1'h0; // @[Debug.scala:1268:41] wire _autoexecProg_WIRE_10 = 1'h0; // @[Debug.scala:1268:41] wire _autoexecProg_WIRE_11 = 1'h0; // @[Debug.scala:1268:41] wire _autoexecProg_WIRE_12 = 1'h0; // @[Debug.scala:1268:41] wire _autoexecProg_WIRE_13 = 1'h0; // @[Debug.scala:1268:41] wire _autoexecProg_WIRE_14 = 1'h0; // @[Debug.scala:1268:41] wire _autoexecProg_WIRE_15 = 1'h0; // @[Debug.scala:1268:41] wire authRdEnMaybe = 1'h0; // @[Debug.scala:1356:33] wire authWrEnMaybe = 1'h0; // @[Debug.scala:1357:33] wire _SBCSFieldsRegReset_WIRE_sbbusyerror = 1'h0; // @[SBA.scala:49:51] wire _SBCSFieldsRegReset_WIRE_sbbusy = 1'h0; // @[SBA.scala:49:51] wire _SBCSFieldsRegReset_WIRE_sbreadonaddr = 1'h0; // @[SBA.scala:49:51] wire _SBCSFieldsRegReset_WIRE_sbautoincrement = 1'h0; // @[SBA.scala:49:51] wire _SBCSFieldsRegReset_WIRE_sbreadondata = 1'h0; // @[SBA.scala:49:51] wire _SBCSFieldsRegReset_WIRE_sbaccess128 = 1'h0; // @[SBA.scala:49:51] wire _SBCSFieldsRegReset_WIRE_sbaccess64 = 1'h0; // @[SBA.scala:49:51] wire _SBCSFieldsRegReset_WIRE_sbaccess32 = 1'h0; // @[SBA.scala:49:51] wire _SBCSFieldsRegReset_WIRE_sbaccess16 = 1'h0; // @[SBA.scala:49:51] wire _SBCSFieldsRegReset_WIRE_sbaccess8 = 1'h0; // @[SBA.scala:49:51] wire SBCSFieldsRegReset_sbbusyerror = 1'h0; // @[SBA.scala:49:38] wire SBCSFieldsRegReset_sbreadonaddr = 1'h0; // @[SBA.scala:49:38] wire SBCSFieldsRegReset_sbautoincrement = 1'h0; // @[SBA.scala:49:38] wire SBCSFieldsRegReset_sbreadondata = 1'h0; // @[SBA.scala:49:38] wire SBCSFieldsRegReset_sbaccess128 = 1'h0; // @[SBA.scala:49:38] wire _SBCSRdData_WIRE_sbbusyerror = 1'h0; // @[SBA.scala:60:51] wire _SBCSRdData_WIRE_sbbusy = 1'h0; // @[SBA.scala:60:51] wire _SBCSRdData_WIRE_sbreadonaddr = 1'h0; // @[SBA.scala:60:51] wire _SBCSRdData_WIRE_sbautoincrement = 1'h0; // @[SBA.scala:60:51] wire _SBCSRdData_WIRE_sbreadondata = 1'h0; // @[SBA.scala:60:51] wire _SBCSRdData_WIRE_sbaccess128 = 1'h0; // @[SBA.scala:60:51] wire _SBCSRdData_WIRE_sbaccess64 = 1'h0; // @[SBA.scala:60:51] wire _SBCSRdData_WIRE_sbaccess32 = 1'h0; // @[SBA.scala:60:51] wire _SBCSRdData_WIRE_sbaccess16 = 1'h0; // @[SBA.scala:60:51] wire _SBCSRdData_WIRE_sbaccess8 = 1'h0; // @[SBA.scala:60:51] wire SBCSRdData_sbaccess128 = 1'h0; // @[SBA.scala:60:38] wire _SBCSWrData_WIRE_sbbusyerror = 1'h0; // @[SBA.scala:63:61] wire _SBCSWrData_WIRE_sbbusy = 1'h0; // @[SBA.scala:63:61] wire _SBCSWrData_WIRE_sbreadonaddr = 1'h0; // @[SBA.scala:63:61] wire _SBCSWrData_WIRE_sbautoincrement = 1'h0; // @[SBA.scala:63:61] wire _SBCSWrData_WIRE_sbreadondata = 1'h0; // @[SBA.scala:63:61] wire _SBCSWrData_WIRE_sbaccess128 = 1'h0; // @[SBA.scala:63:61] wire _SBCSWrData_WIRE_sbaccess64 = 1'h0; // @[SBA.scala:63:61] wire _SBCSWrData_WIRE_sbaccess32 = 1'h0; // @[SBA.scala:63:61] wire _SBCSWrData_WIRE_sbaccess16 = 1'h0; // @[SBA.scala:63:61] wire _SBCSWrData_WIRE_sbaccess8 = 1'h0; // @[SBA.scala:63:61] wire _SBCSWrData_T = 1'h0; // @[SBA.scala:63:61] wire _SBCSWrData_T_1 = 1'h0; // @[SBA.scala:63:61] wire _SBCSWrData_T_2 = 1'h0; // @[SBA.scala:63:61] wire _SBCSWrData_T_3 = 1'h0; // @[SBA.scala:63:61] wire _SBCSWrData_T_4 = 1'h0; // @[SBA.scala:63:61] wire _SBCSWrData_T_7 = 1'h0; // @[SBA.scala:63:61] wire _SBCSWrData_T_8 = 1'h0; // @[SBA.scala:63:61] wire _SBCSWrData_T_10 = 1'h0; // @[SBA.scala:63:61] wire _SBCSWrData_T_11 = 1'h0; // @[SBA.scala:63:61] wire _SBCSWrData_T_12 = 1'h0; // @[SBA.scala:63:61] wire SBCSWrData_sbbusy = 1'h0; // @[SBA.scala:63:38] wire SBCSWrData_sbaccess128 = 1'h0; // @[SBA.scala:63:38] wire SBCSWrData_sbaccess64 = 1'h0; // @[SBA.scala:63:38] wire SBCSWrData_sbaccess32 = 1'h0; // @[SBA.scala:63:38] wire SBCSWrData_sbaccess16 = 1'h0; // @[SBA.scala:63:38] wire SBCSWrData_sbaccess8 = 1'h0; // @[SBA.scala:63:38] wire _SBADDRESSRdEn_WIRE_0 = 1'h0; // @[SBA.scala:107:46] wire _SBADDRESSRdEn_WIRE_1 = 1'h0; // @[SBA.scala:107:46] wire _SBADDRESSRdEn_WIRE_2 = 1'h0; // @[SBA.scala:107:46] wire _SBADDRESSRdEn_WIRE_3 = 1'h0; // @[SBA.scala:107:46] wire SBADDRESSRdEn_1 = 1'h0; // @[SBA.scala:107:38] wire SBADDRESSRdEn_2 = 1'h0; // @[SBA.scala:107:38] wire SBADDRESSRdEn_3 = 1'h0; // @[SBA.scala:107:38] wire _SBADDRESSWrEn_WIRE_0 = 1'h0; // @[SBA.scala:108:46] wire _SBADDRESSWrEn_WIRE_1 = 1'h0; // @[SBA.scala:108:46] wire _SBADDRESSWrEn_WIRE_2 = 1'h0; // @[SBA.scala:108:46] wire _SBADDRESSWrEn_WIRE_3 = 1'h0; // @[SBA.scala:108:46] wire SBADDRESSWrEn_1 = 1'h0; // @[SBA.scala:108:38] wire SBADDRESSWrEn_2 = 1'h0; // @[SBA.scala:108:38] wire SBADDRESSWrEn_3 = 1'h0; // @[SBA.scala:108:38] wire _SBDATARdEn_WIRE_0 = 1'h0; // @[SBA.scala:149:43] wire _SBDATARdEn_WIRE_1 = 1'h0; // @[SBA.scala:149:43] wire _SBDATARdEn_WIRE_2 = 1'h0; // @[SBA.scala:149:43] wire _SBDATARdEn_WIRE_3 = 1'h0; // @[SBA.scala:149:43] wire SBDATARdEn_2 = 1'h0; // @[SBA.scala:149:35] wire SBDATARdEn_3 = 1'h0; // @[SBA.scala:149:35] wire _SBDATAWrEn_WIRE_0 = 1'h0; // @[SBA.scala:150:43] wire _SBDATAWrEn_WIRE_1 = 1'h0; // @[SBA.scala:150:43] wire _SBDATAWrEn_WIRE_2 = 1'h0; // @[SBA.scala:150:43] wire _SBDATAWrEn_WIRE_3 = 1'h0; // @[SBA.scala:150:43] wire SBDATAWrEn_2 = 1'h0; // @[SBA.scala:150:35] wire SBDATAWrEn_3 = 1'h0; // @[SBA.scala:150:35] wire _sbAccessError_T_1 = 1'h0; // @[SBA.scala:182:88] wire _sbAccessError_T_2 = 1'h0; // @[SBA.scala:182:58] wire _sbAccessError_T_4 = 1'h0; // @[SBA.scala:183:88] wire _sbAccessError_T_5 = 1'h0; // @[SBA.scala:183:58] wire _sbAccessError_T_6 = 1'h0; // @[SBA.scala:182:97] wire _sbAccessError_T_8 = 1'h0; // @[SBA.scala:184:88] wire _sbAccessError_T_9 = 1'h0; // @[SBA.scala:184:58] wire _sbAccessError_T_10 = 1'h0; // @[SBA.scala:183:97] wire _sbAccessError_T_12 = 1'h0; // @[SBA.scala:185:88] wire _sbAccessError_T_13 = 1'h0; // @[SBA.scala:185:58] wire _sbAccessError_T_14 = 1'h0; // @[SBA.scala:184:97] wire _SBCSRdData_WIRE_1_sbbusyerror = 1'h0; // @[SBA.scala:243:33] wire _SBCSRdData_WIRE_1_sbbusy = 1'h0; // @[SBA.scala:243:33] wire _SBCSRdData_WIRE_1_sbreadonaddr = 1'h0; // @[SBA.scala:243:33] wire _SBCSRdData_WIRE_1_sbautoincrement = 1'h0; // @[SBA.scala:243:33] wire _SBCSRdData_WIRE_1_sbreadondata = 1'h0; // @[SBA.scala:243:33] wire _SBCSRdData_WIRE_1_sbaccess128 = 1'h0; // @[SBA.scala:243:33] wire _SBCSRdData_WIRE_1_sbaccess64 = 1'h0; // @[SBA.scala:243:33] wire _SBCSRdData_WIRE_1_sbaccess32 = 1'h0; // @[SBA.scala:243:33] wire _SBCSRdData_WIRE_1_sbaccess16 = 1'h0; // @[SBA.scala:243:33] wire _SBCSRdData_WIRE_1_sbaccess8 = 1'h0; // @[SBA.scala:243:33] wire _out_rifireMux_T_8 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_12 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_16 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_52 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_56 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_60 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_64 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_68 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_76 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_84 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_88 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_104 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_108 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_112 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_116 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_120 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_124 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_128 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_196 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_200 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_204 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_208 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_212 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_216 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_220 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_224 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_236 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_240 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_252 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_256 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_258 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wifireMux_T_9 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_13 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_17 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_53 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_57 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_61 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_65 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_69 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_77 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_85 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_89 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_105 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_109 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_113 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_117 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_121 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_125 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_129 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_197 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_201 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_205 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_209 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_213 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_217 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_221 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_225 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_237 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_241 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_253 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_257 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_259 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_rofireMux_T_8 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_12 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_16 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_52 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_56 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_60 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_64 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_68 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_76 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_84 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_88 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_104 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_108 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_112 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_116 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_120 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_124 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_128 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_196 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_200 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_204 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_208 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_212 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_216 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_220 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_224 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_236 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_240 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_252 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_256 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_258 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wofireMux_T_9 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_13 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_17 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_53 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_57 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_61 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_65 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_69 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_77 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_85 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_89 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_105 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_109 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_113 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_117 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_121 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_125 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_129 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_197 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_201 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_205 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_209 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_213 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_217 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_221 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_225 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_237 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_241 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_253 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_257 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_259 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T_2 = 1'h0; // @[MuxLiteral.scala:49:17] wire dmiNodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17] wire dmiNodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17] wire dmiNodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17] wire _jalAbstract_WIRE_imm3 = 1'h0; // @[Debug.scala:1497:66] wire _jalAbstract_WIRE_imm1 = 1'h0; // @[Debug.scala:1497:66] wire jalAbstract_imm3 = 1'h0; // @[Debug.scala:1497:32] wire jalAbstract_imm1 = 1'h0; // @[Debug.scala:1497:32] wire _immBits_T = 1'h0; // @[Debug.scala:1575:48] wire _immBits_T_1 = 1'h0; // @[Debug.scala:1575:48] wire _immBits_T_2 = 1'h0; // @[Debug.scala:1575:48] wire _immBits_T_6 = 1'h0; // @[Debug.scala:1575:48] wire _immBits_T_7 = 1'h0; // @[Debug.scala:1575:48] wire _immBits_T_8 = 1'h0; // @[Debug.scala:1575:48] wire _immBits_T_9 = 1'h0; // @[Debug.scala:1575:48] wire _immBits_T_10 = 1'h0; // @[Debug.scala:1575:48] wire _immBits_T_11 = 1'h0; // @[Debug.scala:1575:48] wire _immBits_T_12 = 1'h0; // @[Debug.scala:1575:48] wire _immBits_T_13 = 1'h0; // @[Debug.scala:1575:48] wire _immBits_T_14 = 1'h0; // @[Debug.scala:1575:48] wire _immBits_T_15 = 1'h0; // @[Debug.scala:1575:48] wire _immBits_T_16 = 1'h0; // @[Debug.scala:1575:48] wire _immBits_T_17 = 1'h0; // @[Debug.scala:1575:48] wire _immBits_T_18 = 1'h0; // @[Debug.scala:1575:48] wire _immBits_T_19 = 1'h0; // @[Debug.scala:1575:48] wire _immBits_T_20 = 1'h0; // @[Debug.scala:1575:48] wire _immBits_WIRE_0 = 1'h0; // @[Debug.scala:1575:39] wire _immBits_WIRE_1 = 1'h0; // @[Debug.scala:1575:39] wire _immBits_WIRE_2 = 1'h0; // @[Debug.scala:1575:39] wire _immBits_WIRE_6 = 1'h0; // @[Debug.scala:1575:39] wire _immBits_WIRE_7 = 1'h0; // @[Debug.scala:1575:39] wire _immBits_WIRE_8 = 1'h0; // @[Debug.scala:1575:39] wire _immBits_WIRE_9 = 1'h0; // @[Debug.scala:1575:39] wire _immBits_WIRE_10 = 1'h0; // @[Debug.scala:1575:39] wire _immBits_WIRE_11 = 1'h0; // @[Debug.scala:1575:39] wire _immBits_WIRE_12 = 1'h0; // @[Debug.scala:1575:39] wire _immBits_WIRE_13 = 1'h0; // @[Debug.scala:1575:39] wire _immBits_WIRE_14 = 1'h0; // @[Debug.scala:1575:39] wire _immBits_WIRE_15 = 1'h0; // @[Debug.scala:1575:39] wire _immBits_WIRE_16 = 1'h0; // @[Debug.scala:1575:39] wire _immBits_WIRE_17 = 1'h0; // @[Debug.scala:1575:39] wire _immBits_WIRE_18 = 1'h0; // @[Debug.scala:1575:39] wire _immBits_WIRE_19 = 1'h0; // @[Debug.scala:1575:39] wire _immBits_WIRE_20 = 1'h0; // @[Debug.scala:1575:39] wire immBits_0 = 1'h0; // @[Debug.scala:1575:31] wire immBits_1 = 1'h0; // @[Debug.scala:1575:31] wire immBits_2 = 1'h0; // @[Debug.scala:1575:31] wire immBits_6 = 1'h0; // @[Debug.scala:1575:31] wire immBits_7 = 1'h0; // @[Debug.scala:1575:31] wire immBits_8 = 1'h0; // @[Debug.scala:1575:31] wire immBits_9 = 1'h0; // @[Debug.scala:1575:31] wire immBits_10 = 1'h0; // @[Debug.scala:1575:31] wire immBits_11 = 1'h0; // @[Debug.scala:1575:31] wire immBits_12 = 1'h0; // @[Debug.scala:1575:31] wire immBits_13 = 1'h0; // @[Debug.scala:1575:31] wire immBits_14 = 1'h0; // @[Debug.scala:1575:31] wire immBits_15 = 1'h0; // @[Debug.scala:1575:31] wire immBits_16 = 1'h0; // @[Debug.scala:1575:31] wire immBits_17 = 1'h0; // @[Debug.scala:1575:31] wire immBits_18 = 1'h0; // @[Debug.scala:1575:31] wire immBits_19 = 1'h0; // @[Debug.scala:1575:31] wire immBits_20 = 1'h0; // @[Debug.scala:1575:31] wire _flags_WIRE_resume = 1'h0; // @[Debug.scala:1517:87] wire _flags_WIRE_go = 1'h0; // @[Debug.scala:1517:87] wire _flags_WIRE_1_resume = 1'h0; // @[Debug.scala:1517:87] wire _flags_WIRE_1_go = 1'h0; // @[Debug.scala:1517:87] wire _flags_WIRE_2_0_resume = 1'h0; // @[Debug.scala:1517:33] wire _flags_WIRE_2_0_go = 1'h0; // @[Debug.scala:1517:33] wire _flags_WIRE_2_1_resume = 1'h0; // @[Debug.scala:1517:33] wire _flags_WIRE_2_1_go = 1'h0; // @[Debug.scala:1517:33] wire flags_1_resume = 1'h0; // @[Debug.scala:1517:25] wire flags_1_go = 1'h0; // @[Debug.scala:1517:25] wire componentSel = 1'h0; // @[Debug.scala:1523:34] wire _out_rifireMux_T_307 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_311 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_315 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_319 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_323 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_327 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_331 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_335 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_339 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_343 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_347 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_351 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_355 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_359 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_363 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_367 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_371 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_375 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_379 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_383 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_387 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_399 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_403 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_407 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_411 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_415 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_419 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_423 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_427 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_431 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_435 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_439 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_443 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_447 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_451 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_455 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_459 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_463 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_467 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_471 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_475 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_479 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_483 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_487 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_491 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_495 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_499 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_503 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_507 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_511 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_515 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_519 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_523 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_527 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_531 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_535 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_539 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_543 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_547 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_551 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_555 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_559 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_563 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_567 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_571 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_575 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_579 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_583 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_587 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_591 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_595 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_599 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_603 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_607 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_611 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_615 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_619 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_623 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_627 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_631 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_635 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_639 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_643 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_651 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_655 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_659 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_663 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_667 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_671 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_727 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_731 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_735 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_739 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_743 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_747 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_751 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_755 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_759 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_763 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_767 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_771 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1285 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wifireMux_T_309 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_313 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_317 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_321 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_325 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_329 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_333 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_337 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_341 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_345 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_349 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_353 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_357 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_361 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_365 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_369 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_373 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_377 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_381 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_385 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_389 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_401 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_405 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_409 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_413 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_417 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_421 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_425 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_429 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_433 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_437 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_441 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_445 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_449 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_453 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_457 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_461 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_465 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_469 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_473 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_477 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_481 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_485 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_489 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_493 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_497 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_501 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_505 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_509 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_513 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_517 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_521 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_525 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_529 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_533 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_537 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_541 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_545 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_549 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_553 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_557 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_561 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_565 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_569 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_573 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_577 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_581 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_585 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_589 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_593 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_597 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_601 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_605 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_609 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_613 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_617 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_621 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_625 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_629 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_633 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_637 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_641 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_645 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_653 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_657 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_661 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_665 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_669 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_673 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_729 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_733 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_737 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_741 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_745 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_749 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_753 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_757 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_761 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_765 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_769 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_773 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1287 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_rofireMux_T_307 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_311 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_315 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_319 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_323 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_327 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_331 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_335 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_339 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_343 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_347 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_351 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_355 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_359 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_363 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_367 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_371 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_375 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_379 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_383 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_387 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_399 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_403 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_407 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_411 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_415 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_419 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_423 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_427 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_431 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_435 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_439 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_443 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_447 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_451 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_455 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_459 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_463 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_467 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_471 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_475 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_479 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_483 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_487 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_491 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_495 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_499 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_503 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_507 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_511 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_515 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_519 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_523 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_527 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_531 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_535 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_539 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_543 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_547 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_551 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_555 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_559 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_563 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_567 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_571 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_575 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_579 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_583 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_587 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_591 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_595 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_599 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_603 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_607 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_611 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_615 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_619 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_623 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_627 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_631 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_635 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_639 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_643 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_651 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_655 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_659 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_663 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_667 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_671 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_727 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_731 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_735 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_739 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_743 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_747 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_751 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_755 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_759 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_763 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_767 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_771 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1285 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wofireMux_T_309 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_313 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_317 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_321 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_325 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_329 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_333 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_337 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_341 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_345 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_349 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_353 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_357 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_361 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_365 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_369 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_373 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_377 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_381 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_385 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_389 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_401 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_405 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_409 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_413 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_417 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_421 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_425 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_429 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_433 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_437 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_441 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_445 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_449 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_453 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_457 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_461 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_465 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_469 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_473 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_477 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_481 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_485 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_489 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_493 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_497 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_501 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_505 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_509 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_513 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_517 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_521 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_525 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_529 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_533 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_537 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_541 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_545 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_549 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_553 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_557 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_561 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_565 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_569 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_573 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_577 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_581 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_585 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_589 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_593 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_597 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_601 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_605 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_609 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_613 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_617 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_621 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_625 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_629 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_633 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_637 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_641 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_645 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_653 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_657 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_661 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_665 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_669 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_673 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_729 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_733 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_737 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_741 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_745 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_749 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_753 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_757 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_761 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_765 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_769 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_773 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1287 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T_5 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T_7 = 1'h0; // @[MuxLiteral.scala:49:17] wire tlNodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17] wire tlNodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17] wire tlNodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17] wire [63:0] autoIncrementedAddr_hi = 64'h0; // @[SBA.scala:111:31] wire [63:0] sb2tlOpt_io_addrIn_hi = 64'h0; // @[SBA.scala:132:14] wire [63:0] sb2tlOpt_io_addrIn_hi_1 = 64'h0; // @[SBA.scala:133:10] wire [63:0] sb2tlOpt_io_dataIn_hi = 64'h0; // @[SBA.scala:175:59] wire [63:0] sb2tlOpt_io_dataIn_hi_1 = 64'h0; // @[SBA.scala:175:85] wire [63:0] _out_out_bits_data_WIRE_3_11 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_12 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_13 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_14 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_15 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_16 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_17 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_18 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_19 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_20 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_21 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_22 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_23 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_24 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_25 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_26 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_27 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_28 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_29 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_30 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_31 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_32 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_33 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_34 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_35 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_36 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_37 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_38 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_39 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_40 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_41 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_42 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_43 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_44 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_45 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_46 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_47 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_48 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_49 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_50 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_51 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_52 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_53 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_54 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_55 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_56 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_57 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_58 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_59 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_60 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_61 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_62 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_63 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_64 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_65 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_66 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_67 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_68 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_69 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_70 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_71 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_72 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_73 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_74 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_75 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_76 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_77 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_78 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_79 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_80 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_81 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_82 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_83 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_84 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_85 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_86 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_87 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_88 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_89 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_90 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_91 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_92 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_93 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_94 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_95 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_97 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_98 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_99 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_100 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_101 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_102 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_116 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_117 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_118 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_119 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_120 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_121 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_122 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_123 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_124 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_125 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_126 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_127 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] tlNodeIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17] wire [2:0] auto_sb2tlOpt_out_a_bits_param = 3'h0; // @[Debug.scala:790:9] wire [2:0] _ABSTRACTCSReset_WIRE_reserved0 = 3'h0; // @[Debug.scala:1179:48] wire [2:0] _ABSTRACTCSReset_WIRE_cmderr = 3'h0; // @[Debug.scala:1179:48] wire [2:0] ABSTRACTCSReset_reserved0 = 3'h0; // @[Debug.scala:1179:35] wire [2:0] ABSTRACTCSReset_cmderr = 3'h0; // @[Debug.scala:1179:35] wire [2:0] _ABSTRACTCSWrData_WIRE_reserved0 = 3'h0; // @[Debug.scala:1184:52] wire [2:0] _ABSTRACTCSWrData_WIRE_cmderr = 3'h0; // @[Debug.scala:1184:52] wire [2:0] ABSTRACTCSWrData_reserved0 = 3'h0; // @[Debug.scala:1184:39] wire [2:0] ABSTRACTCSRdData_reserved0 = 3'h0; // @[Debug.scala:1185:39] wire [2:0] _SBCSFieldsRegReset_WIRE_sbversion = 3'h0; // @[SBA.scala:49:51] wire [2:0] _SBCSFieldsRegReset_WIRE_sbaccess = 3'h0; // @[SBA.scala:49:51] wire [2:0] _SBCSFieldsRegReset_WIRE_sberror = 3'h0; // @[SBA.scala:49:51] wire [2:0] SBCSFieldsRegReset_sberror = 3'h0; // @[SBA.scala:49:38] wire [2:0] _SBCSRdData_WIRE_sbversion = 3'h0; // @[SBA.scala:60:51] wire [2:0] _SBCSRdData_WIRE_sbaccess = 3'h0; // @[SBA.scala:60:51] wire [2:0] _SBCSRdData_WIRE_sberror = 3'h0; // @[SBA.scala:60:51] wire [2:0] _SBCSWrData_WIRE_sbversion = 3'h0; // @[SBA.scala:63:61] wire [2:0] _SBCSWrData_WIRE_sbaccess = 3'h0; // @[SBA.scala:63:61] wire [2:0] _SBCSWrData_WIRE_sberror = 3'h0; // @[SBA.scala:63:61] wire [2:0] _SBCSWrData_T_6 = 3'h0; // @[SBA.scala:63:61] wire [2:0] _SBCSWrData_T_9 = 3'h0; // @[SBA.scala:63:61] wire [2:0] _SBCSWrData_T_14 = 3'h0; // @[SBA.scala:63:61] wire [2:0] SBCSWrData_sbversion = 3'h0; // @[SBA.scala:63:38] wire [2:0] _SBCSRdData_WIRE_1_sbversion = 3'h0; // @[SBA.scala:243:33] wire [2:0] _SBCSRdData_WIRE_1_sbaccess = 3'h0; // @[SBA.scala:243:33] wire [2:0] _SBCSRdData_WIRE_1_sberror = 3'h0; // @[SBA.scala:243:33] wire [2:0] dmiNodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17] wire [2:0] jalAbstract_imm0_hi_hi = 3'h0; // @[package.scala:45:27] wire [2:0] jalAbstract_imm1_lo_hi = 3'h0; // @[package.scala:45:27] wire [2:0] jalAbstract_imm1_hi_hi = 3'h0; // @[package.scala:45:27] wire [2:0] nop_funct3 = 3'h0; // @[Debug.scala:1623:19] wire [2:0] _nop_WIRE_funct3 = 3'h0; // @[Debug.scala:1624:46] wire [2:0] isa_funct3 = 3'h0; // @[Debug.scala:1629:19] wire [2:0] _isa_WIRE_funct3 = 3'h0; // @[Debug.scala:1630:47] wire [2:0] tlNodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17] wire auto_sb2tlOpt_out_a_bits_mask = 1'h1; // @[Debug.scala:790:9] wire io_innerCtrl_ready = 1'h1; // @[Debug.scala:790:9] wire hamaskFull_0 = 1'h1; // @[Debug.scala:903:30] wire DMSTATUSRdData_authenticated = 1'h1; // @[Debug.scala:978:34] wire DMSTATUSRdData_hasresethaltreq = 1'h1; // @[Debug.scala:978:34] wire _DMSTATUSRdData_anyhalted_T = 1'h1; // @[package.scala:79:37] wire _DMSTATUSRdData_anyrunning_T = 1'h1; // @[package.scala:79:37] wire _DMSTATUSRdData_allhalted_T = 1'h1; // @[package.scala:79:37] wire _DMSTATUSRdData_allrunning_T = 1'h1; // @[package.scala:79:37] wire SBCSFieldsRegReset_sbaccess64 = 1'h1; // @[SBA.scala:49:38] wire SBCSFieldsRegReset_sbaccess32 = 1'h1; // @[SBA.scala:49:38] wire SBCSFieldsRegReset_sbaccess16 = 1'h1; // @[SBA.scala:49:38] wire SBCSFieldsRegReset_sbaccess8 = 1'h1; // @[SBA.scala:49:38] wire SBCSRdData_sbaccess64 = 1'h1; // @[SBA.scala:60:38] wire SBCSRdData_sbaccess32 = 1'h1; // @[SBA.scala:60:38] wire SBCSRdData_sbaccess16 = 1'h1; // @[SBA.scala:60:38] wire SBCSRdData_sbaccess8 = 1'h1; // @[SBA.scala:60:38] wire _sbAccessError_T_16 = 1'h1; // @[SBA.scala:186:88] wire _out_T_438 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_T_439 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_prepend_T_24 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_4 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_21 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_25 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_29 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_7 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_33 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_8 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_37 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_41 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_45 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_11 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_49 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_12 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_53 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_57 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_61 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_15 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_65 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_16 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_69 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_73 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_77 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_19 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_81 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_20 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_85 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_21 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_89 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_22 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_93 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_23 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_97 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_24 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_101 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_25 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_105 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_26 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_109 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_27 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_113 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_28 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_117 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_29 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_121 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_30 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_125 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_31 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_129 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_32 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_133 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_33 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_137 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_34 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_141 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_35 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_145 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_36 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_149 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_37 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_153 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_38 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_157 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_39 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_161 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_40 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_165 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_41 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_169 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_42 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_173 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_43 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_177 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_44 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_181 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_45 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_185 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_46 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_189 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_47 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_193 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_48 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_197 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_49 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_201 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_50 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_205 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_51 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_209 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_52 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_213 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_53 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_217 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_54 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_221 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_55 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_225 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_56 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_229 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_57 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_233 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_58 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_237 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_59 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_241 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_60 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_245 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_61 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_249 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_62 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_253 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_63 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_257 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_4 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_5 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_6 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_7 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_8 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_9 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_10 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_11 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_12 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_13 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_14 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_15 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_16 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_17 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_18 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_19 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_20 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_21 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_22 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_23 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_24 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_25 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_26 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_27 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_28 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_29 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_30 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_31 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_32 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_33 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_34 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_35 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_36 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_37 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_38 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_39 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_40 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_41 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_42 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_43 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_44 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_45 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_46 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_47 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_48 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_49 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_50 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_51 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_52 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_53 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_54 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_55 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_56 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_57 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_58 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_59 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_60 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_61 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_62 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_63 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_4 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_22 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_26 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_30 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_7 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_34 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_8 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_38 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_42 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_46 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_11 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_50 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_12 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_54 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_58 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_62 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_15 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_66 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_16 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_70 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_74 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_78 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_19 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_82 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_20 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_86 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_21 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_90 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_22 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_94 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_23 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_98 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_24 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_102 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_25 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_106 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_26 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_110 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_27 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_114 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_28 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_118 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_29 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_122 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_30 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_126 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_31 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_130 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_32 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_134 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_33 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_138 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_34 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_142 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_35 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_146 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_36 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_150 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_37 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_154 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_38 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_158 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_39 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_162 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_40 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_166 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_41 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_170 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_42 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_174 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_43 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_178 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_44 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_182 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_45 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_186 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_46 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_190 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_47 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_194 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_48 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_198 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_49 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_202 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_50 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_206 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_51 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_210 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_52 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_214 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_53 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_218 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_54 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_222 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_55 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_226 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_56 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_230 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_57 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_234 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_58 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_238 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_59 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_242 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_60 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_246 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_61 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_250 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_62 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_254 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_63 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_258 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_4 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_5 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_6 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_7 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_8 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_9 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_10 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_11 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_12 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_13 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_14 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_15 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_16 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_17 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_18 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_19 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_20 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_21 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_22 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_23 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_24 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_25 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_26 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_27 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_28 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_29 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_30 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_31 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_32 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_33 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_34 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_35 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_36 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_37 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_38 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_39 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_40 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_41 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_42 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_43 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_44 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_45 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_46 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_47 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_48 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_49 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_50 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_51 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_52 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_53 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_54 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_55 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_56 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_57 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_58 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_59 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_60 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_61 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_62 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_63 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_4 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_21 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_25 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_29 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_7 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_33 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_8 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_37 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_41 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_45 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_11 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_49 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_12 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_53 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_57 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_61 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_15 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_65 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_16 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_69 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_73 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_77 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_19 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_81 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_20 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_85 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_21 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_89 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_22 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_93 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_23 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_97 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_24 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_101 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_25 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_105 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_26 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_109 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_27 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_113 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_28 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_117 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_29 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_121 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_30 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_125 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_31 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_129 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_32 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_133 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_33 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_137 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_34 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_141 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_35 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_145 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_36 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_149 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_37 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_153 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_38 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_157 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_39 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_161 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_40 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_165 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_41 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_169 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_42 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_173 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_43 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_177 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_44 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_181 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_45 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_185 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_46 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_189 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_47 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_193 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_48 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_197 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_49 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_201 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_50 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_205 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_51 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_209 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_52 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_213 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_53 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_217 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_54 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_221 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_55 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_225 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_56 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_229 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_57 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_233 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_58 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_237 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_59 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_241 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_60 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_245 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_61 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_249 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_62 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_253 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_63 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_257 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_4 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_5 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_6 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_7 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_8 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_9 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_10 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_11 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_12 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_13 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_14 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_15 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_16 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_17 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_18 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_19 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_20 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_21 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_22 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_23 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_24 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_25 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_26 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_27 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_28 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_29 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_30 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_31 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_32 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_33 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_34 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_35 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_36 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_37 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_38 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_39 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_40 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_41 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_42 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_43 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_44 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_45 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_46 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_47 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_48 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_49 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_50 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_51 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_52 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_53 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_54 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_55 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_56 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_57 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_58 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_59 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_60 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_61 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_62 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_63 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_4 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_22 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_26 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_30 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_7 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_34 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_8 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_38 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_42 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_46 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_11 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_50 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_12 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_54 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_58 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_62 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_15 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_66 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_16 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_70 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_74 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_78 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_19 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_82 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_20 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_86 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_21 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_90 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_22 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_94 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_23 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_98 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_24 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_102 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_25 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_106 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_26 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_110 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_27 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_114 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_28 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_118 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_29 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_122 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_30 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_126 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_31 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_130 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_32 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_134 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_33 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_138 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_34 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_142 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_35 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_146 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_36 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_150 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_37 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_154 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_38 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_158 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_39 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_162 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_40 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_166 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_41 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_170 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_42 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_174 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_43 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_178 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_44 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_182 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_45 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_186 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_46 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_190 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_47 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_194 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_48 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_198 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_49 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_202 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_50 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_206 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_51 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_210 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_52 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_214 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_53 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_218 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_54 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_222 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_55 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_226 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_56 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_230 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_57 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_234 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_58 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_238 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_59 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_242 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_60 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_246 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_61 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_250 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_62 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_254 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_63 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_258 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_4 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_5 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_6 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_7 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_8 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_9 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_10 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_11 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_12 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_13 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_14 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_15 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_16 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_17 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_18 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_19 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_20 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_21 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_22 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_23 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_24 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_25 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_26 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_27 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_28 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_29 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_30 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_31 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_32 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_33 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_34 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_35 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_36 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_37 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_38 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_39 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_40 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_41 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_42 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_43 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_44 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_45 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_46 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_47 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_48 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_49 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_50 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_51 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_52 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_53 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_54 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_55 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_56 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_57 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_58 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_59 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_60 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_61 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_62 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_63 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_iready = 1'h1; // @[RegisterRouter.scala:87:24] wire out_oready = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_12 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_13 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_14 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_15 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_16 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_18 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_20 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_21 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_25 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_26 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_27 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_28 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_29 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_30 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_31 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_48 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_49 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_50 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_51 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_52 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_53 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_54 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_55 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_58 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_59 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_62 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_63 = 1'h1; // @[MuxLiteral.scala:49:48] wire _immBits_T_3 = 1'h1; // @[Debug.scala:1575:48] wire _immBits_T_4 = 1'h1; // @[Debug.scala:1575:48] wire _immBits_T_5 = 1'h1; // @[Debug.scala:1575:48] wire _immBits_WIRE_3 = 1'h1; // @[Debug.scala:1575:39] wire _immBits_WIRE_4 = 1'h1; // @[Debug.scala:1575:39] wire _immBits_WIRE_5 = 1'h1; // @[Debug.scala:1575:39] wire immBits_3 = 1'h1; // @[Debug.scala:1575:31] wire immBits_4 = 1'h1; // @[Debug.scala:1575:31] wire immBits_5 = 1'h1; // @[Debug.scala:1575:31] wire out_rifireMux_out_64 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_264 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_65 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_268 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_66 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_272 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_67 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_276 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_68 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_280 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_69 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_284 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_70 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_288 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_71 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_292 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_72 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_296 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_73 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_300 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_74 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_304 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_75 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_308 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_76 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_312 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_77 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_316 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_78 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_320 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_79 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_324 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_80 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_328 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_81 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_332 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_82 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_336 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_83 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_340 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_84 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_344 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_85 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_348 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_86 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_352 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_87 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_356 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_88 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_360 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_89 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_364 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_90 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_368 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_91 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_372 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_92 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_376 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_93 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_380 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_94 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_384 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_95 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_388 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_96 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_392 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_97 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_396 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_98 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_400 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_99 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_404 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_100 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_408 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_101 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_412 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_102 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_416 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_103 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_420 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_104 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_424 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_105 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_428 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_106 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_432 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_107 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_436 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_108 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_440 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_109 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_444 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_110 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_448 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_111 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_452 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_112 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_456 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_113 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_460 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_114 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_464 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_115 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_468 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_116 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_472 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_117 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_476 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_118 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_480 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_119 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_484 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_120 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_488 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_121 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_492 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_122 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_496 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_123 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_500 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_124 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_504 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_125 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_508 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_126 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_512 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_127 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_516 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_128 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_520 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_129 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_524 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_130 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_528 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_131 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_532 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_132 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_536 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_133 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_540 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_134 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_544 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_135 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_548 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_136 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_552 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_137 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_556 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_138 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_560 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_139 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_564 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_140 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_568 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_141 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_572 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_142 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_576 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_143 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_580 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_144 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_584 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_145 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_588 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_146 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_592 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_147 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_596 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_148 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_600 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_149 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_604 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_150 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_608 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_151 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_612 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_152 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_616 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_153 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_620 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_154 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_624 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_155 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_628 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_156 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_632 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_157 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_636 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_158 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_640 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_159 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_644 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_160 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_648 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_161 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_652 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_162 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_656 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_163 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_660 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_164 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_664 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_165 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_668 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_166 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_672 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_167 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_676 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_168 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_680 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_169 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_684 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_170 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_688 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_171 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_692 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_172 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_696 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_173 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_700 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_174 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_704 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_175 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_708 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_176 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_712 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_177 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_716 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_178 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_720 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_179 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_724 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_180 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_728 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_181 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_732 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_182 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_736 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_183 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_740 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_184 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_744 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_185 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_748 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_186 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_752 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_187 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_756 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_188 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_760 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_189 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_764 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_190 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_768 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_191 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_772 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_192 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_776 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_193 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_780 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_194 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_784 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_195 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_788 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_196 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_792 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_197 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_796 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_198 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_800 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_199 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_804 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_200 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_808 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_201 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_812 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_202 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_816 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_203 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_820 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_204 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_824 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_205 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_828 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_206 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_832 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_207 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_836 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_208 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_840 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_209 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_844 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_210 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_848 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_211 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_852 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_212 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_856 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_213 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_860 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_214 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_864 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_215 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_868 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_216 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_872 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_217 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_876 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_218 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_880 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_219 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_884 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_220 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_888 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_221 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_892 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_222 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_896 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_223 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_900 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_224 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_904 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_225 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_908 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_226 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_912 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_227 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_916 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_228 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_920 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_229 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_924 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_230 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_928 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_231 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_932 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_232 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_936 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_233 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_940 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_234 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_944 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_235 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_948 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_236 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_952 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_237 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_956 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_238 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_960 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_239 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_964 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_240 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_968 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_241 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_972 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_242 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_976 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_243 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_980 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_244 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_984 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_245 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_988 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_246 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_992 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_247 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_996 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_248 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1000 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_249 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1004 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_250 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1008 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_251 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1012 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_252 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1016 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_253 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1020 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_254 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1024 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_255 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1028 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_256 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1032 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_257 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1036 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_258 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1040 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_259 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1044 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_260 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1048 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_261 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1052 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_262 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1056 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_263 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1060 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_264 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1064 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_265 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1068 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_266 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1072 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_267 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1076 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_268 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1080 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_269 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1084 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_270 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1088 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_271 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1092 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_272 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1096 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_273 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1100 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_274 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1104 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_275 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1108 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_276 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1112 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_277 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1116 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_278 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1120 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_279 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1124 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_280 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1128 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_281 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1132 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_282 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1136 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_283 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1140 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_284 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1144 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_285 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1148 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_286 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1152 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_287 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1156 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_288 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1160 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_289 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1164 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_290 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1168 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_291 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1172 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_292 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1176 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_293 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1180 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_294 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1184 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_295 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1188 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_296 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1192 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_297 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1196 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_298 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1200 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_299 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1204 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_300 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1208 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_301 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1212 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_302 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1216 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_303 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1220 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_304 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1224 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_305 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1228 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_306 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1232 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_307 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1236 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_308 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1240 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_309 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1244 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_310 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1248 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_311 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1252 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_312 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1256 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_313 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1260 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_314 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1264 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_315 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1268 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_316 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1272 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_317 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1276 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_318 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1280 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_319 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1284 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_WIRE_1_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_4 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_5 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_6 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_7 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_8 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_9 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_10 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_11 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_12 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_13 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_14 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_15 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_16 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_17 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_18 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_19 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_20 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_21 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_22 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_23 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_24 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_25 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_26 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_27 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_28 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_29 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_30 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_31 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_32 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_33 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_34 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_35 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_36 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_37 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_38 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_39 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_40 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_41 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_42 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_43 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_44 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_45 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_46 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_47 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_48 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_49 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_50 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_51 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_52 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_53 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_54 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_55 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_56 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_57 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_58 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_59 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_60 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_61 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_62 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_63 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_64 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_65 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_66 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_67 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_68 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_69 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_70 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_71 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_72 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_73 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_74 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_75 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_76 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_77 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_78 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_79 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_80 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_81 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_82 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_83 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_84 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_85 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_86 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_87 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_88 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_89 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_90 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_91 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_92 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_93 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_94 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_95 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_96 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_97 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_98 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_99 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_100 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_101 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_102 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_103 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_104 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_105 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_106 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_107 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_108 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_109 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_110 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_111 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_112 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_113 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_114 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_115 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_116 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_117 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_118 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_119 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_120 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_121 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_122 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_123 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_124 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_125 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_126 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_127 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_128 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_129 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_130 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_131 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_132 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_133 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_134 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_135 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_136 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_137 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_138 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_139 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_140 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_141 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_142 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_143 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_144 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_145 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_146 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_147 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_148 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_149 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_150 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_151 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_152 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_153 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_154 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_155 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_156 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_157 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_158 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_159 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_160 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_161 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_162 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_163 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_164 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_165 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_166 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_167 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_168 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_169 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_170 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_171 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_172 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_173 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_174 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_175 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_176 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_177 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_178 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_179 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_180 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_181 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_182 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_183 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_184 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_185 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_186 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_187 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_188 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_189 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_190 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_191 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_192 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_193 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_194 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_195 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_196 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_197 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_198 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_199 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_200 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_201 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_202 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_203 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_204 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_205 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_206 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_207 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_208 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_209 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_210 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_211 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_212 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_213 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_214 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_215 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_216 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_217 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_218 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_219 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_220 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_221 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_222 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_223 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_224 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_225 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_226 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_227 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_228 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_229 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_230 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_231 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_232 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_233 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_234 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_235 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_236 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_237 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_238 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_239 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_240 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_241 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_242 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_243 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_244 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_245 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_246 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_247 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_248 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_249 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_250 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_251 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_252 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_253 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_254 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_255 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rifireMux_1 = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wifireMux_out_64 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_266 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_65 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_270 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_66 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_274 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_67 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_278 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_68 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_282 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_69 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_286 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_70 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_290 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_71 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_294 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_72 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_298 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_73 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_302 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_74 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_306 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_75 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_310 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_76 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_314 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_77 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_318 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_78 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_322 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_79 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_326 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_80 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_330 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_81 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_334 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_82 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_338 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_83 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_342 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_84 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_346 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_85 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_350 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_86 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_354 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_87 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_358 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_88 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_362 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_89 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_366 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_90 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_370 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_91 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_374 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_92 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_378 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_93 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_382 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_94 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_386 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_95 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_390 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_96 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_394 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_97 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_398 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_98 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_402 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_99 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_406 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_100 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_410 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_101 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_414 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_102 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_418 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_103 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_422 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_104 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_426 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_105 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_430 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_106 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_434 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_107 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_438 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_108 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_442 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_109 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_446 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_110 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_450 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_111 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_454 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_112 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_458 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_113 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_462 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_114 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_466 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_115 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_470 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_116 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_474 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_117 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_478 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_118 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_482 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_119 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_486 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_120 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_490 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_121 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_494 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_122 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_498 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_123 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_502 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_124 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_506 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_125 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_510 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_126 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_514 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_127 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_518 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_128 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_522 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_129 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_526 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_130 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_530 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_131 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_534 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_132 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_538 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_133 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_542 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_134 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_546 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_135 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_550 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_136 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_554 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_137 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_558 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_138 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_562 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_139 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_566 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_140 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_570 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_141 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_574 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_142 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_578 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_143 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_582 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_144 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_586 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_145 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_590 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_146 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_594 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_147 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_598 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_148 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_602 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_149 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_606 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_150 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_610 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_151 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_614 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_152 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_618 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_153 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_622 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_154 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_626 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_155 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_630 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_156 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_634 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_157 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_638 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_158 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_642 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_159 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_646 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_160 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_650 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_161 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_654 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_162 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_658 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_163 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_662 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_164 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_666 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_165 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_670 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_166 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_674 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_167 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_678 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_168 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_682 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_169 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_686 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_170 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_690 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_171 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_694 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_172 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_698 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_173 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_702 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_174 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_706 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_175 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_710 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_176 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_714 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_177 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_718 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_178 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_722 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_179 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_726 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_180 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_730 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_181 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_734 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_182 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_738 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_183 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_742 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_184 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_746 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_185 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_750 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_186 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_754 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_187 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_758 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_188 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_762 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_189 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_766 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_190 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_770 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_191 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_774 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_192 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_778 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_193 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_782 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_194 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_786 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_195 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_790 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_196 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_794 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_197 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_798 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_198 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_802 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_199 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_806 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_200 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_810 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_201 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_814 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_202 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_818 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_203 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_822 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_204 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_826 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_205 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_830 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_206 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_834 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_207 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_838 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_208 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_842 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_209 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_846 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_210 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_850 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_211 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_854 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_212 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_858 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_213 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_862 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_214 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_866 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_215 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_870 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_216 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_874 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_217 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_878 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_218 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_882 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_219 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_886 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_220 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_890 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_221 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_894 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_222 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_898 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_223 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_902 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_224 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_906 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_225 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_910 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_226 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_914 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_227 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_918 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_228 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_922 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_229 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_926 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_230 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_930 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_231 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_934 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_232 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_938 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_233 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_942 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_234 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_946 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_235 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_950 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_236 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_954 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_237 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_958 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_238 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_962 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_239 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_966 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_240 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_970 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_241 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_974 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_242 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_978 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_243 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_982 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_244 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_986 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_245 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_990 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_246 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_994 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_247 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_998 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_248 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1002 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_249 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1006 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_250 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1010 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_251 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1014 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_252 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1018 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_253 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1022 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_254 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1026 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_255 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1030 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_256 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1034 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_257 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1038 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_258 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1042 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_259 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1046 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_260 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1050 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_261 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1054 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_262 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1058 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_263 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1062 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_264 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1066 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_265 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1070 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_266 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1074 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_267 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1078 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_268 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1082 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_269 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1086 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_270 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1090 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_271 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1094 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_272 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1098 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_273 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1102 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_274 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1106 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_275 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1110 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_276 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1114 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_277 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1118 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_278 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1122 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_279 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1126 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_280 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1130 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_281 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1134 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_282 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1138 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_283 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1142 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_284 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1146 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_285 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1150 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_286 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1154 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_287 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1158 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_288 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1162 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_289 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1166 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_290 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1170 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_291 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1174 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_292 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1178 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_293 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1182 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_294 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1186 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_295 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1190 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_296 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1194 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_297 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1198 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_298 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1202 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_299 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1206 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_300 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1210 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_301 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1214 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_302 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1218 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_303 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1222 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_304 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1226 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_305 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1230 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_306 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1234 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_307 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1238 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_308 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1242 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_309 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1246 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_310 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1250 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_311 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1254 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_312 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1258 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_313 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1262 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_314 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1266 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_315 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1270 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_316 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1274 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_317 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1278 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_318 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1282 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_319 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1286 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_WIRE_1_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_4 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_5 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_6 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_7 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_8 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_9 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_10 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_11 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_12 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_13 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_14 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_15 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_16 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_17 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_18 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_19 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_20 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_21 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_22 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_23 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_24 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_25 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_26 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_27 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_28 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_29 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_30 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_31 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_32 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_33 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_34 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_35 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_36 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_37 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_38 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_39 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_40 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_41 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_42 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_43 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_44 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_45 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_46 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_47 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_48 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_49 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_50 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_51 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_52 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_53 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_54 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_55 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_56 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_57 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_58 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_59 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_60 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_61 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_62 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_63 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_64 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_65 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_66 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_67 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_68 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_69 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_70 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_71 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_72 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_73 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_74 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_75 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_76 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_77 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_78 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_79 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_80 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_81 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_82 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_83 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_84 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_85 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_86 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_87 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_88 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_89 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_90 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_91 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_92 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_93 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_94 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_95 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_96 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_97 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_98 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_99 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_100 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_101 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_102 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_103 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_104 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_105 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_106 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_107 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_108 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_109 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_110 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_111 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_112 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_113 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_114 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_115 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_116 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_117 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_118 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_119 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_120 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_121 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_122 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_123 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_124 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_125 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_126 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_127 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_128 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_129 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_130 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_131 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_132 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_133 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_134 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_135 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_136 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_137 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_138 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_139 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_140 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_141 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_142 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_143 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_144 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_145 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_146 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_147 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_148 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_149 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_150 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_151 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_152 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_153 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_154 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_155 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_156 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_157 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_158 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_159 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_160 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_161 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_162 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_163 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_164 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_165 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_166 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_167 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_168 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_169 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_170 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_171 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_172 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_173 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_174 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_175 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_176 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_177 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_178 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_179 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_180 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_181 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_182 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_183 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_184 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_185 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_186 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_187 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_188 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_189 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_190 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_191 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_192 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_193 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_194 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_195 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_196 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_197 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_198 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_199 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_200 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_201 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_202 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_203 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_204 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_205 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_206 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_207 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_208 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_209 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_210 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_211 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_212 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_213 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_214 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_215 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_216 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_217 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_218 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_219 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_220 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_221 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_222 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_223 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_224 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_225 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_226 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_227 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_228 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_229 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_230 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_231 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_232 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_233 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_234 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_235 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_236 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_237 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_238 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_239 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_240 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_241 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_242 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_243 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_244 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_245 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_246 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_247 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_248 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_249 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_250 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_251 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_252 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_253 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_254 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_255 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wifireMux_1 = 1'h1; // @[MuxLiteral.scala:49:10] wire out_rofireMux_out_64 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_264 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_65 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_268 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_66 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_272 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_67 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_276 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_68 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_280 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_69 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_284 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_70 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_288 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_71 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_292 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_72 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_296 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_73 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_300 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_74 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_304 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_75 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_308 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_76 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_312 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_77 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_316 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_78 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_320 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_79 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_324 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_80 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_328 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_81 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_332 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_82 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_336 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_83 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_340 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_84 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_344 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_85 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_348 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_86 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_352 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_87 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_356 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_88 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_360 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_89 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_364 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_90 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_368 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_91 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_372 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_92 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_376 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_93 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_380 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_94 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_384 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_95 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_388 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_96 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_392 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_97 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_396 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_98 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_400 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_99 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_404 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_100 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_408 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_101 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_412 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_102 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_416 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_103 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_420 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_104 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_424 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_105 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_428 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_106 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_432 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_107 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_436 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_108 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_440 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_109 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_444 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_110 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_448 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_111 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_452 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_112 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_456 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_113 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_460 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_114 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_464 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_115 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_468 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_116 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_472 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_117 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_476 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_118 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_480 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_119 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_484 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_120 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_488 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_121 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_492 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_122 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_496 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_123 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_500 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_124 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_504 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_125 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_508 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_126 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_512 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_127 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_516 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_128 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_520 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_129 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_524 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_130 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_528 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_131 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_532 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_132 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_536 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_133 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_540 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_134 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_544 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_135 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_548 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_136 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_552 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_137 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_556 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_138 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_560 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_139 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_564 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_140 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_568 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_141 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_572 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_142 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_576 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_143 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_580 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_144 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_584 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_145 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_588 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_146 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_592 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_147 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_596 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_148 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_600 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_149 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_604 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_150 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_608 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_151 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_612 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_152 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_616 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_153 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_620 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_154 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_624 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_155 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_628 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_156 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_632 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_157 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_636 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_158 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_640 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_159 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_644 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_160 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_648 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_161 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_652 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_162 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_656 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_163 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_660 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_164 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_664 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_165 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_668 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_166 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_672 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_167 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_676 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_168 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_680 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_169 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_684 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_170 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_688 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_171 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_692 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_172 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_696 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_173 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_700 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_174 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_704 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_175 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_708 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_176 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_712 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_177 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_716 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_178 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_720 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_179 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_724 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_180 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_728 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_181 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_732 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_182 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_736 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_183 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_740 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_184 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_744 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_185 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_748 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_186 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_752 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_187 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_756 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_188 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_760 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_189 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_764 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_190 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_768 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_191 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_772 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_192 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_776 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_193 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_780 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_194 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_784 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_195 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_788 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_196 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_792 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_197 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_796 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_198 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_800 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_199 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_804 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_200 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_808 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_201 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_812 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_202 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_816 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_203 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_820 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_204 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_824 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_205 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_828 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_206 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_832 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_207 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_836 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_208 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_840 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_209 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_844 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_210 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_848 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_211 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_852 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_212 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_856 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_213 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_860 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_214 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_864 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_215 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_868 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_216 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_872 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_217 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_876 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_218 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_880 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_219 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_884 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_220 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_888 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_221 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_892 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_222 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_896 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_223 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_900 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_224 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_904 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_225 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_908 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_226 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_912 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_227 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_916 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_228 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_920 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_229 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_924 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_230 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_928 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_231 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_932 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_232 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_936 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_233 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_940 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_234 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_944 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_235 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_948 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_236 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_952 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_237 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_956 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_238 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_960 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_239 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_964 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_240 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_968 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_241 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_972 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_242 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_976 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_243 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_980 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_244 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_984 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_245 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_988 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_246 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_992 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_247 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_996 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_248 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1000 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_249 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1004 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_250 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1008 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_251 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1012 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_252 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1016 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_253 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1020 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_254 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1024 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_255 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1028 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_256 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1032 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_257 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1036 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_258 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1040 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_259 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1044 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_260 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1048 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_261 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1052 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_262 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1056 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_263 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1060 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_264 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1064 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_265 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1068 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_266 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1072 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_267 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1076 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_268 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1080 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_269 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1084 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_270 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1088 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_271 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1092 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_272 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1096 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_273 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1100 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_274 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1104 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_275 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1108 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_276 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1112 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_277 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1116 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_278 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1120 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_279 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1124 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_280 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1128 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_281 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1132 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_282 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1136 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_283 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1140 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_284 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1144 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_285 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1148 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_286 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1152 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_287 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1156 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_288 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1160 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_289 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1164 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_290 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1168 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_291 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1172 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_292 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1176 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_293 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1180 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_294 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1184 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_295 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1188 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_296 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1192 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_297 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1196 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_298 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1200 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_299 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1204 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_300 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1208 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_301 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1212 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_302 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1216 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_303 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1220 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_304 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1224 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_305 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1228 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_306 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1232 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_307 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1236 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_308 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1240 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_309 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1244 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_310 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1248 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_311 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1252 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_312 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1256 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_313 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1260 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_314 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1264 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_315 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1268 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_316 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1272 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_317 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1276 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_318 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1280 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_319 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1284 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_WIRE_1_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_4 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_5 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_6 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_7 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_8 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_9 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_10 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_11 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_12 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_13 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_14 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_15 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_16 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_17 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_18 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_19 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_20 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_21 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_22 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_23 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_24 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_25 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_26 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_27 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_28 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_29 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_30 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_31 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_32 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_33 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_34 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_35 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_36 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_37 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_38 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_39 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_40 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_41 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_42 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_43 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_44 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_45 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_46 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_47 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_48 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_49 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_50 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_51 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_52 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_53 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_54 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_55 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_56 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_57 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_58 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_59 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_60 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_61 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_62 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_63 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_64 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_65 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_66 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_67 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_68 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_69 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_70 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_71 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_72 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_73 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_74 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_75 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_76 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_77 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_78 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_79 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_80 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_81 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_82 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_83 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_84 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_85 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_86 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_87 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_88 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_89 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_90 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_91 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_92 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_93 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_94 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_95 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_96 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_97 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_98 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_99 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_100 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_101 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_102 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_103 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_104 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_105 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_106 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_107 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_108 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_109 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_110 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_111 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_112 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_113 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_114 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_115 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_116 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_117 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_118 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_119 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_120 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_121 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_122 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_123 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_124 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_125 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_126 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_127 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_128 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_129 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_130 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_131 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_132 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_133 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_134 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_135 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_136 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_137 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_138 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_139 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_140 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_141 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_142 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_143 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_144 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_145 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_146 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_147 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_148 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_149 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_150 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_151 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_152 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_153 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_154 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_155 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_156 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_157 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_158 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_159 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_160 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_161 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_162 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_163 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_164 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_165 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_166 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_167 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_168 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_169 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_170 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_171 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_172 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_173 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_174 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_175 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_176 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_177 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_178 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_179 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_180 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_181 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_182 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_183 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_184 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_185 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_186 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_187 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_188 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_189 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_190 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_191 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_192 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_193 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_194 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_195 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_196 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_197 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_198 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_199 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_200 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_201 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_202 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_203 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_204 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_205 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_206 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_207 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_208 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_209 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_210 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_211 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_212 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_213 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_214 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_215 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_216 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_217 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_218 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_219 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_220 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_221 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_222 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_223 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_224 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_225 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_226 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_227 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_228 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_229 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_230 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_231 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_232 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_233 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_234 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_235 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_236 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_237 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_238 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_239 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_240 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_241 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_242 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_243 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_244 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_245 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_246 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_247 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_248 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_249 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_250 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_251 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_252 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_253 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_254 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_255 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rofireMux_1 = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wofireMux_out_64 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_266 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_65 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_270 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_66 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_274 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_67 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_278 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_68 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_282 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_69 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_286 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_70 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_290 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_71 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_294 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_72 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_298 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_73 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_302 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_74 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_306 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_75 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_310 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_76 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_314 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_77 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_318 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_78 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_322 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_79 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_326 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_80 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_330 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_81 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_334 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_82 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_338 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_83 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_342 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_84 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_346 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_85 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_350 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_86 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_354 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_87 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_358 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_88 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_362 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_89 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_366 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_90 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_370 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_91 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_374 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_92 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_378 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_93 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_382 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_94 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_386 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_95 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_390 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_96 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_394 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_97 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_398 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_98 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_402 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_99 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_406 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_100 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_410 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_101 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_414 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_102 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_418 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_103 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_422 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_104 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_426 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_105 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_430 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_106 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_434 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_107 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_438 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_108 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_442 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_109 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_446 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_110 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_450 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_111 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_454 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_112 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_458 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_113 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_462 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_114 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_466 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_115 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_470 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_116 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_474 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_117 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_478 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_118 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_482 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_119 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_486 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_120 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_490 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_121 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_494 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_122 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_498 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_123 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_502 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_124 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_506 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_125 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_510 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_126 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_514 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_127 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_518 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_128 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_522 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_129 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_526 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_130 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_530 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_131 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_534 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_132 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_538 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_133 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_542 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_134 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_546 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_135 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_550 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_136 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_554 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_137 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_558 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_138 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_562 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_139 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_566 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_140 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_570 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_141 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_574 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_142 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_578 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_143 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_582 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_144 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_586 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_145 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_590 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_146 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_594 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_147 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_598 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_148 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_602 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_149 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_606 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_150 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_610 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_151 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_614 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_152 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_618 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_153 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_622 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_154 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_626 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_155 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_630 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_156 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_634 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_157 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_638 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_158 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_642 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_159 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_646 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_160 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_650 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_161 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_654 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_162 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_658 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_163 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_662 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_164 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_666 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_165 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_670 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_166 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_674 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_167 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_678 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_168 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_682 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_169 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_686 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_170 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_690 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_171 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_694 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_172 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_698 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_173 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_702 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_174 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_706 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_175 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_710 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_176 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_714 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_177 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_718 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_178 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_722 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_179 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_726 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_180 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_730 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_181 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_734 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_182 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_738 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_183 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_742 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_184 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_746 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_185 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_750 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_186 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_754 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_187 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_758 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_188 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_762 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_189 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_766 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_190 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_770 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_191 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_774 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_192 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_778 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_193 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_782 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_194 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_786 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_195 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_790 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_196 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_794 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_197 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_798 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_198 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_802 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_199 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_806 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_200 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_810 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_201 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_814 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_202 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_818 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_203 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_822 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_204 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_826 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_205 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_830 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_206 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_834 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_207 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_838 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_208 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_842 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_209 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_846 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_210 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_850 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_211 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_854 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_212 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_858 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_213 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_862 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_214 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_866 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_215 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_870 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_216 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_874 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_217 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_878 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_218 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_882 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_219 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_886 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_220 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_890 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_221 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_894 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_222 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_898 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_223 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_902 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_224 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_906 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_225 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_910 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_226 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_914 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_227 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_918 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_228 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_922 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_229 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_926 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_230 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_930 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_231 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_934 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_232 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_938 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_233 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_942 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_234 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_946 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_235 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_950 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_236 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_954 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_237 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_958 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_238 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_962 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_239 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_966 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_240 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_970 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_241 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_974 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_242 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_978 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_243 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_982 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_244 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_986 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_245 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_990 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_246 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_994 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_247 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_998 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_248 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1002 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_249 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1006 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_250 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1010 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_251 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1014 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_252 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1018 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_253 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1022 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_254 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1026 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_255 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1030 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_256 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1034 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_257 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1038 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_258 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1042 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_259 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1046 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_260 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1050 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_261 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1054 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_262 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1058 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_263 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1062 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_264 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1066 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_265 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1070 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_266 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1074 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_267 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1078 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_268 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1082 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_269 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1086 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_270 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1090 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_271 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1094 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_272 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1098 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_273 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1102 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_274 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1106 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_275 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1110 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_276 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1114 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_277 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1118 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_278 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1122 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_279 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1126 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_280 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1130 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_281 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1134 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_282 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1138 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_283 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1142 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_284 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1146 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_285 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1150 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_286 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1154 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_287 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1158 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_288 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1162 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_289 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1166 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_290 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1170 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_291 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1174 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_292 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1178 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_293 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1182 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_294 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1186 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_295 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1190 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_296 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1194 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_297 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1198 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_298 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1202 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_299 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1206 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_300 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1210 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_301 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1214 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_302 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1218 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_303 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1222 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_304 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1226 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_305 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1230 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_306 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1234 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_307 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1238 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_308 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1242 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_309 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1246 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_310 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1250 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_311 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1254 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_312 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1258 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_313 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1262 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_314 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1266 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_315 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1270 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_316 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1274 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_317 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1278 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_318 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1282 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_319 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1286 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_1_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_4 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_5 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_6 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_7 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_8 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_9 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_10 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_11 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_12 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_13 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_14 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_15 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_16 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_17 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_18 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_19 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_20 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_21 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_22 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_23 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_24 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_25 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_26 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_27 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_28 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_29 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_30 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_31 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_32 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_33 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_34 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_35 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_36 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_37 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_38 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_39 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_40 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_41 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_42 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_43 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_44 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_45 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_46 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_47 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_48 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_49 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_50 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_51 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_52 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_53 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_54 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_55 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_56 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_57 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_58 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_59 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_60 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_61 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_62 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_63 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_64 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_65 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_66 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_67 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_68 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_69 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_70 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_71 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_72 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_73 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_74 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_75 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_76 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_77 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_78 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_79 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_80 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_81 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_82 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_83 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_84 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_85 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_86 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_87 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_88 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_89 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_90 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_91 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_92 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_93 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_94 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_95 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_96 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_97 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_98 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_99 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_100 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_101 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_102 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_103 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_104 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_105 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_106 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_107 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_108 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_109 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_110 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_111 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_112 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_113 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_114 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_115 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_116 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_117 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_118 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_119 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_120 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_121 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_122 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_123 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_124 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_125 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_126 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_127 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_128 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_129 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_130 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_131 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_132 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_133 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_134 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_135 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_136 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_137 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_138 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_139 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_140 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_141 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_142 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_143 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_144 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_145 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_146 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_147 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_148 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_149 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_150 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_151 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_152 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_153 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_154 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_155 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_156 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_157 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_158 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_159 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_160 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_161 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_162 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_163 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_164 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_165 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_166 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_167 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_168 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_169 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_170 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_171 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_172 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_173 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_174 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_175 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_176 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_177 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_178 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_179 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_180 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_181 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_182 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_183 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_184 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_185 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_186 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_187 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_188 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_189 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_190 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_191 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_192 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_193 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_194 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_195 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_196 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_197 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_198 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_199 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_200 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_201 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_202 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_203 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_204 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_205 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_206 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_207 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_208 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_209 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_210 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_211 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_212 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_213 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_214 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_215 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_216 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_217 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_218 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_219 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_220 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_221 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_222 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_223 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_224 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_225 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_226 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_227 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_228 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_229 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_230 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_231 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_232 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_233 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_234 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_235 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_236 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_237 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_238 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_239 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_240 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_241 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_242 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_243 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_244 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_245 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_246 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_247 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_248 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_249 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_250 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_251 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_252 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_253 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_254 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_255 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wofireMux_1 = 1'h1; // @[MuxLiteral.scala:49:10] wire out_iready_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_oready_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_2_11 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_12 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_13 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_14 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_15 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_16 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_17 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_18 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_19 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_20 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_21 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_22 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_23 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_24 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_25 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_26 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_27 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_28 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_29 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_30 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_31 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_34 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_35 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_36 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_37 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_38 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_39 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_40 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_41 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_42 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_43 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_44 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_45 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_46 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_47 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_48 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_49 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_50 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_51 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_52 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_53 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_54 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_55 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_56 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_57 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_58 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_59 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_60 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_61 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_62 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_63 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_64 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_65 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_66 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_67 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_68 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_69 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_70 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_71 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_72 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_73 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_74 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_75 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_76 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_77 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_78 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_79 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_80 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_81 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_82 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_83 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_84 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_85 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_86 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_87 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_88 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_89 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_90 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_91 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_92 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_93 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_94 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_95 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_97 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_98 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_99 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_100 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_101 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_102 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_116 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_117 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_118 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_119 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_120 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_121 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_122 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_123 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_124 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_125 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_126 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_127 = 1'h1; // @[MuxLiteral.scala:49:48] wire [31:0] SBCSWrDataVal = 32'h0; // @[SBA.scala:62:38] wire [31:0] _SBCSWrData_WIRE_1 = 32'h0; // @[SBA.scala:63:61] wire [31:0] _SBADDRESSWrData_WIRE_0 = 32'h0; // @[SBA.scala:106:46] wire [31:0] _SBADDRESSWrData_WIRE_1 = 32'h0; // @[SBA.scala:106:46] wire [31:0] _SBADDRESSWrData_WIRE_2 = 32'h0; // @[SBA.scala:106:46] wire [31:0] _SBADDRESSWrData_WIRE_3 = 32'h0; // @[SBA.scala:106:46] wire [31:0] SBADDRESSWrData_1 = 32'h0; // @[SBA.scala:106:38] wire [31:0] SBADDRESSWrData_2 = 32'h0; // @[SBA.scala:106:38] wire [31:0] SBADDRESSWrData_3 = 32'h0; // @[SBA.scala:106:38] wire [31:0] _SBDATARdData_WIRE_0 = 32'h0; // @[SBA.scala:145:43] wire [31:0] _SBDATARdData_WIRE_1 = 32'h0; // @[SBA.scala:145:43] wire [31:0] _SBDATARdData_WIRE_2 = 32'h0; // @[SBA.scala:145:43] wire [31:0] _SBDATARdData_WIRE_3 = 32'h0; // @[SBA.scala:145:43] wire [31:0] SBDATARdData_2 = 32'h0; // @[SBA.scala:145:35] wire [31:0] SBDATARdData_3 = 32'h0; // @[SBA.scala:145:35] wire [31:0] _SBDATAWrData_WIRE_0 = 32'h0; // @[SBA.scala:147:43] wire [31:0] _SBDATAWrData_WIRE_1 = 32'h0; // @[SBA.scala:147:43] wire [31:0] _SBDATAWrData_WIRE_2 = 32'h0; // @[SBA.scala:147:43] wire [31:0] _SBDATAWrData_WIRE_3 = 32'h0; // @[SBA.scala:147:43] wire [31:0] SBDATAWrData_2 = 32'h0; // @[SBA.scala:147:35] wire [31:0] SBDATAWrData_3 = 32'h0; // @[SBA.scala:147:35] wire [31:0] sb2tlOpt_io_dataIn_hi_lo = 32'h0; // @[SBA.scala:175:85] wire [31:0] sb2tlOpt_io_dataIn_hi_hi = 32'h0; // @[SBA.scala:175:85] wire [31:0] _out_out_bits_data_WIRE_1_1 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_2 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_3 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_12 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_13 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_14 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_15 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_16 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_18 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_20 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_21 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_25 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_26 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_27 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_28 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_29 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_30 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_31 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_48 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_49 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_50 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_51 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_52 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_53 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_54 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_55 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_58 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_59 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_62 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_63 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] dmiNodeIn_d_bits_d_data = 32'h0; // @[Edges.scala:792:17] wire [31:0] _out_prepend_T_420 = 32'h0; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_578 = 32'h0; // @[RegisterRouter.scala:87:24] wire [5:0] _SBCSFieldsRegReset_WIRE_reserved0 = 6'h0; // @[SBA.scala:49:51] wire [5:0] SBCSFieldsRegReset_reserved0 = 6'h0; // @[SBA.scala:49:38] wire [5:0] _SBCSRdData_WIRE_reserved0 = 6'h0; // @[SBA.scala:60:51] wire [5:0] SBCSRdData_reserved0 = 6'h0; // @[SBA.scala:60:38] wire [5:0] _SBCSWrData_WIRE_reserved0 = 6'h0; // @[SBA.scala:63:61] wire [5:0] _SBCSWrData_T_13 = 6'h0; // @[SBA.scala:63:61] wire [5:0] SBCSWrData_reserved0 = 6'h0; // @[SBA.scala:63:38] wire [5:0] _SBCSRdData_WIRE_1_reserved0 = 6'h0; // @[SBA.scala:243:33] wire [5:0] _flags_WIRE_reserved = 6'h0; // @[Debug.scala:1517:87] wire [5:0] _flags_WIRE_1_reserved = 6'h0; // @[Debug.scala:1517:87] wire [5:0] _flags_WIRE_2_0_reserved = 6'h0; // @[Debug.scala:1517:33] wire [5:0] _flags_WIRE_2_1_reserved = 6'h0; // @[Debug.scala:1517:33] wire [5:0] flags_0_reserved = 6'h0; // @[Debug.scala:1517:25] wire [5:0] flags_1_reserved = 6'h0; // @[Debug.scala:1517:25] wire [3:0] _DMSTATUSRdData_WIRE_version = 4'h0; // @[Debug.scala:978:47] wire [3:0] _DMCS2RdData_WIRE_exttrigger = 4'h0; // @[Debug.scala:1025:47] wire [3:0] DMCS2RdData_exttrigger = 4'h0; // @[Debug.scala:1025:34] wire [3:0] _DMCS2WrData_WIRE_exttrigger = 4'h0; // @[Debug.scala:1026:47] wire [3:0] DMCS2WrData_exttrigger = 4'h0; // @[Debug.scala:1026:34] wire [3:0] _ABSTRACTCSReset_WIRE_reserved3 = 4'h0; // @[Debug.scala:1179:48] wire [3:0] _ABSTRACTCSReset_WIRE_datacount = 4'h0; // @[Debug.scala:1179:48] wire [3:0] ABSTRACTCSReset_reserved3 = 4'h0; // @[Debug.scala:1179:35] wire [3:0] _ABSTRACTCSWrData_WIRE_reserved3 = 4'h0; // @[Debug.scala:1184:52] wire [3:0] _ABSTRACTCSWrData_WIRE_datacount = 4'h0; // @[Debug.scala:1184:52] wire [3:0] ABSTRACTCSWrData_reserved3 = 4'h0; // @[Debug.scala:1184:39] wire [3:0] ABSTRACTCSWrData_datacount = 4'h0; // @[Debug.scala:1184:39] wire [3:0] ABSTRACTCSRdData_reserved3 = 4'h0; // @[Debug.scala:1185:39] wire [3:0] _ABSTRACTAUTOReset_WIRE_reserved0 = 4'h0; // @[Debug.scala:1234:54] wire [3:0] ABSTRACTAUTOReset_reserved0 = 4'h0; // @[Debug.scala:1234:41] wire [3:0] _ABSTRACTAUTOWrData_WIRE_reserved0 = 4'h0; // @[Debug.scala:1236:54] wire [3:0] ABSTRACTAUTOWrData_reserved0 = 4'h0; // @[Debug.scala:1236:41] wire [3:0] ABSTRACTAUTORdData_reserved0 = 4'h0; // @[Debug.scala:1237:41] wire [3:0] jalAbstract_imm2_lo = 4'h0; // @[package.scala:45:27] wire [3:0] jalAbstract_imm2_hi = 4'h0; // @[package.scala:45:27] wire [7:0] _out_T_1223 = 8'h8; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1224 = 8'h8; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_86 = 8'h8; // @[RegisterRouter.scala:87:24] wire [4:0] out_prepend_85 = 5'h8; // @[RegisterRouter.scala:87:24] wire [3:0] ABSTRACTCSReset_datacount = 4'h8; // @[Debug.scala:1179:35] wire [3:0] ABSTRACTCSRdData_datacount = 4'h8; // @[Debug.scala:1185:39] wire [3:0] _out_T_1214 = 4'h8; // @[RegisterRouter.scala:87:24] wire [3:0] _out_T_1215 = 4'h8; // @[RegisterRouter.scala:87:24] wire [3:0] _out_prepend_T_85 = 4'h8; // @[RegisterRouter.scala:87:24] wire [15:0] _ABSTRACTAUTOReset_WIRE_autoexecprogbuf = 16'h0; // @[Debug.scala:1234:54] wire [15:0] ABSTRACTAUTOReset_autoexecprogbuf = 16'h0; // @[Debug.scala:1234:41] wire [15:0] _ABSTRACTAUTOWrData_WIRE_autoexecprogbuf = 16'h0; // @[Debug.scala:1236:54] wire [15:0] sb2tlOpt_io_dataIn_hi_lo_lo = 16'h0; // @[SBA.scala:175:85] wire [15:0] sb2tlOpt_io_dataIn_hi_lo_hi = 16'h0; // @[SBA.scala:175:85] wire [15:0] sb2tlOpt_io_dataIn_hi_hi_lo = 16'h0; // @[SBA.scala:175:85] wire [15:0] sb2tlOpt_io_dataIn_hi_hi_hi = 16'h0; // @[SBA.scala:175:85] wire [95:0] _sb2tlOpt_io_addrIn_T = 96'h0; // @[SBA.scala:132:14] wire [2:0] SBCSFieldsRegReset_sbversion = 3'h1; // @[SBA.scala:49:38] wire [2:0] SBCSRdData_sbversion = 3'h1; // @[SBA.scala:60:38] wire [10:0] _ABSTRACTCSReset_WIRE_reserved1 = 11'h0; // @[Debug.scala:1179:48] wire [10:0] ABSTRACTCSReset_reserved1 = 11'h0; // @[Debug.scala:1179:35] wire [10:0] _ABSTRACTCSWrData_WIRE_reserved1 = 11'h0; // @[Debug.scala:1184:52] wire [10:0] ABSTRACTCSWrData_reserved1 = 11'h0; // @[Debug.scala:1184:39] wire [10:0] ABSTRACTCSRdData_reserved1 = 11'h0; // @[Debug.scala:1185:39] wire [4:0] ABSTRACTCSReset_progbufsize = 5'h10; // @[Debug.scala:1179:35] wire [4:0] ABSTRACTCSRdData_progbufsize = 5'h10; // @[Debug.scala:1185:39] wire [7:0] _COMMANDReset_WIRE_cmdtype = 8'h0; // @[Debug.scala:1276:45] wire [7:0] COMMANDReset_cmdtype = 8'h0; // @[Debug.scala:1276:32] wire [7:0] _jalAbstract_WIRE_imm2 = 8'h0; // @[Debug.scala:1497:66] wire [7:0] jalAbstract_imm2 = 8'h0; // @[Debug.scala:1497:32] wire [7:0] _jalAbstract_imm2_T = 8'h0; // @[package.scala:45:27] wire [6:0] SBCSFieldsRegReset_sbasize = 7'h20; // @[SBA.scala:49:38] wire [6:0] SBCSRdData_sbasize = 7'h20; // @[SBA.scala:60:38] wire [1:0] auto_tl_in_d_bits_param = 2'h0; // @[Debug.scala:790:9] wire [1:0] auto_dmi_in_d_bits_param = 2'h0; // @[Debug.scala:790:9] wire [1:0] dmiNodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] tlNodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] _DMSTATUSRdData_WIRE_reserved1 = 2'h0; // @[Debug.scala:978:47] wire [1:0] DMSTATUSRdData_reserved1 = 2'h0; // @[Debug.scala:978:34] wire [1:0] _haltedBitRegs_T_4 = 2'h0; // @[Debug.scala:1330:43] wire [1:0] _haltedBitRegs_T_6 = 2'h0; // @[Debug.scala:1330:69] wire [1:0] _resumeReqRegs_T_3 = 2'h0; // @[Debug.scala:1338:43] wire [1:0] _resumeReqRegs_T_5 = 2'h0; // @[Debug.scala:1338:69] wire [1:0] dmiNodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17] wire [1:0] jalAbstract_imm0_lo_lo = 2'h0; // @[package.scala:45:27] wire [1:0] jalAbstract_imm0_hi_lo = 2'h0; // @[package.scala:45:27] wire [1:0] jalAbstract_imm0_hi_hi_hi = 2'h0; // @[package.scala:45:27] wire [1:0] jalAbstract_imm1_lo_lo = 2'h0; // @[package.scala:45:27] wire [1:0] jalAbstract_imm1_lo_hi_hi = 2'h0; // @[package.scala:45:27] wire [1:0] jalAbstract_imm1_hi_lo = 2'h0; // @[package.scala:45:27] wire [1:0] jalAbstract_imm1_hi_hi_hi = 2'h0; // @[package.scala:45:27] wire [1:0] jalAbstract_imm2_lo_lo = 2'h0; // @[package.scala:45:27] wire [1:0] jalAbstract_imm2_lo_hi = 2'h0; // @[package.scala:45:27] wire [1:0] jalAbstract_imm2_hi_lo = 2'h0; // @[package.scala:45:27] wire [1:0] jalAbstract_imm2_hi_hi = 2'h0; // @[package.scala:45:27] wire [1:0] tlNodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17] wire [63:0] _out_out_bits_data_WIRE_3_96 = 64'h380006F; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_10 = 64'h100073; // @[MuxLiteral.scala:49:48] wire [63:0] out_prepend_349 = 64'h100026237B200073; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4404 = 64'h100026237B200073; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4405 = 64'h100026237B200073; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_9 = 64'h100026237B200073; // @[MuxLiteral.scala:49:48] wire [63:0] out_prepend_592 = 64'h7B20247310802423; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6965 = 64'h7B20247310802423; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6966 = 64'h7B20247310802423; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_8 = 64'h7B20247310802423; // @[MuxLiteral.scala:49:48] wire [63:0] out_prepend_866 = 64'hF140247330000067; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9839 = 64'hF140247330000067; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9840 = 64'hF140247330000067; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_7 = 64'hF140247330000067; // @[MuxLiteral.scala:49:48] wire [63:0] out_prepend_1055 = 64'h100022237B202473; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11815 = 64'h100022237B202473; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11816 = 64'h100022237B202473; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_6 = 64'h100022237B202473; // @[MuxLiteral.scala:49:48] wire [63:0] out_prepend_258 = 64'h4086300147413; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3452 = 64'h4086300147413; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3453 = 64'h4086300147413; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_5 = 64'h4086300147413; // @[MuxLiteral.scala:49:48] wire [63:0] out_prepend_391 = 64'hFE0408E300347413; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4836 = 64'hFE0408E300347413; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4837 = 64'hFE0408E300347413; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_4 = 64'hFE0408E300347413; // @[MuxLiteral.scala:49:48] wire [63:0] out_prepend_641 = 64'h4004440310802023; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7469 = 64'h4004440310802023; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7470 = 64'h4004440310802023; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_3 = 64'h4004440310802023; // @[MuxLiteral.scala:49:48] wire [63:0] out_prepend_950 = 64'hF14024737B241073; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10719 = 64'hF14024737B241073; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10720 = 64'hF14024737B241073; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_2 = 64'hF14024737B241073; // @[MuxLiteral.scala:49:48] wire [63:0] out_prepend_202 = 64'hFF0000F0440006F; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2860 = 64'hFF0000F0440006F; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2861 = 64'hFF0000F0440006F; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_1 = 64'hFF0000F0440006F; // @[MuxLiteral.scala:49:48] wire [63:0] out_prepend_511 = 64'h380006F00C0006F; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6103 = 64'h380006F00C0006F; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6104 = 64'h380006F00C0006F; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_0 = 64'h380006F00C0006F; // @[MuxLiteral.scala:49:48] wire [55:0] out_prepend_1054 = 56'h22237B202473; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11806 = 56'h22237B202473; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11807 = 56'h22237B202473; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1055 = 56'h22237B202473; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1053 = 48'h22237B202473; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11797 = 48'h22237B202473; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11798 = 48'h22237B202473; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1054 = 48'h22237B202473; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1052 = 40'h237B202473; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11788 = 40'h237B202473; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11789 = 40'h237B202473; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1053 = 40'h237B202473; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1051 = 32'h7B202473; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11779 = 32'h7B202473; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11780 = 32'h7B202473; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1052 = 32'h7B202473; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1050 = 24'h202473; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11770 = 24'h202473; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11771 = 24'h202473; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1051 = 24'h202473; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1049 = 16'h2473; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11761 = 16'h2473; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11762 = 16'h2473; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1050 = 16'h2473; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4341 = 8'h73; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4342 = 8'h73; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_343 = 8'h73; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6328 = 8'h73; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6329 = 8'h73; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_533 = 8'h73; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10656 = 8'h73; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10657 = 8'h73; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_944 = 8'h73; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11752 = 8'h73; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11753 = 8'h73; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1049 = 8'h73; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_949 = 56'h4024737B241073; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10710 = 56'h4024737B241073; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10711 = 56'h4024737B241073; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_950 = 56'h4024737B241073; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_948 = 48'h24737B241073; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10701 = 48'h24737B241073; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10702 = 48'h24737B241073; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_949 = 48'h24737B241073; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_947 = 40'h737B241073; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10692 = 40'h737B241073; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10693 = 40'h737B241073; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_948 = 40'h737B241073; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_946 = 32'h7B241073; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10683 = 32'h7B241073; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10684 = 32'h7B241073; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_947 = 32'h7B241073; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_945 = 24'h241073; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10674 = 24'h241073; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10675 = 24'h241073; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_946 = 24'h241073; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_944 = 16'h1073; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10665 = 16'h1073; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10666 = 16'h1073; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_945 = 16'h1073; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_865 = 56'h40247330000067; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9830 = 56'h40247330000067; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9831 = 56'h40247330000067; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_866 = 56'h40247330000067; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_864 = 48'h247330000067; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9821 = 48'h247330000067; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9822 = 48'h247330000067; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_865 = 48'h247330000067; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_863 = 40'h7330000067; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9812 = 40'h7330000067; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9813 = 40'h7330000067; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_864 = 40'h7330000067; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_862 = 32'h30000067; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9803 = 32'h30000067; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9804 = 32'h30000067; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_863 = 32'h30000067; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_861 = 24'h67; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9794 = 24'h67; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9795 = 24'h67; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_862 = 24'h67; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_860 = 16'h67; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9785 = 16'h67; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9786 = 16'h67; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_861 = 16'h67; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9776 = 8'h67; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9777 = 8'h67; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_860 = 8'h67; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_640 = 56'h4440310802023; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7460 = 56'h4440310802023; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7461 = 56'h4440310802023; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_641 = 56'h4440310802023; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_639 = 48'h440310802023; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7451 = 48'h440310802023; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7452 = 48'h440310802023; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_640 = 48'h440310802023; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_638 = 40'h310802023; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7442 = 40'h310802023; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7443 = 40'h310802023; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_639 = 40'h310802023; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_637 = 32'h10802023; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7433 = 32'h10802023; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7434 = 32'h10802023; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_638 = 32'h10802023; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_636 = 24'h802023; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7424 = 24'h802023; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7425 = 24'h802023; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_637 = 24'h802023; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_635 = 16'h2023; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7415 = 16'h2023; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7416 = 16'h2023; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_636 = 16'h2023; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6902 = 8'h23; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6903 = 8'h23; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_586 = 8'h23; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7406 = 8'h23; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7407 = 8'h23; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_635 = 8'h23; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_591 = 56'h20247310802423; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6956 = 56'h20247310802423; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6957 = 56'h20247310802423; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_592 = 56'h20247310802423; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_590 = 48'h247310802423; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6947 = 48'h247310802423; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6948 = 48'h247310802423; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_591 = 48'h247310802423; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_589 = 40'h7310802423; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6938 = 40'h7310802423; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6939 = 40'h7310802423; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_590 = 40'h7310802423; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_588 = 32'h10802423; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6929 = 32'h10802423; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6930 = 32'h10802423; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_589 = 32'h10802423; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_587 = 24'h802423; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6920 = 24'h802423; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6921 = 24'h802423; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_588 = 24'h802423; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_586 = 16'h2423; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6911 = 16'h2423; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6912 = 16'h2423; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_587 = 16'h2423; // @[RegisterRouter.scala:87:24] wire [41:0] _out_T_5142 = 42'h0; // @[RegisterRouter.scala:87:24] wire [41:0] _out_T_5143 = 42'h0; // @[RegisterRouter.scala:87:24] wire [41:0] _out_T_6821 = 42'h0; // @[RegisterRouter.scala:87:24] wire [41:0] _out_T_6822 = 42'h0; // @[RegisterRouter.scala:87:24] wire [32:0] out_prepend_420 = 33'h0; // @[RegisterRouter.scala:87:24] wire [32:0] out_prepend_578 = 33'h0; // @[RegisterRouter.scala:87:24] wire [9:0] _jalAbstract_WIRE_imm0 = 10'h0; // @[Debug.scala:1497:66] wire [9:0] _jalAbstract_imm1_T = 10'h0; // @[package.scala:45:27] wire [9:0] _out_T_5133 = 10'h0; // @[RegisterRouter.scala:87:24] wire [9:0] _out_T_5134 = 10'h0; // @[RegisterRouter.scala:87:24] wire [9:0] _out_T_6812 = 10'h0; // @[RegisterRouter.scala:87:24] wire [9:0] _out_T_6813 = 10'h0; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_535 = 32'h100073; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6355 = 32'h100073; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6356 = 32'h100073; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_534 = 24'h100073; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6346 = 24'h100073; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6347 = 24'h100073; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_535 = 24'h100073; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_343 = 16'h73; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4350 = 16'h73; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4351 = 16'h73; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_344 = 16'h73; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_533 = 16'h73; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6337 = 16'h73; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6338 = 16'h73; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_534 = 16'h73; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_510 = 56'h80006F00C0006F; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6094 = 56'h80006F00C0006F; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6095 = 56'h80006F00C0006F; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_511 = 56'h80006F00C0006F; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_509 = 48'h6F00C0006F; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6085 = 48'h6F00C0006F; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6086 = 48'h6F00C0006F; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_510 = 48'h6F00C0006F; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_508 = 40'h6F00C0006F; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6076 = 40'h6F00C0006F; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6077 = 40'h6F00C0006F; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_509 = 40'h6F00C0006F; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_507 = 32'hC0006F; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6067 = 32'hC0006F; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6068 = 32'hC0006F; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_508 = 32'hC0006F; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_506 = 24'hC0006F; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6058 = 24'hC0006F; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6059 = 24'hC0006F; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_507 = 24'hC0006F; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_196 = 16'h6F; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2806 = 16'h6F; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2807 = 16'h6F; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_197 = 16'h6F; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_505 = 16'h6F; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6049 = 16'h6F; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6050 = 16'h6F; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_506 = 16'h6F; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2797 = 8'h6F; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2798 = 8'h6F; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_196 = 8'h6F; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6040 = 8'h6F; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6041 = 8'h6F; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_505 = 8'h6F; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5943 = 32'h380006F; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5944 = 32'h380006F; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_390 = 56'h408E300347413; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4827 = 56'h408E300347413; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4828 = 56'h408E300347413; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_391 = 56'h408E300347413; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_389 = 48'h8E300347413; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4818 = 48'h8E300347413; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4819 = 48'h8E300347413; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_390 = 48'h8E300347413; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_388 = 40'hE300347413; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4809 = 40'hE300347413; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4810 = 40'hE300347413; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_389 = 40'hE300347413; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_387 = 32'h347413; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4800 = 32'h347413; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4801 = 32'h347413; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_388 = 32'h347413; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_386 = 24'h347413; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4791 = 24'h347413; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4792 = 24'h347413; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_387 = 24'h347413; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_252 = 16'h7413; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3398 = 16'h7413; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3399 = 16'h7413; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_253 = 16'h7413; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_385 = 16'h7413; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4782 = 16'h7413; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4783 = 16'h7413; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_386 = 16'h7413; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3389 = 8'h13; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3390 = 8'h13; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_252 = 8'h13; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4773 = 8'h13; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4774 = 8'h13; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_385 = 8'h13; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_348 = 56'h26237B200073; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4395 = 56'h26237B200073; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4396 = 56'h26237B200073; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_349 = 56'h26237B200073; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_347 = 48'h26237B200073; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4386 = 48'h26237B200073; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4387 = 48'h26237B200073; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_348 = 48'h26237B200073; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_346 = 40'h237B200073; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4377 = 40'h237B200073; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4378 = 40'h237B200073; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_347 = 40'h237B200073; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_345 = 32'h7B200073; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4368 = 32'h7B200073; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4369 = 32'h7B200073; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_346 = 32'h7B200073; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_344 = 24'h200073; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4359 = 24'h200073; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4360 = 24'h200073; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_345 = 24'h200073; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_257 = 56'h4086300147413; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3443 = 56'h4086300147413; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3444 = 56'h4086300147413; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_258 = 56'h4086300147413; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_256 = 48'h86300147413; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3434 = 48'h86300147413; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3435 = 48'h86300147413; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_257 = 48'h86300147413; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_255 = 40'h6300147413; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3425 = 40'h6300147413; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3426 = 40'h6300147413; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_256 = 40'h6300147413; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_254 = 32'h147413; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3416 = 32'h147413; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3417 = 32'h147413; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_255 = 32'h147413; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_253 = 24'h147413; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3407 = 24'h147413; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3408 = 24'h147413; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_254 = 24'h147413; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_201 = 56'hF0000F0440006F; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2851 = 56'hF0000F0440006F; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2852 = 56'hF0000F0440006F; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_202 = 56'hF0000F0440006F; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_200 = 48'hF0440006F; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2842 = 48'hF0440006F; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2843 = 48'hF0440006F; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_201 = 48'hF0440006F; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_199 = 40'hF0440006F; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2833 = 40'hF0440006F; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2834 = 40'hF0440006F; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_200 = 40'hF0440006F; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_198 = 32'h440006F; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2824 = 32'h440006F; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2825 = 32'h440006F; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_199 = 32'h440006F; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_197 = 24'h40006F; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2815 = 24'h40006F; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2816 = 24'h40006F; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_198 = 24'h40006F; // @[RegisterRouter.scala:87:24] wire [8:0] out_maskMatch_1 = 9'h100; // @[RegisterRouter.scala:87:24] wire [11:0] hi = 12'h38; // @[Debug.scala:1697:55] wire [10:0] hi_hi = 11'h1C; // @[Debug.scala:1697:55] wire [19:0] lo = 20'h6F; // @[Debug.scala:1697:55] wire [12:0] lo_hi = 13'h0; // @[Debug.scala:1697:55] wire [31:0] _abstractGeneratedMem_0_T_3 = 32'h13; // @[Debug.scala:1642:15] wire [31:0] _abstractGeneratedMem_1_T = 32'h13; // @[Debug.scala:1645:15] wire [19:0] abstractGeneratedMem_0_hi_2 = 20'h0; // @[Debug.scala:1642:15] wire [19:0] abstractGeneratedMem_1_hi = 20'h0; // @[Debug.scala:1645:15] wire [16:0] abstractGeneratedMem_0_hi_hi_2 = 17'h0; // @[Debug.scala:1642:15] wire [16:0] abstractGeneratedMem_1_hi_hi = 17'h0; // @[Debug.scala:1645:15] wire [11:0] abstractGeneratedMem_0_lo_2 = 12'h13; // @[Debug.scala:1642:15] wire [11:0] abstractGeneratedMem_1_lo = 12'h13; // @[Debug.scala:1645:15] wire [6:0] abstractGeneratedMem_0_inst_1_opcode = 7'h23; // @[Debug.scala:1601:22] wire [6:0] _abstractGeneratedMem_0_inst_opcode_WIRE_1_opcode = 7'h23; // @[Debug.scala:1604:55] wire [4:0] _DMCS2RdData_WIRE_haltgroup = 5'h0; // @[Debug.scala:1025:47] wire [4:0] DMCS2RdData_haltgroup = 5'h0; // @[Debug.scala:1025:34] wire [4:0] _DMCS2WrData_WIRE_haltgroup = 5'h0; // @[Debug.scala:1026:47] wire [4:0] DMCS2WrData_haltgroup = 5'h0; // @[Debug.scala:1026:34] wire [4:0] _ABSTRACTCSReset_WIRE_progbufsize = 5'h0; // @[Debug.scala:1179:48] wire [4:0] _ABSTRACTCSWrData_WIRE_progbufsize = 5'h0; // @[Debug.scala:1184:52] wire [4:0] ABSTRACTCSWrData_progbufsize = 5'h0; // @[Debug.scala:1184:39] wire [4:0] _jalAbstract_WIRE_rd = 5'h0; // @[Debug.scala:1497:66] wire [4:0] jalAbstract_rd = 5'h0; // @[Debug.scala:1497:32] wire [4:0] jalAbstract_imm0_hi = 5'h0; // @[package.scala:45:27] wire [4:0] jalAbstract_imm1_lo = 5'h0; // @[package.scala:45:27] wire [4:0] jalAbstract_imm1_hi = 5'h0; // @[package.scala:45:27] wire [4:0] nop_rs1 = 5'h0; // @[Debug.scala:1623:19] wire [4:0] nop_rd = 5'h0; // @[Debug.scala:1623:19] wire [4:0] _nop_WIRE_rs1 = 5'h0; // @[Debug.scala:1624:46] wire [4:0] _nop_WIRE_rd = 5'h0; // @[Debug.scala:1624:46] wire [4:0] isa_rs1 = 5'h0; // @[Debug.scala:1629:19] wire [4:0] isa_rd = 5'h0; // @[Debug.scala:1629:19] wire [4:0] _isa_WIRE_rs1 = 5'h0; // @[Debug.scala:1630:47] wire [4:0] _isa_WIRE_rd = 5'h0; // @[Debug.scala:1630:47] wire [4:0] abstractGeneratedMem_0_inst_rs1 = 5'h0; // @[Debug.scala:1589:22] wire [4:0] _abstractGeneratedMem_0_inst_opcode_WIRE_rs1 = 5'h0; // @[Debug.scala:1592:55] wire [4:0] _abstractGeneratedMem_0_inst_opcode_WIRE_rd = 5'h0; // @[Debug.scala:1592:55] wire [4:0] abstractGeneratedMem_0_inst_1_rs1 = 5'h0; // @[Debug.scala:1601:22] wire [4:0] abstractGeneratedMem_0_inst_1_immlo = 5'h0; // @[Debug.scala:1601:22] wire [4:0] _abstractGeneratedMem_0_inst_opcode_WIRE_1_rs2 = 5'h0; // @[Debug.scala:1604:55] wire [4:0] _abstractGeneratedMem_0_inst_opcode_WIRE_1_rs1 = 5'h0; // @[Debug.scala:1604:55] wire [4:0] _abstractGeneratedMem_0_inst_opcode_WIRE_1_immlo = 5'h0; // @[Debug.scala:1604:55] wire [2:0] SBCSFieldsRegReset_sbaccess = 3'h2; // @[SBA.scala:49:38] wire [2:0] _abstractGeneratedMem_0_inst_opcode_WIRE_funct3 = 3'h2; // @[Debug.scala:1592:55] wire [2:0] _abstractGeneratedMem_0_inst_opcode_WIRE_1_funct3 = 3'h2; // @[Debug.scala:1604:55] wire [6:0] _SBCSFieldsRegReset_WIRE_sbasize = 7'h0; // @[SBA.scala:49:51] wire [6:0] _SBCSRdData_WIRE_sbasize = 7'h0; // @[SBA.scala:60:51] wire [6:0] _SBCSWrData_WIRE_sbasize = 7'h0; // @[SBA.scala:63:61] wire [6:0] _SBCSWrData_T_5 = 7'h0; // @[SBA.scala:63:61] wire [6:0] SBCSWrData_sbasize = 7'h0; // @[SBA.scala:63:38] wire [6:0] _SBCSRdData_WIRE_1_sbasize = 7'h0; // @[SBA.scala:243:33] wire [6:0] _abstractGeneratedMem_0_inst_opcode_WIRE_1_immhi = 7'h0; // @[Debug.scala:1604:55] wire [6:0] abstractGeneratedMem_0_inst_1_immhi = 7'h1C; // @[Debug.scala:1601:22] wire [16:0] abstractGeneratedMem_0_hi_hi = 17'h7000; // @[Debug.scala:1597:12] wire [6:0] abstractGeneratedMem_0_inst_opcode = 7'h3; // @[Debug.scala:1589:22] wire [6:0] _abstractGeneratedMem_0_inst_opcode_WIRE_opcode = 7'h3; // @[Debug.scala:1592:55] wire [11:0] _ABSTRACTAUTOReset_WIRE_autoexecdata = 12'h0; // @[Debug.scala:1234:54] wire [11:0] ABSTRACTAUTOReset_autoexecdata = 12'h0; // @[Debug.scala:1234:41] wire [11:0] _ABSTRACTAUTOWrData_WIRE_autoexecdata = 12'h0; // @[Debug.scala:1236:54] wire [11:0] nop_imm = 12'h0; // @[Debug.scala:1623:19] wire [11:0] _nop_WIRE_imm = 12'h0; // @[Debug.scala:1624:46] wire [11:0] isa_imm = 12'h0; // @[Debug.scala:1629:19] wire [11:0] _isa_WIRE_imm = 12'h0; // @[Debug.scala:1630:47] wire [11:0] _abstractGeneratedMem_0_inst_opcode_WIRE_imm = 12'h0; // @[Debug.scala:1592:55] wire [11:0] abstractGeneratedMem_0_inst_imm = 12'h380; // @[Debug.scala:1589:22] wire [6:0] isa_opcode = 7'h1B; // @[Debug.scala:1629:19] wire [6:0] _isa_WIRE_opcode = 7'h1B; // @[Debug.scala:1630:47] wire [6:0] nop_opcode = 7'h13; // @[Debug.scala:1623:19] wire [6:0] _nop_WIRE_opcode = 7'h13; // @[Debug.scala:1624:46] wire [9:0] jalAbstract_imm0 = 10'h1C; // @[Debug.scala:1497:32] wire [9:0] _jalAbstract_imm0_T = 10'h1C; // @[package.scala:45:27] wire [4:0] jalAbstract_imm0_lo = 5'h1C; // @[package.scala:45:27] wire [2:0] out_prepend_25 = 3'h7; // @[RegisterRouter.scala:87:24] wire [2:0] _out_T_456 = 3'h7; // @[RegisterRouter.scala:87:24] wire [2:0] _out_T_457 = 3'h7; // @[RegisterRouter.scala:87:24] wire [2:0] _out_prepend_T_26 = 3'h7; // @[RegisterRouter.scala:87:24] wire [2:0] jalAbstract_imm0_lo_hi = 3'h7; // @[package.scala:45:27] wire [1:0] out_prepend_24 = 2'h3; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_447 = 2'h3; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_448 = 2'h3; // @[RegisterRouter.scala:87:24] wire [1:0] _out_prepend_T_25 = 2'h3; // @[RegisterRouter.scala:87:24] wire [1:0] jalAbstract_imm0_lo_hi_hi = 2'h3; // @[package.scala:45:27] wire [20:0] immWire = 21'h38; // @[Debug.scala:1574:31] wire [6:0] _jalAbstract_WIRE_opcode = 7'h6F; // @[Debug.scala:1497:66] wire [6:0] jalAbstract_opcode = 7'h6F; // @[Debug.scala:1497:32] wire [7:0] out_prepend_64 = 8'hA2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_991 = 8'hA2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_992 = 8'hA2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_65 = 8'hA2; // @[RegisterRouter.scala:87:24] wire [6:0] out_prepend_63 = 7'h22; // @[RegisterRouter.scala:87:24] wire [6:0] _out_T_982 = 7'h22; // @[RegisterRouter.scala:87:24] wire [6:0] _out_T_983 = 7'h22; // @[RegisterRouter.scala:87:24] wire [6:0] _out_prepend_T_64 = 7'h22; // @[RegisterRouter.scala:87:24] wire [5:0] out_prepend_62 = 6'h22; // @[RegisterRouter.scala:87:24] wire [5:0] _out_T_973 = 6'h22; // @[RegisterRouter.scala:87:24] wire [5:0] _out_T_974 = 6'h22; // @[RegisterRouter.scala:87:24] wire [5:0] _out_prepend_T_63 = 6'h22; // @[RegisterRouter.scala:87:24] wire [4:0] out_prepend_61 = 5'h2; // @[RegisterRouter.scala:87:24] wire [4:0] _out_T_964 = 5'h2; // @[RegisterRouter.scala:87:24] wire [4:0] _out_T_965 = 5'h2; // @[RegisterRouter.scala:87:24] wire [4:0] _out_prepend_T_62 = 5'h2; // @[RegisterRouter.scala:87:24] wire [3:0] DMSTATUSRdData_version = 4'h2; // @[Debug.scala:978:34] wire [3:0] _out_T_955 = 4'h2; // @[RegisterRouter.scala:87:24] wire [3:0] _out_T_956 = 4'h2; // @[RegisterRouter.scala:87:24] wire [3:0] _out_prepend_T_61 = 4'h2; // @[RegisterRouter.scala:87:24] wire [11:0] out_prepend_28 = 12'h40F; // @[RegisterRouter.scala:87:24] wire [11:0] _out_T_483 = 12'h40F; // @[RegisterRouter.scala:87:24] wire [11:0] _out_T_484 = 12'h40F; // @[RegisterRouter.scala:87:24] wire [11:0] _out_prepend_T_29 = 12'h40F; // @[RegisterRouter.scala:87:24] wire [4:0] out_prepend_27 = 5'hF; // @[RegisterRouter.scala:87:24] wire [4:0] _out_T_474 = 5'hF; // @[RegisterRouter.scala:87:24] wire [4:0] _out_T_475 = 5'hF; // @[RegisterRouter.scala:87:24] wire [4:0] _out_prepend_T_28 = 5'hF; // @[RegisterRouter.scala:87:24] wire [3:0] out_prepend_26 = 4'hF; // @[RegisterRouter.scala:87:24] wire [3:0] _out_T_465 = 4'hF; // @[RegisterRouter.scala:87:24] wire [3:0] _out_T_466 = 4'hF; // @[RegisterRouter.scala:87:24] wire [3:0] _out_prepend_T_27 = 4'hF; // @[RegisterRouter.scala:87:24] wire [6:0] out_maskMatch = 7'h40; // @[RegisterRouter.scala:87:24] wire [1:0] _haltedBitRegs_T_3 = 2'h2; // @[Debug.scala:1330:45] wire [1:0] _resumeReqRegs_T_2 = 2'h2; // @[Debug.scala:1338:45] wire [1:0] hartHaltedIdIndex = 2'h1; // @[OneHot.scala:58:35] wire [1:0] hartResumingIdIndex = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _haltedBitRegs_T = 2'h1; // @[Debug.scala:1327:43] wire [23:0] _COMMANDReset_WIRE_control = 24'h0; // @[Debug.scala:1276:45] wire [23:0] COMMANDReset_control = 24'h0; // @[Debug.scala:1276:32] wire [20:0] _DMCS2RdData_WIRE_reserved0 = 21'h0; // @[Debug.scala:1025:47] wire [20:0] DMCS2RdData_reserved0 = 21'h0; // @[Debug.scala:1025:34] wire [20:0] _DMCS2WrData_WIRE_reserved0 = 21'h0; // @[Debug.scala:1026:47] wire [20:0] DMCS2WrData_reserved0 = 21'h0; // @[Debug.scala:1026:34] wire [8:0] _DMSTATUSRdData_WIRE_reserved0 = 9'h0; // @[Debug.scala:978:47] wire [8:0] DMSTATUSRdData_reserved0 = 9'h0; // @[Debug.scala:978:34] wire tlNodeIn_a_ready; // @[MixedNode.scala:551:17] wire tlNodeIn_a_valid = auto_tl_in_a_valid_0; // @[Debug.scala:790:9] wire [2:0] tlNodeIn_a_bits_opcode = auto_tl_in_a_bits_opcode_0; // @[Debug.scala:790:9] wire [2:0] tlNodeIn_a_bits_param = auto_tl_in_a_bits_param_0; // @[Debug.scala:790:9] wire [1:0] tlNodeIn_a_bits_size = auto_tl_in_a_bits_size_0; // @[Debug.scala:790:9] wire [10:0] tlNodeIn_a_bits_source = auto_tl_in_a_bits_source_0; // @[Debug.scala:790:9] wire [11:0] tlNodeIn_a_bits_address = auto_tl_in_a_bits_address_0; // @[Debug.scala:790:9] wire [7:0] tlNodeIn_a_bits_mask = auto_tl_in_a_bits_mask_0; // @[Debug.scala:790:9] wire [63:0] tlNodeIn_a_bits_data = auto_tl_in_a_bits_data_0; // @[Debug.scala:790:9] wire tlNodeIn_a_bits_corrupt = auto_tl_in_a_bits_corrupt_0; // @[Debug.scala:790:9] wire tlNodeIn_d_ready = auto_tl_in_d_ready_0; // @[Debug.scala:790:9] wire tlNodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] tlNodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] tlNodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [10:0] tlNodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] tlNodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire dmiNodeIn_a_ready; // @[MixedNode.scala:551:17] wire dmiNodeIn_a_valid = auto_dmi_in_a_valid_0; // @[Debug.scala:790:9] wire [2:0] dmiNodeIn_a_bits_opcode = auto_dmi_in_a_bits_opcode_0; // @[Debug.scala:790:9] wire [2:0] dmiNodeIn_a_bits_param = auto_dmi_in_a_bits_param_0; // @[Debug.scala:790:9] wire [1:0] dmiNodeIn_a_bits_size = auto_dmi_in_a_bits_size_0; // @[Debug.scala:790:9] wire dmiNodeIn_a_bits_source = auto_dmi_in_a_bits_source_0; // @[Debug.scala:790:9] wire [8:0] dmiNodeIn_a_bits_address = auto_dmi_in_a_bits_address_0; // @[Debug.scala:790:9] wire [3:0] dmiNodeIn_a_bits_mask = auto_dmi_in_a_bits_mask_0; // @[Debug.scala:790:9] wire [31:0] dmiNodeIn_a_bits_data = auto_dmi_in_a_bits_data_0; // @[Debug.scala:790:9] wire dmiNodeIn_a_bits_corrupt = auto_dmi_in_a_bits_corrupt_0; // @[Debug.scala:790:9] wire dmiNodeIn_d_ready = auto_dmi_in_d_ready_0; // @[Debug.scala:790:9] wire dmiNodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] dmiNodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] dmiNodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire dmiNodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [31:0] dmiNodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire _resumereq_T = io_innerCtrl_valid_0; // @[Decoupled.scala:51:35] wire hrDebugInt_0; // @[Debug.scala:946:26] wire [2:0] auto_sb2tlOpt_out_a_bits_opcode_0; // @[Debug.scala:790:9] wire [3:0] auto_sb2tlOpt_out_a_bits_size_0; // @[Debug.scala:790:9] wire [31:0] auto_sb2tlOpt_out_a_bits_address_0; // @[Debug.scala:790:9] wire [7:0] auto_sb2tlOpt_out_a_bits_data_0; // @[Debug.scala:790:9] wire auto_sb2tlOpt_out_a_valid_0; // @[Debug.scala:790:9] wire auto_sb2tlOpt_out_d_ready_0; // @[Debug.scala:790:9] wire auto_tl_in_a_ready_0; // @[Debug.scala:790:9] wire [2:0] auto_tl_in_d_bits_opcode_0; // @[Debug.scala:790:9] wire [1:0] auto_tl_in_d_bits_size_0; // @[Debug.scala:790:9] wire [10:0] auto_tl_in_d_bits_source_0; // @[Debug.scala:790:9] wire [63:0] auto_tl_in_d_bits_data_0; // @[Debug.scala:790:9] wire auto_tl_in_d_valid_0; // @[Debug.scala:790:9] wire auto_dmi_in_a_ready_0; // @[Debug.scala:790:9] wire [2:0] auto_dmi_in_d_bits_opcode_0; // @[Debug.scala:790:9] wire [1:0] auto_dmi_in_d_bits_size_0; // @[Debug.scala:790:9] wire auto_dmi_in_d_bits_source_0; // @[Debug.scala:790:9] wire [31:0] auto_dmi_in_d_bits_data_0; // @[Debug.scala:790:9] wire auto_dmi_in_d_valid_0; // @[Debug.scala:790:9] wire io_hgDebugInt_0_0; // @[Debug.scala:790:9] wire in_ready; // @[RegisterRouter.scala:73:18] assign auto_dmi_in_a_ready_0 = dmiNodeIn_a_ready; // @[Debug.scala:790:9] wire in_valid = dmiNodeIn_a_valid; // @[RegisterRouter.scala:73:18] wire [1:0] in_bits_extra_tlrr_extra_size = dmiNodeIn_a_bits_size; // @[RegisterRouter.scala:73:18] wire in_bits_extra_tlrr_extra_source = dmiNodeIn_a_bits_source; // @[RegisterRouter.scala:73:18] wire [3:0] in_bits_mask = dmiNodeIn_a_bits_mask; // @[RegisterRouter.scala:73:18] wire [31:0] in_bits_data = dmiNodeIn_a_bits_data; // @[RegisterRouter.scala:73:18] wire out_ready = dmiNodeIn_d_ready; // @[RegisterRouter.scala:87:24] wire out_valid; // @[RegisterRouter.scala:87:24] assign auto_dmi_in_d_valid_0 = dmiNodeIn_d_valid; // @[Debug.scala:790:9] assign auto_dmi_in_d_bits_opcode_0 = dmiNodeIn_d_bits_opcode; // @[Debug.scala:790:9] wire [1:0] dmiNodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign auto_dmi_in_d_bits_size_0 = dmiNodeIn_d_bits_size; // @[Debug.scala:790:9] wire dmiNodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign auto_dmi_in_d_bits_source_0 = dmiNodeIn_d_bits_source; // @[Debug.scala:790:9] wire [31:0] out_bits_data; // @[RegisterRouter.scala:87:24] assign auto_dmi_in_d_bits_data_0 = dmiNodeIn_d_bits_data; // @[Debug.scala:790:9] wire in_1_ready; // @[RegisterRouter.scala:73:18] assign auto_tl_in_a_ready_0 = tlNodeIn_a_ready; // @[Debug.scala:790:9] wire in_1_valid = tlNodeIn_a_valid; // @[RegisterRouter.scala:73:18] wire [1:0] in_1_bits_extra_tlrr_extra_size = tlNodeIn_a_bits_size; // @[RegisterRouter.scala:73:18] wire [10:0] in_1_bits_extra_tlrr_extra_source = tlNodeIn_a_bits_source; // @[RegisterRouter.scala:73:18] wire [7:0] in_1_bits_mask = tlNodeIn_a_bits_mask; // @[RegisterRouter.scala:73:18] wire [63:0] in_1_bits_data = tlNodeIn_a_bits_data; // @[RegisterRouter.scala:73:18] wire out_1_ready = tlNodeIn_d_ready; // @[RegisterRouter.scala:87:24] wire out_1_valid; // @[RegisterRouter.scala:87:24] assign auto_tl_in_d_valid_0 = tlNodeIn_d_valid; // @[Debug.scala:790:9] assign auto_tl_in_d_bits_opcode_0 = tlNodeIn_d_bits_opcode; // @[Debug.scala:790:9] wire [1:0] tlNodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign auto_tl_in_d_bits_size_0 = tlNodeIn_d_bits_size; // @[Debug.scala:790:9] wire [10:0] tlNodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign auto_tl_in_d_bits_source_0 = tlNodeIn_d_bits_source; // @[Debug.scala:790:9] wire [63:0] out_1_bits_data; // @[RegisterRouter.scala:87:24] assign auto_tl_in_d_bits_data_0 = tlNodeIn_d_bits_data; // @[Debug.scala:790:9] reg haltedBitRegs; // @[Debug.scala:861:31] wire _DMSTATUSRdData_anyhalted_T_1 = haltedBitRegs; // @[Debug.scala:861:31, :995:77] wire _DMSTATUSRdData_anyrunning_T_1 = haltedBitRegs; // @[Debug.scala:861:31, :996:77] wire _DMSTATUSRdData_allhalted_T_1 = haltedBitRegs; // @[Debug.scala:861:31, :1001:79] wire _DMSTATUSRdData_allrunning_T_1 = haltedBitRegs; // @[Debug.scala:861:31, :1002:79] wire _haltedStatus_0_T = haltedBitRegs; // @[Debug.scala:861:31, :1163:43] wire _hartHalted_T = haltedBitRegs; // @[Debug.scala:861:31, :1734:37] reg resumeReqRegs; // @[Debug.scala:863:31] wire _flags_resume_T = resumeReqRegs; // @[Debug.scala:863:31, :1524:80] reg haveResetBitRegs; // @[Debug.scala:865:31] wire _DMSTATUSRdData_anyhavereset_T = haveResetBitRegs; // @[Debug.scala:865:31, :997:58] wire _DMSTATUSRdData_allhavereset_T = haveResetBitRegs; // @[Debug.scala:865:31, :1003:60] wire resumeAcks; // @[Debug.scala:869:32] wire _DMSTATUSRdData_anyresumeack_T = resumeAcks; // @[Debug.scala:869:32, :998:52] wire _DMSTATUSRdData_allresumeack_T = resumeAcks; // @[Debug.scala:869:32, :1004:54] wire out_f_woready_681; // @[RegisterRouter.scala:87:24] wire hartHaltedWrEn; // @[Debug.scala:875:36] wire [9:0] _out_T_6805; // @[RegisterRouter.scala:87:24] wire [9:0] hartHaltedId; // @[Debug.scala:876:36] wire out_f_woready_682; // @[RegisterRouter.scala:87:24] wire hartGoingWrEn; // @[Debug.scala:877:36] wire [9:0] _out_T_6814; // @[RegisterRouter.scala:87:24] wire [9:0] hartGoingId; // @[Debug.scala:878:36] wire out_f_woready_498; // @[RegisterRouter.scala:87:24] wire hartResumingWrEn; // @[Debug.scala:879:36] wire [9:0] _out_T_5126; // @[RegisterRouter.scala:87:24] wire [9:0] hartResumingId; // @[Debug.scala:880:36] wire out_f_woready_499; // @[RegisterRouter.scala:87:24] wire hartExceptionWrEn; // @[Debug.scala:881:36] wire [9:0] _out_T_5135; // @[RegisterRouter.scala:87:24] wire [9:0] hartExceptionId; // @[Debug.scala:882:36] wire out_f_roready_101; // @[RegisterRouter.scala:87:24] wire out_f_roready_102; // @[RegisterRouter.scala:87:24] wire out_f_roready_103; // @[RegisterRouter.scala:87:24] wire out_f_roready_104; // @[RegisterRouter.scala:87:24] wire out_f_roready_73; // @[RegisterRouter.scala:87:24] wire out_f_roready_74; // @[RegisterRouter.scala:87:24] wire out_f_roready_75; // @[RegisterRouter.scala:87:24] wire out_f_roready_76; // @[RegisterRouter.scala:87:24] wire out_f_roready_105; // @[RegisterRouter.scala:87:24] wire out_f_roready_106; // @[RegisterRouter.scala:87:24] wire out_f_roready_107; // @[RegisterRouter.scala:87:24] wire out_f_roready_108; // @[RegisterRouter.scala:87:24] wire out_f_roready_13; // @[RegisterRouter.scala:87:24] wire out_f_roready_14; // @[RegisterRouter.scala:87:24] wire out_f_roready_15; // @[RegisterRouter.scala:87:24] wire out_f_roready_16; // @[RegisterRouter.scala:87:24] wire out_f_roready_141; // @[RegisterRouter.scala:87:24] wire out_f_roready_142; // @[RegisterRouter.scala:87:24] wire out_f_roready_143; // @[RegisterRouter.scala:87:24] wire out_f_roready_144; // @[RegisterRouter.scala:87:24] wire out_f_roready_55; // @[RegisterRouter.scala:87:24] wire out_f_roready_56; // @[RegisterRouter.scala:87:24] wire out_f_roready_57; // @[RegisterRouter.scala:87:24] wire out_f_roready_58; // @[RegisterRouter.scala:87:24] wire out_f_roready_69; // @[RegisterRouter.scala:87:24] wire out_f_roready_70; // @[RegisterRouter.scala:87:24] wire out_f_roready_71; // @[RegisterRouter.scala:87:24] wire out_f_roready_72; // @[RegisterRouter.scala:87:24] wire out_f_roready_124; // @[RegisterRouter.scala:87:24] wire out_f_roready_125; // @[RegisterRouter.scala:87:24] wire out_f_roready_126; // @[RegisterRouter.scala:87:24] wire out_f_roready_127; // @[RegisterRouter.scala:87:24] wire out_f_roready_136; // @[RegisterRouter.scala:87:24] wire out_f_roready_137; // @[RegisterRouter.scala:87:24] wire out_f_roready_138; // @[RegisterRouter.scala:87:24] wire out_f_roready_139; // @[RegisterRouter.scala:87:24] wire out_f_roready_9; // @[RegisterRouter.scala:87:24] wire out_f_roready_10; // @[RegisterRouter.scala:87:24] wire out_f_roready_11; // @[RegisterRouter.scala:87:24] wire out_f_roready_12; // @[RegisterRouter.scala:87:24] wire out_f_roready_48; // @[RegisterRouter.scala:87:24] wire out_f_roready_49; // @[RegisterRouter.scala:87:24] wire out_f_roready_50; // @[RegisterRouter.scala:87:24] wire out_f_roready_51; // @[RegisterRouter.scala:87:24] wire out_f_roready_132; // @[RegisterRouter.scala:87:24] wire out_f_roready_133; // @[RegisterRouter.scala:87:24] wire out_f_roready_134; // @[RegisterRouter.scala:87:24] wire out_f_roready_135; // @[RegisterRouter.scala:87:24] wire out_f_roready_116; // @[RegisterRouter.scala:87:24] wire out_f_roready_117; // @[RegisterRouter.scala:87:24] wire out_f_roready_118; // @[RegisterRouter.scala:87:24] wire out_f_roready_119; // @[RegisterRouter.scala:87:24] wire out_f_roready_77; // @[RegisterRouter.scala:87:24] wire out_f_roready_78; // @[RegisterRouter.scala:87:24] wire out_f_roready_79; // @[RegisterRouter.scala:87:24] wire out_f_roready_80; // @[RegisterRouter.scala:87:24] wire out_f_roready_59; // @[RegisterRouter.scala:87:24] wire out_f_roready_60; // @[RegisterRouter.scala:87:24] wire out_f_roready_61; // @[RegisterRouter.scala:87:24] wire out_f_roready_62; // @[RegisterRouter.scala:87:24] wire out_f_roready_25; // @[RegisterRouter.scala:87:24] wire out_f_roready_26; // @[RegisterRouter.scala:87:24] wire out_f_roready_27; // @[RegisterRouter.scala:87:24] wire out_f_roready_28; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_0; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_1; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_2; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_3; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_4; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_5; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_6; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_7; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_8; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_9; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_10; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_11; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_12; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_13; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_14; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_15; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_16; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_17; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_18; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_19; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_20; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_21; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_22; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_23; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_24; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_25; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_26; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_27; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_28; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_29; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_30; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_31; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_32; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_33; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_34; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_35; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_36; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_37; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_38; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_39; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_40; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_41; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_42; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_43; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_44; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_45; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_46; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_47; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_48; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_49; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_50; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_51; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_52; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_53; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_54; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_55; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_56; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_57; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_58; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_59; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_60; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_61; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_62; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_63; // @[Debug.scala:887:40] wire _dmiProgramBufferAccessLegal_T; // @[Debug.scala:1746:50] wire dmiProgramBufferAccessLegal; // @[Debug.scala:888:47] wire out_f_woready_101; // @[RegisterRouter.scala:87:24] wire out_f_woready_102; // @[RegisterRouter.scala:87:24] wire out_f_woready_103; // @[RegisterRouter.scala:87:24] wire out_f_woready_104; // @[RegisterRouter.scala:87:24] wire out_f_woready_73; // @[RegisterRouter.scala:87:24] wire out_f_woready_74; // @[RegisterRouter.scala:87:24] wire out_f_woready_75; // @[RegisterRouter.scala:87:24] wire out_f_woready_76; // @[RegisterRouter.scala:87:24] wire out_f_woready_105; // @[RegisterRouter.scala:87:24] wire out_f_woready_106; // @[RegisterRouter.scala:87:24] wire out_f_woready_107; // @[RegisterRouter.scala:87:24] wire out_f_woready_108; // @[RegisterRouter.scala:87:24] wire out_f_woready_13; // @[RegisterRouter.scala:87:24] wire out_f_woready_14; // @[RegisterRouter.scala:87:24] wire out_f_woready_15; // @[RegisterRouter.scala:87:24] wire out_f_woready_16; // @[RegisterRouter.scala:87:24] wire out_f_woready_141; // @[RegisterRouter.scala:87:24] wire out_f_woready_142; // @[RegisterRouter.scala:87:24] wire out_f_woready_143; // @[RegisterRouter.scala:87:24] wire out_f_woready_144; // @[RegisterRouter.scala:87:24] wire out_f_woready_55; // @[RegisterRouter.scala:87:24] wire out_f_woready_56; // @[RegisterRouter.scala:87:24] wire out_f_woready_57; // @[RegisterRouter.scala:87:24] wire out_f_woready_58; // @[RegisterRouter.scala:87:24] wire out_f_woready_69; // @[RegisterRouter.scala:87:24] wire out_f_woready_70; // @[RegisterRouter.scala:87:24] wire out_f_woready_71; // @[RegisterRouter.scala:87:24] wire out_f_woready_72; // @[RegisterRouter.scala:87:24] wire out_f_woready_124; // @[RegisterRouter.scala:87:24] wire out_f_woready_125; // @[RegisterRouter.scala:87:24] wire out_f_woready_126; // @[RegisterRouter.scala:87:24] wire out_f_woready_127; // @[RegisterRouter.scala:87:24] wire out_f_woready_136; // @[RegisterRouter.scala:87:24] wire out_f_woready_137; // @[RegisterRouter.scala:87:24] wire out_f_woready_138; // @[RegisterRouter.scala:87:24] wire out_f_woready_139; // @[RegisterRouter.scala:87:24] wire out_f_woready_9; // @[RegisterRouter.scala:87:24] wire out_f_woready_10; // @[RegisterRouter.scala:87:24] wire out_f_woready_11; // @[RegisterRouter.scala:87:24] wire out_f_woready_12; // @[RegisterRouter.scala:87:24] wire out_f_woready_48; // @[RegisterRouter.scala:87:24] wire out_f_woready_49; // @[RegisterRouter.scala:87:24] wire out_f_woready_50; // @[RegisterRouter.scala:87:24] wire out_f_woready_51; // @[RegisterRouter.scala:87:24] wire out_f_woready_132; // @[RegisterRouter.scala:87:24] wire out_f_woready_133; // @[RegisterRouter.scala:87:24] wire out_f_woready_134; // @[RegisterRouter.scala:87:24] wire out_f_woready_135; // @[RegisterRouter.scala:87:24] wire out_f_woready_116; // @[RegisterRouter.scala:87:24] wire out_f_woready_117; // @[RegisterRouter.scala:87:24] wire out_f_woready_118; // @[RegisterRouter.scala:87:24] wire out_f_woready_119; // @[RegisterRouter.scala:87:24] wire out_f_woready_77; // @[RegisterRouter.scala:87:24] wire out_f_woready_78; // @[RegisterRouter.scala:87:24] wire out_f_woready_79; // @[RegisterRouter.scala:87:24] wire out_f_woready_80; // @[RegisterRouter.scala:87:24] wire out_f_woready_59; // @[RegisterRouter.scala:87:24] wire out_f_woready_60; // @[RegisterRouter.scala:87:24] wire out_f_woready_61; // @[RegisterRouter.scala:87:24] wire out_f_woready_62; // @[RegisterRouter.scala:87:24] wire out_f_woready_25; // @[RegisterRouter.scala:87:24] wire out_f_woready_26; // @[RegisterRouter.scala:87:24] wire out_f_woready_27; // @[RegisterRouter.scala:87:24] wire out_f_woready_28; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_0; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_1; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_2; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_3; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_4; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_5; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_6; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_7; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_8; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_9; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_10; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_11; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_12; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_13; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_14; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_15; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_16; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_17; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_18; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_19; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_20; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_21; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_22; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_23; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_24; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_25; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_26; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_27; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_28; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_29; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_30; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_31; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_32; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_33; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_34; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_35; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_36; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_37; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_38; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_39; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_40; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_41; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_42; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_43; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_44; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_45; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_46; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_47; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_48; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_49; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_50; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_51; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_52; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_53; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_54; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_55; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_56; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_57; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_58; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_59; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_60; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_61; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_62; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_63; // @[Debug.scala:889:45] wire out_f_roready_21; // @[RegisterRouter.scala:87:24] wire out_f_roready_22; // @[RegisterRouter.scala:87:24] wire out_f_roready_23; // @[RegisterRouter.scala:87:24] wire out_f_roready_24; // @[RegisterRouter.scala:87:24] wire out_f_roready; // @[RegisterRouter.scala:87:24] wire out_f_roready_1; // @[RegisterRouter.scala:87:24] wire out_f_roready_2; // @[RegisterRouter.scala:87:24] wire out_f_roready_3; // @[RegisterRouter.scala:87:24] wire out_f_roready_64; // @[RegisterRouter.scala:87:24] wire out_f_roready_65; // @[RegisterRouter.scala:87:24] wire out_f_roready_66; // @[RegisterRouter.scala:87:24] wire out_f_roready_67; // @[RegisterRouter.scala:87:24] wire out_f_roready_120; // @[RegisterRouter.scala:87:24] wire out_f_roready_121; // @[RegisterRouter.scala:87:24] wire out_f_roready_122; // @[RegisterRouter.scala:87:24] wire out_f_roready_123; // @[RegisterRouter.scala:87:24] wire out_f_roready_17; // @[RegisterRouter.scala:87:24] wire out_f_roready_18; // @[RegisterRouter.scala:87:24] wire out_f_roready_19; // @[RegisterRouter.scala:87:24] wire out_f_roready_20; // @[RegisterRouter.scala:87:24] wire out_f_roready_5; // @[RegisterRouter.scala:87:24] wire out_f_roready_6; // @[RegisterRouter.scala:87:24] wire out_f_roready_7; // @[RegisterRouter.scala:87:24] wire out_f_roready_8; // @[RegisterRouter.scala:87:24] wire out_f_roready_29; // @[RegisterRouter.scala:87:24] wire out_f_roready_30; // @[RegisterRouter.scala:87:24] wire out_f_roready_31; // @[RegisterRouter.scala:87:24] wire out_f_roready_32; // @[RegisterRouter.scala:87:24] wire out_f_roready_128; // @[RegisterRouter.scala:87:24] wire out_f_roready_129; // @[RegisterRouter.scala:87:24] wire out_f_roready_130; // @[RegisterRouter.scala:87:24] wire out_f_roready_131; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataRdEn_0; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_1; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_2; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_3; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_4; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_5; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_6; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_7; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_8; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_9; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_10; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_11; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_12; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_13; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_14; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_15; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_16; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_17; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_18; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_19; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_20; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_21; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_22; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_23; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_24; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_25; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_26; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_27; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_28; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_29; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_30; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_31; // @[Debug.scala:891:39] wire _dmiAbstractDataAccessLegal_T; // @[Debug.scala:1745:50] wire dmiAbstractDataAccessLegal; // @[Debug.scala:892:46] wire out_f_woready_21; // @[RegisterRouter.scala:87:24] wire out_f_woready_22; // @[RegisterRouter.scala:87:24] wire out_f_woready_23; // @[RegisterRouter.scala:87:24] wire out_f_woready_24; // @[RegisterRouter.scala:87:24] wire out_f_woready; // @[RegisterRouter.scala:87:24] wire out_f_woready_1; // @[RegisterRouter.scala:87:24] wire out_f_woready_2; // @[RegisterRouter.scala:87:24] wire out_f_woready_3; // @[RegisterRouter.scala:87:24] wire out_f_woready_64; // @[RegisterRouter.scala:87:24] wire out_f_woready_65; // @[RegisterRouter.scala:87:24] wire out_f_woready_66; // @[RegisterRouter.scala:87:24] wire out_f_woready_67; // @[RegisterRouter.scala:87:24] wire out_f_woready_120; // @[RegisterRouter.scala:87:24] wire out_f_woready_121; // @[RegisterRouter.scala:87:24] wire out_f_woready_122; // @[RegisterRouter.scala:87:24] wire out_f_woready_123; // @[RegisterRouter.scala:87:24] wire out_f_woready_17; // @[RegisterRouter.scala:87:24] wire out_f_woready_18; // @[RegisterRouter.scala:87:24] wire out_f_woready_19; // @[RegisterRouter.scala:87:24] wire out_f_woready_20; // @[RegisterRouter.scala:87:24] wire out_f_woready_5; // @[RegisterRouter.scala:87:24] wire out_f_woready_6; // @[RegisterRouter.scala:87:24] wire out_f_woready_7; // @[RegisterRouter.scala:87:24] wire out_f_woready_8; // @[RegisterRouter.scala:87:24] wire out_f_woready_29; // @[RegisterRouter.scala:87:24] wire out_f_woready_30; // @[RegisterRouter.scala:87:24] wire out_f_woready_31; // @[RegisterRouter.scala:87:24] wire out_f_woready_32; // @[RegisterRouter.scala:87:24] wire out_f_woready_128; // @[RegisterRouter.scala:87:24] wire out_f_woready_129; // @[RegisterRouter.scala:87:24] wire out_f_woready_130; // @[RegisterRouter.scala:87:24] wire out_f_woready_131; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataWrEnMaybe_0; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_1; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_2; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_3; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_4; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_5; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_6; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_7; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_8; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_9; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_10; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_11; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_12; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_13; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_14; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_15; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_16; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_17; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_18; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_19; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_20; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_21; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_22; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_23; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_24; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_25; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_26; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_27; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_28; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_29; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_30; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_31; // @[Debug.scala:893:44] wire _hamaskWrSel_0_T_1; // @[Debug.scala:935:78] wire hamaskWrSel_0; // @[Debug.scala:933:31] wire _hamaskWrSel_0_T = io_innerCtrl_bits_hartsel_0 == 10'h0; // @[Debug.scala:790:9, :935:61] assign _hamaskWrSel_0_T_1 = _hamaskWrSel_0_T; // @[Debug.scala:935:{61,78}] assign hamaskWrSel_0 = _hamaskWrSel_0_T_1; // @[Debug.scala:933:31, :935:78] assign io_hgDebugInt_0_0 = hrDebugInt_0; // @[Debug.scala:790:9, :946:26] reg hrmaskReg_0; // @[Debug.scala:947:29] wire _hartIsInResetSync_0_WIRE; // @[ShiftReg.scala:48:24] wire hartIsInResetSync_0; // @[Debug.scala:948:33] assign hartIsInResetSync_0 = _hartIsInResetSync_0_WIRE; // @[ShiftReg.scala:48:24] reg hrDebugIntReg_0; // @[Debug.scala:961:34] assign hrDebugInt_0 = hrDebugIntReg_0; // @[Debug.scala:946:26, :961:34] wire _DMSTATUSRdData_allnonexistent_T_2; // @[Debug.scala:991:75] wire DMSTATUSRdData_allhavereset; // @[Debug.scala:978:34] wire DMSTATUSRdData_anyhavereset; // @[Debug.scala:978:34] wire DMSTATUSRdData_allresumeack; // @[Debug.scala:978:34] wire DMSTATUSRdData_anyresumeack; // @[Debug.scala:978:34] wire DMSTATUSRdData_allnonexistent; // @[Debug.scala:978:34] wire DMSTATUSRdData_anynonexistent; // @[Debug.scala:978:34] wire DMSTATUSRdData_allunavail; // @[Debug.scala:978:34] wire DMSTATUSRdData_allrunning; // @[Debug.scala:978:34] wire DMSTATUSRdData_anyrunning; // @[Debug.scala:978:34] wire DMSTATUSRdData_allhalted; // @[Debug.scala:978:34] wire DMSTATUSRdData_anyhalted; // @[Debug.scala:978:34] wire resumereq = _resumereq_T & io_innerCtrl_bits_resumereq_0; // @[Decoupled.scala:51:35] assign DMSTATUSRdData_anynonexistent = _DMSTATUSRdData_anynonexistent_T; // @[Debug.scala:978:34, :988:57] wire _DMSTATUSRdData_allnonexistent_T_1 = ~hamaskFull_0; // @[Debug.scala:903:30, :991:78] assign _DMSTATUSRdData_allnonexistent_T_2 = _DMSTATUSRdData_allnonexistent_T & _DMSTATUSRdData_allnonexistent_T_1; // @[Debug.scala:991:{57,75,78}] assign DMSTATUSRdData_allnonexistent = _DMSTATUSRdData_allnonexistent_T_2; // @[Debug.scala:978:34, :991:75] wire _DMSTATUSRdData_anyhalted_T_2 = _DMSTATUSRdData_anyhalted_T_1; // @[package.scala:74:72] wire _DMSTATUSRdData_anyhalted_T_3 = _DMSTATUSRdData_anyhalted_T_2 & hamaskFull_0; // @[package.scala:74:72] assign DMSTATUSRdData_anyhalted = ~DMSTATUSRdData_allnonexistent & _DMSTATUSRdData_anyhalted_T_3; // @[package.scala:74:72] wire _DMSTATUSRdData_anyrunning_T_2 = ~_DMSTATUSRdData_anyrunning_T_1; // @[package.scala:79:37] wire _DMSTATUSRdData_anyrunning_T_3 = _DMSTATUSRdData_anyrunning_T_2; // @[package.scala:74:72, :79:37] wire _DMSTATUSRdData_anyrunning_T_4 = _DMSTATUSRdData_anyrunning_T_3 & hamaskFull_0; // @[package.scala:74:72] assign DMSTATUSRdData_anyrunning = ~DMSTATUSRdData_allnonexistent & _DMSTATUSRdData_anyrunning_T_4; // @[package.scala:74:72] wire _DMSTATUSRdData_anyhavereset_T_1 = _DMSTATUSRdData_anyhavereset_T & hamaskFull_0; // @[package.scala:74:72] assign DMSTATUSRdData_anyhavereset = ~DMSTATUSRdData_allnonexistent & _DMSTATUSRdData_anyhavereset_T_1; // @[package.scala:74:72] wire _DMSTATUSRdData_anyresumeack_T_1 = _DMSTATUSRdData_anyresumeack_T & hamaskFull_0; // @[package.scala:74:72] assign DMSTATUSRdData_anyresumeack = ~DMSTATUSRdData_allnonexistent & _DMSTATUSRdData_anyresumeack_T_1; // @[package.scala:74:72] wire _DMSTATUSRdData_allunavail_T = ~hamaskFull_0; // @[package.scala:79:37] wire _DMSTATUSRdData_allunavail_T_1 = _DMSTATUSRdData_allunavail_T; // @[package.scala:75:75, :79:37] wire _GEN = ~DMSTATUSRdData_allnonexistent & ~DMSTATUSRdData_anynonexistent; // @[Debug.scala:978:34, :993:{13,45}, :999:{15,47}, :1000:39] assign DMSTATUSRdData_allunavail = _GEN & _DMSTATUSRdData_allunavail_T_1; // @[package.scala:75:75] wire _DMSTATUSRdData_allhalted_T_2 = _DMSTATUSRdData_allhalted_T_1; // @[package.scala:74:72] wire _DMSTATUSRdData_allhalted_T_3 = ~hamaskFull_0; // @[package.scala:79:37] wire _DMSTATUSRdData_allhalted_T_4 = _DMSTATUSRdData_allhalted_T_2 \| _DMSTATUSRdData_allhalted_T_3; // @[package.scala:74:72, :75:75, :79:37] assign DMSTATUSRdData_allhalted = _GEN & _DMSTATUSRdData_allhalted_T_4; // @[package.scala:75:75] wire _DMSTATUSRdData_allrunning_T_2 = ~_DMSTATUSRdData_allrunning_T_1; // @[package.scala:79:37] wire _DMSTATUSRdData_allrunning_T_3 = _DMSTATUSRdData_allrunning_T_2; // @[package.scala:74:72, :79:37] wire _DMSTATUSRdData_allrunning_T_4 = ~hamaskFull_0; // @[package.scala:79:37] wire _DMSTATUSRdData_allrunning_T_5 = _DMSTATUSRdData_allrunning_T_3 \| _DMSTATUSRdData_allrunning_T_4; // @[package.scala:74:72, :75:75, :79:37] assign DMSTATUSRdData_allrunning = _GEN & _DMSTATUSRdData_allrunning_T_5; // @[package.scala:75:75] wire _DMSTATUSRdData_allhavereset_T_1 = ~hamaskFull_0; // @[package.scala:79:37] wire _DMSTATUSRdData_allhavereset_T_2 = _DMSTATUSRdData_allhavereset_T \| _DMSTATUSRdData_allhavereset_T_1; // @[package.scala:75:75, :79:37] assign DMSTATUSRdData_allhavereset = _GEN & _DMSTATUSRdData_allhavereset_T_2; // @[package.scala:75:75] wire _DMSTATUSRdData_allresumeack_T_1 = ~hamaskFull_0; // @[package.scala:79:37] wire _DMSTATUSRdData_allresumeack_T_2 = _DMSTATUSRdData_allresumeack_T \| _DMSTATUSRdData_allresumeack_T_1; // @[package.scala:75:75, :79:37] assign DMSTATUSRdData_allresumeack = _GEN & _DMSTATUSRdData_allresumeack_T_2; // @[package.scala:75:75] wire _haveResetBitRegs_T = ~hamaskWrSel_0; // @[Debug.scala:933:31, :1017:50] wire _haveResetBitRegs_T_1 = haveResetBitRegs & _haveResetBitRegs_T; // @[Debug.scala:865:31, :1017:{47,50}] wire _haveResetBitRegs_T_2 = _haveResetBitRegs_T_1 \| hartIsInResetSync_0; // @[Debug.scala:948:33, :1017:{47,74}] wire _haveResetBitRegs_T_3 = haveResetBitRegs \| hartIsInResetSync_0; // @[Debug.scala:865:31, :948:33, :1019:46] wire [31:0] haltedStatus_0; // @[Debug.scala:1159:30] wire [31:0] selectedHaltedStatus = haltedStatus_0; // @[Debug.scala:1159:30, :1172:35] assign haltedStatus_0 = {31'h0, _haltedStatus_0_T}; // @[Debug.scala:1159:30, :1163:{26,43}] wire haltedSummary = \|haltedStatus_0; // @[Debug.scala:1159:30, :1169:48] wire [31:0] _HALTSUM1RdData_T; // @[Debug.scala:1170:48] wire [31:0] HALTSUM1RdData_haltsum1; // @[Debug.scala:1170:48] wire [31:0] _out_T_1598 = HALTSUM1RdData_haltsum1; // @[RegisterRouter.scala:87:24] assign _HALTSUM1RdData_T = _HALTSUM1RdData_WIRE; // @[Debug.scala:1170:48] assign _HALTSUM1RdData_WIRE = {31'h0, haltedSummary}; // @[Debug.scala:1169:48, :1170:48] assign HALTSUM1RdData_haltsum1 = _HALTSUM1RdData_T; // @[Debug.scala:1170:48] wire [31:0] _HALTSUM0RdData_WIRE = selectedHaltedStatus; // @[Debug.scala:1172:35, :1173:55] wire [31:0] _HALTSUM0RdData_T; // @[Debug.scala:1173:55] wire [31:0] HALTSUM0RdData_haltsum0; // @[Debug.scala:1173:55] wire [31:0] _out_T_946 = HALTSUM0RdData_haltsum0; // @[RegisterRouter.scala:87:24] assign _HALTSUM0RdData_T = _HALTSUM0RdData_WIRE; // @[Debug.scala:1173:55] assign HALTSUM0RdData_haltsum0 = _HALTSUM0RdData_T; // @[Debug.scala:1173:55] reg [2:0] ABSTRACTCSReg_cmderr; // @[Debug.scala:1183:34] wire [2:0] ABSTRACTCSRdData_cmderr = ABSTRACTCSReg_cmderr; // @[Debug.scala:1183:34, :1185:39] wire [2:0] _out_T_1225; // @[RegisterRouter.scala:87:24] wire [2:0] ABSTRACTCSWrData_cmderr; // @[Debug.scala:1184:39] wire abstractCommandBusy; // @[Debug.scala:1220:39] wire ABSTRACTCSRdData_busy; // @[Debug.scala:1185:39] wire out_f_woready_111; // @[RegisterRouter.scala:87:24] wire ABSTRACTCSWrEnMaybe; // @[Debug.scala:1188:39] wire _ABSTRACTCSWrEnLegal_T; // @[Debug.scala:1742:44] wire ABSTRACTCSWrEnLegal; // @[Debug.scala:1190:39] wire ABSTRACTCSWrEn = ABSTRACTCSWrEnMaybe & ABSTRACTCSWrEnLegal; // @[Debug.scala:1188:39, :1190:39, :1191:51] wire _errorBusy_T_16; // @[Debug.scala:1752:74] wire errorBusy; // @[Debug.scala:1195:36] wire errorException; // @[Debug.scala:1196:36] wire errorUnsupported; // @[Debug.scala:1197:36] wire errorHaltResume; // @[Debug.scala:1198:36] wire [2:0] _ABSTRACTCSReg_cmderr_T = ~ABSTRACTCSWrData_cmderr; // @[Debug.scala:1184:39, :1214:58] wire [2:0] _ABSTRACTCSReg_cmderr_T_1 = ABSTRACTCSReg_cmderr & _ABSTRACTCSReg_cmderr_T; // @[Debug.scala:1183:34, :1214:{56,58}] wire _abstractCommandBusy_T; // @[Debug.scala:1740:42] assign ABSTRACTCSRdData_busy = abstractCommandBusy; // @[Debug.scala:1185:39, :1220:39] reg [15:0] ABSTRACTAUTOReg_autoexecprogbuf; // @[Debug.scala:1235:36] wire [15:0] ABSTRACTAUTORdData_autoexecprogbuf = ABSTRACTAUTOReg_autoexecprogbuf; // @[Debug.scala:1235:36, :1237:41] reg [11:0] ABSTRACTAUTOReg_autoexecdata; // @[Debug.scala:1235:36] wire [11:0] ABSTRACTAUTORdData_autoexecdata = ABSTRACTAUTOReg_autoexecdata; // @[Debug.scala:1235:36, :1237:41] wire [15:0] _out_T_642; // @[RegisterRouter.scala:87:24] wire [15:0] _ABSTRACTAUTOReg_autoexecprogbuf_T = ABSTRACTAUTOWrData_autoexecprogbuf; // @[Debug.scala:1236:41, :1249:79] wire [11:0] ABSTRACTAUTOWrData_autoexecdata; // @[Debug.scala:1236:41] wire [11:0] _out_T_631 = ABSTRACTAUTORdData_autoexecdata; // @[RegisterRouter.scala:87:24] wire out_f_woready_52; // @[RegisterRouter.scala:87:24] wire autoexecdataWrEnMaybe; // @[Debug.scala:1240:41] wire out_f_woready_54; // @[RegisterRouter.scala:87:24] wire autoexecprogbufWrEnMaybe; // @[Debug.scala:1241:44] wire _ABSTRACTAUTOWrEnLegal_T; // @[Debug.scala:1744:44] wire ABSTRACTAUTOWrEnLegal; // @[Debug.scala:1243:41] wire [11:0] _ABSTRACTAUTOReg_autoexecdata_T = {4'h0, ABSTRACTAUTOWrData_autoexecdata[7:0]}; // @[Debug.scala:1236:41, :1252:73] wire dmiAbstractDataAccessVec_0; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_1; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_2; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_3; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_4; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_5; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_6; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_7; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_8; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_9; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_10; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_11; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_12; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_13; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_14; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_15; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_16; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_17; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_18; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_19; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_20; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_21; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_22; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_23; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_24; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_25; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_26; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_27; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_28; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_29; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_30; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_31; // @[Debug.scala:1257:45] assign dmiAbstractDataAccessVec_0 = dmiAbstractDataWrEnMaybe_0 \| dmiAbstractDataRdEn_0; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_1 = dmiAbstractDataWrEnMaybe_1 \| dmiAbstractDataRdEn_1; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_2 = dmiAbstractDataWrEnMaybe_2 \| dmiAbstractDataRdEn_2; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_3 = dmiAbstractDataWrEnMaybe_3 \| dmiAbstractDataRdEn_3; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_4 = dmiAbstractDataWrEnMaybe_4 \| dmiAbstractDataRdEn_4; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_5 = dmiAbstractDataWrEnMaybe_5 \| dmiAbstractDataRdEn_5; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_6 = dmiAbstractDataWrEnMaybe_6 \| dmiAbstractDataRdEn_6; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_7 = dmiAbstractDataWrEnMaybe_7 \| dmiAbstractDataRdEn_7; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_8 = dmiAbstractDataWrEnMaybe_8 \| dmiAbstractDataRdEn_8; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_9 = dmiAbstractDataWrEnMaybe_9 \| dmiAbstractDataRdEn_9; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_10 = dmiAbstractDataWrEnMaybe_10 \| dmiAbstractDataRdEn_10; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_11 = dmiAbstractDataWrEnMaybe_11 \| dmiAbstractDataRdEn_11; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_12 = dmiAbstractDataWrEnMaybe_12 \| dmiAbstractDataRdEn_12; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_13 = dmiAbstractDataWrEnMaybe_13 \| dmiAbstractDataRdEn_13; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_14 = dmiAbstractDataWrEnMaybe_14 \| dmiAbstractDataRdEn_14; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_15 = dmiAbstractDataWrEnMaybe_15 \| dmiAbstractDataRdEn_15; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_16 = dmiAbstractDataWrEnMaybe_16 \| dmiAbstractDataRdEn_16; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_17 = dmiAbstractDataWrEnMaybe_17 \| dmiAbstractDataRdEn_17; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_18 = dmiAbstractDataWrEnMaybe_18 \| dmiAbstractDataRdEn_18; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_19 = dmiAbstractDataWrEnMaybe_19 \| dmiAbstractDataRdEn_19; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_20 = dmiAbstractDataWrEnMaybe_20 \| dmiAbstractDataRdEn_20; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_21 = dmiAbstractDataWrEnMaybe_21 \| dmiAbstractDataRdEn_21; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_22 = dmiAbstractDataWrEnMaybe_22 \| dmiAbstractDataRdEn_22; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_23 = dmiAbstractDataWrEnMaybe_23 \| dmiAbstractDataRdEn_23; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_24 = dmiAbstractDataWrEnMaybe_24 \| dmiAbstractDataRdEn_24; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_25 = dmiAbstractDataWrEnMaybe_25 \| dmiAbstractDataRdEn_25; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_26 = dmiAbstractDataWrEnMaybe_26 \| dmiAbstractDataRdEn_26; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_27 = dmiAbstractDataWrEnMaybe_27 \| dmiAbstractDataRdEn_27; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_28 = dmiAbstractDataWrEnMaybe_28 \| dmiAbstractDataRdEn_28; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_29 = dmiAbstractDataWrEnMaybe_29 \| dmiAbstractDataRdEn_29; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_30 = dmiAbstractDataWrEnMaybe_30 \| dmiAbstractDataRdEn_30; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_31 = dmiAbstractDataWrEnMaybe_31 \| dmiAbstractDataRdEn_31; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] wire dmiProgramBufferAccessVec_0; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_1; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_2; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_3; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_4; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_5; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_6; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_7; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_8; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_9; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_10; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_11; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_12; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_13; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_14; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_15; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_16; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_17; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_18; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_19; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_20; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_21; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_22; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_23; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_24; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_25; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_26; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_27; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_28; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_29; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_30; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_31; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_32; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_33; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_34; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_35; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_36; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_37; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_38; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_39; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_40; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_41; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_42; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_43; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_44; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_45; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_46; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_47; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_48; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_49; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_50; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_51; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_52; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_53; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_54; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_55; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_56; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_57; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_58; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_59; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_60; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_61; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_62; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_63; // @[Debug.scala:1260:46] assign dmiProgramBufferAccessVec_0 = dmiProgramBufferWrEnMaybe_0 \| dmiProgramBufferRdEn_0; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_1 = dmiProgramBufferWrEnMaybe_1 \| dmiProgramBufferRdEn_1; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_2 = dmiProgramBufferWrEnMaybe_2 \| dmiProgramBufferRdEn_2; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_3 = dmiProgramBufferWrEnMaybe_3 \| dmiProgramBufferRdEn_3; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_4 = dmiProgramBufferWrEnMaybe_4 \| dmiProgramBufferRdEn_4; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_5 = dmiProgramBufferWrEnMaybe_5 \| dmiProgramBufferRdEn_5; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_6 = dmiProgramBufferWrEnMaybe_6 \| dmiProgramBufferRdEn_6; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_7 = dmiProgramBufferWrEnMaybe_7 \| dmiProgramBufferRdEn_7; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_8 = dmiProgramBufferWrEnMaybe_8 \| dmiProgramBufferRdEn_8; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_9 = dmiProgramBufferWrEnMaybe_9 \| dmiProgramBufferRdEn_9; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_10 = dmiProgramBufferWrEnMaybe_10 \| dmiProgramBufferRdEn_10; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_11 = dmiProgramBufferWrEnMaybe_11 \| dmiProgramBufferRdEn_11; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_12 = dmiProgramBufferWrEnMaybe_12 \| dmiProgramBufferRdEn_12; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_13 = dmiProgramBufferWrEnMaybe_13 \| dmiProgramBufferRdEn_13; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_14 = dmiProgramBufferWrEnMaybe_14 \| dmiProgramBufferRdEn_14; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_15 = dmiProgramBufferWrEnMaybe_15 \| dmiProgramBufferRdEn_15; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_16 = dmiProgramBufferWrEnMaybe_16 \| dmiProgramBufferRdEn_16; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_17 = dmiProgramBufferWrEnMaybe_17 \| dmiProgramBufferRdEn_17; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_18 = dmiProgramBufferWrEnMaybe_18 \| dmiProgramBufferRdEn_18; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_19 = dmiProgramBufferWrEnMaybe_19 \| dmiProgramBufferRdEn_19; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_20 = dmiProgramBufferWrEnMaybe_20 \| dmiProgramBufferRdEn_20; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_21 = dmiProgramBufferWrEnMaybe_21 \| dmiProgramBufferRdEn_21; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_22 = dmiProgramBufferWrEnMaybe_22 \| dmiProgramBufferRdEn_22; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_23 = dmiProgramBufferWrEnMaybe_23 \| dmiProgramBufferRdEn_23; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_24 = dmiProgramBufferWrEnMaybe_24 \| dmiProgramBufferRdEn_24; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_25 = dmiProgramBufferWrEnMaybe_25 \| dmiProgramBufferRdEn_25; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_26 = dmiProgramBufferWrEnMaybe_26 \| dmiProgramBufferRdEn_26; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_27 = dmiProgramBufferWrEnMaybe_27 \| dmiProgramBufferRdEn_27; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_28 = dmiProgramBufferWrEnMaybe_28 \| dmiProgramBufferRdEn_28; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_29 = dmiProgramBufferWrEnMaybe_29 \| dmiProgramBufferRdEn_29; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_30 = dmiProgramBufferWrEnMaybe_30 \| dmiProgramBufferRdEn_30; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_31 = dmiProgramBufferWrEnMaybe_31 \| dmiProgramBufferRdEn_31; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_32 = dmiProgramBufferWrEnMaybe_32 \| dmiProgramBufferRdEn_32; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_33 = dmiProgramBufferWrEnMaybe_33 \| dmiProgramBufferRdEn_33; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_34 = dmiProgramBufferWrEnMaybe_34 \| dmiProgramBufferRdEn_34; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_35 = dmiProgramBufferWrEnMaybe_35 \| dmiProgramBufferRdEn_35; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_36 = dmiProgramBufferWrEnMaybe_36 \| dmiProgramBufferRdEn_36; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_37 = dmiProgramBufferWrEnMaybe_37 \| dmiProgramBufferRdEn_37; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_38 = dmiProgramBufferWrEnMaybe_38 \| dmiProgramBufferRdEn_38; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_39 = dmiProgramBufferWrEnMaybe_39 \| dmiProgramBufferRdEn_39; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_40 = dmiProgramBufferWrEnMaybe_40 \| dmiProgramBufferRdEn_40; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_41 = dmiProgramBufferWrEnMaybe_41 \| dmiProgramBufferRdEn_41; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_42 = dmiProgramBufferWrEnMaybe_42 \| dmiProgramBufferRdEn_42; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_43 = dmiProgramBufferWrEnMaybe_43 \| dmiProgramBufferRdEn_43; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_44 = dmiProgramBufferWrEnMaybe_44 \| dmiProgramBufferRdEn_44; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_45 = dmiProgramBufferWrEnMaybe_45 \| dmiProgramBufferRdEn_45; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_46 = dmiProgramBufferWrEnMaybe_46 \| dmiProgramBufferRdEn_46; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_47 = dmiProgramBufferWrEnMaybe_47 \| dmiProgramBufferRdEn_47; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_48 = dmiProgramBufferWrEnMaybe_48 \| dmiProgramBufferRdEn_48; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_49 = dmiProgramBufferWrEnMaybe_49 \| dmiProgramBufferRdEn_49; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_50 = dmiProgramBufferWrEnMaybe_50 \| dmiProgramBufferRdEn_50; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_51 = dmiProgramBufferWrEnMaybe_51 \| dmiProgramBufferRdEn_51; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_52 = dmiProgramBufferWrEnMaybe_52 \| dmiProgramBufferRdEn_52; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_53 = dmiProgramBufferWrEnMaybe_53 \| dmiProgramBufferRdEn_53; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_54 = dmiProgramBufferWrEnMaybe_54 \| dmiProgramBufferRdEn_54; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_55 = dmiProgramBufferWrEnMaybe_55 \| dmiProgramBufferRdEn_55; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_56 = dmiProgramBufferWrEnMaybe_56 \| dmiProgramBufferRdEn_56; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_57 = dmiProgramBufferWrEnMaybe_57 \| dmiProgramBufferRdEn_57; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_58 = dmiProgramBufferWrEnMaybe_58 \| dmiProgramBufferRdEn_58; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_59 = dmiProgramBufferWrEnMaybe_59 \| dmiProgramBufferRdEn_59; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_60 = dmiProgramBufferWrEnMaybe_60 \| dmiProgramBufferRdEn_60; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_61 = dmiProgramBufferWrEnMaybe_61 \| dmiProgramBufferRdEn_61; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_62 = dmiProgramBufferWrEnMaybe_62 \| dmiProgramBufferRdEn_62; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_63 = dmiProgramBufferWrEnMaybe_63 \| dmiProgramBufferRdEn_63; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] wire _dmiAbstractDataAccess_T = dmiAbstractDataAccessVec_0 \| dmiAbstractDataAccessVec_1; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_1 = _dmiAbstractDataAccess_T \| dmiAbstractDataAccessVec_2; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_2 = _dmiAbstractDataAccess_T_1 \| dmiAbstractDataAccessVec_3; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_3 = _dmiAbstractDataAccess_T_2 \| dmiAbstractDataAccessVec_4; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_4 = _dmiAbstractDataAccess_T_3 \| dmiAbstractDataAccessVec_5; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_5 = _dmiAbstractDataAccess_T_4 \| dmiAbstractDataAccessVec_6; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_6 = _dmiAbstractDataAccess_T_5 \| dmiAbstractDataAccessVec_7; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_7 = _dmiAbstractDataAccess_T_6 \| dmiAbstractDataAccessVec_8; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_8 = _dmiAbstractDataAccess_T_7 \| dmiAbstractDataAccessVec_9; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_9 = _dmiAbstractDataAccess_T_8 \| dmiAbstractDataAccessVec_10; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_10 = _dmiAbstractDataAccess_T_9 \| dmiAbstractDataAccessVec_11; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_11 = _dmiAbstractDataAccess_T_10 \| dmiAbstractDataAccessVec_12; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_12 = _dmiAbstractDataAccess_T_11 \| dmiAbstractDataAccessVec_13; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_13 = _dmiAbstractDataAccess_T_12 \| dmiAbstractDataAccessVec_14; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_14 = _dmiAbstractDataAccess_T_13 \| dmiAbstractDataAccessVec_15; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_15 = _dmiAbstractDataAccess_T_14 \| dmiAbstractDataAccessVec_16; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_16 = _dmiAbstractDataAccess_T_15 \| dmiAbstractDataAccessVec_17; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_17 = _dmiAbstractDataAccess_T_16 \| dmiAbstractDataAccessVec_18; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_18 = _dmiAbstractDataAccess_T_17 \| dmiAbstractDataAccessVec_19; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_19 = _dmiAbstractDataAccess_T_18 \| dmiAbstractDataAccessVec_20; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_20 = _dmiAbstractDataAccess_T_19 \| dmiAbstractDataAccessVec_21; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_21 = _dmiAbstractDataAccess_T_20 \| dmiAbstractDataAccessVec_22; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_22 = _dmiAbstractDataAccess_T_21 \| dmiAbstractDataAccessVec_23; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_23 = _dmiAbstractDataAccess_T_22 \| dmiAbstractDataAccessVec_24; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_24 = _dmiAbstractDataAccess_T_23 \| dmiAbstractDataAccessVec_25; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_25 = _dmiAbstractDataAccess_T_24 \| dmiAbstractDataAccessVec_26; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_26 = _dmiAbstractDataAccess_T_25 \| dmiAbstractDataAccessVec_27; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_27 = _dmiAbstractDataAccess_T_26 \| dmiAbstractDataAccessVec_28; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_28 = _dmiAbstractDataAccess_T_27 \| dmiAbstractDataAccessVec_29; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_29 = _dmiAbstractDataAccess_T_28 \| dmiAbstractDataAccessVec_30; // @[Debug.scala:1257:45, :1263:68] wire dmiAbstractDataAccess = _dmiAbstractDataAccess_T_29 \| dmiAbstractDataAccessVec_31; // @[Debug.scala:1257:45, :1263:68] wire _dmiProgramBufferAccess_T = dmiProgramBufferAccessVec_0 \| dmiProgramBufferAccessVec_1; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_1 = _dmiProgramBufferAccess_T \| dmiProgramBufferAccessVec_2; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_2 = _dmiProgramBufferAccess_T_1 \| dmiProgramBufferAccessVec_3; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_3 = _dmiProgramBufferAccess_T_2 \| dmiProgramBufferAccessVec_4; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_4 = _dmiProgramBufferAccess_T_3 \| dmiProgramBufferAccessVec_5; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_5 = _dmiProgramBufferAccess_T_4 \| dmiProgramBufferAccessVec_6; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_6 = _dmiProgramBufferAccess_T_5 \| dmiProgramBufferAccessVec_7; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_7 = _dmiProgramBufferAccess_T_6 \| dmiProgramBufferAccessVec_8; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_8 = _dmiProgramBufferAccess_T_7 \| dmiProgramBufferAccessVec_9; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_9 = _dmiProgramBufferAccess_T_8 \| dmiProgramBufferAccessVec_10; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_10 = _dmiProgramBufferAccess_T_9 \| dmiProgramBufferAccessVec_11; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_11 = _dmiProgramBufferAccess_T_10 \| dmiProgramBufferAccessVec_12; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_12 = _dmiProgramBufferAccess_T_11 \| dmiProgramBufferAccessVec_13; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_13 = _dmiProgramBufferAccess_T_12 \| dmiProgramBufferAccessVec_14; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_14 = _dmiProgramBufferAccess_T_13 \| dmiProgramBufferAccessVec_15; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_15 = _dmiProgramBufferAccess_T_14 \| dmiProgramBufferAccessVec_16; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_16 = _dmiProgramBufferAccess_T_15 \| dmiProgramBufferAccessVec_17; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_17 = _dmiProgramBufferAccess_T_16 \| dmiProgramBufferAccessVec_18; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_18 = _dmiProgramBufferAccess_T_17 \| dmiProgramBufferAccessVec_19; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_19 = _dmiProgramBufferAccess_T_18 \| dmiProgramBufferAccessVec_20; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_20 = _dmiProgramBufferAccess_T_19 \| dmiProgramBufferAccessVec_21; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_21 = _dmiProgramBufferAccess_T_20 \| dmiProgramBufferAccessVec_22; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_22 = _dmiProgramBufferAccess_T_21 \| dmiProgramBufferAccessVec_23; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_23 = _dmiProgramBufferAccess_T_22 \| dmiProgramBufferAccessVec_24; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_24 = _dmiProgramBufferAccess_T_23 \| dmiProgramBufferAccessVec_25; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_25 = _dmiProgramBufferAccess_T_24 \| dmiProgramBufferAccessVec_26; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_26 = _dmiProgramBufferAccess_T_25 \| dmiProgramBufferAccessVec_27; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_27 = _dmiProgramBufferAccess_T_26 \| dmiProgramBufferAccessVec_28; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_28 = _dmiProgramBufferAccess_T_27 \| dmiProgramBufferAccessVec_29; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_29 = _dmiProgramBufferAccess_T_28 \| dmiProgramBufferAccessVec_30; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_30 = _dmiProgramBufferAccess_T_29 \| dmiProgramBufferAccessVec_31; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_31 = _dmiProgramBufferAccess_T_30 \| dmiProgramBufferAccessVec_32; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_32 = _dmiProgramBufferAccess_T_31 \| dmiProgramBufferAccessVec_33; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_33 = _dmiProgramBufferAccess_T_32 \| dmiProgramBufferAccessVec_34; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_34 = _dmiProgramBufferAccess_T_33 \| dmiProgramBufferAccessVec_35; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_35 = _dmiProgramBufferAccess_T_34 \| dmiProgramBufferAccessVec_36; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_36 = _dmiProgramBufferAccess_T_35 \| dmiProgramBufferAccessVec_37; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_37 = _dmiProgramBufferAccess_T_36 \| dmiProgramBufferAccessVec_38; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_38 = _dmiProgramBufferAccess_T_37 \| dmiProgramBufferAccessVec_39; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_39 = _dmiProgramBufferAccess_T_38 \| dmiProgramBufferAccessVec_40; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_40 = _dmiProgramBufferAccess_T_39 \| dmiProgramBufferAccessVec_41; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_41 = _dmiProgramBufferAccess_T_40 \| dmiProgramBufferAccessVec_42; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_42 = _dmiProgramBufferAccess_T_41 \| dmiProgramBufferAccessVec_43; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_43 = _dmiProgramBufferAccess_T_42 \| dmiProgramBufferAccessVec_44; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_44 = _dmiProgramBufferAccess_T_43 \| dmiProgramBufferAccessVec_45; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_45 = _dmiProgramBufferAccess_T_44 \| dmiProgramBufferAccessVec_46; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_46 = _dmiProgramBufferAccess_T_45 \| dmiProgramBufferAccessVec_47; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_47 = _dmiProgramBufferAccess_T_46 \| dmiProgramBufferAccessVec_48; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_48 = _dmiProgramBufferAccess_T_47 \| dmiProgramBufferAccessVec_49; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_49 = _dmiProgramBufferAccess_T_48 \| dmiProgramBufferAccessVec_50; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_50 = _dmiProgramBufferAccess_T_49 \| dmiProgramBufferAccessVec_51; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_51 = _dmiProgramBufferAccess_T_50 \| dmiProgramBufferAccessVec_52; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_52 = _dmiProgramBufferAccess_T_51 \| dmiProgramBufferAccessVec_53; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_53 = _dmiProgramBufferAccess_T_52 \| dmiProgramBufferAccessVec_54; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_54 = _dmiProgramBufferAccess_T_53 \| dmiProgramBufferAccessVec_55; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_55 = _dmiProgramBufferAccess_T_54 \| dmiProgramBufferAccessVec_56; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_56 = _dmiProgramBufferAccess_T_55 \| dmiProgramBufferAccessVec_57; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_57 = _dmiProgramBufferAccess_T_56 \| dmiProgramBufferAccessVec_58; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_58 = _dmiProgramBufferAccess_T_57 \| dmiProgramBufferAccessVec_59; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_59 = _dmiProgramBufferAccess_T_58 \| dmiProgramBufferAccessVec_60; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_60 = _dmiProgramBufferAccess_T_59 \| dmiProgramBufferAccessVec_61; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_61 = _dmiProgramBufferAccess_T_60 \| dmiProgramBufferAccessVec_62; // @[Debug.scala:1260:46, :1264:69] wire dmiProgramBufferAccess = _dmiProgramBufferAccess_T_61 \| dmiProgramBufferAccessVec_63; // @[Debug.scala:1260:46, :1264:69] wire _autoexecData_0_T; // @[Debug.scala:1269:140] wire _autoexecData_1_T; // @[Debug.scala:1269:140] wire _autoexecData_2_T; // @[Debug.scala:1269:140] wire _autoexecData_3_T; // @[Debug.scala:1269:140] wire _autoexecData_4_T; // @[Debug.scala:1269:140] wire _autoexecData_5_T; // @[Debug.scala:1269:140] wire _autoexecData_6_T; // @[Debug.scala:1269:140] wire _autoexecData_7_T; // @[Debug.scala:1269:140] wire autoexecData_0; // @[Debug.scala:1267:33] wire autoexecData_1; // @[Debug.scala:1267:33] wire autoexecData_2; // @[Debug.scala:1267:33] wire autoexecData_3; // @[Debug.scala:1267:33] wire autoexecData_4; // @[Debug.scala:1267:33] wire autoexecData_5; // @[Debug.scala:1267:33] wire autoexecData_6; // @[Debug.scala:1267:33] wire autoexecData_7; // @[Debug.scala:1267:33] wire _autoexecProg_0_T; // @[Debug.scala:1270:144] wire _autoexecProg_1_T; // @[Debug.scala:1270:144] wire _autoexecProg_2_T; // @[Debug.scala:1270:144] wire _autoexecProg_3_T; // @[Debug.scala:1270:144] wire _autoexecProg_4_T; // @[Debug.scala:1270:144] wire _autoexecProg_5_T; // @[Debug.scala:1270:144] wire _autoexecProg_6_T; // @[Debug.scala:1270:144] wire _autoexecProg_7_T; // @[Debug.scala:1270:144] wire _autoexecProg_8_T; // @[Debug.scala:1270:144] wire _autoexecProg_9_T; // @[Debug.scala:1270:144] wire _autoexecProg_10_T; // @[Debug.scala:1270:144] wire _autoexecProg_11_T; // @[Debug.scala:1270:144] wire _autoexecProg_12_T; // @[Debug.scala:1270:144] wire _autoexecProg_13_T; // @[Debug.scala:1270:144] wire _autoexecProg_14_T; // @[Debug.scala:1270:144] wire _autoexecProg_15_T; // @[Debug.scala:1270:144] wire autoexecProg_0; // @[Debug.scala:1268:33] wire autoexecProg_1; // @[Debug.scala:1268:33] wire autoexecProg_2; // @[Debug.scala:1268:33] wire autoexecProg_3; // @[Debug.scala:1268:33] wire autoexecProg_4; // @[Debug.scala:1268:33] wire autoexecProg_5; // @[Debug.scala:1268:33] wire autoexecProg_6; // @[Debug.scala:1268:33] wire autoexecProg_7; // @[Debug.scala:1268:33] wire autoexecProg_8; // @[Debug.scala:1268:33] wire autoexecProg_9; // @[Debug.scala:1268:33] wire autoexecProg_10; // @[Debug.scala:1268:33] wire autoexecProg_11; // @[Debug.scala:1268:33] wire autoexecProg_12; // @[Debug.scala:1268:33] wire autoexecProg_13; // @[Debug.scala:1268:33] wire autoexecProg_14; // @[Debug.scala:1268:33] wire autoexecProg_15; // @[Debug.scala:1268:33] assign _autoexecData_0_T = dmiAbstractDataAccessVec_0 & ABSTRACTAUTOReg_autoexecdata[0]; // @[Debug.scala:1235:36, :1257:45, :1269:{54,140}] assign autoexecData_0 = _autoexecData_0_T; // @[Debug.scala:1267:33, :1269:140] assign _autoexecData_1_T = dmiAbstractDataAccessVec_4 & ABSTRACTAUTOReg_autoexecdata[1]; // @[Debug.scala:1235:36, :1257:45, :1269:{54,140}] assign autoexecData_1 = _autoexecData_1_T; // @[Debug.scala:1267:33, :1269:140] assign _autoexecData_2_T = dmiAbstractDataAccessVec_8 & ABSTRACTAUTOReg_autoexecdata[2]; // @[Debug.scala:1235:36, :1257:45, :1269:{54,140}] assign autoexecData_2 = _autoexecData_2_T; // @[Debug.scala:1267:33, :1269:140] assign _autoexecData_3_T = dmiAbstractDataAccessVec_12 & ABSTRACTAUTOReg_autoexecdata[3]; // @[Debug.scala:1235:36, :1257:45, :1269:{54,140}] assign autoexecData_3 = _autoexecData_3_T; // @[Debug.scala:1267:33, :1269:140] assign _autoexecData_4_T = dmiAbstractDataAccessVec_16 & ABSTRACTAUTOReg_autoexecdata[4]; // @[Debug.scala:1235:36, :1257:45, :1269:{54,140}] assign autoexecData_4 = _autoexecData_4_T; // @[Debug.scala:1267:33, :1269:140] assign _autoexecData_5_T = dmiAbstractDataAccessVec_20 & ABSTRACTAUTOReg_autoexecdata[5]; // @[Debug.scala:1235:36, :1257:45, :1269:{54,140}] assign autoexecData_5 = _autoexecData_5_T; // @[Debug.scala:1267:33, :1269:140] assign _autoexecData_6_T = dmiAbstractDataAccessVec_24 & ABSTRACTAUTOReg_autoexecdata[6]; // @[Debug.scala:1235:36, :1257:45, :1269:{54,140}] assign autoexecData_6 = _autoexecData_6_T; // @[Debug.scala:1267:33, :1269:140] assign _autoexecData_7_T = dmiAbstractDataAccessVec_28 & ABSTRACTAUTOReg_autoexecdata[7]; // @[Debug.scala:1235:36, :1257:45, :1269:{54,140}] assign autoexecData_7 = _autoexecData_7_T; // @[Debug.scala:1267:33, :1269:140] assign _autoexecProg_0_T = dmiProgramBufferAccessVec_0 & ABSTRACTAUTOReg_autoexecprogbuf[0]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}] assign autoexecProg_0 = _autoexecProg_0_T; // @[Debug.scala:1268:33, :1270:144] assign _autoexecProg_1_T = dmiProgramBufferAccessVec_4 & ABSTRACTAUTOReg_autoexecprogbuf[1]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}] assign autoexecProg_1 = _autoexecProg_1_T; // @[Debug.scala:1268:33, :1270:144] assign _autoexecProg_2_T = dmiProgramBufferAccessVec_8 & ABSTRACTAUTOReg_autoexecprogbuf[2]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}] assign autoexecProg_2 = _autoexecProg_2_T; // @[Debug.scala:1268:33, :1270:144] assign _autoexecProg_3_T = dmiProgramBufferAccessVec_12 & ABSTRACTAUTOReg_autoexecprogbuf[3]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}] assign autoexecProg_3 = _autoexecProg_3_T; // @[Debug.scala:1268:33, :1270:144] assign _autoexecProg_4_T = dmiProgramBufferAccessVec_16 & ABSTRACTAUTOReg_autoexecprogbuf[4]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}] assign autoexecProg_4 = _autoexecProg_4_T; // @[Debug.scala:1268:33, :1270:144] assign _autoexecProg_5_T = dmiProgramBufferAccessVec_20 & ABSTRACTAUTOReg_autoexecprogbuf[5]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}] assign autoexecProg_5 = _autoexecProg_5_T; // @[Debug.scala:1268:33, :1270:144] assign _autoexecProg_6_T = dmiProgramBufferAccessVec_24 & ABSTRACTAUTOReg_autoexecprogbuf[6]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}] assign autoexecProg_6 = _autoexecProg_6_T; // @[Debug.scala:1268:33, :1270:144] assign _autoexecProg_7_T = dmiProgramBufferAccessVec_28 & ABSTRACTAUTOReg_autoexecprogbuf[7]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}] assign autoexecProg_7 = _autoexecProg_7_T; // @[Debug.scala:1268:33, :1270:144] assign _autoexecProg_8_T = dmiProgramBufferAccessVec_32 & ABSTRACTAUTOReg_autoexecprogbuf[8]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}] assign autoexecProg_8 = _autoexecProg_8_T; // @[Debug.scala:1268:33, :1270:144] assign _autoexecProg_9_T = dmiProgramBufferAccessVec_36 & ABSTRACTAUTOReg_autoexecprogbuf[9]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}] assign autoexecProg_9 = _autoexecProg_9_T; // @[Debug.scala:1268:33, :1270:144] assign _autoexecProg_10_T = dmiProgramBufferAccessVec_40 & ABSTRACTAUTOReg_autoexecprogbuf[10]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}] assign autoexecProg_10 = _autoexecProg_10_T; // @[Debug.scala:1268:33, :1270:144] assign _autoexecProg_11_T = dmiProgramBufferAccessVec_44 & ABSTRACTAUTOReg_autoexecprogbuf[11]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}] assign autoexecProg_11 = _autoexecProg_11_T; // @[Debug.scala:1268:33, :1270:144] assign _autoexecProg_12_T = dmiProgramBufferAccessVec_48 & ABSTRACTAUTOReg_autoexecprogbuf[12]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}] assign autoexecProg_12 = _autoexecProg_12_T; // @[Debug.scala:1268:33, :1270:144] assign _autoexecProg_13_T = dmiProgramBufferAccessVec_52 & ABSTRACTAUTOReg_autoexecprogbuf[13]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}] assign autoexecProg_13 = _autoexecProg_13_T; // @[Debug.scala:1268:33, :1270:144] assign _autoexecProg_14_T = dmiProgramBufferAccessVec_56 & ABSTRACTAUTOReg_autoexecprogbuf[14]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}] assign autoexecProg_14 = _autoexecProg_14_T; // @[Debug.scala:1268:33, :1270:144] assign _autoexecProg_15_T = dmiProgramBufferAccessVec_60 & ABSTRACTAUTOReg_autoexecprogbuf[15]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}] assign autoexecProg_15 = _autoexecProg_15_T; // @[Debug.scala:1268:33, :1270:144] wire _autoexec_T = autoexecData_0 \| autoexecData_1; // @[Debug.scala:1267:33, :1272:42] wire _autoexec_T_1 = _autoexec_T \| autoexecData_2; // @[Debug.scala:1267:33, :1272:42] wire _autoexec_T_2 = _autoexec_T_1 \| autoexecData_3; // @[Debug.scala:1267:33, :1272:42] wire _autoexec_T_3 = _autoexec_T_2 \| autoexecData_4; // @[Debug.scala:1267:33, :1272:42] wire _autoexec_T_4 = _autoexec_T_3 \| autoexecData_5; // @[Debug.scala:1267:33, :1272:42] wire _autoexec_T_5 = _autoexec_T_4 \| autoexecData_6; // @[Debug.scala:1267:33, :1272:42] wire _autoexec_T_6 = _autoexec_T_5 \| autoexecData_7; // @[Debug.scala:1267:33, :1272:42] wire _autoexec_T_7 = autoexecProg_0 \| autoexecProg_1; // @[Debug.scala:1268:33, :1272:73] wire _autoexec_T_8 = _autoexec_T_7 \| autoexecProg_2; // @[Debug.scala:1268:33, :1272:73] wire _autoexec_T_9 = _autoexec_T_8 \| autoexecProg_3; // @[Debug.scala:1268:33, :1272:73] wire _autoexec_T_10 = _autoexec_T_9 \| autoexecProg_4; // @[Debug.scala:1268:33, :1272:73] wire _autoexec_T_11 = _autoexec_T_10 \| autoexecProg_5; // @[Debug.scala:1268:33, :1272:73] wire _autoexec_T_12 = _autoexec_T_11 \| autoexecProg_6; // @[Debug.scala:1268:33, :1272:73] wire _autoexec_T_13 = _autoexec_T_12 \| autoexecProg_7; // @[Debug.scala:1268:33, :1272:73] wire _autoexec_T_14 = _autoexec_T_13 \| autoexecProg_8; // @[Debug.scala:1268:33, :1272:73] wire _autoexec_T_15 = _autoexec_T_14 \| autoexecProg_9; // @[Debug.scala:1268:33, :1272:73] wire _autoexec_T_16 = _autoexec_T_15 \| autoexecProg_10; // @[Debug.scala:1268:33, :1272:73] wire _autoexec_T_17 = _autoexec_T_16 \| autoexecProg_11; // @[Debug.scala:1268:33, :1272:73] wire _autoexec_T_18 = _autoexec_T_17 \| autoexecProg_12; // @[Debug.scala:1268:33, :1272:73] wire _autoexec_T_19 = _autoexec_T_18 \| autoexecProg_13; // @[Debug.scala:1268:33, :1272:73] wire _autoexec_T_20 = _autoexec_T_19 \| autoexecProg_14; // @[Debug.scala:1268:33, :1272:73] wire _autoexec_T_21 = _autoexec_T_20 \| autoexecProg_15; // @[Debug.scala:1268:33, :1272:73] wire autoexec = _autoexec_T_6 \| _autoexec_T_21; // @[Debug.scala:1272:{42,48,73}] reg [7:0] COMMANDReg_cmdtype; // @[Debug.scala:1277:25] reg [23:0] COMMANDReg_control; // @[Debug.scala:1277:25] wire [31:0] COMMANDWrDataVal; // @[Debug.scala:1279:39] wire [31:0] _COMMANDWrData_WIRE_1 = COMMANDWrDataVal; // @[Debug.scala:1279:39, :1280:65] wire [7:0] _COMMANDWrData_T_1; // @[Debug.scala:1280:65] wire [23:0] _COMMANDWrData_T; // @[Debug.scala:1280:65] wire [7:0] COMMANDWrData_cmdtype = _COMMANDWrData_WIRE_cmdtype; // @[Debug.scala:1280:{39,65}] wire [23:0] COMMANDWrData_control = _COMMANDWrData_WIRE_control; // @[Debug.scala:1280:{39,65}] assign _COMMANDWrData_T = _COMMANDWrData_WIRE_1[23:0]; // @[Debug.scala:1280:65] assign _COMMANDWrData_WIRE_control = _COMMANDWrData_T; // @[Debug.scala:1280:65] assign _COMMANDWrData_T_1 = _COMMANDWrData_WIRE_1[31:24]; // @[Debug.scala:1280:65] assign _COMMANDWrData_WIRE_cmdtype = _COMMANDWrData_T_1; // @[Debug.scala:1280:65] wire out_f_woready_140; // @[RegisterRouter.scala:87:24] wire COMMANDWrEnMaybe; // @[Debug.scala:1281:39] wire _COMMANDWrEnLegal_T; // @[Debug.scala:1743:44] wire COMMANDWrEnLegal; // @[Debug.scala:1282:39] wire out_f_roready_140; // @[RegisterRouter.scala:87:24] wire COMMANDRdEn; // @[Debug.scala:1283:32] wire COMMANDWrEn = COMMANDWrEnMaybe & COMMANDWrEnLegal; // @[Debug.scala:1281:39, :1282:39, :1285:40] reg [7:0] abstractDataMem_0; // @[Debug.scala:1300:36] wire [7:0] _out_T_308 = abstractDataMem_0; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9474 = abstractDataMem_0; // @[RegisterRouter.scala:87:24] reg [7:0] abstractDataMem_1; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_2; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_3; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_4; // @[Debug.scala:1300:36] wire [7:0] _out_T_77 = abstractDataMem_4; // @[RegisterRouter.scala:87:24] reg [7:0] abstractDataMem_5; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_6; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_7; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_8; // @[Debug.scala:1300:36] wire [7:0] _out_T_761 = abstractDataMem_8; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7912 = abstractDataMem_8; // @[RegisterRouter.scala:87:24] reg [7:0] abstractDataMem_9; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_10; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_11; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_12; // @[Debug.scala:1300:36] wire [7:0] _out_T_1325 = abstractDataMem_12; // @[RegisterRouter.scala:87:24] reg [7:0] abstractDataMem_13; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_14; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_15; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_16; // @[Debug.scala:1300:36] wire [7:0] _out_T_264 = abstractDataMem_16; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10874 = abstractDataMem_16; // @[RegisterRouter.scala:87:24] reg [7:0] abstractDataMem_17; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_18; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_19; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_20; // @[Debug.scala:1300:36] wire [7:0] _out_T_132 = abstractDataMem_20; // @[RegisterRouter.scala:87:24] reg [7:0] abstractDataMem_21; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_22; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_23; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_24; // @[Debug.scala:1300:36] wire [7:0] _out_T_396 = abstractDataMem_24; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2207 = abstractDataMem_24; // @[RegisterRouter.scala:87:24] reg [7:0] abstractDataMem_25; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_26; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_27; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_28; // @[Debug.scala:1300:36] wire [7:0] _out_T_1413 = abstractDataMem_28; // @[RegisterRouter.scala:87:24] reg [7:0] abstractDataMem_29; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_30; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_31; // @[Debug.scala:1300:36] wire [7:0] abstractDataNxt_0; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_1; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_2; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_3; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_4; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_5; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_6; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_7; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_8; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_9; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_10; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_11; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_12; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_13; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_14; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_15; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_16; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_17; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_18; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_19; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_20; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_21; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_22; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_23; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_24; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_25; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_26; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_27; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_28; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_29; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_30; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_31; // @[Debug.scala:1301:41] reg [7:0] programBufferMem_0; // @[Debug.scala:1306:34] wire [7:0] _out_T_1128 = programBufferMem_0; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10426 = programBufferMem_0; // @[RegisterRouter.scala:87:24] reg [7:0] programBufferMem_1; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_2; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_3; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_4; // @[Debug.scala:1306:34] wire [7:0] _out_T_860 = programBufferMem_4; // @[RegisterRouter.scala:87:24] reg [7:0] programBufferMem_5; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_6; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_7; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_8; // @[Debug.scala:1306:34] wire [7:0] _out_T_1172 = programBufferMem_8; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6582 = programBufferMem_8; // @[RegisterRouter.scala:87:24] reg [7:0] programBufferMem_9; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_10; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_11; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_12; // @[Debug.scala:1306:34] wire [7:0] _out_T_220 = programBufferMem_12; // @[RegisterRouter.scala:87:24] reg [7:0] programBufferMem_13; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_14; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_15; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_16; // @[Debug.scala:1306:34] wire [7:0] _out_T_1556 = programBufferMem_16; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3679 = programBufferMem_16; // @[RegisterRouter.scala:87:24] reg [7:0] programBufferMem_17; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_18; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_19; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_20; // @[Debug.scala:1306:34] wire [7:0] _out_T_662 = programBufferMem_20; // @[RegisterRouter.scala:87:24] reg [7:0] programBufferMem_21; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_22; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_23; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_24; // @[Debug.scala:1306:34] wire [7:0] _out_T_816 = programBufferMem_24; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11898 = programBufferMem_24; // @[RegisterRouter.scala:87:24] reg [7:0] programBufferMem_25; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_26; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_27; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_28; // @[Debug.scala:1306:34] wire [7:0] _out_T_1369 = programBufferMem_28; // @[RegisterRouter.scala:87:24] reg [7:0] programBufferMem_29; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_30; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_31; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_32; // @[Debug.scala:1306:34] wire [7:0] _out_T_1501 = programBufferMem_32; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8594 = programBufferMem_32; // @[RegisterRouter.scala:87:24] reg [7:0] programBufferMem_33; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_34; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_35; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_36; // @[Debug.scala:1306:34] wire [7:0] _out_T_176 = programBufferMem_36; // @[RegisterRouter.scala:87:24] reg [7:0] programBufferMem_37; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_38; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_39; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_40; // @[Debug.scala:1306:34] wire [7:0] _out_T_587 = programBufferMem_40; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5954 = programBufferMem_40; // @[RegisterRouter.scala:87:24] reg [7:0] programBufferMem_41; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_42; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_43; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_44; // @[Debug.scala:1306:34] wire [7:0] _out_T_1457 = programBufferMem_44; // @[RegisterRouter.scala:87:24] reg [7:0] programBufferMem_45; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_46; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_47; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_48; // @[Debug.scala:1306:34] wire [7:0] _out_T_1281 = programBufferMem_48; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2943 = programBufferMem_48; // @[RegisterRouter.scala:87:24] reg [7:0] programBufferMem_49; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_50; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_51; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_52; // @[Debug.scala:1306:34] wire [7:0] _out_T_904 = programBufferMem_52; // @[RegisterRouter.scala:87:24] reg [7:0] programBufferMem_53; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_54; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_55; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_56; // @[Debug.scala:1306:34] wire [7:0] _out_T_706 = programBufferMem_56; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12562 = programBufferMem_56; // @[RegisterRouter.scala:87:24] reg [7:0] programBufferMem_57; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_58; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_59; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_60; // @[Debug.scala:1306:34] wire [7:0] _out_T_352 = programBufferMem_60; // @[RegisterRouter.scala:87:24] reg [7:0] programBufferMem_61; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_62; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_63; // @[Debug.scala:1306:34] wire [7:0] programBufferNxt_0; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_1; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_2; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_3; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_4; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_5; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_6; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_7; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_8; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_9; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_10; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_11; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_12; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_13; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_14; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_15; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_16; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_17; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_18; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_19; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_20; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_21; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_22; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_23; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_24; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_25; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_26; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_27; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_28; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_29; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_30; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_31; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_32; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_33; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_34; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_35; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_36; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_37; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_38; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_39; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_40; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_41; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_42; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_43; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_44; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_45; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_46; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_47; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_48; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_49; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_50; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_51; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_52; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_53; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_54; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_55; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_56; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_57; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_58; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_59; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_60; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_61; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_62; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_63; // @[Debug.scala:1307:39] wire _resumeReqRegs_T = ~hartIsInResetSync_0; // @[Debug.scala:948:33, :1320:42] wire _resumeReqRegs_T_1 = resumeReqRegs & _resumeReqRegs_T; // @[Debug.scala:863:31, :1320:{40,42}] wire [1023:0] hartselIndex = 1024'h1 << io_innerCtrl_bits_hartsel_0; // @[OneHot.scala:58:35] wire _haltedBitRegs_T_1 = ~hartIsInResetSync_0; // @[Debug.scala:948:33, :1320:42, :1327:66] wire [1:0] _haltedBitRegs_T_2 = {1'h0, _haltedBitRegs_T[0] & _haltedBitRegs_T_1}; // @[Debug.scala:1327:{43,64,66}] wire _haltedBitRegs_T_5 = ~hartIsInResetSync_0; // @[Debug.scala:948:33, :1320:42, :1330:71] wire _haltedBitRegs_T_7 = ~hartIsInResetSync_0; // @[Debug.scala:948:33, :1320:42, :1333:44] wire _haltedBitRegs_T_8 = haltedBitRegs & _haltedBitRegs_T_7; // @[Debug.scala:861:31, :1333:{42,44}] wire _resumeReqRegs_T_4 = ~hartIsInResetSync_0; // @[Debug.scala:948:33, :1320:42, :1338:71] wire _resumeReqRegs_T_6 = resumeReqRegs \| hamaskWrSel_0; // @[Debug.scala:863:31, :933:31, :1342:43] wire _resumeReqRegs_T_7 = ~hartIsInResetSync_0; // @[Debug.scala:948:33, :1320:42, :1342:67] wire _resumeReqRegs_T_8 = _resumeReqRegs_T_6 & _resumeReqRegs_T_7; // @[Debug.scala:1342:{43,65,67}] wire _resumeAcks_T = ~resumeReqRegs; // @[Debug.scala:863:31, :1349:24] wire _resumeAcks_T_1 = ~hamaskWrSel_0; // @[Debug.scala:933:31, :1017:50, :1349:41] wire _resumeAcks_T_2 = _resumeAcks_T & _resumeAcks_T_1; // @[Debug.scala:1349:{24,39,41}] wire _resumeAcks_T_3 = ~resumeReqRegs; // @[Debug.scala:863:31, :1349:24, :1351:23] assign resumeAcks = resumereq ? _resumeAcks_T_2 : _resumeAcks_T_3; // @[Debug.scala:869:32, :983:39, :1347:24, :1349:{20,39}, :1351:{20,23}] wire _anyAddressWrEn_T_2; // @[SBA.scala:134:54] wire anyAddressWrEn; // @[SBA.scala:42:34] wire _anyDataRdEn_T_2; // @[SBA.scala:176:51] wire anyDataRdEn; // @[SBA.scala:43:34] wire _anyDataWrEn_T_2; // @[SBA.scala:177:51] wire anyDataWrEn; // @[SBA.scala:44:34] reg SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28] wire SBCSRdData_sbbusyerror = SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28, :60:38] reg SBCSFieldsReg_sbbusy; // @[SBA.scala:47:28] reg SBCSFieldsReg_sbreadonaddr; // @[SBA.scala:47:28] wire SBCSRdData_sbreadonaddr = SBCSFieldsReg_sbreadonaddr; // @[SBA.scala:47:28, :60:38] reg [2:0] SBCSFieldsReg_sbaccess; // @[SBA.scala:47:28] wire [2:0] SBCSRdData_sbaccess = SBCSFieldsReg_sbaccess; // @[SBA.scala:47:28, :60:38] reg SBCSFieldsReg_sbautoincrement; // @[SBA.scala:47:28] wire SBCSRdData_sbautoincrement = SBCSFieldsReg_sbautoincrement; // @[SBA.scala:47:28, :60:38] reg SBCSFieldsReg_sbreadondata; // @[SBA.scala:47:28] wire SBCSRdData_sbreadondata = SBCSFieldsReg_sbreadondata; // @[SBA.scala:47:28, :60:38] wire _SBCSFieldsRegReset_sbbusy_T; // @[SBA.scala:51:67] wire SBCSFieldsRegReset_sbbusy; // @[SBA.scala:49:38] assign _SBCSFieldsRegReset_sbbusy_T = \|_sb2tlOpt_io_sbStateOut; // @[SBA.scala:51:67] assign SBCSFieldsRegReset_sbbusy = _SBCSFieldsRegReset_sbbusy_T; // @[SBA.scala:49:38, :51:67] wire sbBusy; // @[SBA.scala:203:46] wire SBCSRdData_sbbusy; // @[SBA.scala:60:38] wire [2:0] SBCSRdData_sberror; // @[SBA.scala:60:38] wire _out_T_549; // @[RegisterRouter.scala:87:24] wire _out_T_529; // @[RegisterRouter.scala:87:24] wire [2:0] _out_T_518; // @[RegisterRouter.scala:87:24] wire _out_T_507; // @[RegisterRouter.scala:87:24] wire _out_T_496; // @[RegisterRouter.scala:87:24] wire [2:0] _out_T_485; // @[RegisterRouter.scala:87:24] wire SBCSWrData_sbbusyerror; // @[SBA.scala:63:38] wire SBCSWrData_sbreadonaddr; // @[SBA.scala:63:38] wire [2:0] SBCSWrData_sbaccess; // @[SBA.scala:63:38] wire SBCSWrData_sbautoincrement; // @[SBA.scala:63:38] wire SBCSWrData_sbreadondata; // @[SBA.scala:63:38] wire [2:0] SBCSWrData_sberror; // @[SBA.scala:63:38] wire out_f_woready_39; // @[RegisterRouter.scala:87:24] wire sberrorWrEn; // @[SBA.scala:65:38] wire out_f_woready_40; // @[RegisterRouter.scala:87:24] wire sbreadondataWrEn; // @[SBA.scala:66:38] wire out_f_woready_41; // @[RegisterRouter.scala:87:24] wire sbautoincrementWrEn; // @[SBA.scala:67:38] wire out_f_woready_42; // @[RegisterRouter.scala:87:24] wire sbaccessWrEn; // @[SBA.scala:68:38] wire out_f_woready_43; // @[RegisterRouter.scala:87:24] wire sbreadonaddrWrEn; // @[SBA.scala:69:38] wire out_f_woready_45; // @[RegisterRouter.scala:87:24] wire sbbusyerrorWrEn; // @[SBA.scala:70:38] reg [31:0] SBADDRESSFieldsReg_0; // @[SBA.scala:104:33] wire [31:0] _out_T_750 = SBADDRESSFieldsReg_0; // @[RegisterRouter.scala:87:24] wire [31:0] SBADDRESSWrData_0; // @[SBA.scala:106:38] wire out_f_roready_63; // @[RegisterRouter.scala:87:24] wire SBADDRESSRdEn_0; // @[SBA.scala:107:38] wire out_f_woready_63; // @[RegisterRouter.scala:87:24] wire _anyAddressWrEn_T = SBADDRESSWrEn_0; // @[SBA.scala:108:38, :134:54] wire [127:0] _autoIncrementedAddr_T_3; // @[SBA.scala:111:60] wire [127:0] autoIncrementedAddr; // @[SBA.scala:110:39] wire [63:0] _GEN_0 = {32'h0, SBADDRESSFieldsReg_0}; // @[SBA.scala:104:33, :111:31] wire [63:0] autoIncrementedAddr_lo; // @[SBA.scala:111:31] assign autoIncrementedAddr_lo = _GEN_0; // @[SBA.scala:111:31] wire [63:0] sb2tlOpt_io_addrIn_lo; // @[SBA.scala:133:10] assign sb2tlOpt_io_addrIn_lo = _GEN_0; // @[SBA.scala:111:31, :133:10] wire [127:0] _autoIncrementedAddr_T = {64'h0, autoIncrementedAddr_lo}; // @[SBA.scala:111:31] wire [7:0] _autoIncrementedAddr_T_1 = 8'h1 << SBCSFieldsReg_sbaccess; // @[SBA.scala:47:28, :111:67] wire [128:0] _autoIncrementedAddr_T_2 = {1'h0, _autoIncrementedAddr_T} + {121'h0, _autoIncrementedAddr_T_1}; // @[SBA.scala:111:{31,60,67}] assign _autoIncrementedAddr_T_3 = _autoIncrementedAddr_T_2[127:0]; // @[SBA.scala:111:60] assign autoIncrementedAddr = _autoIncrementedAddr_T_3; // @[SBA.scala:110:39, :111:60] wire _GEN_1 = SBCSRdData_sberror == 3'h0; // @[SBA.scala:60:38, :119:40] wire _SBADDRESSFieldsReg_0_T; // @[SBA.scala:119:40] assign _SBADDRESSFieldsReg_0_T = _GEN_1; // @[SBA.scala:119:40] wire _SBDATAFieldsReg_0_0_T_4; // @[SBA.scala:160:97] assign _SBDATAFieldsReg_0_0_T_4 = _GEN_1; // @[SBA.scala:119:40, :160:97] wire _SBDATAFieldsReg_0_1_T_4; // @[SBA.scala:160:97] assign _SBDATAFieldsReg_0_1_T_4 = _GEN_1; // @[SBA.scala:119:40, :160:97] wire _SBDATAFieldsReg_0_2_T_4; // @[SBA.scala:160:97] assign _SBDATAFieldsReg_0_2_T_4 = _GEN_1; // @[SBA.scala:119:40, :160:97] wire _SBDATAFieldsReg_0_3_T_4; // @[SBA.scala:160:97] assign _SBDATAFieldsReg_0_3_T_4 = _GEN_1; // @[SBA.scala:119:40, :160:97] wire _SBDATAFieldsReg_1_0_T_4; // @[SBA.scala:160:97] assign _SBDATAFieldsReg_1_0_T_4 = _GEN_1; // @[SBA.scala:119:40, :160:97] wire _SBDATAFieldsReg_1_1_T_4; // @[SBA.scala:160:97] assign _SBDATAFieldsReg_1_1_T_4 = _GEN_1; // @[SBA.scala:119:40, :160:97] wire _SBDATAFieldsReg_1_2_T_4; // @[SBA.scala:160:97] assign _SBDATAFieldsReg_1_2_T_4 = _GEN_1; // @[SBA.scala:119:40, :160:97] wire _SBDATAFieldsReg_1_3_T_4; // @[SBA.scala:160:97] assign _SBDATAFieldsReg_1_3_T_4 = _GEN_1; // @[SBA.scala:119:40, :160:97] wire _sb2tlOpt_io_wrEn_T_5; // @[SBA.scala:199:118] assign _sb2tlOpt_io_wrEn_T_5 = _GEN_1; // @[SBA.scala:119:40, :199:118] wire _sb2tlOpt_io_rdEn_T_5; // @[SBA.scala:200:118] assign _sb2tlOpt_io_rdEn_T_5 = _GEN_1; // @[SBA.scala:119:40, :200:118] wire _SBADDRESSFieldsReg_0_T_1 = SBADDRESSWrEn_0 & _SBADDRESSFieldsReg_0_T; // @[SBA.scala:108:38, :119:{37,40}] wire _SBADDRESSFieldsReg_0_T_2 = ~SBCSFieldsReg_sbbusy; // @[SBA.scala:47:28, :119:63] wire _SBADDRESSFieldsReg_0_T_3 = _SBADDRESSFieldsReg_0_T_1 & _SBADDRESSFieldsReg_0_T_2; // @[SBA.scala:119:{37,60,63}] wire _SBADDRESSFieldsReg_0_T_4 = ~SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28, :119:88] wire _SBADDRESSFieldsReg_0_T_5 = _SBADDRESSFieldsReg_0_T_3 & _SBADDRESSFieldsReg_0_T_4; // @[SBA.scala:119:{60,85,88}] wire _GEN_2 = _sb2tlOpt_io_rdDone \| _sb2tlOpt_io_wrDone; // @[SBA.scala:120:44] wire _SBADDRESSFieldsReg_0_T_6; // @[SBA.scala:120:44] assign _SBADDRESSFieldsReg_0_T_6 = _GEN_2; // @[SBA.scala:120:44] wire _sbErrorReg_0_T_12; // @[SBA.scala:229:54] assign _sbErrorReg_0_T_12 = _GEN_2; // @[SBA.scala:120:44, :229:54] wire _sbErrorReg_1_T_12; // @[SBA.scala:229:54] assign _sbErrorReg_1_T_12 = _GEN_2; // @[SBA.scala:120:44, :229:54] wire _sbErrorReg_2_T_12; // @[SBA.scala:229:54] assign _sbErrorReg_2_T_12 = _GEN_2; // @[SBA.scala:120:44, :229:54] wire _SBADDRESSFieldsReg_0_T_7 = _SBADDRESSFieldsReg_0_T_6 & SBCSFieldsReg_sbautoincrement; // @[SBA.scala:47:28, :120:{44,71}] wire [31:0] _SBADDRESSFieldsReg_0_T_8 = autoIncrementedAddr[31:0]; // @[SBA.scala:110:39, :120:124] wire [31:0] _SBADDRESSFieldsReg_0_T_9 = _SBADDRESSFieldsReg_0_T_7 ? _SBADDRESSFieldsReg_0_T_8 : SBADDRESSFieldsReg_0; // @[SBA.scala:104:33, :120:{19,71,124}] wire [31:0] _SBADDRESSFieldsReg_0_T_10 = _SBADDRESSFieldsReg_0_T_5 ? SBADDRESSWrData_0 : _SBADDRESSFieldsReg_0_T_9; // @[SBA.scala:106:38, :119:{19,85}, :120:19] wire [127:0] _sb2tlOpt_io_addrIn_T_1 = {96'h0, SBADDRESSWrData_0}; // @[SBA.scala:106:38, :132:10] wire [127:0] _sb2tlOpt_io_addrIn_T_2 = {64'h0, sb2tlOpt_io_addrIn_lo}; // @[SBA.scala:133:10] wire [127:0] _sb2tlOpt_io_addrIn_T_3 = SBADDRESSWrEn_0 ? _sb2tlOpt_io_addrIn_T_1 : _sb2tlOpt_io_addrIn_T_2; // @[SBA.scala:108:38, :131:34, :132:10, :133:10] wire _anyAddressWrEn_T_1 = _anyAddressWrEn_T; // @[SBA.scala:134:54] assign _anyAddressWrEn_T_2 = _anyAddressWrEn_T_1; // @[SBA.scala:134:54] assign anyAddressWrEn = _anyAddressWrEn_T_2; // @[SBA.scala:42:34, :134:54] reg [7:0] SBDATAFieldsReg_0_0; // @[SBA.scala:143:30] reg [7:0] SBDATAFieldsReg_0_1; // @[SBA.scala:143:30] reg [7:0] SBDATAFieldsReg_0_2; // @[SBA.scala:143:30] reg [7:0] SBDATAFieldsReg_0_3; // @[SBA.scala:143:30] reg [7:0] SBDATAFieldsReg_1_0; // @[SBA.scala:143:30] reg [7:0] SBDATAFieldsReg_1_1; // @[SBA.scala:143:30] reg [7:0] SBDATAFieldsReg_1_2; // @[SBA.scala:143:30] reg [7:0] SBDATAFieldsReg_1_3; // @[SBA.scala:143:30] wire [31:0] _SBDATARdData_0_T; // @[SBA.scala:165:31] wire [31:0] _SBDATARdData_1_T; // @[SBA.scala:165:31] wire [31:0] _out_T_805 = SBDATARdData_0; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_121 = SBDATARdData_1; // @[RegisterRouter.scala:87:24] wire [31:0] SBDATAWrData_0; // @[SBA.scala:147:35] wire [31:0] SBDATAWrData_1; // @[SBA.scala:147:35] wire out_f_roready_68; // @[RegisterRouter.scala:87:24] wire out_f_roready_4; // @[RegisterRouter.scala:87:24] wire SBDATARdEn_0; // @[SBA.scala:149:35] wire SBDATARdEn_1; // @[SBA.scala:149:35] wire out_f_woready_68; // @[RegisterRouter.scala:87:24] wire _sb2tlOpt_io_wrEn_T = SBDATAWrEn_0; // @[SBA.scala:150:35, :199:49] wire out_f_woready_4; // @[RegisterRouter.scala:87:24] wire SBDATAWrEn_1; // @[SBA.scala:150:35] wire _SBDATAFieldsReg_0_0_T = ~SBCSFieldsReg_sbbusy; // @[SBA.scala:47:28, :119:63, :160:42] wire _SBDATAFieldsReg_0_0_T_1 = SBDATAWrEn_0 & _SBDATAFieldsReg_0_0_T; // @[SBA.scala:150:35, :160:{39,42}] wire _SBDATAFieldsReg_0_0_T_2 = ~SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28, :119:88, :160:67] wire _SBDATAFieldsReg_0_0_T_3 = _SBDATAFieldsReg_0_0_T_1 & _SBDATAFieldsReg_0_0_T_2; // @[SBA.scala:160:{39,64,67}] wire _SBDATAFieldsReg_0_0_T_5 = _SBDATAFieldsReg_0_0_T_3 & _SBDATAFieldsReg_0_0_T_4; // @[SBA.scala:160:{64,94,97}] wire [7:0] _SBDATAFieldsReg_0_0_T_6 = SBDATAWrData_0[7:0]; // @[SBA.scala:147:35, :160:133] wire [7:0] _SBDATAFieldsReg_0_0_T_7 = _sb2tlOpt_io_rdLoad_0 ? _sb2tlOpt_io_dataOut : SBDATAFieldsReg_0_0; // @[SBA.scala:143:30, :161:24] wire [7:0] _SBDATAFieldsReg_0_0_T_8 = _SBDATAFieldsReg_0_0_T_5 ? _SBDATAFieldsReg_0_0_T_6 : _SBDATAFieldsReg_0_0_T_7; // @[SBA.scala:160:{24,94,133}, :161:24] wire _SBDATAFieldsReg_0_1_T = ~SBCSFieldsReg_sbbusy; // @[SBA.scala:47:28, :119:63, :160:42] wire _SBDATAFieldsReg_0_1_T_1 = SBDATAWrEn_0 & _SBDATAFieldsReg_0_1_T; // @[SBA.scala:150:35, :160:{39,42}] wire _SBDATAFieldsReg_0_1_T_2 = ~SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28, :119:88, :160:67] wire _SBDATAFieldsReg_0_1_T_3 = _SBDATAFieldsReg_0_1_T_1 & _SBDATAFieldsReg_0_1_T_2; // @[SBA.scala:160:{39,64,67}] wire _SBDATAFieldsReg_0_1_T_5 = _SBDATAFieldsReg_0_1_T_3 & _SBDATAFieldsReg_0_1_T_4; // @[SBA.scala:160:{64,94,97}] wire [7:0] _SBDATAFieldsReg_0_1_T_6 = SBDATAWrData_0[15:8]; // @[SBA.scala:147:35, :160:133] wire [7:0] _SBDATAFieldsReg_0_1_T_7 = _sb2tlOpt_io_rdLoad_1 ? _sb2tlOpt_io_dataOut : SBDATAFieldsReg_0_1; // @[SBA.scala:143:30, :161:24] wire [7:0] _SBDATAFieldsReg_0_1_T_8 = _SBDATAFieldsReg_0_1_T_5 ? _SBDATAFieldsReg_0_1_T_6 : _SBDATAFieldsReg_0_1_T_7; // @[SBA.scala:160:{24,94,133}, :161:24] wire _SBDATAFieldsReg_0_2_T = ~SBCSFieldsReg_sbbusy; // @[SBA.scala:47:28, :119:63, :160:42] wire _SBDATAFieldsReg_0_2_T_1 = SBDATAWrEn_0 & _SBDATAFieldsReg_0_2_T; // @[SBA.scala:150:35, :160:{39,42}] wire _SBDATAFieldsReg_0_2_T_2 = ~SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28, :119:88, :160:67] wire _SBDATAFieldsReg_0_2_T_3 = _SBDATAFieldsReg_0_2_T_1 & _SBDATAFieldsReg_0_2_T_2; // @[SBA.scala:160:{39,64,67}] wire _SBDATAFieldsReg_0_2_T_5 = _SBDATAFieldsReg_0_2_T_3 & _SBDATAFieldsReg_0_2_T_4; // @[SBA.scala:160:{64,94,97}] wire [7:0] _SBDATAFieldsReg_0_2_T_6 = SBDATAWrData_0[23:16]; // @[SBA.scala:147:35, :160:133] wire [7:0] _SBDATAFieldsReg_0_2_T_7 = _sb2tlOpt_io_rdLoad_2 ? _sb2tlOpt_io_dataOut : SBDATAFieldsReg_0_2; // @[SBA.scala:143:30, :161:24] wire [7:0] _SBDATAFieldsReg_0_2_T_8 = _SBDATAFieldsReg_0_2_T_5 ? _SBDATAFieldsReg_0_2_T_6 : _SBDATAFieldsReg_0_2_T_7; // @[SBA.scala:160:{24,94,133}, :161:24] wire _SBDATAFieldsReg_0_3_T = ~SBCSFieldsReg_sbbusy; // @[SBA.scala:47:28, :119:63, :160:42] wire _SBDATAFieldsReg_0_3_T_1 = SBDATAWrEn_0 & _SBDATAFieldsReg_0_3_T; // @[SBA.scala:150:35, :160:{39,42}] wire _SBDATAFieldsReg_0_3_T_2 = ~SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28, :119:88, :160:67] wire _SBDATAFieldsReg_0_3_T_3 = _SBDATAFieldsReg_0_3_T_1 & _SBDATAFieldsReg_0_3_T_2; // @[SBA.scala:160:{39,64,67}] wire _SBDATAFieldsReg_0_3_T_5 = _SBDATAFieldsReg_0_3_T_3 & _SBDATAFieldsReg_0_3_T_4; // @[SBA.scala:160:{64,94,97}] wire [7:0] _SBDATAFieldsReg_0_3_T_6 = SBDATAWrData_0[31:24]; // @[SBA.scala:147:35, :160:133] wire [7:0] _SBDATAFieldsReg_0_3_T_7 = _sb2tlOpt_io_rdLoad_3 ? _sb2tlOpt_io_dataOut : SBDATAFieldsReg_0_3; // @[SBA.scala:143:30, :161:24] wire [7:0] _SBDATAFieldsReg_0_3_T_8 = _SBDATAFieldsReg_0_3_T_5 ? _SBDATAFieldsReg_0_3_T_6 : _SBDATAFieldsReg_0_3_T_7; // @[SBA.scala:160:{24,94,133}, :161:24] wire [15:0] _GEN_3 = {SBDATAFieldsReg_0_1, SBDATAFieldsReg_0_0}; // @[SBA.scala:143:30, :165:31] wire [15:0] SBDATARdData_0_lo; // @[SBA.scala:165:31] assign SBDATARdData_0_lo = _GEN_3; // @[SBA.scala:165:31] wire [15:0] sb2tlOpt_io_dataIn_lo_lo_lo; // @[SBA.scala:175:85] assign sb2tlOpt_io_dataIn_lo_lo_lo = _GEN_3; // @[SBA.scala:165:31, :175:85] wire [15:0] _GEN_4 = {SBDATAFieldsReg_0_3, SBDATAFieldsReg_0_2}; // @[SBA.scala:143:30, :165:31] wire [15:0] SBDATARdData_0_hi; // @[SBA.scala:165:31] assign SBDATARdData_0_hi = _GEN_4; // @[SBA.scala:165:31] wire [15:0] sb2tlOpt_io_dataIn_lo_lo_hi; // @[SBA.scala:175:85] assign sb2tlOpt_io_dataIn_lo_lo_hi = _GEN_4; // @[SBA.scala:165:31, :175:85] assign _SBDATARdData_0_T = {SBDATARdData_0_hi, SBDATARdData_0_lo}; // @[SBA.scala:165:31] assign SBDATARdData_0 = _SBDATARdData_0_T; // @[SBA.scala:145:35, :165:31] wire _SBDATAFieldsReg_1_0_T = ~SBCSFieldsReg_sbbusy; // @[SBA.scala:47:28, :119:63, :160:42] wire _SBDATAFieldsReg_1_0_T_1 = SBDATAWrEn_1 & _SBDATAFieldsReg_1_0_T; // @[SBA.scala:150:35, :160:{39,42}] wire _SBDATAFieldsReg_1_0_T_2 = ~SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28, :119:88, :160:67] wire _SBDATAFieldsReg_1_0_T_3 = _SBDATAFieldsReg_1_0_T_1 & _SBDATAFieldsReg_1_0_T_2; // @[SBA.scala:160:{39,64,67}] wire _SBDATAFieldsReg_1_0_T_5 = _SBDATAFieldsReg_1_0_T_3 & _SBDATAFieldsReg_1_0_T_4; // @[SBA.scala:160:{64,94,97}] wire [7:0] _SBDATAFieldsReg_1_0_T_6 = SBDATAWrData_1[7:0]; // @[SBA.scala:147:35, :160:133] wire [7:0] _SBDATAFieldsReg_1_0_T_7 = _sb2tlOpt_io_rdLoad_4 ? _sb2tlOpt_io_dataOut : SBDATAFieldsReg_1_0; // @[SBA.scala:143:30, :161:24] wire [7:0] _SBDATAFieldsReg_1_0_T_8 = _SBDATAFieldsReg_1_0_T_5 ? _SBDATAFieldsReg_1_0_T_6 : _SBDATAFieldsReg_1_0_T_7; // @[SBA.scala:160:{24,94,133}, :161:24] wire _SBDATAFieldsReg_1_1_T = ~SBCSFieldsReg_sbbusy; // @[SBA.scala:47:28, :119:63, :160:42] wire _SBDATAFieldsReg_1_1_T_1 = SBDATAWrEn_1 & _SBDATAFieldsReg_1_1_T; // @[SBA.scala:150:35, :160:{39,42}] wire _SBDATAFieldsReg_1_1_T_2 = ~SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28, :119:88, :160:67] wire _SBDATAFieldsReg_1_1_T_3 = _SBDATAFieldsReg_1_1_T_1 & _SBDATAFieldsReg_1_1_T_2; // @[SBA.scala:160:{39,64,67}] wire _SBDATAFieldsReg_1_1_T_5 = _SBDATAFieldsReg_1_1_T_3 & _SBDATAFieldsReg_1_1_T_4; // @[SBA.scala:160:{64,94,97}] wire [7:0] _SBDATAFieldsReg_1_1_T_6 = SBDATAWrData_1[15:8]; // @[SBA.scala:147:35, :160:133] wire [7:0] _SBDATAFieldsReg_1_1_T_7 = _sb2tlOpt_io_rdLoad_5 ? _sb2tlOpt_io_dataOut : SBDATAFieldsReg_1_1; // @[SBA.scala:143:30, :161:24] wire [7:0] _SBDATAFieldsReg_1_1_T_8 = _SBDATAFieldsReg_1_1_T_5 ? _SBDATAFieldsReg_1_1_T_6 : _SBDATAFieldsReg_1_1_T_7; // @[SBA.scala:160:{24,94,133}, :161:24] wire _SBDATAFieldsReg_1_2_T = ~SBCSFieldsReg_sbbusy; // @[SBA.scala:47:28, :119:63, :160:42] wire _SBDATAFieldsReg_1_2_T_1 = SBDATAWrEn_1 & _SBDATAFieldsReg_1_2_T; // @[SBA.scala:150:35, :160:{39,42}] wire _SBDATAFieldsReg_1_2_T_2 = ~SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28, :119:88, :160:67] wire _SBDATAFieldsReg_1_2_T_3 = _SBDATAFieldsReg_1_2_T_1 & _SBDATAFieldsReg_1_2_T_2; // @[SBA.scala:160:{39,64,67}] wire _SBDATAFieldsReg_1_2_T_5 = _SBDATAFieldsReg_1_2_T_3 & _SBDATAFieldsReg_1_2_T_4; // @[SBA.scala:160:{64,94,97}] wire [7:0] _SBDATAFieldsReg_1_2_T_6 = SBDATAWrData_1[23:16]; // @[SBA.scala:147:35, :160:133] wire [7:0] _SBDATAFieldsReg_1_2_T_7 = _sb2tlOpt_io_rdLoad_6 ? _sb2tlOpt_io_dataOut : SBDATAFieldsReg_1_2; // @[SBA.scala:143:30, :161:24] wire [7:0] _SBDATAFieldsReg_1_2_T_8 = _SBDATAFieldsReg_1_2_T_5 ? _SBDATAFieldsReg_1_2_T_6 : _SBDATAFieldsReg_1_2_T_7; // @[SBA.scala:160:{24,94,133}, :161:24] wire _SBDATAFieldsReg_1_3_T = ~SBCSFieldsReg_sbbusy; // @[SBA.scala:47:28, :119:63, :160:42] wire _SBDATAFieldsReg_1_3_T_1 = SBDATAWrEn_1 & _SBDATAFieldsReg_1_3_T; // @[SBA.scala:150:35, :160:{39,42}] wire _SBDATAFieldsReg_1_3_T_2 = ~SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28, :119:88, :160:67] wire _SBDATAFieldsReg_1_3_T_3 = _SBDATAFieldsReg_1_3_T_1 & _SBDATAFieldsReg_1_3_T_2; // @[SBA.scala:160:{39,64,67}] wire _SBDATAFieldsReg_1_3_T_5 = _SBDATAFieldsReg_1_3_T_3 & _SBDATAFieldsReg_1_3_T_4; // @[SBA.scala:160:{64,94,97}] wire [7:0] _SBDATAFieldsReg_1_3_T_6 = SBDATAWrData_1[31:24]; // @[SBA.scala:147:35, :160:133] wire [7:0] _SBDATAFieldsReg_1_3_T_7 = _sb2tlOpt_io_rdLoad_7 ? _sb2tlOpt_io_dataOut : SBDATAFieldsReg_1_3; // @[SBA.scala:143:30, :161:24] wire [7:0] _SBDATAFieldsReg_1_3_T_8 = _SBDATAFieldsReg_1_3_T_5 ? _SBDATAFieldsReg_1_3_T_6 : _SBDATAFieldsReg_1_3_T_7; // @[SBA.scala:160:{24,94,133}, :161:24] wire [15:0] _GEN_5 = {SBDATAFieldsReg_1_1, SBDATAFieldsReg_1_0}; // @[SBA.scala:143:30, :165:31] wire [15:0] SBDATARdData_1_lo; // @[SBA.scala:165:31] assign SBDATARdData_1_lo = _GEN_5; // @[SBA.scala:165:31] wire [15:0] sb2tlOpt_io_dataIn_lo_hi_lo; // @[SBA.scala:175:85] assign sb2tlOpt_io_dataIn_lo_hi_lo = _GEN_5; // @[SBA.scala:165:31, :175:85] wire [15:0] _GEN_6 = {SBDATAFieldsReg_1_3, SBDATAFieldsReg_1_2}; // @[SBA.scala:143:30, :165:31] wire [15:0] SBDATARdData_1_hi; // @[SBA.scala:165:31] assign SBDATARdData_1_hi = _GEN_6; // @[SBA.scala:165:31] wire [15:0] sb2tlOpt_io_dataIn_lo_hi_hi; // @[SBA.scala:175:85] assign sb2tlOpt_io_dataIn_lo_hi_hi = _GEN_6; // @[SBA.scala:165:31, :175:85] assign _SBDATARdData_1_T = {SBDATARdData_1_hi, SBDATARdData_1_lo}; // @[SBA.scala:165:31] assign SBDATARdData_1 = _SBDATARdData_1_T; // @[SBA.scala:145:35, :165:31] wire [63:0] sb2tlOpt_io_dataIn_lo = {SBDATAWrData_1, SBDATAWrData_0}; // @[SBA.scala:147:35, :175:59] wire [127:0] _sb2tlOpt_io_dataIn_T = {64'h0, sb2tlOpt_io_dataIn_lo}; // @[SBA.scala:175:59] wire [31:0] sb2tlOpt_io_dataIn_lo_lo = {sb2tlOpt_io_dataIn_lo_lo_hi, sb2tlOpt_io_dataIn_lo_lo_lo}; // @[SBA.scala:175:85] wire [31:0] sb2tlOpt_io_dataIn_lo_hi = {sb2tlOpt_io_dataIn_lo_hi_hi, sb2tlOpt_io_dataIn_lo_hi_lo}; // @[SBA.scala:175:85] wire [63:0] sb2tlOpt_io_dataIn_lo_1 = {sb2tlOpt_io_dataIn_lo_hi, sb2tlOpt_io_dataIn_lo_lo}; // @[SBA.scala:175:85] wire [127:0] _sb2tlOpt_io_dataIn_T_1 = {64'h0, sb2tlOpt_io_dataIn_lo_1}; // @[SBA.scala:175:85] wire _sb2tlOpt_io_wrEn_T_10; // @[SBA.scala:199:156] wire [127:0] _sb2tlOpt_io_dataIn_T_2 = _sb2tlOpt_io_wrEn_T_10 ? _sb2tlOpt_io_dataIn_T : _sb2tlOpt_io_dataIn_T_1; // @[SBA.scala:175:{34,59,85}, :199:156] wire _anyDataRdEn_T = SBDATARdEn_0 \| SBDATARdEn_1; // @[SBA.scala:149:35, :176:51] wire _anyDataRdEn_T_1 = _anyDataRdEn_T; // @[SBA.scala:176:51] assign _anyDataRdEn_T_2 = _anyDataRdEn_T_1; // @[SBA.scala:176:51] assign anyDataRdEn = _anyDataRdEn_T_2; // @[SBA.scala:43:34, :176:51] wire _anyDataWrEn_T = SBDATAWrEn_0 \| SBDATAWrEn_1; // @[SBA.scala:150:35, :177:51] wire _anyDataWrEn_T_1 = _anyDataWrEn_T; // @[SBA.scala:177:51] assign _anyDataWrEn_T_2 = _anyDataWrEn_T_1; // @[SBA.scala:177:51] assign anyDataWrEn = _anyDataWrEn_T_2; // @[SBA.scala:44:34, :177:51] wire _tryRdEn_T = SBADDRESSWrEn_0 & SBCSFieldsReg_sbreadonaddr; // @[SBA.scala:47:28, :108:38, :180:37] wire _tryRdEn_T_1 = SBDATARdEn_0 & SBCSFieldsReg_sbreadondata; // @[SBA.scala:47:28, :149:35, :180:86] wire tryRdEn = _tryRdEn_T \| _tryRdEn_T_1; // @[SBA.scala:180:{37,68,86}] wire _sb2tlOpt_io_rdEn_T = tryRdEn; // @[SBA.scala:180:68, :200:49] wire _sbAccessError_T = SBCSFieldsReg_sbaccess == 3'h0; // @[SBA.scala:47:28, :182:49] wire _T_204 = SBCSFieldsReg_sbaccess == 3'h1; // @[SBA.scala:47:28, :183:49] wire _sbAccessError_T_3; // @[SBA.scala:183:49] assign _sbAccessError_T_3 = _T_204; // @[SBA.scala:183:49] wire _sbAlignmentError_T; // @[SBA.scala:191:52] assign _sbAlignmentError_T = _T_204; // @[SBA.scala:183:49, :191:52] wire _T_211 = SBCSFieldsReg_sbaccess == 3'h2; // @[SBA.scala:47:28, :184:49] wire _sbAccessError_T_7; // @[SBA.scala:184:49] assign _sbAccessError_T_7 = _T_211; // @[SBA.scala:184:49] wire _sbAlignmentError_T_4; // @[SBA.scala:192:52] assign _sbAlignmentError_T_4 = _T_211; // @[SBA.scala:184:49, :192:52] wire _T_218 = SBCSFieldsReg_sbaccess == 3'h3; // @[SBA.scala:47:28, :185:49] wire _sbAccessError_T_11; // @[SBA.scala:185:49] assign _sbAccessError_T_11 = _T_218; // @[SBA.scala:185:49] wire _sbAlignmentError_T_9; // @[SBA.scala:193:52] assign _sbAlignmentError_T_9 = _T_218; // @[SBA.scala:185:49, :193:52] wire _T_225 = SBCSFieldsReg_sbaccess == 3'h4; // @[SBA.scala:47:28, :186:49] wire _sbAccessError_T_15; // @[SBA.scala:186:49] assign _sbAccessError_T_15 = _T_225; // @[SBA.scala:186:49] wire _sbAlignmentError_T_14; // @[SBA.scala:194:52] assign _sbAlignmentError_T_14 = _T_225; // @[SBA.scala:186:49, :194:52] wire _sbAccessError_T_17 = _sbAccessError_T_15; // @[SBA.scala:186:{49,58}] wire _sbAccessError_T_18 = _sbAccessError_T_17; // @[SBA.scala:185:97, :186:58] wire _sbAccessError_T_19 = SBCSFieldsReg_sbaccess > 3'h4; // @[SBA.scala:47:28, :186:124] wire sbAccessError = _sbAccessError_T_18 \| _sbAccessError_T_19; // @[SBA.scala:185:97, :186:{97,124}] wire [31:0] _compareAddr_T; // @[SBA.scala:189:23] wire [31:0] compareAddr; // @[SBA.scala:188:27] assign _compareAddr_T = SBADDRESSWrEn_0 ? SBADDRESSWrData_0 : SBADDRESSFieldsReg_0; // @[SBA.scala:104:33, :106:38, :108:38, :189:23] assign compareAddr = _compareAddr_T; // @[SBA.scala:188:27, :189:23] wire _sbAlignmentError_T_1 = compareAddr[0]; // @[SBA.scala:188:27, :191:76] wire _sbAlignmentError_T_2 = _sbAlignmentError_T_1; // @[SBA.scala:191:{76,82}] wire _sbAlignmentError_T_3 = _sbAlignmentError_T & _sbAlignmentError_T_2; // @[SBA.scala:191:{52,61,82}] wire [1:0] _sbAlignmentError_T_5 = compareAddr[1:0]; // @[SBA.scala:188:27, :192:76] wire _sbAlignmentError_T_6 = \|_sbAlignmentError_T_5; // @[SBA.scala:192:{76,82}] wire _sbAlignmentError_T_7 = _sbAlignmentError_T_4 & _sbAlignmentError_T_6; // @[SBA.scala:192:{52,61,82}] wire _sbAlignmentError_T_8 = _sbAlignmentError_T_3 \| _sbAlignmentError_T_7; // @[SBA.scala:191:{61,91}, :192:61] wire [2:0] _sbAlignmentError_T_10 = compareAddr[2:0]; // @[SBA.scala:188:27, :193:76] wire _sbAlignmentError_T_11 = \|_sbAlignmentError_T_10; // @[SBA.scala:193:{76,82}] wire _sbAlignmentError_T_12 = _sbAlignmentError_T_9 & _sbAlignmentError_T_11; // @[SBA.scala:193:{52,61,82}] wire _sbAlignmentError_T_13 = _sbAlignmentError_T_8 \| _sbAlignmentError_T_12; // @[SBA.scala:191:91, :192:91, :193:61] wire [3:0] _sbAlignmentError_T_15 = compareAddr[3:0]; // @[SBA.scala:188:27, :194:76] wire _sbAlignmentError_T_16 = \|_sbAlignmentError_T_15; // @[SBA.scala:194:{76,82}] wire _sbAlignmentError_T_17 = _sbAlignmentError_T_14 & _sbAlignmentError_T_16; // @[SBA.scala:194:{52,61,82}] wire sbAlignmentError = _sbAlignmentError_T_13 \| _sbAlignmentError_T_17; // @[SBA.scala:192:91, :193:91, :194:61] wire _sb2tlOpt_io_wrEn_T_1 = ~SBCSFieldsReg_sbbusy; // @[SBA.scala:47:28, :119:63, :199:63] wire _sb2tlOpt_io_wrEn_T_2 = _sb2tlOpt_io_wrEn_T & _sb2tlOpt_io_wrEn_T_1; // @[SBA.scala:199:{49,60,63}] wire _sb2tlOpt_io_wrEn_T_3 = ~SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28, :119:88, :199:88] wire _sb2tlOpt_io_wrEn_T_4 = _sb2tlOpt_io_wrEn_T_2 & _sb2tlOpt_io_wrEn_T_3; // @[SBA.scala:199:{60,85,88}] wire _sb2tlOpt_io_wrEn_T_6 = _sb2tlOpt_io_wrEn_T_4 & _sb2tlOpt_io_wrEn_T_5; // @[SBA.scala:199:{85,115,118}] wire _sb2tlOpt_io_wrEn_T_7 = ~sbAccessError; // @[SBA.scala:186:97, :199:141] wire _sb2tlOpt_io_wrEn_T_8 = _sb2tlOpt_io_wrEn_T_6 & _sb2tlOpt_io_wrEn_T_7; // @[SBA.scala:199:{115,138,141}] wire _sb2tlOpt_io_wrEn_T_9 = ~sbAlignmentError; // @[SBA.scala:193:91, :199:159] assign _sb2tlOpt_io_wrEn_T_10 = _sb2tlOpt_io_wrEn_T_8 & _sb2tlOpt_io_wrEn_T_9; // @[SBA.scala:199:{138,156,159}] wire _sb2tlOpt_io_rdEn_T_1 = ~SBCSFieldsReg_sbbusy; // @[SBA.scala:47:28, :119:63, :200:63] wire _sb2tlOpt_io_rdEn_T_2 = _sb2tlOpt_io_rdEn_T & _sb2tlOpt_io_rdEn_T_1; // @[SBA.scala:200:{49,60,63}] wire _sb2tlOpt_io_rdEn_T_3 = ~SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28, :119:88, :200:88] wire _sb2tlOpt_io_rdEn_T_4 = _sb2tlOpt_io_rdEn_T_2 & _sb2tlOpt_io_rdEn_T_3; // @[SBA.scala:200:{60,85,88}] wire _sb2tlOpt_io_rdEn_T_6 = _sb2tlOpt_io_rdEn_T_4 & _sb2tlOpt_io_rdEn_T_5; // @[SBA.scala:200:{85,115,118}] wire _sb2tlOpt_io_rdEn_T_7 = ~sbAccessError; // @[SBA.scala:186:97, :199:141, :200:141] wire _sb2tlOpt_io_rdEn_T_8 = _sb2tlOpt_io_rdEn_T_6 & _sb2tlOpt_io_rdEn_T_7; // @[SBA.scala:200:{115,138,141}] wire _sb2tlOpt_io_rdEn_T_9 = ~sbAlignmentError; // @[SBA.scala:193:91, :199:159, :200:159] wire _sb2tlOpt_io_rdEn_T_10 = _sb2tlOpt_io_rdEn_T_8 & _sb2tlOpt_io_rdEn_T_9; // @[SBA.scala:200:{138,156,159}] assign sbBusy = \|_sb2tlOpt_io_sbStateOut; // @[SBA.scala:51:67, :203:46] assign SBCSRdData_sbbusy = sbBusy; // @[SBA.scala:60:38, :203:46] wire _SBCSFieldsReg_sbbusyerror_T = sbbusyerrorWrEn & SBCSWrData_sbbusyerror; // @[SBA.scala:63:38, :70:38, :208:60] wire _SBCSFieldsReg_sbbusyerror_T_1 = anyAddressWrEn & sbBusy; // @[SBA.scala:42:34, :203:46, :209:59] wire _SBCSFieldsReg_sbbusyerror_T_2 = anyDataRdEn \| anyDataWrEn; // @[SBA.scala:43:34, :44:34, :210:57] wire _SBCSFieldsReg_sbbusyerror_T_3 = _SBCSFieldsReg_sbbusyerror_T_2 & sbBusy; // @[SBA.scala:203:46, :210:{57,73}] wire _SBCSFieldsReg_sbbusyerror_T_4 = _SBCSFieldsReg_sbbusyerror_T_3 \| SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28, :210:{43,73}] wire _SBCSFieldsReg_sbbusyerror_T_5 = _SBCSFieldsReg_sbbusyerror_T_1 \| _SBCSFieldsReg_sbbusyerror_T_4; // @[SBA.scala:209:{43,59}, :210:43] wire _SBCSFieldsReg_sbbusyerror_T_6 = ~_SBCSFieldsReg_sbbusyerror_T & _SBCSFieldsReg_sbbusyerror_T_5; // @[SBA.scala:208:{43,60}, :209:43] wire _SBCSFieldsReg_sbreadonaddr_T = sbreadonaddrWrEn ? SBCSWrData_sbreadonaddr : SBCSFieldsReg_sbreadonaddr; // @[SBA.scala:47:28, :63:38, :69:38, :211:43] wire _SBCSFieldsReg_sbautoincrement_T = sbautoincrementWrEn ? SBCSWrData_sbautoincrement : SBCSFieldsReg_sbautoincrement; // @[SBA.scala:47:28, :63:38, :67:38, :212:43] wire _SBCSFieldsReg_sbreadondata_T = sbreadondataWrEn ? SBCSWrData_sbreadondata : SBCSFieldsReg_sbreadondata; // @[SBA.scala:47:28, :63:38, :66:38, :213:43] wire [2:0] _SBCSFieldsReg_sbaccess_T = sbaccessWrEn ? SBCSWrData_sbaccess : SBCSFieldsReg_sbaccess; // @[SBA.scala:47:28, :63:38, :68:38, :214:43] reg sbErrorReg_0; // @[SBA.scala:219:25] reg sbErrorReg_1; // @[SBA.scala:219:25] reg sbErrorReg_2; // @[SBA.scala:219:25] wire _sbErrorReg_0_T = SBCSWrData_sberror[0]; // @[SBA.scala:63:38, :225:63] wire _sbErrorReg_0_T_1 = _sbErrorReg_0_T; // @[SBA.scala:225:{63,67}] wire _sbErrorReg_0_T_2 = sberrorWrEn & _sbErrorReg_0_T_1; // @[SBA.scala:65:38, :225:{42,67}] wire _sbErrorReg_0_T_3 = ~_sb2tlOpt_io_wrLegal; // @[SBA.scala:226:55] wire _sbErrorReg_0_T_4 = _sb2tlOpt_io_wrEn_T_10 & _sbErrorReg_0_T_3; // @[SBA.scala:199:156, :226:{52,55}] wire _sbErrorReg_0_T_5 = ~_sb2tlOpt_io_rdLegal; // @[SBA.scala:226:109] wire _sbErrorReg_0_T_6 = _sb2tlOpt_io_rdEn_T_10 & _sbErrorReg_0_T_5; // @[SBA.scala:200:156, :226:{106,109}] wire _sbErrorReg_0_T_7 = _sbErrorReg_0_T_4 \| _sbErrorReg_0_T_6; // @[SBA.scala:226:{52,81,106}] wire _GEN_7 = SBDATAWrEn_0 \| tryRdEn; // @[SBA.scala:150:35, :180:68, :227:39] wire _sbErrorReg_0_T_8; // @[SBA.scala:227:39] assign _sbErrorReg_0_T_8 = _GEN_7; // @[SBA.scala:227:39] wire _sbErrorReg_0_T_10; // @[SBA.scala:228:39] assign _sbErrorReg_0_T_10 = _GEN_7; // @[SBA.scala:227:39, :228:39] wire _sbErrorReg_1_T_8; // @[SBA.scala:227:39] assign _sbErrorReg_1_T_8 = _GEN_7; // @[SBA.scala:227:39] wire _sbErrorReg_1_T_10; // @[SBA.scala:228:39] assign _sbErrorReg_1_T_10 = _GEN_7; // @[SBA.scala:227:39, :228:39] wire _sbErrorReg_2_T_8; // @[SBA.scala:227:39] assign _sbErrorReg_2_T_8 = _GEN_7; // @[SBA.scala:227:39] wire _sbErrorReg_2_T_10; // @[SBA.scala:228:39] assign _sbErrorReg_2_T_10 = _GEN_7; // @[SBA.scala:227:39, :228:39] wire _sbErrorReg_0_T_9 = _sbErrorReg_0_T_8 & sbAlignmentError; // @[SBA.scala:193:91, :227:{39,51}] wire _sbErrorReg_0_T_11 = _sbErrorReg_0_T_10 & sbAccessError; // @[SBA.scala:186:97, :228:{39,51}] wire _sbErrorReg_0_T_13 = _sbErrorReg_0_T_12 & _sb2tlOpt_io_respError; // @[SBA.scala:229:{54,81}] wire _sbErrorReg_0_T_14 = _sbErrorReg_0_T_13 \| sbErrorReg_0; // @[SBA.scala:219:25, :229:{29,81}] wire _sbErrorReg_0_T_15 = ~_sbErrorReg_0_T_11 & _sbErrorReg_0_T_14; // @[SBA.scala:228:{29,51}, :229:29] wire _sbErrorReg_0_T_16 = _sbErrorReg_0_T_9 \| _sbErrorReg_0_T_15; // @[SBA.scala:227:{29,51}, :228:29] wire _sbErrorReg_0_T_17 = ~_sbErrorReg_0_T_7 & _sbErrorReg_0_T_16; // @[SBA.scala:226:{29,81}, :227:29] wire _sbErrorReg_0_T_18 = ~_sbErrorReg_0_T_2 & _sbErrorReg_0_T_17; // @[SBA.scala:225:{29,42}, :226:29] wire _sbErrorReg_1_T = SBCSWrData_sberror[1]; // @[SBA.scala:63:38, :225:63] wire _sbErrorReg_1_T_1 = _sbErrorReg_1_T; // @[SBA.scala:225:{63,67}] wire _sbErrorReg_1_T_2 = sberrorWrEn & _sbErrorReg_1_T_1; // @[SBA.scala:65:38, :225:{42,67}] wire _sbErrorReg_1_T_3 = ~_sb2tlOpt_io_wrLegal; // @[SBA.scala:226:55] wire _sbErrorReg_1_T_4 = _sb2tlOpt_io_wrEn_T_10 & _sbErrorReg_1_T_3; // @[SBA.scala:199:156, :226:{52,55}] wire _sbErrorReg_1_T_5 = ~_sb2tlOpt_io_rdLegal; // @[SBA.scala:226:109] wire _sbErrorReg_1_T_6 = _sb2tlOpt_io_rdEn_T_10 & _sbErrorReg_1_T_5; // @[SBA.scala:200:156, :226:{106,109}] wire _sbErrorReg_1_T_7 = _sbErrorReg_1_T_4 \| _sbErrorReg_1_T_6; // @[SBA.scala:226:{52,81,106}] wire _sbErrorReg_1_T_9 = _sbErrorReg_1_T_8 & sbAlignmentError; // @[SBA.scala:193:91, :227:{39,51}] wire _sbErrorReg_1_T_11 = _sbErrorReg_1_T_10 & sbAccessError; // @[SBA.scala:186:97, :228:{39,51}] wire _sbErrorReg_1_T_13 = _sbErrorReg_1_T_12 & _sb2tlOpt_io_respError; // @[SBA.scala:229:{54,81}] wire _sbErrorReg_1_T_14 = _sbErrorReg_1_T_13 \| sbErrorReg_1; // @[SBA.scala:219:25, :229:{29,81}] wire _sbErrorReg_1_T_15 = ~_sbErrorReg_1_T_11 & _sbErrorReg_1_T_14; // @[SBA.scala:228:{29,51}, :229:29] wire _sbErrorReg_1_T_16 = _sbErrorReg_1_T_9 \| _sbErrorReg_1_T_15; // @[SBA.scala:227:{29,51}, :228:29] wire _sbErrorReg_1_T_17 = _sbErrorReg_1_T_7 \| _sbErrorReg_1_T_16; // @[SBA.scala:226:{29,81}, :227:29] wire _sbErrorReg_1_T_18 = ~_sbErrorReg_1_T_2 & _sbErrorReg_1_T_17; // @[SBA.scala:225:{29,42}, :226:29] wire _sbErrorReg_2_T = SBCSWrData_sberror[2]; // @[SBA.scala:63:38, :225:63] wire _sbErrorReg_2_T_1 = _sbErrorReg_2_T; // @[SBA.scala:225:{63,67}] wire _sbErrorReg_2_T_2 = sberrorWrEn & _sbErrorReg_2_T_1; // @[SBA.scala:65:38, :225:{42,67}] wire _sbErrorReg_2_T_3 = ~_sb2tlOpt_io_wrLegal; // @[SBA.scala:226:55] wire _sbErrorReg_2_T_4 = _sb2tlOpt_io_wrEn_T_10 & _sbErrorReg_2_T_3; // @[SBA.scala:199:156, :226:{52,55}] wire _sbErrorReg_2_T_5 = ~_sb2tlOpt_io_rdLegal; // @[SBA.scala:226:109] wire _sbErrorReg_2_T_6 = _sb2tlOpt_io_rdEn_T_10 & _sbErrorReg_2_T_5; // @[SBA.scala:200:156, :226:{106,109}] wire _sbErrorReg_2_T_7 = _sbErrorReg_2_T_4 \| _sbErrorReg_2_T_6; // @[SBA.scala:226:{52,81,106}] wire _sbErrorReg_2_T_9 = _sbErrorReg_2_T_8 & sbAlignmentError; // @[SBA.scala:193:91, :227:{39,51}] wire _sbErrorReg_2_T_11 = _sbErrorReg_2_T_10 & sbAccessError; // @[SBA.scala:186:97, :228:{39,51}] wire _sbErrorReg_2_T_13 = _sbErrorReg_2_T_12 & _sb2tlOpt_io_respError; // @[SBA.scala:229:{54,81}] wire _sbErrorReg_2_T_14 = _sbErrorReg_2_T_13 \| sbErrorReg_2; // @[SBA.scala:219:25, :229:{29,81}] wire _sbErrorReg_2_T_15 = _sbErrorReg_2_T_11 \| _sbErrorReg_2_T_14; // @[SBA.scala:228:{29,51}, :229:29] wire _sbErrorReg_2_T_16 = ~_sbErrorReg_2_T_9 & _sbErrorReg_2_T_15; // @[SBA.scala:227:{29,51}, :228:29] wire _sbErrorReg_2_T_17 = ~_sbErrorReg_2_T_7 & _sbErrorReg_2_T_16; // @[SBA.scala:226:{29,81}, :227:29] wire _sbErrorReg_2_T_18 = ~_sbErrorReg_2_T_2 & _sbErrorReg_2_T_17; // @[SBA.scala:225:{29,42}, :226:29] wire [1:0] SBCSRdData_sberror_lo = {sbErrorReg_1, sbErrorReg_0}; // @[SBA.scala:219:25, :240:42] wire [1:0] SBCSRdData_sberror_hi = {1'h0, sbErrorReg_2}; // @[SBA.scala:219:25, :240:42] wire [3:0] _SBCSRdData_sberror_T = {SBCSRdData_sberror_hi, SBCSRdData_sberror_lo}; // @[SBA.scala:240:42] assign SBCSRdData_sberror = _SBCSRdData_sberror_T[2:0]; // @[SBA.scala:60:38, :240:{28,42}] wire [31:0] _T_237 = {COMMANDReg_cmdtype, COMMANDReg_control}; // @[Debug.scala:1277:25, :1435:40] wire [31:0] _out_T_1545; // @[RegisterRouter.scala:87:24] assign _out_T_1545 = _T_237; // @[RegisterRouter.scala:87:24] wire _out_in_ready_T; // @[RegisterRouter.scala:87:24] wire [31:0] _accessRegisterCommandReg_T; // @[Debug.scala:1533:56] assign _accessRegisterCommandReg_T = _T_237; // @[Debug.scala:1435:40, :1533:56] assign dmiNodeIn_a_ready = in_ready; // @[RegisterRouter.scala:73:18] wire _in_bits_read_T; // @[RegisterRouter.scala:74:36] wire _out_front_valid_T = in_valid; // @[RegisterRouter.scala:73:18, :87:24] wire [6:0] _in_bits_index_T; // @[Edges.scala:192:34] wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24] wire [6:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24] wire [31:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24] wire [3:0] out_front_bits_mask = in_bits_mask; // @[RegisterRouter.scala:73:18, :87:24] wire out_front_bits_extra_tlrr_extra_source = in_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24] wire [1:0] out_front_bits_extra_tlrr_extra_size = in_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24] assign _in_bits_read_T = dmiNodeIn_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36] assign _in_bits_index_T = dmiNodeIn_a_bits_address[8:2]; // @[Edges.scala:192:34] assign in_bits_index = _in_bits_index_T; // @[RegisterRouter.scala:73:18] wire _out_front_ready_T = out_ready; // @[RegisterRouter.scala:87:24] wire _out_out_valid_T; // @[RegisterRouter.scala:87:24] assign dmiNodeIn_d_valid = out_valid; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24] wire _dmiNodeIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25] assign dmiNodeIn_d_bits_data = out_bits_data; // @[RegisterRouter.scala:87:24] assign dmiNodeIn_d_bits_d_source = out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [1:0] out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign dmiNodeIn_d_bits_d_size = out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign _out_in_ready_T = out_front_ready; // @[RegisterRouter.scala:87:24] assign _out_out_valid_T = out_front_valid; // @[RegisterRouter.scala:87:24] assign out_bits_read = out_front_bits_read; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_112 = out_front_bits_data; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_741 = out_front_bits_data; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_796 = out_front_bits_data; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_939 = out_front_bits_data; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1536 = out_front_bits_data; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1591 = out_front_bits_data; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_source = out_front_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_size = out_front_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] wire [6:0] _GEN_8 = out_front_bits_index & 7'h40; // @[RegisterRouter.scala:87:24] wire [6:0] out_findex; // @[RegisterRouter.scala:87:24] assign out_findex = _GEN_8; // @[RegisterRouter.scala:87:24] wire [6:0] out_bindex; // @[RegisterRouter.scala:87:24] assign out_bindex = _GEN_8; // @[RegisterRouter.scala:87:24] wire _GEN_9 = out_findex == 7'h0; // @[RegisterRouter.scala:87:24] wire _out_T; // @[RegisterRouter.scala:87:24] assign _out_T = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_2; // @[RegisterRouter.scala:87:24] assign _out_T_2 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_4; // @[RegisterRouter.scala:87:24] assign _out_T_4 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_6; // @[RegisterRouter.scala:87:24] assign _out_T_6 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_8; // @[RegisterRouter.scala:87:24] assign _out_T_8 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_10; // @[RegisterRouter.scala:87:24] assign _out_T_10 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_12; // @[RegisterRouter.scala:87:24] assign _out_T_12 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_14; // @[RegisterRouter.scala:87:24] assign _out_T_14 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_16; // @[RegisterRouter.scala:87:24] assign _out_T_16 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_18; // @[RegisterRouter.scala:87:24] assign _out_T_18 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_20; // @[RegisterRouter.scala:87:24] assign _out_T_20 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_22; // @[RegisterRouter.scala:87:24] assign _out_T_22 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_24; // @[RegisterRouter.scala:87:24] assign _out_T_24 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_26; // @[RegisterRouter.scala:87:24] assign _out_T_26 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_28; // @[RegisterRouter.scala:87:24] assign _out_T_28 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_30; // @[RegisterRouter.scala:87:24] assign _out_T_30 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_32; // @[RegisterRouter.scala:87:24] assign _out_T_32 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_34; // @[RegisterRouter.scala:87:24] assign _out_T_34 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_36; // @[RegisterRouter.scala:87:24] assign _out_T_36 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_38; // @[RegisterRouter.scala:87:24] assign _out_T_38 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_42; // @[RegisterRouter.scala:87:24] assign _out_T_42 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_44; // @[RegisterRouter.scala:87:24] assign _out_T_44 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_46; // @[RegisterRouter.scala:87:24] assign _out_T_46 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_48; // @[RegisterRouter.scala:87:24] assign _out_T_48 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_50; // @[RegisterRouter.scala:87:24] assign _out_T_50 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_52; // @[RegisterRouter.scala:87:24] assign _out_T_52 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_54; // @[RegisterRouter.scala:87:24] assign _out_T_54 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_56; // @[RegisterRouter.scala:87:24] assign _out_T_56 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_58; // @[RegisterRouter.scala:87:24] assign _out_T_58 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_60; // @[RegisterRouter.scala:87:24] assign _out_T_60 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_62; // @[RegisterRouter.scala:87:24] assign _out_T_62 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_64; // @[RegisterRouter.scala:87:24] assign _out_T_64 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_66; // @[RegisterRouter.scala:87:24] assign _out_T_66 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _GEN_10 = out_bindex == 7'h0; // @[RegisterRouter.scala:87:24] wire _out_T_1; // @[RegisterRouter.scala:87:24] assign _out_T_1 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_3; // @[RegisterRouter.scala:87:24] assign _out_T_3 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_5; // @[RegisterRouter.scala:87:24] assign _out_T_5 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_7; // @[RegisterRouter.scala:87:24] assign _out_T_7 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_9; // @[RegisterRouter.scala:87:24] assign _out_T_9 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_11; // @[RegisterRouter.scala:87:24] assign _out_T_11 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_13; // @[RegisterRouter.scala:87:24] assign _out_T_13 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_15; // @[RegisterRouter.scala:87:24] assign _out_T_15 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_17; // @[RegisterRouter.scala:87:24] assign _out_T_17 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_19; // @[RegisterRouter.scala:87:24] assign _out_T_19 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_21; // @[RegisterRouter.scala:87:24] assign _out_T_21 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_23; // @[RegisterRouter.scala:87:24] assign _out_T_23 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_25; // @[RegisterRouter.scala:87:24] assign _out_T_25 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_27; // @[RegisterRouter.scala:87:24] assign _out_T_27 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_29; // @[RegisterRouter.scala:87:24] assign _out_T_29 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_31; // @[RegisterRouter.scala:87:24] assign _out_T_31 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_33; // @[RegisterRouter.scala:87:24] assign _out_T_33 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_35; // @[RegisterRouter.scala:87:24] assign _out_T_35 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_37; // @[RegisterRouter.scala:87:24] assign _out_T_37 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_39; // @[RegisterRouter.scala:87:24] assign _out_T_39 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_43; // @[RegisterRouter.scala:87:24] assign _out_T_43 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_45; // @[RegisterRouter.scala:87:24] assign _out_T_45 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_47; // @[RegisterRouter.scala:87:24] assign _out_T_47 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_49; // @[RegisterRouter.scala:87:24] assign _out_T_49 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_51; // @[RegisterRouter.scala:87:24] assign _out_T_51 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_53; // @[RegisterRouter.scala:87:24] assign _out_T_53 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_55; // @[RegisterRouter.scala:87:24] assign _out_T_55 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_57; // @[RegisterRouter.scala:87:24] assign _out_T_57 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_59; // @[RegisterRouter.scala:87:24] assign _out_T_59 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_61; // @[RegisterRouter.scala:87:24] assign _out_T_61 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_63; // @[RegisterRouter.scala:87:24] assign _out_T_63 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_65; // @[RegisterRouter.scala:87:24] assign _out_T_65 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_67; // @[RegisterRouter.scala:87:24] assign _out_T_67 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_5 = _out_T_1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_61 = _out_T_3; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_9 = _out_T_5; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_41 = _out_T_7; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_35 = _out_T_9; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_8 = _out_T_11; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_4 = _out_T_13; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_47 = _out_T_15; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_10 = _out_T_17; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_56 = _out_T_19; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_42 = _out_T_21; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_24 = _out_T_23; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_37 = _out_T_25; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_46 = _out_T_27; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_57 = _out_T_29; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_6 = _out_T_31; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_60 = _out_T_33; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_38 = _out_T_35; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_33 = _out_T_37; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_45 = _out_T_39; // @[MuxLiteral.scala:49:48] wire _out_T_40 = out_findex == 7'h40; // @[RegisterRouter.scala:87:24] wire _out_T_41 = out_bindex == 7'h40; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_0 = _out_T_41; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_17 = _out_T_43; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_32 = _out_T_45; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_34 = _out_T_47; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_22 = _out_T_49; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_44 = _out_T_51; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_7 = _out_T_53; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_39 = _out_T_55; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_11 = _out_T_57; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_43 = _out_T_59; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_40 = _out_T_61; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_23 = _out_T_63; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_36 = _out_T_65; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_T_23; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_19 = _out_T_67; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_T_247; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_39; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_167; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_143; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_35; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_19; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_191; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_43; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_171; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_99; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_151; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_187; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_231; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_27; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_243; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_155; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_135; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_183; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_131; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_139; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_91; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_179; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_31; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_159; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_47; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_175; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_163; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_95; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_147; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_79; // @[RegisterRouter.scala:87:24] wire out_rivalid_0; // @[RegisterRouter.scala:87:24] wire out_rivalid_1; // @[RegisterRouter.scala:87:24] wire out_rivalid_2; // @[RegisterRouter.scala:87:24] wire out_rivalid_3; // @[RegisterRouter.scala:87:24] wire out_rivalid_4; // @[RegisterRouter.scala:87:24] wire out_rivalid_5; // @[RegisterRouter.scala:87:24] wire out_rivalid_6; // @[RegisterRouter.scala:87:24] wire out_rivalid_7; // @[RegisterRouter.scala:87:24] wire out_rivalid_8; // @[RegisterRouter.scala:87:24] wire out_rivalid_9; // @[RegisterRouter.scala:87:24] wire out_rivalid_10; // @[RegisterRouter.scala:87:24] wire out_rivalid_11; // @[RegisterRouter.scala:87:24] wire out_rivalid_12; // @[RegisterRouter.scala:87:24] wire out_rivalid_13; // @[RegisterRouter.scala:87:24] wire out_rivalid_14; // @[RegisterRouter.scala:87:24] wire out_rivalid_15; // @[RegisterRouter.scala:87:24] wire out_rivalid_16; // @[RegisterRouter.scala:87:24] wire out_rivalid_17; // @[RegisterRouter.scala:87:24] wire out_rivalid_18; // @[RegisterRouter.scala:87:24] wire out_rivalid_19; // @[RegisterRouter.scala:87:24] wire out_rivalid_20; // @[RegisterRouter.scala:87:24] wire out_rivalid_21; // @[RegisterRouter.scala:87:24] wire out_rivalid_22; // @[RegisterRouter.scala:87:24] wire out_rivalid_23; // @[RegisterRouter.scala:87:24] wire out_rivalid_24; // @[RegisterRouter.scala:87:24] wire out_rivalid_25; // @[RegisterRouter.scala:87:24] wire out_rivalid_26; // @[RegisterRouter.scala:87:24] wire out_rivalid_27; // @[RegisterRouter.scala:87:24] wire out_rivalid_28; // @[RegisterRouter.scala:87:24] wire out_rivalid_29; // @[RegisterRouter.scala:87:24] wire out_rivalid_30; // @[RegisterRouter.scala:87:24] wire out_rivalid_31; // @[RegisterRouter.scala:87:24] wire out_rivalid_32; // @[RegisterRouter.scala:87:24] wire out_rivalid_33; // @[RegisterRouter.scala:87:24] wire out_rivalid_34; // @[RegisterRouter.scala:87:24] wire out_rivalid_35; // @[RegisterRouter.scala:87:24] wire out_rivalid_36; // @[RegisterRouter.scala:87:24] wire out_rivalid_37; // @[RegisterRouter.scala:87:24] wire out_rivalid_38; // @[RegisterRouter.scala:87:24] wire out_rivalid_39; // @[RegisterRouter.scala:87:24] wire out_rivalid_40; // @[RegisterRouter.scala:87:24] wire out_rivalid_41; // @[RegisterRouter.scala:87:24] wire out_rivalid_42; // @[RegisterRouter.scala:87:24] wire out_rivalid_43; // @[RegisterRouter.scala:87:24] wire out_rivalid_44; // @[RegisterRouter.scala:87:24] wire out_rivalid_45; // @[RegisterRouter.scala:87:24] wire out_rivalid_46; // @[RegisterRouter.scala:87:24] wire out_rivalid_47; // @[RegisterRouter.scala:87:24] wire out_rivalid_48; // @[RegisterRouter.scala:87:24] wire out_rivalid_49; // @[RegisterRouter.scala:87:24] wire out_rivalid_50; // @[RegisterRouter.scala:87:24] wire out_rivalid_51; // @[RegisterRouter.scala:87:24] wire out_rivalid_52; // @[RegisterRouter.scala:87:24] wire out_rivalid_53; // @[RegisterRouter.scala:87:24] wire out_rivalid_54; // @[RegisterRouter.scala:87:24] wire out_rivalid_55; // @[RegisterRouter.scala:87:24] wire out_rivalid_56; // @[RegisterRouter.scala:87:24] wire out_rivalid_57; // @[RegisterRouter.scala:87:24] wire out_rivalid_58; // @[RegisterRouter.scala:87:24] wire out_rivalid_59; // @[RegisterRouter.scala:87:24] wire out_rivalid_60; // @[RegisterRouter.scala:87:24] wire out_rivalid_61; // @[RegisterRouter.scala:87:24] wire out_rivalid_62; // @[RegisterRouter.scala:87:24] wire out_rivalid_63; // @[RegisterRouter.scala:87:24] wire out_rivalid_64; // @[RegisterRouter.scala:87:24] wire out_rivalid_65; // @[RegisterRouter.scala:87:24] wire out_rivalid_66; // @[RegisterRouter.scala:87:24] wire out_rivalid_67; // @[RegisterRouter.scala:87:24] wire out_rivalid_68; // @[RegisterRouter.scala:87:24] wire out_rivalid_69; // @[RegisterRouter.scala:87:24] wire out_rivalid_70; // @[RegisterRouter.scala:87:24] wire out_rivalid_71; // @[RegisterRouter.scala:87:24] wire out_rivalid_72; // @[RegisterRouter.scala:87:24] wire out_rivalid_73; // @[RegisterRouter.scala:87:24] wire out_rivalid_74; // @[RegisterRouter.scala:87:24] wire out_rivalid_75; // @[RegisterRouter.scala:87:24] wire out_rivalid_76; // @[RegisterRouter.scala:87:24] wire out_rivalid_77; // @[RegisterRouter.scala:87:24] wire out_rivalid_78; // @[RegisterRouter.scala:87:24] wire out_rivalid_79; // @[RegisterRouter.scala:87:24] wire out_rivalid_80; // @[RegisterRouter.scala:87:24] wire out_rivalid_81; // @[RegisterRouter.scala:87:24] wire out_rivalid_82; // @[RegisterRouter.scala:87:24] wire out_rivalid_83; // @[RegisterRouter.scala:87:24] wire out_rivalid_84; // @[RegisterRouter.scala:87:24] wire out_rivalid_85; // @[RegisterRouter.scala:87:24] wire out_rivalid_86; // @[RegisterRouter.scala:87:24] wire out_rivalid_87; // @[RegisterRouter.scala:87:24] wire out_rivalid_88; // @[RegisterRouter.scala:87:24] wire out_rivalid_89; // @[RegisterRouter.scala:87:24] wire out_rivalid_90; // @[RegisterRouter.scala:87:24] wire out_rivalid_91; // @[RegisterRouter.scala:87:24] wire out_rivalid_92; // @[RegisterRouter.scala:87:24] wire out_rivalid_93; // @[RegisterRouter.scala:87:24] wire out_rivalid_94; // @[RegisterRouter.scala:87:24] wire out_rivalid_95; // @[RegisterRouter.scala:87:24] wire out_rivalid_96; // @[RegisterRouter.scala:87:24] wire out_rivalid_97; // @[RegisterRouter.scala:87:24] wire out_rivalid_98; // @[RegisterRouter.scala:87:24] wire out_rivalid_99; // @[RegisterRouter.scala:87:24] wire out_rivalid_100; // @[RegisterRouter.scala:87:24] wire out_rivalid_101; // @[RegisterRouter.scala:87:24] wire out_rivalid_102; // @[RegisterRouter.scala:87:24] wire out_rivalid_103; // @[RegisterRouter.scala:87:24] wire out_rivalid_104; // @[RegisterRouter.scala:87:24] wire out_rivalid_105; // @[RegisterRouter.scala:87:24] wire out_rivalid_106; // @[RegisterRouter.scala:87:24] wire out_rivalid_107; // @[RegisterRouter.scala:87:24] wire out_rivalid_108; // @[RegisterRouter.scala:87:24] wire out_rivalid_109; // @[RegisterRouter.scala:87:24] wire out_rivalid_110; // @[RegisterRouter.scala:87:24] wire out_rivalid_111; // @[RegisterRouter.scala:87:24] wire out_rivalid_112; // @[RegisterRouter.scala:87:24] wire out_rivalid_113; // @[RegisterRouter.scala:87:24] wire out_rivalid_114; // @[RegisterRouter.scala:87:24] wire out_rivalid_115; // @[RegisterRouter.scala:87:24] wire out_rivalid_116; // @[RegisterRouter.scala:87:24] wire out_rivalid_117; // @[RegisterRouter.scala:87:24] wire out_rivalid_118; // @[RegisterRouter.scala:87:24] wire out_rivalid_119; // @[RegisterRouter.scala:87:24] wire out_rivalid_120; // @[RegisterRouter.scala:87:24] wire out_rivalid_121; // @[RegisterRouter.scala:87:24] wire out_rivalid_122; // @[RegisterRouter.scala:87:24] wire out_rivalid_123; // @[RegisterRouter.scala:87:24] wire out_rivalid_124; // @[RegisterRouter.scala:87:24] wire out_rivalid_125; // @[RegisterRouter.scala:87:24] wire out_rivalid_126; // @[RegisterRouter.scala:87:24] wire out_rivalid_127; // @[RegisterRouter.scala:87:24] wire out_rivalid_128; // @[RegisterRouter.scala:87:24] wire out_rivalid_129; // @[RegisterRouter.scala:87:24] wire out_rivalid_130; // @[RegisterRouter.scala:87:24] wire out_rivalid_131; // @[RegisterRouter.scala:87:24] wire out_rivalid_132; // @[RegisterRouter.scala:87:24] wire out_rivalid_133; // @[RegisterRouter.scala:87:24] wire out_rivalid_134; // @[RegisterRouter.scala:87:24] wire out_rivalid_135; // @[RegisterRouter.scala:87:24] wire out_rivalid_136; // @[RegisterRouter.scala:87:24] wire out_rivalid_137; // @[RegisterRouter.scala:87:24] wire out_rivalid_138; // @[RegisterRouter.scala:87:24] wire out_rivalid_139; // @[RegisterRouter.scala:87:24] wire out_rivalid_140; // @[RegisterRouter.scala:87:24] wire out_rivalid_141; // @[RegisterRouter.scala:87:24] wire out_rivalid_142; // @[RegisterRouter.scala:87:24] wire out_rivalid_143; // @[RegisterRouter.scala:87:24] wire out_rivalid_144; // @[RegisterRouter.scala:87:24] wire out_rivalid_145; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_24; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_248; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_40; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_168; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_144; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_36; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_20; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_192; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_44; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_172; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_100; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_152; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_188; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_232; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_28; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_244; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_156; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_136; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_184; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_132; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_140; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_92; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_180; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_32; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_160; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_48; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_176; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_164; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_96; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_148; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_80; // @[RegisterRouter.scala:87:24] wire out_wivalid_0; // @[RegisterRouter.scala:87:24] wire out_wivalid_1; // @[RegisterRouter.scala:87:24] wire out_wivalid_2; // @[RegisterRouter.scala:87:24] wire out_wivalid_3; // @[RegisterRouter.scala:87:24] wire out_wivalid_4; // @[RegisterRouter.scala:87:24] wire out_wivalid_5; // @[RegisterRouter.scala:87:24] wire out_wivalid_6; // @[RegisterRouter.scala:87:24] wire out_wivalid_7; // @[RegisterRouter.scala:87:24] wire out_wivalid_8; // @[RegisterRouter.scala:87:24] wire out_wivalid_9; // @[RegisterRouter.scala:87:24] wire out_wivalid_10; // @[RegisterRouter.scala:87:24] wire out_wivalid_11; // @[RegisterRouter.scala:87:24] wire out_wivalid_12; // @[RegisterRouter.scala:87:24] wire out_wivalid_13; // @[RegisterRouter.scala:87:24] wire out_wivalid_14; // @[RegisterRouter.scala:87:24] wire out_wivalid_15; // @[RegisterRouter.scala:87:24] wire out_wivalid_16; // @[RegisterRouter.scala:87:24] wire out_wivalid_17; // @[RegisterRouter.scala:87:24] wire out_wivalid_18; // @[RegisterRouter.scala:87:24] wire out_wivalid_19; // @[RegisterRouter.scala:87:24] wire out_wivalid_20; // @[RegisterRouter.scala:87:24] wire out_wivalid_21; // @[RegisterRouter.scala:87:24] wire out_wivalid_22; // @[RegisterRouter.scala:87:24] wire out_wivalid_23; // @[RegisterRouter.scala:87:24] wire out_wivalid_24; // @[RegisterRouter.scala:87:24] wire out_wivalid_25; // @[RegisterRouter.scala:87:24] wire out_wivalid_26; // @[RegisterRouter.scala:87:24] wire out_wivalid_27; // @[RegisterRouter.scala:87:24] wire out_wivalid_28; // @[RegisterRouter.scala:87:24] wire out_wivalid_29; // @[RegisterRouter.scala:87:24] wire out_wivalid_30; // @[RegisterRouter.scala:87:24] wire out_wivalid_31; // @[RegisterRouter.scala:87:24] wire out_wivalid_32; // @[RegisterRouter.scala:87:24] wire out_wivalid_33; // @[RegisterRouter.scala:87:24] wire out_wivalid_34; // @[RegisterRouter.scala:87:24] wire out_wivalid_35; // @[RegisterRouter.scala:87:24] wire out_wivalid_36; // @[RegisterRouter.scala:87:24] wire out_wivalid_37; // @[RegisterRouter.scala:87:24] wire out_wivalid_38; // @[RegisterRouter.scala:87:24] wire out_wivalid_39; // @[RegisterRouter.scala:87:24] wire out_wivalid_40; // @[RegisterRouter.scala:87:24] wire out_wivalid_41; // @[RegisterRouter.scala:87:24] wire out_wivalid_42; // @[RegisterRouter.scala:87:24] wire out_wivalid_43; // @[RegisterRouter.scala:87:24] wire out_wivalid_44; // @[RegisterRouter.scala:87:24] wire out_wivalid_45; // @[RegisterRouter.scala:87:24] wire out_wivalid_46; // @[RegisterRouter.scala:87:24] wire out_wivalid_47; // @[RegisterRouter.scala:87:24] wire out_wivalid_48; // @[RegisterRouter.scala:87:24] wire out_wivalid_49; // @[RegisterRouter.scala:87:24] wire out_wivalid_50; // @[RegisterRouter.scala:87:24] wire out_wivalid_51; // @[RegisterRouter.scala:87:24] wire out_wivalid_52; // @[RegisterRouter.scala:87:24] wire out_wivalid_53; // @[RegisterRouter.scala:87:24] wire out_wivalid_54; // @[RegisterRouter.scala:87:24] wire out_wivalid_55; // @[RegisterRouter.scala:87:24] wire out_wivalid_56; // @[RegisterRouter.scala:87:24] wire out_wivalid_57; // @[RegisterRouter.scala:87:24] wire out_wivalid_58; // @[RegisterRouter.scala:87:24] wire out_wivalid_59; // @[RegisterRouter.scala:87:24] wire out_wivalid_60; // @[RegisterRouter.scala:87:24] wire out_wivalid_61; // @[RegisterRouter.scala:87:24] wire out_wivalid_62; // @[RegisterRouter.scala:87:24] wire out_wivalid_63; // @[RegisterRouter.scala:87:24] wire out_wivalid_64; // @[RegisterRouter.scala:87:24] wire out_wivalid_65; // @[RegisterRouter.scala:87:24] wire out_wivalid_66; // @[RegisterRouter.scala:87:24] wire out_wivalid_67; // @[RegisterRouter.scala:87:24] wire out_wivalid_68; // @[RegisterRouter.scala:87:24] wire out_wivalid_69; // @[RegisterRouter.scala:87:24] wire out_wivalid_70; // @[RegisterRouter.scala:87:24] wire out_wivalid_71; // @[RegisterRouter.scala:87:24] wire out_wivalid_72; // @[RegisterRouter.scala:87:24] wire out_wivalid_73; // @[RegisterRouter.scala:87:24] wire out_wivalid_74; // @[RegisterRouter.scala:87:24] wire out_wivalid_75; // @[RegisterRouter.scala:87:24] wire out_wivalid_76; // @[RegisterRouter.scala:87:24] wire out_wivalid_77; // @[RegisterRouter.scala:87:24] wire out_wivalid_78; // @[RegisterRouter.scala:87:24] wire out_wivalid_79; // @[RegisterRouter.scala:87:24] wire out_wivalid_80; // @[RegisterRouter.scala:87:24] wire out_wivalid_81; // @[RegisterRouter.scala:87:24] wire out_wivalid_82; // @[RegisterRouter.scala:87:24] wire out_wivalid_83; // @[RegisterRouter.scala:87:24] wire out_wivalid_84; // @[RegisterRouter.scala:87:24] wire out_wivalid_85; // @[RegisterRouter.scala:87:24] wire out_wivalid_86; // @[RegisterRouter.scala:87:24] wire out_wivalid_87; // @[RegisterRouter.scala:87:24] wire out_wivalid_88; // @[RegisterRouter.scala:87:24] wire out_wivalid_89; // @[RegisterRouter.scala:87:24] wire out_wivalid_90; // @[RegisterRouter.scala:87:24] wire out_wivalid_91; // @[RegisterRouter.scala:87:24] wire out_wivalid_92; // @[RegisterRouter.scala:87:24] wire out_wivalid_93; // @[RegisterRouter.scala:87:24] wire out_wivalid_94; // @[RegisterRouter.scala:87:24] wire out_wivalid_95; // @[RegisterRouter.scala:87:24] wire out_wivalid_96; // @[RegisterRouter.scala:87:24] wire out_wivalid_97; // @[RegisterRouter.scala:87:24] wire out_wivalid_98; // @[RegisterRouter.scala:87:24] wire out_wivalid_99; // @[RegisterRouter.scala:87:24] wire out_wivalid_100; // @[RegisterRouter.scala:87:24] wire out_wivalid_101; // @[RegisterRouter.scala:87:24] wire out_wivalid_102; // @[RegisterRouter.scala:87:24] wire out_wivalid_103; // @[RegisterRouter.scala:87:24] wire out_wivalid_104; // @[RegisterRouter.scala:87:24] wire out_wivalid_105; // @[RegisterRouter.scala:87:24] wire out_wivalid_106; // @[RegisterRouter.scala:87:24] wire out_wivalid_107; // @[RegisterRouter.scala:87:24] wire out_wivalid_108; // @[RegisterRouter.scala:87:24] wire out_wivalid_109; // @[RegisterRouter.scala:87:24] wire out_wivalid_110; // @[RegisterRouter.scala:87:24] wire out_wivalid_111; // @[RegisterRouter.scala:87:24] wire out_wivalid_112; // @[RegisterRouter.scala:87:24] wire out_wivalid_113; // @[RegisterRouter.scala:87:24] wire out_wivalid_114; // @[RegisterRouter.scala:87:24] wire out_wivalid_115; // @[RegisterRouter.scala:87:24] wire out_wivalid_116; // @[RegisterRouter.scala:87:24] wire out_wivalid_117; // @[RegisterRouter.scala:87:24] wire out_wivalid_118; // @[RegisterRouter.scala:87:24] wire out_wivalid_119; // @[RegisterRouter.scala:87:24] wire out_wivalid_120; // @[RegisterRouter.scala:87:24] wire out_wivalid_121; // @[RegisterRouter.scala:87:24] wire out_wivalid_122; // @[RegisterRouter.scala:87:24] wire out_wivalid_123; // @[RegisterRouter.scala:87:24] wire out_wivalid_124; // @[RegisterRouter.scala:87:24] wire out_wivalid_125; // @[RegisterRouter.scala:87:24] wire out_wivalid_126; // @[RegisterRouter.scala:87:24] wire out_wivalid_127; // @[RegisterRouter.scala:87:24] wire out_wivalid_128; // @[RegisterRouter.scala:87:24] wire out_wivalid_129; // @[RegisterRouter.scala:87:24] wire out_wivalid_130; // @[RegisterRouter.scala:87:24] wire out_wivalid_131; // @[RegisterRouter.scala:87:24] wire out_wivalid_132; // @[RegisterRouter.scala:87:24] wire out_wivalid_133; // @[RegisterRouter.scala:87:24] wire out_wivalid_134; // @[RegisterRouter.scala:87:24] wire out_wivalid_135; // @[RegisterRouter.scala:87:24] wire out_wivalid_136; // @[RegisterRouter.scala:87:24] wire out_wivalid_137; // @[RegisterRouter.scala:87:24] wire out_wivalid_138; // @[RegisterRouter.scala:87:24] wire out_wivalid_139; // @[RegisterRouter.scala:87:24] wire out_wivalid_140; // @[RegisterRouter.scala:87:24] wire out_wivalid_141; // @[RegisterRouter.scala:87:24] wire out_wivalid_142; // @[RegisterRouter.scala:87:24] wire out_wivalid_143; // @[RegisterRouter.scala:87:24] wire out_wivalid_144; // @[RegisterRouter.scala:87:24] wire out_wivalid_145; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_23; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_247; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_39; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_167; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_143; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_35; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_19; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_191; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_43; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_171; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_99; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_151; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_187; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_231; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_27; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_243; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_155; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_135; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_183; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_131; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_139; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_91; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_179; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_31; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_159; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_47; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_175; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_163; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_95; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_147; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_79; // @[RegisterRouter.scala:87:24] wire out_roready_0; // @[RegisterRouter.scala:87:24] wire out_roready_1; // @[RegisterRouter.scala:87:24] wire out_roready_2; // @[RegisterRouter.scala:87:24] wire out_roready_3; // @[RegisterRouter.scala:87:24] wire out_roready_4; // @[RegisterRouter.scala:87:24] wire out_roready_5; // @[RegisterRouter.scala:87:24] wire out_roready_6; // @[RegisterRouter.scala:87:24] wire out_roready_7; // @[RegisterRouter.scala:87:24] wire out_roready_8; // @[RegisterRouter.scala:87:24] wire out_roready_9; // @[RegisterRouter.scala:87:24] wire out_roready_10; // @[RegisterRouter.scala:87:24] wire out_roready_11; // @[RegisterRouter.scala:87:24] wire out_roready_12; // @[RegisterRouter.scala:87:24] wire out_roready_13; // @[RegisterRouter.scala:87:24] wire out_roready_14; // @[RegisterRouter.scala:87:24] wire out_roready_15; // @[RegisterRouter.scala:87:24] wire out_roready_16; // @[RegisterRouter.scala:87:24] wire out_roready_17; // @[RegisterRouter.scala:87:24] wire out_roready_18; // @[RegisterRouter.scala:87:24] wire out_roready_19; // @[RegisterRouter.scala:87:24] wire out_roready_20; // @[RegisterRouter.scala:87:24] wire out_roready_21; // @[RegisterRouter.scala:87:24] wire out_roready_22; // @[RegisterRouter.scala:87:24] wire out_roready_23; // @[RegisterRouter.scala:87:24] wire out_roready_24; // @[RegisterRouter.scala:87:24] wire out_roready_25; // @[RegisterRouter.scala:87:24] wire out_roready_26; // @[RegisterRouter.scala:87:24] wire out_roready_27; // @[RegisterRouter.scala:87:24] wire out_roready_28; // @[RegisterRouter.scala:87:24] wire out_roready_29; // @[RegisterRouter.scala:87:24] wire out_roready_30; // @[RegisterRouter.scala:87:24] wire out_roready_31; // @[RegisterRouter.scala:87:24] wire out_roready_32; // @[RegisterRouter.scala:87:24] wire out_roready_33; // @[RegisterRouter.scala:87:24] wire out_roready_34; // @[RegisterRouter.scala:87:24] wire out_roready_35; // @[RegisterRouter.scala:87:24] wire out_roready_36; // @[RegisterRouter.scala:87:24] wire out_roready_37; // @[RegisterRouter.scala:87:24] wire out_roready_38; // @[RegisterRouter.scala:87:24] wire out_roready_39; // @[RegisterRouter.scala:87:24] wire out_roready_40; // @[RegisterRouter.scala:87:24] wire out_roready_41; // @[RegisterRouter.scala:87:24] wire out_roready_42; // @[RegisterRouter.scala:87:24] wire out_roready_43; // @[RegisterRouter.scala:87:24] wire out_roready_44; // @[RegisterRouter.scala:87:24] wire out_roready_45; // @[RegisterRouter.scala:87:24] wire out_roready_46; // @[RegisterRouter.scala:87:24] wire out_roready_47; // @[RegisterRouter.scala:87:24] wire out_roready_48; // @[RegisterRouter.scala:87:24] wire out_roready_49; // @[RegisterRouter.scala:87:24] wire out_roready_50; // @[RegisterRouter.scala:87:24] wire out_roready_51; // @[RegisterRouter.scala:87:24] wire out_roready_52; // @[RegisterRouter.scala:87:24] wire out_roready_53; // @[RegisterRouter.scala:87:24] wire out_roready_54; // @[RegisterRouter.scala:87:24] wire out_roready_55; // @[RegisterRouter.scala:87:24] wire out_roready_56; // @[RegisterRouter.scala:87:24] wire out_roready_57; // @[RegisterRouter.scala:87:24] wire out_roready_58; // @[RegisterRouter.scala:87:24] wire out_roready_59; // @[RegisterRouter.scala:87:24] wire out_roready_60; // @[RegisterRouter.scala:87:24] wire out_roready_61; // @[RegisterRouter.scala:87:24] wire out_roready_62; // @[RegisterRouter.scala:87:24] wire out_roready_63; // @[RegisterRouter.scala:87:24] wire out_roready_64; // @[RegisterRouter.scala:87:24] wire out_roready_65; // @[RegisterRouter.scala:87:24] wire out_roready_66; // @[RegisterRouter.scala:87:24] wire out_roready_67; // @[RegisterRouter.scala:87:24] wire out_roready_68; // @[RegisterRouter.scala:87:24] wire out_roready_69; // @[RegisterRouter.scala:87:24] wire out_roready_70; // @[RegisterRouter.scala:87:24] wire out_roready_71; // @[RegisterRouter.scala:87:24] wire out_roready_72; // @[RegisterRouter.scala:87:24] wire out_roready_73; // @[RegisterRouter.scala:87:24] wire out_roready_74; // @[RegisterRouter.scala:87:24] wire out_roready_75; // @[RegisterRouter.scala:87:24] wire out_roready_76; // @[RegisterRouter.scala:87:24] wire out_roready_77; // @[RegisterRouter.scala:87:24] wire out_roready_78; // @[RegisterRouter.scala:87:24] wire out_roready_79; // @[RegisterRouter.scala:87:24] wire out_roready_80; // @[RegisterRouter.scala:87:24] wire out_roready_81; // @[RegisterRouter.scala:87:24] wire out_roready_82; // @[RegisterRouter.scala:87:24] wire out_roready_83; // @[RegisterRouter.scala:87:24] wire out_roready_84; // @[RegisterRouter.scala:87:24] wire out_roready_85; // @[RegisterRouter.scala:87:24] wire out_roready_86; // @[RegisterRouter.scala:87:24] wire out_roready_87; // @[RegisterRouter.scala:87:24] wire out_roready_88; // @[RegisterRouter.scala:87:24] wire out_roready_89; // @[RegisterRouter.scala:87:24] wire out_roready_90; // @[RegisterRouter.scala:87:24] wire out_roready_91; // @[RegisterRouter.scala:87:24] wire out_roready_92; // @[RegisterRouter.scala:87:24] wire out_roready_93; // @[RegisterRouter.scala:87:24] wire out_roready_94; // @[RegisterRouter.scala:87:24] wire out_roready_95; // @[RegisterRouter.scala:87:24] wire out_roready_96; // @[RegisterRouter.scala:87:24] wire out_roready_97; // @[RegisterRouter.scala:87:24] wire out_roready_98; // @[RegisterRouter.scala:87:24] wire out_roready_99; // @[RegisterRouter.scala:87:24] wire out_roready_100; // @[RegisterRouter.scala:87:24] wire out_roready_101; // @[RegisterRouter.scala:87:24] wire out_roready_102; // @[RegisterRouter.scala:87:24] wire out_roready_103; // @[RegisterRouter.scala:87:24] wire out_roready_104; // @[RegisterRouter.scala:87:24] wire out_roready_105; // @[RegisterRouter.scala:87:24] wire out_roready_106; // @[RegisterRouter.scala:87:24] wire out_roready_107; // @[RegisterRouter.scala:87:24] wire out_roready_108; // @[RegisterRouter.scala:87:24] wire out_roready_109; // @[RegisterRouter.scala:87:24] wire out_roready_110; // @[RegisterRouter.scala:87:24] wire out_roready_111; // @[RegisterRouter.scala:87:24] wire out_roready_112; // @[RegisterRouter.scala:87:24] wire out_roready_113; // @[RegisterRouter.scala:87:24] wire out_roready_114; // @[RegisterRouter.scala:87:24] wire out_roready_115; // @[RegisterRouter.scala:87:24] wire out_roready_116; // @[RegisterRouter.scala:87:24] wire out_roready_117; // @[RegisterRouter.scala:87:24] wire out_roready_118; // @[RegisterRouter.scala:87:24] wire out_roready_119; // @[RegisterRouter.scala:87:24] wire out_roready_120; // @[RegisterRouter.scala:87:24] wire out_roready_121; // @[RegisterRouter.scala:87:24] wire out_roready_122; // @[RegisterRouter.scala:87:24] wire out_roready_123; // @[RegisterRouter.scala:87:24] wire out_roready_124; // @[RegisterRouter.scala:87:24] wire out_roready_125; // @[RegisterRouter.scala:87:24] wire out_roready_126; // @[RegisterRouter.scala:87:24] wire out_roready_127; // @[RegisterRouter.scala:87:24] wire out_roready_128; // @[RegisterRouter.scala:87:24] wire out_roready_129; // @[RegisterRouter.scala:87:24] wire out_roready_130; // @[RegisterRouter.scala:87:24] wire out_roready_131; // @[RegisterRouter.scala:87:24] wire out_roready_132; // @[RegisterRouter.scala:87:24] wire out_roready_133; // @[RegisterRouter.scala:87:24] wire out_roready_134; // @[RegisterRouter.scala:87:24] wire out_roready_135; // @[RegisterRouter.scala:87:24] wire out_roready_136; // @[RegisterRouter.scala:87:24] wire out_roready_137; // @[RegisterRouter.scala:87:24] wire out_roready_138; // @[RegisterRouter.scala:87:24] wire out_roready_139; // @[RegisterRouter.scala:87:24] wire out_roready_140; // @[RegisterRouter.scala:87:24] wire out_roready_141; // @[RegisterRouter.scala:87:24] wire out_roready_142; // @[RegisterRouter.scala:87:24] wire out_roready_143; // @[RegisterRouter.scala:87:24] wire out_roready_144; // @[RegisterRouter.scala:87:24] wire out_roready_145; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_24; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_248; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_40; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_168; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_144; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_36; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_20; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_192; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_44; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_172; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_100; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_152; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_188; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_232; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_28; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_244; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_156; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_136; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_184; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_132; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_140; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_92; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_180; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_32; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_160; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_48; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_176; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_164; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_96; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_148; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_80; // @[RegisterRouter.scala:87:24] wire out_woready_0; // @[RegisterRouter.scala:87:24] wire out_woready_1; // @[RegisterRouter.scala:87:24] wire out_woready_2; // @[RegisterRouter.scala:87:24] wire out_woready_3; // @[RegisterRouter.scala:87:24] wire out_woready_4; // @[RegisterRouter.scala:87:24] wire out_woready_5; // @[RegisterRouter.scala:87:24] wire out_woready_6; // @[RegisterRouter.scala:87:24] wire out_woready_7; // @[RegisterRouter.scala:87:24] wire out_woready_8; // @[RegisterRouter.scala:87:24] wire out_woready_9; // @[RegisterRouter.scala:87:24] wire out_woready_10; // @[RegisterRouter.scala:87:24] wire out_woready_11; // @[RegisterRouter.scala:87:24] wire out_woready_12; // @[RegisterRouter.scala:87:24] wire out_woready_13; // @[RegisterRouter.scala:87:24] wire out_woready_14; // @[RegisterRouter.scala:87:24] wire out_woready_15; // @[RegisterRouter.scala:87:24] wire out_woready_16; // @[RegisterRouter.scala:87:24] wire out_woready_17; // @[RegisterRouter.scala:87:24] wire out_woready_18; // @[RegisterRouter.scala:87:24] wire out_woready_19; // @[RegisterRouter.scala:87:24] wire out_woready_20; // @[RegisterRouter.scala:87:24] wire out_woready_21; // @[RegisterRouter.scala:87:24] wire out_woready_22; // @[RegisterRouter.scala:87:24] wire out_woready_23; // @[RegisterRouter.scala:87:24] wire out_woready_24; // @[RegisterRouter.scala:87:24] wire out_woready_25; // @[RegisterRouter.scala:87:24] wire out_woready_26; // @[RegisterRouter.scala:87:24] wire out_woready_27; // @[RegisterRouter.scala:87:24] wire out_woready_28; // @[RegisterRouter.scala:87:24] wire out_woready_29; // @[RegisterRouter.scala:87:24] wire out_woready_30; // @[RegisterRouter.scala:87:24] wire out_woready_31; // @[RegisterRouter.scala:87:24] wire out_woready_32; // @[RegisterRouter.scala:87:24] wire out_woready_33; // @[RegisterRouter.scala:87:24] wire out_woready_34; // @[RegisterRouter.scala:87:24] wire out_woready_35; // @[RegisterRouter.scala:87:24] wire out_woready_36; // @[RegisterRouter.scala:87:24] wire out_woready_37; // @[RegisterRouter.scala:87:24] wire out_woready_38; // @[RegisterRouter.scala:87:24] wire out_woready_39; // @[RegisterRouter.scala:87:24] wire out_woready_40; // @[RegisterRouter.scala:87:24] wire out_woready_41; // @[RegisterRouter.scala:87:24] wire out_woready_42; // @[RegisterRouter.scala:87:24] wire out_woready_43; // @[RegisterRouter.scala:87:24] wire out_woready_44; // @[RegisterRouter.scala:87:24] wire out_woready_45; // @[RegisterRouter.scala:87:24] wire out_woready_46; // @[RegisterRouter.scala:87:24] wire out_woready_47; // @[RegisterRouter.scala:87:24] wire out_woready_48; // @[RegisterRouter.scala:87:24] wire out_woready_49; // @[RegisterRouter.scala:87:24] wire out_woready_50; // @[RegisterRouter.scala:87:24] wire out_woready_51; // @[RegisterRouter.scala:87:24] wire out_woready_52; // @[RegisterRouter.scala:87:24] wire out_woready_53; // @[RegisterRouter.scala:87:24] wire out_woready_54; // @[RegisterRouter.scala:87:24] wire out_woready_55; // @[RegisterRouter.scala:87:24] wire out_woready_56; // @[RegisterRouter.scala:87:24] wire out_woready_57; // @[RegisterRouter.scala:87:24] wire out_woready_58; // @[RegisterRouter.scala:87:24] wire out_woready_59; // @[RegisterRouter.scala:87:24] wire out_woready_60; // @[RegisterRouter.scala:87:24] wire out_woready_61; // @[RegisterRouter.scala:87:24] wire out_woready_62; // @[RegisterRouter.scala:87:24] wire out_woready_63; // @[RegisterRouter.scala:87:24] wire out_woready_64; // @[RegisterRouter.scala:87:24] wire out_woready_65; // @[RegisterRouter.scala:87:24] wire out_woready_66; // @[RegisterRouter.scala:87:24] wire out_woready_67; // @[RegisterRouter.scala:87:24] wire out_woready_68; // @[RegisterRouter.scala:87:24] wire out_woready_69; // @[RegisterRouter.scala:87:24] wire out_woready_70; // @[RegisterRouter.scala:87:24] wire out_woready_71; // @[RegisterRouter.scala:87:24] wire out_woready_72; // @[RegisterRouter.scala:87:24] wire out_woready_73; // @[RegisterRouter.scala:87:24] wire out_woready_74; // @[RegisterRouter.scala:87:24] wire out_woready_75; // @[RegisterRouter.scala:87:24] wire out_woready_76; // @[RegisterRouter.scala:87:24] wire out_woready_77; // @[RegisterRouter.scala:87:24] wire out_woready_78; // @[RegisterRouter.scala:87:24] wire out_woready_79; // @[RegisterRouter.scala:87:24] wire out_woready_80; // @[RegisterRouter.scala:87:24] wire out_woready_81; // @[RegisterRouter.scala:87:24] wire out_woready_82; // @[RegisterRouter.scala:87:24] wire out_woready_83; // @[RegisterRouter.scala:87:24] wire out_woready_84; // @[RegisterRouter.scala:87:24] wire out_woready_85; // @[RegisterRouter.scala:87:24] wire out_woready_86; // @[RegisterRouter.scala:87:24] wire out_woready_87; // @[RegisterRouter.scala:87:24] wire out_woready_88; // @[RegisterRouter.scala:87:24] wire out_woready_89; // @[RegisterRouter.scala:87:24] wire out_woready_90; // @[RegisterRouter.scala:87:24] wire out_woready_91; // @[RegisterRouter.scala:87:24] wire out_woready_92; // @[RegisterRouter.scala:87:24] wire out_woready_93; // @[RegisterRouter.scala:87:24] wire out_woready_94; // @[RegisterRouter.scala:87:24] wire out_woready_95; // @[RegisterRouter.scala:87:24] wire out_woready_96; // @[RegisterRouter.scala:87:24] wire out_woready_97; // @[RegisterRouter.scala:87:24] wire out_woready_98; // @[RegisterRouter.scala:87:24] wire out_woready_99; // @[RegisterRouter.scala:87:24] wire out_woready_100; // @[RegisterRouter.scala:87:24] wire out_woready_101; // @[RegisterRouter.scala:87:24] wire out_woready_102; // @[RegisterRouter.scala:87:24] wire out_woready_103; // @[RegisterRouter.scala:87:24] wire out_woready_104; // @[RegisterRouter.scala:87:24] wire out_woready_105; // @[RegisterRouter.scala:87:24] wire out_woready_106; // @[RegisterRouter.scala:87:24] wire out_woready_107; // @[RegisterRouter.scala:87:24] wire out_woready_108; // @[RegisterRouter.scala:87:24] wire out_woready_109; // @[RegisterRouter.scala:87:24] wire out_woready_110; // @[RegisterRouter.scala:87:24] wire out_woready_111; // @[RegisterRouter.scala:87:24] wire out_woready_112; // @[RegisterRouter.scala:87:24] wire out_woready_113; // @[RegisterRouter.scala:87:24] wire out_woready_114; // @[RegisterRouter.scala:87:24] wire out_woready_115; // @[RegisterRouter.scala:87:24] wire out_woready_116; // @[RegisterRouter.scala:87:24] wire out_woready_117; // @[RegisterRouter.scala:87:24] wire out_woready_118; // @[RegisterRouter.scala:87:24] wire out_woready_119; // @[RegisterRouter.scala:87:24] wire out_woready_120; // @[RegisterRouter.scala:87:24] wire out_woready_121; // @[RegisterRouter.scala:87:24] wire out_woready_122; // @[RegisterRouter.scala:87:24] wire out_woready_123; // @[RegisterRouter.scala:87:24] wire out_woready_124; // @[RegisterRouter.scala:87:24] wire out_woready_125; // @[RegisterRouter.scala:87:24] wire out_woready_126; // @[RegisterRouter.scala:87:24] wire out_woready_127; // @[RegisterRouter.scala:87:24] wire out_woready_128; // @[RegisterRouter.scala:87:24] wire out_woready_129; // @[RegisterRouter.scala:87:24] wire out_woready_130; // @[RegisterRouter.scala:87:24] wire out_woready_131; // @[RegisterRouter.scala:87:24] wire out_woready_132; // @[RegisterRouter.scala:87:24] wire out_woready_133; // @[RegisterRouter.scala:87:24] wire out_woready_134; // @[RegisterRouter.scala:87:24] wire out_woready_135; // @[RegisterRouter.scala:87:24] wire out_woready_136; // @[RegisterRouter.scala:87:24] wire out_woready_137; // @[RegisterRouter.scala:87:24] wire out_woready_138; // @[RegisterRouter.scala:87:24] wire out_woready_139; // @[RegisterRouter.scala:87:24] wire out_woready_140; // @[RegisterRouter.scala:87:24] wire out_woready_141; // @[RegisterRouter.scala:87:24] wire out_woready_142; // @[RegisterRouter.scala:87:24] wire out_woready_143; // @[RegisterRouter.scala:87:24] wire out_woready_144; // @[RegisterRouter.scala:87:24] wire out_woready_145; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_4 = {8{_out_frontMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_5 = {8{_out_frontMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_6 = {8{_out_frontMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_7 = {8{_out_frontMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo = {_out_frontMask_T_5, _out_frontMask_T_4}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi = {_out_frontMask_T_7, _out_frontMask_T_6}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask = {out_frontMask_hi, out_frontMask_lo}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_rimask_T_4 = out_frontMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_wimask_T_4 = out_frontMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_rimask_T_63 = out_frontMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_wimask_T_63 = out_frontMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_rimask_T_68 = out_frontMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_wimask_T_68 = out_frontMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_rimask_T_81 = out_frontMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_wimask_T_81 = out_frontMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_rimask_T_140 = out_frontMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_wimask_T_140 = out_frontMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_rimask_T_145 = out_frontMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_wimask_T_145 = out_frontMask; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_4 = {8{_out_backMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_5 = {8{_out_backMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_6 = {8{_out_backMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_7 = {8{_out_backMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo = {_out_backMask_T_5, _out_backMask_T_4}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi = {_out_backMask_T_7, _out_backMask_T_6}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask = {out_backMask_hi, out_backMask_lo}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_romask_T_4 = out_backMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_womask_T_4 = out_backMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_romask_T_63 = out_backMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_womask_T_63 = out_backMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_romask_T_68 = out_backMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_womask_T_68 = out_backMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_romask_T_81 = out_backMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_womask_T_81 = out_backMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_romask_T_140 = out_backMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_womask_T_140 = out_backMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_romask_T_145 = out_backMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_womask_T_145 = out_backMask; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_5 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_5 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_9 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_9 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_13 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_13 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_17 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_17 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_21 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_21 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_25 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_25 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_29 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_29 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_48 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_48 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_52 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_52 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_55 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_55 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_59 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_59 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_64 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_64 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_69 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_69 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_73 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_73 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_77 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_77 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_101 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_101 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_105 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_105 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_116 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_116 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_120 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_120 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_124 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_124 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_128 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_128 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_132 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_132 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_136 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_136 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_141 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_141 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire out_rimask = \|_out_rimask_T; // @[RegisterRouter.scala:87:24] wire out_wimask = &_out_wimask_T; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_5 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_5 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_9 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_9 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_13 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_13 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_17 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_17 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_21 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_21 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_25 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_25 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_29 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_29 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_48 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_48 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_52 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_52 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_55 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_55 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_59 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_59 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_64 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_64 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_69 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_69 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_73 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_73 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_77 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_77 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_101 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_101 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_105 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_105 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_116 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_116 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_120 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_120 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_124 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_124 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_128 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_128 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_132 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_132 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_136 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_136 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_141 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_141 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire out_romask = \|_out_romask_T; // @[RegisterRouter.scala:87:24] wire out_womask = &_out_womask_T; // @[RegisterRouter.scala:87:24] wire out_f_rivalid = out_rivalid_0 & out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_69 = out_f_rivalid; // @[RegisterRouter.scala:87:24] assign out_f_roready = out_roready_0 & out_romask; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_4 = out_f_roready; // @[RegisterRouter.scala:87:24] wire _out_T_70 = out_f_roready; // @[RegisterRouter.scala:87:24] wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_71 = out_f_wivalid; // @[RegisterRouter.scala:87:24] assign out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_4 = out_f_woready; // @[RegisterRouter.scala:87:24] wire _out_T_72 = out_f_woready; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_68 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_123 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_167 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_211 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_255 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_299 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_343 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_387 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_578 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_622 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_653 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_697 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_752 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_807 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_851 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_895 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1119 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1163 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1272 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1316 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1360 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1404 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1448 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1492 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1547 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_4 = out_f_woready ? _out_T_68 : abstractDataMem_4; // @[RegisterRouter.scala:87:24] wire _out_T_73 = ~out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_74 = ~out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_75 = ~out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_76 = ~out_womask; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_78 = _out_T_77; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T = _out_T_78; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_6 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_6 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_10 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_10 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_14 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_14 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_18 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_18 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_22 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_22 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_26 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_26 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_30 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_30 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_49 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_49 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_53 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_53 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_56 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_56 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_60 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_60 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_65 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_65 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_70 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_70 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_74 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_74 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_78 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_78 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_102 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_102 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_106 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_106 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_117 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_117 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_121 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_121 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_125 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_125 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_129 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_129 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_133 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_133 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_137 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_137 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_142 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_142 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire out_rimask_1 = \|_out_rimask_T_1; // @[RegisterRouter.scala:87:24] wire out_wimask_1 = &_out_wimask_T_1; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_6 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_6 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_10 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_10 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_14 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_14 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_18 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_18 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_22 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_22 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_26 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_26 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_30 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_30 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_49 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_49 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_53 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_53 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_56 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_56 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_60 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_60 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_65 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_65 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_70 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_70 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_74 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_74 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_78 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_78 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_102 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_102 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_106 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_106 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_117 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_117 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_121 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_121 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_125 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_125 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_129 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_129 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_133 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_133 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_137 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_137 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_142 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_142 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire out_romask_1 = \|_out_romask_T_1; // @[RegisterRouter.scala:87:24] wire out_womask_1 = &_out_womask_T_1; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1 = out_rivalid_1 & out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_80 = out_f_rivalid_1; // @[RegisterRouter.scala:87:24] assign out_f_roready_1 = out_roready_1 & out_romask_1; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_5 = out_f_roready_1; // @[RegisterRouter.scala:87:24] wire _out_T_81 = out_f_roready_1; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1 = out_wivalid_1 & out_wimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_82 = out_f_wivalid_1; // @[RegisterRouter.scala:87:24] assign out_f_woready_1 = out_woready_1 & out_womask_1; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_5 = out_f_woready_1; // @[RegisterRouter.scala:87:24] wire _out_T_83 = out_f_woready_1; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_79 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_134 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_178 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_222 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_266 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_310 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_354 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_398 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_589 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_633 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_664 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_708 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_763 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_818 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_862 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_906 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1130 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1174 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1283 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1327 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1371 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1415 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1459 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1503 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1558 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_5 = out_f_woready_1 ? _out_T_79 : abstractDataMem_5; // @[RegisterRouter.scala:87:24] wire _out_T_84 = ~out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_85 = ~out_wimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_86 = ~out_romask_1; // @[RegisterRouter.scala:87:24] wire _out_T_87 = ~out_womask_1; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend = {abstractDataMem_5, _out_prepend_T}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_88 = out_prepend; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_89 = _out_T_88; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1 = _out_T_89; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_2 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_2 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_7 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_7 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_11 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_11 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_15 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_15 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_19 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_19 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_23 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_23 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_27 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_27 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_31 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_31 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_50 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_50 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_57 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_57 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_61 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_61 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_66 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_66 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_71 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_71 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_75 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_75 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_79 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_79 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_103 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_103 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_107 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_107 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_118 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_118 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_122 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_122 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_126 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_126 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_130 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_130 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_134 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_134 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_138 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_138 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_143 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_143 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire out_rimask_2 = \|_out_rimask_T_2; // @[RegisterRouter.scala:87:24] wire out_wimask_2 = &_out_wimask_T_2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_2 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_2 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_7 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_7 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_11 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_11 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_15 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_15 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_19 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_19 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_23 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_23 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_27 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_27 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_31 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_31 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_50 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_50 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_57 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_57 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_61 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_61 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_66 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_66 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_71 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_71 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_75 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_75 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_79 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_79 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_103 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_103 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_107 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_107 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_118 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_118 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_122 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_122 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_126 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_126 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_130 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_130 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_134 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_134 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_138 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_138 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_143 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_143 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire out_romask_2 = \|_out_romask_T_2; // @[RegisterRouter.scala:87:24] wire out_womask_2 = &_out_womask_T_2; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_2 = out_rivalid_2 & out_rimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_91 = out_f_rivalid_2; // @[RegisterRouter.scala:87:24] assign out_f_roready_2 = out_roready_2 & out_romask_2; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_6 = out_f_roready_2; // @[RegisterRouter.scala:87:24] wire _out_T_92 = out_f_roready_2; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_2 = out_wivalid_2 & out_wimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_93 = out_f_wivalid_2; // @[RegisterRouter.scala:87:24] assign out_f_woready_2 = out_woready_2 & out_womask_2; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_6 = out_f_woready_2; // @[RegisterRouter.scala:87:24] wire _out_T_94 = out_f_woready_2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_90 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_145 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_189 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_233 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_277 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_321 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_365 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_409 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_600 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_675 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_719 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_774 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_829 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_873 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_917 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1141 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1185 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1294 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1338 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1382 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1426 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1470 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1514 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1569 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_6 = out_f_woready_2 ? _out_T_90 : abstractDataMem_6; // @[RegisterRouter.scala:87:24] wire _out_T_95 = ~out_rimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_96 = ~out_wimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_97 = ~out_romask_2; // @[RegisterRouter.scala:87:24] wire _out_T_98 = ~out_womask_2; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1 = {abstractDataMem_6, _out_prepend_T_1}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_99 = out_prepend_1; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_100 = _out_T_99; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_2 = _out_T_100; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_3 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_3 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_8 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_8 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_12 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_12 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_16 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_16 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_20 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_20 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_24 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_24 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_28 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_28 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_32 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_32 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_51 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_51 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_58 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_58 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_62 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_62 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_67 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_67 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_72 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_72 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_76 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_76 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_80 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_80 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_104 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_104 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_108 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_108 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_119 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_119 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_123 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_123 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_127 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_127 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_131 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_131 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_135 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_135 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_139 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_139 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_144 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_144 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire out_rimask_3 = \|_out_rimask_T_3; // @[RegisterRouter.scala:87:24] wire out_wimask_3 = &_out_wimask_T_3; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_3 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_3 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_8 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_8 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_12 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_12 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_16 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_16 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_20 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_20 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_24 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_24 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_28 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_28 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_32 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_32 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_51 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_51 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_58 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_58 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_62 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_62 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_67 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_67 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_72 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_72 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_76 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_76 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_80 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_80 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_104 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_104 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_108 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_108 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_119 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_119 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_123 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_123 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_127 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_127 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_131 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_131 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_135 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_135 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_139 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_139 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_144 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_144 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire out_romask_3 = \|_out_romask_T_3; // @[RegisterRouter.scala:87:24] wire out_womask_3 = &_out_womask_T_3; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_3 = out_rivalid_3 & out_rimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_102 = out_f_rivalid_3; // @[RegisterRouter.scala:87:24] assign out_f_roready_3 = out_roready_3 & out_romask_3; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_7 = out_f_roready_3; // @[RegisterRouter.scala:87:24] wire _out_T_103 = out_f_roready_3; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_3 = out_wivalid_3 & out_wimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_104 = out_f_wivalid_3; // @[RegisterRouter.scala:87:24] assign out_f_woready_3 = out_woready_3 & out_womask_3; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_7 = out_f_woready_3; // @[RegisterRouter.scala:87:24] wire _out_T_105 = out_f_woready_3; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_101 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_156 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_200 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_244 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_288 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_332 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_376 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_420 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_611 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_686 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_730 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_785 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_840 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_884 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_928 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1152 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1196 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1305 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1349 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1393 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1437 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1481 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1525 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1580 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_7 = out_f_woready_3 ? _out_T_101 : abstractDataMem_7; // @[RegisterRouter.scala:87:24] wire _out_T_106 = ~out_rimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_107 = ~out_wimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_108 = ~out_romask_3; // @[RegisterRouter.scala:87:24] wire _out_T_109 = ~out_womask_3; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_2 = {abstractDataMem_7, _out_prepend_T_2}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_110 = out_prepend_2; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_111 = _out_T_110; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_5 = _out_T_111; // @[MuxLiteral.scala:49:48] wire out_rimask_4 = \|_out_rimask_T_4; // @[RegisterRouter.scala:87:24] wire out_wimask_4 = &_out_wimask_T_4; // @[RegisterRouter.scala:87:24] wire out_romask_4 = \|_out_romask_T_4; // @[RegisterRouter.scala:87:24] wire out_womask_4 = &_out_womask_T_4; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_4 = out_rivalid_4 & out_rimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_113 = out_f_rivalid_4; // @[RegisterRouter.scala:87:24] assign out_f_roready_4 = out_roready_4 & out_romask_4; // @[RegisterRouter.scala:87:24] assign SBDATARdEn_1 = out_f_roready_4; // @[RegisterRouter.scala:87:24] wire _out_T_114 = out_f_roready_4; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_4 = out_wivalid_4 & out_wimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_115 = out_f_wivalid_4; // @[RegisterRouter.scala:87:24] assign out_f_woready_4 = out_woready_4 & out_womask_4; // @[RegisterRouter.scala:87:24] assign SBDATAWrEn_1 = out_f_woready_4; // @[RegisterRouter.scala:87:24] wire _out_T_116 = out_f_woready_4; // @[RegisterRouter.scala:87:24] assign SBDATAWrData_1 = out_f_woready_4 ? _out_T_112 : 32'h0; // @[RegisterRouter.scala:87:24] wire _out_T_117 = ~out_rimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_118 = ~out_wimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_119 = ~out_romask_4; // @[RegisterRouter.scala:87:24] wire _out_T_120 = ~out_womask_4; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_122 = _out_T_121; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_61 = _out_T_122; // @[MuxLiteral.scala:49:48] wire out_rimask_5 = \|_out_rimask_T_5; // @[RegisterRouter.scala:87:24] wire out_wimask_5 = &_out_wimask_T_5; // @[RegisterRouter.scala:87:24] wire out_romask_5 = \|_out_romask_T_5; // @[RegisterRouter.scala:87:24] wire out_womask_5 = &_out_womask_T_5; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_5 = out_rivalid_5 & out_rimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_124 = out_f_rivalid_5; // @[RegisterRouter.scala:87:24] assign out_f_roready_5 = out_roready_5 & out_romask_5; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_20 = out_f_roready_5; // @[RegisterRouter.scala:87:24] wire _out_T_125 = out_f_roready_5; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_5 = out_wivalid_5 & out_wimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_126 = out_f_wivalid_5; // @[RegisterRouter.scala:87:24] assign out_f_woready_5 = out_woready_5 & out_womask_5; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_20 = out_f_woready_5; // @[RegisterRouter.scala:87:24] wire _out_T_127 = out_f_woready_5; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_20 = out_f_woready_5 ? _out_T_123 : abstractDataMem_20; // @[RegisterRouter.scala:87:24] wire _out_T_128 = ~out_rimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_129 = ~out_wimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_130 = ~out_romask_5; // @[RegisterRouter.scala:87:24] wire _out_T_131 = ~out_womask_5; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_133 = _out_T_132; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_3 = _out_T_133; // @[RegisterRouter.scala:87:24] wire out_rimask_6 = \|_out_rimask_T_6; // @[RegisterRouter.scala:87:24] wire out_wimask_6 = &_out_wimask_T_6; // @[RegisterRouter.scala:87:24] wire out_romask_6 = \|_out_romask_T_6; // @[RegisterRouter.scala:87:24] wire out_womask_6 = &_out_womask_T_6; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_6 = out_rivalid_6 & out_rimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_135 = out_f_rivalid_6; // @[RegisterRouter.scala:87:24] assign out_f_roready_6 = out_roready_6 & out_romask_6; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_21 = out_f_roready_6; // @[RegisterRouter.scala:87:24] wire _out_T_136 = out_f_roready_6; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_6 = out_wivalid_6 & out_wimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_137 = out_f_wivalid_6; // @[RegisterRouter.scala:87:24] assign out_f_woready_6 = out_woready_6 & out_womask_6; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_21 = out_f_woready_6; // @[RegisterRouter.scala:87:24] wire _out_T_138 = out_f_woready_6; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_21 = out_f_woready_6 ? _out_T_134 : abstractDataMem_21; // @[RegisterRouter.scala:87:24] wire _out_T_139 = ~out_rimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_140 = ~out_wimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_141 = ~out_romask_6; // @[RegisterRouter.scala:87:24] wire _out_T_142 = ~out_womask_6; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_3 = {abstractDataMem_21, _out_prepend_T_3}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_143 = out_prepend_3; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_144 = _out_T_143; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_4 = _out_T_144; // @[RegisterRouter.scala:87:24] wire out_rimask_7 = \|_out_rimask_T_7; // @[RegisterRouter.scala:87:24] wire out_wimask_7 = &_out_wimask_T_7; // @[RegisterRouter.scala:87:24] wire out_romask_7 = \|_out_romask_T_7; // @[RegisterRouter.scala:87:24] wire out_womask_7 = &_out_womask_T_7; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_7 = out_rivalid_7 & out_rimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_146 = out_f_rivalid_7; // @[RegisterRouter.scala:87:24] assign out_f_roready_7 = out_roready_7 & out_romask_7; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_22 = out_f_roready_7; // @[RegisterRouter.scala:87:24] wire _out_T_147 = out_f_roready_7; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_7 = out_wivalid_7 & out_wimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_148 = out_f_wivalid_7; // @[RegisterRouter.scala:87:24] assign out_f_woready_7 = out_woready_7 & out_womask_7; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_22 = out_f_woready_7; // @[RegisterRouter.scala:87:24] wire _out_T_149 = out_f_woready_7; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_22 = out_f_woready_7 ? _out_T_145 : abstractDataMem_22; // @[RegisterRouter.scala:87:24] wire _out_T_150 = ~out_rimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_151 = ~out_wimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_152 = ~out_romask_7; // @[RegisterRouter.scala:87:24] wire _out_T_153 = ~out_womask_7; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_4 = {abstractDataMem_22, _out_prepend_T_4}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_154 = out_prepend_4; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_155 = _out_T_154; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_5 = _out_T_155; // @[RegisterRouter.scala:87:24] wire out_rimask_8 = \|_out_rimask_T_8; // @[RegisterRouter.scala:87:24] wire out_wimask_8 = &_out_wimask_T_8; // @[RegisterRouter.scala:87:24] wire out_romask_8 = \|_out_romask_T_8; // @[RegisterRouter.scala:87:24] wire out_womask_8 = &_out_womask_T_8; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_8 = out_rivalid_8 & out_rimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_157 = out_f_rivalid_8; // @[RegisterRouter.scala:87:24] assign out_f_roready_8 = out_roready_8 & out_romask_8; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_23 = out_f_roready_8; // @[RegisterRouter.scala:87:24] wire _out_T_158 = out_f_roready_8; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_8 = out_wivalid_8 & out_wimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_159 = out_f_wivalid_8; // @[RegisterRouter.scala:87:24] assign out_f_woready_8 = out_woready_8 & out_womask_8; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_23 = out_f_woready_8; // @[RegisterRouter.scala:87:24] wire _out_T_160 = out_f_woready_8; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_23 = out_f_woready_8 ? _out_T_156 : abstractDataMem_23; // @[RegisterRouter.scala:87:24] wire _out_T_161 = ~out_rimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_162 = ~out_wimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_163 = ~out_romask_8; // @[RegisterRouter.scala:87:24] wire _out_T_164 = ~out_womask_8; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_5 = {abstractDataMem_23, _out_prepend_T_5}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_165 = out_prepend_5; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_166 = _out_T_165; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_9 = _out_T_166; // @[MuxLiteral.scala:49:48] wire out_rimask_9 = \|_out_rimask_T_9; // @[RegisterRouter.scala:87:24] wire out_wimask_9 = &_out_wimask_T_9; // @[RegisterRouter.scala:87:24] wire out_romask_9 = \|_out_romask_T_9; // @[RegisterRouter.scala:87:24] wire out_womask_9 = &_out_womask_T_9; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_9 = out_rivalid_9 & out_rimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_168 = out_f_rivalid_9; // @[RegisterRouter.scala:87:24] assign out_f_roready_9 = out_roready_9 & out_romask_9; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_36 = out_f_roready_9; // @[RegisterRouter.scala:87:24] wire _out_T_169 = out_f_roready_9; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_9 = out_wivalid_9 & out_wimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_170 = out_f_wivalid_9; // @[RegisterRouter.scala:87:24] assign out_f_woready_9 = out_woready_9 & out_womask_9; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_36 = out_f_woready_9; // @[RegisterRouter.scala:87:24] wire _out_T_171 = out_f_woready_9; // @[RegisterRouter.scala:87:24] assign programBufferNxt_36 = out_f_woready_9 ? _out_T_167 : programBufferMem_36; // @[RegisterRouter.scala:87:24] wire _out_T_172 = ~out_rimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_173 = ~out_wimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_174 = ~out_romask_9; // @[RegisterRouter.scala:87:24] wire _out_T_175 = ~out_womask_9; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_177 = _out_T_176; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_6 = _out_T_177; // @[RegisterRouter.scala:87:24] wire out_rimask_10 = \|_out_rimask_T_10; // @[RegisterRouter.scala:87:24] wire out_wimask_10 = &_out_wimask_T_10; // @[RegisterRouter.scala:87:24] wire out_romask_10 = \|_out_romask_T_10; // @[RegisterRouter.scala:87:24] wire out_womask_10 = &_out_womask_T_10; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_10 = out_rivalid_10 & out_rimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_179 = out_f_rivalid_10; // @[RegisterRouter.scala:87:24] assign out_f_roready_10 = out_roready_10 & out_romask_10; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_37 = out_f_roready_10; // @[RegisterRouter.scala:87:24] wire _out_T_180 = out_f_roready_10; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_10 = out_wivalid_10 & out_wimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_181 = out_f_wivalid_10; // @[RegisterRouter.scala:87:24] assign out_f_woready_10 = out_woready_10 & out_womask_10; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_37 = out_f_woready_10; // @[RegisterRouter.scala:87:24] wire _out_T_182 = out_f_woready_10; // @[RegisterRouter.scala:87:24] assign programBufferNxt_37 = out_f_woready_10 ? _out_T_178 : programBufferMem_37; // @[RegisterRouter.scala:87:24] wire _out_T_183 = ~out_rimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_184 = ~out_wimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_185 = ~out_romask_10; // @[RegisterRouter.scala:87:24] wire _out_T_186 = ~out_womask_10; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_6 = {programBufferMem_37, _out_prepend_T_6}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_187 = out_prepend_6; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_188 = _out_T_187; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_7 = _out_T_188; // @[RegisterRouter.scala:87:24] wire out_rimask_11 = \|_out_rimask_T_11; // @[RegisterRouter.scala:87:24] wire out_wimask_11 = &_out_wimask_T_11; // @[RegisterRouter.scala:87:24] wire out_romask_11 = \|_out_romask_T_11; // @[RegisterRouter.scala:87:24] wire out_womask_11 = &_out_womask_T_11; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_11 = out_rivalid_11 & out_rimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_190 = out_f_rivalid_11; // @[RegisterRouter.scala:87:24] assign out_f_roready_11 = out_roready_11 & out_romask_11; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_38 = out_f_roready_11; // @[RegisterRouter.scala:87:24] wire _out_T_191 = out_f_roready_11; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_11 = out_wivalid_11 & out_wimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_192 = out_f_wivalid_11; // @[RegisterRouter.scala:87:24] assign out_f_woready_11 = out_woready_11 & out_womask_11; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_38 = out_f_woready_11; // @[RegisterRouter.scala:87:24] wire _out_T_193 = out_f_woready_11; // @[RegisterRouter.scala:87:24] assign programBufferNxt_38 = out_f_woready_11 ? _out_T_189 : programBufferMem_38; // @[RegisterRouter.scala:87:24] wire _out_T_194 = ~out_rimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_195 = ~out_wimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_196 = ~out_romask_11; // @[RegisterRouter.scala:87:24] wire _out_T_197 = ~out_womask_11; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_7 = {programBufferMem_38, _out_prepend_T_7}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_198 = out_prepend_7; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_199 = _out_T_198; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_8 = _out_T_199; // @[RegisterRouter.scala:87:24] wire out_rimask_12 = \|_out_rimask_T_12; // @[RegisterRouter.scala:87:24] wire out_wimask_12 = &_out_wimask_T_12; // @[RegisterRouter.scala:87:24] wire out_romask_12 = \|_out_romask_T_12; // @[RegisterRouter.scala:87:24] wire out_womask_12 = &_out_womask_T_12; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_12 = out_rivalid_12 & out_rimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_201 = out_f_rivalid_12; // @[RegisterRouter.scala:87:24] assign out_f_roready_12 = out_roready_12 & out_romask_12; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_39 = out_f_roready_12; // @[RegisterRouter.scala:87:24] wire _out_T_202 = out_f_roready_12; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_12 = out_wivalid_12 & out_wimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_203 = out_f_wivalid_12; // @[RegisterRouter.scala:87:24] assign out_f_woready_12 = out_woready_12 & out_womask_12; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_39 = out_f_woready_12; // @[RegisterRouter.scala:87:24] wire _out_T_204 = out_f_woready_12; // @[RegisterRouter.scala:87:24] assign programBufferNxt_39 = out_f_woready_12 ? _out_T_200 : programBufferMem_39; // @[RegisterRouter.scala:87:24] wire _out_T_205 = ~out_rimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_206 = ~out_wimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_207 = ~out_romask_12; // @[RegisterRouter.scala:87:24] wire _out_T_208 = ~out_womask_12; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_8 = {programBufferMem_39, _out_prepend_T_8}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_209 = out_prepend_8; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_210 = _out_T_209; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_41 = _out_T_210; // @[MuxLiteral.scala:49:48] wire out_rimask_13 = \|_out_rimask_T_13; // @[RegisterRouter.scala:87:24] wire out_wimask_13 = &_out_wimask_T_13; // @[RegisterRouter.scala:87:24] wire out_romask_13 = \|_out_romask_T_13; // @[RegisterRouter.scala:87:24] wire out_womask_13 = &_out_womask_T_13; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_13 = out_rivalid_13 & out_rimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_212 = out_f_rivalid_13; // @[RegisterRouter.scala:87:24] assign out_f_roready_13 = out_roready_13 & out_romask_13; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_12 = out_f_roready_13; // @[RegisterRouter.scala:87:24] wire _out_T_213 = out_f_roready_13; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_13 = out_wivalid_13 & out_wimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_214 = out_f_wivalid_13; // @[RegisterRouter.scala:87:24] assign out_f_woready_13 = out_woready_13 & out_womask_13; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_12 = out_f_woready_13; // @[RegisterRouter.scala:87:24] wire _out_T_215 = out_f_woready_13; // @[RegisterRouter.scala:87:24] assign programBufferNxt_12 = out_f_woready_13 ? _out_T_211 : programBufferMem_12; // @[RegisterRouter.scala:87:24] wire _out_T_216 = ~out_rimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_217 = ~out_wimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_218 = ~out_romask_13; // @[RegisterRouter.scala:87:24] wire _out_T_219 = ~out_womask_13; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_221 = _out_T_220; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_9 = _out_T_221; // @[RegisterRouter.scala:87:24] wire out_rimask_14 = \|_out_rimask_T_14; // @[RegisterRouter.scala:87:24] wire out_wimask_14 = &_out_wimask_T_14; // @[RegisterRouter.scala:87:24] wire out_romask_14 = \|_out_romask_T_14; // @[RegisterRouter.scala:87:24] wire out_womask_14 = &_out_womask_T_14; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_14 = out_rivalid_14 & out_rimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_223 = out_f_rivalid_14; // @[RegisterRouter.scala:87:24] assign out_f_roready_14 = out_roready_14 & out_romask_14; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_13 = out_f_roready_14; // @[RegisterRouter.scala:87:24] wire _out_T_224 = out_f_roready_14; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_14 = out_wivalid_14 & out_wimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_225 = out_f_wivalid_14; // @[RegisterRouter.scala:87:24] assign out_f_woready_14 = out_woready_14 & out_womask_14; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_13 = out_f_woready_14; // @[RegisterRouter.scala:87:24] wire _out_T_226 = out_f_woready_14; // @[RegisterRouter.scala:87:24] assign programBufferNxt_13 = out_f_woready_14 ? _out_T_222 : programBufferMem_13; // @[RegisterRouter.scala:87:24] wire _out_T_227 = ~out_rimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_228 = ~out_wimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_229 = ~out_romask_14; // @[RegisterRouter.scala:87:24] wire _out_T_230 = ~out_womask_14; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_9 = {programBufferMem_13, _out_prepend_T_9}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_231 = out_prepend_9; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_232 = _out_T_231; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_10 = _out_T_232; // @[RegisterRouter.scala:87:24] wire out_rimask_15 = \|_out_rimask_T_15; // @[RegisterRouter.scala:87:24] wire out_wimask_15 = &_out_wimask_T_15; // @[RegisterRouter.scala:87:24] wire out_romask_15 = \|_out_romask_T_15; // @[RegisterRouter.scala:87:24] wire out_womask_15 = &_out_womask_T_15; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_15 = out_rivalid_15 & out_rimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_234 = out_f_rivalid_15; // @[RegisterRouter.scala:87:24] assign out_f_roready_15 = out_roready_15 & out_romask_15; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_14 = out_f_roready_15; // @[RegisterRouter.scala:87:24] wire _out_T_235 = out_f_roready_15; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_15 = out_wivalid_15 & out_wimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_236 = out_f_wivalid_15; // @[RegisterRouter.scala:87:24] assign out_f_woready_15 = out_woready_15 & out_womask_15; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_14 = out_f_woready_15; // @[RegisterRouter.scala:87:24] wire _out_T_237 = out_f_woready_15; // @[RegisterRouter.scala:87:24] assign programBufferNxt_14 = out_f_woready_15 ? _out_T_233 : programBufferMem_14; // @[RegisterRouter.scala:87:24] wire _out_T_238 = ~out_rimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_239 = ~out_wimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_240 = ~out_romask_15; // @[RegisterRouter.scala:87:24] wire _out_T_241 = ~out_womask_15; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_10 = {programBufferMem_14, _out_prepend_T_10}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_242 = out_prepend_10; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_243 = _out_T_242; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_11 = _out_T_243; // @[RegisterRouter.scala:87:24] wire out_rimask_16 = \|_out_rimask_T_16; // @[RegisterRouter.scala:87:24] wire out_wimask_16 = &_out_wimask_T_16; // @[RegisterRouter.scala:87:24] wire out_romask_16 = \|_out_romask_T_16; // @[RegisterRouter.scala:87:24] wire out_womask_16 = &_out_womask_T_16; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_16 = out_rivalid_16 & out_rimask_16; // @[RegisterRouter.scala:87:24] wire _out_T_245 = out_f_rivalid_16; // @[RegisterRouter.scala:87:24] assign out_f_roready_16 = out_roready_16 & out_romask_16; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_15 = out_f_roready_16; // @[RegisterRouter.scala:87:24] wire _out_T_246 = out_f_roready_16; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_16 = out_wivalid_16 & out_wimask_16; // @[RegisterRouter.scala:87:24] wire _out_T_247 = out_f_wivalid_16; // @[RegisterRouter.scala:87:24] assign out_f_woready_16 = out_woready_16 & out_womask_16; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_15 = out_f_woready_16; // @[RegisterRouter.scala:87:24] wire _out_T_248 = out_f_woready_16; // @[RegisterRouter.scala:87:24] assign programBufferNxt_15 = out_f_woready_16 ? _out_T_244 : programBufferMem_15; // @[RegisterRouter.scala:87:24] wire _out_T_249 = ~out_rimask_16; // @[RegisterRouter.scala:87:24] wire _out_T_250 = ~out_wimask_16; // @[RegisterRouter.scala:87:24] wire _out_T_251 = ~out_romask_16; // @[RegisterRouter.scala:87:24] wire _out_T_252 = ~out_womask_16; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_11 = {programBufferMem_15, _out_prepend_T_11}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_253 = out_prepend_11; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_254 = _out_T_253; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_35 = _out_T_254; // @[MuxLiteral.scala:49:48] wire out_rimask_17 = \|_out_rimask_T_17; // @[RegisterRouter.scala:87:24] wire out_wimask_17 = &_out_wimask_T_17; // @[RegisterRouter.scala:87:24] wire out_romask_17 = \|_out_romask_T_17; // @[RegisterRouter.scala:87:24] wire out_womask_17 = &_out_womask_T_17; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_17 = out_rivalid_17 & out_rimask_17; // @[RegisterRouter.scala:87:24] wire _out_T_256 = out_f_rivalid_17; // @[RegisterRouter.scala:87:24] assign out_f_roready_17 = out_roready_17 & out_romask_17; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_16 = out_f_roready_17; // @[RegisterRouter.scala:87:24] wire _out_T_257 = out_f_roready_17; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_17 = out_wivalid_17 & out_wimask_17; // @[RegisterRouter.scala:87:24] wire _out_T_258 = out_f_wivalid_17; // @[RegisterRouter.scala:87:24] assign out_f_woready_17 = out_woready_17 & out_womask_17; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_16 = out_f_woready_17; // @[RegisterRouter.scala:87:24] wire _out_T_259 = out_f_woready_17; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_16 = out_f_woready_17 ? _out_T_255 : abstractDataMem_16; // @[RegisterRouter.scala:87:24] wire _out_T_260 = ~out_rimask_17; // @[RegisterRouter.scala:87:24] wire _out_T_261 = ~out_wimask_17; // @[RegisterRouter.scala:87:24] wire _out_T_262 = ~out_romask_17; // @[RegisterRouter.scala:87:24] wire _out_T_263 = ~out_womask_17; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_265 = _out_T_264; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_12 = _out_T_265; // @[RegisterRouter.scala:87:24] wire out_rimask_18 = \|_out_rimask_T_18; // @[RegisterRouter.scala:87:24] wire out_wimask_18 = &_out_wimask_T_18; // @[RegisterRouter.scala:87:24] wire out_romask_18 = \|_out_romask_T_18; // @[RegisterRouter.scala:87:24] wire out_womask_18 = &_out_womask_T_18; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_18 = out_rivalid_18 & out_rimask_18; // @[RegisterRouter.scala:87:24] wire _out_T_267 = out_f_rivalid_18; // @[RegisterRouter.scala:87:24] assign out_f_roready_18 = out_roready_18 & out_romask_18; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_17 = out_f_roready_18; // @[RegisterRouter.scala:87:24] wire _out_T_268 = out_f_roready_18; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_18 = out_wivalid_18 & out_wimask_18; // @[RegisterRouter.scala:87:24] wire _out_T_269 = out_f_wivalid_18; // @[RegisterRouter.scala:87:24] assign out_f_woready_18 = out_woready_18 & out_womask_18; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_17 = out_f_woready_18; // @[RegisterRouter.scala:87:24] wire _out_T_270 = out_f_woready_18; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_17 = out_f_woready_18 ? _out_T_266 : abstractDataMem_17; // @[RegisterRouter.scala:87:24] wire _out_T_271 = ~out_rimask_18; // @[RegisterRouter.scala:87:24] wire _out_T_272 = ~out_wimask_18; // @[RegisterRouter.scala:87:24] wire _out_T_273 = ~out_romask_18; // @[RegisterRouter.scala:87:24] wire _out_T_274 = ~out_womask_18; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_12 = {abstractDataMem_17, _out_prepend_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_275 = out_prepend_12; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_276 = _out_T_275; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_13 = _out_T_276; // @[RegisterRouter.scala:87:24] wire out_rimask_19 = \|_out_rimask_T_19; // @[RegisterRouter.scala:87:24] wire out_wimask_19 = &_out_wimask_T_19; // @[RegisterRouter.scala:87:24] wire out_romask_19 = \|_out_romask_T_19; // @[RegisterRouter.scala:87:24] wire out_womask_19 = &_out_womask_T_19; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_19 = out_rivalid_19 & out_rimask_19; // @[RegisterRouter.scala:87:24] wire _out_T_278 = out_f_rivalid_19; // @[RegisterRouter.scala:87:24] assign out_f_roready_19 = out_roready_19 & out_romask_19; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_18 = out_f_roready_19; // @[RegisterRouter.scala:87:24] wire _out_T_279 = out_f_roready_19; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_19 = out_wivalid_19 & out_wimask_19; // @[RegisterRouter.scala:87:24] wire _out_T_280 = out_f_wivalid_19; // @[RegisterRouter.scala:87:24] assign out_f_woready_19 = out_woready_19 & out_womask_19; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_18 = out_f_woready_19; // @[RegisterRouter.scala:87:24] wire _out_T_281 = out_f_woready_19; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_18 = out_f_woready_19 ? _out_T_277 : abstractDataMem_18; // @[RegisterRouter.scala:87:24] wire _out_T_282 = ~out_rimask_19; // @[RegisterRouter.scala:87:24] wire _out_T_283 = ~out_wimask_19; // @[RegisterRouter.scala:87:24] wire _out_T_284 = ~out_romask_19; // @[RegisterRouter.scala:87:24] wire _out_T_285 = ~out_womask_19; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_13 = {abstractDataMem_18, _out_prepend_T_13}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_286 = out_prepend_13; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_287 = _out_T_286; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_14 = _out_T_287; // @[RegisterRouter.scala:87:24] wire out_rimask_20 = \|_out_rimask_T_20; // @[RegisterRouter.scala:87:24] wire out_wimask_20 = &_out_wimask_T_20; // @[RegisterRouter.scala:87:24] wire out_romask_20 = \|_out_romask_T_20; // @[RegisterRouter.scala:87:24] wire out_womask_20 = &_out_womask_T_20; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_20 = out_rivalid_20 & out_rimask_20; // @[RegisterRouter.scala:87:24] wire _out_T_289 = out_f_rivalid_20; // @[RegisterRouter.scala:87:24] assign out_f_roready_20 = out_roready_20 & out_romask_20; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_19 = out_f_roready_20; // @[RegisterRouter.scala:87:24] wire _out_T_290 = out_f_roready_20; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_20 = out_wivalid_20 & out_wimask_20; // @[RegisterRouter.scala:87:24] wire _out_T_291 = out_f_wivalid_20; // @[RegisterRouter.scala:87:24] assign out_f_woready_20 = out_woready_20 & out_womask_20; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_19 = out_f_woready_20; // @[RegisterRouter.scala:87:24] wire _out_T_292 = out_f_woready_20; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_19 = out_f_woready_20 ? _out_T_288 : abstractDataMem_19; // @[RegisterRouter.scala:87:24] wire _out_T_293 = ~out_rimask_20; // @[RegisterRouter.scala:87:24] wire _out_T_294 = ~out_wimask_20; // @[RegisterRouter.scala:87:24] wire _out_T_295 = ~out_romask_20; // @[RegisterRouter.scala:87:24] wire _out_T_296 = ~out_womask_20; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_14 = {abstractDataMem_19, _out_prepend_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_297 = out_prepend_14; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_298 = _out_T_297; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_8 = _out_T_298; // @[MuxLiteral.scala:49:48] wire out_rimask_21 = \|_out_rimask_T_21; // @[RegisterRouter.scala:87:24] wire out_wimask_21 = &_out_wimask_T_21; // @[RegisterRouter.scala:87:24] wire out_romask_21 = \|_out_romask_T_21; // @[RegisterRouter.scala:87:24] wire out_womask_21 = &_out_womask_T_21; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_21 = out_rivalid_21 & out_rimask_21; // @[RegisterRouter.scala:87:24] wire _out_T_300 = out_f_rivalid_21; // @[RegisterRouter.scala:87:24] assign out_f_roready_21 = out_roready_21 & out_romask_21; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_0 = out_f_roready_21; // @[RegisterRouter.scala:87:24] wire _out_T_301 = out_f_roready_21; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_21 = out_wivalid_21 & out_wimask_21; // @[RegisterRouter.scala:87:24] wire _out_T_302 = out_f_wivalid_21; // @[RegisterRouter.scala:87:24] assign out_f_woready_21 = out_woready_21 & out_womask_21; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_0 = out_f_woready_21; // @[RegisterRouter.scala:87:24] wire _out_T_303 = out_f_woready_21; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_0 = out_f_woready_21 ? _out_T_299 : abstractDataMem_0; // @[RegisterRouter.scala:87:24] wire _out_T_304 = ~out_rimask_21; // @[RegisterRouter.scala:87:24] wire _out_T_305 = ~out_wimask_21; // @[RegisterRouter.scala:87:24] wire _out_T_306 = ~out_romask_21; // @[RegisterRouter.scala:87:24] wire _out_T_307 = ~out_womask_21; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_309 = _out_T_308; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_15 = _out_T_309; // @[RegisterRouter.scala:87:24] wire out_rimask_22 = \|_out_rimask_T_22; // @[RegisterRouter.scala:87:24] wire out_wimask_22 = &_out_wimask_T_22; // @[RegisterRouter.scala:87:24] wire out_romask_22 = \|_out_romask_T_22; // @[RegisterRouter.scala:87:24] wire out_womask_22 = &_out_womask_T_22; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_22 = out_rivalid_22 & out_rimask_22; // @[RegisterRouter.scala:87:24] wire _out_T_311 = out_f_rivalid_22; // @[RegisterRouter.scala:87:24] assign out_f_roready_22 = out_roready_22 & out_romask_22; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_1 = out_f_roready_22; // @[RegisterRouter.scala:87:24] wire _out_T_312 = out_f_roready_22; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_22 = out_wivalid_22 & out_wimask_22; // @[RegisterRouter.scala:87:24] wire _out_T_313 = out_f_wivalid_22; // @[RegisterRouter.scala:87:24] assign out_f_woready_22 = out_woready_22 & out_womask_22; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_1 = out_f_woready_22; // @[RegisterRouter.scala:87:24] wire _out_T_314 = out_f_woready_22; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_1 = out_f_woready_22 ? _out_T_310 : abstractDataMem_1; // @[RegisterRouter.scala:87:24] wire _out_T_315 = ~out_rimask_22; // @[RegisterRouter.scala:87:24] wire _out_T_316 = ~out_wimask_22; // @[RegisterRouter.scala:87:24] wire _out_T_317 = ~out_romask_22; // @[RegisterRouter.scala:87:24] wire _out_T_318 = ~out_womask_22; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_15 = {abstractDataMem_1, _out_prepend_T_15}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_319 = out_prepend_15; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_320 = _out_T_319; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_16 = _out_T_320; // @[RegisterRouter.scala:87:24] wire out_rimask_23 = \|_out_rimask_T_23; // @[RegisterRouter.scala:87:24] wire out_wimask_23 = &_out_wimask_T_23; // @[RegisterRouter.scala:87:24] wire out_romask_23 = \|_out_romask_T_23; // @[RegisterRouter.scala:87:24] wire out_womask_23 = &_out_womask_T_23; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_23 = out_rivalid_23 & out_rimask_23; // @[RegisterRouter.scala:87:24] wire _out_T_322 = out_f_rivalid_23; // @[RegisterRouter.scala:87:24] assign out_f_roready_23 = out_roready_23 & out_romask_23; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_2 = out_f_roready_23; // @[RegisterRouter.scala:87:24] wire _out_T_323 = out_f_roready_23; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_23 = out_wivalid_23 & out_wimask_23; // @[RegisterRouter.scala:87:24] wire _out_T_324 = out_f_wivalid_23; // @[RegisterRouter.scala:87:24] assign out_f_woready_23 = out_woready_23 & out_womask_23; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_2 = out_f_woready_23; // @[RegisterRouter.scala:87:24] wire _out_T_325 = out_f_woready_23; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_2 = out_f_woready_23 ? _out_T_321 : abstractDataMem_2; // @[RegisterRouter.scala:87:24] wire _out_T_326 = ~out_rimask_23; // @[RegisterRouter.scala:87:24] wire _out_T_327 = ~out_wimask_23; // @[RegisterRouter.scala:87:24] wire _out_T_328 = ~out_romask_23; // @[RegisterRouter.scala:87:24] wire _out_T_329 = ~out_womask_23; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_16 = {abstractDataMem_2, _out_prepend_T_16}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_330 = out_prepend_16; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_331 = _out_T_330; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_17 = _out_T_331; // @[RegisterRouter.scala:87:24] wire out_rimask_24 = \|_out_rimask_T_24; // @[RegisterRouter.scala:87:24] wire out_wimask_24 = &_out_wimask_T_24; // @[RegisterRouter.scala:87:24] wire out_romask_24 = \|_out_romask_T_24; // @[RegisterRouter.scala:87:24] wire out_womask_24 = &_out_womask_T_24; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_24 = out_rivalid_24 & out_rimask_24; // @[RegisterRouter.scala:87:24] wire _out_T_333 = out_f_rivalid_24; // @[RegisterRouter.scala:87:24] assign out_f_roready_24 = out_roready_24 & out_romask_24; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_3 = out_f_roready_24; // @[RegisterRouter.scala:87:24] wire _out_T_334 = out_f_roready_24; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_24 = out_wivalid_24 & out_wimask_24; // @[RegisterRouter.scala:87:24] wire _out_T_335 = out_f_wivalid_24; // @[RegisterRouter.scala:87:24] assign out_f_woready_24 = out_woready_24 & out_womask_24; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_3 = out_f_woready_24; // @[RegisterRouter.scala:87:24] wire _out_T_336 = out_f_woready_24; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_3 = out_f_woready_24 ? _out_T_332 : abstractDataMem_3; // @[RegisterRouter.scala:87:24] wire _out_T_337 = ~out_rimask_24; // @[RegisterRouter.scala:87:24] wire _out_T_338 = ~out_wimask_24; // @[RegisterRouter.scala:87:24] wire _out_T_339 = ~out_romask_24; // @[RegisterRouter.scala:87:24] wire _out_T_340 = ~out_womask_24; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_17 = {abstractDataMem_3, _out_prepend_T_17}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_341 = out_prepend_17; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_342 = _out_T_341; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_4 = _out_T_342; // @[MuxLiteral.scala:49:48] wire out_rimask_25 = \|_out_rimask_T_25; // @[RegisterRouter.scala:87:24] wire out_wimask_25 = &_out_wimask_T_25; // @[RegisterRouter.scala:87:24] wire out_romask_25 = \|_out_romask_T_25; // @[RegisterRouter.scala:87:24] wire out_womask_25 = &_out_womask_T_25; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_25 = out_rivalid_25 & out_rimask_25; // @[RegisterRouter.scala:87:24] wire _out_T_344 = out_f_rivalid_25; // @[RegisterRouter.scala:87:24] assign out_f_roready_25 = out_roready_25 & out_romask_25; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_60 = out_f_roready_25; // @[RegisterRouter.scala:87:24] wire _out_T_345 = out_f_roready_25; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_25 = out_wivalid_25 & out_wimask_25; // @[RegisterRouter.scala:87:24] wire _out_T_346 = out_f_wivalid_25; // @[RegisterRouter.scala:87:24] assign out_f_woready_25 = out_woready_25 & out_womask_25; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_60 = out_f_woready_25; // @[RegisterRouter.scala:87:24] wire _out_T_347 = out_f_woready_25; // @[RegisterRouter.scala:87:24] assign programBufferNxt_60 = out_f_woready_25 ? _out_T_343 : programBufferMem_60; // @[RegisterRouter.scala:87:24] wire _out_T_348 = ~out_rimask_25; // @[RegisterRouter.scala:87:24] wire _out_T_349 = ~out_wimask_25; // @[RegisterRouter.scala:87:24] wire _out_T_350 = ~out_romask_25; // @[RegisterRouter.scala:87:24] wire _out_T_351 = ~out_womask_25; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_353 = _out_T_352; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_18 = _out_T_353; // @[RegisterRouter.scala:87:24] wire out_rimask_26 = \|_out_rimask_T_26; // @[RegisterRouter.scala:87:24] wire out_wimask_26 = &_out_wimask_T_26; // @[RegisterRouter.scala:87:24] wire out_romask_26 = \|_out_romask_T_26; // @[RegisterRouter.scala:87:24] wire out_womask_26 = &_out_womask_T_26; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_26 = out_rivalid_26 & out_rimask_26; // @[RegisterRouter.scala:87:24] wire _out_T_355 = out_f_rivalid_26; // @[RegisterRouter.scala:87:24] assign out_f_roready_26 = out_roready_26 & out_romask_26; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_61 = out_f_roready_26; // @[RegisterRouter.scala:87:24] wire _out_T_356 = out_f_roready_26; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_26 = out_wivalid_26 & out_wimask_26; // @[RegisterRouter.scala:87:24] wire _out_T_357 = out_f_wivalid_26; // @[RegisterRouter.scala:87:24] assign out_f_woready_26 = out_woready_26 & out_womask_26; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_61 = out_f_woready_26; // @[RegisterRouter.scala:87:24] wire _out_T_358 = out_f_woready_26; // @[RegisterRouter.scala:87:24] assign programBufferNxt_61 = out_f_woready_26 ? _out_T_354 : programBufferMem_61; // @[RegisterRouter.scala:87:24] wire _out_T_359 = ~out_rimask_26; // @[RegisterRouter.scala:87:24] wire _out_T_360 = ~out_wimask_26; // @[RegisterRouter.scala:87:24] wire _out_T_361 = ~out_romask_26; // @[RegisterRouter.scala:87:24] wire _out_T_362 = ~out_womask_26; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_18 = {programBufferMem_61, _out_prepend_T_18}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_363 = out_prepend_18; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_364 = _out_T_363; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_19 = _out_T_364; // @[RegisterRouter.scala:87:24] wire out_rimask_27 = \|_out_rimask_T_27; // @[RegisterRouter.scala:87:24] wire out_wimask_27 = &_out_wimask_T_27; // @[RegisterRouter.scala:87:24] wire out_romask_27 = \|_out_romask_T_27; // @[RegisterRouter.scala:87:24] wire out_womask_27 = &_out_womask_T_27; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_27 = out_rivalid_27 & out_rimask_27; // @[RegisterRouter.scala:87:24] wire _out_T_366 = out_f_rivalid_27; // @[RegisterRouter.scala:87:24] assign out_f_roready_27 = out_roready_27 & out_romask_27; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_62 = out_f_roready_27; // @[RegisterRouter.scala:87:24] wire _out_T_367 = out_f_roready_27; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_27 = out_wivalid_27 & out_wimask_27; // @[RegisterRouter.scala:87:24] wire _out_T_368 = out_f_wivalid_27; // @[RegisterRouter.scala:87:24] assign out_f_woready_27 = out_woready_27 & out_womask_27; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_62 = out_f_woready_27; // @[RegisterRouter.scala:87:24] wire _out_T_369 = out_f_woready_27; // @[RegisterRouter.scala:87:24] assign programBufferNxt_62 = out_f_woready_27 ? _out_T_365 : programBufferMem_62; // @[RegisterRouter.scala:87:24] wire _out_T_370 = ~out_rimask_27; // @[RegisterRouter.scala:87:24] wire _out_T_371 = ~out_wimask_27; // @[RegisterRouter.scala:87:24] wire _out_T_372 = ~out_romask_27; // @[RegisterRouter.scala:87:24] wire _out_T_373 = ~out_womask_27; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_19 = {programBufferMem_62, _out_prepend_T_19}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_374 = out_prepend_19; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_375 = _out_T_374; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_20 = _out_T_375; // @[RegisterRouter.scala:87:24] wire out_rimask_28 = \|_out_rimask_T_28; // @[RegisterRouter.scala:87:24] wire out_wimask_28 = &_out_wimask_T_28; // @[RegisterRouter.scala:87:24] wire out_romask_28 = \|_out_romask_T_28; // @[RegisterRouter.scala:87:24] wire out_womask_28 = &_out_womask_T_28; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_28 = out_rivalid_28 & out_rimask_28; // @[RegisterRouter.scala:87:24] wire _out_T_377 = out_f_rivalid_28; // @[RegisterRouter.scala:87:24] assign out_f_roready_28 = out_roready_28 & out_romask_28; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_63 = out_f_roready_28; // @[RegisterRouter.scala:87:24] wire _out_T_378 = out_f_roready_28; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_28 = out_wivalid_28 & out_wimask_28; // @[RegisterRouter.scala:87:24] wire _out_T_379 = out_f_wivalid_28; // @[RegisterRouter.scala:87:24] assign out_f_woready_28 = out_woready_28 & out_womask_28; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_63 = out_f_woready_28; // @[RegisterRouter.scala:87:24] wire _out_T_380 = out_f_woready_28; // @[RegisterRouter.scala:87:24] assign programBufferNxt_63 = out_f_woready_28 ? _out_T_376 : programBufferMem_63; // @[RegisterRouter.scala:87:24] wire _out_T_381 = ~out_rimask_28; // @[RegisterRouter.scala:87:24] wire _out_T_382 = ~out_wimask_28; // @[RegisterRouter.scala:87:24] wire _out_T_383 = ~out_romask_28; // @[RegisterRouter.scala:87:24] wire _out_T_384 = ~out_womask_28; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_20 = {programBufferMem_63, _out_prepend_T_20}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_385 = out_prepend_20; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_386 = _out_T_385; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_47 = _out_T_386; // @[MuxLiteral.scala:49:48] wire out_rimask_29 = \|_out_rimask_T_29; // @[RegisterRouter.scala:87:24] wire out_wimask_29 = &_out_wimask_T_29; // @[RegisterRouter.scala:87:24] wire out_romask_29 = \|_out_romask_T_29; // @[RegisterRouter.scala:87:24] wire out_womask_29 = &_out_womask_T_29; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_29 = out_rivalid_29 & out_rimask_29; // @[RegisterRouter.scala:87:24] wire _out_T_388 = out_f_rivalid_29; // @[RegisterRouter.scala:87:24] assign out_f_roready_29 = out_roready_29 & out_romask_29; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_24 = out_f_roready_29; // @[RegisterRouter.scala:87:24] wire _out_T_389 = out_f_roready_29; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_29 = out_wivalid_29 & out_wimask_29; // @[RegisterRouter.scala:87:24] wire _out_T_390 = out_f_wivalid_29; // @[RegisterRouter.scala:87:24] assign out_f_woready_29 = out_woready_29 & out_womask_29; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_24 = out_f_woready_29; // @[RegisterRouter.scala:87:24] wire _out_T_391 = out_f_woready_29; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_24 = out_f_woready_29 ? _out_T_387 : abstractDataMem_24; // @[RegisterRouter.scala:87:24] wire _out_T_392 = ~out_rimask_29; // @[RegisterRouter.scala:87:24] wire _out_T_393 = ~out_wimask_29; // @[RegisterRouter.scala:87:24] wire _out_T_394 = ~out_romask_29; // @[RegisterRouter.scala:87:24] wire _out_T_395 = ~out_womask_29; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_397 = _out_T_396; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_21 = _out_T_397; // @[RegisterRouter.scala:87:24] wire out_rimask_30 = \|_out_rimask_T_30; // @[RegisterRouter.scala:87:24] wire out_wimask_30 = &_out_wimask_T_30; // @[RegisterRouter.scala:87:24] wire out_romask_30 = \|_out_romask_T_30; // @[RegisterRouter.scala:87:24] wire out_womask_30 = &_out_womask_T_30; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_30 = out_rivalid_30 & out_rimask_30; // @[RegisterRouter.scala:87:24] wire _out_T_399 = out_f_rivalid_30; // @[RegisterRouter.scala:87:24] assign out_f_roready_30 = out_roready_30 & out_romask_30; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_25 = out_f_roready_30; // @[RegisterRouter.scala:87:24] wire _out_T_400 = out_f_roready_30; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_30 = out_wivalid_30 & out_wimask_30; // @[RegisterRouter.scala:87:24] wire _out_T_401 = out_f_wivalid_30; // @[RegisterRouter.scala:87:24] assign out_f_woready_30 = out_woready_30 & out_womask_30; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_25 = out_f_woready_30; // @[RegisterRouter.scala:87:24] wire _out_T_402 = out_f_woready_30; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_25 = out_f_woready_30 ? _out_T_398 : abstractDataMem_25; // @[RegisterRouter.scala:87:24] wire _out_T_403 = ~out_rimask_30; // @[RegisterRouter.scala:87:24] wire _out_T_404 = ~out_wimask_30; // @[RegisterRouter.scala:87:24] wire _out_T_405 = ~out_romask_30; // @[RegisterRouter.scala:87:24] wire _out_T_406 = ~out_womask_30; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_21 = {abstractDataMem_25, _out_prepend_T_21}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_407 = out_prepend_21; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_408 = _out_T_407; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_22 = _out_T_408; // @[RegisterRouter.scala:87:24] wire out_rimask_31 = \|_out_rimask_T_31; // @[RegisterRouter.scala:87:24] wire out_wimask_31 = &_out_wimask_T_31; // @[RegisterRouter.scala:87:24] wire out_romask_31 = \|_out_romask_T_31; // @[RegisterRouter.scala:87:24] wire out_womask_31 = &_out_womask_T_31; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_31 = out_rivalid_31 & out_rimask_31; // @[RegisterRouter.scala:87:24] wire _out_T_410 = out_f_rivalid_31; // @[RegisterRouter.scala:87:24] assign out_f_roready_31 = out_roready_31 & out_romask_31; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_26 = out_f_roready_31; // @[RegisterRouter.scala:87:24] wire _out_T_411 = out_f_roready_31; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_31 = out_wivalid_31 & out_wimask_31; // @[RegisterRouter.scala:87:24] wire _out_T_412 = out_f_wivalid_31; // @[RegisterRouter.scala:87:24] assign out_f_woready_31 = out_woready_31 & out_womask_31; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_26 = out_f_woready_31; // @[RegisterRouter.scala:87:24] wire _out_T_413 = out_f_woready_31; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_26 = out_f_woready_31 ? _out_T_409 : abstractDataMem_26; // @[RegisterRouter.scala:87:24] wire _out_T_414 = ~out_rimask_31; // @[RegisterRouter.scala:87:24] wire _out_T_415 = ~out_wimask_31; // @[RegisterRouter.scala:87:24] wire _out_T_416 = ~out_romask_31; // @[RegisterRouter.scala:87:24] wire _out_T_417 = ~out_womask_31; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_22 = {abstractDataMem_26, _out_prepend_T_22}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_418 = out_prepend_22; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_419 = _out_T_418; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_23 = _out_T_419; // @[RegisterRouter.scala:87:24] wire out_rimask_32 = \|_out_rimask_T_32; // @[RegisterRouter.scala:87:24] wire out_wimask_32 = &_out_wimask_T_32; // @[RegisterRouter.scala:87:24] wire out_romask_32 = \|_out_romask_T_32; // @[RegisterRouter.scala:87:24] wire out_womask_32 = &_out_womask_T_32; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_32 = out_rivalid_32 & out_rimask_32; // @[RegisterRouter.scala:87:24] wire _out_T_421 = out_f_rivalid_32; // @[RegisterRouter.scala:87:24] assign out_f_roready_32 = out_roready_32 & out_romask_32; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_27 = out_f_roready_32; // @[RegisterRouter.scala:87:24] wire _out_T_422 = out_f_roready_32; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_32 = out_wivalid_32 & out_wimask_32; // @[RegisterRouter.scala:87:24] wire _out_T_423 = out_f_wivalid_32; // @[RegisterRouter.scala:87:24] assign out_f_woready_32 = out_woready_32 & out_womask_32; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_27 = out_f_woready_32; // @[RegisterRouter.scala:87:24] wire _out_T_424 = out_f_woready_32; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_27 = out_f_woready_32 ? _out_T_420 : abstractDataMem_27; // @[RegisterRouter.scala:87:24] wire _out_T_425 = ~out_rimask_32; // @[RegisterRouter.scala:87:24] wire _out_T_426 = ~out_wimask_32; // @[RegisterRouter.scala:87:24] wire _out_T_427 = ~out_romask_32; // @[RegisterRouter.scala:87:24] wire _out_T_428 = ~out_womask_32; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_23 = {abstractDataMem_27, _out_prepend_T_23}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_429 = out_prepend_23; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_430 = _out_T_429; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_10 = _out_T_430; // @[MuxLiteral.scala:49:48] wire _out_rimask_T_33 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_33 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire out_rimask_33 = _out_rimask_T_33; // @[RegisterRouter.scala:87:24] wire out_wimask_33 = _out_wimask_T_33; // @[RegisterRouter.scala:87:24] wire _out_romask_T_33 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_33 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire out_romask_33 = _out_romask_T_33; // @[RegisterRouter.scala:87:24] wire out_womask_33 = _out_womask_T_33; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_33 = out_rivalid_33 & out_rimask_33; // @[RegisterRouter.scala:87:24] wire _out_T_432 = out_f_rivalid_33; // @[RegisterRouter.scala:87:24] wire out_f_roready_33 = out_roready_33 & out_romask_33; // @[RegisterRouter.scala:87:24] wire _out_T_433 = out_f_roready_33; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_33 = out_wivalid_33 & out_wimask_33; // @[RegisterRouter.scala:87:24] wire out_f_woready_33 = out_woready_33 & out_womask_33; // @[RegisterRouter.scala:87:24] wire _out_T_431 = out_front_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_434 = ~out_rimask_33; // @[RegisterRouter.scala:87:24] wire _out_T_435 = ~out_wimask_33; // @[RegisterRouter.scala:87:24] wire _out_T_436 = ~out_romask_33; // @[RegisterRouter.scala:87:24] wire _out_T_437 = ~out_womask_33; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_34 = out_frontMask[1]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_34 = out_frontMask[1]; // @[RegisterRouter.scala:87:24] wire out_rimask_34 = _out_rimask_T_34; // @[RegisterRouter.scala:87:24] wire out_wimask_34 = _out_wimask_T_34; // @[RegisterRouter.scala:87:24] wire _out_romask_T_34 = out_backMask[1]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_34 = out_backMask[1]; // @[RegisterRouter.scala:87:24] wire out_romask_34 = _out_romask_T_34; // @[RegisterRouter.scala:87:24] wire out_womask_34 = _out_womask_T_34; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_34 = out_rivalid_34 & out_rimask_34; // @[RegisterRouter.scala:87:24] wire _out_T_441 = out_f_rivalid_34; // @[RegisterRouter.scala:87:24] wire out_f_roready_34 = out_roready_34 & out_romask_34; // @[RegisterRouter.scala:87:24] wire _out_T_442 = out_f_roready_34; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_34 = out_wivalid_34 & out_wimask_34; // @[RegisterRouter.scala:87:24] wire out_f_woready_34 = out_woready_34 & out_womask_34; // @[RegisterRouter.scala:87:24] wire _out_T_440 = out_front_bits_data[1]; // @[RegisterRouter.scala:87:24] wire _out_T_443 = ~out_rimask_34; // @[RegisterRouter.scala:87:24] wire _out_T_444 = ~out_wimask_34; // @[RegisterRouter.scala:87:24] wire _out_T_445 = ~out_romask_34; // @[RegisterRouter.scala:87:24] wire _out_T_446 = ~out_womask_34; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_35 = out_frontMask[2]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_35 = out_frontMask[2]; // @[RegisterRouter.scala:87:24] wire out_rimask_35 = _out_rimask_T_35; // @[RegisterRouter.scala:87:24] wire out_wimask_35 = _out_wimask_T_35; // @[RegisterRouter.scala:87:24] wire _out_romask_T_35 = out_backMask[2]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_35 = out_backMask[2]; // @[RegisterRouter.scala:87:24] wire out_romask_35 = _out_romask_T_35; // @[RegisterRouter.scala:87:24] wire out_womask_35 = _out_womask_T_35; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_35 = out_rivalid_35 & out_rimask_35; // @[RegisterRouter.scala:87:24] wire _out_T_450 = out_f_rivalid_35; // @[RegisterRouter.scala:87:24] wire out_f_roready_35 = out_roready_35 & out_romask_35; // @[RegisterRouter.scala:87:24] wire _out_T_451 = out_f_roready_35; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_35 = out_wivalid_35 & out_wimask_35; // @[RegisterRouter.scala:87:24] wire out_f_woready_35 = out_woready_35 & out_womask_35; // @[RegisterRouter.scala:87:24] wire _out_T_449 = out_front_bits_data[2]; // @[RegisterRouter.scala:87:24] wire _out_T_452 = ~out_rimask_35; // @[RegisterRouter.scala:87:24] wire _out_T_453 = ~out_wimask_35; // @[RegisterRouter.scala:87:24] wire _out_T_454 = ~out_romask_35; // @[RegisterRouter.scala:87:24] wire _out_T_455 = ~out_womask_35; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_36 = out_frontMask[3]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_36 = out_frontMask[3]; // @[RegisterRouter.scala:87:24] wire out_rimask_36 = _out_rimask_T_36; // @[RegisterRouter.scala:87:24] wire out_wimask_36 = _out_wimask_T_36; // @[RegisterRouter.scala:87:24] wire _out_romask_T_36 = out_backMask[3]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_36 = out_backMask[3]; // @[RegisterRouter.scala:87:24] wire out_romask_36 = _out_romask_T_36; // @[RegisterRouter.scala:87:24] wire out_womask_36 = _out_womask_T_36; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_36 = out_rivalid_36 & out_rimask_36; // @[RegisterRouter.scala:87:24] wire _out_T_459 = out_f_rivalid_36; // @[RegisterRouter.scala:87:24] wire out_f_roready_36 = out_roready_36 & out_romask_36; // @[RegisterRouter.scala:87:24] wire _out_T_460 = out_f_roready_36; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_36 = out_wivalid_36 & out_wimask_36; // @[RegisterRouter.scala:87:24] wire out_f_woready_36 = out_woready_36 & out_womask_36; // @[RegisterRouter.scala:87:24] wire _out_T_458 = out_front_bits_data[3]; // @[RegisterRouter.scala:87:24] wire _out_T_461 = ~out_rimask_36; // @[RegisterRouter.scala:87:24] wire _out_T_462 = ~out_wimask_36; // @[RegisterRouter.scala:87:24] wire _out_T_463 = ~out_romask_36; // @[RegisterRouter.scala:87:24] wire _out_T_464 = ~out_womask_36; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_37 = out_frontMask[4]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_37 = out_frontMask[4]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_83 = out_frontMask[4]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_83 = out_frontMask[4]; // @[RegisterRouter.scala:87:24] wire out_rimask_37 = _out_rimask_T_37; // @[RegisterRouter.scala:87:24] wire out_wimask_37 = _out_wimask_T_37; // @[RegisterRouter.scala:87:24] wire _out_romask_T_37 = out_backMask[4]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_37 = out_backMask[4]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_83 = out_backMask[4]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_83 = out_backMask[4]; // @[RegisterRouter.scala:87:24] wire out_romask_37 = _out_romask_T_37; // @[RegisterRouter.scala:87:24] wire out_womask_37 = _out_womask_T_37; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_37 = out_rivalid_37 & out_rimask_37; // @[RegisterRouter.scala:87:24] wire _out_T_468 = out_f_rivalid_37; // @[RegisterRouter.scala:87:24] wire out_f_roready_37 = out_roready_37 & out_romask_37; // @[RegisterRouter.scala:87:24] wire _out_T_469 = out_f_roready_37; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_37 = out_wivalid_37 & out_wimask_37; // @[RegisterRouter.scala:87:24] wire out_f_woready_37 = out_woready_37 & out_womask_37; // @[RegisterRouter.scala:87:24] wire _out_T_467 = out_front_bits_data[4]; // @[RegisterRouter.scala:87:24] wire _out_T_957 = out_front_bits_data[4]; // @[RegisterRouter.scala:87:24] wire _out_T_470 = ~out_rimask_37; // @[RegisterRouter.scala:87:24] wire _out_T_471 = ~out_wimask_37; // @[RegisterRouter.scala:87:24] wire _out_T_472 = ~out_romask_37; // @[RegisterRouter.scala:87:24] wire _out_T_473 = ~out_womask_37; // @[RegisterRouter.scala:87:24] wire [6:0] _out_rimask_T_38 = out_frontMask[11:5]; // @[RegisterRouter.scala:87:24] wire [6:0] _out_wimask_T_38 = out_frontMask[11:5]; // @[RegisterRouter.scala:87:24] wire out_rimask_38 = \|_out_rimask_T_38; // @[RegisterRouter.scala:87:24] wire out_wimask_38 = &_out_wimask_T_38; // @[RegisterRouter.scala:87:24] wire [6:0] _out_romask_T_38 = out_backMask[11:5]; // @[RegisterRouter.scala:87:24] wire [6:0] _out_womask_T_38 = out_backMask[11:5]; // @[RegisterRouter.scala:87:24] wire out_romask_38 = \|_out_romask_T_38; // @[RegisterRouter.scala:87:24] wire out_womask_38 = &_out_womask_T_38; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_38 = out_rivalid_38 & out_rimask_38; // @[RegisterRouter.scala:87:24] wire _out_T_477 = out_f_rivalid_38; // @[RegisterRouter.scala:87:24] wire out_f_roready_38 = out_roready_38 & out_romask_38; // @[RegisterRouter.scala:87:24] wire _out_T_478 = out_f_roready_38; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_38 = out_wivalid_38 & out_wimask_38; // @[RegisterRouter.scala:87:24] wire out_f_woready_38 = out_woready_38 & out_womask_38; // @[RegisterRouter.scala:87:24] wire [6:0] _out_T_476 = out_front_bits_data[11:5]; // @[RegisterRouter.scala:87:24] wire _out_T_479 = ~out_rimask_38; // @[RegisterRouter.scala:87:24] wire _out_T_480 = ~out_wimask_38; // @[RegisterRouter.scala:87:24] wire _out_T_481 = ~out_romask_38; // @[RegisterRouter.scala:87:24] wire _out_T_482 = ~out_womask_38; // @[RegisterRouter.scala:87:24] wire [2:0] _out_rimask_T_39 = out_frontMask[14:12]; // @[RegisterRouter.scala:87:24] wire [2:0] _out_wimask_T_39 = out_frontMask[14:12]; // @[RegisterRouter.scala:87:24] wire out_rimask_39 = \|_out_rimask_T_39; // @[RegisterRouter.scala:87:24] wire out_wimask_39 = &_out_wimask_T_39; // @[RegisterRouter.scala:87:24] wire [2:0] _out_romask_T_39 = out_backMask[14:12]; // @[RegisterRouter.scala:87:24] wire [2:0] _out_womask_T_39 = out_backMask[14:12]; // @[RegisterRouter.scala:87:24] wire out_romask_39 = \|_out_romask_T_39; // @[RegisterRouter.scala:87:24] wire out_womask_39 = &_out_womask_T_39; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_39 = out_rivalid_39 & out_rimask_39; // @[RegisterRouter.scala:87:24] wire _out_T_486 = out_f_rivalid_39; // @[RegisterRouter.scala:87:24] wire out_f_roready_39 = out_roready_39 & out_romask_39; // @[RegisterRouter.scala:87:24] wire _out_T_487 = out_f_roready_39; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_39 = out_wivalid_39 & out_wimask_39; // @[RegisterRouter.scala:87:24] wire _out_T_488 = out_f_wivalid_39; // @[RegisterRouter.scala:87:24] assign out_f_woready_39 = out_woready_39 & out_womask_39; // @[RegisterRouter.scala:87:24] assign sberrorWrEn = out_f_woready_39; // @[RegisterRouter.scala:87:24] wire _out_T_489 = out_f_woready_39; // @[RegisterRouter.scala:87:24] assign _out_T_485 = out_front_bits_data[14:12]; // @[RegisterRouter.scala:87:24] assign SBCSWrData_sberror = _out_T_485; // @[RegisterRouter.scala:87:24] wire _out_T_490 = ~out_rimask_39; // @[RegisterRouter.scala:87:24] wire _out_T_491 = ~out_wimask_39; // @[RegisterRouter.scala:87:24] wire _out_T_492 = ~out_romask_39; // @[RegisterRouter.scala:87:24] wire _out_T_493 = ~out_womask_39; // @[RegisterRouter.scala:87:24] wire [14:0] out_prepend_29 = {SBCSRdData_sberror, 12'h40F}; // @[RegisterRouter.scala:87:24] wire [14:0] _out_T_494 = out_prepend_29; // @[RegisterRouter.scala:87:24] wire [14:0] _out_T_495 = _out_T_494; // @[RegisterRouter.scala:87:24] wire [14:0] _out_prepend_T_30 = _out_T_495; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_40 = out_frontMask[15]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_40 = out_frontMask[15]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_94 = out_frontMask[15]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_94 = out_frontMask[15]; // @[RegisterRouter.scala:87:24] wire out_rimask_40 = _out_rimask_T_40; // @[RegisterRouter.scala:87:24] wire out_wimask_40 = _out_wimask_T_40; // @[RegisterRouter.scala:87:24] wire _out_romask_T_40 = out_backMask[15]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_40 = out_backMask[15]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_94 = out_backMask[15]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_94 = out_backMask[15]; // @[RegisterRouter.scala:87:24] wire out_romask_40 = _out_romask_T_40; // @[RegisterRouter.scala:87:24] wire out_womask_40 = _out_womask_T_40; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_40 = out_rivalid_40 & out_rimask_40; // @[RegisterRouter.scala:87:24] wire _out_T_497 = out_f_rivalid_40; // @[RegisterRouter.scala:87:24] wire out_f_roready_40 = out_roready_40 & out_romask_40; // @[RegisterRouter.scala:87:24] wire _out_T_498 = out_f_roready_40; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_40 = out_wivalid_40 & out_wimask_40; // @[RegisterRouter.scala:87:24] wire _out_T_499 = out_f_wivalid_40; // @[RegisterRouter.scala:87:24] assign out_f_woready_40 = out_woready_40 & out_womask_40; // @[RegisterRouter.scala:87:24] assign sbreadondataWrEn = out_f_woready_40; // @[RegisterRouter.scala:87:24] wire _out_T_500 = out_f_woready_40; // @[RegisterRouter.scala:87:24] assign _out_T_496 = out_front_bits_data[15]; // @[RegisterRouter.scala:87:24] wire _out_T_1056 = out_front_bits_data[15]; // @[RegisterRouter.scala:87:24] assign SBCSWrData_sbreadondata = _out_T_496; // @[RegisterRouter.scala:87:24] wire _out_T_501 = ~out_rimask_40; // @[RegisterRouter.scala:87:24] wire _out_T_502 = ~out_wimask_40; // @[RegisterRouter.scala:87:24] wire _out_T_503 = ~out_romask_40; // @[RegisterRouter.scala:87:24] wire _out_T_504 = ~out_womask_40; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_30 = {SBCSRdData_sbreadondata, _out_prepend_T_30}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_505 = out_prepend_30; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_506 = _out_T_505; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_31 = _out_T_506; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_41 = out_frontMask[16]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_41 = out_frontMask[16]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_95 = out_frontMask[16]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_95 = out_frontMask[16]; // @[RegisterRouter.scala:87:24] wire out_rimask_41 = _out_rimask_T_41; // @[RegisterRouter.scala:87:24] wire out_wimask_41 = _out_wimask_T_41; // @[RegisterRouter.scala:87:24] wire _out_romask_T_41 = out_backMask[16]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_41 = out_backMask[16]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_95 = out_backMask[16]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_95 = out_backMask[16]; // @[RegisterRouter.scala:87:24] wire out_romask_41 = _out_romask_T_41; // @[RegisterRouter.scala:87:24] wire out_womask_41 = _out_womask_T_41; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_41 = out_rivalid_41 & out_rimask_41; // @[RegisterRouter.scala:87:24] wire _out_T_508 = out_f_rivalid_41; // @[RegisterRouter.scala:87:24] wire out_f_roready_41 = out_roready_41 & out_romask_41; // @[RegisterRouter.scala:87:24] wire _out_T_509 = out_f_roready_41; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_41 = out_wivalid_41 & out_wimask_41; // @[RegisterRouter.scala:87:24] wire _out_T_510 = out_f_wivalid_41; // @[RegisterRouter.scala:87:24] assign out_f_woready_41 = out_woready_41 & out_womask_41; // @[RegisterRouter.scala:87:24] assign sbautoincrementWrEn = out_f_woready_41; // @[RegisterRouter.scala:87:24] wire _out_T_511 = out_f_woready_41; // @[RegisterRouter.scala:87:24] assign _out_T_507 = out_front_bits_data[16]; // @[RegisterRouter.scala:87:24] wire _out_T_1065 = out_front_bits_data[16]; // @[RegisterRouter.scala:87:24] assign SBCSWrData_sbautoincrement = _out_T_507; // @[RegisterRouter.scala:87:24] wire _out_T_512 = ~out_rimask_41; // @[RegisterRouter.scala:87:24] wire _out_T_513 = ~out_wimask_41; // @[RegisterRouter.scala:87:24] wire _out_T_514 = ~out_romask_41; // @[RegisterRouter.scala:87:24] wire _out_T_515 = ~out_womask_41; // @[RegisterRouter.scala:87:24] wire [16:0] out_prepend_31 = {SBCSRdData_sbautoincrement, _out_prepend_T_31}; // @[RegisterRouter.scala:87:24] wire [16:0] _out_T_516 = out_prepend_31; // @[RegisterRouter.scala:87:24] wire [16:0] _out_T_517 = _out_T_516; // @[RegisterRouter.scala:87:24] wire [16:0] _out_prepend_T_32 = _out_T_517; // @[RegisterRouter.scala:87:24] wire [2:0] _out_rimask_T_42 = out_frontMask[19:17]; // @[RegisterRouter.scala:87:24] wire [2:0] _out_wimask_T_42 = out_frontMask[19:17]; // @[RegisterRouter.scala:87:24] wire out_rimask_42 = \|_out_rimask_T_42; // @[RegisterRouter.scala:87:24] wire out_wimask_42 = &_out_wimask_T_42; // @[RegisterRouter.scala:87:24] wire [2:0] _out_romask_T_42 = out_backMask[19:17]; // @[RegisterRouter.scala:87:24] wire [2:0] _out_womask_T_42 = out_backMask[19:17]; // @[RegisterRouter.scala:87:24] wire out_romask_42 = \|_out_romask_T_42; // @[RegisterRouter.scala:87:24] wire out_womask_42 = &_out_womask_T_42; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_42 = out_rivalid_42 & out_rimask_42; // @[RegisterRouter.scala:87:24] wire _out_T_519 = out_f_rivalid_42; // @[RegisterRouter.scala:87:24] wire out_f_roready_42 = out_roready_42 & out_romask_42; // @[RegisterRouter.scala:87:24] wire _out_T_520 = out_f_roready_42; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_42 = out_wivalid_42 & out_wimask_42; // @[RegisterRouter.scala:87:24] wire _out_T_521 = out_f_wivalid_42; // @[RegisterRouter.scala:87:24] assign out_f_woready_42 = out_woready_42 & out_womask_42; // @[RegisterRouter.scala:87:24] assign sbaccessWrEn = out_f_woready_42; // @[RegisterRouter.scala:87:24] wire _out_T_522 = out_f_woready_42; // @[RegisterRouter.scala:87:24] assign _out_T_518 = out_front_bits_data[19:17]; // @[RegisterRouter.scala:87:24] assign SBCSWrData_sbaccess = _out_T_518; // @[RegisterRouter.scala:87:24] wire _out_T_523 = ~out_rimask_42; // @[RegisterRouter.scala:87:24] wire _out_T_524 = ~out_wimask_42; // @[RegisterRouter.scala:87:24] wire _out_T_525 = ~out_romask_42; // @[RegisterRouter.scala:87:24] wire _out_T_526 = ~out_womask_42; // @[RegisterRouter.scala:87:24] wire [19:0] out_prepend_32 = {SBCSRdData_sbaccess, _out_prepend_T_32}; // @[RegisterRouter.scala:87:24] wire [19:0] _out_T_527 = out_prepend_32; // @[RegisterRouter.scala:87:24] wire [19:0] _out_T_528 = _out_T_527; // @[RegisterRouter.scala:87:24] wire [19:0] _out_prepend_T_33 = _out_T_528; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_43 = out_frontMask[20]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_43 = out_frontMask[20]; // @[RegisterRouter.scala:87:24] wire out_rimask_43 = _out_rimask_T_43; // @[RegisterRouter.scala:87:24] wire out_wimask_43 = _out_wimask_T_43; // @[RegisterRouter.scala:87:24] wire _out_romask_T_43 = out_backMask[20]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_43 = out_backMask[20]; // @[RegisterRouter.scala:87:24] wire out_romask_43 = _out_romask_T_43; // @[RegisterRouter.scala:87:24] wire out_womask_43 = _out_womask_T_43; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_43 = out_rivalid_43 & out_rimask_43; // @[RegisterRouter.scala:87:24] wire _out_T_530 = out_f_rivalid_43; // @[RegisterRouter.scala:87:24] wire out_f_roready_43 = out_roready_43 & out_romask_43; // @[RegisterRouter.scala:87:24] wire _out_T_531 = out_f_roready_43; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_43 = out_wivalid_43 & out_wimask_43; // @[RegisterRouter.scala:87:24] wire _out_T_532 = out_f_wivalid_43; // @[RegisterRouter.scala:87:24] assign out_f_woready_43 = out_woready_43 & out_womask_43; // @[RegisterRouter.scala:87:24] assign sbreadonaddrWrEn = out_f_woready_43; // @[RegisterRouter.scala:87:24] wire _out_T_533 = out_f_woready_43; // @[RegisterRouter.scala:87:24] assign _out_T_529 = out_front_bits_data[20]; // @[RegisterRouter.scala:87:24] assign SBCSWrData_sbreadonaddr = _out_T_529; // @[RegisterRouter.scala:87:24] wire _out_T_534 = ~out_rimask_43; // @[RegisterRouter.scala:87:24] wire _out_T_535 = ~out_wimask_43; // @[RegisterRouter.scala:87:24] wire _out_T_536 = ~out_romask_43; // @[RegisterRouter.scala:87:24] wire _out_T_537 = ~out_womask_43; // @[RegisterRouter.scala:87:24] wire [20:0] out_prepend_33 = {SBCSRdData_sbreadonaddr, _out_prepend_T_33}; // @[RegisterRouter.scala:87:24] wire [20:0] _out_T_538 = out_prepend_33; // @[RegisterRouter.scala:87:24] wire [20:0] _out_T_539 = _out_T_538; // @[RegisterRouter.scala:87:24] wire [20:0] _out_prepend_T_34 = _out_T_539; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_44 = out_frontMask[21]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_44 = out_frontMask[21]; // @[RegisterRouter.scala:87:24] wire out_rimask_44 = _out_rimask_T_44; // @[RegisterRouter.scala:87:24] wire out_wimask_44 = _out_wimask_T_44; // @[RegisterRouter.scala:87:24] wire _out_romask_T_44 = out_backMask[21]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_44 = out_backMask[21]; // @[RegisterRouter.scala:87:24] wire out_romask_44 = _out_romask_T_44; // @[RegisterRouter.scala:87:24] wire out_womask_44 = _out_womask_T_44; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_44 = out_rivalid_44 & out_rimask_44; // @[RegisterRouter.scala:87:24] wire _out_T_541 = out_f_rivalid_44; // @[RegisterRouter.scala:87:24] wire out_f_roready_44 = out_roready_44 & out_romask_44; // @[RegisterRouter.scala:87:24] wire _out_T_542 = out_f_roready_44; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_44 = out_wivalid_44 & out_wimask_44; // @[RegisterRouter.scala:87:24] wire out_f_woready_44 = out_woready_44 & out_womask_44; // @[RegisterRouter.scala:87:24] wire _out_T_540 = out_front_bits_data[21]; // @[RegisterRouter.scala:87:24] wire _out_T_543 = ~out_rimask_44; // @[RegisterRouter.scala:87:24] wire _out_T_544 = ~out_wimask_44; // @[RegisterRouter.scala:87:24] wire _out_T_545 = ~out_romask_44; // @[RegisterRouter.scala:87:24] wire _out_T_546 = ~out_womask_44; // @[RegisterRouter.scala:87:24] wire [21:0] out_prepend_34 = {SBCSRdData_sbbusy, _out_prepend_T_34}; // @[RegisterRouter.scala:87:24] wire [21:0] _out_T_547 = out_prepend_34; // @[RegisterRouter.scala:87:24] wire [21:0] _out_T_548 = _out_T_547; // @[RegisterRouter.scala:87:24] wire [21:0] _out_prepend_T_35 = _out_T_548; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_45 = out_frontMask[22]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_45 = out_frontMask[22]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_100 = out_frontMask[22]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_100 = out_frontMask[22]; // @[RegisterRouter.scala:87:24] wire out_rimask_45 = _out_rimask_T_45; // @[RegisterRouter.scala:87:24] wire out_wimask_45 = _out_wimask_T_45; // @[RegisterRouter.scala:87:24] wire _out_romask_T_45 = out_backMask[22]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_45 = out_backMask[22]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_100 = out_backMask[22]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_100 = out_backMask[22]; // @[RegisterRouter.scala:87:24] wire out_romask_45 = _out_romask_T_45; // @[RegisterRouter.scala:87:24] wire out_womask_45 = _out_womask_T_45; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_45 = out_rivalid_45 & out_rimask_45; // @[RegisterRouter.scala:87:24] wire _out_T_550 = out_f_rivalid_45; // @[RegisterRouter.scala:87:24] wire out_f_roready_45 = out_roready_45 & out_romask_45; // @[RegisterRouter.scala:87:24] wire _out_T_551 = out_f_roready_45; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_45 = out_wivalid_45 & out_wimask_45; // @[RegisterRouter.scala:87:24] wire _out_T_552 = out_f_wivalid_45; // @[RegisterRouter.scala:87:24] assign out_f_woready_45 = out_woready_45 & out_womask_45; // @[RegisterRouter.scala:87:24] assign sbbusyerrorWrEn = out_f_woready_45; // @[RegisterRouter.scala:87:24] wire _out_T_553 = out_f_woready_45; // @[RegisterRouter.scala:87:24] assign _out_T_549 = out_front_bits_data[22]; // @[RegisterRouter.scala:87:24] wire _out_T_1110 = out_front_bits_data[22]; // @[RegisterRouter.scala:87:24] assign SBCSWrData_sbbusyerror = _out_T_549; // @[RegisterRouter.scala:87:24] wire _out_T_554 = ~out_rimask_45; // @[RegisterRouter.scala:87:24] wire _out_T_555 = ~out_wimask_45; // @[RegisterRouter.scala:87:24] wire _out_T_556 = ~out_romask_45; // @[RegisterRouter.scala:87:24] wire _out_T_557 = ~out_womask_45; // @[RegisterRouter.scala:87:24] wire [22:0] out_prepend_35 = {SBCSRdData_sbbusyerror, _out_prepend_T_35}; // @[RegisterRouter.scala:87:24] wire [22:0] _out_T_558 = out_prepend_35; // @[RegisterRouter.scala:87:24] wire [22:0] _out_T_559 = _out_T_558; // @[RegisterRouter.scala:87:24] wire [22:0] _out_prepend_T_36 = _out_T_559; // @[RegisterRouter.scala:87:24] wire [5:0] _out_rimask_T_46 = out_frontMask[28:23]; // @[RegisterRouter.scala:87:24] wire [5:0] _out_wimask_T_46 = out_frontMask[28:23]; // @[RegisterRouter.scala:87:24] wire out_rimask_46 = \|_out_rimask_T_46; // @[RegisterRouter.scala:87:24] wire out_wimask_46 = &_out_wimask_T_46; // @[RegisterRouter.scala:87:24] wire [5:0] _out_romask_T_46 = out_backMask[28:23]; // @[RegisterRouter.scala:87:24] wire [5:0] _out_womask_T_46 = out_backMask[28:23]; // @[RegisterRouter.scala:87:24] wire out_romask_46 = \|_out_romask_T_46; // @[RegisterRouter.scala:87:24] wire out_womask_46 = &_out_womask_T_46; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_46 = out_rivalid_46 & out_rimask_46; // @[RegisterRouter.scala:87:24] wire _out_T_561 = out_f_rivalid_46; // @[RegisterRouter.scala:87:24] wire out_f_roready_46 = out_roready_46 & out_romask_46; // @[RegisterRouter.scala:87:24] wire _out_T_562 = out_f_roready_46; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_46 = out_wivalid_46 & out_wimask_46; // @[RegisterRouter.scala:87:24] wire out_f_woready_46 = out_woready_46 & out_womask_46; // @[RegisterRouter.scala:87:24] wire [5:0] _out_T_560 = out_front_bits_data[28:23]; // @[RegisterRouter.scala:87:24] wire _out_T_563 = ~out_rimask_46; // @[RegisterRouter.scala:87:24] wire _out_T_564 = ~out_wimask_46; // @[RegisterRouter.scala:87:24] wire _out_T_565 = ~out_romask_46; // @[RegisterRouter.scala:87:24] wire _out_T_566 = ~out_womask_46; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_36 = {1'h0, _out_prepend_T_36}; // @[RegisterRouter.scala:87:24] wire [28:0] _out_T_567 = {5'h0, out_prepend_36}; // @[RegisterRouter.scala:87:24] wire [28:0] _out_T_568 = _out_T_567; // @[RegisterRouter.scala:87:24] wire [28:0] _out_prepend_T_37 = _out_T_568; // @[RegisterRouter.scala:87:24] wire [2:0] _out_rimask_T_47 = out_frontMask[31:29]; // @[RegisterRouter.scala:87:24] wire [2:0] _out_wimask_T_47 = out_frontMask[31:29]; // @[RegisterRouter.scala:87:24] wire out_rimask_47 = \|_out_rimask_T_47; // @[RegisterRouter.scala:87:24] wire out_wimask_47 = &_out_wimask_T_47; // @[RegisterRouter.scala:87:24] wire [2:0] _out_romask_T_47 = out_backMask[31:29]; // @[RegisterRouter.scala:87:24] wire [2:0] _out_womask_T_47 = out_backMask[31:29]; // @[RegisterRouter.scala:87:24] wire out_romask_47 = \|_out_romask_T_47; // @[RegisterRouter.scala:87:24] wire out_womask_47 = &_out_womask_T_47; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_47 = out_rivalid_47 & out_rimask_47; // @[RegisterRouter.scala:87:24] wire _out_T_570 = out_f_rivalid_47; // @[RegisterRouter.scala:87:24] wire out_f_roready_47 = out_roready_47 & out_romask_47; // @[RegisterRouter.scala:87:24] wire _out_T_571 = out_f_roready_47; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_47 = out_wivalid_47 & out_wimask_47; // @[RegisterRouter.scala:87:24] wire out_f_woready_47 = out_woready_47 & out_womask_47; // @[RegisterRouter.scala:87:24] wire [2:0] _out_T_569 = out_front_bits_data[31:29]; // @[RegisterRouter.scala:87:24] wire _out_T_572 = ~out_rimask_47; // @[RegisterRouter.scala:87:24] wire _out_T_573 = ~out_wimask_47; // @[RegisterRouter.scala:87:24] wire _out_T_574 = ~out_romask_47; // @[RegisterRouter.scala:87:24] wire _out_T_575 = ~out_womask_47; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_37 = {3'h1, _out_prepend_T_37}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_576 = out_prepend_37; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_577 = _out_T_576; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_56 = _out_T_577; // @[MuxLiteral.scala:49:48] wire out_rimask_48 = \|_out_rimask_T_48; // @[RegisterRouter.scala:87:24] wire out_wimask_48 = &_out_wimask_T_48; // @[RegisterRouter.scala:87:24] wire out_romask_48 = \|_out_romask_T_48; // @[RegisterRouter.scala:87:24] wire out_womask_48 = &_out_womask_T_48; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_48 = out_rivalid_48 & out_rimask_48; // @[RegisterRouter.scala:87:24] wire _out_T_579 = out_f_rivalid_48; // @[RegisterRouter.scala:87:24] assign out_f_roready_48 = out_roready_48 & out_romask_48; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_40 = out_f_roready_48; // @[RegisterRouter.scala:87:24] wire _out_T_580 = out_f_roready_48; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_48 = out_wivalid_48 & out_wimask_48; // @[RegisterRouter.scala:87:24] wire _out_T_581 = out_f_wivalid_48; // @[RegisterRouter.scala:87:24] assign out_f_woready_48 = out_woready_48 & out_womask_48; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_40 = out_f_woready_48; // @[RegisterRouter.scala:87:24] wire _out_T_582 = out_f_woready_48; // @[RegisterRouter.scala:87:24] assign programBufferNxt_40 = out_f_woready_48 ? _out_T_578 : programBufferMem_40; // @[RegisterRouter.scala:87:24] wire _out_T_583 = ~out_rimask_48; // @[RegisterRouter.scala:87:24] wire _out_T_584 = ~out_wimask_48; // @[RegisterRouter.scala:87:24] wire _out_T_585 = ~out_romask_48; // @[RegisterRouter.scala:87:24] wire _out_T_586 = ~out_womask_48; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_588 = _out_T_587; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_38 = _out_T_588; // @[RegisterRouter.scala:87:24] wire out_rimask_49 = \|_out_rimask_T_49; // @[RegisterRouter.scala:87:24] wire out_wimask_49 = &_out_wimask_T_49; // @[RegisterRouter.scala:87:24] wire out_romask_49 = \|_out_romask_T_49; // @[RegisterRouter.scala:87:24] wire out_womask_49 = &_out_womask_T_49; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_49 = out_rivalid_49 & out_rimask_49; // @[RegisterRouter.scala:87:24] wire _out_T_590 = out_f_rivalid_49; // @[RegisterRouter.scala:87:24] assign out_f_roready_49 = out_roready_49 & out_romask_49; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_41 = out_f_roready_49; // @[RegisterRouter.scala:87:24] wire _out_T_591 = out_f_roready_49; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_49 = out_wivalid_49 & out_wimask_49; // @[RegisterRouter.scala:87:24] wire _out_T_592 = out_f_wivalid_49; // @[RegisterRouter.scala:87:24] assign out_f_woready_49 = out_woready_49 & out_womask_49; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_41 = out_f_woready_49; // @[RegisterRouter.scala:87:24] wire _out_T_593 = out_f_woready_49; // @[RegisterRouter.scala:87:24] assign programBufferNxt_41 = out_f_woready_49 ? _out_T_589 : programBufferMem_41; // @[RegisterRouter.scala:87:24] wire _out_T_594 = ~out_rimask_49; // @[RegisterRouter.scala:87:24] wire _out_T_595 = ~out_wimask_49; // @[RegisterRouter.scala:87:24] wire _out_T_596 = ~out_romask_49; // @[RegisterRouter.scala:87:24] wire _out_T_597 = ~out_womask_49; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_38 = {programBufferMem_41, _out_prepend_T_38}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_598 = out_prepend_38; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_599 = _out_T_598; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_39 = _out_T_599; // @[RegisterRouter.scala:87:24] wire out_rimask_50 = \|_out_rimask_T_50; // @[RegisterRouter.scala:87:24] wire out_wimask_50 = &_out_wimask_T_50; // @[RegisterRouter.scala:87:24] wire out_romask_50 = \|_out_romask_T_50; // @[RegisterRouter.scala:87:24] wire out_womask_50 = &_out_womask_T_50; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_50 = out_rivalid_50 & out_rimask_50; // @[RegisterRouter.scala:87:24] wire _out_T_601 = out_f_rivalid_50; // @[RegisterRouter.scala:87:24] assign out_f_roready_50 = out_roready_50 & out_romask_50; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_42 = out_f_roready_50; // @[RegisterRouter.scala:87:24] wire _out_T_602 = out_f_roready_50; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_50 = out_wivalid_50 & out_wimask_50; // @[RegisterRouter.scala:87:24] wire _out_T_603 = out_f_wivalid_50; // @[RegisterRouter.scala:87:24] assign out_f_woready_50 = out_woready_50 & out_womask_50; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_42 = out_f_woready_50; // @[RegisterRouter.scala:87:24] wire _out_T_604 = out_f_woready_50; // @[RegisterRouter.scala:87:24] assign programBufferNxt_42 = out_f_woready_50 ? _out_T_600 : programBufferMem_42; // @[RegisterRouter.scala:87:24] wire _out_T_605 = ~out_rimask_50; // @[RegisterRouter.scala:87:24] wire _out_T_606 = ~out_wimask_50; // @[RegisterRouter.scala:87:24] wire _out_T_607 = ~out_romask_50; // @[RegisterRouter.scala:87:24] wire _out_T_608 = ~out_womask_50; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_39 = {programBufferMem_42, _out_prepend_T_39}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_609 = out_prepend_39; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_610 = _out_T_609; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_40 = _out_T_610; // @[RegisterRouter.scala:87:24] wire out_rimask_51 = \|_out_rimask_T_51; // @[RegisterRouter.scala:87:24] wire out_wimask_51 = &_out_wimask_T_51; // @[RegisterRouter.scala:87:24] wire out_romask_51 = \|_out_romask_T_51; // @[RegisterRouter.scala:87:24] wire out_womask_51 = &_out_womask_T_51; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_51 = out_rivalid_51 & out_rimask_51; // @[RegisterRouter.scala:87:24] wire _out_T_612 = out_f_rivalid_51; // @[RegisterRouter.scala:87:24] assign out_f_roready_51 = out_roready_51 & out_romask_51; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_43 = out_f_roready_51; // @[RegisterRouter.scala:87:24] wire _out_T_613 = out_f_roready_51; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_51 = out_wivalid_51 & out_wimask_51; // @[RegisterRouter.scala:87:24] wire _out_T_614 = out_f_wivalid_51; // @[RegisterRouter.scala:87:24] assign out_f_woready_51 = out_woready_51 & out_womask_51; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_43 = out_f_woready_51; // @[RegisterRouter.scala:87:24] wire _out_T_615 = out_f_woready_51; // @[RegisterRouter.scala:87:24] assign programBufferNxt_43 = out_f_woready_51 ? _out_T_611 : programBufferMem_43; // @[RegisterRouter.scala:87:24] wire _out_T_616 = ~out_rimask_51; // @[RegisterRouter.scala:87:24] wire _out_T_617 = ~out_wimask_51; // @[RegisterRouter.scala:87:24] wire _out_T_618 = ~out_romask_51; // @[RegisterRouter.scala:87:24] wire _out_T_619 = ~out_womask_51; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_40 = {programBufferMem_43, _out_prepend_T_40}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_620 = out_prepend_40; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_621 = _out_T_620; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_42 = _out_T_621; // @[MuxLiteral.scala:49:48] wire out_rimask_52 = \|_out_rimask_T_52; // @[RegisterRouter.scala:87:24] wire out_wimask_52 = &_out_wimask_T_52; // @[RegisterRouter.scala:87:24] wire out_romask_52 = \|_out_romask_T_52; // @[RegisterRouter.scala:87:24] wire out_womask_52 = &_out_womask_T_52; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_52 = out_rivalid_52 & out_rimask_52; // @[RegisterRouter.scala:87:24] wire _out_T_623 = out_f_rivalid_52; // @[RegisterRouter.scala:87:24] wire out_f_roready_52 = out_roready_52 & out_romask_52; // @[RegisterRouter.scala:87:24] wire _out_T_624 = out_f_roready_52; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_52 = out_wivalid_52 & out_wimask_52; // @[RegisterRouter.scala:87:24] wire _out_T_625 = out_f_wivalid_52; // @[RegisterRouter.scala:87:24] assign out_f_woready_52 = out_woready_52 & out_womask_52; // @[RegisterRouter.scala:87:24] assign autoexecdataWrEnMaybe = out_f_woready_52; // @[RegisterRouter.scala:87:24] wire _out_T_626 = out_f_woready_52; // @[RegisterRouter.scala:87:24] assign ABSTRACTAUTOWrData_autoexecdata = {4'h0, _out_T_622}; // @[RegisterRouter.scala:87:24] wire _out_T_627 = ~out_rimask_52; // @[RegisterRouter.scala:87:24] wire _out_T_628 = ~out_wimask_52; // @[RegisterRouter.scala:87:24] wire _out_T_629 = ~out_romask_52; // @[RegisterRouter.scala:87:24] wire _out_T_630 = ~out_womask_52; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_632 = _out_T_631[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_41 = _out_T_632; // @[RegisterRouter.scala:87:24] wire out_rimask_53 = \|_out_rimask_T_53; // @[RegisterRouter.scala:87:24] wire out_wimask_53 = &_out_wimask_T_53; // @[RegisterRouter.scala:87:24] wire out_romask_53 = \|_out_romask_T_53; // @[RegisterRouter.scala:87:24] wire out_womask_53 = &_out_womask_T_53; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_53 = out_rivalid_53 & out_rimask_53; // @[RegisterRouter.scala:87:24] wire _out_T_634 = out_f_rivalid_53; // @[RegisterRouter.scala:87:24] wire out_f_roready_53 = out_roready_53 & out_romask_53; // @[RegisterRouter.scala:87:24] wire _out_T_635 = out_f_roready_53; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_53 = out_wivalid_53 & out_wimask_53; // @[RegisterRouter.scala:87:24] wire out_f_woready_53 = out_woready_53 & out_womask_53; // @[RegisterRouter.scala:87:24] wire _out_T_636 = ~out_rimask_53; // @[RegisterRouter.scala:87:24] wire _out_T_637 = ~out_wimask_53; // @[RegisterRouter.scala:87:24] wire _out_T_638 = ~out_romask_53; // @[RegisterRouter.scala:87:24] wire _out_T_639 = ~out_womask_53; // @[RegisterRouter.scala:87:24] wire [8:0] out_prepend_41 = {1'h0, _out_prepend_T_41}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_640 = {7'h0, out_prepend_41}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_641 = _out_T_640; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_42 = _out_T_641; // @[RegisterRouter.scala:87:24] wire [15:0] _out_rimask_T_54 = out_frontMask[31:16]; // @[RegisterRouter.scala:87:24] wire [15:0] _out_wimask_T_54 = out_frontMask[31:16]; // @[RegisterRouter.scala:87:24] wire out_rimask_54 = \|_out_rimask_T_54; // @[RegisterRouter.scala:87:24] wire out_wimask_54 = &_out_wimask_T_54; // @[RegisterRouter.scala:87:24] wire [15:0] _out_romask_T_54 = out_backMask[31:16]; // @[RegisterRouter.scala:87:24] wire [15:0] _out_womask_T_54 = out_backMask[31:16]; // @[RegisterRouter.scala:87:24] wire out_romask_54 = \|_out_romask_T_54; // @[RegisterRouter.scala:87:24] wire out_womask_54 = &_out_womask_T_54; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_54 = out_rivalid_54 & out_rimask_54; // @[RegisterRouter.scala:87:24] wire _out_T_643 = out_f_rivalid_54; // @[RegisterRouter.scala:87:24] wire out_f_roready_54 = out_roready_54 & out_romask_54; // @[RegisterRouter.scala:87:24] wire _out_T_644 = out_f_roready_54; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_54 = out_wivalid_54 & out_wimask_54; // @[RegisterRouter.scala:87:24] wire _out_T_645 = out_f_wivalid_54; // @[RegisterRouter.scala:87:24] assign out_f_woready_54 = out_woready_54 & out_womask_54; // @[RegisterRouter.scala:87:24] assign autoexecprogbufWrEnMaybe = out_f_woready_54; // @[RegisterRouter.scala:87:24] wire _out_T_646 = out_f_woready_54; // @[RegisterRouter.scala:87:24] assign _out_T_642 = out_front_bits_data[31:16]; // @[RegisterRouter.scala:87:24] assign ABSTRACTAUTOWrData_autoexecprogbuf = _out_T_642; // @[RegisterRouter.scala:87:24] wire _out_T_647 = ~out_rimask_54; // @[RegisterRouter.scala:87:24] wire _out_T_648 = ~out_wimask_54; // @[RegisterRouter.scala:87:24] wire _out_T_649 = ~out_romask_54; // @[RegisterRouter.scala:87:24] wire _out_T_650 = ~out_womask_54; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_42 = {ABSTRACTAUTORdData_autoexecprogbuf, _out_prepend_T_42}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_651 = out_prepend_42; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_652 = _out_T_651; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_24 = _out_T_652; // @[MuxLiteral.scala:49:48] wire out_rimask_55 = \|_out_rimask_T_55; // @[RegisterRouter.scala:87:24] wire out_wimask_55 = &_out_wimask_T_55; // @[RegisterRouter.scala:87:24] wire out_romask_55 = \|_out_romask_T_55; // @[RegisterRouter.scala:87:24] wire out_womask_55 = &_out_womask_T_55; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_55 = out_rivalid_55 & out_rimask_55; // @[RegisterRouter.scala:87:24] wire _out_T_654 = out_f_rivalid_55; // @[RegisterRouter.scala:87:24] assign out_f_roready_55 = out_roready_55 & out_romask_55; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_20 = out_f_roready_55; // @[RegisterRouter.scala:87:24] wire _out_T_655 = out_f_roready_55; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_55 = out_wivalid_55 & out_wimask_55; // @[RegisterRouter.scala:87:24] wire _out_T_656 = out_f_wivalid_55; // @[RegisterRouter.scala:87:24] assign out_f_woready_55 = out_woready_55 & out_womask_55; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_20 = out_f_woready_55; // @[RegisterRouter.scala:87:24] wire _out_T_657 = out_f_woready_55; // @[RegisterRouter.scala:87:24] assign programBufferNxt_20 = out_f_woready_55 ? _out_T_653 : programBufferMem_20; // @[RegisterRouter.scala:87:24] wire _out_T_658 = ~out_rimask_55; // @[RegisterRouter.scala:87:24] wire _out_T_659 = ~out_wimask_55; // @[RegisterRouter.scala:87:24] wire _out_T_660 = ~out_romask_55; // @[RegisterRouter.scala:87:24] wire _out_T_661 = ~out_womask_55; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_663 = _out_T_662; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_43 = _out_T_663; // @[RegisterRouter.scala:87:24] wire out_rimask_56 = \|_out_rimask_T_56; // @[RegisterRouter.scala:87:24] wire out_wimask_56 = &_out_wimask_T_56; // @[RegisterRouter.scala:87:24] wire out_romask_56 = \|_out_romask_T_56; // @[RegisterRouter.scala:87:24] wire out_womask_56 = &_out_womask_T_56; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_56 = out_rivalid_56 & out_rimask_56; // @[RegisterRouter.scala:87:24] wire _out_T_665 = out_f_rivalid_56; // @[RegisterRouter.scala:87:24] assign out_f_roready_56 = out_roready_56 & out_romask_56; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_21 = out_f_roready_56; // @[RegisterRouter.scala:87:24] wire _out_T_666 = out_f_roready_56; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_56 = out_wivalid_56 & out_wimask_56; // @[RegisterRouter.scala:87:24] wire _out_T_667 = out_f_wivalid_56; // @[RegisterRouter.scala:87:24] assign out_f_woready_56 = out_woready_56 & out_womask_56; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_21 = out_f_woready_56; // @[RegisterRouter.scala:87:24] wire _out_T_668 = out_f_woready_56; // @[RegisterRouter.scala:87:24] assign programBufferNxt_21 = out_f_woready_56 ? _out_T_664 : programBufferMem_21; // @[RegisterRouter.scala:87:24] wire _out_T_669 = ~out_rimask_56; // @[RegisterRouter.scala:87:24] wire _out_T_670 = ~out_wimask_56; // @[RegisterRouter.scala:87:24] wire _out_T_671 = ~out_romask_56; // @[RegisterRouter.scala:87:24] wire _out_T_672 = ~out_womask_56; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_43 = {programBufferMem_21, _out_prepend_T_43}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_673 = out_prepend_43; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_674 = _out_T_673; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_44 = _out_T_674; // @[RegisterRouter.scala:87:24] wire out_rimask_57 = \|_out_rimask_T_57; // @[RegisterRouter.scala:87:24] wire out_wimask_57 = &_out_wimask_T_57; // @[RegisterRouter.scala:87:24] wire out_romask_57 = \|_out_romask_T_57; // @[RegisterRouter.scala:87:24] wire out_womask_57 = &_out_womask_T_57; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_57 = out_rivalid_57 & out_rimask_57; // @[RegisterRouter.scala:87:24] wire _out_T_676 = out_f_rivalid_57; // @[RegisterRouter.scala:87:24] assign out_f_roready_57 = out_roready_57 & out_romask_57; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_22 = out_f_roready_57; // @[RegisterRouter.scala:87:24] wire _out_T_677 = out_f_roready_57; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_57 = out_wivalid_57 & out_wimask_57; // @[RegisterRouter.scala:87:24] wire _out_T_678 = out_f_wivalid_57; // @[RegisterRouter.scala:87:24] assign out_f_woready_57 = out_woready_57 & out_womask_57; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_22 = out_f_woready_57; // @[RegisterRouter.scala:87:24] wire _out_T_679 = out_f_woready_57; // @[RegisterRouter.scala:87:24] assign programBufferNxt_22 = out_f_woready_57 ? _out_T_675 : programBufferMem_22; // @[RegisterRouter.scala:87:24] wire _out_T_680 = ~out_rimask_57; // @[RegisterRouter.scala:87:24] wire _out_T_681 = ~out_wimask_57; // @[RegisterRouter.scala:87:24] wire _out_T_682 = ~out_romask_57; // @[RegisterRouter.scala:87:24] wire _out_T_683 = ~out_womask_57; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_44 = {programBufferMem_22, _out_prepend_T_44}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_684 = out_prepend_44; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_685 = _out_T_684; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_45 = _out_T_685; // @[RegisterRouter.scala:87:24] wire out_rimask_58 = \|_out_rimask_T_58; // @[RegisterRouter.scala:87:24] wire out_wimask_58 = &_out_wimask_T_58; // @[RegisterRouter.scala:87:24] wire out_romask_58 = \|_out_romask_T_58; // @[RegisterRouter.scala:87:24] wire out_womask_58 = &_out_womask_T_58; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_58 = out_rivalid_58 & out_rimask_58; // @[RegisterRouter.scala:87:24] wire _out_T_687 = out_f_rivalid_58; // @[RegisterRouter.scala:87:24] assign out_f_roready_58 = out_roready_58 & out_romask_58; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_23 = out_f_roready_58; // @[RegisterRouter.scala:87:24] wire _out_T_688 = out_f_roready_58; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_58 = out_wivalid_58 & out_wimask_58; // @[RegisterRouter.scala:87:24] wire _out_T_689 = out_f_wivalid_58; // @[RegisterRouter.scala:87:24] assign out_f_woready_58 = out_woready_58 & out_womask_58; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_23 = out_f_woready_58; // @[RegisterRouter.scala:87:24] wire _out_T_690 = out_f_woready_58; // @[RegisterRouter.scala:87:24] assign programBufferNxt_23 = out_f_woready_58 ? _out_T_686 : programBufferMem_23; // @[RegisterRouter.scala:87:24] wire _out_T_691 = ~out_rimask_58; // @[RegisterRouter.scala:87:24] wire _out_T_692 = ~out_wimask_58; // @[RegisterRouter.scala:87:24] wire _out_T_693 = ~out_romask_58; // @[RegisterRouter.scala:87:24] wire _out_T_694 = ~out_womask_58; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_45 = {programBufferMem_23, _out_prepend_T_45}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_695 = out_prepend_45; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_696 = _out_T_695; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_37 = _out_T_696; // @[MuxLiteral.scala:49:48] wire out_rimask_59 = \|_out_rimask_T_59; // @[RegisterRouter.scala:87:24] wire out_wimask_59 = &_out_wimask_T_59; // @[RegisterRouter.scala:87:24] wire out_romask_59 = \|_out_romask_T_59; // @[RegisterRouter.scala:87:24] wire out_womask_59 = &_out_womask_T_59; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_59 = out_rivalid_59 & out_rimask_59; // @[RegisterRouter.scala:87:24] wire _out_T_698 = out_f_rivalid_59; // @[RegisterRouter.scala:87:24] assign out_f_roready_59 = out_roready_59 & out_romask_59; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_56 = out_f_roready_59; // @[RegisterRouter.scala:87:24] wire _out_T_699 = out_f_roready_59; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_59 = out_wivalid_59 & out_wimask_59; // @[RegisterRouter.scala:87:24] wire _out_T_700 = out_f_wivalid_59; // @[RegisterRouter.scala:87:24] assign out_f_woready_59 = out_woready_59 & out_womask_59; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_56 = out_f_woready_59; // @[RegisterRouter.scala:87:24] wire _out_T_701 = out_f_woready_59; // @[RegisterRouter.scala:87:24] assign programBufferNxt_56 = out_f_woready_59 ? _out_T_697 : programBufferMem_56; // @[RegisterRouter.scala:87:24] wire _out_T_702 = ~out_rimask_59; // @[RegisterRouter.scala:87:24] wire _out_T_703 = ~out_wimask_59; // @[RegisterRouter.scala:87:24] wire _out_T_704 = ~out_romask_59; // @[RegisterRouter.scala:87:24] wire _out_T_705 = ~out_womask_59; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_707 = _out_T_706; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_46 = _out_T_707; // @[RegisterRouter.scala:87:24] wire out_rimask_60 = \|_out_rimask_T_60; // @[RegisterRouter.scala:87:24] wire out_wimask_60 = &_out_wimask_T_60; // @[RegisterRouter.scala:87:24] wire out_romask_60 = \|_out_romask_T_60; // @[RegisterRouter.scala:87:24] wire out_womask_60 = &_out_womask_T_60; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_60 = out_rivalid_60 & out_rimask_60; // @[RegisterRouter.scala:87:24] wire _out_T_709 = out_f_rivalid_60; // @[RegisterRouter.scala:87:24] assign out_f_roready_60 = out_roready_60 & out_romask_60; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_57 = out_f_roready_60; // @[RegisterRouter.scala:87:24] wire _out_T_710 = out_f_roready_60; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_60 = out_wivalid_60 & out_wimask_60; // @[RegisterRouter.scala:87:24] wire _out_T_711 = out_f_wivalid_60; // @[RegisterRouter.scala:87:24] assign out_f_woready_60 = out_woready_60 & out_womask_60; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_57 = out_f_woready_60; // @[RegisterRouter.scala:87:24] wire _out_T_712 = out_f_woready_60; // @[RegisterRouter.scala:87:24] assign programBufferNxt_57 = out_f_woready_60 ? _out_T_708 : programBufferMem_57; // @[RegisterRouter.scala:87:24] wire _out_T_713 = ~out_rimask_60; // @[RegisterRouter.scala:87:24] wire _out_T_714 = ~out_wimask_60; // @[RegisterRouter.scala:87:24] wire _out_T_715 = ~out_romask_60; // @[RegisterRouter.scala:87:24] wire _out_T_716 = ~out_womask_60; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_46 = {programBufferMem_57, _out_prepend_T_46}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_717 = out_prepend_46; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_718 = _out_T_717; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_47 = _out_T_718; // @[RegisterRouter.scala:87:24] wire out_rimask_61 = \|_out_rimask_T_61; // @[RegisterRouter.scala:87:24] wire out_wimask_61 = &_out_wimask_T_61; // @[RegisterRouter.scala:87:24] wire out_romask_61 = \|_out_romask_T_61; // @[RegisterRouter.scala:87:24] wire out_womask_61 = &_out_womask_T_61; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_61 = out_rivalid_61 & out_rimask_61; // @[RegisterRouter.scala:87:24] wire _out_T_720 = out_f_rivalid_61; // @[RegisterRouter.scala:87:24] assign out_f_roready_61 = out_roready_61 & out_romask_61; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_58 = out_f_roready_61; // @[RegisterRouter.scala:87:24] wire _out_T_721 = out_f_roready_61; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_61 = out_wivalid_61 & out_wimask_61; // @[RegisterRouter.scala:87:24] wire _out_T_722 = out_f_wivalid_61; // @[RegisterRouter.scala:87:24] assign out_f_woready_61 = out_woready_61 & out_womask_61; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_58 = out_f_woready_61; // @[RegisterRouter.scala:87:24] wire _out_T_723 = out_f_woready_61; // @[RegisterRouter.scala:87:24] assign programBufferNxt_58 = out_f_woready_61 ? _out_T_719 : programBufferMem_58; // @[RegisterRouter.scala:87:24] wire _out_T_724 = ~out_rimask_61; // @[RegisterRouter.scala:87:24] wire _out_T_725 = ~out_wimask_61; // @[RegisterRouter.scala:87:24] wire _out_T_726 = ~out_romask_61; // @[RegisterRouter.scala:87:24] wire _out_T_727 = ~out_womask_61; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_47 = {programBufferMem_58, _out_prepend_T_47}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_728 = out_prepend_47; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_729 = _out_T_728; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_48 = _out_T_729; // @[RegisterRouter.scala:87:24] wire out_rimask_62 = \|_out_rimask_T_62; // @[RegisterRouter.scala:87:24] wire out_wimask_62 = &_out_wimask_T_62; // @[RegisterRouter.scala:87:24] wire out_romask_62 = \|_out_romask_T_62; // @[RegisterRouter.scala:87:24] wire out_womask_62 = &_out_womask_T_62; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_62 = out_rivalid_62 & out_rimask_62; // @[RegisterRouter.scala:87:24] wire _out_T_731 = out_f_rivalid_62; // @[RegisterRouter.scala:87:24] assign out_f_roready_62 = out_roready_62 & out_romask_62; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_59 = out_f_roready_62; // @[RegisterRouter.scala:87:24] wire _out_T_732 = out_f_roready_62; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_62 = out_wivalid_62 & out_wimask_62; // @[RegisterRouter.scala:87:24] wire _out_T_733 = out_f_wivalid_62; // @[RegisterRouter.scala:87:24] assign out_f_woready_62 = out_woready_62 & out_womask_62; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_59 = out_f_woready_62; // @[RegisterRouter.scala:87:24] wire _out_T_734 = out_f_woready_62; // @[RegisterRouter.scala:87:24] assign programBufferNxt_59 = out_f_woready_62 ? _out_T_730 : programBufferMem_59; // @[RegisterRouter.scala:87:24] wire _out_T_735 = ~out_rimask_62; // @[RegisterRouter.scala:87:24] wire _out_T_736 = ~out_wimask_62; // @[RegisterRouter.scala:87:24] wire _out_T_737 = ~out_romask_62; // @[RegisterRouter.scala:87:24] wire _out_T_738 = ~out_womask_62; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_48 = {programBufferMem_59, _out_prepend_T_48}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_739 = out_prepend_48; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_740 = _out_T_739; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_46 = _out_T_740; // @[MuxLiteral.scala:49:48] wire out_rimask_63 = \|_out_rimask_T_63; // @[RegisterRouter.scala:87:24] wire out_wimask_63 = &_out_wimask_T_63; // @[RegisterRouter.scala:87:24] wire out_romask_63 = \|_out_romask_T_63; // @[RegisterRouter.scala:87:24] wire out_womask_63 = &_out_womask_T_63; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_63 = out_rivalid_63 & out_rimask_63; // @[RegisterRouter.scala:87:24] wire _out_T_742 = out_f_rivalid_63; // @[RegisterRouter.scala:87:24] assign out_f_roready_63 = out_roready_63 & out_romask_63; // @[RegisterRouter.scala:87:24] assign SBADDRESSRdEn_0 = out_f_roready_63; // @[RegisterRouter.scala:87:24] wire _out_T_743 = out_f_roready_63; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_63 = out_wivalid_63 & out_wimask_63; // @[RegisterRouter.scala:87:24] wire _out_T_744 = out_f_wivalid_63; // @[RegisterRouter.scala:87:24] assign out_f_woready_63 = out_woready_63 & out_womask_63; // @[RegisterRouter.scala:87:24] assign SBADDRESSWrEn_0 = out_f_woready_63; // @[RegisterRouter.scala:87:24] wire _out_T_745 = out_f_woready_63; // @[RegisterRouter.scala:87:24] assign SBADDRESSWrData_0 = out_f_woready_63 ? _out_T_741 : 32'h0; // @[RegisterRouter.scala:87:24] wire _out_T_746 = ~out_rimask_63; // @[RegisterRouter.scala:87:24] wire _out_T_747 = ~out_wimask_63; // @[RegisterRouter.scala:87:24] wire _out_T_748 = ~out_romask_63; // @[RegisterRouter.scala:87:24] wire _out_T_749 = ~out_womask_63; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_751 = _out_T_750; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_57 = _out_T_751; // @[MuxLiteral.scala:49:48] wire out_rimask_64 = \|_out_rimask_T_64; // @[RegisterRouter.scala:87:24] wire out_wimask_64 = &_out_wimask_T_64; // @[RegisterRouter.scala:87:24] wire out_romask_64 = \|_out_romask_T_64; // @[RegisterRouter.scala:87:24] wire out_womask_64 = &_out_womask_T_64; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_64 = out_rivalid_64 & out_rimask_64; // @[RegisterRouter.scala:87:24] wire _out_T_753 = out_f_rivalid_64; // @[RegisterRouter.scala:87:24] assign out_f_roready_64 = out_roready_64 & out_romask_64; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_8 = out_f_roready_64; // @[RegisterRouter.scala:87:24] wire _out_T_754 = out_f_roready_64; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_64 = out_wivalid_64 & out_wimask_64; // @[RegisterRouter.scala:87:24] wire _out_T_755 = out_f_wivalid_64; // @[RegisterRouter.scala:87:24] assign out_f_woready_64 = out_woready_64 & out_womask_64; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_8 = out_f_woready_64; // @[RegisterRouter.scala:87:24] wire _out_T_756 = out_f_woready_64; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_8 = out_f_woready_64 ? _out_T_752 : abstractDataMem_8; // @[RegisterRouter.scala:87:24] wire _out_T_757 = ~out_rimask_64; // @[RegisterRouter.scala:87:24] wire _out_T_758 = ~out_wimask_64; // @[RegisterRouter.scala:87:24] wire _out_T_759 = ~out_romask_64; // @[RegisterRouter.scala:87:24] wire _out_T_760 = ~out_womask_64; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_762 = _out_T_761; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_49 = _out_T_762; // @[RegisterRouter.scala:87:24] wire out_rimask_65 = \|_out_rimask_T_65; // @[RegisterRouter.scala:87:24] wire out_wimask_65 = &_out_wimask_T_65; // @[RegisterRouter.scala:87:24] wire out_romask_65 = \|_out_romask_T_65; // @[RegisterRouter.scala:87:24] wire out_womask_65 = &_out_womask_T_65; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_65 = out_rivalid_65 & out_rimask_65; // @[RegisterRouter.scala:87:24] wire _out_T_764 = out_f_rivalid_65; // @[RegisterRouter.scala:87:24] assign out_f_roready_65 = out_roready_65 & out_romask_65; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_9 = out_f_roready_65; // @[RegisterRouter.scala:87:24] wire _out_T_765 = out_f_roready_65; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_65 = out_wivalid_65 & out_wimask_65; // @[RegisterRouter.scala:87:24] wire _out_T_766 = out_f_wivalid_65; // @[RegisterRouter.scala:87:24] assign out_f_woready_65 = out_woready_65 & out_womask_65; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_9 = out_f_woready_65; // @[RegisterRouter.scala:87:24] wire _out_T_767 = out_f_woready_65; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_9 = out_f_woready_65 ? _out_T_763 : abstractDataMem_9; // @[RegisterRouter.scala:87:24] wire _out_T_768 = ~out_rimask_65; // @[RegisterRouter.scala:87:24] wire _out_T_769 = ~out_wimask_65; // @[RegisterRouter.scala:87:24] wire _out_T_770 = ~out_romask_65; // @[RegisterRouter.scala:87:24] wire _out_T_771 = ~out_womask_65; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_49 = {abstractDataMem_9, _out_prepend_T_49}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_772 = out_prepend_49; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_773 = _out_T_772; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_50 = _out_T_773; // @[RegisterRouter.scala:87:24] wire out_rimask_66 = \|_out_rimask_T_66; // @[RegisterRouter.scala:87:24] wire out_wimask_66 = &_out_wimask_T_66; // @[RegisterRouter.scala:87:24] wire out_romask_66 = \|_out_romask_T_66; // @[RegisterRouter.scala:87:24] wire out_womask_66 = &_out_womask_T_66; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_66 = out_rivalid_66 & out_rimask_66; // @[RegisterRouter.scala:87:24] wire _out_T_775 = out_f_rivalid_66; // @[RegisterRouter.scala:87:24] assign out_f_roready_66 = out_roready_66 & out_romask_66; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_10 = out_f_roready_66; // @[RegisterRouter.scala:87:24] wire _out_T_776 = out_f_roready_66; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_66 = out_wivalid_66 & out_wimask_66; // @[RegisterRouter.scala:87:24] wire _out_T_777 = out_f_wivalid_66; // @[RegisterRouter.scala:87:24] assign out_f_woready_66 = out_woready_66 & out_womask_66; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_10 = out_f_woready_66; // @[RegisterRouter.scala:87:24] wire _out_T_778 = out_f_woready_66; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_10 = out_f_woready_66 ? _out_T_774 : abstractDataMem_10; // @[RegisterRouter.scala:87:24] wire _out_T_779 = ~out_rimask_66; // @[RegisterRouter.scala:87:24] wire _out_T_780 = ~out_wimask_66; // @[RegisterRouter.scala:87:24] wire _out_T_781 = ~out_romask_66; // @[RegisterRouter.scala:87:24] wire _out_T_782 = ~out_womask_66; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_50 = {abstractDataMem_10, _out_prepend_T_50}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_783 = out_prepend_50; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_784 = _out_T_783; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_51 = _out_T_784; // @[RegisterRouter.scala:87:24] wire out_rimask_67 = \|_out_rimask_T_67; // @[RegisterRouter.scala:87:24] wire out_wimask_67 = &_out_wimask_T_67; // @[RegisterRouter.scala:87:24] wire out_romask_67 = \|_out_romask_T_67; // @[RegisterRouter.scala:87:24] wire out_womask_67 = &_out_womask_T_67; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_67 = out_rivalid_67 & out_rimask_67; // @[RegisterRouter.scala:87:24] wire _out_T_786 = out_f_rivalid_67; // @[RegisterRouter.scala:87:24] assign out_f_roready_67 = out_roready_67 & out_romask_67; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_11 = out_f_roready_67; // @[RegisterRouter.scala:87:24] wire _out_T_787 = out_f_roready_67; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_67 = out_wivalid_67 & out_wimask_67; // @[RegisterRouter.scala:87:24] wire _out_T_788 = out_f_wivalid_67; // @[RegisterRouter.scala:87:24] assign out_f_woready_67 = out_woready_67 & out_womask_67; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_11 = out_f_woready_67; // @[RegisterRouter.scala:87:24] wire _out_T_789 = out_f_woready_67; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_11 = out_f_woready_67 ? _out_T_785 : abstractDataMem_11; // @[RegisterRouter.scala:87:24] wire _out_T_790 = ~out_rimask_67; // @[RegisterRouter.scala:87:24] wire _out_T_791 = ~out_wimask_67; // @[RegisterRouter.scala:87:24] wire _out_T_792 = ~out_romask_67; // @[RegisterRouter.scala:87:24] wire _out_T_793 = ~out_womask_67; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_51 = {abstractDataMem_11, _out_prepend_T_51}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_794 = out_prepend_51; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_795 = _out_T_794; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_6 = _out_T_795; // @[MuxLiteral.scala:49:48] wire out_rimask_68 = \|_out_rimask_T_68; // @[RegisterRouter.scala:87:24] wire out_wimask_68 = &_out_wimask_T_68; // @[RegisterRouter.scala:87:24] wire out_romask_68 = \|_out_romask_T_68; // @[RegisterRouter.scala:87:24] wire out_womask_68 = &_out_womask_T_68; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_68 = out_rivalid_68 & out_rimask_68; // @[RegisterRouter.scala:87:24] wire _out_T_797 = out_f_rivalid_68; // @[RegisterRouter.scala:87:24] assign out_f_roready_68 = out_roready_68 & out_romask_68; // @[RegisterRouter.scala:87:24] assign SBDATARdEn_0 = out_f_roready_68; // @[RegisterRouter.scala:87:24] wire _out_T_798 = out_f_roready_68; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_68 = out_wivalid_68 & out_wimask_68; // @[RegisterRouter.scala:87:24] wire _out_T_799 = out_f_wivalid_68; // @[RegisterRouter.scala:87:24] assign out_f_woready_68 = out_woready_68 & out_womask_68; // @[RegisterRouter.scala:87:24] assign SBDATAWrEn_0 = out_f_woready_68; // @[RegisterRouter.scala:87:24] wire _out_T_800 = out_f_woready_68; // @[RegisterRouter.scala:87:24] assign SBDATAWrData_0 = out_f_woready_68 ? _out_T_796 : 32'h0; // @[RegisterRouter.scala:87:24] wire _out_T_801 = ~out_rimask_68; // @[RegisterRouter.scala:87:24] wire _out_T_802 = ~out_wimask_68; // @[RegisterRouter.scala:87:24] wire _out_T_803 = ~out_romask_68; // @[RegisterRouter.scala:87:24] wire _out_T_804 = ~out_womask_68; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_806 = _out_T_805; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_60 = _out_T_806; // @[MuxLiteral.scala:49:48] wire out_rimask_69 = \|_out_rimask_T_69; // @[RegisterRouter.scala:87:24] wire out_wimask_69 = &_out_wimask_T_69; // @[RegisterRouter.scala:87:24] wire out_romask_69 = \|_out_romask_T_69; // @[RegisterRouter.scala:87:24] wire out_womask_69 = &_out_womask_T_69; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_69 = out_rivalid_69 & out_rimask_69; // @[RegisterRouter.scala:87:24] wire _out_T_808 = out_f_rivalid_69; // @[RegisterRouter.scala:87:24] assign out_f_roready_69 = out_roready_69 & out_romask_69; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_24 = out_f_roready_69; // @[RegisterRouter.scala:87:24] wire _out_T_809 = out_f_roready_69; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_69 = out_wivalid_69 & out_wimask_69; // @[RegisterRouter.scala:87:24] wire _out_T_810 = out_f_wivalid_69; // @[RegisterRouter.scala:87:24] assign out_f_woready_69 = out_woready_69 & out_womask_69; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_24 = out_f_woready_69; // @[RegisterRouter.scala:87:24] wire _out_T_811 = out_f_woready_69; // @[RegisterRouter.scala:87:24] assign programBufferNxt_24 = out_f_woready_69 ? _out_T_807 : programBufferMem_24; // @[RegisterRouter.scala:87:24] wire _out_T_812 = ~out_rimask_69; // @[RegisterRouter.scala:87:24] wire _out_T_813 = ~out_wimask_69; // @[RegisterRouter.scala:87:24] wire _out_T_814 = ~out_romask_69; // @[RegisterRouter.scala:87:24] wire _out_T_815 = ~out_womask_69; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_817 = _out_T_816; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_52 = _out_T_817; // @[RegisterRouter.scala:87:24] wire out_rimask_70 = \|_out_rimask_T_70; // @[RegisterRouter.scala:87:24] wire out_wimask_70 = &_out_wimask_T_70; // @[RegisterRouter.scala:87:24] wire out_romask_70 = \|_out_romask_T_70; // @[RegisterRouter.scala:87:24] wire out_womask_70 = &_out_womask_T_70; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_70 = out_rivalid_70 & out_rimask_70; // @[RegisterRouter.scala:87:24] wire _out_T_819 = out_f_rivalid_70; // @[RegisterRouter.scala:87:24] assign out_f_roready_70 = out_roready_70 & out_romask_70; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_25 = out_f_roready_70; // @[RegisterRouter.scala:87:24] wire _out_T_820 = out_f_roready_70; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_70 = out_wivalid_70 & out_wimask_70; // @[RegisterRouter.scala:87:24] wire _out_T_821 = out_f_wivalid_70; // @[RegisterRouter.scala:87:24] assign out_f_woready_70 = out_woready_70 & out_womask_70; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_25 = out_f_woready_70; // @[RegisterRouter.scala:87:24] wire _out_T_822 = out_f_woready_70; // @[RegisterRouter.scala:87:24] assign programBufferNxt_25 = out_f_woready_70 ? _out_T_818 : programBufferMem_25; // @[RegisterRouter.scala:87:24] wire _out_T_823 = ~out_rimask_70; // @[RegisterRouter.scala:87:24] wire _out_T_824 = ~out_wimask_70; // @[RegisterRouter.scala:87:24] wire _out_T_825 = ~out_romask_70; // @[RegisterRouter.scala:87:24] wire _out_T_826 = ~out_womask_70; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_52 = {programBufferMem_25, _out_prepend_T_52}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_827 = out_prepend_52; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_828 = _out_T_827; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_53 = _out_T_828; // @[RegisterRouter.scala:87:24] wire out_rimask_71 = \|_out_rimask_T_71; // @[RegisterRouter.scala:87:24] wire out_wimask_71 = &_out_wimask_T_71; // @[RegisterRouter.scala:87:24] wire out_romask_71 = \|_out_romask_T_71; // @[RegisterRouter.scala:87:24] wire out_womask_71 = &_out_womask_T_71; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_71 = out_rivalid_71 & out_rimask_71; // @[RegisterRouter.scala:87:24] wire _out_T_830 = out_f_rivalid_71; // @[RegisterRouter.scala:87:24] assign out_f_roready_71 = out_roready_71 & out_romask_71; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_26 = out_f_roready_71; // @[RegisterRouter.scala:87:24] wire _out_T_831 = out_f_roready_71; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_71 = out_wivalid_71 & out_wimask_71; // @[RegisterRouter.scala:87:24] wire _out_T_832 = out_f_wivalid_71; // @[RegisterRouter.scala:87:24] assign out_f_woready_71 = out_woready_71 & out_womask_71; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_26 = out_f_woready_71; // @[RegisterRouter.scala:87:24] wire _out_T_833 = out_f_woready_71; // @[RegisterRouter.scala:87:24] assign programBufferNxt_26 = out_f_woready_71 ? _out_T_829 : programBufferMem_26; // @[RegisterRouter.scala:87:24] wire _out_T_834 = ~out_rimask_71; // @[RegisterRouter.scala:87:24] wire _out_T_835 = ~out_wimask_71; // @[RegisterRouter.scala:87:24] wire _out_T_836 = ~out_romask_71; // @[RegisterRouter.scala:87:24] wire _out_T_837 = ~out_womask_71; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_53 = {programBufferMem_26, _out_prepend_T_53}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_838 = out_prepend_53; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_839 = _out_T_838; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_54 = _out_T_839; // @[RegisterRouter.scala:87:24] wire out_rimask_72 = \|_out_rimask_T_72; // @[RegisterRouter.scala:87:24] wire out_wimask_72 = &_out_wimask_T_72; // @[RegisterRouter.scala:87:24] wire out_romask_72 = \|_out_romask_T_72; // @[RegisterRouter.scala:87:24] wire out_womask_72 = &_out_womask_T_72; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_72 = out_rivalid_72 & out_rimask_72; // @[RegisterRouter.scala:87:24] wire _out_T_841 = out_f_rivalid_72; // @[RegisterRouter.scala:87:24] assign out_f_roready_72 = out_roready_72 & out_romask_72; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_27 = out_f_roready_72; // @[RegisterRouter.scala:87:24] wire _out_T_842 = out_f_roready_72; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_72 = out_wivalid_72 & out_wimask_72; // @[RegisterRouter.scala:87:24] wire _out_T_843 = out_f_wivalid_72; // @[RegisterRouter.scala:87:24] assign out_f_woready_72 = out_woready_72 & out_womask_72; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_27 = out_f_woready_72; // @[RegisterRouter.scala:87:24] wire _out_T_844 = out_f_woready_72; // @[RegisterRouter.scala:87:24] assign programBufferNxt_27 = out_f_woready_72 ? _out_T_840 : programBufferMem_27; // @[RegisterRouter.scala:87:24] wire _out_T_845 = ~out_rimask_72; // @[RegisterRouter.scala:87:24] wire _out_T_846 = ~out_wimask_72; // @[RegisterRouter.scala:87:24] wire _out_T_847 = ~out_romask_72; // @[RegisterRouter.scala:87:24] wire _out_T_848 = ~out_womask_72; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_54 = {programBufferMem_27, _out_prepend_T_54}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_849 = out_prepend_54; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_850 = _out_T_849; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_38 = _out_T_850; // @[MuxLiteral.scala:49:48] wire out_rimask_73 = \|_out_rimask_T_73; // @[RegisterRouter.scala:87:24] wire out_wimask_73 = &_out_wimask_T_73; // @[RegisterRouter.scala:87:24] wire out_romask_73 = \|_out_romask_T_73; // @[RegisterRouter.scala:87:24] wire out_womask_73 = &_out_womask_T_73; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_73 = out_rivalid_73 & out_rimask_73; // @[RegisterRouter.scala:87:24] wire _out_T_852 = out_f_rivalid_73; // @[RegisterRouter.scala:87:24] assign out_f_roready_73 = out_roready_73 & out_romask_73; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_4 = out_f_roready_73; // @[RegisterRouter.scala:87:24] wire _out_T_853 = out_f_roready_73; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_73 = out_wivalid_73 & out_wimask_73; // @[RegisterRouter.scala:87:24] wire _out_T_854 = out_f_wivalid_73; // @[RegisterRouter.scala:87:24] assign out_f_woready_73 = out_woready_73 & out_womask_73; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_4 = out_f_woready_73; // @[RegisterRouter.scala:87:24] wire _out_T_855 = out_f_woready_73; // @[RegisterRouter.scala:87:24] assign programBufferNxt_4 = out_f_woready_73 ? _out_T_851 : programBufferMem_4; // @[RegisterRouter.scala:87:24] wire _out_T_856 = ~out_rimask_73; // @[RegisterRouter.scala:87:24] wire _out_T_857 = ~out_wimask_73; // @[RegisterRouter.scala:87:24] wire _out_T_858 = ~out_romask_73; // @[RegisterRouter.scala:87:24] wire _out_T_859 = ~out_womask_73; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_861 = _out_T_860; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_55 = _out_T_861; // @[RegisterRouter.scala:87:24] wire out_rimask_74 = \|_out_rimask_T_74; // @[RegisterRouter.scala:87:24] wire out_wimask_74 = &_out_wimask_T_74; // @[RegisterRouter.scala:87:24] wire out_romask_74 = \|_out_romask_T_74; // @[RegisterRouter.scala:87:24] wire out_womask_74 = &_out_womask_T_74; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_74 = out_rivalid_74 & out_rimask_74; // @[RegisterRouter.scala:87:24] wire _out_T_863 = out_f_rivalid_74; // @[RegisterRouter.scala:87:24] assign out_f_roready_74 = out_roready_74 & out_romask_74; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_5 = out_f_roready_74; // @[RegisterRouter.scala:87:24] wire _out_T_864 = out_f_roready_74; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_74 = out_wivalid_74 & out_wimask_74; // @[RegisterRouter.scala:87:24] wire _out_T_865 = out_f_wivalid_74; // @[RegisterRouter.scala:87:24] assign out_f_woready_74 = out_woready_74 & out_womask_74; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_5 = out_f_woready_74; // @[RegisterRouter.scala:87:24] wire _out_T_866 = out_f_woready_74; // @[RegisterRouter.scala:87:24] assign programBufferNxt_5 = out_f_woready_74 ? _out_T_862 : programBufferMem_5; // @[RegisterRouter.scala:87:24] wire _out_T_867 = ~out_rimask_74; // @[RegisterRouter.scala:87:24] wire _out_T_868 = ~out_wimask_74; // @[RegisterRouter.scala:87:24] wire _out_T_869 = ~out_romask_74; // @[RegisterRouter.scala:87:24] wire _out_T_870 = ~out_womask_74; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_55 = {programBufferMem_5, _out_prepend_T_55}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_871 = out_prepend_55; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_872 = _out_T_871; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_56 = _out_T_872; // @[RegisterRouter.scala:87:24] wire out_rimask_75 = \|_out_rimask_T_75; // @[RegisterRouter.scala:87:24] wire out_wimask_75 = &_out_wimask_T_75; // @[RegisterRouter.scala:87:24] wire out_romask_75 = \|_out_romask_T_75; // @[RegisterRouter.scala:87:24] wire out_womask_75 = &_out_womask_T_75; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_75 = out_rivalid_75 & out_rimask_75; // @[RegisterRouter.scala:87:24] wire _out_T_874 = out_f_rivalid_75; // @[RegisterRouter.scala:87:24] assign out_f_roready_75 = out_roready_75 & out_romask_75; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_6 = out_f_roready_75; // @[RegisterRouter.scala:87:24] wire _out_T_875 = out_f_roready_75; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_75 = out_wivalid_75 & out_wimask_75; // @[RegisterRouter.scala:87:24] wire _out_T_876 = out_f_wivalid_75; // @[RegisterRouter.scala:87:24] assign out_f_woready_75 = out_woready_75 & out_womask_75; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_6 = out_f_woready_75; // @[RegisterRouter.scala:87:24] wire _out_T_877 = out_f_woready_75; // @[RegisterRouter.scala:87:24] assign programBufferNxt_6 = out_f_woready_75 ? _out_T_873 : programBufferMem_6; // @[RegisterRouter.scala:87:24] wire _out_T_878 = ~out_rimask_75; // @[RegisterRouter.scala:87:24] wire _out_T_879 = ~out_wimask_75; // @[RegisterRouter.scala:87:24] wire _out_T_880 = ~out_romask_75; // @[RegisterRouter.scala:87:24] wire _out_T_881 = ~out_womask_75; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_56 = {programBufferMem_6, _out_prepend_T_56}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_882 = out_prepend_56; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_883 = _out_T_882; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_57 = _out_T_883; // @[RegisterRouter.scala:87:24] wire out_rimask_76 = \|_out_rimask_T_76; // @[RegisterRouter.scala:87:24] wire out_wimask_76 = &_out_wimask_T_76; // @[RegisterRouter.scala:87:24] wire out_romask_76 = \|_out_romask_T_76; // @[RegisterRouter.scala:87:24] wire out_womask_76 = &_out_womask_T_76; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_76 = out_rivalid_76 & out_rimask_76; // @[RegisterRouter.scala:87:24] wire _out_T_885 = out_f_rivalid_76; // @[RegisterRouter.scala:87:24] assign out_f_roready_76 = out_roready_76 & out_romask_76; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_7 = out_f_roready_76; // @[RegisterRouter.scala:87:24] wire _out_T_886 = out_f_roready_76; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_76 = out_wivalid_76 & out_wimask_76; // @[RegisterRouter.scala:87:24] wire _out_T_887 = out_f_wivalid_76; // @[RegisterRouter.scala:87:24] assign out_f_woready_76 = out_woready_76 & out_womask_76; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_7 = out_f_woready_76; // @[RegisterRouter.scala:87:24] wire _out_T_888 = out_f_woready_76; // @[RegisterRouter.scala:87:24] assign programBufferNxt_7 = out_f_woready_76 ? _out_T_884 : programBufferMem_7; // @[RegisterRouter.scala:87:24] wire _out_T_889 = ~out_rimask_76; // @[RegisterRouter.scala:87:24] wire _out_T_890 = ~out_wimask_76; // @[RegisterRouter.scala:87:24] wire _out_T_891 = ~out_romask_76; // @[RegisterRouter.scala:87:24] wire _out_T_892 = ~out_womask_76; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_57 = {programBufferMem_7, _out_prepend_T_57}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_893 = out_prepend_57; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_894 = _out_T_893; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_33 = _out_T_894; // @[MuxLiteral.scala:49:48] wire out_rimask_77 = \|_out_rimask_T_77; // @[RegisterRouter.scala:87:24] wire out_wimask_77 = &_out_wimask_T_77; // @[RegisterRouter.scala:87:24] wire out_romask_77 = \|_out_romask_T_77; // @[RegisterRouter.scala:87:24] wire out_womask_77 = &_out_womask_T_77; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_77 = out_rivalid_77 & out_rimask_77; // @[RegisterRouter.scala:87:24] wire _out_T_896 = out_f_rivalid_77; // @[RegisterRouter.scala:87:24] assign out_f_roready_77 = out_roready_77 & out_romask_77; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_52 = out_f_roready_77; // @[RegisterRouter.scala:87:24] wire _out_T_897 = out_f_roready_77; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_77 = out_wivalid_77 & out_wimask_77; // @[RegisterRouter.scala:87:24] wire _out_T_898 = out_f_wivalid_77; // @[RegisterRouter.scala:87:24] assign out_f_woready_77 = out_woready_77 & out_womask_77; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_52 = out_f_woready_77; // @[RegisterRouter.scala:87:24] wire _out_T_899 = out_f_woready_77; // @[RegisterRouter.scala:87:24] assign programBufferNxt_52 = out_f_woready_77 ? _out_T_895 : programBufferMem_52; // @[RegisterRouter.scala:87:24] wire _out_T_900 = ~out_rimask_77; // @[RegisterRouter.scala:87:24] wire _out_T_901 = ~out_wimask_77; // @[RegisterRouter.scala:87:24] wire _out_T_902 = ~out_romask_77; // @[RegisterRouter.scala:87:24] wire _out_T_903 = ~out_womask_77; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_905 = _out_T_904; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_58 = _out_T_905; // @[RegisterRouter.scala:87:24] wire out_rimask_78 = \|_out_rimask_T_78; // @[RegisterRouter.scala:87:24] wire out_wimask_78 = &_out_wimask_T_78; // @[RegisterRouter.scala:87:24] wire out_romask_78 = \|_out_romask_T_78; // @[RegisterRouter.scala:87:24] wire out_womask_78 = &_out_womask_T_78; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_78 = out_rivalid_78 & out_rimask_78; // @[RegisterRouter.scala:87:24] wire _out_T_907 = out_f_rivalid_78; // @[RegisterRouter.scala:87:24] assign out_f_roready_78 = out_roready_78 & out_romask_78; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_53 = out_f_roready_78; // @[RegisterRouter.scala:87:24] wire _out_T_908 = out_f_roready_78; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_78 = out_wivalid_78 & out_wimask_78; // @[RegisterRouter.scala:87:24] wire _out_T_909 = out_f_wivalid_78; // @[RegisterRouter.scala:87:24] assign out_f_woready_78 = out_woready_78 & out_womask_78; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_53 = out_f_woready_78; // @[RegisterRouter.scala:87:24] wire _out_T_910 = out_f_woready_78; // @[RegisterRouter.scala:87:24] assign programBufferNxt_53 = out_f_woready_78 ? _out_T_906 : programBufferMem_53; // @[RegisterRouter.scala:87:24] wire _out_T_911 = ~out_rimask_78; // @[RegisterRouter.scala:87:24] wire _out_T_912 = ~out_wimask_78; // @[RegisterRouter.scala:87:24] wire _out_T_913 = ~out_romask_78; // @[RegisterRouter.scala:87:24] wire _out_T_914 = ~out_womask_78; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_58 = {programBufferMem_53, _out_prepend_T_58}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_915 = out_prepend_58; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_916 = _out_T_915; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_59 = _out_T_916; // @[RegisterRouter.scala:87:24] wire out_rimask_79 = \|_out_rimask_T_79; // @[RegisterRouter.scala:87:24] wire out_wimask_79 = &_out_wimask_T_79; // @[RegisterRouter.scala:87:24] wire out_romask_79 = \|_out_romask_T_79; // @[RegisterRouter.scala:87:24] wire out_womask_79 = &_out_womask_T_79; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_79 = out_rivalid_79 & out_rimask_79; // @[RegisterRouter.scala:87:24] wire _out_T_918 = out_f_rivalid_79; // @[RegisterRouter.scala:87:24] assign out_f_roready_79 = out_roready_79 & out_romask_79; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_54 = out_f_roready_79; // @[RegisterRouter.scala:87:24] wire _out_T_919 = out_f_roready_79; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_79 = out_wivalid_79 & out_wimask_79; // @[RegisterRouter.scala:87:24] wire _out_T_920 = out_f_wivalid_79; // @[RegisterRouter.scala:87:24] assign out_f_woready_79 = out_woready_79 & out_womask_79; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_54 = out_f_woready_79; // @[RegisterRouter.scala:87:24] wire _out_T_921 = out_f_woready_79; // @[RegisterRouter.scala:87:24] assign programBufferNxt_54 = out_f_woready_79 ? _out_T_917 : programBufferMem_54; // @[RegisterRouter.scala:87:24] wire _out_T_922 = ~out_rimask_79; // @[RegisterRouter.scala:87:24] wire _out_T_923 = ~out_wimask_79; // @[RegisterRouter.scala:87:24] wire _out_T_924 = ~out_romask_79; // @[RegisterRouter.scala:87:24] wire _out_T_925 = ~out_womask_79; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_59 = {programBufferMem_54, _out_prepend_T_59}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_926 = out_prepend_59; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_927 = _out_T_926; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_60 = _out_T_927; // @[RegisterRouter.scala:87:24] wire out_rimask_80 = \|_out_rimask_T_80; // @[RegisterRouter.scala:87:24] wire out_wimask_80 = &_out_wimask_T_80; // @[RegisterRouter.scala:87:24] wire out_romask_80 = \|_out_romask_T_80; // @[RegisterRouter.scala:87:24] wire out_womask_80 = &_out_womask_T_80; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_80 = out_rivalid_80 & out_rimask_80; // @[RegisterRouter.scala:87:24] wire _out_T_929 = out_f_rivalid_80; // @[RegisterRouter.scala:87:24] assign out_f_roready_80 = out_roready_80 & out_romask_80; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_55 = out_f_roready_80; // @[RegisterRouter.scala:87:24] wire _out_T_930 = out_f_roready_80; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_80 = out_wivalid_80 & out_wimask_80; // @[RegisterRouter.scala:87:24] wire _out_T_931 = out_f_wivalid_80; // @[RegisterRouter.scala:87:24] assign out_f_woready_80 = out_woready_80 & out_womask_80; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_55 = out_f_woready_80; // @[RegisterRouter.scala:87:24] wire _out_T_932 = out_f_woready_80; // @[RegisterRouter.scala:87:24] assign programBufferNxt_55 = out_f_woready_80 ? _out_T_928 : programBufferMem_55; // @[RegisterRouter.scala:87:24] wire _out_T_933 = ~out_rimask_80; // @[RegisterRouter.scala:87:24] wire _out_T_934 = ~out_wimask_80; // @[RegisterRouter.scala:87:24] wire _out_T_935 = ~out_romask_80; // @[RegisterRouter.scala:87:24] wire _out_T_936 = ~out_womask_80; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_60 = {programBufferMem_55, _out_prepend_T_60}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_937 = out_prepend_60; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_938 = _out_T_937; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_45 = _out_T_938; // @[MuxLiteral.scala:49:48] wire out_rimask_81 = \|_out_rimask_T_81; // @[RegisterRouter.scala:87:24] wire out_wimask_81 = &_out_wimask_T_81; // @[RegisterRouter.scala:87:24] wire out_romask_81 = \|_out_romask_T_81; // @[RegisterRouter.scala:87:24] wire out_womask_81 = &_out_womask_T_81; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_81 = out_rivalid_81 & out_rimask_81; // @[RegisterRouter.scala:87:24] wire _out_T_940 = out_f_rivalid_81; // @[RegisterRouter.scala:87:24] wire out_f_roready_81 = out_roready_81 & out_romask_81; // @[RegisterRouter.scala:87:24] wire _out_T_941 = out_f_roready_81; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_81 = out_wivalid_81 & out_wimask_81; // @[RegisterRouter.scala:87:24] wire out_f_woready_81 = out_woready_81 & out_womask_81; // @[RegisterRouter.scala:87:24] wire _out_T_942 = ~out_rimask_81; // @[RegisterRouter.scala:87:24] wire _out_T_943 = ~out_wimask_81; // @[RegisterRouter.scala:87:24] wire _out_T_944 = ~out_romask_81; // @[RegisterRouter.scala:87:24] wire _out_T_945 = ~out_womask_81; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_947 = _out_T_946; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_0 = _out_T_947; // @[MuxLiteral.scala:49:48] wire [3:0] _out_rimask_T_82 = out_frontMask[3:0]; // @[RegisterRouter.scala:87:24] wire [3:0] _out_wimask_T_82 = out_frontMask[3:0]; // @[RegisterRouter.scala:87:24] wire [3:0] _out_rimask_T_109 = out_frontMask[3:0]; // @[RegisterRouter.scala:87:24] wire [3:0] _out_wimask_T_109 = out_frontMask[3:0]; // @[RegisterRouter.scala:87:24] wire out_rimask_82 = \|_out_rimask_T_82; // @[RegisterRouter.scala:87:24] wire out_wimask_82 = &_out_wimask_T_82; // @[RegisterRouter.scala:87:24] wire [3:0] _out_romask_T_82 = out_backMask[3:0]; // @[RegisterRouter.scala:87:24] wire [3:0] _out_womask_T_82 = out_backMask[3:0]; // @[RegisterRouter.scala:87:24] wire [3:0] _out_romask_T_109 = out_backMask[3:0]; // @[RegisterRouter.scala:87:24] wire [3:0] _out_womask_T_109 = out_backMask[3:0]; // @[RegisterRouter.scala:87:24] wire out_romask_82 = \|_out_romask_T_82; // @[RegisterRouter.scala:87:24] wire out_womask_82 = &_out_womask_T_82; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_82 = out_rivalid_82 & out_rimask_82; // @[RegisterRouter.scala:87:24] wire _out_T_949 = out_f_rivalid_82; // @[RegisterRouter.scala:87:24] wire out_f_roready_82 = out_roready_82 & out_romask_82; // @[RegisterRouter.scala:87:24] wire _out_T_950 = out_f_roready_82; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_82 = out_wivalid_82 & out_wimask_82; // @[RegisterRouter.scala:87:24] wire out_f_woready_82 = out_woready_82 & out_womask_82; // @[RegisterRouter.scala:87:24] wire [3:0] _out_T_948 = out_front_bits_data[3:0]; // @[RegisterRouter.scala:87:24] wire [3:0] _out_T_1207 = out_front_bits_data[3:0]; // @[RegisterRouter.scala:87:24] wire _out_T_951 = ~out_rimask_82; // @[RegisterRouter.scala:87:24] wire _out_T_952 = ~out_wimask_82; // @[RegisterRouter.scala:87:24] wire _out_T_953 = ~out_romask_82; // @[RegisterRouter.scala:87:24] wire _out_T_954 = ~out_womask_82; // @[RegisterRouter.scala:87:24] wire out_rimask_83 = _out_rimask_T_83; // @[RegisterRouter.scala:87:24] wire out_wimask_83 = _out_wimask_T_83; // @[RegisterRouter.scala:87:24] wire out_romask_83 = _out_romask_T_83; // @[RegisterRouter.scala:87:24] wire out_womask_83 = _out_womask_T_83; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_83 = out_rivalid_83 & out_rimask_83; // @[RegisterRouter.scala:87:24] wire _out_T_958 = out_f_rivalid_83; // @[RegisterRouter.scala:87:24] wire out_f_roready_83 = out_roready_83 & out_romask_83; // @[RegisterRouter.scala:87:24] wire _out_T_959 = out_f_roready_83; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_83 = out_wivalid_83 & out_wimask_83; // @[RegisterRouter.scala:87:24] wire out_f_woready_83 = out_woready_83 & out_womask_83; // @[RegisterRouter.scala:87:24] wire _out_T_960 = ~out_rimask_83; // @[RegisterRouter.scala:87:24] wire _out_T_961 = ~out_wimask_83; // @[RegisterRouter.scala:87:24] wire _out_T_962 = ~out_romask_83; // @[RegisterRouter.scala:87:24] wire _out_T_963 = ~out_womask_83; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_84 = out_frontMask[5]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_84 = out_frontMask[5]; // @[RegisterRouter.scala:87:24] wire out_rimask_84 = _out_rimask_T_84; // @[RegisterRouter.scala:87:24] wire out_wimask_84 = _out_wimask_T_84; // @[RegisterRouter.scala:87:24] wire _out_romask_T_84 = out_backMask[5]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_84 = out_backMask[5]; // @[RegisterRouter.scala:87:24] wire out_romask_84 = _out_romask_T_84; // @[RegisterRouter.scala:87:24] wire out_womask_84 = _out_womask_T_84; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_84 = out_rivalid_84 & out_rimask_84; // @[RegisterRouter.scala:87:24] wire _out_T_967 = out_f_rivalid_84; // @[RegisterRouter.scala:87:24] wire out_f_roready_84 = out_roready_84 & out_romask_84; // @[RegisterRouter.scala:87:24] wire _out_T_968 = out_f_roready_84; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_84 = out_wivalid_84 & out_wimask_84; // @[RegisterRouter.scala:87:24] wire out_f_woready_84 = out_woready_84 & out_womask_84; // @[RegisterRouter.scala:87:24] wire _out_T_966 = out_front_bits_data[5]; // @[RegisterRouter.scala:87:24] wire _out_T_969 = ~out_rimask_84; // @[RegisterRouter.scala:87:24] wire _out_T_970 = ~out_wimask_84; // @[RegisterRouter.scala:87:24] wire _out_T_971 = ~out_romask_84; // @[RegisterRouter.scala:87:24] wire _out_T_972 = ~out_womask_84; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_85 = out_frontMask[6]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_85 = out_frontMask[6]; // @[RegisterRouter.scala:87:24] wire out_rimask_85 = _out_rimask_T_85; // @[RegisterRouter.scala:87:24] wire out_wimask_85 = _out_wimask_T_85; // @[RegisterRouter.scala:87:24] wire _out_romask_T_85 = out_backMask[6]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_85 = out_backMask[6]; // @[RegisterRouter.scala:87:24] wire out_romask_85 = _out_romask_T_85; // @[RegisterRouter.scala:87:24] wire out_womask_85 = _out_womask_T_85; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_85 = out_rivalid_85 & out_rimask_85; // @[RegisterRouter.scala:87:24] wire _out_T_976 = out_f_rivalid_85; // @[RegisterRouter.scala:87:24] wire out_f_roready_85 = out_roready_85 & out_romask_85; // @[RegisterRouter.scala:87:24] wire _out_T_977 = out_f_roready_85; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_85 = out_wivalid_85 & out_wimask_85; // @[RegisterRouter.scala:87:24] wire out_f_woready_85 = out_woready_85 & out_womask_85; // @[RegisterRouter.scala:87:24] wire _out_T_975 = out_front_bits_data[6]; // @[RegisterRouter.scala:87:24] wire _out_T_978 = ~out_rimask_85; // @[RegisterRouter.scala:87:24] wire _out_T_979 = ~out_wimask_85; // @[RegisterRouter.scala:87:24] wire _out_T_980 = ~out_romask_85; // @[RegisterRouter.scala:87:24] wire _out_T_981 = ~out_womask_85; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_86 = out_frontMask[7]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_86 = out_frontMask[7]; // @[RegisterRouter.scala:87:24] wire out_rimask_86 = _out_rimask_T_86; // @[RegisterRouter.scala:87:24] wire out_wimask_86 = _out_wimask_T_86; // @[RegisterRouter.scala:87:24] wire _out_romask_T_86 = out_backMask[7]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_86 = out_backMask[7]; // @[RegisterRouter.scala:87:24] wire out_romask_86 = _out_romask_T_86; // @[RegisterRouter.scala:87:24] wire out_womask_86 = _out_womask_T_86; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_86 = out_rivalid_86 & out_rimask_86; // @[RegisterRouter.scala:87:24] wire _out_T_985 = out_f_rivalid_86; // @[RegisterRouter.scala:87:24] wire out_f_roready_86 = out_roready_86 & out_romask_86; // @[RegisterRouter.scala:87:24] wire _out_T_986 = out_f_roready_86; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_86 = out_wivalid_86 & out_wimask_86; // @[RegisterRouter.scala:87:24] wire out_f_woready_86 = out_woready_86 & out_womask_86; // @[RegisterRouter.scala:87:24] wire _out_T_984 = out_front_bits_data[7]; // @[RegisterRouter.scala:87:24] wire _out_T_987 = ~out_rimask_86; // @[RegisterRouter.scala:87:24] wire _out_T_988 = ~out_wimask_86; // @[RegisterRouter.scala:87:24] wire _out_T_989 = ~out_romask_86; // @[RegisterRouter.scala:87:24] wire _out_T_990 = ~out_womask_86; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_87 = out_frontMask[8]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_87 = out_frontMask[8]; // @[RegisterRouter.scala:87:24] wire out_rimask_87 = _out_rimask_T_87; // @[RegisterRouter.scala:87:24] wire out_wimask_87 = _out_wimask_T_87; // @[RegisterRouter.scala:87:24] wire _out_romask_T_87 = out_backMask[8]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_87 = out_backMask[8]; // @[RegisterRouter.scala:87:24] wire out_romask_87 = _out_romask_T_87; // @[RegisterRouter.scala:87:24] wire out_womask_87 = _out_womask_T_87; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_87 = out_rivalid_87 & out_rimask_87; // @[RegisterRouter.scala:87:24] wire _out_T_994 = out_f_rivalid_87; // @[RegisterRouter.scala:87:24] wire out_f_roready_87 = out_roready_87 & out_romask_87; // @[RegisterRouter.scala:87:24] wire _out_T_995 = out_f_roready_87; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_87 = out_wivalid_87 & out_wimask_87; // @[RegisterRouter.scala:87:24] wire out_f_woready_87 = out_woready_87 & out_womask_87; // @[RegisterRouter.scala:87:24] wire _out_T_993 = out_front_bits_data[8]; // @[RegisterRouter.scala:87:24] wire _out_T_996 = ~out_rimask_87; // @[RegisterRouter.scala:87:24] wire _out_T_997 = ~out_wimask_87; // @[RegisterRouter.scala:87:24] wire _out_T_998 = ~out_romask_87; // @[RegisterRouter.scala:87:24] wire _out_T_999 = ~out_womask_87; // @[RegisterRouter.scala:87:24] wire [8:0] out_prepend_65 = {DMSTATUSRdData_anyhalted, 8'hA2}; // @[RegisterRouter.scala:87:24] wire [8:0] _out_T_1000 = out_prepend_65; // @[RegisterRouter.scala:87:24] wire [8:0] _out_T_1001 = _out_T_1000; // @[RegisterRouter.scala:87:24] wire [8:0] _out_prepend_T_66 = _out_T_1001; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_88 = out_frontMask[9]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_88 = out_frontMask[9]; // @[RegisterRouter.scala:87:24] wire out_rimask_88 = _out_rimask_T_88; // @[RegisterRouter.scala:87:24] wire out_wimask_88 = _out_wimask_T_88; // @[RegisterRouter.scala:87:24] wire _out_romask_T_88 = out_backMask[9]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_88 = out_backMask[9]; // @[RegisterRouter.scala:87:24] wire out_romask_88 = _out_romask_T_88; // @[RegisterRouter.scala:87:24] wire out_womask_88 = _out_womask_T_88; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_88 = out_rivalid_88 & out_rimask_88; // @[RegisterRouter.scala:87:24] wire _out_T_1003 = out_f_rivalid_88; // @[RegisterRouter.scala:87:24] wire out_f_roready_88 = out_roready_88 & out_romask_88; // @[RegisterRouter.scala:87:24] wire _out_T_1004 = out_f_roready_88; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_88 = out_wivalid_88 & out_wimask_88; // @[RegisterRouter.scala:87:24] wire out_f_woready_88 = out_woready_88 & out_womask_88; // @[RegisterRouter.scala:87:24] wire _out_T_1002 = out_front_bits_data[9]; // @[RegisterRouter.scala:87:24] wire _out_T_1005 = ~out_rimask_88; // @[RegisterRouter.scala:87:24] wire _out_T_1006 = ~out_wimask_88; // @[RegisterRouter.scala:87:24] wire _out_T_1007 = ~out_romask_88; // @[RegisterRouter.scala:87:24] wire _out_T_1008 = ~out_womask_88; // @[RegisterRouter.scala:87:24] wire [9:0] out_prepend_66 = {DMSTATUSRdData_allhalted, _out_prepend_T_66}; // @[RegisterRouter.scala:87:24] wire [9:0] _out_T_1009 = out_prepend_66; // @[RegisterRouter.scala:87:24] wire [9:0] _out_T_1010 = _out_T_1009; // @[RegisterRouter.scala:87:24] wire [9:0] _out_prepend_T_67 = _out_T_1010; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_89 = out_frontMask[10]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_89 = out_frontMask[10]; // @[RegisterRouter.scala:87:24] wire out_rimask_89 = _out_rimask_T_89; // @[RegisterRouter.scala:87:24] wire out_wimask_89 = _out_wimask_T_89; // @[RegisterRouter.scala:87:24] wire _out_romask_T_89 = out_backMask[10]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_89 = out_backMask[10]; // @[RegisterRouter.scala:87:24] wire out_romask_89 = _out_romask_T_89; // @[RegisterRouter.scala:87:24] wire out_womask_89 = _out_womask_T_89; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_89 = out_rivalid_89 & out_rimask_89; // @[RegisterRouter.scala:87:24] wire _out_T_1012 = out_f_rivalid_89; // @[RegisterRouter.scala:87:24] wire out_f_roready_89 = out_roready_89 & out_romask_89; // @[RegisterRouter.scala:87:24] wire _out_T_1013 = out_f_roready_89; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_89 = out_wivalid_89 & out_wimask_89; // @[RegisterRouter.scala:87:24] wire out_f_woready_89 = out_woready_89 & out_womask_89; // @[RegisterRouter.scala:87:24] wire _out_T_1011 = out_front_bits_data[10]; // @[RegisterRouter.scala:87:24] wire _out_T_1014 = ~out_rimask_89; // @[RegisterRouter.scala:87:24] wire _out_T_1015 = ~out_wimask_89; // @[RegisterRouter.scala:87:24] wire _out_T_1016 = ~out_romask_89; // @[RegisterRouter.scala:87:24] wire _out_T_1017 = ~out_womask_89; // @[RegisterRouter.scala:87:24] wire [10:0] out_prepend_67 = {DMSTATUSRdData_anyrunning, _out_prepend_T_67}; // @[RegisterRouter.scala:87:24] wire [10:0] _out_T_1018 = out_prepend_67; // @[RegisterRouter.scala:87:24] wire [10:0] _out_T_1019 = _out_T_1018; // @[RegisterRouter.scala:87:24] wire [10:0] _out_prepend_T_68 = _out_T_1019; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_90 = out_frontMask[11]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_90 = out_frontMask[11]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_112 = out_frontMask[11]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_112 = out_frontMask[11]; // @[RegisterRouter.scala:87:24] wire out_rimask_90 = _out_rimask_T_90; // @[RegisterRouter.scala:87:24] wire out_wimask_90 = _out_wimask_T_90; // @[RegisterRouter.scala:87:24] wire _out_romask_T_90 = out_backMask[11]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_90 = out_backMask[11]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_112 = out_backMask[11]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_112 = out_backMask[11]; // @[RegisterRouter.scala:87:24] wire out_romask_90 = _out_romask_T_90; // @[RegisterRouter.scala:87:24] wire out_womask_90 = _out_womask_T_90; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_90 = out_rivalid_90 & out_rimask_90; // @[RegisterRouter.scala:87:24] wire _out_T_1021 = out_f_rivalid_90; // @[RegisterRouter.scala:87:24] wire out_f_roready_90 = out_roready_90 & out_romask_90; // @[RegisterRouter.scala:87:24] wire _out_T_1022 = out_f_roready_90; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_90 = out_wivalid_90 & out_wimask_90; // @[RegisterRouter.scala:87:24] wire out_f_woready_90 = out_woready_90 & out_womask_90; // @[RegisterRouter.scala:87:24] wire _out_T_1020 = out_front_bits_data[11]; // @[RegisterRouter.scala:87:24] wire _out_T_1236 = out_front_bits_data[11]; // @[RegisterRouter.scala:87:24] wire _out_T_1023 = ~out_rimask_90; // @[RegisterRouter.scala:87:24] wire _out_T_1024 = ~out_wimask_90; // @[RegisterRouter.scala:87:24] wire _out_T_1025 = ~out_romask_90; // @[RegisterRouter.scala:87:24] wire _out_T_1026 = ~out_womask_90; // @[RegisterRouter.scala:87:24] wire [11:0] out_prepend_68 = {DMSTATUSRdData_allrunning, _out_prepend_T_68}; // @[RegisterRouter.scala:87:24] wire [11:0] _out_T_1027 = out_prepend_68; // @[RegisterRouter.scala:87:24] wire [11:0] _out_T_1028 = _out_T_1027; // @[RegisterRouter.scala:87:24] wire [11:0] _out_prepend_T_69 = _out_T_1028; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_91 = out_frontMask[12]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_91 = out_frontMask[12]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_113 = out_frontMask[12]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_113 = out_frontMask[12]; // @[RegisterRouter.scala:87:24] wire out_rimask_91 = _out_rimask_T_91; // @[RegisterRouter.scala:87:24] wire out_wimask_91 = _out_wimask_T_91; // @[RegisterRouter.scala:87:24] wire _out_romask_T_91 = out_backMask[12]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_91 = out_backMask[12]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_113 = out_backMask[12]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_113 = out_backMask[12]; // @[RegisterRouter.scala:87:24] wire out_romask_91 = _out_romask_T_91; // @[RegisterRouter.scala:87:24] wire out_womask_91 = _out_womask_T_91; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_91 = out_rivalid_91 & out_rimask_91; // @[RegisterRouter.scala:87:24] wire _out_T_1030 = out_f_rivalid_91; // @[RegisterRouter.scala:87:24] wire out_f_roready_91 = out_roready_91 & out_romask_91; // @[RegisterRouter.scala:87:24] wire _out_T_1031 = out_f_roready_91; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_91 = out_wivalid_91 & out_wimask_91; // @[RegisterRouter.scala:87:24] wire out_f_woready_91 = out_woready_91 & out_womask_91; // @[RegisterRouter.scala:87:24] wire _out_T_1029 = out_front_bits_data[12]; // @[RegisterRouter.scala:87:24] wire _out_T_1245 = out_front_bits_data[12]; // @[RegisterRouter.scala:87:24] wire _out_T_1032 = ~out_rimask_91; // @[RegisterRouter.scala:87:24] wire _out_T_1033 = ~out_wimask_91; // @[RegisterRouter.scala:87:24] wire _out_T_1034 = ~out_romask_91; // @[RegisterRouter.scala:87:24] wire _out_T_1035 = ~out_womask_91; // @[RegisterRouter.scala:87:24] wire [12:0] out_prepend_69 = {1'h0, _out_prepend_T_69}; // @[RegisterRouter.scala:87:24] wire [12:0] _out_T_1036 = out_prepend_69; // @[RegisterRouter.scala:87:24] wire [12:0] _out_T_1037 = _out_T_1036; // @[RegisterRouter.scala:87:24] wire [12:0] _out_prepend_T_70 = _out_T_1037; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_92 = out_frontMask[13]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_92 = out_frontMask[13]; // @[RegisterRouter.scala:87:24] wire out_rimask_92 = _out_rimask_T_92; // @[RegisterRouter.scala:87:24] wire out_wimask_92 = _out_wimask_T_92; // @[RegisterRouter.scala:87:24] wire _out_romask_T_92 = out_backMask[13]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_92 = out_backMask[13]; // @[RegisterRouter.scala:87:24] wire out_romask_92 = _out_romask_T_92; // @[RegisterRouter.scala:87:24] wire out_womask_92 = _out_womask_T_92; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_92 = out_rivalid_92 & out_rimask_92; // @[RegisterRouter.scala:87:24] wire _out_T_1039 = out_f_rivalid_92; // @[RegisterRouter.scala:87:24] wire out_f_roready_92 = out_roready_92 & out_romask_92; // @[RegisterRouter.scala:87:24] wire _out_T_1040 = out_f_roready_92; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_92 = out_wivalid_92 & out_wimask_92; // @[RegisterRouter.scala:87:24] wire out_f_woready_92 = out_woready_92 & out_womask_92; // @[RegisterRouter.scala:87:24] wire _out_T_1038 = out_front_bits_data[13]; // @[RegisterRouter.scala:87:24] wire _out_T_1041 = ~out_rimask_92; // @[RegisterRouter.scala:87:24] wire _out_T_1042 = ~out_wimask_92; // @[RegisterRouter.scala:87:24] wire _out_T_1043 = ~out_romask_92; // @[RegisterRouter.scala:87:24] wire _out_T_1044 = ~out_womask_92; // @[RegisterRouter.scala:87:24] wire [13:0] out_prepend_70 = {DMSTATUSRdData_allunavail, _out_prepend_T_70}; // @[RegisterRouter.scala:87:24] wire [13:0] _out_T_1045 = out_prepend_70; // @[RegisterRouter.scala:87:24] wire [13:0] _out_T_1046 = _out_T_1045; // @[RegisterRouter.scala:87:24] wire [13:0] _out_prepend_T_71 = _out_T_1046; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_93 = out_frontMask[14]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_93 = out_frontMask[14]; // @[RegisterRouter.scala:87:24] wire out_rimask_93 = _out_rimask_T_93; // @[RegisterRouter.scala:87:24] wire out_wimask_93 = _out_wimask_T_93; // @[RegisterRouter.scala:87:24] wire _out_romask_T_93 = out_backMask[14]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_93 = out_backMask[14]; // @[RegisterRouter.scala:87:24] wire out_romask_93 = _out_romask_T_93; // @[RegisterRouter.scala:87:24] wire out_womask_93 = _out_womask_T_93; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_93 = out_rivalid_93 & out_rimask_93; // @[RegisterRouter.scala:87:24] wire _out_T_1048 = out_f_rivalid_93; // @[RegisterRouter.scala:87:24] wire out_f_roready_93 = out_roready_93 & out_romask_93; // @[RegisterRouter.scala:87:24] wire _out_T_1049 = out_f_roready_93; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_93 = out_wivalid_93 & out_wimask_93; // @[RegisterRouter.scala:87:24] wire out_f_woready_93 = out_woready_93 & out_womask_93; // @[RegisterRouter.scala:87:24] wire _out_T_1047 = out_front_bits_data[14]; // @[RegisterRouter.scala:87:24] wire _out_T_1050 = ~out_rimask_93; // @[RegisterRouter.scala:87:24] wire _out_T_1051 = ~out_wimask_93; // @[RegisterRouter.scala:87:24] wire _out_T_1052 = ~out_romask_93; // @[RegisterRouter.scala:87:24] wire _out_T_1053 = ~out_womask_93; // @[RegisterRouter.scala:87:24] wire [14:0] out_prepend_71 = {DMSTATUSRdData_anynonexistent, _out_prepend_T_71}; // @[RegisterRouter.scala:87:24] wire [14:0] _out_T_1054 = out_prepend_71; // @[RegisterRouter.scala:87:24] wire [14:0] _out_T_1055 = _out_T_1054; // @[RegisterRouter.scala:87:24] wire [14:0] _out_prepend_T_72 = _out_T_1055; // @[RegisterRouter.scala:87:24] wire out_rimask_94 = _out_rimask_T_94; // @[RegisterRouter.scala:87:24] wire out_wimask_94 = _out_wimask_T_94; // @[RegisterRouter.scala:87:24] wire out_romask_94 = _out_romask_T_94; // @[RegisterRouter.scala:87:24] wire out_womask_94 = _out_womask_T_94; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_94 = out_rivalid_94 & out_rimask_94; // @[RegisterRouter.scala:87:24] wire _out_T_1057 = out_f_rivalid_94; // @[RegisterRouter.scala:87:24] wire out_f_roready_94 = out_roready_94 & out_romask_94; // @[RegisterRouter.scala:87:24] wire _out_T_1058 = out_f_roready_94; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_94 = out_wivalid_94 & out_wimask_94; // @[RegisterRouter.scala:87:24] wire out_f_woready_94 = out_woready_94 & out_womask_94; // @[RegisterRouter.scala:87:24] wire _out_T_1059 = ~out_rimask_94; // @[RegisterRouter.scala:87:24] wire _out_T_1060 = ~out_wimask_94; // @[RegisterRouter.scala:87:24] wire _out_T_1061 = ~out_romask_94; // @[RegisterRouter.scala:87:24] wire _out_T_1062 = ~out_womask_94; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_72 = {DMSTATUSRdData_allnonexistent, _out_prepend_T_72}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1063 = out_prepend_72; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1064 = _out_T_1063; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_73 = _out_T_1064; // @[RegisterRouter.scala:87:24] wire out_rimask_95 = _out_rimask_T_95; // @[RegisterRouter.scala:87:24] wire out_wimask_95 = _out_wimask_T_95; // @[RegisterRouter.scala:87:24] wire out_romask_95 = _out_romask_T_95; // @[RegisterRouter.scala:87:24] wire out_womask_95 = _out_womask_T_95; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_95 = out_rivalid_95 & out_rimask_95; // @[RegisterRouter.scala:87:24] wire _out_T_1066 = out_f_rivalid_95; // @[RegisterRouter.scala:87:24] wire out_f_roready_95 = out_roready_95 & out_romask_95; // @[RegisterRouter.scala:87:24] wire _out_T_1067 = out_f_roready_95; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_95 = out_wivalid_95 & out_wimask_95; // @[RegisterRouter.scala:87:24] wire out_f_woready_95 = out_woready_95 & out_womask_95; // @[RegisterRouter.scala:87:24] wire _out_T_1068 = ~out_rimask_95; // @[RegisterRouter.scala:87:24] wire _out_T_1069 = ~out_wimask_95; // @[RegisterRouter.scala:87:24] wire _out_T_1070 = ~out_romask_95; // @[RegisterRouter.scala:87:24] wire _out_T_1071 = ~out_womask_95; // @[RegisterRouter.scala:87:24] wire [16:0] out_prepend_73 = {DMSTATUSRdData_anyresumeack, _out_prepend_T_73}; // @[RegisterRouter.scala:87:24] wire [16:0] _out_T_1072 = out_prepend_73; // @[RegisterRouter.scala:87:24] wire [16:0] _out_T_1073 = _out_T_1072; // @[RegisterRouter.scala:87:24] wire [16:0] _out_prepend_T_74 = _out_T_1073; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_96 = out_frontMask[17]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_96 = out_frontMask[17]; // @[RegisterRouter.scala:87:24] wire out_rimask_96 = _out_rimask_T_96; // @[RegisterRouter.scala:87:24] wire out_wimask_96 = _out_wimask_T_96; // @[RegisterRouter.scala:87:24] wire _out_romask_T_96 = out_backMask[17]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_96 = out_backMask[17]; // @[RegisterRouter.scala:87:24] wire out_romask_96 = _out_romask_T_96; // @[RegisterRouter.scala:87:24] wire out_womask_96 = _out_womask_T_96; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_96 = out_rivalid_96 & out_rimask_96; // @[RegisterRouter.scala:87:24] wire _out_T_1075 = out_f_rivalid_96; // @[RegisterRouter.scala:87:24] wire out_f_roready_96 = out_roready_96 & out_romask_96; // @[RegisterRouter.scala:87:24] wire _out_T_1076 = out_f_roready_96; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_96 = out_wivalid_96 & out_wimask_96; // @[RegisterRouter.scala:87:24] wire out_f_woready_96 = out_woready_96 & out_womask_96; // @[RegisterRouter.scala:87:24] wire _out_T_1074 = out_front_bits_data[17]; // @[RegisterRouter.scala:87:24] wire _out_T_1077 = ~out_rimask_96; // @[RegisterRouter.scala:87:24] wire _out_T_1078 = ~out_wimask_96; // @[RegisterRouter.scala:87:24] wire _out_T_1079 = ~out_romask_96; // @[RegisterRouter.scala:87:24] wire _out_T_1080 = ~out_womask_96; // @[RegisterRouter.scala:87:24] wire [17:0] out_prepend_74 = {DMSTATUSRdData_allresumeack, _out_prepend_T_74}; // @[RegisterRouter.scala:87:24] wire [17:0] _out_T_1081 = out_prepend_74; // @[RegisterRouter.scala:87:24] wire [17:0] _out_T_1082 = _out_T_1081; // @[RegisterRouter.scala:87:24] wire [17:0] _out_prepend_T_75 = _out_T_1082; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_97 = out_frontMask[18]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_97 = out_frontMask[18]; // @[RegisterRouter.scala:87:24] wire out_rimask_97 = _out_rimask_T_97; // @[RegisterRouter.scala:87:24] wire out_wimask_97 = _out_wimask_T_97; // @[RegisterRouter.scala:87:24] wire _out_romask_T_97 = out_backMask[18]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_97 = out_backMask[18]; // @[RegisterRouter.scala:87:24] wire out_romask_97 = _out_romask_T_97; // @[RegisterRouter.scala:87:24] wire out_womask_97 = _out_womask_T_97; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_97 = out_rivalid_97 & out_rimask_97; // @[RegisterRouter.scala:87:24] wire _out_T_1084 = out_f_rivalid_97; // @[RegisterRouter.scala:87:24] wire out_f_roready_97 = out_roready_97 & out_romask_97; // @[RegisterRouter.scala:87:24] wire _out_T_1085 = out_f_roready_97; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_97 = out_wivalid_97 & out_wimask_97; // @[RegisterRouter.scala:87:24] wire out_f_woready_97 = out_woready_97 & out_womask_97; // @[RegisterRouter.scala:87:24] wire _out_T_1083 = out_front_bits_data[18]; // @[RegisterRouter.scala:87:24] wire _out_T_1086 = ~out_rimask_97; // @[RegisterRouter.scala:87:24] wire _out_T_1087 = ~out_wimask_97; // @[RegisterRouter.scala:87:24] wire _out_T_1088 = ~out_romask_97; // @[RegisterRouter.scala:87:24] wire _out_T_1089 = ~out_womask_97; // @[RegisterRouter.scala:87:24] wire [18:0] out_prepend_75 = {DMSTATUSRdData_anyhavereset, _out_prepend_T_75}; // @[RegisterRouter.scala:87:24] wire [18:0] _out_T_1090 = out_prepend_75; // @[RegisterRouter.scala:87:24] wire [18:0] _out_T_1091 = _out_T_1090; // @[RegisterRouter.scala:87:24] wire [18:0] _out_prepend_T_76 = _out_T_1091; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_98 = out_frontMask[19]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_98 = out_frontMask[19]; // @[RegisterRouter.scala:87:24] wire out_rimask_98 = _out_rimask_T_98; // @[RegisterRouter.scala:87:24] wire out_wimask_98 = _out_wimask_T_98; // @[RegisterRouter.scala:87:24] wire _out_romask_T_98 = out_backMask[19]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_98 = out_backMask[19]; // @[RegisterRouter.scala:87:24] wire out_romask_98 = _out_romask_T_98; // @[RegisterRouter.scala:87:24] wire out_womask_98 = _out_womask_T_98; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_98 = out_rivalid_98 & out_rimask_98; // @[RegisterRouter.scala:87:24] wire _out_T_1093 = out_f_rivalid_98; // @[RegisterRouter.scala:87:24] wire out_f_roready_98 = out_roready_98 & out_romask_98; // @[RegisterRouter.scala:87:24] wire _out_T_1094 = out_f_roready_98; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_98 = out_wivalid_98 & out_wimask_98; // @[RegisterRouter.scala:87:24] wire out_f_woready_98 = out_woready_98 & out_womask_98; // @[RegisterRouter.scala:87:24] wire _out_T_1092 = out_front_bits_data[19]; // @[RegisterRouter.scala:87:24] wire _out_T_1095 = ~out_rimask_98; // @[RegisterRouter.scala:87:24] wire _out_T_1096 = ~out_wimask_98; // @[RegisterRouter.scala:87:24] wire _out_T_1097 = ~out_romask_98; // @[RegisterRouter.scala:87:24] wire _out_T_1098 = ~out_womask_98; // @[RegisterRouter.scala:87:24] wire [19:0] out_prepend_76 = {DMSTATUSRdData_allhavereset, _out_prepend_T_76}; // @[RegisterRouter.scala:87:24] wire [19:0] _out_T_1099 = out_prepend_76; // @[RegisterRouter.scala:87:24] wire [19:0] _out_T_1100 = _out_T_1099; // @[RegisterRouter.scala:87:24] wire [19:0] _out_prepend_T_77 = _out_T_1100; // @[RegisterRouter.scala:87:24] wire [1:0] _out_rimask_T_99 = out_frontMask[21:20]; // @[RegisterRouter.scala:87:24] wire [1:0] _out_wimask_T_99 = out_frontMask[21:20]; // @[RegisterRouter.scala:87:24] wire out_rimask_99 = \|_out_rimask_T_99; // @[RegisterRouter.scala:87:24] wire out_wimask_99 = &_out_wimask_T_99; // @[RegisterRouter.scala:87:24] wire [1:0] _out_romask_T_99 = out_backMask[21:20]; // @[RegisterRouter.scala:87:24] wire [1:0] _out_womask_T_99 = out_backMask[21:20]; // @[RegisterRouter.scala:87:24] wire out_romask_99 = \|_out_romask_T_99; // @[RegisterRouter.scala:87:24] wire out_womask_99 = &_out_womask_T_99; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_99 = out_rivalid_99 & out_rimask_99; // @[RegisterRouter.scala:87:24] wire _out_T_1102 = out_f_rivalid_99; // @[RegisterRouter.scala:87:24] wire out_f_roready_99 = out_roready_99 & out_romask_99; // @[RegisterRouter.scala:87:24] wire _out_T_1103 = out_f_roready_99; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_99 = out_wivalid_99 & out_wimask_99; // @[RegisterRouter.scala:87:24] wire out_f_woready_99 = out_woready_99 & out_womask_99; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_1101 = out_front_bits_data[21:20]; // @[RegisterRouter.scala:87:24] wire _out_T_1104 = ~out_rimask_99; // @[RegisterRouter.scala:87:24] wire _out_T_1105 = ~out_wimask_99; // @[RegisterRouter.scala:87:24] wire _out_T_1106 = ~out_romask_99; // @[RegisterRouter.scala:87:24] wire _out_T_1107 = ~out_womask_99; // @[RegisterRouter.scala:87:24] wire [20:0] out_prepend_77 = {1'h0, _out_prepend_T_77}; // @[RegisterRouter.scala:87:24] wire [21:0] _out_T_1108 = {1'h0, out_prepend_77}; // @[RegisterRouter.scala:87:24] wire [21:0] _out_T_1109 = _out_T_1108; // @[RegisterRouter.scala:87:24] wire [21:0] _out_prepend_T_78 = _out_T_1109; // @[RegisterRouter.scala:87:24] wire out_rimask_100 = _out_rimask_T_100; // @[RegisterRouter.scala:87:24] wire out_wimask_100 = _out_wimask_T_100; // @[RegisterRouter.scala:87:24] wire out_romask_100 = _out_romask_T_100; // @[RegisterRouter.scala:87:24] wire out_womask_100 = _out_womask_T_100; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_100 = out_rivalid_100 & out_rimask_100; // @[RegisterRouter.scala:87:24] wire _out_T_1111 = out_f_rivalid_100; // @[RegisterRouter.scala:87:24] wire out_f_roready_100 = out_roready_100 & out_romask_100; // @[RegisterRouter.scala:87:24] wire _out_T_1112 = out_f_roready_100; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_100 = out_wivalid_100 & out_wimask_100; // @[RegisterRouter.scala:87:24] wire out_f_woready_100 = out_woready_100 & out_womask_100; // @[RegisterRouter.scala:87:24] wire _out_T_1113 = ~out_rimask_100; // @[RegisterRouter.scala:87:24] wire _out_T_1114 = ~out_wimask_100; // @[RegisterRouter.scala:87:24] wire _out_T_1115 = ~out_romask_100; // @[RegisterRouter.scala:87:24] wire _out_T_1116 = ~out_womask_100; // @[RegisterRouter.scala:87:24] wire [22:0] out_prepend_78 = {1'h0, _out_prepend_T_78}; // @[RegisterRouter.scala:87:24] wire [22:0] _out_T_1117 = out_prepend_78; // @[RegisterRouter.scala:87:24] wire [22:0] _out_T_1118 = _out_T_1117; // @[RegisterRouter.scala:87:24] wire out_rimask_101 = \|_out_rimask_T_101; // @[RegisterRouter.scala:87:24] wire out_wimask_101 = &_out_wimask_T_101; // @[RegisterRouter.scala:87:24] wire out_romask_101 = \|_out_romask_T_101; // @[RegisterRouter.scala:87:24] wire out_womask_101 = &_out_womask_T_101; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_101 = out_rivalid_101 & out_rimask_101; // @[RegisterRouter.scala:87:24] wire _out_T_1120 = out_f_rivalid_101; // @[RegisterRouter.scala:87:24] assign out_f_roready_101 = out_roready_101 & out_romask_101; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_0 = out_f_roready_101; // @[RegisterRouter.scala:87:24] wire _out_T_1121 = out_f_roready_101; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_101 = out_wivalid_101 & out_wimask_101; // @[RegisterRouter.scala:87:24] wire _out_T_1122 = out_f_wivalid_101; // @[RegisterRouter.scala:87:24] assign out_f_woready_101 = out_woready_101 & out_womask_101; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_0 = out_f_woready_101; // @[RegisterRouter.scala:87:24] wire _out_T_1123 = out_f_woready_101; // @[RegisterRouter.scala:87:24] assign programBufferNxt_0 = out_f_woready_101 ? _out_T_1119 : programBufferMem_0; // @[RegisterRouter.scala:87:24] wire _out_T_1124 = ~out_rimask_101; // @[RegisterRouter.scala:87:24] wire _out_T_1125 = ~out_wimask_101; // @[RegisterRouter.scala:87:24] wire _out_T_1126 = ~out_romask_101; // @[RegisterRouter.scala:87:24] wire _out_T_1127 = ~out_womask_101; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1129 = _out_T_1128; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_79 = _out_T_1129; // @[RegisterRouter.scala:87:24] wire out_rimask_102 = \|_out_rimask_T_102; // @[RegisterRouter.scala:87:24] wire out_wimask_102 = &_out_wimask_T_102; // @[RegisterRouter.scala:87:24] wire out_romask_102 = \|_out_romask_T_102; // @[RegisterRouter.scala:87:24] wire out_womask_102 = &_out_womask_T_102; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_102 = out_rivalid_102 & out_rimask_102; // @[RegisterRouter.scala:87:24] wire _out_T_1131 = out_f_rivalid_102; // @[RegisterRouter.scala:87:24] assign out_f_roready_102 = out_roready_102 & out_romask_102; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_1 = out_f_roready_102; // @[RegisterRouter.scala:87:24] wire _out_T_1132 = out_f_roready_102; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_102 = out_wivalid_102 & out_wimask_102; // @[RegisterRouter.scala:87:24] wire _out_T_1133 = out_f_wivalid_102; // @[RegisterRouter.scala:87:24] assign out_f_woready_102 = out_woready_102 & out_womask_102; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_1 = out_f_woready_102; // @[RegisterRouter.scala:87:24] wire _out_T_1134 = out_f_woready_102; // @[RegisterRouter.scala:87:24] assign programBufferNxt_1 = out_f_woready_102 ? _out_T_1130 : programBufferMem_1; // @[RegisterRouter.scala:87:24] wire _out_T_1135 = ~out_rimask_102; // @[RegisterRouter.scala:87:24] wire _out_T_1136 = ~out_wimask_102; // @[RegisterRouter.scala:87:24] wire _out_T_1137 = ~out_romask_102; // @[RegisterRouter.scala:87:24] wire _out_T_1138 = ~out_womask_102; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_79 = {programBufferMem_1, _out_prepend_T_79}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1139 = out_prepend_79; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1140 = _out_T_1139; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_80 = _out_T_1140; // @[RegisterRouter.scala:87:24] wire out_rimask_103 = \|_out_rimask_T_103; // @[RegisterRouter.scala:87:24] wire out_wimask_103 = &_out_wimask_T_103; // @[RegisterRouter.scala:87:24] wire out_romask_103 = \|_out_romask_T_103; // @[RegisterRouter.scala:87:24] wire out_womask_103 = &_out_womask_T_103; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_103 = out_rivalid_103 & out_rimask_103; // @[RegisterRouter.scala:87:24] wire _out_T_1142 = out_f_rivalid_103; // @[RegisterRouter.scala:87:24] assign out_f_roready_103 = out_roready_103 & out_romask_103; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_2 = out_f_roready_103; // @[RegisterRouter.scala:87:24] wire _out_T_1143 = out_f_roready_103; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_103 = out_wivalid_103 & out_wimask_103; // @[RegisterRouter.scala:87:24] wire _out_T_1144 = out_f_wivalid_103; // @[RegisterRouter.scala:87:24] assign out_f_woready_103 = out_woready_103 & out_womask_103; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_2 = out_f_woready_103; // @[RegisterRouter.scala:87:24] wire _out_T_1145 = out_f_woready_103; // @[RegisterRouter.scala:87:24] assign programBufferNxt_2 = out_f_woready_103 ? _out_T_1141 : programBufferMem_2; // @[RegisterRouter.scala:87:24] wire _out_T_1146 = ~out_rimask_103; // @[RegisterRouter.scala:87:24] wire _out_T_1147 = ~out_wimask_103; // @[RegisterRouter.scala:87:24] wire _out_T_1148 = ~out_romask_103; // @[RegisterRouter.scala:87:24] wire _out_T_1149 = ~out_womask_103; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_80 = {programBufferMem_2, _out_prepend_T_80}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1150 = out_prepend_80; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1151 = _out_T_1150; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_81 = _out_T_1151; // @[RegisterRouter.scala:87:24] wire out_rimask_104 = \|_out_rimask_T_104; // @[RegisterRouter.scala:87:24] wire out_wimask_104 = &_out_wimask_T_104; // @[RegisterRouter.scala:87:24] wire out_romask_104 = \|_out_romask_T_104; // @[RegisterRouter.scala:87:24] wire out_womask_104 = &_out_womask_T_104; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_104 = out_rivalid_104 & out_rimask_104; // @[RegisterRouter.scala:87:24] wire _out_T_1153 = out_f_rivalid_104; // @[RegisterRouter.scala:87:24] assign out_f_roready_104 = out_roready_104 & out_romask_104; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_3 = out_f_roready_104; // @[RegisterRouter.scala:87:24] wire _out_T_1154 = out_f_roready_104; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_104 = out_wivalid_104 & out_wimask_104; // @[RegisterRouter.scala:87:24] wire _out_T_1155 = out_f_wivalid_104; // @[RegisterRouter.scala:87:24] assign out_f_woready_104 = out_woready_104 & out_womask_104; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_3 = out_f_woready_104; // @[RegisterRouter.scala:87:24] wire _out_T_1156 = out_f_woready_104; // @[RegisterRouter.scala:87:24] assign programBufferNxt_3 = out_f_woready_104 ? _out_T_1152 : programBufferMem_3; // @[RegisterRouter.scala:87:24] wire _out_T_1157 = ~out_rimask_104; // @[RegisterRouter.scala:87:24] wire _out_T_1158 = ~out_wimask_104; // @[RegisterRouter.scala:87:24] wire _out_T_1159 = ~out_romask_104; // @[RegisterRouter.scala:87:24] wire _out_T_1160 = ~out_womask_104; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_81 = {programBufferMem_3, _out_prepend_T_81}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1161 = out_prepend_81; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1162 = _out_T_1161; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_32 = _out_T_1162; // @[MuxLiteral.scala:49:48] wire out_rimask_105 = \|_out_rimask_T_105; // @[RegisterRouter.scala:87:24] wire out_wimask_105 = &_out_wimask_T_105; // @[RegisterRouter.scala:87:24] wire out_romask_105 = \|_out_romask_T_105; // @[RegisterRouter.scala:87:24] wire out_womask_105 = &_out_womask_T_105; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_105 = out_rivalid_105 & out_rimask_105; // @[RegisterRouter.scala:87:24] wire _out_T_1164 = out_f_rivalid_105; // @[RegisterRouter.scala:87:24] assign out_f_roready_105 = out_roready_105 & out_romask_105; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_8 = out_f_roready_105; // @[RegisterRouter.scala:87:24] wire _out_T_1165 = out_f_roready_105; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_105 = out_wivalid_105 & out_wimask_105; // @[RegisterRouter.scala:87:24] wire _out_T_1166 = out_f_wivalid_105; // @[RegisterRouter.scala:87:24] assign out_f_woready_105 = out_woready_105 & out_womask_105; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_8 = out_f_woready_105; // @[RegisterRouter.scala:87:24] wire _out_T_1167 = out_f_woready_105; // @[RegisterRouter.scala:87:24] assign programBufferNxt_8 = out_f_woready_105 ? _out_T_1163 : programBufferMem_8; // @[RegisterRouter.scala:87:24] wire _out_T_1168 = ~out_rimask_105; // @[RegisterRouter.scala:87:24] wire _out_T_1169 = ~out_wimask_105; // @[RegisterRouter.scala:87:24] wire _out_T_1170 = ~out_romask_105; // @[RegisterRouter.scala:87:24] wire _out_T_1171 = ~out_womask_105; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1173 = _out_T_1172; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_82 = _out_T_1173; // @[RegisterRouter.scala:87:24] wire out_rimask_106 = \|_out_rimask_T_106; // @[RegisterRouter.scala:87:24] wire out_wimask_106 = &_out_wimask_T_106; // @[RegisterRouter.scala:87:24] wire out_romask_106 = \|_out_romask_T_106; // @[RegisterRouter.scala:87:24] wire out_womask_106 = &_out_womask_T_106; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_106 = out_rivalid_106 & out_rimask_106; // @[RegisterRouter.scala:87:24] wire _out_T_1175 = out_f_rivalid_106; // @[RegisterRouter.scala:87:24] assign out_f_roready_106 = out_roready_106 & out_romask_106; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_9 = out_f_roready_106; // @[RegisterRouter.scala:87:24] wire _out_T_1176 = out_f_roready_106; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_106 = out_wivalid_106 & out_wimask_106; // @[RegisterRouter.scala:87:24] wire _out_T_1177 = out_f_wivalid_106; // @[RegisterRouter.scala:87:24] assign out_f_woready_106 = out_woready_106 & out_womask_106; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_9 = out_f_woready_106; // @[RegisterRouter.scala:87:24] wire _out_T_1178 = out_f_woready_106; // @[RegisterRouter.scala:87:24] assign programBufferNxt_9 = out_f_woready_106 ? _out_T_1174 : programBufferMem_9; // @[RegisterRouter.scala:87:24] wire _out_T_1179 = ~out_rimask_106; // @[RegisterRouter.scala:87:24] wire _out_T_1180 = ~out_wimask_106; // @[RegisterRouter.scala:87:24] wire _out_T_1181 = ~out_romask_106; // @[RegisterRouter.scala:87:24] wire _out_T_1182 = ~out_womask_106; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_82 = {programBufferMem_9, _out_prepend_T_82}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1183 = out_prepend_82; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1184 = _out_T_1183; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_83 = _out_T_1184; // @[RegisterRouter.scala:87:24] wire out_rimask_107 = \|_out_rimask_T_107; // @[RegisterRouter.scala:87:24] wire out_wimask_107 = &_out_wimask_T_107; // @[RegisterRouter.scala:87:24] wire out_romask_107 = \|_out_romask_T_107; // @[RegisterRouter.scala:87:24] wire out_womask_107 = &_out_womask_T_107; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_107 = out_rivalid_107 & out_rimask_107; // @[RegisterRouter.scala:87:24] wire _out_T_1186 = out_f_rivalid_107; // @[RegisterRouter.scala:87:24] assign out_f_roready_107 = out_roready_107 & out_romask_107; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_10 = out_f_roready_107; // @[RegisterRouter.scala:87:24] wire _out_T_1187 = out_f_roready_107; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_107 = out_wivalid_107 & out_wimask_107; // @[RegisterRouter.scala:87:24] wire _out_T_1188 = out_f_wivalid_107; // @[RegisterRouter.scala:87:24] assign out_f_woready_107 = out_woready_107 & out_womask_107; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_10 = out_f_woready_107; // @[RegisterRouter.scala:87:24] wire _out_T_1189 = out_f_woready_107; // @[RegisterRouter.scala:87:24] assign programBufferNxt_10 = out_f_woready_107 ? _out_T_1185 : programBufferMem_10; // @[RegisterRouter.scala:87:24] wire _out_T_1190 = ~out_rimask_107; // @[RegisterRouter.scala:87:24] wire _out_T_1191 = ~out_wimask_107; // @[RegisterRouter.scala:87:24] wire _out_T_1192 = ~out_romask_107; // @[RegisterRouter.scala:87:24] wire _out_T_1193 = ~out_womask_107; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_83 = {programBufferMem_10, _out_prepend_T_83}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1194 = out_prepend_83; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1195 = _out_T_1194; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_84 = _out_T_1195; // @[RegisterRouter.scala:87:24] wire out_rimask_108 = \|_out_rimask_T_108; // @[RegisterRouter.scala:87:24] wire out_wimask_108 = &_out_wimask_T_108; // @[RegisterRouter.scala:87:24] wire out_romask_108 = \|_out_romask_T_108; // @[RegisterRouter.scala:87:24] wire out_womask_108 = &_out_womask_T_108; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_108 = out_rivalid_108 & out_rimask_108; // @[RegisterRouter.scala:87:24] wire _out_T_1197 = out_f_rivalid_108; // @[RegisterRouter.scala:87:24] assign out_f_roready_108 = out_roready_108 & out_romask_108; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_11 = out_f_roready_108; // @[RegisterRouter.scala:87:24] wire _out_T_1198 = out_f_roready_108; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_108 = out_wivalid_108 & out_wimask_108; // @[RegisterRouter.scala:87:24] wire _out_T_1199 = out_f_wivalid_108; // @[RegisterRouter.scala:87:24] assign out_f_woready_108 = out_woready_108 & out_womask_108; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_11 = out_f_woready_108; // @[RegisterRouter.scala:87:24] wire _out_T_1200 = out_f_woready_108; // @[RegisterRouter.scala:87:24] assign programBufferNxt_11 = out_f_woready_108 ? _out_T_1196 : programBufferMem_11; // @[RegisterRouter.scala:87:24] wire _out_T_1201 = ~out_rimask_108; // @[RegisterRouter.scala:87:24] wire _out_T_1202 = ~out_wimask_108; // @[RegisterRouter.scala:87:24] wire _out_T_1203 = ~out_romask_108; // @[RegisterRouter.scala:87:24] wire _out_T_1204 = ~out_womask_108; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_84 = {programBufferMem_11, _out_prepend_T_84}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1205 = out_prepend_84; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1206 = _out_T_1205; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_34 = _out_T_1206; // @[MuxLiteral.scala:49:48] wire out_rimask_109 = \|_out_rimask_T_109; // @[RegisterRouter.scala:87:24] wire out_wimask_109 = &_out_wimask_T_109; // @[RegisterRouter.scala:87:24] wire out_romask_109 = \|_out_romask_T_109; // @[RegisterRouter.scala:87:24] wire out_womask_109 = &_out_womask_T_109; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_109 = out_rivalid_109 & out_rimask_109; // @[RegisterRouter.scala:87:24] wire _out_T_1208 = out_f_rivalid_109; // @[RegisterRouter.scala:87:24] wire out_f_roready_109 = out_roready_109 & out_romask_109; // @[RegisterRouter.scala:87:24] wire _out_T_1209 = out_f_roready_109; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_109 = out_wivalid_109 & out_wimask_109; // @[RegisterRouter.scala:87:24] wire out_f_woready_109 = out_woready_109 & out_womask_109; // @[RegisterRouter.scala:87:24] wire _out_T_1210 = ~out_rimask_109; // @[RegisterRouter.scala:87:24] wire _out_T_1211 = ~out_wimask_109; // @[RegisterRouter.scala:87:24] wire _out_T_1212 = ~out_romask_109; // @[RegisterRouter.scala:87:24] wire _out_T_1213 = ~out_womask_109; // @[RegisterRouter.scala:87:24] wire [3:0] _out_rimask_T_110 = out_frontMask[7:4]; // @[RegisterRouter.scala:87:24] wire [3:0] _out_wimask_T_110 = out_frontMask[7:4]; // @[RegisterRouter.scala:87:24] wire out_rimask_110 = \|_out_rimask_T_110; // @[RegisterRouter.scala:87:24] wire out_wimask_110 = &_out_wimask_T_110; // @[RegisterRouter.scala:87:24] wire [3:0] _out_romask_T_110 = out_backMask[7:4]; // @[RegisterRouter.scala:87:24] wire [3:0] _out_womask_T_110 = out_backMask[7:4]; // @[RegisterRouter.scala:87:24] wire out_romask_110 = \|_out_romask_T_110; // @[RegisterRouter.scala:87:24] wire out_womask_110 = &_out_womask_T_110; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_110 = out_rivalid_110 & out_rimask_110; // @[RegisterRouter.scala:87:24] wire _out_T_1217 = out_f_rivalid_110; // @[RegisterRouter.scala:87:24] wire out_f_roready_110 = out_roready_110 & out_romask_110; // @[RegisterRouter.scala:87:24] wire _out_T_1218 = out_f_roready_110; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_110 = out_wivalid_110 & out_wimask_110; // @[RegisterRouter.scala:87:24] wire out_f_woready_110 = out_woready_110 & out_womask_110; // @[RegisterRouter.scala:87:24] wire [3:0] _out_T_1216 = out_front_bits_data[7:4]; // @[RegisterRouter.scala:87:24] wire _out_T_1219 = ~out_rimask_110; // @[RegisterRouter.scala:87:24] wire _out_T_1220 = ~out_wimask_110; // @[RegisterRouter.scala:87:24] wire _out_T_1221 = ~out_romask_110; // @[RegisterRouter.scala:87:24] wire _out_T_1222 = ~out_womask_110; // @[RegisterRouter.scala:87:24] wire [2:0] _out_rimask_T_111 = out_frontMask[10:8]; // @[RegisterRouter.scala:87:24] wire [2:0] _out_wimask_T_111 = out_frontMask[10:8]; // @[RegisterRouter.scala:87:24] wire out_rimask_111 = \|_out_rimask_T_111; // @[RegisterRouter.scala:87:24] wire out_wimask_111 = &_out_wimask_T_111; // @[RegisterRouter.scala:87:24] wire [2:0] _out_romask_T_111 = out_backMask[10:8]; // @[RegisterRouter.scala:87:24] wire [2:0] _out_womask_T_111 = out_backMask[10:8]; // @[RegisterRouter.scala:87:24] wire out_romask_111 = \|_out_romask_T_111; // @[RegisterRouter.scala:87:24] wire out_womask_111 = &_out_womask_T_111; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_111 = out_rivalid_111 & out_rimask_111; // @[RegisterRouter.scala:87:24] wire _out_T_1226 = out_f_rivalid_111; // @[RegisterRouter.scala:87:24] wire out_f_roready_111 = out_roready_111 & out_romask_111; // @[RegisterRouter.scala:87:24] wire _out_T_1227 = out_f_roready_111; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_111 = out_wivalid_111 & out_wimask_111; // @[RegisterRouter.scala:87:24] wire _out_T_1228 = out_f_wivalid_111; // @[RegisterRouter.scala:87:24] assign out_f_woready_111 = out_woready_111 & out_womask_111; // @[RegisterRouter.scala:87:24] assign ABSTRACTCSWrEnMaybe = out_f_woready_111; // @[RegisterRouter.scala:87:24] wire _out_T_1229 = out_f_woready_111; // @[RegisterRouter.scala:87:24] assign _out_T_1225 = out_front_bits_data[10:8]; // @[RegisterRouter.scala:87:24] assign ABSTRACTCSWrData_cmderr = _out_T_1225; // @[RegisterRouter.scala:87:24] wire _out_T_1230 = ~out_rimask_111; // @[RegisterRouter.scala:87:24] wire _out_T_1231 = ~out_wimask_111; // @[RegisterRouter.scala:87:24] wire _out_T_1232 = ~out_romask_111; // @[RegisterRouter.scala:87:24] wire _out_T_1233 = ~out_womask_111; // @[RegisterRouter.scala:87:24] wire [10:0] out_prepend_86 = {ABSTRACTCSRdData_cmderr, 8'h8}; // @[RegisterRouter.scala:87:24] wire [10:0] _out_T_1234 = out_prepend_86; // @[RegisterRouter.scala:87:24] wire [10:0] _out_T_1235 = _out_T_1234; // @[RegisterRouter.scala:87:24] wire [10:0] _out_prepend_T_87 = _out_T_1235; // @[RegisterRouter.scala:87:24] wire out_rimask_112 = _out_rimask_T_112; // @[RegisterRouter.scala:87:24] wire out_wimask_112 = _out_wimask_T_112; // @[RegisterRouter.scala:87:24] wire out_romask_112 = _out_romask_T_112; // @[RegisterRouter.scala:87:24] wire out_womask_112 = _out_womask_T_112; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_112 = out_rivalid_112 & out_rimask_112; // @[RegisterRouter.scala:87:24] wire _out_T_1237 = out_f_rivalid_112; // @[RegisterRouter.scala:87:24] wire out_f_roready_112 = out_roready_112 & out_romask_112; // @[RegisterRouter.scala:87:24] wire _out_T_1238 = out_f_roready_112; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_112 = out_wivalid_112 & out_wimask_112; // @[RegisterRouter.scala:87:24] wire out_f_woready_112 = out_woready_112 & out_womask_112; // @[RegisterRouter.scala:87:24] wire _out_T_1239 = ~out_rimask_112; // @[RegisterRouter.scala:87:24] wire _out_T_1240 = ~out_wimask_112; // @[RegisterRouter.scala:87:24] wire _out_T_1241 = ~out_romask_112; // @[RegisterRouter.scala:87:24] wire _out_T_1242 = ~out_womask_112; // @[RegisterRouter.scala:87:24] wire [11:0] out_prepend_87 = {1'h0, _out_prepend_T_87}; // @[RegisterRouter.scala:87:24] wire [11:0] _out_T_1243 = out_prepend_87; // @[RegisterRouter.scala:87:24] wire [11:0] _out_T_1244 = _out_T_1243; // @[RegisterRouter.scala:87:24] wire [11:0] _out_prepend_T_88 = _out_T_1244; // @[RegisterRouter.scala:87:24] wire out_rimask_113 = _out_rimask_T_113; // @[RegisterRouter.scala:87:24] wire out_wimask_113 = _out_wimask_T_113; // @[RegisterRouter.scala:87:24] wire out_romask_113 = _out_romask_T_113; // @[RegisterRouter.scala:87:24] wire out_womask_113 = _out_womask_T_113; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_113 = out_rivalid_113 & out_rimask_113; // @[RegisterRouter.scala:87:24] wire _out_T_1246 = out_f_rivalid_113; // @[RegisterRouter.scala:87:24] wire out_f_roready_113 = out_roready_113 & out_romask_113; // @[RegisterRouter.scala:87:24] wire _out_T_1247 = out_f_roready_113; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_113 = out_wivalid_113 & out_wimask_113; // @[RegisterRouter.scala:87:24] wire out_f_woready_113 = out_woready_113 & out_womask_113; // @[RegisterRouter.scala:87:24] wire _out_T_1248 = ~out_rimask_113; // @[RegisterRouter.scala:87:24] wire _out_T_1249 = ~out_wimask_113; // @[RegisterRouter.scala:87:24] wire _out_T_1250 = ~out_romask_113; // @[RegisterRouter.scala:87:24] wire _out_T_1251 = ~out_womask_113; // @[RegisterRouter.scala:87:24] wire [12:0] out_prepend_88 = {ABSTRACTCSRdData_busy, _out_prepend_T_88}; // @[RegisterRouter.scala:87:24] wire [12:0] _out_T_1252 = out_prepend_88; // @[RegisterRouter.scala:87:24] wire [12:0] _out_T_1253 = _out_T_1252; // @[RegisterRouter.scala:87:24] wire [12:0] _out_prepend_T_89 = _out_T_1253; // @[RegisterRouter.scala:87:24] wire [10:0] _out_rimask_T_114 = out_frontMask[23:13]; // @[RegisterRouter.scala:87:24] wire [10:0] _out_wimask_T_114 = out_frontMask[23:13]; // @[RegisterRouter.scala:87:24] wire out_rimask_114 = \|_out_rimask_T_114; // @[RegisterRouter.scala:87:24] wire out_wimask_114 = &_out_wimask_T_114; // @[RegisterRouter.scala:87:24] wire [10:0] _out_romask_T_114 = out_backMask[23:13]; // @[RegisterRouter.scala:87:24] wire [10:0] _out_womask_T_114 = out_backMask[23:13]; // @[RegisterRouter.scala:87:24] wire out_romask_114 = \|_out_romask_T_114; // @[RegisterRouter.scala:87:24] wire out_womask_114 = &_out_womask_T_114; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_114 = out_rivalid_114 & out_rimask_114; // @[RegisterRouter.scala:87:24] wire _out_T_1255 = out_f_rivalid_114; // @[RegisterRouter.scala:87:24] wire out_f_roready_114 = out_roready_114 & out_romask_114; // @[RegisterRouter.scala:87:24] wire _out_T_1256 = out_f_roready_114; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_114 = out_wivalid_114 & out_wimask_114; // @[RegisterRouter.scala:87:24] wire out_f_woready_114 = out_woready_114 & out_womask_114; // @[RegisterRouter.scala:87:24] wire [10:0] _out_T_1254 = out_front_bits_data[23:13]; // @[RegisterRouter.scala:87:24] wire _out_T_1257 = ~out_rimask_114; // @[RegisterRouter.scala:87:24] wire _out_T_1258 = ~out_wimask_114; // @[RegisterRouter.scala:87:24] wire _out_T_1259 = ~out_romask_114; // @[RegisterRouter.scala:87:24] wire _out_T_1260 = ~out_womask_114; // @[RegisterRouter.scala:87:24] wire [13:0] out_prepend_89 = {1'h0, _out_prepend_T_89}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1261 = {10'h0, out_prepend_89}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1262 = _out_T_1261; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_90 = _out_T_1262; // @[RegisterRouter.scala:87:24] wire [4:0] _out_rimask_T_115 = out_frontMask[28:24]; // @[RegisterRouter.scala:87:24] wire [4:0] _out_wimask_T_115 = out_frontMask[28:24]; // @[RegisterRouter.scala:87:24] wire out_rimask_115 = \|_out_rimask_T_115; // @[RegisterRouter.scala:87:24] wire out_wimask_115 = &_out_wimask_T_115; // @[RegisterRouter.scala:87:24] wire [4:0] _out_romask_T_115 = out_backMask[28:24]; // @[RegisterRouter.scala:87:24] wire [4:0] _out_womask_T_115 = out_backMask[28:24]; // @[RegisterRouter.scala:87:24] wire out_romask_115 = \|_out_romask_T_115; // @[RegisterRouter.scala:87:24] wire out_womask_115 = &_out_womask_T_115; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_115 = out_rivalid_115 & out_rimask_115; // @[RegisterRouter.scala:87:24] wire _out_T_1264 = out_f_rivalid_115; // @[RegisterRouter.scala:87:24] wire out_f_roready_115 = out_roready_115 & out_romask_115; // @[RegisterRouter.scala:87:24] wire _out_T_1265 = out_f_roready_115; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_115 = out_wivalid_115 & out_wimask_115; // @[RegisterRouter.scala:87:24] wire out_f_woready_115 = out_woready_115 & out_womask_115; // @[RegisterRouter.scala:87:24] wire [4:0] _out_T_1263 = out_front_bits_data[28:24]; // @[RegisterRouter.scala:87:24] wire _out_T_1266 = ~out_rimask_115; // @[RegisterRouter.scala:87:24] wire _out_T_1267 = ~out_wimask_115; // @[RegisterRouter.scala:87:24] wire _out_T_1268 = ~out_romask_115; // @[RegisterRouter.scala:87:24] wire _out_T_1269 = ~out_womask_115; // @[RegisterRouter.scala:87:24] wire [28:0] out_prepend_90 = {5'h10, _out_prepend_T_90}; // @[RegisterRouter.scala:87:24] wire [28:0] _out_T_1270 = out_prepend_90; // @[RegisterRouter.scala:87:24] wire [28:0] _out_T_1271 = _out_T_1270; // @[RegisterRouter.scala:87:24] wire out_rimask_116 = \|_out_rimask_T_116; // @[RegisterRouter.scala:87:24] wire out_wimask_116 = &_out_wimask_T_116; // @[RegisterRouter.scala:87:24] wire out_romask_116 = \|_out_romask_T_116; // @[RegisterRouter.scala:87:24] wire out_womask_116 = &_out_womask_T_116; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_116 = out_rivalid_116 & out_rimask_116; // @[RegisterRouter.scala:87:24] wire _out_T_1273 = out_f_rivalid_116; // @[RegisterRouter.scala:87:24] assign out_f_roready_116 = out_roready_116 & out_romask_116; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_48 = out_f_roready_116; // @[RegisterRouter.scala:87:24] wire _out_T_1274 = out_f_roready_116; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_116 = out_wivalid_116 & out_wimask_116; // @[RegisterRouter.scala:87:24] wire _out_T_1275 = out_f_wivalid_116; // @[RegisterRouter.scala:87:24] assign out_f_woready_116 = out_woready_116 & out_womask_116; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_48 = out_f_woready_116; // @[RegisterRouter.scala:87:24] wire _out_T_1276 = out_f_woready_116; // @[RegisterRouter.scala:87:24] assign programBufferNxt_48 = out_f_woready_116 ? _out_T_1272 : programBufferMem_48; // @[RegisterRouter.scala:87:24] wire _out_T_1277 = ~out_rimask_116; // @[RegisterRouter.scala:87:24] wire _out_T_1278 = ~out_wimask_116; // @[RegisterRouter.scala:87:24] wire _out_T_1279 = ~out_romask_116; // @[RegisterRouter.scala:87:24] wire _out_T_1280 = ~out_womask_116; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1282 = _out_T_1281; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_91 = _out_T_1282; // @[RegisterRouter.scala:87:24] wire out_rimask_117 = \|_out_rimask_T_117; // @[RegisterRouter.scala:87:24] wire out_wimask_117 = &_out_wimask_T_117; // @[RegisterRouter.scala:87:24] wire out_romask_117 = \|_out_romask_T_117; // @[RegisterRouter.scala:87:24] wire out_womask_117 = &_out_womask_T_117; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_117 = out_rivalid_117 & out_rimask_117; // @[RegisterRouter.scala:87:24] wire _out_T_1284 = out_f_rivalid_117; // @[RegisterRouter.scala:87:24] assign out_f_roready_117 = out_roready_117 & out_romask_117; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_49 = out_f_roready_117; // @[RegisterRouter.scala:87:24] wire _out_T_1285 = out_f_roready_117; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_117 = out_wivalid_117 & out_wimask_117; // @[RegisterRouter.scala:87:24] wire _out_T_1286 = out_f_wivalid_117; // @[RegisterRouter.scala:87:24] assign out_f_woready_117 = out_woready_117 & out_womask_117; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_49 = out_f_woready_117; // @[RegisterRouter.scala:87:24] wire _out_T_1287 = out_f_woready_117; // @[RegisterRouter.scala:87:24] assign programBufferNxt_49 = out_f_woready_117 ? _out_T_1283 : programBufferMem_49; // @[RegisterRouter.scala:87:24] wire _out_T_1288 = ~out_rimask_117; // @[RegisterRouter.scala:87:24] wire _out_T_1289 = ~out_wimask_117; // @[RegisterRouter.scala:87:24] wire _out_T_1290 = ~out_romask_117; // @[RegisterRouter.scala:87:24] wire _out_T_1291 = ~out_womask_117; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_91 = {programBufferMem_49, _out_prepend_T_91}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1292 = out_prepend_91; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1293 = _out_T_1292; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_92 = _out_T_1293; // @[RegisterRouter.scala:87:24] wire out_rimask_118 = \|_out_rimask_T_118; // @[RegisterRouter.scala:87:24] wire out_wimask_118 = &_out_wimask_T_118; // @[RegisterRouter.scala:87:24] wire out_romask_118 = \|_out_romask_T_118; // @[RegisterRouter.scala:87:24] wire out_womask_118 = &_out_womask_T_118; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_118 = out_rivalid_118 & out_rimask_118; // @[RegisterRouter.scala:87:24] wire _out_T_1295 = out_f_rivalid_118; // @[RegisterRouter.scala:87:24] assign out_f_roready_118 = out_roready_118 & out_romask_118; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_50 = out_f_roready_118; // @[RegisterRouter.scala:87:24] wire _out_T_1296 = out_f_roready_118; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_118 = out_wivalid_118 & out_wimask_118; // @[RegisterRouter.scala:87:24] wire _out_T_1297 = out_f_wivalid_118; // @[RegisterRouter.scala:87:24] assign out_f_woready_118 = out_woready_118 & out_womask_118; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_50 = out_f_woready_118; // @[RegisterRouter.scala:87:24] wire _out_T_1298 = out_f_woready_118; // @[RegisterRouter.scala:87:24] assign programBufferNxt_50 = out_f_woready_118 ? _out_T_1294 : programBufferMem_50; // @[RegisterRouter.scala:87:24] wire _out_T_1299 = ~out_rimask_118; // @[RegisterRouter.scala:87:24] wire _out_T_1300 = ~out_wimask_118; // @[RegisterRouter.scala:87:24] wire _out_T_1301 = ~out_romask_118; // @[RegisterRouter.scala:87:24] wire _out_T_1302 = ~out_womask_118; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_92 = {programBufferMem_50, _out_prepend_T_92}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1303 = out_prepend_92; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1304 = _out_T_1303; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_93 = _out_T_1304; // @[RegisterRouter.scala:87:24] wire out_rimask_119 = \|_out_rimask_T_119; // @[RegisterRouter.scala:87:24] wire out_wimask_119 = &_out_wimask_T_119; // @[RegisterRouter.scala:87:24] wire out_romask_119 = \|_out_romask_T_119; // @[RegisterRouter.scala:87:24] wire out_womask_119 = &_out_womask_T_119; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_119 = out_rivalid_119 & out_rimask_119; // @[RegisterRouter.scala:87:24] wire _out_T_1306 = out_f_rivalid_119; // @[RegisterRouter.scala:87:24] assign out_f_roready_119 = out_roready_119 & out_romask_119; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_51 = out_f_roready_119; // @[RegisterRouter.scala:87:24] wire _out_T_1307 = out_f_roready_119; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_119 = out_wivalid_119 & out_wimask_119; // @[RegisterRouter.scala:87:24] wire _out_T_1308 = out_f_wivalid_119; // @[RegisterRouter.scala:87:24] assign out_f_woready_119 = out_woready_119 & out_womask_119; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_51 = out_f_woready_119; // @[RegisterRouter.scala:87:24] wire _out_T_1309 = out_f_woready_119; // @[RegisterRouter.scala:87:24] assign programBufferNxt_51 = out_f_woready_119 ? _out_T_1305 : programBufferMem_51; // @[RegisterRouter.scala:87:24] wire _out_T_1310 = ~out_rimask_119; // @[RegisterRouter.scala:87:24] wire _out_T_1311 = ~out_wimask_119; // @[RegisterRouter.scala:87:24] wire _out_T_1312 = ~out_romask_119; // @[RegisterRouter.scala:87:24] wire _out_T_1313 = ~out_womask_119; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_93 = {programBufferMem_51, _out_prepend_T_93}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1314 = out_prepend_93; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1315 = _out_T_1314; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_44 = _out_T_1315; // @[MuxLiteral.scala:49:48] wire out_rimask_120 = \|_out_rimask_T_120; // @[RegisterRouter.scala:87:24] wire out_wimask_120 = &_out_wimask_T_120; // @[RegisterRouter.scala:87:24] wire out_romask_120 = \|_out_romask_T_120; // @[RegisterRouter.scala:87:24] wire out_womask_120 = &_out_womask_T_120; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_120 = out_rivalid_120 & out_rimask_120; // @[RegisterRouter.scala:87:24] wire _out_T_1317 = out_f_rivalid_120; // @[RegisterRouter.scala:87:24] assign out_f_roready_120 = out_roready_120 & out_romask_120; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_12 = out_f_roready_120; // @[RegisterRouter.scala:87:24] wire _out_T_1318 = out_f_roready_120; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_120 = out_wivalid_120 & out_wimask_120; // @[RegisterRouter.scala:87:24] wire _out_T_1319 = out_f_wivalid_120; // @[RegisterRouter.scala:87:24] assign out_f_woready_120 = out_woready_120 & out_womask_120; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_12 = out_f_woready_120; // @[RegisterRouter.scala:87:24] wire _out_T_1320 = out_f_woready_120; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_12 = out_f_woready_120 ? _out_T_1316 : abstractDataMem_12; // @[RegisterRouter.scala:87:24] wire _out_T_1321 = ~out_rimask_120; // @[RegisterRouter.scala:87:24] wire _out_T_1322 = ~out_wimask_120; // @[RegisterRouter.scala:87:24] wire _out_T_1323 = ~out_romask_120; // @[RegisterRouter.scala:87:24] wire _out_T_1324 = ~out_womask_120; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1326 = _out_T_1325; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_94 = _out_T_1326; // @[RegisterRouter.scala:87:24] wire out_rimask_121 = \|_out_rimask_T_121; // @[RegisterRouter.scala:87:24] wire out_wimask_121 = &_out_wimask_T_121; // @[RegisterRouter.scala:87:24] wire out_romask_121 = \|_out_romask_T_121; // @[RegisterRouter.scala:87:24] wire out_womask_121 = &_out_womask_T_121; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_121 = out_rivalid_121 & out_rimask_121; // @[RegisterRouter.scala:87:24] wire _out_T_1328 = out_f_rivalid_121; // @[RegisterRouter.scala:87:24] assign out_f_roready_121 = out_roready_121 & out_romask_121; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_13 = out_f_roready_121; // @[RegisterRouter.scala:87:24] wire _out_T_1329 = out_f_roready_121; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_121 = out_wivalid_121 & out_wimask_121; // @[RegisterRouter.scala:87:24] wire _out_T_1330 = out_f_wivalid_121; // @[RegisterRouter.scala:87:24] assign out_f_woready_121 = out_woready_121 & out_womask_121; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_13 = out_f_woready_121; // @[RegisterRouter.scala:87:24] wire _out_T_1331 = out_f_woready_121; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_13 = out_f_woready_121 ? _out_T_1327 : abstractDataMem_13; // @[RegisterRouter.scala:87:24] wire _out_T_1332 = ~out_rimask_121; // @[RegisterRouter.scala:87:24] wire _out_T_1333 = ~out_wimask_121; // @[RegisterRouter.scala:87:24] wire _out_T_1334 = ~out_romask_121; // @[RegisterRouter.scala:87:24] wire _out_T_1335 = ~out_womask_121; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_94 = {abstractDataMem_13, _out_prepend_T_94}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1336 = out_prepend_94; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1337 = _out_T_1336; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_95 = _out_T_1337; // @[RegisterRouter.scala:87:24] wire out_rimask_122 = \|_out_rimask_T_122; // @[RegisterRouter.scala:87:24] wire out_wimask_122 = &_out_wimask_T_122; // @[RegisterRouter.scala:87:24] wire out_romask_122 = \|_out_romask_T_122; // @[RegisterRouter.scala:87:24] wire out_womask_122 = &_out_womask_T_122; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_122 = out_rivalid_122 & out_rimask_122; // @[RegisterRouter.scala:87:24] wire _out_T_1339 = out_f_rivalid_122; // @[RegisterRouter.scala:87:24] assign out_f_roready_122 = out_roready_122 & out_romask_122; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_14 = out_f_roready_122; // @[RegisterRouter.scala:87:24] wire _out_T_1340 = out_f_roready_122; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_122 = out_wivalid_122 & out_wimask_122; // @[RegisterRouter.scala:87:24] wire _out_T_1341 = out_f_wivalid_122; // @[RegisterRouter.scala:87:24] assign out_f_woready_122 = out_woready_122 & out_womask_122; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_14 = out_f_woready_122; // @[RegisterRouter.scala:87:24] wire _out_T_1342 = out_f_woready_122; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_14 = out_f_woready_122 ? _out_T_1338 : abstractDataMem_14; // @[RegisterRouter.scala:87:24] wire _out_T_1343 = ~out_rimask_122; // @[RegisterRouter.scala:87:24] wire _out_T_1344 = ~out_wimask_122; // @[RegisterRouter.scala:87:24] wire _out_T_1345 = ~out_romask_122; // @[RegisterRouter.scala:87:24] wire _out_T_1346 = ~out_womask_122; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_95 = {abstractDataMem_14, _out_prepend_T_95}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1347 = out_prepend_95; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1348 = _out_T_1347; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_96 = _out_T_1348; // @[RegisterRouter.scala:87:24] wire out_rimask_123 = \|_out_rimask_T_123; // @[RegisterRouter.scala:87:24] wire out_wimask_123 = &_out_wimask_T_123; // @[RegisterRouter.scala:87:24] wire out_romask_123 = \|_out_romask_T_123; // @[RegisterRouter.scala:87:24] wire out_womask_123 = &_out_womask_T_123; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_123 = out_rivalid_123 & out_rimask_123; // @[RegisterRouter.scala:87:24] wire _out_T_1350 = out_f_rivalid_123; // @[RegisterRouter.scala:87:24] assign out_f_roready_123 = out_roready_123 & out_romask_123; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_15 = out_f_roready_123; // @[RegisterRouter.scala:87:24] wire _out_T_1351 = out_f_roready_123; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_123 = out_wivalid_123 & out_wimask_123; // @[RegisterRouter.scala:87:24] wire _out_T_1352 = out_f_wivalid_123; // @[RegisterRouter.scala:87:24] assign out_f_woready_123 = out_woready_123 & out_womask_123; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_15 = out_f_woready_123; // @[RegisterRouter.scala:87:24] wire _out_T_1353 = out_f_woready_123; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_15 = out_f_woready_123 ? _out_T_1349 : abstractDataMem_15; // @[RegisterRouter.scala:87:24] wire _out_T_1354 = ~out_rimask_123; // @[RegisterRouter.scala:87:24] wire _out_T_1355 = ~out_wimask_123; // @[RegisterRouter.scala:87:24] wire _out_T_1356 = ~out_romask_123; // @[RegisterRouter.scala:87:24] wire _out_T_1357 = ~out_womask_123; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_96 = {abstractDataMem_15, _out_prepend_T_96}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1358 = out_prepend_96; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1359 = _out_T_1358; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_7 = _out_T_1359; // @[MuxLiteral.scala:49:48] wire out_rimask_124 = \|_out_rimask_T_124; // @[RegisterRouter.scala:87:24] wire out_wimask_124 = &_out_wimask_T_124; // @[RegisterRouter.scala:87:24] wire out_romask_124 = \|_out_romask_T_124; // @[RegisterRouter.scala:87:24] wire out_womask_124 = &_out_womask_T_124; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_124 = out_rivalid_124 & out_rimask_124; // @[RegisterRouter.scala:87:24] wire _out_T_1361 = out_f_rivalid_124; // @[RegisterRouter.scala:87:24] assign out_f_roready_124 = out_roready_124 & out_romask_124; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_28 = out_f_roready_124; // @[RegisterRouter.scala:87:24] wire _out_T_1362 = out_f_roready_124; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_124 = out_wivalid_124 & out_wimask_124; // @[RegisterRouter.scala:87:24] wire _out_T_1363 = out_f_wivalid_124; // @[RegisterRouter.scala:87:24] assign out_f_woready_124 = out_woready_124 & out_womask_124; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_28 = out_f_woready_124; // @[RegisterRouter.scala:87:24] wire _out_T_1364 = out_f_woready_124; // @[RegisterRouter.scala:87:24] assign programBufferNxt_28 = out_f_woready_124 ? _out_T_1360 : programBufferMem_28; // @[RegisterRouter.scala:87:24] wire _out_T_1365 = ~out_rimask_124; // @[RegisterRouter.scala:87:24] wire _out_T_1366 = ~out_wimask_124; // @[RegisterRouter.scala:87:24] wire _out_T_1367 = ~out_romask_124; // @[RegisterRouter.scala:87:24] wire _out_T_1368 = ~out_womask_124; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1370 = _out_T_1369; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_97 = _out_T_1370; // @[RegisterRouter.scala:87:24] wire out_rimask_125 = \|_out_rimask_T_125; // @[RegisterRouter.scala:87:24] wire out_wimask_125 = &_out_wimask_T_125; // @[RegisterRouter.scala:87:24] wire out_romask_125 = \|_out_romask_T_125; // @[RegisterRouter.scala:87:24] wire out_womask_125 = &_out_womask_T_125; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_125 = out_rivalid_125 & out_rimask_125; // @[RegisterRouter.scala:87:24] wire _out_T_1372 = out_f_rivalid_125; // @[RegisterRouter.scala:87:24] assign out_f_roready_125 = out_roready_125 & out_romask_125; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_29 = out_f_roready_125; // @[RegisterRouter.scala:87:24] wire _out_T_1373 = out_f_roready_125; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_125 = out_wivalid_125 & out_wimask_125; // @[RegisterRouter.scala:87:24] wire _out_T_1374 = out_f_wivalid_125; // @[RegisterRouter.scala:87:24] assign out_f_woready_125 = out_woready_125 & out_womask_125; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_29 = out_f_woready_125; // @[RegisterRouter.scala:87:24] wire _out_T_1375 = out_f_woready_125; // @[RegisterRouter.scala:87:24] assign programBufferNxt_29 = out_f_woready_125 ? _out_T_1371 : programBufferMem_29; // @[RegisterRouter.scala:87:24] wire _out_T_1376 = ~out_rimask_125; // @[RegisterRouter.scala:87:24] wire _out_T_1377 = ~out_wimask_125; // @[RegisterRouter.scala:87:24] wire _out_T_1378 = ~out_romask_125; // @[RegisterRouter.scala:87:24] wire _out_T_1379 = ~out_womask_125; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_97 = {programBufferMem_29, _out_prepend_T_97}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1380 = out_prepend_97; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1381 = _out_T_1380; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_98 = _out_T_1381; // @[RegisterRouter.scala:87:24] wire out_rimask_126 = \|_out_rimask_T_126; // @[RegisterRouter.scala:87:24] wire out_wimask_126 = &_out_wimask_T_126; // @[RegisterRouter.scala:87:24] wire out_romask_126 = \|_out_romask_T_126; // @[RegisterRouter.scala:87:24] wire out_womask_126 = &_out_womask_T_126; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_126 = out_rivalid_126 & out_rimask_126; // @[RegisterRouter.scala:87:24] wire _out_T_1383 = out_f_rivalid_126; // @[RegisterRouter.scala:87:24] assign out_f_roready_126 = out_roready_126 & out_romask_126; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_30 = out_f_roready_126; // @[RegisterRouter.scala:87:24] wire _out_T_1384 = out_f_roready_126; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_126 = out_wivalid_126 & out_wimask_126; // @[RegisterRouter.scala:87:24] wire _out_T_1385 = out_f_wivalid_126; // @[RegisterRouter.scala:87:24] assign out_f_woready_126 = out_woready_126 & out_womask_126; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_30 = out_f_woready_126; // @[RegisterRouter.scala:87:24] wire _out_T_1386 = out_f_woready_126; // @[RegisterRouter.scala:87:24] assign programBufferNxt_30 = out_f_woready_126 ? _out_T_1382 : programBufferMem_30; // @[RegisterRouter.scala:87:24] wire _out_T_1387 = ~out_rimask_126; // @[RegisterRouter.scala:87:24] wire _out_T_1388 = ~out_wimask_126; // @[RegisterRouter.scala:87:24] wire _out_T_1389 = ~out_romask_126; // @[RegisterRouter.scala:87:24] wire _out_T_1390 = ~out_womask_126; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_98 = {programBufferMem_30, _out_prepend_T_98}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1391 = out_prepend_98; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1392 = _out_T_1391; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_99 = _out_T_1392; // @[RegisterRouter.scala:87:24] wire out_rimask_127 = \|_out_rimask_T_127; // @[RegisterRouter.scala:87:24] wire out_wimask_127 = &_out_wimask_T_127; // @[RegisterRouter.scala:87:24] wire out_romask_127 = \|_out_romask_T_127; // @[RegisterRouter.scala:87:24] wire out_womask_127 = &_out_womask_T_127; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_127 = out_rivalid_127 & out_rimask_127; // @[RegisterRouter.scala:87:24] wire _out_T_1394 = out_f_rivalid_127; // @[RegisterRouter.scala:87:24] assign out_f_roready_127 = out_roready_127 & out_romask_127; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_31 = out_f_roready_127; // @[RegisterRouter.scala:87:24] wire _out_T_1395 = out_f_roready_127; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_127 = out_wivalid_127 & out_wimask_127; // @[RegisterRouter.scala:87:24] wire _out_T_1396 = out_f_wivalid_127; // @[RegisterRouter.scala:87:24] assign out_f_woready_127 = out_woready_127 & out_womask_127; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_31 = out_f_woready_127; // @[RegisterRouter.scala:87:24] wire _out_T_1397 = out_f_woready_127; // @[RegisterRouter.scala:87:24] assign programBufferNxt_31 = out_f_woready_127 ? _out_T_1393 : programBufferMem_31; // @[RegisterRouter.scala:87:24] wire _out_T_1398 = ~out_rimask_127; // @[RegisterRouter.scala:87:24] wire _out_T_1399 = ~out_wimask_127; // @[RegisterRouter.scala:87:24] wire _out_T_1400 = ~out_romask_127; // @[RegisterRouter.scala:87:24] wire _out_T_1401 = ~out_womask_127; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_99 = {programBufferMem_31, _out_prepend_T_99}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1402 = out_prepend_99; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1403 = _out_T_1402; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_39 = _out_T_1403; // @[MuxLiteral.scala:49:48] wire out_rimask_128 = \|_out_rimask_T_128; // @[RegisterRouter.scala:87:24] wire out_wimask_128 = &_out_wimask_T_128; // @[RegisterRouter.scala:87:24] wire out_romask_128 = \|_out_romask_T_128; // @[RegisterRouter.scala:87:24] wire out_womask_128 = &_out_womask_T_128; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_128 = out_rivalid_128 & out_rimask_128; // @[RegisterRouter.scala:87:24] wire _out_T_1405 = out_f_rivalid_128; // @[RegisterRouter.scala:87:24] assign out_f_roready_128 = out_roready_128 & out_romask_128; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_28 = out_f_roready_128; // @[RegisterRouter.scala:87:24] wire _out_T_1406 = out_f_roready_128; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_128 = out_wivalid_128 & out_wimask_128; // @[RegisterRouter.scala:87:24] wire _out_T_1407 = out_f_wivalid_128; // @[RegisterRouter.scala:87:24] assign out_f_woready_128 = out_woready_128 & out_womask_128; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_28 = out_f_woready_128; // @[RegisterRouter.scala:87:24] wire _out_T_1408 = out_f_woready_128; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_28 = out_f_woready_128 ? _out_T_1404 : abstractDataMem_28; // @[RegisterRouter.scala:87:24] wire _out_T_1409 = ~out_rimask_128; // @[RegisterRouter.scala:87:24] wire _out_T_1410 = ~out_wimask_128; // @[RegisterRouter.scala:87:24] wire _out_T_1411 = ~out_romask_128; // @[RegisterRouter.scala:87:24] wire _out_T_1412 = ~out_womask_128; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1414 = _out_T_1413; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_100 = _out_T_1414; // @[RegisterRouter.scala:87:24] wire out_rimask_129 = \|_out_rimask_T_129; // @[RegisterRouter.scala:87:24] wire out_wimask_129 = &_out_wimask_T_129; // @[RegisterRouter.scala:87:24] wire out_romask_129 = \|_out_romask_T_129; // @[RegisterRouter.scala:87:24] wire out_womask_129 = &_out_womask_T_129; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_129 = out_rivalid_129 & out_rimask_129; // @[RegisterRouter.scala:87:24] wire _out_T_1416 = out_f_rivalid_129; // @[RegisterRouter.scala:87:24] assign out_f_roready_129 = out_roready_129 & out_romask_129; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_29 = out_f_roready_129; // @[RegisterRouter.scala:87:24] wire _out_T_1417 = out_f_roready_129; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_129 = out_wivalid_129 & out_wimask_129; // @[RegisterRouter.scala:87:24] wire _out_T_1418 = out_f_wivalid_129; // @[RegisterRouter.scala:87:24] assign out_f_woready_129 = out_woready_129 & out_womask_129; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_29 = out_f_woready_129; // @[RegisterRouter.scala:87:24] wire _out_T_1419 = out_f_woready_129; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_29 = out_f_woready_129 ? _out_T_1415 : abstractDataMem_29; // @[RegisterRouter.scala:87:24] wire _out_T_1420 = ~out_rimask_129; // @[RegisterRouter.scala:87:24] wire _out_T_1421 = ~out_wimask_129; // @[RegisterRouter.scala:87:24] wire _out_T_1422 = ~out_romask_129; // @[RegisterRouter.scala:87:24] wire _out_T_1423 = ~out_womask_129; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_100 = {abstractDataMem_29, _out_prepend_T_100}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1424 = out_prepend_100; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1425 = _out_T_1424; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_101 = _out_T_1425; // @[RegisterRouter.scala:87:24] wire out_rimask_130 = \|_out_rimask_T_130; // @[RegisterRouter.scala:87:24] wire out_wimask_130 = &_out_wimask_T_130; // @[RegisterRouter.scala:87:24] wire out_romask_130 = \|_out_romask_T_130; // @[RegisterRouter.scala:87:24] wire out_womask_130 = &_out_womask_T_130; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_130 = out_rivalid_130 & out_rimask_130; // @[RegisterRouter.scala:87:24] wire _out_T_1427 = out_f_rivalid_130; // @[RegisterRouter.scala:87:24] assign out_f_roready_130 = out_roready_130 & out_romask_130; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_30 = out_f_roready_130; // @[RegisterRouter.scala:87:24] wire _out_T_1428 = out_f_roready_130; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_130 = out_wivalid_130 & out_wimask_130; // @[RegisterRouter.scala:87:24] wire _out_T_1429 = out_f_wivalid_130; // @[RegisterRouter.scala:87:24] assign out_f_woready_130 = out_woready_130 & out_womask_130; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_30 = out_f_woready_130; // @[RegisterRouter.scala:87:24] wire _out_T_1430 = out_f_woready_130; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_30 = out_f_woready_130 ? _out_T_1426 : abstractDataMem_30; // @[RegisterRouter.scala:87:24] wire _out_T_1431 = ~out_rimask_130; // @[RegisterRouter.scala:87:24] wire _out_T_1432 = ~out_wimask_130; // @[RegisterRouter.scala:87:24] wire _out_T_1433 = ~out_romask_130; // @[RegisterRouter.scala:87:24] wire _out_T_1434 = ~out_womask_130; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_101 = {abstractDataMem_30, _out_prepend_T_101}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1435 = out_prepend_101; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1436 = _out_T_1435; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_102 = _out_T_1436; // @[RegisterRouter.scala:87:24] wire out_rimask_131 = \|_out_rimask_T_131; // @[RegisterRouter.scala:87:24] wire out_wimask_131 = &_out_wimask_T_131; // @[RegisterRouter.scala:87:24] wire out_romask_131 = \|_out_romask_T_131; // @[RegisterRouter.scala:87:24] wire out_womask_131 = &_out_womask_T_131; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_131 = out_rivalid_131 & out_rimask_131; // @[RegisterRouter.scala:87:24] wire _out_T_1438 = out_f_rivalid_131; // @[RegisterRouter.scala:87:24] assign out_f_roready_131 = out_roready_131 & out_romask_131; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_31 = out_f_roready_131; // @[RegisterRouter.scala:87:24] wire _out_T_1439 = out_f_roready_131; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_131 = out_wivalid_131 & out_wimask_131; // @[RegisterRouter.scala:87:24] wire _out_T_1440 = out_f_wivalid_131; // @[RegisterRouter.scala:87:24] assign out_f_woready_131 = out_woready_131 & out_womask_131; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_31 = out_f_woready_131; // @[RegisterRouter.scala:87:24] wire _out_T_1441 = out_f_woready_131; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_31 = out_f_woready_131 ? _out_T_1437 : abstractDataMem_31; // @[RegisterRouter.scala:87:24] wire _out_T_1442 = ~out_rimask_131; // @[RegisterRouter.scala:87:24] wire _out_T_1443 = ~out_wimask_131; // @[RegisterRouter.scala:87:24] wire _out_T_1444 = ~out_romask_131; // @[RegisterRouter.scala:87:24] wire _out_T_1445 = ~out_womask_131; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_102 = {abstractDataMem_31, _out_prepend_T_102}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1446 = out_prepend_102; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1447 = _out_T_1446; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_11 = _out_T_1447; // @[MuxLiteral.scala:49:48] wire out_rimask_132 = \|_out_rimask_T_132; // @[RegisterRouter.scala:87:24] wire out_wimask_132 = &_out_wimask_T_132; // @[RegisterRouter.scala:87:24] wire out_romask_132 = \|_out_romask_T_132; // @[RegisterRouter.scala:87:24] wire out_womask_132 = &_out_womask_T_132; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_132 = out_rivalid_132 & out_rimask_132; // @[RegisterRouter.scala:87:24] wire _out_T_1449 = out_f_rivalid_132; // @[RegisterRouter.scala:87:24] assign out_f_roready_132 = out_roready_132 & out_romask_132; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_44 = out_f_roready_132; // @[RegisterRouter.scala:87:24] wire _out_T_1450 = out_f_roready_132; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_132 = out_wivalid_132 & out_wimask_132; // @[RegisterRouter.scala:87:24] wire _out_T_1451 = out_f_wivalid_132; // @[RegisterRouter.scala:87:24] assign out_f_woready_132 = out_woready_132 & out_womask_132; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_44 = out_f_woready_132; // @[RegisterRouter.scala:87:24] wire _out_T_1452 = out_f_woready_132; // @[RegisterRouter.scala:87:24] assign programBufferNxt_44 = out_f_woready_132 ? _out_T_1448 : programBufferMem_44; // @[RegisterRouter.scala:87:24] wire _out_T_1453 = ~out_rimask_132; // @[RegisterRouter.scala:87:24] wire _out_T_1454 = ~out_wimask_132; // @[RegisterRouter.scala:87:24] wire _out_T_1455 = ~out_romask_132; // @[RegisterRouter.scala:87:24] wire _out_T_1456 = ~out_womask_132; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1458 = _out_T_1457; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_103 = _out_T_1458; // @[RegisterRouter.scala:87:24] wire out_rimask_133 = \|_out_rimask_T_133; // @[RegisterRouter.scala:87:24] wire out_wimask_133 = &_out_wimask_T_133; // @[RegisterRouter.scala:87:24] wire out_romask_133 = \|_out_romask_T_133; // @[RegisterRouter.scala:87:24] wire out_womask_133 = &_out_womask_T_133; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_133 = out_rivalid_133 & out_rimask_133; // @[RegisterRouter.scala:87:24] wire _out_T_1460 = out_f_rivalid_133; // @[RegisterRouter.scala:87:24] assign out_f_roready_133 = out_roready_133 & out_romask_133; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_45 = out_f_roready_133; // @[RegisterRouter.scala:87:24] wire _out_T_1461 = out_f_roready_133; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_133 = out_wivalid_133 & out_wimask_133; // @[RegisterRouter.scala:87:24] wire _out_T_1462 = out_f_wivalid_133; // @[RegisterRouter.scala:87:24] assign out_f_woready_133 = out_woready_133 & out_womask_133; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_45 = out_f_woready_133; // @[RegisterRouter.scala:87:24] wire _out_T_1463 = out_f_woready_133; // @[RegisterRouter.scala:87:24] assign programBufferNxt_45 = out_f_woready_133 ? _out_T_1459 : programBufferMem_45; // @[RegisterRouter.scala:87:24] wire _out_T_1464 = ~out_rimask_133; // @[RegisterRouter.scala:87:24] wire _out_T_1465 = ~out_wimask_133; // @[RegisterRouter.scala:87:24] wire _out_T_1466 = ~out_romask_133; // @[RegisterRouter.scala:87:24] wire _out_T_1467 = ~out_womask_133; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_103 = {programBufferMem_45, _out_prepend_T_103}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1468 = out_prepend_103; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1469 = _out_T_1468; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_104 = _out_T_1469; // @[RegisterRouter.scala:87:24] wire out_rimask_134 = \|_out_rimask_T_134; // @[RegisterRouter.scala:87:24] wire out_wimask_134 = &_out_wimask_T_134; // @[RegisterRouter.scala:87:24] wire out_romask_134 = \|_out_romask_T_134; // @[RegisterRouter.scala:87:24] wire out_womask_134 = &_out_womask_T_134; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_134 = out_rivalid_134 & out_rimask_134; // @[RegisterRouter.scala:87:24] wire _out_T_1471 = out_f_rivalid_134; // @[RegisterRouter.scala:87:24] assign out_f_roready_134 = out_roready_134 & out_romask_134; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_46 = out_f_roready_134; // @[RegisterRouter.scala:87:24] wire _out_T_1472 = out_f_roready_134; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_134 = out_wivalid_134 & out_wimask_134; // @[RegisterRouter.scala:87:24] wire _out_T_1473 = out_f_wivalid_134; // @[RegisterRouter.scala:87:24] assign out_f_woready_134 = out_woready_134 & out_womask_134; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_46 = out_f_woready_134; // @[RegisterRouter.scala:87:24] wire _out_T_1474 = out_f_woready_134; // @[RegisterRouter.scala:87:24] assign programBufferNxt_46 = out_f_woready_134 ? _out_T_1470 : programBufferMem_46; // @[RegisterRouter.scala:87:24] wire _out_T_1475 = ~out_rimask_134; // @[RegisterRouter.scala:87:24] wire _out_T_1476 = ~out_wimask_134; // @[RegisterRouter.scala:87:24] wire _out_T_1477 = ~out_romask_134; // @[RegisterRouter.scala:87:24] wire _out_T_1478 = ~out_womask_134; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_104 = {programBufferMem_46, _out_prepend_T_104}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1479 = out_prepend_104; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1480 = _out_T_1479; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_105 = _out_T_1480; // @[RegisterRouter.scala:87:24] wire out_rimask_135 = \|_out_rimask_T_135; // @[RegisterRouter.scala:87:24] wire out_wimask_135 = &_out_wimask_T_135; // @[RegisterRouter.scala:87:24] wire out_romask_135 = \|_out_romask_T_135; // @[RegisterRouter.scala:87:24] wire out_womask_135 = &_out_womask_T_135; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_135 = out_rivalid_135 & out_rimask_135; // @[RegisterRouter.scala:87:24] wire _out_T_1482 = out_f_rivalid_135; // @[RegisterRouter.scala:87:24] assign out_f_roready_135 = out_roready_135 & out_romask_135; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_47 = out_f_roready_135; // @[RegisterRouter.scala:87:24] wire _out_T_1483 = out_f_roready_135; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_135 = out_wivalid_135 & out_wimask_135; // @[RegisterRouter.scala:87:24] wire _out_T_1484 = out_f_wivalid_135; // @[RegisterRouter.scala:87:24] assign out_f_woready_135 = out_woready_135 & out_womask_135; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_47 = out_f_woready_135; // @[RegisterRouter.scala:87:24] wire _out_T_1485 = out_f_woready_135; // @[RegisterRouter.scala:87:24] assign programBufferNxt_47 = out_f_woready_135 ? _out_T_1481 : programBufferMem_47; // @[RegisterRouter.scala:87:24] wire _out_T_1486 = ~out_rimask_135; // @[RegisterRouter.scala:87:24] wire _out_T_1487 = ~out_wimask_135; // @[RegisterRouter.scala:87:24] wire _out_T_1488 = ~out_romask_135; // @[RegisterRouter.scala:87:24] wire _out_T_1489 = ~out_womask_135; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_105 = {programBufferMem_47, _out_prepend_T_105}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1490 = out_prepend_105; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1491 = _out_T_1490; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_43 = _out_T_1491; // @[MuxLiteral.scala:49:48] wire out_rimask_136 = \|_out_rimask_T_136; // @[RegisterRouter.scala:87:24] wire out_wimask_136 = &_out_wimask_T_136; // @[RegisterRouter.scala:87:24] wire out_romask_136 = \|_out_romask_T_136; // @[RegisterRouter.scala:87:24] wire out_womask_136 = &_out_womask_T_136; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_136 = out_rivalid_136 & out_rimask_136; // @[RegisterRouter.scala:87:24] wire _out_T_1493 = out_f_rivalid_136; // @[RegisterRouter.scala:87:24] assign out_f_roready_136 = out_roready_136 & out_romask_136; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_32 = out_f_roready_136; // @[RegisterRouter.scala:87:24] wire _out_T_1494 = out_f_roready_136; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_136 = out_wivalid_136 & out_wimask_136; // @[RegisterRouter.scala:87:24] wire _out_T_1495 = out_f_wivalid_136; // @[RegisterRouter.scala:87:24] assign out_f_woready_136 = out_woready_136 & out_womask_136; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_32 = out_f_woready_136; // @[RegisterRouter.scala:87:24] wire _out_T_1496 = out_f_woready_136; // @[RegisterRouter.scala:87:24] assign programBufferNxt_32 = out_f_woready_136 ? _out_T_1492 : programBufferMem_32; // @[RegisterRouter.scala:87:24] wire _out_T_1497 = ~out_rimask_136; // @[RegisterRouter.scala:87:24] wire _out_T_1498 = ~out_wimask_136; // @[RegisterRouter.scala:87:24] wire _out_T_1499 = ~out_romask_136; // @[RegisterRouter.scala:87:24] wire _out_T_1500 = ~out_womask_136; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1502 = _out_T_1501; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_106 = _out_T_1502; // @[RegisterRouter.scala:87:24] wire out_rimask_137 = \|_out_rimask_T_137; // @[RegisterRouter.scala:87:24] wire out_wimask_137 = &_out_wimask_T_137; // @[RegisterRouter.scala:87:24] wire out_romask_137 = \|_out_romask_T_137; // @[RegisterRouter.scala:87:24] wire out_womask_137 = &_out_womask_T_137; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_137 = out_rivalid_137 & out_rimask_137; // @[RegisterRouter.scala:87:24] wire _out_T_1504 = out_f_rivalid_137; // @[RegisterRouter.scala:87:24] assign out_f_roready_137 = out_roready_137 & out_romask_137; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_33 = out_f_roready_137; // @[RegisterRouter.scala:87:24] wire _out_T_1505 = out_f_roready_137; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_137 = out_wivalid_137 & out_wimask_137; // @[RegisterRouter.scala:87:24] wire _out_T_1506 = out_f_wivalid_137; // @[RegisterRouter.scala:87:24] assign out_f_woready_137 = out_woready_137 & out_womask_137; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_33 = out_f_woready_137; // @[RegisterRouter.scala:87:24] wire _out_T_1507 = out_f_woready_137; // @[RegisterRouter.scala:87:24] assign programBufferNxt_33 = out_f_woready_137 ? _out_T_1503 : programBufferMem_33; // @[RegisterRouter.scala:87:24] wire _out_T_1508 = ~out_rimask_137; // @[RegisterRouter.scala:87:24] wire _out_T_1509 = ~out_wimask_137; // @[RegisterRouter.scala:87:24] wire _out_T_1510 = ~out_romask_137; // @[RegisterRouter.scala:87:24] wire _out_T_1511 = ~out_womask_137; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_106 = {programBufferMem_33, _out_prepend_T_106}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1512 = out_prepend_106; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1513 = _out_T_1512; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_107 = _out_T_1513; // @[RegisterRouter.scala:87:24] wire out_rimask_138 = \|_out_rimask_T_138; // @[RegisterRouter.scala:87:24] wire out_wimask_138 = &_out_wimask_T_138; // @[RegisterRouter.scala:87:24] wire out_romask_138 = \|_out_romask_T_138; // @[RegisterRouter.scala:87:24] wire out_womask_138 = &_out_womask_T_138; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_138 = out_rivalid_138 & out_rimask_138; // @[RegisterRouter.scala:87:24] wire _out_T_1515 = out_f_rivalid_138; // @[RegisterRouter.scala:87:24] assign out_f_roready_138 = out_roready_138 & out_romask_138; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_34 = out_f_roready_138; // @[RegisterRouter.scala:87:24] wire _out_T_1516 = out_f_roready_138; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_138 = out_wivalid_138 & out_wimask_138; // @[RegisterRouter.scala:87:24] wire _out_T_1517 = out_f_wivalid_138; // @[RegisterRouter.scala:87:24] assign out_f_woready_138 = out_woready_138 & out_womask_138; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_34 = out_f_woready_138; // @[RegisterRouter.scala:87:24] wire _out_T_1518 = out_f_woready_138; // @[RegisterRouter.scala:87:24] assign programBufferNxt_34 = out_f_woready_138 ? _out_T_1514 : programBufferMem_34; // @[RegisterRouter.scala:87:24] wire _out_T_1519 = ~out_rimask_138; // @[RegisterRouter.scala:87:24] wire _out_T_1520 = ~out_wimask_138; // @[RegisterRouter.scala:87:24] wire _out_T_1521 = ~out_romask_138; // @[RegisterRouter.scala:87:24] wire _out_T_1522 = ~out_womask_138; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_107 = {programBufferMem_34, _out_prepend_T_107}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1523 = out_prepend_107; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1524 = _out_T_1523; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_108 = _out_T_1524; // @[RegisterRouter.scala:87:24] wire out_rimask_139 = \|_out_rimask_T_139; // @[RegisterRouter.scala:87:24] wire out_wimask_139 = &_out_wimask_T_139; // @[RegisterRouter.scala:87:24] wire out_romask_139 = \|_out_romask_T_139; // @[RegisterRouter.scala:87:24] wire out_womask_139 = &_out_womask_T_139; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_139 = out_rivalid_139 & out_rimask_139; // @[RegisterRouter.scala:87:24] wire _out_T_1526 = out_f_rivalid_139; // @[RegisterRouter.scala:87:24] assign out_f_roready_139 = out_roready_139 & out_romask_139; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_35 = out_f_roready_139; // @[RegisterRouter.scala:87:24] wire _out_T_1527 = out_f_roready_139; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_139 = out_wivalid_139 & out_wimask_139; // @[RegisterRouter.scala:87:24] wire _out_T_1528 = out_f_wivalid_139; // @[RegisterRouter.scala:87:24] assign out_f_woready_139 = out_woready_139 & out_womask_139; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_35 = out_f_woready_139; // @[RegisterRouter.scala:87:24] wire _out_T_1529 = out_f_woready_139; // @[RegisterRouter.scala:87:24] assign programBufferNxt_35 = out_f_woready_139 ? _out_T_1525 : programBufferMem_35; // @[RegisterRouter.scala:87:24] wire _out_T_1530 = ~out_rimask_139; // @[RegisterRouter.scala:87:24] wire _out_T_1531 = ~out_wimask_139; // @[RegisterRouter.scala:87:24] wire _out_T_1532 = ~out_romask_139; // @[RegisterRouter.scala:87:24] wire _out_T_1533 = ~out_womask_139; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_108 = {programBufferMem_35, _out_prepend_T_108}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1534 = out_prepend_108; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1535 = _out_T_1534; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_40 = _out_T_1535; // @[MuxLiteral.scala:49:48] wire out_rimask_140 = \|_out_rimask_T_140; // @[RegisterRouter.scala:87:24] wire out_wimask_140 = &_out_wimask_T_140; // @[RegisterRouter.scala:87:24] wire out_romask_140 = \|_out_romask_T_140; // @[RegisterRouter.scala:87:24] wire out_womask_140 = &_out_womask_T_140; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_140 = out_rivalid_140 & out_rimask_140; // @[RegisterRouter.scala:87:24] wire _out_T_1537 = out_f_rivalid_140; // @[RegisterRouter.scala:87:24] assign out_f_roready_140 = out_roready_140 & out_romask_140; // @[RegisterRouter.scala:87:24] assign COMMANDRdEn = out_f_roready_140; // @[RegisterRouter.scala:87:24] wire _out_T_1538 = out_f_roready_140; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_140 = out_wivalid_140 & out_wimask_140; // @[RegisterRouter.scala:87:24] wire _out_T_1539 = out_f_wivalid_140; // @[RegisterRouter.scala:87:24] assign out_f_woready_140 = out_woready_140 & out_womask_140; // @[RegisterRouter.scala:87:24] assign COMMANDWrEnMaybe = out_f_woready_140; // @[RegisterRouter.scala:87:24] wire _out_T_1540 = out_f_woready_140; // @[RegisterRouter.scala:87:24] assign COMMANDWrDataVal = out_f_woready_140 ? _out_T_1536 : 32'h0; // @[RegisterRouter.scala:87:24] wire _out_T_1541 = ~out_rimask_140; // @[RegisterRouter.scala:87:24] wire _out_T_1542 = ~out_wimask_140; // @[RegisterRouter.scala:87:24] wire _out_T_1543 = ~out_romask_140; // @[RegisterRouter.scala:87:24] wire _out_T_1544 = ~out_womask_140; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1546 = _out_T_1545; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_23 = _out_T_1546; // @[MuxLiteral.scala:49:48] wire out_rimask_141 = \|_out_rimask_T_141; // @[RegisterRouter.scala:87:24] wire out_wimask_141 = &_out_wimask_T_141; // @[RegisterRouter.scala:87:24] wire out_romask_141 = \|_out_romask_T_141; // @[RegisterRouter.scala:87:24] wire out_womask_141 = &_out_womask_T_141; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_141 = out_rivalid_141 & out_rimask_141; // @[RegisterRouter.scala:87:24] wire _out_T_1548 = out_f_rivalid_141; // @[RegisterRouter.scala:87:24] assign out_f_roready_141 = out_roready_141 & out_romask_141; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_16 = out_f_roready_141; // @[RegisterRouter.scala:87:24] wire _out_T_1549 = out_f_roready_141; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_141 = out_wivalid_141 & out_wimask_141; // @[RegisterRouter.scala:87:24] wire _out_T_1550 = out_f_wivalid_141; // @[RegisterRouter.scala:87:24] assign out_f_woready_141 = out_woready_141 & out_womask_141; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_16 = out_f_woready_141; // @[RegisterRouter.scala:87:24] wire _out_T_1551 = out_f_woready_141; // @[RegisterRouter.scala:87:24] assign programBufferNxt_16 = out_f_woready_141 ? _out_T_1547 : programBufferMem_16; // @[RegisterRouter.scala:87:24] wire _out_T_1552 = ~out_rimask_141; // @[RegisterRouter.scala:87:24] wire _out_T_1553 = ~out_wimask_141; // @[RegisterRouter.scala:87:24] wire _out_T_1554 = ~out_romask_141; // @[RegisterRouter.scala:87:24] wire _out_T_1555 = ~out_womask_141; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1557 = _out_T_1556; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_109 = _out_T_1557; // @[RegisterRouter.scala:87:24] wire out_rimask_142 = \|_out_rimask_T_142; // @[RegisterRouter.scala:87:24] wire out_wimask_142 = &_out_wimask_T_142; // @[RegisterRouter.scala:87:24] wire out_romask_142 = \|_out_romask_T_142; // @[RegisterRouter.scala:87:24] wire out_womask_142 = &_out_womask_T_142; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_142 = out_rivalid_142 & out_rimask_142; // @[RegisterRouter.scala:87:24] wire _out_T_1559 = out_f_rivalid_142; // @[RegisterRouter.scala:87:24] assign out_f_roready_142 = out_roready_142 & out_romask_142; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_17 = out_f_roready_142; // @[RegisterRouter.scala:87:24] wire _out_T_1560 = out_f_roready_142; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_142 = out_wivalid_142 & out_wimask_142; // @[RegisterRouter.scala:87:24] wire _out_T_1561 = out_f_wivalid_142; // @[RegisterRouter.scala:87:24] assign out_f_woready_142 = out_woready_142 & out_womask_142; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_17 = out_f_woready_142; // @[RegisterRouter.scala:87:24] wire _out_T_1562 = out_f_woready_142; // @[RegisterRouter.scala:87:24] assign programBufferNxt_17 = out_f_woready_142 ? _out_T_1558 : programBufferMem_17; // @[RegisterRouter.scala:87:24] wire _out_T_1563 = ~out_rimask_142; // @[RegisterRouter.scala:87:24] wire _out_T_1564 = ~out_wimask_142; // @[RegisterRouter.scala:87:24] wire _out_T_1565 = ~out_romask_142; // @[RegisterRouter.scala:87:24] wire _out_T_1566 = ~out_womask_142; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_109 = {programBufferMem_17, _out_prepend_T_109}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1567 = out_prepend_109; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1568 = _out_T_1567; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_110 = _out_T_1568; // @[RegisterRouter.scala:87:24] wire out_rimask_143 = \|_out_rimask_T_143; // @[RegisterRouter.scala:87:24] wire out_wimask_143 = &_out_wimask_T_143; // @[RegisterRouter.scala:87:24] wire out_romask_143 = \|_out_romask_T_143; // @[RegisterRouter.scala:87:24] wire out_womask_143 = &_out_womask_T_143; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_143 = out_rivalid_143 & out_rimask_143; // @[RegisterRouter.scala:87:24] wire _out_T_1570 = out_f_rivalid_143; // @[RegisterRouter.scala:87:24] assign out_f_roready_143 = out_roready_143 & out_romask_143; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_18 = out_f_roready_143; // @[RegisterRouter.scala:87:24] wire _out_T_1571 = out_f_roready_143; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_143 = out_wivalid_143 & out_wimask_143; // @[RegisterRouter.scala:87:24] wire _out_T_1572 = out_f_wivalid_143; // @[RegisterRouter.scala:87:24] assign out_f_woready_143 = out_woready_143 & out_womask_143; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_18 = out_f_woready_143; // @[RegisterRouter.scala:87:24] wire _out_T_1573 = out_f_woready_143; // @[RegisterRouter.scala:87:24] assign programBufferNxt_18 = out_f_woready_143 ? _out_T_1569 : programBufferMem_18; // @[RegisterRouter.scala:87:24] wire _out_T_1574 = ~out_rimask_143; // @[RegisterRouter.scala:87:24] wire _out_T_1575 = ~out_wimask_143; // @[RegisterRouter.scala:87:24] wire _out_T_1576 = ~out_romask_143; // @[RegisterRouter.scala:87:24] wire _out_T_1577 = ~out_womask_143; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_110 = {programBufferMem_18, _out_prepend_T_110}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1578 = out_prepend_110; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1579 = _out_T_1578; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_111 = _out_T_1579; // @[RegisterRouter.scala:87:24] wire out_rimask_144 = \|_out_rimask_T_144; // @[RegisterRouter.scala:87:24] wire out_wimask_144 = &_out_wimask_T_144; // @[RegisterRouter.scala:87:24] wire out_romask_144 = \|_out_romask_T_144; // @[RegisterRouter.scala:87:24] wire out_womask_144 = &_out_womask_T_144; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_144 = out_rivalid_144 & out_rimask_144; // @[RegisterRouter.scala:87:24] wire _out_T_1581 = out_f_rivalid_144; // @[RegisterRouter.scala:87:24] assign out_f_roready_144 = out_roready_144 & out_romask_144; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_19 = out_f_roready_144; // @[RegisterRouter.scala:87:24] wire _out_T_1582 = out_f_roready_144; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_144 = out_wivalid_144 & out_wimask_144; // @[RegisterRouter.scala:87:24] wire _out_T_1583 = out_f_wivalid_144; // @[RegisterRouter.scala:87:24] assign out_f_woready_144 = out_woready_144 & out_womask_144; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_19 = out_f_woready_144; // @[RegisterRouter.scala:87:24] wire _out_T_1584 = out_f_woready_144; // @[RegisterRouter.scala:87:24] assign programBufferNxt_19 = out_f_woready_144 ? _out_T_1580 : programBufferMem_19; // @[RegisterRouter.scala:87:24] wire _out_T_1585 = ~out_rimask_144; // @[RegisterRouter.scala:87:24] wire _out_T_1586 = ~out_wimask_144; // @[RegisterRouter.scala:87:24] wire _out_T_1587 = ~out_romask_144; // @[RegisterRouter.scala:87:24] wire _out_T_1588 = ~out_womask_144; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_111 = {programBufferMem_19, _out_prepend_T_111}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1589 = out_prepend_111; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1590 = _out_T_1589; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_36 = _out_T_1590; // @[MuxLiteral.scala:49:48] wire out_rimask_145 = \|_out_rimask_T_145; // @[RegisterRouter.scala:87:24] wire out_wimask_145 = &_out_wimask_T_145; // @[RegisterRouter.scala:87:24] wire out_romask_145 = \|_out_romask_T_145; // @[RegisterRouter.scala:87:24] wire out_womask_145 = &_out_womask_T_145; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_145 = out_rivalid_145 & out_rimask_145; // @[RegisterRouter.scala:87:24] wire _out_T_1592 = out_f_rivalid_145; // @[RegisterRouter.scala:87:24] wire out_f_roready_145 = out_roready_145 & out_romask_145; // @[RegisterRouter.scala:87:24] wire _out_T_1593 = out_f_roready_145; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_145 = out_wivalid_145 & out_wimask_145; // @[RegisterRouter.scala:87:24] wire out_f_woready_145 = out_woready_145 & out_womask_145; // @[RegisterRouter.scala:87:24] wire _out_T_1594 = ~out_rimask_145; // @[RegisterRouter.scala:87:24] wire _out_T_1595 = ~out_wimask_145; // @[RegisterRouter.scala:87:24] wire _out_T_1596 = ~out_romask_145; // @[RegisterRouter.scala:87:24] wire _out_T_1597 = ~out_womask_145; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1599 = _out_T_1598; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_19 = _out_T_1599; // @[MuxLiteral.scala:49:48] wire _out_iindex_T = out_front_bits_index[0]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T = out_front_bits_index[0]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_1 = out_front_bits_index[1]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_1 = out_front_bits_index[1]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_2 = out_front_bits_index[2]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_2 = out_front_bits_index[2]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_3 = out_front_bits_index[3]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_3 = out_front_bits_index[3]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_4 = out_front_bits_index[4]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_4 = out_front_bits_index[4]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_5 = out_front_bits_index[5]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_5 = out_front_bits_index[5]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_6 = out_front_bits_index[6]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_6 = out_front_bits_index[6]; // @[RegisterRouter.scala:87:24] wire [1:0] out_iindex_lo_hi = {_out_iindex_T_2, _out_iindex_T_1}; // @[RegisterRouter.scala:87:24] wire [2:0] out_iindex_lo = {out_iindex_lo_hi, _out_iindex_T}; // @[RegisterRouter.scala:87:24] wire [1:0] out_iindex_hi_hi = {_out_iindex_T_5, _out_iindex_T_4}; // @[RegisterRouter.scala:87:24] wire [2:0] out_iindex_hi = {out_iindex_hi_hi, _out_iindex_T_3}; // @[RegisterRouter.scala:87:24] wire [5:0] out_iindex = {out_iindex_hi, out_iindex_lo}; // @[RegisterRouter.scala:87:24] wire [1:0] out_oindex_lo_hi = {_out_oindex_T_2, _out_oindex_T_1}; // @[RegisterRouter.scala:87:24] wire [2:0] out_oindex_lo = {out_oindex_lo_hi, _out_oindex_T}; // @[RegisterRouter.scala:87:24] wire [1:0] out_oindex_hi_hi = {_out_oindex_T_5, _out_oindex_T_4}; // @[RegisterRouter.scala:87:24] wire [2:0] out_oindex_hi = {out_oindex_hi_hi, _out_oindex_T_3}; // @[RegisterRouter.scala:87:24] wire [5:0] out_oindex = {out_oindex_hi, out_oindex_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_frontSel_T = 64'h1 << out_iindex; // @[OneHot.scala:58:35] wire out_frontSel_0 = _out_frontSel_T[0]; // @[OneHot.scala:58:35] wire out_frontSel_1 = _out_frontSel_T[1]; // @[OneHot.scala:58:35] wire out_frontSel_2 = _out_frontSel_T[2]; // @[OneHot.scala:58:35] wire out_frontSel_3 = _out_frontSel_T[3]; // @[OneHot.scala:58:35] wire out_frontSel_4 = _out_frontSel_T[4]; // @[OneHot.scala:58:35] wire out_frontSel_5 = _out_frontSel_T[5]; // @[OneHot.scala:58:35] wire out_frontSel_6 = _out_frontSel_T[6]; // @[OneHot.scala:58:35] wire out_frontSel_7 = _out_frontSel_T[7]; // @[OneHot.scala:58:35] wire out_frontSel_8 = _out_frontSel_T[8]; // @[OneHot.scala:58:35] wire out_frontSel_9 = _out_frontSel_T[9]; // @[OneHot.scala:58:35] wire out_frontSel_10 = _out_frontSel_T[10]; // @[OneHot.scala:58:35] wire out_frontSel_11 = _out_frontSel_T[11]; // @[OneHot.scala:58:35] wire out_frontSel_12 = _out_frontSel_T[12]; // @[OneHot.scala:58:35] wire out_frontSel_13 = _out_frontSel_T[13]; // @[OneHot.scala:58:35] wire out_frontSel_14 = _out_frontSel_T[14]; // @[OneHot.scala:58:35] wire out_frontSel_15 = _out_frontSel_T[15]; // @[OneHot.scala:58:35] wire out_frontSel_16 = _out_frontSel_T[16]; // @[OneHot.scala:58:35] wire out_frontSel_17 = _out_frontSel_T[17]; // @[OneHot.scala:58:35] wire out_frontSel_18 = _out_frontSel_T[18]; // @[OneHot.scala:58:35] wire out_frontSel_19 = _out_frontSel_T[19]; // @[OneHot.scala:58:35] wire out_frontSel_20 = _out_frontSel_T[20]; // @[OneHot.scala:58:35] wire out_frontSel_21 = _out_frontSel_T[21]; // @[OneHot.scala:58:35] wire out_frontSel_22 = _out_frontSel_T[22]; // @[OneHot.scala:58:35] wire out_frontSel_23 = _out_frontSel_T[23]; // @[OneHot.scala:58:35] wire out_frontSel_24 = _out_frontSel_T[24]; // @[OneHot.scala:58:35] wire out_frontSel_25 = _out_frontSel_T[25]; // @[OneHot.scala:58:35] wire out_frontSel_26 = _out_frontSel_T[26]; // @[OneHot.scala:58:35] wire out_frontSel_27 = _out_frontSel_T[27]; // @[OneHot.scala:58:35] wire out_frontSel_28 = _out_frontSel_T[28]; // @[OneHot.scala:58:35] wire out_frontSel_29 = _out_frontSel_T[29]; // @[OneHot.scala:58:35] wire out_frontSel_30 = _out_frontSel_T[30]; // @[OneHot.scala:58:35] wire out_frontSel_31 = _out_frontSel_T[31]; // @[OneHot.scala:58:35] wire out_frontSel_32 = _out_frontSel_T[32]; // @[OneHot.scala:58:35] wire out_frontSel_33 = _out_frontSel_T[33]; // @[OneHot.scala:58:35] wire out_frontSel_34 = _out_frontSel_T[34]; // @[OneHot.scala:58:35] wire out_frontSel_35 = _out_frontSel_T[35]; // @[OneHot.scala:58:35] wire out_frontSel_36 = _out_frontSel_T[36]; // @[OneHot.scala:58:35] wire out_frontSel_37 = _out_frontSel_T[37]; // @[OneHot.scala:58:35] wire out_frontSel_38 = _out_frontSel_T[38]; // @[OneHot.scala:58:35] wire out_frontSel_39 = _out_frontSel_T[39]; // @[OneHot.scala:58:35] wire out_frontSel_40 = _out_frontSel_T[40]; // @[OneHot.scala:58:35] wire out_frontSel_41 = _out_frontSel_T[41]; // @[OneHot.scala:58:35] wire out_frontSel_42 = _out_frontSel_T[42]; // @[OneHot.scala:58:35] wire out_frontSel_43 = _out_frontSel_T[43]; // @[OneHot.scala:58:35] wire out_frontSel_44 = _out_frontSel_T[44]; // @[OneHot.scala:58:35] wire out_frontSel_45 = _out_frontSel_T[45]; // @[OneHot.scala:58:35] wire out_frontSel_46 = _out_frontSel_T[46]; // @[OneHot.scala:58:35] wire out_frontSel_47 = _out_frontSel_T[47]; // @[OneHot.scala:58:35] wire out_frontSel_48 = _out_frontSel_T[48]; // @[OneHot.scala:58:35] wire out_frontSel_49 = _out_frontSel_T[49]; // @[OneHot.scala:58:35] wire out_frontSel_50 = _out_frontSel_T[50]; // @[OneHot.scala:58:35] wire out_frontSel_51 = _out_frontSel_T[51]; // @[OneHot.scala:58:35] wire out_frontSel_52 = _out_frontSel_T[52]; // @[OneHot.scala:58:35] wire out_frontSel_53 = _out_frontSel_T[53]; // @[OneHot.scala:58:35] wire out_frontSel_54 = _out_frontSel_T[54]; // @[OneHot.scala:58:35] wire out_frontSel_55 = _out_frontSel_T[55]; // @[OneHot.scala:58:35] wire out_frontSel_56 = _out_frontSel_T[56]; // @[OneHot.scala:58:35] wire out_frontSel_57 = _out_frontSel_T[57]; // @[OneHot.scala:58:35] wire out_frontSel_58 = _out_frontSel_T[58]; // @[OneHot.scala:58:35] wire out_frontSel_59 = _out_frontSel_T[59]; // @[OneHot.scala:58:35] wire out_frontSel_60 = _out_frontSel_T[60]; // @[OneHot.scala:58:35] wire out_frontSel_61 = _out_frontSel_T[61]; // @[OneHot.scala:58:35] wire out_frontSel_62 = _out_frontSel_T[62]; // @[OneHot.scala:58:35] wire out_frontSel_63 = _out_frontSel_T[63]; // @[OneHot.scala:58:35] wire [63:0] _out_backSel_T = 64'h1 << out_oindex; // @[OneHot.scala:58:35] wire out_backSel_0 = _out_backSel_T[0]; // @[OneHot.scala:58:35] wire out_backSel_1 = _out_backSel_T[1]; // @[OneHot.scala:58:35] wire out_backSel_2 = _out_backSel_T[2]; // @[OneHot.scala:58:35] wire out_backSel_3 = _out_backSel_T[3]; // @[OneHot.scala:58:35] wire out_backSel_4 = _out_backSel_T[4]; // @[OneHot.scala:58:35] wire out_backSel_5 = _out_backSel_T[5]; // @[OneHot.scala:58:35] wire out_backSel_6 = _out_backSel_T[6]; // @[OneHot.scala:58:35] wire out_backSel_7 = _out_backSel_T[7]; // @[OneHot.scala:58:35] wire out_backSel_8 = _out_backSel_T[8]; // @[OneHot.scala:58:35] wire out_backSel_9 = _out_backSel_T[9]; // @[OneHot.scala:58:35] wire out_backSel_10 = _out_backSel_T[10]; // @[OneHot.scala:58:35] wire out_backSel_11 = _out_backSel_T[11]; // @[OneHot.scala:58:35] wire out_backSel_12 = _out_backSel_T[12]; // @[OneHot.scala:58:35] wire out_backSel_13 = _out_backSel_T[13]; // @[OneHot.scala:58:35] wire out_backSel_14 = _out_backSel_T[14]; // @[OneHot.scala:58:35] wire out_backSel_15 = _out_backSel_T[15]; // @[OneHot.scala:58:35] wire out_backSel_16 = _out_backSel_T[16]; // @[OneHot.scala:58:35] wire out_backSel_17 = _out_backSel_T[17]; // @[OneHot.scala:58:35] wire out_backSel_18 = _out_backSel_T[18]; // @[OneHot.scala:58:35] wire out_backSel_19 = _out_backSel_T[19]; // @[OneHot.scala:58:35] wire out_backSel_20 = _out_backSel_T[20]; // @[OneHot.scala:58:35] wire out_backSel_21 = _out_backSel_T[21]; // @[OneHot.scala:58:35] wire out_backSel_22 = _out_backSel_T[22]; // @[OneHot.scala:58:35] wire out_backSel_23 = _out_backSel_T[23]; // @[OneHot.scala:58:35] wire out_backSel_24 = _out_backSel_T[24]; // @[OneHot.scala:58:35] wire out_backSel_25 = _out_backSel_T[25]; // @[OneHot.scala:58:35] wire out_backSel_26 = _out_backSel_T[26]; // @[OneHot.scala:58:35] wire out_backSel_27 = _out_backSel_T[27]; // @[OneHot.scala:58:35] wire out_backSel_28 = _out_backSel_T[28]; // @[OneHot.scala:58:35] wire out_backSel_29 = _out_backSel_T[29]; // @[OneHot.scala:58:35] wire out_backSel_30 = _out_backSel_T[30]; // @[OneHot.scala:58:35] wire out_backSel_31 = _out_backSel_T[31]; // @[OneHot.scala:58:35] wire out_backSel_32 = _out_backSel_T[32]; // @[OneHot.scala:58:35] wire out_backSel_33 = _out_backSel_T[33]; // @[OneHot.scala:58:35] wire out_backSel_34 = _out_backSel_T[34]; // @[OneHot.scala:58:35] wire out_backSel_35 = _out_backSel_T[35]; // @[OneHot.scala:58:35] wire out_backSel_36 = _out_backSel_T[36]; // @[OneHot.scala:58:35] wire out_backSel_37 = _out_backSel_T[37]; // @[OneHot.scala:58:35] wire out_backSel_38 = _out_backSel_T[38]; // @[OneHot.scala:58:35] wire out_backSel_39 = _out_backSel_T[39]; // @[OneHot.scala:58:35] wire out_backSel_40 = _out_backSel_T[40]; // @[OneHot.scala:58:35] wire out_backSel_41 = _out_backSel_T[41]; // @[OneHot.scala:58:35] wire out_backSel_42 = _out_backSel_T[42]; // @[OneHot.scala:58:35] wire out_backSel_43 = _out_backSel_T[43]; // @[OneHot.scala:58:35] wire out_backSel_44 = _out_backSel_T[44]; // @[OneHot.scala:58:35] wire out_backSel_45 = _out_backSel_T[45]; // @[OneHot.scala:58:35] wire out_backSel_46 = _out_backSel_T[46]; // @[OneHot.scala:58:35] wire out_backSel_47 = _out_backSel_T[47]; // @[OneHot.scala:58:35] wire out_backSel_48 = _out_backSel_T[48]; // @[OneHot.scala:58:35] wire out_backSel_49 = _out_backSel_T[49]; // @[OneHot.scala:58:35] wire out_backSel_50 = _out_backSel_T[50]; // @[OneHot.scala:58:35] wire out_backSel_51 = _out_backSel_T[51]; // @[OneHot.scala:58:35] wire out_backSel_52 = _out_backSel_T[52]; // @[OneHot.scala:58:35] wire out_backSel_53 = _out_backSel_T[53]; // @[OneHot.scala:58:35] wire out_backSel_54 = _out_backSel_T[54]; // @[OneHot.scala:58:35] wire out_backSel_55 = _out_backSel_T[55]; // @[OneHot.scala:58:35] wire out_backSel_56 = _out_backSel_T[56]; // @[OneHot.scala:58:35] wire out_backSel_57 = _out_backSel_T[57]; // @[OneHot.scala:58:35] wire out_backSel_58 = _out_backSel_T[58]; // @[OneHot.scala:58:35] wire out_backSel_59 = _out_backSel_T[59]; // @[OneHot.scala:58:35] wire out_backSel_60 = _out_backSel_T[60]; // @[OneHot.scala:58:35] wire out_backSel_61 = _out_backSel_T[61]; // @[OneHot.scala:58:35] wire out_backSel_62 = _out_backSel_T[62]; // @[OneHot.scala:58:35] wire out_backSel_63 = _out_backSel_T[63]; // @[OneHot.scala:58:35] wire _GEN_11 = in_valid & out_front_ready; // @[RegisterRouter.scala:73:18, :87:24] wire _out_rifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T = _GEN_11; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T = _GEN_11; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1 = _out_rifireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_2 = _out_rifireMux_T_1 & out_frontSel_0; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_3 = _out_rifireMux_T_2 & _out_T_40; // @[RegisterRouter.scala:87:24] assign out_rivalid_81 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_4 = ~_out_T_40; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_6 = _out_rifireMux_T_1 & out_frontSel_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_7 = _out_rifireMux_T_6; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_10 = _out_rifireMux_T_1 & out_frontSel_2; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_11 = _out_rifireMux_T_10; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_14 = _out_rifireMux_T_1 & out_frontSel_3; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_15 = _out_rifireMux_T_14; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_18 = _out_rifireMux_T_1 & out_frontSel_4; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_19 = _out_rifireMux_T_18 & _out_T_12; // @[RegisterRouter.scala:87:24] assign out_rivalid_21 = _out_rifireMux_T_19; // @[RegisterRouter.scala:87:24] assign out_rivalid_22 = _out_rifireMux_T_19; // @[RegisterRouter.scala:87:24] assign out_rivalid_23 = _out_rifireMux_T_19; // @[RegisterRouter.scala:87:24] assign out_rivalid_24 = _out_rifireMux_T_19; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_20 = ~_out_T_12; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_22 = _out_rifireMux_T_1 & out_frontSel_5; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_23 = _out_rifireMux_T_22 & _out_T; // @[RegisterRouter.scala:87:24] assign out_rivalid_0 = _out_rifireMux_T_23; // @[RegisterRouter.scala:87:24] assign out_rivalid_1 = _out_rifireMux_T_23; // @[RegisterRouter.scala:87:24] assign out_rivalid_2 = _out_rifireMux_T_23; // @[RegisterRouter.scala:87:24] assign out_rivalid_3 = _out_rifireMux_T_23; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_24 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_26 = _out_rifireMux_T_1 & out_frontSel_6; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_27 = _out_rifireMux_T_26 & _out_T_30; // @[RegisterRouter.scala:87:24] assign out_rivalid_64 = _out_rifireMux_T_27; // @[RegisterRouter.scala:87:24] assign out_rivalid_65 = _out_rifireMux_T_27; // @[RegisterRouter.scala:87:24] assign out_rivalid_66 = _out_rifireMux_T_27; // @[RegisterRouter.scala:87:24] assign out_rivalid_67 = _out_rifireMux_T_27; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_28 = ~_out_T_30; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_30 = _out_rifireMux_T_1 & out_frontSel_7; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_31 = _out_rifireMux_T_30 & _out_T_52; // @[RegisterRouter.scala:87:24] assign out_rivalid_120 = _out_rifireMux_T_31; // @[RegisterRouter.scala:87:24] assign out_rivalid_121 = _out_rifireMux_T_31; // @[RegisterRouter.scala:87:24] assign out_rivalid_122 = _out_rifireMux_T_31; // @[RegisterRouter.scala:87:24] assign out_rivalid_123 = _out_rifireMux_T_31; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_32 = ~_out_T_52; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_34 = _out_rifireMux_T_1 & out_frontSel_8; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_35 = _out_rifireMux_T_34 & _out_T_10; // @[RegisterRouter.scala:87:24] assign out_rivalid_17 = _out_rifireMux_T_35; // @[RegisterRouter.scala:87:24] assign out_rivalid_18 = _out_rifireMux_T_35; // @[RegisterRouter.scala:87:24] assign out_rivalid_19 = _out_rifireMux_T_35; // @[RegisterRouter.scala:87:24] assign out_rivalid_20 = _out_rifireMux_T_35; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_36 = ~_out_T_10; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_38 = _out_rifireMux_T_1 & out_frontSel_9; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_39 = _out_rifireMux_T_38 & _out_T_4; // @[RegisterRouter.scala:87:24] assign out_rivalid_5 = _out_rifireMux_T_39; // @[RegisterRouter.scala:87:24] assign out_rivalid_6 = _out_rifireMux_T_39; // @[RegisterRouter.scala:87:24] assign out_rivalid_7 = _out_rifireMux_T_39; // @[RegisterRouter.scala:87:24] assign out_rivalid_8 = _out_rifireMux_T_39; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_40 = ~_out_T_4; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_42 = _out_rifireMux_T_1 & out_frontSel_10; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_43 = _out_rifireMux_T_42 & _out_T_16; // @[RegisterRouter.scala:87:24] assign out_rivalid_29 = _out_rifireMux_T_43; // @[RegisterRouter.scala:87:24] assign out_rivalid_30 = _out_rifireMux_T_43; // @[RegisterRouter.scala:87:24] assign out_rivalid_31 = _out_rifireMux_T_43; // @[RegisterRouter.scala:87:24] assign out_rivalid_32 = _out_rifireMux_T_43; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_44 = ~_out_T_16; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_46 = _out_rifireMux_T_1 & out_frontSel_11; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_47 = _out_rifireMux_T_46 & _out_T_56; // @[RegisterRouter.scala:87:24] assign out_rivalid_128 = _out_rifireMux_T_47; // @[RegisterRouter.scala:87:24] assign out_rivalid_129 = _out_rifireMux_T_47; // @[RegisterRouter.scala:87:24] assign out_rivalid_130 = _out_rifireMux_T_47; // @[RegisterRouter.scala:87:24] assign out_rivalid_131 = _out_rifireMux_T_47; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_48 = ~_out_T_56; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_50 = _out_rifireMux_T_1 & out_frontSel_12; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_51 = _out_rifireMux_T_50; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_54 = _out_rifireMux_T_1 & out_frontSel_13; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_55 = _out_rifireMux_T_54; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_58 = _out_rifireMux_T_1 & out_frontSel_14; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_59 = _out_rifireMux_T_58; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_62 = _out_rifireMux_T_1 & out_frontSel_15; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_63 = _out_rifireMux_T_62; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_66 = _out_rifireMux_T_1 & out_frontSel_16; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_67 = _out_rifireMux_T_66; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_70 = _out_rifireMux_T_1 & out_frontSel_17; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_71 = _out_rifireMux_T_70 & _out_T_42; // @[RegisterRouter.scala:87:24] assign out_rivalid_82 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_rivalid_83 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_rivalid_84 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_rivalid_85 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_rivalid_86 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_rivalid_87 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_rivalid_88 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_rivalid_89 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_rivalid_90 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_rivalid_91 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_rivalid_92 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_rivalid_93 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_rivalid_94 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_rivalid_95 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_rivalid_96 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_rivalid_97 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_rivalid_98 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_rivalid_99 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_rivalid_100 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_72 = ~_out_T_42; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_74 = _out_rifireMux_T_1 & out_frontSel_18; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_75 = _out_rifireMux_T_74; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_78 = _out_rifireMux_T_1 & out_frontSel_19; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_79 = _out_rifireMux_T_78 & _out_T_66; // @[RegisterRouter.scala:87:24] assign out_rivalid_145 = _out_rifireMux_T_79; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_80 = ~_out_T_66; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_82 = _out_rifireMux_T_1 & out_frontSel_20; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_83 = _out_rifireMux_T_82; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_86 = _out_rifireMux_T_1 & out_frontSel_21; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_87 = _out_rifireMux_T_86; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_90 = _out_rifireMux_T_1 & out_frontSel_22; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_91 = _out_rifireMux_T_90 & _out_T_48; // @[RegisterRouter.scala:87:24] assign out_rivalid_109 = _out_rifireMux_T_91; // @[RegisterRouter.scala:87:24] assign out_rivalid_110 = _out_rifireMux_T_91; // @[RegisterRouter.scala:87:24] assign out_rivalid_111 = _out_rifireMux_T_91; // @[RegisterRouter.scala:87:24] assign out_rivalid_112 = _out_rifireMux_T_91; // @[RegisterRouter.scala:87:24] assign out_rivalid_113 = _out_rifireMux_T_91; // @[RegisterRouter.scala:87:24] assign out_rivalid_114 = _out_rifireMux_T_91; // @[RegisterRouter.scala:87:24] assign out_rivalid_115 = _out_rifireMux_T_91; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_92 = ~_out_T_48; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_94 = _out_rifireMux_T_1 & out_frontSel_23; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_95 = _out_rifireMux_T_94 & _out_T_62; // @[RegisterRouter.scala:87:24] assign out_rivalid_140 = _out_rifireMux_T_95; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_96 = ~_out_T_62; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_98 = _out_rifireMux_T_1 & out_frontSel_24; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_99 = _out_rifireMux_T_98 & _out_T_22; // @[RegisterRouter.scala:87:24] assign out_rivalid_52 = _out_rifireMux_T_99; // @[RegisterRouter.scala:87:24] assign out_rivalid_53 = _out_rifireMux_T_99; // @[RegisterRouter.scala:87:24] assign out_rivalid_54 = _out_rifireMux_T_99; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_100 = ~_out_T_22; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_102 = _out_rifireMux_T_1 & out_frontSel_25; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_103 = _out_rifireMux_T_102; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_106 = _out_rifireMux_T_1 & out_frontSel_26; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_107 = _out_rifireMux_T_106; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_110 = _out_rifireMux_T_1 & out_frontSel_27; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_111 = _out_rifireMux_T_110; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_114 = _out_rifireMux_T_1 & out_frontSel_28; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_115 = _out_rifireMux_T_114; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_118 = _out_rifireMux_T_1 & out_frontSel_29; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_119 = _out_rifireMux_T_118; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_122 = _out_rifireMux_T_1 & out_frontSel_30; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_123 = _out_rifireMux_T_122; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_126 = _out_rifireMux_T_1 & out_frontSel_31; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_127 = _out_rifireMux_T_126; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_130 = _out_rifireMux_T_1 & out_frontSel_32; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_131 = _out_rifireMux_T_130 & _out_T_44; // @[RegisterRouter.scala:87:24] assign out_rivalid_101 = _out_rifireMux_T_131; // @[RegisterRouter.scala:87:24] assign out_rivalid_102 = _out_rifireMux_T_131; // @[RegisterRouter.scala:87:24] assign out_rivalid_103 = _out_rifireMux_T_131; // @[RegisterRouter.scala:87:24] assign out_rivalid_104 = _out_rifireMux_T_131; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_132 = ~_out_T_44; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_134 = _out_rifireMux_T_1 & out_frontSel_33; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_135 = _out_rifireMux_T_134 & _out_T_36; // @[RegisterRouter.scala:87:24] assign out_rivalid_73 = _out_rifireMux_T_135; // @[RegisterRouter.scala:87:24] assign out_rivalid_74 = _out_rifireMux_T_135; // @[RegisterRouter.scala:87:24] assign out_rivalid_75 = _out_rifireMux_T_135; // @[RegisterRouter.scala:87:24] assign out_rivalid_76 = _out_rifireMux_T_135; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_136 = ~_out_T_36; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_138 = _out_rifireMux_T_1 & out_frontSel_34; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_139 = _out_rifireMux_T_138 & _out_T_46; // @[RegisterRouter.scala:87:24] assign out_rivalid_105 = _out_rifireMux_T_139; // @[RegisterRouter.scala:87:24] assign out_rivalid_106 = _out_rifireMux_T_139; // @[RegisterRouter.scala:87:24] assign out_rivalid_107 = _out_rifireMux_T_139; // @[RegisterRouter.scala:87:24] assign out_rivalid_108 = _out_rifireMux_T_139; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_140 = ~_out_T_46; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_142 = _out_rifireMux_T_1 & out_frontSel_35; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_143 = _out_rifireMux_T_142 & _out_T_8; // @[RegisterRouter.scala:87:24] assign out_rivalid_13 = _out_rifireMux_T_143; // @[RegisterRouter.scala:87:24] assign out_rivalid_14 = _out_rifireMux_T_143; // @[RegisterRouter.scala:87:24] assign out_rivalid_15 = _out_rifireMux_T_143; // @[RegisterRouter.scala:87:24] assign out_rivalid_16 = _out_rifireMux_T_143; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_144 = ~_out_T_8; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_146 = _out_rifireMux_T_1 & out_frontSel_36; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_147 = _out_rifireMux_T_146 & _out_T_64; // @[RegisterRouter.scala:87:24] assign out_rivalid_141 = _out_rifireMux_T_147; // @[RegisterRouter.scala:87:24] assign out_rivalid_142 = _out_rifireMux_T_147; // @[RegisterRouter.scala:87:24] assign out_rivalid_143 = _out_rifireMux_T_147; // @[RegisterRouter.scala:87:24] assign out_rivalid_144 = _out_rifireMux_T_147; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_148 = ~_out_T_64; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_150 = _out_rifireMux_T_1 & out_frontSel_37; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_151 = _out_rifireMux_T_150 & _out_T_24; // @[RegisterRouter.scala:87:24] assign out_rivalid_55 = _out_rifireMux_T_151; // @[RegisterRouter.scala:87:24] assign out_rivalid_56 = _out_rifireMux_T_151; // @[RegisterRouter.scala:87:24] assign out_rivalid_57 = _out_rifireMux_T_151; // @[RegisterRouter.scala:87:24] assign out_rivalid_58 = _out_rifireMux_T_151; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_152 = ~_out_T_24; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_154 = _out_rifireMux_T_1 & out_frontSel_38; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_155 = _out_rifireMux_T_154 & _out_T_34; // @[RegisterRouter.scala:87:24] assign out_rivalid_69 = _out_rifireMux_T_155; // @[RegisterRouter.scala:87:24] assign out_rivalid_70 = _out_rifireMux_T_155; // @[RegisterRouter.scala:87:24] assign out_rivalid_71 = _out_rifireMux_T_155; // @[RegisterRouter.scala:87:24] assign out_rivalid_72 = _out_rifireMux_T_155; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_156 = ~_out_T_34; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_158 = _out_rifireMux_T_1 & out_frontSel_39; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_159 = _out_rifireMux_T_158 & _out_T_54; // @[RegisterRouter.scala:87:24] assign out_rivalid_124 = _out_rifireMux_T_159; // @[RegisterRouter.scala:87:24] assign out_rivalid_125 = _out_rifireMux_T_159; // @[RegisterRouter.scala:87:24] assign out_rivalid_126 = _out_rifireMux_T_159; // @[RegisterRouter.scala:87:24] assign out_rivalid_127 = _out_rifireMux_T_159; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_160 = ~_out_T_54; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_162 = _out_rifireMux_T_1 & out_frontSel_40; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_163 = _out_rifireMux_T_162 & _out_T_60; // @[RegisterRouter.scala:87:24] assign out_rivalid_136 = _out_rifireMux_T_163; // @[RegisterRouter.scala:87:24] assign out_rivalid_137 = _out_rifireMux_T_163; // @[RegisterRouter.scala:87:24] assign out_rivalid_138 = _out_rifireMux_T_163; // @[RegisterRouter.scala:87:24] assign out_rivalid_139 = _out_rifireMux_T_163; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_164 = ~_out_T_60; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_166 = _out_rifireMux_T_1 & out_frontSel_41; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_167 = _out_rifireMux_T_166 & _out_T_6; // @[RegisterRouter.scala:87:24] assign out_rivalid_9 = _out_rifireMux_T_167; // @[RegisterRouter.scala:87:24] assign out_rivalid_10 = _out_rifireMux_T_167; // @[RegisterRouter.scala:87:24] assign out_rivalid_11 = _out_rifireMux_T_167; // @[RegisterRouter.scala:87:24] assign out_rivalid_12 = _out_rifireMux_T_167; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_168 = ~_out_T_6; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_170 = _out_rifireMux_T_1 & out_frontSel_42; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_171 = _out_rifireMux_T_170 & _out_T_20; // @[RegisterRouter.scala:87:24] assign out_rivalid_48 = _out_rifireMux_T_171; // @[RegisterRouter.scala:87:24] assign out_rivalid_49 = _out_rifireMux_T_171; // @[RegisterRouter.scala:87:24] assign out_rivalid_50 = _out_rifireMux_T_171; // @[RegisterRouter.scala:87:24] assign out_rivalid_51 = _out_rifireMux_T_171; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_172 = ~_out_T_20; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_174 = _out_rifireMux_T_1 & out_frontSel_43; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_175 = _out_rifireMux_T_174 & _out_T_58; // @[RegisterRouter.scala:87:24] assign out_rivalid_132 = _out_rifireMux_T_175; // @[RegisterRouter.scala:87:24] assign out_rivalid_133 = _out_rifireMux_T_175; // @[RegisterRouter.scala:87:24] assign out_rivalid_134 = _out_rifireMux_T_175; // @[RegisterRouter.scala:87:24] assign out_rivalid_135 = _out_rifireMux_T_175; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_176 = ~_out_T_58; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_178 = _out_rifireMux_T_1 & out_frontSel_44; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_179 = _out_rifireMux_T_178 & _out_T_50; // @[RegisterRouter.scala:87:24] assign out_rivalid_116 = _out_rifireMux_T_179; // @[RegisterRouter.scala:87:24] assign out_rivalid_117 = _out_rifireMux_T_179; // @[RegisterRouter.scala:87:24] assign out_rivalid_118 = _out_rifireMux_T_179; // @[RegisterRouter.scala:87:24] assign out_rivalid_119 = _out_rifireMux_T_179; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_180 = ~_out_T_50; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_182 = _out_rifireMux_T_1 & out_frontSel_45; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_183 = _out_rifireMux_T_182 & _out_T_38; // @[RegisterRouter.scala:87:24] assign out_rivalid_77 = _out_rifireMux_T_183; // @[RegisterRouter.scala:87:24] assign out_rivalid_78 = _out_rifireMux_T_183; // @[RegisterRouter.scala:87:24] assign out_rivalid_79 = _out_rifireMux_T_183; // @[RegisterRouter.scala:87:24] assign out_rivalid_80 = _out_rifireMux_T_183; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_184 = ~_out_T_38; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_186 = _out_rifireMux_T_1 & out_frontSel_46; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_187 = _out_rifireMux_T_186 & _out_T_26; // @[RegisterRouter.scala:87:24] assign out_rivalid_59 = _out_rifireMux_T_187; // @[RegisterRouter.scala:87:24] assign out_rivalid_60 = _out_rifireMux_T_187; // @[RegisterRouter.scala:87:24] assign out_rivalid_61 = _out_rifireMux_T_187; // @[RegisterRouter.scala:87:24] assign out_rivalid_62 = _out_rifireMux_T_187; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_188 = ~_out_T_26; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_190 = _out_rifireMux_T_1 & out_frontSel_47; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_191 = _out_rifireMux_T_190 & _out_T_14; // @[RegisterRouter.scala:87:24] assign out_rivalid_25 = _out_rifireMux_T_191; // @[RegisterRouter.scala:87:24] assign out_rivalid_26 = _out_rifireMux_T_191; // @[RegisterRouter.scala:87:24] assign out_rivalid_27 = _out_rifireMux_T_191; // @[RegisterRouter.scala:87:24] assign out_rivalid_28 = _out_rifireMux_T_191; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_192 = ~_out_T_14; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_194 = _out_rifireMux_T_1 & out_frontSel_48; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_195 = _out_rifireMux_T_194; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_198 = _out_rifireMux_T_1 & out_frontSel_49; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_199 = _out_rifireMux_T_198; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_202 = _out_rifireMux_T_1 & out_frontSel_50; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_203 = _out_rifireMux_T_202; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_206 = _out_rifireMux_T_1 & out_frontSel_51; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_207 = _out_rifireMux_T_206; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_210 = _out_rifireMux_T_1 & out_frontSel_52; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_211 = _out_rifireMux_T_210; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_214 = _out_rifireMux_T_1 & out_frontSel_53; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_215 = _out_rifireMux_T_214; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_218 = _out_rifireMux_T_1 & out_frontSel_54; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_219 = _out_rifireMux_T_218; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_222 = _out_rifireMux_T_1 & out_frontSel_55; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_223 = _out_rifireMux_T_222; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_226 = _out_rifireMux_T_1 & out_frontSel_56; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_227 = _out_rifireMux_T_226 & _out_T_18; // @[RegisterRouter.scala:87:24] assign out_rivalid_33 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_rivalid_34 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_rivalid_35 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_rivalid_36 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_rivalid_37 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_rivalid_38 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_rivalid_39 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_rivalid_40 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_rivalid_41 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_rivalid_42 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_rivalid_43 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_rivalid_44 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_rivalid_45 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_rivalid_46 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_rivalid_47 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_228 = ~_out_T_18; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_230 = _out_rifireMux_T_1 & out_frontSel_57; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_231 = _out_rifireMux_T_230 & _out_T_28; // @[RegisterRouter.scala:87:24] assign out_rivalid_63 = _out_rifireMux_T_231; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_232 = ~_out_T_28; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_234 = _out_rifireMux_T_1 & out_frontSel_58; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_235 = _out_rifireMux_T_234; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_238 = _out_rifireMux_T_1 & out_frontSel_59; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_239 = _out_rifireMux_T_238; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_242 = _out_rifireMux_T_1 & out_frontSel_60; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_243 = _out_rifireMux_T_242 & _out_T_32; // @[RegisterRouter.scala:87:24] assign out_rivalid_68 = _out_rifireMux_T_243; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_244 = ~_out_T_32; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_246 = _out_rifireMux_T_1 & out_frontSel_61; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_247 = _out_rifireMux_T_246 & _out_T_2; // @[RegisterRouter.scala:87:24] assign out_rivalid_4 = _out_rifireMux_T_247; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_248 = ~_out_T_2; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_250 = _out_rifireMux_T_1 & out_frontSel_62; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_251 = _out_rifireMux_T_250; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_254 = _out_rifireMux_T_1 & out_frontSel_63; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_255 = _out_rifireMux_T_254; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_2 = _out_wifireMux_T & _out_wifireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_3 = _out_wifireMux_T_2 & out_frontSel_0; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_4 = _out_wifireMux_T_3 & _out_T_40; // @[RegisterRouter.scala:87:24] assign out_wivalid_81 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_5 = ~_out_T_40; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_7 = _out_wifireMux_T_2 & out_frontSel_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_8 = _out_wifireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_11 = _out_wifireMux_T_2 & out_frontSel_2; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_12 = _out_wifireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_15 = _out_wifireMux_T_2 & out_frontSel_3; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_16 = _out_wifireMux_T_15; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_19 = _out_wifireMux_T_2 & out_frontSel_4; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_20 = _out_wifireMux_T_19 & _out_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_21 = _out_wifireMux_T_20; // @[RegisterRouter.scala:87:24] assign out_wivalid_22 = _out_wifireMux_T_20; // @[RegisterRouter.scala:87:24] assign out_wivalid_23 = _out_wifireMux_T_20; // @[RegisterRouter.scala:87:24] assign out_wivalid_24 = _out_wifireMux_T_20; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_21 = ~_out_T_12; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_23 = _out_wifireMux_T_2 & out_frontSel_5; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_24 = _out_wifireMux_T_23 & _out_T; // @[RegisterRouter.scala:87:24] assign out_wivalid_0 = _out_wifireMux_T_24; // @[RegisterRouter.scala:87:24] assign out_wivalid_1 = _out_wifireMux_T_24; // @[RegisterRouter.scala:87:24] assign out_wivalid_2 = _out_wifireMux_T_24; // @[RegisterRouter.scala:87:24] assign out_wivalid_3 = _out_wifireMux_T_24; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_25 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_27 = _out_wifireMux_T_2 & out_frontSel_6; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_28 = _out_wifireMux_T_27 & _out_T_30; // @[RegisterRouter.scala:87:24] assign out_wivalid_64 = _out_wifireMux_T_28; // @[RegisterRouter.scala:87:24] assign out_wivalid_65 = _out_wifireMux_T_28; // @[RegisterRouter.scala:87:24] assign out_wivalid_66 = _out_wifireMux_T_28; // @[RegisterRouter.scala:87:24] assign out_wivalid_67 = _out_wifireMux_T_28; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_29 = ~_out_T_30; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_31 = _out_wifireMux_T_2 & out_frontSel_7; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_32 = _out_wifireMux_T_31 & _out_T_52; // @[RegisterRouter.scala:87:24] assign out_wivalid_120 = _out_wifireMux_T_32; // @[RegisterRouter.scala:87:24] assign out_wivalid_121 = _out_wifireMux_T_32; // @[RegisterRouter.scala:87:24] assign out_wivalid_122 = _out_wifireMux_T_32; // @[RegisterRouter.scala:87:24] assign out_wivalid_123 = _out_wifireMux_T_32; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_33 = ~_out_T_52; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_35 = _out_wifireMux_T_2 & out_frontSel_8; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_36 = _out_wifireMux_T_35 & _out_T_10; // @[RegisterRouter.scala:87:24] assign out_wivalid_17 = _out_wifireMux_T_36; // @[RegisterRouter.scala:87:24] assign out_wivalid_18 = _out_wifireMux_T_36; // @[RegisterRouter.scala:87:24] assign out_wivalid_19 = _out_wifireMux_T_36; // @[RegisterRouter.scala:87:24] assign out_wivalid_20 = _out_wifireMux_T_36; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_37 = ~_out_T_10; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_39 = _out_wifireMux_T_2 & out_frontSel_9; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_40 = _out_wifireMux_T_39 & _out_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_5 = _out_wifireMux_T_40; // @[RegisterRouter.scala:87:24] assign out_wivalid_6 = _out_wifireMux_T_40; // @[RegisterRouter.scala:87:24] assign out_wivalid_7 = _out_wifireMux_T_40; // @[RegisterRouter.scala:87:24] assign out_wivalid_8 = _out_wifireMux_T_40; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_41 = ~_out_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_43 = _out_wifireMux_T_2 & out_frontSel_10; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_44 = _out_wifireMux_T_43 & _out_T_16; // @[RegisterRouter.scala:87:24] assign out_wivalid_29 = _out_wifireMux_T_44; // @[RegisterRouter.scala:87:24] assign out_wivalid_30 = _out_wifireMux_T_44; // @[RegisterRouter.scala:87:24] assign out_wivalid_31 = _out_wifireMux_T_44; // @[RegisterRouter.scala:87:24] assign out_wivalid_32 = _out_wifireMux_T_44; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_45 = ~_out_T_16; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_47 = _out_wifireMux_T_2 & out_frontSel_11; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_48 = _out_wifireMux_T_47 & _out_T_56; // @[RegisterRouter.scala:87:24] assign out_wivalid_128 = _out_wifireMux_T_48; // @[RegisterRouter.scala:87:24] assign out_wivalid_129 = _out_wifireMux_T_48; // @[RegisterRouter.scala:87:24] assign out_wivalid_130 = _out_wifireMux_T_48; // @[RegisterRouter.scala:87:24] assign out_wivalid_131 = _out_wifireMux_T_48; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_49 = ~_out_T_56; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_51 = _out_wifireMux_T_2 & out_frontSel_12; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_52 = _out_wifireMux_T_51; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_55 = _out_wifireMux_T_2 & out_frontSel_13; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_56 = _out_wifireMux_T_55; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_59 = _out_wifireMux_T_2 & out_frontSel_14; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_60 = _out_wifireMux_T_59; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_63 = _out_wifireMux_T_2 & out_frontSel_15; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_64 = _out_wifireMux_T_63; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_67 = _out_wifireMux_T_2 & out_frontSel_16; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_68 = _out_wifireMux_T_67; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_71 = _out_wifireMux_T_2 & out_frontSel_17; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_72 = _out_wifireMux_T_71 & _out_T_42; // @[RegisterRouter.scala:87:24] assign out_wivalid_82 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_wivalid_83 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_wivalid_84 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_wivalid_85 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_wivalid_86 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_wivalid_87 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_wivalid_88 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_wivalid_89 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_wivalid_90 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_wivalid_91 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_wivalid_92 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_wivalid_93 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_wivalid_94 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_wivalid_95 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_wivalid_96 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_wivalid_97 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_wivalid_98 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_wivalid_99 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_wivalid_100 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_73 = ~_out_T_42; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_75 = _out_wifireMux_T_2 & out_frontSel_18; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_76 = _out_wifireMux_T_75; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_79 = _out_wifireMux_T_2 & out_frontSel_19; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_80 = _out_wifireMux_T_79 & _out_T_66; // @[RegisterRouter.scala:87:24] assign out_wivalid_145 = _out_wifireMux_T_80; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_81 = ~_out_T_66; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_83 = _out_wifireMux_T_2 & out_frontSel_20; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_84 = _out_wifireMux_T_83; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_87 = _out_wifireMux_T_2 & out_frontSel_21; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_88 = _out_wifireMux_T_87; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_91 = _out_wifireMux_T_2 & out_frontSel_22; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_92 = _out_wifireMux_T_91 & _out_T_48; // @[RegisterRouter.scala:87:24] assign out_wivalid_109 = _out_wifireMux_T_92; // @[RegisterRouter.scala:87:24] assign out_wivalid_110 = _out_wifireMux_T_92; // @[RegisterRouter.scala:87:24] assign out_wivalid_111 = _out_wifireMux_T_92; // @[RegisterRouter.scala:87:24] assign out_wivalid_112 = _out_wifireMux_T_92; // @[RegisterRouter.scala:87:24] assign out_wivalid_113 = _out_wifireMux_T_92; // @[RegisterRouter.scala:87:24] assign out_wivalid_114 = _out_wifireMux_T_92; // @[RegisterRouter.scala:87:24] assign out_wivalid_115 = _out_wifireMux_T_92; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_93 = ~_out_T_48; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_95 = _out_wifireMux_T_2 & out_frontSel_23; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_96 = _out_wifireMux_T_95 & _out_T_62; // @[RegisterRouter.scala:87:24] assign out_wivalid_140 = _out_wifireMux_T_96; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_97 = ~_out_T_62; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_99 = _out_wifireMux_T_2 & out_frontSel_24; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_100 = _out_wifireMux_T_99 & _out_T_22; // @[RegisterRouter.scala:87:24] assign out_wivalid_52 = _out_wifireMux_T_100; // @[RegisterRouter.scala:87:24] assign out_wivalid_53 = _out_wifireMux_T_100; // @[RegisterRouter.scala:87:24] assign out_wivalid_54 = _out_wifireMux_T_100; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_101 = ~_out_T_22; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_103 = _out_wifireMux_T_2 & out_frontSel_25; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_104 = _out_wifireMux_T_103; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_107 = _out_wifireMux_T_2 & out_frontSel_26; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_108 = _out_wifireMux_T_107; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_111 = _out_wifireMux_T_2 & out_frontSel_27; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_112 = _out_wifireMux_T_111; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_115 = _out_wifireMux_T_2 & out_frontSel_28; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_116 = _out_wifireMux_T_115; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_119 = _out_wifireMux_T_2 & out_frontSel_29; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_120 = _out_wifireMux_T_119; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_123 = _out_wifireMux_T_2 & out_frontSel_30; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_124 = _out_wifireMux_T_123; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_127 = _out_wifireMux_T_2 & out_frontSel_31; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_128 = _out_wifireMux_T_127; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_131 = _out_wifireMux_T_2 & out_frontSel_32; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_132 = _out_wifireMux_T_131 & _out_T_44; // @[RegisterRouter.scala:87:24] assign out_wivalid_101 = _out_wifireMux_T_132; // @[RegisterRouter.scala:87:24] assign out_wivalid_102 = _out_wifireMux_T_132; // @[RegisterRouter.scala:87:24] assign out_wivalid_103 = _out_wifireMux_T_132; // @[RegisterRouter.scala:87:24] assign out_wivalid_104 = _out_wifireMux_T_132; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_133 = ~_out_T_44; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_135 = _out_wifireMux_T_2 & out_frontSel_33; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_136 = _out_wifireMux_T_135 & _out_T_36; // @[RegisterRouter.scala:87:24] assign out_wivalid_73 = _out_wifireMux_T_136; // @[RegisterRouter.scala:87:24] assign out_wivalid_74 = _out_wifireMux_T_136; // @[RegisterRouter.scala:87:24] assign out_wivalid_75 = _out_wifireMux_T_136; // @[RegisterRouter.scala:87:24] assign out_wivalid_76 = _out_wifireMux_T_136; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_137 = ~_out_T_36; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_139 = _out_wifireMux_T_2 & out_frontSel_34; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_140 = _out_wifireMux_T_139 & _out_T_46; // @[RegisterRouter.scala:87:24] assign out_wivalid_105 = _out_wifireMux_T_140; // @[RegisterRouter.scala:87:24] assign out_wivalid_106 = _out_wifireMux_T_140; // @[RegisterRouter.scala:87:24] assign out_wivalid_107 = _out_wifireMux_T_140; // @[RegisterRouter.scala:87:24] assign out_wivalid_108 = _out_wifireMux_T_140; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_141 = ~_out_T_46; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_143 = _out_wifireMux_T_2 & out_frontSel_35; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_144 = _out_wifireMux_T_143 & _out_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_13 = _out_wifireMux_T_144; // @[RegisterRouter.scala:87:24] assign out_wivalid_14 = _out_wifireMux_T_144; // @[RegisterRouter.scala:87:24] assign out_wivalid_15 = _out_wifireMux_T_144; // @[RegisterRouter.scala:87:24] assign out_wivalid_16 = _out_wifireMux_T_144; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_145 = ~_out_T_8; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_147 = _out_wifireMux_T_2 & out_frontSel_36; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_148 = _out_wifireMux_T_147 & _out_T_64; // @[RegisterRouter.scala:87:24] assign out_wivalid_141 = _out_wifireMux_T_148; // @[RegisterRouter.scala:87:24] assign out_wivalid_142 = _out_wifireMux_T_148; // @[RegisterRouter.scala:87:24] assign out_wivalid_143 = _out_wifireMux_T_148; // @[RegisterRouter.scala:87:24] assign out_wivalid_144 = _out_wifireMux_T_148; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_149 = ~_out_T_64; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_151 = _out_wifireMux_T_2 & out_frontSel_37; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_152 = _out_wifireMux_T_151 & _out_T_24; // @[RegisterRouter.scala:87:24] assign out_wivalid_55 = _out_wifireMux_T_152; // @[RegisterRouter.scala:87:24] assign out_wivalid_56 = _out_wifireMux_T_152; // @[RegisterRouter.scala:87:24] assign out_wivalid_57 = _out_wifireMux_T_152; // @[RegisterRouter.scala:87:24] assign out_wivalid_58 = _out_wifireMux_T_152; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_153 = ~_out_T_24; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_155 = _out_wifireMux_T_2 & out_frontSel_38; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_156 = _out_wifireMux_T_155 & _out_T_34; // @[RegisterRouter.scala:87:24] assign out_wivalid_69 = _out_wifireMux_T_156; // @[RegisterRouter.scala:87:24] assign out_wivalid_70 = _out_wifireMux_T_156; // @[RegisterRouter.scala:87:24] assign out_wivalid_71 = _out_wifireMux_T_156; // @[RegisterRouter.scala:87:24] assign out_wivalid_72 = _out_wifireMux_T_156; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_157 = ~_out_T_34; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_159 = _out_wifireMux_T_2 & out_frontSel_39; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_160 = _out_wifireMux_T_159 & _out_T_54; // @[RegisterRouter.scala:87:24] assign out_wivalid_124 = _out_wifireMux_T_160; // @[RegisterRouter.scala:87:24] assign out_wivalid_125 = _out_wifireMux_T_160; // @[RegisterRouter.scala:87:24] assign out_wivalid_126 = _out_wifireMux_T_160; // @[RegisterRouter.scala:87:24] assign out_wivalid_127 = _out_wifireMux_T_160; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_161 = ~_out_T_54; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_163 = _out_wifireMux_T_2 & out_frontSel_40; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_164 = _out_wifireMux_T_163 & _out_T_60; // @[RegisterRouter.scala:87:24] assign out_wivalid_136 = _out_wifireMux_T_164; // @[RegisterRouter.scala:87:24] assign out_wivalid_137 = _out_wifireMux_T_164; // @[RegisterRouter.scala:87:24] assign out_wivalid_138 = _out_wifireMux_T_164; // @[RegisterRouter.scala:87:24] assign out_wivalid_139 = _out_wifireMux_T_164; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_165 = ~_out_T_60; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_167 = _out_wifireMux_T_2 & out_frontSel_41; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_168 = _out_wifireMux_T_167 & _out_T_6; // @[RegisterRouter.scala:87:24] assign out_wivalid_9 = _out_wifireMux_T_168; // @[RegisterRouter.scala:87:24] assign out_wivalid_10 = _out_wifireMux_T_168; // @[RegisterRouter.scala:87:24] assign out_wivalid_11 = _out_wifireMux_T_168; // @[RegisterRouter.scala:87:24] assign out_wivalid_12 = _out_wifireMux_T_168; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_169 = ~_out_T_6; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_171 = _out_wifireMux_T_2 & out_frontSel_42; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_172 = _out_wifireMux_T_171 & _out_T_20; // @[RegisterRouter.scala:87:24] assign out_wivalid_48 = _out_wifireMux_T_172; // @[RegisterRouter.scala:87:24] assign out_wivalid_49 = _out_wifireMux_T_172; // @[RegisterRouter.scala:87:24] assign out_wivalid_50 = _out_wifireMux_T_172; // @[RegisterRouter.scala:87:24] assign out_wivalid_51 = _out_wifireMux_T_172; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_173 = ~_out_T_20; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_175 = _out_wifireMux_T_2 & out_frontSel_43; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_176 = _out_wifireMux_T_175 & _out_T_58; // @[RegisterRouter.scala:87:24] assign out_wivalid_132 = _out_wifireMux_T_176; // @[RegisterRouter.scala:87:24] assign out_wivalid_133 = _out_wifireMux_T_176; // @[RegisterRouter.scala:87:24] assign out_wivalid_134 = _out_wifireMux_T_176; // @[RegisterRouter.scala:87:24] assign out_wivalid_135 = _out_wifireMux_T_176; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_177 = ~_out_T_58; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_179 = _out_wifireMux_T_2 & out_frontSel_44; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_180 = _out_wifireMux_T_179 & _out_T_50; // @[RegisterRouter.scala:87:24] assign out_wivalid_116 = _out_wifireMux_T_180; // @[RegisterRouter.scala:87:24] assign out_wivalid_117 = _out_wifireMux_T_180; // @[RegisterRouter.scala:87:24] assign out_wivalid_118 = _out_wifireMux_T_180; // @[RegisterRouter.scala:87:24] assign out_wivalid_119 = _out_wifireMux_T_180; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_181 = ~_out_T_50; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_183 = _out_wifireMux_T_2 & out_frontSel_45; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_184 = _out_wifireMux_T_183 & _out_T_38; // @[RegisterRouter.scala:87:24] assign out_wivalid_77 = _out_wifireMux_T_184; // @[RegisterRouter.scala:87:24] assign out_wivalid_78 = _out_wifireMux_T_184; // @[RegisterRouter.scala:87:24] assign out_wivalid_79 = _out_wifireMux_T_184; // @[RegisterRouter.scala:87:24] assign out_wivalid_80 = _out_wifireMux_T_184; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_185 = ~_out_T_38; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_187 = _out_wifireMux_T_2 & out_frontSel_46; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_188 = _out_wifireMux_T_187 & _out_T_26; // @[RegisterRouter.scala:87:24] assign out_wivalid_59 = _out_wifireMux_T_188; // @[RegisterRouter.scala:87:24] assign out_wivalid_60 = _out_wifireMux_T_188; // @[RegisterRouter.scala:87:24] assign out_wivalid_61 = _out_wifireMux_T_188; // @[RegisterRouter.scala:87:24] assign out_wivalid_62 = _out_wifireMux_T_188; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_189 = ~_out_T_26; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_191 = _out_wifireMux_T_2 & out_frontSel_47; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_192 = _out_wifireMux_T_191 & _out_T_14; // @[RegisterRouter.scala:87:24] assign out_wivalid_25 = _out_wifireMux_T_192; // @[RegisterRouter.scala:87:24] assign out_wivalid_26 = _out_wifireMux_T_192; // @[RegisterRouter.scala:87:24] assign out_wivalid_27 = _out_wifireMux_T_192; // @[RegisterRouter.scala:87:24] assign out_wivalid_28 = _out_wifireMux_T_192; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_193 = ~_out_T_14; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_195 = _out_wifireMux_T_2 & out_frontSel_48; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_196 = _out_wifireMux_T_195; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_199 = _out_wifireMux_T_2 & out_frontSel_49; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_200 = _out_wifireMux_T_199; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_203 = _out_wifireMux_T_2 & out_frontSel_50; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_204 = _out_wifireMux_T_203; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_207 = _out_wifireMux_T_2 & out_frontSel_51; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_208 = _out_wifireMux_T_207; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_211 = _out_wifireMux_T_2 & out_frontSel_52; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_212 = _out_wifireMux_T_211; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_215 = _out_wifireMux_T_2 & out_frontSel_53; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_216 = _out_wifireMux_T_215; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_219 = _out_wifireMux_T_2 & out_frontSel_54; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_220 = _out_wifireMux_T_219; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_223 = _out_wifireMux_T_2 & out_frontSel_55; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_224 = _out_wifireMux_T_223; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_227 = _out_wifireMux_T_2 & out_frontSel_56; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_228 = _out_wifireMux_T_227 & _out_T_18; // @[RegisterRouter.scala:87:24] assign out_wivalid_33 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_wivalid_34 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_wivalid_35 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_wivalid_36 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_wivalid_37 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_wivalid_38 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_wivalid_39 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_wivalid_40 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_wivalid_41 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_wivalid_42 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_wivalid_43 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_wivalid_44 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_wivalid_45 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_wivalid_46 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_wivalid_47 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_229 = ~_out_T_18; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_231 = _out_wifireMux_T_2 & out_frontSel_57; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_232 = _out_wifireMux_T_231 & _out_T_28; // @[RegisterRouter.scala:87:24] assign out_wivalid_63 = _out_wifireMux_T_232; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_233 = ~_out_T_28; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_235 = _out_wifireMux_T_2 & out_frontSel_58; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_236 = _out_wifireMux_T_235; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_239 = _out_wifireMux_T_2 & out_frontSel_59; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_240 = _out_wifireMux_T_239; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_243 = _out_wifireMux_T_2 & out_frontSel_60; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_244 = _out_wifireMux_T_243 & _out_T_32; // @[RegisterRouter.scala:87:24] assign out_wivalid_68 = _out_wifireMux_T_244; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_245 = ~_out_T_32; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_247 = _out_wifireMux_T_2 & out_frontSel_61; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_248 = _out_wifireMux_T_247 & _out_T_2; // @[RegisterRouter.scala:87:24] assign out_wivalid_4 = _out_wifireMux_T_248; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_249 = ~_out_T_2; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_251 = _out_wifireMux_T_2 & out_frontSel_62; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_252 = _out_wifireMux_T_251; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_255 = _out_wifireMux_T_2 & out_frontSel_63; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_256 = _out_wifireMux_T_255; // @[RegisterRouter.scala:87:24] wire _GEN_12 = out_front_valid & out_ready; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T = _GEN_12; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T = _GEN_12; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1 = _out_rofireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_2 = _out_rofireMux_T_1 & out_backSel_0; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_3 = _out_rofireMux_T_2 & _out_T_41; // @[RegisterRouter.scala:87:24] assign out_roready_81 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_4 = ~_out_T_41; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_6 = _out_rofireMux_T_1 & out_backSel_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_7 = _out_rofireMux_T_6; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_10 = _out_rofireMux_T_1 & out_backSel_2; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_11 = _out_rofireMux_T_10; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_14 = _out_rofireMux_T_1 & out_backSel_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_15 = _out_rofireMux_T_14; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_18 = _out_rofireMux_T_1 & out_backSel_4; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_19 = _out_rofireMux_T_18 & _out_T_13; // @[RegisterRouter.scala:87:24] assign out_roready_21 = _out_rofireMux_T_19; // @[RegisterRouter.scala:87:24] assign out_roready_22 = _out_rofireMux_T_19; // @[RegisterRouter.scala:87:24] assign out_roready_23 = _out_rofireMux_T_19; // @[RegisterRouter.scala:87:24] assign out_roready_24 = _out_rofireMux_T_19; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_20 = ~_out_T_13; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_22 = _out_rofireMux_T_1 & out_backSel_5; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_23 = _out_rofireMux_T_22 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_roready_0 = _out_rofireMux_T_23; // @[RegisterRouter.scala:87:24] assign out_roready_1 = _out_rofireMux_T_23; // @[RegisterRouter.scala:87:24] assign out_roready_2 = _out_rofireMux_T_23; // @[RegisterRouter.scala:87:24] assign out_roready_3 = _out_rofireMux_T_23; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_24 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_26 = _out_rofireMux_T_1 & out_backSel_6; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_27 = _out_rofireMux_T_26 & _out_T_31; // @[RegisterRouter.scala:87:24] assign out_roready_64 = _out_rofireMux_T_27; // @[RegisterRouter.scala:87:24] assign out_roready_65 = _out_rofireMux_T_27; // @[RegisterRouter.scala:87:24] assign out_roready_66 = _out_rofireMux_T_27; // @[RegisterRouter.scala:87:24] assign out_roready_67 = _out_rofireMux_T_27; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_28 = ~_out_T_31; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_30 = _out_rofireMux_T_1 & out_backSel_7; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_31 = _out_rofireMux_T_30 & _out_T_53; // @[RegisterRouter.scala:87:24] assign out_roready_120 = _out_rofireMux_T_31; // @[RegisterRouter.scala:87:24] assign out_roready_121 = _out_rofireMux_T_31; // @[RegisterRouter.scala:87:24] assign out_roready_122 = _out_rofireMux_T_31; // @[RegisterRouter.scala:87:24] assign out_roready_123 = _out_rofireMux_T_31; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_32 = ~_out_T_53; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_34 = _out_rofireMux_T_1 & out_backSel_8; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_35 = _out_rofireMux_T_34 & _out_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_17 = _out_rofireMux_T_35; // @[RegisterRouter.scala:87:24] assign out_roready_18 = _out_rofireMux_T_35; // @[RegisterRouter.scala:87:24] assign out_roready_19 = _out_rofireMux_T_35; // @[RegisterRouter.scala:87:24] assign out_roready_20 = _out_rofireMux_T_35; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_36 = ~_out_T_11; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_38 = _out_rofireMux_T_1 & out_backSel_9; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_39 = _out_rofireMux_T_38 & _out_T_5; // @[RegisterRouter.scala:87:24] assign out_roready_5 = _out_rofireMux_T_39; // @[RegisterRouter.scala:87:24] assign out_roready_6 = _out_rofireMux_T_39; // @[RegisterRouter.scala:87:24] assign out_roready_7 = _out_rofireMux_T_39; // @[RegisterRouter.scala:87:24] assign out_roready_8 = _out_rofireMux_T_39; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_40 = ~_out_T_5; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_42 = _out_rofireMux_T_1 & out_backSel_10; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_43 = _out_rofireMux_T_42 & _out_T_17; // @[RegisterRouter.scala:87:24] assign out_roready_29 = _out_rofireMux_T_43; // @[RegisterRouter.scala:87:24] assign out_roready_30 = _out_rofireMux_T_43; // @[RegisterRouter.scala:87:24] assign out_roready_31 = _out_rofireMux_T_43; // @[RegisterRouter.scala:87:24] assign out_roready_32 = _out_rofireMux_T_43; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_44 = ~_out_T_17; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_46 = _out_rofireMux_T_1 & out_backSel_11; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_47 = _out_rofireMux_T_46 & _out_T_57; // @[RegisterRouter.scala:87:24] assign out_roready_128 = _out_rofireMux_T_47; // @[RegisterRouter.scala:87:24] assign out_roready_129 = _out_rofireMux_T_47; // @[RegisterRouter.scala:87:24] assign out_roready_130 = _out_rofireMux_T_47; // @[RegisterRouter.scala:87:24] assign out_roready_131 = _out_rofireMux_T_47; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_48 = ~_out_T_57; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_50 = _out_rofireMux_T_1 & out_backSel_12; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_51 = _out_rofireMux_T_50; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_54 = _out_rofireMux_T_1 & out_backSel_13; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_55 = _out_rofireMux_T_54; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_58 = _out_rofireMux_T_1 & out_backSel_14; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_59 = _out_rofireMux_T_58; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_62 = _out_rofireMux_T_1 & out_backSel_15; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_63 = _out_rofireMux_T_62; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_66 = _out_rofireMux_T_1 & out_backSel_16; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_67 = _out_rofireMux_T_66; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_70 = _out_rofireMux_T_1 & out_backSel_17; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_71 = _out_rofireMux_T_70 & _out_T_43; // @[RegisterRouter.scala:87:24] assign out_roready_82 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_roready_83 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_roready_84 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_roready_85 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_roready_86 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_roready_87 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_roready_88 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_roready_89 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_roready_90 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_roready_91 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_roready_92 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_roready_93 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_roready_94 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_roready_95 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_roready_96 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_roready_97 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_roready_98 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_roready_99 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_roready_100 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_72 = ~_out_T_43; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_74 = _out_rofireMux_T_1 & out_backSel_18; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_75 = _out_rofireMux_T_74; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_78 = _out_rofireMux_T_1 & out_backSel_19; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_79 = _out_rofireMux_T_78 & _out_T_67; // @[RegisterRouter.scala:87:24] assign out_roready_145 = _out_rofireMux_T_79; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_80 = ~_out_T_67; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_82 = _out_rofireMux_T_1 & out_backSel_20; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_83 = _out_rofireMux_T_82; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_86 = _out_rofireMux_T_1 & out_backSel_21; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_87 = _out_rofireMux_T_86; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_90 = _out_rofireMux_T_1 & out_backSel_22; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_91 = _out_rofireMux_T_90 & _out_T_49; // @[RegisterRouter.scala:87:24] assign out_roready_109 = _out_rofireMux_T_91; // @[RegisterRouter.scala:87:24] assign out_roready_110 = _out_rofireMux_T_91; // @[RegisterRouter.scala:87:24] assign out_roready_111 = _out_rofireMux_T_91; // @[RegisterRouter.scala:87:24] assign out_roready_112 = _out_rofireMux_T_91; // @[RegisterRouter.scala:87:24] assign out_roready_113 = _out_rofireMux_T_91; // @[RegisterRouter.scala:87:24] assign out_roready_114 = _out_rofireMux_T_91; // @[RegisterRouter.scala:87:24] assign out_roready_115 = _out_rofireMux_T_91; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_92 = ~_out_T_49; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_94 = _out_rofireMux_T_1 & out_backSel_23; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_95 = _out_rofireMux_T_94 & _out_T_63; // @[RegisterRouter.scala:87:24] assign out_roready_140 = _out_rofireMux_T_95; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_96 = ~_out_T_63; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_98 = _out_rofireMux_T_1 & out_backSel_24; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_99 = _out_rofireMux_T_98 & _out_T_23; // @[RegisterRouter.scala:87:24] assign out_roready_52 = _out_rofireMux_T_99; // @[RegisterRouter.scala:87:24] assign out_roready_53 = _out_rofireMux_T_99; // @[RegisterRouter.scala:87:24] assign out_roready_54 = _out_rofireMux_T_99; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_100 = ~_out_T_23; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_102 = _out_rofireMux_T_1 & out_backSel_25; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_103 = _out_rofireMux_T_102; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_106 = _out_rofireMux_T_1 & out_backSel_26; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_107 = _out_rofireMux_T_106; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_110 = _out_rofireMux_T_1 & out_backSel_27; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_111 = _out_rofireMux_T_110; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_114 = _out_rofireMux_T_1 & out_backSel_28; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_115 = _out_rofireMux_T_114; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_118 = _out_rofireMux_T_1 & out_backSel_29; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_119 = _out_rofireMux_T_118; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_122 = _out_rofireMux_T_1 & out_backSel_30; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_123 = _out_rofireMux_T_122; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_126 = _out_rofireMux_T_1 & out_backSel_31; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_127 = _out_rofireMux_T_126; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_130 = _out_rofireMux_T_1 & out_backSel_32; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_131 = _out_rofireMux_T_130 & _out_T_45; // @[RegisterRouter.scala:87:24] assign out_roready_101 = _out_rofireMux_T_131; // @[RegisterRouter.scala:87:24] assign out_roready_102 = _out_rofireMux_T_131; // @[RegisterRouter.scala:87:24] assign out_roready_103 = _out_rofireMux_T_131; // @[RegisterRouter.scala:87:24] assign out_roready_104 = _out_rofireMux_T_131; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_132 = ~_out_T_45; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_134 = _out_rofireMux_T_1 & out_backSel_33; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_135 = _out_rofireMux_T_134 & _out_T_37; // @[RegisterRouter.scala:87:24] assign out_roready_73 = _out_rofireMux_T_135; // @[RegisterRouter.scala:87:24] assign out_roready_74 = _out_rofireMux_T_135; // @[RegisterRouter.scala:87:24] assign out_roready_75 = _out_rofireMux_T_135; // @[RegisterRouter.scala:87:24] assign out_roready_76 = _out_rofireMux_T_135; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_136 = ~_out_T_37; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_138 = _out_rofireMux_T_1 & out_backSel_34; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_139 = _out_rofireMux_T_138 & _out_T_47; // @[RegisterRouter.scala:87:24] assign out_roready_105 = _out_rofireMux_T_139; // @[RegisterRouter.scala:87:24] assign out_roready_106 = _out_rofireMux_T_139; // @[RegisterRouter.scala:87:24] assign out_roready_107 = _out_rofireMux_T_139; // @[RegisterRouter.scala:87:24] assign out_roready_108 = _out_rofireMux_T_139; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_140 = ~_out_T_47; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_142 = _out_rofireMux_T_1 & out_backSel_35; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_143 = _out_rofireMux_T_142 & _out_T_9; // @[RegisterRouter.scala:87:24] assign out_roready_13 = _out_rofireMux_T_143; // @[RegisterRouter.scala:87:24] assign out_roready_14 = _out_rofireMux_T_143; // @[RegisterRouter.scala:87:24] assign out_roready_15 = _out_rofireMux_T_143; // @[RegisterRouter.scala:87:24] assign out_roready_16 = _out_rofireMux_T_143; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_144 = ~_out_T_9; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_146 = _out_rofireMux_T_1 & out_backSel_36; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_147 = _out_rofireMux_T_146 & _out_T_65; // @[RegisterRouter.scala:87:24] assign out_roready_141 = _out_rofireMux_T_147; // @[RegisterRouter.scala:87:24] assign out_roready_142 = _out_rofireMux_T_147; // @[RegisterRouter.scala:87:24] assign out_roready_143 = _out_rofireMux_T_147; // @[RegisterRouter.scala:87:24] assign out_roready_144 = _out_rofireMux_T_147; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_148 = ~_out_T_65; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_150 = _out_rofireMux_T_1 & out_backSel_37; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_151 = _out_rofireMux_T_150 & _out_T_25; // @[RegisterRouter.scala:87:24] assign out_roready_55 = _out_rofireMux_T_151; // @[RegisterRouter.scala:87:24] assign out_roready_56 = _out_rofireMux_T_151; // @[RegisterRouter.scala:87:24] assign out_roready_57 = _out_rofireMux_T_151; // @[RegisterRouter.scala:87:24] assign out_roready_58 = _out_rofireMux_T_151; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_152 = ~_out_T_25; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_154 = _out_rofireMux_T_1 & out_backSel_38; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_155 = _out_rofireMux_T_154 & _out_T_35; // @[RegisterRouter.scala:87:24] assign out_roready_69 = _out_rofireMux_T_155; // @[RegisterRouter.scala:87:24] assign out_roready_70 = _out_rofireMux_T_155; // @[RegisterRouter.scala:87:24] assign out_roready_71 = _out_rofireMux_T_155; // @[RegisterRouter.scala:87:24] assign out_roready_72 = _out_rofireMux_T_155; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_156 = ~_out_T_35; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_158 = _out_rofireMux_T_1 & out_backSel_39; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_159 = _out_rofireMux_T_158 & _out_T_55; // @[RegisterRouter.scala:87:24] assign out_roready_124 = _out_rofireMux_T_159; // @[RegisterRouter.scala:87:24] assign out_roready_125 = _out_rofireMux_T_159; // @[RegisterRouter.scala:87:24] assign out_roready_126 = _out_rofireMux_T_159; // @[RegisterRouter.scala:87:24] assign out_roready_127 = _out_rofireMux_T_159; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_160 = ~_out_T_55; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_162 = _out_rofireMux_T_1 & out_backSel_40; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_163 = _out_rofireMux_T_162 & _out_T_61; // @[RegisterRouter.scala:87:24] assign out_roready_136 = _out_rofireMux_T_163; // @[RegisterRouter.scala:87:24] assign out_roready_137 = _out_rofireMux_T_163; // @[RegisterRouter.scala:87:24] assign out_roready_138 = _out_rofireMux_T_163; // @[RegisterRouter.scala:87:24] assign out_roready_139 = _out_rofireMux_T_163; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_164 = ~_out_T_61; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_166 = _out_rofireMux_T_1 & out_backSel_41; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_167 = _out_rofireMux_T_166 & _out_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_9 = _out_rofireMux_T_167; // @[RegisterRouter.scala:87:24] assign out_roready_10 = _out_rofireMux_T_167; // @[RegisterRouter.scala:87:24] assign out_roready_11 = _out_rofireMux_T_167; // @[RegisterRouter.scala:87:24] assign out_roready_12 = _out_rofireMux_T_167; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_168 = ~_out_T_7; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_170 = _out_rofireMux_T_1 & out_backSel_42; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_171 = _out_rofireMux_T_170 & _out_T_21; // @[RegisterRouter.scala:87:24] assign out_roready_48 = _out_rofireMux_T_171; // @[RegisterRouter.scala:87:24] assign out_roready_49 = _out_rofireMux_T_171; // @[RegisterRouter.scala:87:24] assign out_roready_50 = _out_rofireMux_T_171; // @[RegisterRouter.scala:87:24] assign out_roready_51 = _out_rofireMux_T_171; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_172 = ~_out_T_21; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_174 = _out_rofireMux_T_1 & out_backSel_43; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_175 = _out_rofireMux_T_174 & _out_T_59; // @[RegisterRouter.scala:87:24] assign out_roready_132 = _out_rofireMux_T_175; // @[RegisterRouter.scala:87:24] assign out_roready_133 = _out_rofireMux_T_175; // @[RegisterRouter.scala:87:24] assign out_roready_134 = _out_rofireMux_T_175; // @[RegisterRouter.scala:87:24] assign out_roready_135 = _out_rofireMux_T_175; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_176 = ~_out_T_59; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_178 = _out_rofireMux_T_1 & out_backSel_44; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_179 = _out_rofireMux_T_178 & _out_T_51; // @[RegisterRouter.scala:87:24] assign out_roready_116 = _out_rofireMux_T_179; // @[RegisterRouter.scala:87:24] assign out_roready_117 = _out_rofireMux_T_179; // @[RegisterRouter.scala:87:24] assign out_roready_118 = _out_rofireMux_T_179; // @[RegisterRouter.scala:87:24] assign out_roready_119 = _out_rofireMux_T_179; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_180 = ~_out_T_51; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_182 = _out_rofireMux_T_1 & out_backSel_45; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_183 = _out_rofireMux_T_182 & _out_T_39; // @[RegisterRouter.scala:87:24] assign out_roready_77 = _out_rofireMux_T_183; // @[RegisterRouter.scala:87:24] assign out_roready_78 = _out_rofireMux_T_183; // @[RegisterRouter.scala:87:24] assign out_roready_79 = _out_rofireMux_T_183; // @[RegisterRouter.scala:87:24] assign out_roready_80 = _out_rofireMux_T_183; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_184 = ~_out_T_39; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_186 = _out_rofireMux_T_1 & out_backSel_46; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_187 = _out_rofireMux_T_186 & _out_T_27; // @[RegisterRouter.scala:87:24] assign out_roready_59 = _out_rofireMux_T_187; // @[RegisterRouter.scala:87:24] assign out_roready_60 = _out_rofireMux_T_187; // @[RegisterRouter.scala:87:24] assign out_roready_61 = _out_rofireMux_T_187; // @[RegisterRouter.scala:87:24] assign out_roready_62 = _out_rofireMux_T_187; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_188 = ~_out_T_27; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_190 = _out_rofireMux_T_1 & out_backSel_47; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_191 = _out_rofireMux_T_190 & _out_T_15; // @[RegisterRouter.scala:87:24] assign out_roready_25 = _out_rofireMux_T_191; // @[RegisterRouter.scala:87:24] assign out_roready_26 = _out_rofireMux_T_191; // @[RegisterRouter.scala:87:24] assign out_roready_27 = _out_rofireMux_T_191; // @[RegisterRouter.scala:87:24] assign out_roready_28 = _out_rofireMux_T_191; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_192 = ~_out_T_15; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_194 = _out_rofireMux_T_1 & out_backSel_48; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_195 = _out_rofireMux_T_194; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_198 = _out_rofireMux_T_1 & out_backSel_49; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_199 = _out_rofireMux_T_198; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_202 = _out_rofireMux_T_1 & out_backSel_50; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_203 = _out_rofireMux_T_202; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_206 = _out_rofireMux_T_1 & out_backSel_51; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_207 = _out_rofireMux_T_206; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_210 = _out_rofireMux_T_1 & out_backSel_52; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_211 = _out_rofireMux_T_210; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_214 = _out_rofireMux_T_1 & out_backSel_53; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_215 = _out_rofireMux_T_214; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_218 = _out_rofireMux_T_1 & out_backSel_54; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_219 = _out_rofireMux_T_218; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_222 = _out_rofireMux_T_1 & out_backSel_55; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_223 = _out_rofireMux_T_222; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_226 = _out_rofireMux_T_1 & out_backSel_56; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_227 = _out_rofireMux_T_226 & _out_T_19; // @[RegisterRouter.scala:87:24] assign out_roready_33 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_roready_34 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_roready_35 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_roready_36 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_roready_37 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_roready_38 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_roready_39 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_roready_40 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_roready_41 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_roready_42 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_roready_43 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_roready_44 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_roready_45 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_roready_46 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_roready_47 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_228 = ~_out_T_19; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_230 = _out_rofireMux_T_1 & out_backSel_57; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_231 = _out_rofireMux_T_230 & _out_T_29; // @[RegisterRouter.scala:87:24] assign out_roready_63 = _out_rofireMux_T_231; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_232 = ~_out_T_29; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_234 = _out_rofireMux_T_1 & out_backSel_58; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_235 = _out_rofireMux_T_234; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_238 = _out_rofireMux_T_1 & out_backSel_59; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_239 = _out_rofireMux_T_238; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_242 = _out_rofireMux_T_1 & out_backSel_60; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_243 = _out_rofireMux_T_242 & _out_T_33; // @[RegisterRouter.scala:87:24] assign out_roready_68 = _out_rofireMux_T_243; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_244 = ~_out_T_33; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_246 = _out_rofireMux_T_1 & out_backSel_61; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_247 = _out_rofireMux_T_246 & _out_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_4 = _out_rofireMux_T_247; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_248 = ~_out_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_250 = _out_rofireMux_T_1 & out_backSel_62; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_251 = _out_rofireMux_T_250; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_254 = _out_rofireMux_T_1 & out_backSel_63; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_255 = _out_rofireMux_T_254; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_2 = _out_wofireMux_T & _out_wofireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_3 = _out_wofireMux_T_2 & out_backSel_0; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_4 = _out_wofireMux_T_3 & _out_T_41; // @[RegisterRouter.scala:87:24] assign out_woready_81 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_5 = ~_out_T_41; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_7 = _out_wofireMux_T_2 & out_backSel_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_8 = _out_wofireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_11 = _out_wofireMux_T_2 & out_backSel_2; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_12 = _out_wofireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_15 = _out_wofireMux_T_2 & out_backSel_3; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_16 = _out_wofireMux_T_15; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_19 = _out_wofireMux_T_2 & out_backSel_4; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_20 = _out_wofireMux_T_19 & _out_T_13; // @[RegisterRouter.scala:87:24] assign out_woready_21 = _out_wofireMux_T_20; // @[RegisterRouter.scala:87:24] assign out_woready_22 = _out_wofireMux_T_20; // @[RegisterRouter.scala:87:24] assign out_woready_23 = _out_wofireMux_T_20; // @[RegisterRouter.scala:87:24] assign out_woready_24 = _out_wofireMux_T_20; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_21 = ~_out_T_13; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_23 = _out_wofireMux_T_2 & out_backSel_5; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_24 = _out_wofireMux_T_23 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_woready_0 = _out_wofireMux_T_24; // @[RegisterRouter.scala:87:24] assign out_woready_1 = _out_wofireMux_T_24; // @[RegisterRouter.scala:87:24] assign out_woready_2 = _out_wofireMux_T_24; // @[RegisterRouter.scala:87:24] assign out_woready_3 = _out_wofireMux_T_24; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_25 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_27 = _out_wofireMux_T_2 & out_backSel_6; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_28 = _out_wofireMux_T_27 & _out_T_31; // @[RegisterRouter.scala:87:24] assign out_woready_64 = _out_wofireMux_T_28; // @[RegisterRouter.scala:87:24] assign out_woready_65 = _out_wofireMux_T_28; // @[RegisterRouter.scala:87:24] assign out_woready_66 = _out_wofireMux_T_28; // @[RegisterRouter.scala:87:24] assign out_woready_67 = _out_wofireMux_T_28; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_29 = ~_out_T_31; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_31 = _out_wofireMux_T_2 & out_backSel_7; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_32 = _out_wofireMux_T_31 & _out_T_53; // @[RegisterRouter.scala:87:24] assign out_woready_120 = _out_wofireMux_T_32; // @[RegisterRouter.scala:87:24] assign out_woready_121 = _out_wofireMux_T_32; // @[RegisterRouter.scala:87:24] assign out_woready_122 = _out_wofireMux_T_32; // @[RegisterRouter.scala:87:24] assign out_woready_123 = _out_wofireMux_T_32; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_33 = ~_out_T_53; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_35 = _out_wofireMux_T_2 & out_backSel_8; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_36 = _out_wofireMux_T_35 & _out_T_11; // @[RegisterRouter.scala:87:24] assign out_woready_17 = _out_wofireMux_T_36; // @[RegisterRouter.scala:87:24] assign out_woready_18 = _out_wofireMux_T_36; // @[RegisterRouter.scala:87:24] assign out_woready_19 = _out_wofireMux_T_36; // @[RegisterRouter.scala:87:24] assign out_woready_20 = _out_wofireMux_T_36; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_37 = ~_out_T_11; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_39 = _out_wofireMux_T_2 & out_backSel_9; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_40 = _out_wofireMux_T_39 & _out_T_5; // @[RegisterRouter.scala:87:24] assign out_woready_5 = _out_wofireMux_T_40; // @[RegisterRouter.scala:87:24] assign out_woready_6 = _out_wofireMux_T_40; // @[RegisterRouter.scala:87:24] assign out_woready_7 = _out_wofireMux_T_40; // @[RegisterRouter.scala:87:24] assign out_woready_8 = _out_wofireMux_T_40; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_41 = ~_out_T_5; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_43 = _out_wofireMux_T_2 & out_backSel_10; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_44 = _out_wofireMux_T_43 & _out_T_17; // @[RegisterRouter.scala:87:24] assign out_woready_29 = _out_wofireMux_T_44; // @[RegisterRouter.scala:87:24] assign out_woready_30 = _out_wofireMux_T_44; // @[RegisterRouter.scala:87:24] assign out_woready_31 = _out_wofireMux_T_44; // @[RegisterRouter.scala:87:24] assign out_woready_32 = _out_wofireMux_T_44; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_45 = ~_out_T_17; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_47 = _out_wofireMux_T_2 & out_backSel_11; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_48 = _out_wofireMux_T_47 & _out_T_57; // @[RegisterRouter.scala:87:24] assign out_woready_128 = _out_wofireMux_T_48; // @[RegisterRouter.scala:87:24] assign out_woready_129 = _out_wofireMux_T_48; // @[RegisterRouter.scala:87:24] assign out_woready_130 = _out_wofireMux_T_48; // @[RegisterRouter.scala:87:24] assign out_woready_131 = _out_wofireMux_T_48; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_49 = ~_out_T_57; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_51 = _out_wofireMux_T_2 & out_backSel_12; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_52 = _out_wofireMux_T_51; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_55 = _out_wofireMux_T_2 & out_backSel_13; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_56 = _out_wofireMux_T_55; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_59 = _out_wofireMux_T_2 & out_backSel_14; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_60 = _out_wofireMux_T_59; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_63 = _out_wofireMux_T_2 & out_backSel_15; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_64 = _out_wofireMux_T_63; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_67 = _out_wofireMux_T_2 & out_backSel_16; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_68 = _out_wofireMux_T_67; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_71 = _out_wofireMux_T_2 & out_backSel_17; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_72 = _out_wofireMux_T_71 & _out_T_43; // @[RegisterRouter.scala:87:24] assign out_woready_82 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_woready_83 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_woready_84 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_woready_85 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_woready_86 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_woready_87 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_woready_88 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_woready_89 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_woready_90 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_woready_91 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_woready_92 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_woready_93 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_woready_94 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_woready_95 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_woready_96 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_woready_97 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_woready_98 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_woready_99 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_woready_100 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_73 = ~_out_T_43; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_75 = _out_wofireMux_T_2 & out_backSel_18; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_76 = _out_wofireMux_T_75; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_79 = _out_wofireMux_T_2 & out_backSel_19; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_80 = _out_wofireMux_T_79 & _out_T_67; // @[RegisterRouter.scala:87:24] assign out_woready_145 = _out_wofireMux_T_80; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_81 = ~_out_T_67; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_83 = _out_wofireMux_T_2 & out_backSel_20; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_84 = _out_wofireMux_T_83; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_87 = _out_wofireMux_T_2 & out_backSel_21; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_88 = _out_wofireMux_T_87; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_91 = _out_wofireMux_T_2 & out_backSel_22; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_92 = _out_wofireMux_T_91 & _out_T_49; // @[RegisterRouter.scala:87:24] assign out_woready_109 = _out_wofireMux_T_92; // @[RegisterRouter.scala:87:24] assign out_woready_110 = _out_wofireMux_T_92; // @[RegisterRouter.scala:87:24] assign out_woready_111 = _out_wofireMux_T_92; // @[RegisterRouter.scala:87:24] assign out_woready_112 = _out_wofireMux_T_92; // @[RegisterRouter.scala:87:24] assign out_woready_113 = _out_wofireMux_T_92; // @[RegisterRouter.scala:87:24] assign out_woready_114 = _out_wofireMux_T_92; // @[RegisterRouter.scala:87:24] assign out_woready_115 = _out_wofireMux_T_92; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_93 = ~_out_T_49; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_95 = _out_wofireMux_T_2 & out_backSel_23; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_96 = _out_wofireMux_T_95 & _out_T_63; // @[RegisterRouter.scala:87:24] assign out_woready_140 = _out_wofireMux_T_96; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_97 = ~_out_T_63; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_99 = _out_wofireMux_T_2 & out_backSel_24; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_100 = _out_wofireMux_T_99 & _out_T_23; // @[RegisterRouter.scala:87:24] assign out_woready_52 = _out_wofireMux_T_100; // @[RegisterRouter.scala:87:24] assign out_woready_53 = _out_wofireMux_T_100; // @[RegisterRouter.scala:87:24] assign out_woready_54 = _out_wofireMux_T_100; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_101 = ~_out_T_23; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_103 = _out_wofireMux_T_2 & out_backSel_25; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_104 = _out_wofireMux_T_103; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_107 = _out_wofireMux_T_2 & out_backSel_26; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_108 = _out_wofireMux_T_107; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_111 = _out_wofireMux_T_2 & out_backSel_27; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_112 = _out_wofireMux_T_111; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_115 = _out_wofireMux_T_2 & out_backSel_28; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_116 = _out_wofireMux_T_115; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_119 = _out_wofireMux_T_2 & out_backSel_29; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_120 = _out_wofireMux_T_119; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_123 = _out_wofireMux_T_2 & out_backSel_30; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_124 = _out_wofireMux_T_123; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_127 = _out_wofireMux_T_2 & out_backSel_31; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_128 = _out_wofireMux_T_127; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_131 = _out_wofireMux_T_2 & out_backSel_32; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_132 = _out_wofireMux_T_131 & _out_T_45; // @[RegisterRouter.scala:87:24] assign out_woready_101 = _out_wofireMux_T_132; // @[RegisterRouter.scala:87:24] assign out_woready_102 = _out_wofireMux_T_132; // @[RegisterRouter.scala:87:24] assign out_woready_103 = _out_wofireMux_T_132; // @[RegisterRouter.scala:87:24] assign out_woready_104 = _out_wofireMux_T_132; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_133 = ~_out_T_45; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_135 = _out_wofireMux_T_2 & out_backSel_33; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_136 = _out_wofireMux_T_135 & _out_T_37; // @[RegisterRouter.scala:87:24] assign out_woready_73 = _out_wofireMux_T_136; // @[RegisterRouter.scala:87:24] assign out_woready_74 = _out_wofireMux_T_136; // @[RegisterRouter.scala:87:24] assign out_woready_75 = _out_wofireMux_T_136; // @[RegisterRouter.scala:87:24] assign out_woready_76 = _out_wofireMux_T_136; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_137 = ~_out_T_37; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_139 = _out_wofireMux_T_2 & out_backSel_34; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_140 = _out_wofireMux_T_139 & _out_T_47; // @[RegisterRouter.scala:87:24] assign out_woready_105 = _out_wofireMux_T_140; // @[RegisterRouter.scala:87:24] assign out_woready_106 = _out_wofireMux_T_140; // @[RegisterRouter.scala:87:24] assign out_woready_107 = _out_wofireMux_T_140; // @[RegisterRouter.scala:87:24] assign out_woready_108 = _out_wofireMux_T_140; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_141 = ~_out_T_47; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_143 = _out_wofireMux_T_2 & out_backSel_35; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_144 = _out_wofireMux_T_143 & _out_T_9; // @[RegisterRouter.scala:87:24] assign out_woready_13 = _out_wofireMux_T_144; // @[RegisterRouter.scala:87:24] assign out_woready_14 = _out_wofireMux_T_144; // @[RegisterRouter.scala:87:24] assign out_woready_15 = _out_wofireMux_T_144; // @[RegisterRouter.scala:87:24] assign out_woready_16 = _out_wofireMux_T_144; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_145 = ~_out_T_9; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_147 = _out_wofireMux_T_2 & out_backSel_36; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_148 = _out_wofireMux_T_147 & _out_T_65; // @[RegisterRouter.scala:87:24] assign out_woready_141 = _out_wofireMux_T_148; // @[RegisterRouter.scala:87:24] assign out_woready_142 = _out_wofireMux_T_148; // @[RegisterRouter.scala:87:24] assign out_woready_143 = _out_wofireMux_T_148; // @[RegisterRouter.scala:87:24] assign out_woready_144 = _out_wofireMux_T_148; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_149 = ~_out_T_65; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_151 = _out_wofireMux_T_2 & out_backSel_37; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_152 = _out_wofireMux_T_151 & _out_T_25; // @[RegisterRouter.scala:87:24] assign out_woready_55 = _out_wofireMux_T_152; // @[RegisterRouter.scala:87:24] assign out_woready_56 = _out_wofireMux_T_152; // @[RegisterRouter.scala:87:24] assign out_woready_57 = _out_wofireMux_T_152; // @[RegisterRouter.scala:87:24] assign out_woready_58 = _out_wofireMux_T_152; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_153 = ~_out_T_25; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_155 = _out_wofireMux_T_2 & out_backSel_38; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_156 = _out_wofireMux_T_155 & _out_T_35; // @[RegisterRouter.scala:87:24] assign out_woready_69 = _out_wofireMux_T_156; // @[RegisterRouter.scala:87:24] assign out_woready_70 = _out_wofireMux_T_156; // @[RegisterRouter.scala:87:24] assign out_woready_71 = _out_wofireMux_T_156; // @[RegisterRouter.scala:87:24] assign out_woready_72 = _out_wofireMux_T_156; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_157 = ~_out_T_35; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_159 = _out_wofireMux_T_2 & out_backSel_39; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_160 = _out_wofireMux_T_159 & _out_T_55; // @[RegisterRouter.scala:87:24] assign out_woready_124 = _out_wofireMux_T_160; // @[RegisterRouter.scala:87:24] assign out_woready_125 = _out_wofireMux_T_160; // @[RegisterRouter.scala:87:24] assign out_woready_126 = _out_wofireMux_T_160; // @[RegisterRouter.scala:87:24] assign out_woready_127 = _out_wofireMux_T_160; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_161 = ~_out_T_55; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_163 = _out_wofireMux_T_2 & out_backSel_40; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_164 = _out_wofireMux_T_163 & _out_T_61; // @[RegisterRouter.scala:87:24] assign out_woready_136 = _out_wofireMux_T_164; // @[RegisterRouter.scala:87:24] assign out_woready_137 = _out_wofireMux_T_164; // @[RegisterRouter.scala:87:24] assign out_woready_138 = _out_wofireMux_T_164; // @[RegisterRouter.scala:87:24] assign out_woready_139 = _out_wofireMux_T_164; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_165 = ~_out_T_61; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_167 = _out_wofireMux_T_2 & out_backSel_41; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_168 = _out_wofireMux_T_167 & _out_T_7; // @[RegisterRouter.scala:87:24] assign out_woready_9 = _out_wofireMux_T_168; // @[RegisterRouter.scala:87:24] assign out_woready_10 = _out_wofireMux_T_168; // @[RegisterRouter.scala:87:24] assign out_woready_11 = _out_wofireMux_T_168; // @[RegisterRouter.scala:87:24] assign out_woready_12 = _out_wofireMux_T_168; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_169 = ~_out_T_7; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_171 = _out_wofireMux_T_2 & out_backSel_42; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_172 = _out_wofireMux_T_171 & _out_T_21; // @[RegisterRouter.scala:87:24] assign out_woready_48 = _out_wofireMux_T_172; // @[RegisterRouter.scala:87:24] assign out_woready_49 = _out_wofireMux_T_172; // @[RegisterRouter.scala:87:24] assign out_woready_50 = _out_wofireMux_T_172; // @[RegisterRouter.scala:87:24] assign out_woready_51 = _out_wofireMux_T_172; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_173 = ~_out_T_21; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_175 = _out_wofireMux_T_2 & out_backSel_43; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_176 = _out_wofireMux_T_175 & _out_T_59; // @[RegisterRouter.scala:87:24] assign out_woready_132 = _out_wofireMux_T_176; // @[RegisterRouter.scala:87:24] assign out_woready_133 = _out_wofireMux_T_176; // @[RegisterRouter.scala:87:24] assign out_woready_134 = _out_wofireMux_T_176; // @[RegisterRouter.scala:87:24] assign out_woready_135 = _out_wofireMux_T_176; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_177 = ~_out_T_59; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_179 = _out_wofireMux_T_2 & out_backSel_44; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_180 = _out_wofireMux_T_179 & _out_T_51; // @[RegisterRouter.scala:87:24] assign out_woready_116 = _out_wofireMux_T_180; // @[RegisterRouter.scala:87:24] assign out_woready_117 = _out_wofireMux_T_180; // @[RegisterRouter.scala:87:24] assign out_woready_118 = _out_wofireMux_T_180; // @[RegisterRouter.scala:87:24] assign out_woready_119 = _out_wofireMux_T_180; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_181 = ~_out_T_51; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_183 = _out_wofireMux_T_2 & out_backSel_45; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_184 = _out_wofireMux_T_183 & _out_T_39; // @[RegisterRouter.scala:87:24] assign out_woready_77 = _out_wofireMux_T_184; // @[RegisterRouter.scala:87:24] assign out_woready_78 = _out_wofireMux_T_184; // @[RegisterRouter.scala:87:24] assign out_woready_79 = _out_wofireMux_T_184; // @[RegisterRouter.scala:87:24] assign out_woready_80 = _out_wofireMux_T_184; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_185 = ~_out_T_39; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_187 = _out_wofireMux_T_2 & out_backSel_46; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_188 = _out_wofireMux_T_187 & _out_T_27; // @[RegisterRouter.scala:87:24] assign out_woready_59 = _out_wofireMux_T_188; // @[RegisterRouter.scala:87:24] assign out_woready_60 = _out_wofireMux_T_188; // @[RegisterRouter.scala:87:24] assign out_woready_61 = _out_wofireMux_T_188; // @[RegisterRouter.scala:87:24] assign out_woready_62 = _out_wofireMux_T_188; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_189 = ~_out_T_27; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_191 = _out_wofireMux_T_2 & out_backSel_47; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_192 = _out_wofireMux_T_191 & _out_T_15; // @[RegisterRouter.scala:87:24] assign out_woready_25 = _out_wofireMux_T_192; // @[RegisterRouter.scala:87:24] assign out_woready_26 = _out_wofireMux_T_192; // @[RegisterRouter.scala:87:24] assign out_woready_27 = _out_wofireMux_T_192; // @[RegisterRouter.scala:87:24] assign out_woready_28 = _out_wofireMux_T_192; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_193 = ~_out_T_15; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_195 = _out_wofireMux_T_2 & out_backSel_48; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_196 = _out_wofireMux_T_195; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_199 = _out_wofireMux_T_2 & out_backSel_49; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_200 = _out_wofireMux_T_199; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_203 = _out_wofireMux_T_2 & out_backSel_50; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_204 = _out_wofireMux_T_203; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_207 = _out_wofireMux_T_2 & out_backSel_51; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_208 = _out_wofireMux_T_207; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_211 = _out_wofireMux_T_2 & out_backSel_52; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_212 = _out_wofireMux_T_211; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_215 = _out_wofireMux_T_2 & out_backSel_53; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_216 = _out_wofireMux_T_215; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_219 = _out_wofireMux_T_2 & out_backSel_54; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_220 = _out_wofireMux_T_219; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_223 = _out_wofireMux_T_2 & out_backSel_55; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_224 = _out_wofireMux_T_223; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_227 = _out_wofireMux_T_2 & out_backSel_56; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_228 = _out_wofireMux_T_227 & _out_T_19; // @[RegisterRouter.scala:87:24] assign out_woready_33 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_woready_34 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_woready_35 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_woready_36 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_woready_37 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_woready_38 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_woready_39 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_woready_40 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_woready_41 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_woready_42 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_woready_43 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_woready_44 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_woready_45 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_woready_46 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_woready_47 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_229 = ~_out_T_19; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_231 = _out_wofireMux_T_2 & out_backSel_57; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_232 = _out_wofireMux_T_231 & _out_T_29; // @[RegisterRouter.scala:87:24] assign out_woready_63 = _out_wofireMux_T_232; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_233 = ~_out_T_29; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_235 = _out_wofireMux_T_2 & out_backSel_58; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_236 = _out_wofireMux_T_235; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_239 = _out_wofireMux_T_2 & out_backSel_59; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_240 = _out_wofireMux_T_239; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_243 = _out_wofireMux_T_2 & out_backSel_60; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_244 = _out_wofireMux_T_243 & _out_T_33; // @[RegisterRouter.scala:87:24] assign out_woready_68 = _out_wofireMux_T_244; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_245 = ~_out_T_33; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_247 = _out_wofireMux_T_2 & out_backSel_61; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_248 = _out_wofireMux_T_247 & _out_T_3; // @[RegisterRouter.scala:87:24] assign out_woready_4 = _out_wofireMux_T_248; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_249 = ~_out_T_3; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_251 = _out_wofireMux_T_2 & out_backSel_62; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_252 = _out_wofireMux_T_251; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_255 = _out_wofireMux_T_2 & out_backSel_63; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_256 = _out_wofireMux_T_255; // @[RegisterRouter.scala:87:24] assign in_ready = _out_in_ready_T; // @[RegisterRouter.scala:73:18, :87:24] assign out_front_valid = _out_front_valid_T; // @[RegisterRouter.scala:87:24] assign out_front_ready = _out_front_ready_T; // @[RegisterRouter.scala:87:24] assign out_valid = _out_out_valid_T; // @[RegisterRouter.scala:87:24] wire [63:0] _GEN_13 = {{1'h1}, {1'h1}, {_out_out_bits_data_WIRE_61}, {_out_out_bits_data_WIRE_60}, {1'h1}, {1'h1}, {_out_out_bits_data_WIRE_57}, {_out_out_bits_data_WIRE_56}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {_out_out_bits_data_WIRE_47}, {_out_out_bits_data_WIRE_46}, {_out_out_bits_data_WIRE_45}, {_out_out_bits_data_WIRE_44}, {_out_out_bits_data_WIRE_43}, {_out_out_bits_data_WIRE_42}, {_out_out_bits_data_WIRE_41}, {_out_out_bits_data_WIRE_40}, {_out_out_bits_data_WIRE_39}, {_out_out_bits_data_WIRE_38}, {_out_out_bits_data_WIRE_37}, {_out_out_bits_data_WIRE_36}, {_out_out_bits_data_WIRE_35}, {_out_out_bits_data_WIRE_34}, {_out_out_bits_data_WIRE_33}, {_out_out_bits_data_WIRE_32}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {_out_out_bits_data_WIRE_24}, {_out_out_bits_data_WIRE_23}, {_out_out_bits_data_WIRE_22}, {1'h1}, {1'h1}, {_out_out_bits_data_WIRE_19}, {1'h1}, {_out_out_bits_data_WIRE_17}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {_out_out_bits_data_WIRE_11}, {_out_out_bits_data_WIRE_10}, {_out_out_bits_data_WIRE_9}, {_out_out_bits_data_WIRE_8}, {_out_out_bits_data_WIRE_7}, {_out_out_bits_data_WIRE_6}, {_out_out_bits_data_WIRE_5}, {_out_out_bits_data_WIRE_4}, {1'h1}, {1'h1}, {1'h1}, {_out_out_bits_data_WIRE_0}}; // @[MuxLiteral.scala:49:{10,48}] wire _out_out_bits_data_T_1 = _GEN_13[out_oindex]; // @[MuxLiteral.scala:49:10] wire [31:0] _out_out_bits_data_WIRE_1_17 = {9'h0, _out_T_1118}; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_22 = {3'h0, _out_T_1271}; // @[MuxLiteral.scala:49:48] wire [63:0][31:0] _GEN_14 = {{32'h0}, {32'h0}, {_out_out_bits_data_WIRE_1_61}, {_out_out_bits_data_WIRE_1_60}, {32'h0}, {32'h0}, {_out_out_bits_data_WIRE_1_57}, {_out_out_bits_data_WIRE_1_56}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {_out_out_bits_data_WIRE_1_47}, {_out_out_bits_data_WIRE_1_46}, {_out_out_bits_data_WIRE_1_45}, {_out_out_bits_data_WIRE_1_44}, {_out_out_bits_data_WIRE_1_43}, {_out_out_bits_data_WIRE_1_42}, {_out_out_bits_data_WIRE_1_41}, {_out_out_bits_data_WIRE_1_40}, {_out_out_bits_data_WIRE_1_39}, {_out_out_bits_data_WIRE_1_38}, {_out_out_bits_data_WIRE_1_37}, {_out_out_bits_data_WIRE_1_36}, {_out_out_bits_data_WIRE_1_35}, {_out_out_bits_data_WIRE_1_34}, {_out_out_bits_data_WIRE_1_33}, {_out_out_bits_data_WIRE_1_32}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {_out_out_bits_data_WIRE_1_24}, {_out_out_bits_data_WIRE_1_23}, {_out_out_bits_data_WIRE_1_22}, {32'h0}, {32'h0}, {_out_out_bits_data_WIRE_1_19}, {32'h0}, {_out_out_bits_data_WIRE_1_17}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {_out_out_bits_data_WIRE_1_11}, {_out_out_bits_data_WIRE_1_10}, {_out_out_bits_data_WIRE_1_9}, {_out_out_bits_data_WIRE_1_8}, {_out_out_bits_data_WIRE_1_7}, {_out_out_bits_data_WIRE_1_6}, {_out_out_bits_data_WIRE_1_5}, {_out_out_bits_data_WIRE_1_4}, {32'h0}, {32'h0}, {32'h0}, {_out_out_bits_data_WIRE_1_0}}; // @[MuxLiteral.scala:49:{10,48}] wire [31:0] _out_out_bits_data_T_3 = _GEN_14[out_oindex]; // @[MuxLiteral.scala:49:10] assign _out_out_bits_data_T_4 = _out_out_bits_data_T_1 ? _out_out_bits_data_T_3 : 32'h0; // @[MuxLiteral.scala:49:10] assign out_bits_data = _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24] assign dmiNodeIn_d_bits_size = dmiNodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign dmiNodeIn_d_bits_source = dmiNodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign dmiNodeIn_d_bits_opcode = {2'h0, _dmiNodeIn_d_bits_opcode_T}; // @[RegisterRouter.scala:105:{19,25}] reg goReg; // @[Debug.scala:1494:27] wire flags_0_go = goReg; // @[Debug.scala:1494:27, :1517:25] wire goAbstract; // @[Debug.scala:1495:32] wire goCustom; // @[Debug.scala:1496:32] wire flags_0_resume; // @[Debug.scala:1517:25] assign flags_0_resume = _flags_resume_T; // @[Debug.scala:1517:25, :1524:80] wire [31:0] _accessRegisterCommandWr_T = {COMMANDWrData_cmdtype, COMMANDWrData_control}; // @[Debug.scala:1280:39, :1531:59] wire [31:0] _accessRegisterCommandWr_WIRE_1 = _accessRegisterCommandWr_T; // @[Debug.scala:1531:{59,74}] wire [7:0] _accessRegisterCommandWr_T_8; // @[Debug.scala:1531:74] wire _accessRegisterCommandWr_T_7; // @[Debug.scala:1531:74] wire [7:0] accessRegisterCommandWr_cmdtype = _accessRegisterCommandWr_WIRE_cmdtype; // @[Debug.scala:1531:{44,74}] wire [2:0] _accessRegisterCommandWr_T_6; // @[Debug.scala:1531:74] wire accessRegisterCommandWr_reserved0 = _accessRegisterCommandWr_WIRE_reserved0; // @[Debug.scala:1531:{44,74}] wire _accessRegisterCommandWr_T_5; // @[Debug.scala:1531:74] wire [2:0] accessRegisterCommandWr_size = _accessRegisterCommandWr_WIRE_size; // @[Debug.scala:1531:{44,74}] wire _accessRegisterCommandWr_T_4; // @[Debug.scala:1531:74] wire accessRegisterCommandWr_reserved1 = _accessRegisterCommandWr_WIRE_reserved1; // @[Debug.scala:1531:{44,74}] wire _accessRegisterCommandWr_T_3; // @[Debug.scala:1531:74] wire accessRegisterCommandWr_postexec = _accessRegisterCommandWr_WIRE_postexec; // @[Debug.scala:1531:{44,74}] wire _accessRegisterCommandWr_T_2; // @[Debug.scala:1531:74] wire accessRegisterCommandWr_transfer = _accessRegisterCommandWr_WIRE_transfer; // @[Debug.scala:1531:{44,74}] wire [15:0] _accessRegisterCommandWr_T_1; // @[Debug.scala:1531:74] wire accessRegisterCommandWr_write = _accessRegisterCommandWr_WIRE_write; // @[Debug.scala:1531:{44,74}] wire [15:0] accessRegisterCommandWr_regno = _accessRegisterCommandWr_WIRE_regno; // @[Debug.scala:1531:{44,74}] assign _accessRegisterCommandWr_T_1 = _accessRegisterCommandWr_WIRE_1[15:0]; // @[Debug.scala:1531:74] assign _accessRegisterCommandWr_WIRE_regno = _accessRegisterCommandWr_T_1; // @[Debug.scala:1531:74] assign _accessRegisterCommandWr_T_2 = _accessRegisterCommandWr_WIRE_1[16]; // @[Debug.scala:1531:74] assign _accessRegisterCommandWr_WIRE_write = _accessRegisterCommandWr_T_2; // @[Debug.scala:1531:74] assign _accessRegisterCommandWr_T_3 = _accessRegisterCommandWr_WIRE_1[17]; // @[Debug.scala:1531:74] assign _accessRegisterCommandWr_WIRE_transfer = _accessRegisterCommandWr_T_3; // @[Debug.scala:1531:74] assign _accessRegisterCommandWr_T_4 = _accessRegisterCommandWr_WIRE_1[18]; // @[Debug.scala:1531:74] assign _accessRegisterCommandWr_WIRE_postexec = _accessRegisterCommandWr_T_4; // @[Debug.scala:1531:74] assign _accessRegisterCommandWr_T_5 = _accessRegisterCommandWr_WIRE_1[19]; // @[Debug.scala:1531:74] assign _accessRegisterCommandWr_WIRE_reserved1 = _accessRegisterCommandWr_T_5; // @[Debug.scala:1531:74] assign _accessRegisterCommandWr_T_6 = _accessRegisterCommandWr_WIRE_1[22:20]; // @[Debug.scala:1531:74] assign _accessRegisterCommandWr_WIRE_size = _accessRegisterCommandWr_T_6; // @[Debug.scala:1531:74] assign _accessRegisterCommandWr_T_7 = _accessRegisterCommandWr_WIRE_1[23]; // @[Debug.scala:1531:74] assign _accessRegisterCommandWr_WIRE_reserved0 = _accessRegisterCommandWr_T_7; // @[Debug.scala:1531:74] assign _accessRegisterCommandWr_T_8 = _accessRegisterCommandWr_WIRE_1[31:24]; // @[Debug.scala:1531:74] assign _accessRegisterCommandWr_WIRE_cmdtype = _accessRegisterCommandWr_T_8; // @[Debug.scala:1531:74] wire [31:0] _accessRegisterCommandReg_WIRE_1 = _accessRegisterCommandReg_T; // @[Debug.scala:1533:{56,71}] wire [7:0] _accessRegisterCommandReg_T_8; // @[Debug.scala:1533:71] wire _accessRegisterCommandReg_T_7; // @[Debug.scala:1533:71] wire [7:0] accessRegisterCommandReg_cmdtype = _accessRegisterCommandReg_WIRE_cmdtype; // @[Debug.scala:1533:{44,71}] wire [2:0] _accessRegisterCommandReg_T_6; // @[Debug.scala:1533:71] wire accessRegisterCommandReg_reserved0 = _accessRegisterCommandReg_WIRE_reserved0; // @[Debug.scala:1533:{44,71}] wire _accessRegisterCommandReg_T_5; // @[Debug.scala:1533:71] wire [2:0] accessRegisterCommandReg_size = _accessRegisterCommandReg_WIRE_size; // @[Debug.scala:1533:{44,71}] wire _accessRegisterCommandReg_T_4; // @[Debug.scala:1533:71] wire accessRegisterCommandReg_reserved1 = _accessRegisterCommandReg_WIRE_reserved1; // @[Debug.scala:1533:{44,71}] wire _accessRegisterCommandReg_T_3; // @[Debug.scala:1533:71] wire accessRegisterCommandReg_postexec = _accessRegisterCommandReg_WIRE_postexec; // @[Debug.scala:1533:{44,71}] wire _accessRegisterCommandReg_T_2; // @[Debug.scala:1533:71] wire accessRegisterCommandReg_transfer = _accessRegisterCommandReg_WIRE_transfer; // @[Debug.scala:1533:{44,71}] wire [15:0] _accessRegisterCommandReg_T_1; // @[Debug.scala:1533:71] wire accessRegisterCommandReg_write = _accessRegisterCommandReg_WIRE_write; // @[Debug.scala:1533:{44,71}] wire [15:0] accessRegisterCommandReg_regno = _accessRegisterCommandReg_WIRE_regno; // @[Debug.scala:1533:{44,71}] assign _accessRegisterCommandReg_T_1 = _accessRegisterCommandReg_WIRE_1[15:0]; // @[Debug.scala:1533:71] assign _accessRegisterCommandReg_WIRE_regno = _accessRegisterCommandReg_T_1; // @[Debug.scala:1533:71] assign _accessRegisterCommandReg_T_2 = _accessRegisterCommandReg_WIRE_1[16]; // @[Debug.scala:1533:71] assign _accessRegisterCommandReg_WIRE_write = _accessRegisterCommandReg_T_2; // @[Debug.scala:1533:71] assign _accessRegisterCommandReg_T_3 = _accessRegisterCommandReg_WIRE_1[17]; // @[Debug.scala:1533:71] assign _accessRegisterCommandReg_WIRE_transfer = _accessRegisterCommandReg_T_3; // @[Debug.scala:1533:71] assign _accessRegisterCommandReg_T_4 = _accessRegisterCommandReg_WIRE_1[18]; // @[Debug.scala:1533:71] assign _accessRegisterCommandReg_WIRE_postexec = _accessRegisterCommandReg_T_4; // @[Debug.scala:1533:71] assign _accessRegisterCommandReg_T_5 = _accessRegisterCommandReg_WIRE_1[19]; // @[Debug.scala:1533:71] assign _accessRegisterCommandReg_WIRE_reserved1 = _accessRegisterCommandReg_T_5; // @[Debug.scala:1533:71] assign _accessRegisterCommandReg_T_6 = _accessRegisterCommandReg_WIRE_1[22:20]; // @[Debug.scala:1533:71] assign _accessRegisterCommandReg_WIRE_size = _accessRegisterCommandReg_T_6; // @[Debug.scala:1533:71] assign _accessRegisterCommandReg_T_7 = _accessRegisterCommandReg_WIRE_1[23]; // @[Debug.scala:1533:71] assign _accessRegisterCommandReg_WIRE_reserved0 = _accessRegisterCommandReg_T_7; // @[Debug.scala:1533:71] assign _accessRegisterCommandReg_T_8 = _accessRegisterCommandReg_WIRE_1[31:24]; // @[Debug.scala:1533:71] assign _accessRegisterCommandReg_WIRE_cmdtype = _accessRegisterCommandReg_T_8; // @[Debug.scala:1533:71] wire [2:0] abstractGeneratedMem_0_inst_funct3 = accessRegisterCommandReg_size; // @[Debug.scala:1533:44, :1589:22] wire [2:0] abstractGeneratedMem_0_inst_1_funct3 = accessRegisterCommandReg_size; // @[Debug.scala:1533:44, :1601:22] reg [31:0] abstractGeneratedMem_0; // @[Debug.scala:1586:35] wire [31:0] _out_T_8286 = abstractGeneratedMem_0; // @[RegisterRouter.scala:87:24] reg [31:0] abstractGeneratedMem_1; // @[Debug.scala:1586:35] wire [4:0] abstractGeneratedMem_0_inst_rd; // @[Debug.scala:1589:22] wire [15:0] _GEN_15 = {11'h0, accessRegisterCommandReg_regno[4:0]}; // @[Debug.scala:1533:44, :1593:54] wire [15:0] _abstractGeneratedMem_0_inst_rd_T; // @[Debug.scala:1593:54] assign _abstractGeneratedMem_0_inst_rd_T = _GEN_15; // @[Debug.scala:1593:54] wire [15:0] _abstractGeneratedMem_0_inst_rs2_T; // @[Debug.scala:1608:54] assign _abstractGeneratedMem_0_inst_rs2_T = _GEN_15; // @[Debug.scala:1593:54, :1608:54] assign abstractGeneratedMem_0_inst_rd = _abstractGeneratedMem_0_inst_rd_T[4:0]; // @[Debug.scala:1589:22, :1593:{19,54}] wire [11:0] abstractGeneratedMem_0_lo = {abstractGeneratedMem_0_inst_rd, 7'h3}; // @[Debug.scala:1589:22, :1597:12] wire [19:0] abstractGeneratedMem_0_hi = {17'h7000, abstractGeneratedMem_0_inst_funct3}; // @[Debug.scala:1589:22, :1597:12] wire [31:0] _abstractGeneratedMem_0_T = {abstractGeneratedMem_0_hi, abstractGeneratedMem_0_lo}; // @[Debug.scala:1597:12] wire [4:0] abstractGeneratedMem_0_inst_1_rs2; // @[Debug.scala:1601:22] assign abstractGeneratedMem_0_inst_1_rs2 = _abstractGeneratedMem_0_inst_rs2_T[4:0]; // @[Debug.scala:1601:22, :1608:{19,54}] wire [7:0] abstractGeneratedMem_0_lo_hi = {abstractGeneratedMem_0_inst_1_funct3, 5'h0}; // @[Debug.scala:1601:22, :1610:12] wire [14:0] abstractGeneratedMem_0_lo_1 = {abstractGeneratedMem_0_lo_hi, 7'h23}; // @[Debug.scala:1610:12] wire [11:0] abstractGeneratedMem_0_hi_hi_1 = {7'h1C, abstractGeneratedMem_0_inst_1_rs2}; // @[Debug.scala:1601:22, :1610:12] wire [16:0] abstractGeneratedMem_0_hi_1 = {abstractGeneratedMem_0_hi_hi_1, 5'h0}; // @[Debug.scala:1610:12] wire [31:0] _abstractGeneratedMem_0_T_1 = {abstractGeneratedMem_0_hi_1, abstractGeneratedMem_0_lo_1}; // @[Debug.scala:1610:12] wire [31:0] _abstractGeneratedMem_0_T_2 = accessRegisterCommandReg_write ? _abstractGeneratedMem_0_T : _abstractGeneratedMem_0_T_1; // @[Debug.scala:1533:44, :1597:12, :1610:12, :1641:14] wire [31:0] _abstractGeneratedMem_0_T_4 = accessRegisterCommandReg_transfer ? _abstractGeneratedMem_0_T_2 : 32'h13; // @[Debug.scala:1533:44, :1640:39, :1641:14] wire [31:0] _abstractGeneratedMem_1_T_1 = accessRegisterCommandReg_postexec ? 32'h13 : 32'h100073; // @[Debug.scala:1533:44, :1644:39] wire [6:0] _GEN_16 = {6'h0, flags_0_resume}; // @[Debug.scala:1517:25, :1702:60] wire [6:0] hi_1; // @[Debug.scala:1702:60] assign hi_1 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_2; // @[Debug.scala:1702:60] assign hi_2 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_3; // @[Debug.scala:1702:60] assign hi_3 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_4; // @[Debug.scala:1702:60] assign hi_4 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_5; // @[Debug.scala:1702:60] assign hi_5 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_6; // @[Debug.scala:1702:60] assign hi_6 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_7; // @[Debug.scala:1702:60] assign hi_7 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_8; // @[Debug.scala:1702:60] assign hi_8 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_9; // @[Debug.scala:1702:60] assign hi_9 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_10; // @[Debug.scala:1702:60] assign hi_10 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_11; // @[Debug.scala:1702:60] assign hi_11 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_12; // @[Debug.scala:1702:60] assign hi_12 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_13; // @[Debug.scala:1702:60] assign hi_13 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_14; // @[Debug.scala:1702:60] assign hi_14 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_15; // @[Debug.scala:1702:60] assign hi_15 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_16; // @[Debug.scala:1702:60] assign hi_16 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_17; // @[Debug.scala:1702:60] assign hi_17 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_18; // @[Debug.scala:1702:60] assign hi_18 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_19; // @[Debug.scala:1702:60] assign hi_19 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_20; // @[Debug.scala:1702:60] assign hi_20 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_21; // @[Debug.scala:1702:60] assign hi_21 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_22; // @[Debug.scala:1702:60] assign hi_22 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_23; // @[Debug.scala:1702:60] assign hi_23 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_24; // @[Debug.scala:1702:60] assign hi_24 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_25; // @[Debug.scala:1702:60] assign hi_25 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_26; // @[Debug.scala:1702:60] assign hi_26 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_27; // @[Debug.scala:1702:60] assign hi_27 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_28; // @[Debug.scala:1702:60] assign hi_28 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_29; // @[Debug.scala:1702:60] assign hi_29 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_30; // @[Debug.scala:1702:60] assign hi_30 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_31; // @[Debug.scala:1702:60] assign hi_31 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_32; // @[Debug.scala:1702:60] assign hi_32 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_33; // @[Debug.scala:1702:60] assign hi_33 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_34; // @[Debug.scala:1702:60] assign hi_34 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_35; // @[Debug.scala:1702:60] assign hi_35 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_36; // @[Debug.scala:1702:60] assign hi_36 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_37; // @[Debug.scala:1702:60] assign hi_37 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_38; // @[Debug.scala:1702:60] assign hi_38 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_39; // @[Debug.scala:1702:60] assign hi_39 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_40; // @[Debug.scala:1702:60] assign hi_40 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_41; // @[Debug.scala:1702:60] assign hi_41 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_42; // @[Debug.scala:1702:60] assign hi_42 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_43; // @[Debug.scala:1702:60] assign hi_43 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_44; // @[Debug.scala:1702:60] assign hi_44 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_45; // @[Debug.scala:1702:60] assign hi_45 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_46; // @[Debug.scala:1702:60] assign hi_46 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_47; // @[Debug.scala:1702:60] assign hi_47 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_48; // @[Debug.scala:1702:60] assign hi_48 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_49; // @[Debug.scala:1702:60] assign hi_49 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_50; // @[Debug.scala:1702:60] assign hi_50 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_51; // @[Debug.scala:1702:60] assign hi_51 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_52; // @[Debug.scala:1702:60] assign hi_52 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_53; // @[Debug.scala:1702:60] assign hi_53 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_54; // @[Debug.scala:1702:60] assign hi_54 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_55; // @[Debug.scala:1702:60] assign hi_55 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_56; // @[Debug.scala:1702:60] assign hi_56 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_57; // @[Debug.scala:1702:60] assign hi_57 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_58; // @[Debug.scala:1702:60] assign hi_58 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_59; // @[Debug.scala:1702:60] assign hi_59 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_60; // @[Debug.scala:1702:60] assign hi_60 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_61; // @[Debug.scala:1702:60] assign hi_61 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_62; // @[Debug.scala:1702:60] assign hi_62 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_63; // @[Debug.scala:1702:60] assign hi_63 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_64; // @[Debug.scala:1702:60] assign hi_64 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_65; // @[Debug.scala:1702:60] assign hi_65 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_66; // @[Debug.scala:1702:60] assign hi_66 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_67; // @[Debug.scala:1702:60] assign hi_67 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_68; // @[Debug.scala:1702:60] assign hi_68 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_69; // @[Debug.scala:1702:60] assign hi_69 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_70; // @[Debug.scala:1702:60] assign hi_70 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_71; // @[Debug.scala:1702:60] assign hi_71 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_72; // @[Debug.scala:1702:60] assign hi_72 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_73; // @[Debug.scala:1702:60] assign hi_73 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_74; // @[Debug.scala:1702:60] assign hi_74 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_75; // @[Debug.scala:1702:60] assign hi_75 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_76; // @[Debug.scala:1702:60] assign hi_76 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_77; // @[Debug.scala:1702:60] assign hi_77 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_78; // @[Debug.scala:1702:60] assign hi_78 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_79; // @[Debug.scala:1702:60] assign hi_79 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_80; // @[Debug.scala:1702:60] assign hi_80 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_81; // @[Debug.scala:1702:60] assign hi_81 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_82; // @[Debug.scala:1702:60] assign hi_82 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_83; // @[Debug.scala:1702:60] assign hi_83 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_84; // @[Debug.scala:1702:60] assign hi_84 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_85; // @[Debug.scala:1702:60] assign hi_85 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_86; // @[Debug.scala:1702:60] assign hi_86 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_87; // @[Debug.scala:1702:60] assign hi_87 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_88; // @[Debug.scala:1702:60] assign hi_88 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_89; // @[Debug.scala:1702:60] assign hi_89 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_90; // @[Debug.scala:1702:60] assign hi_90 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_91; // @[Debug.scala:1702:60] assign hi_91 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_92; // @[Debug.scala:1702:60] assign hi_92 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_93; // @[Debug.scala:1702:60] assign hi_93 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_94; // @[Debug.scala:1702:60] assign hi_94 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_95; // @[Debug.scala:1702:60] assign hi_95 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_96; // @[Debug.scala:1702:60] assign hi_96 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_97; // @[Debug.scala:1702:60] assign hi_97 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_98; // @[Debug.scala:1702:60] assign hi_98 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_99; // @[Debug.scala:1702:60] assign hi_99 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_100; // @[Debug.scala:1702:60] assign hi_100 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_101; // @[Debug.scala:1702:60] assign hi_101 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_102; // @[Debug.scala:1702:60] assign hi_102 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_103; // @[Debug.scala:1702:60] assign hi_103 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_104; // @[Debug.scala:1702:60] assign hi_104 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_105; // @[Debug.scala:1702:60] assign hi_105 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_106; // @[Debug.scala:1702:60] assign hi_106 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_107; // @[Debug.scala:1702:60] assign hi_107 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_108; // @[Debug.scala:1702:60] assign hi_108 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_109; // @[Debug.scala:1702:60] assign hi_109 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_110; // @[Debug.scala:1702:60] assign hi_110 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_111; // @[Debug.scala:1702:60] assign hi_111 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_112; // @[Debug.scala:1702:60] assign hi_112 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_113; // @[Debug.scala:1702:60] assign hi_113 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_114; // @[Debug.scala:1702:60] assign hi_114 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_115; // @[Debug.scala:1702:60] assign hi_115 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_116; // @[Debug.scala:1702:60] assign hi_116 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_117; // @[Debug.scala:1702:60] assign hi_117 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_118; // @[Debug.scala:1702:60] assign hi_118 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_119; // @[Debug.scala:1702:60] assign hi_119 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_120; // @[Debug.scala:1702:60] assign hi_120 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_121; // @[Debug.scala:1702:60] assign hi_121 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_122; // @[Debug.scala:1702:60] assign hi_122 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_123; // @[Debug.scala:1702:60] assign hi_123 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_124; // @[Debug.scala:1702:60] assign hi_124 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_125; // @[Debug.scala:1702:60] assign hi_125 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_126; // @[Debug.scala:1702:60] assign hi_126 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_127; // @[Debug.scala:1702:60] assign hi_127 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_128; // @[Debug.scala:1702:60] assign hi_128 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_129; // @[Debug.scala:1702:60] assign hi_129 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_130; // @[Debug.scala:1702:60] assign hi_130 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_131; // @[Debug.scala:1702:60] assign hi_131 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_132; // @[Debug.scala:1702:60] assign hi_132 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_133; // @[Debug.scala:1702:60] assign hi_133 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_134; // @[Debug.scala:1702:60] assign hi_134 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_135; // @[Debug.scala:1702:60] assign hi_135 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_136; // @[Debug.scala:1702:60] assign hi_136 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_137; // @[Debug.scala:1702:60] assign hi_137 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_138; // @[Debug.scala:1702:60] assign hi_138 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_139; // @[Debug.scala:1702:60] assign hi_139 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_140; // @[Debug.scala:1702:60] assign hi_140 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_141; // @[Debug.scala:1702:60] assign hi_141 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_142; // @[Debug.scala:1702:60] assign hi_142 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_143; // @[Debug.scala:1702:60] assign hi_143 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_144; // @[Debug.scala:1702:60] assign hi_144 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_145; // @[Debug.scala:1702:60] assign hi_145 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_146; // @[Debug.scala:1702:60] assign hi_146 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_147; // @[Debug.scala:1702:60] assign hi_147 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_148; // @[Debug.scala:1702:60] assign hi_148 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_149; // @[Debug.scala:1702:60] assign hi_149 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_150; // @[Debug.scala:1702:60] assign hi_150 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_151; // @[Debug.scala:1702:60] assign hi_151 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_152; // @[Debug.scala:1702:60] assign hi_152 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_153; // @[Debug.scala:1702:60] assign hi_153 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_154; // @[Debug.scala:1702:60] assign hi_154 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_155; // @[Debug.scala:1702:60] assign hi_155 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_156; // @[Debug.scala:1702:60] assign hi_156 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_157; // @[Debug.scala:1702:60] assign hi_157 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_158; // @[Debug.scala:1702:60] assign hi_158 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_159; // @[Debug.scala:1702:60] assign hi_159 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_160; // @[Debug.scala:1702:60] assign hi_160 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_161; // @[Debug.scala:1702:60] assign hi_161 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_162; // @[Debug.scala:1702:60] assign hi_162 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_163; // @[Debug.scala:1702:60] assign hi_163 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_164; // @[Debug.scala:1702:60] assign hi_164 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_165; // @[Debug.scala:1702:60] assign hi_165 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_166; // @[Debug.scala:1702:60] assign hi_166 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_167; // @[Debug.scala:1702:60] assign hi_167 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_168; // @[Debug.scala:1702:60] assign hi_168 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_169; // @[Debug.scala:1702:60] assign hi_169 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_170; // @[Debug.scala:1702:60] assign hi_170 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_171; // @[Debug.scala:1702:60] assign hi_171 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_172; // @[Debug.scala:1702:60] assign hi_172 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_173; // @[Debug.scala:1702:60] assign hi_173 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_174; // @[Debug.scala:1702:60] assign hi_174 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_175; // @[Debug.scala:1702:60] assign hi_175 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_176; // @[Debug.scala:1702:60] assign hi_176 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_177; // @[Debug.scala:1702:60] assign hi_177 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_178; // @[Debug.scala:1702:60] assign hi_178 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_179; // @[Debug.scala:1702:60] assign hi_179 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_180; // @[Debug.scala:1702:60] assign hi_180 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_181; // @[Debug.scala:1702:60] assign hi_181 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_182; // @[Debug.scala:1702:60] assign hi_182 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_183; // @[Debug.scala:1702:60] assign hi_183 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_184; // @[Debug.scala:1702:60] assign hi_184 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_185; // @[Debug.scala:1702:60] assign hi_185 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_186; // @[Debug.scala:1702:60] assign hi_186 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_187; // @[Debug.scala:1702:60] assign hi_187 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_188; // @[Debug.scala:1702:60] assign hi_188 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_189; // @[Debug.scala:1702:60] assign hi_189 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_190; // @[Debug.scala:1702:60] assign hi_190 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_191; // @[Debug.scala:1702:60] assign hi_191 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_192; // @[Debug.scala:1702:60] assign hi_192 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_193; // @[Debug.scala:1702:60] assign hi_193 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_194; // @[Debug.scala:1702:60] assign hi_194 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_195; // @[Debug.scala:1702:60] assign hi_195 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_196; // @[Debug.scala:1702:60] assign hi_196 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_197; // @[Debug.scala:1702:60] assign hi_197 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_198; // @[Debug.scala:1702:60] assign hi_198 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_199; // @[Debug.scala:1702:60] assign hi_199 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_200; // @[Debug.scala:1702:60] assign hi_200 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_201; // @[Debug.scala:1702:60] assign hi_201 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_202; // @[Debug.scala:1702:60] assign hi_202 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_203; // @[Debug.scala:1702:60] assign hi_203 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_204; // @[Debug.scala:1702:60] assign hi_204 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_205; // @[Debug.scala:1702:60] assign hi_205 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_206; // @[Debug.scala:1702:60] assign hi_206 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_207; // @[Debug.scala:1702:60] assign hi_207 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_208; // @[Debug.scala:1702:60] assign hi_208 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_209; // @[Debug.scala:1702:60] assign hi_209 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_210; // @[Debug.scala:1702:60] assign hi_210 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_211; // @[Debug.scala:1702:60] assign hi_211 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_212; // @[Debug.scala:1702:60] assign hi_212 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_213; // @[Debug.scala:1702:60] assign hi_213 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_214; // @[Debug.scala:1702:60] assign hi_214 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_215; // @[Debug.scala:1702:60] assign hi_215 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_216; // @[Debug.scala:1702:60] assign hi_216 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_217; // @[Debug.scala:1702:60] assign hi_217 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_218; // @[Debug.scala:1702:60] assign hi_218 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_219; // @[Debug.scala:1702:60] assign hi_219 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_220; // @[Debug.scala:1702:60] assign hi_220 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_221; // @[Debug.scala:1702:60] assign hi_221 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_222; // @[Debug.scala:1702:60] assign hi_222 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_223; // @[Debug.scala:1702:60] assign hi_223 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_224; // @[Debug.scala:1702:60] assign hi_224 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_225; // @[Debug.scala:1702:60] assign hi_225 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_226; // @[Debug.scala:1702:60] assign hi_226 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_227; // @[Debug.scala:1702:60] assign hi_227 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_228; // @[Debug.scala:1702:60] assign hi_228 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_229; // @[Debug.scala:1702:60] assign hi_229 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_230; // @[Debug.scala:1702:60] assign hi_230 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_231; // @[Debug.scala:1702:60] assign hi_231 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_232; // @[Debug.scala:1702:60] assign hi_232 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_233; // @[Debug.scala:1702:60] assign hi_233 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_234; // @[Debug.scala:1702:60] assign hi_234 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_235; // @[Debug.scala:1702:60] assign hi_235 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_236; // @[Debug.scala:1702:60] assign hi_236 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_237; // @[Debug.scala:1702:60] assign hi_237 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_238; // @[Debug.scala:1702:60] assign hi_238 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_239; // @[Debug.scala:1702:60] assign hi_239 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_240; // @[Debug.scala:1702:60] assign hi_240 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_241; // @[Debug.scala:1702:60] assign hi_241 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_242; // @[Debug.scala:1702:60] assign hi_242 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_243; // @[Debug.scala:1702:60] assign hi_243 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_244; // @[Debug.scala:1702:60] assign hi_244 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_245; // @[Debug.scala:1702:60] assign hi_245 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_246; // @[Debug.scala:1702:60] assign hi_246 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_247; // @[Debug.scala:1702:60] assign hi_247 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_248; // @[Debug.scala:1702:60] assign hi_248 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_249; // @[Debug.scala:1702:60] assign hi_249 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_250; // @[Debug.scala:1702:60] assign hi_250 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_251; // @[Debug.scala:1702:60] assign hi_251 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_252; // @[Debug.scala:1702:60] assign hi_252 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_253; // @[Debug.scala:1702:60] assign hi_253 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_254; // @[Debug.scala:1702:60] assign hi_254 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_255; // @[Debug.scala:1702:60] assign hi_255 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_256; // @[Debug.scala:1702:60] assign hi_256 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_257; // @[Debug.scala:1702:60] assign hi_257 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_258; // @[Debug.scala:1702:60] assign hi_258 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_259; // @[Debug.scala:1702:60] assign hi_259 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_260; // @[Debug.scala:1702:60] assign hi_260 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_261; // @[Debug.scala:1702:60] assign hi_261 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_262; // @[Debug.scala:1702:60] assign hi_262 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_263; // @[Debug.scala:1702:60] assign hi_263 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_264; // @[Debug.scala:1702:60] assign hi_264 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_265; // @[Debug.scala:1702:60] assign hi_265 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_266; // @[Debug.scala:1702:60] assign hi_266 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_267; // @[Debug.scala:1702:60] assign hi_267 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_268; // @[Debug.scala:1702:60] assign hi_268 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_269; // @[Debug.scala:1702:60] assign hi_269 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_270; // @[Debug.scala:1702:60] assign hi_270 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_271; // @[Debug.scala:1702:60] assign hi_271 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_272; // @[Debug.scala:1702:60] assign hi_272 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_273; // @[Debug.scala:1702:60] assign hi_273 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_274; // @[Debug.scala:1702:60] assign hi_274 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_275; // @[Debug.scala:1702:60] assign hi_275 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_276; // @[Debug.scala:1702:60] assign hi_276 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_277; // @[Debug.scala:1702:60] assign hi_277 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_278; // @[Debug.scala:1702:60] assign hi_278 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_279; // @[Debug.scala:1702:60] assign hi_279 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_280; // @[Debug.scala:1702:60] assign hi_280 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_281; // @[Debug.scala:1702:60] assign hi_281 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_282; // @[Debug.scala:1702:60] assign hi_282 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_283; // @[Debug.scala:1702:60] assign hi_283 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_284; // @[Debug.scala:1702:60] assign hi_284 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_285; // @[Debug.scala:1702:60] assign hi_285 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_286; // @[Debug.scala:1702:60] assign hi_286 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_287; // @[Debug.scala:1702:60] assign hi_287 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_288; // @[Debug.scala:1702:60] assign hi_288 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_289; // @[Debug.scala:1702:60] assign hi_289 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_290; // @[Debug.scala:1702:60] assign hi_290 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_291; // @[Debug.scala:1702:60] assign hi_291 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_292; // @[Debug.scala:1702:60] assign hi_292 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_293; // @[Debug.scala:1702:60] assign hi_293 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_294; // @[Debug.scala:1702:60] assign hi_294 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_295; // @[Debug.scala:1702:60] assign hi_295 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_296; // @[Debug.scala:1702:60] assign hi_296 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_297; // @[Debug.scala:1702:60] assign hi_297 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_298; // @[Debug.scala:1702:60] assign hi_298 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_299; // @[Debug.scala:1702:60] assign hi_299 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_300; // @[Debug.scala:1702:60] assign hi_300 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_301; // @[Debug.scala:1702:60] assign hi_301 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_302; // @[Debug.scala:1702:60] assign hi_302 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_303; // @[Debug.scala:1702:60] assign hi_303 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_304; // @[Debug.scala:1702:60] assign hi_304 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_305; // @[Debug.scala:1702:60] assign hi_305 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_306; // @[Debug.scala:1702:60] assign hi_306 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_307; // @[Debug.scala:1702:60] assign hi_307 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_308; // @[Debug.scala:1702:60] assign hi_308 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_309; // @[Debug.scala:1702:60] assign hi_309 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_310; // @[Debug.scala:1702:60] assign hi_310 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_311; // @[Debug.scala:1702:60] assign hi_311 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_312; // @[Debug.scala:1702:60] assign hi_312 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_313; // @[Debug.scala:1702:60] assign hi_313 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_314; // @[Debug.scala:1702:60] assign hi_314 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_315; // @[Debug.scala:1702:60] assign hi_315 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_316; // @[Debug.scala:1702:60] assign hi_316 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_317; // @[Debug.scala:1702:60] assign hi_317 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_318; // @[Debug.scala:1702:60] assign hi_318 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_319; // @[Debug.scala:1702:60] assign hi_319 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_320; // @[Debug.scala:1702:60] assign hi_320 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_321; // @[Debug.scala:1702:60] assign hi_321 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_322; // @[Debug.scala:1702:60] assign hi_322 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_323; // @[Debug.scala:1702:60] assign hi_323 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_324; // @[Debug.scala:1702:60] assign hi_324 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_325; // @[Debug.scala:1702:60] assign hi_325 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_326; // @[Debug.scala:1702:60] assign hi_326 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_327; // @[Debug.scala:1702:60] assign hi_327 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_328; // @[Debug.scala:1702:60] assign hi_328 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_329; // @[Debug.scala:1702:60] assign hi_329 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_330; // @[Debug.scala:1702:60] assign hi_330 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_331; // @[Debug.scala:1702:60] assign hi_331 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_332; // @[Debug.scala:1702:60] assign hi_332 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_333; // @[Debug.scala:1702:60] assign hi_333 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_334; // @[Debug.scala:1702:60] assign hi_334 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_335; // @[Debug.scala:1702:60] assign hi_335 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_336; // @[Debug.scala:1702:60] assign hi_336 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_337; // @[Debug.scala:1702:60] assign hi_337 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_338; // @[Debug.scala:1702:60] assign hi_338 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_339; // @[Debug.scala:1702:60] assign hi_339 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_340; // @[Debug.scala:1702:60] assign hi_340 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_341; // @[Debug.scala:1702:60] assign hi_341 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_342; // @[Debug.scala:1702:60] assign hi_342 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_343; // @[Debug.scala:1702:60] assign hi_343 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_344; // @[Debug.scala:1702:60] assign hi_344 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_345; // @[Debug.scala:1702:60] assign hi_345 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_346; // @[Debug.scala:1702:60] assign hi_346 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_347; // @[Debug.scala:1702:60] assign hi_347 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_348; // @[Debug.scala:1702:60] assign hi_348 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_349; // @[Debug.scala:1702:60] assign hi_349 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_350; // @[Debug.scala:1702:60] assign hi_350 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_351; // @[Debug.scala:1702:60] assign hi_351 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_352; // @[Debug.scala:1702:60] assign hi_352 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_353; // @[Debug.scala:1702:60] assign hi_353 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_354; // @[Debug.scala:1702:60] assign hi_354 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_355; // @[Debug.scala:1702:60] assign hi_355 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_356; // @[Debug.scala:1702:60] assign hi_356 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_357; // @[Debug.scala:1702:60] assign hi_357 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_358; // @[Debug.scala:1702:60] assign hi_358 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_359; // @[Debug.scala:1702:60] assign hi_359 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_360; // @[Debug.scala:1702:60] assign hi_360 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_361; // @[Debug.scala:1702:60] assign hi_361 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_362; // @[Debug.scala:1702:60] assign hi_362 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_363; // @[Debug.scala:1702:60] assign hi_363 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_364; // @[Debug.scala:1702:60] assign hi_364 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_365; // @[Debug.scala:1702:60] assign hi_365 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_366; // @[Debug.scala:1702:60] assign hi_366 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_367; // @[Debug.scala:1702:60] assign hi_367 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_368; // @[Debug.scala:1702:60] assign hi_368 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_369; // @[Debug.scala:1702:60] assign hi_369 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_370; // @[Debug.scala:1702:60] assign hi_370 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_371; // @[Debug.scala:1702:60] assign hi_371 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_372; // @[Debug.scala:1702:60] assign hi_372 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_373; // @[Debug.scala:1702:60] assign hi_373 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_374; // @[Debug.scala:1702:60] assign hi_374 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_375; // @[Debug.scala:1702:60] assign hi_375 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_376; // @[Debug.scala:1702:60] assign hi_376 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_377; // @[Debug.scala:1702:60] assign hi_377 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_378; // @[Debug.scala:1702:60] assign hi_378 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_379; // @[Debug.scala:1702:60] assign hi_379 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_380; // @[Debug.scala:1702:60] assign hi_380 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_381; // @[Debug.scala:1702:60] assign hi_381 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_382; // @[Debug.scala:1702:60] assign hi_382 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_383; // @[Debug.scala:1702:60] assign hi_383 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_384; // @[Debug.scala:1702:60] assign hi_384 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_385; // @[Debug.scala:1702:60] assign hi_385 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_386; // @[Debug.scala:1702:60] assign hi_386 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_387; // @[Debug.scala:1702:60] assign hi_387 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_388; // @[Debug.scala:1702:60] assign hi_388 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_389; // @[Debug.scala:1702:60] assign hi_389 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_390; // @[Debug.scala:1702:60] assign hi_390 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_391; // @[Debug.scala:1702:60] assign hi_391 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_392; // @[Debug.scala:1702:60] assign hi_392 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_393; // @[Debug.scala:1702:60] assign hi_393 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_394; // @[Debug.scala:1702:60] assign hi_394 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_395; // @[Debug.scala:1702:60] assign hi_395 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_396; // @[Debug.scala:1702:60] assign hi_396 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_397; // @[Debug.scala:1702:60] assign hi_397 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_398; // @[Debug.scala:1702:60] assign hi_398 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_399; // @[Debug.scala:1702:60] assign hi_399 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_400; // @[Debug.scala:1702:60] assign hi_400 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_401; // @[Debug.scala:1702:60] assign hi_401 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_402; // @[Debug.scala:1702:60] assign hi_402 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_403; // @[Debug.scala:1702:60] assign hi_403 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_404; // @[Debug.scala:1702:60] assign hi_404 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_405; // @[Debug.scala:1702:60] assign hi_405 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_406; // @[Debug.scala:1702:60] assign hi_406 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_407; // @[Debug.scala:1702:60] assign hi_407 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_408; // @[Debug.scala:1702:60] assign hi_408 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_409; // @[Debug.scala:1702:60] assign hi_409 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_410; // @[Debug.scala:1702:60] assign hi_410 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_411; // @[Debug.scala:1702:60] assign hi_411 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_412; // @[Debug.scala:1702:60] assign hi_412 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_413; // @[Debug.scala:1702:60] assign hi_413 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_414; // @[Debug.scala:1702:60] assign hi_414 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_415; // @[Debug.scala:1702:60] assign hi_415 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_416; // @[Debug.scala:1702:60] assign hi_416 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_417; // @[Debug.scala:1702:60] assign hi_417 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_418; // @[Debug.scala:1702:60] assign hi_418 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_419; // @[Debug.scala:1702:60] assign hi_419 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_420; // @[Debug.scala:1702:60] assign hi_420 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_421; // @[Debug.scala:1702:60] assign hi_421 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_422; // @[Debug.scala:1702:60] assign hi_422 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_423; // @[Debug.scala:1702:60] assign hi_423 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_424; // @[Debug.scala:1702:60] assign hi_424 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_425; // @[Debug.scala:1702:60] assign hi_425 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_426; // @[Debug.scala:1702:60] assign hi_426 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_427; // @[Debug.scala:1702:60] assign hi_427 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_428; // @[Debug.scala:1702:60] assign hi_428 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_429; // @[Debug.scala:1702:60] assign hi_429 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_430; // @[Debug.scala:1702:60] assign hi_430 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_431; // @[Debug.scala:1702:60] assign hi_431 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_432; // @[Debug.scala:1702:60] assign hi_432 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_433; // @[Debug.scala:1702:60] assign hi_433 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_434; // @[Debug.scala:1702:60] assign hi_434 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_435; // @[Debug.scala:1702:60] assign hi_435 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_436; // @[Debug.scala:1702:60] assign hi_436 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_437; // @[Debug.scala:1702:60] assign hi_437 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_438; // @[Debug.scala:1702:60] assign hi_438 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_439; // @[Debug.scala:1702:60] assign hi_439 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_440; // @[Debug.scala:1702:60] assign hi_440 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_441; // @[Debug.scala:1702:60] assign hi_441 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_442; // @[Debug.scala:1702:60] assign hi_442 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_443; // @[Debug.scala:1702:60] assign hi_443 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_444; // @[Debug.scala:1702:60] assign hi_444 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_445; // @[Debug.scala:1702:60] assign hi_445 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_446; // @[Debug.scala:1702:60] assign hi_446 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_447; // @[Debug.scala:1702:60] assign hi_447 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_448; // @[Debug.scala:1702:60] assign hi_448 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_449; // @[Debug.scala:1702:60] assign hi_449 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_450; // @[Debug.scala:1702:60] assign hi_450 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_451; // @[Debug.scala:1702:60] assign hi_451 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_452; // @[Debug.scala:1702:60] assign hi_452 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_453; // @[Debug.scala:1702:60] assign hi_453 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_454; // @[Debug.scala:1702:60] assign hi_454 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_455; // @[Debug.scala:1702:60] assign hi_455 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_456; // @[Debug.scala:1702:60] assign hi_456 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_457; // @[Debug.scala:1702:60] assign hi_457 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_458; // @[Debug.scala:1702:60] assign hi_458 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_459; // @[Debug.scala:1702:60] assign hi_459 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_460; // @[Debug.scala:1702:60] assign hi_460 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_461; // @[Debug.scala:1702:60] assign hi_461 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_462; // @[Debug.scala:1702:60] assign hi_462 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_463; // @[Debug.scala:1702:60] assign hi_463 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_464; // @[Debug.scala:1702:60] assign hi_464 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_465; // @[Debug.scala:1702:60] assign hi_465 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_466; // @[Debug.scala:1702:60] assign hi_466 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_467; // @[Debug.scala:1702:60] assign hi_467 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_468; // @[Debug.scala:1702:60] assign hi_468 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_469; // @[Debug.scala:1702:60] assign hi_469 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_470; // @[Debug.scala:1702:60] assign hi_470 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_471; // @[Debug.scala:1702:60] assign hi_471 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_472; // @[Debug.scala:1702:60] assign hi_472 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_473; // @[Debug.scala:1702:60] assign hi_473 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_474; // @[Debug.scala:1702:60] assign hi_474 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_475; // @[Debug.scala:1702:60] assign hi_475 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_476; // @[Debug.scala:1702:60] assign hi_476 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_477; // @[Debug.scala:1702:60] assign hi_477 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_478; // @[Debug.scala:1702:60] assign hi_478 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_479; // @[Debug.scala:1702:60] assign hi_479 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_480; // @[Debug.scala:1702:60] assign hi_480 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_481; // @[Debug.scala:1702:60] assign hi_481 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_482; // @[Debug.scala:1702:60] assign hi_482 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_483; // @[Debug.scala:1702:60] assign hi_483 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_484; // @[Debug.scala:1702:60] assign hi_484 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_485; // @[Debug.scala:1702:60] assign hi_485 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_486; // @[Debug.scala:1702:60] assign hi_486 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_487; // @[Debug.scala:1702:60] assign hi_487 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_488; // @[Debug.scala:1702:60] assign hi_488 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_489; // @[Debug.scala:1702:60] assign hi_489 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_490; // @[Debug.scala:1702:60] assign hi_490 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_491; // @[Debug.scala:1702:60] assign hi_491 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_492; // @[Debug.scala:1702:60] assign hi_492 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_493; // @[Debug.scala:1702:60] assign hi_493 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_494; // @[Debug.scala:1702:60] assign hi_494 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_495; // @[Debug.scala:1702:60] assign hi_495 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_496; // @[Debug.scala:1702:60] assign hi_496 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_497; // @[Debug.scala:1702:60] assign hi_497 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_498; // @[Debug.scala:1702:60] assign hi_498 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_499; // @[Debug.scala:1702:60] assign hi_499 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_500; // @[Debug.scala:1702:60] assign hi_500 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_501; // @[Debug.scala:1702:60] assign hi_501 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_502; // @[Debug.scala:1702:60] assign hi_502 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_503; // @[Debug.scala:1702:60] assign hi_503 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_504; // @[Debug.scala:1702:60] assign hi_504 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_505; // @[Debug.scala:1702:60] assign hi_505 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_506; // @[Debug.scala:1702:60] assign hi_506 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_507; // @[Debug.scala:1702:60] assign hi_507 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_508; // @[Debug.scala:1702:60] assign hi_508 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_509; // @[Debug.scala:1702:60] assign hi_509 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_510; // @[Debug.scala:1702:60] assign hi_510 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_511; // @[Debug.scala:1702:60] assign hi_511 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_512; // @[Debug.scala:1702:60] assign hi_512 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_513; // @[Debug.scala:1702:60] assign hi_513 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_514; // @[Debug.scala:1702:60] assign hi_514 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_515; // @[Debug.scala:1702:60] assign hi_515 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_516; // @[Debug.scala:1702:60] assign hi_516 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_517; // @[Debug.scala:1702:60] assign hi_517 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_518; // @[Debug.scala:1702:60] assign hi_518 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_519; // @[Debug.scala:1702:60] assign hi_519 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_520; // @[Debug.scala:1702:60] assign hi_520 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_521; // @[Debug.scala:1702:60] assign hi_521 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_522; // @[Debug.scala:1702:60] assign hi_522 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_523; // @[Debug.scala:1702:60] assign hi_523 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_524; // @[Debug.scala:1702:60] assign hi_524 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_525; // @[Debug.scala:1702:60] assign hi_525 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_526; // @[Debug.scala:1702:60] assign hi_526 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_527; // @[Debug.scala:1702:60] assign hi_527 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_528; // @[Debug.scala:1702:60] assign hi_528 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_529; // @[Debug.scala:1702:60] assign hi_529 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_530; // @[Debug.scala:1702:60] assign hi_530 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_531; // @[Debug.scala:1702:60] assign hi_531 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_532; // @[Debug.scala:1702:60] assign hi_532 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_533; // @[Debug.scala:1702:60] assign hi_533 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_534; // @[Debug.scala:1702:60] assign hi_534 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_535; // @[Debug.scala:1702:60] assign hi_535 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_536; // @[Debug.scala:1702:60] assign hi_536 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_537; // @[Debug.scala:1702:60] assign hi_537 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_538; // @[Debug.scala:1702:60] assign hi_538 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_539; // @[Debug.scala:1702:60] assign hi_539 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_540; // @[Debug.scala:1702:60] assign hi_540 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_541; // @[Debug.scala:1702:60] assign hi_541 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_542; // @[Debug.scala:1702:60] assign hi_542 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_543; // @[Debug.scala:1702:60] assign hi_543 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_544; // @[Debug.scala:1702:60] assign hi_544 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_545; // @[Debug.scala:1702:60] assign hi_545 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_546; // @[Debug.scala:1702:60] assign hi_546 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_547; // @[Debug.scala:1702:60] assign hi_547 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_548; // @[Debug.scala:1702:60] assign hi_548 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_549; // @[Debug.scala:1702:60] assign hi_549 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_550; // @[Debug.scala:1702:60] assign hi_550 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_551; // @[Debug.scala:1702:60] assign hi_551 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_552; // @[Debug.scala:1702:60] assign hi_552 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_553; // @[Debug.scala:1702:60] assign hi_553 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_554; // @[Debug.scala:1702:60] assign hi_554 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_555; // @[Debug.scala:1702:60] assign hi_555 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_556; // @[Debug.scala:1702:60] assign hi_556 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_557; // @[Debug.scala:1702:60] assign hi_557 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_558; // @[Debug.scala:1702:60] assign hi_558 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_559; // @[Debug.scala:1702:60] assign hi_559 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_560; // @[Debug.scala:1702:60] assign hi_560 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_561; // @[Debug.scala:1702:60] assign hi_561 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_562; // @[Debug.scala:1702:60] assign hi_562 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_563; // @[Debug.scala:1702:60] assign hi_563 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_564; // @[Debug.scala:1702:60] assign hi_564 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_565; // @[Debug.scala:1702:60] assign hi_565 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_566; // @[Debug.scala:1702:60] assign hi_566 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_567; // @[Debug.scala:1702:60] assign hi_567 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_568; // @[Debug.scala:1702:60] assign hi_568 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_569; // @[Debug.scala:1702:60] assign hi_569 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_570; // @[Debug.scala:1702:60] assign hi_570 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_571; // @[Debug.scala:1702:60] assign hi_571 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_572; // @[Debug.scala:1702:60] assign hi_572 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_573; // @[Debug.scala:1702:60] assign hi_573 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_574; // @[Debug.scala:1702:60] assign hi_574 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_575; // @[Debug.scala:1702:60] assign hi_575 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_576; // @[Debug.scala:1702:60] assign hi_576 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_577; // @[Debug.scala:1702:60] assign hi_577 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_578; // @[Debug.scala:1702:60] assign hi_578 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_579; // @[Debug.scala:1702:60] assign hi_579 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_580; // @[Debug.scala:1702:60] assign hi_580 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_581; // @[Debug.scala:1702:60] assign hi_581 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_582; // @[Debug.scala:1702:60] assign hi_582 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_583; // @[Debug.scala:1702:60] assign hi_583 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_584; // @[Debug.scala:1702:60] assign hi_584 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_585; // @[Debug.scala:1702:60] assign hi_585 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_586; // @[Debug.scala:1702:60] assign hi_586 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_587; // @[Debug.scala:1702:60] assign hi_587 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_588; // @[Debug.scala:1702:60] assign hi_588 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_589; // @[Debug.scala:1702:60] assign hi_589 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_590; // @[Debug.scala:1702:60] assign hi_590 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_591; // @[Debug.scala:1702:60] assign hi_591 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_592; // @[Debug.scala:1702:60] assign hi_592 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_593; // @[Debug.scala:1702:60] assign hi_593 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_594; // @[Debug.scala:1702:60] assign hi_594 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_595; // @[Debug.scala:1702:60] assign hi_595 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_596; // @[Debug.scala:1702:60] assign hi_596 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_597; // @[Debug.scala:1702:60] assign hi_597 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_598; // @[Debug.scala:1702:60] assign hi_598 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_599; // @[Debug.scala:1702:60] assign hi_599 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_600; // @[Debug.scala:1702:60] assign hi_600 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_601; // @[Debug.scala:1702:60] assign hi_601 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_602; // @[Debug.scala:1702:60] assign hi_602 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_603; // @[Debug.scala:1702:60] assign hi_603 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_604; // @[Debug.scala:1702:60] assign hi_604 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_605; // @[Debug.scala:1702:60] assign hi_605 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_606; // @[Debug.scala:1702:60] assign hi_606 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_607; // @[Debug.scala:1702:60] assign hi_607 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_608; // @[Debug.scala:1702:60] assign hi_608 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_609; // @[Debug.scala:1702:60] assign hi_609 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_610; // @[Debug.scala:1702:60] assign hi_610 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_611; // @[Debug.scala:1702:60] assign hi_611 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_612; // @[Debug.scala:1702:60] assign hi_612 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_613; // @[Debug.scala:1702:60] assign hi_613 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_614; // @[Debug.scala:1702:60] assign hi_614 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_615; // @[Debug.scala:1702:60] assign hi_615 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_616; // @[Debug.scala:1702:60] assign hi_616 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_617; // @[Debug.scala:1702:60] assign hi_617 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_618; // @[Debug.scala:1702:60] assign hi_618 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_619; // @[Debug.scala:1702:60] assign hi_619 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_620; // @[Debug.scala:1702:60] assign hi_620 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_621; // @[Debug.scala:1702:60] assign hi_621 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_622; // @[Debug.scala:1702:60] assign hi_622 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_623; // @[Debug.scala:1702:60] assign hi_623 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_624; // @[Debug.scala:1702:60] assign hi_624 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_625; // @[Debug.scala:1702:60] assign hi_625 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_626; // @[Debug.scala:1702:60] assign hi_626 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_627; // @[Debug.scala:1702:60] assign hi_627 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_628; // @[Debug.scala:1702:60] assign hi_628 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_629; // @[Debug.scala:1702:60] assign hi_629 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_630; // @[Debug.scala:1702:60] assign hi_630 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_631; // @[Debug.scala:1702:60] assign hi_631 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_632; // @[Debug.scala:1702:60] assign hi_632 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_633; // @[Debug.scala:1702:60] assign hi_633 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_634; // @[Debug.scala:1702:60] assign hi_634 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_635; // @[Debug.scala:1702:60] assign hi_635 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_636; // @[Debug.scala:1702:60] assign hi_636 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_637; // @[Debug.scala:1702:60] assign hi_637 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_638; // @[Debug.scala:1702:60] assign hi_638 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_639; // @[Debug.scala:1702:60] assign hi_639 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_640; // @[Debug.scala:1702:60] assign hi_640 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_641; // @[Debug.scala:1702:60] assign hi_641 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_642; // @[Debug.scala:1702:60] assign hi_642 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_643; // @[Debug.scala:1702:60] assign hi_643 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_644; // @[Debug.scala:1702:60] assign hi_644 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_645; // @[Debug.scala:1702:60] assign hi_645 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_646; // @[Debug.scala:1702:60] assign hi_646 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_647; // @[Debug.scala:1702:60] assign hi_647 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_648; // @[Debug.scala:1702:60] assign hi_648 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_649; // @[Debug.scala:1702:60] assign hi_649 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_650; // @[Debug.scala:1702:60] assign hi_650 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_651; // @[Debug.scala:1702:60] assign hi_651 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_652; // @[Debug.scala:1702:60] assign hi_652 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_653; // @[Debug.scala:1702:60] assign hi_653 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_654; // @[Debug.scala:1702:60] assign hi_654 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_655; // @[Debug.scala:1702:60] assign hi_655 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_656; // @[Debug.scala:1702:60] assign hi_656 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_657; // @[Debug.scala:1702:60] assign hi_657 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_658; // @[Debug.scala:1702:60] assign hi_658 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_659; // @[Debug.scala:1702:60] assign hi_659 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_660; // @[Debug.scala:1702:60] assign hi_660 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_661; // @[Debug.scala:1702:60] assign hi_661 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_662; // @[Debug.scala:1702:60] assign hi_662 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_663; // @[Debug.scala:1702:60] assign hi_663 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_664; // @[Debug.scala:1702:60] assign hi_664 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_665; // @[Debug.scala:1702:60] assign hi_665 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_666; // @[Debug.scala:1702:60] assign hi_666 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_667; // @[Debug.scala:1702:60] assign hi_667 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_668; // @[Debug.scala:1702:60] assign hi_668 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_669; // @[Debug.scala:1702:60] assign hi_669 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_670; // @[Debug.scala:1702:60] assign hi_670 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_671; // @[Debug.scala:1702:60] assign hi_671 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_672; // @[Debug.scala:1702:60] assign hi_672 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_673; // @[Debug.scala:1702:60] assign hi_673 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_674; // @[Debug.scala:1702:60] assign hi_674 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_675; // @[Debug.scala:1702:60] assign hi_675 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_676; // @[Debug.scala:1702:60] assign hi_676 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_677; // @[Debug.scala:1702:60] assign hi_677 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_678; // @[Debug.scala:1702:60] assign hi_678 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_679; // @[Debug.scala:1702:60] assign hi_679 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_680; // @[Debug.scala:1702:60] assign hi_680 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_681; // @[Debug.scala:1702:60] assign hi_681 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_682; // @[Debug.scala:1702:60] assign hi_682 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_683; // @[Debug.scala:1702:60] assign hi_683 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_684; // @[Debug.scala:1702:60] assign hi_684 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_685; // @[Debug.scala:1702:60] assign hi_685 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_686; // @[Debug.scala:1702:60] assign hi_686 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_687; // @[Debug.scala:1702:60] assign hi_687 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_688; // @[Debug.scala:1702:60] assign hi_688 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_689; // @[Debug.scala:1702:60] assign hi_689 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_690; // @[Debug.scala:1702:60] assign hi_690 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_691; // @[Debug.scala:1702:60] assign hi_691 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_692; // @[Debug.scala:1702:60] assign hi_692 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_693; // @[Debug.scala:1702:60] assign hi_693 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_694; // @[Debug.scala:1702:60] assign hi_694 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_695; // @[Debug.scala:1702:60] assign hi_695 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_696; // @[Debug.scala:1702:60] assign hi_696 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_697; // @[Debug.scala:1702:60] assign hi_697 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_698; // @[Debug.scala:1702:60] assign hi_698 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_699; // @[Debug.scala:1702:60] assign hi_699 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_700; // @[Debug.scala:1702:60] assign hi_700 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_701; // @[Debug.scala:1702:60] assign hi_701 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_702; // @[Debug.scala:1702:60] assign hi_702 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_703; // @[Debug.scala:1702:60] assign hi_703 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_704; // @[Debug.scala:1702:60] assign hi_704 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_705; // @[Debug.scala:1702:60] assign hi_705 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_706; // @[Debug.scala:1702:60] assign hi_706 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_707; // @[Debug.scala:1702:60] assign hi_707 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_708; // @[Debug.scala:1702:60] assign hi_708 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_709; // @[Debug.scala:1702:60] assign hi_709 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_710; // @[Debug.scala:1702:60] assign hi_710 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_711; // @[Debug.scala:1702:60] assign hi_711 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_712; // @[Debug.scala:1702:60] assign hi_712 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_713; // @[Debug.scala:1702:60] assign hi_713 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_714; // @[Debug.scala:1702:60] assign hi_714 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_715; // @[Debug.scala:1702:60] assign hi_715 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_716; // @[Debug.scala:1702:60] assign hi_716 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_717; // @[Debug.scala:1702:60] assign hi_717 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_718; // @[Debug.scala:1702:60] assign hi_718 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_719; // @[Debug.scala:1702:60] assign hi_719 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_720; // @[Debug.scala:1702:60] assign hi_720 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_721; // @[Debug.scala:1702:60] assign hi_721 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_722; // @[Debug.scala:1702:60] assign hi_722 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_723; // @[Debug.scala:1702:60] assign hi_723 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_724; // @[Debug.scala:1702:60] assign hi_724 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_725; // @[Debug.scala:1702:60] assign hi_725 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_726; // @[Debug.scala:1702:60] assign hi_726 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_727; // @[Debug.scala:1702:60] assign hi_727 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_728; // @[Debug.scala:1702:60] assign hi_728 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_729; // @[Debug.scala:1702:60] assign hi_729 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_730; // @[Debug.scala:1702:60] assign hi_730 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_731; // @[Debug.scala:1702:60] assign hi_731 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_732; // @[Debug.scala:1702:60] assign hi_732 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_733; // @[Debug.scala:1702:60] assign hi_733 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_734; // @[Debug.scala:1702:60] assign hi_734 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_735; // @[Debug.scala:1702:60] assign hi_735 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_736; // @[Debug.scala:1702:60] assign hi_736 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_737; // @[Debug.scala:1702:60] assign hi_737 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_738; // @[Debug.scala:1702:60] assign hi_738 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_739; // @[Debug.scala:1702:60] assign hi_739 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_740; // @[Debug.scala:1702:60] assign hi_740 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_741; // @[Debug.scala:1702:60] assign hi_741 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_742; // @[Debug.scala:1702:60] assign hi_742 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_743; // @[Debug.scala:1702:60] assign hi_743 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_744; // @[Debug.scala:1702:60] assign hi_744 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_745; // @[Debug.scala:1702:60] assign hi_745 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_746; // @[Debug.scala:1702:60] assign hi_746 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_747; // @[Debug.scala:1702:60] assign hi_747 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_748; // @[Debug.scala:1702:60] assign hi_748 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_749; // @[Debug.scala:1702:60] assign hi_749 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_750; // @[Debug.scala:1702:60] assign hi_750 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_751; // @[Debug.scala:1702:60] assign hi_751 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_752; // @[Debug.scala:1702:60] assign hi_752 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_753; // @[Debug.scala:1702:60] assign hi_753 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_754; // @[Debug.scala:1702:60] assign hi_754 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_755; // @[Debug.scala:1702:60] assign hi_755 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_756; // @[Debug.scala:1702:60] assign hi_756 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_757; // @[Debug.scala:1702:60] assign hi_757 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_758; // @[Debug.scala:1702:60] assign hi_758 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_759; // @[Debug.scala:1702:60] assign hi_759 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_760; // @[Debug.scala:1702:60] assign hi_760 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_761; // @[Debug.scala:1702:60] assign hi_761 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_762; // @[Debug.scala:1702:60] assign hi_762 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_763; // @[Debug.scala:1702:60] assign hi_763 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_764; // @[Debug.scala:1702:60] assign hi_764 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_765; // @[Debug.scala:1702:60] assign hi_765 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_766; // @[Debug.scala:1702:60] assign hi_766 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_767; // @[Debug.scala:1702:60] assign hi_767 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_768; // @[Debug.scala:1702:60] assign hi_768 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_769; // @[Debug.scala:1702:60] assign hi_769 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_770; // @[Debug.scala:1702:60] assign hi_770 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_771; // @[Debug.scala:1702:60] assign hi_771 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_772; // @[Debug.scala:1702:60] assign hi_772 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_773; // @[Debug.scala:1702:60] assign hi_773 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_774; // @[Debug.scala:1702:60] assign hi_774 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_775; // @[Debug.scala:1702:60] assign hi_775 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_776; // @[Debug.scala:1702:60] assign hi_776 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_777; // @[Debug.scala:1702:60] assign hi_777 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_778; // @[Debug.scala:1702:60] assign hi_778 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_779; // @[Debug.scala:1702:60] assign hi_779 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_780; // @[Debug.scala:1702:60] assign hi_780 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_781; // @[Debug.scala:1702:60] assign hi_781 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_782; // @[Debug.scala:1702:60] assign hi_782 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_783; // @[Debug.scala:1702:60] assign hi_783 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_784; // @[Debug.scala:1702:60] assign hi_784 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_785; // @[Debug.scala:1702:60] assign hi_785 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_786; // @[Debug.scala:1702:60] assign hi_786 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_787; // @[Debug.scala:1702:60] assign hi_787 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_788; // @[Debug.scala:1702:60] assign hi_788 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_789; // @[Debug.scala:1702:60] assign hi_789 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_790; // @[Debug.scala:1702:60] assign hi_790 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_791; // @[Debug.scala:1702:60] assign hi_791 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_792; // @[Debug.scala:1702:60] assign hi_792 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_793; // @[Debug.scala:1702:60] assign hi_793 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_794; // @[Debug.scala:1702:60] assign hi_794 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_795; // @[Debug.scala:1702:60] assign hi_795 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_796; // @[Debug.scala:1702:60] assign hi_796 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_797; // @[Debug.scala:1702:60] assign hi_797 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_798; // @[Debug.scala:1702:60] assign hi_798 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_799; // @[Debug.scala:1702:60] assign hi_799 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_800; // @[Debug.scala:1702:60] assign hi_800 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_801; // @[Debug.scala:1702:60] assign hi_801 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_802; // @[Debug.scala:1702:60] assign hi_802 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_803; // @[Debug.scala:1702:60] assign hi_803 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_804; // @[Debug.scala:1702:60] assign hi_804 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_805; // @[Debug.scala:1702:60] assign hi_805 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_806; // @[Debug.scala:1702:60] assign hi_806 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_807; // @[Debug.scala:1702:60] assign hi_807 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_808; // @[Debug.scala:1702:60] assign hi_808 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_809; // @[Debug.scala:1702:60] assign hi_809 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_810; // @[Debug.scala:1702:60] assign hi_810 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_811; // @[Debug.scala:1702:60] assign hi_811 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_812; // @[Debug.scala:1702:60] assign hi_812 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_813; // @[Debug.scala:1702:60] assign hi_813 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_814; // @[Debug.scala:1702:60] assign hi_814 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_815; // @[Debug.scala:1702:60] assign hi_815 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_816; // @[Debug.scala:1702:60] assign hi_816 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_817; // @[Debug.scala:1702:60] assign hi_817 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_818; // @[Debug.scala:1702:60] assign hi_818 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_819; // @[Debug.scala:1702:60] assign hi_819 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_820; // @[Debug.scala:1702:60] assign hi_820 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_821; // @[Debug.scala:1702:60] assign hi_821 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_822; // @[Debug.scala:1702:60] assign hi_822 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_823; // @[Debug.scala:1702:60] assign hi_823 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_824; // @[Debug.scala:1702:60] assign hi_824 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_825; // @[Debug.scala:1702:60] assign hi_825 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_826; // @[Debug.scala:1702:60] assign hi_826 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_827; // @[Debug.scala:1702:60] assign hi_827 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_828; // @[Debug.scala:1702:60] assign hi_828 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_829; // @[Debug.scala:1702:60] assign hi_829 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_830; // @[Debug.scala:1702:60] assign hi_830 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_831; // @[Debug.scala:1702:60] assign hi_831 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_832; // @[Debug.scala:1702:60] assign hi_832 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_833; // @[Debug.scala:1702:60] assign hi_833 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_834; // @[Debug.scala:1702:60] assign hi_834 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_835; // @[Debug.scala:1702:60] assign hi_835 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_836; // @[Debug.scala:1702:60] assign hi_836 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_837; // @[Debug.scala:1702:60] assign hi_837 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_838; // @[Debug.scala:1702:60] assign hi_838 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_839; // @[Debug.scala:1702:60] assign hi_839 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_840; // @[Debug.scala:1702:60] assign hi_840 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_841; // @[Debug.scala:1702:60] assign hi_841 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_842; // @[Debug.scala:1702:60] assign hi_842 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_843; // @[Debug.scala:1702:60] assign hi_843 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_844; // @[Debug.scala:1702:60] assign hi_844 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_845; // @[Debug.scala:1702:60] assign hi_845 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_846; // @[Debug.scala:1702:60] assign hi_846 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_847; // @[Debug.scala:1702:60] assign hi_847 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_848; // @[Debug.scala:1702:60] assign hi_848 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_849; // @[Debug.scala:1702:60] assign hi_849 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_850; // @[Debug.scala:1702:60] assign hi_850 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_851; // @[Debug.scala:1702:60] assign hi_851 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_852; // @[Debug.scala:1702:60] assign hi_852 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_853; // @[Debug.scala:1702:60] assign hi_853 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_854; // @[Debug.scala:1702:60] assign hi_854 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_855; // @[Debug.scala:1702:60] assign hi_855 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_856; // @[Debug.scala:1702:60] assign hi_856 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_857; // @[Debug.scala:1702:60] assign hi_857 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_858; // @[Debug.scala:1702:60] assign hi_858 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_859; // @[Debug.scala:1702:60] assign hi_859 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_860; // @[Debug.scala:1702:60] assign hi_860 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_861; // @[Debug.scala:1702:60] assign hi_861 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_862; // @[Debug.scala:1702:60] assign hi_862 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_863; // @[Debug.scala:1702:60] assign hi_863 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_864; // @[Debug.scala:1702:60] assign hi_864 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_865; // @[Debug.scala:1702:60] assign hi_865 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_866; // @[Debug.scala:1702:60] assign hi_866 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_867; // @[Debug.scala:1702:60] assign hi_867 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_868; // @[Debug.scala:1702:60] assign hi_868 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_869; // @[Debug.scala:1702:60] assign hi_869 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_870; // @[Debug.scala:1702:60] assign hi_870 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_871; // @[Debug.scala:1702:60] assign hi_871 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_872; // @[Debug.scala:1702:60] assign hi_872 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_873; // @[Debug.scala:1702:60] assign hi_873 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_874; // @[Debug.scala:1702:60] assign hi_874 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_875; // @[Debug.scala:1702:60] assign hi_875 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_876; // @[Debug.scala:1702:60] assign hi_876 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_877; // @[Debug.scala:1702:60] assign hi_877 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_878; // @[Debug.scala:1702:60] assign hi_878 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_879; // @[Debug.scala:1702:60] assign hi_879 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_880; // @[Debug.scala:1702:60] assign hi_880 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_881; // @[Debug.scala:1702:60] assign hi_881 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_882; // @[Debug.scala:1702:60] assign hi_882 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_883; // @[Debug.scala:1702:60] assign hi_883 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_884; // @[Debug.scala:1702:60] assign hi_884 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_885; // @[Debug.scala:1702:60] assign hi_885 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_886; // @[Debug.scala:1702:60] assign hi_886 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_887; // @[Debug.scala:1702:60] assign hi_887 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_888; // @[Debug.scala:1702:60] assign hi_888 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_889; // @[Debug.scala:1702:60] assign hi_889 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_890; // @[Debug.scala:1702:60] assign hi_890 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_891; // @[Debug.scala:1702:60] assign hi_891 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_892; // @[Debug.scala:1702:60] assign hi_892 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_893; // @[Debug.scala:1702:60] assign hi_893 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_894; // @[Debug.scala:1702:60] assign hi_894 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_895; // @[Debug.scala:1702:60] assign hi_895 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_896; // @[Debug.scala:1702:60] assign hi_896 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_897; // @[Debug.scala:1702:60] assign hi_897 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_898; // @[Debug.scala:1702:60] assign hi_898 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_899; // @[Debug.scala:1702:60] assign hi_899 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_900; // @[Debug.scala:1702:60] assign hi_900 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_901; // @[Debug.scala:1702:60] assign hi_901 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_902; // @[Debug.scala:1702:60] assign hi_902 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_903; // @[Debug.scala:1702:60] assign hi_903 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_904; // @[Debug.scala:1702:60] assign hi_904 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_905; // @[Debug.scala:1702:60] assign hi_905 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_906; // @[Debug.scala:1702:60] assign hi_906 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_907; // @[Debug.scala:1702:60] assign hi_907 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_908; // @[Debug.scala:1702:60] assign hi_908 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_909; // @[Debug.scala:1702:60] assign hi_909 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_910; // @[Debug.scala:1702:60] assign hi_910 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_911; // @[Debug.scala:1702:60] assign hi_911 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_912; // @[Debug.scala:1702:60] assign hi_912 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_913; // @[Debug.scala:1702:60] assign hi_913 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_914; // @[Debug.scala:1702:60] assign hi_914 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_915; // @[Debug.scala:1702:60] assign hi_915 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_916; // @[Debug.scala:1702:60] assign hi_916 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_917; // @[Debug.scala:1702:60] assign hi_917 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_918; // @[Debug.scala:1702:60] assign hi_918 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_919; // @[Debug.scala:1702:60] assign hi_919 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_920; // @[Debug.scala:1702:60] assign hi_920 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_921; // @[Debug.scala:1702:60] assign hi_921 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_922; // @[Debug.scala:1702:60] assign hi_922 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_923; // @[Debug.scala:1702:60] assign hi_923 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_924; // @[Debug.scala:1702:60] assign hi_924 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_925; // @[Debug.scala:1702:60] assign hi_925 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_926; // @[Debug.scala:1702:60] assign hi_926 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_927; // @[Debug.scala:1702:60] assign hi_927 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_928; // @[Debug.scala:1702:60] assign hi_928 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_929; // @[Debug.scala:1702:60] assign hi_929 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_930; // @[Debug.scala:1702:60] assign hi_930 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_931; // @[Debug.scala:1702:60] assign hi_931 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_932; // @[Debug.scala:1702:60] assign hi_932 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_933; // @[Debug.scala:1702:60] assign hi_933 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_934; // @[Debug.scala:1702:60] assign hi_934 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_935; // @[Debug.scala:1702:60] assign hi_935 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_936; // @[Debug.scala:1702:60] assign hi_936 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_937; // @[Debug.scala:1702:60] assign hi_937 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_938; // @[Debug.scala:1702:60] assign hi_938 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_939; // @[Debug.scala:1702:60] assign hi_939 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_940; // @[Debug.scala:1702:60] assign hi_940 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_941; // @[Debug.scala:1702:60] assign hi_941 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_942; // @[Debug.scala:1702:60] assign hi_942 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_943; // @[Debug.scala:1702:60] assign hi_943 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_944; // @[Debug.scala:1702:60] assign hi_944 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_945; // @[Debug.scala:1702:60] assign hi_945 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_946; // @[Debug.scala:1702:60] assign hi_946 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_947; // @[Debug.scala:1702:60] assign hi_947 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_948; // @[Debug.scala:1702:60] assign hi_948 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_949; // @[Debug.scala:1702:60] assign hi_949 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_950; // @[Debug.scala:1702:60] assign hi_950 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_951; // @[Debug.scala:1702:60] assign hi_951 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_952; // @[Debug.scala:1702:60] assign hi_952 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_953; // @[Debug.scala:1702:60] assign hi_953 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_954; // @[Debug.scala:1702:60] assign hi_954 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_955; // @[Debug.scala:1702:60] assign hi_955 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_956; // @[Debug.scala:1702:60] assign hi_956 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_957; // @[Debug.scala:1702:60] assign hi_957 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_958; // @[Debug.scala:1702:60] assign hi_958 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_959; // @[Debug.scala:1702:60] assign hi_959 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_960; // @[Debug.scala:1702:60] assign hi_960 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_961; // @[Debug.scala:1702:60] assign hi_961 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_962; // @[Debug.scala:1702:60] assign hi_962 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_963; // @[Debug.scala:1702:60] assign hi_963 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_964; // @[Debug.scala:1702:60] assign hi_964 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_965; // @[Debug.scala:1702:60] assign hi_965 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_966; // @[Debug.scala:1702:60] assign hi_966 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_967; // @[Debug.scala:1702:60] assign hi_967 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_968; // @[Debug.scala:1702:60] assign hi_968 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_969; // @[Debug.scala:1702:60] assign hi_969 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_970; // @[Debug.scala:1702:60] assign hi_970 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_971; // @[Debug.scala:1702:60] assign hi_971 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_972; // @[Debug.scala:1702:60] assign hi_972 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_973; // @[Debug.scala:1702:60] assign hi_973 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_974; // @[Debug.scala:1702:60] assign hi_974 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_975; // @[Debug.scala:1702:60] assign hi_975 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_976; // @[Debug.scala:1702:60] assign hi_976 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_977; // @[Debug.scala:1702:60] assign hi_977 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_978; // @[Debug.scala:1702:60] assign hi_978 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_979; // @[Debug.scala:1702:60] assign hi_979 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_980; // @[Debug.scala:1702:60] assign hi_980 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_981; // @[Debug.scala:1702:60] assign hi_981 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_982; // @[Debug.scala:1702:60] assign hi_982 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_983; // @[Debug.scala:1702:60] assign hi_983 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_984; // @[Debug.scala:1702:60] assign hi_984 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_985; // @[Debug.scala:1702:60] assign hi_985 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_986; // @[Debug.scala:1702:60] assign hi_986 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_987; // @[Debug.scala:1702:60] assign hi_987 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_988; // @[Debug.scala:1702:60] assign hi_988 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_989; // @[Debug.scala:1702:60] assign hi_989 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_990; // @[Debug.scala:1702:60] assign hi_990 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_991; // @[Debug.scala:1702:60] assign hi_991 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_992; // @[Debug.scala:1702:60] assign hi_992 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_993; // @[Debug.scala:1702:60] assign hi_993 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_994; // @[Debug.scala:1702:60] assign hi_994 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_995; // @[Debug.scala:1702:60] assign hi_995 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_996; // @[Debug.scala:1702:60] assign hi_996 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_997; // @[Debug.scala:1702:60] assign hi_997 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_998; // @[Debug.scala:1702:60] assign hi_998 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_999; // @[Debug.scala:1702:60] assign hi_999 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1000; // @[Debug.scala:1702:60] assign hi_1000 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1001; // @[Debug.scala:1702:60] assign hi_1001 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1002; // @[Debug.scala:1702:60] assign hi_1002 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1003; // @[Debug.scala:1702:60] assign hi_1003 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1004; // @[Debug.scala:1702:60] assign hi_1004 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1005; // @[Debug.scala:1702:60] assign hi_1005 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1006; // @[Debug.scala:1702:60] assign hi_1006 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1007; // @[Debug.scala:1702:60] assign hi_1007 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1008; // @[Debug.scala:1702:60] assign hi_1008 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1009; // @[Debug.scala:1702:60] assign hi_1009 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1010; // @[Debug.scala:1702:60] assign hi_1010 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1011; // @[Debug.scala:1702:60] assign hi_1011 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1012; // @[Debug.scala:1702:60] assign hi_1012 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1013; // @[Debug.scala:1702:60] assign hi_1013 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1014; // @[Debug.scala:1702:60] assign hi_1014 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1015; // @[Debug.scala:1702:60] assign hi_1015 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1016; // @[Debug.scala:1702:60] assign hi_1016 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1017; // @[Debug.scala:1702:60] assign hi_1017 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1018; // @[Debug.scala:1702:60] assign hi_1018 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1019; // @[Debug.scala:1702:60] assign hi_1019 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1020; // @[Debug.scala:1702:60] assign hi_1020 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1021; // @[Debug.scala:1702:60] assign hi_1021 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1022; // @[Debug.scala:1702:60] assign hi_1022 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1023; // @[Debug.scala:1702:60] assign hi_1023 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1024; // @[Debug.scala:1702:60] assign hi_1024 = _GEN_16; // @[Debug.scala:1702:60] wire [7:0] _out_T_6436 = {hi_1, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6184 = {hi_9, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8824 = {hi_17, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12272 = {hi_25, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4125 = {hi_33, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4197 = {hi_41, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6256 = {hi_49, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8968 = {hi_57, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11984 = {hi_65, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4989 = {hi_73, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1917 = {hi_81, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11032 = {hi_89, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8304 = {hi_97, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5655 = {hi_105, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2509 = {hi_113, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10208 = {hi_121, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7478 = {hi_129, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9632 = {hi_137, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11464 = {hi_145, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3981 = {hi_153, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6830 = {hi_161, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7118 = {hi_169, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9704 = {hi_177, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11392 = {hi_185, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3245 = {hi_193, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2581 = {hi_201, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10064 = {hi_209, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8448 = {hi_217, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5439 = {hi_225, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3101 = {hi_233, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10728 = {hi_241, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7694 = {hi_249, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4845 = {hi_257, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6974 = {hi_265, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9256 = {hi_273, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12416 = {hi_281, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3533 = {hi_289, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5061 = {hi_297, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6740 = {hi_305, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9184 = {hi_313, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11680 = {hi_321, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5583 = {hi_329, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2133 = {hi_337, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10960 = {hi_345, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7838 = {hi_353, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6112 = {hi_361, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2653 = {hi_369, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10136 = {hi_377, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7190 = {hi_385, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9920 = {hi_393, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12344 = {hi_401, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3605 = {hi_409, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7046 = {hi_417, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7622 = {hi_425, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9992 = {hi_433, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11608 = {hi_441, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2869 = {hi_449, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2725 = {hi_457, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10800 = {hi_465, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7766 = {hi_473, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5511 = {hi_481, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3173 = {hi_489, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11536 = {hi_497, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7262 = {hi_505, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4917 = {hi_513, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5799 = {hi_521, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9560 = {hi_529, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12056 = {hi_537, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3029 = {hi_545, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5295 = {hi_553, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8520 = {hi_561, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9848 = {hi_569, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12488 = {hi_577, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4629 = {hi_585, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2437 = {hi_593, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10280 = {hi_601, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7334 = {hi_609, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6364 = {hi_617, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4413 = {hi_625, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11104 = {hi_633, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8214 = {hi_641, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9400 = {hi_649, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11824 = {hi_657, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3837 = {hi_665, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5871 = {hi_673, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8376 = {hi_681, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11176 = {hi_689, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12648 = {hi_697, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3461 = {hi_705, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2293 = {hi_713, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10352 = {hi_721, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7998 = {hi_729, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4701 = {hi_737, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4053 = {hi_745, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12720 = {hi_753, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8896 = {hi_761, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5367 = {hi_769, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5727 = {hi_777, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9040 = {hi_785, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12936 = {hi_793, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3317 = {hi_801, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5151 = {hi_809, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8070 = {hi_817, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10584 = {hi_825, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12792 = {hi_833, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4485 = {hi_841, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2061 = {hi_849, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11248 = {hi_857, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7550 = {hi_865, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6508 = {hi_873, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3765 = {hi_881, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12128 = {hi_889, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8680 = {hi_897, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9112 = {hi_905, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12200 = {hi_913, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4269 = {hi_921, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6668 = {hi_929, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8142 = {hi_937, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11320 = {hi_945, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2365 = {hi_953, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4557 = {hi_961, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1989 = {hi_969, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10512 = {hi_977, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8752 = {hi_985, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5223 = {hi_993, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3909 = {hi_1001, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12864 = {hi_1009, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9328 = {hi_1017, flags_0_go}; // @[RegisterRouter.scala:87:24] wire _out_in_ready_T_1; // @[RegisterRouter.scala:87:24] assign tlNodeIn_a_ready = in_1_ready; // @[RegisterRouter.scala:73:18] wire _in_bits_read_T_1; // @[RegisterRouter.scala:74:36] wire _out_front_valid_T_1 = in_1_valid; // @[RegisterRouter.scala:73:18, :87:24] wire [8:0] _in_bits_index_T_1; // @[Edges.scala:192:34] wire out_front_1_bits_read = in_1_bits_read; // @[RegisterRouter.scala:73:18, :87:24] wire [8:0] out_front_1_bits_index = in_1_bits_index; // @[RegisterRouter.scala:73:18, :87:24] wire [63:0] out_front_1_bits_data = in_1_bits_data; // @[RegisterRouter.scala:73:18, :87:24] wire [7:0] out_front_1_bits_mask = in_1_bits_mask; // @[RegisterRouter.scala:73:18, :87:24] wire [10:0] out_front_1_bits_extra_tlrr_extra_source = in_1_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24] wire [1:0] out_front_1_bits_extra_tlrr_extra_size = in_1_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24] assign _in_bits_read_T_1 = tlNodeIn_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] assign in_1_bits_read = _in_bits_read_T_1; // @[RegisterRouter.scala:73:18, :74:36] assign _in_bits_index_T_1 = tlNodeIn_a_bits_address[11:3]; // @[Edges.scala:192:34] assign in_1_bits_index = _in_bits_index_T_1; // @[RegisterRouter.scala:73:18] wire _out_front_ready_T_1 = out_1_ready; // @[RegisterRouter.scala:87:24] wire _out_out_valid_T_1; // @[RegisterRouter.scala:87:24] assign tlNodeIn_d_valid = out_1_valid; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_T_9; // @[RegisterRouter.scala:87:24] wire _tlNodeIn_d_bits_opcode_T = out_1_bits_read; // @[RegisterRouter.scala:87:24, :105:25] assign tlNodeIn_d_bits_data = out_1_bits_data; // @[RegisterRouter.scala:87:24] assign tlNodeIn_d_bits_d_source = out_1_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [1:0] out_1_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign tlNodeIn_d_bits_d_size = out_1_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign _out_in_ready_T_1 = out_front_1_ready; // @[RegisterRouter.scala:87:24] assign _out_out_valid_T_1 = out_front_1_valid; // @[RegisterRouter.scala:87:24] assign out_1_bits_read = out_front_1_bits_read; // @[RegisterRouter.scala:87:24] assign out_1_bits_extra_tlrr_extra_source = out_front_1_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] assign out_1_bits_extra_tlrr_extra_size = out_front_1_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] wire [8:0] _GEN_17 = out_front_1_bits_index & 9'h100; // @[RegisterRouter.scala:87:24] wire [8:0] out_findex_1; // @[RegisterRouter.scala:87:24] assign out_findex_1 = _GEN_17; // @[RegisterRouter.scala:87:24] wire [8:0] out_bindex_1; // @[RegisterRouter.scala:87:24] assign out_bindex_1 = _GEN_17; // @[RegisterRouter.scala:87:24] wire _GEN_18 = out_findex_1 == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_T_1600; // @[RegisterRouter.scala:87:24] assign _out_T_1600 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1602; // @[RegisterRouter.scala:87:24] assign _out_T_1602 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1604; // @[RegisterRouter.scala:87:24] assign _out_T_1604 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1606; // @[RegisterRouter.scala:87:24] assign _out_T_1606 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1608; // @[RegisterRouter.scala:87:24] assign _out_T_1608 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1610; // @[RegisterRouter.scala:87:24] assign _out_T_1610 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1612; // @[RegisterRouter.scala:87:24] assign _out_T_1612 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1614; // @[RegisterRouter.scala:87:24] assign _out_T_1614 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1616; // @[RegisterRouter.scala:87:24] assign _out_T_1616 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1618; // @[RegisterRouter.scala:87:24] assign _out_T_1618 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1620; // @[RegisterRouter.scala:87:24] assign _out_T_1620 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1622; // @[RegisterRouter.scala:87:24] assign _out_T_1622 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1626; // @[RegisterRouter.scala:87:24] assign _out_T_1626 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1628; // @[RegisterRouter.scala:87:24] assign _out_T_1628 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1630; // @[RegisterRouter.scala:87:24] assign _out_T_1630 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1632; // @[RegisterRouter.scala:87:24] assign _out_T_1632 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1634; // @[RegisterRouter.scala:87:24] assign _out_T_1634 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1636; // @[RegisterRouter.scala:87:24] assign _out_T_1636 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1638; // @[RegisterRouter.scala:87:24] assign _out_T_1638 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1642; // @[RegisterRouter.scala:87:24] assign _out_T_1642 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1644; // @[RegisterRouter.scala:87:24] assign _out_T_1644 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1646; // @[RegisterRouter.scala:87:24] assign _out_T_1646 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1648; // @[RegisterRouter.scala:87:24] assign _out_T_1648 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1650; // @[RegisterRouter.scala:87:24] assign _out_T_1650 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1652; // @[RegisterRouter.scala:87:24] assign _out_T_1652 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1654; // @[RegisterRouter.scala:87:24] assign _out_T_1654 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1656; // @[RegisterRouter.scala:87:24] assign _out_T_1656 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1658; // @[RegisterRouter.scala:87:24] assign _out_T_1658 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1660; // @[RegisterRouter.scala:87:24] assign _out_T_1660 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1662; // @[RegisterRouter.scala:87:24] assign _out_T_1662 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1664; // @[RegisterRouter.scala:87:24] assign _out_T_1664 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1668; // @[RegisterRouter.scala:87:24] assign _out_T_1668 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1670; // @[RegisterRouter.scala:87:24] assign _out_T_1670 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1672; // @[RegisterRouter.scala:87:24] assign _out_T_1672 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1674; // @[RegisterRouter.scala:87:24] assign _out_T_1674 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1676; // @[RegisterRouter.scala:87:24] assign _out_T_1676 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1680; // @[RegisterRouter.scala:87:24] assign _out_T_1680 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1682; // @[RegisterRouter.scala:87:24] assign _out_T_1682 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1684; // @[RegisterRouter.scala:87:24] assign _out_T_1684 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1686; // @[RegisterRouter.scala:87:24] assign _out_T_1686 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1688; // @[RegisterRouter.scala:87:24] assign _out_T_1688 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1690; // @[RegisterRouter.scala:87:24] assign _out_T_1690 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1692; // @[RegisterRouter.scala:87:24] assign _out_T_1692 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1694; // @[RegisterRouter.scala:87:24] assign _out_T_1694 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1696; // @[RegisterRouter.scala:87:24] assign _out_T_1696 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1698; // @[RegisterRouter.scala:87:24] assign _out_T_1698 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1700; // @[RegisterRouter.scala:87:24] assign _out_T_1700 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1702; // @[RegisterRouter.scala:87:24] assign _out_T_1702 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1704; // @[RegisterRouter.scala:87:24] assign _out_T_1704 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1706; // @[RegisterRouter.scala:87:24] assign _out_T_1706 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1708; // @[RegisterRouter.scala:87:24] assign _out_T_1708 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1710; // @[RegisterRouter.scala:87:24] assign _out_T_1710 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1712; // @[RegisterRouter.scala:87:24] assign _out_T_1712 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1714; // @[RegisterRouter.scala:87:24] assign _out_T_1714 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1718; // @[RegisterRouter.scala:87:24] assign _out_T_1718 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1720; // @[RegisterRouter.scala:87:24] assign _out_T_1720 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1722; // @[RegisterRouter.scala:87:24] assign _out_T_1722 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1726; // @[RegisterRouter.scala:87:24] assign _out_T_1726 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1728; // @[RegisterRouter.scala:87:24] assign _out_T_1728 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1730; // @[RegisterRouter.scala:87:24] assign _out_T_1730 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1732; // @[RegisterRouter.scala:87:24] assign _out_T_1732 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1734; // @[RegisterRouter.scala:87:24] assign _out_T_1734 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1736; // @[RegisterRouter.scala:87:24] assign _out_T_1736 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1738; // @[RegisterRouter.scala:87:24] assign _out_T_1738 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1740; // @[RegisterRouter.scala:87:24] assign _out_T_1740 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1744; // @[RegisterRouter.scala:87:24] assign _out_T_1744 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1746; // @[RegisterRouter.scala:87:24] assign _out_T_1746 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1748; // @[RegisterRouter.scala:87:24] assign _out_T_1748 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1750; // @[RegisterRouter.scala:87:24] assign _out_T_1750 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1752; // @[RegisterRouter.scala:87:24] assign _out_T_1752 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1754; // @[RegisterRouter.scala:87:24] assign _out_T_1754 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1758; // @[RegisterRouter.scala:87:24] assign _out_T_1758 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1760; // @[RegisterRouter.scala:87:24] assign _out_T_1760 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1762; // @[RegisterRouter.scala:87:24] assign _out_T_1762 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1764; // @[RegisterRouter.scala:87:24] assign _out_T_1764 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1766; // @[RegisterRouter.scala:87:24] assign _out_T_1766 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1768; // @[RegisterRouter.scala:87:24] assign _out_T_1768 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1770; // @[RegisterRouter.scala:87:24] assign _out_T_1770 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1772; // @[RegisterRouter.scala:87:24] assign _out_T_1772 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1774; // @[RegisterRouter.scala:87:24] assign _out_T_1774 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1776; // @[RegisterRouter.scala:87:24] assign _out_T_1776 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1778; // @[RegisterRouter.scala:87:24] assign _out_T_1778 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1780; // @[RegisterRouter.scala:87:24] assign _out_T_1780 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1782; // @[RegisterRouter.scala:87:24] assign _out_T_1782 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1784; // @[RegisterRouter.scala:87:24] assign _out_T_1784 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1786; // @[RegisterRouter.scala:87:24] assign _out_T_1786 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1788; // @[RegisterRouter.scala:87:24] assign _out_T_1788 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1790; // @[RegisterRouter.scala:87:24] assign _out_T_1790 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1792; // @[RegisterRouter.scala:87:24] assign _out_T_1792 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1794; // @[RegisterRouter.scala:87:24] assign _out_T_1794 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1796; // @[RegisterRouter.scala:87:24] assign _out_T_1796 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1798; // @[RegisterRouter.scala:87:24] assign _out_T_1798 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1800; // @[RegisterRouter.scala:87:24] assign _out_T_1800 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1802; // @[RegisterRouter.scala:87:24] assign _out_T_1802 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1804; // @[RegisterRouter.scala:87:24] assign _out_T_1804 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1806; // @[RegisterRouter.scala:87:24] assign _out_T_1806 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1808; // @[RegisterRouter.scala:87:24] assign _out_T_1808 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1810; // @[RegisterRouter.scala:87:24] assign _out_T_1810 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1812; // @[RegisterRouter.scala:87:24] assign _out_T_1812 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1814; // @[RegisterRouter.scala:87:24] assign _out_T_1814 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1816; // @[RegisterRouter.scala:87:24] assign _out_T_1816 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1818; // @[RegisterRouter.scala:87:24] assign _out_T_1818 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1820; // @[RegisterRouter.scala:87:24] assign _out_T_1820 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1824; // @[RegisterRouter.scala:87:24] assign _out_T_1824 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1826; // @[RegisterRouter.scala:87:24] assign _out_T_1826 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1828; // @[RegisterRouter.scala:87:24] assign _out_T_1828 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1830; // @[RegisterRouter.scala:87:24] assign _out_T_1830 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1832; // @[RegisterRouter.scala:87:24] assign _out_T_1832 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1834; // @[RegisterRouter.scala:87:24] assign _out_T_1834 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1836; // @[RegisterRouter.scala:87:24] assign _out_T_1836 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1838; // @[RegisterRouter.scala:87:24] assign _out_T_1838 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1840; // @[RegisterRouter.scala:87:24] assign _out_T_1840 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1842; // @[RegisterRouter.scala:87:24] assign _out_T_1842 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1844; // @[RegisterRouter.scala:87:24] assign _out_T_1844 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1848; // @[RegisterRouter.scala:87:24] assign _out_T_1848 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1850; // @[RegisterRouter.scala:87:24] assign _out_T_1850 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1852; // @[RegisterRouter.scala:87:24] assign _out_T_1852 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1854; // @[RegisterRouter.scala:87:24] assign _out_T_1854 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1856; // @[RegisterRouter.scala:87:24] assign _out_T_1856 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1858; // @[RegisterRouter.scala:87:24] assign _out_T_1858 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1860; // @[RegisterRouter.scala:87:24] assign _out_T_1860 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1862; // @[RegisterRouter.scala:87:24] assign _out_T_1862 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1864; // @[RegisterRouter.scala:87:24] assign _out_T_1864 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1866; // @[RegisterRouter.scala:87:24] assign _out_T_1866 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1868; // @[RegisterRouter.scala:87:24] assign _out_T_1868 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1870; // @[RegisterRouter.scala:87:24] assign _out_T_1870 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1872; // @[RegisterRouter.scala:87:24] assign _out_T_1872 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1874; // @[RegisterRouter.scala:87:24] assign _out_T_1874 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1878; // @[RegisterRouter.scala:87:24] assign _out_T_1878 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1880; // @[RegisterRouter.scala:87:24] assign _out_T_1880 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1882; // @[RegisterRouter.scala:87:24] assign _out_T_1882 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1884; // @[RegisterRouter.scala:87:24] assign _out_T_1884 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1886; // @[RegisterRouter.scala:87:24] assign _out_T_1886 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1888; // @[RegisterRouter.scala:87:24] assign _out_T_1888 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1890; // @[RegisterRouter.scala:87:24] assign _out_T_1890 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1892; // @[RegisterRouter.scala:87:24] assign _out_T_1892 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1894; // @[RegisterRouter.scala:87:24] assign _out_T_1894 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1896; // @[RegisterRouter.scala:87:24] assign _out_T_1896 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1898; // @[RegisterRouter.scala:87:24] assign _out_T_1898 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1900; // @[RegisterRouter.scala:87:24] assign _out_T_1900 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1902; // @[RegisterRouter.scala:87:24] assign _out_T_1902 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1904; // @[RegisterRouter.scala:87:24] assign _out_T_1904 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1906; // @[RegisterRouter.scala:87:24] assign _out_T_1906 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1908; // @[RegisterRouter.scala:87:24] assign _out_T_1908 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _GEN_19 = out_bindex_1 == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_T_1601; // @[RegisterRouter.scala:87:24] assign _out_T_1601 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1603; // @[RegisterRouter.scala:87:24] assign _out_T_1603 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1605; // @[RegisterRouter.scala:87:24] assign _out_T_1605 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1607; // @[RegisterRouter.scala:87:24] assign _out_T_1607 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1609; // @[RegisterRouter.scala:87:24] assign _out_T_1609 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1611; // @[RegisterRouter.scala:87:24] assign _out_T_1611 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1613; // @[RegisterRouter.scala:87:24] assign _out_T_1613 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1615; // @[RegisterRouter.scala:87:24] assign _out_T_1615 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1617; // @[RegisterRouter.scala:87:24] assign _out_T_1617 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1619; // @[RegisterRouter.scala:87:24] assign _out_T_1619 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1621; // @[RegisterRouter.scala:87:24] assign _out_T_1621 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1623; // @[RegisterRouter.scala:87:24] assign _out_T_1623 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1627; // @[RegisterRouter.scala:87:24] assign _out_T_1627 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1629; // @[RegisterRouter.scala:87:24] assign _out_T_1629 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1631; // @[RegisterRouter.scala:87:24] assign _out_T_1631 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1633; // @[RegisterRouter.scala:87:24] assign _out_T_1633 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1635; // @[RegisterRouter.scala:87:24] assign _out_T_1635 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1637; // @[RegisterRouter.scala:87:24] assign _out_T_1637 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1639; // @[RegisterRouter.scala:87:24] assign _out_T_1639 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1643; // @[RegisterRouter.scala:87:24] assign _out_T_1643 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1645; // @[RegisterRouter.scala:87:24] assign _out_T_1645 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1647; // @[RegisterRouter.scala:87:24] assign _out_T_1647 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1649; // @[RegisterRouter.scala:87:24] assign _out_T_1649 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1651; // @[RegisterRouter.scala:87:24] assign _out_T_1651 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1653; // @[RegisterRouter.scala:87:24] assign _out_T_1653 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1655; // @[RegisterRouter.scala:87:24] assign _out_T_1655 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1657; // @[RegisterRouter.scala:87:24] assign _out_T_1657 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1659; // @[RegisterRouter.scala:87:24] assign _out_T_1659 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1661; // @[RegisterRouter.scala:87:24] assign _out_T_1661 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1663; // @[RegisterRouter.scala:87:24] assign _out_T_1663 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1665; // @[RegisterRouter.scala:87:24] assign _out_T_1665 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1669; // @[RegisterRouter.scala:87:24] assign _out_T_1669 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1671; // @[RegisterRouter.scala:87:24] assign _out_T_1671 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1673; // @[RegisterRouter.scala:87:24] assign _out_T_1673 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1675; // @[RegisterRouter.scala:87:24] assign _out_T_1675 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1677; // @[RegisterRouter.scala:87:24] assign _out_T_1677 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1681; // @[RegisterRouter.scala:87:24] assign _out_T_1681 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1683; // @[RegisterRouter.scala:87:24] assign _out_T_1683 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1685; // @[RegisterRouter.scala:87:24] assign _out_T_1685 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1687; // @[RegisterRouter.scala:87:24] assign _out_T_1687 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1689; // @[RegisterRouter.scala:87:24] assign _out_T_1689 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1691; // @[RegisterRouter.scala:87:24] assign _out_T_1691 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1693; // @[RegisterRouter.scala:87:24] assign _out_T_1693 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1695; // @[RegisterRouter.scala:87:24] assign _out_T_1695 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1697; // @[RegisterRouter.scala:87:24] assign _out_T_1697 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1699; // @[RegisterRouter.scala:87:24] assign _out_T_1699 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1701; // @[RegisterRouter.scala:87:24] assign _out_T_1701 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1703; // @[RegisterRouter.scala:87:24] assign _out_T_1703 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1705; // @[RegisterRouter.scala:87:24] assign _out_T_1705 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1707; // @[RegisterRouter.scala:87:24] assign _out_T_1707 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1709; // @[RegisterRouter.scala:87:24] assign _out_T_1709 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1711; // @[RegisterRouter.scala:87:24] assign _out_T_1711 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1713; // @[RegisterRouter.scala:87:24] assign _out_T_1713 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1715; // @[RegisterRouter.scala:87:24] assign _out_T_1715 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1719; // @[RegisterRouter.scala:87:24] assign _out_T_1719 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1721; // @[RegisterRouter.scala:87:24] assign _out_T_1721 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1723; // @[RegisterRouter.scala:87:24] assign _out_T_1723 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1727; // @[RegisterRouter.scala:87:24] assign _out_T_1727 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1729; // @[RegisterRouter.scala:87:24] assign _out_T_1729 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1731; // @[RegisterRouter.scala:87:24] assign _out_T_1731 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1733; // @[RegisterRouter.scala:87:24] assign _out_T_1733 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1735; // @[RegisterRouter.scala:87:24] assign _out_T_1735 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1737; // @[RegisterRouter.scala:87:24] assign _out_T_1737 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1739; // @[RegisterRouter.scala:87:24] assign _out_T_1739 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1741; // @[RegisterRouter.scala:87:24] assign _out_T_1741 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1745; // @[RegisterRouter.scala:87:24] assign _out_T_1745 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1747; // @[RegisterRouter.scala:87:24] assign _out_T_1747 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1749; // @[RegisterRouter.scala:87:24] assign _out_T_1749 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1751; // @[RegisterRouter.scala:87:24] assign _out_T_1751 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1753; // @[RegisterRouter.scala:87:24] assign _out_T_1753 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1755; // @[RegisterRouter.scala:87:24] assign _out_T_1755 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1759; // @[RegisterRouter.scala:87:24] assign _out_T_1759 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1761; // @[RegisterRouter.scala:87:24] assign _out_T_1761 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1763; // @[RegisterRouter.scala:87:24] assign _out_T_1763 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1765; // @[RegisterRouter.scala:87:24] assign _out_T_1765 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1767; // @[RegisterRouter.scala:87:24] assign _out_T_1767 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1769; // @[RegisterRouter.scala:87:24] assign _out_T_1769 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1771; // @[RegisterRouter.scala:87:24] assign _out_T_1771 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1773; // @[RegisterRouter.scala:87:24] assign _out_T_1773 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1775; // @[RegisterRouter.scala:87:24] assign _out_T_1775 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1777; // @[RegisterRouter.scala:87:24] assign _out_T_1777 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1779; // @[RegisterRouter.scala:87:24] assign _out_T_1779 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1781; // @[RegisterRouter.scala:87:24] assign _out_T_1781 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1783; // @[RegisterRouter.scala:87:24] assign _out_T_1783 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1785; // @[RegisterRouter.scala:87:24] assign _out_T_1785 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1787; // @[RegisterRouter.scala:87:24] assign _out_T_1787 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1789; // @[RegisterRouter.scala:87:24] assign _out_T_1789 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1791; // @[RegisterRouter.scala:87:24] assign _out_T_1791 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1793; // @[RegisterRouter.scala:87:24] assign _out_T_1793 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1795; // @[RegisterRouter.scala:87:24] assign _out_T_1795 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1797; // @[RegisterRouter.scala:87:24] assign _out_T_1797 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1799; // @[RegisterRouter.scala:87:24] assign _out_T_1799 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1801; // @[RegisterRouter.scala:87:24] assign _out_T_1801 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1803; // @[RegisterRouter.scala:87:24] assign _out_T_1803 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1805; // @[RegisterRouter.scala:87:24] assign _out_T_1805 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1807; // @[RegisterRouter.scala:87:24] assign _out_T_1807 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1809; // @[RegisterRouter.scala:87:24] assign _out_T_1809 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1811; // @[RegisterRouter.scala:87:24] assign _out_T_1811 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1813; // @[RegisterRouter.scala:87:24] assign _out_T_1813 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1815; // @[RegisterRouter.scala:87:24] assign _out_T_1815 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1817; // @[RegisterRouter.scala:87:24] assign _out_T_1817 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1819; // @[RegisterRouter.scala:87:24] assign _out_T_1819 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1821; // @[RegisterRouter.scala:87:24] assign _out_T_1821 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1825; // @[RegisterRouter.scala:87:24] assign _out_T_1825 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1827; // @[RegisterRouter.scala:87:24] assign _out_T_1827 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1829; // @[RegisterRouter.scala:87:24] assign _out_T_1829 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1831; // @[RegisterRouter.scala:87:24] assign _out_T_1831 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1833; // @[RegisterRouter.scala:87:24] assign _out_T_1833 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1835; // @[RegisterRouter.scala:87:24] assign _out_T_1835 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1837; // @[RegisterRouter.scala:87:24] assign _out_T_1837 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1839; // @[RegisterRouter.scala:87:24] assign _out_T_1839 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1841; // @[RegisterRouter.scala:87:24] assign _out_T_1841 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1843; // @[RegisterRouter.scala:87:24] assign _out_T_1843 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1845; // @[RegisterRouter.scala:87:24] assign _out_T_1845 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1849; // @[RegisterRouter.scala:87:24] assign _out_T_1849 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1851; // @[RegisterRouter.scala:87:24] assign _out_T_1851 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1853; // @[RegisterRouter.scala:87:24] assign _out_T_1853 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1855; // @[RegisterRouter.scala:87:24] assign _out_T_1855 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1857; // @[RegisterRouter.scala:87:24] assign _out_T_1857 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1859; // @[RegisterRouter.scala:87:24] assign _out_T_1859 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1861; // @[RegisterRouter.scala:87:24] assign _out_T_1861 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1863; // @[RegisterRouter.scala:87:24] assign _out_T_1863 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1865; // @[RegisterRouter.scala:87:24] assign _out_T_1865 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1867; // @[RegisterRouter.scala:87:24] assign _out_T_1867 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1869; // @[RegisterRouter.scala:87:24] assign _out_T_1869 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1871; // @[RegisterRouter.scala:87:24] assign _out_T_1871 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1873; // @[RegisterRouter.scala:87:24] assign _out_T_1873 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1875; // @[RegisterRouter.scala:87:24] assign _out_T_1875 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1879; // @[RegisterRouter.scala:87:24] assign _out_T_1879 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1881; // @[RegisterRouter.scala:87:24] assign _out_T_1881 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1883; // @[RegisterRouter.scala:87:24] assign _out_T_1883 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1885; // @[RegisterRouter.scala:87:24] assign _out_T_1885 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1887; // @[RegisterRouter.scala:87:24] assign _out_T_1887 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1889; // @[RegisterRouter.scala:87:24] assign _out_T_1889 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1891; // @[RegisterRouter.scala:87:24] assign _out_T_1891 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1893; // @[RegisterRouter.scala:87:24] assign _out_T_1893 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1895; // @[RegisterRouter.scala:87:24] assign _out_T_1895 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1897; // @[RegisterRouter.scala:87:24] assign _out_T_1897 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1899; // @[RegisterRouter.scala:87:24] assign _out_T_1899 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1901; // @[RegisterRouter.scala:87:24] assign _out_T_1901 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1903; // @[RegisterRouter.scala:87:24] assign _out_T_1903 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1905; // @[RegisterRouter.scala:87:24] assign _out_T_1905 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1907; // @[RegisterRouter.scala:87:24] assign _out_T_1907 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1909; // @[RegisterRouter.scala:87:24] assign _out_T_1909 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_2_138 = _out_T_1601; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_249 = _out_T_1603; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_234 = _out_T_1605; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_170 = _out_T_1607; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_115 = _out_T_1609; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_217 = _out_T_1611; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_247 = _out_T_1613; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_202 = _out_T_1615; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_142 = _out_T_1617; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_153 = _out_T_1619; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_174 = _out_T_1621; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_185 = _out_T_1623; // @[MuxLiteral.scala:49:48] wire _GEN_20 = out_findex_1 == 9'h100; // @[RegisterRouter.scala:87:24] wire _out_T_1624; // @[RegisterRouter.scala:87:24] assign _out_T_1624 = _GEN_20; // @[RegisterRouter.scala:87:24] wire _out_T_1640; // @[RegisterRouter.scala:87:24] assign _out_T_1640 = _GEN_20; // @[RegisterRouter.scala:87:24] wire _out_T_1666; // @[RegisterRouter.scala:87:24] assign _out_T_1666 = _GEN_20; // @[RegisterRouter.scala:87:24] wire _out_T_1678; // @[RegisterRouter.scala:87:24] assign _out_T_1678 = _GEN_20; // @[RegisterRouter.scala:87:24] wire _out_T_1716; // @[RegisterRouter.scala:87:24] assign _out_T_1716 = _GEN_20; // @[RegisterRouter.scala:87:24] wire _out_T_1724; // @[RegisterRouter.scala:87:24] assign _out_T_1724 = _GEN_20; // @[RegisterRouter.scala:87:24] wire _out_T_1742; // @[RegisterRouter.scala:87:24] assign _out_T_1742 = _GEN_20; // @[RegisterRouter.scala:87:24] wire _out_T_1756; // @[RegisterRouter.scala:87:24] assign _out_T_1756 = _GEN_20; // @[RegisterRouter.scala:87:24] wire _out_T_1822; // @[RegisterRouter.scala:87:24] assign _out_T_1822 = _GEN_20; // @[RegisterRouter.scala:87:24] wire _out_T_1846; // @[RegisterRouter.scala:87:24] assign _out_T_1846 = _GEN_20; // @[RegisterRouter.scala:87:24] wire _out_T_1876; // @[RegisterRouter.scala:87:24] assign _out_T_1876 = _GEN_20; // @[RegisterRouter.scala:87:24] wire _GEN_21 = out_bindex_1 == 9'h100; // @[RegisterRouter.scala:87:24] wire _out_T_1625; // @[RegisterRouter.scala:87:24] assign _out_T_1625 = _GEN_21; // @[RegisterRouter.scala:87:24] wire _out_T_1641; // @[RegisterRouter.scala:87:24] assign _out_T_1641 = _GEN_21; // @[RegisterRouter.scala:87:24] wire _out_T_1667; // @[RegisterRouter.scala:87:24] assign _out_T_1667 = _GEN_21; // @[RegisterRouter.scala:87:24] wire _out_T_1679; // @[RegisterRouter.scala:87:24] assign _out_T_1679 = _GEN_21; // @[RegisterRouter.scala:87:24] wire _out_T_1717; // @[RegisterRouter.scala:87:24] assign _out_T_1717 = _GEN_21; // @[RegisterRouter.scala:87:24] wire _out_T_1725; // @[RegisterRouter.scala:87:24] assign _out_T_1725 = _GEN_21; // @[RegisterRouter.scala:87:24] wire _out_T_1743; // @[RegisterRouter.scala:87:24] assign _out_T_1743 = _GEN_21; // @[RegisterRouter.scala:87:24] wire _out_T_1757; // @[RegisterRouter.scala:87:24] assign _out_T_1757 = _GEN_21; // @[RegisterRouter.scala:87:24] wire _out_T_1823; // @[RegisterRouter.scala:87:24] assign _out_T_1823 = _GEN_21; // @[RegisterRouter.scala:87:24] wire _out_T_1847; // @[RegisterRouter.scala:87:24] assign _out_T_1847 = _GEN_21; // @[RegisterRouter.scala:87:24] wire _out_T_1877; // @[RegisterRouter.scala:87:24] assign _out_T_1877 = _GEN_21; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_2_1 = _out_T_1625; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_184 = _out_T_1627; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_110 = _out_T_1629; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_196 = _out_T_1631; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_157 = _out_T_1633; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_189 = _out_T_1635; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_152 = _out_T_1637; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_228 = _out_T_1639; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_5 = _out_T_1641; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_216 = _out_T_1643; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_164 = _out_T_1645; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_179 = _out_T_1647; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_106 = _out_T_1649; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_238 = _out_T_1651; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_211 = _out_T_1653; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_253 = _out_T_1655; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_147 = _out_T_1657; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_221 = _out_T_1659; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_132 = _out_T_1661; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_133 = _out_T_1663; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_243 = _out_T_1665; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_9 = _out_T_1667; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_206 = _out_T_1669; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_233 = _out_T_1671; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_248 = _out_T_1673; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_201 = _out_T_1675; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_220 = _out_T_1677; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_4 = _out_T_1679; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_160 = _out_T_1681; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_192 = _out_T_1683; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_137 = _out_T_1685; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_165 = _out_T_1687; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_33 = _out_T_1689; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_229 = _out_T_1691; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_252 = _out_T_1693; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_197 = _out_T_1695; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_224 = _out_T_1697; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_156 = _out_T_1699; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_188 = _out_T_1701; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_169 = _out_T_1703; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_141 = _out_T_1705; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_225 = _out_T_1707; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_193 = _out_T_1709; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_212 = _out_T_1711; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_96 = _out_T_1713; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_109 = _out_T_1715; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_0 = _out_T_1717; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_173 = _out_T_1719; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_129 = _out_T_1721; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_134 = _out_T_1723; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_10 = _out_T_1725; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_205 = _out_T_1727; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_128 = _out_T_1729; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_237 = _out_T_1731; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_105 = _out_T_1733; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_244 = _out_T_1735; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_166 = _out_T_1737; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_32 = _out_T_1739; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_148 = _out_T_1741; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_8 = _out_T_1743; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_161 = _out_T_1745; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_180 = _out_T_1747; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_149 = _out_T_1749; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_176 = _out_T_1751; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_191 = _out_T_1753; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_204 = _out_T_1755; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_3 = _out_T_1757; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_144 = _out_T_1759; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_236 = _out_T_1761; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_181 = _out_T_1763; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_159 = _out_T_1765; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_187 = _out_T_1767; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_172 = _out_T_1769; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_113 = _out_T_1771; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_219 = _out_T_1773; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_230 = _out_T_1775; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_245 = _out_T_1777; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_208 = _out_T_1779; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_103 = _out_T_1781; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_140 = _out_T_1783; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_213 = _out_T_1785; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_155 = _out_T_1787; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_198 = _out_T_1789; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_108 = _out_T_1791; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_240 = _out_T_1793; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_251 = _out_T_1795; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_130 = _out_T_1797; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_223 = _out_T_1799; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_135 = _out_T_1801; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_226 = _out_T_1803; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_241 = _out_T_1805; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_167 = _out_T_1807; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_162 = _out_T_1809; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_255 = _out_T_1811; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_209 = _out_T_1813; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_112 = _out_T_1815; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_194 = _out_T_1817; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_145 = _out_T_1819; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_150 = _out_T_1821; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_7 = _out_T_1823; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_199 = _out_T_1825; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_177 = _out_T_1827; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_182 = _out_T_1829; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_154 = _out_T_1831; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_175 = _out_T_1833; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_143 = _out_T_1835; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_203 = _out_T_1837; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_218 = _out_T_1839; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_104 = _out_T_1841; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_250 = _out_T_1843; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_231 = _out_T_1845; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_2 = _out_T_1847; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_158 = _out_T_1849; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_186 = _out_T_1851; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_114 = _out_T_1853; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_171 = _out_T_1855; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_139 = _out_T_1857; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_207 = _out_T_1859; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_214 = _out_T_1861; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_235 = _out_T_1863; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_246 = _out_T_1865; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_151 = _out_T_1867; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_146 = _out_T_1869; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_190 = _out_T_1871; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_183 = _out_T_1873; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_168 = _out_T_1875; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_6 = _out_T_1877; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_210 = _out_T_1879; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_107 = _out_T_1881; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_136 = _out_T_1883; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_195 = _out_T_1885; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_239 = _out_T_1887; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_242 = _out_T_1889; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_131 = _out_T_1891; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_178 = _out_T_1893; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_163 = _out_T_1895; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_200 = _out_T_1897; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_111 = _out_T_1899; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_215 = _out_T_1901; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_222 = _out_T_1903; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_232 = _out_T_1905; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_254 = _out_T_1907; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_T_814; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_2_227 = _out_T_1909; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_T_1258; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1198; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_942; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_722; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1130; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1250; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1070; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_830; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_874; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_958; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1002; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_266; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_998; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_702; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1046; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_890; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1018; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_870; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1174; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_282; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1126; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_918; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_978; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_686; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1214; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1106; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1274; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_850; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1146; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_790; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_794; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1234; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_298; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1086; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1194; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1254; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1066; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1142; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_278; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_902; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1030; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_810; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_922; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_394; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1178; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1270; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1050; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1158; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_886; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1014; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_938; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_826; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1162; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1034; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1110; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_646; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_698; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_262; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_954; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_778; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_798; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_302; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1082; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_774; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1210; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_682; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1238; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_926; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_390; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_854; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_294; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_906; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_982; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_858; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_966; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1026; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1078; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_274; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_838; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1206; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_986; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_898; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1010; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_950; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_714; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1138; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1182; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1242; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1094; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_674; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_822; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1114; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_882; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1054; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_694; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1222; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1266; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_782; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1154; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_802; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1166; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1226; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_930; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_910; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1282; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1098; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_710; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1038; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_842; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_862; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_290; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1058; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_970; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_990; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_878; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_962; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_834; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1074; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1134; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_678; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1262; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1186; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_270; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_894; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1006; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_718; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_946; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_818; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1090; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1118; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1202; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1246; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_866; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_846; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1022; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_994; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_934; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_286; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1102; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_690; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_806; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1042; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1218; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1230; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_786; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_974; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_914; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1062; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_706; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1122; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1150; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1190; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1278; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1170; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_0; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_2; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_3; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_4; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_5; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_6; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_7; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_8; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_9; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_10; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_11; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_12; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_13; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_14; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_15; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_16; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_17; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_18; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_19; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_20; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_21; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_22; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_23; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_24; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_25; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_26; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_27; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_28; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_29; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_30; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_31; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_32; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_33; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_34; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_35; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_36; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_37; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_38; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_39; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_40; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_41; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_42; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_43; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_44; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_45; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_46; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_47; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_48; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_49; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_50; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_51; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_52; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_53; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_54; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_55; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_56; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_57; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_58; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_59; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_60; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_61; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_62; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_63; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_64; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_65; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_66; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_67; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_68; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_69; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_70; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_71; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_72; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_73; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_74; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_75; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_76; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_77; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_78; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_79; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_80; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_81; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_82; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_83; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_84; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_85; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_86; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_87; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_88; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_89; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_90; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_91; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_92; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_93; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_94; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_95; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_96; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_97; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_98; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_99; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_100; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_101; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_102; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_103; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_104; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_105; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_106; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_107; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_108; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_109; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_110; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_111; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_112; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_113; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_114; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_115; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_116; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_117; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_118; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_119; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_120; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_121; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_122; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_123; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_124; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_125; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_126; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_127; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_128; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_129; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_130; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_131; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_132; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_133; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_134; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_135; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_136; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_137; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_138; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_139; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_140; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_141; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_142; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_143; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_144; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_145; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_146; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_147; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_148; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_149; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_150; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_151; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_152; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_153; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_154; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_155; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_156; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_157; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_158; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_159; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_160; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_161; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_162; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_163; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_164; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_165; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_166; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_167; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_168; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_169; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_170; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_171; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_172; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_173; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_174; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_175; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_176; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_177; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_178; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_179; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_180; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_181; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_182; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_183; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_184; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_185; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_186; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_187; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_188; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_189; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_190; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_191; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_192; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_193; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_194; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_195; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_196; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_197; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_198; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_199; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_200; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_201; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_202; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_203; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_204; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_205; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_206; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_207; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_208; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_209; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_210; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_211; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_212; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_213; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_214; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_215; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_216; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_217; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_218; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_219; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_220; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_221; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_222; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_223; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_224; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_225; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_226; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_227; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_228; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_229; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_230; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_231; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_232; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_233; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_234; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_235; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_236; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_237; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_238; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_239; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_240; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_241; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_242; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_243; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_244; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_245; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_246; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_247; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_248; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_249; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_250; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_251; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_252; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_253; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_254; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_255; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_256; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_257; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_258; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_259; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_260; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_261; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_262; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_263; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_264; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_265; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_266; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_267; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_268; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_269; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_270; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_271; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_272; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_273; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_274; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_275; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_276; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_277; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_278; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_279; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_280; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_281; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_282; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_283; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_284; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_285; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_286; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_287; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_288; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_289; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_290; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_291; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_292; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_293; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_294; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_295; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_296; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_297; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_298; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_299; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_300; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_301; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_302; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_303; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_304; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_305; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_306; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_307; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_308; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_309; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_310; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_311; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_312; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_313; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_314; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_315; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_316; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_317; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_318; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_319; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_320; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_321; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_322; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_323; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_324; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_325; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_326; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_327; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_328; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_329; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_330; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_331; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_332; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_333; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_334; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_335; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_336; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_337; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_338; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_339; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_340; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_341; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_342; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_343; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_344; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_345; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_346; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_347; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_348; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_349; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_350; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_351; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_352; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_353; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_354; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_355; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_356; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_357; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_358; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_359; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_360; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_361; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_362; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_363; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_364; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_365; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_366; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_367; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_368; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_369; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_370; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_371; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_372; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_373; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_374; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_375; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_376; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_377; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_378; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_379; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_380; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_381; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_382; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_383; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_384; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_385; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_386; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_387; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_388; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_389; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_390; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_391; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_392; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_393; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_394; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_395; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_396; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_397; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_398; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_399; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_400; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_401; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_402; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_403; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_404; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_405; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_406; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_407; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_408; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_409; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_410; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_411; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_412; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_413; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_414; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_415; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_416; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_417; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_418; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_419; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_420; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_421; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_422; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_423; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_424; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_425; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_426; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_427; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_428; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_429; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_430; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_431; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_432; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_433; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_434; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_435; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_436; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_437; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_438; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_439; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_440; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_441; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_442; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_443; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_444; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_445; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_446; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_447; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_448; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_449; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_450; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_451; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_452; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_453; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_454; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_455; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_456; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_457; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_458; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_459; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_460; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_461; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_462; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_463; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_464; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_465; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_466; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_467; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_468; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_469; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_470; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_471; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_472; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_473; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_474; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_475; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_476; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_477; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_478; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_479; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_480; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_481; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_482; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_483; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_484; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_485; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_486; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_487; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_488; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_489; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_490; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_491; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_492; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_493; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_494; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_495; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_496; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_497; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_498; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_499; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_500; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_501; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_502; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_503; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_504; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_505; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_506; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_507; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_508; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_509; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_510; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_511; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_512; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_513; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_514; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_515; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_516; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_517; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_518; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_519; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_520; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_521; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_522; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_523; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_524; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_525; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_526; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_527; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_528; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_529; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_530; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_531; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_532; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_533; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_534; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_535; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_536; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_537; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_538; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_539; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_540; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_541; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_542; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_543; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_544; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_545; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_546; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_547; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_548; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_549; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_550; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_551; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_552; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_553; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_554; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_555; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_556; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_557; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_558; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_559; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_560; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_561; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_562; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_563; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_564; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_565; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_566; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_567; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_568; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_569; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_570; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_571; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_572; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_573; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_574; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_575; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_576; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_577; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_578; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_579; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_580; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_581; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_582; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_583; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_584; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_585; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_586; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_587; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_588; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_589; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_590; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_591; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_592; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_593; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_594; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_595; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_596; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_597; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_598; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_599; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_600; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_601; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_602; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_603; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_604; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_605; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_606; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_607; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_608; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_609; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_610; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_611; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_612; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_613; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_614; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_615; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_616; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_617; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_618; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_619; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_620; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_621; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_622; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_623; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_624; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_625; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_626; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_627; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_628; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_629; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_630; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_631; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_632; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_633; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_634; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_635; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_636; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_637; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_638; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_639; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_640; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_641; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_642; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_643; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_644; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_645; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_646; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_647; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_648; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_649; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_650; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_651; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_652; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_653; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_654; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_655; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_656; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_657; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_658; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_659; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_660; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_661; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_662; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_663; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_664; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_665; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_666; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_667; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_668; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_669; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_670; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_671; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_672; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_673; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_674; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_675; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_676; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_677; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_678; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_679; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_680; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_681; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_682; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_683; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_684; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_685; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_686; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_687; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_688; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_689; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_690; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_691; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_692; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_693; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_694; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_695; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_696; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_697; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_698; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_699; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_700; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_701; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_702; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_703; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_704; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_705; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_706; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_707; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_708; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_709; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_710; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_711; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_712; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_713; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_714; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_715; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_716; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_717; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_718; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_719; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_720; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_721; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_722; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_723; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_724; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_725; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_726; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_727; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_728; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_729; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_730; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_731; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_732; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_733; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_734; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_735; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_736; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_737; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_738; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_739; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_740; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_741; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_742; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_743; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_744; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_745; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_746; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_747; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_748; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_749; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_750; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_751; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_752; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_753; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_754; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_755; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_756; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_757; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_758; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_759; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_760; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_761; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_762; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_763; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_764; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_765; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_766; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_767; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_768; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_769; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_770; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_771; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_772; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_773; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_774; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_775; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_776; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_777; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_778; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_779; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_780; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_781; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_782; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_783; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_784; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_785; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_786; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_787; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_788; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_789; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_790; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_791; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_792; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_793; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_794; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_795; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_796; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_797; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_798; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_799; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_800; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_801; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_802; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_803; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_804; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_805; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_806; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_807; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_808; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_809; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_810; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_811; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_812; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_813; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_814; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_815; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_816; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_817; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_818; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_819; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_820; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_821; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_822; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_823; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_824; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_825; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_826; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_827; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_828; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_829; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_830; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_831; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_832; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_833; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_834; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_835; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_836; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_837; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_838; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_839; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_840; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_841; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_842; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_843; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_844; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_845; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_846; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_847; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_848; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_849; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_850; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_851; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_852; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_853; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_854; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_855; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_856; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_857; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_858; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_859; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_860; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_861; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_862; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_863; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_864; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_865; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_866; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_867; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_868; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_869; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_870; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_871; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_872; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_873; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_874; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_875; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_876; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_877; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_878; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_879; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_880; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_881; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_882; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_883; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_884; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_885; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_886; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_887; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_888; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_889; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_890; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_891; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_892; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_893; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_894; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_895; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_896; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_897; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_898; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_899; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_900; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_901; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_902; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_903; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_904; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_905; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_906; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_907; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_908; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_909; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_910; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_911; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_912; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_913; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_914; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_915; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_916; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_917; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_918; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_919; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_920; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_921; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_922; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_923; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_924; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_925; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_926; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_927; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_928; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_929; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_930; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_931; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_932; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_933; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_934; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_935; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_936; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_937; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_938; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_939; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_940; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_941; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_942; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_943; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_944; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_945; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_946; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_947; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_948; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_949; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_950; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_951; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_952; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_953; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_954; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_955; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_956; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_957; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_958; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_959; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_960; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_961; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_962; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_963; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_964; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_965; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_966; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_967; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_968; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_969; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_970; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_971; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_972; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_973; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_974; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_975; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_976; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_977; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_978; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_979; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_980; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_981; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_982; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_983; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_984; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_985; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_986; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_987; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_988; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_989; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_990; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_991; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_992; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_993; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_994; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_995; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_996; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_997; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_998; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_999; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1000; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1001; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1002; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1003; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1004; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1005; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1006; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1007; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1008; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1009; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1010; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1011; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1012; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1013; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1014; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1015; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1016; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1017; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1018; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1019; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1020; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1021; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1022; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1023; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1024; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1025; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1026; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1027; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1028; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1029; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1030; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1031; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1032; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1033; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1034; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1035; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1036; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1037; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1038; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1039; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1040; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1041; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1042; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1043; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1044; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1045; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1046; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1047; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1048; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1049; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1050; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1051; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1052; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1053; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1054; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1055; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1056; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1057; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1058; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1059; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1060; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1061; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1062; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1063; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1064; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1065; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1066; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1067; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1068; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1069; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1070; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1071; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1072; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1073; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1074; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1075; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1076; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1077; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1078; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1079; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1080; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1081; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1082; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1083; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1084; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1085; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1086; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1087; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1088; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1089; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1090; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1091; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1092; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1093; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1094; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1095; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1096; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1097; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1098; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1099; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1100; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1101; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1102; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1103; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1104; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1105; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1106; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1107; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1108; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1109; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1110; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1111; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1112; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1113; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1114; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1115; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1116; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1117; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1118; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1119; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1120; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1121; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1122; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1123; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1124; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1125; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1126; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1127; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1128; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1129; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1130; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1131; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1132; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1133; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1134; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1135; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1136; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1137; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1138; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1139; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1140; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1141; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1142; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1143; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1144; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1145; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1146; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1147; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1148; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1149; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1150; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1151; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1152; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1153; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1154; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1155; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1156; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1157; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1158; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1159; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1160; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1161; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1162; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1163; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1164; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1165; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1166; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1167; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1168; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1169; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1170; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1171; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1172; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1173; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1174; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1175; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1176; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1177; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1178; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1179; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1180; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1181; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1182; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1183; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1184; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1185; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1186; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1187; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1188; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1189; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1190; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1191; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1192; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1193; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1194; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1195; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1196; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1197; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1198; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1199; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1200; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1201; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1202; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1203; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1204; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1205; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1206; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1207; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1208; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1209; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1210; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_816; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1260; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1200; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_944; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_724; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1132; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1252; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1072; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_832; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_876; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_960; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1004; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_268; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1000; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_704; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1048; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_892; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1020; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_872; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1176; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_284; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1128; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_920; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_980; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_688; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1216; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1108; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1276; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_852; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1148; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_792; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_796; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1236; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_300; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1088; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1196; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1256; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1068; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1144; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_280; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_904; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1032; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_812; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_924; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_396; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1180; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1272; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1052; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1160; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_888; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1016; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_940; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_828; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1164; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1036; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1112; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_648; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_700; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_264; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_956; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_780; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_800; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_304; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1084; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_776; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1212; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_684; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1240; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_928; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_392; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_856; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_296; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_908; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_984; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_860; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_968; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1028; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1080; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_276; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_840; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1208; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_988; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_900; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1012; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_952; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_716; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1140; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1184; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1244; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1096; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_676; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_824; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1116; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_884; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1056; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_696; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1224; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1268; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_784; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1156; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_804; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1168; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1228; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_932; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_912; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1284; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1100; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_712; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1040; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_844; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_864; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_292; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1060; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_972; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_992; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_880; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_964; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_836; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1076; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1136; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_680; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1264; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1188; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_272; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_896; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1008; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_720; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_948; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_820; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1092; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1120; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1204; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1248; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_868; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_848; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1024; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_996; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_936; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_288; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1104; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_692; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_808; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1044; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1220; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1232; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_788; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_976; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_916; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1064; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_708; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1124; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1152; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1192; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1280; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1172; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_0; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_2; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_3; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_4; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_5; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_6; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_7; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_8; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_9; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_10; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_11; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_12; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_13; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_14; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_15; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_16; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_17; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_18; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_19; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_20; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_21; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_22; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_23; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_24; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_25; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_26; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_27; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_28; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_29; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_30; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_31; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_32; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_33; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_34; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_35; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_36; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_37; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_38; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_39; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_40; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_41; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_42; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_43; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_44; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_45; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_46; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_47; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_48; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_49; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_50; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_51; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_52; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_53; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_54; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_55; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_56; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_57; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_58; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_59; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_60; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_61; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_62; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_63; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_64; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_65; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_66; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_67; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_68; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_69; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_70; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_71; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_72; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_73; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_74; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_75; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_76; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_77; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_78; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_79; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_80; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_81; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_82; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_83; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_84; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_85; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_86; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_87; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_88; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_89; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_90; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_91; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_92; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_93; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_94; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_95; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_96; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_97; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_98; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_99; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_100; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_101; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_102; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_103; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_104; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_105; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_106; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_107; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_108; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_109; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_110; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_111; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_112; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_113; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_114; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_115; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_116; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_117; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_118; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_119; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_120; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_121; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_122; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_123; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_124; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_125; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_126; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_127; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_128; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_129; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_130; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_131; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_132; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_133; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_134; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_135; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_136; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_137; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_138; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_139; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_140; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_141; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_142; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_143; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_144; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_145; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_146; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_147; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_148; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_149; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_150; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_151; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_152; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_153; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_154; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_155; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_156; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_157; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_158; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_159; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_160; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_161; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_162; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_163; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_164; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_165; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_166; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_167; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_168; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_169; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_170; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_171; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_172; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_173; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_174; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_175; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_176; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_177; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_178; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_179; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_180; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_181; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_182; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_183; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_184; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_185; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_186; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_187; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_188; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_189; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_190; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_191; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_192; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_193; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_194; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_195; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_196; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_197; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_198; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_199; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_200; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_201; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_202; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_203; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_204; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_205; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_206; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_207; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_208; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_209; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_210; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_211; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_212; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_213; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_214; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_215; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_216; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_217; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_218; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_219; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_220; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_221; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_222; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_223; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_224; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_225; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_226; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_227; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_228; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_229; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_230; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_231; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_232; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_233; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_234; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_235; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_236; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_237; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_238; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_239; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_240; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_241; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_242; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_243; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_244; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_245; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_246; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_247; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_248; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_249; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_250; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_251; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_252; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_253; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_254; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_255; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_256; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_257; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_258; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_259; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_260; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_261; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_262; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_263; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_264; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_265; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_266; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_267; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_268; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_269; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_270; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_271; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_272; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_273; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_274; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_275; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_276; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_277; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_278; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_279; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_280; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_281; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_282; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_283; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_284; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_285; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_286; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_287; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_288; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_289; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_290; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_291; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_292; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_293; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_294; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_295; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_296; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_297; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_298; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_299; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_300; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_301; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_302; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_303; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_304; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_305; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_306; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_307; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_308; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_309; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_310; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_311; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_312; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_313; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_314; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_315; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_316; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_317; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_318; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_319; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_320; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_321; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_322; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_323; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_324; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_325; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_326; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_327; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_328; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_329; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_330; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_331; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_332; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_333; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_334; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_335; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_336; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_337; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_338; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_339; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_340; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_341; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_342; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_343; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_344; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_345; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_346; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_347; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_348; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_349; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_350; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_351; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_352; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_353; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_354; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_355; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_356; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_357; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_358; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_359; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_360; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_361; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_362; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_363; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_364; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_365; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_366; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_367; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_368; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_369; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_370; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_371; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_372; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_373; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_374; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_375; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_376; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_377; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_378; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_379; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_380; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_381; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_382; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_383; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_384; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_385; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_386; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_387; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_388; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_389; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_390; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_391; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_392; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_393; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_394; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_395; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_396; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_397; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_398; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_399; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_400; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_401; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_402; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_403; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_404; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_405; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_406; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_407; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_408; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_409; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_410; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_411; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_412; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_413; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_414; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_415; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_416; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_417; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_418; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_419; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_420; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_421; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_422; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_423; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_424; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_425; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_426; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_427; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_428; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_429; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_430; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_431; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_432; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_433; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_434; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_435; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_436; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_437; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_438; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_439; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_440; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_441; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_442; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_443; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_444; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_445; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_446; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_447; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_448; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_449; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_450; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_451; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_452; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_453; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_454; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_455; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_456; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_457; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_458; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_459; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_460; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_461; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_462; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_463; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_464; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_465; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_466; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_467; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_468; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_469; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_470; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_471; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_472; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_473; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_474; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_475; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_476; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_477; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_478; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_479; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_480; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_481; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_482; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_483; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_484; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_485; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_486; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_487; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_488; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_489; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_490; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_491; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_492; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_493; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_494; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_495; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_496; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_497; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_498; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_499; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_500; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_501; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_502; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_503; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_504; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_505; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_506; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_507; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_508; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_509; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_510; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_511; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_512; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_513; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_514; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_515; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_516; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_517; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_518; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_519; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_520; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_521; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_522; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_523; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_524; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_525; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_526; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_527; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_528; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_529; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_530; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_531; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_532; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_533; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_534; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_535; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_536; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_537; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_538; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_539; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_540; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_541; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_542; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_543; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_544; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_545; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_546; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_547; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_548; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_549; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_550; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_551; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_552; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_553; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_554; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_555; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_556; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_557; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_558; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_559; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_560; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_561; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_562; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_563; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_564; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_565; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_566; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_567; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_568; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_569; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_570; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_571; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_572; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_573; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_574; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_575; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_576; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_577; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_578; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_579; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_580; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_581; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_582; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_583; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_584; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_585; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_586; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_587; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_588; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_589; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_590; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_591; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_592; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_593; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_594; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_595; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_596; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_597; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_598; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_599; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_600; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_601; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_602; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_603; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_604; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_605; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_606; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_607; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_608; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_609; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_610; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_611; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_612; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_613; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_614; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_615; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_616; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_617; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_618; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_619; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_620; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_621; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_622; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_623; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_624; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_625; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_626; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_627; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_628; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_629; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_630; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_631; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_632; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_633; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_634; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_635; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_636; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_637; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_638; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_639; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_640; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_641; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_642; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_643; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_644; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_645; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_646; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_647; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_648; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_649; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_650; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_651; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_652; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_653; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_654; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_655; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_656; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_657; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_658; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_659; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_660; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_661; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_662; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_663; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_664; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_665; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_666; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_667; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_668; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_669; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_670; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_671; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_672; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_673; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_674; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_675; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_676; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_677; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_678; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_679; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_680; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_681; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_682; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_683; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_684; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_685; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_686; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_687; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_688; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_689; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_690; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_691; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_692; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_693; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_694; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_695; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_696; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_697; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_698; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_699; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_700; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_701; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_702; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_703; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_704; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_705; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_706; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_707; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_708; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_709; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_710; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_711; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_712; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_713; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_714; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_715; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_716; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_717; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_718; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_719; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_720; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_721; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_722; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_723; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_724; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_725; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_726; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_727; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_728; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_729; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_730; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_731; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_732; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_733; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_734; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_735; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_736; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_737; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_738; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_739; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_740; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_741; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_742; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_743; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_744; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_745; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_746; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_747; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_748; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_749; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_750; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_751; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_752; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_753; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_754; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_755; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_756; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_757; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_758; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_759; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_760; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_761; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_762; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_763; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_764; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_765; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_766; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_767; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_768; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_769; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_770; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_771; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_772; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_773; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_774; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_775; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_776; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_777; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_778; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_779; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_780; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_781; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_782; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_783; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_784; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_785; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_786; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_787; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_788; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_789; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_790; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_791; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_792; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_793; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_794; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_795; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_796; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_797; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_798; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_799; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_800; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_801; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_802; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_803; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_804; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_805; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_806; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_807; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_808; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_809; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_810; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_811; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_812; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_813; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_814; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_815; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_816; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_817; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_818; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_819; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_820; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_821; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_822; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_823; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_824; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_825; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_826; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_827; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_828; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_829; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_830; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_831; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_832; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_833; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_834; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_835; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_836; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_837; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_838; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_839; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_840; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_841; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_842; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_843; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_844; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_845; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_846; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_847; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_848; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_849; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_850; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_851; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_852; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_853; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_854; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_855; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_856; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_857; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_858; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_859; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_860; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_861; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_862; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_863; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_864; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_865; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_866; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_867; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_868; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_869; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_870; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_871; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_872; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_873; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_874; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_875; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_876; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_877; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_878; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_879; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_880; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_881; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_882; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_883; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_884; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_885; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_886; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_887; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_888; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_889; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_890; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_891; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_892; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_893; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_894; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_895; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_896; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_897; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_898; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_899; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_900; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_901; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_902; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_903; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_904; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_905; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_906; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_907; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_908; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_909; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_910; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_911; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_912; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_913; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_914; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_915; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_916; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_917; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_918; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_919; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_920; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_921; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_922; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_923; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_924; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_925; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_926; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_927; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_928; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_929; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_930; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_931; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_932; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_933; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_934; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_935; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_936; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_937; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_938; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_939; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_940; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_941; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_942; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_943; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_944; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_945; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_946; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_947; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_948; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_949; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_950; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_951; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_952; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_953; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_954; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_955; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_956; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_957; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_958; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_959; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_960; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_961; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_962; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_963; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_964; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_965; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_966; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_967; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_968; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_969; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_970; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_971; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_972; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_973; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_974; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_975; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_976; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_977; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_978; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_979; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_980; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_981; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_982; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_983; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_984; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_985; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_986; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_987; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_988; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_989; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_990; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_991; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_992; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_993; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_994; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_995; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_996; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_997; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_998; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_999; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1000; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1001; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1002; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1003; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1004; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1005; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1006; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1007; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1008; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1009; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1010; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1011; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1012; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1013; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1014; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1015; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1016; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1017; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1018; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1019; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1020; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1021; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1022; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1023; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1024; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1025; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1026; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1027; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1028; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1029; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1030; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1031; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1032; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1033; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1034; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1035; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1036; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1037; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1038; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1039; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1040; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1041; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1042; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1043; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1044; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1045; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1046; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1047; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1048; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1049; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1050; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1051; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1052; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1053; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1054; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1055; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1056; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1057; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1058; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1059; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1060; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1061; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1062; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1063; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1064; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1065; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1066; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1067; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1068; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1069; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1070; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1071; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1072; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1073; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1074; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1075; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1076; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1077; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1078; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1079; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1080; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1081; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1082; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1083; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1084; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1085; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1086; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1087; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1088; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1089; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1090; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1091; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1092; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1093; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1094; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1095; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1096; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1097; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1098; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1099; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1100; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1101; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1102; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1103; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1104; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1105; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1106; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1107; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1108; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1109; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1110; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1111; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1112; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1113; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1114; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1115; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1116; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1117; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1118; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1119; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1120; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1121; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1122; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1123; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1124; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1125; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1126; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1127; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1128; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1129; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1130; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1131; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1132; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1133; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1134; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1135; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1136; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1137; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1138; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1139; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1140; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1141; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1142; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1143; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1144; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1145; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1146; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1147; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1148; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1149; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1150; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1151; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1152; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1153; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1154; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1155; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1156; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1157; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1158; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1159; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1160; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1161; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1162; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1163; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1164; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1165; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1166; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1167; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1168; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1169; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1170; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1171; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1172; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1173; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1174; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1175; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1176; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1177; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1178; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1179; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1180; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1181; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1182; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1183; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1184; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1185; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1186; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1187; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1188; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1189; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1190; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1191; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1192; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1193; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1194; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1195; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1196; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1197; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1198; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1199; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1200; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1201; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1202; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1203; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1204; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1205; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1206; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1207; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1208; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1209; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1210; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_814; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1258; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1198; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_942; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_722; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1130; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1250; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1070; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_830; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_874; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_958; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1002; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_266; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_998; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_702; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1046; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_890; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1018; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_870; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1174; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_282; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1126; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_918; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_978; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_686; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1214; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1106; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1274; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_850; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1146; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_790; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_794; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1234; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_298; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1086; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1194; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1254; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1066; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1142; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_278; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_902; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1030; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_810; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_922; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_394; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1178; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1270; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1050; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1158; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_886; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1014; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_938; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_826; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1162; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1034; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1110; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_646; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_698; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_262; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_954; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_778; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_798; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_302; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1082; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_774; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1210; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_682; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1238; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_926; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_390; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_854; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_294; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_906; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_982; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_858; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_966; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1026; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1078; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_274; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_838; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1206; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_986; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_898; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1010; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_950; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_714; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1138; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1182; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1242; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1094; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_674; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_822; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1114; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_882; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1054; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_694; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1222; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1266; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_782; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1154; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_802; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1166; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1226; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_930; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_910; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1282; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1098; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_710; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1038; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_842; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_862; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_290; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1058; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_970; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_990; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_878; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_962; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_834; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1074; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1134; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_678; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1262; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1186; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_270; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_894; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1006; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_718; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_946; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_818; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1090; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1118; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1202; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1246; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_866; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_846; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1022; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_994; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_934; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_286; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1102; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_690; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_806; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1042; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1218; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1230; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_786; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_974; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_914; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1062; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_706; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1122; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1150; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1190; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1278; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1170; // @[RegisterRouter.scala:87:24] wire out_roready_1_0; // @[RegisterRouter.scala:87:24] wire out_roready_1_1; // @[RegisterRouter.scala:87:24] wire out_roready_1_2; // @[RegisterRouter.scala:87:24] wire out_roready_1_3; // @[RegisterRouter.scala:87:24] wire out_roready_1_4; // @[RegisterRouter.scala:87:24] wire out_roready_1_5; // @[RegisterRouter.scala:87:24] wire out_roready_1_6; // @[RegisterRouter.scala:87:24] wire out_roready_1_7; // @[RegisterRouter.scala:87:24] wire out_roready_1_8; // @[RegisterRouter.scala:87:24] wire out_roready_1_9; // @[RegisterRouter.scala:87:24] wire out_roready_1_10; // @[RegisterRouter.scala:87:24] wire out_roready_1_11; // @[RegisterRouter.scala:87:24] wire out_roready_1_12; // @[RegisterRouter.scala:87:24] wire out_roready_1_13; // @[RegisterRouter.scala:87:24] wire out_roready_1_14; // @[RegisterRouter.scala:87:24] wire out_roready_1_15; // @[RegisterRouter.scala:87:24] wire out_roready_1_16; // @[RegisterRouter.scala:87:24] wire out_roready_1_17; // @[RegisterRouter.scala:87:24] wire out_roready_1_18; // @[RegisterRouter.scala:87:24] wire out_roready_1_19; // @[RegisterRouter.scala:87:24] wire out_roready_1_20; // @[RegisterRouter.scala:87:24] wire out_roready_1_21; // @[RegisterRouter.scala:87:24] wire out_roready_1_22; // @[RegisterRouter.scala:87:24] wire out_roready_1_23; // @[RegisterRouter.scala:87:24] wire out_roready_1_24; // @[RegisterRouter.scala:87:24] wire out_roready_1_25; // @[RegisterRouter.scala:87:24] wire out_roready_1_26; // @[RegisterRouter.scala:87:24] wire out_roready_1_27; // @[RegisterRouter.scala:87:24] wire out_roready_1_28; // @[RegisterRouter.scala:87:24] wire out_roready_1_29; // @[RegisterRouter.scala:87:24] wire out_roready_1_30; // @[RegisterRouter.scala:87:24] wire out_roready_1_31; // @[RegisterRouter.scala:87:24] wire out_roready_1_32; // @[RegisterRouter.scala:87:24] wire out_roready_1_33; // @[RegisterRouter.scala:87:24] wire out_roready_1_34; // @[RegisterRouter.scala:87:24] wire out_roready_1_35; // @[RegisterRouter.scala:87:24] wire out_roready_1_36; // @[RegisterRouter.scala:87:24] wire out_roready_1_37; // @[RegisterRouter.scala:87:24] wire out_roready_1_38; // @[RegisterRouter.scala:87:24] wire out_roready_1_39; // @[RegisterRouter.scala:87:24] wire out_roready_1_40; // @[RegisterRouter.scala:87:24] wire out_roready_1_41; // @[RegisterRouter.scala:87:24] wire out_roready_1_42; // @[RegisterRouter.scala:87:24] wire out_roready_1_43; // @[RegisterRouter.scala:87:24] wire out_roready_1_44; // @[RegisterRouter.scala:87:24] wire out_roready_1_45; // @[RegisterRouter.scala:87:24] wire out_roready_1_46; // @[RegisterRouter.scala:87:24] wire out_roready_1_47; // @[RegisterRouter.scala:87:24] wire out_roready_1_48; // @[RegisterRouter.scala:87:24] wire out_roready_1_49; // @[RegisterRouter.scala:87:24] wire out_roready_1_50; // @[RegisterRouter.scala:87:24] wire out_roready_1_51; // @[RegisterRouter.scala:87:24] wire out_roready_1_52; // @[RegisterRouter.scala:87:24] wire out_roready_1_53; // @[RegisterRouter.scala:87:24] wire out_roready_1_54; // @[RegisterRouter.scala:87:24] wire out_roready_1_55; // @[RegisterRouter.scala:87:24] wire out_roready_1_56; // @[RegisterRouter.scala:87:24] wire out_roready_1_57; // @[RegisterRouter.scala:87:24] wire out_roready_1_58; // @[RegisterRouter.scala:87:24] wire out_roready_1_59; // @[RegisterRouter.scala:87:24] wire out_roready_1_60; // @[RegisterRouter.scala:87:24] wire out_roready_1_61; // @[RegisterRouter.scala:87:24] wire out_roready_1_62; // @[RegisterRouter.scala:87:24] wire out_roready_1_63; // @[RegisterRouter.scala:87:24] wire out_roready_1_64; // @[RegisterRouter.scala:87:24] wire out_roready_1_65; // @[RegisterRouter.scala:87:24] wire out_roready_1_66; // @[RegisterRouter.scala:87:24] wire out_roready_1_67; // @[RegisterRouter.scala:87:24] wire out_roready_1_68; // @[RegisterRouter.scala:87:24] wire out_roready_1_69; // @[RegisterRouter.scala:87:24] wire out_roready_1_70; // @[RegisterRouter.scala:87:24] wire out_roready_1_71; // @[RegisterRouter.scala:87:24] wire out_roready_1_72; // @[RegisterRouter.scala:87:24] wire out_roready_1_73; // @[RegisterRouter.scala:87:24] wire out_roready_1_74; // @[RegisterRouter.scala:87:24] wire out_roready_1_75; // @[RegisterRouter.scala:87:24] wire out_roready_1_76; // @[RegisterRouter.scala:87:24] wire out_roready_1_77; // @[RegisterRouter.scala:87:24] wire out_roready_1_78; // @[RegisterRouter.scala:87:24] wire out_roready_1_79; // @[RegisterRouter.scala:87:24] wire out_roready_1_80; // @[RegisterRouter.scala:87:24] wire out_roready_1_81; // @[RegisterRouter.scala:87:24] wire out_roready_1_82; // @[RegisterRouter.scala:87:24] wire out_roready_1_83; // @[RegisterRouter.scala:87:24] wire out_roready_1_84; // @[RegisterRouter.scala:87:24] wire out_roready_1_85; // @[RegisterRouter.scala:87:24] wire out_roready_1_86; // @[RegisterRouter.scala:87:24] wire out_roready_1_87; // @[RegisterRouter.scala:87:24] wire out_roready_1_88; // @[RegisterRouter.scala:87:24] wire out_roready_1_89; // @[RegisterRouter.scala:87:24] wire out_roready_1_90; // @[RegisterRouter.scala:87:24] wire out_roready_1_91; // @[RegisterRouter.scala:87:24] wire out_roready_1_92; // @[RegisterRouter.scala:87:24] wire out_roready_1_93; // @[RegisterRouter.scala:87:24] wire out_roready_1_94; // @[RegisterRouter.scala:87:24] wire out_roready_1_95; // @[RegisterRouter.scala:87:24] wire out_roready_1_96; // @[RegisterRouter.scala:87:24] wire out_roready_1_97; // @[RegisterRouter.scala:87:24] wire out_roready_1_98; // @[RegisterRouter.scala:87:24] wire out_roready_1_99; // @[RegisterRouter.scala:87:24] wire out_roready_1_100; // @[RegisterRouter.scala:87:24] wire out_roready_1_101; // @[RegisterRouter.scala:87:24] wire out_roready_1_102; // @[RegisterRouter.scala:87:24] wire out_roready_1_103; // @[RegisterRouter.scala:87:24] wire out_roready_1_104; // @[RegisterRouter.scala:87:24] wire out_roready_1_105; // @[RegisterRouter.scala:87:24] wire out_roready_1_106; // @[RegisterRouter.scala:87:24] wire out_roready_1_107; // @[RegisterRouter.scala:87:24] wire out_roready_1_108; // @[RegisterRouter.scala:87:24] wire out_roready_1_109; // @[RegisterRouter.scala:87:24] wire out_roready_1_110; // @[RegisterRouter.scala:87:24] wire out_roready_1_111; // @[RegisterRouter.scala:87:24] wire out_roready_1_112; // @[RegisterRouter.scala:87:24] wire out_roready_1_113; // @[RegisterRouter.scala:87:24] wire out_roready_1_114; // @[RegisterRouter.scala:87:24] wire out_roready_1_115; // @[RegisterRouter.scala:87:24] wire out_roready_1_116; // @[RegisterRouter.scala:87:24] wire out_roready_1_117; // @[RegisterRouter.scala:87:24] wire out_roready_1_118; // @[RegisterRouter.scala:87:24] wire out_roready_1_119; // @[RegisterRouter.scala:87:24] wire out_roready_1_120; // @[RegisterRouter.scala:87:24] wire out_roready_1_121; // @[RegisterRouter.scala:87:24] wire out_roready_1_122; // @[RegisterRouter.scala:87:24] wire out_roready_1_123; // @[RegisterRouter.scala:87:24] wire out_roready_1_124; // @[RegisterRouter.scala:87:24] wire out_roready_1_125; // @[RegisterRouter.scala:87:24] wire out_roready_1_126; // @[RegisterRouter.scala:87:24] wire out_roready_1_127; // @[RegisterRouter.scala:87:24] wire out_roready_1_128; // @[RegisterRouter.scala:87:24] wire out_roready_1_129; // @[RegisterRouter.scala:87:24] wire out_roready_1_130; // @[RegisterRouter.scala:87:24] wire out_roready_1_131; // @[RegisterRouter.scala:87:24] wire out_roready_1_132; // @[RegisterRouter.scala:87:24] wire out_roready_1_133; // @[RegisterRouter.scala:87:24] wire out_roready_1_134; // @[RegisterRouter.scala:87:24] wire out_roready_1_135; // @[RegisterRouter.scala:87:24] wire out_roready_1_136; // @[RegisterRouter.scala:87:24] wire out_roready_1_137; // @[RegisterRouter.scala:87:24] wire out_roready_1_138; // @[RegisterRouter.scala:87:24] wire out_roready_1_139; // @[RegisterRouter.scala:87:24] wire out_roready_1_140; // @[RegisterRouter.scala:87:24] wire out_roready_1_141; // @[RegisterRouter.scala:87:24] wire out_roready_1_142; // @[RegisterRouter.scala:87:24] wire out_roready_1_143; // @[RegisterRouter.scala:87:24] wire out_roready_1_144; // @[RegisterRouter.scala:87:24] wire out_roready_1_145; // @[RegisterRouter.scala:87:24] wire out_roready_1_146; // @[RegisterRouter.scala:87:24] wire out_roready_1_147; // @[RegisterRouter.scala:87:24] wire out_roready_1_148; // @[RegisterRouter.scala:87:24] wire out_roready_1_149; // @[RegisterRouter.scala:87:24] wire out_roready_1_150; // @[RegisterRouter.scala:87:24] wire out_roready_1_151; // @[RegisterRouter.scala:87:24] wire out_roready_1_152; // @[RegisterRouter.scala:87:24] wire out_roready_1_153; // @[RegisterRouter.scala:87:24] wire out_roready_1_154; // @[RegisterRouter.scala:87:24] wire out_roready_1_155; // @[RegisterRouter.scala:87:24] wire out_roready_1_156; // @[RegisterRouter.scala:87:24] wire out_roready_1_157; // @[RegisterRouter.scala:87:24] wire out_roready_1_158; // @[RegisterRouter.scala:87:24] wire out_roready_1_159; // @[RegisterRouter.scala:87:24] wire out_roready_1_160; // @[RegisterRouter.scala:87:24] wire out_roready_1_161; // @[RegisterRouter.scala:87:24] wire out_roready_1_162; // @[RegisterRouter.scala:87:24] wire out_roready_1_163; // @[RegisterRouter.scala:87:24] wire out_roready_1_164; // @[RegisterRouter.scala:87:24] wire out_roready_1_165; // @[RegisterRouter.scala:87:24] wire out_roready_1_166; // @[RegisterRouter.scala:87:24] wire out_roready_1_167; // @[RegisterRouter.scala:87:24] wire out_roready_1_168; // @[RegisterRouter.scala:87:24] wire out_roready_1_169; // @[RegisterRouter.scala:87:24] wire out_roready_1_170; // @[RegisterRouter.scala:87:24] wire out_roready_1_171; // @[RegisterRouter.scala:87:24] wire out_roready_1_172; // @[RegisterRouter.scala:87:24] wire out_roready_1_173; // @[RegisterRouter.scala:87:24] wire out_roready_1_174; // @[RegisterRouter.scala:87:24] wire out_roready_1_175; // @[RegisterRouter.scala:87:24] wire out_roready_1_176; // @[RegisterRouter.scala:87:24] wire out_roready_1_177; // @[RegisterRouter.scala:87:24] wire out_roready_1_178; // @[RegisterRouter.scala:87:24] wire out_roready_1_179; // @[RegisterRouter.scala:87:24] wire out_roready_1_180; // @[RegisterRouter.scala:87:24] wire out_roready_1_181; // @[RegisterRouter.scala:87:24] wire out_roready_1_182; // @[RegisterRouter.scala:87:24] wire out_roready_1_183; // @[RegisterRouter.scala:87:24] wire out_roready_1_184; // @[RegisterRouter.scala:87:24] wire out_roready_1_185; // @[RegisterRouter.scala:87:24] wire out_roready_1_186; // @[RegisterRouter.scala:87:24] wire out_roready_1_187; // @[RegisterRouter.scala:87:24] wire out_roready_1_188; // @[RegisterRouter.scala:87:24] wire out_roready_1_189; // @[RegisterRouter.scala:87:24] wire out_roready_1_190; // @[RegisterRouter.scala:87:24] wire out_roready_1_191; // @[RegisterRouter.scala:87:24] wire out_roready_1_192; // @[RegisterRouter.scala:87:24] wire out_roready_1_193; // @[RegisterRouter.scala:87:24] wire out_roready_1_194; // @[RegisterRouter.scala:87:24] wire out_roready_1_195; // @[RegisterRouter.scala:87:24] wire out_roready_1_196; // @[RegisterRouter.scala:87:24] wire out_roready_1_197; // @[RegisterRouter.scala:87:24] wire out_roready_1_198; // @[RegisterRouter.scala:87:24] wire out_roready_1_199; // @[RegisterRouter.scala:87:24] wire out_roready_1_200; // @[RegisterRouter.scala:87:24] wire out_roready_1_201; // @[RegisterRouter.scala:87:24] wire out_roready_1_202; // @[RegisterRouter.scala:87:24] wire out_roready_1_203; // @[RegisterRouter.scala:87:24] wire out_roready_1_204; // @[RegisterRouter.scala:87:24] wire out_roready_1_205; // @[RegisterRouter.scala:87:24] wire out_roready_1_206; // @[RegisterRouter.scala:87:24] wire out_roready_1_207; // @[RegisterRouter.scala:87:24] wire out_roready_1_208; // @[RegisterRouter.scala:87:24] wire out_roready_1_209; // @[RegisterRouter.scala:87:24] wire out_roready_1_210; // @[RegisterRouter.scala:87:24] wire out_roready_1_211; // @[RegisterRouter.scala:87:24] wire out_roready_1_212; // @[RegisterRouter.scala:87:24] wire out_roready_1_213; // @[RegisterRouter.scala:87:24] wire out_roready_1_214; // @[RegisterRouter.scala:87:24] wire out_roready_1_215; // @[RegisterRouter.scala:87:24] wire out_roready_1_216; // @[RegisterRouter.scala:87:24] wire out_roready_1_217; // @[RegisterRouter.scala:87:24] wire out_roready_1_218; // @[RegisterRouter.scala:87:24] wire out_roready_1_219; // @[RegisterRouter.scala:87:24] wire out_roready_1_220; // @[RegisterRouter.scala:87:24] wire out_roready_1_221; // @[RegisterRouter.scala:87:24] wire out_roready_1_222; // @[RegisterRouter.scala:87:24] wire out_roready_1_223; // @[RegisterRouter.scala:87:24] wire out_roready_1_224; // @[RegisterRouter.scala:87:24] wire out_roready_1_225; // @[RegisterRouter.scala:87:24] wire out_roready_1_226; // @[RegisterRouter.scala:87:24] wire out_roready_1_227; // @[RegisterRouter.scala:87:24] wire out_roready_1_228; // @[RegisterRouter.scala:87:24] wire out_roready_1_229; // @[RegisterRouter.scala:87:24] wire out_roready_1_230; // @[RegisterRouter.scala:87:24] wire out_roready_1_231; // @[RegisterRouter.scala:87:24] wire out_roready_1_232; // @[RegisterRouter.scala:87:24] wire out_roready_1_233; // @[RegisterRouter.scala:87:24] wire out_roready_1_234; // @[RegisterRouter.scala:87:24] wire out_roready_1_235; // @[RegisterRouter.scala:87:24] wire out_roready_1_236; // @[RegisterRouter.scala:87:24] wire out_roready_1_237; // @[RegisterRouter.scala:87:24] wire out_roready_1_238; // @[RegisterRouter.scala:87:24] wire out_roready_1_239; // @[RegisterRouter.scala:87:24] wire out_roready_1_240; // @[RegisterRouter.scala:87:24] wire out_roready_1_241; // @[RegisterRouter.scala:87:24] wire out_roready_1_242; // @[RegisterRouter.scala:87:24] wire out_roready_1_243; // @[RegisterRouter.scala:87:24] wire out_roready_1_244; // @[RegisterRouter.scala:87:24] wire out_roready_1_245; // @[RegisterRouter.scala:87:24] wire out_roready_1_246; // @[RegisterRouter.scala:87:24] wire out_roready_1_247; // @[RegisterRouter.scala:87:24] wire out_roready_1_248; // @[RegisterRouter.scala:87:24] wire out_roready_1_249; // @[RegisterRouter.scala:87:24] wire out_roready_1_250; // @[RegisterRouter.scala:87:24] wire out_roready_1_251; // @[RegisterRouter.scala:87:24] wire out_roready_1_252; // @[RegisterRouter.scala:87:24] wire out_roready_1_253; // @[RegisterRouter.scala:87:24] wire out_roready_1_254; // @[RegisterRouter.scala:87:24] wire out_roready_1_255; // @[RegisterRouter.scala:87:24] wire out_roready_1_256; // @[RegisterRouter.scala:87:24] wire out_roready_1_257; // @[RegisterRouter.scala:87:24] wire out_roready_1_258; // @[RegisterRouter.scala:87:24] wire out_roready_1_259; // @[RegisterRouter.scala:87:24] wire out_roready_1_260; // @[RegisterRouter.scala:87:24] wire out_roready_1_261; // @[RegisterRouter.scala:87:24] wire out_roready_1_262; // @[RegisterRouter.scala:87:24] wire out_roready_1_263; // @[RegisterRouter.scala:87:24] wire out_roready_1_264; // @[RegisterRouter.scala:87:24] wire out_roready_1_265; // @[RegisterRouter.scala:87:24] wire out_roready_1_266; // @[RegisterRouter.scala:87:24] wire out_roready_1_267; // @[RegisterRouter.scala:87:24] wire out_roready_1_268; // @[RegisterRouter.scala:87:24] wire out_roready_1_269; // @[RegisterRouter.scala:87:24] wire out_roready_1_270; // @[RegisterRouter.scala:87:24] wire out_roready_1_271; // @[RegisterRouter.scala:87:24] wire out_roready_1_272; // @[RegisterRouter.scala:87:24] wire out_roready_1_273; // @[RegisterRouter.scala:87:24] wire out_roready_1_274; // @[RegisterRouter.scala:87:24] wire out_roready_1_275; // @[RegisterRouter.scala:87:24] wire out_roready_1_276; // @[RegisterRouter.scala:87:24] wire out_roready_1_277; // @[RegisterRouter.scala:87:24] wire out_roready_1_278; // @[RegisterRouter.scala:87:24] wire out_roready_1_279; // @[RegisterRouter.scala:87:24] wire out_roready_1_280; // @[RegisterRouter.scala:87:24] wire out_roready_1_281; // @[RegisterRouter.scala:87:24] wire out_roready_1_282; // @[RegisterRouter.scala:87:24] wire out_roready_1_283; // @[RegisterRouter.scala:87:24] wire out_roready_1_284; // @[RegisterRouter.scala:87:24] wire out_roready_1_285; // @[RegisterRouter.scala:87:24] wire out_roready_1_286; // @[RegisterRouter.scala:87:24] wire out_roready_1_287; // @[RegisterRouter.scala:87:24] wire out_roready_1_288; // @[RegisterRouter.scala:87:24] wire out_roready_1_289; // @[RegisterRouter.scala:87:24] wire out_roready_1_290; // @[RegisterRouter.scala:87:24] wire out_roready_1_291; // @[RegisterRouter.scala:87:24] wire out_roready_1_292; // @[RegisterRouter.scala:87:24] wire out_roready_1_293; // @[RegisterRouter.scala:87:24] wire out_roready_1_294; // @[RegisterRouter.scala:87:24] wire out_roready_1_295; // @[RegisterRouter.scala:87:24] wire out_roready_1_296; // @[RegisterRouter.scala:87:24] wire out_roready_1_297; // @[RegisterRouter.scala:87:24] wire out_roready_1_298; // @[RegisterRouter.scala:87:24] wire out_roready_1_299; // @[RegisterRouter.scala:87:24] wire out_roready_1_300; // @[RegisterRouter.scala:87:24] wire out_roready_1_301; // @[RegisterRouter.scala:87:24] wire out_roready_1_302; // @[RegisterRouter.scala:87:24] wire out_roready_1_303; // @[RegisterRouter.scala:87:24] wire out_roready_1_304; // @[RegisterRouter.scala:87:24] wire out_roready_1_305; // @[RegisterRouter.scala:87:24] wire out_roready_1_306; // @[RegisterRouter.scala:87:24] wire out_roready_1_307; // @[RegisterRouter.scala:87:24] wire out_roready_1_308; // @[RegisterRouter.scala:87:24] wire out_roready_1_309; // @[RegisterRouter.scala:87:24] wire out_roready_1_310; // @[RegisterRouter.scala:87:24] wire out_roready_1_311; // @[RegisterRouter.scala:87:24] wire out_roready_1_312; // @[RegisterRouter.scala:87:24] wire out_roready_1_313; // @[RegisterRouter.scala:87:24] wire out_roready_1_314; // @[RegisterRouter.scala:87:24] wire out_roready_1_315; // @[RegisterRouter.scala:87:24] wire out_roready_1_316; // @[RegisterRouter.scala:87:24] wire out_roready_1_317; // @[RegisterRouter.scala:87:24] wire out_roready_1_318; // @[RegisterRouter.scala:87:24] wire out_roready_1_319; // @[RegisterRouter.scala:87:24] wire out_roready_1_320; // @[RegisterRouter.scala:87:24] wire out_roready_1_321; // @[RegisterRouter.scala:87:24] wire out_roready_1_322; // @[RegisterRouter.scala:87:24] wire out_roready_1_323; // @[RegisterRouter.scala:87:24] wire out_roready_1_324; // @[RegisterRouter.scala:87:24] wire out_roready_1_325; // @[RegisterRouter.scala:87:24] wire out_roready_1_326; // @[RegisterRouter.scala:87:24] wire out_roready_1_327; // @[RegisterRouter.scala:87:24] wire out_roready_1_328; // @[RegisterRouter.scala:87:24] wire out_roready_1_329; // @[RegisterRouter.scala:87:24] wire out_roready_1_330; // @[RegisterRouter.scala:87:24] wire out_roready_1_331; // @[RegisterRouter.scala:87:24] wire out_roready_1_332; // @[RegisterRouter.scala:87:24] wire out_roready_1_333; // @[RegisterRouter.scala:87:24] wire out_roready_1_334; // @[RegisterRouter.scala:87:24] wire out_roready_1_335; // @[RegisterRouter.scala:87:24] wire out_roready_1_336; // @[RegisterRouter.scala:87:24] wire out_roready_1_337; // @[RegisterRouter.scala:87:24] wire out_roready_1_338; // @[RegisterRouter.scala:87:24] wire out_roready_1_339; // @[RegisterRouter.scala:87:24] wire out_roready_1_340; // @[RegisterRouter.scala:87:24] wire out_roready_1_341; // @[RegisterRouter.scala:87:24] wire out_roready_1_342; // @[RegisterRouter.scala:87:24] wire out_roready_1_343; // @[RegisterRouter.scala:87:24] wire out_roready_1_344; // @[RegisterRouter.scala:87:24] wire out_roready_1_345; // @[RegisterRouter.scala:87:24] wire out_roready_1_346; // @[RegisterRouter.scala:87:24] wire out_roready_1_347; // @[RegisterRouter.scala:87:24] wire out_roready_1_348; // @[RegisterRouter.scala:87:24] wire out_roready_1_349; // @[RegisterRouter.scala:87:24] wire out_roready_1_350; // @[RegisterRouter.scala:87:24] wire out_roready_1_351; // @[RegisterRouter.scala:87:24] wire out_roready_1_352; // @[RegisterRouter.scala:87:24] wire out_roready_1_353; // @[RegisterRouter.scala:87:24] wire out_roready_1_354; // @[RegisterRouter.scala:87:24] wire out_roready_1_355; // @[RegisterRouter.scala:87:24] wire out_roready_1_356; // @[RegisterRouter.scala:87:24] wire out_roready_1_357; // @[RegisterRouter.scala:87:24] wire out_roready_1_358; // @[RegisterRouter.scala:87:24] wire out_roready_1_359; // @[RegisterRouter.scala:87:24] wire out_roready_1_360; // @[RegisterRouter.scala:87:24] wire out_roready_1_361; // @[RegisterRouter.scala:87:24] wire out_roready_1_362; // @[RegisterRouter.scala:87:24] wire out_roready_1_363; // @[RegisterRouter.scala:87:24] wire out_roready_1_364; // @[RegisterRouter.scala:87:24] wire out_roready_1_365; // @[RegisterRouter.scala:87:24] wire out_roready_1_366; // @[RegisterRouter.scala:87:24] wire out_roready_1_367; // @[RegisterRouter.scala:87:24] wire out_roready_1_368; // @[RegisterRouter.scala:87:24] wire out_roready_1_369; // @[RegisterRouter.scala:87:24] wire out_roready_1_370; // @[RegisterRouter.scala:87:24] wire out_roready_1_371; // @[RegisterRouter.scala:87:24] wire out_roready_1_372; // @[RegisterRouter.scala:87:24] wire out_roready_1_373; // @[RegisterRouter.scala:87:24] wire out_roready_1_374; // @[RegisterRouter.scala:87:24] wire out_roready_1_375; // @[RegisterRouter.scala:87:24] wire out_roready_1_376; // @[RegisterRouter.scala:87:24] wire out_roready_1_377; // @[RegisterRouter.scala:87:24] wire out_roready_1_378; // @[RegisterRouter.scala:87:24] wire out_roready_1_379; // @[RegisterRouter.scala:87:24] wire out_roready_1_380; // @[RegisterRouter.scala:87:24] wire out_roready_1_381; // @[RegisterRouter.scala:87:24] wire out_roready_1_382; // @[RegisterRouter.scala:87:24] wire out_roready_1_383; // @[RegisterRouter.scala:87:24] wire out_roready_1_384; // @[RegisterRouter.scala:87:24] wire out_roready_1_385; // @[RegisterRouter.scala:87:24] wire out_roready_1_386; // @[RegisterRouter.scala:87:24] wire out_roready_1_387; // @[RegisterRouter.scala:87:24] wire out_roready_1_388; // @[RegisterRouter.scala:87:24] wire out_roready_1_389; // @[RegisterRouter.scala:87:24] wire out_roready_1_390; // @[RegisterRouter.scala:87:24] wire out_roready_1_391; // @[RegisterRouter.scala:87:24] wire out_roready_1_392; // @[RegisterRouter.scala:87:24] wire out_roready_1_393; // @[RegisterRouter.scala:87:24] wire out_roready_1_394; // @[RegisterRouter.scala:87:24] wire out_roready_1_395; // @[RegisterRouter.scala:87:24] wire out_roready_1_396; // @[RegisterRouter.scala:87:24] wire out_roready_1_397; // @[RegisterRouter.scala:87:24] wire out_roready_1_398; // @[RegisterRouter.scala:87:24] wire out_roready_1_399; // @[RegisterRouter.scala:87:24] wire out_roready_1_400; // @[RegisterRouter.scala:87:24] wire out_roready_1_401; // @[RegisterRouter.scala:87:24] wire out_roready_1_402; // @[RegisterRouter.scala:87:24] wire out_roready_1_403; // @[RegisterRouter.scala:87:24] wire out_roready_1_404; // @[RegisterRouter.scala:87:24] wire out_roready_1_405; // @[RegisterRouter.scala:87:24] wire out_roready_1_406; // @[RegisterRouter.scala:87:24] wire out_roready_1_407; // @[RegisterRouter.scala:87:24] wire out_roready_1_408; // @[RegisterRouter.scala:87:24] wire out_roready_1_409; // @[RegisterRouter.scala:87:24] wire out_roready_1_410; // @[RegisterRouter.scala:87:24] wire out_roready_1_411; // @[RegisterRouter.scala:87:24] wire out_roready_1_412; // @[RegisterRouter.scala:87:24] wire out_roready_1_413; // @[RegisterRouter.scala:87:24] wire out_roready_1_414; // @[RegisterRouter.scala:87:24] wire out_roready_1_415; // @[RegisterRouter.scala:87:24] wire out_roready_1_416; // @[RegisterRouter.scala:87:24] wire out_roready_1_417; // @[RegisterRouter.scala:87:24] wire out_roready_1_418; // @[RegisterRouter.scala:87:24] wire out_roready_1_419; // @[RegisterRouter.scala:87:24] wire out_roready_1_420; // @[RegisterRouter.scala:87:24] wire out_roready_1_421; // @[RegisterRouter.scala:87:24] wire out_roready_1_422; // @[RegisterRouter.scala:87:24] wire out_roready_1_423; // @[RegisterRouter.scala:87:24] wire out_roready_1_424; // @[RegisterRouter.scala:87:24] wire out_roready_1_425; // @[RegisterRouter.scala:87:24] wire out_roready_1_426; // @[RegisterRouter.scala:87:24] wire out_roready_1_427; // @[RegisterRouter.scala:87:24] wire out_roready_1_428; // @[RegisterRouter.scala:87:24] wire out_roready_1_429; // @[RegisterRouter.scala:87:24] wire out_roready_1_430; // @[RegisterRouter.scala:87:24] wire out_roready_1_431; // @[RegisterRouter.scala:87:24] wire out_roready_1_432; // @[RegisterRouter.scala:87:24] wire out_roready_1_433; // @[RegisterRouter.scala:87:24] wire out_roready_1_434; // @[RegisterRouter.scala:87:24] wire out_roready_1_435; // @[RegisterRouter.scala:87:24] wire out_roready_1_436; // @[RegisterRouter.scala:87:24] wire out_roready_1_437; // @[RegisterRouter.scala:87:24] wire out_roready_1_438; // @[RegisterRouter.scala:87:24] wire out_roready_1_439; // @[RegisterRouter.scala:87:24] wire out_roready_1_440; // @[RegisterRouter.scala:87:24] wire out_roready_1_441; // @[RegisterRouter.scala:87:24] wire out_roready_1_442; // @[RegisterRouter.scala:87:24] wire out_roready_1_443; // @[RegisterRouter.scala:87:24] wire out_roready_1_444; // @[RegisterRouter.scala:87:24] wire out_roready_1_445; // @[RegisterRouter.scala:87:24] wire out_roready_1_446; // @[RegisterRouter.scala:87:24] wire out_roready_1_447; // @[RegisterRouter.scala:87:24] wire out_roready_1_448; // @[RegisterRouter.scala:87:24] wire out_roready_1_449; // @[RegisterRouter.scala:87:24] wire out_roready_1_450; // @[RegisterRouter.scala:87:24] wire out_roready_1_451; // @[RegisterRouter.scala:87:24] wire out_roready_1_452; // @[RegisterRouter.scala:87:24] wire out_roready_1_453; // @[RegisterRouter.scala:87:24] wire out_roready_1_454; // @[RegisterRouter.scala:87:24] wire out_roready_1_455; // @[RegisterRouter.scala:87:24] wire out_roready_1_456; // @[RegisterRouter.scala:87:24] wire out_roready_1_457; // @[RegisterRouter.scala:87:24] wire out_roready_1_458; // @[RegisterRouter.scala:87:24] wire out_roready_1_459; // @[RegisterRouter.scala:87:24] wire out_roready_1_460; // @[RegisterRouter.scala:87:24] wire out_roready_1_461; // @[RegisterRouter.scala:87:24] wire out_roready_1_462; // @[RegisterRouter.scala:87:24] wire out_roready_1_463; // @[RegisterRouter.scala:87:24] wire out_roready_1_464; // @[RegisterRouter.scala:87:24] wire out_roready_1_465; // @[RegisterRouter.scala:87:24] wire out_roready_1_466; // @[RegisterRouter.scala:87:24] wire out_roready_1_467; // @[RegisterRouter.scala:87:24] wire out_roready_1_468; // @[RegisterRouter.scala:87:24] wire out_roready_1_469; // @[RegisterRouter.scala:87:24] wire out_roready_1_470; // @[RegisterRouter.scala:87:24] wire out_roready_1_471; // @[RegisterRouter.scala:87:24] wire out_roready_1_472; // @[RegisterRouter.scala:87:24] wire out_roready_1_473; // @[RegisterRouter.scala:87:24] wire out_roready_1_474; // @[RegisterRouter.scala:87:24] wire out_roready_1_475; // @[RegisterRouter.scala:87:24] wire out_roready_1_476; // @[RegisterRouter.scala:87:24] wire out_roready_1_477; // @[RegisterRouter.scala:87:24] wire out_roready_1_478; // @[RegisterRouter.scala:87:24] wire out_roready_1_479; // @[RegisterRouter.scala:87:24] wire out_roready_1_480; // @[RegisterRouter.scala:87:24] wire out_roready_1_481; // @[RegisterRouter.scala:87:24] wire out_roready_1_482; // @[RegisterRouter.scala:87:24] wire out_roready_1_483; // @[RegisterRouter.scala:87:24] wire out_roready_1_484; // @[RegisterRouter.scala:87:24] wire out_roready_1_485; // @[RegisterRouter.scala:87:24] wire out_roready_1_486; // @[RegisterRouter.scala:87:24] wire out_roready_1_487; // @[RegisterRouter.scala:87:24] wire out_roready_1_488; // @[RegisterRouter.scala:87:24] wire out_roready_1_489; // @[RegisterRouter.scala:87:24] wire out_roready_1_490; // @[RegisterRouter.scala:87:24] wire out_roready_1_491; // @[RegisterRouter.scala:87:24] wire out_roready_1_492; // @[RegisterRouter.scala:87:24] wire out_roready_1_493; // @[RegisterRouter.scala:87:24] wire out_roready_1_494; // @[RegisterRouter.scala:87:24] wire out_roready_1_495; // @[RegisterRouter.scala:87:24] wire out_roready_1_496; // @[RegisterRouter.scala:87:24] wire out_roready_1_497; // @[RegisterRouter.scala:87:24] wire out_roready_1_498; // @[RegisterRouter.scala:87:24] wire out_roready_1_499; // @[RegisterRouter.scala:87:24] wire out_roready_1_500; // @[RegisterRouter.scala:87:24] wire out_roready_1_501; // @[RegisterRouter.scala:87:24] wire out_roready_1_502; // @[RegisterRouter.scala:87:24] wire out_roready_1_503; // @[RegisterRouter.scala:87:24] wire out_roready_1_504; // @[RegisterRouter.scala:87:24] wire out_roready_1_505; // @[RegisterRouter.scala:87:24] wire out_roready_1_506; // @[RegisterRouter.scala:87:24] wire out_roready_1_507; // @[RegisterRouter.scala:87:24] wire out_roready_1_508; // @[RegisterRouter.scala:87:24] wire out_roready_1_509; // @[RegisterRouter.scala:87:24] wire out_roready_1_510; // @[RegisterRouter.scala:87:24] wire out_roready_1_511; // @[RegisterRouter.scala:87:24] wire out_roready_1_512; // @[RegisterRouter.scala:87:24] wire out_roready_1_513; // @[RegisterRouter.scala:87:24] wire out_roready_1_514; // @[RegisterRouter.scala:87:24] wire out_roready_1_515; // @[RegisterRouter.scala:87:24] wire out_roready_1_516; // @[RegisterRouter.scala:87:24] wire out_roready_1_517; // @[RegisterRouter.scala:87:24] wire out_roready_1_518; // @[RegisterRouter.scala:87:24] wire out_roready_1_519; // @[RegisterRouter.scala:87:24] wire out_roready_1_520; // @[RegisterRouter.scala:87:24] wire out_roready_1_521; // @[RegisterRouter.scala:87:24] wire out_roready_1_522; // @[RegisterRouter.scala:87:24] wire out_roready_1_523; // @[RegisterRouter.scala:87:24] wire out_roready_1_524; // @[RegisterRouter.scala:87:24] wire out_roready_1_525; // @[RegisterRouter.scala:87:24] wire out_roready_1_526; // @[RegisterRouter.scala:87:24] wire out_roready_1_527; // @[RegisterRouter.scala:87:24] wire out_roready_1_528; // @[RegisterRouter.scala:87:24] wire out_roready_1_529; // @[RegisterRouter.scala:87:24] wire out_roready_1_530; // @[RegisterRouter.scala:87:24] wire out_roready_1_531; // @[RegisterRouter.scala:87:24] wire out_roready_1_532; // @[RegisterRouter.scala:87:24] wire out_roready_1_533; // @[RegisterRouter.scala:87:24] wire out_roready_1_534; // @[RegisterRouter.scala:87:24] wire out_roready_1_535; // @[RegisterRouter.scala:87:24] wire out_roready_1_536; // @[RegisterRouter.scala:87:24] wire out_roready_1_537; // @[RegisterRouter.scala:87:24] wire out_roready_1_538; // @[RegisterRouter.scala:87:24] wire out_roready_1_539; // @[RegisterRouter.scala:87:24] wire out_roready_1_540; // @[RegisterRouter.scala:87:24] wire out_roready_1_541; // @[RegisterRouter.scala:87:24] wire out_roready_1_542; // @[RegisterRouter.scala:87:24] wire out_roready_1_543; // @[RegisterRouter.scala:87:24] wire out_roready_1_544; // @[RegisterRouter.scala:87:24] wire out_roready_1_545; // @[RegisterRouter.scala:87:24] wire out_roready_1_546; // @[RegisterRouter.scala:87:24] wire out_roready_1_547; // @[RegisterRouter.scala:87:24] wire out_roready_1_548; // @[RegisterRouter.scala:87:24] wire out_roready_1_549; // @[RegisterRouter.scala:87:24] wire out_roready_1_550; // @[RegisterRouter.scala:87:24] wire out_roready_1_551; // @[RegisterRouter.scala:87:24] wire out_roready_1_552; // @[RegisterRouter.scala:87:24] wire out_roready_1_553; // @[RegisterRouter.scala:87:24] wire out_roready_1_554; // @[RegisterRouter.scala:87:24] wire out_roready_1_555; // @[RegisterRouter.scala:87:24] wire out_roready_1_556; // @[RegisterRouter.scala:87:24] wire out_roready_1_557; // @[RegisterRouter.scala:87:24] wire out_roready_1_558; // @[RegisterRouter.scala:87:24] wire out_roready_1_559; // @[RegisterRouter.scala:87:24] wire out_roready_1_560; // @[RegisterRouter.scala:87:24] wire out_roready_1_561; // @[RegisterRouter.scala:87:24] wire out_roready_1_562; // @[RegisterRouter.scala:87:24] wire out_roready_1_563; // @[RegisterRouter.scala:87:24] wire out_roready_1_564; // @[RegisterRouter.scala:87:24] wire out_roready_1_565; // @[RegisterRouter.scala:87:24] wire out_roready_1_566; // @[RegisterRouter.scala:87:24] wire out_roready_1_567; // @[RegisterRouter.scala:87:24] wire out_roready_1_568; // @[RegisterRouter.scala:87:24] wire out_roready_1_569; // @[RegisterRouter.scala:87:24] wire out_roready_1_570; // @[RegisterRouter.scala:87:24] wire out_roready_1_571; // @[RegisterRouter.scala:87:24] wire out_roready_1_572; // @[RegisterRouter.scala:87:24] wire out_roready_1_573; // @[RegisterRouter.scala:87:24] wire out_roready_1_574; // @[RegisterRouter.scala:87:24] wire out_roready_1_575; // @[RegisterRouter.scala:87:24] wire out_roready_1_576; // @[RegisterRouter.scala:87:24] wire out_roready_1_577; // @[RegisterRouter.scala:87:24] wire out_roready_1_578; // @[RegisterRouter.scala:87:24] wire out_roready_1_579; // @[RegisterRouter.scala:87:24] wire out_roready_1_580; // @[RegisterRouter.scala:87:24] wire out_roready_1_581; // @[RegisterRouter.scala:87:24] wire out_roready_1_582; // @[RegisterRouter.scala:87:24] wire out_roready_1_583; // @[RegisterRouter.scala:87:24] wire out_roready_1_584; // @[RegisterRouter.scala:87:24] wire out_roready_1_585; // @[RegisterRouter.scala:87:24] wire out_roready_1_586; // @[RegisterRouter.scala:87:24] wire out_roready_1_587; // @[RegisterRouter.scala:87:24] wire out_roready_1_588; // @[RegisterRouter.scala:87:24] wire out_roready_1_589; // @[RegisterRouter.scala:87:24] wire out_roready_1_590; // @[RegisterRouter.scala:87:24] wire out_roready_1_591; // @[RegisterRouter.scala:87:24] wire out_roready_1_592; // @[RegisterRouter.scala:87:24] wire out_roready_1_593; // @[RegisterRouter.scala:87:24] wire out_roready_1_594; // @[RegisterRouter.scala:87:24] wire out_roready_1_595; // @[RegisterRouter.scala:87:24] wire out_roready_1_596; // @[RegisterRouter.scala:87:24] wire out_roready_1_597; // @[RegisterRouter.scala:87:24] wire out_roready_1_598; // @[RegisterRouter.scala:87:24] wire out_roready_1_599; // @[RegisterRouter.scala:87:24] wire out_roready_1_600; // @[RegisterRouter.scala:87:24] wire out_roready_1_601; // @[RegisterRouter.scala:87:24] wire out_roready_1_602; // @[RegisterRouter.scala:87:24] wire out_roready_1_603; // @[RegisterRouter.scala:87:24] wire out_roready_1_604; // @[RegisterRouter.scala:87:24] wire out_roready_1_605; // @[RegisterRouter.scala:87:24] wire out_roready_1_606; // @[RegisterRouter.scala:87:24] wire out_roready_1_607; // @[RegisterRouter.scala:87:24] wire out_roready_1_608; // @[RegisterRouter.scala:87:24] wire out_roready_1_609; // @[RegisterRouter.scala:87:24] wire out_roready_1_610; // @[RegisterRouter.scala:87:24] wire out_roready_1_611; // @[RegisterRouter.scala:87:24] wire out_roready_1_612; // @[RegisterRouter.scala:87:24] wire out_roready_1_613; // @[RegisterRouter.scala:87:24] wire out_roready_1_614; // @[RegisterRouter.scala:87:24] wire out_roready_1_615; // @[RegisterRouter.scala:87:24] wire out_roready_1_616; // @[RegisterRouter.scala:87:24] wire out_roready_1_617; // @[RegisterRouter.scala:87:24] wire out_roready_1_618; // @[RegisterRouter.scala:87:24] wire out_roready_1_619; // @[RegisterRouter.scala:87:24] wire out_roready_1_620; // @[RegisterRouter.scala:87:24] wire out_roready_1_621; // @[RegisterRouter.scala:87:24] wire out_roready_1_622; // @[RegisterRouter.scala:87:24] wire out_roready_1_623; // @[RegisterRouter.scala:87:24] wire out_roready_1_624; // @[RegisterRouter.scala:87:24] wire out_roready_1_625; // @[RegisterRouter.scala:87:24] wire out_roready_1_626; // @[RegisterRouter.scala:87:24] wire out_roready_1_627; // @[RegisterRouter.scala:87:24] wire out_roready_1_628; // @[RegisterRouter.scala:87:24] wire out_roready_1_629; // @[RegisterRouter.scala:87:24] wire out_roready_1_630; // @[RegisterRouter.scala:87:24] wire out_roready_1_631; // @[RegisterRouter.scala:87:24] wire out_roready_1_632; // @[RegisterRouter.scala:87:24] wire out_roready_1_633; // @[RegisterRouter.scala:87:24] wire out_roready_1_634; // @[RegisterRouter.scala:87:24] wire out_roready_1_635; // @[RegisterRouter.scala:87:24] wire out_roready_1_636; // @[RegisterRouter.scala:87:24] wire out_roready_1_637; // @[RegisterRouter.scala:87:24] wire out_roready_1_638; // @[RegisterRouter.scala:87:24] wire out_roready_1_639; // @[RegisterRouter.scala:87:24] wire out_roready_1_640; // @[RegisterRouter.scala:87:24] wire out_roready_1_641; // @[RegisterRouter.scala:87:24] wire out_roready_1_642; // @[RegisterRouter.scala:87:24] wire out_roready_1_643; // @[RegisterRouter.scala:87:24] wire out_roready_1_644; // @[RegisterRouter.scala:87:24] wire out_roready_1_645; // @[RegisterRouter.scala:87:24] wire out_roready_1_646; // @[RegisterRouter.scala:87:24] wire out_roready_1_647; // @[RegisterRouter.scala:87:24] wire out_roready_1_648; // @[RegisterRouter.scala:87:24] wire out_roready_1_649; // @[RegisterRouter.scala:87:24] wire out_roready_1_650; // @[RegisterRouter.scala:87:24] wire out_roready_1_651; // @[RegisterRouter.scala:87:24] wire out_roready_1_652; // @[RegisterRouter.scala:87:24] wire out_roready_1_653; // @[RegisterRouter.scala:87:24] wire out_roready_1_654; // @[RegisterRouter.scala:87:24] wire out_roready_1_655; // @[RegisterRouter.scala:87:24] wire out_roready_1_656; // @[RegisterRouter.scala:87:24] wire out_roready_1_657; // @[RegisterRouter.scala:87:24] wire out_roready_1_658; // @[RegisterRouter.scala:87:24] wire out_roready_1_659; // @[RegisterRouter.scala:87:24] wire out_roready_1_660; // @[RegisterRouter.scala:87:24] wire out_roready_1_661; // @[RegisterRouter.scala:87:24] wire out_roready_1_662; // @[RegisterRouter.scala:87:24] wire out_roready_1_663; // @[RegisterRouter.scala:87:24] wire out_roready_1_664; // @[RegisterRouter.scala:87:24] wire out_roready_1_665; // @[RegisterRouter.scala:87:24] wire out_roready_1_666; // @[RegisterRouter.scala:87:24] wire out_roready_1_667; // @[RegisterRouter.scala:87:24] wire out_roready_1_668; // @[RegisterRouter.scala:87:24] wire out_roready_1_669; // @[RegisterRouter.scala:87:24] wire out_roready_1_670; // @[RegisterRouter.scala:87:24] wire out_roready_1_671; // @[RegisterRouter.scala:87:24] wire out_roready_1_672; // @[RegisterRouter.scala:87:24] wire out_roready_1_673; // @[RegisterRouter.scala:87:24] wire out_roready_1_674; // @[RegisterRouter.scala:87:24] wire out_roready_1_675; // @[RegisterRouter.scala:87:24] wire out_roready_1_676; // @[RegisterRouter.scala:87:24] wire out_roready_1_677; // @[RegisterRouter.scala:87:24] wire out_roready_1_678; // @[RegisterRouter.scala:87:24] wire out_roready_1_679; // @[RegisterRouter.scala:87:24] wire out_roready_1_680; // @[RegisterRouter.scala:87:24] wire out_roready_1_681; // @[RegisterRouter.scala:87:24] wire out_roready_1_682; // @[RegisterRouter.scala:87:24] wire out_roready_1_683; // @[RegisterRouter.scala:87:24] wire out_roready_1_684; // @[RegisterRouter.scala:87:24] wire out_roready_1_685; // @[RegisterRouter.scala:87:24] wire out_roready_1_686; // @[RegisterRouter.scala:87:24] wire out_roready_1_687; // @[RegisterRouter.scala:87:24] wire out_roready_1_688; // @[RegisterRouter.scala:87:24] wire out_roready_1_689; // @[RegisterRouter.scala:87:24] wire out_roready_1_690; // @[RegisterRouter.scala:87:24] wire out_roready_1_691; // @[RegisterRouter.scala:87:24] wire out_roready_1_692; // @[RegisterRouter.scala:87:24] wire out_roready_1_693; // @[RegisterRouter.scala:87:24] wire out_roready_1_694; // @[RegisterRouter.scala:87:24] wire out_roready_1_695; // @[RegisterRouter.scala:87:24] wire out_roready_1_696; // @[RegisterRouter.scala:87:24] wire out_roready_1_697; // @[RegisterRouter.scala:87:24] wire out_roready_1_698; // @[RegisterRouter.scala:87:24] wire out_roready_1_699; // @[RegisterRouter.scala:87:24] wire out_roready_1_700; // @[RegisterRouter.scala:87:24] wire out_roready_1_701; // @[RegisterRouter.scala:87:24] wire out_roready_1_702; // @[RegisterRouter.scala:87:24] wire out_roready_1_703; // @[RegisterRouter.scala:87:24] wire out_roready_1_704; // @[RegisterRouter.scala:87:24] wire out_roready_1_705; // @[RegisterRouter.scala:87:24] wire out_roready_1_706; // @[RegisterRouter.scala:87:24] wire out_roready_1_707; // @[RegisterRouter.scala:87:24] wire out_roready_1_708; // @[RegisterRouter.scala:87:24] wire out_roready_1_709; // @[RegisterRouter.scala:87:24] wire out_roready_1_710; // @[RegisterRouter.scala:87:24] wire out_roready_1_711; // @[RegisterRouter.scala:87:24] wire out_roready_1_712; // @[RegisterRouter.scala:87:24] wire out_roready_1_713; // @[RegisterRouter.scala:87:24] wire out_roready_1_714; // @[RegisterRouter.scala:87:24] wire out_roready_1_715; // @[RegisterRouter.scala:87:24] wire out_roready_1_716; // @[RegisterRouter.scala:87:24] wire out_roready_1_717; // @[RegisterRouter.scala:87:24] wire out_roready_1_718; // @[RegisterRouter.scala:87:24] wire out_roready_1_719; // @[RegisterRouter.scala:87:24] wire out_roready_1_720; // @[RegisterRouter.scala:87:24] wire out_roready_1_721; // @[RegisterRouter.scala:87:24] wire out_roready_1_722; // @[RegisterRouter.scala:87:24] wire out_roready_1_723; // @[RegisterRouter.scala:87:24] wire out_roready_1_724; // @[RegisterRouter.scala:87:24] wire out_roready_1_725; // @[RegisterRouter.scala:87:24] wire out_roready_1_726; // @[RegisterRouter.scala:87:24] wire out_roready_1_727; // @[RegisterRouter.scala:87:24] wire out_roready_1_728; // @[RegisterRouter.scala:87:24] wire out_roready_1_729; // @[RegisterRouter.scala:87:24] wire out_roready_1_730; // @[RegisterRouter.scala:87:24] wire out_roready_1_731; // @[RegisterRouter.scala:87:24] wire out_roready_1_732; // @[RegisterRouter.scala:87:24] wire out_roready_1_733; // @[RegisterRouter.scala:87:24] wire out_roready_1_734; // @[RegisterRouter.scala:87:24] wire out_roready_1_735; // @[RegisterRouter.scala:87:24] wire out_roready_1_736; // @[RegisterRouter.scala:87:24] wire out_roready_1_737; // @[RegisterRouter.scala:87:24] wire out_roready_1_738; // @[RegisterRouter.scala:87:24] wire out_roready_1_739; // @[RegisterRouter.scala:87:24] wire out_roready_1_740; // @[RegisterRouter.scala:87:24] wire out_roready_1_741; // @[RegisterRouter.scala:87:24] wire out_roready_1_742; // @[RegisterRouter.scala:87:24] wire out_roready_1_743; // @[RegisterRouter.scala:87:24] wire out_roready_1_744; // @[RegisterRouter.scala:87:24] wire out_roready_1_745; // @[RegisterRouter.scala:87:24] wire out_roready_1_746; // @[RegisterRouter.scala:87:24] wire out_roready_1_747; // @[RegisterRouter.scala:87:24] wire out_roready_1_748; // @[RegisterRouter.scala:87:24] wire out_roready_1_749; // @[RegisterRouter.scala:87:24] wire out_roready_1_750; // @[RegisterRouter.scala:87:24] wire out_roready_1_751; // @[RegisterRouter.scala:87:24] wire out_roready_1_752; // @[RegisterRouter.scala:87:24] wire out_roready_1_753; // @[RegisterRouter.scala:87:24] wire out_roready_1_754; // @[RegisterRouter.scala:87:24] wire out_roready_1_755; // @[RegisterRouter.scala:87:24] wire out_roready_1_756; // @[RegisterRouter.scala:87:24] wire out_roready_1_757; // @[RegisterRouter.scala:87:24] wire out_roready_1_758; // @[RegisterRouter.scala:87:24] wire out_roready_1_759; // @[RegisterRouter.scala:87:24] wire out_roready_1_760; // @[RegisterRouter.scala:87:24] wire out_roready_1_761; // @[RegisterRouter.scala:87:24] wire out_roready_1_762; // @[RegisterRouter.scala:87:24] wire out_roready_1_763; // @[RegisterRouter.scala:87:24] wire out_roready_1_764; // @[RegisterRouter.scala:87:24] wire out_roready_1_765; // @[RegisterRouter.scala:87:24] wire out_roready_1_766; // @[RegisterRouter.scala:87:24] wire out_roready_1_767; // @[RegisterRouter.scala:87:24] wire out_roready_1_768; // @[RegisterRouter.scala:87:24] wire out_roready_1_769; // @[RegisterRouter.scala:87:24] wire out_roready_1_770; // @[RegisterRouter.scala:87:24] wire out_roready_1_771; // @[RegisterRouter.scala:87:24] wire out_roready_1_772; // @[RegisterRouter.scala:87:24] wire out_roready_1_773; // @[RegisterRouter.scala:87:24] wire out_roready_1_774; // @[RegisterRouter.scala:87:24] wire out_roready_1_775; // @[RegisterRouter.scala:87:24] wire out_roready_1_776; // @[RegisterRouter.scala:87:24] wire out_roready_1_777; // @[RegisterRouter.scala:87:24] wire out_roready_1_778; // @[RegisterRouter.scala:87:24] wire out_roready_1_779; // @[RegisterRouter.scala:87:24] wire out_roready_1_780; // @[RegisterRouter.scala:87:24] wire out_roready_1_781; // @[RegisterRouter.scala:87:24] wire out_roready_1_782; // @[RegisterRouter.scala:87:24] wire out_roready_1_783; // @[RegisterRouter.scala:87:24] wire out_roready_1_784; // @[RegisterRouter.scala:87:24] wire out_roready_1_785; // @[RegisterRouter.scala:87:24] wire out_roready_1_786; // @[RegisterRouter.scala:87:24] wire out_roready_1_787; // @[RegisterRouter.scala:87:24] wire out_roready_1_788; // @[RegisterRouter.scala:87:24] wire out_roready_1_789; // @[RegisterRouter.scala:87:24] wire out_roready_1_790; // @[RegisterRouter.scala:87:24] wire out_roready_1_791; // @[RegisterRouter.scala:87:24] wire out_roready_1_792; // @[RegisterRouter.scala:87:24] wire out_roready_1_793; // @[RegisterRouter.scala:87:24] wire out_roready_1_794; // @[RegisterRouter.scala:87:24] wire out_roready_1_795; // @[RegisterRouter.scala:87:24] wire out_roready_1_796; // @[RegisterRouter.scala:87:24] wire out_roready_1_797; // @[RegisterRouter.scala:87:24] wire out_roready_1_798; // @[RegisterRouter.scala:87:24] wire out_roready_1_799; // @[RegisterRouter.scala:87:24] wire out_roready_1_800; // @[RegisterRouter.scala:87:24] wire out_roready_1_801; // @[RegisterRouter.scala:87:24] wire out_roready_1_802; // @[RegisterRouter.scala:87:24] wire out_roready_1_803; // @[RegisterRouter.scala:87:24] wire out_roready_1_804; // @[RegisterRouter.scala:87:24] wire out_roready_1_805; // @[RegisterRouter.scala:87:24] wire out_roready_1_806; // @[RegisterRouter.scala:87:24] wire out_roready_1_807; // @[RegisterRouter.scala:87:24] wire out_roready_1_808; // @[RegisterRouter.scala:87:24] wire out_roready_1_809; // @[RegisterRouter.scala:87:24] wire out_roready_1_810; // @[RegisterRouter.scala:87:24] wire out_roready_1_811; // @[RegisterRouter.scala:87:24] wire out_roready_1_812; // @[RegisterRouter.scala:87:24] wire out_roready_1_813; // @[RegisterRouter.scala:87:24] wire out_roready_1_814; // @[RegisterRouter.scala:87:24] wire out_roready_1_815; // @[RegisterRouter.scala:87:24] wire out_roready_1_816; // @[RegisterRouter.scala:87:24] wire out_roready_1_817; // @[RegisterRouter.scala:87:24] wire out_roready_1_818; // @[RegisterRouter.scala:87:24] wire out_roready_1_819; // @[RegisterRouter.scala:87:24] wire out_roready_1_820; // @[RegisterRouter.scala:87:24] wire out_roready_1_821; // @[RegisterRouter.scala:87:24] wire out_roready_1_822; // @[RegisterRouter.scala:87:24] wire out_roready_1_823; // @[RegisterRouter.scala:87:24] wire out_roready_1_824; // @[RegisterRouter.scala:87:24] wire out_roready_1_825; // @[RegisterRouter.scala:87:24] wire out_roready_1_826; // @[RegisterRouter.scala:87:24] wire out_roready_1_827; // @[RegisterRouter.scala:87:24] wire out_roready_1_828; // @[RegisterRouter.scala:87:24] wire out_roready_1_829; // @[RegisterRouter.scala:87:24] wire out_roready_1_830; // @[RegisterRouter.scala:87:24] wire out_roready_1_831; // @[RegisterRouter.scala:87:24] wire out_roready_1_832; // @[RegisterRouter.scala:87:24] wire out_roready_1_833; // @[RegisterRouter.scala:87:24] wire out_roready_1_834; // @[RegisterRouter.scala:87:24] wire out_roready_1_835; // @[RegisterRouter.scala:87:24] wire out_roready_1_836; // @[RegisterRouter.scala:87:24] wire out_roready_1_837; // @[RegisterRouter.scala:87:24] wire out_roready_1_838; // @[RegisterRouter.scala:87:24] wire out_roready_1_839; // @[RegisterRouter.scala:87:24] wire out_roready_1_840; // @[RegisterRouter.scala:87:24] wire out_roready_1_841; // @[RegisterRouter.scala:87:24] wire out_roready_1_842; // @[RegisterRouter.scala:87:24] wire out_roready_1_843; // @[RegisterRouter.scala:87:24] wire out_roready_1_844; // @[RegisterRouter.scala:87:24] wire out_roready_1_845; // @[RegisterRouter.scala:87:24] wire out_roready_1_846; // @[RegisterRouter.scala:87:24] wire out_roready_1_847; // @[RegisterRouter.scala:87:24] wire out_roready_1_848; // @[RegisterRouter.scala:87:24] wire out_roready_1_849; // @[RegisterRouter.scala:87:24] wire out_roready_1_850; // @[RegisterRouter.scala:87:24] wire out_roready_1_851; // @[RegisterRouter.scala:87:24] wire out_roready_1_852; // @[RegisterRouter.scala:87:24] wire out_roready_1_853; // @[RegisterRouter.scala:87:24] wire out_roready_1_854; // @[RegisterRouter.scala:87:24] wire out_roready_1_855; // @[RegisterRouter.scala:87:24] wire out_roready_1_856; // @[RegisterRouter.scala:87:24] wire out_roready_1_857; // @[RegisterRouter.scala:87:24] wire out_roready_1_858; // @[RegisterRouter.scala:87:24] wire out_roready_1_859; // @[RegisterRouter.scala:87:24] wire out_roready_1_860; // @[RegisterRouter.scala:87:24] wire out_roready_1_861; // @[RegisterRouter.scala:87:24] wire out_roready_1_862; // @[RegisterRouter.scala:87:24] wire out_roready_1_863; // @[RegisterRouter.scala:87:24] wire out_roready_1_864; // @[RegisterRouter.scala:87:24] wire out_roready_1_865; // @[RegisterRouter.scala:87:24] wire out_roready_1_866; // @[RegisterRouter.scala:87:24] wire out_roready_1_867; // @[RegisterRouter.scala:87:24] wire out_roready_1_868; // @[RegisterRouter.scala:87:24] wire out_roready_1_869; // @[RegisterRouter.scala:87:24] wire out_roready_1_870; // @[RegisterRouter.scala:87:24] wire out_roready_1_871; // @[RegisterRouter.scala:87:24] wire out_roready_1_872; // @[RegisterRouter.scala:87:24] wire out_roready_1_873; // @[RegisterRouter.scala:87:24] wire out_roready_1_874; // @[RegisterRouter.scala:87:24] wire out_roready_1_875; // @[RegisterRouter.scala:87:24] wire out_roready_1_876; // @[RegisterRouter.scala:87:24] wire out_roready_1_877; // @[RegisterRouter.scala:87:24] wire out_roready_1_878; // @[RegisterRouter.scala:87:24] wire out_roready_1_879; // @[RegisterRouter.scala:87:24] wire out_roready_1_880; // @[RegisterRouter.scala:87:24] wire out_roready_1_881; // @[RegisterRouter.scala:87:24] wire out_roready_1_882; // @[RegisterRouter.scala:87:24] wire out_roready_1_883; // @[RegisterRouter.scala:87:24] wire out_roready_1_884; // @[RegisterRouter.scala:87:24] wire out_roready_1_885; // @[RegisterRouter.scala:87:24] wire out_roready_1_886; // @[RegisterRouter.scala:87:24] wire out_roready_1_887; // @[RegisterRouter.scala:87:24] wire out_roready_1_888; // @[RegisterRouter.scala:87:24] wire out_roready_1_889; // @[RegisterRouter.scala:87:24] wire out_roready_1_890; // @[RegisterRouter.scala:87:24] wire out_roready_1_891; // @[RegisterRouter.scala:87:24] wire out_roready_1_892; // @[RegisterRouter.scala:87:24] wire out_roready_1_893; // @[RegisterRouter.scala:87:24] wire out_roready_1_894; // @[RegisterRouter.scala:87:24] wire out_roready_1_895; // @[RegisterRouter.scala:87:24] wire out_roready_1_896; // @[RegisterRouter.scala:87:24] wire out_roready_1_897; // @[RegisterRouter.scala:87:24] wire out_roready_1_898; // @[RegisterRouter.scala:87:24] wire out_roready_1_899; // @[RegisterRouter.scala:87:24] wire out_roready_1_900; // @[RegisterRouter.scala:87:24] wire out_roready_1_901; // @[RegisterRouter.scala:87:24] wire out_roready_1_902; // @[RegisterRouter.scala:87:24] wire out_roready_1_903; // @[RegisterRouter.scala:87:24] wire out_roready_1_904; // @[RegisterRouter.scala:87:24] wire out_roready_1_905; // @[RegisterRouter.scala:87:24] wire out_roready_1_906; // @[RegisterRouter.scala:87:24] wire out_roready_1_907; // @[RegisterRouter.scala:87:24] wire out_roready_1_908; // @[RegisterRouter.scala:87:24] wire out_roready_1_909; // @[RegisterRouter.scala:87:24] wire out_roready_1_910; // @[RegisterRouter.scala:87:24] wire out_roready_1_911; // @[RegisterRouter.scala:87:24] wire out_roready_1_912; // @[RegisterRouter.scala:87:24] wire out_roready_1_913; // @[RegisterRouter.scala:87:24] wire out_roready_1_914; // @[RegisterRouter.scala:87:24] wire out_roready_1_915; // @[RegisterRouter.scala:87:24] wire out_roready_1_916; // @[RegisterRouter.scala:87:24] wire out_roready_1_917; // @[RegisterRouter.scala:87:24] wire out_roready_1_918; // @[RegisterRouter.scala:87:24] wire out_roready_1_919; // @[RegisterRouter.scala:87:24] wire out_roready_1_920; // @[RegisterRouter.scala:87:24] wire out_roready_1_921; // @[RegisterRouter.scala:87:24] wire out_roready_1_922; // @[RegisterRouter.scala:87:24] wire out_roready_1_923; // @[RegisterRouter.scala:87:24] wire out_roready_1_924; // @[RegisterRouter.scala:87:24] wire out_roready_1_925; // @[RegisterRouter.scala:87:24] wire out_roready_1_926; // @[RegisterRouter.scala:87:24] wire out_roready_1_927; // @[RegisterRouter.scala:87:24] wire out_roready_1_928; // @[RegisterRouter.scala:87:24] wire out_roready_1_929; // @[RegisterRouter.scala:87:24] wire out_roready_1_930; // @[RegisterRouter.scala:87:24] wire out_roready_1_931; // @[RegisterRouter.scala:87:24] wire out_roready_1_932; // @[RegisterRouter.scala:87:24] wire out_roready_1_933; // @[RegisterRouter.scala:87:24] wire out_roready_1_934; // @[RegisterRouter.scala:87:24] wire out_roready_1_935; // @[RegisterRouter.scala:87:24] wire out_roready_1_936; // @[RegisterRouter.scala:87:24] wire out_roready_1_937; // @[RegisterRouter.scala:87:24] wire out_roready_1_938; // @[RegisterRouter.scala:87:24] wire out_roready_1_939; // @[RegisterRouter.scala:87:24] wire out_roready_1_940; // @[RegisterRouter.scala:87:24] wire out_roready_1_941; // @[RegisterRouter.scala:87:24] wire out_roready_1_942; // @[RegisterRouter.scala:87:24] wire out_roready_1_943; // @[RegisterRouter.scala:87:24] wire out_roready_1_944; // @[RegisterRouter.scala:87:24] wire out_roready_1_945; // @[RegisterRouter.scala:87:24] wire out_roready_1_946; // @[RegisterRouter.scala:87:24] wire out_roready_1_947; // @[RegisterRouter.scala:87:24] wire out_roready_1_948; // @[RegisterRouter.scala:87:24] wire out_roready_1_949; // @[RegisterRouter.scala:87:24] wire out_roready_1_950; // @[RegisterRouter.scala:87:24] wire out_roready_1_951; // @[RegisterRouter.scala:87:24] wire out_roready_1_952; // @[RegisterRouter.scala:87:24] wire out_roready_1_953; // @[RegisterRouter.scala:87:24] wire out_roready_1_954; // @[RegisterRouter.scala:87:24] wire out_roready_1_955; // @[RegisterRouter.scala:87:24] wire out_roready_1_956; // @[RegisterRouter.scala:87:24] wire out_roready_1_957; // @[RegisterRouter.scala:87:24] wire out_roready_1_958; // @[RegisterRouter.scala:87:24] wire out_roready_1_959; // @[RegisterRouter.scala:87:24] wire out_roready_1_960; // @[RegisterRouter.scala:87:24] wire out_roready_1_961; // @[RegisterRouter.scala:87:24] wire out_roready_1_962; // @[RegisterRouter.scala:87:24] wire out_roready_1_963; // @[RegisterRouter.scala:87:24] wire out_roready_1_964; // @[RegisterRouter.scala:87:24] wire out_roready_1_965; // @[RegisterRouter.scala:87:24] wire out_roready_1_966; // @[RegisterRouter.scala:87:24] wire out_roready_1_967; // @[RegisterRouter.scala:87:24] wire out_roready_1_968; // @[RegisterRouter.scala:87:24] wire out_roready_1_969; // @[RegisterRouter.scala:87:24] wire out_roready_1_970; // @[RegisterRouter.scala:87:24] wire out_roready_1_971; // @[RegisterRouter.scala:87:24] wire out_roready_1_972; // @[RegisterRouter.scala:87:24] wire out_roready_1_973; // @[RegisterRouter.scala:87:24] wire out_roready_1_974; // @[RegisterRouter.scala:87:24] wire out_roready_1_975; // @[RegisterRouter.scala:87:24] wire out_roready_1_976; // @[RegisterRouter.scala:87:24] wire out_roready_1_977; // @[RegisterRouter.scala:87:24] wire out_roready_1_978; // @[RegisterRouter.scala:87:24] wire out_roready_1_979; // @[RegisterRouter.scala:87:24] wire out_roready_1_980; // @[RegisterRouter.scala:87:24] wire out_roready_1_981; // @[RegisterRouter.scala:87:24] wire out_roready_1_982; // @[RegisterRouter.scala:87:24] wire out_roready_1_983; // @[RegisterRouter.scala:87:24] wire out_roready_1_984; // @[RegisterRouter.scala:87:24] wire out_roready_1_985; // @[RegisterRouter.scala:87:24] wire out_roready_1_986; // @[RegisterRouter.scala:87:24] wire out_roready_1_987; // @[RegisterRouter.scala:87:24] wire out_roready_1_988; // @[RegisterRouter.scala:87:24] wire out_roready_1_989; // @[RegisterRouter.scala:87:24] wire out_roready_1_990; // @[RegisterRouter.scala:87:24] wire out_roready_1_991; // @[RegisterRouter.scala:87:24] wire out_roready_1_992; // @[RegisterRouter.scala:87:24] wire out_roready_1_993; // @[RegisterRouter.scala:87:24] wire out_roready_1_994; // @[RegisterRouter.scala:87:24] wire out_roready_1_995; // @[RegisterRouter.scala:87:24] wire out_roready_1_996; // @[RegisterRouter.scala:87:24] wire out_roready_1_997; // @[RegisterRouter.scala:87:24] wire out_roready_1_998; // @[RegisterRouter.scala:87:24] wire out_roready_1_999; // @[RegisterRouter.scala:87:24] wire out_roready_1_1000; // @[RegisterRouter.scala:87:24] wire out_roready_1_1001; // @[RegisterRouter.scala:87:24] wire out_roready_1_1002; // @[RegisterRouter.scala:87:24] wire out_roready_1_1003; // @[RegisterRouter.scala:87:24] wire out_roready_1_1004; // @[RegisterRouter.scala:87:24] wire out_roready_1_1005; // @[RegisterRouter.scala:87:24] wire out_roready_1_1006; // @[RegisterRouter.scala:87:24] wire out_roready_1_1007; // @[RegisterRouter.scala:87:24] wire out_roready_1_1008; // @[RegisterRouter.scala:87:24] wire out_roready_1_1009; // @[RegisterRouter.scala:87:24] wire out_roready_1_1010; // @[RegisterRouter.scala:87:24] wire out_roready_1_1011; // @[RegisterRouter.scala:87:24] wire out_roready_1_1012; // @[RegisterRouter.scala:87:24] wire out_roready_1_1013; // @[RegisterRouter.scala:87:24] wire out_roready_1_1014; // @[RegisterRouter.scala:87:24] wire out_roready_1_1015; // @[RegisterRouter.scala:87:24] wire out_roready_1_1016; // @[RegisterRouter.scala:87:24] wire out_roready_1_1017; // @[RegisterRouter.scala:87:24] wire out_roready_1_1018; // @[RegisterRouter.scala:87:24] wire out_roready_1_1019; // @[RegisterRouter.scala:87:24] wire out_roready_1_1020; // @[RegisterRouter.scala:87:24] wire out_roready_1_1021; // @[RegisterRouter.scala:87:24] wire out_roready_1_1022; // @[RegisterRouter.scala:87:24] wire out_roready_1_1023; // @[RegisterRouter.scala:87:24] wire out_roready_1_1024; // @[RegisterRouter.scala:87:24] wire out_roready_1_1025; // @[RegisterRouter.scala:87:24] wire out_roready_1_1026; // @[RegisterRouter.scala:87:24] wire out_roready_1_1027; // @[RegisterRouter.scala:87:24] wire out_roready_1_1028; // @[RegisterRouter.scala:87:24] wire out_roready_1_1029; // @[RegisterRouter.scala:87:24] wire out_roready_1_1030; // @[RegisterRouter.scala:87:24] wire out_roready_1_1031; // @[RegisterRouter.scala:87:24] wire out_roready_1_1032; // @[RegisterRouter.scala:87:24] wire out_roready_1_1033; // @[RegisterRouter.scala:87:24] wire out_roready_1_1034; // @[RegisterRouter.scala:87:24] wire out_roready_1_1035; // @[RegisterRouter.scala:87:24] wire out_roready_1_1036; // @[RegisterRouter.scala:87:24] wire out_roready_1_1037; // @[RegisterRouter.scala:87:24] wire out_roready_1_1038; // @[RegisterRouter.scala:87:24] wire out_roready_1_1039; // @[RegisterRouter.scala:87:24] wire out_roready_1_1040; // @[RegisterRouter.scala:87:24] wire out_roready_1_1041; // @[RegisterRouter.scala:87:24] wire out_roready_1_1042; // @[RegisterRouter.scala:87:24] wire out_roready_1_1043; // @[RegisterRouter.scala:87:24] wire out_roready_1_1044; // @[RegisterRouter.scala:87:24] wire out_roready_1_1045; // @[RegisterRouter.scala:87:24] wire out_roready_1_1046; // @[RegisterRouter.scala:87:24] wire out_roready_1_1047; // @[RegisterRouter.scala:87:24] wire out_roready_1_1048; // @[RegisterRouter.scala:87:24] wire out_roready_1_1049; // @[RegisterRouter.scala:87:24] wire out_roready_1_1050; // @[RegisterRouter.scala:87:24] wire out_roready_1_1051; // @[RegisterRouter.scala:87:24] wire out_roready_1_1052; // @[RegisterRouter.scala:87:24] wire out_roready_1_1053; // @[RegisterRouter.scala:87:24] wire out_roready_1_1054; // @[RegisterRouter.scala:87:24] wire out_roready_1_1055; // @[RegisterRouter.scala:87:24] wire out_roready_1_1056; // @[RegisterRouter.scala:87:24] wire out_roready_1_1057; // @[RegisterRouter.scala:87:24] wire out_roready_1_1058; // @[RegisterRouter.scala:87:24] wire out_roready_1_1059; // @[RegisterRouter.scala:87:24] wire out_roready_1_1060; // @[RegisterRouter.scala:87:24] wire out_roready_1_1061; // @[RegisterRouter.scala:87:24] wire out_roready_1_1062; // @[RegisterRouter.scala:87:24] wire out_roready_1_1063; // @[RegisterRouter.scala:87:24] wire out_roready_1_1064; // @[RegisterRouter.scala:87:24] wire out_roready_1_1065; // @[RegisterRouter.scala:87:24] wire out_roready_1_1066; // @[RegisterRouter.scala:87:24] wire out_roready_1_1067; // @[RegisterRouter.scala:87:24] wire out_roready_1_1068; // @[RegisterRouter.scala:87:24] wire out_roready_1_1069; // @[RegisterRouter.scala:87:24] wire out_roready_1_1070; // @[RegisterRouter.scala:87:24] wire out_roready_1_1071; // @[RegisterRouter.scala:87:24] wire out_roready_1_1072; // @[RegisterRouter.scala:87:24] wire out_roready_1_1073; // @[RegisterRouter.scala:87:24] wire out_roready_1_1074; // @[RegisterRouter.scala:87:24] wire out_roready_1_1075; // @[RegisterRouter.scala:87:24] wire out_roready_1_1076; // @[RegisterRouter.scala:87:24] wire out_roready_1_1077; // @[RegisterRouter.scala:87:24] wire out_roready_1_1078; // @[RegisterRouter.scala:87:24] wire out_roready_1_1079; // @[RegisterRouter.scala:87:24] wire out_roready_1_1080; // @[RegisterRouter.scala:87:24] wire out_roready_1_1081; // @[RegisterRouter.scala:87:24] wire out_roready_1_1082; // @[RegisterRouter.scala:87:24] wire out_roready_1_1083; // @[RegisterRouter.scala:87:24] wire out_roready_1_1084; // @[RegisterRouter.scala:87:24] wire out_roready_1_1085; // @[RegisterRouter.scala:87:24] wire out_roready_1_1086; // @[RegisterRouter.scala:87:24] wire out_roready_1_1087; // @[RegisterRouter.scala:87:24] wire out_roready_1_1088; // @[RegisterRouter.scala:87:24] wire out_roready_1_1089; // @[RegisterRouter.scala:87:24] wire out_roready_1_1090; // @[RegisterRouter.scala:87:24] wire out_roready_1_1091; // @[RegisterRouter.scala:87:24] wire out_roready_1_1092; // @[RegisterRouter.scala:87:24] wire out_roready_1_1093; // @[RegisterRouter.scala:87:24] wire out_roready_1_1094; // @[RegisterRouter.scala:87:24] wire out_roready_1_1095; // @[RegisterRouter.scala:87:24] wire out_roready_1_1096; // @[RegisterRouter.scala:87:24] wire out_roready_1_1097; // @[RegisterRouter.scala:87:24] wire out_roready_1_1098; // @[RegisterRouter.scala:87:24] wire out_roready_1_1099; // @[RegisterRouter.scala:87:24] wire out_roready_1_1100; // @[RegisterRouter.scala:87:24] wire out_roready_1_1101; // @[RegisterRouter.scala:87:24] wire out_roready_1_1102; // @[RegisterRouter.scala:87:24] wire out_roready_1_1103; // @[RegisterRouter.scala:87:24] wire out_roready_1_1104; // @[RegisterRouter.scala:87:24] wire out_roready_1_1105; // @[RegisterRouter.scala:87:24] wire out_roready_1_1106; // @[RegisterRouter.scala:87:24] wire out_roready_1_1107; // @[RegisterRouter.scala:87:24] wire out_roready_1_1108; // @[RegisterRouter.scala:87:24] wire out_roready_1_1109; // @[RegisterRouter.scala:87:24] wire out_roready_1_1110; // @[RegisterRouter.scala:87:24] wire out_roready_1_1111; // @[RegisterRouter.scala:87:24] wire out_roready_1_1112; // @[RegisterRouter.scala:87:24] wire out_roready_1_1113; // @[RegisterRouter.scala:87:24] wire out_roready_1_1114; // @[RegisterRouter.scala:87:24] wire out_roready_1_1115; // @[RegisterRouter.scala:87:24] wire out_roready_1_1116; // @[RegisterRouter.scala:87:24] wire out_roready_1_1117; // @[RegisterRouter.scala:87:24] wire out_roready_1_1118; // @[RegisterRouter.scala:87:24] wire out_roready_1_1119; // @[RegisterRouter.scala:87:24] wire out_roready_1_1120; // @[RegisterRouter.scala:87:24] wire out_roready_1_1121; // @[RegisterRouter.scala:87:24] wire out_roready_1_1122; // @[RegisterRouter.scala:87:24] wire out_roready_1_1123; // @[RegisterRouter.scala:87:24] wire out_roready_1_1124; // @[RegisterRouter.scala:87:24] wire out_roready_1_1125; // @[RegisterRouter.scala:87:24] wire out_roready_1_1126; // @[RegisterRouter.scala:87:24] wire out_roready_1_1127; // @[RegisterRouter.scala:87:24] wire out_roready_1_1128; // @[RegisterRouter.scala:87:24] wire out_roready_1_1129; // @[RegisterRouter.scala:87:24] wire out_roready_1_1130; // @[RegisterRouter.scala:87:24] wire out_roready_1_1131; // @[RegisterRouter.scala:87:24] wire out_roready_1_1132; // @[RegisterRouter.scala:87:24] wire out_roready_1_1133; // @[RegisterRouter.scala:87:24] wire out_roready_1_1134; // @[RegisterRouter.scala:87:24] wire out_roready_1_1135; // @[RegisterRouter.scala:87:24] wire out_roready_1_1136; // @[RegisterRouter.scala:87:24] wire out_roready_1_1137; // @[RegisterRouter.scala:87:24] wire out_roready_1_1138; // @[RegisterRouter.scala:87:24] wire out_roready_1_1139; // @[RegisterRouter.scala:87:24] wire out_roready_1_1140; // @[RegisterRouter.scala:87:24] wire out_roready_1_1141; // @[RegisterRouter.scala:87:24] wire out_roready_1_1142; // @[RegisterRouter.scala:87:24] wire out_roready_1_1143; // @[RegisterRouter.scala:87:24] wire out_roready_1_1144; // @[RegisterRouter.scala:87:24] wire out_roready_1_1145; // @[RegisterRouter.scala:87:24] wire out_roready_1_1146; // @[RegisterRouter.scala:87:24] wire out_roready_1_1147; // @[RegisterRouter.scala:87:24] wire out_roready_1_1148; // @[RegisterRouter.scala:87:24] wire out_roready_1_1149; // @[RegisterRouter.scala:87:24] wire out_roready_1_1150; // @[RegisterRouter.scala:87:24] wire out_roready_1_1151; // @[RegisterRouter.scala:87:24] wire out_roready_1_1152; // @[RegisterRouter.scala:87:24] wire out_roready_1_1153; // @[RegisterRouter.scala:87:24] wire out_roready_1_1154; // @[RegisterRouter.scala:87:24] wire out_roready_1_1155; // @[RegisterRouter.scala:87:24] wire out_roready_1_1156; // @[RegisterRouter.scala:87:24] wire out_roready_1_1157; // @[RegisterRouter.scala:87:24] wire out_roready_1_1158; // @[RegisterRouter.scala:87:24] wire out_roready_1_1159; // @[RegisterRouter.scala:87:24] wire out_roready_1_1160; // @[RegisterRouter.scala:87:24] wire out_roready_1_1161; // @[RegisterRouter.scala:87:24] wire out_roready_1_1162; // @[RegisterRouter.scala:87:24] wire out_roready_1_1163; // @[RegisterRouter.scala:87:24] wire out_roready_1_1164; // @[RegisterRouter.scala:87:24] wire out_roready_1_1165; // @[RegisterRouter.scala:87:24] wire out_roready_1_1166; // @[RegisterRouter.scala:87:24] wire out_roready_1_1167; // @[RegisterRouter.scala:87:24] wire out_roready_1_1168; // @[RegisterRouter.scala:87:24] wire out_roready_1_1169; // @[RegisterRouter.scala:87:24] wire out_roready_1_1170; // @[RegisterRouter.scala:87:24] wire out_roready_1_1171; // @[RegisterRouter.scala:87:24] wire out_roready_1_1172; // @[RegisterRouter.scala:87:24] wire out_roready_1_1173; // @[RegisterRouter.scala:87:24] wire out_roready_1_1174; // @[RegisterRouter.scala:87:24] wire out_roready_1_1175; // @[RegisterRouter.scala:87:24] wire out_roready_1_1176; // @[RegisterRouter.scala:87:24] wire out_roready_1_1177; // @[RegisterRouter.scala:87:24] wire out_roready_1_1178; // @[RegisterRouter.scala:87:24] wire out_roready_1_1179; // @[RegisterRouter.scala:87:24] wire out_roready_1_1180; // @[RegisterRouter.scala:87:24] wire out_roready_1_1181; // @[RegisterRouter.scala:87:24] wire out_roready_1_1182; // @[RegisterRouter.scala:87:24] wire out_roready_1_1183; // @[RegisterRouter.scala:87:24] wire out_roready_1_1184; // @[RegisterRouter.scala:87:24] wire out_roready_1_1185; // @[RegisterRouter.scala:87:24] wire out_roready_1_1186; // @[RegisterRouter.scala:87:24] wire out_roready_1_1187; // @[RegisterRouter.scala:87:24] wire out_roready_1_1188; // @[RegisterRouter.scala:87:24] wire out_roready_1_1189; // @[RegisterRouter.scala:87:24] wire out_roready_1_1190; // @[RegisterRouter.scala:87:24] wire out_roready_1_1191; // @[RegisterRouter.scala:87:24] wire out_roready_1_1192; // @[RegisterRouter.scala:87:24] wire out_roready_1_1193; // @[RegisterRouter.scala:87:24] wire out_roready_1_1194; // @[RegisterRouter.scala:87:24] wire out_roready_1_1195; // @[RegisterRouter.scala:87:24] wire out_roready_1_1196; // @[RegisterRouter.scala:87:24] wire out_roready_1_1197; // @[RegisterRouter.scala:87:24] wire out_roready_1_1198; // @[RegisterRouter.scala:87:24] wire out_roready_1_1199; // @[RegisterRouter.scala:87:24] wire out_roready_1_1200; // @[RegisterRouter.scala:87:24] wire out_roready_1_1201; // @[RegisterRouter.scala:87:24] wire out_roready_1_1202; // @[RegisterRouter.scala:87:24] wire out_roready_1_1203; // @[RegisterRouter.scala:87:24] wire out_roready_1_1204; // @[RegisterRouter.scala:87:24] wire out_roready_1_1205; // @[RegisterRouter.scala:87:24] wire out_roready_1_1206; // @[RegisterRouter.scala:87:24] wire out_roready_1_1207; // @[RegisterRouter.scala:87:24] wire out_roready_1_1208; // @[RegisterRouter.scala:87:24] wire out_roready_1_1209; // @[RegisterRouter.scala:87:24] wire out_roready_1_1210; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_816; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1260; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1200; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_944; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_724; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1132; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1252; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1072; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_832; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_876; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_960; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1004; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_268; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1000; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_704; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1048; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_892; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1020; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_872; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1176; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_284; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1128; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_920; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_980; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_688; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1216; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1108; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1276; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_852; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1148; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_792; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_796; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1236; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_300; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1088; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1196; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1256; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1068; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1144; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_280; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_904; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1032; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_812; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_924; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_396; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1180; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1272; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1052; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1160; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_888; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1016; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_940; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_828; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1164; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1036; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1112; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_648; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_700; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_264; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_956; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_780; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_800; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_304; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1084; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_776; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1212; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_684; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1240; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_928; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_392; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_856; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_296; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_908; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_984; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_860; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_968; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1028; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1080; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_276; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_840; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1208; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_988; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_900; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1012; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_952; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_716; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1140; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1184; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1244; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1096; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_676; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_824; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1116; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_884; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1056; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_696; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1224; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1268; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_784; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1156; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_804; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1168; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1228; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_932; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_912; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1284; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1100; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_712; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1040; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_844; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_864; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_292; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1060; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_972; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_992; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_880; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_964; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_836; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1076; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1136; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_680; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1264; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1188; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_272; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_896; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1008; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_720; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_948; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_820; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1092; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1120; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1204; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1248; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_868; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_848; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1024; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_996; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_936; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_288; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1104; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_692; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_808; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1044; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1220; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1232; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_788; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_976; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_916; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1064; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_708; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1124; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1152; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1192; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1280; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1172; // @[RegisterRouter.scala:87:24] wire out_woready_1_0; // @[RegisterRouter.scala:87:24] wire out_woready_1_1; // @[RegisterRouter.scala:87:24] wire out_woready_1_2; // @[RegisterRouter.scala:87:24] wire out_woready_1_3; // @[RegisterRouter.scala:87:24] wire out_woready_1_4; // @[RegisterRouter.scala:87:24] wire out_woready_1_5; // @[RegisterRouter.scala:87:24] wire out_woready_1_6; // @[RegisterRouter.scala:87:24] wire out_woready_1_7; // @[RegisterRouter.scala:87:24] wire out_woready_1_8; // @[RegisterRouter.scala:87:24] wire out_woready_1_9; // @[RegisterRouter.scala:87:24] wire out_woready_1_10; // @[RegisterRouter.scala:87:24] wire out_woready_1_11; // @[RegisterRouter.scala:87:24] wire out_woready_1_12; // @[RegisterRouter.scala:87:24] wire out_woready_1_13; // @[RegisterRouter.scala:87:24] wire out_woready_1_14; // @[RegisterRouter.scala:87:24] wire out_woready_1_15; // @[RegisterRouter.scala:87:24] wire out_woready_1_16; // @[RegisterRouter.scala:87:24] wire out_woready_1_17; // @[RegisterRouter.scala:87:24] wire out_woready_1_18; // @[RegisterRouter.scala:87:24] wire out_woready_1_19; // @[RegisterRouter.scala:87:24] wire out_woready_1_20; // @[RegisterRouter.scala:87:24] wire out_woready_1_21; // @[RegisterRouter.scala:87:24] wire out_woready_1_22; // @[RegisterRouter.scala:87:24] wire out_woready_1_23; // @[RegisterRouter.scala:87:24] wire out_woready_1_24; // @[RegisterRouter.scala:87:24] wire out_woready_1_25; // @[RegisterRouter.scala:87:24] wire out_woready_1_26; // @[RegisterRouter.scala:87:24] wire out_woready_1_27; // @[RegisterRouter.scala:87:24] wire out_woready_1_28; // @[RegisterRouter.scala:87:24] wire out_woready_1_29; // @[RegisterRouter.scala:87:24] wire out_woready_1_30; // @[RegisterRouter.scala:87:24] wire out_woready_1_31; // @[RegisterRouter.scala:87:24] wire out_woready_1_32; // @[RegisterRouter.scala:87:24] wire out_woready_1_33; // @[RegisterRouter.scala:87:24] wire out_woready_1_34; // @[RegisterRouter.scala:87:24] wire out_woready_1_35; // @[RegisterRouter.scala:87:24] wire out_woready_1_36; // @[RegisterRouter.scala:87:24] wire out_woready_1_37; // @[RegisterRouter.scala:87:24] wire out_woready_1_38; // @[RegisterRouter.scala:87:24] wire out_woready_1_39; // @[RegisterRouter.scala:87:24] wire out_woready_1_40; // @[RegisterRouter.scala:87:24] wire out_woready_1_41; // @[RegisterRouter.scala:87:24] wire out_woready_1_42; // @[RegisterRouter.scala:87:24] wire out_woready_1_43; // @[RegisterRouter.scala:87:24] wire out_woready_1_44; // @[RegisterRouter.scala:87:24] wire out_woready_1_45; // @[RegisterRouter.scala:87:24] wire out_woready_1_46; // @[RegisterRouter.scala:87:24] wire out_woready_1_47; // @[RegisterRouter.scala:87:24] wire out_woready_1_48; // @[RegisterRouter.scala:87:24] wire out_woready_1_49; // @[RegisterRouter.scala:87:24] wire out_woready_1_50; // @[RegisterRouter.scala:87:24] wire out_woready_1_51; // @[RegisterRouter.scala:87:24] wire out_woready_1_52; // @[RegisterRouter.scala:87:24] wire out_woready_1_53; // @[RegisterRouter.scala:87:24] wire out_woready_1_54; // @[RegisterRouter.scala:87:24] wire out_woready_1_55; // @[RegisterRouter.scala:87:24] wire out_woready_1_56; // @[RegisterRouter.scala:87:24] wire out_woready_1_57; // @[RegisterRouter.scala:87:24] wire out_woready_1_58; // @[RegisterRouter.scala:87:24] wire out_woready_1_59; // @[RegisterRouter.scala:87:24] wire out_woready_1_60; // @[RegisterRouter.scala:87:24] wire out_woready_1_61; // @[RegisterRouter.scala:87:24] wire out_woready_1_62; // @[RegisterRouter.scala:87:24] wire out_woready_1_63; // @[RegisterRouter.scala:87:24] wire out_woready_1_64; // @[RegisterRouter.scala:87:24] wire out_woready_1_65; // @[RegisterRouter.scala:87:24] wire out_woready_1_66; // @[RegisterRouter.scala:87:24] wire out_woready_1_67; // @[RegisterRouter.scala:87:24] wire out_woready_1_68; // @[RegisterRouter.scala:87:24] wire out_woready_1_69; // @[RegisterRouter.scala:87:24] wire out_woready_1_70; // @[RegisterRouter.scala:87:24] wire out_woready_1_71; // @[RegisterRouter.scala:87:24] wire out_woready_1_72; // @[RegisterRouter.scala:87:24] wire out_woready_1_73; // @[RegisterRouter.scala:87:24] wire out_woready_1_74; // @[RegisterRouter.scala:87:24] wire out_woready_1_75; // @[RegisterRouter.scala:87:24] wire out_woready_1_76; // @[RegisterRouter.scala:87:24] wire out_woready_1_77; // @[RegisterRouter.scala:87:24] wire out_woready_1_78; // @[RegisterRouter.scala:87:24] wire out_woready_1_79; // @[RegisterRouter.scala:87:24] wire out_woready_1_80; // @[RegisterRouter.scala:87:24] wire out_woready_1_81; // @[RegisterRouter.scala:87:24] wire out_woready_1_82; // @[RegisterRouter.scala:87:24] wire out_woready_1_83; // @[RegisterRouter.scala:87:24] wire out_woready_1_84; // @[RegisterRouter.scala:87:24] wire out_woready_1_85; // @[RegisterRouter.scala:87:24] wire out_woready_1_86; // @[RegisterRouter.scala:87:24] wire out_woready_1_87; // @[RegisterRouter.scala:87:24] wire out_woready_1_88; // @[RegisterRouter.scala:87:24] wire out_woready_1_89; // @[RegisterRouter.scala:87:24] wire out_woready_1_90; // @[RegisterRouter.scala:87:24] wire out_woready_1_91; // @[RegisterRouter.scala:87:24] wire out_woready_1_92; // @[RegisterRouter.scala:87:24] wire out_woready_1_93; // @[RegisterRouter.scala:87:24] wire out_woready_1_94; // @[RegisterRouter.scala:87:24] wire out_woready_1_95; // @[RegisterRouter.scala:87:24] wire out_woready_1_96; // @[RegisterRouter.scala:87:24] wire out_woready_1_97; // @[RegisterRouter.scala:87:24] wire out_woready_1_98; // @[RegisterRouter.scala:87:24] wire out_woready_1_99; // @[RegisterRouter.scala:87:24] wire out_woready_1_100; // @[RegisterRouter.scala:87:24] wire out_woready_1_101; // @[RegisterRouter.scala:87:24] wire out_woready_1_102; // @[RegisterRouter.scala:87:24] wire out_woready_1_103; // @[RegisterRouter.scala:87:24] wire out_woready_1_104; // @[RegisterRouter.scala:87:24] wire out_woready_1_105; // @[RegisterRouter.scala:87:24] wire out_woready_1_106; // @[RegisterRouter.scala:87:24] wire out_woready_1_107; // @[RegisterRouter.scala:87:24] wire out_woready_1_108; // @[RegisterRouter.scala:87:24] wire out_woready_1_109; // @[RegisterRouter.scala:87:24] wire out_woready_1_110; // @[RegisterRouter.scala:87:24] wire out_woready_1_111; // @[RegisterRouter.scala:87:24] wire out_woready_1_112; // @[RegisterRouter.scala:87:24] wire out_woready_1_113; // @[RegisterRouter.scala:87:24] wire out_woready_1_114; // @[RegisterRouter.scala:87:24] wire out_woready_1_115; // @[RegisterRouter.scala:87:24] wire out_woready_1_116; // @[RegisterRouter.scala:87:24] wire out_woready_1_117; // @[RegisterRouter.scala:87:24] wire out_woready_1_118; // @[RegisterRouter.scala:87:24] wire out_woready_1_119; // @[RegisterRouter.scala:87:24] wire out_woready_1_120; // @[RegisterRouter.scala:87:24] wire out_woready_1_121; // @[RegisterRouter.scala:87:24] wire out_woready_1_122; // @[RegisterRouter.scala:87:24] wire out_woready_1_123; // @[RegisterRouter.scala:87:24] wire out_woready_1_124; // @[RegisterRouter.scala:87:24] wire out_woready_1_125; // @[RegisterRouter.scala:87:24] wire out_woready_1_126; // @[RegisterRouter.scala:87:24] wire out_woready_1_127; // @[RegisterRouter.scala:87:24] wire out_woready_1_128; // @[RegisterRouter.scala:87:24] wire out_woready_1_129; // @[RegisterRouter.scala:87:24] wire out_woready_1_130; // @[RegisterRouter.scala:87:24] wire out_woready_1_131; // @[RegisterRouter.scala:87:24] wire out_woready_1_132; // @[RegisterRouter.scala:87:24] wire out_woready_1_133; // @[RegisterRouter.scala:87:24] wire out_woready_1_134; // @[RegisterRouter.scala:87:24] wire out_woready_1_135; // @[RegisterRouter.scala:87:24] wire out_woready_1_136; // @[RegisterRouter.scala:87:24] wire out_woready_1_137; // @[RegisterRouter.scala:87:24] wire out_woready_1_138; // @[RegisterRouter.scala:87:24] wire out_woready_1_139; // @[RegisterRouter.scala:87:24] wire out_woready_1_140; // @[RegisterRouter.scala:87:24] wire out_woready_1_141; // @[RegisterRouter.scala:87:24] wire out_woready_1_142; // @[RegisterRouter.scala:87:24] wire out_woready_1_143; // @[RegisterRouter.scala:87:24] wire out_woready_1_144; // @[RegisterRouter.scala:87:24] wire out_woready_1_145; // @[RegisterRouter.scala:87:24] wire out_woready_1_146; // @[RegisterRouter.scala:87:24] wire out_woready_1_147; // @[RegisterRouter.scala:87:24] wire out_woready_1_148; // @[RegisterRouter.scala:87:24] wire out_woready_1_149; // @[RegisterRouter.scala:87:24] wire out_woready_1_150; // @[RegisterRouter.scala:87:24] wire out_woready_1_151; // @[RegisterRouter.scala:87:24] wire out_woready_1_152; // @[RegisterRouter.scala:87:24] wire out_woready_1_153; // @[RegisterRouter.scala:87:24] wire out_woready_1_154; // @[RegisterRouter.scala:87:24] wire out_woready_1_155; // @[RegisterRouter.scala:87:24] wire out_woready_1_156; // @[RegisterRouter.scala:87:24] wire out_woready_1_157; // @[RegisterRouter.scala:87:24] wire out_woready_1_158; // @[RegisterRouter.scala:87:24] wire out_woready_1_159; // @[RegisterRouter.scala:87:24] wire out_woready_1_160; // @[RegisterRouter.scala:87:24] wire out_woready_1_161; // @[RegisterRouter.scala:87:24] wire out_woready_1_162; // @[RegisterRouter.scala:87:24] wire out_woready_1_163; // @[RegisterRouter.scala:87:24] wire out_woready_1_164; // @[RegisterRouter.scala:87:24] wire out_woready_1_165; // @[RegisterRouter.scala:87:24] wire out_woready_1_166; // @[RegisterRouter.scala:87:24] wire out_woready_1_167; // @[RegisterRouter.scala:87:24] wire out_woready_1_168; // @[RegisterRouter.scala:87:24] wire out_woready_1_169; // @[RegisterRouter.scala:87:24] wire out_woready_1_170; // @[RegisterRouter.scala:87:24] wire out_woready_1_171; // @[RegisterRouter.scala:87:24] wire out_woready_1_172; // @[RegisterRouter.scala:87:24] wire out_woready_1_173; // @[RegisterRouter.scala:87:24] wire out_woready_1_174; // @[RegisterRouter.scala:87:24] wire out_woready_1_175; // @[RegisterRouter.scala:87:24] wire out_woready_1_176; // @[RegisterRouter.scala:87:24] wire out_woready_1_177; // @[RegisterRouter.scala:87:24] wire out_woready_1_178; // @[RegisterRouter.scala:87:24] wire out_woready_1_179; // @[RegisterRouter.scala:87:24] wire out_woready_1_180; // @[RegisterRouter.scala:87:24] wire out_woready_1_181; // @[RegisterRouter.scala:87:24] wire out_woready_1_182; // @[RegisterRouter.scala:87:24] wire out_woready_1_183; // @[RegisterRouter.scala:87:24] wire out_woready_1_184; // @[RegisterRouter.scala:87:24] wire out_woready_1_185; // @[RegisterRouter.scala:87:24] wire out_woready_1_186; // @[RegisterRouter.scala:87:24] wire out_woready_1_187; // @[RegisterRouter.scala:87:24] wire out_woready_1_188; // @[RegisterRouter.scala:87:24] wire out_woready_1_189; // @[RegisterRouter.scala:87:24] wire out_woready_1_190; // @[RegisterRouter.scala:87:24] wire out_woready_1_191; // @[RegisterRouter.scala:87:24] wire out_woready_1_192; // @[RegisterRouter.scala:87:24] wire out_woready_1_193; // @[RegisterRouter.scala:87:24] wire out_woready_1_194; // @[RegisterRouter.scala:87:24] wire out_woready_1_195; // @[RegisterRouter.scala:87:24] wire out_woready_1_196; // @[RegisterRouter.scala:87:24] wire out_woready_1_197; // @[RegisterRouter.scala:87:24] wire out_woready_1_198; // @[RegisterRouter.scala:87:24] wire out_woready_1_199; // @[RegisterRouter.scala:87:24] wire out_woready_1_200; // @[RegisterRouter.scala:87:24] wire out_woready_1_201; // @[RegisterRouter.scala:87:24] wire out_woready_1_202; // @[RegisterRouter.scala:87:24] wire out_woready_1_203; // @[RegisterRouter.scala:87:24] wire out_woready_1_204; // @[RegisterRouter.scala:87:24] wire out_woready_1_205; // @[RegisterRouter.scala:87:24] wire out_woready_1_206; // @[RegisterRouter.scala:87:24] wire out_woready_1_207; // @[RegisterRouter.scala:87:24] wire out_woready_1_208; // @[RegisterRouter.scala:87:24] wire out_woready_1_209; // @[RegisterRouter.scala:87:24] wire out_woready_1_210; // @[RegisterRouter.scala:87:24] wire out_woready_1_211; // @[RegisterRouter.scala:87:24] wire out_woready_1_212; // @[RegisterRouter.scala:87:24] wire out_woready_1_213; // @[RegisterRouter.scala:87:24] wire out_woready_1_214; // @[RegisterRouter.scala:87:24] wire out_woready_1_215; // @[RegisterRouter.scala:87:24] wire out_woready_1_216; // @[RegisterRouter.scala:87:24] wire out_woready_1_217; // @[RegisterRouter.scala:87:24] wire out_woready_1_218; // @[RegisterRouter.scala:87:24] wire out_woready_1_219; // @[RegisterRouter.scala:87:24] wire out_woready_1_220; // @[RegisterRouter.scala:87:24] wire out_woready_1_221; // @[RegisterRouter.scala:87:24] wire out_woready_1_222; // @[RegisterRouter.scala:87:24] wire out_woready_1_223; // @[RegisterRouter.scala:87:24] wire out_woready_1_224; // @[RegisterRouter.scala:87:24] wire out_woready_1_225; // @[RegisterRouter.scala:87:24] wire out_woready_1_226; // @[RegisterRouter.scala:87:24] wire out_woready_1_227; // @[RegisterRouter.scala:87:24] wire out_woready_1_228; // @[RegisterRouter.scala:87:24] wire out_woready_1_229; // @[RegisterRouter.scala:87:24] wire out_woready_1_230; // @[RegisterRouter.scala:87:24] wire out_woready_1_231; // @[RegisterRouter.scala:87:24] wire out_woready_1_232; // @[RegisterRouter.scala:87:24] wire out_woready_1_233; // @[RegisterRouter.scala:87:24] wire out_woready_1_234; // @[RegisterRouter.scala:87:24] wire out_woready_1_235; // @[RegisterRouter.scala:87:24] wire out_woready_1_236; // @[RegisterRouter.scala:87:24] wire out_woready_1_237; // @[RegisterRouter.scala:87:24] wire out_woready_1_238; // @[RegisterRouter.scala:87:24] wire out_woready_1_239; // @[RegisterRouter.scala:87:24] wire out_woready_1_240; // @[RegisterRouter.scala:87:24] wire out_woready_1_241; // @[RegisterRouter.scala:87:24] wire out_woready_1_242; // @[RegisterRouter.scala:87:24] wire out_woready_1_243; // @[RegisterRouter.scala:87:24] wire out_woready_1_244; // @[RegisterRouter.scala:87:24] wire out_woready_1_245; // @[RegisterRouter.scala:87:24] wire out_woready_1_246; // @[RegisterRouter.scala:87:24] wire out_woready_1_247; // @[RegisterRouter.scala:87:24] wire out_woready_1_248; // @[RegisterRouter.scala:87:24] wire out_woready_1_249; // @[RegisterRouter.scala:87:24] wire out_woready_1_250; // @[RegisterRouter.scala:87:24] wire out_woready_1_251; // @[RegisterRouter.scala:87:24] wire out_woready_1_252; // @[RegisterRouter.scala:87:24] wire out_woready_1_253; // @[RegisterRouter.scala:87:24] wire out_woready_1_254; // @[RegisterRouter.scala:87:24] wire out_woready_1_255; // @[RegisterRouter.scala:87:24] wire out_woready_1_256; // @[RegisterRouter.scala:87:24] wire out_woready_1_257; // @[RegisterRouter.scala:87:24] wire out_woready_1_258; // @[RegisterRouter.scala:87:24] wire out_woready_1_259; // @[RegisterRouter.scala:87:24] wire out_woready_1_260; // @[RegisterRouter.scala:87:24] wire out_woready_1_261; // @[RegisterRouter.scala:87:24] wire out_woready_1_262; // @[RegisterRouter.scala:87:24] wire out_woready_1_263; // @[RegisterRouter.scala:87:24] wire out_woready_1_264; // @[RegisterRouter.scala:87:24] wire out_woready_1_265; // @[RegisterRouter.scala:87:24] wire out_woready_1_266; // @[RegisterRouter.scala:87:24] wire out_woready_1_267; // @[RegisterRouter.scala:87:24] wire out_woready_1_268; // @[RegisterRouter.scala:87:24] wire out_woready_1_269; // @[RegisterRouter.scala:87:24] wire out_woready_1_270; // @[RegisterRouter.scala:87:24] wire out_woready_1_271; // @[RegisterRouter.scala:87:24] wire out_woready_1_272; // @[RegisterRouter.scala:87:24] wire out_woready_1_273; // @[RegisterRouter.scala:87:24] wire out_woready_1_274; // @[RegisterRouter.scala:87:24] wire out_woready_1_275; // @[RegisterRouter.scala:87:24] wire out_woready_1_276; // @[RegisterRouter.scala:87:24] wire out_woready_1_277; // @[RegisterRouter.scala:87:24] wire out_woready_1_278; // @[RegisterRouter.scala:87:24] wire out_woready_1_279; // @[RegisterRouter.scala:87:24] wire out_woready_1_280; // @[RegisterRouter.scala:87:24] wire out_woready_1_281; // @[RegisterRouter.scala:87:24] wire out_woready_1_282; // @[RegisterRouter.scala:87:24] wire out_woready_1_283; // @[RegisterRouter.scala:87:24] wire out_woready_1_284; // @[RegisterRouter.scala:87:24] wire out_woready_1_285; // @[RegisterRouter.scala:87:24] wire out_woready_1_286; // @[RegisterRouter.scala:87:24] wire out_woready_1_287; // @[RegisterRouter.scala:87:24] wire out_woready_1_288; // @[RegisterRouter.scala:87:24] wire out_woready_1_289; // @[RegisterRouter.scala:87:24] wire out_woready_1_290; // @[RegisterRouter.scala:87:24] wire out_woready_1_291; // @[RegisterRouter.scala:87:24] wire out_woready_1_292; // @[RegisterRouter.scala:87:24] wire out_woready_1_293; // @[RegisterRouter.scala:87:24] wire out_woready_1_294; // @[RegisterRouter.scala:87:24] wire out_woready_1_295; // @[RegisterRouter.scala:87:24] wire out_woready_1_296; // @[RegisterRouter.scala:87:24] wire out_woready_1_297; // @[RegisterRouter.scala:87:24] wire out_woready_1_298; // @[RegisterRouter.scala:87:24] wire out_woready_1_299; // @[RegisterRouter.scala:87:24] wire out_woready_1_300; // @[RegisterRouter.scala:87:24] wire out_woready_1_301; // @[RegisterRouter.scala:87:24] wire out_woready_1_302; // @[RegisterRouter.scala:87:24] wire out_woready_1_303; // @[RegisterRouter.scala:87:24] wire out_woready_1_304; // @[RegisterRouter.scala:87:24] wire out_woready_1_305; // @[RegisterRouter.scala:87:24] wire out_woready_1_306; // @[RegisterRouter.scala:87:24] wire out_woready_1_307; // @[RegisterRouter.scala:87:24] wire out_woready_1_308; // @[RegisterRouter.scala:87:24] wire out_woready_1_309; // @[RegisterRouter.scala:87:24] wire out_woready_1_310; // @[RegisterRouter.scala:87:24] wire out_woready_1_311; // @[RegisterRouter.scala:87:24] wire out_woready_1_312; // @[RegisterRouter.scala:87:24] wire out_woready_1_313; // @[RegisterRouter.scala:87:24] wire out_woready_1_314; // @[RegisterRouter.scala:87:24] wire out_woready_1_315; // @[RegisterRouter.scala:87:24] wire out_woready_1_316; // @[RegisterRouter.scala:87:24] wire out_woready_1_317; // @[RegisterRouter.scala:87:24] wire out_woready_1_318; // @[RegisterRouter.scala:87:24] wire out_woready_1_319; // @[RegisterRouter.scala:87:24] wire out_woready_1_320; // @[RegisterRouter.scala:87:24] wire out_woready_1_321; // @[RegisterRouter.scala:87:24] wire out_woready_1_322; // @[RegisterRouter.scala:87:24] wire out_woready_1_323; // @[RegisterRouter.scala:87:24] wire out_woready_1_324; // @[RegisterRouter.scala:87:24] wire out_woready_1_325; // @[RegisterRouter.scala:87:24] wire out_woready_1_326; // @[RegisterRouter.scala:87:24] wire out_woready_1_327; // @[RegisterRouter.scala:87:24] wire out_woready_1_328; // @[RegisterRouter.scala:87:24] wire out_woready_1_329; // @[RegisterRouter.scala:87:24] wire out_woready_1_330; // @[RegisterRouter.scala:87:24] wire out_woready_1_331; // @[RegisterRouter.scala:87:24] wire out_woready_1_332; // @[RegisterRouter.scala:87:24] wire out_woready_1_333; // @[RegisterRouter.scala:87:24] wire out_woready_1_334; // @[RegisterRouter.scala:87:24] wire out_woready_1_335; // @[RegisterRouter.scala:87:24] wire out_woready_1_336; // @[RegisterRouter.scala:87:24] wire out_woready_1_337; // @[RegisterRouter.scala:87:24] wire out_woready_1_338; // @[RegisterRouter.scala:87:24] wire out_woready_1_339; // @[RegisterRouter.scala:87:24] wire out_woready_1_340; // @[RegisterRouter.scala:87:24] wire out_woready_1_341; // @[RegisterRouter.scala:87:24] wire out_woready_1_342; // @[RegisterRouter.scala:87:24] wire out_woready_1_343; // @[RegisterRouter.scala:87:24] wire out_woready_1_344; // @[RegisterRouter.scala:87:24] wire out_woready_1_345; // @[RegisterRouter.scala:87:24] wire out_woready_1_346; // @[RegisterRouter.scala:87:24] wire out_woready_1_347; // @[RegisterRouter.scala:87:24] wire out_woready_1_348; // @[RegisterRouter.scala:87:24] wire out_woready_1_349; // @[RegisterRouter.scala:87:24] wire out_woready_1_350; // @[RegisterRouter.scala:87:24] wire out_woready_1_351; // @[RegisterRouter.scala:87:24] wire out_woready_1_352; // @[RegisterRouter.scala:87:24] wire out_woready_1_353; // @[RegisterRouter.scala:87:24] wire out_woready_1_354; // @[RegisterRouter.scala:87:24] wire out_woready_1_355; // @[RegisterRouter.scala:87:24] wire out_woready_1_356; // @[RegisterRouter.scala:87:24] wire out_woready_1_357; // @[RegisterRouter.scala:87:24] wire out_woready_1_358; // @[RegisterRouter.scala:87:24] wire out_woready_1_359; // @[RegisterRouter.scala:87:24] wire out_woready_1_360; // @[RegisterRouter.scala:87:24] wire out_woready_1_361; // @[RegisterRouter.scala:87:24] wire out_woready_1_362; // @[RegisterRouter.scala:87:24] wire out_woready_1_363; // @[RegisterRouter.scala:87:24] wire out_woready_1_364; // @[RegisterRouter.scala:87:24] wire out_woready_1_365; // @[RegisterRouter.scala:87:24] wire out_woready_1_366; // @[RegisterRouter.scala:87:24] wire out_woready_1_367; // @[RegisterRouter.scala:87:24] wire out_woready_1_368; // @[RegisterRouter.scala:87:24] wire out_woready_1_369; // @[RegisterRouter.scala:87:24] wire out_woready_1_370; // @[RegisterRouter.scala:87:24] wire out_woready_1_371; // @[RegisterRouter.scala:87:24] wire out_woready_1_372; // @[RegisterRouter.scala:87:24] wire out_woready_1_373; // @[RegisterRouter.scala:87:24] wire out_woready_1_374; // @[RegisterRouter.scala:87:24] wire out_woready_1_375; // @[RegisterRouter.scala:87:24] wire out_woready_1_376; // @[RegisterRouter.scala:87:24] wire out_woready_1_377; // @[RegisterRouter.scala:87:24] wire out_woready_1_378; // @[RegisterRouter.scala:87:24] wire out_woready_1_379; // @[RegisterRouter.scala:87:24] wire out_woready_1_380; // @[RegisterRouter.scala:87:24] wire out_woready_1_381; // @[RegisterRouter.scala:87:24] wire out_woready_1_382; // @[RegisterRouter.scala:87:24] wire out_woready_1_383; // @[RegisterRouter.scala:87:24] wire out_woready_1_384; // @[RegisterRouter.scala:87:24] wire out_woready_1_385; // @[RegisterRouter.scala:87:24] wire out_woready_1_386; // @[RegisterRouter.scala:87:24] wire out_woready_1_387; // @[RegisterRouter.scala:87:24] wire out_woready_1_388; // @[RegisterRouter.scala:87:24] wire out_woready_1_389; // @[RegisterRouter.scala:87:24] wire out_woready_1_390; // @[RegisterRouter.scala:87:24] wire out_woready_1_391; // @[RegisterRouter.scala:87:24] wire out_woready_1_392; // @[RegisterRouter.scala:87:24] wire out_woready_1_393; // @[RegisterRouter.scala:87:24] wire out_woready_1_394; // @[RegisterRouter.scala:87:24] wire out_woready_1_395; // @[RegisterRouter.scala:87:24] wire out_woready_1_396; // @[RegisterRouter.scala:87:24] wire out_woready_1_397; // @[RegisterRouter.scala:87:24] wire out_woready_1_398; // @[RegisterRouter.scala:87:24] wire out_woready_1_399; // @[RegisterRouter.scala:87:24] wire out_woready_1_400; // @[RegisterRouter.scala:87:24] wire out_woready_1_401; // @[RegisterRouter.scala:87:24] wire out_woready_1_402; // @[RegisterRouter.scala:87:24] wire out_woready_1_403; // @[RegisterRouter.scala:87:24] wire out_woready_1_404; // @[RegisterRouter.scala:87:24] wire out_woready_1_405; // @[RegisterRouter.scala:87:24] wire out_woready_1_406; // @[RegisterRouter.scala:87:24] wire out_woready_1_407; // @[RegisterRouter.scala:87:24] wire out_woready_1_408; // @[RegisterRouter.scala:87:24] wire out_woready_1_409; // @[RegisterRouter.scala:87:24] wire out_woready_1_410; // @[RegisterRouter.scala:87:24] wire out_woready_1_411; // @[RegisterRouter.scala:87:24] wire out_woready_1_412; // @[RegisterRouter.scala:87:24] wire out_woready_1_413; // @[RegisterRouter.scala:87:24] wire out_woready_1_414; // @[RegisterRouter.scala:87:24] wire out_woready_1_415; // @[RegisterRouter.scala:87:24] wire out_woready_1_416; // @[RegisterRouter.scala:87:24] wire out_woready_1_417; // @[RegisterRouter.scala:87:24] wire out_woready_1_418; // @[RegisterRouter.scala:87:24] wire out_woready_1_419; // @[RegisterRouter.scala:87:24] wire out_woready_1_420; // @[RegisterRouter.scala:87:24] wire out_woready_1_421; // @[RegisterRouter.scala:87:24] wire out_woready_1_422; // @[RegisterRouter.scala:87:24] wire out_woready_1_423; // @[RegisterRouter.scala:87:24] wire out_woready_1_424; // @[RegisterRouter.scala:87:24] wire out_woready_1_425; // @[RegisterRouter.scala:87:24] wire out_woready_1_426; // @[RegisterRouter.scala:87:24] wire out_woready_1_427; // @[RegisterRouter.scala:87:24] wire out_woready_1_428; // @[RegisterRouter.scala:87:24] wire out_woready_1_429; // @[RegisterRouter.scala:87:24] wire out_woready_1_430; // @[RegisterRouter.scala:87:24] wire out_woready_1_431; // @[RegisterRouter.scala:87:24] wire out_woready_1_432; // @[RegisterRouter.scala:87:24] wire out_woready_1_433; // @[RegisterRouter.scala:87:24] wire out_woready_1_434; // @[RegisterRouter.scala:87:24] wire out_woready_1_435; // @[RegisterRouter.scala:87:24] wire out_woready_1_436; // @[RegisterRouter.scala:87:24] wire out_woready_1_437; // @[RegisterRouter.scala:87:24] wire out_woready_1_438; // @[RegisterRouter.scala:87:24] wire out_woready_1_439; // @[RegisterRouter.scala:87:24] wire out_woready_1_440; // @[RegisterRouter.scala:87:24] wire out_woready_1_441; // @[RegisterRouter.scala:87:24] wire out_woready_1_442; // @[RegisterRouter.scala:87:24] wire out_woready_1_443; // @[RegisterRouter.scala:87:24] wire out_woready_1_444; // @[RegisterRouter.scala:87:24] wire out_woready_1_445; // @[RegisterRouter.scala:87:24] wire out_woready_1_446; // @[RegisterRouter.scala:87:24] wire out_woready_1_447; // @[RegisterRouter.scala:87:24] wire out_woready_1_448; // @[RegisterRouter.scala:87:24] wire out_woready_1_449; // @[RegisterRouter.scala:87:24] wire out_woready_1_450; // @[RegisterRouter.scala:87:24] wire out_woready_1_451; // @[RegisterRouter.scala:87:24] wire out_woready_1_452; // @[RegisterRouter.scala:87:24] wire out_woready_1_453; // @[RegisterRouter.scala:87:24] wire out_woready_1_454; // @[RegisterRouter.scala:87:24] wire out_woready_1_455; // @[RegisterRouter.scala:87:24] wire out_woready_1_456; // @[RegisterRouter.scala:87:24] wire out_woready_1_457; // @[RegisterRouter.scala:87:24] wire out_woready_1_458; // @[RegisterRouter.scala:87:24] wire out_woready_1_459; // @[RegisterRouter.scala:87:24] wire out_woready_1_460; // @[RegisterRouter.scala:87:24] wire out_woready_1_461; // @[RegisterRouter.scala:87:24] wire out_woready_1_462; // @[RegisterRouter.scala:87:24] wire out_woready_1_463; // @[RegisterRouter.scala:87:24] wire out_woready_1_464; // @[RegisterRouter.scala:87:24] wire out_woready_1_465; // @[RegisterRouter.scala:87:24] wire out_woready_1_466; // @[RegisterRouter.scala:87:24] wire out_woready_1_467; // @[RegisterRouter.scala:87:24] wire out_woready_1_468; // @[RegisterRouter.scala:87:24] wire out_woready_1_469; // @[RegisterRouter.scala:87:24] wire out_woready_1_470; // @[RegisterRouter.scala:87:24] wire out_woready_1_471; // @[RegisterRouter.scala:87:24] wire out_woready_1_472; // @[RegisterRouter.scala:87:24] wire out_woready_1_473; // @[RegisterRouter.scala:87:24] wire out_woready_1_474; // @[RegisterRouter.scala:87:24] wire out_woready_1_475; // @[RegisterRouter.scala:87:24] wire out_woready_1_476; // @[RegisterRouter.scala:87:24] wire out_woready_1_477; // @[RegisterRouter.scala:87:24] wire out_woready_1_478; // @[RegisterRouter.scala:87:24] wire out_woready_1_479; // @[RegisterRouter.scala:87:24] wire out_woready_1_480; // @[RegisterRouter.scala:87:24] wire out_woready_1_481; // @[RegisterRouter.scala:87:24] wire out_woready_1_482; // @[RegisterRouter.scala:87:24] wire out_woready_1_483; // @[RegisterRouter.scala:87:24] wire out_woready_1_484; // @[RegisterRouter.scala:87:24] wire out_woready_1_485; // @[RegisterRouter.scala:87:24] wire out_woready_1_486; // @[RegisterRouter.scala:87:24] wire out_woready_1_487; // @[RegisterRouter.scala:87:24] wire out_woready_1_488; // @[RegisterRouter.scala:87:24] wire out_woready_1_489; // @[RegisterRouter.scala:87:24] wire out_woready_1_490; // @[RegisterRouter.scala:87:24] wire out_woready_1_491; // @[RegisterRouter.scala:87:24] wire out_woready_1_492; // @[RegisterRouter.scala:87:24] wire out_woready_1_493; // @[RegisterRouter.scala:87:24] wire out_woready_1_494; // @[RegisterRouter.scala:87:24] wire out_woready_1_495; // @[RegisterRouter.scala:87:24] wire out_woready_1_496; // @[RegisterRouter.scala:87:24] wire out_woready_1_497; // @[RegisterRouter.scala:87:24] wire out_woready_1_498; // @[RegisterRouter.scala:87:24] wire out_woready_1_499; // @[RegisterRouter.scala:87:24] wire out_woready_1_500; // @[RegisterRouter.scala:87:24] wire out_woready_1_501; // @[RegisterRouter.scala:87:24] wire out_woready_1_502; // @[RegisterRouter.scala:87:24] wire out_woready_1_503; // @[RegisterRouter.scala:87:24] wire out_woready_1_504; // @[RegisterRouter.scala:87:24] wire out_woready_1_505; // @[RegisterRouter.scala:87:24] wire out_woready_1_506; // @[RegisterRouter.scala:87:24] wire out_woready_1_507; // @[RegisterRouter.scala:87:24] wire out_woready_1_508; // @[RegisterRouter.scala:87:24] wire out_woready_1_509; // @[RegisterRouter.scala:87:24] wire out_woready_1_510; // @[RegisterRouter.scala:87:24] wire out_woready_1_511; // @[RegisterRouter.scala:87:24] wire out_woready_1_512; // @[RegisterRouter.scala:87:24] wire out_woready_1_513; // @[RegisterRouter.scala:87:24] wire out_woready_1_514; // @[RegisterRouter.scala:87:24] wire out_woready_1_515; // @[RegisterRouter.scala:87:24] wire out_woready_1_516; // @[RegisterRouter.scala:87:24] wire out_woready_1_517; // @[RegisterRouter.scala:87:24] wire out_woready_1_518; // @[RegisterRouter.scala:87:24] wire out_woready_1_519; // @[RegisterRouter.scala:87:24] wire out_woready_1_520; // @[RegisterRouter.scala:87:24] wire out_woready_1_521; // @[RegisterRouter.scala:87:24] wire out_woready_1_522; // @[RegisterRouter.scala:87:24] wire out_woready_1_523; // @[RegisterRouter.scala:87:24] wire out_woready_1_524; // @[RegisterRouter.scala:87:24] wire out_woready_1_525; // @[RegisterRouter.scala:87:24] wire out_woready_1_526; // @[RegisterRouter.scala:87:24] wire out_woready_1_527; // @[RegisterRouter.scala:87:24] wire out_woready_1_528; // @[RegisterRouter.scala:87:24] wire out_woready_1_529; // @[RegisterRouter.scala:87:24] wire out_woready_1_530; // @[RegisterRouter.scala:87:24] wire out_woready_1_531; // @[RegisterRouter.scala:87:24] wire out_woready_1_532; // @[RegisterRouter.scala:87:24] wire out_woready_1_533; // @[RegisterRouter.scala:87:24] wire out_woready_1_534; // @[RegisterRouter.scala:87:24] wire out_woready_1_535; // @[RegisterRouter.scala:87:24] wire out_woready_1_536; // @[RegisterRouter.scala:87:24] wire out_woready_1_537; // @[RegisterRouter.scala:87:24] wire out_woready_1_538; // @[RegisterRouter.scala:87:24] wire out_woready_1_539; // @[RegisterRouter.scala:87:24] wire out_woready_1_540; // @[RegisterRouter.scala:87:24] wire out_woready_1_541; // @[RegisterRouter.scala:87:24] wire out_woready_1_542; // @[RegisterRouter.scala:87:24] wire out_woready_1_543; // @[RegisterRouter.scala:87:24] wire out_woready_1_544; // @[RegisterRouter.scala:87:24] wire out_woready_1_545; // @[RegisterRouter.scala:87:24] wire out_woready_1_546; // @[RegisterRouter.scala:87:24] wire out_woready_1_547; // @[RegisterRouter.scala:87:24] wire out_woready_1_548; // @[RegisterRouter.scala:87:24] wire out_woready_1_549; // @[RegisterRouter.scala:87:24] wire out_woready_1_550; // @[RegisterRouter.scala:87:24] wire out_woready_1_551; // @[RegisterRouter.scala:87:24] wire out_woready_1_552; // @[RegisterRouter.scala:87:24] wire out_woready_1_553; // @[RegisterRouter.scala:87:24] wire out_woready_1_554; // @[RegisterRouter.scala:87:24] wire out_woready_1_555; // @[RegisterRouter.scala:87:24] wire out_woready_1_556; // @[RegisterRouter.scala:87:24] wire out_woready_1_557; // @[RegisterRouter.scala:87:24] wire out_woready_1_558; // @[RegisterRouter.scala:87:24] wire out_woready_1_559; // @[RegisterRouter.scala:87:24] wire out_woready_1_560; // @[RegisterRouter.scala:87:24] wire out_woready_1_561; // @[RegisterRouter.scala:87:24] wire out_woready_1_562; // @[RegisterRouter.scala:87:24] wire out_woready_1_563; // @[RegisterRouter.scala:87:24] wire out_woready_1_564; // @[RegisterRouter.scala:87:24] wire out_woready_1_565; // @[RegisterRouter.scala:87:24] wire out_woready_1_566; // @[RegisterRouter.scala:87:24] wire out_woready_1_567; // @[RegisterRouter.scala:87:24] wire out_woready_1_568; // @[RegisterRouter.scala:87:24] wire out_woready_1_569; // @[RegisterRouter.scala:87:24] wire out_woready_1_570; // @[RegisterRouter.scala:87:24] wire out_woready_1_571; // @[RegisterRouter.scala:87:24] wire out_woready_1_572; // @[RegisterRouter.scala:87:24] wire out_woready_1_573; // @[RegisterRouter.scala:87:24] wire out_woready_1_574; // @[RegisterRouter.scala:87:24] wire out_woready_1_575; // @[RegisterRouter.scala:87:24] wire out_woready_1_576; // @[RegisterRouter.scala:87:24] wire out_woready_1_577; // @[RegisterRouter.scala:87:24] wire out_woready_1_578; // @[RegisterRouter.scala:87:24] wire out_woready_1_579; // @[RegisterRouter.scala:87:24] wire out_woready_1_580; // @[RegisterRouter.scala:87:24] wire out_woready_1_581; // @[RegisterRouter.scala:87:24] wire out_woready_1_582; // @[RegisterRouter.scala:87:24] wire out_woready_1_583; // @[RegisterRouter.scala:87:24] wire out_woready_1_584; // @[RegisterRouter.scala:87:24] wire out_woready_1_585; // @[RegisterRouter.scala:87:24] wire out_woready_1_586; // @[RegisterRouter.scala:87:24] wire out_woready_1_587; // @[RegisterRouter.scala:87:24] wire out_woready_1_588; // @[RegisterRouter.scala:87:24] wire out_woready_1_589; // @[RegisterRouter.scala:87:24] wire out_woready_1_590; // @[RegisterRouter.scala:87:24] wire out_woready_1_591; // @[RegisterRouter.scala:87:24] wire out_woready_1_592; // @[RegisterRouter.scala:87:24] wire out_woready_1_593; // @[RegisterRouter.scala:87:24] wire out_woready_1_594; // @[RegisterRouter.scala:87:24] wire out_woready_1_595; // @[RegisterRouter.scala:87:24] wire out_woready_1_596; // @[RegisterRouter.scala:87:24] wire out_woready_1_597; // @[RegisterRouter.scala:87:24] wire out_woready_1_598; // @[RegisterRouter.scala:87:24] wire out_woready_1_599; // @[RegisterRouter.scala:87:24] wire out_woready_1_600; // @[RegisterRouter.scala:87:24] wire out_woready_1_601; // @[RegisterRouter.scala:87:24] wire out_woready_1_602; // @[RegisterRouter.scala:87:24] wire out_woready_1_603; // @[RegisterRouter.scala:87:24] wire out_woready_1_604; // @[RegisterRouter.scala:87:24] wire out_woready_1_605; // @[RegisterRouter.scala:87:24] wire out_woready_1_606; // @[RegisterRouter.scala:87:24] wire out_woready_1_607; // @[RegisterRouter.scala:87:24] wire out_woready_1_608; // @[RegisterRouter.scala:87:24] wire out_woready_1_609; // @[RegisterRouter.scala:87:24] wire out_woready_1_610; // @[RegisterRouter.scala:87:24] wire out_woready_1_611; // @[RegisterRouter.scala:87:24] wire out_woready_1_612; // @[RegisterRouter.scala:87:24] wire out_woready_1_613; // @[RegisterRouter.scala:87:24] wire out_woready_1_614; // @[RegisterRouter.scala:87:24] wire out_woready_1_615; // @[RegisterRouter.scala:87:24] wire out_woready_1_616; // @[RegisterRouter.scala:87:24] wire out_woready_1_617; // @[RegisterRouter.scala:87:24] wire out_woready_1_618; // @[RegisterRouter.scala:87:24] wire out_woready_1_619; // @[RegisterRouter.scala:87:24] wire out_woready_1_620; // @[RegisterRouter.scala:87:24] wire out_woready_1_621; // @[RegisterRouter.scala:87:24] wire out_woready_1_622; // @[RegisterRouter.scala:87:24] wire out_woready_1_623; // @[RegisterRouter.scala:87:24] wire out_woready_1_624; // @[RegisterRouter.scala:87:24] wire out_woready_1_625; // @[RegisterRouter.scala:87:24] wire out_woready_1_626; // @[RegisterRouter.scala:87:24] wire out_woready_1_627; // @[RegisterRouter.scala:87:24] wire out_woready_1_628; // @[RegisterRouter.scala:87:24] wire out_woready_1_629; // @[RegisterRouter.scala:87:24] wire out_woready_1_630; // @[RegisterRouter.scala:87:24] wire out_woready_1_631; // @[RegisterRouter.scala:87:24] wire out_woready_1_632; // @[RegisterRouter.scala:87:24] wire out_woready_1_633; // @[RegisterRouter.scala:87:24] wire out_woready_1_634; // @[RegisterRouter.scala:87:24] wire out_woready_1_635; // @[RegisterRouter.scala:87:24] wire out_woready_1_636; // @[RegisterRouter.scala:87:24] wire out_woready_1_637; // @[RegisterRouter.scala:87:24] wire out_woready_1_638; // @[RegisterRouter.scala:87:24] wire out_woready_1_639; // @[RegisterRouter.scala:87:24] wire out_woready_1_640; // @[RegisterRouter.scala:87:24] wire out_woready_1_641; // @[RegisterRouter.scala:87:24] wire out_woready_1_642; // @[RegisterRouter.scala:87:24] wire out_woready_1_643; // @[RegisterRouter.scala:87:24] wire out_woready_1_644; // @[RegisterRouter.scala:87:24] wire out_woready_1_645; // @[RegisterRouter.scala:87:24] wire out_woready_1_646; // @[RegisterRouter.scala:87:24] wire out_woready_1_647; // @[RegisterRouter.scala:87:24] wire out_woready_1_648; // @[RegisterRouter.scala:87:24] wire out_woready_1_649; // @[RegisterRouter.scala:87:24] wire out_woready_1_650; // @[RegisterRouter.scala:87:24] wire out_woready_1_651; // @[RegisterRouter.scala:87:24] wire out_woready_1_652; // @[RegisterRouter.scala:87:24] wire out_woready_1_653; // @[RegisterRouter.scala:87:24] wire out_woready_1_654; // @[RegisterRouter.scala:87:24] wire out_woready_1_655; // @[RegisterRouter.scala:87:24] wire out_woready_1_656; // @[RegisterRouter.scala:87:24] wire out_woready_1_657; // @[RegisterRouter.scala:87:24] wire out_woready_1_658; // @[RegisterRouter.scala:87:24] wire out_woready_1_659; // @[RegisterRouter.scala:87:24] wire out_woready_1_660; // @[RegisterRouter.scala:87:24] wire out_woready_1_661; // @[RegisterRouter.scala:87:24] wire out_woready_1_662; // @[RegisterRouter.scala:87:24] wire out_woready_1_663; // @[RegisterRouter.scala:87:24] wire out_woready_1_664; // @[RegisterRouter.scala:87:24] wire out_woready_1_665; // @[RegisterRouter.scala:87:24] wire out_woready_1_666; // @[RegisterRouter.scala:87:24] wire out_woready_1_667; // @[RegisterRouter.scala:87:24] wire out_woready_1_668; // @[RegisterRouter.scala:87:24] wire out_woready_1_669; // @[RegisterRouter.scala:87:24] wire out_woready_1_670; // @[RegisterRouter.scala:87:24] wire out_woready_1_671; // @[RegisterRouter.scala:87:24] wire out_woready_1_672; // @[RegisterRouter.scala:87:24] wire out_woready_1_673; // @[RegisterRouter.scala:87:24] wire out_woready_1_674; // @[RegisterRouter.scala:87:24] wire out_woready_1_675; // @[RegisterRouter.scala:87:24] wire out_woready_1_676; // @[RegisterRouter.scala:87:24] wire out_woready_1_677; // @[RegisterRouter.scala:87:24] wire out_woready_1_678; // @[RegisterRouter.scala:87:24] wire out_woready_1_679; // @[RegisterRouter.scala:87:24] wire out_woready_1_680; // @[RegisterRouter.scala:87:24] wire out_woready_1_681; // @[RegisterRouter.scala:87:24] wire out_woready_1_682; // @[RegisterRouter.scala:87:24] wire out_woready_1_683; // @[RegisterRouter.scala:87:24] wire out_woready_1_684; // @[RegisterRouter.scala:87:24] wire out_woready_1_685; // @[RegisterRouter.scala:87:24] wire out_woready_1_686; // @[RegisterRouter.scala:87:24] wire out_woready_1_687; // @[RegisterRouter.scala:87:24] wire out_woready_1_688; // @[RegisterRouter.scala:87:24] wire out_woready_1_689; // @[RegisterRouter.scala:87:24] wire out_woready_1_690; // @[RegisterRouter.scala:87:24] wire out_woready_1_691; // @[RegisterRouter.scala:87:24] wire out_woready_1_692; // @[RegisterRouter.scala:87:24] wire out_woready_1_693; // @[RegisterRouter.scala:87:24] wire out_woready_1_694; // @[RegisterRouter.scala:87:24] wire out_woready_1_695; // @[RegisterRouter.scala:87:24] wire out_woready_1_696; // @[RegisterRouter.scala:87:24] wire out_woready_1_697; // @[RegisterRouter.scala:87:24] wire out_woready_1_698; // @[RegisterRouter.scala:87:24] wire out_woready_1_699; // @[RegisterRouter.scala:87:24] wire out_woready_1_700; // @[RegisterRouter.scala:87:24] wire out_woready_1_701; // @[RegisterRouter.scala:87:24] wire out_woready_1_702; // @[RegisterRouter.scala:87:24] wire out_woready_1_703; // @[RegisterRouter.scala:87:24] wire out_woready_1_704; // @[RegisterRouter.scala:87:24] wire out_woready_1_705; // @[RegisterRouter.scala:87:24] wire out_woready_1_706; // @[RegisterRouter.scala:87:24] wire out_woready_1_707; // @[RegisterRouter.scala:87:24] wire out_woready_1_708; // @[RegisterRouter.scala:87:24] wire out_woready_1_709; // @[RegisterRouter.scala:87:24] wire out_woready_1_710; // @[RegisterRouter.scala:87:24] wire out_woready_1_711; // @[RegisterRouter.scala:87:24] wire out_woready_1_712; // @[RegisterRouter.scala:87:24] wire out_woready_1_713; // @[RegisterRouter.scala:87:24] wire out_woready_1_714; // @[RegisterRouter.scala:87:24] wire out_woready_1_715; // @[RegisterRouter.scala:87:24] wire out_woready_1_716; // @[RegisterRouter.scala:87:24] wire out_woready_1_717; // @[RegisterRouter.scala:87:24] wire out_woready_1_718; // @[RegisterRouter.scala:87:24] wire out_woready_1_719; // @[RegisterRouter.scala:87:24] wire out_woready_1_720; // @[RegisterRouter.scala:87:24] wire out_woready_1_721; // @[RegisterRouter.scala:87:24] wire out_woready_1_722; // @[RegisterRouter.scala:87:24] wire out_woready_1_723; // @[RegisterRouter.scala:87:24] wire out_woready_1_724; // @[RegisterRouter.scala:87:24] wire out_woready_1_725; // @[RegisterRouter.scala:87:24] wire out_woready_1_726; // @[RegisterRouter.scala:87:24] wire out_woready_1_727; // @[RegisterRouter.scala:87:24] wire out_woready_1_728; // @[RegisterRouter.scala:87:24] wire out_woready_1_729; // @[RegisterRouter.scala:87:24] wire out_woready_1_730; // @[RegisterRouter.scala:87:24] wire out_woready_1_731; // @[RegisterRouter.scala:87:24] wire out_woready_1_732; // @[RegisterRouter.scala:87:24] wire out_woready_1_733; // @[RegisterRouter.scala:87:24] wire out_woready_1_734; // @[RegisterRouter.scala:87:24] wire out_woready_1_735; // @[RegisterRouter.scala:87:24] wire out_woready_1_736; // @[RegisterRouter.scala:87:24] wire out_woready_1_737; // @[RegisterRouter.scala:87:24] wire out_woready_1_738; // @[RegisterRouter.scala:87:24] wire out_woready_1_739; // @[RegisterRouter.scala:87:24] wire out_woready_1_740; // @[RegisterRouter.scala:87:24] wire out_woready_1_741; // @[RegisterRouter.scala:87:24] wire out_woready_1_742; // @[RegisterRouter.scala:87:24] wire out_woready_1_743; // @[RegisterRouter.scala:87:24] wire out_woready_1_744; // @[RegisterRouter.scala:87:24] wire out_woready_1_745; // @[RegisterRouter.scala:87:24] wire out_woready_1_746; // @[RegisterRouter.scala:87:24] wire out_woready_1_747; // @[RegisterRouter.scala:87:24] wire out_woready_1_748; // @[RegisterRouter.scala:87:24] wire out_woready_1_749; // @[RegisterRouter.scala:87:24] wire out_woready_1_750; // @[RegisterRouter.scala:87:24] wire out_woready_1_751; // @[RegisterRouter.scala:87:24] wire out_woready_1_752; // @[RegisterRouter.scala:87:24] wire out_woready_1_753; // @[RegisterRouter.scala:87:24] wire out_woready_1_754; // @[RegisterRouter.scala:87:24] wire out_woready_1_755; // @[RegisterRouter.scala:87:24] wire out_woready_1_756; // @[RegisterRouter.scala:87:24] wire out_woready_1_757; // @[RegisterRouter.scala:87:24] wire out_woready_1_758; // @[RegisterRouter.scala:87:24] wire out_woready_1_759; // @[RegisterRouter.scala:87:24] wire out_woready_1_760; // @[RegisterRouter.scala:87:24] wire out_woready_1_761; // @[RegisterRouter.scala:87:24] wire out_woready_1_762; // @[RegisterRouter.scala:87:24] wire out_woready_1_763; // @[RegisterRouter.scala:87:24] wire out_woready_1_764; // @[RegisterRouter.scala:87:24] wire out_woready_1_765; // @[RegisterRouter.scala:87:24] wire out_woready_1_766; // @[RegisterRouter.scala:87:24] wire out_woready_1_767; // @[RegisterRouter.scala:87:24] wire out_woready_1_768; // @[RegisterRouter.scala:87:24] wire out_woready_1_769; // @[RegisterRouter.scala:87:24] wire out_woready_1_770; // @[RegisterRouter.scala:87:24] wire out_woready_1_771; // @[RegisterRouter.scala:87:24] wire out_woready_1_772; // @[RegisterRouter.scala:87:24] wire out_woready_1_773; // @[RegisterRouter.scala:87:24] wire out_woready_1_774; // @[RegisterRouter.scala:87:24] wire out_woready_1_775; // @[RegisterRouter.scala:87:24] wire out_woready_1_776; // @[RegisterRouter.scala:87:24] wire out_woready_1_777; // @[RegisterRouter.scala:87:24] wire out_woready_1_778; // @[RegisterRouter.scala:87:24] wire out_woready_1_779; // @[RegisterRouter.scala:87:24] wire out_woready_1_780; // @[RegisterRouter.scala:87:24] wire out_woready_1_781; // @[RegisterRouter.scala:87:24] wire out_woready_1_782; // @[RegisterRouter.scala:87:24] wire out_woready_1_783; // @[RegisterRouter.scala:87:24] wire out_woready_1_784; // @[RegisterRouter.scala:87:24] wire out_woready_1_785; // @[RegisterRouter.scala:87:24] wire out_woready_1_786; // @[RegisterRouter.scala:87:24] wire out_woready_1_787; // @[RegisterRouter.scala:87:24] wire out_woready_1_788; // @[RegisterRouter.scala:87:24] wire out_woready_1_789; // @[RegisterRouter.scala:87:24] wire out_woready_1_790; // @[RegisterRouter.scala:87:24] wire out_woready_1_791; // @[RegisterRouter.scala:87:24] wire out_woready_1_792; // @[RegisterRouter.scala:87:24] wire out_woready_1_793; // @[RegisterRouter.scala:87:24] wire out_woready_1_794; // @[RegisterRouter.scala:87:24] wire out_woready_1_795; // @[RegisterRouter.scala:87:24] wire out_woready_1_796; // @[RegisterRouter.scala:87:24] wire out_woready_1_797; // @[RegisterRouter.scala:87:24] wire out_woready_1_798; // @[RegisterRouter.scala:87:24] wire out_woready_1_799; // @[RegisterRouter.scala:87:24] wire out_woready_1_800; // @[RegisterRouter.scala:87:24] wire out_woready_1_801; // @[RegisterRouter.scala:87:24] wire out_woready_1_802; // @[RegisterRouter.scala:87:24] wire out_woready_1_803; // @[RegisterRouter.scala:87:24] wire out_woready_1_804; // @[RegisterRouter.scala:87:24] wire out_woready_1_805; // @[RegisterRouter.scala:87:24] wire out_woready_1_806; // @[RegisterRouter.scala:87:24] wire out_woready_1_807; // @[RegisterRouter.scala:87:24] wire out_woready_1_808; // @[RegisterRouter.scala:87:24] wire out_woready_1_809; // @[RegisterRouter.scala:87:24] wire out_woready_1_810; // @[RegisterRouter.scala:87:24] wire out_woready_1_811; // @[RegisterRouter.scala:87:24] wire out_woready_1_812; // @[RegisterRouter.scala:87:24] wire out_woready_1_813; // @[RegisterRouter.scala:87:24] wire out_woready_1_814; // @[RegisterRouter.scala:87:24] wire out_woready_1_815; // @[RegisterRouter.scala:87:24] wire out_woready_1_816; // @[RegisterRouter.scala:87:24] wire out_woready_1_817; // @[RegisterRouter.scala:87:24] wire out_woready_1_818; // @[RegisterRouter.scala:87:24] wire out_woready_1_819; // @[RegisterRouter.scala:87:24] wire out_woready_1_820; // @[RegisterRouter.scala:87:24] wire out_woready_1_821; // @[RegisterRouter.scala:87:24] wire out_woready_1_822; // @[RegisterRouter.scala:87:24] wire out_woready_1_823; // @[RegisterRouter.scala:87:24] wire out_woready_1_824; // @[RegisterRouter.scala:87:24] wire out_woready_1_825; // @[RegisterRouter.scala:87:24] wire out_woready_1_826; // @[RegisterRouter.scala:87:24] wire out_woready_1_827; // @[RegisterRouter.scala:87:24] wire out_woready_1_828; // @[RegisterRouter.scala:87:24] wire out_woready_1_829; // @[RegisterRouter.scala:87:24] wire out_woready_1_830; // @[RegisterRouter.scala:87:24] wire out_woready_1_831; // @[RegisterRouter.scala:87:24] wire out_woready_1_832; // @[RegisterRouter.scala:87:24] wire out_woready_1_833; // @[RegisterRouter.scala:87:24] wire out_woready_1_834; // @[RegisterRouter.scala:87:24] wire out_woready_1_835; // @[RegisterRouter.scala:87:24] wire out_woready_1_836; // @[RegisterRouter.scala:87:24] wire out_woready_1_837; // @[RegisterRouter.scala:87:24] wire out_woready_1_838; // @[RegisterRouter.scala:87:24] wire out_woready_1_839; // @[RegisterRouter.scala:87:24] wire out_woready_1_840; // @[RegisterRouter.scala:87:24] wire out_woready_1_841; // @[RegisterRouter.scala:87:24] wire out_woready_1_842; // @[RegisterRouter.scala:87:24] wire out_woready_1_843; // @[RegisterRouter.scala:87:24] wire out_woready_1_844; // @[RegisterRouter.scala:87:24] wire out_woready_1_845; // @[RegisterRouter.scala:87:24] wire out_woready_1_846; // @[RegisterRouter.scala:87:24] wire out_woready_1_847; // @[RegisterRouter.scala:87:24] wire out_woready_1_848; // @[RegisterRouter.scala:87:24] wire out_woready_1_849; // @[RegisterRouter.scala:87:24] wire out_woready_1_850; // @[RegisterRouter.scala:87:24] wire out_woready_1_851; // @[RegisterRouter.scala:87:24] wire out_woready_1_852; // @[RegisterRouter.scala:87:24] wire out_woready_1_853; // @[RegisterRouter.scala:87:24] wire out_woready_1_854; // @[RegisterRouter.scala:87:24] wire out_woready_1_855; // @[RegisterRouter.scala:87:24] wire out_woready_1_856; // @[RegisterRouter.scala:87:24] wire out_woready_1_857; // @[RegisterRouter.scala:87:24] wire out_woready_1_858; // @[RegisterRouter.scala:87:24] wire out_woready_1_859; // @[RegisterRouter.scala:87:24] wire out_woready_1_860; // @[RegisterRouter.scala:87:24] wire out_woready_1_861; // @[RegisterRouter.scala:87:24] wire out_woready_1_862; // @[RegisterRouter.scala:87:24] wire out_woready_1_863; // @[RegisterRouter.scala:87:24] wire out_woready_1_864; // @[RegisterRouter.scala:87:24] wire out_woready_1_865; // @[RegisterRouter.scala:87:24] wire out_woready_1_866; // @[RegisterRouter.scala:87:24] wire out_woready_1_867; // @[RegisterRouter.scala:87:24] wire out_woready_1_868; // @[RegisterRouter.scala:87:24] wire out_woready_1_869; // @[RegisterRouter.scala:87:24] wire out_woready_1_870; // @[RegisterRouter.scala:87:24] wire out_woready_1_871; // @[RegisterRouter.scala:87:24] wire out_woready_1_872; // @[RegisterRouter.scala:87:24] wire out_woready_1_873; // @[RegisterRouter.scala:87:24] wire out_woready_1_874; // @[RegisterRouter.scala:87:24] wire out_woready_1_875; // @[RegisterRouter.scala:87:24] wire out_woready_1_876; // @[RegisterRouter.scala:87:24] wire out_woready_1_877; // @[RegisterRouter.scala:87:24] wire out_woready_1_878; // @[RegisterRouter.scala:87:24] wire out_woready_1_879; // @[RegisterRouter.scala:87:24] wire out_woready_1_880; // @[RegisterRouter.scala:87:24] wire out_woready_1_881; // @[RegisterRouter.scala:87:24] wire out_woready_1_882; // @[RegisterRouter.scala:87:24] wire out_woready_1_883; // @[RegisterRouter.scala:87:24] wire out_woready_1_884; // @[RegisterRouter.scala:87:24] wire out_woready_1_885; // @[RegisterRouter.scala:87:24] wire out_woready_1_886; // @[RegisterRouter.scala:87:24] wire out_woready_1_887; // @[RegisterRouter.scala:87:24] wire out_woready_1_888; // @[RegisterRouter.scala:87:24] wire out_woready_1_889; // @[RegisterRouter.scala:87:24] wire out_woready_1_890; // @[RegisterRouter.scala:87:24] wire out_woready_1_891; // @[RegisterRouter.scala:87:24] wire out_woready_1_892; // @[RegisterRouter.scala:87:24] wire out_woready_1_893; // @[RegisterRouter.scala:87:24] wire out_woready_1_894; // @[RegisterRouter.scala:87:24] wire out_woready_1_895; // @[RegisterRouter.scala:87:24] wire out_woready_1_896; // @[RegisterRouter.scala:87:24] wire out_woready_1_897; // @[RegisterRouter.scala:87:24] wire out_woready_1_898; // @[RegisterRouter.scala:87:24] wire out_woready_1_899; // @[RegisterRouter.scala:87:24] wire out_woready_1_900; // @[RegisterRouter.scala:87:24] wire out_woready_1_901; // @[RegisterRouter.scala:87:24] wire out_woready_1_902; // @[RegisterRouter.scala:87:24] wire out_woready_1_903; // @[RegisterRouter.scala:87:24] wire out_woready_1_904; // @[RegisterRouter.scala:87:24] wire out_woready_1_905; // @[RegisterRouter.scala:87:24] wire out_woready_1_906; // @[RegisterRouter.scala:87:24] wire out_woready_1_907; // @[RegisterRouter.scala:87:24] wire out_woready_1_908; // @[RegisterRouter.scala:87:24] wire out_woready_1_909; // @[RegisterRouter.scala:87:24] wire out_woready_1_910; // @[RegisterRouter.scala:87:24] wire out_woready_1_911; // @[RegisterRouter.scala:87:24] wire out_woready_1_912; // @[RegisterRouter.scala:87:24] wire out_woready_1_913; // @[RegisterRouter.scala:87:24] wire out_woready_1_914; // @[RegisterRouter.scala:87:24] wire out_woready_1_915; // @[RegisterRouter.scala:87:24] wire out_woready_1_916; // @[RegisterRouter.scala:87:24] wire out_woready_1_917; // @[RegisterRouter.scala:87:24] wire out_woready_1_918; // @[RegisterRouter.scala:87:24] wire out_woready_1_919; // @[RegisterRouter.scala:87:24] wire out_woready_1_920; // @[RegisterRouter.scala:87:24] wire out_woready_1_921; // @[RegisterRouter.scala:87:24] wire out_woready_1_922; // @[RegisterRouter.scala:87:24] wire out_woready_1_923; // @[RegisterRouter.scala:87:24] wire out_woready_1_924; // @[RegisterRouter.scala:87:24] wire out_woready_1_925; // @[RegisterRouter.scala:87:24] wire out_woready_1_926; // @[RegisterRouter.scala:87:24] wire out_woready_1_927; // @[RegisterRouter.scala:87:24] wire out_woready_1_928; // @[RegisterRouter.scala:87:24] wire out_woready_1_929; // @[RegisterRouter.scala:87:24] wire out_woready_1_930; // @[RegisterRouter.scala:87:24] wire out_woready_1_931; // @[RegisterRouter.scala:87:24] wire out_woready_1_932; // @[RegisterRouter.scala:87:24] wire out_woready_1_933; // @[RegisterRouter.scala:87:24] wire out_woready_1_934; // @[RegisterRouter.scala:87:24] wire out_woready_1_935; // @[RegisterRouter.scala:87:24] wire out_woready_1_936; // @[RegisterRouter.scala:87:24] wire out_woready_1_937; // @[RegisterRouter.scala:87:24] wire out_woready_1_938; // @[RegisterRouter.scala:87:24] wire out_woready_1_939; // @[RegisterRouter.scala:87:24] wire out_woready_1_940; // @[RegisterRouter.scala:87:24] wire out_woready_1_941; // @[RegisterRouter.scala:87:24] wire out_woready_1_942; // @[RegisterRouter.scala:87:24] wire out_woready_1_943; // @[RegisterRouter.scala:87:24] wire out_woready_1_944; // @[RegisterRouter.scala:87:24] wire out_woready_1_945; // @[RegisterRouter.scala:87:24] wire out_woready_1_946; // @[RegisterRouter.scala:87:24] wire out_woready_1_947; // @[RegisterRouter.scala:87:24] wire out_woready_1_948; // @[RegisterRouter.scala:87:24] wire out_woready_1_949; // @[RegisterRouter.scala:87:24] wire out_woready_1_950; // @[RegisterRouter.scala:87:24] wire out_woready_1_951; // @[RegisterRouter.scala:87:24] wire out_woready_1_952; // @[RegisterRouter.scala:87:24] wire out_woready_1_953; // @[RegisterRouter.scala:87:24] wire out_woready_1_954; // @[RegisterRouter.scala:87:24] wire out_woready_1_955; // @[RegisterRouter.scala:87:24] wire out_woready_1_956; // @[RegisterRouter.scala:87:24] wire out_woready_1_957; // @[RegisterRouter.scala:87:24] wire out_woready_1_958; // @[RegisterRouter.scala:87:24] wire out_woready_1_959; // @[RegisterRouter.scala:87:24] wire out_woready_1_960; // @[RegisterRouter.scala:87:24] wire out_woready_1_961; // @[RegisterRouter.scala:87:24] wire out_woready_1_962; // @[RegisterRouter.scala:87:24] wire out_woready_1_963; // @[RegisterRouter.scala:87:24] wire out_woready_1_964; // @[RegisterRouter.scala:87:24] wire out_woready_1_965; // @[RegisterRouter.scala:87:24] wire out_woready_1_966; // @[RegisterRouter.scala:87:24] wire out_woready_1_967; // @[RegisterRouter.scala:87:24] wire out_woready_1_968; // @[RegisterRouter.scala:87:24] wire out_woready_1_969; // @[RegisterRouter.scala:87:24] wire out_woready_1_970; // @[RegisterRouter.scala:87:24] wire out_woready_1_971; // @[RegisterRouter.scala:87:24] wire out_woready_1_972; // @[RegisterRouter.scala:87:24] wire out_woready_1_973; // @[RegisterRouter.scala:87:24] wire out_woready_1_974; // @[RegisterRouter.scala:87:24] wire out_woready_1_975; // @[RegisterRouter.scala:87:24] wire out_woready_1_976; // @[RegisterRouter.scala:87:24] wire out_woready_1_977; // @[RegisterRouter.scala:87:24] wire out_woready_1_978; // @[RegisterRouter.scala:87:24] wire out_woready_1_979; // @[RegisterRouter.scala:87:24] wire out_woready_1_980; // @[RegisterRouter.scala:87:24] wire out_woready_1_981; // @[RegisterRouter.scala:87:24] wire out_woready_1_982; // @[RegisterRouter.scala:87:24] wire out_woready_1_983; // @[RegisterRouter.scala:87:24] wire out_woready_1_984; // @[RegisterRouter.scala:87:24] wire out_woready_1_985; // @[RegisterRouter.scala:87:24] wire out_woready_1_986; // @[RegisterRouter.scala:87:24] wire out_woready_1_987; // @[RegisterRouter.scala:87:24] wire out_woready_1_988; // @[RegisterRouter.scala:87:24] wire out_woready_1_989; // @[RegisterRouter.scala:87:24] wire out_woready_1_990; // @[RegisterRouter.scala:87:24] wire out_woready_1_991; // @[RegisterRouter.scala:87:24] wire out_woready_1_992; // @[RegisterRouter.scala:87:24] wire out_woready_1_993; // @[RegisterRouter.scala:87:24] wire out_woready_1_994; // @[RegisterRouter.scala:87:24] wire out_woready_1_995; // @[RegisterRouter.scala:87:24] wire out_woready_1_996; // @[RegisterRouter.scala:87:24] wire out_woready_1_997; // @[RegisterRouter.scala:87:24] wire out_woready_1_998; // @[RegisterRouter.scala:87:24] wire out_woready_1_999; // @[RegisterRouter.scala:87:24] wire out_woready_1_1000; // @[RegisterRouter.scala:87:24] wire out_woready_1_1001; // @[RegisterRouter.scala:87:24] wire out_woready_1_1002; // @[RegisterRouter.scala:87:24] wire out_woready_1_1003; // @[RegisterRouter.scala:87:24] wire out_woready_1_1004; // @[RegisterRouter.scala:87:24] wire out_woready_1_1005; // @[RegisterRouter.scala:87:24] wire out_woready_1_1006; // @[RegisterRouter.scala:87:24] wire out_woready_1_1007; // @[RegisterRouter.scala:87:24] wire out_woready_1_1008; // @[RegisterRouter.scala:87:24] wire out_woready_1_1009; // @[RegisterRouter.scala:87:24] wire out_woready_1_1010; // @[RegisterRouter.scala:87:24] wire out_woready_1_1011; // @[RegisterRouter.scala:87:24] wire out_woready_1_1012; // @[RegisterRouter.scala:87:24] wire out_woready_1_1013; // @[RegisterRouter.scala:87:24] wire out_woready_1_1014; // @[RegisterRouter.scala:87:24] wire out_woready_1_1015; // @[RegisterRouter.scala:87:24] wire out_woready_1_1016; // @[RegisterRouter.scala:87:24] wire out_woready_1_1017; // @[RegisterRouter.scala:87:24] wire out_woready_1_1018; // @[RegisterRouter.scala:87:24] wire out_woready_1_1019; // @[RegisterRouter.scala:87:24] wire out_woready_1_1020; // @[RegisterRouter.scala:87:24] wire out_woready_1_1021; // @[RegisterRouter.scala:87:24] wire out_woready_1_1022; // @[RegisterRouter.scala:87:24] wire out_woready_1_1023; // @[RegisterRouter.scala:87:24] wire out_woready_1_1024; // @[RegisterRouter.scala:87:24] wire out_woready_1_1025; // @[RegisterRouter.scala:87:24] wire out_woready_1_1026; // @[RegisterRouter.scala:87:24] wire out_woready_1_1027; // @[RegisterRouter.scala:87:24] wire out_woready_1_1028; // @[RegisterRouter.scala:87:24] wire out_woready_1_1029; // @[RegisterRouter.scala:87:24] wire out_woready_1_1030; // @[RegisterRouter.scala:87:24] wire out_woready_1_1031; // @[RegisterRouter.scala:87:24] wire out_woready_1_1032; // @[RegisterRouter.scala:87:24] wire out_woready_1_1033; // @[RegisterRouter.scala:87:24] wire out_woready_1_1034; // @[RegisterRouter.scala:87:24] wire out_woready_1_1035; // @[RegisterRouter.scala:87:24] wire out_woready_1_1036; // @[RegisterRouter.scala:87:24] wire out_woready_1_1037; // @[RegisterRouter.scala:87:24] wire out_woready_1_1038; // @[RegisterRouter.scala:87:24] wire out_woready_1_1039; // @[RegisterRouter.scala:87:24] wire out_woready_1_1040; // @[RegisterRouter.scala:87:24] wire out_woready_1_1041; // @[RegisterRouter.scala:87:24] wire out_woready_1_1042; // @[RegisterRouter.scala:87:24] wire out_woready_1_1043; // @[RegisterRouter.scala:87:24] wire out_woready_1_1044; // @[RegisterRouter.scala:87:24] wire out_woready_1_1045; // @[RegisterRouter.scala:87:24] wire out_woready_1_1046; // @[RegisterRouter.scala:87:24] wire out_woready_1_1047; // @[RegisterRouter.scala:87:24] wire out_woready_1_1048; // @[RegisterRouter.scala:87:24] wire out_woready_1_1049; // @[RegisterRouter.scala:87:24] wire out_woready_1_1050; // @[RegisterRouter.scala:87:24] wire out_woready_1_1051; // @[RegisterRouter.scala:87:24] wire out_woready_1_1052; // @[RegisterRouter.scala:87:24] wire out_woready_1_1053; // @[RegisterRouter.scala:87:24] wire out_woready_1_1054; // @[RegisterRouter.scala:87:24] wire out_woready_1_1055; // @[RegisterRouter.scala:87:24] wire out_woready_1_1056; // @[RegisterRouter.scala:87:24] wire out_woready_1_1057; // @[RegisterRouter.scala:87:24] wire out_woready_1_1058; // @[RegisterRouter.scala:87:24] wire out_woready_1_1059; // @[RegisterRouter.scala:87:24] wire out_woready_1_1060; // @[RegisterRouter.scala:87:24] wire out_woready_1_1061; // @[RegisterRouter.scala:87:24] wire out_woready_1_1062; // @[RegisterRouter.scala:87:24] wire out_woready_1_1063; // @[RegisterRouter.scala:87:24] wire out_woready_1_1064; // @[RegisterRouter.scala:87:24] wire out_woready_1_1065; // @[RegisterRouter.scala:87:24] wire out_woready_1_1066; // @[RegisterRouter.scala:87:24] wire out_woready_1_1067; // @[RegisterRouter.scala:87:24] wire out_woready_1_1068; // @[RegisterRouter.scala:87:24] wire out_woready_1_1069; // @[RegisterRouter.scala:87:24] wire out_woready_1_1070; // @[RegisterRouter.scala:87:24] wire out_woready_1_1071; // @[RegisterRouter.scala:87:24] wire out_woready_1_1072; // @[RegisterRouter.scala:87:24] wire out_woready_1_1073; // @[RegisterRouter.scala:87:24] wire out_woready_1_1074; // @[RegisterRouter.scala:87:24] wire out_woready_1_1075; // @[RegisterRouter.scala:87:24] wire out_woready_1_1076; // @[RegisterRouter.scala:87:24] wire out_woready_1_1077; // @[RegisterRouter.scala:87:24] wire out_woready_1_1078; // @[RegisterRouter.scala:87:24] wire out_woready_1_1079; // @[RegisterRouter.scala:87:24] wire out_woready_1_1080; // @[RegisterRouter.scala:87:24] wire out_woready_1_1081; // @[RegisterRouter.scala:87:24] wire out_woready_1_1082; // @[RegisterRouter.scala:87:24] wire out_woready_1_1083; // @[RegisterRouter.scala:87:24] wire out_woready_1_1084; // @[RegisterRouter.scala:87:24] wire out_woready_1_1085; // @[RegisterRouter.scala:87:24] wire out_woready_1_1086; // @[RegisterRouter.scala:87:24] wire out_woready_1_1087; // @[RegisterRouter.scala:87:24] wire out_woready_1_1088; // @[RegisterRouter.scala:87:24] wire out_woready_1_1089; // @[RegisterRouter.scala:87:24] wire out_woready_1_1090; // @[RegisterRouter.scala:87:24] wire out_woready_1_1091; // @[RegisterRouter.scala:87:24] wire out_woready_1_1092; // @[RegisterRouter.scala:87:24] wire out_woready_1_1093; // @[RegisterRouter.scala:87:24] wire out_woready_1_1094; // @[RegisterRouter.scala:87:24] wire out_woready_1_1095; // @[RegisterRouter.scala:87:24] wire out_woready_1_1096; // @[RegisterRouter.scala:87:24] wire out_woready_1_1097; // @[RegisterRouter.scala:87:24] wire out_woready_1_1098; // @[RegisterRouter.scala:87:24] wire out_woready_1_1099; // @[RegisterRouter.scala:87:24] wire out_woready_1_1100; // @[RegisterRouter.scala:87:24] wire out_woready_1_1101; // @[RegisterRouter.scala:87:24] wire out_woready_1_1102; // @[RegisterRouter.scala:87:24] wire out_woready_1_1103; // @[RegisterRouter.scala:87:24] wire out_woready_1_1104; // @[RegisterRouter.scala:87:24] wire out_woready_1_1105; // @[RegisterRouter.scala:87:24] wire out_woready_1_1106; // @[RegisterRouter.scala:87:24] wire out_woready_1_1107; // @[RegisterRouter.scala:87:24] wire out_woready_1_1108; // @[RegisterRouter.scala:87:24] wire out_woready_1_1109; // @[RegisterRouter.scala:87:24] wire out_woready_1_1110; // @[RegisterRouter.scala:87:24] wire out_woready_1_1111; // @[RegisterRouter.scala:87:24] wire out_woready_1_1112; // @[RegisterRouter.scala:87:24] wire out_woready_1_1113; // @[RegisterRouter.scala:87:24] wire out_woready_1_1114; // @[RegisterRouter.scala:87:24] wire out_woready_1_1115; // @[RegisterRouter.scala:87:24] wire out_woready_1_1116; // @[RegisterRouter.scala:87:24] wire out_woready_1_1117; // @[RegisterRouter.scala:87:24] wire out_woready_1_1118; // @[RegisterRouter.scala:87:24] wire out_woready_1_1119; // @[RegisterRouter.scala:87:24] wire out_woready_1_1120; // @[RegisterRouter.scala:87:24] wire out_woready_1_1121; // @[RegisterRouter.scala:87:24] wire out_woready_1_1122; // @[RegisterRouter.scala:87:24] wire out_woready_1_1123; // @[RegisterRouter.scala:87:24] wire out_woready_1_1124; // @[RegisterRouter.scala:87:24] wire out_woready_1_1125; // @[RegisterRouter.scala:87:24] wire out_woready_1_1126; // @[RegisterRouter.scala:87:24] wire out_woready_1_1127; // @[RegisterRouter.scala:87:24] wire out_woready_1_1128; // @[RegisterRouter.scala:87:24] wire out_woready_1_1129; // @[RegisterRouter.scala:87:24] wire out_woready_1_1130; // @[RegisterRouter.scala:87:24] wire out_woready_1_1131; // @[RegisterRouter.scala:87:24] wire out_woready_1_1132; // @[RegisterRouter.scala:87:24] wire out_woready_1_1133; // @[RegisterRouter.scala:87:24] wire out_woready_1_1134; // @[RegisterRouter.scala:87:24] wire out_woready_1_1135; // @[RegisterRouter.scala:87:24] wire out_woready_1_1136; // @[RegisterRouter.scala:87:24] wire out_woready_1_1137; // @[RegisterRouter.scala:87:24] wire out_woready_1_1138; // @[RegisterRouter.scala:87:24] wire out_woready_1_1139; // @[RegisterRouter.scala:87:24] wire out_woready_1_1140; // @[RegisterRouter.scala:87:24] wire out_woready_1_1141; // @[RegisterRouter.scala:87:24] wire out_woready_1_1142; // @[RegisterRouter.scala:87:24] wire out_woready_1_1143; // @[RegisterRouter.scala:87:24] wire out_woready_1_1144; // @[RegisterRouter.scala:87:24] wire out_woready_1_1145; // @[RegisterRouter.scala:87:24] wire out_woready_1_1146; // @[RegisterRouter.scala:87:24] wire out_woready_1_1147; // @[RegisterRouter.scala:87:24] wire out_woready_1_1148; // @[RegisterRouter.scala:87:24] wire out_woready_1_1149; // @[RegisterRouter.scala:87:24] wire out_woready_1_1150; // @[RegisterRouter.scala:87:24] wire out_woready_1_1151; // @[RegisterRouter.scala:87:24] wire out_woready_1_1152; // @[RegisterRouter.scala:87:24] wire out_woready_1_1153; // @[RegisterRouter.scala:87:24] wire out_woready_1_1154; // @[RegisterRouter.scala:87:24] wire out_woready_1_1155; // @[RegisterRouter.scala:87:24] wire out_woready_1_1156; // @[RegisterRouter.scala:87:24] wire out_woready_1_1157; // @[RegisterRouter.scala:87:24] wire out_woready_1_1158; // @[RegisterRouter.scala:87:24] wire out_woready_1_1159; // @[RegisterRouter.scala:87:24] wire out_woready_1_1160; // @[RegisterRouter.scala:87:24] wire out_woready_1_1161; // @[RegisterRouter.scala:87:24] wire out_woready_1_1162; // @[RegisterRouter.scala:87:24] wire out_woready_1_1163; // @[RegisterRouter.scala:87:24] wire out_woready_1_1164; // @[RegisterRouter.scala:87:24] wire out_woready_1_1165; // @[RegisterRouter.scala:87:24] wire out_woready_1_1166; // @[RegisterRouter.scala:87:24] wire out_woready_1_1167; // @[RegisterRouter.scala:87:24] wire out_woready_1_1168; // @[RegisterRouter.scala:87:24] wire out_woready_1_1169; // @[RegisterRouter.scala:87:24] wire out_woready_1_1170; // @[RegisterRouter.scala:87:24] wire out_woready_1_1171; // @[RegisterRouter.scala:87:24] wire out_woready_1_1172; // @[RegisterRouter.scala:87:24] wire out_woready_1_1173; // @[RegisterRouter.scala:87:24] wire out_woready_1_1174; // @[RegisterRouter.scala:87:24] wire out_woready_1_1175; // @[RegisterRouter.scala:87:24] wire out_woready_1_1176; // @[RegisterRouter.scala:87:24] wire out_woready_1_1177; // @[RegisterRouter.scala:87:24] wire out_woready_1_1178; // @[RegisterRouter.scala:87:24] wire out_woready_1_1179; // @[RegisterRouter.scala:87:24] wire out_woready_1_1180; // @[RegisterRouter.scala:87:24] wire out_woready_1_1181; // @[RegisterRouter.scala:87:24] wire out_woready_1_1182; // @[RegisterRouter.scala:87:24] wire out_woready_1_1183; // @[RegisterRouter.scala:87:24] wire out_woready_1_1184; // @[RegisterRouter.scala:87:24] wire out_woready_1_1185; // @[RegisterRouter.scala:87:24] wire out_woready_1_1186; // @[RegisterRouter.scala:87:24] wire out_woready_1_1187; // @[RegisterRouter.scala:87:24] wire out_woready_1_1188; // @[RegisterRouter.scala:87:24] wire out_woready_1_1189; // @[RegisterRouter.scala:87:24] wire out_woready_1_1190; // @[RegisterRouter.scala:87:24] wire out_woready_1_1191; // @[RegisterRouter.scala:87:24] wire out_woready_1_1192; // @[RegisterRouter.scala:87:24] wire out_woready_1_1193; // @[RegisterRouter.scala:87:24] wire out_woready_1_1194; // @[RegisterRouter.scala:87:24] wire out_woready_1_1195; // @[RegisterRouter.scala:87:24] wire out_woready_1_1196; // @[RegisterRouter.scala:87:24] wire out_woready_1_1197; // @[RegisterRouter.scala:87:24] wire out_woready_1_1198; // @[RegisterRouter.scala:87:24] wire out_woready_1_1199; // @[RegisterRouter.scala:87:24] wire out_woready_1_1200; // @[RegisterRouter.scala:87:24] wire out_woready_1_1201; // @[RegisterRouter.scala:87:24] wire out_woready_1_1202; // @[RegisterRouter.scala:87:24] wire out_woready_1_1203; // @[RegisterRouter.scala:87:24] wire out_woready_1_1204; // @[RegisterRouter.scala:87:24] wire out_woready_1_1205; // @[RegisterRouter.scala:87:24] wire out_woready_1_1206; // @[RegisterRouter.scala:87:24] wire out_woready_1_1207; // @[RegisterRouter.scala:87:24] wire out_woready_1_1208; // @[RegisterRouter.scala:87:24] wire out_woready_1_1209; // @[RegisterRouter.scala:87:24] wire out_woready_1_1210; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_8 = out_front_1_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_8 = out_front_1_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_9 = out_front_1_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_9 = out_front_1_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_10 = out_front_1_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_10 = out_front_1_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_11 = out_front_1_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_11 = out_front_1_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_12 = out_front_1_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_12 = out_front_1_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_13 = out_front_1_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_13 = out_front_1_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_14 = out_front_1_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_14 = out_front_1_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_15 = out_front_1_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_15 = out_front_1_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_16 = {8{_out_frontMask_T_8}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_17 = {8{_out_frontMask_T_9}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_18 = {8{_out_frontMask_T_10}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_19 = {8{_out_frontMask_T_11}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_20 = {8{_out_frontMask_T_12}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_21 = {8{_out_frontMask_T_13}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_22 = {8{_out_frontMask_T_14}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_23 = {8{_out_frontMask_T_15}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_lo = {_out_frontMask_T_17, _out_frontMask_T_16}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_hi = {_out_frontMask_T_19, _out_frontMask_T_18}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_lo_1 = {out_frontMask_lo_hi, out_frontMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_lo = {_out_frontMask_T_21, _out_frontMask_T_20}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_hi = {_out_frontMask_T_23, _out_frontMask_T_22}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_hi_1 = {out_frontMask_hi_hi, out_frontMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_frontMask_1 = {out_frontMask_hi_1, out_frontMask_lo_1}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_16 = {8{_out_backMask_T_8}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_17 = {8{_out_backMask_T_9}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_18 = {8{_out_backMask_T_10}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_19 = {8{_out_backMask_T_11}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_20 = {8{_out_backMask_T_12}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_21 = {8{_out_backMask_T_13}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_22 = {8{_out_backMask_T_14}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_23 = {8{_out_backMask_T_15}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_lo = {_out_backMask_T_17, _out_backMask_T_16}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_hi = {_out_backMask_T_19, _out_backMask_T_18}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_lo_1 = {out_backMask_lo_hi, out_backMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_lo = {_out_backMask_T_21, _out_backMask_T_20}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_hi = {_out_backMask_T_23, _out_backMask_T_22}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_hi_1 = {out_backMask_hi_hi, out_backMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_backMask_1 = {out_backMask_hi_1, out_backMask_lo_1}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_146 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_146 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_154 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_154 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_162 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_162 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_170 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_170 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_178 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_178 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_186 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_186 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_194 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_194 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_202 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_202 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_210 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_210 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_218 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_218 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_226 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_226 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_234 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_234 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_242 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_242 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_250 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_250 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_258 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_258 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_266 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_266 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_274 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_274 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_282 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_282 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_290 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_290 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_298 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_298 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_306 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_306 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_314 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_314 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_322 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_322 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_330 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_330 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_338 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_338 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_346 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_346 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_354 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_354 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_362 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_362 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_370 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_370 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_378 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_378 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_386 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_386 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_394 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_394 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_402 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_402 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_410 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_410 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_418 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_418 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_426 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_426 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_434 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_434 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_442 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_442 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_450 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_450 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_458 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_458 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_466 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_466 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_474 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_474 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_482 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_482 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_490 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_490 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_500 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_500 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_508 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_508 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_516 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_516 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_524 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_524 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_532 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_532 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_540 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_540 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_548 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_548 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_556 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_556 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_564 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_564 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_572 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_572 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_580 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_580 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_589 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_589 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_597 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_597 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_605 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_605 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_613 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_613 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_621 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_621 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_629 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_629 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_633 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_633 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_641 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_641 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_649 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_649 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_657 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_657 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_665 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_665 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_673 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_673 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_683 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_683 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_691 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_691 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_699 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_699 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_707 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_707 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_715 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_715 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_723 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_723 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_731 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_731 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_739 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_739 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_747 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_747 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_755 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_755 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_763 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_763 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_771 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_771 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_779 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_779 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_787 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_787 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_795 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_795 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_803 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_803 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_811 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_811 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_819 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_819 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_827 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_827 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_835 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_835 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_845 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_845 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_853 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_853 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_861 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_861 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_869 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_869 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_877 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_877 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_885 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_885 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_893 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_893 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_901 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_901 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_909 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_909 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_917 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_917 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_925 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_925 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_933 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_933 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_941 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_941 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_949 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_949 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_957 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_957 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_965 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_965 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_973 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_973 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_981 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_981 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_989 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_989 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_997 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_997 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1005 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1005 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1013 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1013 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1021 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1021 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1029 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1029 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1037 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1037 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1045 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1045 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1053 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1053 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1061 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1061 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1069 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1069 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1077 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1077 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1085 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1085 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1093 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1093 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1101 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1101 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1109 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1109 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1117 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1117 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1125 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1125 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1133 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1133 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1141 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1141 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1149 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1149 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1157 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1157 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1165 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1165 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1173 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1173 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1181 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1181 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1189 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1189 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1197 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1197 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1205 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1205 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1213 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1213 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1221 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1221 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1229 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1229 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1237 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1237 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1245 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1245 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1253 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1253 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1261 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1261 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1269 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1269 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1277 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1277 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1285 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1285 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1293 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1293 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1301 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1301 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1309 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1309 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1317 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1317 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1325 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1325 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1333 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1333 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1341 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1341 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1349 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1349 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire out_rimask_146 = \|_out_rimask_T_146; // @[RegisterRouter.scala:87:24] wire out_wimask_146 = &_out_wimask_T_146; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_146 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_146 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_154 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_154 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_162 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_162 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_170 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_170 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_178 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_178 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_186 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_186 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_194 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_194 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_202 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_202 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_210 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_210 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_218 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_218 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_226 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_226 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_234 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_234 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_242 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_242 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_250 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_250 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_258 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_258 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_266 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_266 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_274 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_274 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_282 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_282 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_290 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_290 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_298 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_298 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_306 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_306 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_314 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_314 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_322 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_322 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_330 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_330 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_338 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_338 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_346 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_346 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_354 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_354 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_362 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_362 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_370 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_370 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_378 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_378 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_386 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_386 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_394 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_394 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_402 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_402 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_410 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_410 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_418 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_418 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_426 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_426 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_434 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_434 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_442 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_442 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_450 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_450 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_458 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_458 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_466 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_466 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_474 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_474 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_482 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_482 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_490 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_490 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_500 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_500 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_508 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_508 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_516 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_516 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_524 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_524 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_532 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_532 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_540 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_540 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_548 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_548 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_556 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_556 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_564 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_564 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_572 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_572 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_580 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_580 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_589 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_589 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_597 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_597 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_605 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_605 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_613 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_613 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_621 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_621 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_629 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_629 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_633 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_633 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_641 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_641 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_649 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_649 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_657 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_657 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_665 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_665 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_673 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_673 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_683 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_683 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_691 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_691 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_699 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_699 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_707 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_707 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_715 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_715 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_723 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_723 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_731 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_731 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_739 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_739 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_747 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_747 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_755 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_755 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_763 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_763 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_771 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_771 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_779 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_779 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_787 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_787 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_795 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_795 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_803 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_803 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_811 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_811 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_819 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_819 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_827 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_827 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_835 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_835 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_845 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_845 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_853 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_853 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_861 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_861 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_869 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_869 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_877 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_877 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_885 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_885 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_893 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_893 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_901 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_901 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_909 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_909 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_917 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_917 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_925 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_925 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_933 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_933 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_941 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_941 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_949 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_949 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_957 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_957 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_965 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_965 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_973 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_973 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_981 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_981 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_989 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_989 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_997 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_997 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1005 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1005 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1013 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1013 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1021 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1021 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1029 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1029 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1037 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1037 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1045 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1045 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1053 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1053 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1061 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1061 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1069 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1069 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1077 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1077 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1085 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1085 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1093 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1093 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1101 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1101 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1109 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1109 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1117 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1117 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1125 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1125 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1133 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1133 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1141 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1141 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1149 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1149 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1157 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1157 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1165 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1165 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1173 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1173 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1181 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1181 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1189 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1189 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1197 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1197 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1205 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1205 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1213 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1213 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1221 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1221 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1229 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1229 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1237 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1237 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1245 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1245 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1253 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1253 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1261 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1261 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1269 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1269 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1277 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1277 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1285 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1285 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1293 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1293 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1301 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1301 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1309 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1309 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1317 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1317 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1325 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1325 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1333 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1333 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1341 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1341 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1349 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1349 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire out_romask_146 = \|_out_romask_T_146; // @[RegisterRouter.scala:87:24] wire out_womask_146 = &_out_womask_T_146; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_146 = out_rivalid_1_0 & out_rimask_146; // @[RegisterRouter.scala:87:24] wire _out_T_1911 = out_f_rivalid_146; // @[RegisterRouter.scala:87:24] wire out_f_roready_146 = out_roready_1_0 & out_romask_146; // @[RegisterRouter.scala:87:24] wire _out_T_1912 = out_f_roready_146; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_146 = out_wivalid_1_0 & out_wimask_146; // @[RegisterRouter.scala:87:24] wire out_f_woready_146 = out_woready_1_0 & out_womask_146; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1910 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1982 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2054 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2126 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2198 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2286 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2358 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2430 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2502 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2574 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2646 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2718 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2790 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2862 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2934 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3022 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3094 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3166 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3238 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3310 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3382 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3454 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3526 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3598 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3670 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3758 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3830 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3902 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3974 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4046 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4118 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4190 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4262 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4334 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4406 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4478 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4550 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4622 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4694 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4766 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4838 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4910 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4982 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5054 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5144 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5216 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5288 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5360 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5432 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5504 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5576 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5648 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5720 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5792 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5864 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5945 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6033 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6105 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6177 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6249 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6321 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6357 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6429 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6501 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6573 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6661 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6733 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6823 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6895 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6967 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7039 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7111 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7183 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7255 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7327 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7399 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7471 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7543 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7615 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7687 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7759 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7831 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7903 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7991 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8063 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8135 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8207 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8297 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8369 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8441 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8513 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8585 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8673 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8745 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8817 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8889 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8961 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9033 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9105 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9177 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9249 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9321 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9393 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9465 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9553 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9625 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9697 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9769 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9841 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9913 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9985 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10057 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10129 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10201 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10273 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10345 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10417 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10505 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10577 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10649 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10721 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10793 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10865 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10953 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11025 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11097 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11169 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11241 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11313 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11385 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11457 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11529 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11601 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11673 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11745 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11817 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11889 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11977 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12049 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12121 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12193 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12265 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12337 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12409 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12481 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12553 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12641 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12713 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12785 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12857 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12929 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire _out_T_1913 = ~out_rimask_146; // @[RegisterRouter.scala:87:24] wire _out_T_1914 = ~out_wimask_146; // @[RegisterRouter.scala:87:24] wire _out_T_1915 = ~out_romask_146; // @[RegisterRouter.scala:87:24] wire _out_T_1916 = ~out_womask_146; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1918 = _out_T_1917; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_112 = _out_T_1918; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_147 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_147 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_155 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_155 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_163 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_163 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_171 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_171 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_179 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_179 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_187 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_187 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_195 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_195 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_203 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_203 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_211 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_211 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_219 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_219 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_227 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_227 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_235 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_235 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_243 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_243 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_251 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_251 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_259 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_259 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_267 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_267 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_275 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_275 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_283 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_283 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_291 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_291 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_299 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_299 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_307 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_307 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_315 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_315 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_323 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_323 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_331 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_331 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_339 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_339 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_347 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_347 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_355 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_355 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_363 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_363 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_371 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_371 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_379 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_379 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_387 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_387 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_395 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_395 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_403 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_403 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_411 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_411 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_419 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_419 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_427 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_427 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_435 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_435 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_443 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_443 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_451 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_451 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_459 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_459 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_467 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_467 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_475 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_475 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_483 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_483 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_491 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_491 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_501 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_501 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_509 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_509 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_517 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_517 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_525 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_525 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_533 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_533 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_541 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_541 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_549 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_549 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_557 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_557 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_565 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_565 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_573 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_573 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_581 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_581 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_590 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_590 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_598 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_598 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_606 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_606 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_614 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_614 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_622 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_622 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_630 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_630 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_634 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_634 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_642 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_642 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_650 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_650 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_658 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_658 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_666 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_666 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_674 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_674 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_684 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_684 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_692 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_692 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_700 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_700 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_708 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_708 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_716 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_716 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_724 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_724 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_732 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_732 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_740 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_740 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_748 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_748 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_756 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_756 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_764 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_764 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_772 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_772 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_780 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_780 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_788 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_788 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_796 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_796 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_804 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_804 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_812 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_812 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_820 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_820 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_828 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_828 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_836 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_836 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_846 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_846 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_854 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_854 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_862 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_862 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_870 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_870 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_878 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_878 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_886 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_886 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_894 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_894 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_902 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_902 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_910 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_910 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_918 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_918 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_926 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_926 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_934 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_934 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_942 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_942 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_950 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_950 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_958 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_958 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_966 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_966 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_974 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_974 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_982 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_982 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_990 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_990 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_998 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_998 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1006 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1006 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1014 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1014 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1022 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1022 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1030 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1030 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1038 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1038 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1046 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1046 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1054 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1054 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1062 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1062 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1070 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1070 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1078 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1078 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1086 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1086 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1094 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1094 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1102 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1102 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1110 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1110 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1118 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1118 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1126 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1126 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1134 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1134 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1142 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1142 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1150 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1150 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1158 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1158 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1166 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1166 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1174 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1174 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1182 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1182 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1190 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1190 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1198 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1198 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1206 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1206 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1214 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1214 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1222 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1222 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1230 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1230 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1238 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1238 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1246 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1246 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1254 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1254 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1262 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1262 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1270 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1270 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1278 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1278 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1286 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1286 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1294 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1294 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1302 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1302 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1310 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1310 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1318 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1318 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1326 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1326 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1334 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1334 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1342 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1342 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1350 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1350 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire out_rimask_147 = \|_out_rimask_T_147; // @[RegisterRouter.scala:87:24] wire out_wimask_147 = &_out_wimask_T_147; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_147 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_147 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_155 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_155 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_163 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_163 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_171 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_171 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_179 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_179 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_187 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_187 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_195 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_195 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_203 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_203 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_211 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_211 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_219 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_219 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_227 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_227 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_235 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_235 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_243 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_243 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_251 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_251 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_259 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_259 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_267 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_267 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_275 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_275 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_283 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_283 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_291 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_291 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_299 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_299 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_307 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_307 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_315 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_315 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_323 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_323 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_331 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_331 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_339 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_339 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_347 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_347 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_355 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_355 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_363 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_363 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_371 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_371 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_379 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_379 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_387 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_387 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_395 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_395 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_403 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_403 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_411 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_411 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_419 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_419 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_427 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_427 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_435 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_435 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_443 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_443 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_451 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_451 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_459 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_459 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_467 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_467 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_475 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_475 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_483 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_483 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_491 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_491 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_501 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_501 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_509 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_509 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_517 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_517 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_525 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_525 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_533 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_533 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_541 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_541 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_549 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_549 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_557 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_557 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_565 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_565 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_573 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_573 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_581 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_581 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_590 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_590 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_598 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_598 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_606 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_606 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_614 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_614 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_622 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_622 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_630 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_630 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_634 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_634 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_642 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_642 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_650 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_650 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_658 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_658 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_666 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_666 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_674 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_674 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_684 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_684 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_692 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_692 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_700 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_700 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_708 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_708 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_716 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_716 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_724 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_724 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_732 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_732 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_740 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_740 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_748 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_748 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_756 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_756 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_764 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_764 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_772 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_772 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_780 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_780 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_788 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_788 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_796 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_796 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_804 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_804 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_812 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_812 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_820 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_820 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_828 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_828 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_836 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_836 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_846 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_846 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_854 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_854 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_862 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_862 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_870 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_870 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_878 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_878 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_886 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_886 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_894 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_894 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_902 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_902 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_910 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_910 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_918 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_918 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_926 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_926 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_934 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_934 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_942 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_942 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_950 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_950 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_958 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_958 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_966 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_966 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_974 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_974 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_982 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_982 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_990 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_990 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_998 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_998 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1006 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1006 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1014 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1014 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1022 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1022 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1030 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1030 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1038 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1038 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1046 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1046 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1054 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1054 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1062 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1062 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1070 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1070 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1078 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1078 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1086 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1086 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1094 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1094 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1102 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1102 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1110 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1110 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1118 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1118 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1126 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1126 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1134 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1134 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1142 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1142 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1150 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1150 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1158 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1158 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1166 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1166 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1174 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1174 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1182 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1182 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1190 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1190 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1198 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1198 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1206 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1206 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1214 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1214 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1222 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1222 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1230 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1230 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1238 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1238 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1246 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1246 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1254 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1254 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1262 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1262 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1270 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1270 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1278 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1278 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1286 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1286 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1294 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1294 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1302 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1302 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1310 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1310 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1318 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1318 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1326 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1326 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1334 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1334 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1342 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1342 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1350 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1350 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire out_romask_147 = \|_out_romask_T_147; // @[RegisterRouter.scala:87:24] wire out_womask_147 = &_out_womask_T_147; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_147 = out_rivalid_1_1 & out_rimask_147; // @[RegisterRouter.scala:87:24] wire _out_T_1920 = out_f_rivalid_147; // @[RegisterRouter.scala:87:24] wire out_f_roready_147 = out_roready_1_1 & out_romask_147; // @[RegisterRouter.scala:87:24] wire _out_T_1921 = out_f_roready_147; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_147 = out_wivalid_1_1 & out_wimask_147; // @[RegisterRouter.scala:87:24] wire out_f_woready_147 = out_woready_1_1 & out_womask_147; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1919 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1991 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2063 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2135 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2209 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2295 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2367 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2439 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2511 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2583 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2655 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2727 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2799 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2871 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2945 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3031 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3103 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3175 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3247 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3319 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3391 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3463 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3535 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3607 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3681 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3767 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3839 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3911 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3983 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4055 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4127 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4199 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4271 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4343 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4415 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4487 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4559 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4631 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4703 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4775 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4847 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4919 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4991 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5063 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5153 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5225 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5297 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5369 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5441 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5513 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5585 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5657 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5729 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5801 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5873 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5956 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6042 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6114 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6186 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6258 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6330 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6366 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6438 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6510 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6584 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6670 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6742 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6832 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6904 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6976 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7048 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7120 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7192 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7264 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7336 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7408 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7480 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7552 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7624 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7696 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7768 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7840 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7914 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8000 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8072 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8144 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8216 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8306 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8378 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8450 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8522 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8596 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8682 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8754 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8826 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8898 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8970 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9042 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9114 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9186 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9258 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9330 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9402 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9476 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9562 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9634 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9706 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9778 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9850 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9922 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9994 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10066 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10138 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10210 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10282 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10354 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10428 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10514 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10586 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10658 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10730 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10802 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10876 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10962 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11034 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11106 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11178 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11250 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11322 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11394 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11466 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11538 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11610 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11682 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11754 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11826 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11900 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11986 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12058 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12130 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12202 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12274 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12346 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12418 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12490 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12564 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12650 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12722 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12794 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12866 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12938 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire _out_T_1922 = ~out_rimask_147; // @[RegisterRouter.scala:87:24] wire _out_T_1923 = ~out_wimask_147; // @[RegisterRouter.scala:87:24] wire _out_T_1924 = ~out_romask_147; // @[RegisterRouter.scala:87:24] wire _out_T_1925 = ~out_womask_147; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_112 = {hi_82, flags_0_go, _out_prepend_T_112}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1926 = out_prepend_112; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1927 = _out_T_1926; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_113 = _out_T_1927; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_148 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_148 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_156 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_156 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_164 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_164 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_172 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_172 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_180 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_180 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_188 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_188 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_196 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_196 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_204 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_204 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_212 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_212 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_220 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_220 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_228 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_228 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_236 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_236 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_244 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_244 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_252 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_252 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_260 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_260 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_268 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_268 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_276 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_276 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_284 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_284 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_292 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_292 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_300 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_300 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_308 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_308 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_316 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_316 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_324 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_324 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_332 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_332 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_340 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_340 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_348 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_348 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_356 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_356 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_364 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_364 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_372 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_372 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_380 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_380 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_388 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_388 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_396 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_396 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_404 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_404 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_412 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_412 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_420 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_420 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_428 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_428 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_436 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_436 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_444 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_444 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_452 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_452 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_460 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_460 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_468 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_468 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_476 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_476 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_484 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_484 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_492 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_492 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_502 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_502 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_510 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_510 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_518 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_518 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_526 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_526 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_534 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_534 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_542 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_542 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_550 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_550 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_558 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_558 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_566 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_566 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_574 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_574 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_582 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_582 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_591 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_591 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_599 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_599 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_607 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_607 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_615 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_615 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_623 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_623 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_631 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_631 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_635 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_635 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_643 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_643 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_651 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_651 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_659 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_659 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_667 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_667 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_675 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_675 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_685 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_685 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_693 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_693 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_701 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_701 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_709 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_709 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_717 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_717 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_725 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_725 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_733 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_733 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_741 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_741 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_749 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_749 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_757 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_757 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_765 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_765 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_773 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_773 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_781 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_781 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_789 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_789 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_797 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_797 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_805 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_805 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_813 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_813 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_821 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_821 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_829 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_829 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_837 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_837 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_847 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_847 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_855 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_855 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_863 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_863 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_871 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_871 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_879 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_879 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_887 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_887 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_895 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_895 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_903 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_903 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_911 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_911 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_919 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_919 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_927 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_927 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_935 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_935 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_943 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_943 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_951 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_951 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_959 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_959 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_967 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_967 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_975 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_975 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_983 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_983 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_991 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_991 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_999 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_999 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1007 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1007 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1015 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1015 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1023 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1023 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1031 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1031 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1039 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1039 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1047 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1047 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1055 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1055 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1063 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1063 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1071 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1071 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1079 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1079 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1087 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1087 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1095 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1095 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1103 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1103 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1111 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1111 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1119 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1119 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1127 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1127 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1135 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1135 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1143 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1143 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1151 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1151 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1159 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1159 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1167 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1167 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1175 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1175 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1183 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1183 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1191 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1191 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1199 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1199 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1207 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1207 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1215 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1215 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1223 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1223 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1231 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1231 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1239 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1239 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1247 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1247 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1255 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1255 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1263 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1263 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1271 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1271 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1279 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1279 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1287 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1287 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1295 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1295 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1303 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1303 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1311 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1311 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1319 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1319 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1327 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1327 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1335 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1335 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1343 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1343 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1351 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1351 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire out_rimask_148 = \|_out_rimask_T_148; // @[RegisterRouter.scala:87:24] wire out_wimask_148 = &_out_wimask_T_148; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_148 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_148 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_156 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_156 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_164 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_164 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_172 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_172 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_180 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_180 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_188 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_188 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_196 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_196 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_204 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_204 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_212 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_212 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_220 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_220 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_228 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_228 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_236 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_236 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_244 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_244 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_252 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_252 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_260 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_260 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_268 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_268 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_276 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_276 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_284 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_284 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_292 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_292 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_300 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_300 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_308 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_308 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_316 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_316 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_324 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_324 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_332 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_332 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_340 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_340 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_348 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_348 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_356 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_356 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_364 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_364 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_372 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_372 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_380 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_380 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_388 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_388 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_396 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_396 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_404 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_404 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_412 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_412 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_420 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_420 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_428 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_428 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_436 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_436 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_444 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_444 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_452 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_452 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_460 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_460 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_468 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_468 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_476 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_476 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_484 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_484 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_492 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_492 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_502 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_502 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_510 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_510 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_518 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_518 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_526 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_526 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_534 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_534 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_542 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_542 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_550 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_550 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_558 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_558 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_566 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_566 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_574 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_574 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_582 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_582 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_591 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_591 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_599 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_599 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_607 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_607 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_615 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_615 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_623 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_623 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_631 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_631 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_635 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_635 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_643 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_643 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_651 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_651 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_659 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_659 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_667 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_667 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_675 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_675 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_685 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_685 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_693 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_693 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_701 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_701 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_709 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_709 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_717 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_717 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_725 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_725 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_733 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_733 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_741 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_741 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_749 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_749 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_757 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_757 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_765 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_765 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_773 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_773 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_781 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_781 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_789 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_789 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_797 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_797 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_805 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_805 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_813 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_813 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_821 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_821 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_829 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_829 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_837 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_837 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_847 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_847 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_855 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_855 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_863 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_863 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_871 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_871 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_879 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_879 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_887 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_887 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_895 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_895 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_903 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_903 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_911 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_911 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_919 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_919 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_927 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_927 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_935 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_935 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_943 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_943 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_951 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_951 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_959 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_959 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_967 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_967 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_975 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_975 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_983 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_983 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_991 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_991 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_999 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_999 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1007 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1007 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1015 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1015 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1023 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1023 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1031 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1031 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1039 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1039 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1047 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1047 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1055 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1055 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1063 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1063 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1071 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1071 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1079 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1079 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1087 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1087 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1095 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1095 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1103 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1103 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1111 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1111 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1119 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1119 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1127 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1127 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1135 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1135 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1143 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1143 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1151 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1151 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1159 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1159 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1167 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1167 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1175 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1175 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1183 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1183 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1191 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1191 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1199 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1199 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1207 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1207 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1215 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1215 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1223 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1223 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1231 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1231 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1239 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1239 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1247 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1247 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1255 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1255 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1263 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1263 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1271 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1271 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1279 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1279 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1287 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1287 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1295 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1295 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1303 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1303 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1311 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1311 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1319 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1319 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1327 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1327 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1335 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1335 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1343 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1343 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1351 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1351 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire out_romask_148 = \|_out_romask_T_148; // @[RegisterRouter.scala:87:24] wire out_womask_148 = &_out_womask_T_148; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_148 = out_rivalid_1_2 & out_rimask_148; // @[RegisterRouter.scala:87:24] wire _out_T_1929 = out_f_rivalid_148; // @[RegisterRouter.scala:87:24] wire out_f_roready_148 = out_roready_1_2 & out_romask_148; // @[RegisterRouter.scala:87:24] wire _out_T_1930 = out_f_roready_148; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_148 = out_wivalid_1_2 & out_wimask_148; // @[RegisterRouter.scala:87:24] wire out_f_woready_148 = out_woready_1_2 & out_womask_148; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1928 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2000 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2072 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2144 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2220 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2304 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2376 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2448 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2520 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2592 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2664 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2736 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2808 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2880 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2956 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3040 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3112 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3184 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3256 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3328 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3400 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3472 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3544 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3616 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3692 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3776 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3848 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3920 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3992 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4064 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4136 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4208 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4280 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4352 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4424 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4496 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4568 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4640 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4712 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4784 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4856 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4928 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5000 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5072 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5162 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5234 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5306 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5378 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5450 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5522 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5594 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5666 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5738 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5810 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5882 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5967 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6051 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6123 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6195 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6267 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6339 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6375 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6447 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6519 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6595 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6679 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6751 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6841 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6913 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6985 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7057 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7129 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7201 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7273 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7345 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7417 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7489 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7561 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7633 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7705 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7777 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7849 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7925 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8009 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8081 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8153 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8225 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8315 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8387 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8459 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8531 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8607 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8691 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8763 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8835 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8907 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8979 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9051 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9123 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9195 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9267 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9339 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9411 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9487 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9571 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9643 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9715 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9787 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9859 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9931 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10003 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10075 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10147 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10219 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10291 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10363 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10439 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10523 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10595 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10667 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10739 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10811 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10887 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10971 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11043 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11115 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11187 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11259 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11331 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11403 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11475 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11547 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11619 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11691 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11763 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11835 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11911 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11995 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12067 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12139 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12211 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12283 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12355 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12427 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12499 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12575 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12659 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12731 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12803 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12875 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12947 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire _out_T_1931 = ~out_rimask_148; // @[RegisterRouter.scala:87:24] wire _out_T_1932 = ~out_wimask_148; // @[RegisterRouter.scala:87:24] wire _out_T_1933 = ~out_romask_148; // @[RegisterRouter.scala:87:24] wire _out_T_1934 = ~out_womask_148; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_113 = {hi_83, flags_0_go, _out_prepend_T_113}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1935 = out_prepend_113; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1936 = _out_T_1935; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_114 = _out_T_1936; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_149 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_149 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_157 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_157 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_165 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_165 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_173 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_173 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_181 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_181 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_189 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_189 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_197 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_197 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_205 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_205 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_213 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_213 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_221 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_221 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_229 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_229 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_237 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_237 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_245 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_245 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_253 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_253 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_261 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_261 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_269 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_269 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_277 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_277 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_285 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_285 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_293 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_293 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_301 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_301 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_309 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_309 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_317 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_317 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_325 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_325 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_333 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_333 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_341 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_341 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_349 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_349 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_357 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_357 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_365 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_365 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_373 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_373 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_381 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_381 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_389 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_389 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_397 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_397 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_405 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_405 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_413 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_413 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_421 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_421 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_429 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_429 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_437 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_437 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_445 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_445 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_453 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_453 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_461 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_461 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_469 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_469 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_477 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_477 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_485 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_485 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_493 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_493 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_503 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_503 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_511 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_511 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_519 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_519 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_527 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_527 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_535 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_535 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_543 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_543 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_551 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_551 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_559 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_559 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_567 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_567 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_575 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_575 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_583 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_583 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_592 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_592 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_600 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_600 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_608 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_608 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_616 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_616 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_624 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_624 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_632 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_632 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_636 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_636 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_644 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_644 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_652 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_652 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_660 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_660 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_668 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_668 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_676 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_676 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_686 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_686 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_694 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_694 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_702 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_702 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_710 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_710 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_718 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_718 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_726 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_726 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_734 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_734 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_742 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_742 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_750 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_750 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_758 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_758 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_766 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_766 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_774 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_774 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_782 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_782 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_790 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_790 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_798 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_798 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_806 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_806 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_814 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_814 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_822 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_822 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_830 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_830 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_838 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_838 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_848 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_848 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_856 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_856 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_864 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_864 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_872 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_872 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_880 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_880 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_888 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_888 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_896 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_896 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_904 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_904 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_912 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_912 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_920 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_920 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_928 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_928 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_936 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_936 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_944 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_944 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_952 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_952 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_960 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_960 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_968 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_968 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_976 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_976 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_984 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_984 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_992 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_992 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1000 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1000 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1008 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1008 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1016 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1016 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1024 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1024 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1032 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1032 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1040 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1040 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1048 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1048 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1056 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1056 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1064 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1064 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1072 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1072 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1080 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1080 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1088 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1088 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1096 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1096 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1104 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1104 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1112 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1112 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1120 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1120 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1128 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1128 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1136 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1136 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1144 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1144 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1152 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1152 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1160 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1160 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1168 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1168 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1176 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1176 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1184 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1184 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1192 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1192 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1200 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1200 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1208 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1208 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1216 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1216 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1224 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1224 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1232 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1232 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1240 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1240 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1248 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1248 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1256 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1256 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1264 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1264 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1272 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1272 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1280 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1280 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1288 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1288 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1296 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1296 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1304 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1304 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1312 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1312 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1320 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1320 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1328 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1328 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1336 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1336 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1344 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1344 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1352 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1352 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire out_rimask_149 = \|_out_rimask_T_149; // @[RegisterRouter.scala:87:24] wire out_wimask_149 = &_out_wimask_T_149; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_149 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_149 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_157 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_157 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_165 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_165 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_173 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_173 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_181 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_181 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_189 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_189 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_197 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_197 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_205 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_205 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_213 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_213 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_221 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_221 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_229 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_229 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_237 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_237 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_245 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_245 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_253 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_253 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_261 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_261 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_269 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_269 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_277 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_277 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_285 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_285 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_293 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_293 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_301 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_301 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_309 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_309 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_317 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_317 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_325 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_325 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_333 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_333 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_341 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_341 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_349 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_349 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_357 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_357 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_365 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_365 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_373 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_373 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_381 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_381 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_389 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_389 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_397 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_397 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_405 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_405 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_413 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_413 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_421 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_421 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_429 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_429 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_437 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_437 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_445 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_445 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_453 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_453 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_461 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_461 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_469 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_469 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_477 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_477 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_485 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_485 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_493 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_493 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_503 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_503 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_511 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_511 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_519 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_519 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_527 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_527 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_535 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_535 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_543 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_543 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_551 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_551 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_559 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_559 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_567 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_567 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_575 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_575 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_583 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_583 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_592 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_592 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_600 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_600 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_608 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_608 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_616 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_616 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_624 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_624 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_632 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_632 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_636 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_636 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_644 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_644 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_652 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_652 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_660 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_660 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_668 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_668 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_676 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_676 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_686 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_686 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_694 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_694 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_702 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_702 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_710 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_710 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_718 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_718 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_726 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_726 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_734 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_734 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_742 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_742 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_750 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_750 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_758 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_758 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_766 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_766 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_774 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_774 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_782 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_782 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_790 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_790 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_798 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_798 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_806 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_806 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_814 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_814 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_822 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_822 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_830 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_830 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_838 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_838 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_848 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_848 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_856 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_856 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_864 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_864 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_872 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_872 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_880 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_880 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_888 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_888 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_896 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_896 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_904 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_904 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_912 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_912 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_920 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_920 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_928 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_928 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_936 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_936 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_944 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_944 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_952 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_952 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_960 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_960 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_968 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_968 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_976 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_976 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_984 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_984 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_992 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_992 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1000 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1000 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1008 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1008 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1016 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1016 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1024 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1024 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1032 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1032 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1040 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1040 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1048 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1048 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1056 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1056 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1064 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1064 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1072 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1072 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1080 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1080 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1088 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1088 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1096 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1096 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1104 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1104 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1112 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1112 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1120 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1120 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1128 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1128 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1136 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1136 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1144 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1144 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1152 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1152 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1160 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1160 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1168 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1168 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1176 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1176 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1184 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1184 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1192 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1192 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1200 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1200 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1208 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1208 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1216 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1216 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1224 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1224 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1232 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1232 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1240 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1240 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1248 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1248 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1256 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1256 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1264 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1264 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1272 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1272 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1280 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1280 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1288 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1288 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1296 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1296 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1304 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1304 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1312 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1312 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1320 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1320 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1328 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1328 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1336 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1336 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1344 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1344 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1352 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1352 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire out_romask_149 = \|_out_romask_T_149; // @[RegisterRouter.scala:87:24] wire out_womask_149 = &_out_womask_T_149; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_149 = out_rivalid_1_3 & out_rimask_149; // @[RegisterRouter.scala:87:24] wire _out_T_1938 = out_f_rivalid_149; // @[RegisterRouter.scala:87:24] wire out_f_roready_149 = out_roready_1_3 & out_romask_149; // @[RegisterRouter.scala:87:24] wire _out_T_1939 = out_f_roready_149; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_149 = out_wivalid_1_3 & out_wimask_149; // @[RegisterRouter.scala:87:24] wire out_f_woready_149 = out_woready_1_3 & out_womask_149; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1937 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2009 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2081 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2153 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2231 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2313 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2385 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2457 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2529 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2601 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2673 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2745 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2817 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2889 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2967 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3049 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3121 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3193 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3265 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3337 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3409 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3481 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3553 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3625 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3703 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3785 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3857 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3929 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4001 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4073 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4145 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4217 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4289 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4361 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4433 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4505 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4577 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4649 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4721 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4793 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4865 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4937 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5009 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5081 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5171 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5243 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5315 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5387 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5459 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5531 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5603 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5675 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5747 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5819 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5891 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5978 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6060 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6132 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6204 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6276 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6348 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6384 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6456 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6528 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6606 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6688 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6760 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6850 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6922 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6994 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7066 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7138 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7210 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7282 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7354 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7426 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7498 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7570 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7642 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7714 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7786 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7858 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7936 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8018 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8090 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8162 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8234 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8324 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8396 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8468 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8540 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8618 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8700 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8772 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8844 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8916 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8988 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9060 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9132 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9204 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9276 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9348 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9420 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9498 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9580 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9652 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9724 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9796 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9868 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9940 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10012 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10084 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10156 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10228 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10300 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10372 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10450 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10532 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10604 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10676 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10748 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10820 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10898 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10980 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11052 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11124 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11196 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11268 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11340 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11412 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11484 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11556 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11628 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11700 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11772 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11844 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11922 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12004 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12076 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12148 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12220 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12292 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12364 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12436 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12508 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12586 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12668 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12740 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12812 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12884 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12956 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire _out_T_1940 = ~out_rimask_149; // @[RegisterRouter.scala:87:24] wire _out_T_1941 = ~out_wimask_149; // @[RegisterRouter.scala:87:24] wire _out_T_1942 = ~out_romask_149; // @[RegisterRouter.scala:87:24] wire _out_T_1943 = ~out_womask_149; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_114 = {hi_84, flags_0_go, _out_prepend_T_114}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1944 = out_prepend_114; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1945 = _out_T_1944; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_115 = _out_T_1945; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_150 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_150 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_158 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_158 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_166 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_166 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_174 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_174 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_182 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_182 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_190 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_190 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_198 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_198 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_206 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_206 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_214 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_214 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_222 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_222 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_230 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_230 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_238 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_238 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_246 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_246 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_254 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_254 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_262 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_262 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_270 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_270 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_278 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_278 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_286 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_286 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_294 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_294 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_302 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_302 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_310 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_310 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_318 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_318 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_326 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_326 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_334 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_334 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_342 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_342 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_350 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_350 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_358 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_358 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_366 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_366 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_374 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_374 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_382 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_382 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_390 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_390 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_398 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_398 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_406 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_406 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_414 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_414 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_422 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_422 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_430 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_430 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_438 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_438 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_446 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_446 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_454 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_454 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_462 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_462 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_470 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_470 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_478 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_478 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_486 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_486 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_494 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_494 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_504 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_504 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_512 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_512 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_520 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_520 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_528 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_528 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_536 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_536 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_544 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_544 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_552 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_552 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_560 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_560 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_568 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_568 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_576 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_576 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_584 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_584 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_593 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_593 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_601 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_601 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_609 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_609 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_617 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_617 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_625 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_625 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_637 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_637 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_645 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_645 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_653 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_653 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_661 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_661 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_669 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_669 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_677 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_677 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_687 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_687 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_695 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_695 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_703 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_703 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_711 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_711 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_719 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_719 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_727 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_727 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_735 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_735 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_743 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_743 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_751 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_751 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_759 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_759 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_767 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_767 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_775 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_775 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_783 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_783 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_791 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_791 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_799 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_799 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_807 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_807 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_815 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_815 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_823 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_823 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_831 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_831 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_839 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_839 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_849 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_849 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_857 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_857 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_865 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_865 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_873 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_873 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_881 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_881 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_889 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_889 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_897 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_897 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_905 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_905 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_913 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_913 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_921 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_921 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_929 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_929 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_937 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_937 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_945 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_945 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_953 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_953 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_961 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_961 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_969 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_969 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_977 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_977 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_985 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_985 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_993 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_993 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1001 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1001 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1009 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1009 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1017 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1017 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1025 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1025 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1033 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1033 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1041 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1041 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1049 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1049 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1057 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1057 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1065 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1065 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1073 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1073 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1081 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1081 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1089 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1089 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1097 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1097 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1105 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1105 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1113 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1113 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1121 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1121 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1129 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1129 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1137 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1137 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1145 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1145 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1153 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1153 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1161 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1161 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1169 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1169 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1177 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1177 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1185 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1185 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1193 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1193 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1201 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1201 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1209 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1209 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1217 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1217 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1225 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1225 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1233 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1233 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1241 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1241 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1249 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1249 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1257 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1257 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1265 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1265 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1273 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1273 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1281 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1281 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1289 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1289 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1297 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1297 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1305 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1305 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1313 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1313 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1321 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1321 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1329 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1329 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1337 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1337 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1345 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1345 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1353 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1353 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire out_rimask_150 = \|_out_rimask_T_150; // @[RegisterRouter.scala:87:24] wire out_wimask_150 = &_out_wimask_T_150; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_150 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_150 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_158 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_158 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_166 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_166 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_174 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_174 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_182 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_182 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_190 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_190 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_198 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_198 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_206 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_206 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_214 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_214 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_222 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_222 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_230 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_230 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_238 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_238 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_246 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_246 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_254 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_254 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_262 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_262 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_270 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_270 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_278 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_278 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_286 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_286 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_294 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_294 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_302 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_302 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_310 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_310 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_318 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_318 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_326 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_326 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_334 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_334 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_342 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_342 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_350 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_350 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_358 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_358 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_366 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_366 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_374 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_374 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_382 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_382 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_390 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_390 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_398 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_398 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_406 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_406 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_414 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_414 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_422 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_422 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_430 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_430 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_438 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_438 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_446 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_446 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_454 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_454 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_462 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_462 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_470 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_470 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_478 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_478 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_486 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_486 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_494 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_494 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_504 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_504 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_512 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_512 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_520 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_520 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_528 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_528 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_536 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_536 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_544 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_544 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_552 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_552 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_560 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_560 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_568 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_568 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_576 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_576 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_584 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_584 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_593 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_593 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_601 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_601 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_609 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_609 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_617 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_617 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_625 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_625 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_637 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_637 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_645 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_645 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_653 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_653 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_661 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_661 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_669 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_669 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_677 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_677 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_687 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_687 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_695 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_695 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_703 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_703 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_711 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_711 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_719 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_719 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_727 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_727 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_735 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_735 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_743 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_743 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_751 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_751 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_759 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_759 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_767 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_767 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_775 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_775 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_783 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_783 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_791 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_791 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_799 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_799 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_807 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_807 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_815 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_815 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_823 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_823 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_831 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_831 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_839 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_839 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_849 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_849 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_857 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_857 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_865 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_865 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_873 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_873 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_881 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_881 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_889 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_889 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_897 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_897 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_905 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_905 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_913 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_913 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_921 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_921 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_929 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_929 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_937 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_937 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_945 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_945 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_953 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_953 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_961 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_961 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_969 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_969 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_977 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_977 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_985 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_985 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_993 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_993 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1001 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1001 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1009 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1009 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1017 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1017 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1025 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1025 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1033 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1033 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1041 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1041 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1049 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1049 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1057 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1057 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1065 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1065 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1073 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1073 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1081 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1081 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1089 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1089 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1097 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1097 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1105 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1105 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1113 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1113 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1121 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1121 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1129 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1129 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1137 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1137 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1145 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1145 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1153 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1153 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1161 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1161 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1169 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1169 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1177 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1177 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1185 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1185 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1193 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1193 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1201 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1201 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1209 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1209 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1217 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1217 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1225 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1225 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1233 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1233 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1241 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1241 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1249 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1249 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1257 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1257 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1265 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1265 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1273 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1273 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1281 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1281 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1289 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1289 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1297 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1297 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1305 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1305 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1313 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1313 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1321 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1321 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1329 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1329 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1337 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1337 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1345 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1345 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1353 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1353 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire out_romask_150 = \|_out_romask_T_150; // @[RegisterRouter.scala:87:24] wire out_womask_150 = &_out_womask_T_150; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_150 = out_rivalid_1_4 & out_rimask_150; // @[RegisterRouter.scala:87:24] wire _out_T_1947 = out_f_rivalid_150; // @[RegisterRouter.scala:87:24] wire out_f_roready_150 = out_roready_1_4 & out_romask_150; // @[RegisterRouter.scala:87:24] wire _out_T_1948 = out_f_roready_150; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_150 = out_wivalid_1_4 & out_wimask_150; // @[RegisterRouter.scala:87:24] wire out_f_woready_150 = out_woready_1_4 & out_womask_150; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1946 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2018 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2090 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2162 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2242 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2322 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2394 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2466 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2538 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2610 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2682 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2754 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2826 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2898 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2978 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3058 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3130 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3202 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3274 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3346 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3418 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3490 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3562 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3634 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3714 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3794 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3866 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3938 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4010 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4082 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4154 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4226 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4298 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4370 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4442 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4514 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4586 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4658 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4730 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4802 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4874 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4946 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5018 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5090 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5180 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5252 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5324 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5396 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5468 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5540 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5612 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5684 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5756 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5828 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5900 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5989 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6069 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6141 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6213 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6285 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6393 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6465 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6537 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6617 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6697 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6769 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6859 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6931 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7003 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7075 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7147 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7219 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7291 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7363 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7435 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7507 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7579 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7651 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7723 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7795 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7867 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7947 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8027 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8099 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8171 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8243 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8333 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8405 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8477 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8549 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8629 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8709 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8781 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8853 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8925 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8997 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9069 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9141 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9213 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9285 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9357 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9429 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9509 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9589 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9661 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9733 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9805 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9877 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9949 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10021 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10093 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10165 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10237 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10309 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10381 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10461 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10541 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10613 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10685 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10757 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10829 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10909 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10989 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11061 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11133 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11205 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11277 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11349 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11421 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11493 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11565 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11637 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11709 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11781 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11853 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11933 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12013 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12085 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12157 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12229 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12301 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12373 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12445 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12517 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12597 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12677 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12749 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12821 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12893 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12965 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire _out_T_1949 = ~out_rimask_150; // @[RegisterRouter.scala:87:24] wire _out_T_1950 = ~out_wimask_150; // @[RegisterRouter.scala:87:24] wire _out_T_1951 = ~out_romask_150; // @[RegisterRouter.scala:87:24] wire _out_T_1952 = ~out_womask_150; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_115 = {hi_85, flags_0_go, _out_prepend_T_115}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_1953 = out_prepend_115; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_1954 = _out_T_1953; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_116 = _out_T_1954; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_151 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_151 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_159 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_159 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_167 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_167 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_175 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_175 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_183 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_183 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_191 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_191 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_199 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_199 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_207 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_207 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_215 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_215 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_223 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_223 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_231 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_231 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_239 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_239 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_247 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_247 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_255 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_255 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_263 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_263 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_271 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_271 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_279 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_279 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_287 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_287 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_295 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_295 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_303 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_303 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_311 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_311 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_319 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_319 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_327 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_327 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_335 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_335 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_343 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_343 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_351 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_351 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_359 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_359 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_367 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_367 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_375 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_375 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_383 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_383 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_391 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_391 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_399 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_399 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_407 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_407 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_415 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_415 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_423 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_423 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_431 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_431 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_439 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_439 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_447 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_447 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_455 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_455 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_463 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_463 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_471 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_471 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_479 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_479 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_487 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_487 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_495 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_495 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_505 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_505 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_513 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_513 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_521 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_521 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_529 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_529 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_537 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_537 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_545 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_545 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_553 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_553 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_561 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_561 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_569 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_569 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_577 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_577 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_585 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_585 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_594 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_594 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_602 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_602 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_610 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_610 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_618 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_618 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_626 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_626 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_638 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_638 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_646 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_646 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_654 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_654 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_662 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_662 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_670 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_670 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_678 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_678 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_688 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_688 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_696 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_696 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_704 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_704 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_712 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_712 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_720 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_720 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_728 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_728 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_736 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_736 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_744 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_744 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_752 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_752 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_760 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_760 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_768 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_768 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_776 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_776 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_784 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_784 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_792 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_792 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_800 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_800 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_808 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_808 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_816 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_816 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_824 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_824 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_832 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_832 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_840 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_840 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_850 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_850 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_858 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_858 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_866 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_866 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_874 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_874 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_882 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_882 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_890 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_890 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_898 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_898 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_906 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_906 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_914 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_914 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_922 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_922 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_930 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_930 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_938 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_938 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_946 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_946 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_954 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_954 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_962 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_962 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_970 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_970 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_978 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_978 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_986 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_986 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_994 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_994 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1002 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1002 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1010 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1010 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1018 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1018 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1026 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1026 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1034 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1034 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1042 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1042 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1050 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1050 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1058 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1058 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1066 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1066 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1074 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1074 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1082 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1082 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1090 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1090 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1098 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1098 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1106 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1106 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1114 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1114 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1122 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1122 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1130 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1130 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1138 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1138 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1146 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1146 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1154 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1154 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1162 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1162 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1170 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1170 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1178 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1178 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1186 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1186 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1194 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1194 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1202 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1202 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1210 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1210 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1218 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1218 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1226 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1226 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1234 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1234 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1242 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1242 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1250 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1250 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1258 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1258 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1266 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1266 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1274 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1274 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1282 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1282 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1290 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1290 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1298 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1298 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1306 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1306 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1314 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1314 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1322 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1322 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1330 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1330 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1338 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1338 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1346 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1346 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1354 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1354 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire out_rimask_151 = \|_out_rimask_T_151; // @[RegisterRouter.scala:87:24] wire out_wimask_151 = &_out_wimask_T_151; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_151 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_151 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_159 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_159 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_167 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_167 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_175 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_175 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_183 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_183 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_191 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_191 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_199 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_199 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_207 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_207 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_215 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_215 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_223 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_223 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_231 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_231 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_239 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_239 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_247 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_247 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_255 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_255 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_263 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_263 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_271 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_271 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_279 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_279 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_287 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_287 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_295 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_295 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_303 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_303 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_311 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_311 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_319 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_319 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_327 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_327 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_335 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_335 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_343 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_343 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_351 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_351 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_359 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_359 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_367 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_367 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_375 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_375 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_383 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_383 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_391 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_391 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_399 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_399 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_407 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_407 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_415 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_415 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_423 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_423 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_431 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_431 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_439 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_439 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_447 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_447 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_455 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_455 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_463 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_463 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_471 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_471 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_479 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_479 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_487 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_487 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_495 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_495 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_505 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_505 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_513 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_513 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_521 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_521 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_529 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_529 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_537 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_537 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_545 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_545 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_553 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_553 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_561 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_561 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_569 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_569 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_577 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_577 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_585 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_585 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_594 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_594 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_602 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_602 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_610 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_610 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_618 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_618 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_626 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_626 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_638 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_638 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_646 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_646 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_654 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_654 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_662 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_662 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_670 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_670 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_678 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_678 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_688 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_688 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_696 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_696 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_704 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_704 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_712 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_712 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_720 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_720 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_728 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_728 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_736 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_736 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_744 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_744 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_752 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_752 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_760 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_760 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_768 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_768 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_776 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_776 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_784 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_784 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_792 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_792 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_800 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_800 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_808 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_808 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_816 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_816 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_824 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_824 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_832 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_832 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_840 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_840 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_850 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_850 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_858 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_858 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_866 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_866 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_874 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_874 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_882 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_882 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_890 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_890 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_898 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_898 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_906 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_906 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_914 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_914 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_922 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_922 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_930 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_930 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_938 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_938 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_946 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_946 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_954 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_954 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_962 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_962 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_970 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_970 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_978 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_978 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_986 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_986 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_994 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_994 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1002 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1002 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1010 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1010 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1018 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1018 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1026 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1026 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1034 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1034 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1042 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1042 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1050 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1050 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1058 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1058 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1066 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1066 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1074 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1074 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1082 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1082 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1090 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1090 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1098 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1098 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1106 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1106 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1114 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1114 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1122 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1122 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1130 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1130 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1138 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1138 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1146 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1146 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1154 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1154 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1162 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1162 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1170 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1170 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1178 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1178 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1186 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1186 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1194 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1194 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1202 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1202 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1210 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1210 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1218 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1218 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1226 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1226 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1234 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1234 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1242 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1242 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1250 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1250 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1258 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1258 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1266 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1266 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1274 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1274 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1282 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1282 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1290 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1290 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1298 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1298 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1306 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1306 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1314 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1314 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1322 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1322 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1330 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1330 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1338 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1338 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1346 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1346 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1354 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1354 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire out_romask_151 = \|_out_romask_T_151; // @[RegisterRouter.scala:87:24] wire out_womask_151 = &_out_womask_T_151; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_151 = out_rivalid_1_5 & out_rimask_151; // @[RegisterRouter.scala:87:24] wire _out_T_1956 = out_f_rivalid_151; // @[RegisterRouter.scala:87:24] wire out_f_roready_151 = out_roready_1_5 & out_romask_151; // @[RegisterRouter.scala:87:24] wire _out_T_1957 = out_f_roready_151; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_151 = out_wivalid_1_5 & out_wimask_151; // @[RegisterRouter.scala:87:24] wire out_f_woready_151 = out_woready_1_5 & out_womask_151; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1955 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2027 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2099 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2171 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2253 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2331 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2403 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2475 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2547 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2619 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2691 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2763 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2835 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2907 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2989 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3067 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3139 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3211 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3283 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3355 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3427 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3499 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3571 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3643 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3725 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3803 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3875 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3947 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4019 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4091 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4163 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4235 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4307 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4379 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4451 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4523 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4595 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4667 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4739 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4811 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4883 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4955 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5027 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5099 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5189 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5261 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5333 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5405 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5477 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5549 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5621 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5693 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5765 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5837 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5909 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6000 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6078 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6150 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6222 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6294 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6402 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6474 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6546 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6628 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6706 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6778 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6868 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6940 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7012 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7084 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7156 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7228 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7300 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7372 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7444 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7516 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7588 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7660 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7732 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7804 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7876 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7958 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8036 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8108 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8180 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8252 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8342 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8414 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8486 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8558 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8640 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8718 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8790 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8862 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8934 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9006 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9078 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9150 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9222 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9294 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9366 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9438 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9520 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9598 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9670 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9742 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9814 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9886 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9958 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10030 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10102 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10174 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10246 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10318 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10390 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10472 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10550 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10622 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10694 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10766 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10838 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10920 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10998 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11070 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11142 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11214 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11286 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11358 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11430 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11502 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11574 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11646 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11718 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11790 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11862 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11944 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12022 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12094 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12166 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12238 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12310 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12382 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12454 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12526 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12608 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12686 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12758 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12830 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12902 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12974 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire _out_T_1958 = ~out_rimask_151; // @[RegisterRouter.scala:87:24] wire _out_T_1959 = ~out_wimask_151; // @[RegisterRouter.scala:87:24] wire _out_T_1960 = ~out_romask_151; // @[RegisterRouter.scala:87:24] wire _out_T_1961 = ~out_womask_151; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_116 = {hi_86, flags_0_go, _out_prepend_T_116}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_1962 = out_prepend_116; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_1963 = _out_T_1962; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_117 = _out_T_1963; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_152 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_152 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_160 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_160 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_168 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_168 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_176 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_176 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_184 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_184 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_192 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_192 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_200 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_200 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_208 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_208 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_216 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_216 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_224 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_224 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_232 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_232 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_240 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_240 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_248 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_248 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_256 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_256 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_264 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_264 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_272 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_272 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_280 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_280 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_288 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_288 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_296 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_296 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_304 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_304 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_312 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_312 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_320 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_320 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_328 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_328 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_336 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_336 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_344 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_344 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_352 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_352 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_360 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_360 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_368 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_368 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_376 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_376 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_384 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_384 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_392 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_392 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_400 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_400 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_408 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_408 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_416 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_416 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_424 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_424 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_432 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_432 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_440 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_440 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_448 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_448 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_456 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_456 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_464 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_464 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_472 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_472 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_480 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_480 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_488 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_488 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_496 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_496 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_506 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_506 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_514 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_514 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_522 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_522 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_530 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_530 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_538 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_538 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_546 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_546 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_554 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_554 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_562 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_562 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_570 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_570 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_578 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_578 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_586 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_586 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_595 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_595 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_603 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_603 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_611 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_611 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_619 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_619 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_627 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_627 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_639 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_639 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_647 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_647 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_655 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_655 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_663 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_663 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_671 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_671 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_679 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_679 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_689 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_689 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_697 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_697 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_705 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_705 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_713 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_713 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_721 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_721 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_729 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_729 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_737 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_737 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_745 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_745 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_753 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_753 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_761 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_761 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_769 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_769 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_777 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_777 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_785 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_785 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_793 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_793 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_801 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_801 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_809 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_809 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_817 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_817 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_825 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_825 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_833 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_833 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_841 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_841 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_851 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_851 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_859 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_859 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_867 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_867 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_875 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_875 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_883 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_883 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_891 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_891 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_899 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_899 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_907 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_907 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_915 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_915 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_923 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_923 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_931 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_931 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_939 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_939 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_947 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_947 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_955 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_955 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_963 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_963 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_971 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_971 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_979 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_979 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_987 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_987 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_995 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_995 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1003 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1003 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1011 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1011 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1019 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1019 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1027 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1027 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1035 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1035 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1043 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1043 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1051 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1051 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1059 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1059 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1067 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1067 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1075 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1075 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1083 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1083 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1091 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1091 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1099 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1099 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1107 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1107 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1115 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1115 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1123 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1123 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1131 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1131 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1139 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1139 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1147 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1147 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1155 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1155 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1163 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1163 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1171 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1171 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1179 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1179 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1187 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1187 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1195 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1195 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1203 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1203 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1211 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1211 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1219 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1219 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1227 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1227 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1235 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1235 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1243 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1243 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1251 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1251 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1259 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1259 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1267 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1267 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1275 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1275 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1283 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1283 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1291 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1291 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1299 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1299 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1307 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1307 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1315 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1315 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1323 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1323 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1331 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1331 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1339 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1339 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1347 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1347 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1355 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1355 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire out_rimask_152 = \|_out_rimask_T_152; // @[RegisterRouter.scala:87:24] wire out_wimask_152 = &_out_wimask_T_152; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_152 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_152 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_160 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_160 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_168 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_168 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_176 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_176 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_184 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_184 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_192 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_192 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_200 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_200 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_208 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_208 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_216 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_216 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_224 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_224 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_232 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_232 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_240 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_240 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_248 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_248 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_256 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_256 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_264 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_264 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_272 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_272 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_280 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_280 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_288 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_288 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_296 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_296 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_304 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_304 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_312 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_312 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_320 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_320 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_328 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_328 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_336 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_336 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_344 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_344 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_352 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_352 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_360 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_360 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_368 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_368 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_376 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_376 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_384 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_384 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_392 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_392 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_400 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_400 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_408 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_408 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_416 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_416 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_424 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_424 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_432 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_432 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_440 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_440 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_448 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_448 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_456 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_456 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_464 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_464 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_472 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_472 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_480 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_480 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_488 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_488 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_496 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_496 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_506 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_506 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_514 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_514 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_522 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_522 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_530 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_530 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_538 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_538 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_546 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_546 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_554 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_554 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_562 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_562 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_570 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_570 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_578 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_578 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_586 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_586 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_595 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_595 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_603 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_603 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_611 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_611 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_619 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_619 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_627 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_627 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_639 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_639 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_647 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_647 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_655 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_655 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_663 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_663 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_671 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_671 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_679 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_679 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_689 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_689 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_697 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_697 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_705 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_705 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_713 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_713 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_721 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_721 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_729 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_729 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_737 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_737 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_745 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_745 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_753 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_753 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_761 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_761 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_769 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_769 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_777 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_777 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_785 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_785 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_793 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_793 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_801 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_801 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_809 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_809 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_817 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_817 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_825 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_825 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_833 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_833 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_841 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_841 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_851 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_851 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_859 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_859 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_867 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_867 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_875 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_875 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_883 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_883 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_891 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_891 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_899 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_899 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_907 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_907 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_915 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_915 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_923 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_923 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_931 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_931 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_939 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_939 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_947 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_947 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_955 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_955 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_963 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_963 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_971 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_971 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_979 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_979 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_987 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_987 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_995 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_995 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1003 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1003 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1011 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1011 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1019 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1019 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1027 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1027 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1035 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1035 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1043 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1043 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1051 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1051 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1059 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1059 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1067 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1067 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1075 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1075 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1083 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1083 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1091 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1091 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1099 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1099 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1107 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1107 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1115 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1115 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1123 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1123 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1131 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1131 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1139 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1139 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1147 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1147 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1155 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1155 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1163 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1163 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1171 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1171 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1179 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1179 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1187 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1187 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1195 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1195 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1203 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1203 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1211 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1211 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1219 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1219 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1227 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1227 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1235 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1235 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1243 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1243 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1251 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1251 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1259 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1259 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1267 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1267 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1275 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1275 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1283 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1283 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1291 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1291 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1299 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1299 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1307 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1307 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1315 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1315 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1323 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1323 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1331 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1331 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1339 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1339 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1347 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1347 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1355 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1355 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire out_romask_152 = \|_out_romask_T_152; // @[RegisterRouter.scala:87:24] wire out_womask_152 = &_out_womask_T_152; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_152 = out_rivalid_1_6 & out_rimask_152; // @[RegisterRouter.scala:87:24] wire _out_T_1965 = out_f_rivalid_152; // @[RegisterRouter.scala:87:24] wire out_f_roready_152 = out_roready_1_6 & out_romask_152; // @[RegisterRouter.scala:87:24] wire _out_T_1966 = out_f_roready_152; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_152 = out_wivalid_1_6 & out_wimask_152; // @[RegisterRouter.scala:87:24] wire out_f_woready_152 = out_woready_1_6 & out_womask_152; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1964 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2036 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2108 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2180 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2264 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2340 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2412 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2484 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2556 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2628 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2700 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2772 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2844 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2916 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3000 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3076 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3148 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3220 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3292 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3364 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3436 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3508 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3580 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3652 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3736 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3812 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3884 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3956 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4028 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4100 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4172 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4244 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4316 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4388 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4460 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4532 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4604 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4676 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4748 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4820 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4892 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4964 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5036 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5108 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5198 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5270 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5342 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5414 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5486 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5558 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5630 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5702 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5774 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5846 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5918 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6011 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6087 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6159 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6231 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6303 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6411 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6483 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6555 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6639 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6715 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6787 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6877 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6949 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7021 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7093 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7165 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7237 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7309 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7381 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7453 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7525 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7597 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7669 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7741 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7813 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7885 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7969 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8045 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8117 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8189 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8261 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8351 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8423 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8495 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8567 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8651 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8727 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8799 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8871 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8943 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9015 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9087 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9159 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9231 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9303 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9375 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9447 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9531 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9607 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9679 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9751 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9823 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9895 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9967 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10039 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10111 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10183 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10255 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10327 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10399 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10483 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10559 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10631 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10703 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10775 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10847 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10931 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11007 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11079 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11151 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11223 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11295 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11367 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11439 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11511 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11583 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11655 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11727 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11799 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11871 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11955 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12031 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12103 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12175 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12247 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12319 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12391 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12463 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12535 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12619 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12695 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12767 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12839 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12911 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12983 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire _out_T_1967 = ~out_rimask_152; // @[RegisterRouter.scala:87:24] wire _out_T_1968 = ~out_wimask_152; // @[RegisterRouter.scala:87:24] wire _out_T_1969 = ~out_romask_152; // @[RegisterRouter.scala:87:24] wire _out_T_1970 = ~out_womask_152; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_117 = {hi_87, flags_0_go, _out_prepend_T_117}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_1971 = out_prepend_117; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_1972 = _out_T_1971; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_118 = _out_T_1972; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_153 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_153 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_161 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_161 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_169 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_169 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_177 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_177 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_185 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_185 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_193 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_193 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_201 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_201 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_209 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_209 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_217 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_217 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_225 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_225 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_233 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_233 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_241 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_241 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_249 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_249 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_257 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_257 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_265 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_265 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_273 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_273 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_281 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_281 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_289 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_289 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_297 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_297 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_305 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_305 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_313 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_313 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_321 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_321 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_329 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_329 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_337 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_337 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_345 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_345 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_353 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_353 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_361 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_361 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_369 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_369 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_377 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_377 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_385 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_385 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_393 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_393 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_401 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_401 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_409 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_409 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_417 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_417 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_425 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_425 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_433 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_433 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_441 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_441 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_449 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_449 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_457 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_457 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_465 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_465 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_473 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_473 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_481 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_481 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_489 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_489 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_497 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_497 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_507 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_507 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_515 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_515 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_523 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_523 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_531 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_531 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_539 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_539 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_547 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_547 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_555 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_555 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_563 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_563 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_571 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_571 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_579 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_579 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_587 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_587 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_596 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_596 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_604 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_604 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_612 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_612 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_620 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_620 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_628 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_628 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_640 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_640 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_648 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_648 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_656 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_656 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_664 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_664 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_672 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_672 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_680 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_680 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_690 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_690 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_698 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_698 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_706 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_706 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_714 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_714 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_722 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_722 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_730 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_730 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_738 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_738 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_746 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_746 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_754 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_754 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_762 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_762 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_770 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_770 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_778 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_778 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_786 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_786 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_794 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_794 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_802 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_802 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_810 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_810 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_818 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_818 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_826 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_826 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_834 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_834 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_842 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_842 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_852 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_852 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_860 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_860 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_868 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_868 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_876 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_876 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_884 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_884 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_892 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_892 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_900 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_900 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_908 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_908 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_916 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_916 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_924 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_924 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_932 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_932 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_940 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_940 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_948 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_948 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_956 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_956 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_964 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_964 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_972 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_972 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_980 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_980 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_988 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_988 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_996 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_996 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1004 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1004 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1012 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1012 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1020 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1020 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1028 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1028 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1036 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1036 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1044 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1044 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1052 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1052 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1060 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1060 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1068 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1068 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1076 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1076 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1084 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1084 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1092 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1092 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1100 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1100 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1108 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1108 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1116 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1116 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1124 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1124 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1132 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1132 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1140 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1140 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1148 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1148 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1156 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1156 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1164 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1164 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1172 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1172 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1180 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1180 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1188 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1188 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1196 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1196 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1204 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1204 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1212 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1212 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1220 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1220 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1228 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1228 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1236 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1236 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1244 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1244 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1252 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1252 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1260 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1260 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1268 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1268 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1276 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1276 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1284 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1284 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1292 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1292 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1300 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1300 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1308 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1308 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1316 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1316 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1324 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1324 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1332 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1332 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1340 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1340 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1348 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1348 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1356 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1356 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire out_rimask_153 = \|_out_rimask_T_153; // @[RegisterRouter.scala:87:24] wire out_wimask_153 = &_out_wimask_T_153; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_153 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_153 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_161 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_161 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_169 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_169 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_177 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_177 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_185 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_185 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_193 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_193 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_201 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_201 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_209 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_209 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_217 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_217 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_225 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_225 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_233 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_233 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_241 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_241 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_249 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_249 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_257 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_257 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_265 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_265 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_273 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_273 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_281 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_281 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_289 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_289 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_297 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_297 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_305 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_305 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_313 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_313 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_321 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_321 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_329 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_329 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_337 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_337 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_345 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_345 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_353 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_353 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_361 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_361 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_369 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_369 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_377 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_377 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_385 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_385 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_393 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_393 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_401 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_401 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_409 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_409 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_417 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_417 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_425 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_425 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_433 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_433 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_441 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_441 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_449 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_449 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_457 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_457 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_465 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_465 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_473 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_473 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_481 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_481 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_489 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_489 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_497 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_497 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_507 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_507 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_515 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_515 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_523 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_523 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_531 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_531 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_539 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_539 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_547 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_547 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_555 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_555 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_563 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_563 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_571 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_571 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_579 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_579 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_587 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_587 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_596 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_596 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_604 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_604 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_612 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_612 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_620 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_620 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_628 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_628 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_640 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_640 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_648 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_648 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_656 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_656 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_664 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_664 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_672 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_672 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_680 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_680 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_690 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_690 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_698 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_698 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_706 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_706 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_714 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_714 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_722 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_722 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_730 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_730 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_738 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_738 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_746 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_746 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_754 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_754 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_762 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_762 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_770 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_770 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_778 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_778 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_786 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_786 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_794 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_794 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_802 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_802 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_810 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_810 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_818 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_818 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_826 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_826 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_834 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_834 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_842 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_842 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_852 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_852 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_860 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_860 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_868 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_868 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_876 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_876 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_884 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_884 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_892 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_892 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_900 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_900 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_908 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_908 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_916 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_916 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_924 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_924 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_932 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_932 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_940 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_940 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_948 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_948 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_956 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_956 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_964 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_964 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_972 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_972 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_980 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_980 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_988 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_988 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_996 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_996 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1004 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1004 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1012 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1012 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1020 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1020 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1028 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1028 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1036 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1036 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1044 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1044 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1052 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1052 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1060 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1060 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1068 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1068 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1076 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1076 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1084 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1084 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1092 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1092 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1100 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1100 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1108 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1108 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1116 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1116 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1124 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1124 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1132 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1132 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1140 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1140 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1148 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1148 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1156 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1156 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1164 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1164 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1172 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1172 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1180 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1180 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1188 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1188 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1196 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1196 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1204 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1204 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1212 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1212 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1220 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1220 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1228 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1228 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1236 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1236 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1244 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1244 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1252 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1252 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1260 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1260 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1268 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1268 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1276 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1276 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1284 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1284 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1292 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1292 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1300 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1300 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1308 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1308 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1316 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1316 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1324 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1324 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1332 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1332 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1340 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1340 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1348 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1348 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1356 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1356 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire out_romask_153 = \|_out_romask_T_153; // @[RegisterRouter.scala:87:24] wire out_womask_153 = &_out_womask_T_153; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_153 = out_rivalid_1_7 & out_rimask_153; // @[RegisterRouter.scala:87:24] wire _out_T_1974 = out_f_rivalid_153; // @[RegisterRouter.scala:87:24] wire out_f_roready_153 = out_roready_1_7 & out_romask_153; // @[RegisterRouter.scala:87:24] wire _out_T_1975 = out_f_roready_153; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_153 = out_wivalid_1_7 & out_wimask_153; // @[RegisterRouter.scala:87:24] wire out_f_woready_153 = out_woready_1_7 & out_womask_153; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1973 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2045 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2117 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2189 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2275 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2349 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2421 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2493 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2565 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2637 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2709 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2781 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2853 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2925 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3011 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3085 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3157 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3229 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3301 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3373 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3445 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3517 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3589 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3661 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3747 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3821 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3893 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3965 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4037 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4109 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4181 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4253 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4325 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4397 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4469 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4541 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4613 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4685 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4757 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4829 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4901 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4973 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5045 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5117 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5207 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5279 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5351 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5423 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5495 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5567 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5639 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5711 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5783 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5855 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5927 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6022 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6096 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6168 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6240 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6312 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6420 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6492 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6564 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6650 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6724 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6796 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6886 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6958 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7030 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7102 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7174 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7246 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7318 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7390 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7462 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7534 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7606 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7678 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7750 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7822 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7894 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7980 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8054 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8126 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8198 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8270 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8360 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8432 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8504 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8576 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8662 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8736 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8808 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8880 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8952 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9024 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9096 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9168 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9240 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9312 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9384 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9456 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9542 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9616 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9688 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9760 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9832 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9904 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9976 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10048 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10120 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10192 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10264 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10336 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10408 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10494 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10568 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10640 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10712 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10784 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10856 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10942 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11016 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11088 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11160 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11232 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11304 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11376 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11448 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11520 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11592 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11664 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11736 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11808 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11880 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11966 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12040 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12112 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12184 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12256 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12328 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12400 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12472 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12544 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12630 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12704 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12776 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12848 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12920 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12992 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire _out_T_1976 = ~out_rimask_153; // @[RegisterRouter.scala:87:24] wire _out_T_1977 = ~out_wimask_153; // @[RegisterRouter.scala:87:24] wire _out_T_1978 = ~out_romask_153; // @[RegisterRouter.scala:87:24] wire _out_T_1979 = ~out_womask_153; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_118 = {hi_88, flags_0_go, _out_prepend_T_118}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_1980 = out_prepend_118; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_1981 = _out_T_1980; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_138 = _out_T_1981; // @[MuxLiteral.scala:49:48] wire out_rimask_154 = \|_out_rimask_T_154; // @[RegisterRouter.scala:87:24] wire out_wimask_154 = &_out_wimask_T_154; // @[RegisterRouter.scala:87:24] wire out_romask_154 = \|_out_romask_T_154; // @[RegisterRouter.scala:87:24] wire out_womask_154 = &_out_womask_T_154; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_154 = out_rivalid_1_8 & out_rimask_154; // @[RegisterRouter.scala:87:24] wire _out_T_1983 = out_f_rivalid_154; // @[RegisterRouter.scala:87:24] wire out_f_roready_154 = out_roready_1_8 & out_romask_154; // @[RegisterRouter.scala:87:24] wire _out_T_1984 = out_f_roready_154; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_154 = out_wivalid_1_8 & out_wimask_154; // @[RegisterRouter.scala:87:24] wire out_f_woready_154 = out_woready_1_8 & out_womask_154; // @[RegisterRouter.scala:87:24] wire _out_T_1985 = ~out_rimask_154; // @[RegisterRouter.scala:87:24] wire _out_T_1986 = ~out_wimask_154; // @[RegisterRouter.scala:87:24] wire _out_T_1987 = ~out_romask_154; // @[RegisterRouter.scala:87:24] wire _out_T_1988 = ~out_womask_154; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1990 = _out_T_1989; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_119 = _out_T_1990; // @[RegisterRouter.scala:87:24] wire out_rimask_155 = \|_out_rimask_T_155; // @[RegisterRouter.scala:87:24] wire out_wimask_155 = &_out_wimask_T_155; // @[RegisterRouter.scala:87:24] wire out_romask_155 = \|_out_romask_T_155; // @[RegisterRouter.scala:87:24] wire out_womask_155 = &_out_womask_T_155; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_155 = out_rivalid_1_9 & out_rimask_155; // @[RegisterRouter.scala:87:24] wire _out_T_1992 = out_f_rivalid_155; // @[RegisterRouter.scala:87:24] wire out_f_roready_155 = out_roready_1_9 & out_romask_155; // @[RegisterRouter.scala:87:24] wire _out_T_1993 = out_f_roready_155; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_155 = out_wivalid_1_9 & out_wimask_155; // @[RegisterRouter.scala:87:24] wire out_f_woready_155 = out_woready_1_9 & out_womask_155; // @[RegisterRouter.scala:87:24] wire _out_T_1994 = ~out_rimask_155; // @[RegisterRouter.scala:87:24] wire _out_T_1995 = ~out_wimask_155; // @[RegisterRouter.scala:87:24] wire _out_T_1996 = ~out_romask_155; // @[RegisterRouter.scala:87:24] wire _out_T_1997 = ~out_womask_155; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_119 = {hi_970, flags_0_go, _out_prepend_T_119}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1998 = out_prepend_119; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1999 = _out_T_1998; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_120 = _out_T_1999; // @[RegisterRouter.scala:87:24] wire out_rimask_156 = \|_out_rimask_T_156; // @[RegisterRouter.scala:87:24] wire out_wimask_156 = &_out_wimask_T_156; // @[RegisterRouter.scala:87:24] wire out_romask_156 = \|_out_romask_T_156; // @[RegisterRouter.scala:87:24] wire out_womask_156 = &_out_womask_T_156; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_156 = out_rivalid_1_10 & out_rimask_156; // @[RegisterRouter.scala:87:24] wire _out_T_2001 = out_f_rivalid_156; // @[RegisterRouter.scala:87:24] wire out_f_roready_156 = out_roready_1_10 & out_romask_156; // @[RegisterRouter.scala:87:24] wire _out_T_2002 = out_f_roready_156; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_156 = out_wivalid_1_10 & out_wimask_156; // @[RegisterRouter.scala:87:24] wire out_f_woready_156 = out_woready_1_10 & out_womask_156; // @[RegisterRouter.scala:87:24] wire _out_T_2003 = ~out_rimask_156; // @[RegisterRouter.scala:87:24] wire _out_T_2004 = ~out_wimask_156; // @[RegisterRouter.scala:87:24] wire _out_T_2005 = ~out_romask_156; // @[RegisterRouter.scala:87:24] wire _out_T_2006 = ~out_womask_156; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_120 = {hi_971, flags_0_go, _out_prepend_T_120}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2007 = out_prepend_120; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2008 = _out_T_2007; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_121 = _out_T_2008; // @[RegisterRouter.scala:87:24] wire out_rimask_157 = \|_out_rimask_T_157; // @[RegisterRouter.scala:87:24] wire out_wimask_157 = &_out_wimask_T_157; // @[RegisterRouter.scala:87:24] wire out_romask_157 = \|_out_romask_T_157; // @[RegisterRouter.scala:87:24] wire out_womask_157 = &_out_womask_T_157; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_157 = out_rivalid_1_11 & out_rimask_157; // @[RegisterRouter.scala:87:24] wire _out_T_2010 = out_f_rivalid_157; // @[RegisterRouter.scala:87:24] wire out_f_roready_157 = out_roready_1_11 & out_romask_157; // @[RegisterRouter.scala:87:24] wire _out_T_2011 = out_f_roready_157; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_157 = out_wivalid_1_11 & out_wimask_157; // @[RegisterRouter.scala:87:24] wire out_f_woready_157 = out_woready_1_11 & out_womask_157; // @[RegisterRouter.scala:87:24] wire _out_T_2012 = ~out_rimask_157; // @[RegisterRouter.scala:87:24] wire _out_T_2013 = ~out_wimask_157; // @[RegisterRouter.scala:87:24] wire _out_T_2014 = ~out_romask_157; // @[RegisterRouter.scala:87:24] wire _out_T_2015 = ~out_womask_157; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_121 = {hi_972, flags_0_go, _out_prepend_T_121}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2016 = out_prepend_121; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2017 = _out_T_2016; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_122 = _out_T_2017; // @[RegisterRouter.scala:87:24] wire out_rimask_158 = \|_out_rimask_T_158; // @[RegisterRouter.scala:87:24] wire out_wimask_158 = &_out_wimask_T_158; // @[RegisterRouter.scala:87:24] wire out_romask_158 = \|_out_romask_T_158; // @[RegisterRouter.scala:87:24] wire out_womask_158 = &_out_womask_T_158; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_158 = out_rivalid_1_12 & out_rimask_158; // @[RegisterRouter.scala:87:24] wire _out_T_2019 = out_f_rivalid_158; // @[RegisterRouter.scala:87:24] wire out_f_roready_158 = out_roready_1_12 & out_romask_158; // @[RegisterRouter.scala:87:24] wire _out_T_2020 = out_f_roready_158; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_158 = out_wivalid_1_12 & out_wimask_158; // @[RegisterRouter.scala:87:24] wire out_f_woready_158 = out_woready_1_12 & out_womask_158; // @[RegisterRouter.scala:87:24] wire _out_T_2021 = ~out_rimask_158; // @[RegisterRouter.scala:87:24] wire _out_T_2022 = ~out_wimask_158; // @[RegisterRouter.scala:87:24] wire _out_T_2023 = ~out_romask_158; // @[RegisterRouter.scala:87:24] wire _out_T_2024 = ~out_womask_158; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_122 = {hi_973, flags_0_go, _out_prepend_T_122}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2025 = out_prepend_122; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2026 = _out_T_2025; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_123 = _out_T_2026; // @[RegisterRouter.scala:87:24] wire out_rimask_159 = \|_out_rimask_T_159; // @[RegisterRouter.scala:87:24] wire out_wimask_159 = &_out_wimask_T_159; // @[RegisterRouter.scala:87:24] wire out_romask_159 = \|_out_romask_T_159; // @[RegisterRouter.scala:87:24] wire out_womask_159 = &_out_womask_T_159; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_159 = out_rivalid_1_13 & out_rimask_159; // @[RegisterRouter.scala:87:24] wire _out_T_2028 = out_f_rivalid_159; // @[RegisterRouter.scala:87:24] wire out_f_roready_159 = out_roready_1_13 & out_romask_159; // @[RegisterRouter.scala:87:24] wire _out_T_2029 = out_f_roready_159; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_159 = out_wivalid_1_13 & out_wimask_159; // @[RegisterRouter.scala:87:24] wire out_f_woready_159 = out_woready_1_13 & out_womask_159; // @[RegisterRouter.scala:87:24] wire _out_T_2030 = ~out_rimask_159; // @[RegisterRouter.scala:87:24] wire _out_T_2031 = ~out_wimask_159; // @[RegisterRouter.scala:87:24] wire _out_T_2032 = ~out_romask_159; // @[RegisterRouter.scala:87:24] wire _out_T_2033 = ~out_womask_159; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_123 = {hi_974, flags_0_go, _out_prepend_T_123}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2034 = out_prepend_123; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2035 = _out_T_2034; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_124 = _out_T_2035; // @[RegisterRouter.scala:87:24] wire out_rimask_160 = \|_out_rimask_T_160; // @[RegisterRouter.scala:87:24] wire out_wimask_160 = &_out_wimask_T_160; // @[RegisterRouter.scala:87:24] wire out_romask_160 = \|_out_romask_T_160; // @[RegisterRouter.scala:87:24] wire out_womask_160 = &_out_womask_T_160; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_160 = out_rivalid_1_14 & out_rimask_160; // @[RegisterRouter.scala:87:24] wire _out_T_2037 = out_f_rivalid_160; // @[RegisterRouter.scala:87:24] wire out_f_roready_160 = out_roready_1_14 & out_romask_160; // @[RegisterRouter.scala:87:24] wire _out_T_2038 = out_f_roready_160; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_160 = out_wivalid_1_14 & out_wimask_160; // @[RegisterRouter.scala:87:24] wire out_f_woready_160 = out_woready_1_14 & out_womask_160; // @[RegisterRouter.scala:87:24] wire _out_T_2039 = ~out_rimask_160; // @[RegisterRouter.scala:87:24] wire _out_T_2040 = ~out_wimask_160; // @[RegisterRouter.scala:87:24] wire _out_T_2041 = ~out_romask_160; // @[RegisterRouter.scala:87:24] wire _out_T_2042 = ~out_womask_160; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_124 = {hi_975, flags_0_go, _out_prepend_T_124}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2043 = out_prepend_124; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2044 = _out_T_2043; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_125 = _out_T_2044; // @[RegisterRouter.scala:87:24] wire out_rimask_161 = \|_out_rimask_T_161; // @[RegisterRouter.scala:87:24] wire out_wimask_161 = &_out_wimask_T_161; // @[RegisterRouter.scala:87:24] wire out_romask_161 = \|_out_romask_T_161; // @[RegisterRouter.scala:87:24] wire out_womask_161 = &_out_womask_T_161; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_161 = out_rivalid_1_15 & out_rimask_161; // @[RegisterRouter.scala:87:24] wire _out_T_2046 = out_f_rivalid_161; // @[RegisterRouter.scala:87:24] wire out_f_roready_161 = out_roready_1_15 & out_romask_161; // @[RegisterRouter.scala:87:24] wire _out_T_2047 = out_f_roready_161; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_161 = out_wivalid_1_15 & out_wimask_161; // @[RegisterRouter.scala:87:24] wire out_f_woready_161 = out_woready_1_15 & out_womask_161; // @[RegisterRouter.scala:87:24] wire _out_T_2048 = ~out_rimask_161; // @[RegisterRouter.scala:87:24] wire _out_T_2049 = ~out_wimask_161; // @[RegisterRouter.scala:87:24] wire _out_T_2050 = ~out_romask_161; // @[RegisterRouter.scala:87:24] wire _out_T_2051 = ~out_womask_161; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_125 = {hi_976, flags_0_go, _out_prepend_T_125}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2052 = out_prepend_125; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2053 = _out_T_2052; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_249 = _out_T_2053; // @[MuxLiteral.scala:49:48] wire out_rimask_162 = \|_out_rimask_T_162; // @[RegisterRouter.scala:87:24] wire out_wimask_162 = &_out_wimask_T_162; // @[RegisterRouter.scala:87:24] wire out_romask_162 = \|_out_romask_T_162; // @[RegisterRouter.scala:87:24] wire out_womask_162 = &_out_womask_T_162; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_162 = out_rivalid_1_16 & out_rimask_162; // @[RegisterRouter.scala:87:24] wire _out_T_2055 = out_f_rivalid_162; // @[RegisterRouter.scala:87:24] wire out_f_roready_162 = out_roready_1_16 & out_romask_162; // @[RegisterRouter.scala:87:24] wire _out_T_2056 = out_f_roready_162; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_162 = out_wivalid_1_16 & out_wimask_162; // @[RegisterRouter.scala:87:24] wire out_f_woready_162 = out_woready_1_16 & out_womask_162; // @[RegisterRouter.scala:87:24] wire _out_T_2057 = ~out_rimask_162; // @[RegisterRouter.scala:87:24] wire _out_T_2058 = ~out_wimask_162; // @[RegisterRouter.scala:87:24] wire _out_T_2059 = ~out_romask_162; // @[RegisterRouter.scala:87:24] wire _out_T_2060 = ~out_womask_162; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2062 = _out_T_2061; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_126 = _out_T_2062; // @[RegisterRouter.scala:87:24] wire out_rimask_163 = \|_out_rimask_T_163; // @[RegisterRouter.scala:87:24] wire out_wimask_163 = &_out_wimask_T_163; // @[RegisterRouter.scala:87:24] wire out_romask_163 = \|_out_romask_T_163; // @[RegisterRouter.scala:87:24] wire out_womask_163 = &_out_womask_T_163; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_163 = out_rivalid_1_17 & out_rimask_163; // @[RegisterRouter.scala:87:24] wire _out_T_2064 = out_f_rivalid_163; // @[RegisterRouter.scala:87:24] wire out_f_roready_163 = out_roready_1_17 & out_romask_163; // @[RegisterRouter.scala:87:24] wire _out_T_2065 = out_f_roready_163; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_163 = out_wivalid_1_17 & out_wimask_163; // @[RegisterRouter.scala:87:24] wire out_f_woready_163 = out_woready_1_17 & out_womask_163; // @[RegisterRouter.scala:87:24] wire _out_T_2066 = ~out_rimask_163; // @[RegisterRouter.scala:87:24] wire _out_T_2067 = ~out_wimask_163; // @[RegisterRouter.scala:87:24] wire _out_T_2068 = ~out_romask_163; // @[RegisterRouter.scala:87:24] wire _out_T_2069 = ~out_womask_163; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_126 = {hi_850, flags_0_go, _out_prepend_T_126}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2070 = out_prepend_126; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2071 = _out_T_2070; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_127 = _out_T_2071; // @[RegisterRouter.scala:87:24] wire out_rimask_164 = \|_out_rimask_T_164; // @[RegisterRouter.scala:87:24] wire out_wimask_164 = &_out_wimask_T_164; // @[RegisterRouter.scala:87:24] wire out_romask_164 = \|_out_romask_T_164; // @[RegisterRouter.scala:87:24] wire out_womask_164 = &_out_womask_T_164; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_164 = out_rivalid_1_18 & out_rimask_164; // @[RegisterRouter.scala:87:24] wire _out_T_2073 = out_f_rivalid_164; // @[RegisterRouter.scala:87:24] wire out_f_roready_164 = out_roready_1_18 & out_romask_164; // @[RegisterRouter.scala:87:24] wire _out_T_2074 = out_f_roready_164; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_164 = out_wivalid_1_18 & out_wimask_164; // @[RegisterRouter.scala:87:24] wire out_f_woready_164 = out_woready_1_18 & out_womask_164; // @[RegisterRouter.scala:87:24] wire _out_T_2075 = ~out_rimask_164; // @[RegisterRouter.scala:87:24] wire _out_T_2076 = ~out_wimask_164; // @[RegisterRouter.scala:87:24] wire _out_T_2077 = ~out_romask_164; // @[RegisterRouter.scala:87:24] wire _out_T_2078 = ~out_womask_164; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_127 = {hi_851, flags_0_go, _out_prepend_T_127}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2079 = out_prepend_127; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2080 = _out_T_2079; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_128 = _out_T_2080; // @[RegisterRouter.scala:87:24] wire out_rimask_165 = \|_out_rimask_T_165; // @[RegisterRouter.scala:87:24] wire out_wimask_165 = &_out_wimask_T_165; // @[RegisterRouter.scala:87:24] wire out_romask_165 = \|_out_romask_T_165; // @[RegisterRouter.scala:87:24] wire out_womask_165 = &_out_womask_T_165; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_165 = out_rivalid_1_19 & out_rimask_165; // @[RegisterRouter.scala:87:24] wire _out_T_2082 = out_f_rivalid_165; // @[RegisterRouter.scala:87:24] wire out_f_roready_165 = out_roready_1_19 & out_romask_165; // @[RegisterRouter.scala:87:24] wire _out_T_2083 = out_f_roready_165; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_165 = out_wivalid_1_19 & out_wimask_165; // @[RegisterRouter.scala:87:24] wire out_f_woready_165 = out_woready_1_19 & out_womask_165; // @[RegisterRouter.scala:87:24] wire _out_T_2084 = ~out_rimask_165; // @[RegisterRouter.scala:87:24] wire _out_T_2085 = ~out_wimask_165; // @[RegisterRouter.scala:87:24] wire _out_T_2086 = ~out_romask_165; // @[RegisterRouter.scala:87:24] wire _out_T_2087 = ~out_womask_165; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_128 = {hi_852, flags_0_go, _out_prepend_T_128}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2088 = out_prepend_128; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2089 = _out_T_2088; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_129 = _out_T_2089; // @[RegisterRouter.scala:87:24] wire out_rimask_166 = \|_out_rimask_T_166; // @[RegisterRouter.scala:87:24] wire out_wimask_166 = &_out_wimask_T_166; // @[RegisterRouter.scala:87:24] wire out_romask_166 = \|_out_romask_T_166; // @[RegisterRouter.scala:87:24] wire out_womask_166 = &_out_womask_T_166; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_166 = out_rivalid_1_20 & out_rimask_166; // @[RegisterRouter.scala:87:24] wire _out_T_2091 = out_f_rivalid_166; // @[RegisterRouter.scala:87:24] wire out_f_roready_166 = out_roready_1_20 & out_romask_166; // @[RegisterRouter.scala:87:24] wire _out_T_2092 = out_f_roready_166; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_166 = out_wivalid_1_20 & out_wimask_166; // @[RegisterRouter.scala:87:24] wire out_f_woready_166 = out_woready_1_20 & out_womask_166; // @[RegisterRouter.scala:87:24] wire _out_T_2093 = ~out_rimask_166; // @[RegisterRouter.scala:87:24] wire _out_T_2094 = ~out_wimask_166; // @[RegisterRouter.scala:87:24] wire _out_T_2095 = ~out_romask_166; // @[RegisterRouter.scala:87:24] wire _out_T_2096 = ~out_womask_166; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_129 = {hi_853, flags_0_go, _out_prepend_T_129}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2097 = out_prepend_129; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2098 = _out_T_2097; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_130 = _out_T_2098; // @[RegisterRouter.scala:87:24] wire out_rimask_167 = \|_out_rimask_T_167; // @[RegisterRouter.scala:87:24] wire out_wimask_167 = &_out_wimask_T_167; // @[RegisterRouter.scala:87:24] wire out_romask_167 = \|_out_romask_T_167; // @[RegisterRouter.scala:87:24] wire out_womask_167 = &_out_womask_T_167; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_167 = out_rivalid_1_21 & out_rimask_167; // @[RegisterRouter.scala:87:24] wire _out_T_2100 = out_f_rivalid_167; // @[RegisterRouter.scala:87:24] wire out_f_roready_167 = out_roready_1_21 & out_romask_167; // @[RegisterRouter.scala:87:24] wire _out_T_2101 = out_f_roready_167; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_167 = out_wivalid_1_21 & out_wimask_167; // @[RegisterRouter.scala:87:24] wire out_f_woready_167 = out_woready_1_21 & out_womask_167; // @[RegisterRouter.scala:87:24] wire _out_T_2102 = ~out_rimask_167; // @[RegisterRouter.scala:87:24] wire _out_T_2103 = ~out_wimask_167; // @[RegisterRouter.scala:87:24] wire _out_T_2104 = ~out_romask_167; // @[RegisterRouter.scala:87:24] wire _out_T_2105 = ~out_womask_167; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_130 = {hi_854, flags_0_go, _out_prepend_T_130}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2106 = out_prepend_130; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2107 = _out_T_2106; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_131 = _out_T_2107; // @[RegisterRouter.scala:87:24] wire out_rimask_168 = \|_out_rimask_T_168; // @[RegisterRouter.scala:87:24] wire out_wimask_168 = &_out_wimask_T_168; // @[RegisterRouter.scala:87:24] wire out_romask_168 = \|_out_romask_T_168; // @[RegisterRouter.scala:87:24] wire out_womask_168 = &_out_womask_T_168; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_168 = out_rivalid_1_22 & out_rimask_168; // @[RegisterRouter.scala:87:24] wire _out_T_2109 = out_f_rivalid_168; // @[RegisterRouter.scala:87:24] wire out_f_roready_168 = out_roready_1_22 & out_romask_168; // @[RegisterRouter.scala:87:24] wire _out_T_2110 = out_f_roready_168; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_168 = out_wivalid_1_22 & out_wimask_168; // @[RegisterRouter.scala:87:24] wire out_f_woready_168 = out_woready_1_22 & out_womask_168; // @[RegisterRouter.scala:87:24] wire _out_T_2111 = ~out_rimask_168; // @[RegisterRouter.scala:87:24] wire _out_T_2112 = ~out_wimask_168; // @[RegisterRouter.scala:87:24] wire _out_T_2113 = ~out_romask_168; // @[RegisterRouter.scala:87:24] wire _out_T_2114 = ~out_womask_168; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_131 = {hi_855, flags_0_go, _out_prepend_T_131}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2115 = out_prepend_131; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2116 = _out_T_2115; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_132 = _out_T_2116; // @[RegisterRouter.scala:87:24] wire out_rimask_169 = \|_out_rimask_T_169; // @[RegisterRouter.scala:87:24] wire out_wimask_169 = &_out_wimask_T_169; // @[RegisterRouter.scala:87:24] wire out_romask_169 = \|_out_romask_T_169; // @[RegisterRouter.scala:87:24] wire out_womask_169 = &_out_womask_T_169; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_169 = out_rivalid_1_23 & out_rimask_169; // @[RegisterRouter.scala:87:24] wire _out_T_2118 = out_f_rivalid_169; // @[RegisterRouter.scala:87:24] wire out_f_roready_169 = out_roready_1_23 & out_romask_169; // @[RegisterRouter.scala:87:24] wire _out_T_2119 = out_f_roready_169; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_169 = out_wivalid_1_23 & out_wimask_169; // @[RegisterRouter.scala:87:24] wire out_f_woready_169 = out_woready_1_23 & out_womask_169; // @[RegisterRouter.scala:87:24] wire _out_T_2120 = ~out_rimask_169; // @[RegisterRouter.scala:87:24] wire _out_T_2121 = ~out_wimask_169; // @[RegisterRouter.scala:87:24] wire _out_T_2122 = ~out_romask_169; // @[RegisterRouter.scala:87:24] wire _out_T_2123 = ~out_womask_169; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_132 = {hi_856, flags_0_go, _out_prepend_T_132}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2124 = out_prepend_132; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2125 = _out_T_2124; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_234 = _out_T_2125; // @[MuxLiteral.scala:49:48] wire out_rimask_170 = \|_out_rimask_T_170; // @[RegisterRouter.scala:87:24] wire out_wimask_170 = &_out_wimask_T_170; // @[RegisterRouter.scala:87:24] wire out_romask_170 = \|_out_romask_T_170; // @[RegisterRouter.scala:87:24] wire out_womask_170 = &_out_womask_T_170; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_170 = out_rivalid_1_24 & out_rimask_170; // @[RegisterRouter.scala:87:24] wire _out_T_2127 = out_f_rivalid_170; // @[RegisterRouter.scala:87:24] wire out_f_roready_170 = out_roready_1_24 & out_romask_170; // @[RegisterRouter.scala:87:24] wire _out_T_2128 = out_f_roready_170; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_170 = out_wivalid_1_24 & out_wimask_170; // @[RegisterRouter.scala:87:24] wire out_f_woready_170 = out_woready_1_24 & out_womask_170; // @[RegisterRouter.scala:87:24] wire _out_T_2129 = ~out_rimask_170; // @[RegisterRouter.scala:87:24] wire _out_T_2130 = ~out_wimask_170; // @[RegisterRouter.scala:87:24] wire _out_T_2131 = ~out_romask_170; // @[RegisterRouter.scala:87:24] wire _out_T_2132 = ~out_womask_170; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2134 = _out_T_2133; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_133 = _out_T_2134; // @[RegisterRouter.scala:87:24] wire out_rimask_171 = \|_out_rimask_T_171; // @[RegisterRouter.scala:87:24] wire out_wimask_171 = &_out_wimask_T_171; // @[RegisterRouter.scala:87:24] wire out_romask_171 = \|_out_romask_T_171; // @[RegisterRouter.scala:87:24] wire out_womask_171 = &_out_womask_T_171; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_171 = out_rivalid_1_25 & out_rimask_171; // @[RegisterRouter.scala:87:24] wire _out_T_2136 = out_f_rivalid_171; // @[RegisterRouter.scala:87:24] wire out_f_roready_171 = out_roready_1_25 & out_romask_171; // @[RegisterRouter.scala:87:24] wire _out_T_2137 = out_f_roready_171; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_171 = out_wivalid_1_25 & out_wimask_171; // @[RegisterRouter.scala:87:24] wire out_f_woready_171 = out_woready_1_25 & out_womask_171; // @[RegisterRouter.scala:87:24] wire _out_T_2138 = ~out_rimask_171; // @[RegisterRouter.scala:87:24] wire _out_T_2139 = ~out_wimask_171; // @[RegisterRouter.scala:87:24] wire _out_T_2140 = ~out_romask_171; // @[RegisterRouter.scala:87:24] wire _out_T_2141 = ~out_womask_171; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_133 = {hi_338, flags_0_go, _out_prepend_T_133}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2142 = out_prepend_133; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2143 = _out_T_2142; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_134 = _out_T_2143; // @[RegisterRouter.scala:87:24] wire out_rimask_172 = \|_out_rimask_T_172; // @[RegisterRouter.scala:87:24] wire out_wimask_172 = &_out_wimask_T_172; // @[RegisterRouter.scala:87:24] wire out_romask_172 = \|_out_romask_T_172; // @[RegisterRouter.scala:87:24] wire out_womask_172 = &_out_womask_T_172; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_172 = out_rivalid_1_26 & out_rimask_172; // @[RegisterRouter.scala:87:24] wire _out_T_2145 = out_f_rivalid_172; // @[RegisterRouter.scala:87:24] wire out_f_roready_172 = out_roready_1_26 & out_romask_172; // @[RegisterRouter.scala:87:24] wire _out_T_2146 = out_f_roready_172; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_172 = out_wivalid_1_26 & out_wimask_172; // @[RegisterRouter.scala:87:24] wire out_f_woready_172 = out_woready_1_26 & out_womask_172; // @[RegisterRouter.scala:87:24] wire _out_T_2147 = ~out_rimask_172; // @[RegisterRouter.scala:87:24] wire _out_T_2148 = ~out_wimask_172; // @[RegisterRouter.scala:87:24] wire _out_T_2149 = ~out_romask_172; // @[RegisterRouter.scala:87:24] wire _out_T_2150 = ~out_womask_172; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_134 = {hi_339, flags_0_go, _out_prepend_T_134}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2151 = out_prepend_134; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2152 = _out_T_2151; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_135 = _out_T_2152; // @[RegisterRouter.scala:87:24] wire out_rimask_173 = \|_out_rimask_T_173; // @[RegisterRouter.scala:87:24] wire out_wimask_173 = &_out_wimask_T_173; // @[RegisterRouter.scala:87:24] wire out_romask_173 = \|_out_romask_T_173; // @[RegisterRouter.scala:87:24] wire out_womask_173 = &_out_womask_T_173; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_173 = out_rivalid_1_27 & out_rimask_173; // @[RegisterRouter.scala:87:24] wire _out_T_2154 = out_f_rivalid_173; // @[RegisterRouter.scala:87:24] wire out_f_roready_173 = out_roready_1_27 & out_romask_173; // @[RegisterRouter.scala:87:24] wire _out_T_2155 = out_f_roready_173; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_173 = out_wivalid_1_27 & out_wimask_173; // @[RegisterRouter.scala:87:24] wire out_f_woready_173 = out_woready_1_27 & out_womask_173; // @[RegisterRouter.scala:87:24] wire _out_T_2156 = ~out_rimask_173; // @[RegisterRouter.scala:87:24] wire _out_T_2157 = ~out_wimask_173; // @[RegisterRouter.scala:87:24] wire _out_T_2158 = ~out_romask_173; // @[RegisterRouter.scala:87:24] wire _out_T_2159 = ~out_womask_173; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_135 = {hi_340, flags_0_go, _out_prepend_T_135}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2160 = out_prepend_135; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2161 = _out_T_2160; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_136 = _out_T_2161; // @[RegisterRouter.scala:87:24] wire out_rimask_174 = \|_out_rimask_T_174; // @[RegisterRouter.scala:87:24] wire out_wimask_174 = &_out_wimask_T_174; // @[RegisterRouter.scala:87:24] wire out_romask_174 = \|_out_romask_T_174; // @[RegisterRouter.scala:87:24] wire out_womask_174 = &_out_womask_T_174; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_174 = out_rivalid_1_28 & out_rimask_174; // @[RegisterRouter.scala:87:24] wire _out_T_2163 = out_f_rivalid_174; // @[RegisterRouter.scala:87:24] wire out_f_roready_174 = out_roready_1_28 & out_romask_174; // @[RegisterRouter.scala:87:24] wire _out_T_2164 = out_f_roready_174; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_174 = out_wivalid_1_28 & out_wimask_174; // @[RegisterRouter.scala:87:24] wire out_f_woready_174 = out_woready_1_28 & out_womask_174; // @[RegisterRouter.scala:87:24] wire _out_T_2165 = ~out_rimask_174; // @[RegisterRouter.scala:87:24] wire _out_T_2166 = ~out_wimask_174; // @[RegisterRouter.scala:87:24] wire _out_T_2167 = ~out_romask_174; // @[RegisterRouter.scala:87:24] wire _out_T_2168 = ~out_womask_174; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_136 = {hi_341, flags_0_go, _out_prepend_T_136}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2169 = out_prepend_136; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2170 = _out_T_2169; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_137 = _out_T_2170; // @[RegisterRouter.scala:87:24] wire out_rimask_175 = \|_out_rimask_T_175; // @[RegisterRouter.scala:87:24] wire out_wimask_175 = &_out_wimask_T_175; // @[RegisterRouter.scala:87:24] wire out_romask_175 = \|_out_romask_T_175; // @[RegisterRouter.scala:87:24] wire out_womask_175 = &_out_womask_T_175; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_175 = out_rivalid_1_29 & out_rimask_175; // @[RegisterRouter.scala:87:24] wire _out_T_2172 = out_f_rivalid_175; // @[RegisterRouter.scala:87:24] wire out_f_roready_175 = out_roready_1_29 & out_romask_175; // @[RegisterRouter.scala:87:24] wire _out_T_2173 = out_f_roready_175; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_175 = out_wivalid_1_29 & out_wimask_175; // @[RegisterRouter.scala:87:24] wire out_f_woready_175 = out_woready_1_29 & out_womask_175; // @[RegisterRouter.scala:87:24] wire _out_T_2174 = ~out_rimask_175; // @[RegisterRouter.scala:87:24] wire _out_T_2175 = ~out_wimask_175; // @[RegisterRouter.scala:87:24] wire _out_T_2176 = ~out_romask_175; // @[RegisterRouter.scala:87:24] wire _out_T_2177 = ~out_womask_175; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_137 = {hi_342, flags_0_go, _out_prepend_T_137}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2178 = out_prepend_137; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2179 = _out_T_2178; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_138 = _out_T_2179; // @[RegisterRouter.scala:87:24] wire out_rimask_176 = \|_out_rimask_T_176; // @[RegisterRouter.scala:87:24] wire out_wimask_176 = &_out_wimask_T_176; // @[RegisterRouter.scala:87:24] wire out_romask_176 = \|_out_romask_T_176; // @[RegisterRouter.scala:87:24] wire out_womask_176 = &_out_womask_T_176; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_176 = out_rivalid_1_30 & out_rimask_176; // @[RegisterRouter.scala:87:24] wire _out_T_2181 = out_f_rivalid_176; // @[RegisterRouter.scala:87:24] wire out_f_roready_176 = out_roready_1_30 & out_romask_176; // @[RegisterRouter.scala:87:24] wire _out_T_2182 = out_f_roready_176; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_176 = out_wivalid_1_30 & out_wimask_176; // @[RegisterRouter.scala:87:24] wire out_f_woready_176 = out_woready_1_30 & out_womask_176; // @[RegisterRouter.scala:87:24] wire _out_T_2183 = ~out_rimask_176; // @[RegisterRouter.scala:87:24] wire _out_T_2184 = ~out_wimask_176; // @[RegisterRouter.scala:87:24] wire _out_T_2185 = ~out_romask_176; // @[RegisterRouter.scala:87:24] wire _out_T_2186 = ~out_womask_176; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_138 = {hi_343, flags_0_go, _out_prepend_T_138}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2187 = out_prepend_138; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2188 = _out_T_2187; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_139 = _out_T_2188; // @[RegisterRouter.scala:87:24] wire out_rimask_177 = \|_out_rimask_T_177; // @[RegisterRouter.scala:87:24] wire out_wimask_177 = &_out_wimask_T_177; // @[RegisterRouter.scala:87:24] wire out_romask_177 = \|_out_romask_T_177; // @[RegisterRouter.scala:87:24] wire out_womask_177 = &_out_womask_T_177; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_177 = out_rivalid_1_31 & out_rimask_177; // @[RegisterRouter.scala:87:24] wire _out_T_2190 = out_f_rivalid_177; // @[RegisterRouter.scala:87:24] wire out_f_roready_177 = out_roready_1_31 & out_romask_177; // @[RegisterRouter.scala:87:24] wire _out_T_2191 = out_f_roready_177; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_177 = out_wivalid_1_31 & out_wimask_177; // @[RegisterRouter.scala:87:24] wire out_f_woready_177 = out_woready_1_31 & out_womask_177; // @[RegisterRouter.scala:87:24] wire _out_T_2192 = ~out_rimask_177; // @[RegisterRouter.scala:87:24] wire _out_T_2193 = ~out_wimask_177; // @[RegisterRouter.scala:87:24] wire _out_T_2194 = ~out_romask_177; // @[RegisterRouter.scala:87:24] wire _out_T_2195 = ~out_womask_177; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_139 = {hi_344, flags_0_go, _out_prepend_T_139}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2196 = out_prepend_139; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2197 = _out_T_2196; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_170 = _out_T_2197; // @[MuxLiteral.scala:49:48] wire out_rimask_178 = \|_out_rimask_T_178; // @[RegisterRouter.scala:87:24] wire out_wimask_178 = &_out_wimask_T_178; // @[RegisterRouter.scala:87:24] wire out_romask_178 = \|_out_romask_T_178; // @[RegisterRouter.scala:87:24] wire out_womask_178 = &_out_womask_T_178; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_178 = out_rivalid_1_32 & out_rimask_178; // @[RegisterRouter.scala:87:24] wire _out_T_2199 = out_f_rivalid_178; // @[RegisterRouter.scala:87:24] wire out_f_roready_178 = out_roready_1_32 & out_romask_178; // @[RegisterRouter.scala:87:24] wire _out_T_2200 = out_f_roready_178; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_178 = out_wivalid_1_32 & out_wimask_178; // @[RegisterRouter.scala:87:24] wire _out_T_2201 = out_f_wivalid_178; // @[RegisterRouter.scala:87:24] wire out_f_woready_178 = out_woready_1_32 & out_womask_178; // @[RegisterRouter.scala:87:24] wire _out_T_2202 = out_f_woready_178; // @[RegisterRouter.scala:87:24] wire _out_T_2203 = ~out_rimask_178; // @[RegisterRouter.scala:87:24] wire _out_T_2204 = ~out_wimask_178; // @[RegisterRouter.scala:87:24] wire _out_T_2205 = ~out_romask_178; // @[RegisterRouter.scala:87:24] wire _out_T_2206 = ~out_womask_178; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2208 = _out_T_2207; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_140 = _out_T_2208; // @[RegisterRouter.scala:87:24] wire out_rimask_179 = \|_out_rimask_T_179; // @[RegisterRouter.scala:87:24] wire out_wimask_179 = &_out_wimask_T_179; // @[RegisterRouter.scala:87:24] wire out_romask_179 = \|_out_romask_T_179; // @[RegisterRouter.scala:87:24] wire out_womask_179 = &_out_womask_T_179; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_179 = out_rivalid_1_33 & out_rimask_179; // @[RegisterRouter.scala:87:24] wire _out_T_2210 = out_f_rivalid_179; // @[RegisterRouter.scala:87:24] wire out_f_roready_179 = out_roready_1_33 & out_romask_179; // @[RegisterRouter.scala:87:24] wire _out_T_2211 = out_f_roready_179; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_179 = out_wivalid_1_33 & out_wimask_179; // @[RegisterRouter.scala:87:24] wire _out_T_2212 = out_f_wivalid_179; // @[RegisterRouter.scala:87:24] wire out_f_woready_179 = out_woready_1_33 & out_womask_179; // @[RegisterRouter.scala:87:24] wire _out_T_2213 = out_f_woready_179; // @[RegisterRouter.scala:87:24] wire _out_T_2214 = ~out_rimask_179; // @[RegisterRouter.scala:87:24] wire _out_T_2215 = ~out_wimask_179; // @[RegisterRouter.scala:87:24] wire _out_T_2216 = ~out_romask_179; // @[RegisterRouter.scala:87:24] wire _out_T_2217 = ~out_womask_179; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_140 = {abstractDataMem_25, _out_prepend_T_140}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2218 = out_prepend_140; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2219 = _out_T_2218; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_141 = _out_T_2219; // @[RegisterRouter.scala:87:24] wire out_rimask_180 = \|_out_rimask_T_180; // @[RegisterRouter.scala:87:24] wire out_wimask_180 = &_out_wimask_T_180; // @[RegisterRouter.scala:87:24] wire out_romask_180 = \|_out_romask_T_180; // @[RegisterRouter.scala:87:24] wire out_womask_180 = &_out_womask_T_180; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_180 = out_rivalid_1_34 & out_rimask_180; // @[RegisterRouter.scala:87:24] wire _out_T_2221 = out_f_rivalid_180; // @[RegisterRouter.scala:87:24] wire out_f_roready_180 = out_roready_1_34 & out_romask_180; // @[RegisterRouter.scala:87:24] wire _out_T_2222 = out_f_roready_180; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_180 = out_wivalid_1_34 & out_wimask_180; // @[RegisterRouter.scala:87:24] wire _out_T_2223 = out_f_wivalid_180; // @[RegisterRouter.scala:87:24] wire out_f_woready_180 = out_woready_1_34 & out_womask_180; // @[RegisterRouter.scala:87:24] wire _out_T_2224 = out_f_woready_180; // @[RegisterRouter.scala:87:24] wire _out_T_2225 = ~out_rimask_180; // @[RegisterRouter.scala:87:24] wire _out_T_2226 = ~out_wimask_180; // @[RegisterRouter.scala:87:24] wire _out_T_2227 = ~out_romask_180; // @[RegisterRouter.scala:87:24] wire _out_T_2228 = ~out_womask_180; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_141 = {abstractDataMem_26, _out_prepend_T_141}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2229 = out_prepend_141; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2230 = _out_T_2229; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_142 = _out_T_2230; // @[RegisterRouter.scala:87:24] wire out_rimask_181 = \|_out_rimask_T_181; // @[RegisterRouter.scala:87:24] wire out_wimask_181 = &_out_wimask_T_181; // @[RegisterRouter.scala:87:24] wire out_romask_181 = \|_out_romask_T_181; // @[RegisterRouter.scala:87:24] wire out_womask_181 = &_out_womask_T_181; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_181 = out_rivalid_1_35 & out_rimask_181; // @[RegisterRouter.scala:87:24] wire _out_T_2232 = out_f_rivalid_181; // @[RegisterRouter.scala:87:24] wire out_f_roready_181 = out_roready_1_35 & out_romask_181; // @[RegisterRouter.scala:87:24] wire _out_T_2233 = out_f_roready_181; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_181 = out_wivalid_1_35 & out_wimask_181; // @[RegisterRouter.scala:87:24] wire _out_T_2234 = out_f_wivalid_181; // @[RegisterRouter.scala:87:24] wire out_f_woready_181 = out_woready_1_35 & out_womask_181; // @[RegisterRouter.scala:87:24] wire _out_T_2235 = out_f_woready_181; // @[RegisterRouter.scala:87:24] wire _out_T_2236 = ~out_rimask_181; // @[RegisterRouter.scala:87:24] wire _out_T_2237 = ~out_wimask_181; // @[RegisterRouter.scala:87:24] wire _out_T_2238 = ~out_romask_181; // @[RegisterRouter.scala:87:24] wire _out_T_2239 = ~out_womask_181; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_142 = {abstractDataMem_27, _out_prepend_T_142}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2240 = out_prepend_142; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2241 = _out_T_2240; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_143 = _out_T_2241; // @[RegisterRouter.scala:87:24] wire out_rimask_182 = \|_out_rimask_T_182; // @[RegisterRouter.scala:87:24] wire out_wimask_182 = &_out_wimask_T_182; // @[RegisterRouter.scala:87:24] wire out_romask_182 = \|_out_romask_T_182; // @[RegisterRouter.scala:87:24] wire out_womask_182 = &_out_womask_T_182; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_182 = out_rivalid_1_36 & out_rimask_182; // @[RegisterRouter.scala:87:24] wire _out_T_2243 = out_f_rivalid_182; // @[RegisterRouter.scala:87:24] wire out_f_roready_182 = out_roready_1_36 & out_romask_182; // @[RegisterRouter.scala:87:24] wire _out_T_2244 = out_f_roready_182; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_182 = out_wivalid_1_36 & out_wimask_182; // @[RegisterRouter.scala:87:24] wire _out_T_2245 = out_f_wivalid_182; // @[RegisterRouter.scala:87:24] wire out_f_woready_182 = out_woready_1_36 & out_womask_182; // @[RegisterRouter.scala:87:24] wire _out_T_2246 = out_f_woready_182; // @[RegisterRouter.scala:87:24] wire _out_T_2247 = ~out_rimask_182; // @[RegisterRouter.scala:87:24] wire _out_T_2248 = ~out_wimask_182; // @[RegisterRouter.scala:87:24] wire _out_T_2249 = ~out_romask_182; // @[RegisterRouter.scala:87:24] wire _out_T_2250 = ~out_womask_182; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_143 = {abstractDataMem_28, _out_prepend_T_143}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2251 = out_prepend_143; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2252 = _out_T_2251; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_144 = _out_T_2252; // @[RegisterRouter.scala:87:24] wire out_rimask_183 = \|_out_rimask_T_183; // @[RegisterRouter.scala:87:24] wire out_wimask_183 = &_out_wimask_T_183; // @[RegisterRouter.scala:87:24] wire out_romask_183 = \|_out_romask_T_183; // @[RegisterRouter.scala:87:24] wire out_womask_183 = &_out_womask_T_183; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_183 = out_rivalid_1_37 & out_rimask_183; // @[RegisterRouter.scala:87:24] wire _out_T_2254 = out_f_rivalid_183; // @[RegisterRouter.scala:87:24] wire out_f_roready_183 = out_roready_1_37 & out_romask_183; // @[RegisterRouter.scala:87:24] wire _out_T_2255 = out_f_roready_183; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_183 = out_wivalid_1_37 & out_wimask_183; // @[RegisterRouter.scala:87:24] wire _out_T_2256 = out_f_wivalid_183; // @[RegisterRouter.scala:87:24] wire out_f_woready_183 = out_woready_1_37 & out_womask_183; // @[RegisterRouter.scala:87:24] wire _out_T_2257 = out_f_woready_183; // @[RegisterRouter.scala:87:24] wire _out_T_2258 = ~out_rimask_183; // @[RegisterRouter.scala:87:24] wire _out_T_2259 = ~out_wimask_183; // @[RegisterRouter.scala:87:24] wire _out_T_2260 = ~out_romask_183; // @[RegisterRouter.scala:87:24] wire _out_T_2261 = ~out_womask_183; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_144 = {abstractDataMem_29, _out_prepend_T_144}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2262 = out_prepend_144; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2263 = _out_T_2262; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_145 = _out_T_2263; // @[RegisterRouter.scala:87:24] wire out_rimask_184 = \|_out_rimask_T_184; // @[RegisterRouter.scala:87:24] wire out_wimask_184 = &_out_wimask_T_184; // @[RegisterRouter.scala:87:24] wire out_romask_184 = \|_out_romask_T_184; // @[RegisterRouter.scala:87:24] wire out_womask_184 = &_out_womask_T_184; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_184 = out_rivalid_1_38 & out_rimask_184; // @[RegisterRouter.scala:87:24] wire _out_T_2265 = out_f_rivalid_184; // @[RegisterRouter.scala:87:24] wire out_f_roready_184 = out_roready_1_38 & out_romask_184; // @[RegisterRouter.scala:87:24] wire _out_T_2266 = out_f_roready_184; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_184 = out_wivalid_1_38 & out_wimask_184; // @[RegisterRouter.scala:87:24] wire _out_T_2267 = out_f_wivalid_184; // @[RegisterRouter.scala:87:24] wire out_f_woready_184 = out_woready_1_38 & out_womask_184; // @[RegisterRouter.scala:87:24] wire _out_T_2268 = out_f_woready_184; // @[RegisterRouter.scala:87:24] wire _out_T_2269 = ~out_rimask_184; // @[RegisterRouter.scala:87:24] wire _out_T_2270 = ~out_wimask_184; // @[RegisterRouter.scala:87:24] wire _out_T_2271 = ~out_romask_184; // @[RegisterRouter.scala:87:24] wire _out_T_2272 = ~out_womask_184; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_145 = {abstractDataMem_30, _out_prepend_T_145}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2273 = out_prepend_145; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2274 = _out_T_2273; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_146 = _out_T_2274; // @[RegisterRouter.scala:87:24] wire out_rimask_185 = \|_out_rimask_T_185; // @[RegisterRouter.scala:87:24] wire out_wimask_185 = &_out_wimask_T_185; // @[RegisterRouter.scala:87:24] wire out_romask_185 = \|_out_romask_T_185; // @[RegisterRouter.scala:87:24] wire out_womask_185 = &_out_womask_T_185; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_185 = out_rivalid_1_39 & out_rimask_185; // @[RegisterRouter.scala:87:24] wire _out_T_2276 = out_f_rivalid_185; // @[RegisterRouter.scala:87:24] wire out_f_roready_185 = out_roready_1_39 & out_romask_185; // @[RegisterRouter.scala:87:24] wire _out_T_2277 = out_f_roready_185; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_185 = out_wivalid_1_39 & out_wimask_185; // @[RegisterRouter.scala:87:24] wire _out_T_2278 = out_f_wivalid_185; // @[RegisterRouter.scala:87:24] wire out_f_woready_185 = out_woready_1_39 & out_womask_185; // @[RegisterRouter.scala:87:24] wire _out_T_2279 = out_f_woready_185; // @[RegisterRouter.scala:87:24] wire _out_T_2280 = ~out_rimask_185; // @[RegisterRouter.scala:87:24] wire _out_T_2281 = ~out_wimask_185; // @[RegisterRouter.scala:87:24] wire _out_T_2282 = ~out_romask_185; // @[RegisterRouter.scala:87:24] wire _out_T_2283 = ~out_womask_185; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_146 = {abstractDataMem_31, _out_prepend_T_146}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2284 = out_prepend_146; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2285 = _out_T_2284; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_115 = _out_T_2285; // @[MuxLiteral.scala:49:48] wire out_rimask_186 = \|_out_rimask_T_186; // @[RegisterRouter.scala:87:24] wire out_wimask_186 = &_out_wimask_T_186; // @[RegisterRouter.scala:87:24] wire out_romask_186 = \|_out_romask_T_186; // @[RegisterRouter.scala:87:24] wire out_womask_186 = &_out_womask_T_186; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_186 = out_rivalid_1_40 & out_rimask_186; // @[RegisterRouter.scala:87:24] wire _out_T_2287 = out_f_rivalid_186; // @[RegisterRouter.scala:87:24] wire out_f_roready_186 = out_roready_1_40 & out_romask_186; // @[RegisterRouter.scala:87:24] wire _out_T_2288 = out_f_roready_186; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_186 = out_wivalid_1_40 & out_wimask_186; // @[RegisterRouter.scala:87:24] wire out_f_woready_186 = out_woready_1_40 & out_womask_186; // @[RegisterRouter.scala:87:24] wire _out_T_2289 = ~out_rimask_186; // @[RegisterRouter.scala:87:24] wire _out_T_2290 = ~out_wimask_186; // @[RegisterRouter.scala:87:24] wire _out_T_2291 = ~out_romask_186; // @[RegisterRouter.scala:87:24] wire _out_T_2292 = ~out_womask_186; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2294 = _out_T_2293; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_147 = _out_T_2294; // @[RegisterRouter.scala:87:24] wire out_rimask_187 = \|_out_rimask_T_187; // @[RegisterRouter.scala:87:24] wire out_wimask_187 = &_out_wimask_T_187; // @[RegisterRouter.scala:87:24] wire out_romask_187 = \|_out_romask_T_187; // @[RegisterRouter.scala:87:24] wire out_womask_187 = &_out_womask_T_187; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_187 = out_rivalid_1_41 & out_rimask_187; // @[RegisterRouter.scala:87:24] wire _out_T_2296 = out_f_rivalid_187; // @[RegisterRouter.scala:87:24] wire out_f_roready_187 = out_roready_1_41 & out_romask_187; // @[RegisterRouter.scala:87:24] wire _out_T_2297 = out_f_roready_187; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_187 = out_wivalid_1_41 & out_wimask_187; // @[RegisterRouter.scala:87:24] wire out_f_woready_187 = out_woready_1_41 & out_womask_187; // @[RegisterRouter.scala:87:24] wire _out_T_2298 = ~out_rimask_187; // @[RegisterRouter.scala:87:24] wire _out_T_2299 = ~out_wimask_187; // @[RegisterRouter.scala:87:24] wire _out_T_2300 = ~out_romask_187; // @[RegisterRouter.scala:87:24] wire _out_T_2301 = ~out_womask_187; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_147 = {hi_714, flags_0_go, _out_prepend_T_147}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2302 = out_prepend_147; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2303 = _out_T_2302; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_148 = _out_T_2303; // @[RegisterRouter.scala:87:24] wire out_rimask_188 = \|_out_rimask_T_188; // @[RegisterRouter.scala:87:24] wire out_wimask_188 = &_out_wimask_T_188; // @[RegisterRouter.scala:87:24] wire out_romask_188 = \|_out_romask_T_188; // @[RegisterRouter.scala:87:24] wire out_womask_188 = &_out_womask_T_188; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_188 = out_rivalid_1_42 & out_rimask_188; // @[RegisterRouter.scala:87:24] wire _out_T_2305 = out_f_rivalid_188; // @[RegisterRouter.scala:87:24] wire out_f_roready_188 = out_roready_1_42 & out_romask_188; // @[RegisterRouter.scala:87:24] wire _out_T_2306 = out_f_roready_188; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_188 = out_wivalid_1_42 & out_wimask_188; // @[RegisterRouter.scala:87:24] wire out_f_woready_188 = out_woready_1_42 & out_womask_188; // @[RegisterRouter.scala:87:24] wire _out_T_2307 = ~out_rimask_188; // @[RegisterRouter.scala:87:24] wire _out_T_2308 = ~out_wimask_188; // @[RegisterRouter.scala:87:24] wire _out_T_2309 = ~out_romask_188; // @[RegisterRouter.scala:87:24] wire _out_T_2310 = ~out_womask_188; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_148 = {hi_715, flags_0_go, _out_prepend_T_148}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2311 = out_prepend_148; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2312 = _out_T_2311; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_149 = _out_T_2312; // @[RegisterRouter.scala:87:24] wire out_rimask_189 = \|_out_rimask_T_189; // @[RegisterRouter.scala:87:24] wire out_wimask_189 = &_out_wimask_T_189; // @[RegisterRouter.scala:87:24] wire out_romask_189 = \|_out_romask_T_189; // @[RegisterRouter.scala:87:24] wire out_womask_189 = &_out_womask_T_189; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_189 = out_rivalid_1_43 & out_rimask_189; // @[RegisterRouter.scala:87:24] wire _out_T_2314 = out_f_rivalid_189; // @[RegisterRouter.scala:87:24] wire out_f_roready_189 = out_roready_1_43 & out_romask_189; // @[RegisterRouter.scala:87:24] wire _out_T_2315 = out_f_roready_189; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_189 = out_wivalid_1_43 & out_wimask_189; // @[RegisterRouter.scala:87:24] wire out_f_woready_189 = out_woready_1_43 & out_womask_189; // @[RegisterRouter.scala:87:24] wire _out_T_2316 = ~out_rimask_189; // @[RegisterRouter.scala:87:24] wire _out_T_2317 = ~out_wimask_189; // @[RegisterRouter.scala:87:24] wire _out_T_2318 = ~out_romask_189; // @[RegisterRouter.scala:87:24] wire _out_T_2319 = ~out_womask_189; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_149 = {hi_716, flags_0_go, _out_prepend_T_149}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2320 = out_prepend_149; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2321 = _out_T_2320; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_150 = _out_T_2321; // @[RegisterRouter.scala:87:24] wire out_rimask_190 = \|_out_rimask_T_190; // @[RegisterRouter.scala:87:24] wire out_wimask_190 = &_out_wimask_T_190; // @[RegisterRouter.scala:87:24] wire out_romask_190 = \|_out_romask_T_190; // @[RegisterRouter.scala:87:24] wire out_womask_190 = &_out_womask_T_190; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_190 = out_rivalid_1_44 & out_rimask_190; // @[RegisterRouter.scala:87:24] wire _out_T_2323 = out_f_rivalid_190; // @[RegisterRouter.scala:87:24] wire out_f_roready_190 = out_roready_1_44 & out_romask_190; // @[RegisterRouter.scala:87:24] wire _out_T_2324 = out_f_roready_190; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_190 = out_wivalid_1_44 & out_wimask_190; // @[RegisterRouter.scala:87:24] wire out_f_woready_190 = out_woready_1_44 & out_womask_190; // @[RegisterRouter.scala:87:24] wire _out_T_2325 = ~out_rimask_190; // @[RegisterRouter.scala:87:24] wire _out_T_2326 = ~out_wimask_190; // @[RegisterRouter.scala:87:24] wire _out_T_2327 = ~out_romask_190; // @[RegisterRouter.scala:87:24] wire _out_T_2328 = ~out_womask_190; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_150 = {hi_717, flags_0_go, _out_prepend_T_150}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2329 = out_prepend_150; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2330 = _out_T_2329; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_151 = _out_T_2330; // @[RegisterRouter.scala:87:24] wire out_rimask_191 = \|_out_rimask_T_191; // @[RegisterRouter.scala:87:24] wire out_wimask_191 = &_out_wimask_T_191; // @[RegisterRouter.scala:87:24] wire out_romask_191 = \|_out_romask_T_191; // @[RegisterRouter.scala:87:24] wire out_womask_191 = &_out_womask_T_191; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_191 = out_rivalid_1_45 & out_rimask_191; // @[RegisterRouter.scala:87:24] wire _out_T_2332 = out_f_rivalid_191; // @[RegisterRouter.scala:87:24] wire out_f_roready_191 = out_roready_1_45 & out_romask_191; // @[RegisterRouter.scala:87:24] wire _out_T_2333 = out_f_roready_191; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_191 = out_wivalid_1_45 & out_wimask_191; // @[RegisterRouter.scala:87:24] wire out_f_woready_191 = out_woready_1_45 & out_womask_191; // @[RegisterRouter.scala:87:24] wire _out_T_2334 = ~out_rimask_191; // @[RegisterRouter.scala:87:24] wire _out_T_2335 = ~out_wimask_191; // @[RegisterRouter.scala:87:24] wire _out_T_2336 = ~out_romask_191; // @[RegisterRouter.scala:87:24] wire _out_T_2337 = ~out_womask_191; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_151 = {hi_718, flags_0_go, _out_prepend_T_151}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2338 = out_prepend_151; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2339 = _out_T_2338; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_152 = _out_T_2339; // @[RegisterRouter.scala:87:24] wire out_rimask_192 = \|_out_rimask_T_192; // @[RegisterRouter.scala:87:24] wire out_wimask_192 = &_out_wimask_T_192; // @[RegisterRouter.scala:87:24] wire out_romask_192 = \|_out_romask_T_192; // @[RegisterRouter.scala:87:24] wire out_womask_192 = &_out_womask_T_192; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_192 = out_rivalid_1_46 & out_rimask_192; // @[RegisterRouter.scala:87:24] wire _out_T_2341 = out_f_rivalid_192; // @[RegisterRouter.scala:87:24] wire out_f_roready_192 = out_roready_1_46 & out_romask_192; // @[RegisterRouter.scala:87:24] wire _out_T_2342 = out_f_roready_192; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_192 = out_wivalid_1_46 & out_wimask_192; // @[RegisterRouter.scala:87:24] wire out_f_woready_192 = out_woready_1_46 & out_womask_192; // @[RegisterRouter.scala:87:24] wire _out_T_2343 = ~out_rimask_192; // @[RegisterRouter.scala:87:24] wire _out_T_2344 = ~out_wimask_192; // @[RegisterRouter.scala:87:24] wire _out_T_2345 = ~out_romask_192; // @[RegisterRouter.scala:87:24] wire _out_T_2346 = ~out_womask_192; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_152 = {hi_719, flags_0_go, _out_prepend_T_152}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2347 = out_prepend_152; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2348 = _out_T_2347; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_153 = _out_T_2348; // @[RegisterRouter.scala:87:24] wire out_rimask_193 = \|_out_rimask_T_193; // @[RegisterRouter.scala:87:24] wire out_wimask_193 = &_out_wimask_T_193; // @[RegisterRouter.scala:87:24] wire out_romask_193 = \|_out_romask_T_193; // @[RegisterRouter.scala:87:24] wire out_womask_193 = &_out_womask_T_193; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_193 = out_rivalid_1_47 & out_rimask_193; // @[RegisterRouter.scala:87:24] wire _out_T_2350 = out_f_rivalid_193; // @[RegisterRouter.scala:87:24] wire out_f_roready_193 = out_roready_1_47 & out_romask_193; // @[RegisterRouter.scala:87:24] wire _out_T_2351 = out_f_roready_193; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_193 = out_wivalid_1_47 & out_wimask_193; // @[RegisterRouter.scala:87:24] wire out_f_woready_193 = out_woready_1_47 & out_womask_193; // @[RegisterRouter.scala:87:24] wire _out_T_2352 = ~out_rimask_193; // @[RegisterRouter.scala:87:24] wire _out_T_2353 = ~out_wimask_193; // @[RegisterRouter.scala:87:24] wire _out_T_2354 = ~out_romask_193; // @[RegisterRouter.scala:87:24] wire _out_T_2355 = ~out_womask_193; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_153 = {hi_720, flags_0_go, _out_prepend_T_153}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2356 = out_prepend_153; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2357 = _out_T_2356; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_217 = _out_T_2357; // @[MuxLiteral.scala:49:48] wire out_rimask_194 = \|_out_rimask_T_194; // @[RegisterRouter.scala:87:24] wire out_wimask_194 = &_out_wimask_T_194; // @[RegisterRouter.scala:87:24] wire out_romask_194 = \|_out_romask_T_194; // @[RegisterRouter.scala:87:24] wire out_womask_194 = &_out_womask_T_194; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_194 = out_rivalid_1_48 & out_rimask_194; // @[RegisterRouter.scala:87:24] wire _out_T_2359 = out_f_rivalid_194; // @[RegisterRouter.scala:87:24] wire out_f_roready_194 = out_roready_1_48 & out_romask_194; // @[RegisterRouter.scala:87:24] wire _out_T_2360 = out_f_roready_194; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_194 = out_wivalid_1_48 & out_wimask_194; // @[RegisterRouter.scala:87:24] wire out_f_woready_194 = out_woready_1_48 & out_womask_194; // @[RegisterRouter.scala:87:24] wire _out_T_2361 = ~out_rimask_194; // @[RegisterRouter.scala:87:24] wire _out_T_2362 = ~out_wimask_194; // @[RegisterRouter.scala:87:24] wire _out_T_2363 = ~out_romask_194; // @[RegisterRouter.scala:87:24] wire _out_T_2364 = ~out_womask_194; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2366 = _out_T_2365; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_154 = _out_T_2366; // @[RegisterRouter.scala:87:24] wire out_rimask_195 = \|_out_rimask_T_195; // @[RegisterRouter.scala:87:24] wire out_wimask_195 = &_out_wimask_T_195; // @[RegisterRouter.scala:87:24] wire out_romask_195 = \|_out_romask_T_195; // @[RegisterRouter.scala:87:24] wire out_womask_195 = &_out_womask_T_195; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_195 = out_rivalid_1_49 & out_rimask_195; // @[RegisterRouter.scala:87:24] wire _out_T_2368 = out_f_rivalid_195; // @[RegisterRouter.scala:87:24] wire out_f_roready_195 = out_roready_1_49 & out_romask_195; // @[RegisterRouter.scala:87:24] wire _out_T_2369 = out_f_roready_195; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_195 = out_wivalid_1_49 & out_wimask_195; // @[RegisterRouter.scala:87:24] wire out_f_woready_195 = out_woready_1_49 & out_womask_195; // @[RegisterRouter.scala:87:24] wire _out_T_2370 = ~out_rimask_195; // @[RegisterRouter.scala:87:24] wire _out_T_2371 = ~out_wimask_195; // @[RegisterRouter.scala:87:24] wire _out_T_2372 = ~out_romask_195; // @[RegisterRouter.scala:87:24] wire _out_T_2373 = ~out_womask_195; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_154 = {hi_954, flags_0_go, _out_prepend_T_154}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2374 = out_prepend_154; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2375 = _out_T_2374; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_155 = _out_T_2375; // @[RegisterRouter.scala:87:24] wire out_rimask_196 = \|_out_rimask_T_196; // @[RegisterRouter.scala:87:24] wire out_wimask_196 = &_out_wimask_T_196; // @[RegisterRouter.scala:87:24] wire out_romask_196 = \|_out_romask_T_196; // @[RegisterRouter.scala:87:24] wire out_womask_196 = &_out_womask_T_196; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_196 = out_rivalid_1_50 & out_rimask_196; // @[RegisterRouter.scala:87:24] wire _out_T_2377 = out_f_rivalid_196; // @[RegisterRouter.scala:87:24] wire out_f_roready_196 = out_roready_1_50 & out_romask_196; // @[RegisterRouter.scala:87:24] wire _out_T_2378 = out_f_roready_196; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_196 = out_wivalid_1_50 & out_wimask_196; // @[RegisterRouter.scala:87:24] wire out_f_woready_196 = out_woready_1_50 & out_womask_196; // @[RegisterRouter.scala:87:24] wire _out_T_2379 = ~out_rimask_196; // @[RegisterRouter.scala:87:24] wire _out_T_2380 = ~out_wimask_196; // @[RegisterRouter.scala:87:24] wire _out_T_2381 = ~out_romask_196; // @[RegisterRouter.scala:87:24] wire _out_T_2382 = ~out_womask_196; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_155 = {hi_955, flags_0_go, _out_prepend_T_155}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2383 = out_prepend_155; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2384 = _out_T_2383; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_156 = _out_T_2384; // @[RegisterRouter.scala:87:24] wire out_rimask_197 = \|_out_rimask_T_197; // @[RegisterRouter.scala:87:24] wire out_wimask_197 = &_out_wimask_T_197; // @[RegisterRouter.scala:87:24] wire out_romask_197 = \|_out_romask_T_197; // @[RegisterRouter.scala:87:24] wire out_womask_197 = &_out_womask_T_197; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_197 = out_rivalid_1_51 & out_rimask_197; // @[RegisterRouter.scala:87:24] wire _out_T_2386 = out_f_rivalid_197; // @[RegisterRouter.scala:87:24] wire out_f_roready_197 = out_roready_1_51 & out_romask_197; // @[RegisterRouter.scala:87:24] wire _out_T_2387 = out_f_roready_197; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_197 = out_wivalid_1_51 & out_wimask_197; // @[RegisterRouter.scala:87:24] wire out_f_woready_197 = out_woready_1_51 & out_womask_197; // @[RegisterRouter.scala:87:24] wire _out_T_2388 = ~out_rimask_197; // @[RegisterRouter.scala:87:24] wire _out_T_2389 = ~out_wimask_197; // @[RegisterRouter.scala:87:24] wire _out_T_2390 = ~out_romask_197; // @[RegisterRouter.scala:87:24] wire _out_T_2391 = ~out_womask_197; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_156 = {hi_956, flags_0_go, _out_prepend_T_156}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2392 = out_prepend_156; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2393 = _out_T_2392; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_157 = _out_T_2393; // @[RegisterRouter.scala:87:24] wire out_rimask_198 = \|_out_rimask_T_198; // @[RegisterRouter.scala:87:24] wire out_wimask_198 = &_out_wimask_T_198; // @[RegisterRouter.scala:87:24] wire out_romask_198 = \|_out_romask_T_198; // @[RegisterRouter.scala:87:24] wire out_womask_198 = &_out_womask_T_198; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_198 = out_rivalid_1_52 & out_rimask_198; // @[RegisterRouter.scala:87:24] wire _out_T_2395 = out_f_rivalid_198; // @[RegisterRouter.scala:87:24] wire out_f_roready_198 = out_roready_1_52 & out_romask_198; // @[RegisterRouter.scala:87:24] wire _out_T_2396 = out_f_roready_198; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_198 = out_wivalid_1_52 & out_wimask_198; // @[RegisterRouter.scala:87:24] wire out_f_woready_198 = out_woready_1_52 & out_womask_198; // @[RegisterRouter.scala:87:24] wire _out_T_2397 = ~out_rimask_198; // @[RegisterRouter.scala:87:24] wire _out_T_2398 = ~out_wimask_198; // @[RegisterRouter.scala:87:24] wire _out_T_2399 = ~out_romask_198; // @[RegisterRouter.scala:87:24] wire _out_T_2400 = ~out_womask_198; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_157 = {hi_957, flags_0_go, _out_prepend_T_157}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2401 = out_prepend_157; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2402 = _out_T_2401; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_158 = _out_T_2402; // @[RegisterRouter.scala:87:24] wire out_rimask_199 = \|_out_rimask_T_199; // @[RegisterRouter.scala:87:24] wire out_wimask_199 = &_out_wimask_T_199; // @[RegisterRouter.scala:87:24] wire out_romask_199 = \|_out_romask_T_199; // @[RegisterRouter.scala:87:24] wire out_womask_199 = &_out_womask_T_199; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_199 = out_rivalid_1_53 & out_rimask_199; // @[RegisterRouter.scala:87:24] wire _out_T_2404 = out_f_rivalid_199; // @[RegisterRouter.scala:87:24] wire out_f_roready_199 = out_roready_1_53 & out_romask_199; // @[RegisterRouter.scala:87:24] wire _out_T_2405 = out_f_roready_199; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_199 = out_wivalid_1_53 & out_wimask_199; // @[RegisterRouter.scala:87:24] wire out_f_woready_199 = out_woready_1_53 & out_womask_199; // @[RegisterRouter.scala:87:24] wire _out_T_2406 = ~out_rimask_199; // @[RegisterRouter.scala:87:24] wire _out_T_2407 = ~out_wimask_199; // @[RegisterRouter.scala:87:24] wire _out_T_2408 = ~out_romask_199; // @[RegisterRouter.scala:87:24] wire _out_T_2409 = ~out_womask_199; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_158 = {hi_958, flags_0_go, _out_prepend_T_158}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2410 = out_prepend_158; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2411 = _out_T_2410; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_159 = _out_T_2411; // @[RegisterRouter.scala:87:24] wire out_rimask_200 = \|_out_rimask_T_200; // @[RegisterRouter.scala:87:24] wire out_wimask_200 = &_out_wimask_T_200; // @[RegisterRouter.scala:87:24] wire out_romask_200 = \|_out_romask_T_200; // @[RegisterRouter.scala:87:24] wire out_womask_200 = &_out_womask_T_200; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_200 = out_rivalid_1_54 & out_rimask_200; // @[RegisterRouter.scala:87:24] wire _out_T_2413 = out_f_rivalid_200; // @[RegisterRouter.scala:87:24] wire out_f_roready_200 = out_roready_1_54 & out_romask_200; // @[RegisterRouter.scala:87:24] wire _out_T_2414 = out_f_roready_200; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_200 = out_wivalid_1_54 & out_wimask_200; // @[RegisterRouter.scala:87:24] wire out_f_woready_200 = out_woready_1_54 & out_womask_200; // @[RegisterRouter.scala:87:24] wire _out_T_2415 = ~out_rimask_200; // @[RegisterRouter.scala:87:24] wire _out_T_2416 = ~out_wimask_200; // @[RegisterRouter.scala:87:24] wire _out_T_2417 = ~out_romask_200; // @[RegisterRouter.scala:87:24] wire _out_T_2418 = ~out_womask_200; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_159 = {hi_959, flags_0_go, _out_prepend_T_159}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2419 = out_prepend_159; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2420 = _out_T_2419; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_160 = _out_T_2420; // @[RegisterRouter.scala:87:24] wire out_rimask_201 = \|_out_rimask_T_201; // @[RegisterRouter.scala:87:24] wire out_wimask_201 = &_out_wimask_T_201; // @[RegisterRouter.scala:87:24] wire out_romask_201 = \|_out_romask_T_201; // @[RegisterRouter.scala:87:24] wire out_womask_201 = &_out_womask_T_201; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_201 = out_rivalid_1_55 & out_rimask_201; // @[RegisterRouter.scala:87:24] wire _out_T_2422 = out_f_rivalid_201; // @[RegisterRouter.scala:87:24] wire out_f_roready_201 = out_roready_1_55 & out_romask_201; // @[RegisterRouter.scala:87:24] wire _out_T_2423 = out_f_roready_201; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_201 = out_wivalid_1_55 & out_wimask_201; // @[RegisterRouter.scala:87:24] wire out_f_woready_201 = out_woready_1_55 & out_womask_201; // @[RegisterRouter.scala:87:24] wire _out_T_2424 = ~out_rimask_201; // @[RegisterRouter.scala:87:24] wire _out_T_2425 = ~out_wimask_201; // @[RegisterRouter.scala:87:24] wire _out_T_2426 = ~out_romask_201; // @[RegisterRouter.scala:87:24] wire _out_T_2427 = ~out_womask_201; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_160 = {hi_960, flags_0_go, _out_prepend_T_160}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2428 = out_prepend_160; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2429 = _out_T_2428; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_247 = _out_T_2429; // @[MuxLiteral.scala:49:48] wire out_rimask_202 = \|_out_rimask_T_202; // @[RegisterRouter.scala:87:24] wire out_wimask_202 = &_out_wimask_T_202; // @[RegisterRouter.scala:87:24] wire out_romask_202 = \|_out_romask_T_202; // @[RegisterRouter.scala:87:24] wire out_womask_202 = &_out_womask_T_202; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_202 = out_rivalid_1_56 & out_rimask_202; // @[RegisterRouter.scala:87:24] wire _out_T_2431 = out_f_rivalid_202; // @[RegisterRouter.scala:87:24] wire out_f_roready_202 = out_roready_1_56 & out_romask_202; // @[RegisterRouter.scala:87:24] wire _out_T_2432 = out_f_roready_202; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_202 = out_wivalid_1_56 & out_wimask_202; // @[RegisterRouter.scala:87:24] wire out_f_woready_202 = out_woready_1_56 & out_womask_202; // @[RegisterRouter.scala:87:24] wire _out_T_2433 = ~out_rimask_202; // @[RegisterRouter.scala:87:24] wire _out_T_2434 = ~out_wimask_202; // @[RegisterRouter.scala:87:24] wire _out_T_2435 = ~out_romask_202; // @[RegisterRouter.scala:87:24] wire _out_T_2436 = ~out_womask_202; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2438 = _out_T_2437; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_161 = _out_T_2438; // @[RegisterRouter.scala:87:24] wire out_rimask_203 = \|_out_rimask_T_203; // @[RegisterRouter.scala:87:24] wire out_wimask_203 = &_out_wimask_T_203; // @[RegisterRouter.scala:87:24] wire out_romask_203 = \|_out_romask_T_203; // @[RegisterRouter.scala:87:24] wire out_womask_203 = &_out_womask_T_203; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_203 = out_rivalid_1_57 & out_rimask_203; // @[RegisterRouter.scala:87:24] wire _out_T_2440 = out_f_rivalid_203; // @[RegisterRouter.scala:87:24] wire out_f_roready_203 = out_roready_1_57 & out_romask_203; // @[RegisterRouter.scala:87:24] wire _out_T_2441 = out_f_roready_203; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_203 = out_wivalid_1_57 & out_wimask_203; // @[RegisterRouter.scala:87:24] wire out_f_woready_203 = out_woready_1_57 & out_womask_203; // @[RegisterRouter.scala:87:24] wire _out_T_2442 = ~out_rimask_203; // @[RegisterRouter.scala:87:24] wire _out_T_2443 = ~out_wimask_203; // @[RegisterRouter.scala:87:24] wire _out_T_2444 = ~out_romask_203; // @[RegisterRouter.scala:87:24] wire _out_T_2445 = ~out_womask_203; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_161 = {hi_594, flags_0_go, _out_prepend_T_161}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2446 = out_prepend_161; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2447 = _out_T_2446; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_162 = _out_T_2447; // @[RegisterRouter.scala:87:24] wire out_rimask_204 = \|_out_rimask_T_204; // @[RegisterRouter.scala:87:24] wire out_wimask_204 = &_out_wimask_T_204; // @[RegisterRouter.scala:87:24] wire out_romask_204 = \|_out_romask_T_204; // @[RegisterRouter.scala:87:24] wire out_womask_204 = &_out_womask_T_204; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_204 = out_rivalid_1_58 & out_rimask_204; // @[RegisterRouter.scala:87:24] wire _out_T_2449 = out_f_rivalid_204; // @[RegisterRouter.scala:87:24] wire out_f_roready_204 = out_roready_1_58 & out_romask_204; // @[RegisterRouter.scala:87:24] wire _out_T_2450 = out_f_roready_204; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_204 = out_wivalid_1_58 & out_wimask_204; // @[RegisterRouter.scala:87:24] wire out_f_woready_204 = out_woready_1_58 & out_womask_204; // @[RegisterRouter.scala:87:24] wire _out_T_2451 = ~out_rimask_204; // @[RegisterRouter.scala:87:24] wire _out_T_2452 = ~out_wimask_204; // @[RegisterRouter.scala:87:24] wire _out_T_2453 = ~out_romask_204; // @[RegisterRouter.scala:87:24] wire _out_T_2454 = ~out_womask_204; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_162 = {hi_595, flags_0_go, _out_prepend_T_162}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2455 = out_prepend_162; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2456 = _out_T_2455; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_163 = _out_T_2456; // @[RegisterRouter.scala:87:24] wire out_rimask_205 = \|_out_rimask_T_205; // @[RegisterRouter.scala:87:24] wire out_wimask_205 = &_out_wimask_T_205; // @[RegisterRouter.scala:87:24] wire out_romask_205 = \|_out_romask_T_205; // @[RegisterRouter.scala:87:24] wire out_womask_205 = &_out_womask_T_205; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_205 = out_rivalid_1_59 & out_rimask_205; // @[RegisterRouter.scala:87:24] wire _out_T_2458 = out_f_rivalid_205; // @[RegisterRouter.scala:87:24] wire out_f_roready_205 = out_roready_1_59 & out_romask_205; // @[RegisterRouter.scala:87:24] wire _out_T_2459 = out_f_roready_205; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_205 = out_wivalid_1_59 & out_wimask_205; // @[RegisterRouter.scala:87:24] wire out_f_woready_205 = out_woready_1_59 & out_womask_205; // @[RegisterRouter.scala:87:24] wire _out_T_2460 = ~out_rimask_205; // @[RegisterRouter.scala:87:24] wire _out_T_2461 = ~out_wimask_205; // @[RegisterRouter.scala:87:24] wire _out_T_2462 = ~out_romask_205; // @[RegisterRouter.scala:87:24] wire _out_T_2463 = ~out_womask_205; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_163 = {hi_596, flags_0_go, _out_prepend_T_163}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2464 = out_prepend_163; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2465 = _out_T_2464; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_164 = _out_T_2465; // @[RegisterRouter.scala:87:24] wire out_rimask_206 = \|_out_rimask_T_206; // @[RegisterRouter.scala:87:24] wire out_wimask_206 = &_out_wimask_T_206; // @[RegisterRouter.scala:87:24] wire out_romask_206 = \|_out_romask_T_206; // @[RegisterRouter.scala:87:24] wire out_womask_206 = &_out_womask_T_206; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_206 = out_rivalid_1_60 & out_rimask_206; // @[RegisterRouter.scala:87:24] wire _out_T_2467 = out_f_rivalid_206; // @[RegisterRouter.scala:87:24] wire out_f_roready_206 = out_roready_1_60 & out_romask_206; // @[RegisterRouter.scala:87:24] wire _out_T_2468 = out_f_roready_206; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_206 = out_wivalid_1_60 & out_wimask_206; // @[RegisterRouter.scala:87:24] wire out_f_woready_206 = out_woready_1_60 & out_womask_206; // @[RegisterRouter.scala:87:24] wire _out_T_2469 = ~out_rimask_206; // @[RegisterRouter.scala:87:24] wire _out_T_2470 = ~out_wimask_206; // @[RegisterRouter.scala:87:24] wire _out_T_2471 = ~out_romask_206; // @[RegisterRouter.scala:87:24] wire _out_T_2472 = ~out_womask_206; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_164 = {hi_597, flags_0_go, _out_prepend_T_164}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2473 = out_prepend_164; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2474 = _out_T_2473; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_165 = _out_T_2474; // @[RegisterRouter.scala:87:24] wire out_rimask_207 = \|_out_rimask_T_207; // @[RegisterRouter.scala:87:24] wire out_wimask_207 = &_out_wimask_T_207; // @[RegisterRouter.scala:87:24] wire out_romask_207 = \|_out_romask_T_207; // @[RegisterRouter.scala:87:24] wire out_womask_207 = &_out_womask_T_207; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_207 = out_rivalid_1_61 & out_rimask_207; // @[RegisterRouter.scala:87:24] wire _out_T_2476 = out_f_rivalid_207; // @[RegisterRouter.scala:87:24] wire out_f_roready_207 = out_roready_1_61 & out_romask_207; // @[RegisterRouter.scala:87:24] wire _out_T_2477 = out_f_roready_207; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_207 = out_wivalid_1_61 & out_wimask_207; // @[RegisterRouter.scala:87:24] wire out_f_woready_207 = out_woready_1_61 & out_womask_207; // @[RegisterRouter.scala:87:24] wire _out_T_2478 = ~out_rimask_207; // @[RegisterRouter.scala:87:24] wire _out_T_2479 = ~out_wimask_207; // @[RegisterRouter.scala:87:24] wire _out_T_2480 = ~out_romask_207; // @[RegisterRouter.scala:87:24] wire _out_T_2481 = ~out_womask_207; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_165 = {hi_598, flags_0_go, _out_prepend_T_165}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2482 = out_prepend_165; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2483 = _out_T_2482; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_166 = _out_T_2483; // @[RegisterRouter.scala:87:24] wire out_rimask_208 = \|_out_rimask_T_208; // @[RegisterRouter.scala:87:24] wire out_wimask_208 = &_out_wimask_T_208; // @[RegisterRouter.scala:87:24] wire out_romask_208 = \|_out_romask_T_208; // @[RegisterRouter.scala:87:24] wire out_womask_208 = &_out_womask_T_208; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_208 = out_rivalid_1_62 & out_rimask_208; // @[RegisterRouter.scala:87:24] wire _out_T_2485 = out_f_rivalid_208; // @[RegisterRouter.scala:87:24] wire out_f_roready_208 = out_roready_1_62 & out_romask_208; // @[RegisterRouter.scala:87:24] wire _out_T_2486 = out_f_roready_208; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_208 = out_wivalid_1_62 & out_wimask_208; // @[RegisterRouter.scala:87:24] wire out_f_woready_208 = out_woready_1_62 & out_womask_208; // @[RegisterRouter.scala:87:24] wire _out_T_2487 = ~out_rimask_208; // @[RegisterRouter.scala:87:24] wire _out_T_2488 = ~out_wimask_208; // @[RegisterRouter.scala:87:24] wire _out_T_2489 = ~out_romask_208; // @[RegisterRouter.scala:87:24] wire _out_T_2490 = ~out_womask_208; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_166 = {hi_599, flags_0_go, _out_prepend_T_166}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2491 = out_prepend_166; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2492 = _out_T_2491; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_167 = _out_T_2492; // @[RegisterRouter.scala:87:24] wire out_rimask_209 = \|_out_rimask_T_209; // @[RegisterRouter.scala:87:24] wire out_wimask_209 = &_out_wimask_T_209; // @[RegisterRouter.scala:87:24] wire out_romask_209 = \|_out_romask_T_209; // @[RegisterRouter.scala:87:24] wire out_womask_209 = &_out_womask_T_209; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_209 = out_rivalid_1_63 & out_rimask_209; // @[RegisterRouter.scala:87:24] wire _out_T_2494 = out_f_rivalid_209; // @[RegisterRouter.scala:87:24] wire out_f_roready_209 = out_roready_1_63 & out_romask_209; // @[RegisterRouter.scala:87:24] wire _out_T_2495 = out_f_roready_209; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_209 = out_wivalid_1_63 & out_wimask_209; // @[RegisterRouter.scala:87:24] wire out_f_woready_209 = out_woready_1_63 & out_womask_209; // @[RegisterRouter.scala:87:24] wire _out_T_2496 = ~out_rimask_209; // @[RegisterRouter.scala:87:24] wire _out_T_2497 = ~out_wimask_209; // @[RegisterRouter.scala:87:24] wire _out_T_2498 = ~out_romask_209; // @[RegisterRouter.scala:87:24] wire _out_T_2499 = ~out_womask_209; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_167 = {hi_600, flags_0_go, _out_prepend_T_167}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2500 = out_prepend_167; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2501 = _out_T_2500; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_202 = _out_T_2501; // @[MuxLiteral.scala:49:48] wire out_rimask_210 = \|_out_rimask_T_210; // @[RegisterRouter.scala:87:24] wire out_wimask_210 = &_out_wimask_T_210; // @[RegisterRouter.scala:87:24] wire out_romask_210 = \|_out_romask_T_210; // @[RegisterRouter.scala:87:24] wire out_womask_210 = &_out_womask_T_210; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_210 = out_rivalid_1_64 & out_rimask_210; // @[RegisterRouter.scala:87:24] wire _out_T_2503 = out_f_rivalid_210; // @[RegisterRouter.scala:87:24] wire out_f_roready_210 = out_roready_1_64 & out_romask_210; // @[RegisterRouter.scala:87:24] wire _out_T_2504 = out_f_roready_210; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_210 = out_wivalid_1_64 & out_wimask_210; // @[RegisterRouter.scala:87:24] wire out_f_woready_210 = out_woready_1_64 & out_womask_210; // @[RegisterRouter.scala:87:24] wire _out_T_2505 = ~out_rimask_210; // @[RegisterRouter.scala:87:24] wire _out_T_2506 = ~out_wimask_210; // @[RegisterRouter.scala:87:24] wire _out_T_2507 = ~out_romask_210; // @[RegisterRouter.scala:87:24] wire _out_T_2508 = ~out_womask_210; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2510 = _out_T_2509; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_168 = _out_T_2510; // @[RegisterRouter.scala:87:24] wire out_rimask_211 = \|_out_rimask_T_211; // @[RegisterRouter.scala:87:24] wire out_wimask_211 = &_out_wimask_T_211; // @[RegisterRouter.scala:87:24] wire out_romask_211 = \|_out_romask_T_211; // @[RegisterRouter.scala:87:24] wire out_womask_211 = &_out_womask_T_211; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_211 = out_rivalid_1_65 & out_rimask_211; // @[RegisterRouter.scala:87:24] wire _out_T_2512 = out_f_rivalid_211; // @[RegisterRouter.scala:87:24] wire out_f_roready_211 = out_roready_1_65 & out_romask_211; // @[RegisterRouter.scala:87:24] wire _out_T_2513 = out_f_roready_211; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_211 = out_wivalid_1_65 & out_wimask_211; // @[RegisterRouter.scala:87:24] wire out_f_woready_211 = out_woready_1_65 & out_womask_211; // @[RegisterRouter.scala:87:24] wire _out_T_2514 = ~out_rimask_211; // @[RegisterRouter.scala:87:24] wire _out_T_2515 = ~out_wimask_211; // @[RegisterRouter.scala:87:24] wire _out_T_2516 = ~out_romask_211; // @[RegisterRouter.scala:87:24] wire _out_T_2517 = ~out_womask_211; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_168 = {hi_114, flags_0_go, _out_prepend_T_168}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2518 = out_prepend_168; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2519 = _out_T_2518; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_169 = _out_T_2519; // @[RegisterRouter.scala:87:24] wire out_rimask_212 = \|_out_rimask_T_212; // @[RegisterRouter.scala:87:24] wire out_wimask_212 = &_out_wimask_T_212; // @[RegisterRouter.scala:87:24] wire out_romask_212 = \|_out_romask_T_212; // @[RegisterRouter.scala:87:24] wire out_womask_212 = &_out_womask_T_212; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_212 = out_rivalid_1_66 & out_rimask_212; // @[RegisterRouter.scala:87:24] wire _out_T_2521 = out_f_rivalid_212; // @[RegisterRouter.scala:87:24] wire out_f_roready_212 = out_roready_1_66 & out_romask_212; // @[RegisterRouter.scala:87:24] wire _out_T_2522 = out_f_roready_212; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_212 = out_wivalid_1_66 & out_wimask_212; // @[RegisterRouter.scala:87:24] wire out_f_woready_212 = out_woready_1_66 & out_womask_212; // @[RegisterRouter.scala:87:24] wire _out_T_2523 = ~out_rimask_212; // @[RegisterRouter.scala:87:24] wire _out_T_2524 = ~out_wimask_212; // @[RegisterRouter.scala:87:24] wire _out_T_2525 = ~out_romask_212; // @[RegisterRouter.scala:87:24] wire _out_T_2526 = ~out_womask_212; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_169 = {hi_115, flags_0_go, _out_prepend_T_169}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2527 = out_prepend_169; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2528 = _out_T_2527; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_170 = _out_T_2528; // @[RegisterRouter.scala:87:24] wire out_rimask_213 = \|_out_rimask_T_213; // @[RegisterRouter.scala:87:24] wire out_wimask_213 = &_out_wimask_T_213; // @[RegisterRouter.scala:87:24] wire out_romask_213 = \|_out_romask_T_213; // @[RegisterRouter.scala:87:24] wire out_womask_213 = &_out_womask_T_213; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_213 = out_rivalid_1_67 & out_rimask_213; // @[RegisterRouter.scala:87:24] wire _out_T_2530 = out_f_rivalid_213; // @[RegisterRouter.scala:87:24] wire out_f_roready_213 = out_roready_1_67 & out_romask_213; // @[RegisterRouter.scala:87:24] wire _out_T_2531 = out_f_roready_213; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_213 = out_wivalid_1_67 & out_wimask_213; // @[RegisterRouter.scala:87:24] wire out_f_woready_213 = out_woready_1_67 & out_womask_213; // @[RegisterRouter.scala:87:24] wire _out_T_2532 = ~out_rimask_213; // @[RegisterRouter.scala:87:24] wire _out_T_2533 = ~out_wimask_213; // @[RegisterRouter.scala:87:24] wire _out_T_2534 = ~out_romask_213; // @[RegisterRouter.scala:87:24] wire _out_T_2535 = ~out_womask_213; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_170 = {hi_116, flags_0_go, _out_prepend_T_170}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2536 = out_prepend_170; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2537 = _out_T_2536; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_171 = _out_T_2537; // @[RegisterRouter.scala:87:24] wire out_rimask_214 = \|_out_rimask_T_214; // @[RegisterRouter.scala:87:24] wire out_wimask_214 = &_out_wimask_T_214; // @[RegisterRouter.scala:87:24] wire out_romask_214 = \|_out_romask_T_214; // @[RegisterRouter.scala:87:24] wire out_womask_214 = &_out_womask_T_214; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_214 = out_rivalid_1_68 & out_rimask_214; // @[RegisterRouter.scala:87:24] wire _out_T_2539 = out_f_rivalid_214; // @[RegisterRouter.scala:87:24] wire out_f_roready_214 = out_roready_1_68 & out_romask_214; // @[RegisterRouter.scala:87:24] wire _out_T_2540 = out_f_roready_214; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_214 = out_wivalid_1_68 & out_wimask_214; // @[RegisterRouter.scala:87:24] wire out_f_woready_214 = out_woready_1_68 & out_womask_214; // @[RegisterRouter.scala:87:24] wire _out_T_2541 = ~out_rimask_214; // @[RegisterRouter.scala:87:24] wire _out_T_2542 = ~out_wimask_214; // @[RegisterRouter.scala:87:24] wire _out_T_2543 = ~out_romask_214; // @[RegisterRouter.scala:87:24] wire _out_T_2544 = ~out_womask_214; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_171 = {hi_117, flags_0_go, _out_prepend_T_171}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2545 = out_prepend_171; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2546 = _out_T_2545; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_172 = _out_T_2546; // @[RegisterRouter.scala:87:24] wire out_rimask_215 = \|_out_rimask_T_215; // @[RegisterRouter.scala:87:24] wire out_wimask_215 = &_out_wimask_T_215; // @[RegisterRouter.scala:87:24] wire out_romask_215 = \|_out_romask_T_215; // @[RegisterRouter.scala:87:24] wire out_womask_215 = &_out_womask_T_215; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_215 = out_rivalid_1_69 & out_rimask_215; // @[RegisterRouter.scala:87:24] wire _out_T_2548 = out_f_rivalid_215; // @[RegisterRouter.scala:87:24] wire out_f_roready_215 = out_roready_1_69 & out_romask_215; // @[RegisterRouter.scala:87:24] wire _out_T_2549 = out_f_roready_215; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_215 = out_wivalid_1_69 & out_wimask_215; // @[RegisterRouter.scala:87:24] wire out_f_woready_215 = out_woready_1_69 & out_womask_215; // @[RegisterRouter.scala:87:24] wire _out_T_2550 = ~out_rimask_215; // @[RegisterRouter.scala:87:24] wire _out_T_2551 = ~out_wimask_215; // @[RegisterRouter.scala:87:24] wire _out_T_2552 = ~out_romask_215; // @[RegisterRouter.scala:87:24] wire _out_T_2553 = ~out_womask_215; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_172 = {hi_118, flags_0_go, _out_prepend_T_172}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2554 = out_prepend_172; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2555 = _out_T_2554; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_173 = _out_T_2555; // @[RegisterRouter.scala:87:24] wire out_rimask_216 = \|_out_rimask_T_216; // @[RegisterRouter.scala:87:24] wire out_wimask_216 = &_out_wimask_T_216; // @[RegisterRouter.scala:87:24] wire out_romask_216 = \|_out_romask_T_216; // @[RegisterRouter.scala:87:24] wire out_womask_216 = &_out_womask_T_216; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_216 = out_rivalid_1_70 & out_rimask_216; // @[RegisterRouter.scala:87:24] wire _out_T_2557 = out_f_rivalid_216; // @[RegisterRouter.scala:87:24] wire out_f_roready_216 = out_roready_1_70 & out_romask_216; // @[RegisterRouter.scala:87:24] wire _out_T_2558 = out_f_roready_216; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_216 = out_wivalid_1_70 & out_wimask_216; // @[RegisterRouter.scala:87:24] wire out_f_woready_216 = out_woready_1_70 & out_womask_216; // @[RegisterRouter.scala:87:24] wire _out_T_2559 = ~out_rimask_216; // @[RegisterRouter.scala:87:24] wire _out_T_2560 = ~out_wimask_216; // @[RegisterRouter.scala:87:24] wire _out_T_2561 = ~out_romask_216; // @[RegisterRouter.scala:87:24] wire _out_T_2562 = ~out_womask_216; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_173 = {hi_119, flags_0_go, _out_prepend_T_173}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2563 = out_prepend_173; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2564 = _out_T_2563; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_174 = _out_T_2564; // @[RegisterRouter.scala:87:24] wire out_rimask_217 = \|_out_rimask_T_217; // @[RegisterRouter.scala:87:24] wire out_wimask_217 = &_out_wimask_T_217; // @[RegisterRouter.scala:87:24] wire out_romask_217 = \|_out_romask_T_217; // @[RegisterRouter.scala:87:24] wire out_womask_217 = &_out_womask_T_217; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_217 = out_rivalid_1_71 & out_rimask_217; // @[RegisterRouter.scala:87:24] wire _out_T_2566 = out_f_rivalid_217; // @[RegisterRouter.scala:87:24] wire out_f_roready_217 = out_roready_1_71 & out_romask_217; // @[RegisterRouter.scala:87:24] wire _out_T_2567 = out_f_roready_217; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_217 = out_wivalid_1_71 & out_wimask_217; // @[RegisterRouter.scala:87:24] wire out_f_woready_217 = out_woready_1_71 & out_womask_217; // @[RegisterRouter.scala:87:24] wire _out_T_2568 = ~out_rimask_217; // @[RegisterRouter.scala:87:24] wire _out_T_2569 = ~out_wimask_217; // @[RegisterRouter.scala:87:24] wire _out_T_2570 = ~out_romask_217; // @[RegisterRouter.scala:87:24] wire _out_T_2571 = ~out_womask_217; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_174 = {hi_120, flags_0_go, _out_prepend_T_174}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2572 = out_prepend_174; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2573 = _out_T_2572; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_142 = _out_T_2573; // @[MuxLiteral.scala:49:48] wire out_rimask_218 = \|_out_rimask_T_218; // @[RegisterRouter.scala:87:24] wire out_wimask_218 = &_out_wimask_T_218; // @[RegisterRouter.scala:87:24] wire out_romask_218 = \|_out_romask_T_218; // @[RegisterRouter.scala:87:24] wire out_womask_218 = &_out_womask_T_218; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_218 = out_rivalid_1_72 & out_rimask_218; // @[RegisterRouter.scala:87:24] wire _out_T_2575 = out_f_rivalid_218; // @[RegisterRouter.scala:87:24] wire out_f_roready_218 = out_roready_1_72 & out_romask_218; // @[RegisterRouter.scala:87:24] wire _out_T_2576 = out_f_roready_218; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_218 = out_wivalid_1_72 & out_wimask_218; // @[RegisterRouter.scala:87:24] wire out_f_woready_218 = out_woready_1_72 & out_womask_218; // @[RegisterRouter.scala:87:24] wire _out_T_2577 = ~out_rimask_218; // @[RegisterRouter.scala:87:24] wire _out_T_2578 = ~out_wimask_218; // @[RegisterRouter.scala:87:24] wire _out_T_2579 = ~out_romask_218; // @[RegisterRouter.scala:87:24] wire _out_T_2580 = ~out_womask_218; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2582 = _out_T_2581; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_175 = _out_T_2582; // @[RegisterRouter.scala:87:24] wire out_rimask_219 = \|_out_rimask_T_219; // @[RegisterRouter.scala:87:24] wire out_wimask_219 = &_out_wimask_T_219; // @[RegisterRouter.scala:87:24] wire out_romask_219 = \|_out_romask_T_219; // @[RegisterRouter.scala:87:24] wire out_womask_219 = &_out_womask_T_219; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_219 = out_rivalid_1_73 & out_rimask_219; // @[RegisterRouter.scala:87:24] wire _out_T_2584 = out_f_rivalid_219; // @[RegisterRouter.scala:87:24] wire out_f_roready_219 = out_roready_1_73 & out_romask_219; // @[RegisterRouter.scala:87:24] wire _out_T_2585 = out_f_roready_219; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_219 = out_wivalid_1_73 & out_wimask_219; // @[RegisterRouter.scala:87:24] wire out_f_woready_219 = out_woready_1_73 & out_womask_219; // @[RegisterRouter.scala:87:24] wire _out_T_2586 = ~out_rimask_219; // @[RegisterRouter.scala:87:24] wire _out_T_2587 = ~out_wimask_219; // @[RegisterRouter.scala:87:24] wire _out_T_2588 = ~out_romask_219; // @[RegisterRouter.scala:87:24] wire _out_T_2589 = ~out_womask_219; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_175 = {hi_202, flags_0_go, _out_prepend_T_175}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2590 = out_prepend_175; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2591 = _out_T_2590; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_176 = _out_T_2591; // @[RegisterRouter.scala:87:24] wire out_rimask_220 = \|_out_rimask_T_220; // @[RegisterRouter.scala:87:24] wire out_wimask_220 = &_out_wimask_T_220; // @[RegisterRouter.scala:87:24] wire out_romask_220 = \|_out_romask_T_220; // @[RegisterRouter.scala:87:24] wire out_womask_220 = &_out_womask_T_220; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_220 = out_rivalid_1_74 & out_rimask_220; // @[RegisterRouter.scala:87:24] wire _out_T_2593 = out_f_rivalid_220; // @[RegisterRouter.scala:87:24] wire out_f_roready_220 = out_roready_1_74 & out_romask_220; // @[RegisterRouter.scala:87:24] wire _out_T_2594 = out_f_roready_220; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_220 = out_wivalid_1_74 & out_wimask_220; // @[RegisterRouter.scala:87:24] wire out_f_woready_220 = out_woready_1_74 & out_womask_220; // @[RegisterRouter.scala:87:24] wire _out_T_2595 = ~out_rimask_220; // @[RegisterRouter.scala:87:24] wire _out_T_2596 = ~out_wimask_220; // @[RegisterRouter.scala:87:24] wire _out_T_2597 = ~out_romask_220; // @[RegisterRouter.scala:87:24] wire _out_T_2598 = ~out_womask_220; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_176 = {hi_203, flags_0_go, _out_prepend_T_176}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2599 = out_prepend_176; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2600 = _out_T_2599; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_177 = _out_T_2600; // @[RegisterRouter.scala:87:24] wire out_rimask_221 = \|_out_rimask_T_221; // @[RegisterRouter.scala:87:24] wire out_wimask_221 = &_out_wimask_T_221; // @[RegisterRouter.scala:87:24] wire out_romask_221 = \|_out_romask_T_221; // @[RegisterRouter.scala:87:24] wire out_womask_221 = &_out_womask_T_221; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_221 = out_rivalid_1_75 & out_rimask_221; // @[RegisterRouter.scala:87:24] wire _out_T_2602 = out_f_rivalid_221; // @[RegisterRouter.scala:87:24] wire out_f_roready_221 = out_roready_1_75 & out_romask_221; // @[RegisterRouter.scala:87:24] wire _out_T_2603 = out_f_roready_221; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_221 = out_wivalid_1_75 & out_wimask_221; // @[RegisterRouter.scala:87:24] wire out_f_woready_221 = out_woready_1_75 & out_womask_221; // @[RegisterRouter.scala:87:24] wire _out_T_2604 = ~out_rimask_221; // @[RegisterRouter.scala:87:24] wire _out_T_2605 = ~out_wimask_221; // @[RegisterRouter.scala:87:24] wire _out_T_2606 = ~out_romask_221; // @[RegisterRouter.scala:87:24] wire _out_T_2607 = ~out_womask_221; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_177 = {hi_204, flags_0_go, _out_prepend_T_177}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2608 = out_prepend_177; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2609 = _out_T_2608; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_178 = _out_T_2609; // @[RegisterRouter.scala:87:24] wire out_rimask_222 = \|_out_rimask_T_222; // @[RegisterRouter.scala:87:24] wire out_wimask_222 = &_out_wimask_T_222; // @[RegisterRouter.scala:87:24] wire out_romask_222 = \|_out_romask_T_222; // @[RegisterRouter.scala:87:24] wire out_womask_222 = &_out_womask_T_222; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_222 = out_rivalid_1_76 & out_rimask_222; // @[RegisterRouter.scala:87:24] wire _out_T_2611 = out_f_rivalid_222; // @[RegisterRouter.scala:87:24] wire out_f_roready_222 = out_roready_1_76 & out_romask_222; // @[RegisterRouter.scala:87:24] wire _out_T_2612 = out_f_roready_222; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_222 = out_wivalid_1_76 & out_wimask_222; // @[RegisterRouter.scala:87:24] wire out_f_woready_222 = out_woready_1_76 & out_womask_222; // @[RegisterRouter.scala:87:24] wire _out_T_2613 = ~out_rimask_222; // @[RegisterRouter.scala:87:24] wire _out_T_2614 = ~out_wimask_222; // @[RegisterRouter.scala:87:24] wire _out_T_2615 = ~out_romask_222; // @[RegisterRouter.scala:87:24] wire _out_T_2616 = ~out_womask_222; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_178 = {hi_205, flags_0_go, _out_prepend_T_178}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2617 = out_prepend_178; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2618 = _out_T_2617; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_179 = _out_T_2618; // @[RegisterRouter.scala:87:24] wire out_rimask_223 = \|_out_rimask_T_223; // @[RegisterRouter.scala:87:24] wire out_wimask_223 = &_out_wimask_T_223; // @[RegisterRouter.scala:87:24] wire out_romask_223 = \|_out_romask_T_223; // @[RegisterRouter.scala:87:24] wire out_womask_223 = &_out_womask_T_223; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_223 = out_rivalid_1_77 & out_rimask_223; // @[RegisterRouter.scala:87:24] wire _out_T_2620 = out_f_rivalid_223; // @[RegisterRouter.scala:87:24] wire out_f_roready_223 = out_roready_1_77 & out_romask_223; // @[RegisterRouter.scala:87:24] wire _out_T_2621 = out_f_roready_223; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_223 = out_wivalid_1_77 & out_wimask_223; // @[RegisterRouter.scala:87:24] wire out_f_woready_223 = out_woready_1_77 & out_womask_223; // @[RegisterRouter.scala:87:24] wire _out_T_2622 = ~out_rimask_223; // @[RegisterRouter.scala:87:24] wire _out_T_2623 = ~out_wimask_223; // @[RegisterRouter.scala:87:24] wire _out_T_2624 = ~out_romask_223; // @[RegisterRouter.scala:87:24] wire _out_T_2625 = ~out_womask_223; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_179 = {hi_206, flags_0_go, _out_prepend_T_179}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2626 = out_prepend_179; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2627 = _out_T_2626; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_180 = _out_T_2627; // @[RegisterRouter.scala:87:24] wire out_rimask_224 = \|_out_rimask_T_224; // @[RegisterRouter.scala:87:24] wire out_wimask_224 = &_out_wimask_T_224; // @[RegisterRouter.scala:87:24] wire out_romask_224 = \|_out_romask_T_224; // @[RegisterRouter.scala:87:24] wire out_womask_224 = &_out_womask_T_224; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_224 = out_rivalid_1_78 & out_rimask_224; // @[RegisterRouter.scala:87:24] wire _out_T_2629 = out_f_rivalid_224; // @[RegisterRouter.scala:87:24] wire out_f_roready_224 = out_roready_1_78 & out_romask_224; // @[RegisterRouter.scala:87:24] wire _out_T_2630 = out_f_roready_224; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_224 = out_wivalid_1_78 & out_wimask_224; // @[RegisterRouter.scala:87:24] wire out_f_woready_224 = out_woready_1_78 & out_womask_224; // @[RegisterRouter.scala:87:24] wire _out_T_2631 = ~out_rimask_224; // @[RegisterRouter.scala:87:24] wire _out_T_2632 = ~out_wimask_224; // @[RegisterRouter.scala:87:24] wire _out_T_2633 = ~out_romask_224; // @[RegisterRouter.scala:87:24] wire _out_T_2634 = ~out_womask_224; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_180 = {hi_207, flags_0_go, _out_prepend_T_180}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2635 = out_prepend_180; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2636 = _out_T_2635; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_181 = _out_T_2636; // @[RegisterRouter.scala:87:24] wire out_rimask_225 = \|_out_rimask_T_225; // @[RegisterRouter.scala:87:24] wire out_wimask_225 = &_out_wimask_T_225; // @[RegisterRouter.scala:87:24] wire out_romask_225 = \|_out_romask_T_225; // @[RegisterRouter.scala:87:24] wire out_womask_225 = &_out_womask_T_225; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_225 = out_rivalid_1_79 & out_rimask_225; // @[RegisterRouter.scala:87:24] wire _out_T_2638 = out_f_rivalid_225; // @[RegisterRouter.scala:87:24] wire out_f_roready_225 = out_roready_1_79 & out_romask_225; // @[RegisterRouter.scala:87:24] wire _out_T_2639 = out_f_roready_225; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_225 = out_wivalid_1_79 & out_wimask_225; // @[RegisterRouter.scala:87:24] wire out_f_woready_225 = out_woready_1_79 & out_womask_225; // @[RegisterRouter.scala:87:24] wire _out_T_2640 = ~out_rimask_225; // @[RegisterRouter.scala:87:24] wire _out_T_2641 = ~out_wimask_225; // @[RegisterRouter.scala:87:24] wire _out_T_2642 = ~out_romask_225; // @[RegisterRouter.scala:87:24] wire _out_T_2643 = ~out_womask_225; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_181 = {hi_208, flags_0_go, _out_prepend_T_181}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2644 = out_prepend_181; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2645 = _out_T_2644; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_153 = _out_T_2645; // @[MuxLiteral.scala:49:48] wire out_rimask_226 = \|_out_rimask_T_226; // @[RegisterRouter.scala:87:24] wire out_wimask_226 = &_out_wimask_T_226; // @[RegisterRouter.scala:87:24] wire out_romask_226 = \|_out_romask_T_226; // @[RegisterRouter.scala:87:24] wire out_womask_226 = &_out_womask_T_226; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_226 = out_rivalid_1_80 & out_rimask_226; // @[RegisterRouter.scala:87:24] wire _out_T_2647 = out_f_rivalid_226; // @[RegisterRouter.scala:87:24] wire out_f_roready_226 = out_roready_1_80 & out_romask_226; // @[RegisterRouter.scala:87:24] wire _out_T_2648 = out_f_roready_226; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_226 = out_wivalid_1_80 & out_wimask_226; // @[RegisterRouter.scala:87:24] wire out_f_woready_226 = out_woready_1_80 & out_womask_226; // @[RegisterRouter.scala:87:24] wire _out_T_2649 = ~out_rimask_226; // @[RegisterRouter.scala:87:24] wire _out_T_2650 = ~out_wimask_226; // @[RegisterRouter.scala:87:24] wire _out_T_2651 = ~out_romask_226; // @[RegisterRouter.scala:87:24] wire _out_T_2652 = ~out_womask_226; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2654 = _out_T_2653; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_182 = _out_T_2654; // @[RegisterRouter.scala:87:24] wire out_rimask_227 = \|_out_rimask_T_227; // @[RegisterRouter.scala:87:24] wire out_wimask_227 = &_out_wimask_T_227; // @[RegisterRouter.scala:87:24] wire out_romask_227 = \|_out_romask_T_227; // @[RegisterRouter.scala:87:24] wire out_womask_227 = &_out_womask_T_227; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_227 = out_rivalid_1_81 & out_rimask_227; // @[RegisterRouter.scala:87:24] wire _out_T_2656 = out_f_rivalid_227; // @[RegisterRouter.scala:87:24] wire out_f_roready_227 = out_roready_1_81 & out_romask_227; // @[RegisterRouter.scala:87:24] wire _out_T_2657 = out_f_roready_227; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_227 = out_wivalid_1_81 & out_wimask_227; // @[RegisterRouter.scala:87:24] wire out_f_woready_227 = out_woready_1_81 & out_womask_227; // @[RegisterRouter.scala:87:24] wire _out_T_2658 = ~out_rimask_227; // @[RegisterRouter.scala:87:24] wire _out_T_2659 = ~out_wimask_227; // @[RegisterRouter.scala:87:24] wire _out_T_2660 = ~out_romask_227; // @[RegisterRouter.scala:87:24] wire _out_T_2661 = ~out_womask_227; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_182 = {hi_370, flags_0_go, _out_prepend_T_182}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2662 = out_prepend_182; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2663 = _out_T_2662; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_183 = _out_T_2663; // @[RegisterRouter.scala:87:24] wire out_rimask_228 = \|_out_rimask_T_228; // @[RegisterRouter.scala:87:24] wire out_wimask_228 = &_out_wimask_T_228; // @[RegisterRouter.scala:87:24] wire out_romask_228 = \|_out_romask_T_228; // @[RegisterRouter.scala:87:24] wire out_womask_228 = &_out_womask_T_228; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_228 = out_rivalid_1_82 & out_rimask_228; // @[RegisterRouter.scala:87:24] wire _out_T_2665 = out_f_rivalid_228; // @[RegisterRouter.scala:87:24] wire out_f_roready_228 = out_roready_1_82 & out_romask_228; // @[RegisterRouter.scala:87:24] wire _out_T_2666 = out_f_roready_228; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_228 = out_wivalid_1_82 & out_wimask_228; // @[RegisterRouter.scala:87:24] wire out_f_woready_228 = out_woready_1_82 & out_womask_228; // @[RegisterRouter.scala:87:24] wire _out_T_2667 = ~out_rimask_228; // @[RegisterRouter.scala:87:24] wire _out_T_2668 = ~out_wimask_228; // @[RegisterRouter.scala:87:24] wire _out_T_2669 = ~out_romask_228; // @[RegisterRouter.scala:87:24] wire _out_T_2670 = ~out_womask_228; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_183 = {hi_371, flags_0_go, _out_prepend_T_183}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2671 = out_prepend_183; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2672 = _out_T_2671; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_184 = _out_T_2672; // @[RegisterRouter.scala:87:24] wire out_rimask_229 = \|_out_rimask_T_229; // @[RegisterRouter.scala:87:24] wire out_wimask_229 = &_out_wimask_T_229; // @[RegisterRouter.scala:87:24] wire out_romask_229 = \|_out_romask_T_229; // @[RegisterRouter.scala:87:24] wire out_womask_229 = &_out_womask_T_229; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_229 = out_rivalid_1_83 & out_rimask_229; // @[RegisterRouter.scala:87:24] wire _out_T_2674 = out_f_rivalid_229; // @[RegisterRouter.scala:87:24] wire out_f_roready_229 = out_roready_1_83 & out_romask_229; // @[RegisterRouter.scala:87:24] wire _out_T_2675 = out_f_roready_229; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_229 = out_wivalid_1_83 & out_wimask_229; // @[RegisterRouter.scala:87:24] wire out_f_woready_229 = out_woready_1_83 & out_womask_229; // @[RegisterRouter.scala:87:24] wire _out_T_2676 = ~out_rimask_229; // @[RegisterRouter.scala:87:24] wire _out_T_2677 = ~out_wimask_229; // @[RegisterRouter.scala:87:24] wire _out_T_2678 = ~out_romask_229; // @[RegisterRouter.scala:87:24] wire _out_T_2679 = ~out_womask_229; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_184 = {hi_372, flags_0_go, _out_prepend_T_184}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2680 = out_prepend_184; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2681 = _out_T_2680; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_185 = _out_T_2681; // @[RegisterRouter.scala:87:24] wire out_rimask_230 = \|_out_rimask_T_230; // @[RegisterRouter.scala:87:24] wire out_wimask_230 = &_out_wimask_T_230; // @[RegisterRouter.scala:87:24] wire out_romask_230 = \|_out_romask_T_230; // @[RegisterRouter.scala:87:24] wire out_womask_230 = &_out_womask_T_230; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_230 = out_rivalid_1_84 & out_rimask_230; // @[RegisterRouter.scala:87:24] wire _out_T_2683 = out_f_rivalid_230; // @[RegisterRouter.scala:87:24] wire out_f_roready_230 = out_roready_1_84 & out_romask_230; // @[RegisterRouter.scala:87:24] wire _out_T_2684 = out_f_roready_230; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_230 = out_wivalid_1_84 & out_wimask_230; // @[RegisterRouter.scala:87:24] wire out_f_woready_230 = out_woready_1_84 & out_womask_230; // @[RegisterRouter.scala:87:24] wire _out_T_2685 = ~out_rimask_230; // @[RegisterRouter.scala:87:24] wire _out_T_2686 = ~out_wimask_230; // @[RegisterRouter.scala:87:24] wire _out_T_2687 = ~out_romask_230; // @[RegisterRouter.scala:87:24] wire _out_T_2688 = ~out_womask_230; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_185 = {hi_373, flags_0_go, _out_prepend_T_185}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2689 = out_prepend_185; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2690 = _out_T_2689; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_186 = _out_T_2690; // @[RegisterRouter.scala:87:24] wire out_rimask_231 = \|_out_rimask_T_231; // @[RegisterRouter.scala:87:24] wire out_wimask_231 = &_out_wimask_T_231; // @[RegisterRouter.scala:87:24] wire out_romask_231 = \|_out_romask_T_231; // @[RegisterRouter.scala:87:24] wire out_womask_231 = &_out_womask_T_231; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_231 = out_rivalid_1_85 & out_rimask_231; // @[RegisterRouter.scala:87:24] wire _out_T_2692 = out_f_rivalid_231; // @[RegisterRouter.scala:87:24] wire out_f_roready_231 = out_roready_1_85 & out_romask_231; // @[RegisterRouter.scala:87:24] wire _out_T_2693 = out_f_roready_231; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_231 = out_wivalid_1_85 & out_wimask_231; // @[RegisterRouter.scala:87:24] wire out_f_woready_231 = out_woready_1_85 & out_womask_231; // @[RegisterRouter.scala:87:24] wire _out_T_2694 = ~out_rimask_231; // @[RegisterRouter.scala:87:24] wire _out_T_2695 = ~out_wimask_231; // @[RegisterRouter.scala:87:24] wire _out_T_2696 = ~out_romask_231; // @[RegisterRouter.scala:87:24] wire _out_T_2697 = ~out_womask_231; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_186 = {hi_374, flags_0_go, _out_prepend_T_186}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2698 = out_prepend_186; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2699 = _out_T_2698; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_187 = _out_T_2699; // @[RegisterRouter.scala:87:24] wire out_rimask_232 = \|_out_rimask_T_232; // @[RegisterRouter.scala:87:24] wire out_wimask_232 = &_out_wimask_T_232; // @[RegisterRouter.scala:87:24] wire out_romask_232 = \|_out_romask_T_232; // @[RegisterRouter.scala:87:24] wire out_womask_232 = &_out_womask_T_232; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_232 = out_rivalid_1_86 & out_rimask_232; // @[RegisterRouter.scala:87:24] wire _out_T_2701 = out_f_rivalid_232; // @[RegisterRouter.scala:87:24] wire out_f_roready_232 = out_roready_1_86 & out_romask_232; // @[RegisterRouter.scala:87:24] wire _out_T_2702 = out_f_roready_232; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_232 = out_wivalid_1_86 & out_wimask_232; // @[RegisterRouter.scala:87:24] wire out_f_woready_232 = out_woready_1_86 & out_womask_232; // @[RegisterRouter.scala:87:24] wire _out_T_2703 = ~out_rimask_232; // @[RegisterRouter.scala:87:24] wire _out_T_2704 = ~out_wimask_232; // @[RegisterRouter.scala:87:24] wire _out_T_2705 = ~out_romask_232; // @[RegisterRouter.scala:87:24] wire _out_T_2706 = ~out_womask_232; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_187 = {hi_375, flags_0_go, _out_prepend_T_187}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2707 = out_prepend_187; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2708 = _out_T_2707; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_188 = _out_T_2708; // @[RegisterRouter.scala:87:24] wire out_rimask_233 = \|_out_rimask_T_233; // @[RegisterRouter.scala:87:24] wire out_wimask_233 = &_out_wimask_T_233; // @[RegisterRouter.scala:87:24] wire out_romask_233 = \|_out_romask_T_233; // @[RegisterRouter.scala:87:24] wire out_womask_233 = &_out_womask_T_233; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_233 = out_rivalid_1_87 & out_rimask_233; // @[RegisterRouter.scala:87:24] wire _out_T_2710 = out_f_rivalid_233; // @[RegisterRouter.scala:87:24] wire out_f_roready_233 = out_roready_1_87 & out_romask_233; // @[RegisterRouter.scala:87:24] wire _out_T_2711 = out_f_roready_233; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_233 = out_wivalid_1_87 & out_wimask_233; // @[RegisterRouter.scala:87:24] wire out_f_woready_233 = out_woready_1_87 & out_womask_233; // @[RegisterRouter.scala:87:24] wire _out_T_2712 = ~out_rimask_233; // @[RegisterRouter.scala:87:24] wire _out_T_2713 = ~out_wimask_233; // @[RegisterRouter.scala:87:24] wire _out_T_2714 = ~out_romask_233; // @[RegisterRouter.scala:87:24] wire _out_T_2715 = ~out_womask_233; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_188 = {hi_376, flags_0_go, _out_prepend_T_188}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2716 = out_prepend_188; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2717 = _out_T_2716; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_174 = _out_T_2717; // @[MuxLiteral.scala:49:48] wire out_rimask_234 = \|_out_rimask_T_234; // @[RegisterRouter.scala:87:24] wire out_wimask_234 = &_out_wimask_T_234; // @[RegisterRouter.scala:87:24] wire out_romask_234 = \|_out_romask_T_234; // @[RegisterRouter.scala:87:24] wire out_womask_234 = &_out_womask_T_234; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_234 = out_rivalid_1_88 & out_rimask_234; // @[RegisterRouter.scala:87:24] wire _out_T_2719 = out_f_rivalid_234; // @[RegisterRouter.scala:87:24] wire out_f_roready_234 = out_roready_1_88 & out_romask_234; // @[RegisterRouter.scala:87:24] wire _out_T_2720 = out_f_roready_234; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_234 = out_wivalid_1_88 & out_wimask_234; // @[RegisterRouter.scala:87:24] wire out_f_woready_234 = out_woready_1_88 & out_womask_234; // @[RegisterRouter.scala:87:24] wire _out_T_2721 = ~out_rimask_234; // @[RegisterRouter.scala:87:24] wire _out_T_2722 = ~out_wimask_234; // @[RegisterRouter.scala:87:24] wire _out_T_2723 = ~out_romask_234; // @[RegisterRouter.scala:87:24] wire _out_T_2724 = ~out_womask_234; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2726 = _out_T_2725; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_189 = _out_T_2726; // @[RegisterRouter.scala:87:24] wire out_rimask_235 = \|_out_rimask_T_235; // @[RegisterRouter.scala:87:24] wire out_wimask_235 = &_out_wimask_T_235; // @[RegisterRouter.scala:87:24] wire out_romask_235 = \|_out_romask_T_235; // @[RegisterRouter.scala:87:24] wire out_womask_235 = &_out_womask_T_235; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_235 = out_rivalid_1_89 & out_rimask_235; // @[RegisterRouter.scala:87:24] wire _out_T_2728 = out_f_rivalid_235; // @[RegisterRouter.scala:87:24] wire out_f_roready_235 = out_roready_1_89 & out_romask_235; // @[RegisterRouter.scala:87:24] wire _out_T_2729 = out_f_roready_235; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_235 = out_wivalid_1_89 & out_wimask_235; // @[RegisterRouter.scala:87:24] wire out_f_woready_235 = out_woready_1_89 & out_womask_235; // @[RegisterRouter.scala:87:24] wire _out_T_2730 = ~out_rimask_235; // @[RegisterRouter.scala:87:24] wire _out_T_2731 = ~out_wimask_235; // @[RegisterRouter.scala:87:24] wire _out_T_2732 = ~out_romask_235; // @[RegisterRouter.scala:87:24] wire _out_T_2733 = ~out_womask_235; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_189 = {hi_458, flags_0_go, _out_prepend_T_189}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2734 = out_prepend_189; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2735 = _out_T_2734; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_190 = _out_T_2735; // @[RegisterRouter.scala:87:24] wire out_rimask_236 = \|_out_rimask_T_236; // @[RegisterRouter.scala:87:24] wire out_wimask_236 = &_out_wimask_T_236; // @[RegisterRouter.scala:87:24] wire out_romask_236 = \|_out_romask_T_236; // @[RegisterRouter.scala:87:24] wire out_womask_236 = &_out_womask_T_236; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_236 = out_rivalid_1_90 & out_rimask_236; // @[RegisterRouter.scala:87:24] wire _out_T_2737 = out_f_rivalid_236; // @[RegisterRouter.scala:87:24] wire out_f_roready_236 = out_roready_1_90 & out_romask_236; // @[RegisterRouter.scala:87:24] wire _out_T_2738 = out_f_roready_236; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_236 = out_wivalid_1_90 & out_wimask_236; // @[RegisterRouter.scala:87:24] wire out_f_woready_236 = out_woready_1_90 & out_womask_236; // @[RegisterRouter.scala:87:24] wire _out_T_2739 = ~out_rimask_236; // @[RegisterRouter.scala:87:24] wire _out_T_2740 = ~out_wimask_236; // @[RegisterRouter.scala:87:24] wire _out_T_2741 = ~out_romask_236; // @[RegisterRouter.scala:87:24] wire _out_T_2742 = ~out_womask_236; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_190 = {hi_459, flags_0_go, _out_prepend_T_190}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2743 = out_prepend_190; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2744 = _out_T_2743; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_191 = _out_T_2744; // @[RegisterRouter.scala:87:24] wire out_rimask_237 = \|_out_rimask_T_237; // @[RegisterRouter.scala:87:24] wire out_wimask_237 = &_out_wimask_T_237; // @[RegisterRouter.scala:87:24] wire out_romask_237 = \|_out_romask_T_237; // @[RegisterRouter.scala:87:24] wire out_womask_237 = &_out_womask_T_237; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_237 = out_rivalid_1_91 & out_rimask_237; // @[RegisterRouter.scala:87:24] wire _out_T_2746 = out_f_rivalid_237; // @[RegisterRouter.scala:87:24] wire out_f_roready_237 = out_roready_1_91 & out_romask_237; // @[RegisterRouter.scala:87:24] wire _out_T_2747 = out_f_roready_237; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_237 = out_wivalid_1_91 & out_wimask_237; // @[RegisterRouter.scala:87:24] wire out_f_woready_237 = out_woready_1_91 & out_womask_237; // @[RegisterRouter.scala:87:24] wire _out_T_2748 = ~out_rimask_237; // @[RegisterRouter.scala:87:24] wire _out_T_2749 = ~out_wimask_237; // @[RegisterRouter.scala:87:24] wire _out_T_2750 = ~out_romask_237; // @[RegisterRouter.scala:87:24] wire _out_T_2751 = ~out_womask_237; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_191 = {hi_460, flags_0_go, _out_prepend_T_191}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2752 = out_prepend_191; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2753 = _out_T_2752; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_192 = _out_T_2753; // @[RegisterRouter.scala:87:24] wire out_rimask_238 = \|_out_rimask_T_238; // @[RegisterRouter.scala:87:24] wire out_wimask_238 = &_out_wimask_T_238; // @[RegisterRouter.scala:87:24] wire out_romask_238 = \|_out_romask_T_238; // @[RegisterRouter.scala:87:24] wire out_womask_238 = &_out_womask_T_238; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_238 = out_rivalid_1_92 & out_rimask_238; // @[RegisterRouter.scala:87:24] wire _out_T_2755 = out_f_rivalid_238; // @[RegisterRouter.scala:87:24] wire out_f_roready_238 = out_roready_1_92 & out_romask_238; // @[RegisterRouter.scala:87:24] wire _out_T_2756 = out_f_roready_238; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_238 = out_wivalid_1_92 & out_wimask_238; // @[RegisterRouter.scala:87:24] wire out_f_woready_238 = out_woready_1_92 & out_womask_238; // @[RegisterRouter.scala:87:24] wire _out_T_2757 = ~out_rimask_238; // @[RegisterRouter.scala:87:24] wire _out_T_2758 = ~out_wimask_238; // @[RegisterRouter.scala:87:24] wire _out_T_2759 = ~out_romask_238; // @[RegisterRouter.scala:87:24] wire _out_T_2760 = ~out_womask_238; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_192 = {hi_461, flags_0_go, _out_prepend_T_192}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2761 = out_prepend_192; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2762 = _out_T_2761; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_193 = _out_T_2762; // @[RegisterRouter.scala:87:24] wire out_rimask_239 = \|_out_rimask_T_239; // @[RegisterRouter.scala:87:24] wire out_wimask_239 = &_out_wimask_T_239; // @[RegisterRouter.scala:87:24] wire out_romask_239 = \|_out_romask_T_239; // @[RegisterRouter.scala:87:24] wire out_womask_239 = &_out_womask_T_239; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_239 = out_rivalid_1_93 & out_rimask_239; // @[RegisterRouter.scala:87:24] wire _out_T_2764 = out_f_rivalid_239; // @[RegisterRouter.scala:87:24] wire out_f_roready_239 = out_roready_1_93 & out_romask_239; // @[RegisterRouter.scala:87:24] wire _out_T_2765 = out_f_roready_239; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_239 = out_wivalid_1_93 & out_wimask_239; // @[RegisterRouter.scala:87:24] wire out_f_woready_239 = out_woready_1_93 & out_womask_239; // @[RegisterRouter.scala:87:24] wire _out_T_2766 = ~out_rimask_239; // @[RegisterRouter.scala:87:24] wire _out_T_2767 = ~out_wimask_239; // @[RegisterRouter.scala:87:24] wire _out_T_2768 = ~out_romask_239; // @[RegisterRouter.scala:87:24] wire _out_T_2769 = ~out_womask_239; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_193 = {hi_462, flags_0_go, _out_prepend_T_193}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2770 = out_prepend_193; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2771 = _out_T_2770; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_194 = _out_T_2771; // @[RegisterRouter.scala:87:24] wire out_rimask_240 = \|_out_rimask_T_240; // @[RegisterRouter.scala:87:24] wire out_wimask_240 = &_out_wimask_T_240; // @[RegisterRouter.scala:87:24] wire out_romask_240 = \|_out_romask_T_240; // @[RegisterRouter.scala:87:24] wire out_womask_240 = &_out_womask_T_240; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_240 = out_rivalid_1_94 & out_rimask_240; // @[RegisterRouter.scala:87:24] wire _out_T_2773 = out_f_rivalid_240; // @[RegisterRouter.scala:87:24] wire out_f_roready_240 = out_roready_1_94 & out_romask_240; // @[RegisterRouter.scala:87:24] wire _out_T_2774 = out_f_roready_240; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_240 = out_wivalid_1_94 & out_wimask_240; // @[RegisterRouter.scala:87:24] wire out_f_woready_240 = out_woready_1_94 & out_womask_240; // @[RegisterRouter.scala:87:24] wire _out_T_2775 = ~out_rimask_240; // @[RegisterRouter.scala:87:24] wire _out_T_2776 = ~out_wimask_240; // @[RegisterRouter.scala:87:24] wire _out_T_2777 = ~out_romask_240; // @[RegisterRouter.scala:87:24] wire _out_T_2778 = ~out_womask_240; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_194 = {hi_463, flags_0_go, _out_prepend_T_194}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2779 = out_prepend_194; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2780 = _out_T_2779; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_195 = _out_T_2780; // @[RegisterRouter.scala:87:24] wire out_rimask_241 = \|_out_rimask_T_241; // @[RegisterRouter.scala:87:24] wire out_wimask_241 = &_out_wimask_T_241; // @[RegisterRouter.scala:87:24] wire out_romask_241 = \|_out_romask_T_241; // @[RegisterRouter.scala:87:24] wire out_womask_241 = &_out_womask_T_241; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_241 = out_rivalid_1_95 & out_rimask_241; // @[RegisterRouter.scala:87:24] wire _out_T_2782 = out_f_rivalid_241; // @[RegisterRouter.scala:87:24] wire out_f_roready_241 = out_roready_1_95 & out_romask_241; // @[RegisterRouter.scala:87:24] wire _out_T_2783 = out_f_roready_241; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_241 = out_wivalid_1_95 & out_wimask_241; // @[RegisterRouter.scala:87:24] wire out_f_woready_241 = out_woready_1_95 & out_womask_241; // @[RegisterRouter.scala:87:24] wire _out_T_2784 = ~out_rimask_241; // @[RegisterRouter.scala:87:24] wire _out_T_2785 = ~out_wimask_241; // @[RegisterRouter.scala:87:24] wire _out_T_2786 = ~out_romask_241; // @[RegisterRouter.scala:87:24] wire _out_T_2787 = ~out_womask_241; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_195 = {hi_464, flags_0_go, _out_prepend_T_195}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2788 = out_prepend_195; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2789 = _out_T_2788; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_185 = _out_T_2789; // @[MuxLiteral.scala:49:48] wire out_rimask_242 = \|_out_rimask_T_242; // @[RegisterRouter.scala:87:24] wire out_wimask_242 = &_out_wimask_T_242; // @[RegisterRouter.scala:87:24] wire out_romask_242 = \|_out_romask_T_242; // @[RegisterRouter.scala:87:24] wire out_womask_242 = &_out_womask_T_242; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_242 = out_rivalid_1_96 & out_rimask_242; // @[RegisterRouter.scala:87:24] wire _out_T_2791 = out_f_rivalid_242; // @[RegisterRouter.scala:87:24] wire out_f_roready_242 = out_roready_1_96 & out_romask_242; // @[RegisterRouter.scala:87:24] wire _out_T_2792 = out_f_roready_242; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_242 = out_wivalid_1_96 & out_wimask_242; // @[RegisterRouter.scala:87:24] wire out_f_woready_242 = out_woready_1_96 & out_womask_242; // @[RegisterRouter.scala:87:24] wire _out_T_2793 = ~out_rimask_242; // @[RegisterRouter.scala:87:24] wire _out_T_2794 = ~out_wimask_242; // @[RegisterRouter.scala:87:24] wire _out_T_2795 = ~out_romask_242; // @[RegisterRouter.scala:87:24] wire _out_T_2796 = ~out_womask_242; // @[RegisterRouter.scala:87:24] wire out_rimask_243 = \|_out_rimask_T_243; // @[RegisterRouter.scala:87:24] wire out_wimask_243 = &_out_wimask_T_243; // @[RegisterRouter.scala:87:24] wire out_romask_243 = \|_out_romask_T_243; // @[RegisterRouter.scala:87:24] wire out_womask_243 = &_out_womask_T_243; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_243 = out_rivalid_1_97 & out_rimask_243; // @[RegisterRouter.scala:87:24] wire _out_T_2800 = out_f_rivalid_243; // @[RegisterRouter.scala:87:24] wire out_f_roready_243 = out_roready_1_97 & out_romask_243; // @[RegisterRouter.scala:87:24] wire _out_T_2801 = out_f_roready_243; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_243 = out_wivalid_1_97 & out_wimask_243; // @[RegisterRouter.scala:87:24] wire out_f_woready_243 = out_woready_1_97 & out_womask_243; // @[RegisterRouter.scala:87:24] wire _out_T_2802 = ~out_rimask_243; // @[RegisterRouter.scala:87:24] wire _out_T_2803 = ~out_wimask_243; // @[RegisterRouter.scala:87:24] wire _out_T_2804 = ~out_romask_243; // @[RegisterRouter.scala:87:24] wire _out_T_2805 = ~out_womask_243; // @[RegisterRouter.scala:87:24] wire out_rimask_244 = \|_out_rimask_T_244; // @[RegisterRouter.scala:87:24] wire out_wimask_244 = &_out_wimask_T_244; // @[RegisterRouter.scala:87:24] wire out_romask_244 = \|_out_romask_T_244; // @[RegisterRouter.scala:87:24] wire out_womask_244 = &_out_womask_T_244; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_244 = out_rivalid_1_98 & out_rimask_244; // @[RegisterRouter.scala:87:24] wire _out_T_2809 = out_f_rivalid_244; // @[RegisterRouter.scala:87:24] wire out_f_roready_244 = out_roready_1_98 & out_romask_244; // @[RegisterRouter.scala:87:24] wire _out_T_2810 = out_f_roready_244; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_244 = out_wivalid_1_98 & out_wimask_244; // @[RegisterRouter.scala:87:24] wire out_f_woready_244 = out_woready_1_98 & out_womask_244; // @[RegisterRouter.scala:87:24] wire _out_T_2811 = ~out_rimask_244; // @[RegisterRouter.scala:87:24] wire _out_T_2812 = ~out_wimask_244; // @[RegisterRouter.scala:87:24] wire _out_T_2813 = ~out_romask_244; // @[RegisterRouter.scala:87:24] wire _out_T_2814 = ~out_womask_244; // @[RegisterRouter.scala:87:24] wire out_rimask_245 = \|_out_rimask_T_245; // @[RegisterRouter.scala:87:24] wire out_wimask_245 = &_out_wimask_T_245; // @[RegisterRouter.scala:87:24] wire out_romask_245 = \|_out_romask_T_245; // @[RegisterRouter.scala:87:24] wire out_womask_245 = &_out_womask_T_245; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_245 = out_rivalid_1_99 & out_rimask_245; // @[RegisterRouter.scala:87:24] wire _out_T_2818 = out_f_rivalid_245; // @[RegisterRouter.scala:87:24] wire out_f_roready_245 = out_roready_1_99 & out_romask_245; // @[RegisterRouter.scala:87:24] wire _out_T_2819 = out_f_roready_245; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_245 = out_wivalid_1_99 & out_wimask_245; // @[RegisterRouter.scala:87:24] wire out_f_woready_245 = out_woready_1_99 & out_womask_245; // @[RegisterRouter.scala:87:24] wire _out_T_2820 = ~out_rimask_245; // @[RegisterRouter.scala:87:24] wire _out_T_2821 = ~out_wimask_245; // @[RegisterRouter.scala:87:24] wire _out_T_2822 = ~out_romask_245; // @[RegisterRouter.scala:87:24] wire _out_T_2823 = ~out_womask_245; // @[RegisterRouter.scala:87:24] wire out_rimask_246 = \|_out_rimask_T_246; // @[RegisterRouter.scala:87:24] wire out_wimask_246 = &_out_wimask_T_246; // @[RegisterRouter.scala:87:24] wire out_romask_246 = \|_out_romask_T_246; // @[RegisterRouter.scala:87:24] wire out_womask_246 = &_out_womask_T_246; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_246 = out_rivalid_1_100 & out_rimask_246; // @[RegisterRouter.scala:87:24] wire _out_T_2827 = out_f_rivalid_246; // @[RegisterRouter.scala:87:24] wire out_f_roready_246 = out_roready_1_100 & out_romask_246; // @[RegisterRouter.scala:87:24] wire _out_T_2828 = out_f_roready_246; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_246 = out_wivalid_1_100 & out_wimask_246; // @[RegisterRouter.scala:87:24] wire out_f_woready_246 = out_woready_1_100 & out_womask_246; // @[RegisterRouter.scala:87:24] wire _out_T_2829 = ~out_rimask_246; // @[RegisterRouter.scala:87:24] wire _out_T_2830 = ~out_wimask_246; // @[RegisterRouter.scala:87:24] wire _out_T_2831 = ~out_romask_246; // @[RegisterRouter.scala:87:24] wire _out_T_2832 = ~out_womask_246; // @[RegisterRouter.scala:87:24] wire out_rimask_247 = \|_out_rimask_T_247; // @[RegisterRouter.scala:87:24] wire out_wimask_247 = &_out_wimask_T_247; // @[RegisterRouter.scala:87:24] wire out_romask_247 = \|_out_romask_T_247; // @[RegisterRouter.scala:87:24] wire out_womask_247 = &_out_womask_T_247; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_247 = out_rivalid_1_101 & out_rimask_247; // @[RegisterRouter.scala:87:24] wire _out_T_2836 = out_f_rivalid_247; // @[RegisterRouter.scala:87:24] wire out_f_roready_247 = out_roready_1_101 & out_romask_247; // @[RegisterRouter.scala:87:24] wire _out_T_2837 = out_f_roready_247; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_247 = out_wivalid_1_101 & out_wimask_247; // @[RegisterRouter.scala:87:24] wire out_f_woready_247 = out_woready_1_101 & out_womask_247; // @[RegisterRouter.scala:87:24] wire _out_T_2838 = ~out_rimask_247; // @[RegisterRouter.scala:87:24] wire _out_T_2839 = ~out_wimask_247; // @[RegisterRouter.scala:87:24] wire _out_T_2840 = ~out_romask_247; // @[RegisterRouter.scala:87:24] wire _out_T_2841 = ~out_womask_247; // @[RegisterRouter.scala:87:24] wire out_rimask_248 = \|_out_rimask_T_248; // @[RegisterRouter.scala:87:24] wire out_wimask_248 = &_out_wimask_T_248; // @[RegisterRouter.scala:87:24] wire out_romask_248 = \|_out_romask_T_248; // @[RegisterRouter.scala:87:24] wire out_womask_248 = &_out_womask_T_248; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_248 = out_rivalid_1_102 & out_rimask_248; // @[RegisterRouter.scala:87:24] wire _out_T_2845 = out_f_rivalid_248; // @[RegisterRouter.scala:87:24] wire out_f_roready_248 = out_roready_1_102 & out_romask_248; // @[RegisterRouter.scala:87:24] wire _out_T_2846 = out_f_roready_248; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_248 = out_wivalid_1_102 & out_wimask_248; // @[RegisterRouter.scala:87:24] wire out_f_woready_248 = out_woready_1_102 & out_womask_248; // @[RegisterRouter.scala:87:24] wire _out_T_2847 = ~out_rimask_248; // @[RegisterRouter.scala:87:24] wire _out_T_2848 = ~out_wimask_248; // @[RegisterRouter.scala:87:24] wire _out_T_2849 = ~out_romask_248; // @[RegisterRouter.scala:87:24] wire _out_T_2850 = ~out_womask_248; // @[RegisterRouter.scala:87:24] wire out_rimask_249 = \|_out_rimask_T_249; // @[RegisterRouter.scala:87:24] wire out_wimask_249 = &_out_wimask_T_249; // @[RegisterRouter.scala:87:24] wire out_romask_249 = \|_out_romask_T_249; // @[RegisterRouter.scala:87:24] wire out_womask_249 = &_out_womask_T_249; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_249 = out_rivalid_1_103 & out_rimask_249; // @[RegisterRouter.scala:87:24] wire _out_T_2854 = out_f_rivalid_249; // @[RegisterRouter.scala:87:24] wire out_f_roready_249 = out_roready_1_103 & out_romask_249; // @[RegisterRouter.scala:87:24] wire _out_T_2855 = out_f_roready_249; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_249 = out_wivalid_1_103 & out_wimask_249; // @[RegisterRouter.scala:87:24] wire out_f_woready_249 = out_woready_1_103 & out_womask_249; // @[RegisterRouter.scala:87:24] wire _out_T_2856 = ~out_rimask_249; // @[RegisterRouter.scala:87:24] wire _out_T_2857 = ~out_wimask_249; // @[RegisterRouter.scala:87:24] wire _out_T_2858 = ~out_romask_249; // @[RegisterRouter.scala:87:24] wire _out_T_2859 = ~out_womask_249; // @[RegisterRouter.scala:87:24] wire out_rimask_250 = \|_out_rimask_T_250; // @[RegisterRouter.scala:87:24] wire out_wimask_250 = &_out_wimask_T_250; // @[RegisterRouter.scala:87:24] wire out_romask_250 = \|_out_romask_T_250; // @[RegisterRouter.scala:87:24] wire out_womask_250 = &_out_womask_T_250; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_250 = out_rivalid_1_104 & out_rimask_250; // @[RegisterRouter.scala:87:24] wire _out_T_2863 = out_f_rivalid_250; // @[RegisterRouter.scala:87:24] wire out_f_roready_250 = out_roready_1_104 & out_romask_250; // @[RegisterRouter.scala:87:24] wire _out_T_2864 = out_f_roready_250; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_250 = out_wivalid_1_104 & out_wimask_250; // @[RegisterRouter.scala:87:24] wire out_f_woready_250 = out_woready_1_104 & out_womask_250; // @[RegisterRouter.scala:87:24] wire _out_T_2865 = ~out_rimask_250; // @[RegisterRouter.scala:87:24] wire _out_T_2866 = ~out_wimask_250; // @[RegisterRouter.scala:87:24] wire _out_T_2867 = ~out_romask_250; // @[RegisterRouter.scala:87:24] wire _out_T_2868 = ~out_womask_250; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2870 = _out_T_2869; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_203 = _out_T_2870; // @[RegisterRouter.scala:87:24] wire out_rimask_251 = \|_out_rimask_T_251; // @[RegisterRouter.scala:87:24] wire out_wimask_251 = &_out_wimask_T_251; // @[RegisterRouter.scala:87:24] wire out_romask_251 = \|_out_romask_T_251; // @[RegisterRouter.scala:87:24] wire out_womask_251 = &_out_womask_T_251; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_251 = out_rivalid_1_105 & out_rimask_251; // @[RegisterRouter.scala:87:24] wire _out_T_2872 = out_f_rivalid_251; // @[RegisterRouter.scala:87:24] wire out_f_roready_251 = out_roready_1_105 & out_romask_251; // @[RegisterRouter.scala:87:24] wire _out_T_2873 = out_f_roready_251; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_251 = out_wivalid_1_105 & out_wimask_251; // @[RegisterRouter.scala:87:24] wire out_f_woready_251 = out_woready_1_105 & out_womask_251; // @[RegisterRouter.scala:87:24] wire _out_T_2874 = ~out_rimask_251; // @[RegisterRouter.scala:87:24] wire _out_T_2875 = ~out_wimask_251; // @[RegisterRouter.scala:87:24] wire _out_T_2876 = ~out_romask_251; // @[RegisterRouter.scala:87:24] wire _out_T_2877 = ~out_womask_251; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_203 = {hi_450, flags_0_go, _out_prepend_T_203}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2878 = out_prepend_203; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2879 = _out_T_2878; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_204 = _out_T_2879; // @[RegisterRouter.scala:87:24] wire out_rimask_252 = \|_out_rimask_T_252; // @[RegisterRouter.scala:87:24] wire out_wimask_252 = &_out_wimask_T_252; // @[RegisterRouter.scala:87:24] wire out_romask_252 = \|_out_romask_T_252; // @[RegisterRouter.scala:87:24] wire out_womask_252 = &_out_womask_T_252; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_252 = out_rivalid_1_106 & out_rimask_252; // @[RegisterRouter.scala:87:24] wire _out_T_2881 = out_f_rivalid_252; // @[RegisterRouter.scala:87:24] wire out_f_roready_252 = out_roready_1_106 & out_romask_252; // @[RegisterRouter.scala:87:24] wire _out_T_2882 = out_f_roready_252; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_252 = out_wivalid_1_106 & out_wimask_252; // @[RegisterRouter.scala:87:24] wire out_f_woready_252 = out_woready_1_106 & out_womask_252; // @[RegisterRouter.scala:87:24] wire _out_T_2883 = ~out_rimask_252; // @[RegisterRouter.scala:87:24] wire _out_T_2884 = ~out_wimask_252; // @[RegisterRouter.scala:87:24] wire _out_T_2885 = ~out_romask_252; // @[RegisterRouter.scala:87:24] wire _out_T_2886 = ~out_womask_252; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_204 = {hi_451, flags_0_go, _out_prepend_T_204}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2887 = out_prepend_204; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2888 = _out_T_2887; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_205 = _out_T_2888; // @[RegisterRouter.scala:87:24] wire out_rimask_253 = \|_out_rimask_T_253; // @[RegisterRouter.scala:87:24] wire out_wimask_253 = &_out_wimask_T_253; // @[RegisterRouter.scala:87:24] wire out_romask_253 = \|_out_romask_T_253; // @[RegisterRouter.scala:87:24] wire out_womask_253 = &_out_womask_T_253; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_253 = out_rivalid_1_107 & out_rimask_253; // @[RegisterRouter.scala:87:24] wire _out_T_2890 = out_f_rivalid_253; // @[RegisterRouter.scala:87:24] wire out_f_roready_253 = out_roready_1_107 & out_romask_253; // @[RegisterRouter.scala:87:24] wire _out_T_2891 = out_f_roready_253; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_253 = out_wivalid_1_107 & out_wimask_253; // @[RegisterRouter.scala:87:24] wire out_f_woready_253 = out_woready_1_107 & out_womask_253; // @[RegisterRouter.scala:87:24] wire _out_T_2892 = ~out_rimask_253; // @[RegisterRouter.scala:87:24] wire _out_T_2893 = ~out_wimask_253; // @[RegisterRouter.scala:87:24] wire _out_T_2894 = ~out_romask_253; // @[RegisterRouter.scala:87:24] wire _out_T_2895 = ~out_womask_253; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_205 = {hi_452, flags_0_go, _out_prepend_T_205}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2896 = out_prepend_205; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2897 = _out_T_2896; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_206 = _out_T_2897; // @[RegisterRouter.scala:87:24] wire out_rimask_254 = \|_out_rimask_T_254; // @[RegisterRouter.scala:87:24] wire out_wimask_254 = &_out_wimask_T_254; // @[RegisterRouter.scala:87:24] wire out_romask_254 = \|_out_romask_T_254; // @[RegisterRouter.scala:87:24] wire out_womask_254 = &_out_womask_T_254; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_254 = out_rivalid_1_108 & out_rimask_254; // @[RegisterRouter.scala:87:24] wire _out_T_2899 = out_f_rivalid_254; // @[RegisterRouter.scala:87:24] wire out_f_roready_254 = out_roready_1_108 & out_romask_254; // @[RegisterRouter.scala:87:24] wire _out_T_2900 = out_f_roready_254; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_254 = out_wivalid_1_108 & out_wimask_254; // @[RegisterRouter.scala:87:24] wire out_f_woready_254 = out_woready_1_108 & out_womask_254; // @[RegisterRouter.scala:87:24] wire _out_T_2901 = ~out_rimask_254; // @[RegisterRouter.scala:87:24] wire _out_T_2902 = ~out_wimask_254; // @[RegisterRouter.scala:87:24] wire _out_T_2903 = ~out_romask_254; // @[RegisterRouter.scala:87:24] wire _out_T_2904 = ~out_womask_254; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_206 = {hi_453, flags_0_go, _out_prepend_T_206}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2905 = out_prepend_206; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2906 = _out_T_2905; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_207 = _out_T_2906; // @[RegisterRouter.scala:87:24] wire out_rimask_255 = \|_out_rimask_T_255; // @[RegisterRouter.scala:87:24] wire out_wimask_255 = &_out_wimask_T_255; // @[RegisterRouter.scala:87:24] wire out_romask_255 = \|_out_romask_T_255; // @[RegisterRouter.scala:87:24] wire out_womask_255 = &_out_womask_T_255; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_255 = out_rivalid_1_109 & out_rimask_255; // @[RegisterRouter.scala:87:24] wire _out_T_2908 = out_f_rivalid_255; // @[RegisterRouter.scala:87:24] wire out_f_roready_255 = out_roready_1_109 & out_romask_255; // @[RegisterRouter.scala:87:24] wire _out_T_2909 = out_f_roready_255; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_255 = out_wivalid_1_109 & out_wimask_255; // @[RegisterRouter.scala:87:24] wire out_f_woready_255 = out_woready_1_109 & out_womask_255; // @[RegisterRouter.scala:87:24] wire _out_T_2910 = ~out_rimask_255; // @[RegisterRouter.scala:87:24] wire _out_T_2911 = ~out_wimask_255; // @[RegisterRouter.scala:87:24] wire _out_T_2912 = ~out_romask_255; // @[RegisterRouter.scala:87:24] wire _out_T_2913 = ~out_womask_255; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_207 = {hi_454, flags_0_go, _out_prepend_T_207}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2914 = out_prepend_207; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2915 = _out_T_2914; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_208 = _out_T_2915; // @[RegisterRouter.scala:87:24] wire out_rimask_256 = \|_out_rimask_T_256; // @[RegisterRouter.scala:87:24] wire out_wimask_256 = &_out_wimask_T_256; // @[RegisterRouter.scala:87:24] wire out_romask_256 = \|_out_romask_T_256; // @[RegisterRouter.scala:87:24] wire out_womask_256 = &_out_womask_T_256; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_256 = out_rivalid_1_110 & out_rimask_256; // @[RegisterRouter.scala:87:24] wire _out_T_2917 = out_f_rivalid_256; // @[RegisterRouter.scala:87:24] wire out_f_roready_256 = out_roready_1_110 & out_romask_256; // @[RegisterRouter.scala:87:24] wire _out_T_2918 = out_f_roready_256; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_256 = out_wivalid_1_110 & out_wimask_256; // @[RegisterRouter.scala:87:24] wire out_f_woready_256 = out_woready_1_110 & out_womask_256; // @[RegisterRouter.scala:87:24] wire _out_T_2919 = ~out_rimask_256; // @[RegisterRouter.scala:87:24] wire _out_T_2920 = ~out_wimask_256; // @[RegisterRouter.scala:87:24] wire _out_T_2921 = ~out_romask_256; // @[RegisterRouter.scala:87:24] wire _out_T_2922 = ~out_womask_256; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_208 = {hi_455, flags_0_go, _out_prepend_T_208}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2923 = out_prepend_208; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2924 = _out_T_2923; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_209 = _out_T_2924; // @[RegisterRouter.scala:87:24] wire out_rimask_257 = \|_out_rimask_T_257; // @[RegisterRouter.scala:87:24] wire out_wimask_257 = &_out_wimask_T_257; // @[RegisterRouter.scala:87:24] wire out_romask_257 = \|_out_romask_T_257; // @[RegisterRouter.scala:87:24] wire out_womask_257 = &_out_womask_T_257; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_257 = out_rivalid_1_111 & out_rimask_257; // @[RegisterRouter.scala:87:24] wire _out_T_2926 = out_f_rivalid_257; // @[RegisterRouter.scala:87:24] wire out_f_roready_257 = out_roready_1_111 & out_romask_257; // @[RegisterRouter.scala:87:24] wire _out_T_2927 = out_f_roready_257; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_257 = out_wivalid_1_111 & out_wimask_257; // @[RegisterRouter.scala:87:24] wire out_f_woready_257 = out_woready_1_111 & out_womask_257; // @[RegisterRouter.scala:87:24] wire _out_T_2928 = ~out_rimask_257; // @[RegisterRouter.scala:87:24] wire _out_T_2929 = ~out_wimask_257; // @[RegisterRouter.scala:87:24] wire _out_T_2930 = ~out_romask_257; // @[RegisterRouter.scala:87:24] wire _out_T_2931 = ~out_womask_257; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_209 = {hi_456, flags_0_go, _out_prepend_T_209}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2932 = out_prepend_209; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2933 = _out_T_2932; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_184 = _out_T_2933; // @[MuxLiteral.scala:49:48] wire out_rimask_258 = \|_out_rimask_T_258; // @[RegisterRouter.scala:87:24] wire out_wimask_258 = &_out_wimask_T_258; // @[RegisterRouter.scala:87:24] wire out_romask_258 = \|_out_romask_T_258; // @[RegisterRouter.scala:87:24] wire out_womask_258 = &_out_womask_T_258; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_258 = out_rivalid_1_112 & out_rimask_258; // @[RegisterRouter.scala:87:24] wire _out_T_2935 = out_f_rivalid_258; // @[RegisterRouter.scala:87:24] wire out_f_roready_258 = out_roready_1_112 & out_romask_258; // @[RegisterRouter.scala:87:24] wire _out_T_2936 = out_f_roready_258; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_258 = out_wivalid_1_112 & out_wimask_258; // @[RegisterRouter.scala:87:24] wire _out_T_2937 = out_f_wivalid_258; // @[RegisterRouter.scala:87:24] wire out_f_woready_258 = out_woready_1_112 & out_womask_258; // @[RegisterRouter.scala:87:24] wire _out_T_2938 = out_f_woready_258; // @[RegisterRouter.scala:87:24] wire _out_T_2939 = ~out_rimask_258; // @[RegisterRouter.scala:87:24] wire _out_T_2940 = ~out_wimask_258; // @[RegisterRouter.scala:87:24] wire _out_T_2941 = ~out_romask_258; // @[RegisterRouter.scala:87:24] wire _out_T_2942 = ~out_womask_258; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2944 = _out_T_2943; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_210 = _out_T_2944; // @[RegisterRouter.scala:87:24] wire out_rimask_259 = \|_out_rimask_T_259; // @[RegisterRouter.scala:87:24] wire out_wimask_259 = &_out_wimask_T_259; // @[RegisterRouter.scala:87:24] wire out_romask_259 = \|_out_romask_T_259; // @[RegisterRouter.scala:87:24] wire out_womask_259 = &_out_womask_T_259; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_259 = out_rivalid_1_113 & out_rimask_259; // @[RegisterRouter.scala:87:24] wire _out_T_2946 = out_f_rivalid_259; // @[RegisterRouter.scala:87:24] wire out_f_roready_259 = out_roready_1_113 & out_romask_259; // @[RegisterRouter.scala:87:24] wire _out_T_2947 = out_f_roready_259; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_259 = out_wivalid_1_113 & out_wimask_259; // @[RegisterRouter.scala:87:24] wire _out_T_2948 = out_f_wivalid_259; // @[RegisterRouter.scala:87:24] wire out_f_woready_259 = out_woready_1_113 & out_womask_259; // @[RegisterRouter.scala:87:24] wire _out_T_2949 = out_f_woready_259; // @[RegisterRouter.scala:87:24] wire _out_T_2950 = ~out_rimask_259; // @[RegisterRouter.scala:87:24] wire _out_T_2951 = ~out_wimask_259; // @[RegisterRouter.scala:87:24] wire _out_T_2952 = ~out_romask_259; // @[RegisterRouter.scala:87:24] wire _out_T_2953 = ~out_womask_259; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_210 = {programBufferMem_49, _out_prepend_T_210}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2954 = out_prepend_210; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2955 = _out_T_2954; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_211 = _out_T_2955; // @[RegisterRouter.scala:87:24] wire out_rimask_260 = \|_out_rimask_T_260; // @[RegisterRouter.scala:87:24] wire out_wimask_260 = &_out_wimask_T_260; // @[RegisterRouter.scala:87:24] wire out_romask_260 = \|_out_romask_T_260; // @[RegisterRouter.scala:87:24] wire out_womask_260 = &_out_womask_T_260; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_260 = out_rivalid_1_114 & out_rimask_260; // @[RegisterRouter.scala:87:24] wire _out_T_2957 = out_f_rivalid_260; // @[RegisterRouter.scala:87:24] wire out_f_roready_260 = out_roready_1_114 & out_romask_260; // @[RegisterRouter.scala:87:24] wire _out_T_2958 = out_f_roready_260; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_260 = out_wivalid_1_114 & out_wimask_260; // @[RegisterRouter.scala:87:24] wire _out_T_2959 = out_f_wivalid_260; // @[RegisterRouter.scala:87:24] wire out_f_woready_260 = out_woready_1_114 & out_womask_260; // @[RegisterRouter.scala:87:24] wire _out_T_2960 = out_f_woready_260; // @[RegisterRouter.scala:87:24] wire _out_T_2961 = ~out_rimask_260; // @[RegisterRouter.scala:87:24] wire _out_T_2962 = ~out_wimask_260; // @[RegisterRouter.scala:87:24] wire _out_T_2963 = ~out_romask_260; // @[RegisterRouter.scala:87:24] wire _out_T_2964 = ~out_womask_260; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_211 = {programBufferMem_50, _out_prepend_T_211}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2965 = out_prepend_211; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2966 = _out_T_2965; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_212 = _out_T_2966; // @[RegisterRouter.scala:87:24] wire out_rimask_261 = \|_out_rimask_T_261; // @[RegisterRouter.scala:87:24] wire out_wimask_261 = &_out_wimask_T_261; // @[RegisterRouter.scala:87:24] wire out_romask_261 = \|_out_romask_T_261; // @[RegisterRouter.scala:87:24] wire out_womask_261 = &_out_womask_T_261; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_261 = out_rivalid_1_115 & out_rimask_261; // @[RegisterRouter.scala:87:24] wire _out_T_2968 = out_f_rivalid_261; // @[RegisterRouter.scala:87:24] wire out_f_roready_261 = out_roready_1_115 & out_romask_261; // @[RegisterRouter.scala:87:24] wire _out_T_2969 = out_f_roready_261; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_261 = out_wivalid_1_115 & out_wimask_261; // @[RegisterRouter.scala:87:24] wire _out_T_2970 = out_f_wivalid_261; // @[RegisterRouter.scala:87:24] wire out_f_woready_261 = out_woready_1_115 & out_womask_261; // @[RegisterRouter.scala:87:24] wire _out_T_2971 = out_f_woready_261; // @[RegisterRouter.scala:87:24] wire _out_T_2972 = ~out_rimask_261; // @[RegisterRouter.scala:87:24] wire _out_T_2973 = ~out_wimask_261; // @[RegisterRouter.scala:87:24] wire _out_T_2974 = ~out_romask_261; // @[RegisterRouter.scala:87:24] wire _out_T_2975 = ~out_womask_261; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_212 = {programBufferMem_51, _out_prepend_T_212}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2976 = out_prepend_212; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2977 = _out_T_2976; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_213 = _out_T_2977; // @[RegisterRouter.scala:87:24] wire out_rimask_262 = \|_out_rimask_T_262; // @[RegisterRouter.scala:87:24] wire out_wimask_262 = &_out_wimask_T_262; // @[RegisterRouter.scala:87:24] wire out_romask_262 = \|_out_romask_T_262; // @[RegisterRouter.scala:87:24] wire out_womask_262 = &_out_womask_T_262; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_262 = out_rivalid_1_116 & out_rimask_262; // @[RegisterRouter.scala:87:24] wire _out_T_2979 = out_f_rivalid_262; // @[RegisterRouter.scala:87:24] wire out_f_roready_262 = out_roready_1_116 & out_romask_262; // @[RegisterRouter.scala:87:24] wire _out_T_2980 = out_f_roready_262; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_262 = out_wivalid_1_116 & out_wimask_262; // @[RegisterRouter.scala:87:24] wire _out_T_2981 = out_f_wivalid_262; // @[RegisterRouter.scala:87:24] wire out_f_woready_262 = out_woready_1_116 & out_womask_262; // @[RegisterRouter.scala:87:24] wire _out_T_2982 = out_f_woready_262; // @[RegisterRouter.scala:87:24] wire _out_T_2983 = ~out_rimask_262; // @[RegisterRouter.scala:87:24] wire _out_T_2984 = ~out_wimask_262; // @[RegisterRouter.scala:87:24] wire _out_T_2985 = ~out_romask_262; // @[RegisterRouter.scala:87:24] wire _out_T_2986 = ~out_womask_262; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_213 = {programBufferMem_52, _out_prepend_T_213}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2987 = out_prepend_213; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2988 = _out_T_2987; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_214 = _out_T_2988; // @[RegisterRouter.scala:87:24] wire out_rimask_263 = \|_out_rimask_T_263; // @[RegisterRouter.scala:87:24] wire out_wimask_263 = &_out_wimask_T_263; // @[RegisterRouter.scala:87:24] wire out_romask_263 = \|_out_romask_T_263; // @[RegisterRouter.scala:87:24] wire out_womask_263 = &_out_womask_T_263; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_263 = out_rivalid_1_117 & out_rimask_263; // @[RegisterRouter.scala:87:24] wire _out_T_2990 = out_f_rivalid_263; // @[RegisterRouter.scala:87:24] wire out_f_roready_263 = out_roready_1_117 & out_romask_263; // @[RegisterRouter.scala:87:24] wire _out_T_2991 = out_f_roready_263; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_263 = out_wivalid_1_117 & out_wimask_263; // @[RegisterRouter.scala:87:24] wire _out_T_2992 = out_f_wivalid_263; // @[RegisterRouter.scala:87:24] wire out_f_woready_263 = out_woready_1_117 & out_womask_263; // @[RegisterRouter.scala:87:24] wire _out_T_2993 = out_f_woready_263; // @[RegisterRouter.scala:87:24] wire _out_T_2994 = ~out_rimask_263; // @[RegisterRouter.scala:87:24] wire _out_T_2995 = ~out_wimask_263; // @[RegisterRouter.scala:87:24] wire _out_T_2996 = ~out_romask_263; // @[RegisterRouter.scala:87:24] wire _out_T_2997 = ~out_womask_263; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_214 = {programBufferMem_53, _out_prepend_T_214}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2998 = out_prepend_214; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2999 = _out_T_2998; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_215 = _out_T_2999; // @[RegisterRouter.scala:87:24] wire out_rimask_264 = \|_out_rimask_T_264; // @[RegisterRouter.scala:87:24] wire out_wimask_264 = &_out_wimask_T_264; // @[RegisterRouter.scala:87:24] wire out_romask_264 = \|_out_romask_T_264; // @[RegisterRouter.scala:87:24] wire out_womask_264 = &_out_womask_T_264; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_264 = out_rivalid_1_118 & out_rimask_264; // @[RegisterRouter.scala:87:24] wire _out_T_3001 = out_f_rivalid_264; // @[RegisterRouter.scala:87:24] wire out_f_roready_264 = out_roready_1_118 & out_romask_264; // @[RegisterRouter.scala:87:24] wire _out_T_3002 = out_f_roready_264; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_264 = out_wivalid_1_118 & out_wimask_264; // @[RegisterRouter.scala:87:24] wire _out_T_3003 = out_f_wivalid_264; // @[RegisterRouter.scala:87:24] wire out_f_woready_264 = out_woready_1_118 & out_womask_264; // @[RegisterRouter.scala:87:24] wire _out_T_3004 = out_f_woready_264; // @[RegisterRouter.scala:87:24] wire _out_T_3005 = ~out_rimask_264; // @[RegisterRouter.scala:87:24] wire _out_T_3006 = ~out_wimask_264; // @[RegisterRouter.scala:87:24] wire _out_T_3007 = ~out_romask_264; // @[RegisterRouter.scala:87:24] wire _out_T_3008 = ~out_womask_264; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_215 = {programBufferMem_54, _out_prepend_T_215}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3009 = out_prepend_215; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3010 = _out_T_3009; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_216 = _out_T_3010; // @[RegisterRouter.scala:87:24] wire out_rimask_265 = \|_out_rimask_T_265; // @[RegisterRouter.scala:87:24] wire out_wimask_265 = &_out_wimask_T_265; // @[RegisterRouter.scala:87:24] wire out_romask_265 = \|_out_romask_T_265; // @[RegisterRouter.scala:87:24] wire out_womask_265 = &_out_womask_T_265; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_265 = out_rivalid_1_119 & out_rimask_265; // @[RegisterRouter.scala:87:24] wire _out_T_3012 = out_f_rivalid_265; // @[RegisterRouter.scala:87:24] wire out_f_roready_265 = out_roready_1_119 & out_romask_265; // @[RegisterRouter.scala:87:24] wire _out_T_3013 = out_f_roready_265; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_265 = out_wivalid_1_119 & out_wimask_265; // @[RegisterRouter.scala:87:24] wire _out_T_3014 = out_f_wivalid_265; // @[RegisterRouter.scala:87:24] wire out_f_woready_265 = out_woready_1_119 & out_womask_265; // @[RegisterRouter.scala:87:24] wire _out_T_3015 = out_f_woready_265; // @[RegisterRouter.scala:87:24] wire _out_T_3016 = ~out_rimask_265; // @[RegisterRouter.scala:87:24] wire _out_T_3017 = ~out_wimask_265; // @[RegisterRouter.scala:87:24] wire _out_T_3018 = ~out_romask_265; // @[RegisterRouter.scala:87:24] wire _out_T_3019 = ~out_womask_265; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_216 = {programBufferMem_55, _out_prepend_T_216}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3020 = out_prepend_216; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3021 = _out_T_3020; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_110 = _out_T_3021; // @[MuxLiteral.scala:49:48] wire out_rimask_266 = \|_out_rimask_T_266; // @[RegisterRouter.scala:87:24] wire out_wimask_266 = &_out_wimask_T_266; // @[RegisterRouter.scala:87:24] wire out_romask_266 = \|_out_romask_T_266; // @[RegisterRouter.scala:87:24] wire out_womask_266 = &_out_womask_T_266; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_266 = out_rivalid_1_120 & out_rimask_266; // @[RegisterRouter.scala:87:24] wire _out_T_3023 = out_f_rivalid_266; // @[RegisterRouter.scala:87:24] wire out_f_roready_266 = out_roready_1_120 & out_romask_266; // @[RegisterRouter.scala:87:24] wire _out_T_3024 = out_f_roready_266; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_266 = out_wivalid_1_120 & out_wimask_266; // @[RegisterRouter.scala:87:24] wire out_f_woready_266 = out_woready_1_120 & out_womask_266; // @[RegisterRouter.scala:87:24] wire _out_T_3025 = ~out_rimask_266; // @[RegisterRouter.scala:87:24] wire _out_T_3026 = ~out_wimask_266; // @[RegisterRouter.scala:87:24] wire _out_T_3027 = ~out_romask_266; // @[RegisterRouter.scala:87:24] wire _out_T_3028 = ~out_womask_266; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3030 = _out_T_3029; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_217 = _out_T_3030; // @[RegisterRouter.scala:87:24] wire out_rimask_267 = \|_out_rimask_T_267; // @[RegisterRouter.scala:87:24] wire out_wimask_267 = &_out_wimask_T_267; // @[RegisterRouter.scala:87:24] wire out_romask_267 = \|_out_romask_T_267; // @[RegisterRouter.scala:87:24] wire out_womask_267 = &_out_womask_T_267; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_267 = out_rivalid_1_121 & out_rimask_267; // @[RegisterRouter.scala:87:24] wire _out_T_3032 = out_f_rivalid_267; // @[RegisterRouter.scala:87:24] wire out_f_roready_267 = out_roready_1_121 & out_romask_267; // @[RegisterRouter.scala:87:24] wire _out_T_3033 = out_f_roready_267; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_267 = out_wivalid_1_121 & out_wimask_267; // @[RegisterRouter.scala:87:24] wire out_f_woready_267 = out_woready_1_121 & out_womask_267; // @[RegisterRouter.scala:87:24] wire _out_T_3034 = ~out_rimask_267; // @[RegisterRouter.scala:87:24] wire _out_T_3035 = ~out_wimask_267; // @[RegisterRouter.scala:87:24] wire _out_T_3036 = ~out_romask_267; // @[RegisterRouter.scala:87:24] wire _out_T_3037 = ~out_womask_267; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_217 = {hi_546, flags_0_go, _out_prepend_T_217}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3038 = out_prepend_217; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3039 = _out_T_3038; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_218 = _out_T_3039; // @[RegisterRouter.scala:87:24] wire out_rimask_268 = \|_out_rimask_T_268; // @[RegisterRouter.scala:87:24] wire out_wimask_268 = &_out_wimask_T_268; // @[RegisterRouter.scala:87:24] wire out_romask_268 = \|_out_romask_T_268; // @[RegisterRouter.scala:87:24] wire out_womask_268 = &_out_womask_T_268; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_268 = out_rivalid_1_122 & out_rimask_268; // @[RegisterRouter.scala:87:24] wire _out_T_3041 = out_f_rivalid_268; // @[RegisterRouter.scala:87:24] wire out_f_roready_268 = out_roready_1_122 & out_romask_268; // @[RegisterRouter.scala:87:24] wire _out_T_3042 = out_f_roready_268; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_268 = out_wivalid_1_122 & out_wimask_268; // @[RegisterRouter.scala:87:24] wire out_f_woready_268 = out_woready_1_122 & out_womask_268; // @[RegisterRouter.scala:87:24] wire _out_T_3043 = ~out_rimask_268; // @[RegisterRouter.scala:87:24] wire _out_T_3044 = ~out_wimask_268; // @[RegisterRouter.scala:87:24] wire _out_T_3045 = ~out_romask_268; // @[RegisterRouter.scala:87:24] wire _out_T_3046 = ~out_womask_268; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_218 = {hi_547, flags_0_go, _out_prepend_T_218}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3047 = out_prepend_218; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3048 = _out_T_3047; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_219 = _out_T_3048; // @[RegisterRouter.scala:87:24] wire out_rimask_269 = \|_out_rimask_T_269; // @[RegisterRouter.scala:87:24] wire out_wimask_269 = &_out_wimask_T_269; // @[RegisterRouter.scala:87:24] wire out_romask_269 = \|_out_romask_T_269; // @[RegisterRouter.scala:87:24] wire out_womask_269 = &_out_womask_T_269; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_269 = out_rivalid_1_123 & out_rimask_269; // @[RegisterRouter.scala:87:24] wire _out_T_3050 = out_f_rivalid_269; // @[RegisterRouter.scala:87:24] wire out_f_roready_269 = out_roready_1_123 & out_romask_269; // @[RegisterRouter.scala:87:24] wire _out_T_3051 = out_f_roready_269; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_269 = out_wivalid_1_123 & out_wimask_269; // @[RegisterRouter.scala:87:24] wire out_f_woready_269 = out_woready_1_123 & out_womask_269; // @[RegisterRouter.scala:87:24] wire _out_T_3052 = ~out_rimask_269; // @[RegisterRouter.scala:87:24] wire _out_T_3053 = ~out_wimask_269; // @[RegisterRouter.scala:87:24] wire _out_T_3054 = ~out_romask_269; // @[RegisterRouter.scala:87:24] wire _out_T_3055 = ~out_womask_269; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_219 = {hi_548, flags_0_go, _out_prepend_T_219}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3056 = out_prepend_219; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3057 = _out_T_3056; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_220 = _out_T_3057; // @[RegisterRouter.scala:87:24] wire out_rimask_270 = \|_out_rimask_T_270; // @[RegisterRouter.scala:87:24] wire out_wimask_270 = &_out_wimask_T_270; // @[RegisterRouter.scala:87:24] wire out_romask_270 = \|_out_romask_T_270; // @[RegisterRouter.scala:87:24] wire out_womask_270 = &_out_womask_T_270; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_270 = out_rivalid_1_124 & out_rimask_270; // @[RegisterRouter.scala:87:24] wire _out_T_3059 = out_f_rivalid_270; // @[RegisterRouter.scala:87:24] wire out_f_roready_270 = out_roready_1_124 & out_romask_270; // @[RegisterRouter.scala:87:24] wire _out_T_3060 = out_f_roready_270; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_270 = out_wivalid_1_124 & out_wimask_270; // @[RegisterRouter.scala:87:24] wire out_f_woready_270 = out_woready_1_124 & out_womask_270; // @[RegisterRouter.scala:87:24] wire _out_T_3061 = ~out_rimask_270; // @[RegisterRouter.scala:87:24] wire _out_T_3062 = ~out_wimask_270; // @[RegisterRouter.scala:87:24] wire _out_T_3063 = ~out_romask_270; // @[RegisterRouter.scala:87:24] wire _out_T_3064 = ~out_womask_270; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_220 = {hi_549, flags_0_go, _out_prepend_T_220}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3065 = out_prepend_220; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3066 = _out_T_3065; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_221 = _out_T_3066; // @[RegisterRouter.scala:87:24] wire out_rimask_271 = \|_out_rimask_T_271; // @[RegisterRouter.scala:87:24] wire out_wimask_271 = &_out_wimask_T_271; // @[RegisterRouter.scala:87:24] wire out_romask_271 = \|_out_romask_T_271; // @[RegisterRouter.scala:87:24] wire out_womask_271 = &_out_womask_T_271; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_271 = out_rivalid_1_125 & out_rimask_271; // @[RegisterRouter.scala:87:24] wire _out_T_3068 = out_f_rivalid_271; // @[RegisterRouter.scala:87:24] wire out_f_roready_271 = out_roready_1_125 & out_romask_271; // @[RegisterRouter.scala:87:24] wire _out_T_3069 = out_f_roready_271; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_271 = out_wivalid_1_125 & out_wimask_271; // @[RegisterRouter.scala:87:24] wire out_f_woready_271 = out_woready_1_125 & out_womask_271; // @[RegisterRouter.scala:87:24] wire _out_T_3070 = ~out_rimask_271; // @[RegisterRouter.scala:87:24] wire _out_T_3071 = ~out_wimask_271; // @[RegisterRouter.scala:87:24] wire _out_T_3072 = ~out_romask_271; // @[RegisterRouter.scala:87:24] wire _out_T_3073 = ~out_womask_271; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_221 = {hi_550, flags_0_go, _out_prepend_T_221}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3074 = out_prepend_221; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3075 = _out_T_3074; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_222 = _out_T_3075; // @[RegisterRouter.scala:87:24] wire out_rimask_272 = \|_out_rimask_T_272; // @[RegisterRouter.scala:87:24] wire out_wimask_272 = &_out_wimask_T_272; // @[RegisterRouter.scala:87:24] wire out_romask_272 = \|_out_romask_T_272; // @[RegisterRouter.scala:87:24] wire out_womask_272 = &_out_womask_T_272; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_272 = out_rivalid_1_126 & out_rimask_272; // @[RegisterRouter.scala:87:24] wire _out_T_3077 = out_f_rivalid_272; // @[RegisterRouter.scala:87:24] wire out_f_roready_272 = out_roready_1_126 & out_romask_272; // @[RegisterRouter.scala:87:24] wire _out_T_3078 = out_f_roready_272; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_272 = out_wivalid_1_126 & out_wimask_272; // @[RegisterRouter.scala:87:24] wire out_f_woready_272 = out_woready_1_126 & out_womask_272; // @[RegisterRouter.scala:87:24] wire _out_T_3079 = ~out_rimask_272; // @[RegisterRouter.scala:87:24] wire _out_T_3080 = ~out_wimask_272; // @[RegisterRouter.scala:87:24] wire _out_T_3081 = ~out_romask_272; // @[RegisterRouter.scala:87:24] wire _out_T_3082 = ~out_womask_272; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_222 = {hi_551, flags_0_go, _out_prepend_T_222}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3083 = out_prepend_222; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3084 = _out_T_3083; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_223 = _out_T_3084; // @[RegisterRouter.scala:87:24] wire out_rimask_273 = \|_out_rimask_T_273; // @[RegisterRouter.scala:87:24] wire out_wimask_273 = &_out_wimask_T_273; // @[RegisterRouter.scala:87:24] wire out_romask_273 = \|_out_romask_T_273; // @[RegisterRouter.scala:87:24] wire out_womask_273 = &_out_womask_T_273; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_273 = out_rivalid_1_127 & out_rimask_273; // @[RegisterRouter.scala:87:24] wire _out_T_3086 = out_f_rivalid_273; // @[RegisterRouter.scala:87:24] wire out_f_roready_273 = out_roready_1_127 & out_romask_273; // @[RegisterRouter.scala:87:24] wire _out_T_3087 = out_f_roready_273; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_273 = out_wivalid_1_127 & out_wimask_273; // @[RegisterRouter.scala:87:24] wire out_f_woready_273 = out_woready_1_127 & out_womask_273; // @[RegisterRouter.scala:87:24] wire _out_T_3088 = ~out_rimask_273; // @[RegisterRouter.scala:87:24] wire _out_T_3089 = ~out_wimask_273; // @[RegisterRouter.scala:87:24] wire _out_T_3090 = ~out_romask_273; // @[RegisterRouter.scala:87:24] wire _out_T_3091 = ~out_womask_273; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_223 = {hi_552, flags_0_go, _out_prepend_T_223}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3092 = out_prepend_223; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3093 = _out_T_3092; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_196 = _out_T_3093; // @[MuxLiteral.scala:49:48] wire out_rimask_274 = \|_out_rimask_T_274; // @[RegisterRouter.scala:87:24] wire out_wimask_274 = &_out_wimask_T_274; // @[RegisterRouter.scala:87:24] wire out_romask_274 = \|_out_romask_T_274; // @[RegisterRouter.scala:87:24] wire out_womask_274 = &_out_womask_T_274; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_274 = out_rivalid_1_128 & out_rimask_274; // @[RegisterRouter.scala:87:24] wire _out_T_3095 = out_f_rivalid_274; // @[RegisterRouter.scala:87:24] wire out_f_roready_274 = out_roready_1_128 & out_romask_274; // @[RegisterRouter.scala:87:24] wire _out_T_3096 = out_f_roready_274; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_274 = out_wivalid_1_128 & out_wimask_274; // @[RegisterRouter.scala:87:24] wire out_f_woready_274 = out_woready_1_128 & out_womask_274; // @[RegisterRouter.scala:87:24] wire _out_T_3097 = ~out_rimask_274; // @[RegisterRouter.scala:87:24] wire _out_T_3098 = ~out_wimask_274; // @[RegisterRouter.scala:87:24] wire _out_T_3099 = ~out_romask_274; // @[RegisterRouter.scala:87:24] wire _out_T_3100 = ~out_womask_274; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3102 = _out_T_3101; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_224 = _out_T_3102; // @[RegisterRouter.scala:87:24] wire out_rimask_275 = \|_out_rimask_T_275; // @[RegisterRouter.scala:87:24] wire out_wimask_275 = &_out_wimask_T_275; // @[RegisterRouter.scala:87:24] wire out_romask_275 = \|_out_romask_T_275; // @[RegisterRouter.scala:87:24] wire out_womask_275 = &_out_womask_T_275; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_275 = out_rivalid_1_129 & out_rimask_275; // @[RegisterRouter.scala:87:24] wire _out_T_3104 = out_f_rivalid_275; // @[RegisterRouter.scala:87:24] wire out_f_roready_275 = out_roready_1_129 & out_romask_275; // @[RegisterRouter.scala:87:24] wire _out_T_3105 = out_f_roready_275; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_275 = out_wivalid_1_129 & out_wimask_275; // @[RegisterRouter.scala:87:24] wire out_f_woready_275 = out_woready_1_129 & out_womask_275; // @[RegisterRouter.scala:87:24] wire _out_T_3106 = ~out_rimask_275; // @[RegisterRouter.scala:87:24] wire _out_T_3107 = ~out_wimask_275; // @[RegisterRouter.scala:87:24] wire _out_T_3108 = ~out_romask_275; // @[RegisterRouter.scala:87:24] wire _out_T_3109 = ~out_womask_275; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_224 = {hi_234, flags_0_go, _out_prepend_T_224}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3110 = out_prepend_224; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3111 = _out_T_3110; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_225 = _out_T_3111; // @[RegisterRouter.scala:87:24] wire out_rimask_276 = \|_out_rimask_T_276; // @[RegisterRouter.scala:87:24] wire out_wimask_276 = &_out_wimask_T_276; // @[RegisterRouter.scala:87:24] wire out_romask_276 = \|_out_romask_T_276; // @[RegisterRouter.scala:87:24] wire out_womask_276 = &_out_womask_T_276; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_276 = out_rivalid_1_130 & out_rimask_276; // @[RegisterRouter.scala:87:24] wire _out_T_3113 = out_f_rivalid_276; // @[RegisterRouter.scala:87:24] wire out_f_roready_276 = out_roready_1_130 & out_romask_276; // @[RegisterRouter.scala:87:24] wire _out_T_3114 = out_f_roready_276; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_276 = out_wivalid_1_130 & out_wimask_276; // @[RegisterRouter.scala:87:24] wire out_f_woready_276 = out_woready_1_130 & out_womask_276; // @[RegisterRouter.scala:87:24] wire _out_T_3115 = ~out_rimask_276; // @[RegisterRouter.scala:87:24] wire _out_T_3116 = ~out_wimask_276; // @[RegisterRouter.scala:87:24] wire _out_T_3117 = ~out_romask_276; // @[RegisterRouter.scala:87:24] wire _out_T_3118 = ~out_womask_276; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_225 = {hi_235, flags_0_go, _out_prepend_T_225}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3119 = out_prepend_225; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3120 = _out_T_3119; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_226 = _out_T_3120; // @[RegisterRouter.scala:87:24] wire out_rimask_277 = \|_out_rimask_T_277; // @[RegisterRouter.scala:87:24] wire out_wimask_277 = &_out_wimask_T_277; // @[RegisterRouter.scala:87:24] wire out_romask_277 = \|_out_romask_T_277; // @[RegisterRouter.scala:87:24] wire out_womask_277 = &_out_womask_T_277; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_277 = out_rivalid_1_131 & out_rimask_277; // @[RegisterRouter.scala:87:24] wire _out_T_3122 = out_f_rivalid_277; // @[RegisterRouter.scala:87:24] wire out_f_roready_277 = out_roready_1_131 & out_romask_277; // @[RegisterRouter.scala:87:24] wire _out_T_3123 = out_f_roready_277; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_277 = out_wivalid_1_131 & out_wimask_277; // @[RegisterRouter.scala:87:24] wire out_f_woready_277 = out_woready_1_131 & out_womask_277; // @[RegisterRouter.scala:87:24] wire _out_T_3124 = ~out_rimask_277; // @[RegisterRouter.scala:87:24] wire _out_T_3125 = ~out_wimask_277; // @[RegisterRouter.scala:87:24] wire _out_T_3126 = ~out_romask_277; // @[RegisterRouter.scala:87:24] wire _out_T_3127 = ~out_womask_277; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_226 = {hi_236, flags_0_go, _out_prepend_T_226}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3128 = out_prepend_226; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3129 = _out_T_3128; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_227 = _out_T_3129; // @[RegisterRouter.scala:87:24] wire out_rimask_278 = \|_out_rimask_T_278; // @[RegisterRouter.scala:87:24] wire out_wimask_278 = &_out_wimask_T_278; // @[RegisterRouter.scala:87:24] wire out_romask_278 = \|_out_romask_T_278; // @[RegisterRouter.scala:87:24] wire out_womask_278 = &_out_womask_T_278; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_278 = out_rivalid_1_132 & out_rimask_278; // @[RegisterRouter.scala:87:24] wire _out_T_3131 = out_f_rivalid_278; // @[RegisterRouter.scala:87:24] wire out_f_roready_278 = out_roready_1_132 & out_romask_278; // @[RegisterRouter.scala:87:24] wire _out_T_3132 = out_f_roready_278; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_278 = out_wivalid_1_132 & out_wimask_278; // @[RegisterRouter.scala:87:24] wire out_f_woready_278 = out_woready_1_132 & out_womask_278; // @[RegisterRouter.scala:87:24] wire _out_T_3133 = ~out_rimask_278; // @[RegisterRouter.scala:87:24] wire _out_T_3134 = ~out_wimask_278; // @[RegisterRouter.scala:87:24] wire _out_T_3135 = ~out_romask_278; // @[RegisterRouter.scala:87:24] wire _out_T_3136 = ~out_womask_278; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_227 = {hi_237, flags_0_go, _out_prepend_T_227}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3137 = out_prepend_227; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3138 = _out_T_3137; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_228 = _out_T_3138; // @[RegisterRouter.scala:87:24] wire out_rimask_279 = \|_out_rimask_T_279; // @[RegisterRouter.scala:87:24] wire out_wimask_279 = &_out_wimask_T_279; // @[RegisterRouter.scala:87:24] wire out_romask_279 = \|_out_romask_T_279; // @[RegisterRouter.scala:87:24] wire out_womask_279 = &_out_womask_T_279; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_279 = out_rivalid_1_133 & out_rimask_279; // @[RegisterRouter.scala:87:24] wire _out_T_3140 = out_f_rivalid_279; // @[RegisterRouter.scala:87:24] wire out_f_roready_279 = out_roready_1_133 & out_romask_279; // @[RegisterRouter.scala:87:24] wire _out_T_3141 = out_f_roready_279; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_279 = out_wivalid_1_133 & out_wimask_279; // @[RegisterRouter.scala:87:24] wire out_f_woready_279 = out_woready_1_133 & out_womask_279; // @[RegisterRouter.scala:87:24] wire _out_T_3142 = ~out_rimask_279; // @[RegisterRouter.scala:87:24] wire _out_T_3143 = ~out_wimask_279; // @[RegisterRouter.scala:87:24] wire _out_T_3144 = ~out_romask_279; // @[RegisterRouter.scala:87:24] wire _out_T_3145 = ~out_womask_279; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_228 = {hi_238, flags_0_go, _out_prepend_T_228}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3146 = out_prepend_228; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3147 = _out_T_3146; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_229 = _out_T_3147; // @[RegisterRouter.scala:87:24] wire out_rimask_280 = \|_out_rimask_T_280; // @[RegisterRouter.scala:87:24] wire out_wimask_280 = &_out_wimask_T_280; // @[RegisterRouter.scala:87:24] wire out_romask_280 = \|_out_romask_T_280; // @[RegisterRouter.scala:87:24] wire out_womask_280 = &_out_womask_T_280; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_280 = out_rivalid_1_134 & out_rimask_280; // @[RegisterRouter.scala:87:24] wire _out_T_3149 = out_f_rivalid_280; // @[RegisterRouter.scala:87:24] wire out_f_roready_280 = out_roready_1_134 & out_romask_280; // @[RegisterRouter.scala:87:24] wire _out_T_3150 = out_f_roready_280; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_280 = out_wivalid_1_134 & out_wimask_280; // @[RegisterRouter.scala:87:24] wire out_f_woready_280 = out_woready_1_134 & out_womask_280; // @[RegisterRouter.scala:87:24] wire _out_T_3151 = ~out_rimask_280; // @[RegisterRouter.scala:87:24] wire _out_T_3152 = ~out_wimask_280; // @[RegisterRouter.scala:87:24] wire _out_T_3153 = ~out_romask_280; // @[RegisterRouter.scala:87:24] wire _out_T_3154 = ~out_womask_280; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_229 = {hi_239, flags_0_go, _out_prepend_T_229}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3155 = out_prepend_229; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3156 = _out_T_3155; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_230 = _out_T_3156; // @[RegisterRouter.scala:87:24] wire out_rimask_281 = \|_out_rimask_T_281; // @[RegisterRouter.scala:87:24] wire out_wimask_281 = &_out_wimask_T_281; // @[RegisterRouter.scala:87:24] wire out_romask_281 = \|_out_romask_T_281; // @[RegisterRouter.scala:87:24] wire out_womask_281 = &_out_womask_T_281; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_281 = out_rivalid_1_135 & out_rimask_281; // @[RegisterRouter.scala:87:24] wire _out_T_3158 = out_f_rivalid_281; // @[RegisterRouter.scala:87:24] wire out_f_roready_281 = out_roready_1_135 & out_romask_281; // @[RegisterRouter.scala:87:24] wire _out_T_3159 = out_f_roready_281; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_281 = out_wivalid_1_135 & out_wimask_281; // @[RegisterRouter.scala:87:24] wire out_f_woready_281 = out_woready_1_135 & out_womask_281; // @[RegisterRouter.scala:87:24] wire _out_T_3160 = ~out_rimask_281; // @[RegisterRouter.scala:87:24] wire _out_T_3161 = ~out_wimask_281; // @[RegisterRouter.scala:87:24] wire _out_T_3162 = ~out_romask_281; // @[RegisterRouter.scala:87:24] wire _out_T_3163 = ~out_womask_281; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_230 = {hi_240, flags_0_go, _out_prepend_T_230}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3164 = out_prepend_230; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3165 = _out_T_3164; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_157 = _out_T_3165; // @[MuxLiteral.scala:49:48] wire out_rimask_282 = \|_out_rimask_T_282; // @[RegisterRouter.scala:87:24] wire out_wimask_282 = &_out_wimask_T_282; // @[RegisterRouter.scala:87:24] wire out_romask_282 = \|_out_romask_T_282; // @[RegisterRouter.scala:87:24] wire out_womask_282 = &_out_womask_T_282; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_282 = out_rivalid_1_136 & out_rimask_282; // @[RegisterRouter.scala:87:24] wire _out_T_3167 = out_f_rivalid_282; // @[RegisterRouter.scala:87:24] wire out_f_roready_282 = out_roready_1_136 & out_romask_282; // @[RegisterRouter.scala:87:24] wire _out_T_3168 = out_f_roready_282; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_282 = out_wivalid_1_136 & out_wimask_282; // @[RegisterRouter.scala:87:24] wire out_f_woready_282 = out_woready_1_136 & out_womask_282; // @[RegisterRouter.scala:87:24] wire _out_T_3169 = ~out_rimask_282; // @[RegisterRouter.scala:87:24] wire _out_T_3170 = ~out_wimask_282; // @[RegisterRouter.scala:87:24] wire _out_T_3171 = ~out_romask_282; // @[RegisterRouter.scala:87:24] wire _out_T_3172 = ~out_womask_282; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3174 = _out_T_3173; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_231 = _out_T_3174; // @[RegisterRouter.scala:87:24] wire out_rimask_283 = \|_out_rimask_T_283; // @[RegisterRouter.scala:87:24] wire out_wimask_283 = &_out_wimask_T_283; // @[RegisterRouter.scala:87:24] wire out_romask_283 = \|_out_romask_T_283; // @[RegisterRouter.scala:87:24] wire out_womask_283 = &_out_womask_T_283; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_283 = out_rivalid_1_137 & out_rimask_283; // @[RegisterRouter.scala:87:24] wire _out_T_3176 = out_f_rivalid_283; // @[RegisterRouter.scala:87:24] wire out_f_roready_283 = out_roready_1_137 & out_romask_283; // @[RegisterRouter.scala:87:24] wire _out_T_3177 = out_f_roready_283; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_283 = out_wivalid_1_137 & out_wimask_283; // @[RegisterRouter.scala:87:24] wire out_f_woready_283 = out_woready_1_137 & out_womask_283; // @[RegisterRouter.scala:87:24] wire _out_T_3178 = ~out_rimask_283; // @[RegisterRouter.scala:87:24] wire _out_T_3179 = ~out_wimask_283; // @[RegisterRouter.scala:87:24] wire _out_T_3180 = ~out_romask_283; // @[RegisterRouter.scala:87:24] wire _out_T_3181 = ~out_womask_283; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_231 = {hi_490, flags_0_go, _out_prepend_T_231}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3182 = out_prepend_231; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3183 = _out_T_3182; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_232 = _out_T_3183; // @[RegisterRouter.scala:87:24] wire out_rimask_284 = \|_out_rimask_T_284; // @[RegisterRouter.scala:87:24] wire out_wimask_284 = &_out_wimask_T_284; // @[RegisterRouter.scala:87:24] wire out_romask_284 = \|_out_romask_T_284; // @[RegisterRouter.scala:87:24] wire out_womask_284 = &_out_womask_T_284; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_284 = out_rivalid_1_138 & out_rimask_284; // @[RegisterRouter.scala:87:24] wire _out_T_3185 = out_f_rivalid_284; // @[RegisterRouter.scala:87:24] wire out_f_roready_284 = out_roready_1_138 & out_romask_284; // @[RegisterRouter.scala:87:24] wire _out_T_3186 = out_f_roready_284; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_284 = out_wivalid_1_138 & out_wimask_284; // @[RegisterRouter.scala:87:24] wire out_f_woready_284 = out_woready_1_138 & out_womask_284; // @[RegisterRouter.scala:87:24] wire _out_T_3187 = ~out_rimask_284; // @[RegisterRouter.scala:87:24] wire _out_T_3188 = ~out_wimask_284; // @[RegisterRouter.scala:87:24] wire _out_T_3189 = ~out_romask_284; // @[RegisterRouter.scala:87:24] wire _out_T_3190 = ~out_womask_284; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_232 = {hi_491, flags_0_go, _out_prepend_T_232}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3191 = out_prepend_232; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3192 = _out_T_3191; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_233 = _out_T_3192; // @[RegisterRouter.scala:87:24] wire out_rimask_285 = \|_out_rimask_T_285; // @[RegisterRouter.scala:87:24] wire out_wimask_285 = &_out_wimask_T_285; // @[RegisterRouter.scala:87:24] wire out_romask_285 = \|_out_romask_T_285; // @[RegisterRouter.scala:87:24] wire out_womask_285 = &_out_womask_T_285; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_285 = out_rivalid_1_139 & out_rimask_285; // @[RegisterRouter.scala:87:24] wire _out_T_3194 = out_f_rivalid_285; // @[RegisterRouter.scala:87:24] wire out_f_roready_285 = out_roready_1_139 & out_romask_285; // @[RegisterRouter.scala:87:24] wire _out_T_3195 = out_f_roready_285; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_285 = out_wivalid_1_139 & out_wimask_285; // @[RegisterRouter.scala:87:24] wire out_f_woready_285 = out_woready_1_139 & out_womask_285; // @[RegisterRouter.scala:87:24] wire _out_T_3196 = ~out_rimask_285; // @[RegisterRouter.scala:87:24] wire _out_T_3197 = ~out_wimask_285; // @[RegisterRouter.scala:87:24] wire _out_T_3198 = ~out_romask_285; // @[RegisterRouter.scala:87:24] wire _out_T_3199 = ~out_womask_285; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_233 = {hi_492, flags_0_go, _out_prepend_T_233}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3200 = out_prepend_233; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3201 = _out_T_3200; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_234 = _out_T_3201; // @[RegisterRouter.scala:87:24] wire out_rimask_286 = \|_out_rimask_T_286; // @[RegisterRouter.scala:87:24] wire out_wimask_286 = &_out_wimask_T_286; // @[RegisterRouter.scala:87:24] wire out_romask_286 = \|_out_romask_T_286; // @[RegisterRouter.scala:87:24] wire out_womask_286 = &_out_womask_T_286; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_286 = out_rivalid_1_140 & out_rimask_286; // @[RegisterRouter.scala:87:24] wire _out_T_3203 = out_f_rivalid_286; // @[RegisterRouter.scala:87:24] wire out_f_roready_286 = out_roready_1_140 & out_romask_286; // @[RegisterRouter.scala:87:24] wire _out_T_3204 = out_f_roready_286; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_286 = out_wivalid_1_140 & out_wimask_286; // @[RegisterRouter.scala:87:24] wire out_f_woready_286 = out_woready_1_140 & out_womask_286; // @[RegisterRouter.scala:87:24] wire _out_T_3205 = ~out_rimask_286; // @[RegisterRouter.scala:87:24] wire _out_T_3206 = ~out_wimask_286; // @[RegisterRouter.scala:87:24] wire _out_T_3207 = ~out_romask_286; // @[RegisterRouter.scala:87:24] wire _out_T_3208 = ~out_womask_286; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_234 = {hi_493, flags_0_go, _out_prepend_T_234}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3209 = out_prepend_234; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3210 = _out_T_3209; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_235 = _out_T_3210; // @[RegisterRouter.scala:87:24] wire out_rimask_287 = \|_out_rimask_T_287; // @[RegisterRouter.scala:87:24] wire out_wimask_287 = &_out_wimask_T_287; // @[RegisterRouter.scala:87:24] wire out_romask_287 = \|_out_romask_T_287; // @[RegisterRouter.scala:87:24] wire out_womask_287 = &_out_womask_T_287; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_287 = out_rivalid_1_141 & out_rimask_287; // @[RegisterRouter.scala:87:24] wire _out_T_3212 = out_f_rivalid_287; // @[RegisterRouter.scala:87:24] wire out_f_roready_287 = out_roready_1_141 & out_romask_287; // @[RegisterRouter.scala:87:24] wire _out_T_3213 = out_f_roready_287; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_287 = out_wivalid_1_141 & out_wimask_287; // @[RegisterRouter.scala:87:24] wire out_f_woready_287 = out_woready_1_141 & out_womask_287; // @[RegisterRouter.scala:87:24] wire _out_T_3214 = ~out_rimask_287; // @[RegisterRouter.scala:87:24] wire _out_T_3215 = ~out_wimask_287; // @[RegisterRouter.scala:87:24] wire _out_T_3216 = ~out_romask_287; // @[RegisterRouter.scala:87:24] wire _out_T_3217 = ~out_womask_287; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_235 = {hi_494, flags_0_go, _out_prepend_T_235}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3218 = out_prepend_235; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3219 = _out_T_3218; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_236 = _out_T_3219; // @[RegisterRouter.scala:87:24] wire out_rimask_288 = \|_out_rimask_T_288; // @[RegisterRouter.scala:87:24] wire out_wimask_288 = &_out_wimask_T_288; // @[RegisterRouter.scala:87:24] wire out_romask_288 = \|_out_romask_T_288; // @[RegisterRouter.scala:87:24] wire out_womask_288 = &_out_womask_T_288; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_288 = out_rivalid_1_142 & out_rimask_288; // @[RegisterRouter.scala:87:24] wire _out_T_3221 = out_f_rivalid_288; // @[RegisterRouter.scala:87:24] wire out_f_roready_288 = out_roready_1_142 & out_romask_288; // @[RegisterRouter.scala:87:24] wire _out_T_3222 = out_f_roready_288; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_288 = out_wivalid_1_142 & out_wimask_288; // @[RegisterRouter.scala:87:24] wire out_f_woready_288 = out_woready_1_142 & out_womask_288; // @[RegisterRouter.scala:87:24] wire _out_T_3223 = ~out_rimask_288; // @[RegisterRouter.scala:87:24] wire _out_T_3224 = ~out_wimask_288; // @[RegisterRouter.scala:87:24] wire _out_T_3225 = ~out_romask_288; // @[RegisterRouter.scala:87:24] wire _out_T_3226 = ~out_womask_288; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_236 = {hi_495, flags_0_go, _out_prepend_T_236}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3227 = out_prepend_236; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3228 = _out_T_3227; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_237 = _out_T_3228; // @[RegisterRouter.scala:87:24] wire out_rimask_289 = \|_out_rimask_T_289; // @[RegisterRouter.scala:87:24] wire out_wimask_289 = &_out_wimask_T_289; // @[RegisterRouter.scala:87:24] wire out_romask_289 = \|_out_romask_T_289; // @[RegisterRouter.scala:87:24] wire out_womask_289 = &_out_womask_T_289; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_289 = out_rivalid_1_143 & out_rimask_289; // @[RegisterRouter.scala:87:24] wire _out_T_3230 = out_f_rivalid_289; // @[RegisterRouter.scala:87:24] wire out_f_roready_289 = out_roready_1_143 & out_romask_289; // @[RegisterRouter.scala:87:24] wire _out_T_3231 = out_f_roready_289; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_289 = out_wivalid_1_143 & out_wimask_289; // @[RegisterRouter.scala:87:24] wire out_f_woready_289 = out_woready_1_143 & out_womask_289; // @[RegisterRouter.scala:87:24] wire _out_T_3232 = ~out_rimask_289; // @[RegisterRouter.scala:87:24] wire _out_T_3233 = ~out_wimask_289; // @[RegisterRouter.scala:87:24] wire _out_T_3234 = ~out_romask_289; // @[RegisterRouter.scala:87:24] wire _out_T_3235 = ~out_womask_289; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_237 = {hi_496, flags_0_go, _out_prepend_T_237}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3236 = out_prepend_237; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3237 = _out_T_3236; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_189 = _out_T_3237; // @[MuxLiteral.scala:49:48] wire out_rimask_290 = \|_out_rimask_T_290; // @[RegisterRouter.scala:87:24] wire out_wimask_290 = &_out_wimask_T_290; // @[RegisterRouter.scala:87:24] wire out_romask_290 = \|_out_romask_T_290; // @[RegisterRouter.scala:87:24] wire out_womask_290 = &_out_womask_T_290; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_290 = out_rivalid_1_144 & out_rimask_290; // @[RegisterRouter.scala:87:24] wire _out_T_3239 = out_f_rivalid_290; // @[RegisterRouter.scala:87:24] wire out_f_roready_290 = out_roready_1_144 & out_romask_290; // @[RegisterRouter.scala:87:24] wire _out_T_3240 = out_f_roready_290; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_290 = out_wivalid_1_144 & out_wimask_290; // @[RegisterRouter.scala:87:24] wire out_f_woready_290 = out_woready_1_144 & out_womask_290; // @[RegisterRouter.scala:87:24] wire _out_T_3241 = ~out_rimask_290; // @[RegisterRouter.scala:87:24] wire _out_T_3242 = ~out_wimask_290; // @[RegisterRouter.scala:87:24] wire _out_T_3243 = ~out_romask_290; // @[RegisterRouter.scala:87:24] wire _out_T_3244 = ~out_womask_290; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3246 = _out_T_3245; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_238 = _out_T_3246; // @[RegisterRouter.scala:87:24] wire out_rimask_291 = \|_out_rimask_T_291; // @[RegisterRouter.scala:87:24] wire out_wimask_291 = &_out_wimask_T_291; // @[RegisterRouter.scala:87:24] wire out_romask_291 = \|_out_romask_T_291; // @[RegisterRouter.scala:87:24] wire out_womask_291 = &_out_womask_T_291; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_291 = out_rivalid_1_145 & out_rimask_291; // @[RegisterRouter.scala:87:24] wire _out_T_3248 = out_f_rivalid_291; // @[RegisterRouter.scala:87:24] wire out_f_roready_291 = out_roready_1_145 & out_romask_291; // @[RegisterRouter.scala:87:24] wire _out_T_3249 = out_f_roready_291; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_291 = out_wivalid_1_145 & out_wimask_291; // @[RegisterRouter.scala:87:24] wire out_f_woready_291 = out_woready_1_145 & out_womask_291; // @[RegisterRouter.scala:87:24] wire _out_T_3250 = ~out_rimask_291; // @[RegisterRouter.scala:87:24] wire _out_T_3251 = ~out_wimask_291; // @[RegisterRouter.scala:87:24] wire _out_T_3252 = ~out_romask_291; // @[RegisterRouter.scala:87:24] wire _out_T_3253 = ~out_womask_291; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_238 = {hi_194, flags_0_go, _out_prepend_T_238}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3254 = out_prepend_238; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3255 = _out_T_3254; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_239 = _out_T_3255; // @[RegisterRouter.scala:87:24] wire out_rimask_292 = \|_out_rimask_T_292; // @[RegisterRouter.scala:87:24] wire out_wimask_292 = &_out_wimask_T_292; // @[RegisterRouter.scala:87:24] wire out_romask_292 = \|_out_romask_T_292; // @[RegisterRouter.scala:87:24] wire out_womask_292 = &_out_womask_T_292; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_292 = out_rivalid_1_146 & out_rimask_292; // @[RegisterRouter.scala:87:24] wire _out_T_3257 = out_f_rivalid_292; // @[RegisterRouter.scala:87:24] wire out_f_roready_292 = out_roready_1_146 & out_romask_292; // @[RegisterRouter.scala:87:24] wire _out_T_3258 = out_f_roready_292; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_292 = out_wivalid_1_146 & out_wimask_292; // @[RegisterRouter.scala:87:24] wire out_f_woready_292 = out_woready_1_146 & out_womask_292; // @[RegisterRouter.scala:87:24] wire _out_T_3259 = ~out_rimask_292; // @[RegisterRouter.scala:87:24] wire _out_T_3260 = ~out_wimask_292; // @[RegisterRouter.scala:87:24] wire _out_T_3261 = ~out_romask_292; // @[RegisterRouter.scala:87:24] wire _out_T_3262 = ~out_womask_292; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_239 = {hi_195, flags_0_go, _out_prepend_T_239}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3263 = out_prepend_239; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3264 = _out_T_3263; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_240 = _out_T_3264; // @[RegisterRouter.scala:87:24] wire out_rimask_293 = \|_out_rimask_T_293; // @[RegisterRouter.scala:87:24] wire out_wimask_293 = &_out_wimask_T_293; // @[RegisterRouter.scala:87:24] wire out_romask_293 = \|_out_romask_T_293; // @[RegisterRouter.scala:87:24] wire out_womask_293 = &_out_womask_T_293; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_293 = out_rivalid_1_147 & out_rimask_293; // @[RegisterRouter.scala:87:24] wire _out_T_3266 = out_f_rivalid_293; // @[RegisterRouter.scala:87:24] wire out_f_roready_293 = out_roready_1_147 & out_romask_293; // @[RegisterRouter.scala:87:24] wire _out_T_3267 = out_f_roready_293; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_293 = out_wivalid_1_147 & out_wimask_293; // @[RegisterRouter.scala:87:24] wire out_f_woready_293 = out_woready_1_147 & out_womask_293; // @[RegisterRouter.scala:87:24] wire _out_T_3268 = ~out_rimask_293; // @[RegisterRouter.scala:87:24] wire _out_T_3269 = ~out_wimask_293; // @[RegisterRouter.scala:87:24] wire _out_T_3270 = ~out_romask_293; // @[RegisterRouter.scala:87:24] wire _out_T_3271 = ~out_womask_293; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_240 = {hi_196, flags_0_go, _out_prepend_T_240}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3272 = out_prepend_240; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3273 = _out_T_3272; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_241 = _out_T_3273; // @[RegisterRouter.scala:87:24] wire out_rimask_294 = \|_out_rimask_T_294; // @[RegisterRouter.scala:87:24] wire out_wimask_294 = &_out_wimask_T_294; // @[RegisterRouter.scala:87:24] wire out_romask_294 = \|_out_romask_T_294; // @[RegisterRouter.scala:87:24] wire out_womask_294 = &_out_womask_T_294; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_294 = out_rivalid_1_148 & out_rimask_294; // @[RegisterRouter.scala:87:24] wire _out_T_3275 = out_f_rivalid_294; // @[RegisterRouter.scala:87:24] wire out_f_roready_294 = out_roready_1_148 & out_romask_294; // @[RegisterRouter.scala:87:24] wire _out_T_3276 = out_f_roready_294; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_294 = out_wivalid_1_148 & out_wimask_294; // @[RegisterRouter.scala:87:24] wire out_f_woready_294 = out_woready_1_148 & out_womask_294; // @[RegisterRouter.scala:87:24] wire _out_T_3277 = ~out_rimask_294; // @[RegisterRouter.scala:87:24] wire _out_T_3278 = ~out_wimask_294; // @[RegisterRouter.scala:87:24] wire _out_T_3279 = ~out_romask_294; // @[RegisterRouter.scala:87:24] wire _out_T_3280 = ~out_womask_294; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_241 = {hi_197, flags_0_go, _out_prepend_T_241}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3281 = out_prepend_241; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3282 = _out_T_3281; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_242 = _out_T_3282; // @[RegisterRouter.scala:87:24] wire out_rimask_295 = \|_out_rimask_T_295; // @[RegisterRouter.scala:87:24] wire out_wimask_295 = &_out_wimask_T_295; // @[RegisterRouter.scala:87:24] wire out_romask_295 = \|_out_romask_T_295; // @[RegisterRouter.scala:87:24] wire out_womask_295 = &_out_womask_T_295; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_295 = out_rivalid_1_149 & out_rimask_295; // @[RegisterRouter.scala:87:24] wire _out_T_3284 = out_f_rivalid_295; // @[RegisterRouter.scala:87:24] wire out_f_roready_295 = out_roready_1_149 & out_romask_295; // @[RegisterRouter.scala:87:24] wire _out_T_3285 = out_f_roready_295; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_295 = out_wivalid_1_149 & out_wimask_295; // @[RegisterRouter.scala:87:24] wire out_f_woready_295 = out_woready_1_149 & out_womask_295; // @[RegisterRouter.scala:87:24] wire _out_T_3286 = ~out_rimask_295; // @[RegisterRouter.scala:87:24] wire _out_T_3287 = ~out_wimask_295; // @[RegisterRouter.scala:87:24] wire _out_T_3288 = ~out_romask_295; // @[RegisterRouter.scala:87:24] wire _out_T_3289 = ~out_womask_295; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_242 = {hi_198, flags_0_go, _out_prepend_T_242}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3290 = out_prepend_242; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3291 = _out_T_3290; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_243 = _out_T_3291; // @[RegisterRouter.scala:87:24] wire out_rimask_296 = \|_out_rimask_T_296; // @[RegisterRouter.scala:87:24] wire out_wimask_296 = &_out_wimask_T_296; // @[RegisterRouter.scala:87:24] wire out_romask_296 = \|_out_romask_T_296; // @[RegisterRouter.scala:87:24] wire out_womask_296 = &_out_womask_T_296; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_296 = out_rivalid_1_150 & out_rimask_296; // @[RegisterRouter.scala:87:24] wire _out_T_3293 = out_f_rivalid_296; // @[RegisterRouter.scala:87:24] wire out_f_roready_296 = out_roready_1_150 & out_romask_296; // @[RegisterRouter.scala:87:24] wire _out_T_3294 = out_f_roready_296; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_296 = out_wivalid_1_150 & out_wimask_296; // @[RegisterRouter.scala:87:24] wire out_f_woready_296 = out_woready_1_150 & out_womask_296; // @[RegisterRouter.scala:87:24] wire _out_T_3295 = ~out_rimask_296; // @[RegisterRouter.scala:87:24] wire _out_T_3296 = ~out_wimask_296; // @[RegisterRouter.scala:87:24] wire _out_T_3297 = ~out_romask_296; // @[RegisterRouter.scala:87:24] wire _out_T_3298 = ~out_womask_296; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_243 = {hi_199, flags_0_go, _out_prepend_T_243}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3299 = out_prepend_243; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3300 = _out_T_3299; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_244 = _out_T_3300; // @[RegisterRouter.scala:87:24] wire out_rimask_297 = \|_out_rimask_T_297; // @[RegisterRouter.scala:87:24] wire out_wimask_297 = &_out_wimask_T_297; // @[RegisterRouter.scala:87:24] wire out_romask_297 = \|_out_romask_T_297; // @[RegisterRouter.scala:87:24] wire out_womask_297 = &_out_womask_T_297; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_297 = out_rivalid_1_151 & out_rimask_297; // @[RegisterRouter.scala:87:24] wire _out_T_3302 = out_f_rivalid_297; // @[RegisterRouter.scala:87:24] wire out_f_roready_297 = out_roready_1_151 & out_romask_297; // @[RegisterRouter.scala:87:24] wire _out_T_3303 = out_f_roready_297; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_297 = out_wivalid_1_151 & out_wimask_297; // @[RegisterRouter.scala:87:24] wire out_f_woready_297 = out_woready_1_151 & out_womask_297; // @[RegisterRouter.scala:87:24] wire _out_T_3304 = ~out_rimask_297; // @[RegisterRouter.scala:87:24] wire _out_T_3305 = ~out_wimask_297; // @[RegisterRouter.scala:87:24] wire _out_T_3306 = ~out_romask_297; // @[RegisterRouter.scala:87:24] wire _out_T_3307 = ~out_womask_297; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_244 = {hi_200, flags_0_go, _out_prepend_T_244}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3308 = out_prepend_244; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3309 = _out_T_3308; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_152 = _out_T_3309; // @[MuxLiteral.scala:49:48] wire out_rimask_298 = \|_out_rimask_T_298; // @[RegisterRouter.scala:87:24] wire out_wimask_298 = &_out_wimask_T_298; // @[RegisterRouter.scala:87:24] wire out_romask_298 = \|_out_romask_T_298; // @[RegisterRouter.scala:87:24] wire out_womask_298 = &_out_womask_T_298; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_298 = out_rivalid_1_152 & out_rimask_298; // @[RegisterRouter.scala:87:24] wire _out_T_3311 = out_f_rivalid_298; // @[RegisterRouter.scala:87:24] wire out_f_roready_298 = out_roready_1_152 & out_romask_298; // @[RegisterRouter.scala:87:24] wire _out_T_3312 = out_f_roready_298; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_298 = out_wivalid_1_152 & out_wimask_298; // @[RegisterRouter.scala:87:24] wire out_f_woready_298 = out_woready_1_152 & out_womask_298; // @[RegisterRouter.scala:87:24] wire _out_T_3313 = ~out_rimask_298; // @[RegisterRouter.scala:87:24] wire _out_T_3314 = ~out_wimask_298; // @[RegisterRouter.scala:87:24] wire _out_T_3315 = ~out_romask_298; // @[RegisterRouter.scala:87:24] wire _out_T_3316 = ~out_womask_298; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3318 = _out_T_3317; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_245 = _out_T_3318; // @[RegisterRouter.scala:87:24] wire out_rimask_299 = \|_out_rimask_T_299; // @[RegisterRouter.scala:87:24] wire out_wimask_299 = &_out_wimask_T_299; // @[RegisterRouter.scala:87:24] wire out_romask_299 = \|_out_romask_T_299; // @[RegisterRouter.scala:87:24] wire out_womask_299 = &_out_womask_T_299; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_299 = out_rivalid_1_153 & out_rimask_299; // @[RegisterRouter.scala:87:24] wire _out_T_3320 = out_f_rivalid_299; // @[RegisterRouter.scala:87:24] wire out_f_roready_299 = out_roready_1_153 & out_romask_299; // @[RegisterRouter.scala:87:24] wire _out_T_3321 = out_f_roready_299; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_299 = out_wivalid_1_153 & out_wimask_299; // @[RegisterRouter.scala:87:24] wire out_f_woready_299 = out_woready_1_153 & out_womask_299; // @[RegisterRouter.scala:87:24] wire _out_T_3322 = ~out_rimask_299; // @[RegisterRouter.scala:87:24] wire _out_T_3323 = ~out_wimask_299; // @[RegisterRouter.scala:87:24] wire _out_T_3324 = ~out_romask_299; // @[RegisterRouter.scala:87:24] wire _out_T_3325 = ~out_womask_299; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_245 = {hi_802, flags_0_go, _out_prepend_T_245}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3326 = out_prepend_245; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3327 = _out_T_3326; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_246 = _out_T_3327; // @[RegisterRouter.scala:87:24] wire out_rimask_300 = \|_out_rimask_T_300; // @[RegisterRouter.scala:87:24] wire out_wimask_300 = &_out_wimask_T_300; // @[RegisterRouter.scala:87:24] wire out_romask_300 = \|_out_romask_T_300; // @[RegisterRouter.scala:87:24] wire out_womask_300 = &_out_womask_T_300; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_300 = out_rivalid_1_154 & out_rimask_300; // @[RegisterRouter.scala:87:24] wire _out_T_3329 = out_f_rivalid_300; // @[RegisterRouter.scala:87:24] wire out_f_roready_300 = out_roready_1_154 & out_romask_300; // @[RegisterRouter.scala:87:24] wire _out_T_3330 = out_f_roready_300; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_300 = out_wivalid_1_154 & out_wimask_300; // @[RegisterRouter.scala:87:24] wire out_f_woready_300 = out_woready_1_154 & out_womask_300; // @[RegisterRouter.scala:87:24] wire _out_T_3331 = ~out_rimask_300; // @[RegisterRouter.scala:87:24] wire _out_T_3332 = ~out_wimask_300; // @[RegisterRouter.scala:87:24] wire _out_T_3333 = ~out_romask_300; // @[RegisterRouter.scala:87:24] wire _out_T_3334 = ~out_womask_300; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_246 = {hi_803, flags_0_go, _out_prepend_T_246}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3335 = out_prepend_246; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3336 = _out_T_3335; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_247 = _out_T_3336; // @[RegisterRouter.scala:87:24] wire out_rimask_301 = \|_out_rimask_T_301; // @[RegisterRouter.scala:87:24] wire out_wimask_301 = &_out_wimask_T_301; // @[RegisterRouter.scala:87:24] wire out_romask_301 = \|_out_romask_T_301; // @[RegisterRouter.scala:87:24] wire out_womask_301 = &_out_womask_T_301; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_301 = out_rivalid_1_155 & out_rimask_301; // @[RegisterRouter.scala:87:24] wire _out_T_3338 = out_f_rivalid_301; // @[RegisterRouter.scala:87:24] wire out_f_roready_301 = out_roready_1_155 & out_romask_301; // @[RegisterRouter.scala:87:24] wire _out_T_3339 = out_f_roready_301; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_301 = out_wivalid_1_155 & out_wimask_301; // @[RegisterRouter.scala:87:24] wire out_f_woready_301 = out_woready_1_155 & out_womask_301; // @[RegisterRouter.scala:87:24] wire _out_T_3340 = ~out_rimask_301; // @[RegisterRouter.scala:87:24] wire _out_T_3341 = ~out_wimask_301; // @[RegisterRouter.scala:87:24] wire _out_T_3342 = ~out_romask_301; // @[RegisterRouter.scala:87:24] wire _out_T_3343 = ~out_womask_301; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_247 = {hi_804, flags_0_go, _out_prepend_T_247}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3344 = out_prepend_247; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3345 = _out_T_3344; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_248 = _out_T_3345; // @[RegisterRouter.scala:87:24] wire out_rimask_302 = \|_out_rimask_T_302; // @[RegisterRouter.scala:87:24] wire out_wimask_302 = &_out_wimask_T_302; // @[RegisterRouter.scala:87:24] wire out_romask_302 = \|_out_romask_T_302; // @[RegisterRouter.scala:87:24] wire out_womask_302 = &_out_womask_T_302; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_302 = out_rivalid_1_156 & out_rimask_302; // @[RegisterRouter.scala:87:24] wire _out_T_3347 = out_f_rivalid_302; // @[RegisterRouter.scala:87:24] wire out_f_roready_302 = out_roready_1_156 & out_romask_302; // @[RegisterRouter.scala:87:24] wire _out_T_3348 = out_f_roready_302; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_302 = out_wivalid_1_156 & out_wimask_302; // @[RegisterRouter.scala:87:24] wire out_f_woready_302 = out_woready_1_156 & out_womask_302; // @[RegisterRouter.scala:87:24] wire _out_T_3349 = ~out_rimask_302; // @[RegisterRouter.scala:87:24] wire _out_T_3350 = ~out_wimask_302; // @[RegisterRouter.scala:87:24] wire _out_T_3351 = ~out_romask_302; // @[RegisterRouter.scala:87:24] wire _out_T_3352 = ~out_womask_302; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_248 = {hi_805, flags_0_go, _out_prepend_T_248}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3353 = out_prepend_248; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3354 = _out_T_3353; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_249 = _out_T_3354; // @[RegisterRouter.scala:87:24] wire out_rimask_303 = \|_out_rimask_T_303; // @[RegisterRouter.scala:87:24] wire out_wimask_303 = &_out_wimask_T_303; // @[RegisterRouter.scala:87:24] wire out_romask_303 = \|_out_romask_T_303; // @[RegisterRouter.scala:87:24] wire out_womask_303 = &_out_womask_T_303; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_303 = out_rivalid_1_157 & out_rimask_303; // @[RegisterRouter.scala:87:24] wire _out_T_3356 = out_f_rivalid_303; // @[RegisterRouter.scala:87:24] wire out_f_roready_303 = out_roready_1_157 & out_romask_303; // @[RegisterRouter.scala:87:24] wire _out_T_3357 = out_f_roready_303; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_303 = out_wivalid_1_157 & out_wimask_303; // @[RegisterRouter.scala:87:24] wire out_f_woready_303 = out_woready_1_157 & out_womask_303; // @[RegisterRouter.scala:87:24] wire _out_T_3358 = ~out_rimask_303; // @[RegisterRouter.scala:87:24] wire _out_T_3359 = ~out_wimask_303; // @[RegisterRouter.scala:87:24] wire _out_T_3360 = ~out_romask_303; // @[RegisterRouter.scala:87:24] wire _out_T_3361 = ~out_womask_303; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_249 = {hi_806, flags_0_go, _out_prepend_T_249}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3362 = out_prepend_249; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3363 = _out_T_3362; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_250 = _out_T_3363; // @[RegisterRouter.scala:87:24] wire out_rimask_304 = \|_out_rimask_T_304; // @[RegisterRouter.scala:87:24] wire out_wimask_304 = &_out_wimask_T_304; // @[RegisterRouter.scala:87:24] wire out_romask_304 = \|_out_romask_T_304; // @[RegisterRouter.scala:87:24] wire out_womask_304 = &_out_womask_T_304; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_304 = out_rivalid_1_158 & out_rimask_304; // @[RegisterRouter.scala:87:24] wire _out_T_3365 = out_f_rivalid_304; // @[RegisterRouter.scala:87:24] wire out_f_roready_304 = out_roready_1_158 & out_romask_304; // @[RegisterRouter.scala:87:24] wire _out_T_3366 = out_f_roready_304; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_304 = out_wivalid_1_158 & out_wimask_304; // @[RegisterRouter.scala:87:24] wire out_f_woready_304 = out_woready_1_158 & out_womask_304; // @[RegisterRouter.scala:87:24] wire _out_T_3367 = ~out_rimask_304; // @[RegisterRouter.scala:87:24] wire _out_T_3368 = ~out_wimask_304; // @[RegisterRouter.scala:87:24] wire _out_T_3369 = ~out_romask_304; // @[RegisterRouter.scala:87:24] wire _out_T_3370 = ~out_womask_304; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_250 = {hi_807, flags_0_go, _out_prepend_T_250}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3371 = out_prepend_250; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3372 = _out_T_3371; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_251 = _out_T_3372; // @[RegisterRouter.scala:87:24] wire out_rimask_305 = \|_out_rimask_T_305; // @[RegisterRouter.scala:87:24] wire out_wimask_305 = &_out_wimask_T_305; // @[RegisterRouter.scala:87:24] wire out_romask_305 = \|_out_romask_T_305; // @[RegisterRouter.scala:87:24] wire out_womask_305 = &_out_womask_T_305; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_305 = out_rivalid_1_159 & out_rimask_305; // @[RegisterRouter.scala:87:24] wire _out_T_3374 = out_f_rivalid_305; // @[RegisterRouter.scala:87:24] wire out_f_roready_305 = out_roready_1_159 & out_romask_305; // @[RegisterRouter.scala:87:24] wire _out_T_3375 = out_f_roready_305; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_305 = out_wivalid_1_159 & out_wimask_305; // @[RegisterRouter.scala:87:24] wire out_f_woready_305 = out_woready_1_159 & out_womask_305; // @[RegisterRouter.scala:87:24] wire _out_T_3376 = ~out_rimask_305; // @[RegisterRouter.scala:87:24] wire _out_T_3377 = ~out_wimask_305; // @[RegisterRouter.scala:87:24] wire _out_T_3378 = ~out_romask_305; // @[RegisterRouter.scala:87:24] wire _out_T_3379 = ~out_womask_305; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_251 = {hi_808, flags_0_go, _out_prepend_T_251}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3380 = out_prepend_251; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3381 = _out_T_3380; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_228 = _out_T_3381; // @[MuxLiteral.scala:49:48] wire out_rimask_306 = \|_out_rimask_T_306; // @[RegisterRouter.scala:87:24] wire out_wimask_306 = &_out_wimask_T_306; // @[RegisterRouter.scala:87:24] wire out_romask_306 = \|_out_romask_T_306; // @[RegisterRouter.scala:87:24] wire out_womask_306 = &_out_womask_T_306; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_306 = out_rivalid_1_160 & out_rimask_306; // @[RegisterRouter.scala:87:24] wire _out_T_3383 = out_f_rivalid_306; // @[RegisterRouter.scala:87:24] wire out_f_roready_306 = out_roready_1_160 & out_romask_306; // @[RegisterRouter.scala:87:24] wire _out_T_3384 = out_f_roready_306; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_306 = out_wivalid_1_160 & out_wimask_306; // @[RegisterRouter.scala:87:24] wire out_f_woready_306 = out_woready_1_160 & out_womask_306; // @[RegisterRouter.scala:87:24] wire _out_T_3385 = ~out_rimask_306; // @[RegisterRouter.scala:87:24] wire _out_T_3386 = ~out_wimask_306; // @[RegisterRouter.scala:87:24] wire _out_T_3387 = ~out_romask_306; // @[RegisterRouter.scala:87:24] wire _out_T_3388 = ~out_womask_306; // @[RegisterRouter.scala:87:24] wire out_rimask_307 = \|_out_rimask_T_307; // @[RegisterRouter.scala:87:24] wire out_wimask_307 = &_out_wimask_T_307; // @[RegisterRouter.scala:87:24] wire out_romask_307 = \|_out_romask_T_307; // @[RegisterRouter.scala:87:24] wire out_womask_307 = &_out_womask_T_307; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_307 = out_rivalid_1_161 & out_rimask_307; // @[RegisterRouter.scala:87:24] wire _out_T_3392 = out_f_rivalid_307; // @[RegisterRouter.scala:87:24] wire out_f_roready_307 = out_roready_1_161 & out_romask_307; // @[RegisterRouter.scala:87:24] wire _out_T_3393 = out_f_roready_307; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_307 = out_wivalid_1_161 & out_wimask_307; // @[RegisterRouter.scala:87:24] wire out_f_woready_307 = out_woready_1_161 & out_womask_307; // @[RegisterRouter.scala:87:24] wire _out_T_3394 = ~out_rimask_307; // @[RegisterRouter.scala:87:24] wire _out_T_3395 = ~out_wimask_307; // @[RegisterRouter.scala:87:24] wire _out_T_3396 = ~out_romask_307; // @[RegisterRouter.scala:87:24] wire _out_T_3397 = ~out_womask_307; // @[RegisterRouter.scala:87:24] wire out_rimask_308 = \|_out_rimask_T_308; // @[RegisterRouter.scala:87:24] wire out_wimask_308 = &_out_wimask_T_308; // @[RegisterRouter.scala:87:24] wire out_romask_308 = \|_out_romask_T_308; // @[RegisterRouter.scala:87:24] wire out_womask_308 = &_out_womask_T_308; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_308 = out_rivalid_1_162 & out_rimask_308; // @[RegisterRouter.scala:87:24] wire _out_T_3401 = out_f_rivalid_308; // @[RegisterRouter.scala:87:24] wire out_f_roready_308 = out_roready_1_162 & out_romask_308; // @[RegisterRouter.scala:87:24] wire _out_T_3402 = out_f_roready_308; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_308 = out_wivalid_1_162 & out_wimask_308; // @[RegisterRouter.scala:87:24] wire out_f_woready_308 = out_woready_1_162 & out_womask_308; // @[RegisterRouter.scala:87:24] wire _out_T_3403 = ~out_rimask_308; // @[RegisterRouter.scala:87:24] wire _out_T_3404 = ~out_wimask_308; // @[RegisterRouter.scala:87:24] wire _out_T_3405 = ~out_romask_308; // @[RegisterRouter.scala:87:24] wire _out_T_3406 = ~out_womask_308; // @[RegisterRouter.scala:87:24] wire out_rimask_309 = \|_out_rimask_T_309; // @[RegisterRouter.scala:87:24] wire out_wimask_309 = &_out_wimask_T_309; // @[RegisterRouter.scala:87:24] wire out_romask_309 = \|_out_romask_T_309; // @[RegisterRouter.scala:87:24] wire out_womask_309 = &_out_womask_T_309; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_309 = out_rivalid_1_163 & out_rimask_309; // @[RegisterRouter.scala:87:24] wire _out_T_3410 = out_f_rivalid_309; // @[RegisterRouter.scala:87:24] wire out_f_roready_309 = out_roready_1_163 & out_romask_309; // @[RegisterRouter.scala:87:24] wire _out_T_3411 = out_f_roready_309; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_309 = out_wivalid_1_163 & out_wimask_309; // @[RegisterRouter.scala:87:24] wire out_f_woready_309 = out_woready_1_163 & out_womask_309; // @[RegisterRouter.scala:87:24] wire _out_T_3412 = ~out_rimask_309; // @[RegisterRouter.scala:87:24] wire _out_T_3413 = ~out_wimask_309; // @[RegisterRouter.scala:87:24] wire _out_T_3414 = ~out_romask_309; // @[RegisterRouter.scala:87:24] wire _out_T_3415 = ~out_womask_309; // @[RegisterRouter.scala:87:24] wire out_rimask_310 = \|_out_rimask_T_310; // @[RegisterRouter.scala:87:24] wire out_wimask_310 = &_out_wimask_T_310; // @[RegisterRouter.scala:87:24] wire out_romask_310 = \|_out_romask_T_310; // @[RegisterRouter.scala:87:24] wire out_womask_310 = &_out_womask_T_310; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_310 = out_rivalid_1_164 & out_rimask_310; // @[RegisterRouter.scala:87:24] wire _out_T_3419 = out_f_rivalid_310; // @[RegisterRouter.scala:87:24] wire out_f_roready_310 = out_roready_1_164 & out_romask_310; // @[RegisterRouter.scala:87:24] wire _out_T_3420 = out_f_roready_310; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_310 = out_wivalid_1_164 & out_wimask_310; // @[RegisterRouter.scala:87:24] wire out_f_woready_310 = out_woready_1_164 & out_womask_310; // @[RegisterRouter.scala:87:24] wire _out_T_3421 = ~out_rimask_310; // @[RegisterRouter.scala:87:24] wire _out_T_3422 = ~out_wimask_310; // @[RegisterRouter.scala:87:24] wire _out_T_3423 = ~out_romask_310; // @[RegisterRouter.scala:87:24] wire _out_T_3424 = ~out_womask_310; // @[RegisterRouter.scala:87:24] wire out_rimask_311 = \|_out_rimask_T_311; // @[RegisterRouter.scala:87:24] wire out_wimask_311 = &_out_wimask_T_311; // @[RegisterRouter.scala:87:24] wire out_romask_311 = \|_out_romask_T_311; // @[RegisterRouter.scala:87:24] wire out_womask_311 = &_out_womask_T_311; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_311 = out_rivalid_1_165 & out_rimask_311; // @[RegisterRouter.scala:87:24] wire _out_T_3428 = out_f_rivalid_311; // @[RegisterRouter.scala:87:24] wire out_f_roready_311 = out_roready_1_165 & out_romask_311; // @[RegisterRouter.scala:87:24] wire _out_T_3429 = out_f_roready_311; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_311 = out_wivalid_1_165 & out_wimask_311; // @[RegisterRouter.scala:87:24] wire out_f_woready_311 = out_woready_1_165 & out_womask_311; // @[RegisterRouter.scala:87:24] wire _out_T_3430 = ~out_rimask_311; // @[RegisterRouter.scala:87:24] wire _out_T_3431 = ~out_wimask_311; // @[RegisterRouter.scala:87:24] wire _out_T_3432 = ~out_romask_311; // @[RegisterRouter.scala:87:24] wire _out_T_3433 = ~out_womask_311; // @[RegisterRouter.scala:87:24] wire out_rimask_312 = \|_out_rimask_T_312; // @[RegisterRouter.scala:87:24] wire out_wimask_312 = &_out_wimask_T_312; // @[RegisterRouter.scala:87:24] wire out_romask_312 = \|_out_romask_T_312; // @[RegisterRouter.scala:87:24] wire out_womask_312 = &_out_womask_T_312; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_312 = out_rivalid_1_166 & out_rimask_312; // @[RegisterRouter.scala:87:24] wire _out_T_3437 = out_f_rivalid_312; // @[RegisterRouter.scala:87:24] wire out_f_roready_312 = out_roready_1_166 & out_romask_312; // @[RegisterRouter.scala:87:24] wire _out_T_3438 = out_f_roready_312; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_312 = out_wivalid_1_166 & out_wimask_312; // @[RegisterRouter.scala:87:24] wire out_f_woready_312 = out_woready_1_166 & out_womask_312; // @[RegisterRouter.scala:87:24] wire _out_T_3439 = ~out_rimask_312; // @[RegisterRouter.scala:87:24] wire _out_T_3440 = ~out_wimask_312; // @[RegisterRouter.scala:87:24] wire _out_T_3441 = ~out_romask_312; // @[RegisterRouter.scala:87:24] wire _out_T_3442 = ~out_womask_312; // @[RegisterRouter.scala:87:24] wire out_rimask_313 = \|_out_rimask_T_313; // @[RegisterRouter.scala:87:24] wire out_wimask_313 = &_out_wimask_T_313; // @[RegisterRouter.scala:87:24] wire out_romask_313 = \|_out_romask_T_313; // @[RegisterRouter.scala:87:24] wire out_womask_313 = &_out_womask_T_313; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_313 = out_rivalid_1_167 & out_rimask_313; // @[RegisterRouter.scala:87:24] wire _out_T_3446 = out_f_rivalid_313; // @[RegisterRouter.scala:87:24] wire out_f_roready_313 = out_roready_1_167 & out_romask_313; // @[RegisterRouter.scala:87:24] wire _out_T_3447 = out_f_roready_313; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_313 = out_wivalid_1_167 & out_wimask_313; // @[RegisterRouter.scala:87:24] wire out_f_woready_313 = out_woready_1_167 & out_womask_313; // @[RegisterRouter.scala:87:24] wire _out_T_3448 = ~out_rimask_313; // @[RegisterRouter.scala:87:24] wire _out_T_3449 = ~out_wimask_313; // @[RegisterRouter.scala:87:24] wire _out_T_3450 = ~out_romask_313; // @[RegisterRouter.scala:87:24] wire _out_T_3451 = ~out_womask_313; // @[RegisterRouter.scala:87:24] wire out_rimask_314 = \|_out_rimask_T_314; // @[RegisterRouter.scala:87:24] wire out_wimask_314 = &_out_wimask_T_314; // @[RegisterRouter.scala:87:24] wire out_romask_314 = \|_out_romask_T_314; // @[RegisterRouter.scala:87:24] wire out_womask_314 = &_out_womask_T_314; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_314 = out_rivalid_1_168 & out_rimask_314; // @[RegisterRouter.scala:87:24] wire _out_T_3455 = out_f_rivalid_314; // @[RegisterRouter.scala:87:24] wire out_f_roready_314 = out_roready_1_168 & out_romask_314; // @[RegisterRouter.scala:87:24] wire _out_T_3456 = out_f_roready_314; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_314 = out_wivalid_1_168 & out_wimask_314; // @[RegisterRouter.scala:87:24] wire out_f_woready_314 = out_woready_1_168 & out_womask_314; // @[RegisterRouter.scala:87:24] wire _out_T_3457 = ~out_rimask_314; // @[RegisterRouter.scala:87:24] wire _out_T_3458 = ~out_wimask_314; // @[RegisterRouter.scala:87:24] wire _out_T_3459 = ~out_romask_314; // @[RegisterRouter.scala:87:24] wire _out_T_3460 = ~out_womask_314; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3462 = _out_T_3461; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_259 = _out_T_3462; // @[RegisterRouter.scala:87:24] wire out_rimask_315 = \|_out_rimask_T_315; // @[RegisterRouter.scala:87:24] wire out_wimask_315 = &_out_wimask_T_315; // @[RegisterRouter.scala:87:24] wire out_romask_315 = \|_out_romask_T_315; // @[RegisterRouter.scala:87:24] wire out_womask_315 = &_out_womask_T_315; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_315 = out_rivalid_1_169 & out_rimask_315; // @[RegisterRouter.scala:87:24] wire _out_T_3464 = out_f_rivalid_315; // @[RegisterRouter.scala:87:24] wire out_f_roready_315 = out_roready_1_169 & out_romask_315; // @[RegisterRouter.scala:87:24] wire _out_T_3465 = out_f_roready_315; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_315 = out_wivalid_1_169 & out_wimask_315; // @[RegisterRouter.scala:87:24] wire out_f_woready_315 = out_woready_1_169 & out_womask_315; // @[RegisterRouter.scala:87:24] wire _out_T_3466 = ~out_rimask_315; // @[RegisterRouter.scala:87:24] wire _out_T_3467 = ~out_wimask_315; // @[RegisterRouter.scala:87:24] wire _out_T_3468 = ~out_romask_315; // @[RegisterRouter.scala:87:24] wire _out_T_3469 = ~out_womask_315; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_259 = {hi_706, flags_0_go, _out_prepend_T_259}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3470 = out_prepend_259; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3471 = _out_T_3470; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_260 = _out_T_3471; // @[RegisterRouter.scala:87:24] wire out_rimask_316 = \|_out_rimask_T_316; // @[RegisterRouter.scala:87:24] wire out_wimask_316 = &_out_wimask_T_316; // @[RegisterRouter.scala:87:24] wire out_romask_316 = \|_out_romask_T_316; // @[RegisterRouter.scala:87:24] wire out_womask_316 = &_out_womask_T_316; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_316 = out_rivalid_1_170 & out_rimask_316; // @[RegisterRouter.scala:87:24] wire _out_T_3473 = out_f_rivalid_316; // @[RegisterRouter.scala:87:24] wire out_f_roready_316 = out_roready_1_170 & out_romask_316; // @[RegisterRouter.scala:87:24] wire _out_T_3474 = out_f_roready_316; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_316 = out_wivalid_1_170 & out_wimask_316; // @[RegisterRouter.scala:87:24] wire out_f_woready_316 = out_woready_1_170 & out_womask_316; // @[RegisterRouter.scala:87:24] wire _out_T_3475 = ~out_rimask_316; // @[RegisterRouter.scala:87:24] wire _out_T_3476 = ~out_wimask_316; // @[RegisterRouter.scala:87:24] wire _out_T_3477 = ~out_romask_316; // @[RegisterRouter.scala:87:24] wire _out_T_3478 = ~out_womask_316; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_260 = {hi_707, flags_0_go, _out_prepend_T_260}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3479 = out_prepend_260; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3480 = _out_T_3479; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_261 = _out_T_3480; // @[RegisterRouter.scala:87:24] wire out_rimask_317 = \|_out_rimask_T_317; // @[RegisterRouter.scala:87:24] wire out_wimask_317 = &_out_wimask_T_317; // @[RegisterRouter.scala:87:24] wire out_romask_317 = \|_out_romask_T_317; // @[RegisterRouter.scala:87:24] wire out_womask_317 = &_out_womask_T_317; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_317 = out_rivalid_1_171 & out_rimask_317; // @[RegisterRouter.scala:87:24] wire _out_T_3482 = out_f_rivalid_317; // @[RegisterRouter.scala:87:24] wire out_f_roready_317 = out_roready_1_171 & out_romask_317; // @[RegisterRouter.scala:87:24] wire _out_T_3483 = out_f_roready_317; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_317 = out_wivalid_1_171 & out_wimask_317; // @[RegisterRouter.scala:87:24] wire out_f_woready_317 = out_woready_1_171 & out_womask_317; // @[RegisterRouter.scala:87:24] wire _out_T_3484 = ~out_rimask_317; // @[RegisterRouter.scala:87:24] wire _out_T_3485 = ~out_wimask_317; // @[RegisterRouter.scala:87:24] wire _out_T_3486 = ~out_romask_317; // @[RegisterRouter.scala:87:24] wire _out_T_3487 = ~out_womask_317; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_261 = {hi_708, flags_0_go, _out_prepend_T_261}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3488 = out_prepend_261; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3489 = _out_T_3488; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_262 = _out_T_3489; // @[RegisterRouter.scala:87:24] wire out_rimask_318 = \|_out_rimask_T_318; // @[RegisterRouter.scala:87:24] wire out_wimask_318 = &_out_wimask_T_318; // @[RegisterRouter.scala:87:24] wire out_romask_318 = \|_out_romask_T_318; // @[RegisterRouter.scala:87:24] wire out_womask_318 = &_out_womask_T_318; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_318 = out_rivalid_1_172 & out_rimask_318; // @[RegisterRouter.scala:87:24] wire _out_T_3491 = out_f_rivalid_318; // @[RegisterRouter.scala:87:24] wire out_f_roready_318 = out_roready_1_172 & out_romask_318; // @[RegisterRouter.scala:87:24] wire _out_T_3492 = out_f_roready_318; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_318 = out_wivalid_1_172 & out_wimask_318; // @[RegisterRouter.scala:87:24] wire out_f_woready_318 = out_woready_1_172 & out_womask_318; // @[RegisterRouter.scala:87:24] wire _out_T_3493 = ~out_rimask_318; // @[RegisterRouter.scala:87:24] wire _out_T_3494 = ~out_wimask_318; // @[RegisterRouter.scala:87:24] wire _out_T_3495 = ~out_romask_318; // @[RegisterRouter.scala:87:24] wire _out_T_3496 = ~out_womask_318; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_262 = {hi_709, flags_0_go, _out_prepend_T_262}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3497 = out_prepend_262; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3498 = _out_T_3497; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_263 = _out_T_3498; // @[RegisterRouter.scala:87:24] wire out_rimask_319 = \|_out_rimask_T_319; // @[RegisterRouter.scala:87:24] wire out_wimask_319 = &_out_wimask_T_319; // @[RegisterRouter.scala:87:24] wire out_romask_319 = \|_out_romask_T_319; // @[RegisterRouter.scala:87:24] wire out_womask_319 = &_out_womask_T_319; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_319 = out_rivalid_1_173 & out_rimask_319; // @[RegisterRouter.scala:87:24] wire _out_T_3500 = out_f_rivalid_319; // @[RegisterRouter.scala:87:24] wire out_f_roready_319 = out_roready_1_173 & out_romask_319; // @[RegisterRouter.scala:87:24] wire _out_T_3501 = out_f_roready_319; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_319 = out_wivalid_1_173 & out_wimask_319; // @[RegisterRouter.scala:87:24] wire out_f_woready_319 = out_woready_1_173 & out_womask_319; // @[RegisterRouter.scala:87:24] wire _out_T_3502 = ~out_rimask_319; // @[RegisterRouter.scala:87:24] wire _out_T_3503 = ~out_wimask_319; // @[RegisterRouter.scala:87:24] wire _out_T_3504 = ~out_romask_319; // @[RegisterRouter.scala:87:24] wire _out_T_3505 = ~out_womask_319; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_263 = {hi_710, flags_0_go, _out_prepend_T_263}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3506 = out_prepend_263; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3507 = _out_T_3506; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_264 = _out_T_3507; // @[RegisterRouter.scala:87:24] wire out_rimask_320 = \|_out_rimask_T_320; // @[RegisterRouter.scala:87:24] wire out_wimask_320 = &_out_wimask_T_320; // @[RegisterRouter.scala:87:24] wire out_romask_320 = \|_out_romask_T_320; // @[RegisterRouter.scala:87:24] wire out_womask_320 = &_out_womask_T_320; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_320 = out_rivalid_1_174 & out_rimask_320; // @[RegisterRouter.scala:87:24] wire _out_T_3509 = out_f_rivalid_320; // @[RegisterRouter.scala:87:24] wire out_f_roready_320 = out_roready_1_174 & out_romask_320; // @[RegisterRouter.scala:87:24] wire _out_T_3510 = out_f_roready_320; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_320 = out_wivalid_1_174 & out_wimask_320; // @[RegisterRouter.scala:87:24] wire out_f_woready_320 = out_woready_1_174 & out_womask_320; // @[RegisterRouter.scala:87:24] wire _out_T_3511 = ~out_rimask_320; // @[RegisterRouter.scala:87:24] wire _out_T_3512 = ~out_wimask_320; // @[RegisterRouter.scala:87:24] wire _out_T_3513 = ~out_romask_320; // @[RegisterRouter.scala:87:24] wire _out_T_3514 = ~out_womask_320; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_264 = {hi_711, flags_0_go, _out_prepend_T_264}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3515 = out_prepend_264; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3516 = _out_T_3515; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_265 = _out_T_3516; // @[RegisterRouter.scala:87:24] wire out_rimask_321 = \|_out_rimask_T_321; // @[RegisterRouter.scala:87:24] wire out_wimask_321 = &_out_wimask_T_321; // @[RegisterRouter.scala:87:24] wire out_romask_321 = \|_out_romask_T_321; // @[RegisterRouter.scala:87:24] wire out_womask_321 = &_out_womask_T_321; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_321 = out_rivalid_1_175 & out_rimask_321; // @[RegisterRouter.scala:87:24] wire _out_T_3518 = out_f_rivalid_321; // @[RegisterRouter.scala:87:24] wire out_f_roready_321 = out_roready_1_175 & out_romask_321; // @[RegisterRouter.scala:87:24] wire _out_T_3519 = out_f_roready_321; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_321 = out_wivalid_1_175 & out_wimask_321; // @[RegisterRouter.scala:87:24] wire out_f_woready_321 = out_woready_1_175 & out_womask_321; // @[RegisterRouter.scala:87:24] wire _out_T_3520 = ~out_rimask_321; // @[RegisterRouter.scala:87:24] wire _out_T_3521 = ~out_wimask_321; // @[RegisterRouter.scala:87:24] wire _out_T_3522 = ~out_romask_321; // @[RegisterRouter.scala:87:24] wire _out_T_3523 = ~out_womask_321; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_265 = {hi_712, flags_0_go, _out_prepend_T_265}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3524 = out_prepend_265; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3525 = _out_T_3524; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_216 = _out_T_3525; // @[MuxLiteral.scala:49:48] wire out_rimask_322 = \|_out_rimask_T_322; // @[RegisterRouter.scala:87:24] wire out_wimask_322 = &_out_wimask_T_322; // @[RegisterRouter.scala:87:24] wire out_romask_322 = \|_out_romask_T_322; // @[RegisterRouter.scala:87:24] wire out_womask_322 = &_out_womask_T_322; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_322 = out_rivalid_1_176 & out_rimask_322; // @[RegisterRouter.scala:87:24] wire _out_T_3527 = out_f_rivalid_322; // @[RegisterRouter.scala:87:24] wire out_f_roready_322 = out_roready_1_176 & out_romask_322; // @[RegisterRouter.scala:87:24] wire _out_T_3528 = out_f_roready_322; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_322 = out_wivalid_1_176 & out_wimask_322; // @[RegisterRouter.scala:87:24] wire out_f_woready_322 = out_woready_1_176 & out_womask_322; // @[RegisterRouter.scala:87:24] wire _out_T_3529 = ~out_rimask_322; // @[RegisterRouter.scala:87:24] wire _out_T_3530 = ~out_wimask_322; // @[RegisterRouter.scala:87:24] wire _out_T_3531 = ~out_romask_322; // @[RegisterRouter.scala:87:24] wire _out_T_3532 = ~out_womask_322; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3534 = _out_T_3533; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_266 = _out_T_3534; // @[RegisterRouter.scala:87:24] wire out_rimask_323 = \|_out_rimask_T_323; // @[RegisterRouter.scala:87:24] wire out_wimask_323 = &_out_wimask_T_323; // @[RegisterRouter.scala:87:24] wire out_romask_323 = \|_out_romask_T_323; // @[RegisterRouter.scala:87:24] wire out_womask_323 = &_out_womask_T_323; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_323 = out_rivalid_1_177 & out_rimask_323; // @[RegisterRouter.scala:87:24] wire _out_T_3536 = out_f_rivalid_323; // @[RegisterRouter.scala:87:24] wire out_f_roready_323 = out_roready_1_177 & out_romask_323; // @[RegisterRouter.scala:87:24] wire _out_T_3537 = out_f_roready_323; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_323 = out_wivalid_1_177 & out_wimask_323; // @[RegisterRouter.scala:87:24] wire out_f_woready_323 = out_woready_1_177 & out_womask_323; // @[RegisterRouter.scala:87:24] wire _out_T_3538 = ~out_rimask_323; // @[RegisterRouter.scala:87:24] wire _out_T_3539 = ~out_wimask_323; // @[RegisterRouter.scala:87:24] wire _out_T_3540 = ~out_romask_323; // @[RegisterRouter.scala:87:24] wire _out_T_3541 = ~out_womask_323; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_266 = {hi_290, flags_0_go, _out_prepend_T_266}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3542 = out_prepend_266; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3543 = _out_T_3542; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_267 = _out_T_3543; // @[RegisterRouter.scala:87:24] wire out_rimask_324 = \|_out_rimask_T_324; // @[RegisterRouter.scala:87:24] wire out_wimask_324 = &_out_wimask_T_324; // @[RegisterRouter.scala:87:24] wire out_romask_324 = \|_out_romask_T_324; // @[RegisterRouter.scala:87:24] wire out_womask_324 = &_out_womask_T_324; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_324 = out_rivalid_1_178 & out_rimask_324; // @[RegisterRouter.scala:87:24] wire _out_T_3545 = out_f_rivalid_324; // @[RegisterRouter.scala:87:24] wire out_f_roready_324 = out_roready_1_178 & out_romask_324; // @[RegisterRouter.scala:87:24] wire _out_T_3546 = out_f_roready_324; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_324 = out_wivalid_1_178 & out_wimask_324; // @[RegisterRouter.scala:87:24] wire out_f_woready_324 = out_woready_1_178 & out_womask_324; // @[RegisterRouter.scala:87:24] wire _out_T_3547 = ~out_rimask_324; // @[RegisterRouter.scala:87:24] wire _out_T_3548 = ~out_wimask_324; // @[RegisterRouter.scala:87:24] wire _out_T_3549 = ~out_romask_324; // @[RegisterRouter.scala:87:24] wire _out_T_3550 = ~out_womask_324; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_267 = {hi_291, flags_0_go, _out_prepend_T_267}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3551 = out_prepend_267; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3552 = _out_T_3551; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_268 = _out_T_3552; // @[RegisterRouter.scala:87:24] wire out_rimask_325 = \|_out_rimask_T_325; // @[RegisterRouter.scala:87:24] wire out_wimask_325 = &_out_wimask_T_325; // @[RegisterRouter.scala:87:24] wire out_romask_325 = \|_out_romask_T_325; // @[RegisterRouter.scala:87:24] wire out_womask_325 = &_out_womask_T_325; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_325 = out_rivalid_1_179 & out_rimask_325; // @[RegisterRouter.scala:87:24] wire _out_T_3554 = out_f_rivalid_325; // @[RegisterRouter.scala:87:24] wire out_f_roready_325 = out_roready_1_179 & out_romask_325; // @[RegisterRouter.scala:87:24] wire _out_T_3555 = out_f_roready_325; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_325 = out_wivalid_1_179 & out_wimask_325; // @[RegisterRouter.scala:87:24] wire out_f_woready_325 = out_woready_1_179 & out_womask_325; // @[RegisterRouter.scala:87:24] wire _out_T_3556 = ~out_rimask_325; // @[RegisterRouter.scala:87:24] wire _out_T_3557 = ~out_wimask_325; // @[RegisterRouter.scala:87:24] wire _out_T_3558 = ~out_romask_325; // @[RegisterRouter.scala:87:24] wire _out_T_3559 = ~out_womask_325; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_268 = {hi_292, flags_0_go, _out_prepend_T_268}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3560 = out_prepend_268; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3561 = _out_T_3560; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_269 = _out_T_3561; // @[RegisterRouter.scala:87:24] wire out_rimask_326 = \|_out_rimask_T_326; // @[RegisterRouter.scala:87:24] wire out_wimask_326 = &_out_wimask_T_326; // @[RegisterRouter.scala:87:24] wire out_romask_326 = \|_out_romask_T_326; // @[RegisterRouter.scala:87:24] wire out_womask_326 = &_out_womask_T_326; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_326 = out_rivalid_1_180 & out_rimask_326; // @[RegisterRouter.scala:87:24] wire _out_T_3563 = out_f_rivalid_326; // @[RegisterRouter.scala:87:24] wire out_f_roready_326 = out_roready_1_180 & out_romask_326; // @[RegisterRouter.scala:87:24] wire _out_T_3564 = out_f_roready_326; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_326 = out_wivalid_1_180 & out_wimask_326; // @[RegisterRouter.scala:87:24] wire out_f_woready_326 = out_woready_1_180 & out_womask_326; // @[RegisterRouter.scala:87:24] wire _out_T_3565 = ~out_rimask_326; // @[RegisterRouter.scala:87:24] wire _out_T_3566 = ~out_wimask_326; // @[RegisterRouter.scala:87:24] wire _out_T_3567 = ~out_romask_326; // @[RegisterRouter.scala:87:24] wire _out_T_3568 = ~out_womask_326; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_269 = {hi_293, flags_0_go, _out_prepend_T_269}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3569 = out_prepend_269; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3570 = _out_T_3569; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_270 = _out_T_3570; // @[RegisterRouter.scala:87:24] wire out_rimask_327 = \|_out_rimask_T_327; // @[RegisterRouter.scala:87:24] wire out_wimask_327 = &_out_wimask_T_327; // @[RegisterRouter.scala:87:24] wire out_romask_327 = \|_out_romask_T_327; // @[RegisterRouter.scala:87:24] wire out_womask_327 = &_out_womask_T_327; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_327 = out_rivalid_1_181 & out_rimask_327; // @[RegisterRouter.scala:87:24] wire _out_T_3572 = out_f_rivalid_327; // @[RegisterRouter.scala:87:24] wire out_f_roready_327 = out_roready_1_181 & out_romask_327; // @[RegisterRouter.scala:87:24] wire _out_T_3573 = out_f_roready_327; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_327 = out_wivalid_1_181 & out_wimask_327; // @[RegisterRouter.scala:87:24] wire out_f_woready_327 = out_woready_1_181 & out_womask_327; // @[RegisterRouter.scala:87:24] wire _out_T_3574 = ~out_rimask_327; // @[RegisterRouter.scala:87:24] wire _out_T_3575 = ~out_wimask_327; // @[RegisterRouter.scala:87:24] wire _out_T_3576 = ~out_romask_327; // @[RegisterRouter.scala:87:24] wire _out_T_3577 = ~out_womask_327; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_270 = {hi_294, flags_0_go, _out_prepend_T_270}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3578 = out_prepend_270; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3579 = _out_T_3578; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_271 = _out_T_3579; // @[RegisterRouter.scala:87:24] wire out_rimask_328 = \|_out_rimask_T_328; // @[RegisterRouter.scala:87:24] wire out_wimask_328 = &_out_wimask_T_328; // @[RegisterRouter.scala:87:24] wire out_romask_328 = \|_out_romask_T_328; // @[RegisterRouter.scala:87:24] wire out_womask_328 = &_out_womask_T_328; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_328 = out_rivalid_1_182 & out_rimask_328; // @[RegisterRouter.scala:87:24] wire _out_T_3581 = out_f_rivalid_328; // @[RegisterRouter.scala:87:24] wire out_f_roready_328 = out_roready_1_182 & out_romask_328; // @[RegisterRouter.scala:87:24] wire _out_T_3582 = out_f_roready_328; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_328 = out_wivalid_1_182 & out_wimask_328; // @[RegisterRouter.scala:87:24] wire out_f_woready_328 = out_woready_1_182 & out_womask_328; // @[RegisterRouter.scala:87:24] wire _out_T_3583 = ~out_rimask_328; // @[RegisterRouter.scala:87:24] wire _out_T_3584 = ~out_wimask_328; // @[RegisterRouter.scala:87:24] wire _out_T_3585 = ~out_romask_328; // @[RegisterRouter.scala:87:24] wire _out_T_3586 = ~out_womask_328; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_271 = {hi_295, flags_0_go, _out_prepend_T_271}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3587 = out_prepend_271; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3588 = _out_T_3587; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_272 = _out_T_3588; // @[RegisterRouter.scala:87:24] wire out_rimask_329 = \|_out_rimask_T_329; // @[RegisterRouter.scala:87:24] wire out_wimask_329 = &_out_wimask_T_329; // @[RegisterRouter.scala:87:24] wire out_romask_329 = \|_out_romask_T_329; // @[RegisterRouter.scala:87:24] wire out_womask_329 = &_out_womask_T_329; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_329 = out_rivalid_1_183 & out_rimask_329; // @[RegisterRouter.scala:87:24] wire _out_T_3590 = out_f_rivalid_329; // @[RegisterRouter.scala:87:24] wire out_f_roready_329 = out_roready_1_183 & out_romask_329; // @[RegisterRouter.scala:87:24] wire _out_T_3591 = out_f_roready_329; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_329 = out_wivalid_1_183 & out_wimask_329; // @[RegisterRouter.scala:87:24] wire out_f_woready_329 = out_woready_1_183 & out_womask_329; // @[RegisterRouter.scala:87:24] wire _out_T_3592 = ~out_rimask_329; // @[RegisterRouter.scala:87:24] wire _out_T_3593 = ~out_wimask_329; // @[RegisterRouter.scala:87:24] wire _out_T_3594 = ~out_romask_329; // @[RegisterRouter.scala:87:24] wire _out_T_3595 = ~out_womask_329; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_272 = {hi_296, flags_0_go, _out_prepend_T_272}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3596 = out_prepend_272; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3597 = _out_T_3596; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_164 = _out_T_3597; // @[MuxLiteral.scala:49:48] wire out_rimask_330 = \|_out_rimask_T_330; // @[RegisterRouter.scala:87:24] wire out_wimask_330 = &_out_wimask_T_330; // @[RegisterRouter.scala:87:24] wire out_romask_330 = \|_out_romask_T_330; // @[RegisterRouter.scala:87:24] wire out_womask_330 = &_out_womask_T_330; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_330 = out_rivalid_1_184 & out_rimask_330; // @[RegisterRouter.scala:87:24] wire _out_T_3599 = out_f_rivalid_330; // @[RegisterRouter.scala:87:24] wire out_f_roready_330 = out_roready_1_184 & out_romask_330; // @[RegisterRouter.scala:87:24] wire _out_T_3600 = out_f_roready_330; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_330 = out_wivalid_1_184 & out_wimask_330; // @[RegisterRouter.scala:87:24] wire out_f_woready_330 = out_woready_1_184 & out_womask_330; // @[RegisterRouter.scala:87:24] wire _out_T_3601 = ~out_rimask_330; // @[RegisterRouter.scala:87:24] wire _out_T_3602 = ~out_wimask_330; // @[RegisterRouter.scala:87:24] wire _out_T_3603 = ~out_romask_330; // @[RegisterRouter.scala:87:24] wire _out_T_3604 = ~out_womask_330; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3606 = _out_T_3605; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_273 = _out_T_3606; // @[RegisterRouter.scala:87:24] wire out_rimask_331 = \|_out_rimask_T_331; // @[RegisterRouter.scala:87:24] wire out_wimask_331 = &_out_wimask_T_331; // @[RegisterRouter.scala:87:24] wire out_romask_331 = \|_out_romask_T_331; // @[RegisterRouter.scala:87:24] wire out_womask_331 = &_out_womask_T_331; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_331 = out_rivalid_1_185 & out_rimask_331; // @[RegisterRouter.scala:87:24] wire _out_T_3608 = out_f_rivalid_331; // @[RegisterRouter.scala:87:24] wire out_f_roready_331 = out_roready_1_185 & out_romask_331; // @[RegisterRouter.scala:87:24] wire _out_T_3609 = out_f_roready_331; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_331 = out_wivalid_1_185 & out_wimask_331; // @[RegisterRouter.scala:87:24] wire out_f_woready_331 = out_woready_1_185 & out_womask_331; // @[RegisterRouter.scala:87:24] wire _out_T_3610 = ~out_rimask_331; // @[RegisterRouter.scala:87:24] wire _out_T_3611 = ~out_wimask_331; // @[RegisterRouter.scala:87:24] wire _out_T_3612 = ~out_romask_331; // @[RegisterRouter.scala:87:24] wire _out_T_3613 = ~out_womask_331; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_273 = {hi_410, flags_0_go, _out_prepend_T_273}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3614 = out_prepend_273; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3615 = _out_T_3614; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_274 = _out_T_3615; // @[RegisterRouter.scala:87:24] wire out_rimask_332 = \|_out_rimask_T_332; // @[RegisterRouter.scala:87:24] wire out_wimask_332 = &_out_wimask_T_332; // @[RegisterRouter.scala:87:24] wire out_romask_332 = \|_out_romask_T_332; // @[RegisterRouter.scala:87:24] wire out_womask_332 = &_out_womask_T_332; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_332 = out_rivalid_1_186 & out_rimask_332; // @[RegisterRouter.scala:87:24] wire _out_T_3617 = out_f_rivalid_332; // @[RegisterRouter.scala:87:24] wire out_f_roready_332 = out_roready_1_186 & out_romask_332; // @[RegisterRouter.scala:87:24] wire _out_T_3618 = out_f_roready_332; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_332 = out_wivalid_1_186 & out_wimask_332; // @[RegisterRouter.scala:87:24] wire out_f_woready_332 = out_woready_1_186 & out_womask_332; // @[RegisterRouter.scala:87:24] wire _out_T_3619 = ~out_rimask_332; // @[RegisterRouter.scala:87:24] wire _out_T_3620 = ~out_wimask_332; // @[RegisterRouter.scala:87:24] wire _out_T_3621 = ~out_romask_332; // @[RegisterRouter.scala:87:24] wire _out_T_3622 = ~out_womask_332; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_274 = {hi_411, flags_0_go, _out_prepend_T_274}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3623 = out_prepend_274; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3624 = _out_T_3623; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_275 = _out_T_3624; // @[RegisterRouter.scala:87:24] wire out_rimask_333 = \|_out_rimask_T_333; // @[RegisterRouter.scala:87:24] wire out_wimask_333 = &_out_wimask_T_333; // @[RegisterRouter.scala:87:24] wire out_romask_333 = \|_out_romask_T_333; // @[RegisterRouter.scala:87:24] wire out_womask_333 = &_out_womask_T_333; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_333 = out_rivalid_1_187 & out_rimask_333; // @[RegisterRouter.scala:87:24] wire _out_T_3626 = out_f_rivalid_333; // @[RegisterRouter.scala:87:24] wire out_f_roready_333 = out_roready_1_187 & out_romask_333; // @[RegisterRouter.scala:87:24] wire _out_T_3627 = out_f_roready_333; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_333 = out_wivalid_1_187 & out_wimask_333; // @[RegisterRouter.scala:87:24] wire out_f_woready_333 = out_woready_1_187 & out_womask_333; // @[RegisterRouter.scala:87:24] wire _out_T_3628 = ~out_rimask_333; // @[RegisterRouter.scala:87:24] wire _out_T_3629 = ~out_wimask_333; // @[RegisterRouter.scala:87:24] wire _out_T_3630 = ~out_romask_333; // @[RegisterRouter.scala:87:24] wire _out_T_3631 = ~out_womask_333; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_275 = {hi_412, flags_0_go, _out_prepend_T_275}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3632 = out_prepend_275; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3633 = _out_T_3632; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_276 = _out_T_3633; // @[RegisterRouter.scala:87:24] wire out_rimask_334 = \|_out_rimask_T_334; // @[RegisterRouter.scala:87:24] wire out_wimask_334 = &_out_wimask_T_334; // @[RegisterRouter.scala:87:24] wire out_romask_334 = \|_out_romask_T_334; // @[RegisterRouter.scala:87:24] wire out_womask_334 = &_out_womask_T_334; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_334 = out_rivalid_1_188 & out_rimask_334; // @[RegisterRouter.scala:87:24] wire _out_T_3635 = out_f_rivalid_334; // @[RegisterRouter.scala:87:24] wire out_f_roready_334 = out_roready_1_188 & out_romask_334; // @[RegisterRouter.scala:87:24] wire _out_T_3636 = out_f_roready_334; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_334 = out_wivalid_1_188 & out_wimask_334; // @[RegisterRouter.scala:87:24] wire out_f_woready_334 = out_woready_1_188 & out_womask_334; // @[RegisterRouter.scala:87:24] wire _out_T_3637 = ~out_rimask_334; // @[RegisterRouter.scala:87:24] wire _out_T_3638 = ~out_wimask_334; // @[RegisterRouter.scala:87:24] wire _out_T_3639 = ~out_romask_334; // @[RegisterRouter.scala:87:24] wire _out_T_3640 = ~out_womask_334; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_276 = {hi_413, flags_0_go, _out_prepend_T_276}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3641 = out_prepend_276; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3642 = _out_T_3641; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_277 = _out_T_3642; // @[RegisterRouter.scala:87:24] wire out_rimask_335 = \|_out_rimask_T_335; // @[RegisterRouter.scala:87:24] wire out_wimask_335 = &_out_wimask_T_335; // @[RegisterRouter.scala:87:24] wire out_romask_335 = \|_out_romask_T_335; // @[RegisterRouter.scala:87:24] wire out_womask_335 = &_out_womask_T_335; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_335 = out_rivalid_1_189 & out_rimask_335; // @[RegisterRouter.scala:87:24] wire _out_T_3644 = out_f_rivalid_335; // @[RegisterRouter.scala:87:24] wire out_f_roready_335 = out_roready_1_189 & out_romask_335; // @[RegisterRouter.scala:87:24] wire _out_T_3645 = out_f_roready_335; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_335 = out_wivalid_1_189 & out_wimask_335; // @[RegisterRouter.scala:87:24] wire out_f_woready_335 = out_woready_1_189 & out_womask_335; // @[RegisterRouter.scala:87:24] wire _out_T_3646 = ~out_rimask_335; // @[RegisterRouter.scala:87:24] wire _out_T_3647 = ~out_wimask_335; // @[RegisterRouter.scala:87:24] wire _out_T_3648 = ~out_romask_335; // @[RegisterRouter.scala:87:24] wire _out_T_3649 = ~out_womask_335; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_277 = {hi_414, flags_0_go, _out_prepend_T_277}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3650 = out_prepend_277; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3651 = _out_T_3650; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_278 = _out_T_3651; // @[RegisterRouter.scala:87:24] wire out_rimask_336 = \|_out_rimask_T_336; // @[RegisterRouter.scala:87:24] wire out_wimask_336 = &_out_wimask_T_336; // @[RegisterRouter.scala:87:24] wire out_romask_336 = \|_out_romask_T_336; // @[RegisterRouter.scala:87:24] wire out_womask_336 = &_out_womask_T_336; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_336 = out_rivalid_1_190 & out_rimask_336; // @[RegisterRouter.scala:87:24] wire _out_T_3653 = out_f_rivalid_336; // @[RegisterRouter.scala:87:24] wire out_f_roready_336 = out_roready_1_190 & out_romask_336; // @[RegisterRouter.scala:87:24] wire _out_T_3654 = out_f_roready_336; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_336 = out_wivalid_1_190 & out_wimask_336; // @[RegisterRouter.scala:87:24] wire out_f_woready_336 = out_woready_1_190 & out_womask_336; // @[RegisterRouter.scala:87:24] wire _out_T_3655 = ~out_rimask_336; // @[RegisterRouter.scala:87:24] wire _out_T_3656 = ~out_wimask_336; // @[RegisterRouter.scala:87:24] wire _out_T_3657 = ~out_romask_336; // @[RegisterRouter.scala:87:24] wire _out_T_3658 = ~out_womask_336; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_278 = {hi_415, flags_0_go, _out_prepend_T_278}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3659 = out_prepend_278; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3660 = _out_T_3659; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_279 = _out_T_3660; // @[RegisterRouter.scala:87:24] wire out_rimask_337 = \|_out_rimask_T_337; // @[RegisterRouter.scala:87:24] wire out_wimask_337 = &_out_wimask_T_337; // @[RegisterRouter.scala:87:24] wire out_romask_337 = \|_out_romask_T_337; // @[RegisterRouter.scala:87:24] wire out_womask_337 = &_out_womask_T_337; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_337 = out_rivalid_1_191 & out_rimask_337; // @[RegisterRouter.scala:87:24] wire _out_T_3662 = out_f_rivalid_337; // @[RegisterRouter.scala:87:24] wire out_f_roready_337 = out_roready_1_191 & out_romask_337; // @[RegisterRouter.scala:87:24] wire _out_T_3663 = out_f_roready_337; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_337 = out_wivalid_1_191 & out_wimask_337; // @[RegisterRouter.scala:87:24] wire out_f_woready_337 = out_woready_1_191 & out_womask_337; // @[RegisterRouter.scala:87:24] wire _out_T_3664 = ~out_rimask_337; // @[RegisterRouter.scala:87:24] wire _out_T_3665 = ~out_wimask_337; // @[RegisterRouter.scala:87:24] wire _out_T_3666 = ~out_romask_337; // @[RegisterRouter.scala:87:24] wire _out_T_3667 = ~out_womask_337; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_279 = {hi_416, flags_0_go, _out_prepend_T_279}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3668 = out_prepend_279; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3669 = _out_T_3668; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_179 = _out_T_3669; // @[MuxLiteral.scala:49:48] wire out_rimask_338 = \|_out_rimask_T_338; // @[RegisterRouter.scala:87:24] wire out_wimask_338 = &_out_wimask_T_338; // @[RegisterRouter.scala:87:24] wire out_romask_338 = \|_out_romask_T_338; // @[RegisterRouter.scala:87:24] wire out_womask_338 = &_out_womask_T_338; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_338 = out_rivalid_1_192 & out_rimask_338; // @[RegisterRouter.scala:87:24] wire _out_T_3671 = out_f_rivalid_338; // @[RegisterRouter.scala:87:24] wire out_f_roready_338 = out_roready_1_192 & out_romask_338; // @[RegisterRouter.scala:87:24] wire _out_T_3672 = out_f_roready_338; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_338 = out_wivalid_1_192 & out_wimask_338; // @[RegisterRouter.scala:87:24] wire _out_T_3673 = out_f_wivalid_338; // @[RegisterRouter.scala:87:24] wire out_f_woready_338 = out_woready_1_192 & out_womask_338; // @[RegisterRouter.scala:87:24] wire _out_T_3674 = out_f_woready_338; // @[RegisterRouter.scala:87:24] wire _out_T_3675 = ~out_rimask_338; // @[RegisterRouter.scala:87:24] wire _out_T_3676 = ~out_wimask_338; // @[RegisterRouter.scala:87:24] wire _out_T_3677 = ~out_romask_338; // @[RegisterRouter.scala:87:24] wire _out_T_3678 = ~out_womask_338; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3680 = _out_T_3679; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_280 = _out_T_3680; // @[RegisterRouter.scala:87:24] wire out_rimask_339 = \|_out_rimask_T_339; // @[RegisterRouter.scala:87:24] wire out_wimask_339 = &_out_wimask_T_339; // @[RegisterRouter.scala:87:24] wire out_romask_339 = \|_out_romask_T_339; // @[RegisterRouter.scala:87:24] wire out_womask_339 = &_out_womask_T_339; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_339 = out_rivalid_1_193 & out_rimask_339; // @[RegisterRouter.scala:87:24] wire _out_T_3682 = out_f_rivalid_339; // @[RegisterRouter.scala:87:24] wire out_f_roready_339 = out_roready_1_193 & out_romask_339; // @[RegisterRouter.scala:87:24] wire _out_T_3683 = out_f_roready_339; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_339 = out_wivalid_1_193 & out_wimask_339; // @[RegisterRouter.scala:87:24] wire _out_T_3684 = out_f_wivalid_339; // @[RegisterRouter.scala:87:24] wire out_f_woready_339 = out_woready_1_193 & out_womask_339; // @[RegisterRouter.scala:87:24] wire _out_T_3685 = out_f_woready_339; // @[RegisterRouter.scala:87:24] wire _out_T_3686 = ~out_rimask_339; // @[RegisterRouter.scala:87:24] wire _out_T_3687 = ~out_wimask_339; // @[RegisterRouter.scala:87:24] wire _out_T_3688 = ~out_romask_339; // @[RegisterRouter.scala:87:24] wire _out_T_3689 = ~out_womask_339; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_280 = {programBufferMem_17, _out_prepend_T_280}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3690 = out_prepend_280; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3691 = _out_T_3690; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_281 = _out_T_3691; // @[RegisterRouter.scala:87:24] wire out_rimask_340 = \|_out_rimask_T_340; // @[RegisterRouter.scala:87:24] wire out_wimask_340 = &_out_wimask_T_340; // @[RegisterRouter.scala:87:24] wire out_romask_340 = \|_out_romask_T_340; // @[RegisterRouter.scala:87:24] wire out_womask_340 = &_out_womask_T_340; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_340 = out_rivalid_1_194 & out_rimask_340; // @[RegisterRouter.scala:87:24] wire _out_T_3693 = out_f_rivalid_340; // @[RegisterRouter.scala:87:24] wire out_f_roready_340 = out_roready_1_194 & out_romask_340; // @[RegisterRouter.scala:87:24] wire _out_T_3694 = out_f_roready_340; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_340 = out_wivalid_1_194 & out_wimask_340; // @[RegisterRouter.scala:87:24] wire _out_T_3695 = out_f_wivalid_340; // @[RegisterRouter.scala:87:24] wire out_f_woready_340 = out_woready_1_194 & out_womask_340; // @[RegisterRouter.scala:87:24] wire _out_T_3696 = out_f_woready_340; // @[RegisterRouter.scala:87:24] wire _out_T_3697 = ~out_rimask_340; // @[RegisterRouter.scala:87:24] wire _out_T_3698 = ~out_wimask_340; // @[RegisterRouter.scala:87:24] wire _out_T_3699 = ~out_romask_340; // @[RegisterRouter.scala:87:24] wire _out_T_3700 = ~out_womask_340; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_281 = {programBufferMem_18, _out_prepend_T_281}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3701 = out_prepend_281; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3702 = _out_T_3701; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_282 = _out_T_3702; // @[RegisterRouter.scala:87:24] wire out_rimask_341 = \|_out_rimask_T_341; // @[RegisterRouter.scala:87:24] wire out_wimask_341 = &_out_wimask_T_341; // @[RegisterRouter.scala:87:24] wire out_romask_341 = \|_out_romask_T_341; // @[RegisterRouter.scala:87:24] wire out_womask_341 = &_out_womask_T_341; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_341 = out_rivalid_1_195 & out_rimask_341; // @[RegisterRouter.scala:87:24] wire _out_T_3704 = out_f_rivalid_341; // @[RegisterRouter.scala:87:24] wire out_f_roready_341 = out_roready_1_195 & out_romask_341; // @[RegisterRouter.scala:87:24] wire _out_T_3705 = out_f_roready_341; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_341 = out_wivalid_1_195 & out_wimask_341; // @[RegisterRouter.scala:87:24] wire _out_T_3706 = out_f_wivalid_341; // @[RegisterRouter.scala:87:24] wire out_f_woready_341 = out_woready_1_195 & out_womask_341; // @[RegisterRouter.scala:87:24] wire _out_T_3707 = out_f_woready_341; // @[RegisterRouter.scala:87:24] wire _out_T_3708 = ~out_rimask_341; // @[RegisterRouter.scala:87:24] wire _out_T_3709 = ~out_wimask_341; // @[RegisterRouter.scala:87:24] wire _out_T_3710 = ~out_romask_341; // @[RegisterRouter.scala:87:24] wire _out_T_3711 = ~out_womask_341; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_282 = {programBufferMem_19, _out_prepend_T_282}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3712 = out_prepend_282; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3713 = _out_T_3712; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_283 = _out_T_3713; // @[RegisterRouter.scala:87:24] wire out_rimask_342 = \|_out_rimask_T_342; // @[RegisterRouter.scala:87:24] wire out_wimask_342 = &_out_wimask_T_342; // @[RegisterRouter.scala:87:24] wire out_romask_342 = \|_out_romask_T_342; // @[RegisterRouter.scala:87:24] wire out_womask_342 = &_out_womask_T_342; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_342 = out_rivalid_1_196 & out_rimask_342; // @[RegisterRouter.scala:87:24] wire _out_T_3715 = out_f_rivalid_342; // @[RegisterRouter.scala:87:24] wire out_f_roready_342 = out_roready_1_196 & out_romask_342; // @[RegisterRouter.scala:87:24] wire _out_T_3716 = out_f_roready_342; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_342 = out_wivalid_1_196 & out_wimask_342; // @[RegisterRouter.scala:87:24] wire _out_T_3717 = out_f_wivalid_342; // @[RegisterRouter.scala:87:24] wire out_f_woready_342 = out_woready_1_196 & out_womask_342; // @[RegisterRouter.scala:87:24] wire _out_T_3718 = out_f_woready_342; // @[RegisterRouter.scala:87:24] wire _out_T_3719 = ~out_rimask_342; // @[RegisterRouter.scala:87:24] wire _out_T_3720 = ~out_wimask_342; // @[RegisterRouter.scala:87:24] wire _out_T_3721 = ~out_romask_342; // @[RegisterRouter.scala:87:24] wire _out_T_3722 = ~out_womask_342; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_283 = {programBufferMem_20, _out_prepend_T_283}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3723 = out_prepend_283; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3724 = _out_T_3723; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_284 = _out_T_3724; // @[RegisterRouter.scala:87:24] wire out_rimask_343 = \|_out_rimask_T_343; // @[RegisterRouter.scala:87:24] wire out_wimask_343 = &_out_wimask_T_343; // @[RegisterRouter.scala:87:24] wire out_romask_343 = \|_out_romask_T_343; // @[RegisterRouter.scala:87:24] wire out_womask_343 = &_out_womask_T_343; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_343 = out_rivalid_1_197 & out_rimask_343; // @[RegisterRouter.scala:87:24] wire _out_T_3726 = out_f_rivalid_343; // @[RegisterRouter.scala:87:24] wire out_f_roready_343 = out_roready_1_197 & out_romask_343; // @[RegisterRouter.scala:87:24] wire _out_T_3727 = out_f_roready_343; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_343 = out_wivalid_1_197 & out_wimask_343; // @[RegisterRouter.scala:87:24] wire _out_T_3728 = out_f_wivalid_343; // @[RegisterRouter.scala:87:24] wire out_f_woready_343 = out_woready_1_197 & out_womask_343; // @[RegisterRouter.scala:87:24] wire _out_T_3729 = out_f_woready_343; // @[RegisterRouter.scala:87:24] wire _out_T_3730 = ~out_rimask_343; // @[RegisterRouter.scala:87:24] wire _out_T_3731 = ~out_wimask_343; // @[RegisterRouter.scala:87:24] wire _out_T_3732 = ~out_romask_343; // @[RegisterRouter.scala:87:24] wire _out_T_3733 = ~out_womask_343; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_284 = {programBufferMem_21, _out_prepend_T_284}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3734 = out_prepend_284; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3735 = _out_T_3734; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_285 = _out_T_3735; // @[RegisterRouter.scala:87:24] wire out_rimask_344 = \|_out_rimask_T_344; // @[RegisterRouter.scala:87:24] wire out_wimask_344 = &_out_wimask_T_344; // @[RegisterRouter.scala:87:24] wire out_romask_344 = \|_out_romask_T_344; // @[RegisterRouter.scala:87:24] wire out_womask_344 = &_out_womask_T_344; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_344 = out_rivalid_1_198 & out_rimask_344; // @[RegisterRouter.scala:87:24] wire _out_T_3737 = out_f_rivalid_344; // @[RegisterRouter.scala:87:24] wire out_f_roready_344 = out_roready_1_198 & out_romask_344; // @[RegisterRouter.scala:87:24] wire _out_T_3738 = out_f_roready_344; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_344 = out_wivalid_1_198 & out_wimask_344; // @[RegisterRouter.scala:87:24] wire _out_T_3739 = out_f_wivalid_344; // @[RegisterRouter.scala:87:24] wire out_f_woready_344 = out_woready_1_198 & out_womask_344; // @[RegisterRouter.scala:87:24] wire _out_T_3740 = out_f_woready_344; // @[RegisterRouter.scala:87:24] wire _out_T_3741 = ~out_rimask_344; // @[RegisterRouter.scala:87:24] wire _out_T_3742 = ~out_wimask_344; // @[RegisterRouter.scala:87:24] wire _out_T_3743 = ~out_romask_344; // @[RegisterRouter.scala:87:24] wire _out_T_3744 = ~out_womask_344; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_285 = {programBufferMem_22, _out_prepend_T_285}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3745 = out_prepend_285; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3746 = _out_T_3745; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_286 = _out_T_3746; // @[RegisterRouter.scala:87:24] wire out_rimask_345 = \|_out_rimask_T_345; // @[RegisterRouter.scala:87:24] wire out_wimask_345 = &_out_wimask_T_345; // @[RegisterRouter.scala:87:24] wire out_romask_345 = \|_out_romask_T_345; // @[RegisterRouter.scala:87:24] wire out_womask_345 = &_out_womask_T_345; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_345 = out_rivalid_1_199 & out_rimask_345; // @[RegisterRouter.scala:87:24] wire _out_T_3748 = out_f_rivalid_345; // @[RegisterRouter.scala:87:24] wire out_f_roready_345 = out_roready_1_199 & out_romask_345; // @[RegisterRouter.scala:87:24] wire _out_T_3749 = out_f_roready_345; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_345 = out_wivalid_1_199 & out_wimask_345; // @[RegisterRouter.scala:87:24] wire _out_T_3750 = out_f_wivalid_345; // @[RegisterRouter.scala:87:24] wire out_f_woready_345 = out_woready_1_199 & out_womask_345; // @[RegisterRouter.scala:87:24] wire _out_T_3751 = out_f_woready_345; // @[RegisterRouter.scala:87:24] wire _out_T_3752 = ~out_rimask_345; // @[RegisterRouter.scala:87:24] wire _out_T_3753 = ~out_wimask_345; // @[RegisterRouter.scala:87:24] wire _out_T_3754 = ~out_romask_345; // @[RegisterRouter.scala:87:24] wire _out_T_3755 = ~out_womask_345; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_286 = {programBufferMem_23, _out_prepend_T_286}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3756 = out_prepend_286; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3757 = _out_T_3756; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_106 = _out_T_3757; // @[MuxLiteral.scala:49:48] wire out_rimask_346 = \|_out_rimask_T_346; // @[RegisterRouter.scala:87:24] wire out_wimask_346 = &_out_wimask_T_346; // @[RegisterRouter.scala:87:24] wire out_romask_346 = \|_out_romask_T_346; // @[RegisterRouter.scala:87:24] wire out_womask_346 = &_out_womask_T_346; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_346 = out_rivalid_1_200 & out_rimask_346; // @[RegisterRouter.scala:87:24] wire _out_T_3759 = out_f_rivalid_346; // @[RegisterRouter.scala:87:24] wire out_f_roready_346 = out_roready_1_200 & out_romask_346; // @[RegisterRouter.scala:87:24] wire _out_T_3760 = out_f_roready_346; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_346 = out_wivalid_1_200 & out_wimask_346; // @[RegisterRouter.scala:87:24] wire out_f_woready_346 = out_woready_1_200 & out_womask_346; // @[RegisterRouter.scala:87:24] wire _out_T_3761 = ~out_rimask_346; // @[RegisterRouter.scala:87:24] wire _out_T_3762 = ~out_wimask_346; // @[RegisterRouter.scala:87:24] wire _out_T_3763 = ~out_romask_346; // @[RegisterRouter.scala:87:24] wire _out_T_3764 = ~out_womask_346; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3766 = _out_T_3765; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_287 = _out_T_3766; // @[RegisterRouter.scala:87:24] wire out_rimask_347 = \|_out_rimask_T_347; // @[RegisterRouter.scala:87:24] wire out_wimask_347 = &_out_wimask_T_347; // @[RegisterRouter.scala:87:24] wire out_romask_347 = \|_out_romask_T_347; // @[RegisterRouter.scala:87:24] wire out_womask_347 = &_out_womask_T_347; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_347 = out_rivalid_1_201 & out_rimask_347; // @[RegisterRouter.scala:87:24] wire _out_T_3768 = out_f_rivalid_347; // @[RegisterRouter.scala:87:24] wire out_f_roready_347 = out_roready_1_201 & out_romask_347; // @[RegisterRouter.scala:87:24] wire _out_T_3769 = out_f_roready_347; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_347 = out_wivalid_1_201 & out_wimask_347; // @[RegisterRouter.scala:87:24] wire out_f_woready_347 = out_woready_1_201 & out_womask_347; // @[RegisterRouter.scala:87:24] wire _out_T_3770 = ~out_rimask_347; // @[RegisterRouter.scala:87:24] wire _out_T_3771 = ~out_wimask_347; // @[RegisterRouter.scala:87:24] wire _out_T_3772 = ~out_romask_347; // @[RegisterRouter.scala:87:24] wire _out_T_3773 = ~out_womask_347; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_287 = {hi_882, flags_0_go, _out_prepend_T_287}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3774 = out_prepend_287; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3775 = _out_T_3774; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_288 = _out_T_3775; // @[RegisterRouter.scala:87:24] wire out_rimask_348 = \|_out_rimask_T_348; // @[RegisterRouter.scala:87:24] wire out_wimask_348 = &_out_wimask_T_348; // @[RegisterRouter.scala:87:24] wire out_romask_348 = \|_out_romask_T_348; // @[RegisterRouter.scala:87:24] wire out_womask_348 = &_out_womask_T_348; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_348 = out_rivalid_1_202 & out_rimask_348; // @[RegisterRouter.scala:87:24] wire _out_T_3777 = out_f_rivalid_348; // @[RegisterRouter.scala:87:24] wire out_f_roready_348 = out_roready_1_202 & out_romask_348; // @[RegisterRouter.scala:87:24] wire _out_T_3778 = out_f_roready_348; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_348 = out_wivalid_1_202 & out_wimask_348; // @[RegisterRouter.scala:87:24] wire out_f_woready_348 = out_woready_1_202 & out_womask_348; // @[RegisterRouter.scala:87:24] wire _out_T_3779 = ~out_rimask_348; // @[RegisterRouter.scala:87:24] wire _out_T_3780 = ~out_wimask_348; // @[RegisterRouter.scala:87:24] wire _out_T_3781 = ~out_romask_348; // @[RegisterRouter.scala:87:24] wire _out_T_3782 = ~out_womask_348; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_288 = {hi_883, flags_0_go, _out_prepend_T_288}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3783 = out_prepend_288; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3784 = _out_T_3783; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_289 = _out_T_3784; // @[RegisterRouter.scala:87:24] wire out_rimask_349 = \|_out_rimask_T_349; // @[RegisterRouter.scala:87:24] wire out_wimask_349 = &_out_wimask_T_349; // @[RegisterRouter.scala:87:24] wire out_romask_349 = \|_out_romask_T_349; // @[RegisterRouter.scala:87:24] wire out_womask_349 = &_out_womask_T_349; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_349 = out_rivalid_1_203 & out_rimask_349; // @[RegisterRouter.scala:87:24] wire _out_T_3786 = out_f_rivalid_349; // @[RegisterRouter.scala:87:24] wire out_f_roready_349 = out_roready_1_203 & out_romask_349; // @[RegisterRouter.scala:87:24] wire _out_T_3787 = out_f_roready_349; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_349 = out_wivalid_1_203 & out_wimask_349; // @[RegisterRouter.scala:87:24] wire out_f_woready_349 = out_woready_1_203 & out_womask_349; // @[RegisterRouter.scala:87:24] wire _out_T_3788 = ~out_rimask_349; // @[RegisterRouter.scala:87:24] wire _out_T_3789 = ~out_wimask_349; // @[RegisterRouter.scala:87:24] wire _out_T_3790 = ~out_romask_349; // @[RegisterRouter.scala:87:24] wire _out_T_3791 = ~out_womask_349; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_289 = {hi_884, flags_0_go, _out_prepend_T_289}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3792 = out_prepend_289; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3793 = _out_T_3792; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_290 = _out_T_3793; // @[RegisterRouter.scala:87:24] wire out_rimask_350 = \|_out_rimask_T_350; // @[RegisterRouter.scala:87:24] wire out_wimask_350 = &_out_wimask_T_350; // @[RegisterRouter.scala:87:24] wire out_romask_350 = \|_out_romask_T_350; // @[RegisterRouter.scala:87:24] wire out_womask_350 = &_out_womask_T_350; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_350 = out_rivalid_1_204 & out_rimask_350; // @[RegisterRouter.scala:87:24] wire _out_T_3795 = out_f_rivalid_350; // @[RegisterRouter.scala:87:24] wire out_f_roready_350 = out_roready_1_204 & out_romask_350; // @[RegisterRouter.scala:87:24] wire _out_T_3796 = out_f_roready_350; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_350 = out_wivalid_1_204 & out_wimask_350; // @[RegisterRouter.scala:87:24] wire out_f_woready_350 = out_woready_1_204 & out_womask_350; // @[RegisterRouter.scala:87:24] wire _out_T_3797 = ~out_rimask_350; // @[RegisterRouter.scala:87:24] wire _out_T_3798 = ~out_wimask_350; // @[RegisterRouter.scala:87:24] wire _out_T_3799 = ~out_romask_350; // @[RegisterRouter.scala:87:24] wire _out_T_3800 = ~out_womask_350; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_290 = {hi_885, flags_0_go, _out_prepend_T_290}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3801 = out_prepend_290; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3802 = _out_T_3801; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_291 = _out_T_3802; // @[RegisterRouter.scala:87:24] wire out_rimask_351 = \|_out_rimask_T_351; // @[RegisterRouter.scala:87:24] wire out_wimask_351 = &_out_wimask_T_351; // @[RegisterRouter.scala:87:24] wire out_romask_351 = \|_out_romask_T_351; // @[RegisterRouter.scala:87:24] wire out_womask_351 = &_out_womask_T_351; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_351 = out_rivalid_1_205 & out_rimask_351; // @[RegisterRouter.scala:87:24] wire _out_T_3804 = out_f_rivalid_351; // @[RegisterRouter.scala:87:24] wire out_f_roready_351 = out_roready_1_205 & out_romask_351; // @[RegisterRouter.scala:87:24] wire _out_T_3805 = out_f_roready_351; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_351 = out_wivalid_1_205 & out_wimask_351; // @[RegisterRouter.scala:87:24] wire out_f_woready_351 = out_woready_1_205 & out_womask_351; // @[RegisterRouter.scala:87:24] wire _out_T_3806 = ~out_rimask_351; // @[RegisterRouter.scala:87:24] wire _out_T_3807 = ~out_wimask_351; // @[RegisterRouter.scala:87:24] wire _out_T_3808 = ~out_romask_351; // @[RegisterRouter.scala:87:24] wire _out_T_3809 = ~out_womask_351; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_291 = {hi_886, flags_0_go, _out_prepend_T_291}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3810 = out_prepend_291; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3811 = _out_T_3810; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_292 = _out_T_3811; // @[RegisterRouter.scala:87:24] wire out_rimask_352 = \|_out_rimask_T_352; // @[RegisterRouter.scala:87:24] wire out_wimask_352 = &_out_wimask_T_352; // @[RegisterRouter.scala:87:24] wire out_romask_352 = \|_out_romask_T_352; // @[RegisterRouter.scala:87:24] wire out_womask_352 = &_out_womask_T_352; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_352 = out_rivalid_1_206 & out_rimask_352; // @[RegisterRouter.scala:87:24] wire _out_T_3813 = out_f_rivalid_352; // @[RegisterRouter.scala:87:24] wire out_f_roready_352 = out_roready_1_206 & out_romask_352; // @[RegisterRouter.scala:87:24] wire _out_T_3814 = out_f_roready_352; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_352 = out_wivalid_1_206 & out_wimask_352; // @[RegisterRouter.scala:87:24] wire out_f_woready_352 = out_woready_1_206 & out_womask_352; // @[RegisterRouter.scala:87:24] wire _out_T_3815 = ~out_rimask_352; // @[RegisterRouter.scala:87:24] wire _out_T_3816 = ~out_wimask_352; // @[RegisterRouter.scala:87:24] wire _out_T_3817 = ~out_romask_352; // @[RegisterRouter.scala:87:24] wire _out_T_3818 = ~out_womask_352; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_292 = {hi_887, flags_0_go, _out_prepend_T_292}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3819 = out_prepend_292; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3820 = _out_T_3819; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_293 = _out_T_3820; // @[RegisterRouter.scala:87:24] wire out_rimask_353 = \|_out_rimask_T_353; // @[RegisterRouter.scala:87:24] wire out_wimask_353 = &_out_wimask_T_353; // @[RegisterRouter.scala:87:24] wire out_romask_353 = \|_out_romask_T_353; // @[RegisterRouter.scala:87:24] wire out_womask_353 = &_out_womask_T_353; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_353 = out_rivalid_1_207 & out_rimask_353; // @[RegisterRouter.scala:87:24] wire _out_T_3822 = out_f_rivalid_353; // @[RegisterRouter.scala:87:24] wire out_f_roready_353 = out_roready_1_207 & out_romask_353; // @[RegisterRouter.scala:87:24] wire _out_T_3823 = out_f_roready_353; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_353 = out_wivalid_1_207 & out_wimask_353; // @[RegisterRouter.scala:87:24] wire out_f_woready_353 = out_woready_1_207 & out_womask_353; // @[RegisterRouter.scala:87:24] wire _out_T_3824 = ~out_rimask_353; // @[RegisterRouter.scala:87:24] wire _out_T_3825 = ~out_wimask_353; // @[RegisterRouter.scala:87:24] wire _out_T_3826 = ~out_romask_353; // @[RegisterRouter.scala:87:24] wire _out_T_3827 = ~out_womask_353; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_293 = {hi_888, flags_0_go, _out_prepend_T_293}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3828 = out_prepend_293; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3829 = _out_T_3828; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_238 = _out_T_3829; // @[MuxLiteral.scala:49:48] wire out_rimask_354 = \|_out_rimask_T_354; // @[RegisterRouter.scala:87:24] wire out_wimask_354 = &_out_wimask_T_354; // @[RegisterRouter.scala:87:24] wire out_romask_354 = \|_out_romask_T_354; // @[RegisterRouter.scala:87:24] wire out_womask_354 = &_out_womask_T_354; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_354 = out_rivalid_1_208 & out_rimask_354; // @[RegisterRouter.scala:87:24] wire _out_T_3831 = out_f_rivalid_354; // @[RegisterRouter.scala:87:24] wire out_f_roready_354 = out_roready_1_208 & out_romask_354; // @[RegisterRouter.scala:87:24] wire _out_T_3832 = out_f_roready_354; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_354 = out_wivalid_1_208 & out_wimask_354; // @[RegisterRouter.scala:87:24] wire out_f_woready_354 = out_woready_1_208 & out_womask_354; // @[RegisterRouter.scala:87:24] wire _out_T_3833 = ~out_rimask_354; // @[RegisterRouter.scala:87:24] wire _out_T_3834 = ~out_wimask_354; // @[RegisterRouter.scala:87:24] wire _out_T_3835 = ~out_romask_354; // @[RegisterRouter.scala:87:24] wire _out_T_3836 = ~out_womask_354; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3838 = _out_T_3837; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_294 = _out_T_3838; // @[RegisterRouter.scala:87:24] wire out_rimask_355 = \|_out_rimask_T_355; // @[RegisterRouter.scala:87:24] wire out_wimask_355 = &_out_wimask_T_355; // @[RegisterRouter.scala:87:24] wire out_romask_355 = \|_out_romask_T_355; // @[RegisterRouter.scala:87:24] wire out_womask_355 = &_out_womask_T_355; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_355 = out_rivalid_1_209 & out_rimask_355; // @[RegisterRouter.scala:87:24] wire _out_T_3840 = out_f_rivalid_355; // @[RegisterRouter.scala:87:24] wire out_f_roready_355 = out_roready_1_209 & out_romask_355; // @[RegisterRouter.scala:87:24] wire _out_T_3841 = out_f_roready_355; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_355 = out_wivalid_1_209 & out_wimask_355; // @[RegisterRouter.scala:87:24] wire out_f_woready_355 = out_woready_1_209 & out_womask_355; // @[RegisterRouter.scala:87:24] wire _out_T_3842 = ~out_rimask_355; // @[RegisterRouter.scala:87:24] wire _out_T_3843 = ~out_wimask_355; // @[RegisterRouter.scala:87:24] wire _out_T_3844 = ~out_romask_355; // @[RegisterRouter.scala:87:24] wire _out_T_3845 = ~out_womask_355; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_294 = {hi_666, flags_0_go, _out_prepend_T_294}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3846 = out_prepend_294; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3847 = _out_T_3846; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_295 = _out_T_3847; // @[RegisterRouter.scala:87:24] wire out_rimask_356 = \|_out_rimask_T_356; // @[RegisterRouter.scala:87:24] wire out_wimask_356 = &_out_wimask_T_356; // @[RegisterRouter.scala:87:24] wire out_romask_356 = \|_out_romask_T_356; // @[RegisterRouter.scala:87:24] wire out_womask_356 = &_out_womask_T_356; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_356 = out_rivalid_1_210 & out_rimask_356; // @[RegisterRouter.scala:87:24] wire _out_T_3849 = out_f_rivalid_356; // @[RegisterRouter.scala:87:24] wire out_f_roready_356 = out_roready_1_210 & out_romask_356; // @[RegisterRouter.scala:87:24] wire _out_T_3850 = out_f_roready_356; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_356 = out_wivalid_1_210 & out_wimask_356; // @[RegisterRouter.scala:87:24] wire out_f_woready_356 = out_woready_1_210 & out_womask_356; // @[RegisterRouter.scala:87:24] wire _out_T_3851 = ~out_rimask_356; // @[RegisterRouter.scala:87:24] wire _out_T_3852 = ~out_wimask_356; // @[RegisterRouter.scala:87:24] wire _out_T_3853 = ~out_romask_356; // @[RegisterRouter.scala:87:24] wire _out_T_3854 = ~out_womask_356; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_295 = {hi_667, flags_0_go, _out_prepend_T_295}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3855 = out_prepend_295; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3856 = _out_T_3855; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_296 = _out_T_3856; // @[RegisterRouter.scala:87:24] wire out_rimask_357 = \|_out_rimask_T_357; // @[RegisterRouter.scala:87:24] wire out_wimask_357 = &_out_wimask_T_357; // @[RegisterRouter.scala:87:24] wire out_romask_357 = \|_out_romask_T_357; // @[RegisterRouter.scala:87:24] wire out_womask_357 = &_out_womask_T_357; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_357 = out_rivalid_1_211 & out_rimask_357; // @[RegisterRouter.scala:87:24] wire _out_T_3858 = out_f_rivalid_357; // @[RegisterRouter.scala:87:24] wire out_f_roready_357 = out_roready_1_211 & out_romask_357; // @[RegisterRouter.scala:87:24] wire _out_T_3859 = out_f_roready_357; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_357 = out_wivalid_1_211 & out_wimask_357; // @[RegisterRouter.scala:87:24] wire out_f_woready_357 = out_woready_1_211 & out_womask_357; // @[RegisterRouter.scala:87:24] wire _out_T_3860 = ~out_rimask_357; // @[RegisterRouter.scala:87:24] wire _out_T_3861 = ~out_wimask_357; // @[RegisterRouter.scala:87:24] wire _out_T_3862 = ~out_romask_357; // @[RegisterRouter.scala:87:24] wire _out_T_3863 = ~out_womask_357; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_296 = {hi_668, flags_0_go, _out_prepend_T_296}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3864 = out_prepend_296; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3865 = _out_T_3864; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_297 = _out_T_3865; // @[RegisterRouter.scala:87:24] wire out_rimask_358 = \|_out_rimask_T_358; // @[RegisterRouter.scala:87:24] wire out_wimask_358 = &_out_wimask_T_358; // @[RegisterRouter.scala:87:24] wire out_romask_358 = \|_out_romask_T_358; // @[RegisterRouter.scala:87:24] wire out_womask_358 = &_out_womask_T_358; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_358 = out_rivalid_1_212 & out_rimask_358; // @[RegisterRouter.scala:87:24] wire _out_T_3867 = out_f_rivalid_358; // @[RegisterRouter.scala:87:24] wire out_f_roready_358 = out_roready_1_212 & out_romask_358; // @[RegisterRouter.scala:87:24] wire _out_T_3868 = out_f_roready_358; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_358 = out_wivalid_1_212 & out_wimask_358; // @[RegisterRouter.scala:87:24] wire out_f_woready_358 = out_woready_1_212 & out_womask_358; // @[RegisterRouter.scala:87:24] wire _out_T_3869 = ~out_rimask_358; // @[RegisterRouter.scala:87:24] wire _out_T_3870 = ~out_wimask_358; // @[RegisterRouter.scala:87:24] wire _out_T_3871 = ~out_romask_358; // @[RegisterRouter.scala:87:24] wire _out_T_3872 = ~out_womask_358; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_297 = {hi_669, flags_0_go, _out_prepend_T_297}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3873 = out_prepend_297; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3874 = _out_T_3873; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_298 = _out_T_3874; // @[RegisterRouter.scala:87:24] wire out_rimask_359 = \|_out_rimask_T_359; // @[RegisterRouter.scala:87:24] wire out_wimask_359 = &_out_wimask_T_359; // @[RegisterRouter.scala:87:24] wire out_romask_359 = \|_out_romask_T_359; // @[RegisterRouter.scala:87:24] wire out_womask_359 = &_out_womask_T_359; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_359 = out_rivalid_1_213 & out_rimask_359; // @[RegisterRouter.scala:87:24] wire _out_T_3876 = out_f_rivalid_359; // @[RegisterRouter.scala:87:24] wire out_f_roready_359 = out_roready_1_213 & out_romask_359; // @[RegisterRouter.scala:87:24] wire _out_T_3877 = out_f_roready_359; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_359 = out_wivalid_1_213 & out_wimask_359; // @[RegisterRouter.scala:87:24] wire out_f_woready_359 = out_woready_1_213 & out_womask_359; // @[RegisterRouter.scala:87:24] wire _out_T_3878 = ~out_rimask_359; // @[RegisterRouter.scala:87:24] wire _out_T_3879 = ~out_wimask_359; // @[RegisterRouter.scala:87:24] wire _out_T_3880 = ~out_romask_359; // @[RegisterRouter.scala:87:24] wire _out_T_3881 = ~out_womask_359; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_298 = {hi_670, flags_0_go, _out_prepend_T_298}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3882 = out_prepend_298; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3883 = _out_T_3882; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_299 = _out_T_3883; // @[RegisterRouter.scala:87:24] wire out_rimask_360 = \|_out_rimask_T_360; // @[RegisterRouter.scala:87:24] wire out_wimask_360 = &_out_wimask_T_360; // @[RegisterRouter.scala:87:24] wire out_romask_360 = \|_out_romask_T_360; // @[RegisterRouter.scala:87:24] wire out_womask_360 = &_out_womask_T_360; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_360 = out_rivalid_1_214 & out_rimask_360; // @[RegisterRouter.scala:87:24] wire _out_T_3885 = out_f_rivalid_360; // @[RegisterRouter.scala:87:24] wire out_f_roready_360 = out_roready_1_214 & out_romask_360; // @[RegisterRouter.scala:87:24] wire _out_T_3886 = out_f_roready_360; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_360 = out_wivalid_1_214 & out_wimask_360; // @[RegisterRouter.scala:87:24] wire out_f_woready_360 = out_woready_1_214 & out_womask_360; // @[RegisterRouter.scala:87:24] wire _out_T_3887 = ~out_rimask_360; // @[RegisterRouter.scala:87:24] wire _out_T_3888 = ~out_wimask_360; // @[RegisterRouter.scala:87:24] wire _out_T_3889 = ~out_romask_360; // @[RegisterRouter.scala:87:24] wire _out_T_3890 = ~out_womask_360; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_299 = {hi_671, flags_0_go, _out_prepend_T_299}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3891 = out_prepend_299; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3892 = _out_T_3891; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_300 = _out_T_3892; // @[RegisterRouter.scala:87:24] wire out_rimask_361 = \|_out_rimask_T_361; // @[RegisterRouter.scala:87:24] wire out_wimask_361 = &_out_wimask_T_361; // @[RegisterRouter.scala:87:24] wire out_romask_361 = \|_out_romask_T_361; // @[RegisterRouter.scala:87:24] wire out_womask_361 = &_out_womask_T_361; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_361 = out_rivalid_1_215 & out_rimask_361; // @[RegisterRouter.scala:87:24] wire _out_T_3894 = out_f_rivalid_361; // @[RegisterRouter.scala:87:24] wire out_f_roready_361 = out_roready_1_215 & out_romask_361; // @[RegisterRouter.scala:87:24] wire _out_T_3895 = out_f_roready_361; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_361 = out_wivalid_1_215 & out_wimask_361; // @[RegisterRouter.scala:87:24] wire out_f_woready_361 = out_woready_1_215 & out_womask_361; // @[RegisterRouter.scala:87:24] wire _out_T_3896 = ~out_rimask_361; // @[RegisterRouter.scala:87:24] wire _out_T_3897 = ~out_wimask_361; // @[RegisterRouter.scala:87:24] wire _out_T_3898 = ~out_romask_361; // @[RegisterRouter.scala:87:24] wire _out_T_3899 = ~out_womask_361; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_300 = {hi_672, flags_0_go, _out_prepend_T_300}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3900 = out_prepend_300; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3901 = _out_T_3900; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_211 = _out_T_3901; // @[MuxLiteral.scala:49:48] wire out_rimask_362 = \|_out_rimask_T_362; // @[RegisterRouter.scala:87:24] wire out_wimask_362 = &_out_wimask_T_362; // @[RegisterRouter.scala:87:24] wire out_romask_362 = \|_out_romask_T_362; // @[RegisterRouter.scala:87:24] wire out_womask_362 = &_out_womask_T_362; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_362 = out_rivalid_1_216 & out_rimask_362; // @[RegisterRouter.scala:87:24] wire _out_T_3903 = out_f_rivalid_362; // @[RegisterRouter.scala:87:24] wire out_f_roready_362 = out_roready_1_216 & out_romask_362; // @[RegisterRouter.scala:87:24] wire _out_T_3904 = out_f_roready_362; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_362 = out_wivalid_1_216 & out_wimask_362; // @[RegisterRouter.scala:87:24] wire out_f_woready_362 = out_woready_1_216 & out_womask_362; // @[RegisterRouter.scala:87:24] wire _out_T_3905 = ~out_rimask_362; // @[RegisterRouter.scala:87:24] wire _out_T_3906 = ~out_wimask_362; // @[RegisterRouter.scala:87:24] wire _out_T_3907 = ~out_romask_362; // @[RegisterRouter.scala:87:24] wire _out_T_3908 = ~out_womask_362; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3910 = _out_T_3909; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_301 = _out_T_3910; // @[RegisterRouter.scala:87:24] wire out_rimask_363 = \|_out_rimask_T_363; // @[RegisterRouter.scala:87:24] wire out_wimask_363 = &_out_wimask_T_363; // @[RegisterRouter.scala:87:24] wire out_romask_363 = \|_out_romask_T_363; // @[RegisterRouter.scala:87:24] wire out_womask_363 = &_out_womask_T_363; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_363 = out_rivalid_1_217 & out_rimask_363; // @[RegisterRouter.scala:87:24] wire _out_T_3912 = out_f_rivalid_363; // @[RegisterRouter.scala:87:24] wire out_f_roready_363 = out_roready_1_217 & out_romask_363; // @[RegisterRouter.scala:87:24] wire _out_T_3913 = out_f_roready_363; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_363 = out_wivalid_1_217 & out_wimask_363; // @[RegisterRouter.scala:87:24] wire out_f_woready_363 = out_woready_1_217 & out_womask_363; // @[RegisterRouter.scala:87:24] wire _out_T_3914 = ~out_rimask_363; // @[RegisterRouter.scala:87:24] wire _out_T_3915 = ~out_wimask_363; // @[RegisterRouter.scala:87:24] wire _out_T_3916 = ~out_romask_363; // @[RegisterRouter.scala:87:24] wire _out_T_3917 = ~out_womask_363; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_301 = {hi_1002, flags_0_go, _out_prepend_T_301}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3918 = out_prepend_301; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3919 = _out_T_3918; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_302 = _out_T_3919; // @[RegisterRouter.scala:87:24] wire out_rimask_364 = \|_out_rimask_T_364; // @[RegisterRouter.scala:87:24] wire out_wimask_364 = &_out_wimask_T_364; // @[RegisterRouter.scala:87:24] wire out_romask_364 = \|_out_romask_T_364; // @[RegisterRouter.scala:87:24] wire out_womask_364 = &_out_womask_T_364; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_364 = out_rivalid_1_218 & out_rimask_364; // @[RegisterRouter.scala:87:24] wire _out_T_3921 = out_f_rivalid_364; // @[RegisterRouter.scala:87:24] wire out_f_roready_364 = out_roready_1_218 & out_romask_364; // @[RegisterRouter.scala:87:24] wire _out_T_3922 = out_f_roready_364; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_364 = out_wivalid_1_218 & out_wimask_364; // @[RegisterRouter.scala:87:24] wire out_f_woready_364 = out_woready_1_218 & out_womask_364; // @[RegisterRouter.scala:87:24] wire _out_T_3923 = ~out_rimask_364; // @[RegisterRouter.scala:87:24] wire _out_T_3924 = ~out_wimask_364; // @[RegisterRouter.scala:87:24] wire _out_T_3925 = ~out_romask_364; // @[RegisterRouter.scala:87:24] wire _out_T_3926 = ~out_womask_364; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_302 = {hi_1003, flags_0_go, _out_prepend_T_302}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3927 = out_prepend_302; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3928 = _out_T_3927; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_303 = _out_T_3928; // @[RegisterRouter.scala:87:24] wire out_rimask_365 = \|_out_rimask_T_365; // @[RegisterRouter.scala:87:24] wire out_wimask_365 = &_out_wimask_T_365; // @[RegisterRouter.scala:87:24] wire out_romask_365 = \|_out_romask_T_365; // @[RegisterRouter.scala:87:24] wire out_womask_365 = &_out_womask_T_365; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_365 = out_rivalid_1_219 & out_rimask_365; // @[RegisterRouter.scala:87:24] wire _out_T_3930 = out_f_rivalid_365; // @[RegisterRouter.scala:87:24] wire out_f_roready_365 = out_roready_1_219 & out_romask_365; // @[RegisterRouter.scala:87:24] wire _out_T_3931 = out_f_roready_365; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_365 = out_wivalid_1_219 & out_wimask_365; // @[RegisterRouter.scala:87:24] wire out_f_woready_365 = out_woready_1_219 & out_womask_365; // @[RegisterRouter.scala:87:24] wire _out_T_3932 = ~out_rimask_365; // @[RegisterRouter.scala:87:24] wire _out_T_3933 = ~out_wimask_365; // @[RegisterRouter.scala:87:24] wire _out_T_3934 = ~out_romask_365; // @[RegisterRouter.scala:87:24] wire _out_T_3935 = ~out_womask_365; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_303 = {hi_1004, flags_0_go, _out_prepend_T_303}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3936 = out_prepend_303; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3937 = _out_T_3936; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_304 = _out_T_3937; // @[RegisterRouter.scala:87:24] wire out_rimask_366 = \|_out_rimask_T_366; // @[RegisterRouter.scala:87:24] wire out_wimask_366 = &_out_wimask_T_366; // @[RegisterRouter.scala:87:24] wire out_romask_366 = \|_out_romask_T_366; // @[RegisterRouter.scala:87:24] wire out_womask_366 = &_out_womask_T_366; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_366 = out_rivalid_1_220 & out_rimask_366; // @[RegisterRouter.scala:87:24] wire _out_T_3939 = out_f_rivalid_366; // @[RegisterRouter.scala:87:24] wire out_f_roready_366 = out_roready_1_220 & out_romask_366; // @[RegisterRouter.scala:87:24] wire _out_T_3940 = out_f_roready_366; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_366 = out_wivalid_1_220 & out_wimask_366; // @[RegisterRouter.scala:87:24] wire out_f_woready_366 = out_woready_1_220 & out_womask_366; // @[RegisterRouter.scala:87:24] wire _out_T_3941 = ~out_rimask_366; // @[RegisterRouter.scala:87:24] wire _out_T_3942 = ~out_wimask_366; // @[RegisterRouter.scala:87:24] wire _out_T_3943 = ~out_romask_366; // @[RegisterRouter.scala:87:24] wire _out_T_3944 = ~out_womask_366; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_304 = {hi_1005, flags_0_go, _out_prepend_T_304}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3945 = out_prepend_304; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3946 = _out_T_3945; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_305 = _out_T_3946; // @[RegisterRouter.scala:87:24] wire out_rimask_367 = \|_out_rimask_T_367; // @[RegisterRouter.scala:87:24] wire out_wimask_367 = &_out_wimask_T_367; // @[RegisterRouter.scala:87:24] wire out_romask_367 = \|_out_romask_T_367; // @[RegisterRouter.scala:87:24] wire out_womask_367 = &_out_womask_T_367; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_367 = out_rivalid_1_221 & out_rimask_367; // @[RegisterRouter.scala:87:24] wire _out_T_3948 = out_f_rivalid_367; // @[RegisterRouter.scala:87:24] wire out_f_roready_367 = out_roready_1_221 & out_romask_367; // @[RegisterRouter.scala:87:24] wire _out_T_3949 = out_f_roready_367; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_367 = out_wivalid_1_221 & out_wimask_367; // @[RegisterRouter.scala:87:24] wire out_f_woready_367 = out_woready_1_221 & out_womask_367; // @[RegisterRouter.scala:87:24] wire _out_T_3950 = ~out_rimask_367; // @[RegisterRouter.scala:87:24] wire _out_T_3951 = ~out_wimask_367; // @[RegisterRouter.scala:87:24] wire _out_T_3952 = ~out_romask_367; // @[RegisterRouter.scala:87:24] wire _out_T_3953 = ~out_womask_367; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_305 = {hi_1006, flags_0_go, _out_prepend_T_305}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3954 = out_prepend_305; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3955 = _out_T_3954; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_306 = _out_T_3955; // @[RegisterRouter.scala:87:24] wire out_rimask_368 = \|_out_rimask_T_368; // @[RegisterRouter.scala:87:24] wire out_wimask_368 = &_out_wimask_T_368; // @[RegisterRouter.scala:87:24] wire out_romask_368 = \|_out_romask_T_368; // @[RegisterRouter.scala:87:24] wire out_womask_368 = &_out_womask_T_368; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_368 = out_rivalid_1_222 & out_rimask_368; // @[RegisterRouter.scala:87:24] wire _out_T_3957 = out_f_rivalid_368; // @[RegisterRouter.scala:87:24] wire out_f_roready_368 = out_roready_1_222 & out_romask_368; // @[RegisterRouter.scala:87:24] wire _out_T_3958 = out_f_roready_368; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_368 = out_wivalid_1_222 & out_wimask_368; // @[RegisterRouter.scala:87:24] wire out_f_woready_368 = out_woready_1_222 & out_womask_368; // @[RegisterRouter.scala:87:24] wire _out_T_3959 = ~out_rimask_368; // @[RegisterRouter.scala:87:24] wire _out_T_3960 = ~out_wimask_368; // @[RegisterRouter.scala:87:24] wire _out_T_3961 = ~out_romask_368; // @[RegisterRouter.scala:87:24] wire _out_T_3962 = ~out_womask_368; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_306 = {hi_1007, flags_0_go, _out_prepend_T_306}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3963 = out_prepend_306; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3964 = _out_T_3963; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_307 = _out_T_3964; // @[RegisterRouter.scala:87:24] wire out_rimask_369 = \|_out_rimask_T_369; // @[RegisterRouter.scala:87:24] wire out_wimask_369 = &_out_wimask_T_369; // @[RegisterRouter.scala:87:24] wire out_romask_369 = \|_out_romask_T_369; // @[RegisterRouter.scala:87:24] wire out_womask_369 = &_out_womask_T_369; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_369 = out_rivalid_1_223 & out_rimask_369; // @[RegisterRouter.scala:87:24] wire _out_T_3966 = out_f_rivalid_369; // @[RegisterRouter.scala:87:24] wire out_f_roready_369 = out_roready_1_223 & out_romask_369; // @[RegisterRouter.scala:87:24] wire _out_T_3967 = out_f_roready_369; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_369 = out_wivalid_1_223 & out_wimask_369; // @[RegisterRouter.scala:87:24] wire out_f_woready_369 = out_woready_1_223 & out_womask_369; // @[RegisterRouter.scala:87:24] wire _out_T_3968 = ~out_rimask_369; // @[RegisterRouter.scala:87:24] wire _out_T_3969 = ~out_wimask_369; // @[RegisterRouter.scala:87:24] wire _out_T_3970 = ~out_romask_369; // @[RegisterRouter.scala:87:24] wire _out_T_3971 = ~out_womask_369; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_307 = {hi_1008, flags_0_go, _out_prepend_T_307}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3972 = out_prepend_307; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3973 = _out_T_3972; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_253 = _out_T_3973; // @[MuxLiteral.scala:49:48] wire out_rimask_370 = \|_out_rimask_T_370; // @[RegisterRouter.scala:87:24] wire out_wimask_370 = &_out_wimask_T_370; // @[RegisterRouter.scala:87:24] wire out_romask_370 = \|_out_romask_T_370; // @[RegisterRouter.scala:87:24] wire out_womask_370 = &_out_womask_T_370; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_370 = out_rivalid_1_224 & out_rimask_370; // @[RegisterRouter.scala:87:24] wire _out_T_3975 = out_f_rivalid_370; // @[RegisterRouter.scala:87:24] wire out_f_roready_370 = out_roready_1_224 & out_romask_370; // @[RegisterRouter.scala:87:24] wire _out_T_3976 = out_f_roready_370; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_370 = out_wivalid_1_224 & out_wimask_370; // @[RegisterRouter.scala:87:24] wire out_f_woready_370 = out_woready_1_224 & out_womask_370; // @[RegisterRouter.scala:87:24] wire _out_T_3977 = ~out_rimask_370; // @[RegisterRouter.scala:87:24] wire _out_T_3978 = ~out_wimask_370; // @[RegisterRouter.scala:87:24] wire _out_T_3979 = ~out_romask_370; // @[RegisterRouter.scala:87:24] wire _out_T_3980 = ~out_womask_370; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3982 = _out_T_3981; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_308 = _out_T_3982; // @[RegisterRouter.scala:87:24] wire out_rimask_371 = \|_out_rimask_T_371; // @[RegisterRouter.scala:87:24] wire out_wimask_371 = &_out_wimask_T_371; // @[RegisterRouter.scala:87:24] wire out_romask_371 = \|_out_romask_T_371; // @[RegisterRouter.scala:87:24] wire out_womask_371 = &_out_womask_T_371; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_371 = out_rivalid_1_225 & out_rimask_371; // @[RegisterRouter.scala:87:24] wire _out_T_3984 = out_f_rivalid_371; // @[RegisterRouter.scala:87:24] wire out_f_roready_371 = out_roready_1_225 & out_romask_371; // @[RegisterRouter.scala:87:24] wire _out_T_3985 = out_f_roready_371; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_371 = out_wivalid_1_225 & out_wimask_371; // @[RegisterRouter.scala:87:24] wire out_f_woready_371 = out_woready_1_225 & out_womask_371; // @[RegisterRouter.scala:87:24] wire _out_T_3986 = ~out_rimask_371; // @[RegisterRouter.scala:87:24] wire _out_T_3987 = ~out_wimask_371; // @[RegisterRouter.scala:87:24] wire _out_T_3988 = ~out_romask_371; // @[RegisterRouter.scala:87:24] wire _out_T_3989 = ~out_womask_371; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_308 = {hi_154, flags_0_go, _out_prepend_T_308}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3990 = out_prepend_308; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3991 = _out_T_3990; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_309 = _out_T_3991; // @[RegisterRouter.scala:87:24] wire out_rimask_372 = \|_out_rimask_T_372; // @[RegisterRouter.scala:87:24] wire out_wimask_372 = &_out_wimask_T_372; // @[RegisterRouter.scala:87:24] wire out_romask_372 = \|_out_romask_T_372; // @[RegisterRouter.scala:87:24] wire out_womask_372 = &_out_womask_T_372; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_372 = out_rivalid_1_226 & out_rimask_372; // @[RegisterRouter.scala:87:24] wire _out_T_3993 = out_f_rivalid_372; // @[RegisterRouter.scala:87:24] wire out_f_roready_372 = out_roready_1_226 & out_romask_372; // @[RegisterRouter.scala:87:24] wire _out_T_3994 = out_f_roready_372; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_372 = out_wivalid_1_226 & out_wimask_372; // @[RegisterRouter.scala:87:24] wire out_f_woready_372 = out_woready_1_226 & out_womask_372; // @[RegisterRouter.scala:87:24] wire _out_T_3995 = ~out_rimask_372; // @[RegisterRouter.scala:87:24] wire _out_T_3996 = ~out_wimask_372; // @[RegisterRouter.scala:87:24] wire _out_T_3997 = ~out_romask_372; // @[RegisterRouter.scala:87:24] wire _out_T_3998 = ~out_womask_372; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_309 = {hi_155, flags_0_go, _out_prepend_T_309}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3999 = out_prepend_309; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4000 = _out_T_3999; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_310 = _out_T_4000; // @[RegisterRouter.scala:87:24] wire out_rimask_373 = \|_out_rimask_T_373; // @[RegisterRouter.scala:87:24] wire out_wimask_373 = &_out_wimask_T_373; // @[RegisterRouter.scala:87:24] wire out_romask_373 = \|_out_romask_T_373; // @[RegisterRouter.scala:87:24] wire out_womask_373 = &_out_womask_T_373; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_373 = out_rivalid_1_227 & out_rimask_373; // @[RegisterRouter.scala:87:24] wire _out_T_4002 = out_f_rivalid_373; // @[RegisterRouter.scala:87:24] wire out_f_roready_373 = out_roready_1_227 & out_romask_373; // @[RegisterRouter.scala:87:24] wire _out_T_4003 = out_f_roready_373; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_373 = out_wivalid_1_227 & out_wimask_373; // @[RegisterRouter.scala:87:24] wire out_f_woready_373 = out_woready_1_227 & out_womask_373; // @[RegisterRouter.scala:87:24] wire _out_T_4004 = ~out_rimask_373; // @[RegisterRouter.scala:87:24] wire _out_T_4005 = ~out_wimask_373; // @[RegisterRouter.scala:87:24] wire _out_T_4006 = ~out_romask_373; // @[RegisterRouter.scala:87:24] wire _out_T_4007 = ~out_womask_373; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_310 = {hi_156, flags_0_go, _out_prepend_T_310}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4008 = out_prepend_310; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4009 = _out_T_4008; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_311 = _out_T_4009; // @[RegisterRouter.scala:87:24] wire out_rimask_374 = \|_out_rimask_T_374; // @[RegisterRouter.scala:87:24] wire out_wimask_374 = &_out_wimask_T_374; // @[RegisterRouter.scala:87:24] wire out_romask_374 = \|_out_romask_T_374; // @[RegisterRouter.scala:87:24] wire out_womask_374 = &_out_womask_T_374; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_374 = out_rivalid_1_228 & out_rimask_374; // @[RegisterRouter.scala:87:24] wire _out_T_4011 = out_f_rivalid_374; // @[RegisterRouter.scala:87:24] wire out_f_roready_374 = out_roready_1_228 & out_romask_374; // @[RegisterRouter.scala:87:24] wire _out_T_4012 = out_f_roready_374; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_374 = out_wivalid_1_228 & out_wimask_374; // @[RegisterRouter.scala:87:24] wire out_f_woready_374 = out_woready_1_228 & out_womask_374; // @[RegisterRouter.scala:87:24] wire _out_T_4013 = ~out_rimask_374; // @[RegisterRouter.scala:87:24] wire _out_T_4014 = ~out_wimask_374; // @[RegisterRouter.scala:87:24] wire _out_T_4015 = ~out_romask_374; // @[RegisterRouter.scala:87:24] wire _out_T_4016 = ~out_womask_374; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_311 = {hi_157, flags_0_go, _out_prepend_T_311}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4017 = out_prepend_311; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4018 = _out_T_4017; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_312 = _out_T_4018; // @[RegisterRouter.scala:87:24] wire out_rimask_375 = \|_out_rimask_T_375; // @[RegisterRouter.scala:87:24] wire out_wimask_375 = &_out_wimask_T_375; // @[RegisterRouter.scala:87:24] wire out_romask_375 = \|_out_romask_T_375; // @[RegisterRouter.scala:87:24] wire out_womask_375 = &_out_womask_T_375; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_375 = out_rivalid_1_229 & out_rimask_375; // @[RegisterRouter.scala:87:24] wire _out_T_4020 = out_f_rivalid_375; // @[RegisterRouter.scala:87:24] wire out_f_roready_375 = out_roready_1_229 & out_romask_375; // @[RegisterRouter.scala:87:24] wire _out_T_4021 = out_f_roready_375; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_375 = out_wivalid_1_229 & out_wimask_375; // @[RegisterRouter.scala:87:24] wire out_f_woready_375 = out_woready_1_229 & out_womask_375; // @[RegisterRouter.scala:87:24] wire _out_T_4022 = ~out_rimask_375; // @[RegisterRouter.scala:87:24] wire _out_T_4023 = ~out_wimask_375; // @[RegisterRouter.scala:87:24] wire _out_T_4024 = ~out_romask_375; // @[RegisterRouter.scala:87:24] wire _out_T_4025 = ~out_womask_375; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_312 = {hi_158, flags_0_go, _out_prepend_T_312}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4026 = out_prepend_312; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4027 = _out_T_4026; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_313 = _out_T_4027; // @[RegisterRouter.scala:87:24] wire out_rimask_376 = \|_out_rimask_T_376; // @[RegisterRouter.scala:87:24] wire out_wimask_376 = &_out_wimask_T_376; // @[RegisterRouter.scala:87:24] wire out_romask_376 = \|_out_romask_T_376; // @[RegisterRouter.scala:87:24] wire out_womask_376 = &_out_womask_T_376; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_376 = out_rivalid_1_230 & out_rimask_376; // @[RegisterRouter.scala:87:24] wire _out_T_4029 = out_f_rivalid_376; // @[RegisterRouter.scala:87:24] wire out_f_roready_376 = out_roready_1_230 & out_romask_376; // @[RegisterRouter.scala:87:24] wire _out_T_4030 = out_f_roready_376; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_376 = out_wivalid_1_230 & out_wimask_376; // @[RegisterRouter.scala:87:24] wire out_f_woready_376 = out_woready_1_230 & out_womask_376; // @[RegisterRouter.scala:87:24] wire _out_T_4031 = ~out_rimask_376; // @[RegisterRouter.scala:87:24] wire _out_T_4032 = ~out_wimask_376; // @[RegisterRouter.scala:87:24] wire _out_T_4033 = ~out_romask_376; // @[RegisterRouter.scala:87:24] wire _out_T_4034 = ~out_womask_376; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_313 = {hi_159, flags_0_go, _out_prepend_T_313}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4035 = out_prepend_313; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4036 = _out_T_4035; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_314 = _out_T_4036; // @[RegisterRouter.scala:87:24] wire out_rimask_377 = \|_out_rimask_T_377; // @[RegisterRouter.scala:87:24] wire out_wimask_377 = &_out_wimask_T_377; // @[RegisterRouter.scala:87:24] wire out_romask_377 = \|_out_romask_T_377; // @[RegisterRouter.scala:87:24] wire out_womask_377 = &_out_womask_T_377; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_377 = out_rivalid_1_231 & out_rimask_377; // @[RegisterRouter.scala:87:24] wire _out_T_4038 = out_f_rivalid_377; // @[RegisterRouter.scala:87:24] wire out_f_roready_377 = out_roready_1_231 & out_romask_377; // @[RegisterRouter.scala:87:24] wire _out_T_4039 = out_f_roready_377; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_377 = out_wivalid_1_231 & out_wimask_377; // @[RegisterRouter.scala:87:24] wire out_f_woready_377 = out_woready_1_231 & out_womask_377; // @[RegisterRouter.scala:87:24] wire _out_T_4040 = ~out_rimask_377; // @[RegisterRouter.scala:87:24] wire _out_T_4041 = ~out_wimask_377; // @[RegisterRouter.scala:87:24] wire _out_T_4042 = ~out_romask_377; // @[RegisterRouter.scala:87:24] wire _out_T_4043 = ~out_womask_377; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_314 = {hi_160, flags_0_go, _out_prepend_T_314}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4044 = out_prepend_314; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4045 = _out_T_4044; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_147 = _out_T_4045; // @[MuxLiteral.scala:49:48] wire out_rimask_378 = \|_out_rimask_T_378; // @[RegisterRouter.scala:87:24] wire out_wimask_378 = &_out_wimask_T_378; // @[RegisterRouter.scala:87:24] wire out_romask_378 = \|_out_romask_T_378; // @[RegisterRouter.scala:87:24] wire out_womask_378 = &_out_womask_T_378; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_378 = out_rivalid_1_232 & out_rimask_378; // @[RegisterRouter.scala:87:24] wire _out_T_4047 = out_f_rivalid_378; // @[RegisterRouter.scala:87:24] wire out_f_roready_378 = out_roready_1_232 & out_romask_378; // @[RegisterRouter.scala:87:24] wire _out_T_4048 = out_f_roready_378; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_378 = out_wivalid_1_232 & out_wimask_378; // @[RegisterRouter.scala:87:24] wire out_f_woready_378 = out_woready_1_232 & out_womask_378; // @[RegisterRouter.scala:87:24] wire _out_T_4049 = ~out_rimask_378; // @[RegisterRouter.scala:87:24] wire _out_T_4050 = ~out_wimask_378; // @[RegisterRouter.scala:87:24] wire _out_T_4051 = ~out_romask_378; // @[RegisterRouter.scala:87:24] wire _out_T_4052 = ~out_womask_378; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4054 = _out_T_4053; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_315 = _out_T_4054; // @[RegisterRouter.scala:87:24] wire out_rimask_379 = \|_out_rimask_T_379; // @[RegisterRouter.scala:87:24] wire out_wimask_379 = &_out_wimask_T_379; // @[RegisterRouter.scala:87:24] wire out_romask_379 = \|_out_romask_T_379; // @[RegisterRouter.scala:87:24] wire out_womask_379 = &_out_womask_T_379; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_379 = out_rivalid_1_233 & out_rimask_379; // @[RegisterRouter.scala:87:24] wire _out_T_4056 = out_f_rivalid_379; // @[RegisterRouter.scala:87:24] wire out_f_roready_379 = out_roready_1_233 & out_romask_379; // @[RegisterRouter.scala:87:24] wire _out_T_4057 = out_f_roready_379; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_379 = out_wivalid_1_233 & out_wimask_379; // @[RegisterRouter.scala:87:24] wire out_f_woready_379 = out_woready_1_233 & out_womask_379; // @[RegisterRouter.scala:87:24] wire _out_T_4058 = ~out_rimask_379; // @[RegisterRouter.scala:87:24] wire _out_T_4059 = ~out_wimask_379; // @[RegisterRouter.scala:87:24] wire _out_T_4060 = ~out_romask_379; // @[RegisterRouter.scala:87:24] wire _out_T_4061 = ~out_womask_379; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_315 = {hi_746, flags_0_go, _out_prepend_T_315}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4062 = out_prepend_315; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4063 = _out_T_4062; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_316 = _out_T_4063; // @[RegisterRouter.scala:87:24] wire out_rimask_380 = \|_out_rimask_T_380; // @[RegisterRouter.scala:87:24] wire out_wimask_380 = &_out_wimask_T_380; // @[RegisterRouter.scala:87:24] wire out_romask_380 = \|_out_romask_T_380; // @[RegisterRouter.scala:87:24] wire out_womask_380 = &_out_womask_T_380; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_380 = out_rivalid_1_234 & out_rimask_380; // @[RegisterRouter.scala:87:24] wire _out_T_4065 = out_f_rivalid_380; // @[RegisterRouter.scala:87:24] wire out_f_roready_380 = out_roready_1_234 & out_romask_380; // @[RegisterRouter.scala:87:24] wire _out_T_4066 = out_f_roready_380; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_380 = out_wivalid_1_234 & out_wimask_380; // @[RegisterRouter.scala:87:24] wire out_f_woready_380 = out_woready_1_234 & out_womask_380; // @[RegisterRouter.scala:87:24] wire _out_T_4067 = ~out_rimask_380; // @[RegisterRouter.scala:87:24] wire _out_T_4068 = ~out_wimask_380; // @[RegisterRouter.scala:87:24] wire _out_T_4069 = ~out_romask_380; // @[RegisterRouter.scala:87:24] wire _out_T_4070 = ~out_womask_380; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_316 = {hi_747, flags_0_go, _out_prepend_T_316}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4071 = out_prepend_316; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4072 = _out_T_4071; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_317 = _out_T_4072; // @[RegisterRouter.scala:87:24] wire out_rimask_381 = \|_out_rimask_T_381; // @[RegisterRouter.scala:87:24] wire out_wimask_381 = &_out_wimask_T_381; // @[RegisterRouter.scala:87:24] wire out_romask_381 = \|_out_romask_T_381; // @[RegisterRouter.scala:87:24] wire out_womask_381 = &_out_womask_T_381; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_381 = out_rivalid_1_235 & out_rimask_381; // @[RegisterRouter.scala:87:24] wire _out_T_4074 = out_f_rivalid_381; // @[RegisterRouter.scala:87:24] wire out_f_roready_381 = out_roready_1_235 & out_romask_381; // @[RegisterRouter.scala:87:24] wire _out_T_4075 = out_f_roready_381; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_381 = out_wivalid_1_235 & out_wimask_381; // @[RegisterRouter.scala:87:24] wire out_f_woready_381 = out_woready_1_235 & out_womask_381; // @[RegisterRouter.scala:87:24] wire _out_T_4076 = ~out_rimask_381; // @[RegisterRouter.scala:87:24] wire _out_T_4077 = ~out_wimask_381; // @[RegisterRouter.scala:87:24] wire _out_T_4078 = ~out_romask_381; // @[RegisterRouter.scala:87:24] wire _out_T_4079 = ~out_womask_381; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_317 = {hi_748, flags_0_go, _out_prepend_T_317}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4080 = out_prepend_317; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4081 = _out_T_4080; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_318 = _out_T_4081; // @[RegisterRouter.scala:87:24] wire out_rimask_382 = \|_out_rimask_T_382; // @[RegisterRouter.scala:87:24] wire out_wimask_382 = &_out_wimask_T_382; // @[RegisterRouter.scala:87:24] wire out_romask_382 = \|_out_romask_T_382; // @[RegisterRouter.scala:87:24] wire out_womask_382 = &_out_womask_T_382; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_382 = out_rivalid_1_236 & out_rimask_382; // @[RegisterRouter.scala:87:24] wire _out_T_4083 = out_f_rivalid_382; // @[RegisterRouter.scala:87:24] wire out_f_roready_382 = out_roready_1_236 & out_romask_382; // @[RegisterRouter.scala:87:24] wire _out_T_4084 = out_f_roready_382; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_382 = out_wivalid_1_236 & out_wimask_382; // @[RegisterRouter.scala:87:24] wire out_f_woready_382 = out_woready_1_236 & out_womask_382; // @[RegisterRouter.scala:87:24] wire _out_T_4085 = ~out_rimask_382; // @[RegisterRouter.scala:87:24] wire _out_T_4086 = ~out_wimask_382; // @[RegisterRouter.scala:87:24] wire _out_T_4087 = ~out_romask_382; // @[RegisterRouter.scala:87:24] wire _out_T_4088 = ~out_womask_382; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_318 = {hi_749, flags_0_go, _out_prepend_T_318}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4089 = out_prepend_318; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4090 = _out_T_4089; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_319 = _out_T_4090; // @[RegisterRouter.scala:87:24] wire out_rimask_383 = \|_out_rimask_T_383; // @[RegisterRouter.scala:87:24] wire out_wimask_383 = &_out_wimask_T_383; // @[RegisterRouter.scala:87:24] wire out_romask_383 = \|_out_romask_T_383; // @[RegisterRouter.scala:87:24] wire out_womask_383 = &_out_womask_T_383; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_383 = out_rivalid_1_237 & out_rimask_383; // @[RegisterRouter.scala:87:24] wire _out_T_4092 = out_f_rivalid_383; // @[RegisterRouter.scala:87:24] wire out_f_roready_383 = out_roready_1_237 & out_romask_383; // @[RegisterRouter.scala:87:24] wire _out_T_4093 = out_f_roready_383; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_383 = out_wivalid_1_237 & out_wimask_383; // @[RegisterRouter.scala:87:24] wire out_f_woready_383 = out_woready_1_237 & out_womask_383; // @[RegisterRouter.scala:87:24] wire _out_T_4094 = ~out_rimask_383; // @[RegisterRouter.scala:87:24] wire _out_T_4095 = ~out_wimask_383; // @[RegisterRouter.scala:87:24] wire _out_T_4096 = ~out_romask_383; // @[RegisterRouter.scala:87:24] wire _out_T_4097 = ~out_womask_383; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_319 = {hi_750, flags_0_go, _out_prepend_T_319}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4098 = out_prepend_319; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4099 = _out_T_4098; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_320 = _out_T_4099; // @[RegisterRouter.scala:87:24] wire out_rimask_384 = \|_out_rimask_T_384; // @[RegisterRouter.scala:87:24] wire out_wimask_384 = &_out_wimask_T_384; // @[RegisterRouter.scala:87:24] wire out_romask_384 = \|_out_romask_T_384; // @[RegisterRouter.scala:87:24] wire out_womask_384 = &_out_womask_T_384; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_384 = out_rivalid_1_238 & out_rimask_384; // @[RegisterRouter.scala:87:24] wire _out_T_4101 = out_f_rivalid_384; // @[RegisterRouter.scala:87:24] wire out_f_roready_384 = out_roready_1_238 & out_romask_384; // @[RegisterRouter.scala:87:24] wire _out_T_4102 = out_f_roready_384; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_384 = out_wivalid_1_238 & out_wimask_384; // @[RegisterRouter.scala:87:24] wire out_f_woready_384 = out_woready_1_238 & out_womask_384; // @[RegisterRouter.scala:87:24] wire _out_T_4103 = ~out_rimask_384; // @[RegisterRouter.scala:87:24] wire _out_T_4104 = ~out_wimask_384; // @[RegisterRouter.scala:87:24] wire _out_T_4105 = ~out_romask_384; // @[RegisterRouter.scala:87:24] wire _out_T_4106 = ~out_womask_384; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_320 = {hi_751, flags_0_go, _out_prepend_T_320}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4107 = out_prepend_320; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4108 = _out_T_4107; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_321 = _out_T_4108; // @[RegisterRouter.scala:87:24] wire out_rimask_385 = \|_out_rimask_T_385; // @[RegisterRouter.scala:87:24] wire out_wimask_385 = &_out_wimask_T_385; // @[RegisterRouter.scala:87:24] wire out_romask_385 = \|_out_romask_T_385; // @[RegisterRouter.scala:87:24] wire out_womask_385 = &_out_womask_T_385; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_385 = out_rivalid_1_239 & out_rimask_385; // @[RegisterRouter.scala:87:24] wire _out_T_4110 = out_f_rivalid_385; // @[RegisterRouter.scala:87:24] wire out_f_roready_385 = out_roready_1_239 & out_romask_385; // @[RegisterRouter.scala:87:24] wire _out_T_4111 = out_f_roready_385; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_385 = out_wivalid_1_239 & out_wimask_385; // @[RegisterRouter.scala:87:24] wire out_f_woready_385 = out_woready_1_239 & out_womask_385; // @[RegisterRouter.scala:87:24] wire _out_T_4112 = ~out_rimask_385; // @[RegisterRouter.scala:87:24] wire _out_T_4113 = ~out_wimask_385; // @[RegisterRouter.scala:87:24] wire _out_T_4114 = ~out_romask_385; // @[RegisterRouter.scala:87:24] wire _out_T_4115 = ~out_womask_385; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_321 = {hi_752, flags_0_go, _out_prepend_T_321}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4116 = out_prepend_321; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4117 = _out_T_4116; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_221 = _out_T_4117; // @[MuxLiteral.scala:49:48] wire out_rimask_386 = \|_out_rimask_T_386; // @[RegisterRouter.scala:87:24] wire out_wimask_386 = &_out_wimask_T_386; // @[RegisterRouter.scala:87:24] wire out_romask_386 = \|_out_romask_T_386; // @[RegisterRouter.scala:87:24] wire out_womask_386 = &_out_womask_T_386; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_386 = out_rivalid_1_240 & out_rimask_386; // @[RegisterRouter.scala:87:24] wire _out_T_4119 = out_f_rivalid_386; // @[RegisterRouter.scala:87:24] wire out_f_roready_386 = out_roready_1_240 & out_romask_386; // @[RegisterRouter.scala:87:24] wire _out_T_4120 = out_f_roready_386; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_386 = out_wivalid_1_240 & out_wimask_386; // @[RegisterRouter.scala:87:24] wire out_f_woready_386 = out_woready_1_240 & out_womask_386; // @[RegisterRouter.scala:87:24] wire _out_T_4121 = ~out_rimask_386; // @[RegisterRouter.scala:87:24] wire _out_T_4122 = ~out_wimask_386; // @[RegisterRouter.scala:87:24] wire _out_T_4123 = ~out_romask_386; // @[RegisterRouter.scala:87:24] wire _out_T_4124 = ~out_womask_386; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4126 = _out_T_4125; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_322 = _out_T_4126; // @[RegisterRouter.scala:87:24] wire out_rimask_387 = \|_out_rimask_T_387; // @[RegisterRouter.scala:87:24] wire out_wimask_387 = &_out_wimask_T_387; // @[RegisterRouter.scala:87:24] wire out_romask_387 = \|_out_romask_T_387; // @[RegisterRouter.scala:87:24] wire out_womask_387 = &_out_womask_T_387; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_387 = out_rivalid_1_241 & out_rimask_387; // @[RegisterRouter.scala:87:24] wire _out_T_4128 = out_f_rivalid_387; // @[RegisterRouter.scala:87:24] wire out_f_roready_387 = out_roready_1_241 & out_romask_387; // @[RegisterRouter.scala:87:24] wire _out_T_4129 = out_f_roready_387; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_387 = out_wivalid_1_241 & out_wimask_387; // @[RegisterRouter.scala:87:24] wire out_f_woready_387 = out_woready_1_241 & out_womask_387; // @[RegisterRouter.scala:87:24] wire _out_T_4130 = ~out_rimask_387; // @[RegisterRouter.scala:87:24] wire _out_T_4131 = ~out_wimask_387; // @[RegisterRouter.scala:87:24] wire _out_T_4132 = ~out_romask_387; // @[RegisterRouter.scala:87:24] wire _out_T_4133 = ~out_womask_387; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_322 = {hi_34, flags_0_go, _out_prepend_T_322}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4134 = out_prepend_322; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4135 = _out_T_4134; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_323 = _out_T_4135; // @[RegisterRouter.scala:87:24] wire out_rimask_388 = \|_out_rimask_T_388; // @[RegisterRouter.scala:87:24] wire out_wimask_388 = &_out_wimask_T_388; // @[RegisterRouter.scala:87:24] wire out_romask_388 = \|_out_romask_T_388; // @[RegisterRouter.scala:87:24] wire out_womask_388 = &_out_womask_T_388; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_388 = out_rivalid_1_242 & out_rimask_388; // @[RegisterRouter.scala:87:24] wire _out_T_4137 = out_f_rivalid_388; // @[RegisterRouter.scala:87:24] wire out_f_roready_388 = out_roready_1_242 & out_romask_388; // @[RegisterRouter.scala:87:24] wire _out_T_4138 = out_f_roready_388; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_388 = out_wivalid_1_242 & out_wimask_388; // @[RegisterRouter.scala:87:24] wire out_f_woready_388 = out_woready_1_242 & out_womask_388; // @[RegisterRouter.scala:87:24] wire _out_T_4139 = ~out_rimask_388; // @[RegisterRouter.scala:87:24] wire _out_T_4140 = ~out_wimask_388; // @[RegisterRouter.scala:87:24] wire _out_T_4141 = ~out_romask_388; // @[RegisterRouter.scala:87:24] wire _out_T_4142 = ~out_womask_388; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_323 = {hi_35, flags_0_go, _out_prepend_T_323}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4143 = out_prepend_323; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4144 = _out_T_4143; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_324 = _out_T_4144; // @[RegisterRouter.scala:87:24] wire out_rimask_389 = \|_out_rimask_T_389; // @[RegisterRouter.scala:87:24] wire out_wimask_389 = &_out_wimask_T_389; // @[RegisterRouter.scala:87:24] wire out_romask_389 = \|_out_romask_T_389; // @[RegisterRouter.scala:87:24] wire out_womask_389 = &_out_womask_T_389; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_389 = out_rivalid_1_243 & out_rimask_389; // @[RegisterRouter.scala:87:24] wire _out_T_4146 = out_f_rivalid_389; // @[RegisterRouter.scala:87:24] wire out_f_roready_389 = out_roready_1_243 & out_romask_389; // @[RegisterRouter.scala:87:24] wire _out_T_4147 = out_f_roready_389; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_389 = out_wivalid_1_243 & out_wimask_389; // @[RegisterRouter.scala:87:24] wire out_f_woready_389 = out_woready_1_243 & out_womask_389; // @[RegisterRouter.scala:87:24] wire _out_T_4148 = ~out_rimask_389; // @[RegisterRouter.scala:87:24] wire _out_T_4149 = ~out_wimask_389; // @[RegisterRouter.scala:87:24] wire _out_T_4150 = ~out_romask_389; // @[RegisterRouter.scala:87:24] wire _out_T_4151 = ~out_womask_389; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_324 = {hi_36, flags_0_go, _out_prepend_T_324}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4152 = out_prepend_324; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4153 = _out_T_4152; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_325 = _out_T_4153; // @[RegisterRouter.scala:87:24] wire out_rimask_390 = \|_out_rimask_T_390; // @[RegisterRouter.scala:87:24] wire out_wimask_390 = &_out_wimask_T_390; // @[RegisterRouter.scala:87:24] wire out_romask_390 = \|_out_romask_T_390; // @[RegisterRouter.scala:87:24] wire out_womask_390 = &_out_womask_T_390; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_390 = out_rivalid_1_244 & out_rimask_390; // @[RegisterRouter.scala:87:24] wire _out_T_4155 = out_f_rivalid_390; // @[RegisterRouter.scala:87:24] wire out_f_roready_390 = out_roready_1_244 & out_romask_390; // @[RegisterRouter.scala:87:24] wire _out_T_4156 = out_f_roready_390; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_390 = out_wivalid_1_244 & out_wimask_390; // @[RegisterRouter.scala:87:24] wire out_f_woready_390 = out_woready_1_244 & out_womask_390; // @[RegisterRouter.scala:87:24] wire _out_T_4157 = ~out_rimask_390; // @[RegisterRouter.scala:87:24] wire _out_T_4158 = ~out_wimask_390; // @[RegisterRouter.scala:87:24] wire _out_T_4159 = ~out_romask_390; // @[RegisterRouter.scala:87:24] wire _out_T_4160 = ~out_womask_390; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_325 = {hi_37, flags_0_go, _out_prepend_T_325}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4161 = out_prepend_325; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4162 = _out_T_4161; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_326 = _out_T_4162; // @[RegisterRouter.scala:87:24] wire out_rimask_391 = \|_out_rimask_T_391; // @[RegisterRouter.scala:87:24] wire out_wimask_391 = &_out_wimask_T_391; // @[RegisterRouter.scala:87:24] wire out_romask_391 = \|_out_romask_T_391; // @[RegisterRouter.scala:87:24] wire out_womask_391 = &_out_womask_T_391; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_391 = out_rivalid_1_245 & out_rimask_391; // @[RegisterRouter.scala:87:24] wire _out_T_4164 = out_f_rivalid_391; // @[RegisterRouter.scala:87:24] wire out_f_roready_391 = out_roready_1_245 & out_romask_391; // @[RegisterRouter.scala:87:24] wire _out_T_4165 = out_f_roready_391; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_391 = out_wivalid_1_245 & out_wimask_391; // @[RegisterRouter.scala:87:24] wire out_f_woready_391 = out_woready_1_245 & out_womask_391; // @[RegisterRouter.scala:87:24] wire _out_T_4166 = ~out_rimask_391; // @[RegisterRouter.scala:87:24] wire _out_T_4167 = ~out_wimask_391; // @[RegisterRouter.scala:87:24] wire _out_T_4168 = ~out_romask_391; // @[RegisterRouter.scala:87:24] wire _out_T_4169 = ~out_womask_391; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_326 = {hi_38, flags_0_go, _out_prepend_T_326}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4170 = out_prepend_326; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4171 = _out_T_4170; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_327 = _out_T_4171; // @[RegisterRouter.scala:87:24] wire out_rimask_392 = \|_out_rimask_T_392; // @[RegisterRouter.scala:87:24] wire out_wimask_392 = &_out_wimask_T_392; // @[RegisterRouter.scala:87:24] wire out_romask_392 = \|_out_romask_T_392; // @[RegisterRouter.scala:87:24] wire out_womask_392 = &_out_womask_T_392; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_392 = out_rivalid_1_246 & out_rimask_392; // @[RegisterRouter.scala:87:24] wire _out_T_4173 = out_f_rivalid_392; // @[RegisterRouter.scala:87:24] wire out_f_roready_392 = out_roready_1_246 & out_romask_392; // @[RegisterRouter.scala:87:24] wire _out_T_4174 = out_f_roready_392; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_392 = out_wivalid_1_246 & out_wimask_392; // @[RegisterRouter.scala:87:24] wire out_f_woready_392 = out_woready_1_246 & out_womask_392; // @[RegisterRouter.scala:87:24] wire _out_T_4175 = ~out_rimask_392; // @[RegisterRouter.scala:87:24] wire _out_T_4176 = ~out_wimask_392; // @[RegisterRouter.scala:87:24] wire _out_T_4177 = ~out_romask_392; // @[RegisterRouter.scala:87:24] wire _out_T_4178 = ~out_womask_392; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_327 = {hi_39, flags_0_go, _out_prepend_T_327}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4179 = out_prepend_327; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4180 = _out_T_4179; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_328 = _out_T_4180; // @[RegisterRouter.scala:87:24] wire out_rimask_393 = \|_out_rimask_T_393; // @[RegisterRouter.scala:87:24] wire out_wimask_393 = &_out_wimask_T_393; // @[RegisterRouter.scala:87:24] wire out_romask_393 = \|_out_romask_T_393; // @[RegisterRouter.scala:87:24] wire out_womask_393 = &_out_womask_T_393; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_393 = out_rivalid_1_247 & out_rimask_393; // @[RegisterRouter.scala:87:24] wire _out_T_4182 = out_f_rivalid_393; // @[RegisterRouter.scala:87:24] wire out_f_roready_393 = out_roready_1_247 & out_romask_393; // @[RegisterRouter.scala:87:24] wire _out_T_4183 = out_f_roready_393; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_393 = out_wivalid_1_247 & out_wimask_393; // @[RegisterRouter.scala:87:24] wire out_f_woready_393 = out_woready_1_247 & out_womask_393; // @[RegisterRouter.scala:87:24] wire _out_T_4184 = ~out_rimask_393; // @[RegisterRouter.scala:87:24] wire _out_T_4185 = ~out_wimask_393; // @[RegisterRouter.scala:87:24] wire _out_T_4186 = ~out_romask_393; // @[RegisterRouter.scala:87:24] wire _out_T_4187 = ~out_womask_393; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_328 = {hi_40, flags_0_go, _out_prepend_T_328}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4188 = out_prepend_328; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4189 = _out_T_4188; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_132 = _out_T_4189; // @[MuxLiteral.scala:49:48] wire out_rimask_394 = \|_out_rimask_T_394; // @[RegisterRouter.scala:87:24] wire out_wimask_394 = &_out_wimask_T_394; // @[RegisterRouter.scala:87:24] wire out_romask_394 = \|_out_romask_T_394; // @[RegisterRouter.scala:87:24] wire out_womask_394 = &_out_womask_T_394; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_394 = out_rivalid_1_248 & out_rimask_394; // @[RegisterRouter.scala:87:24] wire _out_T_4191 = out_f_rivalid_394; // @[RegisterRouter.scala:87:24] wire out_f_roready_394 = out_roready_1_248 & out_romask_394; // @[RegisterRouter.scala:87:24] wire _out_T_4192 = out_f_roready_394; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_394 = out_wivalid_1_248 & out_wimask_394; // @[RegisterRouter.scala:87:24] wire out_f_woready_394 = out_woready_1_248 & out_womask_394; // @[RegisterRouter.scala:87:24] wire _out_T_4193 = ~out_rimask_394; // @[RegisterRouter.scala:87:24] wire _out_T_4194 = ~out_wimask_394; // @[RegisterRouter.scala:87:24] wire _out_T_4195 = ~out_romask_394; // @[RegisterRouter.scala:87:24] wire _out_T_4196 = ~out_womask_394; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4198 = _out_T_4197; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_329 = _out_T_4198; // @[RegisterRouter.scala:87:24] wire out_rimask_395 = \|_out_rimask_T_395; // @[RegisterRouter.scala:87:24] wire out_wimask_395 = &_out_wimask_T_395; // @[RegisterRouter.scala:87:24] wire out_romask_395 = \|_out_romask_T_395; // @[RegisterRouter.scala:87:24] wire out_womask_395 = &_out_womask_T_395; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_395 = out_rivalid_1_249 & out_rimask_395; // @[RegisterRouter.scala:87:24] wire _out_T_4200 = out_f_rivalid_395; // @[RegisterRouter.scala:87:24] wire out_f_roready_395 = out_roready_1_249 & out_romask_395; // @[RegisterRouter.scala:87:24] wire _out_T_4201 = out_f_roready_395; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_395 = out_wivalid_1_249 & out_wimask_395; // @[RegisterRouter.scala:87:24] wire out_f_woready_395 = out_woready_1_249 & out_womask_395; // @[RegisterRouter.scala:87:24] wire _out_T_4202 = ~out_rimask_395; // @[RegisterRouter.scala:87:24] wire _out_T_4203 = ~out_wimask_395; // @[RegisterRouter.scala:87:24] wire _out_T_4204 = ~out_romask_395; // @[RegisterRouter.scala:87:24] wire _out_T_4205 = ~out_womask_395; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_329 = {hi_42, flags_0_go, _out_prepend_T_329}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4206 = out_prepend_329; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4207 = _out_T_4206; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_330 = _out_T_4207; // @[RegisterRouter.scala:87:24] wire out_rimask_396 = \|_out_rimask_T_396; // @[RegisterRouter.scala:87:24] wire out_wimask_396 = &_out_wimask_T_396; // @[RegisterRouter.scala:87:24] wire out_romask_396 = \|_out_romask_T_396; // @[RegisterRouter.scala:87:24] wire out_womask_396 = &_out_womask_T_396; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_396 = out_rivalid_1_250 & out_rimask_396; // @[RegisterRouter.scala:87:24] wire _out_T_4209 = out_f_rivalid_396; // @[RegisterRouter.scala:87:24] wire out_f_roready_396 = out_roready_1_250 & out_romask_396; // @[RegisterRouter.scala:87:24] wire _out_T_4210 = out_f_roready_396; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_396 = out_wivalid_1_250 & out_wimask_396; // @[RegisterRouter.scala:87:24] wire out_f_woready_396 = out_woready_1_250 & out_womask_396; // @[RegisterRouter.scala:87:24] wire _out_T_4211 = ~out_rimask_396; // @[RegisterRouter.scala:87:24] wire _out_T_4212 = ~out_wimask_396; // @[RegisterRouter.scala:87:24] wire _out_T_4213 = ~out_romask_396; // @[RegisterRouter.scala:87:24] wire _out_T_4214 = ~out_womask_396; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_330 = {hi_43, flags_0_go, _out_prepend_T_330}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4215 = out_prepend_330; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4216 = _out_T_4215; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_331 = _out_T_4216; // @[RegisterRouter.scala:87:24] wire out_rimask_397 = \|_out_rimask_T_397; // @[RegisterRouter.scala:87:24] wire out_wimask_397 = &_out_wimask_T_397; // @[RegisterRouter.scala:87:24] wire out_romask_397 = \|_out_romask_T_397; // @[RegisterRouter.scala:87:24] wire out_womask_397 = &_out_womask_T_397; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_397 = out_rivalid_1_251 & out_rimask_397; // @[RegisterRouter.scala:87:24] wire _out_T_4218 = out_f_rivalid_397; // @[RegisterRouter.scala:87:24] wire out_f_roready_397 = out_roready_1_251 & out_romask_397; // @[RegisterRouter.scala:87:24] wire _out_T_4219 = out_f_roready_397; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_397 = out_wivalid_1_251 & out_wimask_397; // @[RegisterRouter.scala:87:24] wire out_f_woready_397 = out_woready_1_251 & out_womask_397; // @[RegisterRouter.scala:87:24] wire _out_T_4220 = ~out_rimask_397; // @[RegisterRouter.scala:87:24] wire _out_T_4221 = ~out_wimask_397; // @[RegisterRouter.scala:87:24] wire _out_T_4222 = ~out_romask_397; // @[RegisterRouter.scala:87:24] wire _out_T_4223 = ~out_womask_397; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_331 = {hi_44, flags_0_go, _out_prepend_T_331}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4224 = out_prepend_331; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4225 = _out_T_4224; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_332 = _out_T_4225; // @[RegisterRouter.scala:87:24] wire out_rimask_398 = \|_out_rimask_T_398; // @[RegisterRouter.scala:87:24] wire out_wimask_398 = &_out_wimask_T_398; // @[RegisterRouter.scala:87:24] wire out_romask_398 = \|_out_romask_T_398; // @[RegisterRouter.scala:87:24] wire out_womask_398 = &_out_womask_T_398; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_398 = out_rivalid_1_252 & out_rimask_398; // @[RegisterRouter.scala:87:24] wire _out_T_4227 = out_f_rivalid_398; // @[RegisterRouter.scala:87:24] wire out_f_roready_398 = out_roready_1_252 & out_romask_398; // @[RegisterRouter.scala:87:24] wire _out_T_4228 = out_f_roready_398; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_398 = out_wivalid_1_252 & out_wimask_398; // @[RegisterRouter.scala:87:24] wire out_f_woready_398 = out_woready_1_252 & out_womask_398; // @[RegisterRouter.scala:87:24] wire _out_T_4229 = ~out_rimask_398; // @[RegisterRouter.scala:87:24] wire _out_T_4230 = ~out_wimask_398; // @[RegisterRouter.scala:87:24] wire _out_T_4231 = ~out_romask_398; // @[RegisterRouter.scala:87:24] wire _out_T_4232 = ~out_womask_398; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_332 = {hi_45, flags_0_go, _out_prepend_T_332}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4233 = out_prepend_332; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4234 = _out_T_4233; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_333 = _out_T_4234; // @[RegisterRouter.scala:87:24] wire out_rimask_399 = \|_out_rimask_T_399; // @[RegisterRouter.scala:87:24] wire out_wimask_399 = &_out_wimask_T_399; // @[RegisterRouter.scala:87:24] wire out_romask_399 = \|_out_romask_T_399; // @[RegisterRouter.scala:87:24] wire out_womask_399 = &_out_womask_T_399; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_399 = out_rivalid_1_253 & out_rimask_399; // @[RegisterRouter.scala:87:24] wire _out_T_4236 = out_f_rivalid_399; // @[RegisterRouter.scala:87:24] wire out_f_roready_399 = out_roready_1_253 & out_romask_399; // @[RegisterRouter.scala:87:24] wire _out_T_4237 = out_f_roready_399; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_399 = out_wivalid_1_253 & out_wimask_399; // @[RegisterRouter.scala:87:24] wire out_f_woready_399 = out_woready_1_253 & out_womask_399; // @[RegisterRouter.scala:87:24] wire _out_T_4238 = ~out_rimask_399; // @[RegisterRouter.scala:87:24] wire _out_T_4239 = ~out_wimask_399; // @[RegisterRouter.scala:87:24] wire _out_T_4240 = ~out_romask_399; // @[RegisterRouter.scala:87:24] wire _out_T_4241 = ~out_womask_399; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_333 = {hi_46, flags_0_go, _out_prepend_T_333}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4242 = out_prepend_333; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4243 = _out_T_4242; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_334 = _out_T_4243; // @[RegisterRouter.scala:87:24] wire out_rimask_400 = \|_out_rimask_T_400; // @[RegisterRouter.scala:87:24] wire out_wimask_400 = &_out_wimask_T_400; // @[RegisterRouter.scala:87:24] wire out_romask_400 = \|_out_romask_T_400; // @[RegisterRouter.scala:87:24] wire out_womask_400 = &_out_womask_T_400; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_400 = out_rivalid_1_254 & out_rimask_400; // @[RegisterRouter.scala:87:24] wire _out_T_4245 = out_f_rivalid_400; // @[RegisterRouter.scala:87:24] wire out_f_roready_400 = out_roready_1_254 & out_romask_400; // @[RegisterRouter.scala:87:24] wire _out_T_4246 = out_f_roready_400; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_400 = out_wivalid_1_254 & out_wimask_400; // @[RegisterRouter.scala:87:24] wire out_f_woready_400 = out_woready_1_254 & out_womask_400; // @[RegisterRouter.scala:87:24] wire _out_T_4247 = ~out_rimask_400; // @[RegisterRouter.scala:87:24] wire _out_T_4248 = ~out_wimask_400; // @[RegisterRouter.scala:87:24] wire _out_T_4249 = ~out_romask_400; // @[RegisterRouter.scala:87:24] wire _out_T_4250 = ~out_womask_400; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_334 = {hi_47, flags_0_go, _out_prepend_T_334}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4251 = out_prepend_334; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4252 = _out_T_4251; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_335 = _out_T_4252; // @[RegisterRouter.scala:87:24] wire out_rimask_401 = \|_out_rimask_T_401; // @[RegisterRouter.scala:87:24] wire out_wimask_401 = &_out_wimask_T_401; // @[RegisterRouter.scala:87:24] wire out_romask_401 = \|_out_romask_T_401; // @[RegisterRouter.scala:87:24] wire out_womask_401 = &_out_womask_T_401; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_401 = out_rivalid_1_255 & out_rimask_401; // @[RegisterRouter.scala:87:24] wire _out_T_4254 = out_f_rivalid_401; // @[RegisterRouter.scala:87:24] wire out_f_roready_401 = out_roready_1_255 & out_romask_401; // @[RegisterRouter.scala:87:24] wire _out_T_4255 = out_f_roready_401; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_401 = out_wivalid_1_255 & out_wimask_401; // @[RegisterRouter.scala:87:24] wire out_f_woready_401 = out_woready_1_255 & out_womask_401; // @[RegisterRouter.scala:87:24] wire _out_T_4256 = ~out_rimask_401; // @[RegisterRouter.scala:87:24] wire _out_T_4257 = ~out_wimask_401; // @[RegisterRouter.scala:87:24] wire _out_T_4258 = ~out_romask_401; // @[RegisterRouter.scala:87:24] wire _out_T_4259 = ~out_womask_401; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_335 = {hi_48, flags_0_go, _out_prepend_T_335}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4260 = out_prepend_335; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4261 = _out_T_4260; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_133 = _out_T_4261; // @[MuxLiteral.scala:49:48] wire out_rimask_402 = \|_out_rimask_T_402; // @[RegisterRouter.scala:87:24] wire out_wimask_402 = &_out_wimask_T_402; // @[RegisterRouter.scala:87:24] wire out_romask_402 = \|_out_romask_T_402; // @[RegisterRouter.scala:87:24] wire out_womask_402 = &_out_womask_T_402; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_402 = out_rivalid_1_256 & out_rimask_402; // @[RegisterRouter.scala:87:24] wire _out_T_4263 = out_f_rivalid_402; // @[RegisterRouter.scala:87:24] wire out_f_roready_402 = out_roready_1_256 & out_romask_402; // @[RegisterRouter.scala:87:24] wire _out_T_4264 = out_f_roready_402; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_402 = out_wivalid_1_256 & out_wimask_402; // @[RegisterRouter.scala:87:24] wire out_f_woready_402 = out_woready_1_256 & out_womask_402; // @[RegisterRouter.scala:87:24] wire _out_T_4265 = ~out_rimask_402; // @[RegisterRouter.scala:87:24] wire _out_T_4266 = ~out_wimask_402; // @[RegisterRouter.scala:87:24] wire _out_T_4267 = ~out_romask_402; // @[RegisterRouter.scala:87:24] wire _out_T_4268 = ~out_womask_402; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4270 = _out_T_4269; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_336 = _out_T_4270; // @[RegisterRouter.scala:87:24] wire out_rimask_403 = \|_out_rimask_T_403; // @[RegisterRouter.scala:87:24] wire out_wimask_403 = &_out_wimask_T_403; // @[RegisterRouter.scala:87:24] wire out_romask_403 = \|_out_romask_T_403; // @[RegisterRouter.scala:87:24] wire out_womask_403 = &_out_womask_T_403; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_403 = out_rivalid_1_257 & out_rimask_403; // @[RegisterRouter.scala:87:24] wire _out_T_4272 = out_f_rivalid_403; // @[RegisterRouter.scala:87:24] wire out_f_roready_403 = out_roready_1_257 & out_romask_403; // @[RegisterRouter.scala:87:24] wire _out_T_4273 = out_f_roready_403; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_403 = out_wivalid_1_257 & out_wimask_403; // @[RegisterRouter.scala:87:24] wire out_f_woready_403 = out_woready_1_257 & out_womask_403; // @[RegisterRouter.scala:87:24] wire _out_T_4274 = ~out_rimask_403; // @[RegisterRouter.scala:87:24] wire _out_T_4275 = ~out_wimask_403; // @[RegisterRouter.scala:87:24] wire _out_T_4276 = ~out_romask_403; // @[RegisterRouter.scala:87:24] wire _out_T_4277 = ~out_womask_403; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_336 = {hi_922, flags_0_go, _out_prepend_T_336}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4278 = out_prepend_336; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4279 = _out_T_4278; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_337 = _out_T_4279; // @[RegisterRouter.scala:87:24] wire out_rimask_404 = \|_out_rimask_T_404; // @[RegisterRouter.scala:87:24] wire out_wimask_404 = &_out_wimask_T_404; // @[RegisterRouter.scala:87:24] wire out_romask_404 = \|_out_romask_T_404; // @[RegisterRouter.scala:87:24] wire out_womask_404 = &_out_womask_T_404; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_404 = out_rivalid_1_258 & out_rimask_404; // @[RegisterRouter.scala:87:24] wire _out_T_4281 = out_f_rivalid_404; // @[RegisterRouter.scala:87:24] wire out_f_roready_404 = out_roready_1_258 & out_romask_404; // @[RegisterRouter.scala:87:24] wire _out_T_4282 = out_f_roready_404; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_404 = out_wivalid_1_258 & out_wimask_404; // @[RegisterRouter.scala:87:24] wire out_f_woready_404 = out_woready_1_258 & out_womask_404; // @[RegisterRouter.scala:87:24] wire _out_T_4283 = ~out_rimask_404; // @[RegisterRouter.scala:87:24] wire _out_T_4284 = ~out_wimask_404; // @[RegisterRouter.scala:87:24] wire _out_T_4285 = ~out_romask_404; // @[RegisterRouter.scala:87:24] wire _out_T_4286 = ~out_womask_404; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_337 = {hi_923, flags_0_go, _out_prepend_T_337}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4287 = out_prepend_337; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4288 = _out_T_4287; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_338 = _out_T_4288; // @[RegisterRouter.scala:87:24] wire out_rimask_405 = \|_out_rimask_T_405; // @[RegisterRouter.scala:87:24] wire out_wimask_405 = &_out_wimask_T_405; // @[RegisterRouter.scala:87:24] wire out_romask_405 = \|_out_romask_T_405; // @[RegisterRouter.scala:87:24] wire out_womask_405 = &_out_womask_T_405; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_405 = out_rivalid_1_259 & out_rimask_405; // @[RegisterRouter.scala:87:24] wire _out_T_4290 = out_f_rivalid_405; // @[RegisterRouter.scala:87:24] wire out_f_roready_405 = out_roready_1_259 & out_romask_405; // @[RegisterRouter.scala:87:24] wire _out_T_4291 = out_f_roready_405; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_405 = out_wivalid_1_259 & out_wimask_405; // @[RegisterRouter.scala:87:24] wire out_f_woready_405 = out_woready_1_259 & out_womask_405; // @[RegisterRouter.scala:87:24] wire _out_T_4292 = ~out_rimask_405; // @[RegisterRouter.scala:87:24] wire _out_T_4293 = ~out_wimask_405; // @[RegisterRouter.scala:87:24] wire _out_T_4294 = ~out_romask_405; // @[RegisterRouter.scala:87:24] wire _out_T_4295 = ~out_womask_405; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_338 = {hi_924, flags_0_go, _out_prepend_T_338}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4296 = out_prepend_338; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4297 = _out_T_4296; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_339 = _out_T_4297; // @[RegisterRouter.scala:87:24] wire out_rimask_406 = \|_out_rimask_T_406; // @[RegisterRouter.scala:87:24] wire out_wimask_406 = &_out_wimask_T_406; // @[RegisterRouter.scala:87:24] wire out_romask_406 = \|_out_romask_T_406; // @[RegisterRouter.scala:87:24] wire out_womask_406 = &_out_womask_T_406; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_406 = out_rivalid_1_260 & out_rimask_406; // @[RegisterRouter.scala:87:24] wire _out_T_4299 = out_f_rivalid_406; // @[RegisterRouter.scala:87:24] wire out_f_roready_406 = out_roready_1_260 & out_romask_406; // @[RegisterRouter.scala:87:24] wire _out_T_4300 = out_f_roready_406; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_406 = out_wivalid_1_260 & out_wimask_406; // @[RegisterRouter.scala:87:24] wire out_f_woready_406 = out_woready_1_260 & out_womask_406; // @[RegisterRouter.scala:87:24] wire _out_T_4301 = ~out_rimask_406; // @[RegisterRouter.scala:87:24] wire _out_T_4302 = ~out_wimask_406; // @[RegisterRouter.scala:87:24] wire _out_T_4303 = ~out_romask_406; // @[RegisterRouter.scala:87:24] wire _out_T_4304 = ~out_womask_406; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_339 = {hi_925, flags_0_go, _out_prepend_T_339}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4305 = out_prepend_339; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4306 = _out_T_4305; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_340 = _out_T_4306; // @[RegisterRouter.scala:87:24] wire out_rimask_407 = \|_out_rimask_T_407; // @[RegisterRouter.scala:87:24] wire out_wimask_407 = &_out_wimask_T_407; // @[RegisterRouter.scala:87:24] wire out_romask_407 = \|_out_romask_T_407; // @[RegisterRouter.scala:87:24] wire out_womask_407 = &_out_womask_T_407; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_407 = out_rivalid_1_261 & out_rimask_407; // @[RegisterRouter.scala:87:24] wire _out_T_4308 = out_f_rivalid_407; // @[RegisterRouter.scala:87:24] wire out_f_roready_407 = out_roready_1_261 & out_romask_407; // @[RegisterRouter.scala:87:24] wire _out_T_4309 = out_f_roready_407; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_407 = out_wivalid_1_261 & out_wimask_407; // @[RegisterRouter.scala:87:24] wire out_f_woready_407 = out_woready_1_261 & out_womask_407; // @[RegisterRouter.scala:87:24] wire _out_T_4310 = ~out_rimask_407; // @[RegisterRouter.scala:87:24] wire _out_T_4311 = ~out_wimask_407; // @[RegisterRouter.scala:87:24] wire _out_T_4312 = ~out_romask_407; // @[RegisterRouter.scala:87:24] wire _out_T_4313 = ~out_womask_407; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_340 = {hi_926, flags_0_go, _out_prepend_T_340}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4314 = out_prepend_340; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4315 = _out_T_4314; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_341 = _out_T_4315; // @[RegisterRouter.scala:87:24] wire out_rimask_408 = \|_out_rimask_T_408; // @[RegisterRouter.scala:87:24] wire out_wimask_408 = &_out_wimask_T_408; // @[RegisterRouter.scala:87:24] wire out_romask_408 = \|_out_romask_T_408; // @[RegisterRouter.scala:87:24] wire out_womask_408 = &_out_womask_T_408; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_408 = out_rivalid_1_262 & out_rimask_408; // @[RegisterRouter.scala:87:24] wire _out_T_4317 = out_f_rivalid_408; // @[RegisterRouter.scala:87:24] wire out_f_roready_408 = out_roready_1_262 & out_romask_408; // @[RegisterRouter.scala:87:24] wire _out_T_4318 = out_f_roready_408; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_408 = out_wivalid_1_262 & out_wimask_408; // @[RegisterRouter.scala:87:24] wire out_f_woready_408 = out_woready_1_262 & out_womask_408; // @[RegisterRouter.scala:87:24] wire _out_T_4319 = ~out_rimask_408; // @[RegisterRouter.scala:87:24] wire _out_T_4320 = ~out_wimask_408; // @[RegisterRouter.scala:87:24] wire _out_T_4321 = ~out_romask_408; // @[RegisterRouter.scala:87:24] wire _out_T_4322 = ~out_womask_408; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_341 = {hi_927, flags_0_go, _out_prepend_T_341}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4323 = out_prepend_341; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4324 = _out_T_4323; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_342 = _out_T_4324; // @[RegisterRouter.scala:87:24] wire out_rimask_409 = \|_out_rimask_T_409; // @[RegisterRouter.scala:87:24] wire out_wimask_409 = &_out_wimask_T_409; // @[RegisterRouter.scala:87:24] wire out_romask_409 = \|_out_romask_T_409; // @[RegisterRouter.scala:87:24] wire out_womask_409 = &_out_womask_T_409; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_409 = out_rivalid_1_263 & out_rimask_409; // @[RegisterRouter.scala:87:24] wire _out_T_4326 = out_f_rivalid_409; // @[RegisterRouter.scala:87:24] wire out_f_roready_409 = out_roready_1_263 & out_romask_409; // @[RegisterRouter.scala:87:24] wire _out_T_4327 = out_f_roready_409; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_409 = out_wivalid_1_263 & out_wimask_409; // @[RegisterRouter.scala:87:24] wire out_f_woready_409 = out_woready_1_263 & out_womask_409; // @[RegisterRouter.scala:87:24] wire _out_T_4328 = ~out_rimask_409; // @[RegisterRouter.scala:87:24] wire _out_T_4329 = ~out_wimask_409; // @[RegisterRouter.scala:87:24] wire _out_T_4330 = ~out_romask_409; // @[RegisterRouter.scala:87:24] wire _out_T_4331 = ~out_womask_409; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_342 = {hi_928, flags_0_go, _out_prepend_T_342}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4332 = out_prepend_342; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4333 = _out_T_4332; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_243 = _out_T_4333; // @[MuxLiteral.scala:49:48] wire out_rimask_410 = \|_out_rimask_T_410; // @[RegisterRouter.scala:87:24] wire out_wimask_410 = &_out_wimask_T_410; // @[RegisterRouter.scala:87:24] wire out_romask_410 = \|_out_romask_T_410; // @[RegisterRouter.scala:87:24] wire out_womask_410 = &_out_womask_T_410; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_410 = out_rivalid_1_264 & out_rimask_410; // @[RegisterRouter.scala:87:24] wire _out_T_4335 = out_f_rivalid_410; // @[RegisterRouter.scala:87:24] wire out_f_roready_410 = out_roready_1_264 & out_romask_410; // @[RegisterRouter.scala:87:24] wire _out_T_4336 = out_f_roready_410; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_410 = out_wivalid_1_264 & out_wimask_410; // @[RegisterRouter.scala:87:24] wire out_f_woready_410 = out_woready_1_264 & out_womask_410; // @[RegisterRouter.scala:87:24] wire _out_T_4337 = ~out_rimask_410; // @[RegisterRouter.scala:87:24] wire _out_T_4338 = ~out_wimask_410; // @[RegisterRouter.scala:87:24] wire _out_T_4339 = ~out_romask_410; // @[RegisterRouter.scala:87:24] wire _out_T_4340 = ~out_womask_410; // @[RegisterRouter.scala:87:24] wire out_rimask_411 = \|_out_rimask_T_411; // @[RegisterRouter.scala:87:24] wire out_wimask_411 = &_out_wimask_T_411; // @[RegisterRouter.scala:87:24] wire out_romask_411 = \|_out_romask_T_411; // @[RegisterRouter.scala:87:24] wire out_womask_411 = &_out_womask_T_411; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_411 = out_rivalid_1_265 & out_rimask_411; // @[RegisterRouter.scala:87:24] wire _out_T_4344 = out_f_rivalid_411; // @[RegisterRouter.scala:87:24] wire out_f_roready_411 = out_roready_1_265 & out_romask_411; // @[RegisterRouter.scala:87:24] wire _out_T_4345 = out_f_roready_411; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_411 = out_wivalid_1_265 & out_wimask_411; // @[RegisterRouter.scala:87:24] wire out_f_woready_411 = out_woready_1_265 & out_womask_411; // @[RegisterRouter.scala:87:24] wire _out_T_4346 = ~out_rimask_411; // @[RegisterRouter.scala:87:24] wire _out_T_4347 = ~out_wimask_411; // @[RegisterRouter.scala:87:24] wire _out_T_4348 = ~out_romask_411; // @[RegisterRouter.scala:87:24] wire _out_T_4349 = ~out_womask_411; // @[RegisterRouter.scala:87:24] wire out_rimask_412 = \|_out_rimask_T_412; // @[RegisterRouter.scala:87:24] wire out_wimask_412 = &_out_wimask_T_412; // @[RegisterRouter.scala:87:24] wire out_romask_412 = \|_out_romask_T_412; // @[RegisterRouter.scala:87:24] wire out_womask_412 = &_out_womask_T_412; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_412 = out_rivalid_1_266 & out_rimask_412; // @[RegisterRouter.scala:87:24] wire _out_T_4353 = out_f_rivalid_412; // @[RegisterRouter.scala:87:24] wire out_f_roready_412 = out_roready_1_266 & out_romask_412; // @[RegisterRouter.scala:87:24] wire _out_T_4354 = out_f_roready_412; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_412 = out_wivalid_1_266 & out_wimask_412; // @[RegisterRouter.scala:87:24] wire out_f_woready_412 = out_woready_1_266 & out_womask_412; // @[RegisterRouter.scala:87:24] wire _out_T_4355 = ~out_rimask_412; // @[RegisterRouter.scala:87:24] wire _out_T_4356 = ~out_wimask_412; // @[RegisterRouter.scala:87:24] wire _out_T_4357 = ~out_romask_412; // @[RegisterRouter.scala:87:24] wire _out_T_4358 = ~out_womask_412; // @[RegisterRouter.scala:87:24] wire out_rimask_413 = \|_out_rimask_T_413; // @[RegisterRouter.scala:87:24] wire out_wimask_413 = &_out_wimask_T_413; // @[RegisterRouter.scala:87:24] wire out_romask_413 = \|_out_romask_T_413; // @[RegisterRouter.scala:87:24] wire out_womask_413 = &_out_womask_T_413; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_413 = out_rivalid_1_267 & out_rimask_413; // @[RegisterRouter.scala:87:24] wire _out_T_4362 = out_f_rivalid_413; // @[RegisterRouter.scala:87:24] wire out_f_roready_413 = out_roready_1_267 & out_romask_413; // @[RegisterRouter.scala:87:24] wire _out_T_4363 = out_f_roready_413; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_413 = out_wivalid_1_267 & out_wimask_413; // @[RegisterRouter.scala:87:24] wire out_f_woready_413 = out_woready_1_267 & out_womask_413; // @[RegisterRouter.scala:87:24] wire _out_T_4364 = ~out_rimask_413; // @[RegisterRouter.scala:87:24] wire _out_T_4365 = ~out_wimask_413; // @[RegisterRouter.scala:87:24] wire _out_T_4366 = ~out_romask_413; // @[RegisterRouter.scala:87:24] wire _out_T_4367 = ~out_womask_413; // @[RegisterRouter.scala:87:24] wire out_rimask_414 = \|_out_rimask_T_414; // @[RegisterRouter.scala:87:24] wire out_wimask_414 = &_out_wimask_T_414; // @[RegisterRouter.scala:87:24] wire out_romask_414 = \|_out_romask_T_414; // @[RegisterRouter.scala:87:24] wire out_womask_414 = &_out_womask_T_414; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_414 = out_rivalid_1_268 & out_rimask_414; // @[RegisterRouter.scala:87:24] wire _out_T_4371 = out_f_rivalid_414; // @[RegisterRouter.scala:87:24] wire out_f_roready_414 = out_roready_1_268 & out_romask_414; // @[RegisterRouter.scala:87:24] wire _out_T_4372 = out_f_roready_414; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_414 = out_wivalid_1_268 & out_wimask_414; // @[RegisterRouter.scala:87:24] wire out_f_woready_414 = out_woready_1_268 & out_womask_414; // @[RegisterRouter.scala:87:24] wire _out_T_4373 = ~out_rimask_414; // @[RegisterRouter.scala:87:24] wire _out_T_4374 = ~out_wimask_414; // @[RegisterRouter.scala:87:24] wire _out_T_4375 = ~out_romask_414; // @[RegisterRouter.scala:87:24] wire _out_T_4376 = ~out_womask_414; // @[RegisterRouter.scala:87:24] wire out_rimask_415 = \|_out_rimask_T_415; // @[RegisterRouter.scala:87:24] wire out_wimask_415 = &_out_wimask_T_415; // @[RegisterRouter.scala:87:24] wire out_romask_415 = \|_out_romask_T_415; // @[RegisterRouter.scala:87:24] wire out_womask_415 = &_out_womask_T_415; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_415 = out_rivalid_1_269 & out_rimask_415; // @[RegisterRouter.scala:87:24] wire _out_T_4380 = out_f_rivalid_415; // @[RegisterRouter.scala:87:24] wire out_f_roready_415 = out_roready_1_269 & out_romask_415; // @[RegisterRouter.scala:87:24] wire _out_T_4381 = out_f_roready_415; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_415 = out_wivalid_1_269 & out_wimask_415; // @[RegisterRouter.scala:87:24] wire out_f_woready_415 = out_woready_1_269 & out_womask_415; // @[RegisterRouter.scala:87:24] wire _out_T_4382 = ~out_rimask_415; // @[RegisterRouter.scala:87:24] wire _out_T_4383 = ~out_wimask_415; // @[RegisterRouter.scala:87:24] wire _out_T_4384 = ~out_romask_415; // @[RegisterRouter.scala:87:24] wire _out_T_4385 = ~out_womask_415; // @[RegisterRouter.scala:87:24] wire out_rimask_416 = \|_out_rimask_T_416; // @[RegisterRouter.scala:87:24] wire out_wimask_416 = &_out_wimask_T_416; // @[RegisterRouter.scala:87:24] wire out_romask_416 = \|_out_romask_T_416; // @[RegisterRouter.scala:87:24] wire out_womask_416 = &_out_womask_T_416; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_416 = out_rivalid_1_270 & out_rimask_416; // @[RegisterRouter.scala:87:24] wire _out_T_4389 = out_f_rivalid_416; // @[RegisterRouter.scala:87:24] wire out_f_roready_416 = out_roready_1_270 & out_romask_416; // @[RegisterRouter.scala:87:24] wire _out_T_4390 = out_f_roready_416; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_416 = out_wivalid_1_270 & out_wimask_416; // @[RegisterRouter.scala:87:24] wire out_f_woready_416 = out_woready_1_270 & out_womask_416; // @[RegisterRouter.scala:87:24] wire _out_T_4391 = ~out_rimask_416; // @[RegisterRouter.scala:87:24] wire _out_T_4392 = ~out_wimask_416; // @[RegisterRouter.scala:87:24] wire _out_T_4393 = ~out_romask_416; // @[RegisterRouter.scala:87:24] wire _out_T_4394 = ~out_womask_416; // @[RegisterRouter.scala:87:24] wire out_rimask_417 = \|_out_rimask_T_417; // @[RegisterRouter.scala:87:24] wire out_wimask_417 = &_out_wimask_T_417; // @[RegisterRouter.scala:87:24] wire out_romask_417 = \|_out_romask_T_417; // @[RegisterRouter.scala:87:24] wire out_womask_417 = &_out_womask_T_417; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_417 = out_rivalid_1_271 & out_rimask_417; // @[RegisterRouter.scala:87:24] wire _out_T_4398 = out_f_rivalid_417; // @[RegisterRouter.scala:87:24] wire out_f_roready_417 = out_roready_1_271 & out_romask_417; // @[RegisterRouter.scala:87:24] wire _out_T_4399 = out_f_roready_417; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_417 = out_wivalid_1_271 & out_wimask_417; // @[RegisterRouter.scala:87:24] wire out_f_woready_417 = out_woready_1_271 & out_womask_417; // @[RegisterRouter.scala:87:24] wire _out_T_4400 = ~out_rimask_417; // @[RegisterRouter.scala:87:24] wire _out_T_4401 = ~out_wimask_417; // @[RegisterRouter.scala:87:24] wire _out_T_4402 = ~out_romask_417; // @[RegisterRouter.scala:87:24] wire _out_T_4403 = ~out_womask_417; // @[RegisterRouter.scala:87:24] wire out_rimask_418 = \|_out_rimask_T_418; // @[RegisterRouter.scala:87:24] wire out_wimask_418 = &_out_wimask_T_418; // @[RegisterRouter.scala:87:24] wire out_romask_418 = \|_out_romask_T_418; // @[RegisterRouter.scala:87:24] wire out_womask_418 = &_out_womask_T_418; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_418 = out_rivalid_1_272 & out_rimask_418; // @[RegisterRouter.scala:87:24] wire _out_T_4407 = out_f_rivalid_418; // @[RegisterRouter.scala:87:24] wire out_f_roready_418 = out_roready_1_272 & out_romask_418; // @[RegisterRouter.scala:87:24] wire _out_T_4408 = out_f_roready_418; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_418 = out_wivalid_1_272 & out_wimask_418; // @[RegisterRouter.scala:87:24] wire out_f_woready_418 = out_woready_1_272 & out_womask_418; // @[RegisterRouter.scala:87:24] wire _out_T_4409 = ~out_rimask_418; // @[RegisterRouter.scala:87:24] wire _out_T_4410 = ~out_wimask_418; // @[RegisterRouter.scala:87:24] wire _out_T_4411 = ~out_romask_418; // @[RegisterRouter.scala:87:24] wire _out_T_4412 = ~out_womask_418; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4414 = _out_T_4413; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_350 = _out_T_4414; // @[RegisterRouter.scala:87:24] wire out_rimask_419 = \|_out_rimask_T_419; // @[RegisterRouter.scala:87:24] wire out_wimask_419 = &_out_wimask_T_419; // @[RegisterRouter.scala:87:24] wire out_romask_419 = \|_out_romask_T_419; // @[RegisterRouter.scala:87:24] wire out_womask_419 = &_out_womask_T_419; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_419 = out_rivalid_1_273 & out_rimask_419; // @[RegisterRouter.scala:87:24] wire _out_T_4416 = out_f_rivalid_419; // @[RegisterRouter.scala:87:24] wire out_f_roready_419 = out_roready_1_273 & out_romask_419; // @[RegisterRouter.scala:87:24] wire _out_T_4417 = out_f_roready_419; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_419 = out_wivalid_1_273 & out_wimask_419; // @[RegisterRouter.scala:87:24] wire out_f_woready_419 = out_woready_1_273 & out_womask_419; // @[RegisterRouter.scala:87:24] wire _out_T_4418 = ~out_rimask_419; // @[RegisterRouter.scala:87:24] wire _out_T_4419 = ~out_wimask_419; // @[RegisterRouter.scala:87:24] wire _out_T_4420 = ~out_romask_419; // @[RegisterRouter.scala:87:24] wire _out_T_4421 = ~out_womask_419; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_350 = {hi_626, flags_0_go, _out_prepend_T_350}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4422 = out_prepend_350; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4423 = _out_T_4422; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_351 = _out_T_4423; // @[RegisterRouter.scala:87:24] wire out_rimask_420 = \|_out_rimask_T_420; // @[RegisterRouter.scala:87:24] wire out_wimask_420 = &_out_wimask_T_420; // @[RegisterRouter.scala:87:24] wire out_romask_420 = \|_out_romask_T_420; // @[RegisterRouter.scala:87:24] wire out_womask_420 = &_out_womask_T_420; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_420 = out_rivalid_1_274 & out_rimask_420; // @[RegisterRouter.scala:87:24] wire _out_T_4425 = out_f_rivalid_420; // @[RegisterRouter.scala:87:24] wire out_f_roready_420 = out_roready_1_274 & out_romask_420; // @[RegisterRouter.scala:87:24] wire _out_T_4426 = out_f_roready_420; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_420 = out_wivalid_1_274 & out_wimask_420; // @[RegisterRouter.scala:87:24] wire out_f_woready_420 = out_woready_1_274 & out_womask_420; // @[RegisterRouter.scala:87:24] wire _out_T_4427 = ~out_rimask_420; // @[RegisterRouter.scala:87:24] wire _out_T_4428 = ~out_wimask_420; // @[RegisterRouter.scala:87:24] wire _out_T_4429 = ~out_romask_420; // @[RegisterRouter.scala:87:24] wire _out_T_4430 = ~out_womask_420; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_351 = {hi_627, flags_0_go, _out_prepend_T_351}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4431 = out_prepend_351; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4432 = _out_T_4431; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_352 = _out_T_4432; // @[RegisterRouter.scala:87:24] wire out_rimask_421 = \|_out_rimask_T_421; // @[RegisterRouter.scala:87:24] wire out_wimask_421 = &_out_wimask_T_421; // @[RegisterRouter.scala:87:24] wire out_romask_421 = \|_out_romask_T_421; // @[RegisterRouter.scala:87:24] wire out_womask_421 = &_out_womask_T_421; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_421 = out_rivalid_1_275 & out_rimask_421; // @[RegisterRouter.scala:87:24] wire _out_T_4434 = out_f_rivalid_421; // @[RegisterRouter.scala:87:24] wire out_f_roready_421 = out_roready_1_275 & out_romask_421; // @[RegisterRouter.scala:87:24] wire _out_T_4435 = out_f_roready_421; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_421 = out_wivalid_1_275 & out_wimask_421; // @[RegisterRouter.scala:87:24] wire out_f_woready_421 = out_woready_1_275 & out_womask_421; // @[RegisterRouter.scala:87:24] wire _out_T_4436 = ~out_rimask_421; // @[RegisterRouter.scala:87:24] wire _out_T_4437 = ~out_wimask_421; // @[RegisterRouter.scala:87:24] wire _out_T_4438 = ~out_romask_421; // @[RegisterRouter.scala:87:24] wire _out_T_4439 = ~out_womask_421; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_352 = {hi_628, flags_0_go, _out_prepend_T_352}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4440 = out_prepend_352; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4441 = _out_T_4440; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_353 = _out_T_4441; // @[RegisterRouter.scala:87:24] wire out_rimask_422 = \|_out_rimask_T_422; // @[RegisterRouter.scala:87:24] wire out_wimask_422 = &_out_wimask_T_422; // @[RegisterRouter.scala:87:24] wire out_romask_422 = \|_out_romask_T_422; // @[RegisterRouter.scala:87:24] wire out_womask_422 = &_out_womask_T_422; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_422 = out_rivalid_1_276 & out_rimask_422; // @[RegisterRouter.scala:87:24] wire _out_T_4443 = out_f_rivalid_422; // @[RegisterRouter.scala:87:24] wire out_f_roready_422 = out_roready_1_276 & out_romask_422; // @[RegisterRouter.scala:87:24] wire _out_T_4444 = out_f_roready_422; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_422 = out_wivalid_1_276 & out_wimask_422; // @[RegisterRouter.scala:87:24] wire out_f_woready_422 = out_woready_1_276 & out_womask_422; // @[RegisterRouter.scala:87:24] wire _out_T_4445 = ~out_rimask_422; // @[RegisterRouter.scala:87:24] wire _out_T_4446 = ~out_wimask_422; // @[RegisterRouter.scala:87:24] wire _out_T_4447 = ~out_romask_422; // @[RegisterRouter.scala:87:24] wire _out_T_4448 = ~out_womask_422; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_353 = {hi_629, flags_0_go, _out_prepend_T_353}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4449 = out_prepend_353; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4450 = _out_T_4449; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_354 = _out_T_4450; // @[RegisterRouter.scala:87:24] wire out_rimask_423 = \|_out_rimask_T_423; // @[RegisterRouter.scala:87:24] wire out_wimask_423 = &_out_wimask_T_423; // @[RegisterRouter.scala:87:24] wire out_romask_423 = \|_out_romask_T_423; // @[RegisterRouter.scala:87:24] wire out_womask_423 = &_out_womask_T_423; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_423 = out_rivalid_1_277 & out_rimask_423; // @[RegisterRouter.scala:87:24] wire _out_T_4452 = out_f_rivalid_423; // @[RegisterRouter.scala:87:24] wire out_f_roready_423 = out_roready_1_277 & out_romask_423; // @[RegisterRouter.scala:87:24] wire _out_T_4453 = out_f_roready_423; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_423 = out_wivalid_1_277 & out_wimask_423; // @[RegisterRouter.scala:87:24] wire out_f_woready_423 = out_woready_1_277 & out_womask_423; // @[RegisterRouter.scala:87:24] wire _out_T_4454 = ~out_rimask_423; // @[RegisterRouter.scala:87:24] wire _out_T_4455 = ~out_wimask_423; // @[RegisterRouter.scala:87:24] wire _out_T_4456 = ~out_romask_423; // @[RegisterRouter.scala:87:24] wire _out_T_4457 = ~out_womask_423; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_354 = {hi_630, flags_0_go, _out_prepend_T_354}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4458 = out_prepend_354; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4459 = _out_T_4458; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_355 = _out_T_4459; // @[RegisterRouter.scala:87:24] wire out_rimask_424 = \|_out_rimask_T_424; // @[RegisterRouter.scala:87:24] wire out_wimask_424 = &_out_wimask_T_424; // @[RegisterRouter.scala:87:24] wire out_romask_424 = \|_out_romask_T_424; // @[RegisterRouter.scala:87:24] wire out_womask_424 = &_out_womask_T_424; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_424 = out_rivalid_1_278 & out_rimask_424; // @[RegisterRouter.scala:87:24] wire _out_T_4461 = out_f_rivalid_424; // @[RegisterRouter.scala:87:24] wire out_f_roready_424 = out_roready_1_278 & out_romask_424; // @[RegisterRouter.scala:87:24] wire _out_T_4462 = out_f_roready_424; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_424 = out_wivalid_1_278 & out_wimask_424; // @[RegisterRouter.scala:87:24] wire out_f_woready_424 = out_woready_1_278 & out_womask_424; // @[RegisterRouter.scala:87:24] wire _out_T_4463 = ~out_rimask_424; // @[RegisterRouter.scala:87:24] wire _out_T_4464 = ~out_wimask_424; // @[RegisterRouter.scala:87:24] wire _out_T_4465 = ~out_romask_424; // @[RegisterRouter.scala:87:24] wire _out_T_4466 = ~out_womask_424; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_355 = {hi_631, flags_0_go, _out_prepend_T_355}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4467 = out_prepend_355; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4468 = _out_T_4467; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_356 = _out_T_4468; // @[RegisterRouter.scala:87:24] wire out_rimask_425 = \|_out_rimask_T_425; // @[RegisterRouter.scala:87:24] wire out_wimask_425 = &_out_wimask_T_425; // @[RegisterRouter.scala:87:24] wire out_romask_425 = \|_out_romask_T_425; // @[RegisterRouter.scala:87:24] wire out_womask_425 = &_out_womask_T_425; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_425 = out_rivalid_1_279 & out_rimask_425; // @[RegisterRouter.scala:87:24] wire _out_T_4470 = out_f_rivalid_425; // @[RegisterRouter.scala:87:24] wire out_f_roready_425 = out_roready_1_279 & out_romask_425; // @[RegisterRouter.scala:87:24] wire _out_T_4471 = out_f_roready_425; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_425 = out_wivalid_1_279 & out_wimask_425; // @[RegisterRouter.scala:87:24] wire out_f_woready_425 = out_woready_1_279 & out_womask_425; // @[RegisterRouter.scala:87:24] wire _out_T_4472 = ~out_rimask_425; // @[RegisterRouter.scala:87:24] wire _out_T_4473 = ~out_wimask_425; // @[RegisterRouter.scala:87:24] wire _out_T_4474 = ~out_romask_425; // @[RegisterRouter.scala:87:24] wire _out_T_4475 = ~out_womask_425; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_356 = {hi_632, flags_0_go, _out_prepend_T_356}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4476 = out_prepend_356; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4477 = _out_T_4476; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_206 = _out_T_4477; // @[MuxLiteral.scala:49:48] wire out_rimask_426 = \|_out_rimask_T_426; // @[RegisterRouter.scala:87:24] wire out_wimask_426 = &_out_wimask_T_426; // @[RegisterRouter.scala:87:24] wire out_romask_426 = \|_out_romask_T_426; // @[RegisterRouter.scala:87:24] wire out_womask_426 = &_out_womask_T_426; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_426 = out_rivalid_1_280 & out_rimask_426; // @[RegisterRouter.scala:87:24] wire _out_T_4479 = out_f_rivalid_426; // @[RegisterRouter.scala:87:24] wire out_f_roready_426 = out_roready_1_280 & out_romask_426; // @[RegisterRouter.scala:87:24] wire _out_T_4480 = out_f_roready_426; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_426 = out_wivalid_1_280 & out_wimask_426; // @[RegisterRouter.scala:87:24] wire out_f_woready_426 = out_woready_1_280 & out_womask_426; // @[RegisterRouter.scala:87:24] wire _out_T_4481 = ~out_rimask_426; // @[RegisterRouter.scala:87:24] wire _out_T_4482 = ~out_wimask_426; // @[RegisterRouter.scala:87:24] wire _out_T_4483 = ~out_romask_426; // @[RegisterRouter.scala:87:24] wire _out_T_4484 = ~out_womask_426; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4486 = _out_T_4485; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_357 = _out_T_4486; // @[RegisterRouter.scala:87:24] wire out_rimask_427 = \|_out_rimask_T_427; // @[RegisterRouter.scala:87:24] wire out_wimask_427 = &_out_wimask_T_427; // @[RegisterRouter.scala:87:24] wire out_romask_427 = \|_out_romask_T_427; // @[RegisterRouter.scala:87:24] wire out_womask_427 = &_out_womask_T_427; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_427 = out_rivalid_1_281 & out_rimask_427; // @[RegisterRouter.scala:87:24] wire _out_T_4488 = out_f_rivalid_427; // @[RegisterRouter.scala:87:24] wire out_f_roready_427 = out_roready_1_281 & out_romask_427; // @[RegisterRouter.scala:87:24] wire _out_T_4489 = out_f_roready_427; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_427 = out_wivalid_1_281 & out_wimask_427; // @[RegisterRouter.scala:87:24] wire out_f_woready_427 = out_woready_1_281 & out_womask_427; // @[RegisterRouter.scala:87:24] wire _out_T_4490 = ~out_rimask_427; // @[RegisterRouter.scala:87:24] wire _out_T_4491 = ~out_wimask_427; // @[RegisterRouter.scala:87:24] wire _out_T_4492 = ~out_romask_427; // @[RegisterRouter.scala:87:24] wire _out_T_4493 = ~out_womask_427; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_357 = {hi_842, flags_0_go, _out_prepend_T_357}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4494 = out_prepend_357; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4495 = _out_T_4494; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_358 = _out_T_4495; // @[RegisterRouter.scala:87:24] wire out_rimask_428 = \|_out_rimask_T_428; // @[RegisterRouter.scala:87:24] wire out_wimask_428 = &_out_wimask_T_428; // @[RegisterRouter.scala:87:24] wire out_romask_428 = \|_out_romask_T_428; // @[RegisterRouter.scala:87:24] wire out_womask_428 = &_out_womask_T_428; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_428 = out_rivalid_1_282 & out_rimask_428; // @[RegisterRouter.scala:87:24] wire _out_T_4497 = out_f_rivalid_428; // @[RegisterRouter.scala:87:24] wire out_f_roready_428 = out_roready_1_282 & out_romask_428; // @[RegisterRouter.scala:87:24] wire _out_T_4498 = out_f_roready_428; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_428 = out_wivalid_1_282 & out_wimask_428; // @[RegisterRouter.scala:87:24] wire out_f_woready_428 = out_woready_1_282 & out_womask_428; // @[RegisterRouter.scala:87:24] wire _out_T_4499 = ~out_rimask_428; // @[RegisterRouter.scala:87:24] wire _out_T_4500 = ~out_wimask_428; // @[RegisterRouter.scala:87:24] wire _out_T_4501 = ~out_romask_428; // @[RegisterRouter.scala:87:24] wire _out_T_4502 = ~out_womask_428; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_358 = {hi_843, flags_0_go, _out_prepend_T_358}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4503 = out_prepend_358; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4504 = _out_T_4503; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_359 = _out_T_4504; // @[RegisterRouter.scala:87:24] wire out_rimask_429 = \|_out_rimask_T_429; // @[RegisterRouter.scala:87:24] wire out_wimask_429 = &_out_wimask_T_429; // @[RegisterRouter.scala:87:24] wire out_romask_429 = \|_out_romask_T_429; // @[RegisterRouter.scala:87:24] wire out_womask_429 = &_out_womask_T_429; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_429 = out_rivalid_1_283 & out_rimask_429; // @[RegisterRouter.scala:87:24] wire _out_T_4506 = out_f_rivalid_429; // @[RegisterRouter.scala:87:24] wire out_f_roready_429 = out_roready_1_283 & out_romask_429; // @[RegisterRouter.scala:87:24] wire _out_T_4507 = out_f_roready_429; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_429 = out_wivalid_1_283 & out_wimask_429; // @[RegisterRouter.scala:87:24] wire out_f_woready_429 = out_woready_1_283 & out_womask_429; // @[RegisterRouter.scala:87:24] wire _out_T_4508 = ~out_rimask_429; // @[RegisterRouter.scala:87:24] wire _out_T_4509 = ~out_wimask_429; // @[RegisterRouter.scala:87:24] wire _out_T_4510 = ~out_romask_429; // @[RegisterRouter.scala:87:24] wire _out_T_4511 = ~out_womask_429; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_359 = {hi_844, flags_0_go, _out_prepend_T_359}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4512 = out_prepend_359; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4513 = _out_T_4512; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_360 = _out_T_4513; // @[RegisterRouter.scala:87:24] wire out_rimask_430 = \|_out_rimask_T_430; // @[RegisterRouter.scala:87:24] wire out_wimask_430 = &_out_wimask_T_430; // @[RegisterRouter.scala:87:24] wire out_romask_430 = \|_out_romask_T_430; // @[RegisterRouter.scala:87:24] wire out_womask_430 = &_out_womask_T_430; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_430 = out_rivalid_1_284 & out_rimask_430; // @[RegisterRouter.scala:87:24] wire _out_T_4515 = out_f_rivalid_430; // @[RegisterRouter.scala:87:24] wire out_f_roready_430 = out_roready_1_284 & out_romask_430; // @[RegisterRouter.scala:87:24] wire _out_T_4516 = out_f_roready_430; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_430 = out_wivalid_1_284 & out_wimask_430; // @[RegisterRouter.scala:87:24] wire out_f_woready_430 = out_woready_1_284 & out_womask_430; // @[RegisterRouter.scala:87:24] wire _out_T_4517 = ~out_rimask_430; // @[RegisterRouter.scala:87:24] wire _out_T_4518 = ~out_wimask_430; // @[RegisterRouter.scala:87:24] wire _out_T_4519 = ~out_romask_430; // @[RegisterRouter.scala:87:24] wire _out_T_4520 = ~out_womask_430; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_360 = {hi_845, flags_0_go, _out_prepend_T_360}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4521 = out_prepend_360; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4522 = _out_T_4521; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_361 = _out_T_4522; // @[RegisterRouter.scala:87:24] wire out_rimask_431 = \|_out_rimask_T_431; // @[RegisterRouter.scala:87:24] wire out_wimask_431 = &_out_wimask_T_431; // @[RegisterRouter.scala:87:24] wire out_romask_431 = \|_out_romask_T_431; // @[RegisterRouter.scala:87:24] wire out_womask_431 = &_out_womask_T_431; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_431 = out_rivalid_1_285 & out_rimask_431; // @[RegisterRouter.scala:87:24] wire _out_T_4524 = out_f_rivalid_431; // @[RegisterRouter.scala:87:24] wire out_f_roready_431 = out_roready_1_285 & out_romask_431; // @[RegisterRouter.scala:87:24] wire _out_T_4525 = out_f_roready_431; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_431 = out_wivalid_1_285 & out_wimask_431; // @[RegisterRouter.scala:87:24] wire out_f_woready_431 = out_woready_1_285 & out_womask_431; // @[RegisterRouter.scala:87:24] wire _out_T_4526 = ~out_rimask_431; // @[RegisterRouter.scala:87:24] wire _out_T_4527 = ~out_wimask_431; // @[RegisterRouter.scala:87:24] wire _out_T_4528 = ~out_romask_431; // @[RegisterRouter.scala:87:24] wire _out_T_4529 = ~out_womask_431; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_361 = {hi_846, flags_0_go, _out_prepend_T_361}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4530 = out_prepend_361; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4531 = _out_T_4530; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_362 = _out_T_4531; // @[RegisterRouter.scala:87:24] wire out_rimask_432 = \|_out_rimask_T_432; // @[RegisterRouter.scala:87:24] wire out_wimask_432 = &_out_wimask_T_432; // @[RegisterRouter.scala:87:24] wire out_romask_432 = \|_out_romask_T_432; // @[RegisterRouter.scala:87:24] wire out_womask_432 = &_out_womask_T_432; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_432 = out_rivalid_1_286 & out_rimask_432; // @[RegisterRouter.scala:87:24] wire _out_T_4533 = out_f_rivalid_432; // @[RegisterRouter.scala:87:24] wire out_f_roready_432 = out_roready_1_286 & out_romask_432; // @[RegisterRouter.scala:87:24] wire _out_T_4534 = out_f_roready_432; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_432 = out_wivalid_1_286 & out_wimask_432; // @[RegisterRouter.scala:87:24] wire out_f_woready_432 = out_woready_1_286 & out_womask_432; // @[RegisterRouter.scala:87:24] wire _out_T_4535 = ~out_rimask_432; // @[RegisterRouter.scala:87:24] wire _out_T_4536 = ~out_wimask_432; // @[RegisterRouter.scala:87:24] wire _out_T_4537 = ~out_romask_432; // @[RegisterRouter.scala:87:24] wire _out_T_4538 = ~out_womask_432; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_362 = {hi_847, flags_0_go, _out_prepend_T_362}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4539 = out_prepend_362; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4540 = _out_T_4539; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_363 = _out_T_4540; // @[RegisterRouter.scala:87:24] wire out_rimask_433 = \|_out_rimask_T_433; // @[RegisterRouter.scala:87:24] wire out_wimask_433 = &_out_wimask_T_433; // @[RegisterRouter.scala:87:24] wire out_romask_433 = \|_out_romask_T_433; // @[RegisterRouter.scala:87:24] wire out_womask_433 = &_out_womask_T_433; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_433 = out_rivalid_1_287 & out_rimask_433; // @[RegisterRouter.scala:87:24] wire _out_T_4542 = out_f_rivalid_433; // @[RegisterRouter.scala:87:24] wire out_f_roready_433 = out_roready_1_287 & out_romask_433; // @[RegisterRouter.scala:87:24] wire _out_T_4543 = out_f_roready_433; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_433 = out_wivalid_1_287 & out_wimask_433; // @[RegisterRouter.scala:87:24] wire out_f_woready_433 = out_woready_1_287 & out_womask_433; // @[RegisterRouter.scala:87:24] wire _out_T_4544 = ~out_rimask_433; // @[RegisterRouter.scala:87:24] wire _out_T_4545 = ~out_wimask_433; // @[RegisterRouter.scala:87:24] wire _out_T_4546 = ~out_romask_433; // @[RegisterRouter.scala:87:24] wire _out_T_4547 = ~out_womask_433; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_363 = {hi_848, flags_0_go, _out_prepend_T_363}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4548 = out_prepend_363; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4549 = _out_T_4548; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_233 = _out_T_4549; // @[MuxLiteral.scala:49:48] wire out_rimask_434 = \|_out_rimask_T_434; // @[RegisterRouter.scala:87:24] wire out_wimask_434 = &_out_wimask_T_434; // @[RegisterRouter.scala:87:24] wire out_romask_434 = \|_out_romask_T_434; // @[RegisterRouter.scala:87:24] wire out_womask_434 = &_out_womask_T_434; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_434 = out_rivalid_1_288 & out_rimask_434; // @[RegisterRouter.scala:87:24] wire _out_T_4551 = out_f_rivalid_434; // @[RegisterRouter.scala:87:24] wire out_f_roready_434 = out_roready_1_288 & out_romask_434; // @[RegisterRouter.scala:87:24] wire _out_T_4552 = out_f_roready_434; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_434 = out_wivalid_1_288 & out_wimask_434; // @[RegisterRouter.scala:87:24] wire out_f_woready_434 = out_woready_1_288 & out_womask_434; // @[RegisterRouter.scala:87:24] wire _out_T_4553 = ~out_rimask_434; // @[RegisterRouter.scala:87:24] wire _out_T_4554 = ~out_wimask_434; // @[RegisterRouter.scala:87:24] wire _out_T_4555 = ~out_romask_434; // @[RegisterRouter.scala:87:24] wire _out_T_4556 = ~out_womask_434; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4558 = _out_T_4557; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_364 = _out_T_4558; // @[RegisterRouter.scala:87:24] wire out_rimask_435 = \|_out_rimask_T_435; // @[RegisterRouter.scala:87:24] wire out_wimask_435 = &_out_wimask_T_435; // @[RegisterRouter.scala:87:24] wire out_romask_435 = \|_out_romask_T_435; // @[RegisterRouter.scala:87:24] wire out_womask_435 = &_out_womask_T_435; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_435 = out_rivalid_1_289 & out_rimask_435; // @[RegisterRouter.scala:87:24] wire _out_T_4560 = out_f_rivalid_435; // @[RegisterRouter.scala:87:24] wire out_f_roready_435 = out_roready_1_289 & out_romask_435; // @[RegisterRouter.scala:87:24] wire _out_T_4561 = out_f_roready_435; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_435 = out_wivalid_1_289 & out_wimask_435; // @[RegisterRouter.scala:87:24] wire out_f_woready_435 = out_woready_1_289 & out_womask_435; // @[RegisterRouter.scala:87:24] wire _out_T_4562 = ~out_rimask_435; // @[RegisterRouter.scala:87:24] wire _out_T_4563 = ~out_wimask_435; // @[RegisterRouter.scala:87:24] wire _out_T_4564 = ~out_romask_435; // @[RegisterRouter.scala:87:24] wire _out_T_4565 = ~out_womask_435; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_364 = {hi_962, flags_0_go, _out_prepend_T_364}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4566 = out_prepend_364; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4567 = _out_T_4566; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_365 = _out_T_4567; // @[RegisterRouter.scala:87:24] wire out_rimask_436 = \|_out_rimask_T_436; // @[RegisterRouter.scala:87:24] wire out_wimask_436 = &_out_wimask_T_436; // @[RegisterRouter.scala:87:24] wire out_romask_436 = \|_out_romask_T_436; // @[RegisterRouter.scala:87:24] wire out_womask_436 = &_out_womask_T_436; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_436 = out_rivalid_1_290 & out_rimask_436; // @[RegisterRouter.scala:87:24] wire _out_T_4569 = out_f_rivalid_436; // @[RegisterRouter.scala:87:24] wire out_f_roready_436 = out_roready_1_290 & out_romask_436; // @[RegisterRouter.scala:87:24] wire _out_T_4570 = out_f_roready_436; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_436 = out_wivalid_1_290 & out_wimask_436; // @[RegisterRouter.scala:87:24] wire out_f_woready_436 = out_woready_1_290 & out_womask_436; // @[RegisterRouter.scala:87:24] wire _out_T_4571 = ~out_rimask_436; // @[RegisterRouter.scala:87:24] wire _out_T_4572 = ~out_wimask_436; // @[RegisterRouter.scala:87:24] wire _out_T_4573 = ~out_romask_436; // @[RegisterRouter.scala:87:24] wire _out_T_4574 = ~out_womask_436; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_365 = {hi_963, flags_0_go, _out_prepend_T_365}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4575 = out_prepend_365; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4576 = _out_T_4575; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_366 = _out_T_4576; // @[RegisterRouter.scala:87:24] wire out_rimask_437 = \|_out_rimask_T_437; // @[RegisterRouter.scala:87:24] wire out_wimask_437 = &_out_wimask_T_437; // @[RegisterRouter.scala:87:24] wire out_romask_437 = \|_out_romask_T_437; // @[RegisterRouter.scala:87:24] wire out_womask_437 = &_out_womask_T_437; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_437 = out_rivalid_1_291 & out_rimask_437; // @[RegisterRouter.scala:87:24] wire _out_T_4578 = out_f_rivalid_437; // @[RegisterRouter.scala:87:24] wire out_f_roready_437 = out_roready_1_291 & out_romask_437; // @[RegisterRouter.scala:87:24] wire _out_T_4579 = out_f_roready_437; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_437 = out_wivalid_1_291 & out_wimask_437; // @[RegisterRouter.scala:87:24] wire out_f_woready_437 = out_woready_1_291 & out_womask_437; // @[RegisterRouter.scala:87:24] wire _out_T_4580 = ~out_rimask_437; // @[RegisterRouter.scala:87:24] wire _out_T_4581 = ~out_wimask_437; // @[RegisterRouter.scala:87:24] wire _out_T_4582 = ~out_romask_437; // @[RegisterRouter.scala:87:24] wire _out_T_4583 = ~out_womask_437; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_366 = {hi_964, flags_0_go, _out_prepend_T_366}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4584 = out_prepend_366; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4585 = _out_T_4584; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_367 = _out_T_4585; // @[RegisterRouter.scala:87:24] wire out_rimask_438 = \|_out_rimask_T_438; // @[RegisterRouter.scala:87:24] wire out_wimask_438 = &_out_wimask_T_438; // @[RegisterRouter.scala:87:24] wire out_romask_438 = \|_out_romask_T_438; // @[RegisterRouter.scala:87:24] wire out_womask_438 = &_out_womask_T_438; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_438 = out_rivalid_1_292 & out_rimask_438; // @[RegisterRouter.scala:87:24] wire _out_T_4587 = out_f_rivalid_438; // @[RegisterRouter.scala:87:24] wire out_f_roready_438 = out_roready_1_292 & out_romask_438; // @[RegisterRouter.scala:87:24] wire _out_T_4588 = out_f_roready_438; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_438 = out_wivalid_1_292 & out_wimask_438; // @[RegisterRouter.scala:87:24] wire out_f_woready_438 = out_woready_1_292 & out_womask_438; // @[RegisterRouter.scala:87:24] wire _out_T_4589 = ~out_rimask_438; // @[RegisterRouter.scala:87:24] wire _out_T_4590 = ~out_wimask_438; // @[RegisterRouter.scala:87:24] wire _out_T_4591 = ~out_romask_438; // @[RegisterRouter.scala:87:24] wire _out_T_4592 = ~out_womask_438; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_367 = {hi_965, flags_0_go, _out_prepend_T_367}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4593 = out_prepend_367; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4594 = _out_T_4593; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_368 = _out_T_4594; // @[RegisterRouter.scala:87:24] wire out_rimask_439 = \|_out_rimask_T_439; // @[RegisterRouter.scala:87:24] wire out_wimask_439 = &_out_wimask_T_439; // @[RegisterRouter.scala:87:24] wire out_romask_439 = \|_out_romask_T_439; // @[RegisterRouter.scala:87:24] wire out_womask_439 = &_out_womask_T_439; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_439 = out_rivalid_1_293 & out_rimask_439; // @[RegisterRouter.scala:87:24] wire _out_T_4596 = out_f_rivalid_439; // @[RegisterRouter.scala:87:24] wire out_f_roready_439 = out_roready_1_293 & out_romask_439; // @[RegisterRouter.scala:87:24] wire _out_T_4597 = out_f_roready_439; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_439 = out_wivalid_1_293 & out_wimask_439; // @[RegisterRouter.scala:87:24] wire out_f_woready_439 = out_woready_1_293 & out_womask_439; // @[RegisterRouter.scala:87:24] wire _out_T_4598 = ~out_rimask_439; // @[RegisterRouter.scala:87:24] wire _out_T_4599 = ~out_wimask_439; // @[RegisterRouter.scala:87:24] wire _out_T_4600 = ~out_romask_439; // @[RegisterRouter.scala:87:24] wire _out_T_4601 = ~out_womask_439; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_368 = {hi_966, flags_0_go, _out_prepend_T_368}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4602 = out_prepend_368; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4603 = _out_T_4602; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_369 = _out_T_4603; // @[RegisterRouter.scala:87:24] wire out_rimask_440 = \|_out_rimask_T_440; // @[RegisterRouter.scala:87:24] wire out_wimask_440 = &_out_wimask_T_440; // @[RegisterRouter.scala:87:24] wire out_romask_440 = \|_out_romask_T_440; // @[RegisterRouter.scala:87:24] wire out_womask_440 = &_out_womask_T_440; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_440 = out_rivalid_1_294 & out_rimask_440; // @[RegisterRouter.scala:87:24] wire _out_T_4605 = out_f_rivalid_440; // @[RegisterRouter.scala:87:24] wire out_f_roready_440 = out_roready_1_294 & out_romask_440; // @[RegisterRouter.scala:87:24] wire _out_T_4606 = out_f_roready_440; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_440 = out_wivalid_1_294 & out_wimask_440; // @[RegisterRouter.scala:87:24] wire out_f_woready_440 = out_woready_1_294 & out_womask_440; // @[RegisterRouter.scala:87:24] wire _out_T_4607 = ~out_rimask_440; // @[RegisterRouter.scala:87:24] wire _out_T_4608 = ~out_wimask_440; // @[RegisterRouter.scala:87:24] wire _out_T_4609 = ~out_romask_440; // @[RegisterRouter.scala:87:24] wire _out_T_4610 = ~out_womask_440; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_369 = {hi_967, flags_0_go, _out_prepend_T_369}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4611 = out_prepend_369; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4612 = _out_T_4611; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_370 = _out_T_4612; // @[RegisterRouter.scala:87:24] wire out_rimask_441 = \|_out_rimask_T_441; // @[RegisterRouter.scala:87:24] wire out_wimask_441 = &_out_wimask_T_441; // @[RegisterRouter.scala:87:24] wire out_romask_441 = \|_out_romask_T_441; // @[RegisterRouter.scala:87:24] wire out_womask_441 = &_out_womask_T_441; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_441 = out_rivalid_1_295 & out_rimask_441; // @[RegisterRouter.scala:87:24] wire _out_T_4614 = out_f_rivalid_441; // @[RegisterRouter.scala:87:24] wire out_f_roready_441 = out_roready_1_295 & out_romask_441; // @[RegisterRouter.scala:87:24] wire _out_T_4615 = out_f_roready_441; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_441 = out_wivalid_1_295 & out_wimask_441; // @[RegisterRouter.scala:87:24] wire out_f_woready_441 = out_woready_1_295 & out_womask_441; // @[RegisterRouter.scala:87:24] wire _out_T_4616 = ~out_rimask_441; // @[RegisterRouter.scala:87:24] wire _out_T_4617 = ~out_wimask_441; // @[RegisterRouter.scala:87:24] wire _out_T_4618 = ~out_romask_441; // @[RegisterRouter.scala:87:24] wire _out_T_4619 = ~out_womask_441; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_370 = {hi_968, flags_0_go, _out_prepend_T_370}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4620 = out_prepend_370; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4621 = _out_T_4620; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_248 = _out_T_4621; // @[MuxLiteral.scala:49:48] wire out_rimask_442 = \|_out_rimask_T_442; // @[RegisterRouter.scala:87:24] wire out_wimask_442 = &_out_wimask_T_442; // @[RegisterRouter.scala:87:24] wire out_romask_442 = \|_out_romask_T_442; // @[RegisterRouter.scala:87:24] wire out_womask_442 = &_out_womask_T_442; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_442 = out_rivalid_1_296 & out_rimask_442; // @[RegisterRouter.scala:87:24] wire _out_T_4623 = out_f_rivalid_442; // @[RegisterRouter.scala:87:24] wire out_f_roready_442 = out_roready_1_296 & out_romask_442; // @[RegisterRouter.scala:87:24] wire _out_T_4624 = out_f_roready_442; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_442 = out_wivalid_1_296 & out_wimask_442; // @[RegisterRouter.scala:87:24] wire out_f_woready_442 = out_woready_1_296 & out_womask_442; // @[RegisterRouter.scala:87:24] wire _out_T_4625 = ~out_rimask_442; // @[RegisterRouter.scala:87:24] wire _out_T_4626 = ~out_wimask_442; // @[RegisterRouter.scala:87:24] wire _out_T_4627 = ~out_romask_442; // @[RegisterRouter.scala:87:24] wire _out_T_4628 = ~out_womask_442; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4630 = _out_T_4629; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_371 = _out_T_4630; // @[RegisterRouter.scala:87:24] wire out_rimask_443 = \|_out_rimask_T_443; // @[RegisterRouter.scala:87:24] wire out_wimask_443 = &_out_wimask_T_443; // @[RegisterRouter.scala:87:24] wire out_romask_443 = \|_out_romask_T_443; // @[RegisterRouter.scala:87:24] wire out_womask_443 = &_out_womask_T_443; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_443 = out_rivalid_1_297 & out_rimask_443; // @[RegisterRouter.scala:87:24] wire _out_T_4632 = out_f_rivalid_443; // @[RegisterRouter.scala:87:24] wire out_f_roready_443 = out_roready_1_297 & out_romask_443; // @[RegisterRouter.scala:87:24] wire _out_T_4633 = out_f_roready_443; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_443 = out_wivalid_1_297 & out_wimask_443; // @[RegisterRouter.scala:87:24] wire out_f_woready_443 = out_woready_1_297 & out_womask_443; // @[RegisterRouter.scala:87:24] wire _out_T_4634 = ~out_rimask_443; // @[RegisterRouter.scala:87:24] wire _out_T_4635 = ~out_wimask_443; // @[RegisterRouter.scala:87:24] wire _out_T_4636 = ~out_romask_443; // @[RegisterRouter.scala:87:24] wire _out_T_4637 = ~out_womask_443; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_371 = {hi_586, flags_0_go, _out_prepend_T_371}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4638 = out_prepend_371; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4639 = _out_T_4638; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_372 = _out_T_4639; // @[RegisterRouter.scala:87:24] wire out_rimask_444 = \|_out_rimask_T_444; // @[RegisterRouter.scala:87:24] wire out_wimask_444 = &_out_wimask_T_444; // @[RegisterRouter.scala:87:24] wire out_romask_444 = \|_out_romask_T_444; // @[RegisterRouter.scala:87:24] wire out_womask_444 = &_out_womask_T_444; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_444 = out_rivalid_1_298 & out_rimask_444; // @[RegisterRouter.scala:87:24] wire _out_T_4641 = out_f_rivalid_444; // @[RegisterRouter.scala:87:24] wire out_f_roready_444 = out_roready_1_298 & out_romask_444; // @[RegisterRouter.scala:87:24] wire _out_T_4642 = out_f_roready_444; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_444 = out_wivalid_1_298 & out_wimask_444; // @[RegisterRouter.scala:87:24] wire out_f_woready_444 = out_woready_1_298 & out_womask_444; // @[RegisterRouter.scala:87:24] wire _out_T_4643 = ~out_rimask_444; // @[RegisterRouter.scala:87:24] wire _out_T_4644 = ~out_wimask_444; // @[RegisterRouter.scala:87:24] wire _out_T_4645 = ~out_romask_444; // @[RegisterRouter.scala:87:24] wire _out_T_4646 = ~out_womask_444; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_372 = {hi_587, flags_0_go, _out_prepend_T_372}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4647 = out_prepend_372; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4648 = _out_T_4647; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_373 = _out_T_4648; // @[RegisterRouter.scala:87:24] wire out_rimask_445 = \|_out_rimask_T_445; // @[RegisterRouter.scala:87:24] wire out_wimask_445 = &_out_wimask_T_445; // @[RegisterRouter.scala:87:24] wire out_romask_445 = \|_out_romask_T_445; // @[RegisterRouter.scala:87:24] wire out_womask_445 = &_out_womask_T_445; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_445 = out_rivalid_1_299 & out_rimask_445; // @[RegisterRouter.scala:87:24] wire _out_T_4650 = out_f_rivalid_445; // @[RegisterRouter.scala:87:24] wire out_f_roready_445 = out_roready_1_299 & out_romask_445; // @[RegisterRouter.scala:87:24] wire _out_T_4651 = out_f_roready_445; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_445 = out_wivalid_1_299 & out_wimask_445; // @[RegisterRouter.scala:87:24] wire out_f_woready_445 = out_woready_1_299 & out_womask_445; // @[RegisterRouter.scala:87:24] wire _out_T_4652 = ~out_rimask_445; // @[RegisterRouter.scala:87:24] wire _out_T_4653 = ~out_wimask_445; // @[RegisterRouter.scala:87:24] wire _out_T_4654 = ~out_romask_445; // @[RegisterRouter.scala:87:24] wire _out_T_4655 = ~out_womask_445; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_373 = {hi_588, flags_0_go, _out_prepend_T_373}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4656 = out_prepend_373; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4657 = _out_T_4656; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_374 = _out_T_4657; // @[RegisterRouter.scala:87:24] wire out_rimask_446 = \|_out_rimask_T_446; // @[RegisterRouter.scala:87:24] wire out_wimask_446 = &_out_wimask_T_446; // @[RegisterRouter.scala:87:24] wire out_romask_446 = \|_out_romask_T_446; // @[RegisterRouter.scala:87:24] wire out_womask_446 = &_out_womask_T_446; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_446 = out_rivalid_1_300 & out_rimask_446; // @[RegisterRouter.scala:87:24] wire _out_T_4659 = out_f_rivalid_446; // @[RegisterRouter.scala:87:24] wire out_f_roready_446 = out_roready_1_300 & out_romask_446; // @[RegisterRouter.scala:87:24] wire _out_T_4660 = out_f_roready_446; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_446 = out_wivalid_1_300 & out_wimask_446; // @[RegisterRouter.scala:87:24] wire out_f_woready_446 = out_woready_1_300 & out_womask_446; // @[RegisterRouter.scala:87:24] wire _out_T_4661 = ~out_rimask_446; // @[RegisterRouter.scala:87:24] wire _out_T_4662 = ~out_wimask_446; // @[RegisterRouter.scala:87:24] wire _out_T_4663 = ~out_romask_446; // @[RegisterRouter.scala:87:24] wire _out_T_4664 = ~out_womask_446; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_374 = {hi_589, flags_0_go, _out_prepend_T_374}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4665 = out_prepend_374; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4666 = _out_T_4665; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_375 = _out_T_4666; // @[RegisterRouter.scala:87:24] wire out_rimask_447 = \|_out_rimask_T_447; // @[RegisterRouter.scala:87:24] wire out_wimask_447 = &_out_wimask_T_447; // @[RegisterRouter.scala:87:24] wire out_romask_447 = \|_out_romask_T_447; // @[RegisterRouter.scala:87:24] wire out_womask_447 = &_out_womask_T_447; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_447 = out_rivalid_1_301 & out_rimask_447; // @[RegisterRouter.scala:87:24] wire _out_T_4668 = out_f_rivalid_447; // @[RegisterRouter.scala:87:24] wire out_f_roready_447 = out_roready_1_301 & out_romask_447; // @[RegisterRouter.scala:87:24] wire _out_T_4669 = out_f_roready_447; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_447 = out_wivalid_1_301 & out_wimask_447; // @[RegisterRouter.scala:87:24] wire out_f_woready_447 = out_woready_1_301 & out_womask_447; // @[RegisterRouter.scala:87:24] wire _out_T_4670 = ~out_rimask_447; // @[RegisterRouter.scala:87:24] wire _out_T_4671 = ~out_wimask_447; // @[RegisterRouter.scala:87:24] wire _out_T_4672 = ~out_romask_447; // @[RegisterRouter.scala:87:24] wire _out_T_4673 = ~out_womask_447; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_375 = {hi_590, flags_0_go, _out_prepend_T_375}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4674 = out_prepend_375; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4675 = _out_T_4674; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_376 = _out_T_4675; // @[RegisterRouter.scala:87:24] wire out_rimask_448 = \|_out_rimask_T_448; // @[RegisterRouter.scala:87:24] wire out_wimask_448 = &_out_wimask_T_448; // @[RegisterRouter.scala:87:24] wire out_romask_448 = \|_out_romask_T_448; // @[RegisterRouter.scala:87:24] wire out_womask_448 = &_out_womask_T_448; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_448 = out_rivalid_1_302 & out_rimask_448; // @[RegisterRouter.scala:87:24] wire _out_T_4677 = out_f_rivalid_448; // @[RegisterRouter.scala:87:24] wire out_f_roready_448 = out_roready_1_302 & out_romask_448; // @[RegisterRouter.scala:87:24] wire _out_T_4678 = out_f_roready_448; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_448 = out_wivalid_1_302 & out_wimask_448; // @[RegisterRouter.scala:87:24] wire out_f_woready_448 = out_woready_1_302 & out_womask_448; // @[RegisterRouter.scala:87:24] wire _out_T_4679 = ~out_rimask_448; // @[RegisterRouter.scala:87:24] wire _out_T_4680 = ~out_wimask_448; // @[RegisterRouter.scala:87:24] wire _out_T_4681 = ~out_romask_448; // @[RegisterRouter.scala:87:24] wire _out_T_4682 = ~out_womask_448; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_376 = {hi_591, flags_0_go, _out_prepend_T_376}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4683 = out_prepend_376; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4684 = _out_T_4683; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_377 = _out_T_4684; // @[RegisterRouter.scala:87:24] wire out_rimask_449 = \|_out_rimask_T_449; // @[RegisterRouter.scala:87:24] wire out_wimask_449 = &_out_wimask_T_449; // @[RegisterRouter.scala:87:24] wire out_romask_449 = \|_out_romask_T_449; // @[RegisterRouter.scala:87:24] wire out_womask_449 = &_out_womask_T_449; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_449 = out_rivalid_1_303 & out_rimask_449; // @[RegisterRouter.scala:87:24] wire _out_T_4686 = out_f_rivalid_449; // @[RegisterRouter.scala:87:24] wire out_f_roready_449 = out_roready_1_303 & out_romask_449; // @[RegisterRouter.scala:87:24] wire _out_T_4687 = out_f_roready_449; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_449 = out_wivalid_1_303 & out_wimask_449; // @[RegisterRouter.scala:87:24] wire out_f_woready_449 = out_woready_1_303 & out_womask_449; // @[RegisterRouter.scala:87:24] wire _out_T_4688 = ~out_rimask_449; // @[RegisterRouter.scala:87:24] wire _out_T_4689 = ~out_wimask_449; // @[RegisterRouter.scala:87:24] wire _out_T_4690 = ~out_romask_449; // @[RegisterRouter.scala:87:24] wire _out_T_4691 = ~out_womask_449; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_377 = {hi_592, flags_0_go, _out_prepend_T_377}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4692 = out_prepend_377; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4693 = _out_T_4692; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_201 = _out_T_4693; // @[MuxLiteral.scala:49:48] wire out_rimask_450 = \|_out_rimask_T_450; // @[RegisterRouter.scala:87:24] wire out_wimask_450 = &_out_wimask_T_450; // @[RegisterRouter.scala:87:24] wire out_romask_450 = \|_out_romask_T_450; // @[RegisterRouter.scala:87:24] wire out_womask_450 = &_out_womask_T_450; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_450 = out_rivalid_1_304 & out_rimask_450; // @[RegisterRouter.scala:87:24] wire _out_T_4695 = out_f_rivalid_450; // @[RegisterRouter.scala:87:24] wire out_f_roready_450 = out_roready_1_304 & out_romask_450; // @[RegisterRouter.scala:87:24] wire _out_T_4696 = out_f_roready_450; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_450 = out_wivalid_1_304 & out_wimask_450; // @[RegisterRouter.scala:87:24] wire out_f_woready_450 = out_woready_1_304 & out_womask_450; // @[RegisterRouter.scala:87:24] wire _out_T_4697 = ~out_rimask_450; // @[RegisterRouter.scala:87:24] wire _out_T_4698 = ~out_wimask_450; // @[RegisterRouter.scala:87:24] wire _out_T_4699 = ~out_romask_450; // @[RegisterRouter.scala:87:24] wire _out_T_4700 = ~out_womask_450; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4702 = _out_T_4701; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_378 = _out_T_4702; // @[RegisterRouter.scala:87:24] wire out_rimask_451 = \|_out_rimask_T_451; // @[RegisterRouter.scala:87:24] wire out_wimask_451 = &_out_wimask_T_451; // @[RegisterRouter.scala:87:24] wire out_romask_451 = \|_out_romask_T_451; // @[RegisterRouter.scala:87:24] wire out_womask_451 = &_out_womask_T_451; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_451 = out_rivalid_1_305 & out_rimask_451; // @[RegisterRouter.scala:87:24] wire _out_T_4704 = out_f_rivalid_451; // @[RegisterRouter.scala:87:24] wire out_f_roready_451 = out_roready_1_305 & out_romask_451; // @[RegisterRouter.scala:87:24] wire _out_T_4705 = out_f_roready_451; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_451 = out_wivalid_1_305 & out_wimask_451; // @[RegisterRouter.scala:87:24] wire out_f_woready_451 = out_woready_1_305 & out_womask_451; // @[RegisterRouter.scala:87:24] wire _out_T_4706 = ~out_rimask_451; // @[RegisterRouter.scala:87:24] wire _out_T_4707 = ~out_wimask_451; // @[RegisterRouter.scala:87:24] wire _out_T_4708 = ~out_romask_451; // @[RegisterRouter.scala:87:24] wire _out_T_4709 = ~out_womask_451; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_378 = {hi_738, flags_0_go, _out_prepend_T_378}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4710 = out_prepend_378; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4711 = _out_T_4710; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_379 = _out_T_4711; // @[RegisterRouter.scala:87:24] wire out_rimask_452 = \|_out_rimask_T_452; // @[RegisterRouter.scala:87:24] wire out_wimask_452 = &_out_wimask_T_452; // @[RegisterRouter.scala:87:24] wire out_romask_452 = \|_out_romask_T_452; // @[RegisterRouter.scala:87:24] wire out_womask_452 = &_out_womask_T_452; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_452 = out_rivalid_1_306 & out_rimask_452; // @[RegisterRouter.scala:87:24] wire _out_T_4713 = out_f_rivalid_452; // @[RegisterRouter.scala:87:24] wire out_f_roready_452 = out_roready_1_306 & out_romask_452; // @[RegisterRouter.scala:87:24] wire _out_T_4714 = out_f_roready_452; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_452 = out_wivalid_1_306 & out_wimask_452; // @[RegisterRouter.scala:87:24] wire out_f_woready_452 = out_woready_1_306 & out_womask_452; // @[RegisterRouter.scala:87:24] wire _out_T_4715 = ~out_rimask_452; // @[RegisterRouter.scala:87:24] wire _out_T_4716 = ~out_wimask_452; // @[RegisterRouter.scala:87:24] wire _out_T_4717 = ~out_romask_452; // @[RegisterRouter.scala:87:24] wire _out_T_4718 = ~out_womask_452; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_379 = {hi_739, flags_0_go, _out_prepend_T_379}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4719 = out_prepend_379; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4720 = _out_T_4719; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_380 = _out_T_4720; // @[RegisterRouter.scala:87:24] wire out_rimask_453 = \|_out_rimask_T_453; // @[RegisterRouter.scala:87:24] wire out_wimask_453 = &_out_wimask_T_453; // @[RegisterRouter.scala:87:24] wire out_romask_453 = \|_out_romask_T_453; // @[RegisterRouter.scala:87:24] wire out_womask_453 = &_out_womask_T_453; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_453 = out_rivalid_1_307 & out_rimask_453; // @[RegisterRouter.scala:87:24] wire _out_T_4722 = out_f_rivalid_453; // @[RegisterRouter.scala:87:24] wire out_f_roready_453 = out_roready_1_307 & out_romask_453; // @[RegisterRouter.scala:87:24] wire _out_T_4723 = out_f_roready_453; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_453 = out_wivalid_1_307 & out_wimask_453; // @[RegisterRouter.scala:87:24] wire out_f_woready_453 = out_woready_1_307 & out_womask_453; // @[RegisterRouter.scala:87:24] wire _out_T_4724 = ~out_rimask_453; // @[RegisterRouter.scala:87:24] wire _out_T_4725 = ~out_wimask_453; // @[RegisterRouter.scala:87:24] wire _out_T_4726 = ~out_romask_453; // @[RegisterRouter.scala:87:24] wire _out_T_4727 = ~out_womask_453; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_380 = {hi_740, flags_0_go, _out_prepend_T_380}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4728 = out_prepend_380; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4729 = _out_T_4728; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_381 = _out_T_4729; // @[RegisterRouter.scala:87:24] wire out_rimask_454 = \|_out_rimask_T_454; // @[RegisterRouter.scala:87:24] wire out_wimask_454 = &_out_wimask_T_454; // @[RegisterRouter.scala:87:24] wire out_romask_454 = \|_out_romask_T_454; // @[RegisterRouter.scala:87:24] wire out_womask_454 = &_out_womask_T_454; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_454 = out_rivalid_1_308 & out_rimask_454; // @[RegisterRouter.scala:87:24] wire _out_T_4731 = out_f_rivalid_454; // @[RegisterRouter.scala:87:24] wire out_f_roready_454 = out_roready_1_308 & out_romask_454; // @[RegisterRouter.scala:87:24] wire _out_T_4732 = out_f_roready_454; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_454 = out_wivalid_1_308 & out_wimask_454; // @[RegisterRouter.scala:87:24] wire out_f_woready_454 = out_woready_1_308 & out_womask_454; // @[RegisterRouter.scala:87:24] wire _out_T_4733 = ~out_rimask_454; // @[RegisterRouter.scala:87:24] wire _out_T_4734 = ~out_wimask_454; // @[RegisterRouter.scala:87:24] wire _out_T_4735 = ~out_romask_454; // @[RegisterRouter.scala:87:24] wire _out_T_4736 = ~out_womask_454; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_381 = {hi_741, flags_0_go, _out_prepend_T_381}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4737 = out_prepend_381; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4738 = _out_T_4737; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_382 = _out_T_4738; // @[RegisterRouter.scala:87:24] wire out_rimask_455 = \|_out_rimask_T_455; // @[RegisterRouter.scala:87:24] wire out_wimask_455 = &_out_wimask_T_455; // @[RegisterRouter.scala:87:24] wire out_romask_455 = \|_out_romask_T_455; // @[RegisterRouter.scala:87:24] wire out_womask_455 = &_out_womask_T_455; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_455 = out_rivalid_1_309 & out_rimask_455; // @[RegisterRouter.scala:87:24] wire _out_T_4740 = out_f_rivalid_455; // @[RegisterRouter.scala:87:24] wire out_f_roready_455 = out_roready_1_309 & out_romask_455; // @[RegisterRouter.scala:87:24] wire _out_T_4741 = out_f_roready_455; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_455 = out_wivalid_1_309 & out_wimask_455; // @[RegisterRouter.scala:87:24] wire out_f_woready_455 = out_woready_1_309 & out_womask_455; // @[RegisterRouter.scala:87:24] wire _out_T_4742 = ~out_rimask_455; // @[RegisterRouter.scala:87:24] wire _out_T_4743 = ~out_wimask_455; // @[RegisterRouter.scala:87:24] wire _out_T_4744 = ~out_romask_455; // @[RegisterRouter.scala:87:24] wire _out_T_4745 = ~out_womask_455; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_382 = {hi_742, flags_0_go, _out_prepend_T_382}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4746 = out_prepend_382; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4747 = _out_T_4746; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_383 = _out_T_4747; // @[RegisterRouter.scala:87:24] wire out_rimask_456 = \|_out_rimask_T_456; // @[RegisterRouter.scala:87:24] wire out_wimask_456 = &_out_wimask_T_456; // @[RegisterRouter.scala:87:24] wire out_romask_456 = \|_out_romask_T_456; // @[RegisterRouter.scala:87:24] wire out_womask_456 = &_out_womask_T_456; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_456 = out_rivalid_1_310 & out_rimask_456; // @[RegisterRouter.scala:87:24] wire _out_T_4749 = out_f_rivalid_456; // @[RegisterRouter.scala:87:24] wire out_f_roready_456 = out_roready_1_310 & out_romask_456; // @[RegisterRouter.scala:87:24] wire _out_T_4750 = out_f_roready_456; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_456 = out_wivalid_1_310 & out_wimask_456; // @[RegisterRouter.scala:87:24] wire out_f_woready_456 = out_woready_1_310 & out_womask_456; // @[RegisterRouter.scala:87:24] wire _out_T_4751 = ~out_rimask_456; // @[RegisterRouter.scala:87:24] wire _out_T_4752 = ~out_wimask_456; // @[RegisterRouter.scala:87:24] wire _out_T_4753 = ~out_romask_456; // @[RegisterRouter.scala:87:24] wire _out_T_4754 = ~out_womask_456; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_383 = {hi_743, flags_0_go, _out_prepend_T_383}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4755 = out_prepend_383; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4756 = _out_T_4755; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_384 = _out_T_4756; // @[RegisterRouter.scala:87:24] wire out_rimask_457 = \|_out_rimask_T_457; // @[RegisterRouter.scala:87:24] wire out_wimask_457 = &_out_wimask_T_457; // @[RegisterRouter.scala:87:24] wire out_romask_457 = \|_out_romask_T_457; // @[RegisterRouter.scala:87:24] wire out_womask_457 = &_out_womask_T_457; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_457 = out_rivalid_1_311 & out_rimask_457; // @[RegisterRouter.scala:87:24] wire _out_T_4758 = out_f_rivalid_457; // @[RegisterRouter.scala:87:24] wire out_f_roready_457 = out_roready_1_311 & out_romask_457; // @[RegisterRouter.scala:87:24] wire _out_T_4759 = out_f_roready_457; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_457 = out_wivalid_1_311 & out_wimask_457; // @[RegisterRouter.scala:87:24] wire out_f_woready_457 = out_woready_1_311 & out_womask_457; // @[RegisterRouter.scala:87:24] wire _out_T_4760 = ~out_rimask_457; // @[RegisterRouter.scala:87:24] wire _out_T_4761 = ~out_wimask_457; // @[RegisterRouter.scala:87:24] wire _out_T_4762 = ~out_romask_457; // @[RegisterRouter.scala:87:24] wire _out_T_4763 = ~out_womask_457; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_384 = {hi_744, flags_0_go, _out_prepend_T_384}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4764 = out_prepend_384; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4765 = _out_T_4764; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_220 = _out_T_4765; // @[MuxLiteral.scala:49:48] wire out_rimask_458 = \|_out_rimask_T_458; // @[RegisterRouter.scala:87:24] wire out_wimask_458 = &_out_wimask_T_458; // @[RegisterRouter.scala:87:24] wire out_romask_458 = \|_out_romask_T_458; // @[RegisterRouter.scala:87:24] wire out_womask_458 = &_out_womask_T_458; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_458 = out_rivalid_1_312 & out_rimask_458; // @[RegisterRouter.scala:87:24] wire _out_T_4767 = out_f_rivalid_458; // @[RegisterRouter.scala:87:24] wire out_f_roready_458 = out_roready_1_312 & out_romask_458; // @[RegisterRouter.scala:87:24] wire _out_T_4768 = out_f_roready_458; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_458 = out_wivalid_1_312 & out_wimask_458; // @[RegisterRouter.scala:87:24] wire out_f_woready_458 = out_woready_1_312 & out_womask_458; // @[RegisterRouter.scala:87:24] wire _out_T_4769 = ~out_rimask_458; // @[RegisterRouter.scala:87:24] wire _out_T_4770 = ~out_wimask_458; // @[RegisterRouter.scala:87:24] wire _out_T_4771 = ~out_romask_458; // @[RegisterRouter.scala:87:24] wire _out_T_4772 = ~out_womask_458; // @[RegisterRouter.scala:87:24] wire out_rimask_459 = \|_out_rimask_T_459; // @[RegisterRouter.scala:87:24] wire out_wimask_459 = &_out_wimask_T_459; // @[RegisterRouter.scala:87:24] wire out_romask_459 = \|_out_romask_T_459; // @[RegisterRouter.scala:87:24] wire out_womask_459 = &_out_womask_T_459; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_459 = out_rivalid_1_313 & out_rimask_459; // @[RegisterRouter.scala:87:24] wire _out_T_4776 = out_f_rivalid_459; // @[RegisterRouter.scala:87:24] wire out_f_roready_459 = out_roready_1_313 & out_romask_459; // @[RegisterRouter.scala:87:24] wire _out_T_4777 = out_f_roready_459; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_459 = out_wivalid_1_313 & out_wimask_459; // @[RegisterRouter.scala:87:24] wire out_f_woready_459 = out_woready_1_313 & out_womask_459; // @[RegisterRouter.scala:87:24] wire _out_T_4778 = ~out_rimask_459; // @[RegisterRouter.scala:87:24] wire _out_T_4779 = ~out_wimask_459; // @[RegisterRouter.scala:87:24] wire _out_T_4780 = ~out_romask_459; // @[RegisterRouter.scala:87:24] wire _out_T_4781 = ~out_womask_459; // @[RegisterRouter.scala:87:24] wire out_rimask_460 = \|_out_rimask_T_460; // @[RegisterRouter.scala:87:24] wire out_wimask_460 = &_out_wimask_T_460; // @[RegisterRouter.scala:87:24] wire out_romask_460 = \|_out_romask_T_460; // @[RegisterRouter.scala:87:24] wire out_womask_460 = &_out_womask_T_460; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_460 = out_rivalid_1_314 & out_rimask_460; // @[RegisterRouter.scala:87:24] wire _out_T_4785 = out_f_rivalid_460; // @[RegisterRouter.scala:87:24] wire out_f_roready_460 = out_roready_1_314 & out_romask_460; // @[RegisterRouter.scala:87:24] wire _out_T_4786 = out_f_roready_460; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_460 = out_wivalid_1_314 & out_wimask_460; // @[RegisterRouter.scala:87:24] wire out_f_woready_460 = out_woready_1_314 & out_womask_460; // @[RegisterRouter.scala:87:24] wire _out_T_4787 = ~out_rimask_460; // @[RegisterRouter.scala:87:24] wire _out_T_4788 = ~out_wimask_460; // @[RegisterRouter.scala:87:24] wire _out_T_4789 = ~out_romask_460; // @[RegisterRouter.scala:87:24] wire _out_T_4790 = ~out_womask_460; // @[RegisterRouter.scala:87:24] wire out_rimask_461 = \|_out_rimask_T_461; // @[RegisterRouter.scala:87:24] wire out_wimask_461 = &_out_wimask_T_461; // @[RegisterRouter.scala:87:24] wire out_romask_461 = \|_out_romask_T_461; // @[RegisterRouter.scala:87:24] wire out_womask_461 = &_out_womask_T_461; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_461 = out_rivalid_1_315 & out_rimask_461; // @[RegisterRouter.scala:87:24] wire _out_T_4794 = out_f_rivalid_461; // @[RegisterRouter.scala:87:24] wire out_f_roready_461 = out_roready_1_315 & out_romask_461; // @[RegisterRouter.scala:87:24] wire _out_T_4795 = out_f_roready_461; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_461 = out_wivalid_1_315 & out_wimask_461; // @[RegisterRouter.scala:87:24] wire out_f_woready_461 = out_woready_1_315 & out_womask_461; // @[RegisterRouter.scala:87:24] wire _out_T_4796 = ~out_rimask_461; // @[RegisterRouter.scala:87:24] wire _out_T_4797 = ~out_wimask_461; // @[RegisterRouter.scala:87:24] wire _out_T_4798 = ~out_romask_461; // @[RegisterRouter.scala:87:24] wire _out_T_4799 = ~out_womask_461; // @[RegisterRouter.scala:87:24] wire out_rimask_462 = \|_out_rimask_T_462; // @[RegisterRouter.scala:87:24] wire out_wimask_462 = &_out_wimask_T_462; // @[RegisterRouter.scala:87:24] wire out_romask_462 = \|_out_romask_T_462; // @[RegisterRouter.scala:87:24] wire out_womask_462 = &_out_womask_T_462; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_462 = out_rivalid_1_316 & out_rimask_462; // @[RegisterRouter.scala:87:24] wire _out_T_4803 = out_f_rivalid_462; // @[RegisterRouter.scala:87:24] wire out_f_roready_462 = out_roready_1_316 & out_romask_462; // @[RegisterRouter.scala:87:24] wire _out_T_4804 = out_f_roready_462; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_462 = out_wivalid_1_316 & out_wimask_462; // @[RegisterRouter.scala:87:24] wire out_f_woready_462 = out_woready_1_316 & out_womask_462; // @[RegisterRouter.scala:87:24] wire _out_T_4805 = ~out_rimask_462; // @[RegisterRouter.scala:87:24] wire _out_T_4806 = ~out_wimask_462; // @[RegisterRouter.scala:87:24] wire _out_T_4807 = ~out_romask_462; // @[RegisterRouter.scala:87:24] wire _out_T_4808 = ~out_womask_462; // @[RegisterRouter.scala:87:24] wire out_rimask_463 = \|_out_rimask_T_463; // @[RegisterRouter.scala:87:24] wire out_wimask_463 = &_out_wimask_T_463; // @[RegisterRouter.scala:87:24] wire out_romask_463 = \|_out_romask_T_463; // @[RegisterRouter.scala:87:24] wire out_womask_463 = &_out_womask_T_463; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_463 = out_rivalid_1_317 & out_rimask_463; // @[RegisterRouter.scala:87:24] wire _out_T_4812 = out_f_rivalid_463; // @[RegisterRouter.scala:87:24] wire out_f_roready_463 = out_roready_1_317 & out_romask_463; // @[RegisterRouter.scala:87:24] wire _out_T_4813 = out_f_roready_463; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_463 = out_wivalid_1_317 & out_wimask_463; // @[RegisterRouter.scala:87:24] wire out_f_woready_463 = out_woready_1_317 & out_womask_463; // @[RegisterRouter.scala:87:24] wire _out_T_4814 = ~out_rimask_463; // @[RegisterRouter.scala:87:24] wire _out_T_4815 = ~out_wimask_463; // @[RegisterRouter.scala:87:24] wire _out_T_4816 = ~out_romask_463; // @[RegisterRouter.scala:87:24] wire _out_T_4817 = ~out_womask_463; // @[RegisterRouter.scala:87:24] wire out_rimask_464 = \|_out_rimask_T_464; // @[RegisterRouter.scala:87:24] wire out_wimask_464 = &_out_wimask_T_464; // @[RegisterRouter.scala:87:24] wire out_romask_464 = \|_out_romask_T_464; // @[RegisterRouter.scala:87:24] wire out_womask_464 = &_out_womask_T_464; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_464 = out_rivalid_1_318 & out_rimask_464; // @[RegisterRouter.scala:87:24] wire _out_T_4821 = out_f_rivalid_464; // @[RegisterRouter.scala:87:24] wire out_f_roready_464 = out_roready_1_318 & out_romask_464; // @[RegisterRouter.scala:87:24] wire _out_T_4822 = out_f_roready_464; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_464 = out_wivalid_1_318 & out_wimask_464; // @[RegisterRouter.scala:87:24] wire out_f_woready_464 = out_woready_1_318 & out_womask_464; // @[RegisterRouter.scala:87:24] wire _out_T_4823 = ~out_rimask_464; // @[RegisterRouter.scala:87:24] wire _out_T_4824 = ~out_wimask_464; // @[RegisterRouter.scala:87:24] wire _out_T_4825 = ~out_romask_464; // @[RegisterRouter.scala:87:24] wire _out_T_4826 = ~out_womask_464; // @[RegisterRouter.scala:87:24] wire out_rimask_465 = \|_out_rimask_T_465; // @[RegisterRouter.scala:87:24] wire out_wimask_465 = &_out_wimask_T_465; // @[RegisterRouter.scala:87:24] wire out_romask_465 = \|_out_romask_T_465; // @[RegisterRouter.scala:87:24] wire out_womask_465 = &_out_womask_T_465; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_465 = out_rivalid_1_319 & out_rimask_465; // @[RegisterRouter.scala:87:24] wire _out_T_4830 = out_f_rivalid_465; // @[RegisterRouter.scala:87:24] wire out_f_roready_465 = out_roready_1_319 & out_romask_465; // @[RegisterRouter.scala:87:24] wire _out_T_4831 = out_f_roready_465; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_465 = out_wivalid_1_319 & out_wimask_465; // @[RegisterRouter.scala:87:24] wire out_f_woready_465 = out_woready_1_319 & out_womask_465; // @[RegisterRouter.scala:87:24] wire _out_T_4832 = ~out_rimask_465; // @[RegisterRouter.scala:87:24] wire _out_T_4833 = ~out_wimask_465; // @[RegisterRouter.scala:87:24] wire _out_T_4834 = ~out_romask_465; // @[RegisterRouter.scala:87:24] wire _out_T_4835 = ~out_womask_465; // @[RegisterRouter.scala:87:24] wire out_rimask_466 = \|_out_rimask_T_466; // @[RegisterRouter.scala:87:24] wire out_wimask_466 = &_out_wimask_T_466; // @[RegisterRouter.scala:87:24] wire out_romask_466 = \|_out_romask_T_466; // @[RegisterRouter.scala:87:24] wire out_womask_466 = &_out_womask_T_466; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_466 = out_rivalid_1_320 & out_rimask_466; // @[RegisterRouter.scala:87:24] wire _out_T_4839 = out_f_rivalid_466; // @[RegisterRouter.scala:87:24] wire out_f_roready_466 = out_roready_1_320 & out_romask_466; // @[RegisterRouter.scala:87:24] wire _out_T_4840 = out_f_roready_466; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_466 = out_wivalid_1_320 & out_wimask_466; // @[RegisterRouter.scala:87:24] wire out_f_woready_466 = out_woready_1_320 & out_womask_466; // @[RegisterRouter.scala:87:24] wire _out_T_4841 = ~out_rimask_466; // @[RegisterRouter.scala:87:24] wire _out_T_4842 = ~out_wimask_466; // @[RegisterRouter.scala:87:24] wire _out_T_4843 = ~out_romask_466; // @[RegisterRouter.scala:87:24] wire _out_T_4844 = ~out_womask_466; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4846 = _out_T_4845; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_392 = _out_T_4846; // @[RegisterRouter.scala:87:24] wire out_rimask_467 = \|_out_rimask_T_467; // @[RegisterRouter.scala:87:24] wire out_wimask_467 = &_out_wimask_T_467; // @[RegisterRouter.scala:87:24] wire out_romask_467 = \|_out_romask_T_467; // @[RegisterRouter.scala:87:24] wire out_womask_467 = &_out_womask_T_467; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_467 = out_rivalid_1_321 & out_rimask_467; // @[RegisterRouter.scala:87:24] wire _out_T_4848 = out_f_rivalid_467; // @[RegisterRouter.scala:87:24] wire out_f_roready_467 = out_roready_1_321 & out_romask_467; // @[RegisterRouter.scala:87:24] wire _out_T_4849 = out_f_roready_467; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_467 = out_wivalid_1_321 & out_wimask_467; // @[RegisterRouter.scala:87:24] wire out_f_woready_467 = out_woready_1_321 & out_womask_467; // @[RegisterRouter.scala:87:24] wire _out_T_4850 = ~out_rimask_467; // @[RegisterRouter.scala:87:24] wire _out_T_4851 = ~out_wimask_467; // @[RegisterRouter.scala:87:24] wire _out_T_4852 = ~out_romask_467; // @[RegisterRouter.scala:87:24] wire _out_T_4853 = ~out_womask_467; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_392 = {hi_258, flags_0_go, _out_prepend_T_392}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4854 = out_prepend_392; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4855 = _out_T_4854; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_393 = _out_T_4855; // @[RegisterRouter.scala:87:24] wire out_rimask_468 = \|_out_rimask_T_468; // @[RegisterRouter.scala:87:24] wire out_wimask_468 = &_out_wimask_T_468; // @[RegisterRouter.scala:87:24] wire out_romask_468 = \|_out_romask_T_468; // @[RegisterRouter.scala:87:24] wire out_womask_468 = &_out_womask_T_468; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_468 = out_rivalid_1_322 & out_rimask_468; // @[RegisterRouter.scala:87:24] wire _out_T_4857 = out_f_rivalid_468; // @[RegisterRouter.scala:87:24] wire out_f_roready_468 = out_roready_1_322 & out_romask_468; // @[RegisterRouter.scala:87:24] wire _out_T_4858 = out_f_roready_468; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_468 = out_wivalid_1_322 & out_wimask_468; // @[RegisterRouter.scala:87:24] wire out_f_woready_468 = out_woready_1_322 & out_womask_468; // @[RegisterRouter.scala:87:24] wire _out_T_4859 = ~out_rimask_468; // @[RegisterRouter.scala:87:24] wire _out_T_4860 = ~out_wimask_468; // @[RegisterRouter.scala:87:24] wire _out_T_4861 = ~out_romask_468; // @[RegisterRouter.scala:87:24] wire _out_T_4862 = ~out_womask_468; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_393 = {hi_259, flags_0_go, _out_prepend_T_393}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4863 = out_prepend_393; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4864 = _out_T_4863; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_394 = _out_T_4864; // @[RegisterRouter.scala:87:24] wire out_rimask_469 = \|_out_rimask_T_469; // @[RegisterRouter.scala:87:24] wire out_wimask_469 = &_out_wimask_T_469; // @[RegisterRouter.scala:87:24] wire out_romask_469 = \|_out_romask_T_469; // @[RegisterRouter.scala:87:24] wire out_womask_469 = &_out_womask_T_469; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_469 = out_rivalid_1_323 & out_rimask_469; // @[RegisterRouter.scala:87:24] wire _out_T_4866 = out_f_rivalid_469; // @[RegisterRouter.scala:87:24] wire out_f_roready_469 = out_roready_1_323 & out_romask_469; // @[RegisterRouter.scala:87:24] wire _out_T_4867 = out_f_roready_469; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_469 = out_wivalid_1_323 & out_wimask_469; // @[RegisterRouter.scala:87:24] wire out_f_woready_469 = out_woready_1_323 & out_womask_469; // @[RegisterRouter.scala:87:24] wire _out_T_4868 = ~out_rimask_469; // @[RegisterRouter.scala:87:24] wire _out_T_4869 = ~out_wimask_469; // @[RegisterRouter.scala:87:24] wire _out_T_4870 = ~out_romask_469; // @[RegisterRouter.scala:87:24] wire _out_T_4871 = ~out_womask_469; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_394 = {hi_260, flags_0_go, _out_prepend_T_394}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4872 = out_prepend_394; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4873 = _out_T_4872; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_395 = _out_T_4873; // @[RegisterRouter.scala:87:24] wire out_rimask_470 = \|_out_rimask_T_470; // @[RegisterRouter.scala:87:24] wire out_wimask_470 = &_out_wimask_T_470; // @[RegisterRouter.scala:87:24] wire out_romask_470 = \|_out_romask_T_470; // @[RegisterRouter.scala:87:24] wire out_womask_470 = &_out_womask_T_470; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_470 = out_rivalid_1_324 & out_rimask_470; // @[RegisterRouter.scala:87:24] wire _out_T_4875 = out_f_rivalid_470; // @[RegisterRouter.scala:87:24] wire out_f_roready_470 = out_roready_1_324 & out_romask_470; // @[RegisterRouter.scala:87:24] wire _out_T_4876 = out_f_roready_470; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_470 = out_wivalid_1_324 & out_wimask_470; // @[RegisterRouter.scala:87:24] wire out_f_woready_470 = out_woready_1_324 & out_womask_470; // @[RegisterRouter.scala:87:24] wire _out_T_4877 = ~out_rimask_470; // @[RegisterRouter.scala:87:24] wire _out_T_4878 = ~out_wimask_470; // @[RegisterRouter.scala:87:24] wire _out_T_4879 = ~out_romask_470; // @[RegisterRouter.scala:87:24] wire _out_T_4880 = ~out_womask_470; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_395 = {hi_261, flags_0_go, _out_prepend_T_395}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4881 = out_prepend_395; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4882 = _out_T_4881; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_396 = _out_T_4882; // @[RegisterRouter.scala:87:24] wire out_rimask_471 = \|_out_rimask_T_471; // @[RegisterRouter.scala:87:24] wire out_wimask_471 = &_out_wimask_T_471; // @[RegisterRouter.scala:87:24] wire out_romask_471 = \|_out_romask_T_471; // @[RegisterRouter.scala:87:24] wire out_womask_471 = &_out_womask_T_471; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_471 = out_rivalid_1_325 & out_rimask_471; // @[RegisterRouter.scala:87:24] wire _out_T_4884 = out_f_rivalid_471; // @[RegisterRouter.scala:87:24] wire out_f_roready_471 = out_roready_1_325 & out_romask_471; // @[RegisterRouter.scala:87:24] wire _out_T_4885 = out_f_roready_471; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_471 = out_wivalid_1_325 & out_wimask_471; // @[RegisterRouter.scala:87:24] wire out_f_woready_471 = out_woready_1_325 & out_womask_471; // @[RegisterRouter.scala:87:24] wire _out_T_4886 = ~out_rimask_471; // @[RegisterRouter.scala:87:24] wire _out_T_4887 = ~out_wimask_471; // @[RegisterRouter.scala:87:24] wire _out_T_4888 = ~out_romask_471; // @[RegisterRouter.scala:87:24] wire _out_T_4889 = ~out_womask_471; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_396 = {hi_262, flags_0_go, _out_prepend_T_396}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4890 = out_prepend_396; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4891 = _out_T_4890; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_397 = _out_T_4891; // @[RegisterRouter.scala:87:24] wire out_rimask_472 = \|_out_rimask_T_472; // @[RegisterRouter.scala:87:24] wire out_wimask_472 = &_out_wimask_T_472; // @[RegisterRouter.scala:87:24] wire out_romask_472 = \|_out_romask_T_472; // @[RegisterRouter.scala:87:24] wire out_womask_472 = &_out_womask_T_472; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_472 = out_rivalid_1_326 & out_rimask_472; // @[RegisterRouter.scala:87:24] wire _out_T_4893 = out_f_rivalid_472; // @[RegisterRouter.scala:87:24] wire out_f_roready_472 = out_roready_1_326 & out_romask_472; // @[RegisterRouter.scala:87:24] wire _out_T_4894 = out_f_roready_472; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_472 = out_wivalid_1_326 & out_wimask_472; // @[RegisterRouter.scala:87:24] wire out_f_woready_472 = out_woready_1_326 & out_womask_472; // @[RegisterRouter.scala:87:24] wire _out_T_4895 = ~out_rimask_472; // @[RegisterRouter.scala:87:24] wire _out_T_4896 = ~out_wimask_472; // @[RegisterRouter.scala:87:24] wire _out_T_4897 = ~out_romask_472; // @[RegisterRouter.scala:87:24] wire _out_T_4898 = ~out_womask_472; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_397 = {hi_263, flags_0_go, _out_prepend_T_397}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4899 = out_prepend_397; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4900 = _out_T_4899; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_398 = _out_T_4900; // @[RegisterRouter.scala:87:24] wire out_rimask_473 = \|_out_rimask_T_473; // @[RegisterRouter.scala:87:24] wire out_wimask_473 = &_out_wimask_T_473; // @[RegisterRouter.scala:87:24] wire out_romask_473 = \|_out_romask_T_473; // @[RegisterRouter.scala:87:24] wire out_womask_473 = &_out_womask_T_473; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_473 = out_rivalid_1_327 & out_rimask_473; // @[RegisterRouter.scala:87:24] wire _out_T_4902 = out_f_rivalid_473; // @[RegisterRouter.scala:87:24] wire out_f_roready_473 = out_roready_1_327 & out_romask_473; // @[RegisterRouter.scala:87:24] wire _out_T_4903 = out_f_roready_473; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_473 = out_wivalid_1_327 & out_wimask_473; // @[RegisterRouter.scala:87:24] wire out_f_woready_473 = out_woready_1_327 & out_womask_473; // @[RegisterRouter.scala:87:24] wire _out_T_4904 = ~out_rimask_473; // @[RegisterRouter.scala:87:24] wire _out_T_4905 = ~out_wimask_473; // @[RegisterRouter.scala:87:24] wire _out_T_4906 = ~out_romask_473; // @[RegisterRouter.scala:87:24] wire _out_T_4907 = ~out_womask_473; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_398 = {hi_264, flags_0_go, _out_prepend_T_398}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4908 = out_prepend_398; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4909 = _out_T_4908; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_160 = _out_T_4909; // @[MuxLiteral.scala:49:48] wire out_rimask_474 = \|_out_rimask_T_474; // @[RegisterRouter.scala:87:24] wire out_wimask_474 = &_out_wimask_T_474; // @[RegisterRouter.scala:87:24] wire out_romask_474 = \|_out_romask_T_474; // @[RegisterRouter.scala:87:24] wire out_womask_474 = &_out_womask_T_474; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_474 = out_rivalid_1_328 & out_rimask_474; // @[RegisterRouter.scala:87:24] wire _out_T_4911 = out_f_rivalid_474; // @[RegisterRouter.scala:87:24] wire out_f_roready_474 = out_roready_1_328 & out_romask_474; // @[RegisterRouter.scala:87:24] wire _out_T_4912 = out_f_roready_474; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_474 = out_wivalid_1_328 & out_wimask_474; // @[RegisterRouter.scala:87:24] wire out_f_woready_474 = out_woready_1_328 & out_womask_474; // @[RegisterRouter.scala:87:24] wire _out_T_4913 = ~out_rimask_474; // @[RegisterRouter.scala:87:24] wire _out_T_4914 = ~out_wimask_474; // @[RegisterRouter.scala:87:24] wire _out_T_4915 = ~out_romask_474; // @[RegisterRouter.scala:87:24] wire _out_T_4916 = ~out_womask_474; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4918 = _out_T_4917; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_399 = _out_T_4918; // @[RegisterRouter.scala:87:24] wire out_rimask_475 = \|_out_rimask_T_475; // @[RegisterRouter.scala:87:24] wire out_wimask_475 = &_out_wimask_T_475; // @[RegisterRouter.scala:87:24] wire out_romask_475 = \|_out_romask_T_475; // @[RegisterRouter.scala:87:24] wire out_womask_475 = &_out_womask_T_475; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_475 = out_rivalid_1_329 & out_rimask_475; // @[RegisterRouter.scala:87:24] wire _out_T_4920 = out_f_rivalid_475; // @[RegisterRouter.scala:87:24] wire out_f_roready_475 = out_roready_1_329 & out_romask_475; // @[RegisterRouter.scala:87:24] wire _out_T_4921 = out_f_roready_475; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_475 = out_wivalid_1_329 & out_wimask_475; // @[RegisterRouter.scala:87:24] wire out_f_woready_475 = out_woready_1_329 & out_womask_475; // @[RegisterRouter.scala:87:24] wire _out_T_4922 = ~out_rimask_475; // @[RegisterRouter.scala:87:24] wire _out_T_4923 = ~out_wimask_475; // @[RegisterRouter.scala:87:24] wire _out_T_4924 = ~out_romask_475; // @[RegisterRouter.scala:87:24] wire _out_T_4925 = ~out_womask_475; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_399 = {hi_514, flags_0_go, _out_prepend_T_399}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4926 = out_prepend_399; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4927 = _out_T_4926; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_400 = _out_T_4927; // @[RegisterRouter.scala:87:24] wire out_rimask_476 = \|_out_rimask_T_476; // @[RegisterRouter.scala:87:24] wire out_wimask_476 = &_out_wimask_T_476; // @[RegisterRouter.scala:87:24] wire out_romask_476 = \|_out_romask_T_476; // @[RegisterRouter.scala:87:24] wire out_womask_476 = &_out_womask_T_476; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_476 = out_rivalid_1_330 & out_rimask_476; // @[RegisterRouter.scala:87:24] wire _out_T_4929 = out_f_rivalid_476; // @[RegisterRouter.scala:87:24] wire out_f_roready_476 = out_roready_1_330 & out_romask_476; // @[RegisterRouter.scala:87:24] wire _out_T_4930 = out_f_roready_476; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_476 = out_wivalid_1_330 & out_wimask_476; // @[RegisterRouter.scala:87:24] wire out_f_woready_476 = out_woready_1_330 & out_womask_476; // @[RegisterRouter.scala:87:24] wire _out_T_4931 = ~out_rimask_476; // @[RegisterRouter.scala:87:24] wire _out_T_4932 = ~out_wimask_476; // @[RegisterRouter.scala:87:24] wire _out_T_4933 = ~out_romask_476; // @[RegisterRouter.scala:87:24] wire _out_T_4934 = ~out_womask_476; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_400 = {hi_515, flags_0_go, _out_prepend_T_400}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4935 = out_prepend_400; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4936 = _out_T_4935; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_401 = _out_T_4936; // @[RegisterRouter.scala:87:24] wire out_rimask_477 = \|_out_rimask_T_477; // @[RegisterRouter.scala:87:24] wire out_wimask_477 = &_out_wimask_T_477; // @[RegisterRouter.scala:87:24] wire out_romask_477 = \|_out_romask_T_477; // @[RegisterRouter.scala:87:24] wire out_womask_477 = &_out_womask_T_477; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_477 = out_rivalid_1_331 & out_rimask_477; // @[RegisterRouter.scala:87:24] wire _out_T_4938 = out_f_rivalid_477; // @[RegisterRouter.scala:87:24] wire out_f_roready_477 = out_roready_1_331 & out_romask_477; // @[RegisterRouter.scala:87:24] wire _out_T_4939 = out_f_roready_477; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_477 = out_wivalid_1_331 & out_wimask_477; // @[RegisterRouter.scala:87:24] wire out_f_woready_477 = out_woready_1_331 & out_womask_477; // @[RegisterRouter.scala:87:24] wire _out_T_4940 = ~out_rimask_477; // @[RegisterRouter.scala:87:24] wire _out_T_4941 = ~out_wimask_477; // @[RegisterRouter.scala:87:24] wire _out_T_4942 = ~out_romask_477; // @[RegisterRouter.scala:87:24] wire _out_T_4943 = ~out_womask_477; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_401 = {hi_516, flags_0_go, _out_prepend_T_401}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4944 = out_prepend_401; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4945 = _out_T_4944; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_402 = _out_T_4945; // @[RegisterRouter.scala:87:24] wire out_rimask_478 = \|_out_rimask_T_478; // @[RegisterRouter.scala:87:24] wire out_wimask_478 = &_out_wimask_T_478; // @[RegisterRouter.scala:87:24] wire out_romask_478 = \|_out_romask_T_478; // @[RegisterRouter.scala:87:24] wire out_womask_478 = &_out_womask_T_478; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_478 = out_rivalid_1_332 & out_rimask_478; // @[RegisterRouter.scala:87:24] wire _out_T_4947 = out_f_rivalid_478; // @[RegisterRouter.scala:87:24] wire out_f_roready_478 = out_roready_1_332 & out_romask_478; // @[RegisterRouter.scala:87:24] wire _out_T_4948 = out_f_roready_478; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_478 = out_wivalid_1_332 & out_wimask_478; // @[RegisterRouter.scala:87:24] wire out_f_woready_478 = out_woready_1_332 & out_womask_478; // @[RegisterRouter.scala:87:24] wire _out_T_4949 = ~out_rimask_478; // @[RegisterRouter.scala:87:24] wire _out_T_4950 = ~out_wimask_478; // @[RegisterRouter.scala:87:24] wire _out_T_4951 = ~out_romask_478; // @[RegisterRouter.scala:87:24] wire _out_T_4952 = ~out_womask_478; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_402 = {hi_517, flags_0_go, _out_prepend_T_402}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4953 = out_prepend_402; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4954 = _out_T_4953; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_403 = _out_T_4954; // @[RegisterRouter.scala:87:24] wire out_rimask_479 = \|_out_rimask_T_479; // @[RegisterRouter.scala:87:24] wire out_wimask_479 = &_out_wimask_T_479; // @[RegisterRouter.scala:87:24] wire out_romask_479 = \|_out_romask_T_479; // @[RegisterRouter.scala:87:24] wire out_womask_479 = &_out_womask_T_479; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_479 = out_rivalid_1_333 & out_rimask_479; // @[RegisterRouter.scala:87:24] wire _out_T_4956 = out_f_rivalid_479; // @[RegisterRouter.scala:87:24] wire out_f_roready_479 = out_roready_1_333 & out_romask_479; // @[RegisterRouter.scala:87:24] wire _out_T_4957 = out_f_roready_479; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_479 = out_wivalid_1_333 & out_wimask_479; // @[RegisterRouter.scala:87:24] wire out_f_woready_479 = out_woready_1_333 & out_womask_479; // @[RegisterRouter.scala:87:24] wire _out_T_4958 = ~out_rimask_479; // @[RegisterRouter.scala:87:24] wire _out_T_4959 = ~out_wimask_479; // @[RegisterRouter.scala:87:24] wire _out_T_4960 = ~out_romask_479; // @[RegisterRouter.scala:87:24] wire _out_T_4961 = ~out_womask_479; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_403 = {hi_518, flags_0_go, _out_prepend_T_403}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4962 = out_prepend_403; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4963 = _out_T_4962; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_404 = _out_T_4963; // @[RegisterRouter.scala:87:24] wire out_rimask_480 = \|_out_rimask_T_480; // @[RegisterRouter.scala:87:24] wire out_wimask_480 = &_out_wimask_T_480; // @[RegisterRouter.scala:87:24] wire out_romask_480 = \|_out_romask_T_480; // @[RegisterRouter.scala:87:24] wire out_womask_480 = &_out_womask_T_480; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_480 = out_rivalid_1_334 & out_rimask_480; // @[RegisterRouter.scala:87:24] wire _out_T_4965 = out_f_rivalid_480; // @[RegisterRouter.scala:87:24] wire out_f_roready_480 = out_roready_1_334 & out_romask_480; // @[RegisterRouter.scala:87:24] wire _out_T_4966 = out_f_roready_480; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_480 = out_wivalid_1_334 & out_wimask_480; // @[RegisterRouter.scala:87:24] wire out_f_woready_480 = out_woready_1_334 & out_womask_480; // @[RegisterRouter.scala:87:24] wire _out_T_4967 = ~out_rimask_480; // @[RegisterRouter.scala:87:24] wire _out_T_4968 = ~out_wimask_480; // @[RegisterRouter.scala:87:24] wire _out_T_4969 = ~out_romask_480; // @[RegisterRouter.scala:87:24] wire _out_T_4970 = ~out_womask_480; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_404 = {hi_519, flags_0_go, _out_prepend_T_404}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4971 = out_prepend_404; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4972 = _out_T_4971; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_405 = _out_T_4972; // @[RegisterRouter.scala:87:24] wire out_rimask_481 = \|_out_rimask_T_481; // @[RegisterRouter.scala:87:24] wire out_wimask_481 = &_out_wimask_T_481; // @[RegisterRouter.scala:87:24] wire out_romask_481 = \|_out_romask_T_481; // @[RegisterRouter.scala:87:24] wire out_womask_481 = &_out_womask_T_481; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_481 = out_rivalid_1_335 & out_rimask_481; // @[RegisterRouter.scala:87:24] wire _out_T_4974 = out_f_rivalid_481; // @[RegisterRouter.scala:87:24] wire out_f_roready_481 = out_roready_1_335 & out_romask_481; // @[RegisterRouter.scala:87:24] wire _out_T_4975 = out_f_roready_481; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_481 = out_wivalid_1_335 & out_wimask_481; // @[RegisterRouter.scala:87:24] wire out_f_woready_481 = out_woready_1_335 & out_womask_481; // @[RegisterRouter.scala:87:24] wire _out_T_4976 = ~out_rimask_481; // @[RegisterRouter.scala:87:24] wire _out_T_4977 = ~out_wimask_481; // @[RegisterRouter.scala:87:24] wire _out_T_4978 = ~out_romask_481; // @[RegisterRouter.scala:87:24] wire _out_T_4979 = ~out_womask_481; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_405 = {hi_520, flags_0_go, _out_prepend_T_405}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4980 = out_prepend_405; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4981 = _out_T_4980; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_192 = _out_T_4981; // @[MuxLiteral.scala:49:48] wire out_rimask_482 = \|_out_rimask_T_482; // @[RegisterRouter.scala:87:24] wire out_wimask_482 = &_out_wimask_T_482; // @[RegisterRouter.scala:87:24] wire out_romask_482 = \|_out_romask_T_482; // @[RegisterRouter.scala:87:24] wire out_womask_482 = &_out_womask_T_482; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_482 = out_rivalid_1_336 & out_rimask_482; // @[RegisterRouter.scala:87:24] wire _out_T_4983 = out_f_rivalid_482; // @[RegisterRouter.scala:87:24] wire out_f_roready_482 = out_roready_1_336 & out_romask_482; // @[RegisterRouter.scala:87:24] wire _out_T_4984 = out_f_roready_482; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_482 = out_wivalid_1_336 & out_wimask_482; // @[RegisterRouter.scala:87:24] wire out_f_woready_482 = out_woready_1_336 & out_womask_482; // @[RegisterRouter.scala:87:24] wire _out_T_4985 = ~out_rimask_482; // @[RegisterRouter.scala:87:24] wire _out_T_4986 = ~out_wimask_482; // @[RegisterRouter.scala:87:24] wire _out_T_4987 = ~out_romask_482; // @[RegisterRouter.scala:87:24] wire _out_T_4988 = ~out_womask_482; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4990 = _out_T_4989; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_406 = _out_T_4990; // @[RegisterRouter.scala:87:24] wire out_rimask_483 = \|_out_rimask_T_483; // @[RegisterRouter.scala:87:24] wire out_wimask_483 = &_out_wimask_T_483; // @[RegisterRouter.scala:87:24] wire out_romask_483 = \|_out_romask_T_483; // @[RegisterRouter.scala:87:24] wire out_womask_483 = &_out_womask_T_483; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_483 = out_rivalid_1_337 & out_rimask_483; // @[RegisterRouter.scala:87:24] wire _out_T_4992 = out_f_rivalid_483; // @[RegisterRouter.scala:87:24] wire out_f_roready_483 = out_roready_1_337 & out_romask_483; // @[RegisterRouter.scala:87:24] wire _out_T_4993 = out_f_roready_483; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_483 = out_wivalid_1_337 & out_wimask_483; // @[RegisterRouter.scala:87:24] wire out_f_woready_483 = out_woready_1_337 & out_womask_483; // @[RegisterRouter.scala:87:24] wire _out_T_4994 = ~out_rimask_483; // @[RegisterRouter.scala:87:24] wire _out_T_4995 = ~out_wimask_483; // @[RegisterRouter.scala:87:24] wire _out_T_4996 = ~out_romask_483; // @[RegisterRouter.scala:87:24] wire _out_T_4997 = ~out_womask_483; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_406 = {hi_74, flags_0_go, _out_prepend_T_406}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4998 = out_prepend_406; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4999 = _out_T_4998; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_407 = _out_T_4999; // @[RegisterRouter.scala:87:24] wire out_rimask_484 = \|_out_rimask_T_484; // @[RegisterRouter.scala:87:24] wire out_wimask_484 = &_out_wimask_T_484; // @[RegisterRouter.scala:87:24] wire out_romask_484 = \|_out_romask_T_484; // @[RegisterRouter.scala:87:24] wire out_womask_484 = &_out_womask_T_484; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_484 = out_rivalid_1_338 & out_rimask_484; // @[RegisterRouter.scala:87:24] wire _out_T_5001 = out_f_rivalid_484; // @[RegisterRouter.scala:87:24] wire out_f_roready_484 = out_roready_1_338 & out_romask_484; // @[RegisterRouter.scala:87:24] wire _out_T_5002 = out_f_roready_484; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_484 = out_wivalid_1_338 & out_wimask_484; // @[RegisterRouter.scala:87:24] wire out_f_woready_484 = out_woready_1_338 & out_womask_484; // @[RegisterRouter.scala:87:24] wire _out_T_5003 = ~out_rimask_484; // @[RegisterRouter.scala:87:24] wire _out_T_5004 = ~out_wimask_484; // @[RegisterRouter.scala:87:24] wire _out_T_5005 = ~out_romask_484; // @[RegisterRouter.scala:87:24] wire _out_T_5006 = ~out_womask_484; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_407 = {hi_75, flags_0_go, _out_prepend_T_407}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5007 = out_prepend_407; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5008 = _out_T_5007; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_408 = _out_T_5008; // @[RegisterRouter.scala:87:24] wire out_rimask_485 = \|_out_rimask_T_485; // @[RegisterRouter.scala:87:24] wire out_wimask_485 = &_out_wimask_T_485; // @[RegisterRouter.scala:87:24] wire out_romask_485 = \|_out_romask_T_485; // @[RegisterRouter.scala:87:24] wire out_womask_485 = &_out_womask_T_485; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_485 = out_rivalid_1_339 & out_rimask_485; // @[RegisterRouter.scala:87:24] wire _out_T_5010 = out_f_rivalid_485; // @[RegisterRouter.scala:87:24] wire out_f_roready_485 = out_roready_1_339 & out_romask_485; // @[RegisterRouter.scala:87:24] wire _out_T_5011 = out_f_roready_485; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_485 = out_wivalid_1_339 & out_wimask_485; // @[RegisterRouter.scala:87:24] wire out_f_woready_485 = out_woready_1_339 & out_womask_485; // @[RegisterRouter.scala:87:24] wire _out_T_5012 = ~out_rimask_485; // @[RegisterRouter.scala:87:24] wire _out_T_5013 = ~out_wimask_485; // @[RegisterRouter.scala:87:24] wire _out_T_5014 = ~out_romask_485; // @[RegisterRouter.scala:87:24] wire _out_T_5015 = ~out_womask_485; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_408 = {hi_76, flags_0_go, _out_prepend_T_408}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5016 = out_prepend_408; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5017 = _out_T_5016; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_409 = _out_T_5017; // @[RegisterRouter.scala:87:24] wire out_rimask_486 = \|_out_rimask_T_486; // @[RegisterRouter.scala:87:24] wire out_wimask_486 = &_out_wimask_T_486; // @[RegisterRouter.scala:87:24] wire out_romask_486 = \|_out_romask_T_486; // @[RegisterRouter.scala:87:24] wire out_womask_486 = &_out_womask_T_486; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_486 = out_rivalid_1_340 & out_rimask_486; // @[RegisterRouter.scala:87:24] wire _out_T_5019 = out_f_rivalid_486; // @[RegisterRouter.scala:87:24] wire out_f_roready_486 = out_roready_1_340 & out_romask_486; // @[RegisterRouter.scala:87:24] wire _out_T_5020 = out_f_roready_486; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_486 = out_wivalid_1_340 & out_wimask_486; // @[RegisterRouter.scala:87:24] wire out_f_woready_486 = out_woready_1_340 & out_womask_486; // @[RegisterRouter.scala:87:24] wire _out_T_5021 = ~out_rimask_486; // @[RegisterRouter.scala:87:24] wire _out_T_5022 = ~out_wimask_486; // @[RegisterRouter.scala:87:24] wire _out_T_5023 = ~out_romask_486; // @[RegisterRouter.scala:87:24] wire _out_T_5024 = ~out_womask_486; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_409 = {hi_77, flags_0_go, _out_prepend_T_409}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5025 = out_prepend_409; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5026 = _out_T_5025; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_410 = _out_T_5026; // @[RegisterRouter.scala:87:24] wire out_rimask_487 = \|_out_rimask_T_487; // @[RegisterRouter.scala:87:24] wire out_wimask_487 = &_out_wimask_T_487; // @[RegisterRouter.scala:87:24] wire out_romask_487 = \|_out_romask_T_487; // @[RegisterRouter.scala:87:24] wire out_womask_487 = &_out_womask_T_487; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_487 = out_rivalid_1_341 & out_rimask_487; // @[RegisterRouter.scala:87:24] wire _out_T_5028 = out_f_rivalid_487; // @[RegisterRouter.scala:87:24] wire out_f_roready_487 = out_roready_1_341 & out_romask_487; // @[RegisterRouter.scala:87:24] wire _out_T_5029 = out_f_roready_487; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_487 = out_wivalid_1_341 & out_wimask_487; // @[RegisterRouter.scala:87:24] wire out_f_woready_487 = out_woready_1_341 & out_womask_487; // @[RegisterRouter.scala:87:24] wire _out_T_5030 = ~out_rimask_487; // @[RegisterRouter.scala:87:24] wire _out_T_5031 = ~out_wimask_487; // @[RegisterRouter.scala:87:24] wire _out_T_5032 = ~out_romask_487; // @[RegisterRouter.scala:87:24] wire _out_T_5033 = ~out_womask_487; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_410 = {hi_78, flags_0_go, _out_prepend_T_410}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5034 = out_prepend_410; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5035 = _out_T_5034; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_411 = _out_T_5035; // @[RegisterRouter.scala:87:24] wire out_rimask_488 = \|_out_rimask_T_488; // @[RegisterRouter.scala:87:24] wire out_wimask_488 = &_out_wimask_T_488; // @[RegisterRouter.scala:87:24] wire out_romask_488 = \|_out_romask_T_488; // @[RegisterRouter.scala:87:24] wire out_womask_488 = &_out_womask_T_488; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_488 = out_rivalid_1_342 & out_rimask_488; // @[RegisterRouter.scala:87:24] wire _out_T_5037 = out_f_rivalid_488; // @[RegisterRouter.scala:87:24] wire out_f_roready_488 = out_roready_1_342 & out_romask_488; // @[RegisterRouter.scala:87:24] wire _out_T_5038 = out_f_roready_488; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_488 = out_wivalid_1_342 & out_wimask_488; // @[RegisterRouter.scala:87:24] wire out_f_woready_488 = out_woready_1_342 & out_womask_488; // @[RegisterRouter.scala:87:24] wire _out_T_5039 = ~out_rimask_488; // @[RegisterRouter.scala:87:24] wire _out_T_5040 = ~out_wimask_488; // @[RegisterRouter.scala:87:24] wire _out_T_5041 = ~out_romask_488; // @[RegisterRouter.scala:87:24] wire _out_T_5042 = ~out_womask_488; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_411 = {hi_79, flags_0_go, _out_prepend_T_411}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5043 = out_prepend_411; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5044 = _out_T_5043; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_412 = _out_T_5044; // @[RegisterRouter.scala:87:24] wire out_rimask_489 = \|_out_rimask_T_489; // @[RegisterRouter.scala:87:24] wire out_wimask_489 = &_out_wimask_T_489; // @[RegisterRouter.scala:87:24] wire out_romask_489 = \|_out_romask_T_489; // @[RegisterRouter.scala:87:24] wire out_womask_489 = &_out_womask_T_489; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_489 = out_rivalid_1_343 & out_rimask_489; // @[RegisterRouter.scala:87:24] wire _out_T_5046 = out_f_rivalid_489; // @[RegisterRouter.scala:87:24] wire out_f_roready_489 = out_roready_1_343 & out_romask_489; // @[RegisterRouter.scala:87:24] wire _out_T_5047 = out_f_roready_489; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_489 = out_wivalid_1_343 & out_wimask_489; // @[RegisterRouter.scala:87:24] wire out_f_woready_489 = out_woready_1_343 & out_womask_489; // @[RegisterRouter.scala:87:24] wire _out_T_5048 = ~out_rimask_489; // @[RegisterRouter.scala:87:24] wire _out_T_5049 = ~out_wimask_489; // @[RegisterRouter.scala:87:24] wire _out_T_5050 = ~out_romask_489; // @[RegisterRouter.scala:87:24] wire _out_T_5051 = ~out_womask_489; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_412 = {hi_80, flags_0_go, _out_prepend_T_412}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5052 = out_prepend_412; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5053 = _out_T_5052; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_137 = _out_T_5053; // @[MuxLiteral.scala:49:48] wire out_rimask_490 = \|_out_rimask_T_490; // @[RegisterRouter.scala:87:24] wire out_wimask_490 = &_out_wimask_T_490; // @[RegisterRouter.scala:87:24] wire out_romask_490 = \|_out_romask_T_490; // @[RegisterRouter.scala:87:24] wire out_womask_490 = &_out_womask_T_490; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_490 = out_rivalid_1_344 & out_rimask_490; // @[RegisterRouter.scala:87:24] wire _out_T_5055 = out_f_rivalid_490; // @[RegisterRouter.scala:87:24] wire out_f_roready_490 = out_roready_1_344 & out_romask_490; // @[RegisterRouter.scala:87:24] wire _out_T_5056 = out_f_roready_490; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_490 = out_wivalid_1_344 & out_wimask_490; // @[RegisterRouter.scala:87:24] wire out_f_woready_490 = out_woready_1_344 & out_womask_490; // @[RegisterRouter.scala:87:24] wire _out_T_5057 = ~out_rimask_490; // @[RegisterRouter.scala:87:24] wire _out_T_5058 = ~out_wimask_490; // @[RegisterRouter.scala:87:24] wire _out_T_5059 = ~out_romask_490; // @[RegisterRouter.scala:87:24] wire _out_T_5060 = ~out_womask_490; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5062 = _out_T_5061; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_413 = _out_T_5062; // @[RegisterRouter.scala:87:24] wire out_rimask_491 = \|_out_rimask_T_491; // @[RegisterRouter.scala:87:24] wire out_wimask_491 = &_out_wimask_T_491; // @[RegisterRouter.scala:87:24] wire out_romask_491 = \|_out_romask_T_491; // @[RegisterRouter.scala:87:24] wire out_womask_491 = &_out_womask_T_491; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_491 = out_rivalid_1_345 & out_rimask_491; // @[RegisterRouter.scala:87:24] wire _out_T_5064 = out_f_rivalid_491; // @[RegisterRouter.scala:87:24] wire out_f_roready_491 = out_roready_1_345 & out_romask_491; // @[RegisterRouter.scala:87:24] wire _out_T_5065 = out_f_roready_491; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_491 = out_wivalid_1_345 & out_wimask_491; // @[RegisterRouter.scala:87:24] wire out_f_woready_491 = out_woready_1_345 & out_womask_491; // @[RegisterRouter.scala:87:24] wire _out_T_5066 = ~out_rimask_491; // @[RegisterRouter.scala:87:24] wire _out_T_5067 = ~out_wimask_491; // @[RegisterRouter.scala:87:24] wire _out_T_5068 = ~out_romask_491; // @[RegisterRouter.scala:87:24] wire _out_T_5069 = ~out_womask_491; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_413 = {hi_298, flags_0_go, _out_prepend_T_413}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5070 = out_prepend_413; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5071 = _out_T_5070; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_414 = _out_T_5071; // @[RegisterRouter.scala:87:24] wire out_rimask_492 = \|_out_rimask_T_492; // @[RegisterRouter.scala:87:24] wire out_wimask_492 = &_out_wimask_T_492; // @[RegisterRouter.scala:87:24] wire out_romask_492 = \|_out_romask_T_492; // @[RegisterRouter.scala:87:24] wire out_womask_492 = &_out_womask_T_492; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_492 = out_rivalid_1_346 & out_rimask_492; // @[RegisterRouter.scala:87:24] wire _out_T_5073 = out_f_rivalid_492; // @[RegisterRouter.scala:87:24] wire out_f_roready_492 = out_roready_1_346 & out_romask_492; // @[RegisterRouter.scala:87:24] wire _out_T_5074 = out_f_roready_492; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_492 = out_wivalid_1_346 & out_wimask_492; // @[RegisterRouter.scala:87:24] wire out_f_woready_492 = out_woready_1_346 & out_womask_492; // @[RegisterRouter.scala:87:24] wire _out_T_5075 = ~out_rimask_492; // @[RegisterRouter.scala:87:24] wire _out_T_5076 = ~out_wimask_492; // @[RegisterRouter.scala:87:24] wire _out_T_5077 = ~out_romask_492; // @[RegisterRouter.scala:87:24] wire _out_T_5078 = ~out_womask_492; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_414 = {hi_299, flags_0_go, _out_prepend_T_414}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5079 = out_prepend_414; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5080 = _out_T_5079; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_415 = _out_T_5080; // @[RegisterRouter.scala:87:24] wire out_rimask_493 = \|_out_rimask_T_493; // @[RegisterRouter.scala:87:24] wire out_wimask_493 = &_out_wimask_T_493; // @[RegisterRouter.scala:87:24] wire out_romask_493 = \|_out_romask_T_493; // @[RegisterRouter.scala:87:24] wire out_womask_493 = &_out_womask_T_493; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_493 = out_rivalid_1_347 & out_rimask_493; // @[RegisterRouter.scala:87:24] wire _out_T_5082 = out_f_rivalid_493; // @[RegisterRouter.scala:87:24] wire out_f_roready_493 = out_roready_1_347 & out_romask_493; // @[RegisterRouter.scala:87:24] wire _out_T_5083 = out_f_roready_493; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_493 = out_wivalid_1_347 & out_wimask_493; // @[RegisterRouter.scala:87:24] wire out_f_woready_493 = out_woready_1_347 & out_womask_493; // @[RegisterRouter.scala:87:24] wire _out_T_5084 = ~out_rimask_493; // @[RegisterRouter.scala:87:24] wire _out_T_5085 = ~out_wimask_493; // @[RegisterRouter.scala:87:24] wire _out_T_5086 = ~out_romask_493; // @[RegisterRouter.scala:87:24] wire _out_T_5087 = ~out_womask_493; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_415 = {hi_300, flags_0_go, _out_prepend_T_415}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5088 = out_prepend_415; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5089 = _out_T_5088; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_416 = _out_T_5089; // @[RegisterRouter.scala:87:24] wire out_rimask_494 = \|_out_rimask_T_494; // @[RegisterRouter.scala:87:24] wire out_wimask_494 = &_out_wimask_T_494; // @[RegisterRouter.scala:87:24] wire out_romask_494 = \|_out_romask_T_494; // @[RegisterRouter.scala:87:24] wire out_womask_494 = &_out_womask_T_494; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_494 = out_rivalid_1_348 & out_rimask_494; // @[RegisterRouter.scala:87:24] wire _out_T_5091 = out_f_rivalid_494; // @[RegisterRouter.scala:87:24] wire out_f_roready_494 = out_roready_1_348 & out_romask_494; // @[RegisterRouter.scala:87:24] wire _out_T_5092 = out_f_roready_494; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_494 = out_wivalid_1_348 & out_wimask_494; // @[RegisterRouter.scala:87:24] wire out_f_woready_494 = out_woready_1_348 & out_womask_494; // @[RegisterRouter.scala:87:24] wire _out_T_5093 = ~out_rimask_494; // @[RegisterRouter.scala:87:24] wire _out_T_5094 = ~out_wimask_494; // @[RegisterRouter.scala:87:24] wire _out_T_5095 = ~out_romask_494; // @[RegisterRouter.scala:87:24] wire _out_T_5096 = ~out_womask_494; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_416 = {hi_301, flags_0_go, _out_prepend_T_416}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5097 = out_prepend_416; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5098 = _out_T_5097; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_417 = _out_T_5098; // @[RegisterRouter.scala:87:24] wire out_rimask_495 = \|_out_rimask_T_495; // @[RegisterRouter.scala:87:24] wire out_wimask_495 = &_out_wimask_T_495; // @[RegisterRouter.scala:87:24] wire out_romask_495 = \|_out_romask_T_495; // @[RegisterRouter.scala:87:24] wire out_womask_495 = &_out_womask_T_495; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_495 = out_rivalid_1_349 & out_rimask_495; // @[RegisterRouter.scala:87:24] wire _out_T_5100 = out_f_rivalid_495; // @[RegisterRouter.scala:87:24] wire out_f_roready_495 = out_roready_1_349 & out_romask_495; // @[RegisterRouter.scala:87:24] wire _out_T_5101 = out_f_roready_495; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_495 = out_wivalid_1_349 & out_wimask_495; // @[RegisterRouter.scala:87:24] wire out_f_woready_495 = out_woready_1_349 & out_womask_495; // @[RegisterRouter.scala:87:24] wire _out_T_5102 = ~out_rimask_495; // @[RegisterRouter.scala:87:24] wire _out_T_5103 = ~out_wimask_495; // @[RegisterRouter.scala:87:24] wire _out_T_5104 = ~out_romask_495; // @[RegisterRouter.scala:87:24] wire _out_T_5105 = ~out_womask_495; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_417 = {hi_302, flags_0_go, _out_prepend_T_417}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5106 = out_prepend_417; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5107 = _out_T_5106; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_418 = _out_T_5107; // @[RegisterRouter.scala:87:24] wire out_rimask_496 = \|_out_rimask_T_496; // @[RegisterRouter.scala:87:24] wire out_wimask_496 = &_out_wimask_T_496; // @[RegisterRouter.scala:87:24] wire out_romask_496 = \|_out_romask_T_496; // @[RegisterRouter.scala:87:24] wire out_womask_496 = &_out_womask_T_496; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_496 = out_rivalid_1_350 & out_rimask_496; // @[RegisterRouter.scala:87:24] wire _out_T_5109 = out_f_rivalid_496; // @[RegisterRouter.scala:87:24] wire out_f_roready_496 = out_roready_1_350 & out_romask_496; // @[RegisterRouter.scala:87:24] wire _out_T_5110 = out_f_roready_496; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_496 = out_wivalid_1_350 & out_wimask_496; // @[RegisterRouter.scala:87:24] wire out_f_woready_496 = out_woready_1_350 & out_womask_496; // @[RegisterRouter.scala:87:24] wire _out_T_5111 = ~out_rimask_496; // @[RegisterRouter.scala:87:24] wire _out_T_5112 = ~out_wimask_496; // @[RegisterRouter.scala:87:24] wire _out_T_5113 = ~out_romask_496; // @[RegisterRouter.scala:87:24] wire _out_T_5114 = ~out_womask_496; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_418 = {hi_303, flags_0_go, _out_prepend_T_418}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5115 = out_prepend_418; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5116 = _out_T_5115; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_419 = _out_T_5116; // @[RegisterRouter.scala:87:24] wire out_rimask_497 = \|_out_rimask_T_497; // @[RegisterRouter.scala:87:24] wire out_wimask_497 = &_out_wimask_T_497; // @[RegisterRouter.scala:87:24] wire out_romask_497 = \|_out_romask_T_497; // @[RegisterRouter.scala:87:24] wire out_womask_497 = &_out_womask_T_497; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_497 = out_rivalid_1_351 & out_rimask_497; // @[RegisterRouter.scala:87:24] wire _out_T_5118 = out_f_rivalid_497; // @[RegisterRouter.scala:87:24] wire out_f_roready_497 = out_roready_1_351 & out_romask_497; // @[RegisterRouter.scala:87:24] wire _out_T_5119 = out_f_roready_497; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_497 = out_wivalid_1_351 & out_wimask_497; // @[RegisterRouter.scala:87:24] wire out_f_woready_497 = out_woready_1_351 & out_womask_497; // @[RegisterRouter.scala:87:24] wire _out_T_5120 = ~out_rimask_497; // @[RegisterRouter.scala:87:24] wire _out_T_5121 = ~out_wimask_497; // @[RegisterRouter.scala:87:24] wire _out_T_5122 = ~out_romask_497; // @[RegisterRouter.scala:87:24] wire _out_T_5123 = ~out_womask_497; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_419 = {hi_304, flags_0_go, _out_prepend_T_419}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5124 = out_prepend_419; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5125 = _out_T_5124; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_165 = _out_T_5125; // @[MuxLiteral.scala:49:48] wire [9:0] _out_rimask_T_498 = out_frontMask_1[9:0]; // @[RegisterRouter.scala:87:24] wire [9:0] _out_wimask_T_498 = out_frontMask_1[9:0]; // @[RegisterRouter.scala:87:24] wire [9:0] _out_rimask_T_681 = out_frontMask_1[9:0]; // @[RegisterRouter.scala:87:24] wire [9:0] _out_wimask_T_681 = out_frontMask_1[9:0]; // @[RegisterRouter.scala:87:24] wire out_rimask_498 = \|_out_rimask_T_498; // @[RegisterRouter.scala:87:24] wire out_wimask_498 = &_out_wimask_T_498; // @[RegisterRouter.scala:87:24] wire [9:0] _out_romask_T_498 = out_backMask_1[9:0]; // @[RegisterRouter.scala:87:24] wire [9:0] _out_womask_T_498 = out_backMask_1[9:0]; // @[RegisterRouter.scala:87:24] wire [9:0] _out_romask_T_681 = out_backMask_1[9:0]; // @[RegisterRouter.scala:87:24] wire [9:0] _out_womask_T_681 = out_backMask_1[9:0]; // @[RegisterRouter.scala:87:24] wire out_romask_498 = \|_out_romask_T_498; // @[RegisterRouter.scala:87:24] wire out_womask_498 = &_out_womask_T_498; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_498 = out_rivalid_1_352 & out_rimask_498; // @[RegisterRouter.scala:87:24] wire out_f_roready_498 = out_roready_1_352 & out_romask_498; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_498 = out_wivalid_1_352 & out_wimask_498; // @[RegisterRouter.scala:87:24] wire _out_T_5127 = out_f_wivalid_498; // @[RegisterRouter.scala:87:24] assign out_f_woready_498 = out_woready_1_352 & out_womask_498; // @[RegisterRouter.scala:87:24] assign hartResumingWrEn = out_f_woready_498; // @[RegisterRouter.scala:87:24] wire _out_T_5128 = out_f_woready_498; // @[RegisterRouter.scala:87:24] assign _out_T_5126 = out_front_1_bits_data[9:0]; // @[RegisterRouter.scala:87:24] assign _out_T_6805 = out_front_1_bits_data[9:0]; // @[RegisterRouter.scala:87:24] assign hartResumingId = _out_T_5126; // @[RegisterRouter.scala:87:24] wire _out_T_5129 = ~out_rimask_498; // @[RegisterRouter.scala:87:24] wire _out_T_5130 = ~out_wimask_498; // @[RegisterRouter.scala:87:24] wire _out_T_5131 = ~out_romask_498; // @[RegisterRouter.scala:87:24] wire _out_T_5132 = ~out_womask_498; // @[RegisterRouter.scala:87:24] wire [9:0] _out_rimask_T_499 = out_frontMask_1[41:32]; // @[RegisterRouter.scala:87:24] wire [9:0] _out_wimask_T_499 = out_frontMask_1[41:32]; // @[RegisterRouter.scala:87:24] wire [9:0] _out_rimask_T_682 = out_frontMask_1[41:32]; // @[RegisterRouter.scala:87:24] wire [9:0] _out_wimask_T_682 = out_frontMask_1[41:32]; // @[RegisterRouter.scala:87:24] wire out_rimask_499 = \|_out_rimask_T_499; // @[RegisterRouter.scala:87:24] wire out_wimask_499 = &_out_wimask_T_499; // @[RegisterRouter.scala:87:24] wire [9:0] _out_romask_T_499 = out_backMask_1[41:32]; // @[RegisterRouter.scala:87:24] wire [9:0] _out_womask_T_499 = out_backMask_1[41:32]; // @[RegisterRouter.scala:87:24] wire [9:0] _out_romask_T_682 = out_backMask_1[41:32]; // @[RegisterRouter.scala:87:24] wire [9:0] _out_womask_T_682 = out_backMask_1[41:32]; // @[RegisterRouter.scala:87:24] wire out_romask_499 = \|_out_romask_T_499; // @[RegisterRouter.scala:87:24] wire out_womask_499 = &_out_womask_T_499; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_499 = out_rivalid_1_353 & out_rimask_499; // @[RegisterRouter.scala:87:24] wire out_f_roready_499 = out_roready_1_353 & out_romask_499; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_499 = out_wivalid_1_353 & out_wimask_499; // @[RegisterRouter.scala:87:24] wire _out_T_5136 = out_f_wivalid_499; // @[RegisterRouter.scala:87:24] assign out_f_woready_499 = out_woready_1_353 & out_womask_499; // @[RegisterRouter.scala:87:24] assign hartExceptionWrEn = out_f_woready_499; // @[RegisterRouter.scala:87:24] wire _out_T_5137 = out_f_woready_499; // @[RegisterRouter.scala:87:24] assign _out_T_5135 = out_front_1_bits_data[41:32]; // @[RegisterRouter.scala:87:24] assign _out_T_6814 = out_front_1_bits_data[41:32]; // @[RegisterRouter.scala:87:24] assign hartExceptionId = _out_T_5135; // @[RegisterRouter.scala:87:24] wire _out_T_5138 = ~out_rimask_499; // @[RegisterRouter.scala:87:24] wire _out_T_5139 = ~out_wimask_499; // @[RegisterRouter.scala:87:24] wire _out_T_5140 = ~out_romask_499; // @[RegisterRouter.scala:87:24] wire _out_T_5141 = ~out_womask_499; // @[RegisterRouter.scala:87:24] wire out_rimask_500 = \|_out_rimask_T_500; // @[RegisterRouter.scala:87:24] wire out_wimask_500 = &_out_wimask_T_500; // @[RegisterRouter.scala:87:24] wire out_romask_500 = \|_out_romask_T_500; // @[RegisterRouter.scala:87:24] wire out_womask_500 = &_out_womask_T_500; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_500 = out_rivalid_1_354 & out_rimask_500; // @[RegisterRouter.scala:87:24] wire _out_T_5145 = out_f_rivalid_500; // @[RegisterRouter.scala:87:24] wire out_f_roready_500 = out_roready_1_354 & out_romask_500; // @[RegisterRouter.scala:87:24] wire _out_T_5146 = out_f_roready_500; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_500 = out_wivalid_1_354 & out_wimask_500; // @[RegisterRouter.scala:87:24] wire out_f_woready_500 = out_woready_1_354 & out_womask_500; // @[RegisterRouter.scala:87:24] wire _out_T_5147 = ~out_rimask_500; // @[RegisterRouter.scala:87:24] wire _out_T_5148 = ~out_wimask_500; // @[RegisterRouter.scala:87:24] wire _out_T_5149 = ~out_romask_500; // @[RegisterRouter.scala:87:24] wire _out_T_5150 = ~out_womask_500; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5152 = _out_T_5151; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_421 = _out_T_5152; // @[RegisterRouter.scala:87:24] wire out_rimask_501 = \|_out_rimask_T_501; // @[RegisterRouter.scala:87:24] wire out_wimask_501 = &_out_wimask_T_501; // @[RegisterRouter.scala:87:24] wire out_romask_501 = \|_out_romask_T_501; // @[RegisterRouter.scala:87:24] wire out_womask_501 = &_out_womask_T_501; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_501 = out_rivalid_1_355 & out_rimask_501; // @[RegisterRouter.scala:87:24] wire _out_T_5154 = out_f_rivalid_501; // @[RegisterRouter.scala:87:24] wire out_f_roready_501 = out_roready_1_355 & out_romask_501; // @[RegisterRouter.scala:87:24] wire _out_T_5155 = out_f_roready_501; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_501 = out_wivalid_1_355 & out_wimask_501; // @[RegisterRouter.scala:87:24] wire out_f_woready_501 = out_woready_1_355 & out_womask_501; // @[RegisterRouter.scala:87:24] wire _out_T_5156 = ~out_rimask_501; // @[RegisterRouter.scala:87:24] wire _out_T_5157 = ~out_wimask_501; // @[RegisterRouter.scala:87:24] wire _out_T_5158 = ~out_romask_501; // @[RegisterRouter.scala:87:24] wire _out_T_5159 = ~out_womask_501; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_421 = {hi_810, flags_0_go, _out_prepend_T_421}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5160 = out_prepend_421; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5161 = _out_T_5160; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_422 = _out_T_5161; // @[RegisterRouter.scala:87:24] wire out_rimask_502 = \|_out_rimask_T_502; // @[RegisterRouter.scala:87:24] wire out_wimask_502 = &_out_wimask_T_502; // @[RegisterRouter.scala:87:24] wire out_romask_502 = \|_out_romask_T_502; // @[RegisterRouter.scala:87:24] wire out_womask_502 = &_out_womask_T_502; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_502 = out_rivalid_1_356 & out_rimask_502; // @[RegisterRouter.scala:87:24] wire _out_T_5163 = out_f_rivalid_502; // @[RegisterRouter.scala:87:24] wire out_f_roready_502 = out_roready_1_356 & out_romask_502; // @[RegisterRouter.scala:87:24] wire _out_T_5164 = out_f_roready_502; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_502 = out_wivalid_1_356 & out_wimask_502; // @[RegisterRouter.scala:87:24] wire out_f_woready_502 = out_woready_1_356 & out_womask_502; // @[RegisterRouter.scala:87:24] wire _out_T_5165 = ~out_rimask_502; // @[RegisterRouter.scala:87:24] wire _out_T_5166 = ~out_wimask_502; // @[RegisterRouter.scala:87:24] wire _out_T_5167 = ~out_romask_502; // @[RegisterRouter.scala:87:24] wire _out_T_5168 = ~out_womask_502; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_422 = {hi_811, flags_0_go, _out_prepend_T_422}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5169 = out_prepend_422; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5170 = _out_T_5169; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_423 = _out_T_5170; // @[RegisterRouter.scala:87:24] wire out_rimask_503 = \|_out_rimask_T_503; // @[RegisterRouter.scala:87:24] wire out_wimask_503 = &_out_wimask_T_503; // @[RegisterRouter.scala:87:24] wire out_romask_503 = \|_out_romask_T_503; // @[RegisterRouter.scala:87:24] wire out_womask_503 = &_out_womask_T_503; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_503 = out_rivalid_1_357 & out_rimask_503; // @[RegisterRouter.scala:87:24] wire _out_T_5172 = out_f_rivalid_503; // @[RegisterRouter.scala:87:24] wire out_f_roready_503 = out_roready_1_357 & out_romask_503; // @[RegisterRouter.scala:87:24] wire _out_T_5173 = out_f_roready_503; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_503 = out_wivalid_1_357 & out_wimask_503; // @[RegisterRouter.scala:87:24] wire out_f_woready_503 = out_woready_1_357 & out_womask_503; // @[RegisterRouter.scala:87:24] wire _out_T_5174 = ~out_rimask_503; // @[RegisterRouter.scala:87:24] wire _out_T_5175 = ~out_wimask_503; // @[RegisterRouter.scala:87:24] wire _out_T_5176 = ~out_romask_503; // @[RegisterRouter.scala:87:24] wire _out_T_5177 = ~out_womask_503; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_423 = {hi_812, flags_0_go, _out_prepend_T_423}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5178 = out_prepend_423; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5179 = _out_T_5178; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_424 = _out_T_5179; // @[RegisterRouter.scala:87:24] wire out_rimask_504 = \|_out_rimask_T_504; // @[RegisterRouter.scala:87:24] wire out_wimask_504 = &_out_wimask_T_504; // @[RegisterRouter.scala:87:24] wire out_romask_504 = \|_out_romask_T_504; // @[RegisterRouter.scala:87:24] wire out_womask_504 = &_out_womask_T_504; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_504 = out_rivalid_1_358 & out_rimask_504; // @[RegisterRouter.scala:87:24] wire _out_T_5181 = out_f_rivalid_504; // @[RegisterRouter.scala:87:24] wire out_f_roready_504 = out_roready_1_358 & out_romask_504; // @[RegisterRouter.scala:87:24] wire _out_T_5182 = out_f_roready_504; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_504 = out_wivalid_1_358 & out_wimask_504; // @[RegisterRouter.scala:87:24] wire out_f_woready_504 = out_woready_1_358 & out_womask_504; // @[RegisterRouter.scala:87:24] wire _out_T_5183 = ~out_rimask_504; // @[RegisterRouter.scala:87:24] wire _out_T_5184 = ~out_wimask_504; // @[RegisterRouter.scala:87:24] wire _out_T_5185 = ~out_romask_504; // @[RegisterRouter.scala:87:24] wire _out_T_5186 = ~out_womask_504; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_424 = {hi_813, flags_0_go, _out_prepend_T_424}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5187 = out_prepend_424; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5188 = _out_T_5187; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_425 = _out_T_5188; // @[RegisterRouter.scala:87:24] wire out_rimask_505 = \|_out_rimask_T_505; // @[RegisterRouter.scala:87:24] wire out_wimask_505 = &_out_wimask_T_505; // @[RegisterRouter.scala:87:24] wire out_romask_505 = \|_out_romask_T_505; // @[RegisterRouter.scala:87:24] wire out_womask_505 = &_out_womask_T_505; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_505 = out_rivalid_1_359 & out_rimask_505; // @[RegisterRouter.scala:87:24] wire _out_T_5190 = out_f_rivalid_505; // @[RegisterRouter.scala:87:24] wire out_f_roready_505 = out_roready_1_359 & out_romask_505; // @[RegisterRouter.scala:87:24] wire _out_T_5191 = out_f_roready_505; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_505 = out_wivalid_1_359 & out_wimask_505; // @[RegisterRouter.scala:87:24] wire out_f_woready_505 = out_woready_1_359 & out_womask_505; // @[RegisterRouter.scala:87:24] wire _out_T_5192 = ~out_rimask_505; // @[RegisterRouter.scala:87:24] wire _out_T_5193 = ~out_wimask_505; // @[RegisterRouter.scala:87:24] wire _out_T_5194 = ~out_romask_505; // @[RegisterRouter.scala:87:24] wire _out_T_5195 = ~out_womask_505; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_425 = {hi_814, flags_0_go, _out_prepend_T_425}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5196 = out_prepend_425; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5197 = _out_T_5196; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_426 = _out_T_5197; // @[RegisterRouter.scala:87:24] wire out_rimask_506 = \|_out_rimask_T_506; // @[RegisterRouter.scala:87:24] wire out_wimask_506 = &_out_wimask_T_506; // @[RegisterRouter.scala:87:24] wire out_romask_506 = \|_out_romask_T_506; // @[RegisterRouter.scala:87:24] wire out_womask_506 = &_out_womask_T_506; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_506 = out_rivalid_1_360 & out_rimask_506; // @[RegisterRouter.scala:87:24] wire _out_T_5199 = out_f_rivalid_506; // @[RegisterRouter.scala:87:24] wire out_f_roready_506 = out_roready_1_360 & out_romask_506; // @[RegisterRouter.scala:87:24] wire _out_T_5200 = out_f_roready_506; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_506 = out_wivalid_1_360 & out_wimask_506; // @[RegisterRouter.scala:87:24] wire out_f_woready_506 = out_woready_1_360 & out_womask_506; // @[RegisterRouter.scala:87:24] wire _out_T_5201 = ~out_rimask_506; // @[RegisterRouter.scala:87:24] wire _out_T_5202 = ~out_wimask_506; // @[RegisterRouter.scala:87:24] wire _out_T_5203 = ~out_romask_506; // @[RegisterRouter.scala:87:24] wire _out_T_5204 = ~out_womask_506; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_426 = {hi_815, flags_0_go, _out_prepend_T_426}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5205 = out_prepend_426; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5206 = _out_T_5205; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_427 = _out_T_5206; // @[RegisterRouter.scala:87:24] wire out_rimask_507 = \|_out_rimask_T_507; // @[RegisterRouter.scala:87:24] wire out_wimask_507 = &_out_wimask_T_507; // @[RegisterRouter.scala:87:24] wire out_romask_507 = \|_out_romask_T_507; // @[RegisterRouter.scala:87:24] wire out_womask_507 = &_out_womask_T_507; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_507 = out_rivalid_1_361 & out_rimask_507; // @[RegisterRouter.scala:87:24] wire _out_T_5208 = out_f_rivalid_507; // @[RegisterRouter.scala:87:24] wire out_f_roready_507 = out_roready_1_361 & out_romask_507; // @[RegisterRouter.scala:87:24] wire _out_T_5209 = out_f_roready_507; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_507 = out_wivalid_1_361 & out_wimask_507; // @[RegisterRouter.scala:87:24] wire out_f_woready_507 = out_woready_1_361 & out_womask_507; // @[RegisterRouter.scala:87:24] wire _out_T_5210 = ~out_rimask_507; // @[RegisterRouter.scala:87:24] wire _out_T_5211 = ~out_wimask_507; // @[RegisterRouter.scala:87:24] wire _out_T_5212 = ~out_romask_507; // @[RegisterRouter.scala:87:24] wire _out_T_5213 = ~out_womask_507; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_427 = {hi_816, flags_0_go, _out_prepend_T_427}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5214 = out_prepend_427; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5215 = _out_T_5214; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_229 = _out_T_5215; // @[MuxLiteral.scala:49:48] wire out_rimask_508 = \|_out_rimask_T_508; // @[RegisterRouter.scala:87:24] wire out_wimask_508 = &_out_wimask_T_508; // @[RegisterRouter.scala:87:24] wire out_romask_508 = \|_out_romask_T_508; // @[RegisterRouter.scala:87:24] wire out_womask_508 = &_out_womask_T_508; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_508 = out_rivalid_1_362 & out_rimask_508; // @[RegisterRouter.scala:87:24] wire _out_T_5217 = out_f_rivalid_508; // @[RegisterRouter.scala:87:24] wire out_f_roready_508 = out_roready_1_362 & out_romask_508; // @[RegisterRouter.scala:87:24] wire _out_T_5218 = out_f_roready_508; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_508 = out_wivalid_1_362 & out_wimask_508; // @[RegisterRouter.scala:87:24] wire out_f_woready_508 = out_woready_1_362 & out_womask_508; // @[RegisterRouter.scala:87:24] wire _out_T_5219 = ~out_rimask_508; // @[RegisterRouter.scala:87:24] wire _out_T_5220 = ~out_wimask_508; // @[RegisterRouter.scala:87:24] wire _out_T_5221 = ~out_romask_508; // @[RegisterRouter.scala:87:24] wire _out_T_5222 = ~out_womask_508; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5224 = _out_T_5223; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_428 = _out_T_5224; // @[RegisterRouter.scala:87:24] wire out_rimask_509 = \|_out_rimask_T_509; // @[RegisterRouter.scala:87:24] wire out_wimask_509 = &_out_wimask_T_509; // @[RegisterRouter.scala:87:24] wire out_romask_509 = \|_out_romask_T_509; // @[RegisterRouter.scala:87:24] wire out_womask_509 = &_out_womask_T_509; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_509 = out_rivalid_1_363 & out_rimask_509; // @[RegisterRouter.scala:87:24] wire _out_T_5226 = out_f_rivalid_509; // @[RegisterRouter.scala:87:24] wire out_f_roready_509 = out_roready_1_363 & out_romask_509; // @[RegisterRouter.scala:87:24] wire _out_T_5227 = out_f_roready_509; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_509 = out_wivalid_1_363 & out_wimask_509; // @[RegisterRouter.scala:87:24] wire out_f_woready_509 = out_woready_1_363 & out_womask_509; // @[RegisterRouter.scala:87:24] wire _out_T_5228 = ~out_rimask_509; // @[RegisterRouter.scala:87:24] wire _out_T_5229 = ~out_wimask_509; // @[RegisterRouter.scala:87:24] wire _out_T_5230 = ~out_romask_509; // @[RegisterRouter.scala:87:24] wire _out_T_5231 = ~out_womask_509; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_428 = {hi_994, flags_0_go, _out_prepend_T_428}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5232 = out_prepend_428; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5233 = _out_T_5232; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_429 = _out_T_5233; // @[RegisterRouter.scala:87:24] wire out_rimask_510 = \|_out_rimask_T_510; // @[RegisterRouter.scala:87:24] wire out_wimask_510 = &_out_wimask_T_510; // @[RegisterRouter.scala:87:24] wire out_romask_510 = \|_out_romask_T_510; // @[RegisterRouter.scala:87:24] wire out_womask_510 = &_out_womask_T_510; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_510 = out_rivalid_1_364 & out_rimask_510; // @[RegisterRouter.scala:87:24] wire _out_T_5235 = out_f_rivalid_510; // @[RegisterRouter.scala:87:24] wire out_f_roready_510 = out_roready_1_364 & out_romask_510; // @[RegisterRouter.scala:87:24] wire _out_T_5236 = out_f_roready_510; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_510 = out_wivalid_1_364 & out_wimask_510; // @[RegisterRouter.scala:87:24] wire out_f_woready_510 = out_woready_1_364 & out_womask_510; // @[RegisterRouter.scala:87:24] wire _out_T_5237 = ~out_rimask_510; // @[RegisterRouter.scala:87:24] wire _out_T_5238 = ~out_wimask_510; // @[RegisterRouter.scala:87:24] wire _out_T_5239 = ~out_romask_510; // @[RegisterRouter.scala:87:24] wire _out_T_5240 = ~out_womask_510; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_429 = {hi_995, flags_0_go, _out_prepend_T_429}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5241 = out_prepend_429; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5242 = _out_T_5241; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_430 = _out_T_5242; // @[RegisterRouter.scala:87:24] wire out_rimask_511 = \|_out_rimask_T_511; // @[RegisterRouter.scala:87:24] wire out_wimask_511 = &_out_wimask_T_511; // @[RegisterRouter.scala:87:24] wire out_romask_511 = \|_out_romask_T_511; // @[RegisterRouter.scala:87:24] wire out_womask_511 = &_out_womask_T_511; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_511 = out_rivalid_1_365 & out_rimask_511; // @[RegisterRouter.scala:87:24] wire _out_T_5244 = out_f_rivalid_511; // @[RegisterRouter.scala:87:24] wire out_f_roready_511 = out_roready_1_365 & out_romask_511; // @[RegisterRouter.scala:87:24] wire _out_T_5245 = out_f_roready_511; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_511 = out_wivalid_1_365 & out_wimask_511; // @[RegisterRouter.scala:87:24] wire out_f_woready_511 = out_woready_1_365 & out_womask_511; // @[RegisterRouter.scala:87:24] wire _out_T_5246 = ~out_rimask_511; // @[RegisterRouter.scala:87:24] wire _out_T_5247 = ~out_wimask_511; // @[RegisterRouter.scala:87:24] wire _out_T_5248 = ~out_romask_511; // @[RegisterRouter.scala:87:24] wire _out_T_5249 = ~out_womask_511; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_430 = {hi_996, flags_0_go, _out_prepend_T_430}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5250 = out_prepend_430; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5251 = _out_T_5250; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_431 = _out_T_5251; // @[RegisterRouter.scala:87:24] wire out_rimask_512 = \|_out_rimask_T_512; // @[RegisterRouter.scala:87:24] wire out_wimask_512 = &_out_wimask_T_512; // @[RegisterRouter.scala:87:24] wire out_romask_512 = \|_out_romask_T_512; // @[RegisterRouter.scala:87:24] wire out_womask_512 = &_out_womask_T_512; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_512 = out_rivalid_1_366 & out_rimask_512; // @[RegisterRouter.scala:87:24] wire _out_T_5253 = out_f_rivalid_512; // @[RegisterRouter.scala:87:24] wire out_f_roready_512 = out_roready_1_366 & out_romask_512; // @[RegisterRouter.scala:87:24] wire _out_T_5254 = out_f_roready_512; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_512 = out_wivalid_1_366 & out_wimask_512; // @[RegisterRouter.scala:87:24] wire out_f_woready_512 = out_woready_1_366 & out_womask_512; // @[RegisterRouter.scala:87:24] wire _out_T_5255 = ~out_rimask_512; // @[RegisterRouter.scala:87:24] wire _out_T_5256 = ~out_wimask_512; // @[RegisterRouter.scala:87:24] wire _out_T_5257 = ~out_romask_512; // @[RegisterRouter.scala:87:24] wire _out_T_5258 = ~out_womask_512; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_431 = {hi_997, flags_0_go, _out_prepend_T_431}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5259 = out_prepend_431; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5260 = _out_T_5259; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_432 = _out_T_5260; // @[RegisterRouter.scala:87:24] wire out_rimask_513 = \|_out_rimask_T_513; // @[RegisterRouter.scala:87:24] wire out_wimask_513 = &_out_wimask_T_513; // @[RegisterRouter.scala:87:24] wire out_romask_513 = \|_out_romask_T_513; // @[RegisterRouter.scala:87:24] wire out_womask_513 = &_out_womask_T_513; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_513 = out_rivalid_1_367 & out_rimask_513; // @[RegisterRouter.scala:87:24] wire _out_T_5262 = out_f_rivalid_513; // @[RegisterRouter.scala:87:24] wire out_f_roready_513 = out_roready_1_367 & out_romask_513; // @[RegisterRouter.scala:87:24] wire _out_T_5263 = out_f_roready_513; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_513 = out_wivalid_1_367 & out_wimask_513; // @[RegisterRouter.scala:87:24] wire out_f_woready_513 = out_woready_1_367 & out_womask_513; // @[RegisterRouter.scala:87:24] wire _out_T_5264 = ~out_rimask_513; // @[RegisterRouter.scala:87:24] wire _out_T_5265 = ~out_wimask_513; // @[RegisterRouter.scala:87:24] wire _out_T_5266 = ~out_romask_513; // @[RegisterRouter.scala:87:24] wire _out_T_5267 = ~out_womask_513; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_432 = {hi_998, flags_0_go, _out_prepend_T_432}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5268 = out_prepend_432; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5269 = _out_T_5268; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_433 = _out_T_5269; // @[RegisterRouter.scala:87:24] wire out_rimask_514 = \|_out_rimask_T_514; // @[RegisterRouter.scala:87:24] wire out_wimask_514 = &_out_wimask_T_514; // @[RegisterRouter.scala:87:24] wire out_romask_514 = \|_out_romask_T_514; // @[RegisterRouter.scala:87:24] wire out_womask_514 = &_out_womask_T_514; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_514 = out_rivalid_1_368 & out_rimask_514; // @[RegisterRouter.scala:87:24] wire _out_T_5271 = out_f_rivalid_514; // @[RegisterRouter.scala:87:24] wire out_f_roready_514 = out_roready_1_368 & out_romask_514; // @[RegisterRouter.scala:87:24] wire _out_T_5272 = out_f_roready_514; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_514 = out_wivalid_1_368 & out_wimask_514; // @[RegisterRouter.scala:87:24] wire out_f_woready_514 = out_woready_1_368 & out_womask_514; // @[RegisterRouter.scala:87:24] wire _out_T_5273 = ~out_rimask_514; // @[RegisterRouter.scala:87:24] wire _out_T_5274 = ~out_wimask_514; // @[RegisterRouter.scala:87:24] wire _out_T_5275 = ~out_romask_514; // @[RegisterRouter.scala:87:24] wire _out_T_5276 = ~out_womask_514; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_433 = {hi_999, flags_0_go, _out_prepend_T_433}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5277 = out_prepend_433; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5278 = _out_T_5277; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_434 = _out_T_5278; // @[RegisterRouter.scala:87:24] wire out_rimask_515 = \|_out_rimask_T_515; // @[RegisterRouter.scala:87:24] wire out_wimask_515 = &_out_wimask_T_515; // @[RegisterRouter.scala:87:24] wire out_romask_515 = \|_out_romask_T_515; // @[RegisterRouter.scala:87:24] wire out_womask_515 = &_out_womask_T_515; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_515 = out_rivalid_1_369 & out_rimask_515; // @[RegisterRouter.scala:87:24] wire _out_T_5280 = out_f_rivalid_515; // @[RegisterRouter.scala:87:24] wire out_f_roready_515 = out_roready_1_369 & out_romask_515; // @[RegisterRouter.scala:87:24] wire _out_T_5281 = out_f_roready_515; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_515 = out_wivalid_1_369 & out_wimask_515; // @[RegisterRouter.scala:87:24] wire out_f_woready_515 = out_woready_1_369 & out_womask_515; // @[RegisterRouter.scala:87:24] wire _out_T_5282 = ~out_rimask_515; // @[RegisterRouter.scala:87:24] wire _out_T_5283 = ~out_wimask_515; // @[RegisterRouter.scala:87:24] wire _out_T_5284 = ~out_romask_515; // @[RegisterRouter.scala:87:24] wire _out_T_5285 = ~out_womask_515; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_434 = {hi_1000, flags_0_go, _out_prepend_T_434}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5286 = out_prepend_434; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5287 = _out_T_5286; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_252 = _out_T_5287; // @[MuxLiteral.scala:49:48] wire out_rimask_516 = \|_out_rimask_T_516; // @[RegisterRouter.scala:87:24] wire out_wimask_516 = &_out_wimask_T_516; // @[RegisterRouter.scala:87:24] wire out_romask_516 = \|_out_romask_T_516; // @[RegisterRouter.scala:87:24] wire out_womask_516 = &_out_womask_T_516; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_516 = out_rivalid_1_370 & out_rimask_516; // @[RegisterRouter.scala:87:24] wire _out_T_5289 = out_f_rivalid_516; // @[RegisterRouter.scala:87:24] wire out_f_roready_516 = out_roready_1_370 & out_romask_516; // @[RegisterRouter.scala:87:24] wire _out_T_5290 = out_f_roready_516; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_516 = out_wivalid_1_370 & out_wimask_516; // @[RegisterRouter.scala:87:24] wire out_f_woready_516 = out_woready_1_370 & out_womask_516; // @[RegisterRouter.scala:87:24] wire _out_T_5291 = ~out_rimask_516; // @[RegisterRouter.scala:87:24] wire _out_T_5292 = ~out_wimask_516; // @[RegisterRouter.scala:87:24] wire _out_T_5293 = ~out_romask_516; // @[RegisterRouter.scala:87:24] wire _out_T_5294 = ~out_womask_516; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5296 = _out_T_5295; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_435 = _out_T_5296; // @[RegisterRouter.scala:87:24] wire out_rimask_517 = \|_out_rimask_T_517; // @[RegisterRouter.scala:87:24] wire out_wimask_517 = &_out_wimask_T_517; // @[RegisterRouter.scala:87:24] wire out_romask_517 = \|_out_romask_T_517; // @[RegisterRouter.scala:87:24] wire out_womask_517 = &_out_womask_T_517; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_517 = out_rivalid_1_371 & out_rimask_517; // @[RegisterRouter.scala:87:24] wire _out_T_5298 = out_f_rivalid_517; // @[RegisterRouter.scala:87:24] wire out_f_roready_517 = out_roready_1_371 & out_romask_517; // @[RegisterRouter.scala:87:24] wire _out_T_5299 = out_f_roready_517; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_517 = out_wivalid_1_371 & out_wimask_517; // @[RegisterRouter.scala:87:24] wire out_f_woready_517 = out_woready_1_371 & out_womask_517; // @[RegisterRouter.scala:87:24] wire _out_T_5300 = ~out_rimask_517; // @[RegisterRouter.scala:87:24] wire _out_T_5301 = ~out_wimask_517; // @[RegisterRouter.scala:87:24] wire _out_T_5302 = ~out_romask_517; // @[RegisterRouter.scala:87:24] wire _out_T_5303 = ~out_womask_517; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_435 = {hi_554, flags_0_go, _out_prepend_T_435}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5304 = out_prepend_435; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5305 = _out_T_5304; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_436 = _out_T_5305; // @[RegisterRouter.scala:87:24] wire out_rimask_518 = \|_out_rimask_T_518; // @[RegisterRouter.scala:87:24] wire out_wimask_518 = &_out_wimask_T_518; // @[RegisterRouter.scala:87:24] wire out_romask_518 = \|_out_romask_T_518; // @[RegisterRouter.scala:87:24] wire out_womask_518 = &_out_womask_T_518; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_518 = out_rivalid_1_372 & out_rimask_518; // @[RegisterRouter.scala:87:24] wire _out_T_5307 = out_f_rivalid_518; // @[RegisterRouter.scala:87:24] wire out_f_roready_518 = out_roready_1_372 & out_romask_518; // @[RegisterRouter.scala:87:24] wire _out_T_5308 = out_f_roready_518; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_518 = out_wivalid_1_372 & out_wimask_518; // @[RegisterRouter.scala:87:24] wire out_f_woready_518 = out_woready_1_372 & out_womask_518; // @[RegisterRouter.scala:87:24] wire _out_T_5309 = ~out_rimask_518; // @[RegisterRouter.scala:87:24] wire _out_T_5310 = ~out_wimask_518; // @[RegisterRouter.scala:87:24] wire _out_T_5311 = ~out_romask_518; // @[RegisterRouter.scala:87:24] wire _out_T_5312 = ~out_womask_518; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_436 = {hi_555, flags_0_go, _out_prepend_T_436}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5313 = out_prepend_436; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5314 = _out_T_5313; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_437 = _out_T_5314; // @[RegisterRouter.scala:87:24] wire out_rimask_519 = \|_out_rimask_T_519; // @[RegisterRouter.scala:87:24] wire out_wimask_519 = &_out_wimask_T_519; // @[RegisterRouter.scala:87:24] wire out_romask_519 = \|_out_romask_T_519; // @[RegisterRouter.scala:87:24] wire out_womask_519 = &_out_womask_T_519; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_519 = out_rivalid_1_373 & out_rimask_519; // @[RegisterRouter.scala:87:24] wire _out_T_5316 = out_f_rivalid_519; // @[RegisterRouter.scala:87:24] wire out_f_roready_519 = out_roready_1_373 & out_romask_519; // @[RegisterRouter.scala:87:24] wire _out_T_5317 = out_f_roready_519; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_519 = out_wivalid_1_373 & out_wimask_519; // @[RegisterRouter.scala:87:24] wire out_f_woready_519 = out_woready_1_373 & out_womask_519; // @[RegisterRouter.scala:87:24] wire _out_T_5318 = ~out_rimask_519; // @[RegisterRouter.scala:87:24] wire _out_T_5319 = ~out_wimask_519; // @[RegisterRouter.scala:87:24] wire _out_T_5320 = ~out_romask_519; // @[RegisterRouter.scala:87:24] wire _out_T_5321 = ~out_womask_519; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_437 = {hi_556, flags_0_go, _out_prepend_T_437}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5322 = out_prepend_437; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5323 = _out_T_5322; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_438 = _out_T_5323; // @[RegisterRouter.scala:87:24] wire out_rimask_520 = \|_out_rimask_T_520; // @[RegisterRouter.scala:87:24] wire out_wimask_520 = &_out_wimask_T_520; // @[RegisterRouter.scala:87:24] wire out_romask_520 = \|_out_romask_T_520; // @[RegisterRouter.scala:87:24] wire out_womask_520 = &_out_womask_T_520; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_520 = out_rivalid_1_374 & out_rimask_520; // @[RegisterRouter.scala:87:24] wire _out_T_5325 = out_f_rivalid_520; // @[RegisterRouter.scala:87:24] wire out_f_roready_520 = out_roready_1_374 & out_romask_520; // @[RegisterRouter.scala:87:24] wire _out_T_5326 = out_f_roready_520; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_520 = out_wivalid_1_374 & out_wimask_520; // @[RegisterRouter.scala:87:24] wire out_f_woready_520 = out_woready_1_374 & out_womask_520; // @[RegisterRouter.scala:87:24] wire _out_T_5327 = ~out_rimask_520; // @[RegisterRouter.scala:87:24] wire _out_T_5328 = ~out_wimask_520; // @[RegisterRouter.scala:87:24] wire _out_T_5329 = ~out_romask_520; // @[RegisterRouter.scala:87:24] wire _out_T_5330 = ~out_womask_520; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_438 = {hi_557, flags_0_go, _out_prepend_T_438}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5331 = out_prepend_438; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5332 = _out_T_5331; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_439 = _out_T_5332; // @[RegisterRouter.scala:87:24] wire out_rimask_521 = \|_out_rimask_T_521; // @[RegisterRouter.scala:87:24] wire out_wimask_521 = &_out_wimask_T_521; // @[RegisterRouter.scala:87:24] wire out_romask_521 = \|_out_romask_T_521; // @[RegisterRouter.scala:87:24] wire out_womask_521 = &_out_womask_T_521; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_521 = out_rivalid_1_375 & out_rimask_521; // @[RegisterRouter.scala:87:24] wire _out_T_5334 = out_f_rivalid_521; // @[RegisterRouter.scala:87:24] wire out_f_roready_521 = out_roready_1_375 & out_romask_521; // @[RegisterRouter.scala:87:24] wire _out_T_5335 = out_f_roready_521; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_521 = out_wivalid_1_375 & out_wimask_521; // @[RegisterRouter.scala:87:24] wire out_f_woready_521 = out_woready_1_375 & out_womask_521; // @[RegisterRouter.scala:87:24] wire _out_T_5336 = ~out_rimask_521; // @[RegisterRouter.scala:87:24] wire _out_T_5337 = ~out_wimask_521; // @[RegisterRouter.scala:87:24] wire _out_T_5338 = ~out_romask_521; // @[RegisterRouter.scala:87:24] wire _out_T_5339 = ~out_womask_521; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_439 = {hi_558, flags_0_go, _out_prepend_T_439}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5340 = out_prepend_439; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5341 = _out_T_5340; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_440 = _out_T_5341; // @[RegisterRouter.scala:87:24] wire out_rimask_522 = \|_out_rimask_T_522; // @[RegisterRouter.scala:87:24] wire out_wimask_522 = &_out_wimask_T_522; // @[RegisterRouter.scala:87:24] wire out_romask_522 = \|_out_romask_T_522; // @[RegisterRouter.scala:87:24] wire out_womask_522 = &_out_womask_T_522; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_522 = out_rivalid_1_376 & out_rimask_522; // @[RegisterRouter.scala:87:24] wire _out_T_5343 = out_f_rivalid_522; // @[RegisterRouter.scala:87:24] wire out_f_roready_522 = out_roready_1_376 & out_romask_522; // @[RegisterRouter.scala:87:24] wire _out_T_5344 = out_f_roready_522; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_522 = out_wivalid_1_376 & out_wimask_522; // @[RegisterRouter.scala:87:24] wire out_f_woready_522 = out_woready_1_376 & out_womask_522; // @[RegisterRouter.scala:87:24] wire _out_T_5345 = ~out_rimask_522; // @[RegisterRouter.scala:87:24] wire _out_T_5346 = ~out_wimask_522; // @[RegisterRouter.scala:87:24] wire _out_T_5347 = ~out_romask_522; // @[RegisterRouter.scala:87:24] wire _out_T_5348 = ~out_womask_522; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_440 = {hi_559, flags_0_go, _out_prepend_T_440}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5349 = out_prepend_440; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5350 = _out_T_5349; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_441 = _out_T_5350; // @[RegisterRouter.scala:87:24] wire out_rimask_523 = \|_out_rimask_T_523; // @[RegisterRouter.scala:87:24] wire out_wimask_523 = &_out_wimask_T_523; // @[RegisterRouter.scala:87:24] wire out_romask_523 = \|_out_romask_T_523; // @[RegisterRouter.scala:87:24] wire out_womask_523 = &_out_womask_T_523; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_523 = out_rivalid_1_377 & out_rimask_523; // @[RegisterRouter.scala:87:24] wire _out_T_5352 = out_f_rivalid_523; // @[RegisterRouter.scala:87:24] wire out_f_roready_523 = out_roready_1_377 & out_romask_523; // @[RegisterRouter.scala:87:24] wire _out_T_5353 = out_f_roready_523; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_523 = out_wivalid_1_377 & out_wimask_523; // @[RegisterRouter.scala:87:24] wire out_f_woready_523 = out_woready_1_377 & out_womask_523; // @[RegisterRouter.scala:87:24] wire _out_T_5354 = ~out_rimask_523; // @[RegisterRouter.scala:87:24] wire _out_T_5355 = ~out_wimask_523; // @[RegisterRouter.scala:87:24] wire _out_T_5356 = ~out_romask_523; // @[RegisterRouter.scala:87:24] wire _out_T_5357 = ~out_womask_523; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_441 = {hi_560, flags_0_go, _out_prepend_T_441}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5358 = out_prepend_441; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5359 = _out_T_5358; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_197 = _out_T_5359; // @[MuxLiteral.scala:49:48] wire out_rimask_524 = \|_out_rimask_T_524; // @[RegisterRouter.scala:87:24] wire out_wimask_524 = &_out_wimask_T_524; // @[RegisterRouter.scala:87:24] wire out_romask_524 = \|_out_romask_T_524; // @[RegisterRouter.scala:87:24] wire out_womask_524 = &_out_womask_T_524; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_524 = out_rivalid_1_378 & out_rimask_524; // @[RegisterRouter.scala:87:24] wire _out_T_5361 = out_f_rivalid_524; // @[RegisterRouter.scala:87:24] wire out_f_roready_524 = out_roready_1_378 & out_romask_524; // @[RegisterRouter.scala:87:24] wire _out_T_5362 = out_f_roready_524; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_524 = out_wivalid_1_378 & out_wimask_524; // @[RegisterRouter.scala:87:24] wire out_f_woready_524 = out_woready_1_378 & out_womask_524; // @[RegisterRouter.scala:87:24] wire _out_T_5363 = ~out_rimask_524; // @[RegisterRouter.scala:87:24] wire _out_T_5364 = ~out_wimask_524; // @[RegisterRouter.scala:87:24] wire _out_T_5365 = ~out_romask_524; // @[RegisterRouter.scala:87:24] wire _out_T_5366 = ~out_womask_524; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5368 = _out_T_5367; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_442 = _out_T_5368; // @[RegisterRouter.scala:87:24] wire out_rimask_525 = \|_out_rimask_T_525; // @[RegisterRouter.scala:87:24] wire out_wimask_525 = &_out_wimask_T_525; // @[RegisterRouter.scala:87:24] wire out_romask_525 = \|_out_romask_T_525; // @[RegisterRouter.scala:87:24] wire out_womask_525 = &_out_womask_T_525; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_525 = out_rivalid_1_379 & out_rimask_525; // @[RegisterRouter.scala:87:24] wire _out_T_5370 = out_f_rivalid_525; // @[RegisterRouter.scala:87:24] wire out_f_roready_525 = out_roready_1_379 & out_romask_525; // @[RegisterRouter.scala:87:24] wire _out_T_5371 = out_f_roready_525; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_525 = out_wivalid_1_379 & out_wimask_525; // @[RegisterRouter.scala:87:24] wire out_f_woready_525 = out_woready_1_379 & out_womask_525; // @[RegisterRouter.scala:87:24] wire _out_T_5372 = ~out_rimask_525; // @[RegisterRouter.scala:87:24] wire _out_T_5373 = ~out_wimask_525; // @[RegisterRouter.scala:87:24] wire _out_T_5374 = ~out_romask_525; // @[RegisterRouter.scala:87:24] wire _out_T_5375 = ~out_womask_525; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_442 = {hi_770, flags_0_go, _out_prepend_T_442}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5376 = out_prepend_442; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5377 = _out_T_5376; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_443 = _out_T_5377; // @[RegisterRouter.scala:87:24] wire out_rimask_526 = \|_out_rimask_T_526; // @[RegisterRouter.scala:87:24] wire out_wimask_526 = &_out_wimask_T_526; // @[RegisterRouter.scala:87:24] wire out_romask_526 = \|_out_romask_T_526; // @[RegisterRouter.scala:87:24] wire out_womask_526 = &_out_womask_T_526; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_526 = out_rivalid_1_380 & out_rimask_526; // @[RegisterRouter.scala:87:24] wire _out_T_5379 = out_f_rivalid_526; // @[RegisterRouter.scala:87:24] wire out_f_roready_526 = out_roready_1_380 & out_romask_526; // @[RegisterRouter.scala:87:24] wire _out_T_5380 = out_f_roready_526; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_526 = out_wivalid_1_380 & out_wimask_526; // @[RegisterRouter.scala:87:24] wire out_f_woready_526 = out_woready_1_380 & out_womask_526; // @[RegisterRouter.scala:87:24] wire _out_T_5381 = ~out_rimask_526; // @[RegisterRouter.scala:87:24] wire _out_T_5382 = ~out_wimask_526; // @[RegisterRouter.scala:87:24] wire _out_T_5383 = ~out_romask_526; // @[RegisterRouter.scala:87:24] wire _out_T_5384 = ~out_womask_526; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_443 = {hi_771, flags_0_go, _out_prepend_T_443}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5385 = out_prepend_443; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5386 = _out_T_5385; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_444 = _out_T_5386; // @[RegisterRouter.scala:87:24] wire out_rimask_527 = \|_out_rimask_T_527; // @[RegisterRouter.scala:87:24] wire out_wimask_527 = &_out_wimask_T_527; // @[RegisterRouter.scala:87:24] wire out_romask_527 = \|_out_romask_T_527; // @[RegisterRouter.scala:87:24] wire out_womask_527 = &_out_womask_T_527; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_527 = out_rivalid_1_381 & out_rimask_527; // @[RegisterRouter.scala:87:24] wire _out_T_5388 = out_f_rivalid_527; // @[RegisterRouter.scala:87:24] wire out_f_roready_527 = out_roready_1_381 & out_romask_527; // @[RegisterRouter.scala:87:24] wire _out_T_5389 = out_f_roready_527; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_527 = out_wivalid_1_381 & out_wimask_527; // @[RegisterRouter.scala:87:24] wire out_f_woready_527 = out_woready_1_381 & out_womask_527; // @[RegisterRouter.scala:87:24] wire _out_T_5390 = ~out_rimask_527; // @[RegisterRouter.scala:87:24] wire _out_T_5391 = ~out_wimask_527; // @[RegisterRouter.scala:87:24] wire _out_T_5392 = ~out_romask_527; // @[RegisterRouter.scala:87:24] wire _out_T_5393 = ~out_womask_527; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_444 = {hi_772, flags_0_go, _out_prepend_T_444}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5394 = out_prepend_444; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5395 = _out_T_5394; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_445 = _out_T_5395; // @[RegisterRouter.scala:87:24] wire out_rimask_528 = \|_out_rimask_T_528; // @[RegisterRouter.scala:87:24] wire out_wimask_528 = &_out_wimask_T_528; // @[RegisterRouter.scala:87:24] wire out_romask_528 = \|_out_romask_T_528; // @[RegisterRouter.scala:87:24] wire out_womask_528 = &_out_womask_T_528; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_528 = out_rivalid_1_382 & out_rimask_528; // @[RegisterRouter.scala:87:24] wire _out_T_5397 = out_f_rivalid_528; // @[RegisterRouter.scala:87:24] wire out_f_roready_528 = out_roready_1_382 & out_romask_528; // @[RegisterRouter.scala:87:24] wire _out_T_5398 = out_f_roready_528; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_528 = out_wivalid_1_382 & out_wimask_528; // @[RegisterRouter.scala:87:24] wire out_f_woready_528 = out_woready_1_382 & out_womask_528; // @[RegisterRouter.scala:87:24] wire _out_T_5399 = ~out_rimask_528; // @[RegisterRouter.scala:87:24] wire _out_T_5400 = ~out_wimask_528; // @[RegisterRouter.scala:87:24] wire _out_T_5401 = ~out_romask_528; // @[RegisterRouter.scala:87:24] wire _out_T_5402 = ~out_womask_528; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_445 = {hi_773, flags_0_go, _out_prepend_T_445}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5403 = out_prepend_445; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5404 = _out_T_5403; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_446 = _out_T_5404; // @[RegisterRouter.scala:87:24] wire out_rimask_529 = \|_out_rimask_T_529; // @[RegisterRouter.scala:87:24] wire out_wimask_529 = &_out_wimask_T_529; // @[RegisterRouter.scala:87:24] wire out_romask_529 = \|_out_romask_T_529; // @[RegisterRouter.scala:87:24] wire out_womask_529 = &_out_womask_T_529; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_529 = out_rivalid_1_383 & out_rimask_529; // @[RegisterRouter.scala:87:24] wire _out_T_5406 = out_f_rivalid_529; // @[RegisterRouter.scala:87:24] wire out_f_roready_529 = out_roready_1_383 & out_romask_529; // @[RegisterRouter.scala:87:24] wire _out_T_5407 = out_f_roready_529; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_529 = out_wivalid_1_383 & out_wimask_529; // @[RegisterRouter.scala:87:24] wire out_f_woready_529 = out_woready_1_383 & out_womask_529; // @[RegisterRouter.scala:87:24] wire _out_T_5408 = ~out_rimask_529; // @[RegisterRouter.scala:87:24] wire _out_T_5409 = ~out_wimask_529; // @[RegisterRouter.scala:87:24] wire _out_T_5410 = ~out_romask_529; // @[RegisterRouter.scala:87:24] wire _out_T_5411 = ~out_womask_529; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_446 = {hi_774, flags_0_go, _out_prepend_T_446}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5412 = out_prepend_446; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5413 = _out_T_5412; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_447 = _out_T_5413; // @[RegisterRouter.scala:87:24] wire out_rimask_530 = \|_out_rimask_T_530; // @[RegisterRouter.scala:87:24] wire out_wimask_530 = &_out_wimask_T_530; // @[RegisterRouter.scala:87:24] wire out_romask_530 = \|_out_romask_T_530; // @[RegisterRouter.scala:87:24] wire out_womask_530 = &_out_womask_T_530; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_530 = out_rivalid_1_384 & out_rimask_530; // @[RegisterRouter.scala:87:24] wire _out_T_5415 = out_f_rivalid_530; // @[RegisterRouter.scala:87:24] wire out_f_roready_530 = out_roready_1_384 & out_romask_530; // @[RegisterRouter.scala:87:24] wire _out_T_5416 = out_f_roready_530; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_530 = out_wivalid_1_384 & out_wimask_530; // @[RegisterRouter.scala:87:24] wire out_f_woready_530 = out_woready_1_384 & out_womask_530; // @[RegisterRouter.scala:87:24] wire _out_T_5417 = ~out_rimask_530; // @[RegisterRouter.scala:87:24] wire _out_T_5418 = ~out_wimask_530; // @[RegisterRouter.scala:87:24] wire _out_T_5419 = ~out_romask_530; // @[RegisterRouter.scala:87:24] wire _out_T_5420 = ~out_womask_530; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_447 = {hi_775, flags_0_go, _out_prepend_T_447}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5421 = out_prepend_447; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5422 = _out_T_5421; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_448 = _out_T_5422; // @[RegisterRouter.scala:87:24] wire out_rimask_531 = \|_out_rimask_T_531; // @[RegisterRouter.scala:87:24] wire out_wimask_531 = &_out_wimask_T_531; // @[RegisterRouter.scala:87:24] wire out_romask_531 = \|_out_romask_T_531; // @[RegisterRouter.scala:87:24] wire out_womask_531 = &_out_womask_T_531; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_531 = out_rivalid_1_385 & out_rimask_531; // @[RegisterRouter.scala:87:24] wire _out_T_5424 = out_f_rivalid_531; // @[RegisterRouter.scala:87:24] wire out_f_roready_531 = out_roready_1_385 & out_romask_531; // @[RegisterRouter.scala:87:24] wire _out_T_5425 = out_f_roready_531; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_531 = out_wivalid_1_385 & out_wimask_531; // @[RegisterRouter.scala:87:24] wire out_f_woready_531 = out_woready_1_385 & out_womask_531; // @[RegisterRouter.scala:87:24] wire _out_T_5426 = ~out_rimask_531; // @[RegisterRouter.scala:87:24] wire _out_T_5427 = ~out_wimask_531; // @[RegisterRouter.scala:87:24] wire _out_T_5428 = ~out_romask_531; // @[RegisterRouter.scala:87:24] wire _out_T_5429 = ~out_womask_531; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_448 = {hi_776, flags_0_go, _out_prepend_T_448}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5430 = out_prepend_448; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5431 = _out_T_5430; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_224 = _out_T_5431; // @[MuxLiteral.scala:49:48] wire out_rimask_532 = \|_out_rimask_T_532; // @[RegisterRouter.scala:87:24] wire out_wimask_532 = &_out_wimask_T_532; // @[RegisterRouter.scala:87:24] wire out_romask_532 = \|_out_romask_T_532; // @[RegisterRouter.scala:87:24] wire out_womask_532 = &_out_womask_T_532; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_532 = out_rivalid_1_386 & out_rimask_532; // @[RegisterRouter.scala:87:24] wire _out_T_5433 = out_f_rivalid_532; // @[RegisterRouter.scala:87:24] wire out_f_roready_532 = out_roready_1_386 & out_romask_532; // @[RegisterRouter.scala:87:24] wire _out_T_5434 = out_f_roready_532; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_532 = out_wivalid_1_386 & out_wimask_532; // @[RegisterRouter.scala:87:24] wire out_f_woready_532 = out_woready_1_386 & out_womask_532; // @[RegisterRouter.scala:87:24] wire _out_T_5435 = ~out_rimask_532; // @[RegisterRouter.scala:87:24] wire _out_T_5436 = ~out_wimask_532; // @[RegisterRouter.scala:87:24] wire _out_T_5437 = ~out_romask_532; // @[RegisterRouter.scala:87:24] wire _out_T_5438 = ~out_womask_532; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5440 = _out_T_5439; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_449 = _out_T_5440; // @[RegisterRouter.scala:87:24] wire out_rimask_533 = \|_out_rimask_T_533; // @[RegisterRouter.scala:87:24] wire out_wimask_533 = &_out_wimask_T_533; // @[RegisterRouter.scala:87:24] wire out_romask_533 = \|_out_romask_T_533; // @[RegisterRouter.scala:87:24] wire out_womask_533 = &_out_womask_T_533; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_533 = out_rivalid_1_387 & out_rimask_533; // @[RegisterRouter.scala:87:24] wire _out_T_5442 = out_f_rivalid_533; // @[RegisterRouter.scala:87:24] wire out_f_roready_533 = out_roready_1_387 & out_romask_533; // @[RegisterRouter.scala:87:24] wire _out_T_5443 = out_f_roready_533; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_533 = out_wivalid_1_387 & out_wimask_533; // @[RegisterRouter.scala:87:24] wire out_f_woready_533 = out_woready_1_387 & out_womask_533; // @[RegisterRouter.scala:87:24] wire _out_T_5444 = ~out_rimask_533; // @[RegisterRouter.scala:87:24] wire _out_T_5445 = ~out_wimask_533; // @[RegisterRouter.scala:87:24] wire _out_T_5446 = ~out_romask_533; // @[RegisterRouter.scala:87:24] wire _out_T_5447 = ~out_womask_533; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_449 = {hi_226, flags_0_go, _out_prepend_T_449}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5448 = out_prepend_449; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5449 = _out_T_5448; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_450 = _out_T_5449; // @[RegisterRouter.scala:87:24] wire out_rimask_534 = \|_out_rimask_T_534; // @[RegisterRouter.scala:87:24] wire out_wimask_534 = &_out_wimask_T_534; // @[RegisterRouter.scala:87:24] wire out_romask_534 = \|_out_romask_T_534; // @[RegisterRouter.scala:87:24] wire out_womask_534 = &_out_womask_T_534; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_534 = out_rivalid_1_388 & out_rimask_534; // @[RegisterRouter.scala:87:24] wire _out_T_5451 = out_f_rivalid_534; // @[RegisterRouter.scala:87:24] wire out_f_roready_534 = out_roready_1_388 & out_romask_534; // @[RegisterRouter.scala:87:24] wire _out_T_5452 = out_f_roready_534; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_534 = out_wivalid_1_388 & out_wimask_534; // @[RegisterRouter.scala:87:24] wire out_f_woready_534 = out_woready_1_388 & out_womask_534; // @[RegisterRouter.scala:87:24] wire _out_T_5453 = ~out_rimask_534; // @[RegisterRouter.scala:87:24] wire _out_T_5454 = ~out_wimask_534; // @[RegisterRouter.scala:87:24] wire _out_T_5455 = ~out_romask_534; // @[RegisterRouter.scala:87:24] wire _out_T_5456 = ~out_womask_534; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_450 = {hi_227, flags_0_go, _out_prepend_T_450}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5457 = out_prepend_450; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5458 = _out_T_5457; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_451 = _out_T_5458; // @[RegisterRouter.scala:87:24] wire out_rimask_535 = \|_out_rimask_T_535; // @[RegisterRouter.scala:87:24] wire out_wimask_535 = &_out_wimask_T_535; // @[RegisterRouter.scala:87:24] wire out_romask_535 = \|_out_romask_T_535; // @[RegisterRouter.scala:87:24] wire out_womask_535 = &_out_womask_T_535; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_535 = out_rivalid_1_389 & out_rimask_535; // @[RegisterRouter.scala:87:24] wire _out_T_5460 = out_f_rivalid_535; // @[RegisterRouter.scala:87:24] wire out_f_roready_535 = out_roready_1_389 & out_romask_535; // @[RegisterRouter.scala:87:24] wire _out_T_5461 = out_f_roready_535; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_535 = out_wivalid_1_389 & out_wimask_535; // @[RegisterRouter.scala:87:24] wire out_f_woready_535 = out_woready_1_389 & out_womask_535; // @[RegisterRouter.scala:87:24] wire _out_T_5462 = ~out_rimask_535; // @[RegisterRouter.scala:87:24] wire _out_T_5463 = ~out_wimask_535; // @[RegisterRouter.scala:87:24] wire _out_T_5464 = ~out_romask_535; // @[RegisterRouter.scala:87:24] wire _out_T_5465 = ~out_womask_535; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_451 = {hi_228, flags_0_go, _out_prepend_T_451}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5466 = out_prepend_451; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5467 = _out_T_5466; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_452 = _out_T_5467; // @[RegisterRouter.scala:87:24] wire out_rimask_536 = \|_out_rimask_T_536; // @[RegisterRouter.scala:87:24] wire out_wimask_536 = &_out_wimask_T_536; // @[RegisterRouter.scala:87:24] wire out_romask_536 = \|_out_romask_T_536; // @[RegisterRouter.scala:87:24] wire out_womask_536 = &_out_womask_T_536; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_536 = out_rivalid_1_390 & out_rimask_536; // @[RegisterRouter.scala:87:24] wire _out_T_5469 = out_f_rivalid_536; // @[RegisterRouter.scala:87:24] wire out_f_roready_536 = out_roready_1_390 & out_romask_536; // @[RegisterRouter.scala:87:24] wire _out_T_5470 = out_f_roready_536; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_536 = out_wivalid_1_390 & out_wimask_536; // @[RegisterRouter.scala:87:24] wire out_f_woready_536 = out_woready_1_390 & out_womask_536; // @[RegisterRouter.scala:87:24] wire _out_T_5471 = ~out_rimask_536; // @[RegisterRouter.scala:87:24] wire _out_T_5472 = ~out_wimask_536; // @[RegisterRouter.scala:87:24] wire _out_T_5473 = ~out_romask_536; // @[RegisterRouter.scala:87:24] wire _out_T_5474 = ~out_womask_536; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_452 = {hi_229, flags_0_go, _out_prepend_T_452}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5475 = out_prepend_452; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5476 = _out_T_5475; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_453 = _out_T_5476; // @[RegisterRouter.scala:87:24] wire out_rimask_537 = \|_out_rimask_T_537; // @[RegisterRouter.scala:87:24] wire out_wimask_537 = &_out_wimask_T_537; // @[RegisterRouter.scala:87:24] wire out_romask_537 = \|_out_romask_T_537; // @[RegisterRouter.scala:87:24] wire out_womask_537 = &_out_womask_T_537; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_537 = out_rivalid_1_391 & out_rimask_537; // @[RegisterRouter.scala:87:24] wire _out_T_5478 = out_f_rivalid_537; // @[RegisterRouter.scala:87:24] wire out_f_roready_537 = out_roready_1_391 & out_romask_537; // @[RegisterRouter.scala:87:24] wire _out_T_5479 = out_f_roready_537; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_537 = out_wivalid_1_391 & out_wimask_537; // @[RegisterRouter.scala:87:24] wire out_f_woready_537 = out_woready_1_391 & out_womask_537; // @[RegisterRouter.scala:87:24] wire _out_T_5480 = ~out_rimask_537; // @[RegisterRouter.scala:87:24] wire _out_T_5481 = ~out_wimask_537; // @[RegisterRouter.scala:87:24] wire _out_T_5482 = ~out_romask_537; // @[RegisterRouter.scala:87:24] wire _out_T_5483 = ~out_womask_537; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_453 = {hi_230, flags_0_go, _out_prepend_T_453}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5484 = out_prepend_453; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5485 = _out_T_5484; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_454 = _out_T_5485; // @[RegisterRouter.scala:87:24] wire out_rimask_538 = \|_out_rimask_T_538; // @[RegisterRouter.scala:87:24] wire out_wimask_538 = &_out_wimask_T_538; // @[RegisterRouter.scala:87:24] wire out_romask_538 = \|_out_romask_T_538; // @[RegisterRouter.scala:87:24] wire out_womask_538 = &_out_womask_T_538; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_538 = out_rivalid_1_392 & out_rimask_538; // @[RegisterRouter.scala:87:24] wire _out_T_5487 = out_f_rivalid_538; // @[RegisterRouter.scala:87:24] wire out_f_roready_538 = out_roready_1_392 & out_romask_538; // @[RegisterRouter.scala:87:24] wire _out_T_5488 = out_f_roready_538; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_538 = out_wivalid_1_392 & out_wimask_538; // @[RegisterRouter.scala:87:24] wire out_f_woready_538 = out_woready_1_392 & out_womask_538; // @[RegisterRouter.scala:87:24] wire _out_T_5489 = ~out_rimask_538; // @[RegisterRouter.scala:87:24] wire _out_T_5490 = ~out_wimask_538; // @[RegisterRouter.scala:87:24] wire _out_T_5491 = ~out_romask_538; // @[RegisterRouter.scala:87:24] wire _out_T_5492 = ~out_womask_538; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_454 = {hi_231, flags_0_go, _out_prepend_T_454}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5493 = out_prepend_454; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5494 = _out_T_5493; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_455 = _out_T_5494; // @[RegisterRouter.scala:87:24] wire out_rimask_539 = \|_out_rimask_T_539; // @[RegisterRouter.scala:87:24] wire out_wimask_539 = &_out_wimask_T_539; // @[RegisterRouter.scala:87:24] wire out_romask_539 = \|_out_romask_T_539; // @[RegisterRouter.scala:87:24] wire out_womask_539 = &_out_womask_T_539; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_539 = out_rivalid_1_393 & out_rimask_539; // @[RegisterRouter.scala:87:24] wire _out_T_5496 = out_f_rivalid_539; // @[RegisterRouter.scala:87:24] wire out_f_roready_539 = out_roready_1_393 & out_romask_539; // @[RegisterRouter.scala:87:24] wire _out_T_5497 = out_f_roready_539; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_539 = out_wivalid_1_393 & out_wimask_539; // @[RegisterRouter.scala:87:24] wire out_f_woready_539 = out_woready_1_393 & out_womask_539; // @[RegisterRouter.scala:87:24] wire _out_T_5498 = ~out_rimask_539; // @[RegisterRouter.scala:87:24] wire _out_T_5499 = ~out_wimask_539; // @[RegisterRouter.scala:87:24] wire _out_T_5500 = ~out_romask_539; // @[RegisterRouter.scala:87:24] wire _out_T_5501 = ~out_womask_539; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_455 = {hi_232, flags_0_go, _out_prepend_T_455}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5502 = out_prepend_455; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5503 = _out_T_5502; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_156 = _out_T_5503; // @[MuxLiteral.scala:49:48] wire out_rimask_540 = \|_out_rimask_T_540; // @[RegisterRouter.scala:87:24] wire out_wimask_540 = &_out_wimask_T_540; // @[RegisterRouter.scala:87:24] wire out_romask_540 = \|_out_romask_T_540; // @[RegisterRouter.scala:87:24] wire out_womask_540 = &_out_womask_T_540; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_540 = out_rivalid_1_394 & out_rimask_540; // @[RegisterRouter.scala:87:24] wire _out_T_5505 = out_f_rivalid_540; // @[RegisterRouter.scala:87:24] wire out_f_roready_540 = out_roready_1_394 & out_romask_540; // @[RegisterRouter.scala:87:24] wire _out_T_5506 = out_f_roready_540; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_540 = out_wivalid_1_394 & out_wimask_540; // @[RegisterRouter.scala:87:24] wire out_f_woready_540 = out_woready_1_394 & out_womask_540; // @[RegisterRouter.scala:87:24] wire _out_T_5507 = ~out_rimask_540; // @[RegisterRouter.scala:87:24] wire _out_T_5508 = ~out_wimask_540; // @[RegisterRouter.scala:87:24] wire _out_T_5509 = ~out_romask_540; // @[RegisterRouter.scala:87:24] wire _out_T_5510 = ~out_womask_540; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5512 = _out_T_5511; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_456 = _out_T_5512; // @[RegisterRouter.scala:87:24] wire out_rimask_541 = \|_out_rimask_T_541; // @[RegisterRouter.scala:87:24] wire out_wimask_541 = &_out_wimask_T_541; // @[RegisterRouter.scala:87:24] wire out_romask_541 = \|_out_romask_T_541; // @[RegisterRouter.scala:87:24] wire out_womask_541 = &_out_womask_T_541; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_541 = out_rivalid_1_395 & out_rimask_541; // @[RegisterRouter.scala:87:24] wire _out_T_5514 = out_f_rivalid_541; // @[RegisterRouter.scala:87:24] wire out_f_roready_541 = out_roready_1_395 & out_romask_541; // @[RegisterRouter.scala:87:24] wire _out_T_5515 = out_f_roready_541; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_541 = out_wivalid_1_395 & out_wimask_541; // @[RegisterRouter.scala:87:24] wire out_f_woready_541 = out_woready_1_395 & out_womask_541; // @[RegisterRouter.scala:87:24] wire _out_T_5516 = ~out_rimask_541; // @[RegisterRouter.scala:87:24] wire _out_T_5517 = ~out_wimask_541; // @[RegisterRouter.scala:87:24] wire _out_T_5518 = ~out_romask_541; // @[RegisterRouter.scala:87:24] wire _out_T_5519 = ~out_womask_541; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_456 = {hi_482, flags_0_go, _out_prepend_T_456}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5520 = out_prepend_456; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5521 = _out_T_5520; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_457 = _out_T_5521; // @[RegisterRouter.scala:87:24] wire out_rimask_542 = \|_out_rimask_T_542; // @[RegisterRouter.scala:87:24] wire out_wimask_542 = &_out_wimask_T_542; // @[RegisterRouter.scala:87:24] wire out_romask_542 = \|_out_romask_T_542; // @[RegisterRouter.scala:87:24] wire out_womask_542 = &_out_womask_T_542; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_542 = out_rivalid_1_396 & out_rimask_542; // @[RegisterRouter.scala:87:24] wire _out_T_5523 = out_f_rivalid_542; // @[RegisterRouter.scala:87:24] wire out_f_roready_542 = out_roready_1_396 & out_romask_542; // @[RegisterRouter.scala:87:24] wire _out_T_5524 = out_f_roready_542; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_542 = out_wivalid_1_396 & out_wimask_542; // @[RegisterRouter.scala:87:24] wire out_f_woready_542 = out_woready_1_396 & out_womask_542; // @[RegisterRouter.scala:87:24] wire _out_T_5525 = ~out_rimask_542; // @[RegisterRouter.scala:87:24] wire _out_T_5526 = ~out_wimask_542; // @[RegisterRouter.scala:87:24] wire _out_T_5527 = ~out_romask_542; // @[RegisterRouter.scala:87:24] wire _out_T_5528 = ~out_womask_542; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_457 = {hi_483, flags_0_go, _out_prepend_T_457}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5529 = out_prepend_457; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5530 = _out_T_5529; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_458 = _out_T_5530; // @[RegisterRouter.scala:87:24] wire out_rimask_543 = \|_out_rimask_T_543; // @[RegisterRouter.scala:87:24] wire out_wimask_543 = &_out_wimask_T_543; // @[RegisterRouter.scala:87:24] wire out_romask_543 = \|_out_romask_T_543; // @[RegisterRouter.scala:87:24] wire out_womask_543 = &_out_womask_T_543; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_543 = out_rivalid_1_397 & out_rimask_543; // @[RegisterRouter.scala:87:24] wire _out_T_5532 = out_f_rivalid_543; // @[RegisterRouter.scala:87:24] wire out_f_roready_543 = out_roready_1_397 & out_romask_543; // @[RegisterRouter.scala:87:24] wire _out_T_5533 = out_f_roready_543; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_543 = out_wivalid_1_397 & out_wimask_543; // @[RegisterRouter.scala:87:24] wire out_f_woready_543 = out_woready_1_397 & out_womask_543; // @[RegisterRouter.scala:87:24] wire _out_T_5534 = ~out_rimask_543; // @[RegisterRouter.scala:87:24] wire _out_T_5535 = ~out_wimask_543; // @[RegisterRouter.scala:87:24] wire _out_T_5536 = ~out_romask_543; // @[RegisterRouter.scala:87:24] wire _out_T_5537 = ~out_womask_543; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_458 = {hi_484, flags_0_go, _out_prepend_T_458}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5538 = out_prepend_458; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5539 = _out_T_5538; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_459 = _out_T_5539; // @[RegisterRouter.scala:87:24] wire out_rimask_544 = \|_out_rimask_T_544; // @[RegisterRouter.scala:87:24] wire out_wimask_544 = &_out_wimask_T_544; // @[RegisterRouter.scala:87:24] wire out_romask_544 = \|_out_romask_T_544; // @[RegisterRouter.scala:87:24] wire out_womask_544 = &_out_womask_T_544; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_544 = out_rivalid_1_398 & out_rimask_544; // @[RegisterRouter.scala:87:24] wire _out_T_5541 = out_f_rivalid_544; // @[RegisterRouter.scala:87:24] wire out_f_roready_544 = out_roready_1_398 & out_romask_544; // @[RegisterRouter.scala:87:24] wire _out_T_5542 = out_f_roready_544; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_544 = out_wivalid_1_398 & out_wimask_544; // @[RegisterRouter.scala:87:24] wire out_f_woready_544 = out_woready_1_398 & out_womask_544; // @[RegisterRouter.scala:87:24] wire _out_T_5543 = ~out_rimask_544; // @[RegisterRouter.scala:87:24] wire _out_T_5544 = ~out_wimask_544; // @[RegisterRouter.scala:87:24] wire _out_T_5545 = ~out_romask_544; // @[RegisterRouter.scala:87:24] wire _out_T_5546 = ~out_womask_544; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_459 = {hi_485, flags_0_go, _out_prepend_T_459}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5547 = out_prepend_459; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5548 = _out_T_5547; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_460 = _out_T_5548; // @[RegisterRouter.scala:87:24] wire out_rimask_545 = \|_out_rimask_T_545; // @[RegisterRouter.scala:87:24] wire out_wimask_545 = &_out_wimask_T_545; // @[RegisterRouter.scala:87:24] wire out_romask_545 = \|_out_romask_T_545; // @[RegisterRouter.scala:87:24] wire out_womask_545 = &_out_womask_T_545; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_545 = out_rivalid_1_399 & out_rimask_545; // @[RegisterRouter.scala:87:24] wire _out_T_5550 = out_f_rivalid_545; // @[RegisterRouter.scala:87:24] wire out_f_roready_545 = out_roready_1_399 & out_romask_545; // @[RegisterRouter.scala:87:24] wire _out_T_5551 = out_f_roready_545; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_545 = out_wivalid_1_399 & out_wimask_545; // @[RegisterRouter.scala:87:24] wire out_f_woready_545 = out_woready_1_399 & out_womask_545; // @[RegisterRouter.scala:87:24] wire _out_T_5552 = ~out_rimask_545; // @[RegisterRouter.scala:87:24] wire _out_T_5553 = ~out_wimask_545; // @[RegisterRouter.scala:87:24] wire _out_T_5554 = ~out_romask_545; // @[RegisterRouter.scala:87:24] wire _out_T_5555 = ~out_womask_545; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_460 = {hi_486, flags_0_go, _out_prepend_T_460}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5556 = out_prepend_460; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5557 = _out_T_5556; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_461 = _out_T_5557; // @[RegisterRouter.scala:87:24] wire out_rimask_546 = \|_out_rimask_T_546; // @[RegisterRouter.scala:87:24] wire out_wimask_546 = &_out_wimask_T_546; // @[RegisterRouter.scala:87:24] wire out_romask_546 = \|_out_romask_T_546; // @[RegisterRouter.scala:87:24] wire out_womask_546 = &_out_womask_T_546; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_546 = out_rivalid_1_400 & out_rimask_546; // @[RegisterRouter.scala:87:24] wire _out_T_5559 = out_f_rivalid_546; // @[RegisterRouter.scala:87:24] wire out_f_roready_546 = out_roready_1_400 & out_romask_546; // @[RegisterRouter.scala:87:24] wire _out_T_5560 = out_f_roready_546; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_546 = out_wivalid_1_400 & out_wimask_546; // @[RegisterRouter.scala:87:24] wire out_f_woready_546 = out_woready_1_400 & out_womask_546; // @[RegisterRouter.scala:87:24] wire _out_T_5561 = ~out_rimask_546; // @[RegisterRouter.scala:87:24] wire _out_T_5562 = ~out_wimask_546; // @[RegisterRouter.scala:87:24] wire _out_T_5563 = ~out_romask_546; // @[RegisterRouter.scala:87:24] wire _out_T_5564 = ~out_womask_546; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_461 = {hi_487, flags_0_go, _out_prepend_T_461}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5565 = out_prepend_461; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5566 = _out_T_5565; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_462 = _out_T_5566; // @[RegisterRouter.scala:87:24] wire out_rimask_547 = \|_out_rimask_T_547; // @[RegisterRouter.scala:87:24] wire out_wimask_547 = &_out_wimask_T_547; // @[RegisterRouter.scala:87:24] wire out_romask_547 = \|_out_romask_T_547; // @[RegisterRouter.scala:87:24] wire out_womask_547 = &_out_womask_T_547; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_547 = out_rivalid_1_401 & out_rimask_547; // @[RegisterRouter.scala:87:24] wire _out_T_5568 = out_f_rivalid_547; // @[RegisterRouter.scala:87:24] wire out_f_roready_547 = out_roready_1_401 & out_romask_547; // @[RegisterRouter.scala:87:24] wire _out_T_5569 = out_f_roready_547; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_547 = out_wivalid_1_401 & out_wimask_547; // @[RegisterRouter.scala:87:24] wire out_f_woready_547 = out_woready_1_401 & out_womask_547; // @[RegisterRouter.scala:87:24] wire _out_T_5570 = ~out_rimask_547; // @[RegisterRouter.scala:87:24] wire _out_T_5571 = ~out_wimask_547; // @[RegisterRouter.scala:87:24] wire _out_T_5572 = ~out_romask_547; // @[RegisterRouter.scala:87:24] wire _out_T_5573 = ~out_womask_547; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_462 = {hi_488, flags_0_go, _out_prepend_T_462}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5574 = out_prepend_462; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5575 = _out_T_5574; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_188 = _out_T_5575; // @[MuxLiteral.scala:49:48] wire out_rimask_548 = \|_out_rimask_T_548; // @[RegisterRouter.scala:87:24] wire out_wimask_548 = &_out_wimask_T_548; // @[RegisterRouter.scala:87:24] wire out_romask_548 = \|_out_romask_T_548; // @[RegisterRouter.scala:87:24] wire out_womask_548 = &_out_womask_T_548; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_548 = out_rivalid_1_402 & out_rimask_548; // @[RegisterRouter.scala:87:24] wire _out_T_5577 = out_f_rivalid_548; // @[RegisterRouter.scala:87:24] wire out_f_roready_548 = out_roready_1_402 & out_romask_548; // @[RegisterRouter.scala:87:24] wire _out_T_5578 = out_f_roready_548; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_548 = out_wivalid_1_402 & out_wimask_548; // @[RegisterRouter.scala:87:24] wire out_f_woready_548 = out_woready_1_402 & out_womask_548; // @[RegisterRouter.scala:87:24] wire _out_T_5579 = ~out_rimask_548; // @[RegisterRouter.scala:87:24] wire _out_T_5580 = ~out_wimask_548; // @[RegisterRouter.scala:87:24] wire _out_T_5581 = ~out_romask_548; // @[RegisterRouter.scala:87:24] wire _out_T_5582 = ~out_womask_548; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5584 = _out_T_5583; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_463 = _out_T_5584; // @[RegisterRouter.scala:87:24] wire out_rimask_549 = \|_out_rimask_T_549; // @[RegisterRouter.scala:87:24] wire out_wimask_549 = &_out_wimask_T_549; // @[RegisterRouter.scala:87:24] wire out_romask_549 = \|_out_romask_T_549; // @[RegisterRouter.scala:87:24] wire out_womask_549 = &_out_womask_T_549; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_549 = out_rivalid_1_403 & out_rimask_549; // @[RegisterRouter.scala:87:24] wire _out_T_5586 = out_f_rivalid_549; // @[RegisterRouter.scala:87:24] wire out_f_roready_549 = out_roready_1_403 & out_romask_549; // @[RegisterRouter.scala:87:24] wire _out_T_5587 = out_f_roready_549; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_549 = out_wivalid_1_403 & out_wimask_549; // @[RegisterRouter.scala:87:24] wire out_f_woready_549 = out_woready_1_403 & out_womask_549; // @[RegisterRouter.scala:87:24] wire _out_T_5588 = ~out_rimask_549; // @[RegisterRouter.scala:87:24] wire _out_T_5589 = ~out_wimask_549; // @[RegisterRouter.scala:87:24] wire _out_T_5590 = ~out_romask_549; // @[RegisterRouter.scala:87:24] wire _out_T_5591 = ~out_womask_549; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_463 = {hi_330, flags_0_go, _out_prepend_T_463}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5592 = out_prepend_463; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5593 = _out_T_5592; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_464 = _out_T_5593; // @[RegisterRouter.scala:87:24] wire out_rimask_550 = \|_out_rimask_T_550; // @[RegisterRouter.scala:87:24] wire out_wimask_550 = &_out_wimask_T_550; // @[RegisterRouter.scala:87:24] wire out_romask_550 = \|_out_romask_T_550; // @[RegisterRouter.scala:87:24] wire out_womask_550 = &_out_womask_T_550; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_550 = out_rivalid_1_404 & out_rimask_550; // @[RegisterRouter.scala:87:24] wire _out_T_5595 = out_f_rivalid_550; // @[RegisterRouter.scala:87:24] wire out_f_roready_550 = out_roready_1_404 & out_romask_550; // @[RegisterRouter.scala:87:24] wire _out_T_5596 = out_f_roready_550; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_550 = out_wivalid_1_404 & out_wimask_550; // @[RegisterRouter.scala:87:24] wire out_f_woready_550 = out_woready_1_404 & out_womask_550; // @[RegisterRouter.scala:87:24] wire _out_T_5597 = ~out_rimask_550; // @[RegisterRouter.scala:87:24] wire _out_T_5598 = ~out_wimask_550; // @[RegisterRouter.scala:87:24] wire _out_T_5599 = ~out_romask_550; // @[RegisterRouter.scala:87:24] wire _out_T_5600 = ~out_womask_550; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_464 = {hi_331, flags_0_go, _out_prepend_T_464}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5601 = out_prepend_464; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5602 = _out_T_5601; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_465 = _out_T_5602; // @[RegisterRouter.scala:87:24] wire out_rimask_551 = \|_out_rimask_T_551; // @[RegisterRouter.scala:87:24] wire out_wimask_551 = &_out_wimask_T_551; // @[RegisterRouter.scala:87:24] wire out_romask_551 = \|_out_romask_T_551; // @[RegisterRouter.scala:87:24] wire out_womask_551 = &_out_womask_T_551; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_551 = out_rivalid_1_405 & out_rimask_551; // @[RegisterRouter.scala:87:24] wire _out_T_5604 = out_f_rivalid_551; // @[RegisterRouter.scala:87:24] wire out_f_roready_551 = out_roready_1_405 & out_romask_551; // @[RegisterRouter.scala:87:24] wire _out_T_5605 = out_f_roready_551; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_551 = out_wivalid_1_405 & out_wimask_551; // @[RegisterRouter.scala:87:24] wire out_f_woready_551 = out_woready_1_405 & out_womask_551; // @[RegisterRouter.scala:87:24] wire _out_T_5606 = ~out_rimask_551; // @[RegisterRouter.scala:87:24] wire _out_T_5607 = ~out_wimask_551; // @[RegisterRouter.scala:87:24] wire _out_T_5608 = ~out_romask_551; // @[RegisterRouter.scala:87:24] wire _out_T_5609 = ~out_womask_551; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_465 = {hi_332, flags_0_go, _out_prepend_T_465}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5610 = out_prepend_465; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5611 = _out_T_5610; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_466 = _out_T_5611; // @[RegisterRouter.scala:87:24] wire out_rimask_552 = \|_out_rimask_T_552; // @[RegisterRouter.scala:87:24] wire out_wimask_552 = &_out_wimask_T_552; // @[RegisterRouter.scala:87:24] wire out_romask_552 = \|_out_romask_T_552; // @[RegisterRouter.scala:87:24] wire out_womask_552 = &_out_womask_T_552; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_552 = out_rivalid_1_406 & out_rimask_552; // @[RegisterRouter.scala:87:24] wire _out_T_5613 = out_f_rivalid_552; // @[RegisterRouter.scala:87:24] wire out_f_roready_552 = out_roready_1_406 & out_romask_552; // @[RegisterRouter.scala:87:24] wire _out_T_5614 = out_f_roready_552; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_552 = out_wivalid_1_406 & out_wimask_552; // @[RegisterRouter.scala:87:24] wire out_f_woready_552 = out_woready_1_406 & out_womask_552; // @[RegisterRouter.scala:87:24] wire _out_T_5615 = ~out_rimask_552; // @[RegisterRouter.scala:87:24] wire _out_T_5616 = ~out_wimask_552; // @[RegisterRouter.scala:87:24] wire _out_T_5617 = ~out_romask_552; // @[RegisterRouter.scala:87:24] wire _out_T_5618 = ~out_womask_552; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_466 = {hi_333, flags_0_go, _out_prepend_T_466}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5619 = out_prepend_466; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5620 = _out_T_5619; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_467 = _out_T_5620; // @[RegisterRouter.scala:87:24] wire out_rimask_553 = \|_out_rimask_T_553; // @[RegisterRouter.scala:87:24] wire out_wimask_553 = &_out_wimask_T_553; // @[RegisterRouter.scala:87:24] wire out_romask_553 = \|_out_romask_T_553; // @[RegisterRouter.scala:87:24] wire out_womask_553 = &_out_womask_T_553; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_553 = out_rivalid_1_407 & out_rimask_553; // @[RegisterRouter.scala:87:24] wire _out_T_5622 = out_f_rivalid_553; // @[RegisterRouter.scala:87:24] wire out_f_roready_553 = out_roready_1_407 & out_romask_553; // @[RegisterRouter.scala:87:24] wire _out_T_5623 = out_f_roready_553; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_553 = out_wivalid_1_407 & out_wimask_553; // @[RegisterRouter.scala:87:24] wire out_f_woready_553 = out_woready_1_407 & out_womask_553; // @[RegisterRouter.scala:87:24] wire _out_T_5624 = ~out_rimask_553; // @[RegisterRouter.scala:87:24] wire _out_T_5625 = ~out_wimask_553; // @[RegisterRouter.scala:87:24] wire _out_T_5626 = ~out_romask_553; // @[RegisterRouter.scala:87:24] wire _out_T_5627 = ~out_womask_553; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_467 = {hi_334, flags_0_go, _out_prepend_T_467}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5628 = out_prepend_467; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5629 = _out_T_5628; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_468 = _out_T_5629; // @[RegisterRouter.scala:87:24] wire out_rimask_554 = \|_out_rimask_T_554; // @[RegisterRouter.scala:87:24] wire out_wimask_554 = &_out_wimask_T_554; // @[RegisterRouter.scala:87:24] wire out_romask_554 = \|_out_romask_T_554; // @[RegisterRouter.scala:87:24] wire out_womask_554 = &_out_womask_T_554; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_554 = out_rivalid_1_408 & out_rimask_554; // @[RegisterRouter.scala:87:24] wire _out_T_5631 = out_f_rivalid_554; // @[RegisterRouter.scala:87:24] wire out_f_roready_554 = out_roready_1_408 & out_romask_554; // @[RegisterRouter.scala:87:24] wire _out_T_5632 = out_f_roready_554; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_554 = out_wivalid_1_408 & out_wimask_554; // @[RegisterRouter.scala:87:24] wire out_f_woready_554 = out_woready_1_408 & out_womask_554; // @[RegisterRouter.scala:87:24] wire _out_T_5633 = ~out_rimask_554; // @[RegisterRouter.scala:87:24] wire _out_T_5634 = ~out_wimask_554; // @[RegisterRouter.scala:87:24] wire _out_T_5635 = ~out_romask_554; // @[RegisterRouter.scala:87:24] wire _out_T_5636 = ~out_womask_554; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_468 = {hi_335, flags_0_go, _out_prepend_T_468}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5637 = out_prepend_468; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5638 = _out_T_5637; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_469 = _out_T_5638; // @[RegisterRouter.scala:87:24] wire out_rimask_555 = \|_out_rimask_T_555; // @[RegisterRouter.scala:87:24] wire out_wimask_555 = &_out_wimask_T_555; // @[RegisterRouter.scala:87:24] wire out_romask_555 = \|_out_romask_T_555; // @[RegisterRouter.scala:87:24] wire out_womask_555 = &_out_womask_T_555; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_555 = out_rivalid_1_409 & out_rimask_555; // @[RegisterRouter.scala:87:24] wire _out_T_5640 = out_f_rivalid_555; // @[RegisterRouter.scala:87:24] wire out_f_roready_555 = out_roready_1_409 & out_romask_555; // @[RegisterRouter.scala:87:24] wire _out_T_5641 = out_f_roready_555; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_555 = out_wivalid_1_409 & out_wimask_555; // @[RegisterRouter.scala:87:24] wire out_f_woready_555 = out_woready_1_409 & out_womask_555; // @[RegisterRouter.scala:87:24] wire _out_T_5642 = ~out_rimask_555; // @[RegisterRouter.scala:87:24] wire _out_T_5643 = ~out_wimask_555; // @[RegisterRouter.scala:87:24] wire _out_T_5644 = ~out_romask_555; // @[RegisterRouter.scala:87:24] wire _out_T_5645 = ~out_womask_555; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_469 = {hi_336, flags_0_go, _out_prepend_T_469}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5646 = out_prepend_469; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5647 = _out_T_5646; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_169 = _out_T_5647; // @[MuxLiteral.scala:49:48] wire out_rimask_556 = \|_out_rimask_T_556; // @[RegisterRouter.scala:87:24] wire out_wimask_556 = &_out_wimask_T_556; // @[RegisterRouter.scala:87:24] wire out_romask_556 = \|_out_romask_T_556; // @[RegisterRouter.scala:87:24] wire out_womask_556 = &_out_womask_T_556; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_556 = out_rivalid_1_410 & out_rimask_556; // @[RegisterRouter.scala:87:24] wire _out_T_5649 = out_f_rivalid_556; // @[RegisterRouter.scala:87:24] wire out_f_roready_556 = out_roready_1_410 & out_romask_556; // @[RegisterRouter.scala:87:24] wire _out_T_5650 = out_f_roready_556; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_556 = out_wivalid_1_410 & out_wimask_556; // @[RegisterRouter.scala:87:24] wire out_f_woready_556 = out_woready_1_410 & out_womask_556; // @[RegisterRouter.scala:87:24] wire _out_T_5651 = ~out_rimask_556; // @[RegisterRouter.scala:87:24] wire _out_T_5652 = ~out_wimask_556; // @[RegisterRouter.scala:87:24] wire _out_T_5653 = ~out_romask_556; // @[RegisterRouter.scala:87:24] wire _out_T_5654 = ~out_womask_556; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5656 = _out_T_5655; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_470 = _out_T_5656; // @[RegisterRouter.scala:87:24] wire out_rimask_557 = \|_out_rimask_T_557; // @[RegisterRouter.scala:87:24] wire out_wimask_557 = &_out_wimask_T_557; // @[RegisterRouter.scala:87:24] wire out_romask_557 = \|_out_romask_T_557; // @[RegisterRouter.scala:87:24] wire out_womask_557 = &_out_womask_T_557; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_557 = out_rivalid_1_411 & out_rimask_557; // @[RegisterRouter.scala:87:24] wire _out_T_5658 = out_f_rivalid_557; // @[RegisterRouter.scala:87:24] wire out_f_roready_557 = out_roready_1_411 & out_romask_557; // @[RegisterRouter.scala:87:24] wire _out_T_5659 = out_f_roready_557; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_557 = out_wivalid_1_411 & out_wimask_557; // @[RegisterRouter.scala:87:24] wire out_f_woready_557 = out_woready_1_411 & out_womask_557; // @[RegisterRouter.scala:87:24] wire _out_T_5660 = ~out_rimask_557; // @[RegisterRouter.scala:87:24] wire _out_T_5661 = ~out_wimask_557; // @[RegisterRouter.scala:87:24] wire _out_T_5662 = ~out_romask_557; // @[RegisterRouter.scala:87:24] wire _out_T_5663 = ~out_womask_557; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_470 = {hi_106, flags_0_go, _out_prepend_T_470}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5664 = out_prepend_470; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5665 = _out_T_5664; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_471 = _out_T_5665; // @[RegisterRouter.scala:87:24] wire out_rimask_558 = \|_out_rimask_T_558; // @[RegisterRouter.scala:87:24] wire out_wimask_558 = &_out_wimask_T_558; // @[RegisterRouter.scala:87:24] wire out_romask_558 = \|_out_romask_T_558; // @[RegisterRouter.scala:87:24] wire out_womask_558 = &_out_womask_T_558; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_558 = out_rivalid_1_412 & out_rimask_558; // @[RegisterRouter.scala:87:24] wire _out_T_5667 = out_f_rivalid_558; // @[RegisterRouter.scala:87:24] wire out_f_roready_558 = out_roready_1_412 & out_romask_558; // @[RegisterRouter.scala:87:24] wire _out_T_5668 = out_f_roready_558; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_558 = out_wivalid_1_412 & out_wimask_558; // @[RegisterRouter.scala:87:24] wire out_f_woready_558 = out_woready_1_412 & out_womask_558; // @[RegisterRouter.scala:87:24] wire _out_T_5669 = ~out_rimask_558; // @[RegisterRouter.scala:87:24] wire _out_T_5670 = ~out_wimask_558; // @[RegisterRouter.scala:87:24] wire _out_T_5671 = ~out_romask_558; // @[RegisterRouter.scala:87:24] wire _out_T_5672 = ~out_womask_558; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_471 = {hi_107, flags_0_go, _out_prepend_T_471}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5673 = out_prepend_471; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5674 = _out_T_5673; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_472 = _out_T_5674; // @[RegisterRouter.scala:87:24] wire out_rimask_559 = \|_out_rimask_T_559; // @[RegisterRouter.scala:87:24] wire out_wimask_559 = &_out_wimask_T_559; // @[RegisterRouter.scala:87:24] wire out_romask_559 = \|_out_romask_T_559; // @[RegisterRouter.scala:87:24] wire out_womask_559 = &_out_womask_T_559; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_559 = out_rivalid_1_413 & out_rimask_559; // @[RegisterRouter.scala:87:24] wire _out_T_5676 = out_f_rivalid_559; // @[RegisterRouter.scala:87:24] wire out_f_roready_559 = out_roready_1_413 & out_romask_559; // @[RegisterRouter.scala:87:24] wire _out_T_5677 = out_f_roready_559; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_559 = out_wivalid_1_413 & out_wimask_559; // @[RegisterRouter.scala:87:24] wire out_f_woready_559 = out_woready_1_413 & out_womask_559; // @[RegisterRouter.scala:87:24] wire _out_T_5678 = ~out_rimask_559; // @[RegisterRouter.scala:87:24] wire _out_T_5679 = ~out_wimask_559; // @[RegisterRouter.scala:87:24] wire _out_T_5680 = ~out_romask_559; // @[RegisterRouter.scala:87:24] wire _out_T_5681 = ~out_womask_559; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_472 = {hi_108, flags_0_go, _out_prepend_T_472}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5682 = out_prepend_472; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5683 = _out_T_5682; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_473 = _out_T_5683; // @[RegisterRouter.scala:87:24] wire out_rimask_560 = \|_out_rimask_T_560; // @[RegisterRouter.scala:87:24] wire out_wimask_560 = &_out_wimask_T_560; // @[RegisterRouter.scala:87:24] wire out_romask_560 = \|_out_romask_T_560; // @[RegisterRouter.scala:87:24] wire out_womask_560 = &_out_womask_T_560; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_560 = out_rivalid_1_414 & out_rimask_560; // @[RegisterRouter.scala:87:24] wire _out_T_5685 = out_f_rivalid_560; // @[RegisterRouter.scala:87:24] wire out_f_roready_560 = out_roready_1_414 & out_romask_560; // @[RegisterRouter.scala:87:24] wire _out_T_5686 = out_f_roready_560; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_560 = out_wivalid_1_414 & out_wimask_560; // @[RegisterRouter.scala:87:24] wire out_f_woready_560 = out_woready_1_414 & out_womask_560; // @[RegisterRouter.scala:87:24] wire _out_T_5687 = ~out_rimask_560; // @[RegisterRouter.scala:87:24] wire _out_T_5688 = ~out_wimask_560; // @[RegisterRouter.scala:87:24] wire _out_T_5689 = ~out_romask_560; // @[RegisterRouter.scala:87:24] wire _out_T_5690 = ~out_womask_560; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_473 = {hi_109, flags_0_go, _out_prepend_T_473}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5691 = out_prepend_473; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5692 = _out_T_5691; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_474 = _out_T_5692; // @[RegisterRouter.scala:87:24] wire out_rimask_561 = \|_out_rimask_T_561; // @[RegisterRouter.scala:87:24] wire out_wimask_561 = &_out_wimask_T_561; // @[RegisterRouter.scala:87:24] wire out_romask_561 = \|_out_romask_T_561; // @[RegisterRouter.scala:87:24] wire out_womask_561 = &_out_womask_T_561; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_561 = out_rivalid_1_415 & out_rimask_561; // @[RegisterRouter.scala:87:24] wire _out_T_5694 = out_f_rivalid_561; // @[RegisterRouter.scala:87:24] wire out_f_roready_561 = out_roready_1_415 & out_romask_561; // @[RegisterRouter.scala:87:24] wire _out_T_5695 = out_f_roready_561; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_561 = out_wivalid_1_415 & out_wimask_561; // @[RegisterRouter.scala:87:24] wire out_f_woready_561 = out_woready_1_415 & out_womask_561; // @[RegisterRouter.scala:87:24] wire _out_T_5696 = ~out_rimask_561; // @[RegisterRouter.scala:87:24] wire _out_T_5697 = ~out_wimask_561; // @[RegisterRouter.scala:87:24] wire _out_T_5698 = ~out_romask_561; // @[RegisterRouter.scala:87:24] wire _out_T_5699 = ~out_womask_561; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_474 = {hi_110, flags_0_go, _out_prepend_T_474}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5700 = out_prepend_474; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5701 = _out_T_5700; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_475 = _out_T_5701; // @[RegisterRouter.scala:87:24] wire out_rimask_562 = \|_out_rimask_T_562; // @[RegisterRouter.scala:87:24] wire out_wimask_562 = &_out_wimask_T_562; // @[RegisterRouter.scala:87:24] wire out_romask_562 = \|_out_romask_T_562; // @[RegisterRouter.scala:87:24] wire out_womask_562 = &_out_womask_T_562; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_562 = out_rivalid_1_416 & out_rimask_562; // @[RegisterRouter.scala:87:24] wire _out_T_5703 = out_f_rivalid_562; // @[RegisterRouter.scala:87:24] wire out_f_roready_562 = out_roready_1_416 & out_romask_562; // @[RegisterRouter.scala:87:24] wire _out_T_5704 = out_f_roready_562; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_562 = out_wivalid_1_416 & out_wimask_562; // @[RegisterRouter.scala:87:24] wire out_f_woready_562 = out_woready_1_416 & out_womask_562; // @[RegisterRouter.scala:87:24] wire _out_T_5705 = ~out_rimask_562; // @[RegisterRouter.scala:87:24] wire _out_T_5706 = ~out_wimask_562; // @[RegisterRouter.scala:87:24] wire _out_T_5707 = ~out_romask_562; // @[RegisterRouter.scala:87:24] wire _out_T_5708 = ~out_womask_562; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_475 = {hi_111, flags_0_go, _out_prepend_T_475}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5709 = out_prepend_475; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5710 = _out_T_5709; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_476 = _out_T_5710; // @[RegisterRouter.scala:87:24] wire out_rimask_563 = \|_out_rimask_T_563; // @[RegisterRouter.scala:87:24] wire out_wimask_563 = &_out_wimask_T_563; // @[RegisterRouter.scala:87:24] wire out_romask_563 = \|_out_romask_T_563; // @[RegisterRouter.scala:87:24] wire out_womask_563 = &_out_womask_T_563; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_563 = out_rivalid_1_417 & out_rimask_563; // @[RegisterRouter.scala:87:24] wire _out_T_5712 = out_f_rivalid_563; // @[RegisterRouter.scala:87:24] wire out_f_roready_563 = out_roready_1_417 & out_romask_563; // @[RegisterRouter.scala:87:24] wire _out_T_5713 = out_f_roready_563; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_563 = out_wivalid_1_417 & out_wimask_563; // @[RegisterRouter.scala:87:24] wire out_f_woready_563 = out_woready_1_417 & out_womask_563; // @[RegisterRouter.scala:87:24] wire _out_T_5714 = ~out_rimask_563; // @[RegisterRouter.scala:87:24] wire _out_T_5715 = ~out_wimask_563; // @[RegisterRouter.scala:87:24] wire _out_T_5716 = ~out_romask_563; // @[RegisterRouter.scala:87:24] wire _out_T_5717 = ~out_womask_563; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_476 = {hi_112, flags_0_go, _out_prepend_T_476}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5718 = out_prepend_476; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5719 = _out_T_5718; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_141 = _out_T_5719; // @[MuxLiteral.scala:49:48] wire out_rimask_564 = \|_out_rimask_T_564; // @[RegisterRouter.scala:87:24] wire out_wimask_564 = &_out_wimask_T_564; // @[RegisterRouter.scala:87:24] wire out_romask_564 = \|_out_romask_T_564; // @[RegisterRouter.scala:87:24] wire out_womask_564 = &_out_womask_T_564; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_564 = out_rivalid_1_418 & out_rimask_564; // @[RegisterRouter.scala:87:24] wire _out_T_5721 = out_f_rivalid_564; // @[RegisterRouter.scala:87:24] wire out_f_roready_564 = out_roready_1_418 & out_romask_564; // @[RegisterRouter.scala:87:24] wire _out_T_5722 = out_f_roready_564; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_564 = out_wivalid_1_418 & out_wimask_564; // @[RegisterRouter.scala:87:24] wire out_f_woready_564 = out_woready_1_418 & out_womask_564; // @[RegisterRouter.scala:87:24] wire _out_T_5723 = ~out_rimask_564; // @[RegisterRouter.scala:87:24] wire _out_T_5724 = ~out_wimask_564; // @[RegisterRouter.scala:87:24] wire _out_T_5725 = ~out_romask_564; // @[RegisterRouter.scala:87:24] wire _out_T_5726 = ~out_womask_564; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5728 = _out_T_5727; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_477 = _out_T_5728; // @[RegisterRouter.scala:87:24] wire out_rimask_565 = \|_out_rimask_T_565; // @[RegisterRouter.scala:87:24] wire out_wimask_565 = &_out_wimask_T_565; // @[RegisterRouter.scala:87:24] wire out_romask_565 = \|_out_romask_T_565; // @[RegisterRouter.scala:87:24] wire out_womask_565 = &_out_womask_T_565; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_565 = out_rivalid_1_419 & out_rimask_565; // @[RegisterRouter.scala:87:24] wire _out_T_5730 = out_f_rivalid_565; // @[RegisterRouter.scala:87:24] wire out_f_roready_565 = out_roready_1_419 & out_romask_565; // @[RegisterRouter.scala:87:24] wire _out_T_5731 = out_f_roready_565; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_565 = out_wivalid_1_419 & out_wimask_565; // @[RegisterRouter.scala:87:24] wire out_f_woready_565 = out_woready_1_419 & out_womask_565; // @[RegisterRouter.scala:87:24] wire _out_T_5732 = ~out_rimask_565; // @[RegisterRouter.scala:87:24] wire _out_T_5733 = ~out_wimask_565; // @[RegisterRouter.scala:87:24] wire _out_T_5734 = ~out_romask_565; // @[RegisterRouter.scala:87:24] wire _out_T_5735 = ~out_womask_565; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_477 = {hi_778, flags_0_go, _out_prepend_T_477}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5736 = out_prepend_477; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5737 = _out_T_5736; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_478 = _out_T_5737; // @[RegisterRouter.scala:87:24] wire out_rimask_566 = \|_out_rimask_T_566; // @[RegisterRouter.scala:87:24] wire out_wimask_566 = &_out_wimask_T_566; // @[RegisterRouter.scala:87:24] wire out_romask_566 = \|_out_romask_T_566; // @[RegisterRouter.scala:87:24] wire out_womask_566 = &_out_womask_T_566; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_566 = out_rivalid_1_420 & out_rimask_566; // @[RegisterRouter.scala:87:24] wire _out_T_5739 = out_f_rivalid_566; // @[RegisterRouter.scala:87:24] wire out_f_roready_566 = out_roready_1_420 & out_romask_566; // @[RegisterRouter.scala:87:24] wire _out_T_5740 = out_f_roready_566; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_566 = out_wivalid_1_420 & out_wimask_566; // @[RegisterRouter.scala:87:24] wire out_f_woready_566 = out_woready_1_420 & out_womask_566; // @[RegisterRouter.scala:87:24] wire _out_T_5741 = ~out_rimask_566; // @[RegisterRouter.scala:87:24] wire _out_T_5742 = ~out_wimask_566; // @[RegisterRouter.scala:87:24] wire _out_T_5743 = ~out_romask_566; // @[RegisterRouter.scala:87:24] wire _out_T_5744 = ~out_womask_566; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_478 = {hi_779, flags_0_go, _out_prepend_T_478}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5745 = out_prepend_478; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5746 = _out_T_5745; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_479 = _out_T_5746; // @[RegisterRouter.scala:87:24] wire out_rimask_567 = \|_out_rimask_T_567; // @[RegisterRouter.scala:87:24] wire out_wimask_567 = &_out_wimask_T_567; // @[RegisterRouter.scala:87:24] wire out_romask_567 = \|_out_romask_T_567; // @[RegisterRouter.scala:87:24] wire out_womask_567 = &_out_womask_T_567; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_567 = out_rivalid_1_421 & out_rimask_567; // @[RegisterRouter.scala:87:24] wire _out_T_5748 = out_f_rivalid_567; // @[RegisterRouter.scala:87:24] wire out_f_roready_567 = out_roready_1_421 & out_romask_567; // @[RegisterRouter.scala:87:24] wire _out_T_5749 = out_f_roready_567; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_567 = out_wivalid_1_421 & out_wimask_567; // @[RegisterRouter.scala:87:24] wire out_f_woready_567 = out_woready_1_421 & out_womask_567; // @[RegisterRouter.scala:87:24] wire _out_T_5750 = ~out_rimask_567; // @[RegisterRouter.scala:87:24] wire _out_T_5751 = ~out_wimask_567; // @[RegisterRouter.scala:87:24] wire _out_T_5752 = ~out_romask_567; // @[RegisterRouter.scala:87:24] wire _out_T_5753 = ~out_womask_567; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_479 = {hi_780, flags_0_go, _out_prepend_T_479}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5754 = out_prepend_479; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5755 = _out_T_5754; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_480 = _out_T_5755; // @[RegisterRouter.scala:87:24] wire out_rimask_568 = \|_out_rimask_T_568; // @[RegisterRouter.scala:87:24] wire out_wimask_568 = &_out_wimask_T_568; // @[RegisterRouter.scala:87:24] wire out_romask_568 = \|_out_romask_T_568; // @[RegisterRouter.scala:87:24] wire out_womask_568 = &_out_womask_T_568; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_568 = out_rivalid_1_422 & out_rimask_568; // @[RegisterRouter.scala:87:24] wire _out_T_5757 = out_f_rivalid_568; // @[RegisterRouter.scala:87:24] wire out_f_roready_568 = out_roready_1_422 & out_romask_568; // @[RegisterRouter.scala:87:24] wire _out_T_5758 = out_f_roready_568; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_568 = out_wivalid_1_422 & out_wimask_568; // @[RegisterRouter.scala:87:24] wire out_f_woready_568 = out_woready_1_422 & out_womask_568; // @[RegisterRouter.scala:87:24] wire _out_T_5759 = ~out_rimask_568; // @[RegisterRouter.scala:87:24] wire _out_T_5760 = ~out_wimask_568; // @[RegisterRouter.scala:87:24] wire _out_T_5761 = ~out_romask_568; // @[RegisterRouter.scala:87:24] wire _out_T_5762 = ~out_womask_568; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_480 = {hi_781, flags_0_go, _out_prepend_T_480}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5763 = out_prepend_480; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5764 = _out_T_5763; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_481 = _out_T_5764; // @[RegisterRouter.scala:87:24] wire out_rimask_569 = \|_out_rimask_T_569; // @[RegisterRouter.scala:87:24] wire out_wimask_569 = &_out_wimask_T_569; // @[RegisterRouter.scala:87:24] wire out_romask_569 = \|_out_romask_T_569; // @[RegisterRouter.scala:87:24] wire out_womask_569 = &_out_womask_T_569; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_569 = out_rivalid_1_423 & out_rimask_569; // @[RegisterRouter.scala:87:24] wire _out_T_5766 = out_f_rivalid_569; // @[RegisterRouter.scala:87:24] wire out_f_roready_569 = out_roready_1_423 & out_romask_569; // @[RegisterRouter.scala:87:24] wire _out_T_5767 = out_f_roready_569; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_569 = out_wivalid_1_423 & out_wimask_569; // @[RegisterRouter.scala:87:24] wire out_f_woready_569 = out_woready_1_423 & out_womask_569; // @[RegisterRouter.scala:87:24] wire _out_T_5768 = ~out_rimask_569; // @[RegisterRouter.scala:87:24] wire _out_T_5769 = ~out_wimask_569; // @[RegisterRouter.scala:87:24] wire _out_T_5770 = ~out_romask_569; // @[RegisterRouter.scala:87:24] wire _out_T_5771 = ~out_womask_569; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_481 = {hi_782, flags_0_go, _out_prepend_T_481}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5772 = out_prepend_481; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5773 = _out_T_5772; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_482 = _out_T_5773; // @[RegisterRouter.scala:87:24] wire out_rimask_570 = \|_out_rimask_T_570; // @[RegisterRouter.scala:87:24] wire out_wimask_570 = &_out_wimask_T_570; // @[RegisterRouter.scala:87:24] wire out_romask_570 = \|_out_romask_T_570; // @[RegisterRouter.scala:87:24] wire out_womask_570 = &_out_womask_T_570; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_570 = out_rivalid_1_424 & out_rimask_570; // @[RegisterRouter.scala:87:24] wire _out_T_5775 = out_f_rivalid_570; // @[RegisterRouter.scala:87:24] wire out_f_roready_570 = out_roready_1_424 & out_romask_570; // @[RegisterRouter.scala:87:24] wire _out_T_5776 = out_f_roready_570; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_570 = out_wivalid_1_424 & out_wimask_570; // @[RegisterRouter.scala:87:24] wire out_f_woready_570 = out_woready_1_424 & out_womask_570; // @[RegisterRouter.scala:87:24] wire _out_T_5777 = ~out_rimask_570; // @[RegisterRouter.scala:87:24] wire _out_T_5778 = ~out_wimask_570; // @[RegisterRouter.scala:87:24] wire _out_T_5779 = ~out_romask_570; // @[RegisterRouter.scala:87:24] wire _out_T_5780 = ~out_womask_570; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_482 = {hi_783, flags_0_go, _out_prepend_T_482}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5781 = out_prepend_482; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5782 = _out_T_5781; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_483 = _out_T_5782; // @[RegisterRouter.scala:87:24] wire out_rimask_571 = \|_out_rimask_T_571; // @[RegisterRouter.scala:87:24] wire out_wimask_571 = &_out_wimask_T_571; // @[RegisterRouter.scala:87:24] wire out_romask_571 = \|_out_romask_T_571; // @[RegisterRouter.scala:87:24] wire out_womask_571 = &_out_womask_T_571; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_571 = out_rivalid_1_425 & out_rimask_571; // @[RegisterRouter.scala:87:24] wire _out_T_5784 = out_f_rivalid_571; // @[RegisterRouter.scala:87:24] wire out_f_roready_571 = out_roready_1_425 & out_romask_571; // @[RegisterRouter.scala:87:24] wire _out_T_5785 = out_f_roready_571; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_571 = out_wivalid_1_425 & out_wimask_571; // @[RegisterRouter.scala:87:24] wire out_f_woready_571 = out_woready_1_425 & out_womask_571; // @[RegisterRouter.scala:87:24] wire _out_T_5786 = ~out_rimask_571; // @[RegisterRouter.scala:87:24] wire _out_T_5787 = ~out_wimask_571; // @[RegisterRouter.scala:87:24] wire _out_T_5788 = ~out_romask_571; // @[RegisterRouter.scala:87:24] wire _out_T_5789 = ~out_womask_571; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_483 = {hi_784, flags_0_go, _out_prepend_T_483}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5790 = out_prepend_483; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5791 = _out_T_5790; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_225 = _out_T_5791; // @[MuxLiteral.scala:49:48] wire out_rimask_572 = \|_out_rimask_T_572; // @[RegisterRouter.scala:87:24] wire out_wimask_572 = &_out_wimask_T_572; // @[RegisterRouter.scala:87:24] wire out_romask_572 = \|_out_romask_T_572; // @[RegisterRouter.scala:87:24] wire out_womask_572 = &_out_womask_T_572; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_572 = out_rivalid_1_426 & out_rimask_572; // @[RegisterRouter.scala:87:24] wire _out_T_5793 = out_f_rivalid_572; // @[RegisterRouter.scala:87:24] wire out_f_roready_572 = out_roready_1_426 & out_romask_572; // @[RegisterRouter.scala:87:24] wire _out_T_5794 = out_f_roready_572; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_572 = out_wivalid_1_426 & out_wimask_572; // @[RegisterRouter.scala:87:24] wire out_f_woready_572 = out_woready_1_426 & out_womask_572; // @[RegisterRouter.scala:87:24] wire _out_T_5795 = ~out_rimask_572; // @[RegisterRouter.scala:87:24] wire _out_T_5796 = ~out_wimask_572; // @[RegisterRouter.scala:87:24] wire _out_T_5797 = ~out_romask_572; // @[RegisterRouter.scala:87:24] wire _out_T_5798 = ~out_womask_572; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5800 = _out_T_5799; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_484 = _out_T_5800; // @[RegisterRouter.scala:87:24] wire out_rimask_573 = \|_out_rimask_T_573; // @[RegisterRouter.scala:87:24] wire out_wimask_573 = &_out_wimask_T_573; // @[RegisterRouter.scala:87:24] wire out_romask_573 = \|_out_romask_T_573; // @[RegisterRouter.scala:87:24] wire out_womask_573 = &_out_womask_T_573; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_573 = out_rivalid_1_427 & out_rimask_573; // @[RegisterRouter.scala:87:24] wire _out_T_5802 = out_f_rivalid_573; // @[RegisterRouter.scala:87:24] wire out_f_roready_573 = out_roready_1_427 & out_romask_573; // @[RegisterRouter.scala:87:24] wire _out_T_5803 = out_f_roready_573; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_573 = out_wivalid_1_427 & out_wimask_573; // @[RegisterRouter.scala:87:24] wire out_f_woready_573 = out_woready_1_427 & out_womask_573; // @[RegisterRouter.scala:87:24] wire _out_T_5804 = ~out_rimask_573; // @[RegisterRouter.scala:87:24] wire _out_T_5805 = ~out_wimask_573; // @[RegisterRouter.scala:87:24] wire _out_T_5806 = ~out_romask_573; // @[RegisterRouter.scala:87:24] wire _out_T_5807 = ~out_womask_573; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_484 = {hi_522, flags_0_go, _out_prepend_T_484}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5808 = out_prepend_484; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5809 = _out_T_5808; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_485 = _out_T_5809; // @[RegisterRouter.scala:87:24] wire out_rimask_574 = \|_out_rimask_T_574; // @[RegisterRouter.scala:87:24] wire out_wimask_574 = &_out_wimask_T_574; // @[RegisterRouter.scala:87:24] wire out_romask_574 = \|_out_romask_T_574; // @[RegisterRouter.scala:87:24] wire out_womask_574 = &_out_womask_T_574; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_574 = out_rivalid_1_428 & out_rimask_574; // @[RegisterRouter.scala:87:24] wire _out_T_5811 = out_f_rivalid_574; // @[RegisterRouter.scala:87:24] wire out_f_roready_574 = out_roready_1_428 & out_romask_574; // @[RegisterRouter.scala:87:24] wire _out_T_5812 = out_f_roready_574; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_574 = out_wivalid_1_428 & out_wimask_574; // @[RegisterRouter.scala:87:24] wire out_f_woready_574 = out_woready_1_428 & out_womask_574; // @[RegisterRouter.scala:87:24] wire _out_T_5813 = ~out_rimask_574; // @[RegisterRouter.scala:87:24] wire _out_T_5814 = ~out_wimask_574; // @[RegisterRouter.scala:87:24] wire _out_T_5815 = ~out_romask_574; // @[RegisterRouter.scala:87:24] wire _out_T_5816 = ~out_womask_574; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_485 = {hi_523, flags_0_go, _out_prepend_T_485}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5817 = out_prepend_485; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5818 = _out_T_5817; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_486 = _out_T_5818; // @[RegisterRouter.scala:87:24] wire out_rimask_575 = \|_out_rimask_T_575; // @[RegisterRouter.scala:87:24] wire out_wimask_575 = &_out_wimask_T_575; // @[RegisterRouter.scala:87:24] wire out_romask_575 = \|_out_romask_T_575; // @[RegisterRouter.scala:87:24] wire out_womask_575 = &_out_womask_T_575; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_575 = out_rivalid_1_429 & out_rimask_575; // @[RegisterRouter.scala:87:24] wire _out_T_5820 = out_f_rivalid_575; // @[RegisterRouter.scala:87:24] wire out_f_roready_575 = out_roready_1_429 & out_romask_575; // @[RegisterRouter.scala:87:24] wire _out_T_5821 = out_f_roready_575; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_575 = out_wivalid_1_429 & out_wimask_575; // @[RegisterRouter.scala:87:24] wire out_f_woready_575 = out_woready_1_429 & out_womask_575; // @[RegisterRouter.scala:87:24] wire _out_T_5822 = ~out_rimask_575; // @[RegisterRouter.scala:87:24] wire _out_T_5823 = ~out_wimask_575; // @[RegisterRouter.scala:87:24] wire _out_T_5824 = ~out_romask_575; // @[RegisterRouter.scala:87:24] wire _out_T_5825 = ~out_womask_575; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_486 = {hi_524, flags_0_go, _out_prepend_T_486}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5826 = out_prepend_486; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5827 = _out_T_5826; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_487 = _out_T_5827; // @[RegisterRouter.scala:87:24] wire out_rimask_576 = \|_out_rimask_T_576; // @[RegisterRouter.scala:87:24] wire out_wimask_576 = &_out_wimask_T_576; // @[RegisterRouter.scala:87:24] wire out_romask_576 = \|_out_romask_T_576; // @[RegisterRouter.scala:87:24] wire out_womask_576 = &_out_womask_T_576; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_576 = out_rivalid_1_430 & out_rimask_576; // @[RegisterRouter.scala:87:24] wire _out_T_5829 = out_f_rivalid_576; // @[RegisterRouter.scala:87:24] wire out_f_roready_576 = out_roready_1_430 & out_romask_576; // @[RegisterRouter.scala:87:24] wire _out_T_5830 = out_f_roready_576; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_576 = out_wivalid_1_430 & out_wimask_576; // @[RegisterRouter.scala:87:24] wire out_f_woready_576 = out_woready_1_430 & out_womask_576; // @[RegisterRouter.scala:87:24] wire _out_T_5831 = ~out_rimask_576; // @[RegisterRouter.scala:87:24] wire _out_T_5832 = ~out_wimask_576; // @[RegisterRouter.scala:87:24] wire _out_T_5833 = ~out_romask_576; // @[RegisterRouter.scala:87:24] wire _out_T_5834 = ~out_womask_576; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_487 = {hi_525, flags_0_go, _out_prepend_T_487}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5835 = out_prepend_487; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5836 = _out_T_5835; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_488 = _out_T_5836; // @[RegisterRouter.scala:87:24] wire out_rimask_577 = \|_out_rimask_T_577; // @[RegisterRouter.scala:87:24] wire out_wimask_577 = &_out_wimask_T_577; // @[RegisterRouter.scala:87:24] wire out_romask_577 = \|_out_romask_T_577; // @[RegisterRouter.scala:87:24] wire out_womask_577 = &_out_womask_T_577; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_577 = out_rivalid_1_431 & out_rimask_577; // @[RegisterRouter.scala:87:24] wire _out_T_5838 = out_f_rivalid_577; // @[RegisterRouter.scala:87:24] wire out_f_roready_577 = out_roready_1_431 & out_romask_577; // @[RegisterRouter.scala:87:24] wire _out_T_5839 = out_f_roready_577; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_577 = out_wivalid_1_431 & out_wimask_577; // @[RegisterRouter.scala:87:24] wire out_f_woready_577 = out_woready_1_431 & out_womask_577; // @[RegisterRouter.scala:87:24] wire _out_T_5840 = ~out_rimask_577; // @[RegisterRouter.scala:87:24] wire _out_T_5841 = ~out_wimask_577; // @[RegisterRouter.scala:87:24] wire _out_T_5842 = ~out_romask_577; // @[RegisterRouter.scala:87:24] wire _out_T_5843 = ~out_womask_577; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_488 = {hi_526, flags_0_go, _out_prepend_T_488}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5844 = out_prepend_488; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5845 = _out_T_5844; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_489 = _out_T_5845; // @[RegisterRouter.scala:87:24] wire out_rimask_578 = \|_out_rimask_T_578; // @[RegisterRouter.scala:87:24] wire out_wimask_578 = &_out_wimask_T_578; // @[RegisterRouter.scala:87:24] wire out_romask_578 = \|_out_romask_T_578; // @[RegisterRouter.scala:87:24] wire out_womask_578 = &_out_womask_T_578; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_578 = out_rivalid_1_432 & out_rimask_578; // @[RegisterRouter.scala:87:24] wire _out_T_5847 = out_f_rivalid_578; // @[RegisterRouter.scala:87:24] wire out_f_roready_578 = out_roready_1_432 & out_romask_578; // @[RegisterRouter.scala:87:24] wire _out_T_5848 = out_f_roready_578; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_578 = out_wivalid_1_432 & out_wimask_578; // @[RegisterRouter.scala:87:24] wire out_f_woready_578 = out_woready_1_432 & out_womask_578; // @[RegisterRouter.scala:87:24] wire _out_T_5849 = ~out_rimask_578; // @[RegisterRouter.scala:87:24] wire _out_T_5850 = ~out_wimask_578; // @[RegisterRouter.scala:87:24] wire _out_T_5851 = ~out_romask_578; // @[RegisterRouter.scala:87:24] wire _out_T_5852 = ~out_womask_578; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_489 = {hi_527, flags_0_go, _out_prepend_T_489}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5853 = out_prepend_489; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5854 = _out_T_5853; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_490 = _out_T_5854; // @[RegisterRouter.scala:87:24] wire out_rimask_579 = \|_out_rimask_T_579; // @[RegisterRouter.scala:87:24] wire out_wimask_579 = &_out_wimask_T_579; // @[RegisterRouter.scala:87:24] wire out_romask_579 = \|_out_romask_T_579; // @[RegisterRouter.scala:87:24] wire out_womask_579 = &_out_womask_T_579; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_579 = out_rivalid_1_433 & out_rimask_579; // @[RegisterRouter.scala:87:24] wire _out_T_5856 = out_f_rivalid_579; // @[RegisterRouter.scala:87:24] wire out_f_roready_579 = out_roready_1_433 & out_romask_579; // @[RegisterRouter.scala:87:24] wire _out_T_5857 = out_f_roready_579; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_579 = out_wivalid_1_433 & out_wimask_579; // @[RegisterRouter.scala:87:24] wire out_f_woready_579 = out_woready_1_433 & out_womask_579; // @[RegisterRouter.scala:87:24] wire _out_T_5858 = ~out_rimask_579; // @[RegisterRouter.scala:87:24] wire _out_T_5859 = ~out_wimask_579; // @[RegisterRouter.scala:87:24] wire _out_T_5860 = ~out_romask_579; // @[RegisterRouter.scala:87:24] wire _out_T_5861 = ~out_womask_579; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_490 = {hi_528, flags_0_go, _out_prepend_T_490}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5862 = out_prepend_490; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5863 = _out_T_5862; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_193 = _out_T_5863; // @[MuxLiteral.scala:49:48] wire out_rimask_580 = \|_out_rimask_T_580; // @[RegisterRouter.scala:87:24] wire out_wimask_580 = &_out_wimask_T_580; // @[RegisterRouter.scala:87:24] wire out_romask_580 = \|_out_romask_T_580; // @[RegisterRouter.scala:87:24] wire out_womask_580 = &_out_womask_T_580; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_580 = out_rivalid_1_434 & out_rimask_580; // @[RegisterRouter.scala:87:24] wire _out_T_5865 = out_f_rivalid_580; // @[RegisterRouter.scala:87:24] wire out_f_roready_580 = out_roready_1_434 & out_romask_580; // @[RegisterRouter.scala:87:24] wire _out_T_5866 = out_f_roready_580; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_580 = out_wivalid_1_434 & out_wimask_580; // @[RegisterRouter.scala:87:24] wire out_f_woready_580 = out_woready_1_434 & out_womask_580; // @[RegisterRouter.scala:87:24] wire _out_T_5867 = ~out_rimask_580; // @[RegisterRouter.scala:87:24] wire _out_T_5868 = ~out_wimask_580; // @[RegisterRouter.scala:87:24] wire _out_T_5869 = ~out_romask_580; // @[RegisterRouter.scala:87:24] wire _out_T_5870 = ~out_womask_580; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5872 = _out_T_5871; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_491 = _out_T_5872; // @[RegisterRouter.scala:87:24] wire out_rimask_581 = \|_out_rimask_T_581; // @[RegisterRouter.scala:87:24] wire out_wimask_581 = &_out_wimask_T_581; // @[RegisterRouter.scala:87:24] wire out_romask_581 = \|_out_romask_T_581; // @[RegisterRouter.scala:87:24] wire out_womask_581 = &_out_womask_T_581; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_581 = out_rivalid_1_435 & out_rimask_581; // @[RegisterRouter.scala:87:24] wire _out_T_5874 = out_f_rivalid_581; // @[RegisterRouter.scala:87:24] wire out_f_roready_581 = out_roready_1_435 & out_romask_581; // @[RegisterRouter.scala:87:24] wire _out_T_5875 = out_f_roready_581; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_581 = out_wivalid_1_435 & out_wimask_581; // @[RegisterRouter.scala:87:24] wire out_f_woready_581 = out_woready_1_435 & out_womask_581; // @[RegisterRouter.scala:87:24] wire _out_T_5876 = ~out_rimask_581; // @[RegisterRouter.scala:87:24] wire _out_T_5877 = ~out_wimask_581; // @[RegisterRouter.scala:87:24] wire _out_T_5878 = ~out_romask_581; // @[RegisterRouter.scala:87:24] wire _out_T_5879 = ~out_womask_581; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_491 = {hi_674, flags_0_go, _out_prepend_T_491}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5880 = out_prepend_491; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5881 = _out_T_5880; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_492 = _out_T_5881; // @[RegisterRouter.scala:87:24] wire out_rimask_582 = \|_out_rimask_T_582; // @[RegisterRouter.scala:87:24] wire out_wimask_582 = &_out_wimask_T_582; // @[RegisterRouter.scala:87:24] wire out_romask_582 = \|_out_romask_T_582; // @[RegisterRouter.scala:87:24] wire out_womask_582 = &_out_womask_T_582; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_582 = out_rivalid_1_436 & out_rimask_582; // @[RegisterRouter.scala:87:24] wire _out_T_5883 = out_f_rivalid_582; // @[RegisterRouter.scala:87:24] wire out_f_roready_582 = out_roready_1_436 & out_romask_582; // @[RegisterRouter.scala:87:24] wire _out_T_5884 = out_f_roready_582; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_582 = out_wivalid_1_436 & out_wimask_582; // @[RegisterRouter.scala:87:24] wire out_f_woready_582 = out_woready_1_436 & out_womask_582; // @[RegisterRouter.scala:87:24] wire _out_T_5885 = ~out_rimask_582; // @[RegisterRouter.scala:87:24] wire _out_T_5886 = ~out_wimask_582; // @[RegisterRouter.scala:87:24] wire _out_T_5887 = ~out_romask_582; // @[RegisterRouter.scala:87:24] wire _out_T_5888 = ~out_womask_582; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_492 = {hi_675, flags_0_go, _out_prepend_T_492}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5889 = out_prepend_492; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5890 = _out_T_5889; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_493 = _out_T_5890; // @[RegisterRouter.scala:87:24] wire out_rimask_583 = \|_out_rimask_T_583; // @[RegisterRouter.scala:87:24] wire out_wimask_583 = &_out_wimask_T_583; // @[RegisterRouter.scala:87:24] wire out_romask_583 = \|_out_romask_T_583; // @[RegisterRouter.scala:87:24] wire out_womask_583 = &_out_womask_T_583; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_583 = out_rivalid_1_437 & out_rimask_583; // @[RegisterRouter.scala:87:24] wire _out_T_5892 = out_f_rivalid_583; // @[RegisterRouter.scala:87:24] wire out_f_roready_583 = out_roready_1_437 & out_romask_583; // @[RegisterRouter.scala:87:24] wire _out_T_5893 = out_f_roready_583; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_583 = out_wivalid_1_437 & out_wimask_583; // @[RegisterRouter.scala:87:24] wire out_f_woready_583 = out_woready_1_437 & out_womask_583; // @[RegisterRouter.scala:87:24] wire _out_T_5894 = ~out_rimask_583; // @[RegisterRouter.scala:87:24] wire _out_T_5895 = ~out_wimask_583; // @[RegisterRouter.scala:87:24] wire _out_T_5896 = ~out_romask_583; // @[RegisterRouter.scala:87:24] wire _out_T_5897 = ~out_womask_583; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_493 = {hi_676, flags_0_go, _out_prepend_T_493}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5898 = out_prepend_493; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5899 = _out_T_5898; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_494 = _out_T_5899; // @[RegisterRouter.scala:87:24] wire out_rimask_584 = \|_out_rimask_T_584; // @[RegisterRouter.scala:87:24] wire out_wimask_584 = &_out_wimask_T_584; // @[RegisterRouter.scala:87:24] wire out_romask_584 = \|_out_romask_T_584; // @[RegisterRouter.scala:87:24] wire out_womask_584 = &_out_womask_T_584; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_584 = out_rivalid_1_438 & out_rimask_584; // @[RegisterRouter.scala:87:24] wire _out_T_5901 = out_f_rivalid_584; // @[RegisterRouter.scala:87:24] wire out_f_roready_584 = out_roready_1_438 & out_romask_584; // @[RegisterRouter.scala:87:24] wire _out_T_5902 = out_f_roready_584; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_584 = out_wivalid_1_438 & out_wimask_584; // @[RegisterRouter.scala:87:24] wire out_f_woready_584 = out_woready_1_438 & out_womask_584; // @[RegisterRouter.scala:87:24] wire _out_T_5903 = ~out_rimask_584; // @[RegisterRouter.scala:87:24] wire _out_T_5904 = ~out_wimask_584; // @[RegisterRouter.scala:87:24] wire _out_T_5905 = ~out_romask_584; // @[RegisterRouter.scala:87:24] wire _out_T_5906 = ~out_womask_584; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_494 = {hi_677, flags_0_go, _out_prepend_T_494}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5907 = out_prepend_494; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5908 = _out_T_5907; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_495 = _out_T_5908; // @[RegisterRouter.scala:87:24] wire out_rimask_585 = \|_out_rimask_T_585; // @[RegisterRouter.scala:87:24] wire out_wimask_585 = &_out_wimask_T_585; // @[RegisterRouter.scala:87:24] wire out_romask_585 = \|_out_romask_T_585; // @[RegisterRouter.scala:87:24] wire out_womask_585 = &_out_womask_T_585; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_585 = out_rivalid_1_439 & out_rimask_585; // @[RegisterRouter.scala:87:24] wire _out_T_5910 = out_f_rivalid_585; // @[RegisterRouter.scala:87:24] wire out_f_roready_585 = out_roready_1_439 & out_romask_585; // @[RegisterRouter.scala:87:24] wire _out_T_5911 = out_f_roready_585; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_585 = out_wivalid_1_439 & out_wimask_585; // @[RegisterRouter.scala:87:24] wire out_f_woready_585 = out_woready_1_439 & out_womask_585; // @[RegisterRouter.scala:87:24] wire _out_T_5912 = ~out_rimask_585; // @[RegisterRouter.scala:87:24] wire _out_T_5913 = ~out_wimask_585; // @[RegisterRouter.scala:87:24] wire _out_T_5914 = ~out_romask_585; // @[RegisterRouter.scala:87:24] wire _out_T_5915 = ~out_womask_585; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_495 = {hi_678, flags_0_go, _out_prepend_T_495}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5916 = out_prepend_495; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5917 = _out_T_5916; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_496 = _out_T_5917; // @[RegisterRouter.scala:87:24] wire out_rimask_586 = \|_out_rimask_T_586; // @[RegisterRouter.scala:87:24] wire out_wimask_586 = &_out_wimask_T_586; // @[RegisterRouter.scala:87:24] wire out_romask_586 = \|_out_romask_T_586; // @[RegisterRouter.scala:87:24] wire out_womask_586 = &_out_womask_T_586; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_586 = out_rivalid_1_440 & out_rimask_586; // @[RegisterRouter.scala:87:24] wire _out_T_5919 = out_f_rivalid_586; // @[RegisterRouter.scala:87:24] wire out_f_roready_586 = out_roready_1_440 & out_romask_586; // @[RegisterRouter.scala:87:24] wire _out_T_5920 = out_f_roready_586; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_586 = out_wivalid_1_440 & out_wimask_586; // @[RegisterRouter.scala:87:24] wire out_f_woready_586 = out_woready_1_440 & out_womask_586; // @[RegisterRouter.scala:87:24] wire _out_T_5921 = ~out_rimask_586; // @[RegisterRouter.scala:87:24] wire _out_T_5922 = ~out_wimask_586; // @[RegisterRouter.scala:87:24] wire _out_T_5923 = ~out_romask_586; // @[RegisterRouter.scala:87:24] wire _out_T_5924 = ~out_womask_586; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_496 = {hi_679, flags_0_go, _out_prepend_T_496}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5925 = out_prepend_496; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5926 = _out_T_5925; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_497 = _out_T_5926; // @[RegisterRouter.scala:87:24] wire out_rimask_587 = \|_out_rimask_T_587; // @[RegisterRouter.scala:87:24] wire out_wimask_587 = &_out_wimask_T_587; // @[RegisterRouter.scala:87:24] wire out_romask_587 = \|_out_romask_T_587; // @[RegisterRouter.scala:87:24] wire out_womask_587 = &_out_womask_T_587; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_587 = out_rivalid_1_441 & out_rimask_587; // @[RegisterRouter.scala:87:24] wire _out_T_5928 = out_f_rivalid_587; // @[RegisterRouter.scala:87:24] wire out_f_roready_587 = out_roready_1_441 & out_romask_587; // @[RegisterRouter.scala:87:24] wire _out_T_5929 = out_f_roready_587; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_587 = out_wivalid_1_441 & out_wimask_587; // @[RegisterRouter.scala:87:24] wire out_f_woready_587 = out_woready_1_441 & out_womask_587; // @[RegisterRouter.scala:87:24] wire _out_T_5930 = ~out_rimask_587; // @[RegisterRouter.scala:87:24] wire _out_T_5931 = ~out_wimask_587; // @[RegisterRouter.scala:87:24] wire _out_T_5932 = ~out_romask_587; // @[RegisterRouter.scala:87:24] wire _out_T_5933 = ~out_womask_587; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_497 = {hi_680, flags_0_go, _out_prepend_T_497}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5934 = out_prepend_497; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5935 = _out_T_5934; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_212 = _out_T_5935; // @[MuxLiteral.scala:49:48] wire [31:0] _out_rimask_T_588 = out_frontMask_1[31:0]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_wimask_T_588 = out_frontMask_1[31:0]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_rimask_T_843 = out_frontMask_1[31:0]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_wimask_T_843 = out_frontMask_1[31:0]; // @[RegisterRouter.scala:87:24] wire out_rimask_588 = \|_out_rimask_T_588; // @[RegisterRouter.scala:87:24] wire out_wimask_588 = &_out_wimask_T_588; // @[RegisterRouter.scala:87:24] wire [31:0] _out_romask_T_588 = out_backMask_1[31:0]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_womask_T_588 = out_backMask_1[31:0]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_romask_T_843 = out_backMask_1[31:0]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_womask_T_843 = out_backMask_1[31:0]; // @[RegisterRouter.scala:87:24] wire out_romask_588 = \|_out_romask_T_588; // @[RegisterRouter.scala:87:24] wire out_womask_588 = &_out_womask_T_588; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_588 = out_rivalid_1_442 & out_rimask_588; // @[RegisterRouter.scala:87:24] wire _out_T_5937 = out_f_rivalid_588; // @[RegisterRouter.scala:87:24] wire out_f_roready_588 = out_roready_1_442 & out_romask_588; // @[RegisterRouter.scala:87:24] wire _out_T_5938 = out_f_roready_588; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_588 = out_wivalid_1_442 & out_wimask_588; // @[RegisterRouter.scala:87:24] wire out_f_woready_588 = out_woready_1_442 & out_womask_588; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5936 = out_front_1_bits_data[31:0]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8279 = out_front_1_bits_data[31:0]; // @[RegisterRouter.scala:87:24] wire _out_T_5939 = ~out_rimask_588; // @[RegisterRouter.scala:87:24] wire _out_T_5940 = ~out_wimask_588; // @[RegisterRouter.scala:87:24] wire _out_T_5941 = ~out_romask_588; // @[RegisterRouter.scala:87:24] wire _out_T_5942 = ~out_womask_588; // @[RegisterRouter.scala:87:24] wire out_rimask_589 = \|_out_rimask_T_589; // @[RegisterRouter.scala:87:24] wire out_wimask_589 = &_out_wimask_T_589; // @[RegisterRouter.scala:87:24] wire out_romask_589 = \|_out_romask_T_589; // @[RegisterRouter.scala:87:24] wire out_womask_589 = &_out_womask_T_589; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_589 = out_rivalid_1_443 & out_rimask_589; // @[RegisterRouter.scala:87:24] wire _out_T_5946 = out_f_rivalid_589; // @[RegisterRouter.scala:87:24] wire out_f_roready_589 = out_roready_1_443 & out_romask_589; // @[RegisterRouter.scala:87:24] wire _out_T_5947 = out_f_roready_589; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_589 = out_wivalid_1_443 & out_wimask_589; // @[RegisterRouter.scala:87:24] wire _out_T_5948 = out_f_wivalid_589; // @[RegisterRouter.scala:87:24] wire out_f_woready_589 = out_woready_1_443 & out_womask_589; // @[RegisterRouter.scala:87:24] wire _out_T_5949 = out_f_woready_589; // @[RegisterRouter.scala:87:24] wire _out_T_5950 = ~out_rimask_589; // @[RegisterRouter.scala:87:24] wire _out_T_5951 = ~out_wimask_589; // @[RegisterRouter.scala:87:24] wire _out_T_5952 = ~out_romask_589; // @[RegisterRouter.scala:87:24] wire _out_T_5953 = ~out_womask_589; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5955 = _out_T_5954; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_498 = _out_T_5955; // @[RegisterRouter.scala:87:24] wire out_rimask_590 = \|_out_rimask_T_590; // @[RegisterRouter.scala:87:24] wire out_wimask_590 = &_out_wimask_T_590; // @[RegisterRouter.scala:87:24] wire out_romask_590 = \|_out_romask_T_590; // @[RegisterRouter.scala:87:24] wire out_womask_590 = &_out_womask_T_590; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_590 = out_rivalid_1_444 & out_rimask_590; // @[RegisterRouter.scala:87:24] wire _out_T_5957 = out_f_rivalid_590; // @[RegisterRouter.scala:87:24] wire out_f_roready_590 = out_roready_1_444 & out_romask_590; // @[RegisterRouter.scala:87:24] wire _out_T_5958 = out_f_roready_590; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_590 = out_wivalid_1_444 & out_wimask_590; // @[RegisterRouter.scala:87:24] wire _out_T_5959 = out_f_wivalid_590; // @[RegisterRouter.scala:87:24] wire out_f_woready_590 = out_woready_1_444 & out_womask_590; // @[RegisterRouter.scala:87:24] wire _out_T_5960 = out_f_woready_590; // @[RegisterRouter.scala:87:24] wire _out_T_5961 = ~out_rimask_590; // @[RegisterRouter.scala:87:24] wire _out_T_5962 = ~out_wimask_590; // @[RegisterRouter.scala:87:24] wire _out_T_5963 = ~out_romask_590; // @[RegisterRouter.scala:87:24] wire _out_T_5964 = ~out_womask_590; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_498 = {programBufferMem_41, _out_prepend_T_498}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5965 = out_prepend_498; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5966 = _out_T_5965; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_499 = _out_T_5966; // @[RegisterRouter.scala:87:24] wire out_rimask_591 = \|_out_rimask_T_591; // @[RegisterRouter.scala:87:24] wire out_wimask_591 = &_out_wimask_T_591; // @[RegisterRouter.scala:87:24] wire out_romask_591 = \|_out_romask_T_591; // @[RegisterRouter.scala:87:24] wire out_womask_591 = &_out_womask_T_591; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_591 = out_rivalid_1_445 & out_rimask_591; // @[RegisterRouter.scala:87:24] wire _out_T_5968 = out_f_rivalid_591; // @[RegisterRouter.scala:87:24] wire out_f_roready_591 = out_roready_1_445 & out_romask_591; // @[RegisterRouter.scala:87:24] wire _out_T_5969 = out_f_roready_591; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_591 = out_wivalid_1_445 & out_wimask_591; // @[RegisterRouter.scala:87:24] wire _out_T_5970 = out_f_wivalid_591; // @[RegisterRouter.scala:87:24] wire out_f_woready_591 = out_woready_1_445 & out_womask_591; // @[RegisterRouter.scala:87:24] wire _out_T_5971 = out_f_woready_591; // @[RegisterRouter.scala:87:24] wire _out_T_5972 = ~out_rimask_591; // @[RegisterRouter.scala:87:24] wire _out_T_5973 = ~out_wimask_591; // @[RegisterRouter.scala:87:24] wire _out_T_5974 = ~out_romask_591; // @[RegisterRouter.scala:87:24] wire _out_T_5975 = ~out_womask_591; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_499 = {programBufferMem_42, _out_prepend_T_499}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5976 = out_prepend_499; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5977 = _out_T_5976; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_500 = _out_T_5977; // @[RegisterRouter.scala:87:24] wire out_rimask_592 = \|_out_rimask_T_592; // @[RegisterRouter.scala:87:24] wire out_wimask_592 = &_out_wimask_T_592; // @[RegisterRouter.scala:87:24] wire out_romask_592 = \|_out_romask_T_592; // @[RegisterRouter.scala:87:24] wire out_womask_592 = &_out_womask_T_592; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_592 = out_rivalid_1_446 & out_rimask_592; // @[RegisterRouter.scala:87:24] wire _out_T_5979 = out_f_rivalid_592; // @[RegisterRouter.scala:87:24] wire out_f_roready_592 = out_roready_1_446 & out_romask_592; // @[RegisterRouter.scala:87:24] wire _out_T_5980 = out_f_roready_592; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_592 = out_wivalid_1_446 & out_wimask_592; // @[RegisterRouter.scala:87:24] wire _out_T_5981 = out_f_wivalid_592; // @[RegisterRouter.scala:87:24] wire out_f_woready_592 = out_woready_1_446 & out_womask_592; // @[RegisterRouter.scala:87:24] wire _out_T_5982 = out_f_woready_592; // @[RegisterRouter.scala:87:24] wire _out_T_5983 = ~out_rimask_592; // @[RegisterRouter.scala:87:24] wire _out_T_5984 = ~out_wimask_592; // @[RegisterRouter.scala:87:24] wire _out_T_5985 = ~out_romask_592; // @[RegisterRouter.scala:87:24] wire _out_T_5986 = ~out_womask_592; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_500 = {programBufferMem_43, _out_prepend_T_500}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5987 = out_prepend_500; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5988 = _out_T_5987; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_501 = _out_T_5988; // @[RegisterRouter.scala:87:24] wire out_rimask_593 = \|_out_rimask_T_593; // @[RegisterRouter.scala:87:24] wire out_wimask_593 = &_out_wimask_T_593; // @[RegisterRouter.scala:87:24] wire out_romask_593 = \|_out_romask_T_593; // @[RegisterRouter.scala:87:24] wire out_womask_593 = &_out_womask_T_593; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_593 = out_rivalid_1_447 & out_rimask_593; // @[RegisterRouter.scala:87:24] wire _out_T_5990 = out_f_rivalid_593; // @[RegisterRouter.scala:87:24] wire out_f_roready_593 = out_roready_1_447 & out_romask_593; // @[RegisterRouter.scala:87:24] wire _out_T_5991 = out_f_roready_593; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_593 = out_wivalid_1_447 & out_wimask_593; // @[RegisterRouter.scala:87:24] wire _out_T_5992 = out_f_wivalid_593; // @[RegisterRouter.scala:87:24] wire out_f_woready_593 = out_woready_1_447 & out_womask_593; // @[RegisterRouter.scala:87:24] wire _out_T_5993 = out_f_woready_593; // @[RegisterRouter.scala:87:24] wire _out_T_5994 = ~out_rimask_593; // @[RegisterRouter.scala:87:24] wire _out_T_5995 = ~out_wimask_593; // @[RegisterRouter.scala:87:24] wire _out_T_5996 = ~out_romask_593; // @[RegisterRouter.scala:87:24] wire _out_T_5997 = ~out_womask_593; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_501 = {programBufferMem_44, _out_prepend_T_501}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5998 = out_prepend_501; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5999 = _out_T_5998; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_502 = _out_T_5999; // @[RegisterRouter.scala:87:24] wire out_rimask_594 = \|_out_rimask_T_594; // @[RegisterRouter.scala:87:24] wire out_wimask_594 = &_out_wimask_T_594; // @[RegisterRouter.scala:87:24] wire out_romask_594 = \|_out_romask_T_594; // @[RegisterRouter.scala:87:24] wire out_womask_594 = &_out_womask_T_594; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_594 = out_rivalid_1_448 & out_rimask_594; // @[RegisterRouter.scala:87:24] wire _out_T_6001 = out_f_rivalid_594; // @[RegisterRouter.scala:87:24] wire out_f_roready_594 = out_roready_1_448 & out_romask_594; // @[RegisterRouter.scala:87:24] wire _out_T_6002 = out_f_roready_594; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_594 = out_wivalid_1_448 & out_wimask_594; // @[RegisterRouter.scala:87:24] wire _out_T_6003 = out_f_wivalid_594; // @[RegisterRouter.scala:87:24] wire out_f_woready_594 = out_woready_1_448 & out_womask_594; // @[RegisterRouter.scala:87:24] wire _out_T_6004 = out_f_woready_594; // @[RegisterRouter.scala:87:24] wire _out_T_6005 = ~out_rimask_594; // @[RegisterRouter.scala:87:24] wire _out_T_6006 = ~out_wimask_594; // @[RegisterRouter.scala:87:24] wire _out_T_6007 = ~out_romask_594; // @[RegisterRouter.scala:87:24] wire _out_T_6008 = ~out_womask_594; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_502 = {programBufferMem_45, _out_prepend_T_502}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6009 = out_prepend_502; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6010 = _out_T_6009; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_503 = _out_T_6010; // @[RegisterRouter.scala:87:24] wire out_rimask_595 = \|_out_rimask_T_595; // @[RegisterRouter.scala:87:24] wire out_wimask_595 = &_out_wimask_T_595; // @[RegisterRouter.scala:87:24] wire out_romask_595 = \|_out_romask_T_595; // @[RegisterRouter.scala:87:24] wire out_womask_595 = &_out_womask_T_595; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_595 = out_rivalid_1_449 & out_rimask_595; // @[RegisterRouter.scala:87:24] wire _out_T_6012 = out_f_rivalid_595; // @[RegisterRouter.scala:87:24] wire out_f_roready_595 = out_roready_1_449 & out_romask_595; // @[RegisterRouter.scala:87:24] wire _out_T_6013 = out_f_roready_595; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_595 = out_wivalid_1_449 & out_wimask_595; // @[RegisterRouter.scala:87:24] wire _out_T_6014 = out_f_wivalid_595; // @[RegisterRouter.scala:87:24] wire out_f_woready_595 = out_woready_1_449 & out_womask_595; // @[RegisterRouter.scala:87:24] wire _out_T_6015 = out_f_woready_595; // @[RegisterRouter.scala:87:24] wire _out_T_6016 = ~out_rimask_595; // @[RegisterRouter.scala:87:24] wire _out_T_6017 = ~out_wimask_595; // @[RegisterRouter.scala:87:24] wire _out_T_6018 = ~out_romask_595; // @[RegisterRouter.scala:87:24] wire _out_T_6019 = ~out_womask_595; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_503 = {programBufferMem_46, _out_prepend_T_503}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6020 = out_prepend_503; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6021 = _out_T_6020; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_504 = _out_T_6021; // @[RegisterRouter.scala:87:24] wire out_rimask_596 = \|_out_rimask_T_596; // @[RegisterRouter.scala:87:24] wire out_wimask_596 = &_out_wimask_T_596; // @[RegisterRouter.scala:87:24] wire out_romask_596 = \|_out_romask_T_596; // @[RegisterRouter.scala:87:24] wire out_womask_596 = &_out_womask_T_596; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_596 = out_rivalid_1_450 & out_rimask_596; // @[RegisterRouter.scala:87:24] wire _out_T_6023 = out_f_rivalid_596; // @[RegisterRouter.scala:87:24] wire out_f_roready_596 = out_roready_1_450 & out_romask_596; // @[RegisterRouter.scala:87:24] wire _out_T_6024 = out_f_roready_596; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_596 = out_wivalid_1_450 & out_wimask_596; // @[RegisterRouter.scala:87:24] wire _out_T_6025 = out_f_wivalid_596; // @[RegisterRouter.scala:87:24] wire out_f_woready_596 = out_woready_1_450 & out_womask_596; // @[RegisterRouter.scala:87:24] wire _out_T_6026 = out_f_woready_596; // @[RegisterRouter.scala:87:24] wire _out_T_6027 = ~out_rimask_596; // @[RegisterRouter.scala:87:24] wire _out_T_6028 = ~out_wimask_596; // @[RegisterRouter.scala:87:24] wire _out_T_6029 = ~out_romask_596; // @[RegisterRouter.scala:87:24] wire _out_T_6030 = ~out_womask_596; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_504 = {programBufferMem_47, _out_prepend_T_504}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6031 = out_prepend_504; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6032 = _out_T_6031; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_109 = _out_T_6032; // @[MuxLiteral.scala:49:48] wire out_rimask_597 = \|_out_rimask_T_597; // @[RegisterRouter.scala:87:24] wire out_wimask_597 = &_out_wimask_T_597; // @[RegisterRouter.scala:87:24] wire out_romask_597 = \|_out_romask_T_597; // @[RegisterRouter.scala:87:24] wire out_womask_597 = &_out_womask_T_597; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_597 = out_rivalid_1_451 & out_rimask_597; // @[RegisterRouter.scala:87:24] wire _out_T_6034 = out_f_rivalid_597; // @[RegisterRouter.scala:87:24] wire out_f_roready_597 = out_roready_1_451 & out_romask_597; // @[RegisterRouter.scala:87:24] wire _out_T_6035 = out_f_roready_597; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_597 = out_wivalid_1_451 & out_wimask_597; // @[RegisterRouter.scala:87:24] wire out_f_woready_597 = out_woready_1_451 & out_womask_597; // @[RegisterRouter.scala:87:24] wire _out_T_6036 = ~out_rimask_597; // @[RegisterRouter.scala:87:24] wire _out_T_6037 = ~out_wimask_597; // @[RegisterRouter.scala:87:24] wire _out_T_6038 = ~out_romask_597; // @[RegisterRouter.scala:87:24] wire _out_T_6039 = ~out_womask_597; // @[RegisterRouter.scala:87:24] wire out_rimask_598 = \|_out_rimask_T_598; // @[RegisterRouter.scala:87:24] wire out_wimask_598 = &_out_wimask_T_598; // @[RegisterRouter.scala:87:24] wire out_romask_598 = \|_out_romask_T_598; // @[RegisterRouter.scala:87:24] wire out_womask_598 = &_out_womask_T_598; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_598 = out_rivalid_1_452 & out_rimask_598; // @[RegisterRouter.scala:87:24] wire _out_T_6043 = out_f_rivalid_598; // @[RegisterRouter.scala:87:24] wire out_f_roready_598 = out_roready_1_452 & out_romask_598; // @[RegisterRouter.scala:87:24] wire _out_T_6044 = out_f_roready_598; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_598 = out_wivalid_1_452 & out_wimask_598; // @[RegisterRouter.scala:87:24] wire out_f_woready_598 = out_woready_1_452 & out_womask_598; // @[RegisterRouter.scala:87:24] wire _out_T_6045 = ~out_rimask_598; // @[RegisterRouter.scala:87:24] wire _out_T_6046 = ~out_wimask_598; // @[RegisterRouter.scala:87:24] wire _out_T_6047 = ~out_romask_598; // @[RegisterRouter.scala:87:24] wire _out_T_6048 = ~out_womask_598; // @[RegisterRouter.scala:87:24] wire out_rimask_599 = \|_out_rimask_T_599; // @[RegisterRouter.scala:87:24] wire out_wimask_599 = &_out_wimask_T_599; // @[RegisterRouter.scala:87:24] wire out_romask_599 = \|_out_romask_T_599; // @[RegisterRouter.scala:87:24] wire out_womask_599 = &_out_womask_T_599; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_599 = out_rivalid_1_453 & out_rimask_599; // @[RegisterRouter.scala:87:24] wire _out_T_6052 = out_f_rivalid_599; // @[RegisterRouter.scala:87:24] wire out_f_roready_599 = out_roready_1_453 & out_romask_599; // @[RegisterRouter.scala:87:24] wire _out_T_6053 = out_f_roready_599; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_599 = out_wivalid_1_453 & out_wimask_599; // @[RegisterRouter.scala:87:24] wire out_f_woready_599 = out_woready_1_453 & out_womask_599; // @[RegisterRouter.scala:87:24] wire _out_T_6054 = ~out_rimask_599; // @[RegisterRouter.scala:87:24] wire _out_T_6055 = ~out_wimask_599; // @[RegisterRouter.scala:87:24] wire _out_T_6056 = ~out_romask_599; // @[RegisterRouter.scala:87:24] wire _out_T_6057 = ~out_womask_599; // @[RegisterRouter.scala:87:24] wire out_rimask_600 = \|_out_rimask_T_600; // @[RegisterRouter.scala:87:24] wire out_wimask_600 = &_out_wimask_T_600; // @[RegisterRouter.scala:87:24] wire out_romask_600 = \|_out_romask_T_600; // @[RegisterRouter.scala:87:24] wire out_womask_600 = &_out_womask_T_600; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_600 = out_rivalid_1_454 & out_rimask_600; // @[RegisterRouter.scala:87:24] wire _out_T_6061 = out_f_rivalid_600; // @[RegisterRouter.scala:87:24] wire out_f_roready_600 = out_roready_1_454 & out_romask_600; // @[RegisterRouter.scala:87:24] wire _out_T_6062 = out_f_roready_600; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_600 = out_wivalid_1_454 & out_wimask_600; // @[RegisterRouter.scala:87:24] wire out_f_woready_600 = out_woready_1_454 & out_womask_600; // @[RegisterRouter.scala:87:24] wire _out_T_6063 = ~out_rimask_600; // @[RegisterRouter.scala:87:24] wire _out_T_6064 = ~out_wimask_600; // @[RegisterRouter.scala:87:24] wire _out_T_6065 = ~out_romask_600; // @[RegisterRouter.scala:87:24] wire _out_T_6066 = ~out_womask_600; // @[RegisterRouter.scala:87:24] wire out_rimask_601 = \|_out_rimask_T_601; // @[RegisterRouter.scala:87:24] wire out_wimask_601 = &_out_wimask_T_601; // @[RegisterRouter.scala:87:24] wire out_romask_601 = \|_out_romask_T_601; // @[RegisterRouter.scala:87:24] wire out_womask_601 = &_out_womask_T_601; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_601 = out_rivalid_1_455 & out_rimask_601; // @[RegisterRouter.scala:87:24] wire _out_T_6070 = out_f_rivalid_601; // @[RegisterRouter.scala:87:24] wire out_f_roready_601 = out_roready_1_455 & out_romask_601; // @[RegisterRouter.scala:87:24] wire _out_T_6071 = out_f_roready_601; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_601 = out_wivalid_1_455 & out_wimask_601; // @[RegisterRouter.scala:87:24] wire out_f_woready_601 = out_woready_1_455 & out_womask_601; // @[RegisterRouter.scala:87:24] wire _out_T_6072 = ~out_rimask_601; // @[RegisterRouter.scala:87:24] wire _out_T_6073 = ~out_wimask_601; // @[RegisterRouter.scala:87:24] wire _out_T_6074 = ~out_romask_601; // @[RegisterRouter.scala:87:24] wire _out_T_6075 = ~out_womask_601; // @[RegisterRouter.scala:87:24] wire out_rimask_602 = \|_out_rimask_T_602; // @[RegisterRouter.scala:87:24] wire out_wimask_602 = &_out_wimask_T_602; // @[RegisterRouter.scala:87:24] wire out_romask_602 = \|_out_romask_T_602; // @[RegisterRouter.scala:87:24] wire out_womask_602 = &_out_womask_T_602; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_602 = out_rivalid_1_456 & out_rimask_602; // @[RegisterRouter.scala:87:24] wire _out_T_6079 = out_f_rivalid_602; // @[RegisterRouter.scala:87:24] wire out_f_roready_602 = out_roready_1_456 & out_romask_602; // @[RegisterRouter.scala:87:24] wire _out_T_6080 = out_f_roready_602; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_602 = out_wivalid_1_456 & out_wimask_602; // @[RegisterRouter.scala:87:24] wire out_f_woready_602 = out_woready_1_456 & out_womask_602; // @[RegisterRouter.scala:87:24] wire _out_T_6081 = ~out_rimask_602; // @[RegisterRouter.scala:87:24] wire _out_T_6082 = ~out_wimask_602; // @[RegisterRouter.scala:87:24] wire _out_T_6083 = ~out_romask_602; // @[RegisterRouter.scala:87:24] wire _out_T_6084 = ~out_womask_602; // @[RegisterRouter.scala:87:24] wire out_rimask_603 = \|_out_rimask_T_603; // @[RegisterRouter.scala:87:24] wire out_wimask_603 = &_out_wimask_T_603; // @[RegisterRouter.scala:87:24] wire out_romask_603 = \|_out_romask_T_603; // @[RegisterRouter.scala:87:24] wire out_womask_603 = &_out_womask_T_603; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_603 = out_rivalid_1_457 & out_rimask_603; // @[RegisterRouter.scala:87:24] wire _out_T_6088 = out_f_rivalid_603; // @[RegisterRouter.scala:87:24] wire out_f_roready_603 = out_roready_1_457 & out_romask_603; // @[RegisterRouter.scala:87:24] wire _out_T_6089 = out_f_roready_603; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_603 = out_wivalid_1_457 & out_wimask_603; // @[RegisterRouter.scala:87:24] wire out_f_woready_603 = out_woready_1_457 & out_womask_603; // @[RegisterRouter.scala:87:24] wire _out_T_6090 = ~out_rimask_603; // @[RegisterRouter.scala:87:24] wire _out_T_6091 = ~out_wimask_603; // @[RegisterRouter.scala:87:24] wire _out_T_6092 = ~out_romask_603; // @[RegisterRouter.scala:87:24] wire _out_T_6093 = ~out_womask_603; // @[RegisterRouter.scala:87:24] wire out_rimask_604 = \|_out_rimask_T_604; // @[RegisterRouter.scala:87:24] wire out_wimask_604 = &_out_wimask_T_604; // @[RegisterRouter.scala:87:24] wire out_romask_604 = \|_out_romask_T_604; // @[RegisterRouter.scala:87:24] wire out_womask_604 = &_out_womask_T_604; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_604 = out_rivalid_1_458 & out_rimask_604; // @[RegisterRouter.scala:87:24] wire _out_T_6097 = out_f_rivalid_604; // @[RegisterRouter.scala:87:24] wire out_f_roready_604 = out_roready_1_458 & out_romask_604; // @[RegisterRouter.scala:87:24] wire _out_T_6098 = out_f_roready_604; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_604 = out_wivalid_1_458 & out_wimask_604; // @[RegisterRouter.scala:87:24] wire out_f_woready_604 = out_woready_1_458 & out_womask_604; // @[RegisterRouter.scala:87:24] wire _out_T_6099 = ~out_rimask_604; // @[RegisterRouter.scala:87:24] wire _out_T_6100 = ~out_wimask_604; // @[RegisterRouter.scala:87:24] wire _out_T_6101 = ~out_romask_604; // @[RegisterRouter.scala:87:24] wire _out_T_6102 = ~out_womask_604; // @[RegisterRouter.scala:87:24] wire out_rimask_605 = \|_out_rimask_T_605; // @[RegisterRouter.scala:87:24] wire out_wimask_605 = &_out_wimask_T_605; // @[RegisterRouter.scala:87:24] wire out_romask_605 = \|_out_romask_T_605; // @[RegisterRouter.scala:87:24] wire out_womask_605 = &_out_womask_T_605; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_605 = out_rivalid_1_459 & out_rimask_605; // @[RegisterRouter.scala:87:24] wire _out_T_6106 = out_f_rivalid_605; // @[RegisterRouter.scala:87:24] wire out_f_roready_605 = out_roready_1_459 & out_romask_605; // @[RegisterRouter.scala:87:24] wire _out_T_6107 = out_f_roready_605; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_605 = out_wivalid_1_459 & out_wimask_605; // @[RegisterRouter.scala:87:24] wire out_f_woready_605 = out_woready_1_459 & out_womask_605; // @[RegisterRouter.scala:87:24] wire _out_T_6108 = ~out_rimask_605; // @[RegisterRouter.scala:87:24] wire _out_T_6109 = ~out_wimask_605; // @[RegisterRouter.scala:87:24] wire _out_T_6110 = ~out_romask_605; // @[RegisterRouter.scala:87:24] wire _out_T_6111 = ~out_womask_605; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6113 = _out_T_6112; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_512 = _out_T_6113; // @[RegisterRouter.scala:87:24] wire out_rimask_606 = \|_out_rimask_T_606; // @[RegisterRouter.scala:87:24] wire out_wimask_606 = &_out_wimask_T_606; // @[RegisterRouter.scala:87:24] wire out_romask_606 = \|_out_romask_T_606; // @[RegisterRouter.scala:87:24] wire out_womask_606 = &_out_womask_T_606; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_606 = out_rivalid_1_460 & out_rimask_606; // @[RegisterRouter.scala:87:24] wire _out_T_6115 = out_f_rivalid_606; // @[RegisterRouter.scala:87:24] wire out_f_roready_606 = out_roready_1_460 & out_romask_606; // @[RegisterRouter.scala:87:24] wire _out_T_6116 = out_f_roready_606; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_606 = out_wivalid_1_460 & out_wimask_606; // @[RegisterRouter.scala:87:24] wire out_f_woready_606 = out_woready_1_460 & out_womask_606; // @[RegisterRouter.scala:87:24] wire _out_T_6117 = ~out_rimask_606; // @[RegisterRouter.scala:87:24] wire _out_T_6118 = ~out_wimask_606; // @[RegisterRouter.scala:87:24] wire _out_T_6119 = ~out_romask_606; // @[RegisterRouter.scala:87:24] wire _out_T_6120 = ~out_womask_606; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_512 = {hi_362, flags_0_go, _out_prepend_T_512}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6121 = out_prepend_512; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6122 = _out_T_6121; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_513 = _out_T_6122; // @[RegisterRouter.scala:87:24] wire out_rimask_607 = \|_out_rimask_T_607; // @[RegisterRouter.scala:87:24] wire out_wimask_607 = &_out_wimask_T_607; // @[RegisterRouter.scala:87:24] wire out_romask_607 = \|_out_romask_T_607; // @[RegisterRouter.scala:87:24] wire out_womask_607 = &_out_womask_T_607; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_607 = out_rivalid_1_461 & out_rimask_607; // @[RegisterRouter.scala:87:24] wire _out_T_6124 = out_f_rivalid_607; // @[RegisterRouter.scala:87:24] wire out_f_roready_607 = out_roready_1_461 & out_romask_607; // @[RegisterRouter.scala:87:24] wire _out_T_6125 = out_f_roready_607; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_607 = out_wivalid_1_461 & out_wimask_607; // @[RegisterRouter.scala:87:24] wire out_f_woready_607 = out_woready_1_461 & out_womask_607; // @[RegisterRouter.scala:87:24] wire _out_T_6126 = ~out_rimask_607; // @[RegisterRouter.scala:87:24] wire _out_T_6127 = ~out_wimask_607; // @[RegisterRouter.scala:87:24] wire _out_T_6128 = ~out_romask_607; // @[RegisterRouter.scala:87:24] wire _out_T_6129 = ~out_womask_607; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_513 = {hi_363, flags_0_go, _out_prepend_T_513}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6130 = out_prepend_513; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6131 = _out_T_6130; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_514 = _out_T_6131; // @[RegisterRouter.scala:87:24] wire out_rimask_608 = \|_out_rimask_T_608; // @[RegisterRouter.scala:87:24] wire out_wimask_608 = &_out_wimask_T_608; // @[RegisterRouter.scala:87:24] wire out_romask_608 = \|_out_romask_T_608; // @[RegisterRouter.scala:87:24] wire out_womask_608 = &_out_womask_T_608; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_608 = out_rivalid_1_462 & out_rimask_608; // @[RegisterRouter.scala:87:24] wire _out_T_6133 = out_f_rivalid_608; // @[RegisterRouter.scala:87:24] wire out_f_roready_608 = out_roready_1_462 & out_romask_608; // @[RegisterRouter.scala:87:24] wire _out_T_6134 = out_f_roready_608; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_608 = out_wivalid_1_462 & out_wimask_608; // @[RegisterRouter.scala:87:24] wire out_f_woready_608 = out_woready_1_462 & out_womask_608; // @[RegisterRouter.scala:87:24] wire _out_T_6135 = ~out_rimask_608; // @[RegisterRouter.scala:87:24] wire _out_T_6136 = ~out_wimask_608; // @[RegisterRouter.scala:87:24] wire _out_T_6137 = ~out_romask_608; // @[RegisterRouter.scala:87:24] wire _out_T_6138 = ~out_womask_608; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_514 = {hi_364, flags_0_go, _out_prepend_T_514}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6139 = out_prepend_514; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6140 = _out_T_6139; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_515 = _out_T_6140; // @[RegisterRouter.scala:87:24] wire out_rimask_609 = \|_out_rimask_T_609; // @[RegisterRouter.scala:87:24] wire out_wimask_609 = &_out_wimask_T_609; // @[RegisterRouter.scala:87:24] wire out_romask_609 = \|_out_romask_T_609; // @[RegisterRouter.scala:87:24] wire out_womask_609 = &_out_womask_T_609; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_609 = out_rivalid_1_463 & out_rimask_609; // @[RegisterRouter.scala:87:24] wire _out_T_6142 = out_f_rivalid_609; // @[RegisterRouter.scala:87:24] wire out_f_roready_609 = out_roready_1_463 & out_romask_609; // @[RegisterRouter.scala:87:24] wire _out_T_6143 = out_f_roready_609; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_609 = out_wivalid_1_463 & out_wimask_609; // @[RegisterRouter.scala:87:24] wire out_f_woready_609 = out_woready_1_463 & out_womask_609; // @[RegisterRouter.scala:87:24] wire _out_T_6144 = ~out_rimask_609; // @[RegisterRouter.scala:87:24] wire _out_T_6145 = ~out_wimask_609; // @[RegisterRouter.scala:87:24] wire _out_T_6146 = ~out_romask_609; // @[RegisterRouter.scala:87:24] wire _out_T_6147 = ~out_womask_609; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_515 = {hi_365, flags_0_go, _out_prepend_T_515}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6148 = out_prepend_515; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6149 = _out_T_6148; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_516 = _out_T_6149; // @[RegisterRouter.scala:87:24] wire out_rimask_610 = \|_out_rimask_T_610; // @[RegisterRouter.scala:87:24] wire out_wimask_610 = &_out_wimask_T_610; // @[RegisterRouter.scala:87:24] wire out_romask_610 = \|_out_romask_T_610; // @[RegisterRouter.scala:87:24] wire out_womask_610 = &_out_womask_T_610; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_610 = out_rivalid_1_464 & out_rimask_610; // @[RegisterRouter.scala:87:24] wire _out_T_6151 = out_f_rivalid_610; // @[RegisterRouter.scala:87:24] wire out_f_roready_610 = out_roready_1_464 & out_romask_610; // @[RegisterRouter.scala:87:24] wire _out_T_6152 = out_f_roready_610; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_610 = out_wivalid_1_464 & out_wimask_610; // @[RegisterRouter.scala:87:24] wire out_f_woready_610 = out_woready_1_464 & out_womask_610; // @[RegisterRouter.scala:87:24] wire _out_T_6153 = ~out_rimask_610; // @[RegisterRouter.scala:87:24] wire _out_T_6154 = ~out_wimask_610; // @[RegisterRouter.scala:87:24] wire _out_T_6155 = ~out_romask_610; // @[RegisterRouter.scala:87:24] wire _out_T_6156 = ~out_womask_610; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_516 = {hi_366, flags_0_go, _out_prepend_T_516}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6157 = out_prepend_516; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6158 = _out_T_6157; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_517 = _out_T_6158; // @[RegisterRouter.scala:87:24] wire out_rimask_611 = \|_out_rimask_T_611; // @[RegisterRouter.scala:87:24] wire out_wimask_611 = &_out_wimask_T_611; // @[RegisterRouter.scala:87:24] wire out_romask_611 = \|_out_romask_T_611; // @[RegisterRouter.scala:87:24] wire out_womask_611 = &_out_womask_T_611; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_611 = out_rivalid_1_465 & out_rimask_611; // @[RegisterRouter.scala:87:24] wire _out_T_6160 = out_f_rivalid_611; // @[RegisterRouter.scala:87:24] wire out_f_roready_611 = out_roready_1_465 & out_romask_611; // @[RegisterRouter.scala:87:24] wire _out_T_6161 = out_f_roready_611; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_611 = out_wivalid_1_465 & out_wimask_611; // @[RegisterRouter.scala:87:24] wire out_f_woready_611 = out_woready_1_465 & out_womask_611; // @[RegisterRouter.scala:87:24] wire _out_T_6162 = ~out_rimask_611; // @[RegisterRouter.scala:87:24] wire _out_T_6163 = ~out_wimask_611; // @[RegisterRouter.scala:87:24] wire _out_T_6164 = ~out_romask_611; // @[RegisterRouter.scala:87:24] wire _out_T_6165 = ~out_womask_611; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_517 = {hi_367, flags_0_go, _out_prepend_T_517}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6166 = out_prepend_517; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6167 = _out_T_6166; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_518 = _out_T_6167; // @[RegisterRouter.scala:87:24] wire out_rimask_612 = \|_out_rimask_T_612; // @[RegisterRouter.scala:87:24] wire out_wimask_612 = &_out_wimask_T_612; // @[RegisterRouter.scala:87:24] wire out_romask_612 = \|_out_romask_T_612; // @[RegisterRouter.scala:87:24] wire out_womask_612 = &_out_womask_T_612; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_612 = out_rivalid_1_466 & out_rimask_612; // @[RegisterRouter.scala:87:24] wire _out_T_6169 = out_f_rivalid_612; // @[RegisterRouter.scala:87:24] wire out_f_roready_612 = out_roready_1_466 & out_romask_612; // @[RegisterRouter.scala:87:24] wire _out_T_6170 = out_f_roready_612; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_612 = out_wivalid_1_466 & out_wimask_612; // @[RegisterRouter.scala:87:24] wire out_f_woready_612 = out_woready_1_466 & out_womask_612; // @[RegisterRouter.scala:87:24] wire _out_T_6171 = ~out_rimask_612; // @[RegisterRouter.scala:87:24] wire _out_T_6172 = ~out_wimask_612; // @[RegisterRouter.scala:87:24] wire _out_T_6173 = ~out_romask_612; // @[RegisterRouter.scala:87:24] wire _out_T_6174 = ~out_womask_612; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_518 = {hi_368, flags_0_go, _out_prepend_T_518}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6175 = out_prepend_518; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6176 = _out_T_6175; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_173 = _out_T_6176; // @[MuxLiteral.scala:49:48] wire out_rimask_613 = \|_out_rimask_T_613; // @[RegisterRouter.scala:87:24] wire out_wimask_613 = &_out_wimask_T_613; // @[RegisterRouter.scala:87:24] wire out_romask_613 = \|_out_romask_T_613; // @[RegisterRouter.scala:87:24] wire out_womask_613 = &_out_womask_T_613; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_613 = out_rivalid_1_467 & out_rimask_613; // @[RegisterRouter.scala:87:24] wire _out_T_6178 = out_f_rivalid_613; // @[RegisterRouter.scala:87:24] wire out_f_roready_613 = out_roready_1_467 & out_romask_613; // @[RegisterRouter.scala:87:24] wire _out_T_6179 = out_f_roready_613; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_613 = out_wivalid_1_467 & out_wimask_613; // @[RegisterRouter.scala:87:24] wire out_f_woready_613 = out_woready_1_467 & out_womask_613; // @[RegisterRouter.scala:87:24] wire _out_T_6180 = ~out_rimask_613; // @[RegisterRouter.scala:87:24] wire _out_T_6181 = ~out_wimask_613; // @[RegisterRouter.scala:87:24] wire _out_T_6182 = ~out_romask_613; // @[RegisterRouter.scala:87:24] wire _out_T_6183 = ~out_womask_613; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6185 = _out_T_6184; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_519 = _out_T_6185; // @[RegisterRouter.scala:87:24] wire out_rimask_614 = \|_out_rimask_T_614; // @[RegisterRouter.scala:87:24] wire out_wimask_614 = &_out_wimask_T_614; // @[RegisterRouter.scala:87:24] wire out_romask_614 = \|_out_romask_T_614; // @[RegisterRouter.scala:87:24] wire out_womask_614 = &_out_womask_T_614; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_614 = out_rivalid_1_468 & out_rimask_614; // @[RegisterRouter.scala:87:24] wire _out_T_6187 = out_f_rivalid_614; // @[RegisterRouter.scala:87:24] wire out_f_roready_614 = out_roready_1_468 & out_romask_614; // @[RegisterRouter.scala:87:24] wire _out_T_6188 = out_f_roready_614; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_614 = out_wivalid_1_468 & out_wimask_614; // @[RegisterRouter.scala:87:24] wire out_f_woready_614 = out_woready_1_468 & out_womask_614; // @[RegisterRouter.scala:87:24] wire _out_T_6189 = ~out_rimask_614; // @[RegisterRouter.scala:87:24] wire _out_T_6190 = ~out_wimask_614; // @[RegisterRouter.scala:87:24] wire _out_T_6191 = ~out_romask_614; // @[RegisterRouter.scala:87:24] wire _out_T_6192 = ~out_womask_614; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_519 = {hi_10, flags_0_go, _out_prepend_T_519}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6193 = out_prepend_519; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6194 = _out_T_6193; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_520 = _out_T_6194; // @[RegisterRouter.scala:87:24] wire out_rimask_615 = \|_out_rimask_T_615; // @[RegisterRouter.scala:87:24] wire out_wimask_615 = &_out_wimask_T_615; // @[RegisterRouter.scala:87:24] wire out_romask_615 = \|_out_romask_T_615; // @[RegisterRouter.scala:87:24] wire out_womask_615 = &_out_womask_T_615; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_615 = out_rivalid_1_469 & out_rimask_615; // @[RegisterRouter.scala:87:24] wire _out_T_6196 = out_f_rivalid_615; // @[RegisterRouter.scala:87:24] wire out_f_roready_615 = out_roready_1_469 & out_romask_615; // @[RegisterRouter.scala:87:24] wire _out_T_6197 = out_f_roready_615; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_615 = out_wivalid_1_469 & out_wimask_615; // @[RegisterRouter.scala:87:24] wire out_f_woready_615 = out_woready_1_469 & out_womask_615; // @[RegisterRouter.scala:87:24] wire _out_T_6198 = ~out_rimask_615; // @[RegisterRouter.scala:87:24] wire _out_T_6199 = ~out_wimask_615; // @[RegisterRouter.scala:87:24] wire _out_T_6200 = ~out_romask_615; // @[RegisterRouter.scala:87:24] wire _out_T_6201 = ~out_womask_615; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_520 = {hi_11, flags_0_go, _out_prepend_T_520}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6202 = out_prepend_520; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6203 = _out_T_6202; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_521 = _out_T_6203; // @[RegisterRouter.scala:87:24] wire out_rimask_616 = \|_out_rimask_T_616; // @[RegisterRouter.scala:87:24] wire out_wimask_616 = &_out_wimask_T_616; // @[RegisterRouter.scala:87:24] wire out_romask_616 = \|_out_romask_T_616; // @[RegisterRouter.scala:87:24] wire out_womask_616 = &_out_womask_T_616; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_616 = out_rivalid_1_470 & out_rimask_616; // @[RegisterRouter.scala:87:24] wire _out_T_6205 = out_f_rivalid_616; // @[RegisterRouter.scala:87:24] wire out_f_roready_616 = out_roready_1_470 & out_romask_616; // @[RegisterRouter.scala:87:24] wire _out_T_6206 = out_f_roready_616; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_616 = out_wivalid_1_470 & out_wimask_616; // @[RegisterRouter.scala:87:24] wire out_f_woready_616 = out_woready_1_470 & out_womask_616; // @[RegisterRouter.scala:87:24] wire _out_T_6207 = ~out_rimask_616; // @[RegisterRouter.scala:87:24] wire _out_T_6208 = ~out_wimask_616; // @[RegisterRouter.scala:87:24] wire _out_T_6209 = ~out_romask_616; // @[RegisterRouter.scala:87:24] wire _out_T_6210 = ~out_womask_616; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_521 = {hi_12, flags_0_go, _out_prepend_T_521}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6211 = out_prepend_521; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6212 = _out_T_6211; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_522 = _out_T_6212; // @[RegisterRouter.scala:87:24] wire out_rimask_617 = \|_out_rimask_T_617; // @[RegisterRouter.scala:87:24] wire out_wimask_617 = &_out_wimask_T_617; // @[RegisterRouter.scala:87:24] wire out_romask_617 = \|_out_romask_T_617; // @[RegisterRouter.scala:87:24] wire out_womask_617 = &_out_womask_T_617; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_617 = out_rivalid_1_471 & out_rimask_617; // @[RegisterRouter.scala:87:24] wire _out_T_6214 = out_f_rivalid_617; // @[RegisterRouter.scala:87:24] wire out_f_roready_617 = out_roready_1_471 & out_romask_617; // @[RegisterRouter.scala:87:24] wire _out_T_6215 = out_f_roready_617; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_617 = out_wivalid_1_471 & out_wimask_617; // @[RegisterRouter.scala:87:24] wire out_f_woready_617 = out_woready_1_471 & out_womask_617; // @[RegisterRouter.scala:87:24] wire _out_T_6216 = ~out_rimask_617; // @[RegisterRouter.scala:87:24] wire _out_T_6217 = ~out_wimask_617; // @[RegisterRouter.scala:87:24] wire _out_T_6218 = ~out_romask_617; // @[RegisterRouter.scala:87:24] wire _out_T_6219 = ~out_womask_617; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_522 = {hi_13, flags_0_go, _out_prepend_T_522}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6220 = out_prepend_522; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6221 = _out_T_6220; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_523 = _out_T_6221; // @[RegisterRouter.scala:87:24] wire out_rimask_618 = \|_out_rimask_T_618; // @[RegisterRouter.scala:87:24] wire out_wimask_618 = &_out_wimask_T_618; // @[RegisterRouter.scala:87:24] wire out_romask_618 = \|_out_romask_T_618; // @[RegisterRouter.scala:87:24] wire out_womask_618 = &_out_womask_T_618; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_618 = out_rivalid_1_472 & out_rimask_618; // @[RegisterRouter.scala:87:24] wire _out_T_6223 = out_f_rivalid_618; // @[RegisterRouter.scala:87:24] wire out_f_roready_618 = out_roready_1_472 & out_romask_618; // @[RegisterRouter.scala:87:24] wire _out_T_6224 = out_f_roready_618; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_618 = out_wivalid_1_472 & out_wimask_618; // @[RegisterRouter.scala:87:24] wire out_f_woready_618 = out_woready_1_472 & out_womask_618; // @[RegisterRouter.scala:87:24] wire _out_T_6225 = ~out_rimask_618; // @[RegisterRouter.scala:87:24] wire _out_T_6226 = ~out_wimask_618; // @[RegisterRouter.scala:87:24] wire _out_T_6227 = ~out_romask_618; // @[RegisterRouter.scala:87:24] wire _out_T_6228 = ~out_womask_618; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_523 = {hi_14, flags_0_go, _out_prepend_T_523}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6229 = out_prepend_523; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6230 = _out_T_6229; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_524 = _out_T_6230; // @[RegisterRouter.scala:87:24] wire out_rimask_619 = \|_out_rimask_T_619; // @[RegisterRouter.scala:87:24] wire out_wimask_619 = &_out_wimask_T_619; // @[RegisterRouter.scala:87:24] wire out_romask_619 = \|_out_romask_T_619; // @[RegisterRouter.scala:87:24] wire out_womask_619 = &_out_womask_T_619; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_619 = out_rivalid_1_473 & out_rimask_619; // @[RegisterRouter.scala:87:24] wire _out_T_6232 = out_f_rivalid_619; // @[RegisterRouter.scala:87:24] wire out_f_roready_619 = out_roready_1_473 & out_romask_619; // @[RegisterRouter.scala:87:24] wire _out_T_6233 = out_f_roready_619; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_619 = out_wivalid_1_473 & out_wimask_619; // @[RegisterRouter.scala:87:24] wire out_f_woready_619 = out_woready_1_473 & out_womask_619; // @[RegisterRouter.scala:87:24] wire _out_T_6234 = ~out_rimask_619; // @[RegisterRouter.scala:87:24] wire _out_T_6235 = ~out_wimask_619; // @[RegisterRouter.scala:87:24] wire _out_T_6236 = ~out_romask_619; // @[RegisterRouter.scala:87:24] wire _out_T_6237 = ~out_womask_619; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_524 = {hi_15, flags_0_go, _out_prepend_T_524}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6238 = out_prepend_524; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6239 = _out_T_6238; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_525 = _out_T_6239; // @[RegisterRouter.scala:87:24] wire out_rimask_620 = \|_out_rimask_T_620; // @[RegisterRouter.scala:87:24] wire out_wimask_620 = &_out_wimask_T_620; // @[RegisterRouter.scala:87:24] wire out_romask_620 = \|_out_romask_T_620; // @[RegisterRouter.scala:87:24] wire out_womask_620 = &_out_womask_T_620; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_620 = out_rivalid_1_474 & out_rimask_620; // @[RegisterRouter.scala:87:24] wire _out_T_6241 = out_f_rivalid_620; // @[RegisterRouter.scala:87:24] wire out_f_roready_620 = out_roready_1_474 & out_romask_620; // @[RegisterRouter.scala:87:24] wire _out_T_6242 = out_f_roready_620; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_620 = out_wivalid_1_474 & out_wimask_620; // @[RegisterRouter.scala:87:24] wire out_f_woready_620 = out_woready_1_474 & out_womask_620; // @[RegisterRouter.scala:87:24] wire _out_T_6243 = ~out_rimask_620; // @[RegisterRouter.scala:87:24] wire _out_T_6244 = ~out_wimask_620; // @[RegisterRouter.scala:87:24] wire _out_T_6245 = ~out_romask_620; // @[RegisterRouter.scala:87:24] wire _out_T_6246 = ~out_womask_620; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_525 = {hi_16, flags_0_go, _out_prepend_T_525}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6247 = out_prepend_525; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6248 = _out_T_6247; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_129 = _out_T_6248; // @[MuxLiteral.scala:49:48] wire out_rimask_621 = \|_out_rimask_T_621; // @[RegisterRouter.scala:87:24] wire out_wimask_621 = &_out_wimask_T_621; // @[RegisterRouter.scala:87:24] wire out_romask_621 = \|_out_romask_T_621; // @[RegisterRouter.scala:87:24] wire out_womask_621 = &_out_womask_T_621; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_621 = out_rivalid_1_475 & out_rimask_621; // @[RegisterRouter.scala:87:24] wire _out_T_6250 = out_f_rivalid_621; // @[RegisterRouter.scala:87:24] wire out_f_roready_621 = out_roready_1_475 & out_romask_621; // @[RegisterRouter.scala:87:24] wire _out_T_6251 = out_f_roready_621; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_621 = out_wivalid_1_475 & out_wimask_621; // @[RegisterRouter.scala:87:24] wire out_f_woready_621 = out_woready_1_475 & out_womask_621; // @[RegisterRouter.scala:87:24] wire _out_T_6252 = ~out_rimask_621; // @[RegisterRouter.scala:87:24] wire _out_T_6253 = ~out_wimask_621; // @[RegisterRouter.scala:87:24] wire _out_T_6254 = ~out_romask_621; // @[RegisterRouter.scala:87:24] wire _out_T_6255 = ~out_womask_621; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6257 = _out_T_6256; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_526 = _out_T_6257; // @[RegisterRouter.scala:87:24] wire out_rimask_622 = \|_out_rimask_T_622; // @[RegisterRouter.scala:87:24] wire out_wimask_622 = &_out_wimask_T_622; // @[RegisterRouter.scala:87:24] wire out_romask_622 = \|_out_romask_T_622; // @[RegisterRouter.scala:87:24] wire out_womask_622 = &_out_womask_T_622; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_622 = out_rivalid_1_476 & out_rimask_622; // @[RegisterRouter.scala:87:24] wire _out_T_6259 = out_f_rivalid_622; // @[RegisterRouter.scala:87:24] wire out_f_roready_622 = out_roready_1_476 & out_romask_622; // @[RegisterRouter.scala:87:24] wire _out_T_6260 = out_f_roready_622; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_622 = out_wivalid_1_476 & out_wimask_622; // @[RegisterRouter.scala:87:24] wire out_f_woready_622 = out_woready_1_476 & out_womask_622; // @[RegisterRouter.scala:87:24] wire _out_T_6261 = ~out_rimask_622; // @[RegisterRouter.scala:87:24] wire _out_T_6262 = ~out_wimask_622; // @[RegisterRouter.scala:87:24] wire _out_T_6263 = ~out_romask_622; // @[RegisterRouter.scala:87:24] wire _out_T_6264 = ~out_womask_622; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_526 = {hi_50, flags_0_go, _out_prepend_T_526}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6265 = out_prepend_526; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6266 = _out_T_6265; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_527 = _out_T_6266; // @[RegisterRouter.scala:87:24] wire out_rimask_623 = \|_out_rimask_T_623; // @[RegisterRouter.scala:87:24] wire out_wimask_623 = &_out_wimask_T_623; // @[RegisterRouter.scala:87:24] wire out_romask_623 = \|_out_romask_T_623; // @[RegisterRouter.scala:87:24] wire out_womask_623 = &_out_womask_T_623; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_623 = out_rivalid_1_477 & out_rimask_623; // @[RegisterRouter.scala:87:24] wire _out_T_6268 = out_f_rivalid_623; // @[RegisterRouter.scala:87:24] wire out_f_roready_623 = out_roready_1_477 & out_romask_623; // @[RegisterRouter.scala:87:24] wire _out_T_6269 = out_f_roready_623; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_623 = out_wivalid_1_477 & out_wimask_623; // @[RegisterRouter.scala:87:24] wire out_f_woready_623 = out_woready_1_477 & out_womask_623; // @[RegisterRouter.scala:87:24] wire _out_T_6270 = ~out_rimask_623; // @[RegisterRouter.scala:87:24] wire _out_T_6271 = ~out_wimask_623; // @[RegisterRouter.scala:87:24] wire _out_T_6272 = ~out_romask_623; // @[RegisterRouter.scala:87:24] wire _out_T_6273 = ~out_womask_623; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_527 = {hi_51, flags_0_go, _out_prepend_T_527}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6274 = out_prepend_527; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6275 = _out_T_6274; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_528 = _out_T_6275; // @[RegisterRouter.scala:87:24] wire out_rimask_624 = \|_out_rimask_T_624; // @[RegisterRouter.scala:87:24] wire out_wimask_624 = &_out_wimask_T_624; // @[RegisterRouter.scala:87:24] wire out_romask_624 = \|_out_romask_T_624; // @[RegisterRouter.scala:87:24] wire out_womask_624 = &_out_womask_T_624; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_624 = out_rivalid_1_478 & out_rimask_624; // @[RegisterRouter.scala:87:24] wire _out_T_6277 = out_f_rivalid_624; // @[RegisterRouter.scala:87:24] wire out_f_roready_624 = out_roready_1_478 & out_romask_624; // @[RegisterRouter.scala:87:24] wire _out_T_6278 = out_f_roready_624; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_624 = out_wivalid_1_478 & out_wimask_624; // @[RegisterRouter.scala:87:24] wire out_f_woready_624 = out_woready_1_478 & out_womask_624; // @[RegisterRouter.scala:87:24] wire _out_T_6279 = ~out_rimask_624; // @[RegisterRouter.scala:87:24] wire _out_T_6280 = ~out_wimask_624; // @[RegisterRouter.scala:87:24] wire _out_T_6281 = ~out_romask_624; // @[RegisterRouter.scala:87:24] wire _out_T_6282 = ~out_womask_624; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_528 = {hi_52, flags_0_go, _out_prepend_T_528}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6283 = out_prepend_528; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6284 = _out_T_6283; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_529 = _out_T_6284; // @[RegisterRouter.scala:87:24] wire out_rimask_625 = \|_out_rimask_T_625; // @[RegisterRouter.scala:87:24] wire out_wimask_625 = &_out_wimask_T_625; // @[RegisterRouter.scala:87:24] wire out_romask_625 = \|_out_romask_T_625; // @[RegisterRouter.scala:87:24] wire out_womask_625 = &_out_womask_T_625; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_625 = out_rivalid_1_479 & out_rimask_625; // @[RegisterRouter.scala:87:24] wire _out_T_6286 = out_f_rivalid_625; // @[RegisterRouter.scala:87:24] wire out_f_roready_625 = out_roready_1_479 & out_romask_625; // @[RegisterRouter.scala:87:24] wire _out_T_6287 = out_f_roready_625; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_625 = out_wivalid_1_479 & out_wimask_625; // @[RegisterRouter.scala:87:24] wire out_f_woready_625 = out_woready_1_479 & out_womask_625; // @[RegisterRouter.scala:87:24] wire _out_T_6288 = ~out_rimask_625; // @[RegisterRouter.scala:87:24] wire _out_T_6289 = ~out_wimask_625; // @[RegisterRouter.scala:87:24] wire _out_T_6290 = ~out_romask_625; // @[RegisterRouter.scala:87:24] wire _out_T_6291 = ~out_womask_625; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_529 = {hi_53, flags_0_go, _out_prepend_T_529}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6292 = out_prepend_529; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6293 = _out_T_6292; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_530 = _out_T_6293; // @[RegisterRouter.scala:87:24] wire out_rimask_626 = \|_out_rimask_T_626; // @[RegisterRouter.scala:87:24] wire out_wimask_626 = &_out_wimask_T_626; // @[RegisterRouter.scala:87:24] wire out_romask_626 = \|_out_romask_T_626; // @[RegisterRouter.scala:87:24] wire out_womask_626 = &_out_womask_T_626; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_626 = out_rivalid_1_480 & out_rimask_626; // @[RegisterRouter.scala:87:24] wire _out_T_6295 = out_f_rivalid_626; // @[RegisterRouter.scala:87:24] wire out_f_roready_626 = out_roready_1_480 & out_romask_626; // @[RegisterRouter.scala:87:24] wire _out_T_6296 = out_f_roready_626; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_626 = out_wivalid_1_480 & out_wimask_626; // @[RegisterRouter.scala:87:24] wire out_f_woready_626 = out_woready_1_480 & out_womask_626; // @[RegisterRouter.scala:87:24] wire _out_T_6297 = ~out_rimask_626; // @[RegisterRouter.scala:87:24] wire _out_T_6298 = ~out_wimask_626; // @[RegisterRouter.scala:87:24] wire _out_T_6299 = ~out_romask_626; // @[RegisterRouter.scala:87:24] wire _out_T_6300 = ~out_womask_626; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_530 = {hi_54, flags_0_go, _out_prepend_T_530}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6301 = out_prepend_530; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6302 = _out_T_6301; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_531 = _out_T_6302; // @[RegisterRouter.scala:87:24] wire out_rimask_627 = \|_out_rimask_T_627; // @[RegisterRouter.scala:87:24] wire out_wimask_627 = &_out_wimask_T_627; // @[RegisterRouter.scala:87:24] wire out_romask_627 = \|_out_romask_T_627; // @[RegisterRouter.scala:87:24] wire out_womask_627 = &_out_womask_T_627; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_627 = out_rivalid_1_481 & out_rimask_627; // @[RegisterRouter.scala:87:24] wire _out_T_6304 = out_f_rivalid_627; // @[RegisterRouter.scala:87:24] wire out_f_roready_627 = out_roready_1_481 & out_romask_627; // @[RegisterRouter.scala:87:24] wire _out_T_6305 = out_f_roready_627; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_627 = out_wivalid_1_481 & out_wimask_627; // @[RegisterRouter.scala:87:24] wire out_f_woready_627 = out_woready_1_481 & out_womask_627; // @[RegisterRouter.scala:87:24] wire _out_T_6306 = ~out_rimask_627; // @[RegisterRouter.scala:87:24] wire _out_T_6307 = ~out_wimask_627; // @[RegisterRouter.scala:87:24] wire _out_T_6308 = ~out_romask_627; // @[RegisterRouter.scala:87:24] wire _out_T_6309 = ~out_womask_627; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_531 = {hi_55, flags_0_go, _out_prepend_T_531}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6310 = out_prepend_531; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6311 = _out_T_6310; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_532 = _out_T_6311; // @[RegisterRouter.scala:87:24] wire out_rimask_628 = \|_out_rimask_T_628; // @[RegisterRouter.scala:87:24] wire out_wimask_628 = &_out_wimask_T_628; // @[RegisterRouter.scala:87:24] wire out_romask_628 = \|_out_romask_T_628; // @[RegisterRouter.scala:87:24] wire out_womask_628 = &_out_womask_T_628; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_628 = out_rivalid_1_482 & out_rimask_628; // @[RegisterRouter.scala:87:24] wire _out_T_6313 = out_f_rivalid_628; // @[RegisterRouter.scala:87:24] wire out_f_roready_628 = out_roready_1_482 & out_romask_628; // @[RegisterRouter.scala:87:24] wire _out_T_6314 = out_f_roready_628; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_628 = out_wivalid_1_482 & out_wimask_628; // @[RegisterRouter.scala:87:24] wire out_f_woready_628 = out_woready_1_482 & out_womask_628; // @[RegisterRouter.scala:87:24] wire _out_T_6315 = ~out_rimask_628; // @[RegisterRouter.scala:87:24] wire _out_T_6316 = ~out_wimask_628; // @[RegisterRouter.scala:87:24] wire _out_T_6317 = ~out_romask_628; // @[RegisterRouter.scala:87:24] wire _out_T_6318 = ~out_womask_628; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_532 = {hi_56, flags_0_go, _out_prepend_T_532}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6319 = out_prepend_532; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6320 = _out_T_6319; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_134 = _out_T_6320; // @[MuxLiteral.scala:49:48] wire out_rimask_629 = \|_out_rimask_T_629; // @[RegisterRouter.scala:87:24] wire out_wimask_629 = &_out_wimask_T_629; // @[RegisterRouter.scala:87:24] wire out_romask_629 = \|_out_romask_T_629; // @[RegisterRouter.scala:87:24] wire out_womask_629 = &_out_womask_T_629; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_629 = out_rivalid_1_483 & out_rimask_629; // @[RegisterRouter.scala:87:24] wire _out_T_6322 = out_f_rivalid_629; // @[RegisterRouter.scala:87:24] wire out_f_roready_629 = out_roready_1_483 & out_romask_629; // @[RegisterRouter.scala:87:24] wire _out_T_6323 = out_f_roready_629; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_629 = out_wivalid_1_483 & out_wimask_629; // @[RegisterRouter.scala:87:24] wire out_f_woready_629 = out_woready_1_483 & out_womask_629; // @[RegisterRouter.scala:87:24] wire _out_T_6324 = ~out_rimask_629; // @[RegisterRouter.scala:87:24] wire _out_T_6325 = ~out_wimask_629; // @[RegisterRouter.scala:87:24] wire _out_T_6326 = ~out_romask_629; // @[RegisterRouter.scala:87:24] wire _out_T_6327 = ~out_womask_629; // @[RegisterRouter.scala:87:24] wire out_rimask_630 = \|_out_rimask_T_630; // @[RegisterRouter.scala:87:24] wire out_wimask_630 = &_out_wimask_T_630; // @[RegisterRouter.scala:87:24] wire out_romask_630 = \|_out_romask_T_630; // @[RegisterRouter.scala:87:24] wire out_womask_630 = &_out_womask_T_630; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_630 = out_rivalid_1_484 & out_rimask_630; // @[RegisterRouter.scala:87:24] wire _out_T_6331 = out_f_rivalid_630; // @[RegisterRouter.scala:87:24] wire out_f_roready_630 = out_roready_1_484 & out_romask_630; // @[RegisterRouter.scala:87:24] wire _out_T_6332 = out_f_roready_630; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_630 = out_wivalid_1_484 & out_wimask_630; // @[RegisterRouter.scala:87:24] wire out_f_woready_630 = out_woready_1_484 & out_womask_630; // @[RegisterRouter.scala:87:24] wire _out_T_6333 = ~out_rimask_630; // @[RegisterRouter.scala:87:24] wire _out_T_6334 = ~out_wimask_630; // @[RegisterRouter.scala:87:24] wire _out_T_6335 = ~out_romask_630; // @[RegisterRouter.scala:87:24] wire _out_T_6336 = ~out_womask_630; // @[RegisterRouter.scala:87:24] wire out_rimask_631 = \|_out_rimask_T_631; // @[RegisterRouter.scala:87:24] wire out_wimask_631 = &_out_wimask_T_631; // @[RegisterRouter.scala:87:24] wire out_romask_631 = \|_out_romask_T_631; // @[RegisterRouter.scala:87:24] wire out_womask_631 = &_out_womask_T_631; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_631 = out_rivalid_1_485 & out_rimask_631; // @[RegisterRouter.scala:87:24] wire _out_T_6340 = out_f_rivalid_631; // @[RegisterRouter.scala:87:24] wire out_f_roready_631 = out_roready_1_485 & out_romask_631; // @[RegisterRouter.scala:87:24] wire _out_T_6341 = out_f_roready_631; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_631 = out_wivalid_1_485 & out_wimask_631; // @[RegisterRouter.scala:87:24] wire out_f_woready_631 = out_woready_1_485 & out_womask_631; // @[RegisterRouter.scala:87:24] wire _out_T_6342 = ~out_rimask_631; // @[RegisterRouter.scala:87:24] wire _out_T_6343 = ~out_wimask_631; // @[RegisterRouter.scala:87:24] wire _out_T_6344 = ~out_romask_631; // @[RegisterRouter.scala:87:24] wire _out_T_6345 = ~out_womask_631; // @[RegisterRouter.scala:87:24] wire out_rimask_632 = \|_out_rimask_T_632; // @[RegisterRouter.scala:87:24] wire out_wimask_632 = &_out_wimask_T_632; // @[RegisterRouter.scala:87:24] wire out_romask_632 = \|_out_romask_T_632; // @[RegisterRouter.scala:87:24] wire out_womask_632 = &_out_womask_T_632; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_632 = out_rivalid_1_486 & out_rimask_632; // @[RegisterRouter.scala:87:24] wire _out_T_6349 = out_f_rivalid_632; // @[RegisterRouter.scala:87:24] wire out_f_roready_632 = out_roready_1_486 & out_romask_632; // @[RegisterRouter.scala:87:24] wire _out_T_6350 = out_f_roready_632; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_632 = out_wivalid_1_486 & out_wimask_632; // @[RegisterRouter.scala:87:24] wire out_f_woready_632 = out_woready_1_486 & out_womask_632; // @[RegisterRouter.scala:87:24] wire _out_T_6351 = ~out_rimask_632; // @[RegisterRouter.scala:87:24] wire _out_T_6352 = ~out_wimask_632; // @[RegisterRouter.scala:87:24] wire _out_T_6353 = ~out_romask_632; // @[RegisterRouter.scala:87:24] wire _out_T_6354 = ~out_womask_632; // @[RegisterRouter.scala:87:24] wire out_rimask_633 = \|_out_rimask_T_633; // @[RegisterRouter.scala:87:24] wire out_wimask_633 = &_out_wimask_T_633; // @[RegisterRouter.scala:87:24] wire out_romask_633 = \|_out_romask_T_633; // @[RegisterRouter.scala:87:24] wire out_womask_633 = &_out_womask_T_633; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_633 = out_rivalid_1_487 & out_rimask_633; // @[RegisterRouter.scala:87:24] wire _out_T_6358 = out_f_rivalid_633; // @[RegisterRouter.scala:87:24] wire out_f_roready_633 = out_roready_1_487 & out_romask_633; // @[RegisterRouter.scala:87:24] wire _out_T_6359 = out_f_roready_633; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_633 = out_wivalid_1_487 & out_wimask_633; // @[RegisterRouter.scala:87:24] wire out_f_woready_633 = out_woready_1_487 & out_womask_633; // @[RegisterRouter.scala:87:24] wire _out_T_6360 = ~out_rimask_633; // @[RegisterRouter.scala:87:24] wire _out_T_6361 = ~out_wimask_633; // @[RegisterRouter.scala:87:24] wire _out_T_6362 = ~out_romask_633; // @[RegisterRouter.scala:87:24] wire _out_T_6363 = ~out_womask_633; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6365 = _out_T_6364; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_536 = _out_T_6365; // @[RegisterRouter.scala:87:24] wire out_rimask_634 = \|_out_rimask_T_634; // @[RegisterRouter.scala:87:24] wire out_wimask_634 = &_out_wimask_T_634; // @[RegisterRouter.scala:87:24] wire out_romask_634 = \|_out_romask_T_634; // @[RegisterRouter.scala:87:24] wire out_womask_634 = &_out_womask_T_634; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_634 = out_rivalid_1_488 & out_rimask_634; // @[RegisterRouter.scala:87:24] wire _out_T_6367 = out_f_rivalid_634; // @[RegisterRouter.scala:87:24] wire out_f_roready_634 = out_roready_1_488 & out_romask_634; // @[RegisterRouter.scala:87:24] wire _out_T_6368 = out_f_roready_634; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_634 = out_wivalid_1_488 & out_wimask_634; // @[RegisterRouter.scala:87:24] wire out_f_woready_634 = out_woready_1_488 & out_womask_634; // @[RegisterRouter.scala:87:24] wire _out_T_6369 = ~out_rimask_634; // @[RegisterRouter.scala:87:24] wire _out_T_6370 = ~out_wimask_634; // @[RegisterRouter.scala:87:24] wire _out_T_6371 = ~out_romask_634; // @[RegisterRouter.scala:87:24] wire _out_T_6372 = ~out_womask_634; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_536 = {hi_618, flags_0_go, _out_prepend_T_536}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6373 = out_prepend_536; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6374 = _out_T_6373; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_537 = _out_T_6374; // @[RegisterRouter.scala:87:24] wire out_rimask_635 = \|_out_rimask_T_635; // @[RegisterRouter.scala:87:24] wire out_wimask_635 = &_out_wimask_T_635; // @[RegisterRouter.scala:87:24] wire out_romask_635 = \|_out_romask_T_635; // @[RegisterRouter.scala:87:24] wire out_womask_635 = &_out_womask_T_635; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_635 = out_rivalid_1_489 & out_rimask_635; // @[RegisterRouter.scala:87:24] wire _out_T_6376 = out_f_rivalid_635; // @[RegisterRouter.scala:87:24] wire out_f_roready_635 = out_roready_1_489 & out_romask_635; // @[RegisterRouter.scala:87:24] wire _out_T_6377 = out_f_roready_635; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_635 = out_wivalid_1_489 & out_wimask_635; // @[RegisterRouter.scala:87:24] wire out_f_woready_635 = out_woready_1_489 & out_womask_635; // @[RegisterRouter.scala:87:24] wire _out_T_6378 = ~out_rimask_635; // @[RegisterRouter.scala:87:24] wire _out_T_6379 = ~out_wimask_635; // @[RegisterRouter.scala:87:24] wire _out_T_6380 = ~out_romask_635; // @[RegisterRouter.scala:87:24] wire _out_T_6381 = ~out_womask_635; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_537 = {hi_619, flags_0_go, _out_prepend_T_537}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6382 = out_prepend_537; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6383 = _out_T_6382; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_538 = _out_T_6383; // @[RegisterRouter.scala:87:24] wire out_rimask_636 = \|_out_rimask_T_636; // @[RegisterRouter.scala:87:24] wire out_wimask_636 = &_out_wimask_T_636; // @[RegisterRouter.scala:87:24] wire out_romask_636 = \|_out_romask_T_636; // @[RegisterRouter.scala:87:24] wire out_womask_636 = &_out_womask_T_636; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_636 = out_rivalid_1_490 & out_rimask_636; // @[RegisterRouter.scala:87:24] wire _out_T_6385 = out_f_rivalid_636; // @[RegisterRouter.scala:87:24] wire out_f_roready_636 = out_roready_1_490 & out_romask_636; // @[RegisterRouter.scala:87:24] wire _out_T_6386 = out_f_roready_636; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_636 = out_wivalid_1_490 & out_wimask_636; // @[RegisterRouter.scala:87:24] wire out_f_woready_636 = out_woready_1_490 & out_womask_636; // @[RegisterRouter.scala:87:24] wire _out_T_6387 = ~out_rimask_636; // @[RegisterRouter.scala:87:24] wire _out_T_6388 = ~out_wimask_636; // @[RegisterRouter.scala:87:24] wire _out_T_6389 = ~out_romask_636; // @[RegisterRouter.scala:87:24] wire _out_T_6390 = ~out_womask_636; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_538 = {hi_620, flags_0_go, _out_prepend_T_538}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6391 = out_prepend_538; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6392 = _out_T_6391; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_539 = _out_T_6392; // @[RegisterRouter.scala:87:24] wire out_rimask_637 = \|_out_rimask_T_637; // @[RegisterRouter.scala:87:24] wire out_wimask_637 = &_out_wimask_T_637; // @[RegisterRouter.scala:87:24] wire out_romask_637 = \|_out_romask_T_637; // @[RegisterRouter.scala:87:24] wire out_womask_637 = &_out_womask_T_637; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_637 = out_rivalid_1_491 & out_rimask_637; // @[RegisterRouter.scala:87:24] wire _out_T_6394 = out_f_rivalid_637; // @[RegisterRouter.scala:87:24] wire out_f_roready_637 = out_roready_1_491 & out_romask_637; // @[RegisterRouter.scala:87:24] wire _out_T_6395 = out_f_roready_637; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_637 = out_wivalid_1_491 & out_wimask_637; // @[RegisterRouter.scala:87:24] wire out_f_woready_637 = out_woready_1_491 & out_womask_637; // @[RegisterRouter.scala:87:24] wire _out_T_6396 = ~out_rimask_637; // @[RegisterRouter.scala:87:24] wire _out_T_6397 = ~out_wimask_637; // @[RegisterRouter.scala:87:24] wire _out_T_6398 = ~out_romask_637; // @[RegisterRouter.scala:87:24] wire _out_T_6399 = ~out_womask_637; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_539 = {hi_621, flags_0_go, _out_prepend_T_539}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6400 = out_prepend_539; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6401 = _out_T_6400; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_540 = _out_T_6401; // @[RegisterRouter.scala:87:24] wire out_rimask_638 = \|_out_rimask_T_638; // @[RegisterRouter.scala:87:24] wire out_wimask_638 = &_out_wimask_T_638; // @[RegisterRouter.scala:87:24] wire out_romask_638 = \|_out_romask_T_638; // @[RegisterRouter.scala:87:24] wire out_womask_638 = &_out_womask_T_638; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_638 = out_rivalid_1_492 & out_rimask_638; // @[RegisterRouter.scala:87:24] wire _out_T_6403 = out_f_rivalid_638; // @[RegisterRouter.scala:87:24] wire out_f_roready_638 = out_roready_1_492 & out_romask_638; // @[RegisterRouter.scala:87:24] wire _out_T_6404 = out_f_roready_638; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_638 = out_wivalid_1_492 & out_wimask_638; // @[RegisterRouter.scala:87:24] wire out_f_woready_638 = out_woready_1_492 & out_womask_638; // @[RegisterRouter.scala:87:24] wire _out_T_6405 = ~out_rimask_638; // @[RegisterRouter.scala:87:24] wire _out_T_6406 = ~out_wimask_638; // @[RegisterRouter.scala:87:24] wire _out_T_6407 = ~out_romask_638; // @[RegisterRouter.scala:87:24] wire _out_T_6408 = ~out_womask_638; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_540 = {hi_622, flags_0_go, _out_prepend_T_540}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6409 = out_prepend_540; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6410 = _out_T_6409; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_541 = _out_T_6410; // @[RegisterRouter.scala:87:24] wire out_rimask_639 = \|_out_rimask_T_639; // @[RegisterRouter.scala:87:24] wire out_wimask_639 = &_out_wimask_T_639; // @[RegisterRouter.scala:87:24] wire out_romask_639 = \|_out_romask_T_639; // @[RegisterRouter.scala:87:24] wire out_womask_639 = &_out_womask_T_639; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_639 = out_rivalid_1_493 & out_rimask_639; // @[RegisterRouter.scala:87:24] wire _out_T_6412 = out_f_rivalid_639; // @[RegisterRouter.scala:87:24] wire out_f_roready_639 = out_roready_1_493 & out_romask_639; // @[RegisterRouter.scala:87:24] wire _out_T_6413 = out_f_roready_639; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_639 = out_wivalid_1_493 & out_wimask_639; // @[RegisterRouter.scala:87:24] wire out_f_woready_639 = out_woready_1_493 & out_womask_639; // @[RegisterRouter.scala:87:24] wire _out_T_6414 = ~out_rimask_639; // @[RegisterRouter.scala:87:24] wire _out_T_6415 = ~out_wimask_639; // @[RegisterRouter.scala:87:24] wire _out_T_6416 = ~out_romask_639; // @[RegisterRouter.scala:87:24] wire _out_T_6417 = ~out_womask_639; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_541 = {hi_623, flags_0_go, _out_prepend_T_541}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6418 = out_prepend_541; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6419 = _out_T_6418; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_542 = _out_T_6419; // @[RegisterRouter.scala:87:24] wire out_rimask_640 = \|_out_rimask_T_640; // @[RegisterRouter.scala:87:24] wire out_wimask_640 = &_out_wimask_T_640; // @[RegisterRouter.scala:87:24] wire out_romask_640 = \|_out_romask_T_640; // @[RegisterRouter.scala:87:24] wire out_womask_640 = &_out_womask_T_640; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_640 = out_rivalid_1_494 & out_rimask_640; // @[RegisterRouter.scala:87:24] wire _out_T_6421 = out_f_rivalid_640; // @[RegisterRouter.scala:87:24] wire out_f_roready_640 = out_roready_1_494 & out_romask_640; // @[RegisterRouter.scala:87:24] wire _out_T_6422 = out_f_roready_640; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_640 = out_wivalid_1_494 & out_wimask_640; // @[RegisterRouter.scala:87:24] wire out_f_woready_640 = out_woready_1_494 & out_womask_640; // @[RegisterRouter.scala:87:24] wire _out_T_6423 = ~out_rimask_640; // @[RegisterRouter.scala:87:24] wire _out_T_6424 = ~out_wimask_640; // @[RegisterRouter.scala:87:24] wire _out_T_6425 = ~out_romask_640; // @[RegisterRouter.scala:87:24] wire _out_T_6426 = ~out_womask_640; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_542 = {hi_624, flags_0_go, _out_prepend_T_542}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6427 = out_prepend_542; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6428 = _out_T_6427; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_205 = _out_T_6428; // @[MuxLiteral.scala:49:48] wire out_rimask_641 = \|_out_rimask_T_641; // @[RegisterRouter.scala:87:24] wire out_wimask_641 = &_out_wimask_T_641; // @[RegisterRouter.scala:87:24] wire out_romask_641 = \|_out_romask_T_641; // @[RegisterRouter.scala:87:24] wire out_womask_641 = &_out_womask_T_641; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_641 = out_rivalid_1_495 & out_rimask_641; // @[RegisterRouter.scala:87:24] wire _out_T_6430 = out_f_rivalid_641; // @[RegisterRouter.scala:87:24] wire out_f_roready_641 = out_roready_1_495 & out_romask_641; // @[RegisterRouter.scala:87:24] wire _out_T_6431 = out_f_roready_641; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_641 = out_wivalid_1_495 & out_wimask_641; // @[RegisterRouter.scala:87:24] wire out_f_woready_641 = out_woready_1_495 & out_womask_641; // @[RegisterRouter.scala:87:24] wire _out_T_6432 = ~out_rimask_641; // @[RegisterRouter.scala:87:24] wire _out_T_6433 = ~out_wimask_641; // @[RegisterRouter.scala:87:24] wire _out_T_6434 = ~out_romask_641; // @[RegisterRouter.scala:87:24] wire _out_T_6435 = ~out_womask_641; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6437 = _out_T_6436; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_543 = _out_T_6437; // @[RegisterRouter.scala:87:24] wire out_rimask_642 = \|_out_rimask_T_642; // @[RegisterRouter.scala:87:24] wire out_wimask_642 = &_out_wimask_T_642; // @[RegisterRouter.scala:87:24] wire out_romask_642 = \|_out_romask_T_642; // @[RegisterRouter.scala:87:24] wire out_womask_642 = &_out_womask_T_642; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_642 = out_rivalid_1_496 & out_rimask_642; // @[RegisterRouter.scala:87:24] wire _out_T_6439 = out_f_rivalid_642; // @[RegisterRouter.scala:87:24] wire out_f_roready_642 = out_roready_1_496 & out_romask_642; // @[RegisterRouter.scala:87:24] wire _out_T_6440 = out_f_roready_642; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_642 = out_wivalid_1_496 & out_wimask_642; // @[RegisterRouter.scala:87:24] wire out_f_woready_642 = out_woready_1_496 & out_womask_642; // @[RegisterRouter.scala:87:24] wire _out_T_6441 = ~out_rimask_642; // @[RegisterRouter.scala:87:24] wire _out_T_6442 = ~out_wimask_642; // @[RegisterRouter.scala:87:24] wire _out_T_6443 = ~out_romask_642; // @[RegisterRouter.scala:87:24] wire _out_T_6444 = ~out_womask_642; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_543 = {hi_2, flags_0_go, _out_prepend_T_543}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6445 = out_prepend_543; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6446 = _out_T_6445; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_544 = _out_T_6446; // @[RegisterRouter.scala:87:24] wire out_rimask_643 = \|_out_rimask_T_643; // @[RegisterRouter.scala:87:24] wire out_wimask_643 = &_out_wimask_T_643; // @[RegisterRouter.scala:87:24] wire out_romask_643 = \|_out_romask_T_643; // @[RegisterRouter.scala:87:24] wire out_womask_643 = &_out_womask_T_643; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_643 = out_rivalid_1_497 & out_rimask_643; // @[RegisterRouter.scala:87:24] wire _out_T_6448 = out_f_rivalid_643; // @[RegisterRouter.scala:87:24] wire out_f_roready_643 = out_roready_1_497 & out_romask_643; // @[RegisterRouter.scala:87:24] wire _out_T_6449 = out_f_roready_643; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_643 = out_wivalid_1_497 & out_wimask_643; // @[RegisterRouter.scala:87:24] wire out_f_woready_643 = out_woready_1_497 & out_womask_643; // @[RegisterRouter.scala:87:24] wire _out_T_6450 = ~out_rimask_643; // @[RegisterRouter.scala:87:24] wire _out_T_6451 = ~out_wimask_643; // @[RegisterRouter.scala:87:24] wire _out_T_6452 = ~out_romask_643; // @[RegisterRouter.scala:87:24] wire _out_T_6453 = ~out_womask_643; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_544 = {hi_3, flags_0_go, _out_prepend_T_544}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6454 = out_prepend_544; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6455 = _out_T_6454; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_545 = _out_T_6455; // @[RegisterRouter.scala:87:24] wire out_rimask_644 = \|_out_rimask_T_644; // @[RegisterRouter.scala:87:24] wire out_wimask_644 = &_out_wimask_T_644; // @[RegisterRouter.scala:87:24] wire out_romask_644 = \|_out_romask_T_644; // @[RegisterRouter.scala:87:24] wire out_womask_644 = &_out_womask_T_644; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_644 = out_rivalid_1_498 & out_rimask_644; // @[RegisterRouter.scala:87:24] wire _out_T_6457 = out_f_rivalid_644; // @[RegisterRouter.scala:87:24] wire out_f_roready_644 = out_roready_1_498 & out_romask_644; // @[RegisterRouter.scala:87:24] wire _out_T_6458 = out_f_roready_644; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_644 = out_wivalid_1_498 & out_wimask_644; // @[RegisterRouter.scala:87:24] wire out_f_woready_644 = out_woready_1_498 & out_womask_644; // @[RegisterRouter.scala:87:24] wire _out_T_6459 = ~out_rimask_644; // @[RegisterRouter.scala:87:24] wire _out_T_6460 = ~out_wimask_644; // @[RegisterRouter.scala:87:24] wire _out_T_6461 = ~out_romask_644; // @[RegisterRouter.scala:87:24] wire _out_T_6462 = ~out_womask_644; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_545 = {hi_4, flags_0_go, _out_prepend_T_545}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6463 = out_prepend_545; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6464 = _out_T_6463; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_546 = _out_T_6464; // @[RegisterRouter.scala:87:24] wire out_rimask_645 = \|_out_rimask_T_645; // @[RegisterRouter.scala:87:24] wire out_wimask_645 = &_out_wimask_T_645; // @[RegisterRouter.scala:87:24] wire out_romask_645 = \|_out_romask_T_645; // @[RegisterRouter.scala:87:24] wire out_womask_645 = &_out_womask_T_645; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_645 = out_rivalid_1_499 & out_rimask_645; // @[RegisterRouter.scala:87:24] wire _out_T_6466 = out_f_rivalid_645; // @[RegisterRouter.scala:87:24] wire out_f_roready_645 = out_roready_1_499 & out_romask_645; // @[RegisterRouter.scala:87:24] wire _out_T_6467 = out_f_roready_645; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_645 = out_wivalid_1_499 & out_wimask_645; // @[RegisterRouter.scala:87:24] wire out_f_woready_645 = out_woready_1_499 & out_womask_645; // @[RegisterRouter.scala:87:24] wire _out_T_6468 = ~out_rimask_645; // @[RegisterRouter.scala:87:24] wire _out_T_6469 = ~out_wimask_645; // @[RegisterRouter.scala:87:24] wire _out_T_6470 = ~out_romask_645; // @[RegisterRouter.scala:87:24] wire _out_T_6471 = ~out_womask_645; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_546 = {hi_5, flags_0_go, _out_prepend_T_546}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6472 = out_prepend_546; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6473 = _out_T_6472; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_547 = _out_T_6473; // @[RegisterRouter.scala:87:24] wire out_rimask_646 = \|_out_rimask_T_646; // @[RegisterRouter.scala:87:24] wire out_wimask_646 = &_out_wimask_T_646; // @[RegisterRouter.scala:87:24] wire out_romask_646 = \|_out_romask_T_646; // @[RegisterRouter.scala:87:24] wire out_womask_646 = &_out_womask_T_646; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_646 = out_rivalid_1_500 & out_rimask_646; // @[RegisterRouter.scala:87:24] wire _out_T_6475 = out_f_rivalid_646; // @[RegisterRouter.scala:87:24] wire out_f_roready_646 = out_roready_1_500 & out_romask_646; // @[RegisterRouter.scala:87:24] wire _out_T_6476 = out_f_roready_646; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_646 = out_wivalid_1_500 & out_wimask_646; // @[RegisterRouter.scala:87:24] wire out_f_woready_646 = out_woready_1_500 & out_womask_646; // @[RegisterRouter.scala:87:24] wire _out_T_6477 = ~out_rimask_646; // @[RegisterRouter.scala:87:24] wire _out_T_6478 = ~out_wimask_646; // @[RegisterRouter.scala:87:24] wire _out_T_6479 = ~out_romask_646; // @[RegisterRouter.scala:87:24] wire _out_T_6480 = ~out_womask_646; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_547 = {hi_6, flags_0_go, _out_prepend_T_547}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6481 = out_prepend_547; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6482 = _out_T_6481; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_548 = _out_T_6482; // @[RegisterRouter.scala:87:24] wire out_rimask_647 = \|_out_rimask_T_647; // @[RegisterRouter.scala:87:24] wire out_wimask_647 = &_out_wimask_T_647; // @[RegisterRouter.scala:87:24] wire out_romask_647 = \|_out_romask_T_647; // @[RegisterRouter.scala:87:24] wire out_womask_647 = &_out_womask_T_647; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_647 = out_rivalid_1_501 & out_rimask_647; // @[RegisterRouter.scala:87:24] wire _out_T_6484 = out_f_rivalid_647; // @[RegisterRouter.scala:87:24] wire out_f_roready_647 = out_roready_1_501 & out_romask_647; // @[RegisterRouter.scala:87:24] wire _out_T_6485 = out_f_roready_647; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_647 = out_wivalid_1_501 & out_wimask_647; // @[RegisterRouter.scala:87:24] wire out_f_woready_647 = out_woready_1_501 & out_womask_647; // @[RegisterRouter.scala:87:24] wire _out_T_6486 = ~out_rimask_647; // @[RegisterRouter.scala:87:24] wire _out_T_6487 = ~out_wimask_647; // @[RegisterRouter.scala:87:24] wire _out_T_6488 = ~out_romask_647; // @[RegisterRouter.scala:87:24] wire _out_T_6489 = ~out_womask_647; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_548 = {hi_7, flags_0_go, _out_prepend_T_548}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6490 = out_prepend_548; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6491 = _out_T_6490; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_549 = _out_T_6491; // @[RegisterRouter.scala:87:24] wire out_rimask_648 = \|_out_rimask_T_648; // @[RegisterRouter.scala:87:24] wire out_wimask_648 = &_out_wimask_T_648; // @[RegisterRouter.scala:87:24] wire out_romask_648 = \|_out_romask_T_648; // @[RegisterRouter.scala:87:24] wire out_womask_648 = &_out_womask_T_648; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_648 = out_rivalid_1_502 & out_rimask_648; // @[RegisterRouter.scala:87:24] wire _out_T_6493 = out_f_rivalid_648; // @[RegisterRouter.scala:87:24] wire out_f_roready_648 = out_roready_1_502 & out_romask_648; // @[RegisterRouter.scala:87:24] wire _out_T_6494 = out_f_roready_648; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_648 = out_wivalid_1_502 & out_wimask_648; // @[RegisterRouter.scala:87:24] wire out_f_woready_648 = out_woready_1_502 & out_womask_648; // @[RegisterRouter.scala:87:24] wire _out_T_6495 = ~out_rimask_648; // @[RegisterRouter.scala:87:24] wire _out_T_6496 = ~out_wimask_648; // @[RegisterRouter.scala:87:24] wire _out_T_6497 = ~out_romask_648; // @[RegisterRouter.scala:87:24] wire _out_T_6498 = ~out_womask_648; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_549 = {hi_8, flags_0_go, _out_prepend_T_549}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6499 = out_prepend_549; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6500 = _out_T_6499; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_128 = _out_T_6500; // @[MuxLiteral.scala:49:48] wire out_rimask_649 = \|_out_rimask_T_649; // @[RegisterRouter.scala:87:24] wire out_wimask_649 = &_out_wimask_T_649; // @[RegisterRouter.scala:87:24] wire out_romask_649 = \|_out_romask_T_649; // @[RegisterRouter.scala:87:24] wire out_womask_649 = &_out_womask_T_649; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_649 = out_rivalid_1_503 & out_rimask_649; // @[RegisterRouter.scala:87:24] wire _out_T_6502 = out_f_rivalid_649; // @[RegisterRouter.scala:87:24] wire out_f_roready_649 = out_roready_1_503 & out_romask_649; // @[RegisterRouter.scala:87:24] wire _out_T_6503 = out_f_roready_649; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_649 = out_wivalid_1_503 & out_wimask_649; // @[RegisterRouter.scala:87:24] wire out_f_woready_649 = out_woready_1_503 & out_womask_649; // @[RegisterRouter.scala:87:24] wire _out_T_6504 = ~out_rimask_649; // @[RegisterRouter.scala:87:24] wire _out_T_6505 = ~out_wimask_649; // @[RegisterRouter.scala:87:24] wire _out_T_6506 = ~out_romask_649; // @[RegisterRouter.scala:87:24] wire _out_T_6507 = ~out_womask_649; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6509 = _out_T_6508; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_550 = _out_T_6509; // @[RegisterRouter.scala:87:24] wire out_rimask_650 = \|_out_rimask_T_650; // @[RegisterRouter.scala:87:24] wire out_wimask_650 = &_out_wimask_T_650; // @[RegisterRouter.scala:87:24] wire out_romask_650 = \|_out_romask_T_650; // @[RegisterRouter.scala:87:24] wire out_womask_650 = &_out_womask_T_650; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_650 = out_rivalid_1_504 & out_rimask_650; // @[RegisterRouter.scala:87:24] wire _out_T_6511 = out_f_rivalid_650; // @[RegisterRouter.scala:87:24] wire out_f_roready_650 = out_roready_1_504 & out_romask_650; // @[RegisterRouter.scala:87:24] wire _out_T_6512 = out_f_roready_650; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_650 = out_wivalid_1_504 & out_wimask_650; // @[RegisterRouter.scala:87:24] wire out_f_woready_650 = out_woready_1_504 & out_womask_650; // @[RegisterRouter.scala:87:24] wire _out_T_6513 = ~out_rimask_650; // @[RegisterRouter.scala:87:24] wire _out_T_6514 = ~out_wimask_650; // @[RegisterRouter.scala:87:24] wire _out_T_6515 = ~out_romask_650; // @[RegisterRouter.scala:87:24] wire _out_T_6516 = ~out_womask_650; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_550 = {hi_874, flags_0_go, _out_prepend_T_550}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6517 = out_prepend_550; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6518 = _out_T_6517; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_551 = _out_T_6518; // @[RegisterRouter.scala:87:24] wire out_rimask_651 = \|_out_rimask_T_651; // @[RegisterRouter.scala:87:24] wire out_wimask_651 = &_out_wimask_T_651; // @[RegisterRouter.scala:87:24] wire out_romask_651 = \|_out_romask_T_651; // @[RegisterRouter.scala:87:24] wire out_womask_651 = &_out_womask_T_651; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_651 = out_rivalid_1_505 & out_rimask_651; // @[RegisterRouter.scala:87:24] wire _out_T_6520 = out_f_rivalid_651; // @[RegisterRouter.scala:87:24] wire out_f_roready_651 = out_roready_1_505 & out_romask_651; // @[RegisterRouter.scala:87:24] wire _out_T_6521 = out_f_roready_651; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_651 = out_wivalid_1_505 & out_wimask_651; // @[RegisterRouter.scala:87:24] wire out_f_woready_651 = out_woready_1_505 & out_womask_651; // @[RegisterRouter.scala:87:24] wire _out_T_6522 = ~out_rimask_651; // @[RegisterRouter.scala:87:24] wire _out_T_6523 = ~out_wimask_651; // @[RegisterRouter.scala:87:24] wire _out_T_6524 = ~out_romask_651; // @[RegisterRouter.scala:87:24] wire _out_T_6525 = ~out_womask_651; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_551 = {hi_875, flags_0_go, _out_prepend_T_551}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6526 = out_prepend_551; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6527 = _out_T_6526; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_552 = _out_T_6527; // @[RegisterRouter.scala:87:24] wire out_rimask_652 = \|_out_rimask_T_652; // @[RegisterRouter.scala:87:24] wire out_wimask_652 = &_out_wimask_T_652; // @[RegisterRouter.scala:87:24] wire out_romask_652 = \|_out_romask_T_652; // @[RegisterRouter.scala:87:24] wire out_womask_652 = &_out_womask_T_652; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_652 = out_rivalid_1_506 & out_rimask_652; // @[RegisterRouter.scala:87:24] wire _out_T_6529 = out_f_rivalid_652; // @[RegisterRouter.scala:87:24] wire out_f_roready_652 = out_roready_1_506 & out_romask_652; // @[RegisterRouter.scala:87:24] wire _out_T_6530 = out_f_roready_652; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_652 = out_wivalid_1_506 & out_wimask_652; // @[RegisterRouter.scala:87:24] wire out_f_woready_652 = out_woready_1_506 & out_womask_652; // @[RegisterRouter.scala:87:24] wire _out_T_6531 = ~out_rimask_652; // @[RegisterRouter.scala:87:24] wire _out_T_6532 = ~out_wimask_652; // @[RegisterRouter.scala:87:24] wire _out_T_6533 = ~out_romask_652; // @[RegisterRouter.scala:87:24] wire _out_T_6534 = ~out_womask_652; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_552 = {hi_876, flags_0_go, _out_prepend_T_552}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6535 = out_prepend_552; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6536 = _out_T_6535; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_553 = _out_T_6536; // @[RegisterRouter.scala:87:24] wire out_rimask_653 = \|_out_rimask_T_653; // @[RegisterRouter.scala:87:24] wire out_wimask_653 = &_out_wimask_T_653; // @[RegisterRouter.scala:87:24] wire out_romask_653 = \|_out_romask_T_653; // @[RegisterRouter.scala:87:24] wire out_womask_653 = &_out_womask_T_653; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_653 = out_rivalid_1_507 & out_rimask_653; // @[RegisterRouter.scala:87:24] wire _out_T_6538 = out_f_rivalid_653; // @[RegisterRouter.scala:87:24] wire out_f_roready_653 = out_roready_1_507 & out_romask_653; // @[RegisterRouter.scala:87:24] wire _out_T_6539 = out_f_roready_653; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_653 = out_wivalid_1_507 & out_wimask_653; // @[RegisterRouter.scala:87:24] wire out_f_woready_653 = out_woready_1_507 & out_womask_653; // @[RegisterRouter.scala:87:24] wire _out_T_6540 = ~out_rimask_653; // @[RegisterRouter.scala:87:24] wire _out_T_6541 = ~out_wimask_653; // @[RegisterRouter.scala:87:24] wire _out_T_6542 = ~out_romask_653; // @[RegisterRouter.scala:87:24] wire _out_T_6543 = ~out_womask_653; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_553 = {hi_877, flags_0_go, _out_prepend_T_553}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6544 = out_prepend_553; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6545 = _out_T_6544; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_554 = _out_T_6545; // @[RegisterRouter.scala:87:24] wire out_rimask_654 = \|_out_rimask_T_654; // @[RegisterRouter.scala:87:24] wire out_wimask_654 = &_out_wimask_T_654; // @[RegisterRouter.scala:87:24] wire out_romask_654 = \|_out_romask_T_654; // @[RegisterRouter.scala:87:24] wire out_womask_654 = &_out_womask_T_654; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_654 = out_rivalid_1_508 & out_rimask_654; // @[RegisterRouter.scala:87:24] wire _out_T_6547 = out_f_rivalid_654; // @[RegisterRouter.scala:87:24] wire out_f_roready_654 = out_roready_1_508 & out_romask_654; // @[RegisterRouter.scala:87:24] wire _out_T_6548 = out_f_roready_654; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_654 = out_wivalid_1_508 & out_wimask_654; // @[RegisterRouter.scala:87:24] wire out_f_woready_654 = out_woready_1_508 & out_womask_654; // @[RegisterRouter.scala:87:24] wire _out_T_6549 = ~out_rimask_654; // @[RegisterRouter.scala:87:24] wire _out_T_6550 = ~out_wimask_654; // @[RegisterRouter.scala:87:24] wire _out_T_6551 = ~out_romask_654; // @[RegisterRouter.scala:87:24] wire _out_T_6552 = ~out_womask_654; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_554 = {hi_878, flags_0_go, _out_prepend_T_554}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6553 = out_prepend_554; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6554 = _out_T_6553; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_555 = _out_T_6554; // @[RegisterRouter.scala:87:24] wire out_rimask_655 = \|_out_rimask_T_655; // @[RegisterRouter.scala:87:24] wire out_wimask_655 = &_out_wimask_T_655; // @[RegisterRouter.scala:87:24] wire out_romask_655 = \|_out_romask_T_655; // @[RegisterRouter.scala:87:24] wire out_womask_655 = &_out_womask_T_655; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_655 = out_rivalid_1_509 & out_rimask_655; // @[RegisterRouter.scala:87:24] wire _out_T_6556 = out_f_rivalid_655; // @[RegisterRouter.scala:87:24] wire out_f_roready_655 = out_roready_1_509 & out_romask_655; // @[RegisterRouter.scala:87:24] wire _out_T_6557 = out_f_roready_655; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_655 = out_wivalid_1_509 & out_wimask_655; // @[RegisterRouter.scala:87:24] wire out_f_woready_655 = out_woready_1_509 & out_womask_655; // @[RegisterRouter.scala:87:24] wire _out_T_6558 = ~out_rimask_655; // @[RegisterRouter.scala:87:24] wire _out_T_6559 = ~out_wimask_655; // @[RegisterRouter.scala:87:24] wire _out_T_6560 = ~out_romask_655; // @[RegisterRouter.scala:87:24] wire _out_T_6561 = ~out_womask_655; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_555 = {hi_879, flags_0_go, _out_prepend_T_555}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6562 = out_prepend_555; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6563 = _out_T_6562; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_556 = _out_T_6563; // @[RegisterRouter.scala:87:24] wire out_rimask_656 = \|_out_rimask_T_656; // @[RegisterRouter.scala:87:24] wire out_wimask_656 = &_out_wimask_T_656; // @[RegisterRouter.scala:87:24] wire out_romask_656 = \|_out_romask_T_656; // @[RegisterRouter.scala:87:24] wire out_womask_656 = &_out_womask_T_656; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_656 = out_rivalid_1_510 & out_rimask_656; // @[RegisterRouter.scala:87:24] wire _out_T_6565 = out_f_rivalid_656; // @[RegisterRouter.scala:87:24] wire out_f_roready_656 = out_roready_1_510 & out_romask_656; // @[RegisterRouter.scala:87:24] wire _out_T_6566 = out_f_roready_656; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_656 = out_wivalid_1_510 & out_wimask_656; // @[RegisterRouter.scala:87:24] wire out_f_woready_656 = out_woready_1_510 & out_womask_656; // @[RegisterRouter.scala:87:24] wire _out_T_6567 = ~out_rimask_656; // @[RegisterRouter.scala:87:24] wire _out_T_6568 = ~out_wimask_656; // @[RegisterRouter.scala:87:24] wire _out_T_6569 = ~out_romask_656; // @[RegisterRouter.scala:87:24] wire _out_T_6570 = ~out_womask_656; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_556 = {hi_880, flags_0_go, _out_prepend_T_556}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6571 = out_prepend_556; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6572 = _out_T_6571; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_237 = _out_T_6572; // @[MuxLiteral.scala:49:48] wire out_rimask_657 = \|_out_rimask_T_657; // @[RegisterRouter.scala:87:24] wire out_wimask_657 = &_out_wimask_T_657; // @[RegisterRouter.scala:87:24] wire out_romask_657 = \|_out_romask_T_657; // @[RegisterRouter.scala:87:24] wire out_womask_657 = &_out_womask_T_657; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_657 = out_rivalid_1_511 & out_rimask_657; // @[RegisterRouter.scala:87:24] wire _out_T_6574 = out_f_rivalid_657; // @[RegisterRouter.scala:87:24] wire out_f_roready_657 = out_roready_1_511 & out_romask_657; // @[RegisterRouter.scala:87:24] wire _out_T_6575 = out_f_roready_657; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_657 = out_wivalid_1_511 & out_wimask_657; // @[RegisterRouter.scala:87:24] wire _out_T_6576 = out_f_wivalid_657; // @[RegisterRouter.scala:87:24] wire out_f_woready_657 = out_woready_1_511 & out_womask_657; // @[RegisterRouter.scala:87:24] wire _out_T_6577 = out_f_woready_657; // @[RegisterRouter.scala:87:24] wire _out_T_6578 = ~out_rimask_657; // @[RegisterRouter.scala:87:24] wire _out_T_6579 = ~out_wimask_657; // @[RegisterRouter.scala:87:24] wire _out_T_6580 = ~out_romask_657; // @[RegisterRouter.scala:87:24] wire _out_T_6581 = ~out_womask_657; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6583 = _out_T_6582; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_557 = _out_T_6583; // @[RegisterRouter.scala:87:24] wire out_rimask_658 = \|_out_rimask_T_658; // @[RegisterRouter.scala:87:24] wire out_wimask_658 = &_out_wimask_T_658; // @[RegisterRouter.scala:87:24] wire out_romask_658 = \|_out_romask_T_658; // @[RegisterRouter.scala:87:24] wire out_womask_658 = &_out_womask_T_658; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_658 = out_rivalid_1_512 & out_rimask_658; // @[RegisterRouter.scala:87:24] wire _out_T_6585 = out_f_rivalid_658; // @[RegisterRouter.scala:87:24] wire out_f_roready_658 = out_roready_1_512 & out_romask_658; // @[RegisterRouter.scala:87:24] wire _out_T_6586 = out_f_roready_658; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_658 = out_wivalid_1_512 & out_wimask_658; // @[RegisterRouter.scala:87:24] wire _out_T_6587 = out_f_wivalid_658; // @[RegisterRouter.scala:87:24] wire out_f_woready_658 = out_woready_1_512 & out_womask_658; // @[RegisterRouter.scala:87:24] wire _out_T_6588 = out_f_woready_658; // @[RegisterRouter.scala:87:24] wire _out_T_6589 = ~out_rimask_658; // @[RegisterRouter.scala:87:24] wire _out_T_6590 = ~out_wimask_658; // @[RegisterRouter.scala:87:24] wire _out_T_6591 = ~out_romask_658; // @[RegisterRouter.scala:87:24] wire _out_T_6592 = ~out_womask_658; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_557 = {programBufferMem_9, _out_prepend_T_557}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6593 = out_prepend_557; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6594 = _out_T_6593; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_558 = _out_T_6594; // @[RegisterRouter.scala:87:24] wire out_rimask_659 = \|_out_rimask_T_659; // @[RegisterRouter.scala:87:24] wire out_wimask_659 = &_out_wimask_T_659; // @[RegisterRouter.scala:87:24] wire out_romask_659 = \|_out_romask_T_659; // @[RegisterRouter.scala:87:24] wire out_womask_659 = &_out_womask_T_659; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_659 = out_rivalid_1_513 & out_rimask_659; // @[RegisterRouter.scala:87:24] wire _out_T_6596 = out_f_rivalid_659; // @[RegisterRouter.scala:87:24] wire out_f_roready_659 = out_roready_1_513 & out_romask_659; // @[RegisterRouter.scala:87:24] wire _out_T_6597 = out_f_roready_659; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_659 = out_wivalid_1_513 & out_wimask_659; // @[RegisterRouter.scala:87:24] wire _out_T_6598 = out_f_wivalid_659; // @[RegisterRouter.scala:87:24] wire out_f_woready_659 = out_woready_1_513 & out_womask_659; // @[RegisterRouter.scala:87:24] wire _out_T_6599 = out_f_woready_659; // @[RegisterRouter.scala:87:24] wire _out_T_6600 = ~out_rimask_659; // @[RegisterRouter.scala:87:24] wire _out_T_6601 = ~out_wimask_659; // @[RegisterRouter.scala:87:24] wire _out_T_6602 = ~out_romask_659; // @[RegisterRouter.scala:87:24] wire _out_T_6603 = ~out_womask_659; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_558 = {programBufferMem_10, _out_prepend_T_558}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6604 = out_prepend_558; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6605 = _out_T_6604; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_559 = _out_T_6605; // @[RegisterRouter.scala:87:24] wire out_rimask_660 = \|_out_rimask_T_660; // @[RegisterRouter.scala:87:24] wire out_wimask_660 = &_out_wimask_T_660; // @[RegisterRouter.scala:87:24] wire out_romask_660 = \|_out_romask_T_660; // @[RegisterRouter.scala:87:24] wire out_womask_660 = &_out_womask_T_660; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_660 = out_rivalid_1_514 & out_rimask_660; // @[RegisterRouter.scala:87:24] wire _out_T_6607 = out_f_rivalid_660; // @[RegisterRouter.scala:87:24] wire out_f_roready_660 = out_roready_1_514 & out_romask_660; // @[RegisterRouter.scala:87:24] wire _out_T_6608 = out_f_roready_660; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_660 = out_wivalid_1_514 & out_wimask_660; // @[RegisterRouter.scala:87:24] wire _out_T_6609 = out_f_wivalid_660; // @[RegisterRouter.scala:87:24] wire out_f_woready_660 = out_woready_1_514 & out_womask_660; // @[RegisterRouter.scala:87:24] wire _out_T_6610 = out_f_woready_660; // @[RegisterRouter.scala:87:24] wire _out_T_6611 = ~out_rimask_660; // @[RegisterRouter.scala:87:24] wire _out_T_6612 = ~out_wimask_660; // @[RegisterRouter.scala:87:24] wire _out_T_6613 = ~out_romask_660; // @[RegisterRouter.scala:87:24] wire _out_T_6614 = ~out_womask_660; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_559 = {programBufferMem_11, _out_prepend_T_559}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6615 = out_prepend_559; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6616 = _out_T_6615; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_560 = _out_T_6616; // @[RegisterRouter.scala:87:24] wire out_rimask_661 = \|_out_rimask_T_661; // @[RegisterRouter.scala:87:24] wire out_wimask_661 = &_out_wimask_T_661; // @[RegisterRouter.scala:87:24] wire out_romask_661 = \|_out_romask_T_661; // @[RegisterRouter.scala:87:24] wire out_womask_661 = &_out_womask_T_661; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_661 = out_rivalid_1_515 & out_rimask_661; // @[RegisterRouter.scala:87:24] wire _out_T_6618 = out_f_rivalid_661; // @[RegisterRouter.scala:87:24] wire out_f_roready_661 = out_roready_1_515 & out_romask_661; // @[RegisterRouter.scala:87:24] wire _out_T_6619 = out_f_roready_661; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_661 = out_wivalid_1_515 & out_wimask_661; // @[RegisterRouter.scala:87:24] wire _out_T_6620 = out_f_wivalid_661; // @[RegisterRouter.scala:87:24] wire out_f_woready_661 = out_woready_1_515 & out_womask_661; // @[RegisterRouter.scala:87:24] wire _out_T_6621 = out_f_woready_661; // @[RegisterRouter.scala:87:24] wire _out_T_6622 = ~out_rimask_661; // @[RegisterRouter.scala:87:24] wire _out_T_6623 = ~out_wimask_661; // @[RegisterRouter.scala:87:24] wire _out_T_6624 = ~out_romask_661; // @[RegisterRouter.scala:87:24] wire _out_T_6625 = ~out_womask_661; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_560 = {programBufferMem_12, _out_prepend_T_560}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6626 = out_prepend_560; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6627 = _out_T_6626; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_561 = _out_T_6627; // @[RegisterRouter.scala:87:24] wire out_rimask_662 = \|_out_rimask_T_662; // @[RegisterRouter.scala:87:24] wire out_wimask_662 = &_out_wimask_T_662; // @[RegisterRouter.scala:87:24] wire out_romask_662 = \|_out_romask_T_662; // @[RegisterRouter.scala:87:24] wire out_womask_662 = &_out_womask_T_662; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_662 = out_rivalid_1_516 & out_rimask_662; // @[RegisterRouter.scala:87:24] wire _out_T_6629 = out_f_rivalid_662; // @[RegisterRouter.scala:87:24] wire out_f_roready_662 = out_roready_1_516 & out_romask_662; // @[RegisterRouter.scala:87:24] wire _out_T_6630 = out_f_roready_662; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_662 = out_wivalid_1_516 & out_wimask_662; // @[RegisterRouter.scala:87:24] wire _out_T_6631 = out_f_wivalid_662; // @[RegisterRouter.scala:87:24] wire out_f_woready_662 = out_woready_1_516 & out_womask_662; // @[RegisterRouter.scala:87:24] wire _out_T_6632 = out_f_woready_662; // @[RegisterRouter.scala:87:24] wire _out_T_6633 = ~out_rimask_662; // @[RegisterRouter.scala:87:24] wire _out_T_6634 = ~out_wimask_662; // @[RegisterRouter.scala:87:24] wire _out_T_6635 = ~out_romask_662; // @[RegisterRouter.scala:87:24] wire _out_T_6636 = ~out_womask_662; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_561 = {programBufferMem_13, _out_prepend_T_561}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6637 = out_prepend_561; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6638 = _out_T_6637; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_562 = _out_T_6638; // @[RegisterRouter.scala:87:24] wire out_rimask_663 = \|_out_rimask_T_663; // @[RegisterRouter.scala:87:24] wire out_wimask_663 = &_out_wimask_T_663; // @[RegisterRouter.scala:87:24] wire out_romask_663 = \|_out_romask_T_663; // @[RegisterRouter.scala:87:24] wire out_womask_663 = &_out_womask_T_663; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_663 = out_rivalid_1_517 & out_rimask_663; // @[RegisterRouter.scala:87:24] wire _out_T_6640 = out_f_rivalid_663; // @[RegisterRouter.scala:87:24] wire out_f_roready_663 = out_roready_1_517 & out_romask_663; // @[RegisterRouter.scala:87:24] wire _out_T_6641 = out_f_roready_663; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_663 = out_wivalid_1_517 & out_wimask_663; // @[RegisterRouter.scala:87:24] wire _out_T_6642 = out_f_wivalid_663; // @[RegisterRouter.scala:87:24] wire out_f_woready_663 = out_woready_1_517 & out_womask_663; // @[RegisterRouter.scala:87:24] wire _out_T_6643 = out_f_woready_663; // @[RegisterRouter.scala:87:24] wire _out_T_6644 = ~out_rimask_663; // @[RegisterRouter.scala:87:24] wire _out_T_6645 = ~out_wimask_663; // @[RegisterRouter.scala:87:24] wire _out_T_6646 = ~out_romask_663; // @[RegisterRouter.scala:87:24] wire _out_T_6647 = ~out_womask_663; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_562 = {programBufferMem_14, _out_prepend_T_562}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6648 = out_prepend_562; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6649 = _out_T_6648; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_563 = _out_T_6649; // @[RegisterRouter.scala:87:24] wire out_rimask_664 = \|_out_rimask_T_664; // @[RegisterRouter.scala:87:24] wire out_wimask_664 = &_out_wimask_T_664; // @[RegisterRouter.scala:87:24] wire out_romask_664 = \|_out_romask_T_664; // @[RegisterRouter.scala:87:24] wire out_womask_664 = &_out_womask_T_664; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_664 = out_rivalid_1_518 & out_rimask_664; // @[RegisterRouter.scala:87:24] wire _out_T_6651 = out_f_rivalid_664; // @[RegisterRouter.scala:87:24] wire out_f_roready_664 = out_roready_1_518 & out_romask_664; // @[RegisterRouter.scala:87:24] wire _out_T_6652 = out_f_roready_664; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_664 = out_wivalid_1_518 & out_wimask_664; // @[RegisterRouter.scala:87:24] wire _out_T_6653 = out_f_wivalid_664; // @[RegisterRouter.scala:87:24] wire out_f_woready_664 = out_woready_1_518 & out_womask_664; // @[RegisterRouter.scala:87:24] wire _out_T_6654 = out_f_woready_664; // @[RegisterRouter.scala:87:24] wire _out_T_6655 = ~out_rimask_664; // @[RegisterRouter.scala:87:24] wire _out_T_6656 = ~out_wimask_664; // @[RegisterRouter.scala:87:24] wire _out_T_6657 = ~out_romask_664; // @[RegisterRouter.scala:87:24] wire _out_T_6658 = ~out_womask_664; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_563 = {programBufferMem_15, _out_prepend_T_563}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6659 = out_prepend_563; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6660 = _out_T_6659; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_105 = _out_T_6660; // @[MuxLiteral.scala:49:48] wire out_rimask_665 = \|_out_rimask_T_665; // @[RegisterRouter.scala:87:24] wire out_wimask_665 = &_out_wimask_T_665; // @[RegisterRouter.scala:87:24] wire out_romask_665 = \|_out_romask_T_665; // @[RegisterRouter.scala:87:24] wire out_womask_665 = &_out_womask_T_665; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_665 = out_rivalid_1_519 & out_rimask_665; // @[RegisterRouter.scala:87:24] wire _out_T_6662 = out_f_rivalid_665; // @[RegisterRouter.scala:87:24] wire out_f_roready_665 = out_roready_1_519 & out_romask_665; // @[RegisterRouter.scala:87:24] wire _out_T_6663 = out_f_roready_665; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_665 = out_wivalid_1_519 & out_wimask_665; // @[RegisterRouter.scala:87:24] wire out_f_woready_665 = out_woready_1_519 & out_womask_665; // @[RegisterRouter.scala:87:24] wire _out_T_6664 = ~out_rimask_665; // @[RegisterRouter.scala:87:24] wire _out_T_6665 = ~out_wimask_665; // @[RegisterRouter.scala:87:24] wire _out_T_6666 = ~out_romask_665; // @[RegisterRouter.scala:87:24] wire _out_T_6667 = ~out_womask_665; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6669 = _out_T_6668; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_564 = _out_T_6669; // @[RegisterRouter.scala:87:24] wire out_rimask_666 = \|_out_rimask_T_666; // @[RegisterRouter.scala:87:24] wire out_wimask_666 = &_out_wimask_T_666; // @[RegisterRouter.scala:87:24] wire out_romask_666 = \|_out_romask_T_666; // @[RegisterRouter.scala:87:24] wire out_womask_666 = &_out_womask_T_666; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_666 = out_rivalid_1_520 & out_rimask_666; // @[RegisterRouter.scala:87:24] wire _out_T_6671 = out_f_rivalid_666; // @[RegisterRouter.scala:87:24] wire out_f_roready_666 = out_roready_1_520 & out_romask_666; // @[RegisterRouter.scala:87:24] wire _out_T_6672 = out_f_roready_666; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_666 = out_wivalid_1_520 & out_wimask_666; // @[RegisterRouter.scala:87:24] wire out_f_woready_666 = out_woready_1_520 & out_womask_666; // @[RegisterRouter.scala:87:24] wire _out_T_6673 = ~out_rimask_666; // @[RegisterRouter.scala:87:24] wire _out_T_6674 = ~out_wimask_666; // @[RegisterRouter.scala:87:24] wire _out_T_6675 = ~out_romask_666; // @[RegisterRouter.scala:87:24] wire _out_T_6676 = ~out_womask_666; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_564 = {hi_930, flags_0_go, _out_prepend_T_564}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6677 = out_prepend_564; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6678 = _out_T_6677; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_565 = _out_T_6678; // @[RegisterRouter.scala:87:24] wire out_rimask_667 = \|_out_rimask_T_667; // @[RegisterRouter.scala:87:24] wire out_wimask_667 = &_out_wimask_T_667; // @[RegisterRouter.scala:87:24] wire out_romask_667 = \|_out_romask_T_667; // @[RegisterRouter.scala:87:24] wire out_womask_667 = &_out_womask_T_667; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_667 = out_rivalid_1_521 & out_rimask_667; // @[RegisterRouter.scala:87:24] wire _out_T_6680 = out_f_rivalid_667; // @[RegisterRouter.scala:87:24] wire out_f_roready_667 = out_roready_1_521 & out_romask_667; // @[RegisterRouter.scala:87:24] wire _out_T_6681 = out_f_roready_667; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_667 = out_wivalid_1_521 & out_wimask_667; // @[RegisterRouter.scala:87:24] wire out_f_woready_667 = out_woready_1_521 & out_womask_667; // @[RegisterRouter.scala:87:24] wire _out_T_6682 = ~out_rimask_667; // @[RegisterRouter.scala:87:24] wire _out_T_6683 = ~out_wimask_667; // @[RegisterRouter.scala:87:24] wire _out_T_6684 = ~out_romask_667; // @[RegisterRouter.scala:87:24] wire _out_T_6685 = ~out_womask_667; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_565 = {hi_931, flags_0_go, _out_prepend_T_565}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6686 = out_prepend_565; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6687 = _out_T_6686; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_566 = _out_T_6687; // @[RegisterRouter.scala:87:24] wire out_rimask_668 = \|_out_rimask_T_668; // @[RegisterRouter.scala:87:24] wire out_wimask_668 = &_out_wimask_T_668; // @[RegisterRouter.scala:87:24] wire out_romask_668 = \|_out_romask_T_668; // @[RegisterRouter.scala:87:24] wire out_womask_668 = &_out_womask_T_668; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_668 = out_rivalid_1_522 & out_rimask_668; // @[RegisterRouter.scala:87:24] wire _out_T_6689 = out_f_rivalid_668; // @[RegisterRouter.scala:87:24] wire out_f_roready_668 = out_roready_1_522 & out_romask_668; // @[RegisterRouter.scala:87:24] wire _out_T_6690 = out_f_roready_668; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_668 = out_wivalid_1_522 & out_wimask_668; // @[RegisterRouter.scala:87:24] wire out_f_woready_668 = out_woready_1_522 & out_womask_668; // @[RegisterRouter.scala:87:24] wire _out_T_6691 = ~out_rimask_668; // @[RegisterRouter.scala:87:24] wire _out_T_6692 = ~out_wimask_668; // @[RegisterRouter.scala:87:24] wire _out_T_6693 = ~out_romask_668; // @[RegisterRouter.scala:87:24] wire _out_T_6694 = ~out_womask_668; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_566 = {hi_932, flags_0_go, _out_prepend_T_566}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6695 = out_prepend_566; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6696 = _out_T_6695; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_567 = _out_T_6696; // @[RegisterRouter.scala:87:24] wire out_rimask_669 = \|_out_rimask_T_669; // @[RegisterRouter.scala:87:24] wire out_wimask_669 = &_out_wimask_T_669; // @[RegisterRouter.scala:87:24] wire out_romask_669 = \|_out_romask_T_669; // @[RegisterRouter.scala:87:24] wire out_womask_669 = &_out_womask_T_669; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_669 = out_rivalid_1_523 & out_rimask_669; // @[RegisterRouter.scala:87:24] wire _out_T_6698 = out_f_rivalid_669; // @[RegisterRouter.scala:87:24] wire out_f_roready_669 = out_roready_1_523 & out_romask_669; // @[RegisterRouter.scala:87:24] wire _out_T_6699 = out_f_roready_669; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_669 = out_wivalid_1_523 & out_wimask_669; // @[RegisterRouter.scala:87:24] wire out_f_woready_669 = out_woready_1_523 & out_womask_669; // @[RegisterRouter.scala:87:24] wire _out_T_6700 = ~out_rimask_669; // @[RegisterRouter.scala:87:24] wire _out_T_6701 = ~out_wimask_669; // @[RegisterRouter.scala:87:24] wire _out_T_6702 = ~out_romask_669; // @[RegisterRouter.scala:87:24] wire _out_T_6703 = ~out_womask_669; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_567 = {hi_933, flags_0_go, _out_prepend_T_567}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6704 = out_prepend_567; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6705 = _out_T_6704; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_568 = _out_T_6705; // @[RegisterRouter.scala:87:24] wire out_rimask_670 = \|_out_rimask_T_670; // @[RegisterRouter.scala:87:24] wire out_wimask_670 = &_out_wimask_T_670; // @[RegisterRouter.scala:87:24] wire out_romask_670 = \|_out_romask_T_670; // @[RegisterRouter.scala:87:24] wire out_womask_670 = &_out_womask_T_670; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_670 = out_rivalid_1_524 & out_rimask_670; // @[RegisterRouter.scala:87:24] wire _out_T_6707 = out_f_rivalid_670; // @[RegisterRouter.scala:87:24] wire out_f_roready_670 = out_roready_1_524 & out_romask_670; // @[RegisterRouter.scala:87:24] wire _out_T_6708 = out_f_roready_670; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_670 = out_wivalid_1_524 & out_wimask_670; // @[RegisterRouter.scala:87:24] wire out_f_woready_670 = out_woready_1_524 & out_womask_670; // @[RegisterRouter.scala:87:24] wire _out_T_6709 = ~out_rimask_670; // @[RegisterRouter.scala:87:24] wire _out_T_6710 = ~out_wimask_670; // @[RegisterRouter.scala:87:24] wire _out_T_6711 = ~out_romask_670; // @[RegisterRouter.scala:87:24] wire _out_T_6712 = ~out_womask_670; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_568 = {hi_934, flags_0_go, _out_prepend_T_568}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6713 = out_prepend_568; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6714 = _out_T_6713; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_569 = _out_T_6714; // @[RegisterRouter.scala:87:24] wire out_rimask_671 = \|_out_rimask_T_671; // @[RegisterRouter.scala:87:24] wire out_wimask_671 = &_out_wimask_T_671; // @[RegisterRouter.scala:87:24] wire out_romask_671 = \|_out_romask_T_671; // @[RegisterRouter.scala:87:24] wire out_womask_671 = &_out_womask_T_671; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_671 = out_rivalid_1_525 & out_rimask_671; // @[RegisterRouter.scala:87:24] wire _out_T_6716 = out_f_rivalid_671; // @[RegisterRouter.scala:87:24] wire out_f_roready_671 = out_roready_1_525 & out_romask_671; // @[RegisterRouter.scala:87:24] wire _out_T_6717 = out_f_roready_671; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_671 = out_wivalid_1_525 & out_wimask_671; // @[RegisterRouter.scala:87:24] wire out_f_woready_671 = out_woready_1_525 & out_womask_671; // @[RegisterRouter.scala:87:24] wire _out_T_6718 = ~out_rimask_671; // @[RegisterRouter.scala:87:24] wire _out_T_6719 = ~out_wimask_671; // @[RegisterRouter.scala:87:24] wire _out_T_6720 = ~out_romask_671; // @[RegisterRouter.scala:87:24] wire _out_T_6721 = ~out_womask_671; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_569 = {hi_935, flags_0_go, _out_prepend_T_569}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6722 = out_prepend_569; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6723 = _out_T_6722; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_570 = _out_T_6723; // @[RegisterRouter.scala:87:24] wire out_rimask_672 = \|_out_rimask_T_672; // @[RegisterRouter.scala:87:24] wire out_wimask_672 = &_out_wimask_T_672; // @[RegisterRouter.scala:87:24] wire out_romask_672 = \|_out_romask_T_672; // @[RegisterRouter.scala:87:24] wire out_womask_672 = &_out_womask_T_672; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_672 = out_rivalid_1_526 & out_rimask_672; // @[RegisterRouter.scala:87:24] wire _out_T_6725 = out_f_rivalid_672; // @[RegisterRouter.scala:87:24] wire out_f_roready_672 = out_roready_1_526 & out_romask_672; // @[RegisterRouter.scala:87:24] wire _out_T_6726 = out_f_roready_672; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_672 = out_wivalid_1_526 & out_wimask_672; // @[RegisterRouter.scala:87:24] wire out_f_woready_672 = out_woready_1_526 & out_womask_672; // @[RegisterRouter.scala:87:24] wire _out_T_6727 = ~out_rimask_672; // @[RegisterRouter.scala:87:24] wire _out_T_6728 = ~out_wimask_672; // @[RegisterRouter.scala:87:24] wire _out_T_6729 = ~out_romask_672; // @[RegisterRouter.scala:87:24] wire _out_T_6730 = ~out_womask_672; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_570 = {hi_936, flags_0_go, _out_prepend_T_570}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6731 = out_prepend_570; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6732 = _out_T_6731; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_244 = _out_T_6732; // @[MuxLiteral.scala:49:48] wire out_rimask_673 = \|_out_rimask_T_673; // @[RegisterRouter.scala:87:24] wire out_wimask_673 = &_out_wimask_T_673; // @[RegisterRouter.scala:87:24] wire out_romask_673 = \|_out_romask_T_673; // @[RegisterRouter.scala:87:24] wire out_womask_673 = &_out_womask_T_673; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_673 = out_rivalid_1_527 & out_rimask_673; // @[RegisterRouter.scala:87:24] wire _out_T_6734 = out_f_rivalid_673; // @[RegisterRouter.scala:87:24] wire out_f_roready_673 = out_roready_1_527 & out_romask_673; // @[RegisterRouter.scala:87:24] wire _out_T_6735 = out_f_roready_673; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_673 = out_wivalid_1_527 & out_wimask_673; // @[RegisterRouter.scala:87:24] wire out_f_woready_673 = out_woready_1_527 & out_womask_673; // @[RegisterRouter.scala:87:24] wire _out_T_6736 = ~out_rimask_673; // @[RegisterRouter.scala:87:24] wire _out_T_6737 = ~out_wimask_673; // @[RegisterRouter.scala:87:24] wire _out_T_6738 = ~out_romask_673; // @[RegisterRouter.scala:87:24] wire _out_T_6739 = ~out_womask_673; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6741 = _out_T_6740; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_571 = _out_T_6741; // @[RegisterRouter.scala:87:24] wire out_rimask_674 = \|_out_rimask_T_674; // @[RegisterRouter.scala:87:24] wire out_wimask_674 = &_out_wimask_T_674; // @[RegisterRouter.scala:87:24] wire out_romask_674 = \|_out_romask_T_674; // @[RegisterRouter.scala:87:24] wire out_womask_674 = &_out_womask_T_674; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_674 = out_rivalid_1_528 & out_rimask_674; // @[RegisterRouter.scala:87:24] wire _out_T_6743 = out_f_rivalid_674; // @[RegisterRouter.scala:87:24] wire out_f_roready_674 = out_roready_1_528 & out_romask_674; // @[RegisterRouter.scala:87:24] wire _out_T_6744 = out_f_roready_674; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_674 = out_wivalid_1_528 & out_wimask_674; // @[RegisterRouter.scala:87:24] wire out_f_woready_674 = out_woready_1_528 & out_womask_674; // @[RegisterRouter.scala:87:24] wire _out_T_6745 = ~out_rimask_674; // @[RegisterRouter.scala:87:24] wire _out_T_6746 = ~out_wimask_674; // @[RegisterRouter.scala:87:24] wire _out_T_6747 = ~out_romask_674; // @[RegisterRouter.scala:87:24] wire _out_T_6748 = ~out_womask_674; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_571 = {hi_306, flags_0_go, _out_prepend_T_571}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6749 = out_prepend_571; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6750 = _out_T_6749; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_572 = _out_T_6750; // @[RegisterRouter.scala:87:24] wire out_rimask_675 = \|_out_rimask_T_675; // @[RegisterRouter.scala:87:24] wire out_wimask_675 = &_out_wimask_T_675; // @[RegisterRouter.scala:87:24] wire out_romask_675 = \|_out_romask_T_675; // @[RegisterRouter.scala:87:24] wire out_womask_675 = &_out_womask_T_675; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_675 = out_rivalid_1_529 & out_rimask_675; // @[RegisterRouter.scala:87:24] wire _out_T_6752 = out_f_rivalid_675; // @[RegisterRouter.scala:87:24] wire out_f_roready_675 = out_roready_1_529 & out_romask_675; // @[RegisterRouter.scala:87:24] wire _out_T_6753 = out_f_roready_675; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_675 = out_wivalid_1_529 & out_wimask_675; // @[RegisterRouter.scala:87:24] wire out_f_woready_675 = out_woready_1_529 & out_womask_675; // @[RegisterRouter.scala:87:24] wire _out_T_6754 = ~out_rimask_675; // @[RegisterRouter.scala:87:24] wire _out_T_6755 = ~out_wimask_675; // @[RegisterRouter.scala:87:24] wire _out_T_6756 = ~out_romask_675; // @[RegisterRouter.scala:87:24] wire _out_T_6757 = ~out_womask_675; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_572 = {hi_307, flags_0_go, _out_prepend_T_572}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6758 = out_prepend_572; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6759 = _out_T_6758; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_573 = _out_T_6759; // @[RegisterRouter.scala:87:24] wire out_rimask_676 = \|_out_rimask_T_676; // @[RegisterRouter.scala:87:24] wire out_wimask_676 = &_out_wimask_T_676; // @[RegisterRouter.scala:87:24] wire out_romask_676 = \|_out_romask_T_676; // @[RegisterRouter.scala:87:24] wire out_womask_676 = &_out_womask_T_676; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_676 = out_rivalid_1_530 & out_rimask_676; // @[RegisterRouter.scala:87:24] wire _out_T_6761 = out_f_rivalid_676; // @[RegisterRouter.scala:87:24] wire out_f_roready_676 = out_roready_1_530 & out_romask_676; // @[RegisterRouter.scala:87:24] wire _out_T_6762 = out_f_roready_676; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_676 = out_wivalid_1_530 & out_wimask_676; // @[RegisterRouter.scala:87:24] wire out_f_woready_676 = out_woready_1_530 & out_womask_676; // @[RegisterRouter.scala:87:24] wire _out_T_6763 = ~out_rimask_676; // @[RegisterRouter.scala:87:24] wire _out_T_6764 = ~out_wimask_676; // @[RegisterRouter.scala:87:24] wire _out_T_6765 = ~out_romask_676; // @[RegisterRouter.scala:87:24] wire _out_T_6766 = ~out_womask_676; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_573 = {hi_308, flags_0_go, _out_prepend_T_573}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6767 = out_prepend_573; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6768 = _out_T_6767; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_574 = _out_T_6768; // @[RegisterRouter.scala:87:24] wire out_rimask_677 = \|_out_rimask_T_677; // @[RegisterRouter.scala:87:24] wire out_wimask_677 = &_out_wimask_T_677; // @[RegisterRouter.scala:87:24] wire out_romask_677 = \|_out_romask_T_677; // @[RegisterRouter.scala:87:24] wire out_womask_677 = &_out_womask_T_677; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_677 = out_rivalid_1_531 & out_rimask_677; // @[RegisterRouter.scala:87:24] wire _out_T_6770 = out_f_rivalid_677; // @[RegisterRouter.scala:87:24] wire out_f_roready_677 = out_roready_1_531 & out_romask_677; // @[RegisterRouter.scala:87:24] wire _out_T_6771 = out_f_roready_677; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_677 = out_wivalid_1_531 & out_wimask_677; // @[RegisterRouter.scala:87:24] wire out_f_woready_677 = out_woready_1_531 & out_womask_677; // @[RegisterRouter.scala:87:24] wire _out_T_6772 = ~out_rimask_677; // @[RegisterRouter.scala:87:24] wire _out_T_6773 = ~out_wimask_677; // @[RegisterRouter.scala:87:24] wire _out_T_6774 = ~out_romask_677; // @[RegisterRouter.scala:87:24] wire _out_T_6775 = ~out_womask_677; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_574 = {hi_309, flags_0_go, _out_prepend_T_574}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6776 = out_prepend_574; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6777 = _out_T_6776; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_575 = _out_T_6777; // @[RegisterRouter.scala:87:24] wire out_rimask_678 = \|_out_rimask_T_678; // @[RegisterRouter.scala:87:24] wire out_wimask_678 = &_out_wimask_T_678; // @[RegisterRouter.scala:87:24] wire out_romask_678 = \|_out_romask_T_678; // @[RegisterRouter.scala:87:24] wire out_womask_678 = &_out_womask_T_678; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_678 = out_rivalid_1_532 & out_rimask_678; // @[RegisterRouter.scala:87:24] wire _out_T_6779 = out_f_rivalid_678; // @[RegisterRouter.scala:87:24] wire out_f_roready_678 = out_roready_1_532 & out_romask_678; // @[RegisterRouter.scala:87:24] wire _out_T_6780 = out_f_roready_678; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_678 = out_wivalid_1_532 & out_wimask_678; // @[RegisterRouter.scala:87:24] wire out_f_woready_678 = out_woready_1_532 & out_womask_678; // @[RegisterRouter.scala:87:24] wire _out_T_6781 = ~out_rimask_678; // @[RegisterRouter.scala:87:24] wire _out_T_6782 = ~out_wimask_678; // @[RegisterRouter.scala:87:24] wire _out_T_6783 = ~out_romask_678; // @[RegisterRouter.scala:87:24] wire _out_T_6784 = ~out_womask_678; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_575 = {hi_310, flags_0_go, _out_prepend_T_575}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6785 = out_prepend_575; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6786 = _out_T_6785; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_576 = _out_T_6786; // @[RegisterRouter.scala:87:24] wire out_rimask_679 = \|_out_rimask_T_679; // @[RegisterRouter.scala:87:24] wire out_wimask_679 = &_out_wimask_T_679; // @[RegisterRouter.scala:87:24] wire out_romask_679 = \|_out_romask_T_679; // @[RegisterRouter.scala:87:24] wire out_womask_679 = &_out_womask_T_679; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_679 = out_rivalid_1_533 & out_rimask_679; // @[RegisterRouter.scala:87:24] wire _out_T_6788 = out_f_rivalid_679; // @[RegisterRouter.scala:87:24] wire out_f_roready_679 = out_roready_1_533 & out_romask_679; // @[RegisterRouter.scala:87:24] wire _out_T_6789 = out_f_roready_679; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_679 = out_wivalid_1_533 & out_wimask_679; // @[RegisterRouter.scala:87:24] wire out_f_woready_679 = out_woready_1_533 & out_womask_679; // @[RegisterRouter.scala:87:24] wire _out_T_6790 = ~out_rimask_679; // @[RegisterRouter.scala:87:24] wire _out_T_6791 = ~out_wimask_679; // @[RegisterRouter.scala:87:24] wire _out_T_6792 = ~out_romask_679; // @[RegisterRouter.scala:87:24] wire _out_T_6793 = ~out_womask_679; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_576 = {hi_311, flags_0_go, _out_prepend_T_576}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6794 = out_prepend_576; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6795 = _out_T_6794; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_577 = _out_T_6795; // @[RegisterRouter.scala:87:24] wire out_rimask_680 = \|_out_rimask_T_680; // @[RegisterRouter.scala:87:24] wire out_wimask_680 = &_out_wimask_T_680; // @[RegisterRouter.scala:87:24] wire out_romask_680 = \|_out_romask_T_680; // @[RegisterRouter.scala:87:24] wire out_womask_680 = &_out_womask_T_680; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_680 = out_rivalid_1_534 & out_rimask_680; // @[RegisterRouter.scala:87:24] wire _out_T_6797 = out_f_rivalid_680; // @[RegisterRouter.scala:87:24] wire out_f_roready_680 = out_roready_1_534 & out_romask_680; // @[RegisterRouter.scala:87:24] wire _out_T_6798 = out_f_roready_680; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_680 = out_wivalid_1_534 & out_wimask_680; // @[RegisterRouter.scala:87:24] wire out_f_woready_680 = out_woready_1_534 & out_womask_680; // @[RegisterRouter.scala:87:24] wire _out_T_6799 = ~out_rimask_680; // @[RegisterRouter.scala:87:24] wire _out_T_6800 = ~out_wimask_680; // @[RegisterRouter.scala:87:24] wire _out_T_6801 = ~out_romask_680; // @[RegisterRouter.scala:87:24] wire _out_T_6802 = ~out_womask_680; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_577 = {hi_312, flags_0_go, _out_prepend_T_577}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6803 = out_prepend_577; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6804 = _out_T_6803; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_166 = _out_T_6804; // @[MuxLiteral.scala:49:48] wire out_rimask_681 = \|_out_rimask_T_681; // @[RegisterRouter.scala:87:24] wire out_wimask_681 = &_out_wimask_T_681; // @[RegisterRouter.scala:87:24] wire out_romask_681 = \|_out_romask_T_681; // @[RegisterRouter.scala:87:24] wire out_womask_681 = &_out_womask_T_681; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_681 = out_rivalid_1_535 & out_rimask_681; // @[RegisterRouter.scala:87:24] wire out_f_roready_681 = out_roready_1_535 & out_romask_681; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_681 = out_wivalid_1_535 & out_wimask_681; // @[RegisterRouter.scala:87:24] wire _out_T_6806 = out_f_wivalid_681; // @[RegisterRouter.scala:87:24] assign out_f_woready_681 = out_woready_1_535 & out_womask_681; // @[RegisterRouter.scala:87:24] assign hartHaltedWrEn = out_f_woready_681; // @[RegisterRouter.scala:87:24] wire _out_T_6807 = out_f_woready_681; // @[RegisterRouter.scala:87:24] assign hartHaltedId = _out_T_6805; // @[RegisterRouter.scala:87:24] wire _out_T_6808 = ~out_rimask_681; // @[RegisterRouter.scala:87:24] wire _out_T_6809 = ~out_wimask_681; // @[RegisterRouter.scala:87:24] wire _out_T_6810 = ~out_romask_681; // @[RegisterRouter.scala:87:24] wire _out_T_6811 = ~out_womask_681; // @[RegisterRouter.scala:87:24] wire out_rimask_682 = \|_out_rimask_T_682; // @[RegisterRouter.scala:87:24] wire out_wimask_682 = &_out_wimask_T_682; // @[RegisterRouter.scala:87:24] wire out_romask_682 = \|_out_romask_T_682; // @[RegisterRouter.scala:87:24] wire out_womask_682 = &_out_womask_T_682; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_682 = out_rivalid_1_536 & out_rimask_682; // @[RegisterRouter.scala:87:24] wire out_f_roready_682 = out_roready_1_536 & out_romask_682; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_682 = out_wivalid_1_536 & out_wimask_682; // @[RegisterRouter.scala:87:24] wire _out_T_6815 = out_f_wivalid_682; // @[RegisterRouter.scala:87:24] assign out_f_woready_682 = out_woready_1_536 & out_womask_682; // @[RegisterRouter.scala:87:24] assign hartGoingWrEn = out_f_woready_682; // @[RegisterRouter.scala:87:24] wire _out_T_6816 = out_f_woready_682; // @[RegisterRouter.scala:87:24] assign hartGoingId = _out_T_6814; // @[RegisterRouter.scala:87:24] wire _out_T_6817 = ~out_rimask_682; // @[RegisterRouter.scala:87:24] wire _out_T_6818 = ~out_wimask_682; // @[RegisterRouter.scala:87:24] wire _out_T_6819 = ~out_romask_682; // @[RegisterRouter.scala:87:24] wire _out_T_6820 = ~out_womask_682; // @[RegisterRouter.scala:87:24] wire out_rimask_683 = \|_out_rimask_T_683; // @[RegisterRouter.scala:87:24] wire out_wimask_683 = &_out_wimask_T_683; // @[RegisterRouter.scala:87:24] wire out_romask_683 = \|_out_romask_T_683; // @[RegisterRouter.scala:87:24] wire out_womask_683 = &_out_womask_T_683; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_683 = out_rivalid_1_537 & out_rimask_683; // @[RegisterRouter.scala:87:24] wire _out_T_6824 = out_f_rivalid_683; // @[RegisterRouter.scala:87:24] wire out_f_roready_683 = out_roready_1_537 & out_romask_683; // @[RegisterRouter.scala:87:24] wire _out_T_6825 = out_f_roready_683; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_683 = out_wivalid_1_537 & out_wimask_683; // @[RegisterRouter.scala:87:24] wire out_f_woready_683 = out_woready_1_537 & out_womask_683; // @[RegisterRouter.scala:87:24] wire _out_T_6826 = ~out_rimask_683; // @[RegisterRouter.scala:87:24] wire _out_T_6827 = ~out_wimask_683; // @[RegisterRouter.scala:87:24] wire _out_T_6828 = ~out_romask_683; // @[RegisterRouter.scala:87:24] wire _out_T_6829 = ~out_womask_683; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6831 = _out_T_6830; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_579 = _out_T_6831; // @[RegisterRouter.scala:87:24] wire out_rimask_684 = \|_out_rimask_T_684; // @[RegisterRouter.scala:87:24] wire out_wimask_684 = &_out_wimask_T_684; // @[RegisterRouter.scala:87:24] wire out_romask_684 = \|_out_romask_T_684; // @[RegisterRouter.scala:87:24] wire out_womask_684 = &_out_womask_T_684; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_684 = out_rivalid_1_538 & out_rimask_684; // @[RegisterRouter.scala:87:24] wire _out_T_6833 = out_f_rivalid_684; // @[RegisterRouter.scala:87:24] wire out_f_roready_684 = out_roready_1_538 & out_romask_684; // @[RegisterRouter.scala:87:24] wire _out_T_6834 = out_f_roready_684; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_684 = out_wivalid_1_538 & out_wimask_684; // @[RegisterRouter.scala:87:24] wire out_f_woready_684 = out_woready_1_538 & out_womask_684; // @[RegisterRouter.scala:87:24] wire _out_T_6835 = ~out_rimask_684; // @[RegisterRouter.scala:87:24] wire _out_T_6836 = ~out_wimask_684; // @[RegisterRouter.scala:87:24] wire _out_T_6837 = ~out_romask_684; // @[RegisterRouter.scala:87:24] wire _out_T_6838 = ~out_womask_684; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_579 = {hi_162, flags_0_go, _out_prepend_T_579}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6839 = out_prepend_579; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6840 = _out_T_6839; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_580 = _out_T_6840; // @[RegisterRouter.scala:87:24] wire out_rimask_685 = \|_out_rimask_T_685; // @[RegisterRouter.scala:87:24] wire out_wimask_685 = &_out_wimask_T_685; // @[RegisterRouter.scala:87:24] wire out_romask_685 = \|_out_romask_T_685; // @[RegisterRouter.scala:87:24] wire out_womask_685 = &_out_womask_T_685; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_685 = out_rivalid_1_539 & out_rimask_685; // @[RegisterRouter.scala:87:24] wire _out_T_6842 = out_f_rivalid_685; // @[RegisterRouter.scala:87:24] wire out_f_roready_685 = out_roready_1_539 & out_romask_685; // @[RegisterRouter.scala:87:24] wire _out_T_6843 = out_f_roready_685; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_685 = out_wivalid_1_539 & out_wimask_685; // @[RegisterRouter.scala:87:24] wire out_f_woready_685 = out_woready_1_539 & out_womask_685; // @[RegisterRouter.scala:87:24] wire _out_T_6844 = ~out_rimask_685; // @[RegisterRouter.scala:87:24] wire _out_T_6845 = ~out_wimask_685; // @[RegisterRouter.scala:87:24] wire _out_T_6846 = ~out_romask_685; // @[RegisterRouter.scala:87:24] wire _out_T_6847 = ~out_womask_685; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_580 = {hi_163, flags_0_go, _out_prepend_T_580}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6848 = out_prepend_580; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6849 = _out_T_6848; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_581 = _out_T_6849; // @[RegisterRouter.scala:87:24] wire out_rimask_686 = \|_out_rimask_T_686; // @[RegisterRouter.scala:87:24] wire out_wimask_686 = &_out_wimask_T_686; // @[RegisterRouter.scala:87:24] wire out_romask_686 = \|_out_romask_T_686; // @[RegisterRouter.scala:87:24] wire out_womask_686 = &_out_womask_T_686; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_686 = out_rivalid_1_540 & out_rimask_686; // @[RegisterRouter.scala:87:24] wire _out_T_6851 = out_f_rivalid_686; // @[RegisterRouter.scala:87:24] wire out_f_roready_686 = out_roready_1_540 & out_romask_686; // @[RegisterRouter.scala:87:24] wire _out_T_6852 = out_f_roready_686; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_686 = out_wivalid_1_540 & out_wimask_686; // @[RegisterRouter.scala:87:24] wire out_f_woready_686 = out_woready_1_540 & out_womask_686; // @[RegisterRouter.scala:87:24] wire _out_T_6853 = ~out_rimask_686; // @[RegisterRouter.scala:87:24] wire _out_T_6854 = ~out_wimask_686; // @[RegisterRouter.scala:87:24] wire _out_T_6855 = ~out_romask_686; // @[RegisterRouter.scala:87:24] wire _out_T_6856 = ~out_womask_686; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_581 = {hi_164, flags_0_go, _out_prepend_T_581}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6857 = out_prepend_581; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6858 = _out_T_6857; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_582 = _out_T_6858; // @[RegisterRouter.scala:87:24] wire out_rimask_687 = \|_out_rimask_T_687; // @[RegisterRouter.scala:87:24] wire out_wimask_687 = &_out_wimask_T_687; // @[RegisterRouter.scala:87:24] wire out_romask_687 = \|_out_romask_T_687; // @[RegisterRouter.scala:87:24] wire out_womask_687 = &_out_womask_T_687; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_687 = out_rivalid_1_541 & out_rimask_687; // @[RegisterRouter.scala:87:24] wire _out_T_6860 = out_f_rivalid_687; // @[RegisterRouter.scala:87:24] wire out_f_roready_687 = out_roready_1_541 & out_romask_687; // @[RegisterRouter.scala:87:24] wire _out_T_6861 = out_f_roready_687; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_687 = out_wivalid_1_541 & out_wimask_687; // @[RegisterRouter.scala:87:24] wire out_f_woready_687 = out_woready_1_541 & out_womask_687; // @[RegisterRouter.scala:87:24] wire _out_T_6862 = ~out_rimask_687; // @[RegisterRouter.scala:87:24] wire _out_T_6863 = ~out_wimask_687; // @[RegisterRouter.scala:87:24] wire _out_T_6864 = ~out_romask_687; // @[RegisterRouter.scala:87:24] wire _out_T_6865 = ~out_womask_687; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_582 = {hi_165, flags_0_go, _out_prepend_T_582}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6866 = out_prepend_582; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6867 = _out_T_6866; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_583 = _out_T_6867; // @[RegisterRouter.scala:87:24] wire out_rimask_688 = \|_out_rimask_T_688; // @[RegisterRouter.scala:87:24] wire out_wimask_688 = &_out_wimask_T_688; // @[RegisterRouter.scala:87:24] wire out_romask_688 = \|_out_romask_T_688; // @[RegisterRouter.scala:87:24] wire out_womask_688 = &_out_womask_T_688; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_688 = out_rivalid_1_542 & out_rimask_688; // @[RegisterRouter.scala:87:24] wire _out_T_6869 = out_f_rivalid_688; // @[RegisterRouter.scala:87:24] wire out_f_roready_688 = out_roready_1_542 & out_romask_688; // @[RegisterRouter.scala:87:24] wire _out_T_6870 = out_f_roready_688; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_688 = out_wivalid_1_542 & out_wimask_688; // @[RegisterRouter.scala:87:24] wire out_f_woready_688 = out_woready_1_542 & out_womask_688; // @[RegisterRouter.scala:87:24] wire _out_T_6871 = ~out_rimask_688; // @[RegisterRouter.scala:87:24] wire _out_T_6872 = ~out_wimask_688; // @[RegisterRouter.scala:87:24] wire _out_T_6873 = ~out_romask_688; // @[RegisterRouter.scala:87:24] wire _out_T_6874 = ~out_womask_688; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_583 = {hi_166, flags_0_go, _out_prepend_T_583}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6875 = out_prepend_583; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6876 = _out_T_6875; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_584 = _out_T_6876; // @[RegisterRouter.scala:87:24] wire out_rimask_689 = \|_out_rimask_T_689; // @[RegisterRouter.scala:87:24] wire out_wimask_689 = &_out_wimask_T_689; // @[RegisterRouter.scala:87:24] wire out_romask_689 = \|_out_romask_T_689; // @[RegisterRouter.scala:87:24] wire out_womask_689 = &_out_womask_T_689; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_689 = out_rivalid_1_543 & out_rimask_689; // @[RegisterRouter.scala:87:24] wire _out_T_6878 = out_f_rivalid_689; // @[RegisterRouter.scala:87:24] wire out_f_roready_689 = out_roready_1_543 & out_romask_689; // @[RegisterRouter.scala:87:24] wire _out_T_6879 = out_f_roready_689; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_689 = out_wivalid_1_543 & out_wimask_689; // @[RegisterRouter.scala:87:24] wire out_f_woready_689 = out_woready_1_543 & out_womask_689; // @[RegisterRouter.scala:87:24] wire _out_T_6880 = ~out_rimask_689; // @[RegisterRouter.scala:87:24] wire _out_T_6881 = ~out_wimask_689; // @[RegisterRouter.scala:87:24] wire _out_T_6882 = ~out_romask_689; // @[RegisterRouter.scala:87:24] wire _out_T_6883 = ~out_womask_689; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_584 = {hi_167, flags_0_go, _out_prepend_T_584}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6884 = out_prepend_584; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6885 = _out_T_6884; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_585 = _out_T_6885; // @[RegisterRouter.scala:87:24] wire out_rimask_690 = \|_out_rimask_T_690; // @[RegisterRouter.scala:87:24] wire out_wimask_690 = &_out_wimask_T_690; // @[RegisterRouter.scala:87:24] wire out_romask_690 = \|_out_romask_T_690; // @[RegisterRouter.scala:87:24] wire out_womask_690 = &_out_womask_T_690; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_690 = out_rivalid_1_544 & out_rimask_690; // @[RegisterRouter.scala:87:24] wire _out_T_6887 = out_f_rivalid_690; // @[RegisterRouter.scala:87:24] wire out_f_roready_690 = out_roready_1_544 & out_romask_690; // @[RegisterRouter.scala:87:24] wire _out_T_6888 = out_f_roready_690; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_690 = out_wivalid_1_544 & out_wimask_690; // @[RegisterRouter.scala:87:24] wire out_f_woready_690 = out_woready_1_544 & out_womask_690; // @[RegisterRouter.scala:87:24] wire _out_T_6889 = ~out_rimask_690; // @[RegisterRouter.scala:87:24] wire _out_T_6890 = ~out_wimask_690; // @[RegisterRouter.scala:87:24] wire _out_T_6891 = ~out_romask_690; // @[RegisterRouter.scala:87:24] wire _out_T_6892 = ~out_womask_690; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_585 = {hi_168, flags_0_go, _out_prepend_T_585}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6893 = out_prepend_585; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6894 = _out_T_6893; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_148 = _out_T_6894; // @[MuxLiteral.scala:49:48] wire out_rimask_691 = \|_out_rimask_T_691; // @[RegisterRouter.scala:87:24] wire out_wimask_691 = &_out_wimask_T_691; // @[RegisterRouter.scala:87:24] wire out_romask_691 = \|_out_romask_T_691; // @[RegisterRouter.scala:87:24] wire out_womask_691 = &_out_womask_T_691; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_691 = out_rivalid_1_545 & out_rimask_691; // @[RegisterRouter.scala:87:24] wire _out_T_6896 = out_f_rivalid_691; // @[RegisterRouter.scala:87:24] wire out_f_roready_691 = out_roready_1_545 & out_romask_691; // @[RegisterRouter.scala:87:24] wire _out_T_6897 = out_f_roready_691; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_691 = out_wivalid_1_545 & out_wimask_691; // @[RegisterRouter.scala:87:24] wire out_f_woready_691 = out_woready_1_545 & out_womask_691; // @[RegisterRouter.scala:87:24] wire _out_T_6898 = ~out_rimask_691; // @[RegisterRouter.scala:87:24] wire _out_T_6899 = ~out_wimask_691; // @[RegisterRouter.scala:87:24] wire _out_T_6900 = ~out_romask_691; // @[RegisterRouter.scala:87:24] wire _out_T_6901 = ~out_womask_691; // @[RegisterRouter.scala:87:24] wire out_rimask_692 = \|_out_rimask_T_692; // @[RegisterRouter.scala:87:24] wire out_wimask_692 = &_out_wimask_T_692; // @[RegisterRouter.scala:87:24] wire out_romask_692 = \|_out_romask_T_692; // @[RegisterRouter.scala:87:24] wire out_womask_692 = &_out_womask_T_692; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_692 = out_rivalid_1_546 & out_rimask_692; // @[RegisterRouter.scala:87:24] wire _out_T_6905 = out_f_rivalid_692; // @[RegisterRouter.scala:87:24] wire out_f_roready_692 = out_roready_1_546 & out_romask_692; // @[RegisterRouter.scala:87:24] wire _out_T_6906 = out_f_roready_692; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_692 = out_wivalid_1_546 & out_wimask_692; // @[RegisterRouter.scala:87:24] wire out_f_woready_692 = out_woready_1_546 & out_womask_692; // @[RegisterRouter.scala:87:24] wire _out_T_6907 = ~out_rimask_692; // @[RegisterRouter.scala:87:24] wire _out_T_6908 = ~out_wimask_692; // @[RegisterRouter.scala:87:24] wire _out_T_6909 = ~out_romask_692; // @[RegisterRouter.scala:87:24] wire _out_T_6910 = ~out_womask_692; // @[RegisterRouter.scala:87:24] wire out_rimask_693 = \|_out_rimask_T_693; // @[RegisterRouter.scala:87:24] wire out_wimask_693 = &_out_wimask_T_693; // @[RegisterRouter.scala:87:24] wire out_romask_693 = \|_out_romask_T_693; // @[RegisterRouter.scala:87:24] wire out_womask_693 = &_out_womask_T_693; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_693 = out_rivalid_1_547 & out_rimask_693; // @[RegisterRouter.scala:87:24] wire _out_T_6914 = out_f_rivalid_693; // @[RegisterRouter.scala:87:24] wire out_f_roready_693 = out_roready_1_547 & out_romask_693; // @[RegisterRouter.scala:87:24] wire _out_T_6915 = out_f_roready_693; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_693 = out_wivalid_1_547 & out_wimask_693; // @[RegisterRouter.scala:87:24] wire out_f_woready_693 = out_woready_1_547 & out_womask_693; // @[RegisterRouter.scala:87:24] wire _out_T_6916 = ~out_rimask_693; // @[RegisterRouter.scala:87:24] wire _out_T_6917 = ~out_wimask_693; // @[RegisterRouter.scala:87:24] wire _out_T_6918 = ~out_romask_693; // @[RegisterRouter.scala:87:24] wire _out_T_6919 = ~out_womask_693; // @[RegisterRouter.scala:87:24] wire out_rimask_694 = \|_out_rimask_T_694; // @[RegisterRouter.scala:87:24] wire out_wimask_694 = &_out_wimask_T_694; // @[RegisterRouter.scala:87:24] wire out_romask_694 = \|_out_romask_T_694; // @[RegisterRouter.scala:87:24] wire out_womask_694 = &_out_womask_T_694; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_694 = out_rivalid_1_548 & out_rimask_694; // @[RegisterRouter.scala:87:24] wire _out_T_6923 = out_f_rivalid_694; // @[RegisterRouter.scala:87:24] wire out_f_roready_694 = out_roready_1_548 & out_romask_694; // @[RegisterRouter.scala:87:24] wire _out_T_6924 = out_f_roready_694; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_694 = out_wivalid_1_548 & out_wimask_694; // @[RegisterRouter.scala:87:24] wire out_f_woready_694 = out_woready_1_548 & out_womask_694; // @[RegisterRouter.scala:87:24] wire _out_T_6925 = ~out_rimask_694; // @[RegisterRouter.scala:87:24] wire _out_T_6926 = ~out_wimask_694; // @[RegisterRouter.scala:87:24] wire _out_T_6927 = ~out_romask_694; // @[RegisterRouter.scala:87:24] wire _out_T_6928 = ~out_womask_694; // @[RegisterRouter.scala:87:24] wire out_rimask_695 = \|_out_rimask_T_695; // @[RegisterRouter.scala:87:24] wire out_wimask_695 = &_out_wimask_T_695; // @[RegisterRouter.scala:87:24] wire out_romask_695 = \|_out_romask_T_695; // @[RegisterRouter.scala:87:24] wire out_womask_695 = &_out_womask_T_695; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_695 = out_rivalid_1_549 & out_rimask_695; // @[RegisterRouter.scala:87:24] wire _out_T_6932 = out_f_rivalid_695; // @[RegisterRouter.scala:87:24] wire out_f_roready_695 = out_roready_1_549 & out_romask_695; // @[RegisterRouter.scala:87:24] wire _out_T_6933 = out_f_roready_695; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_695 = out_wivalid_1_549 & out_wimask_695; // @[RegisterRouter.scala:87:24] wire out_f_woready_695 = out_woready_1_549 & out_womask_695; // @[RegisterRouter.scala:87:24] wire _out_T_6934 = ~out_rimask_695; // @[RegisterRouter.scala:87:24] wire _out_T_6935 = ~out_wimask_695; // @[RegisterRouter.scala:87:24] wire _out_T_6936 = ~out_romask_695; // @[RegisterRouter.scala:87:24] wire _out_T_6937 = ~out_womask_695; // @[RegisterRouter.scala:87:24] wire out_rimask_696 = \|_out_rimask_T_696; // @[RegisterRouter.scala:87:24] wire out_wimask_696 = &_out_wimask_T_696; // @[RegisterRouter.scala:87:24] wire out_romask_696 = \|_out_romask_T_696; // @[RegisterRouter.scala:87:24] wire out_womask_696 = &_out_womask_T_696; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_696 = out_rivalid_1_550 & out_rimask_696; // @[RegisterRouter.scala:87:24] wire _out_T_6941 = out_f_rivalid_696; // @[RegisterRouter.scala:87:24] wire out_f_roready_696 = out_roready_1_550 & out_romask_696; // @[RegisterRouter.scala:87:24] wire _out_T_6942 = out_f_roready_696; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_696 = out_wivalid_1_550 & out_wimask_696; // @[RegisterRouter.scala:87:24] wire out_f_woready_696 = out_woready_1_550 & out_womask_696; // @[RegisterRouter.scala:87:24] wire _out_T_6943 = ~out_rimask_696; // @[RegisterRouter.scala:87:24] wire _out_T_6944 = ~out_wimask_696; // @[RegisterRouter.scala:87:24] wire _out_T_6945 = ~out_romask_696; // @[RegisterRouter.scala:87:24] wire _out_T_6946 = ~out_womask_696; // @[RegisterRouter.scala:87:24] wire out_rimask_697 = \|_out_rimask_T_697; // @[RegisterRouter.scala:87:24] wire out_wimask_697 = &_out_wimask_T_697; // @[RegisterRouter.scala:87:24] wire out_romask_697 = \|_out_romask_T_697; // @[RegisterRouter.scala:87:24] wire out_womask_697 = &_out_womask_T_697; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_697 = out_rivalid_1_551 & out_rimask_697; // @[RegisterRouter.scala:87:24] wire _out_T_6950 = out_f_rivalid_697; // @[RegisterRouter.scala:87:24] wire out_f_roready_697 = out_roready_1_551 & out_romask_697; // @[RegisterRouter.scala:87:24] wire _out_T_6951 = out_f_roready_697; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_697 = out_wivalid_1_551 & out_wimask_697; // @[RegisterRouter.scala:87:24] wire out_f_woready_697 = out_woready_1_551 & out_womask_697; // @[RegisterRouter.scala:87:24] wire _out_T_6952 = ~out_rimask_697; // @[RegisterRouter.scala:87:24] wire _out_T_6953 = ~out_wimask_697; // @[RegisterRouter.scala:87:24] wire _out_T_6954 = ~out_romask_697; // @[RegisterRouter.scala:87:24] wire _out_T_6955 = ~out_womask_697; // @[RegisterRouter.scala:87:24] wire out_rimask_698 = \|_out_rimask_T_698; // @[RegisterRouter.scala:87:24] wire out_wimask_698 = &_out_wimask_T_698; // @[RegisterRouter.scala:87:24] wire out_romask_698 = \|_out_romask_T_698; // @[RegisterRouter.scala:87:24] wire out_womask_698 = &_out_womask_T_698; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_698 = out_rivalid_1_552 & out_rimask_698; // @[RegisterRouter.scala:87:24] wire _out_T_6959 = out_f_rivalid_698; // @[RegisterRouter.scala:87:24] wire out_f_roready_698 = out_roready_1_552 & out_romask_698; // @[RegisterRouter.scala:87:24] wire _out_T_6960 = out_f_roready_698; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_698 = out_wivalid_1_552 & out_wimask_698; // @[RegisterRouter.scala:87:24] wire out_f_woready_698 = out_woready_1_552 & out_womask_698; // @[RegisterRouter.scala:87:24] wire _out_T_6961 = ~out_rimask_698; // @[RegisterRouter.scala:87:24] wire _out_T_6962 = ~out_wimask_698; // @[RegisterRouter.scala:87:24] wire _out_T_6963 = ~out_romask_698; // @[RegisterRouter.scala:87:24] wire _out_T_6964 = ~out_womask_698; // @[RegisterRouter.scala:87:24] wire out_rimask_699 = \|_out_rimask_T_699; // @[RegisterRouter.scala:87:24] wire out_wimask_699 = &_out_wimask_T_699; // @[RegisterRouter.scala:87:24] wire out_romask_699 = \|_out_romask_T_699; // @[RegisterRouter.scala:87:24] wire out_womask_699 = &_out_womask_T_699; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_699 = out_rivalid_1_553 & out_rimask_699; // @[RegisterRouter.scala:87:24] wire _out_T_6968 = out_f_rivalid_699; // @[RegisterRouter.scala:87:24] wire out_f_roready_699 = out_roready_1_553 & out_romask_699; // @[RegisterRouter.scala:87:24] wire _out_T_6969 = out_f_roready_699; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_699 = out_wivalid_1_553 & out_wimask_699; // @[RegisterRouter.scala:87:24] wire out_f_woready_699 = out_woready_1_553 & out_womask_699; // @[RegisterRouter.scala:87:24] wire _out_T_6970 = ~out_rimask_699; // @[RegisterRouter.scala:87:24] wire _out_T_6971 = ~out_wimask_699; // @[RegisterRouter.scala:87:24] wire _out_T_6972 = ~out_romask_699; // @[RegisterRouter.scala:87:24] wire _out_T_6973 = ~out_womask_699; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6975 = _out_T_6974; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_593 = _out_T_6975; // @[RegisterRouter.scala:87:24] wire out_rimask_700 = \|_out_rimask_T_700; // @[RegisterRouter.scala:87:24] wire out_wimask_700 = &_out_wimask_T_700; // @[RegisterRouter.scala:87:24] wire out_romask_700 = \|_out_romask_T_700; // @[RegisterRouter.scala:87:24] wire out_womask_700 = &_out_womask_T_700; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_700 = out_rivalid_1_554 & out_rimask_700; // @[RegisterRouter.scala:87:24] wire _out_T_6977 = out_f_rivalid_700; // @[RegisterRouter.scala:87:24] wire out_f_roready_700 = out_roready_1_554 & out_romask_700; // @[RegisterRouter.scala:87:24] wire _out_T_6978 = out_f_roready_700; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_700 = out_wivalid_1_554 & out_wimask_700; // @[RegisterRouter.scala:87:24] wire out_f_woready_700 = out_woready_1_554 & out_womask_700; // @[RegisterRouter.scala:87:24] wire _out_T_6979 = ~out_rimask_700; // @[RegisterRouter.scala:87:24] wire _out_T_6980 = ~out_wimask_700; // @[RegisterRouter.scala:87:24] wire _out_T_6981 = ~out_romask_700; // @[RegisterRouter.scala:87:24] wire _out_T_6982 = ~out_womask_700; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_593 = {hi_266, flags_0_go, _out_prepend_T_593}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6983 = out_prepend_593; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6984 = _out_T_6983; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_594 = _out_T_6984; // @[RegisterRouter.scala:87:24] wire out_rimask_701 = \|_out_rimask_T_701; // @[RegisterRouter.scala:87:24] wire out_wimask_701 = &_out_wimask_T_701; // @[RegisterRouter.scala:87:24] wire out_romask_701 = \|_out_romask_T_701; // @[RegisterRouter.scala:87:24] wire out_womask_701 = &_out_womask_T_701; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_701 = out_rivalid_1_555 & out_rimask_701; // @[RegisterRouter.scala:87:24] wire _out_T_6986 = out_f_rivalid_701; // @[RegisterRouter.scala:87:24] wire out_f_roready_701 = out_roready_1_555 & out_romask_701; // @[RegisterRouter.scala:87:24] wire _out_T_6987 = out_f_roready_701; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_701 = out_wivalid_1_555 & out_wimask_701; // @[RegisterRouter.scala:87:24] wire out_f_woready_701 = out_woready_1_555 & out_womask_701; // @[RegisterRouter.scala:87:24] wire _out_T_6988 = ~out_rimask_701; // @[RegisterRouter.scala:87:24] wire _out_T_6989 = ~out_wimask_701; // @[RegisterRouter.scala:87:24] wire _out_T_6990 = ~out_romask_701; // @[RegisterRouter.scala:87:24] wire _out_T_6991 = ~out_womask_701; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_594 = {hi_267, flags_0_go, _out_prepend_T_594}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6992 = out_prepend_594; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6993 = _out_T_6992; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_595 = _out_T_6993; // @[RegisterRouter.scala:87:24] wire out_rimask_702 = \|_out_rimask_T_702; // @[RegisterRouter.scala:87:24] wire out_wimask_702 = &_out_wimask_T_702; // @[RegisterRouter.scala:87:24] wire out_romask_702 = \|_out_romask_T_702; // @[RegisterRouter.scala:87:24] wire out_womask_702 = &_out_womask_T_702; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_702 = out_rivalid_1_556 & out_rimask_702; // @[RegisterRouter.scala:87:24] wire _out_T_6995 = out_f_rivalid_702; // @[RegisterRouter.scala:87:24] wire out_f_roready_702 = out_roready_1_556 & out_romask_702; // @[RegisterRouter.scala:87:24] wire _out_T_6996 = out_f_roready_702; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_702 = out_wivalid_1_556 & out_wimask_702; // @[RegisterRouter.scala:87:24] wire out_f_woready_702 = out_woready_1_556 & out_womask_702; // @[RegisterRouter.scala:87:24] wire _out_T_6997 = ~out_rimask_702; // @[RegisterRouter.scala:87:24] wire _out_T_6998 = ~out_wimask_702; // @[RegisterRouter.scala:87:24] wire _out_T_6999 = ~out_romask_702; // @[RegisterRouter.scala:87:24] wire _out_T_7000 = ~out_womask_702; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_595 = {hi_268, flags_0_go, _out_prepend_T_595}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7001 = out_prepend_595; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7002 = _out_T_7001; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_596 = _out_T_7002; // @[RegisterRouter.scala:87:24] wire out_rimask_703 = \|_out_rimask_T_703; // @[RegisterRouter.scala:87:24] wire out_wimask_703 = &_out_wimask_T_703; // @[RegisterRouter.scala:87:24] wire out_romask_703 = \|_out_romask_T_703; // @[RegisterRouter.scala:87:24] wire out_womask_703 = &_out_womask_T_703; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_703 = out_rivalid_1_557 & out_rimask_703; // @[RegisterRouter.scala:87:24] wire _out_T_7004 = out_f_rivalid_703; // @[RegisterRouter.scala:87:24] wire out_f_roready_703 = out_roready_1_557 & out_romask_703; // @[RegisterRouter.scala:87:24] wire _out_T_7005 = out_f_roready_703; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_703 = out_wivalid_1_557 & out_wimask_703; // @[RegisterRouter.scala:87:24] wire out_f_woready_703 = out_woready_1_557 & out_womask_703; // @[RegisterRouter.scala:87:24] wire _out_T_7006 = ~out_rimask_703; // @[RegisterRouter.scala:87:24] wire _out_T_7007 = ~out_wimask_703; // @[RegisterRouter.scala:87:24] wire _out_T_7008 = ~out_romask_703; // @[RegisterRouter.scala:87:24] wire _out_T_7009 = ~out_womask_703; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_596 = {hi_269, flags_0_go, _out_prepend_T_596}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7010 = out_prepend_596; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7011 = _out_T_7010; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_597 = _out_T_7011; // @[RegisterRouter.scala:87:24] wire out_rimask_704 = \|_out_rimask_T_704; // @[RegisterRouter.scala:87:24] wire out_wimask_704 = &_out_wimask_T_704; // @[RegisterRouter.scala:87:24] wire out_romask_704 = \|_out_romask_T_704; // @[RegisterRouter.scala:87:24] wire out_womask_704 = &_out_womask_T_704; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_704 = out_rivalid_1_558 & out_rimask_704; // @[RegisterRouter.scala:87:24] wire _out_T_7013 = out_f_rivalid_704; // @[RegisterRouter.scala:87:24] wire out_f_roready_704 = out_roready_1_558 & out_romask_704; // @[RegisterRouter.scala:87:24] wire _out_T_7014 = out_f_roready_704; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_704 = out_wivalid_1_558 & out_wimask_704; // @[RegisterRouter.scala:87:24] wire out_f_woready_704 = out_woready_1_558 & out_womask_704; // @[RegisterRouter.scala:87:24] wire _out_T_7015 = ~out_rimask_704; // @[RegisterRouter.scala:87:24] wire _out_T_7016 = ~out_wimask_704; // @[RegisterRouter.scala:87:24] wire _out_T_7017 = ~out_romask_704; // @[RegisterRouter.scala:87:24] wire _out_T_7018 = ~out_womask_704; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_597 = {hi_270, flags_0_go, _out_prepend_T_597}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7019 = out_prepend_597; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7020 = _out_T_7019; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_598 = _out_T_7020; // @[RegisterRouter.scala:87:24] wire out_rimask_705 = \|_out_rimask_T_705; // @[RegisterRouter.scala:87:24] wire out_wimask_705 = &_out_wimask_T_705; // @[RegisterRouter.scala:87:24] wire out_romask_705 = \|_out_romask_T_705; // @[RegisterRouter.scala:87:24] wire out_womask_705 = &_out_womask_T_705; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_705 = out_rivalid_1_559 & out_rimask_705; // @[RegisterRouter.scala:87:24] wire _out_T_7022 = out_f_rivalid_705; // @[RegisterRouter.scala:87:24] wire out_f_roready_705 = out_roready_1_559 & out_romask_705; // @[RegisterRouter.scala:87:24] wire _out_T_7023 = out_f_roready_705; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_705 = out_wivalid_1_559 & out_wimask_705; // @[RegisterRouter.scala:87:24] wire out_f_woready_705 = out_woready_1_559 & out_womask_705; // @[RegisterRouter.scala:87:24] wire _out_T_7024 = ~out_rimask_705; // @[RegisterRouter.scala:87:24] wire _out_T_7025 = ~out_wimask_705; // @[RegisterRouter.scala:87:24] wire _out_T_7026 = ~out_romask_705; // @[RegisterRouter.scala:87:24] wire _out_T_7027 = ~out_womask_705; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_598 = {hi_271, flags_0_go, _out_prepend_T_598}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7028 = out_prepend_598; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7029 = _out_T_7028; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_599 = _out_T_7029; // @[RegisterRouter.scala:87:24] wire out_rimask_706 = \|_out_rimask_T_706; // @[RegisterRouter.scala:87:24] wire out_wimask_706 = &_out_wimask_T_706; // @[RegisterRouter.scala:87:24] wire out_romask_706 = \|_out_romask_T_706; // @[RegisterRouter.scala:87:24] wire out_womask_706 = &_out_womask_T_706; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_706 = out_rivalid_1_560 & out_rimask_706; // @[RegisterRouter.scala:87:24] wire _out_T_7031 = out_f_rivalid_706; // @[RegisterRouter.scala:87:24] wire out_f_roready_706 = out_roready_1_560 & out_romask_706; // @[RegisterRouter.scala:87:24] wire _out_T_7032 = out_f_roready_706; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_706 = out_wivalid_1_560 & out_wimask_706; // @[RegisterRouter.scala:87:24] wire out_f_woready_706 = out_woready_1_560 & out_womask_706; // @[RegisterRouter.scala:87:24] wire _out_T_7033 = ~out_rimask_706; // @[RegisterRouter.scala:87:24] wire _out_T_7034 = ~out_wimask_706; // @[RegisterRouter.scala:87:24] wire _out_T_7035 = ~out_romask_706; // @[RegisterRouter.scala:87:24] wire _out_T_7036 = ~out_womask_706; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_599 = {hi_272, flags_0_go, _out_prepend_T_599}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7037 = out_prepend_599; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7038 = _out_T_7037; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_161 = _out_T_7038; // @[MuxLiteral.scala:49:48] wire out_rimask_707 = \|_out_rimask_T_707; // @[RegisterRouter.scala:87:24] wire out_wimask_707 = &_out_wimask_T_707; // @[RegisterRouter.scala:87:24] wire out_romask_707 = \|_out_romask_T_707; // @[RegisterRouter.scala:87:24] wire out_womask_707 = &_out_womask_T_707; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_707 = out_rivalid_1_561 & out_rimask_707; // @[RegisterRouter.scala:87:24] wire _out_T_7040 = out_f_rivalid_707; // @[RegisterRouter.scala:87:24] wire out_f_roready_707 = out_roready_1_561 & out_romask_707; // @[RegisterRouter.scala:87:24] wire _out_T_7041 = out_f_roready_707; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_707 = out_wivalid_1_561 & out_wimask_707; // @[RegisterRouter.scala:87:24] wire out_f_woready_707 = out_woready_1_561 & out_womask_707; // @[RegisterRouter.scala:87:24] wire _out_T_7042 = ~out_rimask_707; // @[RegisterRouter.scala:87:24] wire _out_T_7043 = ~out_wimask_707; // @[RegisterRouter.scala:87:24] wire _out_T_7044 = ~out_romask_707; // @[RegisterRouter.scala:87:24] wire _out_T_7045 = ~out_womask_707; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7047 = _out_T_7046; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_600 = _out_T_7047; // @[RegisterRouter.scala:87:24] wire out_rimask_708 = \|_out_rimask_T_708; // @[RegisterRouter.scala:87:24] wire out_wimask_708 = &_out_wimask_T_708; // @[RegisterRouter.scala:87:24] wire out_romask_708 = \|_out_romask_T_708; // @[RegisterRouter.scala:87:24] wire out_womask_708 = &_out_womask_T_708; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_708 = out_rivalid_1_562 & out_rimask_708; // @[RegisterRouter.scala:87:24] wire _out_T_7049 = out_f_rivalid_708; // @[RegisterRouter.scala:87:24] wire out_f_roready_708 = out_roready_1_562 & out_romask_708; // @[RegisterRouter.scala:87:24] wire _out_T_7050 = out_f_roready_708; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_708 = out_wivalid_1_562 & out_wimask_708; // @[RegisterRouter.scala:87:24] wire out_f_woready_708 = out_woready_1_562 & out_womask_708; // @[RegisterRouter.scala:87:24] wire _out_T_7051 = ~out_rimask_708; // @[RegisterRouter.scala:87:24] wire _out_T_7052 = ~out_wimask_708; // @[RegisterRouter.scala:87:24] wire _out_T_7053 = ~out_romask_708; // @[RegisterRouter.scala:87:24] wire _out_T_7054 = ~out_womask_708; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_600 = {hi_418, flags_0_go, _out_prepend_T_600}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7055 = out_prepend_600; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7056 = _out_T_7055; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_601 = _out_T_7056; // @[RegisterRouter.scala:87:24] wire out_rimask_709 = \|_out_rimask_T_709; // @[RegisterRouter.scala:87:24] wire out_wimask_709 = &_out_wimask_T_709; // @[RegisterRouter.scala:87:24] wire out_romask_709 = \|_out_romask_T_709; // @[RegisterRouter.scala:87:24] wire out_womask_709 = &_out_womask_T_709; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_709 = out_rivalid_1_563 & out_rimask_709; // @[RegisterRouter.scala:87:24] wire _out_T_7058 = out_f_rivalid_709; // @[RegisterRouter.scala:87:24] wire out_f_roready_709 = out_roready_1_563 & out_romask_709; // @[RegisterRouter.scala:87:24] wire _out_T_7059 = out_f_roready_709; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_709 = out_wivalid_1_563 & out_wimask_709; // @[RegisterRouter.scala:87:24] wire out_f_woready_709 = out_woready_1_563 & out_womask_709; // @[RegisterRouter.scala:87:24] wire _out_T_7060 = ~out_rimask_709; // @[RegisterRouter.scala:87:24] wire _out_T_7061 = ~out_wimask_709; // @[RegisterRouter.scala:87:24] wire _out_T_7062 = ~out_romask_709; // @[RegisterRouter.scala:87:24] wire _out_T_7063 = ~out_womask_709; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_601 = {hi_419, flags_0_go, _out_prepend_T_601}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7064 = out_prepend_601; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7065 = _out_T_7064; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_602 = _out_T_7065; // @[RegisterRouter.scala:87:24] wire out_rimask_710 = \|_out_rimask_T_710; // @[RegisterRouter.scala:87:24] wire out_wimask_710 = &_out_wimask_T_710; // @[RegisterRouter.scala:87:24] wire out_romask_710 = \|_out_romask_T_710; // @[RegisterRouter.scala:87:24] wire out_womask_710 = &_out_womask_T_710; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_710 = out_rivalid_1_564 & out_rimask_710; // @[RegisterRouter.scala:87:24] wire _out_T_7067 = out_f_rivalid_710; // @[RegisterRouter.scala:87:24] wire out_f_roready_710 = out_roready_1_564 & out_romask_710; // @[RegisterRouter.scala:87:24] wire _out_T_7068 = out_f_roready_710; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_710 = out_wivalid_1_564 & out_wimask_710; // @[RegisterRouter.scala:87:24] wire out_f_woready_710 = out_woready_1_564 & out_womask_710; // @[RegisterRouter.scala:87:24] wire _out_T_7069 = ~out_rimask_710; // @[RegisterRouter.scala:87:24] wire _out_T_7070 = ~out_wimask_710; // @[RegisterRouter.scala:87:24] wire _out_T_7071 = ~out_romask_710; // @[RegisterRouter.scala:87:24] wire _out_T_7072 = ~out_womask_710; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_602 = {hi_420, flags_0_go, _out_prepend_T_602}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7073 = out_prepend_602; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7074 = _out_T_7073; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_603 = _out_T_7074; // @[RegisterRouter.scala:87:24] wire out_rimask_711 = \|_out_rimask_T_711; // @[RegisterRouter.scala:87:24] wire out_wimask_711 = &_out_wimask_T_711; // @[RegisterRouter.scala:87:24] wire out_romask_711 = \|_out_romask_T_711; // @[RegisterRouter.scala:87:24] wire out_womask_711 = &_out_womask_T_711; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_711 = out_rivalid_1_565 & out_rimask_711; // @[RegisterRouter.scala:87:24] wire _out_T_7076 = out_f_rivalid_711; // @[RegisterRouter.scala:87:24] wire out_f_roready_711 = out_roready_1_565 & out_romask_711; // @[RegisterRouter.scala:87:24] wire _out_T_7077 = out_f_roready_711; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_711 = out_wivalid_1_565 & out_wimask_711; // @[RegisterRouter.scala:87:24] wire out_f_woready_711 = out_woready_1_565 & out_womask_711; // @[RegisterRouter.scala:87:24] wire _out_T_7078 = ~out_rimask_711; // @[RegisterRouter.scala:87:24] wire _out_T_7079 = ~out_wimask_711; // @[RegisterRouter.scala:87:24] wire _out_T_7080 = ~out_romask_711; // @[RegisterRouter.scala:87:24] wire _out_T_7081 = ~out_womask_711; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_603 = {hi_421, flags_0_go, _out_prepend_T_603}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7082 = out_prepend_603; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7083 = _out_T_7082; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_604 = _out_T_7083; // @[RegisterRouter.scala:87:24] wire out_rimask_712 = \|_out_rimask_T_712; // @[RegisterRouter.scala:87:24] wire out_wimask_712 = &_out_wimask_T_712; // @[RegisterRouter.scala:87:24] wire out_romask_712 = \|_out_romask_T_712; // @[RegisterRouter.scala:87:24] wire out_womask_712 = &_out_womask_T_712; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_712 = out_rivalid_1_566 & out_rimask_712; // @[RegisterRouter.scala:87:24] wire _out_T_7085 = out_f_rivalid_712; // @[RegisterRouter.scala:87:24] wire out_f_roready_712 = out_roready_1_566 & out_romask_712; // @[RegisterRouter.scala:87:24] wire _out_T_7086 = out_f_roready_712; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_712 = out_wivalid_1_566 & out_wimask_712; // @[RegisterRouter.scala:87:24] wire out_f_woready_712 = out_woready_1_566 & out_womask_712; // @[RegisterRouter.scala:87:24] wire _out_T_7087 = ~out_rimask_712; // @[RegisterRouter.scala:87:24] wire _out_T_7088 = ~out_wimask_712; // @[RegisterRouter.scala:87:24] wire _out_T_7089 = ~out_romask_712; // @[RegisterRouter.scala:87:24] wire _out_T_7090 = ~out_womask_712; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_604 = {hi_422, flags_0_go, _out_prepend_T_604}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7091 = out_prepend_604; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7092 = _out_T_7091; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_605 = _out_T_7092; // @[RegisterRouter.scala:87:24] wire out_rimask_713 = \|_out_rimask_T_713; // @[RegisterRouter.scala:87:24] wire out_wimask_713 = &_out_wimask_T_713; // @[RegisterRouter.scala:87:24] wire out_romask_713 = \|_out_romask_T_713; // @[RegisterRouter.scala:87:24] wire out_womask_713 = &_out_womask_T_713; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_713 = out_rivalid_1_567 & out_rimask_713; // @[RegisterRouter.scala:87:24] wire _out_T_7094 = out_f_rivalid_713; // @[RegisterRouter.scala:87:24] wire out_f_roready_713 = out_roready_1_567 & out_romask_713; // @[RegisterRouter.scala:87:24] wire _out_T_7095 = out_f_roready_713; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_713 = out_wivalid_1_567 & out_wimask_713; // @[RegisterRouter.scala:87:24] wire out_f_woready_713 = out_woready_1_567 & out_womask_713; // @[RegisterRouter.scala:87:24] wire _out_T_7096 = ~out_rimask_713; // @[RegisterRouter.scala:87:24] wire _out_T_7097 = ~out_wimask_713; // @[RegisterRouter.scala:87:24] wire _out_T_7098 = ~out_romask_713; // @[RegisterRouter.scala:87:24] wire _out_T_7099 = ~out_womask_713; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_605 = {hi_423, flags_0_go, _out_prepend_T_605}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7100 = out_prepend_605; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7101 = _out_T_7100; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_606 = _out_T_7101; // @[RegisterRouter.scala:87:24] wire out_rimask_714 = \|_out_rimask_T_714; // @[RegisterRouter.scala:87:24] wire out_wimask_714 = &_out_wimask_T_714; // @[RegisterRouter.scala:87:24] wire out_romask_714 = \|_out_romask_T_714; // @[RegisterRouter.scala:87:24] wire out_womask_714 = &_out_womask_T_714; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_714 = out_rivalid_1_568 & out_rimask_714; // @[RegisterRouter.scala:87:24] wire _out_T_7103 = out_f_rivalid_714; // @[RegisterRouter.scala:87:24] wire out_f_roready_714 = out_roready_1_568 & out_romask_714; // @[RegisterRouter.scala:87:24] wire _out_T_7104 = out_f_roready_714; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_714 = out_wivalid_1_568 & out_wimask_714; // @[RegisterRouter.scala:87:24] wire out_f_woready_714 = out_woready_1_568 & out_womask_714; // @[RegisterRouter.scala:87:24] wire _out_T_7105 = ~out_rimask_714; // @[RegisterRouter.scala:87:24] wire _out_T_7106 = ~out_wimask_714; // @[RegisterRouter.scala:87:24] wire _out_T_7107 = ~out_romask_714; // @[RegisterRouter.scala:87:24] wire _out_T_7108 = ~out_womask_714; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_606 = {hi_424, flags_0_go, _out_prepend_T_606}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7109 = out_prepend_606; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7110 = _out_T_7109; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_180 = _out_T_7110; // @[MuxLiteral.scala:49:48] wire out_rimask_715 = \|_out_rimask_T_715; // @[RegisterRouter.scala:87:24] wire out_wimask_715 = &_out_wimask_T_715; // @[RegisterRouter.scala:87:24] wire out_romask_715 = \|_out_romask_T_715; // @[RegisterRouter.scala:87:24] wire out_womask_715 = &_out_womask_T_715; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_715 = out_rivalid_1_569 & out_rimask_715; // @[RegisterRouter.scala:87:24] wire _out_T_7112 = out_f_rivalid_715; // @[RegisterRouter.scala:87:24] wire out_f_roready_715 = out_roready_1_569 & out_romask_715; // @[RegisterRouter.scala:87:24] wire _out_T_7113 = out_f_roready_715; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_715 = out_wivalid_1_569 & out_wimask_715; // @[RegisterRouter.scala:87:24] wire out_f_woready_715 = out_woready_1_569 & out_womask_715; // @[RegisterRouter.scala:87:24] wire _out_T_7114 = ~out_rimask_715; // @[RegisterRouter.scala:87:24] wire _out_T_7115 = ~out_wimask_715; // @[RegisterRouter.scala:87:24] wire _out_T_7116 = ~out_romask_715; // @[RegisterRouter.scala:87:24] wire _out_T_7117 = ~out_womask_715; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7119 = _out_T_7118; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_607 = _out_T_7119; // @[RegisterRouter.scala:87:24] wire out_rimask_716 = \|_out_rimask_T_716; // @[RegisterRouter.scala:87:24] wire out_wimask_716 = &_out_wimask_T_716; // @[RegisterRouter.scala:87:24] wire out_romask_716 = \|_out_romask_T_716; // @[RegisterRouter.scala:87:24] wire out_womask_716 = &_out_womask_T_716; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_716 = out_rivalid_1_570 & out_rimask_716; // @[RegisterRouter.scala:87:24] wire _out_T_7121 = out_f_rivalid_716; // @[RegisterRouter.scala:87:24] wire out_f_roready_716 = out_roready_1_570 & out_romask_716; // @[RegisterRouter.scala:87:24] wire _out_T_7122 = out_f_roready_716; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_716 = out_wivalid_1_570 & out_wimask_716; // @[RegisterRouter.scala:87:24] wire out_f_woready_716 = out_woready_1_570 & out_womask_716; // @[RegisterRouter.scala:87:24] wire _out_T_7123 = ~out_rimask_716; // @[RegisterRouter.scala:87:24] wire _out_T_7124 = ~out_wimask_716; // @[RegisterRouter.scala:87:24] wire _out_T_7125 = ~out_romask_716; // @[RegisterRouter.scala:87:24] wire _out_T_7126 = ~out_womask_716; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_607 = {hi_170, flags_0_go, _out_prepend_T_607}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7127 = out_prepend_607; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7128 = _out_T_7127; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_608 = _out_T_7128; // @[RegisterRouter.scala:87:24] wire out_rimask_717 = \|_out_rimask_T_717; // @[RegisterRouter.scala:87:24] wire out_wimask_717 = &_out_wimask_T_717; // @[RegisterRouter.scala:87:24] wire out_romask_717 = \|_out_romask_T_717; // @[RegisterRouter.scala:87:24] wire out_womask_717 = &_out_womask_T_717; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_717 = out_rivalid_1_571 & out_rimask_717; // @[RegisterRouter.scala:87:24] wire _out_T_7130 = out_f_rivalid_717; // @[RegisterRouter.scala:87:24] wire out_f_roready_717 = out_roready_1_571 & out_romask_717; // @[RegisterRouter.scala:87:24] wire _out_T_7131 = out_f_roready_717; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_717 = out_wivalid_1_571 & out_wimask_717; // @[RegisterRouter.scala:87:24] wire out_f_woready_717 = out_woready_1_571 & out_womask_717; // @[RegisterRouter.scala:87:24] wire _out_T_7132 = ~out_rimask_717; // @[RegisterRouter.scala:87:24] wire _out_T_7133 = ~out_wimask_717; // @[RegisterRouter.scala:87:24] wire _out_T_7134 = ~out_romask_717; // @[RegisterRouter.scala:87:24] wire _out_T_7135 = ~out_womask_717; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_608 = {hi_171, flags_0_go, _out_prepend_T_608}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7136 = out_prepend_608; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7137 = _out_T_7136; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_609 = _out_T_7137; // @[RegisterRouter.scala:87:24] wire out_rimask_718 = \|_out_rimask_T_718; // @[RegisterRouter.scala:87:24] wire out_wimask_718 = &_out_wimask_T_718; // @[RegisterRouter.scala:87:24] wire out_romask_718 = \|_out_romask_T_718; // @[RegisterRouter.scala:87:24] wire out_womask_718 = &_out_womask_T_718; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_718 = out_rivalid_1_572 & out_rimask_718; // @[RegisterRouter.scala:87:24] wire _out_T_7139 = out_f_rivalid_718; // @[RegisterRouter.scala:87:24] wire out_f_roready_718 = out_roready_1_572 & out_romask_718; // @[RegisterRouter.scala:87:24] wire _out_T_7140 = out_f_roready_718; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_718 = out_wivalid_1_572 & out_wimask_718; // @[RegisterRouter.scala:87:24] wire out_f_woready_718 = out_woready_1_572 & out_womask_718; // @[RegisterRouter.scala:87:24] wire _out_T_7141 = ~out_rimask_718; // @[RegisterRouter.scala:87:24] wire _out_T_7142 = ~out_wimask_718; // @[RegisterRouter.scala:87:24] wire _out_T_7143 = ~out_romask_718; // @[RegisterRouter.scala:87:24] wire _out_T_7144 = ~out_womask_718; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_609 = {hi_172, flags_0_go, _out_prepend_T_609}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7145 = out_prepend_609; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7146 = _out_T_7145; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_610 = _out_T_7146; // @[RegisterRouter.scala:87:24] wire out_rimask_719 = \|_out_rimask_T_719; // @[RegisterRouter.scala:87:24] wire out_wimask_719 = &_out_wimask_T_719; // @[RegisterRouter.scala:87:24] wire out_romask_719 = \|_out_romask_T_719; // @[RegisterRouter.scala:87:24] wire out_womask_719 = &_out_womask_T_719; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_719 = out_rivalid_1_573 & out_rimask_719; // @[RegisterRouter.scala:87:24] wire _out_T_7148 = out_f_rivalid_719; // @[RegisterRouter.scala:87:24] wire out_f_roready_719 = out_roready_1_573 & out_romask_719; // @[RegisterRouter.scala:87:24] wire _out_T_7149 = out_f_roready_719; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_719 = out_wivalid_1_573 & out_wimask_719; // @[RegisterRouter.scala:87:24] wire out_f_woready_719 = out_woready_1_573 & out_womask_719; // @[RegisterRouter.scala:87:24] wire _out_T_7150 = ~out_rimask_719; // @[RegisterRouter.scala:87:24] wire _out_T_7151 = ~out_wimask_719; // @[RegisterRouter.scala:87:24] wire _out_T_7152 = ~out_romask_719; // @[RegisterRouter.scala:87:24] wire _out_T_7153 = ~out_womask_719; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_610 = {hi_173, flags_0_go, _out_prepend_T_610}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7154 = out_prepend_610; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7155 = _out_T_7154; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_611 = _out_T_7155; // @[RegisterRouter.scala:87:24] wire out_rimask_720 = \|_out_rimask_T_720; // @[RegisterRouter.scala:87:24] wire out_wimask_720 = &_out_wimask_T_720; // @[RegisterRouter.scala:87:24] wire out_romask_720 = \|_out_romask_T_720; // @[RegisterRouter.scala:87:24] wire out_womask_720 = &_out_womask_T_720; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_720 = out_rivalid_1_574 & out_rimask_720; // @[RegisterRouter.scala:87:24] wire _out_T_7157 = out_f_rivalid_720; // @[RegisterRouter.scala:87:24] wire out_f_roready_720 = out_roready_1_574 & out_romask_720; // @[RegisterRouter.scala:87:24] wire _out_T_7158 = out_f_roready_720; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_720 = out_wivalid_1_574 & out_wimask_720; // @[RegisterRouter.scala:87:24] wire out_f_woready_720 = out_woready_1_574 & out_womask_720; // @[RegisterRouter.scala:87:24] wire _out_T_7159 = ~out_rimask_720; // @[RegisterRouter.scala:87:24] wire _out_T_7160 = ~out_wimask_720; // @[RegisterRouter.scala:87:24] wire _out_T_7161 = ~out_romask_720; // @[RegisterRouter.scala:87:24] wire _out_T_7162 = ~out_womask_720; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_611 = {hi_174, flags_0_go, _out_prepend_T_611}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7163 = out_prepend_611; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7164 = _out_T_7163; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_612 = _out_T_7164; // @[RegisterRouter.scala:87:24] wire out_rimask_721 = \|_out_rimask_T_721; // @[RegisterRouter.scala:87:24] wire out_wimask_721 = &_out_wimask_T_721; // @[RegisterRouter.scala:87:24] wire out_romask_721 = \|_out_romask_T_721; // @[RegisterRouter.scala:87:24] wire out_womask_721 = &_out_womask_T_721; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_721 = out_rivalid_1_575 & out_rimask_721; // @[RegisterRouter.scala:87:24] wire _out_T_7166 = out_f_rivalid_721; // @[RegisterRouter.scala:87:24] wire out_f_roready_721 = out_roready_1_575 & out_romask_721; // @[RegisterRouter.scala:87:24] wire _out_T_7167 = out_f_roready_721; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_721 = out_wivalid_1_575 & out_wimask_721; // @[RegisterRouter.scala:87:24] wire out_f_woready_721 = out_woready_1_575 & out_womask_721; // @[RegisterRouter.scala:87:24] wire _out_T_7168 = ~out_rimask_721; // @[RegisterRouter.scala:87:24] wire _out_T_7169 = ~out_wimask_721; // @[RegisterRouter.scala:87:24] wire _out_T_7170 = ~out_romask_721; // @[RegisterRouter.scala:87:24] wire _out_T_7171 = ~out_womask_721; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_612 = {hi_175, flags_0_go, _out_prepend_T_612}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7172 = out_prepend_612; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7173 = _out_T_7172; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_613 = _out_T_7173; // @[RegisterRouter.scala:87:24] wire out_rimask_722 = \|_out_rimask_T_722; // @[RegisterRouter.scala:87:24] wire out_wimask_722 = &_out_wimask_T_722; // @[RegisterRouter.scala:87:24] wire out_romask_722 = \|_out_romask_T_722; // @[RegisterRouter.scala:87:24] wire out_womask_722 = &_out_womask_T_722; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_722 = out_rivalid_1_576 & out_rimask_722; // @[RegisterRouter.scala:87:24] wire _out_T_7175 = out_f_rivalid_722; // @[RegisterRouter.scala:87:24] wire out_f_roready_722 = out_roready_1_576 & out_romask_722; // @[RegisterRouter.scala:87:24] wire _out_T_7176 = out_f_roready_722; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_722 = out_wivalid_1_576 & out_wimask_722; // @[RegisterRouter.scala:87:24] wire out_f_woready_722 = out_woready_1_576 & out_womask_722; // @[RegisterRouter.scala:87:24] wire _out_T_7177 = ~out_rimask_722; // @[RegisterRouter.scala:87:24] wire _out_T_7178 = ~out_wimask_722; // @[RegisterRouter.scala:87:24] wire _out_T_7179 = ~out_romask_722; // @[RegisterRouter.scala:87:24] wire _out_T_7180 = ~out_womask_722; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_613 = {hi_176, flags_0_go, _out_prepend_T_613}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7181 = out_prepend_613; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7182 = _out_T_7181; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_149 = _out_T_7182; // @[MuxLiteral.scala:49:48] wire out_rimask_723 = \|_out_rimask_T_723; // @[RegisterRouter.scala:87:24] wire out_wimask_723 = &_out_wimask_T_723; // @[RegisterRouter.scala:87:24] wire out_romask_723 = \|_out_romask_T_723; // @[RegisterRouter.scala:87:24] wire out_womask_723 = &_out_womask_T_723; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_723 = out_rivalid_1_577 & out_rimask_723; // @[RegisterRouter.scala:87:24] wire _out_T_7184 = out_f_rivalid_723; // @[RegisterRouter.scala:87:24] wire out_f_roready_723 = out_roready_1_577 & out_romask_723; // @[RegisterRouter.scala:87:24] wire _out_T_7185 = out_f_roready_723; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_723 = out_wivalid_1_577 & out_wimask_723; // @[RegisterRouter.scala:87:24] wire out_f_woready_723 = out_woready_1_577 & out_womask_723; // @[RegisterRouter.scala:87:24] wire _out_T_7186 = ~out_rimask_723; // @[RegisterRouter.scala:87:24] wire _out_T_7187 = ~out_wimask_723; // @[RegisterRouter.scala:87:24] wire _out_T_7188 = ~out_romask_723; // @[RegisterRouter.scala:87:24] wire _out_T_7189 = ~out_womask_723; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7191 = _out_T_7190; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_614 = _out_T_7191; // @[RegisterRouter.scala:87:24] wire out_rimask_724 = \|_out_rimask_T_724; // @[RegisterRouter.scala:87:24] wire out_wimask_724 = &_out_wimask_T_724; // @[RegisterRouter.scala:87:24] wire out_romask_724 = \|_out_romask_T_724; // @[RegisterRouter.scala:87:24] wire out_womask_724 = &_out_womask_T_724; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_724 = out_rivalid_1_578 & out_rimask_724; // @[RegisterRouter.scala:87:24] wire _out_T_7193 = out_f_rivalid_724; // @[RegisterRouter.scala:87:24] wire out_f_roready_724 = out_roready_1_578 & out_romask_724; // @[RegisterRouter.scala:87:24] wire _out_T_7194 = out_f_roready_724; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_724 = out_wivalid_1_578 & out_wimask_724; // @[RegisterRouter.scala:87:24] wire out_f_woready_724 = out_woready_1_578 & out_womask_724; // @[RegisterRouter.scala:87:24] wire _out_T_7195 = ~out_rimask_724; // @[RegisterRouter.scala:87:24] wire _out_T_7196 = ~out_wimask_724; // @[RegisterRouter.scala:87:24] wire _out_T_7197 = ~out_romask_724; // @[RegisterRouter.scala:87:24] wire _out_T_7198 = ~out_womask_724; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_614 = {hi_386, flags_0_go, _out_prepend_T_614}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7199 = out_prepend_614; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7200 = _out_T_7199; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_615 = _out_T_7200; // @[RegisterRouter.scala:87:24] wire out_rimask_725 = \|_out_rimask_T_725; // @[RegisterRouter.scala:87:24] wire out_wimask_725 = &_out_wimask_T_725; // @[RegisterRouter.scala:87:24] wire out_romask_725 = \|_out_romask_T_725; // @[RegisterRouter.scala:87:24] wire out_womask_725 = &_out_womask_T_725; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_725 = out_rivalid_1_579 & out_rimask_725; // @[RegisterRouter.scala:87:24] wire _out_T_7202 = out_f_rivalid_725; // @[RegisterRouter.scala:87:24] wire out_f_roready_725 = out_roready_1_579 & out_romask_725; // @[RegisterRouter.scala:87:24] wire _out_T_7203 = out_f_roready_725; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_725 = out_wivalid_1_579 & out_wimask_725; // @[RegisterRouter.scala:87:24] wire out_f_woready_725 = out_woready_1_579 & out_womask_725; // @[RegisterRouter.scala:87:24] wire _out_T_7204 = ~out_rimask_725; // @[RegisterRouter.scala:87:24] wire _out_T_7205 = ~out_wimask_725; // @[RegisterRouter.scala:87:24] wire _out_T_7206 = ~out_romask_725; // @[RegisterRouter.scala:87:24] wire _out_T_7207 = ~out_womask_725; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_615 = {hi_387, flags_0_go, _out_prepend_T_615}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7208 = out_prepend_615; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7209 = _out_T_7208; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_616 = _out_T_7209; // @[RegisterRouter.scala:87:24] wire out_rimask_726 = \|_out_rimask_T_726; // @[RegisterRouter.scala:87:24] wire out_wimask_726 = &_out_wimask_T_726; // @[RegisterRouter.scala:87:24] wire out_romask_726 = \|_out_romask_T_726; // @[RegisterRouter.scala:87:24] wire out_womask_726 = &_out_womask_T_726; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_726 = out_rivalid_1_580 & out_rimask_726; // @[RegisterRouter.scala:87:24] wire _out_T_7211 = out_f_rivalid_726; // @[RegisterRouter.scala:87:24] wire out_f_roready_726 = out_roready_1_580 & out_romask_726; // @[RegisterRouter.scala:87:24] wire _out_T_7212 = out_f_roready_726; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_726 = out_wivalid_1_580 & out_wimask_726; // @[RegisterRouter.scala:87:24] wire out_f_woready_726 = out_woready_1_580 & out_womask_726; // @[RegisterRouter.scala:87:24] wire _out_T_7213 = ~out_rimask_726; // @[RegisterRouter.scala:87:24] wire _out_T_7214 = ~out_wimask_726; // @[RegisterRouter.scala:87:24] wire _out_T_7215 = ~out_romask_726; // @[RegisterRouter.scala:87:24] wire _out_T_7216 = ~out_womask_726; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_616 = {hi_388, flags_0_go, _out_prepend_T_616}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7217 = out_prepend_616; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7218 = _out_T_7217; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_617 = _out_T_7218; // @[RegisterRouter.scala:87:24] wire out_rimask_727 = \|_out_rimask_T_727; // @[RegisterRouter.scala:87:24] wire out_wimask_727 = &_out_wimask_T_727; // @[RegisterRouter.scala:87:24] wire out_romask_727 = \|_out_romask_T_727; // @[RegisterRouter.scala:87:24] wire out_womask_727 = &_out_womask_T_727; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_727 = out_rivalid_1_581 & out_rimask_727; // @[RegisterRouter.scala:87:24] wire _out_T_7220 = out_f_rivalid_727; // @[RegisterRouter.scala:87:24] wire out_f_roready_727 = out_roready_1_581 & out_romask_727; // @[RegisterRouter.scala:87:24] wire _out_T_7221 = out_f_roready_727; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_727 = out_wivalid_1_581 & out_wimask_727; // @[RegisterRouter.scala:87:24] wire out_f_woready_727 = out_woready_1_581 & out_womask_727; // @[RegisterRouter.scala:87:24] wire _out_T_7222 = ~out_rimask_727; // @[RegisterRouter.scala:87:24] wire _out_T_7223 = ~out_wimask_727; // @[RegisterRouter.scala:87:24] wire _out_T_7224 = ~out_romask_727; // @[RegisterRouter.scala:87:24] wire _out_T_7225 = ~out_womask_727; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_617 = {hi_389, flags_0_go, _out_prepend_T_617}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7226 = out_prepend_617; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7227 = _out_T_7226; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_618 = _out_T_7227; // @[RegisterRouter.scala:87:24] wire out_rimask_728 = \|_out_rimask_T_728; // @[RegisterRouter.scala:87:24] wire out_wimask_728 = &_out_wimask_T_728; // @[RegisterRouter.scala:87:24] wire out_romask_728 = \|_out_romask_T_728; // @[RegisterRouter.scala:87:24] wire out_womask_728 = &_out_womask_T_728; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_728 = out_rivalid_1_582 & out_rimask_728; // @[RegisterRouter.scala:87:24] wire _out_T_7229 = out_f_rivalid_728; // @[RegisterRouter.scala:87:24] wire out_f_roready_728 = out_roready_1_582 & out_romask_728; // @[RegisterRouter.scala:87:24] wire _out_T_7230 = out_f_roready_728; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_728 = out_wivalid_1_582 & out_wimask_728; // @[RegisterRouter.scala:87:24] wire out_f_woready_728 = out_woready_1_582 & out_womask_728; // @[RegisterRouter.scala:87:24] wire _out_T_7231 = ~out_rimask_728; // @[RegisterRouter.scala:87:24] wire _out_T_7232 = ~out_wimask_728; // @[RegisterRouter.scala:87:24] wire _out_T_7233 = ~out_romask_728; // @[RegisterRouter.scala:87:24] wire _out_T_7234 = ~out_womask_728; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_618 = {hi_390, flags_0_go, _out_prepend_T_618}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7235 = out_prepend_618; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7236 = _out_T_7235; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_619 = _out_T_7236; // @[RegisterRouter.scala:87:24] wire out_rimask_729 = \|_out_rimask_T_729; // @[RegisterRouter.scala:87:24] wire out_wimask_729 = &_out_wimask_T_729; // @[RegisterRouter.scala:87:24] wire out_romask_729 = \|_out_romask_T_729; // @[RegisterRouter.scala:87:24] wire out_womask_729 = &_out_womask_T_729; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_729 = out_rivalid_1_583 & out_rimask_729; // @[RegisterRouter.scala:87:24] wire _out_T_7238 = out_f_rivalid_729; // @[RegisterRouter.scala:87:24] wire out_f_roready_729 = out_roready_1_583 & out_romask_729; // @[RegisterRouter.scala:87:24] wire _out_T_7239 = out_f_roready_729; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_729 = out_wivalid_1_583 & out_wimask_729; // @[RegisterRouter.scala:87:24] wire out_f_woready_729 = out_woready_1_583 & out_womask_729; // @[RegisterRouter.scala:87:24] wire _out_T_7240 = ~out_rimask_729; // @[RegisterRouter.scala:87:24] wire _out_T_7241 = ~out_wimask_729; // @[RegisterRouter.scala:87:24] wire _out_T_7242 = ~out_romask_729; // @[RegisterRouter.scala:87:24] wire _out_T_7243 = ~out_womask_729; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_619 = {hi_391, flags_0_go, _out_prepend_T_619}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7244 = out_prepend_619; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7245 = _out_T_7244; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_620 = _out_T_7245; // @[RegisterRouter.scala:87:24] wire out_rimask_730 = \|_out_rimask_T_730; // @[RegisterRouter.scala:87:24] wire out_wimask_730 = &_out_wimask_T_730; // @[RegisterRouter.scala:87:24] wire out_romask_730 = \|_out_romask_T_730; // @[RegisterRouter.scala:87:24] wire out_womask_730 = &_out_womask_T_730; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_730 = out_rivalid_1_584 & out_rimask_730; // @[RegisterRouter.scala:87:24] wire _out_T_7247 = out_f_rivalid_730; // @[RegisterRouter.scala:87:24] wire out_f_roready_730 = out_roready_1_584 & out_romask_730; // @[RegisterRouter.scala:87:24] wire _out_T_7248 = out_f_roready_730; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_730 = out_wivalid_1_584 & out_wimask_730; // @[RegisterRouter.scala:87:24] wire out_f_woready_730 = out_woready_1_584 & out_womask_730; // @[RegisterRouter.scala:87:24] wire _out_T_7249 = ~out_rimask_730; // @[RegisterRouter.scala:87:24] wire _out_T_7250 = ~out_wimask_730; // @[RegisterRouter.scala:87:24] wire _out_T_7251 = ~out_romask_730; // @[RegisterRouter.scala:87:24] wire _out_T_7252 = ~out_womask_730; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_620 = {hi_392, flags_0_go, _out_prepend_T_620}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7253 = out_prepend_620; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7254 = _out_T_7253; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_176 = _out_T_7254; // @[MuxLiteral.scala:49:48] wire out_rimask_731 = \|_out_rimask_T_731; // @[RegisterRouter.scala:87:24] wire out_wimask_731 = &_out_wimask_T_731; // @[RegisterRouter.scala:87:24] wire out_romask_731 = \|_out_romask_T_731; // @[RegisterRouter.scala:87:24] wire out_womask_731 = &_out_womask_T_731; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_731 = out_rivalid_1_585 & out_rimask_731; // @[RegisterRouter.scala:87:24] wire _out_T_7256 = out_f_rivalid_731; // @[RegisterRouter.scala:87:24] wire out_f_roready_731 = out_roready_1_585 & out_romask_731; // @[RegisterRouter.scala:87:24] wire _out_T_7257 = out_f_roready_731; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_731 = out_wivalid_1_585 & out_wimask_731; // @[RegisterRouter.scala:87:24] wire out_f_woready_731 = out_woready_1_585 & out_womask_731; // @[RegisterRouter.scala:87:24] wire _out_T_7258 = ~out_rimask_731; // @[RegisterRouter.scala:87:24] wire _out_T_7259 = ~out_wimask_731; // @[RegisterRouter.scala:87:24] wire _out_T_7260 = ~out_romask_731; // @[RegisterRouter.scala:87:24] wire _out_T_7261 = ~out_womask_731; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7263 = _out_T_7262; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_621 = _out_T_7263; // @[RegisterRouter.scala:87:24] wire out_rimask_732 = \|_out_rimask_T_732; // @[RegisterRouter.scala:87:24] wire out_wimask_732 = &_out_wimask_T_732; // @[RegisterRouter.scala:87:24] wire out_romask_732 = \|_out_romask_T_732; // @[RegisterRouter.scala:87:24] wire out_womask_732 = &_out_womask_T_732; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_732 = out_rivalid_1_586 & out_rimask_732; // @[RegisterRouter.scala:87:24] wire _out_T_7265 = out_f_rivalid_732; // @[RegisterRouter.scala:87:24] wire out_f_roready_732 = out_roready_1_586 & out_romask_732; // @[RegisterRouter.scala:87:24] wire _out_T_7266 = out_f_roready_732; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_732 = out_wivalid_1_586 & out_wimask_732; // @[RegisterRouter.scala:87:24] wire out_f_woready_732 = out_woready_1_586 & out_womask_732; // @[RegisterRouter.scala:87:24] wire _out_T_7267 = ~out_rimask_732; // @[RegisterRouter.scala:87:24] wire _out_T_7268 = ~out_wimask_732; // @[RegisterRouter.scala:87:24] wire _out_T_7269 = ~out_romask_732; // @[RegisterRouter.scala:87:24] wire _out_T_7270 = ~out_womask_732; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_621 = {hi_506, flags_0_go, _out_prepend_T_621}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7271 = out_prepend_621; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7272 = _out_T_7271; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_622 = _out_T_7272; // @[RegisterRouter.scala:87:24] wire out_rimask_733 = \|_out_rimask_T_733; // @[RegisterRouter.scala:87:24] wire out_wimask_733 = &_out_wimask_T_733; // @[RegisterRouter.scala:87:24] wire out_romask_733 = \|_out_romask_T_733; // @[RegisterRouter.scala:87:24] wire out_womask_733 = &_out_womask_T_733; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_733 = out_rivalid_1_587 & out_rimask_733; // @[RegisterRouter.scala:87:24] wire _out_T_7274 = out_f_rivalid_733; // @[RegisterRouter.scala:87:24] wire out_f_roready_733 = out_roready_1_587 & out_romask_733; // @[RegisterRouter.scala:87:24] wire _out_T_7275 = out_f_roready_733; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_733 = out_wivalid_1_587 & out_wimask_733; // @[RegisterRouter.scala:87:24] wire out_f_woready_733 = out_woready_1_587 & out_womask_733; // @[RegisterRouter.scala:87:24] wire _out_T_7276 = ~out_rimask_733; // @[RegisterRouter.scala:87:24] wire _out_T_7277 = ~out_wimask_733; // @[RegisterRouter.scala:87:24] wire _out_T_7278 = ~out_romask_733; // @[RegisterRouter.scala:87:24] wire _out_T_7279 = ~out_womask_733; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_622 = {hi_507, flags_0_go, _out_prepend_T_622}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7280 = out_prepend_622; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7281 = _out_T_7280; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_623 = _out_T_7281; // @[RegisterRouter.scala:87:24] wire out_rimask_734 = \|_out_rimask_T_734; // @[RegisterRouter.scala:87:24] wire out_wimask_734 = &_out_wimask_T_734; // @[RegisterRouter.scala:87:24] wire out_romask_734 = \|_out_romask_T_734; // @[RegisterRouter.scala:87:24] wire out_womask_734 = &_out_womask_T_734; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_734 = out_rivalid_1_588 & out_rimask_734; // @[RegisterRouter.scala:87:24] wire _out_T_7283 = out_f_rivalid_734; // @[RegisterRouter.scala:87:24] wire out_f_roready_734 = out_roready_1_588 & out_romask_734; // @[RegisterRouter.scala:87:24] wire _out_T_7284 = out_f_roready_734; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_734 = out_wivalid_1_588 & out_wimask_734; // @[RegisterRouter.scala:87:24] wire out_f_woready_734 = out_woready_1_588 & out_womask_734; // @[RegisterRouter.scala:87:24] wire _out_T_7285 = ~out_rimask_734; // @[RegisterRouter.scala:87:24] wire _out_T_7286 = ~out_wimask_734; // @[RegisterRouter.scala:87:24] wire _out_T_7287 = ~out_romask_734; // @[RegisterRouter.scala:87:24] wire _out_T_7288 = ~out_womask_734; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_623 = {hi_508, flags_0_go, _out_prepend_T_623}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7289 = out_prepend_623; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7290 = _out_T_7289; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_624 = _out_T_7290; // @[RegisterRouter.scala:87:24] wire out_rimask_735 = \|_out_rimask_T_735; // @[RegisterRouter.scala:87:24] wire out_wimask_735 = &_out_wimask_T_735; // @[RegisterRouter.scala:87:24] wire out_romask_735 = \|_out_romask_T_735; // @[RegisterRouter.scala:87:24] wire out_womask_735 = &_out_womask_T_735; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_735 = out_rivalid_1_589 & out_rimask_735; // @[RegisterRouter.scala:87:24] wire _out_T_7292 = out_f_rivalid_735; // @[RegisterRouter.scala:87:24] wire out_f_roready_735 = out_roready_1_589 & out_romask_735; // @[RegisterRouter.scala:87:24] wire _out_T_7293 = out_f_roready_735; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_735 = out_wivalid_1_589 & out_wimask_735; // @[RegisterRouter.scala:87:24] wire out_f_woready_735 = out_woready_1_589 & out_womask_735; // @[RegisterRouter.scala:87:24] wire _out_T_7294 = ~out_rimask_735; // @[RegisterRouter.scala:87:24] wire _out_T_7295 = ~out_wimask_735; // @[RegisterRouter.scala:87:24] wire _out_T_7296 = ~out_romask_735; // @[RegisterRouter.scala:87:24] wire _out_T_7297 = ~out_womask_735; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_624 = {hi_509, flags_0_go, _out_prepend_T_624}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7298 = out_prepend_624; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7299 = _out_T_7298; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_625 = _out_T_7299; // @[RegisterRouter.scala:87:24] wire out_rimask_736 = \|_out_rimask_T_736; // @[RegisterRouter.scala:87:24] wire out_wimask_736 = &_out_wimask_T_736; // @[RegisterRouter.scala:87:24] wire out_romask_736 = \|_out_romask_T_736; // @[RegisterRouter.scala:87:24] wire out_womask_736 = &_out_womask_T_736; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_736 = out_rivalid_1_590 & out_rimask_736; // @[RegisterRouter.scala:87:24] wire _out_T_7301 = out_f_rivalid_736; // @[RegisterRouter.scala:87:24] wire out_f_roready_736 = out_roready_1_590 & out_romask_736; // @[RegisterRouter.scala:87:24] wire _out_T_7302 = out_f_roready_736; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_736 = out_wivalid_1_590 & out_wimask_736; // @[RegisterRouter.scala:87:24] wire out_f_woready_736 = out_woready_1_590 & out_womask_736; // @[RegisterRouter.scala:87:24] wire _out_T_7303 = ~out_rimask_736; // @[RegisterRouter.scala:87:24] wire _out_T_7304 = ~out_wimask_736; // @[RegisterRouter.scala:87:24] wire _out_T_7305 = ~out_romask_736; // @[RegisterRouter.scala:87:24] wire _out_T_7306 = ~out_womask_736; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_625 = {hi_510, flags_0_go, _out_prepend_T_625}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7307 = out_prepend_625; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7308 = _out_T_7307; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_626 = _out_T_7308; // @[RegisterRouter.scala:87:24] wire out_rimask_737 = \|_out_rimask_T_737; // @[RegisterRouter.scala:87:24] wire out_wimask_737 = &_out_wimask_T_737; // @[RegisterRouter.scala:87:24] wire out_romask_737 = \|_out_romask_T_737; // @[RegisterRouter.scala:87:24] wire out_womask_737 = &_out_womask_T_737; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_737 = out_rivalid_1_591 & out_rimask_737; // @[RegisterRouter.scala:87:24] wire _out_T_7310 = out_f_rivalid_737; // @[RegisterRouter.scala:87:24] wire out_f_roready_737 = out_roready_1_591 & out_romask_737; // @[RegisterRouter.scala:87:24] wire _out_T_7311 = out_f_roready_737; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_737 = out_wivalid_1_591 & out_wimask_737; // @[RegisterRouter.scala:87:24] wire out_f_woready_737 = out_woready_1_591 & out_womask_737; // @[RegisterRouter.scala:87:24] wire _out_T_7312 = ~out_rimask_737; // @[RegisterRouter.scala:87:24] wire _out_T_7313 = ~out_wimask_737; // @[RegisterRouter.scala:87:24] wire _out_T_7314 = ~out_romask_737; // @[RegisterRouter.scala:87:24] wire _out_T_7315 = ~out_womask_737; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_626 = {hi_511, flags_0_go, _out_prepend_T_626}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7316 = out_prepend_626; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7317 = _out_T_7316; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_627 = _out_T_7317; // @[RegisterRouter.scala:87:24] wire out_rimask_738 = \|_out_rimask_T_738; // @[RegisterRouter.scala:87:24] wire out_wimask_738 = &_out_wimask_T_738; // @[RegisterRouter.scala:87:24] wire out_romask_738 = \|_out_romask_T_738; // @[RegisterRouter.scala:87:24] wire out_womask_738 = &_out_womask_T_738; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_738 = out_rivalid_1_592 & out_rimask_738; // @[RegisterRouter.scala:87:24] wire _out_T_7319 = out_f_rivalid_738; // @[RegisterRouter.scala:87:24] wire out_f_roready_738 = out_roready_1_592 & out_romask_738; // @[RegisterRouter.scala:87:24] wire _out_T_7320 = out_f_roready_738; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_738 = out_wivalid_1_592 & out_wimask_738; // @[RegisterRouter.scala:87:24] wire out_f_woready_738 = out_woready_1_592 & out_womask_738; // @[RegisterRouter.scala:87:24] wire _out_T_7321 = ~out_rimask_738; // @[RegisterRouter.scala:87:24] wire _out_T_7322 = ~out_wimask_738; // @[RegisterRouter.scala:87:24] wire _out_T_7323 = ~out_romask_738; // @[RegisterRouter.scala:87:24] wire _out_T_7324 = ~out_womask_738; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_627 = {hi_512, flags_0_go, _out_prepend_T_627}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7325 = out_prepend_627; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7326 = _out_T_7325; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_191 = _out_T_7326; // @[MuxLiteral.scala:49:48] wire out_rimask_739 = \|_out_rimask_T_739; // @[RegisterRouter.scala:87:24] wire out_wimask_739 = &_out_wimask_T_739; // @[RegisterRouter.scala:87:24] wire out_romask_739 = \|_out_romask_T_739; // @[RegisterRouter.scala:87:24] wire out_womask_739 = &_out_womask_T_739; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_739 = out_rivalid_1_593 & out_rimask_739; // @[RegisterRouter.scala:87:24] wire _out_T_7328 = out_f_rivalid_739; // @[RegisterRouter.scala:87:24] wire out_f_roready_739 = out_roready_1_593 & out_romask_739; // @[RegisterRouter.scala:87:24] wire _out_T_7329 = out_f_roready_739; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_739 = out_wivalid_1_593 & out_wimask_739; // @[RegisterRouter.scala:87:24] wire out_f_woready_739 = out_woready_1_593 & out_womask_739; // @[RegisterRouter.scala:87:24] wire _out_T_7330 = ~out_rimask_739; // @[RegisterRouter.scala:87:24] wire _out_T_7331 = ~out_wimask_739; // @[RegisterRouter.scala:87:24] wire _out_T_7332 = ~out_romask_739; // @[RegisterRouter.scala:87:24] wire _out_T_7333 = ~out_womask_739; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7335 = _out_T_7334; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_628 = _out_T_7335; // @[RegisterRouter.scala:87:24] wire out_rimask_740 = \|_out_rimask_T_740; // @[RegisterRouter.scala:87:24] wire out_wimask_740 = &_out_wimask_T_740; // @[RegisterRouter.scala:87:24] wire out_romask_740 = \|_out_romask_T_740; // @[RegisterRouter.scala:87:24] wire out_womask_740 = &_out_womask_T_740; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_740 = out_rivalid_1_594 & out_rimask_740; // @[RegisterRouter.scala:87:24] wire _out_T_7337 = out_f_rivalid_740; // @[RegisterRouter.scala:87:24] wire out_f_roready_740 = out_roready_1_594 & out_romask_740; // @[RegisterRouter.scala:87:24] wire _out_T_7338 = out_f_roready_740; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_740 = out_wivalid_1_594 & out_wimask_740; // @[RegisterRouter.scala:87:24] wire out_f_woready_740 = out_woready_1_594 & out_womask_740; // @[RegisterRouter.scala:87:24] wire _out_T_7339 = ~out_rimask_740; // @[RegisterRouter.scala:87:24] wire _out_T_7340 = ~out_wimask_740; // @[RegisterRouter.scala:87:24] wire _out_T_7341 = ~out_romask_740; // @[RegisterRouter.scala:87:24] wire _out_T_7342 = ~out_womask_740; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_628 = {hi_610, flags_0_go, _out_prepend_T_628}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7343 = out_prepend_628; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7344 = _out_T_7343; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_629 = _out_T_7344; // @[RegisterRouter.scala:87:24] wire out_rimask_741 = \|_out_rimask_T_741; // @[RegisterRouter.scala:87:24] wire out_wimask_741 = &_out_wimask_T_741; // @[RegisterRouter.scala:87:24] wire out_romask_741 = \|_out_romask_T_741; // @[RegisterRouter.scala:87:24] wire out_womask_741 = &_out_womask_T_741; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_741 = out_rivalid_1_595 & out_rimask_741; // @[RegisterRouter.scala:87:24] wire _out_T_7346 = out_f_rivalid_741; // @[RegisterRouter.scala:87:24] wire out_f_roready_741 = out_roready_1_595 & out_romask_741; // @[RegisterRouter.scala:87:24] wire _out_T_7347 = out_f_roready_741; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_741 = out_wivalid_1_595 & out_wimask_741; // @[RegisterRouter.scala:87:24] wire out_f_woready_741 = out_woready_1_595 & out_womask_741; // @[RegisterRouter.scala:87:24] wire _out_T_7348 = ~out_rimask_741; // @[RegisterRouter.scala:87:24] wire _out_T_7349 = ~out_wimask_741; // @[RegisterRouter.scala:87:24] wire _out_T_7350 = ~out_romask_741; // @[RegisterRouter.scala:87:24] wire _out_T_7351 = ~out_womask_741; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_629 = {hi_611, flags_0_go, _out_prepend_T_629}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7352 = out_prepend_629; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7353 = _out_T_7352; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_630 = _out_T_7353; // @[RegisterRouter.scala:87:24] wire out_rimask_742 = \|_out_rimask_T_742; // @[RegisterRouter.scala:87:24] wire out_wimask_742 = &_out_wimask_T_742; // @[RegisterRouter.scala:87:24] wire out_romask_742 = \|_out_romask_T_742; // @[RegisterRouter.scala:87:24] wire out_womask_742 = &_out_womask_T_742; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_742 = out_rivalid_1_596 & out_rimask_742; // @[RegisterRouter.scala:87:24] wire _out_T_7355 = out_f_rivalid_742; // @[RegisterRouter.scala:87:24] wire out_f_roready_742 = out_roready_1_596 & out_romask_742; // @[RegisterRouter.scala:87:24] wire _out_T_7356 = out_f_roready_742; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_742 = out_wivalid_1_596 & out_wimask_742; // @[RegisterRouter.scala:87:24] wire out_f_woready_742 = out_woready_1_596 & out_womask_742; // @[RegisterRouter.scala:87:24] wire _out_T_7357 = ~out_rimask_742; // @[RegisterRouter.scala:87:24] wire _out_T_7358 = ~out_wimask_742; // @[RegisterRouter.scala:87:24] wire _out_T_7359 = ~out_romask_742; // @[RegisterRouter.scala:87:24] wire _out_T_7360 = ~out_womask_742; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_630 = {hi_612, flags_0_go, _out_prepend_T_630}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7361 = out_prepend_630; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7362 = _out_T_7361; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_631 = _out_T_7362; // @[RegisterRouter.scala:87:24] wire out_rimask_743 = \|_out_rimask_T_743; // @[RegisterRouter.scala:87:24] wire out_wimask_743 = &_out_wimask_T_743; // @[RegisterRouter.scala:87:24] wire out_romask_743 = \|_out_romask_T_743; // @[RegisterRouter.scala:87:24] wire out_womask_743 = &_out_womask_T_743; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_743 = out_rivalid_1_597 & out_rimask_743; // @[RegisterRouter.scala:87:24] wire _out_T_7364 = out_f_rivalid_743; // @[RegisterRouter.scala:87:24] wire out_f_roready_743 = out_roready_1_597 & out_romask_743; // @[RegisterRouter.scala:87:24] wire _out_T_7365 = out_f_roready_743; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_743 = out_wivalid_1_597 & out_wimask_743; // @[RegisterRouter.scala:87:24] wire out_f_woready_743 = out_woready_1_597 & out_womask_743; // @[RegisterRouter.scala:87:24] wire _out_T_7366 = ~out_rimask_743; // @[RegisterRouter.scala:87:24] wire _out_T_7367 = ~out_wimask_743; // @[RegisterRouter.scala:87:24] wire _out_T_7368 = ~out_romask_743; // @[RegisterRouter.scala:87:24] wire _out_T_7369 = ~out_womask_743; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_631 = {hi_613, flags_0_go, _out_prepend_T_631}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7370 = out_prepend_631; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7371 = _out_T_7370; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_632 = _out_T_7371; // @[RegisterRouter.scala:87:24] wire out_rimask_744 = \|_out_rimask_T_744; // @[RegisterRouter.scala:87:24] wire out_wimask_744 = &_out_wimask_T_744; // @[RegisterRouter.scala:87:24] wire out_romask_744 = \|_out_romask_T_744; // @[RegisterRouter.scala:87:24] wire out_womask_744 = &_out_womask_T_744; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_744 = out_rivalid_1_598 & out_rimask_744; // @[RegisterRouter.scala:87:24] wire _out_T_7373 = out_f_rivalid_744; // @[RegisterRouter.scala:87:24] wire out_f_roready_744 = out_roready_1_598 & out_romask_744; // @[RegisterRouter.scala:87:24] wire _out_T_7374 = out_f_roready_744; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_744 = out_wivalid_1_598 & out_wimask_744; // @[RegisterRouter.scala:87:24] wire out_f_woready_744 = out_woready_1_598 & out_womask_744; // @[RegisterRouter.scala:87:24] wire _out_T_7375 = ~out_rimask_744; // @[RegisterRouter.scala:87:24] wire _out_T_7376 = ~out_wimask_744; // @[RegisterRouter.scala:87:24] wire _out_T_7377 = ~out_romask_744; // @[RegisterRouter.scala:87:24] wire _out_T_7378 = ~out_womask_744; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_632 = {hi_614, flags_0_go, _out_prepend_T_632}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7379 = out_prepend_632; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7380 = _out_T_7379; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_633 = _out_T_7380; // @[RegisterRouter.scala:87:24] wire out_rimask_745 = \|_out_rimask_T_745; // @[RegisterRouter.scala:87:24] wire out_wimask_745 = &_out_wimask_T_745; // @[RegisterRouter.scala:87:24] wire out_romask_745 = \|_out_romask_T_745; // @[RegisterRouter.scala:87:24] wire out_womask_745 = &_out_womask_T_745; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_745 = out_rivalid_1_599 & out_rimask_745; // @[RegisterRouter.scala:87:24] wire _out_T_7382 = out_f_rivalid_745; // @[RegisterRouter.scala:87:24] wire out_f_roready_745 = out_roready_1_599 & out_romask_745; // @[RegisterRouter.scala:87:24] wire _out_T_7383 = out_f_roready_745; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_745 = out_wivalid_1_599 & out_wimask_745; // @[RegisterRouter.scala:87:24] wire out_f_woready_745 = out_woready_1_599 & out_womask_745; // @[RegisterRouter.scala:87:24] wire _out_T_7384 = ~out_rimask_745; // @[RegisterRouter.scala:87:24] wire _out_T_7385 = ~out_wimask_745; // @[RegisterRouter.scala:87:24] wire _out_T_7386 = ~out_romask_745; // @[RegisterRouter.scala:87:24] wire _out_T_7387 = ~out_womask_745; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_633 = {hi_615, flags_0_go, _out_prepend_T_633}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7388 = out_prepend_633; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7389 = _out_T_7388; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_634 = _out_T_7389; // @[RegisterRouter.scala:87:24] wire out_rimask_746 = \|_out_rimask_T_746; // @[RegisterRouter.scala:87:24] wire out_wimask_746 = &_out_wimask_T_746; // @[RegisterRouter.scala:87:24] wire out_romask_746 = \|_out_romask_T_746; // @[RegisterRouter.scala:87:24] wire out_womask_746 = &_out_womask_T_746; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_746 = out_rivalid_1_600 & out_rimask_746; // @[RegisterRouter.scala:87:24] wire _out_T_7391 = out_f_rivalid_746; // @[RegisterRouter.scala:87:24] wire out_f_roready_746 = out_roready_1_600 & out_romask_746; // @[RegisterRouter.scala:87:24] wire _out_T_7392 = out_f_roready_746; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_746 = out_wivalid_1_600 & out_wimask_746; // @[RegisterRouter.scala:87:24] wire out_f_woready_746 = out_woready_1_600 & out_womask_746; // @[RegisterRouter.scala:87:24] wire _out_T_7393 = ~out_rimask_746; // @[RegisterRouter.scala:87:24] wire _out_T_7394 = ~out_wimask_746; // @[RegisterRouter.scala:87:24] wire _out_T_7395 = ~out_romask_746; // @[RegisterRouter.scala:87:24] wire _out_T_7396 = ~out_womask_746; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_634 = {hi_616, flags_0_go, _out_prepend_T_634}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7397 = out_prepend_634; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7398 = _out_T_7397; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_204 = _out_T_7398; // @[MuxLiteral.scala:49:48] wire out_rimask_747 = \|_out_rimask_T_747; // @[RegisterRouter.scala:87:24] wire out_wimask_747 = &_out_wimask_T_747; // @[RegisterRouter.scala:87:24] wire out_romask_747 = \|_out_romask_T_747; // @[RegisterRouter.scala:87:24] wire out_womask_747 = &_out_womask_T_747; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_747 = out_rivalid_1_601 & out_rimask_747; // @[RegisterRouter.scala:87:24] wire _out_T_7400 = out_f_rivalid_747; // @[RegisterRouter.scala:87:24] wire out_f_roready_747 = out_roready_1_601 & out_romask_747; // @[RegisterRouter.scala:87:24] wire _out_T_7401 = out_f_roready_747; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_747 = out_wivalid_1_601 & out_wimask_747; // @[RegisterRouter.scala:87:24] wire out_f_woready_747 = out_woready_1_601 & out_womask_747; // @[RegisterRouter.scala:87:24] wire _out_T_7402 = ~out_rimask_747; // @[RegisterRouter.scala:87:24] wire _out_T_7403 = ~out_wimask_747; // @[RegisterRouter.scala:87:24] wire _out_T_7404 = ~out_romask_747; // @[RegisterRouter.scala:87:24] wire _out_T_7405 = ~out_womask_747; // @[RegisterRouter.scala:87:24] wire out_rimask_748 = \|_out_rimask_T_748; // @[RegisterRouter.scala:87:24] wire out_wimask_748 = &_out_wimask_T_748; // @[RegisterRouter.scala:87:24] wire out_romask_748 = \|_out_romask_T_748; // @[RegisterRouter.scala:87:24] wire out_womask_748 = &_out_womask_T_748; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_748 = out_rivalid_1_602 & out_rimask_748; // @[RegisterRouter.scala:87:24] wire _out_T_7409 = out_f_rivalid_748; // @[RegisterRouter.scala:87:24] wire out_f_roready_748 = out_roready_1_602 & out_romask_748; // @[RegisterRouter.scala:87:24] wire _out_T_7410 = out_f_roready_748; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_748 = out_wivalid_1_602 & out_wimask_748; // @[RegisterRouter.scala:87:24] wire out_f_woready_748 = out_woready_1_602 & out_womask_748; // @[RegisterRouter.scala:87:24] wire _out_T_7411 = ~out_rimask_748; // @[RegisterRouter.scala:87:24] wire _out_T_7412 = ~out_wimask_748; // @[RegisterRouter.scala:87:24] wire _out_T_7413 = ~out_romask_748; // @[RegisterRouter.scala:87:24] wire _out_T_7414 = ~out_womask_748; // @[RegisterRouter.scala:87:24] wire out_rimask_749 = \|_out_rimask_T_749; // @[RegisterRouter.scala:87:24] wire out_wimask_749 = &_out_wimask_T_749; // @[RegisterRouter.scala:87:24] wire out_romask_749 = \|_out_romask_T_749; // @[RegisterRouter.scala:87:24] wire out_womask_749 = &_out_womask_T_749; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_749 = out_rivalid_1_603 & out_rimask_749; // @[RegisterRouter.scala:87:24] wire _out_T_7418 = out_f_rivalid_749; // @[RegisterRouter.scala:87:24] wire out_f_roready_749 = out_roready_1_603 & out_romask_749; // @[RegisterRouter.scala:87:24] wire _out_T_7419 = out_f_roready_749; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_749 = out_wivalid_1_603 & out_wimask_749; // @[RegisterRouter.scala:87:24] wire out_f_woready_749 = out_woready_1_603 & out_womask_749; // @[RegisterRouter.scala:87:24] wire _out_T_7420 = ~out_rimask_749; // @[RegisterRouter.scala:87:24] wire _out_T_7421 = ~out_wimask_749; // @[RegisterRouter.scala:87:24] wire _out_T_7422 = ~out_romask_749; // @[RegisterRouter.scala:87:24] wire _out_T_7423 = ~out_womask_749; // @[RegisterRouter.scala:87:24] wire out_rimask_750 = \|_out_rimask_T_750; // @[RegisterRouter.scala:87:24] wire out_wimask_750 = &_out_wimask_T_750; // @[RegisterRouter.scala:87:24] wire out_romask_750 = \|_out_romask_T_750; // @[RegisterRouter.scala:87:24] wire out_womask_750 = &_out_womask_T_750; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_750 = out_rivalid_1_604 & out_rimask_750; // @[RegisterRouter.scala:87:24] wire _out_T_7427 = out_f_rivalid_750; // @[RegisterRouter.scala:87:24] wire out_f_roready_750 = out_roready_1_604 & out_romask_750; // @[RegisterRouter.scala:87:24] wire _out_T_7428 = out_f_roready_750; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_750 = out_wivalid_1_604 & out_wimask_750; // @[RegisterRouter.scala:87:24] wire out_f_woready_750 = out_woready_1_604 & out_womask_750; // @[RegisterRouter.scala:87:24] wire _out_T_7429 = ~out_rimask_750; // @[RegisterRouter.scala:87:24] wire _out_T_7430 = ~out_wimask_750; // @[RegisterRouter.scala:87:24] wire _out_T_7431 = ~out_romask_750; // @[RegisterRouter.scala:87:24] wire _out_T_7432 = ~out_womask_750; // @[RegisterRouter.scala:87:24] wire out_rimask_751 = \|_out_rimask_T_751; // @[RegisterRouter.scala:87:24] wire out_wimask_751 = &_out_wimask_T_751; // @[RegisterRouter.scala:87:24] wire out_romask_751 = \|_out_romask_T_751; // @[RegisterRouter.scala:87:24] wire out_womask_751 = &_out_womask_T_751; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_751 = out_rivalid_1_605 & out_rimask_751; // @[RegisterRouter.scala:87:24] wire _out_T_7436 = out_f_rivalid_751; // @[RegisterRouter.scala:87:24] wire out_f_roready_751 = out_roready_1_605 & out_romask_751; // @[RegisterRouter.scala:87:24] wire _out_T_7437 = out_f_roready_751; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_751 = out_wivalid_1_605 & out_wimask_751; // @[RegisterRouter.scala:87:24] wire out_f_woready_751 = out_woready_1_605 & out_womask_751; // @[RegisterRouter.scala:87:24] wire _out_T_7438 = ~out_rimask_751; // @[RegisterRouter.scala:87:24] wire _out_T_7439 = ~out_wimask_751; // @[RegisterRouter.scala:87:24] wire _out_T_7440 = ~out_romask_751; // @[RegisterRouter.scala:87:24] wire _out_T_7441 = ~out_womask_751; // @[RegisterRouter.scala:87:24] wire out_rimask_752 = \|_out_rimask_T_752; // @[RegisterRouter.scala:87:24] wire out_wimask_752 = &_out_wimask_T_752; // @[RegisterRouter.scala:87:24] wire out_romask_752 = \|_out_romask_T_752; // @[RegisterRouter.scala:87:24] wire out_womask_752 = &_out_womask_T_752; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_752 = out_rivalid_1_606 & out_rimask_752; // @[RegisterRouter.scala:87:24] wire _out_T_7445 = out_f_rivalid_752; // @[RegisterRouter.scala:87:24] wire out_f_roready_752 = out_roready_1_606 & out_romask_752; // @[RegisterRouter.scala:87:24] wire _out_T_7446 = out_f_roready_752; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_752 = out_wivalid_1_606 & out_wimask_752; // @[RegisterRouter.scala:87:24] wire out_f_woready_752 = out_woready_1_606 & out_womask_752; // @[RegisterRouter.scala:87:24] wire _out_T_7447 = ~out_rimask_752; // @[RegisterRouter.scala:87:24] wire _out_T_7448 = ~out_wimask_752; // @[RegisterRouter.scala:87:24] wire _out_T_7449 = ~out_romask_752; // @[RegisterRouter.scala:87:24] wire _out_T_7450 = ~out_womask_752; // @[RegisterRouter.scala:87:24] wire out_rimask_753 = \|_out_rimask_T_753; // @[RegisterRouter.scala:87:24] wire out_wimask_753 = &_out_wimask_T_753; // @[RegisterRouter.scala:87:24] wire out_romask_753 = \|_out_romask_T_753; // @[RegisterRouter.scala:87:24] wire out_womask_753 = &_out_womask_T_753; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_753 = out_rivalid_1_607 & out_rimask_753; // @[RegisterRouter.scala:87:24] wire _out_T_7454 = out_f_rivalid_753; // @[RegisterRouter.scala:87:24] wire out_f_roready_753 = out_roready_1_607 & out_romask_753; // @[RegisterRouter.scala:87:24] wire _out_T_7455 = out_f_roready_753; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_753 = out_wivalid_1_607 & out_wimask_753; // @[RegisterRouter.scala:87:24] wire out_f_woready_753 = out_woready_1_607 & out_womask_753; // @[RegisterRouter.scala:87:24] wire _out_T_7456 = ~out_rimask_753; // @[RegisterRouter.scala:87:24] wire _out_T_7457 = ~out_wimask_753; // @[RegisterRouter.scala:87:24] wire _out_T_7458 = ~out_romask_753; // @[RegisterRouter.scala:87:24] wire _out_T_7459 = ~out_womask_753; // @[RegisterRouter.scala:87:24] wire out_rimask_754 = \|_out_rimask_T_754; // @[RegisterRouter.scala:87:24] wire out_wimask_754 = &_out_wimask_T_754; // @[RegisterRouter.scala:87:24] wire out_romask_754 = \|_out_romask_T_754; // @[RegisterRouter.scala:87:24] wire out_womask_754 = &_out_womask_T_754; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_754 = out_rivalid_1_608 & out_rimask_754; // @[RegisterRouter.scala:87:24] wire _out_T_7463 = out_f_rivalid_754; // @[RegisterRouter.scala:87:24] wire out_f_roready_754 = out_roready_1_608 & out_romask_754; // @[RegisterRouter.scala:87:24] wire _out_T_7464 = out_f_roready_754; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_754 = out_wivalid_1_608 & out_wimask_754; // @[RegisterRouter.scala:87:24] wire out_f_woready_754 = out_woready_1_608 & out_womask_754; // @[RegisterRouter.scala:87:24] wire _out_T_7465 = ~out_rimask_754; // @[RegisterRouter.scala:87:24] wire _out_T_7466 = ~out_wimask_754; // @[RegisterRouter.scala:87:24] wire _out_T_7467 = ~out_romask_754; // @[RegisterRouter.scala:87:24] wire _out_T_7468 = ~out_womask_754; // @[RegisterRouter.scala:87:24] wire out_rimask_755 = \|_out_rimask_T_755; // @[RegisterRouter.scala:87:24] wire out_wimask_755 = &_out_wimask_T_755; // @[RegisterRouter.scala:87:24] wire out_romask_755 = \|_out_romask_T_755; // @[RegisterRouter.scala:87:24] wire out_womask_755 = &_out_womask_T_755; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_755 = out_rivalid_1_609 & out_rimask_755; // @[RegisterRouter.scala:87:24] wire _out_T_7472 = out_f_rivalid_755; // @[RegisterRouter.scala:87:24] wire out_f_roready_755 = out_roready_1_609 & out_romask_755; // @[RegisterRouter.scala:87:24] wire _out_T_7473 = out_f_roready_755; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_755 = out_wivalid_1_609 & out_wimask_755; // @[RegisterRouter.scala:87:24] wire out_f_woready_755 = out_woready_1_609 & out_womask_755; // @[RegisterRouter.scala:87:24] wire _out_T_7474 = ~out_rimask_755; // @[RegisterRouter.scala:87:24] wire _out_T_7475 = ~out_wimask_755; // @[RegisterRouter.scala:87:24] wire _out_T_7476 = ~out_romask_755; // @[RegisterRouter.scala:87:24] wire _out_T_7477 = ~out_womask_755; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7479 = _out_T_7478; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_642 = _out_T_7479; // @[RegisterRouter.scala:87:24] wire out_rimask_756 = \|_out_rimask_T_756; // @[RegisterRouter.scala:87:24] wire out_wimask_756 = &_out_wimask_T_756; // @[RegisterRouter.scala:87:24] wire out_romask_756 = \|_out_romask_T_756; // @[RegisterRouter.scala:87:24] wire out_womask_756 = &_out_womask_T_756; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_756 = out_rivalid_1_610 & out_rimask_756; // @[RegisterRouter.scala:87:24] wire _out_T_7481 = out_f_rivalid_756; // @[RegisterRouter.scala:87:24] wire out_f_roready_756 = out_roready_1_610 & out_romask_756; // @[RegisterRouter.scala:87:24] wire _out_T_7482 = out_f_roready_756; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_756 = out_wivalid_1_610 & out_wimask_756; // @[RegisterRouter.scala:87:24] wire out_f_woready_756 = out_woready_1_610 & out_womask_756; // @[RegisterRouter.scala:87:24] wire _out_T_7483 = ~out_rimask_756; // @[RegisterRouter.scala:87:24] wire _out_T_7484 = ~out_wimask_756; // @[RegisterRouter.scala:87:24] wire _out_T_7485 = ~out_romask_756; // @[RegisterRouter.scala:87:24] wire _out_T_7486 = ~out_womask_756; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_642 = {hi_130, flags_0_go, _out_prepend_T_642}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7487 = out_prepend_642; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7488 = _out_T_7487; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_643 = _out_T_7488; // @[RegisterRouter.scala:87:24] wire out_rimask_757 = \|_out_rimask_T_757; // @[RegisterRouter.scala:87:24] wire out_wimask_757 = &_out_wimask_T_757; // @[RegisterRouter.scala:87:24] wire out_romask_757 = \|_out_romask_T_757; // @[RegisterRouter.scala:87:24] wire out_womask_757 = &_out_womask_T_757; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_757 = out_rivalid_1_611 & out_rimask_757; // @[RegisterRouter.scala:87:24] wire _out_T_7490 = out_f_rivalid_757; // @[RegisterRouter.scala:87:24] wire out_f_roready_757 = out_roready_1_611 & out_romask_757; // @[RegisterRouter.scala:87:24] wire _out_T_7491 = out_f_roready_757; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_757 = out_wivalid_1_611 & out_wimask_757; // @[RegisterRouter.scala:87:24] wire out_f_woready_757 = out_woready_1_611 & out_womask_757; // @[RegisterRouter.scala:87:24] wire _out_T_7492 = ~out_rimask_757; // @[RegisterRouter.scala:87:24] wire _out_T_7493 = ~out_wimask_757; // @[RegisterRouter.scala:87:24] wire _out_T_7494 = ~out_romask_757; // @[RegisterRouter.scala:87:24] wire _out_T_7495 = ~out_womask_757; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_643 = {hi_131, flags_0_go, _out_prepend_T_643}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7496 = out_prepend_643; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7497 = _out_T_7496; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_644 = _out_T_7497; // @[RegisterRouter.scala:87:24] wire out_rimask_758 = \|_out_rimask_T_758; // @[RegisterRouter.scala:87:24] wire out_wimask_758 = &_out_wimask_T_758; // @[RegisterRouter.scala:87:24] wire out_romask_758 = \|_out_romask_T_758; // @[RegisterRouter.scala:87:24] wire out_womask_758 = &_out_womask_T_758; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_758 = out_rivalid_1_612 & out_rimask_758; // @[RegisterRouter.scala:87:24] wire _out_T_7499 = out_f_rivalid_758; // @[RegisterRouter.scala:87:24] wire out_f_roready_758 = out_roready_1_612 & out_romask_758; // @[RegisterRouter.scala:87:24] wire _out_T_7500 = out_f_roready_758; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_758 = out_wivalid_1_612 & out_wimask_758; // @[RegisterRouter.scala:87:24] wire out_f_woready_758 = out_woready_1_612 & out_womask_758; // @[RegisterRouter.scala:87:24] wire _out_T_7501 = ~out_rimask_758; // @[RegisterRouter.scala:87:24] wire _out_T_7502 = ~out_wimask_758; // @[RegisterRouter.scala:87:24] wire _out_T_7503 = ~out_romask_758; // @[RegisterRouter.scala:87:24] wire _out_T_7504 = ~out_womask_758; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_644 = {hi_132, flags_0_go, _out_prepend_T_644}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7505 = out_prepend_644; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7506 = _out_T_7505; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_645 = _out_T_7506; // @[RegisterRouter.scala:87:24] wire out_rimask_759 = \|_out_rimask_T_759; // @[RegisterRouter.scala:87:24] wire out_wimask_759 = &_out_wimask_T_759; // @[RegisterRouter.scala:87:24] wire out_romask_759 = \|_out_romask_T_759; // @[RegisterRouter.scala:87:24] wire out_womask_759 = &_out_womask_T_759; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_759 = out_rivalid_1_613 & out_rimask_759; // @[RegisterRouter.scala:87:24] wire _out_T_7508 = out_f_rivalid_759; // @[RegisterRouter.scala:87:24] wire out_f_roready_759 = out_roready_1_613 & out_romask_759; // @[RegisterRouter.scala:87:24] wire _out_T_7509 = out_f_roready_759; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_759 = out_wivalid_1_613 & out_wimask_759; // @[RegisterRouter.scala:87:24] wire out_f_woready_759 = out_woready_1_613 & out_womask_759; // @[RegisterRouter.scala:87:24] wire _out_T_7510 = ~out_rimask_759; // @[RegisterRouter.scala:87:24] wire _out_T_7511 = ~out_wimask_759; // @[RegisterRouter.scala:87:24] wire _out_T_7512 = ~out_romask_759; // @[RegisterRouter.scala:87:24] wire _out_T_7513 = ~out_womask_759; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_645 = {hi_133, flags_0_go, _out_prepend_T_645}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7514 = out_prepend_645; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7515 = _out_T_7514; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_646 = _out_T_7515; // @[RegisterRouter.scala:87:24] wire out_rimask_760 = \|_out_rimask_T_760; // @[RegisterRouter.scala:87:24] wire out_wimask_760 = &_out_wimask_T_760; // @[RegisterRouter.scala:87:24] wire out_romask_760 = \|_out_romask_T_760; // @[RegisterRouter.scala:87:24] wire out_womask_760 = &_out_womask_T_760; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_760 = out_rivalid_1_614 & out_rimask_760; // @[RegisterRouter.scala:87:24] wire _out_T_7517 = out_f_rivalid_760; // @[RegisterRouter.scala:87:24] wire out_f_roready_760 = out_roready_1_614 & out_romask_760; // @[RegisterRouter.scala:87:24] wire _out_T_7518 = out_f_roready_760; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_760 = out_wivalid_1_614 & out_wimask_760; // @[RegisterRouter.scala:87:24] wire out_f_woready_760 = out_woready_1_614 & out_womask_760; // @[RegisterRouter.scala:87:24] wire _out_T_7519 = ~out_rimask_760; // @[RegisterRouter.scala:87:24] wire _out_T_7520 = ~out_wimask_760; // @[RegisterRouter.scala:87:24] wire _out_T_7521 = ~out_romask_760; // @[RegisterRouter.scala:87:24] wire _out_T_7522 = ~out_womask_760; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_646 = {hi_134, flags_0_go, _out_prepend_T_646}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7523 = out_prepend_646; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7524 = _out_T_7523; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_647 = _out_T_7524; // @[RegisterRouter.scala:87:24] wire out_rimask_761 = \|_out_rimask_T_761; // @[RegisterRouter.scala:87:24] wire out_wimask_761 = &_out_wimask_T_761; // @[RegisterRouter.scala:87:24] wire out_romask_761 = \|_out_romask_T_761; // @[RegisterRouter.scala:87:24] wire out_womask_761 = &_out_womask_T_761; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_761 = out_rivalid_1_615 & out_rimask_761; // @[RegisterRouter.scala:87:24] wire _out_T_7526 = out_f_rivalid_761; // @[RegisterRouter.scala:87:24] wire out_f_roready_761 = out_roready_1_615 & out_romask_761; // @[RegisterRouter.scala:87:24] wire _out_T_7527 = out_f_roready_761; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_761 = out_wivalid_1_615 & out_wimask_761; // @[RegisterRouter.scala:87:24] wire out_f_woready_761 = out_woready_1_615 & out_womask_761; // @[RegisterRouter.scala:87:24] wire _out_T_7528 = ~out_rimask_761; // @[RegisterRouter.scala:87:24] wire _out_T_7529 = ~out_wimask_761; // @[RegisterRouter.scala:87:24] wire _out_T_7530 = ~out_romask_761; // @[RegisterRouter.scala:87:24] wire _out_T_7531 = ~out_womask_761; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_647 = {hi_135, flags_0_go, _out_prepend_T_647}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7532 = out_prepend_647; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7533 = _out_T_7532; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_648 = _out_T_7533; // @[RegisterRouter.scala:87:24] wire out_rimask_762 = \|_out_rimask_T_762; // @[RegisterRouter.scala:87:24] wire out_wimask_762 = &_out_wimask_T_762; // @[RegisterRouter.scala:87:24] wire out_romask_762 = \|_out_romask_T_762; // @[RegisterRouter.scala:87:24] wire out_womask_762 = &_out_womask_T_762; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_762 = out_rivalid_1_616 & out_rimask_762; // @[RegisterRouter.scala:87:24] wire _out_T_7535 = out_f_rivalid_762; // @[RegisterRouter.scala:87:24] wire out_f_roready_762 = out_roready_1_616 & out_romask_762; // @[RegisterRouter.scala:87:24] wire _out_T_7536 = out_f_roready_762; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_762 = out_wivalid_1_616 & out_wimask_762; // @[RegisterRouter.scala:87:24] wire out_f_woready_762 = out_woready_1_616 & out_womask_762; // @[RegisterRouter.scala:87:24] wire _out_T_7537 = ~out_rimask_762; // @[RegisterRouter.scala:87:24] wire _out_T_7538 = ~out_wimask_762; // @[RegisterRouter.scala:87:24] wire _out_T_7539 = ~out_romask_762; // @[RegisterRouter.scala:87:24] wire _out_T_7540 = ~out_womask_762; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_648 = {hi_136, flags_0_go, _out_prepend_T_648}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7541 = out_prepend_648; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7542 = _out_T_7541; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_144 = _out_T_7542; // @[MuxLiteral.scala:49:48] wire out_rimask_763 = \|_out_rimask_T_763; // @[RegisterRouter.scala:87:24] wire out_wimask_763 = &_out_wimask_T_763; // @[RegisterRouter.scala:87:24] wire out_romask_763 = \|_out_romask_T_763; // @[RegisterRouter.scala:87:24] wire out_womask_763 = &_out_womask_T_763; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_763 = out_rivalid_1_617 & out_rimask_763; // @[RegisterRouter.scala:87:24] wire _out_T_7544 = out_f_rivalid_763; // @[RegisterRouter.scala:87:24] wire out_f_roready_763 = out_roready_1_617 & out_romask_763; // @[RegisterRouter.scala:87:24] wire _out_T_7545 = out_f_roready_763; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_763 = out_wivalid_1_617 & out_wimask_763; // @[RegisterRouter.scala:87:24] wire out_f_woready_763 = out_woready_1_617 & out_womask_763; // @[RegisterRouter.scala:87:24] wire _out_T_7546 = ~out_rimask_763; // @[RegisterRouter.scala:87:24] wire _out_T_7547 = ~out_wimask_763; // @[RegisterRouter.scala:87:24] wire _out_T_7548 = ~out_romask_763; // @[RegisterRouter.scala:87:24] wire _out_T_7549 = ~out_womask_763; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7551 = _out_T_7550; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_649 = _out_T_7551; // @[RegisterRouter.scala:87:24] wire out_rimask_764 = \|_out_rimask_T_764; // @[RegisterRouter.scala:87:24] wire out_wimask_764 = &_out_wimask_T_764; // @[RegisterRouter.scala:87:24] wire out_romask_764 = \|_out_romask_T_764; // @[RegisterRouter.scala:87:24] wire out_womask_764 = &_out_womask_T_764; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_764 = out_rivalid_1_618 & out_rimask_764; // @[RegisterRouter.scala:87:24] wire _out_T_7553 = out_f_rivalid_764; // @[RegisterRouter.scala:87:24] wire out_f_roready_764 = out_roready_1_618 & out_romask_764; // @[RegisterRouter.scala:87:24] wire _out_T_7554 = out_f_roready_764; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_764 = out_wivalid_1_618 & out_wimask_764; // @[RegisterRouter.scala:87:24] wire out_f_woready_764 = out_woready_1_618 & out_womask_764; // @[RegisterRouter.scala:87:24] wire _out_T_7555 = ~out_rimask_764; // @[RegisterRouter.scala:87:24] wire _out_T_7556 = ~out_wimask_764; // @[RegisterRouter.scala:87:24] wire _out_T_7557 = ~out_romask_764; // @[RegisterRouter.scala:87:24] wire _out_T_7558 = ~out_womask_764; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_649 = {hi_866, flags_0_go, _out_prepend_T_649}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7559 = out_prepend_649; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7560 = _out_T_7559; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_650 = _out_T_7560; // @[RegisterRouter.scala:87:24] wire out_rimask_765 = \|_out_rimask_T_765; // @[RegisterRouter.scala:87:24] wire out_wimask_765 = &_out_wimask_T_765; // @[RegisterRouter.scala:87:24] wire out_romask_765 = \|_out_romask_T_765; // @[RegisterRouter.scala:87:24] wire out_womask_765 = &_out_womask_T_765; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_765 = out_rivalid_1_619 & out_rimask_765; // @[RegisterRouter.scala:87:24] wire _out_T_7562 = out_f_rivalid_765; // @[RegisterRouter.scala:87:24] wire out_f_roready_765 = out_roready_1_619 & out_romask_765; // @[RegisterRouter.scala:87:24] wire _out_T_7563 = out_f_roready_765; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_765 = out_wivalid_1_619 & out_wimask_765; // @[RegisterRouter.scala:87:24] wire out_f_woready_765 = out_woready_1_619 & out_womask_765; // @[RegisterRouter.scala:87:24] wire _out_T_7564 = ~out_rimask_765; // @[RegisterRouter.scala:87:24] wire _out_T_7565 = ~out_wimask_765; // @[RegisterRouter.scala:87:24] wire _out_T_7566 = ~out_romask_765; // @[RegisterRouter.scala:87:24] wire _out_T_7567 = ~out_womask_765; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_650 = {hi_867, flags_0_go, _out_prepend_T_650}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7568 = out_prepend_650; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7569 = _out_T_7568; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_651 = _out_T_7569; // @[RegisterRouter.scala:87:24] wire out_rimask_766 = \|_out_rimask_T_766; // @[RegisterRouter.scala:87:24] wire out_wimask_766 = &_out_wimask_T_766; // @[RegisterRouter.scala:87:24] wire out_romask_766 = \|_out_romask_T_766; // @[RegisterRouter.scala:87:24] wire out_womask_766 = &_out_womask_T_766; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_766 = out_rivalid_1_620 & out_rimask_766; // @[RegisterRouter.scala:87:24] wire _out_T_7571 = out_f_rivalid_766; // @[RegisterRouter.scala:87:24] wire out_f_roready_766 = out_roready_1_620 & out_romask_766; // @[RegisterRouter.scala:87:24] wire _out_T_7572 = out_f_roready_766; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_766 = out_wivalid_1_620 & out_wimask_766; // @[RegisterRouter.scala:87:24] wire out_f_woready_766 = out_woready_1_620 & out_womask_766; // @[RegisterRouter.scala:87:24] wire _out_T_7573 = ~out_rimask_766; // @[RegisterRouter.scala:87:24] wire _out_T_7574 = ~out_wimask_766; // @[RegisterRouter.scala:87:24] wire _out_T_7575 = ~out_romask_766; // @[RegisterRouter.scala:87:24] wire _out_T_7576 = ~out_womask_766; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_651 = {hi_868, flags_0_go, _out_prepend_T_651}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7577 = out_prepend_651; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7578 = _out_T_7577; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_652 = _out_T_7578; // @[RegisterRouter.scala:87:24] wire out_rimask_767 = \|_out_rimask_T_767; // @[RegisterRouter.scala:87:24] wire out_wimask_767 = &_out_wimask_T_767; // @[RegisterRouter.scala:87:24] wire out_romask_767 = \|_out_romask_T_767; // @[RegisterRouter.scala:87:24] wire out_womask_767 = &_out_womask_T_767; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_767 = out_rivalid_1_621 & out_rimask_767; // @[RegisterRouter.scala:87:24] wire _out_T_7580 = out_f_rivalid_767; // @[RegisterRouter.scala:87:24] wire out_f_roready_767 = out_roready_1_621 & out_romask_767; // @[RegisterRouter.scala:87:24] wire _out_T_7581 = out_f_roready_767; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_767 = out_wivalid_1_621 & out_wimask_767; // @[RegisterRouter.scala:87:24] wire out_f_woready_767 = out_woready_1_621 & out_womask_767; // @[RegisterRouter.scala:87:24] wire _out_T_7582 = ~out_rimask_767; // @[RegisterRouter.scala:87:24] wire _out_T_7583 = ~out_wimask_767; // @[RegisterRouter.scala:87:24] wire _out_T_7584 = ~out_romask_767; // @[RegisterRouter.scala:87:24] wire _out_T_7585 = ~out_womask_767; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_652 = {hi_869, flags_0_go, _out_prepend_T_652}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7586 = out_prepend_652; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7587 = _out_T_7586; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_653 = _out_T_7587; // @[RegisterRouter.scala:87:24] wire out_rimask_768 = \|_out_rimask_T_768; // @[RegisterRouter.scala:87:24] wire out_wimask_768 = &_out_wimask_T_768; // @[RegisterRouter.scala:87:24] wire out_romask_768 = \|_out_romask_T_768; // @[RegisterRouter.scala:87:24] wire out_womask_768 = &_out_womask_T_768; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_768 = out_rivalid_1_622 & out_rimask_768; // @[RegisterRouter.scala:87:24] wire _out_T_7589 = out_f_rivalid_768; // @[RegisterRouter.scala:87:24] wire out_f_roready_768 = out_roready_1_622 & out_romask_768; // @[RegisterRouter.scala:87:24] wire _out_T_7590 = out_f_roready_768; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_768 = out_wivalid_1_622 & out_wimask_768; // @[RegisterRouter.scala:87:24] wire out_f_woready_768 = out_woready_1_622 & out_womask_768; // @[RegisterRouter.scala:87:24] wire _out_T_7591 = ~out_rimask_768; // @[RegisterRouter.scala:87:24] wire _out_T_7592 = ~out_wimask_768; // @[RegisterRouter.scala:87:24] wire _out_T_7593 = ~out_romask_768; // @[RegisterRouter.scala:87:24] wire _out_T_7594 = ~out_womask_768; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_653 = {hi_870, flags_0_go, _out_prepend_T_653}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7595 = out_prepend_653; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7596 = _out_T_7595; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_654 = _out_T_7596; // @[RegisterRouter.scala:87:24] wire out_rimask_769 = \|_out_rimask_T_769; // @[RegisterRouter.scala:87:24] wire out_wimask_769 = &_out_wimask_T_769; // @[RegisterRouter.scala:87:24] wire out_romask_769 = \|_out_romask_T_769; // @[RegisterRouter.scala:87:24] wire out_womask_769 = &_out_womask_T_769; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_769 = out_rivalid_1_623 & out_rimask_769; // @[RegisterRouter.scala:87:24] wire _out_T_7598 = out_f_rivalid_769; // @[RegisterRouter.scala:87:24] wire out_f_roready_769 = out_roready_1_623 & out_romask_769; // @[RegisterRouter.scala:87:24] wire _out_T_7599 = out_f_roready_769; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_769 = out_wivalid_1_623 & out_wimask_769; // @[RegisterRouter.scala:87:24] wire out_f_woready_769 = out_woready_1_623 & out_womask_769; // @[RegisterRouter.scala:87:24] wire _out_T_7600 = ~out_rimask_769; // @[RegisterRouter.scala:87:24] wire _out_T_7601 = ~out_wimask_769; // @[RegisterRouter.scala:87:24] wire _out_T_7602 = ~out_romask_769; // @[RegisterRouter.scala:87:24] wire _out_T_7603 = ~out_womask_769; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_654 = {hi_871, flags_0_go, _out_prepend_T_654}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7604 = out_prepend_654; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7605 = _out_T_7604; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_655 = _out_T_7605; // @[RegisterRouter.scala:87:24] wire out_rimask_770 = \|_out_rimask_T_770; // @[RegisterRouter.scala:87:24] wire out_wimask_770 = &_out_wimask_T_770; // @[RegisterRouter.scala:87:24] wire out_romask_770 = \|_out_romask_T_770; // @[RegisterRouter.scala:87:24] wire out_womask_770 = &_out_womask_T_770; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_770 = out_rivalid_1_624 & out_rimask_770; // @[RegisterRouter.scala:87:24] wire _out_T_7607 = out_f_rivalid_770; // @[RegisterRouter.scala:87:24] wire out_f_roready_770 = out_roready_1_624 & out_romask_770; // @[RegisterRouter.scala:87:24] wire _out_T_7608 = out_f_roready_770; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_770 = out_wivalid_1_624 & out_wimask_770; // @[RegisterRouter.scala:87:24] wire out_f_woready_770 = out_woready_1_624 & out_womask_770; // @[RegisterRouter.scala:87:24] wire _out_T_7609 = ~out_rimask_770; // @[RegisterRouter.scala:87:24] wire _out_T_7610 = ~out_wimask_770; // @[RegisterRouter.scala:87:24] wire _out_T_7611 = ~out_romask_770; // @[RegisterRouter.scala:87:24] wire _out_T_7612 = ~out_womask_770; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_655 = {hi_872, flags_0_go, _out_prepend_T_655}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7613 = out_prepend_655; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7614 = _out_T_7613; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_236 = _out_T_7614; // @[MuxLiteral.scala:49:48] wire out_rimask_771 = \|_out_rimask_T_771; // @[RegisterRouter.scala:87:24] wire out_wimask_771 = &_out_wimask_T_771; // @[RegisterRouter.scala:87:24] wire out_romask_771 = \|_out_romask_T_771; // @[RegisterRouter.scala:87:24] wire out_womask_771 = &_out_womask_T_771; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_771 = out_rivalid_1_625 & out_rimask_771; // @[RegisterRouter.scala:87:24] wire _out_T_7616 = out_f_rivalid_771; // @[RegisterRouter.scala:87:24] wire out_f_roready_771 = out_roready_1_625 & out_romask_771; // @[RegisterRouter.scala:87:24] wire _out_T_7617 = out_f_roready_771; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_771 = out_wivalid_1_625 & out_wimask_771; // @[RegisterRouter.scala:87:24] wire out_f_woready_771 = out_woready_1_625 & out_womask_771; // @[RegisterRouter.scala:87:24] wire _out_T_7618 = ~out_rimask_771; // @[RegisterRouter.scala:87:24] wire _out_T_7619 = ~out_wimask_771; // @[RegisterRouter.scala:87:24] wire _out_T_7620 = ~out_romask_771; // @[RegisterRouter.scala:87:24] wire _out_T_7621 = ~out_womask_771; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7623 = _out_T_7622; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_656 = _out_T_7623; // @[RegisterRouter.scala:87:24] wire out_rimask_772 = \|_out_rimask_T_772; // @[RegisterRouter.scala:87:24] wire out_wimask_772 = &_out_wimask_T_772; // @[RegisterRouter.scala:87:24] wire out_romask_772 = \|_out_romask_T_772; // @[RegisterRouter.scala:87:24] wire out_womask_772 = &_out_womask_T_772; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_772 = out_rivalid_1_626 & out_rimask_772; // @[RegisterRouter.scala:87:24] wire _out_T_7625 = out_f_rivalid_772; // @[RegisterRouter.scala:87:24] wire out_f_roready_772 = out_roready_1_626 & out_romask_772; // @[RegisterRouter.scala:87:24] wire _out_T_7626 = out_f_roready_772; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_772 = out_wivalid_1_626 & out_wimask_772; // @[RegisterRouter.scala:87:24] wire out_f_woready_772 = out_woready_1_626 & out_womask_772; // @[RegisterRouter.scala:87:24] wire _out_T_7627 = ~out_rimask_772; // @[RegisterRouter.scala:87:24] wire _out_T_7628 = ~out_wimask_772; // @[RegisterRouter.scala:87:24] wire _out_T_7629 = ~out_romask_772; // @[RegisterRouter.scala:87:24] wire _out_T_7630 = ~out_womask_772; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_656 = {hi_426, flags_0_go, _out_prepend_T_656}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7631 = out_prepend_656; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7632 = _out_T_7631; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_657 = _out_T_7632; // @[RegisterRouter.scala:87:24] wire out_rimask_773 = \|_out_rimask_T_773; // @[RegisterRouter.scala:87:24] wire out_wimask_773 = &_out_wimask_T_773; // @[RegisterRouter.scala:87:24] wire out_romask_773 = \|_out_romask_T_773; // @[RegisterRouter.scala:87:24] wire out_womask_773 = &_out_womask_T_773; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_773 = out_rivalid_1_627 & out_rimask_773; // @[RegisterRouter.scala:87:24] wire _out_T_7634 = out_f_rivalid_773; // @[RegisterRouter.scala:87:24] wire out_f_roready_773 = out_roready_1_627 & out_romask_773; // @[RegisterRouter.scala:87:24] wire _out_T_7635 = out_f_roready_773; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_773 = out_wivalid_1_627 & out_wimask_773; // @[RegisterRouter.scala:87:24] wire out_f_woready_773 = out_woready_1_627 & out_womask_773; // @[RegisterRouter.scala:87:24] wire _out_T_7636 = ~out_rimask_773; // @[RegisterRouter.scala:87:24] wire _out_T_7637 = ~out_wimask_773; // @[RegisterRouter.scala:87:24] wire _out_T_7638 = ~out_romask_773; // @[RegisterRouter.scala:87:24] wire _out_T_7639 = ~out_womask_773; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_657 = {hi_427, flags_0_go, _out_prepend_T_657}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7640 = out_prepend_657; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7641 = _out_T_7640; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_658 = _out_T_7641; // @[RegisterRouter.scala:87:24] wire out_rimask_774 = \|_out_rimask_T_774; // @[RegisterRouter.scala:87:24] wire out_wimask_774 = &_out_wimask_T_774; // @[RegisterRouter.scala:87:24] wire out_romask_774 = \|_out_romask_T_774; // @[RegisterRouter.scala:87:24] wire out_womask_774 = &_out_womask_T_774; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_774 = out_rivalid_1_628 & out_rimask_774; // @[RegisterRouter.scala:87:24] wire _out_T_7643 = out_f_rivalid_774; // @[RegisterRouter.scala:87:24] wire out_f_roready_774 = out_roready_1_628 & out_romask_774; // @[RegisterRouter.scala:87:24] wire _out_T_7644 = out_f_roready_774; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_774 = out_wivalid_1_628 & out_wimask_774; // @[RegisterRouter.scala:87:24] wire out_f_woready_774 = out_woready_1_628 & out_womask_774; // @[RegisterRouter.scala:87:24] wire _out_T_7645 = ~out_rimask_774; // @[RegisterRouter.scala:87:24] wire _out_T_7646 = ~out_wimask_774; // @[RegisterRouter.scala:87:24] wire _out_T_7647 = ~out_romask_774; // @[RegisterRouter.scala:87:24] wire _out_T_7648 = ~out_womask_774; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_658 = {hi_428, flags_0_go, _out_prepend_T_658}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7649 = out_prepend_658; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7650 = _out_T_7649; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_659 = _out_T_7650; // @[RegisterRouter.scala:87:24] wire out_rimask_775 = \|_out_rimask_T_775; // @[RegisterRouter.scala:87:24] wire out_wimask_775 = &_out_wimask_T_775; // @[RegisterRouter.scala:87:24] wire out_romask_775 = \|_out_romask_T_775; // @[RegisterRouter.scala:87:24] wire out_womask_775 = &_out_womask_T_775; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_775 = out_rivalid_1_629 & out_rimask_775; // @[RegisterRouter.scala:87:24] wire _out_T_7652 = out_f_rivalid_775; // @[RegisterRouter.scala:87:24] wire out_f_roready_775 = out_roready_1_629 & out_romask_775; // @[RegisterRouter.scala:87:24] wire _out_T_7653 = out_f_roready_775; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_775 = out_wivalid_1_629 & out_wimask_775; // @[RegisterRouter.scala:87:24] wire out_f_woready_775 = out_woready_1_629 & out_womask_775; // @[RegisterRouter.scala:87:24] wire _out_T_7654 = ~out_rimask_775; // @[RegisterRouter.scala:87:24] wire _out_T_7655 = ~out_wimask_775; // @[RegisterRouter.scala:87:24] wire _out_T_7656 = ~out_romask_775; // @[RegisterRouter.scala:87:24] wire _out_T_7657 = ~out_womask_775; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_659 = {hi_429, flags_0_go, _out_prepend_T_659}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7658 = out_prepend_659; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7659 = _out_T_7658; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_660 = _out_T_7659; // @[RegisterRouter.scala:87:24] wire out_rimask_776 = \|_out_rimask_T_776; // @[RegisterRouter.scala:87:24] wire out_wimask_776 = &_out_wimask_T_776; // @[RegisterRouter.scala:87:24] wire out_romask_776 = \|_out_romask_T_776; // @[RegisterRouter.scala:87:24] wire out_womask_776 = &_out_womask_T_776; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_776 = out_rivalid_1_630 & out_rimask_776; // @[RegisterRouter.scala:87:24] wire _out_T_7661 = out_f_rivalid_776; // @[RegisterRouter.scala:87:24] wire out_f_roready_776 = out_roready_1_630 & out_romask_776; // @[RegisterRouter.scala:87:24] wire _out_T_7662 = out_f_roready_776; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_776 = out_wivalid_1_630 & out_wimask_776; // @[RegisterRouter.scala:87:24] wire out_f_woready_776 = out_woready_1_630 & out_womask_776; // @[RegisterRouter.scala:87:24] wire _out_T_7663 = ~out_rimask_776; // @[RegisterRouter.scala:87:24] wire _out_T_7664 = ~out_wimask_776; // @[RegisterRouter.scala:87:24] wire _out_T_7665 = ~out_romask_776; // @[RegisterRouter.scala:87:24] wire _out_T_7666 = ~out_womask_776; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_660 = {hi_430, flags_0_go, _out_prepend_T_660}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7667 = out_prepend_660; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7668 = _out_T_7667; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_661 = _out_T_7668; // @[RegisterRouter.scala:87:24] wire out_rimask_777 = \|_out_rimask_T_777; // @[RegisterRouter.scala:87:24] wire out_wimask_777 = &_out_wimask_T_777; // @[RegisterRouter.scala:87:24] wire out_romask_777 = \|_out_romask_T_777; // @[RegisterRouter.scala:87:24] wire out_womask_777 = &_out_womask_T_777; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_777 = out_rivalid_1_631 & out_rimask_777; // @[RegisterRouter.scala:87:24] wire _out_T_7670 = out_f_rivalid_777; // @[RegisterRouter.scala:87:24] wire out_f_roready_777 = out_roready_1_631 & out_romask_777; // @[RegisterRouter.scala:87:24] wire _out_T_7671 = out_f_roready_777; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_777 = out_wivalid_1_631 & out_wimask_777; // @[RegisterRouter.scala:87:24] wire out_f_woready_777 = out_woready_1_631 & out_womask_777; // @[RegisterRouter.scala:87:24] wire _out_T_7672 = ~out_rimask_777; // @[RegisterRouter.scala:87:24] wire _out_T_7673 = ~out_wimask_777; // @[RegisterRouter.scala:87:24] wire _out_T_7674 = ~out_romask_777; // @[RegisterRouter.scala:87:24] wire _out_T_7675 = ~out_womask_777; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_661 = {hi_431, flags_0_go, _out_prepend_T_661}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7676 = out_prepend_661; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7677 = _out_T_7676; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_662 = _out_T_7677; // @[RegisterRouter.scala:87:24] wire out_rimask_778 = \|_out_rimask_T_778; // @[RegisterRouter.scala:87:24] wire out_wimask_778 = &_out_wimask_T_778; // @[RegisterRouter.scala:87:24] wire out_romask_778 = \|_out_romask_T_778; // @[RegisterRouter.scala:87:24] wire out_womask_778 = &_out_womask_T_778; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_778 = out_rivalid_1_632 & out_rimask_778; // @[RegisterRouter.scala:87:24] wire _out_T_7679 = out_f_rivalid_778; // @[RegisterRouter.scala:87:24] wire out_f_roready_778 = out_roready_1_632 & out_romask_778; // @[RegisterRouter.scala:87:24] wire _out_T_7680 = out_f_roready_778; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_778 = out_wivalid_1_632 & out_wimask_778; // @[RegisterRouter.scala:87:24] wire out_f_woready_778 = out_woready_1_632 & out_womask_778; // @[RegisterRouter.scala:87:24] wire _out_T_7681 = ~out_rimask_778; // @[RegisterRouter.scala:87:24] wire _out_T_7682 = ~out_wimask_778; // @[RegisterRouter.scala:87:24] wire _out_T_7683 = ~out_romask_778; // @[RegisterRouter.scala:87:24] wire _out_T_7684 = ~out_womask_778; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_662 = {hi_432, flags_0_go, _out_prepend_T_662}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7685 = out_prepend_662; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7686 = _out_T_7685; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_181 = _out_T_7686; // @[MuxLiteral.scala:49:48] wire out_rimask_779 = \|_out_rimask_T_779; // @[RegisterRouter.scala:87:24] wire out_wimask_779 = &_out_wimask_T_779; // @[RegisterRouter.scala:87:24] wire out_romask_779 = \|_out_romask_T_779; // @[RegisterRouter.scala:87:24] wire out_womask_779 = &_out_womask_T_779; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_779 = out_rivalid_1_633 & out_rimask_779; // @[RegisterRouter.scala:87:24] wire _out_T_7688 = out_f_rivalid_779; // @[RegisterRouter.scala:87:24] wire out_f_roready_779 = out_roready_1_633 & out_romask_779; // @[RegisterRouter.scala:87:24] wire _out_T_7689 = out_f_roready_779; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_779 = out_wivalid_1_633 & out_wimask_779; // @[RegisterRouter.scala:87:24] wire out_f_woready_779 = out_woready_1_633 & out_womask_779; // @[RegisterRouter.scala:87:24] wire _out_T_7690 = ~out_rimask_779; // @[RegisterRouter.scala:87:24] wire _out_T_7691 = ~out_wimask_779; // @[RegisterRouter.scala:87:24] wire _out_T_7692 = ~out_romask_779; // @[RegisterRouter.scala:87:24] wire _out_T_7693 = ~out_womask_779; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7695 = _out_T_7694; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_663 = _out_T_7695; // @[RegisterRouter.scala:87:24] wire out_rimask_780 = \|_out_rimask_T_780; // @[RegisterRouter.scala:87:24] wire out_wimask_780 = &_out_wimask_T_780; // @[RegisterRouter.scala:87:24] wire out_romask_780 = \|_out_romask_T_780; // @[RegisterRouter.scala:87:24] wire out_womask_780 = &_out_womask_T_780; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_780 = out_rivalid_1_634 & out_rimask_780; // @[RegisterRouter.scala:87:24] wire _out_T_7697 = out_f_rivalid_780; // @[RegisterRouter.scala:87:24] wire out_f_roready_780 = out_roready_1_634 & out_romask_780; // @[RegisterRouter.scala:87:24] wire _out_T_7698 = out_f_roready_780; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_780 = out_wivalid_1_634 & out_wimask_780; // @[RegisterRouter.scala:87:24] wire out_f_woready_780 = out_woready_1_634 & out_womask_780; // @[RegisterRouter.scala:87:24] wire _out_T_7699 = ~out_rimask_780; // @[RegisterRouter.scala:87:24] wire _out_T_7700 = ~out_wimask_780; // @[RegisterRouter.scala:87:24] wire _out_T_7701 = ~out_romask_780; // @[RegisterRouter.scala:87:24] wire _out_T_7702 = ~out_womask_780; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_663 = {hi_250, flags_0_go, _out_prepend_T_663}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7703 = out_prepend_663; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7704 = _out_T_7703; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_664 = _out_T_7704; // @[RegisterRouter.scala:87:24] wire out_rimask_781 = \|_out_rimask_T_781; // @[RegisterRouter.scala:87:24] wire out_wimask_781 = &_out_wimask_T_781; // @[RegisterRouter.scala:87:24] wire out_romask_781 = \|_out_romask_T_781; // @[RegisterRouter.scala:87:24] wire out_womask_781 = &_out_womask_T_781; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_781 = out_rivalid_1_635 & out_rimask_781; // @[RegisterRouter.scala:87:24] wire _out_T_7706 = out_f_rivalid_781; // @[RegisterRouter.scala:87:24] wire out_f_roready_781 = out_roready_1_635 & out_romask_781; // @[RegisterRouter.scala:87:24] wire _out_T_7707 = out_f_roready_781; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_781 = out_wivalid_1_635 & out_wimask_781; // @[RegisterRouter.scala:87:24] wire out_f_woready_781 = out_woready_1_635 & out_womask_781; // @[RegisterRouter.scala:87:24] wire _out_T_7708 = ~out_rimask_781; // @[RegisterRouter.scala:87:24] wire _out_T_7709 = ~out_wimask_781; // @[RegisterRouter.scala:87:24] wire _out_T_7710 = ~out_romask_781; // @[RegisterRouter.scala:87:24] wire _out_T_7711 = ~out_womask_781; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_664 = {hi_251, flags_0_go, _out_prepend_T_664}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7712 = out_prepend_664; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7713 = _out_T_7712; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_665 = _out_T_7713; // @[RegisterRouter.scala:87:24] wire out_rimask_782 = \|_out_rimask_T_782; // @[RegisterRouter.scala:87:24] wire out_wimask_782 = &_out_wimask_T_782; // @[RegisterRouter.scala:87:24] wire out_romask_782 = \|_out_romask_T_782; // @[RegisterRouter.scala:87:24] wire out_womask_782 = &_out_womask_T_782; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_782 = out_rivalid_1_636 & out_rimask_782; // @[RegisterRouter.scala:87:24] wire _out_T_7715 = out_f_rivalid_782; // @[RegisterRouter.scala:87:24] wire out_f_roready_782 = out_roready_1_636 & out_romask_782; // @[RegisterRouter.scala:87:24] wire _out_T_7716 = out_f_roready_782; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_782 = out_wivalid_1_636 & out_wimask_782; // @[RegisterRouter.scala:87:24] wire out_f_woready_782 = out_woready_1_636 & out_womask_782; // @[RegisterRouter.scala:87:24] wire _out_T_7717 = ~out_rimask_782; // @[RegisterRouter.scala:87:24] wire _out_T_7718 = ~out_wimask_782; // @[RegisterRouter.scala:87:24] wire _out_T_7719 = ~out_romask_782; // @[RegisterRouter.scala:87:24] wire _out_T_7720 = ~out_womask_782; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_665 = {hi_252, flags_0_go, _out_prepend_T_665}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7721 = out_prepend_665; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7722 = _out_T_7721; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_666 = _out_T_7722; // @[RegisterRouter.scala:87:24] wire out_rimask_783 = \|_out_rimask_T_783; // @[RegisterRouter.scala:87:24] wire out_wimask_783 = &_out_wimask_T_783; // @[RegisterRouter.scala:87:24] wire out_romask_783 = \|_out_romask_T_783; // @[RegisterRouter.scala:87:24] wire out_womask_783 = &_out_womask_T_783; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_783 = out_rivalid_1_637 & out_rimask_783; // @[RegisterRouter.scala:87:24] wire _out_T_7724 = out_f_rivalid_783; // @[RegisterRouter.scala:87:24] wire out_f_roready_783 = out_roready_1_637 & out_romask_783; // @[RegisterRouter.scala:87:24] wire _out_T_7725 = out_f_roready_783; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_783 = out_wivalid_1_637 & out_wimask_783; // @[RegisterRouter.scala:87:24] wire out_f_woready_783 = out_woready_1_637 & out_womask_783; // @[RegisterRouter.scala:87:24] wire _out_T_7726 = ~out_rimask_783; // @[RegisterRouter.scala:87:24] wire _out_T_7727 = ~out_wimask_783; // @[RegisterRouter.scala:87:24] wire _out_T_7728 = ~out_romask_783; // @[RegisterRouter.scala:87:24] wire _out_T_7729 = ~out_womask_783; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_666 = {hi_253, flags_0_go, _out_prepend_T_666}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7730 = out_prepend_666; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7731 = _out_T_7730; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_667 = _out_T_7731; // @[RegisterRouter.scala:87:24] wire out_rimask_784 = \|_out_rimask_T_784; // @[RegisterRouter.scala:87:24] wire out_wimask_784 = &_out_wimask_T_784; // @[RegisterRouter.scala:87:24] wire out_romask_784 = \|_out_romask_T_784; // @[RegisterRouter.scala:87:24] wire out_womask_784 = &_out_womask_T_784; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_784 = out_rivalid_1_638 & out_rimask_784; // @[RegisterRouter.scala:87:24] wire _out_T_7733 = out_f_rivalid_784; // @[RegisterRouter.scala:87:24] wire out_f_roready_784 = out_roready_1_638 & out_romask_784; // @[RegisterRouter.scala:87:24] wire _out_T_7734 = out_f_roready_784; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_784 = out_wivalid_1_638 & out_wimask_784; // @[RegisterRouter.scala:87:24] wire out_f_woready_784 = out_woready_1_638 & out_womask_784; // @[RegisterRouter.scala:87:24] wire _out_T_7735 = ~out_rimask_784; // @[RegisterRouter.scala:87:24] wire _out_T_7736 = ~out_wimask_784; // @[RegisterRouter.scala:87:24] wire _out_T_7737 = ~out_romask_784; // @[RegisterRouter.scala:87:24] wire _out_T_7738 = ~out_womask_784; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_667 = {hi_254, flags_0_go, _out_prepend_T_667}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7739 = out_prepend_667; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7740 = _out_T_7739; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_668 = _out_T_7740; // @[RegisterRouter.scala:87:24] wire out_rimask_785 = \|_out_rimask_T_785; // @[RegisterRouter.scala:87:24] wire out_wimask_785 = &_out_wimask_T_785; // @[RegisterRouter.scala:87:24] wire out_romask_785 = \|_out_romask_T_785; // @[RegisterRouter.scala:87:24] wire out_womask_785 = &_out_womask_T_785; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_785 = out_rivalid_1_639 & out_rimask_785; // @[RegisterRouter.scala:87:24] wire _out_T_7742 = out_f_rivalid_785; // @[RegisterRouter.scala:87:24] wire out_f_roready_785 = out_roready_1_639 & out_romask_785; // @[RegisterRouter.scala:87:24] wire _out_T_7743 = out_f_roready_785; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_785 = out_wivalid_1_639 & out_wimask_785; // @[RegisterRouter.scala:87:24] wire out_f_woready_785 = out_woready_1_639 & out_womask_785; // @[RegisterRouter.scala:87:24] wire _out_T_7744 = ~out_rimask_785; // @[RegisterRouter.scala:87:24] wire _out_T_7745 = ~out_wimask_785; // @[RegisterRouter.scala:87:24] wire _out_T_7746 = ~out_romask_785; // @[RegisterRouter.scala:87:24] wire _out_T_7747 = ~out_womask_785; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_668 = {hi_255, flags_0_go, _out_prepend_T_668}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7748 = out_prepend_668; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7749 = _out_T_7748; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_669 = _out_T_7749; // @[RegisterRouter.scala:87:24] wire out_rimask_786 = \|_out_rimask_T_786; // @[RegisterRouter.scala:87:24] wire out_wimask_786 = &_out_wimask_T_786; // @[RegisterRouter.scala:87:24] wire out_romask_786 = \|_out_romask_T_786; // @[RegisterRouter.scala:87:24] wire out_womask_786 = &_out_womask_T_786; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_786 = out_rivalid_1_640 & out_rimask_786; // @[RegisterRouter.scala:87:24] wire _out_T_7751 = out_f_rivalid_786; // @[RegisterRouter.scala:87:24] wire out_f_roready_786 = out_roready_1_640 & out_romask_786; // @[RegisterRouter.scala:87:24] wire _out_T_7752 = out_f_roready_786; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_786 = out_wivalid_1_640 & out_wimask_786; // @[RegisterRouter.scala:87:24] wire out_f_woready_786 = out_woready_1_640 & out_womask_786; // @[RegisterRouter.scala:87:24] wire _out_T_7753 = ~out_rimask_786; // @[RegisterRouter.scala:87:24] wire _out_T_7754 = ~out_wimask_786; // @[RegisterRouter.scala:87:24] wire _out_T_7755 = ~out_romask_786; // @[RegisterRouter.scala:87:24] wire _out_T_7756 = ~out_womask_786; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_669 = {hi_256, flags_0_go, _out_prepend_T_669}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7757 = out_prepend_669; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7758 = _out_T_7757; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_159 = _out_T_7758; // @[MuxLiteral.scala:49:48] wire out_rimask_787 = \|_out_rimask_T_787; // @[RegisterRouter.scala:87:24] wire out_wimask_787 = &_out_wimask_T_787; // @[RegisterRouter.scala:87:24] wire out_romask_787 = \|_out_romask_T_787; // @[RegisterRouter.scala:87:24] wire out_womask_787 = &_out_womask_T_787; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_787 = out_rivalid_1_641 & out_rimask_787; // @[RegisterRouter.scala:87:24] wire _out_T_7760 = out_f_rivalid_787; // @[RegisterRouter.scala:87:24] wire out_f_roready_787 = out_roready_1_641 & out_romask_787; // @[RegisterRouter.scala:87:24] wire _out_T_7761 = out_f_roready_787; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_787 = out_wivalid_1_641 & out_wimask_787; // @[RegisterRouter.scala:87:24] wire out_f_woready_787 = out_woready_1_641 & out_womask_787; // @[RegisterRouter.scala:87:24] wire _out_T_7762 = ~out_rimask_787; // @[RegisterRouter.scala:87:24] wire _out_T_7763 = ~out_wimask_787; // @[RegisterRouter.scala:87:24] wire _out_T_7764 = ~out_romask_787; // @[RegisterRouter.scala:87:24] wire _out_T_7765 = ~out_womask_787; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7767 = _out_T_7766; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_670 = _out_T_7767; // @[RegisterRouter.scala:87:24] wire out_rimask_788 = \|_out_rimask_T_788; // @[RegisterRouter.scala:87:24] wire out_wimask_788 = &_out_wimask_T_788; // @[RegisterRouter.scala:87:24] wire out_romask_788 = \|_out_romask_T_788; // @[RegisterRouter.scala:87:24] wire out_womask_788 = &_out_womask_T_788; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_788 = out_rivalid_1_642 & out_rimask_788; // @[RegisterRouter.scala:87:24] wire _out_T_7769 = out_f_rivalid_788; // @[RegisterRouter.scala:87:24] wire out_f_roready_788 = out_roready_1_642 & out_romask_788; // @[RegisterRouter.scala:87:24] wire _out_T_7770 = out_f_roready_788; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_788 = out_wivalid_1_642 & out_wimask_788; // @[RegisterRouter.scala:87:24] wire out_f_woready_788 = out_woready_1_642 & out_womask_788; // @[RegisterRouter.scala:87:24] wire _out_T_7771 = ~out_rimask_788; // @[RegisterRouter.scala:87:24] wire _out_T_7772 = ~out_wimask_788; // @[RegisterRouter.scala:87:24] wire _out_T_7773 = ~out_romask_788; // @[RegisterRouter.scala:87:24] wire _out_T_7774 = ~out_womask_788; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_670 = {hi_474, flags_0_go, _out_prepend_T_670}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7775 = out_prepend_670; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7776 = _out_T_7775; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_671 = _out_T_7776; // @[RegisterRouter.scala:87:24] wire out_rimask_789 = \|_out_rimask_T_789; // @[RegisterRouter.scala:87:24] wire out_wimask_789 = &_out_wimask_T_789; // @[RegisterRouter.scala:87:24] wire out_romask_789 = \|_out_romask_T_789; // @[RegisterRouter.scala:87:24] wire out_womask_789 = &_out_womask_T_789; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_789 = out_rivalid_1_643 & out_rimask_789; // @[RegisterRouter.scala:87:24] wire _out_T_7778 = out_f_rivalid_789; // @[RegisterRouter.scala:87:24] wire out_f_roready_789 = out_roready_1_643 & out_romask_789; // @[RegisterRouter.scala:87:24] wire _out_T_7779 = out_f_roready_789; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_789 = out_wivalid_1_643 & out_wimask_789; // @[RegisterRouter.scala:87:24] wire out_f_woready_789 = out_woready_1_643 & out_womask_789; // @[RegisterRouter.scala:87:24] wire _out_T_7780 = ~out_rimask_789; // @[RegisterRouter.scala:87:24] wire _out_T_7781 = ~out_wimask_789; // @[RegisterRouter.scala:87:24] wire _out_T_7782 = ~out_romask_789; // @[RegisterRouter.scala:87:24] wire _out_T_7783 = ~out_womask_789; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_671 = {hi_475, flags_0_go, _out_prepend_T_671}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7784 = out_prepend_671; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7785 = _out_T_7784; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_672 = _out_T_7785; // @[RegisterRouter.scala:87:24] wire out_rimask_790 = \|_out_rimask_T_790; // @[RegisterRouter.scala:87:24] wire out_wimask_790 = &_out_wimask_T_790; // @[RegisterRouter.scala:87:24] wire out_romask_790 = \|_out_romask_T_790; // @[RegisterRouter.scala:87:24] wire out_womask_790 = &_out_womask_T_790; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_790 = out_rivalid_1_644 & out_rimask_790; // @[RegisterRouter.scala:87:24] wire _out_T_7787 = out_f_rivalid_790; // @[RegisterRouter.scala:87:24] wire out_f_roready_790 = out_roready_1_644 & out_romask_790; // @[RegisterRouter.scala:87:24] wire _out_T_7788 = out_f_roready_790; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_790 = out_wivalid_1_644 & out_wimask_790; // @[RegisterRouter.scala:87:24] wire out_f_woready_790 = out_woready_1_644 & out_womask_790; // @[RegisterRouter.scala:87:24] wire _out_T_7789 = ~out_rimask_790; // @[RegisterRouter.scala:87:24] wire _out_T_7790 = ~out_wimask_790; // @[RegisterRouter.scala:87:24] wire _out_T_7791 = ~out_romask_790; // @[RegisterRouter.scala:87:24] wire _out_T_7792 = ~out_womask_790; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_672 = {hi_476, flags_0_go, _out_prepend_T_672}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7793 = out_prepend_672; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7794 = _out_T_7793; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_673 = _out_T_7794; // @[RegisterRouter.scala:87:24] wire out_rimask_791 = \|_out_rimask_T_791; // @[RegisterRouter.scala:87:24] wire out_wimask_791 = &_out_wimask_T_791; // @[RegisterRouter.scala:87:24] wire out_romask_791 = \|_out_romask_T_791; // @[RegisterRouter.scala:87:24] wire out_womask_791 = &_out_womask_T_791; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_791 = out_rivalid_1_645 & out_rimask_791; // @[RegisterRouter.scala:87:24] wire _out_T_7796 = out_f_rivalid_791; // @[RegisterRouter.scala:87:24] wire out_f_roready_791 = out_roready_1_645 & out_romask_791; // @[RegisterRouter.scala:87:24] wire _out_T_7797 = out_f_roready_791; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_791 = out_wivalid_1_645 & out_wimask_791; // @[RegisterRouter.scala:87:24] wire out_f_woready_791 = out_woready_1_645 & out_womask_791; // @[RegisterRouter.scala:87:24] wire _out_T_7798 = ~out_rimask_791; // @[RegisterRouter.scala:87:24] wire _out_T_7799 = ~out_wimask_791; // @[RegisterRouter.scala:87:24] wire _out_T_7800 = ~out_romask_791; // @[RegisterRouter.scala:87:24] wire _out_T_7801 = ~out_womask_791; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_673 = {hi_477, flags_0_go, _out_prepend_T_673}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7802 = out_prepend_673; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7803 = _out_T_7802; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_674 = _out_T_7803; // @[RegisterRouter.scala:87:24] wire out_rimask_792 = \|_out_rimask_T_792; // @[RegisterRouter.scala:87:24] wire out_wimask_792 = &_out_wimask_T_792; // @[RegisterRouter.scala:87:24] wire out_romask_792 = \|_out_romask_T_792; // @[RegisterRouter.scala:87:24] wire out_womask_792 = &_out_womask_T_792; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_792 = out_rivalid_1_646 & out_rimask_792; // @[RegisterRouter.scala:87:24] wire _out_T_7805 = out_f_rivalid_792; // @[RegisterRouter.scala:87:24] wire out_f_roready_792 = out_roready_1_646 & out_romask_792; // @[RegisterRouter.scala:87:24] wire _out_T_7806 = out_f_roready_792; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_792 = out_wivalid_1_646 & out_wimask_792; // @[RegisterRouter.scala:87:24] wire out_f_woready_792 = out_woready_1_646 & out_womask_792; // @[RegisterRouter.scala:87:24] wire _out_T_7807 = ~out_rimask_792; // @[RegisterRouter.scala:87:24] wire _out_T_7808 = ~out_wimask_792; // @[RegisterRouter.scala:87:24] wire _out_T_7809 = ~out_romask_792; // @[RegisterRouter.scala:87:24] wire _out_T_7810 = ~out_womask_792; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_674 = {hi_478, flags_0_go, _out_prepend_T_674}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7811 = out_prepend_674; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7812 = _out_T_7811; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_675 = _out_T_7812; // @[RegisterRouter.scala:87:24] wire out_rimask_793 = \|_out_rimask_T_793; // @[RegisterRouter.scala:87:24] wire out_wimask_793 = &_out_wimask_T_793; // @[RegisterRouter.scala:87:24] wire out_romask_793 = \|_out_romask_T_793; // @[RegisterRouter.scala:87:24] wire out_womask_793 = &_out_womask_T_793; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_793 = out_rivalid_1_647 & out_rimask_793; // @[RegisterRouter.scala:87:24] wire _out_T_7814 = out_f_rivalid_793; // @[RegisterRouter.scala:87:24] wire out_f_roready_793 = out_roready_1_647 & out_romask_793; // @[RegisterRouter.scala:87:24] wire _out_T_7815 = out_f_roready_793; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_793 = out_wivalid_1_647 & out_wimask_793; // @[RegisterRouter.scala:87:24] wire out_f_woready_793 = out_woready_1_647 & out_womask_793; // @[RegisterRouter.scala:87:24] wire _out_T_7816 = ~out_rimask_793; // @[RegisterRouter.scala:87:24] wire _out_T_7817 = ~out_wimask_793; // @[RegisterRouter.scala:87:24] wire _out_T_7818 = ~out_romask_793; // @[RegisterRouter.scala:87:24] wire _out_T_7819 = ~out_womask_793; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_675 = {hi_479, flags_0_go, _out_prepend_T_675}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7820 = out_prepend_675; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7821 = _out_T_7820; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_676 = _out_T_7821; // @[RegisterRouter.scala:87:24] wire out_rimask_794 = \|_out_rimask_T_794; // @[RegisterRouter.scala:87:24] wire out_wimask_794 = &_out_wimask_T_794; // @[RegisterRouter.scala:87:24] wire out_romask_794 = \|_out_romask_T_794; // @[RegisterRouter.scala:87:24] wire out_womask_794 = &_out_womask_T_794; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_794 = out_rivalid_1_648 & out_rimask_794; // @[RegisterRouter.scala:87:24] wire _out_T_7823 = out_f_rivalid_794; // @[RegisterRouter.scala:87:24] wire out_f_roready_794 = out_roready_1_648 & out_romask_794; // @[RegisterRouter.scala:87:24] wire _out_T_7824 = out_f_roready_794; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_794 = out_wivalid_1_648 & out_wimask_794; // @[RegisterRouter.scala:87:24] wire out_f_woready_794 = out_woready_1_648 & out_womask_794; // @[RegisterRouter.scala:87:24] wire _out_T_7825 = ~out_rimask_794; // @[RegisterRouter.scala:87:24] wire _out_T_7826 = ~out_wimask_794; // @[RegisterRouter.scala:87:24] wire _out_T_7827 = ~out_romask_794; // @[RegisterRouter.scala:87:24] wire _out_T_7828 = ~out_womask_794; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_676 = {hi_480, flags_0_go, _out_prepend_T_676}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7829 = out_prepend_676; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7830 = _out_T_7829; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_187 = _out_T_7830; // @[MuxLiteral.scala:49:48] wire out_rimask_795 = \|_out_rimask_T_795; // @[RegisterRouter.scala:87:24] wire out_wimask_795 = &_out_wimask_T_795; // @[RegisterRouter.scala:87:24] wire out_romask_795 = \|_out_romask_T_795; // @[RegisterRouter.scala:87:24] wire out_womask_795 = &_out_womask_T_795; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_795 = out_rivalid_1_649 & out_rimask_795; // @[RegisterRouter.scala:87:24] wire _out_T_7832 = out_f_rivalid_795; // @[RegisterRouter.scala:87:24] wire out_f_roready_795 = out_roready_1_649 & out_romask_795; // @[RegisterRouter.scala:87:24] wire _out_T_7833 = out_f_roready_795; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_795 = out_wivalid_1_649 & out_wimask_795; // @[RegisterRouter.scala:87:24] wire out_f_woready_795 = out_woready_1_649 & out_womask_795; // @[RegisterRouter.scala:87:24] wire _out_T_7834 = ~out_rimask_795; // @[RegisterRouter.scala:87:24] wire _out_T_7835 = ~out_wimask_795; // @[RegisterRouter.scala:87:24] wire _out_T_7836 = ~out_romask_795; // @[RegisterRouter.scala:87:24] wire _out_T_7837 = ~out_womask_795; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7839 = _out_T_7838; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_677 = _out_T_7839; // @[RegisterRouter.scala:87:24] wire out_rimask_796 = \|_out_rimask_T_796; // @[RegisterRouter.scala:87:24] wire out_wimask_796 = &_out_wimask_T_796; // @[RegisterRouter.scala:87:24] wire out_romask_796 = \|_out_romask_T_796; // @[RegisterRouter.scala:87:24] wire out_womask_796 = &_out_womask_T_796; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_796 = out_rivalid_1_650 & out_rimask_796; // @[RegisterRouter.scala:87:24] wire _out_T_7841 = out_f_rivalid_796; // @[RegisterRouter.scala:87:24] wire out_f_roready_796 = out_roready_1_650 & out_romask_796; // @[RegisterRouter.scala:87:24] wire _out_T_7842 = out_f_roready_796; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_796 = out_wivalid_1_650 & out_wimask_796; // @[RegisterRouter.scala:87:24] wire out_f_woready_796 = out_woready_1_650 & out_womask_796; // @[RegisterRouter.scala:87:24] wire _out_T_7843 = ~out_rimask_796; // @[RegisterRouter.scala:87:24] wire _out_T_7844 = ~out_wimask_796; // @[RegisterRouter.scala:87:24] wire _out_T_7845 = ~out_romask_796; // @[RegisterRouter.scala:87:24] wire _out_T_7846 = ~out_womask_796; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_677 = {hi_354, flags_0_go, _out_prepend_T_677}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7847 = out_prepend_677; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7848 = _out_T_7847; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_678 = _out_T_7848; // @[RegisterRouter.scala:87:24] wire out_rimask_797 = \|_out_rimask_T_797; // @[RegisterRouter.scala:87:24] wire out_wimask_797 = &_out_wimask_T_797; // @[RegisterRouter.scala:87:24] wire out_romask_797 = \|_out_romask_T_797; // @[RegisterRouter.scala:87:24] wire out_womask_797 = &_out_womask_T_797; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_797 = out_rivalid_1_651 & out_rimask_797; // @[RegisterRouter.scala:87:24] wire _out_T_7850 = out_f_rivalid_797; // @[RegisterRouter.scala:87:24] wire out_f_roready_797 = out_roready_1_651 & out_romask_797; // @[RegisterRouter.scala:87:24] wire _out_T_7851 = out_f_roready_797; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_797 = out_wivalid_1_651 & out_wimask_797; // @[RegisterRouter.scala:87:24] wire out_f_woready_797 = out_woready_1_651 & out_womask_797; // @[RegisterRouter.scala:87:24] wire _out_T_7852 = ~out_rimask_797; // @[RegisterRouter.scala:87:24] wire _out_T_7853 = ~out_wimask_797; // @[RegisterRouter.scala:87:24] wire _out_T_7854 = ~out_romask_797; // @[RegisterRouter.scala:87:24] wire _out_T_7855 = ~out_womask_797; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_678 = {hi_355, flags_0_go, _out_prepend_T_678}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7856 = out_prepend_678; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7857 = _out_T_7856; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_679 = _out_T_7857; // @[RegisterRouter.scala:87:24] wire out_rimask_798 = \|_out_rimask_T_798; // @[RegisterRouter.scala:87:24] wire out_wimask_798 = &_out_wimask_T_798; // @[RegisterRouter.scala:87:24] wire out_romask_798 = \|_out_romask_T_798; // @[RegisterRouter.scala:87:24] wire out_womask_798 = &_out_womask_T_798; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_798 = out_rivalid_1_652 & out_rimask_798; // @[RegisterRouter.scala:87:24] wire _out_T_7859 = out_f_rivalid_798; // @[RegisterRouter.scala:87:24] wire out_f_roready_798 = out_roready_1_652 & out_romask_798; // @[RegisterRouter.scala:87:24] wire _out_T_7860 = out_f_roready_798; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_798 = out_wivalid_1_652 & out_wimask_798; // @[RegisterRouter.scala:87:24] wire out_f_woready_798 = out_woready_1_652 & out_womask_798; // @[RegisterRouter.scala:87:24] wire _out_T_7861 = ~out_rimask_798; // @[RegisterRouter.scala:87:24] wire _out_T_7862 = ~out_wimask_798; // @[RegisterRouter.scala:87:24] wire _out_T_7863 = ~out_romask_798; // @[RegisterRouter.scala:87:24] wire _out_T_7864 = ~out_womask_798; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_679 = {hi_356, flags_0_go, _out_prepend_T_679}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7865 = out_prepend_679; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7866 = _out_T_7865; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_680 = _out_T_7866; // @[RegisterRouter.scala:87:24] wire out_rimask_799 = \|_out_rimask_T_799; // @[RegisterRouter.scala:87:24] wire out_wimask_799 = &_out_wimask_T_799; // @[RegisterRouter.scala:87:24] wire out_romask_799 = \|_out_romask_T_799; // @[RegisterRouter.scala:87:24] wire out_womask_799 = &_out_womask_T_799; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_799 = out_rivalid_1_653 & out_rimask_799; // @[RegisterRouter.scala:87:24] wire _out_T_7868 = out_f_rivalid_799; // @[RegisterRouter.scala:87:24] wire out_f_roready_799 = out_roready_1_653 & out_romask_799; // @[RegisterRouter.scala:87:24] wire _out_T_7869 = out_f_roready_799; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_799 = out_wivalid_1_653 & out_wimask_799; // @[RegisterRouter.scala:87:24] wire out_f_woready_799 = out_woready_1_653 & out_womask_799; // @[RegisterRouter.scala:87:24] wire _out_T_7870 = ~out_rimask_799; // @[RegisterRouter.scala:87:24] wire _out_T_7871 = ~out_wimask_799; // @[RegisterRouter.scala:87:24] wire _out_T_7872 = ~out_romask_799; // @[RegisterRouter.scala:87:24] wire _out_T_7873 = ~out_womask_799; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_680 = {hi_357, flags_0_go, _out_prepend_T_680}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7874 = out_prepend_680; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7875 = _out_T_7874; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_681 = _out_T_7875; // @[RegisterRouter.scala:87:24] wire out_rimask_800 = \|_out_rimask_T_800; // @[RegisterRouter.scala:87:24] wire out_wimask_800 = &_out_wimask_T_800; // @[RegisterRouter.scala:87:24] wire out_romask_800 = \|_out_romask_T_800; // @[RegisterRouter.scala:87:24] wire out_womask_800 = &_out_womask_T_800; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_800 = out_rivalid_1_654 & out_rimask_800; // @[RegisterRouter.scala:87:24] wire _out_T_7877 = out_f_rivalid_800; // @[RegisterRouter.scala:87:24] wire out_f_roready_800 = out_roready_1_654 & out_romask_800; // @[RegisterRouter.scala:87:24] wire _out_T_7878 = out_f_roready_800; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_800 = out_wivalid_1_654 & out_wimask_800; // @[RegisterRouter.scala:87:24] wire out_f_woready_800 = out_woready_1_654 & out_womask_800; // @[RegisterRouter.scala:87:24] wire _out_T_7879 = ~out_rimask_800; // @[RegisterRouter.scala:87:24] wire _out_T_7880 = ~out_wimask_800; // @[RegisterRouter.scala:87:24] wire _out_T_7881 = ~out_romask_800; // @[RegisterRouter.scala:87:24] wire _out_T_7882 = ~out_womask_800; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_681 = {hi_358, flags_0_go, _out_prepend_T_681}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7883 = out_prepend_681; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7884 = _out_T_7883; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_682 = _out_T_7884; // @[RegisterRouter.scala:87:24] wire out_rimask_801 = \|_out_rimask_T_801; // @[RegisterRouter.scala:87:24] wire out_wimask_801 = &_out_wimask_T_801; // @[RegisterRouter.scala:87:24] wire out_romask_801 = \|_out_romask_T_801; // @[RegisterRouter.scala:87:24] wire out_womask_801 = &_out_womask_T_801; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_801 = out_rivalid_1_655 & out_rimask_801; // @[RegisterRouter.scala:87:24] wire _out_T_7886 = out_f_rivalid_801; // @[RegisterRouter.scala:87:24] wire out_f_roready_801 = out_roready_1_655 & out_romask_801; // @[RegisterRouter.scala:87:24] wire _out_T_7887 = out_f_roready_801; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_801 = out_wivalid_1_655 & out_wimask_801; // @[RegisterRouter.scala:87:24] wire out_f_woready_801 = out_woready_1_655 & out_womask_801; // @[RegisterRouter.scala:87:24] wire _out_T_7888 = ~out_rimask_801; // @[RegisterRouter.scala:87:24] wire _out_T_7889 = ~out_wimask_801; // @[RegisterRouter.scala:87:24] wire _out_T_7890 = ~out_romask_801; // @[RegisterRouter.scala:87:24] wire _out_T_7891 = ~out_womask_801; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_682 = {hi_359, flags_0_go, _out_prepend_T_682}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7892 = out_prepend_682; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7893 = _out_T_7892; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_683 = _out_T_7893; // @[RegisterRouter.scala:87:24] wire out_rimask_802 = \|_out_rimask_T_802; // @[RegisterRouter.scala:87:24] wire out_wimask_802 = &_out_wimask_T_802; // @[RegisterRouter.scala:87:24] wire out_romask_802 = \|_out_romask_T_802; // @[RegisterRouter.scala:87:24] wire out_womask_802 = &_out_womask_T_802; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_802 = out_rivalid_1_656 & out_rimask_802; // @[RegisterRouter.scala:87:24] wire _out_T_7895 = out_f_rivalid_802; // @[RegisterRouter.scala:87:24] wire out_f_roready_802 = out_roready_1_656 & out_romask_802; // @[RegisterRouter.scala:87:24] wire _out_T_7896 = out_f_roready_802; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_802 = out_wivalid_1_656 & out_wimask_802; // @[RegisterRouter.scala:87:24] wire out_f_woready_802 = out_woready_1_656 & out_womask_802; // @[RegisterRouter.scala:87:24] wire _out_T_7897 = ~out_rimask_802; // @[RegisterRouter.scala:87:24] wire _out_T_7898 = ~out_wimask_802; // @[RegisterRouter.scala:87:24] wire _out_T_7899 = ~out_romask_802; // @[RegisterRouter.scala:87:24] wire _out_T_7900 = ~out_womask_802; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_683 = {hi_360, flags_0_go, _out_prepend_T_683}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7901 = out_prepend_683; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7902 = _out_T_7901; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_172 = _out_T_7902; // @[MuxLiteral.scala:49:48] wire out_rimask_803 = \|_out_rimask_T_803; // @[RegisterRouter.scala:87:24] wire out_wimask_803 = &_out_wimask_T_803; // @[RegisterRouter.scala:87:24] wire out_romask_803 = \|_out_romask_T_803; // @[RegisterRouter.scala:87:24] wire out_womask_803 = &_out_womask_T_803; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_803 = out_rivalid_1_657 & out_rimask_803; // @[RegisterRouter.scala:87:24] wire _out_T_7904 = out_f_rivalid_803; // @[RegisterRouter.scala:87:24] wire out_f_roready_803 = out_roready_1_657 & out_romask_803; // @[RegisterRouter.scala:87:24] wire _out_T_7905 = out_f_roready_803; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_803 = out_wivalid_1_657 & out_wimask_803; // @[RegisterRouter.scala:87:24] wire _out_T_7906 = out_f_wivalid_803; // @[RegisterRouter.scala:87:24] wire out_f_woready_803 = out_woready_1_657 & out_womask_803; // @[RegisterRouter.scala:87:24] wire _out_T_7907 = out_f_woready_803; // @[RegisterRouter.scala:87:24] wire _out_T_7908 = ~out_rimask_803; // @[RegisterRouter.scala:87:24] wire _out_T_7909 = ~out_wimask_803; // @[RegisterRouter.scala:87:24] wire _out_T_7910 = ~out_romask_803; // @[RegisterRouter.scala:87:24] wire _out_T_7911 = ~out_womask_803; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7913 = _out_T_7912; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_684 = _out_T_7913; // @[RegisterRouter.scala:87:24] wire out_rimask_804 = \|_out_rimask_T_804; // @[RegisterRouter.scala:87:24] wire out_wimask_804 = &_out_wimask_T_804; // @[RegisterRouter.scala:87:24] wire out_romask_804 = \|_out_romask_T_804; // @[RegisterRouter.scala:87:24] wire out_womask_804 = &_out_womask_T_804; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_804 = out_rivalid_1_658 & out_rimask_804; // @[RegisterRouter.scala:87:24] wire _out_T_7915 = out_f_rivalid_804; // @[RegisterRouter.scala:87:24] wire out_f_roready_804 = out_roready_1_658 & out_romask_804; // @[RegisterRouter.scala:87:24] wire _out_T_7916 = out_f_roready_804; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_804 = out_wivalid_1_658 & out_wimask_804; // @[RegisterRouter.scala:87:24] wire _out_T_7917 = out_f_wivalid_804; // @[RegisterRouter.scala:87:24] wire out_f_woready_804 = out_woready_1_658 & out_womask_804; // @[RegisterRouter.scala:87:24] wire _out_T_7918 = out_f_woready_804; // @[RegisterRouter.scala:87:24] wire _out_T_7919 = ~out_rimask_804; // @[RegisterRouter.scala:87:24] wire _out_T_7920 = ~out_wimask_804; // @[RegisterRouter.scala:87:24] wire _out_T_7921 = ~out_romask_804; // @[RegisterRouter.scala:87:24] wire _out_T_7922 = ~out_womask_804; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_684 = {abstractDataMem_9, _out_prepend_T_684}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7923 = out_prepend_684; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7924 = _out_T_7923; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_685 = _out_T_7924; // @[RegisterRouter.scala:87:24] wire out_rimask_805 = \|_out_rimask_T_805; // @[RegisterRouter.scala:87:24] wire out_wimask_805 = &_out_wimask_T_805; // @[RegisterRouter.scala:87:24] wire out_romask_805 = \|_out_romask_T_805; // @[RegisterRouter.scala:87:24] wire out_womask_805 = &_out_womask_T_805; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_805 = out_rivalid_1_659 & out_rimask_805; // @[RegisterRouter.scala:87:24] wire _out_T_7926 = out_f_rivalid_805; // @[RegisterRouter.scala:87:24] wire out_f_roready_805 = out_roready_1_659 & out_romask_805; // @[RegisterRouter.scala:87:24] wire _out_T_7927 = out_f_roready_805; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_805 = out_wivalid_1_659 & out_wimask_805; // @[RegisterRouter.scala:87:24] wire _out_T_7928 = out_f_wivalid_805; // @[RegisterRouter.scala:87:24] wire out_f_woready_805 = out_woready_1_659 & out_womask_805; // @[RegisterRouter.scala:87:24] wire _out_T_7929 = out_f_woready_805; // @[RegisterRouter.scala:87:24] wire _out_T_7930 = ~out_rimask_805; // @[RegisterRouter.scala:87:24] wire _out_T_7931 = ~out_wimask_805; // @[RegisterRouter.scala:87:24] wire _out_T_7932 = ~out_romask_805; // @[RegisterRouter.scala:87:24] wire _out_T_7933 = ~out_womask_805; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_685 = {abstractDataMem_10, _out_prepend_T_685}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7934 = out_prepend_685; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7935 = _out_T_7934; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_686 = _out_T_7935; // @[RegisterRouter.scala:87:24] wire out_rimask_806 = \|_out_rimask_T_806; // @[RegisterRouter.scala:87:24] wire out_wimask_806 = &_out_wimask_T_806; // @[RegisterRouter.scala:87:24] wire out_romask_806 = \|_out_romask_T_806; // @[RegisterRouter.scala:87:24] wire out_womask_806 = &_out_womask_T_806; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_806 = out_rivalid_1_660 & out_rimask_806; // @[RegisterRouter.scala:87:24] wire _out_T_7937 = out_f_rivalid_806; // @[RegisterRouter.scala:87:24] wire out_f_roready_806 = out_roready_1_660 & out_romask_806; // @[RegisterRouter.scala:87:24] wire _out_T_7938 = out_f_roready_806; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_806 = out_wivalid_1_660 & out_wimask_806; // @[RegisterRouter.scala:87:24] wire _out_T_7939 = out_f_wivalid_806; // @[RegisterRouter.scala:87:24] wire out_f_woready_806 = out_woready_1_660 & out_womask_806; // @[RegisterRouter.scala:87:24] wire _out_T_7940 = out_f_woready_806; // @[RegisterRouter.scala:87:24] wire _out_T_7941 = ~out_rimask_806; // @[RegisterRouter.scala:87:24] wire _out_T_7942 = ~out_wimask_806; // @[RegisterRouter.scala:87:24] wire _out_T_7943 = ~out_romask_806; // @[RegisterRouter.scala:87:24] wire _out_T_7944 = ~out_womask_806; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_686 = {abstractDataMem_11, _out_prepend_T_686}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7945 = out_prepend_686; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7946 = _out_T_7945; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_687 = _out_T_7946; // @[RegisterRouter.scala:87:24] wire out_rimask_807 = \|_out_rimask_T_807; // @[RegisterRouter.scala:87:24] wire out_wimask_807 = &_out_wimask_T_807; // @[RegisterRouter.scala:87:24] wire out_romask_807 = \|_out_romask_T_807; // @[RegisterRouter.scala:87:24] wire out_womask_807 = &_out_womask_T_807; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_807 = out_rivalid_1_661 & out_rimask_807; // @[RegisterRouter.scala:87:24] wire _out_T_7948 = out_f_rivalid_807; // @[RegisterRouter.scala:87:24] wire out_f_roready_807 = out_roready_1_661 & out_romask_807; // @[RegisterRouter.scala:87:24] wire _out_T_7949 = out_f_roready_807; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_807 = out_wivalid_1_661 & out_wimask_807; // @[RegisterRouter.scala:87:24] wire _out_T_7950 = out_f_wivalid_807; // @[RegisterRouter.scala:87:24] wire out_f_woready_807 = out_woready_1_661 & out_womask_807; // @[RegisterRouter.scala:87:24] wire _out_T_7951 = out_f_woready_807; // @[RegisterRouter.scala:87:24] wire _out_T_7952 = ~out_rimask_807; // @[RegisterRouter.scala:87:24] wire _out_T_7953 = ~out_wimask_807; // @[RegisterRouter.scala:87:24] wire _out_T_7954 = ~out_romask_807; // @[RegisterRouter.scala:87:24] wire _out_T_7955 = ~out_womask_807; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_687 = {abstractDataMem_12, _out_prepend_T_687}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7956 = out_prepend_687; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7957 = _out_T_7956; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_688 = _out_T_7957; // @[RegisterRouter.scala:87:24] wire out_rimask_808 = \|_out_rimask_T_808; // @[RegisterRouter.scala:87:24] wire out_wimask_808 = &_out_wimask_T_808; // @[RegisterRouter.scala:87:24] wire out_romask_808 = \|_out_romask_T_808; // @[RegisterRouter.scala:87:24] wire out_womask_808 = &_out_womask_T_808; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_808 = out_rivalid_1_662 & out_rimask_808; // @[RegisterRouter.scala:87:24] wire _out_T_7959 = out_f_rivalid_808; // @[RegisterRouter.scala:87:24] wire out_f_roready_808 = out_roready_1_662 & out_romask_808; // @[RegisterRouter.scala:87:24] wire _out_T_7960 = out_f_roready_808; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_808 = out_wivalid_1_662 & out_wimask_808; // @[RegisterRouter.scala:87:24] wire _out_T_7961 = out_f_wivalid_808; // @[RegisterRouter.scala:87:24] wire out_f_woready_808 = out_woready_1_662 & out_womask_808; // @[RegisterRouter.scala:87:24] wire _out_T_7962 = out_f_woready_808; // @[RegisterRouter.scala:87:24] wire _out_T_7963 = ~out_rimask_808; // @[RegisterRouter.scala:87:24] wire _out_T_7964 = ~out_wimask_808; // @[RegisterRouter.scala:87:24] wire _out_T_7965 = ~out_romask_808; // @[RegisterRouter.scala:87:24] wire _out_T_7966 = ~out_womask_808; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_688 = {abstractDataMem_13, _out_prepend_T_688}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7967 = out_prepend_688; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7968 = _out_T_7967; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_689 = _out_T_7968; // @[RegisterRouter.scala:87:24] wire out_rimask_809 = \|_out_rimask_T_809; // @[RegisterRouter.scala:87:24] wire out_wimask_809 = &_out_wimask_T_809; // @[RegisterRouter.scala:87:24] wire out_romask_809 = \|_out_romask_T_809; // @[RegisterRouter.scala:87:24] wire out_womask_809 = &_out_womask_T_809; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_809 = out_rivalid_1_663 & out_rimask_809; // @[RegisterRouter.scala:87:24] wire _out_T_7970 = out_f_rivalid_809; // @[RegisterRouter.scala:87:24] wire out_f_roready_809 = out_roready_1_663 & out_romask_809; // @[RegisterRouter.scala:87:24] wire _out_T_7971 = out_f_roready_809; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_809 = out_wivalid_1_663 & out_wimask_809; // @[RegisterRouter.scala:87:24] wire _out_T_7972 = out_f_wivalid_809; // @[RegisterRouter.scala:87:24] wire out_f_woready_809 = out_woready_1_663 & out_womask_809; // @[RegisterRouter.scala:87:24] wire _out_T_7973 = out_f_woready_809; // @[RegisterRouter.scala:87:24] wire _out_T_7974 = ~out_rimask_809; // @[RegisterRouter.scala:87:24] wire _out_T_7975 = ~out_wimask_809; // @[RegisterRouter.scala:87:24] wire _out_T_7976 = ~out_romask_809; // @[RegisterRouter.scala:87:24] wire _out_T_7977 = ~out_womask_809; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_689 = {abstractDataMem_14, _out_prepend_T_689}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7978 = out_prepend_689; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7979 = _out_T_7978; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_690 = _out_T_7979; // @[RegisterRouter.scala:87:24] wire out_rimask_810 = \|_out_rimask_T_810; // @[RegisterRouter.scala:87:24] wire out_wimask_810 = &_out_wimask_T_810; // @[RegisterRouter.scala:87:24] wire out_romask_810 = \|_out_romask_T_810; // @[RegisterRouter.scala:87:24] wire out_womask_810 = &_out_womask_T_810; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_810 = out_rivalid_1_664 & out_rimask_810; // @[RegisterRouter.scala:87:24] wire _out_T_7981 = out_f_rivalid_810; // @[RegisterRouter.scala:87:24] wire out_f_roready_810 = out_roready_1_664 & out_romask_810; // @[RegisterRouter.scala:87:24] wire _out_T_7982 = out_f_roready_810; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_810 = out_wivalid_1_664 & out_wimask_810; // @[RegisterRouter.scala:87:24] wire _out_T_7983 = out_f_wivalid_810; // @[RegisterRouter.scala:87:24] wire out_f_woready_810 = out_woready_1_664 & out_womask_810; // @[RegisterRouter.scala:87:24] wire _out_T_7984 = out_f_woready_810; // @[RegisterRouter.scala:87:24] wire _out_T_7985 = ~out_rimask_810; // @[RegisterRouter.scala:87:24] wire _out_T_7986 = ~out_wimask_810; // @[RegisterRouter.scala:87:24] wire _out_T_7987 = ~out_romask_810; // @[RegisterRouter.scala:87:24] wire _out_T_7988 = ~out_womask_810; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_690 = {abstractDataMem_15, _out_prepend_T_690}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7989 = out_prepend_690; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7990 = _out_T_7989; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_113 = _out_T_7990; // @[MuxLiteral.scala:49:48] wire out_rimask_811 = \|_out_rimask_T_811; // @[RegisterRouter.scala:87:24] wire out_wimask_811 = &_out_wimask_T_811; // @[RegisterRouter.scala:87:24] wire out_romask_811 = \|_out_romask_T_811; // @[RegisterRouter.scala:87:24] wire out_womask_811 = &_out_womask_T_811; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_811 = out_rivalid_1_665 & out_rimask_811; // @[RegisterRouter.scala:87:24] wire _out_T_7992 = out_f_rivalid_811; // @[RegisterRouter.scala:87:24] wire out_f_roready_811 = out_roready_1_665 & out_romask_811; // @[RegisterRouter.scala:87:24] wire _out_T_7993 = out_f_roready_811; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_811 = out_wivalid_1_665 & out_wimask_811; // @[RegisterRouter.scala:87:24] wire out_f_woready_811 = out_woready_1_665 & out_womask_811; // @[RegisterRouter.scala:87:24] wire _out_T_7994 = ~out_rimask_811; // @[RegisterRouter.scala:87:24] wire _out_T_7995 = ~out_wimask_811; // @[RegisterRouter.scala:87:24] wire _out_T_7996 = ~out_romask_811; // @[RegisterRouter.scala:87:24] wire _out_T_7997 = ~out_womask_811; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7999 = _out_T_7998; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_691 = _out_T_7999; // @[RegisterRouter.scala:87:24] wire out_rimask_812 = \|_out_rimask_T_812; // @[RegisterRouter.scala:87:24] wire out_wimask_812 = &_out_wimask_T_812; // @[RegisterRouter.scala:87:24] wire out_romask_812 = \|_out_romask_T_812; // @[RegisterRouter.scala:87:24] wire out_womask_812 = &_out_womask_T_812; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_812 = out_rivalid_1_666 & out_rimask_812; // @[RegisterRouter.scala:87:24] wire _out_T_8001 = out_f_rivalid_812; // @[RegisterRouter.scala:87:24] wire out_f_roready_812 = out_roready_1_666 & out_romask_812; // @[RegisterRouter.scala:87:24] wire _out_T_8002 = out_f_roready_812; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_812 = out_wivalid_1_666 & out_wimask_812; // @[RegisterRouter.scala:87:24] wire out_f_woready_812 = out_woready_1_666 & out_womask_812; // @[RegisterRouter.scala:87:24] wire _out_T_8003 = ~out_rimask_812; // @[RegisterRouter.scala:87:24] wire _out_T_8004 = ~out_wimask_812; // @[RegisterRouter.scala:87:24] wire _out_T_8005 = ~out_romask_812; // @[RegisterRouter.scala:87:24] wire _out_T_8006 = ~out_womask_812; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_691 = {hi_730, flags_0_go, _out_prepend_T_691}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8007 = out_prepend_691; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8008 = _out_T_8007; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_692 = _out_T_8008; // @[RegisterRouter.scala:87:24] wire out_rimask_813 = \|_out_rimask_T_813; // @[RegisterRouter.scala:87:24] wire out_wimask_813 = &_out_wimask_T_813; // @[RegisterRouter.scala:87:24] wire out_romask_813 = \|_out_romask_T_813; // @[RegisterRouter.scala:87:24] wire out_womask_813 = &_out_womask_T_813; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_813 = out_rivalid_1_667 & out_rimask_813; // @[RegisterRouter.scala:87:24] wire _out_T_8010 = out_f_rivalid_813; // @[RegisterRouter.scala:87:24] wire out_f_roready_813 = out_roready_1_667 & out_romask_813; // @[RegisterRouter.scala:87:24] wire _out_T_8011 = out_f_roready_813; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_813 = out_wivalid_1_667 & out_wimask_813; // @[RegisterRouter.scala:87:24] wire out_f_woready_813 = out_woready_1_667 & out_womask_813; // @[RegisterRouter.scala:87:24] wire _out_T_8012 = ~out_rimask_813; // @[RegisterRouter.scala:87:24] wire _out_T_8013 = ~out_wimask_813; // @[RegisterRouter.scala:87:24] wire _out_T_8014 = ~out_romask_813; // @[RegisterRouter.scala:87:24] wire _out_T_8015 = ~out_womask_813; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_692 = {hi_731, flags_0_go, _out_prepend_T_692}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8016 = out_prepend_692; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8017 = _out_T_8016; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_693 = _out_T_8017; // @[RegisterRouter.scala:87:24] wire out_rimask_814 = \|_out_rimask_T_814; // @[RegisterRouter.scala:87:24] wire out_wimask_814 = &_out_wimask_T_814; // @[RegisterRouter.scala:87:24] wire out_romask_814 = \|_out_romask_T_814; // @[RegisterRouter.scala:87:24] wire out_womask_814 = &_out_womask_T_814; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_814 = out_rivalid_1_668 & out_rimask_814; // @[RegisterRouter.scala:87:24] wire _out_T_8019 = out_f_rivalid_814; // @[RegisterRouter.scala:87:24] wire out_f_roready_814 = out_roready_1_668 & out_romask_814; // @[RegisterRouter.scala:87:24] wire _out_T_8020 = out_f_roready_814; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_814 = out_wivalid_1_668 & out_wimask_814; // @[RegisterRouter.scala:87:24] wire out_f_woready_814 = out_woready_1_668 & out_womask_814; // @[RegisterRouter.scala:87:24] wire _out_T_8021 = ~out_rimask_814; // @[RegisterRouter.scala:87:24] wire _out_T_8022 = ~out_wimask_814; // @[RegisterRouter.scala:87:24] wire _out_T_8023 = ~out_romask_814; // @[RegisterRouter.scala:87:24] wire _out_T_8024 = ~out_womask_814; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_693 = {hi_732, flags_0_go, _out_prepend_T_693}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8025 = out_prepend_693; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8026 = _out_T_8025; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_694 = _out_T_8026; // @[RegisterRouter.scala:87:24] wire out_rimask_815 = \|_out_rimask_T_815; // @[RegisterRouter.scala:87:24] wire out_wimask_815 = &_out_wimask_T_815; // @[RegisterRouter.scala:87:24] wire out_romask_815 = \|_out_romask_T_815; // @[RegisterRouter.scala:87:24] wire out_womask_815 = &_out_womask_T_815; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_815 = out_rivalid_1_669 & out_rimask_815; // @[RegisterRouter.scala:87:24] wire _out_T_8028 = out_f_rivalid_815; // @[RegisterRouter.scala:87:24] wire out_f_roready_815 = out_roready_1_669 & out_romask_815; // @[RegisterRouter.scala:87:24] wire _out_T_8029 = out_f_roready_815; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_815 = out_wivalid_1_669 & out_wimask_815; // @[RegisterRouter.scala:87:24] wire out_f_woready_815 = out_woready_1_669 & out_womask_815; // @[RegisterRouter.scala:87:24] wire _out_T_8030 = ~out_rimask_815; // @[RegisterRouter.scala:87:24] wire _out_T_8031 = ~out_wimask_815; // @[RegisterRouter.scala:87:24] wire _out_T_8032 = ~out_romask_815; // @[RegisterRouter.scala:87:24] wire _out_T_8033 = ~out_womask_815; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_694 = {hi_733, flags_0_go, _out_prepend_T_694}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8034 = out_prepend_694; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8035 = _out_T_8034; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_695 = _out_T_8035; // @[RegisterRouter.scala:87:24] wire out_rimask_816 = \|_out_rimask_T_816; // @[RegisterRouter.scala:87:24] wire out_wimask_816 = &_out_wimask_T_816; // @[RegisterRouter.scala:87:24] wire out_romask_816 = \|_out_romask_T_816; // @[RegisterRouter.scala:87:24] wire out_womask_816 = &_out_womask_T_816; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_816 = out_rivalid_1_670 & out_rimask_816; // @[RegisterRouter.scala:87:24] wire _out_T_8037 = out_f_rivalid_816; // @[RegisterRouter.scala:87:24] wire out_f_roready_816 = out_roready_1_670 & out_romask_816; // @[RegisterRouter.scala:87:24] wire _out_T_8038 = out_f_roready_816; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_816 = out_wivalid_1_670 & out_wimask_816; // @[RegisterRouter.scala:87:24] wire out_f_woready_816 = out_woready_1_670 & out_womask_816; // @[RegisterRouter.scala:87:24] wire _out_T_8039 = ~out_rimask_816; // @[RegisterRouter.scala:87:24] wire _out_T_8040 = ~out_wimask_816; // @[RegisterRouter.scala:87:24] wire _out_T_8041 = ~out_romask_816; // @[RegisterRouter.scala:87:24] wire _out_T_8042 = ~out_womask_816; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_695 = {hi_734, flags_0_go, _out_prepend_T_695}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8043 = out_prepend_695; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8044 = _out_T_8043; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_696 = _out_T_8044; // @[RegisterRouter.scala:87:24] wire out_rimask_817 = \|_out_rimask_T_817; // @[RegisterRouter.scala:87:24] wire out_wimask_817 = &_out_wimask_T_817; // @[RegisterRouter.scala:87:24] wire out_romask_817 = \|_out_romask_T_817; // @[RegisterRouter.scala:87:24] wire out_womask_817 = &_out_womask_T_817; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_817 = out_rivalid_1_671 & out_rimask_817; // @[RegisterRouter.scala:87:24] wire _out_T_8046 = out_f_rivalid_817; // @[RegisterRouter.scala:87:24] wire out_f_roready_817 = out_roready_1_671 & out_romask_817; // @[RegisterRouter.scala:87:24] wire _out_T_8047 = out_f_roready_817; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_817 = out_wivalid_1_671 & out_wimask_817; // @[RegisterRouter.scala:87:24] wire out_f_woready_817 = out_woready_1_671 & out_womask_817; // @[RegisterRouter.scala:87:24] wire _out_T_8048 = ~out_rimask_817; // @[RegisterRouter.scala:87:24] wire _out_T_8049 = ~out_wimask_817; // @[RegisterRouter.scala:87:24] wire _out_T_8050 = ~out_romask_817; // @[RegisterRouter.scala:87:24] wire _out_T_8051 = ~out_womask_817; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_696 = {hi_735, flags_0_go, _out_prepend_T_696}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8052 = out_prepend_696; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8053 = _out_T_8052; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_697 = _out_T_8053; // @[RegisterRouter.scala:87:24] wire out_rimask_818 = \|_out_rimask_T_818; // @[RegisterRouter.scala:87:24] wire out_wimask_818 = &_out_wimask_T_818; // @[RegisterRouter.scala:87:24] wire out_romask_818 = \|_out_romask_T_818; // @[RegisterRouter.scala:87:24] wire out_womask_818 = &_out_womask_T_818; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_818 = out_rivalid_1_672 & out_rimask_818; // @[RegisterRouter.scala:87:24] wire _out_T_8055 = out_f_rivalid_818; // @[RegisterRouter.scala:87:24] wire out_f_roready_818 = out_roready_1_672 & out_romask_818; // @[RegisterRouter.scala:87:24] wire _out_T_8056 = out_f_roready_818; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_818 = out_wivalid_1_672 & out_wimask_818; // @[RegisterRouter.scala:87:24] wire out_f_woready_818 = out_woready_1_672 & out_womask_818; // @[RegisterRouter.scala:87:24] wire _out_T_8057 = ~out_rimask_818; // @[RegisterRouter.scala:87:24] wire _out_T_8058 = ~out_wimask_818; // @[RegisterRouter.scala:87:24] wire _out_T_8059 = ~out_romask_818; // @[RegisterRouter.scala:87:24] wire _out_T_8060 = ~out_womask_818; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_697 = {hi_736, flags_0_go, _out_prepend_T_697}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8061 = out_prepend_697; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8062 = _out_T_8061; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_219 = _out_T_8062; // @[MuxLiteral.scala:49:48] wire out_rimask_819 = \|_out_rimask_T_819; // @[RegisterRouter.scala:87:24] wire out_wimask_819 = &_out_wimask_T_819; // @[RegisterRouter.scala:87:24] wire out_romask_819 = \|_out_romask_T_819; // @[RegisterRouter.scala:87:24] wire out_womask_819 = &_out_womask_T_819; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_819 = out_rivalid_1_673 & out_rimask_819; // @[RegisterRouter.scala:87:24] wire _out_T_8064 = out_f_rivalid_819; // @[RegisterRouter.scala:87:24] wire out_f_roready_819 = out_roready_1_673 & out_romask_819; // @[RegisterRouter.scala:87:24] wire _out_T_8065 = out_f_roready_819; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_819 = out_wivalid_1_673 & out_wimask_819; // @[RegisterRouter.scala:87:24] wire out_f_woready_819 = out_woready_1_673 & out_womask_819; // @[RegisterRouter.scala:87:24] wire _out_T_8066 = ~out_rimask_819; // @[RegisterRouter.scala:87:24] wire _out_T_8067 = ~out_wimask_819; // @[RegisterRouter.scala:87:24] wire _out_T_8068 = ~out_romask_819; // @[RegisterRouter.scala:87:24] wire _out_T_8069 = ~out_womask_819; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8071 = _out_T_8070; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_698 = _out_T_8071; // @[RegisterRouter.scala:87:24] wire out_rimask_820 = \|_out_rimask_T_820; // @[RegisterRouter.scala:87:24] wire out_wimask_820 = &_out_wimask_T_820; // @[RegisterRouter.scala:87:24] wire out_romask_820 = \|_out_romask_T_820; // @[RegisterRouter.scala:87:24] wire out_womask_820 = &_out_womask_T_820; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_820 = out_rivalid_1_674 & out_rimask_820; // @[RegisterRouter.scala:87:24] wire _out_T_8073 = out_f_rivalid_820; // @[RegisterRouter.scala:87:24] wire out_f_roready_820 = out_roready_1_674 & out_romask_820; // @[RegisterRouter.scala:87:24] wire _out_T_8074 = out_f_roready_820; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_820 = out_wivalid_1_674 & out_wimask_820; // @[RegisterRouter.scala:87:24] wire out_f_woready_820 = out_woready_1_674 & out_womask_820; // @[RegisterRouter.scala:87:24] wire _out_T_8075 = ~out_rimask_820; // @[RegisterRouter.scala:87:24] wire _out_T_8076 = ~out_wimask_820; // @[RegisterRouter.scala:87:24] wire _out_T_8077 = ~out_romask_820; // @[RegisterRouter.scala:87:24] wire _out_T_8078 = ~out_womask_820; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_698 = {hi_818, flags_0_go, _out_prepend_T_698}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8079 = out_prepend_698; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8080 = _out_T_8079; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_699 = _out_T_8080; // @[RegisterRouter.scala:87:24] wire out_rimask_821 = \|_out_rimask_T_821; // @[RegisterRouter.scala:87:24] wire out_wimask_821 = &_out_wimask_T_821; // @[RegisterRouter.scala:87:24] wire out_romask_821 = \|_out_romask_T_821; // @[RegisterRouter.scala:87:24] wire out_womask_821 = &_out_womask_T_821; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_821 = out_rivalid_1_675 & out_rimask_821; // @[RegisterRouter.scala:87:24] wire _out_T_8082 = out_f_rivalid_821; // @[RegisterRouter.scala:87:24] wire out_f_roready_821 = out_roready_1_675 & out_romask_821; // @[RegisterRouter.scala:87:24] wire _out_T_8083 = out_f_roready_821; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_821 = out_wivalid_1_675 & out_wimask_821; // @[RegisterRouter.scala:87:24] wire out_f_woready_821 = out_woready_1_675 & out_womask_821; // @[RegisterRouter.scala:87:24] wire _out_T_8084 = ~out_rimask_821; // @[RegisterRouter.scala:87:24] wire _out_T_8085 = ~out_wimask_821; // @[RegisterRouter.scala:87:24] wire _out_T_8086 = ~out_romask_821; // @[RegisterRouter.scala:87:24] wire _out_T_8087 = ~out_womask_821; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_699 = {hi_819, flags_0_go, _out_prepend_T_699}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8088 = out_prepend_699; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8089 = _out_T_8088; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_700 = _out_T_8089; // @[RegisterRouter.scala:87:24] wire out_rimask_822 = \|_out_rimask_T_822; // @[RegisterRouter.scala:87:24] wire out_wimask_822 = &_out_wimask_T_822; // @[RegisterRouter.scala:87:24] wire out_romask_822 = \|_out_romask_T_822; // @[RegisterRouter.scala:87:24] wire out_womask_822 = &_out_womask_T_822; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_822 = out_rivalid_1_676 & out_rimask_822; // @[RegisterRouter.scala:87:24] wire _out_T_8091 = out_f_rivalid_822; // @[RegisterRouter.scala:87:24] wire out_f_roready_822 = out_roready_1_676 & out_romask_822; // @[RegisterRouter.scala:87:24] wire _out_T_8092 = out_f_roready_822; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_822 = out_wivalid_1_676 & out_wimask_822; // @[RegisterRouter.scala:87:24] wire out_f_woready_822 = out_woready_1_676 & out_womask_822; // @[RegisterRouter.scala:87:24] wire _out_T_8093 = ~out_rimask_822; // @[RegisterRouter.scala:87:24] wire _out_T_8094 = ~out_wimask_822; // @[RegisterRouter.scala:87:24] wire _out_T_8095 = ~out_romask_822; // @[RegisterRouter.scala:87:24] wire _out_T_8096 = ~out_womask_822; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_700 = {hi_820, flags_0_go, _out_prepend_T_700}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8097 = out_prepend_700; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8098 = _out_T_8097; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_701 = _out_T_8098; // @[RegisterRouter.scala:87:24] wire out_rimask_823 = \|_out_rimask_T_823; // @[RegisterRouter.scala:87:24] wire out_wimask_823 = &_out_wimask_T_823; // @[RegisterRouter.scala:87:24] wire out_romask_823 = \|_out_romask_T_823; // @[RegisterRouter.scala:87:24] wire out_womask_823 = &_out_womask_T_823; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_823 = out_rivalid_1_677 & out_rimask_823; // @[RegisterRouter.scala:87:24] wire _out_T_8100 = out_f_rivalid_823; // @[RegisterRouter.scala:87:24] wire out_f_roready_823 = out_roready_1_677 & out_romask_823; // @[RegisterRouter.scala:87:24] wire _out_T_8101 = out_f_roready_823; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_823 = out_wivalid_1_677 & out_wimask_823; // @[RegisterRouter.scala:87:24] wire out_f_woready_823 = out_woready_1_677 & out_womask_823; // @[RegisterRouter.scala:87:24] wire _out_T_8102 = ~out_rimask_823; // @[RegisterRouter.scala:87:24] wire _out_T_8103 = ~out_wimask_823; // @[RegisterRouter.scala:87:24] wire _out_T_8104 = ~out_romask_823; // @[RegisterRouter.scala:87:24] wire _out_T_8105 = ~out_womask_823; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_701 = {hi_821, flags_0_go, _out_prepend_T_701}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8106 = out_prepend_701; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8107 = _out_T_8106; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_702 = _out_T_8107; // @[RegisterRouter.scala:87:24] wire out_rimask_824 = \|_out_rimask_T_824; // @[RegisterRouter.scala:87:24] wire out_wimask_824 = &_out_wimask_T_824; // @[RegisterRouter.scala:87:24] wire out_romask_824 = \|_out_romask_T_824; // @[RegisterRouter.scala:87:24] wire out_womask_824 = &_out_womask_T_824; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_824 = out_rivalid_1_678 & out_rimask_824; // @[RegisterRouter.scala:87:24] wire _out_T_8109 = out_f_rivalid_824; // @[RegisterRouter.scala:87:24] wire out_f_roready_824 = out_roready_1_678 & out_romask_824; // @[RegisterRouter.scala:87:24] wire _out_T_8110 = out_f_roready_824; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_824 = out_wivalid_1_678 & out_wimask_824; // @[RegisterRouter.scala:87:24] wire out_f_woready_824 = out_woready_1_678 & out_womask_824; // @[RegisterRouter.scala:87:24] wire _out_T_8111 = ~out_rimask_824; // @[RegisterRouter.scala:87:24] wire _out_T_8112 = ~out_wimask_824; // @[RegisterRouter.scala:87:24] wire _out_T_8113 = ~out_romask_824; // @[RegisterRouter.scala:87:24] wire _out_T_8114 = ~out_womask_824; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_702 = {hi_822, flags_0_go, _out_prepend_T_702}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8115 = out_prepend_702; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8116 = _out_T_8115; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_703 = _out_T_8116; // @[RegisterRouter.scala:87:24] wire out_rimask_825 = \|_out_rimask_T_825; // @[RegisterRouter.scala:87:24] wire out_wimask_825 = &_out_wimask_T_825; // @[RegisterRouter.scala:87:24] wire out_romask_825 = \|_out_romask_T_825; // @[RegisterRouter.scala:87:24] wire out_womask_825 = &_out_womask_T_825; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_825 = out_rivalid_1_679 & out_rimask_825; // @[RegisterRouter.scala:87:24] wire _out_T_8118 = out_f_rivalid_825; // @[RegisterRouter.scala:87:24] wire out_f_roready_825 = out_roready_1_679 & out_romask_825; // @[RegisterRouter.scala:87:24] wire _out_T_8119 = out_f_roready_825; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_825 = out_wivalid_1_679 & out_wimask_825; // @[RegisterRouter.scala:87:24] wire out_f_woready_825 = out_woready_1_679 & out_womask_825; // @[RegisterRouter.scala:87:24] wire _out_T_8120 = ~out_rimask_825; // @[RegisterRouter.scala:87:24] wire _out_T_8121 = ~out_wimask_825; // @[RegisterRouter.scala:87:24] wire _out_T_8122 = ~out_romask_825; // @[RegisterRouter.scala:87:24] wire _out_T_8123 = ~out_womask_825; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_703 = {hi_823, flags_0_go, _out_prepend_T_703}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8124 = out_prepend_703; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8125 = _out_T_8124; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_704 = _out_T_8125; // @[RegisterRouter.scala:87:24] wire out_rimask_826 = \|_out_rimask_T_826; // @[RegisterRouter.scala:87:24] wire out_wimask_826 = &_out_wimask_T_826; // @[RegisterRouter.scala:87:24] wire out_romask_826 = \|_out_romask_T_826; // @[RegisterRouter.scala:87:24] wire out_womask_826 = &_out_womask_T_826; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_826 = out_rivalid_1_680 & out_rimask_826; // @[RegisterRouter.scala:87:24] wire _out_T_8127 = out_f_rivalid_826; // @[RegisterRouter.scala:87:24] wire out_f_roready_826 = out_roready_1_680 & out_romask_826; // @[RegisterRouter.scala:87:24] wire _out_T_8128 = out_f_roready_826; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_826 = out_wivalid_1_680 & out_wimask_826; // @[RegisterRouter.scala:87:24] wire out_f_woready_826 = out_woready_1_680 & out_womask_826; // @[RegisterRouter.scala:87:24] wire _out_T_8129 = ~out_rimask_826; // @[RegisterRouter.scala:87:24] wire _out_T_8130 = ~out_wimask_826; // @[RegisterRouter.scala:87:24] wire _out_T_8131 = ~out_romask_826; // @[RegisterRouter.scala:87:24] wire _out_T_8132 = ~out_womask_826; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_704 = {hi_824, flags_0_go, _out_prepend_T_704}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8133 = out_prepend_704; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8134 = _out_T_8133; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_230 = _out_T_8134; // @[MuxLiteral.scala:49:48] wire out_rimask_827 = \|_out_rimask_T_827; // @[RegisterRouter.scala:87:24] wire out_wimask_827 = &_out_wimask_T_827; // @[RegisterRouter.scala:87:24] wire out_romask_827 = \|_out_romask_T_827; // @[RegisterRouter.scala:87:24] wire out_womask_827 = &_out_womask_T_827; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_827 = out_rivalid_1_681 & out_rimask_827; // @[RegisterRouter.scala:87:24] wire _out_T_8136 = out_f_rivalid_827; // @[RegisterRouter.scala:87:24] wire out_f_roready_827 = out_roready_1_681 & out_romask_827; // @[RegisterRouter.scala:87:24] wire _out_T_8137 = out_f_roready_827; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_827 = out_wivalid_1_681 & out_wimask_827; // @[RegisterRouter.scala:87:24] wire out_f_woready_827 = out_woready_1_681 & out_womask_827; // @[RegisterRouter.scala:87:24] wire _out_T_8138 = ~out_rimask_827; // @[RegisterRouter.scala:87:24] wire _out_T_8139 = ~out_wimask_827; // @[RegisterRouter.scala:87:24] wire _out_T_8140 = ~out_romask_827; // @[RegisterRouter.scala:87:24] wire _out_T_8141 = ~out_womask_827; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8143 = _out_T_8142; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_705 = _out_T_8143; // @[RegisterRouter.scala:87:24] wire out_rimask_828 = \|_out_rimask_T_828; // @[RegisterRouter.scala:87:24] wire out_wimask_828 = &_out_wimask_T_828; // @[RegisterRouter.scala:87:24] wire out_romask_828 = \|_out_romask_T_828; // @[RegisterRouter.scala:87:24] wire out_womask_828 = &_out_womask_T_828; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_828 = out_rivalid_1_682 & out_rimask_828; // @[RegisterRouter.scala:87:24] wire _out_T_8145 = out_f_rivalid_828; // @[RegisterRouter.scala:87:24] wire out_f_roready_828 = out_roready_1_682 & out_romask_828; // @[RegisterRouter.scala:87:24] wire _out_T_8146 = out_f_roready_828; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_828 = out_wivalid_1_682 & out_wimask_828; // @[RegisterRouter.scala:87:24] wire out_f_woready_828 = out_woready_1_682 & out_womask_828; // @[RegisterRouter.scala:87:24] wire _out_T_8147 = ~out_rimask_828; // @[RegisterRouter.scala:87:24] wire _out_T_8148 = ~out_wimask_828; // @[RegisterRouter.scala:87:24] wire _out_T_8149 = ~out_romask_828; // @[RegisterRouter.scala:87:24] wire _out_T_8150 = ~out_womask_828; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_705 = {hi_938, flags_0_go, _out_prepend_T_705}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8151 = out_prepend_705; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8152 = _out_T_8151; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_706 = _out_T_8152; // @[RegisterRouter.scala:87:24] wire out_rimask_829 = \|_out_rimask_T_829; // @[RegisterRouter.scala:87:24] wire out_wimask_829 = &_out_wimask_T_829; // @[RegisterRouter.scala:87:24] wire out_romask_829 = \|_out_romask_T_829; // @[RegisterRouter.scala:87:24] wire out_womask_829 = &_out_womask_T_829; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_829 = out_rivalid_1_683 & out_rimask_829; // @[RegisterRouter.scala:87:24] wire _out_T_8154 = out_f_rivalid_829; // @[RegisterRouter.scala:87:24] wire out_f_roready_829 = out_roready_1_683 & out_romask_829; // @[RegisterRouter.scala:87:24] wire _out_T_8155 = out_f_roready_829; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_829 = out_wivalid_1_683 & out_wimask_829; // @[RegisterRouter.scala:87:24] wire out_f_woready_829 = out_woready_1_683 & out_womask_829; // @[RegisterRouter.scala:87:24] wire _out_T_8156 = ~out_rimask_829; // @[RegisterRouter.scala:87:24] wire _out_T_8157 = ~out_wimask_829; // @[RegisterRouter.scala:87:24] wire _out_T_8158 = ~out_romask_829; // @[RegisterRouter.scala:87:24] wire _out_T_8159 = ~out_womask_829; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_706 = {hi_939, flags_0_go, _out_prepend_T_706}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8160 = out_prepend_706; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8161 = _out_T_8160; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_707 = _out_T_8161; // @[RegisterRouter.scala:87:24] wire out_rimask_830 = \|_out_rimask_T_830; // @[RegisterRouter.scala:87:24] wire out_wimask_830 = &_out_wimask_T_830; // @[RegisterRouter.scala:87:24] wire out_romask_830 = \|_out_romask_T_830; // @[RegisterRouter.scala:87:24] wire out_womask_830 = &_out_womask_T_830; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_830 = out_rivalid_1_684 & out_rimask_830; // @[RegisterRouter.scala:87:24] wire _out_T_8163 = out_f_rivalid_830; // @[RegisterRouter.scala:87:24] wire out_f_roready_830 = out_roready_1_684 & out_romask_830; // @[RegisterRouter.scala:87:24] wire _out_T_8164 = out_f_roready_830; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_830 = out_wivalid_1_684 & out_wimask_830; // @[RegisterRouter.scala:87:24] wire out_f_woready_830 = out_woready_1_684 & out_womask_830; // @[RegisterRouter.scala:87:24] wire _out_T_8165 = ~out_rimask_830; // @[RegisterRouter.scala:87:24] wire _out_T_8166 = ~out_wimask_830; // @[RegisterRouter.scala:87:24] wire _out_T_8167 = ~out_romask_830; // @[RegisterRouter.scala:87:24] wire _out_T_8168 = ~out_womask_830; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_707 = {hi_940, flags_0_go, _out_prepend_T_707}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8169 = out_prepend_707; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8170 = _out_T_8169; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_708 = _out_T_8170; // @[RegisterRouter.scala:87:24] wire out_rimask_831 = \|_out_rimask_T_831; // @[RegisterRouter.scala:87:24] wire out_wimask_831 = &_out_wimask_T_831; // @[RegisterRouter.scala:87:24] wire out_romask_831 = \|_out_romask_T_831; // @[RegisterRouter.scala:87:24] wire out_womask_831 = &_out_womask_T_831; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_831 = out_rivalid_1_685 & out_rimask_831; // @[RegisterRouter.scala:87:24] wire _out_T_8172 = out_f_rivalid_831; // @[RegisterRouter.scala:87:24] wire out_f_roready_831 = out_roready_1_685 & out_romask_831; // @[RegisterRouter.scala:87:24] wire _out_T_8173 = out_f_roready_831; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_831 = out_wivalid_1_685 & out_wimask_831; // @[RegisterRouter.scala:87:24] wire out_f_woready_831 = out_woready_1_685 & out_womask_831; // @[RegisterRouter.scala:87:24] wire _out_T_8174 = ~out_rimask_831; // @[RegisterRouter.scala:87:24] wire _out_T_8175 = ~out_wimask_831; // @[RegisterRouter.scala:87:24] wire _out_T_8176 = ~out_romask_831; // @[RegisterRouter.scala:87:24] wire _out_T_8177 = ~out_womask_831; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_708 = {hi_941, flags_0_go, _out_prepend_T_708}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8178 = out_prepend_708; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8179 = _out_T_8178; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_709 = _out_T_8179; // @[RegisterRouter.scala:87:24] wire out_rimask_832 = \|_out_rimask_T_832; // @[RegisterRouter.scala:87:24] wire out_wimask_832 = &_out_wimask_T_832; // @[RegisterRouter.scala:87:24] wire out_romask_832 = \|_out_romask_T_832; // @[RegisterRouter.scala:87:24] wire out_womask_832 = &_out_womask_T_832; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_832 = out_rivalid_1_686 & out_rimask_832; // @[RegisterRouter.scala:87:24] wire _out_T_8181 = out_f_rivalid_832; // @[RegisterRouter.scala:87:24] wire out_f_roready_832 = out_roready_1_686 & out_romask_832; // @[RegisterRouter.scala:87:24] wire _out_T_8182 = out_f_roready_832; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_832 = out_wivalid_1_686 & out_wimask_832; // @[RegisterRouter.scala:87:24] wire out_f_woready_832 = out_woready_1_686 & out_womask_832; // @[RegisterRouter.scala:87:24] wire _out_T_8183 = ~out_rimask_832; // @[RegisterRouter.scala:87:24] wire _out_T_8184 = ~out_wimask_832; // @[RegisterRouter.scala:87:24] wire _out_T_8185 = ~out_romask_832; // @[RegisterRouter.scala:87:24] wire _out_T_8186 = ~out_womask_832; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_709 = {hi_942, flags_0_go, _out_prepend_T_709}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8187 = out_prepend_709; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8188 = _out_T_8187; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_710 = _out_T_8188; // @[RegisterRouter.scala:87:24] wire out_rimask_833 = \|_out_rimask_T_833; // @[RegisterRouter.scala:87:24] wire out_wimask_833 = &_out_wimask_T_833; // @[RegisterRouter.scala:87:24] wire out_romask_833 = \|_out_romask_T_833; // @[RegisterRouter.scala:87:24] wire out_womask_833 = &_out_womask_T_833; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_833 = out_rivalid_1_687 & out_rimask_833; // @[RegisterRouter.scala:87:24] wire _out_T_8190 = out_f_rivalid_833; // @[RegisterRouter.scala:87:24] wire out_f_roready_833 = out_roready_1_687 & out_romask_833; // @[RegisterRouter.scala:87:24] wire _out_T_8191 = out_f_roready_833; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_833 = out_wivalid_1_687 & out_wimask_833; // @[RegisterRouter.scala:87:24] wire out_f_woready_833 = out_woready_1_687 & out_womask_833; // @[RegisterRouter.scala:87:24] wire _out_T_8192 = ~out_rimask_833; // @[RegisterRouter.scala:87:24] wire _out_T_8193 = ~out_wimask_833; // @[RegisterRouter.scala:87:24] wire _out_T_8194 = ~out_romask_833; // @[RegisterRouter.scala:87:24] wire _out_T_8195 = ~out_womask_833; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_710 = {hi_943, flags_0_go, _out_prepend_T_710}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8196 = out_prepend_710; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8197 = _out_T_8196; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_711 = _out_T_8197; // @[RegisterRouter.scala:87:24] wire out_rimask_834 = \|_out_rimask_T_834; // @[RegisterRouter.scala:87:24] wire out_wimask_834 = &_out_wimask_T_834; // @[RegisterRouter.scala:87:24] wire out_romask_834 = \|_out_romask_T_834; // @[RegisterRouter.scala:87:24] wire out_womask_834 = &_out_womask_T_834; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_834 = out_rivalid_1_688 & out_rimask_834; // @[RegisterRouter.scala:87:24] wire _out_T_8199 = out_f_rivalid_834; // @[RegisterRouter.scala:87:24] wire out_f_roready_834 = out_roready_1_688 & out_romask_834; // @[RegisterRouter.scala:87:24] wire _out_T_8200 = out_f_roready_834; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_834 = out_wivalid_1_688 & out_wimask_834; // @[RegisterRouter.scala:87:24] wire out_f_woready_834 = out_woready_1_688 & out_womask_834; // @[RegisterRouter.scala:87:24] wire _out_T_8201 = ~out_rimask_834; // @[RegisterRouter.scala:87:24] wire _out_T_8202 = ~out_wimask_834; // @[RegisterRouter.scala:87:24] wire _out_T_8203 = ~out_romask_834; // @[RegisterRouter.scala:87:24] wire _out_T_8204 = ~out_womask_834; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_711 = {hi_944, flags_0_go, _out_prepend_T_711}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8205 = out_prepend_711; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8206 = _out_T_8205; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_245 = _out_T_8206; // @[MuxLiteral.scala:49:48] wire out_rimask_835 = \|_out_rimask_T_835; // @[RegisterRouter.scala:87:24] wire out_wimask_835 = &_out_wimask_T_835; // @[RegisterRouter.scala:87:24] wire out_romask_835 = \|_out_romask_T_835; // @[RegisterRouter.scala:87:24] wire out_womask_835 = &_out_womask_T_835; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_835 = out_rivalid_1_689 & out_rimask_835; // @[RegisterRouter.scala:87:24] wire _out_T_8208 = out_f_rivalid_835; // @[RegisterRouter.scala:87:24] wire out_f_roready_835 = out_roready_1_689 & out_romask_835; // @[RegisterRouter.scala:87:24] wire _out_T_8209 = out_f_roready_835; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_835 = out_wivalid_1_689 & out_wimask_835; // @[RegisterRouter.scala:87:24] wire out_f_woready_835 = out_woready_1_689 & out_womask_835; // @[RegisterRouter.scala:87:24] wire _out_T_8210 = ~out_rimask_835; // @[RegisterRouter.scala:87:24] wire _out_T_8211 = ~out_wimask_835; // @[RegisterRouter.scala:87:24] wire _out_T_8212 = ~out_romask_835; // @[RegisterRouter.scala:87:24] wire _out_T_8213 = ~out_womask_835; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8215 = _out_T_8214; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_712 = _out_T_8215; // @[RegisterRouter.scala:87:24] wire out_rimask_836 = \|_out_rimask_T_836; // @[RegisterRouter.scala:87:24] wire out_wimask_836 = &_out_wimask_T_836; // @[RegisterRouter.scala:87:24] wire out_romask_836 = \|_out_romask_T_836; // @[RegisterRouter.scala:87:24] wire out_womask_836 = &_out_womask_T_836; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_836 = out_rivalid_1_690 & out_rimask_836; // @[RegisterRouter.scala:87:24] wire _out_T_8217 = out_f_rivalid_836; // @[RegisterRouter.scala:87:24] wire out_f_roready_836 = out_roready_1_690 & out_romask_836; // @[RegisterRouter.scala:87:24] wire _out_T_8218 = out_f_roready_836; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_836 = out_wivalid_1_690 & out_wimask_836; // @[RegisterRouter.scala:87:24] wire out_f_woready_836 = out_woready_1_690 & out_womask_836; // @[RegisterRouter.scala:87:24] wire _out_T_8219 = ~out_rimask_836; // @[RegisterRouter.scala:87:24] wire _out_T_8220 = ~out_wimask_836; // @[RegisterRouter.scala:87:24] wire _out_T_8221 = ~out_romask_836; // @[RegisterRouter.scala:87:24] wire _out_T_8222 = ~out_womask_836; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_712 = {hi_642, flags_0_go, _out_prepend_T_712}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8223 = out_prepend_712; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8224 = _out_T_8223; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_713 = _out_T_8224; // @[RegisterRouter.scala:87:24] wire out_rimask_837 = \|_out_rimask_T_837; // @[RegisterRouter.scala:87:24] wire out_wimask_837 = &_out_wimask_T_837; // @[RegisterRouter.scala:87:24] wire out_romask_837 = \|_out_romask_T_837; // @[RegisterRouter.scala:87:24] wire out_womask_837 = &_out_womask_T_837; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_837 = out_rivalid_1_691 & out_rimask_837; // @[RegisterRouter.scala:87:24] wire _out_T_8226 = out_f_rivalid_837; // @[RegisterRouter.scala:87:24] wire out_f_roready_837 = out_roready_1_691 & out_romask_837; // @[RegisterRouter.scala:87:24] wire _out_T_8227 = out_f_roready_837; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_837 = out_wivalid_1_691 & out_wimask_837; // @[RegisterRouter.scala:87:24] wire out_f_woready_837 = out_woready_1_691 & out_womask_837; // @[RegisterRouter.scala:87:24] wire _out_T_8228 = ~out_rimask_837; // @[RegisterRouter.scala:87:24] wire _out_T_8229 = ~out_wimask_837; // @[RegisterRouter.scala:87:24] wire _out_T_8230 = ~out_romask_837; // @[RegisterRouter.scala:87:24] wire _out_T_8231 = ~out_womask_837; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_713 = {hi_643, flags_0_go, _out_prepend_T_713}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8232 = out_prepend_713; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8233 = _out_T_8232; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_714 = _out_T_8233; // @[RegisterRouter.scala:87:24] wire out_rimask_838 = \|_out_rimask_T_838; // @[RegisterRouter.scala:87:24] wire out_wimask_838 = &_out_wimask_T_838; // @[RegisterRouter.scala:87:24] wire out_romask_838 = \|_out_romask_T_838; // @[RegisterRouter.scala:87:24] wire out_womask_838 = &_out_womask_T_838; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_838 = out_rivalid_1_692 & out_rimask_838; // @[RegisterRouter.scala:87:24] wire _out_T_8235 = out_f_rivalid_838; // @[RegisterRouter.scala:87:24] wire out_f_roready_838 = out_roready_1_692 & out_romask_838; // @[RegisterRouter.scala:87:24] wire _out_T_8236 = out_f_roready_838; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_838 = out_wivalid_1_692 & out_wimask_838; // @[RegisterRouter.scala:87:24] wire out_f_woready_838 = out_woready_1_692 & out_womask_838; // @[RegisterRouter.scala:87:24] wire _out_T_8237 = ~out_rimask_838; // @[RegisterRouter.scala:87:24] wire _out_T_8238 = ~out_wimask_838; // @[RegisterRouter.scala:87:24] wire _out_T_8239 = ~out_romask_838; // @[RegisterRouter.scala:87:24] wire _out_T_8240 = ~out_womask_838; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_714 = {hi_644, flags_0_go, _out_prepend_T_714}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8241 = out_prepend_714; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8242 = _out_T_8241; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_715 = _out_T_8242; // @[RegisterRouter.scala:87:24] wire out_rimask_839 = \|_out_rimask_T_839; // @[RegisterRouter.scala:87:24] wire out_wimask_839 = &_out_wimask_T_839; // @[RegisterRouter.scala:87:24] wire out_romask_839 = \|_out_romask_T_839; // @[RegisterRouter.scala:87:24] wire out_womask_839 = &_out_womask_T_839; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_839 = out_rivalid_1_693 & out_rimask_839; // @[RegisterRouter.scala:87:24] wire _out_T_8244 = out_f_rivalid_839; // @[RegisterRouter.scala:87:24] wire out_f_roready_839 = out_roready_1_693 & out_romask_839; // @[RegisterRouter.scala:87:24] wire _out_T_8245 = out_f_roready_839; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_839 = out_wivalid_1_693 & out_wimask_839; // @[RegisterRouter.scala:87:24] wire out_f_woready_839 = out_woready_1_693 & out_womask_839; // @[RegisterRouter.scala:87:24] wire _out_T_8246 = ~out_rimask_839; // @[RegisterRouter.scala:87:24] wire _out_T_8247 = ~out_wimask_839; // @[RegisterRouter.scala:87:24] wire _out_T_8248 = ~out_romask_839; // @[RegisterRouter.scala:87:24] wire _out_T_8249 = ~out_womask_839; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_715 = {hi_645, flags_0_go, _out_prepend_T_715}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8250 = out_prepend_715; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8251 = _out_T_8250; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_716 = _out_T_8251; // @[RegisterRouter.scala:87:24] wire out_rimask_840 = \|_out_rimask_T_840; // @[RegisterRouter.scala:87:24] wire out_wimask_840 = &_out_wimask_T_840; // @[RegisterRouter.scala:87:24] wire out_romask_840 = \|_out_romask_T_840; // @[RegisterRouter.scala:87:24] wire out_womask_840 = &_out_womask_T_840; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_840 = out_rivalid_1_694 & out_rimask_840; // @[RegisterRouter.scala:87:24] wire _out_T_8253 = out_f_rivalid_840; // @[RegisterRouter.scala:87:24] wire out_f_roready_840 = out_roready_1_694 & out_romask_840; // @[RegisterRouter.scala:87:24] wire _out_T_8254 = out_f_roready_840; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_840 = out_wivalid_1_694 & out_wimask_840; // @[RegisterRouter.scala:87:24] wire out_f_woready_840 = out_woready_1_694 & out_womask_840; // @[RegisterRouter.scala:87:24] wire _out_T_8255 = ~out_rimask_840; // @[RegisterRouter.scala:87:24] wire _out_T_8256 = ~out_wimask_840; // @[RegisterRouter.scala:87:24] wire _out_T_8257 = ~out_romask_840; // @[RegisterRouter.scala:87:24] wire _out_T_8258 = ~out_womask_840; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_716 = {hi_646, flags_0_go, _out_prepend_T_716}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8259 = out_prepend_716; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8260 = _out_T_8259; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_717 = _out_T_8260; // @[RegisterRouter.scala:87:24] wire out_rimask_841 = \|_out_rimask_T_841; // @[RegisterRouter.scala:87:24] wire out_wimask_841 = &_out_wimask_T_841; // @[RegisterRouter.scala:87:24] wire out_romask_841 = \|_out_romask_T_841; // @[RegisterRouter.scala:87:24] wire out_womask_841 = &_out_womask_T_841; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_841 = out_rivalid_1_695 & out_rimask_841; // @[RegisterRouter.scala:87:24] wire _out_T_8262 = out_f_rivalid_841; // @[RegisterRouter.scala:87:24] wire out_f_roready_841 = out_roready_1_695 & out_romask_841; // @[RegisterRouter.scala:87:24] wire _out_T_8263 = out_f_roready_841; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_841 = out_wivalid_1_695 & out_wimask_841; // @[RegisterRouter.scala:87:24] wire out_f_woready_841 = out_woready_1_695 & out_womask_841; // @[RegisterRouter.scala:87:24] wire _out_T_8264 = ~out_rimask_841; // @[RegisterRouter.scala:87:24] wire _out_T_8265 = ~out_wimask_841; // @[RegisterRouter.scala:87:24] wire _out_T_8266 = ~out_romask_841; // @[RegisterRouter.scala:87:24] wire _out_T_8267 = ~out_womask_841; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_717 = {hi_647, flags_0_go, _out_prepend_T_717}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8268 = out_prepend_717; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8269 = _out_T_8268; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_718 = _out_T_8269; // @[RegisterRouter.scala:87:24] wire out_rimask_842 = \|_out_rimask_T_842; // @[RegisterRouter.scala:87:24] wire out_wimask_842 = &_out_wimask_T_842; // @[RegisterRouter.scala:87:24] wire out_romask_842 = \|_out_romask_T_842; // @[RegisterRouter.scala:87:24] wire out_womask_842 = &_out_womask_T_842; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_842 = out_rivalid_1_696 & out_rimask_842; // @[RegisterRouter.scala:87:24] wire _out_T_8271 = out_f_rivalid_842; // @[RegisterRouter.scala:87:24] wire out_f_roready_842 = out_roready_1_696 & out_romask_842; // @[RegisterRouter.scala:87:24] wire _out_T_8272 = out_f_roready_842; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_842 = out_wivalid_1_696 & out_wimask_842; // @[RegisterRouter.scala:87:24] wire out_f_woready_842 = out_woready_1_696 & out_womask_842; // @[RegisterRouter.scala:87:24] wire _out_T_8273 = ~out_rimask_842; // @[RegisterRouter.scala:87:24] wire _out_T_8274 = ~out_wimask_842; // @[RegisterRouter.scala:87:24] wire _out_T_8275 = ~out_romask_842; // @[RegisterRouter.scala:87:24] wire _out_T_8276 = ~out_womask_842; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_718 = {hi_648, flags_0_go, _out_prepend_T_718}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8277 = out_prepend_718; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8278 = _out_T_8277; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_208 = _out_T_8278; // @[MuxLiteral.scala:49:48] wire out_rimask_843 = \|_out_rimask_T_843; // @[RegisterRouter.scala:87:24] wire out_wimask_843 = &_out_wimask_T_843; // @[RegisterRouter.scala:87:24] wire out_romask_843 = \|_out_romask_T_843; // @[RegisterRouter.scala:87:24] wire out_womask_843 = &_out_womask_T_843; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_843 = out_rivalid_1_697 & out_rimask_843; // @[RegisterRouter.scala:87:24] wire _out_T_8280 = out_f_rivalid_843; // @[RegisterRouter.scala:87:24] wire out_f_roready_843 = out_roready_1_697 & out_romask_843; // @[RegisterRouter.scala:87:24] wire _out_T_8281 = out_f_roready_843; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_843 = out_wivalid_1_697 & out_wimask_843; // @[RegisterRouter.scala:87:24] wire out_f_woready_843 = out_woready_1_697 & out_womask_843; // @[RegisterRouter.scala:87:24] wire _out_T_8282 = ~out_rimask_843; // @[RegisterRouter.scala:87:24] wire _out_T_8283 = ~out_wimask_843; // @[RegisterRouter.scala:87:24] wire _out_T_8284 = ~out_romask_843; // @[RegisterRouter.scala:87:24] wire _out_T_8285 = ~out_womask_843; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8287 = _out_T_8286; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_719 = _out_T_8287; // @[RegisterRouter.scala:87:24] wire [31:0] _out_rimask_T_844 = out_frontMask_1[63:32]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_wimask_T_844 = out_frontMask_1[63:32]; // @[RegisterRouter.scala:87:24] wire out_rimask_844 = \|_out_rimask_T_844; // @[RegisterRouter.scala:87:24] wire out_wimask_844 = &_out_wimask_T_844; // @[RegisterRouter.scala:87:24] wire [31:0] _out_romask_T_844 = out_backMask_1[63:32]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_womask_T_844 = out_backMask_1[63:32]; // @[RegisterRouter.scala:87:24] wire out_romask_844 = \|_out_romask_T_844; // @[RegisterRouter.scala:87:24] wire out_womask_844 = &_out_womask_T_844; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_844 = out_rivalid_1_698 & out_rimask_844; // @[RegisterRouter.scala:87:24] wire _out_T_8289 = out_f_rivalid_844; // @[RegisterRouter.scala:87:24] wire out_f_roready_844 = out_roready_1_698 & out_romask_844; // @[RegisterRouter.scala:87:24] wire _out_T_8290 = out_f_roready_844; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_844 = out_wivalid_1_698 & out_wimask_844; // @[RegisterRouter.scala:87:24] wire out_f_woready_844 = out_woready_1_698 & out_womask_844; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8288 = out_front_1_bits_data[63:32]; // @[RegisterRouter.scala:87:24] wire _out_T_8291 = ~out_rimask_844; // @[RegisterRouter.scala:87:24] wire _out_T_8292 = ~out_wimask_844; // @[RegisterRouter.scala:87:24] wire _out_T_8293 = ~out_romask_844; // @[RegisterRouter.scala:87:24] wire _out_T_8294 = ~out_womask_844; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_719 = {abstractGeneratedMem_1, _out_prepend_T_719}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8295 = out_prepend_719; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8296 = _out_T_8295; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_103 = _out_T_8296; // @[MuxLiteral.scala:49:48] wire out_rimask_845 = \|_out_rimask_T_845; // @[RegisterRouter.scala:87:24] wire out_wimask_845 = &_out_wimask_T_845; // @[RegisterRouter.scala:87:24] wire out_romask_845 = \|_out_romask_T_845; // @[RegisterRouter.scala:87:24] wire out_womask_845 = &_out_womask_T_845; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_845 = out_rivalid_1_699 & out_rimask_845; // @[RegisterRouter.scala:87:24] wire _out_T_8298 = out_f_rivalid_845; // @[RegisterRouter.scala:87:24] wire out_f_roready_845 = out_roready_1_699 & out_romask_845; // @[RegisterRouter.scala:87:24] wire _out_T_8299 = out_f_roready_845; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_845 = out_wivalid_1_699 & out_wimask_845; // @[RegisterRouter.scala:87:24] wire out_f_woready_845 = out_woready_1_699 & out_womask_845; // @[RegisterRouter.scala:87:24] wire _out_T_8300 = ~out_rimask_845; // @[RegisterRouter.scala:87:24] wire _out_T_8301 = ~out_wimask_845; // @[RegisterRouter.scala:87:24] wire _out_T_8302 = ~out_romask_845; // @[RegisterRouter.scala:87:24] wire _out_T_8303 = ~out_womask_845; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8305 = _out_T_8304; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_720 = _out_T_8305; // @[RegisterRouter.scala:87:24] wire out_rimask_846 = \|_out_rimask_T_846; // @[RegisterRouter.scala:87:24] wire out_wimask_846 = &_out_wimask_T_846; // @[RegisterRouter.scala:87:24] wire out_romask_846 = \|_out_romask_T_846; // @[RegisterRouter.scala:87:24] wire out_womask_846 = &_out_womask_T_846; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_846 = out_rivalid_1_700 & out_rimask_846; // @[RegisterRouter.scala:87:24] wire _out_T_8307 = out_f_rivalid_846; // @[RegisterRouter.scala:87:24] wire out_f_roready_846 = out_roready_1_700 & out_romask_846; // @[RegisterRouter.scala:87:24] wire _out_T_8308 = out_f_roready_846; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_846 = out_wivalid_1_700 & out_wimask_846; // @[RegisterRouter.scala:87:24] wire out_f_woready_846 = out_woready_1_700 & out_womask_846; // @[RegisterRouter.scala:87:24] wire _out_T_8309 = ~out_rimask_846; // @[RegisterRouter.scala:87:24] wire _out_T_8310 = ~out_wimask_846; // @[RegisterRouter.scala:87:24] wire _out_T_8311 = ~out_romask_846; // @[RegisterRouter.scala:87:24] wire _out_T_8312 = ~out_womask_846; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_720 = {hi_98, flags_0_go, _out_prepend_T_720}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8313 = out_prepend_720; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8314 = _out_T_8313; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_721 = _out_T_8314; // @[RegisterRouter.scala:87:24] wire out_rimask_847 = \|_out_rimask_T_847; // @[RegisterRouter.scala:87:24] wire out_wimask_847 = &_out_wimask_T_847; // @[RegisterRouter.scala:87:24] wire out_romask_847 = \|_out_romask_T_847; // @[RegisterRouter.scala:87:24] wire out_womask_847 = &_out_womask_T_847; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_847 = out_rivalid_1_701 & out_rimask_847; // @[RegisterRouter.scala:87:24] wire _out_T_8316 = out_f_rivalid_847; // @[RegisterRouter.scala:87:24] wire out_f_roready_847 = out_roready_1_701 & out_romask_847; // @[RegisterRouter.scala:87:24] wire _out_T_8317 = out_f_roready_847; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_847 = out_wivalid_1_701 & out_wimask_847; // @[RegisterRouter.scala:87:24] wire out_f_woready_847 = out_woready_1_701 & out_womask_847; // @[RegisterRouter.scala:87:24] wire _out_T_8318 = ~out_rimask_847; // @[RegisterRouter.scala:87:24] wire _out_T_8319 = ~out_wimask_847; // @[RegisterRouter.scala:87:24] wire _out_T_8320 = ~out_romask_847; // @[RegisterRouter.scala:87:24] wire _out_T_8321 = ~out_womask_847; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_721 = {hi_99, flags_0_go, _out_prepend_T_721}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8322 = out_prepend_721; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8323 = _out_T_8322; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_722 = _out_T_8323; // @[RegisterRouter.scala:87:24] wire out_rimask_848 = \|_out_rimask_T_848; // @[RegisterRouter.scala:87:24] wire out_wimask_848 = &_out_wimask_T_848; // @[RegisterRouter.scala:87:24] wire out_romask_848 = \|_out_romask_T_848; // @[RegisterRouter.scala:87:24] wire out_womask_848 = &_out_womask_T_848; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_848 = out_rivalid_1_702 & out_rimask_848; // @[RegisterRouter.scala:87:24] wire _out_T_8325 = out_f_rivalid_848; // @[RegisterRouter.scala:87:24] wire out_f_roready_848 = out_roready_1_702 & out_romask_848; // @[RegisterRouter.scala:87:24] wire _out_T_8326 = out_f_roready_848; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_848 = out_wivalid_1_702 & out_wimask_848; // @[RegisterRouter.scala:87:24] wire out_f_woready_848 = out_woready_1_702 & out_womask_848; // @[RegisterRouter.scala:87:24] wire _out_T_8327 = ~out_rimask_848; // @[RegisterRouter.scala:87:24] wire _out_T_8328 = ~out_wimask_848; // @[RegisterRouter.scala:87:24] wire _out_T_8329 = ~out_romask_848; // @[RegisterRouter.scala:87:24] wire _out_T_8330 = ~out_womask_848; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_722 = {hi_100, flags_0_go, _out_prepend_T_722}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8331 = out_prepend_722; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8332 = _out_T_8331; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_723 = _out_T_8332; // @[RegisterRouter.scala:87:24] wire out_rimask_849 = \|_out_rimask_T_849; // @[RegisterRouter.scala:87:24] wire out_wimask_849 = &_out_wimask_T_849; // @[RegisterRouter.scala:87:24] wire out_romask_849 = \|_out_romask_T_849; // @[RegisterRouter.scala:87:24] wire out_womask_849 = &_out_womask_T_849; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_849 = out_rivalid_1_703 & out_rimask_849; // @[RegisterRouter.scala:87:24] wire _out_T_8334 = out_f_rivalid_849; // @[RegisterRouter.scala:87:24] wire out_f_roready_849 = out_roready_1_703 & out_romask_849; // @[RegisterRouter.scala:87:24] wire _out_T_8335 = out_f_roready_849; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_849 = out_wivalid_1_703 & out_wimask_849; // @[RegisterRouter.scala:87:24] wire out_f_woready_849 = out_woready_1_703 & out_womask_849; // @[RegisterRouter.scala:87:24] wire _out_T_8336 = ~out_rimask_849; // @[RegisterRouter.scala:87:24] wire _out_T_8337 = ~out_wimask_849; // @[RegisterRouter.scala:87:24] wire _out_T_8338 = ~out_romask_849; // @[RegisterRouter.scala:87:24] wire _out_T_8339 = ~out_womask_849; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_723 = {hi_101, flags_0_go, _out_prepend_T_723}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8340 = out_prepend_723; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8341 = _out_T_8340; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_724 = _out_T_8341; // @[RegisterRouter.scala:87:24] wire out_rimask_850 = \|_out_rimask_T_850; // @[RegisterRouter.scala:87:24] wire out_wimask_850 = &_out_wimask_T_850; // @[RegisterRouter.scala:87:24] wire out_romask_850 = \|_out_romask_T_850; // @[RegisterRouter.scala:87:24] wire out_womask_850 = &_out_womask_T_850; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_850 = out_rivalid_1_704 & out_rimask_850; // @[RegisterRouter.scala:87:24] wire _out_T_8343 = out_f_rivalid_850; // @[RegisterRouter.scala:87:24] wire out_f_roready_850 = out_roready_1_704 & out_romask_850; // @[RegisterRouter.scala:87:24] wire _out_T_8344 = out_f_roready_850; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_850 = out_wivalid_1_704 & out_wimask_850; // @[RegisterRouter.scala:87:24] wire out_f_woready_850 = out_woready_1_704 & out_womask_850; // @[RegisterRouter.scala:87:24] wire _out_T_8345 = ~out_rimask_850; // @[RegisterRouter.scala:87:24] wire _out_T_8346 = ~out_wimask_850; // @[RegisterRouter.scala:87:24] wire _out_T_8347 = ~out_romask_850; // @[RegisterRouter.scala:87:24] wire _out_T_8348 = ~out_womask_850; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_724 = {hi_102, flags_0_go, _out_prepend_T_724}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8349 = out_prepend_724; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8350 = _out_T_8349; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_725 = _out_T_8350; // @[RegisterRouter.scala:87:24] wire out_rimask_851 = \|_out_rimask_T_851; // @[RegisterRouter.scala:87:24] wire out_wimask_851 = &_out_wimask_T_851; // @[RegisterRouter.scala:87:24] wire out_romask_851 = \|_out_romask_T_851; // @[RegisterRouter.scala:87:24] wire out_womask_851 = &_out_womask_T_851; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_851 = out_rivalid_1_705 & out_rimask_851; // @[RegisterRouter.scala:87:24] wire _out_T_8352 = out_f_rivalid_851; // @[RegisterRouter.scala:87:24] wire out_f_roready_851 = out_roready_1_705 & out_romask_851; // @[RegisterRouter.scala:87:24] wire _out_T_8353 = out_f_roready_851; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_851 = out_wivalid_1_705 & out_wimask_851; // @[RegisterRouter.scala:87:24] wire out_f_woready_851 = out_woready_1_705 & out_womask_851; // @[RegisterRouter.scala:87:24] wire _out_T_8354 = ~out_rimask_851; // @[RegisterRouter.scala:87:24] wire _out_T_8355 = ~out_wimask_851; // @[RegisterRouter.scala:87:24] wire _out_T_8356 = ~out_romask_851; // @[RegisterRouter.scala:87:24] wire _out_T_8357 = ~out_womask_851; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_725 = {hi_103, flags_0_go, _out_prepend_T_725}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8358 = out_prepend_725; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8359 = _out_T_8358; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_726 = _out_T_8359; // @[RegisterRouter.scala:87:24] wire out_rimask_852 = \|_out_rimask_T_852; // @[RegisterRouter.scala:87:24] wire out_wimask_852 = &_out_wimask_T_852; // @[RegisterRouter.scala:87:24] wire out_romask_852 = \|_out_romask_T_852; // @[RegisterRouter.scala:87:24] wire out_womask_852 = &_out_womask_T_852; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_852 = out_rivalid_1_706 & out_rimask_852; // @[RegisterRouter.scala:87:24] wire _out_T_8361 = out_f_rivalid_852; // @[RegisterRouter.scala:87:24] wire out_f_roready_852 = out_roready_1_706 & out_romask_852; // @[RegisterRouter.scala:87:24] wire _out_T_8362 = out_f_roready_852; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_852 = out_wivalid_1_706 & out_wimask_852; // @[RegisterRouter.scala:87:24] wire out_f_woready_852 = out_woready_1_706 & out_womask_852; // @[RegisterRouter.scala:87:24] wire _out_T_8363 = ~out_rimask_852; // @[RegisterRouter.scala:87:24] wire _out_T_8364 = ~out_wimask_852; // @[RegisterRouter.scala:87:24] wire _out_T_8365 = ~out_romask_852; // @[RegisterRouter.scala:87:24] wire _out_T_8366 = ~out_womask_852; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_726 = {hi_104, flags_0_go, _out_prepend_T_726}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8367 = out_prepend_726; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8368 = _out_T_8367; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_140 = _out_T_8368; // @[MuxLiteral.scala:49:48] wire out_rimask_853 = \|_out_rimask_T_853; // @[RegisterRouter.scala:87:24] wire out_wimask_853 = &_out_wimask_T_853; // @[RegisterRouter.scala:87:24] wire out_romask_853 = \|_out_romask_T_853; // @[RegisterRouter.scala:87:24] wire out_womask_853 = &_out_womask_T_853; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_853 = out_rivalid_1_707 & out_rimask_853; // @[RegisterRouter.scala:87:24] wire _out_T_8370 = out_f_rivalid_853; // @[RegisterRouter.scala:87:24] wire out_f_roready_853 = out_roready_1_707 & out_romask_853; // @[RegisterRouter.scala:87:24] wire _out_T_8371 = out_f_roready_853; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_853 = out_wivalid_1_707 & out_wimask_853; // @[RegisterRouter.scala:87:24] wire out_f_woready_853 = out_woready_1_707 & out_womask_853; // @[RegisterRouter.scala:87:24] wire _out_T_8372 = ~out_rimask_853; // @[RegisterRouter.scala:87:24] wire _out_T_8373 = ~out_wimask_853; // @[RegisterRouter.scala:87:24] wire _out_T_8374 = ~out_romask_853; // @[RegisterRouter.scala:87:24] wire _out_T_8375 = ~out_womask_853; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8377 = _out_T_8376; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_727 = _out_T_8377; // @[RegisterRouter.scala:87:24] wire out_rimask_854 = \|_out_rimask_T_854; // @[RegisterRouter.scala:87:24] wire out_wimask_854 = &_out_wimask_T_854; // @[RegisterRouter.scala:87:24] wire out_romask_854 = \|_out_romask_T_854; // @[RegisterRouter.scala:87:24] wire out_womask_854 = &_out_womask_T_854; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_854 = out_rivalid_1_708 & out_rimask_854; // @[RegisterRouter.scala:87:24] wire _out_T_8379 = out_f_rivalid_854; // @[RegisterRouter.scala:87:24] wire out_f_roready_854 = out_roready_1_708 & out_romask_854; // @[RegisterRouter.scala:87:24] wire _out_T_8380 = out_f_roready_854; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_854 = out_wivalid_1_708 & out_wimask_854; // @[RegisterRouter.scala:87:24] wire out_f_woready_854 = out_woready_1_708 & out_womask_854; // @[RegisterRouter.scala:87:24] wire _out_T_8381 = ~out_rimask_854; // @[RegisterRouter.scala:87:24] wire _out_T_8382 = ~out_wimask_854; // @[RegisterRouter.scala:87:24] wire _out_T_8383 = ~out_romask_854; // @[RegisterRouter.scala:87:24] wire _out_T_8384 = ~out_womask_854; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_727 = {hi_682, flags_0_go, _out_prepend_T_727}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8385 = out_prepend_727; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8386 = _out_T_8385; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_728 = _out_T_8386; // @[RegisterRouter.scala:87:24] wire out_rimask_855 = \|_out_rimask_T_855; // @[RegisterRouter.scala:87:24] wire out_wimask_855 = &_out_wimask_T_855; // @[RegisterRouter.scala:87:24] wire out_romask_855 = \|_out_romask_T_855; // @[RegisterRouter.scala:87:24] wire out_womask_855 = &_out_womask_T_855; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_855 = out_rivalid_1_709 & out_rimask_855; // @[RegisterRouter.scala:87:24] wire _out_T_8388 = out_f_rivalid_855; // @[RegisterRouter.scala:87:24] wire out_f_roready_855 = out_roready_1_709 & out_romask_855; // @[RegisterRouter.scala:87:24] wire _out_T_8389 = out_f_roready_855; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_855 = out_wivalid_1_709 & out_wimask_855; // @[RegisterRouter.scala:87:24] wire out_f_woready_855 = out_woready_1_709 & out_womask_855; // @[RegisterRouter.scala:87:24] wire _out_T_8390 = ~out_rimask_855; // @[RegisterRouter.scala:87:24] wire _out_T_8391 = ~out_wimask_855; // @[RegisterRouter.scala:87:24] wire _out_T_8392 = ~out_romask_855; // @[RegisterRouter.scala:87:24] wire _out_T_8393 = ~out_womask_855; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_728 = {hi_683, flags_0_go, _out_prepend_T_728}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8394 = out_prepend_728; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8395 = _out_T_8394; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_729 = _out_T_8395; // @[RegisterRouter.scala:87:24] wire out_rimask_856 = \|_out_rimask_T_856; // @[RegisterRouter.scala:87:24] wire out_wimask_856 = &_out_wimask_T_856; // @[RegisterRouter.scala:87:24] wire out_romask_856 = \|_out_romask_T_856; // @[RegisterRouter.scala:87:24] wire out_womask_856 = &_out_womask_T_856; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_856 = out_rivalid_1_710 & out_rimask_856; // @[RegisterRouter.scala:87:24] wire _out_T_8397 = out_f_rivalid_856; // @[RegisterRouter.scala:87:24] wire out_f_roready_856 = out_roready_1_710 & out_romask_856; // @[RegisterRouter.scala:87:24] wire _out_T_8398 = out_f_roready_856; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_856 = out_wivalid_1_710 & out_wimask_856; // @[RegisterRouter.scala:87:24] wire out_f_woready_856 = out_woready_1_710 & out_womask_856; // @[RegisterRouter.scala:87:24] wire _out_T_8399 = ~out_rimask_856; // @[RegisterRouter.scala:87:24] wire _out_T_8400 = ~out_wimask_856; // @[RegisterRouter.scala:87:24] wire _out_T_8401 = ~out_romask_856; // @[RegisterRouter.scala:87:24] wire _out_T_8402 = ~out_womask_856; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_729 = {hi_684, flags_0_go, _out_prepend_T_729}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8403 = out_prepend_729; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8404 = _out_T_8403; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_730 = _out_T_8404; // @[RegisterRouter.scala:87:24] wire out_rimask_857 = \|_out_rimask_T_857; // @[RegisterRouter.scala:87:24] wire out_wimask_857 = &_out_wimask_T_857; // @[RegisterRouter.scala:87:24] wire out_romask_857 = \|_out_romask_T_857; // @[RegisterRouter.scala:87:24] wire out_womask_857 = &_out_womask_T_857; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_857 = out_rivalid_1_711 & out_rimask_857; // @[RegisterRouter.scala:87:24] wire _out_T_8406 = out_f_rivalid_857; // @[RegisterRouter.scala:87:24] wire out_f_roready_857 = out_roready_1_711 & out_romask_857; // @[RegisterRouter.scala:87:24] wire _out_T_8407 = out_f_roready_857; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_857 = out_wivalid_1_711 & out_wimask_857; // @[RegisterRouter.scala:87:24] wire out_f_woready_857 = out_woready_1_711 & out_womask_857; // @[RegisterRouter.scala:87:24] wire _out_T_8408 = ~out_rimask_857; // @[RegisterRouter.scala:87:24] wire _out_T_8409 = ~out_wimask_857; // @[RegisterRouter.scala:87:24] wire _out_T_8410 = ~out_romask_857; // @[RegisterRouter.scala:87:24] wire _out_T_8411 = ~out_womask_857; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_730 = {hi_685, flags_0_go, _out_prepend_T_730}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8412 = out_prepend_730; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8413 = _out_T_8412; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_731 = _out_T_8413; // @[RegisterRouter.scala:87:24] wire out_rimask_858 = \|_out_rimask_T_858; // @[RegisterRouter.scala:87:24] wire out_wimask_858 = &_out_wimask_T_858; // @[RegisterRouter.scala:87:24] wire out_romask_858 = \|_out_romask_T_858; // @[RegisterRouter.scala:87:24] wire out_womask_858 = &_out_womask_T_858; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_858 = out_rivalid_1_712 & out_rimask_858; // @[RegisterRouter.scala:87:24] wire _out_T_8415 = out_f_rivalid_858; // @[RegisterRouter.scala:87:24] wire out_f_roready_858 = out_roready_1_712 & out_romask_858; // @[RegisterRouter.scala:87:24] wire _out_T_8416 = out_f_roready_858; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_858 = out_wivalid_1_712 & out_wimask_858; // @[RegisterRouter.scala:87:24] wire out_f_woready_858 = out_woready_1_712 & out_womask_858; // @[RegisterRouter.scala:87:24] wire _out_T_8417 = ~out_rimask_858; // @[RegisterRouter.scala:87:24] wire _out_T_8418 = ~out_wimask_858; // @[RegisterRouter.scala:87:24] wire _out_T_8419 = ~out_romask_858; // @[RegisterRouter.scala:87:24] wire _out_T_8420 = ~out_womask_858; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_731 = {hi_686, flags_0_go, _out_prepend_T_731}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8421 = out_prepend_731; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8422 = _out_T_8421; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_732 = _out_T_8422; // @[RegisterRouter.scala:87:24] wire out_rimask_859 = \|_out_rimask_T_859; // @[RegisterRouter.scala:87:24] wire out_wimask_859 = &_out_wimask_T_859; // @[RegisterRouter.scala:87:24] wire out_romask_859 = \|_out_romask_T_859; // @[RegisterRouter.scala:87:24] wire out_womask_859 = &_out_womask_T_859; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_859 = out_rivalid_1_713 & out_rimask_859; // @[RegisterRouter.scala:87:24] wire _out_T_8424 = out_f_rivalid_859; // @[RegisterRouter.scala:87:24] wire out_f_roready_859 = out_roready_1_713 & out_romask_859; // @[RegisterRouter.scala:87:24] wire _out_T_8425 = out_f_roready_859; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_859 = out_wivalid_1_713 & out_wimask_859; // @[RegisterRouter.scala:87:24] wire out_f_woready_859 = out_woready_1_713 & out_womask_859; // @[RegisterRouter.scala:87:24] wire _out_T_8426 = ~out_rimask_859; // @[RegisterRouter.scala:87:24] wire _out_T_8427 = ~out_wimask_859; // @[RegisterRouter.scala:87:24] wire _out_T_8428 = ~out_romask_859; // @[RegisterRouter.scala:87:24] wire _out_T_8429 = ~out_womask_859; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_732 = {hi_687, flags_0_go, _out_prepend_T_732}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8430 = out_prepend_732; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8431 = _out_T_8430; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_733 = _out_T_8431; // @[RegisterRouter.scala:87:24] wire out_rimask_860 = \|_out_rimask_T_860; // @[RegisterRouter.scala:87:24] wire out_wimask_860 = &_out_wimask_T_860; // @[RegisterRouter.scala:87:24] wire out_romask_860 = \|_out_romask_T_860; // @[RegisterRouter.scala:87:24] wire out_womask_860 = &_out_womask_T_860; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_860 = out_rivalid_1_714 & out_rimask_860; // @[RegisterRouter.scala:87:24] wire _out_T_8433 = out_f_rivalid_860; // @[RegisterRouter.scala:87:24] wire out_f_roready_860 = out_roready_1_714 & out_romask_860; // @[RegisterRouter.scala:87:24] wire _out_T_8434 = out_f_roready_860; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_860 = out_wivalid_1_714 & out_wimask_860; // @[RegisterRouter.scala:87:24] wire out_f_woready_860 = out_woready_1_714 & out_womask_860; // @[RegisterRouter.scala:87:24] wire _out_T_8435 = ~out_rimask_860; // @[RegisterRouter.scala:87:24] wire _out_T_8436 = ~out_wimask_860; // @[RegisterRouter.scala:87:24] wire _out_T_8437 = ~out_romask_860; // @[RegisterRouter.scala:87:24] wire _out_T_8438 = ~out_womask_860; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_733 = {hi_688, flags_0_go, _out_prepend_T_733}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8439 = out_prepend_733; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8440 = _out_T_8439; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_213 = _out_T_8440; // @[MuxLiteral.scala:49:48] wire out_rimask_861 = \|_out_rimask_T_861; // @[RegisterRouter.scala:87:24] wire out_wimask_861 = &_out_wimask_T_861; // @[RegisterRouter.scala:87:24] wire out_romask_861 = \|_out_romask_T_861; // @[RegisterRouter.scala:87:24] wire out_womask_861 = &_out_womask_T_861; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_861 = out_rivalid_1_715 & out_rimask_861; // @[RegisterRouter.scala:87:24] wire _out_T_8442 = out_f_rivalid_861; // @[RegisterRouter.scala:87:24] wire out_f_roready_861 = out_roready_1_715 & out_romask_861; // @[RegisterRouter.scala:87:24] wire _out_T_8443 = out_f_roready_861; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_861 = out_wivalid_1_715 & out_wimask_861; // @[RegisterRouter.scala:87:24] wire out_f_woready_861 = out_woready_1_715 & out_womask_861; // @[RegisterRouter.scala:87:24] wire _out_T_8444 = ~out_rimask_861; // @[RegisterRouter.scala:87:24] wire _out_T_8445 = ~out_wimask_861; // @[RegisterRouter.scala:87:24] wire _out_T_8446 = ~out_romask_861; // @[RegisterRouter.scala:87:24] wire _out_T_8447 = ~out_womask_861; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8449 = _out_T_8448; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_734 = _out_T_8449; // @[RegisterRouter.scala:87:24] wire out_rimask_862 = \|_out_rimask_T_862; // @[RegisterRouter.scala:87:24] wire out_wimask_862 = &_out_wimask_T_862; // @[RegisterRouter.scala:87:24] wire out_romask_862 = \|_out_romask_T_862; // @[RegisterRouter.scala:87:24] wire out_womask_862 = &_out_womask_T_862; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_862 = out_rivalid_1_716 & out_rimask_862; // @[RegisterRouter.scala:87:24] wire _out_T_8451 = out_f_rivalid_862; // @[RegisterRouter.scala:87:24] wire out_f_roready_862 = out_roready_1_716 & out_romask_862; // @[RegisterRouter.scala:87:24] wire _out_T_8452 = out_f_roready_862; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_862 = out_wivalid_1_716 & out_wimask_862; // @[RegisterRouter.scala:87:24] wire out_f_woready_862 = out_woready_1_716 & out_womask_862; // @[RegisterRouter.scala:87:24] wire _out_T_8453 = ~out_rimask_862; // @[RegisterRouter.scala:87:24] wire _out_T_8454 = ~out_wimask_862; // @[RegisterRouter.scala:87:24] wire _out_T_8455 = ~out_romask_862; // @[RegisterRouter.scala:87:24] wire _out_T_8456 = ~out_womask_862; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_734 = {hi_218, flags_0_go, _out_prepend_T_734}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8457 = out_prepend_734; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8458 = _out_T_8457; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_735 = _out_T_8458; // @[RegisterRouter.scala:87:24] wire out_rimask_863 = \|_out_rimask_T_863; // @[RegisterRouter.scala:87:24] wire out_wimask_863 = &_out_wimask_T_863; // @[RegisterRouter.scala:87:24] wire out_romask_863 = \|_out_romask_T_863; // @[RegisterRouter.scala:87:24] wire out_womask_863 = &_out_womask_T_863; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_863 = out_rivalid_1_717 & out_rimask_863; // @[RegisterRouter.scala:87:24] wire _out_T_8460 = out_f_rivalid_863; // @[RegisterRouter.scala:87:24] wire out_f_roready_863 = out_roready_1_717 & out_romask_863; // @[RegisterRouter.scala:87:24] wire _out_T_8461 = out_f_roready_863; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_863 = out_wivalid_1_717 & out_wimask_863; // @[RegisterRouter.scala:87:24] wire out_f_woready_863 = out_woready_1_717 & out_womask_863; // @[RegisterRouter.scala:87:24] wire _out_T_8462 = ~out_rimask_863; // @[RegisterRouter.scala:87:24] wire _out_T_8463 = ~out_wimask_863; // @[RegisterRouter.scala:87:24] wire _out_T_8464 = ~out_romask_863; // @[RegisterRouter.scala:87:24] wire _out_T_8465 = ~out_womask_863; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_735 = {hi_219, flags_0_go, _out_prepend_T_735}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8466 = out_prepend_735; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8467 = _out_T_8466; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_736 = _out_T_8467; // @[RegisterRouter.scala:87:24] wire out_rimask_864 = \|_out_rimask_T_864; // @[RegisterRouter.scala:87:24] wire out_wimask_864 = &_out_wimask_T_864; // @[RegisterRouter.scala:87:24] wire out_romask_864 = \|_out_romask_T_864; // @[RegisterRouter.scala:87:24] wire out_womask_864 = &_out_womask_T_864; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_864 = out_rivalid_1_718 & out_rimask_864; // @[RegisterRouter.scala:87:24] wire _out_T_8469 = out_f_rivalid_864; // @[RegisterRouter.scala:87:24] wire out_f_roready_864 = out_roready_1_718 & out_romask_864; // @[RegisterRouter.scala:87:24] wire _out_T_8470 = out_f_roready_864; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_864 = out_wivalid_1_718 & out_wimask_864; // @[RegisterRouter.scala:87:24] wire out_f_woready_864 = out_woready_1_718 & out_womask_864; // @[RegisterRouter.scala:87:24] wire _out_T_8471 = ~out_rimask_864; // @[RegisterRouter.scala:87:24] wire _out_T_8472 = ~out_wimask_864; // @[RegisterRouter.scala:87:24] wire _out_T_8473 = ~out_romask_864; // @[RegisterRouter.scala:87:24] wire _out_T_8474 = ~out_womask_864; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_736 = {hi_220, flags_0_go, _out_prepend_T_736}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8475 = out_prepend_736; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8476 = _out_T_8475; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_737 = _out_T_8476; // @[RegisterRouter.scala:87:24] wire out_rimask_865 = \|_out_rimask_T_865; // @[RegisterRouter.scala:87:24] wire out_wimask_865 = &_out_wimask_T_865; // @[RegisterRouter.scala:87:24] wire out_romask_865 = \|_out_romask_T_865; // @[RegisterRouter.scala:87:24] wire out_womask_865 = &_out_womask_T_865; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_865 = out_rivalid_1_719 & out_rimask_865; // @[RegisterRouter.scala:87:24] wire _out_T_8478 = out_f_rivalid_865; // @[RegisterRouter.scala:87:24] wire out_f_roready_865 = out_roready_1_719 & out_romask_865; // @[RegisterRouter.scala:87:24] wire _out_T_8479 = out_f_roready_865; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_865 = out_wivalid_1_719 & out_wimask_865; // @[RegisterRouter.scala:87:24] wire out_f_woready_865 = out_woready_1_719 & out_womask_865; // @[RegisterRouter.scala:87:24] wire _out_T_8480 = ~out_rimask_865; // @[RegisterRouter.scala:87:24] wire _out_T_8481 = ~out_wimask_865; // @[RegisterRouter.scala:87:24] wire _out_T_8482 = ~out_romask_865; // @[RegisterRouter.scala:87:24] wire _out_T_8483 = ~out_womask_865; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_737 = {hi_221, flags_0_go, _out_prepend_T_737}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8484 = out_prepend_737; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8485 = _out_T_8484; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_738 = _out_T_8485; // @[RegisterRouter.scala:87:24] wire out_rimask_866 = \|_out_rimask_T_866; // @[RegisterRouter.scala:87:24] wire out_wimask_866 = &_out_wimask_T_866; // @[RegisterRouter.scala:87:24] wire out_romask_866 = \|_out_romask_T_866; // @[RegisterRouter.scala:87:24] wire out_womask_866 = &_out_womask_T_866; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_866 = out_rivalid_1_720 & out_rimask_866; // @[RegisterRouter.scala:87:24] wire _out_T_8487 = out_f_rivalid_866; // @[RegisterRouter.scala:87:24] wire out_f_roready_866 = out_roready_1_720 & out_romask_866; // @[RegisterRouter.scala:87:24] wire _out_T_8488 = out_f_roready_866; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_866 = out_wivalid_1_720 & out_wimask_866; // @[RegisterRouter.scala:87:24] wire out_f_woready_866 = out_woready_1_720 & out_womask_866; // @[RegisterRouter.scala:87:24] wire _out_T_8489 = ~out_rimask_866; // @[RegisterRouter.scala:87:24] wire _out_T_8490 = ~out_wimask_866; // @[RegisterRouter.scala:87:24] wire _out_T_8491 = ~out_romask_866; // @[RegisterRouter.scala:87:24] wire _out_T_8492 = ~out_womask_866; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_738 = {hi_222, flags_0_go, _out_prepend_T_738}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8493 = out_prepend_738; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8494 = _out_T_8493; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_739 = _out_T_8494; // @[RegisterRouter.scala:87:24] wire out_rimask_867 = \|_out_rimask_T_867; // @[RegisterRouter.scala:87:24] wire out_wimask_867 = &_out_wimask_T_867; // @[RegisterRouter.scala:87:24] wire out_romask_867 = \|_out_romask_T_867; // @[RegisterRouter.scala:87:24] wire out_womask_867 = &_out_womask_T_867; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_867 = out_rivalid_1_721 & out_rimask_867; // @[RegisterRouter.scala:87:24] wire _out_T_8496 = out_f_rivalid_867; // @[RegisterRouter.scala:87:24] wire out_f_roready_867 = out_roready_1_721 & out_romask_867; // @[RegisterRouter.scala:87:24] wire _out_T_8497 = out_f_roready_867; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_867 = out_wivalid_1_721 & out_wimask_867; // @[RegisterRouter.scala:87:24] wire out_f_woready_867 = out_woready_1_721 & out_womask_867; // @[RegisterRouter.scala:87:24] wire _out_T_8498 = ~out_rimask_867; // @[RegisterRouter.scala:87:24] wire _out_T_8499 = ~out_wimask_867; // @[RegisterRouter.scala:87:24] wire _out_T_8500 = ~out_romask_867; // @[RegisterRouter.scala:87:24] wire _out_T_8501 = ~out_womask_867; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_739 = {hi_223, flags_0_go, _out_prepend_T_739}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8502 = out_prepend_739; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8503 = _out_T_8502; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_740 = _out_T_8503; // @[RegisterRouter.scala:87:24] wire out_rimask_868 = \|_out_rimask_T_868; // @[RegisterRouter.scala:87:24] wire out_wimask_868 = &_out_wimask_T_868; // @[RegisterRouter.scala:87:24] wire out_romask_868 = \|_out_romask_T_868; // @[RegisterRouter.scala:87:24] wire out_womask_868 = &_out_womask_T_868; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_868 = out_rivalid_1_722 & out_rimask_868; // @[RegisterRouter.scala:87:24] wire _out_T_8505 = out_f_rivalid_868; // @[RegisterRouter.scala:87:24] wire out_f_roready_868 = out_roready_1_722 & out_romask_868; // @[RegisterRouter.scala:87:24] wire _out_T_8506 = out_f_roready_868; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_868 = out_wivalid_1_722 & out_wimask_868; // @[RegisterRouter.scala:87:24] wire out_f_woready_868 = out_woready_1_722 & out_womask_868; // @[RegisterRouter.scala:87:24] wire _out_T_8507 = ~out_rimask_868; // @[RegisterRouter.scala:87:24] wire _out_T_8508 = ~out_wimask_868; // @[RegisterRouter.scala:87:24] wire _out_T_8509 = ~out_romask_868; // @[RegisterRouter.scala:87:24] wire _out_T_8510 = ~out_womask_868; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_740 = {hi_224, flags_0_go, _out_prepend_T_740}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8511 = out_prepend_740; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8512 = _out_T_8511; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_155 = _out_T_8512; // @[MuxLiteral.scala:49:48] wire out_rimask_869 = \|_out_rimask_T_869; // @[RegisterRouter.scala:87:24] wire out_wimask_869 = &_out_wimask_T_869; // @[RegisterRouter.scala:87:24] wire out_romask_869 = \|_out_romask_T_869; // @[RegisterRouter.scala:87:24] wire out_womask_869 = &_out_womask_T_869; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_869 = out_rivalid_1_723 & out_rimask_869; // @[RegisterRouter.scala:87:24] wire _out_T_8514 = out_f_rivalid_869; // @[RegisterRouter.scala:87:24] wire out_f_roready_869 = out_roready_1_723 & out_romask_869; // @[RegisterRouter.scala:87:24] wire _out_T_8515 = out_f_roready_869; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_869 = out_wivalid_1_723 & out_wimask_869; // @[RegisterRouter.scala:87:24] wire out_f_woready_869 = out_woready_1_723 & out_womask_869; // @[RegisterRouter.scala:87:24] wire _out_T_8516 = ~out_rimask_869; // @[RegisterRouter.scala:87:24] wire _out_T_8517 = ~out_wimask_869; // @[RegisterRouter.scala:87:24] wire _out_T_8518 = ~out_romask_869; // @[RegisterRouter.scala:87:24] wire _out_T_8519 = ~out_womask_869; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8521 = _out_T_8520; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_741 = _out_T_8521; // @[RegisterRouter.scala:87:24] wire out_rimask_870 = \|_out_rimask_T_870; // @[RegisterRouter.scala:87:24] wire out_wimask_870 = &_out_wimask_T_870; // @[RegisterRouter.scala:87:24] wire out_romask_870 = \|_out_romask_T_870; // @[RegisterRouter.scala:87:24] wire out_womask_870 = &_out_womask_T_870; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_870 = out_rivalid_1_724 & out_rimask_870; // @[RegisterRouter.scala:87:24] wire _out_T_8523 = out_f_rivalid_870; // @[RegisterRouter.scala:87:24] wire out_f_roready_870 = out_roready_1_724 & out_romask_870; // @[RegisterRouter.scala:87:24] wire _out_T_8524 = out_f_roready_870; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_870 = out_wivalid_1_724 & out_wimask_870; // @[RegisterRouter.scala:87:24] wire out_f_woready_870 = out_woready_1_724 & out_womask_870; // @[RegisterRouter.scala:87:24] wire _out_T_8525 = ~out_rimask_870; // @[RegisterRouter.scala:87:24] wire _out_T_8526 = ~out_wimask_870; // @[RegisterRouter.scala:87:24] wire _out_T_8527 = ~out_romask_870; // @[RegisterRouter.scala:87:24] wire _out_T_8528 = ~out_womask_870; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_741 = {hi_562, flags_0_go, _out_prepend_T_741}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8529 = out_prepend_741; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8530 = _out_T_8529; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_742 = _out_T_8530; // @[RegisterRouter.scala:87:24] wire out_rimask_871 = \|_out_rimask_T_871; // @[RegisterRouter.scala:87:24] wire out_wimask_871 = &_out_wimask_T_871; // @[RegisterRouter.scala:87:24] wire out_romask_871 = \|_out_romask_T_871; // @[RegisterRouter.scala:87:24] wire out_womask_871 = &_out_womask_T_871; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_871 = out_rivalid_1_725 & out_rimask_871; // @[RegisterRouter.scala:87:24] wire _out_T_8532 = out_f_rivalid_871; // @[RegisterRouter.scala:87:24] wire out_f_roready_871 = out_roready_1_725 & out_romask_871; // @[RegisterRouter.scala:87:24] wire _out_T_8533 = out_f_roready_871; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_871 = out_wivalid_1_725 & out_wimask_871; // @[RegisterRouter.scala:87:24] wire out_f_woready_871 = out_woready_1_725 & out_womask_871; // @[RegisterRouter.scala:87:24] wire _out_T_8534 = ~out_rimask_871; // @[RegisterRouter.scala:87:24] wire _out_T_8535 = ~out_wimask_871; // @[RegisterRouter.scala:87:24] wire _out_T_8536 = ~out_romask_871; // @[RegisterRouter.scala:87:24] wire _out_T_8537 = ~out_womask_871; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_742 = {hi_563, flags_0_go, _out_prepend_T_742}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8538 = out_prepend_742; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8539 = _out_T_8538; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_743 = _out_T_8539; // @[RegisterRouter.scala:87:24] wire out_rimask_872 = \|_out_rimask_T_872; // @[RegisterRouter.scala:87:24] wire out_wimask_872 = &_out_wimask_T_872; // @[RegisterRouter.scala:87:24] wire out_romask_872 = \|_out_romask_T_872; // @[RegisterRouter.scala:87:24] wire out_womask_872 = &_out_womask_T_872; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_872 = out_rivalid_1_726 & out_rimask_872; // @[RegisterRouter.scala:87:24] wire _out_T_8541 = out_f_rivalid_872; // @[RegisterRouter.scala:87:24] wire out_f_roready_872 = out_roready_1_726 & out_romask_872; // @[RegisterRouter.scala:87:24] wire _out_T_8542 = out_f_roready_872; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_872 = out_wivalid_1_726 & out_wimask_872; // @[RegisterRouter.scala:87:24] wire out_f_woready_872 = out_woready_1_726 & out_womask_872; // @[RegisterRouter.scala:87:24] wire _out_T_8543 = ~out_rimask_872; // @[RegisterRouter.scala:87:24] wire _out_T_8544 = ~out_wimask_872; // @[RegisterRouter.scala:87:24] wire _out_T_8545 = ~out_romask_872; // @[RegisterRouter.scala:87:24] wire _out_T_8546 = ~out_womask_872; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_743 = {hi_564, flags_0_go, _out_prepend_T_743}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8547 = out_prepend_743; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8548 = _out_T_8547; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_744 = _out_T_8548; // @[RegisterRouter.scala:87:24] wire out_rimask_873 = \|_out_rimask_T_873; // @[RegisterRouter.scala:87:24] wire out_wimask_873 = &_out_wimask_T_873; // @[RegisterRouter.scala:87:24] wire out_romask_873 = \|_out_romask_T_873; // @[RegisterRouter.scala:87:24] wire out_womask_873 = &_out_womask_T_873; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_873 = out_rivalid_1_727 & out_rimask_873; // @[RegisterRouter.scala:87:24] wire _out_T_8550 = out_f_rivalid_873; // @[RegisterRouter.scala:87:24] wire out_f_roready_873 = out_roready_1_727 & out_romask_873; // @[RegisterRouter.scala:87:24] wire _out_T_8551 = out_f_roready_873; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_873 = out_wivalid_1_727 & out_wimask_873; // @[RegisterRouter.scala:87:24] wire out_f_woready_873 = out_woready_1_727 & out_womask_873; // @[RegisterRouter.scala:87:24] wire _out_T_8552 = ~out_rimask_873; // @[RegisterRouter.scala:87:24] wire _out_T_8553 = ~out_wimask_873; // @[RegisterRouter.scala:87:24] wire _out_T_8554 = ~out_romask_873; // @[RegisterRouter.scala:87:24] wire _out_T_8555 = ~out_womask_873; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_744 = {hi_565, flags_0_go, _out_prepend_T_744}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8556 = out_prepend_744; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8557 = _out_T_8556; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_745 = _out_T_8557; // @[RegisterRouter.scala:87:24] wire out_rimask_874 = \|_out_rimask_T_874; // @[RegisterRouter.scala:87:24] wire out_wimask_874 = &_out_wimask_T_874; // @[RegisterRouter.scala:87:24] wire out_romask_874 = \|_out_romask_T_874; // @[RegisterRouter.scala:87:24] wire out_womask_874 = &_out_womask_T_874; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_874 = out_rivalid_1_728 & out_rimask_874; // @[RegisterRouter.scala:87:24] wire _out_T_8559 = out_f_rivalid_874; // @[RegisterRouter.scala:87:24] wire out_f_roready_874 = out_roready_1_728 & out_romask_874; // @[RegisterRouter.scala:87:24] wire _out_T_8560 = out_f_roready_874; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_874 = out_wivalid_1_728 & out_wimask_874; // @[RegisterRouter.scala:87:24] wire out_f_woready_874 = out_woready_1_728 & out_womask_874; // @[RegisterRouter.scala:87:24] wire _out_T_8561 = ~out_rimask_874; // @[RegisterRouter.scala:87:24] wire _out_T_8562 = ~out_wimask_874; // @[RegisterRouter.scala:87:24] wire _out_T_8563 = ~out_romask_874; // @[RegisterRouter.scala:87:24] wire _out_T_8564 = ~out_womask_874; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_745 = {hi_566, flags_0_go, _out_prepend_T_745}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8565 = out_prepend_745; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8566 = _out_T_8565; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_746 = _out_T_8566; // @[RegisterRouter.scala:87:24] wire out_rimask_875 = \|_out_rimask_T_875; // @[RegisterRouter.scala:87:24] wire out_wimask_875 = &_out_wimask_T_875; // @[RegisterRouter.scala:87:24] wire out_romask_875 = \|_out_romask_T_875; // @[RegisterRouter.scala:87:24] wire out_womask_875 = &_out_womask_T_875; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_875 = out_rivalid_1_729 & out_rimask_875; // @[RegisterRouter.scala:87:24] wire _out_T_8568 = out_f_rivalid_875; // @[RegisterRouter.scala:87:24] wire out_f_roready_875 = out_roready_1_729 & out_romask_875; // @[RegisterRouter.scala:87:24] wire _out_T_8569 = out_f_roready_875; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_875 = out_wivalid_1_729 & out_wimask_875; // @[RegisterRouter.scala:87:24] wire out_f_woready_875 = out_woready_1_729 & out_womask_875; // @[RegisterRouter.scala:87:24] wire _out_T_8570 = ~out_rimask_875; // @[RegisterRouter.scala:87:24] wire _out_T_8571 = ~out_wimask_875; // @[RegisterRouter.scala:87:24] wire _out_T_8572 = ~out_romask_875; // @[RegisterRouter.scala:87:24] wire _out_T_8573 = ~out_womask_875; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_746 = {hi_567, flags_0_go, _out_prepend_T_746}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8574 = out_prepend_746; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8575 = _out_T_8574; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_747 = _out_T_8575; // @[RegisterRouter.scala:87:24] wire out_rimask_876 = \|_out_rimask_T_876; // @[RegisterRouter.scala:87:24] wire out_wimask_876 = &_out_wimask_T_876; // @[RegisterRouter.scala:87:24] wire out_romask_876 = \|_out_romask_T_876; // @[RegisterRouter.scala:87:24] wire out_womask_876 = &_out_womask_T_876; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_876 = out_rivalid_1_730 & out_rimask_876; // @[RegisterRouter.scala:87:24] wire _out_T_8577 = out_f_rivalid_876; // @[RegisterRouter.scala:87:24] wire out_f_roready_876 = out_roready_1_730 & out_romask_876; // @[RegisterRouter.scala:87:24] wire _out_T_8578 = out_f_roready_876; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_876 = out_wivalid_1_730 & out_wimask_876; // @[RegisterRouter.scala:87:24] wire out_f_woready_876 = out_woready_1_730 & out_womask_876; // @[RegisterRouter.scala:87:24] wire _out_T_8579 = ~out_rimask_876; // @[RegisterRouter.scala:87:24] wire _out_T_8580 = ~out_wimask_876; // @[RegisterRouter.scala:87:24] wire _out_T_8581 = ~out_romask_876; // @[RegisterRouter.scala:87:24] wire _out_T_8582 = ~out_womask_876; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_747 = {hi_568, flags_0_go, _out_prepend_T_747}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8583 = out_prepend_747; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8584 = _out_T_8583; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_198 = _out_T_8584; // @[MuxLiteral.scala:49:48] wire out_rimask_877 = \|_out_rimask_T_877; // @[RegisterRouter.scala:87:24] wire out_wimask_877 = &_out_wimask_T_877; // @[RegisterRouter.scala:87:24] wire out_romask_877 = \|_out_romask_T_877; // @[RegisterRouter.scala:87:24] wire out_womask_877 = &_out_womask_T_877; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_877 = out_rivalid_1_731 & out_rimask_877; // @[RegisterRouter.scala:87:24] wire _out_T_8586 = out_f_rivalid_877; // @[RegisterRouter.scala:87:24] wire out_f_roready_877 = out_roready_1_731 & out_romask_877; // @[RegisterRouter.scala:87:24] wire _out_T_8587 = out_f_roready_877; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_877 = out_wivalid_1_731 & out_wimask_877; // @[RegisterRouter.scala:87:24] wire _out_T_8588 = out_f_wivalid_877; // @[RegisterRouter.scala:87:24] wire out_f_woready_877 = out_woready_1_731 & out_womask_877; // @[RegisterRouter.scala:87:24] wire _out_T_8589 = out_f_woready_877; // @[RegisterRouter.scala:87:24] wire _out_T_8590 = ~out_rimask_877; // @[RegisterRouter.scala:87:24] wire _out_T_8591 = ~out_wimask_877; // @[RegisterRouter.scala:87:24] wire _out_T_8592 = ~out_romask_877; // @[RegisterRouter.scala:87:24] wire _out_T_8593 = ~out_womask_877; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8595 = _out_T_8594; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_748 = _out_T_8595; // @[RegisterRouter.scala:87:24] wire out_rimask_878 = \|_out_rimask_T_878; // @[RegisterRouter.scala:87:24] wire out_wimask_878 = &_out_wimask_T_878; // @[RegisterRouter.scala:87:24] wire out_romask_878 = \|_out_romask_T_878; // @[RegisterRouter.scala:87:24] wire out_womask_878 = &_out_womask_T_878; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_878 = out_rivalid_1_732 & out_rimask_878; // @[RegisterRouter.scala:87:24] wire _out_T_8597 = out_f_rivalid_878; // @[RegisterRouter.scala:87:24] wire out_f_roready_878 = out_roready_1_732 & out_romask_878; // @[RegisterRouter.scala:87:24] wire _out_T_8598 = out_f_roready_878; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_878 = out_wivalid_1_732 & out_wimask_878; // @[RegisterRouter.scala:87:24] wire _out_T_8599 = out_f_wivalid_878; // @[RegisterRouter.scala:87:24] wire out_f_woready_878 = out_woready_1_732 & out_womask_878; // @[RegisterRouter.scala:87:24] wire _out_T_8600 = out_f_woready_878; // @[RegisterRouter.scala:87:24] wire _out_T_8601 = ~out_rimask_878; // @[RegisterRouter.scala:87:24] wire _out_T_8602 = ~out_wimask_878; // @[RegisterRouter.scala:87:24] wire _out_T_8603 = ~out_romask_878; // @[RegisterRouter.scala:87:24] wire _out_T_8604 = ~out_womask_878; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_748 = {programBufferMem_33, _out_prepend_T_748}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8605 = out_prepend_748; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8606 = _out_T_8605; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_749 = _out_T_8606; // @[RegisterRouter.scala:87:24] wire out_rimask_879 = \|_out_rimask_T_879; // @[RegisterRouter.scala:87:24] wire out_wimask_879 = &_out_wimask_T_879; // @[RegisterRouter.scala:87:24] wire out_romask_879 = \|_out_romask_T_879; // @[RegisterRouter.scala:87:24] wire out_womask_879 = &_out_womask_T_879; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_879 = out_rivalid_1_733 & out_rimask_879; // @[RegisterRouter.scala:87:24] wire _out_T_8608 = out_f_rivalid_879; // @[RegisterRouter.scala:87:24] wire out_f_roready_879 = out_roready_1_733 & out_romask_879; // @[RegisterRouter.scala:87:24] wire _out_T_8609 = out_f_roready_879; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_879 = out_wivalid_1_733 & out_wimask_879; // @[RegisterRouter.scala:87:24] wire _out_T_8610 = out_f_wivalid_879; // @[RegisterRouter.scala:87:24] wire out_f_woready_879 = out_woready_1_733 & out_womask_879; // @[RegisterRouter.scala:87:24] wire _out_T_8611 = out_f_woready_879; // @[RegisterRouter.scala:87:24] wire _out_T_8612 = ~out_rimask_879; // @[RegisterRouter.scala:87:24] wire _out_T_8613 = ~out_wimask_879; // @[RegisterRouter.scala:87:24] wire _out_T_8614 = ~out_romask_879; // @[RegisterRouter.scala:87:24] wire _out_T_8615 = ~out_womask_879; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_749 = {programBufferMem_34, _out_prepend_T_749}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8616 = out_prepend_749; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8617 = _out_T_8616; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_750 = _out_T_8617; // @[RegisterRouter.scala:87:24] wire out_rimask_880 = \|_out_rimask_T_880; // @[RegisterRouter.scala:87:24] wire out_wimask_880 = &_out_wimask_T_880; // @[RegisterRouter.scala:87:24] wire out_romask_880 = \|_out_romask_T_880; // @[RegisterRouter.scala:87:24] wire out_womask_880 = &_out_womask_T_880; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_880 = out_rivalid_1_734 & out_rimask_880; // @[RegisterRouter.scala:87:24] wire _out_T_8619 = out_f_rivalid_880; // @[RegisterRouter.scala:87:24] wire out_f_roready_880 = out_roready_1_734 & out_romask_880; // @[RegisterRouter.scala:87:24] wire _out_T_8620 = out_f_roready_880; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_880 = out_wivalid_1_734 & out_wimask_880; // @[RegisterRouter.scala:87:24] wire _out_T_8621 = out_f_wivalid_880; // @[RegisterRouter.scala:87:24] wire out_f_woready_880 = out_woready_1_734 & out_womask_880; // @[RegisterRouter.scala:87:24] wire _out_T_8622 = out_f_woready_880; // @[RegisterRouter.scala:87:24] wire _out_T_8623 = ~out_rimask_880; // @[RegisterRouter.scala:87:24] wire _out_T_8624 = ~out_wimask_880; // @[RegisterRouter.scala:87:24] wire _out_T_8625 = ~out_romask_880; // @[RegisterRouter.scala:87:24] wire _out_T_8626 = ~out_womask_880; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_750 = {programBufferMem_35, _out_prepend_T_750}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8627 = out_prepend_750; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8628 = _out_T_8627; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_751 = _out_T_8628; // @[RegisterRouter.scala:87:24] wire out_rimask_881 = \|_out_rimask_T_881; // @[RegisterRouter.scala:87:24] wire out_wimask_881 = &_out_wimask_T_881; // @[RegisterRouter.scala:87:24] wire out_romask_881 = \|_out_romask_T_881; // @[RegisterRouter.scala:87:24] wire out_womask_881 = &_out_womask_T_881; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_881 = out_rivalid_1_735 & out_rimask_881; // @[RegisterRouter.scala:87:24] wire _out_T_8630 = out_f_rivalid_881; // @[RegisterRouter.scala:87:24] wire out_f_roready_881 = out_roready_1_735 & out_romask_881; // @[RegisterRouter.scala:87:24] wire _out_T_8631 = out_f_roready_881; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_881 = out_wivalid_1_735 & out_wimask_881; // @[RegisterRouter.scala:87:24] wire _out_T_8632 = out_f_wivalid_881; // @[RegisterRouter.scala:87:24] wire out_f_woready_881 = out_woready_1_735 & out_womask_881; // @[RegisterRouter.scala:87:24] wire _out_T_8633 = out_f_woready_881; // @[RegisterRouter.scala:87:24] wire _out_T_8634 = ~out_rimask_881; // @[RegisterRouter.scala:87:24] wire _out_T_8635 = ~out_wimask_881; // @[RegisterRouter.scala:87:24] wire _out_T_8636 = ~out_romask_881; // @[RegisterRouter.scala:87:24] wire _out_T_8637 = ~out_womask_881; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_751 = {programBufferMem_36, _out_prepend_T_751}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8638 = out_prepend_751; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8639 = _out_T_8638; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_752 = _out_T_8639; // @[RegisterRouter.scala:87:24] wire out_rimask_882 = \|_out_rimask_T_882; // @[RegisterRouter.scala:87:24] wire out_wimask_882 = &_out_wimask_T_882; // @[RegisterRouter.scala:87:24] wire out_romask_882 = \|_out_romask_T_882; // @[RegisterRouter.scala:87:24] wire out_womask_882 = &_out_womask_T_882; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_882 = out_rivalid_1_736 & out_rimask_882; // @[RegisterRouter.scala:87:24] wire _out_T_8641 = out_f_rivalid_882; // @[RegisterRouter.scala:87:24] wire out_f_roready_882 = out_roready_1_736 & out_romask_882; // @[RegisterRouter.scala:87:24] wire _out_T_8642 = out_f_roready_882; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_882 = out_wivalid_1_736 & out_wimask_882; // @[RegisterRouter.scala:87:24] wire _out_T_8643 = out_f_wivalid_882; // @[RegisterRouter.scala:87:24] wire out_f_woready_882 = out_woready_1_736 & out_womask_882; // @[RegisterRouter.scala:87:24] wire _out_T_8644 = out_f_woready_882; // @[RegisterRouter.scala:87:24] wire _out_T_8645 = ~out_rimask_882; // @[RegisterRouter.scala:87:24] wire _out_T_8646 = ~out_wimask_882; // @[RegisterRouter.scala:87:24] wire _out_T_8647 = ~out_romask_882; // @[RegisterRouter.scala:87:24] wire _out_T_8648 = ~out_womask_882; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_752 = {programBufferMem_37, _out_prepend_T_752}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8649 = out_prepend_752; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8650 = _out_T_8649; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_753 = _out_T_8650; // @[RegisterRouter.scala:87:24] wire out_rimask_883 = \|_out_rimask_T_883; // @[RegisterRouter.scala:87:24] wire out_wimask_883 = &_out_wimask_T_883; // @[RegisterRouter.scala:87:24] wire out_romask_883 = \|_out_romask_T_883; // @[RegisterRouter.scala:87:24] wire out_womask_883 = &_out_womask_T_883; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_883 = out_rivalid_1_737 & out_rimask_883; // @[RegisterRouter.scala:87:24] wire _out_T_8652 = out_f_rivalid_883; // @[RegisterRouter.scala:87:24] wire out_f_roready_883 = out_roready_1_737 & out_romask_883; // @[RegisterRouter.scala:87:24] wire _out_T_8653 = out_f_roready_883; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_883 = out_wivalid_1_737 & out_wimask_883; // @[RegisterRouter.scala:87:24] wire _out_T_8654 = out_f_wivalid_883; // @[RegisterRouter.scala:87:24] wire out_f_woready_883 = out_woready_1_737 & out_womask_883; // @[RegisterRouter.scala:87:24] wire _out_T_8655 = out_f_woready_883; // @[RegisterRouter.scala:87:24] wire _out_T_8656 = ~out_rimask_883; // @[RegisterRouter.scala:87:24] wire _out_T_8657 = ~out_wimask_883; // @[RegisterRouter.scala:87:24] wire _out_T_8658 = ~out_romask_883; // @[RegisterRouter.scala:87:24] wire _out_T_8659 = ~out_womask_883; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_753 = {programBufferMem_38, _out_prepend_T_753}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8660 = out_prepend_753; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8661 = _out_T_8660; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_754 = _out_T_8661; // @[RegisterRouter.scala:87:24] wire out_rimask_884 = \|_out_rimask_T_884; // @[RegisterRouter.scala:87:24] wire out_wimask_884 = &_out_wimask_T_884; // @[RegisterRouter.scala:87:24] wire out_romask_884 = \|_out_romask_T_884; // @[RegisterRouter.scala:87:24] wire out_womask_884 = &_out_womask_T_884; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_884 = out_rivalid_1_738 & out_rimask_884; // @[RegisterRouter.scala:87:24] wire _out_T_8663 = out_f_rivalid_884; // @[RegisterRouter.scala:87:24] wire out_f_roready_884 = out_roready_1_738 & out_romask_884; // @[RegisterRouter.scala:87:24] wire _out_T_8664 = out_f_roready_884; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_884 = out_wivalid_1_738 & out_wimask_884; // @[RegisterRouter.scala:87:24] wire _out_T_8665 = out_f_wivalid_884; // @[RegisterRouter.scala:87:24] wire out_f_woready_884 = out_woready_1_738 & out_womask_884; // @[RegisterRouter.scala:87:24] wire _out_T_8666 = out_f_woready_884; // @[RegisterRouter.scala:87:24] wire _out_T_8667 = ~out_rimask_884; // @[RegisterRouter.scala:87:24] wire _out_T_8668 = ~out_wimask_884; // @[RegisterRouter.scala:87:24] wire _out_T_8669 = ~out_romask_884; // @[RegisterRouter.scala:87:24] wire _out_T_8670 = ~out_womask_884; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_754 = {programBufferMem_39, _out_prepend_T_754}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8671 = out_prepend_754; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8672 = _out_T_8671; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_108 = _out_T_8672; // @[MuxLiteral.scala:49:48] wire out_rimask_885 = \|_out_rimask_T_885; // @[RegisterRouter.scala:87:24] wire out_wimask_885 = &_out_wimask_T_885; // @[RegisterRouter.scala:87:24] wire out_romask_885 = \|_out_romask_T_885; // @[RegisterRouter.scala:87:24] wire out_womask_885 = &_out_womask_T_885; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_885 = out_rivalid_1_739 & out_rimask_885; // @[RegisterRouter.scala:87:24] wire _out_T_8674 = out_f_rivalid_885; // @[RegisterRouter.scala:87:24] wire out_f_roready_885 = out_roready_1_739 & out_romask_885; // @[RegisterRouter.scala:87:24] wire _out_T_8675 = out_f_roready_885; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_885 = out_wivalid_1_739 & out_wimask_885; // @[RegisterRouter.scala:87:24] wire out_f_woready_885 = out_woready_1_739 & out_womask_885; // @[RegisterRouter.scala:87:24] wire _out_T_8676 = ~out_rimask_885; // @[RegisterRouter.scala:87:24] wire _out_T_8677 = ~out_wimask_885; // @[RegisterRouter.scala:87:24] wire _out_T_8678 = ~out_romask_885; // @[RegisterRouter.scala:87:24] wire _out_T_8679 = ~out_womask_885; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8681 = _out_T_8680; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_755 = _out_T_8681; // @[RegisterRouter.scala:87:24] wire out_rimask_886 = \|_out_rimask_T_886; // @[RegisterRouter.scala:87:24] wire out_wimask_886 = &_out_wimask_T_886; // @[RegisterRouter.scala:87:24] wire out_romask_886 = \|_out_romask_T_886; // @[RegisterRouter.scala:87:24] wire out_womask_886 = &_out_womask_T_886; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_886 = out_rivalid_1_740 & out_rimask_886; // @[RegisterRouter.scala:87:24] wire _out_T_8683 = out_f_rivalid_886; // @[RegisterRouter.scala:87:24] wire out_f_roready_886 = out_roready_1_740 & out_romask_886; // @[RegisterRouter.scala:87:24] wire _out_T_8684 = out_f_roready_886; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_886 = out_wivalid_1_740 & out_wimask_886; // @[RegisterRouter.scala:87:24] wire out_f_woready_886 = out_woready_1_740 & out_womask_886; // @[RegisterRouter.scala:87:24] wire _out_T_8685 = ~out_rimask_886; // @[RegisterRouter.scala:87:24] wire _out_T_8686 = ~out_wimask_886; // @[RegisterRouter.scala:87:24] wire _out_T_8687 = ~out_romask_886; // @[RegisterRouter.scala:87:24] wire _out_T_8688 = ~out_womask_886; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_755 = {hi_898, flags_0_go, _out_prepend_T_755}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8689 = out_prepend_755; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8690 = _out_T_8689; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_756 = _out_T_8690; // @[RegisterRouter.scala:87:24] wire out_rimask_887 = \|_out_rimask_T_887; // @[RegisterRouter.scala:87:24] wire out_wimask_887 = &_out_wimask_T_887; // @[RegisterRouter.scala:87:24] wire out_romask_887 = \|_out_romask_T_887; // @[RegisterRouter.scala:87:24] wire out_womask_887 = &_out_womask_T_887; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_887 = out_rivalid_1_741 & out_rimask_887; // @[RegisterRouter.scala:87:24] wire _out_T_8692 = out_f_rivalid_887; // @[RegisterRouter.scala:87:24] wire out_f_roready_887 = out_roready_1_741 & out_romask_887; // @[RegisterRouter.scala:87:24] wire _out_T_8693 = out_f_roready_887; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_887 = out_wivalid_1_741 & out_wimask_887; // @[RegisterRouter.scala:87:24] wire out_f_woready_887 = out_woready_1_741 & out_womask_887; // @[RegisterRouter.scala:87:24] wire _out_T_8694 = ~out_rimask_887; // @[RegisterRouter.scala:87:24] wire _out_T_8695 = ~out_wimask_887; // @[RegisterRouter.scala:87:24] wire _out_T_8696 = ~out_romask_887; // @[RegisterRouter.scala:87:24] wire _out_T_8697 = ~out_womask_887; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_756 = {hi_899, flags_0_go, _out_prepend_T_756}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8698 = out_prepend_756; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8699 = _out_T_8698; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_757 = _out_T_8699; // @[RegisterRouter.scala:87:24] wire out_rimask_888 = \|_out_rimask_T_888; // @[RegisterRouter.scala:87:24] wire out_wimask_888 = &_out_wimask_T_888; // @[RegisterRouter.scala:87:24] wire out_romask_888 = \|_out_romask_T_888; // @[RegisterRouter.scala:87:24] wire out_womask_888 = &_out_womask_T_888; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_888 = out_rivalid_1_742 & out_rimask_888; // @[RegisterRouter.scala:87:24] wire _out_T_8701 = out_f_rivalid_888; // @[RegisterRouter.scala:87:24] wire out_f_roready_888 = out_roready_1_742 & out_romask_888; // @[RegisterRouter.scala:87:24] wire _out_T_8702 = out_f_roready_888; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_888 = out_wivalid_1_742 & out_wimask_888; // @[RegisterRouter.scala:87:24] wire out_f_woready_888 = out_woready_1_742 & out_womask_888; // @[RegisterRouter.scala:87:24] wire _out_T_8703 = ~out_rimask_888; // @[RegisterRouter.scala:87:24] wire _out_T_8704 = ~out_wimask_888; // @[RegisterRouter.scala:87:24] wire _out_T_8705 = ~out_romask_888; // @[RegisterRouter.scala:87:24] wire _out_T_8706 = ~out_womask_888; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_757 = {hi_900, flags_0_go, _out_prepend_T_757}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8707 = out_prepend_757; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8708 = _out_T_8707; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_758 = _out_T_8708; // @[RegisterRouter.scala:87:24] wire out_rimask_889 = \|_out_rimask_T_889; // @[RegisterRouter.scala:87:24] wire out_wimask_889 = &_out_wimask_T_889; // @[RegisterRouter.scala:87:24] wire out_romask_889 = \|_out_romask_T_889; // @[RegisterRouter.scala:87:24] wire out_womask_889 = &_out_womask_T_889; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_889 = out_rivalid_1_743 & out_rimask_889; // @[RegisterRouter.scala:87:24] wire _out_T_8710 = out_f_rivalid_889; // @[RegisterRouter.scala:87:24] wire out_f_roready_889 = out_roready_1_743 & out_romask_889; // @[RegisterRouter.scala:87:24] wire _out_T_8711 = out_f_roready_889; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_889 = out_wivalid_1_743 & out_wimask_889; // @[RegisterRouter.scala:87:24] wire out_f_woready_889 = out_woready_1_743 & out_womask_889; // @[RegisterRouter.scala:87:24] wire _out_T_8712 = ~out_rimask_889; // @[RegisterRouter.scala:87:24] wire _out_T_8713 = ~out_wimask_889; // @[RegisterRouter.scala:87:24] wire _out_T_8714 = ~out_romask_889; // @[RegisterRouter.scala:87:24] wire _out_T_8715 = ~out_womask_889; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_758 = {hi_901, flags_0_go, _out_prepend_T_758}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8716 = out_prepend_758; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8717 = _out_T_8716; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_759 = _out_T_8717; // @[RegisterRouter.scala:87:24] wire out_rimask_890 = \|_out_rimask_T_890; // @[RegisterRouter.scala:87:24] wire out_wimask_890 = &_out_wimask_T_890; // @[RegisterRouter.scala:87:24] wire out_romask_890 = \|_out_romask_T_890; // @[RegisterRouter.scala:87:24] wire out_womask_890 = &_out_womask_T_890; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_890 = out_rivalid_1_744 & out_rimask_890; // @[RegisterRouter.scala:87:24] wire _out_T_8719 = out_f_rivalid_890; // @[RegisterRouter.scala:87:24] wire out_f_roready_890 = out_roready_1_744 & out_romask_890; // @[RegisterRouter.scala:87:24] wire _out_T_8720 = out_f_roready_890; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_890 = out_wivalid_1_744 & out_wimask_890; // @[RegisterRouter.scala:87:24] wire out_f_woready_890 = out_woready_1_744 & out_womask_890; // @[RegisterRouter.scala:87:24] wire _out_T_8721 = ~out_rimask_890; // @[RegisterRouter.scala:87:24] wire _out_T_8722 = ~out_wimask_890; // @[RegisterRouter.scala:87:24] wire _out_T_8723 = ~out_romask_890; // @[RegisterRouter.scala:87:24] wire _out_T_8724 = ~out_womask_890; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_759 = {hi_902, flags_0_go, _out_prepend_T_759}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8725 = out_prepend_759; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8726 = _out_T_8725; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_760 = _out_T_8726; // @[RegisterRouter.scala:87:24] wire out_rimask_891 = \|_out_rimask_T_891; // @[RegisterRouter.scala:87:24] wire out_wimask_891 = &_out_wimask_T_891; // @[RegisterRouter.scala:87:24] wire out_romask_891 = \|_out_romask_T_891; // @[RegisterRouter.scala:87:24] wire out_womask_891 = &_out_womask_T_891; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_891 = out_rivalid_1_745 & out_rimask_891; // @[RegisterRouter.scala:87:24] wire _out_T_8728 = out_f_rivalid_891; // @[RegisterRouter.scala:87:24] wire out_f_roready_891 = out_roready_1_745 & out_romask_891; // @[RegisterRouter.scala:87:24] wire _out_T_8729 = out_f_roready_891; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_891 = out_wivalid_1_745 & out_wimask_891; // @[RegisterRouter.scala:87:24] wire out_f_woready_891 = out_woready_1_745 & out_womask_891; // @[RegisterRouter.scala:87:24] wire _out_T_8730 = ~out_rimask_891; // @[RegisterRouter.scala:87:24] wire _out_T_8731 = ~out_wimask_891; // @[RegisterRouter.scala:87:24] wire _out_T_8732 = ~out_romask_891; // @[RegisterRouter.scala:87:24] wire _out_T_8733 = ~out_womask_891; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_760 = {hi_903, flags_0_go, _out_prepend_T_760}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8734 = out_prepend_760; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8735 = _out_T_8734; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_761 = _out_T_8735; // @[RegisterRouter.scala:87:24] wire out_rimask_892 = \|_out_rimask_T_892; // @[RegisterRouter.scala:87:24] wire out_wimask_892 = &_out_wimask_T_892; // @[RegisterRouter.scala:87:24] wire out_romask_892 = \|_out_romask_T_892; // @[RegisterRouter.scala:87:24] wire out_womask_892 = &_out_womask_T_892; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_892 = out_rivalid_1_746 & out_rimask_892; // @[RegisterRouter.scala:87:24] wire _out_T_8737 = out_f_rivalid_892; // @[RegisterRouter.scala:87:24] wire out_f_roready_892 = out_roready_1_746 & out_romask_892; // @[RegisterRouter.scala:87:24] wire _out_T_8738 = out_f_roready_892; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_892 = out_wivalid_1_746 & out_wimask_892; // @[RegisterRouter.scala:87:24] wire out_f_woready_892 = out_woready_1_746 & out_womask_892; // @[RegisterRouter.scala:87:24] wire _out_T_8739 = ~out_rimask_892; // @[RegisterRouter.scala:87:24] wire _out_T_8740 = ~out_wimask_892; // @[RegisterRouter.scala:87:24] wire _out_T_8741 = ~out_romask_892; // @[RegisterRouter.scala:87:24] wire _out_T_8742 = ~out_womask_892; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_761 = {hi_904, flags_0_go, _out_prepend_T_761}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8743 = out_prepend_761; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8744 = _out_T_8743; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_240 = _out_T_8744; // @[MuxLiteral.scala:49:48] wire out_rimask_893 = \|_out_rimask_T_893; // @[RegisterRouter.scala:87:24] wire out_wimask_893 = &_out_wimask_T_893; // @[RegisterRouter.scala:87:24] wire out_romask_893 = \|_out_romask_T_893; // @[RegisterRouter.scala:87:24] wire out_womask_893 = &_out_womask_T_893; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_893 = out_rivalid_1_747 & out_rimask_893; // @[RegisterRouter.scala:87:24] wire _out_T_8746 = out_f_rivalid_893; // @[RegisterRouter.scala:87:24] wire out_f_roready_893 = out_roready_1_747 & out_romask_893; // @[RegisterRouter.scala:87:24] wire _out_T_8747 = out_f_roready_893; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_893 = out_wivalid_1_747 & out_wimask_893; // @[RegisterRouter.scala:87:24] wire out_f_woready_893 = out_woready_1_747 & out_womask_893; // @[RegisterRouter.scala:87:24] wire _out_T_8748 = ~out_rimask_893; // @[RegisterRouter.scala:87:24] wire _out_T_8749 = ~out_wimask_893; // @[RegisterRouter.scala:87:24] wire _out_T_8750 = ~out_romask_893; // @[RegisterRouter.scala:87:24] wire _out_T_8751 = ~out_womask_893; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8753 = _out_T_8752; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_762 = _out_T_8753; // @[RegisterRouter.scala:87:24] wire out_rimask_894 = \|_out_rimask_T_894; // @[RegisterRouter.scala:87:24] wire out_wimask_894 = &_out_wimask_T_894; // @[RegisterRouter.scala:87:24] wire out_romask_894 = \|_out_romask_T_894; // @[RegisterRouter.scala:87:24] wire out_womask_894 = &_out_womask_T_894; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_894 = out_rivalid_1_748 & out_rimask_894; // @[RegisterRouter.scala:87:24] wire _out_T_8755 = out_f_rivalid_894; // @[RegisterRouter.scala:87:24] wire out_f_roready_894 = out_roready_1_748 & out_romask_894; // @[RegisterRouter.scala:87:24] wire _out_T_8756 = out_f_roready_894; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_894 = out_wivalid_1_748 & out_wimask_894; // @[RegisterRouter.scala:87:24] wire out_f_woready_894 = out_woready_1_748 & out_womask_894; // @[RegisterRouter.scala:87:24] wire _out_T_8757 = ~out_rimask_894; // @[RegisterRouter.scala:87:24] wire _out_T_8758 = ~out_wimask_894; // @[RegisterRouter.scala:87:24] wire _out_T_8759 = ~out_romask_894; // @[RegisterRouter.scala:87:24] wire _out_T_8760 = ~out_womask_894; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_762 = {hi_986, flags_0_go, _out_prepend_T_762}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8761 = out_prepend_762; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8762 = _out_T_8761; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_763 = _out_T_8762; // @[RegisterRouter.scala:87:24] wire out_rimask_895 = \|_out_rimask_T_895; // @[RegisterRouter.scala:87:24] wire out_wimask_895 = &_out_wimask_T_895; // @[RegisterRouter.scala:87:24] wire out_romask_895 = \|_out_romask_T_895; // @[RegisterRouter.scala:87:24] wire out_womask_895 = &_out_womask_T_895; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_895 = out_rivalid_1_749 & out_rimask_895; // @[RegisterRouter.scala:87:24] wire _out_T_8764 = out_f_rivalid_895; // @[RegisterRouter.scala:87:24] wire out_f_roready_895 = out_roready_1_749 & out_romask_895; // @[RegisterRouter.scala:87:24] wire _out_T_8765 = out_f_roready_895; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_895 = out_wivalid_1_749 & out_wimask_895; // @[RegisterRouter.scala:87:24] wire out_f_woready_895 = out_woready_1_749 & out_womask_895; // @[RegisterRouter.scala:87:24] wire _out_T_8766 = ~out_rimask_895; // @[RegisterRouter.scala:87:24] wire _out_T_8767 = ~out_wimask_895; // @[RegisterRouter.scala:87:24] wire _out_T_8768 = ~out_romask_895; // @[RegisterRouter.scala:87:24] wire _out_T_8769 = ~out_womask_895; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_763 = {hi_987, flags_0_go, _out_prepend_T_763}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8770 = out_prepend_763; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8771 = _out_T_8770; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_764 = _out_T_8771; // @[RegisterRouter.scala:87:24] wire out_rimask_896 = \|_out_rimask_T_896; // @[RegisterRouter.scala:87:24] wire out_wimask_896 = &_out_wimask_T_896; // @[RegisterRouter.scala:87:24] wire out_romask_896 = \|_out_romask_T_896; // @[RegisterRouter.scala:87:24] wire out_womask_896 = &_out_womask_T_896; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_896 = out_rivalid_1_750 & out_rimask_896; // @[RegisterRouter.scala:87:24] wire _out_T_8773 = out_f_rivalid_896; // @[RegisterRouter.scala:87:24] wire out_f_roready_896 = out_roready_1_750 & out_romask_896; // @[RegisterRouter.scala:87:24] wire _out_T_8774 = out_f_roready_896; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_896 = out_wivalid_1_750 & out_wimask_896; // @[RegisterRouter.scala:87:24] wire out_f_woready_896 = out_woready_1_750 & out_womask_896; // @[RegisterRouter.scala:87:24] wire _out_T_8775 = ~out_rimask_896; // @[RegisterRouter.scala:87:24] wire _out_T_8776 = ~out_wimask_896; // @[RegisterRouter.scala:87:24] wire _out_T_8777 = ~out_romask_896; // @[RegisterRouter.scala:87:24] wire _out_T_8778 = ~out_womask_896; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_764 = {hi_988, flags_0_go, _out_prepend_T_764}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8779 = out_prepend_764; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8780 = _out_T_8779; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_765 = _out_T_8780; // @[RegisterRouter.scala:87:24] wire out_rimask_897 = \|_out_rimask_T_897; // @[RegisterRouter.scala:87:24] wire out_wimask_897 = &_out_wimask_T_897; // @[RegisterRouter.scala:87:24] wire out_romask_897 = \|_out_romask_T_897; // @[RegisterRouter.scala:87:24] wire out_womask_897 = &_out_womask_T_897; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_897 = out_rivalid_1_751 & out_rimask_897; // @[RegisterRouter.scala:87:24] wire _out_T_8782 = out_f_rivalid_897; // @[RegisterRouter.scala:87:24] wire out_f_roready_897 = out_roready_1_751 & out_romask_897; // @[RegisterRouter.scala:87:24] wire _out_T_8783 = out_f_roready_897; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_897 = out_wivalid_1_751 & out_wimask_897; // @[RegisterRouter.scala:87:24] wire out_f_woready_897 = out_woready_1_751 & out_womask_897; // @[RegisterRouter.scala:87:24] wire _out_T_8784 = ~out_rimask_897; // @[RegisterRouter.scala:87:24] wire _out_T_8785 = ~out_wimask_897; // @[RegisterRouter.scala:87:24] wire _out_T_8786 = ~out_romask_897; // @[RegisterRouter.scala:87:24] wire _out_T_8787 = ~out_womask_897; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_765 = {hi_989, flags_0_go, _out_prepend_T_765}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8788 = out_prepend_765; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8789 = _out_T_8788; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_766 = _out_T_8789; // @[RegisterRouter.scala:87:24] wire out_rimask_898 = \|_out_rimask_T_898; // @[RegisterRouter.scala:87:24] wire out_wimask_898 = &_out_wimask_T_898; // @[RegisterRouter.scala:87:24] wire out_romask_898 = \|_out_romask_T_898; // @[RegisterRouter.scala:87:24] wire out_womask_898 = &_out_womask_T_898; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_898 = out_rivalid_1_752 & out_rimask_898; // @[RegisterRouter.scala:87:24] wire _out_T_8791 = out_f_rivalid_898; // @[RegisterRouter.scala:87:24] wire out_f_roready_898 = out_roready_1_752 & out_romask_898; // @[RegisterRouter.scala:87:24] wire _out_T_8792 = out_f_roready_898; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_898 = out_wivalid_1_752 & out_wimask_898; // @[RegisterRouter.scala:87:24] wire out_f_woready_898 = out_woready_1_752 & out_womask_898; // @[RegisterRouter.scala:87:24] wire _out_T_8793 = ~out_rimask_898; // @[RegisterRouter.scala:87:24] wire _out_T_8794 = ~out_wimask_898; // @[RegisterRouter.scala:87:24] wire _out_T_8795 = ~out_romask_898; // @[RegisterRouter.scala:87:24] wire _out_T_8796 = ~out_womask_898; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_766 = {hi_990, flags_0_go, _out_prepend_T_766}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8797 = out_prepend_766; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8798 = _out_T_8797; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_767 = _out_T_8798; // @[RegisterRouter.scala:87:24] wire out_rimask_899 = \|_out_rimask_T_899; // @[RegisterRouter.scala:87:24] wire out_wimask_899 = &_out_wimask_T_899; // @[RegisterRouter.scala:87:24] wire out_romask_899 = \|_out_romask_T_899; // @[RegisterRouter.scala:87:24] wire out_womask_899 = &_out_womask_T_899; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_899 = out_rivalid_1_753 & out_rimask_899; // @[RegisterRouter.scala:87:24] wire _out_T_8800 = out_f_rivalid_899; // @[RegisterRouter.scala:87:24] wire out_f_roready_899 = out_roready_1_753 & out_romask_899; // @[RegisterRouter.scala:87:24] wire _out_T_8801 = out_f_roready_899; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_899 = out_wivalid_1_753 & out_wimask_899; // @[RegisterRouter.scala:87:24] wire out_f_woready_899 = out_woready_1_753 & out_womask_899; // @[RegisterRouter.scala:87:24] wire _out_T_8802 = ~out_rimask_899; // @[RegisterRouter.scala:87:24] wire _out_T_8803 = ~out_wimask_899; // @[RegisterRouter.scala:87:24] wire _out_T_8804 = ~out_romask_899; // @[RegisterRouter.scala:87:24] wire _out_T_8805 = ~out_womask_899; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_767 = {hi_991, flags_0_go, _out_prepend_T_767}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8806 = out_prepend_767; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8807 = _out_T_8806; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_768 = _out_T_8807; // @[RegisterRouter.scala:87:24] wire out_rimask_900 = \|_out_rimask_T_900; // @[RegisterRouter.scala:87:24] wire out_wimask_900 = &_out_wimask_T_900; // @[RegisterRouter.scala:87:24] wire out_romask_900 = \|_out_romask_T_900; // @[RegisterRouter.scala:87:24] wire out_womask_900 = &_out_womask_T_900; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_900 = out_rivalid_1_754 & out_rimask_900; // @[RegisterRouter.scala:87:24] wire _out_T_8809 = out_f_rivalid_900; // @[RegisterRouter.scala:87:24] wire out_f_roready_900 = out_roready_1_754 & out_romask_900; // @[RegisterRouter.scala:87:24] wire _out_T_8810 = out_f_roready_900; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_900 = out_wivalid_1_754 & out_wimask_900; // @[RegisterRouter.scala:87:24] wire out_f_woready_900 = out_woready_1_754 & out_womask_900; // @[RegisterRouter.scala:87:24] wire _out_T_8811 = ~out_rimask_900; // @[RegisterRouter.scala:87:24] wire _out_T_8812 = ~out_wimask_900; // @[RegisterRouter.scala:87:24] wire _out_T_8813 = ~out_romask_900; // @[RegisterRouter.scala:87:24] wire _out_T_8814 = ~out_womask_900; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_768 = {hi_992, flags_0_go, _out_prepend_T_768}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8815 = out_prepend_768; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8816 = _out_T_8815; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_251 = _out_T_8816; // @[MuxLiteral.scala:49:48] wire out_rimask_901 = \|_out_rimask_T_901; // @[RegisterRouter.scala:87:24] wire out_wimask_901 = &_out_wimask_T_901; // @[RegisterRouter.scala:87:24] wire out_romask_901 = \|_out_romask_T_901; // @[RegisterRouter.scala:87:24] wire out_womask_901 = &_out_womask_T_901; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_901 = out_rivalid_1_755 & out_rimask_901; // @[RegisterRouter.scala:87:24] wire _out_T_8818 = out_f_rivalid_901; // @[RegisterRouter.scala:87:24] wire out_f_roready_901 = out_roready_1_755 & out_romask_901; // @[RegisterRouter.scala:87:24] wire _out_T_8819 = out_f_roready_901; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_901 = out_wivalid_1_755 & out_wimask_901; // @[RegisterRouter.scala:87:24] wire out_f_woready_901 = out_woready_1_755 & out_womask_901; // @[RegisterRouter.scala:87:24] wire _out_T_8820 = ~out_rimask_901; // @[RegisterRouter.scala:87:24] wire _out_T_8821 = ~out_wimask_901; // @[RegisterRouter.scala:87:24] wire _out_T_8822 = ~out_romask_901; // @[RegisterRouter.scala:87:24] wire _out_T_8823 = ~out_womask_901; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8825 = _out_T_8824; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_769 = _out_T_8825; // @[RegisterRouter.scala:87:24] wire out_rimask_902 = \|_out_rimask_T_902; // @[RegisterRouter.scala:87:24] wire out_wimask_902 = &_out_wimask_T_902; // @[RegisterRouter.scala:87:24] wire out_romask_902 = \|_out_romask_T_902; // @[RegisterRouter.scala:87:24] wire out_womask_902 = &_out_womask_T_902; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_902 = out_rivalid_1_756 & out_rimask_902; // @[RegisterRouter.scala:87:24] wire _out_T_8827 = out_f_rivalid_902; // @[RegisterRouter.scala:87:24] wire out_f_roready_902 = out_roready_1_756 & out_romask_902; // @[RegisterRouter.scala:87:24] wire _out_T_8828 = out_f_roready_902; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_902 = out_wivalid_1_756 & out_wimask_902; // @[RegisterRouter.scala:87:24] wire out_f_woready_902 = out_woready_1_756 & out_womask_902; // @[RegisterRouter.scala:87:24] wire _out_T_8829 = ~out_rimask_902; // @[RegisterRouter.scala:87:24] wire _out_T_8830 = ~out_wimask_902; // @[RegisterRouter.scala:87:24] wire _out_T_8831 = ~out_romask_902; // @[RegisterRouter.scala:87:24] wire _out_T_8832 = ~out_womask_902; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_769 = {hi_18, flags_0_go, _out_prepend_T_769}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8833 = out_prepend_769; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8834 = _out_T_8833; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_770 = _out_T_8834; // @[RegisterRouter.scala:87:24] wire out_rimask_903 = \|_out_rimask_T_903; // @[RegisterRouter.scala:87:24] wire out_wimask_903 = &_out_wimask_T_903; // @[RegisterRouter.scala:87:24] wire out_romask_903 = \|_out_romask_T_903; // @[RegisterRouter.scala:87:24] wire out_womask_903 = &_out_womask_T_903; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_903 = out_rivalid_1_757 & out_rimask_903; // @[RegisterRouter.scala:87:24] wire _out_T_8836 = out_f_rivalid_903; // @[RegisterRouter.scala:87:24] wire out_f_roready_903 = out_roready_1_757 & out_romask_903; // @[RegisterRouter.scala:87:24] wire _out_T_8837 = out_f_roready_903; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_903 = out_wivalid_1_757 & out_wimask_903; // @[RegisterRouter.scala:87:24] wire out_f_woready_903 = out_woready_1_757 & out_womask_903; // @[RegisterRouter.scala:87:24] wire _out_T_8838 = ~out_rimask_903; // @[RegisterRouter.scala:87:24] wire _out_T_8839 = ~out_wimask_903; // @[RegisterRouter.scala:87:24] wire _out_T_8840 = ~out_romask_903; // @[RegisterRouter.scala:87:24] wire _out_T_8841 = ~out_womask_903; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_770 = {hi_19, flags_0_go, _out_prepend_T_770}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8842 = out_prepend_770; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8843 = _out_T_8842; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_771 = _out_T_8843; // @[RegisterRouter.scala:87:24] wire out_rimask_904 = \|_out_rimask_T_904; // @[RegisterRouter.scala:87:24] wire out_wimask_904 = &_out_wimask_T_904; // @[RegisterRouter.scala:87:24] wire out_romask_904 = \|_out_romask_T_904; // @[RegisterRouter.scala:87:24] wire out_womask_904 = &_out_womask_T_904; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_904 = out_rivalid_1_758 & out_rimask_904; // @[RegisterRouter.scala:87:24] wire _out_T_8845 = out_f_rivalid_904; // @[RegisterRouter.scala:87:24] wire out_f_roready_904 = out_roready_1_758 & out_romask_904; // @[RegisterRouter.scala:87:24] wire _out_T_8846 = out_f_roready_904; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_904 = out_wivalid_1_758 & out_wimask_904; // @[RegisterRouter.scala:87:24] wire out_f_woready_904 = out_woready_1_758 & out_womask_904; // @[RegisterRouter.scala:87:24] wire _out_T_8847 = ~out_rimask_904; // @[RegisterRouter.scala:87:24] wire _out_T_8848 = ~out_wimask_904; // @[RegisterRouter.scala:87:24] wire _out_T_8849 = ~out_romask_904; // @[RegisterRouter.scala:87:24] wire _out_T_8850 = ~out_womask_904; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_771 = {hi_20, flags_0_go, _out_prepend_T_771}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8851 = out_prepend_771; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8852 = _out_T_8851; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_772 = _out_T_8852; // @[RegisterRouter.scala:87:24] wire out_rimask_905 = \|_out_rimask_T_905; // @[RegisterRouter.scala:87:24] wire out_wimask_905 = &_out_wimask_T_905; // @[RegisterRouter.scala:87:24] wire out_romask_905 = \|_out_romask_T_905; // @[RegisterRouter.scala:87:24] wire out_womask_905 = &_out_womask_T_905; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_905 = out_rivalid_1_759 & out_rimask_905; // @[RegisterRouter.scala:87:24] wire _out_T_8854 = out_f_rivalid_905; // @[RegisterRouter.scala:87:24] wire out_f_roready_905 = out_roready_1_759 & out_romask_905; // @[RegisterRouter.scala:87:24] wire _out_T_8855 = out_f_roready_905; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_905 = out_wivalid_1_759 & out_wimask_905; // @[RegisterRouter.scala:87:24] wire out_f_woready_905 = out_woready_1_759 & out_womask_905; // @[RegisterRouter.scala:87:24] wire _out_T_8856 = ~out_rimask_905; // @[RegisterRouter.scala:87:24] wire _out_T_8857 = ~out_wimask_905; // @[RegisterRouter.scala:87:24] wire _out_T_8858 = ~out_romask_905; // @[RegisterRouter.scala:87:24] wire _out_T_8859 = ~out_womask_905; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_772 = {hi_21, flags_0_go, _out_prepend_T_772}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8860 = out_prepend_772; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8861 = _out_T_8860; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_773 = _out_T_8861; // @[RegisterRouter.scala:87:24] wire out_rimask_906 = \|_out_rimask_T_906; // @[RegisterRouter.scala:87:24] wire out_wimask_906 = &_out_wimask_T_906; // @[RegisterRouter.scala:87:24] wire out_romask_906 = \|_out_romask_T_906; // @[RegisterRouter.scala:87:24] wire out_womask_906 = &_out_womask_T_906; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_906 = out_rivalid_1_760 & out_rimask_906; // @[RegisterRouter.scala:87:24] wire _out_T_8863 = out_f_rivalid_906; // @[RegisterRouter.scala:87:24] wire out_f_roready_906 = out_roready_1_760 & out_romask_906; // @[RegisterRouter.scala:87:24] wire _out_T_8864 = out_f_roready_906; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_906 = out_wivalid_1_760 & out_wimask_906; // @[RegisterRouter.scala:87:24] wire out_f_woready_906 = out_woready_1_760 & out_womask_906; // @[RegisterRouter.scala:87:24] wire _out_T_8865 = ~out_rimask_906; // @[RegisterRouter.scala:87:24] wire _out_T_8866 = ~out_wimask_906; // @[RegisterRouter.scala:87:24] wire _out_T_8867 = ~out_romask_906; // @[RegisterRouter.scala:87:24] wire _out_T_8868 = ~out_womask_906; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_773 = {hi_22, flags_0_go, _out_prepend_T_773}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8869 = out_prepend_773; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8870 = _out_T_8869; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_774 = _out_T_8870; // @[RegisterRouter.scala:87:24] wire out_rimask_907 = \|_out_rimask_T_907; // @[RegisterRouter.scala:87:24] wire out_wimask_907 = &_out_wimask_T_907; // @[RegisterRouter.scala:87:24] wire out_romask_907 = \|_out_romask_T_907; // @[RegisterRouter.scala:87:24] wire out_womask_907 = &_out_womask_T_907; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_907 = out_rivalid_1_761 & out_rimask_907; // @[RegisterRouter.scala:87:24] wire _out_T_8872 = out_f_rivalid_907; // @[RegisterRouter.scala:87:24] wire out_f_roready_907 = out_roready_1_761 & out_romask_907; // @[RegisterRouter.scala:87:24] wire _out_T_8873 = out_f_roready_907; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_907 = out_wivalid_1_761 & out_wimask_907; // @[RegisterRouter.scala:87:24] wire out_f_woready_907 = out_woready_1_761 & out_womask_907; // @[RegisterRouter.scala:87:24] wire _out_T_8874 = ~out_rimask_907; // @[RegisterRouter.scala:87:24] wire _out_T_8875 = ~out_wimask_907; // @[RegisterRouter.scala:87:24] wire _out_T_8876 = ~out_romask_907; // @[RegisterRouter.scala:87:24] wire _out_T_8877 = ~out_womask_907; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_774 = {hi_23, flags_0_go, _out_prepend_T_774}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8878 = out_prepend_774; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8879 = _out_T_8878; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_775 = _out_T_8879; // @[RegisterRouter.scala:87:24] wire out_rimask_908 = \|_out_rimask_T_908; // @[RegisterRouter.scala:87:24] wire out_wimask_908 = &_out_wimask_T_908; // @[RegisterRouter.scala:87:24] wire out_romask_908 = \|_out_romask_T_908; // @[RegisterRouter.scala:87:24] wire out_womask_908 = &_out_womask_T_908; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_908 = out_rivalid_1_762 & out_rimask_908; // @[RegisterRouter.scala:87:24] wire _out_T_8881 = out_f_rivalid_908; // @[RegisterRouter.scala:87:24] wire out_f_roready_908 = out_roready_1_762 & out_romask_908; // @[RegisterRouter.scala:87:24] wire _out_T_8882 = out_f_roready_908; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_908 = out_wivalid_1_762 & out_wimask_908; // @[RegisterRouter.scala:87:24] wire out_f_woready_908 = out_woready_1_762 & out_womask_908; // @[RegisterRouter.scala:87:24] wire _out_T_8883 = ~out_rimask_908; // @[RegisterRouter.scala:87:24] wire _out_T_8884 = ~out_wimask_908; // @[RegisterRouter.scala:87:24] wire _out_T_8885 = ~out_romask_908; // @[RegisterRouter.scala:87:24] wire _out_T_8886 = ~out_womask_908; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_775 = {hi_24, flags_0_go, _out_prepend_T_775}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8887 = out_prepend_775; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8888 = _out_T_8887; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_130 = _out_T_8888; // @[MuxLiteral.scala:49:48] wire out_rimask_909 = \|_out_rimask_T_909; // @[RegisterRouter.scala:87:24] wire out_wimask_909 = &_out_wimask_T_909; // @[RegisterRouter.scala:87:24] wire out_romask_909 = \|_out_romask_T_909; // @[RegisterRouter.scala:87:24] wire out_womask_909 = &_out_womask_T_909; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_909 = out_rivalid_1_763 & out_rimask_909; // @[RegisterRouter.scala:87:24] wire _out_T_8890 = out_f_rivalid_909; // @[RegisterRouter.scala:87:24] wire out_f_roready_909 = out_roready_1_763 & out_romask_909; // @[RegisterRouter.scala:87:24] wire _out_T_8891 = out_f_roready_909; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_909 = out_wivalid_1_763 & out_wimask_909; // @[RegisterRouter.scala:87:24] wire out_f_woready_909 = out_woready_1_763 & out_womask_909; // @[RegisterRouter.scala:87:24] wire _out_T_8892 = ~out_rimask_909; // @[RegisterRouter.scala:87:24] wire _out_T_8893 = ~out_wimask_909; // @[RegisterRouter.scala:87:24] wire _out_T_8894 = ~out_romask_909; // @[RegisterRouter.scala:87:24] wire _out_T_8895 = ~out_womask_909; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8897 = _out_T_8896; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_776 = _out_T_8897; // @[RegisterRouter.scala:87:24] wire out_rimask_910 = \|_out_rimask_T_910; // @[RegisterRouter.scala:87:24] wire out_wimask_910 = &_out_wimask_T_910; // @[RegisterRouter.scala:87:24] wire out_romask_910 = \|_out_romask_T_910; // @[RegisterRouter.scala:87:24] wire out_womask_910 = &_out_womask_T_910; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_910 = out_rivalid_1_764 & out_rimask_910; // @[RegisterRouter.scala:87:24] wire _out_T_8899 = out_f_rivalid_910; // @[RegisterRouter.scala:87:24] wire out_f_roready_910 = out_roready_1_764 & out_romask_910; // @[RegisterRouter.scala:87:24] wire _out_T_8900 = out_f_roready_910; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_910 = out_wivalid_1_764 & out_wimask_910; // @[RegisterRouter.scala:87:24] wire out_f_woready_910 = out_woready_1_764 & out_womask_910; // @[RegisterRouter.scala:87:24] wire _out_T_8901 = ~out_rimask_910; // @[RegisterRouter.scala:87:24] wire _out_T_8902 = ~out_wimask_910; // @[RegisterRouter.scala:87:24] wire _out_T_8903 = ~out_romask_910; // @[RegisterRouter.scala:87:24] wire _out_T_8904 = ~out_womask_910; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_776 = {hi_762, flags_0_go, _out_prepend_T_776}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8905 = out_prepend_776; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8906 = _out_T_8905; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_777 = _out_T_8906; // @[RegisterRouter.scala:87:24] wire out_rimask_911 = \|_out_rimask_T_911; // @[RegisterRouter.scala:87:24] wire out_wimask_911 = &_out_wimask_T_911; // @[RegisterRouter.scala:87:24] wire out_romask_911 = \|_out_romask_T_911; // @[RegisterRouter.scala:87:24] wire out_womask_911 = &_out_womask_T_911; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_911 = out_rivalid_1_765 & out_rimask_911; // @[RegisterRouter.scala:87:24] wire _out_T_8908 = out_f_rivalid_911; // @[RegisterRouter.scala:87:24] wire out_f_roready_911 = out_roready_1_765 & out_romask_911; // @[RegisterRouter.scala:87:24] wire _out_T_8909 = out_f_roready_911; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_911 = out_wivalid_1_765 & out_wimask_911; // @[RegisterRouter.scala:87:24] wire out_f_woready_911 = out_woready_1_765 & out_womask_911; // @[RegisterRouter.scala:87:24] wire _out_T_8910 = ~out_rimask_911; // @[RegisterRouter.scala:87:24] wire _out_T_8911 = ~out_wimask_911; // @[RegisterRouter.scala:87:24] wire _out_T_8912 = ~out_romask_911; // @[RegisterRouter.scala:87:24] wire _out_T_8913 = ~out_womask_911; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_777 = {hi_763, flags_0_go, _out_prepend_T_777}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8914 = out_prepend_777; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8915 = _out_T_8914; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_778 = _out_T_8915; // @[RegisterRouter.scala:87:24] wire out_rimask_912 = \|_out_rimask_T_912; // @[RegisterRouter.scala:87:24] wire out_wimask_912 = &_out_wimask_T_912; // @[RegisterRouter.scala:87:24] wire out_romask_912 = \|_out_romask_T_912; // @[RegisterRouter.scala:87:24] wire out_womask_912 = &_out_womask_T_912; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_912 = out_rivalid_1_766 & out_rimask_912; // @[RegisterRouter.scala:87:24] wire _out_T_8917 = out_f_rivalid_912; // @[RegisterRouter.scala:87:24] wire out_f_roready_912 = out_roready_1_766 & out_romask_912; // @[RegisterRouter.scala:87:24] wire _out_T_8918 = out_f_roready_912; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_912 = out_wivalid_1_766 & out_wimask_912; // @[RegisterRouter.scala:87:24] wire out_f_woready_912 = out_woready_1_766 & out_womask_912; // @[RegisterRouter.scala:87:24] wire _out_T_8919 = ~out_rimask_912; // @[RegisterRouter.scala:87:24] wire _out_T_8920 = ~out_wimask_912; // @[RegisterRouter.scala:87:24] wire _out_T_8921 = ~out_romask_912; // @[RegisterRouter.scala:87:24] wire _out_T_8922 = ~out_womask_912; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_778 = {hi_764, flags_0_go, _out_prepend_T_778}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8923 = out_prepend_778; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8924 = _out_T_8923; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_779 = _out_T_8924; // @[RegisterRouter.scala:87:24] wire out_rimask_913 = \|_out_rimask_T_913; // @[RegisterRouter.scala:87:24] wire out_wimask_913 = &_out_wimask_T_913; // @[RegisterRouter.scala:87:24] wire out_romask_913 = \|_out_romask_T_913; // @[RegisterRouter.scala:87:24] wire out_womask_913 = &_out_womask_T_913; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_913 = out_rivalid_1_767 & out_rimask_913; // @[RegisterRouter.scala:87:24] wire _out_T_8926 = out_f_rivalid_913; // @[RegisterRouter.scala:87:24] wire out_f_roready_913 = out_roready_1_767 & out_romask_913; // @[RegisterRouter.scala:87:24] wire _out_T_8927 = out_f_roready_913; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_913 = out_wivalid_1_767 & out_wimask_913; // @[RegisterRouter.scala:87:24] wire out_f_woready_913 = out_woready_1_767 & out_womask_913; // @[RegisterRouter.scala:87:24] wire _out_T_8928 = ~out_rimask_913; // @[RegisterRouter.scala:87:24] wire _out_T_8929 = ~out_wimask_913; // @[RegisterRouter.scala:87:24] wire _out_T_8930 = ~out_romask_913; // @[RegisterRouter.scala:87:24] wire _out_T_8931 = ~out_womask_913; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_779 = {hi_765, flags_0_go, _out_prepend_T_779}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8932 = out_prepend_779; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8933 = _out_T_8932; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_780 = _out_T_8933; // @[RegisterRouter.scala:87:24] wire out_rimask_914 = \|_out_rimask_T_914; // @[RegisterRouter.scala:87:24] wire out_wimask_914 = &_out_wimask_T_914; // @[RegisterRouter.scala:87:24] wire out_romask_914 = \|_out_romask_T_914; // @[RegisterRouter.scala:87:24] wire out_womask_914 = &_out_womask_T_914; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_914 = out_rivalid_1_768 & out_rimask_914; // @[RegisterRouter.scala:87:24] wire _out_T_8935 = out_f_rivalid_914; // @[RegisterRouter.scala:87:24] wire out_f_roready_914 = out_roready_1_768 & out_romask_914; // @[RegisterRouter.scala:87:24] wire _out_T_8936 = out_f_roready_914; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_914 = out_wivalid_1_768 & out_wimask_914; // @[RegisterRouter.scala:87:24] wire out_f_woready_914 = out_woready_1_768 & out_womask_914; // @[RegisterRouter.scala:87:24] wire _out_T_8937 = ~out_rimask_914; // @[RegisterRouter.scala:87:24] wire _out_T_8938 = ~out_wimask_914; // @[RegisterRouter.scala:87:24] wire _out_T_8939 = ~out_romask_914; // @[RegisterRouter.scala:87:24] wire _out_T_8940 = ~out_womask_914; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_780 = {hi_766, flags_0_go, _out_prepend_T_780}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8941 = out_prepend_780; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8942 = _out_T_8941; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_781 = _out_T_8942; // @[RegisterRouter.scala:87:24] wire out_rimask_915 = \|_out_rimask_T_915; // @[RegisterRouter.scala:87:24] wire out_wimask_915 = &_out_wimask_T_915; // @[RegisterRouter.scala:87:24] wire out_romask_915 = \|_out_romask_T_915; // @[RegisterRouter.scala:87:24] wire out_womask_915 = &_out_womask_T_915; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_915 = out_rivalid_1_769 & out_rimask_915; // @[RegisterRouter.scala:87:24] wire _out_T_8944 = out_f_rivalid_915; // @[RegisterRouter.scala:87:24] wire out_f_roready_915 = out_roready_1_769 & out_romask_915; // @[RegisterRouter.scala:87:24] wire _out_T_8945 = out_f_roready_915; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_915 = out_wivalid_1_769 & out_wimask_915; // @[RegisterRouter.scala:87:24] wire out_f_woready_915 = out_woready_1_769 & out_womask_915; // @[RegisterRouter.scala:87:24] wire _out_T_8946 = ~out_rimask_915; // @[RegisterRouter.scala:87:24] wire _out_T_8947 = ~out_wimask_915; // @[RegisterRouter.scala:87:24] wire _out_T_8948 = ~out_romask_915; // @[RegisterRouter.scala:87:24] wire _out_T_8949 = ~out_womask_915; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_781 = {hi_767, flags_0_go, _out_prepend_T_781}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8950 = out_prepend_781; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8951 = _out_T_8950; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_782 = _out_T_8951; // @[RegisterRouter.scala:87:24] wire out_rimask_916 = \|_out_rimask_T_916; // @[RegisterRouter.scala:87:24] wire out_wimask_916 = &_out_wimask_T_916; // @[RegisterRouter.scala:87:24] wire out_romask_916 = \|_out_romask_T_916; // @[RegisterRouter.scala:87:24] wire out_womask_916 = &_out_womask_T_916; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_916 = out_rivalid_1_770 & out_rimask_916; // @[RegisterRouter.scala:87:24] wire _out_T_8953 = out_f_rivalid_916; // @[RegisterRouter.scala:87:24] wire out_f_roready_916 = out_roready_1_770 & out_romask_916; // @[RegisterRouter.scala:87:24] wire _out_T_8954 = out_f_roready_916; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_916 = out_wivalid_1_770 & out_wimask_916; // @[RegisterRouter.scala:87:24] wire out_f_woready_916 = out_woready_1_770 & out_womask_916; // @[RegisterRouter.scala:87:24] wire _out_T_8955 = ~out_rimask_916; // @[RegisterRouter.scala:87:24] wire _out_T_8956 = ~out_wimask_916; // @[RegisterRouter.scala:87:24] wire _out_T_8957 = ~out_romask_916; // @[RegisterRouter.scala:87:24] wire _out_T_8958 = ~out_womask_916; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_782 = {hi_768, flags_0_go, _out_prepend_T_782}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8959 = out_prepend_782; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8960 = _out_T_8959; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_223 = _out_T_8960; // @[MuxLiteral.scala:49:48] wire out_rimask_917 = \|_out_rimask_T_917; // @[RegisterRouter.scala:87:24] wire out_wimask_917 = &_out_wimask_T_917; // @[RegisterRouter.scala:87:24] wire out_romask_917 = \|_out_romask_T_917; // @[RegisterRouter.scala:87:24] wire out_womask_917 = &_out_womask_T_917; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_917 = out_rivalid_1_771 & out_rimask_917; // @[RegisterRouter.scala:87:24] wire _out_T_8962 = out_f_rivalid_917; // @[RegisterRouter.scala:87:24] wire out_f_roready_917 = out_roready_1_771 & out_romask_917; // @[RegisterRouter.scala:87:24] wire _out_T_8963 = out_f_roready_917; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_917 = out_wivalid_1_771 & out_wimask_917; // @[RegisterRouter.scala:87:24] wire out_f_woready_917 = out_woready_1_771 & out_womask_917; // @[RegisterRouter.scala:87:24] wire _out_T_8964 = ~out_rimask_917; // @[RegisterRouter.scala:87:24] wire _out_T_8965 = ~out_wimask_917; // @[RegisterRouter.scala:87:24] wire _out_T_8966 = ~out_romask_917; // @[RegisterRouter.scala:87:24] wire _out_T_8967 = ~out_womask_917; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8969 = _out_T_8968; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_783 = _out_T_8969; // @[RegisterRouter.scala:87:24] wire out_rimask_918 = \|_out_rimask_T_918; // @[RegisterRouter.scala:87:24] wire out_wimask_918 = &_out_wimask_T_918; // @[RegisterRouter.scala:87:24] wire out_romask_918 = \|_out_romask_T_918; // @[RegisterRouter.scala:87:24] wire out_womask_918 = &_out_womask_T_918; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_918 = out_rivalid_1_772 & out_rimask_918; // @[RegisterRouter.scala:87:24] wire _out_T_8971 = out_f_rivalid_918; // @[RegisterRouter.scala:87:24] wire out_f_roready_918 = out_roready_1_772 & out_romask_918; // @[RegisterRouter.scala:87:24] wire _out_T_8972 = out_f_roready_918; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_918 = out_wivalid_1_772 & out_wimask_918; // @[RegisterRouter.scala:87:24] wire out_f_woready_918 = out_woready_1_772 & out_womask_918; // @[RegisterRouter.scala:87:24] wire _out_T_8973 = ~out_rimask_918; // @[RegisterRouter.scala:87:24] wire _out_T_8974 = ~out_wimask_918; // @[RegisterRouter.scala:87:24] wire _out_T_8975 = ~out_romask_918; // @[RegisterRouter.scala:87:24] wire _out_T_8976 = ~out_womask_918; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_783 = {hi_58, flags_0_go, _out_prepend_T_783}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8977 = out_prepend_783; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8978 = _out_T_8977; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_784 = _out_T_8978; // @[RegisterRouter.scala:87:24] wire out_rimask_919 = \|_out_rimask_T_919; // @[RegisterRouter.scala:87:24] wire out_wimask_919 = &_out_wimask_T_919; // @[RegisterRouter.scala:87:24] wire out_romask_919 = \|_out_romask_T_919; // @[RegisterRouter.scala:87:24] wire out_womask_919 = &_out_womask_T_919; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_919 = out_rivalid_1_773 & out_rimask_919; // @[RegisterRouter.scala:87:24] wire _out_T_8980 = out_f_rivalid_919; // @[RegisterRouter.scala:87:24] wire out_f_roready_919 = out_roready_1_773 & out_romask_919; // @[RegisterRouter.scala:87:24] wire _out_T_8981 = out_f_roready_919; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_919 = out_wivalid_1_773 & out_wimask_919; // @[RegisterRouter.scala:87:24] wire out_f_woready_919 = out_woready_1_773 & out_womask_919; // @[RegisterRouter.scala:87:24] wire _out_T_8982 = ~out_rimask_919; // @[RegisterRouter.scala:87:24] wire _out_T_8983 = ~out_wimask_919; // @[RegisterRouter.scala:87:24] wire _out_T_8984 = ~out_romask_919; // @[RegisterRouter.scala:87:24] wire _out_T_8985 = ~out_womask_919; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_784 = {hi_59, flags_0_go, _out_prepend_T_784}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8986 = out_prepend_784; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8987 = _out_T_8986; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_785 = _out_T_8987; // @[RegisterRouter.scala:87:24] wire out_rimask_920 = \|_out_rimask_T_920; // @[RegisterRouter.scala:87:24] wire out_wimask_920 = &_out_wimask_T_920; // @[RegisterRouter.scala:87:24] wire out_romask_920 = \|_out_romask_T_920; // @[RegisterRouter.scala:87:24] wire out_womask_920 = &_out_womask_T_920; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_920 = out_rivalid_1_774 & out_rimask_920; // @[RegisterRouter.scala:87:24] wire _out_T_8989 = out_f_rivalid_920; // @[RegisterRouter.scala:87:24] wire out_f_roready_920 = out_roready_1_774 & out_romask_920; // @[RegisterRouter.scala:87:24] wire _out_T_8990 = out_f_roready_920; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_920 = out_wivalid_1_774 & out_wimask_920; // @[RegisterRouter.scala:87:24] wire out_f_woready_920 = out_woready_1_774 & out_womask_920; // @[RegisterRouter.scala:87:24] wire _out_T_8991 = ~out_rimask_920; // @[RegisterRouter.scala:87:24] wire _out_T_8992 = ~out_wimask_920; // @[RegisterRouter.scala:87:24] wire _out_T_8993 = ~out_romask_920; // @[RegisterRouter.scala:87:24] wire _out_T_8994 = ~out_womask_920; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_785 = {hi_60, flags_0_go, _out_prepend_T_785}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8995 = out_prepend_785; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8996 = _out_T_8995; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_786 = _out_T_8996; // @[RegisterRouter.scala:87:24] wire out_rimask_921 = \|_out_rimask_T_921; // @[RegisterRouter.scala:87:24] wire out_wimask_921 = &_out_wimask_T_921; // @[RegisterRouter.scala:87:24] wire out_romask_921 = \|_out_romask_T_921; // @[RegisterRouter.scala:87:24] wire out_womask_921 = &_out_womask_T_921; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_921 = out_rivalid_1_775 & out_rimask_921; // @[RegisterRouter.scala:87:24] wire _out_T_8998 = out_f_rivalid_921; // @[RegisterRouter.scala:87:24] wire out_f_roready_921 = out_roready_1_775 & out_romask_921; // @[RegisterRouter.scala:87:24] wire _out_T_8999 = out_f_roready_921; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_921 = out_wivalid_1_775 & out_wimask_921; // @[RegisterRouter.scala:87:24] wire out_f_woready_921 = out_woready_1_775 & out_womask_921; // @[RegisterRouter.scala:87:24] wire _out_T_9000 = ~out_rimask_921; // @[RegisterRouter.scala:87:24] wire _out_T_9001 = ~out_wimask_921; // @[RegisterRouter.scala:87:24] wire _out_T_9002 = ~out_romask_921; // @[RegisterRouter.scala:87:24] wire _out_T_9003 = ~out_womask_921; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_786 = {hi_61, flags_0_go, _out_prepend_T_786}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9004 = out_prepend_786; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9005 = _out_T_9004; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_787 = _out_T_9005; // @[RegisterRouter.scala:87:24] wire out_rimask_922 = \|_out_rimask_T_922; // @[RegisterRouter.scala:87:24] wire out_wimask_922 = &_out_wimask_T_922; // @[RegisterRouter.scala:87:24] wire out_romask_922 = \|_out_romask_T_922; // @[RegisterRouter.scala:87:24] wire out_womask_922 = &_out_womask_T_922; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_922 = out_rivalid_1_776 & out_rimask_922; // @[RegisterRouter.scala:87:24] wire _out_T_9007 = out_f_rivalid_922; // @[RegisterRouter.scala:87:24] wire out_f_roready_922 = out_roready_1_776 & out_romask_922; // @[RegisterRouter.scala:87:24] wire _out_T_9008 = out_f_roready_922; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_922 = out_wivalid_1_776 & out_wimask_922; // @[RegisterRouter.scala:87:24] wire out_f_woready_922 = out_woready_1_776 & out_womask_922; // @[RegisterRouter.scala:87:24] wire _out_T_9009 = ~out_rimask_922; // @[RegisterRouter.scala:87:24] wire _out_T_9010 = ~out_wimask_922; // @[RegisterRouter.scala:87:24] wire _out_T_9011 = ~out_romask_922; // @[RegisterRouter.scala:87:24] wire _out_T_9012 = ~out_womask_922; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_787 = {hi_62, flags_0_go, _out_prepend_T_787}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9013 = out_prepend_787; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9014 = _out_T_9013; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_788 = _out_T_9014; // @[RegisterRouter.scala:87:24] wire out_rimask_923 = \|_out_rimask_T_923; // @[RegisterRouter.scala:87:24] wire out_wimask_923 = &_out_wimask_T_923; // @[RegisterRouter.scala:87:24] wire out_romask_923 = \|_out_romask_T_923; // @[RegisterRouter.scala:87:24] wire out_womask_923 = &_out_womask_T_923; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_923 = out_rivalid_1_777 & out_rimask_923; // @[RegisterRouter.scala:87:24] wire _out_T_9016 = out_f_rivalid_923; // @[RegisterRouter.scala:87:24] wire out_f_roready_923 = out_roready_1_777 & out_romask_923; // @[RegisterRouter.scala:87:24] wire _out_T_9017 = out_f_roready_923; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_923 = out_wivalid_1_777 & out_wimask_923; // @[RegisterRouter.scala:87:24] wire out_f_woready_923 = out_woready_1_777 & out_womask_923; // @[RegisterRouter.scala:87:24] wire _out_T_9018 = ~out_rimask_923; // @[RegisterRouter.scala:87:24] wire _out_T_9019 = ~out_wimask_923; // @[RegisterRouter.scala:87:24] wire _out_T_9020 = ~out_romask_923; // @[RegisterRouter.scala:87:24] wire _out_T_9021 = ~out_womask_923; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_788 = {hi_63, flags_0_go, _out_prepend_T_788}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9022 = out_prepend_788; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9023 = _out_T_9022; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_789 = _out_T_9023; // @[RegisterRouter.scala:87:24] wire out_rimask_924 = \|_out_rimask_T_924; // @[RegisterRouter.scala:87:24] wire out_wimask_924 = &_out_wimask_T_924; // @[RegisterRouter.scala:87:24] wire out_romask_924 = \|_out_romask_T_924; // @[RegisterRouter.scala:87:24] wire out_womask_924 = &_out_womask_T_924; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_924 = out_rivalid_1_778 & out_rimask_924; // @[RegisterRouter.scala:87:24] wire _out_T_9025 = out_f_rivalid_924; // @[RegisterRouter.scala:87:24] wire out_f_roready_924 = out_roready_1_778 & out_romask_924; // @[RegisterRouter.scala:87:24] wire _out_T_9026 = out_f_roready_924; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_924 = out_wivalid_1_778 & out_wimask_924; // @[RegisterRouter.scala:87:24] wire out_f_woready_924 = out_woready_1_778 & out_womask_924; // @[RegisterRouter.scala:87:24] wire _out_T_9027 = ~out_rimask_924; // @[RegisterRouter.scala:87:24] wire _out_T_9028 = ~out_wimask_924; // @[RegisterRouter.scala:87:24] wire _out_T_9029 = ~out_romask_924; // @[RegisterRouter.scala:87:24] wire _out_T_9030 = ~out_womask_924; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_789 = {hi_64, flags_0_go, _out_prepend_T_789}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9031 = out_prepend_789; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9032 = _out_T_9031; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_135 = _out_T_9032; // @[MuxLiteral.scala:49:48] wire out_rimask_925 = \|_out_rimask_T_925; // @[RegisterRouter.scala:87:24] wire out_wimask_925 = &_out_wimask_T_925; // @[RegisterRouter.scala:87:24] wire out_romask_925 = \|_out_romask_T_925; // @[RegisterRouter.scala:87:24] wire out_womask_925 = &_out_womask_T_925; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_925 = out_rivalid_1_779 & out_rimask_925; // @[RegisterRouter.scala:87:24] wire _out_T_9034 = out_f_rivalid_925; // @[RegisterRouter.scala:87:24] wire out_f_roready_925 = out_roready_1_779 & out_romask_925; // @[RegisterRouter.scala:87:24] wire _out_T_9035 = out_f_roready_925; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_925 = out_wivalid_1_779 & out_wimask_925; // @[RegisterRouter.scala:87:24] wire out_f_woready_925 = out_woready_1_779 & out_womask_925; // @[RegisterRouter.scala:87:24] wire _out_T_9036 = ~out_rimask_925; // @[RegisterRouter.scala:87:24] wire _out_T_9037 = ~out_wimask_925; // @[RegisterRouter.scala:87:24] wire _out_T_9038 = ~out_romask_925; // @[RegisterRouter.scala:87:24] wire _out_T_9039 = ~out_womask_925; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9041 = _out_T_9040; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_790 = _out_T_9041; // @[RegisterRouter.scala:87:24] wire out_rimask_926 = \|_out_rimask_T_926; // @[RegisterRouter.scala:87:24] wire out_wimask_926 = &_out_wimask_T_926; // @[RegisterRouter.scala:87:24] wire out_romask_926 = \|_out_romask_T_926; // @[RegisterRouter.scala:87:24] wire out_womask_926 = &_out_womask_T_926; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_926 = out_rivalid_1_780 & out_rimask_926; // @[RegisterRouter.scala:87:24] wire _out_T_9043 = out_f_rivalid_926; // @[RegisterRouter.scala:87:24] wire out_f_roready_926 = out_roready_1_780 & out_romask_926; // @[RegisterRouter.scala:87:24] wire _out_T_9044 = out_f_roready_926; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_926 = out_wivalid_1_780 & out_wimask_926; // @[RegisterRouter.scala:87:24] wire out_f_woready_926 = out_woready_1_780 & out_womask_926; // @[RegisterRouter.scala:87:24] wire _out_T_9045 = ~out_rimask_926; // @[RegisterRouter.scala:87:24] wire _out_T_9046 = ~out_wimask_926; // @[RegisterRouter.scala:87:24] wire _out_T_9047 = ~out_romask_926; // @[RegisterRouter.scala:87:24] wire _out_T_9048 = ~out_womask_926; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_790 = {hi_786, flags_0_go, _out_prepend_T_790}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9049 = out_prepend_790; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9050 = _out_T_9049; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_791 = _out_T_9050; // @[RegisterRouter.scala:87:24] wire out_rimask_927 = \|_out_rimask_T_927; // @[RegisterRouter.scala:87:24] wire out_wimask_927 = &_out_wimask_T_927; // @[RegisterRouter.scala:87:24] wire out_romask_927 = \|_out_romask_T_927; // @[RegisterRouter.scala:87:24] wire out_womask_927 = &_out_womask_T_927; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_927 = out_rivalid_1_781 & out_rimask_927; // @[RegisterRouter.scala:87:24] wire _out_T_9052 = out_f_rivalid_927; // @[RegisterRouter.scala:87:24] wire out_f_roready_927 = out_roready_1_781 & out_romask_927; // @[RegisterRouter.scala:87:24] wire _out_T_9053 = out_f_roready_927; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_927 = out_wivalid_1_781 & out_wimask_927; // @[RegisterRouter.scala:87:24] wire out_f_woready_927 = out_woready_1_781 & out_womask_927; // @[RegisterRouter.scala:87:24] wire _out_T_9054 = ~out_rimask_927; // @[RegisterRouter.scala:87:24] wire _out_T_9055 = ~out_wimask_927; // @[RegisterRouter.scala:87:24] wire _out_T_9056 = ~out_romask_927; // @[RegisterRouter.scala:87:24] wire _out_T_9057 = ~out_womask_927; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_791 = {hi_787, flags_0_go, _out_prepend_T_791}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9058 = out_prepend_791; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9059 = _out_T_9058; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_792 = _out_T_9059; // @[RegisterRouter.scala:87:24] wire out_rimask_928 = \|_out_rimask_T_928; // @[RegisterRouter.scala:87:24] wire out_wimask_928 = &_out_wimask_T_928; // @[RegisterRouter.scala:87:24] wire out_romask_928 = \|_out_romask_T_928; // @[RegisterRouter.scala:87:24] wire out_womask_928 = &_out_womask_T_928; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_928 = out_rivalid_1_782 & out_rimask_928; // @[RegisterRouter.scala:87:24] wire _out_T_9061 = out_f_rivalid_928; // @[RegisterRouter.scala:87:24] wire out_f_roready_928 = out_roready_1_782 & out_romask_928; // @[RegisterRouter.scala:87:24] wire _out_T_9062 = out_f_roready_928; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_928 = out_wivalid_1_782 & out_wimask_928; // @[RegisterRouter.scala:87:24] wire out_f_woready_928 = out_woready_1_782 & out_womask_928; // @[RegisterRouter.scala:87:24] wire _out_T_9063 = ~out_rimask_928; // @[RegisterRouter.scala:87:24] wire _out_T_9064 = ~out_wimask_928; // @[RegisterRouter.scala:87:24] wire _out_T_9065 = ~out_romask_928; // @[RegisterRouter.scala:87:24] wire _out_T_9066 = ~out_womask_928; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_792 = {hi_788, flags_0_go, _out_prepend_T_792}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9067 = out_prepend_792; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9068 = _out_T_9067; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_793 = _out_T_9068; // @[RegisterRouter.scala:87:24] wire out_rimask_929 = \|_out_rimask_T_929; // @[RegisterRouter.scala:87:24] wire out_wimask_929 = &_out_wimask_T_929; // @[RegisterRouter.scala:87:24] wire out_romask_929 = \|_out_romask_T_929; // @[RegisterRouter.scala:87:24] wire out_womask_929 = &_out_womask_T_929; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_929 = out_rivalid_1_783 & out_rimask_929; // @[RegisterRouter.scala:87:24] wire _out_T_9070 = out_f_rivalid_929; // @[RegisterRouter.scala:87:24] wire out_f_roready_929 = out_roready_1_783 & out_romask_929; // @[RegisterRouter.scala:87:24] wire _out_T_9071 = out_f_roready_929; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_929 = out_wivalid_1_783 & out_wimask_929; // @[RegisterRouter.scala:87:24] wire out_f_woready_929 = out_woready_1_783 & out_womask_929; // @[RegisterRouter.scala:87:24] wire _out_T_9072 = ~out_rimask_929; // @[RegisterRouter.scala:87:24] wire _out_T_9073 = ~out_wimask_929; // @[RegisterRouter.scala:87:24] wire _out_T_9074 = ~out_romask_929; // @[RegisterRouter.scala:87:24] wire _out_T_9075 = ~out_womask_929; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_793 = {hi_789, flags_0_go, _out_prepend_T_793}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9076 = out_prepend_793; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9077 = _out_T_9076; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_794 = _out_T_9077; // @[RegisterRouter.scala:87:24] wire out_rimask_930 = \|_out_rimask_T_930; // @[RegisterRouter.scala:87:24] wire out_wimask_930 = &_out_wimask_T_930; // @[RegisterRouter.scala:87:24] wire out_romask_930 = \|_out_romask_T_930; // @[RegisterRouter.scala:87:24] wire out_womask_930 = &_out_womask_T_930; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_930 = out_rivalid_1_784 & out_rimask_930; // @[RegisterRouter.scala:87:24] wire _out_T_9079 = out_f_rivalid_930; // @[RegisterRouter.scala:87:24] wire out_f_roready_930 = out_roready_1_784 & out_romask_930; // @[RegisterRouter.scala:87:24] wire _out_T_9080 = out_f_roready_930; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_930 = out_wivalid_1_784 & out_wimask_930; // @[RegisterRouter.scala:87:24] wire out_f_woready_930 = out_woready_1_784 & out_womask_930; // @[RegisterRouter.scala:87:24] wire _out_T_9081 = ~out_rimask_930; // @[RegisterRouter.scala:87:24] wire _out_T_9082 = ~out_wimask_930; // @[RegisterRouter.scala:87:24] wire _out_T_9083 = ~out_romask_930; // @[RegisterRouter.scala:87:24] wire _out_T_9084 = ~out_womask_930; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_794 = {hi_790, flags_0_go, _out_prepend_T_794}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9085 = out_prepend_794; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9086 = _out_T_9085; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_795 = _out_T_9086; // @[RegisterRouter.scala:87:24] wire out_rimask_931 = \|_out_rimask_T_931; // @[RegisterRouter.scala:87:24] wire out_wimask_931 = &_out_wimask_T_931; // @[RegisterRouter.scala:87:24] wire out_romask_931 = \|_out_romask_T_931; // @[RegisterRouter.scala:87:24] wire out_womask_931 = &_out_womask_T_931; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_931 = out_rivalid_1_785 & out_rimask_931; // @[RegisterRouter.scala:87:24] wire _out_T_9088 = out_f_rivalid_931; // @[RegisterRouter.scala:87:24] wire out_f_roready_931 = out_roready_1_785 & out_romask_931; // @[RegisterRouter.scala:87:24] wire _out_T_9089 = out_f_roready_931; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_931 = out_wivalid_1_785 & out_wimask_931; // @[RegisterRouter.scala:87:24] wire out_f_woready_931 = out_woready_1_785 & out_womask_931; // @[RegisterRouter.scala:87:24] wire _out_T_9090 = ~out_rimask_931; // @[RegisterRouter.scala:87:24] wire _out_T_9091 = ~out_wimask_931; // @[RegisterRouter.scala:87:24] wire _out_T_9092 = ~out_romask_931; // @[RegisterRouter.scala:87:24] wire _out_T_9093 = ~out_womask_931; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_795 = {hi_791, flags_0_go, _out_prepend_T_795}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9094 = out_prepend_795; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9095 = _out_T_9094; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_796 = _out_T_9095; // @[RegisterRouter.scala:87:24] wire out_rimask_932 = \|_out_rimask_T_932; // @[RegisterRouter.scala:87:24] wire out_wimask_932 = &_out_wimask_T_932; // @[RegisterRouter.scala:87:24] wire out_romask_932 = \|_out_romask_T_932; // @[RegisterRouter.scala:87:24] wire out_womask_932 = &_out_womask_T_932; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_932 = out_rivalid_1_786 & out_rimask_932; // @[RegisterRouter.scala:87:24] wire _out_T_9097 = out_f_rivalid_932; // @[RegisterRouter.scala:87:24] wire out_f_roready_932 = out_roready_1_786 & out_romask_932; // @[RegisterRouter.scala:87:24] wire _out_T_9098 = out_f_roready_932; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_932 = out_wivalid_1_786 & out_wimask_932; // @[RegisterRouter.scala:87:24] wire out_f_woready_932 = out_woready_1_786 & out_womask_932; // @[RegisterRouter.scala:87:24] wire _out_T_9099 = ~out_rimask_932; // @[RegisterRouter.scala:87:24] wire _out_T_9100 = ~out_wimask_932; // @[RegisterRouter.scala:87:24] wire _out_T_9101 = ~out_romask_932; // @[RegisterRouter.scala:87:24] wire _out_T_9102 = ~out_womask_932; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_796 = {hi_792, flags_0_go, _out_prepend_T_796}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9103 = out_prepend_796; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9104 = _out_T_9103; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_226 = _out_T_9104; // @[MuxLiteral.scala:49:48] wire out_rimask_933 = \|_out_rimask_T_933; // @[RegisterRouter.scala:87:24] wire out_wimask_933 = &_out_wimask_T_933; // @[RegisterRouter.scala:87:24] wire out_romask_933 = \|_out_romask_T_933; // @[RegisterRouter.scala:87:24] wire out_womask_933 = &_out_womask_T_933; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_933 = out_rivalid_1_787 & out_rimask_933; // @[RegisterRouter.scala:87:24] wire _out_T_9106 = out_f_rivalid_933; // @[RegisterRouter.scala:87:24] wire out_f_roready_933 = out_roready_1_787 & out_romask_933; // @[RegisterRouter.scala:87:24] wire _out_T_9107 = out_f_roready_933; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_933 = out_wivalid_1_787 & out_wimask_933; // @[RegisterRouter.scala:87:24] wire out_f_woready_933 = out_woready_1_787 & out_womask_933; // @[RegisterRouter.scala:87:24] wire _out_T_9108 = ~out_rimask_933; // @[RegisterRouter.scala:87:24] wire _out_T_9109 = ~out_wimask_933; // @[RegisterRouter.scala:87:24] wire _out_T_9110 = ~out_romask_933; // @[RegisterRouter.scala:87:24] wire _out_T_9111 = ~out_womask_933; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9113 = _out_T_9112; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_797 = _out_T_9113; // @[RegisterRouter.scala:87:24] wire out_rimask_934 = \|_out_rimask_T_934; // @[RegisterRouter.scala:87:24] wire out_wimask_934 = &_out_wimask_T_934; // @[RegisterRouter.scala:87:24] wire out_romask_934 = \|_out_romask_T_934; // @[RegisterRouter.scala:87:24] wire out_womask_934 = &_out_womask_T_934; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_934 = out_rivalid_1_788 & out_rimask_934; // @[RegisterRouter.scala:87:24] wire _out_T_9115 = out_f_rivalid_934; // @[RegisterRouter.scala:87:24] wire out_f_roready_934 = out_roready_1_788 & out_romask_934; // @[RegisterRouter.scala:87:24] wire _out_T_9116 = out_f_roready_934; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_934 = out_wivalid_1_788 & out_wimask_934; // @[RegisterRouter.scala:87:24] wire out_f_woready_934 = out_woready_1_788 & out_womask_934; // @[RegisterRouter.scala:87:24] wire _out_T_9117 = ~out_rimask_934; // @[RegisterRouter.scala:87:24] wire _out_T_9118 = ~out_wimask_934; // @[RegisterRouter.scala:87:24] wire _out_T_9119 = ~out_romask_934; // @[RegisterRouter.scala:87:24] wire _out_T_9120 = ~out_womask_934; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_797 = {hi_906, flags_0_go, _out_prepend_T_797}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9121 = out_prepend_797; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9122 = _out_T_9121; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_798 = _out_T_9122; // @[RegisterRouter.scala:87:24] wire out_rimask_935 = \|_out_rimask_T_935; // @[RegisterRouter.scala:87:24] wire out_wimask_935 = &_out_wimask_T_935; // @[RegisterRouter.scala:87:24] wire out_romask_935 = \|_out_romask_T_935; // @[RegisterRouter.scala:87:24] wire out_womask_935 = &_out_womask_T_935; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_935 = out_rivalid_1_789 & out_rimask_935; // @[RegisterRouter.scala:87:24] wire _out_T_9124 = out_f_rivalid_935; // @[RegisterRouter.scala:87:24] wire out_f_roready_935 = out_roready_1_789 & out_romask_935; // @[RegisterRouter.scala:87:24] wire _out_T_9125 = out_f_roready_935; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_935 = out_wivalid_1_789 & out_wimask_935; // @[RegisterRouter.scala:87:24] wire out_f_woready_935 = out_woready_1_789 & out_womask_935; // @[RegisterRouter.scala:87:24] wire _out_T_9126 = ~out_rimask_935; // @[RegisterRouter.scala:87:24] wire _out_T_9127 = ~out_wimask_935; // @[RegisterRouter.scala:87:24] wire _out_T_9128 = ~out_romask_935; // @[RegisterRouter.scala:87:24] wire _out_T_9129 = ~out_womask_935; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_798 = {hi_907, flags_0_go, _out_prepend_T_798}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9130 = out_prepend_798; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9131 = _out_T_9130; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_799 = _out_T_9131; // @[RegisterRouter.scala:87:24] wire out_rimask_936 = \|_out_rimask_T_936; // @[RegisterRouter.scala:87:24] wire out_wimask_936 = &_out_wimask_T_936; // @[RegisterRouter.scala:87:24] wire out_romask_936 = \|_out_romask_T_936; // @[RegisterRouter.scala:87:24] wire out_womask_936 = &_out_womask_T_936; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_936 = out_rivalid_1_790 & out_rimask_936; // @[RegisterRouter.scala:87:24] wire _out_T_9133 = out_f_rivalid_936; // @[RegisterRouter.scala:87:24] wire out_f_roready_936 = out_roready_1_790 & out_romask_936; // @[RegisterRouter.scala:87:24] wire _out_T_9134 = out_f_roready_936; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_936 = out_wivalid_1_790 & out_wimask_936; // @[RegisterRouter.scala:87:24] wire out_f_woready_936 = out_woready_1_790 & out_womask_936; // @[RegisterRouter.scala:87:24] wire _out_T_9135 = ~out_rimask_936; // @[RegisterRouter.scala:87:24] wire _out_T_9136 = ~out_wimask_936; // @[RegisterRouter.scala:87:24] wire _out_T_9137 = ~out_romask_936; // @[RegisterRouter.scala:87:24] wire _out_T_9138 = ~out_womask_936; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_799 = {hi_908, flags_0_go, _out_prepend_T_799}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9139 = out_prepend_799; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9140 = _out_T_9139; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_800 = _out_T_9140; // @[RegisterRouter.scala:87:24] wire out_rimask_937 = \|_out_rimask_T_937; // @[RegisterRouter.scala:87:24] wire out_wimask_937 = &_out_wimask_T_937; // @[RegisterRouter.scala:87:24] wire out_romask_937 = \|_out_romask_T_937; // @[RegisterRouter.scala:87:24] wire out_womask_937 = &_out_womask_T_937; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_937 = out_rivalid_1_791 & out_rimask_937; // @[RegisterRouter.scala:87:24] wire _out_T_9142 = out_f_rivalid_937; // @[RegisterRouter.scala:87:24] wire out_f_roready_937 = out_roready_1_791 & out_romask_937; // @[RegisterRouter.scala:87:24] wire _out_T_9143 = out_f_roready_937; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_937 = out_wivalid_1_791 & out_wimask_937; // @[RegisterRouter.scala:87:24] wire out_f_woready_937 = out_woready_1_791 & out_womask_937; // @[RegisterRouter.scala:87:24] wire _out_T_9144 = ~out_rimask_937; // @[RegisterRouter.scala:87:24] wire _out_T_9145 = ~out_wimask_937; // @[RegisterRouter.scala:87:24] wire _out_T_9146 = ~out_romask_937; // @[RegisterRouter.scala:87:24] wire _out_T_9147 = ~out_womask_937; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_800 = {hi_909, flags_0_go, _out_prepend_T_800}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9148 = out_prepend_800; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9149 = _out_T_9148; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_801 = _out_T_9149; // @[RegisterRouter.scala:87:24] wire out_rimask_938 = \|_out_rimask_T_938; // @[RegisterRouter.scala:87:24] wire out_wimask_938 = &_out_wimask_T_938; // @[RegisterRouter.scala:87:24] wire out_romask_938 = \|_out_romask_T_938; // @[RegisterRouter.scala:87:24] wire out_womask_938 = &_out_womask_T_938; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_938 = out_rivalid_1_792 & out_rimask_938; // @[RegisterRouter.scala:87:24] wire _out_T_9151 = out_f_rivalid_938; // @[RegisterRouter.scala:87:24] wire out_f_roready_938 = out_roready_1_792 & out_romask_938; // @[RegisterRouter.scala:87:24] wire _out_T_9152 = out_f_roready_938; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_938 = out_wivalid_1_792 & out_wimask_938; // @[RegisterRouter.scala:87:24] wire out_f_woready_938 = out_woready_1_792 & out_womask_938; // @[RegisterRouter.scala:87:24] wire _out_T_9153 = ~out_rimask_938; // @[RegisterRouter.scala:87:24] wire _out_T_9154 = ~out_wimask_938; // @[RegisterRouter.scala:87:24] wire _out_T_9155 = ~out_romask_938; // @[RegisterRouter.scala:87:24] wire _out_T_9156 = ~out_womask_938; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_801 = {hi_910, flags_0_go, _out_prepend_T_801}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9157 = out_prepend_801; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9158 = _out_T_9157; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_802 = _out_T_9158; // @[RegisterRouter.scala:87:24] wire out_rimask_939 = \|_out_rimask_T_939; // @[RegisterRouter.scala:87:24] wire out_wimask_939 = &_out_wimask_T_939; // @[RegisterRouter.scala:87:24] wire out_romask_939 = \|_out_romask_T_939; // @[RegisterRouter.scala:87:24] wire out_womask_939 = &_out_womask_T_939; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_939 = out_rivalid_1_793 & out_rimask_939; // @[RegisterRouter.scala:87:24] wire _out_T_9160 = out_f_rivalid_939; // @[RegisterRouter.scala:87:24] wire out_f_roready_939 = out_roready_1_793 & out_romask_939; // @[RegisterRouter.scala:87:24] wire _out_T_9161 = out_f_roready_939; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_939 = out_wivalid_1_793 & out_wimask_939; // @[RegisterRouter.scala:87:24] wire out_f_woready_939 = out_woready_1_793 & out_womask_939; // @[RegisterRouter.scala:87:24] wire _out_T_9162 = ~out_rimask_939; // @[RegisterRouter.scala:87:24] wire _out_T_9163 = ~out_wimask_939; // @[RegisterRouter.scala:87:24] wire _out_T_9164 = ~out_romask_939; // @[RegisterRouter.scala:87:24] wire _out_T_9165 = ~out_womask_939; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_802 = {hi_911, flags_0_go, _out_prepend_T_802}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9166 = out_prepend_802; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9167 = _out_T_9166; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_803 = _out_T_9167; // @[RegisterRouter.scala:87:24] wire out_rimask_940 = \|_out_rimask_T_940; // @[RegisterRouter.scala:87:24] wire out_wimask_940 = &_out_wimask_T_940; // @[RegisterRouter.scala:87:24] wire out_romask_940 = \|_out_romask_T_940; // @[RegisterRouter.scala:87:24] wire out_womask_940 = &_out_womask_T_940; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_940 = out_rivalid_1_794 & out_rimask_940; // @[RegisterRouter.scala:87:24] wire _out_T_9169 = out_f_rivalid_940; // @[RegisterRouter.scala:87:24] wire out_f_roready_940 = out_roready_1_794 & out_romask_940; // @[RegisterRouter.scala:87:24] wire _out_T_9170 = out_f_roready_940; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_940 = out_wivalid_1_794 & out_wimask_940; // @[RegisterRouter.scala:87:24] wire out_f_woready_940 = out_woready_1_794 & out_womask_940; // @[RegisterRouter.scala:87:24] wire _out_T_9171 = ~out_rimask_940; // @[RegisterRouter.scala:87:24] wire _out_T_9172 = ~out_wimask_940; // @[RegisterRouter.scala:87:24] wire _out_T_9173 = ~out_romask_940; // @[RegisterRouter.scala:87:24] wire _out_T_9174 = ~out_womask_940; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_803 = {hi_912, flags_0_go, _out_prepend_T_803}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9175 = out_prepend_803; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9176 = _out_T_9175; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_241 = _out_T_9176; // @[MuxLiteral.scala:49:48] wire out_rimask_941 = \|_out_rimask_T_941; // @[RegisterRouter.scala:87:24] wire out_wimask_941 = &_out_wimask_T_941; // @[RegisterRouter.scala:87:24] wire out_romask_941 = \|_out_romask_T_941; // @[RegisterRouter.scala:87:24] wire out_womask_941 = &_out_womask_T_941; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_941 = out_rivalid_1_795 & out_rimask_941; // @[RegisterRouter.scala:87:24] wire _out_T_9178 = out_f_rivalid_941; // @[RegisterRouter.scala:87:24] wire out_f_roready_941 = out_roready_1_795 & out_romask_941; // @[RegisterRouter.scala:87:24] wire _out_T_9179 = out_f_roready_941; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_941 = out_wivalid_1_795 & out_wimask_941; // @[RegisterRouter.scala:87:24] wire out_f_woready_941 = out_woready_1_795 & out_womask_941; // @[RegisterRouter.scala:87:24] wire _out_T_9180 = ~out_rimask_941; // @[RegisterRouter.scala:87:24] wire _out_T_9181 = ~out_wimask_941; // @[RegisterRouter.scala:87:24] wire _out_T_9182 = ~out_romask_941; // @[RegisterRouter.scala:87:24] wire _out_T_9183 = ~out_womask_941; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9185 = _out_T_9184; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_804 = _out_T_9185; // @[RegisterRouter.scala:87:24] wire out_rimask_942 = \|_out_rimask_T_942; // @[RegisterRouter.scala:87:24] wire out_wimask_942 = &_out_wimask_T_942; // @[RegisterRouter.scala:87:24] wire out_romask_942 = \|_out_romask_T_942; // @[RegisterRouter.scala:87:24] wire out_womask_942 = &_out_womask_T_942; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_942 = out_rivalid_1_796 & out_rimask_942; // @[RegisterRouter.scala:87:24] wire _out_T_9187 = out_f_rivalid_942; // @[RegisterRouter.scala:87:24] wire out_f_roready_942 = out_roready_1_796 & out_romask_942; // @[RegisterRouter.scala:87:24] wire _out_T_9188 = out_f_roready_942; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_942 = out_wivalid_1_796 & out_wimask_942; // @[RegisterRouter.scala:87:24] wire out_f_woready_942 = out_woready_1_796 & out_womask_942; // @[RegisterRouter.scala:87:24] wire _out_T_9189 = ~out_rimask_942; // @[RegisterRouter.scala:87:24] wire _out_T_9190 = ~out_wimask_942; // @[RegisterRouter.scala:87:24] wire _out_T_9191 = ~out_romask_942; // @[RegisterRouter.scala:87:24] wire _out_T_9192 = ~out_womask_942; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_804 = {hi_314, flags_0_go, _out_prepend_T_804}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9193 = out_prepend_804; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9194 = _out_T_9193; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_805 = _out_T_9194; // @[RegisterRouter.scala:87:24] wire out_rimask_943 = \|_out_rimask_T_943; // @[RegisterRouter.scala:87:24] wire out_wimask_943 = &_out_wimask_T_943; // @[RegisterRouter.scala:87:24] wire out_romask_943 = \|_out_romask_T_943; // @[RegisterRouter.scala:87:24] wire out_womask_943 = &_out_womask_T_943; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_943 = out_rivalid_1_797 & out_rimask_943; // @[RegisterRouter.scala:87:24] wire _out_T_9196 = out_f_rivalid_943; // @[RegisterRouter.scala:87:24] wire out_f_roready_943 = out_roready_1_797 & out_romask_943; // @[RegisterRouter.scala:87:24] wire _out_T_9197 = out_f_roready_943; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_943 = out_wivalid_1_797 & out_wimask_943; // @[RegisterRouter.scala:87:24] wire out_f_woready_943 = out_woready_1_797 & out_womask_943; // @[RegisterRouter.scala:87:24] wire _out_T_9198 = ~out_rimask_943; // @[RegisterRouter.scala:87:24] wire _out_T_9199 = ~out_wimask_943; // @[RegisterRouter.scala:87:24] wire _out_T_9200 = ~out_romask_943; // @[RegisterRouter.scala:87:24] wire _out_T_9201 = ~out_womask_943; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_805 = {hi_315, flags_0_go, _out_prepend_T_805}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9202 = out_prepend_805; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9203 = _out_T_9202; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_806 = _out_T_9203; // @[RegisterRouter.scala:87:24] wire out_rimask_944 = \|_out_rimask_T_944; // @[RegisterRouter.scala:87:24] wire out_wimask_944 = &_out_wimask_T_944; // @[RegisterRouter.scala:87:24] wire out_romask_944 = \|_out_romask_T_944; // @[RegisterRouter.scala:87:24] wire out_womask_944 = &_out_womask_T_944; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_944 = out_rivalid_1_798 & out_rimask_944; // @[RegisterRouter.scala:87:24] wire _out_T_9205 = out_f_rivalid_944; // @[RegisterRouter.scala:87:24] wire out_f_roready_944 = out_roready_1_798 & out_romask_944; // @[RegisterRouter.scala:87:24] wire _out_T_9206 = out_f_roready_944; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_944 = out_wivalid_1_798 & out_wimask_944; // @[RegisterRouter.scala:87:24] wire out_f_woready_944 = out_woready_1_798 & out_womask_944; // @[RegisterRouter.scala:87:24] wire _out_T_9207 = ~out_rimask_944; // @[RegisterRouter.scala:87:24] wire _out_T_9208 = ~out_wimask_944; // @[RegisterRouter.scala:87:24] wire _out_T_9209 = ~out_romask_944; // @[RegisterRouter.scala:87:24] wire _out_T_9210 = ~out_womask_944; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_806 = {hi_316, flags_0_go, _out_prepend_T_806}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9211 = out_prepend_806; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9212 = _out_T_9211; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_807 = _out_T_9212; // @[RegisterRouter.scala:87:24] wire out_rimask_945 = \|_out_rimask_T_945; // @[RegisterRouter.scala:87:24] wire out_wimask_945 = &_out_wimask_T_945; // @[RegisterRouter.scala:87:24] wire out_romask_945 = \|_out_romask_T_945; // @[RegisterRouter.scala:87:24] wire out_womask_945 = &_out_womask_T_945; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_945 = out_rivalid_1_799 & out_rimask_945; // @[RegisterRouter.scala:87:24] wire _out_T_9214 = out_f_rivalid_945; // @[RegisterRouter.scala:87:24] wire out_f_roready_945 = out_roready_1_799 & out_romask_945; // @[RegisterRouter.scala:87:24] wire _out_T_9215 = out_f_roready_945; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_945 = out_wivalid_1_799 & out_wimask_945; // @[RegisterRouter.scala:87:24] wire out_f_woready_945 = out_woready_1_799 & out_womask_945; // @[RegisterRouter.scala:87:24] wire _out_T_9216 = ~out_rimask_945; // @[RegisterRouter.scala:87:24] wire _out_T_9217 = ~out_wimask_945; // @[RegisterRouter.scala:87:24] wire _out_T_9218 = ~out_romask_945; // @[RegisterRouter.scala:87:24] wire _out_T_9219 = ~out_womask_945; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_807 = {hi_317, flags_0_go, _out_prepend_T_807}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9220 = out_prepend_807; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9221 = _out_T_9220; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_808 = _out_T_9221; // @[RegisterRouter.scala:87:24] wire out_rimask_946 = \|_out_rimask_T_946; // @[RegisterRouter.scala:87:24] wire out_wimask_946 = &_out_wimask_T_946; // @[RegisterRouter.scala:87:24] wire out_romask_946 = \|_out_romask_T_946; // @[RegisterRouter.scala:87:24] wire out_womask_946 = &_out_womask_T_946; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_946 = out_rivalid_1_800 & out_rimask_946; // @[RegisterRouter.scala:87:24] wire _out_T_9223 = out_f_rivalid_946; // @[RegisterRouter.scala:87:24] wire out_f_roready_946 = out_roready_1_800 & out_romask_946; // @[RegisterRouter.scala:87:24] wire _out_T_9224 = out_f_roready_946; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_946 = out_wivalid_1_800 & out_wimask_946; // @[RegisterRouter.scala:87:24] wire out_f_woready_946 = out_woready_1_800 & out_womask_946; // @[RegisterRouter.scala:87:24] wire _out_T_9225 = ~out_rimask_946; // @[RegisterRouter.scala:87:24] wire _out_T_9226 = ~out_wimask_946; // @[RegisterRouter.scala:87:24] wire _out_T_9227 = ~out_romask_946; // @[RegisterRouter.scala:87:24] wire _out_T_9228 = ~out_womask_946; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_808 = {hi_318, flags_0_go, _out_prepend_T_808}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9229 = out_prepend_808; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9230 = _out_T_9229; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_809 = _out_T_9230; // @[RegisterRouter.scala:87:24] wire out_rimask_947 = \|_out_rimask_T_947; // @[RegisterRouter.scala:87:24] wire out_wimask_947 = &_out_wimask_T_947; // @[RegisterRouter.scala:87:24] wire out_romask_947 = \|_out_romask_T_947; // @[RegisterRouter.scala:87:24] wire out_womask_947 = &_out_womask_T_947; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_947 = out_rivalid_1_801 & out_rimask_947; // @[RegisterRouter.scala:87:24] wire _out_T_9232 = out_f_rivalid_947; // @[RegisterRouter.scala:87:24] wire out_f_roready_947 = out_roready_1_801 & out_romask_947; // @[RegisterRouter.scala:87:24] wire _out_T_9233 = out_f_roready_947; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_947 = out_wivalid_1_801 & out_wimask_947; // @[RegisterRouter.scala:87:24] wire out_f_woready_947 = out_woready_1_801 & out_womask_947; // @[RegisterRouter.scala:87:24] wire _out_T_9234 = ~out_rimask_947; // @[RegisterRouter.scala:87:24] wire _out_T_9235 = ~out_wimask_947; // @[RegisterRouter.scala:87:24] wire _out_T_9236 = ~out_romask_947; // @[RegisterRouter.scala:87:24] wire _out_T_9237 = ~out_womask_947; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_809 = {hi_319, flags_0_go, _out_prepend_T_809}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9238 = out_prepend_809; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9239 = _out_T_9238; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_810 = _out_T_9239; // @[RegisterRouter.scala:87:24] wire out_rimask_948 = \|_out_rimask_T_948; // @[RegisterRouter.scala:87:24] wire out_wimask_948 = &_out_wimask_T_948; // @[RegisterRouter.scala:87:24] wire out_romask_948 = \|_out_romask_T_948; // @[RegisterRouter.scala:87:24] wire out_womask_948 = &_out_womask_T_948; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_948 = out_rivalid_1_802 & out_rimask_948; // @[RegisterRouter.scala:87:24] wire _out_T_9241 = out_f_rivalid_948; // @[RegisterRouter.scala:87:24] wire out_f_roready_948 = out_roready_1_802 & out_romask_948; // @[RegisterRouter.scala:87:24] wire _out_T_9242 = out_f_roready_948; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_948 = out_wivalid_1_802 & out_wimask_948; // @[RegisterRouter.scala:87:24] wire out_f_woready_948 = out_woready_1_802 & out_womask_948; // @[RegisterRouter.scala:87:24] wire _out_T_9243 = ~out_rimask_948; // @[RegisterRouter.scala:87:24] wire _out_T_9244 = ~out_wimask_948; // @[RegisterRouter.scala:87:24] wire _out_T_9245 = ~out_romask_948; // @[RegisterRouter.scala:87:24] wire _out_T_9246 = ~out_womask_948; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_810 = {hi_320, flags_0_go, _out_prepend_T_810}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9247 = out_prepend_810; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9248 = _out_T_9247; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_167 = _out_T_9248; // @[MuxLiteral.scala:49:48] wire out_rimask_949 = \|_out_rimask_T_949; // @[RegisterRouter.scala:87:24] wire out_wimask_949 = &_out_wimask_T_949; // @[RegisterRouter.scala:87:24] wire out_romask_949 = \|_out_romask_T_949; // @[RegisterRouter.scala:87:24] wire out_womask_949 = &_out_womask_T_949; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_949 = out_rivalid_1_803 & out_rimask_949; // @[RegisterRouter.scala:87:24] wire _out_T_9250 = out_f_rivalid_949; // @[RegisterRouter.scala:87:24] wire out_f_roready_949 = out_roready_1_803 & out_romask_949; // @[RegisterRouter.scala:87:24] wire _out_T_9251 = out_f_roready_949; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_949 = out_wivalid_1_803 & out_wimask_949; // @[RegisterRouter.scala:87:24] wire out_f_woready_949 = out_woready_1_803 & out_womask_949; // @[RegisterRouter.scala:87:24] wire _out_T_9252 = ~out_rimask_949; // @[RegisterRouter.scala:87:24] wire _out_T_9253 = ~out_wimask_949; // @[RegisterRouter.scala:87:24] wire _out_T_9254 = ~out_romask_949; // @[RegisterRouter.scala:87:24] wire _out_T_9255 = ~out_womask_949; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9257 = _out_T_9256; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_811 = _out_T_9257; // @[RegisterRouter.scala:87:24] wire out_rimask_950 = \|_out_rimask_T_950; // @[RegisterRouter.scala:87:24] wire out_wimask_950 = &_out_wimask_T_950; // @[RegisterRouter.scala:87:24] wire out_romask_950 = \|_out_romask_T_950; // @[RegisterRouter.scala:87:24] wire out_womask_950 = &_out_womask_T_950; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_950 = out_rivalid_1_804 & out_rimask_950; // @[RegisterRouter.scala:87:24] wire _out_T_9259 = out_f_rivalid_950; // @[RegisterRouter.scala:87:24] wire out_f_roready_950 = out_roready_1_804 & out_romask_950; // @[RegisterRouter.scala:87:24] wire _out_T_9260 = out_f_roready_950; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_950 = out_wivalid_1_804 & out_wimask_950; // @[RegisterRouter.scala:87:24] wire out_f_woready_950 = out_woready_1_804 & out_womask_950; // @[RegisterRouter.scala:87:24] wire _out_T_9261 = ~out_rimask_950; // @[RegisterRouter.scala:87:24] wire _out_T_9262 = ~out_wimask_950; // @[RegisterRouter.scala:87:24] wire _out_T_9263 = ~out_romask_950; // @[RegisterRouter.scala:87:24] wire _out_T_9264 = ~out_womask_950; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_811 = {hi_274, flags_0_go, _out_prepend_T_811}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9265 = out_prepend_811; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9266 = _out_T_9265; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_812 = _out_T_9266; // @[RegisterRouter.scala:87:24] wire out_rimask_951 = \|_out_rimask_T_951; // @[RegisterRouter.scala:87:24] wire out_wimask_951 = &_out_wimask_T_951; // @[RegisterRouter.scala:87:24] wire out_romask_951 = \|_out_romask_T_951; // @[RegisterRouter.scala:87:24] wire out_womask_951 = &_out_womask_T_951; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_951 = out_rivalid_1_805 & out_rimask_951; // @[RegisterRouter.scala:87:24] wire _out_T_9268 = out_f_rivalid_951; // @[RegisterRouter.scala:87:24] wire out_f_roready_951 = out_roready_1_805 & out_romask_951; // @[RegisterRouter.scala:87:24] wire _out_T_9269 = out_f_roready_951; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_951 = out_wivalid_1_805 & out_wimask_951; // @[RegisterRouter.scala:87:24] wire out_f_woready_951 = out_woready_1_805 & out_womask_951; // @[RegisterRouter.scala:87:24] wire _out_T_9270 = ~out_rimask_951; // @[RegisterRouter.scala:87:24] wire _out_T_9271 = ~out_wimask_951; // @[RegisterRouter.scala:87:24] wire _out_T_9272 = ~out_romask_951; // @[RegisterRouter.scala:87:24] wire _out_T_9273 = ~out_womask_951; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_812 = {hi_275, flags_0_go, _out_prepend_T_812}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9274 = out_prepend_812; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9275 = _out_T_9274; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_813 = _out_T_9275; // @[RegisterRouter.scala:87:24] wire out_rimask_952 = \|_out_rimask_T_952; // @[RegisterRouter.scala:87:24] wire out_wimask_952 = &_out_wimask_T_952; // @[RegisterRouter.scala:87:24] wire out_romask_952 = \|_out_romask_T_952; // @[RegisterRouter.scala:87:24] wire out_womask_952 = &_out_womask_T_952; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_952 = out_rivalid_1_806 & out_rimask_952; // @[RegisterRouter.scala:87:24] wire _out_T_9277 = out_f_rivalid_952; // @[RegisterRouter.scala:87:24] wire out_f_roready_952 = out_roready_1_806 & out_romask_952; // @[RegisterRouter.scala:87:24] wire _out_T_9278 = out_f_roready_952; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_952 = out_wivalid_1_806 & out_wimask_952; // @[RegisterRouter.scala:87:24] wire out_f_woready_952 = out_woready_1_806 & out_womask_952; // @[RegisterRouter.scala:87:24] wire _out_T_9279 = ~out_rimask_952; // @[RegisterRouter.scala:87:24] wire _out_T_9280 = ~out_wimask_952; // @[RegisterRouter.scala:87:24] wire _out_T_9281 = ~out_romask_952; // @[RegisterRouter.scala:87:24] wire _out_T_9282 = ~out_womask_952; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_813 = {hi_276, flags_0_go, _out_prepend_T_813}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9283 = out_prepend_813; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9284 = _out_T_9283; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_814 = _out_T_9284; // @[RegisterRouter.scala:87:24] wire out_rimask_953 = \|_out_rimask_T_953; // @[RegisterRouter.scala:87:24] wire out_wimask_953 = &_out_wimask_T_953; // @[RegisterRouter.scala:87:24] wire out_romask_953 = \|_out_romask_T_953; // @[RegisterRouter.scala:87:24] wire out_womask_953 = &_out_womask_T_953; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_953 = out_rivalid_1_807 & out_rimask_953; // @[RegisterRouter.scala:87:24] wire _out_T_9286 = out_f_rivalid_953; // @[RegisterRouter.scala:87:24] wire out_f_roready_953 = out_roready_1_807 & out_romask_953; // @[RegisterRouter.scala:87:24] wire _out_T_9287 = out_f_roready_953; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_953 = out_wivalid_1_807 & out_wimask_953; // @[RegisterRouter.scala:87:24] wire out_f_woready_953 = out_woready_1_807 & out_womask_953; // @[RegisterRouter.scala:87:24] wire _out_T_9288 = ~out_rimask_953; // @[RegisterRouter.scala:87:24] wire _out_T_9289 = ~out_wimask_953; // @[RegisterRouter.scala:87:24] wire _out_T_9290 = ~out_romask_953; // @[RegisterRouter.scala:87:24] wire _out_T_9291 = ~out_womask_953; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_814 = {hi_277, flags_0_go, _out_prepend_T_814}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9292 = out_prepend_814; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9293 = _out_T_9292; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_815 = _out_T_9293; // @[RegisterRouter.scala:87:24] wire out_rimask_954 = \|_out_rimask_T_954; // @[RegisterRouter.scala:87:24] wire out_wimask_954 = &_out_wimask_T_954; // @[RegisterRouter.scala:87:24] wire out_romask_954 = \|_out_romask_T_954; // @[RegisterRouter.scala:87:24] wire out_womask_954 = &_out_womask_T_954; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_954 = out_rivalid_1_808 & out_rimask_954; // @[RegisterRouter.scala:87:24] wire _out_T_9295 = out_f_rivalid_954; // @[RegisterRouter.scala:87:24] wire out_f_roready_954 = out_roready_1_808 & out_romask_954; // @[RegisterRouter.scala:87:24] wire _out_T_9296 = out_f_roready_954; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_954 = out_wivalid_1_808 & out_wimask_954; // @[RegisterRouter.scala:87:24] wire out_f_woready_954 = out_woready_1_808 & out_womask_954; // @[RegisterRouter.scala:87:24] wire _out_T_9297 = ~out_rimask_954; // @[RegisterRouter.scala:87:24] wire _out_T_9298 = ~out_wimask_954; // @[RegisterRouter.scala:87:24] wire _out_T_9299 = ~out_romask_954; // @[RegisterRouter.scala:87:24] wire _out_T_9300 = ~out_womask_954; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_815 = {hi_278, flags_0_go, _out_prepend_T_815}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9301 = out_prepend_815; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9302 = _out_T_9301; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_816 = _out_T_9302; // @[RegisterRouter.scala:87:24] wire out_rimask_955 = \|_out_rimask_T_955; // @[RegisterRouter.scala:87:24] wire out_wimask_955 = &_out_wimask_T_955; // @[RegisterRouter.scala:87:24] wire out_romask_955 = \|_out_romask_T_955; // @[RegisterRouter.scala:87:24] wire out_womask_955 = &_out_womask_T_955; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_955 = out_rivalid_1_809 & out_rimask_955; // @[RegisterRouter.scala:87:24] wire _out_T_9304 = out_f_rivalid_955; // @[RegisterRouter.scala:87:24] wire out_f_roready_955 = out_roready_1_809 & out_romask_955; // @[RegisterRouter.scala:87:24] wire _out_T_9305 = out_f_roready_955; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_955 = out_wivalid_1_809 & out_wimask_955; // @[RegisterRouter.scala:87:24] wire out_f_woready_955 = out_woready_1_809 & out_womask_955; // @[RegisterRouter.scala:87:24] wire _out_T_9306 = ~out_rimask_955; // @[RegisterRouter.scala:87:24] wire _out_T_9307 = ~out_wimask_955; // @[RegisterRouter.scala:87:24] wire _out_T_9308 = ~out_romask_955; // @[RegisterRouter.scala:87:24] wire _out_T_9309 = ~out_womask_955; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_816 = {hi_279, flags_0_go, _out_prepend_T_816}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9310 = out_prepend_816; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9311 = _out_T_9310; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_817 = _out_T_9311; // @[RegisterRouter.scala:87:24] wire out_rimask_956 = \|_out_rimask_T_956; // @[RegisterRouter.scala:87:24] wire out_wimask_956 = &_out_wimask_T_956; // @[RegisterRouter.scala:87:24] wire out_romask_956 = \|_out_romask_T_956; // @[RegisterRouter.scala:87:24] wire out_womask_956 = &_out_womask_T_956; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_956 = out_rivalid_1_810 & out_rimask_956; // @[RegisterRouter.scala:87:24] wire _out_T_9313 = out_f_rivalid_956; // @[RegisterRouter.scala:87:24] wire out_f_roready_956 = out_roready_1_810 & out_romask_956; // @[RegisterRouter.scala:87:24] wire _out_T_9314 = out_f_roready_956; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_956 = out_wivalid_1_810 & out_wimask_956; // @[RegisterRouter.scala:87:24] wire out_f_woready_956 = out_woready_1_810 & out_womask_956; // @[RegisterRouter.scala:87:24] wire _out_T_9315 = ~out_rimask_956; // @[RegisterRouter.scala:87:24] wire _out_T_9316 = ~out_wimask_956; // @[RegisterRouter.scala:87:24] wire _out_T_9317 = ~out_romask_956; // @[RegisterRouter.scala:87:24] wire _out_T_9318 = ~out_womask_956; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_817 = {hi_280, flags_0_go, _out_prepend_T_817}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9319 = out_prepend_817; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9320 = _out_T_9319; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_162 = _out_T_9320; // @[MuxLiteral.scala:49:48] wire out_rimask_957 = \|_out_rimask_T_957; // @[RegisterRouter.scala:87:24] wire out_wimask_957 = &_out_wimask_T_957; // @[RegisterRouter.scala:87:24] wire out_romask_957 = \|_out_romask_T_957; // @[RegisterRouter.scala:87:24] wire out_womask_957 = &_out_womask_T_957; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_957 = out_rivalid_1_811 & out_rimask_957; // @[RegisterRouter.scala:87:24] wire _out_T_9322 = out_f_rivalid_957; // @[RegisterRouter.scala:87:24] wire out_f_roready_957 = out_roready_1_811 & out_romask_957; // @[RegisterRouter.scala:87:24] wire _out_T_9323 = out_f_roready_957; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_957 = out_wivalid_1_811 & out_wimask_957; // @[RegisterRouter.scala:87:24] wire out_f_woready_957 = out_woready_1_811 & out_womask_957; // @[RegisterRouter.scala:87:24] wire _out_T_9324 = ~out_rimask_957; // @[RegisterRouter.scala:87:24] wire _out_T_9325 = ~out_wimask_957; // @[RegisterRouter.scala:87:24] wire _out_T_9326 = ~out_romask_957; // @[RegisterRouter.scala:87:24] wire _out_T_9327 = ~out_womask_957; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9329 = _out_T_9328; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_818 = _out_T_9329; // @[RegisterRouter.scala:87:24] wire out_rimask_958 = \|_out_rimask_T_958; // @[RegisterRouter.scala:87:24] wire out_wimask_958 = &_out_wimask_T_958; // @[RegisterRouter.scala:87:24] wire out_romask_958 = \|_out_romask_T_958; // @[RegisterRouter.scala:87:24] wire out_womask_958 = &_out_womask_T_958; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_958 = out_rivalid_1_812 & out_rimask_958; // @[RegisterRouter.scala:87:24] wire _out_T_9331 = out_f_rivalid_958; // @[RegisterRouter.scala:87:24] wire out_f_roready_958 = out_roready_1_812 & out_romask_958; // @[RegisterRouter.scala:87:24] wire _out_T_9332 = out_f_roready_958; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_958 = out_wivalid_1_812 & out_wimask_958; // @[RegisterRouter.scala:87:24] wire out_f_woready_958 = out_woready_1_812 & out_womask_958; // @[RegisterRouter.scala:87:24] wire _out_T_9333 = ~out_rimask_958; // @[RegisterRouter.scala:87:24] wire _out_T_9334 = ~out_wimask_958; // @[RegisterRouter.scala:87:24] wire _out_T_9335 = ~out_romask_958; // @[RegisterRouter.scala:87:24] wire _out_T_9336 = ~out_womask_958; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_818 = {hi_1018, flags_0_go, _out_prepend_T_818}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9337 = out_prepend_818; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9338 = _out_T_9337; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_819 = _out_T_9338; // @[RegisterRouter.scala:87:24] wire out_rimask_959 = \|_out_rimask_T_959; // @[RegisterRouter.scala:87:24] wire out_wimask_959 = &_out_wimask_T_959; // @[RegisterRouter.scala:87:24] wire out_romask_959 = \|_out_romask_T_959; // @[RegisterRouter.scala:87:24] wire out_womask_959 = &_out_womask_T_959; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_959 = out_rivalid_1_813 & out_rimask_959; // @[RegisterRouter.scala:87:24] wire _out_T_9340 = out_f_rivalid_959; // @[RegisterRouter.scala:87:24] wire out_f_roready_959 = out_roready_1_813 & out_romask_959; // @[RegisterRouter.scala:87:24] wire _out_T_9341 = out_f_roready_959; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_959 = out_wivalid_1_813 & out_wimask_959; // @[RegisterRouter.scala:87:24] wire out_f_woready_959 = out_woready_1_813 & out_womask_959; // @[RegisterRouter.scala:87:24] wire _out_T_9342 = ~out_rimask_959; // @[RegisterRouter.scala:87:24] wire _out_T_9343 = ~out_wimask_959; // @[RegisterRouter.scala:87:24] wire _out_T_9344 = ~out_romask_959; // @[RegisterRouter.scala:87:24] wire _out_T_9345 = ~out_womask_959; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_819 = {hi_1019, flags_0_go, _out_prepend_T_819}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9346 = out_prepend_819; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9347 = _out_T_9346; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_820 = _out_T_9347; // @[RegisterRouter.scala:87:24] wire out_rimask_960 = \|_out_rimask_T_960; // @[RegisterRouter.scala:87:24] wire out_wimask_960 = &_out_wimask_T_960; // @[RegisterRouter.scala:87:24] wire out_romask_960 = \|_out_romask_T_960; // @[RegisterRouter.scala:87:24] wire out_womask_960 = &_out_womask_T_960; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_960 = out_rivalid_1_814 & out_rimask_960; // @[RegisterRouter.scala:87:24] wire _out_T_9349 = out_f_rivalid_960; // @[RegisterRouter.scala:87:24] wire out_f_roready_960 = out_roready_1_814 & out_romask_960; // @[RegisterRouter.scala:87:24] wire _out_T_9350 = out_f_roready_960; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_960 = out_wivalid_1_814 & out_wimask_960; // @[RegisterRouter.scala:87:24] wire out_f_woready_960 = out_woready_1_814 & out_womask_960; // @[RegisterRouter.scala:87:24] wire _out_T_9351 = ~out_rimask_960; // @[RegisterRouter.scala:87:24] wire _out_T_9352 = ~out_wimask_960; // @[RegisterRouter.scala:87:24] wire _out_T_9353 = ~out_romask_960; // @[RegisterRouter.scala:87:24] wire _out_T_9354 = ~out_womask_960; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_820 = {hi_1020, flags_0_go, _out_prepend_T_820}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9355 = out_prepend_820; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9356 = _out_T_9355; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_821 = _out_T_9356; // @[RegisterRouter.scala:87:24] wire out_rimask_961 = \|_out_rimask_T_961; // @[RegisterRouter.scala:87:24] wire out_wimask_961 = &_out_wimask_T_961; // @[RegisterRouter.scala:87:24] wire out_romask_961 = \|_out_romask_T_961; // @[RegisterRouter.scala:87:24] wire out_womask_961 = &_out_womask_T_961; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_961 = out_rivalid_1_815 & out_rimask_961; // @[RegisterRouter.scala:87:24] wire _out_T_9358 = out_f_rivalid_961; // @[RegisterRouter.scala:87:24] wire out_f_roready_961 = out_roready_1_815 & out_romask_961; // @[RegisterRouter.scala:87:24] wire _out_T_9359 = out_f_roready_961; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_961 = out_wivalid_1_815 & out_wimask_961; // @[RegisterRouter.scala:87:24] wire out_f_woready_961 = out_woready_1_815 & out_womask_961; // @[RegisterRouter.scala:87:24] wire _out_T_9360 = ~out_rimask_961; // @[RegisterRouter.scala:87:24] wire _out_T_9361 = ~out_wimask_961; // @[RegisterRouter.scala:87:24] wire _out_T_9362 = ~out_romask_961; // @[RegisterRouter.scala:87:24] wire _out_T_9363 = ~out_womask_961; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_821 = {hi_1021, flags_0_go, _out_prepend_T_821}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9364 = out_prepend_821; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9365 = _out_T_9364; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_822 = _out_T_9365; // @[RegisterRouter.scala:87:24] wire out_rimask_962 = \|_out_rimask_T_962; // @[RegisterRouter.scala:87:24] wire out_wimask_962 = &_out_wimask_T_962; // @[RegisterRouter.scala:87:24] wire out_romask_962 = \|_out_romask_T_962; // @[RegisterRouter.scala:87:24] wire out_womask_962 = &_out_womask_T_962; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_962 = out_rivalid_1_816 & out_rimask_962; // @[RegisterRouter.scala:87:24] wire _out_T_9367 = out_f_rivalid_962; // @[RegisterRouter.scala:87:24] wire out_f_roready_962 = out_roready_1_816 & out_romask_962; // @[RegisterRouter.scala:87:24] wire _out_T_9368 = out_f_roready_962; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_962 = out_wivalid_1_816 & out_wimask_962; // @[RegisterRouter.scala:87:24] wire out_f_woready_962 = out_woready_1_816 & out_womask_962; // @[RegisterRouter.scala:87:24] wire _out_T_9369 = ~out_rimask_962; // @[RegisterRouter.scala:87:24] wire _out_T_9370 = ~out_wimask_962; // @[RegisterRouter.scala:87:24] wire _out_T_9371 = ~out_romask_962; // @[RegisterRouter.scala:87:24] wire _out_T_9372 = ~out_womask_962; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_822 = {hi_1022, flags_0_go, _out_prepend_T_822}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9373 = out_prepend_822; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9374 = _out_T_9373; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_823 = _out_T_9374; // @[RegisterRouter.scala:87:24] wire out_rimask_963 = \|_out_rimask_T_963; // @[RegisterRouter.scala:87:24] wire out_wimask_963 = &_out_wimask_T_963; // @[RegisterRouter.scala:87:24] wire out_romask_963 = \|_out_romask_T_963; // @[RegisterRouter.scala:87:24] wire out_womask_963 = &_out_womask_T_963; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_963 = out_rivalid_1_817 & out_rimask_963; // @[RegisterRouter.scala:87:24] wire _out_T_9376 = out_f_rivalid_963; // @[RegisterRouter.scala:87:24] wire out_f_roready_963 = out_roready_1_817 & out_romask_963; // @[RegisterRouter.scala:87:24] wire _out_T_9377 = out_f_roready_963; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_963 = out_wivalid_1_817 & out_wimask_963; // @[RegisterRouter.scala:87:24] wire out_f_woready_963 = out_woready_1_817 & out_womask_963; // @[RegisterRouter.scala:87:24] wire _out_T_9378 = ~out_rimask_963; // @[RegisterRouter.scala:87:24] wire _out_T_9379 = ~out_wimask_963; // @[RegisterRouter.scala:87:24] wire _out_T_9380 = ~out_romask_963; // @[RegisterRouter.scala:87:24] wire _out_T_9381 = ~out_womask_963; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_823 = {hi_1023, flags_0_go, _out_prepend_T_823}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9382 = out_prepend_823; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9383 = _out_T_9382; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_824 = _out_T_9383; // @[RegisterRouter.scala:87:24] wire out_rimask_964 = \|_out_rimask_T_964; // @[RegisterRouter.scala:87:24] wire out_wimask_964 = &_out_wimask_T_964; // @[RegisterRouter.scala:87:24] wire out_romask_964 = \|_out_romask_T_964; // @[RegisterRouter.scala:87:24] wire out_womask_964 = &_out_womask_T_964; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_964 = out_rivalid_1_818 & out_rimask_964; // @[RegisterRouter.scala:87:24] wire _out_T_9385 = out_f_rivalid_964; // @[RegisterRouter.scala:87:24] wire out_f_roready_964 = out_roready_1_818 & out_romask_964; // @[RegisterRouter.scala:87:24] wire _out_T_9386 = out_f_roready_964; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_964 = out_wivalid_1_818 & out_wimask_964; // @[RegisterRouter.scala:87:24] wire out_f_woready_964 = out_woready_1_818 & out_womask_964; // @[RegisterRouter.scala:87:24] wire _out_T_9387 = ~out_rimask_964; // @[RegisterRouter.scala:87:24] wire _out_T_9388 = ~out_wimask_964; // @[RegisterRouter.scala:87:24] wire _out_T_9389 = ~out_romask_964; // @[RegisterRouter.scala:87:24] wire _out_T_9390 = ~out_womask_964; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_824 = {hi_1024, flags_0_go, _out_prepend_T_824}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9391 = out_prepend_824; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9392 = _out_T_9391; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_255 = _out_T_9392; // @[MuxLiteral.scala:49:48] wire out_rimask_965 = \|_out_rimask_T_965; // @[RegisterRouter.scala:87:24] wire out_wimask_965 = &_out_wimask_T_965; // @[RegisterRouter.scala:87:24] wire out_romask_965 = \|_out_romask_T_965; // @[RegisterRouter.scala:87:24] wire out_womask_965 = &_out_womask_T_965; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_965 = out_rivalid_1_819 & out_rimask_965; // @[RegisterRouter.scala:87:24] wire _out_T_9394 = out_f_rivalid_965; // @[RegisterRouter.scala:87:24] wire out_f_roready_965 = out_roready_1_819 & out_romask_965; // @[RegisterRouter.scala:87:24] wire _out_T_9395 = out_f_roready_965; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_965 = out_wivalid_1_819 & out_wimask_965; // @[RegisterRouter.scala:87:24] wire out_f_woready_965 = out_woready_1_819 & out_womask_965; // @[RegisterRouter.scala:87:24] wire _out_T_9396 = ~out_rimask_965; // @[RegisterRouter.scala:87:24] wire _out_T_9397 = ~out_wimask_965; // @[RegisterRouter.scala:87:24] wire _out_T_9398 = ~out_romask_965; // @[RegisterRouter.scala:87:24] wire _out_T_9399 = ~out_womask_965; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9401 = _out_T_9400; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_825 = _out_T_9401; // @[RegisterRouter.scala:87:24] wire out_rimask_966 = \|_out_rimask_T_966; // @[RegisterRouter.scala:87:24] wire out_wimask_966 = &_out_wimask_T_966; // @[RegisterRouter.scala:87:24] wire out_romask_966 = \|_out_romask_T_966; // @[RegisterRouter.scala:87:24] wire out_womask_966 = &_out_womask_T_966; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_966 = out_rivalid_1_820 & out_rimask_966; // @[RegisterRouter.scala:87:24] wire _out_T_9403 = out_f_rivalid_966; // @[RegisterRouter.scala:87:24] wire out_f_roready_966 = out_roready_1_820 & out_romask_966; // @[RegisterRouter.scala:87:24] wire _out_T_9404 = out_f_roready_966; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_966 = out_wivalid_1_820 & out_wimask_966; // @[RegisterRouter.scala:87:24] wire out_f_woready_966 = out_woready_1_820 & out_womask_966; // @[RegisterRouter.scala:87:24] wire _out_T_9405 = ~out_rimask_966; // @[RegisterRouter.scala:87:24] wire _out_T_9406 = ~out_wimask_966; // @[RegisterRouter.scala:87:24] wire _out_T_9407 = ~out_romask_966; // @[RegisterRouter.scala:87:24] wire _out_T_9408 = ~out_womask_966; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_825 = {hi_650, flags_0_go, _out_prepend_T_825}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9409 = out_prepend_825; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9410 = _out_T_9409; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_826 = _out_T_9410; // @[RegisterRouter.scala:87:24] wire out_rimask_967 = \|_out_rimask_T_967; // @[RegisterRouter.scala:87:24] wire out_wimask_967 = &_out_wimask_T_967; // @[RegisterRouter.scala:87:24] wire out_romask_967 = \|_out_romask_T_967; // @[RegisterRouter.scala:87:24] wire out_womask_967 = &_out_womask_T_967; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_967 = out_rivalid_1_821 & out_rimask_967; // @[RegisterRouter.scala:87:24] wire _out_T_9412 = out_f_rivalid_967; // @[RegisterRouter.scala:87:24] wire out_f_roready_967 = out_roready_1_821 & out_romask_967; // @[RegisterRouter.scala:87:24] wire _out_T_9413 = out_f_roready_967; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_967 = out_wivalid_1_821 & out_wimask_967; // @[RegisterRouter.scala:87:24] wire out_f_woready_967 = out_woready_1_821 & out_womask_967; // @[RegisterRouter.scala:87:24] wire _out_T_9414 = ~out_rimask_967; // @[RegisterRouter.scala:87:24] wire _out_T_9415 = ~out_wimask_967; // @[RegisterRouter.scala:87:24] wire _out_T_9416 = ~out_romask_967; // @[RegisterRouter.scala:87:24] wire _out_T_9417 = ~out_womask_967; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_826 = {hi_651, flags_0_go, _out_prepend_T_826}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9418 = out_prepend_826; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9419 = _out_T_9418; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_827 = _out_T_9419; // @[RegisterRouter.scala:87:24] wire out_rimask_968 = \|_out_rimask_T_968; // @[RegisterRouter.scala:87:24] wire out_wimask_968 = &_out_wimask_T_968; // @[RegisterRouter.scala:87:24] wire out_romask_968 = \|_out_romask_T_968; // @[RegisterRouter.scala:87:24] wire out_womask_968 = &_out_womask_T_968; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_968 = out_rivalid_1_822 & out_rimask_968; // @[RegisterRouter.scala:87:24] wire _out_T_9421 = out_f_rivalid_968; // @[RegisterRouter.scala:87:24] wire out_f_roready_968 = out_roready_1_822 & out_romask_968; // @[RegisterRouter.scala:87:24] wire _out_T_9422 = out_f_roready_968; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_968 = out_wivalid_1_822 & out_wimask_968; // @[RegisterRouter.scala:87:24] wire out_f_woready_968 = out_woready_1_822 & out_womask_968; // @[RegisterRouter.scala:87:24] wire _out_T_9423 = ~out_rimask_968; // @[RegisterRouter.scala:87:24] wire _out_T_9424 = ~out_wimask_968; // @[RegisterRouter.scala:87:24] wire _out_T_9425 = ~out_romask_968; // @[RegisterRouter.scala:87:24] wire _out_T_9426 = ~out_womask_968; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_827 = {hi_652, flags_0_go, _out_prepend_T_827}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9427 = out_prepend_827; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9428 = _out_T_9427; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_828 = _out_T_9428; // @[RegisterRouter.scala:87:24] wire out_rimask_969 = \|_out_rimask_T_969; // @[RegisterRouter.scala:87:24] wire out_wimask_969 = &_out_wimask_T_969; // @[RegisterRouter.scala:87:24] wire out_romask_969 = \|_out_romask_T_969; // @[RegisterRouter.scala:87:24] wire out_womask_969 = &_out_womask_T_969; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_969 = out_rivalid_1_823 & out_rimask_969; // @[RegisterRouter.scala:87:24] wire _out_T_9430 = out_f_rivalid_969; // @[RegisterRouter.scala:87:24] wire out_f_roready_969 = out_roready_1_823 & out_romask_969; // @[RegisterRouter.scala:87:24] wire _out_T_9431 = out_f_roready_969; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_969 = out_wivalid_1_823 & out_wimask_969; // @[RegisterRouter.scala:87:24] wire out_f_woready_969 = out_woready_1_823 & out_womask_969; // @[RegisterRouter.scala:87:24] wire _out_T_9432 = ~out_rimask_969; // @[RegisterRouter.scala:87:24] wire _out_T_9433 = ~out_wimask_969; // @[RegisterRouter.scala:87:24] wire _out_T_9434 = ~out_romask_969; // @[RegisterRouter.scala:87:24] wire _out_T_9435 = ~out_womask_969; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_828 = {hi_653, flags_0_go, _out_prepend_T_828}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9436 = out_prepend_828; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9437 = _out_T_9436; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_829 = _out_T_9437; // @[RegisterRouter.scala:87:24] wire out_rimask_970 = \|_out_rimask_T_970; // @[RegisterRouter.scala:87:24] wire out_wimask_970 = &_out_wimask_T_970; // @[RegisterRouter.scala:87:24] wire out_romask_970 = \|_out_romask_T_970; // @[RegisterRouter.scala:87:24] wire out_womask_970 = &_out_womask_T_970; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_970 = out_rivalid_1_824 & out_rimask_970; // @[RegisterRouter.scala:87:24] wire _out_T_9439 = out_f_rivalid_970; // @[RegisterRouter.scala:87:24] wire out_f_roready_970 = out_roready_1_824 & out_romask_970; // @[RegisterRouter.scala:87:24] wire _out_T_9440 = out_f_roready_970; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_970 = out_wivalid_1_824 & out_wimask_970; // @[RegisterRouter.scala:87:24] wire out_f_woready_970 = out_woready_1_824 & out_womask_970; // @[RegisterRouter.scala:87:24] wire _out_T_9441 = ~out_rimask_970; // @[RegisterRouter.scala:87:24] wire _out_T_9442 = ~out_wimask_970; // @[RegisterRouter.scala:87:24] wire _out_T_9443 = ~out_romask_970; // @[RegisterRouter.scala:87:24] wire _out_T_9444 = ~out_womask_970; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_829 = {hi_654, flags_0_go, _out_prepend_T_829}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9445 = out_prepend_829; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9446 = _out_T_9445; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_830 = _out_T_9446; // @[RegisterRouter.scala:87:24] wire out_rimask_971 = \|_out_rimask_T_971; // @[RegisterRouter.scala:87:24] wire out_wimask_971 = &_out_wimask_T_971; // @[RegisterRouter.scala:87:24] wire out_romask_971 = \|_out_romask_T_971; // @[RegisterRouter.scala:87:24] wire out_womask_971 = &_out_womask_T_971; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_971 = out_rivalid_1_825 & out_rimask_971; // @[RegisterRouter.scala:87:24] wire _out_T_9448 = out_f_rivalid_971; // @[RegisterRouter.scala:87:24] wire out_f_roready_971 = out_roready_1_825 & out_romask_971; // @[RegisterRouter.scala:87:24] wire _out_T_9449 = out_f_roready_971; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_971 = out_wivalid_1_825 & out_wimask_971; // @[RegisterRouter.scala:87:24] wire out_f_woready_971 = out_woready_1_825 & out_womask_971; // @[RegisterRouter.scala:87:24] wire _out_T_9450 = ~out_rimask_971; // @[RegisterRouter.scala:87:24] wire _out_T_9451 = ~out_wimask_971; // @[RegisterRouter.scala:87:24] wire _out_T_9452 = ~out_romask_971; // @[RegisterRouter.scala:87:24] wire _out_T_9453 = ~out_womask_971; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_830 = {hi_655, flags_0_go, _out_prepend_T_830}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9454 = out_prepend_830; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9455 = _out_T_9454; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_831 = _out_T_9455; // @[RegisterRouter.scala:87:24] wire out_rimask_972 = \|_out_rimask_T_972; // @[RegisterRouter.scala:87:24] wire out_wimask_972 = &_out_wimask_T_972; // @[RegisterRouter.scala:87:24] wire out_romask_972 = \|_out_romask_T_972; // @[RegisterRouter.scala:87:24] wire out_womask_972 = &_out_womask_T_972; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_972 = out_rivalid_1_826 & out_rimask_972; // @[RegisterRouter.scala:87:24] wire _out_T_9457 = out_f_rivalid_972; // @[RegisterRouter.scala:87:24] wire out_f_roready_972 = out_roready_1_826 & out_romask_972; // @[RegisterRouter.scala:87:24] wire _out_T_9458 = out_f_roready_972; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_972 = out_wivalid_1_826 & out_wimask_972; // @[RegisterRouter.scala:87:24] wire out_f_woready_972 = out_woready_1_826 & out_womask_972; // @[RegisterRouter.scala:87:24] wire _out_T_9459 = ~out_rimask_972; // @[RegisterRouter.scala:87:24] wire _out_T_9460 = ~out_wimask_972; // @[RegisterRouter.scala:87:24] wire _out_T_9461 = ~out_romask_972; // @[RegisterRouter.scala:87:24] wire _out_T_9462 = ~out_womask_972; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_831 = {hi_656, flags_0_go, _out_prepend_T_831}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9463 = out_prepend_831; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9464 = _out_T_9463; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_209 = _out_T_9464; // @[MuxLiteral.scala:49:48] wire out_rimask_973 = \|_out_rimask_T_973; // @[RegisterRouter.scala:87:24] wire out_wimask_973 = &_out_wimask_T_973; // @[RegisterRouter.scala:87:24] wire out_romask_973 = \|_out_romask_T_973; // @[RegisterRouter.scala:87:24] wire out_womask_973 = &_out_womask_T_973; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_973 = out_rivalid_1_827 & out_rimask_973; // @[RegisterRouter.scala:87:24] wire _out_T_9466 = out_f_rivalid_973; // @[RegisterRouter.scala:87:24] wire out_f_roready_973 = out_roready_1_827 & out_romask_973; // @[RegisterRouter.scala:87:24] wire _out_T_9467 = out_f_roready_973; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_973 = out_wivalid_1_827 & out_wimask_973; // @[RegisterRouter.scala:87:24] wire _out_T_9468 = out_f_wivalid_973; // @[RegisterRouter.scala:87:24] wire out_f_woready_973 = out_woready_1_827 & out_womask_973; // @[RegisterRouter.scala:87:24] wire _out_T_9469 = out_f_woready_973; // @[RegisterRouter.scala:87:24] wire _out_T_9470 = ~out_rimask_973; // @[RegisterRouter.scala:87:24] wire _out_T_9471 = ~out_wimask_973; // @[RegisterRouter.scala:87:24] wire _out_T_9472 = ~out_romask_973; // @[RegisterRouter.scala:87:24] wire _out_T_9473 = ~out_womask_973; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9475 = _out_T_9474; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_832 = _out_T_9475; // @[RegisterRouter.scala:87:24] wire out_rimask_974 = \|_out_rimask_T_974; // @[RegisterRouter.scala:87:24] wire out_wimask_974 = &_out_wimask_T_974; // @[RegisterRouter.scala:87:24] wire out_romask_974 = \|_out_romask_T_974; // @[RegisterRouter.scala:87:24] wire out_womask_974 = &_out_womask_T_974; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_974 = out_rivalid_1_828 & out_rimask_974; // @[RegisterRouter.scala:87:24] wire _out_T_9477 = out_f_rivalid_974; // @[RegisterRouter.scala:87:24] wire out_f_roready_974 = out_roready_1_828 & out_romask_974; // @[RegisterRouter.scala:87:24] wire _out_T_9478 = out_f_roready_974; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_974 = out_wivalid_1_828 & out_wimask_974; // @[RegisterRouter.scala:87:24] wire _out_T_9479 = out_f_wivalid_974; // @[RegisterRouter.scala:87:24] wire out_f_woready_974 = out_woready_1_828 & out_womask_974; // @[RegisterRouter.scala:87:24] wire _out_T_9480 = out_f_woready_974; // @[RegisterRouter.scala:87:24] wire _out_T_9481 = ~out_rimask_974; // @[RegisterRouter.scala:87:24] wire _out_T_9482 = ~out_wimask_974; // @[RegisterRouter.scala:87:24] wire _out_T_9483 = ~out_romask_974; // @[RegisterRouter.scala:87:24] wire _out_T_9484 = ~out_womask_974; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_832 = {abstractDataMem_1, _out_prepend_T_832}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9485 = out_prepend_832; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9486 = _out_T_9485; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_833 = _out_T_9486; // @[RegisterRouter.scala:87:24] wire out_rimask_975 = \|_out_rimask_T_975; // @[RegisterRouter.scala:87:24] wire out_wimask_975 = &_out_wimask_T_975; // @[RegisterRouter.scala:87:24] wire out_romask_975 = \|_out_romask_T_975; // @[RegisterRouter.scala:87:24] wire out_womask_975 = &_out_womask_T_975; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_975 = out_rivalid_1_829 & out_rimask_975; // @[RegisterRouter.scala:87:24] wire _out_T_9488 = out_f_rivalid_975; // @[RegisterRouter.scala:87:24] wire out_f_roready_975 = out_roready_1_829 & out_romask_975; // @[RegisterRouter.scala:87:24] wire _out_T_9489 = out_f_roready_975; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_975 = out_wivalid_1_829 & out_wimask_975; // @[RegisterRouter.scala:87:24] wire _out_T_9490 = out_f_wivalid_975; // @[RegisterRouter.scala:87:24] wire out_f_woready_975 = out_woready_1_829 & out_womask_975; // @[RegisterRouter.scala:87:24] wire _out_T_9491 = out_f_woready_975; // @[RegisterRouter.scala:87:24] wire _out_T_9492 = ~out_rimask_975; // @[RegisterRouter.scala:87:24] wire _out_T_9493 = ~out_wimask_975; // @[RegisterRouter.scala:87:24] wire _out_T_9494 = ~out_romask_975; // @[RegisterRouter.scala:87:24] wire _out_T_9495 = ~out_womask_975; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_833 = {abstractDataMem_2, _out_prepend_T_833}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9496 = out_prepend_833; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9497 = _out_T_9496; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_834 = _out_T_9497; // @[RegisterRouter.scala:87:24] wire out_rimask_976 = \|_out_rimask_T_976; // @[RegisterRouter.scala:87:24] wire out_wimask_976 = &_out_wimask_T_976; // @[RegisterRouter.scala:87:24] wire out_romask_976 = \|_out_romask_T_976; // @[RegisterRouter.scala:87:24] wire out_womask_976 = &_out_womask_T_976; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_976 = out_rivalid_1_830 & out_rimask_976; // @[RegisterRouter.scala:87:24] wire _out_T_9499 = out_f_rivalid_976; // @[RegisterRouter.scala:87:24] wire out_f_roready_976 = out_roready_1_830 & out_romask_976; // @[RegisterRouter.scala:87:24] wire _out_T_9500 = out_f_roready_976; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_976 = out_wivalid_1_830 & out_wimask_976; // @[RegisterRouter.scala:87:24] wire _out_T_9501 = out_f_wivalid_976; // @[RegisterRouter.scala:87:24] wire out_f_woready_976 = out_woready_1_830 & out_womask_976; // @[RegisterRouter.scala:87:24] wire _out_T_9502 = out_f_woready_976; // @[RegisterRouter.scala:87:24] wire _out_T_9503 = ~out_rimask_976; // @[RegisterRouter.scala:87:24] wire _out_T_9504 = ~out_wimask_976; // @[RegisterRouter.scala:87:24] wire _out_T_9505 = ~out_romask_976; // @[RegisterRouter.scala:87:24] wire _out_T_9506 = ~out_womask_976; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_834 = {abstractDataMem_3, _out_prepend_T_834}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9507 = out_prepend_834; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9508 = _out_T_9507; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_835 = _out_T_9508; // @[RegisterRouter.scala:87:24] wire out_rimask_977 = \|_out_rimask_T_977; // @[RegisterRouter.scala:87:24] wire out_wimask_977 = &_out_wimask_T_977; // @[RegisterRouter.scala:87:24] wire out_romask_977 = \|_out_romask_T_977; // @[RegisterRouter.scala:87:24] wire out_womask_977 = &_out_womask_T_977; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_977 = out_rivalid_1_831 & out_rimask_977; // @[RegisterRouter.scala:87:24] wire _out_T_9510 = out_f_rivalid_977; // @[RegisterRouter.scala:87:24] wire out_f_roready_977 = out_roready_1_831 & out_romask_977; // @[RegisterRouter.scala:87:24] wire _out_T_9511 = out_f_roready_977; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_977 = out_wivalid_1_831 & out_wimask_977; // @[RegisterRouter.scala:87:24] wire _out_T_9512 = out_f_wivalid_977; // @[RegisterRouter.scala:87:24] wire out_f_woready_977 = out_woready_1_831 & out_womask_977; // @[RegisterRouter.scala:87:24] wire _out_T_9513 = out_f_woready_977; // @[RegisterRouter.scala:87:24] wire _out_T_9514 = ~out_rimask_977; // @[RegisterRouter.scala:87:24] wire _out_T_9515 = ~out_wimask_977; // @[RegisterRouter.scala:87:24] wire _out_T_9516 = ~out_romask_977; // @[RegisterRouter.scala:87:24] wire _out_T_9517 = ~out_womask_977; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_835 = {abstractDataMem_4, _out_prepend_T_835}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9518 = out_prepend_835; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9519 = _out_T_9518; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_836 = _out_T_9519; // @[RegisterRouter.scala:87:24] wire out_rimask_978 = \|_out_rimask_T_978; // @[RegisterRouter.scala:87:24] wire out_wimask_978 = &_out_wimask_T_978; // @[RegisterRouter.scala:87:24] wire out_romask_978 = \|_out_romask_T_978; // @[RegisterRouter.scala:87:24] wire out_womask_978 = &_out_womask_T_978; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_978 = out_rivalid_1_832 & out_rimask_978; // @[RegisterRouter.scala:87:24] wire _out_T_9521 = out_f_rivalid_978; // @[RegisterRouter.scala:87:24] wire out_f_roready_978 = out_roready_1_832 & out_romask_978; // @[RegisterRouter.scala:87:24] wire _out_T_9522 = out_f_roready_978; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_978 = out_wivalid_1_832 & out_wimask_978; // @[RegisterRouter.scala:87:24] wire _out_T_9523 = out_f_wivalid_978; // @[RegisterRouter.scala:87:24] wire out_f_woready_978 = out_woready_1_832 & out_womask_978; // @[RegisterRouter.scala:87:24] wire _out_T_9524 = out_f_woready_978; // @[RegisterRouter.scala:87:24] wire _out_T_9525 = ~out_rimask_978; // @[RegisterRouter.scala:87:24] wire _out_T_9526 = ~out_wimask_978; // @[RegisterRouter.scala:87:24] wire _out_T_9527 = ~out_romask_978; // @[RegisterRouter.scala:87:24] wire _out_T_9528 = ~out_womask_978; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_836 = {abstractDataMem_5, _out_prepend_T_836}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9529 = out_prepend_836; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9530 = _out_T_9529; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_837 = _out_T_9530; // @[RegisterRouter.scala:87:24] wire out_rimask_979 = \|_out_rimask_T_979; // @[RegisterRouter.scala:87:24] wire out_wimask_979 = &_out_wimask_T_979; // @[RegisterRouter.scala:87:24] wire out_romask_979 = \|_out_romask_T_979; // @[RegisterRouter.scala:87:24] wire out_womask_979 = &_out_womask_T_979; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_979 = out_rivalid_1_833 & out_rimask_979; // @[RegisterRouter.scala:87:24] wire _out_T_9532 = out_f_rivalid_979; // @[RegisterRouter.scala:87:24] wire out_f_roready_979 = out_roready_1_833 & out_romask_979; // @[RegisterRouter.scala:87:24] wire _out_T_9533 = out_f_roready_979; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_979 = out_wivalid_1_833 & out_wimask_979; // @[RegisterRouter.scala:87:24] wire _out_T_9534 = out_f_wivalid_979; // @[RegisterRouter.scala:87:24] wire out_f_woready_979 = out_woready_1_833 & out_womask_979; // @[RegisterRouter.scala:87:24] wire _out_T_9535 = out_f_woready_979; // @[RegisterRouter.scala:87:24] wire _out_T_9536 = ~out_rimask_979; // @[RegisterRouter.scala:87:24] wire _out_T_9537 = ~out_wimask_979; // @[RegisterRouter.scala:87:24] wire _out_T_9538 = ~out_romask_979; // @[RegisterRouter.scala:87:24] wire _out_T_9539 = ~out_womask_979; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_837 = {abstractDataMem_6, _out_prepend_T_837}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9540 = out_prepend_837; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9541 = _out_T_9540; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_838 = _out_T_9541; // @[RegisterRouter.scala:87:24] wire out_rimask_980 = \|_out_rimask_T_980; // @[RegisterRouter.scala:87:24] wire out_wimask_980 = &_out_wimask_T_980; // @[RegisterRouter.scala:87:24] wire out_romask_980 = \|_out_romask_T_980; // @[RegisterRouter.scala:87:24] wire out_womask_980 = &_out_womask_T_980; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_980 = out_rivalid_1_834 & out_rimask_980; // @[RegisterRouter.scala:87:24] wire _out_T_9543 = out_f_rivalid_980; // @[RegisterRouter.scala:87:24] wire out_f_roready_980 = out_roready_1_834 & out_romask_980; // @[RegisterRouter.scala:87:24] wire _out_T_9544 = out_f_roready_980; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_980 = out_wivalid_1_834 & out_wimask_980; // @[RegisterRouter.scala:87:24] wire _out_T_9545 = out_f_wivalid_980; // @[RegisterRouter.scala:87:24] wire out_f_woready_980 = out_woready_1_834 & out_womask_980; // @[RegisterRouter.scala:87:24] wire _out_T_9546 = out_f_woready_980; // @[RegisterRouter.scala:87:24] wire _out_T_9547 = ~out_rimask_980; // @[RegisterRouter.scala:87:24] wire _out_T_9548 = ~out_wimask_980; // @[RegisterRouter.scala:87:24] wire _out_T_9549 = ~out_romask_980; // @[RegisterRouter.scala:87:24] wire _out_T_9550 = ~out_womask_980; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_838 = {abstractDataMem_7, _out_prepend_T_838}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9551 = out_prepend_838; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9552 = _out_T_9551; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_112 = _out_T_9552; // @[MuxLiteral.scala:49:48] wire out_rimask_981 = \|_out_rimask_T_981; // @[RegisterRouter.scala:87:24] wire out_wimask_981 = &_out_wimask_T_981; // @[RegisterRouter.scala:87:24] wire out_romask_981 = \|_out_romask_T_981; // @[RegisterRouter.scala:87:24] wire out_womask_981 = &_out_womask_T_981; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_981 = out_rivalid_1_835 & out_rimask_981; // @[RegisterRouter.scala:87:24] wire _out_T_9554 = out_f_rivalid_981; // @[RegisterRouter.scala:87:24] wire out_f_roready_981 = out_roready_1_835 & out_romask_981; // @[RegisterRouter.scala:87:24] wire _out_T_9555 = out_f_roready_981; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_981 = out_wivalid_1_835 & out_wimask_981; // @[RegisterRouter.scala:87:24] wire out_f_woready_981 = out_woready_1_835 & out_womask_981; // @[RegisterRouter.scala:87:24] wire _out_T_9556 = ~out_rimask_981; // @[RegisterRouter.scala:87:24] wire _out_T_9557 = ~out_wimask_981; // @[RegisterRouter.scala:87:24] wire _out_T_9558 = ~out_romask_981; // @[RegisterRouter.scala:87:24] wire _out_T_9559 = ~out_womask_981; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9561 = _out_T_9560; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_839 = _out_T_9561; // @[RegisterRouter.scala:87:24] wire out_rimask_982 = \|_out_rimask_T_982; // @[RegisterRouter.scala:87:24] wire out_wimask_982 = &_out_wimask_T_982; // @[RegisterRouter.scala:87:24] wire out_romask_982 = \|_out_romask_T_982; // @[RegisterRouter.scala:87:24] wire out_womask_982 = &_out_womask_T_982; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_982 = out_rivalid_1_836 & out_rimask_982; // @[RegisterRouter.scala:87:24] wire _out_T_9563 = out_f_rivalid_982; // @[RegisterRouter.scala:87:24] wire out_f_roready_982 = out_roready_1_836 & out_romask_982; // @[RegisterRouter.scala:87:24] wire _out_T_9564 = out_f_roready_982; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_982 = out_wivalid_1_836 & out_wimask_982; // @[RegisterRouter.scala:87:24] wire out_f_woready_982 = out_woready_1_836 & out_womask_982; // @[RegisterRouter.scala:87:24] wire _out_T_9565 = ~out_rimask_982; // @[RegisterRouter.scala:87:24] wire _out_T_9566 = ~out_wimask_982; // @[RegisterRouter.scala:87:24] wire _out_T_9567 = ~out_romask_982; // @[RegisterRouter.scala:87:24] wire _out_T_9568 = ~out_womask_982; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_839 = {hi_530, flags_0_go, _out_prepend_T_839}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9569 = out_prepend_839; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9570 = _out_T_9569; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_840 = _out_T_9570; // @[RegisterRouter.scala:87:24] wire out_rimask_983 = \|_out_rimask_T_983; // @[RegisterRouter.scala:87:24] wire out_wimask_983 = &_out_wimask_T_983; // @[RegisterRouter.scala:87:24] wire out_romask_983 = \|_out_romask_T_983; // @[RegisterRouter.scala:87:24] wire out_womask_983 = &_out_womask_T_983; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_983 = out_rivalid_1_837 & out_rimask_983; // @[RegisterRouter.scala:87:24] wire _out_T_9572 = out_f_rivalid_983; // @[RegisterRouter.scala:87:24] wire out_f_roready_983 = out_roready_1_837 & out_romask_983; // @[RegisterRouter.scala:87:24] wire _out_T_9573 = out_f_roready_983; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_983 = out_wivalid_1_837 & out_wimask_983; // @[RegisterRouter.scala:87:24] wire out_f_woready_983 = out_woready_1_837 & out_womask_983; // @[RegisterRouter.scala:87:24] wire _out_T_9574 = ~out_rimask_983; // @[RegisterRouter.scala:87:24] wire _out_T_9575 = ~out_wimask_983; // @[RegisterRouter.scala:87:24] wire _out_T_9576 = ~out_romask_983; // @[RegisterRouter.scala:87:24] wire _out_T_9577 = ~out_womask_983; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_840 = {hi_531, flags_0_go, _out_prepend_T_840}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9578 = out_prepend_840; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9579 = _out_T_9578; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_841 = _out_T_9579; // @[RegisterRouter.scala:87:24] wire out_rimask_984 = \|_out_rimask_T_984; // @[RegisterRouter.scala:87:24] wire out_wimask_984 = &_out_wimask_T_984; // @[RegisterRouter.scala:87:24] wire out_romask_984 = \|_out_romask_T_984; // @[RegisterRouter.scala:87:24] wire out_womask_984 = &_out_womask_T_984; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_984 = out_rivalid_1_838 & out_rimask_984; // @[RegisterRouter.scala:87:24] wire _out_T_9581 = out_f_rivalid_984; // @[RegisterRouter.scala:87:24] wire out_f_roready_984 = out_roready_1_838 & out_romask_984; // @[RegisterRouter.scala:87:24] wire _out_T_9582 = out_f_roready_984; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_984 = out_wivalid_1_838 & out_wimask_984; // @[RegisterRouter.scala:87:24] wire out_f_woready_984 = out_woready_1_838 & out_womask_984; // @[RegisterRouter.scala:87:24] wire _out_T_9583 = ~out_rimask_984; // @[RegisterRouter.scala:87:24] wire _out_T_9584 = ~out_wimask_984; // @[RegisterRouter.scala:87:24] wire _out_T_9585 = ~out_romask_984; // @[RegisterRouter.scala:87:24] wire _out_T_9586 = ~out_womask_984; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_841 = {hi_532, flags_0_go, _out_prepend_T_841}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9587 = out_prepend_841; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9588 = _out_T_9587; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_842 = _out_T_9588; // @[RegisterRouter.scala:87:24] wire out_rimask_985 = \|_out_rimask_T_985; // @[RegisterRouter.scala:87:24] wire out_wimask_985 = &_out_wimask_T_985; // @[RegisterRouter.scala:87:24] wire out_romask_985 = \|_out_romask_T_985; // @[RegisterRouter.scala:87:24] wire out_womask_985 = &_out_womask_T_985; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_985 = out_rivalid_1_839 & out_rimask_985; // @[RegisterRouter.scala:87:24] wire _out_T_9590 = out_f_rivalid_985; // @[RegisterRouter.scala:87:24] wire out_f_roready_985 = out_roready_1_839 & out_romask_985; // @[RegisterRouter.scala:87:24] wire _out_T_9591 = out_f_roready_985; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_985 = out_wivalid_1_839 & out_wimask_985; // @[RegisterRouter.scala:87:24] wire out_f_woready_985 = out_woready_1_839 & out_womask_985; // @[RegisterRouter.scala:87:24] wire _out_T_9592 = ~out_rimask_985; // @[RegisterRouter.scala:87:24] wire _out_T_9593 = ~out_wimask_985; // @[RegisterRouter.scala:87:24] wire _out_T_9594 = ~out_romask_985; // @[RegisterRouter.scala:87:24] wire _out_T_9595 = ~out_womask_985; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_842 = {hi_533, flags_0_go, _out_prepend_T_842}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9596 = out_prepend_842; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9597 = _out_T_9596; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_843 = _out_T_9597; // @[RegisterRouter.scala:87:24] wire out_rimask_986 = \|_out_rimask_T_986; // @[RegisterRouter.scala:87:24] wire out_wimask_986 = &_out_wimask_T_986; // @[RegisterRouter.scala:87:24] wire out_romask_986 = \|_out_romask_T_986; // @[RegisterRouter.scala:87:24] wire out_womask_986 = &_out_womask_T_986; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_986 = out_rivalid_1_840 & out_rimask_986; // @[RegisterRouter.scala:87:24] wire _out_T_9599 = out_f_rivalid_986; // @[RegisterRouter.scala:87:24] wire out_f_roready_986 = out_roready_1_840 & out_romask_986; // @[RegisterRouter.scala:87:24] wire _out_T_9600 = out_f_roready_986; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_986 = out_wivalid_1_840 & out_wimask_986; // @[RegisterRouter.scala:87:24] wire out_f_woready_986 = out_woready_1_840 & out_womask_986; // @[RegisterRouter.scala:87:24] wire _out_T_9601 = ~out_rimask_986; // @[RegisterRouter.scala:87:24] wire _out_T_9602 = ~out_wimask_986; // @[RegisterRouter.scala:87:24] wire _out_T_9603 = ~out_romask_986; // @[RegisterRouter.scala:87:24] wire _out_T_9604 = ~out_womask_986; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_843 = {hi_534, flags_0_go, _out_prepend_T_843}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9605 = out_prepend_843; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9606 = _out_T_9605; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_844 = _out_T_9606; // @[RegisterRouter.scala:87:24] wire out_rimask_987 = \|_out_rimask_T_987; // @[RegisterRouter.scala:87:24] wire out_wimask_987 = &_out_wimask_T_987; // @[RegisterRouter.scala:87:24] wire out_romask_987 = \|_out_romask_T_987; // @[RegisterRouter.scala:87:24] wire out_womask_987 = &_out_womask_T_987; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_987 = out_rivalid_1_841 & out_rimask_987; // @[RegisterRouter.scala:87:24] wire _out_T_9608 = out_f_rivalid_987; // @[RegisterRouter.scala:87:24] wire out_f_roready_987 = out_roready_1_841 & out_romask_987; // @[RegisterRouter.scala:87:24] wire _out_T_9609 = out_f_roready_987; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_987 = out_wivalid_1_841 & out_wimask_987; // @[RegisterRouter.scala:87:24] wire out_f_woready_987 = out_woready_1_841 & out_womask_987; // @[RegisterRouter.scala:87:24] wire _out_T_9610 = ~out_rimask_987; // @[RegisterRouter.scala:87:24] wire _out_T_9611 = ~out_wimask_987; // @[RegisterRouter.scala:87:24] wire _out_T_9612 = ~out_romask_987; // @[RegisterRouter.scala:87:24] wire _out_T_9613 = ~out_womask_987; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_844 = {hi_535, flags_0_go, _out_prepend_T_844}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9614 = out_prepend_844; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9615 = _out_T_9614; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_845 = _out_T_9615; // @[RegisterRouter.scala:87:24] wire out_rimask_988 = \|_out_rimask_T_988; // @[RegisterRouter.scala:87:24] wire out_wimask_988 = &_out_wimask_T_988; // @[RegisterRouter.scala:87:24] wire out_romask_988 = \|_out_romask_T_988; // @[RegisterRouter.scala:87:24] wire out_womask_988 = &_out_womask_T_988; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_988 = out_rivalid_1_842 & out_rimask_988; // @[RegisterRouter.scala:87:24] wire _out_T_9617 = out_f_rivalid_988; // @[RegisterRouter.scala:87:24] wire out_f_roready_988 = out_roready_1_842 & out_romask_988; // @[RegisterRouter.scala:87:24] wire _out_T_9618 = out_f_roready_988; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_988 = out_wivalid_1_842 & out_wimask_988; // @[RegisterRouter.scala:87:24] wire out_f_woready_988 = out_woready_1_842 & out_womask_988; // @[RegisterRouter.scala:87:24] wire _out_T_9619 = ~out_rimask_988; // @[RegisterRouter.scala:87:24] wire _out_T_9620 = ~out_wimask_988; // @[RegisterRouter.scala:87:24] wire _out_T_9621 = ~out_romask_988; // @[RegisterRouter.scala:87:24] wire _out_T_9622 = ~out_womask_988; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_845 = {hi_536, flags_0_go, _out_prepend_T_845}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9623 = out_prepend_845; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9624 = _out_T_9623; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_194 = _out_T_9624; // @[MuxLiteral.scala:49:48] wire out_rimask_989 = \|_out_rimask_T_989; // @[RegisterRouter.scala:87:24] wire out_wimask_989 = &_out_wimask_T_989; // @[RegisterRouter.scala:87:24] wire out_romask_989 = \|_out_romask_T_989; // @[RegisterRouter.scala:87:24] wire out_womask_989 = &_out_womask_T_989; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_989 = out_rivalid_1_843 & out_rimask_989; // @[RegisterRouter.scala:87:24] wire _out_T_9626 = out_f_rivalid_989; // @[RegisterRouter.scala:87:24] wire out_f_roready_989 = out_roready_1_843 & out_romask_989; // @[RegisterRouter.scala:87:24] wire _out_T_9627 = out_f_roready_989; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_989 = out_wivalid_1_843 & out_wimask_989; // @[RegisterRouter.scala:87:24] wire out_f_woready_989 = out_woready_1_843 & out_womask_989; // @[RegisterRouter.scala:87:24] wire _out_T_9628 = ~out_rimask_989; // @[RegisterRouter.scala:87:24] wire _out_T_9629 = ~out_wimask_989; // @[RegisterRouter.scala:87:24] wire _out_T_9630 = ~out_romask_989; // @[RegisterRouter.scala:87:24] wire _out_T_9631 = ~out_womask_989; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9633 = _out_T_9632; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_846 = _out_T_9633; // @[RegisterRouter.scala:87:24] wire out_rimask_990 = \|_out_rimask_T_990; // @[RegisterRouter.scala:87:24] wire out_wimask_990 = &_out_wimask_T_990; // @[RegisterRouter.scala:87:24] wire out_romask_990 = \|_out_romask_T_990; // @[RegisterRouter.scala:87:24] wire out_womask_990 = &_out_womask_T_990; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_990 = out_rivalid_1_844 & out_rimask_990; // @[RegisterRouter.scala:87:24] wire _out_T_9635 = out_f_rivalid_990; // @[RegisterRouter.scala:87:24] wire out_f_roready_990 = out_roready_1_844 & out_romask_990; // @[RegisterRouter.scala:87:24] wire _out_T_9636 = out_f_roready_990; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_990 = out_wivalid_1_844 & out_wimask_990; // @[RegisterRouter.scala:87:24] wire out_f_woready_990 = out_woready_1_844 & out_womask_990; // @[RegisterRouter.scala:87:24] wire _out_T_9637 = ~out_rimask_990; // @[RegisterRouter.scala:87:24] wire _out_T_9638 = ~out_wimask_990; // @[RegisterRouter.scala:87:24] wire _out_T_9639 = ~out_romask_990; // @[RegisterRouter.scala:87:24] wire _out_T_9640 = ~out_womask_990; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_846 = {hi_138, flags_0_go, _out_prepend_T_846}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9641 = out_prepend_846; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9642 = _out_T_9641; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_847 = _out_T_9642; // @[RegisterRouter.scala:87:24] wire out_rimask_991 = \|_out_rimask_T_991; // @[RegisterRouter.scala:87:24] wire out_wimask_991 = &_out_wimask_T_991; // @[RegisterRouter.scala:87:24] wire out_romask_991 = \|_out_romask_T_991; // @[RegisterRouter.scala:87:24] wire out_womask_991 = &_out_womask_T_991; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_991 = out_rivalid_1_845 & out_rimask_991; // @[RegisterRouter.scala:87:24] wire _out_T_9644 = out_f_rivalid_991; // @[RegisterRouter.scala:87:24] wire out_f_roready_991 = out_roready_1_845 & out_romask_991; // @[RegisterRouter.scala:87:24] wire _out_T_9645 = out_f_roready_991; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_991 = out_wivalid_1_845 & out_wimask_991; // @[RegisterRouter.scala:87:24] wire out_f_woready_991 = out_woready_1_845 & out_womask_991; // @[RegisterRouter.scala:87:24] wire _out_T_9646 = ~out_rimask_991; // @[RegisterRouter.scala:87:24] wire _out_T_9647 = ~out_wimask_991; // @[RegisterRouter.scala:87:24] wire _out_T_9648 = ~out_romask_991; // @[RegisterRouter.scala:87:24] wire _out_T_9649 = ~out_womask_991; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_847 = {hi_139, flags_0_go, _out_prepend_T_847}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9650 = out_prepend_847; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9651 = _out_T_9650; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_848 = _out_T_9651; // @[RegisterRouter.scala:87:24] wire out_rimask_992 = \|_out_rimask_T_992; // @[RegisterRouter.scala:87:24] wire out_wimask_992 = &_out_wimask_T_992; // @[RegisterRouter.scala:87:24] wire out_romask_992 = \|_out_romask_T_992; // @[RegisterRouter.scala:87:24] wire out_womask_992 = &_out_womask_T_992; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_992 = out_rivalid_1_846 & out_rimask_992; // @[RegisterRouter.scala:87:24] wire _out_T_9653 = out_f_rivalid_992; // @[RegisterRouter.scala:87:24] wire out_f_roready_992 = out_roready_1_846 & out_romask_992; // @[RegisterRouter.scala:87:24] wire _out_T_9654 = out_f_roready_992; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_992 = out_wivalid_1_846 & out_wimask_992; // @[RegisterRouter.scala:87:24] wire out_f_woready_992 = out_woready_1_846 & out_womask_992; // @[RegisterRouter.scala:87:24] wire _out_T_9655 = ~out_rimask_992; // @[RegisterRouter.scala:87:24] wire _out_T_9656 = ~out_wimask_992; // @[RegisterRouter.scala:87:24] wire _out_T_9657 = ~out_romask_992; // @[RegisterRouter.scala:87:24] wire _out_T_9658 = ~out_womask_992; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_848 = {hi_140, flags_0_go, _out_prepend_T_848}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9659 = out_prepend_848; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9660 = _out_T_9659; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_849 = _out_T_9660; // @[RegisterRouter.scala:87:24] wire out_rimask_993 = \|_out_rimask_T_993; // @[RegisterRouter.scala:87:24] wire out_wimask_993 = &_out_wimask_T_993; // @[RegisterRouter.scala:87:24] wire out_romask_993 = \|_out_romask_T_993; // @[RegisterRouter.scala:87:24] wire out_womask_993 = &_out_womask_T_993; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_993 = out_rivalid_1_847 & out_rimask_993; // @[RegisterRouter.scala:87:24] wire _out_T_9662 = out_f_rivalid_993; // @[RegisterRouter.scala:87:24] wire out_f_roready_993 = out_roready_1_847 & out_romask_993; // @[RegisterRouter.scala:87:24] wire _out_T_9663 = out_f_roready_993; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_993 = out_wivalid_1_847 & out_wimask_993; // @[RegisterRouter.scala:87:24] wire out_f_woready_993 = out_woready_1_847 & out_womask_993; // @[RegisterRouter.scala:87:24] wire _out_T_9664 = ~out_rimask_993; // @[RegisterRouter.scala:87:24] wire _out_T_9665 = ~out_wimask_993; // @[RegisterRouter.scala:87:24] wire _out_T_9666 = ~out_romask_993; // @[RegisterRouter.scala:87:24] wire _out_T_9667 = ~out_womask_993; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_849 = {hi_141, flags_0_go, _out_prepend_T_849}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9668 = out_prepend_849; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9669 = _out_T_9668; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_850 = _out_T_9669; // @[RegisterRouter.scala:87:24] wire out_rimask_994 = \|_out_rimask_T_994; // @[RegisterRouter.scala:87:24] wire out_wimask_994 = &_out_wimask_T_994; // @[RegisterRouter.scala:87:24] wire out_romask_994 = \|_out_romask_T_994; // @[RegisterRouter.scala:87:24] wire out_womask_994 = &_out_womask_T_994; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_994 = out_rivalid_1_848 & out_rimask_994; // @[RegisterRouter.scala:87:24] wire _out_T_9671 = out_f_rivalid_994; // @[RegisterRouter.scala:87:24] wire out_f_roready_994 = out_roready_1_848 & out_romask_994; // @[RegisterRouter.scala:87:24] wire _out_T_9672 = out_f_roready_994; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_994 = out_wivalid_1_848 & out_wimask_994; // @[RegisterRouter.scala:87:24] wire out_f_woready_994 = out_woready_1_848 & out_womask_994; // @[RegisterRouter.scala:87:24] wire _out_T_9673 = ~out_rimask_994; // @[RegisterRouter.scala:87:24] wire _out_T_9674 = ~out_wimask_994; // @[RegisterRouter.scala:87:24] wire _out_T_9675 = ~out_romask_994; // @[RegisterRouter.scala:87:24] wire _out_T_9676 = ~out_womask_994; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_850 = {hi_142, flags_0_go, _out_prepend_T_850}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9677 = out_prepend_850; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9678 = _out_T_9677; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_851 = _out_T_9678; // @[RegisterRouter.scala:87:24] wire out_rimask_995 = \|_out_rimask_T_995; // @[RegisterRouter.scala:87:24] wire out_wimask_995 = &_out_wimask_T_995; // @[RegisterRouter.scala:87:24] wire out_romask_995 = \|_out_romask_T_995; // @[RegisterRouter.scala:87:24] wire out_womask_995 = &_out_womask_T_995; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_995 = out_rivalid_1_849 & out_rimask_995; // @[RegisterRouter.scala:87:24] wire _out_T_9680 = out_f_rivalid_995; // @[RegisterRouter.scala:87:24] wire out_f_roready_995 = out_roready_1_849 & out_romask_995; // @[RegisterRouter.scala:87:24] wire _out_T_9681 = out_f_roready_995; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_995 = out_wivalid_1_849 & out_wimask_995; // @[RegisterRouter.scala:87:24] wire out_f_woready_995 = out_woready_1_849 & out_womask_995; // @[RegisterRouter.scala:87:24] wire _out_T_9682 = ~out_rimask_995; // @[RegisterRouter.scala:87:24] wire _out_T_9683 = ~out_wimask_995; // @[RegisterRouter.scala:87:24] wire _out_T_9684 = ~out_romask_995; // @[RegisterRouter.scala:87:24] wire _out_T_9685 = ~out_womask_995; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_851 = {hi_143, flags_0_go, _out_prepend_T_851}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9686 = out_prepend_851; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9687 = _out_T_9686; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_852 = _out_T_9687; // @[RegisterRouter.scala:87:24] wire out_rimask_996 = \|_out_rimask_T_996; // @[RegisterRouter.scala:87:24] wire out_wimask_996 = &_out_wimask_T_996; // @[RegisterRouter.scala:87:24] wire out_romask_996 = \|_out_romask_T_996; // @[RegisterRouter.scala:87:24] wire out_womask_996 = &_out_womask_T_996; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_996 = out_rivalid_1_850 & out_rimask_996; // @[RegisterRouter.scala:87:24] wire _out_T_9689 = out_f_rivalid_996; // @[RegisterRouter.scala:87:24] wire out_f_roready_996 = out_roready_1_850 & out_romask_996; // @[RegisterRouter.scala:87:24] wire _out_T_9690 = out_f_roready_996; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_996 = out_wivalid_1_850 & out_wimask_996; // @[RegisterRouter.scala:87:24] wire out_f_woready_996 = out_woready_1_850 & out_womask_996; // @[RegisterRouter.scala:87:24] wire _out_T_9691 = ~out_rimask_996; // @[RegisterRouter.scala:87:24] wire _out_T_9692 = ~out_wimask_996; // @[RegisterRouter.scala:87:24] wire _out_T_9693 = ~out_romask_996; // @[RegisterRouter.scala:87:24] wire _out_T_9694 = ~out_womask_996; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_852 = {hi_144, flags_0_go, _out_prepend_T_852}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9695 = out_prepend_852; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9696 = _out_T_9695; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_145 = _out_T_9696; // @[MuxLiteral.scala:49:48] wire out_rimask_997 = \|_out_rimask_T_997; // @[RegisterRouter.scala:87:24] wire out_wimask_997 = &_out_wimask_T_997; // @[RegisterRouter.scala:87:24] wire out_romask_997 = \|_out_romask_T_997; // @[RegisterRouter.scala:87:24] wire out_womask_997 = &_out_womask_T_997; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_997 = out_rivalid_1_851 & out_rimask_997; // @[RegisterRouter.scala:87:24] wire _out_T_9698 = out_f_rivalid_997; // @[RegisterRouter.scala:87:24] wire out_f_roready_997 = out_roready_1_851 & out_romask_997; // @[RegisterRouter.scala:87:24] wire _out_T_9699 = out_f_roready_997; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_997 = out_wivalid_1_851 & out_wimask_997; // @[RegisterRouter.scala:87:24] wire out_f_woready_997 = out_woready_1_851 & out_womask_997; // @[RegisterRouter.scala:87:24] wire _out_T_9700 = ~out_rimask_997; // @[RegisterRouter.scala:87:24] wire _out_T_9701 = ~out_wimask_997; // @[RegisterRouter.scala:87:24] wire _out_T_9702 = ~out_romask_997; // @[RegisterRouter.scala:87:24] wire _out_T_9703 = ~out_womask_997; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9705 = _out_T_9704; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_853 = _out_T_9705; // @[RegisterRouter.scala:87:24] wire out_rimask_998 = \|_out_rimask_T_998; // @[RegisterRouter.scala:87:24] wire out_wimask_998 = &_out_wimask_T_998; // @[RegisterRouter.scala:87:24] wire out_romask_998 = \|_out_romask_T_998; // @[RegisterRouter.scala:87:24] wire out_womask_998 = &_out_womask_T_998; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_998 = out_rivalid_1_852 & out_rimask_998; // @[RegisterRouter.scala:87:24] wire _out_T_9707 = out_f_rivalid_998; // @[RegisterRouter.scala:87:24] wire out_f_roready_998 = out_roready_1_852 & out_romask_998; // @[RegisterRouter.scala:87:24] wire _out_T_9708 = out_f_roready_998; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_998 = out_wivalid_1_852 & out_wimask_998; // @[RegisterRouter.scala:87:24] wire out_f_woready_998 = out_woready_1_852 & out_womask_998; // @[RegisterRouter.scala:87:24] wire _out_T_9709 = ~out_rimask_998; // @[RegisterRouter.scala:87:24] wire _out_T_9710 = ~out_wimask_998; // @[RegisterRouter.scala:87:24] wire _out_T_9711 = ~out_romask_998; // @[RegisterRouter.scala:87:24] wire _out_T_9712 = ~out_womask_998; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_853 = {hi_178, flags_0_go, _out_prepend_T_853}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9713 = out_prepend_853; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9714 = _out_T_9713; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_854 = _out_T_9714; // @[RegisterRouter.scala:87:24] wire out_rimask_999 = \|_out_rimask_T_999; // @[RegisterRouter.scala:87:24] wire out_wimask_999 = &_out_wimask_T_999; // @[RegisterRouter.scala:87:24] wire out_romask_999 = \|_out_romask_T_999; // @[RegisterRouter.scala:87:24] wire out_womask_999 = &_out_womask_T_999; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_999 = out_rivalid_1_853 & out_rimask_999; // @[RegisterRouter.scala:87:24] wire _out_T_9716 = out_f_rivalid_999; // @[RegisterRouter.scala:87:24] wire out_f_roready_999 = out_roready_1_853 & out_romask_999; // @[RegisterRouter.scala:87:24] wire _out_T_9717 = out_f_roready_999; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_999 = out_wivalid_1_853 & out_wimask_999; // @[RegisterRouter.scala:87:24] wire out_f_woready_999 = out_woready_1_853 & out_womask_999; // @[RegisterRouter.scala:87:24] wire _out_T_9718 = ~out_rimask_999; // @[RegisterRouter.scala:87:24] wire _out_T_9719 = ~out_wimask_999; // @[RegisterRouter.scala:87:24] wire _out_T_9720 = ~out_romask_999; // @[RegisterRouter.scala:87:24] wire _out_T_9721 = ~out_womask_999; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_854 = {hi_179, flags_0_go, _out_prepend_T_854}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9722 = out_prepend_854; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9723 = _out_T_9722; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_855 = _out_T_9723; // @[RegisterRouter.scala:87:24] wire out_rimask_1000 = \|_out_rimask_T_1000; // @[RegisterRouter.scala:87:24] wire out_wimask_1000 = &_out_wimask_T_1000; // @[RegisterRouter.scala:87:24] wire out_romask_1000 = \|_out_romask_T_1000; // @[RegisterRouter.scala:87:24] wire out_womask_1000 = &_out_womask_T_1000; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1000 = out_rivalid_1_854 & out_rimask_1000; // @[RegisterRouter.scala:87:24] wire _out_T_9725 = out_f_rivalid_1000; // @[RegisterRouter.scala:87:24] wire out_f_roready_1000 = out_roready_1_854 & out_romask_1000; // @[RegisterRouter.scala:87:24] wire _out_T_9726 = out_f_roready_1000; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1000 = out_wivalid_1_854 & out_wimask_1000; // @[RegisterRouter.scala:87:24] wire out_f_woready_1000 = out_woready_1_854 & out_womask_1000; // @[RegisterRouter.scala:87:24] wire _out_T_9727 = ~out_rimask_1000; // @[RegisterRouter.scala:87:24] wire _out_T_9728 = ~out_wimask_1000; // @[RegisterRouter.scala:87:24] wire _out_T_9729 = ~out_romask_1000; // @[RegisterRouter.scala:87:24] wire _out_T_9730 = ~out_womask_1000; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_855 = {hi_180, flags_0_go, _out_prepend_T_855}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9731 = out_prepend_855; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9732 = _out_T_9731; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_856 = _out_T_9732; // @[RegisterRouter.scala:87:24] wire out_rimask_1001 = \|_out_rimask_T_1001; // @[RegisterRouter.scala:87:24] wire out_wimask_1001 = &_out_wimask_T_1001; // @[RegisterRouter.scala:87:24] wire out_romask_1001 = \|_out_romask_T_1001; // @[RegisterRouter.scala:87:24] wire out_womask_1001 = &_out_womask_T_1001; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1001 = out_rivalid_1_855 & out_rimask_1001; // @[RegisterRouter.scala:87:24] wire _out_T_9734 = out_f_rivalid_1001; // @[RegisterRouter.scala:87:24] wire out_f_roready_1001 = out_roready_1_855 & out_romask_1001; // @[RegisterRouter.scala:87:24] wire _out_T_9735 = out_f_roready_1001; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1001 = out_wivalid_1_855 & out_wimask_1001; // @[RegisterRouter.scala:87:24] wire out_f_woready_1001 = out_woready_1_855 & out_womask_1001; // @[RegisterRouter.scala:87:24] wire _out_T_9736 = ~out_rimask_1001; // @[RegisterRouter.scala:87:24] wire _out_T_9737 = ~out_wimask_1001; // @[RegisterRouter.scala:87:24] wire _out_T_9738 = ~out_romask_1001; // @[RegisterRouter.scala:87:24] wire _out_T_9739 = ~out_womask_1001; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_856 = {hi_181, flags_0_go, _out_prepend_T_856}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9740 = out_prepend_856; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9741 = _out_T_9740; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_857 = _out_T_9741; // @[RegisterRouter.scala:87:24] wire out_rimask_1002 = \|_out_rimask_T_1002; // @[RegisterRouter.scala:87:24] wire out_wimask_1002 = &_out_wimask_T_1002; // @[RegisterRouter.scala:87:24] wire out_romask_1002 = \|_out_romask_T_1002; // @[RegisterRouter.scala:87:24] wire out_womask_1002 = &_out_womask_T_1002; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1002 = out_rivalid_1_856 & out_rimask_1002; // @[RegisterRouter.scala:87:24] wire _out_T_9743 = out_f_rivalid_1002; // @[RegisterRouter.scala:87:24] wire out_f_roready_1002 = out_roready_1_856 & out_romask_1002; // @[RegisterRouter.scala:87:24] wire _out_T_9744 = out_f_roready_1002; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1002 = out_wivalid_1_856 & out_wimask_1002; // @[RegisterRouter.scala:87:24] wire out_f_woready_1002 = out_woready_1_856 & out_womask_1002; // @[RegisterRouter.scala:87:24] wire _out_T_9745 = ~out_rimask_1002; // @[RegisterRouter.scala:87:24] wire _out_T_9746 = ~out_wimask_1002; // @[RegisterRouter.scala:87:24] wire _out_T_9747 = ~out_romask_1002; // @[RegisterRouter.scala:87:24] wire _out_T_9748 = ~out_womask_1002; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_857 = {hi_182, flags_0_go, _out_prepend_T_857}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9749 = out_prepend_857; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9750 = _out_T_9749; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_858 = _out_T_9750; // @[RegisterRouter.scala:87:24] wire out_rimask_1003 = \|_out_rimask_T_1003; // @[RegisterRouter.scala:87:24] wire out_wimask_1003 = &_out_wimask_T_1003; // @[RegisterRouter.scala:87:24] wire out_romask_1003 = \|_out_romask_T_1003; // @[RegisterRouter.scala:87:24] wire out_womask_1003 = &_out_womask_T_1003; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1003 = out_rivalid_1_857 & out_rimask_1003; // @[RegisterRouter.scala:87:24] wire _out_T_9752 = out_f_rivalid_1003; // @[RegisterRouter.scala:87:24] wire out_f_roready_1003 = out_roready_1_857 & out_romask_1003; // @[RegisterRouter.scala:87:24] wire _out_T_9753 = out_f_roready_1003; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1003 = out_wivalid_1_857 & out_wimask_1003; // @[RegisterRouter.scala:87:24] wire out_f_woready_1003 = out_woready_1_857 & out_womask_1003; // @[RegisterRouter.scala:87:24] wire _out_T_9754 = ~out_rimask_1003; // @[RegisterRouter.scala:87:24] wire _out_T_9755 = ~out_wimask_1003; // @[RegisterRouter.scala:87:24] wire _out_T_9756 = ~out_romask_1003; // @[RegisterRouter.scala:87:24] wire _out_T_9757 = ~out_womask_1003; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_858 = {hi_183, flags_0_go, _out_prepend_T_858}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9758 = out_prepend_858; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9759 = _out_T_9758; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_859 = _out_T_9759; // @[RegisterRouter.scala:87:24] wire out_rimask_1004 = \|_out_rimask_T_1004; // @[RegisterRouter.scala:87:24] wire out_wimask_1004 = &_out_wimask_T_1004; // @[RegisterRouter.scala:87:24] wire out_romask_1004 = \|_out_romask_T_1004; // @[RegisterRouter.scala:87:24] wire out_womask_1004 = &_out_womask_T_1004; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1004 = out_rivalid_1_858 & out_rimask_1004; // @[RegisterRouter.scala:87:24] wire _out_T_9761 = out_f_rivalid_1004; // @[RegisterRouter.scala:87:24] wire out_f_roready_1004 = out_roready_1_858 & out_romask_1004; // @[RegisterRouter.scala:87:24] wire _out_T_9762 = out_f_roready_1004; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1004 = out_wivalid_1_858 & out_wimask_1004; // @[RegisterRouter.scala:87:24] wire out_f_woready_1004 = out_woready_1_858 & out_womask_1004; // @[RegisterRouter.scala:87:24] wire _out_T_9763 = ~out_rimask_1004; // @[RegisterRouter.scala:87:24] wire _out_T_9764 = ~out_wimask_1004; // @[RegisterRouter.scala:87:24] wire _out_T_9765 = ~out_romask_1004; // @[RegisterRouter.scala:87:24] wire _out_T_9766 = ~out_womask_1004; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_859 = {hi_184, flags_0_go, _out_prepend_T_859}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9767 = out_prepend_859; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9768 = _out_T_9767; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_150 = _out_T_9768; // @[MuxLiteral.scala:49:48] wire out_rimask_1005 = \|_out_rimask_T_1005; // @[RegisterRouter.scala:87:24] wire out_wimask_1005 = &_out_wimask_T_1005; // @[RegisterRouter.scala:87:24] wire out_romask_1005 = \|_out_romask_T_1005; // @[RegisterRouter.scala:87:24] wire out_womask_1005 = &_out_womask_T_1005; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1005 = out_rivalid_1_859 & out_rimask_1005; // @[RegisterRouter.scala:87:24] wire _out_T_9770 = out_f_rivalid_1005; // @[RegisterRouter.scala:87:24] wire out_f_roready_1005 = out_roready_1_859 & out_romask_1005; // @[RegisterRouter.scala:87:24] wire _out_T_9771 = out_f_roready_1005; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1005 = out_wivalid_1_859 & out_wimask_1005; // @[RegisterRouter.scala:87:24] wire out_f_woready_1005 = out_woready_1_859 & out_womask_1005; // @[RegisterRouter.scala:87:24] wire _out_T_9772 = ~out_rimask_1005; // @[RegisterRouter.scala:87:24] wire _out_T_9773 = ~out_wimask_1005; // @[RegisterRouter.scala:87:24] wire _out_T_9774 = ~out_romask_1005; // @[RegisterRouter.scala:87:24] wire _out_T_9775 = ~out_womask_1005; // @[RegisterRouter.scala:87:24] wire out_rimask_1006 = \|_out_rimask_T_1006; // @[RegisterRouter.scala:87:24] wire out_wimask_1006 = &_out_wimask_T_1006; // @[RegisterRouter.scala:87:24] wire out_romask_1006 = \|_out_romask_T_1006; // @[RegisterRouter.scala:87:24] wire out_womask_1006 = &_out_womask_T_1006; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1006 = out_rivalid_1_860 & out_rimask_1006; // @[RegisterRouter.scala:87:24] wire _out_T_9779 = out_f_rivalid_1006; // @[RegisterRouter.scala:87:24] wire out_f_roready_1006 = out_roready_1_860 & out_romask_1006; // @[RegisterRouter.scala:87:24] wire _out_T_9780 = out_f_roready_1006; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1006 = out_wivalid_1_860 & out_wimask_1006; // @[RegisterRouter.scala:87:24] wire out_f_woready_1006 = out_woready_1_860 & out_womask_1006; // @[RegisterRouter.scala:87:24] wire _out_T_9781 = ~out_rimask_1006; // @[RegisterRouter.scala:87:24] wire _out_T_9782 = ~out_wimask_1006; // @[RegisterRouter.scala:87:24] wire _out_T_9783 = ~out_romask_1006; // @[RegisterRouter.scala:87:24] wire _out_T_9784 = ~out_womask_1006; // @[RegisterRouter.scala:87:24] wire out_rimask_1007 = \|_out_rimask_T_1007; // @[RegisterRouter.scala:87:24] wire out_wimask_1007 = &_out_wimask_T_1007; // @[RegisterRouter.scala:87:24] wire out_romask_1007 = \|_out_romask_T_1007; // @[RegisterRouter.scala:87:24] wire out_womask_1007 = &_out_womask_T_1007; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1007 = out_rivalid_1_861 & out_rimask_1007; // @[RegisterRouter.scala:87:24] wire _out_T_9788 = out_f_rivalid_1007; // @[RegisterRouter.scala:87:24] wire out_f_roready_1007 = out_roready_1_861 & out_romask_1007; // @[RegisterRouter.scala:87:24] wire _out_T_9789 = out_f_roready_1007; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1007 = out_wivalid_1_861 & out_wimask_1007; // @[RegisterRouter.scala:87:24] wire out_f_woready_1007 = out_woready_1_861 & out_womask_1007; // @[RegisterRouter.scala:87:24] wire _out_T_9790 = ~out_rimask_1007; // @[RegisterRouter.scala:87:24] wire _out_T_9791 = ~out_wimask_1007; // @[RegisterRouter.scala:87:24] wire _out_T_9792 = ~out_romask_1007; // @[RegisterRouter.scala:87:24] wire _out_T_9793 = ~out_womask_1007; // @[RegisterRouter.scala:87:24] wire out_rimask_1008 = \|_out_rimask_T_1008; // @[RegisterRouter.scala:87:24] wire out_wimask_1008 = &_out_wimask_T_1008; // @[RegisterRouter.scala:87:24] wire out_romask_1008 = \|_out_romask_T_1008; // @[RegisterRouter.scala:87:24] wire out_womask_1008 = &_out_womask_T_1008; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1008 = out_rivalid_1_862 & out_rimask_1008; // @[RegisterRouter.scala:87:24] wire _out_T_9797 = out_f_rivalid_1008; // @[RegisterRouter.scala:87:24] wire out_f_roready_1008 = out_roready_1_862 & out_romask_1008; // @[RegisterRouter.scala:87:24] wire _out_T_9798 = out_f_roready_1008; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1008 = out_wivalid_1_862 & out_wimask_1008; // @[RegisterRouter.scala:87:24] wire out_f_woready_1008 = out_woready_1_862 & out_womask_1008; // @[RegisterRouter.scala:87:24] wire _out_T_9799 = ~out_rimask_1008; // @[RegisterRouter.scala:87:24] wire _out_T_9800 = ~out_wimask_1008; // @[RegisterRouter.scala:87:24] wire _out_T_9801 = ~out_romask_1008; // @[RegisterRouter.scala:87:24] wire _out_T_9802 = ~out_womask_1008; // @[RegisterRouter.scala:87:24] wire out_rimask_1009 = \|_out_rimask_T_1009; // @[RegisterRouter.scala:87:24] wire out_wimask_1009 = &_out_wimask_T_1009; // @[RegisterRouter.scala:87:24] wire out_romask_1009 = \|_out_romask_T_1009; // @[RegisterRouter.scala:87:24] wire out_womask_1009 = &_out_womask_T_1009; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1009 = out_rivalid_1_863 & out_rimask_1009; // @[RegisterRouter.scala:87:24] wire _out_T_9806 = out_f_rivalid_1009; // @[RegisterRouter.scala:87:24] wire out_f_roready_1009 = out_roready_1_863 & out_romask_1009; // @[RegisterRouter.scala:87:24] wire _out_T_9807 = out_f_roready_1009; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1009 = out_wivalid_1_863 & out_wimask_1009; // @[RegisterRouter.scala:87:24] wire out_f_woready_1009 = out_woready_1_863 & out_womask_1009; // @[RegisterRouter.scala:87:24] wire _out_T_9808 = ~out_rimask_1009; // @[RegisterRouter.scala:87:24] wire _out_T_9809 = ~out_wimask_1009; // @[RegisterRouter.scala:87:24] wire _out_T_9810 = ~out_romask_1009; // @[RegisterRouter.scala:87:24] wire _out_T_9811 = ~out_womask_1009; // @[RegisterRouter.scala:87:24] wire out_rimask_1010 = \|_out_rimask_T_1010; // @[RegisterRouter.scala:87:24] wire out_wimask_1010 = &_out_wimask_T_1010; // @[RegisterRouter.scala:87:24] wire out_romask_1010 = \|_out_romask_T_1010; // @[RegisterRouter.scala:87:24] wire out_womask_1010 = &_out_womask_T_1010; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1010 = out_rivalid_1_864 & out_rimask_1010; // @[RegisterRouter.scala:87:24] wire _out_T_9815 = out_f_rivalid_1010; // @[RegisterRouter.scala:87:24] wire out_f_roready_1010 = out_roready_1_864 & out_romask_1010; // @[RegisterRouter.scala:87:24] wire _out_T_9816 = out_f_roready_1010; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1010 = out_wivalid_1_864 & out_wimask_1010; // @[RegisterRouter.scala:87:24] wire out_f_woready_1010 = out_woready_1_864 & out_womask_1010; // @[RegisterRouter.scala:87:24] wire _out_T_9817 = ~out_rimask_1010; // @[RegisterRouter.scala:87:24] wire _out_T_9818 = ~out_wimask_1010; // @[RegisterRouter.scala:87:24] wire _out_T_9819 = ~out_romask_1010; // @[RegisterRouter.scala:87:24] wire _out_T_9820 = ~out_womask_1010; // @[RegisterRouter.scala:87:24] wire out_rimask_1011 = \|_out_rimask_T_1011; // @[RegisterRouter.scala:87:24] wire out_wimask_1011 = &_out_wimask_T_1011; // @[RegisterRouter.scala:87:24] wire out_romask_1011 = \|_out_romask_T_1011; // @[RegisterRouter.scala:87:24] wire out_womask_1011 = &_out_womask_T_1011; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1011 = out_rivalid_1_865 & out_rimask_1011; // @[RegisterRouter.scala:87:24] wire _out_T_9824 = out_f_rivalid_1011; // @[RegisterRouter.scala:87:24] wire out_f_roready_1011 = out_roready_1_865 & out_romask_1011; // @[RegisterRouter.scala:87:24] wire _out_T_9825 = out_f_roready_1011; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1011 = out_wivalid_1_865 & out_wimask_1011; // @[RegisterRouter.scala:87:24] wire out_f_woready_1011 = out_woready_1_865 & out_womask_1011; // @[RegisterRouter.scala:87:24] wire _out_T_9826 = ~out_rimask_1011; // @[RegisterRouter.scala:87:24] wire _out_T_9827 = ~out_wimask_1011; // @[RegisterRouter.scala:87:24] wire _out_T_9828 = ~out_romask_1011; // @[RegisterRouter.scala:87:24] wire _out_T_9829 = ~out_womask_1011; // @[RegisterRouter.scala:87:24] wire out_rimask_1012 = \|_out_rimask_T_1012; // @[RegisterRouter.scala:87:24] wire out_wimask_1012 = &_out_wimask_T_1012; // @[RegisterRouter.scala:87:24] wire out_romask_1012 = \|_out_romask_T_1012; // @[RegisterRouter.scala:87:24] wire out_womask_1012 = &_out_womask_T_1012; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1012 = out_rivalid_1_866 & out_rimask_1012; // @[RegisterRouter.scala:87:24] wire _out_T_9833 = out_f_rivalid_1012; // @[RegisterRouter.scala:87:24] wire out_f_roready_1012 = out_roready_1_866 & out_romask_1012; // @[RegisterRouter.scala:87:24] wire _out_T_9834 = out_f_roready_1012; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1012 = out_wivalid_1_866 & out_wimask_1012; // @[RegisterRouter.scala:87:24] wire out_f_woready_1012 = out_woready_1_866 & out_womask_1012; // @[RegisterRouter.scala:87:24] wire _out_T_9835 = ~out_rimask_1012; // @[RegisterRouter.scala:87:24] wire _out_T_9836 = ~out_wimask_1012; // @[RegisterRouter.scala:87:24] wire _out_T_9837 = ~out_romask_1012; // @[RegisterRouter.scala:87:24] wire _out_T_9838 = ~out_womask_1012; // @[RegisterRouter.scala:87:24] wire out_rimask_1013 = \|_out_rimask_T_1013; // @[RegisterRouter.scala:87:24] wire out_wimask_1013 = &_out_wimask_T_1013; // @[RegisterRouter.scala:87:24] wire out_romask_1013 = \|_out_romask_T_1013; // @[RegisterRouter.scala:87:24] wire out_womask_1013 = &_out_womask_T_1013; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1013 = out_rivalid_1_867 & out_rimask_1013; // @[RegisterRouter.scala:87:24] wire _out_T_9842 = out_f_rivalid_1013; // @[RegisterRouter.scala:87:24] wire out_f_roready_1013 = out_roready_1_867 & out_romask_1013; // @[RegisterRouter.scala:87:24] wire _out_T_9843 = out_f_roready_1013; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1013 = out_wivalid_1_867 & out_wimask_1013; // @[RegisterRouter.scala:87:24] wire out_f_woready_1013 = out_woready_1_867 & out_womask_1013; // @[RegisterRouter.scala:87:24] wire _out_T_9844 = ~out_rimask_1013; // @[RegisterRouter.scala:87:24] wire _out_T_9845 = ~out_wimask_1013; // @[RegisterRouter.scala:87:24] wire _out_T_9846 = ~out_romask_1013; // @[RegisterRouter.scala:87:24] wire _out_T_9847 = ~out_womask_1013; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9849 = _out_T_9848; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_867 = _out_T_9849; // @[RegisterRouter.scala:87:24] wire out_rimask_1014 = \|_out_rimask_T_1014; // @[RegisterRouter.scala:87:24] wire out_wimask_1014 = &_out_wimask_T_1014; // @[RegisterRouter.scala:87:24] wire out_romask_1014 = \|_out_romask_T_1014; // @[RegisterRouter.scala:87:24] wire out_womask_1014 = &_out_womask_T_1014; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1014 = out_rivalid_1_868 & out_rimask_1014; // @[RegisterRouter.scala:87:24] wire _out_T_9851 = out_f_rivalid_1014; // @[RegisterRouter.scala:87:24] wire out_f_roready_1014 = out_roready_1_868 & out_romask_1014; // @[RegisterRouter.scala:87:24] wire _out_T_9852 = out_f_roready_1014; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1014 = out_wivalid_1_868 & out_wimask_1014; // @[RegisterRouter.scala:87:24] wire out_f_woready_1014 = out_woready_1_868 & out_womask_1014; // @[RegisterRouter.scala:87:24] wire _out_T_9853 = ~out_rimask_1014; // @[RegisterRouter.scala:87:24] wire _out_T_9854 = ~out_wimask_1014; // @[RegisterRouter.scala:87:24] wire _out_T_9855 = ~out_romask_1014; // @[RegisterRouter.scala:87:24] wire _out_T_9856 = ~out_womask_1014; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_867 = {hi_570, flags_0_go, _out_prepend_T_867}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9857 = out_prepend_867; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9858 = _out_T_9857; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_868 = _out_T_9858; // @[RegisterRouter.scala:87:24] wire out_rimask_1015 = \|_out_rimask_T_1015; // @[RegisterRouter.scala:87:24] wire out_wimask_1015 = &_out_wimask_T_1015; // @[RegisterRouter.scala:87:24] wire out_romask_1015 = \|_out_romask_T_1015; // @[RegisterRouter.scala:87:24] wire out_womask_1015 = &_out_womask_T_1015; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1015 = out_rivalid_1_869 & out_rimask_1015; // @[RegisterRouter.scala:87:24] wire _out_T_9860 = out_f_rivalid_1015; // @[RegisterRouter.scala:87:24] wire out_f_roready_1015 = out_roready_1_869 & out_romask_1015; // @[RegisterRouter.scala:87:24] wire _out_T_9861 = out_f_roready_1015; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1015 = out_wivalid_1_869 & out_wimask_1015; // @[RegisterRouter.scala:87:24] wire out_f_woready_1015 = out_woready_1_869 & out_womask_1015; // @[RegisterRouter.scala:87:24] wire _out_T_9862 = ~out_rimask_1015; // @[RegisterRouter.scala:87:24] wire _out_T_9863 = ~out_wimask_1015; // @[RegisterRouter.scala:87:24] wire _out_T_9864 = ~out_romask_1015; // @[RegisterRouter.scala:87:24] wire _out_T_9865 = ~out_womask_1015; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_868 = {hi_571, flags_0_go, _out_prepend_T_868}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9866 = out_prepend_868; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9867 = _out_T_9866; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_869 = _out_T_9867; // @[RegisterRouter.scala:87:24] wire out_rimask_1016 = \|_out_rimask_T_1016; // @[RegisterRouter.scala:87:24] wire out_wimask_1016 = &_out_wimask_T_1016; // @[RegisterRouter.scala:87:24] wire out_romask_1016 = \|_out_romask_T_1016; // @[RegisterRouter.scala:87:24] wire out_womask_1016 = &_out_womask_T_1016; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1016 = out_rivalid_1_870 & out_rimask_1016; // @[RegisterRouter.scala:87:24] wire _out_T_9869 = out_f_rivalid_1016; // @[RegisterRouter.scala:87:24] wire out_f_roready_1016 = out_roready_1_870 & out_romask_1016; // @[RegisterRouter.scala:87:24] wire _out_T_9870 = out_f_roready_1016; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1016 = out_wivalid_1_870 & out_wimask_1016; // @[RegisterRouter.scala:87:24] wire out_f_woready_1016 = out_woready_1_870 & out_womask_1016; // @[RegisterRouter.scala:87:24] wire _out_T_9871 = ~out_rimask_1016; // @[RegisterRouter.scala:87:24] wire _out_T_9872 = ~out_wimask_1016; // @[RegisterRouter.scala:87:24] wire _out_T_9873 = ~out_romask_1016; // @[RegisterRouter.scala:87:24] wire _out_T_9874 = ~out_womask_1016; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_869 = {hi_572, flags_0_go, _out_prepend_T_869}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9875 = out_prepend_869; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9876 = _out_T_9875; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_870 = _out_T_9876; // @[RegisterRouter.scala:87:24] wire out_rimask_1017 = \|_out_rimask_T_1017; // @[RegisterRouter.scala:87:24] wire out_wimask_1017 = &_out_wimask_T_1017; // @[RegisterRouter.scala:87:24] wire out_romask_1017 = \|_out_romask_T_1017; // @[RegisterRouter.scala:87:24] wire out_womask_1017 = &_out_womask_T_1017; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1017 = out_rivalid_1_871 & out_rimask_1017; // @[RegisterRouter.scala:87:24] wire _out_T_9878 = out_f_rivalid_1017; // @[RegisterRouter.scala:87:24] wire out_f_roready_1017 = out_roready_1_871 & out_romask_1017; // @[RegisterRouter.scala:87:24] wire _out_T_9879 = out_f_roready_1017; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1017 = out_wivalid_1_871 & out_wimask_1017; // @[RegisterRouter.scala:87:24] wire out_f_woready_1017 = out_woready_1_871 & out_womask_1017; // @[RegisterRouter.scala:87:24] wire _out_T_9880 = ~out_rimask_1017; // @[RegisterRouter.scala:87:24] wire _out_T_9881 = ~out_wimask_1017; // @[RegisterRouter.scala:87:24] wire _out_T_9882 = ~out_romask_1017; // @[RegisterRouter.scala:87:24] wire _out_T_9883 = ~out_womask_1017; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_870 = {hi_573, flags_0_go, _out_prepend_T_870}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9884 = out_prepend_870; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9885 = _out_T_9884; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_871 = _out_T_9885; // @[RegisterRouter.scala:87:24] wire out_rimask_1018 = \|_out_rimask_T_1018; // @[RegisterRouter.scala:87:24] wire out_wimask_1018 = &_out_wimask_T_1018; // @[RegisterRouter.scala:87:24] wire out_romask_1018 = \|_out_romask_T_1018; // @[RegisterRouter.scala:87:24] wire out_womask_1018 = &_out_womask_T_1018; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1018 = out_rivalid_1_872 & out_rimask_1018; // @[RegisterRouter.scala:87:24] wire _out_T_9887 = out_f_rivalid_1018; // @[RegisterRouter.scala:87:24] wire out_f_roready_1018 = out_roready_1_872 & out_romask_1018; // @[RegisterRouter.scala:87:24] wire _out_T_9888 = out_f_roready_1018; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1018 = out_wivalid_1_872 & out_wimask_1018; // @[RegisterRouter.scala:87:24] wire out_f_woready_1018 = out_woready_1_872 & out_womask_1018; // @[RegisterRouter.scala:87:24] wire _out_T_9889 = ~out_rimask_1018; // @[RegisterRouter.scala:87:24] wire _out_T_9890 = ~out_wimask_1018; // @[RegisterRouter.scala:87:24] wire _out_T_9891 = ~out_romask_1018; // @[RegisterRouter.scala:87:24] wire _out_T_9892 = ~out_womask_1018; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_871 = {hi_574, flags_0_go, _out_prepend_T_871}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9893 = out_prepend_871; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9894 = _out_T_9893; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_872 = _out_T_9894; // @[RegisterRouter.scala:87:24] wire out_rimask_1019 = \|_out_rimask_T_1019; // @[RegisterRouter.scala:87:24] wire out_wimask_1019 = &_out_wimask_T_1019; // @[RegisterRouter.scala:87:24] wire out_romask_1019 = \|_out_romask_T_1019; // @[RegisterRouter.scala:87:24] wire out_womask_1019 = &_out_womask_T_1019; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1019 = out_rivalid_1_873 & out_rimask_1019; // @[RegisterRouter.scala:87:24] wire _out_T_9896 = out_f_rivalid_1019; // @[RegisterRouter.scala:87:24] wire out_f_roready_1019 = out_roready_1_873 & out_romask_1019; // @[RegisterRouter.scala:87:24] wire _out_T_9897 = out_f_roready_1019; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1019 = out_wivalid_1_873 & out_wimask_1019; // @[RegisterRouter.scala:87:24] wire out_f_woready_1019 = out_woready_1_873 & out_womask_1019; // @[RegisterRouter.scala:87:24] wire _out_T_9898 = ~out_rimask_1019; // @[RegisterRouter.scala:87:24] wire _out_T_9899 = ~out_wimask_1019; // @[RegisterRouter.scala:87:24] wire _out_T_9900 = ~out_romask_1019; // @[RegisterRouter.scala:87:24] wire _out_T_9901 = ~out_womask_1019; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_872 = {hi_575, flags_0_go, _out_prepend_T_872}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9902 = out_prepend_872; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9903 = _out_T_9902; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_873 = _out_T_9903; // @[RegisterRouter.scala:87:24] wire out_rimask_1020 = \|_out_rimask_T_1020; // @[RegisterRouter.scala:87:24] wire out_wimask_1020 = &_out_wimask_T_1020; // @[RegisterRouter.scala:87:24] wire out_romask_1020 = \|_out_romask_T_1020; // @[RegisterRouter.scala:87:24] wire out_womask_1020 = &_out_womask_T_1020; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1020 = out_rivalid_1_874 & out_rimask_1020; // @[RegisterRouter.scala:87:24] wire _out_T_9905 = out_f_rivalid_1020; // @[RegisterRouter.scala:87:24] wire out_f_roready_1020 = out_roready_1_874 & out_romask_1020; // @[RegisterRouter.scala:87:24] wire _out_T_9906 = out_f_roready_1020; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1020 = out_wivalid_1_874 & out_wimask_1020; // @[RegisterRouter.scala:87:24] wire out_f_woready_1020 = out_woready_1_874 & out_womask_1020; // @[RegisterRouter.scala:87:24] wire _out_T_9907 = ~out_rimask_1020; // @[RegisterRouter.scala:87:24] wire _out_T_9908 = ~out_wimask_1020; // @[RegisterRouter.scala:87:24] wire _out_T_9909 = ~out_romask_1020; // @[RegisterRouter.scala:87:24] wire _out_T_9910 = ~out_womask_1020; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_873 = {hi_576, flags_0_go, _out_prepend_T_873}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9911 = out_prepend_873; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9912 = _out_T_9911; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_199 = _out_T_9912; // @[MuxLiteral.scala:49:48] wire out_rimask_1021 = \|_out_rimask_T_1021; // @[RegisterRouter.scala:87:24] wire out_wimask_1021 = &_out_wimask_T_1021; // @[RegisterRouter.scala:87:24] wire out_romask_1021 = \|_out_romask_T_1021; // @[RegisterRouter.scala:87:24] wire out_womask_1021 = &_out_womask_T_1021; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1021 = out_rivalid_1_875 & out_rimask_1021; // @[RegisterRouter.scala:87:24] wire _out_T_9914 = out_f_rivalid_1021; // @[RegisterRouter.scala:87:24] wire out_f_roready_1021 = out_roready_1_875 & out_romask_1021; // @[RegisterRouter.scala:87:24] wire _out_T_9915 = out_f_roready_1021; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1021 = out_wivalid_1_875 & out_wimask_1021; // @[RegisterRouter.scala:87:24] wire out_f_woready_1021 = out_woready_1_875 & out_womask_1021; // @[RegisterRouter.scala:87:24] wire _out_T_9916 = ~out_rimask_1021; // @[RegisterRouter.scala:87:24] wire _out_T_9917 = ~out_wimask_1021; // @[RegisterRouter.scala:87:24] wire _out_T_9918 = ~out_romask_1021; // @[RegisterRouter.scala:87:24] wire _out_T_9919 = ~out_womask_1021; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9921 = _out_T_9920; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_874 = _out_T_9921; // @[RegisterRouter.scala:87:24] wire out_rimask_1022 = \|_out_rimask_T_1022; // @[RegisterRouter.scala:87:24] wire out_wimask_1022 = &_out_wimask_T_1022; // @[RegisterRouter.scala:87:24] wire out_romask_1022 = \|_out_romask_T_1022; // @[RegisterRouter.scala:87:24] wire out_womask_1022 = &_out_womask_T_1022; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1022 = out_rivalid_1_876 & out_rimask_1022; // @[RegisterRouter.scala:87:24] wire _out_T_9923 = out_f_rivalid_1022; // @[RegisterRouter.scala:87:24] wire out_f_roready_1022 = out_roready_1_876 & out_romask_1022; // @[RegisterRouter.scala:87:24] wire _out_T_9924 = out_f_roready_1022; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1022 = out_wivalid_1_876 & out_wimask_1022; // @[RegisterRouter.scala:87:24] wire out_f_woready_1022 = out_woready_1_876 & out_womask_1022; // @[RegisterRouter.scala:87:24] wire _out_T_9925 = ~out_rimask_1022; // @[RegisterRouter.scala:87:24] wire _out_T_9926 = ~out_wimask_1022; // @[RegisterRouter.scala:87:24] wire _out_T_9927 = ~out_romask_1022; // @[RegisterRouter.scala:87:24] wire _out_T_9928 = ~out_womask_1022; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_874 = {hi_394, flags_0_go, _out_prepend_T_874}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9929 = out_prepend_874; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9930 = _out_T_9929; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_875 = _out_T_9930; // @[RegisterRouter.scala:87:24] wire out_rimask_1023 = \|_out_rimask_T_1023; // @[RegisterRouter.scala:87:24] wire out_wimask_1023 = &_out_wimask_T_1023; // @[RegisterRouter.scala:87:24] wire out_romask_1023 = \|_out_romask_T_1023; // @[RegisterRouter.scala:87:24] wire out_womask_1023 = &_out_womask_T_1023; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1023 = out_rivalid_1_877 & out_rimask_1023; // @[RegisterRouter.scala:87:24] wire _out_T_9932 = out_f_rivalid_1023; // @[RegisterRouter.scala:87:24] wire out_f_roready_1023 = out_roready_1_877 & out_romask_1023; // @[RegisterRouter.scala:87:24] wire _out_T_9933 = out_f_roready_1023; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1023 = out_wivalid_1_877 & out_wimask_1023; // @[RegisterRouter.scala:87:24] wire out_f_woready_1023 = out_woready_1_877 & out_womask_1023; // @[RegisterRouter.scala:87:24] wire _out_T_9934 = ~out_rimask_1023; // @[RegisterRouter.scala:87:24] wire _out_T_9935 = ~out_wimask_1023; // @[RegisterRouter.scala:87:24] wire _out_T_9936 = ~out_romask_1023; // @[RegisterRouter.scala:87:24] wire _out_T_9937 = ~out_womask_1023; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_875 = {hi_395, flags_0_go, _out_prepend_T_875}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9938 = out_prepend_875; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9939 = _out_T_9938; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_876 = _out_T_9939; // @[RegisterRouter.scala:87:24] wire out_rimask_1024 = \|_out_rimask_T_1024; // @[RegisterRouter.scala:87:24] wire out_wimask_1024 = &_out_wimask_T_1024; // @[RegisterRouter.scala:87:24] wire out_romask_1024 = \|_out_romask_T_1024; // @[RegisterRouter.scala:87:24] wire out_womask_1024 = &_out_womask_T_1024; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1024 = out_rivalid_1_878 & out_rimask_1024; // @[RegisterRouter.scala:87:24] wire _out_T_9941 = out_f_rivalid_1024; // @[RegisterRouter.scala:87:24] wire out_f_roready_1024 = out_roready_1_878 & out_romask_1024; // @[RegisterRouter.scala:87:24] wire _out_T_9942 = out_f_roready_1024; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1024 = out_wivalid_1_878 & out_wimask_1024; // @[RegisterRouter.scala:87:24] wire out_f_woready_1024 = out_woready_1_878 & out_womask_1024; // @[RegisterRouter.scala:87:24] wire _out_T_9943 = ~out_rimask_1024; // @[RegisterRouter.scala:87:24] wire _out_T_9944 = ~out_wimask_1024; // @[RegisterRouter.scala:87:24] wire _out_T_9945 = ~out_romask_1024; // @[RegisterRouter.scala:87:24] wire _out_T_9946 = ~out_womask_1024; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_876 = {hi_396, flags_0_go, _out_prepend_T_876}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9947 = out_prepend_876; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9948 = _out_T_9947; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_877 = _out_T_9948; // @[RegisterRouter.scala:87:24] wire out_rimask_1025 = \|_out_rimask_T_1025; // @[RegisterRouter.scala:87:24] wire out_wimask_1025 = &_out_wimask_T_1025; // @[RegisterRouter.scala:87:24] wire out_romask_1025 = \|_out_romask_T_1025; // @[RegisterRouter.scala:87:24] wire out_womask_1025 = &_out_womask_T_1025; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1025 = out_rivalid_1_879 & out_rimask_1025; // @[RegisterRouter.scala:87:24] wire _out_T_9950 = out_f_rivalid_1025; // @[RegisterRouter.scala:87:24] wire out_f_roready_1025 = out_roready_1_879 & out_romask_1025; // @[RegisterRouter.scala:87:24] wire _out_T_9951 = out_f_roready_1025; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1025 = out_wivalid_1_879 & out_wimask_1025; // @[RegisterRouter.scala:87:24] wire out_f_woready_1025 = out_woready_1_879 & out_womask_1025; // @[RegisterRouter.scala:87:24] wire _out_T_9952 = ~out_rimask_1025; // @[RegisterRouter.scala:87:24] wire _out_T_9953 = ~out_wimask_1025; // @[RegisterRouter.scala:87:24] wire _out_T_9954 = ~out_romask_1025; // @[RegisterRouter.scala:87:24] wire _out_T_9955 = ~out_womask_1025; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_877 = {hi_397, flags_0_go, _out_prepend_T_877}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9956 = out_prepend_877; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9957 = _out_T_9956; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_878 = _out_T_9957; // @[RegisterRouter.scala:87:24] wire out_rimask_1026 = \|_out_rimask_T_1026; // @[RegisterRouter.scala:87:24] wire out_wimask_1026 = &_out_wimask_T_1026; // @[RegisterRouter.scala:87:24] wire out_romask_1026 = \|_out_romask_T_1026; // @[RegisterRouter.scala:87:24] wire out_womask_1026 = &_out_womask_T_1026; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1026 = out_rivalid_1_880 & out_rimask_1026; // @[RegisterRouter.scala:87:24] wire _out_T_9959 = out_f_rivalid_1026; // @[RegisterRouter.scala:87:24] wire out_f_roready_1026 = out_roready_1_880 & out_romask_1026; // @[RegisterRouter.scala:87:24] wire _out_T_9960 = out_f_roready_1026; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1026 = out_wivalid_1_880 & out_wimask_1026; // @[RegisterRouter.scala:87:24] wire out_f_woready_1026 = out_woready_1_880 & out_womask_1026; // @[RegisterRouter.scala:87:24] wire _out_T_9961 = ~out_rimask_1026; // @[RegisterRouter.scala:87:24] wire _out_T_9962 = ~out_wimask_1026; // @[RegisterRouter.scala:87:24] wire _out_T_9963 = ~out_romask_1026; // @[RegisterRouter.scala:87:24] wire _out_T_9964 = ~out_womask_1026; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_878 = {hi_398, flags_0_go, _out_prepend_T_878}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9965 = out_prepend_878; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9966 = _out_T_9965; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_879 = _out_T_9966; // @[RegisterRouter.scala:87:24] wire out_rimask_1027 = \|_out_rimask_T_1027; // @[RegisterRouter.scala:87:24] wire out_wimask_1027 = &_out_wimask_T_1027; // @[RegisterRouter.scala:87:24] wire out_romask_1027 = \|_out_romask_T_1027; // @[RegisterRouter.scala:87:24] wire out_womask_1027 = &_out_womask_T_1027; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1027 = out_rivalid_1_881 & out_rimask_1027; // @[RegisterRouter.scala:87:24] wire _out_T_9968 = out_f_rivalid_1027; // @[RegisterRouter.scala:87:24] wire out_f_roready_1027 = out_roready_1_881 & out_romask_1027; // @[RegisterRouter.scala:87:24] wire _out_T_9969 = out_f_roready_1027; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1027 = out_wivalid_1_881 & out_wimask_1027; // @[RegisterRouter.scala:87:24] wire out_f_woready_1027 = out_woready_1_881 & out_womask_1027; // @[RegisterRouter.scala:87:24] wire _out_T_9970 = ~out_rimask_1027; // @[RegisterRouter.scala:87:24] wire _out_T_9971 = ~out_wimask_1027; // @[RegisterRouter.scala:87:24] wire _out_T_9972 = ~out_romask_1027; // @[RegisterRouter.scala:87:24] wire _out_T_9973 = ~out_womask_1027; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_879 = {hi_399, flags_0_go, _out_prepend_T_879}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9974 = out_prepend_879; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9975 = _out_T_9974; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_880 = _out_T_9975; // @[RegisterRouter.scala:87:24] wire out_rimask_1028 = \|_out_rimask_T_1028; // @[RegisterRouter.scala:87:24] wire out_wimask_1028 = &_out_wimask_T_1028; // @[RegisterRouter.scala:87:24] wire out_romask_1028 = \|_out_romask_T_1028; // @[RegisterRouter.scala:87:24] wire out_womask_1028 = &_out_womask_T_1028; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1028 = out_rivalid_1_882 & out_rimask_1028; // @[RegisterRouter.scala:87:24] wire _out_T_9977 = out_f_rivalid_1028; // @[RegisterRouter.scala:87:24] wire out_f_roready_1028 = out_roready_1_882 & out_romask_1028; // @[RegisterRouter.scala:87:24] wire _out_T_9978 = out_f_roready_1028; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1028 = out_wivalid_1_882 & out_wimask_1028; // @[RegisterRouter.scala:87:24] wire out_f_woready_1028 = out_woready_1_882 & out_womask_1028; // @[RegisterRouter.scala:87:24] wire _out_T_9979 = ~out_rimask_1028; // @[RegisterRouter.scala:87:24] wire _out_T_9980 = ~out_wimask_1028; // @[RegisterRouter.scala:87:24] wire _out_T_9981 = ~out_romask_1028; // @[RegisterRouter.scala:87:24] wire _out_T_9982 = ~out_womask_1028; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_880 = {hi_400, flags_0_go, _out_prepend_T_880}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9983 = out_prepend_880; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9984 = _out_T_9983; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_177 = _out_T_9984; // @[MuxLiteral.scala:49:48] wire out_rimask_1029 = \|_out_rimask_T_1029; // @[RegisterRouter.scala:87:24] wire out_wimask_1029 = &_out_wimask_T_1029; // @[RegisterRouter.scala:87:24] wire out_romask_1029 = \|_out_romask_T_1029; // @[RegisterRouter.scala:87:24] wire out_womask_1029 = &_out_womask_T_1029; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1029 = out_rivalid_1_883 & out_rimask_1029; // @[RegisterRouter.scala:87:24] wire _out_T_9986 = out_f_rivalid_1029; // @[RegisterRouter.scala:87:24] wire out_f_roready_1029 = out_roready_1_883 & out_romask_1029; // @[RegisterRouter.scala:87:24] wire _out_T_9987 = out_f_roready_1029; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1029 = out_wivalid_1_883 & out_wimask_1029; // @[RegisterRouter.scala:87:24] wire out_f_woready_1029 = out_woready_1_883 & out_womask_1029; // @[RegisterRouter.scala:87:24] wire _out_T_9988 = ~out_rimask_1029; // @[RegisterRouter.scala:87:24] wire _out_T_9989 = ~out_wimask_1029; // @[RegisterRouter.scala:87:24] wire _out_T_9990 = ~out_romask_1029; // @[RegisterRouter.scala:87:24] wire _out_T_9991 = ~out_womask_1029; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9993 = _out_T_9992; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_881 = _out_T_9993; // @[RegisterRouter.scala:87:24] wire out_rimask_1030 = \|_out_rimask_T_1030; // @[RegisterRouter.scala:87:24] wire out_wimask_1030 = &_out_wimask_T_1030; // @[RegisterRouter.scala:87:24] wire out_romask_1030 = \|_out_romask_T_1030; // @[RegisterRouter.scala:87:24] wire out_womask_1030 = &_out_womask_T_1030; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1030 = out_rivalid_1_884 & out_rimask_1030; // @[RegisterRouter.scala:87:24] wire _out_T_9995 = out_f_rivalid_1030; // @[RegisterRouter.scala:87:24] wire out_f_roready_1030 = out_roready_1_884 & out_romask_1030; // @[RegisterRouter.scala:87:24] wire _out_T_9996 = out_f_roready_1030; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1030 = out_wivalid_1_884 & out_wimask_1030; // @[RegisterRouter.scala:87:24] wire out_f_woready_1030 = out_woready_1_884 & out_womask_1030; // @[RegisterRouter.scala:87:24] wire _out_T_9997 = ~out_rimask_1030; // @[RegisterRouter.scala:87:24] wire _out_T_9998 = ~out_wimask_1030; // @[RegisterRouter.scala:87:24] wire _out_T_9999 = ~out_romask_1030; // @[RegisterRouter.scala:87:24] wire _out_T_10000 = ~out_womask_1030; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_881 = {hi_434, flags_0_go, _out_prepend_T_881}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10001 = out_prepend_881; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10002 = _out_T_10001; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_882 = _out_T_10002; // @[RegisterRouter.scala:87:24] wire out_rimask_1031 = \|_out_rimask_T_1031; // @[RegisterRouter.scala:87:24] wire out_wimask_1031 = &_out_wimask_T_1031; // @[RegisterRouter.scala:87:24] wire out_romask_1031 = \|_out_romask_T_1031; // @[RegisterRouter.scala:87:24] wire out_womask_1031 = &_out_womask_T_1031; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1031 = out_rivalid_1_885 & out_rimask_1031; // @[RegisterRouter.scala:87:24] wire _out_T_10004 = out_f_rivalid_1031; // @[RegisterRouter.scala:87:24] wire out_f_roready_1031 = out_roready_1_885 & out_romask_1031; // @[RegisterRouter.scala:87:24] wire _out_T_10005 = out_f_roready_1031; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1031 = out_wivalid_1_885 & out_wimask_1031; // @[RegisterRouter.scala:87:24] wire out_f_woready_1031 = out_woready_1_885 & out_womask_1031; // @[RegisterRouter.scala:87:24] wire _out_T_10006 = ~out_rimask_1031; // @[RegisterRouter.scala:87:24] wire _out_T_10007 = ~out_wimask_1031; // @[RegisterRouter.scala:87:24] wire _out_T_10008 = ~out_romask_1031; // @[RegisterRouter.scala:87:24] wire _out_T_10009 = ~out_womask_1031; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_882 = {hi_435, flags_0_go, _out_prepend_T_882}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10010 = out_prepend_882; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10011 = _out_T_10010; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_883 = _out_T_10011; // @[RegisterRouter.scala:87:24] wire out_rimask_1032 = \|_out_rimask_T_1032; // @[RegisterRouter.scala:87:24] wire out_wimask_1032 = &_out_wimask_T_1032; // @[RegisterRouter.scala:87:24] wire out_romask_1032 = \|_out_romask_T_1032; // @[RegisterRouter.scala:87:24] wire out_womask_1032 = &_out_womask_T_1032; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1032 = out_rivalid_1_886 & out_rimask_1032; // @[RegisterRouter.scala:87:24] wire _out_T_10013 = out_f_rivalid_1032; // @[RegisterRouter.scala:87:24] wire out_f_roready_1032 = out_roready_1_886 & out_romask_1032; // @[RegisterRouter.scala:87:24] wire _out_T_10014 = out_f_roready_1032; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1032 = out_wivalid_1_886 & out_wimask_1032; // @[RegisterRouter.scala:87:24] wire out_f_woready_1032 = out_woready_1_886 & out_womask_1032; // @[RegisterRouter.scala:87:24] wire _out_T_10015 = ~out_rimask_1032; // @[RegisterRouter.scala:87:24] wire _out_T_10016 = ~out_wimask_1032; // @[RegisterRouter.scala:87:24] wire _out_T_10017 = ~out_romask_1032; // @[RegisterRouter.scala:87:24] wire _out_T_10018 = ~out_womask_1032; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_883 = {hi_436, flags_0_go, _out_prepend_T_883}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10019 = out_prepend_883; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10020 = _out_T_10019; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_884 = _out_T_10020; // @[RegisterRouter.scala:87:24] wire out_rimask_1033 = \|_out_rimask_T_1033; // @[RegisterRouter.scala:87:24] wire out_wimask_1033 = &_out_wimask_T_1033; // @[RegisterRouter.scala:87:24] wire out_romask_1033 = \|_out_romask_T_1033; // @[RegisterRouter.scala:87:24] wire out_womask_1033 = &_out_womask_T_1033; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1033 = out_rivalid_1_887 & out_rimask_1033; // @[RegisterRouter.scala:87:24] wire _out_T_10022 = out_f_rivalid_1033; // @[RegisterRouter.scala:87:24] wire out_f_roready_1033 = out_roready_1_887 & out_romask_1033; // @[RegisterRouter.scala:87:24] wire _out_T_10023 = out_f_roready_1033; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1033 = out_wivalid_1_887 & out_wimask_1033; // @[RegisterRouter.scala:87:24] wire out_f_woready_1033 = out_woready_1_887 & out_womask_1033; // @[RegisterRouter.scala:87:24] wire _out_T_10024 = ~out_rimask_1033; // @[RegisterRouter.scala:87:24] wire _out_T_10025 = ~out_wimask_1033; // @[RegisterRouter.scala:87:24] wire _out_T_10026 = ~out_romask_1033; // @[RegisterRouter.scala:87:24] wire _out_T_10027 = ~out_womask_1033; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_884 = {hi_437, flags_0_go, _out_prepend_T_884}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10028 = out_prepend_884; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10029 = _out_T_10028; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_885 = _out_T_10029; // @[RegisterRouter.scala:87:24] wire out_rimask_1034 = \|_out_rimask_T_1034; // @[RegisterRouter.scala:87:24] wire out_wimask_1034 = &_out_wimask_T_1034; // @[RegisterRouter.scala:87:24] wire out_romask_1034 = \|_out_romask_T_1034; // @[RegisterRouter.scala:87:24] wire out_womask_1034 = &_out_womask_T_1034; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1034 = out_rivalid_1_888 & out_rimask_1034; // @[RegisterRouter.scala:87:24] wire _out_T_10031 = out_f_rivalid_1034; // @[RegisterRouter.scala:87:24] wire out_f_roready_1034 = out_roready_1_888 & out_romask_1034; // @[RegisterRouter.scala:87:24] wire _out_T_10032 = out_f_roready_1034; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1034 = out_wivalid_1_888 & out_wimask_1034; // @[RegisterRouter.scala:87:24] wire out_f_woready_1034 = out_woready_1_888 & out_womask_1034; // @[RegisterRouter.scala:87:24] wire _out_T_10033 = ~out_rimask_1034; // @[RegisterRouter.scala:87:24] wire _out_T_10034 = ~out_wimask_1034; // @[RegisterRouter.scala:87:24] wire _out_T_10035 = ~out_romask_1034; // @[RegisterRouter.scala:87:24] wire _out_T_10036 = ~out_womask_1034; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_885 = {hi_438, flags_0_go, _out_prepend_T_885}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10037 = out_prepend_885; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10038 = _out_T_10037; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_886 = _out_T_10038; // @[RegisterRouter.scala:87:24] wire out_rimask_1035 = \|_out_rimask_T_1035; // @[RegisterRouter.scala:87:24] wire out_wimask_1035 = &_out_wimask_T_1035; // @[RegisterRouter.scala:87:24] wire out_romask_1035 = \|_out_romask_T_1035; // @[RegisterRouter.scala:87:24] wire out_womask_1035 = &_out_womask_T_1035; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1035 = out_rivalid_1_889 & out_rimask_1035; // @[RegisterRouter.scala:87:24] wire _out_T_10040 = out_f_rivalid_1035; // @[RegisterRouter.scala:87:24] wire out_f_roready_1035 = out_roready_1_889 & out_romask_1035; // @[RegisterRouter.scala:87:24] wire _out_T_10041 = out_f_roready_1035; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1035 = out_wivalid_1_889 & out_wimask_1035; // @[RegisterRouter.scala:87:24] wire out_f_woready_1035 = out_woready_1_889 & out_womask_1035; // @[RegisterRouter.scala:87:24] wire _out_T_10042 = ~out_rimask_1035; // @[RegisterRouter.scala:87:24] wire _out_T_10043 = ~out_wimask_1035; // @[RegisterRouter.scala:87:24] wire _out_T_10044 = ~out_romask_1035; // @[RegisterRouter.scala:87:24] wire _out_T_10045 = ~out_womask_1035; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_886 = {hi_439, flags_0_go, _out_prepend_T_886}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10046 = out_prepend_886; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10047 = _out_T_10046; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_887 = _out_T_10047; // @[RegisterRouter.scala:87:24] wire out_rimask_1036 = \|_out_rimask_T_1036; // @[RegisterRouter.scala:87:24] wire out_wimask_1036 = &_out_wimask_T_1036; // @[RegisterRouter.scala:87:24] wire out_romask_1036 = \|_out_romask_T_1036; // @[RegisterRouter.scala:87:24] wire out_womask_1036 = &_out_womask_T_1036; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1036 = out_rivalid_1_890 & out_rimask_1036; // @[RegisterRouter.scala:87:24] wire _out_T_10049 = out_f_rivalid_1036; // @[RegisterRouter.scala:87:24] wire out_f_roready_1036 = out_roready_1_890 & out_romask_1036; // @[RegisterRouter.scala:87:24] wire _out_T_10050 = out_f_roready_1036; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1036 = out_wivalid_1_890 & out_wimask_1036; // @[RegisterRouter.scala:87:24] wire out_f_woready_1036 = out_woready_1_890 & out_womask_1036; // @[RegisterRouter.scala:87:24] wire _out_T_10051 = ~out_rimask_1036; // @[RegisterRouter.scala:87:24] wire _out_T_10052 = ~out_wimask_1036; // @[RegisterRouter.scala:87:24] wire _out_T_10053 = ~out_romask_1036; // @[RegisterRouter.scala:87:24] wire _out_T_10054 = ~out_womask_1036; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_887 = {hi_440, flags_0_go, _out_prepend_T_887}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10055 = out_prepend_887; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10056 = _out_T_10055; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_182 = _out_T_10056; // @[MuxLiteral.scala:49:48] wire out_rimask_1037 = \|_out_rimask_T_1037; // @[RegisterRouter.scala:87:24] wire out_wimask_1037 = &_out_wimask_T_1037; // @[RegisterRouter.scala:87:24] wire out_romask_1037 = \|_out_romask_T_1037; // @[RegisterRouter.scala:87:24] wire out_womask_1037 = &_out_womask_T_1037; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1037 = out_rivalid_1_891 & out_rimask_1037; // @[RegisterRouter.scala:87:24] wire _out_T_10058 = out_f_rivalid_1037; // @[RegisterRouter.scala:87:24] wire out_f_roready_1037 = out_roready_1_891 & out_romask_1037; // @[RegisterRouter.scala:87:24] wire _out_T_10059 = out_f_roready_1037; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1037 = out_wivalid_1_891 & out_wimask_1037; // @[RegisterRouter.scala:87:24] wire out_f_woready_1037 = out_woready_1_891 & out_womask_1037; // @[RegisterRouter.scala:87:24] wire _out_T_10060 = ~out_rimask_1037; // @[RegisterRouter.scala:87:24] wire _out_T_10061 = ~out_wimask_1037; // @[RegisterRouter.scala:87:24] wire _out_T_10062 = ~out_romask_1037; // @[RegisterRouter.scala:87:24] wire _out_T_10063 = ~out_womask_1037; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10065 = _out_T_10064; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_888 = _out_T_10065; // @[RegisterRouter.scala:87:24] wire out_rimask_1038 = \|_out_rimask_T_1038; // @[RegisterRouter.scala:87:24] wire out_wimask_1038 = &_out_wimask_T_1038; // @[RegisterRouter.scala:87:24] wire out_romask_1038 = \|_out_romask_T_1038; // @[RegisterRouter.scala:87:24] wire out_womask_1038 = &_out_womask_T_1038; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1038 = out_rivalid_1_892 & out_rimask_1038; // @[RegisterRouter.scala:87:24] wire _out_T_10067 = out_f_rivalid_1038; // @[RegisterRouter.scala:87:24] wire out_f_roready_1038 = out_roready_1_892 & out_romask_1038; // @[RegisterRouter.scala:87:24] wire _out_T_10068 = out_f_roready_1038; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1038 = out_wivalid_1_892 & out_wimask_1038; // @[RegisterRouter.scala:87:24] wire out_f_woready_1038 = out_woready_1_892 & out_womask_1038; // @[RegisterRouter.scala:87:24] wire _out_T_10069 = ~out_rimask_1038; // @[RegisterRouter.scala:87:24] wire _out_T_10070 = ~out_wimask_1038; // @[RegisterRouter.scala:87:24] wire _out_T_10071 = ~out_romask_1038; // @[RegisterRouter.scala:87:24] wire _out_T_10072 = ~out_womask_1038; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_888 = {hi_210, flags_0_go, _out_prepend_T_888}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10073 = out_prepend_888; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10074 = _out_T_10073; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_889 = _out_T_10074; // @[RegisterRouter.scala:87:24] wire out_rimask_1039 = \|_out_rimask_T_1039; // @[RegisterRouter.scala:87:24] wire out_wimask_1039 = &_out_wimask_T_1039; // @[RegisterRouter.scala:87:24] wire out_romask_1039 = \|_out_romask_T_1039; // @[RegisterRouter.scala:87:24] wire out_womask_1039 = &_out_womask_T_1039; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1039 = out_rivalid_1_893 & out_rimask_1039; // @[RegisterRouter.scala:87:24] wire _out_T_10076 = out_f_rivalid_1039; // @[RegisterRouter.scala:87:24] wire out_f_roready_1039 = out_roready_1_893 & out_romask_1039; // @[RegisterRouter.scala:87:24] wire _out_T_10077 = out_f_roready_1039; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1039 = out_wivalid_1_893 & out_wimask_1039; // @[RegisterRouter.scala:87:24] wire out_f_woready_1039 = out_woready_1_893 & out_womask_1039; // @[RegisterRouter.scala:87:24] wire _out_T_10078 = ~out_rimask_1039; // @[RegisterRouter.scala:87:24] wire _out_T_10079 = ~out_wimask_1039; // @[RegisterRouter.scala:87:24] wire _out_T_10080 = ~out_romask_1039; // @[RegisterRouter.scala:87:24] wire _out_T_10081 = ~out_womask_1039; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_889 = {hi_211, flags_0_go, _out_prepend_T_889}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10082 = out_prepend_889; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10083 = _out_T_10082; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_890 = _out_T_10083; // @[RegisterRouter.scala:87:24] wire out_rimask_1040 = \|_out_rimask_T_1040; // @[RegisterRouter.scala:87:24] wire out_wimask_1040 = &_out_wimask_T_1040; // @[RegisterRouter.scala:87:24] wire out_romask_1040 = \|_out_romask_T_1040; // @[RegisterRouter.scala:87:24] wire out_womask_1040 = &_out_womask_T_1040; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1040 = out_rivalid_1_894 & out_rimask_1040; // @[RegisterRouter.scala:87:24] wire _out_T_10085 = out_f_rivalid_1040; // @[RegisterRouter.scala:87:24] wire out_f_roready_1040 = out_roready_1_894 & out_romask_1040; // @[RegisterRouter.scala:87:24] wire _out_T_10086 = out_f_roready_1040; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1040 = out_wivalid_1_894 & out_wimask_1040; // @[RegisterRouter.scala:87:24] wire out_f_woready_1040 = out_woready_1_894 & out_womask_1040; // @[RegisterRouter.scala:87:24] wire _out_T_10087 = ~out_rimask_1040; // @[RegisterRouter.scala:87:24] wire _out_T_10088 = ~out_wimask_1040; // @[RegisterRouter.scala:87:24] wire _out_T_10089 = ~out_romask_1040; // @[RegisterRouter.scala:87:24] wire _out_T_10090 = ~out_womask_1040; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_890 = {hi_212, flags_0_go, _out_prepend_T_890}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10091 = out_prepend_890; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10092 = _out_T_10091; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_891 = _out_T_10092; // @[RegisterRouter.scala:87:24] wire out_rimask_1041 = \|_out_rimask_T_1041; // @[RegisterRouter.scala:87:24] wire out_wimask_1041 = &_out_wimask_T_1041; // @[RegisterRouter.scala:87:24] wire out_romask_1041 = \|_out_romask_T_1041; // @[RegisterRouter.scala:87:24] wire out_womask_1041 = &_out_womask_T_1041; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1041 = out_rivalid_1_895 & out_rimask_1041; // @[RegisterRouter.scala:87:24] wire _out_T_10094 = out_f_rivalid_1041; // @[RegisterRouter.scala:87:24] wire out_f_roready_1041 = out_roready_1_895 & out_romask_1041; // @[RegisterRouter.scala:87:24] wire _out_T_10095 = out_f_roready_1041; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1041 = out_wivalid_1_895 & out_wimask_1041; // @[RegisterRouter.scala:87:24] wire out_f_woready_1041 = out_woready_1_895 & out_womask_1041; // @[RegisterRouter.scala:87:24] wire _out_T_10096 = ~out_rimask_1041; // @[RegisterRouter.scala:87:24] wire _out_T_10097 = ~out_wimask_1041; // @[RegisterRouter.scala:87:24] wire _out_T_10098 = ~out_romask_1041; // @[RegisterRouter.scala:87:24] wire _out_T_10099 = ~out_womask_1041; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_891 = {hi_213, flags_0_go, _out_prepend_T_891}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10100 = out_prepend_891; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10101 = _out_T_10100; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_892 = _out_T_10101; // @[RegisterRouter.scala:87:24] wire out_rimask_1042 = \|_out_rimask_T_1042; // @[RegisterRouter.scala:87:24] wire out_wimask_1042 = &_out_wimask_T_1042; // @[RegisterRouter.scala:87:24] wire out_romask_1042 = \|_out_romask_T_1042; // @[RegisterRouter.scala:87:24] wire out_womask_1042 = &_out_womask_T_1042; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1042 = out_rivalid_1_896 & out_rimask_1042; // @[RegisterRouter.scala:87:24] wire _out_T_10103 = out_f_rivalid_1042; // @[RegisterRouter.scala:87:24] wire out_f_roready_1042 = out_roready_1_896 & out_romask_1042; // @[RegisterRouter.scala:87:24] wire _out_T_10104 = out_f_roready_1042; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1042 = out_wivalid_1_896 & out_wimask_1042; // @[RegisterRouter.scala:87:24] wire out_f_woready_1042 = out_woready_1_896 & out_womask_1042; // @[RegisterRouter.scala:87:24] wire _out_T_10105 = ~out_rimask_1042; // @[RegisterRouter.scala:87:24] wire _out_T_10106 = ~out_wimask_1042; // @[RegisterRouter.scala:87:24] wire _out_T_10107 = ~out_romask_1042; // @[RegisterRouter.scala:87:24] wire _out_T_10108 = ~out_womask_1042; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_892 = {hi_214, flags_0_go, _out_prepend_T_892}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10109 = out_prepend_892; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10110 = _out_T_10109; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_893 = _out_T_10110; // @[RegisterRouter.scala:87:24] wire out_rimask_1043 = \|_out_rimask_T_1043; // @[RegisterRouter.scala:87:24] wire out_wimask_1043 = &_out_wimask_T_1043; // @[RegisterRouter.scala:87:24] wire out_romask_1043 = \|_out_romask_T_1043; // @[RegisterRouter.scala:87:24] wire out_womask_1043 = &_out_womask_T_1043; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1043 = out_rivalid_1_897 & out_rimask_1043; // @[RegisterRouter.scala:87:24] wire _out_T_10112 = out_f_rivalid_1043; // @[RegisterRouter.scala:87:24] wire out_f_roready_1043 = out_roready_1_897 & out_romask_1043; // @[RegisterRouter.scala:87:24] wire _out_T_10113 = out_f_roready_1043; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1043 = out_wivalid_1_897 & out_wimask_1043; // @[RegisterRouter.scala:87:24] wire out_f_woready_1043 = out_woready_1_897 & out_womask_1043; // @[RegisterRouter.scala:87:24] wire _out_T_10114 = ~out_rimask_1043; // @[RegisterRouter.scala:87:24] wire _out_T_10115 = ~out_wimask_1043; // @[RegisterRouter.scala:87:24] wire _out_T_10116 = ~out_romask_1043; // @[RegisterRouter.scala:87:24] wire _out_T_10117 = ~out_womask_1043; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_893 = {hi_215, flags_0_go, _out_prepend_T_893}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10118 = out_prepend_893; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10119 = _out_T_10118; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_894 = _out_T_10119; // @[RegisterRouter.scala:87:24] wire out_rimask_1044 = \|_out_rimask_T_1044; // @[RegisterRouter.scala:87:24] wire out_wimask_1044 = &_out_wimask_T_1044; // @[RegisterRouter.scala:87:24] wire out_romask_1044 = \|_out_romask_T_1044; // @[RegisterRouter.scala:87:24] wire out_womask_1044 = &_out_womask_T_1044; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1044 = out_rivalid_1_898 & out_rimask_1044; // @[RegisterRouter.scala:87:24] wire _out_T_10121 = out_f_rivalid_1044; // @[RegisterRouter.scala:87:24] wire out_f_roready_1044 = out_roready_1_898 & out_romask_1044; // @[RegisterRouter.scala:87:24] wire _out_T_10122 = out_f_roready_1044; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1044 = out_wivalid_1_898 & out_wimask_1044; // @[RegisterRouter.scala:87:24] wire out_f_woready_1044 = out_woready_1_898 & out_womask_1044; // @[RegisterRouter.scala:87:24] wire _out_T_10123 = ~out_rimask_1044; // @[RegisterRouter.scala:87:24] wire _out_T_10124 = ~out_wimask_1044; // @[RegisterRouter.scala:87:24] wire _out_T_10125 = ~out_romask_1044; // @[RegisterRouter.scala:87:24] wire _out_T_10126 = ~out_womask_1044; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_894 = {hi_216, flags_0_go, _out_prepend_T_894}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10127 = out_prepend_894; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10128 = _out_T_10127; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_154 = _out_T_10128; // @[MuxLiteral.scala:49:48] wire out_rimask_1045 = \|_out_rimask_T_1045; // @[RegisterRouter.scala:87:24] wire out_wimask_1045 = &_out_wimask_T_1045; // @[RegisterRouter.scala:87:24] wire out_romask_1045 = \|_out_romask_T_1045; // @[RegisterRouter.scala:87:24] wire out_womask_1045 = &_out_womask_T_1045; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1045 = out_rivalid_1_899 & out_rimask_1045; // @[RegisterRouter.scala:87:24] wire _out_T_10130 = out_f_rivalid_1045; // @[RegisterRouter.scala:87:24] wire out_f_roready_1045 = out_roready_1_899 & out_romask_1045; // @[RegisterRouter.scala:87:24] wire _out_T_10131 = out_f_roready_1045; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1045 = out_wivalid_1_899 & out_wimask_1045; // @[RegisterRouter.scala:87:24] wire out_f_woready_1045 = out_woready_1_899 & out_womask_1045; // @[RegisterRouter.scala:87:24] wire _out_T_10132 = ~out_rimask_1045; // @[RegisterRouter.scala:87:24] wire _out_T_10133 = ~out_wimask_1045; // @[RegisterRouter.scala:87:24] wire _out_T_10134 = ~out_romask_1045; // @[RegisterRouter.scala:87:24] wire _out_T_10135 = ~out_womask_1045; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10137 = _out_T_10136; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_895 = _out_T_10137; // @[RegisterRouter.scala:87:24] wire out_rimask_1046 = \|_out_rimask_T_1046; // @[RegisterRouter.scala:87:24] wire out_wimask_1046 = &_out_wimask_T_1046; // @[RegisterRouter.scala:87:24] wire out_romask_1046 = \|_out_romask_T_1046; // @[RegisterRouter.scala:87:24] wire out_womask_1046 = &_out_womask_T_1046; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1046 = out_rivalid_1_900 & out_rimask_1046; // @[RegisterRouter.scala:87:24] wire _out_T_10139 = out_f_rivalid_1046; // @[RegisterRouter.scala:87:24] wire out_f_roready_1046 = out_roready_1_900 & out_romask_1046; // @[RegisterRouter.scala:87:24] wire _out_T_10140 = out_f_roready_1046; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1046 = out_wivalid_1_900 & out_wimask_1046; // @[RegisterRouter.scala:87:24] wire out_f_woready_1046 = out_woready_1_900 & out_womask_1046; // @[RegisterRouter.scala:87:24] wire _out_T_10141 = ~out_rimask_1046; // @[RegisterRouter.scala:87:24] wire _out_T_10142 = ~out_wimask_1046; // @[RegisterRouter.scala:87:24] wire _out_T_10143 = ~out_romask_1046; // @[RegisterRouter.scala:87:24] wire _out_T_10144 = ~out_womask_1046; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_895 = {hi_378, flags_0_go, _out_prepend_T_895}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10145 = out_prepend_895; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10146 = _out_T_10145; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_896 = _out_T_10146; // @[RegisterRouter.scala:87:24] wire out_rimask_1047 = \|_out_rimask_T_1047; // @[RegisterRouter.scala:87:24] wire out_wimask_1047 = &_out_wimask_T_1047; // @[RegisterRouter.scala:87:24] wire out_romask_1047 = \|_out_romask_T_1047; // @[RegisterRouter.scala:87:24] wire out_womask_1047 = &_out_womask_T_1047; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1047 = out_rivalid_1_901 & out_rimask_1047; // @[RegisterRouter.scala:87:24] wire _out_T_10148 = out_f_rivalid_1047; // @[RegisterRouter.scala:87:24] wire out_f_roready_1047 = out_roready_1_901 & out_romask_1047; // @[RegisterRouter.scala:87:24] wire _out_T_10149 = out_f_roready_1047; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1047 = out_wivalid_1_901 & out_wimask_1047; // @[RegisterRouter.scala:87:24] wire out_f_woready_1047 = out_woready_1_901 & out_womask_1047; // @[RegisterRouter.scala:87:24] wire _out_T_10150 = ~out_rimask_1047; // @[RegisterRouter.scala:87:24] wire _out_T_10151 = ~out_wimask_1047; // @[RegisterRouter.scala:87:24] wire _out_T_10152 = ~out_romask_1047; // @[RegisterRouter.scala:87:24] wire _out_T_10153 = ~out_womask_1047; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_896 = {hi_379, flags_0_go, _out_prepend_T_896}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10154 = out_prepend_896; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10155 = _out_T_10154; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_897 = _out_T_10155; // @[RegisterRouter.scala:87:24] wire out_rimask_1048 = \|_out_rimask_T_1048; // @[RegisterRouter.scala:87:24] wire out_wimask_1048 = &_out_wimask_T_1048; // @[RegisterRouter.scala:87:24] wire out_romask_1048 = \|_out_romask_T_1048; // @[RegisterRouter.scala:87:24] wire out_womask_1048 = &_out_womask_T_1048; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1048 = out_rivalid_1_902 & out_rimask_1048; // @[RegisterRouter.scala:87:24] wire _out_T_10157 = out_f_rivalid_1048; // @[RegisterRouter.scala:87:24] wire out_f_roready_1048 = out_roready_1_902 & out_romask_1048; // @[RegisterRouter.scala:87:24] wire _out_T_10158 = out_f_roready_1048; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1048 = out_wivalid_1_902 & out_wimask_1048; // @[RegisterRouter.scala:87:24] wire out_f_woready_1048 = out_woready_1_902 & out_womask_1048; // @[RegisterRouter.scala:87:24] wire _out_T_10159 = ~out_rimask_1048; // @[RegisterRouter.scala:87:24] wire _out_T_10160 = ~out_wimask_1048; // @[RegisterRouter.scala:87:24] wire _out_T_10161 = ~out_romask_1048; // @[RegisterRouter.scala:87:24] wire _out_T_10162 = ~out_womask_1048; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_897 = {hi_380, flags_0_go, _out_prepend_T_897}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10163 = out_prepend_897; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10164 = _out_T_10163; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_898 = _out_T_10164; // @[RegisterRouter.scala:87:24] wire out_rimask_1049 = \|_out_rimask_T_1049; // @[RegisterRouter.scala:87:24] wire out_wimask_1049 = &_out_wimask_T_1049; // @[RegisterRouter.scala:87:24] wire out_romask_1049 = \|_out_romask_T_1049; // @[RegisterRouter.scala:87:24] wire out_womask_1049 = &_out_womask_T_1049; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1049 = out_rivalid_1_903 & out_rimask_1049; // @[RegisterRouter.scala:87:24] wire _out_T_10166 = out_f_rivalid_1049; // @[RegisterRouter.scala:87:24] wire out_f_roready_1049 = out_roready_1_903 & out_romask_1049; // @[RegisterRouter.scala:87:24] wire _out_T_10167 = out_f_roready_1049; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1049 = out_wivalid_1_903 & out_wimask_1049; // @[RegisterRouter.scala:87:24] wire out_f_woready_1049 = out_woready_1_903 & out_womask_1049; // @[RegisterRouter.scala:87:24] wire _out_T_10168 = ~out_rimask_1049; // @[RegisterRouter.scala:87:24] wire _out_T_10169 = ~out_wimask_1049; // @[RegisterRouter.scala:87:24] wire _out_T_10170 = ~out_romask_1049; // @[RegisterRouter.scala:87:24] wire _out_T_10171 = ~out_womask_1049; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_898 = {hi_381, flags_0_go, _out_prepend_T_898}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10172 = out_prepend_898; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10173 = _out_T_10172; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_899 = _out_T_10173; // @[RegisterRouter.scala:87:24] wire out_rimask_1050 = \|_out_rimask_T_1050; // @[RegisterRouter.scala:87:24] wire out_wimask_1050 = &_out_wimask_T_1050; // @[RegisterRouter.scala:87:24] wire out_romask_1050 = \|_out_romask_T_1050; // @[RegisterRouter.scala:87:24] wire out_womask_1050 = &_out_womask_T_1050; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1050 = out_rivalid_1_904 & out_rimask_1050; // @[RegisterRouter.scala:87:24] wire _out_T_10175 = out_f_rivalid_1050; // @[RegisterRouter.scala:87:24] wire out_f_roready_1050 = out_roready_1_904 & out_romask_1050; // @[RegisterRouter.scala:87:24] wire _out_T_10176 = out_f_roready_1050; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1050 = out_wivalid_1_904 & out_wimask_1050; // @[RegisterRouter.scala:87:24] wire out_f_woready_1050 = out_woready_1_904 & out_womask_1050; // @[RegisterRouter.scala:87:24] wire _out_T_10177 = ~out_rimask_1050; // @[RegisterRouter.scala:87:24] wire _out_T_10178 = ~out_wimask_1050; // @[RegisterRouter.scala:87:24] wire _out_T_10179 = ~out_romask_1050; // @[RegisterRouter.scala:87:24] wire _out_T_10180 = ~out_womask_1050; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_899 = {hi_382, flags_0_go, _out_prepend_T_899}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10181 = out_prepend_899; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10182 = _out_T_10181; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_900 = _out_T_10182; // @[RegisterRouter.scala:87:24] wire out_rimask_1051 = \|_out_rimask_T_1051; // @[RegisterRouter.scala:87:24] wire out_wimask_1051 = &_out_wimask_T_1051; // @[RegisterRouter.scala:87:24] wire out_romask_1051 = \|_out_romask_T_1051; // @[RegisterRouter.scala:87:24] wire out_womask_1051 = &_out_womask_T_1051; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1051 = out_rivalid_1_905 & out_rimask_1051; // @[RegisterRouter.scala:87:24] wire _out_T_10184 = out_f_rivalid_1051; // @[RegisterRouter.scala:87:24] wire out_f_roready_1051 = out_roready_1_905 & out_romask_1051; // @[RegisterRouter.scala:87:24] wire _out_T_10185 = out_f_roready_1051; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1051 = out_wivalid_1_905 & out_wimask_1051; // @[RegisterRouter.scala:87:24] wire out_f_woready_1051 = out_woready_1_905 & out_womask_1051; // @[RegisterRouter.scala:87:24] wire _out_T_10186 = ~out_rimask_1051; // @[RegisterRouter.scala:87:24] wire _out_T_10187 = ~out_wimask_1051; // @[RegisterRouter.scala:87:24] wire _out_T_10188 = ~out_romask_1051; // @[RegisterRouter.scala:87:24] wire _out_T_10189 = ~out_womask_1051; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_900 = {hi_383, flags_0_go, _out_prepend_T_900}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10190 = out_prepend_900; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10191 = _out_T_10190; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_901 = _out_T_10191; // @[RegisterRouter.scala:87:24] wire out_rimask_1052 = \|_out_rimask_T_1052; // @[RegisterRouter.scala:87:24] wire out_wimask_1052 = &_out_wimask_T_1052; // @[RegisterRouter.scala:87:24] wire out_romask_1052 = \|_out_romask_T_1052; // @[RegisterRouter.scala:87:24] wire out_womask_1052 = &_out_womask_T_1052; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1052 = out_rivalid_1_906 & out_rimask_1052; // @[RegisterRouter.scala:87:24] wire _out_T_10193 = out_f_rivalid_1052; // @[RegisterRouter.scala:87:24] wire out_f_roready_1052 = out_roready_1_906 & out_romask_1052; // @[RegisterRouter.scala:87:24] wire _out_T_10194 = out_f_roready_1052; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1052 = out_wivalid_1_906 & out_wimask_1052; // @[RegisterRouter.scala:87:24] wire out_f_woready_1052 = out_woready_1_906 & out_womask_1052; // @[RegisterRouter.scala:87:24] wire _out_T_10195 = ~out_rimask_1052; // @[RegisterRouter.scala:87:24] wire _out_T_10196 = ~out_wimask_1052; // @[RegisterRouter.scala:87:24] wire _out_T_10197 = ~out_romask_1052; // @[RegisterRouter.scala:87:24] wire _out_T_10198 = ~out_womask_1052; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_901 = {hi_384, flags_0_go, _out_prepend_T_901}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10199 = out_prepend_901; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10200 = _out_T_10199; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_175 = _out_T_10200; // @[MuxLiteral.scala:49:48] wire out_rimask_1053 = \|_out_rimask_T_1053; // @[RegisterRouter.scala:87:24] wire out_wimask_1053 = &_out_wimask_T_1053; // @[RegisterRouter.scala:87:24] wire out_romask_1053 = \|_out_romask_T_1053; // @[RegisterRouter.scala:87:24] wire out_womask_1053 = &_out_womask_T_1053; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1053 = out_rivalid_1_907 & out_rimask_1053; // @[RegisterRouter.scala:87:24] wire _out_T_10202 = out_f_rivalid_1053; // @[RegisterRouter.scala:87:24] wire out_f_roready_1053 = out_roready_1_907 & out_romask_1053; // @[RegisterRouter.scala:87:24] wire _out_T_10203 = out_f_roready_1053; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1053 = out_wivalid_1_907 & out_wimask_1053; // @[RegisterRouter.scala:87:24] wire out_f_woready_1053 = out_woready_1_907 & out_womask_1053; // @[RegisterRouter.scala:87:24] wire _out_T_10204 = ~out_rimask_1053; // @[RegisterRouter.scala:87:24] wire _out_T_10205 = ~out_wimask_1053; // @[RegisterRouter.scala:87:24] wire _out_T_10206 = ~out_romask_1053; // @[RegisterRouter.scala:87:24] wire _out_T_10207 = ~out_womask_1053; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10209 = _out_T_10208; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_902 = _out_T_10209; // @[RegisterRouter.scala:87:24] wire out_rimask_1054 = \|_out_rimask_T_1054; // @[RegisterRouter.scala:87:24] wire out_wimask_1054 = &_out_wimask_T_1054; // @[RegisterRouter.scala:87:24] wire out_romask_1054 = \|_out_romask_T_1054; // @[RegisterRouter.scala:87:24] wire out_womask_1054 = &_out_womask_T_1054; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1054 = out_rivalid_1_908 & out_rimask_1054; // @[RegisterRouter.scala:87:24] wire _out_T_10211 = out_f_rivalid_1054; // @[RegisterRouter.scala:87:24] wire out_f_roready_1054 = out_roready_1_908 & out_romask_1054; // @[RegisterRouter.scala:87:24] wire _out_T_10212 = out_f_roready_1054; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1054 = out_wivalid_1_908 & out_wimask_1054; // @[RegisterRouter.scala:87:24] wire out_f_woready_1054 = out_woready_1_908 & out_womask_1054; // @[RegisterRouter.scala:87:24] wire _out_T_10213 = ~out_rimask_1054; // @[RegisterRouter.scala:87:24] wire _out_T_10214 = ~out_wimask_1054; // @[RegisterRouter.scala:87:24] wire _out_T_10215 = ~out_romask_1054; // @[RegisterRouter.scala:87:24] wire _out_T_10216 = ~out_womask_1054; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_902 = {hi_122, flags_0_go, _out_prepend_T_902}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10217 = out_prepend_902; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10218 = _out_T_10217; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_903 = _out_T_10218; // @[RegisterRouter.scala:87:24] wire out_rimask_1055 = \|_out_rimask_T_1055; // @[RegisterRouter.scala:87:24] wire out_wimask_1055 = &_out_wimask_T_1055; // @[RegisterRouter.scala:87:24] wire out_romask_1055 = \|_out_romask_T_1055; // @[RegisterRouter.scala:87:24] wire out_womask_1055 = &_out_womask_T_1055; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1055 = out_rivalid_1_909 & out_rimask_1055; // @[RegisterRouter.scala:87:24] wire _out_T_10220 = out_f_rivalid_1055; // @[RegisterRouter.scala:87:24] wire out_f_roready_1055 = out_roready_1_909 & out_romask_1055; // @[RegisterRouter.scala:87:24] wire _out_T_10221 = out_f_roready_1055; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1055 = out_wivalid_1_909 & out_wimask_1055; // @[RegisterRouter.scala:87:24] wire out_f_woready_1055 = out_woready_1_909 & out_womask_1055; // @[RegisterRouter.scala:87:24] wire _out_T_10222 = ~out_rimask_1055; // @[RegisterRouter.scala:87:24] wire _out_T_10223 = ~out_wimask_1055; // @[RegisterRouter.scala:87:24] wire _out_T_10224 = ~out_romask_1055; // @[RegisterRouter.scala:87:24] wire _out_T_10225 = ~out_womask_1055; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_903 = {hi_123, flags_0_go, _out_prepend_T_903}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10226 = out_prepend_903; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10227 = _out_T_10226; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_904 = _out_T_10227; // @[RegisterRouter.scala:87:24] wire out_rimask_1056 = \|_out_rimask_T_1056; // @[RegisterRouter.scala:87:24] wire out_wimask_1056 = &_out_wimask_T_1056; // @[RegisterRouter.scala:87:24] wire out_romask_1056 = \|_out_romask_T_1056; // @[RegisterRouter.scala:87:24] wire out_womask_1056 = &_out_womask_T_1056; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1056 = out_rivalid_1_910 & out_rimask_1056; // @[RegisterRouter.scala:87:24] wire _out_T_10229 = out_f_rivalid_1056; // @[RegisterRouter.scala:87:24] wire out_f_roready_1056 = out_roready_1_910 & out_romask_1056; // @[RegisterRouter.scala:87:24] wire _out_T_10230 = out_f_roready_1056; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1056 = out_wivalid_1_910 & out_wimask_1056; // @[RegisterRouter.scala:87:24] wire out_f_woready_1056 = out_woready_1_910 & out_womask_1056; // @[RegisterRouter.scala:87:24] wire _out_T_10231 = ~out_rimask_1056; // @[RegisterRouter.scala:87:24] wire _out_T_10232 = ~out_wimask_1056; // @[RegisterRouter.scala:87:24] wire _out_T_10233 = ~out_romask_1056; // @[RegisterRouter.scala:87:24] wire _out_T_10234 = ~out_womask_1056; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_904 = {hi_124, flags_0_go, _out_prepend_T_904}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10235 = out_prepend_904; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10236 = _out_T_10235; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_905 = _out_T_10236; // @[RegisterRouter.scala:87:24] wire out_rimask_1057 = \|_out_rimask_T_1057; // @[RegisterRouter.scala:87:24] wire out_wimask_1057 = &_out_wimask_T_1057; // @[RegisterRouter.scala:87:24] wire out_romask_1057 = \|_out_romask_T_1057; // @[RegisterRouter.scala:87:24] wire out_womask_1057 = &_out_womask_T_1057; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1057 = out_rivalid_1_911 & out_rimask_1057; // @[RegisterRouter.scala:87:24] wire _out_T_10238 = out_f_rivalid_1057; // @[RegisterRouter.scala:87:24] wire out_f_roready_1057 = out_roready_1_911 & out_romask_1057; // @[RegisterRouter.scala:87:24] wire _out_T_10239 = out_f_roready_1057; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1057 = out_wivalid_1_911 & out_wimask_1057; // @[RegisterRouter.scala:87:24] wire out_f_woready_1057 = out_woready_1_911 & out_womask_1057; // @[RegisterRouter.scala:87:24] wire _out_T_10240 = ~out_rimask_1057; // @[RegisterRouter.scala:87:24] wire _out_T_10241 = ~out_wimask_1057; // @[RegisterRouter.scala:87:24] wire _out_T_10242 = ~out_romask_1057; // @[RegisterRouter.scala:87:24] wire _out_T_10243 = ~out_womask_1057; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_905 = {hi_125, flags_0_go, _out_prepend_T_905}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10244 = out_prepend_905; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10245 = _out_T_10244; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_906 = _out_T_10245; // @[RegisterRouter.scala:87:24] wire out_rimask_1058 = \|_out_rimask_T_1058; // @[RegisterRouter.scala:87:24] wire out_wimask_1058 = &_out_wimask_T_1058; // @[RegisterRouter.scala:87:24] wire out_romask_1058 = \|_out_romask_T_1058; // @[RegisterRouter.scala:87:24] wire out_womask_1058 = &_out_womask_T_1058; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1058 = out_rivalid_1_912 & out_rimask_1058; // @[RegisterRouter.scala:87:24] wire _out_T_10247 = out_f_rivalid_1058; // @[RegisterRouter.scala:87:24] wire out_f_roready_1058 = out_roready_1_912 & out_romask_1058; // @[RegisterRouter.scala:87:24] wire _out_T_10248 = out_f_roready_1058; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1058 = out_wivalid_1_912 & out_wimask_1058; // @[RegisterRouter.scala:87:24] wire out_f_woready_1058 = out_woready_1_912 & out_womask_1058; // @[RegisterRouter.scala:87:24] wire _out_T_10249 = ~out_rimask_1058; // @[RegisterRouter.scala:87:24] wire _out_T_10250 = ~out_wimask_1058; // @[RegisterRouter.scala:87:24] wire _out_T_10251 = ~out_romask_1058; // @[RegisterRouter.scala:87:24] wire _out_T_10252 = ~out_womask_1058; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_906 = {hi_126, flags_0_go, _out_prepend_T_906}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10253 = out_prepend_906; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10254 = _out_T_10253; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_907 = _out_T_10254; // @[RegisterRouter.scala:87:24] wire out_rimask_1059 = \|_out_rimask_T_1059; // @[RegisterRouter.scala:87:24] wire out_wimask_1059 = &_out_wimask_T_1059; // @[RegisterRouter.scala:87:24] wire out_romask_1059 = \|_out_romask_T_1059; // @[RegisterRouter.scala:87:24] wire out_womask_1059 = &_out_womask_T_1059; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1059 = out_rivalid_1_913 & out_rimask_1059; // @[RegisterRouter.scala:87:24] wire _out_T_10256 = out_f_rivalid_1059; // @[RegisterRouter.scala:87:24] wire out_f_roready_1059 = out_roready_1_913 & out_romask_1059; // @[RegisterRouter.scala:87:24] wire _out_T_10257 = out_f_roready_1059; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1059 = out_wivalid_1_913 & out_wimask_1059; // @[RegisterRouter.scala:87:24] wire out_f_woready_1059 = out_woready_1_913 & out_womask_1059; // @[RegisterRouter.scala:87:24] wire _out_T_10258 = ~out_rimask_1059; // @[RegisterRouter.scala:87:24] wire _out_T_10259 = ~out_wimask_1059; // @[RegisterRouter.scala:87:24] wire _out_T_10260 = ~out_romask_1059; // @[RegisterRouter.scala:87:24] wire _out_T_10261 = ~out_womask_1059; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_907 = {hi_127, flags_0_go, _out_prepend_T_907}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10262 = out_prepend_907; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10263 = _out_T_10262; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_908 = _out_T_10263; // @[RegisterRouter.scala:87:24] wire out_rimask_1060 = \|_out_rimask_T_1060; // @[RegisterRouter.scala:87:24] wire out_wimask_1060 = &_out_wimask_T_1060; // @[RegisterRouter.scala:87:24] wire out_romask_1060 = \|_out_romask_T_1060; // @[RegisterRouter.scala:87:24] wire out_womask_1060 = &_out_womask_T_1060; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1060 = out_rivalid_1_914 & out_rimask_1060; // @[RegisterRouter.scala:87:24] wire _out_T_10265 = out_f_rivalid_1060; // @[RegisterRouter.scala:87:24] wire out_f_roready_1060 = out_roready_1_914 & out_romask_1060; // @[RegisterRouter.scala:87:24] wire _out_T_10266 = out_f_roready_1060; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1060 = out_wivalid_1_914 & out_wimask_1060; // @[RegisterRouter.scala:87:24] wire out_f_woready_1060 = out_woready_1_914 & out_womask_1060; // @[RegisterRouter.scala:87:24] wire _out_T_10267 = ~out_rimask_1060; // @[RegisterRouter.scala:87:24] wire _out_T_10268 = ~out_wimask_1060; // @[RegisterRouter.scala:87:24] wire _out_T_10269 = ~out_romask_1060; // @[RegisterRouter.scala:87:24] wire _out_T_10270 = ~out_womask_1060; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_908 = {hi_128, flags_0_go, _out_prepend_T_908}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10271 = out_prepend_908; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10272 = _out_T_10271; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_143 = _out_T_10272; // @[MuxLiteral.scala:49:48] wire out_rimask_1061 = \|_out_rimask_T_1061; // @[RegisterRouter.scala:87:24] wire out_wimask_1061 = &_out_wimask_T_1061; // @[RegisterRouter.scala:87:24] wire out_romask_1061 = \|_out_romask_T_1061; // @[RegisterRouter.scala:87:24] wire out_womask_1061 = &_out_womask_T_1061; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1061 = out_rivalid_1_915 & out_rimask_1061; // @[RegisterRouter.scala:87:24] wire _out_T_10274 = out_f_rivalid_1061; // @[RegisterRouter.scala:87:24] wire out_f_roready_1061 = out_roready_1_915 & out_romask_1061; // @[RegisterRouter.scala:87:24] wire _out_T_10275 = out_f_roready_1061; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1061 = out_wivalid_1_915 & out_wimask_1061; // @[RegisterRouter.scala:87:24] wire out_f_woready_1061 = out_woready_1_915 & out_womask_1061; // @[RegisterRouter.scala:87:24] wire _out_T_10276 = ~out_rimask_1061; // @[RegisterRouter.scala:87:24] wire _out_T_10277 = ~out_wimask_1061; // @[RegisterRouter.scala:87:24] wire _out_T_10278 = ~out_romask_1061; // @[RegisterRouter.scala:87:24] wire _out_T_10279 = ~out_womask_1061; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10281 = _out_T_10280; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_909 = _out_T_10281; // @[RegisterRouter.scala:87:24] wire out_rimask_1062 = \|_out_rimask_T_1062; // @[RegisterRouter.scala:87:24] wire out_wimask_1062 = &_out_wimask_T_1062; // @[RegisterRouter.scala:87:24] wire out_romask_1062 = \|_out_romask_T_1062; // @[RegisterRouter.scala:87:24] wire out_womask_1062 = &_out_womask_T_1062; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1062 = out_rivalid_1_916 & out_rimask_1062; // @[RegisterRouter.scala:87:24] wire _out_T_10283 = out_f_rivalid_1062; // @[RegisterRouter.scala:87:24] wire out_f_roready_1062 = out_roready_1_916 & out_romask_1062; // @[RegisterRouter.scala:87:24] wire _out_T_10284 = out_f_roready_1062; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1062 = out_wivalid_1_916 & out_wimask_1062; // @[RegisterRouter.scala:87:24] wire out_f_woready_1062 = out_woready_1_916 & out_womask_1062; // @[RegisterRouter.scala:87:24] wire _out_T_10285 = ~out_rimask_1062; // @[RegisterRouter.scala:87:24] wire _out_T_10286 = ~out_wimask_1062; // @[RegisterRouter.scala:87:24] wire _out_T_10287 = ~out_romask_1062; // @[RegisterRouter.scala:87:24] wire _out_T_10288 = ~out_womask_1062; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_909 = {hi_602, flags_0_go, _out_prepend_T_909}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10289 = out_prepend_909; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10290 = _out_T_10289; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_910 = _out_T_10290; // @[RegisterRouter.scala:87:24] wire out_rimask_1063 = \|_out_rimask_T_1063; // @[RegisterRouter.scala:87:24] wire out_wimask_1063 = &_out_wimask_T_1063; // @[RegisterRouter.scala:87:24] wire out_romask_1063 = \|_out_romask_T_1063; // @[RegisterRouter.scala:87:24] wire out_womask_1063 = &_out_womask_T_1063; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1063 = out_rivalid_1_917 & out_rimask_1063; // @[RegisterRouter.scala:87:24] wire _out_T_10292 = out_f_rivalid_1063; // @[RegisterRouter.scala:87:24] wire out_f_roready_1063 = out_roready_1_917 & out_romask_1063; // @[RegisterRouter.scala:87:24] wire _out_T_10293 = out_f_roready_1063; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1063 = out_wivalid_1_917 & out_wimask_1063; // @[RegisterRouter.scala:87:24] wire out_f_woready_1063 = out_woready_1_917 & out_womask_1063; // @[RegisterRouter.scala:87:24] wire _out_T_10294 = ~out_rimask_1063; // @[RegisterRouter.scala:87:24] wire _out_T_10295 = ~out_wimask_1063; // @[RegisterRouter.scala:87:24] wire _out_T_10296 = ~out_romask_1063; // @[RegisterRouter.scala:87:24] wire _out_T_10297 = ~out_womask_1063; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_910 = {hi_603, flags_0_go, _out_prepend_T_910}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10298 = out_prepend_910; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10299 = _out_T_10298; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_911 = _out_T_10299; // @[RegisterRouter.scala:87:24] wire out_rimask_1064 = \|_out_rimask_T_1064; // @[RegisterRouter.scala:87:24] wire out_wimask_1064 = &_out_wimask_T_1064; // @[RegisterRouter.scala:87:24] wire out_romask_1064 = \|_out_romask_T_1064; // @[RegisterRouter.scala:87:24] wire out_womask_1064 = &_out_womask_T_1064; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1064 = out_rivalid_1_918 & out_rimask_1064; // @[RegisterRouter.scala:87:24] wire _out_T_10301 = out_f_rivalid_1064; // @[RegisterRouter.scala:87:24] wire out_f_roready_1064 = out_roready_1_918 & out_romask_1064; // @[RegisterRouter.scala:87:24] wire _out_T_10302 = out_f_roready_1064; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1064 = out_wivalid_1_918 & out_wimask_1064; // @[RegisterRouter.scala:87:24] wire out_f_woready_1064 = out_woready_1_918 & out_womask_1064; // @[RegisterRouter.scala:87:24] wire _out_T_10303 = ~out_rimask_1064; // @[RegisterRouter.scala:87:24] wire _out_T_10304 = ~out_wimask_1064; // @[RegisterRouter.scala:87:24] wire _out_T_10305 = ~out_romask_1064; // @[RegisterRouter.scala:87:24] wire _out_T_10306 = ~out_womask_1064; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_911 = {hi_604, flags_0_go, _out_prepend_T_911}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10307 = out_prepend_911; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10308 = _out_T_10307; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_912 = _out_T_10308; // @[RegisterRouter.scala:87:24] wire out_rimask_1065 = \|_out_rimask_T_1065; // @[RegisterRouter.scala:87:24] wire out_wimask_1065 = &_out_wimask_T_1065; // @[RegisterRouter.scala:87:24] wire out_romask_1065 = \|_out_romask_T_1065; // @[RegisterRouter.scala:87:24] wire out_womask_1065 = &_out_womask_T_1065; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1065 = out_rivalid_1_919 & out_rimask_1065; // @[RegisterRouter.scala:87:24] wire _out_T_10310 = out_f_rivalid_1065; // @[RegisterRouter.scala:87:24] wire out_f_roready_1065 = out_roready_1_919 & out_romask_1065; // @[RegisterRouter.scala:87:24] wire _out_T_10311 = out_f_roready_1065; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1065 = out_wivalid_1_919 & out_wimask_1065; // @[RegisterRouter.scala:87:24] wire out_f_woready_1065 = out_woready_1_919 & out_womask_1065; // @[RegisterRouter.scala:87:24] wire _out_T_10312 = ~out_rimask_1065; // @[RegisterRouter.scala:87:24] wire _out_T_10313 = ~out_wimask_1065; // @[RegisterRouter.scala:87:24] wire _out_T_10314 = ~out_romask_1065; // @[RegisterRouter.scala:87:24] wire _out_T_10315 = ~out_womask_1065; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_912 = {hi_605, flags_0_go, _out_prepend_T_912}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10316 = out_prepend_912; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10317 = _out_T_10316; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_913 = _out_T_10317; // @[RegisterRouter.scala:87:24] wire out_rimask_1066 = \|_out_rimask_T_1066; // @[RegisterRouter.scala:87:24] wire out_wimask_1066 = &_out_wimask_T_1066; // @[RegisterRouter.scala:87:24] wire out_romask_1066 = \|_out_romask_T_1066; // @[RegisterRouter.scala:87:24] wire out_womask_1066 = &_out_womask_T_1066; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1066 = out_rivalid_1_920 & out_rimask_1066; // @[RegisterRouter.scala:87:24] wire _out_T_10319 = out_f_rivalid_1066; // @[RegisterRouter.scala:87:24] wire out_f_roready_1066 = out_roready_1_920 & out_romask_1066; // @[RegisterRouter.scala:87:24] wire _out_T_10320 = out_f_roready_1066; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1066 = out_wivalid_1_920 & out_wimask_1066; // @[RegisterRouter.scala:87:24] wire out_f_woready_1066 = out_woready_1_920 & out_womask_1066; // @[RegisterRouter.scala:87:24] wire _out_T_10321 = ~out_rimask_1066; // @[RegisterRouter.scala:87:24] wire _out_T_10322 = ~out_wimask_1066; // @[RegisterRouter.scala:87:24] wire _out_T_10323 = ~out_romask_1066; // @[RegisterRouter.scala:87:24] wire _out_T_10324 = ~out_womask_1066; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_913 = {hi_606, flags_0_go, _out_prepend_T_913}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10325 = out_prepend_913; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10326 = _out_T_10325; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_914 = _out_T_10326; // @[RegisterRouter.scala:87:24] wire out_rimask_1067 = \|_out_rimask_T_1067; // @[RegisterRouter.scala:87:24] wire out_wimask_1067 = &_out_wimask_T_1067; // @[RegisterRouter.scala:87:24] wire out_romask_1067 = \|_out_romask_T_1067; // @[RegisterRouter.scala:87:24] wire out_womask_1067 = &_out_womask_T_1067; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1067 = out_rivalid_1_921 & out_rimask_1067; // @[RegisterRouter.scala:87:24] wire _out_T_10328 = out_f_rivalid_1067; // @[RegisterRouter.scala:87:24] wire out_f_roready_1067 = out_roready_1_921 & out_romask_1067; // @[RegisterRouter.scala:87:24] wire _out_T_10329 = out_f_roready_1067; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1067 = out_wivalid_1_921 & out_wimask_1067; // @[RegisterRouter.scala:87:24] wire out_f_woready_1067 = out_woready_1_921 & out_womask_1067; // @[RegisterRouter.scala:87:24] wire _out_T_10330 = ~out_rimask_1067; // @[RegisterRouter.scala:87:24] wire _out_T_10331 = ~out_wimask_1067; // @[RegisterRouter.scala:87:24] wire _out_T_10332 = ~out_romask_1067; // @[RegisterRouter.scala:87:24] wire _out_T_10333 = ~out_womask_1067; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_914 = {hi_607, flags_0_go, _out_prepend_T_914}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10334 = out_prepend_914; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10335 = _out_T_10334; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_915 = _out_T_10335; // @[RegisterRouter.scala:87:24] wire out_rimask_1068 = \|_out_rimask_T_1068; // @[RegisterRouter.scala:87:24] wire out_wimask_1068 = &_out_wimask_T_1068; // @[RegisterRouter.scala:87:24] wire out_romask_1068 = \|_out_romask_T_1068; // @[RegisterRouter.scala:87:24] wire out_womask_1068 = &_out_womask_T_1068; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1068 = out_rivalid_1_922 & out_rimask_1068; // @[RegisterRouter.scala:87:24] wire _out_T_10337 = out_f_rivalid_1068; // @[RegisterRouter.scala:87:24] wire out_f_roready_1068 = out_roready_1_922 & out_romask_1068; // @[RegisterRouter.scala:87:24] wire _out_T_10338 = out_f_roready_1068; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1068 = out_wivalid_1_922 & out_wimask_1068; // @[RegisterRouter.scala:87:24] wire out_f_woready_1068 = out_woready_1_922 & out_womask_1068; // @[RegisterRouter.scala:87:24] wire _out_T_10339 = ~out_rimask_1068; // @[RegisterRouter.scala:87:24] wire _out_T_10340 = ~out_wimask_1068; // @[RegisterRouter.scala:87:24] wire _out_T_10341 = ~out_romask_1068; // @[RegisterRouter.scala:87:24] wire _out_T_10342 = ~out_womask_1068; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_915 = {hi_608, flags_0_go, _out_prepend_T_915}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10343 = out_prepend_915; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10344 = _out_T_10343; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_203 = _out_T_10344; // @[MuxLiteral.scala:49:48] wire out_rimask_1069 = \|_out_rimask_T_1069; // @[RegisterRouter.scala:87:24] wire out_wimask_1069 = &_out_wimask_T_1069; // @[RegisterRouter.scala:87:24] wire out_romask_1069 = \|_out_romask_T_1069; // @[RegisterRouter.scala:87:24] wire out_womask_1069 = &_out_womask_T_1069; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1069 = out_rivalid_1_923 & out_rimask_1069; // @[RegisterRouter.scala:87:24] wire _out_T_10346 = out_f_rivalid_1069; // @[RegisterRouter.scala:87:24] wire out_f_roready_1069 = out_roready_1_923 & out_romask_1069; // @[RegisterRouter.scala:87:24] wire _out_T_10347 = out_f_roready_1069; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1069 = out_wivalid_1_923 & out_wimask_1069; // @[RegisterRouter.scala:87:24] wire out_f_woready_1069 = out_woready_1_923 & out_womask_1069; // @[RegisterRouter.scala:87:24] wire _out_T_10348 = ~out_rimask_1069; // @[RegisterRouter.scala:87:24] wire _out_T_10349 = ~out_wimask_1069; // @[RegisterRouter.scala:87:24] wire _out_T_10350 = ~out_romask_1069; // @[RegisterRouter.scala:87:24] wire _out_T_10351 = ~out_womask_1069; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10353 = _out_T_10352; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_916 = _out_T_10353; // @[RegisterRouter.scala:87:24] wire out_rimask_1070 = \|_out_rimask_T_1070; // @[RegisterRouter.scala:87:24] wire out_wimask_1070 = &_out_wimask_T_1070; // @[RegisterRouter.scala:87:24] wire out_romask_1070 = \|_out_romask_T_1070; // @[RegisterRouter.scala:87:24] wire out_womask_1070 = &_out_womask_T_1070; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1070 = out_rivalid_1_924 & out_rimask_1070; // @[RegisterRouter.scala:87:24] wire _out_T_10355 = out_f_rivalid_1070; // @[RegisterRouter.scala:87:24] wire out_f_roready_1070 = out_roready_1_924 & out_romask_1070; // @[RegisterRouter.scala:87:24] wire _out_T_10356 = out_f_roready_1070; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1070 = out_wivalid_1_924 & out_wimask_1070; // @[RegisterRouter.scala:87:24] wire out_f_woready_1070 = out_woready_1_924 & out_womask_1070; // @[RegisterRouter.scala:87:24] wire _out_T_10357 = ~out_rimask_1070; // @[RegisterRouter.scala:87:24] wire _out_T_10358 = ~out_wimask_1070; // @[RegisterRouter.scala:87:24] wire _out_T_10359 = ~out_romask_1070; // @[RegisterRouter.scala:87:24] wire _out_T_10360 = ~out_womask_1070; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_916 = {hi_722, flags_0_go, _out_prepend_T_916}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10361 = out_prepend_916; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10362 = _out_T_10361; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_917 = _out_T_10362; // @[RegisterRouter.scala:87:24] wire out_rimask_1071 = \|_out_rimask_T_1071; // @[RegisterRouter.scala:87:24] wire out_wimask_1071 = &_out_wimask_T_1071; // @[RegisterRouter.scala:87:24] wire out_romask_1071 = \|_out_romask_T_1071; // @[RegisterRouter.scala:87:24] wire out_womask_1071 = &_out_womask_T_1071; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1071 = out_rivalid_1_925 & out_rimask_1071; // @[RegisterRouter.scala:87:24] wire _out_T_10364 = out_f_rivalid_1071; // @[RegisterRouter.scala:87:24] wire out_f_roready_1071 = out_roready_1_925 & out_romask_1071; // @[RegisterRouter.scala:87:24] wire _out_T_10365 = out_f_roready_1071; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1071 = out_wivalid_1_925 & out_wimask_1071; // @[RegisterRouter.scala:87:24] wire out_f_woready_1071 = out_woready_1_925 & out_womask_1071; // @[RegisterRouter.scala:87:24] wire _out_T_10366 = ~out_rimask_1071; // @[RegisterRouter.scala:87:24] wire _out_T_10367 = ~out_wimask_1071; // @[RegisterRouter.scala:87:24] wire _out_T_10368 = ~out_romask_1071; // @[RegisterRouter.scala:87:24] wire _out_T_10369 = ~out_womask_1071; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_917 = {hi_723, flags_0_go, _out_prepend_T_917}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10370 = out_prepend_917; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10371 = _out_T_10370; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_918 = _out_T_10371; // @[RegisterRouter.scala:87:24] wire out_rimask_1072 = \|_out_rimask_T_1072; // @[RegisterRouter.scala:87:24] wire out_wimask_1072 = &_out_wimask_T_1072; // @[RegisterRouter.scala:87:24] wire out_romask_1072 = \|_out_romask_T_1072; // @[RegisterRouter.scala:87:24] wire out_womask_1072 = &_out_womask_T_1072; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1072 = out_rivalid_1_926 & out_rimask_1072; // @[RegisterRouter.scala:87:24] wire _out_T_10373 = out_f_rivalid_1072; // @[RegisterRouter.scala:87:24] wire out_f_roready_1072 = out_roready_1_926 & out_romask_1072; // @[RegisterRouter.scala:87:24] wire _out_T_10374 = out_f_roready_1072; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1072 = out_wivalid_1_926 & out_wimask_1072; // @[RegisterRouter.scala:87:24] wire out_f_woready_1072 = out_woready_1_926 & out_womask_1072; // @[RegisterRouter.scala:87:24] wire _out_T_10375 = ~out_rimask_1072; // @[RegisterRouter.scala:87:24] wire _out_T_10376 = ~out_wimask_1072; // @[RegisterRouter.scala:87:24] wire _out_T_10377 = ~out_romask_1072; // @[RegisterRouter.scala:87:24] wire _out_T_10378 = ~out_womask_1072; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_918 = {hi_724, flags_0_go, _out_prepend_T_918}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10379 = out_prepend_918; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10380 = _out_T_10379; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_919 = _out_T_10380; // @[RegisterRouter.scala:87:24] wire out_rimask_1073 = \|_out_rimask_T_1073; // @[RegisterRouter.scala:87:24] wire out_wimask_1073 = &_out_wimask_T_1073; // @[RegisterRouter.scala:87:24] wire out_romask_1073 = \|_out_romask_T_1073; // @[RegisterRouter.scala:87:24] wire out_womask_1073 = &_out_womask_T_1073; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1073 = out_rivalid_1_927 & out_rimask_1073; // @[RegisterRouter.scala:87:24] wire _out_T_10382 = out_f_rivalid_1073; // @[RegisterRouter.scala:87:24] wire out_f_roready_1073 = out_roready_1_927 & out_romask_1073; // @[RegisterRouter.scala:87:24] wire _out_T_10383 = out_f_roready_1073; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1073 = out_wivalid_1_927 & out_wimask_1073; // @[RegisterRouter.scala:87:24] wire out_f_woready_1073 = out_woready_1_927 & out_womask_1073; // @[RegisterRouter.scala:87:24] wire _out_T_10384 = ~out_rimask_1073; // @[RegisterRouter.scala:87:24] wire _out_T_10385 = ~out_wimask_1073; // @[RegisterRouter.scala:87:24] wire _out_T_10386 = ~out_romask_1073; // @[RegisterRouter.scala:87:24] wire _out_T_10387 = ~out_womask_1073; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_919 = {hi_725, flags_0_go, _out_prepend_T_919}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10388 = out_prepend_919; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10389 = _out_T_10388; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_920 = _out_T_10389; // @[RegisterRouter.scala:87:24] wire out_rimask_1074 = \|_out_rimask_T_1074; // @[RegisterRouter.scala:87:24] wire out_wimask_1074 = &_out_wimask_T_1074; // @[RegisterRouter.scala:87:24] wire out_romask_1074 = \|_out_romask_T_1074; // @[RegisterRouter.scala:87:24] wire out_womask_1074 = &_out_womask_T_1074; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1074 = out_rivalid_1_928 & out_rimask_1074; // @[RegisterRouter.scala:87:24] wire _out_T_10391 = out_f_rivalid_1074; // @[RegisterRouter.scala:87:24] wire out_f_roready_1074 = out_roready_1_928 & out_romask_1074; // @[RegisterRouter.scala:87:24] wire _out_T_10392 = out_f_roready_1074; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1074 = out_wivalid_1_928 & out_wimask_1074; // @[RegisterRouter.scala:87:24] wire out_f_woready_1074 = out_woready_1_928 & out_womask_1074; // @[RegisterRouter.scala:87:24] wire _out_T_10393 = ~out_rimask_1074; // @[RegisterRouter.scala:87:24] wire _out_T_10394 = ~out_wimask_1074; // @[RegisterRouter.scala:87:24] wire _out_T_10395 = ~out_romask_1074; // @[RegisterRouter.scala:87:24] wire _out_T_10396 = ~out_womask_1074; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_920 = {hi_726, flags_0_go, _out_prepend_T_920}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10397 = out_prepend_920; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10398 = _out_T_10397; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_921 = _out_T_10398; // @[RegisterRouter.scala:87:24] wire out_rimask_1075 = \|_out_rimask_T_1075; // @[RegisterRouter.scala:87:24] wire out_wimask_1075 = &_out_wimask_T_1075; // @[RegisterRouter.scala:87:24] wire out_romask_1075 = \|_out_romask_T_1075; // @[RegisterRouter.scala:87:24] wire out_womask_1075 = &_out_womask_T_1075; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1075 = out_rivalid_1_929 & out_rimask_1075; // @[RegisterRouter.scala:87:24] wire _out_T_10400 = out_f_rivalid_1075; // @[RegisterRouter.scala:87:24] wire out_f_roready_1075 = out_roready_1_929 & out_romask_1075; // @[RegisterRouter.scala:87:24] wire _out_T_10401 = out_f_roready_1075; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1075 = out_wivalid_1_929 & out_wimask_1075; // @[RegisterRouter.scala:87:24] wire out_f_woready_1075 = out_woready_1_929 & out_womask_1075; // @[RegisterRouter.scala:87:24] wire _out_T_10402 = ~out_rimask_1075; // @[RegisterRouter.scala:87:24] wire _out_T_10403 = ~out_wimask_1075; // @[RegisterRouter.scala:87:24] wire _out_T_10404 = ~out_romask_1075; // @[RegisterRouter.scala:87:24] wire _out_T_10405 = ~out_womask_1075; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_921 = {hi_727, flags_0_go, _out_prepend_T_921}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10406 = out_prepend_921; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10407 = _out_T_10406; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_922 = _out_T_10407; // @[RegisterRouter.scala:87:24] wire out_rimask_1076 = \|_out_rimask_T_1076; // @[RegisterRouter.scala:87:24] wire out_wimask_1076 = &_out_wimask_T_1076; // @[RegisterRouter.scala:87:24] wire out_romask_1076 = \|_out_romask_T_1076; // @[RegisterRouter.scala:87:24] wire out_womask_1076 = &_out_womask_T_1076; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1076 = out_rivalid_1_930 & out_rimask_1076; // @[RegisterRouter.scala:87:24] wire _out_T_10409 = out_f_rivalid_1076; // @[RegisterRouter.scala:87:24] wire out_f_roready_1076 = out_roready_1_930 & out_romask_1076; // @[RegisterRouter.scala:87:24] wire _out_T_10410 = out_f_roready_1076; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1076 = out_wivalid_1_930 & out_wimask_1076; // @[RegisterRouter.scala:87:24] wire out_f_woready_1076 = out_woready_1_930 & out_womask_1076; // @[RegisterRouter.scala:87:24] wire _out_T_10411 = ~out_rimask_1076; // @[RegisterRouter.scala:87:24] wire _out_T_10412 = ~out_wimask_1076; // @[RegisterRouter.scala:87:24] wire _out_T_10413 = ~out_romask_1076; // @[RegisterRouter.scala:87:24] wire _out_T_10414 = ~out_womask_1076; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_922 = {hi_728, flags_0_go, _out_prepend_T_922}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10415 = out_prepend_922; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10416 = _out_T_10415; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_218 = _out_T_10416; // @[MuxLiteral.scala:49:48] wire out_rimask_1077 = \|_out_rimask_T_1077; // @[RegisterRouter.scala:87:24] wire out_wimask_1077 = &_out_wimask_T_1077; // @[RegisterRouter.scala:87:24] wire out_romask_1077 = \|_out_romask_T_1077; // @[RegisterRouter.scala:87:24] wire out_womask_1077 = &_out_womask_T_1077; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1077 = out_rivalid_1_931 & out_rimask_1077; // @[RegisterRouter.scala:87:24] wire _out_T_10418 = out_f_rivalid_1077; // @[RegisterRouter.scala:87:24] wire out_f_roready_1077 = out_roready_1_931 & out_romask_1077; // @[RegisterRouter.scala:87:24] wire _out_T_10419 = out_f_roready_1077; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1077 = out_wivalid_1_931 & out_wimask_1077; // @[RegisterRouter.scala:87:24] wire _out_T_10420 = out_f_wivalid_1077; // @[RegisterRouter.scala:87:24] wire out_f_woready_1077 = out_woready_1_931 & out_womask_1077; // @[RegisterRouter.scala:87:24] wire _out_T_10421 = out_f_woready_1077; // @[RegisterRouter.scala:87:24] wire _out_T_10422 = ~out_rimask_1077; // @[RegisterRouter.scala:87:24] wire _out_T_10423 = ~out_wimask_1077; // @[RegisterRouter.scala:87:24] wire _out_T_10424 = ~out_romask_1077; // @[RegisterRouter.scala:87:24] wire _out_T_10425 = ~out_womask_1077; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10427 = _out_T_10426; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_923 = _out_T_10427; // @[RegisterRouter.scala:87:24] wire out_rimask_1078 = \|_out_rimask_T_1078; // @[RegisterRouter.scala:87:24] wire out_wimask_1078 = &_out_wimask_T_1078; // @[RegisterRouter.scala:87:24] wire out_romask_1078 = \|_out_romask_T_1078; // @[RegisterRouter.scala:87:24] wire out_womask_1078 = &_out_womask_T_1078; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1078 = out_rivalid_1_932 & out_rimask_1078; // @[RegisterRouter.scala:87:24] wire _out_T_10429 = out_f_rivalid_1078; // @[RegisterRouter.scala:87:24] wire out_f_roready_1078 = out_roready_1_932 & out_romask_1078; // @[RegisterRouter.scala:87:24] wire _out_T_10430 = out_f_roready_1078; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1078 = out_wivalid_1_932 & out_wimask_1078; // @[RegisterRouter.scala:87:24] wire _out_T_10431 = out_f_wivalid_1078; // @[RegisterRouter.scala:87:24] wire out_f_woready_1078 = out_woready_1_932 & out_womask_1078; // @[RegisterRouter.scala:87:24] wire _out_T_10432 = out_f_woready_1078; // @[RegisterRouter.scala:87:24] wire _out_T_10433 = ~out_rimask_1078; // @[RegisterRouter.scala:87:24] wire _out_T_10434 = ~out_wimask_1078; // @[RegisterRouter.scala:87:24] wire _out_T_10435 = ~out_romask_1078; // @[RegisterRouter.scala:87:24] wire _out_T_10436 = ~out_womask_1078; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_923 = {programBufferMem_1, _out_prepend_T_923}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10437 = out_prepend_923; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10438 = _out_T_10437; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_924 = _out_T_10438; // @[RegisterRouter.scala:87:24] wire out_rimask_1079 = \|_out_rimask_T_1079; // @[RegisterRouter.scala:87:24] wire out_wimask_1079 = &_out_wimask_T_1079; // @[RegisterRouter.scala:87:24] wire out_romask_1079 = \|_out_romask_T_1079; // @[RegisterRouter.scala:87:24] wire out_womask_1079 = &_out_womask_T_1079; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1079 = out_rivalid_1_933 & out_rimask_1079; // @[RegisterRouter.scala:87:24] wire _out_T_10440 = out_f_rivalid_1079; // @[RegisterRouter.scala:87:24] wire out_f_roready_1079 = out_roready_1_933 & out_romask_1079; // @[RegisterRouter.scala:87:24] wire _out_T_10441 = out_f_roready_1079; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1079 = out_wivalid_1_933 & out_wimask_1079; // @[RegisterRouter.scala:87:24] wire _out_T_10442 = out_f_wivalid_1079; // @[RegisterRouter.scala:87:24] wire out_f_woready_1079 = out_woready_1_933 & out_womask_1079; // @[RegisterRouter.scala:87:24] wire _out_T_10443 = out_f_woready_1079; // @[RegisterRouter.scala:87:24] wire _out_T_10444 = ~out_rimask_1079; // @[RegisterRouter.scala:87:24] wire _out_T_10445 = ~out_wimask_1079; // @[RegisterRouter.scala:87:24] wire _out_T_10446 = ~out_romask_1079; // @[RegisterRouter.scala:87:24] wire _out_T_10447 = ~out_womask_1079; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_924 = {programBufferMem_2, _out_prepend_T_924}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10448 = out_prepend_924; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10449 = _out_T_10448; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_925 = _out_T_10449; // @[RegisterRouter.scala:87:24] wire out_rimask_1080 = \|_out_rimask_T_1080; // @[RegisterRouter.scala:87:24] wire out_wimask_1080 = &_out_wimask_T_1080; // @[RegisterRouter.scala:87:24] wire out_romask_1080 = \|_out_romask_T_1080; // @[RegisterRouter.scala:87:24] wire out_womask_1080 = &_out_womask_T_1080; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1080 = out_rivalid_1_934 & out_rimask_1080; // @[RegisterRouter.scala:87:24] wire _out_T_10451 = out_f_rivalid_1080; // @[RegisterRouter.scala:87:24] wire out_f_roready_1080 = out_roready_1_934 & out_romask_1080; // @[RegisterRouter.scala:87:24] wire _out_T_10452 = out_f_roready_1080; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1080 = out_wivalid_1_934 & out_wimask_1080; // @[RegisterRouter.scala:87:24] wire _out_T_10453 = out_f_wivalid_1080; // @[RegisterRouter.scala:87:24] wire out_f_woready_1080 = out_woready_1_934 & out_womask_1080; // @[RegisterRouter.scala:87:24] wire _out_T_10454 = out_f_woready_1080; // @[RegisterRouter.scala:87:24] wire _out_T_10455 = ~out_rimask_1080; // @[RegisterRouter.scala:87:24] wire _out_T_10456 = ~out_wimask_1080; // @[RegisterRouter.scala:87:24] wire _out_T_10457 = ~out_romask_1080; // @[RegisterRouter.scala:87:24] wire _out_T_10458 = ~out_womask_1080; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_925 = {programBufferMem_3, _out_prepend_T_925}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10459 = out_prepend_925; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10460 = _out_T_10459; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_926 = _out_T_10460; // @[RegisterRouter.scala:87:24] wire out_rimask_1081 = \|_out_rimask_T_1081; // @[RegisterRouter.scala:87:24] wire out_wimask_1081 = &_out_wimask_T_1081; // @[RegisterRouter.scala:87:24] wire out_romask_1081 = \|_out_romask_T_1081; // @[RegisterRouter.scala:87:24] wire out_womask_1081 = &_out_womask_T_1081; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1081 = out_rivalid_1_935 & out_rimask_1081; // @[RegisterRouter.scala:87:24] wire _out_T_10462 = out_f_rivalid_1081; // @[RegisterRouter.scala:87:24] wire out_f_roready_1081 = out_roready_1_935 & out_romask_1081; // @[RegisterRouter.scala:87:24] wire _out_T_10463 = out_f_roready_1081; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1081 = out_wivalid_1_935 & out_wimask_1081; // @[RegisterRouter.scala:87:24] wire _out_T_10464 = out_f_wivalid_1081; // @[RegisterRouter.scala:87:24] wire out_f_woready_1081 = out_woready_1_935 & out_womask_1081; // @[RegisterRouter.scala:87:24] wire _out_T_10465 = out_f_woready_1081; // @[RegisterRouter.scala:87:24] wire _out_T_10466 = ~out_rimask_1081; // @[RegisterRouter.scala:87:24] wire _out_T_10467 = ~out_wimask_1081; // @[RegisterRouter.scala:87:24] wire _out_T_10468 = ~out_romask_1081; // @[RegisterRouter.scala:87:24] wire _out_T_10469 = ~out_womask_1081; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_926 = {programBufferMem_4, _out_prepend_T_926}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10470 = out_prepend_926; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10471 = _out_T_10470; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_927 = _out_T_10471; // @[RegisterRouter.scala:87:24] wire out_rimask_1082 = \|_out_rimask_T_1082; // @[RegisterRouter.scala:87:24] wire out_wimask_1082 = &_out_wimask_T_1082; // @[RegisterRouter.scala:87:24] wire out_romask_1082 = \|_out_romask_T_1082; // @[RegisterRouter.scala:87:24] wire out_womask_1082 = &_out_womask_T_1082; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1082 = out_rivalid_1_936 & out_rimask_1082; // @[RegisterRouter.scala:87:24] wire _out_T_10473 = out_f_rivalid_1082; // @[RegisterRouter.scala:87:24] wire out_f_roready_1082 = out_roready_1_936 & out_romask_1082; // @[RegisterRouter.scala:87:24] wire _out_T_10474 = out_f_roready_1082; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1082 = out_wivalid_1_936 & out_wimask_1082; // @[RegisterRouter.scala:87:24] wire _out_T_10475 = out_f_wivalid_1082; // @[RegisterRouter.scala:87:24] wire out_f_woready_1082 = out_woready_1_936 & out_womask_1082; // @[RegisterRouter.scala:87:24] wire _out_T_10476 = out_f_woready_1082; // @[RegisterRouter.scala:87:24] wire _out_T_10477 = ~out_rimask_1082; // @[RegisterRouter.scala:87:24] wire _out_T_10478 = ~out_wimask_1082; // @[RegisterRouter.scala:87:24] wire _out_T_10479 = ~out_romask_1082; // @[RegisterRouter.scala:87:24] wire _out_T_10480 = ~out_womask_1082; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_927 = {programBufferMem_5, _out_prepend_T_927}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10481 = out_prepend_927; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10482 = _out_T_10481; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_928 = _out_T_10482; // @[RegisterRouter.scala:87:24] wire out_rimask_1083 = \|_out_rimask_T_1083; // @[RegisterRouter.scala:87:24] wire out_wimask_1083 = &_out_wimask_T_1083; // @[RegisterRouter.scala:87:24] wire out_romask_1083 = \|_out_romask_T_1083; // @[RegisterRouter.scala:87:24] wire out_womask_1083 = &_out_womask_T_1083; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1083 = out_rivalid_1_937 & out_rimask_1083; // @[RegisterRouter.scala:87:24] wire _out_T_10484 = out_f_rivalid_1083; // @[RegisterRouter.scala:87:24] wire out_f_roready_1083 = out_roready_1_937 & out_romask_1083; // @[RegisterRouter.scala:87:24] wire _out_T_10485 = out_f_roready_1083; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1083 = out_wivalid_1_937 & out_wimask_1083; // @[RegisterRouter.scala:87:24] wire _out_T_10486 = out_f_wivalid_1083; // @[RegisterRouter.scala:87:24] wire out_f_woready_1083 = out_woready_1_937 & out_womask_1083; // @[RegisterRouter.scala:87:24] wire _out_T_10487 = out_f_woready_1083; // @[RegisterRouter.scala:87:24] wire _out_T_10488 = ~out_rimask_1083; // @[RegisterRouter.scala:87:24] wire _out_T_10489 = ~out_wimask_1083; // @[RegisterRouter.scala:87:24] wire _out_T_10490 = ~out_romask_1083; // @[RegisterRouter.scala:87:24] wire _out_T_10491 = ~out_womask_1083; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_928 = {programBufferMem_6, _out_prepend_T_928}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10492 = out_prepend_928; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10493 = _out_T_10492; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_929 = _out_T_10493; // @[RegisterRouter.scala:87:24] wire out_rimask_1084 = \|_out_rimask_T_1084; // @[RegisterRouter.scala:87:24] wire out_wimask_1084 = &_out_wimask_T_1084; // @[RegisterRouter.scala:87:24] wire out_romask_1084 = \|_out_romask_T_1084; // @[RegisterRouter.scala:87:24] wire out_womask_1084 = &_out_womask_T_1084; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1084 = out_rivalid_1_938 & out_rimask_1084; // @[RegisterRouter.scala:87:24] wire _out_T_10495 = out_f_rivalid_1084; // @[RegisterRouter.scala:87:24] wire out_f_roready_1084 = out_roready_1_938 & out_romask_1084; // @[RegisterRouter.scala:87:24] wire _out_T_10496 = out_f_roready_1084; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1084 = out_wivalid_1_938 & out_wimask_1084; // @[RegisterRouter.scala:87:24] wire _out_T_10497 = out_f_wivalid_1084; // @[RegisterRouter.scala:87:24] wire out_f_woready_1084 = out_woready_1_938 & out_womask_1084; // @[RegisterRouter.scala:87:24] wire _out_T_10498 = out_f_woready_1084; // @[RegisterRouter.scala:87:24] wire _out_T_10499 = ~out_rimask_1084; // @[RegisterRouter.scala:87:24] wire _out_T_10500 = ~out_wimask_1084; // @[RegisterRouter.scala:87:24] wire _out_T_10501 = ~out_romask_1084; // @[RegisterRouter.scala:87:24] wire _out_T_10502 = ~out_womask_1084; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_929 = {programBufferMem_7, _out_prepend_T_929}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10503 = out_prepend_929; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10504 = _out_T_10503; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_104 = _out_T_10504; // @[MuxLiteral.scala:49:48] wire out_rimask_1085 = \|_out_rimask_T_1085; // @[RegisterRouter.scala:87:24] wire out_wimask_1085 = &_out_wimask_T_1085; // @[RegisterRouter.scala:87:24] wire out_romask_1085 = \|_out_romask_T_1085; // @[RegisterRouter.scala:87:24] wire out_womask_1085 = &_out_womask_T_1085; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1085 = out_rivalid_1_939 & out_rimask_1085; // @[RegisterRouter.scala:87:24] wire _out_T_10506 = out_f_rivalid_1085; // @[RegisterRouter.scala:87:24] wire out_f_roready_1085 = out_roready_1_939 & out_romask_1085; // @[RegisterRouter.scala:87:24] wire _out_T_10507 = out_f_roready_1085; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1085 = out_wivalid_1_939 & out_wimask_1085; // @[RegisterRouter.scala:87:24] wire out_f_woready_1085 = out_woready_1_939 & out_womask_1085; // @[RegisterRouter.scala:87:24] wire _out_T_10508 = ~out_rimask_1085; // @[RegisterRouter.scala:87:24] wire _out_T_10509 = ~out_wimask_1085; // @[RegisterRouter.scala:87:24] wire _out_T_10510 = ~out_romask_1085; // @[RegisterRouter.scala:87:24] wire _out_T_10511 = ~out_womask_1085; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10513 = _out_T_10512; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_930 = _out_T_10513; // @[RegisterRouter.scala:87:24] wire out_rimask_1086 = \|_out_rimask_T_1086; // @[RegisterRouter.scala:87:24] wire out_wimask_1086 = &_out_wimask_T_1086; // @[RegisterRouter.scala:87:24] wire out_romask_1086 = \|_out_romask_T_1086; // @[RegisterRouter.scala:87:24] wire out_womask_1086 = &_out_womask_T_1086; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1086 = out_rivalid_1_940 & out_rimask_1086; // @[RegisterRouter.scala:87:24] wire _out_T_10515 = out_f_rivalid_1086; // @[RegisterRouter.scala:87:24] wire out_f_roready_1086 = out_roready_1_940 & out_romask_1086; // @[RegisterRouter.scala:87:24] wire _out_T_10516 = out_f_roready_1086; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1086 = out_wivalid_1_940 & out_wimask_1086; // @[RegisterRouter.scala:87:24] wire out_f_woready_1086 = out_woready_1_940 & out_womask_1086; // @[RegisterRouter.scala:87:24] wire _out_T_10517 = ~out_rimask_1086; // @[RegisterRouter.scala:87:24] wire _out_T_10518 = ~out_wimask_1086; // @[RegisterRouter.scala:87:24] wire _out_T_10519 = ~out_romask_1086; // @[RegisterRouter.scala:87:24] wire _out_T_10520 = ~out_womask_1086; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_930 = {hi_978, flags_0_go, _out_prepend_T_930}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10521 = out_prepend_930; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10522 = _out_T_10521; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_931 = _out_T_10522; // @[RegisterRouter.scala:87:24] wire out_rimask_1087 = \|_out_rimask_T_1087; // @[RegisterRouter.scala:87:24] wire out_wimask_1087 = &_out_wimask_T_1087; // @[RegisterRouter.scala:87:24] wire out_romask_1087 = \|_out_romask_T_1087; // @[RegisterRouter.scala:87:24] wire out_womask_1087 = &_out_womask_T_1087; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1087 = out_rivalid_1_941 & out_rimask_1087; // @[RegisterRouter.scala:87:24] wire _out_T_10524 = out_f_rivalid_1087; // @[RegisterRouter.scala:87:24] wire out_f_roready_1087 = out_roready_1_941 & out_romask_1087; // @[RegisterRouter.scala:87:24] wire _out_T_10525 = out_f_roready_1087; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1087 = out_wivalid_1_941 & out_wimask_1087; // @[RegisterRouter.scala:87:24] wire out_f_woready_1087 = out_woready_1_941 & out_womask_1087; // @[RegisterRouter.scala:87:24] wire _out_T_10526 = ~out_rimask_1087; // @[RegisterRouter.scala:87:24] wire _out_T_10527 = ~out_wimask_1087; // @[RegisterRouter.scala:87:24] wire _out_T_10528 = ~out_romask_1087; // @[RegisterRouter.scala:87:24] wire _out_T_10529 = ~out_womask_1087; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_931 = {hi_979, flags_0_go, _out_prepend_T_931}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10530 = out_prepend_931; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10531 = _out_T_10530; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_932 = _out_T_10531; // @[RegisterRouter.scala:87:24] wire out_rimask_1088 = \|_out_rimask_T_1088; // @[RegisterRouter.scala:87:24] wire out_wimask_1088 = &_out_wimask_T_1088; // @[RegisterRouter.scala:87:24] wire out_romask_1088 = \|_out_romask_T_1088; // @[RegisterRouter.scala:87:24] wire out_womask_1088 = &_out_womask_T_1088; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1088 = out_rivalid_1_942 & out_rimask_1088; // @[RegisterRouter.scala:87:24] wire _out_T_10533 = out_f_rivalid_1088; // @[RegisterRouter.scala:87:24] wire out_f_roready_1088 = out_roready_1_942 & out_romask_1088; // @[RegisterRouter.scala:87:24] wire _out_T_10534 = out_f_roready_1088; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1088 = out_wivalid_1_942 & out_wimask_1088; // @[RegisterRouter.scala:87:24] wire out_f_woready_1088 = out_woready_1_942 & out_womask_1088; // @[RegisterRouter.scala:87:24] wire _out_T_10535 = ~out_rimask_1088; // @[RegisterRouter.scala:87:24] wire _out_T_10536 = ~out_wimask_1088; // @[RegisterRouter.scala:87:24] wire _out_T_10537 = ~out_romask_1088; // @[RegisterRouter.scala:87:24] wire _out_T_10538 = ~out_womask_1088; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_932 = {hi_980, flags_0_go, _out_prepend_T_932}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10539 = out_prepend_932; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10540 = _out_T_10539; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_933 = _out_T_10540; // @[RegisterRouter.scala:87:24] wire out_rimask_1089 = \|_out_rimask_T_1089; // @[RegisterRouter.scala:87:24] wire out_wimask_1089 = &_out_wimask_T_1089; // @[RegisterRouter.scala:87:24] wire out_romask_1089 = \|_out_romask_T_1089; // @[RegisterRouter.scala:87:24] wire out_womask_1089 = &_out_womask_T_1089; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1089 = out_rivalid_1_943 & out_rimask_1089; // @[RegisterRouter.scala:87:24] wire _out_T_10542 = out_f_rivalid_1089; // @[RegisterRouter.scala:87:24] wire out_f_roready_1089 = out_roready_1_943 & out_romask_1089; // @[RegisterRouter.scala:87:24] wire _out_T_10543 = out_f_roready_1089; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1089 = out_wivalid_1_943 & out_wimask_1089; // @[RegisterRouter.scala:87:24] wire out_f_woready_1089 = out_woready_1_943 & out_womask_1089; // @[RegisterRouter.scala:87:24] wire _out_T_10544 = ~out_rimask_1089; // @[RegisterRouter.scala:87:24] wire _out_T_10545 = ~out_wimask_1089; // @[RegisterRouter.scala:87:24] wire _out_T_10546 = ~out_romask_1089; // @[RegisterRouter.scala:87:24] wire _out_T_10547 = ~out_womask_1089; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_933 = {hi_981, flags_0_go, _out_prepend_T_933}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10548 = out_prepend_933; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10549 = _out_T_10548; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_934 = _out_T_10549; // @[RegisterRouter.scala:87:24] wire out_rimask_1090 = \|_out_rimask_T_1090; // @[RegisterRouter.scala:87:24] wire out_wimask_1090 = &_out_wimask_T_1090; // @[RegisterRouter.scala:87:24] wire out_romask_1090 = \|_out_romask_T_1090; // @[RegisterRouter.scala:87:24] wire out_womask_1090 = &_out_womask_T_1090; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1090 = out_rivalid_1_944 & out_rimask_1090; // @[RegisterRouter.scala:87:24] wire _out_T_10551 = out_f_rivalid_1090; // @[RegisterRouter.scala:87:24] wire out_f_roready_1090 = out_roready_1_944 & out_romask_1090; // @[RegisterRouter.scala:87:24] wire _out_T_10552 = out_f_roready_1090; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1090 = out_wivalid_1_944 & out_wimask_1090; // @[RegisterRouter.scala:87:24] wire out_f_woready_1090 = out_woready_1_944 & out_womask_1090; // @[RegisterRouter.scala:87:24] wire _out_T_10553 = ~out_rimask_1090; // @[RegisterRouter.scala:87:24] wire _out_T_10554 = ~out_wimask_1090; // @[RegisterRouter.scala:87:24] wire _out_T_10555 = ~out_romask_1090; // @[RegisterRouter.scala:87:24] wire _out_T_10556 = ~out_womask_1090; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_934 = {hi_982, flags_0_go, _out_prepend_T_934}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10557 = out_prepend_934; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10558 = _out_T_10557; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_935 = _out_T_10558; // @[RegisterRouter.scala:87:24] wire out_rimask_1091 = \|_out_rimask_T_1091; // @[RegisterRouter.scala:87:24] wire out_wimask_1091 = &_out_wimask_T_1091; // @[RegisterRouter.scala:87:24] wire out_romask_1091 = \|_out_romask_T_1091; // @[RegisterRouter.scala:87:24] wire out_womask_1091 = &_out_womask_T_1091; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1091 = out_rivalid_1_945 & out_rimask_1091; // @[RegisterRouter.scala:87:24] wire _out_T_10560 = out_f_rivalid_1091; // @[RegisterRouter.scala:87:24] wire out_f_roready_1091 = out_roready_1_945 & out_romask_1091; // @[RegisterRouter.scala:87:24] wire _out_T_10561 = out_f_roready_1091; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1091 = out_wivalid_1_945 & out_wimask_1091; // @[RegisterRouter.scala:87:24] wire out_f_woready_1091 = out_woready_1_945 & out_womask_1091; // @[RegisterRouter.scala:87:24] wire _out_T_10562 = ~out_rimask_1091; // @[RegisterRouter.scala:87:24] wire _out_T_10563 = ~out_wimask_1091; // @[RegisterRouter.scala:87:24] wire _out_T_10564 = ~out_romask_1091; // @[RegisterRouter.scala:87:24] wire _out_T_10565 = ~out_womask_1091; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_935 = {hi_983, flags_0_go, _out_prepend_T_935}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10566 = out_prepend_935; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10567 = _out_T_10566; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_936 = _out_T_10567; // @[RegisterRouter.scala:87:24] wire out_rimask_1092 = \|_out_rimask_T_1092; // @[RegisterRouter.scala:87:24] wire out_wimask_1092 = &_out_wimask_T_1092; // @[RegisterRouter.scala:87:24] wire out_romask_1092 = \|_out_romask_T_1092; // @[RegisterRouter.scala:87:24] wire out_womask_1092 = &_out_womask_T_1092; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1092 = out_rivalid_1_946 & out_rimask_1092; // @[RegisterRouter.scala:87:24] wire _out_T_10569 = out_f_rivalid_1092; // @[RegisterRouter.scala:87:24] wire out_f_roready_1092 = out_roready_1_946 & out_romask_1092; // @[RegisterRouter.scala:87:24] wire _out_T_10570 = out_f_roready_1092; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1092 = out_wivalid_1_946 & out_wimask_1092; // @[RegisterRouter.scala:87:24] wire out_f_woready_1092 = out_woready_1_946 & out_womask_1092; // @[RegisterRouter.scala:87:24] wire _out_T_10571 = ~out_rimask_1092; // @[RegisterRouter.scala:87:24] wire _out_T_10572 = ~out_wimask_1092; // @[RegisterRouter.scala:87:24] wire _out_T_10573 = ~out_romask_1092; // @[RegisterRouter.scala:87:24] wire _out_T_10574 = ~out_womask_1092; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_936 = {hi_984, flags_0_go, _out_prepend_T_936}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10575 = out_prepend_936; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10576 = _out_T_10575; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_250 = _out_T_10576; // @[MuxLiteral.scala:49:48] wire out_rimask_1093 = \|_out_rimask_T_1093; // @[RegisterRouter.scala:87:24] wire out_wimask_1093 = &_out_wimask_T_1093; // @[RegisterRouter.scala:87:24] wire out_romask_1093 = \|_out_romask_T_1093; // @[RegisterRouter.scala:87:24] wire out_womask_1093 = &_out_womask_T_1093; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1093 = out_rivalid_1_947 & out_rimask_1093; // @[RegisterRouter.scala:87:24] wire _out_T_10578 = out_f_rivalid_1093; // @[RegisterRouter.scala:87:24] wire out_f_roready_1093 = out_roready_1_947 & out_romask_1093; // @[RegisterRouter.scala:87:24] wire _out_T_10579 = out_f_roready_1093; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1093 = out_wivalid_1_947 & out_wimask_1093; // @[RegisterRouter.scala:87:24] wire out_f_woready_1093 = out_woready_1_947 & out_womask_1093; // @[RegisterRouter.scala:87:24] wire _out_T_10580 = ~out_rimask_1093; // @[RegisterRouter.scala:87:24] wire _out_T_10581 = ~out_wimask_1093; // @[RegisterRouter.scala:87:24] wire _out_T_10582 = ~out_romask_1093; // @[RegisterRouter.scala:87:24] wire _out_T_10583 = ~out_womask_1093; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10585 = _out_T_10584; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_937 = _out_T_10585; // @[RegisterRouter.scala:87:24] wire out_rimask_1094 = \|_out_rimask_T_1094; // @[RegisterRouter.scala:87:24] wire out_wimask_1094 = &_out_wimask_T_1094; // @[RegisterRouter.scala:87:24] wire out_romask_1094 = \|_out_romask_T_1094; // @[RegisterRouter.scala:87:24] wire out_womask_1094 = &_out_womask_T_1094; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1094 = out_rivalid_1_948 & out_rimask_1094; // @[RegisterRouter.scala:87:24] wire _out_T_10587 = out_f_rivalid_1094; // @[RegisterRouter.scala:87:24] wire out_f_roready_1094 = out_roready_1_948 & out_romask_1094; // @[RegisterRouter.scala:87:24] wire _out_T_10588 = out_f_roready_1094; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1094 = out_wivalid_1_948 & out_wimask_1094; // @[RegisterRouter.scala:87:24] wire out_f_woready_1094 = out_woready_1_948 & out_womask_1094; // @[RegisterRouter.scala:87:24] wire _out_T_10589 = ~out_rimask_1094; // @[RegisterRouter.scala:87:24] wire _out_T_10590 = ~out_wimask_1094; // @[RegisterRouter.scala:87:24] wire _out_T_10591 = ~out_romask_1094; // @[RegisterRouter.scala:87:24] wire _out_T_10592 = ~out_womask_1094; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_937 = {hi_826, flags_0_go, _out_prepend_T_937}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10593 = out_prepend_937; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10594 = _out_T_10593; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_938 = _out_T_10594; // @[RegisterRouter.scala:87:24] wire out_rimask_1095 = \|_out_rimask_T_1095; // @[RegisterRouter.scala:87:24] wire out_wimask_1095 = &_out_wimask_T_1095; // @[RegisterRouter.scala:87:24] wire out_romask_1095 = \|_out_romask_T_1095; // @[RegisterRouter.scala:87:24] wire out_womask_1095 = &_out_womask_T_1095; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1095 = out_rivalid_1_949 & out_rimask_1095; // @[RegisterRouter.scala:87:24] wire _out_T_10596 = out_f_rivalid_1095; // @[RegisterRouter.scala:87:24] wire out_f_roready_1095 = out_roready_1_949 & out_romask_1095; // @[RegisterRouter.scala:87:24] wire _out_T_10597 = out_f_roready_1095; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1095 = out_wivalid_1_949 & out_wimask_1095; // @[RegisterRouter.scala:87:24] wire out_f_woready_1095 = out_woready_1_949 & out_womask_1095; // @[RegisterRouter.scala:87:24] wire _out_T_10598 = ~out_rimask_1095; // @[RegisterRouter.scala:87:24] wire _out_T_10599 = ~out_wimask_1095; // @[RegisterRouter.scala:87:24] wire _out_T_10600 = ~out_romask_1095; // @[RegisterRouter.scala:87:24] wire _out_T_10601 = ~out_womask_1095; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_938 = {hi_827, flags_0_go, _out_prepend_T_938}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10602 = out_prepend_938; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10603 = _out_T_10602; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_939 = _out_T_10603; // @[RegisterRouter.scala:87:24] wire out_rimask_1096 = \|_out_rimask_T_1096; // @[RegisterRouter.scala:87:24] wire out_wimask_1096 = &_out_wimask_T_1096; // @[RegisterRouter.scala:87:24] wire out_romask_1096 = \|_out_romask_T_1096; // @[RegisterRouter.scala:87:24] wire out_womask_1096 = &_out_womask_T_1096; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1096 = out_rivalid_1_950 & out_rimask_1096; // @[RegisterRouter.scala:87:24] wire _out_T_10605 = out_f_rivalid_1096; // @[RegisterRouter.scala:87:24] wire out_f_roready_1096 = out_roready_1_950 & out_romask_1096; // @[RegisterRouter.scala:87:24] wire _out_T_10606 = out_f_roready_1096; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1096 = out_wivalid_1_950 & out_wimask_1096; // @[RegisterRouter.scala:87:24] wire out_f_woready_1096 = out_woready_1_950 & out_womask_1096; // @[RegisterRouter.scala:87:24] wire _out_T_10607 = ~out_rimask_1096; // @[RegisterRouter.scala:87:24] wire _out_T_10608 = ~out_wimask_1096; // @[RegisterRouter.scala:87:24] wire _out_T_10609 = ~out_romask_1096; // @[RegisterRouter.scala:87:24] wire _out_T_10610 = ~out_womask_1096; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_939 = {hi_828, flags_0_go, _out_prepend_T_939}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10611 = out_prepend_939; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10612 = _out_T_10611; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_940 = _out_T_10612; // @[RegisterRouter.scala:87:24] wire out_rimask_1097 = \|_out_rimask_T_1097; // @[RegisterRouter.scala:87:24] wire out_wimask_1097 = &_out_wimask_T_1097; // @[RegisterRouter.scala:87:24] wire out_romask_1097 = \|_out_romask_T_1097; // @[RegisterRouter.scala:87:24] wire out_womask_1097 = &_out_womask_T_1097; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1097 = out_rivalid_1_951 & out_rimask_1097; // @[RegisterRouter.scala:87:24] wire _out_T_10614 = out_f_rivalid_1097; // @[RegisterRouter.scala:87:24] wire out_f_roready_1097 = out_roready_1_951 & out_romask_1097; // @[RegisterRouter.scala:87:24] wire _out_T_10615 = out_f_roready_1097; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1097 = out_wivalid_1_951 & out_wimask_1097; // @[RegisterRouter.scala:87:24] wire out_f_woready_1097 = out_woready_1_951 & out_womask_1097; // @[RegisterRouter.scala:87:24] wire _out_T_10616 = ~out_rimask_1097; // @[RegisterRouter.scala:87:24] wire _out_T_10617 = ~out_wimask_1097; // @[RegisterRouter.scala:87:24] wire _out_T_10618 = ~out_romask_1097; // @[RegisterRouter.scala:87:24] wire _out_T_10619 = ~out_womask_1097; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_940 = {hi_829, flags_0_go, _out_prepend_T_940}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10620 = out_prepend_940; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10621 = _out_T_10620; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_941 = _out_T_10621; // @[RegisterRouter.scala:87:24] wire out_rimask_1098 = \|_out_rimask_T_1098; // @[RegisterRouter.scala:87:24] wire out_wimask_1098 = &_out_wimask_T_1098; // @[RegisterRouter.scala:87:24] wire out_romask_1098 = \|_out_romask_T_1098; // @[RegisterRouter.scala:87:24] wire out_womask_1098 = &_out_womask_T_1098; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1098 = out_rivalid_1_952 & out_rimask_1098; // @[RegisterRouter.scala:87:24] wire _out_T_10623 = out_f_rivalid_1098; // @[RegisterRouter.scala:87:24] wire out_f_roready_1098 = out_roready_1_952 & out_romask_1098; // @[RegisterRouter.scala:87:24] wire _out_T_10624 = out_f_roready_1098; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1098 = out_wivalid_1_952 & out_wimask_1098; // @[RegisterRouter.scala:87:24] wire out_f_woready_1098 = out_woready_1_952 & out_womask_1098; // @[RegisterRouter.scala:87:24] wire _out_T_10625 = ~out_rimask_1098; // @[RegisterRouter.scala:87:24] wire _out_T_10626 = ~out_wimask_1098; // @[RegisterRouter.scala:87:24] wire _out_T_10627 = ~out_romask_1098; // @[RegisterRouter.scala:87:24] wire _out_T_10628 = ~out_womask_1098; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_941 = {hi_830, flags_0_go, _out_prepend_T_941}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10629 = out_prepend_941; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10630 = _out_T_10629; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_942 = _out_T_10630; // @[RegisterRouter.scala:87:24] wire out_rimask_1099 = \|_out_rimask_T_1099; // @[RegisterRouter.scala:87:24] wire out_wimask_1099 = &_out_wimask_T_1099; // @[RegisterRouter.scala:87:24] wire out_romask_1099 = \|_out_romask_T_1099; // @[RegisterRouter.scala:87:24] wire out_womask_1099 = &_out_womask_T_1099; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1099 = out_rivalid_1_953 & out_rimask_1099; // @[RegisterRouter.scala:87:24] wire _out_T_10632 = out_f_rivalid_1099; // @[RegisterRouter.scala:87:24] wire out_f_roready_1099 = out_roready_1_953 & out_romask_1099; // @[RegisterRouter.scala:87:24] wire _out_T_10633 = out_f_roready_1099; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1099 = out_wivalid_1_953 & out_wimask_1099; // @[RegisterRouter.scala:87:24] wire out_f_woready_1099 = out_woready_1_953 & out_womask_1099; // @[RegisterRouter.scala:87:24] wire _out_T_10634 = ~out_rimask_1099; // @[RegisterRouter.scala:87:24] wire _out_T_10635 = ~out_wimask_1099; // @[RegisterRouter.scala:87:24] wire _out_T_10636 = ~out_romask_1099; // @[RegisterRouter.scala:87:24] wire _out_T_10637 = ~out_womask_1099; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_942 = {hi_831, flags_0_go, _out_prepend_T_942}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10638 = out_prepend_942; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10639 = _out_T_10638; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_943 = _out_T_10639; // @[RegisterRouter.scala:87:24] wire out_rimask_1100 = \|_out_rimask_T_1100; // @[RegisterRouter.scala:87:24] wire out_wimask_1100 = &_out_wimask_T_1100; // @[RegisterRouter.scala:87:24] wire out_romask_1100 = \|_out_romask_T_1100; // @[RegisterRouter.scala:87:24] wire out_womask_1100 = &_out_womask_T_1100; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1100 = out_rivalid_1_954 & out_rimask_1100; // @[RegisterRouter.scala:87:24] wire _out_T_10641 = out_f_rivalid_1100; // @[RegisterRouter.scala:87:24] wire out_f_roready_1100 = out_roready_1_954 & out_romask_1100; // @[RegisterRouter.scala:87:24] wire _out_T_10642 = out_f_roready_1100; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1100 = out_wivalid_1_954 & out_wimask_1100; // @[RegisterRouter.scala:87:24] wire out_f_woready_1100 = out_woready_1_954 & out_womask_1100; // @[RegisterRouter.scala:87:24] wire _out_T_10643 = ~out_rimask_1100; // @[RegisterRouter.scala:87:24] wire _out_T_10644 = ~out_wimask_1100; // @[RegisterRouter.scala:87:24] wire _out_T_10645 = ~out_romask_1100; // @[RegisterRouter.scala:87:24] wire _out_T_10646 = ~out_womask_1100; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_943 = {hi_832, flags_0_go, _out_prepend_T_943}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10647 = out_prepend_943; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10648 = _out_T_10647; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_231 = _out_T_10648; // @[MuxLiteral.scala:49:48] wire out_rimask_1101 = \|_out_rimask_T_1101; // @[RegisterRouter.scala:87:24] wire out_wimask_1101 = &_out_wimask_T_1101; // @[RegisterRouter.scala:87:24] wire out_romask_1101 = \|_out_romask_T_1101; // @[RegisterRouter.scala:87:24] wire out_womask_1101 = &_out_womask_T_1101; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1101 = out_rivalid_1_955 & out_rimask_1101; // @[RegisterRouter.scala:87:24] wire _out_T_10650 = out_f_rivalid_1101; // @[RegisterRouter.scala:87:24] wire out_f_roready_1101 = out_roready_1_955 & out_romask_1101; // @[RegisterRouter.scala:87:24] wire _out_T_10651 = out_f_roready_1101; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1101 = out_wivalid_1_955 & out_wimask_1101; // @[RegisterRouter.scala:87:24] wire out_f_woready_1101 = out_woready_1_955 & out_womask_1101; // @[RegisterRouter.scala:87:24] wire _out_T_10652 = ~out_rimask_1101; // @[RegisterRouter.scala:87:24] wire _out_T_10653 = ~out_wimask_1101; // @[RegisterRouter.scala:87:24] wire _out_T_10654 = ~out_romask_1101; // @[RegisterRouter.scala:87:24] wire _out_T_10655 = ~out_womask_1101; // @[RegisterRouter.scala:87:24] wire out_rimask_1102 = \|_out_rimask_T_1102; // @[RegisterRouter.scala:87:24] wire out_wimask_1102 = &_out_wimask_T_1102; // @[RegisterRouter.scala:87:24] wire out_romask_1102 = \|_out_romask_T_1102; // @[RegisterRouter.scala:87:24] wire out_womask_1102 = &_out_womask_T_1102; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1102 = out_rivalid_1_956 & out_rimask_1102; // @[RegisterRouter.scala:87:24] wire _out_T_10659 = out_f_rivalid_1102; // @[RegisterRouter.scala:87:24] wire out_f_roready_1102 = out_roready_1_956 & out_romask_1102; // @[RegisterRouter.scala:87:24] wire _out_T_10660 = out_f_roready_1102; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1102 = out_wivalid_1_956 & out_wimask_1102; // @[RegisterRouter.scala:87:24] wire out_f_woready_1102 = out_woready_1_956 & out_womask_1102; // @[RegisterRouter.scala:87:24] wire _out_T_10661 = ~out_rimask_1102; // @[RegisterRouter.scala:87:24] wire _out_T_10662 = ~out_wimask_1102; // @[RegisterRouter.scala:87:24] wire _out_T_10663 = ~out_romask_1102; // @[RegisterRouter.scala:87:24] wire _out_T_10664 = ~out_womask_1102; // @[RegisterRouter.scala:87:24] wire out_rimask_1103 = \|_out_rimask_T_1103; // @[RegisterRouter.scala:87:24] wire out_wimask_1103 = &_out_wimask_T_1103; // @[RegisterRouter.scala:87:24] wire out_romask_1103 = \|_out_romask_T_1103; // @[RegisterRouter.scala:87:24] wire out_womask_1103 = &_out_womask_T_1103; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1103 = out_rivalid_1_957 & out_rimask_1103; // @[RegisterRouter.scala:87:24] wire _out_T_10668 = out_f_rivalid_1103; // @[RegisterRouter.scala:87:24] wire out_f_roready_1103 = out_roready_1_957 & out_romask_1103; // @[RegisterRouter.scala:87:24] wire _out_T_10669 = out_f_roready_1103; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1103 = out_wivalid_1_957 & out_wimask_1103; // @[RegisterRouter.scala:87:24] wire out_f_woready_1103 = out_woready_1_957 & out_womask_1103; // @[RegisterRouter.scala:87:24] wire _out_T_10670 = ~out_rimask_1103; // @[RegisterRouter.scala:87:24] wire _out_T_10671 = ~out_wimask_1103; // @[RegisterRouter.scala:87:24] wire _out_T_10672 = ~out_romask_1103; // @[RegisterRouter.scala:87:24] wire _out_T_10673 = ~out_womask_1103; // @[RegisterRouter.scala:87:24] wire out_rimask_1104 = \|_out_rimask_T_1104; // @[RegisterRouter.scala:87:24] wire out_wimask_1104 = &_out_wimask_T_1104; // @[RegisterRouter.scala:87:24] wire out_romask_1104 = \|_out_romask_T_1104; // @[RegisterRouter.scala:87:24] wire out_womask_1104 = &_out_womask_T_1104; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1104 = out_rivalid_1_958 & out_rimask_1104; // @[RegisterRouter.scala:87:24] wire _out_T_10677 = out_f_rivalid_1104; // @[RegisterRouter.scala:87:24] wire out_f_roready_1104 = out_roready_1_958 & out_romask_1104; // @[RegisterRouter.scala:87:24] wire _out_T_10678 = out_f_roready_1104; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1104 = out_wivalid_1_958 & out_wimask_1104; // @[RegisterRouter.scala:87:24] wire out_f_woready_1104 = out_woready_1_958 & out_womask_1104; // @[RegisterRouter.scala:87:24] wire _out_T_10679 = ~out_rimask_1104; // @[RegisterRouter.scala:87:24] wire _out_T_10680 = ~out_wimask_1104; // @[RegisterRouter.scala:87:24] wire _out_T_10681 = ~out_romask_1104; // @[RegisterRouter.scala:87:24] wire _out_T_10682 = ~out_womask_1104; // @[RegisterRouter.scala:87:24] wire out_rimask_1105 = \|_out_rimask_T_1105; // @[RegisterRouter.scala:87:24] wire out_wimask_1105 = &_out_wimask_T_1105; // @[RegisterRouter.scala:87:24] wire out_romask_1105 = \|_out_romask_T_1105; // @[RegisterRouter.scala:87:24] wire out_womask_1105 = &_out_womask_T_1105; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1105 = out_rivalid_1_959 & out_rimask_1105; // @[RegisterRouter.scala:87:24] wire _out_T_10686 = out_f_rivalid_1105; // @[RegisterRouter.scala:87:24] wire out_f_roready_1105 = out_roready_1_959 & out_romask_1105; // @[RegisterRouter.scala:87:24] wire _out_T_10687 = out_f_roready_1105; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1105 = out_wivalid_1_959 & out_wimask_1105; // @[RegisterRouter.scala:87:24] wire out_f_woready_1105 = out_woready_1_959 & out_womask_1105; // @[RegisterRouter.scala:87:24] wire _out_T_10688 = ~out_rimask_1105; // @[RegisterRouter.scala:87:24] wire _out_T_10689 = ~out_wimask_1105; // @[RegisterRouter.scala:87:24] wire _out_T_10690 = ~out_romask_1105; // @[RegisterRouter.scala:87:24] wire _out_T_10691 = ~out_womask_1105; // @[RegisterRouter.scala:87:24] wire out_rimask_1106 = \|_out_rimask_T_1106; // @[RegisterRouter.scala:87:24] wire out_wimask_1106 = &_out_wimask_T_1106; // @[RegisterRouter.scala:87:24] wire out_romask_1106 = \|_out_romask_T_1106; // @[RegisterRouter.scala:87:24] wire out_womask_1106 = &_out_womask_T_1106; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1106 = out_rivalid_1_960 & out_rimask_1106; // @[RegisterRouter.scala:87:24] wire _out_T_10695 = out_f_rivalid_1106; // @[RegisterRouter.scala:87:24] wire out_f_roready_1106 = out_roready_1_960 & out_romask_1106; // @[RegisterRouter.scala:87:24] wire _out_T_10696 = out_f_roready_1106; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1106 = out_wivalid_1_960 & out_wimask_1106; // @[RegisterRouter.scala:87:24] wire out_f_woready_1106 = out_woready_1_960 & out_womask_1106; // @[RegisterRouter.scala:87:24] wire _out_T_10697 = ~out_rimask_1106; // @[RegisterRouter.scala:87:24] wire _out_T_10698 = ~out_wimask_1106; // @[RegisterRouter.scala:87:24] wire _out_T_10699 = ~out_romask_1106; // @[RegisterRouter.scala:87:24] wire _out_T_10700 = ~out_womask_1106; // @[RegisterRouter.scala:87:24] wire out_rimask_1107 = \|_out_rimask_T_1107; // @[RegisterRouter.scala:87:24] wire out_wimask_1107 = &_out_wimask_T_1107; // @[RegisterRouter.scala:87:24] wire out_romask_1107 = \|_out_romask_T_1107; // @[RegisterRouter.scala:87:24] wire out_womask_1107 = &_out_womask_T_1107; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1107 = out_rivalid_1_961 & out_rimask_1107; // @[RegisterRouter.scala:87:24] wire _out_T_10704 = out_f_rivalid_1107; // @[RegisterRouter.scala:87:24] wire out_f_roready_1107 = out_roready_1_961 & out_romask_1107; // @[RegisterRouter.scala:87:24] wire _out_T_10705 = out_f_roready_1107; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1107 = out_wivalid_1_961 & out_wimask_1107; // @[RegisterRouter.scala:87:24] wire out_f_woready_1107 = out_woready_1_961 & out_womask_1107; // @[RegisterRouter.scala:87:24] wire _out_T_10706 = ~out_rimask_1107; // @[RegisterRouter.scala:87:24] wire _out_T_10707 = ~out_wimask_1107; // @[RegisterRouter.scala:87:24] wire _out_T_10708 = ~out_romask_1107; // @[RegisterRouter.scala:87:24] wire _out_T_10709 = ~out_womask_1107; // @[RegisterRouter.scala:87:24] wire out_rimask_1108 = \|_out_rimask_T_1108; // @[RegisterRouter.scala:87:24] wire out_wimask_1108 = &_out_wimask_T_1108; // @[RegisterRouter.scala:87:24] wire out_romask_1108 = \|_out_romask_T_1108; // @[RegisterRouter.scala:87:24] wire out_womask_1108 = &_out_womask_T_1108; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1108 = out_rivalid_1_962 & out_rimask_1108; // @[RegisterRouter.scala:87:24] wire _out_T_10713 = out_f_rivalid_1108; // @[RegisterRouter.scala:87:24] wire out_f_roready_1108 = out_roready_1_962 & out_romask_1108; // @[RegisterRouter.scala:87:24] wire _out_T_10714 = out_f_roready_1108; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1108 = out_wivalid_1_962 & out_wimask_1108; // @[RegisterRouter.scala:87:24] wire out_f_woready_1108 = out_woready_1_962 & out_womask_1108; // @[RegisterRouter.scala:87:24] wire _out_T_10715 = ~out_rimask_1108; // @[RegisterRouter.scala:87:24] wire _out_T_10716 = ~out_wimask_1108; // @[RegisterRouter.scala:87:24] wire _out_T_10717 = ~out_romask_1108; // @[RegisterRouter.scala:87:24] wire _out_T_10718 = ~out_womask_1108; // @[RegisterRouter.scala:87:24] wire out_rimask_1109 = \|_out_rimask_T_1109; // @[RegisterRouter.scala:87:24] wire out_wimask_1109 = &_out_wimask_T_1109; // @[RegisterRouter.scala:87:24] wire out_romask_1109 = \|_out_romask_T_1109; // @[RegisterRouter.scala:87:24] wire out_womask_1109 = &_out_womask_T_1109; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1109 = out_rivalid_1_963 & out_rimask_1109; // @[RegisterRouter.scala:87:24] wire _out_T_10722 = out_f_rivalid_1109; // @[RegisterRouter.scala:87:24] wire out_f_roready_1109 = out_roready_1_963 & out_romask_1109; // @[RegisterRouter.scala:87:24] wire _out_T_10723 = out_f_roready_1109; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1109 = out_wivalid_1_963 & out_wimask_1109; // @[RegisterRouter.scala:87:24] wire out_f_woready_1109 = out_woready_1_963 & out_womask_1109; // @[RegisterRouter.scala:87:24] wire _out_T_10724 = ~out_rimask_1109; // @[RegisterRouter.scala:87:24] wire _out_T_10725 = ~out_wimask_1109; // @[RegisterRouter.scala:87:24] wire _out_T_10726 = ~out_romask_1109; // @[RegisterRouter.scala:87:24] wire _out_T_10727 = ~out_womask_1109; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10729 = _out_T_10728; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_951 = _out_T_10729; // @[RegisterRouter.scala:87:24] wire out_rimask_1110 = \|_out_rimask_T_1110; // @[RegisterRouter.scala:87:24] wire out_wimask_1110 = &_out_wimask_T_1110; // @[RegisterRouter.scala:87:24] wire out_romask_1110 = \|_out_romask_T_1110; // @[RegisterRouter.scala:87:24] wire out_womask_1110 = &_out_womask_T_1110; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1110 = out_rivalid_1_964 & out_rimask_1110; // @[RegisterRouter.scala:87:24] wire _out_T_10731 = out_f_rivalid_1110; // @[RegisterRouter.scala:87:24] wire out_f_roready_1110 = out_roready_1_964 & out_romask_1110; // @[RegisterRouter.scala:87:24] wire _out_T_10732 = out_f_roready_1110; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1110 = out_wivalid_1_964 & out_wimask_1110; // @[RegisterRouter.scala:87:24] wire out_f_woready_1110 = out_woready_1_964 & out_womask_1110; // @[RegisterRouter.scala:87:24] wire _out_T_10733 = ~out_rimask_1110; // @[RegisterRouter.scala:87:24] wire _out_T_10734 = ~out_wimask_1110; // @[RegisterRouter.scala:87:24] wire _out_T_10735 = ~out_romask_1110; // @[RegisterRouter.scala:87:24] wire _out_T_10736 = ~out_womask_1110; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_951 = {hi_242, flags_0_go, _out_prepend_T_951}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10737 = out_prepend_951; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10738 = _out_T_10737; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_952 = _out_T_10738; // @[RegisterRouter.scala:87:24] wire out_rimask_1111 = \|_out_rimask_T_1111; // @[RegisterRouter.scala:87:24] wire out_wimask_1111 = &_out_wimask_T_1111; // @[RegisterRouter.scala:87:24] wire out_romask_1111 = \|_out_romask_T_1111; // @[RegisterRouter.scala:87:24] wire out_womask_1111 = &_out_womask_T_1111; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1111 = out_rivalid_1_965 & out_rimask_1111; // @[RegisterRouter.scala:87:24] wire _out_T_10740 = out_f_rivalid_1111; // @[RegisterRouter.scala:87:24] wire out_f_roready_1111 = out_roready_1_965 & out_romask_1111; // @[RegisterRouter.scala:87:24] wire _out_T_10741 = out_f_roready_1111; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1111 = out_wivalid_1_965 & out_wimask_1111; // @[RegisterRouter.scala:87:24] wire out_f_woready_1111 = out_woready_1_965 & out_womask_1111; // @[RegisterRouter.scala:87:24] wire _out_T_10742 = ~out_rimask_1111; // @[RegisterRouter.scala:87:24] wire _out_T_10743 = ~out_wimask_1111; // @[RegisterRouter.scala:87:24] wire _out_T_10744 = ~out_romask_1111; // @[RegisterRouter.scala:87:24] wire _out_T_10745 = ~out_womask_1111; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_952 = {hi_243, flags_0_go, _out_prepend_T_952}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10746 = out_prepend_952; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10747 = _out_T_10746; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_953 = _out_T_10747; // @[RegisterRouter.scala:87:24] wire out_rimask_1112 = \|_out_rimask_T_1112; // @[RegisterRouter.scala:87:24] wire out_wimask_1112 = &_out_wimask_T_1112; // @[RegisterRouter.scala:87:24] wire out_romask_1112 = \|_out_romask_T_1112; // @[RegisterRouter.scala:87:24] wire out_womask_1112 = &_out_womask_T_1112; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1112 = out_rivalid_1_966 & out_rimask_1112; // @[RegisterRouter.scala:87:24] wire _out_T_10749 = out_f_rivalid_1112; // @[RegisterRouter.scala:87:24] wire out_f_roready_1112 = out_roready_1_966 & out_romask_1112; // @[RegisterRouter.scala:87:24] wire _out_T_10750 = out_f_roready_1112; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1112 = out_wivalid_1_966 & out_wimask_1112; // @[RegisterRouter.scala:87:24] wire out_f_woready_1112 = out_woready_1_966 & out_womask_1112; // @[RegisterRouter.scala:87:24] wire _out_T_10751 = ~out_rimask_1112; // @[RegisterRouter.scala:87:24] wire _out_T_10752 = ~out_wimask_1112; // @[RegisterRouter.scala:87:24] wire _out_T_10753 = ~out_romask_1112; // @[RegisterRouter.scala:87:24] wire _out_T_10754 = ~out_womask_1112; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_953 = {hi_244, flags_0_go, _out_prepend_T_953}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10755 = out_prepend_953; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10756 = _out_T_10755; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_954 = _out_T_10756; // @[RegisterRouter.scala:87:24] wire out_rimask_1113 = \|_out_rimask_T_1113; // @[RegisterRouter.scala:87:24] wire out_wimask_1113 = &_out_wimask_T_1113; // @[RegisterRouter.scala:87:24] wire out_romask_1113 = \|_out_romask_T_1113; // @[RegisterRouter.scala:87:24] wire out_womask_1113 = &_out_womask_T_1113; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1113 = out_rivalid_1_967 & out_rimask_1113; // @[RegisterRouter.scala:87:24] wire _out_T_10758 = out_f_rivalid_1113; // @[RegisterRouter.scala:87:24] wire out_f_roready_1113 = out_roready_1_967 & out_romask_1113; // @[RegisterRouter.scala:87:24] wire _out_T_10759 = out_f_roready_1113; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1113 = out_wivalid_1_967 & out_wimask_1113; // @[RegisterRouter.scala:87:24] wire out_f_woready_1113 = out_woready_1_967 & out_womask_1113; // @[RegisterRouter.scala:87:24] wire _out_T_10760 = ~out_rimask_1113; // @[RegisterRouter.scala:87:24] wire _out_T_10761 = ~out_wimask_1113; // @[RegisterRouter.scala:87:24] wire _out_T_10762 = ~out_romask_1113; // @[RegisterRouter.scala:87:24] wire _out_T_10763 = ~out_womask_1113; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_954 = {hi_245, flags_0_go, _out_prepend_T_954}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10764 = out_prepend_954; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10765 = _out_T_10764; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_955 = _out_T_10765; // @[RegisterRouter.scala:87:24] wire out_rimask_1114 = \|_out_rimask_T_1114; // @[RegisterRouter.scala:87:24] wire out_wimask_1114 = &_out_wimask_T_1114; // @[RegisterRouter.scala:87:24] wire out_romask_1114 = \|_out_romask_T_1114; // @[RegisterRouter.scala:87:24] wire out_womask_1114 = &_out_womask_T_1114; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1114 = out_rivalid_1_968 & out_rimask_1114; // @[RegisterRouter.scala:87:24] wire _out_T_10767 = out_f_rivalid_1114; // @[RegisterRouter.scala:87:24] wire out_f_roready_1114 = out_roready_1_968 & out_romask_1114; // @[RegisterRouter.scala:87:24] wire _out_T_10768 = out_f_roready_1114; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1114 = out_wivalid_1_968 & out_wimask_1114; // @[RegisterRouter.scala:87:24] wire out_f_woready_1114 = out_woready_1_968 & out_womask_1114; // @[RegisterRouter.scala:87:24] wire _out_T_10769 = ~out_rimask_1114; // @[RegisterRouter.scala:87:24] wire _out_T_10770 = ~out_wimask_1114; // @[RegisterRouter.scala:87:24] wire _out_T_10771 = ~out_romask_1114; // @[RegisterRouter.scala:87:24] wire _out_T_10772 = ~out_womask_1114; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_955 = {hi_246, flags_0_go, _out_prepend_T_955}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10773 = out_prepend_955; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10774 = _out_T_10773; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_956 = _out_T_10774; // @[RegisterRouter.scala:87:24] wire out_rimask_1115 = \|_out_rimask_T_1115; // @[RegisterRouter.scala:87:24] wire out_wimask_1115 = &_out_wimask_T_1115; // @[RegisterRouter.scala:87:24] wire out_romask_1115 = \|_out_romask_T_1115; // @[RegisterRouter.scala:87:24] wire out_womask_1115 = &_out_womask_T_1115; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1115 = out_rivalid_1_969 & out_rimask_1115; // @[RegisterRouter.scala:87:24] wire _out_T_10776 = out_f_rivalid_1115; // @[RegisterRouter.scala:87:24] wire out_f_roready_1115 = out_roready_1_969 & out_romask_1115; // @[RegisterRouter.scala:87:24] wire _out_T_10777 = out_f_roready_1115; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1115 = out_wivalid_1_969 & out_wimask_1115; // @[RegisterRouter.scala:87:24] wire out_f_woready_1115 = out_woready_1_969 & out_womask_1115; // @[RegisterRouter.scala:87:24] wire _out_T_10778 = ~out_rimask_1115; // @[RegisterRouter.scala:87:24] wire _out_T_10779 = ~out_wimask_1115; // @[RegisterRouter.scala:87:24] wire _out_T_10780 = ~out_romask_1115; // @[RegisterRouter.scala:87:24] wire _out_T_10781 = ~out_womask_1115; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_956 = {hi_247, flags_0_go, _out_prepend_T_956}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10782 = out_prepend_956; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10783 = _out_T_10782; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_957 = _out_T_10783; // @[RegisterRouter.scala:87:24] wire out_rimask_1116 = \|_out_rimask_T_1116; // @[RegisterRouter.scala:87:24] wire out_wimask_1116 = &_out_wimask_T_1116; // @[RegisterRouter.scala:87:24] wire out_romask_1116 = \|_out_romask_T_1116; // @[RegisterRouter.scala:87:24] wire out_womask_1116 = &_out_womask_T_1116; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1116 = out_rivalid_1_970 & out_rimask_1116; // @[RegisterRouter.scala:87:24] wire _out_T_10785 = out_f_rivalid_1116; // @[RegisterRouter.scala:87:24] wire out_f_roready_1116 = out_roready_1_970 & out_romask_1116; // @[RegisterRouter.scala:87:24] wire _out_T_10786 = out_f_roready_1116; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1116 = out_wivalid_1_970 & out_wimask_1116; // @[RegisterRouter.scala:87:24] wire out_f_woready_1116 = out_woready_1_970 & out_womask_1116; // @[RegisterRouter.scala:87:24] wire _out_T_10787 = ~out_rimask_1116; // @[RegisterRouter.scala:87:24] wire _out_T_10788 = ~out_wimask_1116; // @[RegisterRouter.scala:87:24] wire _out_T_10789 = ~out_romask_1116; // @[RegisterRouter.scala:87:24] wire _out_T_10790 = ~out_womask_1116; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_957 = {hi_248, flags_0_go, _out_prepend_T_957}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10791 = out_prepend_957; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10792 = _out_T_10791; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_158 = _out_T_10792; // @[MuxLiteral.scala:49:48] wire out_rimask_1117 = \|_out_rimask_T_1117; // @[RegisterRouter.scala:87:24] wire out_wimask_1117 = &_out_wimask_T_1117; // @[RegisterRouter.scala:87:24] wire out_romask_1117 = \|_out_romask_T_1117; // @[RegisterRouter.scala:87:24] wire out_womask_1117 = &_out_womask_T_1117; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1117 = out_rivalid_1_971 & out_rimask_1117; // @[RegisterRouter.scala:87:24] wire _out_T_10794 = out_f_rivalid_1117; // @[RegisterRouter.scala:87:24] wire out_f_roready_1117 = out_roready_1_971 & out_romask_1117; // @[RegisterRouter.scala:87:24] wire _out_T_10795 = out_f_roready_1117; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1117 = out_wivalid_1_971 & out_wimask_1117; // @[RegisterRouter.scala:87:24] wire out_f_woready_1117 = out_woready_1_971 & out_womask_1117; // @[RegisterRouter.scala:87:24] wire _out_T_10796 = ~out_rimask_1117; // @[RegisterRouter.scala:87:24] wire _out_T_10797 = ~out_wimask_1117; // @[RegisterRouter.scala:87:24] wire _out_T_10798 = ~out_romask_1117; // @[RegisterRouter.scala:87:24] wire _out_T_10799 = ~out_womask_1117; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10801 = _out_T_10800; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_958 = _out_T_10801; // @[RegisterRouter.scala:87:24] wire out_rimask_1118 = \|_out_rimask_T_1118; // @[RegisterRouter.scala:87:24] wire out_wimask_1118 = &_out_wimask_T_1118; // @[RegisterRouter.scala:87:24] wire out_romask_1118 = \|_out_romask_T_1118; // @[RegisterRouter.scala:87:24] wire out_womask_1118 = &_out_womask_T_1118; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1118 = out_rivalid_1_972 & out_rimask_1118; // @[RegisterRouter.scala:87:24] wire _out_T_10803 = out_f_rivalid_1118; // @[RegisterRouter.scala:87:24] wire out_f_roready_1118 = out_roready_1_972 & out_romask_1118; // @[RegisterRouter.scala:87:24] wire _out_T_10804 = out_f_roready_1118; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1118 = out_wivalid_1_972 & out_wimask_1118; // @[RegisterRouter.scala:87:24] wire out_f_woready_1118 = out_woready_1_972 & out_womask_1118; // @[RegisterRouter.scala:87:24] wire _out_T_10805 = ~out_rimask_1118; // @[RegisterRouter.scala:87:24] wire _out_T_10806 = ~out_wimask_1118; // @[RegisterRouter.scala:87:24] wire _out_T_10807 = ~out_romask_1118; // @[RegisterRouter.scala:87:24] wire _out_T_10808 = ~out_womask_1118; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_958 = {hi_466, flags_0_go, _out_prepend_T_958}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10809 = out_prepend_958; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10810 = _out_T_10809; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_959 = _out_T_10810; // @[RegisterRouter.scala:87:24] wire out_rimask_1119 = \|_out_rimask_T_1119; // @[RegisterRouter.scala:87:24] wire out_wimask_1119 = &_out_wimask_T_1119; // @[RegisterRouter.scala:87:24] wire out_romask_1119 = \|_out_romask_T_1119; // @[RegisterRouter.scala:87:24] wire out_womask_1119 = &_out_womask_T_1119; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1119 = out_rivalid_1_973 & out_rimask_1119; // @[RegisterRouter.scala:87:24] wire _out_T_10812 = out_f_rivalid_1119; // @[RegisterRouter.scala:87:24] wire out_f_roready_1119 = out_roready_1_973 & out_romask_1119; // @[RegisterRouter.scala:87:24] wire _out_T_10813 = out_f_roready_1119; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1119 = out_wivalid_1_973 & out_wimask_1119; // @[RegisterRouter.scala:87:24] wire out_f_woready_1119 = out_woready_1_973 & out_womask_1119; // @[RegisterRouter.scala:87:24] wire _out_T_10814 = ~out_rimask_1119; // @[RegisterRouter.scala:87:24] wire _out_T_10815 = ~out_wimask_1119; // @[RegisterRouter.scala:87:24] wire _out_T_10816 = ~out_romask_1119; // @[RegisterRouter.scala:87:24] wire _out_T_10817 = ~out_womask_1119; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_959 = {hi_467, flags_0_go, _out_prepend_T_959}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10818 = out_prepend_959; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10819 = _out_T_10818; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_960 = _out_T_10819; // @[RegisterRouter.scala:87:24] wire out_rimask_1120 = \|_out_rimask_T_1120; // @[RegisterRouter.scala:87:24] wire out_wimask_1120 = &_out_wimask_T_1120; // @[RegisterRouter.scala:87:24] wire out_romask_1120 = \|_out_romask_T_1120; // @[RegisterRouter.scala:87:24] wire out_womask_1120 = &_out_womask_T_1120; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1120 = out_rivalid_1_974 & out_rimask_1120; // @[RegisterRouter.scala:87:24] wire _out_T_10821 = out_f_rivalid_1120; // @[RegisterRouter.scala:87:24] wire out_f_roready_1120 = out_roready_1_974 & out_romask_1120; // @[RegisterRouter.scala:87:24] wire _out_T_10822 = out_f_roready_1120; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1120 = out_wivalid_1_974 & out_wimask_1120; // @[RegisterRouter.scala:87:24] wire out_f_woready_1120 = out_woready_1_974 & out_womask_1120; // @[RegisterRouter.scala:87:24] wire _out_T_10823 = ~out_rimask_1120; // @[RegisterRouter.scala:87:24] wire _out_T_10824 = ~out_wimask_1120; // @[RegisterRouter.scala:87:24] wire _out_T_10825 = ~out_romask_1120; // @[RegisterRouter.scala:87:24] wire _out_T_10826 = ~out_womask_1120; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_960 = {hi_468, flags_0_go, _out_prepend_T_960}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10827 = out_prepend_960; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10828 = _out_T_10827; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_961 = _out_T_10828; // @[RegisterRouter.scala:87:24] wire out_rimask_1121 = \|_out_rimask_T_1121; // @[RegisterRouter.scala:87:24] wire out_wimask_1121 = &_out_wimask_T_1121; // @[RegisterRouter.scala:87:24] wire out_romask_1121 = \|_out_romask_T_1121; // @[RegisterRouter.scala:87:24] wire out_womask_1121 = &_out_womask_T_1121; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1121 = out_rivalid_1_975 & out_rimask_1121; // @[RegisterRouter.scala:87:24] wire _out_T_10830 = out_f_rivalid_1121; // @[RegisterRouter.scala:87:24] wire out_f_roready_1121 = out_roready_1_975 & out_romask_1121; // @[RegisterRouter.scala:87:24] wire _out_T_10831 = out_f_roready_1121; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1121 = out_wivalid_1_975 & out_wimask_1121; // @[RegisterRouter.scala:87:24] wire out_f_woready_1121 = out_woready_1_975 & out_womask_1121; // @[RegisterRouter.scala:87:24] wire _out_T_10832 = ~out_rimask_1121; // @[RegisterRouter.scala:87:24] wire _out_T_10833 = ~out_wimask_1121; // @[RegisterRouter.scala:87:24] wire _out_T_10834 = ~out_romask_1121; // @[RegisterRouter.scala:87:24] wire _out_T_10835 = ~out_womask_1121; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_961 = {hi_469, flags_0_go, _out_prepend_T_961}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10836 = out_prepend_961; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10837 = _out_T_10836; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_962 = _out_T_10837; // @[RegisterRouter.scala:87:24] wire out_rimask_1122 = \|_out_rimask_T_1122; // @[RegisterRouter.scala:87:24] wire out_wimask_1122 = &_out_wimask_T_1122; // @[RegisterRouter.scala:87:24] wire out_romask_1122 = \|_out_romask_T_1122; // @[RegisterRouter.scala:87:24] wire out_womask_1122 = &_out_womask_T_1122; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1122 = out_rivalid_1_976 & out_rimask_1122; // @[RegisterRouter.scala:87:24] wire _out_T_10839 = out_f_rivalid_1122; // @[RegisterRouter.scala:87:24] wire out_f_roready_1122 = out_roready_1_976 & out_romask_1122; // @[RegisterRouter.scala:87:24] wire _out_T_10840 = out_f_roready_1122; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1122 = out_wivalid_1_976 & out_wimask_1122; // @[RegisterRouter.scala:87:24] wire out_f_woready_1122 = out_woready_1_976 & out_womask_1122; // @[RegisterRouter.scala:87:24] wire _out_T_10841 = ~out_rimask_1122; // @[RegisterRouter.scala:87:24] wire _out_T_10842 = ~out_wimask_1122; // @[RegisterRouter.scala:87:24] wire _out_T_10843 = ~out_romask_1122; // @[RegisterRouter.scala:87:24] wire _out_T_10844 = ~out_womask_1122; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_962 = {hi_470, flags_0_go, _out_prepend_T_962}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10845 = out_prepend_962; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10846 = _out_T_10845; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_963 = _out_T_10846; // @[RegisterRouter.scala:87:24] wire out_rimask_1123 = \|_out_rimask_T_1123; // @[RegisterRouter.scala:87:24] wire out_wimask_1123 = &_out_wimask_T_1123; // @[RegisterRouter.scala:87:24] wire out_romask_1123 = \|_out_romask_T_1123; // @[RegisterRouter.scala:87:24] wire out_womask_1123 = &_out_womask_T_1123; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1123 = out_rivalid_1_977 & out_rimask_1123; // @[RegisterRouter.scala:87:24] wire _out_T_10848 = out_f_rivalid_1123; // @[RegisterRouter.scala:87:24] wire out_f_roready_1123 = out_roready_1_977 & out_romask_1123; // @[RegisterRouter.scala:87:24] wire _out_T_10849 = out_f_roready_1123; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1123 = out_wivalid_1_977 & out_wimask_1123; // @[RegisterRouter.scala:87:24] wire out_f_woready_1123 = out_woready_1_977 & out_womask_1123; // @[RegisterRouter.scala:87:24] wire _out_T_10850 = ~out_rimask_1123; // @[RegisterRouter.scala:87:24] wire _out_T_10851 = ~out_wimask_1123; // @[RegisterRouter.scala:87:24] wire _out_T_10852 = ~out_romask_1123; // @[RegisterRouter.scala:87:24] wire _out_T_10853 = ~out_womask_1123; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_963 = {hi_471, flags_0_go, _out_prepend_T_963}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10854 = out_prepend_963; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10855 = _out_T_10854; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_964 = _out_T_10855; // @[RegisterRouter.scala:87:24] wire out_rimask_1124 = \|_out_rimask_T_1124; // @[RegisterRouter.scala:87:24] wire out_wimask_1124 = &_out_wimask_T_1124; // @[RegisterRouter.scala:87:24] wire out_romask_1124 = \|_out_romask_T_1124; // @[RegisterRouter.scala:87:24] wire out_womask_1124 = &_out_womask_T_1124; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1124 = out_rivalid_1_978 & out_rimask_1124; // @[RegisterRouter.scala:87:24] wire _out_T_10857 = out_f_rivalid_1124; // @[RegisterRouter.scala:87:24] wire out_f_roready_1124 = out_roready_1_978 & out_romask_1124; // @[RegisterRouter.scala:87:24] wire _out_T_10858 = out_f_roready_1124; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1124 = out_wivalid_1_978 & out_wimask_1124; // @[RegisterRouter.scala:87:24] wire out_f_woready_1124 = out_woready_1_978 & out_womask_1124; // @[RegisterRouter.scala:87:24] wire _out_T_10859 = ~out_rimask_1124; // @[RegisterRouter.scala:87:24] wire _out_T_10860 = ~out_wimask_1124; // @[RegisterRouter.scala:87:24] wire _out_T_10861 = ~out_romask_1124; // @[RegisterRouter.scala:87:24] wire _out_T_10862 = ~out_womask_1124; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_964 = {hi_472, flags_0_go, _out_prepend_T_964}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10863 = out_prepend_964; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10864 = _out_T_10863; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_186 = _out_T_10864; // @[MuxLiteral.scala:49:48] wire out_rimask_1125 = \|_out_rimask_T_1125; // @[RegisterRouter.scala:87:24] wire out_wimask_1125 = &_out_wimask_T_1125; // @[RegisterRouter.scala:87:24] wire out_romask_1125 = \|_out_romask_T_1125; // @[RegisterRouter.scala:87:24] wire out_womask_1125 = &_out_womask_T_1125; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1125 = out_rivalid_1_979 & out_rimask_1125; // @[RegisterRouter.scala:87:24] wire _out_T_10866 = out_f_rivalid_1125; // @[RegisterRouter.scala:87:24] wire out_f_roready_1125 = out_roready_1_979 & out_romask_1125; // @[RegisterRouter.scala:87:24] wire _out_T_10867 = out_f_roready_1125; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1125 = out_wivalid_1_979 & out_wimask_1125; // @[RegisterRouter.scala:87:24] wire _out_T_10868 = out_f_wivalid_1125; // @[RegisterRouter.scala:87:24] wire out_f_woready_1125 = out_woready_1_979 & out_womask_1125; // @[RegisterRouter.scala:87:24] wire _out_T_10869 = out_f_woready_1125; // @[RegisterRouter.scala:87:24] wire _out_T_10870 = ~out_rimask_1125; // @[RegisterRouter.scala:87:24] wire _out_T_10871 = ~out_wimask_1125; // @[RegisterRouter.scala:87:24] wire _out_T_10872 = ~out_romask_1125; // @[RegisterRouter.scala:87:24] wire _out_T_10873 = ~out_womask_1125; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10875 = _out_T_10874; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_965 = _out_T_10875; // @[RegisterRouter.scala:87:24] wire out_rimask_1126 = \|_out_rimask_T_1126; // @[RegisterRouter.scala:87:24] wire out_wimask_1126 = &_out_wimask_T_1126; // @[RegisterRouter.scala:87:24] wire out_romask_1126 = \|_out_romask_T_1126; // @[RegisterRouter.scala:87:24] wire out_womask_1126 = &_out_womask_T_1126; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1126 = out_rivalid_1_980 & out_rimask_1126; // @[RegisterRouter.scala:87:24] wire _out_T_10877 = out_f_rivalid_1126; // @[RegisterRouter.scala:87:24] wire out_f_roready_1126 = out_roready_1_980 & out_romask_1126; // @[RegisterRouter.scala:87:24] wire _out_T_10878 = out_f_roready_1126; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1126 = out_wivalid_1_980 & out_wimask_1126; // @[RegisterRouter.scala:87:24] wire _out_T_10879 = out_f_wivalid_1126; // @[RegisterRouter.scala:87:24] wire out_f_woready_1126 = out_woready_1_980 & out_womask_1126; // @[RegisterRouter.scala:87:24] wire _out_T_10880 = out_f_woready_1126; // @[RegisterRouter.scala:87:24] wire _out_T_10881 = ~out_rimask_1126; // @[RegisterRouter.scala:87:24] wire _out_T_10882 = ~out_wimask_1126; // @[RegisterRouter.scala:87:24] wire _out_T_10883 = ~out_romask_1126; // @[RegisterRouter.scala:87:24] wire _out_T_10884 = ~out_womask_1126; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_965 = {abstractDataMem_17, _out_prepend_T_965}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10885 = out_prepend_965; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10886 = _out_T_10885; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_966 = _out_T_10886; // @[RegisterRouter.scala:87:24] wire out_rimask_1127 = \|_out_rimask_T_1127; // @[RegisterRouter.scala:87:24] wire out_wimask_1127 = &_out_wimask_T_1127; // @[RegisterRouter.scala:87:24] wire out_romask_1127 = \|_out_romask_T_1127; // @[RegisterRouter.scala:87:24] wire out_womask_1127 = &_out_womask_T_1127; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1127 = out_rivalid_1_981 & out_rimask_1127; // @[RegisterRouter.scala:87:24] wire _out_T_10888 = out_f_rivalid_1127; // @[RegisterRouter.scala:87:24] wire out_f_roready_1127 = out_roready_1_981 & out_romask_1127; // @[RegisterRouter.scala:87:24] wire _out_T_10889 = out_f_roready_1127; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1127 = out_wivalid_1_981 & out_wimask_1127; // @[RegisterRouter.scala:87:24] wire _out_T_10890 = out_f_wivalid_1127; // @[RegisterRouter.scala:87:24] wire out_f_woready_1127 = out_woready_1_981 & out_womask_1127; // @[RegisterRouter.scala:87:24] wire _out_T_10891 = out_f_woready_1127; // @[RegisterRouter.scala:87:24] wire _out_T_10892 = ~out_rimask_1127; // @[RegisterRouter.scala:87:24] wire _out_T_10893 = ~out_wimask_1127; // @[RegisterRouter.scala:87:24] wire _out_T_10894 = ~out_romask_1127; // @[RegisterRouter.scala:87:24] wire _out_T_10895 = ~out_womask_1127; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_966 = {abstractDataMem_18, _out_prepend_T_966}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10896 = out_prepend_966; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10897 = _out_T_10896; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_967 = _out_T_10897; // @[RegisterRouter.scala:87:24] wire out_rimask_1128 = \|_out_rimask_T_1128; // @[RegisterRouter.scala:87:24] wire out_wimask_1128 = &_out_wimask_T_1128; // @[RegisterRouter.scala:87:24] wire out_romask_1128 = \|_out_romask_T_1128; // @[RegisterRouter.scala:87:24] wire out_womask_1128 = &_out_womask_T_1128; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1128 = out_rivalid_1_982 & out_rimask_1128; // @[RegisterRouter.scala:87:24] wire _out_T_10899 = out_f_rivalid_1128; // @[RegisterRouter.scala:87:24] wire out_f_roready_1128 = out_roready_1_982 & out_romask_1128; // @[RegisterRouter.scala:87:24] wire _out_T_10900 = out_f_roready_1128; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1128 = out_wivalid_1_982 & out_wimask_1128; // @[RegisterRouter.scala:87:24] wire _out_T_10901 = out_f_wivalid_1128; // @[RegisterRouter.scala:87:24] wire out_f_woready_1128 = out_woready_1_982 & out_womask_1128; // @[RegisterRouter.scala:87:24] wire _out_T_10902 = out_f_woready_1128; // @[RegisterRouter.scala:87:24] wire _out_T_10903 = ~out_rimask_1128; // @[RegisterRouter.scala:87:24] wire _out_T_10904 = ~out_wimask_1128; // @[RegisterRouter.scala:87:24] wire _out_T_10905 = ~out_romask_1128; // @[RegisterRouter.scala:87:24] wire _out_T_10906 = ~out_womask_1128; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_967 = {abstractDataMem_19, _out_prepend_T_967}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10907 = out_prepend_967; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10908 = _out_T_10907; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_968 = _out_T_10908; // @[RegisterRouter.scala:87:24] wire out_rimask_1129 = \|_out_rimask_T_1129; // @[RegisterRouter.scala:87:24] wire out_wimask_1129 = &_out_wimask_T_1129; // @[RegisterRouter.scala:87:24] wire out_romask_1129 = \|_out_romask_T_1129; // @[RegisterRouter.scala:87:24] wire out_womask_1129 = &_out_womask_T_1129; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1129 = out_rivalid_1_983 & out_rimask_1129; // @[RegisterRouter.scala:87:24] wire _out_T_10910 = out_f_rivalid_1129; // @[RegisterRouter.scala:87:24] wire out_f_roready_1129 = out_roready_1_983 & out_romask_1129; // @[RegisterRouter.scala:87:24] wire _out_T_10911 = out_f_roready_1129; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1129 = out_wivalid_1_983 & out_wimask_1129; // @[RegisterRouter.scala:87:24] wire _out_T_10912 = out_f_wivalid_1129; // @[RegisterRouter.scala:87:24] wire out_f_woready_1129 = out_woready_1_983 & out_womask_1129; // @[RegisterRouter.scala:87:24] wire _out_T_10913 = out_f_woready_1129; // @[RegisterRouter.scala:87:24] wire _out_T_10914 = ~out_rimask_1129; // @[RegisterRouter.scala:87:24] wire _out_T_10915 = ~out_wimask_1129; // @[RegisterRouter.scala:87:24] wire _out_T_10916 = ~out_romask_1129; // @[RegisterRouter.scala:87:24] wire _out_T_10917 = ~out_womask_1129; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_968 = {abstractDataMem_20, _out_prepend_T_968}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10918 = out_prepend_968; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10919 = _out_T_10918; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_969 = _out_T_10919; // @[RegisterRouter.scala:87:24] wire out_rimask_1130 = \|_out_rimask_T_1130; // @[RegisterRouter.scala:87:24] wire out_wimask_1130 = &_out_wimask_T_1130; // @[RegisterRouter.scala:87:24] wire out_romask_1130 = \|_out_romask_T_1130; // @[RegisterRouter.scala:87:24] wire out_womask_1130 = &_out_womask_T_1130; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1130 = out_rivalid_1_984 & out_rimask_1130; // @[RegisterRouter.scala:87:24] wire _out_T_10921 = out_f_rivalid_1130; // @[RegisterRouter.scala:87:24] wire out_f_roready_1130 = out_roready_1_984 & out_romask_1130; // @[RegisterRouter.scala:87:24] wire _out_T_10922 = out_f_roready_1130; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1130 = out_wivalid_1_984 & out_wimask_1130; // @[RegisterRouter.scala:87:24] wire _out_T_10923 = out_f_wivalid_1130; // @[RegisterRouter.scala:87:24] wire out_f_woready_1130 = out_woready_1_984 & out_womask_1130; // @[RegisterRouter.scala:87:24] wire _out_T_10924 = out_f_woready_1130; // @[RegisterRouter.scala:87:24] wire _out_T_10925 = ~out_rimask_1130; // @[RegisterRouter.scala:87:24] wire _out_T_10926 = ~out_wimask_1130; // @[RegisterRouter.scala:87:24] wire _out_T_10927 = ~out_romask_1130; // @[RegisterRouter.scala:87:24] wire _out_T_10928 = ~out_womask_1130; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_969 = {abstractDataMem_21, _out_prepend_T_969}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10929 = out_prepend_969; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10930 = _out_T_10929; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_970 = _out_T_10930; // @[RegisterRouter.scala:87:24] wire out_rimask_1131 = \|_out_rimask_T_1131; // @[RegisterRouter.scala:87:24] wire out_wimask_1131 = &_out_wimask_T_1131; // @[RegisterRouter.scala:87:24] wire out_romask_1131 = \|_out_romask_T_1131; // @[RegisterRouter.scala:87:24] wire out_womask_1131 = &_out_womask_T_1131; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1131 = out_rivalid_1_985 & out_rimask_1131; // @[RegisterRouter.scala:87:24] wire _out_T_10932 = out_f_rivalid_1131; // @[RegisterRouter.scala:87:24] wire out_f_roready_1131 = out_roready_1_985 & out_romask_1131; // @[RegisterRouter.scala:87:24] wire _out_T_10933 = out_f_roready_1131; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1131 = out_wivalid_1_985 & out_wimask_1131; // @[RegisterRouter.scala:87:24] wire _out_T_10934 = out_f_wivalid_1131; // @[RegisterRouter.scala:87:24] wire out_f_woready_1131 = out_woready_1_985 & out_womask_1131; // @[RegisterRouter.scala:87:24] wire _out_T_10935 = out_f_woready_1131; // @[RegisterRouter.scala:87:24] wire _out_T_10936 = ~out_rimask_1131; // @[RegisterRouter.scala:87:24] wire _out_T_10937 = ~out_wimask_1131; // @[RegisterRouter.scala:87:24] wire _out_T_10938 = ~out_romask_1131; // @[RegisterRouter.scala:87:24] wire _out_T_10939 = ~out_womask_1131; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_970 = {abstractDataMem_22, _out_prepend_T_970}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10940 = out_prepend_970; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10941 = _out_T_10940; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_971 = _out_T_10941; // @[RegisterRouter.scala:87:24] wire out_rimask_1132 = \|_out_rimask_T_1132; // @[RegisterRouter.scala:87:24] wire out_wimask_1132 = &_out_wimask_T_1132; // @[RegisterRouter.scala:87:24] wire out_romask_1132 = \|_out_romask_T_1132; // @[RegisterRouter.scala:87:24] wire out_womask_1132 = &_out_womask_T_1132; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1132 = out_rivalid_1_986 & out_rimask_1132; // @[RegisterRouter.scala:87:24] wire _out_T_10943 = out_f_rivalid_1132; // @[RegisterRouter.scala:87:24] wire out_f_roready_1132 = out_roready_1_986 & out_romask_1132; // @[RegisterRouter.scala:87:24] wire _out_T_10944 = out_f_roready_1132; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1132 = out_wivalid_1_986 & out_wimask_1132; // @[RegisterRouter.scala:87:24] wire _out_T_10945 = out_f_wivalid_1132; // @[RegisterRouter.scala:87:24] wire out_f_woready_1132 = out_woready_1_986 & out_womask_1132; // @[RegisterRouter.scala:87:24] wire _out_T_10946 = out_f_woready_1132; // @[RegisterRouter.scala:87:24] wire _out_T_10947 = ~out_rimask_1132; // @[RegisterRouter.scala:87:24] wire _out_T_10948 = ~out_wimask_1132; // @[RegisterRouter.scala:87:24] wire _out_T_10949 = ~out_romask_1132; // @[RegisterRouter.scala:87:24] wire _out_T_10950 = ~out_womask_1132; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_971 = {abstractDataMem_23, _out_prepend_T_971}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10951 = out_prepend_971; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10952 = _out_T_10951; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_114 = _out_T_10952; // @[MuxLiteral.scala:49:48] wire out_rimask_1133 = \|_out_rimask_T_1133; // @[RegisterRouter.scala:87:24] wire out_wimask_1133 = &_out_wimask_T_1133; // @[RegisterRouter.scala:87:24] wire out_romask_1133 = \|_out_romask_T_1133; // @[RegisterRouter.scala:87:24] wire out_womask_1133 = &_out_womask_T_1133; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1133 = out_rivalid_1_987 & out_rimask_1133; // @[RegisterRouter.scala:87:24] wire _out_T_10954 = out_f_rivalid_1133; // @[RegisterRouter.scala:87:24] wire out_f_roready_1133 = out_roready_1_987 & out_romask_1133; // @[RegisterRouter.scala:87:24] wire _out_T_10955 = out_f_roready_1133; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1133 = out_wivalid_1_987 & out_wimask_1133; // @[RegisterRouter.scala:87:24] wire out_f_woready_1133 = out_woready_1_987 & out_womask_1133; // @[RegisterRouter.scala:87:24] wire _out_T_10956 = ~out_rimask_1133; // @[RegisterRouter.scala:87:24] wire _out_T_10957 = ~out_wimask_1133; // @[RegisterRouter.scala:87:24] wire _out_T_10958 = ~out_romask_1133; // @[RegisterRouter.scala:87:24] wire _out_T_10959 = ~out_womask_1133; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10961 = _out_T_10960; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_972 = _out_T_10961; // @[RegisterRouter.scala:87:24] wire out_rimask_1134 = \|_out_rimask_T_1134; // @[RegisterRouter.scala:87:24] wire out_wimask_1134 = &_out_wimask_T_1134; // @[RegisterRouter.scala:87:24] wire out_romask_1134 = \|_out_romask_T_1134; // @[RegisterRouter.scala:87:24] wire out_womask_1134 = &_out_womask_T_1134; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1134 = out_rivalid_1_988 & out_rimask_1134; // @[RegisterRouter.scala:87:24] wire _out_T_10963 = out_f_rivalid_1134; // @[RegisterRouter.scala:87:24] wire out_f_roready_1134 = out_roready_1_988 & out_romask_1134; // @[RegisterRouter.scala:87:24] wire _out_T_10964 = out_f_roready_1134; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1134 = out_wivalid_1_988 & out_wimask_1134; // @[RegisterRouter.scala:87:24] wire out_f_woready_1134 = out_woready_1_988 & out_womask_1134; // @[RegisterRouter.scala:87:24] wire _out_T_10965 = ~out_rimask_1134; // @[RegisterRouter.scala:87:24] wire _out_T_10966 = ~out_wimask_1134; // @[RegisterRouter.scala:87:24] wire _out_T_10967 = ~out_romask_1134; // @[RegisterRouter.scala:87:24] wire _out_T_10968 = ~out_womask_1134; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_972 = {hi_346, flags_0_go, _out_prepend_T_972}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10969 = out_prepend_972; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10970 = _out_T_10969; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_973 = _out_T_10970; // @[RegisterRouter.scala:87:24] wire out_rimask_1135 = \|_out_rimask_T_1135; // @[RegisterRouter.scala:87:24] wire out_wimask_1135 = &_out_wimask_T_1135; // @[RegisterRouter.scala:87:24] wire out_romask_1135 = \|_out_romask_T_1135; // @[RegisterRouter.scala:87:24] wire out_womask_1135 = &_out_womask_T_1135; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1135 = out_rivalid_1_989 & out_rimask_1135; // @[RegisterRouter.scala:87:24] wire _out_T_10972 = out_f_rivalid_1135; // @[RegisterRouter.scala:87:24] wire out_f_roready_1135 = out_roready_1_989 & out_romask_1135; // @[RegisterRouter.scala:87:24] wire _out_T_10973 = out_f_roready_1135; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1135 = out_wivalid_1_989 & out_wimask_1135; // @[RegisterRouter.scala:87:24] wire out_f_woready_1135 = out_woready_1_989 & out_womask_1135; // @[RegisterRouter.scala:87:24] wire _out_T_10974 = ~out_rimask_1135; // @[RegisterRouter.scala:87:24] wire _out_T_10975 = ~out_wimask_1135; // @[RegisterRouter.scala:87:24] wire _out_T_10976 = ~out_romask_1135; // @[RegisterRouter.scala:87:24] wire _out_T_10977 = ~out_womask_1135; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_973 = {hi_347, flags_0_go, _out_prepend_T_973}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10978 = out_prepend_973; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10979 = _out_T_10978; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_974 = _out_T_10979; // @[RegisterRouter.scala:87:24] wire out_rimask_1136 = \|_out_rimask_T_1136; // @[RegisterRouter.scala:87:24] wire out_wimask_1136 = &_out_wimask_T_1136; // @[RegisterRouter.scala:87:24] wire out_romask_1136 = \|_out_romask_T_1136; // @[RegisterRouter.scala:87:24] wire out_womask_1136 = &_out_womask_T_1136; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1136 = out_rivalid_1_990 & out_rimask_1136; // @[RegisterRouter.scala:87:24] wire _out_T_10981 = out_f_rivalid_1136; // @[RegisterRouter.scala:87:24] wire out_f_roready_1136 = out_roready_1_990 & out_romask_1136; // @[RegisterRouter.scala:87:24] wire _out_T_10982 = out_f_roready_1136; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1136 = out_wivalid_1_990 & out_wimask_1136; // @[RegisterRouter.scala:87:24] wire out_f_woready_1136 = out_woready_1_990 & out_womask_1136; // @[RegisterRouter.scala:87:24] wire _out_T_10983 = ~out_rimask_1136; // @[RegisterRouter.scala:87:24] wire _out_T_10984 = ~out_wimask_1136; // @[RegisterRouter.scala:87:24] wire _out_T_10985 = ~out_romask_1136; // @[RegisterRouter.scala:87:24] wire _out_T_10986 = ~out_womask_1136; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_974 = {hi_348, flags_0_go, _out_prepend_T_974}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10987 = out_prepend_974; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10988 = _out_T_10987; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_975 = _out_T_10988; // @[RegisterRouter.scala:87:24] wire out_rimask_1137 = \|_out_rimask_T_1137; // @[RegisterRouter.scala:87:24] wire out_wimask_1137 = &_out_wimask_T_1137; // @[RegisterRouter.scala:87:24] wire out_romask_1137 = \|_out_romask_T_1137; // @[RegisterRouter.scala:87:24] wire out_womask_1137 = &_out_womask_T_1137; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1137 = out_rivalid_1_991 & out_rimask_1137; // @[RegisterRouter.scala:87:24] wire _out_T_10990 = out_f_rivalid_1137; // @[RegisterRouter.scala:87:24] wire out_f_roready_1137 = out_roready_1_991 & out_romask_1137; // @[RegisterRouter.scala:87:24] wire _out_T_10991 = out_f_roready_1137; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1137 = out_wivalid_1_991 & out_wimask_1137; // @[RegisterRouter.scala:87:24] wire out_f_woready_1137 = out_woready_1_991 & out_womask_1137; // @[RegisterRouter.scala:87:24] wire _out_T_10992 = ~out_rimask_1137; // @[RegisterRouter.scala:87:24] wire _out_T_10993 = ~out_wimask_1137; // @[RegisterRouter.scala:87:24] wire _out_T_10994 = ~out_romask_1137; // @[RegisterRouter.scala:87:24] wire _out_T_10995 = ~out_womask_1137; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_975 = {hi_349, flags_0_go, _out_prepend_T_975}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10996 = out_prepend_975; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10997 = _out_T_10996; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_976 = _out_T_10997; // @[RegisterRouter.scala:87:24] wire out_rimask_1138 = \|_out_rimask_T_1138; // @[RegisterRouter.scala:87:24] wire out_wimask_1138 = &_out_wimask_T_1138; // @[RegisterRouter.scala:87:24] wire out_romask_1138 = \|_out_romask_T_1138; // @[RegisterRouter.scala:87:24] wire out_womask_1138 = &_out_womask_T_1138; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1138 = out_rivalid_1_992 & out_rimask_1138; // @[RegisterRouter.scala:87:24] wire _out_T_10999 = out_f_rivalid_1138; // @[RegisterRouter.scala:87:24] wire out_f_roready_1138 = out_roready_1_992 & out_romask_1138; // @[RegisterRouter.scala:87:24] wire _out_T_11000 = out_f_roready_1138; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1138 = out_wivalid_1_992 & out_wimask_1138; // @[RegisterRouter.scala:87:24] wire out_f_woready_1138 = out_woready_1_992 & out_womask_1138; // @[RegisterRouter.scala:87:24] wire _out_T_11001 = ~out_rimask_1138; // @[RegisterRouter.scala:87:24] wire _out_T_11002 = ~out_wimask_1138; // @[RegisterRouter.scala:87:24] wire _out_T_11003 = ~out_romask_1138; // @[RegisterRouter.scala:87:24] wire _out_T_11004 = ~out_womask_1138; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_976 = {hi_350, flags_0_go, _out_prepend_T_976}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11005 = out_prepend_976; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11006 = _out_T_11005; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_977 = _out_T_11006; // @[RegisterRouter.scala:87:24] wire out_rimask_1139 = \|_out_rimask_T_1139; // @[RegisterRouter.scala:87:24] wire out_wimask_1139 = &_out_wimask_T_1139; // @[RegisterRouter.scala:87:24] wire out_romask_1139 = \|_out_romask_T_1139; // @[RegisterRouter.scala:87:24] wire out_womask_1139 = &_out_womask_T_1139; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1139 = out_rivalid_1_993 & out_rimask_1139; // @[RegisterRouter.scala:87:24] wire _out_T_11008 = out_f_rivalid_1139; // @[RegisterRouter.scala:87:24] wire out_f_roready_1139 = out_roready_1_993 & out_romask_1139; // @[RegisterRouter.scala:87:24] wire _out_T_11009 = out_f_roready_1139; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1139 = out_wivalid_1_993 & out_wimask_1139; // @[RegisterRouter.scala:87:24] wire out_f_woready_1139 = out_woready_1_993 & out_womask_1139; // @[RegisterRouter.scala:87:24] wire _out_T_11010 = ~out_rimask_1139; // @[RegisterRouter.scala:87:24] wire _out_T_11011 = ~out_wimask_1139; // @[RegisterRouter.scala:87:24] wire _out_T_11012 = ~out_romask_1139; // @[RegisterRouter.scala:87:24] wire _out_T_11013 = ~out_womask_1139; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_977 = {hi_351, flags_0_go, _out_prepend_T_977}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11014 = out_prepend_977; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11015 = _out_T_11014; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_978 = _out_T_11015; // @[RegisterRouter.scala:87:24] wire out_rimask_1140 = \|_out_rimask_T_1140; // @[RegisterRouter.scala:87:24] wire out_wimask_1140 = &_out_wimask_T_1140; // @[RegisterRouter.scala:87:24] wire out_romask_1140 = \|_out_romask_T_1140; // @[RegisterRouter.scala:87:24] wire out_womask_1140 = &_out_womask_T_1140; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1140 = out_rivalid_1_994 & out_rimask_1140; // @[RegisterRouter.scala:87:24] wire _out_T_11017 = out_f_rivalid_1140; // @[RegisterRouter.scala:87:24] wire out_f_roready_1140 = out_roready_1_994 & out_romask_1140; // @[RegisterRouter.scala:87:24] wire _out_T_11018 = out_f_roready_1140; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1140 = out_wivalid_1_994 & out_wimask_1140; // @[RegisterRouter.scala:87:24] wire out_f_woready_1140 = out_woready_1_994 & out_womask_1140; // @[RegisterRouter.scala:87:24] wire _out_T_11019 = ~out_rimask_1140; // @[RegisterRouter.scala:87:24] wire _out_T_11020 = ~out_wimask_1140; // @[RegisterRouter.scala:87:24] wire _out_T_11021 = ~out_romask_1140; // @[RegisterRouter.scala:87:24] wire _out_T_11022 = ~out_womask_1140; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_978 = {hi_352, flags_0_go, _out_prepend_T_978}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11023 = out_prepend_978; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11024 = _out_T_11023; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_171 = _out_T_11024; // @[MuxLiteral.scala:49:48] wire out_rimask_1141 = \|_out_rimask_T_1141; // @[RegisterRouter.scala:87:24] wire out_wimask_1141 = &_out_wimask_T_1141; // @[RegisterRouter.scala:87:24] wire out_romask_1141 = \|_out_romask_T_1141; // @[RegisterRouter.scala:87:24] wire out_womask_1141 = &_out_womask_T_1141; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1141 = out_rivalid_1_995 & out_rimask_1141; // @[RegisterRouter.scala:87:24] wire _out_T_11026 = out_f_rivalid_1141; // @[RegisterRouter.scala:87:24] wire out_f_roready_1141 = out_roready_1_995 & out_romask_1141; // @[RegisterRouter.scala:87:24] wire _out_T_11027 = out_f_roready_1141; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1141 = out_wivalid_1_995 & out_wimask_1141; // @[RegisterRouter.scala:87:24] wire out_f_woready_1141 = out_woready_1_995 & out_womask_1141; // @[RegisterRouter.scala:87:24] wire _out_T_11028 = ~out_rimask_1141; // @[RegisterRouter.scala:87:24] wire _out_T_11029 = ~out_wimask_1141; // @[RegisterRouter.scala:87:24] wire _out_T_11030 = ~out_romask_1141; // @[RegisterRouter.scala:87:24] wire _out_T_11031 = ~out_womask_1141; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11033 = _out_T_11032; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_979 = _out_T_11033; // @[RegisterRouter.scala:87:24] wire out_rimask_1142 = \|_out_rimask_T_1142; // @[RegisterRouter.scala:87:24] wire out_wimask_1142 = &_out_wimask_T_1142; // @[RegisterRouter.scala:87:24] wire out_romask_1142 = \|_out_romask_T_1142; // @[RegisterRouter.scala:87:24] wire out_womask_1142 = &_out_womask_T_1142; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1142 = out_rivalid_1_996 & out_rimask_1142; // @[RegisterRouter.scala:87:24] wire _out_T_11035 = out_f_rivalid_1142; // @[RegisterRouter.scala:87:24] wire out_f_roready_1142 = out_roready_1_996 & out_romask_1142; // @[RegisterRouter.scala:87:24] wire _out_T_11036 = out_f_roready_1142; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1142 = out_wivalid_1_996 & out_wimask_1142; // @[RegisterRouter.scala:87:24] wire out_f_woready_1142 = out_woready_1_996 & out_womask_1142; // @[RegisterRouter.scala:87:24] wire _out_T_11037 = ~out_rimask_1142; // @[RegisterRouter.scala:87:24] wire _out_T_11038 = ~out_wimask_1142; // @[RegisterRouter.scala:87:24] wire _out_T_11039 = ~out_romask_1142; // @[RegisterRouter.scala:87:24] wire _out_T_11040 = ~out_womask_1142; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_979 = {hi_90, flags_0_go, _out_prepend_T_979}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11041 = out_prepend_979; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11042 = _out_T_11041; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_980 = _out_T_11042; // @[RegisterRouter.scala:87:24] wire out_rimask_1143 = \|_out_rimask_T_1143; // @[RegisterRouter.scala:87:24] wire out_wimask_1143 = &_out_wimask_T_1143; // @[RegisterRouter.scala:87:24] wire out_romask_1143 = \|_out_romask_T_1143; // @[RegisterRouter.scala:87:24] wire out_womask_1143 = &_out_womask_T_1143; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1143 = out_rivalid_1_997 & out_rimask_1143; // @[RegisterRouter.scala:87:24] wire _out_T_11044 = out_f_rivalid_1143; // @[RegisterRouter.scala:87:24] wire out_f_roready_1143 = out_roready_1_997 & out_romask_1143; // @[RegisterRouter.scala:87:24] wire _out_T_11045 = out_f_roready_1143; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1143 = out_wivalid_1_997 & out_wimask_1143; // @[RegisterRouter.scala:87:24] wire out_f_woready_1143 = out_woready_1_997 & out_womask_1143; // @[RegisterRouter.scala:87:24] wire _out_T_11046 = ~out_rimask_1143; // @[RegisterRouter.scala:87:24] wire _out_T_11047 = ~out_wimask_1143; // @[RegisterRouter.scala:87:24] wire _out_T_11048 = ~out_romask_1143; // @[RegisterRouter.scala:87:24] wire _out_T_11049 = ~out_womask_1143; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_980 = {hi_91, flags_0_go, _out_prepend_T_980}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11050 = out_prepend_980; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11051 = _out_T_11050; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_981 = _out_T_11051; // @[RegisterRouter.scala:87:24] wire out_rimask_1144 = \|_out_rimask_T_1144; // @[RegisterRouter.scala:87:24] wire out_wimask_1144 = &_out_wimask_T_1144; // @[RegisterRouter.scala:87:24] wire out_romask_1144 = \|_out_romask_T_1144; // @[RegisterRouter.scala:87:24] wire out_womask_1144 = &_out_womask_T_1144; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1144 = out_rivalid_1_998 & out_rimask_1144; // @[RegisterRouter.scala:87:24] wire _out_T_11053 = out_f_rivalid_1144; // @[RegisterRouter.scala:87:24] wire out_f_roready_1144 = out_roready_1_998 & out_romask_1144; // @[RegisterRouter.scala:87:24] wire _out_T_11054 = out_f_roready_1144; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1144 = out_wivalid_1_998 & out_wimask_1144; // @[RegisterRouter.scala:87:24] wire out_f_woready_1144 = out_woready_1_998 & out_womask_1144; // @[RegisterRouter.scala:87:24] wire _out_T_11055 = ~out_rimask_1144; // @[RegisterRouter.scala:87:24] wire _out_T_11056 = ~out_wimask_1144; // @[RegisterRouter.scala:87:24] wire _out_T_11057 = ~out_romask_1144; // @[RegisterRouter.scala:87:24] wire _out_T_11058 = ~out_womask_1144; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_981 = {hi_92, flags_0_go, _out_prepend_T_981}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11059 = out_prepend_981; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11060 = _out_T_11059; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_982 = _out_T_11060; // @[RegisterRouter.scala:87:24] wire out_rimask_1145 = \|_out_rimask_T_1145; // @[RegisterRouter.scala:87:24] wire out_wimask_1145 = &_out_wimask_T_1145; // @[RegisterRouter.scala:87:24] wire out_romask_1145 = \|_out_romask_T_1145; // @[RegisterRouter.scala:87:24] wire out_womask_1145 = &_out_womask_T_1145; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1145 = out_rivalid_1_999 & out_rimask_1145; // @[RegisterRouter.scala:87:24] wire _out_T_11062 = out_f_rivalid_1145; // @[RegisterRouter.scala:87:24] wire out_f_roready_1145 = out_roready_1_999 & out_romask_1145; // @[RegisterRouter.scala:87:24] wire _out_T_11063 = out_f_roready_1145; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1145 = out_wivalid_1_999 & out_wimask_1145; // @[RegisterRouter.scala:87:24] wire out_f_woready_1145 = out_woready_1_999 & out_womask_1145; // @[RegisterRouter.scala:87:24] wire _out_T_11064 = ~out_rimask_1145; // @[RegisterRouter.scala:87:24] wire _out_T_11065 = ~out_wimask_1145; // @[RegisterRouter.scala:87:24] wire _out_T_11066 = ~out_romask_1145; // @[RegisterRouter.scala:87:24] wire _out_T_11067 = ~out_womask_1145; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_982 = {hi_93, flags_0_go, _out_prepend_T_982}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11068 = out_prepend_982; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11069 = _out_T_11068; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_983 = _out_T_11069; // @[RegisterRouter.scala:87:24] wire out_rimask_1146 = \|_out_rimask_T_1146; // @[RegisterRouter.scala:87:24] wire out_wimask_1146 = &_out_wimask_T_1146; // @[RegisterRouter.scala:87:24] wire out_romask_1146 = \|_out_romask_T_1146; // @[RegisterRouter.scala:87:24] wire out_womask_1146 = &_out_womask_T_1146; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1146 = out_rivalid_1_1000 & out_rimask_1146; // @[RegisterRouter.scala:87:24] wire _out_T_11071 = out_f_rivalid_1146; // @[RegisterRouter.scala:87:24] wire out_f_roready_1146 = out_roready_1_1000 & out_romask_1146; // @[RegisterRouter.scala:87:24] wire _out_T_11072 = out_f_roready_1146; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1146 = out_wivalid_1_1000 & out_wimask_1146; // @[RegisterRouter.scala:87:24] wire out_f_woready_1146 = out_woready_1_1000 & out_womask_1146; // @[RegisterRouter.scala:87:24] wire _out_T_11073 = ~out_rimask_1146; // @[RegisterRouter.scala:87:24] wire _out_T_11074 = ~out_wimask_1146; // @[RegisterRouter.scala:87:24] wire _out_T_11075 = ~out_romask_1146; // @[RegisterRouter.scala:87:24] wire _out_T_11076 = ~out_womask_1146; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_983 = {hi_94, flags_0_go, _out_prepend_T_983}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11077 = out_prepend_983; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11078 = _out_T_11077; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_984 = _out_T_11078; // @[RegisterRouter.scala:87:24] wire out_rimask_1147 = \|_out_rimask_T_1147; // @[RegisterRouter.scala:87:24] wire out_wimask_1147 = &_out_wimask_T_1147; // @[RegisterRouter.scala:87:24] wire out_romask_1147 = \|_out_romask_T_1147; // @[RegisterRouter.scala:87:24] wire out_womask_1147 = &_out_womask_T_1147; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1147 = out_rivalid_1_1001 & out_rimask_1147; // @[RegisterRouter.scala:87:24] wire _out_T_11080 = out_f_rivalid_1147; // @[RegisterRouter.scala:87:24] wire out_f_roready_1147 = out_roready_1_1001 & out_romask_1147; // @[RegisterRouter.scala:87:24] wire _out_T_11081 = out_f_roready_1147; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1147 = out_wivalid_1_1001 & out_wimask_1147; // @[RegisterRouter.scala:87:24] wire out_f_woready_1147 = out_woready_1_1001 & out_womask_1147; // @[RegisterRouter.scala:87:24] wire _out_T_11082 = ~out_rimask_1147; // @[RegisterRouter.scala:87:24] wire _out_T_11083 = ~out_wimask_1147; // @[RegisterRouter.scala:87:24] wire _out_T_11084 = ~out_romask_1147; // @[RegisterRouter.scala:87:24] wire _out_T_11085 = ~out_womask_1147; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_984 = {hi_95, flags_0_go, _out_prepend_T_984}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11086 = out_prepend_984; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11087 = _out_T_11086; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_985 = _out_T_11087; // @[RegisterRouter.scala:87:24] wire out_rimask_1148 = \|_out_rimask_T_1148; // @[RegisterRouter.scala:87:24] wire out_wimask_1148 = &_out_wimask_T_1148; // @[RegisterRouter.scala:87:24] wire out_romask_1148 = \|_out_romask_T_1148; // @[RegisterRouter.scala:87:24] wire out_womask_1148 = &_out_womask_T_1148; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1148 = out_rivalid_1_1002 & out_rimask_1148; // @[RegisterRouter.scala:87:24] wire _out_T_11089 = out_f_rivalid_1148; // @[RegisterRouter.scala:87:24] wire out_f_roready_1148 = out_roready_1_1002 & out_romask_1148; // @[RegisterRouter.scala:87:24] wire _out_T_11090 = out_f_roready_1148; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1148 = out_wivalid_1_1002 & out_wimask_1148; // @[RegisterRouter.scala:87:24] wire out_f_woready_1148 = out_woready_1_1002 & out_womask_1148; // @[RegisterRouter.scala:87:24] wire _out_T_11091 = ~out_rimask_1148; // @[RegisterRouter.scala:87:24] wire _out_T_11092 = ~out_wimask_1148; // @[RegisterRouter.scala:87:24] wire _out_T_11093 = ~out_romask_1148; // @[RegisterRouter.scala:87:24] wire _out_T_11094 = ~out_womask_1148; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_985 = {hi_96, flags_0_go, _out_prepend_T_985}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11095 = out_prepend_985; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11096 = _out_T_11095; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_139 = _out_T_11096; // @[MuxLiteral.scala:49:48] wire out_rimask_1149 = \|_out_rimask_T_1149; // @[RegisterRouter.scala:87:24] wire out_wimask_1149 = &_out_wimask_T_1149; // @[RegisterRouter.scala:87:24] wire out_romask_1149 = \|_out_romask_T_1149; // @[RegisterRouter.scala:87:24] wire out_womask_1149 = &_out_womask_T_1149; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1149 = out_rivalid_1_1003 & out_rimask_1149; // @[RegisterRouter.scala:87:24] wire _out_T_11098 = out_f_rivalid_1149; // @[RegisterRouter.scala:87:24] wire out_f_roready_1149 = out_roready_1_1003 & out_romask_1149; // @[RegisterRouter.scala:87:24] wire _out_T_11099 = out_f_roready_1149; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1149 = out_wivalid_1_1003 & out_wimask_1149; // @[RegisterRouter.scala:87:24] wire out_f_woready_1149 = out_woready_1_1003 & out_womask_1149; // @[RegisterRouter.scala:87:24] wire _out_T_11100 = ~out_rimask_1149; // @[RegisterRouter.scala:87:24] wire _out_T_11101 = ~out_wimask_1149; // @[RegisterRouter.scala:87:24] wire _out_T_11102 = ~out_romask_1149; // @[RegisterRouter.scala:87:24] wire _out_T_11103 = ~out_womask_1149; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11105 = _out_T_11104; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_986 = _out_T_11105; // @[RegisterRouter.scala:87:24] wire out_rimask_1150 = \|_out_rimask_T_1150; // @[RegisterRouter.scala:87:24] wire out_wimask_1150 = &_out_wimask_T_1150; // @[RegisterRouter.scala:87:24] wire out_romask_1150 = \|_out_romask_T_1150; // @[RegisterRouter.scala:87:24] wire out_womask_1150 = &_out_womask_T_1150; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1150 = out_rivalid_1_1004 & out_rimask_1150; // @[RegisterRouter.scala:87:24] wire _out_T_11107 = out_f_rivalid_1150; // @[RegisterRouter.scala:87:24] wire out_f_roready_1150 = out_roready_1_1004 & out_romask_1150; // @[RegisterRouter.scala:87:24] wire _out_T_11108 = out_f_roready_1150; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1150 = out_wivalid_1_1004 & out_wimask_1150; // @[RegisterRouter.scala:87:24] wire out_f_woready_1150 = out_woready_1_1004 & out_womask_1150; // @[RegisterRouter.scala:87:24] wire _out_T_11109 = ~out_rimask_1150; // @[RegisterRouter.scala:87:24] wire _out_T_11110 = ~out_wimask_1150; // @[RegisterRouter.scala:87:24] wire _out_T_11111 = ~out_romask_1150; // @[RegisterRouter.scala:87:24] wire _out_T_11112 = ~out_womask_1150; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_986 = {hi_634, flags_0_go, _out_prepend_T_986}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11113 = out_prepend_986; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11114 = _out_T_11113; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_987 = _out_T_11114; // @[RegisterRouter.scala:87:24] wire out_rimask_1151 = \|_out_rimask_T_1151; // @[RegisterRouter.scala:87:24] wire out_wimask_1151 = &_out_wimask_T_1151; // @[RegisterRouter.scala:87:24] wire out_romask_1151 = \|_out_romask_T_1151; // @[RegisterRouter.scala:87:24] wire out_womask_1151 = &_out_womask_T_1151; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1151 = out_rivalid_1_1005 & out_rimask_1151; // @[RegisterRouter.scala:87:24] wire _out_T_11116 = out_f_rivalid_1151; // @[RegisterRouter.scala:87:24] wire out_f_roready_1151 = out_roready_1_1005 & out_romask_1151; // @[RegisterRouter.scala:87:24] wire _out_T_11117 = out_f_roready_1151; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1151 = out_wivalid_1_1005 & out_wimask_1151; // @[RegisterRouter.scala:87:24] wire out_f_woready_1151 = out_woready_1_1005 & out_womask_1151; // @[RegisterRouter.scala:87:24] wire _out_T_11118 = ~out_rimask_1151; // @[RegisterRouter.scala:87:24] wire _out_T_11119 = ~out_wimask_1151; // @[RegisterRouter.scala:87:24] wire _out_T_11120 = ~out_romask_1151; // @[RegisterRouter.scala:87:24] wire _out_T_11121 = ~out_womask_1151; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_987 = {hi_635, flags_0_go, _out_prepend_T_987}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11122 = out_prepend_987; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11123 = _out_T_11122; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_988 = _out_T_11123; // @[RegisterRouter.scala:87:24] wire out_rimask_1152 = \|_out_rimask_T_1152; // @[RegisterRouter.scala:87:24] wire out_wimask_1152 = &_out_wimask_T_1152; // @[RegisterRouter.scala:87:24] wire out_romask_1152 = \|_out_romask_T_1152; // @[RegisterRouter.scala:87:24] wire out_womask_1152 = &_out_womask_T_1152; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1152 = out_rivalid_1_1006 & out_rimask_1152; // @[RegisterRouter.scala:87:24] wire _out_T_11125 = out_f_rivalid_1152; // @[RegisterRouter.scala:87:24] wire out_f_roready_1152 = out_roready_1_1006 & out_romask_1152; // @[RegisterRouter.scala:87:24] wire _out_T_11126 = out_f_roready_1152; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1152 = out_wivalid_1_1006 & out_wimask_1152; // @[RegisterRouter.scala:87:24] wire out_f_woready_1152 = out_woready_1_1006 & out_womask_1152; // @[RegisterRouter.scala:87:24] wire _out_T_11127 = ~out_rimask_1152; // @[RegisterRouter.scala:87:24] wire _out_T_11128 = ~out_wimask_1152; // @[RegisterRouter.scala:87:24] wire _out_T_11129 = ~out_romask_1152; // @[RegisterRouter.scala:87:24] wire _out_T_11130 = ~out_womask_1152; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_988 = {hi_636, flags_0_go, _out_prepend_T_988}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11131 = out_prepend_988; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11132 = _out_T_11131; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_989 = _out_T_11132; // @[RegisterRouter.scala:87:24] wire out_rimask_1153 = \|_out_rimask_T_1153; // @[RegisterRouter.scala:87:24] wire out_wimask_1153 = &_out_wimask_T_1153; // @[RegisterRouter.scala:87:24] wire out_romask_1153 = \|_out_romask_T_1153; // @[RegisterRouter.scala:87:24] wire out_womask_1153 = &_out_womask_T_1153; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1153 = out_rivalid_1_1007 & out_rimask_1153; // @[RegisterRouter.scala:87:24] wire _out_T_11134 = out_f_rivalid_1153; // @[RegisterRouter.scala:87:24] wire out_f_roready_1153 = out_roready_1_1007 & out_romask_1153; // @[RegisterRouter.scala:87:24] wire _out_T_11135 = out_f_roready_1153; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1153 = out_wivalid_1_1007 & out_wimask_1153; // @[RegisterRouter.scala:87:24] wire out_f_woready_1153 = out_woready_1_1007 & out_womask_1153; // @[RegisterRouter.scala:87:24] wire _out_T_11136 = ~out_rimask_1153; // @[RegisterRouter.scala:87:24] wire _out_T_11137 = ~out_wimask_1153; // @[RegisterRouter.scala:87:24] wire _out_T_11138 = ~out_romask_1153; // @[RegisterRouter.scala:87:24] wire _out_T_11139 = ~out_womask_1153; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_989 = {hi_637, flags_0_go, _out_prepend_T_989}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11140 = out_prepend_989; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11141 = _out_T_11140; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_990 = _out_T_11141; // @[RegisterRouter.scala:87:24] wire out_rimask_1154 = \|_out_rimask_T_1154; // @[RegisterRouter.scala:87:24] wire out_wimask_1154 = &_out_wimask_T_1154; // @[RegisterRouter.scala:87:24] wire out_romask_1154 = \|_out_romask_T_1154; // @[RegisterRouter.scala:87:24] wire out_womask_1154 = &_out_womask_T_1154; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1154 = out_rivalid_1_1008 & out_rimask_1154; // @[RegisterRouter.scala:87:24] wire _out_T_11143 = out_f_rivalid_1154; // @[RegisterRouter.scala:87:24] wire out_f_roready_1154 = out_roready_1_1008 & out_romask_1154; // @[RegisterRouter.scala:87:24] wire _out_T_11144 = out_f_roready_1154; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1154 = out_wivalid_1_1008 & out_wimask_1154; // @[RegisterRouter.scala:87:24] wire out_f_woready_1154 = out_woready_1_1008 & out_womask_1154; // @[RegisterRouter.scala:87:24] wire _out_T_11145 = ~out_rimask_1154; // @[RegisterRouter.scala:87:24] wire _out_T_11146 = ~out_wimask_1154; // @[RegisterRouter.scala:87:24] wire _out_T_11147 = ~out_romask_1154; // @[RegisterRouter.scala:87:24] wire _out_T_11148 = ~out_womask_1154; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_990 = {hi_638, flags_0_go, _out_prepend_T_990}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11149 = out_prepend_990; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11150 = _out_T_11149; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_991 = _out_T_11150; // @[RegisterRouter.scala:87:24] wire out_rimask_1155 = \|_out_rimask_T_1155; // @[RegisterRouter.scala:87:24] wire out_wimask_1155 = &_out_wimask_T_1155; // @[RegisterRouter.scala:87:24] wire out_romask_1155 = \|_out_romask_T_1155; // @[RegisterRouter.scala:87:24] wire out_womask_1155 = &_out_womask_T_1155; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1155 = out_rivalid_1_1009 & out_rimask_1155; // @[RegisterRouter.scala:87:24] wire _out_T_11152 = out_f_rivalid_1155; // @[RegisterRouter.scala:87:24] wire out_f_roready_1155 = out_roready_1_1009 & out_romask_1155; // @[RegisterRouter.scala:87:24] wire _out_T_11153 = out_f_roready_1155; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1155 = out_wivalid_1_1009 & out_wimask_1155; // @[RegisterRouter.scala:87:24] wire out_f_woready_1155 = out_woready_1_1009 & out_womask_1155; // @[RegisterRouter.scala:87:24] wire _out_T_11154 = ~out_rimask_1155; // @[RegisterRouter.scala:87:24] wire _out_T_11155 = ~out_wimask_1155; // @[RegisterRouter.scala:87:24] wire _out_T_11156 = ~out_romask_1155; // @[RegisterRouter.scala:87:24] wire _out_T_11157 = ~out_womask_1155; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_991 = {hi_639, flags_0_go, _out_prepend_T_991}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11158 = out_prepend_991; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11159 = _out_T_11158; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_992 = _out_T_11159; // @[RegisterRouter.scala:87:24] wire out_rimask_1156 = \|_out_rimask_T_1156; // @[RegisterRouter.scala:87:24] wire out_wimask_1156 = &_out_wimask_T_1156; // @[RegisterRouter.scala:87:24] wire out_romask_1156 = \|_out_romask_T_1156; // @[RegisterRouter.scala:87:24] wire out_womask_1156 = &_out_womask_T_1156; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1156 = out_rivalid_1_1010 & out_rimask_1156; // @[RegisterRouter.scala:87:24] wire _out_T_11161 = out_f_rivalid_1156; // @[RegisterRouter.scala:87:24] wire out_f_roready_1156 = out_roready_1_1010 & out_romask_1156; // @[RegisterRouter.scala:87:24] wire _out_T_11162 = out_f_roready_1156; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1156 = out_wivalid_1_1010 & out_wimask_1156; // @[RegisterRouter.scala:87:24] wire out_f_woready_1156 = out_woready_1_1010 & out_womask_1156; // @[RegisterRouter.scala:87:24] wire _out_T_11163 = ~out_rimask_1156; // @[RegisterRouter.scala:87:24] wire _out_T_11164 = ~out_wimask_1156; // @[RegisterRouter.scala:87:24] wire _out_T_11165 = ~out_romask_1156; // @[RegisterRouter.scala:87:24] wire _out_T_11166 = ~out_womask_1156; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_992 = {hi_640, flags_0_go, _out_prepend_T_992}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11167 = out_prepend_992; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11168 = _out_T_11167; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_207 = _out_T_11168; // @[MuxLiteral.scala:49:48] wire out_rimask_1157 = \|_out_rimask_T_1157; // @[RegisterRouter.scala:87:24] wire out_wimask_1157 = &_out_wimask_T_1157; // @[RegisterRouter.scala:87:24] wire out_romask_1157 = \|_out_romask_T_1157; // @[RegisterRouter.scala:87:24] wire out_womask_1157 = &_out_womask_T_1157; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1157 = out_rivalid_1_1011 & out_rimask_1157; // @[RegisterRouter.scala:87:24] wire _out_T_11170 = out_f_rivalid_1157; // @[RegisterRouter.scala:87:24] wire out_f_roready_1157 = out_roready_1_1011 & out_romask_1157; // @[RegisterRouter.scala:87:24] wire _out_T_11171 = out_f_roready_1157; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1157 = out_wivalid_1_1011 & out_wimask_1157; // @[RegisterRouter.scala:87:24] wire out_f_woready_1157 = out_woready_1_1011 & out_womask_1157; // @[RegisterRouter.scala:87:24] wire _out_T_11172 = ~out_rimask_1157; // @[RegisterRouter.scala:87:24] wire _out_T_11173 = ~out_wimask_1157; // @[RegisterRouter.scala:87:24] wire _out_T_11174 = ~out_romask_1157; // @[RegisterRouter.scala:87:24] wire _out_T_11175 = ~out_womask_1157; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11177 = _out_T_11176; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_993 = _out_T_11177; // @[RegisterRouter.scala:87:24] wire out_rimask_1158 = \|_out_rimask_T_1158; // @[RegisterRouter.scala:87:24] wire out_wimask_1158 = &_out_wimask_T_1158; // @[RegisterRouter.scala:87:24] wire out_romask_1158 = \|_out_romask_T_1158; // @[RegisterRouter.scala:87:24] wire out_womask_1158 = &_out_womask_T_1158; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1158 = out_rivalid_1_1012 & out_rimask_1158; // @[RegisterRouter.scala:87:24] wire _out_T_11179 = out_f_rivalid_1158; // @[RegisterRouter.scala:87:24] wire out_f_roready_1158 = out_roready_1_1012 & out_romask_1158; // @[RegisterRouter.scala:87:24] wire _out_T_11180 = out_f_roready_1158; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1158 = out_wivalid_1_1012 & out_wimask_1158; // @[RegisterRouter.scala:87:24] wire out_f_woready_1158 = out_woready_1_1012 & out_womask_1158; // @[RegisterRouter.scala:87:24] wire _out_T_11181 = ~out_rimask_1158; // @[RegisterRouter.scala:87:24] wire _out_T_11182 = ~out_wimask_1158; // @[RegisterRouter.scala:87:24] wire _out_T_11183 = ~out_romask_1158; // @[RegisterRouter.scala:87:24] wire _out_T_11184 = ~out_womask_1158; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_993 = {hi_690, flags_0_go, _out_prepend_T_993}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11185 = out_prepend_993; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11186 = _out_T_11185; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_994 = _out_T_11186; // @[RegisterRouter.scala:87:24] wire out_rimask_1159 = \|_out_rimask_T_1159; // @[RegisterRouter.scala:87:24] wire out_wimask_1159 = &_out_wimask_T_1159; // @[RegisterRouter.scala:87:24] wire out_romask_1159 = \|_out_romask_T_1159; // @[RegisterRouter.scala:87:24] wire out_womask_1159 = &_out_womask_T_1159; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1159 = out_rivalid_1_1013 & out_rimask_1159; // @[RegisterRouter.scala:87:24] wire _out_T_11188 = out_f_rivalid_1159; // @[RegisterRouter.scala:87:24] wire out_f_roready_1159 = out_roready_1_1013 & out_romask_1159; // @[RegisterRouter.scala:87:24] wire _out_T_11189 = out_f_roready_1159; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1159 = out_wivalid_1_1013 & out_wimask_1159; // @[RegisterRouter.scala:87:24] wire out_f_woready_1159 = out_woready_1_1013 & out_womask_1159; // @[RegisterRouter.scala:87:24] wire _out_T_11190 = ~out_rimask_1159; // @[RegisterRouter.scala:87:24] wire _out_T_11191 = ~out_wimask_1159; // @[RegisterRouter.scala:87:24] wire _out_T_11192 = ~out_romask_1159; // @[RegisterRouter.scala:87:24] wire _out_T_11193 = ~out_womask_1159; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_994 = {hi_691, flags_0_go, _out_prepend_T_994}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11194 = out_prepend_994; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11195 = _out_T_11194; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_995 = _out_T_11195; // @[RegisterRouter.scala:87:24] wire out_rimask_1160 = \|_out_rimask_T_1160; // @[RegisterRouter.scala:87:24] wire out_wimask_1160 = &_out_wimask_T_1160; // @[RegisterRouter.scala:87:24] wire out_romask_1160 = \|_out_romask_T_1160; // @[RegisterRouter.scala:87:24] wire out_womask_1160 = &_out_womask_T_1160; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1160 = out_rivalid_1_1014 & out_rimask_1160; // @[RegisterRouter.scala:87:24] wire _out_T_11197 = out_f_rivalid_1160; // @[RegisterRouter.scala:87:24] wire out_f_roready_1160 = out_roready_1_1014 & out_romask_1160; // @[RegisterRouter.scala:87:24] wire _out_T_11198 = out_f_roready_1160; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1160 = out_wivalid_1_1014 & out_wimask_1160; // @[RegisterRouter.scala:87:24] wire out_f_woready_1160 = out_woready_1_1014 & out_womask_1160; // @[RegisterRouter.scala:87:24] wire _out_T_11199 = ~out_rimask_1160; // @[RegisterRouter.scala:87:24] wire _out_T_11200 = ~out_wimask_1160; // @[RegisterRouter.scala:87:24] wire _out_T_11201 = ~out_romask_1160; // @[RegisterRouter.scala:87:24] wire _out_T_11202 = ~out_womask_1160; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_995 = {hi_692, flags_0_go, _out_prepend_T_995}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11203 = out_prepend_995; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11204 = _out_T_11203; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_996 = _out_T_11204; // @[RegisterRouter.scala:87:24] wire out_rimask_1161 = \|_out_rimask_T_1161; // @[RegisterRouter.scala:87:24] wire out_wimask_1161 = &_out_wimask_T_1161; // @[RegisterRouter.scala:87:24] wire out_romask_1161 = \|_out_romask_T_1161; // @[RegisterRouter.scala:87:24] wire out_womask_1161 = &_out_womask_T_1161; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1161 = out_rivalid_1_1015 & out_rimask_1161; // @[RegisterRouter.scala:87:24] wire _out_T_11206 = out_f_rivalid_1161; // @[RegisterRouter.scala:87:24] wire out_f_roready_1161 = out_roready_1_1015 & out_romask_1161; // @[RegisterRouter.scala:87:24] wire _out_T_11207 = out_f_roready_1161; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1161 = out_wivalid_1_1015 & out_wimask_1161; // @[RegisterRouter.scala:87:24] wire out_f_woready_1161 = out_woready_1_1015 & out_womask_1161; // @[RegisterRouter.scala:87:24] wire _out_T_11208 = ~out_rimask_1161; // @[RegisterRouter.scala:87:24] wire _out_T_11209 = ~out_wimask_1161; // @[RegisterRouter.scala:87:24] wire _out_T_11210 = ~out_romask_1161; // @[RegisterRouter.scala:87:24] wire _out_T_11211 = ~out_womask_1161; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_996 = {hi_693, flags_0_go, _out_prepend_T_996}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11212 = out_prepend_996; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11213 = _out_T_11212; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_997 = _out_T_11213; // @[RegisterRouter.scala:87:24] wire out_rimask_1162 = \|_out_rimask_T_1162; // @[RegisterRouter.scala:87:24] wire out_wimask_1162 = &_out_wimask_T_1162; // @[RegisterRouter.scala:87:24] wire out_romask_1162 = \|_out_romask_T_1162; // @[RegisterRouter.scala:87:24] wire out_womask_1162 = &_out_womask_T_1162; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1162 = out_rivalid_1_1016 & out_rimask_1162; // @[RegisterRouter.scala:87:24] wire _out_T_11215 = out_f_rivalid_1162; // @[RegisterRouter.scala:87:24] wire out_f_roready_1162 = out_roready_1_1016 & out_romask_1162; // @[RegisterRouter.scala:87:24] wire _out_T_11216 = out_f_roready_1162; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1162 = out_wivalid_1_1016 & out_wimask_1162; // @[RegisterRouter.scala:87:24] wire out_f_woready_1162 = out_woready_1_1016 & out_womask_1162; // @[RegisterRouter.scala:87:24] wire _out_T_11217 = ~out_rimask_1162; // @[RegisterRouter.scala:87:24] wire _out_T_11218 = ~out_wimask_1162; // @[RegisterRouter.scala:87:24] wire _out_T_11219 = ~out_romask_1162; // @[RegisterRouter.scala:87:24] wire _out_T_11220 = ~out_womask_1162; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_997 = {hi_694, flags_0_go, _out_prepend_T_997}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11221 = out_prepend_997; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11222 = _out_T_11221; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_998 = _out_T_11222; // @[RegisterRouter.scala:87:24] wire out_rimask_1163 = \|_out_rimask_T_1163; // @[RegisterRouter.scala:87:24] wire out_wimask_1163 = &_out_wimask_T_1163; // @[RegisterRouter.scala:87:24] wire out_romask_1163 = \|_out_romask_T_1163; // @[RegisterRouter.scala:87:24] wire out_womask_1163 = &_out_womask_T_1163; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1163 = out_rivalid_1_1017 & out_rimask_1163; // @[RegisterRouter.scala:87:24] wire _out_T_11224 = out_f_rivalid_1163; // @[RegisterRouter.scala:87:24] wire out_f_roready_1163 = out_roready_1_1017 & out_romask_1163; // @[RegisterRouter.scala:87:24] wire _out_T_11225 = out_f_roready_1163; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1163 = out_wivalid_1_1017 & out_wimask_1163; // @[RegisterRouter.scala:87:24] wire out_f_woready_1163 = out_woready_1_1017 & out_womask_1163; // @[RegisterRouter.scala:87:24] wire _out_T_11226 = ~out_rimask_1163; // @[RegisterRouter.scala:87:24] wire _out_T_11227 = ~out_wimask_1163; // @[RegisterRouter.scala:87:24] wire _out_T_11228 = ~out_romask_1163; // @[RegisterRouter.scala:87:24] wire _out_T_11229 = ~out_womask_1163; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_998 = {hi_695, flags_0_go, _out_prepend_T_998}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11230 = out_prepend_998; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11231 = _out_T_11230; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_999 = _out_T_11231; // @[RegisterRouter.scala:87:24] wire out_rimask_1164 = \|_out_rimask_T_1164; // @[RegisterRouter.scala:87:24] wire out_wimask_1164 = &_out_wimask_T_1164; // @[RegisterRouter.scala:87:24] wire out_romask_1164 = \|_out_romask_T_1164; // @[RegisterRouter.scala:87:24] wire out_womask_1164 = &_out_womask_T_1164; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1164 = out_rivalid_1_1018 & out_rimask_1164; // @[RegisterRouter.scala:87:24] wire _out_T_11233 = out_f_rivalid_1164; // @[RegisterRouter.scala:87:24] wire out_f_roready_1164 = out_roready_1_1018 & out_romask_1164; // @[RegisterRouter.scala:87:24] wire _out_T_11234 = out_f_roready_1164; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1164 = out_wivalid_1_1018 & out_wimask_1164; // @[RegisterRouter.scala:87:24] wire out_f_woready_1164 = out_woready_1_1018 & out_womask_1164; // @[RegisterRouter.scala:87:24] wire _out_T_11235 = ~out_rimask_1164; // @[RegisterRouter.scala:87:24] wire _out_T_11236 = ~out_wimask_1164; // @[RegisterRouter.scala:87:24] wire _out_T_11237 = ~out_romask_1164; // @[RegisterRouter.scala:87:24] wire _out_T_11238 = ~out_womask_1164; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_999 = {hi_696, flags_0_go, _out_prepend_T_999}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11239 = out_prepend_999; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11240 = _out_T_11239; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_214 = _out_T_11240; // @[MuxLiteral.scala:49:48] wire out_rimask_1165 = \|_out_rimask_T_1165; // @[RegisterRouter.scala:87:24] wire out_wimask_1165 = &_out_wimask_T_1165; // @[RegisterRouter.scala:87:24] wire out_romask_1165 = \|_out_romask_T_1165; // @[RegisterRouter.scala:87:24] wire out_womask_1165 = &_out_womask_T_1165; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1165 = out_rivalid_1_1019 & out_rimask_1165; // @[RegisterRouter.scala:87:24] wire _out_T_11242 = out_f_rivalid_1165; // @[RegisterRouter.scala:87:24] wire out_f_roready_1165 = out_roready_1_1019 & out_romask_1165; // @[RegisterRouter.scala:87:24] wire _out_T_11243 = out_f_roready_1165; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1165 = out_wivalid_1_1019 & out_wimask_1165; // @[RegisterRouter.scala:87:24] wire out_f_woready_1165 = out_woready_1_1019 & out_womask_1165; // @[RegisterRouter.scala:87:24] wire _out_T_11244 = ~out_rimask_1165; // @[RegisterRouter.scala:87:24] wire _out_T_11245 = ~out_wimask_1165; // @[RegisterRouter.scala:87:24] wire _out_T_11246 = ~out_romask_1165; // @[RegisterRouter.scala:87:24] wire _out_T_11247 = ~out_womask_1165; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11249 = _out_T_11248; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1000 = _out_T_11249; // @[RegisterRouter.scala:87:24] wire out_rimask_1166 = \|_out_rimask_T_1166; // @[RegisterRouter.scala:87:24] wire out_wimask_1166 = &_out_wimask_T_1166; // @[RegisterRouter.scala:87:24] wire out_romask_1166 = \|_out_romask_T_1166; // @[RegisterRouter.scala:87:24] wire out_womask_1166 = &_out_womask_T_1166; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1166 = out_rivalid_1_1020 & out_rimask_1166; // @[RegisterRouter.scala:87:24] wire _out_T_11251 = out_f_rivalid_1166; // @[RegisterRouter.scala:87:24] wire out_f_roready_1166 = out_roready_1_1020 & out_romask_1166; // @[RegisterRouter.scala:87:24] wire _out_T_11252 = out_f_roready_1166; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1166 = out_wivalid_1_1020 & out_wimask_1166; // @[RegisterRouter.scala:87:24] wire out_f_woready_1166 = out_woready_1_1020 & out_womask_1166; // @[RegisterRouter.scala:87:24] wire _out_T_11253 = ~out_rimask_1166; // @[RegisterRouter.scala:87:24] wire _out_T_11254 = ~out_wimask_1166; // @[RegisterRouter.scala:87:24] wire _out_T_11255 = ~out_romask_1166; // @[RegisterRouter.scala:87:24] wire _out_T_11256 = ~out_womask_1166; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1000 = {hi_858, flags_0_go, _out_prepend_T_1000}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11257 = out_prepend_1000; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11258 = _out_T_11257; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1001 = _out_T_11258; // @[RegisterRouter.scala:87:24] wire out_rimask_1167 = \|_out_rimask_T_1167; // @[RegisterRouter.scala:87:24] wire out_wimask_1167 = &_out_wimask_T_1167; // @[RegisterRouter.scala:87:24] wire out_romask_1167 = \|_out_romask_T_1167; // @[RegisterRouter.scala:87:24] wire out_womask_1167 = &_out_womask_T_1167; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1167 = out_rivalid_1_1021 & out_rimask_1167; // @[RegisterRouter.scala:87:24] wire _out_T_11260 = out_f_rivalid_1167; // @[RegisterRouter.scala:87:24] wire out_f_roready_1167 = out_roready_1_1021 & out_romask_1167; // @[RegisterRouter.scala:87:24] wire _out_T_11261 = out_f_roready_1167; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1167 = out_wivalid_1_1021 & out_wimask_1167; // @[RegisterRouter.scala:87:24] wire out_f_woready_1167 = out_woready_1_1021 & out_womask_1167; // @[RegisterRouter.scala:87:24] wire _out_T_11262 = ~out_rimask_1167; // @[RegisterRouter.scala:87:24] wire _out_T_11263 = ~out_wimask_1167; // @[RegisterRouter.scala:87:24] wire _out_T_11264 = ~out_romask_1167; // @[RegisterRouter.scala:87:24] wire _out_T_11265 = ~out_womask_1167; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1001 = {hi_859, flags_0_go, _out_prepend_T_1001}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11266 = out_prepend_1001; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11267 = _out_T_11266; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1002 = _out_T_11267; // @[RegisterRouter.scala:87:24] wire out_rimask_1168 = \|_out_rimask_T_1168; // @[RegisterRouter.scala:87:24] wire out_wimask_1168 = &_out_wimask_T_1168; // @[RegisterRouter.scala:87:24] wire out_romask_1168 = \|_out_romask_T_1168; // @[RegisterRouter.scala:87:24] wire out_womask_1168 = &_out_womask_T_1168; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1168 = out_rivalid_1_1022 & out_rimask_1168; // @[RegisterRouter.scala:87:24] wire _out_T_11269 = out_f_rivalid_1168; // @[RegisterRouter.scala:87:24] wire out_f_roready_1168 = out_roready_1_1022 & out_romask_1168; // @[RegisterRouter.scala:87:24] wire _out_T_11270 = out_f_roready_1168; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1168 = out_wivalid_1_1022 & out_wimask_1168; // @[RegisterRouter.scala:87:24] wire out_f_woready_1168 = out_woready_1_1022 & out_womask_1168; // @[RegisterRouter.scala:87:24] wire _out_T_11271 = ~out_rimask_1168; // @[RegisterRouter.scala:87:24] wire _out_T_11272 = ~out_wimask_1168; // @[RegisterRouter.scala:87:24] wire _out_T_11273 = ~out_romask_1168; // @[RegisterRouter.scala:87:24] wire _out_T_11274 = ~out_womask_1168; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1002 = {hi_860, flags_0_go, _out_prepend_T_1002}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11275 = out_prepend_1002; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11276 = _out_T_11275; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1003 = _out_T_11276; // @[RegisterRouter.scala:87:24] wire out_rimask_1169 = \|_out_rimask_T_1169; // @[RegisterRouter.scala:87:24] wire out_wimask_1169 = &_out_wimask_T_1169; // @[RegisterRouter.scala:87:24] wire out_romask_1169 = \|_out_romask_T_1169; // @[RegisterRouter.scala:87:24] wire out_womask_1169 = &_out_womask_T_1169; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1169 = out_rivalid_1_1023 & out_rimask_1169; // @[RegisterRouter.scala:87:24] wire _out_T_11278 = out_f_rivalid_1169; // @[RegisterRouter.scala:87:24] wire out_f_roready_1169 = out_roready_1_1023 & out_romask_1169; // @[RegisterRouter.scala:87:24] wire _out_T_11279 = out_f_roready_1169; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1169 = out_wivalid_1_1023 & out_wimask_1169; // @[RegisterRouter.scala:87:24] wire out_f_woready_1169 = out_woready_1_1023 & out_womask_1169; // @[RegisterRouter.scala:87:24] wire _out_T_11280 = ~out_rimask_1169; // @[RegisterRouter.scala:87:24] wire _out_T_11281 = ~out_wimask_1169; // @[RegisterRouter.scala:87:24] wire _out_T_11282 = ~out_romask_1169; // @[RegisterRouter.scala:87:24] wire _out_T_11283 = ~out_womask_1169; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1003 = {hi_861, flags_0_go, _out_prepend_T_1003}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11284 = out_prepend_1003; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11285 = _out_T_11284; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1004 = _out_T_11285; // @[RegisterRouter.scala:87:24] wire out_rimask_1170 = \|_out_rimask_T_1170; // @[RegisterRouter.scala:87:24] wire out_wimask_1170 = &_out_wimask_T_1170; // @[RegisterRouter.scala:87:24] wire out_romask_1170 = \|_out_romask_T_1170; // @[RegisterRouter.scala:87:24] wire out_womask_1170 = &_out_womask_T_1170; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1170 = out_rivalid_1_1024 & out_rimask_1170; // @[RegisterRouter.scala:87:24] wire _out_T_11287 = out_f_rivalid_1170; // @[RegisterRouter.scala:87:24] wire out_f_roready_1170 = out_roready_1_1024 & out_romask_1170; // @[RegisterRouter.scala:87:24] wire _out_T_11288 = out_f_roready_1170; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1170 = out_wivalid_1_1024 & out_wimask_1170; // @[RegisterRouter.scala:87:24] wire out_f_woready_1170 = out_woready_1_1024 & out_womask_1170; // @[RegisterRouter.scala:87:24] wire _out_T_11289 = ~out_rimask_1170; // @[RegisterRouter.scala:87:24] wire _out_T_11290 = ~out_wimask_1170; // @[RegisterRouter.scala:87:24] wire _out_T_11291 = ~out_romask_1170; // @[RegisterRouter.scala:87:24] wire _out_T_11292 = ~out_womask_1170; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1004 = {hi_862, flags_0_go, _out_prepend_T_1004}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11293 = out_prepend_1004; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11294 = _out_T_11293; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1005 = _out_T_11294; // @[RegisterRouter.scala:87:24] wire out_rimask_1171 = \|_out_rimask_T_1171; // @[RegisterRouter.scala:87:24] wire out_wimask_1171 = &_out_wimask_T_1171; // @[RegisterRouter.scala:87:24] wire out_romask_1171 = \|_out_romask_T_1171; // @[RegisterRouter.scala:87:24] wire out_womask_1171 = &_out_womask_T_1171; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1171 = out_rivalid_1_1025 & out_rimask_1171; // @[RegisterRouter.scala:87:24] wire _out_T_11296 = out_f_rivalid_1171; // @[RegisterRouter.scala:87:24] wire out_f_roready_1171 = out_roready_1_1025 & out_romask_1171; // @[RegisterRouter.scala:87:24] wire _out_T_11297 = out_f_roready_1171; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1171 = out_wivalid_1_1025 & out_wimask_1171; // @[RegisterRouter.scala:87:24] wire out_f_woready_1171 = out_woready_1_1025 & out_womask_1171; // @[RegisterRouter.scala:87:24] wire _out_T_11298 = ~out_rimask_1171; // @[RegisterRouter.scala:87:24] wire _out_T_11299 = ~out_wimask_1171; // @[RegisterRouter.scala:87:24] wire _out_T_11300 = ~out_romask_1171; // @[RegisterRouter.scala:87:24] wire _out_T_11301 = ~out_womask_1171; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1005 = {hi_863, flags_0_go, _out_prepend_T_1005}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11302 = out_prepend_1005; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11303 = _out_T_11302; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1006 = _out_T_11303; // @[RegisterRouter.scala:87:24] wire out_rimask_1172 = \|_out_rimask_T_1172; // @[RegisterRouter.scala:87:24] wire out_wimask_1172 = &_out_wimask_T_1172; // @[RegisterRouter.scala:87:24] wire out_romask_1172 = \|_out_romask_T_1172; // @[RegisterRouter.scala:87:24] wire out_womask_1172 = &_out_womask_T_1172; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1172 = out_rivalid_1_1026 & out_rimask_1172; // @[RegisterRouter.scala:87:24] wire _out_T_11305 = out_f_rivalid_1172; // @[RegisterRouter.scala:87:24] wire out_f_roready_1172 = out_roready_1_1026 & out_romask_1172; // @[RegisterRouter.scala:87:24] wire _out_T_11306 = out_f_roready_1172; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1172 = out_wivalid_1_1026 & out_wimask_1172; // @[RegisterRouter.scala:87:24] wire out_f_woready_1172 = out_woready_1_1026 & out_womask_1172; // @[RegisterRouter.scala:87:24] wire _out_T_11307 = ~out_rimask_1172; // @[RegisterRouter.scala:87:24] wire _out_T_11308 = ~out_wimask_1172; // @[RegisterRouter.scala:87:24] wire _out_T_11309 = ~out_romask_1172; // @[RegisterRouter.scala:87:24] wire _out_T_11310 = ~out_womask_1172; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1006 = {hi_864, flags_0_go, _out_prepend_T_1006}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11311 = out_prepend_1006; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11312 = _out_T_11311; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_235 = _out_T_11312; // @[MuxLiteral.scala:49:48] wire out_rimask_1173 = \|_out_rimask_T_1173; // @[RegisterRouter.scala:87:24] wire out_wimask_1173 = &_out_wimask_T_1173; // @[RegisterRouter.scala:87:24] wire out_romask_1173 = \|_out_romask_T_1173; // @[RegisterRouter.scala:87:24] wire out_womask_1173 = &_out_womask_T_1173; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1173 = out_rivalid_1_1027 & out_rimask_1173; // @[RegisterRouter.scala:87:24] wire _out_T_11314 = out_f_rivalid_1173; // @[RegisterRouter.scala:87:24] wire out_f_roready_1173 = out_roready_1_1027 & out_romask_1173; // @[RegisterRouter.scala:87:24] wire _out_T_11315 = out_f_roready_1173; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1173 = out_wivalid_1_1027 & out_wimask_1173; // @[RegisterRouter.scala:87:24] wire out_f_woready_1173 = out_woready_1_1027 & out_womask_1173; // @[RegisterRouter.scala:87:24] wire _out_T_11316 = ~out_rimask_1173; // @[RegisterRouter.scala:87:24] wire _out_T_11317 = ~out_wimask_1173; // @[RegisterRouter.scala:87:24] wire _out_T_11318 = ~out_romask_1173; // @[RegisterRouter.scala:87:24] wire _out_T_11319 = ~out_womask_1173; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11321 = _out_T_11320; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1007 = _out_T_11321; // @[RegisterRouter.scala:87:24] wire out_rimask_1174 = \|_out_rimask_T_1174; // @[RegisterRouter.scala:87:24] wire out_wimask_1174 = &_out_wimask_T_1174; // @[RegisterRouter.scala:87:24] wire out_romask_1174 = \|_out_romask_T_1174; // @[RegisterRouter.scala:87:24] wire out_womask_1174 = &_out_womask_T_1174; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1174 = out_rivalid_1_1028 & out_rimask_1174; // @[RegisterRouter.scala:87:24] wire _out_T_11323 = out_f_rivalid_1174; // @[RegisterRouter.scala:87:24] wire out_f_roready_1174 = out_roready_1_1028 & out_romask_1174; // @[RegisterRouter.scala:87:24] wire _out_T_11324 = out_f_roready_1174; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1174 = out_wivalid_1_1028 & out_wimask_1174; // @[RegisterRouter.scala:87:24] wire out_f_woready_1174 = out_woready_1_1028 & out_womask_1174; // @[RegisterRouter.scala:87:24] wire _out_T_11325 = ~out_rimask_1174; // @[RegisterRouter.scala:87:24] wire _out_T_11326 = ~out_wimask_1174; // @[RegisterRouter.scala:87:24] wire _out_T_11327 = ~out_romask_1174; // @[RegisterRouter.scala:87:24] wire _out_T_11328 = ~out_womask_1174; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1007 = {hi_946, flags_0_go, _out_prepend_T_1007}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11329 = out_prepend_1007; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11330 = _out_T_11329; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1008 = _out_T_11330; // @[RegisterRouter.scala:87:24] wire out_rimask_1175 = \|_out_rimask_T_1175; // @[RegisterRouter.scala:87:24] wire out_wimask_1175 = &_out_wimask_T_1175; // @[RegisterRouter.scala:87:24] wire out_romask_1175 = \|_out_romask_T_1175; // @[RegisterRouter.scala:87:24] wire out_womask_1175 = &_out_womask_T_1175; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1175 = out_rivalid_1_1029 & out_rimask_1175; // @[RegisterRouter.scala:87:24] wire _out_T_11332 = out_f_rivalid_1175; // @[RegisterRouter.scala:87:24] wire out_f_roready_1175 = out_roready_1_1029 & out_romask_1175; // @[RegisterRouter.scala:87:24] wire _out_T_11333 = out_f_roready_1175; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1175 = out_wivalid_1_1029 & out_wimask_1175; // @[RegisterRouter.scala:87:24] wire out_f_woready_1175 = out_woready_1_1029 & out_womask_1175; // @[RegisterRouter.scala:87:24] wire _out_T_11334 = ~out_rimask_1175; // @[RegisterRouter.scala:87:24] wire _out_T_11335 = ~out_wimask_1175; // @[RegisterRouter.scala:87:24] wire _out_T_11336 = ~out_romask_1175; // @[RegisterRouter.scala:87:24] wire _out_T_11337 = ~out_womask_1175; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1008 = {hi_947, flags_0_go, _out_prepend_T_1008}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11338 = out_prepend_1008; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11339 = _out_T_11338; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1009 = _out_T_11339; // @[RegisterRouter.scala:87:24] wire out_rimask_1176 = \|_out_rimask_T_1176; // @[RegisterRouter.scala:87:24] wire out_wimask_1176 = &_out_wimask_T_1176; // @[RegisterRouter.scala:87:24] wire out_romask_1176 = \|_out_romask_T_1176; // @[RegisterRouter.scala:87:24] wire out_womask_1176 = &_out_womask_T_1176; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1176 = out_rivalid_1_1030 & out_rimask_1176; // @[RegisterRouter.scala:87:24] wire _out_T_11341 = out_f_rivalid_1176; // @[RegisterRouter.scala:87:24] wire out_f_roready_1176 = out_roready_1_1030 & out_romask_1176; // @[RegisterRouter.scala:87:24] wire _out_T_11342 = out_f_roready_1176; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1176 = out_wivalid_1_1030 & out_wimask_1176; // @[RegisterRouter.scala:87:24] wire out_f_woready_1176 = out_woready_1_1030 & out_womask_1176; // @[RegisterRouter.scala:87:24] wire _out_T_11343 = ~out_rimask_1176; // @[RegisterRouter.scala:87:24] wire _out_T_11344 = ~out_wimask_1176; // @[RegisterRouter.scala:87:24] wire _out_T_11345 = ~out_romask_1176; // @[RegisterRouter.scala:87:24] wire _out_T_11346 = ~out_womask_1176; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1009 = {hi_948, flags_0_go, _out_prepend_T_1009}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11347 = out_prepend_1009; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11348 = _out_T_11347; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1010 = _out_T_11348; // @[RegisterRouter.scala:87:24] wire out_rimask_1177 = \|_out_rimask_T_1177; // @[RegisterRouter.scala:87:24] wire out_wimask_1177 = &_out_wimask_T_1177; // @[RegisterRouter.scala:87:24] wire out_romask_1177 = \|_out_romask_T_1177; // @[RegisterRouter.scala:87:24] wire out_womask_1177 = &_out_womask_T_1177; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1177 = out_rivalid_1_1031 & out_rimask_1177; // @[RegisterRouter.scala:87:24] wire _out_T_11350 = out_f_rivalid_1177; // @[RegisterRouter.scala:87:24] wire out_f_roready_1177 = out_roready_1_1031 & out_romask_1177; // @[RegisterRouter.scala:87:24] wire _out_T_11351 = out_f_roready_1177; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1177 = out_wivalid_1_1031 & out_wimask_1177; // @[RegisterRouter.scala:87:24] wire out_f_woready_1177 = out_woready_1_1031 & out_womask_1177; // @[RegisterRouter.scala:87:24] wire _out_T_11352 = ~out_rimask_1177; // @[RegisterRouter.scala:87:24] wire _out_T_11353 = ~out_wimask_1177; // @[RegisterRouter.scala:87:24] wire _out_T_11354 = ~out_romask_1177; // @[RegisterRouter.scala:87:24] wire _out_T_11355 = ~out_womask_1177; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1010 = {hi_949, flags_0_go, _out_prepend_T_1010}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11356 = out_prepend_1010; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11357 = _out_T_11356; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1011 = _out_T_11357; // @[RegisterRouter.scala:87:24] wire out_rimask_1178 = \|_out_rimask_T_1178; // @[RegisterRouter.scala:87:24] wire out_wimask_1178 = &_out_wimask_T_1178; // @[RegisterRouter.scala:87:24] wire out_romask_1178 = \|_out_romask_T_1178; // @[RegisterRouter.scala:87:24] wire out_womask_1178 = &_out_womask_T_1178; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1178 = out_rivalid_1_1032 & out_rimask_1178; // @[RegisterRouter.scala:87:24] wire _out_T_11359 = out_f_rivalid_1178; // @[RegisterRouter.scala:87:24] wire out_f_roready_1178 = out_roready_1_1032 & out_romask_1178; // @[RegisterRouter.scala:87:24] wire _out_T_11360 = out_f_roready_1178; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1178 = out_wivalid_1_1032 & out_wimask_1178; // @[RegisterRouter.scala:87:24] wire out_f_woready_1178 = out_woready_1_1032 & out_womask_1178; // @[RegisterRouter.scala:87:24] wire _out_T_11361 = ~out_rimask_1178; // @[RegisterRouter.scala:87:24] wire _out_T_11362 = ~out_wimask_1178; // @[RegisterRouter.scala:87:24] wire _out_T_11363 = ~out_romask_1178; // @[RegisterRouter.scala:87:24] wire _out_T_11364 = ~out_womask_1178; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1011 = {hi_950, flags_0_go, _out_prepend_T_1011}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11365 = out_prepend_1011; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11366 = _out_T_11365; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1012 = _out_T_11366; // @[RegisterRouter.scala:87:24] wire out_rimask_1179 = \|_out_rimask_T_1179; // @[RegisterRouter.scala:87:24] wire out_wimask_1179 = &_out_wimask_T_1179; // @[RegisterRouter.scala:87:24] wire out_romask_1179 = \|_out_romask_T_1179; // @[RegisterRouter.scala:87:24] wire out_womask_1179 = &_out_womask_T_1179; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1179 = out_rivalid_1_1033 & out_rimask_1179; // @[RegisterRouter.scala:87:24] wire _out_T_11368 = out_f_rivalid_1179; // @[RegisterRouter.scala:87:24] wire out_f_roready_1179 = out_roready_1_1033 & out_romask_1179; // @[RegisterRouter.scala:87:24] wire _out_T_11369 = out_f_roready_1179; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1179 = out_wivalid_1_1033 & out_wimask_1179; // @[RegisterRouter.scala:87:24] wire out_f_woready_1179 = out_woready_1_1033 & out_womask_1179; // @[RegisterRouter.scala:87:24] wire _out_T_11370 = ~out_rimask_1179; // @[RegisterRouter.scala:87:24] wire _out_T_11371 = ~out_wimask_1179; // @[RegisterRouter.scala:87:24] wire _out_T_11372 = ~out_romask_1179; // @[RegisterRouter.scala:87:24] wire _out_T_11373 = ~out_womask_1179; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1012 = {hi_951, flags_0_go, _out_prepend_T_1012}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11374 = out_prepend_1012; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11375 = _out_T_11374; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1013 = _out_T_11375; // @[RegisterRouter.scala:87:24] wire out_rimask_1180 = \|_out_rimask_T_1180; // @[RegisterRouter.scala:87:24] wire out_wimask_1180 = &_out_wimask_T_1180; // @[RegisterRouter.scala:87:24] wire out_romask_1180 = \|_out_romask_T_1180; // @[RegisterRouter.scala:87:24] wire out_womask_1180 = &_out_womask_T_1180; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1180 = out_rivalid_1_1034 & out_rimask_1180; // @[RegisterRouter.scala:87:24] wire _out_T_11377 = out_f_rivalid_1180; // @[RegisterRouter.scala:87:24] wire out_f_roready_1180 = out_roready_1_1034 & out_romask_1180; // @[RegisterRouter.scala:87:24] wire _out_T_11378 = out_f_roready_1180; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1180 = out_wivalid_1_1034 & out_wimask_1180; // @[RegisterRouter.scala:87:24] wire out_f_woready_1180 = out_woready_1_1034 & out_womask_1180; // @[RegisterRouter.scala:87:24] wire _out_T_11379 = ~out_rimask_1180; // @[RegisterRouter.scala:87:24] wire _out_T_11380 = ~out_wimask_1180; // @[RegisterRouter.scala:87:24] wire _out_T_11381 = ~out_romask_1180; // @[RegisterRouter.scala:87:24] wire _out_T_11382 = ~out_womask_1180; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1013 = {hi_952, flags_0_go, _out_prepend_T_1013}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11383 = out_prepend_1013; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11384 = _out_T_11383; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_246 = _out_T_11384; // @[MuxLiteral.scala:49:48] wire out_rimask_1181 = \|_out_rimask_T_1181; // @[RegisterRouter.scala:87:24] wire out_wimask_1181 = &_out_wimask_T_1181; // @[RegisterRouter.scala:87:24] wire out_romask_1181 = \|_out_romask_T_1181; // @[RegisterRouter.scala:87:24] wire out_womask_1181 = &_out_womask_T_1181; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1181 = out_rivalid_1_1035 & out_rimask_1181; // @[RegisterRouter.scala:87:24] wire _out_T_11386 = out_f_rivalid_1181; // @[RegisterRouter.scala:87:24] wire out_f_roready_1181 = out_roready_1_1035 & out_romask_1181; // @[RegisterRouter.scala:87:24] wire _out_T_11387 = out_f_roready_1181; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1181 = out_wivalid_1_1035 & out_wimask_1181; // @[RegisterRouter.scala:87:24] wire out_f_woready_1181 = out_woready_1_1035 & out_womask_1181; // @[RegisterRouter.scala:87:24] wire _out_T_11388 = ~out_rimask_1181; // @[RegisterRouter.scala:87:24] wire _out_T_11389 = ~out_wimask_1181; // @[RegisterRouter.scala:87:24] wire _out_T_11390 = ~out_romask_1181; // @[RegisterRouter.scala:87:24] wire _out_T_11391 = ~out_womask_1181; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11393 = _out_T_11392; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1014 = _out_T_11393; // @[RegisterRouter.scala:87:24] wire out_rimask_1182 = \|_out_rimask_T_1182; // @[RegisterRouter.scala:87:24] wire out_wimask_1182 = &_out_wimask_T_1182; // @[RegisterRouter.scala:87:24] wire out_romask_1182 = \|_out_romask_T_1182; // @[RegisterRouter.scala:87:24] wire out_womask_1182 = &_out_womask_T_1182; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1182 = out_rivalid_1_1036 & out_rimask_1182; // @[RegisterRouter.scala:87:24] wire _out_T_11395 = out_f_rivalid_1182; // @[RegisterRouter.scala:87:24] wire out_f_roready_1182 = out_roready_1_1036 & out_romask_1182; // @[RegisterRouter.scala:87:24] wire _out_T_11396 = out_f_roready_1182; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1182 = out_wivalid_1_1036 & out_wimask_1182; // @[RegisterRouter.scala:87:24] wire out_f_woready_1182 = out_woready_1_1036 & out_womask_1182; // @[RegisterRouter.scala:87:24] wire _out_T_11397 = ~out_rimask_1182; // @[RegisterRouter.scala:87:24] wire _out_T_11398 = ~out_wimask_1182; // @[RegisterRouter.scala:87:24] wire _out_T_11399 = ~out_romask_1182; // @[RegisterRouter.scala:87:24] wire _out_T_11400 = ~out_womask_1182; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1014 = {hi_186, flags_0_go, _out_prepend_T_1014}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11401 = out_prepend_1014; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11402 = _out_T_11401; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1015 = _out_T_11402; // @[RegisterRouter.scala:87:24] wire out_rimask_1183 = \|_out_rimask_T_1183; // @[RegisterRouter.scala:87:24] wire out_wimask_1183 = &_out_wimask_T_1183; // @[RegisterRouter.scala:87:24] wire out_romask_1183 = \|_out_romask_T_1183; // @[RegisterRouter.scala:87:24] wire out_womask_1183 = &_out_womask_T_1183; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1183 = out_rivalid_1_1037 & out_rimask_1183; // @[RegisterRouter.scala:87:24] wire _out_T_11404 = out_f_rivalid_1183; // @[RegisterRouter.scala:87:24] wire out_f_roready_1183 = out_roready_1_1037 & out_romask_1183; // @[RegisterRouter.scala:87:24] wire _out_T_11405 = out_f_roready_1183; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1183 = out_wivalid_1_1037 & out_wimask_1183; // @[RegisterRouter.scala:87:24] wire out_f_woready_1183 = out_woready_1_1037 & out_womask_1183; // @[RegisterRouter.scala:87:24] wire _out_T_11406 = ~out_rimask_1183; // @[RegisterRouter.scala:87:24] wire _out_T_11407 = ~out_wimask_1183; // @[RegisterRouter.scala:87:24] wire _out_T_11408 = ~out_romask_1183; // @[RegisterRouter.scala:87:24] wire _out_T_11409 = ~out_womask_1183; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1015 = {hi_187, flags_0_go, _out_prepend_T_1015}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11410 = out_prepend_1015; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11411 = _out_T_11410; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1016 = _out_T_11411; // @[RegisterRouter.scala:87:24] wire out_rimask_1184 = \|_out_rimask_T_1184; // @[RegisterRouter.scala:87:24] wire out_wimask_1184 = &_out_wimask_T_1184; // @[RegisterRouter.scala:87:24] wire out_romask_1184 = \|_out_romask_T_1184; // @[RegisterRouter.scala:87:24] wire out_womask_1184 = &_out_womask_T_1184; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1184 = out_rivalid_1_1038 & out_rimask_1184; // @[RegisterRouter.scala:87:24] wire _out_T_11413 = out_f_rivalid_1184; // @[RegisterRouter.scala:87:24] wire out_f_roready_1184 = out_roready_1_1038 & out_romask_1184; // @[RegisterRouter.scala:87:24] wire _out_T_11414 = out_f_roready_1184; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1184 = out_wivalid_1_1038 & out_wimask_1184; // @[RegisterRouter.scala:87:24] wire out_f_woready_1184 = out_woready_1_1038 & out_womask_1184; // @[RegisterRouter.scala:87:24] wire _out_T_11415 = ~out_rimask_1184; // @[RegisterRouter.scala:87:24] wire _out_T_11416 = ~out_wimask_1184; // @[RegisterRouter.scala:87:24] wire _out_T_11417 = ~out_romask_1184; // @[RegisterRouter.scala:87:24] wire _out_T_11418 = ~out_womask_1184; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1016 = {hi_188, flags_0_go, _out_prepend_T_1016}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11419 = out_prepend_1016; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11420 = _out_T_11419; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1017 = _out_T_11420; // @[RegisterRouter.scala:87:24] wire out_rimask_1185 = \|_out_rimask_T_1185; // @[RegisterRouter.scala:87:24] wire out_wimask_1185 = &_out_wimask_T_1185; // @[RegisterRouter.scala:87:24] wire out_romask_1185 = \|_out_romask_T_1185; // @[RegisterRouter.scala:87:24] wire out_womask_1185 = &_out_womask_T_1185; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1185 = out_rivalid_1_1039 & out_rimask_1185; // @[RegisterRouter.scala:87:24] wire _out_T_11422 = out_f_rivalid_1185; // @[RegisterRouter.scala:87:24] wire out_f_roready_1185 = out_roready_1_1039 & out_romask_1185; // @[RegisterRouter.scala:87:24] wire _out_T_11423 = out_f_roready_1185; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1185 = out_wivalid_1_1039 & out_wimask_1185; // @[RegisterRouter.scala:87:24] wire out_f_woready_1185 = out_woready_1_1039 & out_womask_1185; // @[RegisterRouter.scala:87:24] wire _out_T_11424 = ~out_rimask_1185; // @[RegisterRouter.scala:87:24] wire _out_T_11425 = ~out_wimask_1185; // @[RegisterRouter.scala:87:24] wire _out_T_11426 = ~out_romask_1185; // @[RegisterRouter.scala:87:24] wire _out_T_11427 = ~out_womask_1185; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1017 = {hi_189, flags_0_go, _out_prepend_T_1017}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11428 = out_prepend_1017; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11429 = _out_T_11428; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1018 = _out_T_11429; // @[RegisterRouter.scala:87:24] wire out_rimask_1186 = \|_out_rimask_T_1186; // @[RegisterRouter.scala:87:24] wire out_wimask_1186 = &_out_wimask_T_1186; // @[RegisterRouter.scala:87:24] wire out_romask_1186 = \|_out_romask_T_1186; // @[RegisterRouter.scala:87:24] wire out_womask_1186 = &_out_womask_T_1186; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1186 = out_rivalid_1_1040 & out_rimask_1186; // @[RegisterRouter.scala:87:24] wire _out_T_11431 = out_f_rivalid_1186; // @[RegisterRouter.scala:87:24] wire out_f_roready_1186 = out_roready_1_1040 & out_romask_1186; // @[RegisterRouter.scala:87:24] wire _out_T_11432 = out_f_roready_1186; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1186 = out_wivalid_1_1040 & out_wimask_1186; // @[RegisterRouter.scala:87:24] wire out_f_woready_1186 = out_woready_1_1040 & out_womask_1186; // @[RegisterRouter.scala:87:24] wire _out_T_11433 = ~out_rimask_1186; // @[RegisterRouter.scala:87:24] wire _out_T_11434 = ~out_wimask_1186; // @[RegisterRouter.scala:87:24] wire _out_T_11435 = ~out_romask_1186; // @[RegisterRouter.scala:87:24] wire _out_T_11436 = ~out_womask_1186; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1018 = {hi_190, flags_0_go, _out_prepend_T_1018}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11437 = out_prepend_1018; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11438 = _out_T_11437; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1019 = _out_T_11438; // @[RegisterRouter.scala:87:24] wire out_rimask_1187 = \|_out_rimask_T_1187; // @[RegisterRouter.scala:87:24] wire out_wimask_1187 = &_out_wimask_T_1187; // @[RegisterRouter.scala:87:24] wire out_romask_1187 = \|_out_romask_T_1187; // @[RegisterRouter.scala:87:24] wire out_womask_1187 = &_out_womask_T_1187; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1187 = out_rivalid_1_1041 & out_rimask_1187; // @[RegisterRouter.scala:87:24] wire _out_T_11440 = out_f_rivalid_1187; // @[RegisterRouter.scala:87:24] wire out_f_roready_1187 = out_roready_1_1041 & out_romask_1187; // @[RegisterRouter.scala:87:24] wire _out_T_11441 = out_f_roready_1187; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1187 = out_wivalid_1_1041 & out_wimask_1187; // @[RegisterRouter.scala:87:24] wire out_f_woready_1187 = out_woready_1_1041 & out_womask_1187; // @[RegisterRouter.scala:87:24] wire _out_T_11442 = ~out_rimask_1187; // @[RegisterRouter.scala:87:24] wire _out_T_11443 = ~out_wimask_1187; // @[RegisterRouter.scala:87:24] wire _out_T_11444 = ~out_romask_1187; // @[RegisterRouter.scala:87:24] wire _out_T_11445 = ~out_womask_1187; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1019 = {hi_191, flags_0_go, _out_prepend_T_1019}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11446 = out_prepend_1019; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11447 = _out_T_11446; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1020 = _out_T_11447; // @[RegisterRouter.scala:87:24] wire out_rimask_1188 = \|_out_rimask_T_1188; // @[RegisterRouter.scala:87:24] wire out_wimask_1188 = &_out_wimask_T_1188; // @[RegisterRouter.scala:87:24] wire out_romask_1188 = \|_out_romask_T_1188; // @[RegisterRouter.scala:87:24] wire out_womask_1188 = &_out_womask_T_1188; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1188 = out_rivalid_1_1042 & out_rimask_1188; // @[RegisterRouter.scala:87:24] wire _out_T_11449 = out_f_rivalid_1188; // @[RegisterRouter.scala:87:24] wire out_f_roready_1188 = out_roready_1_1042 & out_romask_1188; // @[RegisterRouter.scala:87:24] wire _out_T_11450 = out_f_roready_1188; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1188 = out_wivalid_1_1042 & out_wimask_1188; // @[RegisterRouter.scala:87:24] wire out_f_woready_1188 = out_woready_1_1042 & out_womask_1188; // @[RegisterRouter.scala:87:24] wire _out_T_11451 = ~out_rimask_1188; // @[RegisterRouter.scala:87:24] wire _out_T_11452 = ~out_wimask_1188; // @[RegisterRouter.scala:87:24] wire _out_T_11453 = ~out_romask_1188; // @[RegisterRouter.scala:87:24] wire _out_T_11454 = ~out_womask_1188; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1020 = {hi_192, flags_0_go, _out_prepend_T_1020}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11455 = out_prepend_1020; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11456 = _out_T_11455; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_151 = _out_T_11456; // @[MuxLiteral.scala:49:48] wire out_rimask_1189 = \|_out_rimask_T_1189; // @[RegisterRouter.scala:87:24] wire out_wimask_1189 = &_out_wimask_T_1189; // @[RegisterRouter.scala:87:24] wire out_romask_1189 = \|_out_romask_T_1189; // @[RegisterRouter.scala:87:24] wire out_womask_1189 = &_out_womask_T_1189; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1189 = out_rivalid_1_1043 & out_rimask_1189; // @[RegisterRouter.scala:87:24] wire _out_T_11458 = out_f_rivalid_1189; // @[RegisterRouter.scala:87:24] wire out_f_roready_1189 = out_roready_1_1043 & out_romask_1189; // @[RegisterRouter.scala:87:24] wire _out_T_11459 = out_f_roready_1189; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1189 = out_wivalid_1_1043 & out_wimask_1189; // @[RegisterRouter.scala:87:24] wire out_f_woready_1189 = out_woready_1_1043 & out_womask_1189; // @[RegisterRouter.scala:87:24] wire _out_T_11460 = ~out_rimask_1189; // @[RegisterRouter.scala:87:24] wire _out_T_11461 = ~out_wimask_1189; // @[RegisterRouter.scala:87:24] wire _out_T_11462 = ~out_romask_1189; // @[RegisterRouter.scala:87:24] wire _out_T_11463 = ~out_womask_1189; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11465 = _out_T_11464; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1021 = _out_T_11465; // @[RegisterRouter.scala:87:24] wire out_rimask_1190 = \|_out_rimask_T_1190; // @[RegisterRouter.scala:87:24] wire out_wimask_1190 = &_out_wimask_T_1190; // @[RegisterRouter.scala:87:24] wire out_romask_1190 = \|_out_romask_T_1190; // @[RegisterRouter.scala:87:24] wire out_womask_1190 = &_out_womask_T_1190; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1190 = out_rivalid_1_1044 & out_rimask_1190; // @[RegisterRouter.scala:87:24] wire _out_T_11467 = out_f_rivalid_1190; // @[RegisterRouter.scala:87:24] wire out_f_roready_1190 = out_roready_1_1044 & out_romask_1190; // @[RegisterRouter.scala:87:24] wire _out_T_11468 = out_f_roready_1190; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1190 = out_wivalid_1_1044 & out_wimask_1190; // @[RegisterRouter.scala:87:24] wire out_f_woready_1190 = out_woready_1_1044 & out_womask_1190; // @[RegisterRouter.scala:87:24] wire _out_T_11469 = ~out_rimask_1190; // @[RegisterRouter.scala:87:24] wire _out_T_11470 = ~out_wimask_1190; // @[RegisterRouter.scala:87:24] wire _out_T_11471 = ~out_romask_1190; // @[RegisterRouter.scala:87:24] wire _out_T_11472 = ~out_womask_1190; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1021 = {hi_146, flags_0_go, _out_prepend_T_1021}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11473 = out_prepend_1021; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11474 = _out_T_11473; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1022 = _out_T_11474; // @[RegisterRouter.scala:87:24] wire out_rimask_1191 = \|_out_rimask_T_1191; // @[RegisterRouter.scala:87:24] wire out_wimask_1191 = &_out_wimask_T_1191; // @[RegisterRouter.scala:87:24] wire out_romask_1191 = \|_out_romask_T_1191; // @[RegisterRouter.scala:87:24] wire out_womask_1191 = &_out_womask_T_1191; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1191 = out_rivalid_1_1045 & out_rimask_1191; // @[RegisterRouter.scala:87:24] wire _out_T_11476 = out_f_rivalid_1191; // @[RegisterRouter.scala:87:24] wire out_f_roready_1191 = out_roready_1_1045 & out_romask_1191; // @[RegisterRouter.scala:87:24] wire _out_T_11477 = out_f_roready_1191; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1191 = out_wivalid_1_1045 & out_wimask_1191; // @[RegisterRouter.scala:87:24] wire out_f_woready_1191 = out_woready_1_1045 & out_womask_1191; // @[RegisterRouter.scala:87:24] wire _out_T_11478 = ~out_rimask_1191; // @[RegisterRouter.scala:87:24] wire _out_T_11479 = ~out_wimask_1191; // @[RegisterRouter.scala:87:24] wire _out_T_11480 = ~out_romask_1191; // @[RegisterRouter.scala:87:24] wire _out_T_11481 = ~out_womask_1191; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1022 = {hi_147, flags_0_go, _out_prepend_T_1022}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11482 = out_prepend_1022; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11483 = _out_T_11482; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1023 = _out_T_11483; // @[RegisterRouter.scala:87:24] wire out_rimask_1192 = \|_out_rimask_T_1192; // @[RegisterRouter.scala:87:24] wire out_wimask_1192 = &_out_wimask_T_1192; // @[RegisterRouter.scala:87:24] wire out_romask_1192 = \|_out_romask_T_1192; // @[RegisterRouter.scala:87:24] wire out_womask_1192 = &_out_womask_T_1192; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1192 = out_rivalid_1_1046 & out_rimask_1192; // @[RegisterRouter.scala:87:24] wire _out_T_11485 = out_f_rivalid_1192; // @[RegisterRouter.scala:87:24] wire out_f_roready_1192 = out_roready_1_1046 & out_romask_1192; // @[RegisterRouter.scala:87:24] wire _out_T_11486 = out_f_roready_1192; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1192 = out_wivalid_1_1046 & out_wimask_1192; // @[RegisterRouter.scala:87:24] wire out_f_woready_1192 = out_woready_1_1046 & out_womask_1192; // @[RegisterRouter.scala:87:24] wire _out_T_11487 = ~out_rimask_1192; // @[RegisterRouter.scala:87:24] wire _out_T_11488 = ~out_wimask_1192; // @[RegisterRouter.scala:87:24] wire _out_T_11489 = ~out_romask_1192; // @[RegisterRouter.scala:87:24] wire _out_T_11490 = ~out_womask_1192; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1023 = {hi_148, flags_0_go, _out_prepend_T_1023}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11491 = out_prepend_1023; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11492 = _out_T_11491; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1024 = _out_T_11492; // @[RegisterRouter.scala:87:24] wire out_rimask_1193 = \|_out_rimask_T_1193; // @[RegisterRouter.scala:87:24] wire out_wimask_1193 = &_out_wimask_T_1193; // @[RegisterRouter.scala:87:24] wire out_romask_1193 = \|_out_romask_T_1193; // @[RegisterRouter.scala:87:24] wire out_womask_1193 = &_out_womask_T_1193; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1193 = out_rivalid_1_1047 & out_rimask_1193; // @[RegisterRouter.scala:87:24] wire _out_T_11494 = out_f_rivalid_1193; // @[RegisterRouter.scala:87:24] wire out_f_roready_1193 = out_roready_1_1047 & out_romask_1193; // @[RegisterRouter.scala:87:24] wire _out_T_11495 = out_f_roready_1193; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1193 = out_wivalid_1_1047 & out_wimask_1193; // @[RegisterRouter.scala:87:24] wire out_f_woready_1193 = out_woready_1_1047 & out_womask_1193; // @[RegisterRouter.scala:87:24] wire _out_T_11496 = ~out_rimask_1193; // @[RegisterRouter.scala:87:24] wire _out_T_11497 = ~out_wimask_1193; // @[RegisterRouter.scala:87:24] wire _out_T_11498 = ~out_romask_1193; // @[RegisterRouter.scala:87:24] wire _out_T_11499 = ~out_womask_1193; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1024 = {hi_149, flags_0_go, _out_prepend_T_1024}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11500 = out_prepend_1024; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11501 = _out_T_11500; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1025 = _out_T_11501; // @[RegisterRouter.scala:87:24] wire out_rimask_1194 = \|_out_rimask_T_1194; // @[RegisterRouter.scala:87:24] wire out_wimask_1194 = &_out_wimask_T_1194; // @[RegisterRouter.scala:87:24] wire out_romask_1194 = \|_out_romask_T_1194; // @[RegisterRouter.scala:87:24] wire out_womask_1194 = &_out_womask_T_1194; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1194 = out_rivalid_1_1048 & out_rimask_1194; // @[RegisterRouter.scala:87:24] wire _out_T_11503 = out_f_rivalid_1194; // @[RegisterRouter.scala:87:24] wire out_f_roready_1194 = out_roready_1_1048 & out_romask_1194; // @[RegisterRouter.scala:87:24] wire _out_T_11504 = out_f_roready_1194; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1194 = out_wivalid_1_1048 & out_wimask_1194; // @[RegisterRouter.scala:87:24] wire out_f_woready_1194 = out_woready_1_1048 & out_womask_1194; // @[RegisterRouter.scala:87:24] wire _out_T_11505 = ~out_rimask_1194; // @[RegisterRouter.scala:87:24] wire _out_T_11506 = ~out_wimask_1194; // @[RegisterRouter.scala:87:24] wire _out_T_11507 = ~out_romask_1194; // @[RegisterRouter.scala:87:24] wire _out_T_11508 = ~out_womask_1194; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1025 = {hi_150, flags_0_go, _out_prepend_T_1025}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11509 = out_prepend_1025; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11510 = _out_T_11509; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1026 = _out_T_11510; // @[RegisterRouter.scala:87:24] wire out_rimask_1195 = \|_out_rimask_T_1195; // @[RegisterRouter.scala:87:24] wire out_wimask_1195 = &_out_wimask_T_1195; // @[RegisterRouter.scala:87:24] wire out_romask_1195 = \|_out_romask_T_1195; // @[RegisterRouter.scala:87:24] wire out_womask_1195 = &_out_womask_T_1195; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1195 = out_rivalid_1_1049 & out_rimask_1195; // @[RegisterRouter.scala:87:24] wire _out_T_11512 = out_f_rivalid_1195; // @[RegisterRouter.scala:87:24] wire out_f_roready_1195 = out_roready_1_1049 & out_romask_1195; // @[RegisterRouter.scala:87:24] wire _out_T_11513 = out_f_roready_1195; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1195 = out_wivalid_1_1049 & out_wimask_1195; // @[RegisterRouter.scala:87:24] wire out_f_woready_1195 = out_woready_1_1049 & out_womask_1195; // @[RegisterRouter.scala:87:24] wire _out_T_11514 = ~out_rimask_1195; // @[RegisterRouter.scala:87:24] wire _out_T_11515 = ~out_wimask_1195; // @[RegisterRouter.scala:87:24] wire _out_T_11516 = ~out_romask_1195; // @[RegisterRouter.scala:87:24] wire _out_T_11517 = ~out_womask_1195; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1026 = {hi_151, flags_0_go, _out_prepend_T_1026}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11518 = out_prepend_1026; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11519 = _out_T_11518; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1027 = _out_T_11519; // @[RegisterRouter.scala:87:24] wire out_rimask_1196 = \|_out_rimask_T_1196; // @[RegisterRouter.scala:87:24] wire out_wimask_1196 = &_out_wimask_T_1196; // @[RegisterRouter.scala:87:24] wire out_romask_1196 = \|_out_romask_T_1196; // @[RegisterRouter.scala:87:24] wire out_womask_1196 = &_out_womask_T_1196; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1196 = out_rivalid_1_1050 & out_rimask_1196; // @[RegisterRouter.scala:87:24] wire _out_T_11521 = out_f_rivalid_1196; // @[RegisterRouter.scala:87:24] wire out_f_roready_1196 = out_roready_1_1050 & out_romask_1196; // @[RegisterRouter.scala:87:24] wire _out_T_11522 = out_f_roready_1196; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1196 = out_wivalid_1_1050 & out_wimask_1196; // @[RegisterRouter.scala:87:24] wire out_f_woready_1196 = out_woready_1_1050 & out_womask_1196; // @[RegisterRouter.scala:87:24] wire _out_T_11523 = ~out_rimask_1196; // @[RegisterRouter.scala:87:24] wire _out_T_11524 = ~out_wimask_1196; // @[RegisterRouter.scala:87:24] wire _out_T_11525 = ~out_romask_1196; // @[RegisterRouter.scala:87:24] wire _out_T_11526 = ~out_womask_1196; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1027 = {hi_152, flags_0_go, _out_prepend_T_1027}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11527 = out_prepend_1027; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11528 = _out_T_11527; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_146 = _out_T_11528; // @[MuxLiteral.scala:49:48] wire out_rimask_1197 = \|_out_rimask_T_1197; // @[RegisterRouter.scala:87:24] wire out_wimask_1197 = &_out_wimask_T_1197; // @[RegisterRouter.scala:87:24] wire out_romask_1197 = \|_out_romask_T_1197; // @[RegisterRouter.scala:87:24] wire out_womask_1197 = &_out_womask_T_1197; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1197 = out_rivalid_1_1051 & out_rimask_1197; // @[RegisterRouter.scala:87:24] wire _out_T_11530 = out_f_rivalid_1197; // @[RegisterRouter.scala:87:24] wire out_f_roready_1197 = out_roready_1_1051 & out_romask_1197; // @[RegisterRouter.scala:87:24] wire _out_T_11531 = out_f_roready_1197; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1197 = out_wivalid_1_1051 & out_wimask_1197; // @[RegisterRouter.scala:87:24] wire out_f_woready_1197 = out_woready_1_1051 & out_womask_1197; // @[RegisterRouter.scala:87:24] wire _out_T_11532 = ~out_rimask_1197; // @[RegisterRouter.scala:87:24] wire _out_T_11533 = ~out_wimask_1197; // @[RegisterRouter.scala:87:24] wire _out_T_11534 = ~out_romask_1197; // @[RegisterRouter.scala:87:24] wire _out_T_11535 = ~out_womask_1197; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11537 = _out_T_11536; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1028 = _out_T_11537; // @[RegisterRouter.scala:87:24] wire out_rimask_1198 = \|_out_rimask_T_1198; // @[RegisterRouter.scala:87:24] wire out_wimask_1198 = &_out_wimask_T_1198; // @[RegisterRouter.scala:87:24] wire out_romask_1198 = \|_out_romask_T_1198; // @[RegisterRouter.scala:87:24] wire out_womask_1198 = &_out_womask_T_1198; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1198 = out_rivalid_1_1052 & out_rimask_1198; // @[RegisterRouter.scala:87:24] wire _out_T_11539 = out_f_rivalid_1198; // @[RegisterRouter.scala:87:24] wire out_f_roready_1198 = out_roready_1_1052 & out_romask_1198; // @[RegisterRouter.scala:87:24] wire _out_T_11540 = out_f_roready_1198; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1198 = out_wivalid_1_1052 & out_wimask_1198; // @[RegisterRouter.scala:87:24] wire out_f_woready_1198 = out_woready_1_1052 & out_womask_1198; // @[RegisterRouter.scala:87:24] wire _out_T_11541 = ~out_rimask_1198; // @[RegisterRouter.scala:87:24] wire _out_T_11542 = ~out_wimask_1198; // @[RegisterRouter.scala:87:24] wire _out_T_11543 = ~out_romask_1198; // @[RegisterRouter.scala:87:24] wire _out_T_11544 = ~out_womask_1198; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1028 = {hi_498, flags_0_go, _out_prepend_T_1028}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11545 = out_prepend_1028; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11546 = _out_T_11545; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1029 = _out_T_11546; // @[RegisterRouter.scala:87:24] wire out_rimask_1199 = \|_out_rimask_T_1199; // @[RegisterRouter.scala:87:24] wire out_wimask_1199 = &_out_wimask_T_1199; // @[RegisterRouter.scala:87:24] wire out_romask_1199 = \|_out_romask_T_1199; // @[RegisterRouter.scala:87:24] wire out_womask_1199 = &_out_womask_T_1199; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1199 = out_rivalid_1_1053 & out_rimask_1199; // @[RegisterRouter.scala:87:24] wire _out_T_11548 = out_f_rivalid_1199; // @[RegisterRouter.scala:87:24] wire out_f_roready_1199 = out_roready_1_1053 & out_romask_1199; // @[RegisterRouter.scala:87:24] wire _out_T_11549 = out_f_roready_1199; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1199 = out_wivalid_1_1053 & out_wimask_1199; // @[RegisterRouter.scala:87:24] wire out_f_woready_1199 = out_woready_1_1053 & out_womask_1199; // @[RegisterRouter.scala:87:24] wire _out_T_11550 = ~out_rimask_1199; // @[RegisterRouter.scala:87:24] wire _out_T_11551 = ~out_wimask_1199; // @[RegisterRouter.scala:87:24] wire _out_T_11552 = ~out_romask_1199; // @[RegisterRouter.scala:87:24] wire _out_T_11553 = ~out_womask_1199; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1029 = {hi_499, flags_0_go, _out_prepend_T_1029}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11554 = out_prepend_1029; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11555 = _out_T_11554; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1030 = _out_T_11555; // @[RegisterRouter.scala:87:24] wire out_rimask_1200 = \|_out_rimask_T_1200; // @[RegisterRouter.scala:87:24] wire out_wimask_1200 = &_out_wimask_T_1200; // @[RegisterRouter.scala:87:24] wire out_romask_1200 = \|_out_romask_T_1200; // @[RegisterRouter.scala:87:24] wire out_womask_1200 = &_out_womask_T_1200; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1200 = out_rivalid_1_1054 & out_rimask_1200; // @[RegisterRouter.scala:87:24] wire _out_T_11557 = out_f_rivalid_1200; // @[RegisterRouter.scala:87:24] wire out_f_roready_1200 = out_roready_1_1054 & out_romask_1200; // @[RegisterRouter.scala:87:24] wire _out_T_11558 = out_f_roready_1200; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1200 = out_wivalid_1_1054 & out_wimask_1200; // @[RegisterRouter.scala:87:24] wire out_f_woready_1200 = out_woready_1_1054 & out_womask_1200; // @[RegisterRouter.scala:87:24] wire _out_T_11559 = ~out_rimask_1200; // @[RegisterRouter.scala:87:24] wire _out_T_11560 = ~out_wimask_1200; // @[RegisterRouter.scala:87:24] wire _out_T_11561 = ~out_romask_1200; // @[RegisterRouter.scala:87:24] wire _out_T_11562 = ~out_womask_1200; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1030 = {hi_500, flags_0_go, _out_prepend_T_1030}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11563 = out_prepend_1030; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11564 = _out_T_11563; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1031 = _out_T_11564; // @[RegisterRouter.scala:87:24] wire out_rimask_1201 = \|_out_rimask_T_1201; // @[RegisterRouter.scala:87:24] wire out_wimask_1201 = &_out_wimask_T_1201; // @[RegisterRouter.scala:87:24] wire out_romask_1201 = \|_out_romask_T_1201; // @[RegisterRouter.scala:87:24] wire out_womask_1201 = &_out_womask_T_1201; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1201 = out_rivalid_1_1055 & out_rimask_1201; // @[RegisterRouter.scala:87:24] wire _out_T_11566 = out_f_rivalid_1201; // @[RegisterRouter.scala:87:24] wire out_f_roready_1201 = out_roready_1_1055 & out_romask_1201; // @[RegisterRouter.scala:87:24] wire _out_T_11567 = out_f_roready_1201; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1201 = out_wivalid_1_1055 & out_wimask_1201; // @[RegisterRouter.scala:87:24] wire out_f_woready_1201 = out_woready_1_1055 & out_womask_1201; // @[RegisterRouter.scala:87:24] wire _out_T_11568 = ~out_rimask_1201; // @[RegisterRouter.scala:87:24] wire _out_T_11569 = ~out_wimask_1201; // @[RegisterRouter.scala:87:24] wire _out_T_11570 = ~out_romask_1201; // @[RegisterRouter.scala:87:24] wire _out_T_11571 = ~out_womask_1201; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1031 = {hi_501, flags_0_go, _out_prepend_T_1031}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11572 = out_prepend_1031; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11573 = _out_T_11572; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1032 = _out_T_11573; // @[RegisterRouter.scala:87:24] wire out_rimask_1202 = \|_out_rimask_T_1202; // @[RegisterRouter.scala:87:24] wire out_wimask_1202 = &_out_wimask_T_1202; // @[RegisterRouter.scala:87:24] wire out_romask_1202 = \|_out_romask_T_1202; // @[RegisterRouter.scala:87:24] wire out_womask_1202 = &_out_womask_T_1202; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1202 = out_rivalid_1_1056 & out_rimask_1202; // @[RegisterRouter.scala:87:24] wire _out_T_11575 = out_f_rivalid_1202; // @[RegisterRouter.scala:87:24] wire out_f_roready_1202 = out_roready_1_1056 & out_romask_1202; // @[RegisterRouter.scala:87:24] wire _out_T_11576 = out_f_roready_1202; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1202 = out_wivalid_1_1056 & out_wimask_1202; // @[RegisterRouter.scala:87:24] wire out_f_woready_1202 = out_woready_1_1056 & out_womask_1202; // @[RegisterRouter.scala:87:24] wire _out_T_11577 = ~out_rimask_1202; // @[RegisterRouter.scala:87:24] wire _out_T_11578 = ~out_wimask_1202; // @[RegisterRouter.scala:87:24] wire _out_T_11579 = ~out_romask_1202; // @[RegisterRouter.scala:87:24] wire _out_T_11580 = ~out_womask_1202; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1032 = {hi_502, flags_0_go, _out_prepend_T_1032}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11581 = out_prepend_1032; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11582 = _out_T_11581; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1033 = _out_T_11582; // @[RegisterRouter.scala:87:24] wire out_rimask_1203 = \|_out_rimask_T_1203; // @[RegisterRouter.scala:87:24] wire out_wimask_1203 = &_out_wimask_T_1203; // @[RegisterRouter.scala:87:24] wire out_romask_1203 = \|_out_romask_T_1203; // @[RegisterRouter.scala:87:24] wire out_womask_1203 = &_out_womask_T_1203; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1203 = out_rivalid_1_1057 & out_rimask_1203; // @[RegisterRouter.scala:87:24] wire _out_T_11584 = out_f_rivalid_1203; // @[RegisterRouter.scala:87:24] wire out_f_roready_1203 = out_roready_1_1057 & out_romask_1203; // @[RegisterRouter.scala:87:24] wire _out_T_11585 = out_f_roready_1203; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1203 = out_wivalid_1_1057 & out_wimask_1203; // @[RegisterRouter.scala:87:24] wire out_f_woready_1203 = out_woready_1_1057 & out_womask_1203; // @[RegisterRouter.scala:87:24] wire _out_T_11586 = ~out_rimask_1203; // @[RegisterRouter.scala:87:24] wire _out_T_11587 = ~out_wimask_1203; // @[RegisterRouter.scala:87:24] wire _out_T_11588 = ~out_romask_1203; // @[RegisterRouter.scala:87:24] wire _out_T_11589 = ~out_womask_1203; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1033 = {hi_503, flags_0_go, _out_prepend_T_1033}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11590 = out_prepend_1033; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11591 = _out_T_11590; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1034 = _out_T_11591; // @[RegisterRouter.scala:87:24] wire out_rimask_1204 = \|_out_rimask_T_1204; // @[RegisterRouter.scala:87:24] wire out_wimask_1204 = &_out_wimask_T_1204; // @[RegisterRouter.scala:87:24] wire out_romask_1204 = \|_out_romask_T_1204; // @[RegisterRouter.scala:87:24] wire out_womask_1204 = &_out_womask_T_1204; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1204 = out_rivalid_1_1058 & out_rimask_1204; // @[RegisterRouter.scala:87:24] wire _out_T_11593 = out_f_rivalid_1204; // @[RegisterRouter.scala:87:24] wire out_f_roready_1204 = out_roready_1_1058 & out_romask_1204; // @[RegisterRouter.scala:87:24] wire _out_T_11594 = out_f_roready_1204; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1204 = out_wivalid_1_1058 & out_wimask_1204; // @[RegisterRouter.scala:87:24] wire out_f_woready_1204 = out_woready_1_1058 & out_womask_1204; // @[RegisterRouter.scala:87:24] wire _out_T_11595 = ~out_rimask_1204; // @[RegisterRouter.scala:87:24] wire _out_T_11596 = ~out_wimask_1204; // @[RegisterRouter.scala:87:24] wire _out_T_11597 = ~out_romask_1204; // @[RegisterRouter.scala:87:24] wire _out_T_11598 = ~out_womask_1204; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1034 = {hi_504, flags_0_go, _out_prepend_T_1034}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11599 = out_prepend_1034; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11600 = _out_T_11599; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_190 = _out_T_11600; // @[MuxLiteral.scala:49:48] wire out_rimask_1205 = \|_out_rimask_T_1205; // @[RegisterRouter.scala:87:24] wire out_wimask_1205 = &_out_wimask_T_1205; // @[RegisterRouter.scala:87:24] wire out_romask_1205 = \|_out_romask_T_1205; // @[RegisterRouter.scala:87:24] wire out_womask_1205 = &_out_womask_T_1205; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1205 = out_rivalid_1_1059 & out_rimask_1205; // @[RegisterRouter.scala:87:24] wire _out_T_11602 = out_f_rivalid_1205; // @[RegisterRouter.scala:87:24] wire out_f_roready_1205 = out_roready_1_1059 & out_romask_1205; // @[RegisterRouter.scala:87:24] wire _out_T_11603 = out_f_roready_1205; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1205 = out_wivalid_1_1059 & out_wimask_1205; // @[RegisterRouter.scala:87:24] wire out_f_woready_1205 = out_woready_1_1059 & out_womask_1205; // @[RegisterRouter.scala:87:24] wire _out_T_11604 = ~out_rimask_1205; // @[RegisterRouter.scala:87:24] wire _out_T_11605 = ~out_wimask_1205; // @[RegisterRouter.scala:87:24] wire _out_T_11606 = ~out_romask_1205; // @[RegisterRouter.scala:87:24] wire _out_T_11607 = ~out_womask_1205; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11609 = _out_T_11608; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1035 = _out_T_11609; // @[RegisterRouter.scala:87:24] wire out_rimask_1206 = \|_out_rimask_T_1206; // @[RegisterRouter.scala:87:24] wire out_wimask_1206 = &_out_wimask_T_1206; // @[RegisterRouter.scala:87:24] wire out_romask_1206 = \|_out_romask_T_1206; // @[RegisterRouter.scala:87:24] wire out_womask_1206 = &_out_womask_T_1206; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1206 = out_rivalid_1_1060 & out_rimask_1206; // @[RegisterRouter.scala:87:24] wire _out_T_11611 = out_f_rivalid_1206; // @[RegisterRouter.scala:87:24] wire out_f_roready_1206 = out_roready_1_1060 & out_romask_1206; // @[RegisterRouter.scala:87:24] wire _out_T_11612 = out_f_roready_1206; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1206 = out_wivalid_1_1060 & out_wimask_1206; // @[RegisterRouter.scala:87:24] wire out_f_woready_1206 = out_woready_1_1060 & out_womask_1206; // @[RegisterRouter.scala:87:24] wire _out_T_11613 = ~out_rimask_1206; // @[RegisterRouter.scala:87:24] wire _out_T_11614 = ~out_wimask_1206; // @[RegisterRouter.scala:87:24] wire _out_T_11615 = ~out_romask_1206; // @[RegisterRouter.scala:87:24] wire _out_T_11616 = ~out_womask_1206; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1035 = {hi_442, flags_0_go, _out_prepend_T_1035}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11617 = out_prepend_1035; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11618 = _out_T_11617; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1036 = _out_T_11618; // @[RegisterRouter.scala:87:24] wire out_rimask_1207 = \|_out_rimask_T_1207; // @[RegisterRouter.scala:87:24] wire out_wimask_1207 = &_out_wimask_T_1207; // @[RegisterRouter.scala:87:24] wire out_romask_1207 = \|_out_romask_T_1207; // @[RegisterRouter.scala:87:24] wire out_womask_1207 = &_out_womask_T_1207; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1207 = out_rivalid_1_1061 & out_rimask_1207; // @[RegisterRouter.scala:87:24] wire _out_T_11620 = out_f_rivalid_1207; // @[RegisterRouter.scala:87:24] wire out_f_roready_1207 = out_roready_1_1061 & out_romask_1207; // @[RegisterRouter.scala:87:24] wire _out_T_11621 = out_f_roready_1207; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1207 = out_wivalid_1_1061 & out_wimask_1207; // @[RegisterRouter.scala:87:24] wire out_f_woready_1207 = out_woready_1_1061 & out_womask_1207; // @[RegisterRouter.scala:87:24] wire _out_T_11622 = ~out_rimask_1207; // @[RegisterRouter.scala:87:24] wire _out_T_11623 = ~out_wimask_1207; // @[RegisterRouter.scala:87:24] wire _out_T_11624 = ~out_romask_1207; // @[RegisterRouter.scala:87:24] wire _out_T_11625 = ~out_womask_1207; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1036 = {hi_443, flags_0_go, _out_prepend_T_1036}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11626 = out_prepend_1036; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11627 = _out_T_11626; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1037 = _out_T_11627; // @[RegisterRouter.scala:87:24] wire out_rimask_1208 = \|_out_rimask_T_1208; // @[RegisterRouter.scala:87:24] wire out_wimask_1208 = &_out_wimask_T_1208; // @[RegisterRouter.scala:87:24] wire out_romask_1208 = \|_out_romask_T_1208; // @[RegisterRouter.scala:87:24] wire out_womask_1208 = &_out_womask_T_1208; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1208 = out_rivalid_1_1062 & out_rimask_1208; // @[RegisterRouter.scala:87:24] wire _out_T_11629 = out_f_rivalid_1208; // @[RegisterRouter.scala:87:24] wire out_f_roready_1208 = out_roready_1_1062 & out_romask_1208; // @[RegisterRouter.scala:87:24] wire _out_T_11630 = out_f_roready_1208; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1208 = out_wivalid_1_1062 & out_wimask_1208; // @[RegisterRouter.scala:87:24] wire out_f_woready_1208 = out_woready_1_1062 & out_womask_1208; // @[RegisterRouter.scala:87:24] wire _out_T_11631 = ~out_rimask_1208; // @[RegisterRouter.scala:87:24] wire _out_T_11632 = ~out_wimask_1208; // @[RegisterRouter.scala:87:24] wire _out_T_11633 = ~out_romask_1208; // @[RegisterRouter.scala:87:24] wire _out_T_11634 = ~out_womask_1208; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1037 = {hi_444, flags_0_go, _out_prepend_T_1037}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11635 = out_prepend_1037; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11636 = _out_T_11635; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1038 = _out_T_11636; // @[RegisterRouter.scala:87:24] wire out_rimask_1209 = \|_out_rimask_T_1209; // @[RegisterRouter.scala:87:24] wire out_wimask_1209 = &_out_wimask_T_1209; // @[RegisterRouter.scala:87:24] wire out_romask_1209 = \|_out_romask_T_1209; // @[RegisterRouter.scala:87:24] wire out_womask_1209 = &_out_womask_T_1209; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1209 = out_rivalid_1_1063 & out_rimask_1209; // @[RegisterRouter.scala:87:24] wire _out_T_11638 = out_f_rivalid_1209; // @[RegisterRouter.scala:87:24] wire out_f_roready_1209 = out_roready_1_1063 & out_romask_1209; // @[RegisterRouter.scala:87:24] wire _out_T_11639 = out_f_roready_1209; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1209 = out_wivalid_1_1063 & out_wimask_1209; // @[RegisterRouter.scala:87:24] wire out_f_woready_1209 = out_woready_1_1063 & out_womask_1209; // @[RegisterRouter.scala:87:24] wire _out_T_11640 = ~out_rimask_1209; // @[RegisterRouter.scala:87:24] wire _out_T_11641 = ~out_wimask_1209; // @[RegisterRouter.scala:87:24] wire _out_T_11642 = ~out_romask_1209; // @[RegisterRouter.scala:87:24] wire _out_T_11643 = ~out_womask_1209; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1038 = {hi_445, flags_0_go, _out_prepend_T_1038}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11644 = out_prepend_1038; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11645 = _out_T_11644; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1039 = _out_T_11645; // @[RegisterRouter.scala:87:24] wire out_rimask_1210 = \|_out_rimask_T_1210; // @[RegisterRouter.scala:87:24] wire out_wimask_1210 = &_out_wimask_T_1210; // @[RegisterRouter.scala:87:24] wire out_romask_1210 = \|_out_romask_T_1210; // @[RegisterRouter.scala:87:24] wire out_womask_1210 = &_out_womask_T_1210; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1210 = out_rivalid_1_1064 & out_rimask_1210; // @[RegisterRouter.scala:87:24] wire _out_T_11647 = out_f_rivalid_1210; // @[RegisterRouter.scala:87:24] wire out_f_roready_1210 = out_roready_1_1064 & out_romask_1210; // @[RegisterRouter.scala:87:24] wire _out_T_11648 = out_f_roready_1210; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1210 = out_wivalid_1_1064 & out_wimask_1210; // @[RegisterRouter.scala:87:24] wire out_f_woready_1210 = out_woready_1_1064 & out_womask_1210; // @[RegisterRouter.scala:87:24] wire _out_T_11649 = ~out_rimask_1210; // @[RegisterRouter.scala:87:24] wire _out_T_11650 = ~out_wimask_1210; // @[RegisterRouter.scala:87:24] wire _out_T_11651 = ~out_romask_1210; // @[RegisterRouter.scala:87:24] wire _out_T_11652 = ~out_womask_1210; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1039 = {hi_446, flags_0_go, _out_prepend_T_1039}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11653 = out_prepend_1039; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11654 = _out_T_11653; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1040 = _out_T_11654; // @[RegisterRouter.scala:87:24] wire out_rimask_1211 = \|_out_rimask_T_1211; // @[RegisterRouter.scala:87:24] wire out_wimask_1211 = &_out_wimask_T_1211; // @[RegisterRouter.scala:87:24] wire out_romask_1211 = \|_out_romask_T_1211; // @[RegisterRouter.scala:87:24] wire out_womask_1211 = &_out_womask_T_1211; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1211 = out_rivalid_1_1065 & out_rimask_1211; // @[RegisterRouter.scala:87:24] wire _out_T_11656 = out_f_rivalid_1211; // @[RegisterRouter.scala:87:24] wire out_f_roready_1211 = out_roready_1_1065 & out_romask_1211; // @[RegisterRouter.scala:87:24] wire _out_T_11657 = out_f_roready_1211; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1211 = out_wivalid_1_1065 & out_wimask_1211; // @[RegisterRouter.scala:87:24] wire out_f_woready_1211 = out_woready_1_1065 & out_womask_1211; // @[RegisterRouter.scala:87:24] wire _out_T_11658 = ~out_rimask_1211; // @[RegisterRouter.scala:87:24] wire _out_T_11659 = ~out_wimask_1211; // @[RegisterRouter.scala:87:24] wire _out_T_11660 = ~out_romask_1211; // @[RegisterRouter.scala:87:24] wire _out_T_11661 = ~out_womask_1211; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1040 = {hi_447, flags_0_go, _out_prepend_T_1040}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11662 = out_prepend_1040; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11663 = _out_T_11662; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1041 = _out_T_11663; // @[RegisterRouter.scala:87:24] wire out_rimask_1212 = \|_out_rimask_T_1212; // @[RegisterRouter.scala:87:24] wire out_wimask_1212 = &_out_wimask_T_1212; // @[RegisterRouter.scala:87:24] wire out_romask_1212 = \|_out_romask_T_1212; // @[RegisterRouter.scala:87:24] wire out_womask_1212 = &_out_womask_T_1212; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1212 = out_rivalid_1_1066 & out_rimask_1212; // @[RegisterRouter.scala:87:24] wire _out_T_11665 = out_f_rivalid_1212; // @[RegisterRouter.scala:87:24] wire out_f_roready_1212 = out_roready_1_1066 & out_romask_1212; // @[RegisterRouter.scala:87:24] wire _out_T_11666 = out_f_roready_1212; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1212 = out_wivalid_1_1066 & out_wimask_1212; // @[RegisterRouter.scala:87:24] wire out_f_woready_1212 = out_woready_1_1066 & out_womask_1212; // @[RegisterRouter.scala:87:24] wire _out_T_11667 = ~out_rimask_1212; // @[RegisterRouter.scala:87:24] wire _out_T_11668 = ~out_wimask_1212; // @[RegisterRouter.scala:87:24] wire _out_T_11669 = ~out_romask_1212; // @[RegisterRouter.scala:87:24] wire _out_T_11670 = ~out_womask_1212; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1041 = {hi_448, flags_0_go, _out_prepend_T_1041}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11671 = out_prepend_1041; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11672 = _out_T_11671; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_183 = _out_T_11672; // @[MuxLiteral.scala:49:48] wire out_rimask_1213 = \|_out_rimask_T_1213; // @[RegisterRouter.scala:87:24] wire out_wimask_1213 = &_out_wimask_T_1213; // @[RegisterRouter.scala:87:24] wire out_romask_1213 = \|_out_romask_T_1213; // @[RegisterRouter.scala:87:24] wire out_womask_1213 = &_out_womask_T_1213; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1213 = out_rivalid_1_1067 & out_rimask_1213; // @[RegisterRouter.scala:87:24] wire _out_T_11674 = out_f_rivalid_1213; // @[RegisterRouter.scala:87:24] wire out_f_roready_1213 = out_roready_1_1067 & out_romask_1213; // @[RegisterRouter.scala:87:24] wire _out_T_11675 = out_f_roready_1213; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1213 = out_wivalid_1_1067 & out_wimask_1213; // @[RegisterRouter.scala:87:24] wire out_f_woready_1213 = out_woready_1_1067 & out_womask_1213; // @[RegisterRouter.scala:87:24] wire _out_T_11676 = ~out_rimask_1213; // @[RegisterRouter.scala:87:24] wire _out_T_11677 = ~out_wimask_1213; // @[RegisterRouter.scala:87:24] wire _out_T_11678 = ~out_romask_1213; // @[RegisterRouter.scala:87:24] wire _out_T_11679 = ~out_womask_1213; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11681 = _out_T_11680; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1042 = _out_T_11681; // @[RegisterRouter.scala:87:24] wire out_rimask_1214 = \|_out_rimask_T_1214; // @[RegisterRouter.scala:87:24] wire out_wimask_1214 = &_out_wimask_T_1214; // @[RegisterRouter.scala:87:24] wire out_romask_1214 = \|_out_romask_T_1214; // @[RegisterRouter.scala:87:24] wire out_womask_1214 = &_out_womask_T_1214; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1214 = out_rivalid_1_1068 & out_rimask_1214; // @[RegisterRouter.scala:87:24] wire _out_T_11683 = out_f_rivalid_1214; // @[RegisterRouter.scala:87:24] wire out_f_roready_1214 = out_roready_1_1068 & out_romask_1214; // @[RegisterRouter.scala:87:24] wire _out_T_11684 = out_f_roready_1214; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1214 = out_wivalid_1_1068 & out_wimask_1214; // @[RegisterRouter.scala:87:24] wire out_f_woready_1214 = out_woready_1_1068 & out_womask_1214; // @[RegisterRouter.scala:87:24] wire _out_T_11685 = ~out_rimask_1214; // @[RegisterRouter.scala:87:24] wire _out_T_11686 = ~out_wimask_1214; // @[RegisterRouter.scala:87:24] wire _out_T_11687 = ~out_romask_1214; // @[RegisterRouter.scala:87:24] wire _out_T_11688 = ~out_womask_1214; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1042 = {hi_322, flags_0_go, _out_prepend_T_1042}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11689 = out_prepend_1042; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11690 = _out_T_11689; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1043 = _out_T_11690; // @[RegisterRouter.scala:87:24] wire out_rimask_1215 = \|_out_rimask_T_1215; // @[RegisterRouter.scala:87:24] wire out_wimask_1215 = &_out_wimask_T_1215; // @[RegisterRouter.scala:87:24] wire out_romask_1215 = \|_out_romask_T_1215; // @[RegisterRouter.scala:87:24] wire out_womask_1215 = &_out_womask_T_1215; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1215 = out_rivalid_1_1069 & out_rimask_1215; // @[RegisterRouter.scala:87:24] wire _out_T_11692 = out_f_rivalid_1215; // @[RegisterRouter.scala:87:24] wire out_f_roready_1215 = out_roready_1_1069 & out_romask_1215; // @[RegisterRouter.scala:87:24] wire _out_T_11693 = out_f_roready_1215; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1215 = out_wivalid_1_1069 & out_wimask_1215; // @[RegisterRouter.scala:87:24] wire out_f_woready_1215 = out_woready_1_1069 & out_womask_1215; // @[RegisterRouter.scala:87:24] wire _out_T_11694 = ~out_rimask_1215; // @[RegisterRouter.scala:87:24] wire _out_T_11695 = ~out_wimask_1215; // @[RegisterRouter.scala:87:24] wire _out_T_11696 = ~out_romask_1215; // @[RegisterRouter.scala:87:24] wire _out_T_11697 = ~out_womask_1215; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1043 = {hi_323, flags_0_go, _out_prepend_T_1043}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11698 = out_prepend_1043; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11699 = _out_T_11698; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1044 = _out_T_11699; // @[RegisterRouter.scala:87:24] wire out_rimask_1216 = \|_out_rimask_T_1216; // @[RegisterRouter.scala:87:24] wire out_wimask_1216 = &_out_wimask_T_1216; // @[RegisterRouter.scala:87:24] wire out_romask_1216 = \|_out_romask_T_1216; // @[RegisterRouter.scala:87:24] wire out_womask_1216 = &_out_womask_T_1216; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1216 = out_rivalid_1_1070 & out_rimask_1216; // @[RegisterRouter.scala:87:24] wire _out_T_11701 = out_f_rivalid_1216; // @[RegisterRouter.scala:87:24] wire out_f_roready_1216 = out_roready_1_1070 & out_romask_1216; // @[RegisterRouter.scala:87:24] wire _out_T_11702 = out_f_roready_1216; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1216 = out_wivalid_1_1070 & out_wimask_1216; // @[RegisterRouter.scala:87:24] wire out_f_woready_1216 = out_woready_1_1070 & out_womask_1216; // @[RegisterRouter.scala:87:24] wire _out_T_11703 = ~out_rimask_1216; // @[RegisterRouter.scala:87:24] wire _out_T_11704 = ~out_wimask_1216; // @[RegisterRouter.scala:87:24] wire _out_T_11705 = ~out_romask_1216; // @[RegisterRouter.scala:87:24] wire _out_T_11706 = ~out_womask_1216; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1044 = {hi_324, flags_0_go, _out_prepend_T_1044}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11707 = out_prepend_1044; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11708 = _out_T_11707; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1045 = _out_T_11708; // @[RegisterRouter.scala:87:24] wire out_rimask_1217 = \|_out_rimask_T_1217; // @[RegisterRouter.scala:87:24] wire out_wimask_1217 = &_out_wimask_T_1217; // @[RegisterRouter.scala:87:24] wire out_romask_1217 = \|_out_romask_T_1217; // @[RegisterRouter.scala:87:24] wire out_womask_1217 = &_out_womask_T_1217; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1217 = out_rivalid_1_1071 & out_rimask_1217; // @[RegisterRouter.scala:87:24] wire _out_T_11710 = out_f_rivalid_1217; // @[RegisterRouter.scala:87:24] wire out_f_roready_1217 = out_roready_1_1071 & out_romask_1217; // @[RegisterRouter.scala:87:24] wire _out_T_11711 = out_f_roready_1217; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1217 = out_wivalid_1_1071 & out_wimask_1217; // @[RegisterRouter.scala:87:24] wire out_f_woready_1217 = out_woready_1_1071 & out_womask_1217; // @[RegisterRouter.scala:87:24] wire _out_T_11712 = ~out_rimask_1217; // @[RegisterRouter.scala:87:24] wire _out_T_11713 = ~out_wimask_1217; // @[RegisterRouter.scala:87:24] wire _out_T_11714 = ~out_romask_1217; // @[RegisterRouter.scala:87:24] wire _out_T_11715 = ~out_womask_1217; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1045 = {hi_325, flags_0_go, _out_prepend_T_1045}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11716 = out_prepend_1045; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11717 = _out_T_11716; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1046 = _out_T_11717; // @[RegisterRouter.scala:87:24] wire out_rimask_1218 = \|_out_rimask_T_1218; // @[RegisterRouter.scala:87:24] wire out_wimask_1218 = &_out_wimask_T_1218; // @[RegisterRouter.scala:87:24] wire out_romask_1218 = \|_out_romask_T_1218; // @[RegisterRouter.scala:87:24] wire out_womask_1218 = &_out_womask_T_1218; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1218 = out_rivalid_1_1072 & out_rimask_1218; // @[RegisterRouter.scala:87:24] wire _out_T_11719 = out_f_rivalid_1218; // @[RegisterRouter.scala:87:24] wire out_f_roready_1218 = out_roready_1_1072 & out_romask_1218; // @[RegisterRouter.scala:87:24] wire _out_T_11720 = out_f_roready_1218; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1218 = out_wivalid_1_1072 & out_wimask_1218; // @[RegisterRouter.scala:87:24] wire out_f_woready_1218 = out_woready_1_1072 & out_womask_1218; // @[RegisterRouter.scala:87:24] wire _out_T_11721 = ~out_rimask_1218; // @[RegisterRouter.scala:87:24] wire _out_T_11722 = ~out_wimask_1218; // @[RegisterRouter.scala:87:24] wire _out_T_11723 = ~out_romask_1218; // @[RegisterRouter.scala:87:24] wire _out_T_11724 = ~out_womask_1218; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1046 = {hi_326, flags_0_go, _out_prepend_T_1046}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11725 = out_prepend_1046; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11726 = _out_T_11725; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1047 = _out_T_11726; // @[RegisterRouter.scala:87:24] wire out_rimask_1219 = \|_out_rimask_T_1219; // @[RegisterRouter.scala:87:24] wire out_wimask_1219 = &_out_wimask_T_1219; // @[RegisterRouter.scala:87:24] wire out_romask_1219 = \|_out_romask_T_1219; // @[RegisterRouter.scala:87:24] wire out_womask_1219 = &_out_womask_T_1219; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1219 = out_rivalid_1_1073 & out_rimask_1219; // @[RegisterRouter.scala:87:24] wire _out_T_11728 = out_f_rivalid_1219; // @[RegisterRouter.scala:87:24] wire out_f_roready_1219 = out_roready_1_1073 & out_romask_1219; // @[RegisterRouter.scala:87:24] wire _out_T_11729 = out_f_roready_1219; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1219 = out_wivalid_1_1073 & out_wimask_1219; // @[RegisterRouter.scala:87:24] wire out_f_woready_1219 = out_woready_1_1073 & out_womask_1219; // @[RegisterRouter.scala:87:24] wire _out_T_11730 = ~out_rimask_1219; // @[RegisterRouter.scala:87:24] wire _out_T_11731 = ~out_wimask_1219; // @[RegisterRouter.scala:87:24] wire _out_T_11732 = ~out_romask_1219; // @[RegisterRouter.scala:87:24] wire _out_T_11733 = ~out_womask_1219; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1047 = {hi_327, flags_0_go, _out_prepend_T_1047}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11734 = out_prepend_1047; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11735 = _out_T_11734; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1048 = _out_T_11735; // @[RegisterRouter.scala:87:24] wire out_rimask_1220 = \|_out_rimask_T_1220; // @[RegisterRouter.scala:87:24] wire out_wimask_1220 = &_out_wimask_T_1220; // @[RegisterRouter.scala:87:24] wire out_romask_1220 = \|_out_romask_T_1220; // @[RegisterRouter.scala:87:24] wire out_womask_1220 = &_out_womask_T_1220; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1220 = out_rivalid_1_1074 & out_rimask_1220; // @[RegisterRouter.scala:87:24] wire _out_T_11737 = out_f_rivalid_1220; // @[RegisterRouter.scala:87:24] wire out_f_roready_1220 = out_roready_1_1074 & out_romask_1220; // @[RegisterRouter.scala:87:24] wire _out_T_11738 = out_f_roready_1220; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1220 = out_wivalid_1_1074 & out_wimask_1220; // @[RegisterRouter.scala:87:24] wire out_f_woready_1220 = out_woready_1_1074 & out_womask_1220; // @[RegisterRouter.scala:87:24] wire _out_T_11739 = ~out_rimask_1220; // @[RegisterRouter.scala:87:24] wire _out_T_11740 = ~out_wimask_1220; // @[RegisterRouter.scala:87:24] wire _out_T_11741 = ~out_romask_1220; // @[RegisterRouter.scala:87:24] wire _out_T_11742 = ~out_womask_1220; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1048 = {hi_328, flags_0_go, _out_prepend_T_1048}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11743 = out_prepend_1048; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11744 = _out_T_11743; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_168 = _out_T_11744; // @[MuxLiteral.scala:49:48] wire out_rimask_1221 = \|_out_rimask_T_1221; // @[RegisterRouter.scala:87:24] wire out_wimask_1221 = &_out_wimask_T_1221; // @[RegisterRouter.scala:87:24] wire out_romask_1221 = \|_out_romask_T_1221; // @[RegisterRouter.scala:87:24] wire out_womask_1221 = &_out_womask_T_1221; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1221 = out_rivalid_1_1075 & out_rimask_1221; // @[RegisterRouter.scala:87:24] wire _out_T_11746 = out_f_rivalid_1221; // @[RegisterRouter.scala:87:24] wire out_f_roready_1221 = out_roready_1_1075 & out_romask_1221; // @[RegisterRouter.scala:87:24] wire _out_T_11747 = out_f_roready_1221; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1221 = out_wivalid_1_1075 & out_wimask_1221; // @[RegisterRouter.scala:87:24] wire out_f_woready_1221 = out_woready_1_1075 & out_womask_1221; // @[RegisterRouter.scala:87:24] wire _out_T_11748 = ~out_rimask_1221; // @[RegisterRouter.scala:87:24] wire _out_T_11749 = ~out_wimask_1221; // @[RegisterRouter.scala:87:24] wire _out_T_11750 = ~out_romask_1221; // @[RegisterRouter.scala:87:24] wire _out_T_11751 = ~out_womask_1221; // @[RegisterRouter.scala:87:24] wire out_rimask_1222 = \|_out_rimask_T_1222; // @[RegisterRouter.scala:87:24] wire out_wimask_1222 = &_out_wimask_T_1222; // @[RegisterRouter.scala:87:24] wire out_romask_1222 = \|_out_romask_T_1222; // @[RegisterRouter.scala:87:24] wire out_womask_1222 = &_out_womask_T_1222; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1222 = out_rivalid_1_1076 & out_rimask_1222; // @[RegisterRouter.scala:87:24] wire _out_T_11755 = out_f_rivalid_1222; // @[RegisterRouter.scala:87:24] wire out_f_roready_1222 = out_roready_1_1076 & out_romask_1222; // @[RegisterRouter.scala:87:24] wire _out_T_11756 = out_f_roready_1222; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1222 = out_wivalid_1_1076 & out_wimask_1222; // @[RegisterRouter.scala:87:24] wire out_f_woready_1222 = out_woready_1_1076 & out_womask_1222; // @[RegisterRouter.scala:87:24] wire _out_T_11757 = ~out_rimask_1222; // @[RegisterRouter.scala:87:24] wire _out_T_11758 = ~out_wimask_1222; // @[RegisterRouter.scala:87:24] wire _out_T_11759 = ~out_romask_1222; // @[RegisterRouter.scala:87:24] wire _out_T_11760 = ~out_womask_1222; // @[RegisterRouter.scala:87:24] wire out_rimask_1223 = \|_out_rimask_T_1223; // @[RegisterRouter.scala:87:24] wire out_wimask_1223 = &_out_wimask_T_1223; // @[RegisterRouter.scala:87:24] wire out_romask_1223 = \|_out_romask_T_1223; // @[RegisterRouter.scala:87:24] wire out_womask_1223 = &_out_womask_T_1223; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1223 = out_rivalid_1_1077 & out_rimask_1223; // @[RegisterRouter.scala:87:24] wire _out_T_11764 = out_f_rivalid_1223; // @[RegisterRouter.scala:87:24] wire out_f_roready_1223 = out_roready_1_1077 & out_romask_1223; // @[RegisterRouter.scala:87:24] wire _out_T_11765 = out_f_roready_1223; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1223 = out_wivalid_1_1077 & out_wimask_1223; // @[RegisterRouter.scala:87:24] wire out_f_woready_1223 = out_woready_1_1077 & out_womask_1223; // @[RegisterRouter.scala:87:24] wire _out_T_11766 = ~out_rimask_1223; // @[RegisterRouter.scala:87:24] wire _out_T_11767 = ~out_wimask_1223; // @[RegisterRouter.scala:87:24] wire _out_T_11768 = ~out_romask_1223; // @[RegisterRouter.scala:87:24] wire _out_T_11769 = ~out_womask_1223; // @[RegisterRouter.scala:87:24] wire out_rimask_1224 = \|_out_rimask_T_1224; // @[RegisterRouter.scala:87:24] wire out_wimask_1224 = &_out_wimask_T_1224; // @[RegisterRouter.scala:87:24] wire out_romask_1224 = \|_out_romask_T_1224; // @[RegisterRouter.scala:87:24] wire out_womask_1224 = &_out_womask_T_1224; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1224 = out_rivalid_1_1078 & out_rimask_1224; // @[RegisterRouter.scala:87:24] wire _out_T_11773 = out_f_rivalid_1224; // @[RegisterRouter.scala:87:24] wire out_f_roready_1224 = out_roready_1_1078 & out_romask_1224; // @[RegisterRouter.scala:87:24] wire _out_T_11774 = out_f_roready_1224; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1224 = out_wivalid_1_1078 & out_wimask_1224; // @[RegisterRouter.scala:87:24] wire out_f_woready_1224 = out_woready_1_1078 & out_womask_1224; // @[RegisterRouter.scala:87:24] wire _out_T_11775 = ~out_rimask_1224; // @[RegisterRouter.scala:87:24] wire _out_T_11776 = ~out_wimask_1224; // @[RegisterRouter.scala:87:24] wire _out_T_11777 = ~out_romask_1224; // @[RegisterRouter.scala:87:24] wire _out_T_11778 = ~out_womask_1224; // @[RegisterRouter.scala:87:24] wire out_rimask_1225 = \|_out_rimask_T_1225; // @[RegisterRouter.scala:87:24] wire out_wimask_1225 = &_out_wimask_T_1225; // @[RegisterRouter.scala:87:24] wire out_romask_1225 = \|_out_romask_T_1225; // @[RegisterRouter.scala:87:24] wire out_womask_1225 = &_out_womask_T_1225; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1225 = out_rivalid_1_1079 & out_rimask_1225; // @[RegisterRouter.scala:87:24] wire _out_T_11782 = out_f_rivalid_1225; // @[RegisterRouter.scala:87:24] wire out_f_roready_1225 = out_roready_1_1079 & out_romask_1225; // @[RegisterRouter.scala:87:24] wire _out_T_11783 = out_f_roready_1225; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1225 = out_wivalid_1_1079 & out_wimask_1225; // @[RegisterRouter.scala:87:24] wire out_f_woready_1225 = out_woready_1_1079 & out_womask_1225; // @[RegisterRouter.scala:87:24] wire _out_T_11784 = ~out_rimask_1225; // @[RegisterRouter.scala:87:24] wire _out_T_11785 = ~out_wimask_1225; // @[RegisterRouter.scala:87:24] wire _out_T_11786 = ~out_romask_1225; // @[RegisterRouter.scala:87:24] wire _out_T_11787 = ~out_womask_1225; // @[RegisterRouter.scala:87:24] wire out_rimask_1226 = \|_out_rimask_T_1226; // @[RegisterRouter.scala:87:24] wire out_wimask_1226 = &_out_wimask_T_1226; // @[RegisterRouter.scala:87:24] wire out_romask_1226 = \|_out_romask_T_1226; // @[RegisterRouter.scala:87:24] wire out_womask_1226 = &_out_womask_T_1226; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1226 = out_rivalid_1_1080 & out_rimask_1226; // @[RegisterRouter.scala:87:24] wire _out_T_11791 = out_f_rivalid_1226; // @[RegisterRouter.scala:87:24] wire out_f_roready_1226 = out_roready_1_1080 & out_romask_1226; // @[RegisterRouter.scala:87:24] wire _out_T_11792 = out_f_roready_1226; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1226 = out_wivalid_1_1080 & out_wimask_1226; // @[RegisterRouter.scala:87:24] wire out_f_woready_1226 = out_woready_1_1080 & out_womask_1226; // @[RegisterRouter.scala:87:24] wire _out_T_11793 = ~out_rimask_1226; // @[RegisterRouter.scala:87:24] wire _out_T_11794 = ~out_wimask_1226; // @[RegisterRouter.scala:87:24] wire _out_T_11795 = ~out_romask_1226; // @[RegisterRouter.scala:87:24] wire _out_T_11796 = ~out_womask_1226; // @[RegisterRouter.scala:87:24] wire out_rimask_1227 = \|_out_rimask_T_1227; // @[RegisterRouter.scala:87:24] wire out_wimask_1227 = &_out_wimask_T_1227; // @[RegisterRouter.scala:87:24] wire out_romask_1227 = \|_out_romask_T_1227; // @[RegisterRouter.scala:87:24] wire out_womask_1227 = &_out_womask_T_1227; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1227 = out_rivalid_1_1081 & out_rimask_1227; // @[RegisterRouter.scala:87:24] wire _out_T_11800 = out_f_rivalid_1227; // @[RegisterRouter.scala:87:24] wire out_f_roready_1227 = out_roready_1_1081 & out_romask_1227; // @[RegisterRouter.scala:87:24] wire _out_T_11801 = out_f_roready_1227; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1227 = out_wivalid_1_1081 & out_wimask_1227; // @[RegisterRouter.scala:87:24] wire out_f_woready_1227 = out_woready_1_1081 & out_womask_1227; // @[RegisterRouter.scala:87:24] wire _out_T_11802 = ~out_rimask_1227; // @[RegisterRouter.scala:87:24] wire _out_T_11803 = ~out_wimask_1227; // @[RegisterRouter.scala:87:24] wire _out_T_11804 = ~out_romask_1227; // @[RegisterRouter.scala:87:24] wire _out_T_11805 = ~out_womask_1227; // @[RegisterRouter.scala:87:24] wire out_rimask_1228 = \|_out_rimask_T_1228; // @[RegisterRouter.scala:87:24] wire out_wimask_1228 = &_out_wimask_T_1228; // @[RegisterRouter.scala:87:24] wire out_romask_1228 = \|_out_romask_T_1228; // @[RegisterRouter.scala:87:24] wire out_womask_1228 = &_out_womask_T_1228; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1228 = out_rivalid_1_1082 & out_rimask_1228; // @[RegisterRouter.scala:87:24] wire _out_T_11809 = out_f_rivalid_1228; // @[RegisterRouter.scala:87:24] wire out_f_roready_1228 = out_roready_1_1082 & out_romask_1228; // @[RegisterRouter.scala:87:24] wire _out_T_11810 = out_f_roready_1228; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1228 = out_wivalid_1_1082 & out_wimask_1228; // @[RegisterRouter.scala:87:24] wire out_f_woready_1228 = out_woready_1_1082 & out_womask_1228; // @[RegisterRouter.scala:87:24] wire _out_T_11811 = ~out_rimask_1228; // @[RegisterRouter.scala:87:24] wire _out_T_11812 = ~out_wimask_1228; // @[RegisterRouter.scala:87:24] wire _out_T_11813 = ~out_romask_1228; // @[RegisterRouter.scala:87:24] wire _out_T_11814 = ~out_womask_1228; // @[RegisterRouter.scala:87:24] wire out_rimask_1229 = \|_out_rimask_T_1229; // @[RegisterRouter.scala:87:24] wire out_wimask_1229 = &_out_wimask_T_1229; // @[RegisterRouter.scala:87:24] wire out_romask_1229 = \|_out_romask_T_1229; // @[RegisterRouter.scala:87:24] wire out_womask_1229 = &_out_womask_T_1229; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1229 = out_rivalid_1_1083 & out_rimask_1229; // @[RegisterRouter.scala:87:24] wire _out_T_11818 = out_f_rivalid_1229; // @[RegisterRouter.scala:87:24] wire out_f_roready_1229 = out_roready_1_1083 & out_romask_1229; // @[RegisterRouter.scala:87:24] wire _out_T_11819 = out_f_roready_1229; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1229 = out_wivalid_1_1083 & out_wimask_1229; // @[RegisterRouter.scala:87:24] wire out_f_woready_1229 = out_woready_1_1083 & out_womask_1229; // @[RegisterRouter.scala:87:24] wire _out_T_11820 = ~out_rimask_1229; // @[RegisterRouter.scala:87:24] wire _out_T_11821 = ~out_wimask_1229; // @[RegisterRouter.scala:87:24] wire _out_T_11822 = ~out_romask_1229; // @[RegisterRouter.scala:87:24] wire _out_T_11823 = ~out_womask_1229; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11825 = _out_T_11824; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1056 = _out_T_11825; // @[RegisterRouter.scala:87:24] wire out_rimask_1230 = \|_out_rimask_T_1230; // @[RegisterRouter.scala:87:24] wire out_wimask_1230 = &_out_wimask_T_1230; // @[RegisterRouter.scala:87:24] wire out_romask_1230 = \|_out_romask_T_1230; // @[RegisterRouter.scala:87:24] wire out_womask_1230 = &_out_womask_T_1230; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1230 = out_rivalid_1_1084 & out_rimask_1230; // @[RegisterRouter.scala:87:24] wire _out_T_11827 = out_f_rivalid_1230; // @[RegisterRouter.scala:87:24] wire out_f_roready_1230 = out_roready_1_1084 & out_romask_1230; // @[RegisterRouter.scala:87:24] wire _out_T_11828 = out_f_roready_1230; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1230 = out_wivalid_1_1084 & out_wimask_1230; // @[RegisterRouter.scala:87:24] wire out_f_woready_1230 = out_woready_1_1084 & out_womask_1230; // @[RegisterRouter.scala:87:24] wire _out_T_11829 = ~out_rimask_1230; // @[RegisterRouter.scala:87:24] wire _out_T_11830 = ~out_wimask_1230; // @[RegisterRouter.scala:87:24] wire _out_T_11831 = ~out_romask_1230; // @[RegisterRouter.scala:87:24] wire _out_T_11832 = ~out_womask_1230; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1056 = {hi_658, flags_0_go, _out_prepend_T_1056}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11833 = out_prepend_1056; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11834 = _out_T_11833; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1057 = _out_T_11834; // @[RegisterRouter.scala:87:24] wire out_rimask_1231 = \|_out_rimask_T_1231; // @[RegisterRouter.scala:87:24] wire out_wimask_1231 = &_out_wimask_T_1231; // @[RegisterRouter.scala:87:24] wire out_romask_1231 = \|_out_romask_T_1231; // @[RegisterRouter.scala:87:24] wire out_womask_1231 = &_out_womask_T_1231; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1231 = out_rivalid_1_1085 & out_rimask_1231; // @[RegisterRouter.scala:87:24] wire _out_T_11836 = out_f_rivalid_1231; // @[RegisterRouter.scala:87:24] wire out_f_roready_1231 = out_roready_1_1085 & out_romask_1231; // @[RegisterRouter.scala:87:24] wire _out_T_11837 = out_f_roready_1231; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1231 = out_wivalid_1_1085 & out_wimask_1231; // @[RegisterRouter.scala:87:24] wire out_f_woready_1231 = out_woready_1_1085 & out_womask_1231; // @[RegisterRouter.scala:87:24] wire _out_T_11838 = ~out_rimask_1231; // @[RegisterRouter.scala:87:24] wire _out_T_11839 = ~out_wimask_1231; // @[RegisterRouter.scala:87:24] wire _out_T_11840 = ~out_romask_1231; // @[RegisterRouter.scala:87:24] wire _out_T_11841 = ~out_womask_1231; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1057 = {hi_659, flags_0_go, _out_prepend_T_1057}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11842 = out_prepend_1057; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11843 = _out_T_11842; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1058 = _out_T_11843; // @[RegisterRouter.scala:87:24] wire out_rimask_1232 = \|_out_rimask_T_1232; // @[RegisterRouter.scala:87:24] wire out_wimask_1232 = &_out_wimask_T_1232; // @[RegisterRouter.scala:87:24] wire out_romask_1232 = \|_out_romask_T_1232; // @[RegisterRouter.scala:87:24] wire out_womask_1232 = &_out_womask_T_1232; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1232 = out_rivalid_1_1086 & out_rimask_1232; // @[RegisterRouter.scala:87:24] wire _out_T_11845 = out_f_rivalid_1232; // @[RegisterRouter.scala:87:24] wire out_f_roready_1232 = out_roready_1_1086 & out_romask_1232; // @[RegisterRouter.scala:87:24] wire _out_T_11846 = out_f_roready_1232; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1232 = out_wivalid_1_1086 & out_wimask_1232; // @[RegisterRouter.scala:87:24] wire out_f_woready_1232 = out_woready_1_1086 & out_womask_1232; // @[RegisterRouter.scala:87:24] wire _out_T_11847 = ~out_rimask_1232; // @[RegisterRouter.scala:87:24] wire _out_T_11848 = ~out_wimask_1232; // @[RegisterRouter.scala:87:24] wire _out_T_11849 = ~out_romask_1232; // @[RegisterRouter.scala:87:24] wire _out_T_11850 = ~out_womask_1232; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1058 = {hi_660, flags_0_go, _out_prepend_T_1058}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11851 = out_prepend_1058; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11852 = _out_T_11851; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1059 = _out_T_11852; // @[RegisterRouter.scala:87:24] wire out_rimask_1233 = \|_out_rimask_T_1233; // @[RegisterRouter.scala:87:24] wire out_wimask_1233 = &_out_wimask_T_1233; // @[RegisterRouter.scala:87:24] wire out_romask_1233 = \|_out_romask_T_1233; // @[RegisterRouter.scala:87:24] wire out_womask_1233 = &_out_womask_T_1233; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1233 = out_rivalid_1_1087 & out_rimask_1233; // @[RegisterRouter.scala:87:24] wire _out_T_11854 = out_f_rivalid_1233; // @[RegisterRouter.scala:87:24] wire out_f_roready_1233 = out_roready_1_1087 & out_romask_1233; // @[RegisterRouter.scala:87:24] wire _out_T_11855 = out_f_roready_1233; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1233 = out_wivalid_1_1087 & out_wimask_1233; // @[RegisterRouter.scala:87:24] wire out_f_woready_1233 = out_woready_1_1087 & out_womask_1233; // @[RegisterRouter.scala:87:24] wire _out_T_11856 = ~out_rimask_1233; // @[RegisterRouter.scala:87:24] wire _out_T_11857 = ~out_wimask_1233; // @[RegisterRouter.scala:87:24] wire _out_T_11858 = ~out_romask_1233; // @[RegisterRouter.scala:87:24] wire _out_T_11859 = ~out_womask_1233; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1059 = {hi_661, flags_0_go, _out_prepend_T_1059}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11860 = out_prepend_1059; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11861 = _out_T_11860; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1060 = _out_T_11861; // @[RegisterRouter.scala:87:24] wire out_rimask_1234 = \|_out_rimask_T_1234; // @[RegisterRouter.scala:87:24] wire out_wimask_1234 = &_out_wimask_T_1234; // @[RegisterRouter.scala:87:24] wire out_romask_1234 = \|_out_romask_T_1234; // @[RegisterRouter.scala:87:24] wire out_womask_1234 = &_out_womask_T_1234; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1234 = out_rivalid_1_1088 & out_rimask_1234; // @[RegisterRouter.scala:87:24] wire _out_T_11863 = out_f_rivalid_1234; // @[RegisterRouter.scala:87:24] wire out_f_roready_1234 = out_roready_1_1088 & out_romask_1234; // @[RegisterRouter.scala:87:24] wire _out_T_11864 = out_f_roready_1234; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1234 = out_wivalid_1_1088 & out_wimask_1234; // @[RegisterRouter.scala:87:24] wire out_f_woready_1234 = out_woready_1_1088 & out_womask_1234; // @[RegisterRouter.scala:87:24] wire _out_T_11865 = ~out_rimask_1234; // @[RegisterRouter.scala:87:24] wire _out_T_11866 = ~out_wimask_1234; // @[RegisterRouter.scala:87:24] wire _out_T_11867 = ~out_romask_1234; // @[RegisterRouter.scala:87:24] wire _out_T_11868 = ~out_womask_1234; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1060 = {hi_662, flags_0_go, _out_prepend_T_1060}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11869 = out_prepend_1060; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11870 = _out_T_11869; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1061 = _out_T_11870; // @[RegisterRouter.scala:87:24] wire out_rimask_1235 = \|_out_rimask_T_1235; // @[RegisterRouter.scala:87:24] wire out_wimask_1235 = &_out_wimask_T_1235; // @[RegisterRouter.scala:87:24] wire out_romask_1235 = \|_out_romask_T_1235; // @[RegisterRouter.scala:87:24] wire out_womask_1235 = &_out_womask_T_1235; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1235 = out_rivalid_1_1089 & out_rimask_1235; // @[RegisterRouter.scala:87:24] wire _out_T_11872 = out_f_rivalid_1235; // @[RegisterRouter.scala:87:24] wire out_f_roready_1235 = out_roready_1_1089 & out_romask_1235; // @[RegisterRouter.scala:87:24] wire _out_T_11873 = out_f_roready_1235; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1235 = out_wivalid_1_1089 & out_wimask_1235; // @[RegisterRouter.scala:87:24] wire out_f_woready_1235 = out_woready_1_1089 & out_womask_1235; // @[RegisterRouter.scala:87:24] wire _out_T_11874 = ~out_rimask_1235; // @[RegisterRouter.scala:87:24] wire _out_T_11875 = ~out_wimask_1235; // @[RegisterRouter.scala:87:24] wire _out_T_11876 = ~out_romask_1235; // @[RegisterRouter.scala:87:24] wire _out_T_11877 = ~out_womask_1235; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1061 = {hi_663, flags_0_go, _out_prepend_T_1061}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11878 = out_prepend_1061; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11879 = _out_T_11878; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1062 = _out_T_11879; // @[RegisterRouter.scala:87:24] wire out_rimask_1236 = \|_out_rimask_T_1236; // @[RegisterRouter.scala:87:24] wire out_wimask_1236 = &_out_wimask_T_1236; // @[RegisterRouter.scala:87:24] wire out_romask_1236 = \|_out_romask_T_1236; // @[RegisterRouter.scala:87:24] wire out_womask_1236 = &_out_womask_T_1236; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1236 = out_rivalid_1_1090 & out_rimask_1236; // @[RegisterRouter.scala:87:24] wire _out_T_11881 = out_f_rivalid_1236; // @[RegisterRouter.scala:87:24] wire out_f_roready_1236 = out_roready_1_1090 & out_romask_1236; // @[RegisterRouter.scala:87:24] wire _out_T_11882 = out_f_roready_1236; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1236 = out_wivalid_1_1090 & out_wimask_1236; // @[RegisterRouter.scala:87:24] wire out_f_woready_1236 = out_woready_1_1090 & out_womask_1236; // @[RegisterRouter.scala:87:24] wire _out_T_11883 = ~out_rimask_1236; // @[RegisterRouter.scala:87:24] wire _out_T_11884 = ~out_wimask_1236; // @[RegisterRouter.scala:87:24] wire _out_T_11885 = ~out_romask_1236; // @[RegisterRouter.scala:87:24] wire _out_T_11886 = ~out_womask_1236; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1062 = {hi_664, flags_0_go, _out_prepend_T_1062}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11887 = out_prepend_1062; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11888 = _out_T_11887; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_210 = _out_T_11888; // @[MuxLiteral.scala:49:48] wire out_rimask_1237 = \|_out_rimask_T_1237; // @[RegisterRouter.scala:87:24] wire out_wimask_1237 = &_out_wimask_T_1237; // @[RegisterRouter.scala:87:24] wire out_romask_1237 = \|_out_romask_T_1237; // @[RegisterRouter.scala:87:24] wire out_womask_1237 = &_out_womask_T_1237; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1237 = out_rivalid_1_1091 & out_rimask_1237; // @[RegisterRouter.scala:87:24] wire _out_T_11890 = out_f_rivalid_1237; // @[RegisterRouter.scala:87:24] wire out_f_roready_1237 = out_roready_1_1091 & out_romask_1237; // @[RegisterRouter.scala:87:24] wire _out_T_11891 = out_f_roready_1237; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1237 = out_wivalid_1_1091 & out_wimask_1237; // @[RegisterRouter.scala:87:24] wire _out_T_11892 = out_f_wivalid_1237; // @[RegisterRouter.scala:87:24] wire out_f_woready_1237 = out_woready_1_1091 & out_womask_1237; // @[RegisterRouter.scala:87:24] wire _out_T_11893 = out_f_woready_1237; // @[RegisterRouter.scala:87:24] wire _out_T_11894 = ~out_rimask_1237; // @[RegisterRouter.scala:87:24] wire _out_T_11895 = ~out_wimask_1237; // @[RegisterRouter.scala:87:24] wire _out_T_11896 = ~out_romask_1237; // @[RegisterRouter.scala:87:24] wire _out_T_11897 = ~out_womask_1237; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11899 = _out_T_11898; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1063 = _out_T_11899; // @[RegisterRouter.scala:87:24] wire out_rimask_1238 = \|_out_rimask_T_1238; // @[RegisterRouter.scala:87:24] wire out_wimask_1238 = &_out_wimask_T_1238; // @[RegisterRouter.scala:87:24] wire out_romask_1238 = \|_out_romask_T_1238; // @[RegisterRouter.scala:87:24] wire out_womask_1238 = &_out_womask_T_1238; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1238 = out_rivalid_1_1092 & out_rimask_1238; // @[RegisterRouter.scala:87:24] wire _out_T_11901 = out_f_rivalid_1238; // @[RegisterRouter.scala:87:24] wire out_f_roready_1238 = out_roready_1_1092 & out_romask_1238; // @[RegisterRouter.scala:87:24] wire _out_T_11902 = out_f_roready_1238; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1238 = out_wivalid_1_1092 & out_wimask_1238; // @[RegisterRouter.scala:87:24] wire _out_T_11903 = out_f_wivalid_1238; // @[RegisterRouter.scala:87:24] wire out_f_woready_1238 = out_woready_1_1092 & out_womask_1238; // @[RegisterRouter.scala:87:24] wire _out_T_11904 = out_f_woready_1238; // @[RegisterRouter.scala:87:24] wire _out_T_11905 = ~out_rimask_1238; // @[RegisterRouter.scala:87:24] wire _out_T_11906 = ~out_wimask_1238; // @[RegisterRouter.scala:87:24] wire _out_T_11907 = ~out_romask_1238; // @[RegisterRouter.scala:87:24] wire _out_T_11908 = ~out_womask_1238; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1063 = {programBufferMem_25, _out_prepend_T_1063}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11909 = out_prepend_1063; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11910 = _out_T_11909; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1064 = _out_T_11910; // @[RegisterRouter.scala:87:24] wire out_rimask_1239 = \|_out_rimask_T_1239; // @[RegisterRouter.scala:87:24] wire out_wimask_1239 = &_out_wimask_T_1239; // @[RegisterRouter.scala:87:24] wire out_romask_1239 = \|_out_romask_T_1239; // @[RegisterRouter.scala:87:24] wire out_womask_1239 = &_out_womask_T_1239; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1239 = out_rivalid_1_1093 & out_rimask_1239; // @[RegisterRouter.scala:87:24] wire _out_T_11912 = out_f_rivalid_1239; // @[RegisterRouter.scala:87:24] wire out_f_roready_1239 = out_roready_1_1093 & out_romask_1239; // @[RegisterRouter.scala:87:24] wire _out_T_11913 = out_f_roready_1239; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1239 = out_wivalid_1_1093 & out_wimask_1239; // @[RegisterRouter.scala:87:24] wire _out_T_11914 = out_f_wivalid_1239; // @[RegisterRouter.scala:87:24] wire out_f_woready_1239 = out_woready_1_1093 & out_womask_1239; // @[RegisterRouter.scala:87:24] wire _out_T_11915 = out_f_woready_1239; // @[RegisterRouter.scala:87:24] wire _out_T_11916 = ~out_rimask_1239; // @[RegisterRouter.scala:87:24] wire _out_T_11917 = ~out_wimask_1239; // @[RegisterRouter.scala:87:24] wire _out_T_11918 = ~out_romask_1239; // @[RegisterRouter.scala:87:24] wire _out_T_11919 = ~out_womask_1239; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1064 = {programBufferMem_26, _out_prepend_T_1064}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11920 = out_prepend_1064; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11921 = _out_T_11920; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1065 = _out_T_11921; // @[RegisterRouter.scala:87:24] wire out_rimask_1240 = \|_out_rimask_T_1240; // @[RegisterRouter.scala:87:24] wire out_wimask_1240 = &_out_wimask_T_1240; // @[RegisterRouter.scala:87:24] wire out_romask_1240 = \|_out_romask_T_1240; // @[RegisterRouter.scala:87:24] wire out_womask_1240 = &_out_womask_T_1240; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1240 = out_rivalid_1_1094 & out_rimask_1240; // @[RegisterRouter.scala:87:24] wire _out_T_11923 = out_f_rivalid_1240; // @[RegisterRouter.scala:87:24] wire out_f_roready_1240 = out_roready_1_1094 & out_romask_1240; // @[RegisterRouter.scala:87:24] wire _out_T_11924 = out_f_roready_1240; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1240 = out_wivalid_1_1094 & out_wimask_1240; // @[RegisterRouter.scala:87:24] wire _out_T_11925 = out_f_wivalid_1240; // @[RegisterRouter.scala:87:24] wire out_f_woready_1240 = out_woready_1_1094 & out_womask_1240; // @[RegisterRouter.scala:87:24] wire _out_T_11926 = out_f_woready_1240; // @[RegisterRouter.scala:87:24] wire _out_T_11927 = ~out_rimask_1240; // @[RegisterRouter.scala:87:24] wire _out_T_11928 = ~out_wimask_1240; // @[RegisterRouter.scala:87:24] wire _out_T_11929 = ~out_romask_1240; // @[RegisterRouter.scala:87:24] wire _out_T_11930 = ~out_womask_1240; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1065 = {programBufferMem_27, _out_prepend_T_1065}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11931 = out_prepend_1065; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11932 = _out_T_11931; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1066 = _out_T_11932; // @[RegisterRouter.scala:87:24] wire out_rimask_1241 = \|_out_rimask_T_1241; // @[RegisterRouter.scala:87:24] wire out_wimask_1241 = &_out_wimask_T_1241; // @[RegisterRouter.scala:87:24] wire out_romask_1241 = \|_out_romask_T_1241; // @[RegisterRouter.scala:87:24] wire out_womask_1241 = &_out_womask_T_1241; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1241 = out_rivalid_1_1095 & out_rimask_1241; // @[RegisterRouter.scala:87:24] wire _out_T_11934 = out_f_rivalid_1241; // @[RegisterRouter.scala:87:24] wire out_f_roready_1241 = out_roready_1_1095 & out_romask_1241; // @[RegisterRouter.scala:87:24] wire _out_T_11935 = out_f_roready_1241; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1241 = out_wivalid_1_1095 & out_wimask_1241; // @[RegisterRouter.scala:87:24] wire _out_T_11936 = out_f_wivalid_1241; // @[RegisterRouter.scala:87:24] wire out_f_woready_1241 = out_woready_1_1095 & out_womask_1241; // @[RegisterRouter.scala:87:24] wire _out_T_11937 = out_f_woready_1241; // @[RegisterRouter.scala:87:24] wire _out_T_11938 = ~out_rimask_1241; // @[RegisterRouter.scala:87:24] wire _out_T_11939 = ~out_wimask_1241; // @[RegisterRouter.scala:87:24] wire _out_T_11940 = ~out_romask_1241; // @[RegisterRouter.scala:87:24] wire _out_T_11941 = ~out_womask_1241; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1066 = {programBufferMem_28, _out_prepend_T_1066}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11942 = out_prepend_1066; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11943 = _out_T_11942; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1067 = _out_T_11943; // @[RegisterRouter.scala:87:24] wire out_rimask_1242 = \|_out_rimask_T_1242; // @[RegisterRouter.scala:87:24] wire out_wimask_1242 = &_out_wimask_T_1242; // @[RegisterRouter.scala:87:24] wire out_romask_1242 = \|_out_romask_T_1242; // @[RegisterRouter.scala:87:24] wire out_womask_1242 = &_out_womask_T_1242; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1242 = out_rivalid_1_1096 & out_rimask_1242; // @[RegisterRouter.scala:87:24] wire _out_T_11945 = out_f_rivalid_1242; // @[RegisterRouter.scala:87:24] wire out_f_roready_1242 = out_roready_1_1096 & out_romask_1242; // @[RegisterRouter.scala:87:24] wire _out_T_11946 = out_f_roready_1242; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1242 = out_wivalid_1_1096 & out_wimask_1242; // @[RegisterRouter.scala:87:24] wire _out_T_11947 = out_f_wivalid_1242; // @[RegisterRouter.scala:87:24] wire out_f_woready_1242 = out_woready_1_1096 & out_womask_1242; // @[RegisterRouter.scala:87:24] wire _out_T_11948 = out_f_woready_1242; // @[RegisterRouter.scala:87:24] wire _out_T_11949 = ~out_rimask_1242; // @[RegisterRouter.scala:87:24] wire _out_T_11950 = ~out_wimask_1242; // @[RegisterRouter.scala:87:24] wire _out_T_11951 = ~out_romask_1242; // @[RegisterRouter.scala:87:24] wire _out_T_11952 = ~out_womask_1242; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1067 = {programBufferMem_29, _out_prepend_T_1067}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11953 = out_prepend_1067; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11954 = _out_T_11953; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1068 = _out_T_11954; // @[RegisterRouter.scala:87:24] wire out_rimask_1243 = \|_out_rimask_T_1243; // @[RegisterRouter.scala:87:24] wire out_wimask_1243 = &_out_wimask_T_1243; // @[RegisterRouter.scala:87:24] wire out_romask_1243 = \|_out_romask_T_1243; // @[RegisterRouter.scala:87:24] wire out_womask_1243 = &_out_womask_T_1243; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1243 = out_rivalid_1_1097 & out_rimask_1243; // @[RegisterRouter.scala:87:24] wire _out_T_11956 = out_f_rivalid_1243; // @[RegisterRouter.scala:87:24] wire out_f_roready_1243 = out_roready_1_1097 & out_romask_1243; // @[RegisterRouter.scala:87:24] wire _out_T_11957 = out_f_roready_1243; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1243 = out_wivalid_1_1097 & out_wimask_1243; // @[RegisterRouter.scala:87:24] wire _out_T_11958 = out_f_wivalid_1243; // @[RegisterRouter.scala:87:24] wire out_f_woready_1243 = out_woready_1_1097 & out_womask_1243; // @[RegisterRouter.scala:87:24] wire _out_T_11959 = out_f_woready_1243; // @[RegisterRouter.scala:87:24] wire _out_T_11960 = ~out_rimask_1243; // @[RegisterRouter.scala:87:24] wire _out_T_11961 = ~out_wimask_1243; // @[RegisterRouter.scala:87:24] wire _out_T_11962 = ~out_romask_1243; // @[RegisterRouter.scala:87:24] wire _out_T_11963 = ~out_womask_1243; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1068 = {programBufferMem_30, _out_prepend_T_1068}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11964 = out_prepend_1068; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11965 = _out_T_11964; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1069 = _out_T_11965; // @[RegisterRouter.scala:87:24] wire out_rimask_1244 = \|_out_rimask_T_1244; // @[RegisterRouter.scala:87:24] wire out_wimask_1244 = &_out_wimask_T_1244; // @[RegisterRouter.scala:87:24] wire out_romask_1244 = \|_out_romask_T_1244; // @[RegisterRouter.scala:87:24] wire out_womask_1244 = &_out_womask_T_1244; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1244 = out_rivalid_1_1098 & out_rimask_1244; // @[RegisterRouter.scala:87:24] wire _out_T_11967 = out_f_rivalid_1244; // @[RegisterRouter.scala:87:24] wire out_f_roready_1244 = out_roready_1_1098 & out_romask_1244; // @[RegisterRouter.scala:87:24] wire _out_T_11968 = out_f_roready_1244; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1244 = out_wivalid_1_1098 & out_wimask_1244; // @[RegisterRouter.scala:87:24] wire _out_T_11969 = out_f_wivalid_1244; // @[RegisterRouter.scala:87:24] wire out_f_woready_1244 = out_woready_1_1098 & out_womask_1244; // @[RegisterRouter.scala:87:24] wire _out_T_11970 = out_f_woready_1244; // @[RegisterRouter.scala:87:24] wire _out_T_11971 = ~out_rimask_1244; // @[RegisterRouter.scala:87:24] wire _out_T_11972 = ~out_wimask_1244; // @[RegisterRouter.scala:87:24] wire _out_T_11973 = ~out_romask_1244; // @[RegisterRouter.scala:87:24] wire _out_T_11974 = ~out_womask_1244; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1069 = {programBufferMem_31, _out_prepend_T_1069}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11975 = out_prepend_1069; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11976 = _out_T_11975; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_107 = _out_T_11976; // @[MuxLiteral.scala:49:48] wire out_rimask_1245 = \|_out_rimask_T_1245; // @[RegisterRouter.scala:87:24] wire out_wimask_1245 = &_out_wimask_T_1245; // @[RegisterRouter.scala:87:24] wire out_romask_1245 = \|_out_romask_T_1245; // @[RegisterRouter.scala:87:24] wire out_womask_1245 = &_out_womask_T_1245; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1245 = out_rivalid_1_1099 & out_rimask_1245; // @[RegisterRouter.scala:87:24] wire _out_T_11978 = out_f_rivalid_1245; // @[RegisterRouter.scala:87:24] wire out_f_roready_1245 = out_roready_1_1099 & out_romask_1245; // @[RegisterRouter.scala:87:24] wire _out_T_11979 = out_f_roready_1245; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1245 = out_wivalid_1_1099 & out_wimask_1245; // @[RegisterRouter.scala:87:24] wire out_f_woready_1245 = out_woready_1_1099 & out_womask_1245; // @[RegisterRouter.scala:87:24] wire _out_T_11980 = ~out_rimask_1245; // @[RegisterRouter.scala:87:24] wire _out_T_11981 = ~out_wimask_1245; // @[RegisterRouter.scala:87:24] wire _out_T_11982 = ~out_romask_1245; // @[RegisterRouter.scala:87:24] wire _out_T_11983 = ~out_womask_1245; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11985 = _out_T_11984; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1070 = _out_T_11985; // @[RegisterRouter.scala:87:24] wire out_rimask_1246 = \|_out_rimask_T_1246; // @[RegisterRouter.scala:87:24] wire out_wimask_1246 = &_out_wimask_T_1246; // @[RegisterRouter.scala:87:24] wire out_romask_1246 = \|_out_romask_T_1246; // @[RegisterRouter.scala:87:24] wire out_womask_1246 = &_out_womask_T_1246; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1246 = out_rivalid_1_1100 & out_rimask_1246; // @[RegisterRouter.scala:87:24] wire _out_T_11987 = out_f_rivalid_1246; // @[RegisterRouter.scala:87:24] wire out_f_roready_1246 = out_roready_1_1100 & out_romask_1246; // @[RegisterRouter.scala:87:24] wire _out_T_11988 = out_f_roready_1246; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1246 = out_wivalid_1_1100 & out_wimask_1246; // @[RegisterRouter.scala:87:24] wire out_f_woready_1246 = out_woready_1_1100 & out_womask_1246; // @[RegisterRouter.scala:87:24] wire _out_T_11989 = ~out_rimask_1246; // @[RegisterRouter.scala:87:24] wire _out_T_11990 = ~out_wimask_1246; // @[RegisterRouter.scala:87:24] wire _out_T_11991 = ~out_romask_1246; // @[RegisterRouter.scala:87:24] wire _out_T_11992 = ~out_womask_1246; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1070 = {hi_66, flags_0_go, _out_prepend_T_1070}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11993 = out_prepend_1070; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11994 = _out_T_11993; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1071 = _out_T_11994; // @[RegisterRouter.scala:87:24] wire out_rimask_1247 = \|_out_rimask_T_1247; // @[RegisterRouter.scala:87:24] wire out_wimask_1247 = &_out_wimask_T_1247; // @[RegisterRouter.scala:87:24] wire out_romask_1247 = \|_out_romask_T_1247; // @[RegisterRouter.scala:87:24] wire out_womask_1247 = &_out_womask_T_1247; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1247 = out_rivalid_1_1101 & out_rimask_1247; // @[RegisterRouter.scala:87:24] wire _out_T_11996 = out_f_rivalid_1247; // @[RegisterRouter.scala:87:24] wire out_f_roready_1247 = out_roready_1_1101 & out_romask_1247; // @[RegisterRouter.scala:87:24] wire _out_T_11997 = out_f_roready_1247; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1247 = out_wivalid_1_1101 & out_wimask_1247; // @[RegisterRouter.scala:87:24] wire out_f_woready_1247 = out_woready_1_1101 & out_womask_1247; // @[RegisterRouter.scala:87:24] wire _out_T_11998 = ~out_rimask_1247; // @[RegisterRouter.scala:87:24] wire _out_T_11999 = ~out_wimask_1247; // @[RegisterRouter.scala:87:24] wire _out_T_12000 = ~out_romask_1247; // @[RegisterRouter.scala:87:24] wire _out_T_12001 = ~out_womask_1247; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1071 = {hi_67, flags_0_go, _out_prepend_T_1071}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12002 = out_prepend_1071; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12003 = _out_T_12002; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1072 = _out_T_12003; // @[RegisterRouter.scala:87:24] wire out_rimask_1248 = \|_out_rimask_T_1248; // @[RegisterRouter.scala:87:24] wire out_wimask_1248 = &_out_wimask_T_1248; // @[RegisterRouter.scala:87:24] wire out_romask_1248 = \|_out_romask_T_1248; // @[RegisterRouter.scala:87:24] wire out_womask_1248 = &_out_womask_T_1248; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1248 = out_rivalid_1_1102 & out_rimask_1248; // @[RegisterRouter.scala:87:24] wire _out_T_12005 = out_f_rivalid_1248; // @[RegisterRouter.scala:87:24] wire out_f_roready_1248 = out_roready_1_1102 & out_romask_1248; // @[RegisterRouter.scala:87:24] wire _out_T_12006 = out_f_roready_1248; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1248 = out_wivalid_1_1102 & out_wimask_1248; // @[RegisterRouter.scala:87:24] wire out_f_woready_1248 = out_woready_1_1102 & out_womask_1248; // @[RegisterRouter.scala:87:24] wire _out_T_12007 = ~out_rimask_1248; // @[RegisterRouter.scala:87:24] wire _out_T_12008 = ~out_wimask_1248; // @[RegisterRouter.scala:87:24] wire _out_T_12009 = ~out_romask_1248; // @[RegisterRouter.scala:87:24] wire _out_T_12010 = ~out_womask_1248; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1072 = {hi_68, flags_0_go, _out_prepend_T_1072}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12011 = out_prepend_1072; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12012 = _out_T_12011; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1073 = _out_T_12012; // @[RegisterRouter.scala:87:24] wire out_rimask_1249 = \|_out_rimask_T_1249; // @[RegisterRouter.scala:87:24] wire out_wimask_1249 = &_out_wimask_T_1249; // @[RegisterRouter.scala:87:24] wire out_romask_1249 = \|_out_romask_T_1249; // @[RegisterRouter.scala:87:24] wire out_womask_1249 = &_out_womask_T_1249; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1249 = out_rivalid_1_1103 & out_rimask_1249; // @[RegisterRouter.scala:87:24] wire _out_T_12014 = out_f_rivalid_1249; // @[RegisterRouter.scala:87:24] wire out_f_roready_1249 = out_roready_1_1103 & out_romask_1249; // @[RegisterRouter.scala:87:24] wire _out_T_12015 = out_f_roready_1249; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1249 = out_wivalid_1_1103 & out_wimask_1249; // @[RegisterRouter.scala:87:24] wire out_f_woready_1249 = out_woready_1_1103 & out_womask_1249; // @[RegisterRouter.scala:87:24] wire _out_T_12016 = ~out_rimask_1249; // @[RegisterRouter.scala:87:24] wire _out_T_12017 = ~out_wimask_1249; // @[RegisterRouter.scala:87:24] wire _out_T_12018 = ~out_romask_1249; // @[RegisterRouter.scala:87:24] wire _out_T_12019 = ~out_womask_1249; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1073 = {hi_69, flags_0_go, _out_prepend_T_1073}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12020 = out_prepend_1073; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12021 = _out_T_12020; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1074 = _out_T_12021; // @[RegisterRouter.scala:87:24] wire out_rimask_1250 = \|_out_rimask_T_1250; // @[RegisterRouter.scala:87:24] wire out_wimask_1250 = &_out_wimask_T_1250; // @[RegisterRouter.scala:87:24] wire out_romask_1250 = \|_out_romask_T_1250; // @[RegisterRouter.scala:87:24] wire out_womask_1250 = &_out_womask_T_1250; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1250 = out_rivalid_1_1104 & out_rimask_1250; // @[RegisterRouter.scala:87:24] wire _out_T_12023 = out_f_rivalid_1250; // @[RegisterRouter.scala:87:24] wire out_f_roready_1250 = out_roready_1_1104 & out_romask_1250; // @[RegisterRouter.scala:87:24] wire _out_T_12024 = out_f_roready_1250; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1250 = out_wivalid_1_1104 & out_wimask_1250; // @[RegisterRouter.scala:87:24] wire out_f_woready_1250 = out_woready_1_1104 & out_womask_1250; // @[RegisterRouter.scala:87:24] wire _out_T_12025 = ~out_rimask_1250; // @[RegisterRouter.scala:87:24] wire _out_T_12026 = ~out_wimask_1250; // @[RegisterRouter.scala:87:24] wire _out_T_12027 = ~out_romask_1250; // @[RegisterRouter.scala:87:24] wire _out_T_12028 = ~out_womask_1250; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1074 = {hi_70, flags_0_go, _out_prepend_T_1074}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12029 = out_prepend_1074; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12030 = _out_T_12029; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1075 = _out_T_12030; // @[RegisterRouter.scala:87:24] wire out_rimask_1251 = \|_out_rimask_T_1251; // @[RegisterRouter.scala:87:24] wire out_wimask_1251 = &_out_wimask_T_1251; // @[RegisterRouter.scala:87:24] wire out_romask_1251 = \|_out_romask_T_1251; // @[RegisterRouter.scala:87:24] wire out_womask_1251 = &_out_womask_T_1251; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1251 = out_rivalid_1_1105 & out_rimask_1251; // @[RegisterRouter.scala:87:24] wire _out_T_12032 = out_f_rivalid_1251; // @[RegisterRouter.scala:87:24] wire out_f_roready_1251 = out_roready_1_1105 & out_romask_1251; // @[RegisterRouter.scala:87:24] wire _out_T_12033 = out_f_roready_1251; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1251 = out_wivalid_1_1105 & out_wimask_1251; // @[RegisterRouter.scala:87:24] wire out_f_woready_1251 = out_woready_1_1105 & out_womask_1251; // @[RegisterRouter.scala:87:24] wire _out_T_12034 = ~out_rimask_1251; // @[RegisterRouter.scala:87:24] wire _out_T_12035 = ~out_wimask_1251; // @[RegisterRouter.scala:87:24] wire _out_T_12036 = ~out_romask_1251; // @[RegisterRouter.scala:87:24] wire _out_T_12037 = ~out_womask_1251; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1075 = {hi_71, flags_0_go, _out_prepend_T_1075}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12038 = out_prepend_1075; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12039 = _out_T_12038; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1076 = _out_T_12039; // @[RegisterRouter.scala:87:24] wire out_rimask_1252 = \|_out_rimask_T_1252; // @[RegisterRouter.scala:87:24] wire out_wimask_1252 = &_out_wimask_T_1252; // @[RegisterRouter.scala:87:24] wire out_romask_1252 = \|_out_romask_T_1252; // @[RegisterRouter.scala:87:24] wire out_womask_1252 = &_out_womask_T_1252; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1252 = out_rivalid_1_1106 & out_rimask_1252; // @[RegisterRouter.scala:87:24] wire _out_T_12041 = out_f_rivalid_1252; // @[RegisterRouter.scala:87:24] wire out_f_roready_1252 = out_roready_1_1106 & out_romask_1252; // @[RegisterRouter.scala:87:24] wire _out_T_12042 = out_f_roready_1252; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1252 = out_wivalid_1_1106 & out_wimask_1252; // @[RegisterRouter.scala:87:24] wire out_f_woready_1252 = out_woready_1_1106 & out_womask_1252; // @[RegisterRouter.scala:87:24] wire _out_T_12043 = ~out_rimask_1252; // @[RegisterRouter.scala:87:24] wire _out_T_12044 = ~out_wimask_1252; // @[RegisterRouter.scala:87:24] wire _out_T_12045 = ~out_romask_1252; // @[RegisterRouter.scala:87:24] wire _out_T_12046 = ~out_womask_1252; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1076 = {hi_72, flags_0_go, _out_prepend_T_1076}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12047 = out_prepend_1076; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12048 = _out_T_12047; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_136 = _out_T_12048; // @[MuxLiteral.scala:49:48] wire out_rimask_1253 = \|_out_rimask_T_1253; // @[RegisterRouter.scala:87:24] wire out_wimask_1253 = &_out_wimask_T_1253; // @[RegisterRouter.scala:87:24] wire out_romask_1253 = \|_out_romask_T_1253; // @[RegisterRouter.scala:87:24] wire out_womask_1253 = &_out_womask_T_1253; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1253 = out_rivalid_1_1107 & out_rimask_1253; // @[RegisterRouter.scala:87:24] wire _out_T_12050 = out_f_rivalid_1253; // @[RegisterRouter.scala:87:24] wire out_f_roready_1253 = out_roready_1_1107 & out_romask_1253; // @[RegisterRouter.scala:87:24] wire _out_T_12051 = out_f_roready_1253; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1253 = out_wivalid_1_1107 & out_wimask_1253; // @[RegisterRouter.scala:87:24] wire out_f_woready_1253 = out_woready_1_1107 & out_womask_1253; // @[RegisterRouter.scala:87:24] wire _out_T_12052 = ~out_rimask_1253; // @[RegisterRouter.scala:87:24] wire _out_T_12053 = ~out_wimask_1253; // @[RegisterRouter.scala:87:24] wire _out_T_12054 = ~out_romask_1253; // @[RegisterRouter.scala:87:24] wire _out_T_12055 = ~out_womask_1253; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12057 = _out_T_12056; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1077 = _out_T_12057; // @[RegisterRouter.scala:87:24] wire out_rimask_1254 = \|_out_rimask_T_1254; // @[RegisterRouter.scala:87:24] wire out_wimask_1254 = &_out_wimask_T_1254; // @[RegisterRouter.scala:87:24] wire out_romask_1254 = \|_out_romask_T_1254; // @[RegisterRouter.scala:87:24] wire out_womask_1254 = &_out_womask_T_1254; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1254 = out_rivalid_1_1108 & out_rimask_1254; // @[RegisterRouter.scala:87:24] wire _out_T_12059 = out_f_rivalid_1254; // @[RegisterRouter.scala:87:24] wire out_f_roready_1254 = out_roready_1_1108 & out_romask_1254; // @[RegisterRouter.scala:87:24] wire _out_T_12060 = out_f_roready_1254; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1254 = out_wivalid_1_1108 & out_wimask_1254; // @[RegisterRouter.scala:87:24] wire out_f_woready_1254 = out_woready_1_1108 & out_womask_1254; // @[RegisterRouter.scala:87:24] wire _out_T_12061 = ~out_rimask_1254; // @[RegisterRouter.scala:87:24] wire _out_T_12062 = ~out_wimask_1254; // @[RegisterRouter.scala:87:24] wire _out_T_12063 = ~out_romask_1254; // @[RegisterRouter.scala:87:24] wire _out_T_12064 = ~out_womask_1254; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1077 = {hi_538, flags_0_go, _out_prepend_T_1077}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12065 = out_prepend_1077; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12066 = _out_T_12065; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1078 = _out_T_12066; // @[RegisterRouter.scala:87:24] wire out_rimask_1255 = \|_out_rimask_T_1255; // @[RegisterRouter.scala:87:24] wire out_wimask_1255 = &_out_wimask_T_1255; // @[RegisterRouter.scala:87:24] wire out_romask_1255 = \|_out_romask_T_1255; // @[RegisterRouter.scala:87:24] wire out_womask_1255 = &_out_womask_T_1255; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1255 = out_rivalid_1_1109 & out_rimask_1255; // @[RegisterRouter.scala:87:24] wire _out_T_12068 = out_f_rivalid_1255; // @[RegisterRouter.scala:87:24] wire out_f_roready_1255 = out_roready_1_1109 & out_romask_1255; // @[RegisterRouter.scala:87:24] wire _out_T_12069 = out_f_roready_1255; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1255 = out_wivalid_1_1109 & out_wimask_1255; // @[RegisterRouter.scala:87:24] wire out_f_woready_1255 = out_woready_1_1109 & out_womask_1255; // @[RegisterRouter.scala:87:24] wire _out_T_12070 = ~out_rimask_1255; // @[RegisterRouter.scala:87:24] wire _out_T_12071 = ~out_wimask_1255; // @[RegisterRouter.scala:87:24] wire _out_T_12072 = ~out_romask_1255; // @[RegisterRouter.scala:87:24] wire _out_T_12073 = ~out_womask_1255; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1078 = {hi_539, flags_0_go, _out_prepend_T_1078}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12074 = out_prepend_1078; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12075 = _out_T_12074; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1079 = _out_T_12075; // @[RegisterRouter.scala:87:24] wire out_rimask_1256 = \|_out_rimask_T_1256; // @[RegisterRouter.scala:87:24] wire out_wimask_1256 = &_out_wimask_T_1256; // @[RegisterRouter.scala:87:24] wire out_romask_1256 = \|_out_romask_T_1256; // @[RegisterRouter.scala:87:24] wire out_womask_1256 = &_out_womask_T_1256; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1256 = out_rivalid_1_1110 & out_rimask_1256; // @[RegisterRouter.scala:87:24] wire _out_T_12077 = out_f_rivalid_1256; // @[RegisterRouter.scala:87:24] wire out_f_roready_1256 = out_roready_1_1110 & out_romask_1256; // @[RegisterRouter.scala:87:24] wire _out_T_12078 = out_f_roready_1256; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1256 = out_wivalid_1_1110 & out_wimask_1256; // @[RegisterRouter.scala:87:24] wire out_f_woready_1256 = out_woready_1_1110 & out_womask_1256; // @[RegisterRouter.scala:87:24] wire _out_T_12079 = ~out_rimask_1256; // @[RegisterRouter.scala:87:24] wire _out_T_12080 = ~out_wimask_1256; // @[RegisterRouter.scala:87:24] wire _out_T_12081 = ~out_romask_1256; // @[RegisterRouter.scala:87:24] wire _out_T_12082 = ~out_womask_1256; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1079 = {hi_540, flags_0_go, _out_prepend_T_1079}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12083 = out_prepend_1079; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12084 = _out_T_12083; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1080 = _out_T_12084; // @[RegisterRouter.scala:87:24] wire out_rimask_1257 = \|_out_rimask_T_1257; // @[RegisterRouter.scala:87:24] wire out_wimask_1257 = &_out_wimask_T_1257; // @[RegisterRouter.scala:87:24] wire out_romask_1257 = \|_out_romask_T_1257; // @[RegisterRouter.scala:87:24] wire out_womask_1257 = &_out_womask_T_1257; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1257 = out_rivalid_1_1111 & out_rimask_1257; // @[RegisterRouter.scala:87:24] wire _out_T_12086 = out_f_rivalid_1257; // @[RegisterRouter.scala:87:24] wire out_f_roready_1257 = out_roready_1_1111 & out_romask_1257; // @[RegisterRouter.scala:87:24] wire _out_T_12087 = out_f_roready_1257; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1257 = out_wivalid_1_1111 & out_wimask_1257; // @[RegisterRouter.scala:87:24] wire out_f_woready_1257 = out_woready_1_1111 & out_womask_1257; // @[RegisterRouter.scala:87:24] wire _out_T_12088 = ~out_rimask_1257; // @[RegisterRouter.scala:87:24] wire _out_T_12089 = ~out_wimask_1257; // @[RegisterRouter.scala:87:24] wire _out_T_12090 = ~out_romask_1257; // @[RegisterRouter.scala:87:24] wire _out_T_12091 = ~out_womask_1257; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1080 = {hi_541, flags_0_go, _out_prepend_T_1080}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12092 = out_prepend_1080; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12093 = _out_T_12092; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1081 = _out_T_12093; // @[RegisterRouter.scala:87:24] wire out_rimask_1258 = \|_out_rimask_T_1258; // @[RegisterRouter.scala:87:24] wire out_wimask_1258 = &_out_wimask_T_1258; // @[RegisterRouter.scala:87:24] wire out_romask_1258 = \|_out_romask_T_1258; // @[RegisterRouter.scala:87:24] wire out_womask_1258 = &_out_womask_T_1258; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1258 = out_rivalid_1_1112 & out_rimask_1258; // @[RegisterRouter.scala:87:24] wire _out_T_12095 = out_f_rivalid_1258; // @[RegisterRouter.scala:87:24] wire out_f_roready_1258 = out_roready_1_1112 & out_romask_1258; // @[RegisterRouter.scala:87:24] wire _out_T_12096 = out_f_roready_1258; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1258 = out_wivalid_1_1112 & out_wimask_1258; // @[RegisterRouter.scala:87:24] wire out_f_woready_1258 = out_woready_1_1112 & out_womask_1258; // @[RegisterRouter.scala:87:24] wire _out_T_12097 = ~out_rimask_1258; // @[RegisterRouter.scala:87:24] wire _out_T_12098 = ~out_wimask_1258; // @[RegisterRouter.scala:87:24] wire _out_T_12099 = ~out_romask_1258; // @[RegisterRouter.scala:87:24] wire _out_T_12100 = ~out_womask_1258; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1081 = {hi_542, flags_0_go, _out_prepend_T_1081}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12101 = out_prepend_1081; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12102 = _out_T_12101; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1082 = _out_T_12102; // @[RegisterRouter.scala:87:24] wire out_rimask_1259 = \|_out_rimask_T_1259; // @[RegisterRouter.scala:87:24] wire out_wimask_1259 = &_out_wimask_T_1259; // @[RegisterRouter.scala:87:24] wire out_romask_1259 = \|_out_romask_T_1259; // @[RegisterRouter.scala:87:24] wire out_womask_1259 = &_out_womask_T_1259; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1259 = out_rivalid_1_1113 & out_rimask_1259; // @[RegisterRouter.scala:87:24] wire _out_T_12104 = out_f_rivalid_1259; // @[RegisterRouter.scala:87:24] wire out_f_roready_1259 = out_roready_1_1113 & out_romask_1259; // @[RegisterRouter.scala:87:24] wire _out_T_12105 = out_f_roready_1259; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1259 = out_wivalid_1_1113 & out_wimask_1259; // @[RegisterRouter.scala:87:24] wire out_f_woready_1259 = out_woready_1_1113 & out_womask_1259; // @[RegisterRouter.scala:87:24] wire _out_T_12106 = ~out_rimask_1259; // @[RegisterRouter.scala:87:24] wire _out_T_12107 = ~out_wimask_1259; // @[RegisterRouter.scala:87:24] wire _out_T_12108 = ~out_romask_1259; // @[RegisterRouter.scala:87:24] wire _out_T_12109 = ~out_womask_1259; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1082 = {hi_543, flags_0_go, _out_prepend_T_1082}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12110 = out_prepend_1082; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12111 = _out_T_12110; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1083 = _out_T_12111; // @[RegisterRouter.scala:87:24] wire out_rimask_1260 = \|_out_rimask_T_1260; // @[RegisterRouter.scala:87:24] wire out_wimask_1260 = &_out_wimask_T_1260; // @[RegisterRouter.scala:87:24] wire out_romask_1260 = \|_out_romask_T_1260; // @[RegisterRouter.scala:87:24] wire out_womask_1260 = &_out_womask_T_1260; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1260 = out_rivalid_1_1114 & out_rimask_1260; // @[RegisterRouter.scala:87:24] wire _out_T_12113 = out_f_rivalid_1260; // @[RegisterRouter.scala:87:24] wire out_f_roready_1260 = out_roready_1_1114 & out_romask_1260; // @[RegisterRouter.scala:87:24] wire _out_T_12114 = out_f_roready_1260; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1260 = out_wivalid_1_1114 & out_wimask_1260; // @[RegisterRouter.scala:87:24] wire out_f_woready_1260 = out_woready_1_1114 & out_womask_1260; // @[RegisterRouter.scala:87:24] wire _out_T_12115 = ~out_rimask_1260; // @[RegisterRouter.scala:87:24] wire _out_T_12116 = ~out_wimask_1260; // @[RegisterRouter.scala:87:24] wire _out_T_12117 = ~out_romask_1260; // @[RegisterRouter.scala:87:24] wire _out_T_12118 = ~out_womask_1260; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1083 = {hi_544, flags_0_go, _out_prepend_T_1083}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12119 = out_prepend_1083; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12120 = _out_T_12119; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_195 = _out_T_12120; // @[MuxLiteral.scala:49:48] wire out_rimask_1261 = \|_out_rimask_T_1261; // @[RegisterRouter.scala:87:24] wire out_wimask_1261 = &_out_wimask_T_1261; // @[RegisterRouter.scala:87:24] wire out_romask_1261 = \|_out_romask_T_1261; // @[RegisterRouter.scala:87:24] wire out_womask_1261 = &_out_womask_T_1261; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1261 = out_rivalid_1_1115 & out_rimask_1261; // @[RegisterRouter.scala:87:24] wire _out_T_12122 = out_f_rivalid_1261; // @[RegisterRouter.scala:87:24] wire out_f_roready_1261 = out_roready_1_1115 & out_romask_1261; // @[RegisterRouter.scala:87:24] wire _out_T_12123 = out_f_roready_1261; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1261 = out_wivalid_1_1115 & out_wimask_1261; // @[RegisterRouter.scala:87:24] wire out_f_woready_1261 = out_woready_1_1115 & out_womask_1261; // @[RegisterRouter.scala:87:24] wire _out_T_12124 = ~out_rimask_1261; // @[RegisterRouter.scala:87:24] wire _out_T_12125 = ~out_wimask_1261; // @[RegisterRouter.scala:87:24] wire _out_T_12126 = ~out_romask_1261; // @[RegisterRouter.scala:87:24] wire _out_T_12127 = ~out_womask_1261; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12129 = _out_T_12128; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1084 = _out_T_12129; // @[RegisterRouter.scala:87:24] wire out_rimask_1262 = \|_out_rimask_T_1262; // @[RegisterRouter.scala:87:24] wire out_wimask_1262 = &_out_wimask_T_1262; // @[RegisterRouter.scala:87:24] wire out_romask_1262 = \|_out_romask_T_1262; // @[RegisterRouter.scala:87:24] wire out_womask_1262 = &_out_womask_T_1262; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1262 = out_rivalid_1_1116 & out_rimask_1262; // @[RegisterRouter.scala:87:24] wire _out_T_12131 = out_f_rivalid_1262; // @[RegisterRouter.scala:87:24] wire out_f_roready_1262 = out_roready_1_1116 & out_romask_1262; // @[RegisterRouter.scala:87:24] wire _out_T_12132 = out_f_roready_1262; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1262 = out_wivalid_1_1116 & out_wimask_1262; // @[RegisterRouter.scala:87:24] wire out_f_woready_1262 = out_woready_1_1116 & out_womask_1262; // @[RegisterRouter.scala:87:24] wire _out_T_12133 = ~out_rimask_1262; // @[RegisterRouter.scala:87:24] wire _out_T_12134 = ~out_wimask_1262; // @[RegisterRouter.scala:87:24] wire _out_T_12135 = ~out_romask_1262; // @[RegisterRouter.scala:87:24] wire _out_T_12136 = ~out_womask_1262; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1084 = {hi_890, flags_0_go, _out_prepend_T_1084}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12137 = out_prepend_1084; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12138 = _out_T_12137; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1085 = _out_T_12138; // @[RegisterRouter.scala:87:24] wire out_rimask_1263 = \|_out_rimask_T_1263; // @[RegisterRouter.scala:87:24] wire out_wimask_1263 = &_out_wimask_T_1263; // @[RegisterRouter.scala:87:24] wire out_romask_1263 = \|_out_romask_T_1263; // @[RegisterRouter.scala:87:24] wire out_womask_1263 = &_out_womask_T_1263; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1263 = out_rivalid_1_1117 & out_rimask_1263; // @[RegisterRouter.scala:87:24] wire _out_T_12140 = out_f_rivalid_1263; // @[RegisterRouter.scala:87:24] wire out_f_roready_1263 = out_roready_1_1117 & out_romask_1263; // @[RegisterRouter.scala:87:24] wire _out_T_12141 = out_f_roready_1263; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1263 = out_wivalid_1_1117 & out_wimask_1263; // @[RegisterRouter.scala:87:24] wire out_f_woready_1263 = out_woready_1_1117 & out_womask_1263; // @[RegisterRouter.scala:87:24] wire _out_T_12142 = ~out_rimask_1263; // @[RegisterRouter.scala:87:24] wire _out_T_12143 = ~out_wimask_1263; // @[RegisterRouter.scala:87:24] wire _out_T_12144 = ~out_romask_1263; // @[RegisterRouter.scala:87:24] wire _out_T_12145 = ~out_womask_1263; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1085 = {hi_891, flags_0_go, _out_prepend_T_1085}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12146 = out_prepend_1085; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12147 = _out_T_12146; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1086 = _out_T_12147; // @[RegisterRouter.scala:87:24] wire out_rimask_1264 = \|_out_rimask_T_1264; // @[RegisterRouter.scala:87:24] wire out_wimask_1264 = &_out_wimask_T_1264; // @[RegisterRouter.scala:87:24] wire out_romask_1264 = \|_out_romask_T_1264; // @[RegisterRouter.scala:87:24] wire out_womask_1264 = &_out_womask_T_1264; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1264 = out_rivalid_1_1118 & out_rimask_1264; // @[RegisterRouter.scala:87:24] wire _out_T_12149 = out_f_rivalid_1264; // @[RegisterRouter.scala:87:24] wire out_f_roready_1264 = out_roready_1_1118 & out_romask_1264; // @[RegisterRouter.scala:87:24] wire _out_T_12150 = out_f_roready_1264; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1264 = out_wivalid_1_1118 & out_wimask_1264; // @[RegisterRouter.scala:87:24] wire out_f_woready_1264 = out_woready_1_1118 & out_womask_1264; // @[RegisterRouter.scala:87:24] wire _out_T_12151 = ~out_rimask_1264; // @[RegisterRouter.scala:87:24] wire _out_T_12152 = ~out_wimask_1264; // @[RegisterRouter.scala:87:24] wire _out_T_12153 = ~out_romask_1264; // @[RegisterRouter.scala:87:24] wire _out_T_12154 = ~out_womask_1264; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1086 = {hi_892, flags_0_go, _out_prepend_T_1086}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12155 = out_prepend_1086; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12156 = _out_T_12155; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1087 = _out_T_12156; // @[RegisterRouter.scala:87:24] wire out_rimask_1265 = \|_out_rimask_T_1265; // @[RegisterRouter.scala:87:24] wire out_wimask_1265 = &_out_wimask_T_1265; // @[RegisterRouter.scala:87:24] wire out_romask_1265 = \|_out_romask_T_1265; // @[RegisterRouter.scala:87:24] wire out_womask_1265 = &_out_womask_T_1265; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1265 = out_rivalid_1_1119 & out_rimask_1265; // @[RegisterRouter.scala:87:24] wire _out_T_12158 = out_f_rivalid_1265; // @[RegisterRouter.scala:87:24] wire out_f_roready_1265 = out_roready_1_1119 & out_romask_1265; // @[RegisterRouter.scala:87:24] wire _out_T_12159 = out_f_roready_1265; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1265 = out_wivalid_1_1119 & out_wimask_1265; // @[RegisterRouter.scala:87:24] wire out_f_woready_1265 = out_woready_1_1119 & out_womask_1265; // @[RegisterRouter.scala:87:24] wire _out_T_12160 = ~out_rimask_1265; // @[RegisterRouter.scala:87:24] wire _out_T_12161 = ~out_wimask_1265; // @[RegisterRouter.scala:87:24] wire _out_T_12162 = ~out_romask_1265; // @[RegisterRouter.scala:87:24] wire _out_T_12163 = ~out_womask_1265; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1087 = {hi_893, flags_0_go, _out_prepend_T_1087}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12164 = out_prepend_1087; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12165 = _out_T_12164; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1088 = _out_T_12165; // @[RegisterRouter.scala:87:24] wire out_rimask_1266 = \|_out_rimask_T_1266; // @[RegisterRouter.scala:87:24] wire out_wimask_1266 = &_out_wimask_T_1266; // @[RegisterRouter.scala:87:24] wire out_romask_1266 = \|_out_romask_T_1266; // @[RegisterRouter.scala:87:24] wire out_womask_1266 = &_out_womask_T_1266; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1266 = out_rivalid_1_1120 & out_rimask_1266; // @[RegisterRouter.scala:87:24] wire _out_T_12167 = out_f_rivalid_1266; // @[RegisterRouter.scala:87:24] wire out_f_roready_1266 = out_roready_1_1120 & out_romask_1266; // @[RegisterRouter.scala:87:24] wire _out_T_12168 = out_f_roready_1266; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1266 = out_wivalid_1_1120 & out_wimask_1266; // @[RegisterRouter.scala:87:24] wire out_f_woready_1266 = out_woready_1_1120 & out_womask_1266; // @[RegisterRouter.scala:87:24] wire _out_T_12169 = ~out_rimask_1266; // @[RegisterRouter.scala:87:24] wire _out_T_12170 = ~out_wimask_1266; // @[RegisterRouter.scala:87:24] wire _out_T_12171 = ~out_romask_1266; // @[RegisterRouter.scala:87:24] wire _out_T_12172 = ~out_womask_1266; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1088 = {hi_894, flags_0_go, _out_prepend_T_1088}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12173 = out_prepend_1088; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12174 = _out_T_12173; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1089 = _out_T_12174; // @[RegisterRouter.scala:87:24] wire out_rimask_1267 = \|_out_rimask_T_1267; // @[RegisterRouter.scala:87:24] wire out_wimask_1267 = &_out_wimask_T_1267; // @[RegisterRouter.scala:87:24] wire out_romask_1267 = \|_out_romask_T_1267; // @[RegisterRouter.scala:87:24] wire out_womask_1267 = &_out_womask_T_1267; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1267 = out_rivalid_1_1121 & out_rimask_1267; // @[RegisterRouter.scala:87:24] wire _out_T_12176 = out_f_rivalid_1267; // @[RegisterRouter.scala:87:24] wire out_f_roready_1267 = out_roready_1_1121 & out_romask_1267; // @[RegisterRouter.scala:87:24] wire _out_T_12177 = out_f_roready_1267; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1267 = out_wivalid_1_1121 & out_wimask_1267; // @[RegisterRouter.scala:87:24] wire out_f_woready_1267 = out_woready_1_1121 & out_womask_1267; // @[RegisterRouter.scala:87:24] wire _out_T_12178 = ~out_rimask_1267; // @[RegisterRouter.scala:87:24] wire _out_T_12179 = ~out_wimask_1267; // @[RegisterRouter.scala:87:24] wire _out_T_12180 = ~out_romask_1267; // @[RegisterRouter.scala:87:24] wire _out_T_12181 = ~out_womask_1267; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1089 = {hi_895, flags_0_go, _out_prepend_T_1089}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12182 = out_prepend_1089; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12183 = _out_T_12182; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1090 = _out_T_12183; // @[RegisterRouter.scala:87:24] wire out_rimask_1268 = \|_out_rimask_T_1268; // @[RegisterRouter.scala:87:24] wire out_wimask_1268 = &_out_wimask_T_1268; // @[RegisterRouter.scala:87:24] wire out_romask_1268 = \|_out_romask_T_1268; // @[RegisterRouter.scala:87:24] wire out_womask_1268 = &_out_womask_T_1268; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1268 = out_rivalid_1_1122 & out_rimask_1268; // @[RegisterRouter.scala:87:24] wire _out_T_12185 = out_f_rivalid_1268; // @[RegisterRouter.scala:87:24] wire out_f_roready_1268 = out_roready_1_1122 & out_romask_1268; // @[RegisterRouter.scala:87:24] wire _out_T_12186 = out_f_roready_1268; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1268 = out_wivalid_1_1122 & out_wimask_1268; // @[RegisterRouter.scala:87:24] wire out_f_woready_1268 = out_woready_1_1122 & out_womask_1268; // @[RegisterRouter.scala:87:24] wire _out_T_12187 = ~out_rimask_1268; // @[RegisterRouter.scala:87:24] wire _out_T_12188 = ~out_wimask_1268; // @[RegisterRouter.scala:87:24] wire _out_T_12189 = ~out_romask_1268; // @[RegisterRouter.scala:87:24] wire _out_T_12190 = ~out_womask_1268; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1090 = {hi_896, flags_0_go, _out_prepend_T_1090}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12191 = out_prepend_1090; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12192 = _out_T_12191; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_239 = _out_T_12192; // @[MuxLiteral.scala:49:48] wire out_rimask_1269 = \|_out_rimask_T_1269; // @[RegisterRouter.scala:87:24] wire out_wimask_1269 = &_out_wimask_T_1269; // @[RegisterRouter.scala:87:24] wire out_romask_1269 = \|_out_romask_T_1269; // @[RegisterRouter.scala:87:24] wire out_womask_1269 = &_out_womask_T_1269; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1269 = out_rivalid_1_1123 & out_rimask_1269; // @[RegisterRouter.scala:87:24] wire _out_T_12194 = out_f_rivalid_1269; // @[RegisterRouter.scala:87:24] wire out_f_roready_1269 = out_roready_1_1123 & out_romask_1269; // @[RegisterRouter.scala:87:24] wire _out_T_12195 = out_f_roready_1269; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1269 = out_wivalid_1_1123 & out_wimask_1269; // @[RegisterRouter.scala:87:24] wire out_f_woready_1269 = out_woready_1_1123 & out_womask_1269; // @[RegisterRouter.scala:87:24] wire _out_T_12196 = ~out_rimask_1269; // @[RegisterRouter.scala:87:24] wire _out_T_12197 = ~out_wimask_1269; // @[RegisterRouter.scala:87:24] wire _out_T_12198 = ~out_romask_1269; // @[RegisterRouter.scala:87:24] wire _out_T_12199 = ~out_womask_1269; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12201 = _out_T_12200; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1091 = _out_T_12201; // @[RegisterRouter.scala:87:24] wire out_rimask_1270 = \|_out_rimask_T_1270; // @[RegisterRouter.scala:87:24] wire out_wimask_1270 = &_out_wimask_T_1270; // @[RegisterRouter.scala:87:24] wire out_romask_1270 = \|_out_romask_T_1270; // @[RegisterRouter.scala:87:24] wire out_womask_1270 = &_out_womask_T_1270; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1270 = out_rivalid_1_1124 & out_rimask_1270; // @[RegisterRouter.scala:87:24] wire _out_T_12203 = out_f_rivalid_1270; // @[RegisterRouter.scala:87:24] wire out_f_roready_1270 = out_roready_1_1124 & out_romask_1270; // @[RegisterRouter.scala:87:24] wire _out_T_12204 = out_f_roready_1270; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1270 = out_wivalid_1_1124 & out_wimask_1270; // @[RegisterRouter.scala:87:24] wire out_f_woready_1270 = out_woready_1_1124 & out_womask_1270; // @[RegisterRouter.scala:87:24] wire _out_T_12205 = ~out_rimask_1270; // @[RegisterRouter.scala:87:24] wire _out_T_12206 = ~out_wimask_1270; // @[RegisterRouter.scala:87:24] wire _out_T_12207 = ~out_romask_1270; // @[RegisterRouter.scala:87:24] wire _out_T_12208 = ~out_womask_1270; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1091 = {hi_914, flags_0_go, _out_prepend_T_1091}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12209 = out_prepend_1091; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12210 = _out_T_12209; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1092 = _out_T_12210; // @[RegisterRouter.scala:87:24] wire out_rimask_1271 = \|_out_rimask_T_1271; // @[RegisterRouter.scala:87:24] wire out_wimask_1271 = &_out_wimask_T_1271; // @[RegisterRouter.scala:87:24] wire out_romask_1271 = \|_out_romask_T_1271; // @[RegisterRouter.scala:87:24] wire out_womask_1271 = &_out_womask_T_1271; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1271 = out_rivalid_1_1125 & out_rimask_1271; // @[RegisterRouter.scala:87:24] wire _out_T_12212 = out_f_rivalid_1271; // @[RegisterRouter.scala:87:24] wire out_f_roready_1271 = out_roready_1_1125 & out_romask_1271; // @[RegisterRouter.scala:87:24] wire _out_T_12213 = out_f_roready_1271; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1271 = out_wivalid_1_1125 & out_wimask_1271; // @[RegisterRouter.scala:87:24] wire out_f_woready_1271 = out_woready_1_1125 & out_womask_1271; // @[RegisterRouter.scala:87:24] wire _out_T_12214 = ~out_rimask_1271; // @[RegisterRouter.scala:87:24] wire _out_T_12215 = ~out_wimask_1271; // @[RegisterRouter.scala:87:24] wire _out_T_12216 = ~out_romask_1271; // @[RegisterRouter.scala:87:24] wire _out_T_12217 = ~out_womask_1271; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1092 = {hi_915, flags_0_go, _out_prepend_T_1092}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12218 = out_prepend_1092; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12219 = _out_T_12218; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1093 = _out_T_12219; // @[RegisterRouter.scala:87:24] wire out_rimask_1272 = \|_out_rimask_T_1272; // @[RegisterRouter.scala:87:24] wire out_wimask_1272 = &_out_wimask_T_1272; // @[RegisterRouter.scala:87:24] wire out_romask_1272 = \|_out_romask_T_1272; // @[RegisterRouter.scala:87:24] wire out_womask_1272 = &_out_womask_T_1272; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1272 = out_rivalid_1_1126 & out_rimask_1272; // @[RegisterRouter.scala:87:24] wire _out_T_12221 = out_f_rivalid_1272; // @[RegisterRouter.scala:87:24] wire out_f_roready_1272 = out_roready_1_1126 & out_romask_1272; // @[RegisterRouter.scala:87:24] wire _out_T_12222 = out_f_roready_1272; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1272 = out_wivalid_1_1126 & out_wimask_1272; // @[RegisterRouter.scala:87:24] wire out_f_woready_1272 = out_woready_1_1126 & out_womask_1272; // @[RegisterRouter.scala:87:24] wire _out_T_12223 = ~out_rimask_1272; // @[RegisterRouter.scala:87:24] wire _out_T_12224 = ~out_wimask_1272; // @[RegisterRouter.scala:87:24] wire _out_T_12225 = ~out_romask_1272; // @[RegisterRouter.scala:87:24] wire _out_T_12226 = ~out_womask_1272; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1093 = {hi_916, flags_0_go, _out_prepend_T_1093}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12227 = out_prepend_1093; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12228 = _out_T_12227; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1094 = _out_T_12228; // @[RegisterRouter.scala:87:24] wire out_rimask_1273 = \|_out_rimask_T_1273; // @[RegisterRouter.scala:87:24] wire out_wimask_1273 = &_out_wimask_T_1273; // @[RegisterRouter.scala:87:24] wire out_romask_1273 = \|_out_romask_T_1273; // @[RegisterRouter.scala:87:24] wire out_womask_1273 = &_out_womask_T_1273; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1273 = out_rivalid_1_1127 & out_rimask_1273; // @[RegisterRouter.scala:87:24] wire _out_T_12230 = out_f_rivalid_1273; // @[RegisterRouter.scala:87:24] wire out_f_roready_1273 = out_roready_1_1127 & out_romask_1273; // @[RegisterRouter.scala:87:24] wire _out_T_12231 = out_f_roready_1273; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1273 = out_wivalid_1_1127 & out_wimask_1273; // @[RegisterRouter.scala:87:24] wire out_f_woready_1273 = out_woready_1_1127 & out_womask_1273; // @[RegisterRouter.scala:87:24] wire _out_T_12232 = ~out_rimask_1273; // @[RegisterRouter.scala:87:24] wire _out_T_12233 = ~out_wimask_1273; // @[RegisterRouter.scala:87:24] wire _out_T_12234 = ~out_romask_1273; // @[RegisterRouter.scala:87:24] wire _out_T_12235 = ~out_womask_1273; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1094 = {hi_917, flags_0_go, _out_prepend_T_1094}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12236 = out_prepend_1094; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12237 = _out_T_12236; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1095 = _out_T_12237; // @[RegisterRouter.scala:87:24] wire out_rimask_1274 = \|_out_rimask_T_1274; // @[RegisterRouter.scala:87:24] wire out_wimask_1274 = &_out_wimask_T_1274; // @[RegisterRouter.scala:87:24] wire out_romask_1274 = \|_out_romask_T_1274; // @[RegisterRouter.scala:87:24] wire out_womask_1274 = &_out_womask_T_1274; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1274 = out_rivalid_1_1128 & out_rimask_1274; // @[RegisterRouter.scala:87:24] wire _out_T_12239 = out_f_rivalid_1274; // @[RegisterRouter.scala:87:24] wire out_f_roready_1274 = out_roready_1_1128 & out_romask_1274; // @[RegisterRouter.scala:87:24] wire _out_T_12240 = out_f_roready_1274; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1274 = out_wivalid_1_1128 & out_wimask_1274; // @[RegisterRouter.scala:87:24] wire out_f_woready_1274 = out_woready_1_1128 & out_womask_1274; // @[RegisterRouter.scala:87:24] wire _out_T_12241 = ~out_rimask_1274; // @[RegisterRouter.scala:87:24] wire _out_T_12242 = ~out_wimask_1274; // @[RegisterRouter.scala:87:24] wire _out_T_12243 = ~out_romask_1274; // @[RegisterRouter.scala:87:24] wire _out_T_12244 = ~out_womask_1274; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1095 = {hi_918, flags_0_go, _out_prepend_T_1095}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12245 = out_prepend_1095; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12246 = _out_T_12245; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1096 = _out_T_12246; // @[RegisterRouter.scala:87:24] wire out_rimask_1275 = \|_out_rimask_T_1275; // @[RegisterRouter.scala:87:24] wire out_wimask_1275 = &_out_wimask_T_1275; // @[RegisterRouter.scala:87:24] wire out_romask_1275 = \|_out_romask_T_1275; // @[RegisterRouter.scala:87:24] wire out_womask_1275 = &_out_womask_T_1275; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1275 = out_rivalid_1_1129 & out_rimask_1275; // @[RegisterRouter.scala:87:24] wire _out_T_12248 = out_f_rivalid_1275; // @[RegisterRouter.scala:87:24] wire out_f_roready_1275 = out_roready_1_1129 & out_romask_1275; // @[RegisterRouter.scala:87:24] wire _out_T_12249 = out_f_roready_1275; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1275 = out_wivalid_1_1129 & out_wimask_1275; // @[RegisterRouter.scala:87:24] wire out_f_woready_1275 = out_woready_1_1129 & out_womask_1275; // @[RegisterRouter.scala:87:24] wire _out_T_12250 = ~out_rimask_1275; // @[RegisterRouter.scala:87:24] wire _out_T_12251 = ~out_wimask_1275; // @[RegisterRouter.scala:87:24] wire _out_T_12252 = ~out_romask_1275; // @[RegisterRouter.scala:87:24] wire _out_T_12253 = ~out_womask_1275; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1096 = {hi_919, flags_0_go, _out_prepend_T_1096}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12254 = out_prepend_1096; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12255 = _out_T_12254; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1097 = _out_T_12255; // @[RegisterRouter.scala:87:24] wire out_rimask_1276 = \|_out_rimask_T_1276; // @[RegisterRouter.scala:87:24] wire out_wimask_1276 = &_out_wimask_T_1276; // @[RegisterRouter.scala:87:24] wire out_romask_1276 = \|_out_romask_T_1276; // @[RegisterRouter.scala:87:24] wire out_womask_1276 = &_out_womask_T_1276; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1276 = out_rivalid_1_1130 & out_rimask_1276; // @[RegisterRouter.scala:87:24] wire _out_T_12257 = out_f_rivalid_1276; // @[RegisterRouter.scala:87:24] wire out_f_roready_1276 = out_roready_1_1130 & out_romask_1276; // @[RegisterRouter.scala:87:24] wire _out_T_12258 = out_f_roready_1276; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1276 = out_wivalid_1_1130 & out_wimask_1276; // @[RegisterRouter.scala:87:24] wire out_f_woready_1276 = out_woready_1_1130 & out_womask_1276; // @[RegisterRouter.scala:87:24] wire _out_T_12259 = ~out_rimask_1276; // @[RegisterRouter.scala:87:24] wire _out_T_12260 = ~out_wimask_1276; // @[RegisterRouter.scala:87:24] wire _out_T_12261 = ~out_romask_1276; // @[RegisterRouter.scala:87:24] wire _out_T_12262 = ~out_womask_1276; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1097 = {hi_920, flags_0_go, _out_prepend_T_1097}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12263 = out_prepend_1097; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12264 = _out_T_12263; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_242 = _out_T_12264; // @[MuxLiteral.scala:49:48] wire out_rimask_1277 = \|_out_rimask_T_1277; // @[RegisterRouter.scala:87:24] wire out_wimask_1277 = &_out_wimask_T_1277; // @[RegisterRouter.scala:87:24] wire out_romask_1277 = \|_out_romask_T_1277; // @[RegisterRouter.scala:87:24] wire out_womask_1277 = &_out_womask_T_1277; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1277 = out_rivalid_1_1131 & out_rimask_1277; // @[RegisterRouter.scala:87:24] wire _out_T_12266 = out_f_rivalid_1277; // @[RegisterRouter.scala:87:24] wire out_f_roready_1277 = out_roready_1_1131 & out_romask_1277; // @[RegisterRouter.scala:87:24] wire _out_T_12267 = out_f_roready_1277; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1277 = out_wivalid_1_1131 & out_wimask_1277; // @[RegisterRouter.scala:87:24] wire out_f_woready_1277 = out_woready_1_1131 & out_womask_1277; // @[RegisterRouter.scala:87:24] wire _out_T_12268 = ~out_rimask_1277; // @[RegisterRouter.scala:87:24] wire _out_T_12269 = ~out_wimask_1277; // @[RegisterRouter.scala:87:24] wire _out_T_12270 = ~out_romask_1277; // @[RegisterRouter.scala:87:24] wire _out_T_12271 = ~out_womask_1277; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12273 = _out_T_12272; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1098 = _out_T_12273; // @[RegisterRouter.scala:87:24] wire out_rimask_1278 = \|_out_rimask_T_1278; // @[RegisterRouter.scala:87:24] wire out_wimask_1278 = &_out_wimask_T_1278; // @[RegisterRouter.scala:87:24] wire out_romask_1278 = \|_out_romask_T_1278; // @[RegisterRouter.scala:87:24] wire out_womask_1278 = &_out_womask_T_1278; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1278 = out_rivalid_1_1132 & out_rimask_1278; // @[RegisterRouter.scala:87:24] wire _out_T_12275 = out_f_rivalid_1278; // @[RegisterRouter.scala:87:24] wire out_f_roready_1278 = out_roready_1_1132 & out_romask_1278; // @[RegisterRouter.scala:87:24] wire _out_T_12276 = out_f_roready_1278; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1278 = out_wivalid_1_1132 & out_wimask_1278; // @[RegisterRouter.scala:87:24] wire out_f_woready_1278 = out_woready_1_1132 & out_womask_1278; // @[RegisterRouter.scala:87:24] wire _out_T_12277 = ~out_rimask_1278; // @[RegisterRouter.scala:87:24] wire _out_T_12278 = ~out_wimask_1278; // @[RegisterRouter.scala:87:24] wire _out_T_12279 = ~out_romask_1278; // @[RegisterRouter.scala:87:24] wire _out_T_12280 = ~out_womask_1278; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1098 = {hi_26, flags_0_go, _out_prepend_T_1098}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12281 = out_prepend_1098; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12282 = _out_T_12281; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1099 = _out_T_12282; // @[RegisterRouter.scala:87:24] wire out_rimask_1279 = \|_out_rimask_T_1279; // @[RegisterRouter.scala:87:24] wire out_wimask_1279 = &_out_wimask_T_1279; // @[RegisterRouter.scala:87:24] wire out_romask_1279 = \|_out_romask_T_1279; // @[RegisterRouter.scala:87:24] wire out_womask_1279 = &_out_womask_T_1279; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1279 = out_rivalid_1_1133 & out_rimask_1279; // @[RegisterRouter.scala:87:24] wire _out_T_12284 = out_f_rivalid_1279; // @[RegisterRouter.scala:87:24] wire out_f_roready_1279 = out_roready_1_1133 & out_romask_1279; // @[RegisterRouter.scala:87:24] wire _out_T_12285 = out_f_roready_1279; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1279 = out_wivalid_1_1133 & out_wimask_1279; // @[RegisterRouter.scala:87:24] wire out_f_woready_1279 = out_woready_1_1133 & out_womask_1279; // @[RegisterRouter.scala:87:24] wire _out_T_12286 = ~out_rimask_1279; // @[RegisterRouter.scala:87:24] wire _out_T_12287 = ~out_wimask_1279; // @[RegisterRouter.scala:87:24] wire _out_T_12288 = ~out_romask_1279; // @[RegisterRouter.scala:87:24] wire _out_T_12289 = ~out_womask_1279; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1099 = {hi_27, flags_0_go, _out_prepend_T_1099}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12290 = out_prepend_1099; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12291 = _out_T_12290; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1100 = _out_T_12291; // @[RegisterRouter.scala:87:24] wire out_rimask_1280 = \|_out_rimask_T_1280; // @[RegisterRouter.scala:87:24] wire out_wimask_1280 = &_out_wimask_T_1280; // @[RegisterRouter.scala:87:24] wire out_romask_1280 = \|_out_romask_T_1280; // @[RegisterRouter.scala:87:24] wire out_womask_1280 = &_out_womask_T_1280; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1280 = out_rivalid_1_1134 & out_rimask_1280; // @[RegisterRouter.scala:87:24] wire _out_T_12293 = out_f_rivalid_1280; // @[RegisterRouter.scala:87:24] wire out_f_roready_1280 = out_roready_1_1134 & out_romask_1280; // @[RegisterRouter.scala:87:24] wire _out_T_12294 = out_f_roready_1280; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1280 = out_wivalid_1_1134 & out_wimask_1280; // @[RegisterRouter.scala:87:24] wire out_f_woready_1280 = out_woready_1_1134 & out_womask_1280; // @[RegisterRouter.scala:87:24] wire _out_T_12295 = ~out_rimask_1280; // @[RegisterRouter.scala:87:24] wire _out_T_12296 = ~out_wimask_1280; // @[RegisterRouter.scala:87:24] wire _out_T_12297 = ~out_romask_1280; // @[RegisterRouter.scala:87:24] wire _out_T_12298 = ~out_womask_1280; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1100 = {hi_28, flags_0_go, _out_prepend_T_1100}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12299 = out_prepend_1100; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12300 = _out_T_12299; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1101 = _out_T_12300; // @[RegisterRouter.scala:87:24] wire out_rimask_1281 = \|_out_rimask_T_1281; // @[RegisterRouter.scala:87:24] wire out_wimask_1281 = &_out_wimask_T_1281; // @[RegisterRouter.scala:87:24] wire out_romask_1281 = \|_out_romask_T_1281; // @[RegisterRouter.scala:87:24] wire out_womask_1281 = &_out_womask_T_1281; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1281 = out_rivalid_1_1135 & out_rimask_1281; // @[RegisterRouter.scala:87:24] wire _out_T_12302 = out_f_rivalid_1281; // @[RegisterRouter.scala:87:24] wire out_f_roready_1281 = out_roready_1_1135 & out_romask_1281; // @[RegisterRouter.scala:87:24] wire _out_T_12303 = out_f_roready_1281; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1281 = out_wivalid_1_1135 & out_wimask_1281; // @[RegisterRouter.scala:87:24] wire out_f_woready_1281 = out_woready_1_1135 & out_womask_1281; // @[RegisterRouter.scala:87:24] wire _out_T_12304 = ~out_rimask_1281; // @[RegisterRouter.scala:87:24] wire _out_T_12305 = ~out_wimask_1281; // @[RegisterRouter.scala:87:24] wire _out_T_12306 = ~out_romask_1281; // @[RegisterRouter.scala:87:24] wire _out_T_12307 = ~out_womask_1281; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1101 = {hi_29, flags_0_go, _out_prepend_T_1101}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12308 = out_prepend_1101; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12309 = _out_T_12308; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1102 = _out_T_12309; // @[RegisterRouter.scala:87:24] wire out_rimask_1282 = \|_out_rimask_T_1282; // @[RegisterRouter.scala:87:24] wire out_wimask_1282 = &_out_wimask_T_1282; // @[RegisterRouter.scala:87:24] wire out_romask_1282 = \|_out_romask_T_1282; // @[RegisterRouter.scala:87:24] wire out_womask_1282 = &_out_womask_T_1282; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1282 = out_rivalid_1_1136 & out_rimask_1282; // @[RegisterRouter.scala:87:24] wire _out_T_12311 = out_f_rivalid_1282; // @[RegisterRouter.scala:87:24] wire out_f_roready_1282 = out_roready_1_1136 & out_romask_1282; // @[RegisterRouter.scala:87:24] wire _out_T_12312 = out_f_roready_1282; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1282 = out_wivalid_1_1136 & out_wimask_1282; // @[RegisterRouter.scala:87:24] wire out_f_woready_1282 = out_woready_1_1136 & out_womask_1282; // @[RegisterRouter.scala:87:24] wire _out_T_12313 = ~out_rimask_1282; // @[RegisterRouter.scala:87:24] wire _out_T_12314 = ~out_wimask_1282; // @[RegisterRouter.scala:87:24] wire _out_T_12315 = ~out_romask_1282; // @[RegisterRouter.scala:87:24] wire _out_T_12316 = ~out_womask_1282; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1102 = {hi_30, flags_0_go, _out_prepend_T_1102}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12317 = out_prepend_1102; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12318 = _out_T_12317; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1103 = _out_T_12318; // @[RegisterRouter.scala:87:24] wire out_rimask_1283 = \|_out_rimask_T_1283; // @[RegisterRouter.scala:87:24] wire out_wimask_1283 = &_out_wimask_T_1283; // @[RegisterRouter.scala:87:24] wire out_romask_1283 = \|_out_romask_T_1283; // @[RegisterRouter.scala:87:24] wire out_womask_1283 = &_out_womask_T_1283; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1283 = out_rivalid_1_1137 & out_rimask_1283; // @[RegisterRouter.scala:87:24] wire _out_T_12320 = out_f_rivalid_1283; // @[RegisterRouter.scala:87:24] wire out_f_roready_1283 = out_roready_1_1137 & out_romask_1283; // @[RegisterRouter.scala:87:24] wire _out_T_12321 = out_f_roready_1283; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1283 = out_wivalid_1_1137 & out_wimask_1283; // @[RegisterRouter.scala:87:24] wire out_f_woready_1283 = out_woready_1_1137 & out_womask_1283; // @[RegisterRouter.scala:87:24] wire _out_T_12322 = ~out_rimask_1283; // @[RegisterRouter.scala:87:24] wire _out_T_12323 = ~out_wimask_1283; // @[RegisterRouter.scala:87:24] wire _out_T_12324 = ~out_romask_1283; // @[RegisterRouter.scala:87:24] wire _out_T_12325 = ~out_womask_1283; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1103 = {hi_31, flags_0_go, _out_prepend_T_1103}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12326 = out_prepend_1103; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12327 = _out_T_12326; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1104 = _out_T_12327; // @[RegisterRouter.scala:87:24] wire out_rimask_1284 = \|_out_rimask_T_1284; // @[RegisterRouter.scala:87:24] wire out_wimask_1284 = &_out_wimask_T_1284; // @[RegisterRouter.scala:87:24] wire out_romask_1284 = \|_out_romask_T_1284; // @[RegisterRouter.scala:87:24] wire out_womask_1284 = &_out_womask_T_1284; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1284 = out_rivalid_1_1138 & out_rimask_1284; // @[RegisterRouter.scala:87:24] wire _out_T_12329 = out_f_rivalid_1284; // @[RegisterRouter.scala:87:24] wire out_f_roready_1284 = out_roready_1_1138 & out_romask_1284; // @[RegisterRouter.scala:87:24] wire _out_T_12330 = out_f_roready_1284; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1284 = out_wivalid_1_1138 & out_wimask_1284; // @[RegisterRouter.scala:87:24] wire out_f_woready_1284 = out_woready_1_1138 & out_womask_1284; // @[RegisterRouter.scala:87:24] wire _out_T_12331 = ~out_rimask_1284; // @[RegisterRouter.scala:87:24] wire _out_T_12332 = ~out_wimask_1284; // @[RegisterRouter.scala:87:24] wire _out_T_12333 = ~out_romask_1284; // @[RegisterRouter.scala:87:24] wire _out_T_12334 = ~out_womask_1284; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1104 = {hi_32, flags_0_go, _out_prepend_T_1104}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12335 = out_prepend_1104; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12336 = _out_T_12335; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_131 = _out_T_12336; // @[MuxLiteral.scala:49:48] wire out_rimask_1285 = \|_out_rimask_T_1285; // @[RegisterRouter.scala:87:24] wire out_wimask_1285 = &_out_wimask_T_1285; // @[RegisterRouter.scala:87:24] wire out_romask_1285 = \|_out_romask_T_1285; // @[RegisterRouter.scala:87:24] wire out_womask_1285 = &_out_womask_T_1285; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1285 = out_rivalid_1_1139 & out_rimask_1285; // @[RegisterRouter.scala:87:24] wire _out_T_12338 = out_f_rivalid_1285; // @[RegisterRouter.scala:87:24] wire out_f_roready_1285 = out_roready_1_1139 & out_romask_1285; // @[RegisterRouter.scala:87:24] wire _out_T_12339 = out_f_roready_1285; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1285 = out_wivalid_1_1139 & out_wimask_1285; // @[RegisterRouter.scala:87:24] wire out_f_woready_1285 = out_woready_1_1139 & out_womask_1285; // @[RegisterRouter.scala:87:24] wire _out_T_12340 = ~out_rimask_1285; // @[RegisterRouter.scala:87:24] wire _out_T_12341 = ~out_wimask_1285; // @[RegisterRouter.scala:87:24] wire _out_T_12342 = ~out_romask_1285; // @[RegisterRouter.scala:87:24] wire _out_T_12343 = ~out_womask_1285; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12345 = _out_T_12344; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1105 = _out_T_12345; // @[RegisterRouter.scala:87:24] wire out_rimask_1286 = \|_out_rimask_T_1286; // @[RegisterRouter.scala:87:24] wire out_wimask_1286 = &_out_wimask_T_1286; // @[RegisterRouter.scala:87:24] wire out_romask_1286 = \|_out_romask_T_1286; // @[RegisterRouter.scala:87:24] wire out_womask_1286 = &_out_womask_T_1286; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1286 = out_rivalid_1_1140 & out_rimask_1286; // @[RegisterRouter.scala:87:24] wire _out_T_12347 = out_f_rivalid_1286; // @[RegisterRouter.scala:87:24] wire out_f_roready_1286 = out_roready_1_1140 & out_romask_1286; // @[RegisterRouter.scala:87:24] wire _out_T_12348 = out_f_roready_1286; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1286 = out_wivalid_1_1140 & out_wimask_1286; // @[RegisterRouter.scala:87:24] wire out_f_woready_1286 = out_woready_1_1140 & out_womask_1286; // @[RegisterRouter.scala:87:24] wire _out_T_12349 = ~out_rimask_1286; // @[RegisterRouter.scala:87:24] wire _out_T_12350 = ~out_wimask_1286; // @[RegisterRouter.scala:87:24] wire _out_T_12351 = ~out_romask_1286; // @[RegisterRouter.scala:87:24] wire _out_T_12352 = ~out_womask_1286; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1105 = {hi_402, flags_0_go, _out_prepend_T_1105}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12353 = out_prepend_1105; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12354 = _out_T_12353; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1106 = _out_T_12354; // @[RegisterRouter.scala:87:24] wire out_rimask_1287 = \|_out_rimask_T_1287; // @[RegisterRouter.scala:87:24] wire out_wimask_1287 = &_out_wimask_T_1287; // @[RegisterRouter.scala:87:24] wire out_romask_1287 = \|_out_romask_T_1287; // @[RegisterRouter.scala:87:24] wire out_womask_1287 = &_out_womask_T_1287; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1287 = out_rivalid_1_1141 & out_rimask_1287; // @[RegisterRouter.scala:87:24] wire _out_T_12356 = out_f_rivalid_1287; // @[RegisterRouter.scala:87:24] wire out_f_roready_1287 = out_roready_1_1141 & out_romask_1287; // @[RegisterRouter.scala:87:24] wire _out_T_12357 = out_f_roready_1287; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1287 = out_wivalid_1_1141 & out_wimask_1287; // @[RegisterRouter.scala:87:24] wire out_f_woready_1287 = out_woready_1_1141 & out_womask_1287; // @[RegisterRouter.scala:87:24] wire _out_T_12358 = ~out_rimask_1287; // @[RegisterRouter.scala:87:24] wire _out_T_12359 = ~out_wimask_1287; // @[RegisterRouter.scala:87:24] wire _out_T_12360 = ~out_romask_1287; // @[RegisterRouter.scala:87:24] wire _out_T_12361 = ~out_womask_1287; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1106 = {hi_403, flags_0_go, _out_prepend_T_1106}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12362 = out_prepend_1106; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12363 = _out_T_12362; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1107 = _out_T_12363; // @[RegisterRouter.scala:87:24] wire out_rimask_1288 = \|_out_rimask_T_1288; // @[RegisterRouter.scala:87:24] wire out_wimask_1288 = &_out_wimask_T_1288; // @[RegisterRouter.scala:87:24] wire out_romask_1288 = \|_out_romask_T_1288; // @[RegisterRouter.scala:87:24] wire out_womask_1288 = &_out_womask_T_1288; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1288 = out_rivalid_1_1142 & out_rimask_1288; // @[RegisterRouter.scala:87:24] wire _out_T_12365 = out_f_rivalid_1288; // @[RegisterRouter.scala:87:24] wire out_f_roready_1288 = out_roready_1_1142 & out_romask_1288; // @[RegisterRouter.scala:87:24] wire _out_T_12366 = out_f_roready_1288; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1288 = out_wivalid_1_1142 & out_wimask_1288; // @[RegisterRouter.scala:87:24] wire out_f_woready_1288 = out_woready_1_1142 & out_womask_1288; // @[RegisterRouter.scala:87:24] wire _out_T_12367 = ~out_rimask_1288; // @[RegisterRouter.scala:87:24] wire _out_T_12368 = ~out_wimask_1288; // @[RegisterRouter.scala:87:24] wire _out_T_12369 = ~out_romask_1288; // @[RegisterRouter.scala:87:24] wire _out_T_12370 = ~out_womask_1288; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1107 = {hi_404, flags_0_go, _out_prepend_T_1107}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12371 = out_prepend_1107; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12372 = _out_T_12371; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1108 = _out_T_12372; // @[RegisterRouter.scala:87:24] wire out_rimask_1289 = \|_out_rimask_T_1289; // @[RegisterRouter.scala:87:24] wire out_wimask_1289 = &_out_wimask_T_1289; // @[RegisterRouter.scala:87:24] wire out_romask_1289 = \|_out_romask_T_1289; // @[RegisterRouter.scala:87:24] wire out_womask_1289 = &_out_womask_T_1289; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1289 = out_rivalid_1_1143 & out_rimask_1289; // @[RegisterRouter.scala:87:24] wire _out_T_12374 = out_f_rivalid_1289; // @[RegisterRouter.scala:87:24] wire out_f_roready_1289 = out_roready_1_1143 & out_romask_1289; // @[RegisterRouter.scala:87:24] wire _out_T_12375 = out_f_roready_1289; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1289 = out_wivalid_1_1143 & out_wimask_1289; // @[RegisterRouter.scala:87:24] wire out_f_woready_1289 = out_woready_1_1143 & out_womask_1289; // @[RegisterRouter.scala:87:24] wire _out_T_12376 = ~out_rimask_1289; // @[RegisterRouter.scala:87:24] wire _out_T_12377 = ~out_wimask_1289; // @[RegisterRouter.scala:87:24] wire _out_T_12378 = ~out_romask_1289; // @[RegisterRouter.scala:87:24] wire _out_T_12379 = ~out_womask_1289; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1108 = {hi_405, flags_0_go, _out_prepend_T_1108}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12380 = out_prepend_1108; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12381 = _out_T_12380; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1109 = _out_T_12381; // @[RegisterRouter.scala:87:24] wire out_rimask_1290 = \|_out_rimask_T_1290; // @[RegisterRouter.scala:87:24] wire out_wimask_1290 = &_out_wimask_T_1290; // @[RegisterRouter.scala:87:24] wire out_romask_1290 = \|_out_romask_T_1290; // @[RegisterRouter.scala:87:24] wire out_womask_1290 = &_out_womask_T_1290; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1290 = out_rivalid_1_1144 & out_rimask_1290; // @[RegisterRouter.scala:87:24] wire _out_T_12383 = out_f_rivalid_1290; // @[RegisterRouter.scala:87:24] wire out_f_roready_1290 = out_roready_1_1144 & out_romask_1290; // @[RegisterRouter.scala:87:24] wire _out_T_12384 = out_f_roready_1290; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1290 = out_wivalid_1_1144 & out_wimask_1290; // @[RegisterRouter.scala:87:24] wire out_f_woready_1290 = out_woready_1_1144 & out_womask_1290; // @[RegisterRouter.scala:87:24] wire _out_T_12385 = ~out_rimask_1290; // @[RegisterRouter.scala:87:24] wire _out_T_12386 = ~out_wimask_1290; // @[RegisterRouter.scala:87:24] wire _out_T_12387 = ~out_romask_1290; // @[RegisterRouter.scala:87:24] wire _out_T_12388 = ~out_womask_1290; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1109 = {hi_406, flags_0_go, _out_prepend_T_1109}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12389 = out_prepend_1109; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12390 = _out_T_12389; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1110 = _out_T_12390; // @[RegisterRouter.scala:87:24] wire out_rimask_1291 = \|_out_rimask_T_1291; // @[RegisterRouter.scala:87:24] wire out_wimask_1291 = &_out_wimask_T_1291; // @[RegisterRouter.scala:87:24] wire out_romask_1291 = \|_out_romask_T_1291; // @[RegisterRouter.scala:87:24] wire out_womask_1291 = &_out_womask_T_1291; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1291 = out_rivalid_1_1145 & out_rimask_1291; // @[RegisterRouter.scala:87:24] wire _out_T_12392 = out_f_rivalid_1291; // @[RegisterRouter.scala:87:24] wire out_f_roready_1291 = out_roready_1_1145 & out_romask_1291; // @[RegisterRouter.scala:87:24] wire _out_T_12393 = out_f_roready_1291; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1291 = out_wivalid_1_1145 & out_wimask_1291; // @[RegisterRouter.scala:87:24] wire out_f_woready_1291 = out_woready_1_1145 & out_womask_1291; // @[RegisterRouter.scala:87:24] wire _out_T_12394 = ~out_rimask_1291; // @[RegisterRouter.scala:87:24] wire _out_T_12395 = ~out_wimask_1291; // @[RegisterRouter.scala:87:24] wire _out_T_12396 = ~out_romask_1291; // @[RegisterRouter.scala:87:24] wire _out_T_12397 = ~out_womask_1291; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1110 = {hi_407, flags_0_go, _out_prepend_T_1110}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12398 = out_prepend_1110; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12399 = _out_T_12398; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1111 = _out_T_12399; // @[RegisterRouter.scala:87:24] wire out_rimask_1292 = \|_out_rimask_T_1292; // @[RegisterRouter.scala:87:24] wire out_wimask_1292 = &_out_wimask_T_1292; // @[RegisterRouter.scala:87:24] wire out_romask_1292 = \|_out_romask_T_1292; // @[RegisterRouter.scala:87:24] wire out_womask_1292 = &_out_womask_T_1292; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1292 = out_rivalid_1_1146 & out_rimask_1292; // @[RegisterRouter.scala:87:24] wire _out_T_12401 = out_f_rivalid_1292; // @[RegisterRouter.scala:87:24] wire out_f_roready_1292 = out_roready_1_1146 & out_romask_1292; // @[RegisterRouter.scala:87:24] wire _out_T_12402 = out_f_roready_1292; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1292 = out_wivalid_1_1146 & out_wimask_1292; // @[RegisterRouter.scala:87:24] wire out_f_woready_1292 = out_woready_1_1146 & out_womask_1292; // @[RegisterRouter.scala:87:24] wire _out_T_12403 = ~out_rimask_1292; // @[RegisterRouter.scala:87:24] wire _out_T_12404 = ~out_wimask_1292; // @[RegisterRouter.scala:87:24] wire _out_T_12405 = ~out_romask_1292; // @[RegisterRouter.scala:87:24] wire _out_T_12406 = ~out_womask_1292; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1111 = {hi_408, flags_0_go, _out_prepend_T_1111}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12407 = out_prepend_1111; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12408 = _out_T_12407; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_178 = _out_T_12408; // @[MuxLiteral.scala:49:48] wire out_rimask_1293 = \|_out_rimask_T_1293; // @[RegisterRouter.scala:87:24] wire out_wimask_1293 = &_out_wimask_T_1293; // @[RegisterRouter.scala:87:24] wire out_romask_1293 = \|_out_romask_T_1293; // @[RegisterRouter.scala:87:24] wire out_womask_1293 = &_out_womask_T_1293; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1293 = out_rivalid_1_1147 & out_rimask_1293; // @[RegisterRouter.scala:87:24] wire _out_T_12410 = out_f_rivalid_1293; // @[RegisterRouter.scala:87:24] wire out_f_roready_1293 = out_roready_1_1147 & out_romask_1293; // @[RegisterRouter.scala:87:24] wire _out_T_12411 = out_f_roready_1293; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1293 = out_wivalid_1_1147 & out_wimask_1293; // @[RegisterRouter.scala:87:24] wire out_f_woready_1293 = out_woready_1_1147 & out_womask_1293; // @[RegisterRouter.scala:87:24] wire _out_T_12412 = ~out_rimask_1293; // @[RegisterRouter.scala:87:24] wire _out_T_12413 = ~out_wimask_1293; // @[RegisterRouter.scala:87:24] wire _out_T_12414 = ~out_romask_1293; // @[RegisterRouter.scala:87:24] wire _out_T_12415 = ~out_womask_1293; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12417 = _out_T_12416; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1112 = _out_T_12417; // @[RegisterRouter.scala:87:24] wire out_rimask_1294 = \|_out_rimask_T_1294; // @[RegisterRouter.scala:87:24] wire out_wimask_1294 = &_out_wimask_T_1294; // @[RegisterRouter.scala:87:24] wire out_romask_1294 = \|_out_romask_T_1294; // @[RegisterRouter.scala:87:24] wire out_womask_1294 = &_out_womask_T_1294; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1294 = out_rivalid_1_1148 & out_rimask_1294; // @[RegisterRouter.scala:87:24] wire _out_T_12419 = out_f_rivalid_1294; // @[RegisterRouter.scala:87:24] wire out_f_roready_1294 = out_roready_1_1148 & out_romask_1294; // @[RegisterRouter.scala:87:24] wire _out_T_12420 = out_f_roready_1294; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1294 = out_wivalid_1_1148 & out_wimask_1294; // @[RegisterRouter.scala:87:24] wire out_f_woready_1294 = out_woready_1_1148 & out_womask_1294; // @[RegisterRouter.scala:87:24] wire _out_T_12421 = ~out_rimask_1294; // @[RegisterRouter.scala:87:24] wire _out_T_12422 = ~out_wimask_1294; // @[RegisterRouter.scala:87:24] wire _out_T_12423 = ~out_romask_1294; // @[RegisterRouter.scala:87:24] wire _out_T_12424 = ~out_womask_1294; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1112 = {hi_282, flags_0_go, _out_prepend_T_1112}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12425 = out_prepend_1112; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12426 = _out_T_12425; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1113 = _out_T_12426; // @[RegisterRouter.scala:87:24] wire out_rimask_1295 = \|_out_rimask_T_1295; // @[RegisterRouter.scala:87:24] wire out_wimask_1295 = &_out_wimask_T_1295; // @[RegisterRouter.scala:87:24] wire out_romask_1295 = \|_out_romask_T_1295; // @[RegisterRouter.scala:87:24] wire out_womask_1295 = &_out_womask_T_1295; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1295 = out_rivalid_1_1149 & out_rimask_1295; // @[RegisterRouter.scala:87:24] wire _out_T_12428 = out_f_rivalid_1295; // @[RegisterRouter.scala:87:24] wire out_f_roready_1295 = out_roready_1_1149 & out_romask_1295; // @[RegisterRouter.scala:87:24] wire _out_T_12429 = out_f_roready_1295; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1295 = out_wivalid_1_1149 & out_wimask_1295; // @[RegisterRouter.scala:87:24] wire out_f_woready_1295 = out_woready_1_1149 & out_womask_1295; // @[RegisterRouter.scala:87:24] wire _out_T_12430 = ~out_rimask_1295; // @[RegisterRouter.scala:87:24] wire _out_T_12431 = ~out_wimask_1295; // @[RegisterRouter.scala:87:24] wire _out_T_12432 = ~out_romask_1295; // @[RegisterRouter.scala:87:24] wire _out_T_12433 = ~out_womask_1295; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1113 = {hi_283, flags_0_go, _out_prepend_T_1113}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12434 = out_prepend_1113; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12435 = _out_T_12434; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1114 = _out_T_12435; // @[RegisterRouter.scala:87:24] wire out_rimask_1296 = \|_out_rimask_T_1296; // @[RegisterRouter.scala:87:24] wire out_wimask_1296 = &_out_wimask_T_1296; // @[RegisterRouter.scala:87:24] wire out_romask_1296 = \|_out_romask_T_1296; // @[RegisterRouter.scala:87:24] wire out_womask_1296 = &_out_womask_T_1296; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1296 = out_rivalid_1_1150 & out_rimask_1296; // @[RegisterRouter.scala:87:24] wire _out_T_12437 = out_f_rivalid_1296; // @[RegisterRouter.scala:87:24] wire out_f_roready_1296 = out_roready_1_1150 & out_romask_1296; // @[RegisterRouter.scala:87:24] wire _out_T_12438 = out_f_roready_1296; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1296 = out_wivalid_1_1150 & out_wimask_1296; // @[RegisterRouter.scala:87:24] wire out_f_woready_1296 = out_woready_1_1150 & out_womask_1296; // @[RegisterRouter.scala:87:24] wire _out_T_12439 = ~out_rimask_1296; // @[RegisterRouter.scala:87:24] wire _out_T_12440 = ~out_wimask_1296; // @[RegisterRouter.scala:87:24] wire _out_T_12441 = ~out_romask_1296; // @[RegisterRouter.scala:87:24] wire _out_T_12442 = ~out_womask_1296; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1114 = {hi_284, flags_0_go, _out_prepend_T_1114}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12443 = out_prepend_1114; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12444 = _out_T_12443; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1115 = _out_T_12444; // @[RegisterRouter.scala:87:24] wire out_rimask_1297 = \|_out_rimask_T_1297; // @[RegisterRouter.scala:87:24] wire out_wimask_1297 = &_out_wimask_T_1297; // @[RegisterRouter.scala:87:24] wire out_romask_1297 = \|_out_romask_T_1297; // @[RegisterRouter.scala:87:24] wire out_womask_1297 = &_out_womask_T_1297; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1297 = out_rivalid_1_1151 & out_rimask_1297; // @[RegisterRouter.scala:87:24] wire _out_T_12446 = out_f_rivalid_1297; // @[RegisterRouter.scala:87:24] wire out_f_roready_1297 = out_roready_1_1151 & out_romask_1297; // @[RegisterRouter.scala:87:24] wire _out_T_12447 = out_f_roready_1297; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1297 = out_wivalid_1_1151 & out_wimask_1297; // @[RegisterRouter.scala:87:24] wire out_f_woready_1297 = out_woready_1_1151 & out_womask_1297; // @[RegisterRouter.scala:87:24] wire _out_T_12448 = ~out_rimask_1297; // @[RegisterRouter.scala:87:24] wire _out_T_12449 = ~out_wimask_1297; // @[RegisterRouter.scala:87:24] wire _out_T_12450 = ~out_romask_1297; // @[RegisterRouter.scala:87:24] wire _out_T_12451 = ~out_womask_1297; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1115 = {hi_285, flags_0_go, _out_prepend_T_1115}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12452 = out_prepend_1115; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12453 = _out_T_12452; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1116 = _out_T_12453; // @[RegisterRouter.scala:87:24] wire out_rimask_1298 = \|_out_rimask_T_1298; // @[RegisterRouter.scala:87:24] wire out_wimask_1298 = &_out_wimask_T_1298; // @[RegisterRouter.scala:87:24] wire out_romask_1298 = \|_out_romask_T_1298; // @[RegisterRouter.scala:87:24] wire out_womask_1298 = &_out_womask_T_1298; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1298 = out_rivalid_1_1152 & out_rimask_1298; // @[RegisterRouter.scala:87:24] wire _out_T_12455 = out_f_rivalid_1298; // @[RegisterRouter.scala:87:24] wire out_f_roready_1298 = out_roready_1_1152 & out_romask_1298; // @[RegisterRouter.scala:87:24] wire _out_T_12456 = out_f_roready_1298; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1298 = out_wivalid_1_1152 & out_wimask_1298; // @[RegisterRouter.scala:87:24] wire out_f_woready_1298 = out_woready_1_1152 & out_womask_1298; // @[RegisterRouter.scala:87:24] wire _out_T_12457 = ~out_rimask_1298; // @[RegisterRouter.scala:87:24] wire _out_T_12458 = ~out_wimask_1298; // @[RegisterRouter.scala:87:24] wire _out_T_12459 = ~out_romask_1298; // @[RegisterRouter.scala:87:24] wire _out_T_12460 = ~out_womask_1298; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1116 = {hi_286, flags_0_go, _out_prepend_T_1116}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12461 = out_prepend_1116; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12462 = _out_T_12461; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1117 = _out_T_12462; // @[RegisterRouter.scala:87:24] wire out_rimask_1299 = \|_out_rimask_T_1299; // @[RegisterRouter.scala:87:24] wire out_wimask_1299 = &_out_wimask_T_1299; // @[RegisterRouter.scala:87:24] wire out_romask_1299 = \|_out_romask_T_1299; // @[RegisterRouter.scala:87:24] wire out_womask_1299 = &_out_womask_T_1299; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1299 = out_rivalid_1_1153 & out_rimask_1299; // @[RegisterRouter.scala:87:24] wire _out_T_12464 = out_f_rivalid_1299; // @[RegisterRouter.scala:87:24] wire out_f_roready_1299 = out_roready_1_1153 & out_romask_1299; // @[RegisterRouter.scala:87:24] wire _out_T_12465 = out_f_roready_1299; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1299 = out_wivalid_1_1153 & out_wimask_1299; // @[RegisterRouter.scala:87:24] wire out_f_woready_1299 = out_woready_1_1153 & out_womask_1299; // @[RegisterRouter.scala:87:24] wire _out_T_12466 = ~out_rimask_1299; // @[RegisterRouter.scala:87:24] wire _out_T_12467 = ~out_wimask_1299; // @[RegisterRouter.scala:87:24] wire _out_T_12468 = ~out_romask_1299; // @[RegisterRouter.scala:87:24] wire _out_T_12469 = ~out_womask_1299; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1117 = {hi_287, flags_0_go, _out_prepend_T_1117}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12470 = out_prepend_1117; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12471 = _out_T_12470; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1118 = _out_T_12471; // @[RegisterRouter.scala:87:24] wire out_rimask_1300 = \|_out_rimask_T_1300; // @[RegisterRouter.scala:87:24] wire out_wimask_1300 = &_out_wimask_T_1300; // @[RegisterRouter.scala:87:24] wire out_romask_1300 = \|_out_romask_T_1300; // @[RegisterRouter.scala:87:24] wire out_womask_1300 = &_out_womask_T_1300; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1300 = out_rivalid_1_1154 & out_rimask_1300; // @[RegisterRouter.scala:87:24] wire _out_T_12473 = out_f_rivalid_1300; // @[RegisterRouter.scala:87:24] wire out_f_roready_1300 = out_roready_1_1154 & out_romask_1300; // @[RegisterRouter.scala:87:24] wire _out_T_12474 = out_f_roready_1300; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1300 = out_wivalid_1_1154 & out_wimask_1300; // @[RegisterRouter.scala:87:24] wire out_f_woready_1300 = out_woready_1_1154 & out_womask_1300; // @[RegisterRouter.scala:87:24] wire _out_T_12475 = ~out_rimask_1300; // @[RegisterRouter.scala:87:24] wire _out_T_12476 = ~out_wimask_1300; // @[RegisterRouter.scala:87:24] wire _out_T_12477 = ~out_romask_1300; // @[RegisterRouter.scala:87:24] wire _out_T_12478 = ~out_womask_1300; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1118 = {hi_288, flags_0_go, _out_prepend_T_1118}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12479 = out_prepend_1118; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12480 = _out_T_12479; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_163 = _out_T_12480; // @[MuxLiteral.scala:49:48] wire out_rimask_1301 = \|_out_rimask_T_1301; // @[RegisterRouter.scala:87:24] wire out_wimask_1301 = &_out_wimask_T_1301; // @[RegisterRouter.scala:87:24] wire out_romask_1301 = \|_out_romask_T_1301; // @[RegisterRouter.scala:87:24] wire out_womask_1301 = &_out_womask_T_1301; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1301 = out_rivalid_1_1155 & out_rimask_1301; // @[RegisterRouter.scala:87:24] wire _out_T_12482 = out_f_rivalid_1301; // @[RegisterRouter.scala:87:24] wire out_f_roready_1301 = out_roready_1_1155 & out_romask_1301; // @[RegisterRouter.scala:87:24] wire _out_T_12483 = out_f_roready_1301; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1301 = out_wivalid_1_1155 & out_wimask_1301; // @[RegisterRouter.scala:87:24] wire out_f_woready_1301 = out_woready_1_1155 & out_womask_1301; // @[RegisterRouter.scala:87:24] wire _out_T_12484 = ~out_rimask_1301; // @[RegisterRouter.scala:87:24] wire _out_T_12485 = ~out_wimask_1301; // @[RegisterRouter.scala:87:24] wire _out_T_12486 = ~out_romask_1301; // @[RegisterRouter.scala:87:24] wire _out_T_12487 = ~out_womask_1301; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12489 = _out_T_12488; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1119 = _out_T_12489; // @[RegisterRouter.scala:87:24] wire out_rimask_1302 = \|_out_rimask_T_1302; // @[RegisterRouter.scala:87:24] wire out_wimask_1302 = &_out_wimask_T_1302; // @[RegisterRouter.scala:87:24] wire out_romask_1302 = \|_out_romask_T_1302; // @[RegisterRouter.scala:87:24] wire out_womask_1302 = &_out_womask_T_1302; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1302 = out_rivalid_1_1156 & out_rimask_1302; // @[RegisterRouter.scala:87:24] wire _out_T_12491 = out_f_rivalid_1302; // @[RegisterRouter.scala:87:24] wire out_f_roready_1302 = out_roready_1_1156 & out_romask_1302; // @[RegisterRouter.scala:87:24] wire _out_T_12492 = out_f_roready_1302; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1302 = out_wivalid_1_1156 & out_wimask_1302; // @[RegisterRouter.scala:87:24] wire out_f_woready_1302 = out_woready_1_1156 & out_womask_1302; // @[RegisterRouter.scala:87:24] wire _out_T_12493 = ~out_rimask_1302; // @[RegisterRouter.scala:87:24] wire _out_T_12494 = ~out_wimask_1302; // @[RegisterRouter.scala:87:24] wire _out_T_12495 = ~out_romask_1302; // @[RegisterRouter.scala:87:24] wire _out_T_12496 = ~out_womask_1302; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1119 = {hi_578, flags_0_go, _out_prepend_T_1119}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12497 = out_prepend_1119; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12498 = _out_T_12497; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1120 = _out_T_12498; // @[RegisterRouter.scala:87:24] wire out_rimask_1303 = \|_out_rimask_T_1303; // @[RegisterRouter.scala:87:24] wire out_wimask_1303 = &_out_wimask_T_1303; // @[RegisterRouter.scala:87:24] wire out_romask_1303 = \|_out_romask_T_1303; // @[RegisterRouter.scala:87:24] wire out_womask_1303 = &_out_womask_T_1303; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1303 = out_rivalid_1_1157 & out_rimask_1303; // @[RegisterRouter.scala:87:24] wire _out_T_12500 = out_f_rivalid_1303; // @[RegisterRouter.scala:87:24] wire out_f_roready_1303 = out_roready_1_1157 & out_romask_1303; // @[RegisterRouter.scala:87:24] wire _out_T_12501 = out_f_roready_1303; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1303 = out_wivalid_1_1157 & out_wimask_1303; // @[RegisterRouter.scala:87:24] wire out_f_woready_1303 = out_woready_1_1157 & out_womask_1303; // @[RegisterRouter.scala:87:24] wire _out_T_12502 = ~out_rimask_1303; // @[RegisterRouter.scala:87:24] wire _out_T_12503 = ~out_wimask_1303; // @[RegisterRouter.scala:87:24] wire _out_T_12504 = ~out_romask_1303; // @[RegisterRouter.scala:87:24] wire _out_T_12505 = ~out_womask_1303; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1120 = {hi_579, flags_0_go, _out_prepend_T_1120}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12506 = out_prepend_1120; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12507 = _out_T_12506; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1121 = _out_T_12507; // @[RegisterRouter.scala:87:24] wire out_rimask_1304 = \|_out_rimask_T_1304; // @[RegisterRouter.scala:87:24] wire out_wimask_1304 = &_out_wimask_T_1304; // @[RegisterRouter.scala:87:24] wire out_romask_1304 = \|_out_romask_T_1304; // @[RegisterRouter.scala:87:24] wire out_womask_1304 = &_out_womask_T_1304; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1304 = out_rivalid_1_1158 & out_rimask_1304; // @[RegisterRouter.scala:87:24] wire _out_T_12509 = out_f_rivalid_1304; // @[RegisterRouter.scala:87:24] wire out_f_roready_1304 = out_roready_1_1158 & out_romask_1304; // @[RegisterRouter.scala:87:24] wire _out_T_12510 = out_f_roready_1304; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1304 = out_wivalid_1_1158 & out_wimask_1304; // @[RegisterRouter.scala:87:24] wire out_f_woready_1304 = out_woready_1_1158 & out_womask_1304; // @[RegisterRouter.scala:87:24] wire _out_T_12511 = ~out_rimask_1304; // @[RegisterRouter.scala:87:24] wire _out_T_12512 = ~out_wimask_1304; // @[RegisterRouter.scala:87:24] wire _out_T_12513 = ~out_romask_1304; // @[RegisterRouter.scala:87:24] wire _out_T_12514 = ~out_womask_1304; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1121 = {hi_580, flags_0_go, _out_prepend_T_1121}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12515 = out_prepend_1121; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12516 = _out_T_12515; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1122 = _out_T_12516; // @[RegisterRouter.scala:87:24] wire out_rimask_1305 = \|_out_rimask_T_1305; // @[RegisterRouter.scala:87:24] wire out_wimask_1305 = &_out_wimask_T_1305; // @[RegisterRouter.scala:87:24] wire out_romask_1305 = \|_out_romask_T_1305; // @[RegisterRouter.scala:87:24] wire out_womask_1305 = &_out_womask_T_1305; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1305 = out_rivalid_1_1159 & out_rimask_1305; // @[RegisterRouter.scala:87:24] wire _out_T_12518 = out_f_rivalid_1305; // @[RegisterRouter.scala:87:24] wire out_f_roready_1305 = out_roready_1_1159 & out_romask_1305; // @[RegisterRouter.scala:87:24] wire _out_T_12519 = out_f_roready_1305; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1305 = out_wivalid_1_1159 & out_wimask_1305; // @[RegisterRouter.scala:87:24] wire out_f_woready_1305 = out_woready_1_1159 & out_womask_1305; // @[RegisterRouter.scala:87:24] wire _out_T_12520 = ~out_rimask_1305; // @[RegisterRouter.scala:87:24] wire _out_T_12521 = ~out_wimask_1305; // @[RegisterRouter.scala:87:24] wire _out_T_12522 = ~out_romask_1305; // @[RegisterRouter.scala:87:24] wire _out_T_12523 = ~out_womask_1305; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1122 = {hi_581, flags_0_go, _out_prepend_T_1122}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12524 = out_prepend_1122; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12525 = _out_T_12524; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1123 = _out_T_12525; // @[RegisterRouter.scala:87:24] wire out_rimask_1306 = \|_out_rimask_T_1306; // @[RegisterRouter.scala:87:24] wire out_wimask_1306 = &_out_wimask_T_1306; // @[RegisterRouter.scala:87:24] wire out_romask_1306 = \|_out_romask_T_1306; // @[RegisterRouter.scala:87:24] wire out_womask_1306 = &_out_womask_T_1306; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1306 = out_rivalid_1_1160 & out_rimask_1306; // @[RegisterRouter.scala:87:24] wire _out_T_12527 = out_f_rivalid_1306; // @[RegisterRouter.scala:87:24] wire out_f_roready_1306 = out_roready_1_1160 & out_romask_1306; // @[RegisterRouter.scala:87:24] wire _out_T_12528 = out_f_roready_1306; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1306 = out_wivalid_1_1160 & out_wimask_1306; // @[RegisterRouter.scala:87:24] wire out_f_woready_1306 = out_woready_1_1160 & out_womask_1306; // @[RegisterRouter.scala:87:24] wire _out_T_12529 = ~out_rimask_1306; // @[RegisterRouter.scala:87:24] wire _out_T_12530 = ~out_wimask_1306; // @[RegisterRouter.scala:87:24] wire _out_T_12531 = ~out_romask_1306; // @[RegisterRouter.scala:87:24] wire _out_T_12532 = ~out_womask_1306; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1123 = {hi_582, flags_0_go, _out_prepend_T_1123}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12533 = out_prepend_1123; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12534 = _out_T_12533; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1124 = _out_T_12534; // @[RegisterRouter.scala:87:24] wire out_rimask_1307 = \|_out_rimask_T_1307; // @[RegisterRouter.scala:87:24] wire out_wimask_1307 = &_out_wimask_T_1307; // @[RegisterRouter.scala:87:24] wire out_romask_1307 = \|_out_romask_T_1307; // @[RegisterRouter.scala:87:24] wire out_womask_1307 = &_out_womask_T_1307; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1307 = out_rivalid_1_1161 & out_rimask_1307; // @[RegisterRouter.scala:87:24] wire _out_T_12536 = out_f_rivalid_1307; // @[RegisterRouter.scala:87:24] wire out_f_roready_1307 = out_roready_1_1161 & out_romask_1307; // @[RegisterRouter.scala:87:24] wire _out_T_12537 = out_f_roready_1307; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1307 = out_wivalid_1_1161 & out_wimask_1307; // @[RegisterRouter.scala:87:24] wire out_f_woready_1307 = out_woready_1_1161 & out_womask_1307; // @[RegisterRouter.scala:87:24] wire _out_T_12538 = ~out_rimask_1307; // @[RegisterRouter.scala:87:24] wire _out_T_12539 = ~out_wimask_1307; // @[RegisterRouter.scala:87:24] wire _out_T_12540 = ~out_romask_1307; // @[RegisterRouter.scala:87:24] wire _out_T_12541 = ~out_womask_1307; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1124 = {hi_583, flags_0_go, _out_prepend_T_1124}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12542 = out_prepend_1124; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12543 = _out_T_12542; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1125 = _out_T_12543; // @[RegisterRouter.scala:87:24] wire out_rimask_1308 = \|_out_rimask_T_1308; // @[RegisterRouter.scala:87:24] wire out_wimask_1308 = &_out_wimask_T_1308; // @[RegisterRouter.scala:87:24] wire out_romask_1308 = \|_out_romask_T_1308; // @[RegisterRouter.scala:87:24] wire out_womask_1308 = &_out_womask_T_1308; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1308 = out_rivalid_1_1162 & out_rimask_1308; // @[RegisterRouter.scala:87:24] wire _out_T_12545 = out_f_rivalid_1308; // @[RegisterRouter.scala:87:24] wire out_f_roready_1308 = out_roready_1_1162 & out_romask_1308; // @[RegisterRouter.scala:87:24] wire _out_T_12546 = out_f_roready_1308; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1308 = out_wivalid_1_1162 & out_wimask_1308; // @[RegisterRouter.scala:87:24] wire out_f_woready_1308 = out_woready_1_1162 & out_womask_1308; // @[RegisterRouter.scala:87:24] wire _out_T_12547 = ~out_rimask_1308; // @[RegisterRouter.scala:87:24] wire _out_T_12548 = ~out_wimask_1308; // @[RegisterRouter.scala:87:24] wire _out_T_12549 = ~out_romask_1308; // @[RegisterRouter.scala:87:24] wire _out_T_12550 = ~out_womask_1308; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1125 = {hi_584, flags_0_go, _out_prepend_T_1125}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12551 = out_prepend_1125; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12552 = _out_T_12551; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_200 = _out_T_12552; // @[MuxLiteral.scala:49:48] wire out_rimask_1309 = \|_out_rimask_T_1309; // @[RegisterRouter.scala:87:24] wire out_wimask_1309 = &_out_wimask_T_1309; // @[RegisterRouter.scala:87:24] wire out_romask_1309 = \|_out_romask_T_1309; // @[RegisterRouter.scala:87:24] wire out_womask_1309 = &_out_womask_T_1309; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1309 = out_rivalid_1_1163 & out_rimask_1309; // @[RegisterRouter.scala:87:24] wire _out_T_12554 = out_f_rivalid_1309; // @[RegisterRouter.scala:87:24] wire out_f_roready_1309 = out_roready_1_1163 & out_romask_1309; // @[RegisterRouter.scala:87:24] wire _out_T_12555 = out_f_roready_1309; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1309 = out_wivalid_1_1163 & out_wimask_1309; // @[RegisterRouter.scala:87:24] wire _out_T_12556 = out_f_wivalid_1309; // @[RegisterRouter.scala:87:24] wire out_f_woready_1309 = out_woready_1_1163 & out_womask_1309; // @[RegisterRouter.scala:87:24] wire _out_T_12557 = out_f_woready_1309; // @[RegisterRouter.scala:87:24] wire _out_T_12558 = ~out_rimask_1309; // @[RegisterRouter.scala:87:24] wire _out_T_12559 = ~out_wimask_1309; // @[RegisterRouter.scala:87:24] wire _out_T_12560 = ~out_romask_1309; // @[RegisterRouter.scala:87:24] wire _out_T_12561 = ~out_womask_1309; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12563 = _out_T_12562; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1126 = _out_T_12563; // @[RegisterRouter.scala:87:24] wire out_rimask_1310 = \|_out_rimask_T_1310; // @[RegisterRouter.scala:87:24] wire out_wimask_1310 = &_out_wimask_T_1310; // @[RegisterRouter.scala:87:24] wire out_romask_1310 = \|_out_romask_T_1310; // @[RegisterRouter.scala:87:24] wire out_womask_1310 = &_out_womask_T_1310; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1310 = out_rivalid_1_1164 & out_rimask_1310; // @[RegisterRouter.scala:87:24] wire _out_T_12565 = out_f_rivalid_1310; // @[RegisterRouter.scala:87:24] wire out_f_roready_1310 = out_roready_1_1164 & out_romask_1310; // @[RegisterRouter.scala:87:24] wire _out_T_12566 = out_f_roready_1310; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1310 = out_wivalid_1_1164 & out_wimask_1310; // @[RegisterRouter.scala:87:24] wire _out_T_12567 = out_f_wivalid_1310; // @[RegisterRouter.scala:87:24] wire out_f_woready_1310 = out_woready_1_1164 & out_womask_1310; // @[RegisterRouter.scala:87:24] wire _out_T_12568 = out_f_woready_1310; // @[RegisterRouter.scala:87:24] wire _out_T_12569 = ~out_rimask_1310; // @[RegisterRouter.scala:87:24] wire _out_T_12570 = ~out_wimask_1310; // @[RegisterRouter.scala:87:24] wire _out_T_12571 = ~out_romask_1310; // @[RegisterRouter.scala:87:24] wire _out_T_12572 = ~out_womask_1310; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1126 = {programBufferMem_57, _out_prepend_T_1126}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12573 = out_prepend_1126; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12574 = _out_T_12573; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1127 = _out_T_12574; // @[RegisterRouter.scala:87:24] wire out_rimask_1311 = \|_out_rimask_T_1311; // @[RegisterRouter.scala:87:24] wire out_wimask_1311 = &_out_wimask_T_1311; // @[RegisterRouter.scala:87:24] wire out_romask_1311 = \|_out_romask_T_1311; // @[RegisterRouter.scala:87:24] wire out_womask_1311 = &_out_womask_T_1311; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1311 = out_rivalid_1_1165 & out_rimask_1311; // @[RegisterRouter.scala:87:24] wire _out_T_12576 = out_f_rivalid_1311; // @[RegisterRouter.scala:87:24] wire out_f_roready_1311 = out_roready_1_1165 & out_romask_1311; // @[RegisterRouter.scala:87:24] wire _out_T_12577 = out_f_roready_1311; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1311 = out_wivalid_1_1165 & out_wimask_1311; // @[RegisterRouter.scala:87:24] wire _out_T_12578 = out_f_wivalid_1311; // @[RegisterRouter.scala:87:24] wire out_f_woready_1311 = out_woready_1_1165 & out_womask_1311; // @[RegisterRouter.scala:87:24] wire _out_T_12579 = out_f_woready_1311; // @[RegisterRouter.scala:87:24] wire _out_T_12580 = ~out_rimask_1311; // @[RegisterRouter.scala:87:24] wire _out_T_12581 = ~out_wimask_1311; // @[RegisterRouter.scala:87:24] wire _out_T_12582 = ~out_romask_1311; // @[RegisterRouter.scala:87:24] wire _out_T_12583 = ~out_womask_1311; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1127 = {programBufferMem_58, _out_prepend_T_1127}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12584 = out_prepend_1127; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12585 = _out_T_12584; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1128 = _out_T_12585; // @[RegisterRouter.scala:87:24] wire out_rimask_1312 = \|_out_rimask_T_1312; // @[RegisterRouter.scala:87:24] wire out_wimask_1312 = &_out_wimask_T_1312; // @[RegisterRouter.scala:87:24] wire out_romask_1312 = \|_out_romask_T_1312; // @[RegisterRouter.scala:87:24] wire out_womask_1312 = &_out_womask_T_1312; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1312 = out_rivalid_1_1166 & out_rimask_1312; // @[RegisterRouter.scala:87:24] wire _out_T_12587 = out_f_rivalid_1312; // @[RegisterRouter.scala:87:24] wire out_f_roready_1312 = out_roready_1_1166 & out_romask_1312; // @[RegisterRouter.scala:87:24] wire _out_T_12588 = out_f_roready_1312; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1312 = out_wivalid_1_1166 & out_wimask_1312; // @[RegisterRouter.scala:87:24] wire _out_T_12589 = out_f_wivalid_1312; // @[RegisterRouter.scala:87:24] wire out_f_woready_1312 = out_woready_1_1166 & out_womask_1312; // @[RegisterRouter.scala:87:24] wire _out_T_12590 = out_f_woready_1312; // @[RegisterRouter.scala:87:24] wire _out_T_12591 = ~out_rimask_1312; // @[RegisterRouter.scala:87:24] wire _out_T_12592 = ~out_wimask_1312; // @[RegisterRouter.scala:87:24] wire _out_T_12593 = ~out_romask_1312; // @[RegisterRouter.scala:87:24] wire _out_T_12594 = ~out_womask_1312; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1128 = {programBufferMem_59, _out_prepend_T_1128}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12595 = out_prepend_1128; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12596 = _out_T_12595; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1129 = _out_T_12596; // @[RegisterRouter.scala:87:24] wire out_rimask_1313 = \|_out_rimask_T_1313; // @[RegisterRouter.scala:87:24] wire out_wimask_1313 = &_out_wimask_T_1313; // @[RegisterRouter.scala:87:24] wire out_romask_1313 = \|_out_romask_T_1313; // @[RegisterRouter.scala:87:24] wire out_womask_1313 = &_out_womask_T_1313; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1313 = out_rivalid_1_1167 & out_rimask_1313; // @[RegisterRouter.scala:87:24] wire _out_T_12598 = out_f_rivalid_1313; // @[RegisterRouter.scala:87:24] wire out_f_roready_1313 = out_roready_1_1167 & out_romask_1313; // @[RegisterRouter.scala:87:24] wire _out_T_12599 = out_f_roready_1313; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1313 = out_wivalid_1_1167 & out_wimask_1313; // @[RegisterRouter.scala:87:24] wire _out_T_12600 = out_f_wivalid_1313; // @[RegisterRouter.scala:87:24] wire out_f_woready_1313 = out_woready_1_1167 & out_womask_1313; // @[RegisterRouter.scala:87:24] wire _out_T_12601 = out_f_woready_1313; // @[RegisterRouter.scala:87:24] wire _out_T_12602 = ~out_rimask_1313; // @[RegisterRouter.scala:87:24] wire _out_T_12603 = ~out_wimask_1313; // @[RegisterRouter.scala:87:24] wire _out_T_12604 = ~out_romask_1313; // @[RegisterRouter.scala:87:24] wire _out_T_12605 = ~out_womask_1313; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1129 = {programBufferMem_60, _out_prepend_T_1129}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12606 = out_prepend_1129; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12607 = _out_T_12606; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1130 = _out_T_12607; // @[RegisterRouter.scala:87:24] wire out_rimask_1314 = \|_out_rimask_T_1314; // @[RegisterRouter.scala:87:24] wire out_wimask_1314 = &_out_wimask_T_1314; // @[RegisterRouter.scala:87:24] wire out_romask_1314 = \|_out_romask_T_1314; // @[RegisterRouter.scala:87:24] wire out_womask_1314 = &_out_womask_T_1314; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1314 = out_rivalid_1_1168 & out_rimask_1314; // @[RegisterRouter.scala:87:24] wire _out_T_12609 = out_f_rivalid_1314; // @[RegisterRouter.scala:87:24] wire out_f_roready_1314 = out_roready_1_1168 & out_romask_1314; // @[RegisterRouter.scala:87:24] wire _out_T_12610 = out_f_roready_1314; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1314 = out_wivalid_1_1168 & out_wimask_1314; // @[RegisterRouter.scala:87:24] wire _out_T_12611 = out_f_wivalid_1314; // @[RegisterRouter.scala:87:24] wire out_f_woready_1314 = out_woready_1_1168 & out_womask_1314; // @[RegisterRouter.scala:87:24] wire _out_T_12612 = out_f_woready_1314; // @[RegisterRouter.scala:87:24] wire _out_T_12613 = ~out_rimask_1314; // @[RegisterRouter.scala:87:24] wire _out_T_12614 = ~out_wimask_1314; // @[RegisterRouter.scala:87:24] wire _out_T_12615 = ~out_romask_1314; // @[RegisterRouter.scala:87:24] wire _out_T_12616 = ~out_womask_1314; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1130 = {programBufferMem_61, _out_prepend_T_1130}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12617 = out_prepend_1130; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12618 = _out_T_12617; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1131 = _out_T_12618; // @[RegisterRouter.scala:87:24] wire out_rimask_1315 = \|_out_rimask_T_1315; // @[RegisterRouter.scala:87:24] wire out_wimask_1315 = &_out_wimask_T_1315; // @[RegisterRouter.scala:87:24] wire out_romask_1315 = \|_out_romask_T_1315; // @[RegisterRouter.scala:87:24] wire out_womask_1315 = &_out_womask_T_1315; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1315 = out_rivalid_1_1169 & out_rimask_1315; // @[RegisterRouter.scala:87:24] wire _out_T_12620 = out_f_rivalid_1315; // @[RegisterRouter.scala:87:24] wire out_f_roready_1315 = out_roready_1_1169 & out_romask_1315; // @[RegisterRouter.scala:87:24] wire _out_T_12621 = out_f_roready_1315; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1315 = out_wivalid_1_1169 & out_wimask_1315; // @[RegisterRouter.scala:87:24] wire _out_T_12622 = out_f_wivalid_1315; // @[RegisterRouter.scala:87:24] wire out_f_woready_1315 = out_woready_1_1169 & out_womask_1315; // @[RegisterRouter.scala:87:24] wire _out_T_12623 = out_f_woready_1315; // @[RegisterRouter.scala:87:24] wire _out_T_12624 = ~out_rimask_1315; // @[RegisterRouter.scala:87:24] wire _out_T_12625 = ~out_wimask_1315; // @[RegisterRouter.scala:87:24] wire _out_T_12626 = ~out_romask_1315; // @[RegisterRouter.scala:87:24] wire _out_T_12627 = ~out_womask_1315; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1131 = {programBufferMem_62, _out_prepend_T_1131}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12628 = out_prepend_1131; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12629 = _out_T_12628; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1132 = _out_T_12629; // @[RegisterRouter.scala:87:24] wire out_rimask_1316 = \|_out_rimask_T_1316; // @[RegisterRouter.scala:87:24] wire out_wimask_1316 = &_out_wimask_T_1316; // @[RegisterRouter.scala:87:24] wire out_romask_1316 = \|_out_romask_T_1316; // @[RegisterRouter.scala:87:24] wire out_womask_1316 = &_out_womask_T_1316; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1316 = out_rivalid_1_1170 & out_rimask_1316; // @[RegisterRouter.scala:87:24] wire _out_T_12631 = out_f_rivalid_1316; // @[RegisterRouter.scala:87:24] wire out_f_roready_1316 = out_roready_1_1170 & out_romask_1316; // @[RegisterRouter.scala:87:24] wire _out_T_12632 = out_f_roready_1316; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1316 = out_wivalid_1_1170 & out_wimask_1316; // @[RegisterRouter.scala:87:24] wire _out_T_12633 = out_f_wivalid_1316; // @[RegisterRouter.scala:87:24] wire out_f_woready_1316 = out_woready_1_1170 & out_womask_1316; // @[RegisterRouter.scala:87:24] wire _out_T_12634 = out_f_woready_1316; // @[RegisterRouter.scala:87:24] wire _out_T_12635 = ~out_rimask_1316; // @[RegisterRouter.scala:87:24] wire _out_T_12636 = ~out_wimask_1316; // @[RegisterRouter.scala:87:24] wire _out_T_12637 = ~out_romask_1316; // @[RegisterRouter.scala:87:24] wire _out_T_12638 = ~out_womask_1316; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1132 = {programBufferMem_63, _out_prepend_T_1132}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12639 = out_prepend_1132; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12640 = _out_T_12639; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_111 = _out_T_12640; // @[MuxLiteral.scala:49:48] wire out_rimask_1317 = \|_out_rimask_T_1317; // @[RegisterRouter.scala:87:24] wire out_wimask_1317 = &_out_wimask_T_1317; // @[RegisterRouter.scala:87:24] wire out_romask_1317 = \|_out_romask_T_1317; // @[RegisterRouter.scala:87:24] wire out_womask_1317 = &_out_womask_T_1317; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1317 = out_rivalid_1_1171 & out_rimask_1317; // @[RegisterRouter.scala:87:24] wire _out_T_12642 = out_f_rivalid_1317; // @[RegisterRouter.scala:87:24] wire out_f_roready_1317 = out_roready_1_1171 & out_romask_1317; // @[RegisterRouter.scala:87:24] wire _out_T_12643 = out_f_roready_1317; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1317 = out_wivalid_1_1171 & out_wimask_1317; // @[RegisterRouter.scala:87:24] wire out_f_woready_1317 = out_woready_1_1171 & out_womask_1317; // @[RegisterRouter.scala:87:24] wire _out_T_12644 = ~out_rimask_1317; // @[RegisterRouter.scala:87:24] wire _out_T_12645 = ~out_wimask_1317; // @[RegisterRouter.scala:87:24] wire _out_T_12646 = ~out_romask_1317; // @[RegisterRouter.scala:87:24] wire _out_T_12647 = ~out_womask_1317; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12649 = _out_T_12648; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1133 = _out_T_12649; // @[RegisterRouter.scala:87:24] wire out_rimask_1318 = \|_out_rimask_T_1318; // @[RegisterRouter.scala:87:24] wire out_wimask_1318 = &_out_wimask_T_1318; // @[RegisterRouter.scala:87:24] wire out_romask_1318 = \|_out_romask_T_1318; // @[RegisterRouter.scala:87:24] wire out_womask_1318 = &_out_womask_T_1318; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1318 = out_rivalid_1_1172 & out_rimask_1318; // @[RegisterRouter.scala:87:24] wire _out_T_12651 = out_f_rivalid_1318; // @[RegisterRouter.scala:87:24] wire out_f_roready_1318 = out_roready_1_1172 & out_romask_1318; // @[RegisterRouter.scala:87:24] wire _out_T_12652 = out_f_roready_1318; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1318 = out_wivalid_1_1172 & out_wimask_1318; // @[RegisterRouter.scala:87:24] wire out_f_woready_1318 = out_woready_1_1172 & out_womask_1318; // @[RegisterRouter.scala:87:24] wire _out_T_12653 = ~out_rimask_1318; // @[RegisterRouter.scala:87:24] wire _out_T_12654 = ~out_wimask_1318; // @[RegisterRouter.scala:87:24] wire _out_T_12655 = ~out_romask_1318; // @[RegisterRouter.scala:87:24] wire _out_T_12656 = ~out_womask_1318; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1133 = {hi_698, flags_0_go, _out_prepend_T_1133}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12657 = out_prepend_1133; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12658 = _out_T_12657; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1134 = _out_T_12658; // @[RegisterRouter.scala:87:24] wire out_rimask_1319 = \|_out_rimask_T_1319; // @[RegisterRouter.scala:87:24] wire out_wimask_1319 = &_out_wimask_T_1319; // @[RegisterRouter.scala:87:24] wire out_romask_1319 = \|_out_romask_T_1319; // @[RegisterRouter.scala:87:24] wire out_womask_1319 = &_out_womask_T_1319; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1319 = out_rivalid_1_1173 & out_rimask_1319; // @[RegisterRouter.scala:87:24] wire _out_T_12660 = out_f_rivalid_1319; // @[RegisterRouter.scala:87:24] wire out_f_roready_1319 = out_roready_1_1173 & out_romask_1319; // @[RegisterRouter.scala:87:24] wire _out_T_12661 = out_f_roready_1319; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1319 = out_wivalid_1_1173 & out_wimask_1319; // @[RegisterRouter.scala:87:24] wire out_f_woready_1319 = out_woready_1_1173 & out_womask_1319; // @[RegisterRouter.scala:87:24] wire _out_T_12662 = ~out_rimask_1319; // @[RegisterRouter.scala:87:24] wire _out_T_12663 = ~out_wimask_1319; // @[RegisterRouter.scala:87:24] wire _out_T_12664 = ~out_romask_1319; // @[RegisterRouter.scala:87:24] wire _out_T_12665 = ~out_womask_1319; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1134 = {hi_699, flags_0_go, _out_prepend_T_1134}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12666 = out_prepend_1134; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12667 = _out_T_12666; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1135 = _out_T_12667; // @[RegisterRouter.scala:87:24] wire out_rimask_1320 = \|_out_rimask_T_1320; // @[RegisterRouter.scala:87:24] wire out_wimask_1320 = &_out_wimask_T_1320; // @[RegisterRouter.scala:87:24] wire out_romask_1320 = \|_out_romask_T_1320; // @[RegisterRouter.scala:87:24] wire out_womask_1320 = &_out_womask_T_1320; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1320 = out_rivalid_1_1174 & out_rimask_1320; // @[RegisterRouter.scala:87:24] wire _out_T_12669 = out_f_rivalid_1320; // @[RegisterRouter.scala:87:24] wire out_f_roready_1320 = out_roready_1_1174 & out_romask_1320; // @[RegisterRouter.scala:87:24] wire _out_T_12670 = out_f_roready_1320; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1320 = out_wivalid_1_1174 & out_wimask_1320; // @[RegisterRouter.scala:87:24] wire out_f_woready_1320 = out_woready_1_1174 & out_womask_1320; // @[RegisterRouter.scala:87:24] wire _out_T_12671 = ~out_rimask_1320; // @[RegisterRouter.scala:87:24] wire _out_T_12672 = ~out_wimask_1320; // @[RegisterRouter.scala:87:24] wire _out_T_12673 = ~out_romask_1320; // @[RegisterRouter.scala:87:24] wire _out_T_12674 = ~out_womask_1320; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1135 = {hi_700, flags_0_go, _out_prepend_T_1135}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12675 = out_prepend_1135; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12676 = _out_T_12675; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1136 = _out_T_12676; // @[RegisterRouter.scala:87:24] wire out_rimask_1321 = \|_out_rimask_T_1321; // @[RegisterRouter.scala:87:24] wire out_wimask_1321 = &_out_wimask_T_1321; // @[RegisterRouter.scala:87:24] wire out_romask_1321 = \|_out_romask_T_1321; // @[RegisterRouter.scala:87:24] wire out_womask_1321 = &_out_womask_T_1321; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1321 = out_rivalid_1_1175 & out_rimask_1321; // @[RegisterRouter.scala:87:24] wire _out_T_12678 = out_f_rivalid_1321; // @[RegisterRouter.scala:87:24] wire out_f_roready_1321 = out_roready_1_1175 & out_romask_1321; // @[RegisterRouter.scala:87:24] wire _out_T_12679 = out_f_roready_1321; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1321 = out_wivalid_1_1175 & out_wimask_1321; // @[RegisterRouter.scala:87:24] wire out_f_woready_1321 = out_woready_1_1175 & out_womask_1321; // @[RegisterRouter.scala:87:24] wire _out_T_12680 = ~out_rimask_1321; // @[RegisterRouter.scala:87:24] wire _out_T_12681 = ~out_wimask_1321; // @[RegisterRouter.scala:87:24] wire _out_T_12682 = ~out_romask_1321; // @[RegisterRouter.scala:87:24] wire _out_T_12683 = ~out_womask_1321; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1136 = {hi_701, flags_0_go, _out_prepend_T_1136}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12684 = out_prepend_1136; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12685 = _out_T_12684; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1137 = _out_T_12685; // @[RegisterRouter.scala:87:24] wire out_rimask_1322 = \|_out_rimask_T_1322; // @[RegisterRouter.scala:87:24] wire out_wimask_1322 = &_out_wimask_T_1322; // @[RegisterRouter.scala:87:24] wire out_romask_1322 = \|_out_romask_T_1322; // @[RegisterRouter.scala:87:24] wire out_womask_1322 = &_out_womask_T_1322; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1322 = out_rivalid_1_1176 & out_rimask_1322; // @[RegisterRouter.scala:87:24] wire _out_T_12687 = out_f_rivalid_1322; // @[RegisterRouter.scala:87:24] wire out_f_roready_1322 = out_roready_1_1176 & out_romask_1322; // @[RegisterRouter.scala:87:24] wire _out_T_12688 = out_f_roready_1322; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1322 = out_wivalid_1_1176 & out_wimask_1322; // @[RegisterRouter.scala:87:24] wire out_f_woready_1322 = out_woready_1_1176 & out_womask_1322; // @[RegisterRouter.scala:87:24] wire _out_T_12689 = ~out_rimask_1322; // @[RegisterRouter.scala:87:24] wire _out_T_12690 = ~out_wimask_1322; // @[RegisterRouter.scala:87:24] wire _out_T_12691 = ~out_romask_1322; // @[RegisterRouter.scala:87:24] wire _out_T_12692 = ~out_womask_1322; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1137 = {hi_702, flags_0_go, _out_prepend_T_1137}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12693 = out_prepend_1137; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12694 = _out_T_12693; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1138 = _out_T_12694; // @[RegisterRouter.scala:87:24] wire out_rimask_1323 = \|_out_rimask_T_1323; // @[RegisterRouter.scala:87:24] wire out_wimask_1323 = &_out_wimask_T_1323; // @[RegisterRouter.scala:87:24] wire out_romask_1323 = \|_out_romask_T_1323; // @[RegisterRouter.scala:87:24] wire out_womask_1323 = &_out_womask_T_1323; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1323 = out_rivalid_1_1177 & out_rimask_1323; // @[RegisterRouter.scala:87:24] wire _out_T_12696 = out_f_rivalid_1323; // @[RegisterRouter.scala:87:24] wire out_f_roready_1323 = out_roready_1_1177 & out_romask_1323; // @[RegisterRouter.scala:87:24] wire _out_T_12697 = out_f_roready_1323; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1323 = out_wivalid_1_1177 & out_wimask_1323; // @[RegisterRouter.scala:87:24] wire out_f_woready_1323 = out_woready_1_1177 & out_womask_1323; // @[RegisterRouter.scala:87:24] wire _out_T_12698 = ~out_rimask_1323; // @[RegisterRouter.scala:87:24] wire _out_T_12699 = ~out_wimask_1323; // @[RegisterRouter.scala:87:24] wire _out_T_12700 = ~out_romask_1323; // @[RegisterRouter.scala:87:24] wire _out_T_12701 = ~out_womask_1323; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1138 = {hi_703, flags_0_go, _out_prepend_T_1138}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12702 = out_prepend_1138; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12703 = _out_T_12702; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1139 = _out_T_12703; // @[RegisterRouter.scala:87:24] wire out_rimask_1324 = \|_out_rimask_T_1324; // @[RegisterRouter.scala:87:24] wire out_wimask_1324 = &_out_wimask_T_1324; // @[RegisterRouter.scala:87:24] wire out_romask_1324 = \|_out_romask_T_1324; // @[RegisterRouter.scala:87:24] wire out_womask_1324 = &_out_womask_T_1324; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1324 = out_rivalid_1_1178 & out_rimask_1324; // @[RegisterRouter.scala:87:24] wire _out_T_12705 = out_f_rivalid_1324; // @[RegisterRouter.scala:87:24] wire out_f_roready_1324 = out_roready_1_1178 & out_romask_1324; // @[RegisterRouter.scala:87:24] wire _out_T_12706 = out_f_roready_1324; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1324 = out_wivalid_1_1178 & out_wimask_1324; // @[RegisterRouter.scala:87:24] wire out_f_woready_1324 = out_woready_1_1178 & out_womask_1324; // @[RegisterRouter.scala:87:24] wire _out_T_12707 = ~out_rimask_1324; // @[RegisterRouter.scala:87:24] wire _out_T_12708 = ~out_wimask_1324; // @[RegisterRouter.scala:87:24] wire _out_T_12709 = ~out_romask_1324; // @[RegisterRouter.scala:87:24] wire _out_T_12710 = ~out_womask_1324; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1139 = {hi_704, flags_0_go, _out_prepend_T_1139}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12711 = out_prepend_1139; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12712 = _out_T_12711; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_215 = _out_T_12712; // @[MuxLiteral.scala:49:48] wire out_rimask_1325 = \|_out_rimask_T_1325; // @[RegisterRouter.scala:87:24] wire out_wimask_1325 = &_out_wimask_T_1325; // @[RegisterRouter.scala:87:24] wire out_romask_1325 = \|_out_romask_T_1325; // @[RegisterRouter.scala:87:24] wire out_womask_1325 = &_out_womask_T_1325; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1325 = out_rivalid_1_1179 & out_rimask_1325; // @[RegisterRouter.scala:87:24] wire _out_T_12714 = out_f_rivalid_1325; // @[RegisterRouter.scala:87:24] wire out_f_roready_1325 = out_roready_1_1179 & out_romask_1325; // @[RegisterRouter.scala:87:24] wire _out_T_12715 = out_f_roready_1325; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1325 = out_wivalid_1_1179 & out_wimask_1325; // @[RegisterRouter.scala:87:24] wire out_f_woready_1325 = out_woready_1_1179 & out_womask_1325; // @[RegisterRouter.scala:87:24] wire _out_T_12716 = ~out_rimask_1325; // @[RegisterRouter.scala:87:24] wire _out_T_12717 = ~out_wimask_1325; // @[RegisterRouter.scala:87:24] wire _out_T_12718 = ~out_romask_1325; // @[RegisterRouter.scala:87:24] wire _out_T_12719 = ~out_womask_1325; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12721 = _out_T_12720; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1140 = _out_T_12721; // @[RegisterRouter.scala:87:24] wire out_rimask_1326 = \|_out_rimask_T_1326; // @[RegisterRouter.scala:87:24] wire out_wimask_1326 = &_out_wimask_T_1326; // @[RegisterRouter.scala:87:24] wire out_romask_1326 = \|_out_romask_T_1326; // @[RegisterRouter.scala:87:24] wire out_womask_1326 = &_out_womask_T_1326; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1326 = out_rivalid_1_1180 & out_rimask_1326; // @[RegisterRouter.scala:87:24] wire _out_T_12723 = out_f_rivalid_1326; // @[RegisterRouter.scala:87:24] wire out_f_roready_1326 = out_roready_1_1180 & out_romask_1326; // @[RegisterRouter.scala:87:24] wire _out_T_12724 = out_f_roready_1326; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1326 = out_wivalid_1_1180 & out_wimask_1326; // @[RegisterRouter.scala:87:24] wire out_f_woready_1326 = out_woready_1_1180 & out_womask_1326; // @[RegisterRouter.scala:87:24] wire _out_T_12725 = ~out_rimask_1326; // @[RegisterRouter.scala:87:24] wire _out_T_12726 = ~out_wimask_1326; // @[RegisterRouter.scala:87:24] wire _out_T_12727 = ~out_romask_1326; // @[RegisterRouter.scala:87:24] wire _out_T_12728 = ~out_womask_1326; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1140 = {hi_754, flags_0_go, _out_prepend_T_1140}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12729 = out_prepend_1140; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12730 = _out_T_12729; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1141 = _out_T_12730; // @[RegisterRouter.scala:87:24] wire out_rimask_1327 = \|_out_rimask_T_1327; // @[RegisterRouter.scala:87:24] wire out_wimask_1327 = &_out_wimask_T_1327; // @[RegisterRouter.scala:87:24] wire out_romask_1327 = \|_out_romask_T_1327; // @[RegisterRouter.scala:87:24] wire out_womask_1327 = &_out_womask_T_1327; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1327 = out_rivalid_1_1181 & out_rimask_1327; // @[RegisterRouter.scala:87:24] wire _out_T_12732 = out_f_rivalid_1327; // @[RegisterRouter.scala:87:24] wire out_f_roready_1327 = out_roready_1_1181 & out_romask_1327; // @[RegisterRouter.scala:87:24] wire _out_T_12733 = out_f_roready_1327; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1327 = out_wivalid_1_1181 & out_wimask_1327; // @[RegisterRouter.scala:87:24] wire out_f_woready_1327 = out_woready_1_1181 & out_womask_1327; // @[RegisterRouter.scala:87:24] wire _out_T_12734 = ~out_rimask_1327; // @[RegisterRouter.scala:87:24] wire _out_T_12735 = ~out_wimask_1327; // @[RegisterRouter.scala:87:24] wire _out_T_12736 = ~out_romask_1327; // @[RegisterRouter.scala:87:24] wire _out_T_12737 = ~out_womask_1327; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1141 = {hi_755, flags_0_go, _out_prepend_T_1141}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12738 = out_prepend_1141; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12739 = _out_T_12738; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1142 = _out_T_12739; // @[RegisterRouter.scala:87:24] wire out_rimask_1328 = \|_out_rimask_T_1328; // @[RegisterRouter.scala:87:24] wire out_wimask_1328 = &_out_wimask_T_1328; // @[RegisterRouter.scala:87:24] wire out_romask_1328 = \|_out_romask_T_1328; // @[RegisterRouter.scala:87:24] wire out_womask_1328 = &_out_womask_T_1328; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1328 = out_rivalid_1_1182 & out_rimask_1328; // @[RegisterRouter.scala:87:24] wire _out_T_12741 = out_f_rivalid_1328; // @[RegisterRouter.scala:87:24] wire out_f_roready_1328 = out_roready_1_1182 & out_romask_1328; // @[RegisterRouter.scala:87:24] wire _out_T_12742 = out_f_roready_1328; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1328 = out_wivalid_1_1182 & out_wimask_1328; // @[RegisterRouter.scala:87:24] wire out_f_woready_1328 = out_woready_1_1182 & out_womask_1328; // @[RegisterRouter.scala:87:24] wire _out_T_12743 = ~out_rimask_1328; // @[RegisterRouter.scala:87:24] wire _out_T_12744 = ~out_wimask_1328; // @[RegisterRouter.scala:87:24] wire _out_T_12745 = ~out_romask_1328; // @[RegisterRouter.scala:87:24] wire _out_T_12746 = ~out_womask_1328; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1142 = {hi_756, flags_0_go, _out_prepend_T_1142}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12747 = out_prepend_1142; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12748 = _out_T_12747; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1143 = _out_T_12748; // @[RegisterRouter.scala:87:24] wire out_rimask_1329 = \|_out_rimask_T_1329; // @[RegisterRouter.scala:87:24] wire out_wimask_1329 = &_out_wimask_T_1329; // @[RegisterRouter.scala:87:24] wire out_romask_1329 = \|_out_romask_T_1329; // @[RegisterRouter.scala:87:24] wire out_womask_1329 = &_out_womask_T_1329; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1329 = out_rivalid_1_1183 & out_rimask_1329; // @[RegisterRouter.scala:87:24] wire _out_T_12750 = out_f_rivalid_1329; // @[RegisterRouter.scala:87:24] wire out_f_roready_1329 = out_roready_1_1183 & out_romask_1329; // @[RegisterRouter.scala:87:24] wire _out_T_12751 = out_f_roready_1329; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1329 = out_wivalid_1_1183 & out_wimask_1329; // @[RegisterRouter.scala:87:24] wire out_f_woready_1329 = out_woready_1_1183 & out_womask_1329; // @[RegisterRouter.scala:87:24] wire _out_T_12752 = ~out_rimask_1329; // @[RegisterRouter.scala:87:24] wire _out_T_12753 = ~out_wimask_1329; // @[RegisterRouter.scala:87:24] wire _out_T_12754 = ~out_romask_1329; // @[RegisterRouter.scala:87:24] wire _out_T_12755 = ~out_womask_1329; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1143 = {hi_757, flags_0_go, _out_prepend_T_1143}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12756 = out_prepend_1143; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12757 = _out_T_12756; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1144 = _out_T_12757; // @[RegisterRouter.scala:87:24] wire out_rimask_1330 = \|_out_rimask_T_1330; // @[RegisterRouter.scala:87:24] wire out_wimask_1330 = &_out_wimask_T_1330; // @[RegisterRouter.scala:87:24] wire out_romask_1330 = \|_out_romask_T_1330; // @[RegisterRouter.scala:87:24] wire out_womask_1330 = &_out_womask_T_1330; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1330 = out_rivalid_1_1184 & out_rimask_1330; // @[RegisterRouter.scala:87:24] wire _out_T_12759 = out_f_rivalid_1330; // @[RegisterRouter.scala:87:24] wire out_f_roready_1330 = out_roready_1_1184 & out_romask_1330; // @[RegisterRouter.scala:87:24] wire _out_T_12760 = out_f_roready_1330; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1330 = out_wivalid_1_1184 & out_wimask_1330; // @[RegisterRouter.scala:87:24] wire out_f_woready_1330 = out_woready_1_1184 & out_womask_1330; // @[RegisterRouter.scala:87:24] wire _out_T_12761 = ~out_rimask_1330; // @[RegisterRouter.scala:87:24] wire _out_T_12762 = ~out_wimask_1330; // @[RegisterRouter.scala:87:24] wire _out_T_12763 = ~out_romask_1330; // @[RegisterRouter.scala:87:24] wire _out_T_12764 = ~out_womask_1330; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1144 = {hi_758, flags_0_go, _out_prepend_T_1144}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12765 = out_prepend_1144; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12766 = _out_T_12765; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1145 = _out_T_12766; // @[RegisterRouter.scala:87:24] wire out_rimask_1331 = \|_out_rimask_T_1331; // @[RegisterRouter.scala:87:24] wire out_wimask_1331 = &_out_wimask_T_1331; // @[RegisterRouter.scala:87:24] wire out_romask_1331 = \|_out_romask_T_1331; // @[RegisterRouter.scala:87:24] wire out_womask_1331 = &_out_womask_T_1331; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1331 = out_rivalid_1_1185 & out_rimask_1331; // @[RegisterRouter.scala:87:24] wire _out_T_12768 = out_f_rivalid_1331; // @[RegisterRouter.scala:87:24] wire out_f_roready_1331 = out_roready_1_1185 & out_romask_1331; // @[RegisterRouter.scala:87:24] wire _out_T_12769 = out_f_roready_1331; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1331 = out_wivalid_1_1185 & out_wimask_1331; // @[RegisterRouter.scala:87:24] wire out_f_woready_1331 = out_woready_1_1185 & out_womask_1331; // @[RegisterRouter.scala:87:24] wire _out_T_12770 = ~out_rimask_1331; // @[RegisterRouter.scala:87:24] wire _out_T_12771 = ~out_wimask_1331; // @[RegisterRouter.scala:87:24] wire _out_T_12772 = ~out_romask_1331; // @[RegisterRouter.scala:87:24] wire _out_T_12773 = ~out_womask_1331; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1145 = {hi_759, flags_0_go, _out_prepend_T_1145}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12774 = out_prepend_1145; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12775 = _out_T_12774; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1146 = _out_T_12775; // @[RegisterRouter.scala:87:24] wire out_rimask_1332 = \|_out_rimask_T_1332; // @[RegisterRouter.scala:87:24] wire out_wimask_1332 = &_out_wimask_T_1332; // @[RegisterRouter.scala:87:24] wire out_romask_1332 = \|_out_romask_T_1332; // @[RegisterRouter.scala:87:24] wire out_womask_1332 = &_out_womask_T_1332; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1332 = out_rivalid_1_1186 & out_rimask_1332; // @[RegisterRouter.scala:87:24] wire _out_T_12777 = out_f_rivalid_1332; // @[RegisterRouter.scala:87:24] wire out_f_roready_1332 = out_roready_1_1186 & out_romask_1332; // @[RegisterRouter.scala:87:24] wire _out_T_12778 = out_f_roready_1332; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1332 = out_wivalid_1_1186 & out_wimask_1332; // @[RegisterRouter.scala:87:24] wire out_f_woready_1332 = out_woready_1_1186 & out_womask_1332; // @[RegisterRouter.scala:87:24] wire _out_T_12779 = ~out_rimask_1332; // @[RegisterRouter.scala:87:24] wire _out_T_12780 = ~out_wimask_1332; // @[RegisterRouter.scala:87:24] wire _out_T_12781 = ~out_romask_1332; // @[RegisterRouter.scala:87:24] wire _out_T_12782 = ~out_womask_1332; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1146 = {hi_760, flags_0_go, _out_prepend_T_1146}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12783 = out_prepend_1146; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12784 = _out_T_12783; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_222 = _out_T_12784; // @[MuxLiteral.scala:49:48] wire out_rimask_1333 = \|_out_rimask_T_1333; // @[RegisterRouter.scala:87:24] wire out_wimask_1333 = &_out_wimask_T_1333; // @[RegisterRouter.scala:87:24] wire out_romask_1333 = \|_out_romask_T_1333; // @[RegisterRouter.scala:87:24] wire out_womask_1333 = &_out_womask_T_1333; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1333 = out_rivalid_1_1187 & out_rimask_1333; // @[RegisterRouter.scala:87:24] wire _out_T_12786 = out_f_rivalid_1333; // @[RegisterRouter.scala:87:24] wire out_f_roready_1333 = out_roready_1_1187 & out_romask_1333; // @[RegisterRouter.scala:87:24] wire _out_T_12787 = out_f_roready_1333; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1333 = out_wivalid_1_1187 & out_wimask_1333; // @[RegisterRouter.scala:87:24] wire out_f_woready_1333 = out_woready_1_1187 & out_womask_1333; // @[RegisterRouter.scala:87:24] wire _out_T_12788 = ~out_rimask_1333; // @[RegisterRouter.scala:87:24] wire _out_T_12789 = ~out_wimask_1333; // @[RegisterRouter.scala:87:24] wire _out_T_12790 = ~out_romask_1333; // @[RegisterRouter.scala:87:24] wire _out_T_12791 = ~out_womask_1333; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12793 = _out_T_12792; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1147 = _out_T_12793; // @[RegisterRouter.scala:87:24] wire out_rimask_1334 = \|_out_rimask_T_1334; // @[RegisterRouter.scala:87:24] wire out_wimask_1334 = &_out_wimask_T_1334; // @[RegisterRouter.scala:87:24] wire out_romask_1334 = \|_out_romask_T_1334; // @[RegisterRouter.scala:87:24] wire out_womask_1334 = &_out_womask_T_1334; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1334 = out_rivalid_1_1188 & out_rimask_1334; // @[RegisterRouter.scala:87:24] wire _out_T_12795 = out_f_rivalid_1334; // @[RegisterRouter.scala:87:24] wire out_f_roready_1334 = out_roready_1_1188 & out_romask_1334; // @[RegisterRouter.scala:87:24] wire _out_T_12796 = out_f_roready_1334; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1334 = out_wivalid_1_1188 & out_wimask_1334; // @[RegisterRouter.scala:87:24] wire out_f_woready_1334 = out_woready_1_1188 & out_womask_1334; // @[RegisterRouter.scala:87:24] wire _out_T_12797 = ~out_rimask_1334; // @[RegisterRouter.scala:87:24] wire _out_T_12798 = ~out_wimask_1334; // @[RegisterRouter.scala:87:24] wire _out_T_12799 = ~out_romask_1334; // @[RegisterRouter.scala:87:24] wire _out_T_12800 = ~out_womask_1334; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1147 = {hi_834, flags_0_go, _out_prepend_T_1147}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12801 = out_prepend_1147; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12802 = _out_T_12801; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1148 = _out_T_12802; // @[RegisterRouter.scala:87:24] wire out_rimask_1335 = \|_out_rimask_T_1335; // @[RegisterRouter.scala:87:24] wire out_wimask_1335 = &_out_wimask_T_1335; // @[RegisterRouter.scala:87:24] wire out_romask_1335 = \|_out_romask_T_1335; // @[RegisterRouter.scala:87:24] wire out_womask_1335 = &_out_womask_T_1335; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1335 = out_rivalid_1_1189 & out_rimask_1335; // @[RegisterRouter.scala:87:24] wire _out_T_12804 = out_f_rivalid_1335; // @[RegisterRouter.scala:87:24] wire out_f_roready_1335 = out_roready_1_1189 & out_romask_1335; // @[RegisterRouter.scala:87:24] wire _out_T_12805 = out_f_roready_1335; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1335 = out_wivalid_1_1189 & out_wimask_1335; // @[RegisterRouter.scala:87:24] wire out_f_woready_1335 = out_woready_1_1189 & out_womask_1335; // @[RegisterRouter.scala:87:24] wire _out_T_12806 = ~out_rimask_1335; // @[RegisterRouter.scala:87:24] wire _out_T_12807 = ~out_wimask_1335; // @[RegisterRouter.scala:87:24] wire _out_T_12808 = ~out_romask_1335; // @[RegisterRouter.scala:87:24] wire _out_T_12809 = ~out_womask_1335; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1148 = {hi_835, flags_0_go, _out_prepend_T_1148}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12810 = out_prepend_1148; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12811 = _out_T_12810; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1149 = _out_T_12811; // @[RegisterRouter.scala:87:24] wire out_rimask_1336 = \|_out_rimask_T_1336; // @[RegisterRouter.scala:87:24] wire out_wimask_1336 = &_out_wimask_T_1336; // @[RegisterRouter.scala:87:24] wire out_romask_1336 = \|_out_romask_T_1336; // @[RegisterRouter.scala:87:24] wire out_womask_1336 = &_out_womask_T_1336; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1336 = out_rivalid_1_1190 & out_rimask_1336; // @[RegisterRouter.scala:87:24] wire _out_T_12813 = out_f_rivalid_1336; // @[RegisterRouter.scala:87:24] wire out_f_roready_1336 = out_roready_1_1190 & out_romask_1336; // @[RegisterRouter.scala:87:24] wire _out_T_12814 = out_f_roready_1336; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1336 = out_wivalid_1_1190 & out_wimask_1336; // @[RegisterRouter.scala:87:24] wire out_f_woready_1336 = out_woready_1_1190 & out_womask_1336; // @[RegisterRouter.scala:87:24] wire _out_T_12815 = ~out_rimask_1336; // @[RegisterRouter.scala:87:24] wire _out_T_12816 = ~out_wimask_1336; // @[RegisterRouter.scala:87:24] wire _out_T_12817 = ~out_romask_1336; // @[RegisterRouter.scala:87:24] wire _out_T_12818 = ~out_womask_1336; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1149 = {hi_836, flags_0_go, _out_prepend_T_1149}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12819 = out_prepend_1149; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12820 = _out_T_12819; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1150 = _out_T_12820; // @[RegisterRouter.scala:87:24] wire out_rimask_1337 = \|_out_rimask_T_1337; // @[RegisterRouter.scala:87:24] wire out_wimask_1337 = &_out_wimask_T_1337; // @[RegisterRouter.scala:87:24] wire out_romask_1337 = \|_out_romask_T_1337; // @[RegisterRouter.scala:87:24] wire out_womask_1337 = &_out_womask_T_1337; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1337 = out_rivalid_1_1191 & out_rimask_1337; // @[RegisterRouter.scala:87:24] wire _out_T_12822 = out_f_rivalid_1337; // @[RegisterRouter.scala:87:24] wire out_f_roready_1337 = out_roready_1_1191 & out_romask_1337; // @[RegisterRouter.scala:87:24] wire _out_T_12823 = out_f_roready_1337; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1337 = out_wivalid_1_1191 & out_wimask_1337; // @[RegisterRouter.scala:87:24] wire out_f_woready_1337 = out_woready_1_1191 & out_womask_1337; // @[RegisterRouter.scala:87:24] wire _out_T_12824 = ~out_rimask_1337; // @[RegisterRouter.scala:87:24] wire _out_T_12825 = ~out_wimask_1337; // @[RegisterRouter.scala:87:24] wire _out_T_12826 = ~out_romask_1337; // @[RegisterRouter.scala:87:24] wire _out_T_12827 = ~out_womask_1337; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1150 = {hi_837, flags_0_go, _out_prepend_T_1150}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12828 = out_prepend_1150; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12829 = _out_T_12828; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1151 = _out_T_12829; // @[RegisterRouter.scala:87:24] wire out_rimask_1338 = \|_out_rimask_T_1338; // @[RegisterRouter.scala:87:24] wire out_wimask_1338 = &_out_wimask_T_1338; // @[RegisterRouter.scala:87:24] wire out_romask_1338 = \|_out_romask_T_1338; // @[RegisterRouter.scala:87:24] wire out_womask_1338 = &_out_womask_T_1338; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1338 = out_rivalid_1_1192 & out_rimask_1338; // @[RegisterRouter.scala:87:24] wire _out_T_12831 = out_f_rivalid_1338; // @[RegisterRouter.scala:87:24] wire out_f_roready_1338 = out_roready_1_1192 & out_romask_1338; // @[RegisterRouter.scala:87:24] wire _out_T_12832 = out_f_roready_1338; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1338 = out_wivalid_1_1192 & out_wimask_1338; // @[RegisterRouter.scala:87:24] wire out_f_woready_1338 = out_woready_1_1192 & out_womask_1338; // @[RegisterRouter.scala:87:24] wire _out_T_12833 = ~out_rimask_1338; // @[RegisterRouter.scala:87:24] wire _out_T_12834 = ~out_wimask_1338; // @[RegisterRouter.scala:87:24] wire _out_T_12835 = ~out_romask_1338; // @[RegisterRouter.scala:87:24] wire _out_T_12836 = ~out_womask_1338; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1151 = {hi_838, flags_0_go, _out_prepend_T_1151}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12837 = out_prepend_1151; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12838 = _out_T_12837; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1152 = _out_T_12838; // @[RegisterRouter.scala:87:24] wire out_rimask_1339 = \|_out_rimask_T_1339; // @[RegisterRouter.scala:87:24] wire out_wimask_1339 = &_out_wimask_T_1339; // @[RegisterRouter.scala:87:24] wire out_romask_1339 = \|_out_romask_T_1339; // @[RegisterRouter.scala:87:24] wire out_womask_1339 = &_out_womask_T_1339; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1339 = out_rivalid_1_1193 & out_rimask_1339; // @[RegisterRouter.scala:87:24] wire _out_T_12840 = out_f_rivalid_1339; // @[RegisterRouter.scala:87:24] wire out_f_roready_1339 = out_roready_1_1193 & out_romask_1339; // @[RegisterRouter.scala:87:24] wire _out_T_12841 = out_f_roready_1339; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1339 = out_wivalid_1_1193 & out_wimask_1339; // @[RegisterRouter.scala:87:24] wire out_f_woready_1339 = out_woready_1_1193 & out_womask_1339; // @[RegisterRouter.scala:87:24] wire _out_T_12842 = ~out_rimask_1339; // @[RegisterRouter.scala:87:24] wire _out_T_12843 = ~out_wimask_1339; // @[RegisterRouter.scala:87:24] wire _out_T_12844 = ~out_romask_1339; // @[RegisterRouter.scala:87:24] wire _out_T_12845 = ~out_womask_1339; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1152 = {hi_839, flags_0_go, _out_prepend_T_1152}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12846 = out_prepend_1152; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12847 = _out_T_12846; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1153 = _out_T_12847; // @[RegisterRouter.scala:87:24] wire out_rimask_1340 = \|_out_rimask_T_1340; // @[RegisterRouter.scala:87:24] wire out_wimask_1340 = &_out_wimask_T_1340; // @[RegisterRouter.scala:87:24] wire out_romask_1340 = \|_out_romask_T_1340; // @[RegisterRouter.scala:87:24] wire out_womask_1340 = &_out_womask_T_1340; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1340 = out_rivalid_1_1194 & out_rimask_1340; // @[RegisterRouter.scala:87:24] wire _out_T_12849 = out_f_rivalid_1340; // @[RegisterRouter.scala:87:24] wire out_f_roready_1340 = out_roready_1_1194 & out_romask_1340; // @[RegisterRouter.scala:87:24] wire _out_T_12850 = out_f_roready_1340; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1340 = out_wivalid_1_1194 & out_wimask_1340; // @[RegisterRouter.scala:87:24] wire out_f_woready_1340 = out_woready_1_1194 & out_womask_1340; // @[RegisterRouter.scala:87:24] wire _out_T_12851 = ~out_rimask_1340; // @[RegisterRouter.scala:87:24] wire _out_T_12852 = ~out_wimask_1340; // @[RegisterRouter.scala:87:24] wire _out_T_12853 = ~out_romask_1340; // @[RegisterRouter.scala:87:24] wire _out_T_12854 = ~out_womask_1340; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1153 = {hi_840, flags_0_go, _out_prepend_T_1153}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12855 = out_prepend_1153; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12856 = _out_T_12855; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_232 = _out_T_12856; // @[MuxLiteral.scala:49:48] wire out_rimask_1341 = \|_out_rimask_T_1341; // @[RegisterRouter.scala:87:24] wire out_wimask_1341 = &_out_wimask_T_1341; // @[RegisterRouter.scala:87:24] wire out_romask_1341 = \|_out_romask_T_1341; // @[RegisterRouter.scala:87:24] wire out_womask_1341 = &_out_womask_T_1341; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1341 = out_rivalid_1_1195 & out_rimask_1341; // @[RegisterRouter.scala:87:24] wire _out_T_12858 = out_f_rivalid_1341; // @[RegisterRouter.scala:87:24] wire out_f_roready_1341 = out_roready_1_1195 & out_romask_1341; // @[RegisterRouter.scala:87:24] wire _out_T_12859 = out_f_roready_1341; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1341 = out_wivalid_1_1195 & out_wimask_1341; // @[RegisterRouter.scala:87:24] wire out_f_woready_1341 = out_woready_1_1195 & out_womask_1341; // @[RegisterRouter.scala:87:24] wire _out_T_12860 = ~out_rimask_1341; // @[RegisterRouter.scala:87:24] wire _out_T_12861 = ~out_wimask_1341; // @[RegisterRouter.scala:87:24] wire _out_T_12862 = ~out_romask_1341; // @[RegisterRouter.scala:87:24] wire _out_T_12863 = ~out_womask_1341; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12865 = _out_T_12864; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1154 = _out_T_12865; // @[RegisterRouter.scala:87:24] wire out_rimask_1342 = \|_out_rimask_T_1342; // @[RegisterRouter.scala:87:24] wire out_wimask_1342 = &_out_wimask_T_1342; // @[RegisterRouter.scala:87:24] wire out_romask_1342 = \|_out_romask_T_1342; // @[RegisterRouter.scala:87:24] wire out_womask_1342 = &_out_womask_T_1342; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1342 = out_rivalid_1_1196 & out_rimask_1342; // @[RegisterRouter.scala:87:24] wire _out_T_12867 = out_f_rivalid_1342; // @[RegisterRouter.scala:87:24] wire out_f_roready_1342 = out_roready_1_1196 & out_romask_1342; // @[RegisterRouter.scala:87:24] wire _out_T_12868 = out_f_roready_1342; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1342 = out_wivalid_1_1196 & out_wimask_1342; // @[RegisterRouter.scala:87:24] wire out_f_woready_1342 = out_woready_1_1196 & out_womask_1342; // @[RegisterRouter.scala:87:24] wire _out_T_12869 = ~out_rimask_1342; // @[RegisterRouter.scala:87:24] wire _out_T_12870 = ~out_wimask_1342; // @[RegisterRouter.scala:87:24] wire _out_T_12871 = ~out_romask_1342; // @[RegisterRouter.scala:87:24] wire _out_T_12872 = ~out_womask_1342; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1154 = {hi_1010, flags_0_go, _out_prepend_T_1154}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12873 = out_prepend_1154; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12874 = _out_T_12873; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1155 = _out_T_12874; // @[RegisterRouter.scala:87:24] wire out_rimask_1343 = \|_out_rimask_T_1343; // @[RegisterRouter.scala:87:24] wire out_wimask_1343 = &_out_wimask_T_1343; // @[RegisterRouter.scala:87:24] wire out_romask_1343 = \|_out_romask_T_1343; // @[RegisterRouter.scala:87:24] wire out_womask_1343 = &_out_womask_T_1343; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1343 = out_rivalid_1_1197 & out_rimask_1343; // @[RegisterRouter.scala:87:24] wire _out_T_12876 = out_f_rivalid_1343; // @[RegisterRouter.scala:87:24] wire out_f_roready_1343 = out_roready_1_1197 & out_romask_1343; // @[RegisterRouter.scala:87:24] wire _out_T_12877 = out_f_roready_1343; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1343 = out_wivalid_1_1197 & out_wimask_1343; // @[RegisterRouter.scala:87:24] wire out_f_woready_1343 = out_woready_1_1197 & out_womask_1343; // @[RegisterRouter.scala:87:24] wire _out_T_12878 = ~out_rimask_1343; // @[RegisterRouter.scala:87:24] wire _out_T_12879 = ~out_wimask_1343; // @[RegisterRouter.scala:87:24] wire _out_T_12880 = ~out_romask_1343; // @[RegisterRouter.scala:87:24] wire _out_T_12881 = ~out_womask_1343; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1155 = {hi_1011, flags_0_go, _out_prepend_T_1155}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12882 = out_prepend_1155; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12883 = _out_T_12882; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1156 = _out_T_12883; // @[RegisterRouter.scala:87:24] wire out_rimask_1344 = \|_out_rimask_T_1344; // @[RegisterRouter.scala:87:24] wire out_wimask_1344 = &_out_wimask_T_1344; // @[RegisterRouter.scala:87:24] wire out_romask_1344 = \|_out_romask_T_1344; // @[RegisterRouter.scala:87:24] wire out_womask_1344 = &_out_womask_T_1344; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1344 = out_rivalid_1_1198 & out_rimask_1344; // @[RegisterRouter.scala:87:24] wire _out_T_12885 = out_f_rivalid_1344; // @[RegisterRouter.scala:87:24] wire out_f_roready_1344 = out_roready_1_1198 & out_romask_1344; // @[RegisterRouter.scala:87:24] wire _out_T_12886 = out_f_roready_1344; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1344 = out_wivalid_1_1198 & out_wimask_1344; // @[RegisterRouter.scala:87:24] wire out_f_woready_1344 = out_woready_1_1198 & out_womask_1344; // @[RegisterRouter.scala:87:24] wire _out_T_12887 = ~out_rimask_1344; // @[RegisterRouter.scala:87:24] wire _out_T_12888 = ~out_wimask_1344; // @[RegisterRouter.scala:87:24] wire _out_T_12889 = ~out_romask_1344; // @[RegisterRouter.scala:87:24] wire _out_T_12890 = ~out_womask_1344; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1156 = {hi_1012, flags_0_go, _out_prepend_T_1156}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12891 = out_prepend_1156; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12892 = _out_T_12891; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1157 = _out_T_12892; // @[RegisterRouter.scala:87:24] wire out_rimask_1345 = \|_out_rimask_T_1345; // @[RegisterRouter.scala:87:24] wire out_wimask_1345 = &_out_wimask_T_1345; // @[RegisterRouter.scala:87:24] wire out_romask_1345 = \|_out_romask_T_1345; // @[RegisterRouter.scala:87:24] wire out_womask_1345 = &_out_womask_T_1345; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1345 = out_rivalid_1_1199 & out_rimask_1345; // @[RegisterRouter.scala:87:24] wire _out_T_12894 = out_f_rivalid_1345; // @[RegisterRouter.scala:87:24] wire out_f_roready_1345 = out_roready_1_1199 & out_romask_1345; // @[RegisterRouter.scala:87:24] wire _out_T_12895 = out_f_roready_1345; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1345 = out_wivalid_1_1199 & out_wimask_1345; // @[RegisterRouter.scala:87:24] wire out_f_woready_1345 = out_woready_1_1199 & out_womask_1345; // @[RegisterRouter.scala:87:24] wire _out_T_12896 = ~out_rimask_1345; // @[RegisterRouter.scala:87:24] wire _out_T_12897 = ~out_wimask_1345; // @[RegisterRouter.scala:87:24] wire _out_T_12898 = ~out_romask_1345; // @[RegisterRouter.scala:87:24] wire _out_T_12899 = ~out_womask_1345; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1157 = {hi_1013, flags_0_go, _out_prepend_T_1157}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12900 = out_prepend_1157; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12901 = _out_T_12900; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1158 = _out_T_12901; // @[RegisterRouter.scala:87:24] wire out_rimask_1346 = \|_out_rimask_T_1346; // @[RegisterRouter.scala:87:24] wire out_wimask_1346 = &_out_wimask_T_1346; // @[RegisterRouter.scala:87:24] wire out_romask_1346 = \|_out_romask_T_1346; // @[RegisterRouter.scala:87:24] wire out_womask_1346 = &_out_womask_T_1346; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1346 = out_rivalid_1_1200 & out_rimask_1346; // @[RegisterRouter.scala:87:24] wire _out_T_12903 = out_f_rivalid_1346; // @[RegisterRouter.scala:87:24] wire out_f_roready_1346 = out_roready_1_1200 & out_romask_1346; // @[RegisterRouter.scala:87:24] wire _out_T_12904 = out_f_roready_1346; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1346 = out_wivalid_1_1200 & out_wimask_1346; // @[RegisterRouter.scala:87:24] wire out_f_woready_1346 = out_woready_1_1200 & out_womask_1346; // @[RegisterRouter.scala:87:24] wire _out_T_12905 = ~out_rimask_1346; // @[RegisterRouter.scala:87:24] wire _out_T_12906 = ~out_wimask_1346; // @[RegisterRouter.scala:87:24] wire _out_T_12907 = ~out_romask_1346; // @[RegisterRouter.scala:87:24] wire _out_T_12908 = ~out_womask_1346; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1158 = {hi_1014, flags_0_go, _out_prepend_T_1158}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12909 = out_prepend_1158; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12910 = _out_T_12909; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1159 = _out_T_12910; // @[RegisterRouter.scala:87:24] wire out_rimask_1347 = \|_out_rimask_T_1347; // @[RegisterRouter.scala:87:24] wire out_wimask_1347 = &_out_wimask_T_1347; // @[RegisterRouter.scala:87:24] wire out_romask_1347 = \|_out_romask_T_1347; // @[RegisterRouter.scala:87:24] wire out_womask_1347 = &_out_womask_T_1347; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1347 = out_rivalid_1_1201 & out_rimask_1347; // @[RegisterRouter.scala:87:24] wire _out_T_12912 = out_f_rivalid_1347; // @[RegisterRouter.scala:87:24] wire out_f_roready_1347 = out_roready_1_1201 & out_romask_1347; // @[RegisterRouter.scala:87:24] wire _out_T_12913 = out_f_roready_1347; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1347 = out_wivalid_1_1201 & out_wimask_1347; // @[RegisterRouter.scala:87:24] wire out_f_woready_1347 = out_woready_1_1201 & out_womask_1347; // @[RegisterRouter.scala:87:24] wire _out_T_12914 = ~out_rimask_1347; // @[RegisterRouter.scala:87:24] wire _out_T_12915 = ~out_wimask_1347; // @[RegisterRouter.scala:87:24] wire _out_T_12916 = ~out_romask_1347; // @[RegisterRouter.scala:87:24] wire _out_T_12917 = ~out_womask_1347; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1159 = {hi_1015, flags_0_go, _out_prepend_T_1159}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12918 = out_prepend_1159; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12919 = _out_T_12918; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1160 = _out_T_12919; // @[RegisterRouter.scala:87:24] wire out_rimask_1348 = \|_out_rimask_T_1348; // @[RegisterRouter.scala:87:24] wire out_wimask_1348 = &_out_wimask_T_1348; // @[RegisterRouter.scala:87:24] wire out_romask_1348 = \|_out_romask_T_1348; // @[RegisterRouter.scala:87:24] wire out_womask_1348 = &_out_womask_T_1348; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1348 = out_rivalid_1_1202 & out_rimask_1348; // @[RegisterRouter.scala:87:24] wire _out_T_12921 = out_f_rivalid_1348; // @[RegisterRouter.scala:87:24] wire out_f_roready_1348 = out_roready_1_1202 & out_romask_1348; // @[RegisterRouter.scala:87:24] wire _out_T_12922 = out_f_roready_1348; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1348 = out_wivalid_1_1202 & out_wimask_1348; // @[RegisterRouter.scala:87:24] wire out_f_woready_1348 = out_woready_1_1202 & out_womask_1348; // @[RegisterRouter.scala:87:24] wire _out_T_12923 = ~out_rimask_1348; // @[RegisterRouter.scala:87:24] wire _out_T_12924 = ~out_wimask_1348; // @[RegisterRouter.scala:87:24] wire _out_T_12925 = ~out_romask_1348; // @[RegisterRouter.scala:87:24] wire _out_T_12926 = ~out_womask_1348; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1160 = {hi_1016, flags_0_go, _out_prepend_T_1160}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12927 = out_prepend_1160; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12928 = _out_T_12927; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_254 = _out_T_12928; // @[MuxLiteral.scala:49:48] wire out_rimask_1349 = \|_out_rimask_T_1349; // @[RegisterRouter.scala:87:24] wire out_wimask_1349 = &_out_wimask_T_1349; // @[RegisterRouter.scala:87:24] wire out_romask_1349 = \|_out_romask_T_1349; // @[RegisterRouter.scala:87:24] wire out_womask_1349 = &_out_womask_T_1349; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1349 = out_rivalid_1_1203 & out_rimask_1349; // @[RegisterRouter.scala:87:24] wire _out_T_12930 = out_f_rivalid_1349; // @[RegisterRouter.scala:87:24] wire out_f_roready_1349 = out_roready_1_1203 & out_romask_1349; // @[RegisterRouter.scala:87:24] wire _out_T_12931 = out_f_roready_1349; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1349 = out_wivalid_1_1203 & out_wimask_1349; // @[RegisterRouter.scala:87:24] wire out_f_woready_1349 = out_woready_1_1203 & out_womask_1349; // @[RegisterRouter.scala:87:24] wire _out_T_12932 = ~out_rimask_1349; // @[RegisterRouter.scala:87:24] wire _out_T_12933 = ~out_wimask_1349; // @[RegisterRouter.scala:87:24] wire _out_T_12934 = ~out_romask_1349; // @[RegisterRouter.scala:87:24] wire _out_T_12935 = ~out_womask_1349; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12937 = _out_T_12936; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1161 = _out_T_12937; // @[RegisterRouter.scala:87:24] wire out_rimask_1350 = \|_out_rimask_T_1350; // @[RegisterRouter.scala:87:24] wire out_wimask_1350 = &_out_wimask_T_1350; // @[RegisterRouter.scala:87:24] wire out_romask_1350 = \|_out_romask_T_1350; // @[RegisterRouter.scala:87:24] wire out_womask_1350 = &_out_womask_T_1350; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1350 = out_rivalid_1_1204 & out_rimask_1350; // @[RegisterRouter.scala:87:24] wire _out_T_12939 = out_f_rivalid_1350; // @[RegisterRouter.scala:87:24] wire out_f_roready_1350 = out_roready_1_1204 & out_romask_1350; // @[RegisterRouter.scala:87:24] wire _out_T_12940 = out_f_roready_1350; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1350 = out_wivalid_1_1204 & out_wimask_1350; // @[RegisterRouter.scala:87:24] wire out_f_woready_1350 = out_woready_1_1204 & out_womask_1350; // @[RegisterRouter.scala:87:24] wire _out_T_12941 = ~out_rimask_1350; // @[RegisterRouter.scala:87:24] wire _out_T_12942 = ~out_wimask_1350; // @[RegisterRouter.scala:87:24] wire _out_T_12943 = ~out_romask_1350; // @[RegisterRouter.scala:87:24] wire _out_T_12944 = ~out_womask_1350; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1161 = {hi_794, flags_0_go, _out_prepend_T_1161}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12945 = out_prepend_1161; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12946 = _out_T_12945; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1162 = _out_T_12946; // @[RegisterRouter.scala:87:24] wire out_rimask_1351 = \|_out_rimask_T_1351; // @[RegisterRouter.scala:87:24] wire out_wimask_1351 = &_out_wimask_T_1351; // @[RegisterRouter.scala:87:24] wire out_romask_1351 = \|_out_romask_T_1351; // @[RegisterRouter.scala:87:24] wire out_womask_1351 = &_out_womask_T_1351; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1351 = out_rivalid_1_1205 & out_rimask_1351; // @[RegisterRouter.scala:87:24] wire _out_T_12948 = out_f_rivalid_1351; // @[RegisterRouter.scala:87:24] wire out_f_roready_1351 = out_roready_1_1205 & out_romask_1351; // @[RegisterRouter.scala:87:24] wire _out_T_12949 = out_f_roready_1351; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1351 = out_wivalid_1_1205 & out_wimask_1351; // @[RegisterRouter.scala:87:24] wire out_f_woready_1351 = out_woready_1_1205 & out_womask_1351; // @[RegisterRouter.scala:87:24] wire _out_T_12950 = ~out_rimask_1351; // @[RegisterRouter.scala:87:24] wire _out_T_12951 = ~out_wimask_1351; // @[RegisterRouter.scala:87:24] wire _out_T_12952 = ~out_romask_1351; // @[RegisterRouter.scala:87:24] wire _out_T_12953 = ~out_womask_1351; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1162 = {hi_795, flags_0_go, _out_prepend_T_1162}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12954 = out_prepend_1162; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12955 = _out_T_12954; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1163 = _out_T_12955; // @[RegisterRouter.scala:87:24] wire out_rimask_1352 = \|_out_rimask_T_1352; // @[RegisterRouter.scala:87:24] wire out_wimask_1352 = &_out_wimask_T_1352; // @[RegisterRouter.scala:87:24] wire out_romask_1352 = \|_out_romask_T_1352; // @[RegisterRouter.scala:87:24] wire out_womask_1352 = &_out_womask_T_1352; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1352 = out_rivalid_1_1206 & out_rimask_1352; // @[RegisterRouter.scala:87:24] wire _out_T_12957 = out_f_rivalid_1352; // @[RegisterRouter.scala:87:24] wire out_f_roready_1352 = out_roready_1_1206 & out_romask_1352; // @[RegisterRouter.scala:87:24] wire _out_T_12958 = out_f_roready_1352; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1352 = out_wivalid_1_1206 & out_wimask_1352; // @[RegisterRouter.scala:87:24] wire out_f_woready_1352 = out_woready_1_1206 & out_womask_1352; // @[RegisterRouter.scala:87:24] wire _out_T_12959 = ~out_rimask_1352; // @[RegisterRouter.scala:87:24] wire _out_T_12960 = ~out_wimask_1352; // @[RegisterRouter.scala:87:24] wire _out_T_12961 = ~out_romask_1352; // @[RegisterRouter.scala:87:24] wire _out_T_12962 = ~out_womask_1352; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1163 = {hi_796, flags_0_go, _out_prepend_T_1163}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12963 = out_prepend_1163; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12964 = _out_T_12963; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1164 = _out_T_12964; // @[RegisterRouter.scala:87:24] wire out_rimask_1353 = \|_out_rimask_T_1353; // @[RegisterRouter.scala:87:24] wire out_wimask_1353 = &_out_wimask_T_1353; // @[RegisterRouter.scala:87:24] wire out_romask_1353 = \|_out_romask_T_1353; // @[RegisterRouter.scala:87:24] wire out_womask_1353 = &_out_womask_T_1353; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1353 = out_rivalid_1_1207 & out_rimask_1353; // @[RegisterRouter.scala:87:24] wire _out_T_12966 = out_f_rivalid_1353; // @[RegisterRouter.scala:87:24] wire out_f_roready_1353 = out_roready_1_1207 & out_romask_1353; // @[RegisterRouter.scala:87:24] wire _out_T_12967 = out_f_roready_1353; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1353 = out_wivalid_1_1207 & out_wimask_1353; // @[RegisterRouter.scala:87:24] wire out_f_woready_1353 = out_woready_1_1207 & out_womask_1353; // @[RegisterRouter.scala:87:24] wire _out_T_12968 = ~out_rimask_1353; // @[RegisterRouter.scala:87:24] wire _out_T_12969 = ~out_wimask_1353; // @[RegisterRouter.scala:87:24] wire _out_T_12970 = ~out_romask_1353; // @[RegisterRouter.scala:87:24] wire _out_T_12971 = ~out_womask_1353; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1164 = {hi_797, flags_0_go, _out_prepend_T_1164}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12972 = out_prepend_1164; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12973 = _out_T_12972; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1165 = _out_T_12973; // @[RegisterRouter.scala:87:24] wire out_rimask_1354 = \|_out_rimask_T_1354; // @[RegisterRouter.scala:87:24] wire out_wimask_1354 = &_out_wimask_T_1354; // @[RegisterRouter.scala:87:24] wire out_romask_1354 = \|_out_romask_T_1354; // @[RegisterRouter.scala:87:24] wire out_womask_1354 = &_out_womask_T_1354; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1354 = out_rivalid_1_1208 & out_rimask_1354; // @[RegisterRouter.scala:87:24] wire _out_T_12975 = out_f_rivalid_1354; // @[RegisterRouter.scala:87:24] wire out_f_roready_1354 = out_roready_1_1208 & out_romask_1354; // @[RegisterRouter.scala:87:24] wire _out_T_12976 = out_f_roready_1354; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1354 = out_wivalid_1_1208 & out_wimask_1354; // @[RegisterRouter.scala:87:24] wire out_f_woready_1354 = out_woready_1_1208 & out_womask_1354; // @[RegisterRouter.scala:87:24] wire _out_T_12977 = ~out_rimask_1354; // @[RegisterRouter.scala:87:24] wire _out_T_12978 = ~out_wimask_1354; // @[RegisterRouter.scala:87:24] wire _out_T_12979 = ~out_romask_1354; // @[RegisterRouter.scala:87:24] wire _out_T_12980 = ~out_womask_1354; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1165 = {hi_798, flags_0_go, _out_prepend_T_1165}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12981 = out_prepend_1165; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12982 = _out_T_12981; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1166 = _out_T_12982; // @[RegisterRouter.scala:87:24] wire out_rimask_1355 = \|_out_rimask_T_1355; // @[RegisterRouter.scala:87:24] wire out_wimask_1355 = &_out_wimask_T_1355; // @[RegisterRouter.scala:87:24] wire out_romask_1355 = \|_out_romask_T_1355; // @[RegisterRouter.scala:87:24] wire out_womask_1355 = &_out_womask_T_1355; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1355 = out_rivalid_1_1209 & out_rimask_1355; // @[RegisterRouter.scala:87:24] wire _out_T_12984 = out_f_rivalid_1355; // @[RegisterRouter.scala:87:24] wire out_f_roready_1355 = out_roready_1_1209 & out_romask_1355; // @[RegisterRouter.scala:87:24] wire _out_T_12985 = out_f_roready_1355; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1355 = out_wivalid_1_1209 & out_wimask_1355; // @[RegisterRouter.scala:87:24] wire out_f_woready_1355 = out_woready_1_1209 & out_womask_1355; // @[RegisterRouter.scala:87:24] wire _out_T_12986 = ~out_rimask_1355; // @[RegisterRouter.scala:87:24] wire _out_T_12987 = ~out_wimask_1355; // @[RegisterRouter.scala:87:24] wire _out_T_12988 = ~out_romask_1355; // @[RegisterRouter.scala:87:24] wire _out_T_12989 = ~out_womask_1355; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1166 = {hi_799, flags_0_go, _out_prepend_T_1166}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12990 = out_prepend_1166; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12991 = _out_T_12990; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1167 = _out_T_12991; // @[RegisterRouter.scala:87:24] wire out_rimask_1356 = \|_out_rimask_T_1356; // @[RegisterRouter.scala:87:24] wire out_wimask_1356 = &_out_wimask_T_1356; // @[RegisterRouter.scala:87:24] wire out_romask_1356 = \|_out_romask_T_1356; // @[RegisterRouter.scala:87:24] wire out_womask_1356 = &_out_womask_T_1356; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1356 = out_rivalid_1_1210 & out_rimask_1356; // @[RegisterRouter.scala:87:24] wire _out_T_12993 = out_f_rivalid_1356; // @[RegisterRouter.scala:87:24] wire out_f_roready_1356 = out_roready_1_1210 & out_romask_1356; // @[RegisterRouter.scala:87:24] wire _out_T_12994 = out_f_roready_1356; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1356 = out_wivalid_1_1210 & out_wimask_1356; // @[RegisterRouter.scala:87:24] wire out_f_woready_1356 = out_woready_1_1210 & out_womask_1356; // @[RegisterRouter.scala:87:24] wire _out_T_12995 = ~out_rimask_1356; // @[RegisterRouter.scala:87:24] wire _out_T_12996 = ~out_wimask_1356; // @[RegisterRouter.scala:87:24] wire _out_T_12997 = ~out_romask_1356; // @[RegisterRouter.scala:87:24] wire _out_T_12998 = ~out_womask_1356; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1167 = {hi_800, flags_0_go, _out_prepend_T_1167}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12999 = out_prepend_1167; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_13000 = _out_T_12999; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_227 = _out_T_13000; // @[MuxLiteral.scala:49:48] wire _out_iindex_T_7 = out_front_1_bits_index[0]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_7 = out_front_1_bits_index[0]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_8 = out_front_1_bits_index[1]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_8 = out_front_1_bits_index[1]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_9 = out_front_1_bits_index[2]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_9 = out_front_1_bits_index[2]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_10 = out_front_1_bits_index[3]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_10 = out_front_1_bits_index[3]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_11 = out_front_1_bits_index[4]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_11 = out_front_1_bits_index[4]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_12 = out_front_1_bits_index[5]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_12 = out_front_1_bits_index[5]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_13 = out_front_1_bits_index[6]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_13 = out_front_1_bits_index[6]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_14 = out_front_1_bits_index[7]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_14 = out_front_1_bits_index[7]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_15 = out_front_1_bits_index[8]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_15 = out_front_1_bits_index[8]; // @[RegisterRouter.scala:87:24] wire [1:0] out_iindex_lo_lo = {_out_iindex_T_8, _out_iindex_T_7}; // @[RegisterRouter.scala:87:24] wire [1:0] out_iindex_lo_hi_1 = {_out_iindex_T_10, _out_iindex_T_9}; // @[RegisterRouter.scala:87:24] wire [3:0] out_iindex_lo_1 = {out_iindex_lo_hi_1, out_iindex_lo_lo}; // @[RegisterRouter.scala:87:24] wire [1:0] out_iindex_hi_lo = {_out_iindex_T_12, _out_iindex_T_11}; // @[RegisterRouter.scala:87:24] wire [1:0] out_iindex_hi_hi_1 = {_out_iindex_T_14, _out_iindex_T_13}; // @[RegisterRouter.scala:87:24] wire [3:0] out_iindex_hi_1 = {out_iindex_hi_hi_1, out_iindex_hi_lo}; // @[RegisterRouter.scala:87:24] wire [7:0] out_iindex_1 = {out_iindex_hi_1, out_iindex_lo_1}; // @[RegisterRouter.scala:87:24] wire [1:0] out_oindex_lo_lo = {_out_oindex_T_8, _out_oindex_T_7}; // @[RegisterRouter.scala:87:24] wire [1:0] out_oindex_lo_hi_1 = {_out_oindex_T_10, _out_oindex_T_9}; // @[RegisterRouter.scala:87:24] wire [3:0] out_oindex_lo_1 = {out_oindex_lo_hi_1, out_oindex_lo_lo}; // @[RegisterRouter.scala:87:24] wire [1:0] out_oindex_hi_lo = {_out_oindex_T_12, _out_oindex_T_11}; // @[RegisterRouter.scala:87:24] wire [1:0] out_oindex_hi_hi_1 = {_out_oindex_T_14, _out_oindex_T_13}; // @[RegisterRouter.scala:87:24] wire [3:0] out_oindex_hi_1 = {out_oindex_hi_hi_1, out_oindex_hi_lo}; // @[RegisterRouter.scala:87:24] wire [7:0] out_oindex_1 = {out_oindex_hi_1, out_oindex_lo_1}; // @[RegisterRouter.scala:87:24] wire [255:0] _out_frontSel_T_1 = 256'h1 << out_iindex_1; // @[OneHot.scala:58:35] wire out_frontSel_0_1 = _out_frontSel_T_1[0]; // @[OneHot.scala:58:35] wire out_frontSel_1_1 = _out_frontSel_T_1[1]; // @[OneHot.scala:58:35] wire out_frontSel_2_1 = _out_frontSel_T_1[2]; // @[OneHot.scala:58:35] wire out_frontSel_3_1 = _out_frontSel_T_1[3]; // @[OneHot.scala:58:35] wire out_frontSel_4_1 = _out_frontSel_T_1[4]; // @[OneHot.scala:58:35] wire out_frontSel_5_1 = _out_frontSel_T_1[5]; // @[OneHot.scala:58:35] wire out_frontSel_6_1 = _out_frontSel_T_1[6]; // @[OneHot.scala:58:35] wire out_frontSel_7_1 = _out_frontSel_T_1[7]; // @[OneHot.scala:58:35] wire out_frontSel_8_1 = _out_frontSel_T_1[8]; // @[OneHot.scala:58:35] wire out_frontSel_9_1 = _out_frontSel_T_1[9]; // @[OneHot.scala:58:35] wire out_frontSel_10_1 = _out_frontSel_T_1[10]; // @[OneHot.scala:58:35] wire out_frontSel_11_1 = _out_frontSel_T_1[11]; // @[OneHot.scala:58:35] wire out_frontSel_12_1 = _out_frontSel_T_1[12]; // @[OneHot.scala:58:35] wire out_frontSel_13_1 = _out_frontSel_T_1[13]; // @[OneHot.scala:58:35] wire out_frontSel_14_1 = _out_frontSel_T_1[14]; // @[OneHot.scala:58:35] wire out_frontSel_15_1 = _out_frontSel_T_1[15]; // @[OneHot.scala:58:35] wire out_frontSel_16_1 = _out_frontSel_T_1[16]; // @[OneHot.scala:58:35] wire out_frontSel_17_1 = _out_frontSel_T_1[17]; // @[OneHot.scala:58:35] wire out_frontSel_18_1 = _out_frontSel_T_1[18]; // @[OneHot.scala:58:35] wire out_frontSel_19_1 = _out_frontSel_T_1[19]; // @[OneHot.scala:58:35] wire out_frontSel_20_1 = _out_frontSel_T_1[20]; // @[OneHot.scala:58:35] wire out_frontSel_21_1 = _out_frontSel_T_1[21]; // @[OneHot.scala:58:35] wire out_frontSel_22_1 = _out_frontSel_T_1[22]; // @[OneHot.scala:58:35] wire out_frontSel_23_1 = _out_frontSel_T_1[23]; // @[OneHot.scala:58:35] wire out_frontSel_24_1 = _out_frontSel_T_1[24]; // @[OneHot.scala:58:35] wire out_frontSel_25_1 = _out_frontSel_T_1[25]; // @[OneHot.scala:58:35] wire out_frontSel_26_1 = _out_frontSel_T_1[26]; // @[OneHot.scala:58:35] wire out_frontSel_27_1 = _out_frontSel_T_1[27]; // @[OneHot.scala:58:35] wire out_frontSel_28_1 = _out_frontSel_T_1[28]; // @[OneHot.scala:58:35] wire out_frontSel_29_1 = _out_frontSel_T_1[29]; // @[OneHot.scala:58:35] wire out_frontSel_30_1 = _out_frontSel_T_1[30]; // @[OneHot.scala:58:35] wire out_frontSel_31_1 = _out_frontSel_T_1[31]; // @[OneHot.scala:58:35] wire out_frontSel_32_1 = _out_frontSel_T_1[32]; // @[OneHot.scala:58:35] wire out_frontSel_33_1 = _out_frontSel_T_1[33]; // @[OneHot.scala:58:35] wire out_frontSel_34_1 = _out_frontSel_T_1[34]; // @[OneHot.scala:58:35] wire out_frontSel_35_1 = _out_frontSel_T_1[35]; // @[OneHot.scala:58:35] wire out_frontSel_36_1 = _out_frontSel_T_1[36]; // @[OneHot.scala:58:35] wire out_frontSel_37_1 = _out_frontSel_T_1[37]; // @[OneHot.scala:58:35] wire out_frontSel_38_1 = _out_frontSel_T_1[38]; // @[OneHot.scala:58:35] wire out_frontSel_39_1 = _out_frontSel_T_1[39]; // @[OneHot.scala:58:35] wire out_frontSel_40_1 = _out_frontSel_T_1[40]; // @[OneHot.scala:58:35] wire out_frontSel_41_1 = _out_frontSel_T_1[41]; // @[OneHot.scala:58:35] wire out_frontSel_42_1 = _out_frontSel_T_1[42]; // @[OneHot.scala:58:35] wire out_frontSel_43_1 = _out_frontSel_T_1[43]; // @[OneHot.scala:58:35] wire out_frontSel_44_1 = _out_frontSel_T_1[44]; // @[OneHot.scala:58:35] wire out_frontSel_45_1 = _out_frontSel_T_1[45]; // @[OneHot.scala:58:35] wire out_frontSel_46_1 = _out_frontSel_T_1[46]; // @[OneHot.scala:58:35] wire out_frontSel_47_1 = _out_frontSel_T_1[47]; // @[OneHot.scala:58:35] wire out_frontSel_48_1 = _out_frontSel_T_1[48]; // @[OneHot.scala:58:35] wire out_frontSel_49_1 = _out_frontSel_T_1[49]; // @[OneHot.scala:58:35] wire out_frontSel_50_1 = _out_frontSel_T_1[50]; // @[OneHot.scala:58:35] wire out_frontSel_51_1 = _out_frontSel_T_1[51]; // @[OneHot.scala:58:35] wire out_frontSel_52_1 = _out_frontSel_T_1[52]; // @[OneHot.scala:58:35] wire out_frontSel_53_1 = _out_frontSel_T_1[53]; // @[OneHot.scala:58:35] wire out_frontSel_54_1 = _out_frontSel_T_1[54]; // @[OneHot.scala:58:35] wire out_frontSel_55_1 = _out_frontSel_T_1[55]; // @[OneHot.scala:58:35] wire out_frontSel_56_1 = _out_frontSel_T_1[56]; // @[OneHot.scala:58:35] wire out_frontSel_57_1 = _out_frontSel_T_1[57]; // @[OneHot.scala:58:35] wire out_frontSel_58_1 = _out_frontSel_T_1[58]; // @[OneHot.scala:58:35] wire out_frontSel_59_1 = _out_frontSel_T_1[59]; // @[OneHot.scala:58:35] wire out_frontSel_60_1 = _out_frontSel_T_1[60]; // @[OneHot.scala:58:35] wire out_frontSel_61_1 = _out_frontSel_T_1[61]; // @[OneHot.scala:58:35] wire out_frontSel_62_1 = _out_frontSel_T_1[62]; // @[OneHot.scala:58:35] wire out_frontSel_63_1 = _out_frontSel_T_1[63]; // @[OneHot.scala:58:35] wire out_frontSel_64 = _out_frontSel_T_1[64]; // @[OneHot.scala:58:35] wire out_frontSel_65 = _out_frontSel_T_1[65]; // @[OneHot.scala:58:35] wire out_frontSel_66 = _out_frontSel_T_1[66]; // @[OneHot.scala:58:35] wire out_frontSel_67 = _out_frontSel_T_1[67]; // @[OneHot.scala:58:35] wire out_frontSel_68 = _out_frontSel_T_1[68]; // @[OneHot.scala:58:35] wire out_frontSel_69 = _out_frontSel_T_1[69]; // @[OneHot.scala:58:35] wire out_frontSel_70 = _out_frontSel_T_1[70]; // @[OneHot.scala:58:35] wire out_frontSel_71 = _out_frontSel_T_1[71]; // @[OneHot.scala:58:35] wire out_frontSel_72 = _out_frontSel_T_1[72]; // @[OneHot.scala:58:35] wire out_frontSel_73 = _out_frontSel_T_1[73]; // @[OneHot.scala:58:35] wire out_frontSel_74 = _out_frontSel_T_1[74]; // @[OneHot.scala:58:35] wire out_frontSel_75 = _out_frontSel_T_1[75]; // @[OneHot.scala:58:35] wire out_frontSel_76 = _out_frontSel_T_1[76]; // @[OneHot.scala:58:35] wire out_frontSel_77 = _out_frontSel_T_1[77]; // @[OneHot.scala:58:35] wire out_frontSel_78 = _out_frontSel_T_1[78]; // @[OneHot.scala:58:35] wire out_frontSel_79 = _out_frontSel_T_1[79]; // @[OneHot.scala:58:35] wire out_frontSel_80 = _out_frontSel_T_1[80]; // @[OneHot.scala:58:35] wire out_frontSel_81 = _out_frontSel_T_1[81]; // @[OneHot.scala:58:35] wire out_frontSel_82 = _out_frontSel_T_1[82]; // @[OneHot.scala:58:35] wire out_frontSel_83 = _out_frontSel_T_1[83]; // @[OneHot.scala:58:35] wire out_frontSel_84 = _out_frontSel_T_1[84]; // @[OneHot.scala:58:35] wire out_frontSel_85 = _out_frontSel_T_1[85]; // @[OneHot.scala:58:35] wire out_frontSel_86 = _out_frontSel_T_1[86]; // @[OneHot.scala:58:35] wire out_frontSel_87 = _out_frontSel_T_1[87]; // @[OneHot.scala:58:35] wire out_frontSel_88 = _out_frontSel_T_1[88]; // @[OneHot.scala:58:35] wire out_frontSel_89 = _out_frontSel_T_1[89]; // @[OneHot.scala:58:35] wire out_frontSel_90 = _out_frontSel_T_1[90]; // @[OneHot.scala:58:35] wire out_frontSel_91 = _out_frontSel_T_1[91]; // @[OneHot.scala:58:35] wire out_frontSel_92 = _out_frontSel_T_1[92]; // @[OneHot.scala:58:35] wire out_frontSel_93 = _out_frontSel_T_1[93]; // @[OneHot.scala:58:35] wire out_frontSel_94 = _out_frontSel_T_1[94]; // @[OneHot.scala:58:35] wire out_frontSel_95 = _out_frontSel_T_1[95]; // @[OneHot.scala:58:35] wire out_frontSel_96 = _out_frontSel_T_1[96]; // @[OneHot.scala:58:35] wire out_frontSel_97 = _out_frontSel_T_1[97]; // @[OneHot.scala:58:35] wire out_frontSel_98 = _out_frontSel_T_1[98]; // @[OneHot.scala:58:35] wire out_frontSel_99 = _out_frontSel_T_1[99]; // @[OneHot.scala:58:35] wire out_frontSel_100 = _out_frontSel_T_1[100]; // @[OneHot.scala:58:35] wire out_frontSel_101 = _out_frontSel_T_1[101]; // @[OneHot.scala:58:35] wire out_frontSel_102 = _out_frontSel_T_1[102]; // @[OneHot.scala:58:35] wire out_frontSel_103 = _out_frontSel_T_1[103]; // @[OneHot.scala:58:35] wire out_frontSel_104 = _out_frontSel_T_1[104]; // @[OneHot.scala:58:35] wire out_frontSel_105 = _out_frontSel_T_1[105]; // @[OneHot.scala:58:35] wire out_frontSel_106 = _out_frontSel_T_1[106]; // @[OneHot.scala:58:35] wire out_frontSel_107 = _out_frontSel_T_1[107]; // @[OneHot.scala:58:35] wire out_frontSel_108 = _out_frontSel_T_1[108]; // @[OneHot.scala:58:35] wire out_frontSel_109 = _out_frontSel_T_1[109]; // @[OneHot.scala:58:35] wire out_frontSel_110 = _out_frontSel_T_1[110]; // @[OneHot.scala:58:35] wire out_frontSel_111 = _out_frontSel_T_1[111]; // @[OneHot.scala:58:35] wire out_frontSel_112 = _out_frontSel_T_1[112]; // @[OneHot.scala:58:35] wire out_frontSel_113 = _out_frontSel_T_1[113]; // @[OneHot.scala:58:35] wire out_frontSel_114 = _out_frontSel_T_1[114]; // @[OneHot.scala:58:35] wire out_frontSel_115 = _out_frontSel_T_1[115]; // @[OneHot.scala:58:35] wire out_frontSel_116 = _out_frontSel_T_1[116]; // @[OneHot.scala:58:35] wire out_frontSel_117 = _out_frontSel_T_1[117]; // @[OneHot.scala:58:35] wire out_frontSel_118 = _out_frontSel_T_1[118]; // @[OneHot.scala:58:35] wire out_frontSel_119 = _out_frontSel_T_1[119]; // @[OneHot.scala:58:35] wire out_frontSel_120 = _out_frontSel_T_1[120]; // @[OneHot.scala:58:35] wire out_frontSel_121 = _out_frontSel_T_1[121]; // @[OneHot.scala:58:35] wire out_frontSel_122 = _out_frontSel_T_1[122]; // @[OneHot.scala:58:35] wire out_frontSel_123 = _out_frontSel_T_1[123]; // @[OneHot.scala:58:35] wire out_frontSel_124 = _out_frontSel_T_1[124]; // @[OneHot.scala:58:35] wire out_frontSel_125 = _out_frontSel_T_1[125]; // @[OneHot.scala:58:35] wire out_frontSel_126 = _out_frontSel_T_1[126]; // @[OneHot.scala:58:35] wire out_frontSel_127 = _out_frontSel_T_1[127]; // @[OneHot.scala:58:35] wire out_frontSel_128 = _out_frontSel_T_1[128]; // @[OneHot.scala:58:35] wire out_frontSel_129 = _out_frontSel_T_1[129]; // @[OneHot.scala:58:35] wire out_frontSel_130 = _out_frontSel_T_1[130]; // @[OneHot.scala:58:35] wire out_frontSel_131 = _out_frontSel_T_1[131]; // @[OneHot.scala:58:35] wire out_frontSel_132 = _out_frontSel_T_1[132]; // @[OneHot.scala:58:35] wire out_frontSel_133 = _out_frontSel_T_1[133]; // @[OneHot.scala:58:35] wire out_frontSel_134 = _out_frontSel_T_1[134]; // @[OneHot.scala:58:35] wire out_frontSel_135 = _out_frontSel_T_1[135]; // @[OneHot.scala:58:35] wire out_frontSel_136 = _out_frontSel_T_1[136]; // @[OneHot.scala:58:35] wire out_frontSel_137 = _out_frontSel_T_1[137]; // @[OneHot.scala:58:35] wire out_frontSel_138 = _out_frontSel_T_1[138]; // @[OneHot.scala:58:35] wire out_frontSel_139 = _out_frontSel_T_1[139]; // @[OneHot.scala:58:35] wire out_frontSel_140 = _out_frontSel_T_1[140]; // @[OneHot.scala:58:35] wire out_frontSel_141 = _out_frontSel_T_1[141]; // @[OneHot.scala:58:35] wire out_frontSel_142 = _out_frontSel_T_1[142]; // @[OneHot.scala:58:35] wire out_frontSel_143 = _out_frontSel_T_1[143]; // @[OneHot.scala:58:35] wire out_frontSel_144 = _out_frontSel_T_1[144]; // @[OneHot.scala:58:35] wire out_frontSel_145 = _out_frontSel_T_1[145]; // @[OneHot.scala:58:35] wire out_frontSel_146 = _out_frontSel_T_1[146]; // @[OneHot.scala:58:35] wire out_frontSel_147 = _out_frontSel_T_1[147]; // @[OneHot.scala:58:35] wire out_frontSel_148 = _out_frontSel_T_1[148]; // @[OneHot.scala:58:35] wire out_frontSel_149 = _out_frontSel_T_1[149]; // @[OneHot.scala:58:35] wire out_frontSel_150 = _out_frontSel_T_1[150]; // @[OneHot.scala:58:35] wire out_frontSel_151 = _out_frontSel_T_1[151]; // @[OneHot.scala:58:35] wire out_frontSel_152 = _out_frontSel_T_1[152]; // @[OneHot.scala:58:35] wire out_frontSel_153 = _out_frontSel_T_1[153]; // @[OneHot.scala:58:35] wire out_frontSel_154 = _out_frontSel_T_1[154]; // @[OneHot.scala:58:35] wire out_frontSel_155 = _out_frontSel_T_1[155]; // @[OneHot.scala:58:35] wire out_frontSel_156 = _out_frontSel_T_1[156]; // @[OneHot.scala:58:35] wire out_frontSel_157 = _out_frontSel_T_1[157]; // @[OneHot.scala:58:35] wire out_frontSel_158 = _out_frontSel_T_1[158]; // @[OneHot.scala:58:35] wire out_frontSel_159 = _out_frontSel_T_1[159]; // @[OneHot.scala:58:35] wire out_frontSel_160 = _out_frontSel_T_1[160]; // @[OneHot.scala:58:35] wire out_frontSel_161 = _out_frontSel_T_1[161]; // @[OneHot.scala:58:35] wire out_frontSel_162 = _out_frontSel_T_1[162]; // @[OneHot.scala:58:35] wire out_frontSel_163 = _out_frontSel_T_1[163]; // @[OneHot.scala:58:35] wire out_frontSel_164 = _out_frontSel_T_1[164]; // @[OneHot.scala:58:35] wire out_frontSel_165 = _out_frontSel_T_1[165]; // @[OneHot.scala:58:35] wire out_frontSel_166 = _out_frontSel_T_1[166]; // @[OneHot.scala:58:35] wire out_frontSel_167 = _out_frontSel_T_1[167]; // @[OneHot.scala:58:35] wire out_frontSel_168 = _out_frontSel_T_1[168]; // @[OneHot.scala:58:35] wire out_frontSel_169 = _out_frontSel_T_1[169]; // @[OneHot.scala:58:35] wire out_frontSel_170 = _out_frontSel_T_1[170]; // @[OneHot.scala:58:35] wire out_frontSel_171 = _out_frontSel_T_1[171]; // @[OneHot.scala:58:35] wire out_frontSel_172 = _out_frontSel_T_1[172]; // @[OneHot.scala:58:35] wire out_frontSel_173 = _out_frontSel_T_1[173]; // @[OneHot.scala:58:35] wire out_frontSel_174 = _out_frontSel_T_1[174]; // @[OneHot.scala:58:35] wire out_frontSel_175 = _out_frontSel_T_1[175]; // @[OneHot.scala:58:35] wire out_frontSel_176 = _out_frontSel_T_1[176]; // @[OneHot.scala:58:35] wire out_frontSel_177 = _out_frontSel_T_1[177]; // @[OneHot.scala:58:35] wire out_frontSel_178 = _out_frontSel_T_1[178]; // @[OneHot.scala:58:35] wire out_frontSel_179 = _out_frontSel_T_1[179]; // @[OneHot.scala:58:35] wire out_frontSel_180 = _out_frontSel_T_1[180]; // @[OneHot.scala:58:35] wire out_frontSel_181 = _out_frontSel_T_1[181]; // @[OneHot.scala:58:35] wire out_frontSel_182 = _out_frontSel_T_1[182]; // @[OneHot.scala:58:35] wire out_frontSel_183 = _out_frontSel_T_1[183]; // @[OneHot.scala:58:35] wire out_frontSel_184 = _out_frontSel_T_1[184]; // @[OneHot.scala:58:35] wire out_frontSel_185 = _out_frontSel_T_1[185]; // @[OneHot.scala:58:35] wire out_frontSel_186 = _out_frontSel_T_1[186]; // @[OneHot.scala:58:35] wire out_frontSel_187 = _out_frontSel_T_1[187]; // @[OneHot.scala:58:35] wire out_frontSel_188 = _out_frontSel_T_1[188]; // @[OneHot.scala:58:35] wire out_frontSel_189 = _out_frontSel_T_1[189]; // @[OneHot.scala:58:35] wire out_frontSel_190 = _out_frontSel_T_1[190]; // @[OneHot.scala:58:35] wire out_frontSel_191 = _out_frontSel_T_1[191]; // @[OneHot.scala:58:35] wire out_frontSel_192 = _out_frontSel_T_1[192]; // @[OneHot.scala:58:35] wire out_frontSel_193 = _out_frontSel_T_1[193]; // @[OneHot.scala:58:35] wire out_frontSel_194 = _out_frontSel_T_1[194]; // @[OneHot.scala:58:35] wire out_frontSel_195 = _out_frontSel_T_1[195]; // @[OneHot.scala:58:35] wire out_frontSel_196 = _out_frontSel_T_1[196]; // @[OneHot.scala:58:35] wire out_frontSel_197 = _out_frontSel_T_1[197]; // @[OneHot.scala:58:35] wire out_frontSel_198 = _out_frontSel_T_1[198]; // @[OneHot.scala:58:35] wire out_frontSel_199 = _out_frontSel_T_1[199]; // @[OneHot.scala:58:35] wire out_frontSel_200 = _out_frontSel_T_1[200]; // @[OneHot.scala:58:35] wire out_frontSel_201 = _out_frontSel_T_1[201]; // @[OneHot.scala:58:35] wire out_frontSel_202 = _out_frontSel_T_1[202]; // @[OneHot.scala:58:35] wire out_frontSel_203 = _out_frontSel_T_1[203]; // @[OneHot.scala:58:35] wire out_frontSel_204 = _out_frontSel_T_1[204]; // @[OneHot.scala:58:35] wire out_frontSel_205 = _out_frontSel_T_1[205]; // @[OneHot.scala:58:35] wire out_frontSel_206 = _out_frontSel_T_1[206]; // @[OneHot.scala:58:35] wire out_frontSel_207 = _out_frontSel_T_1[207]; // @[OneHot.scala:58:35] wire out_frontSel_208 = _out_frontSel_T_1[208]; // @[OneHot.scala:58:35] wire out_frontSel_209 = _out_frontSel_T_1[209]; // @[OneHot.scala:58:35] wire out_frontSel_210 = _out_frontSel_T_1[210]; // @[OneHot.scala:58:35] wire out_frontSel_211 = _out_frontSel_T_1[211]; // @[OneHot.scala:58:35] wire out_frontSel_212 = _out_frontSel_T_1[212]; // @[OneHot.scala:58:35] wire out_frontSel_213 = _out_frontSel_T_1[213]; // @[OneHot.scala:58:35] wire out_frontSel_214 = _out_frontSel_T_1[214]; // @[OneHot.scala:58:35] wire out_frontSel_215 = _out_frontSel_T_1[215]; // @[OneHot.scala:58:35] wire out_frontSel_216 = _out_frontSel_T_1[216]; // @[OneHot.scala:58:35] wire out_frontSel_217 = _out_frontSel_T_1[217]; // @[OneHot.scala:58:35] wire out_frontSel_218 = _out_frontSel_T_1[218]; // @[OneHot.scala:58:35] wire out_frontSel_219 = _out_frontSel_T_1[219]; // @[OneHot.scala:58:35] wire out_frontSel_220 = _out_frontSel_T_1[220]; // @[OneHot.scala:58:35] wire out_frontSel_221 = _out_frontSel_T_1[221]; // @[OneHot.scala:58:35] wire out_frontSel_222 = _out_frontSel_T_1[222]; // @[OneHot.scala:58:35] wire out_frontSel_223 = _out_frontSel_T_1[223]; // @[OneHot.scala:58:35] wire out_frontSel_224 = _out_frontSel_T_1[224]; // @[OneHot.scala:58:35] wire out_frontSel_225 = _out_frontSel_T_1[225]; // @[OneHot.scala:58:35] wire out_frontSel_226 = _out_frontSel_T_1[226]; // @[OneHot.scala:58:35] wire out_frontSel_227 = _out_frontSel_T_1[227]; // @[OneHot.scala:58:35] wire out_frontSel_228 = _out_frontSel_T_1[228]; // @[OneHot.scala:58:35] wire out_frontSel_229 = _out_frontSel_T_1[229]; // @[OneHot.scala:58:35] wire out_frontSel_230 = _out_frontSel_T_1[230]; // @[OneHot.scala:58:35] wire out_frontSel_231 = _out_frontSel_T_1[231]; // @[OneHot.scala:58:35] wire out_frontSel_232 = _out_frontSel_T_1[232]; // @[OneHot.scala:58:35] wire out_frontSel_233 = _out_frontSel_T_1[233]; // @[OneHot.scala:58:35] wire out_frontSel_234 = _out_frontSel_T_1[234]; // @[OneHot.scala:58:35] wire out_frontSel_235 = _out_frontSel_T_1[235]; // @[OneHot.scala:58:35] wire out_frontSel_236 = _out_frontSel_T_1[236]; // @[OneHot.scala:58:35] wire out_frontSel_237 = _out_frontSel_T_1[237]; // @[OneHot.scala:58:35] wire out_frontSel_238 = _out_frontSel_T_1[238]; // @[OneHot.scala:58:35] wire out_frontSel_239 = _out_frontSel_T_1[239]; // @[OneHot.scala:58:35] wire out_frontSel_240 = _out_frontSel_T_1[240]; // @[OneHot.scala:58:35] wire out_frontSel_241 = _out_frontSel_T_1[241]; // @[OneHot.scala:58:35] wire out_frontSel_242 = _out_frontSel_T_1[242]; // @[OneHot.scala:58:35] wire out_frontSel_243 = _out_frontSel_T_1[243]; // @[OneHot.scala:58:35] wire out_frontSel_244 = _out_frontSel_T_1[244]; // @[OneHot.scala:58:35] wire out_frontSel_245 = _out_frontSel_T_1[245]; // @[OneHot.scala:58:35] wire out_frontSel_246 = _out_frontSel_T_1[246]; // @[OneHot.scala:58:35] wire out_frontSel_247 = _out_frontSel_T_1[247]; // @[OneHot.scala:58:35] wire out_frontSel_248 = _out_frontSel_T_1[248]; // @[OneHot.scala:58:35] wire out_frontSel_249 = _out_frontSel_T_1[249]; // @[OneHot.scala:58:35] wire out_frontSel_250 = _out_frontSel_T_1[250]; // @[OneHot.scala:58:35] wire out_frontSel_251 = _out_frontSel_T_1[251]; // @[OneHot.scala:58:35] wire out_frontSel_252 = _out_frontSel_T_1[252]; // @[OneHot.scala:58:35] wire out_frontSel_253 = _out_frontSel_T_1[253]; // @[OneHot.scala:58:35] wire out_frontSel_254 = _out_frontSel_T_1[254]; // @[OneHot.scala:58:35] wire out_frontSel_255 = _out_frontSel_T_1[255]; // @[OneHot.scala:58:35] wire [255:0] _out_backSel_T_1 = 256'h1 << out_oindex_1; // @[OneHot.scala:58:35] wire out_backSel_0_1 = _out_backSel_T_1[0]; // @[OneHot.scala:58:35] wire out_backSel_1_1 = _out_backSel_T_1[1]; // @[OneHot.scala:58:35] wire out_backSel_2_1 = _out_backSel_T_1[2]; // @[OneHot.scala:58:35] wire out_backSel_3_1 = _out_backSel_T_1[3]; // @[OneHot.scala:58:35] wire out_backSel_4_1 = _out_backSel_T_1[4]; // @[OneHot.scala:58:35] wire out_backSel_5_1 = _out_backSel_T_1[5]; // @[OneHot.scala:58:35] wire out_backSel_6_1 = _out_backSel_T_1[6]; // @[OneHot.scala:58:35] wire out_backSel_7_1 = _out_backSel_T_1[7]; // @[OneHot.scala:58:35] wire out_backSel_8_1 = _out_backSel_T_1[8]; // @[OneHot.scala:58:35] wire out_backSel_9_1 = _out_backSel_T_1[9]; // @[OneHot.scala:58:35] wire out_backSel_10_1 = _out_backSel_T_1[10]; // @[OneHot.scala:58:35] wire out_backSel_11_1 = _out_backSel_T_1[11]; // @[OneHot.scala:58:35] wire out_backSel_12_1 = _out_backSel_T_1[12]; // @[OneHot.scala:58:35] wire out_backSel_13_1 = _out_backSel_T_1[13]; // @[OneHot.scala:58:35] wire out_backSel_14_1 = _out_backSel_T_1[14]; // @[OneHot.scala:58:35] wire out_backSel_15_1 = _out_backSel_T_1[15]; // @[OneHot.scala:58:35] wire out_backSel_16_1 = _out_backSel_T_1[16]; // @[OneHot.scala:58:35] wire out_backSel_17_1 = _out_backSel_T_1[17]; // @[OneHot.scala:58:35] wire out_backSel_18_1 = _out_backSel_T_1[18]; // @[OneHot.scala:58:35] wire out_backSel_19_1 = _out_backSel_T_1[19]; // @[OneHot.scala:58:35] wire out_backSel_20_1 = _out_backSel_T_1[20]; // @[OneHot.scala:58:35] wire out_backSel_21_1 = _out_backSel_T_1[21]; // @[OneHot.scala:58:35] wire out_backSel_22_1 = _out_backSel_T_1[22]; // @[OneHot.scala:58:35] wire out_backSel_23_1 = _out_backSel_T_1[23]; // @[OneHot.scala:58:35] wire out_backSel_24_1 = _out_backSel_T_1[24]; // @[OneHot.scala:58:35] wire out_backSel_25_1 = _out_backSel_T_1[25]; // @[OneHot.scala:58:35] wire out_backSel_26_1 = _out_backSel_T_1[26]; // @[OneHot.scala:58:35] wire out_backSel_27_1 = _out_backSel_T_1[27]; // @[OneHot.scala:58:35] wire out_backSel_28_1 = _out_backSel_T_1[28]; // @[OneHot.scala:58:35] wire out_backSel_29_1 = _out_backSel_T_1[29]; // @[OneHot.scala:58:35] wire out_backSel_30_1 = _out_backSel_T_1[30]; // @[OneHot.scala:58:35] wire out_backSel_31_1 = _out_backSel_T_1[31]; // @[OneHot.scala:58:35] wire out_backSel_32_1 = _out_backSel_T_1[32]; // @[OneHot.scala:58:35] wire out_backSel_33_1 = _out_backSel_T_1[33]; // @[OneHot.scala:58:35] wire out_backSel_34_1 = _out_backSel_T_1[34]; // @[OneHot.scala:58:35] wire out_backSel_35_1 = _out_backSel_T_1[35]; // @[OneHot.scala:58:35] wire out_backSel_36_1 = _out_backSel_T_1[36]; // @[OneHot.scala:58:35] wire out_backSel_37_1 = _out_backSel_T_1[37]; // @[OneHot.scala:58:35] wire out_backSel_38_1 = _out_backSel_T_1[38]; // @[OneHot.scala:58:35] wire out_backSel_39_1 = _out_backSel_T_1[39]; // @[OneHot.scala:58:35] wire out_backSel_40_1 = _out_backSel_T_1[40]; // @[OneHot.scala:58:35] wire out_backSel_41_1 = _out_backSel_T_1[41]; // @[OneHot.scala:58:35] wire out_backSel_42_1 = _out_backSel_T_1[42]; // @[OneHot.scala:58:35] wire out_backSel_43_1 = _out_backSel_T_1[43]; // @[OneHot.scala:58:35] wire out_backSel_44_1 = _out_backSel_T_1[44]; // @[OneHot.scala:58:35] wire out_backSel_45_1 = _out_backSel_T_1[45]; // @[OneHot.scala:58:35] wire out_backSel_46_1 = _out_backSel_T_1[46]; // @[OneHot.scala:58:35] wire out_backSel_47_1 = _out_backSel_T_1[47]; // @[OneHot.scala:58:35] wire out_backSel_48_1 = _out_backSel_T_1[48]; // @[OneHot.scala:58:35] wire out_backSel_49_1 = _out_backSel_T_1[49]; // @[OneHot.scala:58:35] wire out_backSel_50_1 = _out_backSel_T_1[50]; // @[OneHot.scala:58:35] wire out_backSel_51_1 = _out_backSel_T_1[51]; // @[OneHot.scala:58:35] wire out_backSel_52_1 = _out_backSel_T_1[52]; // @[OneHot.scala:58:35] wire out_backSel_53_1 = _out_backSel_T_1[53]; // @[OneHot.scala:58:35] wire out_backSel_54_1 = _out_backSel_T_1[54]; // @[OneHot.scala:58:35] wire out_backSel_55_1 = _out_backSel_T_1[55]; // @[OneHot.scala:58:35] wire out_backSel_56_1 = _out_backSel_T_1[56]; // @[OneHot.scala:58:35] wire out_backSel_57_1 = _out_backSel_T_1[57]; // @[OneHot.scala:58:35] wire out_backSel_58_1 = _out_backSel_T_1[58]; // @[OneHot.scala:58:35] wire out_backSel_59_1 = _out_backSel_T_1[59]; // @[OneHot.scala:58:35] wire out_backSel_60_1 = _out_backSel_T_1[60]; // @[OneHot.scala:58:35] wire out_backSel_61_1 = _out_backSel_T_1[61]; // @[OneHot.scala:58:35] wire out_backSel_62_1 = _out_backSel_T_1[62]; // @[OneHot.scala:58:35] wire out_backSel_63_1 = _out_backSel_T_1[63]; // @[OneHot.scala:58:35] wire out_backSel_64 = _out_backSel_T_1[64]; // @[OneHot.scala:58:35] wire out_backSel_65 = _out_backSel_T_1[65]; // @[OneHot.scala:58:35] wire out_backSel_66 = _out_backSel_T_1[66]; // @[OneHot.scala:58:35] wire out_backSel_67 = _out_backSel_T_1[67]; // @[OneHot.scala:58:35] wire out_backSel_68 = _out_backSel_T_1[68]; // @[OneHot.scala:58:35] wire out_backSel_69 = _out_backSel_T_1[69]; // @[OneHot.scala:58:35] wire out_backSel_70 = _out_backSel_T_1[70]; // @[OneHot.scala:58:35] wire out_backSel_71 = _out_backSel_T_1[71]; // @[OneHot.scala:58:35] wire out_backSel_72 = _out_backSel_T_1[72]; // @[OneHot.scala:58:35] wire out_backSel_73 = _out_backSel_T_1[73]; // @[OneHot.scala:58:35] wire out_backSel_74 = _out_backSel_T_1[74]; // @[OneHot.scala:58:35] wire out_backSel_75 = _out_backSel_T_1[75]; // @[OneHot.scala:58:35] wire out_backSel_76 = _out_backSel_T_1[76]; // @[OneHot.scala:58:35] wire out_backSel_77 = _out_backSel_T_1[77]; // @[OneHot.scala:58:35] wire out_backSel_78 = _out_backSel_T_1[78]; // @[OneHot.scala:58:35] wire out_backSel_79 = _out_backSel_T_1[79]; // @[OneHot.scala:58:35] wire out_backSel_80 = _out_backSel_T_1[80]; // @[OneHot.scala:58:35] wire out_backSel_81 = _out_backSel_T_1[81]; // @[OneHot.scala:58:35] wire out_backSel_82 = _out_backSel_T_1[82]; // @[OneHot.scala:58:35] wire out_backSel_83 = _out_backSel_T_1[83]; // @[OneHot.scala:58:35] wire out_backSel_84 = _out_backSel_T_1[84]; // @[OneHot.scala:58:35] wire out_backSel_85 = _out_backSel_T_1[85]; // @[OneHot.scala:58:35] wire out_backSel_86 = _out_backSel_T_1[86]; // @[OneHot.scala:58:35] wire out_backSel_87 = _out_backSel_T_1[87]; // @[OneHot.scala:58:35] wire out_backSel_88 = _out_backSel_T_1[88]; // @[OneHot.scala:58:35] wire out_backSel_89 = _out_backSel_T_1[89]; // @[OneHot.scala:58:35] wire out_backSel_90 = _out_backSel_T_1[90]; // @[OneHot.scala:58:35] wire out_backSel_91 = _out_backSel_T_1[91]; // @[OneHot.scala:58:35] wire out_backSel_92 = _out_backSel_T_1[92]; // @[OneHot.scala:58:35] wire out_backSel_93 = _out_backSel_T_1[93]; // @[OneHot.scala:58:35] wire out_backSel_94 = _out_backSel_T_1[94]; // @[OneHot.scala:58:35] wire out_backSel_95 = _out_backSel_T_1[95]; // @[OneHot.scala:58:35] wire out_backSel_96 = _out_backSel_T_1[96]; // @[OneHot.scala:58:35] wire out_backSel_97 = _out_backSel_T_1[97]; // @[OneHot.scala:58:35] wire out_backSel_98 = _out_backSel_T_1[98]; // @[OneHot.scala:58:35] wire out_backSel_99 = _out_backSel_T_1[99]; // @[OneHot.scala:58:35] wire out_backSel_100 = _out_backSel_T_1[100]; // @[OneHot.scala:58:35] wire out_backSel_101 = _out_backSel_T_1[101]; // @[OneHot.scala:58:35] wire out_backSel_102 = _out_backSel_T_1[102]; // @[OneHot.scala:58:35] wire out_backSel_103 = _out_backSel_T_1[103]; // @[OneHot.scala:58:35] wire out_backSel_104 = _out_backSel_T_1[104]; // @[OneHot.scala:58:35] wire out_backSel_105 = _out_backSel_T_1[105]; // @[OneHot.scala:58:35] wire out_backSel_106 = _out_backSel_T_1[106]; // @[OneHot.scala:58:35] wire out_backSel_107 = _out_backSel_T_1[107]; // @[OneHot.scala:58:35] wire out_backSel_108 = _out_backSel_T_1[108]; // @[OneHot.scala:58:35] wire out_backSel_109 = _out_backSel_T_1[109]; // @[OneHot.scala:58:35] wire out_backSel_110 = _out_backSel_T_1[110]; // @[OneHot.scala:58:35] wire out_backSel_111 = _out_backSel_T_1[111]; // @[OneHot.scala:58:35] wire out_backSel_112 = _out_backSel_T_1[112]; // @[OneHot.scala:58:35] wire out_backSel_113 = _out_backSel_T_1[113]; // @[OneHot.scala:58:35] wire out_backSel_114 = _out_backSel_T_1[114]; // @[OneHot.scala:58:35] wire out_backSel_115 = _out_backSel_T_1[115]; // @[OneHot.scala:58:35] wire out_backSel_116 = _out_backSel_T_1[116]; // @[OneHot.scala:58:35] wire out_backSel_117 = _out_backSel_T_1[117]; // @[OneHot.scala:58:35] wire out_backSel_118 = _out_backSel_T_1[118]; // @[OneHot.scala:58:35] wire out_backSel_119 = _out_backSel_T_1[119]; // @[OneHot.scala:58:35] wire out_backSel_120 = _out_backSel_T_1[120]; // @[OneHot.scala:58:35] wire out_backSel_121 = _out_backSel_T_1[121]; // @[OneHot.scala:58:35] wire out_backSel_122 = _out_backSel_T_1[122]; // @[OneHot.scala:58:35] wire out_backSel_123 = _out_backSel_T_1[123]; // @[OneHot.scala:58:35] wire out_backSel_124 = _out_backSel_T_1[124]; // @[OneHot.scala:58:35] wire out_backSel_125 = _out_backSel_T_1[125]; // @[OneHot.scala:58:35] wire out_backSel_126 = _out_backSel_T_1[126]; // @[OneHot.scala:58:35] wire out_backSel_127 = _out_backSel_T_1[127]; // @[OneHot.scala:58:35] wire out_backSel_128 = _out_backSel_T_1[128]; // @[OneHot.scala:58:35] wire out_backSel_129 = _out_backSel_T_1[129]; // @[OneHot.scala:58:35] wire out_backSel_130 = _out_backSel_T_1[130]; // @[OneHot.scala:58:35] wire out_backSel_131 = _out_backSel_T_1[131]; // @[OneHot.scala:58:35] wire out_backSel_132 = _out_backSel_T_1[132]; // @[OneHot.scala:58:35] wire out_backSel_133 = _out_backSel_T_1[133]; // @[OneHot.scala:58:35] wire out_backSel_134 = _out_backSel_T_1[134]; // @[OneHot.scala:58:35] wire out_backSel_135 = _out_backSel_T_1[135]; // @[OneHot.scala:58:35] wire out_backSel_136 = _out_backSel_T_1[136]; // @[OneHot.scala:58:35] wire out_backSel_137 = _out_backSel_T_1[137]; // @[OneHot.scala:58:35] wire out_backSel_138 = _out_backSel_T_1[138]; // @[OneHot.scala:58:35] wire out_backSel_139 = _out_backSel_T_1[139]; // @[OneHot.scala:58:35] wire out_backSel_140 = _out_backSel_T_1[140]; // @[OneHot.scala:58:35] wire out_backSel_141 = _out_backSel_T_1[141]; // @[OneHot.scala:58:35] wire out_backSel_142 = _out_backSel_T_1[142]; // @[OneHot.scala:58:35] wire out_backSel_143 = _out_backSel_T_1[143]; // @[OneHot.scala:58:35] wire out_backSel_144 = _out_backSel_T_1[144]; // @[OneHot.scala:58:35] wire out_backSel_145 = _out_backSel_T_1[145]; // @[OneHot.scala:58:35] wire out_backSel_146 = _out_backSel_T_1[146]; // @[OneHot.scala:58:35] wire out_backSel_147 = _out_backSel_T_1[147]; // @[OneHot.scala:58:35] wire out_backSel_148 = _out_backSel_T_1[148]; // @[OneHot.scala:58:35] wire out_backSel_149 = _out_backSel_T_1[149]; // @[OneHot.scala:58:35] wire out_backSel_150 = _out_backSel_T_1[150]; // @[OneHot.scala:58:35] wire out_backSel_151 = _out_backSel_T_1[151]; // @[OneHot.scala:58:35] wire out_backSel_152 = _out_backSel_T_1[152]; // @[OneHot.scala:58:35] wire out_backSel_153 = _out_backSel_T_1[153]; // @[OneHot.scala:58:35] wire out_backSel_154 = _out_backSel_T_1[154]; // @[OneHot.scala:58:35] wire out_backSel_155 = _out_backSel_T_1[155]; // @[OneHot.scala:58:35] wire out_backSel_156 = _out_backSel_T_1[156]; // @[OneHot.scala:58:35] wire out_backSel_157 = _out_backSel_T_1[157]; // @[OneHot.scala:58:35] wire out_backSel_158 = _out_backSel_T_1[158]; // @[OneHot.scala:58:35] wire out_backSel_159 = _out_backSel_T_1[159]; // @[OneHot.scala:58:35] wire out_backSel_160 = _out_backSel_T_1[160]; // @[OneHot.scala:58:35] wire out_backSel_161 = _out_backSel_T_1[161]; // @[OneHot.scala:58:35] wire out_backSel_162 = _out_backSel_T_1[162]; // @[OneHot.scala:58:35] wire out_backSel_163 = _out_backSel_T_1[163]; // @[OneHot.scala:58:35] wire out_backSel_164 = _out_backSel_T_1[164]; // @[OneHot.scala:58:35] wire out_backSel_165 = _out_backSel_T_1[165]; // @[OneHot.scala:58:35] wire out_backSel_166 = _out_backSel_T_1[166]; // @[OneHot.scala:58:35] wire out_backSel_167 = _out_backSel_T_1[167]; // @[OneHot.scala:58:35] wire out_backSel_168 = _out_backSel_T_1[168]; // @[OneHot.scala:58:35] wire out_backSel_169 = _out_backSel_T_1[169]; // @[OneHot.scala:58:35] wire out_backSel_170 = _out_backSel_T_1[170]; // @[OneHot.scala:58:35] wire out_backSel_171 = _out_backSel_T_1[171]; // @[OneHot.scala:58:35] wire out_backSel_172 = _out_backSel_T_1[172]; // @[OneHot.scala:58:35] wire out_backSel_173 = _out_backSel_T_1[173]; // @[OneHot.scala:58:35] wire out_backSel_174 = _out_backSel_T_1[174]; // @[OneHot.scala:58:35] wire out_backSel_175 = _out_backSel_T_1[175]; // @[OneHot.scala:58:35] wire out_backSel_176 = _out_backSel_T_1[176]; // @[OneHot.scala:58:35] wire out_backSel_177 = _out_backSel_T_1[177]; // @[OneHot.scala:58:35] wire out_backSel_178 = _out_backSel_T_1[178]; // @[OneHot.scala:58:35] wire out_backSel_179 = _out_backSel_T_1[179]; // @[OneHot.scala:58:35] wire out_backSel_180 = _out_backSel_T_1[180]; // @[OneHot.scala:58:35] wire out_backSel_181 = _out_backSel_T_1[181]; // @[OneHot.scala:58:35] wire out_backSel_182 = _out_backSel_T_1[182]; // @[OneHot.scala:58:35] wire out_backSel_183 = _out_backSel_T_1[183]; // @[OneHot.scala:58:35] wire out_backSel_184 = _out_backSel_T_1[184]; // @[OneHot.scala:58:35] wire out_backSel_185 = _out_backSel_T_1[185]; // @[OneHot.scala:58:35] wire out_backSel_186 = _out_backSel_T_1[186]; // @[OneHot.scala:58:35] wire out_backSel_187 = _out_backSel_T_1[187]; // @[OneHot.scala:58:35] wire out_backSel_188 = _out_backSel_T_1[188]; // @[OneHot.scala:58:35] wire out_backSel_189 = _out_backSel_T_1[189]; // @[OneHot.scala:58:35] wire out_backSel_190 = _out_backSel_T_1[190]; // @[OneHot.scala:58:35] wire out_backSel_191 = _out_backSel_T_1[191]; // @[OneHot.scala:58:35] wire out_backSel_192 = _out_backSel_T_1[192]; // @[OneHot.scala:58:35] wire out_backSel_193 = _out_backSel_T_1[193]; // @[OneHot.scala:58:35] wire out_backSel_194 = _out_backSel_T_1[194]; // @[OneHot.scala:58:35] wire out_backSel_195 = _out_backSel_T_1[195]; // @[OneHot.scala:58:35] wire out_backSel_196 = _out_backSel_T_1[196]; // @[OneHot.scala:58:35] wire out_backSel_197 = _out_backSel_T_1[197]; // @[OneHot.scala:58:35] wire out_backSel_198 = _out_backSel_T_1[198]; // @[OneHot.scala:58:35] wire out_backSel_199 = _out_backSel_T_1[199]; // @[OneHot.scala:58:35] wire out_backSel_200 = _out_backSel_T_1[200]; // @[OneHot.scala:58:35] wire out_backSel_201 = _out_backSel_T_1[201]; // @[OneHot.scala:58:35] wire out_backSel_202 = _out_backSel_T_1[202]; // @[OneHot.scala:58:35] wire out_backSel_203 = _out_backSel_T_1[203]; // @[OneHot.scala:58:35] wire out_backSel_204 = _out_backSel_T_1[204]; // @[OneHot.scala:58:35] wire out_backSel_205 = _out_backSel_T_1[205]; // @[OneHot.scala:58:35] wire out_backSel_206 = _out_backSel_T_1[206]; // @[OneHot.scala:58:35] wire out_backSel_207 = _out_backSel_T_1[207]; // @[OneHot.scala:58:35] wire out_backSel_208 = _out_backSel_T_1[208]; // @[OneHot.scala:58:35] wire out_backSel_209 = _out_backSel_T_1[209]; // @[OneHot.scala:58:35] wire out_backSel_210 = _out_backSel_T_1[210]; // @[OneHot.scala:58:35] wire out_backSel_211 = _out_backSel_T_1[211]; // @[OneHot.scala:58:35] wire out_backSel_212 = _out_backSel_T_1[212]; // @[OneHot.scala:58:35] wire out_backSel_213 = _out_backSel_T_1[213]; // @[OneHot.scala:58:35] wire out_backSel_214 = _out_backSel_T_1[214]; // @[OneHot.scala:58:35] wire out_backSel_215 = _out_backSel_T_1[215]; // @[OneHot.scala:58:35] wire out_backSel_216 = _out_backSel_T_1[216]; // @[OneHot.scala:58:35] wire out_backSel_217 = _out_backSel_T_1[217]; // @[OneHot.scala:58:35] wire out_backSel_218 = _out_backSel_T_1[218]; // @[OneHot.scala:58:35] wire out_backSel_219 = _out_backSel_T_1[219]; // @[OneHot.scala:58:35] wire out_backSel_220 = _out_backSel_T_1[220]; // @[OneHot.scala:58:35] wire out_backSel_221 = _out_backSel_T_1[221]; // @[OneHot.scala:58:35] wire out_backSel_222 = _out_backSel_T_1[222]; // @[OneHot.scala:58:35] wire out_backSel_223 = _out_backSel_T_1[223]; // @[OneHot.scala:58:35] wire out_backSel_224 = _out_backSel_T_1[224]; // @[OneHot.scala:58:35] wire out_backSel_225 = _out_backSel_T_1[225]; // @[OneHot.scala:58:35] wire out_backSel_226 = _out_backSel_T_1[226]; // @[OneHot.scala:58:35] wire out_backSel_227 = _out_backSel_T_1[227]; // @[OneHot.scala:58:35] wire out_backSel_228 = _out_backSel_T_1[228]; // @[OneHot.scala:58:35] wire out_backSel_229 = _out_backSel_T_1[229]; // @[OneHot.scala:58:35] wire out_backSel_230 = _out_backSel_T_1[230]; // @[OneHot.scala:58:35] wire out_backSel_231 = _out_backSel_T_1[231]; // @[OneHot.scala:58:35] wire out_backSel_232 = _out_backSel_T_1[232]; // @[OneHot.scala:58:35] wire out_backSel_233 = _out_backSel_T_1[233]; // @[OneHot.scala:58:35] wire out_backSel_234 = _out_backSel_T_1[234]; // @[OneHot.scala:58:35] wire out_backSel_235 = _out_backSel_T_1[235]; // @[OneHot.scala:58:35] wire out_backSel_236 = _out_backSel_T_1[236]; // @[OneHot.scala:58:35] wire out_backSel_237 = _out_backSel_T_1[237]; // @[OneHot.scala:58:35] wire out_backSel_238 = _out_backSel_T_1[238]; // @[OneHot.scala:58:35] wire out_backSel_239 = _out_backSel_T_1[239]; // @[OneHot.scala:58:35] wire out_backSel_240 = _out_backSel_T_1[240]; // @[OneHot.scala:58:35] wire out_backSel_241 = _out_backSel_T_1[241]; // @[OneHot.scala:58:35] wire out_backSel_242 = _out_backSel_T_1[242]; // @[OneHot.scala:58:35] wire out_backSel_243 = _out_backSel_T_1[243]; // @[OneHot.scala:58:35] wire out_backSel_244 = _out_backSel_T_1[244]; // @[OneHot.scala:58:35] wire out_backSel_245 = _out_backSel_T_1[245]; // @[OneHot.scala:58:35] wire out_backSel_246 = _out_backSel_T_1[246]; // @[OneHot.scala:58:35] wire out_backSel_247 = _out_backSel_T_1[247]; // @[OneHot.scala:58:35] wire out_backSel_248 = _out_backSel_T_1[248]; // @[OneHot.scala:58:35] wire out_backSel_249 = _out_backSel_T_1[249]; // @[OneHot.scala:58:35] wire out_backSel_250 = _out_backSel_T_1[250]; // @[OneHot.scala:58:35] wire out_backSel_251 = _out_backSel_T_1[251]; // @[OneHot.scala:58:35] wire out_backSel_252 = _out_backSel_T_1[252]; // @[OneHot.scala:58:35] wire out_backSel_253 = _out_backSel_T_1[253]; // @[OneHot.scala:58:35] wire out_backSel_254 = _out_backSel_T_1[254]; // @[OneHot.scala:58:35] wire out_backSel_255 = _out_backSel_T_1[255]; // @[OneHot.scala:58:35] wire _GEN_22 = in_1_valid & out_front_1_ready; // @[RegisterRouter.scala:73:18, :87:24] wire _out_rifireMux_T_259; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_259 = _GEN_22; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_260; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_260 = _GEN_22; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_260 = _out_rifireMux_T_259 & out_front_1_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_261 = _out_rifireMux_T_260 & out_frontSel_0_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_262 = _out_rifireMux_T_261 & _out_T_1716; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_451 = _out_rifireMux_T_262; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_452 = _out_rifireMux_T_262; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_453 = _out_rifireMux_T_262; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_454 = _out_rifireMux_T_262; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_455 = _out_rifireMux_T_262; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_456 = _out_rifireMux_T_262; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_457 = _out_rifireMux_T_262; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_458 = _out_rifireMux_T_262; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_263 = ~_out_T_1716; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_265 = _out_rifireMux_T_260 & out_frontSel_1_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_266 = _out_rifireMux_T_265 & _out_T_1624; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_96 = _out_rifireMux_T_266; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_97 = _out_rifireMux_T_266; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_98 = _out_rifireMux_T_266; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_99 = _out_rifireMux_T_266; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_100 = _out_rifireMux_T_266; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_101 = _out_rifireMux_T_266; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_102 = _out_rifireMux_T_266; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_103 = _out_rifireMux_T_266; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_267 = ~_out_T_1624; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_269 = _out_rifireMux_T_260 & out_frontSel_2_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_270 = _out_rifireMux_T_269 & _out_T_1846; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_955 = _out_rifireMux_T_270; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_956 = _out_rifireMux_T_270; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_957 = _out_rifireMux_T_270; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_958 = _out_rifireMux_T_270; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_959 = _out_rifireMux_T_270; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_960 = _out_rifireMux_T_270; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_961 = _out_rifireMux_T_270; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_962 = _out_rifireMux_T_270; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_271 = ~_out_T_1846; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_273 = _out_rifireMux_T_260 & out_frontSel_3_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_274 = _out_rifireMux_T_273 & _out_T_1756; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_601 = _out_rifireMux_T_274; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_602 = _out_rifireMux_T_274; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_603 = _out_rifireMux_T_274; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_604 = _out_rifireMux_T_274; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_605 = _out_rifireMux_T_274; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_606 = _out_rifireMux_T_274; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_607 = _out_rifireMux_T_274; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_608 = _out_rifireMux_T_274; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_275 = ~_out_T_1756; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_277 = _out_rifireMux_T_260 & out_frontSel_4_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_278 = _out_rifireMux_T_277 & _out_T_1678; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_312 = _out_rifireMux_T_278; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_313 = _out_rifireMux_T_278; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_314 = _out_rifireMux_T_278; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_315 = _out_rifireMux_T_278; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_316 = _out_rifireMux_T_278; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_317 = _out_rifireMux_T_278; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_318 = _out_rifireMux_T_278; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_319 = _out_rifireMux_T_278; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_279 = ~_out_T_1678; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_281 = _out_rifireMux_T_260 & out_frontSel_5_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_282 = _out_rifireMux_T_281 & _out_T_1640; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_160 = _out_rifireMux_T_282; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_161 = _out_rifireMux_T_282; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_162 = _out_rifireMux_T_282; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_163 = _out_rifireMux_T_282; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_164 = _out_rifireMux_T_282; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_165 = _out_rifireMux_T_282; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_166 = _out_rifireMux_T_282; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_167 = _out_rifireMux_T_282; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_283 = ~_out_T_1640; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_285 = _out_rifireMux_T_260 & out_frontSel_6_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_286 = _out_rifireMux_T_285 & _out_T_1876; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1075 = _out_rifireMux_T_286; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1076 = _out_rifireMux_T_286; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1077 = _out_rifireMux_T_286; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1078 = _out_rifireMux_T_286; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1079 = _out_rifireMux_T_286; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1080 = _out_rifireMux_T_286; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1081 = _out_rifireMux_T_286; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1082 = _out_rifireMux_T_286; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_287 = ~_out_T_1876; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_289 = _out_rifireMux_T_260 & out_frontSel_7_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_290 = _out_rifireMux_T_289 & _out_T_1822; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_859 = _out_rifireMux_T_290; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_860 = _out_rifireMux_T_290; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_861 = _out_rifireMux_T_290; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_862 = _out_rifireMux_T_290; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_863 = _out_rifireMux_T_290; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_864 = _out_rifireMux_T_290; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_865 = _out_rifireMux_T_290; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_866 = _out_rifireMux_T_290; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_291 = ~_out_T_1822; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_293 = _out_rifireMux_T_260 & out_frontSel_8_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_294 = _out_rifireMux_T_293 & _out_T_1742; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_545 = _out_rifireMux_T_294; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_546 = _out_rifireMux_T_294; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_547 = _out_rifireMux_T_294; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_548 = _out_rifireMux_T_294; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_549 = _out_rifireMux_T_294; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_550 = _out_rifireMux_T_294; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_551 = _out_rifireMux_T_294; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_552 = _out_rifireMux_T_294; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_295 = ~_out_T_1742; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_297 = _out_rifireMux_T_260 & out_frontSel_9_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_298 = _out_rifireMux_T_297 & _out_T_1666; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_264 = _out_rifireMux_T_298; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_265 = _out_rifireMux_T_298; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_266 = _out_rifireMux_T_298; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_267 = _out_rifireMux_T_298; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_268 = _out_rifireMux_T_298; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_269 = _out_rifireMux_T_298; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_270 = _out_rifireMux_T_298; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_271 = _out_rifireMux_T_298; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_299 = ~_out_T_1666; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_301 = _out_rifireMux_T_260 & out_frontSel_10_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_302 = _out_rifireMux_T_301 & _out_T_1724; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_483 = _out_rifireMux_T_302; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_484 = _out_rifireMux_T_302; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_485 = _out_rifireMux_T_302; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_486 = _out_rifireMux_T_302; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_303 = ~_out_T_1724; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_305 = _out_rifireMux_T_260 & out_frontSel_11_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_306 = _out_rifireMux_T_305; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_309 = _out_rifireMux_T_260 & out_frontSel_12_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_310 = _out_rifireMux_T_309; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_313 = _out_rifireMux_T_260 & out_frontSel_13_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_314 = _out_rifireMux_T_313; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_317 = _out_rifireMux_T_260 & out_frontSel_14_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_318 = _out_rifireMux_T_317; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_321 = _out_rifireMux_T_260 & out_frontSel_15_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_322 = _out_rifireMux_T_321; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_325 = _out_rifireMux_T_260 & out_frontSel_16_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_326 = _out_rifireMux_T_325; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_329 = _out_rifireMux_T_260 & out_frontSel_17_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_330 = _out_rifireMux_T_329; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_333 = _out_rifireMux_T_260 & out_frontSel_18_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_334 = _out_rifireMux_T_333; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_337 = _out_rifireMux_T_260 & out_frontSel_19_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_338 = _out_rifireMux_T_337; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_341 = _out_rifireMux_T_260 & out_frontSel_20_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_342 = _out_rifireMux_T_341; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_345 = _out_rifireMux_T_260 & out_frontSel_21_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_346 = _out_rifireMux_T_345; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_349 = _out_rifireMux_T_260 & out_frontSel_22_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_350 = _out_rifireMux_T_349; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_353 = _out_rifireMux_T_260 & out_frontSel_23_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_354 = _out_rifireMux_T_353; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_357 = _out_rifireMux_T_260 & out_frontSel_24_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_358 = _out_rifireMux_T_357; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_361 = _out_rifireMux_T_260 & out_frontSel_25_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_362 = _out_rifireMux_T_361; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_365 = _out_rifireMux_T_260 & out_frontSel_26_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_366 = _out_rifireMux_T_365; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_369 = _out_rifireMux_T_260 & out_frontSel_27_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_370 = _out_rifireMux_T_369; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_373 = _out_rifireMux_T_260 & out_frontSel_28_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_374 = _out_rifireMux_T_373; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_377 = _out_rifireMux_T_260 & out_frontSel_29_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_378 = _out_rifireMux_T_377; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_381 = _out_rifireMux_T_260 & out_frontSel_30_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_382 = _out_rifireMux_T_381; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_385 = _out_rifireMux_T_260 & out_frontSel_31_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_386 = _out_rifireMux_T_385; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_389 = _out_rifireMux_T_260 & out_frontSel_32_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_390 = _out_rifireMux_T_389 & _out_T_1738; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_535 = _out_rifireMux_T_390; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_536 = _out_rifireMux_T_390; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_391 = ~_out_T_1738; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_393 = _out_rifireMux_T_260 & out_frontSel_33_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_394 = _out_rifireMux_T_393 & _out_T_1688; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_352 = _out_rifireMux_T_394; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_353 = _out_rifireMux_T_394; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_395 = ~_out_T_1688; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_397 = _out_rifireMux_T_260 & out_frontSel_34_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_398 = _out_rifireMux_T_397; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_401 = _out_rifireMux_T_260 & out_frontSel_35_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_402 = _out_rifireMux_T_401; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_405 = _out_rifireMux_T_260 & out_frontSel_36_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_406 = _out_rifireMux_T_405; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_409 = _out_rifireMux_T_260 & out_frontSel_37_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_410 = _out_rifireMux_T_409; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_413 = _out_rifireMux_T_260 & out_frontSel_38_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_414 = _out_rifireMux_T_413; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_417 = _out_rifireMux_T_260 & out_frontSel_39_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_418 = _out_rifireMux_T_417; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_421 = _out_rifireMux_T_260 & out_frontSel_40_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_422 = _out_rifireMux_T_421; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_425 = _out_rifireMux_T_260 & out_frontSel_41_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_426 = _out_rifireMux_T_425; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_429 = _out_rifireMux_T_260 & out_frontSel_42_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_430 = _out_rifireMux_T_429; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_433 = _out_rifireMux_T_260 & out_frontSel_43_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_434 = _out_rifireMux_T_433; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_437 = _out_rifireMux_T_260 & out_frontSel_44_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_438 = _out_rifireMux_T_437; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_441 = _out_rifireMux_T_260 & out_frontSel_45_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_442 = _out_rifireMux_T_441; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_445 = _out_rifireMux_T_260 & out_frontSel_46_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_446 = _out_rifireMux_T_445; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_449 = _out_rifireMux_T_260 & out_frontSel_47_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_450 = _out_rifireMux_T_449; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_453 = _out_rifireMux_T_260 & out_frontSel_48_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_454 = _out_rifireMux_T_453; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_457 = _out_rifireMux_T_260 & out_frontSel_49_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_458 = _out_rifireMux_T_457; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_461 = _out_rifireMux_T_260 & out_frontSel_50_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_462 = _out_rifireMux_T_461; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_465 = _out_rifireMux_T_260 & out_frontSel_51_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_466 = _out_rifireMux_T_465; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_469 = _out_rifireMux_T_260 & out_frontSel_52_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_470 = _out_rifireMux_T_469; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_473 = _out_rifireMux_T_260 & out_frontSel_53_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_474 = _out_rifireMux_T_473; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_477 = _out_rifireMux_T_260 & out_frontSel_54_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_478 = _out_rifireMux_T_477; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_481 = _out_rifireMux_T_260 & out_frontSel_55_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_482 = _out_rifireMux_T_481; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_485 = _out_rifireMux_T_260 & out_frontSel_56_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_486 = _out_rifireMux_T_485; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_489 = _out_rifireMux_T_260 & out_frontSel_57_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_490 = _out_rifireMux_T_489; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_493 = _out_rifireMux_T_260 & out_frontSel_58_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_494 = _out_rifireMux_T_493; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_497 = _out_rifireMux_T_260 & out_frontSel_59_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_498 = _out_rifireMux_T_497; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_501 = _out_rifireMux_T_260 & out_frontSel_60_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_502 = _out_rifireMux_T_501; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_505 = _out_rifireMux_T_260 & out_frontSel_61_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_506 = _out_rifireMux_T_505; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_509 = _out_rifireMux_T_260 & out_frontSel_62_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_510 = _out_rifireMux_T_509; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_513 = _out_rifireMux_T_260 & out_frontSel_63_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_514 = _out_rifireMux_T_513; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_517 = _out_rifireMux_T_260 & out_frontSel_64; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_518 = _out_rifireMux_T_517; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_521 = _out_rifireMux_T_260 & out_frontSel_65; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_522 = _out_rifireMux_T_521; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_525 = _out_rifireMux_T_260 & out_frontSel_66; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_526 = _out_rifireMux_T_525; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_529 = _out_rifireMux_T_260 & out_frontSel_67; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_530 = _out_rifireMux_T_529; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_533 = _out_rifireMux_T_260 & out_frontSel_68; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_534 = _out_rifireMux_T_533; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_537 = _out_rifireMux_T_260 & out_frontSel_69; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_538 = _out_rifireMux_T_537; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_541 = _out_rifireMux_T_260 & out_frontSel_70; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_542 = _out_rifireMux_T_541; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_545 = _out_rifireMux_T_260 & out_frontSel_71; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_546 = _out_rifireMux_T_545; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_549 = _out_rifireMux_T_260 & out_frontSel_72; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_550 = _out_rifireMux_T_549; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_553 = _out_rifireMux_T_260 & out_frontSel_73; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_554 = _out_rifireMux_T_553; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_557 = _out_rifireMux_T_260 & out_frontSel_74; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_558 = _out_rifireMux_T_557; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_561 = _out_rifireMux_T_260 & out_frontSel_75; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_562 = _out_rifireMux_T_561; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_565 = _out_rifireMux_T_260 & out_frontSel_76; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_566 = _out_rifireMux_T_565; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_569 = _out_rifireMux_T_260 & out_frontSel_77; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_570 = _out_rifireMux_T_569; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_573 = _out_rifireMux_T_260 & out_frontSel_78; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_574 = _out_rifireMux_T_573; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_577 = _out_rifireMux_T_260 & out_frontSel_79; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_578 = _out_rifireMux_T_577; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_581 = _out_rifireMux_T_260 & out_frontSel_80; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_582 = _out_rifireMux_T_581; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_585 = _out_rifireMux_T_260 & out_frontSel_81; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_586 = _out_rifireMux_T_585; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_589 = _out_rifireMux_T_260 & out_frontSel_82; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_590 = _out_rifireMux_T_589; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_593 = _out_rifireMux_T_260 & out_frontSel_83; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_594 = _out_rifireMux_T_593; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_597 = _out_rifireMux_T_260 & out_frontSel_84; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_598 = _out_rifireMux_T_597; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_601 = _out_rifireMux_T_260 & out_frontSel_85; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_602 = _out_rifireMux_T_601; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_605 = _out_rifireMux_T_260 & out_frontSel_86; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_606 = _out_rifireMux_T_605; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_609 = _out_rifireMux_T_260 & out_frontSel_87; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_610 = _out_rifireMux_T_609; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_613 = _out_rifireMux_T_260 & out_frontSel_88; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_614 = _out_rifireMux_T_613; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_617 = _out_rifireMux_T_260 & out_frontSel_89; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_618 = _out_rifireMux_T_617; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_621 = _out_rifireMux_T_260 & out_frontSel_90; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_622 = _out_rifireMux_T_621; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_625 = _out_rifireMux_T_260 & out_frontSel_91; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_626 = _out_rifireMux_T_625; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_629 = _out_rifireMux_T_260 & out_frontSel_92; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_630 = _out_rifireMux_T_629; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_633 = _out_rifireMux_T_260 & out_frontSel_93; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_634 = _out_rifireMux_T_633; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_637 = _out_rifireMux_T_260 & out_frontSel_94; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_638 = _out_rifireMux_T_637; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_641 = _out_rifireMux_T_260 & out_frontSel_95; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_642 = _out_rifireMux_T_641; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_645 = _out_rifireMux_T_260 & out_frontSel_96; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_646 = _out_rifireMux_T_645 & _out_T_1712; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_442 = _out_rifireMux_T_646; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_647 = ~_out_T_1712; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_649 = _out_rifireMux_T_260 & out_frontSel_97; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_650 = _out_rifireMux_T_649; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_653 = _out_rifireMux_T_260 & out_frontSel_98; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_654 = _out_rifireMux_T_653; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_657 = _out_rifireMux_T_260 & out_frontSel_99; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_658 = _out_rifireMux_T_657; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_661 = _out_rifireMux_T_260 & out_frontSel_100; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_662 = _out_rifireMux_T_661; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_665 = _out_rifireMux_T_260 & out_frontSel_101; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_666 = _out_rifireMux_T_665; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_669 = _out_rifireMux_T_260 & out_frontSel_102; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_670 = _out_rifireMux_T_669; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_673 = _out_rifireMux_T_260 & out_frontSel_103; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_674 = _out_rifireMux_T_673 & _out_T_1780; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_697 = _out_rifireMux_T_674; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_698 = _out_rifireMux_T_674; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_675 = ~_out_T_1780; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_677 = _out_rifireMux_T_260 & out_frontSel_104; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_678 = _out_rifireMux_T_677 & _out_T_1840; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_931 = _out_rifireMux_T_678; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_932 = _out_rifireMux_T_678; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_933 = _out_rifireMux_T_678; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_934 = _out_rifireMux_T_678; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_935 = _out_rifireMux_T_678; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_936 = _out_rifireMux_T_678; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_937 = _out_rifireMux_T_678; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_938 = _out_rifireMux_T_678; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_679 = ~_out_T_1840; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_681 = _out_rifireMux_T_260 & out_frontSel_105; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_682 = _out_rifireMux_T_681 & _out_T_1732; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_511 = _out_rifireMux_T_682; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_512 = _out_rifireMux_T_682; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_513 = _out_rifireMux_T_682; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_514 = _out_rifireMux_T_682; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_515 = _out_rifireMux_T_682; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_516 = _out_rifireMux_T_682; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_517 = _out_rifireMux_T_682; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_518 = _out_rifireMux_T_682; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_683 = ~_out_T_1732; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_685 = _out_rifireMux_T_260 & out_frontSel_106; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_686 = _out_rifireMux_T_685 & _out_T_1648; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_192 = _out_rifireMux_T_686; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_193 = _out_rifireMux_T_686; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_194 = _out_rifireMux_T_686; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_195 = _out_rifireMux_T_686; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_196 = _out_rifireMux_T_686; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_197 = _out_rifireMux_T_686; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_198 = _out_rifireMux_T_686; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_199 = _out_rifireMux_T_686; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_687 = ~_out_T_1648; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_689 = _out_rifireMux_T_260 & out_frontSel_107; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_690 = _out_rifireMux_T_689 & _out_T_1880; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1091 = _out_rifireMux_T_690; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1092 = _out_rifireMux_T_690; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1093 = _out_rifireMux_T_690; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1094 = _out_rifireMux_T_690; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1095 = _out_rifireMux_T_690; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1096 = _out_rifireMux_T_690; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1097 = _out_rifireMux_T_690; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1098 = _out_rifireMux_T_690; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_691 = ~_out_T_1880; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_693 = _out_rifireMux_T_260 & out_frontSel_108; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_694 = _out_rifireMux_T_693 & _out_T_1790; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_731 = _out_rifireMux_T_694; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_732 = _out_rifireMux_T_694; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_733 = _out_rifireMux_T_694; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_734 = _out_rifireMux_T_694; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_735 = _out_rifireMux_T_694; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_736 = _out_rifireMux_T_694; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_737 = _out_rifireMux_T_694; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_738 = _out_rifireMux_T_694; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_695 = ~_out_T_1790; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_697 = _out_rifireMux_T_260 & out_frontSel_109; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_698 = _out_rifireMux_T_697 & _out_T_1714; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_443 = _out_rifireMux_T_698; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_444 = _out_rifireMux_T_698; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_445 = _out_rifireMux_T_698; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_446 = _out_rifireMux_T_698; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_447 = _out_rifireMux_T_698; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_448 = _out_rifireMux_T_698; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_449 = _out_rifireMux_T_698; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_450 = _out_rifireMux_T_698; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_699 = ~_out_T_1714; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_701 = _out_rifireMux_T_260 & out_frontSel_110; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_702 = _out_rifireMux_T_701 & _out_T_1628; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_112 = _out_rifireMux_T_702; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_113 = _out_rifireMux_T_702; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_114 = _out_rifireMux_T_702; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_115 = _out_rifireMux_T_702; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_116 = _out_rifireMux_T_702; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_117 = _out_rifireMux_T_702; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_118 = _out_rifireMux_T_702; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_119 = _out_rifireMux_T_702; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_703 = ~_out_T_1628; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_705 = _out_rifireMux_T_260 & out_frontSel_111; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_706 = _out_rifireMux_T_705 & _out_T_1898; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1163 = _out_rifireMux_T_706; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1164 = _out_rifireMux_T_706; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1165 = _out_rifireMux_T_706; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1166 = _out_rifireMux_T_706; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1167 = _out_rifireMux_T_706; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1168 = _out_rifireMux_T_706; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1169 = _out_rifireMux_T_706; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1170 = _out_rifireMux_T_706; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_707 = ~_out_T_1898; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_709 = _out_rifireMux_T_260 & out_frontSel_112; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_710 = _out_rifireMux_T_709 & _out_T_1814; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_827 = _out_rifireMux_T_710; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_828 = _out_rifireMux_T_710; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_829 = _out_rifireMux_T_710; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_830 = _out_rifireMux_T_710; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_831 = _out_rifireMux_T_710; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_832 = _out_rifireMux_T_710; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_833 = _out_rifireMux_T_710; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_834 = _out_rifireMux_T_710; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_711 = ~_out_T_1814; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_713 = _out_rifireMux_T_260 & out_frontSel_113; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_714 = _out_rifireMux_T_713 & _out_T_1770; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_657 = _out_rifireMux_T_714; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_658 = _out_rifireMux_T_714; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_659 = _out_rifireMux_T_714; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_660 = _out_rifireMux_T_714; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_661 = _out_rifireMux_T_714; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_662 = _out_rifireMux_T_714; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_663 = _out_rifireMux_T_714; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_664 = _out_rifireMux_T_714; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_715 = ~_out_T_1770; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_717 = _out_rifireMux_T_260 & out_frontSel_114; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_718 = _out_rifireMux_T_717 & _out_T_1852; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_979 = _out_rifireMux_T_718; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_980 = _out_rifireMux_T_718; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_981 = _out_rifireMux_T_718; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_982 = _out_rifireMux_T_718; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_983 = _out_rifireMux_T_718; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_984 = _out_rifireMux_T_718; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_985 = _out_rifireMux_T_718; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_986 = _out_rifireMux_T_718; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_719 = ~_out_T_1852; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_721 = _out_rifireMux_T_260 & out_frontSel_115; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_722 = _out_rifireMux_T_721 & _out_T_1608; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_32 = _out_rifireMux_T_722; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_33 = _out_rifireMux_T_722; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_34 = _out_rifireMux_T_722; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_35 = _out_rifireMux_T_722; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_36 = _out_rifireMux_T_722; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_37 = _out_rifireMux_T_722; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_38 = _out_rifireMux_T_722; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_39 = _out_rifireMux_T_722; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_723 = ~_out_T_1608; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_725 = _out_rifireMux_T_260 & out_frontSel_116; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_726 = _out_rifireMux_T_725; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_729 = _out_rifireMux_T_260 & out_frontSel_117; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_730 = _out_rifireMux_T_729; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_733 = _out_rifireMux_T_260 & out_frontSel_118; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_734 = _out_rifireMux_T_733; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_737 = _out_rifireMux_T_260 & out_frontSel_119; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_738 = _out_rifireMux_T_737; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_741 = _out_rifireMux_T_260 & out_frontSel_120; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_742 = _out_rifireMux_T_741; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_745 = _out_rifireMux_T_260 & out_frontSel_121; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_746 = _out_rifireMux_T_745; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_749 = _out_rifireMux_T_260 & out_frontSel_122; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_750 = _out_rifireMux_T_749; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_753 = _out_rifireMux_T_260 & out_frontSel_123; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_754 = _out_rifireMux_T_753; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_757 = _out_rifireMux_T_260 & out_frontSel_124; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_758 = _out_rifireMux_T_757; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_761 = _out_rifireMux_T_260 & out_frontSel_125; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_762 = _out_rifireMux_T_761; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_765 = _out_rifireMux_T_260 & out_frontSel_126; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_766 = _out_rifireMux_T_765; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_769 = _out_rifireMux_T_260 & out_frontSel_127; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_770 = _out_rifireMux_T_769; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_773 = _out_rifireMux_T_260 & out_frontSel_128; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_774 = _out_rifireMux_T_773 & _out_T_1728; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_495 = _out_rifireMux_T_774; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_496 = _out_rifireMux_T_774; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_497 = _out_rifireMux_T_774; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_498 = _out_rifireMux_T_774; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_499 = _out_rifireMux_T_774; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_500 = _out_rifireMux_T_774; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_501 = _out_rifireMux_T_774; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_502 = _out_rifireMux_T_774; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_775 = ~_out_T_1728; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_777 = _out_rifireMux_T_260 & out_frontSel_129; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_778 = _out_rifireMux_T_777 & _out_T_1720; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_467 = _out_rifireMux_T_778; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_468 = _out_rifireMux_T_778; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_469 = _out_rifireMux_T_778; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_470 = _out_rifireMux_T_778; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_471 = _out_rifireMux_T_778; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_472 = _out_rifireMux_T_778; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_473 = _out_rifireMux_T_778; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_474 = _out_rifireMux_T_778; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_779 = ~_out_T_1720; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_781 = _out_rifireMux_T_260 & out_frontSel_130; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_782 = _out_rifireMux_T_781 & _out_T_1796; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_755 = _out_rifireMux_T_782; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_756 = _out_rifireMux_T_782; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_757 = _out_rifireMux_T_782; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_758 = _out_rifireMux_T_782; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_759 = _out_rifireMux_T_782; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_760 = _out_rifireMux_T_782; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_761 = _out_rifireMux_T_782; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_762 = _out_rifireMux_T_782; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_783 = ~_out_T_1796; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_785 = _out_rifireMux_T_260 & out_frontSel_131; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_786 = _out_rifireMux_T_785 & _out_T_1890; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1131 = _out_rifireMux_T_786; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1132 = _out_rifireMux_T_786; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1133 = _out_rifireMux_T_786; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1134 = _out_rifireMux_T_786; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1135 = _out_rifireMux_T_786; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1136 = _out_rifireMux_T_786; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1137 = _out_rifireMux_T_786; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1138 = _out_rifireMux_T_786; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_787 = ~_out_T_1890; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_789 = _out_rifireMux_T_260 & out_frontSel_132; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_790 = _out_rifireMux_T_789 & _out_T_1660; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_240 = _out_rifireMux_T_790; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_241 = _out_rifireMux_T_790; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_242 = _out_rifireMux_T_790; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_243 = _out_rifireMux_T_790; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_244 = _out_rifireMux_T_790; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_245 = _out_rifireMux_T_790; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_246 = _out_rifireMux_T_790; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_247 = _out_rifireMux_T_790; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_791 = ~_out_T_1660; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_793 = _out_rifireMux_T_260 & out_frontSel_133; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_794 = _out_rifireMux_T_793 & _out_T_1662; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_248 = _out_rifireMux_T_794; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_249 = _out_rifireMux_T_794; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_250 = _out_rifireMux_T_794; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_251 = _out_rifireMux_T_794; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_252 = _out_rifireMux_T_794; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_253 = _out_rifireMux_T_794; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_254 = _out_rifireMux_T_794; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_255 = _out_rifireMux_T_794; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_795 = ~_out_T_1662; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_797 = _out_rifireMux_T_260 & out_frontSel_134; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_798 = _out_rifireMux_T_797 & _out_T_1722; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_475 = _out_rifireMux_T_798; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_476 = _out_rifireMux_T_798; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_477 = _out_rifireMux_T_798; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_478 = _out_rifireMux_T_798; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_479 = _out_rifireMux_T_798; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_480 = _out_rifireMux_T_798; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_481 = _out_rifireMux_T_798; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_482 = _out_rifireMux_T_798; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_799 = ~_out_T_1722; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_801 = _out_rifireMux_T_260 & out_frontSel_135; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_802 = _out_rifireMux_T_801 & _out_T_1800; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_771 = _out_rifireMux_T_802; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_772 = _out_rifireMux_T_802; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_773 = _out_rifireMux_T_802; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_774 = _out_rifireMux_T_802; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_775 = _out_rifireMux_T_802; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_776 = _out_rifireMux_T_802; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_777 = _out_rifireMux_T_802; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_778 = _out_rifireMux_T_802; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_803 = ~_out_T_1800; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_805 = _out_rifireMux_T_260 & out_frontSel_136; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_806 = _out_rifireMux_T_805 & _out_T_1882; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1099 = _out_rifireMux_T_806; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1100 = _out_rifireMux_T_806; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1101 = _out_rifireMux_T_806; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1102 = _out_rifireMux_T_806; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1103 = _out_rifireMux_T_806; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1104 = _out_rifireMux_T_806; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1105 = _out_rifireMux_T_806; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1106 = _out_rifireMux_T_806; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_807 = ~_out_T_1882; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_809 = _out_rifireMux_T_260 & out_frontSel_137; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_810 = _out_rifireMux_T_809 & _out_T_1684; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_336 = _out_rifireMux_T_810; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_337 = _out_rifireMux_T_810; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_338 = _out_rifireMux_T_810; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_339 = _out_rifireMux_T_810; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_340 = _out_rifireMux_T_810; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_341 = _out_rifireMux_T_810; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_342 = _out_rifireMux_T_810; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_343 = _out_rifireMux_T_810; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_811 = ~_out_T_1684; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_813 = _out_rifireMux_T_260 & out_frontSel_138; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_814 = _out_rifireMux_T_813 & _out_T_1600; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_0 = _out_rifireMux_T_814; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1 = _out_rifireMux_T_814; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_2 = _out_rifireMux_T_814; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_3 = _out_rifireMux_T_814; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_4 = _out_rifireMux_T_814; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_5 = _out_rifireMux_T_814; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_6 = _out_rifireMux_T_814; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_7 = _out_rifireMux_T_814; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_815 = ~_out_T_1600; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_817 = _out_rifireMux_T_260 & out_frontSel_139; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_818 = _out_rifireMux_T_817 & _out_T_1856; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_995 = _out_rifireMux_T_818; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_996 = _out_rifireMux_T_818; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_997 = _out_rifireMux_T_818; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_998 = _out_rifireMux_T_818; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_999 = _out_rifireMux_T_818; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1000 = _out_rifireMux_T_818; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1001 = _out_rifireMux_T_818; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1002 = _out_rifireMux_T_818; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_819 = ~_out_T_1856; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_821 = _out_rifireMux_T_260 & out_frontSel_140; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_822 = _out_rifireMux_T_821 & _out_T_1782; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_699 = _out_rifireMux_T_822; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_700 = _out_rifireMux_T_822; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_701 = _out_rifireMux_T_822; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_702 = _out_rifireMux_T_822; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_703 = _out_rifireMux_T_822; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_704 = _out_rifireMux_T_822; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_705 = _out_rifireMux_T_822; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_706 = _out_rifireMux_T_822; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_823 = ~_out_T_1782; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_825 = _out_rifireMux_T_260 & out_frontSel_141; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_826 = _out_rifireMux_T_825 & _out_T_1704; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_410 = _out_rifireMux_T_826; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_411 = _out_rifireMux_T_826; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_412 = _out_rifireMux_T_826; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_413 = _out_rifireMux_T_826; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_414 = _out_rifireMux_T_826; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_415 = _out_rifireMux_T_826; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_416 = _out_rifireMux_T_826; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_417 = _out_rifireMux_T_826; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_827 = ~_out_T_1704; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_829 = _out_rifireMux_T_260 & out_frontSel_142; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_830 = _out_rifireMux_T_829 & _out_T_1616; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_64 = _out_rifireMux_T_830; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_65 = _out_rifireMux_T_830; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_66 = _out_rifireMux_T_830; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_67 = _out_rifireMux_T_830; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_68 = _out_rifireMux_T_830; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_69 = _out_rifireMux_T_830; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_70 = _out_rifireMux_T_830; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_71 = _out_rifireMux_T_830; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_831 = ~_out_T_1616; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_833 = _out_rifireMux_T_260 & out_frontSel_143; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_834 = _out_rifireMux_T_833 & _out_T_1834; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_907 = _out_rifireMux_T_834; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_908 = _out_rifireMux_T_834; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_909 = _out_rifireMux_T_834; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_910 = _out_rifireMux_T_834; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_911 = _out_rifireMux_T_834; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_912 = _out_rifireMux_T_834; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_913 = _out_rifireMux_T_834; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_914 = _out_rifireMux_T_834; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_835 = ~_out_T_1834; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_837 = _out_rifireMux_T_260 & out_frontSel_144; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_838 = _out_rifireMux_T_837 & _out_T_1758; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_609 = _out_rifireMux_T_838; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_610 = _out_rifireMux_T_838; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_611 = _out_rifireMux_T_838; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_612 = _out_rifireMux_T_838; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_613 = _out_rifireMux_T_838; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_614 = _out_rifireMux_T_838; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_615 = _out_rifireMux_T_838; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_616 = _out_rifireMux_T_838; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_839 = ~_out_T_1758; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_841 = _out_rifireMux_T_260 & out_frontSel_145; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_842 = _out_rifireMux_T_841 & _out_T_1818; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_843 = _out_rifireMux_T_842; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_844 = _out_rifireMux_T_842; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_845 = _out_rifireMux_T_842; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_846 = _out_rifireMux_T_842; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_847 = _out_rifireMux_T_842; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_848 = _out_rifireMux_T_842; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_849 = _out_rifireMux_T_842; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_850 = _out_rifireMux_T_842; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_843 = ~_out_T_1818; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_845 = _out_rifireMux_T_260 & out_frontSel_146; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_846 = _out_rifireMux_T_845 & _out_T_1868; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1043 = _out_rifireMux_T_846; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1044 = _out_rifireMux_T_846; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1045 = _out_rifireMux_T_846; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1046 = _out_rifireMux_T_846; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1047 = _out_rifireMux_T_846; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1048 = _out_rifireMux_T_846; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1049 = _out_rifireMux_T_846; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1050 = _out_rifireMux_T_846; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_847 = ~_out_T_1868; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_849 = _out_rifireMux_T_260 & out_frontSel_147; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_850 = _out_rifireMux_T_849 & _out_T_1656; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_224 = _out_rifireMux_T_850; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_225 = _out_rifireMux_T_850; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_226 = _out_rifireMux_T_850; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_227 = _out_rifireMux_T_850; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_228 = _out_rifireMux_T_850; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_229 = _out_rifireMux_T_850; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_230 = _out_rifireMux_T_850; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_231 = _out_rifireMux_T_850; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_851 = ~_out_T_1656; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_853 = _out_rifireMux_T_260 & out_frontSel_148; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_854 = _out_rifireMux_T_853 & _out_T_1740; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_537 = _out_rifireMux_T_854; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_538 = _out_rifireMux_T_854; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_539 = _out_rifireMux_T_854; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_540 = _out_rifireMux_T_854; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_541 = _out_rifireMux_T_854; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_542 = _out_rifireMux_T_854; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_543 = _out_rifireMux_T_854; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_544 = _out_rifireMux_T_854; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_855 = ~_out_T_1740; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_857 = _out_rifireMux_T_260 & out_frontSel_149; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_858 = _out_rifireMux_T_857 & _out_T_1748; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_569 = _out_rifireMux_T_858; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_570 = _out_rifireMux_T_858; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_571 = _out_rifireMux_T_858; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_572 = _out_rifireMux_T_858; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_573 = _out_rifireMux_T_858; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_574 = _out_rifireMux_T_858; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_575 = _out_rifireMux_T_858; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_576 = _out_rifireMux_T_858; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_859 = ~_out_T_1748; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_861 = _out_rifireMux_T_260 & out_frontSel_150; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_862 = _out_rifireMux_T_861 & _out_T_1820; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_851 = _out_rifireMux_T_862; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_852 = _out_rifireMux_T_862; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_853 = _out_rifireMux_T_862; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_854 = _out_rifireMux_T_862; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_855 = _out_rifireMux_T_862; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_856 = _out_rifireMux_T_862; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_857 = _out_rifireMux_T_862; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_858 = _out_rifireMux_T_862; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_863 = ~_out_T_1820; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_865 = _out_rifireMux_T_260 & out_frontSel_151; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_866 = _out_rifireMux_T_865 & _out_T_1866; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1035 = _out_rifireMux_T_866; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1036 = _out_rifireMux_T_866; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1037 = _out_rifireMux_T_866; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1038 = _out_rifireMux_T_866; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1039 = _out_rifireMux_T_866; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1040 = _out_rifireMux_T_866; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1041 = _out_rifireMux_T_866; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1042 = _out_rifireMux_T_866; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_867 = ~_out_T_1866; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_869 = _out_rifireMux_T_260 & out_frontSel_152; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_870 = _out_rifireMux_T_869 & _out_T_1636; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_144 = _out_rifireMux_T_870; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_145 = _out_rifireMux_T_870; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_146 = _out_rifireMux_T_870; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_147 = _out_rifireMux_T_870; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_148 = _out_rifireMux_T_870; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_149 = _out_rifireMux_T_870; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_150 = _out_rifireMux_T_870; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_151 = _out_rifireMux_T_870; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_871 = ~_out_T_1636; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_873 = _out_rifireMux_T_260 & out_frontSel_153; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_874 = _out_rifireMux_T_873 & _out_T_1618; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_72 = _out_rifireMux_T_874; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_73 = _out_rifireMux_T_874; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_74 = _out_rifireMux_T_874; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_75 = _out_rifireMux_T_874; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_76 = _out_rifireMux_T_874; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_77 = _out_rifireMux_T_874; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_78 = _out_rifireMux_T_874; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_79 = _out_rifireMux_T_874; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_875 = ~_out_T_1618; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_877 = _out_rifireMux_T_260 & out_frontSel_154; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_878 = _out_rifireMux_T_877 & _out_T_1830; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_891 = _out_rifireMux_T_878; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_892 = _out_rifireMux_T_878; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_893 = _out_rifireMux_T_878; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_894 = _out_rifireMux_T_878; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_895 = _out_rifireMux_T_878; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_896 = _out_rifireMux_T_878; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_897 = _out_rifireMux_T_878; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_898 = _out_rifireMux_T_878; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_879 = ~_out_T_1830; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_881 = _out_rifireMux_T_260 & out_frontSel_155; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_882 = _out_rifireMux_T_881 & _out_T_1786; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_715 = _out_rifireMux_T_882; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_716 = _out_rifireMux_T_882; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_717 = _out_rifireMux_T_882; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_718 = _out_rifireMux_T_882; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_719 = _out_rifireMux_T_882; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_720 = _out_rifireMux_T_882; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_721 = _out_rifireMux_T_882; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_722 = _out_rifireMux_T_882; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_883 = ~_out_T_1786; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_885 = _out_rifireMux_T_260 & out_frontSel_156; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_886 = _out_rifireMux_T_885 & _out_T_1698; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_386 = _out_rifireMux_T_886; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_387 = _out_rifireMux_T_886; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_388 = _out_rifireMux_T_886; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_389 = _out_rifireMux_T_886; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_390 = _out_rifireMux_T_886; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_391 = _out_rifireMux_T_886; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_392 = _out_rifireMux_T_886; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_393 = _out_rifireMux_T_886; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_887 = ~_out_T_1698; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_889 = _out_rifireMux_T_260 & out_frontSel_157; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_890 = _out_rifireMux_T_889 & _out_T_1632; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_128 = _out_rifireMux_T_890; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_129 = _out_rifireMux_T_890; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_130 = _out_rifireMux_T_890; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_131 = _out_rifireMux_T_890; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_132 = _out_rifireMux_T_890; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_133 = _out_rifireMux_T_890; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_134 = _out_rifireMux_T_890; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_135 = _out_rifireMux_T_890; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_891 = ~_out_T_1632; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_893 = _out_rifireMux_T_260 & out_frontSel_158; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_894 = _out_rifireMux_T_893 & _out_T_1848; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_963 = _out_rifireMux_T_894; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_964 = _out_rifireMux_T_894; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_965 = _out_rifireMux_T_894; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_966 = _out_rifireMux_T_894; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_967 = _out_rifireMux_T_894; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_968 = _out_rifireMux_T_894; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_969 = _out_rifireMux_T_894; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_970 = _out_rifireMux_T_894; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_895 = ~_out_T_1848; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_897 = _out_rifireMux_T_260 & out_frontSel_159; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_898 = _out_rifireMux_T_897 & _out_T_1764; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_633 = _out_rifireMux_T_898; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_634 = _out_rifireMux_T_898; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_635 = _out_rifireMux_T_898; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_636 = _out_rifireMux_T_898; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_637 = _out_rifireMux_T_898; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_638 = _out_rifireMux_T_898; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_639 = _out_rifireMux_T_898; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_640 = _out_rifireMux_T_898; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_899 = ~_out_T_1764; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_901 = _out_rifireMux_T_260 & out_frontSel_160; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_902 = _out_rifireMux_T_901 & _out_T_1680; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_320 = _out_rifireMux_T_902; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_321 = _out_rifireMux_T_902; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_322 = _out_rifireMux_T_902; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_323 = _out_rifireMux_T_902; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_324 = _out_rifireMux_T_902; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_325 = _out_rifireMux_T_902; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_326 = _out_rifireMux_T_902; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_327 = _out_rifireMux_T_902; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_903 = ~_out_T_1680; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_905 = _out_rifireMux_T_260 & out_frontSel_161; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_906 = _out_rifireMux_T_905 & _out_T_1744; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_553 = _out_rifireMux_T_906; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_554 = _out_rifireMux_T_906; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_555 = _out_rifireMux_T_906; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_556 = _out_rifireMux_T_906; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_557 = _out_rifireMux_T_906; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_558 = _out_rifireMux_T_906; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_559 = _out_rifireMux_T_906; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_560 = _out_rifireMux_T_906; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_907 = ~_out_T_1744; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_909 = _out_rifireMux_T_260 & out_frontSel_162; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_910 = _out_rifireMux_T_909 & _out_T_1808; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_803 = _out_rifireMux_T_910; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_804 = _out_rifireMux_T_910; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_805 = _out_rifireMux_T_910; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_806 = _out_rifireMux_T_910; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_807 = _out_rifireMux_T_910; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_808 = _out_rifireMux_T_910; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_809 = _out_rifireMux_T_910; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_810 = _out_rifireMux_T_910; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_911 = ~_out_T_1808; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_913 = _out_rifireMux_T_260 & out_frontSel_163; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_914 = _out_rifireMux_T_913 & _out_T_1894; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1147 = _out_rifireMux_T_914; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1148 = _out_rifireMux_T_914; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1149 = _out_rifireMux_T_914; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1150 = _out_rifireMux_T_914; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1151 = _out_rifireMux_T_914; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1152 = _out_rifireMux_T_914; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1153 = _out_rifireMux_T_914; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1154 = _out_rifireMux_T_914; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_915 = ~_out_T_1894; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_917 = _out_rifireMux_T_260 & out_frontSel_164; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_918 = _out_rifireMux_T_917 & _out_T_1644; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_176 = _out_rifireMux_T_918; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_177 = _out_rifireMux_T_918; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_178 = _out_rifireMux_T_918; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_179 = _out_rifireMux_T_918; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_180 = _out_rifireMux_T_918; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_181 = _out_rifireMux_T_918; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_182 = _out_rifireMux_T_918; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_183 = _out_rifireMux_T_918; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_919 = ~_out_T_1644; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_921 = _out_rifireMux_T_260 & out_frontSel_165; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_922 = _out_rifireMux_T_921 & _out_T_1686; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_344 = _out_rifireMux_T_922; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_345 = _out_rifireMux_T_922; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_346 = _out_rifireMux_T_922; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_347 = _out_rifireMux_T_922; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_348 = _out_rifireMux_T_922; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_349 = _out_rifireMux_T_922; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_350 = _out_rifireMux_T_922; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_351 = _out_rifireMux_T_922; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_923 = ~_out_T_1686; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_925 = _out_rifireMux_T_260 & out_frontSel_166; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_926 = _out_rifireMux_T_925 & _out_T_1736; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_527 = _out_rifireMux_T_926; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_528 = _out_rifireMux_T_926; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_529 = _out_rifireMux_T_926; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_530 = _out_rifireMux_T_926; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_531 = _out_rifireMux_T_926; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_532 = _out_rifireMux_T_926; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_533 = _out_rifireMux_T_926; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_534 = _out_rifireMux_T_926; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_927 = ~_out_T_1736; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_929 = _out_rifireMux_T_260 & out_frontSel_167; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_930 = _out_rifireMux_T_929 & _out_T_1806; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_795 = _out_rifireMux_T_930; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_796 = _out_rifireMux_T_930; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_797 = _out_rifireMux_T_930; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_798 = _out_rifireMux_T_930; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_799 = _out_rifireMux_T_930; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_800 = _out_rifireMux_T_930; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_801 = _out_rifireMux_T_930; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_802 = _out_rifireMux_T_930; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_931 = ~_out_T_1806; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_933 = _out_rifireMux_T_260 & out_frontSel_168; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_934 = _out_rifireMux_T_933 & _out_T_1874; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1067 = _out_rifireMux_T_934; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1068 = _out_rifireMux_T_934; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1069 = _out_rifireMux_T_934; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1070 = _out_rifireMux_T_934; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1071 = _out_rifireMux_T_934; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1072 = _out_rifireMux_T_934; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1073 = _out_rifireMux_T_934; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1074 = _out_rifireMux_T_934; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_935 = ~_out_T_1874; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_937 = _out_rifireMux_T_260 & out_frontSel_169; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_938 = _out_rifireMux_T_937 & _out_T_1702; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_402 = _out_rifireMux_T_938; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_403 = _out_rifireMux_T_938; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_404 = _out_rifireMux_T_938; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_405 = _out_rifireMux_T_938; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_406 = _out_rifireMux_T_938; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_407 = _out_rifireMux_T_938; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_408 = _out_rifireMux_T_938; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_409 = _out_rifireMux_T_938; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_939 = ~_out_T_1702; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_941 = _out_rifireMux_T_260 & out_frontSel_170; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_942 = _out_rifireMux_T_941 & _out_T_1606; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_24 = _out_rifireMux_T_942; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_25 = _out_rifireMux_T_942; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_26 = _out_rifireMux_T_942; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_27 = _out_rifireMux_T_942; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_28 = _out_rifireMux_T_942; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_29 = _out_rifireMux_T_942; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_30 = _out_rifireMux_T_942; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_31 = _out_rifireMux_T_942; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_943 = ~_out_T_1606; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_945 = _out_rifireMux_T_260 & out_frontSel_171; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_946 = _out_rifireMux_T_945 & _out_T_1854; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_987 = _out_rifireMux_T_946; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_988 = _out_rifireMux_T_946; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_989 = _out_rifireMux_T_946; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_990 = _out_rifireMux_T_946; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_991 = _out_rifireMux_T_946; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_992 = _out_rifireMux_T_946; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_993 = _out_rifireMux_T_946; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_994 = _out_rifireMux_T_946; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_947 = ~_out_T_1854; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_949 = _out_rifireMux_T_260 & out_frontSel_172; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_950 = _out_rifireMux_T_949 & _out_T_1768; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_649 = _out_rifireMux_T_950; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_650 = _out_rifireMux_T_950; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_651 = _out_rifireMux_T_950; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_652 = _out_rifireMux_T_950; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_653 = _out_rifireMux_T_950; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_654 = _out_rifireMux_T_950; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_655 = _out_rifireMux_T_950; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_656 = _out_rifireMux_T_950; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_951 = ~_out_T_1768; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_953 = _out_rifireMux_T_260 & out_frontSel_173; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_954 = _out_rifireMux_T_953 & _out_T_1718; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_459 = _out_rifireMux_T_954; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_460 = _out_rifireMux_T_954; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_461 = _out_rifireMux_T_954; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_462 = _out_rifireMux_T_954; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_463 = _out_rifireMux_T_954; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_464 = _out_rifireMux_T_954; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_465 = _out_rifireMux_T_954; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_466 = _out_rifireMux_T_954; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_955 = ~_out_T_1718; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_957 = _out_rifireMux_T_260 & out_frontSel_174; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_958 = _out_rifireMux_T_957 & _out_T_1620; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_80 = _out_rifireMux_T_958; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_81 = _out_rifireMux_T_958; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_82 = _out_rifireMux_T_958; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_83 = _out_rifireMux_T_958; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_84 = _out_rifireMux_T_958; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_85 = _out_rifireMux_T_958; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_86 = _out_rifireMux_T_958; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_87 = _out_rifireMux_T_958; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_959 = ~_out_T_1620; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_961 = _out_rifireMux_T_260 & out_frontSel_175; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_962 = _out_rifireMux_T_961 & _out_T_1832; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_899 = _out_rifireMux_T_962; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_900 = _out_rifireMux_T_962; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_901 = _out_rifireMux_T_962; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_902 = _out_rifireMux_T_962; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_903 = _out_rifireMux_T_962; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_904 = _out_rifireMux_T_962; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_905 = _out_rifireMux_T_962; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_906 = _out_rifireMux_T_962; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_963 = ~_out_T_1832; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_965 = _out_rifireMux_T_260 & out_frontSel_176; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_966 = _out_rifireMux_T_965 & _out_T_1750; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_577 = _out_rifireMux_T_966; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_578 = _out_rifireMux_T_966; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_579 = _out_rifireMux_T_966; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_580 = _out_rifireMux_T_966; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_581 = _out_rifireMux_T_966; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_582 = _out_rifireMux_T_966; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_583 = _out_rifireMux_T_966; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_584 = _out_rifireMux_T_966; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_967 = ~_out_T_1750; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_969 = _out_rifireMux_T_260 & out_frontSel_177; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_970 = _out_rifireMux_T_969 & _out_T_1826; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_875 = _out_rifireMux_T_970; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_876 = _out_rifireMux_T_970; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_877 = _out_rifireMux_T_970; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_878 = _out_rifireMux_T_970; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_879 = _out_rifireMux_T_970; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_880 = _out_rifireMux_T_970; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_881 = _out_rifireMux_T_970; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_882 = _out_rifireMux_T_970; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_971 = ~_out_T_1826; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_973 = _out_rifireMux_T_260 & out_frontSel_178; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_974 = _out_rifireMux_T_973 & _out_T_1892; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1139 = _out_rifireMux_T_974; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1140 = _out_rifireMux_T_974; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1141 = _out_rifireMux_T_974; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1142 = _out_rifireMux_T_974; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1143 = _out_rifireMux_T_974; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1144 = _out_rifireMux_T_974; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1145 = _out_rifireMux_T_974; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1146 = _out_rifireMux_T_974; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_975 = ~_out_T_1892; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_977 = _out_rifireMux_T_260 & out_frontSel_179; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_978 = _out_rifireMux_T_977 & _out_T_1646; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_184 = _out_rifireMux_T_978; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_185 = _out_rifireMux_T_978; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_186 = _out_rifireMux_T_978; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_187 = _out_rifireMux_T_978; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_188 = _out_rifireMux_T_978; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_189 = _out_rifireMux_T_978; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_190 = _out_rifireMux_T_978; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_191 = _out_rifireMux_T_978; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_979 = ~_out_T_1646; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_981 = _out_rifireMux_T_260 & out_frontSel_180; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_982 = _out_rifireMux_T_981 & _out_T_1746; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_561 = _out_rifireMux_T_982; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_562 = _out_rifireMux_T_982; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_563 = _out_rifireMux_T_982; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_564 = _out_rifireMux_T_982; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_565 = _out_rifireMux_T_982; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_566 = _out_rifireMux_T_982; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_567 = _out_rifireMux_T_982; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_568 = _out_rifireMux_T_982; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_983 = ~_out_T_1746; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_985 = _out_rifireMux_T_260 & out_frontSel_181; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_986 = _out_rifireMux_T_985 & _out_T_1762; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_625 = _out_rifireMux_T_986; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_626 = _out_rifireMux_T_986; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_627 = _out_rifireMux_T_986; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_628 = _out_rifireMux_T_986; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_629 = _out_rifireMux_T_986; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_630 = _out_rifireMux_T_986; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_631 = _out_rifireMux_T_986; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_632 = _out_rifireMux_T_986; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_987 = ~_out_T_1762; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_989 = _out_rifireMux_T_260 & out_frontSel_182; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_990 = _out_rifireMux_T_989 & _out_T_1828; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_883 = _out_rifireMux_T_990; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_884 = _out_rifireMux_T_990; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_885 = _out_rifireMux_T_990; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_886 = _out_rifireMux_T_990; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_887 = _out_rifireMux_T_990; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_888 = _out_rifireMux_T_990; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_889 = _out_rifireMux_T_990; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_890 = _out_rifireMux_T_990; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_991 = ~_out_T_1828; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_993 = _out_rifireMux_T_260 & out_frontSel_183; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_994 = _out_rifireMux_T_993 & _out_T_1872; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1059 = _out_rifireMux_T_994; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1060 = _out_rifireMux_T_994; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1061 = _out_rifireMux_T_994; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1062 = _out_rifireMux_T_994; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1063 = _out_rifireMux_T_994; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1064 = _out_rifireMux_T_994; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1065 = _out_rifireMux_T_994; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1066 = _out_rifireMux_T_994; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_995 = ~_out_T_1872; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_997 = _out_rifireMux_T_260 & out_frontSel_184; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_998 = _out_rifireMux_T_997 & _out_T_1626; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_104 = _out_rifireMux_T_998; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_105 = _out_rifireMux_T_998; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_106 = _out_rifireMux_T_998; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_107 = _out_rifireMux_T_998; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_108 = _out_rifireMux_T_998; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_109 = _out_rifireMux_T_998; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_110 = _out_rifireMux_T_998; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_111 = _out_rifireMux_T_998; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_999 = ~_out_T_1626; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1001 = _out_rifireMux_T_260 & out_frontSel_185; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1002 = _out_rifireMux_T_1001 & _out_T_1622; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_88 = _out_rifireMux_T_1002; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_89 = _out_rifireMux_T_1002; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_90 = _out_rifireMux_T_1002; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_91 = _out_rifireMux_T_1002; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_92 = _out_rifireMux_T_1002; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_93 = _out_rifireMux_T_1002; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_94 = _out_rifireMux_T_1002; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_95 = _out_rifireMux_T_1002; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1003 = ~_out_T_1622; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1005 = _out_rifireMux_T_260 & out_frontSel_186; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1006 = _out_rifireMux_T_1005 & _out_T_1850; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_971 = _out_rifireMux_T_1006; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_972 = _out_rifireMux_T_1006; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_973 = _out_rifireMux_T_1006; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_974 = _out_rifireMux_T_1006; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_975 = _out_rifireMux_T_1006; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_976 = _out_rifireMux_T_1006; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_977 = _out_rifireMux_T_1006; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_978 = _out_rifireMux_T_1006; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1007 = ~_out_T_1850; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1009 = _out_rifireMux_T_260 & out_frontSel_187; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1010 = _out_rifireMux_T_1009 & _out_T_1766; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_641 = _out_rifireMux_T_1010; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_642 = _out_rifireMux_T_1010; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_643 = _out_rifireMux_T_1010; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_644 = _out_rifireMux_T_1010; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_645 = _out_rifireMux_T_1010; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_646 = _out_rifireMux_T_1010; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_647 = _out_rifireMux_T_1010; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_648 = _out_rifireMux_T_1010; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1011 = ~_out_T_1766; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1013 = _out_rifireMux_T_260 & out_frontSel_188; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1014 = _out_rifireMux_T_1013 & _out_T_1700; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_394 = _out_rifireMux_T_1014; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_395 = _out_rifireMux_T_1014; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_396 = _out_rifireMux_T_1014; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_397 = _out_rifireMux_T_1014; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_398 = _out_rifireMux_T_1014; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_399 = _out_rifireMux_T_1014; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_400 = _out_rifireMux_T_1014; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_401 = _out_rifireMux_T_1014; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1015 = ~_out_T_1700; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1017 = _out_rifireMux_T_260 & out_frontSel_189; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1018 = _out_rifireMux_T_1017 & _out_T_1634; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_136 = _out_rifireMux_T_1018; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_137 = _out_rifireMux_T_1018; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_138 = _out_rifireMux_T_1018; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_139 = _out_rifireMux_T_1018; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_140 = _out_rifireMux_T_1018; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_141 = _out_rifireMux_T_1018; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_142 = _out_rifireMux_T_1018; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_143 = _out_rifireMux_T_1018; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1019 = ~_out_T_1634; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1021 = _out_rifireMux_T_260 & out_frontSel_190; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1022 = _out_rifireMux_T_1021 & _out_T_1870; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1051 = _out_rifireMux_T_1022; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1052 = _out_rifireMux_T_1022; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1053 = _out_rifireMux_T_1022; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1054 = _out_rifireMux_T_1022; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1055 = _out_rifireMux_T_1022; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1056 = _out_rifireMux_T_1022; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1057 = _out_rifireMux_T_1022; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1058 = _out_rifireMux_T_1022; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1023 = ~_out_T_1870; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1025 = _out_rifireMux_T_260 & out_frontSel_191; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1026 = _out_rifireMux_T_1025 & _out_T_1752; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_585 = _out_rifireMux_T_1026; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_586 = _out_rifireMux_T_1026; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_587 = _out_rifireMux_T_1026; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_588 = _out_rifireMux_T_1026; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_589 = _out_rifireMux_T_1026; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_590 = _out_rifireMux_T_1026; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_591 = _out_rifireMux_T_1026; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_592 = _out_rifireMux_T_1026; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1027 = ~_out_T_1752; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1029 = _out_rifireMux_T_260 & out_frontSel_192; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1030 = _out_rifireMux_T_1029 & _out_T_1682; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_328 = _out_rifireMux_T_1030; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_329 = _out_rifireMux_T_1030; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_330 = _out_rifireMux_T_1030; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_331 = _out_rifireMux_T_1030; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_332 = _out_rifireMux_T_1030; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_333 = _out_rifireMux_T_1030; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_334 = _out_rifireMux_T_1030; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_335 = _out_rifireMux_T_1030; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1031 = ~_out_T_1682; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1033 = _out_rifireMux_T_260 & out_frontSel_193; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1034 = _out_rifireMux_T_1033 & _out_T_1708; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_426 = _out_rifireMux_T_1034; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_427 = _out_rifireMux_T_1034; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_428 = _out_rifireMux_T_1034; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_429 = _out_rifireMux_T_1034; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_430 = _out_rifireMux_T_1034; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_431 = _out_rifireMux_T_1034; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_432 = _out_rifireMux_T_1034; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_433 = _out_rifireMux_T_1034; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1035 = ~_out_T_1708; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1037 = _out_rifireMux_T_260 & out_frontSel_194; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1038 = _out_rifireMux_T_1037 & _out_T_1816; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_835 = _out_rifireMux_T_1038; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_836 = _out_rifireMux_T_1038; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_837 = _out_rifireMux_T_1038; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_838 = _out_rifireMux_T_1038; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_839 = _out_rifireMux_T_1038; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_840 = _out_rifireMux_T_1038; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_841 = _out_rifireMux_T_1038; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_842 = _out_rifireMux_T_1038; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1039 = ~_out_T_1816; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1041 = _out_rifireMux_T_260 & out_frontSel_195; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1042 = _out_rifireMux_T_1041 & _out_T_1884; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1107 = _out_rifireMux_T_1042; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1108 = _out_rifireMux_T_1042; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1109 = _out_rifireMux_T_1042; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1110 = _out_rifireMux_T_1042; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1111 = _out_rifireMux_T_1042; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1112 = _out_rifireMux_T_1042; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1113 = _out_rifireMux_T_1042; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1114 = _out_rifireMux_T_1042; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1043 = ~_out_T_1884; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1045 = _out_rifireMux_T_260 & out_frontSel_196; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1046 = _out_rifireMux_T_1045 & _out_T_1630; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_120 = _out_rifireMux_T_1046; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_121 = _out_rifireMux_T_1046; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_122 = _out_rifireMux_T_1046; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_123 = _out_rifireMux_T_1046; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_124 = _out_rifireMux_T_1046; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_125 = _out_rifireMux_T_1046; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_126 = _out_rifireMux_T_1046; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_127 = _out_rifireMux_T_1046; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1047 = ~_out_T_1630; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1049 = _out_rifireMux_T_260 & out_frontSel_197; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1050 = _out_rifireMux_T_1049 & _out_T_1694; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_370 = _out_rifireMux_T_1050; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_371 = _out_rifireMux_T_1050; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_372 = _out_rifireMux_T_1050; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_373 = _out_rifireMux_T_1050; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_374 = _out_rifireMux_T_1050; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_375 = _out_rifireMux_T_1050; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_376 = _out_rifireMux_T_1050; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_377 = _out_rifireMux_T_1050; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1051 = ~_out_T_1694; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1053 = _out_rifireMux_T_260 & out_frontSel_198; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1054 = _out_rifireMux_T_1053 & _out_T_1788; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_723 = _out_rifireMux_T_1054; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_724 = _out_rifireMux_T_1054; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_725 = _out_rifireMux_T_1054; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_726 = _out_rifireMux_T_1054; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_727 = _out_rifireMux_T_1054; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_728 = _out_rifireMux_T_1054; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_729 = _out_rifireMux_T_1054; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_730 = _out_rifireMux_T_1054; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1055 = ~_out_T_1788; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1057 = _out_rifireMux_T_260 & out_frontSel_199; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1058 = _out_rifireMux_T_1057 & _out_T_1824; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_867 = _out_rifireMux_T_1058; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_868 = _out_rifireMux_T_1058; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_869 = _out_rifireMux_T_1058; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_870 = _out_rifireMux_T_1058; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_871 = _out_rifireMux_T_1058; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_872 = _out_rifireMux_T_1058; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_873 = _out_rifireMux_T_1058; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_874 = _out_rifireMux_T_1058; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1059 = ~_out_T_1824; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1061 = _out_rifireMux_T_260 & out_frontSel_200; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1062 = _out_rifireMux_T_1061 & _out_T_1896; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1155 = _out_rifireMux_T_1062; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1156 = _out_rifireMux_T_1062; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1157 = _out_rifireMux_T_1062; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1158 = _out_rifireMux_T_1062; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1159 = _out_rifireMux_T_1062; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1160 = _out_rifireMux_T_1062; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1161 = _out_rifireMux_T_1062; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1162 = _out_rifireMux_T_1062; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1063 = ~_out_T_1896; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1065 = _out_rifireMux_T_260 & out_frontSel_201; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1066 = _out_rifireMux_T_1065 & _out_T_1674; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_296 = _out_rifireMux_T_1066; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_297 = _out_rifireMux_T_1066; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_298 = _out_rifireMux_T_1066; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_299 = _out_rifireMux_T_1066; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_300 = _out_rifireMux_T_1066; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_301 = _out_rifireMux_T_1066; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_302 = _out_rifireMux_T_1066; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_303 = _out_rifireMux_T_1066; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1067 = ~_out_T_1674; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1069 = _out_rifireMux_T_260 & out_frontSel_202; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1070 = _out_rifireMux_T_1069 & _out_T_1614; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_56 = _out_rifireMux_T_1070; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_57 = _out_rifireMux_T_1070; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_58 = _out_rifireMux_T_1070; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_59 = _out_rifireMux_T_1070; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_60 = _out_rifireMux_T_1070; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_61 = _out_rifireMux_T_1070; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_62 = _out_rifireMux_T_1070; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_63 = _out_rifireMux_T_1070; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1071 = ~_out_T_1614; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1073 = _out_rifireMux_T_260 & out_frontSel_203; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1074 = _out_rifireMux_T_1073 & _out_T_1836; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_915 = _out_rifireMux_T_1074; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_916 = _out_rifireMux_T_1074; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_917 = _out_rifireMux_T_1074; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_918 = _out_rifireMux_T_1074; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_919 = _out_rifireMux_T_1074; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_920 = _out_rifireMux_T_1074; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_921 = _out_rifireMux_T_1074; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_922 = _out_rifireMux_T_1074; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1075 = ~_out_T_1836; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1077 = _out_rifireMux_T_260 & out_frontSel_204; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1078 = _out_rifireMux_T_1077 & _out_T_1754; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_593 = _out_rifireMux_T_1078; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_594 = _out_rifireMux_T_1078; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_595 = _out_rifireMux_T_1078; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_596 = _out_rifireMux_T_1078; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_597 = _out_rifireMux_T_1078; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_598 = _out_rifireMux_T_1078; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_599 = _out_rifireMux_T_1078; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_600 = _out_rifireMux_T_1078; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1079 = ~_out_T_1754; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1081 = _out_rifireMux_T_260 & out_frontSel_205; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1082 = _out_rifireMux_T_1081 & _out_T_1726; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_487 = _out_rifireMux_T_1082; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_488 = _out_rifireMux_T_1082; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_489 = _out_rifireMux_T_1082; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_490 = _out_rifireMux_T_1082; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_491 = _out_rifireMux_T_1082; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_492 = _out_rifireMux_T_1082; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_493 = _out_rifireMux_T_1082; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_494 = _out_rifireMux_T_1082; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1083 = ~_out_T_1726; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1085 = _out_rifireMux_T_260 & out_frontSel_206; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1086 = _out_rifireMux_T_1085 & _out_T_1668; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_272 = _out_rifireMux_T_1086; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_273 = _out_rifireMux_T_1086; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_274 = _out_rifireMux_T_1086; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_275 = _out_rifireMux_T_1086; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_276 = _out_rifireMux_T_1086; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_277 = _out_rifireMux_T_1086; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_278 = _out_rifireMux_T_1086; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_279 = _out_rifireMux_T_1086; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1087 = ~_out_T_1668; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1089 = _out_rifireMux_T_260 & out_frontSel_207; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1090 = _out_rifireMux_T_1089 & _out_T_1858; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1003 = _out_rifireMux_T_1090; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1004 = _out_rifireMux_T_1090; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1005 = _out_rifireMux_T_1090; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1006 = _out_rifireMux_T_1090; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1007 = _out_rifireMux_T_1090; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1008 = _out_rifireMux_T_1090; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1009 = _out_rifireMux_T_1090; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1010 = _out_rifireMux_T_1090; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1091 = ~_out_T_1858; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1093 = _out_rifireMux_T_260 & out_frontSel_208; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1094 = _out_rifireMux_T_1093 & _out_T_1778; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_689 = _out_rifireMux_T_1094; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_690 = _out_rifireMux_T_1094; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_691 = _out_rifireMux_T_1094; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_692 = _out_rifireMux_T_1094; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_693 = _out_rifireMux_T_1094; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_694 = _out_rifireMux_T_1094; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_695 = _out_rifireMux_T_1094; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_696 = _out_rifireMux_T_1094; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1095 = ~_out_T_1778; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1097 = _out_rifireMux_T_260 & out_frontSel_209; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1098 = _out_rifireMux_T_1097 & _out_T_1812; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_819 = _out_rifireMux_T_1098; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_820 = _out_rifireMux_T_1098; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_821 = _out_rifireMux_T_1098; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_822 = _out_rifireMux_T_1098; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_823 = _out_rifireMux_T_1098; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_824 = _out_rifireMux_T_1098; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_825 = _out_rifireMux_T_1098; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_826 = _out_rifireMux_T_1098; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1099 = ~_out_T_1812; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1101 = _out_rifireMux_T_260 & out_frontSel_210; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1102 = _out_rifireMux_T_1101 & _out_T_1878; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1083 = _out_rifireMux_T_1102; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1084 = _out_rifireMux_T_1102; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1085 = _out_rifireMux_T_1102; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1086 = _out_rifireMux_T_1102; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1087 = _out_rifireMux_T_1102; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1088 = _out_rifireMux_T_1102; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1089 = _out_rifireMux_T_1102; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1090 = _out_rifireMux_T_1102; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1103 = ~_out_T_1878; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1105 = _out_rifireMux_T_260 & out_frontSel_211; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1106 = _out_rifireMux_T_1105 & _out_T_1652; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_208 = _out_rifireMux_T_1106; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_209 = _out_rifireMux_T_1106; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_210 = _out_rifireMux_T_1106; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_211 = _out_rifireMux_T_1106; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_212 = _out_rifireMux_T_1106; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_213 = _out_rifireMux_T_1106; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_214 = _out_rifireMux_T_1106; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_215 = _out_rifireMux_T_1106; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1107 = ~_out_T_1652; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1109 = _out_rifireMux_T_260 & out_frontSel_212; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1110 = _out_rifireMux_T_1109 & _out_T_1710; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_434 = _out_rifireMux_T_1110; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_435 = _out_rifireMux_T_1110; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_436 = _out_rifireMux_T_1110; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_437 = _out_rifireMux_T_1110; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_438 = _out_rifireMux_T_1110; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_439 = _out_rifireMux_T_1110; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_440 = _out_rifireMux_T_1110; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_441 = _out_rifireMux_T_1110; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1111 = ~_out_T_1710; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1113 = _out_rifireMux_T_260 & out_frontSel_213; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1114 = _out_rifireMux_T_1113 & _out_T_1784; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_707 = _out_rifireMux_T_1114; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_708 = _out_rifireMux_T_1114; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_709 = _out_rifireMux_T_1114; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_710 = _out_rifireMux_T_1114; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_711 = _out_rifireMux_T_1114; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_712 = _out_rifireMux_T_1114; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_713 = _out_rifireMux_T_1114; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_714 = _out_rifireMux_T_1114; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1115 = ~_out_T_1784; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1117 = _out_rifireMux_T_260 & out_frontSel_214; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1118 = _out_rifireMux_T_1117 & _out_T_1860; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1011 = _out_rifireMux_T_1118; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1012 = _out_rifireMux_T_1118; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1013 = _out_rifireMux_T_1118; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1014 = _out_rifireMux_T_1118; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1015 = _out_rifireMux_T_1118; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1016 = _out_rifireMux_T_1118; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1017 = _out_rifireMux_T_1118; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1018 = _out_rifireMux_T_1118; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1119 = ~_out_T_1860; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1121 = _out_rifireMux_T_260 & out_frontSel_215; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1122 = _out_rifireMux_T_1121 & _out_T_1900; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1171 = _out_rifireMux_T_1122; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1172 = _out_rifireMux_T_1122; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1173 = _out_rifireMux_T_1122; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1174 = _out_rifireMux_T_1122; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1175 = _out_rifireMux_T_1122; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1176 = _out_rifireMux_T_1122; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1177 = _out_rifireMux_T_1122; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1178 = _out_rifireMux_T_1122; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1123 = ~_out_T_1900; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1125 = _out_rifireMux_T_260 & out_frontSel_216; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1126 = _out_rifireMux_T_1125 & _out_T_1642; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_168 = _out_rifireMux_T_1126; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_169 = _out_rifireMux_T_1126; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_170 = _out_rifireMux_T_1126; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_171 = _out_rifireMux_T_1126; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_172 = _out_rifireMux_T_1126; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_173 = _out_rifireMux_T_1126; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_174 = _out_rifireMux_T_1126; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_175 = _out_rifireMux_T_1126; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1127 = ~_out_T_1642; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1129 = _out_rifireMux_T_260 & out_frontSel_217; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1130 = _out_rifireMux_T_1129 & _out_T_1610; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_40 = _out_rifireMux_T_1130; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_41 = _out_rifireMux_T_1130; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_42 = _out_rifireMux_T_1130; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_43 = _out_rifireMux_T_1130; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_44 = _out_rifireMux_T_1130; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_45 = _out_rifireMux_T_1130; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_46 = _out_rifireMux_T_1130; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_47 = _out_rifireMux_T_1130; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1131 = ~_out_T_1610; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1133 = _out_rifireMux_T_260 & out_frontSel_218; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1134 = _out_rifireMux_T_1133 & _out_T_1838; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_923 = _out_rifireMux_T_1134; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_924 = _out_rifireMux_T_1134; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_925 = _out_rifireMux_T_1134; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_926 = _out_rifireMux_T_1134; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_927 = _out_rifireMux_T_1134; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_928 = _out_rifireMux_T_1134; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_929 = _out_rifireMux_T_1134; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_930 = _out_rifireMux_T_1134; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1135 = ~_out_T_1838; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1137 = _out_rifireMux_T_260 & out_frontSel_219; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1138 = _out_rifireMux_T_1137 & _out_T_1772; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_665 = _out_rifireMux_T_1138; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_666 = _out_rifireMux_T_1138; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_667 = _out_rifireMux_T_1138; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_668 = _out_rifireMux_T_1138; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_669 = _out_rifireMux_T_1138; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_670 = _out_rifireMux_T_1138; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_671 = _out_rifireMux_T_1138; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_672 = _out_rifireMux_T_1138; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1139 = ~_out_T_1772; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1141 = _out_rifireMux_T_260 & out_frontSel_220; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1142 = _out_rifireMux_T_1141 & _out_T_1676; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_304 = _out_rifireMux_T_1142; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_305 = _out_rifireMux_T_1142; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_306 = _out_rifireMux_T_1142; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_307 = _out_rifireMux_T_1142; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_308 = _out_rifireMux_T_1142; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_309 = _out_rifireMux_T_1142; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_310 = _out_rifireMux_T_1142; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_311 = _out_rifireMux_T_1142; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1143 = ~_out_T_1676; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1145 = _out_rifireMux_T_260 & out_frontSel_221; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1146 = _out_rifireMux_T_1145 & _out_T_1658; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_232 = _out_rifireMux_T_1146; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_233 = _out_rifireMux_T_1146; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_234 = _out_rifireMux_T_1146; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_235 = _out_rifireMux_T_1146; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_236 = _out_rifireMux_T_1146; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_237 = _out_rifireMux_T_1146; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_238 = _out_rifireMux_T_1146; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_239 = _out_rifireMux_T_1146; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1147 = ~_out_T_1658; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1149 = _out_rifireMux_T_260 & out_frontSel_222; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1150 = _out_rifireMux_T_1149 & _out_T_1902; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1179 = _out_rifireMux_T_1150; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1180 = _out_rifireMux_T_1150; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1181 = _out_rifireMux_T_1150; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1182 = _out_rifireMux_T_1150; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1183 = _out_rifireMux_T_1150; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1184 = _out_rifireMux_T_1150; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1185 = _out_rifireMux_T_1150; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1186 = _out_rifireMux_T_1150; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1151 = ~_out_T_1902; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1153 = _out_rifireMux_T_260 & out_frontSel_223; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1154 = _out_rifireMux_T_1153 & _out_T_1798; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_763 = _out_rifireMux_T_1154; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_764 = _out_rifireMux_T_1154; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_765 = _out_rifireMux_T_1154; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_766 = _out_rifireMux_T_1154; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_767 = _out_rifireMux_T_1154; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_768 = _out_rifireMux_T_1154; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_769 = _out_rifireMux_T_1154; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_770 = _out_rifireMux_T_1154; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1155 = ~_out_T_1798; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1157 = _out_rifireMux_T_260 & out_frontSel_224; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1158 = _out_rifireMux_T_1157 & _out_T_1696; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_378 = _out_rifireMux_T_1158; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_379 = _out_rifireMux_T_1158; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_380 = _out_rifireMux_T_1158; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_381 = _out_rifireMux_T_1158; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_382 = _out_rifireMux_T_1158; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_383 = _out_rifireMux_T_1158; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_384 = _out_rifireMux_T_1158; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_385 = _out_rifireMux_T_1158; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1159 = ~_out_T_1696; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1161 = _out_rifireMux_T_260 & out_frontSel_225; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1162 = _out_rifireMux_T_1161 & _out_T_1706; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_418 = _out_rifireMux_T_1162; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_419 = _out_rifireMux_T_1162; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_420 = _out_rifireMux_T_1162; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_421 = _out_rifireMux_T_1162; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_422 = _out_rifireMux_T_1162; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_423 = _out_rifireMux_T_1162; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_424 = _out_rifireMux_T_1162; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_425 = _out_rifireMux_T_1162; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1163 = ~_out_T_1706; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1165 = _out_rifireMux_T_260 & out_frontSel_226; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1166 = _out_rifireMux_T_1165 & _out_T_1802; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_779 = _out_rifireMux_T_1166; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_780 = _out_rifireMux_T_1166; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_781 = _out_rifireMux_T_1166; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_782 = _out_rifireMux_T_1166; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_783 = _out_rifireMux_T_1166; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_784 = _out_rifireMux_T_1166; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_785 = _out_rifireMux_T_1166; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_786 = _out_rifireMux_T_1166; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1167 = ~_out_T_1802; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1169 = _out_rifireMux_T_260 & out_frontSel_227; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1170 = _out_rifireMux_T_1169 & _out_T_1908; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1203 = _out_rifireMux_T_1170; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1204 = _out_rifireMux_T_1170; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1205 = _out_rifireMux_T_1170; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1206 = _out_rifireMux_T_1170; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1207 = _out_rifireMux_T_1170; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1208 = _out_rifireMux_T_1170; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1209 = _out_rifireMux_T_1170; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1210 = _out_rifireMux_T_1170; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1171 = ~_out_T_1908; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1173 = _out_rifireMux_T_260 & out_frontSel_228; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1174 = _out_rifireMux_T_1173 & _out_T_1638; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_152 = _out_rifireMux_T_1174; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_153 = _out_rifireMux_T_1174; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_154 = _out_rifireMux_T_1174; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_155 = _out_rifireMux_T_1174; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_156 = _out_rifireMux_T_1174; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_157 = _out_rifireMux_T_1174; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_158 = _out_rifireMux_T_1174; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_159 = _out_rifireMux_T_1174; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1175 = ~_out_T_1638; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1177 = _out_rifireMux_T_260 & out_frontSel_229; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1178 = _out_rifireMux_T_1177 & _out_T_1690; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_354 = _out_rifireMux_T_1178; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_355 = _out_rifireMux_T_1178; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_356 = _out_rifireMux_T_1178; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_357 = _out_rifireMux_T_1178; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_358 = _out_rifireMux_T_1178; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_359 = _out_rifireMux_T_1178; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_360 = _out_rifireMux_T_1178; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_361 = _out_rifireMux_T_1178; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1179 = ~_out_T_1690; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1181 = _out_rifireMux_T_260 & out_frontSel_230; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1182 = _out_rifireMux_T_1181 & _out_T_1774; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_673 = _out_rifireMux_T_1182; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_674 = _out_rifireMux_T_1182; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_675 = _out_rifireMux_T_1182; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_676 = _out_rifireMux_T_1182; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_677 = _out_rifireMux_T_1182; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_678 = _out_rifireMux_T_1182; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_679 = _out_rifireMux_T_1182; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_680 = _out_rifireMux_T_1182; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1183 = ~_out_T_1774; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1185 = _out_rifireMux_T_260 & out_frontSel_231; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1186 = _out_rifireMux_T_1185 & _out_T_1844; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_947 = _out_rifireMux_T_1186; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_948 = _out_rifireMux_T_1186; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_949 = _out_rifireMux_T_1186; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_950 = _out_rifireMux_T_1186; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_951 = _out_rifireMux_T_1186; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_952 = _out_rifireMux_T_1186; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_953 = _out_rifireMux_T_1186; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_954 = _out_rifireMux_T_1186; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1187 = ~_out_T_1844; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1189 = _out_rifireMux_T_260 & out_frontSel_232; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1190 = _out_rifireMux_T_1189 & _out_T_1904; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1187 = _out_rifireMux_T_1190; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1188 = _out_rifireMux_T_1190; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1189 = _out_rifireMux_T_1190; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1190 = _out_rifireMux_T_1190; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1191 = _out_rifireMux_T_1190; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1192 = _out_rifireMux_T_1190; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1193 = _out_rifireMux_T_1190; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1194 = _out_rifireMux_T_1190; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1191 = ~_out_T_1904; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1193 = _out_rifireMux_T_260 & out_frontSel_233; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1194 = _out_rifireMux_T_1193 & _out_T_1670; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_280 = _out_rifireMux_T_1194; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_281 = _out_rifireMux_T_1194; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_282 = _out_rifireMux_T_1194; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_283 = _out_rifireMux_T_1194; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_284 = _out_rifireMux_T_1194; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_285 = _out_rifireMux_T_1194; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_286 = _out_rifireMux_T_1194; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_287 = _out_rifireMux_T_1194; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1195 = ~_out_T_1670; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1197 = _out_rifireMux_T_260 & out_frontSel_234; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1198 = _out_rifireMux_T_1197 & _out_T_1604; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_16 = _out_rifireMux_T_1198; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_17 = _out_rifireMux_T_1198; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_18 = _out_rifireMux_T_1198; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_19 = _out_rifireMux_T_1198; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_20 = _out_rifireMux_T_1198; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_21 = _out_rifireMux_T_1198; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_22 = _out_rifireMux_T_1198; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_23 = _out_rifireMux_T_1198; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1199 = ~_out_T_1604; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1201 = _out_rifireMux_T_260 & out_frontSel_235; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1202 = _out_rifireMux_T_1201 & _out_T_1862; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1019 = _out_rifireMux_T_1202; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1020 = _out_rifireMux_T_1202; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1021 = _out_rifireMux_T_1202; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1022 = _out_rifireMux_T_1202; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1023 = _out_rifireMux_T_1202; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1024 = _out_rifireMux_T_1202; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1025 = _out_rifireMux_T_1202; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1026 = _out_rifireMux_T_1202; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1203 = ~_out_T_1862; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1205 = _out_rifireMux_T_260 & out_frontSel_236; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1206 = _out_rifireMux_T_1205 & _out_T_1760; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_617 = _out_rifireMux_T_1206; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_618 = _out_rifireMux_T_1206; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_619 = _out_rifireMux_T_1206; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_620 = _out_rifireMux_T_1206; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_621 = _out_rifireMux_T_1206; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_622 = _out_rifireMux_T_1206; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_623 = _out_rifireMux_T_1206; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_624 = _out_rifireMux_T_1206; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1207 = ~_out_T_1760; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1209 = _out_rifireMux_T_260 & out_frontSel_237; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1210 = _out_rifireMux_T_1209 & _out_T_1730; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_503 = _out_rifireMux_T_1210; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_504 = _out_rifireMux_T_1210; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_505 = _out_rifireMux_T_1210; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_506 = _out_rifireMux_T_1210; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_507 = _out_rifireMux_T_1210; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_508 = _out_rifireMux_T_1210; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_509 = _out_rifireMux_T_1210; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_510 = _out_rifireMux_T_1210; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1211 = ~_out_T_1730; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1213 = _out_rifireMux_T_260 & out_frontSel_238; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1214 = _out_rifireMux_T_1213 & _out_T_1650; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_200 = _out_rifireMux_T_1214; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_201 = _out_rifireMux_T_1214; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_202 = _out_rifireMux_T_1214; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_203 = _out_rifireMux_T_1214; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_204 = _out_rifireMux_T_1214; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_205 = _out_rifireMux_T_1214; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_206 = _out_rifireMux_T_1214; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_207 = _out_rifireMux_T_1214; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1215 = ~_out_T_1650; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1217 = _out_rifireMux_T_260 & out_frontSel_239; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1218 = _out_rifireMux_T_1217 & _out_T_1886; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1115 = _out_rifireMux_T_1218; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1116 = _out_rifireMux_T_1218; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1117 = _out_rifireMux_T_1218; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1118 = _out_rifireMux_T_1218; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1119 = _out_rifireMux_T_1218; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1120 = _out_rifireMux_T_1218; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1121 = _out_rifireMux_T_1218; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1122 = _out_rifireMux_T_1218; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1219 = ~_out_T_1886; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1221 = _out_rifireMux_T_260 & out_frontSel_240; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1222 = _out_rifireMux_T_1221 & _out_T_1792; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_739 = _out_rifireMux_T_1222; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_740 = _out_rifireMux_T_1222; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_741 = _out_rifireMux_T_1222; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_742 = _out_rifireMux_T_1222; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_743 = _out_rifireMux_T_1222; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_744 = _out_rifireMux_T_1222; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_745 = _out_rifireMux_T_1222; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_746 = _out_rifireMux_T_1222; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1223 = ~_out_T_1792; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1225 = _out_rifireMux_T_260 & out_frontSel_241; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1226 = _out_rifireMux_T_1225 & _out_T_1804; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_787 = _out_rifireMux_T_1226; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_788 = _out_rifireMux_T_1226; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_789 = _out_rifireMux_T_1226; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_790 = _out_rifireMux_T_1226; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_791 = _out_rifireMux_T_1226; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_792 = _out_rifireMux_T_1226; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_793 = _out_rifireMux_T_1226; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_794 = _out_rifireMux_T_1226; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1227 = ~_out_T_1804; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1229 = _out_rifireMux_T_260 & out_frontSel_242; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1230 = _out_rifireMux_T_1229 & _out_T_1888; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1123 = _out_rifireMux_T_1230; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1124 = _out_rifireMux_T_1230; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1125 = _out_rifireMux_T_1230; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1126 = _out_rifireMux_T_1230; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1127 = _out_rifireMux_T_1230; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1128 = _out_rifireMux_T_1230; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1129 = _out_rifireMux_T_1230; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1130 = _out_rifireMux_T_1230; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1231 = ~_out_T_1888; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1233 = _out_rifireMux_T_260 & out_frontSel_243; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1234 = _out_rifireMux_T_1233 & _out_T_1664; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_256 = _out_rifireMux_T_1234; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_257 = _out_rifireMux_T_1234; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_258 = _out_rifireMux_T_1234; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_259 = _out_rifireMux_T_1234; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_260 = _out_rifireMux_T_1234; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_261 = _out_rifireMux_T_1234; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_262 = _out_rifireMux_T_1234; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_263 = _out_rifireMux_T_1234; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1235 = ~_out_T_1664; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1237 = _out_rifireMux_T_260 & out_frontSel_244; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1238 = _out_rifireMux_T_1237 & _out_T_1734; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_519 = _out_rifireMux_T_1238; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_520 = _out_rifireMux_T_1238; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_521 = _out_rifireMux_T_1238; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_522 = _out_rifireMux_T_1238; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_523 = _out_rifireMux_T_1238; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_524 = _out_rifireMux_T_1238; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_525 = _out_rifireMux_T_1238; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_526 = _out_rifireMux_T_1238; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1239 = ~_out_T_1734; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1241 = _out_rifireMux_T_260 & out_frontSel_245; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1242 = _out_rifireMux_T_1241 & _out_T_1776; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_681 = _out_rifireMux_T_1242; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_682 = _out_rifireMux_T_1242; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_683 = _out_rifireMux_T_1242; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_684 = _out_rifireMux_T_1242; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_685 = _out_rifireMux_T_1242; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_686 = _out_rifireMux_T_1242; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_687 = _out_rifireMux_T_1242; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_688 = _out_rifireMux_T_1242; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1243 = ~_out_T_1776; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1245 = _out_rifireMux_T_260 & out_frontSel_246; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1246 = _out_rifireMux_T_1245 & _out_T_1864; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1027 = _out_rifireMux_T_1246; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1028 = _out_rifireMux_T_1246; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1029 = _out_rifireMux_T_1246; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1030 = _out_rifireMux_T_1246; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1031 = _out_rifireMux_T_1246; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1032 = _out_rifireMux_T_1246; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1033 = _out_rifireMux_T_1246; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1034 = _out_rifireMux_T_1246; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1247 = ~_out_T_1864; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1249 = _out_rifireMux_T_260 & out_frontSel_247; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1250 = _out_rifireMux_T_1249 & _out_T_1612; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_48 = _out_rifireMux_T_1250; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_49 = _out_rifireMux_T_1250; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_50 = _out_rifireMux_T_1250; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_51 = _out_rifireMux_T_1250; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_52 = _out_rifireMux_T_1250; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_53 = _out_rifireMux_T_1250; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_54 = _out_rifireMux_T_1250; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_55 = _out_rifireMux_T_1250; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1251 = ~_out_T_1612; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1253 = _out_rifireMux_T_260 & out_frontSel_248; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1254 = _out_rifireMux_T_1253 & _out_T_1672; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_288 = _out_rifireMux_T_1254; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_289 = _out_rifireMux_T_1254; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_290 = _out_rifireMux_T_1254; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_291 = _out_rifireMux_T_1254; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_292 = _out_rifireMux_T_1254; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_293 = _out_rifireMux_T_1254; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_294 = _out_rifireMux_T_1254; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_295 = _out_rifireMux_T_1254; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1255 = ~_out_T_1672; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1257 = _out_rifireMux_T_260 & out_frontSel_249; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1258 = _out_rifireMux_T_1257 & _out_T_1602; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_8 = _out_rifireMux_T_1258; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_9 = _out_rifireMux_T_1258; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_10 = _out_rifireMux_T_1258; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_11 = _out_rifireMux_T_1258; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_12 = _out_rifireMux_T_1258; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_13 = _out_rifireMux_T_1258; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_14 = _out_rifireMux_T_1258; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_15 = _out_rifireMux_T_1258; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1259 = ~_out_T_1602; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1261 = _out_rifireMux_T_260 & out_frontSel_250; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1262 = _out_rifireMux_T_1261 & _out_T_1842; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_939 = _out_rifireMux_T_1262; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_940 = _out_rifireMux_T_1262; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_941 = _out_rifireMux_T_1262; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_942 = _out_rifireMux_T_1262; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_943 = _out_rifireMux_T_1262; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_944 = _out_rifireMux_T_1262; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_945 = _out_rifireMux_T_1262; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_946 = _out_rifireMux_T_1262; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1263 = ~_out_T_1842; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1265 = _out_rifireMux_T_260 & out_frontSel_251; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1266 = _out_rifireMux_T_1265 & _out_T_1794; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_747 = _out_rifireMux_T_1266; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_748 = _out_rifireMux_T_1266; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_749 = _out_rifireMux_T_1266; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_750 = _out_rifireMux_T_1266; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_751 = _out_rifireMux_T_1266; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_752 = _out_rifireMux_T_1266; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_753 = _out_rifireMux_T_1266; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_754 = _out_rifireMux_T_1266; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1267 = ~_out_T_1794; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1269 = _out_rifireMux_T_260 & out_frontSel_252; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1270 = _out_rifireMux_T_1269 & _out_T_1692; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_362 = _out_rifireMux_T_1270; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_363 = _out_rifireMux_T_1270; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_364 = _out_rifireMux_T_1270; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_365 = _out_rifireMux_T_1270; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_366 = _out_rifireMux_T_1270; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_367 = _out_rifireMux_T_1270; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_368 = _out_rifireMux_T_1270; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_369 = _out_rifireMux_T_1270; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1271 = ~_out_T_1692; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1273 = _out_rifireMux_T_260 & out_frontSel_253; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1274 = _out_rifireMux_T_1273 & _out_T_1654; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_216 = _out_rifireMux_T_1274; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_217 = _out_rifireMux_T_1274; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_218 = _out_rifireMux_T_1274; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_219 = _out_rifireMux_T_1274; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_220 = _out_rifireMux_T_1274; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_221 = _out_rifireMux_T_1274; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_222 = _out_rifireMux_T_1274; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_223 = _out_rifireMux_T_1274; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1275 = ~_out_T_1654; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1277 = _out_rifireMux_T_260 & out_frontSel_254; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1278 = _out_rifireMux_T_1277 & _out_T_1906; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1195 = _out_rifireMux_T_1278; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1196 = _out_rifireMux_T_1278; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1197 = _out_rifireMux_T_1278; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1198 = _out_rifireMux_T_1278; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1199 = _out_rifireMux_T_1278; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1200 = _out_rifireMux_T_1278; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1201 = _out_rifireMux_T_1278; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1202 = _out_rifireMux_T_1278; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1279 = ~_out_T_1906; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1281 = _out_rifireMux_T_260 & out_frontSel_255; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1282 = _out_rifireMux_T_1281 & _out_T_1810; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_811 = _out_rifireMux_T_1282; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_812 = _out_rifireMux_T_1282; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_813 = _out_rifireMux_T_1282; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_814 = _out_rifireMux_T_1282; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_815 = _out_rifireMux_T_1282; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_816 = _out_rifireMux_T_1282; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_817 = _out_rifireMux_T_1282; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_818 = _out_rifireMux_T_1282; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1283 = ~_out_T_1810; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_261 = ~out_front_1_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_262 = _out_wifireMux_T_260 & _out_wifireMux_T_261; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_263 = _out_wifireMux_T_262 & out_frontSel_0_1; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_264 = _out_wifireMux_T_263 & _out_T_1716; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_451 = _out_wifireMux_T_264; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_452 = _out_wifireMux_T_264; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_453 = _out_wifireMux_T_264; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_454 = _out_wifireMux_T_264; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_455 = _out_wifireMux_T_264; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_456 = _out_wifireMux_T_264; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_457 = _out_wifireMux_T_264; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_458 = _out_wifireMux_T_264; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_265 = ~_out_T_1716; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_267 = _out_wifireMux_T_262 & out_frontSel_1_1; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_268 = _out_wifireMux_T_267 & _out_T_1624; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_96 = _out_wifireMux_T_268; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_97 = _out_wifireMux_T_268; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_98 = _out_wifireMux_T_268; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_99 = _out_wifireMux_T_268; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_100 = _out_wifireMux_T_268; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_101 = _out_wifireMux_T_268; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_102 = _out_wifireMux_T_268; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_103 = _out_wifireMux_T_268; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_269 = ~_out_T_1624; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_271 = _out_wifireMux_T_262 & out_frontSel_2_1; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_272 = _out_wifireMux_T_271 & _out_T_1846; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_955 = _out_wifireMux_T_272; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_956 = _out_wifireMux_T_272; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_957 = _out_wifireMux_T_272; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_958 = _out_wifireMux_T_272; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_959 = _out_wifireMux_T_272; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_960 = _out_wifireMux_T_272; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_961 = _out_wifireMux_T_272; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_962 = _out_wifireMux_T_272; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_273 = ~_out_T_1846; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_275 = _out_wifireMux_T_262 & out_frontSel_3_1; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_276 = _out_wifireMux_T_275 & _out_T_1756; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_601 = _out_wifireMux_T_276; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_602 = _out_wifireMux_T_276; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_603 = _out_wifireMux_T_276; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_604 = _out_wifireMux_T_276; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_605 = _out_wifireMux_T_276; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_606 = _out_wifireMux_T_276; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_607 = _out_wifireMux_T_276; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_608 = _out_wifireMux_T_276; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_277 = ~_out_T_1756; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_279 = _out_wifireMux_T_262 & out_frontSel_4_1; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_280 = _out_wifireMux_T_279 & _out_T_1678; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_312 = _out_wifireMux_T_280; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_313 = _out_wifireMux_T_280; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_314 = _out_wifireMux_T_280; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_315 = _out_wifireMux_T_280; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_316 = _out_wifireMux_T_280; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_317 = _out_wifireMux_T_280; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_318 = _out_wifireMux_T_280; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_319 = _out_wifireMux_T_280; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_281 = ~_out_T_1678; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_283 = _out_wifireMux_T_262 & out_frontSel_5_1; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_284 = _out_wifireMux_T_283 & _out_T_1640; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_160 = _out_wifireMux_T_284; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_161 = _out_wifireMux_T_284; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_162 = _out_wifireMux_T_284; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_163 = _out_wifireMux_T_284; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_164 = _out_wifireMux_T_284; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_165 = _out_wifireMux_T_284; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_166 = _out_wifireMux_T_284; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_167 = _out_wifireMux_T_284; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_285 = ~_out_T_1640; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_287 = _out_wifireMux_T_262 & out_frontSel_6_1; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_288 = _out_wifireMux_T_287 & _out_T_1876; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1075 = _out_wifireMux_T_288; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1076 = _out_wifireMux_T_288; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1077 = _out_wifireMux_T_288; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1078 = _out_wifireMux_T_288; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1079 = _out_wifireMux_T_288; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1080 = _out_wifireMux_T_288; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1081 = _out_wifireMux_T_288; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1082 = _out_wifireMux_T_288; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_289 = ~_out_T_1876; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_291 = _out_wifireMux_T_262 & out_frontSel_7_1; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_292 = _out_wifireMux_T_291 & _out_T_1822; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_859 = _out_wifireMux_T_292; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_860 = _out_wifireMux_T_292; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_861 = _out_wifireMux_T_292; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_862 = _out_wifireMux_T_292; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_863 = _out_wifireMux_T_292; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_864 = _out_wifireMux_T_292; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_865 = _out_wifireMux_T_292; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_866 = _out_wifireMux_T_292; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_293 = ~_out_T_1822; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_295 = _out_wifireMux_T_262 & out_frontSel_8_1; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_296 = _out_wifireMux_T_295 & _out_T_1742; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_545 = _out_wifireMux_T_296; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_546 = _out_wifireMux_T_296; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_547 = _out_wifireMux_T_296; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_548 = _out_wifireMux_T_296; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_549 = _out_wifireMux_T_296; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_550 = _out_wifireMux_T_296; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_551 = _out_wifireMux_T_296; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_552 = _out_wifireMux_T_296; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_297 = ~_out_T_1742; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_299 = _out_wifireMux_T_262 & out_frontSel_9_1; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_300 = _out_wifireMux_T_299 & _out_T_1666; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_264 = _out_wifireMux_T_300; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_265 = _out_wifireMux_T_300; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_266 = _out_wifireMux_T_300; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_267 = _out_wifireMux_T_300; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_268 = _out_wifireMux_T_300; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_269 = _out_wifireMux_T_300; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_270 = _out_wifireMux_T_300; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_271 = _out_wifireMux_T_300; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_301 = ~_out_T_1666; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_303 = _out_wifireMux_T_262 & out_frontSel_10_1; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_304 = _out_wifireMux_T_303 & _out_T_1724; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_483 = _out_wifireMux_T_304; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_484 = _out_wifireMux_T_304; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_485 = _out_wifireMux_T_304; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_486 = _out_wifireMux_T_304; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_305 = ~_out_T_1724; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_307 = _out_wifireMux_T_262 & out_frontSel_11_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_308 = _out_wifireMux_T_307; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_311 = _out_wifireMux_T_262 & out_frontSel_12_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_312 = _out_wifireMux_T_311; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_315 = _out_wifireMux_T_262 & out_frontSel_13_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_316 = _out_wifireMux_T_315; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_319 = _out_wifireMux_T_262 & out_frontSel_14_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_320 = _out_wifireMux_T_319; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_323 = _out_wifireMux_T_262 & out_frontSel_15_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_324 = _out_wifireMux_T_323; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_327 = _out_wifireMux_T_262 & out_frontSel_16_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_328 = _out_wifireMux_T_327; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_331 = _out_wifireMux_T_262 & out_frontSel_17_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_332 = _out_wifireMux_T_331; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_335 = _out_wifireMux_T_262 & out_frontSel_18_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_336 = _out_wifireMux_T_335; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_339 = _out_wifireMux_T_262 & out_frontSel_19_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_340 = _out_wifireMux_T_339; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_343 = _out_wifireMux_T_262 & out_frontSel_20_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_344 = _out_wifireMux_T_343; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_347 = _out_wifireMux_T_262 & out_frontSel_21_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_348 = _out_wifireMux_T_347; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_351 = _out_wifireMux_T_262 & out_frontSel_22_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_352 = _out_wifireMux_T_351; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_355 = _out_wifireMux_T_262 & out_frontSel_23_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_356 = _out_wifireMux_T_355; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_359 = _out_wifireMux_T_262 & out_frontSel_24_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_360 = _out_wifireMux_T_359; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_363 = _out_wifireMux_T_262 & out_frontSel_25_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_364 = _out_wifireMux_T_363; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_367 = _out_wifireMux_T_262 & out_frontSel_26_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_368 = _out_wifireMux_T_367; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_371 = _out_wifireMux_T_262 & out_frontSel_27_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_372 = _out_wifireMux_T_371; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_375 = _out_wifireMux_T_262 & out_frontSel_28_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_376 = _out_wifireMux_T_375; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_379 = _out_wifireMux_T_262 & out_frontSel_29_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_380 = _out_wifireMux_T_379; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_383 = _out_wifireMux_T_262 & out_frontSel_30_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_384 = _out_wifireMux_T_383; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_387 = _out_wifireMux_T_262 & out_frontSel_31_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_388 = _out_wifireMux_T_387; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_391 = _out_wifireMux_T_262 & out_frontSel_32_1; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_392 = _out_wifireMux_T_391 & _out_T_1738; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_535 = _out_wifireMux_T_392; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_536 = _out_wifireMux_T_392; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_393 = ~_out_T_1738; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_395 = _out_wifireMux_T_262 & out_frontSel_33_1; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_396 = _out_wifireMux_T_395 & _out_T_1688; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_352 = _out_wifireMux_T_396; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_353 = _out_wifireMux_T_396; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_397 = ~_out_T_1688; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_399 = _out_wifireMux_T_262 & out_frontSel_34_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_400 = _out_wifireMux_T_399; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_403 = _out_wifireMux_T_262 & out_frontSel_35_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_404 = _out_wifireMux_T_403; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_407 = _out_wifireMux_T_262 & out_frontSel_36_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_408 = _out_wifireMux_T_407; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_411 = _out_wifireMux_T_262 & out_frontSel_37_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_412 = _out_wifireMux_T_411; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_415 = _out_wifireMux_T_262 & out_frontSel_38_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_416 = _out_wifireMux_T_415; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_419 = _out_wifireMux_T_262 & out_frontSel_39_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_420 = _out_wifireMux_T_419; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_423 = _out_wifireMux_T_262 & out_frontSel_40_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_424 = _out_wifireMux_T_423; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_427 = _out_wifireMux_T_262 & out_frontSel_41_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_428 = _out_wifireMux_T_427; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_431 = _out_wifireMux_T_262 & out_frontSel_42_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_432 = _out_wifireMux_T_431; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_435 = _out_wifireMux_T_262 & out_frontSel_43_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_436 = _out_wifireMux_T_435; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_439 = _out_wifireMux_T_262 & out_frontSel_44_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_440 = _out_wifireMux_T_439; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_443 = _out_wifireMux_T_262 & out_frontSel_45_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_444 = _out_wifireMux_T_443; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_447 = _out_wifireMux_T_262 & out_frontSel_46_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_448 = _out_wifireMux_T_447; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_451 = _out_wifireMux_T_262 & out_frontSel_47_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_452 = _out_wifireMux_T_451; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_455 = _out_wifireMux_T_262 & out_frontSel_48_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_456 = _out_wifireMux_T_455; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_459 = _out_wifireMux_T_262 & out_frontSel_49_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_460 = _out_wifireMux_T_459; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_463 = _out_wifireMux_T_262 & out_frontSel_50_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_464 = _out_wifireMux_T_463; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_467 = _out_wifireMux_T_262 & out_frontSel_51_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_468 = _out_wifireMux_T_467; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_471 = _out_wifireMux_T_262 & out_frontSel_52_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_472 = _out_wifireMux_T_471; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_475 = _out_wifireMux_T_262 & out_frontSel_53_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_476 = _out_wifireMux_T_475; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_479 = _out_wifireMux_T_262 & out_frontSel_54_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_480 = _out_wifireMux_T_479; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_483 = _out_wifireMux_T_262 & out_frontSel_55_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_484 = _out_wifireMux_T_483; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_487 = _out_wifireMux_T_262 & out_frontSel_56_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_488 = _out_wifireMux_T_487; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_491 = _out_wifireMux_T_262 & out_frontSel_57_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_492 = _out_wifireMux_T_491; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_495 = _out_wifireMux_T_262 & out_frontSel_58_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_496 = _out_wifireMux_T_495; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_499 = _out_wifireMux_T_262 & out_frontSel_59_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_500 = _out_wifireMux_T_499; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_503 = _out_wifireMux_T_262 & out_frontSel_60_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_504 = _out_wifireMux_T_503; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_507 = _out_wifireMux_T_262 & out_frontSel_61_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_508 = _out_wifireMux_T_507; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_511 = _out_wifireMux_T_262 & out_frontSel_62_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_512 = _out_wifireMux_T_511; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_515 = _out_wifireMux_T_262 & out_frontSel_63_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_516 = _out_wifireMux_T_515; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_519 = _out_wifireMux_T_262 & out_frontSel_64; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_520 = _out_wifireMux_T_519; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_523 = _out_wifireMux_T_262 & out_frontSel_65; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_524 = _out_wifireMux_T_523; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_527 = _out_wifireMux_T_262 & out_frontSel_66; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_528 = _out_wifireMux_T_527; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_531 = _out_wifireMux_T_262 & out_frontSel_67; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_532 = _out_wifireMux_T_531; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_535 = _out_wifireMux_T_262 & out_frontSel_68; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_536 = _out_wifireMux_T_535; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_539 = _out_wifireMux_T_262 & out_frontSel_69; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_540 = _out_wifireMux_T_539; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_543 = _out_wifireMux_T_262 & out_frontSel_70; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_544 = _out_wifireMux_T_543; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_547 = _out_wifireMux_T_262 & out_frontSel_71; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_548 = _out_wifireMux_T_547; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_551 = _out_wifireMux_T_262 & out_frontSel_72; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_552 = _out_wifireMux_T_551; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_555 = _out_wifireMux_T_262 & out_frontSel_73; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_556 = _out_wifireMux_T_555; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_559 = _out_wifireMux_T_262 & out_frontSel_74; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_560 = _out_wifireMux_T_559; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_563 = _out_wifireMux_T_262 & out_frontSel_75; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_564 = _out_wifireMux_T_563; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_567 = _out_wifireMux_T_262 & out_frontSel_76; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_568 = _out_wifireMux_T_567; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_571 = _out_wifireMux_T_262 & out_frontSel_77; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_572 = _out_wifireMux_T_571; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_575 = _out_wifireMux_T_262 & out_frontSel_78; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_576 = _out_wifireMux_T_575; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_579 = _out_wifireMux_T_262 & out_frontSel_79; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_580 = _out_wifireMux_T_579; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_583 = _out_wifireMux_T_262 & out_frontSel_80; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_584 = _out_wifireMux_T_583; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_587 = _out_wifireMux_T_262 & out_frontSel_81; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_588 = _out_wifireMux_T_587; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_591 = _out_wifireMux_T_262 & out_frontSel_82; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_592 = _out_wifireMux_T_591; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_595 = _out_wifireMux_T_262 & out_frontSel_83; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_596 = _out_wifireMux_T_595; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_599 = _out_wifireMux_T_262 & out_frontSel_84; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_600 = _out_wifireMux_T_599; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_603 = _out_wifireMux_T_262 & out_frontSel_85; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_604 = _out_wifireMux_T_603; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_607 = _out_wifireMux_T_262 & out_frontSel_86; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_608 = _out_wifireMux_T_607; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_611 = _out_wifireMux_T_262 & out_frontSel_87; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_612 = _out_wifireMux_T_611; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_615 = _out_wifireMux_T_262 & out_frontSel_88; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_616 = _out_wifireMux_T_615; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_619 = _out_wifireMux_T_262 & out_frontSel_89; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_620 = _out_wifireMux_T_619; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_623 = _out_wifireMux_T_262 & out_frontSel_90; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_624 = _out_wifireMux_T_623; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_627 = _out_wifireMux_T_262 & out_frontSel_91; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_628 = _out_wifireMux_T_627; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_631 = _out_wifireMux_T_262 & out_frontSel_92; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_632 = _out_wifireMux_T_631; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_635 = _out_wifireMux_T_262 & out_frontSel_93; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_636 = _out_wifireMux_T_635; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_639 = _out_wifireMux_T_262 & out_frontSel_94; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_640 = _out_wifireMux_T_639; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_643 = _out_wifireMux_T_262 & out_frontSel_95; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_644 = _out_wifireMux_T_643; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_647 = _out_wifireMux_T_262 & out_frontSel_96; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_648 = _out_wifireMux_T_647 & _out_T_1712; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_442 = _out_wifireMux_T_648; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_649 = ~_out_T_1712; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_651 = _out_wifireMux_T_262 & out_frontSel_97; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_652 = _out_wifireMux_T_651; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_655 = _out_wifireMux_T_262 & out_frontSel_98; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_656 = _out_wifireMux_T_655; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_659 = _out_wifireMux_T_262 & out_frontSel_99; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_660 = _out_wifireMux_T_659; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_663 = _out_wifireMux_T_262 & out_frontSel_100; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_664 = _out_wifireMux_T_663; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_667 = _out_wifireMux_T_262 & out_frontSel_101; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_668 = _out_wifireMux_T_667; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_671 = _out_wifireMux_T_262 & out_frontSel_102; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_672 = _out_wifireMux_T_671; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_675 = _out_wifireMux_T_262 & out_frontSel_103; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_676 = _out_wifireMux_T_675 & _out_T_1780; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_697 = _out_wifireMux_T_676; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_698 = _out_wifireMux_T_676; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_677 = ~_out_T_1780; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_679 = _out_wifireMux_T_262 & out_frontSel_104; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_680 = _out_wifireMux_T_679 & _out_T_1840; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_931 = _out_wifireMux_T_680; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_932 = _out_wifireMux_T_680; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_933 = _out_wifireMux_T_680; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_934 = _out_wifireMux_T_680; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_935 = _out_wifireMux_T_680; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_936 = _out_wifireMux_T_680; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_937 = _out_wifireMux_T_680; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_938 = _out_wifireMux_T_680; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_681 = ~_out_T_1840; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_683 = _out_wifireMux_T_262 & out_frontSel_105; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_684 = _out_wifireMux_T_683 & _out_T_1732; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_511 = _out_wifireMux_T_684; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_512 = _out_wifireMux_T_684; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_513 = _out_wifireMux_T_684; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_514 = _out_wifireMux_T_684; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_515 = _out_wifireMux_T_684; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_516 = _out_wifireMux_T_684; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_517 = _out_wifireMux_T_684; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_518 = _out_wifireMux_T_684; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_685 = ~_out_T_1732; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_687 = _out_wifireMux_T_262 & out_frontSel_106; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_688 = _out_wifireMux_T_687 & _out_T_1648; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_192 = _out_wifireMux_T_688; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_193 = _out_wifireMux_T_688; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_194 = _out_wifireMux_T_688; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_195 = _out_wifireMux_T_688; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_196 = _out_wifireMux_T_688; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_197 = _out_wifireMux_T_688; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_198 = _out_wifireMux_T_688; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_199 = _out_wifireMux_T_688; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_689 = ~_out_T_1648; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_691 = _out_wifireMux_T_262 & out_frontSel_107; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_692 = _out_wifireMux_T_691 & _out_T_1880; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1091 = _out_wifireMux_T_692; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1092 = _out_wifireMux_T_692; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1093 = _out_wifireMux_T_692; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1094 = _out_wifireMux_T_692; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1095 = _out_wifireMux_T_692; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1096 = _out_wifireMux_T_692; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1097 = _out_wifireMux_T_692; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1098 = _out_wifireMux_T_692; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_693 = ~_out_T_1880; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_695 = _out_wifireMux_T_262 & out_frontSel_108; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_696 = _out_wifireMux_T_695 & _out_T_1790; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_731 = _out_wifireMux_T_696; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_732 = _out_wifireMux_T_696; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_733 = _out_wifireMux_T_696; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_734 = _out_wifireMux_T_696; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_735 = _out_wifireMux_T_696; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_736 = _out_wifireMux_T_696; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_737 = _out_wifireMux_T_696; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_738 = _out_wifireMux_T_696; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_697 = ~_out_T_1790; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_699 = _out_wifireMux_T_262 & out_frontSel_109; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_700 = _out_wifireMux_T_699 & _out_T_1714; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_443 = _out_wifireMux_T_700; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_444 = _out_wifireMux_T_700; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_445 = _out_wifireMux_T_700; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_446 = _out_wifireMux_T_700; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_447 = _out_wifireMux_T_700; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_448 = _out_wifireMux_T_700; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_449 = _out_wifireMux_T_700; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_450 = _out_wifireMux_T_700; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_701 = ~_out_T_1714; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_703 = _out_wifireMux_T_262 & out_frontSel_110; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_704 = _out_wifireMux_T_703 & _out_T_1628; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_112 = _out_wifireMux_T_704; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_113 = _out_wifireMux_T_704; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_114 = _out_wifireMux_T_704; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_115 = _out_wifireMux_T_704; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_116 = _out_wifireMux_T_704; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_117 = _out_wifireMux_T_704; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_118 = _out_wifireMux_T_704; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_119 = _out_wifireMux_T_704; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_705 = ~_out_T_1628; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_707 = _out_wifireMux_T_262 & out_frontSel_111; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_708 = _out_wifireMux_T_707 & _out_T_1898; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1163 = _out_wifireMux_T_708; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1164 = _out_wifireMux_T_708; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1165 = _out_wifireMux_T_708; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1166 = _out_wifireMux_T_708; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1167 = _out_wifireMux_T_708; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1168 = _out_wifireMux_T_708; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1169 = _out_wifireMux_T_708; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1170 = _out_wifireMux_T_708; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_709 = ~_out_T_1898; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_711 = _out_wifireMux_T_262 & out_frontSel_112; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_712 = _out_wifireMux_T_711 & _out_T_1814; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_827 = _out_wifireMux_T_712; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_828 = _out_wifireMux_T_712; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_829 = _out_wifireMux_T_712; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_830 = _out_wifireMux_T_712; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_831 = _out_wifireMux_T_712; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_832 = _out_wifireMux_T_712; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_833 = _out_wifireMux_T_712; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_834 = _out_wifireMux_T_712; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_713 = ~_out_T_1814; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_715 = _out_wifireMux_T_262 & out_frontSel_113; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_716 = _out_wifireMux_T_715 & _out_T_1770; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_657 = _out_wifireMux_T_716; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_658 = _out_wifireMux_T_716; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_659 = _out_wifireMux_T_716; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_660 = _out_wifireMux_T_716; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_661 = _out_wifireMux_T_716; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_662 = _out_wifireMux_T_716; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_663 = _out_wifireMux_T_716; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_664 = _out_wifireMux_T_716; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_717 = ~_out_T_1770; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_719 = _out_wifireMux_T_262 & out_frontSel_114; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_720 = _out_wifireMux_T_719 & _out_T_1852; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_979 = _out_wifireMux_T_720; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_980 = _out_wifireMux_T_720; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_981 = _out_wifireMux_T_720; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_982 = _out_wifireMux_T_720; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_983 = _out_wifireMux_T_720; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_984 = _out_wifireMux_T_720; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_985 = _out_wifireMux_T_720; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_986 = _out_wifireMux_T_720; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_721 = ~_out_T_1852; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_723 = _out_wifireMux_T_262 & out_frontSel_115; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_724 = _out_wifireMux_T_723 & _out_T_1608; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_32 = _out_wifireMux_T_724; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_33 = _out_wifireMux_T_724; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_34 = _out_wifireMux_T_724; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_35 = _out_wifireMux_T_724; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_36 = _out_wifireMux_T_724; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_37 = _out_wifireMux_T_724; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_38 = _out_wifireMux_T_724; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_39 = _out_wifireMux_T_724; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_725 = ~_out_T_1608; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_727 = _out_wifireMux_T_262 & out_frontSel_116; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_728 = _out_wifireMux_T_727; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_731 = _out_wifireMux_T_262 & out_frontSel_117; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_732 = _out_wifireMux_T_731; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_735 = _out_wifireMux_T_262 & out_frontSel_118; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_736 = _out_wifireMux_T_735; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_739 = _out_wifireMux_T_262 & out_frontSel_119; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_740 = _out_wifireMux_T_739; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_743 = _out_wifireMux_T_262 & out_frontSel_120; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_744 = _out_wifireMux_T_743; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_747 = _out_wifireMux_T_262 & out_frontSel_121; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_748 = _out_wifireMux_T_747; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_751 = _out_wifireMux_T_262 & out_frontSel_122; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_752 = _out_wifireMux_T_751; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_755 = _out_wifireMux_T_262 & out_frontSel_123; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_756 = _out_wifireMux_T_755; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_759 = _out_wifireMux_T_262 & out_frontSel_124; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_760 = _out_wifireMux_T_759; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_763 = _out_wifireMux_T_262 & out_frontSel_125; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_764 = _out_wifireMux_T_763; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_767 = _out_wifireMux_T_262 & out_frontSel_126; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_768 = _out_wifireMux_T_767; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_771 = _out_wifireMux_T_262 & out_frontSel_127; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_772 = _out_wifireMux_T_771; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_775 = _out_wifireMux_T_262 & out_frontSel_128; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_776 = _out_wifireMux_T_775 & _out_T_1728; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_495 = _out_wifireMux_T_776; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_496 = _out_wifireMux_T_776; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_497 = _out_wifireMux_T_776; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_498 = _out_wifireMux_T_776; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_499 = _out_wifireMux_T_776; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_500 = _out_wifireMux_T_776; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_501 = _out_wifireMux_T_776; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_502 = _out_wifireMux_T_776; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_777 = ~_out_T_1728; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_779 = _out_wifireMux_T_262 & out_frontSel_129; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_780 = _out_wifireMux_T_779 & _out_T_1720; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_467 = _out_wifireMux_T_780; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_468 = _out_wifireMux_T_780; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_469 = _out_wifireMux_T_780; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_470 = _out_wifireMux_T_780; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_471 = _out_wifireMux_T_780; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_472 = _out_wifireMux_T_780; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_473 = _out_wifireMux_T_780; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_474 = _out_wifireMux_T_780; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_781 = ~_out_T_1720; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_783 = _out_wifireMux_T_262 & out_frontSel_130; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_784 = _out_wifireMux_T_783 & _out_T_1796; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_755 = _out_wifireMux_T_784; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_756 = _out_wifireMux_T_784; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_757 = _out_wifireMux_T_784; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_758 = _out_wifireMux_T_784; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_759 = _out_wifireMux_T_784; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_760 = _out_wifireMux_T_784; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_761 = _out_wifireMux_T_784; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_762 = _out_wifireMux_T_784; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_785 = ~_out_T_1796; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_787 = _out_wifireMux_T_262 & out_frontSel_131; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_788 = _out_wifireMux_T_787 & _out_T_1890; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1131 = _out_wifireMux_T_788; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1132 = _out_wifireMux_T_788; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1133 = _out_wifireMux_T_788; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1134 = _out_wifireMux_T_788; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1135 = _out_wifireMux_T_788; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1136 = _out_wifireMux_T_788; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1137 = _out_wifireMux_T_788; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1138 = _out_wifireMux_T_788; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_789 = ~_out_T_1890; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_791 = _out_wifireMux_T_262 & out_frontSel_132; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_792 = _out_wifireMux_T_791 & _out_T_1660; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_240 = _out_wifireMux_T_792; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_241 = _out_wifireMux_T_792; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_242 = _out_wifireMux_T_792; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_243 = _out_wifireMux_T_792; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_244 = _out_wifireMux_T_792; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_245 = _out_wifireMux_T_792; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_246 = _out_wifireMux_T_792; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_247 = _out_wifireMux_T_792; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_793 = ~_out_T_1660; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_795 = _out_wifireMux_T_262 & out_frontSel_133; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_796 = _out_wifireMux_T_795 & _out_T_1662; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_248 = _out_wifireMux_T_796; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_249 = _out_wifireMux_T_796; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_250 = _out_wifireMux_T_796; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_251 = _out_wifireMux_T_796; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_252 = _out_wifireMux_T_796; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_253 = _out_wifireMux_T_796; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_254 = _out_wifireMux_T_796; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_255 = _out_wifireMux_T_796; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_797 = ~_out_T_1662; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_799 = _out_wifireMux_T_262 & out_frontSel_134; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_800 = _out_wifireMux_T_799 & _out_T_1722; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_475 = _out_wifireMux_T_800; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_476 = _out_wifireMux_T_800; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_477 = _out_wifireMux_T_800; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_478 = _out_wifireMux_T_800; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_479 = _out_wifireMux_T_800; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_480 = _out_wifireMux_T_800; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_481 = _out_wifireMux_T_800; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_482 = _out_wifireMux_T_800; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_801 = ~_out_T_1722; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_803 = _out_wifireMux_T_262 & out_frontSel_135; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_804 = _out_wifireMux_T_803 & _out_T_1800; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_771 = _out_wifireMux_T_804; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_772 = _out_wifireMux_T_804; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_773 = _out_wifireMux_T_804; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_774 = _out_wifireMux_T_804; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_775 = _out_wifireMux_T_804; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_776 = _out_wifireMux_T_804; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_777 = _out_wifireMux_T_804; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_778 = _out_wifireMux_T_804; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_805 = ~_out_T_1800; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_807 = _out_wifireMux_T_262 & out_frontSel_136; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_808 = _out_wifireMux_T_807 & _out_T_1882; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1099 = _out_wifireMux_T_808; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1100 = _out_wifireMux_T_808; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1101 = _out_wifireMux_T_808; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1102 = _out_wifireMux_T_808; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1103 = _out_wifireMux_T_808; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1104 = _out_wifireMux_T_808; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1105 = _out_wifireMux_T_808; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1106 = _out_wifireMux_T_808; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_809 = ~_out_T_1882; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_811 = _out_wifireMux_T_262 & out_frontSel_137; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_812 = _out_wifireMux_T_811 & _out_T_1684; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_336 = _out_wifireMux_T_812; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_337 = _out_wifireMux_T_812; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_338 = _out_wifireMux_T_812; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_339 = _out_wifireMux_T_812; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_340 = _out_wifireMux_T_812; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_341 = _out_wifireMux_T_812; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_342 = _out_wifireMux_T_812; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_343 = _out_wifireMux_T_812; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_813 = ~_out_T_1684; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_815 = _out_wifireMux_T_262 & out_frontSel_138; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_816 = _out_wifireMux_T_815 & _out_T_1600; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_0 = _out_wifireMux_T_816; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1 = _out_wifireMux_T_816; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_2 = _out_wifireMux_T_816; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_3 = _out_wifireMux_T_816; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_4 = _out_wifireMux_T_816; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_5 = _out_wifireMux_T_816; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_6 = _out_wifireMux_T_816; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_7 = _out_wifireMux_T_816; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_817 = ~_out_T_1600; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_819 = _out_wifireMux_T_262 & out_frontSel_139; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_820 = _out_wifireMux_T_819 & _out_T_1856; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_995 = _out_wifireMux_T_820; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_996 = _out_wifireMux_T_820; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_997 = _out_wifireMux_T_820; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_998 = _out_wifireMux_T_820; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_999 = _out_wifireMux_T_820; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1000 = _out_wifireMux_T_820; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1001 = _out_wifireMux_T_820; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1002 = _out_wifireMux_T_820; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_821 = ~_out_T_1856; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_823 = _out_wifireMux_T_262 & out_frontSel_140; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_824 = _out_wifireMux_T_823 & _out_T_1782; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_699 = _out_wifireMux_T_824; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_700 = _out_wifireMux_T_824; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_701 = _out_wifireMux_T_824; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_702 = _out_wifireMux_T_824; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_703 = _out_wifireMux_T_824; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_704 = _out_wifireMux_T_824; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_705 = _out_wifireMux_T_824; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_706 = _out_wifireMux_T_824; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_825 = ~_out_T_1782; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_827 = _out_wifireMux_T_262 & out_frontSel_141; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_828 = _out_wifireMux_T_827 & _out_T_1704; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_410 = _out_wifireMux_T_828; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_411 = _out_wifireMux_T_828; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_412 = _out_wifireMux_T_828; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_413 = _out_wifireMux_T_828; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_414 = _out_wifireMux_T_828; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_415 = _out_wifireMux_T_828; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_416 = _out_wifireMux_T_828; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_417 = _out_wifireMux_T_828; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_829 = ~_out_T_1704; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_831 = _out_wifireMux_T_262 & out_frontSel_142; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_832 = _out_wifireMux_T_831 & _out_T_1616; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_64 = _out_wifireMux_T_832; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_65 = _out_wifireMux_T_832; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_66 = _out_wifireMux_T_832; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_67 = _out_wifireMux_T_832; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_68 = _out_wifireMux_T_832; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_69 = _out_wifireMux_T_832; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_70 = _out_wifireMux_T_832; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_71 = _out_wifireMux_T_832; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_833 = ~_out_T_1616; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_835 = _out_wifireMux_T_262 & out_frontSel_143; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_836 = _out_wifireMux_T_835 & _out_T_1834; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_907 = _out_wifireMux_T_836; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_908 = _out_wifireMux_T_836; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_909 = _out_wifireMux_T_836; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_910 = _out_wifireMux_T_836; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_911 = _out_wifireMux_T_836; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_912 = _out_wifireMux_T_836; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_913 = _out_wifireMux_T_836; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_914 = _out_wifireMux_T_836; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_837 = ~_out_T_1834; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_839 = _out_wifireMux_T_262 & out_frontSel_144; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_840 = _out_wifireMux_T_839 & _out_T_1758; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_609 = _out_wifireMux_T_840; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_610 = _out_wifireMux_T_840; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_611 = _out_wifireMux_T_840; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_612 = _out_wifireMux_T_840; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_613 = _out_wifireMux_T_840; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_614 = _out_wifireMux_T_840; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_615 = _out_wifireMux_T_840; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_616 = _out_wifireMux_T_840; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_841 = ~_out_T_1758; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_843 = _out_wifireMux_T_262 & out_frontSel_145; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_844 = _out_wifireMux_T_843 & _out_T_1818; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_843 = _out_wifireMux_T_844; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_844 = _out_wifireMux_T_844; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_845 = _out_wifireMux_T_844; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_846 = _out_wifireMux_T_844; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_847 = _out_wifireMux_T_844; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_848 = _out_wifireMux_T_844; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_849 = _out_wifireMux_T_844; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_850 = _out_wifireMux_T_844; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_845 = ~_out_T_1818; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_847 = _out_wifireMux_T_262 & out_frontSel_146; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_848 = _out_wifireMux_T_847 & _out_T_1868; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1043 = _out_wifireMux_T_848; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1044 = _out_wifireMux_T_848; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1045 = _out_wifireMux_T_848; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1046 = _out_wifireMux_T_848; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1047 = _out_wifireMux_T_848; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1048 = _out_wifireMux_T_848; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1049 = _out_wifireMux_T_848; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1050 = _out_wifireMux_T_848; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_849 = ~_out_T_1868; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_851 = _out_wifireMux_T_262 & out_frontSel_147; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_852 = _out_wifireMux_T_851 & _out_T_1656; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_224 = _out_wifireMux_T_852; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_225 = _out_wifireMux_T_852; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_226 = _out_wifireMux_T_852; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_227 = _out_wifireMux_T_852; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_228 = _out_wifireMux_T_852; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_229 = _out_wifireMux_T_852; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_230 = _out_wifireMux_T_852; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_231 = _out_wifireMux_T_852; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_853 = ~_out_T_1656; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_855 = _out_wifireMux_T_262 & out_frontSel_148; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_856 = _out_wifireMux_T_855 & _out_T_1740; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_537 = _out_wifireMux_T_856; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_538 = _out_wifireMux_T_856; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_539 = _out_wifireMux_T_856; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_540 = _out_wifireMux_T_856; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_541 = _out_wifireMux_T_856; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_542 = _out_wifireMux_T_856; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_543 = _out_wifireMux_T_856; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_544 = _out_wifireMux_T_856; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_857 = ~_out_T_1740; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_859 = _out_wifireMux_T_262 & out_frontSel_149; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_860 = _out_wifireMux_T_859 & _out_T_1748; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_569 = _out_wifireMux_T_860; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_570 = _out_wifireMux_T_860; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_571 = _out_wifireMux_T_860; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_572 = _out_wifireMux_T_860; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_573 = _out_wifireMux_T_860; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_574 = _out_wifireMux_T_860; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_575 = _out_wifireMux_T_860; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_576 = _out_wifireMux_T_860; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_861 = ~_out_T_1748; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_863 = _out_wifireMux_T_262 & out_frontSel_150; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_864 = _out_wifireMux_T_863 & _out_T_1820; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_851 = _out_wifireMux_T_864; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_852 = _out_wifireMux_T_864; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_853 = _out_wifireMux_T_864; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_854 = _out_wifireMux_T_864; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_855 = _out_wifireMux_T_864; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_856 = _out_wifireMux_T_864; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_857 = _out_wifireMux_T_864; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_858 = _out_wifireMux_T_864; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_865 = ~_out_T_1820; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_867 = _out_wifireMux_T_262 & out_frontSel_151; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_868 = _out_wifireMux_T_867 & _out_T_1866; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1035 = _out_wifireMux_T_868; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1036 = _out_wifireMux_T_868; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1037 = _out_wifireMux_T_868; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1038 = _out_wifireMux_T_868; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1039 = _out_wifireMux_T_868; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1040 = _out_wifireMux_T_868; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1041 = _out_wifireMux_T_868; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1042 = _out_wifireMux_T_868; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_869 = ~_out_T_1866; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_871 = _out_wifireMux_T_262 & out_frontSel_152; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_872 = _out_wifireMux_T_871 & _out_T_1636; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_144 = _out_wifireMux_T_872; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_145 = _out_wifireMux_T_872; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_146 = _out_wifireMux_T_872; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_147 = _out_wifireMux_T_872; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_148 = _out_wifireMux_T_872; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_149 = _out_wifireMux_T_872; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_150 = _out_wifireMux_T_872; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_151 = _out_wifireMux_T_872; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_873 = ~_out_T_1636; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_875 = _out_wifireMux_T_262 & out_frontSel_153; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_876 = _out_wifireMux_T_875 & _out_T_1618; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_72 = _out_wifireMux_T_876; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_73 = _out_wifireMux_T_876; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_74 = _out_wifireMux_T_876; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_75 = _out_wifireMux_T_876; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_76 = _out_wifireMux_T_876; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_77 = _out_wifireMux_T_876; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_78 = _out_wifireMux_T_876; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_79 = _out_wifireMux_T_876; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_877 = ~_out_T_1618; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_879 = _out_wifireMux_T_262 & out_frontSel_154; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_880 = _out_wifireMux_T_879 & _out_T_1830; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_891 = _out_wifireMux_T_880; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_892 = _out_wifireMux_T_880; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_893 = _out_wifireMux_T_880; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_894 = _out_wifireMux_T_880; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_895 = _out_wifireMux_T_880; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_896 = _out_wifireMux_T_880; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_897 = _out_wifireMux_T_880; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_898 = _out_wifireMux_T_880; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_881 = ~_out_T_1830; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_883 = _out_wifireMux_T_262 & out_frontSel_155; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_884 = _out_wifireMux_T_883 & _out_T_1786; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_715 = _out_wifireMux_T_884; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_716 = _out_wifireMux_T_884; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_717 = _out_wifireMux_T_884; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_718 = _out_wifireMux_T_884; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_719 = _out_wifireMux_T_884; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_720 = _out_wifireMux_T_884; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_721 = _out_wifireMux_T_884; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_722 = _out_wifireMux_T_884; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_885 = ~_out_T_1786; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_887 = _out_wifireMux_T_262 & out_frontSel_156; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_888 = _out_wifireMux_T_887 & _out_T_1698; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_386 = _out_wifireMux_T_888; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_387 = _out_wifireMux_T_888; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_388 = _out_wifireMux_T_888; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_389 = _out_wifireMux_T_888; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_390 = _out_wifireMux_T_888; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_391 = _out_wifireMux_T_888; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_392 = _out_wifireMux_T_888; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_393 = _out_wifireMux_T_888; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_889 = ~_out_T_1698; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_891 = _out_wifireMux_T_262 & out_frontSel_157; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_892 = _out_wifireMux_T_891 & _out_T_1632; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_128 = _out_wifireMux_T_892; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_129 = _out_wifireMux_T_892; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_130 = _out_wifireMux_T_892; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_131 = _out_wifireMux_T_892; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_132 = _out_wifireMux_T_892; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_133 = _out_wifireMux_T_892; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_134 = _out_wifireMux_T_892; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_135 = _out_wifireMux_T_892; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_893 = ~_out_T_1632; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_895 = _out_wifireMux_T_262 & out_frontSel_158; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_896 = _out_wifireMux_T_895 & _out_T_1848; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_963 = _out_wifireMux_T_896; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_964 = _out_wifireMux_T_896; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_965 = _out_wifireMux_T_896; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_966 = _out_wifireMux_T_896; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_967 = _out_wifireMux_T_896; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_968 = _out_wifireMux_T_896; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_969 = _out_wifireMux_T_896; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_970 = _out_wifireMux_T_896; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_897 = ~_out_T_1848; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_899 = _out_wifireMux_T_262 & out_frontSel_159; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_900 = _out_wifireMux_T_899 & _out_T_1764; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_633 = _out_wifireMux_T_900; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_634 = _out_wifireMux_T_900; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_635 = _out_wifireMux_T_900; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_636 = _out_wifireMux_T_900; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_637 = _out_wifireMux_T_900; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_638 = _out_wifireMux_T_900; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_639 = _out_wifireMux_T_900; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_640 = _out_wifireMux_T_900; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_901 = ~_out_T_1764; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_903 = _out_wifireMux_T_262 & out_frontSel_160; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_904 = _out_wifireMux_T_903 & _out_T_1680; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_320 = _out_wifireMux_T_904; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_321 = _out_wifireMux_T_904; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_322 = _out_wifireMux_T_904; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_323 = _out_wifireMux_T_904; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_324 = _out_wifireMux_T_904; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_325 = _out_wifireMux_T_904; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_326 = _out_wifireMux_T_904; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_327 = _out_wifireMux_T_904; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_905 = ~_out_T_1680; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_907 = _out_wifireMux_T_262 & out_frontSel_161; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_908 = _out_wifireMux_T_907 & _out_T_1744; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_553 = _out_wifireMux_T_908; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_554 = _out_wifireMux_T_908; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_555 = _out_wifireMux_T_908; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_556 = _out_wifireMux_T_908; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_557 = _out_wifireMux_T_908; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_558 = _out_wifireMux_T_908; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_559 = _out_wifireMux_T_908; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_560 = _out_wifireMux_T_908; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_909 = ~_out_T_1744; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_911 = _out_wifireMux_T_262 & out_frontSel_162; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_912 = _out_wifireMux_T_911 & _out_T_1808; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_803 = _out_wifireMux_T_912; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_804 = _out_wifireMux_T_912; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_805 = _out_wifireMux_T_912; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_806 = _out_wifireMux_T_912; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_807 = _out_wifireMux_T_912; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_808 = _out_wifireMux_T_912; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_809 = _out_wifireMux_T_912; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_810 = _out_wifireMux_T_912; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_913 = ~_out_T_1808; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_915 = _out_wifireMux_T_262 & out_frontSel_163; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_916 = _out_wifireMux_T_915 & _out_T_1894; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1147 = _out_wifireMux_T_916; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1148 = _out_wifireMux_T_916; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1149 = _out_wifireMux_T_916; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1150 = _out_wifireMux_T_916; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1151 = _out_wifireMux_T_916; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1152 = _out_wifireMux_T_916; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1153 = _out_wifireMux_T_916; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1154 = _out_wifireMux_T_916; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_917 = ~_out_T_1894; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_919 = _out_wifireMux_T_262 & out_frontSel_164; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_920 = _out_wifireMux_T_919 & _out_T_1644; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_176 = _out_wifireMux_T_920; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_177 = _out_wifireMux_T_920; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_178 = _out_wifireMux_T_920; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_179 = _out_wifireMux_T_920; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_180 = _out_wifireMux_T_920; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_181 = _out_wifireMux_T_920; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_182 = _out_wifireMux_T_920; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_183 = _out_wifireMux_T_920; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_921 = ~_out_T_1644; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_923 = _out_wifireMux_T_262 & out_frontSel_165; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_924 = _out_wifireMux_T_923 & _out_T_1686; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_344 = _out_wifireMux_T_924; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_345 = _out_wifireMux_T_924; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_346 = _out_wifireMux_T_924; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_347 = _out_wifireMux_T_924; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_348 = _out_wifireMux_T_924; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_349 = _out_wifireMux_T_924; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_350 = _out_wifireMux_T_924; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_351 = _out_wifireMux_T_924; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_925 = ~_out_T_1686; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_927 = _out_wifireMux_T_262 & out_frontSel_166; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_928 = _out_wifireMux_T_927 & _out_T_1736; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_527 = _out_wifireMux_T_928; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_528 = _out_wifireMux_T_928; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_529 = _out_wifireMux_T_928; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_530 = _out_wifireMux_T_928; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_531 = _out_wifireMux_T_928; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_532 = _out_wifireMux_T_928; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_533 = _out_wifireMux_T_928; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_534 = _out_wifireMux_T_928; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_929 = ~_out_T_1736; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_931 = _out_wifireMux_T_262 & out_frontSel_167; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_932 = _out_wifireMux_T_931 & _out_T_1806; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_795 = _out_wifireMux_T_932; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_796 = _out_wifireMux_T_932; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_797 = _out_wifireMux_T_932; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_798 = _out_wifireMux_T_932; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_799 = _out_wifireMux_T_932; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_800 = _out_wifireMux_T_932; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_801 = _out_wifireMux_T_932; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_802 = _out_wifireMux_T_932; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_933 = ~_out_T_1806; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_935 = _out_wifireMux_T_262 & out_frontSel_168; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_936 = _out_wifireMux_T_935 & _out_T_1874; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1067 = _out_wifireMux_T_936; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1068 = _out_wifireMux_T_936; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1069 = _out_wifireMux_T_936; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1070 = _out_wifireMux_T_936; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1071 = _out_wifireMux_T_936; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1072 = _out_wifireMux_T_936; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1073 = _out_wifireMux_T_936; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1074 = _out_wifireMux_T_936; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_937 = ~_out_T_1874; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_939 = _out_wifireMux_T_262 & out_frontSel_169; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_940 = _out_wifireMux_T_939 & _out_T_1702; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_402 = _out_wifireMux_T_940; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_403 = _out_wifireMux_T_940; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_404 = _out_wifireMux_T_940; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_405 = _out_wifireMux_T_940; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_406 = _out_wifireMux_T_940; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_407 = _out_wifireMux_T_940; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_408 = _out_wifireMux_T_940; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_409 = _out_wifireMux_T_940; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_941 = ~_out_T_1702; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_943 = _out_wifireMux_T_262 & out_frontSel_170; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_944 = _out_wifireMux_T_943 & _out_T_1606; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_24 = _out_wifireMux_T_944; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_25 = _out_wifireMux_T_944; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_26 = _out_wifireMux_T_944; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_27 = _out_wifireMux_T_944; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_28 = _out_wifireMux_T_944; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_29 = _out_wifireMux_T_944; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_30 = _out_wifireMux_T_944; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_31 = _out_wifireMux_T_944; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_945 = ~_out_T_1606; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_947 = _out_wifireMux_T_262 & out_frontSel_171; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_948 = _out_wifireMux_T_947 & _out_T_1854; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_987 = _out_wifireMux_T_948; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_988 = _out_wifireMux_T_948; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_989 = _out_wifireMux_T_948; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_990 = _out_wifireMux_T_948; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_991 = _out_wifireMux_T_948; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_992 = _out_wifireMux_T_948; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_993 = _out_wifireMux_T_948; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_994 = _out_wifireMux_T_948; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_949 = ~_out_T_1854; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_951 = _out_wifireMux_T_262 & out_frontSel_172; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_952 = _out_wifireMux_T_951 & _out_T_1768; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_649 = _out_wifireMux_T_952; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_650 = _out_wifireMux_T_952; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_651 = _out_wifireMux_T_952; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_652 = _out_wifireMux_T_952; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_653 = _out_wifireMux_T_952; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_654 = _out_wifireMux_T_952; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_655 = _out_wifireMux_T_952; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_656 = _out_wifireMux_T_952; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_953 = ~_out_T_1768; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_955 = _out_wifireMux_T_262 & out_frontSel_173; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_956 = _out_wifireMux_T_955 & _out_T_1718; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_459 = _out_wifireMux_T_956; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_460 = _out_wifireMux_T_956; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_461 = _out_wifireMux_T_956; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_462 = _out_wifireMux_T_956; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_463 = _out_wifireMux_T_956; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_464 = _out_wifireMux_T_956; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_465 = _out_wifireMux_T_956; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_466 = _out_wifireMux_T_956; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_957 = ~_out_T_1718; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_959 = _out_wifireMux_T_262 & out_frontSel_174; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_960 = _out_wifireMux_T_959 & _out_T_1620; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_80 = _out_wifireMux_T_960; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_81 = _out_wifireMux_T_960; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_82 = _out_wifireMux_T_960; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_83 = _out_wifireMux_T_960; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_84 = _out_wifireMux_T_960; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_85 = _out_wifireMux_T_960; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_86 = _out_wifireMux_T_960; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_87 = _out_wifireMux_T_960; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_961 = ~_out_T_1620; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_963 = _out_wifireMux_T_262 & out_frontSel_175; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_964 = _out_wifireMux_T_963 & _out_T_1832; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_899 = _out_wifireMux_T_964; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_900 = _out_wifireMux_T_964; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_901 = _out_wifireMux_T_964; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_902 = _out_wifireMux_T_964; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_903 = _out_wifireMux_T_964; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_904 = _out_wifireMux_T_964; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_905 = _out_wifireMux_T_964; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_906 = _out_wifireMux_T_964; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_965 = ~_out_T_1832; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_967 = _out_wifireMux_T_262 & out_frontSel_176; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_968 = _out_wifireMux_T_967 & _out_T_1750; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_577 = _out_wifireMux_T_968; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_578 = _out_wifireMux_T_968; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_579 = _out_wifireMux_T_968; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_580 = _out_wifireMux_T_968; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_581 = _out_wifireMux_T_968; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_582 = _out_wifireMux_T_968; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_583 = _out_wifireMux_T_968; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_584 = _out_wifireMux_T_968; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_969 = ~_out_T_1750; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_971 = _out_wifireMux_T_262 & out_frontSel_177; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_972 = _out_wifireMux_T_971 & _out_T_1826; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_875 = _out_wifireMux_T_972; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_876 = _out_wifireMux_T_972; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_877 = _out_wifireMux_T_972; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_878 = _out_wifireMux_T_972; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_879 = _out_wifireMux_T_972; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_880 = _out_wifireMux_T_972; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_881 = _out_wifireMux_T_972; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_882 = _out_wifireMux_T_972; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_973 = ~_out_T_1826; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_975 = _out_wifireMux_T_262 & out_frontSel_178; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_976 = _out_wifireMux_T_975 & _out_T_1892; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1139 = _out_wifireMux_T_976; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1140 = _out_wifireMux_T_976; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1141 = _out_wifireMux_T_976; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1142 = _out_wifireMux_T_976; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1143 = _out_wifireMux_T_976; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1144 = _out_wifireMux_T_976; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1145 = _out_wifireMux_T_976; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1146 = _out_wifireMux_T_976; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_977 = ~_out_T_1892; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_979 = _out_wifireMux_T_262 & out_frontSel_179; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_980 = _out_wifireMux_T_979 & _out_T_1646; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_184 = _out_wifireMux_T_980; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_185 = _out_wifireMux_T_980; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_186 = _out_wifireMux_T_980; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_187 = _out_wifireMux_T_980; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_188 = _out_wifireMux_T_980; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_189 = _out_wifireMux_T_980; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_190 = _out_wifireMux_T_980; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_191 = _out_wifireMux_T_980; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_981 = ~_out_T_1646; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_983 = _out_wifireMux_T_262 & out_frontSel_180; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_984 = _out_wifireMux_T_983 & _out_T_1746; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_561 = _out_wifireMux_T_984; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_562 = _out_wifireMux_T_984; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_563 = _out_wifireMux_T_984; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_564 = _out_wifireMux_T_984; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_565 = _out_wifireMux_T_984; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_566 = _out_wifireMux_T_984; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_567 = _out_wifireMux_T_984; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_568 = _out_wifireMux_T_984; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_985 = ~_out_T_1746; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_987 = _out_wifireMux_T_262 & out_frontSel_181; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_988 = _out_wifireMux_T_987 & _out_T_1762; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_625 = _out_wifireMux_T_988; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_626 = _out_wifireMux_T_988; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_627 = _out_wifireMux_T_988; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_628 = _out_wifireMux_T_988; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_629 = _out_wifireMux_T_988; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_630 = _out_wifireMux_T_988; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_631 = _out_wifireMux_T_988; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_632 = _out_wifireMux_T_988; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_989 = ~_out_T_1762; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_991 = _out_wifireMux_T_262 & out_frontSel_182; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_992 = _out_wifireMux_T_991 & _out_T_1828; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_883 = _out_wifireMux_T_992; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_884 = _out_wifireMux_T_992; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_885 = _out_wifireMux_T_992; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_886 = _out_wifireMux_T_992; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_887 = _out_wifireMux_T_992; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_888 = _out_wifireMux_T_992; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_889 = _out_wifireMux_T_992; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_890 = _out_wifireMux_T_992; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_993 = ~_out_T_1828; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_995 = _out_wifireMux_T_262 & out_frontSel_183; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_996 = _out_wifireMux_T_995 & _out_T_1872; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1059 = _out_wifireMux_T_996; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1060 = _out_wifireMux_T_996; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1061 = _out_wifireMux_T_996; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1062 = _out_wifireMux_T_996; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1063 = _out_wifireMux_T_996; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1064 = _out_wifireMux_T_996; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1065 = _out_wifireMux_T_996; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1066 = _out_wifireMux_T_996; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_997 = ~_out_T_1872; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_999 = _out_wifireMux_T_262 & out_frontSel_184; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1000 = _out_wifireMux_T_999 & _out_T_1626; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_104 = _out_wifireMux_T_1000; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_105 = _out_wifireMux_T_1000; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_106 = _out_wifireMux_T_1000; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_107 = _out_wifireMux_T_1000; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_108 = _out_wifireMux_T_1000; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_109 = _out_wifireMux_T_1000; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_110 = _out_wifireMux_T_1000; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_111 = _out_wifireMux_T_1000; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1001 = ~_out_T_1626; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1003 = _out_wifireMux_T_262 & out_frontSel_185; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1004 = _out_wifireMux_T_1003 & _out_T_1622; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_88 = _out_wifireMux_T_1004; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_89 = _out_wifireMux_T_1004; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_90 = _out_wifireMux_T_1004; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_91 = _out_wifireMux_T_1004; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_92 = _out_wifireMux_T_1004; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_93 = _out_wifireMux_T_1004; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_94 = _out_wifireMux_T_1004; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_95 = _out_wifireMux_T_1004; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1005 = ~_out_T_1622; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1007 = _out_wifireMux_T_262 & out_frontSel_186; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1008 = _out_wifireMux_T_1007 & _out_T_1850; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_971 = _out_wifireMux_T_1008; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_972 = _out_wifireMux_T_1008; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_973 = _out_wifireMux_T_1008; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_974 = _out_wifireMux_T_1008; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_975 = _out_wifireMux_T_1008; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_976 = _out_wifireMux_T_1008; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_977 = _out_wifireMux_T_1008; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_978 = _out_wifireMux_T_1008; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1009 = ~_out_T_1850; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1011 = _out_wifireMux_T_262 & out_frontSel_187; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1012 = _out_wifireMux_T_1011 & _out_T_1766; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_641 = _out_wifireMux_T_1012; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_642 = _out_wifireMux_T_1012; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_643 = _out_wifireMux_T_1012; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_644 = _out_wifireMux_T_1012; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_645 = _out_wifireMux_T_1012; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_646 = _out_wifireMux_T_1012; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_647 = _out_wifireMux_T_1012; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_648 = _out_wifireMux_T_1012; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1013 = ~_out_T_1766; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1015 = _out_wifireMux_T_262 & out_frontSel_188; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1016 = _out_wifireMux_T_1015 & _out_T_1700; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_394 = _out_wifireMux_T_1016; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_395 = _out_wifireMux_T_1016; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_396 = _out_wifireMux_T_1016; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_397 = _out_wifireMux_T_1016; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_398 = _out_wifireMux_T_1016; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_399 = _out_wifireMux_T_1016; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_400 = _out_wifireMux_T_1016; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_401 = _out_wifireMux_T_1016; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1017 = ~_out_T_1700; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1019 = _out_wifireMux_T_262 & out_frontSel_189; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1020 = _out_wifireMux_T_1019 & _out_T_1634; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_136 = _out_wifireMux_T_1020; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_137 = _out_wifireMux_T_1020; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_138 = _out_wifireMux_T_1020; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_139 = _out_wifireMux_T_1020; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_140 = _out_wifireMux_T_1020; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_141 = _out_wifireMux_T_1020; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_142 = _out_wifireMux_T_1020; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_143 = _out_wifireMux_T_1020; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1021 = ~_out_T_1634; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1023 = _out_wifireMux_T_262 & out_frontSel_190; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1024 = _out_wifireMux_T_1023 & _out_T_1870; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1051 = _out_wifireMux_T_1024; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1052 = _out_wifireMux_T_1024; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1053 = _out_wifireMux_T_1024; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1054 = _out_wifireMux_T_1024; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1055 = _out_wifireMux_T_1024; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1056 = _out_wifireMux_T_1024; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1057 = _out_wifireMux_T_1024; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1058 = _out_wifireMux_T_1024; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1025 = ~_out_T_1870; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1027 = _out_wifireMux_T_262 & out_frontSel_191; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1028 = _out_wifireMux_T_1027 & _out_T_1752; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_585 = _out_wifireMux_T_1028; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_586 = _out_wifireMux_T_1028; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_587 = _out_wifireMux_T_1028; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_588 = _out_wifireMux_T_1028; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_589 = _out_wifireMux_T_1028; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_590 = _out_wifireMux_T_1028; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_591 = _out_wifireMux_T_1028; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_592 = _out_wifireMux_T_1028; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1029 = ~_out_T_1752; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1031 = _out_wifireMux_T_262 & out_frontSel_192; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1032 = _out_wifireMux_T_1031 & _out_T_1682; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_328 = _out_wifireMux_T_1032; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_329 = _out_wifireMux_T_1032; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_330 = _out_wifireMux_T_1032; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_331 = _out_wifireMux_T_1032; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_332 = _out_wifireMux_T_1032; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_333 = _out_wifireMux_T_1032; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_334 = _out_wifireMux_T_1032; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_335 = _out_wifireMux_T_1032; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1033 = ~_out_T_1682; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1035 = _out_wifireMux_T_262 & out_frontSel_193; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1036 = _out_wifireMux_T_1035 & _out_T_1708; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_426 = _out_wifireMux_T_1036; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_427 = _out_wifireMux_T_1036; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_428 = _out_wifireMux_T_1036; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_429 = _out_wifireMux_T_1036; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_430 = _out_wifireMux_T_1036; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_431 = _out_wifireMux_T_1036; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_432 = _out_wifireMux_T_1036; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_433 = _out_wifireMux_T_1036; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1037 = ~_out_T_1708; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1039 = _out_wifireMux_T_262 & out_frontSel_194; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1040 = _out_wifireMux_T_1039 & _out_T_1816; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_835 = _out_wifireMux_T_1040; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_836 = _out_wifireMux_T_1040; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_837 = _out_wifireMux_T_1040; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_838 = _out_wifireMux_T_1040; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_839 = _out_wifireMux_T_1040; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_840 = _out_wifireMux_T_1040; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_841 = _out_wifireMux_T_1040; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_842 = _out_wifireMux_T_1040; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1041 = ~_out_T_1816; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1043 = _out_wifireMux_T_262 & out_frontSel_195; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1044 = _out_wifireMux_T_1043 & _out_T_1884; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1107 = _out_wifireMux_T_1044; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1108 = _out_wifireMux_T_1044; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1109 = _out_wifireMux_T_1044; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1110 = _out_wifireMux_T_1044; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1111 = _out_wifireMux_T_1044; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1112 = _out_wifireMux_T_1044; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1113 = _out_wifireMux_T_1044; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1114 = _out_wifireMux_T_1044; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1045 = ~_out_T_1884; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1047 = _out_wifireMux_T_262 & out_frontSel_196; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1048 = _out_wifireMux_T_1047 & _out_T_1630; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_120 = _out_wifireMux_T_1048; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_121 = _out_wifireMux_T_1048; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_122 = _out_wifireMux_T_1048; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_123 = _out_wifireMux_T_1048; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_124 = _out_wifireMux_T_1048; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_125 = _out_wifireMux_T_1048; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_126 = _out_wifireMux_T_1048; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_127 = _out_wifireMux_T_1048; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1049 = ~_out_T_1630; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1051 = _out_wifireMux_T_262 & out_frontSel_197; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1052 = _out_wifireMux_T_1051 & _out_T_1694; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_370 = _out_wifireMux_T_1052; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_371 = _out_wifireMux_T_1052; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_372 = _out_wifireMux_T_1052; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_373 = _out_wifireMux_T_1052; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_374 = _out_wifireMux_T_1052; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_375 = _out_wifireMux_T_1052; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_376 = _out_wifireMux_T_1052; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_377 = _out_wifireMux_T_1052; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1053 = ~_out_T_1694; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1055 = _out_wifireMux_T_262 & out_frontSel_198; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1056 = _out_wifireMux_T_1055 & _out_T_1788; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_723 = _out_wifireMux_T_1056; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_724 = _out_wifireMux_T_1056; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_725 = _out_wifireMux_T_1056; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_726 = _out_wifireMux_T_1056; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_727 = _out_wifireMux_T_1056; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_728 = _out_wifireMux_T_1056; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_729 = _out_wifireMux_T_1056; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_730 = _out_wifireMux_T_1056; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1057 = ~_out_T_1788; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1059 = _out_wifireMux_T_262 & out_frontSel_199; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1060 = _out_wifireMux_T_1059 & _out_T_1824; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_867 = _out_wifireMux_T_1060; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_868 = _out_wifireMux_T_1060; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_869 = _out_wifireMux_T_1060; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_870 = _out_wifireMux_T_1060; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_871 = _out_wifireMux_T_1060; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_872 = _out_wifireMux_T_1060; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_873 = _out_wifireMux_T_1060; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_874 = _out_wifireMux_T_1060; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1061 = ~_out_T_1824; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1063 = _out_wifireMux_T_262 & out_frontSel_200; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1064 = _out_wifireMux_T_1063 & _out_T_1896; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1155 = _out_wifireMux_T_1064; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1156 = _out_wifireMux_T_1064; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1157 = _out_wifireMux_T_1064; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1158 = _out_wifireMux_T_1064; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1159 = _out_wifireMux_T_1064; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1160 = _out_wifireMux_T_1064; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1161 = _out_wifireMux_T_1064; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1162 = _out_wifireMux_T_1064; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1065 = ~_out_T_1896; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1067 = _out_wifireMux_T_262 & out_frontSel_201; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1068 = _out_wifireMux_T_1067 & _out_T_1674; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_296 = _out_wifireMux_T_1068; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_297 = _out_wifireMux_T_1068; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_298 = _out_wifireMux_T_1068; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_299 = _out_wifireMux_T_1068; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_300 = _out_wifireMux_T_1068; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_301 = _out_wifireMux_T_1068; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_302 = _out_wifireMux_T_1068; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_303 = _out_wifireMux_T_1068; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1069 = ~_out_T_1674; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1071 = _out_wifireMux_T_262 & out_frontSel_202; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1072 = _out_wifireMux_T_1071 & _out_T_1614; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_56 = _out_wifireMux_T_1072; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_57 = _out_wifireMux_T_1072; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_58 = _out_wifireMux_T_1072; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_59 = _out_wifireMux_T_1072; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_60 = _out_wifireMux_T_1072; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_61 = _out_wifireMux_T_1072; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_62 = _out_wifireMux_T_1072; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_63 = _out_wifireMux_T_1072; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1073 = ~_out_T_1614; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1075 = _out_wifireMux_T_262 & out_frontSel_203; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1076 = _out_wifireMux_T_1075 & _out_T_1836; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_915 = _out_wifireMux_T_1076; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_916 = _out_wifireMux_T_1076; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_917 = _out_wifireMux_T_1076; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_918 = _out_wifireMux_T_1076; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_919 = _out_wifireMux_T_1076; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_920 = _out_wifireMux_T_1076; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_921 = _out_wifireMux_T_1076; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_922 = _out_wifireMux_T_1076; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1077 = ~_out_T_1836; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1079 = _out_wifireMux_T_262 & out_frontSel_204; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1080 = _out_wifireMux_T_1079 & _out_T_1754; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_593 = _out_wifireMux_T_1080; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_594 = _out_wifireMux_T_1080; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_595 = _out_wifireMux_T_1080; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_596 = _out_wifireMux_T_1080; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_597 = _out_wifireMux_T_1080; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_598 = _out_wifireMux_T_1080; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_599 = _out_wifireMux_T_1080; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_600 = _out_wifireMux_T_1080; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1081 = ~_out_T_1754; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1083 = _out_wifireMux_T_262 & out_frontSel_205; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1084 = _out_wifireMux_T_1083 & _out_T_1726; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_487 = _out_wifireMux_T_1084; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_488 = _out_wifireMux_T_1084; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_489 = _out_wifireMux_T_1084; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_490 = _out_wifireMux_T_1084; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_491 = _out_wifireMux_T_1084; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_492 = _out_wifireMux_T_1084; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_493 = _out_wifireMux_T_1084; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_494 = _out_wifireMux_T_1084; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1085 = ~_out_T_1726; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1087 = _out_wifireMux_T_262 & out_frontSel_206; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1088 = _out_wifireMux_T_1087 & _out_T_1668; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_272 = _out_wifireMux_T_1088; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_273 = _out_wifireMux_T_1088; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_274 = _out_wifireMux_T_1088; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_275 = _out_wifireMux_T_1088; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_276 = _out_wifireMux_T_1088; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_277 = _out_wifireMux_T_1088; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_278 = _out_wifireMux_T_1088; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_279 = _out_wifireMux_T_1088; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1089 = ~_out_T_1668; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1091 = _out_wifireMux_T_262 & out_frontSel_207; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1092 = _out_wifireMux_T_1091 & _out_T_1858; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1003 = _out_wifireMux_T_1092; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1004 = _out_wifireMux_T_1092; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1005 = _out_wifireMux_T_1092; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1006 = _out_wifireMux_T_1092; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1007 = _out_wifireMux_T_1092; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1008 = _out_wifireMux_T_1092; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1009 = _out_wifireMux_T_1092; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1010 = _out_wifireMux_T_1092; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1093 = ~_out_T_1858; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1095 = _out_wifireMux_T_262 & out_frontSel_208; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1096 = _out_wifireMux_T_1095 & _out_T_1778; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_689 = _out_wifireMux_T_1096; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_690 = _out_wifireMux_T_1096; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_691 = _out_wifireMux_T_1096; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_692 = _out_wifireMux_T_1096; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_693 = _out_wifireMux_T_1096; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_694 = _out_wifireMux_T_1096; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_695 = _out_wifireMux_T_1096; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_696 = _out_wifireMux_T_1096; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1097 = ~_out_T_1778; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1099 = _out_wifireMux_T_262 & out_frontSel_209; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1100 = _out_wifireMux_T_1099 & _out_T_1812; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_819 = _out_wifireMux_T_1100; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_820 = _out_wifireMux_T_1100; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_821 = _out_wifireMux_T_1100; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_822 = _out_wifireMux_T_1100; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_823 = _out_wifireMux_T_1100; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_824 = _out_wifireMux_T_1100; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_825 = _out_wifireMux_T_1100; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_826 = _out_wifireMux_T_1100; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1101 = ~_out_T_1812; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1103 = _out_wifireMux_T_262 & out_frontSel_210; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1104 = _out_wifireMux_T_1103 & _out_T_1878; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1083 = _out_wifireMux_T_1104; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1084 = _out_wifireMux_T_1104; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1085 = _out_wifireMux_T_1104; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1086 = _out_wifireMux_T_1104; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1087 = _out_wifireMux_T_1104; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1088 = _out_wifireMux_T_1104; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1089 = _out_wifireMux_T_1104; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1090 = _out_wifireMux_T_1104; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1105 = ~_out_T_1878; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1107 = _out_wifireMux_T_262 & out_frontSel_211; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1108 = _out_wifireMux_T_1107 & _out_T_1652; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_208 = _out_wifireMux_T_1108; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_209 = _out_wifireMux_T_1108; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_210 = _out_wifireMux_T_1108; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_211 = _out_wifireMux_T_1108; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_212 = _out_wifireMux_T_1108; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_213 = _out_wifireMux_T_1108; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_214 = _out_wifireMux_T_1108; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_215 = _out_wifireMux_T_1108; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1109 = ~_out_T_1652; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1111 = _out_wifireMux_T_262 & out_frontSel_212; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1112 = _out_wifireMux_T_1111 & _out_T_1710; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_434 = _out_wifireMux_T_1112; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_435 = _out_wifireMux_T_1112; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_436 = _out_wifireMux_T_1112; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_437 = _out_wifireMux_T_1112; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_438 = _out_wifireMux_T_1112; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_439 = _out_wifireMux_T_1112; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_440 = _out_wifireMux_T_1112; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_441 = _out_wifireMux_T_1112; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1113 = ~_out_T_1710; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1115 = _out_wifireMux_T_262 & out_frontSel_213; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1116 = _out_wifireMux_T_1115 & _out_T_1784; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_707 = _out_wifireMux_T_1116; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_708 = _out_wifireMux_T_1116; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_709 = _out_wifireMux_T_1116; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_710 = _out_wifireMux_T_1116; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_711 = _out_wifireMux_T_1116; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_712 = _out_wifireMux_T_1116; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_713 = _out_wifireMux_T_1116; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_714 = _out_wifireMux_T_1116; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1117 = ~_out_T_1784; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1119 = _out_wifireMux_T_262 & out_frontSel_214; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1120 = _out_wifireMux_T_1119 & _out_T_1860; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1011 = _out_wifireMux_T_1120; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1012 = _out_wifireMux_T_1120; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1013 = _out_wifireMux_T_1120; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1014 = _out_wifireMux_T_1120; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1015 = _out_wifireMux_T_1120; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1016 = _out_wifireMux_T_1120; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1017 = _out_wifireMux_T_1120; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1018 = _out_wifireMux_T_1120; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1121 = ~_out_T_1860; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1123 = _out_wifireMux_T_262 & out_frontSel_215; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1124 = _out_wifireMux_T_1123 & _out_T_1900; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1171 = _out_wifireMux_T_1124; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1172 = _out_wifireMux_T_1124; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1173 = _out_wifireMux_T_1124; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1174 = _out_wifireMux_T_1124; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1175 = _out_wifireMux_T_1124; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1176 = _out_wifireMux_T_1124; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1177 = _out_wifireMux_T_1124; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1178 = _out_wifireMux_T_1124; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1125 = ~_out_T_1900; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1127 = _out_wifireMux_T_262 & out_frontSel_216; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1128 = _out_wifireMux_T_1127 & _out_T_1642; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_168 = _out_wifireMux_T_1128; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_169 = _out_wifireMux_T_1128; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_170 = _out_wifireMux_T_1128; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_171 = _out_wifireMux_T_1128; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_172 = _out_wifireMux_T_1128; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_173 = _out_wifireMux_T_1128; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_174 = _out_wifireMux_T_1128; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_175 = _out_wifireMux_T_1128; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1129 = ~_out_T_1642; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1131 = _out_wifireMux_T_262 & out_frontSel_217; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1132 = _out_wifireMux_T_1131 & _out_T_1610; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_40 = _out_wifireMux_T_1132; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_41 = _out_wifireMux_T_1132; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_42 = _out_wifireMux_T_1132; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_43 = _out_wifireMux_T_1132; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_44 = _out_wifireMux_T_1132; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_45 = _out_wifireMux_T_1132; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_46 = _out_wifireMux_T_1132; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_47 = _out_wifireMux_T_1132; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1133 = ~_out_T_1610; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1135 = _out_wifireMux_T_262 & out_frontSel_218; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1136 = _out_wifireMux_T_1135 & _out_T_1838; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_923 = _out_wifireMux_T_1136; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_924 = _out_wifireMux_T_1136; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_925 = _out_wifireMux_T_1136; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_926 = _out_wifireMux_T_1136; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_927 = _out_wifireMux_T_1136; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_928 = _out_wifireMux_T_1136; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_929 = _out_wifireMux_T_1136; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_930 = _out_wifireMux_T_1136; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1137 = ~_out_T_1838; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1139 = _out_wifireMux_T_262 & out_frontSel_219; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1140 = _out_wifireMux_T_1139 & _out_T_1772; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_665 = _out_wifireMux_T_1140; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_666 = _out_wifireMux_T_1140; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_667 = _out_wifireMux_T_1140; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_668 = _out_wifireMux_T_1140; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_669 = _out_wifireMux_T_1140; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_670 = _out_wifireMux_T_1140; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_671 = _out_wifireMux_T_1140; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_672 = _out_wifireMux_T_1140; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1141 = ~_out_T_1772; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1143 = _out_wifireMux_T_262 & out_frontSel_220; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1144 = _out_wifireMux_T_1143 & _out_T_1676; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_304 = _out_wifireMux_T_1144; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_305 = _out_wifireMux_T_1144; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_306 = _out_wifireMux_T_1144; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_307 = _out_wifireMux_T_1144; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_308 = _out_wifireMux_T_1144; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_309 = _out_wifireMux_T_1144; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_310 = _out_wifireMux_T_1144; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_311 = _out_wifireMux_T_1144; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1145 = ~_out_T_1676; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1147 = _out_wifireMux_T_262 & out_frontSel_221; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1148 = _out_wifireMux_T_1147 & _out_T_1658; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_232 = _out_wifireMux_T_1148; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_233 = _out_wifireMux_T_1148; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_234 = _out_wifireMux_T_1148; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_235 = _out_wifireMux_T_1148; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_236 = _out_wifireMux_T_1148; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_237 = _out_wifireMux_T_1148; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_238 = _out_wifireMux_T_1148; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_239 = _out_wifireMux_T_1148; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1149 = ~_out_T_1658; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1151 = _out_wifireMux_T_262 & out_frontSel_222; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1152 = _out_wifireMux_T_1151 & _out_T_1902; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1179 = _out_wifireMux_T_1152; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1180 = _out_wifireMux_T_1152; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1181 = _out_wifireMux_T_1152; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1182 = _out_wifireMux_T_1152; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1183 = _out_wifireMux_T_1152; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1184 = _out_wifireMux_T_1152; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1185 = _out_wifireMux_T_1152; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1186 = _out_wifireMux_T_1152; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1153 = ~_out_T_1902; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1155 = _out_wifireMux_T_262 & out_frontSel_223; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1156 = _out_wifireMux_T_1155 & _out_T_1798; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_763 = _out_wifireMux_T_1156; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_764 = _out_wifireMux_T_1156; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_765 = _out_wifireMux_T_1156; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_766 = _out_wifireMux_T_1156; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_767 = _out_wifireMux_T_1156; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_768 = _out_wifireMux_T_1156; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_769 = _out_wifireMux_T_1156; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_770 = _out_wifireMux_T_1156; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1157 = ~_out_T_1798; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1159 = _out_wifireMux_T_262 & out_frontSel_224; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1160 = _out_wifireMux_T_1159 & _out_T_1696; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_378 = _out_wifireMux_T_1160; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_379 = _out_wifireMux_T_1160; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_380 = _out_wifireMux_T_1160; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_381 = _out_wifireMux_T_1160; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_382 = _out_wifireMux_T_1160; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_383 = _out_wifireMux_T_1160; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_384 = _out_wifireMux_T_1160; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_385 = _out_wifireMux_T_1160; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1161 = ~_out_T_1696; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1163 = _out_wifireMux_T_262 & out_frontSel_225; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1164 = _out_wifireMux_T_1163 & _out_T_1706; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_418 = _out_wifireMux_T_1164; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_419 = _out_wifireMux_T_1164; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_420 = _out_wifireMux_T_1164; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_421 = _out_wifireMux_T_1164; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_422 = _out_wifireMux_T_1164; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_423 = _out_wifireMux_T_1164; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_424 = _out_wifireMux_T_1164; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_425 = _out_wifireMux_T_1164; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1165 = ~_out_T_1706; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1167 = _out_wifireMux_T_262 & out_frontSel_226; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1168 = _out_wifireMux_T_1167 & _out_T_1802; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_779 = _out_wifireMux_T_1168; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_780 = _out_wifireMux_T_1168; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_781 = _out_wifireMux_T_1168; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_782 = _out_wifireMux_T_1168; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_783 = _out_wifireMux_T_1168; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_784 = _out_wifireMux_T_1168; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_785 = _out_wifireMux_T_1168; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_786 = _out_wifireMux_T_1168; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1169 = ~_out_T_1802; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1171 = _out_wifireMux_T_262 & out_frontSel_227; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1172 = _out_wifireMux_T_1171 & _out_T_1908; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1203 = _out_wifireMux_T_1172; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1204 = _out_wifireMux_T_1172; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1205 = _out_wifireMux_T_1172; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1206 = _out_wifireMux_T_1172; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1207 = _out_wifireMux_T_1172; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1208 = _out_wifireMux_T_1172; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1209 = _out_wifireMux_T_1172; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1210 = _out_wifireMux_T_1172; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1173 = ~_out_T_1908; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1175 = _out_wifireMux_T_262 & out_frontSel_228; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1176 = _out_wifireMux_T_1175 & _out_T_1638; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_152 = _out_wifireMux_T_1176; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_153 = _out_wifireMux_T_1176; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_154 = _out_wifireMux_T_1176; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_155 = _out_wifireMux_T_1176; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_156 = _out_wifireMux_T_1176; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_157 = _out_wifireMux_T_1176; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_158 = _out_wifireMux_T_1176; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_159 = _out_wifireMux_T_1176; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1177 = ~_out_T_1638; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1179 = _out_wifireMux_T_262 & out_frontSel_229; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1180 = _out_wifireMux_T_1179 & _out_T_1690; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_354 = _out_wifireMux_T_1180; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_355 = _out_wifireMux_T_1180; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_356 = _out_wifireMux_T_1180; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_357 = _out_wifireMux_T_1180; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_358 = _out_wifireMux_T_1180; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_359 = _out_wifireMux_T_1180; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_360 = _out_wifireMux_T_1180; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_361 = _out_wifireMux_T_1180; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1181 = ~_out_T_1690; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1183 = _out_wifireMux_T_262 & out_frontSel_230; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1184 = _out_wifireMux_T_1183 & _out_T_1774; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_673 = _out_wifireMux_T_1184; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_674 = _out_wifireMux_T_1184; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_675 = _out_wifireMux_T_1184; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_676 = _out_wifireMux_T_1184; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_677 = _out_wifireMux_T_1184; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_678 = _out_wifireMux_T_1184; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_679 = _out_wifireMux_T_1184; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_680 = _out_wifireMux_T_1184; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1185 = ~_out_T_1774; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1187 = _out_wifireMux_T_262 & out_frontSel_231; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1188 = _out_wifireMux_T_1187 & _out_T_1844; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_947 = _out_wifireMux_T_1188; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_948 = _out_wifireMux_T_1188; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_949 = _out_wifireMux_T_1188; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_950 = _out_wifireMux_T_1188; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_951 = _out_wifireMux_T_1188; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_952 = _out_wifireMux_T_1188; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_953 = _out_wifireMux_T_1188; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_954 = _out_wifireMux_T_1188; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1189 = ~_out_T_1844; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1191 = _out_wifireMux_T_262 & out_frontSel_232; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1192 = _out_wifireMux_T_1191 & _out_T_1904; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1187 = _out_wifireMux_T_1192; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1188 = _out_wifireMux_T_1192; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1189 = _out_wifireMux_T_1192; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1190 = _out_wifireMux_T_1192; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1191 = _out_wifireMux_T_1192; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1192 = _out_wifireMux_T_1192; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1193 = _out_wifireMux_T_1192; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1194 = _out_wifireMux_T_1192; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1193 = ~_out_T_1904; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1195 = _out_wifireMux_T_262 & out_frontSel_233; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1196 = _out_wifireMux_T_1195 & _out_T_1670; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_280 = _out_wifireMux_T_1196; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_281 = _out_wifireMux_T_1196; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_282 = _out_wifireMux_T_1196; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_283 = _out_wifireMux_T_1196; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_284 = _out_wifireMux_T_1196; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_285 = _out_wifireMux_T_1196; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_286 = _out_wifireMux_T_1196; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_287 = _out_wifireMux_T_1196; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1197 = ~_out_T_1670; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1199 = _out_wifireMux_T_262 & out_frontSel_234; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1200 = _out_wifireMux_T_1199 & _out_T_1604; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_16 = _out_wifireMux_T_1200; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_17 = _out_wifireMux_T_1200; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_18 = _out_wifireMux_T_1200; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_19 = _out_wifireMux_T_1200; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_20 = _out_wifireMux_T_1200; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_21 = _out_wifireMux_T_1200; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_22 = _out_wifireMux_T_1200; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_23 = _out_wifireMux_T_1200; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1201 = ~_out_T_1604; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1203 = _out_wifireMux_T_262 & out_frontSel_235; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1204 = _out_wifireMux_T_1203 & _out_T_1862; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1019 = _out_wifireMux_T_1204; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1020 = _out_wifireMux_T_1204; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1021 = _out_wifireMux_T_1204; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1022 = _out_wifireMux_T_1204; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1023 = _out_wifireMux_T_1204; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1024 = _out_wifireMux_T_1204; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1025 = _out_wifireMux_T_1204; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1026 = _out_wifireMux_T_1204; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1205 = ~_out_T_1862; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1207 = _out_wifireMux_T_262 & out_frontSel_236; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1208 = _out_wifireMux_T_1207 & _out_T_1760; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_617 = _out_wifireMux_T_1208; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_618 = _out_wifireMux_T_1208; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_619 = _out_wifireMux_T_1208; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_620 = _out_wifireMux_T_1208; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_621 = _out_wifireMux_T_1208; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_622 = _out_wifireMux_T_1208; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_623 = _out_wifireMux_T_1208; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_624 = _out_wifireMux_T_1208; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1209 = ~_out_T_1760; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1211 = _out_wifireMux_T_262 & out_frontSel_237; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1212 = _out_wifireMux_T_1211 & _out_T_1730; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_503 = _out_wifireMux_T_1212; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_504 = _out_wifireMux_T_1212; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_505 = _out_wifireMux_T_1212; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_506 = _out_wifireMux_T_1212; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_507 = _out_wifireMux_T_1212; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_508 = _out_wifireMux_T_1212; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_509 = _out_wifireMux_T_1212; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_510 = _out_wifireMux_T_1212; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1213 = ~_out_T_1730; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1215 = _out_wifireMux_T_262 & out_frontSel_238; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1216 = _out_wifireMux_T_1215 & _out_T_1650; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_200 = _out_wifireMux_T_1216; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_201 = _out_wifireMux_T_1216; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_202 = _out_wifireMux_T_1216; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_203 = _out_wifireMux_T_1216; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_204 = _out_wifireMux_T_1216; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_205 = _out_wifireMux_T_1216; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_206 = _out_wifireMux_T_1216; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_207 = _out_wifireMux_T_1216; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1217 = ~_out_T_1650; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1219 = _out_wifireMux_T_262 & out_frontSel_239; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1220 = _out_wifireMux_T_1219 & _out_T_1886; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1115 = _out_wifireMux_T_1220; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1116 = _out_wifireMux_T_1220; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1117 = _out_wifireMux_T_1220; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1118 = _out_wifireMux_T_1220; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1119 = _out_wifireMux_T_1220; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1120 = _out_wifireMux_T_1220; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1121 = _out_wifireMux_T_1220; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1122 = _out_wifireMux_T_1220; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1221 = ~_out_T_1886; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1223 = _out_wifireMux_T_262 & out_frontSel_240; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1224 = _out_wifireMux_T_1223 & _out_T_1792; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_739 = _out_wifireMux_T_1224; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_740 = _out_wifireMux_T_1224; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_741 = _out_wifireMux_T_1224; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_742 = _out_wifireMux_T_1224; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_743 = _out_wifireMux_T_1224; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_744 = _out_wifireMux_T_1224; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_745 = _out_wifireMux_T_1224; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_746 = _out_wifireMux_T_1224; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1225 = ~_out_T_1792; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1227 = _out_wifireMux_T_262 & out_frontSel_241; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1228 = _out_wifireMux_T_1227 & _out_T_1804; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_787 = _out_wifireMux_T_1228; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_788 = _out_wifireMux_T_1228; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_789 = _out_wifireMux_T_1228; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_790 = _out_wifireMux_T_1228; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_791 = _out_wifireMux_T_1228; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_792 = _out_wifireMux_T_1228; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_793 = _out_wifireMux_T_1228; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_794 = _out_wifireMux_T_1228; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1229 = ~_out_T_1804; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1231 = _out_wifireMux_T_262 & out_frontSel_242; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1232 = _out_wifireMux_T_1231 & _out_T_1888; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1123 = _out_wifireMux_T_1232; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1124 = _out_wifireMux_T_1232; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1125 = _out_wifireMux_T_1232; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1126 = _out_wifireMux_T_1232; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1127 = _out_wifireMux_T_1232; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1128 = _out_wifireMux_T_1232; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1129 = _out_wifireMux_T_1232; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1130 = _out_wifireMux_T_1232; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1233 = ~_out_T_1888; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1235 = _out_wifireMux_T_262 & out_frontSel_243; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1236 = _out_wifireMux_T_1235 & _out_T_1664; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_256 = _out_wifireMux_T_1236; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_257 = _out_wifireMux_T_1236; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_258 = _out_wifireMux_T_1236; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_259 = _out_wifireMux_T_1236; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_260 = _out_wifireMux_T_1236; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_261 = _out_wifireMux_T_1236; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_262 = _out_wifireMux_T_1236; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_263 = _out_wifireMux_T_1236; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1237 = ~_out_T_1664; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1239 = _out_wifireMux_T_262 & out_frontSel_244; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1240 = _out_wifireMux_T_1239 & _out_T_1734; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_519 = _out_wifireMux_T_1240; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_520 = _out_wifireMux_T_1240; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_521 = _out_wifireMux_T_1240; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_522 = _out_wifireMux_T_1240; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_523 = _out_wifireMux_T_1240; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_524 = _out_wifireMux_T_1240; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_525 = _out_wifireMux_T_1240; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_526 = _out_wifireMux_T_1240; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1241 = ~_out_T_1734; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1243 = _out_wifireMux_T_262 & out_frontSel_245; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1244 = _out_wifireMux_T_1243 & _out_T_1776; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_681 = _out_wifireMux_T_1244; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_682 = _out_wifireMux_T_1244; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_683 = _out_wifireMux_T_1244; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_684 = _out_wifireMux_T_1244; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_685 = _out_wifireMux_T_1244; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_686 = _out_wifireMux_T_1244; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_687 = _out_wifireMux_T_1244; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_688 = _out_wifireMux_T_1244; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1245 = ~_out_T_1776; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1247 = _out_wifireMux_T_262 & out_frontSel_246; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1248 = _out_wifireMux_T_1247 & _out_T_1864; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1027 = _out_wifireMux_T_1248; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1028 = _out_wifireMux_T_1248; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1029 = _out_wifireMux_T_1248; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1030 = _out_wifireMux_T_1248; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1031 = _out_wifireMux_T_1248; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1032 = _out_wifireMux_T_1248; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1033 = _out_wifireMux_T_1248; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1034 = _out_wifireMux_T_1248; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1249 = ~_out_T_1864; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1251 = _out_wifireMux_T_262 & out_frontSel_247; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1252 = _out_wifireMux_T_1251 & _out_T_1612; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_48 = _out_wifireMux_T_1252; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_49 = _out_wifireMux_T_1252; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_50 = _out_wifireMux_T_1252; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_51 = _out_wifireMux_T_1252; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_52 = _out_wifireMux_T_1252; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_53 = _out_wifireMux_T_1252; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_54 = _out_wifireMux_T_1252; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_55 = _out_wifireMux_T_1252; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1253 = ~_out_T_1612; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1255 = _out_wifireMux_T_262 & out_frontSel_248; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1256 = _out_wifireMux_T_1255 & _out_T_1672; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_288 = _out_wifireMux_T_1256; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_289 = _out_wifireMux_T_1256; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_290 = _out_wifireMux_T_1256; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_291 = _out_wifireMux_T_1256; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_292 = _out_wifireMux_T_1256; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_293 = _out_wifireMux_T_1256; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_294 = _out_wifireMux_T_1256; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_295 = _out_wifireMux_T_1256; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1257 = ~_out_T_1672; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1259 = _out_wifireMux_T_262 & out_frontSel_249; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1260 = _out_wifireMux_T_1259 & _out_T_1602; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_8 = _out_wifireMux_T_1260; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_9 = _out_wifireMux_T_1260; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_10 = _out_wifireMux_T_1260; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_11 = _out_wifireMux_T_1260; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_12 = _out_wifireMux_T_1260; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_13 = _out_wifireMux_T_1260; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_14 = _out_wifireMux_T_1260; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_15 = _out_wifireMux_T_1260; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1261 = ~_out_T_1602; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1263 = _out_wifireMux_T_262 & out_frontSel_250; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1264 = _out_wifireMux_T_1263 & _out_T_1842; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_939 = _out_wifireMux_T_1264; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_940 = _out_wifireMux_T_1264; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_941 = _out_wifireMux_T_1264; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_942 = _out_wifireMux_T_1264; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_943 = _out_wifireMux_T_1264; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_944 = _out_wifireMux_T_1264; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_945 = _out_wifireMux_T_1264; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_946 = _out_wifireMux_T_1264; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1265 = ~_out_T_1842; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1267 = _out_wifireMux_T_262 & out_frontSel_251; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1268 = _out_wifireMux_T_1267 & _out_T_1794; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_747 = _out_wifireMux_T_1268; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_748 = _out_wifireMux_T_1268; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_749 = _out_wifireMux_T_1268; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_750 = _out_wifireMux_T_1268; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_751 = _out_wifireMux_T_1268; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_752 = _out_wifireMux_T_1268; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_753 = _out_wifireMux_T_1268; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_754 = _out_wifireMux_T_1268; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1269 = ~_out_T_1794; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1271 = _out_wifireMux_T_262 & out_frontSel_252; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1272 = _out_wifireMux_T_1271 & _out_T_1692; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_362 = _out_wifireMux_T_1272; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_363 = _out_wifireMux_T_1272; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_364 = _out_wifireMux_T_1272; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_365 = _out_wifireMux_T_1272; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_366 = _out_wifireMux_T_1272; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_367 = _out_wifireMux_T_1272; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_368 = _out_wifireMux_T_1272; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_369 = _out_wifireMux_T_1272; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1273 = ~_out_T_1692; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1275 = _out_wifireMux_T_262 & out_frontSel_253; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1276 = _out_wifireMux_T_1275 & _out_T_1654; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_216 = _out_wifireMux_T_1276; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_217 = _out_wifireMux_T_1276; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_218 = _out_wifireMux_T_1276; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_219 = _out_wifireMux_T_1276; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_220 = _out_wifireMux_T_1276; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_221 = _out_wifireMux_T_1276; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_222 = _out_wifireMux_T_1276; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_223 = _out_wifireMux_T_1276; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1277 = ~_out_T_1654; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1279 = _out_wifireMux_T_262 & out_frontSel_254; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1280 = _out_wifireMux_T_1279 & _out_T_1906; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1195 = _out_wifireMux_T_1280; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1196 = _out_wifireMux_T_1280; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1197 = _out_wifireMux_T_1280; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1198 = _out_wifireMux_T_1280; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1199 = _out_wifireMux_T_1280; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1200 = _out_wifireMux_T_1280; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1201 = _out_wifireMux_T_1280; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1202 = _out_wifireMux_T_1280; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1281 = ~_out_T_1906; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1283 = _out_wifireMux_T_262 & out_frontSel_255; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1284 = _out_wifireMux_T_1283 & _out_T_1810; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_811 = _out_wifireMux_T_1284; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_812 = _out_wifireMux_T_1284; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_813 = _out_wifireMux_T_1284; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_814 = _out_wifireMux_T_1284; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_815 = _out_wifireMux_T_1284; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_816 = _out_wifireMux_T_1284; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_817 = _out_wifireMux_T_1284; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_818 = _out_wifireMux_T_1284; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1285 = ~_out_T_1810; // @[RegisterRouter.scala:87:24] wire _GEN_23 = out_front_1_valid & out_1_ready; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_259; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_259 = _GEN_23; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_260; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_260 = _GEN_23; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_260 = _out_rofireMux_T_259 & out_front_1_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_261 = _out_rofireMux_T_260 & out_backSel_0_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_262 = _out_rofireMux_T_261 & _out_T_1717; // @[RegisterRouter.scala:87:24] assign out_roready_1_451 = _out_rofireMux_T_262; // @[RegisterRouter.scala:87:24] assign out_roready_1_452 = _out_rofireMux_T_262; // @[RegisterRouter.scala:87:24] assign out_roready_1_453 = _out_rofireMux_T_262; // @[RegisterRouter.scala:87:24] assign out_roready_1_454 = _out_rofireMux_T_262; // @[RegisterRouter.scala:87:24] assign out_roready_1_455 = _out_rofireMux_T_262; // @[RegisterRouter.scala:87:24] assign out_roready_1_456 = _out_rofireMux_T_262; // @[RegisterRouter.scala:87:24] assign out_roready_1_457 = _out_rofireMux_T_262; // @[RegisterRouter.scala:87:24] assign out_roready_1_458 = _out_rofireMux_T_262; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_263 = ~_out_T_1717; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_265 = _out_rofireMux_T_260 & out_backSel_1_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_266 = _out_rofireMux_T_265 & _out_T_1625; // @[RegisterRouter.scala:87:24] assign out_roready_1_96 = _out_rofireMux_T_266; // @[RegisterRouter.scala:87:24] assign out_roready_1_97 = _out_rofireMux_T_266; // @[RegisterRouter.scala:87:24] assign out_roready_1_98 = _out_rofireMux_T_266; // @[RegisterRouter.scala:87:24] assign out_roready_1_99 = _out_rofireMux_T_266; // @[RegisterRouter.scala:87:24] assign out_roready_1_100 = _out_rofireMux_T_266; // @[RegisterRouter.scala:87:24] assign out_roready_1_101 = _out_rofireMux_T_266; // @[RegisterRouter.scala:87:24] assign out_roready_1_102 = _out_rofireMux_T_266; // @[RegisterRouter.scala:87:24] assign out_roready_1_103 = _out_rofireMux_T_266; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_267 = ~_out_T_1625; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_269 = _out_rofireMux_T_260 & out_backSel_2_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_270 = _out_rofireMux_T_269 & _out_T_1847; // @[RegisterRouter.scala:87:24] assign out_roready_1_955 = _out_rofireMux_T_270; // @[RegisterRouter.scala:87:24] assign out_roready_1_956 = _out_rofireMux_T_270; // @[RegisterRouter.scala:87:24] assign out_roready_1_957 = _out_rofireMux_T_270; // @[RegisterRouter.scala:87:24] assign out_roready_1_958 = _out_rofireMux_T_270; // @[RegisterRouter.scala:87:24] assign out_roready_1_959 = _out_rofireMux_T_270; // @[RegisterRouter.scala:87:24] assign out_roready_1_960 = _out_rofireMux_T_270; // @[RegisterRouter.scala:87:24] assign out_roready_1_961 = _out_rofireMux_T_270; // @[RegisterRouter.scala:87:24] assign out_roready_1_962 = _out_rofireMux_T_270; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_271 = ~_out_T_1847; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_273 = _out_rofireMux_T_260 & out_backSel_3_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_274 = _out_rofireMux_T_273 & _out_T_1757; // @[RegisterRouter.scala:87:24] assign out_roready_1_601 = _out_rofireMux_T_274; // @[RegisterRouter.scala:87:24] assign out_roready_1_602 = _out_rofireMux_T_274; // @[RegisterRouter.scala:87:24] assign out_roready_1_603 = _out_rofireMux_T_274; // @[RegisterRouter.scala:87:24] assign out_roready_1_604 = _out_rofireMux_T_274; // @[RegisterRouter.scala:87:24] assign out_roready_1_605 = _out_rofireMux_T_274; // @[RegisterRouter.scala:87:24] assign out_roready_1_606 = _out_rofireMux_T_274; // @[RegisterRouter.scala:87:24] assign out_roready_1_607 = _out_rofireMux_T_274; // @[RegisterRouter.scala:87:24] assign out_roready_1_608 = _out_rofireMux_T_274; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_275 = ~_out_T_1757; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_277 = _out_rofireMux_T_260 & out_backSel_4_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_278 = _out_rofireMux_T_277 & _out_T_1679; // @[RegisterRouter.scala:87:24] assign out_roready_1_312 = _out_rofireMux_T_278; // @[RegisterRouter.scala:87:24] assign out_roready_1_313 = _out_rofireMux_T_278; // @[RegisterRouter.scala:87:24] assign out_roready_1_314 = _out_rofireMux_T_278; // @[RegisterRouter.scala:87:24] assign out_roready_1_315 = _out_rofireMux_T_278; // @[RegisterRouter.scala:87:24] assign out_roready_1_316 = _out_rofireMux_T_278; // @[RegisterRouter.scala:87:24] assign out_roready_1_317 = _out_rofireMux_T_278; // @[RegisterRouter.scala:87:24] assign out_roready_1_318 = _out_rofireMux_T_278; // @[RegisterRouter.scala:87:24] assign out_roready_1_319 = _out_rofireMux_T_278; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_279 = ~_out_T_1679; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_281 = _out_rofireMux_T_260 & out_backSel_5_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_282 = _out_rofireMux_T_281 & _out_T_1641; // @[RegisterRouter.scala:87:24] assign out_roready_1_160 = _out_rofireMux_T_282; // @[RegisterRouter.scala:87:24] assign out_roready_1_161 = _out_rofireMux_T_282; // @[RegisterRouter.scala:87:24] assign out_roready_1_162 = _out_rofireMux_T_282; // @[RegisterRouter.scala:87:24] assign out_roready_1_163 = _out_rofireMux_T_282; // @[RegisterRouter.scala:87:24] assign out_roready_1_164 = _out_rofireMux_T_282; // @[RegisterRouter.scala:87:24] assign out_roready_1_165 = _out_rofireMux_T_282; // @[RegisterRouter.scala:87:24] assign out_roready_1_166 = _out_rofireMux_T_282; // @[RegisterRouter.scala:87:24] assign out_roready_1_167 = _out_rofireMux_T_282; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_283 = ~_out_T_1641; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_285 = _out_rofireMux_T_260 & out_backSel_6_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_286 = _out_rofireMux_T_285 & _out_T_1877; // @[RegisterRouter.scala:87:24] assign out_roready_1_1075 = _out_rofireMux_T_286; // @[RegisterRouter.scala:87:24] assign out_roready_1_1076 = _out_rofireMux_T_286; // @[RegisterRouter.scala:87:24] assign out_roready_1_1077 = _out_rofireMux_T_286; // @[RegisterRouter.scala:87:24] assign out_roready_1_1078 = _out_rofireMux_T_286; // @[RegisterRouter.scala:87:24] assign out_roready_1_1079 = _out_rofireMux_T_286; // @[RegisterRouter.scala:87:24] assign out_roready_1_1080 = _out_rofireMux_T_286; // @[RegisterRouter.scala:87:24] assign out_roready_1_1081 = _out_rofireMux_T_286; // @[RegisterRouter.scala:87:24] assign out_roready_1_1082 = _out_rofireMux_T_286; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_287 = ~_out_T_1877; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_289 = _out_rofireMux_T_260 & out_backSel_7_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_290 = _out_rofireMux_T_289 & _out_T_1823; // @[RegisterRouter.scala:87:24] assign out_roready_1_859 = _out_rofireMux_T_290; // @[RegisterRouter.scala:87:24] assign out_roready_1_860 = _out_rofireMux_T_290; // @[RegisterRouter.scala:87:24] assign out_roready_1_861 = _out_rofireMux_T_290; // @[RegisterRouter.scala:87:24] assign out_roready_1_862 = _out_rofireMux_T_290; // @[RegisterRouter.scala:87:24] assign out_roready_1_863 = _out_rofireMux_T_290; // @[RegisterRouter.scala:87:24] assign out_roready_1_864 = _out_rofireMux_T_290; // @[RegisterRouter.scala:87:24] assign out_roready_1_865 = _out_rofireMux_T_290; // @[RegisterRouter.scala:87:24] assign out_roready_1_866 = _out_rofireMux_T_290; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_291 = ~_out_T_1823; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_293 = _out_rofireMux_T_260 & out_backSel_8_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_294 = _out_rofireMux_T_293 & _out_T_1743; // @[RegisterRouter.scala:87:24] assign out_roready_1_545 = _out_rofireMux_T_294; // @[RegisterRouter.scala:87:24] assign out_roready_1_546 = _out_rofireMux_T_294; // @[RegisterRouter.scala:87:24] assign out_roready_1_547 = _out_rofireMux_T_294; // @[RegisterRouter.scala:87:24] assign out_roready_1_548 = _out_rofireMux_T_294; // @[RegisterRouter.scala:87:24] assign out_roready_1_549 = _out_rofireMux_T_294; // @[RegisterRouter.scala:87:24] assign out_roready_1_550 = _out_rofireMux_T_294; // @[RegisterRouter.scala:87:24] assign out_roready_1_551 = _out_rofireMux_T_294; // @[RegisterRouter.scala:87:24] assign out_roready_1_552 = _out_rofireMux_T_294; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_295 = ~_out_T_1743; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_297 = _out_rofireMux_T_260 & out_backSel_9_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_298 = _out_rofireMux_T_297 & _out_T_1667; // @[RegisterRouter.scala:87:24] assign out_roready_1_264 = _out_rofireMux_T_298; // @[RegisterRouter.scala:87:24] assign out_roready_1_265 = _out_rofireMux_T_298; // @[RegisterRouter.scala:87:24] assign out_roready_1_266 = _out_rofireMux_T_298; // @[RegisterRouter.scala:87:24] assign out_roready_1_267 = _out_rofireMux_T_298; // @[RegisterRouter.scala:87:24] assign out_roready_1_268 = _out_rofireMux_T_298; // @[RegisterRouter.scala:87:24] assign out_roready_1_269 = _out_rofireMux_T_298; // @[RegisterRouter.scala:87:24] assign out_roready_1_270 = _out_rofireMux_T_298; // @[RegisterRouter.scala:87:24] assign out_roready_1_271 = _out_rofireMux_T_298; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_299 = ~_out_T_1667; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_301 = _out_rofireMux_T_260 & out_backSel_10_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_302 = _out_rofireMux_T_301 & _out_T_1725; // @[RegisterRouter.scala:87:24] assign out_roready_1_483 = _out_rofireMux_T_302; // @[RegisterRouter.scala:87:24] assign out_roready_1_484 = _out_rofireMux_T_302; // @[RegisterRouter.scala:87:24] assign out_roready_1_485 = _out_rofireMux_T_302; // @[RegisterRouter.scala:87:24] assign out_roready_1_486 = _out_rofireMux_T_302; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_303 = ~_out_T_1725; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_305 = _out_rofireMux_T_260 & out_backSel_11_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_306 = _out_rofireMux_T_305; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_309 = _out_rofireMux_T_260 & out_backSel_12_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_310 = _out_rofireMux_T_309; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_313 = _out_rofireMux_T_260 & out_backSel_13_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_314 = _out_rofireMux_T_313; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_317 = _out_rofireMux_T_260 & out_backSel_14_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_318 = _out_rofireMux_T_317; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_321 = _out_rofireMux_T_260 & out_backSel_15_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_322 = _out_rofireMux_T_321; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_325 = _out_rofireMux_T_260 & out_backSel_16_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_326 = _out_rofireMux_T_325; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_329 = _out_rofireMux_T_260 & out_backSel_17_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_330 = _out_rofireMux_T_329; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_333 = _out_rofireMux_T_260 & out_backSel_18_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_334 = _out_rofireMux_T_333; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_337 = _out_rofireMux_T_260 & out_backSel_19_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_338 = _out_rofireMux_T_337; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_341 = _out_rofireMux_T_260 & out_backSel_20_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_342 = _out_rofireMux_T_341; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_345 = _out_rofireMux_T_260 & out_backSel_21_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_346 = _out_rofireMux_T_345; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_349 = _out_rofireMux_T_260 & out_backSel_22_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_350 = _out_rofireMux_T_349; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_353 = _out_rofireMux_T_260 & out_backSel_23_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_354 = _out_rofireMux_T_353; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_357 = _out_rofireMux_T_260 & out_backSel_24_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_358 = _out_rofireMux_T_357; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_361 = _out_rofireMux_T_260 & out_backSel_25_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_362 = _out_rofireMux_T_361; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_365 = _out_rofireMux_T_260 & out_backSel_26_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_366 = _out_rofireMux_T_365; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_369 = _out_rofireMux_T_260 & out_backSel_27_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_370 = _out_rofireMux_T_369; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_373 = _out_rofireMux_T_260 & out_backSel_28_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_374 = _out_rofireMux_T_373; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_377 = _out_rofireMux_T_260 & out_backSel_29_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_378 = _out_rofireMux_T_377; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_381 = _out_rofireMux_T_260 & out_backSel_30_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_382 = _out_rofireMux_T_381; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_385 = _out_rofireMux_T_260 & out_backSel_31_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_386 = _out_rofireMux_T_385; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_389 = _out_rofireMux_T_260 & out_backSel_32_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_390 = _out_rofireMux_T_389 & _out_T_1739; // @[RegisterRouter.scala:87:24] assign out_roready_1_535 = _out_rofireMux_T_390; // @[RegisterRouter.scala:87:24] assign out_roready_1_536 = _out_rofireMux_T_390; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_391 = ~_out_T_1739; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_393 = _out_rofireMux_T_260 & out_backSel_33_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_394 = _out_rofireMux_T_393 & _out_T_1689; // @[RegisterRouter.scala:87:24] assign out_roready_1_352 = _out_rofireMux_T_394; // @[RegisterRouter.scala:87:24] assign out_roready_1_353 = _out_rofireMux_T_394; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_395 = ~_out_T_1689; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_397 = _out_rofireMux_T_260 & out_backSel_34_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_398 = _out_rofireMux_T_397; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_401 = _out_rofireMux_T_260 & out_backSel_35_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_402 = _out_rofireMux_T_401; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_405 = _out_rofireMux_T_260 & out_backSel_36_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_406 = _out_rofireMux_T_405; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_409 = _out_rofireMux_T_260 & out_backSel_37_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_410 = _out_rofireMux_T_409; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_413 = _out_rofireMux_T_260 & out_backSel_38_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_414 = _out_rofireMux_T_413; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_417 = _out_rofireMux_T_260 & out_backSel_39_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_418 = _out_rofireMux_T_417; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_421 = _out_rofireMux_T_260 & out_backSel_40_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_422 = _out_rofireMux_T_421; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_425 = _out_rofireMux_T_260 & out_backSel_41_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_426 = _out_rofireMux_T_425; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_429 = _out_rofireMux_T_260 & out_backSel_42_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_430 = _out_rofireMux_T_429; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_433 = _out_rofireMux_T_260 & out_backSel_43_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_434 = _out_rofireMux_T_433; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_437 = _out_rofireMux_T_260 & out_backSel_44_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_438 = _out_rofireMux_T_437; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_441 = _out_rofireMux_T_260 & out_backSel_45_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_442 = _out_rofireMux_T_441; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_445 = _out_rofireMux_T_260 & out_backSel_46_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_446 = _out_rofireMux_T_445; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_449 = _out_rofireMux_T_260 & out_backSel_47_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_450 = _out_rofireMux_T_449; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_453 = _out_rofireMux_T_260 & out_backSel_48_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_454 = _out_rofireMux_T_453; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_457 = _out_rofireMux_T_260 & out_backSel_49_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_458 = _out_rofireMux_T_457; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_461 = _out_rofireMux_T_260 & out_backSel_50_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_462 = _out_rofireMux_T_461; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_465 = _out_rofireMux_T_260 & out_backSel_51_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_466 = _out_rofireMux_T_465; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_469 = _out_rofireMux_T_260 & out_backSel_52_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_470 = _out_rofireMux_T_469; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_473 = _out_rofireMux_T_260 & out_backSel_53_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_474 = _out_rofireMux_T_473; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_477 = _out_rofireMux_T_260 & out_backSel_54_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_478 = _out_rofireMux_T_477; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_481 = _out_rofireMux_T_260 & out_backSel_55_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_482 = _out_rofireMux_T_481; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_485 = _out_rofireMux_T_260 & out_backSel_56_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_486 = _out_rofireMux_T_485; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_489 = _out_rofireMux_T_260 & out_backSel_57_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_490 = _out_rofireMux_T_489; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_493 = _out_rofireMux_T_260 & out_backSel_58_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_494 = _out_rofireMux_T_493; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_497 = _out_rofireMux_T_260 & out_backSel_59_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_498 = _out_rofireMux_T_497; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_501 = _out_rofireMux_T_260 & out_backSel_60_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_502 = _out_rofireMux_T_501; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_505 = _out_rofireMux_T_260 & out_backSel_61_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_506 = _out_rofireMux_T_505; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_509 = _out_rofireMux_T_260 & out_backSel_62_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_510 = _out_rofireMux_T_509; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_513 = _out_rofireMux_T_260 & out_backSel_63_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_514 = _out_rofireMux_T_513; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_517 = _out_rofireMux_T_260 & out_backSel_64; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_518 = _out_rofireMux_T_517; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_521 = _out_rofireMux_T_260 & out_backSel_65; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_522 = _out_rofireMux_T_521; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_525 = _out_rofireMux_T_260 & out_backSel_66; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_526 = _out_rofireMux_T_525; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_529 = _out_rofireMux_T_260 & out_backSel_67; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_530 = _out_rofireMux_T_529; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_533 = _out_rofireMux_T_260 & out_backSel_68; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_534 = _out_rofireMux_T_533; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_537 = _out_rofireMux_T_260 & out_backSel_69; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_538 = _out_rofireMux_T_537; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_541 = _out_rofireMux_T_260 & out_backSel_70; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_542 = _out_rofireMux_T_541; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_545 = _out_rofireMux_T_260 & out_backSel_71; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_546 = _out_rofireMux_T_545; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_549 = _out_rofireMux_T_260 & out_backSel_72; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_550 = _out_rofireMux_T_549; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_553 = _out_rofireMux_T_260 & out_backSel_73; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_554 = _out_rofireMux_T_553; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_557 = _out_rofireMux_T_260 & out_backSel_74; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_558 = _out_rofireMux_T_557; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_561 = _out_rofireMux_T_260 & out_backSel_75; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_562 = _out_rofireMux_T_561; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_565 = _out_rofireMux_T_260 & out_backSel_76; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_566 = _out_rofireMux_T_565; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_569 = _out_rofireMux_T_260 & out_backSel_77; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_570 = _out_rofireMux_T_569; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_573 = _out_rofireMux_T_260 & out_backSel_78; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_574 = _out_rofireMux_T_573; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_577 = _out_rofireMux_T_260 & out_backSel_79; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_578 = _out_rofireMux_T_577; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_581 = _out_rofireMux_T_260 & out_backSel_80; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_582 = _out_rofireMux_T_581; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_585 = _out_rofireMux_T_260 & out_backSel_81; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_586 = _out_rofireMux_T_585; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_589 = _out_rofireMux_T_260 & out_backSel_82; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_590 = _out_rofireMux_T_589; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_593 = _out_rofireMux_T_260 & out_backSel_83; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_594 = _out_rofireMux_T_593; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_597 = _out_rofireMux_T_260 & out_backSel_84; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_598 = _out_rofireMux_T_597; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_601 = _out_rofireMux_T_260 & out_backSel_85; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_602 = _out_rofireMux_T_601; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_605 = _out_rofireMux_T_260 & out_backSel_86; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_606 = _out_rofireMux_T_605; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_609 = _out_rofireMux_T_260 & out_backSel_87; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_610 = _out_rofireMux_T_609; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_613 = _out_rofireMux_T_260 & out_backSel_88; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_614 = _out_rofireMux_T_613; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_617 = _out_rofireMux_T_260 & out_backSel_89; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_618 = _out_rofireMux_T_617; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_621 = _out_rofireMux_T_260 & out_backSel_90; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_622 = _out_rofireMux_T_621; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_625 = _out_rofireMux_T_260 & out_backSel_91; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_626 = _out_rofireMux_T_625; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_629 = _out_rofireMux_T_260 & out_backSel_92; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_630 = _out_rofireMux_T_629; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_633 = _out_rofireMux_T_260 & out_backSel_93; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_634 = _out_rofireMux_T_633; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_637 = _out_rofireMux_T_260 & out_backSel_94; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_638 = _out_rofireMux_T_637; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_641 = _out_rofireMux_T_260 & out_backSel_95; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_642 = _out_rofireMux_T_641; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_645 = _out_rofireMux_T_260 & out_backSel_96; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_646 = _out_rofireMux_T_645 & _out_T_1713; // @[RegisterRouter.scala:87:24] assign out_roready_1_442 = _out_rofireMux_T_646; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_647 = ~_out_T_1713; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_649 = _out_rofireMux_T_260 & out_backSel_97; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_650 = _out_rofireMux_T_649; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_653 = _out_rofireMux_T_260 & out_backSel_98; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_654 = _out_rofireMux_T_653; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_657 = _out_rofireMux_T_260 & out_backSel_99; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_658 = _out_rofireMux_T_657; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_661 = _out_rofireMux_T_260 & out_backSel_100; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_662 = _out_rofireMux_T_661; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_665 = _out_rofireMux_T_260 & out_backSel_101; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_666 = _out_rofireMux_T_665; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_669 = _out_rofireMux_T_260 & out_backSel_102; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_670 = _out_rofireMux_T_669; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_673 = _out_rofireMux_T_260 & out_backSel_103; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_674 = _out_rofireMux_T_673 & _out_T_1781; // @[RegisterRouter.scala:87:24] assign out_roready_1_697 = _out_rofireMux_T_674; // @[RegisterRouter.scala:87:24] assign out_roready_1_698 = _out_rofireMux_T_674; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_675 = ~_out_T_1781; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_677 = _out_rofireMux_T_260 & out_backSel_104; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_678 = _out_rofireMux_T_677 & _out_T_1841; // @[RegisterRouter.scala:87:24] assign out_roready_1_931 = _out_rofireMux_T_678; // @[RegisterRouter.scala:87:24] assign out_roready_1_932 = _out_rofireMux_T_678; // @[RegisterRouter.scala:87:24] assign out_roready_1_933 = _out_rofireMux_T_678; // @[RegisterRouter.scala:87:24] assign out_roready_1_934 = _out_rofireMux_T_678; // @[RegisterRouter.scala:87:24] assign out_roready_1_935 = _out_rofireMux_T_678; // @[RegisterRouter.scala:87:24] assign out_roready_1_936 = _out_rofireMux_T_678; // @[RegisterRouter.scala:87:24] assign out_roready_1_937 = _out_rofireMux_T_678; // @[RegisterRouter.scala:87:24] assign out_roready_1_938 = _out_rofireMux_T_678; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_679 = ~_out_T_1841; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_681 = _out_rofireMux_T_260 & out_backSel_105; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_682 = _out_rofireMux_T_681 & _out_T_1733; // @[RegisterRouter.scala:87:24] assign out_roready_1_511 = _out_rofireMux_T_682; // @[RegisterRouter.scala:87:24] assign out_roready_1_512 = _out_rofireMux_T_682; // @[RegisterRouter.scala:87:24] assign out_roready_1_513 = _out_rofireMux_T_682; // @[RegisterRouter.scala:87:24] assign out_roready_1_514 = _out_rofireMux_T_682; // @[RegisterRouter.scala:87:24] assign out_roready_1_515 = _out_rofireMux_T_682; // @[RegisterRouter.scala:87:24] assign out_roready_1_516 = _out_rofireMux_T_682; // @[RegisterRouter.scala:87:24] assign out_roready_1_517 = _out_rofireMux_T_682; // @[RegisterRouter.scala:87:24] assign out_roready_1_518 = _out_rofireMux_T_682; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_683 = ~_out_T_1733; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_685 = _out_rofireMux_T_260 & out_backSel_106; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_686 = _out_rofireMux_T_685 & _out_T_1649; // @[RegisterRouter.scala:87:24] assign out_roready_1_192 = _out_rofireMux_T_686; // @[RegisterRouter.scala:87:24] assign out_roready_1_193 = _out_rofireMux_T_686; // @[RegisterRouter.scala:87:24] assign out_roready_1_194 = _out_rofireMux_T_686; // @[RegisterRouter.scala:87:24] assign out_roready_1_195 = _out_rofireMux_T_686; // @[RegisterRouter.scala:87:24] assign out_roready_1_196 = _out_rofireMux_T_686; // @[RegisterRouter.scala:87:24] assign out_roready_1_197 = _out_rofireMux_T_686; // @[RegisterRouter.scala:87:24] assign out_roready_1_198 = _out_rofireMux_T_686; // @[RegisterRouter.scala:87:24] assign out_roready_1_199 = _out_rofireMux_T_686; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_687 = ~_out_T_1649; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_689 = _out_rofireMux_T_260 & out_backSel_107; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_690 = _out_rofireMux_T_689 & _out_T_1881; // @[RegisterRouter.scala:87:24] assign out_roready_1_1091 = _out_rofireMux_T_690; // @[RegisterRouter.scala:87:24] assign out_roready_1_1092 = _out_rofireMux_T_690; // @[RegisterRouter.scala:87:24] assign out_roready_1_1093 = _out_rofireMux_T_690; // @[RegisterRouter.scala:87:24] assign out_roready_1_1094 = _out_rofireMux_T_690; // @[RegisterRouter.scala:87:24] assign out_roready_1_1095 = _out_rofireMux_T_690; // @[RegisterRouter.scala:87:24] assign out_roready_1_1096 = _out_rofireMux_T_690; // @[RegisterRouter.scala:87:24] assign out_roready_1_1097 = _out_rofireMux_T_690; // @[RegisterRouter.scala:87:24] assign out_roready_1_1098 = _out_rofireMux_T_690; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_691 = ~_out_T_1881; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_693 = _out_rofireMux_T_260 & out_backSel_108; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_694 = _out_rofireMux_T_693 & _out_T_1791; // @[RegisterRouter.scala:87:24] assign out_roready_1_731 = _out_rofireMux_T_694; // @[RegisterRouter.scala:87:24] assign out_roready_1_732 = _out_rofireMux_T_694; // @[RegisterRouter.scala:87:24] assign out_roready_1_733 = _out_rofireMux_T_694; // @[RegisterRouter.scala:87:24] assign out_roready_1_734 = _out_rofireMux_T_694; // @[RegisterRouter.scala:87:24] assign out_roready_1_735 = _out_rofireMux_T_694; // @[RegisterRouter.scala:87:24] assign out_roready_1_736 = _out_rofireMux_T_694; // @[RegisterRouter.scala:87:24] assign out_roready_1_737 = _out_rofireMux_T_694; // @[RegisterRouter.scala:87:24] assign out_roready_1_738 = _out_rofireMux_T_694; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_695 = ~_out_T_1791; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_697 = _out_rofireMux_T_260 & out_backSel_109; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_698 = _out_rofireMux_T_697 & _out_T_1715; // @[RegisterRouter.scala:87:24] assign out_roready_1_443 = _out_rofireMux_T_698; // @[RegisterRouter.scala:87:24] assign out_roready_1_444 = _out_rofireMux_T_698; // @[RegisterRouter.scala:87:24] assign out_roready_1_445 = _out_rofireMux_T_698; // @[RegisterRouter.scala:87:24] assign out_roready_1_446 = _out_rofireMux_T_698; // @[RegisterRouter.scala:87:24] assign out_roready_1_447 = _out_rofireMux_T_698; // @[RegisterRouter.scala:87:24] assign out_roready_1_448 = _out_rofireMux_T_698; // @[RegisterRouter.scala:87:24] assign out_roready_1_449 = _out_rofireMux_T_698; // @[RegisterRouter.scala:87:24] assign out_roready_1_450 = _out_rofireMux_T_698; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_699 = ~_out_T_1715; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_701 = _out_rofireMux_T_260 & out_backSel_110; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_702 = _out_rofireMux_T_701 & _out_T_1629; // @[RegisterRouter.scala:87:24] assign out_roready_1_112 = _out_rofireMux_T_702; // @[RegisterRouter.scala:87:24] assign out_roready_1_113 = _out_rofireMux_T_702; // @[RegisterRouter.scala:87:24] assign out_roready_1_114 = _out_rofireMux_T_702; // @[RegisterRouter.scala:87:24] assign out_roready_1_115 = _out_rofireMux_T_702; // @[RegisterRouter.scala:87:24] assign out_roready_1_116 = _out_rofireMux_T_702; // @[RegisterRouter.scala:87:24] assign out_roready_1_117 = _out_rofireMux_T_702; // @[RegisterRouter.scala:87:24] assign out_roready_1_118 = _out_rofireMux_T_702; // @[RegisterRouter.scala:87:24] assign out_roready_1_119 = _out_rofireMux_T_702; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_703 = ~_out_T_1629; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_705 = _out_rofireMux_T_260 & out_backSel_111; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_706 = _out_rofireMux_T_705 & _out_T_1899; // @[RegisterRouter.scala:87:24] assign out_roready_1_1163 = _out_rofireMux_T_706; // @[RegisterRouter.scala:87:24] assign out_roready_1_1164 = _out_rofireMux_T_706; // @[RegisterRouter.scala:87:24] assign out_roready_1_1165 = _out_rofireMux_T_706; // @[RegisterRouter.scala:87:24] assign out_roready_1_1166 = _out_rofireMux_T_706; // @[RegisterRouter.scala:87:24] assign out_roready_1_1167 = _out_rofireMux_T_706; // @[RegisterRouter.scala:87:24] assign out_roready_1_1168 = _out_rofireMux_T_706; // @[RegisterRouter.scala:87:24] assign out_roready_1_1169 = _out_rofireMux_T_706; // @[RegisterRouter.scala:87:24] assign out_roready_1_1170 = _out_rofireMux_T_706; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_707 = ~_out_T_1899; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_709 = _out_rofireMux_T_260 & out_backSel_112; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_710 = _out_rofireMux_T_709 & _out_T_1815; // @[RegisterRouter.scala:87:24] assign out_roready_1_827 = _out_rofireMux_T_710; // @[RegisterRouter.scala:87:24] assign out_roready_1_828 = _out_rofireMux_T_710; // @[RegisterRouter.scala:87:24] assign out_roready_1_829 = _out_rofireMux_T_710; // @[RegisterRouter.scala:87:24] assign out_roready_1_830 = _out_rofireMux_T_710; // @[RegisterRouter.scala:87:24] assign out_roready_1_831 = _out_rofireMux_T_710; // @[RegisterRouter.scala:87:24] assign out_roready_1_832 = _out_rofireMux_T_710; // @[RegisterRouter.scala:87:24] assign out_roready_1_833 = _out_rofireMux_T_710; // @[RegisterRouter.scala:87:24] assign out_roready_1_834 = _out_rofireMux_T_710; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_711 = ~_out_T_1815; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_713 = _out_rofireMux_T_260 & out_backSel_113; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_714 = _out_rofireMux_T_713 & _out_T_1771; // @[RegisterRouter.scala:87:24] assign out_roready_1_657 = _out_rofireMux_T_714; // @[RegisterRouter.scala:87:24] assign out_roready_1_658 = _out_rofireMux_T_714; // @[RegisterRouter.scala:87:24] assign out_roready_1_659 = _out_rofireMux_T_714; // @[RegisterRouter.scala:87:24] assign out_roready_1_660 = _out_rofireMux_T_714; // @[RegisterRouter.scala:87:24] assign out_roready_1_661 = _out_rofireMux_T_714; // @[RegisterRouter.scala:87:24] assign out_roready_1_662 = _out_rofireMux_T_714; // @[RegisterRouter.scala:87:24] assign out_roready_1_663 = _out_rofireMux_T_714; // @[RegisterRouter.scala:87:24] assign out_roready_1_664 = _out_rofireMux_T_714; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_715 = ~_out_T_1771; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_717 = _out_rofireMux_T_260 & out_backSel_114; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_718 = _out_rofireMux_T_717 & _out_T_1853; // @[RegisterRouter.scala:87:24] assign out_roready_1_979 = _out_rofireMux_T_718; // @[RegisterRouter.scala:87:24] assign out_roready_1_980 = _out_rofireMux_T_718; // @[RegisterRouter.scala:87:24] assign out_roready_1_981 = _out_rofireMux_T_718; // @[RegisterRouter.scala:87:24] assign out_roready_1_982 = _out_rofireMux_T_718; // @[RegisterRouter.scala:87:24] assign out_roready_1_983 = _out_rofireMux_T_718; // @[RegisterRouter.scala:87:24] assign out_roready_1_984 = _out_rofireMux_T_718; // @[RegisterRouter.scala:87:24] assign out_roready_1_985 = _out_rofireMux_T_718; // @[RegisterRouter.scala:87:24] assign out_roready_1_986 = _out_rofireMux_T_718; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_719 = ~_out_T_1853; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_721 = _out_rofireMux_T_260 & out_backSel_115; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_722 = _out_rofireMux_T_721 & _out_T_1609; // @[RegisterRouter.scala:87:24] assign out_roready_1_32 = _out_rofireMux_T_722; // @[RegisterRouter.scala:87:24] assign out_roready_1_33 = _out_rofireMux_T_722; // @[RegisterRouter.scala:87:24] assign out_roready_1_34 = _out_rofireMux_T_722; // @[RegisterRouter.scala:87:24] assign out_roready_1_35 = _out_rofireMux_T_722; // @[RegisterRouter.scala:87:24] assign out_roready_1_36 = _out_rofireMux_T_722; // @[RegisterRouter.scala:87:24] assign out_roready_1_37 = _out_rofireMux_T_722; // @[RegisterRouter.scala:87:24] assign out_roready_1_38 = _out_rofireMux_T_722; // @[RegisterRouter.scala:87:24] assign out_roready_1_39 = _out_rofireMux_T_722; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_723 = ~_out_T_1609; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_725 = _out_rofireMux_T_260 & out_backSel_116; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_726 = _out_rofireMux_T_725; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_729 = _out_rofireMux_T_260 & out_backSel_117; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_730 = _out_rofireMux_T_729; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_733 = _out_rofireMux_T_260 & out_backSel_118; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_734 = _out_rofireMux_T_733; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_737 = _out_rofireMux_T_260 & out_backSel_119; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_738 = _out_rofireMux_T_737; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_741 = _out_rofireMux_T_260 & out_backSel_120; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_742 = _out_rofireMux_T_741; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_745 = _out_rofireMux_T_260 & out_backSel_121; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_746 = _out_rofireMux_T_745; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_749 = _out_rofireMux_T_260 & out_backSel_122; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_750 = _out_rofireMux_T_749; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_753 = _out_rofireMux_T_260 & out_backSel_123; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_754 = _out_rofireMux_T_753; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_757 = _out_rofireMux_T_260 & out_backSel_124; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_758 = _out_rofireMux_T_757; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_761 = _out_rofireMux_T_260 & out_backSel_125; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_762 = _out_rofireMux_T_761; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_765 = _out_rofireMux_T_260 & out_backSel_126; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_766 = _out_rofireMux_T_765; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_769 = _out_rofireMux_T_260 & out_backSel_127; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_770 = _out_rofireMux_T_769; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_773 = _out_rofireMux_T_260 & out_backSel_128; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_774 = _out_rofireMux_T_773 & _out_T_1729; // @[RegisterRouter.scala:87:24] assign out_roready_1_495 = _out_rofireMux_T_774; // @[RegisterRouter.scala:87:24] assign out_roready_1_496 = _out_rofireMux_T_774; // @[RegisterRouter.scala:87:24] assign out_roready_1_497 = _out_rofireMux_T_774; // @[RegisterRouter.scala:87:24] assign out_roready_1_498 = _out_rofireMux_T_774; // @[RegisterRouter.scala:87:24] assign out_roready_1_499 = _out_rofireMux_T_774; // @[RegisterRouter.scala:87:24] assign out_roready_1_500 = _out_rofireMux_T_774; // @[RegisterRouter.scala:87:24] assign out_roready_1_501 = _out_rofireMux_T_774; // @[RegisterRouter.scala:87:24] assign out_roready_1_502 = _out_rofireMux_T_774; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_775 = ~_out_T_1729; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_777 = _out_rofireMux_T_260 & out_backSel_129; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_778 = _out_rofireMux_T_777 & _out_T_1721; // @[RegisterRouter.scala:87:24] assign out_roready_1_467 = _out_rofireMux_T_778; // @[RegisterRouter.scala:87:24] assign out_roready_1_468 = _out_rofireMux_T_778; // @[RegisterRouter.scala:87:24] assign out_roready_1_469 = _out_rofireMux_T_778; // @[RegisterRouter.scala:87:24] assign out_roready_1_470 = _out_rofireMux_T_778; // @[RegisterRouter.scala:87:24] assign out_roready_1_471 = _out_rofireMux_T_778; // @[RegisterRouter.scala:87:24] assign out_roready_1_472 = _out_rofireMux_T_778; // @[RegisterRouter.scala:87:24] assign out_roready_1_473 = _out_rofireMux_T_778; // @[RegisterRouter.scala:87:24] assign out_roready_1_474 = _out_rofireMux_T_778; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_779 = ~_out_T_1721; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_781 = _out_rofireMux_T_260 & out_backSel_130; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_782 = _out_rofireMux_T_781 & _out_T_1797; // @[RegisterRouter.scala:87:24] assign out_roready_1_755 = _out_rofireMux_T_782; // @[RegisterRouter.scala:87:24] assign out_roready_1_756 = _out_rofireMux_T_782; // @[RegisterRouter.scala:87:24] assign out_roready_1_757 = _out_rofireMux_T_782; // @[RegisterRouter.scala:87:24] assign out_roready_1_758 = _out_rofireMux_T_782; // @[RegisterRouter.scala:87:24] assign out_roready_1_759 = _out_rofireMux_T_782; // @[RegisterRouter.scala:87:24] assign out_roready_1_760 = _out_rofireMux_T_782; // @[RegisterRouter.scala:87:24] assign out_roready_1_761 = _out_rofireMux_T_782; // @[RegisterRouter.scala:87:24] assign out_roready_1_762 = _out_rofireMux_T_782; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_783 = ~_out_T_1797; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_785 = _out_rofireMux_T_260 & out_backSel_131; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_786 = _out_rofireMux_T_785 & _out_T_1891; // @[RegisterRouter.scala:87:24] assign out_roready_1_1131 = _out_rofireMux_T_786; // @[RegisterRouter.scala:87:24] assign out_roready_1_1132 = _out_rofireMux_T_786; // @[RegisterRouter.scala:87:24] assign out_roready_1_1133 = _out_rofireMux_T_786; // @[RegisterRouter.scala:87:24] assign out_roready_1_1134 = _out_rofireMux_T_786; // @[RegisterRouter.scala:87:24] assign out_roready_1_1135 = _out_rofireMux_T_786; // @[RegisterRouter.scala:87:24] assign out_roready_1_1136 = _out_rofireMux_T_786; // @[RegisterRouter.scala:87:24] assign out_roready_1_1137 = _out_rofireMux_T_786; // @[RegisterRouter.scala:87:24] assign out_roready_1_1138 = _out_rofireMux_T_786; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_787 = ~_out_T_1891; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_789 = _out_rofireMux_T_260 & out_backSel_132; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_790 = _out_rofireMux_T_789 & _out_T_1661; // @[RegisterRouter.scala:87:24] assign out_roready_1_240 = _out_rofireMux_T_790; // @[RegisterRouter.scala:87:24] assign out_roready_1_241 = _out_rofireMux_T_790; // @[RegisterRouter.scala:87:24] assign out_roready_1_242 = _out_rofireMux_T_790; // @[RegisterRouter.scala:87:24] assign out_roready_1_243 = _out_rofireMux_T_790; // @[RegisterRouter.scala:87:24] assign out_roready_1_244 = _out_rofireMux_T_790; // @[RegisterRouter.scala:87:24] assign out_roready_1_245 = _out_rofireMux_T_790; // @[RegisterRouter.scala:87:24] assign out_roready_1_246 = _out_rofireMux_T_790; // @[RegisterRouter.scala:87:24] assign out_roready_1_247 = _out_rofireMux_T_790; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_791 = ~_out_T_1661; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_793 = _out_rofireMux_T_260 & out_backSel_133; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_794 = _out_rofireMux_T_793 & _out_T_1663; // @[RegisterRouter.scala:87:24] assign out_roready_1_248 = _out_rofireMux_T_794; // @[RegisterRouter.scala:87:24] assign out_roready_1_249 = _out_rofireMux_T_794; // @[RegisterRouter.scala:87:24] assign out_roready_1_250 = _out_rofireMux_T_794; // @[RegisterRouter.scala:87:24] assign out_roready_1_251 = _out_rofireMux_T_794; // @[RegisterRouter.scala:87:24] assign out_roready_1_252 = _out_rofireMux_T_794; // @[RegisterRouter.scala:87:24] assign out_roready_1_253 = _out_rofireMux_T_794; // @[RegisterRouter.scala:87:24] assign out_roready_1_254 = _out_rofireMux_T_794; // @[RegisterRouter.scala:87:24] assign out_roready_1_255 = _out_rofireMux_T_794; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_795 = ~_out_T_1663; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_797 = _out_rofireMux_T_260 & out_backSel_134; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_798 = _out_rofireMux_T_797 & _out_T_1723; // @[RegisterRouter.scala:87:24] assign out_roready_1_475 = _out_rofireMux_T_798; // @[RegisterRouter.scala:87:24] assign out_roready_1_476 = _out_rofireMux_T_798; // @[RegisterRouter.scala:87:24] assign out_roready_1_477 = _out_rofireMux_T_798; // @[RegisterRouter.scala:87:24] assign out_roready_1_478 = _out_rofireMux_T_798; // @[RegisterRouter.scala:87:24] assign out_roready_1_479 = _out_rofireMux_T_798; // @[RegisterRouter.scala:87:24] assign out_roready_1_480 = _out_rofireMux_T_798; // @[RegisterRouter.scala:87:24] assign out_roready_1_481 = _out_rofireMux_T_798; // @[RegisterRouter.scala:87:24] assign out_roready_1_482 = _out_rofireMux_T_798; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_799 = ~_out_T_1723; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_801 = _out_rofireMux_T_260 & out_backSel_135; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_802 = _out_rofireMux_T_801 & _out_T_1801; // @[RegisterRouter.scala:87:24] assign out_roready_1_771 = _out_rofireMux_T_802; // @[RegisterRouter.scala:87:24] assign out_roready_1_772 = _out_rofireMux_T_802; // @[RegisterRouter.scala:87:24] assign out_roready_1_773 = _out_rofireMux_T_802; // @[RegisterRouter.scala:87:24] assign out_roready_1_774 = _out_rofireMux_T_802; // @[RegisterRouter.scala:87:24] assign out_roready_1_775 = _out_rofireMux_T_802; // @[RegisterRouter.scala:87:24] assign out_roready_1_776 = _out_rofireMux_T_802; // @[RegisterRouter.scala:87:24] assign out_roready_1_777 = _out_rofireMux_T_802; // @[RegisterRouter.scala:87:24] assign out_roready_1_778 = _out_rofireMux_T_802; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_803 = ~_out_T_1801; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_805 = _out_rofireMux_T_260 & out_backSel_136; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_806 = _out_rofireMux_T_805 & _out_T_1883; // @[RegisterRouter.scala:87:24] assign out_roready_1_1099 = _out_rofireMux_T_806; // @[RegisterRouter.scala:87:24] assign out_roready_1_1100 = _out_rofireMux_T_806; // @[RegisterRouter.scala:87:24] assign out_roready_1_1101 = _out_rofireMux_T_806; // @[RegisterRouter.scala:87:24] assign out_roready_1_1102 = _out_rofireMux_T_806; // @[RegisterRouter.scala:87:24] assign out_roready_1_1103 = _out_rofireMux_T_806; // @[RegisterRouter.scala:87:24] assign out_roready_1_1104 = _out_rofireMux_T_806; // @[RegisterRouter.scala:87:24] assign out_roready_1_1105 = _out_rofireMux_T_806; // @[RegisterRouter.scala:87:24] assign out_roready_1_1106 = _out_rofireMux_T_806; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_807 = ~_out_T_1883; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_809 = _out_rofireMux_T_260 & out_backSel_137; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_810 = _out_rofireMux_T_809 & _out_T_1685; // @[RegisterRouter.scala:87:24] assign out_roready_1_336 = _out_rofireMux_T_810; // @[RegisterRouter.scala:87:24] assign out_roready_1_337 = _out_rofireMux_T_810; // @[RegisterRouter.scala:87:24] assign out_roready_1_338 = _out_rofireMux_T_810; // @[RegisterRouter.scala:87:24] assign out_roready_1_339 = _out_rofireMux_T_810; // @[RegisterRouter.scala:87:24] assign out_roready_1_340 = _out_rofireMux_T_810; // @[RegisterRouter.scala:87:24] assign out_roready_1_341 = _out_rofireMux_T_810; // @[RegisterRouter.scala:87:24] assign out_roready_1_342 = _out_rofireMux_T_810; // @[RegisterRouter.scala:87:24] assign out_roready_1_343 = _out_rofireMux_T_810; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_811 = ~_out_T_1685; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_813 = _out_rofireMux_T_260 & out_backSel_138; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_814 = _out_rofireMux_T_813 & _out_T_1601; // @[RegisterRouter.scala:87:24] assign out_roready_1_0 = _out_rofireMux_T_814; // @[RegisterRouter.scala:87:24] assign out_roready_1_1 = _out_rofireMux_T_814; // @[RegisterRouter.scala:87:24] assign out_roready_1_2 = _out_rofireMux_T_814; // @[RegisterRouter.scala:87:24] assign out_roready_1_3 = _out_rofireMux_T_814; // @[RegisterRouter.scala:87:24] assign out_roready_1_4 = _out_rofireMux_T_814; // @[RegisterRouter.scala:87:24] assign out_roready_1_5 = _out_rofireMux_T_814; // @[RegisterRouter.scala:87:24] assign out_roready_1_6 = _out_rofireMux_T_814; // @[RegisterRouter.scala:87:24] assign out_roready_1_7 = _out_rofireMux_T_814; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_815 = ~_out_T_1601; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_817 = _out_rofireMux_T_260 & out_backSel_139; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_818 = _out_rofireMux_T_817 & _out_T_1857; // @[RegisterRouter.scala:87:24] assign out_roready_1_995 = _out_rofireMux_T_818; // @[RegisterRouter.scala:87:24] assign out_roready_1_996 = _out_rofireMux_T_818; // @[RegisterRouter.scala:87:24] assign out_roready_1_997 = _out_rofireMux_T_818; // @[RegisterRouter.scala:87:24] assign out_roready_1_998 = _out_rofireMux_T_818; // @[RegisterRouter.scala:87:24] assign out_roready_1_999 = _out_rofireMux_T_818; // @[RegisterRouter.scala:87:24] assign out_roready_1_1000 = _out_rofireMux_T_818; // @[RegisterRouter.scala:87:24] assign out_roready_1_1001 = _out_rofireMux_T_818; // @[RegisterRouter.scala:87:24] assign out_roready_1_1002 = _out_rofireMux_T_818; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_819 = ~_out_T_1857; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_821 = _out_rofireMux_T_260 & out_backSel_140; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_822 = _out_rofireMux_T_821 & _out_T_1783; // @[RegisterRouter.scala:87:24] assign out_roready_1_699 = _out_rofireMux_T_822; // @[RegisterRouter.scala:87:24] assign out_roready_1_700 = _out_rofireMux_T_822; // @[RegisterRouter.scala:87:24] assign out_roready_1_701 = _out_rofireMux_T_822; // @[RegisterRouter.scala:87:24] assign out_roready_1_702 = _out_rofireMux_T_822; // @[RegisterRouter.scala:87:24] assign out_roready_1_703 = _out_rofireMux_T_822; // @[RegisterRouter.scala:87:24] assign out_roready_1_704 = _out_rofireMux_T_822; // @[RegisterRouter.scala:87:24] assign out_roready_1_705 = _out_rofireMux_T_822; // @[RegisterRouter.scala:87:24] assign out_roready_1_706 = _out_rofireMux_T_822; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_823 = ~_out_T_1783; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_825 = _out_rofireMux_T_260 & out_backSel_141; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_826 = _out_rofireMux_T_825 & _out_T_1705; // @[RegisterRouter.scala:87:24] assign out_roready_1_410 = _out_rofireMux_T_826; // @[RegisterRouter.scala:87:24] assign out_roready_1_411 = _out_rofireMux_T_826; // @[RegisterRouter.scala:87:24] assign out_roready_1_412 = _out_rofireMux_T_826; // @[RegisterRouter.scala:87:24] assign out_roready_1_413 = _out_rofireMux_T_826; // @[RegisterRouter.scala:87:24] assign out_roready_1_414 = _out_rofireMux_T_826; // @[RegisterRouter.scala:87:24] assign out_roready_1_415 = _out_rofireMux_T_826; // @[RegisterRouter.scala:87:24] assign out_roready_1_416 = _out_rofireMux_T_826; // @[RegisterRouter.scala:87:24] assign out_roready_1_417 = _out_rofireMux_T_826; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_827 = ~_out_T_1705; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_829 = _out_rofireMux_T_260 & out_backSel_142; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_830 = _out_rofireMux_T_829 & _out_T_1617; // @[RegisterRouter.scala:87:24] assign out_roready_1_64 = _out_rofireMux_T_830; // @[RegisterRouter.scala:87:24] assign out_roready_1_65 = _out_rofireMux_T_830; // @[RegisterRouter.scala:87:24] assign out_roready_1_66 = _out_rofireMux_T_830; // @[RegisterRouter.scala:87:24] assign out_roready_1_67 = _out_rofireMux_T_830; // @[RegisterRouter.scala:87:24] assign out_roready_1_68 = _out_rofireMux_T_830; // @[RegisterRouter.scala:87:24] assign out_roready_1_69 = _out_rofireMux_T_830; // @[RegisterRouter.scala:87:24] assign out_roready_1_70 = _out_rofireMux_T_830; // @[RegisterRouter.scala:87:24] assign out_roready_1_71 = _out_rofireMux_T_830; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_831 = ~_out_T_1617; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_833 = _out_rofireMux_T_260 & out_backSel_143; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_834 = _out_rofireMux_T_833 & _out_T_1835; // @[RegisterRouter.scala:87:24] assign out_roready_1_907 = _out_rofireMux_T_834; // @[RegisterRouter.scala:87:24] assign out_roready_1_908 = _out_rofireMux_T_834; // @[RegisterRouter.scala:87:24] assign out_roready_1_909 = _out_rofireMux_T_834; // @[RegisterRouter.scala:87:24] assign out_roready_1_910 = _out_rofireMux_T_834; // @[RegisterRouter.scala:87:24] assign out_roready_1_911 = _out_rofireMux_T_834; // @[RegisterRouter.scala:87:24] assign out_roready_1_912 = _out_rofireMux_T_834; // @[RegisterRouter.scala:87:24] assign out_roready_1_913 = _out_rofireMux_T_834; // @[RegisterRouter.scala:87:24] assign out_roready_1_914 = _out_rofireMux_T_834; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_835 = ~_out_T_1835; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_837 = _out_rofireMux_T_260 & out_backSel_144; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_838 = _out_rofireMux_T_837 & _out_T_1759; // @[RegisterRouter.scala:87:24] assign out_roready_1_609 = _out_rofireMux_T_838; // @[RegisterRouter.scala:87:24] assign out_roready_1_610 = _out_rofireMux_T_838; // @[RegisterRouter.scala:87:24] assign out_roready_1_611 = _out_rofireMux_T_838; // @[RegisterRouter.scala:87:24] assign out_roready_1_612 = _out_rofireMux_T_838; // @[RegisterRouter.scala:87:24] assign out_roready_1_613 = _out_rofireMux_T_838; // @[RegisterRouter.scala:87:24] assign out_roready_1_614 = _out_rofireMux_T_838; // @[RegisterRouter.scala:87:24] assign out_roready_1_615 = _out_rofireMux_T_838; // @[RegisterRouter.scala:87:24] assign out_roready_1_616 = _out_rofireMux_T_838; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_839 = ~_out_T_1759; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_841 = _out_rofireMux_T_260 & out_backSel_145; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_842 = _out_rofireMux_T_841 & _out_T_1819; // @[RegisterRouter.scala:87:24] assign out_roready_1_843 = _out_rofireMux_T_842; // @[RegisterRouter.scala:87:24] assign out_roready_1_844 = _out_rofireMux_T_842; // @[RegisterRouter.scala:87:24] assign out_roready_1_845 = _out_rofireMux_T_842; // @[RegisterRouter.scala:87:24] assign out_roready_1_846 = _out_rofireMux_T_842; // @[RegisterRouter.scala:87:24] assign out_roready_1_847 = _out_rofireMux_T_842; // @[RegisterRouter.scala:87:24] assign out_roready_1_848 = _out_rofireMux_T_842; // @[RegisterRouter.scala:87:24] assign out_roready_1_849 = _out_rofireMux_T_842; // @[RegisterRouter.scala:87:24] assign out_roready_1_850 = _out_rofireMux_T_842; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_843 = ~_out_T_1819; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_845 = _out_rofireMux_T_260 & out_backSel_146; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_846 = _out_rofireMux_T_845 & _out_T_1869; // @[RegisterRouter.scala:87:24] assign out_roready_1_1043 = _out_rofireMux_T_846; // @[RegisterRouter.scala:87:24] assign out_roready_1_1044 = _out_rofireMux_T_846; // @[RegisterRouter.scala:87:24] assign out_roready_1_1045 = _out_rofireMux_T_846; // @[RegisterRouter.scala:87:24] assign out_roready_1_1046 = _out_rofireMux_T_846; // @[RegisterRouter.scala:87:24] assign out_roready_1_1047 = _out_rofireMux_T_846; // @[RegisterRouter.scala:87:24] assign out_roready_1_1048 = _out_rofireMux_T_846; // @[RegisterRouter.scala:87:24] assign out_roready_1_1049 = _out_rofireMux_T_846; // @[RegisterRouter.scala:87:24] assign out_roready_1_1050 = _out_rofireMux_T_846; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_847 = ~_out_T_1869; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_849 = _out_rofireMux_T_260 & out_backSel_147; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_850 = _out_rofireMux_T_849 & _out_T_1657; // @[RegisterRouter.scala:87:24] assign out_roready_1_224 = _out_rofireMux_T_850; // @[RegisterRouter.scala:87:24] assign out_roready_1_225 = _out_rofireMux_T_850; // @[RegisterRouter.scala:87:24] assign out_roready_1_226 = _out_rofireMux_T_850; // @[RegisterRouter.scala:87:24] assign out_roready_1_227 = _out_rofireMux_T_850; // @[RegisterRouter.scala:87:24] assign out_roready_1_228 = _out_rofireMux_T_850; // @[RegisterRouter.scala:87:24] assign out_roready_1_229 = _out_rofireMux_T_850; // @[RegisterRouter.scala:87:24] assign out_roready_1_230 = _out_rofireMux_T_850; // @[RegisterRouter.scala:87:24] assign out_roready_1_231 = _out_rofireMux_T_850; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_851 = ~_out_T_1657; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_853 = _out_rofireMux_T_260 & out_backSel_148; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_854 = _out_rofireMux_T_853 & _out_T_1741; // @[RegisterRouter.scala:87:24] assign out_roready_1_537 = _out_rofireMux_T_854; // @[RegisterRouter.scala:87:24] assign out_roready_1_538 = _out_rofireMux_T_854; // @[RegisterRouter.scala:87:24] assign out_roready_1_539 = _out_rofireMux_T_854; // @[RegisterRouter.scala:87:24] assign out_roready_1_540 = _out_rofireMux_T_854; // @[RegisterRouter.scala:87:24] assign out_roready_1_541 = _out_rofireMux_T_854; // @[RegisterRouter.scala:87:24] assign out_roready_1_542 = _out_rofireMux_T_854; // @[RegisterRouter.scala:87:24] assign out_roready_1_543 = _out_rofireMux_T_854; // @[RegisterRouter.scala:87:24] assign out_roready_1_544 = _out_rofireMux_T_854; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_855 = ~_out_T_1741; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_857 = _out_rofireMux_T_260 & out_backSel_149; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_858 = _out_rofireMux_T_857 & _out_T_1749; // @[RegisterRouter.scala:87:24] assign out_roready_1_569 = _out_rofireMux_T_858; // @[RegisterRouter.scala:87:24] assign out_roready_1_570 = _out_rofireMux_T_858; // @[RegisterRouter.scala:87:24] assign out_roready_1_571 = _out_rofireMux_T_858; // @[RegisterRouter.scala:87:24] assign out_roready_1_572 = _out_rofireMux_T_858; // @[RegisterRouter.scala:87:24] assign out_roready_1_573 = _out_rofireMux_T_858; // @[RegisterRouter.scala:87:24] assign out_roready_1_574 = _out_rofireMux_T_858; // @[RegisterRouter.scala:87:24] assign out_roready_1_575 = _out_rofireMux_T_858; // @[RegisterRouter.scala:87:24] assign out_roready_1_576 = _out_rofireMux_T_858; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_859 = ~_out_T_1749; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_861 = _out_rofireMux_T_260 & out_backSel_150; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_862 = _out_rofireMux_T_861 & _out_T_1821; // @[RegisterRouter.scala:87:24] assign out_roready_1_851 = _out_rofireMux_T_862; // @[RegisterRouter.scala:87:24] assign out_roready_1_852 = _out_rofireMux_T_862; // @[RegisterRouter.scala:87:24] assign out_roready_1_853 = _out_rofireMux_T_862; // @[RegisterRouter.scala:87:24] assign out_roready_1_854 = _out_rofireMux_T_862; // @[RegisterRouter.scala:87:24] assign out_roready_1_855 = _out_rofireMux_T_862; // @[RegisterRouter.scala:87:24] assign out_roready_1_856 = _out_rofireMux_T_862; // @[RegisterRouter.scala:87:24] assign out_roready_1_857 = _out_rofireMux_T_862; // @[RegisterRouter.scala:87:24] assign out_roready_1_858 = _out_rofireMux_T_862; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_863 = ~_out_T_1821; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_865 = _out_rofireMux_T_260 & out_backSel_151; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_866 = _out_rofireMux_T_865 & _out_T_1867; // @[RegisterRouter.scala:87:24] assign out_roready_1_1035 = _out_rofireMux_T_866; // @[RegisterRouter.scala:87:24] assign out_roready_1_1036 = _out_rofireMux_T_866; // @[RegisterRouter.scala:87:24] assign out_roready_1_1037 = _out_rofireMux_T_866; // @[RegisterRouter.scala:87:24] assign out_roready_1_1038 = _out_rofireMux_T_866; // @[RegisterRouter.scala:87:24] assign out_roready_1_1039 = _out_rofireMux_T_866; // @[RegisterRouter.scala:87:24] assign out_roready_1_1040 = _out_rofireMux_T_866; // @[RegisterRouter.scala:87:24] assign out_roready_1_1041 = _out_rofireMux_T_866; // @[RegisterRouter.scala:87:24] assign out_roready_1_1042 = _out_rofireMux_T_866; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_867 = ~_out_T_1867; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_869 = _out_rofireMux_T_260 & out_backSel_152; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_870 = _out_rofireMux_T_869 & _out_T_1637; // @[RegisterRouter.scala:87:24] assign out_roready_1_144 = _out_rofireMux_T_870; // @[RegisterRouter.scala:87:24] assign out_roready_1_145 = _out_rofireMux_T_870; // @[RegisterRouter.scala:87:24] assign out_roready_1_146 = _out_rofireMux_T_870; // @[RegisterRouter.scala:87:24] assign out_roready_1_147 = _out_rofireMux_T_870; // @[RegisterRouter.scala:87:24] assign out_roready_1_148 = _out_rofireMux_T_870; // @[RegisterRouter.scala:87:24] assign out_roready_1_149 = _out_rofireMux_T_870; // @[RegisterRouter.scala:87:24] assign out_roready_1_150 = _out_rofireMux_T_870; // @[RegisterRouter.scala:87:24] assign out_roready_1_151 = _out_rofireMux_T_870; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_871 = ~_out_T_1637; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_873 = _out_rofireMux_T_260 & out_backSel_153; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_874 = _out_rofireMux_T_873 & _out_T_1619; // @[RegisterRouter.scala:87:24] assign out_roready_1_72 = _out_rofireMux_T_874; // @[RegisterRouter.scala:87:24] assign out_roready_1_73 = _out_rofireMux_T_874; // @[RegisterRouter.scala:87:24] assign out_roready_1_74 = _out_rofireMux_T_874; // @[RegisterRouter.scala:87:24] assign out_roready_1_75 = _out_rofireMux_T_874; // @[RegisterRouter.scala:87:24] assign out_roready_1_76 = _out_rofireMux_T_874; // @[RegisterRouter.scala:87:24] assign out_roready_1_77 = _out_rofireMux_T_874; // @[RegisterRouter.scala:87:24] assign out_roready_1_78 = _out_rofireMux_T_874; // @[RegisterRouter.scala:87:24] assign out_roready_1_79 = _out_rofireMux_T_874; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_875 = ~_out_T_1619; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_877 = _out_rofireMux_T_260 & out_backSel_154; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_878 = _out_rofireMux_T_877 & _out_T_1831; // @[RegisterRouter.scala:87:24] assign out_roready_1_891 = _out_rofireMux_T_878; // @[RegisterRouter.scala:87:24] assign out_roready_1_892 = _out_rofireMux_T_878; // @[RegisterRouter.scala:87:24] assign out_roready_1_893 = _out_rofireMux_T_878; // @[RegisterRouter.scala:87:24] assign out_roready_1_894 = _out_rofireMux_T_878; // @[RegisterRouter.scala:87:24] assign out_roready_1_895 = _out_rofireMux_T_878; // @[RegisterRouter.scala:87:24] assign out_roready_1_896 = _out_rofireMux_T_878; // @[RegisterRouter.scala:87:24] assign out_roready_1_897 = _out_rofireMux_T_878; // @[RegisterRouter.scala:87:24] assign out_roready_1_898 = _out_rofireMux_T_878; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_879 = ~_out_T_1831; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_881 = _out_rofireMux_T_260 & out_backSel_155; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_882 = _out_rofireMux_T_881 & _out_T_1787; // @[RegisterRouter.scala:87:24] assign out_roready_1_715 = _out_rofireMux_T_882; // @[RegisterRouter.scala:87:24] assign out_roready_1_716 = _out_rofireMux_T_882; // @[RegisterRouter.scala:87:24] assign out_roready_1_717 = _out_rofireMux_T_882; // @[RegisterRouter.scala:87:24] assign out_roready_1_718 = _out_rofireMux_T_882; // @[RegisterRouter.scala:87:24] assign out_roready_1_719 = _out_rofireMux_T_882; // @[RegisterRouter.scala:87:24] assign out_roready_1_720 = _out_rofireMux_T_882; // @[RegisterRouter.scala:87:24] assign out_roready_1_721 = _out_rofireMux_T_882; // @[RegisterRouter.scala:87:24] assign out_roready_1_722 = _out_rofireMux_T_882; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_883 = ~_out_T_1787; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_885 = _out_rofireMux_T_260 & out_backSel_156; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_886 = _out_rofireMux_T_885 & _out_T_1699; // @[RegisterRouter.scala:87:24] assign out_roready_1_386 = _out_rofireMux_T_886; // @[RegisterRouter.scala:87:24] assign out_roready_1_387 = _out_rofireMux_T_886; // @[RegisterRouter.scala:87:24] assign out_roready_1_388 = _out_rofireMux_T_886; // @[RegisterRouter.scala:87:24] assign out_roready_1_389 = _out_rofireMux_T_886; // @[RegisterRouter.scala:87:24] assign out_roready_1_390 = _out_rofireMux_T_886; // @[RegisterRouter.scala:87:24] assign out_roready_1_391 = _out_rofireMux_T_886; // @[RegisterRouter.scala:87:24] assign out_roready_1_392 = _out_rofireMux_T_886; // @[RegisterRouter.scala:87:24] assign out_roready_1_393 = _out_rofireMux_T_886; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_887 = ~_out_T_1699; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_889 = _out_rofireMux_T_260 & out_backSel_157; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_890 = _out_rofireMux_T_889 & _out_T_1633; // @[RegisterRouter.scala:87:24] assign out_roready_1_128 = _out_rofireMux_T_890; // @[RegisterRouter.scala:87:24] assign out_roready_1_129 = _out_rofireMux_T_890; // @[RegisterRouter.scala:87:24] assign out_roready_1_130 = _out_rofireMux_T_890; // @[RegisterRouter.scala:87:24] assign out_roready_1_131 = _out_rofireMux_T_890; // @[RegisterRouter.scala:87:24] assign out_roready_1_132 = _out_rofireMux_T_890; // @[RegisterRouter.scala:87:24] assign out_roready_1_133 = _out_rofireMux_T_890; // @[RegisterRouter.scala:87:24] assign out_roready_1_134 = _out_rofireMux_T_890; // @[RegisterRouter.scala:87:24] assign out_roready_1_135 = _out_rofireMux_T_890; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_891 = ~_out_T_1633; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_893 = _out_rofireMux_T_260 & out_backSel_158; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_894 = _out_rofireMux_T_893 & _out_T_1849; // @[RegisterRouter.scala:87:24] assign out_roready_1_963 = _out_rofireMux_T_894; // @[RegisterRouter.scala:87:24] assign out_roready_1_964 = _out_rofireMux_T_894; // @[RegisterRouter.scala:87:24] assign out_roready_1_965 = _out_rofireMux_T_894; // @[RegisterRouter.scala:87:24] assign out_roready_1_966 = _out_rofireMux_T_894; // @[RegisterRouter.scala:87:24] assign out_roready_1_967 = _out_rofireMux_T_894; // @[RegisterRouter.scala:87:24] assign out_roready_1_968 = _out_rofireMux_T_894; // @[RegisterRouter.scala:87:24] assign out_roready_1_969 = _out_rofireMux_T_894; // @[RegisterRouter.scala:87:24] assign out_roready_1_970 = _out_rofireMux_T_894; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_895 = ~_out_T_1849; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_897 = _out_rofireMux_T_260 & out_backSel_159; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_898 = _out_rofireMux_T_897 & _out_T_1765; // @[RegisterRouter.scala:87:24] assign out_roready_1_633 = _out_rofireMux_T_898; // @[RegisterRouter.scala:87:24] assign out_roready_1_634 = _out_rofireMux_T_898; // @[RegisterRouter.scala:87:24] assign out_roready_1_635 = _out_rofireMux_T_898; // @[RegisterRouter.scala:87:24] assign out_roready_1_636 = _out_rofireMux_T_898; // @[RegisterRouter.scala:87:24] assign out_roready_1_637 = _out_rofireMux_T_898; // @[RegisterRouter.scala:87:24] assign out_roready_1_638 = _out_rofireMux_T_898; // @[RegisterRouter.scala:87:24] assign out_roready_1_639 = _out_rofireMux_T_898; // @[RegisterRouter.scala:87:24] assign out_roready_1_640 = _out_rofireMux_T_898; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_899 = ~_out_T_1765; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_901 = _out_rofireMux_T_260 & out_backSel_160; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_902 = _out_rofireMux_T_901 & _out_T_1681; // @[RegisterRouter.scala:87:24] assign out_roready_1_320 = _out_rofireMux_T_902; // @[RegisterRouter.scala:87:24] assign out_roready_1_321 = _out_rofireMux_T_902; // @[RegisterRouter.scala:87:24] assign out_roready_1_322 = _out_rofireMux_T_902; // @[RegisterRouter.scala:87:24] assign out_roready_1_323 = _out_rofireMux_T_902; // @[RegisterRouter.scala:87:24] assign out_roready_1_324 = _out_rofireMux_T_902; // @[RegisterRouter.scala:87:24] assign out_roready_1_325 = _out_rofireMux_T_902; // @[RegisterRouter.scala:87:24] assign out_roready_1_326 = _out_rofireMux_T_902; // @[RegisterRouter.scala:87:24] assign out_roready_1_327 = _out_rofireMux_T_902; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_903 = ~_out_T_1681; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_905 = _out_rofireMux_T_260 & out_backSel_161; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_906 = _out_rofireMux_T_905 & _out_T_1745; // @[RegisterRouter.scala:87:24] assign out_roready_1_553 = _out_rofireMux_T_906; // @[RegisterRouter.scala:87:24] assign out_roready_1_554 = _out_rofireMux_T_906; // @[RegisterRouter.scala:87:24] assign out_roready_1_555 = _out_rofireMux_T_906; // @[RegisterRouter.scala:87:24] assign out_roready_1_556 = _out_rofireMux_T_906; // @[RegisterRouter.scala:87:24] assign out_roready_1_557 = _out_rofireMux_T_906; // @[RegisterRouter.scala:87:24] assign out_roready_1_558 = _out_rofireMux_T_906; // @[RegisterRouter.scala:87:24] assign out_roready_1_559 = _out_rofireMux_T_906; // @[RegisterRouter.scala:87:24] assign out_roready_1_560 = _out_rofireMux_T_906; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_907 = ~_out_T_1745; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_909 = _out_rofireMux_T_260 & out_backSel_162; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_910 = _out_rofireMux_T_909 & _out_T_1809; // @[RegisterRouter.scala:87:24] assign out_roready_1_803 = _out_rofireMux_T_910; // @[RegisterRouter.scala:87:24] assign out_roready_1_804 = _out_rofireMux_T_910; // @[RegisterRouter.scala:87:24] assign out_roready_1_805 = _out_rofireMux_T_910; // @[RegisterRouter.scala:87:24] assign out_roready_1_806 = _out_rofireMux_T_910; // @[RegisterRouter.scala:87:24] assign out_roready_1_807 = _out_rofireMux_T_910; // @[RegisterRouter.scala:87:24] assign out_roready_1_808 = _out_rofireMux_T_910; // @[RegisterRouter.scala:87:24] assign out_roready_1_809 = _out_rofireMux_T_910; // @[RegisterRouter.scala:87:24] assign out_roready_1_810 = _out_rofireMux_T_910; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_911 = ~_out_T_1809; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_913 = _out_rofireMux_T_260 & out_backSel_163; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_914 = _out_rofireMux_T_913 & _out_T_1895; // @[RegisterRouter.scala:87:24] assign out_roready_1_1147 = _out_rofireMux_T_914; // @[RegisterRouter.scala:87:24] assign out_roready_1_1148 = _out_rofireMux_T_914; // @[RegisterRouter.scala:87:24] assign out_roready_1_1149 = _out_rofireMux_T_914; // @[RegisterRouter.scala:87:24] assign out_roready_1_1150 = _out_rofireMux_T_914; // @[RegisterRouter.scala:87:24] assign out_roready_1_1151 = _out_rofireMux_T_914; // @[RegisterRouter.scala:87:24] assign out_roready_1_1152 = _out_rofireMux_T_914; // @[RegisterRouter.scala:87:24] assign out_roready_1_1153 = _out_rofireMux_T_914; // @[RegisterRouter.scala:87:24] assign out_roready_1_1154 = _out_rofireMux_T_914; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_915 = ~_out_T_1895; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_917 = _out_rofireMux_T_260 & out_backSel_164; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_918 = _out_rofireMux_T_917 & _out_T_1645; // @[RegisterRouter.scala:87:24] assign out_roready_1_176 = _out_rofireMux_T_918; // @[RegisterRouter.scala:87:24] assign out_roready_1_177 = _out_rofireMux_T_918; // @[RegisterRouter.scala:87:24] assign out_roready_1_178 = _out_rofireMux_T_918; // @[RegisterRouter.scala:87:24] assign out_roready_1_179 = _out_rofireMux_T_918; // @[RegisterRouter.scala:87:24] assign out_roready_1_180 = _out_rofireMux_T_918; // @[RegisterRouter.scala:87:24] assign out_roready_1_181 = _out_rofireMux_T_918; // @[RegisterRouter.scala:87:24] assign out_roready_1_182 = _out_rofireMux_T_918; // @[RegisterRouter.scala:87:24] assign out_roready_1_183 = _out_rofireMux_T_918; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_919 = ~_out_T_1645; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_921 = _out_rofireMux_T_260 & out_backSel_165; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_922 = _out_rofireMux_T_921 & _out_T_1687; // @[RegisterRouter.scala:87:24] assign out_roready_1_344 = _out_rofireMux_T_922; // @[RegisterRouter.scala:87:24] assign out_roready_1_345 = _out_rofireMux_T_922; // @[RegisterRouter.scala:87:24] assign out_roready_1_346 = _out_rofireMux_T_922; // @[RegisterRouter.scala:87:24] assign out_roready_1_347 = _out_rofireMux_T_922; // @[RegisterRouter.scala:87:24] assign out_roready_1_348 = _out_rofireMux_T_922; // @[RegisterRouter.scala:87:24] assign out_roready_1_349 = _out_rofireMux_T_922; // @[RegisterRouter.scala:87:24] assign out_roready_1_350 = _out_rofireMux_T_922; // @[RegisterRouter.scala:87:24] assign out_roready_1_351 = _out_rofireMux_T_922; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_923 = ~_out_T_1687; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_925 = _out_rofireMux_T_260 & out_backSel_166; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_926 = _out_rofireMux_T_925 & _out_T_1737; // @[RegisterRouter.scala:87:24] assign out_roready_1_527 = _out_rofireMux_T_926; // @[RegisterRouter.scala:87:24] assign out_roready_1_528 = _out_rofireMux_T_926; // @[RegisterRouter.scala:87:24] assign out_roready_1_529 = _out_rofireMux_T_926; // @[RegisterRouter.scala:87:24] assign out_roready_1_530 = _out_rofireMux_T_926; // @[RegisterRouter.scala:87:24] assign out_roready_1_531 = _out_rofireMux_T_926; // @[RegisterRouter.scala:87:24] assign out_roready_1_532 = _out_rofireMux_T_926; // @[RegisterRouter.scala:87:24] assign out_roready_1_533 = _out_rofireMux_T_926; // @[RegisterRouter.scala:87:24] assign out_roready_1_534 = _out_rofireMux_T_926; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_927 = ~_out_T_1737; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_929 = _out_rofireMux_T_260 & out_backSel_167; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_930 = _out_rofireMux_T_929 & _out_T_1807; // @[RegisterRouter.scala:87:24] assign out_roready_1_795 = _out_rofireMux_T_930; // @[RegisterRouter.scala:87:24] assign out_roready_1_796 = _out_rofireMux_T_930; // @[RegisterRouter.scala:87:24] assign out_roready_1_797 = _out_rofireMux_T_930; // @[RegisterRouter.scala:87:24] assign out_roready_1_798 = _out_rofireMux_T_930; // @[RegisterRouter.scala:87:24] assign out_roready_1_799 = _out_rofireMux_T_930; // @[RegisterRouter.scala:87:24] assign out_roready_1_800 = _out_rofireMux_T_930; // @[RegisterRouter.scala:87:24] assign out_roready_1_801 = _out_rofireMux_T_930; // @[RegisterRouter.scala:87:24] assign out_roready_1_802 = _out_rofireMux_T_930; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_931 = ~_out_T_1807; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_933 = _out_rofireMux_T_260 & out_backSel_168; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_934 = _out_rofireMux_T_933 & _out_T_1875; // @[RegisterRouter.scala:87:24] assign out_roready_1_1067 = _out_rofireMux_T_934; // @[RegisterRouter.scala:87:24] assign out_roready_1_1068 = _out_rofireMux_T_934; // @[RegisterRouter.scala:87:24] assign out_roready_1_1069 = _out_rofireMux_T_934; // @[RegisterRouter.scala:87:24] assign out_roready_1_1070 = _out_rofireMux_T_934; // @[RegisterRouter.scala:87:24] assign out_roready_1_1071 = _out_rofireMux_T_934; // @[RegisterRouter.scala:87:24] assign out_roready_1_1072 = _out_rofireMux_T_934; // @[RegisterRouter.scala:87:24] assign out_roready_1_1073 = _out_rofireMux_T_934; // @[RegisterRouter.scala:87:24] assign out_roready_1_1074 = _out_rofireMux_T_934; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_935 = ~_out_T_1875; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_937 = _out_rofireMux_T_260 & out_backSel_169; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_938 = _out_rofireMux_T_937 & _out_T_1703; // @[RegisterRouter.scala:87:24] assign out_roready_1_402 = _out_rofireMux_T_938; // @[RegisterRouter.scala:87:24] assign out_roready_1_403 = _out_rofireMux_T_938; // @[RegisterRouter.scala:87:24] assign out_roready_1_404 = _out_rofireMux_T_938; // @[RegisterRouter.scala:87:24] assign out_roready_1_405 = _out_rofireMux_T_938; // @[RegisterRouter.scala:87:24] assign out_roready_1_406 = _out_rofireMux_T_938; // @[RegisterRouter.scala:87:24] assign out_roready_1_407 = _out_rofireMux_T_938; // @[RegisterRouter.scala:87:24] assign out_roready_1_408 = _out_rofireMux_T_938; // @[RegisterRouter.scala:87:24] assign out_roready_1_409 = _out_rofireMux_T_938; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_939 = ~_out_T_1703; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_941 = _out_rofireMux_T_260 & out_backSel_170; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_942 = _out_rofireMux_T_941 & _out_T_1607; // @[RegisterRouter.scala:87:24] assign out_roready_1_24 = _out_rofireMux_T_942; // @[RegisterRouter.scala:87:24] assign out_roready_1_25 = _out_rofireMux_T_942; // @[RegisterRouter.scala:87:24] assign out_roready_1_26 = _out_rofireMux_T_942; // @[RegisterRouter.scala:87:24] assign out_roready_1_27 = _out_rofireMux_T_942; // @[RegisterRouter.scala:87:24] assign out_roready_1_28 = _out_rofireMux_T_942; // @[RegisterRouter.scala:87:24] assign out_roready_1_29 = _out_rofireMux_T_942; // @[RegisterRouter.scala:87:24] assign out_roready_1_30 = _out_rofireMux_T_942; // @[RegisterRouter.scala:87:24] assign out_roready_1_31 = _out_rofireMux_T_942; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_943 = ~_out_T_1607; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_945 = _out_rofireMux_T_260 & out_backSel_171; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_946 = _out_rofireMux_T_945 & _out_T_1855; // @[RegisterRouter.scala:87:24] assign out_roready_1_987 = _out_rofireMux_T_946; // @[RegisterRouter.scala:87:24] assign out_roready_1_988 = _out_rofireMux_T_946; // @[RegisterRouter.scala:87:24] assign out_roready_1_989 = _out_rofireMux_T_946; // @[RegisterRouter.scala:87:24] assign out_roready_1_990 = _out_rofireMux_T_946; // @[RegisterRouter.scala:87:24] assign out_roready_1_991 = _out_rofireMux_T_946; // @[RegisterRouter.scala:87:24] assign out_roready_1_992 = _out_rofireMux_T_946; // @[RegisterRouter.scala:87:24] assign out_roready_1_993 = _out_rofireMux_T_946; // @[RegisterRouter.scala:87:24] assign out_roready_1_994 = _out_rofireMux_T_946; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_947 = ~_out_T_1855; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_949 = _out_rofireMux_T_260 & out_backSel_172; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_950 = _out_rofireMux_T_949 & _out_T_1769; // @[RegisterRouter.scala:87:24] assign out_roready_1_649 = _out_rofireMux_T_950; // @[RegisterRouter.scala:87:24] assign out_roready_1_650 = _out_rofireMux_T_950; // @[RegisterRouter.scala:87:24] assign out_roready_1_651 = _out_rofireMux_T_950; // @[RegisterRouter.scala:87:24] assign out_roready_1_652 = _out_rofireMux_T_950; // @[RegisterRouter.scala:87:24] assign out_roready_1_653 = _out_rofireMux_T_950; // @[RegisterRouter.scala:87:24] assign out_roready_1_654 = _out_rofireMux_T_950; // @[RegisterRouter.scala:87:24] assign out_roready_1_655 = _out_rofireMux_T_950; // @[RegisterRouter.scala:87:24] assign out_roready_1_656 = _out_rofireMux_T_950; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_951 = ~_out_T_1769; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_953 = _out_rofireMux_T_260 & out_backSel_173; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_954 = _out_rofireMux_T_953 & _out_T_1719; // @[RegisterRouter.scala:87:24] assign out_roready_1_459 = _out_rofireMux_T_954; // @[RegisterRouter.scala:87:24] assign out_roready_1_460 = _out_rofireMux_T_954; // @[RegisterRouter.scala:87:24] assign out_roready_1_461 = _out_rofireMux_T_954; // @[RegisterRouter.scala:87:24] assign out_roready_1_462 = _out_rofireMux_T_954; // @[RegisterRouter.scala:87:24] assign out_roready_1_463 = _out_rofireMux_T_954; // @[RegisterRouter.scala:87:24] assign out_roready_1_464 = _out_rofireMux_T_954; // @[RegisterRouter.scala:87:24] assign out_roready_1_465 = _out_rofireMux_T_954; // @[RegisterRouter.scala:87:24] assign out_roready_1_466 = _out_rofireMux_T_954; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_955 = ~_out_T_1719; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_957 = _out_rofireMux_T_260 & out_backSel_174; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_958 = _out_rofireMux_T_957 & _out_T_1621; // @[RegisterRouter.scala:87:24] assign out_roready_1_80 = _out_rofireMux_T_958; // @[RegisterRouter.scala:87:24] assign out_roready_1_81 = _out_rofireMux_T_958; // @[RegisterRouter.scala:87:24] assign out_roready_1_82 = _out_rofireMux_T_958; // @[RegisterRouter.scala:87:24] assign out_roready_1_83 = _out_rofireMux_T_958; // @[RegisterRouter.scala:87:24] assign out_roready_1_84 = _out_rofireMux_T_958; // @[RegisterRouter.scala:87:24] assign out_roready_1_85 = _out_rofireMux_T_958; // @[RegisterRouter.scala:87:24] assign out_roready_1_86 = _out_rofireMux_T_958; // @[RegisterRouter.scala:87:24] assign out_roready_1_87 = _out_rofireMux_T_958; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_959 = ~_out_T_1621; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_961 = _out_rofireMux_T_260 & out_backSel_175; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_962 = _out_rofireMux_T_961 & _out_T_1833; // @[RegisterRouter.scala:87:24] assign out_roready_1_899 = _out_rofireMux_T_962; // @[RegisterRouter.scala:87:24] assign out_roready_1_900 = _out_rofireMux_T_962; // @[RegisterRouter.scala:87:24] assign out_roready_1_901 = _out_rofireMux_T_962; // @[RegisterRouter.scala:87:24] assign out_roready_1_902 = _out_rofireMux_T_962; // @[RegisterRouter.scala:87:24] assign out_roready_1_903 = _out_rofireMux_T_962; // @[RegisterRouter.scala:87:24] assign out_roready_1_904 = _out_rofireMux_T_962; // @[RegisterRouter.scala:87:24] assign out_roready_1_905 = _out_rofireMux_T_962; // @[RegisterRouter.scala:87:24] assign out_roready_1_906 = _out_rofireMux_T_962; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_963 = ~_out_T_1833; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_965 = _out_rofireMux_T_260 & out_backSel_176; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_966 = _out_rofireMux_T_965 & _out_T_1751; // @[RegisterRouter.scala:87:24] assign out_roready_1_577 = _out_rofireMux_T_966; // @[RegisterRouter.scala:87:24] assign out_roready_1_578 = _out_rofireMux_T_966; // @[RegisterRouter.scala:87:24] assign out_roready_1_579 = _out_rofireMux_T_966; // @[RegisterRouter.scala:87:24] assign out_roready_1_580 = _out_rofireMux_T_966; // @[RegisterRouter.scala:87:24] assign out_roready_1_581 = _out_rofireMux_T_966; // @[RegisterRouter.scala:87:24] assign out_roready_1_582 = _out_rofireMux_T_966; // @[RegisterRouter.scala:87:24] assign out_roready_1_583 = _out_rofireMux_T_966; // @[RegisterRouter.scala:87:24] assign out_roready_1_584 = _out_rofireMux_T_966; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_967 = ~_out_T_1751; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_969 = _out_rofireMux_T_260 & out_backSel_177; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_970 = _out_rofireMux_T_969 & _out_T_1827; // @[RegisterRouter.scala:87:24] assign out_roready_1_875 = _out_rofireMux_T_970; // @[RegisterRouter.scala:87:24] assign out_roready_1_876 = _out_rofireMux_T_970; // @[RegisterRouter.scala:87:24] assign out_roready_1_877 = _out_rofireMux_T_970; // @[RegisterRouter.scala:87:24] assign out_roready_1_878 = _out_rofireMux_T_970; // @[RegisterRouter.scala:87:24] assign out_roready_1_879 = _out_rofireMux_T_970; // @[RegisterRouter.scala:87:24] assign out_roready_1_880 = _out_rofireMux_T_970; // @[RegisterRouter.scala:87:24] assign out_roready_1_881 = _out_rofireMux_T_970; // @[RegisterRouter.scala:87:24] assign out_roready_1_882 = _out_rofireMux_T_970; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_971 = ~_out_T_1827; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_973 = _out_rofireMux_T_260 & out_backSel_178; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_974 = _out_rofireMux_T_973 & _out_T_1893; // @[RegisterRouter.scala:87:24] assign out_roready_1_1139 = _out_rofireMux_T_974; // @[RegisterRouter.scala:87:24] assign out_roready_1_1140 = _out_rofireMux_T_974; // @[RegisterRouter.scala:87:24] assign out_roready_1_1141 = _out_rofireMux_T_974; // @[RegisterRouter.scala:87:24] assign out_roready_1_1142 = _out_rofireMux_T_974; // @[RegisterRouter.scala:87:24] assign out_roready_1_1143 = _out_rofireMux_T_974; // @[RegisterRouter.scala:87:24] assign out_roready_1_1144 = _out_rofireMux_T_974; // @[RegisterRouter.scala:87:24] assign out_roready_1_1145 = _out_rofireMux_T_974; // @[RegisterRouter.scala:87:24] assign out_roready_1_1146 = _out_rofireMux_T_974; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_975 = ~_out_T_1893; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_977 = _out_rofireMux_T_260 & out_backSel_179; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_978 = _out_rofireMux_T_977 & _out_T_1647; // @[RegisterRouter.scala:87:24] assign out_roready_1_184 = _out_rofireMux_T_978; // @[RegisterRouter.scala:87:24] assign out_roready_1_185 = _out_rofireMux_T_978; // @[RegisterRouter.scala:87:24] assign out_roready_1_186 = _out_rofireMux_T_978; // @[RegisterRouter.scala:87:24] assign out_roready_1_187 = _out_rofireMux_T_978; // @[RegisterRouter.scala:87:24] assign out_roready_1_188 = _out_rofireMux_T_978; // @[RegisterRouter.scala:87:24] assign out_roready_1_189 = _out_rofireMux_T_978; // @[RegisterRouter.scala:87:24] assign out_roready_1_190 = _out_rofireMux_T_978; // @[RegisterRouter.scala:87:24] assign out_roready_1_191 = _out_rofireMux_T_978; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_979 = ~_out_T_1647; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_981 = _out_rofireMux_T_260 & out_backSel_180; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_982 = _out_rofireMux_T_981 & _out_T_1747; // @[RegisterRouter.scala:87:24] assign out_roready_1_561 = _out_rofireMux_T_982; // @[RegisterRouter.scala:87:24] assign out_roready_1_562 = _out_rofireMux_T_982; // @[RegisterRouter.scala:87:24] assign out_roready_1_563 = _out_rofireMux_T_982; // @[RegisterRouter.scala:87:24] assign out_roready_1_564 = _out_rofireMux_T_982; // @[RegisterRouter.scala:87:24] assign out_roready_1_565 = _out_rofireMux_T_982; // @[RegisterRouter.scala:87:24] assign out_roready_1_566 = _out_rofireMux_T_982; // @[RegisterRouter.scala:87:24] assign out_roready_1_567 = _out_rofireMux_T_982; // @[RegisterRouter.scala:87:24] assign out_roready_1_568 = _out_rofireMux_T_982; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_983 = ~_out_T_1747; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_985 = _out_rofireMux_T_260 & out_backSel_181; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_986 = _out_rofireMux_T_985 & _out_T_1763; // @[RegisterRouter.scala:87:24] assign out_roready_1_625 = _out_rofireMux_T_986; // @[RegisterRouter.scala:87:24] assign out_roready_1_626 = _out_rofireMux_T_986; // @[RegisterRouter.scala:87:24] assign out_roready_1_627 = _out_rofireMux_T_986; // @[RegisterRouter.scala:87:24] assign out_roready_1_628 = _out_rofireMux_T_986; // @[RegisterRouter.scala:87:24] assign out_roready_1_629 = _out_rofireMux_T_986; // @[RegisterRouter.scala:87:24] assign out_roready_1_630 = _out_rofireMux_T_986; // @[RegisterRouter.scala:87:24] assign out_roready_1_631 = _out_rofireMux_T_986; // @[RegisterRouter.scala:87:24] assign out_roready_1_632 = _out_rofireMux_T_986; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_987 = ~_out_T_1763; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_989 = _out_rofireMux_T_260 & out_backSel_182; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_990 = _out_rofireMux_T_989 & _out_T_1829; // @[RegisterRouter.scala:87:24] assign out_roready_1_883 = _out_rofireMux_T_990; // @[RegisterRouter.scala:87:24] assign out_roready_1_884 = _out_rofireMux_T_990; // @[RegisterRouter.scala:87:24] assign out_roready_1_885 = _out_rofireMux_T_990; // @[RegisterRouter.scala:87:24] assign out_roready_1_886 = _out_rofireMux_T_990; // @[RegisterRouter.scala:87:24] assign out_roready_1_887 = _out_rofireMux_T_990; // @[RegisterRouter.scala:87:24] assign out_roready_1_888 = _out_rofireMux_T_990; // @[RegisterRouter.scala:87:24] assign out_roready_1_889 = _out_rofireMux_T_990; // @[RegisterRouter.scala:87:24] assign out_roready_1_890 = _out_rofireMux_T_990; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_991 = ~_out_T_1829; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_993 = _out_rofireMux_T_260 & out_backSel_183; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_994 = _out_rofireMux_T_993 & _out_T_1873; // @[RegisterRouter.scala:87:24] assign out_roready_1_1059 = _out_rofireMux_T_994; // @[RegisterRouter.scala:87:24] assign out_roready_1_1060 = _out_rofireMux_T_994; // @[RegisterRouter.scala:87:24] assign out_roready_1_1061 = _out_rofireMux_T_994; // @[RegisterRouter.scala:87:24] assign out_roready_1_1062 = _out_rofireMux_T_994; // @[RegisterRouter.scala:87:24] assign out_roready_1_1063 = _out_rofireMux_T_994; // @[RegisterRouter.scala:87:24] assign out_roready_1_1064 = _out_rofireMux_T_994; // @[RegisterRouter.scala:87:24] assign out_roready_1_1065 = _out_rofireMux_T_994; // @[RegisterRouter.scala:87:24] assign out_roready_1_1066 = _out_rofireMux_T_994; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_995 = ~_out_T_1873; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_997 = _out_rofireMux_T_260 & out_backSel_184; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_998 = _out_rofireMux_T_997 & _out_T_1627; // @[RegisterRouter.scala:87:24] assign out_roready_1_104 = _out_rofireMux_T_998; // @[RegisterRouter.scala:87:24] assign out_roready_1_105 = _out_rofireMux_T_998; // @[RegisterRouter.scala:87:24] assign out_roready_1_106 = _out_rofireMux_T_998; // @[RegisterRouter.scala:87:24] assign out_roready_1_107 = _out_rofireMux_T_998; // @[RegisterRouter.scala:87:24] assign out_roready_1_108 = _out_rofireMux_T_998; // @[RegisterRouter.scala:87:24] assign out_roready_1_109 = _out_rofireMux_T_998; // @[RegisterRouter.scala:87:24] assign out_roready_1_110 = _out_rofireMux_T_998; // @[RegisterRouter.scala:87:24] assign out_roready_1_111 = _out_rofireMux_T_998; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_999 = ~_out_T_1627; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1001 = _out_rofireMux_T_260 & out_backSel_185; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1002 = _out_rofireMux_T_1001 & _out_T_1623; // @[RegisterRouter.scala:87:24] assign out_roready_1_88 = _out_rofireMux_T_1002; // @[RegisterRouter.scala:87:24] assign out_roready_1_89 = _out_rofireMux_T_1002; // @[RegisterRouter.scala:87:24] assign out_roready_1_90 = _out_rofireMux_T_1002; // @[RegisterRouter.scala:87:24] assign out_roready_1_91 = _out_rofireMux_T_1002; // @[RegisterRouter.scala:87:24] assign out_roready_1_92 = _out_rofireMux_T_1002; // @[RegisterRouter.scala:87:24] assign out_roready_1_93 = _out_rofireMux_T_1002; // @[RegisterRouter.scala:87:24] assign out_roready_1_94 = _out_rofireMux_T_1002; // @[RegisterRouter.scala:87:24] assign out_roready_1_95 = _out_rofireMux_T_1002; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1003 = ~_out_T_1623; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1005 = _out_rofireMux_T_260 & out_backSel_186; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1006 = _out_rofireMux_T_1005 & _out_T_1851; // @[RegisterRouter.scala:87:24] assign out_roready_1_971 = _out_rofireMux_T_1006; // @[RegisterRouter.scala:87:24] assign out_roready_1_972 = _out_rofireMux_T_1006; // @[RegisterRouter.scala:87:24] assign out_roready_1_973 = _out_rofireMux_T_1006; // @[RegisterRouter.scala:87:24] assign out_roready_1_974 = _out_rofireMux_T_1006; // @[RegisterRouter.scala:87:24] assign out_roready_1_975 = _out_rofireMux_T_1006; // @[RegisterRouter.scala:87:24] assign out_roready_1_976 = _out_rofireMux_T_1006; // @[RegisterRouter.scala:87:24] assign out_roready_1_977 = _out_rofireMux_T_1006; // @[RegisterRouter.scala:87:24] assign out_roready_1_978 = _out_rofireMux_T_1006; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1007 = ~_out_T_1851; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1009 = _out_rofireMux_T_260 & out_backSel_187; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1010 = _out_rofireMux_T_1009 & _out_T_1767; // @[RegisterRouter.scala:87:24] assign out_roready_1_641 = _out_rofireMux_T_1010; // @[RegisterRouter.scala:87:24] assign out_roready_1_642 = _out_rofireMux_T_1010; // @[RegisterRouter.scala:87:24] assign out_roready_1_643 = _out_rofireMux_T_1010; // @[RegisterRouter.scala:87:24] assign out_roready_1_644 = _out_rofireMux_T_1010; // @[RegisterRouter.scala:87:24] assign out_roready_1_645 = _out_rofireMux_T_1010; // @[RegisterRouter.scala:87:24] assign out_roready_1_646 = _out_rofireMux_T_1010; // @[RegisterRouter.scala:87:24] assign out_roready_1_647 = _out_rofireMux_T_1010; // @[RegisterRouter.scala:87:24] assign out_roready_1_648 = _out_rofireMux_T_1010; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1011 = ~_out_T_1767; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1013 = _out_rofireMux_T_260 & out_backSel_188; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1014 = _out_rofireMux_T_1013 & _out_T_1701; // @[RegisterRouter.scala:87:24] assign out_roready_1_394 = _out_rofireMux_T_1014; // @[RegisterRouter.scala:87:24] assign out_roready_1_395 = _out_rofireMux_T_1014; // @[RegisterRouter.scala:87:24] assign out_roready_1_396 = _out_rofireMux_T_1014; // @[RegisterRouter.scala:87:24] assign out_roready_1_397 = _out_rofireMux_T_1014; // @[RegisterRouter.scala:87:24] assign out_roready_1_398 = _out_rofireMux_T_1014; // @[RegisterRouter.scala:87:24] assign out_roready_1_399 = _out_rofireMux_T_1014; // @[RegisterRouter.scala:87:24] assign out_roready_1_400 = _out_rofireMux_T_1014; // @[RegisterRouter.scala:87:24] assign out_roready_1_401 = _out_rofireMux_T_1014; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1015 = ~_out_T_1701; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1017 = _out_rofireMux_T_260 & out_backSel_189; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1018 = _out_rofireMux_T_1017 & _out_T_1635; // @[RegisterRouter.scala:87:24] assign out_roready_1_136 = _out_rofireMux_T_1018; // @[RegisterRouter.scala:87:24] assign out_roready_1_137 = _out_rofireMux_T_1018; // @[RegisterRouter.scala:87:24] assign out_roready_1_138 = _out_rofireMux_T_1018; // @[RegisterRouter.scala:87:24] assign out_roready_1_139 = _out_rofireMux_T_1018; // @[RegisterRouter.scala:87:24] assign out_roready_1_140 = _out_rofireMux_T_1018; // @[RegisterRouter.scala:87:24] assign out_roready_1_141 = _out_rofireMux_T_1018; // @[RegisterRouter.scala:87:24] assign out_roready_1_142 = _out_rofireMux_T_1018; // @[RegisterRouter.scala:87:24] assign out_roready_1_143 = _out_rofireMux_T_1018; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1019 = ~_out_T_1635; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1021 = _out_rofireMux_T_260 & out_backSel_190; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1022 = _out_rofireMux_T_1021 & _out_T_1871; // @[RegisterRouter.scala:87:24] assign out_roready_1_1051 = _out_rofireMux_T_1022; // @[RegisterRouter.scala:87:24] assign out_roready_1_1052 = _out_rofireMux_T_1022; // @[RegisterRouter.scala:87:24] assign out_roready_1_1053 = _out_rofireMux_T_1022; // @[RegisterRouter.scala:87:24] assign out_roready_1_1054 = _out_rofireMux_T_1022; // @[RegisterRouter.scala:87:24] assign out_roready_1_1055 = _out_rofireMux_T_1022; // @[RegisterRouter.scala:87:24] assign out_roready_1_1056 = _out_rofireMux_T_1022; // @[RegisterRouter.scala:87:24] assign out_roready_1_1057 = _out_rofireMux_T_1022; // @[RegisterRouter.scala:87:24] assign out_roready_1_1058 = _out_rofireMux_T_1022; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1023 = ~_out_T_1871; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1025 = _out_rofireMux_T_260 & out_backSel_191; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1026 = _out_rofireMux_T_1025 & _out_T_1753; // @[RegisterRouter.scala:87:24] assign out_roready_1_585 = _out_rofireMux_T_1026; // @[RegisterRouter.scala:87:24] assign out_roready_1_586 = _out_rofireMux_T_1026; // @[RegisterRouter.scala:87:24] assign out_roready_1_587 = _out_rofireMux_T_1026; // @[RegisterRouter.scala:87:24] assign out_roready_1_588 = _out_rofireMux_T_1026; // @[RegisterRouter.scala:87:24] assign out_roready_1_589 = _out_rofireMux_T_1026; // @[RegisterRouter.scala:87:24] assign out_roready_1_590 = _out_rofireMux_T_1026; // @[RegisterRouter.scala:87:24] assign out_roready_1_591 = _out_rofireMux_T_1026; // @[RegisterRouter.scala:87:24] assign out_roready_1_592 = _out_rofireMux_T_1026; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1027 = ~_out_T_1753; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1029 = _out_rofireMux_T_260 & out_backSel_192; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1030 = _out_rofireMux_T_1029 & _out_T_1683; // @[RegisterRouter.scala:87:24] assign out_roready_1_328 = _out_rofireMux_T_1030; // @[RegisterRouter.scala:87:24] assign out_roready_1_329 = _out_rofireMux_T_1030; // @[RegisterRouter.scala:87:24] assign out_roready_1_330 = _out_rofireMux_T_1030; // @[RegisterRouter.scala:87:24] assign out_roready_1_331 = _out_rofireMux_T_1030; // @[RegisterRouter.scala:87:24] assign out_roready_1_332 = _out_rofireMux_T_1030; // @[RegisterRouter.scala:87:24] assign out_roready_1_333 = _out_rofireMux_T_1030; // @[RegisterRouter.scala:87:24] assign out_roready_1_334 = _out_rofireMux_T_1030; // @[RegisterRouter.scala:87:24] assign out_roready_1_335 = _out_rofireMux_T_1030; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1031 = ~_out_T_1683; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1033 = _out_rofireMux_T_260 & out_backSel_193; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1034 = _out_rofireMux_T_1033 & _out_T_1709; // @[RegisterRouter.scala:87:24] assign out_roready_1_426 = _out_rofireMux_T_1034; // @[RegisterRouter.scala:87:24] assign out_roready_1_427 = _out_rofireMux_T_1034; // @[RegisterRouter.scala:87:24] assign out_roready_1_428 = _out_rofireMux_T_1034; // @[RegisterRouter.scala:87:24] assign out_roready_1_429 = _out_rofireMux_T_1034; // @[RegisterRouter.scala:87:24] assign out_roready_1_430 = _out_rofireMux_T_1034; // @[RegisterRouter.scala:87:24] assign out_roready_1_431 = _out_rofireMux_T_1034; // @[RegisterRouter.scala:87:24] assign out_roready_1_432 = _out_rofireMux_T_1034; // @[RegisterRouter.scala:87:24] assign out_roready_1_433 = _out_rofireMux_T_1034; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1035 = ~_out_T_1709; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1037 = _out_rofireMux_T_260 & out_backSel_194; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1038 = _out_rofireMux_T_1037 & _out_T_1817; // @[RegisterRouter.scala:87:24] assign out_roready_1_835 = _out_rofireMux_T_1038; // @[RegisterRouter.scala:87:24] assign out_roready_1_836 = _out_rofireMux_T_1038; // @[RegisterRouter.scala:87:24] assign out_roready_1_837 = _out_rofireMux_T_1038; // @[RegisterRouter.scala:87:24] assign out_roready_1_838 = _out_rofireMux_T_1038; // @[RegisterRouter.scala:87:24] assign out_roready_1_839 = _out_rofireMux_T_1038; // @[RegisterRouter.scala:87:24] assign out_roready_1_840 = _out_rofireMux_T_1038; // @[RegisterRouter.scala:87:24] assign out_roready_1_841 = _out_rofireMux_T_1038; // @[RegisterRouter.scala:87:24] assign out_roready_1_842 = _out_rofireMux_T_1038; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1039 = ~_out_T_1817; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1041 = _out_rofireMux_T_260 & out_backSel_195; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1042 = _out_rofireMux_T_1041 & _out_T_1885; // @[RegisterRouter.scala:87:24] assign out_roready_1_1107 = _out_rofireMux_T_1042; // @[RegisterRouter.scala:87:24] assign out_roready_1_1108 = _out_rofireMux_T_1042; // @[RegisterRouter.scala:87:24] assign out_roready_1_1109 = _out_rofireMux_T_1042; // @[RegisterRouter.scala:87:24] assign out_roready_1_1110 = _out_rofireMux_T_1042; // @[RegisterRouter.scala:87:24] assign out_roready_1_1111 = _out_rofireMux_T_1042; // @[RegisterRouter.scala:87:24] assign out_roready_1_1112 = _out_rofireMux_T_1042; // @[RegisterRouter.scala:87:24] assign out_roready_1_1113 = _out_rofireMux_T_1042; // @[RegisterRouter.scala:87:24] assign out_roready_1_1114 = _out_rofireMux_T_1042; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1043 = ~_out_T_1885; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1045 = _out_rofireMux_T_260 & out_backSel_196; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1046 = _out_rofireMux_T_1045 & _out_T_1631; // @[RegisterRouter.scala:87:24] assign out_roready_1_120 = _out_rofireMux_T_1046; // @[RegisterRouter.scala:87:24] assign out_roready_1_121 = _out_rofireMux_T_1046; // @[RegisterRouter.scala:87:24] assign out_roready_1_122 = _out_rofireMux_T_1046; // @[RegisterRouter.scala:87:24] assign out_roready_1_123 = _out_rofireMux_T_1046; // @[RegisterRouter.scala:87:24] assign out_roready_1_124 = _out_rofireMux_T_1046; // @[RegisterRouter.scala:87:24] assign out_roready_1_125 = _out_rofireMux_T_1046; // @[RegisterRouter.scala:87:24] assign out_roready_1_126 = _out_rofireMux_T_1046; // @[RegisterRouter.scala:87:24] assign out_roready_1_127 = _out_rofireMux_T_1046; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1047 = ~_out_T_1631; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1049 = _out_rofireMux_T_260 & out_backSel_197; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1050 = _out_rofireMux_T_1049 & _out_T_1695; // @[RegisterRouter.scala:87:24] assign out_roready_1_370 = _out_rofireMux_T_1050; // @[RegisterRouter.scala:87:24] assign out_roready_1_371 = _out_rofireMux_T_1050; // @[RegisterRouter.scala:87:24] assign out_roready_1_372 = _out_rofireMux_T_1050; // @[RegisterRouter.scala:87:24] assign out_roready_1_373 = _out_rofireMux_T_1050; // @[RegisterRouter.scala:87:24] assign out_roready_1_374 = _out_rofireMux_T_1050; // @[RegisterRouter.scala:87:24] assign out_roready_1_375 = _out_rofireMux_T_1050; // @[RegisterRouter.scala:87:24] assign out_roready_1_376 = _out_rofireMux_T_1050; // @[RegisterRouter.scala:87:24] assign out_roready_1_377 = _out_rofireMux_T_1050; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1051 = ~_out_T_1695; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1053 = _out_rofireMux_T_260 & out_backSel_198; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1054 = _out_rofireMux_T_1053 & _out_T_1789; // @[RegisterRouter.scala:87:24] assign out_roready_1_723 = _out_rofireMux_T_1054; // @[RegisterRouter.scala:87:24] assign out_roready_1_724 = _out_rofireMux_T_1054; // @[RegisterRouter.scala:87:24] assign out_roready_1_725 = _out_rofireMux_T_1054; // @[RegisterRouter.scala:87:24] assign out_roready_1_726 = _out_rofireMux_T_1054; // @[RegisterRouter.scala:87:24] assign out_roready_1_727 = _out_rofireMux_T_1054; // @[RegisterRouter.scala:87:24] assign out_roready_1_728 = _out_rofireMux_T_1054; // @[RegisterRouter.scala:87:24] assign out_roready_1_729 = _out_rofireMux_T_1054; // @[RegisterRouter.scala:87:24] assign out_roready_1_730 = _out_rofireMux_T_1054; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1055 = ~_out_T_1789; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1057 = _out_rofireMux_T_260 & out_backSel_199; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1058 = _out_rofireMux_T_1057 & _out_T_1825; // @[RegisterRouter.scala:87:24] assign out_roready_1_867 = _out_rofireMux_T_1058; // @[RegisterRouter.scala:87:24] assign out_roready_1_868 = _out_rofireMux_T_1058; // @[RegisterRouter.scala:87:24] assign out_roready_1_869 = _out_rofireMux_T_1058; // @[RegisterRouter.scala:87:24] assign out_roready_1_870 = _out_rofireMux_T_1058; // @[RegisterRouter.scala:87:24] assign out_roready_1_871 = _out_rofireMux_T_1058; // @[RegisterRouter.scala:87:24] assign out_roready_1_872 = _out_rofireMux_T_1058; // @[RegisterRouter.scala:87:24] assign out_roready_1_873 = _out_rofireMux_T_1058; // @[RegisterRouter.scala:87:24] assign out_roready_1_874 = _out_rofireMux_T_1058; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1059 = ~_out_T_1825; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1061 = _out_rofireMux_T_260 & out_backSel_200; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1062 = _out_rofireMux_T_1061 & _out_T_1897; // @[RegisterRouter.scala:87:24] assign out_roready_1_1155 = _out_rofireMux_T_1062; // @[RegisterRouter.scala:87:24] assign out_roready_1_1156 = _out_rofireMux_T_1062; // @[RegisterRouter.scala:87:24] assign out_roready_1_1157 = _out_rofireMux_T_1062; // @[RegisterRouter.scala:87:24] assign out_roready_1_1158 = _out_rofireMux_T_1062; // @[RegisterRouter.scala:87:24] assign out_roready_1_1159 = _out_rofireMux_T_1062; // @[RegisterRouter.scala:87:24] assign out_roready_1_1160 = _out_rofireMux_T_1062; // @[RegisterRouter.scala:87:24] assign out_roready_1_1161 = _out_rofireMux_T_1062; // @[RegisterRouter.scala:87:24] assign out_roready_1_1162 = _out_rofireMux_T_1062; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1063 = ~_out_T_1897; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1065 = _out_rofireMux_T_260 & out_backSel_201; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1066 = _out_rofireMux_T_1065 & _out_T_1675; // @[RegisterRouter.scala:87:24] assign out_roready_1_296 = _out_rofireMux_T_1066; // @[RegisterRouter.scala:87:24] assign out_roready_1_297 = _out_rofireMux_T_1066; // @[RegisterRouter.scala:87:24] assign out_roready_1_298 = _out_rofireMux_T_1066; // @[RegisterRouter.scala:87:24] assign out_roready_1_299 = _out_rofireMux_T_1066; // @[RegisterRouter.scala:87:24] assign out_roready_1_300 = _out_rofireMux_T_1066; // @[RegisterRouter.scala:87:24] assign out_roready_1_301 = _out_rofireMux_T_1066; // @[RegisterRouter.scala:87:24] assign out_roready_1_302 = _out_rofireMux_T_1066; // @[RegisterRouter.scala:87:24] assign out_roready_1_303 = _out_rofireMux_T_1066; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1067 = ~_out_T_1675; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1069 = _out_rofireMux_T_260 & out_backSel_202; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1070 = _out_rofireMux_T_1069 & _out_T_1615; // @[RegisterRouter.scala:87:24] assign out_roready_1_56 = _out_rofireMux_T_1070; // @[RegisterRouter.scala:87:24] assign out_roready_1_57 = _out_rofireMux_T_1070; // @[RegisterRouter.scala:87:24] assign out_roready_1_58 = _out_rofireMux_T_1070; // @[RegisterRouter.scala:87:24] assign out_roready_1_59 = _out_rofireMux_T_1070; // @[RegisterRouter.scala:87:24] assign out_roready_1_60 = _out_rofireMux_T_1070; // @[RegisterRouter.scala:87:24] assign out_roready_1_61 = _out_rofireMux_T_1070; // @[RegisterRouter.scala:87:24] assign out_roready_1_62 = _out_rofireMux_T_1070; // @[RegisterRouter.scala:87:24] assign out_roready_1_63 = _out_rofireMux_T_1070; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1071 = ~_out_T_1615; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1073 = _out_rofireMux_T_260 & out_backSel_203; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1074 = _out_rofireMux_T_1073 & _out_T_1837; // @[RegisterRouter.scala:87:24] assign out_roready_1_915 = _out_rofireMux_T_1074; // @[RegisterRouter.scala:87:24] assign out_roready_1_916 = _out_rofireMux_T_1074; // @[RegisterRouter.scala:87:24] assign out_roready_1_917 = _out_rofireMux_T_1074; // @[RegisterRouter.scala:87:24] assign out_roready_1_918 = _out_rofireMux_T_1074; // @[RegisterRouter.scala:87:24] assign out_roready_1_919 = _out_rofireMux_T_1074; // @[RegisterRouter.scala:87:24] assign out_roready_1_920 = _out_rofireMux_T_1074; // @[RegisterRouter.scala:87:24] assign out_roready_1_921 = _out_rofireMux_T_1074; // @[RegisterRouter.scala:87:24] assign out_roready_1_922 = _out_rofireMux_T_1074; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1075 = ~_out_T_1837; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1077 = _out_rofireMux_T_260 & out_backSel_204; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1078 = _out_rofireMux_T_1077 & _out_T_1755; // @[RegisterRouter.scala:87:24] assign out_roready_1_593 = _out_rofireMux_T_1078; // @[RegisterRouter.scala:87:24] assign out_roready_1_594 = _out_rofireMux_T_1078; // @[RegisterRouter.scala:87:24] assign out_roready_1_595 = _out_rofireMux_T_1078; // @[RegisterRouter.scala:87:24] assign out_roready_1_596 = _out_rofireMux_T_1078; // @[RegisterRouter.scala:87:24] assign out_roready_1_597 = _out_rofireMux_T_1078; // @[RegisterRouter.scala:87:24] assign out_roready_1_598 = _out_rofireMux_T_1078; // @[RegisterRouter.scala:87:24] assign out_roready_1_599 = _out_rofireMux_T_1078; // @[RegisterRouter.scala:87:24] assign out_roready_1_600 = _out_rofireMux_T_1078; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1079 = ~_out_T_1755; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1081 = _out_rofireMux_T_260 & out_backSel_205; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1082 = _out_rofireMux_T_1081 & _out_T_1727; // @[RegisterRouter.scala:87:24] assign out_roready_1_487 = _out_rofireMux_T_1082; // @[RegisterRouter.scala:87:24] assign out_roready_1_488 = _out_rofireMux_T_1082; // @[RegisterRouter.scala:87:24] assign out_roready_1_489 = _out_rofireMux_T_1082; // @[RegisterRouter.scala:87:24] assign out_roready_1_490 = _out_rofireMux_T_1082; // @[RegisterRouter.scala:87:24] assign out_roready_1_491 = _out_rofireMux_T_1082; // @[RegisterRouter.scala:87:24] assign out_roready_1_492 = _out_rofireMux_T_1082; // @[RegisterRouter.scala:87:24] assign out_roready_1_493 = _out_rofireMux_T_1082; // @[RegisterRouter.scala:87:24] assign out_roready_1_494 = _out_rofireMux_T_1082; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1083 = ~_out_T_1727; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1085 = _out_rofireMux_T_260 & out_backSel_206; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1086 = _out_rofireMux_T_1085 & _out_T_1669; // @[RegisterRouter.scala:87:24] assign out_roready_1_272 = _out_rofireMux_T_1086; // @[RegisterRouter.scala:87:24] assign out_roready_1_273 = _out_rofireMux_T_1086; // @[RegisterRouter.scala:87:24] assign out_roready_1_274 = _out_rofireMux_T_1086; // @[RegisterRouter.scala:87:24] assign out_roready_1_275 = _out_rofireMux_T_1086; // @[RegisterRouter.scala:87:24] assign out_roready_1_276 = _out_rofireMux_T_1086; // @[RegisterRouter.scala:87:24] assign out_roready_1_277 = _out_rofireMux_T_1086; // @[RegisterRouter.scala:87:24] assign out_roready_1_278 = _out_rofireMux_T_1086; // @[RegisterRouter.scala:87:24] assign out_roready_1_279 = _out_rofireMux_T_1086; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1087 = ~_out_T_1669; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1089 = _out_rofireMux_T_260 & out_backSel_207; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1090 = _out_rofireMux_T_1089 & _out_T_1859; // @[RegisterRouter.scala:87:24] assign out_roready_1_1003 = _out_rofireMux_T_1090; // @[RegisterRouter.scala:87:24] assign out_roready_1_1004 = _out_rofireMux_T_1090; // @[RegisterRouter.scala:87:24] assign out_roready_1_1005 = _out_rofireMux_T_1090; // @[RegisterRouter.scala:87:24] assign out_roready_1_1006 = _out_rofireMux_T_1090; // @[RegisterRouter.scala:87:24] assign out_roready_1_1007 = _out_rofireMux_T_1090; // @[RegisterRouter.scala:87:24] assign out_roready_1_1008 = _out_rofireMux_T_1090; // @[RegisterRouter.scala:87:24] assign out_roready_1_1009 = _out_rofireMux_T_1090; // @[RegisterRouter.scala:87:24] assign out_roready_1_1010 = _out_rofireMux_T_1090; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1091 = ~_out_T_1859; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1093 = _out_rofireMux_T_260 & out_backSel_208; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1094 = _out_rofireMux_T_1093 & _out_T_1779; // @[RegisterRouter.scala:87:24] assign out_roready_1_689 = _out_rofireMux_T_1094; // @[RegisterRouter.scala:87:24] assign out_roready_1_690 = _out_rofireMux_T_1094; // @[RegisterRouter.scala:87:24] assign out_roready_1_691 = _out_rofireMux_T_1094; // @[RegisterRouter.scala:87:24] assign out_roready_1_692 = _out_rofireMux_T_1094; // @[RegisterRouter.scala:87:24] assign out_roready_1_693 = _out_rofireMux_T_1094; // @[RegisterRouter.scala:87:24] assign out_roready_1_694 = _out_rofireMux_T_1094; // @[RegisterRouter.scala:87:24] assign out_roready_1_695 = _out_rofireMux_T_1094; // @[RegisterRouter.scala:87:24] assign out_roready_1_696 = _out_rofireMux_T_1094; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1095 = ~_out_T_1779; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1097 = _out_rofireMux_T_260 & out_backSel_209; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1098 = _out_rofireMux_T_1097 & _out_T_1813; // @[RegisterRouter.scala:87:24] assign out_roready_1_819 = _out_rofireMux_T_1098; // @[RegisterRouter.scala:87:24] assign out_roready_1_820 = _out_rofireMux_T_1098; // @[RegisterRouter.scala:87:24] assign out_roready_1_821 = _out_rofireMux_T_1098; // @[RegisterRouter.scala:87:24] assign out_roready_1_822 = _out_rofireMux_T_1098; // @[RegisterRouter.scala:87:24] assign out_roready_1_823 = _out_rofireMux_T_1098; // @[RegisterRouter.scala:87:24] assign out_roready_1_824 = _out_rofireMux_T_1098; // @[RegisterRouter.scala:87:24] assign out_roready_1_825 = _out_rofireMux_T_1098; // @[RegisterRouter.scala:87:24] assign out_roready_1_826 = _out_rofireMux_T_1098; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1099 = ~_out_T_1813; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1101 = _out_rofireMux_T_260 & out_backSel_210; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1102 = _out_rofireMux_T_1101 & _out_T_1879; // @[RegisterRouter.scala:87:24] assign out_roready_1_1083 = _out_rofireMux_T_1102; // @[RegisterRouter.scala:87:24] assign out_roready_1_1084 = _out_rofireMux_T_1102; // @[RegisterRouter.scala:87:24] assign out_roready_1_1085 = _out_rofireMux_T_1102; // @[RegisterRouter.scala:87:24] assign out_roready_1_1086 = _out_rofireMux_T_1102; // @[RegisterRouter.scala:87:24] assign out_roready_1_1087 = _out_rofireMux_T_1102; // @[RegisterRouter.scala:87:24] assign out_roready_1_1088 = _out_rofireMux_T_1102; // @[RegisterRouter.scala:87:24] assign out_roready_1_1089 = _out_rofireMux_T_1102; // @[RegisterRouter.scala:87:24] assign out_roready_1_1090 = _out_rofireMux_T_1102; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1103 = ~_out_T_1879; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1105 = _out_rofireMux_T_260 & out_backSel_211; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1106 = _out_rofireMux_T_1105 & _out_T_1653; // @[RegisterRouter.scala:87:24] assign out_roready_1_208 = _out_rofireMux_T_1106; // @[RegisterRouter.scala:87:24] assign out_roready_1_209 = _out_rofireMux_T_1106; // @[RegisterRouter.scala:87:24] assign out_roready_1_210 = _out_rofireMux_T_1106; // @[RegisterRouter.scala:87:24] assign out_roready_1_211 = _out_rofireMux_T_1106; // @[RegisterRouter.scala:87:24] assign out_roready_1_212 = _out_rofireMux_T_1106; // @[RegisterRouter.scala:87:24] assign out_roready_1_213 = _out_rofireMux_T_1106; // @[RegisterRouter.scala:87:24] assign out_roready_1_214 = _out_rofireMux_T_1106; // @[RegisterRouter.scala:87:24] assign out_roready_1_215 = _out_rofireMux_T_1106; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1107 = ~_out_T_1653; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1109 = _out_rofireMux_T_260 & out_backSel_212; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1110 = _out_rofireMux_T_1109 & _out_T_1711; // @[RegisterRouter.scala:87:24] assign out_roready_1_434 = _out_rofireMux_T_1110; // @[RegisterRouter.scala:87:24] assign out_roready_1_435 = _out_rofireMux_T_1110; // @[RegisterRouter.scala:87:24] assign out_roready_1_436 = _out_rofireMux_T_1110; // @[RegisterRouter.scala:87:24] assign out_roready_1_437 = _out_rofireMux_T_1110; // @[RegisterRouter.scala:87:24] assign out_roready_1_438 = _out_rofireMux_T_1110; // @[RegisterRouter.scala:87:24] assign out_roready_1_439 = _out_rofireMux_T_1110; // @[RegisterRouter.scala:87:24] assign out_roready_1_440 = _out_rofireMux_T_1110; // @[RegisterRouter.scala:87:24] assign out_roready_1_441 = _out_rofireMux_T_1110; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1111 = ~_out_T_1711; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1113 = _out_rofireMux_T_260 & out_backSel_213; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1114 = _out_rofireMux_T_1113 & _out_T_1785; // @[RegisterRouter.scala:87:24] assign out_roready_1_707 = _out_rofireMux_T_1114; // @[RegisterRouter.scala:87:24] assign out_roready_1_708 = _out_rofireMux_T_1114; // @[RegisterRouter.scala:87:24] assign out_roready_1_709 = _out_rofireMux_T_1114; // @[RegisterRouter.scala:87:24] assign out_roready_1_710 = _out_rofireMux_T_1114; // @[RegisterRouter.scala:87:24] assign out_roready_1_711 = _out_rofireMux_T_1114; // @[RegisterRouter.scala:87:24] assign out_roready_1_712 = _out_rofireMux_T_1114; // @[RegisterRouter.scala:87:24] assign out_roready_1_713 = _out_rofireMux_T_1114; // @[RegisterRouter.scala:87:24] assign out_roready_1_714 = _out_rofireMux_T_1114; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1115 = ~_out_T_1785; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1117 = _out_rofireMux_T_260 & out_backSel_214; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1118 = _out_rofireMux_T_1117 & _out_T_1861; // @[RegisterRouter.scala:87:24] assign out_roready_1_1011 = _out_rofireMux_T_1118; // @[RegisterRouter.scala:87:24] assign out_roready_1_1012 = _out_rofireMux_T_1118; // @[RegisterRouter.scala:87:24] assign out_roready_1_1013 = _out_rofireMux_T_1118; // @[RegisterRouter.scala:87:24] assign out_roready_1_1014 = _out_rofireMux_T_1118; // @[RegisterRouter.scala:87:24] assign out_roready_1_1015 = _out_rofireMux_T_1118; // @[RegisterRouter.scala:87:24] assign out_roready_1_1016 = _out_rofireMux_T_1118; // @[RegisterRouter.scala:87:24] assign out_roready_1_1017 = _out_rofireMux_T_1118; // @[RegisterRouter.scala:87:24] assign out_roready_1_1018 = _out_rofireMux_T_1118; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1119 = ~_out_T_1861; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1121 = _out_rofireMux_T_260 & out_backSel_215; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1122 = _out_rofireMux_T_1121 & _out_T_1901; // @[RegisterRouter.scala:87:24] assign out_roready_1_1171 = _out_rofireMux_T_1122; // @[RegisterRouter.scala:87:24] assign out_roready_1_1172 = _out_rofireMux_T_1122; // @[RegisterRouter.scala:87:24] assign out_roready_1_1173 = _out_rofireMux_T_1122; // @[RegisterRouter.scala:87:24] assign out_roready_1_1174 = _out_rofireMux_T_1122; // @[RegisterRouter.scala:87:24] assign out_roready_1_1175 = _out_rofireMux_T_1122; // @[RegisterRouter.scala:87:24] assign out_roready_1_1176 = _out_rofireMux_T_1122; // @[RegisterRouter.scala:87:24] assign out_roready_1_1177 = _out_rofireMux_T_1122; // @[RegisterRouter.scala:87:24] assign out_roready_1_1178 = _out_rofireMux_T_1122; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1123 = ~_out_T_1901; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1125 = _out_rofireMux_T_260 & out_backSel_216; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1126 = _out_rofireMux_T_1125 & _out_T_1643; // @[RegisterRouter.scala:87:24] assign out_roready_1_168 = _out_rofireMux_T_1126; // @[RegisterRouter.scala:87:24] assign out_roready_1_169 = _out_rofireMux_T_1126; // @[RegisterRouter.scala:87:24] assign out_roready_1_170 = _out_rofireMux_T_1126; // @[RegisterRouter.scala:87:24] assign out_roready_1_171 = _out_rofireMux_T_1126; // @[RegisterRouter.scala:87:24] assign out_roready_1_172 = _out_rofireMux_T_1126; // @[RegisterRouter.scala:87:24] assign out_roready_1_173 = _out_rofireMux_T_1126; // @[RegisterRouter.scala:87:24] assign out_roready_1_174 = _out_rofireMux_T_1126; // @[RegisterRouter.scala:87:24] assign out_roready_1_175 = _out_rofireMux_T_1126; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1127 = ~_out_T_1643; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1129 = _out_rofireMux_T_260 & out_backSel_217; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1130 = _out_rofireMux_T_1129 & _out_T_1611; // @[RegisterRouter.scala:87:24] assign out_roready_1_40 = _out_rofireMux_T_1130; // @[RegisterRouter.scala:87:24] assign out_roready_1_41 = _out_rofireMux_T_1130; // @[RegisterRouter.scala:87:24] assign out_roready_1_42 = _out_rofireMux_T_1130; // @[RegisterRouter.scala:87:24] assign out_roready_1_43 = _out_rofireMux_T_1130; // @[RegisterRouter.scala:87:24] assign out_roready_1_44 = _out_rofireMux_T_1130; // @[RegisterRouter.scala:87:24] assign out_roready_1_45 = _out_rofireMux_T_1130; // @[RegisterRouter.scala:87:24] assign out_roready_1_46 = _out_rofireMux_T_1130; // @[RegisterRouter.scala:87:24] assign out_roready_1_47 = _out_rofireMux_T_1130; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1131 = ~_out_T_1611; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1133 = _out_rofireMux_T_260 & out_backSel_218; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1134 = _out_rofireMux_T_1133 & _out_T_1839; // @[RegisterRouter.scala:87:24] assign out_roready_1_923 = _out_rofireMux_T_1134; // @[RegisterRouter.scala:87:24] assign out_roready_1_924 = _out_rofireMux_T_1134; // @[RegisterRouter.scala:87:24] assign out_roready_1_925 = _out_rofireMux_T_1134; // @[RegisterRouter.scala:87:24] assign out_roready_1_926 = _out_rofireMux_T_1134; // @[RegisterRouter.scala:87:24] assign out_roready_1_927 = _out_rofireMux_T_1134; // @[RegisterRouter.scala:87:24] assign out_roready_1_928 = _out_rofireMux_T_1134; // @[RegisterRouter.scala:87:24] assign out_roready_1_929 = _out_rofireMux_T_1134; // @[RegisterRouter.scala:87:24] assign out_roready_1_930 = _out_rofireMux_T_1134; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1135 = ~_out_T_1839; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1137 = _out_rofireMux_T_260 & out_backSel_219; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1138 = _out_rofireMux_T_1137 & _out_T_1773; // @[RegisterRouter.scala:87:24] assign out_roready_1_665 = _out_rofireMux_T_1138; // @[RegisterRouter.scala:87:24] assign out_roready_1_666 = _out_rofireMux_T_1138; // @[RegisterRouter.scala:87:24] assign out_roready_1_667 = _out_rofireMux_T_1138; // @[RegisterRouter.scala:87:24] assign out_roready_1_668 = _out_rofireMux_T_1138; // @[RegisterRouter.scala:87:24] assign out_roready_1_669 = _out_rofireMux_T_1138; // @[RegisterRouter.scala:87:24] assign out_roready_1_670 = _out_rofireMux_T_1138; // @[RegisterRouter.scala:87:24] assign out_roready_1_671 = _out_rofireMux_T_1138; // @[RegisterRouter.scala:87:24] assign out_roready_1_672 = _out_rofireMux_T_1138; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1139 = ~_out_T_1773; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1141 = _out_rofireMux_T_260 & out_backSel_220; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1142 = _out_rofireMux_T_1141 & _out_T_1677; // @[RegisterRouter.scala:87:24] assign out_roready_1_304 = _out_rofireMux_T_1142; // @[RegisterRouter.scala:87:24] assign out_roready_1_305 = _out_rofireMux_T_1142; // @[RegisterRouter.scala:87:24] assign out_roready_1_306 = _out_rofireMux_T_1142; // @[RegisterRouter.scala:87:24] assign out_roready_1_307 = _out_rofireMux_T_1142; // @[RegisterRouter.scala:87:24] assign out_roready_1_308 = _out_rofireMux_T_1142; // @[RegisterRouter.scala:87:24] assign out_roready_1_309 = _out_rofireMux_T_1142; // @[RegisterRouter.scala:87:24] assign out_roready_1_310 = _out_rofireMux_T_1142; // @[RegisterRouter.scala:87:24] assign out_roready_1_311 = _out_rofireMux_T_1142; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1143 = ~_out_T_1677; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1145 = _out_rofireMux_T_260 & out_backSel_221; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1146 = _out_rofireMux_T_1145 & _out_T_1659; // @[RegisterRouter.scala:87:24] assign out_roready_1_232 = _out_rofireMux_T_1146; // @[RegisterRouter.scala:87:24] assign out_roready_1_233 = _out_rofireMux_T_1146; // @[RegisterRouter.scala:87:24] assign out_roready_1_234 = _out_rofireMux_T_1146; // @[RegisterRouter.scala:87:24] assign out_roready_1_235 = _out_rofireMux_T_1146; // @[RegisterRouter.scala:87:24] assign out_roready_1_236 = _out_rofireMux_T_1146; // @[RegisterRouter.scala:87:24] assign out_roready_1_237 = _out_rofireMux_T_1146; // @[RegisterRouter.scala:87:24] assign out_roready_1_238 = _out_rofireMux_T_1146; // @[RegisterRouter.scala:87:24] assign out_roready_1_239 = _out_rofireMux_T_1146; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1147 = ~_out_T_1659; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1149 = _out_rofireMux_T_260 & out_backSel_222; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1150 = _out_rofireMux_T_1149 & _out_T_1903; // @[RegisterRouter.scala:87:24] assign out_roready_1_1179 = _out_rofireMux_T_1150; // @[RegisterRouter.scala:87:24] assign out_roready_1_1180 = _out_rofireMux_T_1150; // @[RegisterRouter.scala:87:24] assign out_roready_1_1181 = _out_rofireMux_T_1150; // @[RegisterRouter.scala:87:24] assign out_roready_1_1182 = _out_rofireMux_T_1150; // @[RegisterRouter.scala:87:24] assign out_roready_1_1183 = _out_rofireMux_T_1150; // @[RegisterRouter.scala:87:24] assign out_roready_1_1184 = _out_rofireMux_T_1150; // @[RegisterRouter.scala:87:24] assign out_roready_1_1185 = _out_rofireMux_T_1150; // @[RegisterRouter.scala:87:24] assign out_roready_1_1186 = _out_rofireMux_T_1150; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1151 = ~_out_T_1903; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1153 = _out_rofireMux_T_260 & out_backSel_223; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1154 = _out_rofireMux_T_1153 & _out_T_1799; // @[RegisterRouter.scala:87:24] assign out_roready_1_763 = _out_rofireMux_T_1154; // @[RegisterRouter.scala:87:24] assign out_roready_1_764 = _out_rofireMux_T_1154; // @[RegisterRouter.scala:87:24] assign out_roready_1_765 = _out_rofireMux_T_1154; // @[RegisterRouter.scala:87:24] assign out_roready_1_766 = _out_rofireMux_T_1154; // @[RegisterRouter.scala:87:24] assign out_roready_1_767 = _out_rofireMux_T_1154; // @[RegisterRouter.scala:87:24] assign out_roready_1_768 = _out_rofireMux_T_1154; // @[RegisterRouter.scala:87:24] assign out_roready_1_769 = _out_rofireMux_T_1154; // @[RegisterRouter.scala:87:24] assign out_roready_1_770 = _out_rofireMux_T_1154; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1155 = ~_out_T_1799; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1157 = _out_rofireMux_T_260 & out_backSel_224; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1158 = _out_rofireMux_T_1157 & _out_T_1697; // @[RegisterRouter.scala:87:24] assign out_roready_1_378 = _out_rofireMux_T_1158; // @[RegisterRouter.scala:87:24] assign out_roready_1_379 = _out_rofireMux_T_1158; // @[RegisterRouter.scala:87:24] assign out_roready_1_380 = _out_rofireMux_T_1158; // @[RegisterRouter.scala:87:24] assign out_roready_1_381 = _out_rofireMux_T_1158; // @[RegisterRouter.scala:87:24] assign out_roready_1_382 = _out_rofireMux_T_1158; // @[RegisterRouter.scala:87:24] assign out_roready_1_383 = _out_rofireMux_T_1158; // @[RegisterRouter.scala:87:24] assign out_roready_1_384 = _out_rofireMux_T_1158; // @[RegisterRouter.scala:87:24] assign out_roready_1_385 = _out_rofireMux_T_1158; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1159 = ~_out_T_1697; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1161 = _out_rofireMux_T_260 & out_backSel_225; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1162 = _out_rofireMux_T_1161 & _out_T_1707; // @[RegisterRouter.scala:87:24] assign out_roready_1_418 = _out_rofireMux_T_1162; // @[RegisterRouter.scala:87:24] assign out_roready_1_419 = _out_rofireMux_T_1162; // @[RegisterRouter.scala:87:24] assign out_roready_1_420 = _out_rofireMux_T_1162; // @[RegisterRouter.scala:87:24] assign out_roready_1_421 = _out_rofireMux_T_1162; // @[RegisterRouter.scala:87:24] assign out_roready_1_422 = _out_rofireMux_T_1162; // @[RegisterRouter.scala:87:24] assign out_roready_1_423 = _out_rofireMux_T_1162; // @[RegisterRouter.scala:87:24] assign out_roready_1_424 = _out_rofireMux_T_1162; // @[RegisterRouter.scala:87:24] assign out_roready_1_425 = _out_rofireMux_T_1162; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1163 = ~_out_T_1707; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1165 = _out_rofireMux_T_260 & out_backSel_226; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1166 = _out_rofireMux_T_1165 & _out_T_1803; // @[RegisterRouter.scala:87:24] assign out_roready_1_779 = _out_rofireMux_T_1166; // @[RegisterRouter.scala:87:24] assign out_roready_1_780 = _out_rofireMux_T_1166; // @[RegisterRouter.scala:87:24] assign out_roready_1_781 = _out_rofireMux_T_1166; // @[RegisterRouter.scala:87:24] assign out_roready_1_782 = _out_rofireMux_T_1166; // @[RegisterRouter.scala:87:24] assign out_roready_1_783 = _out_rofireMux_T_1166; // @[RegisterRouter.scala:87:24] assign out_roready_1_784 = _out_rofireMux_T_1166; // @[RegisterRouter.scala:87:24] assign out_roready_1_785 = _out_rofireMux_T_1166; // @[RegisterRouter.scala:87:24] assign out_roready_1_786 = _out_rofireMux_T_1166; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1167 = ~_out_T_1803; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1169 = _out_rofireMux_T_260 & out_backSel_227; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1170 = _out_rofireMux_T_1169 & _out_T_1909; // @[RegisterRouter.scala:87:24] assign out_roready_1_1203 = _out_rofireMux_T_1170; // @[RegisterRouter.scala:87:24] assign out_roready_1_1204 = _out_rofireMux_T_1170; // @[RegisterRouter.scala:87:24] assign out_roready_1_1205 = _out_rofireMux_T_1170; // @[RegisterRouter.scala:87:24] assign out_roready_1_1206 = _out_rofireMux_T_1170; // @[RegisterRouter.scala:87:24] assign out_roready_1_1207 = _out_rofireMux_T_1170; // @[RegisterRouter.scala:87:24] assign out_roready_1_1208 = _out_rofireMux_T_1170; // @[RegisterRouter.scala:87:24] assign out_roready_1_1209 = _out_rofireMux_T_1170; // @[RegisterRouter.scala:87:24] assign out_roready_1_1210 = _out_rofireMux_T_1170; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1171 = ~_out_T_1909; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1173 = _out_rofireMux_T_260 & out_backSel_228; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1174 = _out_rofireMux_T_1173 & _out_T_1639; // @[RegisterRouter.scala:87:24] assign out_roready_1_152 = _out_rofireMux_T_1174; // @[RegisterRouter.scala:87:24] assign out_roready_1_153 = _out_rofireMux_T_1174; // @[RegisterRouter.scala:87:24] assign out_roready_1_154 = _out_rofireMux_T_1174; // @[RegisterRouter.scala:87:24] assign out_roready_1_155 = _out_rofireMux_T_1174; // @[RegisterRouter.scala:87:24] assign out_roready_1_156 = _out_rofireMux_T_1174; // @[RegisterRouter.scala:87:24] assign out_roready_1_157 = _out_rofireMux_T_1174; // @[RegisterRouter.scala:87:24] assign out_roready_1_158 = _out_rofireMux_T_1174; // @[RegisterRouter.scala:87:24] assign out_roready_1_159 = _out_rofireMux_T_1174; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1175 = ~_out_T_1639; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1177 = _out_rofireMux_T_260 & out_backSel_229; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1178 = _out_rofireMux_T_1177 & _out_T_1691; // @[RegisterRouter.scala:87:24] assign out_roready_1_354 = _out_rofireMux_T_1178; // @[RegisterRouter.scala:87:24] assign out_roready_1_355 = _out_rofireMux_T_1178; // @[RegisterRouter.scala:87:24] assign out_roready_1_356 = _out_rofireMux_T_1178; // @[RegisterRouter.scala:87:24] assign out_roready_1_357 = _out_rofireMux_T_1178; // @[RegisterRouter.scala:87:24] assign out_roready_1_358 = _out_rofireMux_T_1178; // @[RegisterRouter.scala:87:24] assign out_roready_1_359 = _out_rofireMux_T_1178; // @[RegisterRouter.scala:87:24] assign out_roready_1_360 = _out_rofireMux_T_1178; // @[RegisterRouter.scala:87:24] assign out_roready_1_361 = _out_rofireMux_T_1178; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1179 = ~_out_T_1691; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1181 = _out_rofireMux_T_260 & out_backSel_230; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1182 = _out_rofireMux_T_1181 & _out_T_1775; // @[RegisterRouter.scala:87:24] assign out_roready_1_673 = _out_rofireMux_T_1182; // @[RegisterRouter.scala:87:24] assign out_roready_1_674 = _out_rofireMux_T_1182; // @[RegisterRouter.scala:87:24] assign out_roready_1_675 = _out_rofireMux_T_1182; // @[RegisterRouter.scala:87:24] assign out_roready_1_676 = _out_rofireMux_T_1182; // @[RegisterRouter.scala:87:24] assign out_roready_1_677 = _out_rofireMux_T_1182; // @[RegisterRouter.scala:87:24] assign out_roready_1_678 = _out_rofireMux_T_1182; // @[RegisterRouter.scala:87:24] assign out_roready_1_679 = _out_rofireMux_T_1182; // @[RegisterRouter.scala:87:24] assign out_roready_1_680 = _out_rofireMux_T_1182; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1183 = ~_out_T_1775; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1185 = _out_rofireMux_T_260 & out_backSel_231; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1186 = _out_rofireMux_T_1185 & _out_T_1845; // @[RegisterRouter.scala:87:24] assign out_roready_1_947 = _out_rofireMux_T_1186; // @[RegisterRouter.scala:87:24] assign out_roready_1_948 = _out_rofireMux_T_1186; // @[RegisterRouter.scala:87:24] assign out_roready_1_949 = _out_rofireMux_T_1186; // @[RegisterRouter.scala:87:24] assign out_roready_1_950 = _out_rofireMux_T_1186; // @[RegisterRouter.scala:87:24] assign out_roready_1_951 = _out_rofireMux_T_1186; // @[RegisterRouter.scala:87:24] assign out_roready_1_952 = _out_rofireMux_T_1186; // @[RegisterRouter.scala:87:24] assign out_roready_1_953 = _out_rofireMux_T_1186; // @[RegisterRouter.scala:87:24] assign out_roready_1_954 = _out_rofireMux_T_1186; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1187 = ~_out_T_1845; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1189 = _out_rofireMux_T_260 & out_backSel_232; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1190 = _out_rofireMux_T_1189 & _out_T_1905; // @[RegisterRouter.scala:87:24] assign out_roready_1_1187 = _out_rofireMux_T_1190; // @[RegisterRouter.scala:87:24] assign out_roready_1_1188 = _out_rofireMux_T_1190; // @[RegisterRouter.scala:87:24] assign out_roready_1_1189 = _out_rofireMux_T_1190; // @[RegisterRouter.scala:87:24] assign out_roready_1_1190 = _out_rofireMux_T_1190; // @[RegisterRouter.scala:87:24] assign out_roready_1_1191 = _out_rofireMux_T_1190; // @[RegisterRouter.scala:87:24] assign out_roready_1_1192 = _out_rofireMux_T_1190; // @[RegisterRouter.scala:87:24] assign out_roready_1_1193 = _out_rofireMux_T_1190; // @[RegisterRouter.scala:87:24] assign out_roready_1_1194 = _out_rofireMux_T_1190; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1191 = ~_out_T_1905; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1193 = _out_rofireMux_T_260 & out_backSel_233; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1194 = _out_rofireMux_T_1193 & _out_T_1671; // @[RegisterRouter.scala:87:24] assign out_roready_1_280 = _out_rofireMux_T_1194; // @[RegisterRouter.scala:87:24] assign out_roready_1_281 = _out_rofireMux_T_1194; // @[RegisterRouter.scala:87:24] assign out_roready_1_282 = _out_rofireMux_T_1194; // @[RegisterRouter.scala:87:24] assign out_roready_1_283 = _out_rofireMux_T_1194; // @[RegisterRouter.scala:87:24] assign out_roready_1_284 = _out_rofireMux_T_1194; // @[RegisterRouter.scala:87:24] assign out_roready_1_285 = _out_rofireMux_T_1194; // @[RegisterRouter.scala:87:24] assign out_roready_1_286 = _out_rofireMux_T_1194; // @[RegisterRouter.scala:87:24] assign out_roready_1_287 = _out_rofireMux_T_1194; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1195 = ~_out_T_1671; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1197 = _out_rofireMux_T_260 & out_backSel_234; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1198 = _out_rofireMux_T_1197 & _out_T_1605; // @[RegisterRouter.scala:87:24] assign out_roready_1_16 = _out_rofireMux_T_1198; // @[RegisterRouter.scala:87:24] assign out_roready_1_17 = _out_rofireMux_T_1198; // @[RegisterRouter.scala:87:24] assign out_roready_1_18 = _out_rofireMux_T_1198; // @[RegisterRouter.scala:87:24] assign out_roready_1_19 = _out_rofireMux_T_1198; // @[RegisterRouter.scala:87:24] assign out_roready_1_20 = _out_rofireMux_T_1198; // @[RegisterRouter.scala:87:24] assign out_roready_1_21 = _out_rofireMux_T_1198; // @[RegisterRouter.scala:87:24] assign out_roready_1_22 = _out_rofireMux_T_1198; // @[RegisterRouter.scala:87:24] assign out_roready_1_23 = _out_rofireMux_T_1198; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1199 = ~_out_T_1605; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1201 = _out_rofireMux_T_260 & out_backSel_235; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1202 = _out_rofireMux_T_1201 & _out_T_1863; // @[RegisterRouter.scala:87:24] assign out_roready_1_1019 = _out_rofireMux_T_1202; // @[RegisterRouter.scala:87:24] assign out_roready_1_1020 = _out_rofireMux_T_1202; // @[RegisterRouter.scala:87:24] assign out_roready_1_1021 = _out_rofireMux_T_1202; // @[RegisterRouter.scala:87:24] assign out_roready_1_1022 = _out_rofireMux_T_1202; // @[RegisterRouter.scala:87:24] assign out_roready_1_1023 = _out_rofireMux_T_1202; // @[RegisterRouter.scala:87:24] assign out_roready_1_1024 = _out_rofireMux_T_1202; // @[RegisterRouter.scala:87:24] assign out_roready_1_1025 = _out_rofireMux_T_1202; // @[RegisterRouter.scala:87:24] assign out_roready_1_1026 = _out_rofireMux_T_1202; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1203 = ~_out_T_1863; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1205 = _out_rofireMux_T_260 & out_backSel_236; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1206 = _out_rofireMux_T_1205 & _out_T_1761; // @[RegisterRouter.scala:87:24] assign out_roready_1_617 = _out_rofireMux_T_1206; // @[RegisterRouter.scala:87:24] assign out_roready_1_618 = _out_rofireMux_T_1206; // @[RegisterRouter.scala:87:24] assign out_roready_1_619 = _out_rofireMux_T_1206; // @[RegisterRouter.scala:87:24] assign out_roready_1_620 = _out_rofireMux_T_1206; // @[RegisterRouter.scala:87:24] assign out_roready_1_621 = _out_rofireMux_T_1206; // @[RegisterRouter.scala:87:24] assign out_roready_1_622 = _out_rofireMux_T_1206; // @[RegisterRouter.scala:87:24] assign out_roready_1_623 = _out_rofireMux_T_1206; // @[RegisterRouter.scala:87:24] assign out_roready_1_624 = _out_rofireMux_T_1206; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1207 = ~_out_T_1761; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1209 = _out_rofireMux_T_260 & out_backSel_237; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1210 = _out_rofireMux_T_1209 & _out_T_1731; // @[RegisterRouter.scala:87:24] assign out_roready_1_503 = _out_rofireMux_T_1210; // @[RegisterRouter.scala:87:24] assign out_roready_1_504 = _out_rofireMux_T_1210; // @[RegisterRouter.scala:87:24] assign out_roready_1_505 = _out_rofireMux_T_1210; // @[RegisterRouter.scala:87:24] assign out_roready_1_506 = _out_rofireMux_T_1210; // @[RegisterRouter.scala:87:24] assign out_roready_1_507 = _out_rofireMux_T_1210; // @[RegisterRouter.scala:87:24] assign out_roready_1_508 = _out_rofireMux_T_1210; // @[RegisterRouter.scala:87:24] assign out_roready_1_509 = _out_rofireMux_T_1210; // @[RegisterRouter.scala:87:24] assign out_roready_1_510 = _out_rofireMux_T_1210; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1211 = ~_out_T_1731; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1213 = _out_rofireMux_T_260 & out_backSel_238; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1214 = _out_rofireMux_T_1213 & _out_T_1651; // @[RegisterRouter.scala:87:24] assign out_roready_1_200 = _out_rofireMux_T_1214; // @[RegisterRouter.scala:87:24] assign out_roready_1_201 = _out_rofireMux_T_1214; // @[RegisterRouter.scala:87:24] assign out_roready_1_202 = _out_rofireMux_T_1214; // @[RegisterRouter.scala:87:24] assign out_roready_1_203 = _out_rofireMux_T_1214; // @[RegisterRouter.scala:87:24] assign out_roready_1_204 = _out_rofireMux_T_1214; // @[RegisterRouter.scala:87:24] assign out_roready_1_205 = _out_rofireMux_T_1214; // @[RegisterRouter.scala:87:24] assign out_roready_1_206 = _out_rofireMux_T_1214; // @[RegisterRouter.scala:87:24] assign out_roready_1_207 = _out_rofireMux_T_1214; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1215 = ~_out_T_1651; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1217 = _out_rofireMux_T_260 & out_backSel_239; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1218 = _out_rofireMux_T_1217 & _out_T_1887; // @[RegisterRouter.scala:87:24] assign out_roready_1_1115 = _out_rofireMux_T_1218; // @[RegisterRouter.scala:87:24] assign out_roready_1_1116 = _out_rofireMux_T_1218; // @[RegisterRouter.scala:87:24] assign out_roready_1_1117 = _out_rofireMux_T_1218; // @[RegisterRouter.scala:87:24] assign out_roready_1_1118 = _out_rofireMux_T_1218; // @[RegisterRouter.scala:87:24] assign out_roready_1_1119 = _out_rofireMux_T_1218; // @[RegisterRouter.scala:87:24] assign out_roready_1_1120 = _out_rofireMux_T_1218; // @[RegisterRouter.scala:87:24] assign out_roready_1_1121 = _out_rofireMux_T_1218; // @[RegisterRouter.scala:87:24] assign out_roready_1_1122 = _out_rofireMux_T_1218; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1219 = ~_out_T_1887; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1221 = _out_rofireMux_T_260 & out_backSel_240; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1222 = _out_rofireMux_T_1221 & _out_T_1793; // @[RegisterRouter.scala:87:24] assign out_roready_1_739 = _out_rofireMux_T_1222; // @[RegisterRouter.scala:87:24] assign out_roready_1_740 = _out_rofireMux_T_1222; // @[RegisterRouter.scala:87:24] assign out_roready_1_741 = _out_rofireMux_T_1222; // @[RegisterRouter.scala:87:24] assign out_roready_1_742 = _out_rofireMux_T_1222; // @[RegisterRouter.scala:87:24] assign out_roready_1_743 = _out_rofireMux_T_1222; // @[RegisterRouter.scala:87:24] assign out_roready_1_744 = _out_rofireMux_T_1222; // @[RegisterRouter.scala:87:24] assign out_roready_1_745 = _out_rofireMux_T_1222; // @[RegisterRouter.scala:87:24] assign out_roready_1_746 = _out_rofireMux_T_1222; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1223 = ~_out_T_1793; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1225 = _out_rofireMux_T_260 & out_backSel_241; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1226 = _out_rofireMux_T_1225 & _out_T_1805; // @[RegisterRouter.scala:87:24] assign out_roready_1_787 = _out_rofireMux_T_1226; // @[RegisterRouter.scala:87:24] assign out_roready_1_788 = _out_rofireMux_T_1226; // @[RegisterRouter.scala:87:24] assign out_roready_1_789 = _out_rofireMux_T_1226; // @[RegisterRouter.scala:87:24] assign out_roready_1_790 = _out_rofireMux_T_1226; // @[RegisterRouter.scala:87:24] assign out_roready_1_791 = _out_rofireMux_T_1226; // @[RegisterRouter.scala:87:24] assign out_roready_1_792 = _out_rofireMux_T_1226; // @[RegisterRouter.scala:87:24] assign out_roready_1_793 = _out_rofireMux_T_1226; // @[RegisterRouter.scala:87:24] assign out_roready_1_794 = _out_rofireMux_T_1226; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1227 = ~_out_T_1805; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1229 = _out_rofireMux_T_260 & out_backSel_242; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1230 = _out_rofireMux_T_1229 & _out_T_1889; // @[RegisterRouter.scala:87:24] assign out_roready_1_1123 = _out_rofireMux_T_1230; // @[RegisterRouter.scala:87:24] assign out_roready_1_1124 = _out_rofireMux_T_1230; // @[RegisterRouter.scala:87:24] assign out_roready_1_1125 = _out_rofireMux_T_1230; // @[RegisterRouter.scala:87:24] assign out_roready_1_1126 = _out_rofireMux_T_1230; // @[RegisterRouter.scala:87:24] assign out_roready_1_1127 = _out_rofireMux_T_1230; // @[RegisterRouter.scala:87:24] assign out_roready_1_1128 = _out_rofireMux_T_1230; // @[RegisterRouter.scala:87:24] assign out_roready_1_1129 = _out_rofireMux_T_1230; // @[RegisterRouter.scala:87:24] assign out_roready_1_1130 = _out_rofireMux_T_1230; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1231 = ~_out_T_1889; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1233 = _out_rofireMux_T_260 & out_backSel_243; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1234 = _out_rofireMux_T_1233 & _out_T_1665; // @[RegisterRouter.scala:87:24] assign out_roready_1_256 = _out_rofireMux_T_1234; // @[RegisterRouter.scala:87:24] assign out_roready_1_257 = _out_rofireMux_T_1234; // @[RegisterRouter.scala:87:24] assign out_roready_1_258 = _out_rofireMux_T_1234; // @[RegisterRouter.scala:87:24] assign out_roready_1_259 = _out_rofireMux_T_1234; // @[RegisterRouter.scala:87:24] assign out_roready_1_260 = _out_rofireMux_T_1234; // @[RegisterRouter.scala:87:24] assign out_roready_1_261 = _out_rofireMux_T_1234; // @[RegisterRouter.scala:87:24] assign out_roready_1_262 = _out_rofireMux_T_1234; // @[RegisterRouter.scala:87:24] assign out_roready_1_263 = _out_rofireMux_T_1234; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1235 = ~_out_T_1665; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1237 = _out_rofireMux_T_260 & out_backSel_244; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1238 = _out_rofireMux_T_1237 & _out_T_1735; // @[RegisterRouter.scala:87:24] assign out_roready_1_519 = _out_rofireMux_T_1238; // @[RegisterRouter.scala:87:24] assign out_roready_1_520 = _out_rofireMux_T_1238; // @[RegisterRouter.scala:87:24] assign out_roready_1_521 = _out_rofireMux_T_1238; // @[RegisterRouter.scala:87:24] assign out_roready_1_522 = _out_rofireMux_T_1238; // @[RegisterRouter.scala:87:24] assign out_roready_1_523 = _out_rofireMux_T_1238; // @[RegisterRouter.scala:87:24] assign out_roready_1_524 = _out_rofireMux_T_1238; // @[RegisterRouter.scala:87:24] assign out_roready_1_525 = _out_rofireMux_T_1238; // @[RegisterRouter.scala:87:24] assign out_roready_1_526 = _out_rofireMux_T_1238; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1239 = ~_out_T_1735; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1241 = _out_rofireMux_T_260 & out_backSel_245; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1242 = _out_rofireMux_T_1241 & _out_T_1777; // @[RegisterRouter.scala:87:24] assign out_roready_1_681 = _out_rofireMux_T_1242; // @[RegisterRouter.scala:87:24] assign out_roready_1_682 = _out_rofireMux_T_1242; // @[RegisterRouter.scala:87:24] assign out_roready_1_683 = _out_rofireMux_T_1242; // @[RegisterRouter.scala:87:24] assign out_roready_1_684 = _out_rofireMux_T_1242; // @[RegisterRouter.scala:87:24] assign out_roready_1_685 = _out_rofireMux_T_1242; // @[RegisterRouter.scala:87:24] assign out_roready_1_686 = _out_rofireMux_T_1242; // @[RegisterRouter.scala:87:24] assign out_roready_1_687 = _out_rofireMux_T_1242; // @[RegisterRouter.scala:87:24] assign out_roready_1_688 = _out_rofireMux_T_1242; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1243 = ~_out_T_1777; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1245 = _out_rofireMux_T_260 & out_backSel_246; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1246 = _out_rofireMux_T_1245 & _out_T_1865; // @[RegisterRouter.scala:87:24] assign out_roready_1_1027 = _out_rofireMux_T_1246; // @[RegisterRouter.scala:87:24] assign out_roready_1_1028 = _out_rofireMux_T_1246; // @[RegisterRouter.scala:87:24] assign out_roready_1_1029 = _out_rofireMux_T_1246; // @[RegisterRouter.scala:87:24] assign out_roready_1_1030 = _out_rofireMux_T_1246; // @[RegisterRouter.scala:87:24] assign out_roready_1_1031 = _out_rofireMux_T_1246; // @[RegisterRouter.scala:87:24] assign out_roready_1_1032 = _out_rofireMux_T_1246; // @[RegisterRouter.scala:87:24] assign out_roready_1_1033 = _out_rofireMux_T_1246; // @[RegisterRouter.scala:87:24] assign out_roready_1_1034 = _out_rofireMux_T_1246; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1247 = ~_out_T_1865; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1249 = _out_rofireMux_T_260 & out_backSel_247; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1250 = _out_rofireMux_T_1249 & _out_T_1613; // @[RegisterRouter.scala:87:24] assign out_roready_1_48 = _out_rofireMux_T_1250; // @[RegisterRouter.scala:87:24] assign out_roready_1_49 = _out_rofireMux_T_1250; // @[RegisterRouter.scala:87:24] assign out_roready_1_50 = _out_rofireMux_T_1250; // @[RegisterRouter.scala:87:24] assign out_roready_1_51 = _out_rofireMux_T_1250; // @[RegisterRouter.scala:87:24] assign out_roready_1_52 = _out_rofireMux_T_1250; // @[RegisterRouter.scala:87:24] assign out_roready_1_53 = _out_rofireMux_T_1250; // @[RegisterRouter.scala:87:24] assign out_roready_1_54 = _out_rofireMux_T_1250; // @[RegisterRouter.scala:87:24] assign out_roready_1_55 = _out_rofireMux_T_1250; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1251 = ~_out_T_1613; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1253 = _out_rofireMux_T_260 & out_backSel_248; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1254 = _out_rofireMux_T_1253 & _out_T_1673; // @[RegisterRouter.scala:87:24] assign out_roready_1_288 = _out_rofireMux_T_1254; // @[RegisterRouter.scala:87:24] assign out_roready_1_289 = _out_rofireMux_T_1254; // @[RegisterRouter.scala:87:24] assign out_roready_1_290 = _out_rofireMux_T_1254; // @[RegisterRouter.scala:87:24] assign out_roready_1_291 = _out_rofireMux_T_1254; // @[RegisterRouter.scala:87:24] assign out_roready_1_292 = _out_rofireMux_T_1254; // @[RegisterRouter.scala:87:24] assign out_roready_1_293 = _out_rofireMux_T_1254; // @[RegisterRouter.scala:87:24] assign out_roready_1_294 = _out_rofireMux_T_1254; // @[RegisterRouter.scala:87:24] assign out_roready_1_295 = _out_rofireMux_T_1254; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1255 = ~_out_T_1673; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1257 = _out_rofireMux_T_260 & out_backSel_249; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1258 = _out_rofireMux_T_1257 & _out_T_1603; // @[RegisterRouter.scala:87:24] assign out_roready_1_8 = _out_rofireMux_T_1258; // @[RegisterRouter.scala:87:24] assign out_roready_1_9 = _out_rofireMux_T_1258; // @[RegisterRouter.scala:87:24] assign out_roready_1_10 = _out_rofireMux_T_1258; // @[RegisterRouter.scala:87:24] assign out_roready_1_11 = _out_rofireMux_T_1258; // @[RegisterRouter.scala:87:24] assign out_roready_1_12 = _out_rofireMux_T_1258; // @[RegisterRouter.scala:87:24] assign out_roready_1_13 = _out_rofireMux_T_1258; // @[RegisterRouter.scala:87:24] assign out_roready_1_14 = _out_rofireMux_T_1258; // @[RegisterRouter.scala:87:24] assign out_roready_1_15 = _out_rofireMux_T_1258; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1259 = ~_out_T_1603; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1261 = _out_rofireMux_T_260 & out_backSel_250; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1262 = _out_rofireMux_T_1261 & _out_T_1843; // @[RegisterRouter.scala:87:24] assign out_roready_1_939 = _out_rofireMux_T_1262; // @[RegisterRouter.scala:87:24] assign out_roready_1_940 = _out_rofireMux_T_1262; // @[RegisterRouter.scala:87:24] assign out_roready_1_941 = _out_rofireMux_T_1262; // @[RegisterRouter.scala:87:24] assign out_roready_1_942 = _out_rofireMux_T_1262; // @[RegisterRouter.scala:87:24] assign out_roready_1_943 = _out_rofireMux_T_1262; // @[RegisterRouter.scala:87:24] assign out_roready_1_944 = _out_rofireMux_T_1262; // @[RegisterRouter.scala:87:24] assign out_roready_1_945 = _out_rofireMux_T_1262; // @[RegisterRouter.scala:87:24] assign out_roready_1_946 = _out_rofireMux_T_1262; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1263 = ~_out_T_1843; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1265 = _out_rofireMux_T_260 & out_backSel_251; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1266 = _out_rofireMux_T_1265 & _out_T_1795; // @[RegisterRouter.scala:87:24] assign out_roready_1_747 = _out_rofireMux_T_1266; // @[RegisterRouter.scala:87:24] assign out_roready_1_748 = _out_rofireMux_T_1266; // @[RegisterRouter.scala:87:24] assign out_roready_1_749 = _out_rofireMux_T_1266; // @[RegisterRouter.scala:87:24] assign out_roready_1_750 = _out_rofireMux_T_1266; // @[RegisterRouter.scala:87:24] assign out_roready_1_751 = _out_rofireMux_T_1266; // @[RegisterRouter.scala:87:24] assign out_roready_1_752 = _out_rofireMux_T_1266; // @[RegisterRouter.scala:87:24] assign out_roready_1_753 = _out_rofireMux_T_1266; // @[RegisterRouter.scala:87:24] assign out_roready_1_754 = _out_rofireMux_T_1266; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1267 = ~_out_T_1795; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1269 = _out_rofireMux_T_260 & out_backSel_252; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1270 = _out_rofireMux_T_1269 & _out_T_1693; // @[RegisterRouter.scala:87:24] assign out_roready_1_362 = _out_rofireMux_T_1270; // @[RegisterRouter.scala:87:24] assign out_roready_1_363 = _out_rofireMux_T_1270; // @[RegisterRouter.scala:87:24] assign out_roready_1_364 = _out_rofireMux_T_1270; // @[RegisterRouter.scala:87:24] assign out_roready_1_365 = _out_rofireMux_T_1270; // @[RegisterRouter.scala:87:24] assign out_roready_1_366 = _out_rofireMux_T_1270; // @[RegisterRouter.scala:87:24] assign out_roready_1_367 = _out_rofireMux_T_1270; // @[RegisterRouter.scala:87:24] assign out_roready_1_368 = _out_rofireMux_T_1270; // @[RegisterRouter.scala:87:24] assign out_roready_1_369 = _out_rofireMux_T_1270; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1271 = ~_out_T_1693; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1273 = _out_rofireMux_T_260 & out_backSel_253; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1274 = _out_rofireMux_T_1273 & _out_T_1655; // @[RegisterRouter.scala:87:24] assign out_roready_1_216 = _out_rofireMux_T_1274; // @[RegisterRouter.scala:87:24] assign out_roready_1_217 = _out_rofireMux_T_1274; // @[RegisterRouter.scala:87:24] assign out_roready_1_218 = _out_rofireMux_T_1274; // @[RegisterRouter.scala:87:24] assign out_roready_1_219 = _out_rofireMux_T_1274; // @[RegisterRouter.scala:87:24] assign out_roready_1_220 = _out_rofireMux_T_1274; // @[RegisterRouter.scala:87:24] assign out_roready_1_221 = _out_rofireMux_T_1274; // @[RegisterRouter.scala:87:24] assign out_roready_1_222 = _out_rofireMux_T_1274; // @[RegisterRouter.scala:87:24] assign out_roready_1_223 = _out_rofireMux_T_1274; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1275 = ~_out_T_1655; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1277 = _out_rofireMux_T_260 & out_backSel_254; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1278 = _out_rofireMux_T_1277 & _out_T_1907; // @[RegisterRouter.scala:87:24] assign out_roready_1_1195 = _out_rofireMux_T_1278; // @[RegisterRouter.scala:87:24] assign out_roready_1_1196 = _out_rofireMux_T_1278; // @[RegisterRouter.scala:87:24] assign out_roready_1_1197 = _out_rofireMux_T_1278; // @[RegisterRouter.scala:87:24] assign out_roready_1_1198 = _out_rofireMux_T_1278; // @[RegisterRouter.scala:87:24] assign out_roready_1_1199 = _out_rofireMux_T_1278; // @[RegisterRouter.scala:87:24] assign out_roready_1_1200 = _out_rofireMux_T_1278; // @[RegisterRouter.scala:87:24] assign out_roready_1_1201 = _out_rofireMux_T_1278; // @[RegisterRouter.scala:87:24] assign out_roready_1_1202 = _out_rofireMux_T_1278; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1279 = ~_out_T_1907; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1281 = _out_rofireMux_T_260 & out_backSel_255; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1282 = _out_rofireMux_T_1281 & _out_T_1811; // @[RegisterRouter.scala:87:24] assign out_roready_1_811 = _out_rofireMux_T_1282; // @[RegisterRouter.scala:87:24] assign out_roready_1_812 = _out_rofireMux_T_1282; // @[RegisterRouter.scala:87:24] assign out_roready_1_813 = _out_rofireMux_T_1282; // @[RegisterRouter.scala:87:24] assign out_roready_1_814 = _out_rofireMux_T_1282; // @[RegisterRouter.scala:87:24] assign out_roready_1_815 = _out_rofireMux_T_1282; // @[RegisterRouter.scala:87:24] assign out_roready_1_816 = _out_rofireMux_T_1282; // @[RegisterRouter.scala:87:24] assign out_roready_1_817 = _out_rofireMux_T_1282; // @[RegisterRouter.scala:87:24] assign out_roready_1_818 = _out_rofireMux_T_1282; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1283 = ~_out_T_1811; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_261 = ~out_front_1_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_262 = _out_wofireMux_T_260 & _out_wofireMux_T_261; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_263 = _out_wofireMux_T_262 & out_backSel_0_1; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_264 = _out_wofireMux_T_263 & _out_T_1717; // @[RegisterRouter.scala:87:24] assign out_woready_1_451 = _out_wofireMux_T_264; // @[RegisterRouter.scala:87:24] assign out_woready_1_452 = _out_wofireMux_T_264; // @[RegisterRouter.scala:87:24] assign out_woready_1_453 = _out_wofireMux_T_264; // @[RegisterRouter.scala:87:24] assign out_woready_1_454 = _out_wofireMux_T_264; // @[RegisterRouter.scala:87:24] assign out_woready_1_455 = _out_wofireMux_T_264; // @[RegisterRouter.scala:87:24] assign out_woready_1_456 = _out_wofireMux_T_264; // @[RegisterRouter.scala:87:24] assign out_woready_1_457 = _out_wofireMux_T_264; // @[RegisterRouter.scala:87:24] assign out_woready_1_458 = _out_wofireMux_T_264; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_265 = ~_out_T_1717; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_267 = _out_wofireMux_T_262 & out_backSel_1_1; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_268 = _out_wofireMux_T_267 & _out_T_1625; // @[RegisterRouter.scala:87:24] assign out_woready_1_96 = _out_wofireMux_T_268; // @[RegisterRouter.scala:87:24] assign out_woready_1_97 = _out_wofireMux_T_268; // @[RegisterRouter.scala:87:24] assign out_woready_1_98 = _out_wofireMux_T_268; // @[RegisterRouter.scala:87:24] assign out_woready_1_99 = _out_wofireMux_T_268; // @[RegisterRouter.scala:87:24] assign out_woready_1_100 = _out_wofireMux_T_268; // @[RegisterRouter.scala:87:24] assign out_woready_1_101 = _out_wofireMux_T_268; // @[RegisterRouter.scala:87:24] assign out_woready_1_102 = _out_wofireMux_T_268; // @[RegisterRouter.scala:87:24] assign out_woready_1_103 = _out_wofireMux_T_268; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_269 = ~_out_T_1625; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_271 = _out_wofireMux_T_262 & out_backSel_2_1; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_272 = _out_wofireMux_T_271 & _out_T_1847; // @[RegisterRouter.scala:87:24] assign out_woready_1_955 = _out_wofireMux_T_272; // @[RegisterRouter.scala:87:24] assign out_woready_1_956 = _out_wofireMux_T_272; // @[RegisterRouter.scala:87:24] assign out_woready_1_957 = _out_wofireMux_T_272; // @[RegisterRouter.scala:87:24] assign out_woready_1_958 = _out_wofireMux_T_272; // @[RegisterRouter.scala:87:24] assign out_woready_1_959 = _out_wofireMux_T_272; // @[RegisterRouter.scala:87:24] assign out_woready_1_960 = _out_wofireMux_T_272; // @[RegisterRouter.scala:87:24] assign out_woready_1_961 = _out_wofireMux_T_272; // @[RegisterRouter.scala:87:24] assign out_woready_1_962 = _out_wofireMux_T_272; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_273 = ~_out_T_1847; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_275 = _out_wofireMux_T_262 & out_backSel_3_1; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_276 = _out_wofireMux_T_275 & _out_T_1757; // @[RegisterRouter.scala:87:24] assign out_woready_1_601 = _out_wofireMux_T_276; // @[RegisterRouter.scala:87:24] assign out_woready_1_602 = _out_wofireMux_T_276; // @[RegisterRouter.scala:87:24] assign out_woready_1_603 = _out_wofireMux_T_276; // @[RegisterRouter.scala:87:24] assign out_woready_1_604 = _out_wofireMux_T_276; // @[RegisterRouter.scala:87:24] assign out_woready_1_605 = _out_wofireMux_T_276; // @[RegisterRouter.scala:87:24] assign out_woready_1_606 = _out_wofireMux_T_276; // @[RegisterRouter.scala:87:24] assign out_woready_1_607 = _out_wofireMux_T_276; // @[RegisterRouter.scala:87:24] assign out_woready_1_608 = _out_wofireMux_T_276; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_277 = ~_out_T_1757; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_279 = _out_wofireMux_T_262 & out_backSel_4_1; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_280 = _out_wofireMux_T_279 & _out_T_1679; // @[RegisterRouter.scala:87:24] assign out_woready_1_312 = _out_wofireMux_T_280; // @[RegisterRouter.scala:87:24] assign out_woready_1_313 = _out_wofireMux_T_280; // @[RegisterRouter.scala:87:24] assign out_woready_1_314 = _out_wofireMux_T_280; // @[RegisterRouter.scala:87:24] assign out_woready_1_315 = _out_wofireMux_T_280; // @[RegisterRouter.scala:87:24] assign out_woready_1_316 = _out_wofireMux_T_280; // @[RegisterRouter.scala:87:24] assign out_woready_1_317 = _out_wofireMux_T_280; // @[RegisterRouter.scala:87:24] assign out_woready_1_318 = _out_wofireMux_T_280; // @[RegisterRouter.scala:87:24] assign out_woready_1_319 = _out_wofireMux_T_280; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_281 = ~_out_T_1679; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_283 = _out_wofireMux_T_262 & out_backSel_5_1; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_284 = _out_wofireMux_T_283 & _out_T_1641; // @[RegisterRouter.scala:87:24] assign out_woready_1_160 = _out_wofireMux_T_284; // @[RegisterRouter.scala:87:24] assign out_woready_1_161 = _out_wofireMux_T_284; // @[RegisterRouter.scala:87:24] assign out_woready_1_162 = _out_wofireMux_T_284; // @[RegisterRouter.scala:87:24] assign out_woready_1_163 = _out_wofireMux_T_284; // @[RegisterRouter.scala:87:24] assign out_woready_1_164 = _out_wofireMux_T_284; // @[RegisterRouter.scala:87:24] assign out_woready_1_165 = _out_wofireMux_T_284; // @[RegisterRouter.scala:87:24] assign out_woready_1_166 = _out_wofireMux_T_284; // @[RegisterRouter.scala:87:24] assign out_woready_1_167 = _out_wofireMux_T_284; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_285 = ~_out_T_1641; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_287 = _out_wofireMux_T_262 & out_backSel_6_1; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_288 = _out_wofireMux_T_287 & _out_T_1877; // @[RegisterRouter.scala:87:24] assign out_woready_1_1075 = _out_wofireMux_T_288; // @[RegisterRouter.scala:87:24] assign out_woready_1_1076 = _out_wofireMux_T_288; // @[RegisterRouter.scala:87:24] assign out_woready_1_1077 = _out_wofireMux_T_288; // @[RegisterRouter.scala:87:24] assign out_woready_1_1078 = _out_wofireMux_T_288; // @[RegisterRouter.scala:87:24] assign out_woready_1_1079 = _out_wofireMux_T_288; // @[RegisterRouter.scala:87:24] assign out_woready_1_1080 = _out_wofireMux_T_288; // @[RegisterRouter.scala:87:24] assign out_woready_1_1081 = _out_wofireMux_T_288; // @[RegisterRouter.scala:87:24] assign out_woready_1_1082 = _out_wofireMux_T_288; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_289 = ~_out_T_1877; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_291 = _out_wofireMux_T_262 & out_backSel_7_1; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_292 = _out_wofireMux_T_291 & _out_T_1823; // @[RegisterRouter.scala:87:24] assign out_woready_1_859 = _out_wofireMux_T_292; // @[RegisterRouter.scala:87:24] assign out_woready_1_860 = _out_wofireMux_T_292; // @[RegisterRouter.scala:87:24] assign out_woready_1_861 = _out_wofireMux_T_292; // @[RegisterRouter.scala:87:24] assign out_woready_1_862 = _out_wofireMux_T_292; // @[RegisterRouter.scala:87:24] assign out_woready_1_863 = _out_wofireMux_T_292; // @[RegisterRouter.scala:87:24] assign out_woready_1_864 = _out_wofireMux_T_292; // @[RegisterRouter.scala:87:24] assign out_woready_1_865 = _out_wofireMux_T_292; // @[RegisterRouter.scala:87:24] assign out_woready_1_866 = _out_wofireMux_T_292; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_293 = ~_out_T_1823; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_295 = _out_wofireMux_T_262 & out_backSel_8_1; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_296 = _out_wofireMux_T_295 & _out_T_1743; // @[RegisterRouter.scala:87:24] assign out_woready_1_545 = _out_wofireMux_T_296; // @[RegisterRouter.scala:87:24] assign out_woready_1_546 = _out_wofireMux_T_296; // @[RegisterRouter.scala:87:24] assign out_woready_1_547 = _out_wofireMux_T_296; // @[RegisterRouter.scala:87:24] assign out_woready_1_548 = _out_wofireMux_T_296; // @[RegisterRouter.scala:87:24] assign out_woready_1_549 = _out_wofireMux_T_296; // @[RegisterRouter.scala:87:24] assign out_woready_1_550 = _out_wofireMux_T_296; // @[RegisterRouter.scala:87:24] assign out_woready_1_551 = _out_wofireMux_T_296; // @[RegisterRouter.scala:87:24] assign out_woready_1_552 = _out_wofireMux_T_296; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_297 = ~_out_T_1743; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_299 = _out_wofireMux_T_262 & out_backSel_9_1; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_300 = _out_wofireMux_T_299 & _out_T_1667; // @[RegisterRouter.scala:87:24] assign out_woready_1_264 = _out_wofireMux_T_300; // @[RegisterRouter.scala:87:24] assign out_woready_1_265 = _out_wofireMux_T_300; // @[RegisterRouter.scala:87:24] assign out_woready_1_266 = _out_wofireMux_T_300; // @[RegisterRouter.scala:87:24] assign out_woready_1_267 = _out_wofireMux_T_300; // @[RegisterRouter.scala:87:24] assign out_woready_1_268 = _out_wofireMux_T_300; // @[RegisterRouter.scala:87:24] assign out_woready_1_269 = _out_wofireMux_T_300; // @[RegisterRouter.scala:87:24] assign out_woready_1_270 = _out_wofireMux_T_300; // @[RegisterRouter.scala:87:24] assign out_woready_1_271 = _out_wofireMux_T_300; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_301 = ~_out_T_1667; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_303 = _out_wofireMux_T_262 & out_backSel_10_1; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_304 = _out_wofireMux_T_303 & _out_T_1725; // @[RegisterRouter.scala:87:24] assign out_woready_1_483 = _out_wofireMux_T_304; // @[RegisterRouter.scala:87:24] assign out_woready_1_484 = _out_wofireMux_T_304; // @[RegisterRouter.scala:87:24] assign out_woready_1_485 = _out_wofireMux_T_304; // @[RegisterRouter.scala:87:24] assign out_woready_1_486 = _out_wofireMux_T_304; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_305 = ~_out_T_1725; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_307 = _out_wofireMux_T_262 & out_backSel_11_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_308 = _out_wofireMux_T_307; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_311 = _out_wofireMux_T_262 & out_backSel_12_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_312 = _out_wofireMux_T_311; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_315 = _out_wofireMux_T_262 & out_backSel_13_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_316 = _out_wofireMux_T_315; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_319 = _out_wofireMux_T_262 & out_backSel_14_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_320 = _out_wofireMux_T_319; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_323 = _out_wofireMux_T_262 & out_backSel_15_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_324 = _out_wofireMux_T_323; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_327 = _out_wofireMux_T_262 & out_backSel_16_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_328 = _out_wofireMux_T_327; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_331 = _out_wofireMux_T_262 & out_backSel_17_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_332 = _out_wofireMux_T_331; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_335 = _out_wofireMux_T_262 & out_backSel_18_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_336 = _out_wofireMux_T_335; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_339 = _out_wofireMux_T_262 & out_backSel_19_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_340 = _out_wofireMux_T_339; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_343 = _out_wofireMux_T_262 & out_backSel_20_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_344 = _out_wofireMux_T_343; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_347 = _out_wofireMux_T_262 & out_backSel_21_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_348 = _out_wofireMux_T_347; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_351 = _out_wofireMux_T_262 & out_backSel_22_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_352 = _out_wofireMux_T_351; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_355 = _out_wofireMux_T_262 & out_backSel_23_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_356 = _out_wofireMux_T_355; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_359 = _out_wofireMux_T_262 & out_backSel_24_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_360 = _out_wofireMux_T_359; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_363 = _out_wofireMux_T_262 & out_backSel_25_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_364 = _out_wofireMux_T_363; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_367 = _out_wofireMux_T_262 & out_backSel_26_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_368 = _out_wofireMux_T_367; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_371 = _out_wofireMux_T_262 & out_backSel_27_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_372 = _out_wofireMux_T_371; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_375 = _out_wofireMux_T_262 & out_backSel_28_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_376 = _out_wofireMux_T_375; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_379 = _out_wofireMux_T_262 & out_backSel_29_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_380 = _out_wofireMux_T_379; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_383 = _out_wofireMux_T_262 & out_backSel_30_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_384 = _out_wofireMux_T_383; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_387 = _out_wofireMux_T_262 & out_backSel_31_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_388 = _out_wofireMux_T_387; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_391 = _out_wofireMux_T_262 & out_backSel_32_1; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_392 = _out_wofireMux_T_391 & _out_T_1739; // @[RegisterRouter.scala:87:24] assign out_woready_1_535 = _out_wofireMux_T_392; // @[RegisterRouter.scala:87:24] assign out_woready_1_536 = _out_wofireMux_T_392; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_393 = ~_out_T_1739; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_395 = _out_wofireMux_T_262 & out_backSel_33_1; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_396 = _out_wofireMux_T_395 & _out_T_1689; // @[RegisterRouter.scala:87:24] assign out_woready_1_352 = _out_wofireMux_T_396; // @[RegisterRouter.scala:87:24] assign out_woready_1_353 = _out_wofireMux_T_396; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_397 = ~_out_T_1689; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_399 = _out_wofireMux_T_262 & out_backSel_34_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_400 = _out_wofireMux_T_399; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_403 = _out_wofireMux_T_262 & out_backSel_35_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_404 = _out_wofireMux_T_403; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_407 = _out_wofireMux_T_262 & out_backSel_36_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_408 = _out_wofireMux_T_407; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_411 = _out_wofireMux_T_262 & out_backSel_37_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_412 = _out_wofireMux_T_411; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_415 = _out_wofireMux_T_262 & out_backSel_38_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_416 = _out_wofireMux_T_415; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_419 = _out_wofireMux_T_262 & out_backSel_39_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_420 = _out_wofireMux_T_419; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_423 = _out_wofireMux_T_262 & out_backSel_40_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_424 = _out_wofireMux_T_423; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_427 = _out_wofireMux_T_262 & out_backSel_41_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_428 = _out_wofireMux_T_427; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_431 = _out_wofireMux_T_262 & out_backSel_42_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_432 = _out_wofireMux_T_431; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_435 = _out_wofireMux_T_262 & out_backSel_43_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_436 = _out_wofireMux_T_435; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_439 = _out_wofireMux_T_262 & out_backSel_44_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_440 = _out_wofireMux_T_439; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_443 = _out_wofireMux_T_262 & out_backSel_45_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_444 = _out_wofireMux_T_443; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_447 = _out_wofireMux_T_262 & out_backSel_46_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_448 = _out_wofireMux_T_447; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_451 = _out_wofireMux_T_262 & out_backSel_47_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_452 = _out_wofireMux_T_451; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_455 = _out_wofireMux_T_262 & out_backSel_48_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_456 = _out_wofireMux_T_455; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_459 = _out_wofireMux_T_262 & out_backSel_49_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_460 = _out_wofireMux_T_459; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_463 = _out_wofireMux_T_262 & out_backSel_50_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_464 = _out_wofireMux_T_463; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_467 = _out_wofireMux_T_262 & out_backSel_51_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_468 = _out_wofireMux_T_467; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_471 = _out_wofireMux_T_262 & out_backSel_52_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_472 = _out_wofireMux_T_471; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_475 = _out_wofireMux_T_262 & out_backSel_53_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_476 = _out_wofireMux_T_475; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_479 = _out_wofireMux_T_262 & out_backSel_54_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_480 = _out_wofireMux_T_479; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_483 = _out_wofireMux_T_262 & out_backSel_55_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_484 = _out_wofireMux_T_483; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_487 = _out_wofireMux_T_262 & out_backSel_56_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_488 = _out_wofireMux_T_487; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_491 = _out_wofireMux_T_262 & out_backSel_57_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_492 = _out_wofireMux_T_491; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_495 = _out_wofireMux_T_262 & out_backSel_58_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_496 = _out_wofireMux_T_495; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_499 = _out_wofireMux_T_262 & out_backSel_59_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_500 = _out_wofireMux_T_499; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_503 = _out_wofireMux_T_262 & out_backSel_60_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_504 = _out_wofireMux_T_503; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_507 = _out_wofireMux_T_262 & out_backSel_61_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_508 = _out_wofireMux_T_507; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_511 = _out_wofireMux_T_262 & out_backSel_62_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_512 = _out_wofireMux_T_511; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_515 = _out_wofireMux_T_262 & out_backSel_63_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_516 = _out_wofireMux_T_515; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_519 = _out_wofireMux_T_262 & out_backSel_64; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_520 = _out_wofireMux_T_519; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_523 = _out_wofireMux_T_262 & out_backSel_65; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_524 = _out_wofireMux_T_523; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_527 = _out_wofireMux_T_262 & out_backSel_66; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_528 = _out_wofireMux_T_527; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_531 = _out_wofireMux_T_262 & out_backSel_67; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_532 = _out_wofireMux_T_531; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_535 = _out_wofireMux_T_262 & out_backSel_68; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_536 = _out_wofireMux_T_535; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_539 = _out_wofireMux_T_262 & out_backSel_69; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_540 = _out_wofireMux_T_539; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_543 = _out_wofireMux_T_262 & out_backSel_70; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_544 = _out_wofireMux_T_543; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_547 = _out_wofireMux_T_262 & out_backSel_71; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_548 = _out_wofireMux_T_547; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_551 = _out_wofireMux_T_262 & out_backSel_72; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_552 = _out_wofireMux_T_551; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_555 = _out_wofireMux_T_262 & out_backSel_73; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_556 = _out_wofireMux_T_555; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_559 = _out_wofireMux_T_262 & out_backSel_74; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_560 = _out_wofireMux_T_559; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_563 = _out_wofireMux_T_262 & out_backSel_75; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_564 = _out_wofireMux_T_563; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_567 = _out_wofireMux_T_262 & out_backSel_76; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_568 = _out_wofireMux_T_567; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_571 = _out_wofireMux_T_262 & out_backSel_77; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_572 = _out_wofireMux_T_571; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_575 = _out_wofireMux_T_262 & out_backSel_78; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_576 = _out_wofireMux_T_575; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_579 = _out_wofireMux_T_262 & out_backSel_79; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_580 = _out_wofireMux_T_579; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_583 = _out_wofireMux_T_262 & out_backSel_80; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_584 = _out_wofireMux_T_583; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_587 = _out_wofireMux_T_262 & out_backSel_81; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_588 = _out_wofireMux_T_587; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_591 = _out_wofireMux_T_262 & out_backSel_82; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_592 = _out_wofireMux_T_591; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_595 = _out_wofireMux_T_262 & out_backSel_83; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_596 = _out_wofireMux_T_595; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_599 = _out_wofireMux_T_262 & out_backSel_84; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_600 = _out_wofireMux_T_599; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_603 = _out_wofireMux_T_262 & out_backSel_85; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_604 = _out_wofireMux_T_603; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_607 = _out_wofireMux_T_262 & out_backSel_86; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_608 = _out_wofireMux_T_607; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_611 = _out_wofireMux_T_262 & out_backSel_87; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_612 = _out_wofireMux_T_611; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_615 = _out_wofireMux_T_262 & out_backSel_88; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_616 = _out_wofireMux_T_615; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_619 = _out_wofireMux_T_262 & out_backSel_89; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_620 = _out_wofireMux_T_619; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_623 = _out_wofireMux_T_262 & out_backSel_90; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_624 = _out_wofireMux_T_623; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_627 = _out_wofireMux_T_262 & out_backSel_91; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_628 = _out_wofireMux_T_627; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_631 = _out_wofireMux_T_262 & out_backSel_92; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_632 = _out_wofireMux_T_631; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_635 = _out_wofireMux_T_262 & out_backSel_93; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_636 = _out_wofireMux_T_635; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_639 = _out_wofireMux_T_262 & out_backSel_94; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_640 = _out_wofireMux_T_639; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_643 = _out_wofireMux_T_262 & out_backSel_95; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_644 = _out_wofireMux_T_643; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_647 = _out_wofireMux_T_262 & out_backSel_96; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_648 = _out_wofireMux_T_647 & _out_T_1713; // @[RegisterRouter.scala:87:24] assign out_woready_1_442 = _out_wofireMux_T_648; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_649 = ~_out_T_1713; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_651 = _out_wofireMux_T_262 & out_backSel_97; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_652 = _out_wofireMux_T_651; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_655 = _out_wofireMux_T_262 & out_backSel_98; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_656 = _out_wofireMux_T_655; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_659 = _out_wofireMux_T_262 & out_backSel_99; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_660 = _out_wofireMux_T_659; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_663 = _out_wofireMux_T_262 & out_backSel_100; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_664 = _out_wofireMux_T_663; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_667 = _out_wofireMux_T_262 & out_backSel_101; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_668 = _out_wofireMux_T_667; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_671 = _out_wofireMux_T_262 & out_backSel_102; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_672 = _out_wofireMux_T_671; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_675 = _out_wofireMux_T_262 & out_backSel_103; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_676 = _out_wofireMux_T_675 & _out_T_1781; // @[RegisterRouter.scala:87:24] assign out_woready_1_697 = _out_wofireMux_T_676; // @[RegisterRouter.scala:87:24] assign out_woready_1_698 = _out_wofireMux_T_676; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_677 = ~_out_T_1781; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_679 = _out_wofireMux_T_262 & out_backSel_104; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_680 = _out_wofireMux_T_679 & _out_T_1841; // @[RegisterRouter.scala:87:24] assign out_woready_1_931 = _out_wofireMux_T_680; // @[RegisterRouter.scala:87:24] assign out_woready_1_932 = _out_wofireMux_T_680; // @[RegisterRouter.scala:87:24] assign out_woready_1_933 = _out_wofireMux_T_680; // @[RegisterRouter.scala:87:24] assign out_woready_1_934 = _out_wofireMux_T_680; // @[RegisterRouter.scala:87:24] assign out_woready_1_935 = _out_wofireMux_T_680; // @[RegisterRouter.scala:87:24] assign out_woready_1_936 = _out_wofireMux_T_680; // @[RegisterRouter.scala:87:24] assign out_woready_1_937 = _out_wofireMux_T_680; // @[RegisterRouter.scala:87:24] assign out_woready_1_938 = _out_wofireMux_T_680; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_681 = ~_out_T_1841; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_683 = _out_wofireMux_T_262 & out_backSel_105; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_684 = _out_wofireMux_T_683 & _out_T_1733; // @[RegisterRouter.scala:87:24] assign out_woready_1_511 = _out_wofireMux_T_684; // @[RegisterRouter.scala:87:24] assign out_woready_1_512 = _out_wofireMux_T_684; // @[RegisterRouter.scala:87:24] assign out_woready_1_513 = _out_wofireMux_T_684; // @[RegisterRouter.scala:87:24] assign out_woready_1_514 = _out_wofireMux_T_684; // @[RegisterRouter.scala:87:24] assign out_woready_1_515 = _out_wofireMux_T_684; // @[RegisterRouter.scala:87:24] assign out_woready_1_516 = _out_wofireMux_T_684; // @[RegisterRouter.scala:87:24] assign out_woready_1_517 = _out_wofireMux_T_684; // @[RegisterRouter.scala:87:24] assign out_woready_1_518 = _out_wofireMux_T_684; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_685 = ~_out_T_1733; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_687 = _out_wofireMux_T_262 & out_backSel_106; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_688 = _out_wofireMux_T_687 & _out_T_1649; // @[RegisterRouter.scala:87:24] assign out_woready_1_192 = _out_wofireMux_T_688; // @[RegisterRouter.scala:87:24] assign out_woready_1_193 = _out_wofireMux_T_688; // @[RegisterRouter.scala:87:24] assign out_woready_1_194 = _out_wofireMux_T_688; // @[RegisterRouter.scala:87:24] assign out_woready_1_195 = _out_wofireMux_T_688; // @[RegisterRouter.scala:87:24] assign out_woready_1_196 = _out_wofireMux_T_688; // @[RegisterRouter.scala:87:24] assign out_woready_1_197 = _out_wofireMux_T_688; // @[RegisterRouter.scala:87:24] assign out_woready_1_198 = _out_wofireMux_T_688; // @[RegisterRouter.scala:87:24] assign out_woready_1_199 = _out_wofireMux_T_688; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_689 = ~_out_T_1649; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_691 = _out_wofireMux_T_262 & out_backSel_107; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_692 = _out_wofireMux_T_691 & _out_T_1881; // @[RegisterRouter.scala:87:24] assign out_woready_1_1091 = _out_wofireMux_T_692; // @[RegisterRouter.scala:87:24] assign out_woready_1_1092 = _out_wofireMux_T_692; // @[RegisterRouter.scala:87:24] assign out_woready_1_1093 = _out_wofireMux_T_692; // @[RegisterRouter.scala:87:24] assign out_woready_1_1094 = _out_wofireMux_T_692; // @[RegisterRouter.scala:87:24] assign out_woready_1_1095 = _out_wofireMux_T_692; // @[RegisterRouter.scala:87:24] assign out_woready_1_1096 = _out_wofireMux_T_692; // @[RegisterRouter.scala:87:24] assign out_woready_1_1097 = _out_wofireMux_T_692; // @[RegisterRouter.scala:87:24] assign out_woready_1_1098 = _out_wofireMux_T_692; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_693 = ~_out_T_1881; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_695 = _out_wofireMux_T_262 & out_backSel_108; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_696 = _out_wofireMux_T_695 & _out_T_1791; // @[RegisterRouter.scala:87:24] assign out_woready_1_731 = _out_wofireMux_T_696; // @[RegisterRouter.scala:87:24] assign out_woready_1_732 = _out_wofireMux_T_696; // @[RegisterRouter.scala:87:24] assign out_woready_1_733 = _out_wofireMux_T_696; // @[RegisterRouter.scala:87:24] assign out_woready_1_734 = _out_wofireMux_T_696; // @[RegisterRouter.scala:87:24] assign out_woready_1_735 = _out_wofireMux_T_696; // @[RegisterRouter.scala:87:24] assign out_woready_1_736 = _out_wofireMux_T_696; // @[RegisterRouter.scala:87:24] assign out_woready_1_737 = _out_wofireMux_T_696; // @[RegisterRouter.scala:87:24] assign out_woready_1_738 = _out_wofireMux_T_696; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_697 = ~_out_T_1791; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_699 = _out_wofireMux_T_262 & out_backSel_109; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_700 = _out_wofireMux_T_699 & _out_T_1715; // @[RegisterRouter.scala:87:24] assign out_woready_1_443 = _out_wofireMux_T_700; // @[RegisterRouter.scala:87:24] assign out_woready_1_444 = _out_wofireMux_T_700; // @[RegisterRouter.scala:87:24] assign out_woready_1_445 = _out_wofireMux_T_700; // @[RegisterRouter.scala:87:24] assign out_woready_1_446 = _out_wofireMux_T_700; // @[RegisterRouter.scala:87:24] assign out_woready_1_447 = _out_wofireMux_T_700; // @[RegisterRouter.scala:87:24] assign out_woready_1_448 = _out_wofireMux_T_700; // @[RegisterRouter.scala:87:24] assign out_woready_1_449 = _out_wofireMux_T_700; // @[RegisterRouter.scala:87:24] assign out_woready_1_450 = _out_wofireMux_T_700; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_701 = ~_out_T_1715; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_703 = _out_wofireMux_T_262 & out_backSel_110; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_704 = _out_wofireMux_T_703 & _out_T_1629; // @[RegisterRouter.scala:87:24] assign out_woready_1_112 = _out_wofireMux_T_704; // @[RegisterRouter.scala:87:24] assign out_woready_1_113 = _out_wofireMux_T_704; // @[RegisterRouter.scala:87:24] assign out_woready_1_114 = _out_wofireMux_T_704; // @[RegisterRouter.scala:87:24] assign out_woready_1_115 = _out_wofireMux_T_704; // @[RegisterRouter.scala:87:24] assign out_woready_1_116 = _out_wofireMux_T_704; // @[RegisterRouter.scala:87:24] assign out_woready_1_117 = _out_wofireMux_T_704; // @[RegisterRouter.scala:87:24] assign out_woready_1_118 = _out_wofireMux_T_704; // @[RegisterRouter.scala:87:24] assign out_woready_1_119 = _out_wofireMux_T_704; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_705 = ~_out_T_1629; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_707 = _out_wofireMux_T_262 & out_backSel_111; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_708 = _out_wofireMux_T_707 & _out_T_1899; // @[RegisterRouter.scala:87:24] assign out_woready_1_1163 = _out_wofireMux_T_708; // @[RegisterRouter.scala:87:24] assign out_woready_1_1164 = _out_wofireMux_T_708; // @[RegisterRouter.scala:87:24] assign out_woready_1_1165 = _out_wofireMux_T_708; // @[RegisterRouter.scala:87:24] assign out_woready_1_1166 = _out_wofireMux_T_708; // @[RegisterRouter.scala:87:24] assign out_woready_1_1167 = _out_wofireMux_T_708; // @[RegisterRouter.scala:87:24] assign out_woready_1_1168 = _out_wofireMux_T_708; // @[RegisterRouter.scala:87:24] assign out_woready_1_1169 = _out_wofireMux_T_708; // @[RegisterRouter.scala:87:24] assign out_woready_1_1170 = _out_wofireMux_T_708; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_709 = ~_out_T_1899; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_711 = _out_wofireMux_T_262 & out_backSel_112; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_712 = _out_wofireMux_T_711 & _out_T_1815; // @[RegisterRouter.scala:87:24] assign out_woready_1_827 = _out_wofireMux_T_712; // @[RegisterRouter.scala:87:24] assign out_woready_1_828 = _out_wofireMux_T_712; // @[RegisterRouter.scala:87:24] assign out_woready_1_829 = _out_wofireMux_T_712; // @[RegisterRouter.scala:87:24] assign out_woready_1_830 = _out_wofireMux_T_712; // @[RegisterRouter.scala:87:24] assign out_woready_1_831 = _out_wofireMux_T_712; // @[RegisterRouter.scala:87:24] assign out_woready_1_832 = _out_wofireMux_T_712; // @[RegisterRouter.scala:87:24] assign out_woready_1_833 = _out_wofireMux_T_712; // @[RegisterRouter.scala:87:24] assign out_woready_1_834 = _out_wofireMux_T_712; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_713 = ~_out_T_1815; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_715 = _out_wofireMux_T_262 & out_backSel_113; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_716 = _out_wofireMux_T_715 & _out_T_1771; // @[RegisterRouter.scala:87:24] assign out_woready_1_657 = _out_wofireMux_T_716; // @[RegisterRouter.scala:87:24] assign out_woready_1_658 = _out_wofireMux_T_716; // @[RegisterRouter.scala:87:24] assign out_woready_1_659 = _out_wofireMux_T_716; // @[RegisterRouter.scala:87:24] assign out_woready_1_660 = _out_wofireMux_T_716; // @[RegisterRouter.scala:87:24] assign out_woready_1_661 = _out_wofireMux_T_716; // @[RegisterRouter.scala:87:24] assign out_woready_1_662 = _out_wofireMux_T_716; // @[RegisterRouter.scala:87:24] assign out_woready_1_663 = _out_wofireMux_T_716; // @[RegisterRouter.scala:87:24] assign out_woready_1_664 = _out_wofireMux_T_716; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_717 = ~_out_T_1771; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_719 = _out_wofireMux_T_262 & out_backSel_114; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_720 = _out_wofireMux_T_719 & _out_T_1853; // @[RegisterRouter.scala:87:24] assign out_woready_1_979 = _out_wofireMux_T_720; // @[RegisterRouter.scala:87:24] assign out_woready_1_980 = _out_wofireMux_T_720; // @[RegisterRouter.scala:87:24] assign out_woready_1_981 = _out_wofireMux_T_720; // @[RegisterRouter.scala:87:24] assign out_woready_1_982 = _out_wofireMux_T_720; // @[RegisterRouter.scala:87:24] assign out_woready_1_983 = _out_wofireMux_T_720; // @[RegisterRouter.scala:87:24] assign out_woready_1_984 = _out_wofireMux_T_720; // @[RegisterRouter.scala:87:24] assign out_woready_1_985 = _out_wofireMux_T_720; // @[RegisterRouter.scala:87:24] assign out_woready_1_986 = _out_wofireMux_T_720; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_721 = ~_out_T_1853; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_723 = _out_wofireMux_T_262 & out_backSel_115; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_724 = _out_wofireMux_T_723 & _out_T_1609; // @[RegisterRouter.scala:87:24] assign out_woready_1_32 = _out_wofireMux_T_724; // @[RegisterRouter.scala:87:24] assign out_woready_1_33 = _out_wofireMux_T_724; // @[RegisterRouter.scala:87:24] assign out_woready_1_34 = _out_wofireMux_T_724; // @[RegisterRouter.scala:87:24] assign out_woready_1_35 = _out_wofireMux_T_724; // @[RegisterRouter.scala:87:24] assign out_woready_1_36 = _out_wofireMux_T_724; // @[RegisterRouter.scala:87:24] assign out_woready_1_37 = _out_wofireMux_T_724; // @[RegisterRouter.scala:87:24] assign out_woready_1_38 = _out_wofireMux_T_724; // @[RegisterRouter.scala:87:24] assign out_woready_1_39 = _out_wofireMux_T_724; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_725 = ~_out_T_1609; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_727 = _out_wofireMux_T_262 & out_backSel_116; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_728 = _out_wofireMux_T_727; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_731 = _out_wofireMux_T_262 & out_backSel_117; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_732 = _out_wofireMux_T_731; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_735 = _out_wofireMux_T_262 & out_backSel_118; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_736 = _out_wofireMux_T_735; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_739 = _out_wofireMux_T_262 & out_backSel_119; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_740 = _out_wofireMux_T_739; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_743 = _out_wofireMux_T_262 & out_backSel_120; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_744 = _out_wofireMux_T_743; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_747 = _out_wofireMux_T_262 & out_backSel_121; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_748 = _out_wofireMux_T_747; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_751 = _out_wofireMux_T_262 & out_backSel_122; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_752 = _out_wofireMux_T_751; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_755 = _out_wofireMux_T_262 & out_backSel_123; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_756 = _out_wofireMux_T_755; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_759 = _out_wofireMux_T_262 & out_backSel_124; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_760 = _out_wofireMux_T_759; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_763 = _out_wofireMux_T_262 & out_backSel_125; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_764 = _out_wofireMux_T_763; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_767 = _out_wofireMux_T_262 & out_backSel_126; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_768 = _out_wofireMux_T_767; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_771 = _out_wofireMux_T_262 & out_backSel_127; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_772 = _out_wofireMux_T_771; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_775 = _out_wofireMux_T_262 & out_backSel_128; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_776 = _out_wofireMux_T_775 & _out_T_1729; // @[RegisterRouter.scala:87:24] assign out_woready_1_495 = _out_wofireMux_T_776; // @[RegisterRouter.scala:87:24] assign out_woready_1_496 = _out_wofireMux_T_776; // @[RegisterRouter.scala:87:24] assign out_woready_1_497 = _out_wofireMux_T_776; // @[RegisterRouter.scala:87:24] assign out_woready_1_498 = _out_wofireMux_T_776; // @[RegisterRouter.scala:87:24] assign out_woready_1_499 = _out_wofireMux_T_776; // @[RegisterRouter.scala:87:24] assign out_woready_1_500 = _out_wofireMux_T_776; // @[RegisterRouter.scala:87:24] assign out_woready_1_501 = _out_wofireMux_T_776; // @[RegisterRouter.scala:87:24] assign out_woready_1_502 = _out_wofireMux_T_776; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_777 = ~_out_T_1729; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_779 = _out_wofireMux_T_262 & out_backSel_129; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_780 = _out_wofireMux_T_779 & _out_T_1721; // @[RegisterRouter.scala:87:24] assign out_woready_1_467 = _out_wofireMux_T_780; // @[RegisterRouter.scala:87:24] assign out_woready_1_468 = _out_wofireMux_T_780; // @[RegisterRouter.scala:87:24] assign out_woready_1_469 = _out_wofireMux_T_780; // @[RegisterRouter.scala:87:24] assign out_woready_1_470 = _out_wofireMux_T_780; // @[RegisterRouter.scala:87:24] assign out_woready_1_471 = _out_wofireMux_T_780; // @[RegisterRouter.scala:87:24] assign out_woready_1_472 = _out_wofireMux_T_780; // @[RegisterRouter.scala:87:24] assign out_woready_1_473 = _out_wofireMux_T_780; // @[RegisterRouter.scala:87:24] assign out_woready_1_474 = _out_wofireMux_T_780; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_781 = ~_out_T_1721; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_783 = _out_wofireMux_T_262 & out_backSel_130; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_784 = _out_wofireMux_T_783 & _out_T_1797; // @[RegisterRouter.scala:87:24] assign out_woready_1_755 = _out_wofireMux_T_784; // @[RegisterRouter.scala:87:24] assign out_woready_1_756 = _out_wofireMux_T_784; // @[RegisterRouter.scala:87:24] assign out_woready_1_757 = _out_wofireMux_T_784; // @[RegisterRouter.scala:87:24] assign out_woready_1_758 = _out_wofireMux_T_784; // @[RegisterRouter.scala:87:24] assign out_woready_1_759 = _out_wofireMux_T_784; // @[RegisterRouter.scala:87:24] assign out_woready_1_760 = _out_wofireMux_T_784; // @[RegisterRouter.scala:87:24] assign out_woready_1_761 = _out_wofireMux_T_784; // @[RegisterRouter.scala:87:24] assign out_woready_1_762 = _out_wofireMux_T_784; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_785 = ~_out_T_1797; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_787 = _out_wofireMux_T_262 & out_backSel_131; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_788 = _out_wofireMux_T_787 & _out_T_1891; // @[RegisterRouter.scala:87:24] assign out_woready_1_1131 = _out_wofireMux_T_788; // @[RegisterRouter.scala:87:24] assign out_woready_1_1132 = _out_wofireMux_T_788; // @[RegisterRouter.scala:87:24] assign out_woready_1_1133 = _out_wofireMux_T_788; // @[RegisterRouter.scala:87:24] assign out_woready_1_1134 = _out_wofireMux_T_788; // @[RegisterRouter.scala:87:24] assign out_woready_1_1135 = _out_wofireMux_T_788; // @[RegisterRouter.scala:87:24] assign out_woready_1_1136 = _out_wofireMux_T_788; // @[RegisterRouter.scala:87:24] assign out_woready_1_1137 = _out_wofireMux_T_788; // @[RegisterRouter.scala:87:24] assign out_woready_1_1138 = _out_wofireMux_T_788; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_789 = ~_out_T_1891; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_791 = _out_wofireMux_T_262 & out_backSel_132; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_792 = _out_wofireMux_T_791 & _out_T_1661; // @[RegisterRouter.scala:87:24] assign out_woready_1_240 = _out_wofireMux_T_792; // @[RegisterRouter.scala:87:24] assign out_woready_1_241 = _out_wofireMux_T_792; // @[RegisterRouter.scala:87:24] assign out_woready_1_242 = _out_wofireMux_T_792; // @[RegisterRouter.scala:87:24] assign out_woready_1_243 = _out_wofireMux_T_792; // @[RegisterRouter.scala:87:24] assign out_woready_1_244 = _out_wofireMux_T_792; // @[RegisterRouter.scala:87:24] assign out_woready_1_245 = _out_wofireMux_T_792; // @[RegisterRouter.scala:87:24] assign out_woready_1_246 = _out_wofireMux_T_792; // @[RegisterRouter.scala:87:24] assign out_woready_1_247 = _out_wofireMux_T_792; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_793 = ~_out_T_1661; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_795 = _out_wofireMux_T_262 & out_backSel_133; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_796 = _out_wofireMux_T_795 & _out_T_1663; // @[RegisterRouter.scala:87:24] assign out_woready_1_248 = _out_wofireMux_T_796; // @[RegisterRouter.scala:87:24] assign out_woready_1_249 = _out_wofireMux_T_796; // @[RegisterRouter.scala:87:24] assign out_woready_1_250 = _out_wofireMux_T_796; // @[RegisterRouter.scala:87:24] assign out_woready_1_251 = _out_wofireMux_T_796; // @[RegisterRouter.scala:87:24] assign out_woready_1_252 = _out_wofireMux_T_796; // @[RegisterRouter.scala:87:24] assign out_woready_1_253 = _out_wofireMux_T_796; // @[RegisterRouter.scala:87:24] assign out_woready_1_254 = _out_wofireMux_T_796; // @[RegisterRouter.scala:87:24] assign out_woready_1_255 = _out_wofireMux_T_796; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_797 = ~_out_T_1663; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_799 = _out_wofireMux_T_262 & out_backSel_134; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_800 = _out_wofireMux_T_799 & _out_T_1723; // @[RegisterRouter.scala:87:24] assign out_woready_1_475 = _out_wofireMux_T_800; // @[RegisterRouter.scala:87:24] assign out_woready_1_476 = _out_wofireMux_T_800; // @[RegisterRouter.scala:87:24] assign out_woready_1_477 = _out_wofireMux_T_800; // @[RegisterRouter.scala:87:24] assign out_woready_1_478 = _out_wofireMux_T_800; // @[RegisterRouter.scala:87:24] assign out_woready_1_479 = _out_wofireMux_T_800; // @[RegisterRouter.scala:87:24] assign out_woready_1_480 = _out_wofireMux_T_800; // @[RegisterRouter.scala:87:24] assign out_woready_1_481 = _out_wofireMux_T_800; // @[RegisterRouter.scala:87:24] assign out_woready_1_482 = _out_wofireMux_T_800; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_801 = ~_out_T_1723; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_803 = _out_wofireMux_T_262 & out_backSel_135; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_804 = _out_wofireMux_T_803 & _out_T_1801; // @[RegisterRouter.scala:87:24] assign out_woready_1_771 = _out_wofireMux_T_804; // @[RegisterRouter.scala:87:24] assign out_woready_1_772 = _out_wofireMux_T_804; // @[RegisterRouter.scala:87:24] assign out_woready_1_773 = _out_wofireMux_T_804; // @[RegisterRouter.scala:87:24] assign out_woready_1_774 = _out_wofireMux_T_804; // @[RegisterRouter.scala:87:24] assign out_woready_1_775 = _out_wofireMux_T_804; // @[RegisterRouter.scala:87:24] assign out_woready_1_776 = _out_wofireMux_T_804; // @[RegisterRouter.scala:87:24] assign out_woready_1_777 = _out_wofireMux_T_804; // @[RegisterRouter.scala:87:24] assign out_woready_1_778 = _out_wofireMux_T_804; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_805 = ~_out_T_1801; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_807 = _out_wofireMux_T_262 & out_backSel_136; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_808 = _out_wofireMux_T_807 & _out_T_1883; // @[RegisterRouter.scala:87:24] assign out_woready_1_1099 = _out_wofireMux_T_808; // @[RegisterRouter.scala:87:24] assign out_woready_1_1100 = _out_wofireMux_T_808; // @[RegisterRouter.scala:87:24] assign out_woready_1_1101 = _out_wofireMux_T_808; // @[RegisterRouter.scala:87:24] assign out_woready_1_1102 = _out_wofireMux_T_808; // @[RegisterRouter.scala:87:24] assign out_woready_1_1103 = _out_wofireMux_T_808; // @[RegisterRouter.scala:87:24] assign out_woready_1_1104 = _out_wofireMux_T_808; // @[RegisterRouter.scala:87:24] assign out_woready_1_1105 = _out_wofireMux_T_808; // @[RegisterRouter.scala:87:24] assign out_woready_1_1106 = _out_wofireMux_T_808; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_809 = ~_out_T_1883; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_811 = _out_wofireMux_T_262 & out_backSel_137; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_812 = _out_wofireMux_T_811 & _out_T_1685; // @[RegisterRouter.scala:87:24] assign out_woready_1_336 = _out_wofireMux_T_812; // @[RegisterRouter.scala:87:24] assign out_woready_1_337 = _out_wofireMux_T_812; // @[RegisterRouter.scala:87:24] assign out_woready_1_338 = _out_wofireMux_T_812; // @[RegisterRouter.scala:87:24] assign out_woready_1_339 = _out_wofireMux_T_812; // @[RegisterRouter.scala:87:24] assign out_woready_1_340 = _out_wofireMux_T_812; // @[RegisterRouter.scala:87:24] assign out_woready_1_341 = _out_wofireMux_T_812; // @[RegisterRouter.scala:87:24] assign out_woready_1_342 = _out_wofireMux_T_812; // @[RegisterRouter.scala:87:24] assign out_woready_1_343 = _out_wofireMux_T_812; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_813 = ~_out_T_1685; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_815 = _out_wofireMux_T_262 & out_backSel_138; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_816 = _out_wofireMux_T_815 & _out_T_1601; // @[RegisterRouter.scala:87:24] assign out_woready_1_0 = _out_wofireMux_T_816; // @[RegisterRouter.scala:87:24] assign out_woready_1_1 = _out_wofireMux_T_816; // @[RegisterRouter.scala:87:24] assign out_woready_1_2 = _out_wofireMux_T_816; // @[RegisterRouter.scala:87:24] assign out_woready_1_3 = _out_wofireMux_T_816; // @[RegisterRouter.scala:87:24] assign out_woready_1_4 = _out_wofireMux_T_816; // @[RegisterRouter.scala:87:24] assign out_woready_1_5 = _out_wofireMux_T_816; // @[RegisterRouter.scala:87:24] assign out_woready_1_6 = _out_wofireMux_T_816; // @[RegisterRouter.scala:87:24] assign out_woready_1_7 = _out_wofireMux_T_816; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_817 = ~_out_T_1601; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_819 = _out_wofireMux_T_262 & out_backSel_139; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_820 = _out_wofireMux_T_819 & _out_T_1857; // @[RegisterRouter.scala:87:24] assign out_woready_1_995 = _out_wofireMux_T_820; // @[RegisterRouter.scala:87:24] assign out_woready_1_996 = _out_wofireMux_T_820; // @[RegisterRouter.scala:87:24] assign out_woready_1_997 = _out_wofireMux_T_820; // @[RegisterRouter.scala:87:24] assign out_woready_1_998 = _out_wofireMux_T_820; // @[RegisterRouter.scala:87:24] assign out_woready_1_999 = _out_wofireMux_T_820; // @[RegisterRouter.scala:87:24] assign out_woready_1_1000 = _out_wofireMux_T_820; // @[RegisterRouter.scala:87:24] assign out_woready_1_1001 = _out_wofireMux_T_820; // @[RegisterRouter.scala:87:24] assign out_woready_1_1002 = _out_wofireMux_T_820; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_821 = ~_out_T_1857; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_823 = _out_wofireMux_T_262 & out_backSel_140; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_824 = _out_wofireMux_T_823 & _out_T_1783; // @[RegisterRouter.scala:87:24] assign out_woready_1_699 = _out_wofireMux_T_824; // @[RegisterRouter.scala:87:24] assign out_woready_1_700 = _out_wofireMux_T_824; // @[RegisterRouter.scala:87:24] assign out_woready_1_701 = _out_wofireMux_T_824; // @[RegisterRouter.scala:87:24] assign out_woready_1_702 = _out_wofireMux_T_824; // @[RegisterRouter.scala:87:24] assign out_woready_1_703 = _out_wofireMux_T_824; // @[RegisterRouter.scala:87:24] assign out_woready_1_704 = _out_wofireMux_T_824; // @[RegisterRouter.scala:87:24] assign out_woready_1_705 = _out_wofireMux_T_824; // @[RegisterRouter.scala:87:24] assign out_woready_1_706 = _out_wofireMux_T_824; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_825 = ~_out_T_1783; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_827 = _out_wofireMux_T_262 & out_backSel_141; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_828 = _out_wofireMux_T_827 & _out_T_1705; // @[RegisterRouter.scala:87:24] assign out_woready_1_410 = _out_wofireMux_T_828; // @[RegisterRouter.scala:87:24] assign out_woready_1_411 = _out_wofireMux_T_828; // @[RegisterRouter.scala:87:24] assign out_woready_1_412 = _out_wofireMux_T_828; // @[RegisterRouter.scala:87:24] assign out_woready_1_413 = _out_wofireMux_T_828; // @[RegisterRouter.scala:87:24] assign out_woready_1_414 = _out_wofireMux_T_828; // @[RegisterRouter.scala:87:24] assign out_woready_1_415 = _out_wofireMux_T_828; // @[RegisterRouter.scala:87:24] assign out_woready_1_416 = _out_wofireMux_T_828; // @[RegisterRouter.scala:87:24] assign out_woready_1_417 = _out_wofireMux_T_828; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_829 = ~_out_T_1705; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_831 = _out_wofireMux_T_262 & out_backSel_142; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_832 = _out_wofireMux_T_831 & _out_T_1617; // @[RegisterRouter.scala:87:24] assign out_woready_1_64 = _out_wofireMux_T_832; // @[RegisterRouter.scala:87:24] assign out_woready_1_65 = _out_wofireMux_T_832; // @[RegisterRouter.scala:87:24] assign out_woready_1_66 = _out_wofireMux_T_832; // @[RegisterRouter.scala:87:24] assign out_woready_1_67 = _out_wofireMux_T_832; // @[RegisterRouter.scala:87:24] assign out_woready_1_68 = _out_wofireMux_T_832; // @[RegisterRouter.scala:87:24] assign out_woready_1_69 = _out_wofireMux_T_832; // @[RegisterRouter.scala:87:24] assign out_woready_1_70 = _out_wofireMux_T_832; // @[RegisterRouter.scala:87:24] assign out_woready_1_71 = _out_wofireMux_T_832; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_833 = ~_out_T_1617; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_835 = _out_wofireMux_T_262 & out_backSel_143; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_836 = _out_wofireMux_T_835 & _out_T_1835; // @[RegisterRouter.scala:87:24] assign out_woready_1_907 = _out_wofireMux_T_836; // @[RegisterRouter.scala:87:24] assign out_woready_1_908 = _out_wofireMux_T_836; // @[RegisterRouter.scala:87:24] assign out_woready_1_909 = _out_wofireMux_T_836; // @[RegisterRouter.scala:87:24] assign out_woready_1_910 = _out_wofireMux_T_836; // @[RegisterRouter.scala:87:24] assign out_woready_1_911 = _out_wofireMux_T_836; // @[RegisterRouter.scala:87:24] assign out_woready_1_912 = _out_wofireMux_T_836; // @[RegisterRouter.scala:87:24] assign out_woready_1_913 = _out_wofireMux_T_836; // @[RegisterRouter.scala:87:24] assign out_woready_1_914 = _out_wofireMux_T_836; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_837 = ~_out_T_1835; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_839 = _out_wofireMux_T_262 & out_backSel_144; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_840 = _out_wofireMux_T_839 & _out_T_1759; // @[RegisterRouter.scala:87:24] assign out_woready_1_609 = _out_wofireMux_T_840; // @[RegisterRouter.scala:87:24] assign out_woready_1_610 = _out_wofireMux_T_840; // @[RegisterRouter.scala:87:24] assign out_woready_1_611 = _out_wofireMux_T_840; // @[RegisterRouter.scala:87:24] assign out_woready_1_612 = _out_wofireMux_T_840; // @[RegisterRouter.scala:87:24] assign out_woready_1_613 = _out_wofireMux_T_840; // @[RegisterRouter.scala:87:24] assign out_woready_1_614 = _out_wofireMux_T_840; // @[RegisterRouter.scala:87:24] assign out_woready_1_615 = _out_wofireMux_T_840; // @[RegisterRouter.scala:87:24] assign out_woready_1_616 = _out_wofireMux_T_840; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_841 = ~_out_T_1759; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_843 = _out_wofireMux_T_262 & out_backSel_145; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_844 = _out_wofireMux_T_843 & _out_T_1819; // @[RegisterRouter.scala:87:24] assign out_woready_1_843 = _out_wofireMux_T_844; // @[RegisterRouter.scala:87:24] assign out_woready_1_844 = _out_wofireMux_T_844; // @[RegisterRouter.scala:87:24] assign out_woready_1_845 = _out_wofireMux_T_844; // @[RegisterRouter.scala:87:24] assign out_woready_1_846 = _out_wofireMux_T_844; // @[RegisterRouter.scala:87:24] assign out_woready_1_847 = _out_wofireMux_T_844; // @[RegisterRouter.scala:87:24] assign out_woready_1_848 = _out_wofireMux_T_844; // @[RegisterRouter.scala:87:24] assign out_woready_1_849 = _out_wofireMux_T_844; // @[RegisterRouter.scala:87:24] assign out_woready_1_850 = _out_wofireMux_T_844; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_845 = ~_out_T_1819; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_847 = _out_wofireMux_T_262 & out_backSel_146; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_848 = _out_wofireMux_T_847 & _out_T_1869; // @[RegisterRouter.scala:87:24] assign out_woready_1_1043 = _out_wofireMux_T_848; // @[RegisterRouter.scala:87:24] assign out_woready_1_1044 = _out_wofireMux_T_848; // @[RegisterRouter.scala:87:24] assign out_woready_1_1045 = _out_wofireMux_T_848; // @[RegisterRouter.scala:87:24] assign out_woready_1_1046 = _out_wofireMux_T_848; // @[RegisterRouter.scala:87:24] assign out_woready_1_1047 = _out_wofireMux_T_848; // @[RegisterRouter.scala:87:24] assign out_woready_1_1048 = _out_wofireMux_T_848; // @[RegisterRouter.scala:87:24] assign out_woready_1_1049 = _out_wofireMux_T_848; // @[RegisterRouter.scala:87:24] assign out_woready_1_1050 = _out_wofireMux_T_848; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_849 = ~_out_T_1869; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_851 = _out_wofireMux_T_262 & out_backSel_147; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_852 = _out_wofireMux_T_851 & _out_T_1657; // @[RegisterRouter.scala:87:24] assign out_woready_1_224 = _out_wofireMux_T_852; // @[RegisterRouter.scala:87:24] assign out_woready_1_225 = _out_wofireMux_T_852; // @[RegisterRouter.scala:87:24] assign out_woready_1_226 = _out_wofireMux_T_852; // @[RegisterRouter.scala:87:24] assign out_woready_1_227 = _out_wofireMux_T_852; // @[RegisterRouter.scala:87:24] assign out_woready_1_228 = _out_wofireMux_T_852; // @[RegisterRouter.scala:87:24] assign out_woready_1_229 = _out_wofireMux_T_852; // @[RegisterRouter.scala:87:24] assign out_woready_1_230 = _out_wofireMux_T_852; // @[RegisterRouter.scala:87:24] assign out_woready_1_231 = _out_wofireMux_T_852; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_853 = ~_out_T_1657; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_855 = _out_wofireMux_T_262 & out_backSel_148; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_856 = _out_wofireMux_T_855 & _out_T_1741; // @[RegisterRouter.scala:87:24] assign out_woready_1_537 = _out_wofireMux_T_856; // @[RegisterRouter.scala:87:24] assign out_woready_1_538 = _out_wofireMux_T_856; // @[RegisterRouter.scala:87:24] assign out_woready_1_539 = _out_wofireMux_T_856; // @[RegisterRouter.scala:87:24] assign out_woready_1_540 = _out_wofireMux_T_856; // @[RegisterRouter.scala:87:24] assign out_woready_1_541 = _out_wofireMux_T_856; // @[RegisterRouter.scala:87:24] assign out_woready_1_542 = _out_wofireMux_T_856; // @[RegisterRouter.scala:87:24] assign out_woready_1_543 = _out_wofireMux_T_856; // @[RegisterRouter.scala:87:24] assign out_woready_1_544 = _out_wofireMux_T_856; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_857 = ~_out_T_1741; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_859 = _out_wofireMux_T_262 & out_backSel_149; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_860 = _out_wofireMux_T_859 & _out_T_1749; // @[RegisterRouter.scala:87:24] assign out_woready_1_569 = _out_wofireMux_T_860; // @[RegisterRouter.scala:87:24] assign out_woready_1_570 = _out_wofireMux_T_860; // @[RegisterRouter.scala:87:24] assign out_woready_1_571 = _out_wofireMux_T_860; // @[RegisterRouter.scala:87:24] assign out_woready_1_572 = _out_wofireMux_T_860; // @[RegisterRouter.scala:87:24] assign out_woready_1_573 = _out_wofireMux_T_860; // @[RegisterRouter.scala:87:24] assign out_woready_1_574 = _out_wofireMux_T_860; // @[RegisterRouter.scala:87:24] assign out_woready_1_575 = _out_wofireMux_T_860; // @[RegisterRouter.scala:87:24] assign out_woready_1_576 = _out_wofireMux_T_860; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_861 = ~_out_T_1749; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_863 = _out_wofireMux_T_262 & out_backSel_150; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_864 = _out_wofireMux_T_863 & _out_T_1821; // @[RegisterRouter.scala:87:24] assign out_woready_1_851 = _out_wofireMux_T_864; // @[RegisterRouter.scala:87:24] assign out_woready_1_852 = _out_wofireMux_T_864; // @[RegisterRouter.scala:87:24] assign out_woready_1_853 = _out_wofireMux_T_864; // @[RegisterRouter.scala:87:24] assign out_woready_1_854 = _out_wofireMux_T_864; // @[RegisterRouter.scala:87:24] assign out_woready_1_855 = _out_wofireMux_T_864; // @[RegisterRouter.scala:87:24] assign out_woready_1_856 = _out_wofireMux_T_864; // @[RegisterRouter.scala:87:24] assign out_woready_1_857 = _out_wofireMux_T_864; // @[RegisterRouter.scala:87:24] assign out_woready_1_858 = _out_wofireMux_T_864; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_865 = ~_out_T_1821; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_867 = _out_wofireMux_T_262 & out_backSel_151; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_868 = _out_wofireMux_T_867 & _out_T_1867; // @[RegisterRouter.scala:87:24] assign out_woready_1_1035 = _out_wofireMux_T_868; // @[RegisterRouter.scala:87:24] assign out_woready_1_1036 = _out_wofireMux_T_868; // @[RegisterRouter.scala:87:24] assign out_woready_1_1037 = _out_wofireMux_T_868; // @[RegisterRouter.scala:87:24] assign out_woready_1_1038 = _out_wofireMux_T_868; // @[RegisterRouter.scala:87:24] assign out_woready_1_1039 = _out_wofireMux_T_868; // @[RegisterRouter.scala:87:24] assign out_woready_1_1040 = _out_wofireMux_T_868; // @[RegisterRouter.scala:87:24] assign out_woready_1_1041 = _out_wofireMux_T_868; // @[RegisterRouter.scala:87:24] assign out_woready_1_1042 = _out_wofireMux_T_868; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_869 = ~_out_T_1867; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_871 = _out_wofireMux_T_262 & out_backSel_152; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_872 = _out_wofireMux_T_871 & _out_T_1637; // @[RegisterRouter.scala:87:24] assign out_woready_1_144 = _out_wofireMux_T_872; // @[RegisterRouter.scala:87:24] assign out_woready_1_145 = _out_wofireMux_T_872; // @[RegisterRouter.scala:87:24] assign out_woready_1_146 = _out_wofireMux_T_872; // @[RegisterRouter.scala:87:24] assign out_woready_1_147 = _out_wofireMux_T_872; // @[RegisterRouter.scala:87:24] assign out_woready_1_148 = _out_wofireMux_T_872; // @[RegisterRouter.scala:87:24] assign out_woready_1_149 = _out_wofireMux_T_872; // @[RegisterRouter.scala:87:24] assign out_woready_1_150 = _out_wofireMux_T_872; // @[RegisterRouter.scala:87:24] assign out_woready_1_151 = _out_wofireMux_T_872; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_873 = ~_out_T_1637; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_875 = _out_wofireMux_T_262 & out_backSel_153; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_876 = _out_wofireMux_T_875 & _out_T_1619; // @[RegisterRouter.scala:87:24] assign out_woready_1_72 = _out_wofireMux_T_876; // @[RegisterRouter.scala:87:24] assign out_woready_1_73 = _out_wofireMux_T_876; // @[RegisterRouter.scala:87:24] assign out_woready_1_74 = _out_wofireMux_T_876; // @[RegisterRouter.scala:87:24] assign out_woready_1_75 = _out_wofireMux_T_876; // @[RegisterRouter.scala:87:24] assign out_woready_1_76 = _out_wofireMux_T_876; // @[RegisterRouter.scala:87:24] assign out_woready_1_77 = _out_wofireMux_T_876; // @[RegisterRouter.scala:87:24] assign out_woready_1_78 = _out_wofireMux_T_876; // @[RegisterRouter.scala:87:24] assign out_woready_1_79 = _out_wofireMux_T_876; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_877 = ~_out_T_1619; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_879 = _out_wofireMux_T_262 & out_backSel_154; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_880 = _out_wofireMux_T_879 & _out_T_1831; // @[RegisterRouter.scala:87:24] assign out_woready_1_891 = _out_wofireMux_T_880; // @[RegisterRouter.scala:87:24] assign out_woready_1_892 = _out_wofireMux_T_880; // @[RegisterRouter.scala:87:24] assign out_woready_1_893 = _out_wofireMux_T_880; // @[RegisterRouter.scala:87:24] assign out_woready_1_894 = _out_wofireMux_T_880; // @[RegisterRouter.scala:87:24] assign out_woready_1_895 = _out_wofireMux_T_880; // @[RegisterRouter.scala:87:24] assign out_woready_1_896 = _out_wofireMux_T_880; // @[RegisterRouter.scala:87:24] assign out_woready_1_897 = _out_wofireMux_T_880; // @[RegisterRouter.scala:87:24] assign out_woready_1_898 = _out_wofireMux_T_880; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_881 = ~_out_T_1831; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_883 = _out_wofireMux_T_262 & out_backSel_155; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_884 = _out_wofireMux_T_883 & _out_T_1787; // @[RegisterRouter.scala:87:24] assign out_woready_1_715 = _out_wofireMux_T_884; // @[RegisterRouter.scala:87:24] assign out_woready_1_716 = _out_wofireMux_T_884; // @[RegisterRouter.scala:87:24] assign out_woready_1_717 = _out_wofireMux_T_884; // @[RegisterRouter.scala:87:24] assign out_woready_1_718 = _out_wofireMux_T_884; // @[RegisterRouter.scala:87:24] assign out_woready_1_719 = _out_wofireMux_T_884; // @[RegisterRouter.scala:87:24] assign out_woready_1_720 = _out_wofireMux_T_884; // @[RegisterRouter.scala:87:24] assign out_woready_1_721 = _out_wofireMux_T_884; // @[RegisterRouter.scala:87:24] assign out_woready_1_722 = _out_wofireMux_T_884; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_885 = ~_out_T_1787; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_887 = _out_wofireMux_T_262 & out_backSel_156; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_888 = _out_wofireMux_T_887 & _out_T_1699; // @[RegisterRouter.scala:87:24] assign out_woready_1_386 = _out_wofireMux_T_888; // @[RegisterRouter.scala:87:24] assign out_woready_1_387 = _out_wofireMux_T_888; // @[RegisterRouter.scala:87:24] assign out_woready_1_388 = _out_wofireMux_T_888; // @[RegisterRouter.scala:87:24] assign out_woready_1_389 = _out_wofireMux_T_888; // @[RegisterRouter.scala:87:24] assign out_woready_1_390 = _out_wofireMux_T_888; // @[RegisterRouter.scala:87:24] assign out_woready_1_391 = _out_wofireMux_T_888; // @[RegisterRouter.scala:87:24] assign out_woready_1_392 = _out_wofireMux_T_888; // @[RegisterRouter.scala:87:24] assign out_woready_1_393 = _out_wofireMux_T_888; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_889 = ~_out_T_1699; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_891 = _out_wofireMux_T_262 & out_backSel_157; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_892 = _out_wofireMux_T_891 & _out_T_1633; // @[RegisterRouter.scala:87:24] assign out_woready_1_128 = _out_wofireMux_T_892; // @[RegisterRouter.scala:87:24] assign out_woready_1_129 = _out_wofireMux_T_892; // @[RegisterRouter.scala:87:24] assign out_woready_1_130 = _out_wofireMux_T_892; // @[RegisterRouter.scala:87:24] assign out_woready_1_131 = _out_wofireMux_T_892; // @[RegisterRouter.scala:87:24] assign out_woready_1_132 = _out_wofireMux_T_892; // @[RegisterRouter.scala:87:24] assign out_woready_1_133 = _out_wofireMux_T_892; // @[RegisterRouter.scala:87:24] assign out_woready_1_134 = _out_wofireMux_T_892; // @[RegisterRouter.scala:87:24] assign out_woready_1_135 = _out_wofireMux_T_892; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_893 = ~_out_T_1633; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_895 = _out_wofireMux_T_262 & out_backSel_158; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_896 = _out_wofireMux_T_895 & _out_T_1849; // @[RegisterRouter.scala:87:24] assign out_woready_1_963 = _out_wofireMux_T_896; // @[RegisterRouter.scala:87:24] assign out_woready_1_964 = _out_wofireMux_T_896; // @[RegisterRouter.scala:87:24] assign out_woready_1_965 = _out_wofireMux_T_896; // @[RegisterRouter.scala:87:24] assign out_woready_1_966 = _out_wofireMux_T_896; // @[RegisterRouter.scala:87:24] assign out_woready_1_967 = _out_wofireMux_T_896; // @[RegisterRouter.scala:87:24] assign out_woready_1_968 = _out_wofireMux_T_896; // @[RegisterRouter.scala:87:24] assign out_woready_1_969 = _out_wofireMux_T_896; // @[RegisterRouter.scala:87:24] assign out_woready_1_970 = _out_wofireMux_T_896; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_897 = ~_out_T_1849; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_899 = _out_wofireMux_T_262 & out_backSel_159; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_900 = _out_wofireMux_T_899 & _out_T_1765; // @[RegisterRouter.scala:87:24] assign out_woready_1_633 = _out_wofireMux_T_900; // @[RegisterRouter.scala:87:24] assign out_woready_1_634 = _out_wofireMux_T_900; // @[RegisterRouter.scala:87:24] assign out_woready_1_635 = _out_wofireMux_T_900; // @[RegisterRouter.scala:87:24] assign out_woready_1_636 = _out_wofireMux_T_900; // @[RegisterRouter.scala:87:24] assign out_woready_1_637 = _out_wofireMux_T_900; // @[RegisterRouter.scala:87:24] assign out_woready_1_638 = _out_wofireMux_T_900; // @[RegisterRouter.scala:87:24] assign out_woready_1_639 = _out_wofireMux_T_900; // @[RegisterRouter.scala:87:24] assign out_woready_1_640 = _out_wofireMux_T_900; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_901 = ~_out_T_1765; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_903 = _out_wofireMux_T_262 & out_backSel_160; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_904 = _out_wofireMux_T_903 & _out_T_1681; // @[RegisterRouter.scala:87:24] assign out_woready_1_320 = _out_wofireMux_T_904; // @[RegisterRouter.scala:87:24] assign out_woready_1_321 = _out_wofireMux_T_904; // @[RegisterRouter.scala:87:24] assign out_woready_1_322 = _out_wofireMux_T_904; // @[RegisterRouter.scala:87:24] assign out_woready_1_323 = _out_wofireMux_T_904; // @[RegisterRouter.scala:87:24] assign out_woready_1_324 = _out_wofireMux_T_904; // @[RegisterRouter.scala:87:24] assign out_woready_1_325 = _out_wofireMux_T_904; // @[RegisterRouter.scala:87:24] assign out_woready_1_326 = _out_wofireMux_T_904; // @[RegisterRouter.scala:87:24] assign out_woready_1_327 = _out_wofireMux_T_904; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_905 = ~_out_T_1681; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_907 = _out_wofireMux_T_262 & out_backSel_161; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_908 = _out_wofireMux_T_907 & _out_T_1745; // @[RegisterRouter.scala:87:24] assign out_woready_1_553 = _out_wofireMux_T_908; // @[RegisterRouter.scala:87:24] assign out_woready_1_554 = _out_wofireMux_T_908; // @[RegisterRouter.scala:87:24] assign out_woready_1_555 = _out_wofireMux_T_908; // @[RegisterRouter.scala:87:24] assign out_woready_1_556 = _out_wofireMux_T_908; // @[RegisterRouter.scala:87:24] assign out_woready_1_557 = _out_wofireMux_T_908; // @[RegisterRouter.scala:87:24] assign out_woready_1_558 = _out_wofireMux_T_908; // @[RegisterRouter.scala:87:24] assign out_woready_1_559 = _out_wofireMux_T_908; // @[RegisterRouter.scala:87:24] assign out_woready_1_560 = _out_wofireMux_T_908; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_909 = ~_out_T_1745; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_911 = _out_wofireMux_T_262 & out_backSel_162; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_912 = _out_wofireMux_T_911 & _out_T_1809; // @[RegisterRouter.scala:87:24] assign out_woready_1_803 = _out_wofireMux_T_912; // @[RegisterRouter.scala:87:24] assign out_woready_1_804 = _out_wofireMux_T_912; // @[RegisterRouter.scala:87:24] assign out_woready_1_805 = _out_wofireMux_T_912; // @[RegisterRouter.scala:87:24] assign out_woready_1_806 = _out_wofireMux_T_912; // @[RegisterRouter.scala:87:24] assign out_woready_1_807 = _out_wofireMux_T_912; // @[RegisterRouter.scala:87:24] assign out_woready_1_808 = _out_wofireMux_T_912; // @[RegisterRouter.scala:87:24] assign out_woready_1_809 = _out_wofireMux_T_912; // @[RegisterRouter.scala:87:24] assign out_woready_1_810 = _out_wofireMux_T_912; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_913 = ~_out_T_1809; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_915 = _out_wofireMux_T_262 & out_backSel_163; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_916 = _out_wofireMux_T_915 & _out_T_1895; // @[RegisterRouter.scala:87:24] assign out_woready_1_1147 = _out_wofireMux_T_916; // @[RegisterRouter.scala:87:24] assign out_woready_1_1148 = _out_wofireMux_T_916; // @[RegisterRouter.scala:87:24] assign out_woready_1_1149 = _out_wofireMux_T_916; // @[RegisterRouter.scala:87:24] assign out_woready_1_1150 = _out_wofireMux_T_916; // @[RegisterRouter.scala:87:24] assign out_woready_1_1151 = _out_wofireMux_T_916; // @[RegisterRouter.scala:87:24] assign out_woready_1_1152 = _out_wofireMux_T_916; // @[RegisterRouter.scala:87:24] assign out_woready_1_1153 = _out_wofireMux_T_916; // @[RegisterRouter.scala:87:24] assign out_woready_1_1154 = _out_wofireMux_T_916; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_917 = ~_out_T_1895; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_919 = _out_wofireMux_T_262 & out_backSel_164; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_920 = _out_wofireMux_T_919 & _out_T_1645; // @[RegisterRouter.scala:87:24] assign out_woready_1_176 = _out_wofireMux_T_920; // @[RegisterRouter.scala:87:24] assign out_woready_1_177 = _out_wofireMux_T_920; // @[RegisterRouter.scala:87:24] assign out_woready_1_178 = _out_wofireMux_T_920; // @[RegisterRouter.scala:87:24] assign out_woready_1_179 = _out_wofireMux_T_920; // @[RegisterRouter.scala:87:24] assign out_woready_1_180 = _out_wofireMux_T_920; // @[RegisterRouter.scala:87:24] assign out_woready_1_181 = _out_wofireMux_T_920; // @[RegisterRouter.scala:87:24] assign out_woready_1_182 = _out_wofireMux_T_920; // @[RegisterRouter.scala:87:24] assign out_woready_1_183 = _out_wofireMux_T_920; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_921 = ~_out_T_1645; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_923 = _out_wofireMux_T_262 & out_backSel_165; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_924 = _out_wofireMux_T_923 & _out_T_1687; // @[RegisterRouter.scala:87:24] assign out_woready_1_344 = _out_wofireMux_T_924; // @[RegisterRouter.scala:87:24] assign out_woready_1_345 = _out_wofireMux_T_924; // @[RegisterRouter.scala:87:24] assign out_woready_1_346 = _out_wofireMux_T_924; // @[RegisterRouter.scala:87:24] assign out_woready_1_347 = _out_wofireMux_T_924; // @[RegisterRouter.scala:87:24] assign out_woready_1_348 = _out_wofireMux_T_924; // @[RegisterRouter.scala:87:24] assign out_woready_1_349 = _out_wofireMux_T_924; // @[RegisterRouter.scala:87:24] assign out_woready_1_350 = _out_wofireMux_T_924; // @[RegisterRouter.scala:87:24] assign out_woready_1_351 = _out_wofireMux_T_924; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_925 = ~_out_T_1687; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_927 = _out_wofireMux_T_262 & out_backSel_166; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_928 = _out_wofireMux_T_927 & _out_T_1737; // @[RegisterRouter.scala:87:24] assign out_woready_1_527 = _out_wofireMux_T_928; // @[RegisterRouter.scala:87:24] assign out_woready_1_528 = _out_wofireMux_T_928; // @[RegisterRouter.scala:87:24] assign out_woready_1_529 = _out_wofireMux_T_928; // @[RegisterRouter.scala:87:24] assign out_woready_1_530 = _out_wofireMux_T_928; // @[RegisterRouter.scala:87:24] assign out_woready_1_531 = _out_wofireMux_T_928; // @[RegisterRouter.scala:87:24] assign out_woready_1_532 = _out_wofireMux_T_928; // @[RegisterRouter.scala:87:24] assign out_woready_1_533 = _out_wofireMux_T_928; // @[RegisterRouter.scala:87:24] assign out_woready_1_534 = _out_wofireMux_T_928; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_929 = ~_out_T_1737; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_931 = _out_wofireMux_T_262 & out_backSel_167; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_932 = _out_wofireMux_T_931 & _out_T_1807; // @[RegisterRouter.scala:87:24] assign out_woready_1_795 = _out_wofireMux_T_932; // @[RegisterRouter.scala:87:24] assign out_woready_1_796 = _out_wofireMux_T_932; // @[RegisterRouter.scala:87:24] assign out_woready_1_797 = _out_wofireMux_T_932; // @[RegisterRouter.scala:87:24] assign out_woready_1_798 = _out_wofireMux_T_932; // @[RegisterRouter.scala:87:24] assign out_woready_1_799 = _out_wofireMux_T_932; // @[RegisterRouter.scala:87:24] assign out_woready_1_800 = _out_wofireMux_T_932; // @[RegisterRouter.scala:87:24] assign out_woready_1_801 = _out_wofireMux_T_932; // @[RegisterRouter.scala:87:24] assign out_woready_1_802 = _out_wofireMux_T_932; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_933 = ~_out_T_1807; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_935 = _out_wofireMux_T_262 & out_backSel_168; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_936 = _out_wofireMux_T_935 & _out_T_1875; // @[RegisterRouter.scala:87:24] assign out_woready_1_1067 = _out_wofireMux_T_936; // @[RegisterRouter.scala:87:24] assign out_woready_1_1068 = _out_wofireMux_T_936; // @[RegisterRouter.scala:87:24] assign out_woready_1_1069 = _out_wofireMux_T_936; // @[RegisterRouter.scala:87:24] assign out_woready_1_1070 = _out_wofireMux_T_936; // @[RegisterRouter.scala:87:24] assign out_woready_1_1071 = _out_wofireMux_T_936; // @[RegisterRouter.scala:87:24] assign out_woready_1_1072 = _out_wofireMux_T_936; // @[RegisterRouter.scala:87:24] assign out_woready_1_1073 = _out_wofireMux_T_936; // @[RegisterRouter.scala:87:24] assign out_woready_1_1074 = _out_wofireMux_T_936; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_937 = ~_out_T_1875; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_939 = _out_wofireMux_T_262 & out_backSel_169; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_940 = _out_wofireMux_T_939 & _out_T_1703; // @[RegisterRouter.scala:87:24] assign out_woready_1_402 = _out_wofireMux_T_940; // @[RegisterRouter.scala:87:24] assign out_woready_1_403 = _out_wofireMux_T_940; // @[RegisterRouter.scala:87:24] assign out_woready_1_404 = _out_wofireMux_T_940; // @[RegisterRouter.scala:87:24] assign out_woready_1_405 = _out_wofireMux_T_940; // @[RegisterRouter.scala:87:24] assign out_woready_1_406 = _out_wofireMux_T_940; // @[RegisterRouter.scala:87:24] assign out_woready_1_407 = _out_wofireMux_T_940; // @[RegisterRouter.scala:87:24] assign out_woready_1_408 = _out_wofireMux_T_940; // @[RegisterRouter.scala:87:24] assign out_woready_1_409 = _out_wofireMux_T_940; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_941 = ~_out_T_1703; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_943 = _out_wofireMux_T_262 & out_backSel_170; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_944 = _out_wofireMux_T_943 & _out_T_1607; // @[RegisterRouter.scala:87:24] assign out_woready_1_24 = _out_wofireMux_T_944; // @[RegisterRouter.scala:87:24] assign out_woready_1_25 = _out_wofireMux_T_944; // @[RegisterRouter.scala:87:24] assign out_woready_1_26 = _out_wofireMux_T_944; // @[RegisterRouter.scala:87:24] assign out_woready_1_27 = _out_wofireMux_T_944; // @[RegisterRouter.scala:87:24] assign out_woready_1_28 = _out_wofireMux_T_944; // @[RegisterRouter.scala:87:24] assign out_woready_1_29 = _out_wofireMux_T_944; // @[RegisterRouter.scala:87:24] assign out_woready_1_30 = _out_wofireMux_T_944; // @[RegisterRouter.scala:87:24] assign out_woready_1_31 = _out_wofireMux_T_944; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_945 = ~_out_T_1607; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_947 = _out_wofireMux_T_262 & out_backSel_171; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_948 = _out_wofireMux_T_947 & _out_T_1855; // @[RegisterRouter.scala:87:24] assign out_woready_1_987 = _out_wofireMux_T_948; // @[RegisterRouter.scala:87:24] assign out_woready_1_988 = _out_wofireMux_T_948; // @[RegisterRouter.scala:87:24] assign out_woready_1_989 = _out_wofireMux_T_948; // @[RegisterRouter.scala:87:24] assign out_woready_1_990 = _out_wofireMux_T_948; // @[RegisterRouter.scala:87:24] assign out_woready_1_991 = _out_wofireMux_T_948; // @[RegisterRouter.scala:87:24] assign out_woready_1_992 = _out_wofireMux_T_948; // @[RegisterRouter.scala:87:24] assign out_woready_1_993 = _out_wofireMux_T_948; // @[RegisterRouter.scala:87:24] assign out_woready_1_994 = _out_wofireMux_T_948; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_949 = ~_out_T_1855; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_951 = _out_wofireMux_T_262 & out_backSel_172; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_952 = _out_wofireMux_T_951 & _out_T_1769; // @[RegisterRouter.scala:87:24] assign out_woready_1_649 = _out_wofireMux_T_952; // @[RegisterRouter.scala:87:24] assign out_woready_1_650 = _out_wofireMux_T_952; // @[RegisterRouter.scala:87:24] assign out_woready_1_651 = _out_wofireMux_T_952; // @[RegisterRouter.scala:87:24] assign out_woready_1_652 = _out_wofireMux_T_952; // @[RegisterRouter.scala:87:24] assign out_woready_1_653 = _out_wofireMux_T_952; // @[RegisterRouter.scala:87:24] assign out_woready_1_654 = _out_wofireMux_T_952; // @[RegisterRouter.scala:87:24] assign out_woready_1_655 = _out_wofireMux_T_952; // @[RegisterRouter.scala:87:24] assign out_woready_1_656 = _out_wofireMux_T_952; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_953 = ~_out_T_1769; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_955 = _out_wofireMux_T_262 & out_backSel_173; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_956 = _out_wofireMux_T_955 & _out_T_1719; // @[RegisterRouter.scala:87:24] assign out_woready_1_459 = _out_wofireMux_T_956; // @[RegisterRouter.scala:87:24] assign out_woready_1_460 = _out_wofireMux_T_956; // @[RegisterRouter.scala:87:24] assign out_woready_1_461 = _out_wofireMux_T_956; // @[RegisterRouter.scala:87:24] assign out_woready_1_462 = _out_wofireMux_T_956; // @[RegisterRouter.scala:87:24] assign out_woready_1_463 = _out_wofireMux_T_956; // @[RegisterRouter.scala:87:24] assign out_woready_1_464 = _out_wofireMux_T_956; // @[RegisterRouter.scala:87:24] assign out_woready_1_465 = _out_wofireMux_T_956; // @[RegisterRouter.scala:87:24] assign out_woready_1_466 = _out_wofireMux_T_956; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_957 = ~_out_T_1719; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_959 = _out_wofireMux_T_262 & out_backSel_174; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_960 = _out_wofireMux_T_959 & _out_T_1621; // @[RegisterRouter.scala:87:24] assign out_woready_1_80 = _out_wofireMux_T_960; // @[RegisterRouter.scala:87:24] assign out_woready_1_81 = _out_wofireMux_T_960; // @[RegisterRouter.scala:87:24] assign out_woready_1_82 = _out_wofireMux_T_960; // @[RegisterRouter.scala:87:24] assign out_woready_1_83 = _out_wofireMux_T_960; // @[RegisterRouter.scala:87:24] assign out_woready_1_84 = _out_wofireMux_T_960; // @[RegisterRouter.scala:87:24] assign out_woready_1_85 = _out_wofireMux_T_960; // @[RegisterRouter.scala:87:24] assign out_woready_1_86 = _out_wofireMux_T_960; // @[RegisterRouter.scala:87:24] assign out_woready_1_87 = _out_wofireMux_T_960; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_961 = ~_out_T_1621; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_963 = _out_wofireMux_T_262 & out_backSel_175; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_964 = _out_wofireMux_T_963 & _out_T_1833; // @[RegisterRouter.scala:87:24] assign out_woready_1_899 = _out_wofireMux_T_964; // @[RegisterRouter.scala:87:24] assign out_woready_1_900 = _out_wofireMux_T_964; // @[RegisterRouter.scala:87:24] assign out_woready_1_901 = _out_wofireMux_T_964; // @[RegisterRouter.scala:87:24] assign out_woready_1_902 = _out_wofireMux_T_964; // @[RegisterRouter.scala:87:24] assign out_woready_1_903 = _out_wofireMux_T_964; // @[RegisterRouter.scala:87:24] assign out_woready_1_904 = _out_wofireMux_T_964; // @[RegisterRouter.scala:87:24] assign out_woready_1_905 = _out_wofireMux_T_964; // @[RegisterRouter.scala:87:24] assign out_woready_1_906 = _out_wofireMux_T_964; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_965 = ~_out_T_1833; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_967 = _out_wofireMux_T_262 & out_backSel_176; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_968 = _out_wofireMux_T_967 & _out_T_1751; // @[RegisterRouter.scala:87:24] assign out_woready_1_577 = _out_wofireMux_T_968; // @[RegisterRouter.scala:87:24] assign out_woready_1_578 = _out_wofireMux_T_968; // @[RegisterRouter.scala:87:24] assign out_woready_1_579 = _out_wofireMux_T_968; // @[RegisterRouter.scala:87:24] assign out_woready_1_580 = _out_wofireMux_T_968; // @[RegisterRouter.scala:87:24] assign out_woready_1_581 = _out_wofireMux_T_968; // @[RegisterRouter.scala:87:24] assign out_woready_1_582 = _out_wofireMux_T_968; // @[RegisterRouter.scala:87:24] assign out_woready_1_583 = _out_wofireMux_T_968; // @[RegisterRouter.scala:87:24] assign out_woready_1_584 = _out_wofireMux_T_968; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_969 = ~_out_T_1751; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_971 = _out_wofireMux_T_262 & out_backSel_177; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_972 = _out_wofireMux_T_971 & _out_T_1827; // @[RegisterRouter.scala:87:24] assign out_woready_1_875 = _out_wofireMux_T_972; // @[RegisterRouter.scala:87:24] assign out_woready_1_876 = _out_wofireMux_T_972; // @[RegisterRouter.scala:87:24] assign out_woready_1_877 = _out_wofireMux_T_972; // @[RegisterRouter.scala:87:24] assign out_woready_1_878 = _out_wofireMux_T_972; // @[RegisterRouter.scala:87:24] assign out_woready_1_879 = _out_wofireMux_T_972; // @[RegisterRouter.scala:87:24] assign out_woready_1_880 = _out_wofireMux_T_972; // @[RegisterRouter.scala:87:24] assign out_woready_1_881 = _out_wofireMux_T_972; // @[RegisterRouter.scala:87:24] assign out_woready_1_882 = _out_wofireMux_T_972; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_973 = ~_out_T_1827; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_975 = _out_wofireMux_T_262 & out_backSel_178; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_976 = _out_wofireMux_T_975 & _out_T_1893; // @[RegisterRouter.scala:87:24] assign out_woready_1_1139 = _out_wofireMux_T_976; // @[RegisterRouter.scala:87:24] assign out_woready_1_1140 = _out_wofireMux_T_976; // @[RegisterRouter.scala:87:24] assign out_woready_1_1141 = _out_wofireMux_T_976; // @[RegisterRouter.scala:87:24] assign out_woready_1_1142 = _out_wofireMux_T_976; // @[RegisterRouter.scala:87:24] assign out_woready_1_1143 = _out_wofireMux_T_976; // @[RegisterRouter.scala:87:24] assign out_woready_1_1144 = _out_wofireMux_T_976; // @[RegisterRouter.scala:87:24] assign out_woready_1_1145 = _out_wofireMux_T_976; // @[RegisterRouter.scala:87:24] assign out_woready_1_1146 = _out_wofireMux_T_976; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_977 = ~_out_T_1893; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_979 = _out_wofireMux_T_262 & out_backSel_179; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_980 = _out_wofireMux_T_979 & _out_T_1647; // @[RegisterRouter.scala:87:24] assign out_woready_1_184 = _out_wofireMux_T_980; // @[RegisterRouter.scala:87:24] assign out_woready_1_185 = _out_wofireMux_T_980; // @[RegisterRouter.scala:87:24] assign out_woready_1_186 = _out_wofireMux_T_980; // @[RegisterRouter.scala:87:24] assign out_woready_1_187 = _out_wofireMux_T_980; // @[RegisterRouter.scala:87:24] assign out_woready_1_188 = _out_wofireMux_T_980; // @[RegisterRouter.scala:87:24] assign out_woready_1_189 = _out_wofireMux_T_980; // @[RegisterRouter.scala:87:24] assign out_woready_1_190 = _out_wofireMux_T_980; // @[RegisterRouter.scala:87:24] assign out_woready_1_191 = _out_wofireMux_T_980; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_981 = ~_out_T_1647; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_983 = _out_wofireMux_T_262 & out_backSel_180; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_984 = _out_wofireMux_T_983 & _out_T_1747; // @[RegisterRouter.scala:87:24] assign out_woready_1_561 = _out_wofireMux_T_984; // @[RegisterRouter.scala:87:24] assign out_woready_1_562 = _out_wofireMux_T_984; // @[RegisterRouter.scala:87:24] assign out_woready_1_563 = _out_wofireMux_T_984; // @[RegisterRouter.scala:87:24] assign out_woready_1_564 = _out_wofireMux_T_984; // @[RegisterRouter.scala:87:24] assign out_woready_1_565 = _out_wofireMux_T_984; // @[RegisterRouter.scala:87:24] assign out_woready_1_566 = _out_wofireMux_T_984; // @[RegisterRouter.scala:87:24] assign out_woready_1_567 = _out_wofireMux_T_984; // @[RegisterRouter.scala:87:24] assign out_woready_1_568 = _out_wofireMux_T_984; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_985 = ~_out_T_1747; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_987 = _out_wofireMux_T_262 & out_backSel_181; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_988 = _out_wofireMux_T_987 & _out_T_1763; // @[RegisterRouter.scala:87:24] assign out_woready_1_625 = _out_wofireMux_T_988; // @[RegisterRouter.scala:87:24] assign out_woready_1_626 = _out_wofireMux_T_988; // @[RegisterRouter.scala:87:24] assign out_woready_1_627 = _out_wofireMux_T_988; // @[RegisterRouter.scala:87:24] assign out_woready_1_628 = _out_wofireMux_T_988; // @[RegisterRouter.scala:87:24] assign out_woready_1_629 = _out_wofireMux_T_988; // @[RegisterRouter.scala:87:24] assign out_woready_1_630 = _out_wofireMux_T_988; // @[RegisterRouter.scala:87:24] assign out_woready_1_631 = _out_wofireMux_T_988; // @[RegisterRouter.scala:87:24] assign out_woready_1_632 = _out_wofireMux_T_988; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_989 = ~_out_T_1763; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_991 = _out_wofireMux_T_262 & out_backSel_182; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_992 = _out_wofireMux_T_991 & _out_T_1829; // @[RegisterRouter.scala:87:24] assign out_woready_1_883 = _out_wofireMux_T_992; // @[RegisterRouter.scala:87:24] assign out_woready_1_884 = _out_wofireMux_T_992; // @[RegisterRouter.scala:87:24] assign out_woready_1_885 = _out_wofireMux_T_992; // @[RegisterRouter.scala:87:24] assign out_woready_1_886 = _out_wofireMux_T_992; // @[RegisterRouter.scala:87:24] assign out_woready_1_887 = _out_wofireMux_T_992; // @[RegisterRouter.scala:87:24] assign out_woready_1_888 = _out_wofireMux_T_992; // @[RegisterRouter.scala:87:24] assign out_woready_1_889 = _out_wofireMux_T_992; // @[RegisterRouter.scala:87:24] assign out_woready_1_890 = _out_wofireMux_T_992; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_993 = ~_out_T_1829; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_995 = _out_wofireMux_T_262 & out_backSel_183; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_996 = _out_wofireMux_T_995 & _out_T_1873; // @[RegisterRouter.scala:87:24] assign out_woready_1_1059 = _out_wofireMux_T_996; // @[RegisterRouter.scala:87:24] assign out_woready_1_1060 = _out_wofireMux_T_996; // @[RegisterRouter.scala:87:24] assign out_woready_1_1061 = _out_wofireMux_T_996; // @[RegisterRouter.scala:87:24] assign out_woready_1_1062 = _out_wofireMux_T_996; // @[RegisterRouter.scala:87:24] assign out_woready_1_1063 = _out_wofireMux_T_996; // @[RegisterRouter.scala:87:24] assign out_woready_1_1064 = _out_wofireMux_T_996; // @[RegisterRouter.scala:87:24] assign out_woready_1_1065 = _out_wofireMux_T_996; // @[RegisterRouter.scala:87:24] assign out_woready_1_1066 = _out_wofireMux_T_996; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_997 = ~_out_T_1873; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_999 = _out_wofireMux_T_262 & out_backSel_184; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1000 = _out_wofireMux_T_999 & _out_T_1627; // @[RegisterRouter.scala:87:24] assign out_woready_1_104 = _out_wofireMux_T_1000; // @[RegisterRouter.scala:87:24] assign out_woready_1_105 = _out_wofireMux_T_1000; // @[RegisterRouter.scala:87:24] assign out_woready_1_106 = _out_wofireMux_T_1000; // @[RegisterRouter.scala:87:24] assign out_woready_1_107 = _out_wofireMux_T_1000; // @[RegisterRouter.scala:87:24] assign out_woready_1_108 = _out_wofireMux_T_1000; // @[RegisterRouter.scala:87:24] assign out_woready_1_109 = _out_wofireMux_T_1000; // @[RegisterRouter.scala:87:24] assign out_woready_1_110 = _out_wofireMux_T_1000; // @[RegisterRouter.scala:87:24] assign out_woready_1_111 = _out_wofireMux_T_1000; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1001 = ~_out_T_1627; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1003 = _out_wofireMux_T_262 & out_backSel_185; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1004 = _out_wofireMux_T_1003 & _out_T_1623; // @[RegisterRouter.scala:87:24] assign out_woready_1_88 = _out_wofireMux_T_1004; // @[RegisterRouter.scala:87:24] assign out_woready_1_89 = _out_wofireMux_T_1004; // @[RegisterRouter.scala:87:24] assign out_woready_1_90 = _out_wofireMux_T_1004; // @[RegisterRouter.scala:87:24] assign out_woready_1_91 = _out_wofireMux_T_1004; // @[RegisterRouter.scala:87:24] assign out_woready_1_92 = _out_wofireMux_T_1004; // @[RegisterRouter.scala:87:24] assign out_woready_1_93 = _out_wofireMux_T_1004; // @[RegisterRouter.scala:87:24] assign out_woready_1_94 = _out_wofireMux_T_1004; // @[RegisterRouter.scala:87:24] assign out_woready_1_95 = _out_wofireMux_T_1004; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1005 = ~_out_T_1623; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1007 = _out_wofireMux_T_262 & out_backSel_186; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1008 = _out_wofireMux_T_1007 & _out_T_1851; // @[RegisterRouter.scala:87:24] assign out_woready_1_971 = _out_wofireMux_T_1008; // @[RegisterRouter.scala:87:24] assign out_woready_1_972 = _out_wofireMux_T_1008; // @[RegisterRouter.scala:87:24] assign out_woready_1_973 = _out_wofireMux_T_1008; // @[RegisterRouter.scala:87:24] assign out_woready_1_974 = _out_wofireMux_T_1008; // @[RegisterRouter.scala:87:24] assign out_woready_1_975 = _out_wofireMux_T_1008; // @[RegisterRouter.scala:87:24] assign out_woready_1_976 = _out_wofireMux_T_1008; // @[RegisterRouter.scala:87:24] assign out_woready_1_977 = _out_wofireMux_T_1008; // @[RegisterRouter.scala:87:24] assign out_woready_1_978 = _out_wofireMux_T_1008; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1009 = ~_out_T_1851; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1011 = _out_wofireMux_T_262 & out_backSel_187; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1012 = _out_wofireMux_T_1011 & _out_T_1767; // @[RegisterRouter.scala:87:24] assign out_woready_1_641 = _out_wofireMux_T_1012; // @[RegisterRouter.scala:87:24] assign out_woready_1_642 = _out_wofireMux_T_1012; // @[RegisterRouter.scala:87:24] assign out_woready_1_643 = _out_wofireMux_T_1012; // @[RegisterRouter.scala:87:24] assign out_woready_1_644 = _out_wofireMux_T_1012; // @[RegisterRouter.scala:87:24] assign out_woready_1_645 = _out_wofireMux_T_1012; // @[RegisterRouter.scala:87:24] assign out_woready_1_646 = _out_wofireMux_T_1012; // @[RegisterRouter.scala:87:24] assign out_woready_1_647 = _out_wofireMux_T_1012; // @[RegisterRouter.scala:87:24] assign out_woready_1_648 = _out_wofireMux_T_1012; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1013 = ~_out_T_1767; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1015 = _out_wofireMux_T_262 & out_backSel_188; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1016 = _out_wofireMux_T_1015 & _out_T_1701; // @[RegisterRouter.scala:87:24] assign out_woready_1_394 = _out_wofireMux_T_1016; // @[RegisterRouter.scala:87:24] assign out_woready_1_395 = _out_wofireMux_T_1016; // @[RegisterRouter.scala:87:24] assign out_woready_1_396 = _out_wofireMux_T_1016; // @[RegisterRouter.scala:87:24] assign out_woready_1_397 = _out_wofireMux_T_1016; // @[RegisterRouter.scala:87:24] assign out_woready_1_398 = _out_wofireMux_T_1016; // @[RegisterRouter.scala:87:24] assign out_woready_1_399 = _out_wofireMux_T_1016; // @[RegisterRouter.scala:87:24] assign out_woready_1_400 = _out_wofireMux_T_1016; // @[RegisterRouter.scala:87:24] assign out_woready_1_401 = _out_wofireMux_T_1016; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1017 = ~_out_T_1701; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1019 = _out_wofireMux_T_262 & out_backSel_189; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1020 = _out_wofireMux_T_1019 & _out_T_1635; // @[RegisterRouter.scala:87:24] assign out_woready_1_136 = _out_wofireMux_T_1020; // @[RegisterRouter.scala:87:24] assign out_woready_1_137 = _out_wofireMux_T_1020; // @[RegisterRouter.scala:87:24] assign out_woready_1_138 = _out_wofireMux_T_1020; // @[RegisterRouter.scala:87:24] assign out_woready_1_139 = _out_wofireMux_T_1020; // @[RegisterRouter.scala:87:24] assign out_woready_1_140 = _out_wofireMux_T_1020; // @[RegisterRouter.scala:87:24] assign out_woready_1_141 = _out_wofireMux_T_1020; // @[RegisterRouter.scala:87:24] assign out_woready_1_142 = _out_wofireMux_T_1020; // @[RegisterRouter.scala:87:24] assign out_woready_1_143 = _out_wofireMux_T_1020; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1021 = ~_out_T_1635; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1023 = _out_wofireMux_T_262 & out_backSel_190; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1024 = _out_wofireMux_T_1023 & _out_T_1871; // @[RegisterRouter.scala:87:24] assign out_woready_1_1051 = _out_wofireMux_T_1024; // @[RegisterRouter.scala:87:24] assign out_woready_1_1052 = _out_wofireMux_T_1024; // @[RegisterRouter.scala:87:24] assign out_woready_1_1053 = _out_wofireMux_T_1024; // @[RegisterRouter.scala:87:24] assign out_woready_1_1054 = _out_wofireMux_T_1024; // @[RegisterRouter.scala:87:24] assign out_woready_1_1055 = _out_wofireMux_T_1024; // @[RegisterRouter.scala:87:24] assign out_woready_1_1056 = _out_wofireMux_T_1024; // @[RegisterRouter.scala:87:24] assign out_woready_1_1057 = _out_wofireMux_T_1024; // @[RegisterRouter.scala:87:24] assign out_woready_1_1058 = _out_wofireMux_T_1024; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1025 = ~_out_T_1871; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1027 = _out_wofireMux_T_262 & out_backSel_191; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1028 = _out_wofireMux_T_1027 & _out_T_1753; // @[RegisterRouter.scala:87:24] assign out_woready_1_585 = _out_wofireMux_T_1028; // @[RegisterRouter.scala:87:24] assign out_woready_1_586 = _out_wofireMux_T_1028; // @[RegisterRouter.scala:87:24] assign out_woready_1_587 = _out_wofireMux_T_1028; // @[RegisterRouter.scala:87:24] assign out_woready_1_588 = _out_wofireMux_T_1028; // @[RegisterRouter.scala:87:24] assign out_woready_1_589 = _out_wofireMux_T_1028; // @[RegisterRouter.scala:87:24] assign out_woready_1_590 = _out_wofireMux_T_1028; // @[RegisterRouter.scala:87:24] assign out_woready_1_591 = _out_wofireMux_T_1028; // @[RegisterRouter.scala:87:24] assign out_woready_1_592 = _out_wofireMux_T_1028; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1029 = ~_out_T_1753; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1031 = _out_wofireMux_T_262 & out_backSel_192; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1032 = _out_wofireMux_T_1031 & _out_T_1683; // @[RegisterRouter.scala:87:24] assign out_woready_1_328 = _out_wofireMux_T_1032; // @[RegisterRouter.scala:87:24] assign out_woready_1_329 = _out_wofireMux_T_1032; // @[RegisterRouter.scala:87:24] assign out_woready_1_330 = _out_wofireMux_T_1032; // @[RegisterRouter.scala:87:24] assign out_woready_1_331 = _out_wofireMux_T_1032; // @[RegisterRouter.scala:87:24] assign out_woready_1_332 = _out_wofireMux_T_1032; // @[RegisterRouter.scala:87:24] assign out_woready_1_333 = _out_wofireMux_T_1032; // @[RegisterRouter.scala:87:24] assign out_woready_1_334 = _out_wofireMux_T_1032; // @[RegisterRouter.scala:87:24] assign out_woready_1_335 = _out_wofireMux_T_1032; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1033 = ~_out_T_1683; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1035 = _out_wofireMux_T_262 & out_backSel_193; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1036 = _out_wofireMux_T_1035 & _out_T_1709; // @[RegisterRouter.scala:87:24] assign out_woready_1_426 = _out_wofireMux_T_1036; // @[RegisterRouter.scala:87:24] assign out_woready_1_427 = _out_wofireMux_T_1036; // @[RegisterRouter.scala:87:24] assign out_woready_1_428 = _out_wofireMux_T_1036; // @[RegisterRouter.scala:87:24] assign out_woready_1_429 = _out_wofireMux_T_1036; // @[RegisterRouter.scala:87:24] assign out_woready_1_430 = _out_wofireMux_T_1036; // @[RegisterRouter.scala:87:24] assign out_woready_1_431 = _out_wofireMux_T_1036; // @[RegisterRouter.scala:87:24] assign out_woready_1_432 = _out_wofireMux_T_1036; // @[RegisterRouter.scala:87:24] assign out_woready_1_433 = _out_wofireMux_T_1036; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1037 = ~_out_T_1709; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1039 = _out_wofireMux_T_262 & out_backSel_194; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1040 = _out_wofireMux_T_1039 & _out_T_1817; // @[RegisterRouter.scala:87:24] assign out_woready_1_835 = _out_wofireMux_T_1040; // @[RegisterRouter.scala:87:24] assign out_woready_1_836 = _out_wofireMux_T_1040; // @[RegisterRouter.scala:87:24] assign out_woready_1_837 = _out_wofireMux_T_1040; // @[RegisterRouter.scala:87:24] assign out_woready_1_838 = _out_wofireMux_T_1040; // @[RegisterRouter.scala:87:24] assign out_woready_1_839 = _out_wofireMux_T_1040; // @[RegisterRouter.scala:87:24] assign out_woready_1_840 = _out_wofireMux_T_1040; // @[RegisterRouter.scala:87:24] assign out_woready_1_841 = _out_wofireMux_T_1040; // @[RegisterRouter.scala:87:24] assign out_woready_1_842 = _out_wofireMux_T_1040; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1041 = ~_out_T_1817; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1043 = _out_wofireMux_T_262 & out_backSel_195; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1044 = _out_wofireMux_T_1043 & _out_T_1885; // @[RegisterRouter.scala:87:24] assign out_woready_1_1107 = _out_wofireMux_T_1044; // @[RegisterRouter.scala:87:24] assign out_woready_1_1108 = _out_wofireMux_T_1044; // @[RegisterRouter.scala:87:24] assign out_woready_1_1109 = _out_wofireMux_T_1044; // @[RegisterRouter.scala:87:24] assign out_woready_1_1110 = _out_wofireMux_T_1044; // @[RegisterRouter.scala:87:24] assign out_woready_1_1111 = _out_wofireMux_T_1044; // @[RegisterRouter.scala:87:24] assign out_woready_1_1112 = _out_wofireMux_T_1044; // @[RegisterRouter.scala:87:24] assign out_woready_1_1113 = _out_wofireMux_T_1044; // @[RegisterRouter.scala:87:24] assign out_woready_1_1114 = _out_wofireMux_T_1044; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1045 = ~_out_T_1885; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1047 = _out_wofireMux_T_262 & out_backSel_196; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1048 = _out_wofireMux_T_1047 & _out_T_1631; // @[RegisterRouter.scala:87:24] assign out_woready_1_120 = _out_wofireMux_T_1048; // @[RegisterRouter.scala:87:24] assign out_woready_1_121 = _out_wofireMux_T_1048; // @[RegisterRouter.scala:87:24] assign out_woready_1_122 = _out_wofireMux_T_1048; // @[RegisterRouter.scala:87:24] assign out_woready_1_123 = _out_wofireMux_T_1048; // @[RegisterRouter.scala:87:24] assign out_woready_1_124 = _out_wofireMux_T_1048; // @[RegisterRouter.scala:87:24] assign out_woready_1_125 = _out_wofireMux_T_1048; // @[RegisterRouter.scala:87:24] assign out_woready_1_126 = _out_wofireMux_T_1048; // @[RegisterRouter.scala:87:24] assign out_woready_1_127 = _out_wofireMux_T_1048; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1049 = ~_out_T_1631; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1051 = _out_wofireMux_T_262 & out_backSel_197; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1052 = _out_wofireMux_T_1051 & _out_T_1695; // @[RegisterRouter.scala:87:24] assign out_woready_1_370 = _out_wofireMux_T_1052; // @[RegisterRouter.scala:87:24] assign out_woready_1_371 = _out_wofireMux_T_1052; // @[RegisterRouter.scala:87:24] assign out_woready_1_372 = _out_wofireMux_T_1052; // @[RegisterRouter.scala:87:24] assign out_woready_1_373 = _out_wofireMux_T_1052; // @[RegisterRouter.scala:87:24] assign out_woready_1_374 = _out_wofireMux_T_1052; // @[RegisterRouter.scala:87:24] assign out_woready_1_375 = _out_wofireMux_T_1052; // @[RegisterRouter.scala:87:24] assign out_woready_1_376 = _out_wofireMux_T_1052; // @[RegisterRouter.scala:87:24] assign out_woready_1_377 = _out_wofireMux_T_1052; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1053 = ~_out_T_1695; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1055 = _out_wofireMux_T_262 & out_backSel_198; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1056 = _out_wofireMux_T_1055 & _out_T_1789; // @[RegisterRouter.scala:87:24] assign out_woready_1_723 = _out_wofireMux_T_1056; // @[RegisterRouter.scala:87:24] assign out_woready_1_724 = _out_wofireMux_T_1056; // @[RegisterRouter.scala:87:24] assign out_woready_1_725 = _out_wofireMux_T_1056; // @[RegisterRouter.scala:87:24] assign out_woready_1_726 = _out_wofireMux_T_1056; // @[RegisterRouter.scala:87:24] assign out_woready_1_727 = _out_wofireMux_T_1056; // @[RegisterRouter.scala:87:24] assign out_woready_1_728 = _out_wofireMux_T_1056; // @[RegisterRouter.scala:87:24] assign out_woready_1_729 = _out_wofireMux_T_1056; // @[RegisterRouter.scala:87:24] assign out_woready_1_730 = _out_wofireMux_T_1056; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1057 = ~_out_T_1789; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1059 = _out_wofireMux_T_262 & out_backSel_199; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1060 = _out_wofireMux_T_1059 & _out_T_1825; // @[RegisterRouter.scala:87:24] assign out_woready_1_867 = _out_wofireMux_T_1060; // @[RegisterRouter.scala:87:24] assign out_woready_1_868 = _out_wofireMux_T_1060; // @[RegisterRouter.scala:87:24] assign out_woready_1_869 = _out_wofireMux_T_1060; // @[RegisterRouter.scala:87:24] assign out_woready_1_870 = _out_wofireMux_T_1060; // @[RegisterRouter.scala:87:24] assign out_woready_1_871 = _out_wofireMux_T_1060; // @[RegisterRouter.scala:87:24] assign out_woready_1_872 = _out_wofireMux_T_1060; // @[RegisterRouter.scala:87:24] assign out_woready_1_873 = _out_wofireMux_T_1060; // @[RegisterRouter.scala:87:24] assign out_woready_1_874 = _out_wofireMux_T_1060; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1061 = ~_out_T_1825; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1063 = _out_wofireMux_T_262 & out_backSel_200; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1064 = _out_wofireMux_T_1063 & _out_T_1897; // @[RegisterRouter.scala:87:24] assign out_woready_1_1155 = _out_wofireMux_T_1064; // @[RegisterRouter.scala:87:24] assign out_woready_1_1156 = _out_wofireMux_T_1064; // @[RegisterRouter.scala:87:24] assign out_woready_1_1157 = _out_wofireMux_T_1064; // @[RegisterRouter.scala:87:24] assign out_woready_1_1158 = _out_wofireMux_T_1064; // @[RegisterRouter.scala:87:24] assign out_woready_1_1159 = _out_wofireMux_T_1064; // @[RegisterRouter.scala:87:24] assign out_woready_1_1160 = _out_wofireMux_T_1064; // @[RegisterRouter.scala:87:24] assign out_woready_1_1161 = _out_wofireMux_T_1064; // @[RegisterRouter.scala:87:24] assign out_woready_1_1162 = _out_wofireMux_T_1064; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1065 = ~_out_T_1897; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1067 = _out_wofireMux_T_262 & out_backSel_201; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1068 = _out_wofireMux_T_1067 & _out_T_1675; // @[RegisterRouter.scala:87:24] assign out_woready_1_296 = _out_wofireMux_T_1068; // @[RegisterRouter.scala:87:24] assign out_woready_1_297 = _out_wofireMux_T_1068; // @[RegisterRouter.scala:87:24] assign out_woready_1_298 = _out_wofireMux_T_1068; // @[RegisterRouter.scala:87:24] assign out_woready_1_299 = _out_wofireMux_T_1068; // @[RegisterRouter.scala:87:24] assign out_woready_1_300 = _out_wofireMux_T_1068; // @[RegisterRouter.scala:87:24] assign out_woready_1_301 = _out_wofireMux_T_1068; // @[RegisterRouter.scala:87:24] assign out_woready_1_302 = _out_wofireMux_T_1068; // @[RegisterRouter.scala:87:24] assign out_woready_1_303 = _out_wofireMux_T_1068; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1069 = ~_out_T_1675; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1071 = _out_wofireMux_T_262 & out_backSel_202; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1072 = _out_wofireMux_T_1071 & _out_T_1615; // @[RegisterRouter.scala:87:24] assign out_woready_1_56 = _out_wofireMux_T_1072; // @[RegisterRouter.scala:87:24] assign out_woready_1_57 = _out_wofireMux_T_1072; // @[RegisterRouter.scala:87:24] assign out_woready_1_58 = _out_wofireMux_T_1072; // @[RegisterRouter.scala:87:24] assign out_woready_1_59 = _out_wofireMux_T_1072; // @[RegisterRouter.scala:87:24] assign out_woready_1_60 = _out_wofireMux_T_1072; // @[RegisterRouter.scala:87:24] assign out_woready_1_61 = _out_wofireMux_T_1072; // @[RegisterRouter.scala:87:24] assign out_woready_1_62 = _out_wofireMux_T_1072; // @[RegisterRouter.scala:87:24] assign out_woready_1_63 = _out_wofireMux_T_1072; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1073 = ~_out_T_1615; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1075 = _out_wofireMux_T_262 & out_backSel_203; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1076 = _out_wofireMux_T_1075 & _out_T_1837; // @[RegisterRouter.scala:87:24] assign out_woready_1_915 = _out_wofireMux_T_1076; // @[RegisterRouter.scala:87:24] assign out_woready_1_916 = _out_wofireMux_T_1076; // @[RegisterRouter.scala:87:24] assign out_woready_1_917 = _out_wofireMux_T_1076; // @[RegisterRouter.scala:87:24] assign out_woready_1_918 = _out_wofireMux_T_1076; // @[RegisterRouter.scala:87:24] assign out_woready_1_919 = _out_wofireMux_T_1076; // @[RegisterRouter.scala:87:24] assign out_woready_1_920 = _out_wofireMux_T_1076; // @[RegisterRouter.scala:87:24] assign out_woready_1_921 = _out_wofireMux_T_1076; // @[RegisterRouter.scala:87:24] assign out_woready_1_922 = _out_wofireMux_T_1076; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1077 = ~_out_T_1837; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1079 = _out_wofireMux_T_262 & out_backSel_204; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1080 = _out_wofireMux_T_1079 & _out_T_1755; // @[RegisterRouter.scala:87:24] assign out_woready_1_593 = _out_wofireMux_T_1080; // @[RegisterRouter.scala:87:24] assign out_woready_1_594 = _out_wofireMux_T_1080; // @[RegisterRouter.scala:87:24] assign out_woready_1_595 = _out_wofireMux_T_1080; // @[RegisterRouter.scala:87:24] assign out_woready_1_596 = _out_wofireMux_T_1080; // @[RegisterRouter.scala:87:24] assign out_woready_1_597 = _out_wofireMux_T_1080; // @[RegisterRouter.scala:87:24] assign out_woready_1_598 = _out_wofireMux_T_1080; // @[RegisterRouter.scala:87:24] assign out_woready_1_599 = _out_wofireMux_T_1080; // @[RegisterRouter.scala:87:24] assign out_woready_1_600 = _out_wofireMux_T_1080; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1081 = ~_out_T_1755; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1083 = _out_wofireMux_T_262 & out_backSel_205; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1084 = _out_wofireMux_T_1083 & _out_T_1727; // @[RegisterRouter.scala:87:24] assign out_woready_1_487 = _out_wofireMux_T_1084; // @[RegisterRouter.scala:87:24] assign out_woready_1_488 = _out_wofireMux_T_1084; // @[RegisterRouter.scala:87:24] assign out_woready_1_489 = _out_wofireMux_T_1084; // @[RegisterRouter.scala:87:24] assign out_woready_1_490 = _out_wofireMux_T_1084; // @[RegisterRouter.scala:87:24] assign out_woready_1_491 = _out_wofireMux_T_1084; // @[RegisterRouter.scala:87:24] assign out_woready_1_492 = _out_wofireMux_T_1084; // @[RegisterRouter.scala:87:24] assign out_woready_1_493 = _out_wofireMux_T_1084; // @[RegisterRouter.scala:87:24] assign out_woready_1_494 = _out_wofireMux_T_1084; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1085 = ~_out_T_1727; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1087 = _out_wofireMux_T_262 & out_backSel_206; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1088 = _out_wofireMux_T_1087 & _out_T_1669; // @[RegisterRouter.scala:87:24] assign out_woready_1_272 = _out_wofireMux_T_1088; // @[RegisterRouter.scala:87:24] assign out_woready_1_273 = _out_wofireMux_T_1088; // @[RegisterRouter.scala:87:24] assign out_woready_1_274 = _out_wofireMux_T_1088; // @[RegisterRouter.scala:87:24] assign out_woready_1_275 = _out_wofireMux_T_1088; // @[RegisterRouter.scala:87:24] assign out_woready_1_276 = _out_wofireMux_T_1088; // @[RegisterRouter.scala:87:24] assign out_woready_1_277 = _out_wofireMux_T_1088; // @[RegisterRouter.scala:87:24] assign out_woready_1_278 = _out_wofireMux_T_1088; // @[RegisterRouter.scala:87:24] assign out_woready_1_279 = _out_wofireMux_T_1088; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1089 = ~_out_T_1669; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1091 = _out_wofireMux_T_262 & out_backSel_207; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1092 = _out_wofireMux_T_1091 & _out_T_1859; // @[RegisterRouter.scala:87:24] assign out_woready_1_1003 = _out_wofireMux_T_1092; // @[RegisterRouter.scala:87:24] assign out_woready_1_1004 = _out_wofireMux_T_1092; // @[RegisterRouter.scala:87:24] assign out_woready_1_1005 = _out_wofireMux_T_1092; // @[RegisterRouter.scala:87:24] assign out_woready_1_1006 = _out_wofireMux_T_1092; // @[RegisterRouter.scala:87:24] assign out_woready_1_1007 = _out_wofireMux_T_1092; // @[RegisterRouter.scala:87:24] assign out_woready_1_1008 = _out_wofireMux_T_1092; // @[RegisterRouter.scala:87:24] assign out_woready_1_1009 = _out_wofireMux_T_1092; // @[RegisterRouter.scala:87:24] assign out_woready_1_1010 = _out_wofireMux_T_1092; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1093 = ~_out_T_1859; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1095 = _out_wofireMux_T_262 & out_backSel_208; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1096 = _out_wofireMux_T_1095 & _out_T_1779; // @[RegisterRouter.scala:87:24] assign out_woready_1_689 = _out_wofireMux_T_1096; // @[RegisterRouter.scala:87:24] assign out_woready_1_690 = _out_wofireMux_T_1096; // @[RegisterRouter.scala:87:24] assign out_woready_1_691 = _out_wofireMux_T_1096; // @[RegisterRouter.scala:87:24] assign out_woready_1_692 = _out_wofireMux_T_1096; // @[RegisterRouter.scala:87:24] assign out_woready_1_693 = _out_wofireMux_T_1096; // @[RegisterRouter.scala:87:24] assign out_woready_1_694 = _out_wofireMux_T_1096; // @[RegisterRouter.scala:87:24] assign out_woready_1_695 = _out_wofireMux_T_1096; // @[RegisterRouter.scala:87:24] assign out_woready_1_696 = _out_wofireMux_T_1096; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1097 = ~_out_T_1779; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1099 = _out_wofireMux_T_262 & out_backSel_209; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1100 = _out_wofireMux_T_1099 & _out_T_1813; // @[RegisterRouter.scala:87:24] assign out_woready_1_819 = _out_wofireMux_T_1100; // @[RegisterRouter.scala:87:24] assign out_woready_1_820 = _out_wofireMux_T_1100; // @[RegisterRouter.scala:87:24] assign out_woready_1_821 = _out_wofireMux_T_1100; // @[RegisterRouter.scala:87:24] assign out_woready_1_822 = _out_wofireMux_T_1100; // @[RegisterRouter.scala:87:24] assign out_woready_1_823 = _out_wofireMux_T_1100; // @[RegisterRouter.scala:87:24] assign out_woready_1_824 = _out_wofireMux_T_1100; // @[RegisterRouter.scala:87:24] assign out_woready_1_825 = _out_wofireMux_T_1100; // @[RegisterRouter.scala:87:24] assign out_woready_1_826 = _out_wofireMux_T_1100; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1101 = ~_out_T_1813; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1103 = _out_wofireMux_T_262 & out_backSel_210; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1104 = _out_wofireMux_T_1103 & _out_T_1879; // @[RegisterRouter.scala:87:24] assign out_woready_1_1083 = _out_wofireMux_T_1104; // @[RegisterRouter.scala:87:24] assign out_woready_1_1084 = _out_wofireMux_T_1104; // @[RegisterRouter.scala:87:24] assign out_woready_1_1085 = _out_wofireMux_T_1104; // @[RegisterRouter.scala:87:24] assign out_woready_1_1086 = _out_wofireMux_T_1104; // @[RegisterRouter.scala:87:24] assign out_woready_1_1087 = _out_wofireMux_T_1104; // @[RegisterRouter.scala:87:24] assign out_woready_1_1088 = _out_wofireMux_T_1104; // @[RegisterRouter.scala:87:24] assign out_woready_1_1089 = _out_wofireMux_T_1104; // @[RegisterRouter.scala:87:24] assign out_woready_1_1090 = _out_wofireMux_T_1104; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1105 = ~_out_T_1879; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1107 = _out_wofireMux_T_262 & out_backSel_211; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1108 = _out_wofireMux_T_1107 & _out_T_1653; // @[RegisterRouter.scala:87:24] assign out_woready_1_208 = _out_wofireMux_T_1108; // @[RegisterRouter.scala:87:24] assign out_woready_1_209 = _out_wofireMux_T_1108; // @[RegisterRouter.scala:87:24] assign out_woready_1_210 = _out_wofireMux_T_1108; // @[RegisterRouter.scala:87:24] assign out_woready_1_211 = _out_wofireMux_T_1108; // @[RegisterRouter.scala:87:24] assign out_woready_1_212 = _out_wofireMux_T_1108; // @[RegisterRouter.scala:87:24] assign out_woready_1_213 = _out_wofireMux_T_1108; // @[RegisterRouter.scala:87:24] assign out_woready_1_214 = _out_wofireMux_T_1108; // @[RegisterRouter.scala:87:24] assign out_woready_1_215 = _out_wofireMux_T_1108; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1109 = ~_out_T_1653; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1111 = _out_wofireMux_T_262 & out_backSel_212; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1112 = _out_wofireMux_T_1111 & _out_T_1711; // @[RegisterRouter.scala:87:24] assign out_woready_1_434 = _out_wofireMux_T_1112; // @[RegisterRouter.scala:87:24] assign out_woready_1_435 = _out_wofireMux_T_1112; // @[RegisterRouter.scala:87:24] assign out_woready_1_436 = _out_wofireMux_T_1112; // @[RegisterRouter.scala:87:24] assign out_woready_1_437 = _out_wofireMux_T_1112; // @[RegisterRouter.scala:87:24] assign out_woready_1_438 = _out_wofireMux_T_1112; // @[RegisterRouter.scala:87:24] assign out_woready_1_439 = _out_wofireMux_T_1112; // @[RegisterRouter.scala:87:24] assign out_woready_1_440 = _out_wofireMux_T_1112; // @[RegisterRouter.scala:87:24] assign out_woready_1_441 = _out_wofireMux_T_1112; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1113 = ~_out_T_1711; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1115 = _out_wofireMux_T_262 & out_backSel_213; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1116 = _out_wofireMux_T_1115 & _out_T_1785; // @[RegisterRouter.scala:87:24] assign out_woready_1_707 = _out_wofireMux_T_1116; // @[RegisterRouter.scala:87:24] assign out_woready_1_708 = _out_wofireMux_T_1116; // @[RegisterRouter.scala:87:24] assign out_woready_1_709 = _out_wofireMux_T_1116; // @[RegisterRouter.scala:87:24] assign out_woready_1_710 = _out_wofireMux_T_1116; // @[RegisterRouter.scala:87:24] assign out_woready_1_711 = _out_wofireMux_T_1116; // @[RegisterRouter.scala:87:24] assign out_woready_1_712 = _out_wofireMux_T_1116; // @[RegisterRouter.scala:87:24] assign out_woready_1_713 = _out_wofireMux_T_1116; // @[RegisterRouter.scala:87:24] assign out_woready_1_714 = _out_wofireMux_T_1116; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1117 = ~_out_T_1785; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1119 = _out_wofireMux_T_262 & out_backSel_214; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1120 = _out_wofireMux_T_1119 & _out_T_1861; // @[RegisterRouter.scala:87:24] assign out_woready_1_1011 = _out_wofireMux_T_1120; // @[RegisterRouter.scala:87:24] assign out_woready_1_1012 = _out_wofireMux_T_1120; // @[RegisterRouter.scala:87:24] assign out_woready_1_1013 = _out_wofireMux_T_1120; // @[RegisterRouter.scala:87:24] assign out_woready_1_1014 = _out_wofireMux_T_1120; // @[RegisterRouter.scala:87:24] assign out_woready_1_1015 = _out_wofireMux_T_1120; // @[RegisterRouter.scala:87:24] assign out_woready_1_1016 = _out_wofireMux_T_1120; // @[RegisterRouter.scala:87:24] assign out_woready_1_1017 = _out_wofireMux_T_1120; // @[RegisterRouter.scala:87:24] assign out_woready_1_1018 = _out_wofireMux_T_1120; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1121 = ~_out_T_1861; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1123 = _out_wofireMux_T_262 & out_backSel_215; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1124 = _out_wofireMux_T_1123 & _out_T_1901; // @[RegisterRouter.scala:87:24] assign out_woready_1_1171 = _out_wofireMux_T_1124; // @[RegisterRouter.scala:87:24] assign out_woready_1_1172 = _out_wofireMux_T_1124; // @[RegisterRouter.scala:87:24] assign out_woready_1_1173 = _out_wofireMux_T_1124; // @[RegisterRouter.scala:87:24] assign out_woready_1_1174 = _out_wofireMux_T_1124; // @[RegisterRouter.scala:87:24] assign out_woready_1_1175 = _out_wofireMux_T_1124; // @[RegisterRouter.scala:87:24] assign out_woready_1_1176 = _out_wofireMux_T_1124; // @[RegisterRouter.scala:87:24] assign out_woready_1_1177 = _out_wofireMux_T_1124; // @[RegisterRouter.scala:87:24] assign out_woready_1_1178 = _out_wofireMux_T_1124; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1125 = ~_out_T_1901; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1127 = _out_wofireMux_T_262 & out_backSel_216; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1128 = _out_wofireMux_T_1127 & _out_T_1643; // @[RegisterRouter.scala:87:24] assign out_woready_1_168 = _out_wofireMux_T_1128; // @[RegisterRouter.scala:87:24] assign out_woready_1_169 = _out_wofireMux_T_1128; // @[RegisterRouter.scala:87:24] assign out_woready_1_170 = _out_wofireMux_T_1128; // @[RegisterRouter.scala:87:24] assign out_woready_1_171 = _out_wofireMux_T_1128; // @[RegisterRouter.scala:87:24] assign out_woready_1_172 = _out_wofireMux_T_1128; // @[RegisterRouter.scala:87:24] assign out_woready_1_173 = _out_wofireMux_T_1128; // @[RegisterRouter.scala:87:24] assign out_woready_1_174 = _out_wofireMux_T_1128; // @[RegisterRouter.scala:87:24] assign out_woready_1_175 = _out_wofireMux_T_1128; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1129 = ~_out_T_1643; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1131 = _out_wofireMux_T_262 & out_backSel_217; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1132 = _out_wofireMux_T_1131 & _out_T_1611; // @[RegisterRouter.scala:87:24] assign out_woready_1_40 = _out_wofireMux_T_1132; // @[RegisterRouter.scala:87:24] assign out_woready_1_41 = _out_wofireMux_T_1132; // @[RegisterRouter.scala:87:24] assign out_woready_1_42 = _out_wofireMux_T_1132; // @[RegisterRouter.scala:87:24] assign out_woready_1_43 = _out_wofireMux_T_1132; // @[RegisterRouter.scala:87:24] assign out_woready_1_44 = _out_wofireMux_T_1132; // @[RegisterRouter.scala:87:24] assign out_woready_1_45 = _out_wofireMux_T_1132; // @[RegisterRouter.scala:87:24] assign out_woready_1_46 = _out_wofireMux_T_1132; // @[RegisterRouter.scala:87:24] assign out_woready_1_47 = _out_wofireMux_T_1132; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1133 = ~_out_T_1611; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1135 = _out_wofireMux_T_262 & out_backSel_218; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1136 = _out_wofireMux_T_1135 & _out_T_1839; // @[RegisterRouter.scala:87:24] assign out_woready_1_923 = _out_wofireMux_T_1136; // @[RegisterRouter.scala:87:24] assign out_woready_1_924 = _out_wofireMux_T_1136; // @[RegisterRouter.scala:87:24] assign out_woready_1_925 = _out_wofireMux_T_1136; // @[RegisterRouter.scala:87:24] assign out_woready_1_926 = _out_wofireMux_T_1136; // @[RegisterRouter.scala:87:24] assign out_woready_1_927 = _out_wofireMux_T_1136; // @[RegisterRouter.scala:87:24] assign out_woready_1_928 = _out_wofireMux_T_1136; // @[RegisterRouter.scala:87:24] assign out_woready_1_929 = _out_wofireMux_T_1136; // @[RegisterRouter.scala:87:24] assign out_woready_1_930 = _out_wofireMux_T_1136; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1137 = ~_out_T_1839; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1139 = _out_wofireMux_T_262 & out_backSel_219; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1140 = _out_wofireMux_T_1139 & _out_T_1773; // @[RegisterRouter.scala:87:24] assign out_woready_1_665 = _out_wofireMux_T_1140; // @[RegisterRouter.scala:87:24] assign out_woready_1_666 = _out_wofireMux_T_1140; // @[RegisterRouter.scala:87:24] assign out_woready_1_667 = _out_wofireMux_T_1140; // @[RegisterRouter.scala:87:24] assign out_woready_1_668 = _out_wofireMux_T_1140; // @[RegisterRouter.scala:87:24] assign out_woready_1_669 = _out_wofireMux_T_1140; // @[RegisterRouter.scala:87:24] assign out_woready_1_670 = _out_wofireMux_T_1140; // @[RegisterRouter.scala:87:24] assign out_woready_1_671 = _out_wofireMux_T_1140; // @[RegisterRouter.scala:87:24] assign out_woready_1_672 = _out_wofireMux_T_1140; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1141 = ~_out_T_1773; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1143 = _out_wofireMux_T_262 & out_backSel_220; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1144 = _out_wofireMux_T_1143 & _out_T_1677; // @[RegisterRouter.scala:87:24] assign out_woready_1_304 = _out_wofireMux_T_1144; // @[RegisterRouter.scala:87:24] assign out_woready_1_305 = _out_wofireMux_T_1144; // @[RegisterRouter.scala:87:24] assign out_woready_1_306 = _out_wofireMux_T_1144; // @[RegisterRouter.scala:87:24] assign out_woready_1_307 = _out_wofireMux_T_1144; // @[RegisterRouter.scala:87:24] assign out_woready_1_308 = _out_wofireMux_T_1144; // @[RegisterRouter.scala:87:24] assign out_woready_1_309 = _out_wofireMux_T_1144; // @[RegisterRouter.scala:87:24] assign out_woready_1_310 = _out_wofireMux_T_1144; // @[RegisterRouter.scala:87:24] assign out_woready_1_311 = _out_wofireMux_T_1144; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1145 = ~_out_T_1677; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1147 = _out_wofireMux_T_262 & out_backSel_221; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1148 = _out_wofireMux_T_1147 & _out_T_1659; // @[RegisterRouter.scala:87:24] assign out_woready_1_232 = _out_wofireMux_T_1148; // @[RegisterRouter.scala:87:24] assign out_woready_1_233 = _out_wofireMux_T_1148; // @[RegisterRouter.scala:87:24] assign out_woready_1_234 = _out_wofireMux_T_1148; // @[RegisterRouter.scala:87:24] assign out_woready_1_235 = _out_wofireMux_T_1148; // @[RegisterRouter.scala:87:24] assign out_woready_1_236 = _out_wofireMux_T_1148; // @[RegisterRouter.scala:87:24] assign out_woready_1_237 = _out_wofireMux_T_1148; // @[RegisterRouter.scala:87:24] assign out_woready_1_238 = _out_wofireMux_T_1148; // @[RegisterRouter.scala:87:24] assign out_woready_1_239 = _out_wofireMux_T_1148; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1149 = ~_out_T_1659; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1151 = _out_wofireMux_T_262 & out_backSel_222; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1152 = _out_wofireMux_T_1151 & _out_T_1903; // @[RegisterRouter.scala:87:24] assign out_woready_1_1179 = _out_wofireMux_T_1152; // @[RegisterRouter.scala:87:24] assign out_woready_1_1180 = _out_wofireMux_T_1152; // @[RegisterRouter.scala:87:24] assign out_woready_1_1181 = _out_wofireMux_T_1152; // @[RegisterRouter.scala:87:24] assign out_woready_1_1182 = _out_wofireMux_T_1152; // @[RegisterRouter.scala:87:24] assign out_woready_1_1183 = _out_wofireMux_T_1152; // @[RegisterRouter.scala:87:24] assign out_woready_1_1184 = _out_wofireMux_T_1152; // @[RegisterRouter.scala:87:24] assign out_woready_1_1185 = _out_wofireMux_T_1152; // @[RegisterRouter.scala:87:24] assign out_woready_1_1186 = _out_wofireMux_T_1152; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1153 = ~_out_T_1903; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1155 = _out_wofireMux_T_262 & out_backSel_223; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1156 = _out_wofireMux_T_1155 & _out_T_1799; // @[RegisterRouter.scala:87:24] assign out_woready_1_763 = _out_wofireMux_T_1156; // @[RegisterRouter.scala:87:24] assign out_woready_1_764 = _out_wofireMux_T_1156; // @[RegisterRouter.scala:87:24] assign out_woready_1_765 = _out_wofireMux_T_1156; // @[RegisterRouter.scala:87:24] assign out_woready_1_766 = _out_wofireMux_T_1156; // @[RegisterRouter.scala:87:24] assign out_woready_1_767 = _out_wofireMux_T_1156; // @[RegisterRouter.scala:87:24] assign out_woready_1_768 = _out_wofireMux_T_1156; // @[RegisterRouter.scala:87:24] assign out_woready_1_769 = _out_wofireMux_T_1156; // @[RegisterRouter.scala:87:24] assign out_woready_1_770 = _out_wofireMux_T_1156; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1157 = ~_out_T_1799; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1159 = _out_wofireMux_T_262 & out_backSel_224; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1160 = _out_wofireMux_T_1159 & _out_T_1697; // @[RegisterRouter.scala:87:24] assign out_woready_1_378 = _out_wofireMux_T_1160; // @[RegisterRouter.scala:87:24] assign out_woready_1_379 = _out_wofireMux_T_1160; // @[RegisterRouter.scala:87:24] assign out_woready_1_380 = _out_wofireMux_T_1160; // @[RegisterRouter.scala:87:24] assign out_woready_1_381 = _out_wofireMux_T_1160; // @[RegisterRouter.scala:87:24] assign out_woready_1_382 = _out_wofireMux_T_1160; // @[RegisterRouter.scala:87:24] assign out_woready_1_383 = _out_wofireMux_T_1160; // @[RegisterRouter.scala:87:24] assign out_woready_1_384 = _out_wofireMux_T_1160; // @[RegisterRouter.scala:87:24] assign out_woready_1_385 = _out_wofireMux_T_1160; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1161 = ~_out_T_1697; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1163 = _out_wofireMux_T_262 & out_backSel_225; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1164 = _out_wofireMux_T_1163 & _out_T_1707; // @[RegisterRouter.scala:87:24] assign out_woready_1_418 = _out_wofireMux_T_1164; // @[RegisterRouter.scala:87:24] assign out_woready_1_419 = _out_wofireMux_T_1164; // @[RegisterRouter.scala:87:24] assign out_woready_1_420 = _out_wofireMux_T_1164; // @[RegisterRouter.scala:87:24] assign out_woready_1_421 = _out_wofireMux_T_1164; // @[RegisterRouter.scala:87:24] assign out_woready_1_422 = _out_wofireMux_T_1164; // @[RegisterRouter.scala:87:24] assign out_woready_1_423 = _out_wofireMux_T_1164; // @[RegisterRouter.scala:87:24] assign out_woready_1_424 = _out_wofireMux_T_1164; // @[RegisterRouter.scala:87:24] assign out_woready_1_425 = _out_wofireMux_T_1164; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1165 = ~_out_T_1707; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1167 = _out_wofireMux_T_262 & out_backSel_226; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1168 = _out_wofireMux_T_1167 & _out_T_1803; // @[RegisterRouter.scala:87:24] assign out_woready_1_779 = _out_wofireMux_T_1168; // @[RegisterRouter.scala:87:24] assign out_woready_1_780 = _out_wofireMux_T_1168; // @[RegisterRouter.scala:87:24] assign out_woready_1_781 = _out_wofireMux_T_1168; // @[RegisterRouter.scala:87:24] assign out_woready_1_782 = _out_wofireMux_T_1168; // @[RegisterRouter.scala:87:24] assign out_woready_1_783 = _out_wofireMux_T_1168; // @[RegisterRouter.scala:87:24] assign out_woready_1_784 = _out_wofireMux_T_1168; // @[RegisterRouter.scala:87:24] assign out_woready_1_785 = _out_wofireMux_T_1168; // @[RegisterRouter.scala:87:24] assign out_woready_1_786 = _out_wofireMux_T_1168; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1169 = ~_out_T_1803; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1171 = _out_wofireMux_T_262 & out_backSel_227; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1172 = _out_wofireMux_T_1171 & _out_T_1909; // @[RegisterRouter.scala:87:24] assign out_woready_1_1203 = _out_wofireMux_T_1172; // @[RegisterRouter.scala:87:24] assign out_woready_1_1204 = _out_wofireMux_T_1172; // @[RegisterRouter.scala:87:24] assign out_woready_1_1205 = _out_wofireMux_T_1172; // @[RegisterRouter.scala:87:24] assign out_woready_1_1206 = _out_wofireMux_T_1172; // @[RegisterRouter.scala:87:24] assign out_woready_1_1207 = _out_wofireMux_T_1172; // @[RegisterRouter.scala:87:24] assign out_woready_1_1208 = _out_wofireMux_T_1172; // @[RegisterRouter.scala:87:24] assign out_woready_1_1209 = _out_wofireMux_T_1172; // @[RegisterRouter.scala:87:24] assign out_woready_1_1210 = _out_wofireMux_T_1172; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1173 = ~_out_T_1909; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1175 = _out_wofireMux_T_262 & out_backSel_228; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1176 = _out_wofireMux_T_1175 & _out_T_1639; // @[RegisterRouter.scala:87:24] assign out_woready_1_152 = _out_wofireMux_T_1176; // @[RegisterRouter.scala:87:24] assign out_woready_1_153 = _out_wofireMux_T_1176; // @[RegisterRouter.scala:87:24] assign out_woready_1_154 = _out_wofireMux_T_1176; // @[RegisterRouter.scala:87:24] assign out_woready_1_155 = _out_wofireMux_T_1176; // @[RegisterRouter.scala:87:24] assign out_woready_1_156 = _out_wofireMux_T_1176; // @[RegisterRouter.scala:87:24] assign out_woready_1_157 = _out_wofireMux_T_1176; // @[RegisterRouter.scala:87:24] assign out_woready_1_158 = _out_wofireMux_T_1176; // @[RegisterRouter.scala:87:24] assign out_woready_1_159 = _out_wofireMux_T_1176; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1177 = ~_out_T_1639; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1179 = _out_wofireMux_T_262 & out_backSel_229; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1180 = _out_wofireMux_T_1179 & _out_T_1691; // @[RegisterRouter.scala:87:24] assign out_woready_1_354 = _out_wofireMux_T_1180; // @[RegisterRouter.scala:87:24] assign out_woready_1_355 = _out_wofireMux_T_1180; // @[RegisterRouter.scala:87:24] assign out_woready_1_356 = _out_wofireMux_T_1180; // @[RegisterRouter.scala:87:24] assign out_woready_1_357 = _out_wofireMux_T_1180; // @[RegisterRouter.scala:87:24] assign out_woready_1_358 = _out_wofireMux_T_1180; // @[RegisterRouter.scala:87:24] assign out_woready_1_359 = _out_wofireMux_T_1180; // @[RegisterRouter.scala:87:24] assign out_woready_1_360 = _out_wofireMux_T_1180; // @[RegisterRouter.scala:87:24] assign out_woready_1_361 = _out_wofireMux_T_1180; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1181 = ~_out_T_1691; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1183 = _out_wofireMux_T_262 & out_backSel_230; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1184 = _out_wofireMux_T_1183 & _out_T_1775; // @[RegisterRouter.scala:87:24] assign out_woready_1_673 = _out_wofireMux_T_1184; // @[RegisterRouter.scala:87:24] assign out_woready_1_674 = _out_wofireMux_T_1184; // @[RegisterRouter.scala:87:24] assign out_woready_1_675 = _out_wofireMux_T_1184; // @[RegisterRouter.scala:87:24] assign out_woready_1_676 = _out_wofireMux_T_1184; // @[RegisterRouter.scala:87:24] assign out_woready_1_677 = _out_wofireMux_T_1184; // @[RegisterRouter.scala:87:24] assign out_woready_1_678 = _out_wofireMux_T_1184; // @[RegisterRouter.scala:87:24] assign out_woready_1_679 = _out_wofireMux_T_1184; // @[RegisterRouter.scala:87:24] assign out_woready_1_680 = _out_wofireMux_T_1184; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1185 = ~_out_T_1775; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1187 = _out_wofireMux_T_262 & out_backSel_231; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1188 = _out_wofireMux_T_1187 & _out_T_1845; // @[RegisterRouter.scala:87:24] assign out_woready_1_947 = _out_wofireMux_T_1188; // @[RegisterRouter.scala:87:24] assign out_woready_1_948 = _out_wofireMux_T_1188; // @[RegisterRouter.scala:87:24] assign out_woready_1_949 = _out_wofireMux_T_1188; // @[RegisterRouter.scala:87:24] assign out_woready_1_950 = _out_wofireMux_T_1188; // @[RegisterRouter.scala:87:24] assign out_woready_1_951 = _out_wofireMux_T_1188; // @[RegisterRouter.scala:87:24] assign out_woready_1_952 = _out_wofireMux_T_1188; // @[RegisterRouter.scala:87:24] assign out_woready_1_953 = _out_wofireMux_T_1188; // @[RegisterRouter.scala:87:24] assign out_woready_1_954 = _out_wofireMux_T_1188; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1189 = ~_out_T_1845; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1191 = _out_wofireMux_T_262 & out_backSel_232; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1192 = _out_wofireMux_T_1191 & _out_T_1905; // @[RegisterRouter.scala:87:24] assign out_woready_1_1187 = _out_wofireMux_T_1192; // @[RegisterRouter.scala:87:24] assign out_woready_1_1188 = _out_wofireMux_T_1192; // @[RegisterRouter.scala:87:24] assign out_woready_1_1189 = _out_wofireMux_T_1192; // @[RegisterRouter.scala:87:24] assign out_woready_1_1190 = _out_wofireMux_T_1192; // @[RegisterRouter.scala:87:24] assign out_woready_1_1191 = _out_wofireMux_T_1192; // @[RegisterRouter.scala:87:24] assign out_woready_1_1192 = _out_wofireMux_T_1192; // @[RegisterRouter.scala:87:24] assign out_woready_1_1193 = _out_wofireMux_T_1192; // @[RegisterRouter.scala:87:24] assign out_woready_1_1194 = _out_wofireMux_T_1192; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1193 = ~_out_T_1905; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1195 = _out_wofireMux_T_262 & out_backSel_233; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1196 = _out_wofireMux_T_1195 & _out_T_1671; // @[RegisterRouter.scala:87:24] assign out_woready_1_280 = _out_wofireMux_T_1196; // @[RegisterRouter.scala:87:24] assign out_woready_1_281 = _out_wofireMux_T_1196; // @[RegisterRouter.scala:87:24] assign out_woready_1_282 = _out_wofireMux_T_1196; // @[RegisterRouter.scala:87:24] assign out_woready_1_283 = _out_wofireMux_T_1196; // @[RegisterRouter.scala:87:24] assign out_woready_1_284 = _out_wofireMux_T_1196; // @[RegisterRouter.scala:87:24] assign out_woready_1_285 = _out_wofireMux_T_1196; // @[RegisterRouter.scala:87:24] assign out_woready_1_286 = _out_wofireMux_T_1196; // @[RegisterRouter.scala:87:24] assign out_woready_1_287 = _out_wofireMux_T_1196; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1197 = ~_out_T_1671; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1199 = _out_wofireMux_T_262 & out_backSel_234; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1200 = _out_wofireMux_T_1199 & _out_T_1605; // @[RegisterRouter.scala:87:24] assign out_woready_1_16 = _out_wofireMux_T_1200; // @[RegisterRouter.scala:87:24] assign out_woready_1_17 = _out_wofireMux_T_1200; // @[RegisterRouter.scala:87:24] assign out_woready_1_18 = _out_wofireMux_T_1200; // @[RegisterRouter.scala:87:24] assign out_woready_1_19 = _out_wofireMux_T_1200; // @[RegisterRouter.scala:87:24] assign out_woready_1_20 = _out_wofireMux_T_1200; // @[RegisterRouter.scala:87:24] assign out_woready_1_21 = _out_wofireMux_T_1200; // @[RegisterRouter.scala:87:24] assign out_woready_1_22 = _out_wofireMux_T_1200; // @[RegisterRouter.scala:87:24] assign out_woready_1_23 = _out_wofireMux_T_1200; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1201 = ~_out_T_1605; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1203 = _out_wofireMux_T_262 & out_backSel_235; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1204 = _out_wofireMux_T_1203 & _out_T_1863; // @[RegisterRouter.scala:87:24] assign out_woready_1_1019 = _out_wofireMux_T_1204; // @[RegisterRouter.scala:87:24] assign out_woready_1_1020 = _out_wofireMux_T_1204; // @[RegisterRouter.scala:87:24] assign out_woready_1_1021 = _out_wofireMux_T_1204; // @[RegisterRouter.scala:87:24] assign out_woready_1_1022 = _out_wofireMux_T_1204; // @[RegisterRouter.scala:87:24] assign out_woready_1_1023 = _out_wofireMux_T_1204; // @[RegisterRouter.scala:87:24] assign out_woready_1_1024 = _out_wofireMux_T_1204; // @[RegisterRouter.scala:87:24] assign out_woready_1_1025 = _out_wofireMux_T_1204; // @[RegisterRouter.scala:87:24] assign out_woready_1_1026 = _out_wofireMux_T_1204; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1205 = ~_out_T_1863; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1207 = _out_wofireMux_T_262 & out_backSel_236; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1208 = _out_wofireMux_T_1207 & _out_T_1761; // @[RegisterRouter.scala:87:24] assign out_woready_1_617 = _out_wofireMux_T_1208; // @[RegisterRouter.scala:87:24] assign out_woready_1_618 = _out_wofireMux_T_1208; // @[RegisterRouter.scala:87:24] assign out_woready_1_619 = _out_wofireMux_T_1208; // @[RegisterRouter.scala:87:24] assign out_woready_1_620 = _out_wofireMux_T_1208; // @[RegisterRouter.scala:87:24] assign out_woready_1_621 = _out_wofireMux_T_1208; // @[RegisterRouter.scala:87:24] assign out_woready_1_622 = _out_wofireMux_T_1208; // @[RegisterRouter.scala:87:24] assign out_woready_1_623 = _out_wofireMux_T_1208; // @[RegisterRouter.scala:87:24] assign out_woready_1_624 = _out_wofireMux_T_1208; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1209 = ~_out_T_1761; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1211 = _out_wofireMux_T_262 & out_backSel_237; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1212 = _out_wofireMux_T_1211 & _out_T_1731; // @[RegisterRouter.scala:87:24] assign out_woready_1_503 = _out_wofireMux_T_1212; // @[RegisterRouter.scala:87:24] assign out_woready_1_504 = _out_wofireMux_T_1212; // @[RegisterRouter.scala:87:24] assign out_woready_1_505 = _out_wofireMux_T_1212; // @[RegisterRouter.scala:87:24] assign out_woready_1_506 = _out_wofireMux_T_1212; // @[RegisterRouter.scala:87:24] assign out_woready_1_507 = _out_wofireMux_T_1212; // @[RegisterRouter.scala:87:24] assign out_woready_1_508 = _out_wofireMux_T_1212; // @[RegisterRouter.scala:87:24] assign out_woready_1_509 = _out_wofireMux_T_1212; // @[RegisterRouter.scala:87:24] assign out_woready_1_510 = _out_wofireMux_T_1212; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1213 = ~_out_T_1731; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1215 = _out_wofireMux_T_262 & out_backSel_238; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1216 = _out_wofireMux_T_1215 & _out_T_1651; // @[RegisterRouter.scala:87:24] assign out_woready_1_200 = _out_wofireMux_T_1216; // @[RegisterRouter.scala:87:24] assign out_woready_1_201 = _out_wofireMux_T_1216; // @[RegisterRouter.scala:87:24] assign out_woready_1_202 = _out_wofireMux_T_1216; // @[RegisterRouter.scala:87:24] assign out_woready_1_203 = _out_wofireMux_T_1216; // @[RegisterRouter.scala:87:24] assign out_woready_1_204 = _out_wofireMux_T_1216; // @[RegisterRouter.scala:87:24] assign out_woready_1_205 = _out_wofireMux_T_1216; // @[RegisterRouter.scala:87:24] assign out_woready_1_206 = _out_wofireMux_T_1216; // @[RegisterRouter.scala:87:24] assign out_woready_1_207 = _out_wofireMux_T_1216; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1217 = ~_out_T_1651; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1219 = _out_wofireMux_T_262 & out_backSel_239; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1220 = _out_wofireMux_T_1219 & _out_T_1887; // @[RegisterRouter.scala:87:24] assign out_woready_1_1115 = _out_wofireMux_T_1220; // @[RegisterRouter.scala:87:24] assign out_woready_1_1116 = _out_wofireMux_T_1220; // @[RegisterRouter.scala:87:24] assign out_woready_1_1117 = _out_wofireMux_T_1220; // @[RegisterRouter.scala:87:24] assign out_woready_1_1118 = _out_wofireMux_T_1220; // @[RegisterRouter.scala:87:24] assign out_woready_1_1119 = _out_wofireMux_T_1220; // @[RegisterRouter.scala:87:24] assign out_woready_1_1120 = _out_wofireMux_T_1220; // @[RegisterRouter.scala:87:24] assign out_woready_1_1121 = _out_wofireMux_T_1220; // @[RegisterRouter.scala:87:24] assign out_woready_1_1122 = _out_wofireMux_T_1220; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1221 = ~_out_T_1887; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1223 = _out_wofireMux_T_262 & out_backSel_240; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1224 = _out_wofireMux_T_1223 & _out_T_1793; // @[RegisterRouter.scala:87:24] assign out_woready_1_739 = _out_wofireMux_T_1224; // @[RegisterRouter.scala:87:24] assign out_woready_1_740 = _out_wofireMux_T_1224; // @[RegisterRouter.scala:87:24] assign out_woready_1_741 = _out_wofireMux_T_1224; // @[RegisterRouter.scala:87:24] assign out_woready_1_742 = _out_wofireMux_T_1224; // @[RegisterRouter.scala:87:24] assign out_woready_1_743 = _out_wofireMux_T_1224; // @[RegisterRouter.scala:87:24] assign out_woready_1_744 = _out_wofireMux_T_1224; // @[RegisterRouter.scala:87:24] assign out_woready_1_745 = _out_wofireMux_T_1224; // @[RegisterRouter.scala:87:24] assign out_woready_1_746 = _out_wofireMux_T_1224; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1225 = ~_out_T_1793; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1227 = _out_wofireMux_T_262 & out_backSel_241; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1228 = _out_wofireMux_T_1227 & _out_T_1805; // @[RegisterRouter.scala:87:24] assign out_woready_1_787 = _out_wofireMux_T_1228; // @[RegisterRouter.scala:87:24] assign out_woready_1_788 = _out_wofireMux_T_1228; // @[RegisterRouter.scala:87:24] assign out_woready_1_789 = _out_wofireMux_T_1228; // @[RegisterRouter.scala:87:24] assign out_woready_1_790 = _out_wofireMux_T_1228; // @[RegisterRouter.scala:87:24] assign out_woready_1_791 = _out_wofireMux_T_1228; // @[RegisterRouter.scala:87:24] assign out_woready_1_792 = _out_wofireMux_T_1228; // @[RegisterRouter.scala:87:24] assign out_woready_1_793 = _out_wofireMux_T_1228; // @[RegisterRouter.scala:87:24] assign out_woready_1_794 = _out_wofireMux_T_1228; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1229 = ~_out_T_1805; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1231 = _out_wofireMux_T_262 & out_backSel_242; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1232 = _out_wofireMux_T_1231 & _out_T_1889; // @[RegisterRouter.scala:87:24] assign out_woready_1_1123 = _out_wofireMux_T_1232; // @[RegisterRouter.scala:87:24] assign out_woready_1_1124 = _out_wofireMux_T_1232; // @[RegisterRouter.scala:87:24] assign out_woready_1_1125 = _out_wofireMux_T_1232; // @[RegisterRouter.scala:87:24] assign out_woready_1_1126 = _out_wofireMux_T_1232; // @[RegisterRouter.scala:87:24] assign out_woready_1_1127 = _out_wofireMux_T_1232; // @[RegisterRouter.scala:87:24] assign out_woready_1_1128 = _out_wofireMux_T_1232; // @[RegisterRouter.scala:87:24] assign out_woready_1_1129 = _out_wofireMux_T_1232; // @[RegisterRouter.scala:87:24] assign out_woready_1_1130 = _out_wofireMux_T_1232; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1233 = ~_out_T_1889; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1235 = _out_wofireMux_T_262 & out_backSel_243; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1236 = _out_wofireMux_T_1235 & _out_T_1665; // @[RegisterRouter.scala:87:24] assign out_woready_1_256 = _out_wofireMux_T_1236; // @[RegisterRouter.scala:87:24] assign out_woready_1_257 = _out_wofireMux_T_1236; // @[RegisterRouter.scala:87:24] assign out_woready_1_258 = _out_wofireMux_T_1236; // @[RegisterRouter.scala:87:24] assign out_woready_1_259 = _out_wofireMux_T_1236; // @[RegisterRouter.scala:87:24] assign out_woready_1_260 = _out_wofireMux_T_1236; // @[RegisterRouter.scala:87:24] assign out_woready_1_261 = _out_wofireMux_T_1236; // @[RegisterRouter.scala:87:24] assign out_woready_1_262 = _out_wofireMux_T_1236; // @[RegisterRouter.scala:87:24] assign out_woready_1_263 = _out_wofireMux_T_1236; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1237 = ~_out_T_1665; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1239 = _out_wofireMux_T_262 & out_backSel_244; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1240 = _out_wofireMux_T_1239 & _out_T_1735; // @[RegisterRouter.scala:87:24] assign out_woready_1_519 = _out_wofireMux_T_1240; // @[RegisterRouter.scala:87:24] assign out_woready_1_520 = _out_wofireMux_T_1240; // @[RegisterRouter.scala:87:24] assign out_woready_1_521 = _out_wofireMux_T_1240; // @[RegisterRouter.scala:87:24] assign out_woready_1_522 = _out_wofireMux_T_1240; // @[RegisterRouter.scala:87:24] assign out_woready_1_523 = _out_wofireMux_T_1240; // @[RegisterRouter.scala:87:24] assign out_woready_1_524 = _out_wofireMux_T_1240; // @[RegisterRouter.scala:87:24] assign out_woready_1_525 = _out_wofireMux_T_1240; // @[RegisterRouter.scala:87:24] assign out_woready_1_526 = _out_wofireMux_T_1240; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1241 = ~_out_T_1735; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1243 = _out_wofireMux_T_262 & out_backSel_245; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1244 = _out_wofireMux_T_1243 & _out_T_1777; // @[RegisterRouter.scala:87:24] assign out_woready_1_681 = _out_wofireMux_T_1244; // @[RegisterRouter.scala:87:24] assign out_woready_1_682 = _out_wofireMux_T_1244; // @[RegisterRouter.scala:87:24] assign out_woready_1_683 = _out_wofireMux_T_1244; // @[RegisterRouter.scala:87:24] assign out_woready_1_684 = _out_wofireMux_T_1244; // @[RegisterRouter.scala:87:24] assign out_woready_1_685 = _out_wofireMux_T_1244; // @[RegisterRouter.scala:87:24] assign out_woready_1_686 = _out_wofireMux_T_1244; // @[RegisterRouter.scala:87:24] assign out_woready_1_687 = _out_wofireMux_T_1244; // @[RegisterRouter.scala:87:24] assign out_woready_1_688 = _out_wofireMux_T_1244; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1245 = ~_out_T_1777; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1247 = _out_wofireMux_T_262 & out_backSel_246; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1248 = _out_wofireMux_T_1247 & _out_T_1865; // @[RegisterRouter.scala:87:24] assign out_woready_1_1027 = _out_wofireMux_T_1248; // @[RegisterRouter.scala:87:24] assign out_woready_1_1028 = _out_wofireMux_T_1248; // @[RegisterRouter.scala:87:24] assign out_woready_1_1029 = _out_wofireMux_T_1248; // @[RegisterRouter.scala:87:24] assign out_woready_1_1030 = _out_wofireMux_T_1248; // @[RegisterRouter.scala:87:24] assign out_woready_1_1031 = _out_wofireMux_T_1248; // @[RegisterRouter.scala:87:24] assign out_woready_1_1032 = _out_wofireMux_T_1248; // @[RegisterRouter.scala:87:24] assign out_woready_1_1033 = _out_wofireMux_T_1248; // @[RegisterRouter.scala:87:24] assign out_woready_1_1034 = _out_wofireMux_T_1248; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1249 = ~_out_T_1865; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1251 = _out_wofireMux_T_262 & out_backSel_247; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1252 = _out_wofireMux_T_1251 & _out_T_1613; // @[RegisterRouter.scala:87:24] assign out_woready_1_48 = _out_wofireMux_T_1252; // @[RegisterRouter.scala:87:24] assign out_woready_1_49 = _out_wofireMux_T_1252; // @[RegisterRouter.scala:87:24] assign out_woready_1_50 = _out_wofireMux_T_1252; // @[RegisterRouter.scala:87:24] assign out_woready_1_51 = _out_wofireMux_T_1252; // @[RegisterRouter.scala:87:24] assign out_woready_1_52 = _out_wofireMux_T_1252; // @[RegisterRouter.scala:87:24] assign out_woready_1_53 = _out_wofireMux_T_1252; // @[RegisterRouter.scala:87:24] assign out_woready_1_54 = _out_wofireMux_T_1252; // @[RegisterRouter.scala:87:24] assign out_woready_1_55 = _out_wofireMux_T_1252; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1253 = ~_out_T_1613; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1255 = _out_wofireMux_T_262 & out_backSel_248; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1256 = _out_wofireMux_T_1255 & _out_T_1673; // @[RegisterRouter.scala:87:24] assign out_woready_1_288 = _out_wofireMux_T_1256; // @[RegisterRouter.scala:87:24] assign out_woready_1_289 = _out_wofireMux_T_1256; // @[RegisterRouter.scala:87:24] assign out_woready_1_290 = _out_wofireMux_T_1256; // @[RegisterRouter.scala:87:24] assign out_woready_1_291 = _out_wofireMux_T_1256; // @[RegisterRouter.scala:87:24] assign out_woready_1_292 = _out_wofireMux_T_1256; // @[RegisterRouter.scala:87:24] assign out_woready_1_293 = _out_wofireMux_T_1256; // @[RegisterRouter.scala:87:24] assign out_woready_1_294 = _out_wofireMux_T_1256; // @[RegisterRouter.scala:87:24] assign out_woready_1_295 = _out_wofireMux_T_1256; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1257 = ~_out_T_1673; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1259 = _out_wofireMux_T_262 & out_backSel_249; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1260 = _out_wofireMux_T_1259 & _out_T_1603; // @[RegisterRouter.scala:87:24] assign out_woready_1_8 = _out_wofireMux_T_1260; // @[RegisterRouter.scala:87:24] assign out_woready_1_9 = _out_wofireMux_T_1260; // @[RegisterRouter.scala:87:24] assign out_woready_1_10 = _out_wofireMux_T_1260; // @[RegisterRouter.scala:87:24] assign out_woready_1_11 = _out_wofireMux_T_1260; // @[RegisterRouter.scala:87:24] assign out_woready_1_12 = _out_wofireMux_T_1260; // @[RegisterRouter.scala:87:24] assign out_woready_1_13 = _out_wofireMux_T_1260; // @[RegisterRouter.scala:87:24] assign out_woready_1_14 = _out_wofireMux_T_1260; // @[RegisterRouter.scala:87:24] assign out_woready_1_15 = _out_wofireMux_T_1260; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1261 = ~_out_T_1603; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1263 = _out_wofireMux_T_262 & out_backSel_250; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1264 = _out_wofireMux_T_1263 & _out_T_1843; // @[RegisterRouter.scala:87:24] assign out_woready_1_939 = _out_wofireMux_T_1264; // @[RegisterRouter.scala:87:24] assign out_woready_1_940 = _out_wofireMux_T_1264; // @[RegisterRouter.scala:87:24] assign out_woready_1_941 = _out_wofireMux_T_1264; // @[RegisterRouter.scala:87:24] assign out_woready_1_942 = _out_wofireMux_T_1264; // @[RegisterRouter.scala:87:24] assign out_woready_1_943 = _out_wofireMux_T_1264; // @[RegisterRouter.scala:87:24] assign out_woready_1_944 = _out_wofireMux_T_1264; // @[RegisterRouter.scala:87:24] assign out_woready_1_945 = _out_wofireMux_T_1264; // @[RegisterRouter.scala:87:24] assign out_woready_1_946 = _out_wofireMux_T_1264; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1265 = ~_out_T_1843; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1267 = _out_wofireMux_T_262 & out_backSel_251; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1268 = _out_wofireMux_T_1267 & _out_T_1795; // @[RegisterRouter.scala:87:24] assign out_woready_1_747 = _out_wofireMux_T_1268; // @[RegisterRouter.scala:87:24] assign out_woready_1_748 = _out_wofireMux_T_1268; // @[RegisterRouter.scala:87:24] assign out_woready_1_749 = _out_wofireMux_T_1268; // @[RegisterRouter.scala:87:24] assign out_woready_1_750 = _out_wofireMux_T_1268; // @[RegisterRouter.scala:87:24] assign out_woready_1_751 = _out_wofireMux_T_1268; // @[RegisterRouter.scala:87:24] assign out_woready_1_752 = _out_wofireMux_T_1268; // @[RegisterRouter.scala:87:24] assign out_woready_1_753 = _out_wofireMux_T_1268; // @[RegisterRouter.scala:87:24] assign out_woready_1_754 = _out_wofireMux_T_1268; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1269 = ~_out_T_1795; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1271 = _out_wofireMux_T_262 & out_backSel_252; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1272 = _out_wofireMux_T_1271 & _out_T_1693; // @[RegisterRouter.scala:87:24] assign out_woready_1_362 = _out_wofireMux_T_1272; // @[RegisterRouter.scala:87:24] assign out_woready_1_363 = _out_wofireMux_T_1272; // @[RegisterRouter.scala:87:24] assign out_woready_1_364 = _out_wofireMux_T_1272; // @[RegisterRouter.scala:87:24] assign out_woready_1_365 = _out_wofireMux_T_1272; // @[RegisterRouter.scala:87:24] assign out_woready_1_366 = _out_wofireMux_T_1272; // @[RegisterRouter.scala:87:24] assign out_woready_1_367 = _out_wofireMux_T_1272; // @[RegisterRouter.scala:87:24] assign out_woready_1_368 = _out_wofireMux_T_1272; // @[RegisterRouter.scala:87:24] assign out_woready_1_369 = _out_wofireMux_T_1272; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1273 = ~_out_T_1693; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1275 = _out_wofireMux_T_262 & out_backSel_253; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1276 = _out_wofireMux_T_1275 & _out_T_1655; // @[RegisterRouter.scala:87:24] assign out_woready_1_216 = _out_wofireMux_T_1276; // @[RegisterRouter.scala:87:24] assign out_woready_1_217 = _out_wofireMux_T_1276; // @[RegisterRouter.scala:87:24] assign out_woready_1_218 = _out_wofireMux_T_1276; // @[RegisterRouter.scala:87:24] assign out_woready_1_219 = _out_wofireMux_T_1276; // @[RegisterRouter.scala:87:24] assign out_woready_1_220 = _out_wofireMux_T_1276; // @[RegisterRouter.scala:87:24] assign out_woready_1_221 = _out_wofireMux_T_1276; // @[RegisterRouter.scala:87:24] assign out_woready_1_222 = _out_wofireMux_T_1276; // @[RegisterRouter.scala:87:24] assign out_woready_1_223 = _out_wofireMux_T_1276; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1277 = ~_out_T_1655; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1279 = _out_wofireMux_T_262 & out_backSel_254; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1280 = _out_wofireMux_T_1279 & _out_T_1907; // @[RegisterRouter.scala:87:24] assign out_woready_1_1195 = _out_wofireMux_T_1280; // @[RegisterRouter.scala:87:24] assign out_woready_1_1196 = _out_wofireMux_T_1280; // @[RegisterRouter.scala:87:24] assign out_woready_1_1197 = _out_wofireMux_T_1280; // @[RegisterRouter.scala:87:24] assign out_woready_1_1198 = _out_wofireMux_T_1280; // @[RegisterRouter.scala:87:24] assign out_woready_1_1199 = _out_wofireMux_T_1280; // @[RegisterRouter.scala:87:24] assign out_woready_1_1200 = _out_wofireMux_T_1280; // @[RegisterRouter.scala:87:24] assign out_woready_1_1201 = _out_wofireMux_T_1280; // @[RegisterRouter.scala:87:24] assign out_woready_1_1202 = _out_wofireMux_T_1280; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1281 = ~_out_T_1907; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1283 = _out_wofireMux_T_262 & out_backSel_255; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1284 = _out_wofireMux_T_1283 & _out_T_1811; // @[RegisterRouter.scala:87:24] assign out_woready_1_811 = _out_wofireMux_T_1284; // @[RegisterRouter.scala:87:24] assign out_woready_1_812 = _out_wofireMux_T_1284; // @[RegisterRouter.scala:87:24] assign out_woready_1_813 = _out_wofireMux_T_1284; // @[RegisterRouter.scala:87:24] assign out_woready_1_814 = _out_wofireMux_T_1284; // @[RegisterRouter.scala:87:24] assign out_woready_1_815 = _out_wofireMux_T_1284; // @[RegisterRouter.scala:87:24] assign out_woready_1_816 = _out_wofireMux_T_1284; // @[RegisterRouter.scala:87:24] assign out_woready_1_817 = _out_wofireMux_T_1284; // @[RegisterRouter.scala:87:24] assign out_woready_1_818 = _out_wofireMux_T_1284; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1285 = ~_out_T_1811; // @[RegisterRouter.scala:87:24] assign in_1_ready = _out_in_ready_T_1; // @[RegisterRouter.scala:73:18, :87:24] assign out_front_1_valid = _out_front_valid_T_1; // @[RegisterRouter.scala:87:24] assign out_front_1_ready = _out_front_ready_T_1; // @[RegisterRouter.scala:87:24] assign out_1_valid = _out_out_valid_T_1; // @[RegisterRouter.scala:87:24] wire [255:0] _GEN_24 = {{_out_out_bits_data_WIRE_2_255}, {_out_out_bits_data_WIRE_2_254}, {_out_out_bits_data_WIRE_2_253}, {_out_out_bits_data_WIRE_2_252}, {_out_out_bits_data_WIRE_2_251}, {_out_out_bits_data_WIRE_2_250}, {_out_out_bits_data_WIRE_2_249}, {_out_out_bits_data_WIRE_2_248}, {_out_out_bits_data_WIRE_2_247}, {_out_out_bits_data_WIRE_2_246}, {_out_out_bits_data_WIRE_2_245}, {_out_out_bits_data_WIRE_2_244}, {_out_out_bits_data_WIRE_2_243}, {_out_out_bits_data_WIRE_2_242}, {_out_out_bits_data_WIRE_2_241}, {_out_out_bits_data_WIRE_2_240}, {_out_out_bits_data_WIRE_2_239}, {_out_out_bits_data_WIRE_2_238}, {_out_out_bits_data_WIRE_2_237}, {_out_out_bits_data_WIRE_2_236}, {_out_out_bits_data_WIRE_2_235}, {_out_out_bits_data_WIRE_2_234}, {_out_out_bits_data_WIRE_2_233}, {_out_out_bits_data_WIRE_2_232}, {_out_out_bits_data_WIRE_2_231}, {_out_out_bits_data_WIRE_2_230}, {_out_out_bits_data_WIRE_2_229}, {_out_out_bits_data_WIRE_2_228}, {_out_out_bits_data_WIRE_2_227}, {_out_out_bits_data_WIRE_2_226}, {_out_out_bits_data_WIRE_2_225}, {_out_out_bits_data_WIRE_2_224}, {_out_out_bits_data_WIRE_2_223}, {_out_out_bits_data_WIRE_2_222}, {_out_out_bits_data_WIRE_2_221}, {_out_out_bits_data_WIRE_2_220}, {_out_out_bits_data_WIRE_2_219}, {_out_out_bits_data_WIRE_2_218}, {_out_out_bits_data_WIRE_2_217}, {_out_out_bits_data_WIRE_2_216}, {_out_out_bits_data_WIRE_2_215}, {_out_out_bits_data_WIRE_2_214}, {_out_out_bits_data_WIRE_2_213}, {_out_out_bits_data_WIRE_2_212}, {_out_out_bits_data_WIRE_2_211}, {_out_out_bits_data_WIRE_2_210}, {_out_out_bits_data_WIRE_2_209}, {_out_out_bits_data_WIRE_2_208}, {_out_out_bits_data_WIRE_2_207}, {_out_out_bits_data_WIRE_2_206}, {_out_out_bits_data_WIRE_2_205}, {_out_out_bits_data_WIRE_2_204}, {_out_out_bits_data_WIRE_2_203}, {_out_out_bits_data_WIRE_2_202}, {_out_out_bits_data_WIRE_2_201}, {_out_out_bits_data_WIRE_2_200}, {_out_out_bits_data_WIRE_2_199}, {_out_out_bits_data_WIRE_2_198}, {_out_out_bits_data_WIRE_2_197}, {_out_out_bits_data_WIRE_2_196}, {_out_out_bits_data_WIRE_2_195}, {_out_out_bits_data_WIRE_2_194}, {_out_out_bits_data_WIRE_2_193}, {_out_out_bits_data_WIRE_2_192}, {_out_out_bits_data_WIRE_2_191}, {_out_out_bits_data_WIRE_2_190}, {_out_out_bits_data_WIRE_2_189}, {_out_out_bits_data_WIRE_2_188}, {_out_out_bits_data_WIRE_2_187}, {_out_out_bits_data_WIRE_2_186}, {_out_out_bits_data_WIRE_2_185}, {_out_out_bits_data_WIRE_2_184}, {_out_out_bits_data_WIRE_2_183}, {_out_out_bits_data_WIRE_2_182}, {_out_out_bits_data_WIRE_2_181}, {_out_out_bits_data_WIRE_2_180}, {_out_out_bits_data_WIRE_2_179}, {_out_out_bits_data_WIRE_2_178}, {_out_out_bits_data_WIRE_2_177}, {_out_out_bits_data_WIRE_2_176}, {_out_out_bits_data_WIRE_2_175}, {_out_out_bits_data_WIRE_2_174}, {_out_out_bits_data_WIRE_2_173}, {_out_out_bits_data_WIRE_2_172}, {_out_out_bits_data_WIRE_2_171}, {_out_out_bits_data_WIRE_2_170}, {_out_out_bits_data_WIRE_2_169}, {_out_out_bits_data_WIRE_2_168}, {_out_out_bits_data_WIRE_2_167}, {_out_out_bits_data_WIRE_2_166}, {_out_out_bits_data_WIRE_2_165}, {_out_out_bits_data_WIRE_2_164}, {_out_out_bits_data_WIRE_2_163}, {_out_out_bits_data_WIRE_2_162}, {_out_out_bits_data_WIRE_2_161}, {_out_out_bits_data_WIRE_2_160}, {_out_out_bits_data_WIRE_2_159}, {_out_out_bits_data_WIRE_2_158}, {_out_out_bits_data_WIRE_2_157}, {_out_out_bits_data_WIRE_2_156}, {_out_out_bits_data_WIRE_2_155}, {_out_out_bits_data_WIRE_2_154}, {_out_out_bits_data_WIRE_2_153}, {_out_out_bits_data_WIRE_2_152}, {_out_out_bits_data_WIRE_2_151}, {_out_out_bits_data_WIRE_2_150}, {_out_out_bits_data_WIRE_2_149}, {_out_out_bits_data_WIRE_2_148}, {_out_out_bits_data_WIRE_2_147}, {_out_out_bits_data_WIRE_2_146}, {_out_out_bits_data_WIRE_2_145}, {_out_out_bits_data_WIRE_2_144}, {_out_out_bits_data_WIRE_2_143}, {_out_out_bits_data_WIRE_2_142}, {_out_out_bits_data_WIRE_2_141}, {_out_out_bits_data_WIRE_2_140}, {_out_out_bits_data_WIRE_2_139}, {_out_out_bits_data_WIRE_2_138}, {_out_out_bits_data_WIRE_2_137}, {_out_out_bits_data_WIRE_2_136}, {_out_out_bits_data_WIRE_2_135}, {_out_out_bits_data_WIRE_2_134}, {_out_out_bits_data_WIRE_2_133}, {_out_out_bits_data_WIRE_2_132}, {_out_out_bits_data_WIRE_2_131}, {_out_out_bits_data_WIRE_2_130}, {_out_out_bits_data_WIRE_2_129}, {_out_out_bits_data_WIRE_2_128}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {_out_out_bits_data_WIRE_2_115}, {_out_out_bits_data_WIRE_2_114}, {_out_out_bits_data_WIRE_2_113}, {_out_out_bits_data_WIRE_2_112}, {_out_out_bits_data_WIRE_2_111}, {_out_out_bits_data_WIRE_2_110}, {_out_out_bits_data_WIRE_2_109}, {_out_out_bits_data_WIRE_2_108}, {_out_out_bits_data_WIRE_2_107}, {_out_out_bits_data_WIRE_2_106}, {_out_out_bits_data_WIRE_2_105}, {_out_out_bits_data_WIRE_2_104}, {_out_out_bits_data_WIRE_2_103}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {_out_out_bits_data_WIRE_2_96}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {_out_out_bits_data_WIRE_2_33}, {_out_out_bits_data_WIRE_2_32}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {_out_out_bits_data_WIRE_2_10}, {_out_out_bits_data_WIRE_2_9}, {_out_out_bits_data_WIRE_2_8}, {_out_out_bits_data_WIRE_2_7}, {_out_out_bits_data_WIRE_2_6}, {_out_out_bits_data_WIRE_2_5}, {_out_out_bits_data_WIRE_2_4}, {_out_out_bits_data_WIRE_2_3}, {_out_out_bits_data_WIRE_2_2}, {_out_out_bits_data_WIRE_2_1}, {_out_out_bits_data_WIRE_2_0}}; // @[MuxLiteral.scala:49:{10,48}] wire _out_out_bits_data_T_6 = _GEN_24[out_oindex_1]; // @[MuxLiteral.scala:49:10] wire [255:0][63:0] _GEN_25 = {{_out_out_bits_data_WIRE_3_255}, {_out_out_bits_data_WIRE_3_254}, {_out_out_bits_data_WIRE_3_253}, {_out_out_bits_data_WIRE_3_252}, {_out_out_bits_data_WIRE_3_251}, {_out_out_bits_data_WIRE_3_250}, {_out_out_bits_data_WIRE_3_249}, {_out_out_bits_data_WIRE_3_248}, {_out_out_bits_data_WIRE_3_247}, {_out_out_bits_data_WIRE_3_246}, {_out_out_bits_data_WIRE_3_245}, {_out_out_bits_data_WIRE_3_244}, {_out_out_bits_data_WIRE_3_243}, {_out_out_bits_data_WIRE_3_242}, {_out_out_bits_data_WIRE_3_241}, {_out_out_bits_data_WIRE_3_240}, {_out_out_bits_data_WIRE_3_239}, {_out_out_bits_data_WIRE_3_238}, {_out_out_bits_data_WIRE_3_237}, {_out_out_bits_data_WIRE_3_236}, {_out_out_bits_data_WIRE_3_235}, {_out_out_bits_data_WIRE_3_234}, {_out_out_bits_data_WIRE_3_233}, {_out_out_bits_data_WIRE_3_232}, {_out_out_bits_data_WIRE_3_231}, {_out_out_bits_data_WIRE_3_230}, {_out_out_bits_data_WIRE_3_229}, {_out_out_bits_data_WIRE_3_228}, {_out_out_bits_data_WIRE_3_227}, {_out_out_bits_data_WIRE_3_226}, {_out_out_bits_data_WIRE_3_225}, {_out_out_bits_data_WIRE_3_224}, {_out_out_bits_data_WIRE_3_223}, {_out_out_bits_data_WIRE_3_222}, {_out_out_bits_data_WIRE_3_221}, {_out_out_bits_data_WIRE_3_220}, {_out_out_bits_data_WIRE_3_219}, {_out_out_bits_data_WIRE_3_218}, {_out_out_bits_data_WIRE_3_217}, {_out_out_bits_data_WIRE_3_216}, {_out_out_bits_data_WIRE_3_215}, {_out_out_bits_data_WIRE_3_214}, {_out_out_bits_data_WIRE_3_213}, {_out_out_bits_data_WIRE_3_212}, {_out_out_bits_data_WIRE_3_211}, {_out_out_bits_data_WIRE_3_210}, {_out_out_bits_data_WIRE_3_209}, {_out_out_bits_data_WIRE_3_208}, {_out_out_bits_data_WIRE_3_207}, {_out_out_bits_data_WIRE_3_206}, {_out_out_bits_data_WIRE_3_205}, {_out_out_bits_data_WIRE_3_204}, {_out_out_bits_data_WIRE_3_203}, {_out_out_bits_data_WIRE_3_202}, {_out_out_bits_data_WIRE_3_201}, {_out_out_bits_data_WIRE_3_200}, {_out_out_bits_data_WIRE_3_199}, {_out_out_bits_data_WIRE_3_198}, {_out_out_bits_data_WIRE_3_197}, {_out_out_bits_data_WIRE_3_196}, {_out_out_bits_data_WIRE_3_195}, {_out_out_bits_data_WIRE_3_194}, {_out_out_bits_data_WIRE_3_193}, {_out_out_bits_data_WIRE_3_192}, {_out_out_bits_data_WIRE_3_191}, {_out_out_bits_data_WIRE_3_190}, {_out_out_bits_data_WIRE_3_189}, {_out_out_bits_data_WIRE_3_188}, {_out_out_bits_data_WIRE_3_187}, {_out_out_bits_data_WIRE_3_186}, {_out_out_bits_data_WIRE_3_185}, {_out_out_bits_data_WIRE_3_184}, {_out_out_bits_data_WIRE_3_183}, {_out_out_bits_data_WIRE_3_182}, {_out_out_bits_data_WIRE_3_181}, {_out_out_bits_data_WIRE_3_180}, {_out_out_bits_data_WIRE_3_179}, {_out_out_bits_data_WIRE_3_178}, {_out_out_bits_data_WIRE_3_177}, {_out_out_bits_data_WIRE_3_176}, {_out_out_bits_data_WIRE_3_175}, {_out_out_bits_data_WIRE_3_174}, {_out_out_bits_data_WIRE_3_173}, {_out_out_bits_data_WIRE_3_172}, {_out_out_bits_data_WIRE_3_171}, {_out_out_bits_data_WIRE_3_170}, {_out_out_bits_data_WIRE_3_169}, {_out_out_bits_data_WIRE_3_168}, {_out_out_bits_data_WIRE_3_167}, {_out_out_bits_data_WIRE_3_166}, {_out_out_bits_data_WIRE_3_165}, {_out_out_bits_data_WIRE_3_164}, {_out_out_bits_data_WIRE_3_163}, {_out_out_bits_data_WIRE_3_162}, {_out_out_bits_data_WIRE_3_161}, {_out_out_bits_data_WIRE_3_160}, {_out_out_bits_data_WIRE_3_159}, {_out_out_bits_data_WIRE_3_158}, {_out_out_bits_data_WIRE_3_157}, {_out_out_bits_data_WIRE_3_156}, {_out_out_bits_data_WIRE_3_155}, {_out_out_bits_data_WIRE_3_154}, {_out_out_bits_data_WIRE_3_153}, {_out_out_bits_data_WIRE_3_152}, {_out_out_bits_data_WIRE_3_151}, {_out_out_bits_data_WIRE_3_150}, {_out_out_bits_data_WIRE_3_149}, {_out_out_bits_data_WIRE_3_148}, {_out_out_bits_data_WIRE_3_147}, {_out_out_bits_data_WIRE_3_146}, {_out_out_bits_data_WIRE_3_145}, {_out_out_bits_data_WIRE_3_144}, {_out_out_bits_data_WIRE_3_143}, {_out_out_bits_data_WIRE_3_142}, {_out_out_bits_data_WIRE_3_141}, {_out_out_bits_data_WIRE_3_140}, {_out_out_bits_data_WIRE_3_139}, {_out_out_bits_data_WIRE_3_138}, {_out_out_bits_data_WIRE_3_137}, {_out_out_bits_data_WIRE_3_136}, {_out_out_bits_data_WIRE_3_135}, {_out_out_bits_data_WIRE_3_134}, {_out_out_bits_data_WIRE_3_133}, {_out_out_bits_data_WIRE_3_132}, {_out_out_bits_data_WIRE_3_131}, {_out_out_bits_data_WIRE_3_130}, {_out_out_bits_data_WIRE_3_129}, {_out_out_bits_data_WIRE_3_128}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {_out_out_bits_data_WIRE_3_115}, {_out_out_bits_data_WIRE_3_114}, {_out_out_bits_data_WIRE_3_113}, {_out_out_bits_data_WIRE_3_112}, {_out_out_bits_data_WIRE_3_111}, {_out_out_bits_data_WIRE_3_110}, {_out_out_bits_data_WIRE_3_109}, {_out_out_bits_data_WIRE_3_108}, {_out_out_bits_data_WIRE_3_107}, {_out_out_bits_data_WIRE_3_106}, {_out_out_bits_data_WIRE_3_105}, {_out_out_bits_data_WIRE_3_104}, {_out_out_bits_data_WIRE_3_103}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h380006F}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h100073}, {64'h100026237B200073}, {64'h7B20247310802423}, {64'hF140247330000067}, {64'h100022237B202473}, {64'h4086300147413}, {64'hFE0408E300347413}, {64'h4004440310802023}, {64'hF14024737B241073}, {64'hFF0000F0440006F}, {64'h380006F00C0006F}}; // @[MuxLiteral.scala:49:{10,48}] wire [63:0] _out_out_bits_data_T_8 = _GEN_25[out_oindex_1]; // @[MuxLiteral.scala:49:10] assign _out_out_bits_data_T_9 = _out_out_bits_data_T_6 ? _out_out_bits_data_T_8 : 64'h0; // @[MuxLiteral.scala:49:10] assign out_1_bits_data = _out_out_bits_data_T_9; // @[RegisterRouter.scala:87:24] assign tlNodeIn_d_bits_size = tlNodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign tlNodeIn_d_bits_source = tlNodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign tlNodeIn_d_bits_opcode = {2'h0, _tlNodeIn_d_bits_opcode_T}; // @[RegisterRouter.scala:105:{19,25}] reg [1:0] ctrlStateReg; // @[Debug.scala:1732:27] wire hartHalted = _hartHalted_T; // @[Debug.scala:1734:37] wire [1:0] ctrlStateNxt; // @[Debug.scala:1735:32] assign _abstractCommandBusy_T = \|ctrlStateReg; // @[Debug.scala:1732:27, :1740:42] assign abstractCommandBusy = _abstractCommandBusy_T; // @[Debug.scala:1220:39, :1740:42] assign _ABSTRACTCSWrEnLegal_T = ~(\|ctrlStateReg); // @[Debug.scala:1732:27, :1740:42, :1742:44] assign ABSTRACTCSWrEnLegal = _ABSTRACTCSWrEnLegal_T; // @[Debug.scala:1190:39, :1742:44] assign _COMMANDWrEnLegal_T = ~(\|ctrlStateReg); // @[Debug.scala:1732:27, :1740:42, :1742:44, :1743:44] assign COMMANDWrEnLegal = _COMMANDWrEnLegal_T; // @[Debug.scala:1282:39, :1743:44] assign _ABSTRACTAUTOWrEnLegal_T = ~(\|ctrlStateReg); // @[Debug.scala:1732:27, :1740:42, :1742:44, :1744:44] assign ABSTRACTAUTOWrEnLegal = _ABSTRACTAUTOWrEnLegal_T; // @[Debug.scala:1243:41, :1744:44] assign _dmiAbstractDataAccessLegal_T = ~(\|ctrlStateReg); // @[Debug.scala:1732:27, :1740:42, :1742:44, :1745:50] assign dmiAbstractDataAccessLegal = _dmiAbstractDataAccessLegal_T; // @[Debug.scala:892:46, :1745:50] assign _dmiProgramBufferAccessLegal_T = ~(\|ctrlStateReg); // @[Debug.scala:1732:27, :1740:42, :1742:44, :1746:50] assign dmiProgramBufferAccessLegal = _dmiProgramBufferAccessLegal_T; // @[Debug.scala:888:47, :1746:50] wire _errorBusy_T = ~ABSTRACTCSWrEnLegal; // @[Debug.scala:1190:39, :1748:45] wire _errorBusy_T_1 = ABSTRACTCSWrEnMaybe & _errorBusy_T; // @[Debug.scala:1188:39, :1748:{42,45}] wire _errorBusy_T_2 = ~ABSTRACTAUTOWrEnLegal; // @[Debug.scala:1243:41, :1749:45] wire _errorBusy_T_3 = autoexecdataWrEnMaybe & _errorBusy_T_2; // @[Debug.scala:1240:41, :1749:{42,45}] wire _errorBusy_T_4 = _errorBusy_T_1 \| _errorBusy_T_3; // @[Debug.scala:1748:{42,74}, :1749:42] wire _errorBusy_T_5 = ~ABSTRACTAUTOWrEnLegal; // @[Debug.scala:1243:41, :1749:45, :1750:47] wire _errorBusy_T_6 = autoexecprogbufWrEnMaybe & _errorBusy_T_5; // @[Debug.scala:1241:44, :1750:{44,47}] wire _errorBusy_T_7 = _errorBusy_T_4 \| _errorBusy_T_6; // @[Debug.scala:1748:74, :1749:74, :1750:44] wire _errorBusy_T_8 = ~COMMANDWrEnLegal; // @[Debug.scala:1282:39, :1751:45] wire _errorBusy_T_9 = COMMANDWrEnMaybe & _errorBusy_T_8; // @[Debug.scala:1281:39, :1751:{42,45}] wire _errorBusy_T_10 = _errorBusy_T_7 \| _errorBusy_T_9; // @[Debug.scala:1749:74, :1750:74, :1751:42] wire _errorBusy_T_11 = ~dmiAbstractDataAccessLegal; // @[Debug.scala:892:46, :1752:45] wire _errorBusy_T_12 = dmiAbstractDataAccess & _errorBusy_T_11; // @[Debug.scala:1263:68, :1752:{42,45}] wire _errorBusy_T_13 = _errorBusy_T_10 \| _errorBusy_T_12; // @[Debug.scala:1750:74, :1751:74, :1752:42] wire _errorBusy_T_14 = ~dmiProgramBufferAccessLegal; // @[Debug.scala:888:47, :1753:45] wire _errorBusy_T_15 = dmiProgramBufferAccess & _errorBusy_T_14; // @[Debug.scala:1264:69, :1753:{42,45}] assign _errorBusy_T_16 = _errorBusy_T_13 \| _errorBusy_T_15; // @[Debug.scala:1751:74, :1752:74, :1753:42] assign errorBusy = _errorBusy_T_16; // @[Debug.scala:1195:36, :1752:74] wire commandWrIsAccessRegister = COMMANDWrData_cmdtype == 8'h0; // @[Debug.scala:1280:39, :1756:60] wire commandRegIsAccessRegister = COMMANDReg_cmdtype == 8'h0; // @[Debug.scala:1277:25, :1757:58] wire _commandWrIsUnsupported_T = ~commandWrIsAccessRegister; // @[Debug.scala:1756:60, :1759:49] wire commandWrIsUnsupported = COMMANDWrEn & _commandWrIsUnsupported_T; // @[Debug.scala:1285:40, :1759:{46,49}] wire commandRegIsUnsupported; // @[Debug.scala:1761:43] wire commandRegBadHaltResume; // @[Debug.scala:1762:43] wire _accessRegIsLegalSize_T = accessRegisterCommandReg_size == 3'h2; // @[Debug.scala:1533:44, :1765:63] wire _accessRegIsLegalSize_T_1 = accessRegisterCommandReg_size == 3'h3; // @[Debug.scala:1533:44, :1765:106] wire accessRegIsLegalSize = _accessRegIsLegalSize_T \| _accessRegIsLegalSize_T_1; // @[Debug.scala:1765:{63,72,106}] wire _accessRegIsGPR_T = \|(accessRegisterCommandReg_regno[15:12]); // @[Debug.scala:1533:44, :1766:58] wire _accessRegIsGPR_T_1 = accessRegisterCommandReg_regno < 16'h1020; // @[Debug.scala:1533:44, :1766:104] wire _accessRegIsGPR_T_2 = _accessRegIsGPR_T & _accessRegIsGPR_T_1; // @[Debug.scala:1766:{58,70,104}] wire accessRegIsGPR = _accessRegIsGPR_T_2 & accessRegIsLegalSize; // @[Debug.scala:1765:72, :1766:{70,117}] wire _T_1567 = ~accessRegisterCommandReg_transfer \| accessRegIsGPR; // @[Debug.scala:1533:44, :1766:117, :1776:{19,54}] assign commandRegIsUnsupported = ~commandRegIsAccessRegister \| ~_T_1567; // @[Debug.scala:1757:58, :1761:43, :1773:39, :1774:115, :1775:33, :1776:{54,73}, :1777:33] wire _commandRegBadHaltResume_T = ~hartHalted; // @[Debug.scala:1734:37, :1778:36] assign commandRegBadHaltResume = commandRegIsAccessRegister & _T_1567 & _commandRegBadHaltResume_T; // @[Debug.scala:1757:58, :1762:43, :1773:39, :1774:115, :1776:{54,73}, :1778:{33,36}] wire _wrAccessRegisterCommand_T = COMMANDWrEn & commandWrIsAccessRegister; // @[Debug.scala:1285:40, :1756:60, :1782:48] wire _GEN_26 = ABSTRACTCSReg_cmderr == 3'h0; // @[Debug.scala:1183:34, :1782:103] wire _wrAccessRegisterCommand_T_1; // @[Debug.scala:1782:103] assign _wrAccessRegisterCommand_T_1 = _GEN_26; // @[Debug.scala:1782:103] wire _regAccessRegisterCommand_T_1; // @[Debug.scala:1783:103] assign _regAccessRegisterCommand_T_1 = _GEN_26; // @[Debug.scala:1782:103, :1783:103] wire wrAccessRegisterCommand = _wrAccessRegisterCommand_T & _wrAccessRegisterCommand_T_1; // @[Debug.scala:1782:{48,78,103}] wire _regAccessRegisterCommand_T = autoexec & commandRegIsAccessRegister; // @[Debug.scala:1272:48, :1757:58, :1783:48] wire regAccessRegisterCommand = _regAccessRegisterCommand_T & _regAccessRegisterCommand_T_1; // @[Debug.scala:1783:{48,78,103}] wire _T_1569 = wrAccessRegisterCommand \| regAccessRegisterCommand; // @[Debug.scala:1782:78, :1783:78, :1790:37] wire _T_1571 = ctrlStateReg == 2'h1; // @[Debug.scala:1732:27, :1797:30] assign errorUnsupported = (\|ctrlStateReg) ? _T_1571 & commandRegIsUnsupported : ~_T_1569 & (commandWrIsUnsupported \| autoexec & commandRegIsUnsupported); // @[Debug.scala:1197:36, :1272:48, :1732:27, :1740:42, :1759:46, :1761:43, :1789:47, :1790:{37,66}, :1792:43, :1793:26, :1794:{28,56}, :1797:{30,59}, :1804:38] assign errorHaltResume = (\|ctrlStateReg) & _T_1571 & ~commandRegIsUnsupported & commandRegBadHaltResume; // @[Debug.scala:1198:36, :1732:27, :1740:42, :1761:43, :1762:43, :1789:47, :1797:{30,59}, :1804:38, :1807:43] wire _GEN_27 = commandRegIsUnsupported \| commandRegBadHaltResume; // @[Debug.scala:1761:43, :1762:43, :1804:38, :1806:22, :1807:43, :1809:22, :1811:33] assign goAbstract = (\|ctrlStateReg) & _T_1571 & ~_GEN_27; // @[Debug.scala:1495:32, :1732:27, :1740:42, :1789:47, :1797:{30,59}, :1804:38, :1806:22, :1807:43, :1809:22, :1811:33] wire _T_1572 = ctrlStateReg == 2'h2; // @[Debug.scala:1732:27, :1818:30] wire _GEN_28 = ~(\|ctrlStateReg) \| _T_1571; // @[Debug.scala:1196:36, :1732:27, :1740:42, :1742:44, :1789:47, :1797:{30,59}, :1818:51] assign errorException = ~_GEN_28 & _T_1572 & hartExceptionWrEn; // @[Debug.scala:881:36, :1196:36, :1789:47, :1797:59, :1818:{30,51}, :1826:31] assign goCustom = ~(_GEN_28 \| _T_1572) & (&ctrlStateReg); // @[Debug.scala:1196:36, :1496:32, :1732:27, :1789:47, :1797:59, :1818:{30,51}, :1831:{30,53}] assign ctrlStateNxt = (\|ctrlStateReg) ? (_T_1571 ? {~_GEN_27, 1'h0} : _T_1572 & (hartExceptionWrEn \| ~goReg & hartHaltedWrEn) ? 2'h0 : ctrlStateReg) : _T_1569 ? 2'h1 : ctrlStateReg; // @[Debug.scala:875:36, :881:36, :1494:27, :1732:27, :1735:32, :1740:42, :1789:47, :1790:{37,66}, :1791:22, :1797:{30,59}, :1804:38, :1806:22, :1807:43, :1809:22, :1811:33, :1818:{30,51}, :1823:{18,30,116}, :1824:22, :1826:31, :1828:24, :1831:53]
Generate the Verilog code corresponding to the following Chisel files. File primitives.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object lowMask { def apply(in: UInt, topBound: BigInt, bottomBound: BigInt): UInt = { require(topBound != bottomBound) val numInVals = BigInt(1)<<in.getWidth if (topBound < bottomBound) { lowMask(~in, numInVals - 1 - topBound, numInVals - 1 - bottomBound) } else if (numInVals > 64 /* Empirical /) { // For simulation performance, we should avoid generating // exteremely wide shifters, so we divide and conquer. // Empirically, this does not impact synthesis QoR. val mid = numInVals / 2 val msb = in(in.getWidth - 1) val lsbs = in(in.getWidth - 2, 0) if (mid < topBound) { if (mid <= bottomBound) { Mux(msb, lowMask(lsbs, topBound - mid, bottomBound - mid), 0.U ) } else { Mux(msb, lowMask(lsbs, topBound - mid, 0) ## ((BigInt(1)<<(mid - bottomBound).toInt) - 1).U, lowMask(lsbs, mid, bottomBound) ) } } else { ~Mux(msb, 0.U, ~lowMask(lsbs, topBound, bottomBound)) } } else { val shift = (BigInt(-1)<<numInVals.toInt).S>>in Reverse( shift( (numInVals - 1 - bottomBound).toInt, (numInVals - topBound).toInt ) ) } } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object countLeadingZeros { def apply(in: UInt): UInt = PriorityEncoder(in.asBools.reverse) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy2 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 1)>>1 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix 2 + 1, ix * 2).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 2).orR reducedVec.asUInt } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy4 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 3)>>2 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 4 + 3, ix * 4).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 4).orR reducedVec.asUInt } } File RoundAnyRawFNToRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util.Fill import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundAnyRawFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int, options: Int ) extends RawModule { override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(inExpWidth, inSigWidth)) // (allowed exponent range has limits) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0) val effectiveInSigWidth = if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1 val neverUnderflows = ((options & (flRoundOpt_neverUnderflows \| flRoundOpt_subnormsAlwaysExact) ) != 0) \|\| (inExpWidth < outExpWidth) val neverOverflows = ((options & flRoundOpt_neverOverflows) != 0) \|\| (inExpWidth < outExpWidth) val outNaNExp = BigInt(7)<<(outExpWidth - 2) val outInfExp = BigInt(6)<<(outExpWidth - 2) val outMaxFiniteExp = outInfExp - 1 val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2 val outMinNonzeroExp = outMinNormExp - outSigWidth + 1 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_near_even = (io.roundingMode === round_near_even) val roundingMode_minMag = (io.roundingMode === round_minMag) val roundingMode_min = (io.roundingMode === round_min) val roundingMode_max = (io.roundingMode === round_max) val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag) val roundingMode_odd = (io.roundingMode === round_odd) val roundMagUp = (roundingMode_min && io.in.sign) \|\| (roundingMode_max && ! io.in.sign) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sAdjustedExp = if (inExpWidth < outExpWidth) (io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S )(outExpWidth, 0).zext else if (inExpWidth == outExpWidth) io.in.sExp else io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S val adjustedSig = if (inSigWidth <= outSigWidth + 2) io.in.sig<<(outSigWidth - inSigWidth + 2) else (io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ## io.in.sig(inSigWidth - outSigWidth - 2, 0).orR ) val doShiftSigDown1 = if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2) val common_expOut = Wire(UInt((outExpWidth + 1).W)) val common_fractOut = Wire(UInt((outSigWidth - 1).W)) val common_overflow = Wire(Bool()) val common_totalUnderflow = Wire(Bool()) val common_underflow = Wire(Bool()) val common_inexact = Wire(Bool()) if ( neverOverflows && neverUnderflows && (effectiveInSigWidth <= outSigWidth) ) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1 common_fractOut := Mux(doShiftSigDown1, adjustedSig(outSigWidth + 1, 3), adjustedSig(outSigWidth, 2) ) common_overflow := false.B common_totalUnderflow := false.B common_underflow := false.B common_inexact := false.B } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundMask = if (neverUnderflows) 0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W) else (lowMask( sAdjustedExp(outExpWidth, 0), outMinNormExp - outSigWidth - 1, outMinNormExp ) \| doShiftSigDown1) ## 3.U(2.W) val shiftedRoundMask = 0.U(1.W) ## roundMask>>1 val roundPosMask = ~shiftedRoundMask & roundMask val roundPosBit = (adjustedSig & roundPosMask).orR val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR val anyRound = roundPosBit \|\| anyRoundExtra val roundIncr = ((roundingMode_near_even \|\| roundingMode_near_maxMag) && roundPosBit) \|\| (roundMagUp && anyRound) val roundedSig: Bits = Mux(roundIncr, (((adjustedSig \| roundMask)>>2) +& 1.U) & ~Mux(roundingMode_near_even && roundPosBit && ! anyRoundExtra, roundMask>>1, 0.U((outSigWidth + 2).W) ), (adjustedSig & ~roundMask)>>2 \| Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U) ) //* IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //* M.S. BIT OF SUBNORMAL SIG? val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext common_expOut := sRoundedExp(outExpWidth, 0) common_fractOut := Mux(doShiftSigDown1, roundedSig(outSigWidth - 1, 1), roundedSig(outSigWidth - 2, 0) ) common_overflow := (if (neverOverflows) false.B else //* REWRITE BASED ON BEFORE-ROUNDING EXPONENT?: (sRoundedExp>>(outExpWidth - 1) >= 3.S)) common_totalUnderflow := (if (neverUnderflows) false.B else //* WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?: (sRoundedExp < outMinNonzeroExp.S)) val unboundedRange_roundPosBit = Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1)) val unboundedRange_anyRound = (doShiftSigDown1 && adjustedSig(2)) \|\| adjustedSig(1, 0).orR val unboundedRange_roundIncr = ((roundingMode_near_even \|\| roundingMode_near_maxMag) && unboundedRange_roundPosBit) \|\| (roundMagUp && unboundedRange_anyRound) val roundCarry = Mux(doShiftSigDown1, roundedSig(outSigWidth + 1), roundedSig(outSigWidth) ) common_underflow := (if (neverUnderflows) false.B else common_totalUnderflow \|\| //* IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //* M.S. BIT OF SUBNORMAL SIG? (anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) && Mux(doShiftSigDown1, roundMask(3), roundMask(2)) && ! ((io.detectTininess === tininess_afterRounding) && ! Mux(doShiftSigDown1, roundMask(4), roundMask(3) ) && roundCarry && roundPosBit && unboundedRange_roundIncr))) common_inexact := common_totalUnderflow \|\| anyRound } //------------------------------------------------------------------------ //------------------------------------------------------------------------ val isNaNOut = io.invalidExc \|\| io.in.isNaN val notNaN_isSpecialInfOut = io.infiniteExc \|\| io.in.isInf val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero val overflow = commonCase && common_overflow val underflow = commonCase && common_underflow val inexact = overflow \|\| (commonCase && common_inexact) val overflow_roundMagUp = roundingMode_near_even \|\| roundingMode_near_maxMag \|\| roundMagUp val pegMinNonzeroMagOut = commonCase && common_totalUnderflow && (roundMagUp \|\| roundingMode_odd) val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp val notNaN_isInfOut = notNaN_isSpecialInfOut \|\| (overflow && overflow_roundMagUp) val signOut = Mux(isNaNOut, false.B, io.in.sign) val expOut = (common_expOut & ~Mux(io.in.isZero \|\| common_totalUnderflow, (BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMinNonzeroMagOut, ~outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMaxFiniteMagOut, (BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W), 0.U ) & ~Mux(notNaN_isInfOut, (BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U )) \| Mux(pegMinNonzeroMagOut, outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) \| Mux(pegMaxFiniteMagOut, outMaxFiniteExp.U((outExpWidth + 1).W), 0.U ) \| Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) \| Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U) val fractOut = Mux(isNaNOut \|\| io.in.isZero \|\| common_totalUnderflow, Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U), common_fractOut ) \| Fill(outSigWidth - 1, pegMaxFiniteMagOut) io.out := signOut ## expOut ## fractOut io.exceptionFlags := io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int) extends RawModule { override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(expWidth, sigWidth + 2)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( expWidth, sigWidth + 2, expWidth, sigWidth, options)) roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc roundAnyRawFNToRecFN.io.in := io.in roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags }	module RoundAnyRawFNToRecFN_ie11_is55_oe11_os53_3( // @[RoundAnyRawFNToRecFN.scala:48:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_infiniteExc, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16] input [12:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16] input [55:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16] input [2:0] io_roundingMode, // @[RoundAnyRawFNToRecFN.scala:58:16] output [64:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_infiniteExc_0 = io_infiniteExc; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [12:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [55:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [31:0] _roundMask_T_5 = 32'hFFFF; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_4 = 32'hFFFF0000; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_10 = 32'hFFFF0000; // @[primitives.scala:77:20] wire [23:0] _roundMask_T_13 = 24'hFFFF; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_14 = 32'hFFFF00; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_15 = 32'hFF00FF; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_20 = 32'hFF00FF00; // @[primitives.scala:77:20] wire [27:0] _roundMask_T_23 = 28'hFF00FF; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_24 = 32'hFF00FF0; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_25 = 32'hF0F0F0F; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_30 = 32'hF0F0F0F0; // @[primitives.scala:77:20] wire [29:0] _roundMask_T_33 = 30'hF0F0F0F; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_34 = 32'h3C3C3C3C; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_35 = 32'h33333333; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_40 = 32'hCCCCCCCC; // @[primitives.scala:77:20] wire [30:0] _roundMask_T_43 = 31'h33333333; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_44 = 32'h66666666; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_45 = 32'h55555555; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_50 = 32'hAAAAAAAA; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_56 = 16'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_55 = 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_61 = 16'hFF00; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_64 = 12'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_65 = 16'hFF0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_66 = 16'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_71 = 16'hF0F0; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_74 = 14'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_75 = 16'h3C3C; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_76 = 16'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_81 = 16'hCCCC; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_84 = 15'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_85 = 16'h6666; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_86 = 16'h5555; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_91 = 16'hAAAA; // @[primitives.scala:77:20] wire _common_underflow_T_16 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:222:27] wire [11:0] _expOut_T_4 = 12'hC31; // @[RoundAnyRawFNToRecFN.scala:258:19] wire io_detectTininess = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire _unboundedRange_anyRound_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:205:30] wire _common_underflow_T_7 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:222:49] wire _common_underflow_T_12 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:222:77] wire _common_underflow_T_13 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:226:38] wire _common_underflow_T_14 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:227:45] wire _common_underflow_T_15 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:227:60] wire [55:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22] wire [64:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33] wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66] wire [64:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_near_even = io_roundingMode_0 == 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :90:53] wire roundingMode_minMag = io_roundingMode_0 == 3'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :91:53] wire roundingMode_min = io_roundingMode_0 == 3'h2; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53] wire roundingMode_max = io_roundingMode_0 == 3'h3; // @[RoundAnyRawFNToRecFN.scala:48:5, :93:53] wire roundingMode_near_maxMag = io_roundingMode_0 == 3'h4; // @[RoundAnyRawFNToRecFN.scala:48:5, :94:53] wire roundingMode_odd = io_roundingMode_0 == 3'h6; // @[RoundAnyRawFNToRecFN.scala:48:5, :95:53] wire _roundMagUp_T = roundingMode_min & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53, :98:27] wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66] wire _roundMagUp_T_2 = roundingMode_max & _roundMagUp_T_1; // @[RoundAnyRawFNToRecFN.scala:93:53, :98:{63,66}] wire roundMagUp = _roundMagUp_T \| _roundMagUp_T_2; // @[RoundAnyRawFNToRecFN.scala:98:{27,42,63}] wire [11:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37] wire [11:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31] wire [51:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16] wire [51:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31] wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50] wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37] wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31] wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37] wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40] wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37] wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49] wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37] wire [11:0] _roundMask_T = io_in_sExp_0[11:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37] wire [11:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21] wire roundMask_msb = _roundMask_T_1[11]; // @[primitives.scala:52:21, :58:25] wire [10:0] roundMask_lsbs = _roundMask_T_1[10:0]; // @[primitives.scala:52:21, :59:26] wire roundMask_msb_1 = roundMask_lsbs[10]; // @[primitives.scala:58:25, :59:26] wire [9:0] roundMask_lsbs_1 = roundMask_lsbs[9:0]; // @[primitives.scala:59:26] wire roundMask_msb_2 = roundMask_lsbs_1[9]; // @[primitives.scala:58:25, :59:26] wire roundMask_msb_6 = roundMask_lsbs_1[9]; // @[primitives.scala:58:25, :59:26] wire [8:0] roundMask_lsbs_2 = roundMask_lsbs_1[8:0]; // @[primitives.scala:59:26] wire [8:0] roundMask_lsbs_6 = roundMask_lsbs_1[8:0]; // @[primitives.scala:59:26] wire roundMask_msb_3 = roundMask_lsbs_2[8]; // @[primitives.scala:58:25, :59:26] wire [7:0] roundMask_lsbs_3 = roundMask_lsbs_2[7:0]; // @[primitives.scala:59:26] wire roundMask_msb_4 = roundMask_lsbs_3[7]; // @[primitives.scala:58:25, :59:26] wire [6:0] roundMask_lsbs_4 = roundMask_lsbs_3[6:0]; // @[primitives.scala:59:26] wire roundMask_msb_5 = roundMask_lsbs_4[6]; // @[primitives.scala:58:25, :59:26] wire [5:0] roundMask_lsbs_5 = roundMask_lsbs_4[5:0]; // @[primitives.scala:59:26] wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_5); // @[primitives.scala:59:26, :76:56] wire [50:0] _roundMask_T_2 = roundMask_shift[63:13]; // @[primitives.scala:76:56, :78:22] wire [31:0] _roundMask_T_3 = _roundMask_T_2[31:0]; // @[primitives.scala:77:20, :78:22] wire [15:0] _roundMask_T_6 = _roundMask_T_3[31:16]; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_7 = {16'h0, _roundMask_T_6}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_8 = _roundMask_T_3[15:0]; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_9 = {_roundMask_T_8, 16'h0}; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_11 = _roundMask_T_9 & 32'hFFFF0000; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_12 = _roundMask_T_7 \| _roundMask_T_11; // @[primitives.scala:77:20] wire [23:0] _roundMask_T_16 = _roundMask_T_12[31:8]; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_17 = {8'h0, _roundMask_T_16 & 24'hFF00FF}; // @[primitives.scala:77:20] wire [23:0] _roundMask_T_18 = _roundMask_T_12[23:0]; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_19 = {_roundMask_T_18, 8'h0}; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_21 = _roundMask_T_19 & 32'hFF00FF00; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_22 = _roundMask_T_17 \| _roundMask_T_21; // @[primitives.scala:77:20] wire [27:0] _roundMask_T_26 = _roundMask_T_22[31:4]; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_27 = {4'h0, _roundMask_T_26 & 28'hF0F0F0F}; // @[primitives.scala:77:20] wire [27:0] _roundMask_T_28 = _roundMask_T_22[27:0]; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_29 = {_roundMask_T_28, 4'h0}; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_31 = _roundMask_T_29 & 32'hF0F0F0F0; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_32 = _roundMask_T_27 \| _roundMask_T_31; // @[primitives.scala:77:20] wire [29:0] _roundMask_T_36 = _roundMask_T_32[31:2]; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_37 = {2'h0, _roundMask_T_36 & 30'h33333333}; // @[primitives.scala:77:20] wire [29:0] _roundMask_T_38 = _roundMask_T_32[29:0]; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_39 = {_roundMask_T_38, 2'h0}; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_41 = _roundMask_T_39 & 32'hCCCCCCCC; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_42 = _roundMask_T_37 \| _roundMask_T_41; // @[primitives.scala:77:20] wire [30:0] _roundMask_T_46 = _roundMask_T_42[31:1]; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_47 = {1'h0, _roundMask_T_46 & 31'h55555555}; // @[primitives.scala:77:20] wire [30:0] _roundMask_T_48 = _roundMask_T_42[30:0]; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_49 = {_roundMask_T_48, 1'h0}; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_51 = _roundMask_T_49 & 32'hAAAAAAAA; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_52 = _roundMask_T_47 \| _roundMask_T_51; // @[primitives.scala:77:20] wire [18:0] _roundMask_T_53 = _roundMask_T_2[50:32]; // @[primitives.scala:77:20, :78:22] wire [15:0] _roundMask_T_54 = _roundMask_T_53[15:0]; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_57 = _roundMask_T_54[15:8]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_58 = {8'h0, _roundMask_T_57}; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_59 = _roundMask_T_54[7:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_60 = {_roundMask_T_59, 8'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_62 = _roundMask_T_60 & 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_63 = _roundMask_T_58 \| _roundMask_T_62; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_67 = _roundMask_T_63[15:4]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_68 = {4'h0, _roundMask_T_67 & 12'hF0F}; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_69 = _roundMask_T_63[11:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_70 = {_roundMask_T_69, 4'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_72 = _roundMask_T_70 & 16'hF0F0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_73 = _roundMask_T_68 \| _roundMask_T_72; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_77 = _roundMask_T_73[15:2]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_78 = {2'h0, _roundMask_T_77 & 14'h3333}; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_79 = _roundMask_T_73[13:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_80 = {_roundMask_T_79, 2'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_82 = _roundMask_T_80 & 16'hCCCC; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_83 = _roundMask_T_78 \| _roundMask_T_82; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_87 = _roundMask_T_83[15:1]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_88 = {1'h0, _roundMask_T_87 & 15'h5555}; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_89 = _roundMask_T_83[14:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_90 = {_roundMask_T_89, 1'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_92 = _roundMask_T_90 & 16'hAAAA; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_93 = _roundMask_T_88 \| _roundMask_T_92; // @[primitives.scala:77:20] wire [2:0] _roundMask_T_94 = _roundMask_T_53[18:16]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_95 = _roundMask_T_94[1:0]; // @[primitives.scala:77:20] wire _roundMask_T_96 = _roundMask_T_95[0]; // @[primitives.scala:77:20] wire _roundMask_T_97 = _roundMask_T_95[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_98 = {_roundMask_T_96, _roundMask_T_97}; // @[primitives.scala:77:20] wire _roundMask_T_99 = _roundMask_T_94[2]; // @[primitives.scala:77:20] wire [2:0] _roundMask_T_100 = {_roundMask_T_98, _roundMask_T_99}; // @[primitives.scala:77:20] wire [18:0] _roundMask_T_101 = {_roundMask_T_93, _roundMask_T_100}; // @[primitives.scala:77:20] wire [50:0] _roundMask_T_102 = {_roundMask_T_52, _roundMask_T_101}; // @[primitives.scala:77:20] wire [50:0] _roundMask_T_103 = ~_roundMask_T_102; // @[primitives.scala:73:32, :77:20] wire [50:0] _roundMask_T_104 = roundMask_msb_5 ? 51'h0 : _roundMask_T_103; // @[primitives.scala:58:25, :73:{21,32}] wire [50:0] _roundMask_T_105 = ~_roundMask_T_104; // @[primitives.scala:73:{17,21}] wire [50:0] _roundMask_T_106 = ~_roundMask_T_105; // @[primitives.scala:73:{17,32}] wire [50:0] _roundMask_T_107 = roundMask_msb_4 ? 51'h0 : _roundMask_T_106; // @[primitives.scala:58:25, :73:{21,32}] wire [50:0] _roundMask_T_108 = ~_roundMask_T_107; // @[primitives.scala:73:{17,21}] wire [50:0] _roundMask_T_109 = ~_roundMask_T_108; // @[primitives.scala:73:{17,32}] wire [50:0] _roundMask_T_110 = roundMask_msb_3 ? 51'h0 : _roundMask_T_109; // @[primitives.scala:58:25, :73:{21,32}] wire [50:0] _roundMask_T_111 = ~_roundMask_T_110; // @[primitives.scala:73:{17,21}] wire [50:0] _roundMask_T_112 = ~_roundMask_T_111; // @[primitives.scala:73:{17,32}] wire [50:0] _roundMask_T_113 = roundMask_msb_2 ? 51'h0 : _roundMask_T_112; // @[primitives.scala:58:25, :73:{21,32}] wire [50:0] _roundMask_T_114 = ~_roundMask_T_113; // @[primitives.scala:73:{17,21}] wire [53:0] _roundMask_T_115 = {_roundMask_T_114, 3'h7}; // @[primitives.scala:68:58, :73:17] wire roundMask_msb_7 = roundMask_lsbs_6[8]; // @[primitives.scala:58:25, :59:26] wire [7:0] roundMask_lsbs_7 = roundMask_lsbs_6[7:0]; // @[primitives.scala:59:26] wire roundMask_msb_8 = roundMask_lsbs_7[7]; // @[primitives.scala:58:25, :59:26] wire [6:0] roundMask_lsbs_8 = roundMask_lsbs_7[6:0]; // @[primitives.scala:59:26] wire roundMask_msb_9 = roundMask_lsbs_8[6]; // @[primitives.scala:58:25, :59:26] wire [5:0] roundMask_lsbs_9 = roundMask_lsbs_8[5:0]; // @[primitives.scala:59:26] wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_9); // @[primitives.scala:59:26, :76:56] wire [2:0] _roundMask_T_116 = roundMask_shift_1[2:0]; // @[primitives.scala:76:56, :78:22] wire [1:0] _roundMask_T_117 = _roundMask_T_116[1:0]; // @[primitives.scala:77:20, :78:22] wire _roundMask_T_118 = _roundMask_T_117[0]; // @[primitives.scala:77:20] wire _roundMask_T_119 = _roundMask_T_117[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_120 = {_roundMask_T_118, _roundMask_T_119}; // @[primitives.scala:77:20] wire _roundMask_T_121 = _roundMask_T_116[2]; // @[primitives.scala:77:20, :78:22] wire [2:0] _roundMask_T_122 = {_roundMask_T_120, _roundMask_T_121}; // @[primitives.scala:77:20] wire [2:0] _roundMask_T_123 = roundMask_msb_9 ? _roundMask_T_122 : 3'h0; // @[primitives.scala:58:25, :62:24, :77:20] wire [2:0] _roundMask_T_124 = roundMask_msb_8 ? _roundMask_T_123 : 3'h0; // @[primitives.scala:58:25, :62:24] wire [2:0] _roundMask_T_125 = roundMask_msb_7 ? _roundMask_T_124 : 3'h0; // @[primitives.scala:58:25, :62:24] wire [2:0] _roundMask_T_126 = roundMask_msb_6 ? _roundMask_T_125 : 3'h0; // @[primitives.scala:58:25, :62:24] wire [53:0] _roundMask_T_127 = roundMask_msb_1 ? _roundMask_T_115 : {51'h0, _roundMask_T_126}; // @[primitives.scala:58:25, :62:24, :67:24, :68:58] wire [53:0] _roundMask_T_128 = roundMask_msb ? _roundMask_T_127 : 54'h0; // @[primitives.scala:58:25, :62:24, :67:24] wire [53:0] _roundMask_T_129 = _roundMask_T_128; // @[primitives.scala:62:24] wire [55:0] roundMask = {_roundMask_T_129, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}] wire [56:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41] wire [55:0] shiftedRoundMask = _shiftedRoundMask_T[56:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}] wire [55:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28] wire [55:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}] wire [55:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40] wire roundPosBit = \|_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}] wire [55:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42] wire anyRoundExtra = \|_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}] wire anyRound = roundPosBit \| anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36] wire _GEN = roundingMode_near_even \| roundingMode_near_maxMag; // @[RoundAnyRawFNToRecFN.scala:90:53, :94:53, :169:38] wire _roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:169:38] assign _roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38] wire _unboundedRange_roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:207:38] assign _unboundedRange_roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :207:38] wire _overflow_roundMagUp_T; // @[RoundAnyRawFNToRecFN.scala:243:32] assign _overflow_roundMagUp_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :243:32] wire _roundIncr_T_1 = _roundIncr_T & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:{38,67}] wire _roundIncr_T_2 = roundMagUp & anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :166:36, :171:29] wire roundIncr = _roundIncr_T_1 \| _roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31, :171:29] wire [55:0] _roundedSig_T = adjustedSig \| roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32] wire [53:0] _roundedSig_T_1 = _roundedSig_T[55:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}] wire [54:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 55'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}] wire _roundedSig_T_3 = roundingMode_near_even & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:90:53, :164:56, :175:49] wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30] wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30] wire [54:0] _roundedSig_T_6 = roundMask[55:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35] wire [54:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 55'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35] wire [54:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}] wire [54:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21] wire [55:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32] wire [55:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}] wire [53:0] _roundedSig_T_12 = _roundedSig_T_11[55:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}] wire _roundedSig_T_13 = roundingMode_odd & anyRound; // @[RoundAnyRawFNToRecFN.scala:95:53, :166:36, :181:42] wire [54:0] _roundedSig_T_14 = roundPosMask[55:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67] wire [54:0] _roundedSig_T_15 = _roundedSig_T_13 ? _roundedSig_T_14 : 55'h0; // @[RoundAnyRawFNToRecFN.scala:181:{24,42,67}] wire [54:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12} \| _roundedSig_T_15; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}, :181:24] wire [54:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47] wire [1:0] _sRoundedExp_T = roundedSig[54:53]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54] wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}] wire [13:0] sRoundedExp = {io_in_sExp_0[12], io_in_sExp_0} + {{11{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}] assign _common_expOut_T = sRoundedExp[11:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37] assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37] wire [51:0] _common_fractOut_T = roundedSig[52:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27] wire [51:0] _common_fractOut_T_1 = roundedSig[51:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27] assign _common_fractOut_T_2 = _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:189:16, :191:27] assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16] wire [3:0] _common_overflow_T = sRoundedExp[13:10]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30] assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}] assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50] assign _common_totalUnderflow_T = $signed(sRoundedExp) < 14'sh3CE; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31] assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31] wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45] wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44] wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61] wire unboundedRange_roundPosBit = _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:203:{16,61}] wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63] wire _unboundedRange_anyRound_T_3 = \|_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}] wire unboundedRange_anyRound = _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{49,70}] wire _unboundedRange_roundIncr_T_1 = _unboundedRange_roundIncr_T & unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:{38,67}] wire _unboundedRange_roundIncr_T_2 = roundMagUp & unboundedRange_anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :205:49, :209:29] wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1 \| _unboundedRange_roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46, :209:29] wire _roundCarry_T = roundedSig[54]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27] wire _roundCarry_T_1 = roundedSig[53]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27] wire roundCarry = _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:211:16, :213:27] wire [1:0] _common_underflow_T = io_in_sExp_0[12:11]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49] wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}] wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}] wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57] wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49] wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71] wire _common_underflow_T_5 = _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:221:{30,71}] wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30] wire _common_underflow_T_17 = _common_underflow_T_6; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76] wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49] wire _common_underflow_T_10 = _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:223:39, :225:49] wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}] assign _common_underflow_T_18 = common_totalUnderflow \| _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76] assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40] assign _common_inexact_T = common_totalUnderflow \| anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49] assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49] wire isNaNOut = io_invalidExc_0 \| io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34] wire notNaN_isSpecialInfOut = io_infiniteExc_0 \| io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49] wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22] wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36] wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}] wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64] wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}] wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32] wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32] wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43] wire inexact = overflow \| _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}] wire overflow_roundMagUp = _overflow_roundMagUp_T \| roundMagUp; // @[RoundAnyRawFNToRecFN.scala:98:42, :243:{32,60}] wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20] wire _pegMinNonzeroMagOut_T_1 = roundMagUp \| roundingMode_odd; // @[RoundAnyRawFNToRecFN.scala:95:53, :98:42, :245:60] wire pegMinNonzeroMagOut = _pegMinNonzeroMagOut_T & _pegMinNonzeroMagOut_T_1; // @[RoundAnyRawFNToRecFN.scala:245:{20,45,60}] wire _pegMaxFiniteMagOut_T = ~overflow_roundMagUp; // @[RoundAnyRawFNToRecFN.scala:243:60, :246:42] wire pegMaxFiniteMagOut = overflow & _pegMaxFiniteMagOut_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :246:{39,42}] wire _notNaN_isInfOut_T = overflow & overflow_roundMagUp; // @[RoundAnyRawFNToRecFN.scala:238:32, :243:60, :248:45] wire notNaN_isInfOut = notNaN_isSpecialInfOut \| _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}] wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22] wire _expOut_T = io_in_isZero_0 \| common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32] wire [11:0] _expOut_T_1 = _expOut_T ? 12'hE00 : 12'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}] wire [11:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}] wire [11:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14] wire [11:0] _expOut_T_5 = pegMinNonzeroMagOut ? 12'hC31 : 12'h0; // @[RoundAnyRawFNToRecFN.scala:245:45, :257:18] wire [11:0] _expOut_T_6 = ~_expOut_T_5; // @[RoundAnyRawFNToRecFN.scala:257:{14,18}] wire [11:0] _expOut_T_7 = _expOut_T_3 & _expOut_T_6; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17, :257:14] wire [11:0] _expOut_T_8 = {1'h0, pegMaxFiniteMagOut, 10'h0}; // @[RoundAnyRawFNToRecFN.scala:246:39, :261:18] wire [11:0] _expOut_T_9 = ~_expOut_T_8; // @[RoundAnyRawFNToRecFN.scala:261:{14,18}] wire [11:0] _expOut_T_10 = _expOut_T_7 & _expOut_T_9; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17, :261:14] wire [11:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 9'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18] wire [11:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}] wire [11:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14] wire [11:0] _expOut_T_14 = pegMinNonzeroMagOut ? 12'h3CE : 12'h0; // @[RoundAnyRawFNToRecFN.scala:245:45, :269:16] wire [11:0] _expOut_T_15 = _expOut_T_13 \| _expOut_T_14; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18, :269:16] wire [11:0] _expOut_T_16 = pegMaxFiniteMagOut ? 12'hBFF : 12'h0; // @[RoundAnyRawFNToRecFN.scala:246:39, :273:16] wire [11:0] _expOut_T_17 = _expOut_T_15 \| _expOut_T_16; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15, :273:16] wire [11:0] _expOut_T_18 = notNaN_isInfOut ? 12'hC00 : 12'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16] wire [11:0] _expOut_T_19 = _expOut_T_17 \| _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16] wire [11:0] _expOut_T_20 = isNaNOut ? 12'hE00 : 12'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16] wire [11:0] expOut = _expOut_T_19 \| _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16] wire _fractOut_T = isNaNOut \| io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22] wire _fractOut_T_1 = _fractOut_T \| common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}] wire [51:0] _fractOut_T_2 = {isNaNOut, 51'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16] wire [51:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16] wire [51:0] _fractOut_T_4 = {52{pegMaxFiniteMagOut}}; // @[RoundAnyRawFNToRecFN.scala:246:39, :284:13] wire [51:0] fractOut = _fractOut_T_3 \| _fractOut_T_4; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11, :284:13] wire [12:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23] assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}] assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33] wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, io_infiniteExc_0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23] wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}] wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}] assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] endmodule
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag }	module OptimizationBarrier_TLBEntryData_282( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth \| params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset \|\| !sio.sink_reset_n) \|\| !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise \|\| prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready \|\| !sio.source_reset_n \|\| reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise \|\| prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }	module AsyncValidSync_178( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_188 io_out_sink_extend ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_332( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth \| params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset \|\| !sio.sink_reset_n) \|\| !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise \|\| prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready \|\| !sio.source_reset_n \|\| reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise \|\| prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }	module AsyncValidSync_134( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_144 io_out_source_extend ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File util.scala: //**************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v3.common.{MicroOp} import boom.v3.exu.{BrUpdateInfo} / * Object to XOR fold a input register of fullLength into a compressedLength. / object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /* * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks / object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask) } def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) } } /* * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. / object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /* * Object to return a BR mask given a MicroOp mask and old BR mask. / object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask) out } } /* * Object to check if at least 1 bit matches in two masks / object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /* * Object to clear one bit in a mask given an index / object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /* * Object to shift a register over by one bit and concat a new one / object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /* * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. / object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /* * Object to increment an input value, wrapping it if * necessary. / object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /* * Object to decrement an input value, wrapping it if * necessary. / object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /* * Object to increment an input value, wrapping it if * necessary. / object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /* * Object to decrement an input value, wrapping it if * necessary. / object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /* * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. / object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc \| (b-1).U) } } /* * Object to rotate a signal left by one / object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /* * Object to sext a value to a particular length. / object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /* * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. / object ImmGen { import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U} def apply(ip: UInt, isel: UInt): SInt = { val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U \|\| isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J \|\| isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S \|\| isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt } } /* * Object to get the FP rounding mode out of a packed immediate. / object ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } } /* * Object to get the FP function fype from a packed immediate. * Note: only works if !(IS_B or IS_S) / object ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } } /* * Object to see if an instruction is a JALR. / object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /* * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). / object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /* * Object to return the lowest bit position after the head. / object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /* * Object to determine whether queue * index i0 is older than index i1. / object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } /* * Set all bits at or below the highest order '1'. / object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_\|_) } } /* * Set all bits at or above the lowest order '1'. / object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_\|_) } } /* * Transpose a matrix of Chisel Vecs. / object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /* * N-wide one-hot priority encoder. / object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /* * Connect the first k of n valid input interfaces to k output interfaces. / class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_\|\|_)) val out_valids = sels map (col => col.reduce(_\|\|_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /* * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). / class BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v3.common.BoomModule()(p) with boom.v3.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire) val do_deq = WireInit((io.deq.ready \|\| !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop) uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop)) io.deq.bits := out io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop) // For flow queue behavior. if (flow) { when (io.empty) { io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop) io.deq.bits := io.enq.bits io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) do_deq := false.B when (io.deq.ready) { do_enq := false.B } } } private val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /* * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" / def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) / def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) / def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) / def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /* * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) / def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /* * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) / def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /* * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line / def apply(strs: String)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } File consts.scala: //**************************************************************************** // Copyright (c) 2011 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Constants //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.common.constants import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util.Str import freechips.rocketchip.rocket.RVCExpander / * Mixin for issue queue types / trait IQType { val IQT_SZ = 3 val IQT_INT = 1.U(IQT_SZ.W) val IQT_MEM = 2.U(IQT_SZ.W) val IQT_FP = 4.U(IQT_SZ.W) val IQT_MFP = 6.U(IQT_SZ.W) } /* * Mixin for scalar operation constants / trait ScalarOpConstants { val X = BitPat("b?") val Y = BitPat("b1") val N = BitPat("b0") //********************************* // Extra Constants // Which branch predictor predicted us val BSRC_SZ = 2 val BSRC_1 = 0.U(BSRC_SZ.W) // 1-cycle branch pred val BSRC_2 = 1.U(BSRC_SZ.W) // 2-cycle branch pred val BSRC_3 = 2.U(BSRC_SZ.W) // 3-cycle branch pred val BSRC_C = 3.U(BSRC_SZ.W) // core branch resolution //******************************** // Control Signals // CFI types val CFI_SZ = 3 val CFI_X = 0.U(CFI_SZ.W) // Not a CFI instruction val CFI_BR = 1.U(CFI_SZ.W) // Branch val CFI_JAL = 2.U(CFI_SZ.W) // JAL val CFI_JALR = 3.U(CFI_SZ.W) // JALR // PC Select Signal val PC_PLUS4 = 0.U(2.W) // PC + 4 val PC_BRJMP = 1.U(2.W) // brjmp_target val PC_JALR = 2.U(2.W) // jump_reg_target // Branch Type val BR_N = 0.U(4.W) // Next val BR_NE = 1.U(4.W) // Branch on NotEqual val BR_EQ = 2.U(4.W) // Branch on Equal val BR_GE = 3.U(4.W) // Branch on Greater/Equal val BR_GEU = 4.U(4.W) // Branch on Greater/Equal Unsigned val BR_LT = 5.U(4.W) // Branch on Less Than val BR_LTU = 6.U(4.W) // Branch on Less Than Unsigned val BR_J = 7.U(4.W) // Jump val BR_JR = 8.U(4.W) // Jump Register // RS1 Operand Select Signal val OP1_RS1 = 0.U(2.W) // Register Source #1 val OP1_ZERO= 1.U(2.W) val OP1_PC = 2.U(2.W) val OP1_X = BitPat("b??") // RS2 Operand Select Signal val OP2_RS2 = 0.U(3.W) // Register Source #2 val OP2_IMM = 1.U(3.W) // immediate val OP2_ZERO= 2.U(3.W) // constant 0 val OP2_NEXT= 3.U(3.W) // constant 2/4 (for PC+2/4) val OP2_IMMC= 4.U(3.W) // for CSR imm found in RS1 val OP2_X = BitPat("b???") // Register File Write Enable Signal val REN_0 = false.B val REN_1 = true.B // Is 32b Word or 64b Doubldword? val SZ_DW = 1 val DW_X = true.B // Bool(xLen==64) val DW_32 = false.B val DW_64 = true.B val DW_XPR = true.B // Bool(xLen==64) // Memory Enable Signal val MEN_0 = false.B val MEN_1 = true.B val MEN_X = false.B // Immediate Extend Select val IS_I = 0.U(3.W) // I-Type (LD,ALU) val IS_S = 1.U(3.W) // S-Type (ST) val IS_B = 2.U(3.W) // SB-Type (BR) val IS_U = 3.U(3.W) // U-Type (LUI/AUIPC) val IS_J = 4.U(3.W) // UJ-Type (J/JAL) val IS_X = BitPat("b???") // Decode Stage Control Signals val RT_FIX = 0.U(2.W) val RT_FLT = 1.U(2.W) val RT_PAS = 3.U(2.W) // pass-through (prs1 := lrs1, etc) val RT_X = 2.U(2.W) // not-a-register (but shouldn't get a busy-bit, etc.) // TODO rename RT_NAR // Micro-op opcodes // TODO change micro-op opcodes into using enum val UOPC_SZ = 7 val uopX = BitPat.dontCare(UOPC_SZ) val uopNOP = 0.U(UOPC_SZ.W) val uopLD = 1.U(UOPC_SZ.W) val uopSTA = 2.U(UOPC_SZ.W) // store address generation val uopSTD = 3.U(UOPC_SZ.W) // store data generation val uopLUI = 4.U(UOPC_SZ.W) val uopADDI = 5.U(UOPC_SZ.W) val uopANDI = 6.U(UOPC_SZ.W) val uopORI = 7.U(UOPC_SZ.W) val uopXORI = 8.U(UOPC_SZ.W) val uopSLTI = 9.U(UOPC_SZ.W) val uopSLTIU= 10.U(UOPC_SZ.W) val uopSLLI = 11.U(UOPC_SZ.W) val uopSRAI = 12.U(UOPC_SZ.W) val uopSRLI = 13.U(UOPC_SZ.W) val uopSLL = 14.U(UOPC_SZ.W) val uopADD = 15.U(UOPC_SZ.W) val uopSUB = 16.U(UOPC_SZ.W) val uopSLT = 17.U(UOPC_SZ.W) val uopSLTU = 18.U(UOPC_SZ.W) val uopAND = 19.U(UOPC_SZ.W) val uopOR = 20.U(UOPC_SZ.W) val uopXOR = 21.U(UOPC_SZ.W) val uopSRA = 22.U(UOPC_SZ.W) val uopSRL = 23.U(UOPC_SZ.W) val uopBEQ = 24.U(UOPC_SZ.W) val uopBNE = 25.U(UOPC_SZ.W) val uopBGE = 26.U(UOPC_SZ.W) val uopBGEU = 27.U(UOPC_SZ.W) val uopBLT = 28.U(UOPC_SZ.W) val uopBLTU = 29.U(UOPC_SZ.W) val uopCSRRW= 30.U(UOPC_SZ.W) val uopCSRRS= 31.U(UOPC_SZ.W) val uopCSRRC= 32.U(UOPC_SZ.W) val uopCSRRWI=33.U(UOPC_SZ.W) val uopCSRRSI=34.U(UOPC_SZ.W) val uopCSRRCI=35.U(UOPC_SZ.W) val uopJ = 36.U(UOPC_SZ.W) val uopJAL = 37.U(UOPC_SZ.W) val uopJALR = 38.U(UOPC_SZ.W) val uopAUIPC= 39.U(UOPC_SZ.W) //val uopSRET = 40.U(UOPC_SZ.W) val uopCFLSH= 41.U(UOPC_SZ.W) val uopFENCE= 42.U(UOPC_SZ.W) val uopADDIW= 43.U(UOPC_SZ.W) val uopADDW = 44.U(UOPC_SZ.W) val uopSUBW = 45.U(UOPC_SZ.W) val uopSLLIW= 46.U(UOPC_SZ.W) val uopSLLW = 47.U(UOPC_SZ.W) val uopSRAIW= 48.U(UOPC_SZ.W) val uopSRAW = 49.U(UOPC_SZ.W) val uopSRLIW= 50.U(UOPC_SZ.W) val uopSRLW = 51.U(UOPC_SZ.W) val uopMUL = 52.U(UOPC_SZ.W) val uopMULH = 53.U(UOPC_SZ.W) val uopMULHU= 54.U(UOPC_SZ.W) val uopMULHSU=55.U(UOPC_SZ.W) val uopMULW = 56.U(UOPC_SZ.W) val uopDIV = 57.U(UOPC_SZ.W) val uopDIVU = 58.U(UOPC_SZ.W) val uopREM = 59.U(UOPC_SZ.W) val uopREMU = 60.U(UOPC_SZ.W) val uopDIVW = 61.U(UOPC_SZ.W) val uopDIVUW= 62.U(UOPC_SZ.W) val uopREMW = 63.U(UOPC_SZ.W) val uopREMUW= 64.U(UOPC_SZ.W) val uopFENCEI = 65.U(UOPC_SZ.W) // = 66.U(UOPC_SZ.W) val uopAMO_AG = 67.U(UOPC_SZ.W) // AMO-address gen (use normal STD for datagen) val uopFMV_W_X = 68.U(UOPC_SZ.W) val uopFMV_D_X = 69.U(UOPC_SZ.W) val uopFMV_X_W = 70.U(UOPC_SZ.W) val uopFMV_X_D = 71.U(UOPC_SZ.W) val uopFSGNJ_S = 72.U(UOPC_SZ.W) val uopFSGNJ_D = 73.U(UOPC_SZ.W) val uopFCVT_S_D = 74.U(UOPC_SZ.W) val uopFCVT_D_S = 75.U(UOPC_SZ.W) val uopFCVT_S_X = 76.U(UOPC_SZ.W) val uopFCVT_D_X = 77.U(UOPC_SZ.W) val uopFCVT_X_S = 78.U(UOPC_SZ.W) val uopFCVT_X_D = 79.U(UOPC_SZ.W) val uopCMPR_S = 80.U(UOPC_SZ.W) val uopCMPR_D = 81.U(UOPC_SZ.W) val uopFCLASS_S = 82.U(UOPC_SZ.W) val uopFCLASS_D = 83.U(UOPC_SZ.W) val uopFMINMAX_S = 84.U(UOPC_SZ.W) val uopFMINMAX_D = 85.U(UOPC_SZ.W) // = 86.U(UOPC_SZ.W) val uopFADD_S = 87.U(UOPC_SZ.W) val uopFSUB_S = 88.U(UOPC_SZ.W) val uopFMUL_S = 89.U(UOPC_SZ.W) val uopFADD_D = 90.U(UOPC_SZ.W) val uopFSUB_D = 91.U(UOPC_SZ.W) val uopFMUL_D = 92.U(UOPC_SZ.W) val uopFMADD_S = 93.U(UOPC_SZ.W) val uopFMSUB_S = 94.U(UOPC_SZ.W) val uopFNMADD_S = 95.U(UOPC_SZ.W) val uopFNMSUB_S = 96.U(UOPC_SZ.W) val uopFMADD_D = 97.U(UOPC_SZ.W) val uopFMSUB_D = 98.U(UOPC_SZ.W) val uopFNMADD_D = 99.U(UOPC_SZ.W) val uopFNMSUB_D = 100.U(UOPC_SZ.W) val uopFDIV_S = 101.U(UOPC_SZ.W) val uopFDIV_D = 102.U(UOPC_SZ.W) val uopFSQRT_S = 103.U(UOPC_SZ.W) val uopFSQRT_D = 104.U(UOPC_SZ.W) val uopWFI = 105.U(UOPC_SZ.W) // pass uop down the CSR pipeline val uopERET = 106.U(UOPC_SZ.W) // pass uop down the CSR pipeline, also is ERET val uopSFENCE = 107.U(UOPC_SZ.W) val uopROCC = 108.U(UOPC_SZ.W) val uopMOV = 109.U(UOPC_SZ.W) // conditional mov decoded from "add rd, x0, rs2" // The Bubble Instruction (Machine generated NOP) // Insert (XOR x0,x0,x0) which is different from software compiler // generated NOPs which are (ADDI x0, x0, 0). // Reasoning for this is to let visualizers and stat-trackers differentiate // between software NOPs and machine-generated Bubbles in the pipeline. val BUBBLE = (0x4033).U(32.W) def NullMicroOp()(implicit p: Parameters): boom.v3.common.MicroOp = { val uop = Wire(new boom.v3.common.MicroOp) uop := DontCare // Overridden in the following lines uop.uopc := uopNOP // maybe not required, but helps on asserts that try to catch spurious behavior uop.bypassable := false.B uop.fp_val := false.B uop.uses_stq := false.B uop.uses_ldq := false.B uop.pdst := 0.U uop.dst_rtype := RT_X val cs = Wire(new boom.v3.common.CtrlSignals()) cs := DontCare // Overridden in the following lines cs.br_type := BR_N cs.csr_cmd := freechips.rocketchip.rocket.CSR.N cs.is_load := false.B cs.is_sta := false.B cs.is_std := false.B uop.ctrl := cs uop } } / * Mixin for RISCV constants / trait RISCVConstants { // abstract out instruction decode magic numbers val RD_MSB = 11 val RD_LSB = 7 val RS1_MSB = 19 val RS1_LSB = 15 val RS2_MSB = 24 val RS2_LSB = 20 val RS3_MSB = 31 val RS3_LSB = 27 val CSR_ADDR_MSB = 31 val CSR_ADDR_LSB = 20 val CSR_ADDR_SZ = 12 // location of the fifth bit in the shamt (for checking for illegal ops for SRAIW,etc.) val SHAMT_5_BIT = 25 val LONGEST_IMM_SZ = 20 val X0 = 0.U val RA = 1.U // return address register // memory consistency model // The C/C++ atomics MCM requires that two loads to the same address maintain program order. // The Cortex A9 does NOT enforce load/load ordering (which leads to buggy behavior). val MCM_ORDER_DEPENDENT_LOADS = true val jal_opc = (0x6f).U val jalr_opc = (0x67).U def GetUop(inst: UInt): UInt = inst(6,0) def GetRd (inst: UInt): UInt = inst(RD_MSB,RD_LSB) def GetRs1(inst: UInt): UInt = inst(RS1_MSB,RS1_LSB) def ExpandRVC(inst: UInt)(implicit p: Parameters): UInt = { val rvc_exp = Module(new RVCExpander) rvc_exp.io.in := inst Mux(rvc_exp.io.rvc, rvc_exp.io.out.bits, inst) } // Note: Accepts only EXPANDED rvc instructions def ComputeBranchTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = { val b_imm32 = Cat(Fill(20,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) ((pc.asSInt + b_imm32.asSInt).asSInt & (-2).S).asUInt } // Note: Accepts only EXPANDED rvc instructions def ComputeJALTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = { val j_imm32 = Cat(Fill(12,inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) ((pc.asSInt + j_imm32.asSInt).asSInt & (-2).S).asUInt } // Note: Accepts only EXPANDED rvc instructions def GetCfiType(inst: UInt)(implicit p: Parameters): UInt = { val bdecode = Module(new boom.v3.exu.BranchDecode) bdecode.io.inst := inst bdecode.io.pc := 0.U bdecode.io.out.cfi_type } } /* * Mixin for exception cause constants / trait ExcCauseConstants { // a memory disambigious misspeculation occurred val MINI_EXCEPTION_MEM_ORDERING = 16.U val MINI_EXCEPTION_CSR_REPLAY = 17.U require (!freechips.rocketchip.rocket.Causes.all.contains(16)) require (!freechips.rocketchip.rocket.Causes.all.contains(17)) } File issue-slot.scala: //*************************************************************************** // Copyright (c) 2015 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Issue Slot Logic //-------------------------------------------------------------------------- //------------------------------------------------------------------------------ // // Note: stores (and AMOs) are "broken down" into 2 uops, but stored within a single issue-slot. // TODO XXX make a separate issueSlot for MemoryIssueSlots, and only they break apart stores. // TODO Disable ldspec for FP queue. package boom.v3.exu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import boom.v3.common._ import boom.v3.util._ import FUConstants._ / * IO bundle to interact with Issue slot * * @param numWakeupPorts number of wakeup ports for the slot / class IssueSlotIO(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomBundle { val valid = Output(Bool()) val will_be_valid = Output(Bool()) // TODO code review, do we need this signal so explicitely? val request = Output(Bool()) val request_hp = Output(Bool()) val grant = Input(Bool()) val brupdate = Input(new BrUpdateInfo()) val kill = Input(Bool()) // pipeline flush val clear = Input(Bool()) // entry being moved elsewhere (not mutually exclusive with grant) val ldspec_miss = Input(Bool()) // Previous cycle's speculative load wakeup was mispredicted. val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new IqWakeup(maxPregSz)))) val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W))) val spec_ld_wakeup = Flipped(Vec(memWidth, Valid(UInt(width=maxPregSz.W)))) val in_uop = Flipped(Valid(new MicroOp())) // if valid, this WILL overwrite an entry! val out_uop = Output(new MicroOp()) // the updated slot uop; will be shifted upwards in a collasping queue. val uop = Output(new MicroOp()) // the current Slot's uop. Sent down the pipeline when issued. val debug = { val result = new Bundle { val p1 = Bool() val p2 = Bool() val p3 = Bool() val ppred = Bool() val state = UInt(width=2.W) } Output(result) } } /* * Single issue slot. Holds a uop within the issue queue * * @param numWakeupPorts number of wakeup ports / class IssueSlot(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomModule with IssueUnitConstants { val io = IO(new IssueSlotIO(numWakeupPorts)) // slot invalid? // slot is valid, holding 1 uop // slot is valid, holds 2 uops (like a store) def is_invalid = state === s_invalid def is_valid = state =/= s_invalid val next_state = Wire(UInt()) // the next state of this slot (which might then get moved to a new slot) val next_uopc = Wire(UInt()) // the next uopc of this slot (which might then get moved to a new slot) val next_lrs1_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot) val next_lrs2_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot) val state = RegInit(s_invalid) val p1 = RegInit(false.B) val p2 = RegInit(false.B) val p3 = RegInit(false.B) val ppred = RegInit(false.B) // Poison if woken up by speculative load. // Poison lasts 1 cycle (as ldMiss will come on the next cycle). // SO if poisoned is true, set it to false! val p1_poisoned = RegInit(false.B) val p2_poisoned = RegInit(false.B) p1_poisoned := false.B p2_poisoned := false.B val next_p1_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned) val next_p2_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned) val slot_uop = RegInit(NullMicroOp) val next_uop = Mux(io.in_uop.valid, io.in_uop.bits, slot_uop) //----------------------------------------------------------------------------- // next slot state computation // compute the next state for THIS entry slot (in a collasping queue, the // current uop may get moved elsewhere, and a new uop can enter when (io.kill) { state := s_invalid } .elsewhen (io.in_uop.valid) { state := io.in_uop.bits.iw_state } .elsewhen (io.clear) { state := s_invalid } .otherwise { state := next_state } //----------------------------------------------------------------------------- // "update" state // compute the next state for the micro-op in this slot. This micro-op may // be moved elsewhere, so the "next_state" travels with it. // defaults next_state := state next_uopc := slot_uop.uopc next_lrs1_rtype := slot_uop.lrs1_rtype next_lrs2_rtype := slot_uop.lrs2_rtype when (io.kill) { next_state := s_invalid } .elsewhen ((io.grant && (state === s_valid_1)) \|\| (io.grant && (state === s_valid_2) && p1 && p2 && ppred)) { // try to issue this uop. when (!(io.ldspec_miss && (p1_poisoned \|\| p2_poisoned))) { next_state := s_invalid } } .elsewhen (io.grant && (state === s_valid_2)) { when (!(io.ldspec_miss && (p1_poisoned \|\| p2_poisoned))) { next_state := s_valid_1 when (p1) { slot_uop.uopc := uopSTD next_uopc := uopSTD slot_uop.lrs1_rtype := RT_X next_lrs1_rtype := RT_X } .otherwise { slot_uop.lrs2_rtype := RT_X next_lrs2_rtype := RT_X } } } when (io.in_uop.valid) { slot_uop := io.in_uop.bits assert (is_invalid \|\| io.clear \|\| io.kill, "trying to overwrite a valid issue slot.") } // Wakeup Compare Logic // these signals are the "next_p" for the current slot's micro-op. // they are important for shifting the current slot_uop up to an other entry. val next_p1 = WireInit(p1) val next_p2 = WireInit(p2) val next_p3 = WireInit(p3) val next_ppred = WireInit(ppred) when (io.in_uop.valid) { p1 := !(io.in_uop.bits.prs1_busy) p2 := !(io.in_uop.bits.prs2_busy) p3 := !(io.in_uop.bits.prs3_busy) ppred := !(io.in_uop.bits.ppred_busy) } when (io.ldspec_miss && next_p1_poisoned) { assert(next_uop.prs1 =/= 0.U, "Poison bit can't be set for prs1=x0!") p1 := false.B } when (io.ldspec_miss && next_p2_poisoned) { assert(next_uop.prs2 =/= 0.U, "Poison bit can't be set for prs2=x0!") p2 := false.B } for (i <- 0 until numWakeupPorts) { when (io.wakeup_ports(i).valid && (io.wakeup_ports(i).bits.pdst === next_uop.prs1)) { p1 := true.B } when (io.wakeup_ports(i).valid && (io.wakeup_ports(i).bits.pdst === next_uop.prs2)) { p2 := true.B } when (io.wakeup_ports(i).valid && (io.wakeup_ports(i).bits.pdst === next_uop.prs3)) { p3 := true.B } } when (io.pred_wakeup_port.valid && io.pred_wakeup_port.bits === next_uop.ppred) { ppred := true.B } for (w <- 0 until memWidth) { assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U), "Loads to x0 should never speculatively wakeup other instructions") } // TODO disable if FP IQ. for (w <- 0 until memWidth) { when (io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === next_uop.prs1 && next_uop.lrs1_rtype === RT_FIX) { p1 := true.B p1_poisoned := true.B assert (!next_p1_poisoned) } when (io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === next_uop.prs2 && next_uop.lrs2_rtype === RT_FIX) { p2 := true.B p2_poisoned := true.B assert (!next_p2_poisoned) } } // Handle branch misspeculations val next_br_mask = GetNewBrMask(io.brupdate, slot_uop) // was this micro-op killed by a branch? if yes, we can't let it be valid if // we compact it into an other entry when (IsKilledByBranch(io.brupdate, slot_uop)) { next_state := s_invalid } when (!io.in_uop.valid) { slot_uop.br_mask := next_br_mask } //------------------------------------------------------------- // Request Logic io.request := is_valid && p1 && p2 && p3 && ppred && !io.kill val high_priority = slot_uop.is_br \|\| slot_uop.is_jal \|\| slot_uop.is_jalr io.request_hp := io.request && high_priority when (state === s_valid_1) { io.request := p1 && p2 && p3 && ppred && !io.kill } .elsewhen (state === s_valid_2) { io.request := (p1 \|\| p2) && ppred && !io.kill } .otherwise { io.request := false.B } //assign outputs io.valid := is_valid io.uop := slot_uop io.uop.iw_p1_poisoned := p1_poisoned io.uop.iw_p2_poisoned := p2_poisoned // micro-op will vacate due to grant. val may_vacate = io.grant && ((state === s_valid_1) \|\| (state === s_valid_2) && p1 && p2 && ppred) val squash_grant = io.ldspec_miss && (p1_poisoned \|\| p2_poisoned) io.will_be_valid := is_valid && !(may_vacate && !squash_grant) io.out_uop := slot_uop io.out_uop.iw_state := next_state io.out_uop.uopc := next_uopc io.out_uop.lrs1_rtype := next_lrs1_rtype io.out_uop.lrs2_rtype := next_lrs2_rtype io.out_uop.br_mask := next_br_mask io.out_uop.prs1_busy := !p1 io.out_uop.prs2_busy := !p2 io.out_uop.prs3_busy := !p3 io.out_uop.ppred_busy := !ppred io.out_uop.iw_p1_poisoned := p1_poisoned io.out_uop.iw_p2_poisoned := p2_poisoned when (state === s_valid_2) { when (p1 && p2 && ppred) { ; // send out the entire instruction as one uop } .elsewhen (p1 && ppred) { io.uop.uopc := slot_uop.uopc io.uop.lrs2_rtype := RT_X } .elsewhen (p2 && ppred) { io.uop.uopc := uopSTD io.uop.lrs1_rtype := RT_X } } // debug outputs io.debug.p1 := p1 io.debug.p2 := p2 io.debug.p3 := p3 io.debug.ppred := ppred io.debug.state := state }	module IssueSlot_15( // @[issue-slot.scala:69:7] input clock, // @[issue-slot.scala:69:7] input reset, // @[issue-slot.scala:69:7] output io_valid, // @[issue-slot.scala:73:14] output io_will_be_valid, // @[issue-slot.scala:73:14] output io_request, // @[issue-slot.scala:73:14] output io_request_hp, // @[issue-slot.scala:73:14] input io_grant, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14] input io_brupdate_b2_valid, // @[issue-slot.scala:73:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14] input io_brupdate_b2_taken, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14] input io_kill, // @[issue-slot.scala:73:14] input io_clear, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14] input io_in_uop_valid, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14] input io_in_uop_bits_taken, // @[issue-slot.scala:73:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14] input io_in_uop_bits_exception, // @[issue-slot.scala:73:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14] input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14] output io_out_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14] output io_out_uop_is_br, // @[issue-slot.scala:73:14] output io_out_uop_is_jalr, // @[issue-slot.scala:73:14] output io_out_uop_is_jal, // @[issue-slot.scala:73:14] output io_out_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_out_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14] output io_out_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:73:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_out_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14] output io_out_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14] output io_out_uop_mem_signed, // @[issue-slot.scala:73:14] output io_out_uop_is_fence, // @[issue-slot.scala:73:14] output io_out_uop_is_fencei, // @[issue-slot.scala:73:14] output io_out_uop_is_amo, // @[issue-slot.scala:73:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_out_uop_uses_stq, // @[issue-slot.scala:73:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_out_uop_is_unique, // @[issue-slot.scala:73:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14] output io_out_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_out_uop_frs3_en, // @[issue-slot.scala:73:14] output io_out_uop_fp_val, // @[issue-slot.scala:73:14] output io_out_uop_fp_single, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14] output io_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14] output io_uop_is_br, // @[issue-slot.scala:73:14] output io_uop_is_jalr, // @[issue-slot.scala:73:14] output io_uop_is_jal, // @[issue-slot.scala:73:14] output io_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14] output io_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_uop_ppred, // @[issue-slot.scala:73:14] output io_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14] output io_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14] output io_uop_mem_signed, // @[issue-slot.scala:73:14] output io_uop_is_fence, // @[issue-slot.scala:73:14] output io_uop_is_fencei, // @[issue-slot.scala:73:14] output io_uop_is_amo, // @[issue-slot.scala:73:14] output io_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_uop_uses_stq, // @[issue-slot.scala:73:14] output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_uop_is_unique, // @[issue-slot.scala:73:14] output io_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14] output io_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_uop_frs3_en, // @[issue-slot.scala:73:14] output io_uop_fp_val, // @[issue-slot.scala:73:14] output io_uop_fp_single, // @[issue-slot.scala:73:14] output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14] output io_debug_p1, // @[issue-slot.scala:73:14] output io_debug_p2, // @[issue-slot.scala:73:14] output io_debug_p3, // @[issue-slot.scala:73:14] output io_debug_ppred, // @[issue-slot.scala:73:14] output [1:0] io_debug_state // @[issue-slot.scala:73:14] ); wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7] wire io_ldspec_miss = 1'h0; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_bits_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_bits_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7] wire io_spec_ld_wakeup_0_valid = 1'h0; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_uop_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_uop_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire next_p1_poisoned = 1'h0; // @[issue-slot.scala:99:29] wire next_p2_poisoned = 1'h0; // @[issue-slot.scala:100:29] wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire _squash_grant_T = 1'h0; // @[issue-slot.scala:261:53] wire squash_grant = 1'h0; // @[issue-slot.scala:261:37] wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:69:7] wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [6:0] io_spec_ld_wakeup_0_bits = 7'h0; // @[issue-slot.scala:69:7] wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19] wire _io_will_be_valid_T_1 = 1'h1; // @[issue-slot.scala:262:51] wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [15:0] slot_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19] wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire _io_valid_T; // @[issue-slot.scala:79:24] wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32] wire _io_request_hp_T; // @[issue-slot.scala:243:31] wire [6:0] next_uopc; // @[issue-slot.scala:82:29] wire [1:0] next_state; // @[issue-slot.scala:81:29] wire [15:0] next_br_mask; // @[util.scala:85:25] wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28] wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28] wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28] wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28] wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29] wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29] wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_out_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_out_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire io_debug_p1_0; // @[issue-slot.scala:69:7] wire io_debug_p2_0; // @[issue-slot.scala:69:7] wire io_debug_p3_0; // @[issue-slot.scala:69:7] wire io_debug_ppred_0; // @[issue-slot.scala:69:7] wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7] wire io_valid_0; // @[issue-slot.scala:69:7] wire io_will_be_valid_0; // @[issue-slot.scala:69:7] wire io_request_0; // @[issue-slot.scala:69:7] wire io_request_hp_0; // @[issue-slot.scala:69:7] assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29] assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29] assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29] assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29] reg [1:0] state; // @[issue-slot.scala:86:22] assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22] reg p1; // @[issue-slot.scala:87:22] assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22] wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25] reg p2; // @[issue-slot.scala:88:22] assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22] wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25] reg p3; // @[issue-slot.scala:89:22] assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22] wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25] reg ppred; // @[issue-slot.scala:90:22] assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22] wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28] reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25] reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25] assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25] assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_rvc; // @[issue-slot.scala:102:25] assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25] assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25] assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25] assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_is_br; // @[issue-slot.scala:102:25] assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jalr; // @[issue-slot.scala:102:25] assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jal; // @[issue-slot.scala:102:25] assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sfb; // @[issue-slot.scala:102:25] assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:102:25] assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:102:25] assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_edge_inst; // @[issue-slot.scala:102:25] assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25] assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_taken; // @[issue-slot.scala:102:25] assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25] assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25] assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:102:25] assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:102:25] assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:102:25] assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:102:25] assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25] assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25] assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25] assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25] assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_exception; // @[issue-slot.scala:102:25] assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25] assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bypassable; // @[issue-slot.scala:102:25] assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25] assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_mem_signed; // @[issue-slot.scala:102:25] assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fence; // @[issue-slot.scala:102:25] assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fencei; // @[issue-slot.scala:102:25] assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_amo; // @[issue-slot.scala:102:25] assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_stq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25] assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_unique; // @[issue-slot.scala:102:25] assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25] assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25] assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25] assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25] assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_val; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25] assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25] reg slot_uop_frs3_en; // @[issue-slot.scala:102:25] assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_val; // @[issue-slot.scala:102:25] assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_single; // @[issue-slot.scala:102:25] assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p1_poisoned = ~io_in_uop_valid_0 & slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p2_poisoned = ~io_in_uop_valid_0 & slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [15:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25] wire _T_7 = io_grant_0 & state == 2'h1 \| io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}] wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25] wire _GEN = io_kill_0 \| _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51] wire _GEN_0 = _GEN \| ~(_T_12 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:62, :142:17, :143:23] assign next_uopc = _GEN_0 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51] assign next_lrs1_rtype = _GEN_0 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51] wire _GEN_1 = _GEN \| ~_T_12 \| p1; // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:62, :142:17] assign next_lrs2_rtype = _GEN_1 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17]
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" / black /, label = (ei.manager.beatBytes 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red /, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" / green /) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" / yellow /, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File BusBypass.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.devices.tilelink import chisel3._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ abstract class TLBusBypassBase(beatBytes: Int, deadlock: Boolean = false, bufferError: Boolean = true, maxAtomic: Int = 16, maxTransfer: Int = 4096) (implicit p: Parameters) extends LazyModule { protected val nodeIn = TLIdentityNode() protected val nodeOut = TLIdentityNode() val node = NodeHandle(nodeIn, nodeOut) protected val bar = LazyModule(new TLBusBypassBar(dFn = { mp => mp.v1copy(managers = mp.managers.map { m => m.v1copy( mayDenyPut = m.mayDenyPut \|\| !deadlock, mayDenyGet = m.mayDenyGet \|\| !deadlock) }) })) protected val everything = Seq(AddressSet(0, BigInt("ffffffffffffffffffffffffffffffff", 16))) // 128-bit protected val params = DevNullParams(everything, maxAtomic, maxTransfer, region=RegionType.TRACKED) protected val error = if (deadlock) LazyModule(new TLDeadlock(params, beatBytes)) else LazyModule(new TLError(params, bufferError, beatBytes)) // order matters because the parameters and bypass // assume that the non-bypassed connection is // the last connection to the bar, so keep nodeOut last. bar.node := nodeIn error.node := bar.node nodeOut := bar.node } class TLBusBypass(beatBytes: Int, bufferError: Boolean = false, maxAtomic: Int = 16, maxTransfer: Int = 4096)(implicit p: Parameters) extends TLBusBypassBase(beatBytes, deadlock = false, bufferError = bufferError, maxAtomic = maxAtomic, maxTransfer = maxTransfer) { lazy val module = new Impl class Impl extends LazyModuleImp(this) { val io = IO(new Bundle { val bypass = Input(Bool()) }) bar.module.io.bypass := io.bypass } } class TLBypassNode(dFn: TLSlavePortParameters => TLSlavePortParameters)(implicit valName: ValName) extends TLCustomNode { def resolveStar(iKnown: Int, oKnown: Int, iStars: Int, oStars: Int): (Int, Int) = { require (iStars == 0 && oStars == 0, "TLBypass node does not support := or :=") require (iKnown == 1, "TLBypass node expects exactly one input") require (oKnown == 2, "TLBypass node expects exactly two outputs") (0, 0) } def mapParamsD(n: Int, p: Seq[TLMasterPortParameters]): Seq[TLMasterPortParameters] = { p ++ p } def mapParamsU(n: Int, p: Seq[TLSlavePortParameters]): Seq[TLSlavePortParameters] = { Seq(dFn(p.last).v1copy(minLatency = p.map(_.minLatency).min))} } class TLBusBypassBar(dFn: TLSlavePortParameters => TLSlavePortParameters)(implicit p: Parameters) extends LazyModule { val node = new TLBypassNode(dFn) lazy val module = new Impl class Impl extends LazyModuleImp(this) { val io = IO(new Bundle { val bypass = Input(Bool()) val pending = Output(Bool()) }) val (in, edgeIn) = node.in(0) val Seq((out0, edgeOut0), (out1, edgeOut1)) = node.out require (edgeOut0.manager.beatBytes == edgeOut1.manager.beatBytes, s"BusBypass slave device widths mismatch (${edgeOut0.manager.managers.map(_.name)} has ${edgeOut0.manager.beatBytes}B vs ${edgeOut1.manager.managers.map(_.name)} has ${edgeOut1.manager.beatBytes}B)") // We need to be locked to the given bypass direction until all transactions stop val in_reset = RegNext(false.B, init = true.B) val bypass_reg = Reg(Bool()) val bypass = Mux(in_reset, io.bypass, bypass_reg) val (flight, next_flight) = edgeIn.inFlight(in) io.pending := (flight > 0.U) when (in_reset \|\| (next_flight === 0.U)) { bypass_reg := io.bypass } val stall = (bypass =/= io.bypass) && edgeIn.first(in.a) out0.a.valid := !stall && in.a.valid && bypass out1.a.valid := !stall && in.a.valid && !bypass in.a.ready := !stall && Mux(bypass, out0.a.ready, out1.a.ready) out0.a.bits := in.a.bits out1.a.bits := in.a.bits out0.d.ready := in.d.ready && bypass out1.d.ready := in.d.ready && !bypass in.d.valid := Mux(bypass, out0.d.valid, out1.d.valid) def cast(x: TLBundleD) = { val out = WireDefault(in.d.bits); out <> x; out } in.d.bits := Mux(bypass, cast(out0.d.bits), cast(out1.d.bits)) if (edgeIn.manager.anySupportAcquireB && edgeIn.client.anySupportProbe) { out0.b.ready := in.b.ready && bypass out1.b.ready := in.b.ready && !bypass in.b.valid := Mux(bypass, out0.b.valid, out1.b.valid) def cast(x: TLBundleB) = { val out = Wire(in.b.bits); out <> x; out } in.b.bits := Mux(bypass, cast(out0.b.bits), cast(out1.b.bits)) out0.c.valid := in.c.valid && bypass out1.c.valid := in.c.valid && !bypass in.c.ready := Mux(bypass, out0.c.ready, out1.c.ready) out0.c.bits := in.c.bits out1.c.bits := in.c.bits out0.e.valid := in.e.valid && bypass out1.e.valid := in.e.valid && !bypass in.e.ready := Mux(bypass, out0.e.ready, out1.e.ready) out0.e.bits := in.e.bits out1.e.bits := in.e.bits } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out0.b.ready := true.B out0.c.valid := false.B out0.e.valid := false.B out1.b.ready := true.B out1.c.valid := false.B out1.e.valid := false.B } } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph / def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLBusBypassBar( // @[BusBypass.scala:66:9] input clock, // @[BusBypass.scala:66:9] input reset, // @[BusBypass.scala:66:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [8:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [31:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_1_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_1_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [8:0] auto_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_1_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_1_d_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [31:0] auto_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_0_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_0_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [127:0] auto_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_0_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_0_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_0_d_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25] input auto_out_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] input auto_out_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input io_bypass // @[BusBypass.scala:67:16] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[BusBypass.scala:66:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[BusBypass.scala:66:9] wire [8:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[BusBypass.scala:66:9] wire [31:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[BusBypass.scala:66:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[BusBypass.scala:66:9] wire auto_out_1_a_ready_0 = auto_out_1_a_ready; // @[BusBypass.scala:66:9] wire auto_out_1_d_valid_0 = auto_out_1_d_valid; // @[BusBypass.scala:66:9] wire [2:0] auto_out_1_d_bits_opcode_0 = auto_out_1_d_bits_opcode; // @[BusBypass.scala:66:9] wire [1:0] auto_out_1_d_bits_param_0 = auto_out_1_d_bits_param; // @[BusBypass.scala:66:9] wire [1:0] auto_out_1_d_bits_size_0 = auto_out_1_d_bits_size; // @[BusBypass.scala:66:9] wire auto_out_1_d_bits_source_0 = auto_out_1_d_bits_source; // @[BusBypass.scala:66:9] wire auto_out_1_d_bits_sink_0 = auto_out_1_d_bits_sink; // @[BusBypass.scala:66:9] wire auto_out_1_d_bits_denied_0 = auto_out_1_d_bits_denied; // @[BusBypass.scala:66:9] wire [31:0] auto_out_1_d_bits_data_0 = auto_out_1_d_bits_data; // @[BusBypass.scala:66:9] wire auto_out_1_d_bits_corrupt_0 = auto_out_1_d_bits_corrupt; // @[BusBypass.scala:66:9] wire auto_out_0_a_ready_0 = auto_out_0_a_ready; // @[BusBypass.scala:66:9] wire auto_out_0_d_valid_0 = auto_out_0_d_valid; // @[BusBypass.scala:66:9] wire [2:0] auto_out_0_d_bits_opcode_0 = auto_out_0_d_bits_opcode; // @[BusBypass.scala:66:9] wire [1:0] auto_out_0_d_bits_param_0 = auto_out_0_d_bits_param; // @[BusBypass.scala:66:9] wire [1:0] auto_out_0_d_bits_size_0 = auto_out_0_d_bits_size; // @[BusBypass.scala:66:9] wire auto_out_0_d_bits_denied_0 = auto_out_0_d_bits_denied; // @[BusBypass.scala:66:9] wire auto_out_0_d_bits_corrupt_0 = auto_out_0_d_bits_corrupt; // @[BusBypass.scala:66:9] wire io_bypass_0 = io_bypass; // @[BusBypass.scala:66:9] wire [4:0] _r_beats1_decode_T_3 = 5'h3; // @[package.scala:243:71] wire [4:0] _r_beats1_decode_T_6 = 5'h3; // @[package.scala:243:71] wire [3:0] _b_inc_WIRE_bits_mask = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _b_inc_WIRE_1_bits_mask = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _b_dec_WIRE_bits_mask = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _b_dec_WIRE_1_bits_mask = 4'h0; // @[Bundles.scala:264:61] wire [8:0] _b_inc_WIRE_bits_address = 9'h0; // @[Bundles.scala:264:74] wire [8:0] _b_inc_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:264:61] wire [8:0] _c_inc_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_inc_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _b_dec_WIRE_bits_address = 9'h0; // @[Bundles.scala:264:74] wire [8:0] _b_dec_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:264:61] wire [8:0] _c_dec_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_dec_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [4:0] _r_beats1_decode_T = 5'hC; // @[package.scala:243:71] wire [4:0] _stall_beats1_decode_T = 5'hC; // @[package.scala:243:71] wire [1:0] _r_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _r_beats1_decode_T_5 = 2'h0; // @[package.scala:243:46] wire [1:0] _r_beats1_decode_T_8 = 2'h0; // @[package.scala:243:46] wire [1:0] _b_inc_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _b_inc_WIRE_bits_size = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _b_inc_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _b_inc_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _c_inc_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_inc_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _b_dec_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _b_dec_WIRE_bits_size = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _b_dec_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _b_dec_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _c_dec_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_dec_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _stall_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76] wire [31:0] auto_out_0_d_bits_data = 32'h0; // @[BusBypass.scala:66:9] wire [31:0] nodeOut_d_bits_data = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] _b_inc_WIRE_bits_data = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _b_inc_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _c_inc_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_inc_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _b_dec_WIRE_bits_data = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _b_dec_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _c_dec_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_dec_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] nodeIn_d_bits_out_data = 32'h0; // @[BusBypass.scala:97:53] wire [3:0] auto_in_a_bits_mask = 4'hF; // @[Nodes.scala:27:25] wire [3:0] auto_out_1_a_bits_mask = 4'hF; // @[Nodes.scala:27:25] wire [3:0] auto_out_0_a_bits_mask = 4'hF; // @[Nodes.scala:27:25] wire [3:0] nodeIn_a_bits_mask = 4'hF; // @[Nodes.scala:27:25] wire [3:0] nodeOut_a_bits_mask = 4'hF; // @[Nodes.scala:27:25] wire [3:0] x1_nodeOut_a_bits_mask = 4'hF; // @[Nodes.scala:27:25] wire [1:0] auto_in_a_bits_size = 2'h2; // @[Nodes.scala:27:25] wire [1:0] auto_out_1_a_bits_size = 2'h2; // @[Nodes.scala:27:25] wire [1:0] auto_out_0_a_bits_size = 2'h2; // @[Nodes.scala:27:25] wire [1:0] nodeIn_a_bits_size = 2'h2; // @[Nodes.scala:27:25] wire [1:0] nodeOut_a_bits_size = 2'h2; // @[Nodes.scala:27:25] wire [1:0] x1_nodeOut_a_bits_size = 2'h2; // @[Nodes.scala:27:25] wire [2:0] auto_in_a_bits_param = 3'h0; // @[BusBypass.scala:66:9] wire [2:0] auto_out_1_a_bits_param = 3'h0; // @[BusBypass.scala:66:9] wire [2:0] auto_out_0_a_bits_param = 3'h0; // @[BusBypass.scala:66:9] wire [2:0] nodeIn_a_bits_param = 3'h0; // @[MixedNode.scala:551:17] wire [2:0] nodeOut_a_bits_param = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_a_bits_param = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] _b_inc_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _b_inc_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _c_inc_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_inc_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_inc_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_inc_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _b_dec_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _b_dec_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _c_dec_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_dec_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_dec_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_dec_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [1:0] _r_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46] wire [1:0] _r_beats1_decode_T_4 = 2'h3; // @[package.scala:243:76] wire [1:0] _r_counter1_T_1 = 2'h3; // @[Edges.scala:230:28] wire [1:0] _r_beats1_decode_T_7 = 2'h3; // @[package.scala:243:76] wire [1:0] _r_counter1_T_2 = 2'h3; // @[Edges.scala:230:28] wire [1:0] _r_counter1_T_4 = 2'h3; // @[Edges.scala:230:28] wire [1:0] _stall_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46] wire _r_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_last = 1'h1; // @[Edges.scala:232:33] wire r_beats1_opdata_1 = 1'h1; // @[Edges.scala:97:28] wire r_counter1_1 = 1'h1; // @[Edges.scala:230:28] wire b_first = 1'h1; // @[Edges.scala:231:25] wire _r_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire b_last = 1'h1; // @[Edges.scala:232:33] wire r_counter1_2 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _r_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire c_last = 1'h1; // @[Edges.scala:232:33] wire _r_last_T_7 = 1'h1; // @[Edges.scala:232:43] wire d_last = 1'h1; // @[Edges.scala:232:33] wire r_counter1_4 = 1'h1; // @[Edges.scala:230:28] wire e_first = 1'h1; // @[Edges.scala:231:25] wire _r_last_T_9 = 1'h1; // @[Edges.scala:232:43] wire e_last = 1'h1; // @[Edges.scala:232:33] wire c_response = 1'h1; // @[Edges.scala:82:41] wire _stall_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire stall_last = 1'h1; // @[Edges.scala:232:33] wire auto_in_a_bits_source = 1'h0; // @[BusBypass.scala:66:9] wire auto_in_a_bits_corrupt = 1'h0; // @[BusBypass.scala:66:9] wire auto_out_1_a_bits_source = 1'h0; // @[BusBypass.scala:66:9] wire auto_out_1_a_bits_corrupt = 1'h0; // @[BusBypass.scala:66:9] wire auto_out_0_a_bits_source = 1'h0; // @[BusBypass.scala:66:9] wire auto_out_0_a_bits_corrupt = 1'h0; // @[BusBypass.scala:66:9] wire auto_out_0_d_bits_source = 1'h0; // @[BusBypass.scala:66:9] wire auto_out_0_d_bits_sink = 1'h0; // @[BusBypass.scala:66:9] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire nodeOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_d_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17] wire x1_nodeOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire x1_nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire r_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire r_beats1 = 1'h0; // @[Edges.scala:221:14] wire r_4 = 1'h0; // @[Edges.scala:234:25] wire r_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire _r_beats1_opdata_T_1 = 1'h0; // @[Edges.scala:97:37] wire r_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire _r_last_T_2 = 1'h0; // @[Edges.scala:232:25] wire r_3_1 = 1'h0; // @[Edges.scala:233:22] wire _r_count_T_1 = 1'h0; // @[Edges.scala:234:27] wire r_4_1 = 1'h0; // @[Edges.scala:234:25] wire _r_counter_T_1 = 1'h0; // @[Edges.scala:236:21] wire r_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire r_beats1_opdata_2 = 1'h0; // @[Edges.scala:102:36] wire r_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire _r_last_T_4 = 1'h0; // @[Edges.scala:232:25] wire r_3_2 = 1'h0; // @[Edges.scala:233:22] wire _r_count_T_2 = 1'h0; // @[Edges.scala:234:27] wire r_4_2 = 1'h0; // @[Edges.scala:234:25] wire _r_counter_T_2 = 1'h0; // @[Edges.scala:236:21] wire r_beats1_decode_3 = 1'h0; // @[Edges.scala:220:59] wire r_beats1_3 = 1'h0; // @[Edges.scala:221:14] wire r_4_3 = 1'h0; // @[Edges.scala:234:25] wire _r_last_T_8 = 1'h0; // @[Edges.scala:232:25] wire r_3_4 = 1'h0; // @[Edges.scala:233:22] wire _r_count_T_4 = 1'h0; // @[Edges.scala:234:27] wire r_4_4 = 1'h0; // @[Edges.scala:234:25] wire _r_counter_T_4 = 1'h0; // @[Edges.scala:236:21] wire c_request = 1'h0; // @[Edges.scala:68:40] wire _b_inc_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _b_inc_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _b_inc_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74] wire _b_inc_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _b_inc_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _b_inc_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _b_inc_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:264:61] wire _b_inc_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _b_inc_T = 1'h0; // @[Decoupled.scala:51:35] wire _b_inc_T_1 = 1'h0; // @[Edges.scala:311:26] wire b_inc = 1'h0; // @[Edges.scala:311:37] wire _c_inc_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_inc_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_inc_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_inc_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_inc_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_inc_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_inc_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_inc_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_inc_T = 1'h0; // @[Decoupled.scala:51:35] wire _c_inc_T_1 = 1'h0; // @[Edges.scala:312:26] wire c_inc = 1'h0; // @[Edges.scala:312:37] wire _e_inc_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _e_inc_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _e_inc_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _e_inc_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _e_inc_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _e_inc_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _e_inc_T = 1'h0; // @[Decoupled.scala:51:35] wire _e_inc_T_1 = 1'h0; // @[Edges.scala:314:26] wire e_inc = 1'h0; // @[Edges.scala:314:37] wire a_dec = 1'h0; // @[Edges.scala:317:36] wire _b_dec_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _b_dec_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _b_dec_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74] wire _b_dec_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _b_dec_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _b_dec_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _b_dec_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:264:61] wire _b_dec_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _b_dec_T = 1'h0; // @[Decoupled.scala:51:35] wire _b_dec_T_1 = 1'h0; // @[Edges.scala:318:26] wire b_dec = 1'h0; // @[Edges.scala:318:36] wire _c_dec_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_dec_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_dec_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_dec_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_dec_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_dec_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_dec_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_dec_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_dec_T = 1'h0; // @[Decoupled.scala:51:35] wire _c_dec_T_1 = 1'h0; // @[Edges.scala:319:26] wire c_dec = 1'h0; // @[Edges.scala:319:36] wire _e_dec_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _e_dec_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _e_dec_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _e_dec_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _e_dec_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _e_dec_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _e_dec_T = 1'h0; // @[Decoupled.scala:51:35] wire _e_dec_T_1 = 1'h0; // @[Edges.scala:321:26] wire e_dec = 1'h0; // @[Edges.scala:321:36] wire stall_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire stall_beats1 = 1'h0; // @[Edges.scala:221:14] wire stall_count = 1'h0; // @[Edges.scala:234:25] wire nodeIn_d_bits_out_source = 1'h0; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_sink = 1'h0; // @[BusBypass.scala:97:53] wire nodeIn_a_valid = auto_in_a_valid_0; // @[BusBypass.scala:66:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[BusBypass.scala:66:9] wire [8:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[BusBypass.scala:66:9] wire [31:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[BusBypass.scala:66:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[BusBypass.scala:66:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [31:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire x1_nodeOut_a_ready = auto_out_1_a_ready_0; // @[BusBypass.scala:66:9] wire x1_nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [8:0] x1_nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] x1_nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire x1_nodeOut_d_ready; // @[MixedNode.scala:542:17] wire x1_nodeOut_d_valid = auto_out_1_d_valid_0; // @[BusBypass.scala:66:9] wire [2:0] x1_nodeOut_d_bits_opcode = auto_out_1_d_bits_opcode_0; // @[BusBypass.scala:66:9] wire [1:0] x1_nodeOut_d_bits_param = auto_out_1_d_bits_param_0; // @[BusBypass.scala:66:9] wire [1:0] x1_nodeOut_d_bits_size = auto_out_1_d_bits_size_0; // @[BusBypass.scala:66:9] wire x1_nodeOut_d_bits_source = auto_out_1_d_bits_source_0; // @[BusBypass.scala:66:9] wire x1_nodeOut_d_bits_sink = auto_out_1_d_bits_sink_0; // @[BusBypass.scala:66:9] wire x1_nodeOut_d_bits_denied = auto_out_1_d_bits_denied_0; // @[BusBypass.scala:66:9] wire [31:0] x1_nodeOut_d_bits_data = auto_out_1_d_bits_data_0; // @[BusBypass.scala:66:9] wire x1_nodeOut_d_bits_corrupt = auto_out_1_d_bits_corrupt_0; // @[BusBypass.scala:66:9] wire nodeOut_a_ready = auto_out_0_a_ready_0; // @[BusBypass.scala:66:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [127:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_0_d_valid_0; // @[BusBypass.scala:66:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_0_d_bits_opcode_0; // @[BusBypass.scala:66:9] wire [1:0] nodeOut_d_bits_param = auto_out_0_d_bits_param_0; // @[BusBypass.scala:66:9] wire [1:0] nodeOut_d_bits_size = auto_out_0_d_bits_size_0; // @[BusBypass.scala:66:9] wire nodeOut_d_bits_denied = auto_out_0_d_bits_denied_0; // @[BusBypass.scala:66:9] wire nodeOut_d_bits_corrupt = auto_out_0_d_bits_corrupt_0; // @[BusBypass.scala:66:9] wire _io_pending_T; // @[BusBypass.scala:84:27] wire auto_in_a_ready_0; // @[BusBypass.scala:66:9] wire [2:0] auto_in_d_bits_opcode_0; // @[BusBypass.scala:66:9] wire [1:0] auto_in_d_bits_param_0; // @[BusBypass.scala:66:9] wire [1:0] auto_in_d_bits_size_0; // @[BusBypass.scala:66:9] wire auto_in_d_bits_source_0; // @[BusBypass.scala:66:9] wire auto_in_d_bits_sink_0; // @[BusBypass.scala:66:9] wire auto_in_d_bits_denied_0; // @[BusBypass.scala:66:9] wire [31:0] auto_in_d_bits_data_0; // @[BusBypass.scala:66:9] wire auto_in_d_bits_corrupt_0; // @[BusBypass.scala:66:9] wire auto_in_d_valid_0; // @[BusBypass.scala:66:9] wire [2:0] auto_out_1_a_bits_opcode_0; // @[BusBypass.scala:66:9] wire [8:0] auto_out_1_a_bits_address_0; // @[BusBypass.scala:66:9] wire [31:0] auto_out_1_a_bits_data_0; // @[BusBypass.scala:66:9] wire auto_out_1_a_valid_0; // @[BusBypass.scala:66:9] wire auto_out_1_d_ready_0; // @[BusBypass.scala:66:9] wire [2:0] auto_out_0_a_bits_opcode_0; // @[BusBypass.scala:66:9] wire [127:0] auto_out_0_a_bits_address_0; // @[BusBypass.scala:66:9] wire [31:0] auto_out_0_a_bits_data_0; // @[BusBypass.scala:66:9] wire auto_out_0_a_valid_0; // @[BusBypass.scala:66:9] wire auto_out_0_d_ready_0; // @[BusBypass.scala:66:9] wire io_pending; // @[BusBypass.scala:66:9] wire _nodeIn_a_ready_T_2; // @[BusBypass.scala:90:28] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[BusBypass.scala:66:9] assign nodeOut_a_bits_opcode = nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_nodeOut_a_bits_opcode = nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_nodeOut_a_bits_address = nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_data = nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign x1_nodeOut_a_bits_data = nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] wire _nodeIn_d_valid_T; // @[BusBypass.scala:96:24] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[BusBypass.scala:66:9] wire [2:0] _nodeIn_d_bits_T_opcode; // @[BusBypass.scala:98:21] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[BusBypass.scala:66:9] wire [1:0] _nodeIn_d_bits_T_param; // @[BusBypass.scala:98:21] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[BusBypass.scala:66:9] wire [1:0] _nodeIn_d_bits_T_size; // @[BusBypass.scala:98:21] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[BusBypass.scala:66:9] wire _nodeIn_d_bits_T_source; // @[BusBypass.scala:98:21] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[BusBypass.scala:66:9] wire _nodeIn_d_bits_T_sink; // @[BusBypass.scala:98:21] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[BusBypass.scala:66:9] wire _nodeIn_d_bits_T_denied; // @[BusBypass.scala:98:21] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[BusBypass.scala:66:9] wire [31:0] _nodeIn_d_bits_T_data; // @[BusBypass.scala:98:21] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[BusBypass.scala:66:9] wire _nodeIn_d_bits_T_corrupt; // @[BusBypass.scala:98:21] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[BusBypass.scala:66:9] wire _nodeOut_a_valid_T_2; // @[BusBypass.scala:88:42] assign auto_out_0_a_valid_0 = nodeOut_a_valid; // @[BusBypass.scala:66:9] assign auto_out_0_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[BusBypass.scala:66:9] assign auto_out_0_a_bits_address_0 = nodeOut_a_bits_address; // @[BusBypass.scala:66:9] assign auto_out_0_a_bits_data_0 = nodeOut_a_bits_data; // @[BusBypass.scala:66:9] wire _nodeOut_d_ready_T; // @[BusBypass.scala:94:32] assign auto_out_0_d_ready_0 = nodeOut_d_ready; // @[BusBypass.scala:66:9] wire [2:0] nodeIn_d_bits_out_opcode = nodeOut_d_bits_opcode; // @[BusBypass.scala:97:53] wire [1:0] nodeIn_d_bits_out_param = nodeOut_d_bits_param; // @[BusBypass.scala:97:53] wire [1:0] nodeIn_d_bits_out_size = nodeOut_d_bits_size; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_denied = nodeOut_d_bits_denied; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_corrupt = nodeOut_d_bits_corrupt; // @[BusBypass.scala:97:53] wire _nodeOut_a_valid_T_6; // @[BusBypass.scala:89:42] assign auto_out_1_a_valid_0 = x1_nodeOut_a_valid; // @[BusBypass.scala:66:9] assign auto_out_1_a_bits_opcode_0 = x1_nodeOut_a_bits_opcode; // @[BusBypass.scala:66:9] assign auto_out_1_a_bits_address_0 = x1_nodeOut_a_bits_address; // @[BusBypass.scala:66:9] assign auto_out_1_a_bits_data_0 = x1_nodeOut_a_bits_data; // @[BusBypass.scala:66:9] wire _nodeOut_d_ready_T_2; // @[BusBypass.scala:95:32] assign auto_out_1_d_ready_0 = x1_nodeOut_d_ready; // @[BusBypass.scala:66:9] wire [2:0] nodeIn_d_bits_out_1_opcode = x1_nodeOut_d_bits_opcode; // @[BusBypass.scala:97:53] wire [1:0] nodeIn_d_bits_out_1_param = x1_nodeOut_d_bits_param; // @[BusBypass.scala:97:53] wire [1:0] nodeIn_d_bits_out_1_size = x1_nodeOut_d_bits_size; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_1_source = x1_nodeOut_d_bits_source; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_1_sink = x1_nodeOut_d_bits_sink; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_1_denied = x1_nodeOut_d_bits_denied; // @[BusBypass.scala:97:53] wire [31:0] nodeIn_d_bits_out_1_data = x1_nodeOut_d_bits_data; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_1_corrupt = x1_nodeOut_d_bits_corrupt; // @[BusBypass.scala:97:53] reg in_reset; // @[BusBypass.scala:79:27] reg bypass_reg; // @[BusBypass.scala:80:25] wire bypass = in_reset ? io_bypass_0 : bypass_reg; // @[BusBypass.scala:66:9, :79:27, :80:25, :81:21] reg [1:0] flight; // @[Edges.scala:295:25] wire _T = nodeIn_a_ready & nodeIn_a_valid; // @[Decoupled.scala:51:35] wire r_3; // @[Edges.scala:233:22] assign r_3 = _T; // @[Decoupled.scala:51:35] wire _a_inc_T; // @[Decoupled.scala:51:35] assign _a_inc_T = _T; // @[Decoupled.scala:51:35] wire _a_dec_T; // @[Decoupled.scala:51:35] assign _a_dec_T = _T; // @[Decoupled.scala:51:35] wire _stall_T_1; // @[Decoupled.scala:51:35] assign _stall_T_1 = _T; // @[Decoupled.scala:51:35] wire _r_beats1_opdata_T = nodeIn_a_bits_opcode[2]; // @[Edges.scala:92:37] wire _stall_beats1_opdata_T = nodeIn_a_bits_opcode[2]; // @[Edges.scala:92:37] wire r_beats1_opdata = ~_r_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg r_counter; // @[Edges.scala:229:27] wire _r_last_T = r_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _r_counter1_T = {1'h0, r_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire r_counter1 = _r_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~r_counter; // @[Edges.scala:229:27, :231:25] wire _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27] wire _r_counter_T = ~a_first & r_counter1; // @[Edges.scala:230:28, :231:25, :236:21] wire _T_3 = nodeIn_d_ready & nodeIn_d_valid; // @[Decoupled.scala:51:35] wire r_3_3; // @[Edges.scala:233:22] assign r_3_3 = _T_3; // @[Decoupled.scala:51:35] wire _d_inc_T; // @[Decoupled.scala:51:35] assign _d_inc_T = _T_3; // @[Decoupled.scala:51:35] wire _d_dec_T; // @[Decoupled.scala:51:35] assign _d_dec_T = _T_3; // @[Decoupled.scala:51:35] wire [4:0] _r_beats1_decode_T_9 = 5'h3 << nodeIn_d_bits_size; // @[package.scala:243:71] wire [1:0] _r_beats1_decode_T_10 = _r_beats1_decode_T_9[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _r_beats1_decode_T_11 = ~_r_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire r_beats1_opdata_3 = nodeIn_d_bits_opcode[0]; // @[Edges.scala:106:36] reg r_counter_3; // @[Edges.scala:229:27] wire _r_last_T_6 = r_counter_3; // @[Edges.scala:229:27, :232:25] wire [1:0] _r_counter1_T_3 = {1'h0, r_counter_3} - 2'h1; // @[Edges.scala:229:27, :230:28] wire r_counter1_3 = _r_counter1_T_3[0]; // @[Edges.scala:230:28] wire d_first = ~r_counter_3; // @[Edges.scala:229:27, :231:25] wire _r_count_T_3 = ~r_counter1_3; // @[Edges.scala:230:28, :234:27] wire _r_counter_T_3 = ~d_first & r_counter1_3; // @[Edges.scala:230:28, :231:25, :236:21] wire d_request = nodeIn_d_bits_opcode[2] & ~(nodeIn_d_bits_opcode[1]); // @[Edges.scala:71:{36,40,43,52}] wire _a_inc_T_1 = _a_inc_T & a_first; // @[Decoupled.scala:51:35] wire a_inc = _a_inc_T_1; // @[Edges.scala:310:{26,37}] wire _d_inc_T_1 = _d_inc_T & d_first; // @[Decoupled.scala:51:35] wire d_inc = _d_inc_T_1 & d_request; // @[Edges.scala:71:40, :313:{26,37}] wire [1:0] inc = {a_inc, d_inc}; // @[Edges.scala:310:37, :313:37, :315:18] wire _a_dec_T_1 = _a_dec_T; // @[Decoupled.scala:51:35] wire _d_dec_T_1 = _d_dec_T; // @[Decoupled.scala:51:35] wire d_dec = _d_dec_T_1; // @[Edges.scala:320:{26,36}] wire [1:0] dec = {1'h0, d_dec}; // @[Edges.scala:320:36, :322:18] wire _next_flight_T = inc[0]; // @[Edges.scala:315:18, :324:40] wire _next_flight_T_1 = inc[1]; // @[Edges.scala:315:18, :324:40] wire [1:0] _next_flight_T_2 = {1'h0, _next_flight_T} + {1'h0, _next_flight_T_1}; // @[Edges.scala:324:40] wire [1:0] _next_flight_T_3 = _next_flight_T_2; // @[Edges.scala:324:40] wire [2:0] _next_flight_T_4 = {1'h0, flight} + {1'h0, _next_flight_T_3}; // @[Edges.scala:295:25, :324:{30,40}] wire [1:0] _next_flight_T_5 = _next_flight_T_4[1:0]; // @[Edges.scala:324:30] wire _next_flight_T_6 = dec[0]; // @[Edges.scala:322:18, :324:56] wire _next_flight_T_7 = dec[1]; // @[Edges.scala:322:18, :324:56] wire [1:0] _next_flight_T_8 = {1'h0, _next_flight_T_6} + {1'h0, _next_flight_T_7}; // @[Edges.scala:324:56] wire [1:0] _next_flight_T_9 = _next_flight_T_8; // @[Edges.scala:324:56] wire [2:0] _next_flight_T_10 = {1'h0, _next_flight_T_5} - {1'h0, _next_flight_T_9}; // @[Edges.scala:324:{30,46,56}] wire [1:0] next_flight = _next_flight_T_10[1:0]; // @[Edges.scala:324:46] assign _io_pending_T = \|flight; // @[Edges.scala:295:25] assign io_pending = _io_pending_T; // @[BusBypass.scala:66:9, :84:27] wire _stall_T = bypass != io_bypass_0; // @[BusBypass.scala:66:9, :81:21, :86:25] wire stall_done = _stall_T_1; // @[Decoupled.scala:51:35] wire stall_beats1_opdata = ~_stall_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg stall_counter; // @[Edges.scala:229:27] wire _stall_last_T = stall_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _stall_counter1_T = {1'h0, stall_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire stall_counter1 = _stall_counter1_T[0]; // @[Edges.scala:230:28] wire stall_first = ~stall_counter; // @[Edges.scala:229:27, :231:25] wire _stall_count_T = ~stall_counter1; // @[Edges.scala:230:28, :234:27] wire _stall_counter_T = ~stall_first & stall_counter1; // @[Edges.scala:230:28, :231:25, :236:21] wire stall = _stall_T & stall_first; // @[Edges.scala:231:25] wire _nodeOut_a_valid_T = ~stall; // @[BusBypass.scala:86:40, :88:21] wire _nodeOut_a_valid_T_1 = _nodeOut_a_valid_T & nodeIn_a_valid; // @[BusBypass.scala:88:{21,28}] assign _nodeOut_a_valid_T_2 = _nodeOut_a_valid_T_1 & bypass; // @[BusBypass.scala:81:21, :88:{28,42}] assign nodeOut_a_valid = _nodeOut_a_valid_T_2; // @[BusBypass.scala:88:42] wire _nodeOut_a_valid_T_3 = ~stall; // @[BusBypass.scala:86:40, :88:21, :89:21] wire _nodeOut_a_valid_T_4 = _nodeOut_a_valid_T_3 & nodeIn_a_valid; // @[BusBypass.scala:89:{21,28}] wire _nodeOut_a_valid_T_5 = ~bypass; // @[BusBypass.scala:81:21, :89:45] assign _nodeOut_a_valid_T_6 = _nodeOut_a_valid_T_4 & _nodeOut_a_valid_T_5; // @[BusBypass.scala:89:{28,42,45}] assign x1_nodeOut_a_valid = _nodeOut_a_valid_T_6; // @[BusBypass.scala:89:42] wire _nodeIn_a_ready_T = ~stall; // @[BusBypass.scala:86:40, :88:21, :90:21] wire _nodeIn_a_ready_T_1 = bypass ? nodeOut_a_ready : x1_nodeOut_a_ready; // @[BusBypass.scala:81:21, :90:34] assign _nodeIn_a_ready_T_2 = _nodeIn_a_ready_T & _nodeIn_a_ready_T_1; // @[BusBypass.scala:90:{21,28,34}] assign nodeIn_a_ready = _nodeIn_a_ready_T_2; // @[BusBypass.scala:90:28] assign nodeOut_a_bits_address = {119'h0, nodeIn_a_bits_address}; // @[BusBypass.scala:91:18] assign _nodeOut_d_ready_T = nodeIn_d_ready & bypass; // @[BusBypass.scala:81:21, :94:32] assign nodeOut_d_ready = _nodeOut_d_ready_T; // @[BusBypass.scala:94:32] wire _nodeOut_d_ready_T_1 = ~bypass; // @[BusBypass.scala:81:21, :89:45, :95:35] assign _nodeOut_d_ready_T_2 = nodeIn_d_ready & _nodeOut_d_ready_T_1; // @[BusBypass.scala:95:{32,35}] assign x1_nodeOut_d_ready = _nodeOut_d_ready_T_2; // @[BusBypass.scala:95:32] assign _nodeIn_d_valid_T = bypass ? nodeOut_d_valid : x1_nodeOut_d_valid; // @[BusBypass.scala:81:21, :96:24] assign nodeIn_d_valid = _nodeIn_d_valid_T; // @[BusBypass.scala:96:24] assign _nodeIn_d_bits_T_opcode = bypass ? nodeIn_d_bits_out_opcode : nodeIn_d_bits_out_1_opcode; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_param = bypass ? nodeIn_d_bits_out_param : nodeIn_d_bits_out_1_param; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_size = bypass ? nodeIn_d_bits_out_size : nodeIn_d_bits_out_1_size; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_source = ~bypass & nodeIn_d_bits_out_1_source; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_sink = ~bypass & nodeIn_d_bits_out_1_sink; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_denied = bypass ? nodeIn_d_bits_out_denied : nodeIn_d_bits_out_1_denied; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_data = bypass ? 32'h0 : nodeIn_d_bits_out_1_data; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_corrupt = bypass ? nodeIn_d_bits_out_corrupt : nodeIn_d_bits_out_1_corrupt; // @[BusBypass.scala:81:21, :97:53, :98:21] assign nodeIn_d_bits_opcode = _nodeIn_d_bits_T_opcode; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_param = _nodeIn_d_bits_T_param; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_size = _nodeIn_d_bits_T_size; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_source = _nodeIn_d_bits_T_source; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_sink = _nodeIn_d_bits_T_sink; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_denied = _nodeIn_d_bits_T_denied; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_data = _nodeIn_d_bits_T_data; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_corrupt = _nodeIn_d_bits_T_corrupt; // @[BusBypass.scala:98:21] always @(posedge clock) begin // @[BusBypass.scala:66:9] if (reset) begin // @[BusBypass.scala:66:9] in_reset <= 1'h1; // @[BusBypass.scala:79:27] flight <= 2'h0; // @[Edges.scala:295:25] r_counter <= 1'h0; // @[Edges.scala:229:27] r_counter_3 <= 1'h0; // @[Edges.scala:229:27] stall_counter <= 1'h0; // @[Edges.scala:229:27] end else begin // @[BusBypass.scala:66:9] in_reset <= 1'h0; // @[BusBypass.scala:79:27] flight <= next_flight; // @[Edges.scala:295:25, :324:46] if (_T) // @[Decoupled.scala:51:35] r_counter <= _r_counter_T; // @[Edges.scala:229:27, :236:21] if (_T_3) // @[Decoupled.scala:51:35] r_counter_3 <= _r_counter_T_3; // @[Edges.scala:229:27, :236:21] if (_stall_T_1) // @[Decoupled.scala:51:35] stall_counter <= _stall_counter_T; // @[Edges.scala:229:27, :236:21] end if (in_reset \| next_flight == 2'h0) // @[Edges.scala:324:46] bypass_reg <= io_bypass_0; // @[BusBypass.scala:66:9, :80:25] always @(posedge) TLMonitor_51 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] assign auto_in_a_ready = auto_in_a_ready_0; // @[BusBypass.scala:66:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[BusBypass.scala:66:9] assign auto_out_1_a_valid = auto_out_1_a_valid_0; // @[BusBypass.scala:66:9] assign auto_out_1_a_bits_opcode = auto_out_1_a_bits_opcode_0; // @[BusBypass.scala:66:9] assign auto_out_1_a_bits_address = auto_out_1_a_bits_address_0; // @[BusBypass.scala:66:9] assign auto_out_1_a_bits_data = auto_out_1_a_bits_data_0; // @[BusBypass.scala:66:9] assign auto_out_1_d_ready = auto_out_1_d_ready_0; // @[BusBypass.scala:66:9] assign auto_out_0_a_valid = auto_out_0_a_valid_0; // @[BusBypass.scala:66:9] assign auto_out_0_a_bits_opcode = auto_out_0_a_bits_opcode_0; // @[BusBypass.scala:66:9] assign auto_out_0_a_bits_address = auto_out_0_a_bits_address_0; // @[BusBypass.scala:66:9] assign auto_out_0_a_bits_data = auto_out_0_a_bits_data_0; // @[BusBypass.scala:66:9] assign auto_out_0_d_ready = auto_out_0_d_ready_0; // @[BusBypass.scala:66:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands / class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B \|\| ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B \|\| ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def (t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def (t: UInt) = self t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros \| ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def (t: SInt) = self t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros \| ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid \|\| output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid \|\| output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid \|\| output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def (t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def (t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }	module PE_294( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid, // @[PE.scala:35:14] output io_bad_dataflow // @[PE.scala:35:14] ); wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24] wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [31:0] c1; // @[PE.scala:70:15] wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [31:0] c2; // @[PE.scala:71:15] wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = \|_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25] wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros \| io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = \|_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 \| io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61] wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38] wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38] assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16] assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10] wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10] c1 <= _GEN_7; // @[PE.scala:70:15, :124:10] if (~io_in_control_dataflow_0 \| io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30] end else // @[PE.scala:71:15, :118:101, :119:30] c2 <= _GEN_7; // @[PE.scala:71:15, :124:10] end else begin // @[PE.scala:31:7] c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10] c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10] end last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] end always @(posedge) MacUnit_38 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24] .io_out_d (_mac_unit_io_out_d) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File DescribedSRAM.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3.{Data, SyncReadMem, Vec} import chisel3.util.log2Ceil object DescribedSRAM { def apply[T <: Data]( name: String, desc: String, size: BigInt, // depth data: T ): SyncReadMem[T] = { val mem = SyncReadMem(size, data) mem.suggestName(name) val granWidth = data match { case v: Vec[_] => v.head.getWidth case d => d.getWidth } val uid = 0 Annotated.srams( component = mem, name = name, address_width = log2Ceil(size), data_width = data.getWidth, depth = size, description = desc, write_mask_granularity = granWidth ) mem } }	module rerocc_tile_dcache_tag_array_2( // @[DescribedSRAM.scala:17:26] input [1:0] RW0_addr, input RW0_en, input RW0_clk, input RW0_wmode, input [103:0] RW0_wdata, output [103:0] RW0_rdata, input [3:0] RW0_wmask ); rerocc_tile_dcache_tag_array_ext rerocc_tile_dcache_tag_array_ext ( // @[DescribedSRAM.scala:17:26] .RW0_addr (RW0_addr), .RW0_en (RW0_en), .RW0_clk (RW0_clk), .RW0_wmode (RW0_wmode), .RW0_wdata (RW0_wdata), .RW0_rdata (RW0_rdata), .RW0_wmask (RW0_wmask) ); // @[DescribedSRAM.scala:17:26] endmodule
Generate the Verilog code corresponding to the following Chisel files. File AsyncResetReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ /** This black-boxes an Async Reset * (or Set) * Register. * * Because Chisel doesn't support * parameterized black boxes, * we unfortunately have to * instantiate a number of these. * * We also have to hard-code the set/ * reset behavior. * * Do not confuse an asynchronous * reset signal with an asynchronously * reset reg. You should still * properly synchronize your reset * deassertion. * * @param d Data input * @param q Data Output * @param clk Clock Input * @param rst Reset Input * @param en Write Enable Input * */ class AsyncResetReg(resetValue: Int = 0) extends RawModule { val io = IO(new Bundle { val d = Input(Bool()) val q = Output(Bool()) val en = Input(Bool()) val clk = Input(Clock()) val rst = Input(Reset()) }) val reg = withClockAndReset(io.clk, io.rst.asAsyncReset)(RegInit(resetValue.U(1.W))) when (io.en) { reg := io.d } io.q := reg } class SimpleRegIO(val w: Int) extends Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) } class AsyncResetRegVec(val w: Int, val init: BigInt) extends Module { override def desiredName = s"AsyncResetRegVec_w${w}_i${init}" val io = IO(new SimpleRegIO(w)) val reg = withReset(reset.asAsyncReset)(RegInit(init.U(w.W))) when (io.en) { reg := io.d } io.q := reg } object AsyncResetReg { // Create Single Registers def apply(d: Bool, clk: Clock, rst: Bool, init: Boolean, name: Option[String]): Bool = { val reg = Module(new AsyncResetReg(if (init) 1 else 0)) reg.io.d := d reg.io.clk := clk reg.io.rst := rst reg.io.en := true.B name.foreach(reg.suggestName(_)) reg.io.q } def apply(d: Bool, clk: Clock, rst: Bool): Bool = apply(d, clk, rst, false, None) def apply(d: Bool, clk: Clock, rst: Bool, name: String): Bool = apply(d, clk, rst, false, Some(name)) // Create Vectors of Registers def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: Option[String] = None): UInt = { val w = updateData.getWidth max resetData.bitLength val reg = Module(new AsyncResetRegVec(w, resetData)) name.foreach(reg.suggestName(_)) reg.io.d := updateData reg.io.en := enable reg.io.q } def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: String): UInt = apply(updateData, resetData, enable, Some(name)) def apply(updateData: UInt, resetData: BigInt): UInt = apply(updateData, resetData, enable = true.B) def apply(updateData: UInt, resetData: BigInt, name: String): UInt = apply(updateData, resetData, enable = true.B, Some(name)) def apply(updateData: UInt, enable: Bool): UInt = apply(updateData, resetData=BigInt(0), enable) def apply(updateData: UInt, enable: Bool, name: String): UInt = apply(updateData, resetData = BigInt(0), enable, Some(name)) def apply(updateData: UInt): UInt = apply(updateData, resetData = BigInt(0), enable = true.B) def apply(updateData: UInt, name:String): UInt = apply(updateData, resetData = BigInt(0), enable = true.B, Some(name)) }	module AsyncResetRegVec_w1_i0_24( // @[AsyncResetReg.scala:56:7] input clock, // @[AsyncResetReg.scala:56:7] input reset, // @[AsyncResetReg.scala:56:7] input io_d, // @[AsyncResetReg.scala:59:14] output io_q // @[AsyncResetReg.scala:59:14] ); wire io_d_0 = io_d; // @[AsyncResetReg.scala:56:7] wire _reg_T = reset; // @[AsyncResetReg.scala:61:29] wire io_en = 1'h1; // @[AsyncResetReg.scala:56:7, :59:14] wire io_q_0; // @[AsyncResetReg.scala:56:7] reg reg_0; // @[AsyncResetReg.scala:61:50] assign io_q_0 = reg_0; // @[AsyncResetReg.scala:56:7, :61:50] always @(posedge clock or posedge _reg_T) begin // @[AsyncResetReg.scala:56:7, :61:29] if (_reg_T) // @[AsyncResetReg.scala:56:7, :61:29] reg_0 <= 1'h0; // @[AsyncResetReg.scala:61:50] else // @[AsyncResetReg.scala:56:7] reg_0 <= io_d_0; // @[AsyncResetReg.scala:56:7, :61:50] always @(posedge, posedge)
Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands / class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B \|\| ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B \|\| ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def (t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def (t: UInt) = self t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros \| ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def (t: SInt) = self t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros \| ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid \|\| output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid \|\| output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid \|\| output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def (t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def (t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }	module MacUnit_211( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [19:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54] assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftRegisterPriorityQueue.scala: package compressacc import chisel3._ import chisel3.util._ import chisel3.util._ // TODO : support enq & deq at the same cycle class PriorityQueueStageIO(keyWidth: Int, value: ValueInfo) extends Bundle { val output_prev = KeyValue(keyWidth, value) val output_nxt = KeyValue(keyWidth, value) val input_prev = Flipped(KeyValue(keyWidth, value)) val input_nxt = Flipped(KeyValue(keyWidth, value)) val cmd = Flipped(Valid(UInt(1.W))) val insert_here = Input(Bool()) val cur_input_keyval = Flipped(KeyValue(keyWidth, value)) val cur_output_keyval = KeyValue(keyWidth, value) } class PriorityQueueStage(keyWidth: Int, value: ValueInfo) extends Module { val io = IO(new PriorityQueueStageIO(keyWidth, value)) dontTouch(io) val CMD_DEQ = 0.U val CMD_ENQ = 1.U val MAX_VALUE = (1 << keyWidth) - 1 val key_reg = RegInit(MAX_VALUE.U(keyWidth.W)) val value_reg = Reg(value) io.output_prev.key := key_reg io.output_prev.value := value_reg io.output_nxt.key := key_reg io.output_nxt.value := value_reg io.cur_output_keyval.key := key_reg io.cur_output_keyval.value := value_reg when (io.cmd.valid) { switch (io.cmd.bits) { is (CMD_DEQ) { key_reg := io.input_nxt.key value_reg := io.input_nxt.value } is (CMD_ENQ) { when (io.insert_here) { key_reg := io.cur_input_keyval.key value_reg := io.cur_input_keyval.value } .elsewhen (key_reg >= io.cur_input_keyval.key) { key_reg := io.input_prev.key value_reg := io.input_prev.value } .otherwise { // do nothing } } } } } object PriorityQueueStage { def apply(keyWidth: Int, v: ValueInfo): PriorityQueueStage = new PriorityQueueStage(keyWidth, v) } // TODO // - This design is not scalable as the enqued_keyval is broadcasted to all the stages // - Add pipeline registers later class PriorityQueueIO(queSize: Int, keyWidth: Int, value: ValueInfo) extends Bundle { val cnt_bits = log2Ceil(queSize+1) val counter = Output(UInt(cnt_bits.W)) val enq = Flipped(Decoupled(KeyValue(keyWidth, value))) val deq = Decoupled(KeyValue(keyWidth, value)) } class PriorityQueue(queSize: Int, keyWidth: Int, value: ValueInfo) extends Module { val keyWidthInternal = keyWidth + 1 val CMD_DEQ = 0.U val CMD_ENQ = 1.U val io = IO(new PriorityQueueIO(queSize, keyWidthInternal, value)) dontTouch(io) val MAX_VALUE = ((1 << keyWidthInternal) - 1).U val cnt_bits = log2Ceil(queSize+1) // do not consider cases where we are inserting more entries then the queSize val counter = RegInit(0.U(cnt_bits.W)) io.counter := counter val full = (counter === queSize.U) val empty = (counter === 0.U) io.deq.valid := !empty io.enq.ready := !full when (io.enq.fire) { counter := counter + 1.U } when (io.deq.fire) { counter := counter - 1.U } val cmd_valid = io.enq.valid \|\| io.deq.ready val cmd = Mux(io.enq.valid, CMD_ENQ, CMD_DEQ) assert(!(io.enq.valid && io.deq.ready)) val stages = Seq.fill(queSize)(Module(new PriorityQueueStage(keyWidthInternal, value))) for (i <- 0 until (queSize - 1)) { stages(i+1).io.input_prev <> stages(i).io.output_nxt stages(i).io.input_nxt <> stages(i+1).io.output_prev } stages(queSize-1).io.input_nxt.key := MAX_VALUE // stages(queSize-1).io.input_nxt.value := stages(queSize-1).io.input_nxt.value.symbol := 0.U // stages(queSize-1).io.input_nxt.value.child(0) := 0.U // stages(queSize-1).io.input_nxt.value.child(1) := 0.U stages(0).io.input_prev.key := io.enq.bits.key stages(0).io.input_prev.value <> io.enq.bits.value for (i <- 0 until queSize) { stages(i).io.cmd.valid := cmd_valid stages(i).io.cmd.bits := cmd stages(i).io.cur_input_keyval <> io.enq.bits } val is_large_or_equal = WireInit(VecInit(Seq.fill(queSize)(false.B))) for (i <- 0 until queSize) { is_large_or_equal(i) := (stages(i).io.cur_output_keyval.key >= io.enq.bits.key) } val is_large_or_equal_cat = Wire(UInt(queSize.W)) is_large_or_equal_cat := Cat(is_large_or_equal.reverse) val insert_here_idx = PriorityEncoder(is_large_or_equal_cat) for (i <- 0 until queSize) { when (i.U === insert_here_idx) { stages(i).io.insert_here := true.B } .otherwise { stages(i).io.insert_here := false.B } } io.deq.bits <> stages(0).io.output_prev }	module PriorityQueueStage_83( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File NIC.scala: package icenet import chisel3._ import chisel3.util._ import chisel3.reflect.DataMirror import freechips.rocketchip.subsystem.{BaseSubsystem, TLBusWrapperLocation, PBUS, FBUS} import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.prci._ import freechips.rocketchip.regmapper._ import freechips.rocketchip.interrupts._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import IceNetConsts._ // This is copied from testchipip to avoid dependencies class ClockedIO[T <: Data](private val gen: T) extends Bundle { val clock = Output(Clock()) val bits = DataMirror.internal.chiselTypeClone[T](gen) } /** * @inBufFlits How many flits in the input buffer(s) * @outBufFlits Number of flits in the output buffer * @nMemXacts Maximum number of transactions that the send/receive path can send to memory * @maxAcquireBytes Cache block size * @ctrlQueueDepth Depth of the MMIO control queues * @usePauser Hardware support for Ethernet pause frames * @checksumOffload TCP checksum offload engine * @packetMaxBytes Maximum number of bytes in a packet (header size + MTU) / case class NICConfig( inBufFlits: Int = 2 ETH_STANDARD_MAX_BYTES / NET_IF_BYTES, outBufFlits: Int = 2 * ETH_STANDARD_MAX_BYTES / NET_IF_BYTES, nMemXacts: Int = 8, maxAcquireBytes: Int = 64, ctrlQueueDepth: Int = 10, usePauser: Boolean = false, checksumOffload: Boolean = false, packetMaxBytes: Int = ETH_STANDARD_MAX_BYTES) case class NICAttachParams( masterWhere: TLBusWrapperLocation = FBUS, slaveWhere: TLBusWrapperLocation = PBUS ) case object NICKey extends Field[Option[NICConfig]](None) case object NICAttachKey extends Field[NICAttachParams](NICAttachParams()) trait HasNICParameters { implicit val p: Parameters val nicExternal = p(NICKey).get val inBufFlits = nicExternal.inBufFlits val outBufFlits = nicExternal.outBufFlits val nMemXacts = nicExternal.nMemXacts val maxAcquireBytes = nicExternal.maxAcquireBytes val ctrlQueueDepth = nicExternal.ctrlQueueDepth val usePauser = nicExternal.usePauser val checksumOffload = nicExternal.checksumOffload val packetMaxBytes = nicExternal.packetMaxBytes } abstract class NICLazyModule(implicit p: Parameters) extends LazyModule with HasNICParameters abstract class NICModule(implicit val p: Parameters) extends Module with HasNICParameters abstract class NICBundle(implicit val p: Parameters) extends Bundle with HasNICParameters class PacketArbiter(arbN: Int, rr: Boolean = false) extends HellaPeekingArbiter( new StreamChannel(NET_IF_WIDTH), arbN, (ch: StreamChannel) => ch.last, rr = rr) class IceNicSendIO extends Bundle { val req = Decoupled(UInt(NET_IF_WIDTH.W)) val comp = Flipped(Decoupled(Bool())) } class IceNicRecvIO extends Bundle { val req = Decoupled(UInt(NET_IF_WIDTH.W)) val comp = Flipped(Decoupled(UInt(NET_LEN_BITS.W))) } trait IceNicControllerBundle extends Bundle { val send = new IceNicSendIO val recv = new IceNicRecvIO val macAddr = Input(UInt(ETH_MAC_BITS.W)) val txcsumReq = Decoupled(new ChecksumRewriteRequest) val rxcsumRes = Flipped(Decoupled(new TCPChecksumOffloadResult)) val csumEnable = Output(Bool()) } case class IceNicControllerParams(address: BigInt, beatBytes: Int) /* * Take commands from the CPU over TL2, expose as Queues / class IceNicController(c: IceNicControllerParams)(implicit p: Parameters) extends RegisterRouter(RegisterRouterParams("ice-nic", Seq("ucb-bar,ice-nic"), c.address, beatBytes=c.beatBytes)) with HasTLControlRegMap with HasInterruptSources with HasNICParameters { override def nInterrupts = 2 def tlRegmap(mapping: RegField.Map): Unit = regmap(mapping:_) override lazy val module = new IceNiCControllerModuleImp(this) } class IceNiCControllerModuleImp(outer: IceNicController)(implicit p: Parameters) extends LazyModuleImp(outer) with HasNICParameters { val io = IO(new Bundle with IceNicControllerBundle) val sendCompDown = WireInit(false.B) val qDepth = ctrlQueueDepth require(qDepth < (1 << 8)) def queueCount[T <: Data](qio: QueueIO[T], depth: Int): UInt = TwoWayCounter(qio.enq.fire, qio.deq.fire, depth) // hold (len, addr) of packets that we need to send out val sendReqQueue = Module(new HellaQueue(qDepth)(UInt(NET_IF_WIDTH.W))) val sendReqCount = queueCount(sendReqQueue.io, qDepth) // hold addr of buffers we can write received packets into val recvReqQueue = Module(new HellaQueue(qDepth)(UInt(NET_IF_WIDTH.W))) val recvReqCount = queueCount(recvReqQueue.io, qDepth) // count number of sends completed val sendCompCount = TwoWayCounter(io.send.comp.fire, sendCompDown, qDepth) // hold length of received packets val recvCompQueue = Module(new HellaQueue(qDepth)(UInt(NET_LEN_BITS.W))) val recvCompCount = queueCount(recvCompQueue.io, qDepth) val sendCompValid = sendCompCount > 0.U val intMask = RegInit(0.U(2.W)) io.send.req <> sendReqQueue.io.deq io.recv.req <> recvReqQueue.io.deq io.send.comp.ready := sendCompCount < qDepth.U recvCompQueue.io.enq <> io.recv.comp outer.interrupts(0) := sendCompValid && intMask(0) outer.interrupts(1) := recvCompQueue.io.deq.valid && intMask(1) val sendReqSpace = (qDepth.U - sendReqCount) val recvReqSpace = (qDepth.U - recvReqCount) def sendCompRead = (ready: Bool) => { sendCompDown := sendCompValid && ready (sendCompValid, true.B) } val txcsumReqQueue = Module(new HellaQueue(qDepth)(UInt(49.W))) val rxcsumResQueue = Module(new HellaQueue(qDepth)(UInt(2.W))) val csumEnable = RegInit(false.B) io.txcsumReq.valid := txcsumReqQueue.io.deq.valid io.txcsumReq.bits := txcsumReqQueue.io.deq.bits.asTypeOf(new ChecksumRewriteRequest) txcsumReqQueue.io.deq.ready := io.txcsumReq.ready rxcsumResQueue.io.enq.valid := io.rxcsumRes.valid rxcsumResQueue.io.enq.bits := io.rxcsumRes.bits.asUInt io.rxcsumRes.ready := rxcsumResQueue.io.enq.ready io.csumEnable := csumEnable outer.tlRegmap( 0x00 -> Seq(RegField.w(NET_IF_WIDTH, sendReqQueue.io.enq)), 0x08 -> Seq(RegField.w(NET_IF_WIDTH, recvReqQueue.io.enq)), 0x10 -> Seq(RegField.r(1, sendCompRead)), 0x12 -> Seq(RegField.r(NET_LEN_BITS, recvCompQueue.io.deq)), 0x14 -> Seq( RegField.r(8, sendReqSpace), RegField.r(8, recvReqSpace), RegField.r(8, sendCompCount), RegField.r(8, recvCompCount)), 0x18 -> Seq(RegField.r(ETH_MAC_BITS, io.macAddr)), 0x20 -> Seq(RegField(2, intMask)), 0x28 -> Seq(RegField.w(49, txcsumReqQueue.io.enq)), 0x30 -> Seq(RegField.r(2, rxcsumResQueue.io.deq)), 0x31 -> Seq(RegField(1, csumEnable))) } class IceNicSendPath(nInputTaps: Int = 0)(implicit p: Parameters) extends NICLazyModule { val reader = LazyModule(new StreamReader( nMemXacts, outBufFlits, maxAcquireBytes)) val node = reader.node lazy val module = new Impl class Impl extends LazyModuleImp(this) { val io = IO(new Bundle { val send = Flipped(new IceNicSendIO) val tap = Flipped(Vec(nInputTaps, Decoupled(new StreamChannel(NET_IF_WIDTH)))) val out = Decoupled(new StreamChannel(NET_IF_WIDTH)) val rlimit = Input(new RateLimiterSettings) val csum = checksumOffload.option(new Bundle { val req = Flipped(Decoupled(new ChecksumRewriteRequest)) val enable = Input(Bool()) }) }) val readreq = reader.module.io.req io.send.req.ready := readreq.ready readreq.valid := io.send.req.valid readreq.bits.address := io.send.req.bits(47, 0) readreq.bits.length := io.send.req.bits(62, 48) readreq.bits.partial := io.send.req.bits(63) io.send.comp <> reader.module.io.resp val preArbOut = if (checksumOffload) { val readerOut = reader.module.io.out val arb = Module(new PacketArbiter(2)) val bufFlits = (packetMaxBytes - 1) / NET_IF_BYTES + 1 val rewriter = Module(new ChecksumRewrite(NET_IF_WIDTH, bufFlits)) val enable = io.csum.get.enable rewriter.io.req <> io.csum.get.req arb.io.in(0) <> rewriter.io.stream.out arb.io.in(1).valid := !enable && readerOut.valid arb.io.in(1).bits := readerOut.bits rewriter.io.stream.in.valid := enable && readerOut.valid rewriter.io.stream.in.bits := readerOut.bits readerOut.ready := Mux(enable, rewriter.io.stream.in.ready, arb.io.in(1).ready) arb.io.out } else { reader.module.io.out } val unlimitedOut = if (nInputTaps > 0) { val bufWords = (packetMaxBytes - 1) / NET_IF_BYTES + 1 val inputs = (preArbOut +: io.tap).map { in => // The packet collection buffer doesn't allow sending the first flit // of a packet until the last flit is received. // This ensures that we don't lock the arbiter while waiting for data // to arrive, which could cause deadocks. val buffer = Module(new PacketCollectionBuffer(bufWords)) buffer.io.in <> in buffer.io.out } val arb = Module(new PacketArbiter(inputs.size, rr = true)) arb.io.in <> inputs arb.io.out } else { preArbOut } val limiter = Module(new RateLimiter(new StreamChannel(NET_IF_WIDTH))) limiter.io.in <> unlimitedOut limiter.io.settings := io.rlimit io.out <> limiter.io.out } } class IceNicWriter(implicit p: Parameters) extends NICLazyModule { val writer = LazyModule(new StreamWriter(nMemXacts, maxAcquireBytes)) val node = writer.node lazy val module = new Impl class Impl extends LazyModuleImp(this) { val io = IO(new Bundle { val recv = Flipped(new IceNicRecvIO) val in = Flipped(Decoupled(new StreamChannel(NET_IF_WIDTH))) val length = Flipped(Valid(UInt(NET_LEN_BITS.W))) }) val streaming = RegInit(false.B) val byteAddrBits = log2Ceil(NET_IF_BYTES) val helper = DecoupledHelper( io.recv.req.valid, writer.module.io.req.ready, io.length.valid, !streaming) writer.module.io.req.valid := helper.fire(writer.module.io.req.ready) writer.module.io.req.bits.address := io.recv.req.bits writer.module.io.req.bits.length := io.length.bits io.recv.req.ready := helper.fire(io.recv.req.valid) writer.module.io.in.valid := io.in.valid && streaming writer.module.io.in.bits := io.in.bits io.in.ready := writer.module.io.in.ready && streaming io.recv.comp <> writer.module.io.resp when (io.recv.req.fire) { streaming := true.B } when (io.in.fire && io.in.bits.last) { streaming := false.B } } } / * Recv frames / class IceNicRecvPath(val tapFuncs: Seq[EthernetHeader => Bool] = Nil) (implicit p: Parameters) extends LazyModule { val writer = LazyModule(new IceNicWriter) val node = TLIdentityNode() node := writer.node lazy val module = new IceNicRecvPathModule(this) } class IceNicRecvPathModule(val outer: IceNicRecvPath) extends LazyModuleImp(outer) with HasNICParameters { val io = IO(new Bundle { val recv = Flipped(new IceNicRecvIO) val in = Flipped(Decoupled(new StreamChannel(NET_IF_WIDTH))) // input stream val tap = Vec(outer.tapFuncs.length, Decoupled(new StreamChannel(NET_IF_WIDTH))) val csum = checksumOffload.option(new Bundle { val res = Decoupled(new TCPChecksumOffloadResult) val enable = Input(Bool()) }) val buf_free = Output(Vec(1 + outer.tapFuncs.length, UInt(8.W))) }) def tapOutToDropCheck(tapOut: EthernetHeader => Bool) = { (header: EthernetHeader, ch: StreamChannel, update: Bool) => { val first = RegInit(true.B) val drop = tapOut(header) && first val dropReg = RegInit(false.B) when (update && first) { first := false.B; dropReg := drop } when (update && ch.last) { first := true.B; dropReg := false.B } drop \|\| dropReg } } def duplicateStream(in: DecoupledIO[StreamChannel], outs: Seq[DecoupledIO[StreamChannel]]) = { outs.foreach { out => out.valid := in.valid out.bits := in.bits } in.ready := outs.head.ready val outReadys = Cat(outs.map(_.ready)) assert(outReadys.andR \|\| !outReadys.orR, "Duplicated streams must all be ready simultaneously") outs } def invertCheck(check: (EthernetHeader, StreamChannel, Bool) => Bool) = (eth: EthernetHeader, ch: StreamChannel, up: Bool) => !check(eth, ch, up) val tapDropChecks = outer.tapFuncs.map(func => tapOutToDropCheck(func)) val pauseDropCheck = if (usePauser) Some(PauseDropCheck(_, _, _)) else None val allDropChecks = // Drop checks for the primary buffer // Drop if the packet should be tapped out or is a pause frame Seq(tapDropChecks ++ pauseDropCheck.toSeq) ++ // Drop checks for the tap buffers // For each tap, drop if the packet doesn't match the tap function or is a pause frame tapDropChecks.map(check => invertCheck(check) +: pauseDropCheck.toSeq) val buffers = allDropChecks.map(dropChecks => Module(new NetworkPacketBuffer( inBufFlits, maxBytes = packetMaxBytes, dropChecks = dropChecks, dropless = usePauser))) duplicateStream(io.in, buffers.map(_.io.stream.in)) io.buf_free := buffers.map(_.io.free) io.tap <> buffers.tail.map(_.io.stream.out) val bufout = buffers.head.io.stream.out val buflen = buffers.head.io.length val (csumout, recvreq) = (if (checksumOffload) { val offload = Module(new TCPChecksumOffload(NET_IF_WIDTH)) val offloadReady = offload.io.in.ready \|\| !io.csum.get.enable val out = Wire(Decoupled(new StreamChannel(NET_IF_WIDTH))) val recvreq = Wire(Decoupled(UInt(NET_IF_WIDTH.W))) val reqq = Module(new Queue(UInt(NET_IF_WIDTH.W), 1)) val enqHelper = DecoupledHelper( io.recv.req.valid, reqq.io.enq.ready, recvreq.ready) val deqHelper = DecoupledHelper( bufout.valid, offloadReady, out.ready, reqq.io.deq.valid) reqq.io.enq.valid := enqHelper.fire(reqq.io.enq.ready) reqq.io.enq.bits := io.recv.req.bits io.recv.req.ready := enqHelper.fire(io.recv.req.valid) recvreq.valid := enqHelper.fire(recvreq.ready) recvreq.bits := io.recv.req.bits out.valid := deqHelper.fire(out.ready) out.bits := bufout.bits offload.io.in.valid := deqHelper.fire(offloadReady, io.csum.get.enable) offload.io.in.bits := bufout.bits bufout.ready := deqHelper.fire(bufout.valid) reqq.io.deq.ready := deqHelper.fire(reqq.io.deq.valid, bufout.bits.last) io.csum.get.res <> offload.io.result (out, recvreq) } else { (bufout, io.recv.req) }) val writer = outer.writer.module writer.io.recv.req <> Queue(recvreq, 1) io.recv.comp <> writer.io.recv.comp writer.io.in <> csumout writer.io.length.valid := buflen.valid writer.io.length.bits := buflen.bits } class NICIO extends StreamIO(NET_IF_WIDTH) { val macAddr = Input(UInt(ETH_MAC_BITS.W)) val rlimit = Input(new RateLimiterSettings) val pauser = Input(new PauserSettings) } / * A simple NIC * * Expects ethernet frames (see below), but uses a custom transport * (see ExtBundle) * * Ethernet Frame format: * 2 bytes \| 6 bytes \| 6 bytes \| 2 bytes \| 46-1500B * Padding \| Dest Addr \| Source Addr \| Type/Len \| Data * * @address Starting address of MMIO control registers * @beatBytes Width of memory interface (in bytes) * @tapOutFuncs Sequence of functions for each output tap. * Each function takes the header of an Ethernet frame * and returns Bool that is true if matching and false if not. * @nInputTaps Number of input taps * / class IceNIC(address: BigInt, beatBytes: Int = 8, tapOutFuncs: Seq[EthernetHeader => Bool] = Nil, nInputTaps: Int = 0) (implicit p: Parameters) extends NICLazyModule { val control = LazyModule(new IceNicController( IceNicControllerParams(address, beatBytes))) val sendPath = LazyModule(new IceNicSendPath(nInputTaps)) val recvPath = LazyModule(new IceNicRecvPath(tapOutFuncs)) val mmionode = TLIdentityNode() val dmanode = TLIdentityNode() val intnode = control.intXing(NoCrossing) control.node := TLAtomicAutomata() := mmionode dmanode := TLWidthWidget(NET_IF_BYTES) := sendPath.node dmanode := TLWidthWidget(NET_IF_BYTES) := recvPath.node lazy val module = new Impl class Impl extends LazyModuleImp(this) { val io = IO(new Bundle { val ext = new NICIO val tapOut = Vec(tapOutFuncs.length, Decoupled(new StreamChannel(NET_IF_WIDTH))) val tapIn = Flipped(Vec(nInputTaps, Decoupled(new StreamChannel(NET_IF_WIDTH)))) }) sendPath.module.io.send <> control.module.io.send recvPath.module.io.recv <> control.module.io.recv // connect externally if (usePauser) { val pauser = Module(new Pauser(inBufFlits, 1 + tapOutFuncs.length)) pauser.io.int.out <> sendPath.module.io.out recvPath.module.io.in <> pauser.io.int.in io.ext.out <> pauser.io.ext.out pauser.io.ext.in <> io.ext.in pauser.io.in_free := recvPath.module.io.buf_free pauser.io.macAddr := io.ext.macAddr pauser.io.settings := io.ext.pauser } else { recvPath.module.io.in <> io.ext.in io.ext.out <> sendPath.module.io.out } control.module.io.macAddr := io.ext.macAddr sendPath.module.io.rlimit := io.ext.rlimit io.tapOut <> recvPath.module.io.tap sendPath.module.io.tap <> io.tapIn if (checksumOffload) { sendPath.module.io.csum.get.req <> control.module.io.txcsumReq sendPath.module.io.csum.get.enable := control.module.io.csumEnable control.module.io.rxcsumRes <> recvPath.module.io.csum.get.res recvPath.module.io.csum.get.enable := control.module.io.csumEnable } else { control.module.io.txcsumReq.ready := false.B control.module.io.rxcsumRes.valid := false.B control.module.io.rxcsumRes.bits := DontCare } } } class SimNetwork extends BlackBox with HasBlackBoxResource { val io = IO(new Bundle { val clock = Input(Clock()) val reset = Input(Bool()) val net = Flipped(new NICIOvonly) }) addResource("/vsrc/SimNetwork.v") addResource("/csrc/SimNetwork.cc") addResource("/csrc/device.h") addResource("/csrc/device.cc") addResource("/csrc/switch.h") addResource("/csrc/switch.cc") addResource("/csrc/packet.h") } class NICIOvonly extends Bundle { val in = Flipped(Valid(new StreamChannel(NET_IF_WIDTH))) val out = Valid(new StreamChannel(NET_IF_WIDTH)) val macAddr = Input(UInt(ETH_MAC_BITS.W)) val rlimit = Input(new RateLimiterSettings) val pauser = Input(new PauserSettings) } object NICIOvonly { def apply(nicio: NICIO): NICIOvonly = { val vonly = Wire(new NICIOvonly) vonly.out.valid := nicio.out.valid vonly.out.bits := nicio.out.bits nicio.out.ready := true.B nicio.in.valid := vonly.in.valid nicio.in.bits := vonly.in.bits assert(!vonly.in.valid \|\| nicio.in.ready, "NIC input not ready for valid") nicio.macAddr := vonly.macAddr nicio.rlimit := vonly.rlimit nicio.pauser := vonly.pauser vonly } } object NICIO { def apply(vonly: NICIOvonly): NICIO = { val nicio = Wire(new NICIO) assert(!vonly.out.valid \|\| nicio.out.ready) nicio.out.valid := vonly.out.valid nicio.out.bits := vonly.out.bits vonly.in.valid := nicio.in.valid vonly.in.bits := nicio.in.bits nicio.in.ready := true.B vonly.macAddr := nicio.macAddr vonly.rlimit := nicio.rlimit vonly.pauser := nicio.pauser nicio } } trait CanHavePeripheryIceNIC { this: BaseSubsystem => private val address = BigInt(0x10016000) private val portName = "Ice-NIC" val icenicOpt = p(NICKey).map { params => val manager = locateTLBusWrapper(p(NICAttachKey).slaveWhere) val client = locateTLBusWrapper(p(NICAttachKey).masterWhere) // TODO: currently the controller is in the clock domain of the bus which masters it // we assume this is same as the clock domain of the bus the controller masters val domain = manager.generateSynchronousDomain.suggestName("icenic_domain") val icenic = domain { LazyModule(new IceNIC(address, manager.beatBytes)) } manager.coupleTo(portName) { icenic.mmionode := TLFragmenter(manager.beatBytes, manager.blockBytes) := _ } client.coupleFrom(portName) { _ := icenic.dmanode } ibus.fromSync := icenic.intnode val inner_io = domain { InModuleBody { val inner_io = IO(new NICIOvonly).suggestName("nic") inner_io <> NICIOvonly(icenic.module.io.ext) inner_io } } val outer_io = InModuleBody { val outer_io = IO(new ClockedIO(new NICIOvonly)).suggestName("nic") outer_io.bits <> inner_io outer_io.clock := domain.module.clock outer_io } outer_io } } object NicLoopback { def connect(net: Option[NICIOvonly], nicConf: Option[NICConfig], qDepth: Int, latency: Int = 10): Unit = { net.foreach { netio => import PauseConsts.BT_PER_QUANTA val packetWords = nicConf.get.packetMaxBytes / NET_IF_BYTES val packetQuanta = (nicConf.get.packetMaxBytes * 8) / BT_PER_QUANTA netio.macAddr := PlusArg("macaddr") netio.rlimit.inc := PlusArg("rlimit-inc", 1) netio.rlimit.period := PlusArg("rlimit-period", 1) netio.rlimit.size := PlusArg("rlimit-size", 8) netio.pauser.threshold := PlusArg("pauser-threshold", 2 * packetWords + latency) netio.pauser.quanta := PlusArg("pauser-quanta", 2 * packetQuanta) netio.pauser.refresh := PlusArg("pauser-refresh", packetWords) if (nicConf.get.usePauser) { val pauser = Module(new PauserComplex(qDepth)) pauser.io.ext.flipConnect(NetDelay(NICIO(netio), latency)) pauser.io.int.out <> pauser.io.int.in pauser.io.macAddr := netio.macAddr + (1 << 40).U pauser.io.settings := netio.pauser } else { netio.in := Pipe(netio.out, latency) } netio.in.bits.keep := NET_FULL_KEEP } } def connect(net: NICIOvonly, nicConf: NICConfig): Unit = { val packetWords = nicConf.packetMaxBytes / NET_IF_BYTES NicLoopback.connect(Some(net), Some(nicConf), 4 * packetWords) } } object SimNetwork { def connect(net: Option[NICIOvonly], clock: Clock, reset: Bool) { net.foreach { netio => val sim = Module(new SimNetwork) sim.io.clock := clock sim.io.reset := reset sim.io.net <> netio } } } File Arbiters.scala: // See LICENSE.Berkeley for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters /** A generalized locking RR arbiter that addresses the limitations of the * version in the Chisel standard library / abstract class HellaLockingArbiter[T <: Data](typ: T, arbN: Int, rr: Boolean = false) extends Module { val io = IO(new Bundle { val in = Flipped(Vec(arbN, Decoupled(typ.cloneType))) val out = Decoupled(typ.cloneType) }) def rotateLeft[T <: Data](norm: Vec[T], rot: UInt): Vec[T] = { val n = norm.size VecInit.tabulate(n) { i => Mux(rot < (n - i).U, norm(i.U + rot), norm(rot - (n - i).U)) } } val lockIdx = RegInit(0.U(log2Up(arbN).W)) val locked = RegInit(false.B) val choice = if (rr) { PriorityMux( rotateLeft(VecInit(io.in.map(_.valid)), lockIdx + 1.U), rotateLeft(VecInit((0 until arbN).map(_.U)), lockIdx + 1.U)) } else { PriorityEncoder(io.in.map(_.valid)) } val chosen = Mux(locked, lockIdx, choice) for (i <- 0 until arbN) { io.in(i).ready := io.out.ready && chosen === i.U } io.out.valid := io.in(chosen).valid io.out.bits := io.in(chosen).bits } /* This locking arbiter determines when it is safe to unlock * by peeking at the data / class HellaPeekingArbiter[T <: Data]( typ: T, arbN: Int, canUnlock: T => Bool, needsLock: Option[T => Bool] = None, rr: Boolean = false) extends HellaLockingArbiter(typ, arbN, rr) { def realNeedsLock(data: T): Bool = needsLock.map(_(data)).getOrElse(true.B) when (io.out.fire) { when (!locked && realNeedsLock(io.out.bits)) { lockIdx := choice locked := true.B } // the unlock statement takes precedent when (canUnlock(io.out.bits)) { locked := false.B } } } /* This arbiter determines when it is safe to unlock by counting transactions / class HellaCountingArbiter[T <: Data]( typ: T, arbN: Int, count: Int, val needsLock: Option[T => Bool] = None, rr: Boolean = false) extends HellaLockingArbiter(typ, arbN, rr) { def realNeedsLock(data: T): Bool = needsLock.map(_(data)).getOrElse(true.B) // if count is 1, you should use a non-locking arbiter require(count > 1, "CountingArbiter cannot have count <= 1") val lock_ctr = Counter(count) when (io.out.fire) { when (!locked && realNeedsLock(io.out.bits)) { lockIdx := choice locked := true.B lock_ctr.inc() } when (locked) { when (lock_ctr.inc()) { locked := false.B } } } } /* This arbiter preserves the order of responses */ class InOrderArbiter[T <: Data, U <: Data](reqTyp: T, respTyp: U, n: Int) (implicit p: Parameters) extends Module { val io = IO(new Bundle { val in_req = Flipped(Vec(n, Decoupled(reqTyp))) val in_resp = Vec(n, Decoupled(respTyp)) val out_req = Decoupled(reqTyp) val out_resp = Flipped(Decoupled(respTyp)) }) if (n > 1) { val route_q = Module(new Queue(UInt(log2Up(n).W), 2)) val req_arb = Module(new RRArbiter(reqTyp, n)) req_arb.io.in <> io.in_req val req_helper = DecoupledHelper( req_arb.io.out.valid, route_q.io.enq.ready, io.out_req.ready) io.out_req.bits := req_arb.io.out.bits io.out_req.valid := req_helper.fire(io.out_req.ready) route_q.io.enq.bits := req_arb.io.chosen route_q.io.enq.valid := req_helper.fire(route_q.io.enq.ready) req_arb.io.out.ready := req_helper.fire(req_arb.io.out.valid) val resp_sel = route_q.io.deq.bits val resp_ready = io.in_resp(resp_sel).ready val resp_helper = DecoupledHelper( resp_ready, route_q.io.deq.valid, io.out_resp.valid) val resp_valid = resp_helper.fire(resp_ready) for (i <- 0 until n) { io.in_resp(i).bits := io.out_resp.bits io.in_resp(i).valid := resp_valid && resp_sel === i.U } route_q.io.deq.ready := resp_helper.fire(route_q.io.deq.valid) io.out_resp.ready := resp_helper.fire(io.out_resp.valid) } else { io.out_req <> io.in_req.head io.in_resp.head <> io.out_resp } }	module PacketArbiter( // @[NIC.scala:72:7] input clock, // @[NIC.scala:72:7] input reset, // @[NIC.scala:72:7] output io_in_0_ready, // @[Arbiters.scala:14:14] input io_in_0_valid, // @[Arbiters.scala:14:14] input [63:0] io_in_0_bits_data, // @[Arbiters.scala:14:14] input [7:0] io_in_0_bits_keep, // @[Arbiters.scala:14:14] input io_in_0_bits_last, // @[Arbiters.scala:14:14] output io_in_1_ready, // @[Arbiters.scala:14:14] input io_in_1_valid, // @[Arbiters.scala:14:14] input [63:0] io_in_1_bits_data, // @[Arbiters.scala:14:14] input [7:0] io_in_1_bits_keep, // @[Arbiters.scala:14:14] input io_in_1_bits_last, // @[Arbiters.scala:14:14] input io_out_ready, // @[Arbiters.scala:14:14] output io_out_valid, // @[Arbiters.scala:14:14] output [63:0] io_out_bits_data, // @[Arbiters.scala:14:14] output [7:0] io_out_bits_keep, // @[Arbiters.scala:14:14] output io_out_bits_last // @[Arbiters.scala:14:14] ); wire io_in_0_valid_0 = io_in_0_valid; // @[NIC.scala:72:7] wire [63:0] io_in_0_bits_data_0 = io_in_0_bits_data; // @[NIC.scala:72:7] wire [7:0] io_in_0_bits_keep_0 = io_in_0_bits_keep; // @[NIC.scala:72:7] wire io_in_0_bits_last_0 = io_in_0_bits_last; // @[NIC.scala:72:7] wire io_in_1_valid_0 = io_in_1_valid; // @[NIC.scala:72:7] wire [63:0] io_in_1_bits_data_0 = io_in_1_bits_data; // @[NIC.scala:72:7] wire [7:0] io_in_1_bits_keep_0 = io_in_1_bits_keep; // @[NIC.scala:72:7] wire io_in_1_bits_last_0 = io_in_1_bits_last; // @[NIC.scala:72:7] wire io_out_ready_0 = io_out_ready; // @[NIC.scala:72:7] wire _io_in_0_ready_T_1; // @[Arbiters.scala:40:36] wire _io_in_1_ready_T_1; // @[Arbiters.scala:40:36] wire io_in_0_ready_0; // @[NIC.scala:72:7] wire io_in_1_ready_0; // @[NIC.scala:72:7] wire [63:0] io_out_bits_data_0; // @[NIC.scala:72:7] wire [7:0] io_out_bits_keep_0; // @[NIC.scala:72:7] wire io_out_bits_last_0; // @[NIC.scala:72:7] wire io_out_valid_0; // @[NIC.scala:72:7] reg lockIdx; // @[Arbiters.scala:26:24] reg locked; // @[Arbiters.scala:27:23] wire choice = ~io_in_0_valid_0; // @[Mux.scala:50:70] wire chosen = locked ? lockIdx : choice; // @[Mux.scala:50:70] wire _io_in_1_ready_T = chosen; // @[Arbiters.scala:37:19, :40:46] wire _io_in_0_ready_T = ~chosen; // @[Arbiters.scala:37:19, :40:46] assign _io_in_0_ready_T_1 = io_out_ready_0 & _io_in_0_ready_T; // @[Arbiters.scala:40:{36,46}] assign io_in_0_ready_0 = _io_in_0_ready_T_1; // @[Arbiters.scala:40:36] assign _io_in_1_ready_T_1 = io_out_ready_0 & _io_in_1_ready_T; // @[Arbiters.scala:40:{36,46}] assign io_in_1_ready_0 = _io_in_1_ready_T_1; // @[Arbiters.scala:40:36] assign io_out_valid_0 = chosen ? io_in_1_valid_0 : io_in_0_valid_0; // @[Arbiters.scala:37:19, :43:16] assign io_out_bits_data_0 = chosen ? io_in_1_bits_data_0 : io_in_0_bits_data_0; // @[Arbiters.scala:37:19, :43:16] assign io_out_bits_keep_0 = chosen ? io_in_1_bits_keep_0 : io_in_0_bits_keep_0; // @[Arbiters.scala:37:19, :43:16] assign io_out_bits_last_0 = chosen ? io_in_1_bits_last_0 : io_in_0_bits_last_0; // @[Arbiters.scala:37:19, :43:16] wire _T = io_out_ready_0 & io_out_valid_0; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[NIC.scala:72:7] if (reset) begin // @[NIC.scala:72:7] lockIdx <= 1'h0; // @[Arbiters.scala:26:24] locked <= 1'h0; // @[Arbiters.scala:27:23] end else begin // @[NIC.scala:72:7] if (_T & ~locked) // @[Decoupled.scala:51:35] lockIdx <= choice; // @[Mux.scala:50:70] if (_T) // @[Decoupled.scala:51:35] locked <= ~io_out_bits_last_0; // @[Arbiters.scala:27:23, :60:50, :65:35, :66:14] end always @(posedge) assign io_in_0_ready = io_in_0_ready_0; // @[NIC.scala:72:7] assign io_in_1_ready = io_in_1_ready_0; // @[NIC.scala:72:7] assign io_out_valid = io_out_valid_0; // @[NIC.scala:72:7] assign io_out_bits_data = io_out_bits_data_0; // @[NIC.scala:72:7] assign io_out_bits_keep = io_out_bits_keep_0; // @[NIC.scala:72:7] assign io_out_bits_last = io_out_bits_last_0; // @[NIC.scala:72:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Replacement.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import freechips.rocketchip.util.property.cover abstract class ReplacementPolicy { def nBits: Int def perSet: Boolean def way: UInt def miss: Unit def hit: Unit def access(touch_way: UInt): Unit def access(touch_ways: Seq[Valid[UInt]]): Unit def state_read: UInt def get_next_state(state: UInt, touch_way: UInt): UInt def get_next_state(state: UInt, touch_ways: Seq[Valid[UInt]]): UInt = { touch_ways.foldLeft(state)((prev, touch_way) => Mux(touch_way.valid, get_next_state(prev, touch_way.bits), prev)) } def get_replace_way(state: UInt): UInt } object ReplacementPolicy { def fromString(s: String, n_ways: Int): ReplacementPolicy = s.toLowerCase match { case "random" => new RandomReplacement(n_ways) case "lru" => new TrueLRU(n_ways) case "plru" => new PseudoLRU(n_ways) case t => throw new IllegalArgumentException(s"unknown Replacement Policy type $t") } } class RandomReplacement(n_ways: Int) extends ReplacementPolicy { private val replace = Wire(Bool()) replace := false.B def nBits = 16 def perSet = false private val lfsr = LFSR(nBits, replace) def state_read = WireDefault(lfsr) def way = Random(n_ways, lfsr) def miss = replace := true.B def hit = {} def access(touch_way: UInt) = {} def access(touch_ways: Seq[Valid[UInt]]) = {} def get_next_state(state: UInt, touch_way: UInt) = 0.U //DontCare def get_replace_way(state: UInt) = way } abstract class SeqReplacementPolicy { def access(set: UInt): Unit def update(valid: Bool, hit: Bool, set: UInt, way: UInt): Unit def way: UInt } abstract class SetAssocReplacementPolicy { def access(set: UInt, touch_way: UInt): Unit def access(sets: Seq[UInt], touch_ways: Seq[Valid[UInt]]): Unit def way(set: UInt): UInt } class SeqRandom(n_ways: Int) extends SeqReplacementPolicy { val logic = new RandomReplacement(n_ways) def access(set: UInt) = { } def update(valid: Bool, hit: Bool, set: UInt, way: UInt) = { when (valid && !hit) { logic.miss } } def way = logic.way } class TrueLRU(n_ways: Int) extends ReplacementPolicy { // True LRU replacement policy, using a triangular matrix to track which sets are more recently used than others. // The matrix is packed into a single UInt (or Bits). Example 4-way (6-bits): // [5] - 3 more recent than 2 // [4] - 3 more recent than 1 // [3] - 2 more recent than 1 // [2] - 3 more recent than 0 // [1] - 2 more recent than 0 // [0] - 1 more recent than 0 def nBits = (n_ways (n_ways-1)) / 2 def perSet = true private val state_reg = RegInit(0.U(nBits.W)) def state_read = WireDefault(state_reg) private def extractMRUVec(state: UInt): Seq[UInt] = { // Extract per-way information about which higher-indexed ways are more recently used val moreRecentVec = Wire(Vec(n_ways-1, UInt(n_ways.W))) var lsb = 0 for (i <- 0 until n_ways-1) { moreRecentVec(i) := Cat(state(lsb+n_ways-i-2,lsb), 0.U((i+1).W)) lsb = lsb + (n_ways - i - 1) } moreRecentVec } def get_next_state(state: UInt, touch_way: UInt): UInt = { val nextState = Wire(Vec(n_ways-1, UInt(n_ways.W))) val moreRecentVec = extractMRUVec(state) // reconstruct lower triangular matrix val wayDec = UIntToOH(touch_way, n_ways) // Compute next value of triangular matrix // set the touched way as more recent than every other way nextState.zipWithIndex.map { case (e, i) => e := Mux(i.U === touch_way, 0.U(n_ways.W), moreRecentVec(i) \| wayDec) } nextState.zipWithIndex.tail.foldLeft((nextState.head.apply(n_ways-1,1),0)) { case ((pe,pi),(ce,ci)) => (Cat(ce.apply(n_ways-1,ci+1), pe), ci) }._1 } def access(touch_way: UInt): Unit = { state_reg := get_next_state(state_reg, touch_way) } def access(touch_ways: Seq[Valid[UInt]]): Unit = { when (touch_ways.map(_.valid).orR) { state_reg := get_next_state(state_reg, touch_ways) } for (i <- 1 until touch_ways.size) { cover(PopCount(touch_ways.map(_.valid)) === i.U, s"LRU_UpdateCount$i", s"LRU Update $i simultaneous") } } def get_replace_way(state: UInt): UInt = { val moreRecentVec = extractMRUVec(state) // reconstruct lower triangular matrix // For each way, determine if all other ways are more recent val mruWayDec = (0 until n_ways).map { i => val upperMoreRecent = (if (i == n_ways-1) true.B else moreRecentVec(i).apply(n_ways-1,i+1).andR) val lowerMoreRecent = (if (i == 0) true.B else moreRecentVec.map(e => !e(i)).reduce(_ && _)) upperMoreRecent && lowerMoreRecent } OHToUInt(mruWayDec) } def way = get_replace_way(state_reg) def miss = access(way) def hit = {} @deprecated("replace 'replace' with 'way' from abstract class ReplacementPolicy","Rocket Chip 2020.05") def replace: UInt = way } class PseudoLRU(n_ways: Int) extends ReplacementPolicy { // Pseudo-LRU tree algorithm: https://en.wikipedia.org/wiki/Pseudo-LRU#Tree-PLRU // // // - bits storage example for 4-way PLRU binary tree: // bit[2]: ways 3+2 older than ways 1+0 // / \ // bit[1]: way 3 older than way 2 bit[0]: way 1 older than way 0 // // // - bits storage example for 3-way PLRU binary tree: // bit[1]: way 2 older than ways 1+0 // \ // bit[0]: way 1 older than way 0 // // // - bits storage example for 8-way PLRU binary tree: // bit[6]: ways 7-4 older than ways 3-0 // / \ // bit[5]: ways 7+6 > 5+4 bit[2]: ways 3+2 > 1+0 // / \ / \ // bit[4]: way 7>6 bit[3]: way 5>4 bit[1]: way 3>2 bit[0]: way 1>0 def nBits = n_ways - 1 def perSet = true private val state_reg = if (nBits == 0) Reg(UInt(0.W)) else RegInit(0.U(nBits.W)) def state_read = WireDefault(state_reg) def access(touch_way: UInt): Unit = { state_reg := get_next_state(state_reg, touch_way) } def access(touch_ways: Seq[Valid[UInt]]): Unit = { when (touch_ways.map(_.valid).orR) { state_reg := get_next_state(state_reg, touch_ways) } for (i <- 1 until touch_ways.size) { cover(PopCount(touch_ways.map(_.valid)) === i.U, s"PLRU_UpdateCount$i", s"PLRU Update $i simultaneous") } } /** @param state state_reg bits for this sub-tree * @param touch_way touched way encoded value bits for this sub-tree * @param tree_nways number of ways in this sub-tree / def get_next_state(state: UInt, touch_way: UInt, tree_nways: Int): UInt = { require(state.getWidth == (tree_nways-1), s"wrong state bits width ${state.getWidth} for $tree_nways ways") require(touch_way.getWidth == (log2Ceil(tree_nways) max 1), s"wrong encoded way width ${touch_way.getWidth} for $tree_nways ways") if (tree_nways > 2) { // we are at a branching node in the tree, so recurse val right_nways: Int = 1 << (log2Ceil(tree_nways) - 1) // number of ways in the right sub-tree val left_nways: Int = tree_nways - right_nways // number of ways in the left sub-tree val set_left_older = !touch_way(log2Ceil(tree_nways)-1) val left_subtree_state = state.extract(tree_nways-3, right_nways-1) val right_subtree_state = state(right_nways-2, 0) if (left_nways > 1) { // we are at a branching node in the tree with both left and right sub-trees, so recurse both sub-trees Cat(set_left_older, Mux(set_left_older, left_subtree_state, // if setting left sub-tree as older, do NOT recurse into left sub-tree get_next_state(left_subtree_state, touch_way.extract(log2Ceil(left_nways)-1,0), left_nways)), // recurse left if newer Mux(set_left_older, get_next_state(right_subtree_state, touch_way(log2Ceil(right_nways)-1,0), right_nways), // recurse right if newer right_subtree_state)) // if setting right sub-tree as older, do NOT recurse into right sub-tree } else { // we are at a branching node in the tree with only a right sub-tree, so recurse only right sub-tree Cat(set_left_older, Mux(set_left_older, get_next_state(right_subtree_state, touch_way(log2Ceil(right_nways)-1,0), right_nways), // recurse right if newer right_subtree_state)) // if setting right sub-tree as older, do NOT recurse into right sub-tree } } else if (tree_nways == 2) { // we are at a leaf node at the end of the tree, so set the single state bit opposite of the lsb of the touched way encoded value !touch_way(0) } else { // tree_nways <= 1 // we are at an empty node in an empty tree for 1 way, so return single zero bit for Chisel (no zero-width wires) 0.U(1.W) } } def get_next_state(state: UInt, touch_way: UInt): UInt = { val touch_way_sized = if (touch_way.getWidth < log2Ceil(n_ways)) touch_way.padTo (log2Ceil(n_ways)) else touch_way.extract(log2Ceil(n_ways)-1,0) get_next_state(state, touch_way_sized, n_ways) } /* @param state state_reg bits for this sub-tree * @param tree_nways number of ways in this sub-tree / def get_replace_way(state: UInt, tree_nways: Int): UInt = { require(state.getWidth == (tree_nways-1), s"wrong state bits width ${state.getWidth} for $tree_nways ways") // this algorithm recursively descends the binary tree, filling in the way-to-replace encoded value from msb to lsb if (tree_nways > 2) { // we are at a branching node in the tree, so recurse val right_nways: Int = 1 << (log2Ceil(tree_nways) - 1) // number of ways in the right sub-tree val left_nways: Int = tree_nways - right_nways // number of ways in the left sub-tree val left_subtree_older = state(tree_nways-2) val left_subtree_state = state.extract(tree_nways-3, right_nways-1) val right_subtree_state = state(right_nways-2, 0) if (left_nways > 1) { // we are at a branching node in the tree with both left and right sub-trees, so recurse both sub-trees Cat(left_subtree_older, // return the top state bit (current tree node) as msb of the way-to-replace encoded value Mux(left_subtree_older, // if left sub-tree is older, recurse left, else recurse right get_replace_way(left_subtree_state, left_nways), // recurse left get_replace_way(right_subtree_state, right_nways))) // recurse right } else { // we are at a branching node in the tree with only a right sub-tree, so recurse only right sub-tree Cat(left_subtree_older, // return the top state bit (current tree node) as msb of the way-to-replace encoded value Mux(left_subtree_older, // if left sub-tree is older, return and do not recurse right 0.U(1.W), get_replace_way(right_subtree_state, right_nways))) // recurse right } } else if (tree_nways == 2) { // we are at a leaf node at the end of the tree, so just return the single state bit as lsb of the way-to-replace encoded value state(0) } else { // tree_nways <= 1 // we are at an empty node in an unbalanced tree for non-power-of-2 ways, so return single zero bit as lsb of the way-to-replace encoded value 0.U(1.W) } } def get_replace_way(state: UInt): UInt = get_replace_way(state, n_ways) def way = get_replace_way(state_reg) def miss = access(way) def hit = {} } class SeqPLRU(n_sets: Int, n_ways: Int) extends SeqReplacementPolicy { val logic = new PseudoLRU(n_ways) val state = SyncReadMem(n_sets, UInt(logic.nBits.W)) val current_state = Wire(UInt(logic.nBits.W)) val next_state = Wire(UInt(logic.nBits.W)) val plru_way = logic.get_replace_way(current_state) def access(set: UInt) = { current_state := state.read(set) } def update(valid: Bool, hit: Bool, set: UInt, way: UInt) = { val update_way = Mux(hit, way, plru_way) next_state := logic.get_next_state(current_state, update_way) when (valid) { state.write(set, next_state) } } def way = plru_way } class SetAssocLRU(n_sets: Int, n_ways: Int, policy: String) extends SetAssocReplacementPolicy { val logic = policy.toLowerCase match { case "plru" => new PseudoLRU(n_ways) case "lru" => new TrueLRU(n_ways) case t => throw new IllegalArgumentException(s"unknown Replacement Policy type $t") } val state_vec = if (logic.nBits == 0) Reg(Vec(n_sets, UInt(logic.nBits.W))) // Work around elaboration error on following line else RegInit(VecInit(Seq.fill(n_sets)(0.U(logic.nBits.W)))) def access(set: UInt, touch_way: UInt) = { state_vec(set) := logic.get_next_state(state_vec(set), touch_way) } def access(sets: Seq[UInt], touch_ways: Seq[Valid[UInt]]) = { require(sets.size == touch_ways.size, "internal consistency check: should be same number of simultaneous updates for sets and touch_ways") for (set <- 0 until n_sets) { val set_touch_ways = (sets zip touch_ways).map { case (touch_set, touch_way) => Pipe(touch_way.valid && (touch_set === set.U), touch_way.bits, 0)} when (set_touch_ways.map(_.valid).orR) { state_vec(set) := logic.get_next_state(state_vec(set), set_touch_ways) } } } def way(set: UInt) = logic.get_replace_way(state_vec(set)) } // Synthesizable unit tests import freechips.rocketchip.unittest._ class PLRUTest(n_ways: Int, timeout: Int = 500) extends UnitTest(timeout) { val plru = new PseudoLRU(n_ways) // step io.finished := RegNext(true.B, false.B) val get_replace_ways = (0 until (1 << (n_ways-1))).map(state => plru.get_replace_way(state = state.U((n_ways-1).W))) val get_next_states = (0 until (1 << (n_ways-1))).map(state => (0 until n_ways).map(way => plru.get_next_state (state = state.U((n_ways-1).W), touch_way = way.U(log2Ceil(n_ways).W)))) n_ways match { case 2 => { assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0)) assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1)) assert(get_next_states(0)(0) === 1.U(plru.nBits.W), s"get_next_state state=0 way=0: expected=1 actual=%d", get_next_states(0)(0)) assert(get_next_states(0)(1) === 0.U(plru.nBits.W), s"get_next_state state=0 way=1: expected=0 actual=%d", get_next_states(0)(1)) assert(get_next_states(1)(0) === 1.U(plru.nBits.W), s"get_next_state state=1 way=0: expected=1 actual=%d", get_next_states(1)(0)) assert(get_next_states(1)(1) === 0.U(plru.nBits.W), s"get_next_state state=1 way=1: expected=0 actual=%d", get_next_states(1)(1)) } case 3 => { assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0)) assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1)) assert(get_replace_ways(2) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=2: expected=2 actual=%d", get_replace_ways(2)) assert(get_replace_ways(3) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=3: expected=2 actual=%d", get_replace_ways(3)) assert(get_next_states(0)(0) === 3.U(plru.nBits.W), s"get_next_state state=0 way=0: expected=3 actual=%d", get_next_states(0)(0)) assert(get_next_states(0)(1) === 2.U(plru.nBits.W), s"get_next_state state=0 way=1: expected=2 actual=%d", get_next_states(0)(1)) assert(get_next_states(0)(2) === 0.U(plru.nBits.W), s"get_next_state state=0 way=2: expected=0 actual=%d", get_next_states(0)(2)) assert(get_next_states(1)(0) === 3.U(plru.nBits.W), s"get_next_state state=1 way=0: expected=3 actual=%d", get_next_states(1)(0)) assert(get_next_states(1)(1) === 2.U(plru.nBits.W), s"get_next_state state=1 way=1: expected=2 actual=%d", get_next_states(1)(1)) assert(get_next_states(1)(2) === 1.U(plru.nBits.W), s"get_next_state state=1 way=2: expected=1 actual=%d", get_next_states(1)(2)) assert(get_next_states(2)(0) === 3.U(plru.nBits.W), s"get_next_state state=2 way=0: expected=3 actual=%d", get_next_states(2)(0)) assert(get_next_states(2)(1) === 2.U(plru.nBits.W), s"get_next_state state=2 way=1: expected=2 actual=%d", get_next_states(2)(1)) assert(get_next_states(2)(2) === 0.U(plru.nBits.W), s"get_next_state state=2 way=2: expected=0 actual=%d", get_next_states(2)(2)) assert(get_next_states(3)(0) === 3.U(plru.nBits.W), s"get_next_state state=3 way=0: expected=3 actual=%d", get_next_states(3)(0)) assert(get_next_states(3)(1) === 2.U(plru.nBits.W), s"get_next_state state=3 way=1: expected=2 actual=%d", get_next_states(3)(1)) assert(get_next_states(3)(2) === 1.U(plru.nBits.W), s"get_next_state state=3 way=2: expected=1 actual=%d", get_next_states(3)(2)) } case 4 => { assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0)) assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1)) assert(get_replace_ways(2) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=2: expected=0 actual=%d", get_replace_ways(2)) assert(get_replace_ways(3) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=3: expected=1 actual=%d", get_replace_ways(3)) assert(get_replace_ways(4) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=4: expected=2 actual=%d", get_replace_ways(4)) assert(get_replace_ways(5) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=5: expected=2 actual=%d", get_replace_ways(5)) assert(get_replace_ways(6) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=6: expected=3 actual=%d", get_replace_ways(6)) assert(get_replace_ways(7) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=7: expected=3 actual=%d", get_replace_ways(7)) assert(get_next_states(0)(0) === 5.U(plru.nBits.W), s"get_next_state state=0 way=0: expected=5 actual=%d", get_next_states(0)(0)) assert(get_next_states(0)(1) === 4.U(plru.nBits.W), s"get_next_state state=0 way=1: expected=4 actual=%d", get_next_states(0)(1)) assert(get_next_states(0)(2) === 2.U(plru.nBits.W), s"get_next_state state=0 way=2: expected=2 actual=%d", get_next_states(0)(2)) assert(get_next_states(0)(3) === 0.U(plru.nBits.W), s"get_next_state state=0 way=3: expected=0 actual=%d", get_next_states(0)(3)) assert(get_next_states(1)(0) === 5.U(plru.nBits.W), s"get_next_state state=1 way=0: expected=5 actual=%d", get_next_states(1)(0)) assert(get_next_states(1)(1) === 4.U(plru.nBits.W), s"get_next_state state=1 way=1: expected=4 actual=%d", get_next_states(1)(1)) assert(get_next_states(1)(2) === 3.U(plru.nBits.W), s"get_next_state state=1 way=2: expected=3 actual=%d", get_next_states(1)(2)) assert(get_next_states(1)(3) === 1.U(plru.nBits.W), s"get_next_state state=1 way=3: expected=1 actual=%d", get_next_states(1)(3)) assert(get_next_states(2)(0) === 7.U(plru.nBits.W), s"get_next_state state=2 way=0: expected=7 actual=%d", get_next_states(2)(0)) assert(get_next_states(2)(1) === 6.U(plru.nBits.W), s"get_next_state state=2 way=1: expected=6 actual=%d", get_next_states(2)(1)) assert(get_next_states(2)(2) === 2.U(plru.nBits.W), s"get_next_state state=2 way=2: expected=2 actual=%d", get_next_states(2)(2)) assert(get_next_states(2)(3) === 0.U(plru.nBits.W), s"get_next_state state=2 way=3: expected=0 actual=%d", get_next_states(2)(3)) assert(get_next_states(3)(0) === 7.U(plru.nBits.W), s"get_next_state state=3 way=0: expected=7 actual=%d", get_next_states(3)(0)) assert(get_next_states(3)(1) === 6.U(plru.nBits.W), s"get_next_state state=3 way=1: expected=6 actual=%d", get_next_states(3)(1)) assert(get_next_states(3)(2) === 3.U(plru.nBits.W), s"get_next_state state=3 way=2: expected=3 actual=%d", get_next_states(3)(2)) assert(get_next_states(3)(3) === 1.U(plru.nBits.W), s"get_next_state state=3 way=3: expected=1 actual=%d", get_next_states(3)(3)) assert(get_next_states(4)(0) === 5.U(plru.nBits.W), s"get_next_state state=4 way=0: expected=5 actual=%d", get_next_states(4)(0)) assert(get_next_states(4)(1) === 4.U(plru.nBits.W), s"get_next_state state=4 way=1: expected=4 actual=%d", get_next_states(4)(1)) assert(get_next_states(4)(2) === 2.U(plru.nBits.W), s"get_next_state state=4 way=2: expected=2 actual=%d", get_next_states(4)(2)) assert(get_next_states(4)(3) === 0.U(plru.nBits.W), s"get_next_state state=4 way=3: expected=0 actual=%d", get_next_states(4)(3)) assert(get_next_states(5)(0) === 5.U(plru.nBits.W), s"get_next_state state=5 way=0: expected=5 actual=%d", get_next_states(5)(0)) assert(get_next_states(5)(1) === 4.U(plru.nBits.W), s"get_next_state state=5 way=1: expected=4 actual=%d", get_next_states(5)(1)) assert(get_next_states(5)(2) === 3.U(plru.nBits.W), s"get_next_state state=5 way=2: expected=3 actual=%d", get_next_states(5)(2)) assert(get_next_states(5)(3) === 1.U(plru.nBits.W), s"get_next_state state=5 way=3: expected=1 actual=%d", get_next_states(5)(3)) assert(get_next_states(6)(0) === 7.U(plru.nBits.W), s"get_next_state state=6 way=0: expected=7 actual=%d", get_next_states(6)(0)) assert(get_next_states(6)(1) === 6.U(plru.nBits.W), s"get_next_state state=6 way=1: expected=6 actual=%d", get_next_states(6)(1)) assert(get_next_states(6)(2) === 2.U(plru.nBits.W), s"get_next_state state=6 way=2: expected=2 actual=%d", get_next_states(6)(2)) assert(get_next_states(6)(3) === 0.U(plru.nBits.W), s"get_next_state state=6 way=3: expected=0 actual=%d", get_next_states(6)(3)) assert(get_next_states(7)(0) === 7.U(plru.nBits.W), s"get_next_state state=7 way=0: expected=7 actual=%d", get_next_states(7)(0)) assert(get_next_states(7)(1) === 6.U(plru.nBits.W), s"get_next_state state=7 way=5: expected=6 actual=%d", get_next_states(7)(1)) assert(get_next_states(7)(2) === 3.U(plru.nBits.W), s"get_next_state state=7 way=2: expected=3 actual=%d", get_next_states(7)(2)) assert(get_next_states(7)(3) === 1.U(plru.nBits.W), s"get_next_state state=7 way=3: expected=1 actual=%d", get_next_states(7)(3)) } case 5 => { assert(get_replace_ways( 0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=00: expected=0 actual=%d", get_replace_ways( 0)) assert(get_replace_ways( 1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=01: expected=1 actual=%d", get_replace_ways( 1)) assert(get_replace_ways( 2) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=02: expected=0 actual=%d", get_replace_ways( 2)) assert(get_replace_ways( 3) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=03: expected=1 actual=%d", get_replace_ways( 3)) assert(get_replace_ways( 4) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=04: expected=2 actual=%d", get_replace_ways( 4)) assert(get_replace_ways( 5) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=05: expected=2 actual=%d", get_replace_ways( 5)) assert(get_replace_ways( 6) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=06: expected=3 actual=%d", get_replace_ways( 6)) assert(get_replace_ways( 7) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=07: expected=3 actual=%d", get_replace_ways( 7)) assert(get_replace_ways( 8) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=08: expected=4 actual=%d", get_replace_ways( 8)) assert(get_replace_ways( 9) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=09: expected=4 actual=%d", get_replace_ways( 9)) assert(get_replace_ways(10) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=10: expected=4 actual=%d", get_replace_ways(10)) assert(get_replace_ways(11) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=11: expected=4 actual=%d", get_replace_ways(11)) assert(get_replace_ways(12) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=12: expected=4 actual=%d", get_replace_ways(12)) assert(get_replace_ways(13) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=13: expected=4 actual=%d", get_replace_ways(13)) assert(get_replace_ways(14) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=14: expected=4 actual=%d", get_replace_ways(14)) assert(get_replace_ways(15) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=15: expected=4 actual=%d", get_replace_ways(15)) assert(get_next_states( 0)(0) === 13.U(plru.nBits.W), s"get_next_state state=00 way=0: expected=13 actual=%d", get_next_states( 0)(0)) assert(get_next_states( 0)(1) === 12.U(plru.nBits.W), s"get_next_state state=00 way=1: expected=12 actual=%d", get_next_states( 0)(1)) assert(get_next_states( 0)(2) === 10.U(plru.nBits.W), s"get_next_state state=00 way=2: expected=10 actual=%d", get_next_states( 0)(2)) assert(get_next_states( 0)(3) === 8.U(plru.nBits.W), s"get_next_state state=00 way=3: expected=08 actual=%d", get_next_states( 0)(3)) assert(get_next_states( 0)(4) === 0.U(plru.nBits.W), s"get_next_state state=00 way=4: expected=00 actual=%d", get_next_states( 0)(4)) assert(get_next_states( 1)(0) === 13.U(plru.nBits.W), s"get_next_state state=01 way=0: expected=13 actual=%d", get_next_states( 1)(0)) assert(get_next_states( 1)(1) === 12.U(plru.nBits.W), s"get_next_state state=01 way=1: expected=12 actual=%d", get_next_states( 1)(1)) assert(get_next_states( 1)(2) === 11.U(plru.nBits.W), s"get_next_state state=01 way=2: expected=11 actual=%d", get_next_states( 1)(2)) assert(get_next_states( 1)(3) === 9.U(plru.nBits.W), s"get_next_state state=01 way=3: expected=09 actual=%d", get_next_states( 1)(3)) assert(get_next_states( 1)(4) === 1.U(plru.nBits.W), s"get_next_state state=01 way=4: expected=01 actual=%d", get_next_states( 1)(4)) assert(get_next_states( 2)(0) === 15.U(plru.nBits.W), s"get_next_state state=02 way=0: expected=15 actual=%d", get_next_states( 2)(0)) assert(get_next_states( 2)(1) === 14.U(plru.nBits.W), s"get_next_state state=02 way=1: expected=14 actual=%d", get_next_states( 2)(1)) assert(get_next_states( 2)(2) === 10.U(plru.nBits.W), s"get_next_state state=02 way=2: expected=10 actual=%d", get_next_states( 2)(2)) assert(get_next_states( 2)(3) === 8.U(plru.nBits.W), s"get_next_state state=02 way=3: expected=08 actual=%d", get_next_states( 2)(3)) assert(get_next_states( 2)(4) === 2.U(plru.nBits.W), s"get_next_state state=02 way=4: expected=02 actual=%d", get_next_states( 2)(4)) assert(get_next_states( 3)(0) === 15.U(plru.nBits.W), s"get_next_state state=03 way=0: expected=15 actual=%d", get_next_states( 3)(0)) assert(get_next_states( 3)(1) === 14.U(plru.nBits.W), s"get_next_state state=03 way=1: expected=14 actual=%d", get_next_states( 3)(1)) assert(get_next_states( 3)(2) === 11.U(plru.nBits.W), s"get_next_state state=03 way=2: expected=11 actual=%d", get_next_states( 3)(2)) assert(get_next_states( 3)(3) === 9.U(plru.nBits.W), s"get_next_state state=03 way=3: expected=09 actual=%d", get_next_states( 3)(3)) assert(get_next_states( 3)(4) === 3.U(plru.nBits.W), s"get_next_state state=03 way=4: expected=03 actual=%d", get_next_states( 3)(4)) assert(get_next_states( 4)(0) === 13.U(plru.nBits.W), s"get_next_state state=04 way=0: expected=13 actual=%d", get_next_states( 4)(0)) assert(get_next_states( 4)(1) === 12.U(plru.nBits.W), s"get_next_state state=04 way=1: expected=12 actual=%d", get_next_states( 4)(1)) assert(get_next_states( 4)(2) === 10.U(plru.nBits.W), s"get_next_state state=04 way=2: expected=10 actual=%d", get_next_states( 4)(2)) assert(get_next_states( 4)(3) === 8.U(plru.nBits.W), s"get_next_state state=04 way=3: expected=08 actual=%d", get_next_states( 4)(3)) assert(get_next_states( 4)(4) === 4.U(plru.nBits.W), s"get_next_state state=04 way=4: expected=04 actual=%d", get_next_states( 4)(4)) assert(get_next_states( 5)(0) === 13.U(plru.nBits.W), s"get_next_state state=05 way=0: expected=13 actual=%d", get_next_states( 5)(0)) assert(get_next_states( 5)(1) === 12.U(plru.nBits.W), s"get_next_state state=05 way=1: expected=12 actual=%d", get_next_states( 5)(1)) assert(get_next_states( 5)(2) === 11.U(plru.nBits.W), s"get_next_state state=05 way=2: expected=11 actual=%d", get_next_states( 5)(2)) assert(get_next_states( 5)(3) === 9.U(plru.nBits.W), s"get_next_state state=05 way=3: expected=09 actual=%d", get_next_states( 5)(3)) assert(get_next_states( 5)(4) === 5.U(plru.nBits.W), s"get_next_state state=05 way=4: expected=05 actual=%d", get_next_states( 5)(4)) assert(get_next_states( 6)(0) === 15.U(plru.nBits.W), s"get_next_state state=06 way=0: expected=15 actual=%d", get_next_states( 6)(0)) assert(get_next_states( 6)(1) === 14.U(plru.nBits.W), s"get_next_state state=06 way=1: expected=14 actual=%d", get_next_states( 6)(1)) assert(get_next_states( 6)(2) === 10.U(plru.nBits.W), s"get_next_state state=06 way=2: expected=10 actual=%d", get_next_states( 6)(2)) assert(get_next_states( 6)(3) === 8.U(plru.nBits.W), s"get_next_state state=06 way=3: expected=08 actual=%d", get_next_states( 6)(3)) assert(get_next_states( 6)(4) === 6.U(plru.nBits.W), s"get_next_state state=06 way=4: expected=06 actual=%d", get_next_states( 6)(4)) assert(get_next_states( 7)(0) === 15.U(plru.nBits.W), s"get_next_state state=07 way=0: expected=15 actual=%d", get_next_states( 7)(0)) assert(get_next_states( 7)(1) === 14.U(plru.nBits.W), s"get_next_state state=07 way=5: expected=14 actual=%d", get_next_states( 7)(1)) assert(get_next_states( 7)(2) === 11.U(plru.nBits.W), s"get_next_state state=07 way=2: expected=11 actual=%d", get_next_states( 7)(2)) assert(get_next_states( 7)(3) === 9.U(plru.nBits.W), s"get_next_state state=07 way=3: expected=09 actual=%d", get_next_states( 7)(3)) assert(get_next_states( 7)(4) === 7.U(plru.nBits.W), s"get_next_state state=07 way=4: expected=07 actual=%d", get_next_states( 7)(4)) assert(get_next_states( 8)(0) === 13.U(plru.nBits.W), s"get_next_state state=08 way=0: expected=13 actual=%d", get_next_states( 8)(0)) assert(get_next_states( 8)(1) === 12.U(plru.nBits.W), s"get_next_state state=08 way=1: expected=12 actual=%d", get_next_states( 8)(1)) assert(get_next_states( 8)(2) === 10.U(plru.nBits.W), s"get_next_state state=08 way=2: expected=10 actual=%d", get_next_states( 8)(2)) assert(get_next_states( 8)(3) === 8.U(plru.nBits.W), s"get_next_state state=08 way=3: expected=08 actual=%d", get_next_states( 8)(3)) assert(get_next_states( 8)(4) === 0.U(plru.nBits.W), s"get_next_state state=08 way=4: expected=00 actual=%d", get_next_states( 8)(4)) assert(get_next_states( 9)(0) === 13.U(plru.nBits.W), s"get_next_state state=09 way=0: expected=13 actual=%d", get_next_states( 9)(0)) assert(get_next_states( 9)(1) === 12.U(plru.nBits.W), s"get_next_state state=09 way=1: expected=12 actual=%d", get_next_states( 9)(1)) assert(get_next_states( 9)(2) === 11.U(plru.nBits.W), s"get_next_state state=09 way=2: expected=11 actual=%d", get_next_states( 9)(2)) assert(get_next_states( 9)(3) === 9.U(plru.nBits.W), s"get_next_state state=09 way=3: expected=09 actual=%d", get_next_states( 9)(3)) assert(get_next_states( 9)(4) === 1.U(plru.nBits.W), s"get_next_state state=09 way=4: expected=01 actual=%d", get_next_states( 9)(4)) assert(get_next_states(10)(0) === 15.U(plru.nBits.W), s"get_next_state state=10 way=0: expected=15 actual=%d", get_next_states(10)(0)) assert(get_next_states(10)(1) === 14.U(plru.nBits.W), s"get_next_state state=10 way=1: expected=14 actual=%d", get_next_states(10)(1)) assert(get_next_states(10)(2) === 10.U(plru.nBits.W), s"get_next_state state=10 way=2: expected=10 actual=%d", get_next_states(10)(2)) assert(get_next_states(10)(3) === 8.U(plru.nBits.W), s"get_next_state state=10 way=3: expected=08 actual=%d", get_next_states(10)(3)) assert(get_next_states(10)(4) === 2.U(plru.nBits.W), s"get_next_state state=10 way=4: expected=02 actual=%d", get_next_states(10)(4)) assert(get_next_states(11)(0) === 15.U(plru.nBits.W), s"get_next_state state=11 way=0: expected=15 actual=%d", get_next_states(11)(0)) assert(get_next_states(11)(1) === 14.U(plru.nBits.W), s"get_next_state state=11 way=1: expected=14 actual=%d", get_next_states(11)(1)) assert(get_next_states(11)(2) === 11.U(plru.nBits.W), s"get_next_state state=11 way=2: expected=11 actual=%d", get_next_states(11)(2)) assert(get_next_states(11)(3) === 9.U(plru.nBits.W), s"get_next_state state=11 way=3: expected=09 actual=%d", get_next_states(11)(3)) assert(get_next_states(11)(4) === 3.U(plru.nBits.W), s"get_next_state state=11 way=4: expected=03 actual=%d", get_next_states(11)(4)) assert(get_next_states(12)(0) === 13.U(plru.nBits.W), s"get_next_state state=12 way=0: expected=13 actual=%d", get_next_states(12)(0)) assert(get_next_states(12)(1) === 12.U(plru.nBits.W), s"get_next_state state=12 way=1: expected=12 actual=%d", get_next_states(12)(1)) assert(get_next_states(12)(2) === 10.U(plru.nBits.W), s"get_next_state state=12 way=2: expected=10 actual=%d", get_next_states(12)(2)) assert(get_next_states(12)(3) === 8.U(plru.nBits.W), s"get_next_state state=12 way=3: expected=08 actual=%d", get_next_states(12)(3)) assert(get_next_states(12)(4) === 4.U(plru.nBits.W), s"get_next_state state=12 way=4: expected=04 actual=%d", get_next_states(12)(4)) assert(get_next_states(13)(0) === 13.U(plru.nBits.W), s"get_next_state state=13 way=0: expected=13 actual=%d", get_next_states(13)(0)) assert(get_next_states(13)(1) === 12.U(plru.nBits.W), s"get_next_state state=13 way=1: expected=12 actual=%d", get_next_states(13)(1)) assert(get_next_states(13)(2) === 11.U(plru.nBits.W), s"get_next_state state=13 way=2: expected=11 actual=%d", get_next_states(13)(2)) assert(get_next_states(13)(3) === 9.U(plru.nBits.W), s"get_next_state state=13 way=3: expected=09 actual=%d", get_next_states(13)(3)) assert(get_next_states(13)(4) === 5.U(plru.nBits.W), s"get_next_state state=13 way=4: expected=05 actual=%d", get_next_states(13)(4)) assert(get_next_states(14)(0) === 15.U(plru.nBits.W), s"get_next_state state=14 way=0: expected=15 actual=%d", get_next_states(14)(0)) assert(get_next_states(14)(1) === 14.U(plru.nBits.W), s"get_next_state state=14 way=1: expected=14 actual=%d", get_next_states(14)(1)) assert(get_next_states(14)(2) === 10.U(plru.nBits.W), s"get_next_state state=14 way=2: expected=10 actual=%d", get_next_states(14)(2)) assert(get_next_states(14)(3) === 8.U(plru.nBits.W), s"get_next_state state=14 way=3: expected=08 actual=%d", get_next_states(14)(3)) assert(get_next_states(14)(4) === 6.U(plru.nBits.W), s"get_next_state state=14 way=4: expected=06 actual=%d", get_next_states(14)(4)) assert(get_next_states(15)(0) === 15.U(plru.nBits.W), s"get_next_state state=15 way=0: expected=15 actual=%d", get_next_states(15)(0)) assert(get_next_states(15)(1) === 14.U(plru.nBits.W), s"get_next_state state=15 way=5: expected=14 actual=%d", get_next_states(15)(1)) assert(get_next_states(15)(2) === 11.U(plru.nBits.W), s"get_next_state state=15 way=2: expected=11 actual=%d", get_next_states(15)(2)) assert(get_next_states(15)(3) === 9.U(plru.nBits.W), s"get_next_state state=15 way=3: expected=09 actual=%d", get_next_states(15)(3)) assert(get_next_states(15)(4) === 7.U(plru.nBits.W), s"get_next_state state=15 way=4: expected=07 actual=%d", get_next_states(15)(4)) } case 6 => { assert(get_replace_ways( 0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=00: expected=0 actual=%d", get_replace_ways( 0)) assert(get_replace_ways( 1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=01: expected=1 actual=%d", get_replace_ways( 1)) assert(get_replace_ways( 2) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=02: expected=0 actual=%d", get_replace_ways( 2)) assert(get_replace_ways( 3) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=03: expected=1 actual=%d", get_replace_ways( 3)) assert(get_replace_ways( 4) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=04: expected=2 actual=%d", get_replace_ways( 4)) assert(get_replace_ways( 5) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=05: expected=2 actual=%d", get_replace_ways( 5)) assert(get_replace_ways( 6) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=06: expected=3 actual=%d", get_replace_ways( 6)) assert(get_replace_ways( 7) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=07: expected=3 actual=%d", get_replace_ways( 7)) assert(get_replace_ways( 8) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=08: expected=0 actual=%d", get_replace_ways( 8)) assert(get_replace_ways( 9) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=09: expected=1 actual=%d", get_replace_ways( 9)) assert(get_replace_ways(10) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=10: expected=0 actual=%d", get_replace_ways(10)) assert(get_replace_ways(11) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=11: expected=1 actual=%d", get_replace_ways(11)) assert(get_replace_ways(12) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=12: expected=2 actual=%d", get_replace_ways(12)) assert(get_replace_ways(13) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=13: expected=2 actual=%d", get_replace_ways(13)) assert(get_replace_ways(14) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=14: expected=3 actual=%d", get_replace_ways(14)) assert(get_replace_ways(15) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=15: expected=3 actual=%d", get_replace_ways(15)) assert(get_replace_ways(16) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=16: expected=4 actual=%d", get_replace_ways(16)) assert(get_replace_ways(17) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=17: expected=4 actual=%d", get_replace_ways(17)) assert(get_replace_ways(18) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=18: expected=4 actual=%d", get_replace_ways(18)) assert(get_replace_ways(19) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=19: expected=4 actual=%d", get_replace_ways(19)) assert(get_replace_ways(20) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=20: expected=4 actual=%d", get_replace_ways(20)) assert(get_replace_ways(21) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=21: expected=4 actual=%d", get_replace_ways(21)) assert(get_replace_ways(22) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=22: expected=4 actual=%d", get_replace_ways(22)) assert(get_replace_ways(23) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=23: expected=4 actual=%d", get_replace_ways(23)) assert(get_replace_ways(24) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=24: expected=5 actual=%d", get_replace_ways(24)) assert(get_replace_ways(25) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=25: expected=5 actual=%d", get_replace_ways(25)) assert(get_replace_ways(26) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=26: expected=5 actual=%d", get_replace_ways(26)) assert(get_replace_ways(27) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=27: expected=5 actual=%d", get_replace_ways(27)) assert(get_replace_ways(28) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=28: expected=5 actual=%d", get_replace_ways(28)) assert(get_replace_ways(29) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=29: expected=5 actual=%d", get_replace_ways(29)) assert(get_replace_ways(30) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=30: expected=5 actual=%d", get_replace_ways(30)) assert(get_replace_ways(31) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=31: expected=5 actual=%d", get_replace_ways(31)) } case _ => throw new IllegalArgumentException(s"no test pattern found for n_ways=$n_ways") } } File Consts.scala: // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket.constants import chisel3._ import chisel3.util._ import freechips.rocketchip.util._ trait ScalarOpConstants { val SZ_BR = 3 def BR_X = BitPat("b???") def BR_EQ = 0.U(3.W) def BR_NE = 1.U(3.W) def BR_J = 2.U(3.W) def BR_N = 3.U(3.W) def BR_LT = 4.U(3.W) def BR_GE = 5.U(3.W) def BR_LTU = 6.U(3.W) def BR_GEU = 7.U(3.W) def A1_X = BitPat("b??") def A1_ZERO = 0.U(2.W) def A1_RS1 = 1.U(2.W) def A1_PC = 2.U(2.W) def A1_RS1SHL = 3.U(2.W) def IMM_X = BitPat("b???") def IMM_S = 0.U(3.W) def IMM_SB = 1.U(3.W) def IMM_U = 2.U(3.W) def IMM_UJ = 3.U(3.W) def IMM_I = 4.U(3.W) def IMM_Z = 5.U(3.W) def A2_X = BitPat("b???") def A2_ZERO = 0.U(3.W) def A2_SIZE = 1.U(3.W) def A2_RS2 = 2.U(3.W) def A2_IMM = 3.U(3.W) def A2_RS2OH = 4.U(3.W) def A2_IMMOH = 5.U(3.W) def X = BitPat("b?") def N = BitPat("b0") def Y = BitPat("b1") val SZ_DW = 1 def DW_X = X def DW_32 = false.B def DW_64 = true.B def DW_XPR = DW_64 } trait MemoryOpConstants { val NUM_XA_OPS = 9 val M_SZ = 5 def M_X = BitPat("b?????"); def M_XRD = "b00000".U; // int load def M_XWR = "b00001".U; // int store def M_PFR = "b00010".U; // prefetch with intent to read def M_PFW = "b00011".U; // prefetch with intent to write def M_XA_SWAP = "b00100".U def M_FLUSH_ALL = "b00101".U // flush all lines def M_XLR = "b00110".U def M_XSC = "b00111".U def M_XA_ADD = "b01000".U def M_XA_XOR = "b01001".U def M_XA_OR = "b01010".U def M_XA_AND = "b01011".U def M_XA_MIN = "b01100".U def M_XA_MAX = "b01101".U def M_XA_MINU = "b01110".U def M_XA_MAXU = "b01111".U def M_FLUSH = "b10000".U // write back dirty data and cede R/W permissions def M_PWR = "b10001".U // partial (masked) store def M_PRODUCE = "b10010".U // write back dirty data and cede W permissions def M_CLEAN = "b10011".U // write back dirty data and retain R/W permissions def M_SFENCE = "b10100".U // SFENCE.VMA def M_HFENCEV = "b10101".U // HFENCE.VVMA def M_HFENCEG = "b10110".U // HFENCE.GVMA def M_WOK = "b10111".U // check write permissions but don't perform a write def M_HLVX = "b10000".U // HLVX instruction def isAMOLogical(cmd: UInt) = cmd.isOneOf(M_XA_SWAP, M_XA_XOR, M_XA_OR, M_XA_AND) def isAMOArithmetic(cmd: UInt) = cmd.isOneOf(M_XA_ADD, M_XA_MIN, M_XA_MAX, M_XA_MINU, M_XA_MAXU) def isAMO(cmd: UInt) = isAMOLogical(cmd) \|\| isAMOArithmetic(cmd) def isPrefetch(cmd: UInt) = cmd === M_PFR \|\| cmd === M_PFW def isRead(cmd: UInt) = cmd.isOneOf(M_XRD, M_HLVX, M_XLR, M_XSC) \|\| isAMO(cmd) def isWrite(cmd: UInt) = cmd === M_XWR \|\| cmd === M_PWR \|\| cmd === M_XSC \|\| isAMO(cmd) def isWriteIntent(cmd: UInt) = isWrite(cmd) \|\| cmd === M_PFW \|\| cmd === M_XLR } File TLB.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import freechips.rocketchip.devices.debug.DebugModuleKey import freechips.rocketchip.diplomacy.RegionType import freechips.rocketchip.subsystem.CacheBlockBytes import freechips.rocketchip.tile.{CoreModule, CoreBundle} import freechips.rocketchip.tilelink._ import freechips.rocketchip.util.{OptimizationBarrier, SetAssocLRU, PseudoLRU, PopCountAtLeast, property} import freechips.rocketchip.util.BooleanToAugmentedBoolean import freechips.rocketchip.util.IntToAugmentedInt import freechips.rocketchip.util.UIntToAugmentedUInt import freechips.rocketchip.util.UIntIsOneOf import freechips.rocketchip.util.SeqToAugmentedSeq import freechips.rocketchip.util.SeqBoolBitwiseOps case object ASIdBits extends Field[Int](0) case object VMIdBits extends Field[Int](0) /* =SFENCE= * rs1 rs2 * {{{ * 0 0 -> flush All * 0 1 -> flush by ASID * 1 1 -> flush by ADDR * 1 0 -> flush by ADDR and ASID * }}} * {{{ * If rs1=x0 and rs2=x0, the fence orders all reads and writes made to any level of the page tables, for all address spaces. * If rs1=x0 and rs2!=x0, the fence orders all reads and writes made to any level of the page tables, but only for the address space identified by integer register rs2. Accesses to global mappings (see Section 4.3.1) are not ordered. * If rs1!=x0 and rs2=x0, the fence orders only reads and writes made to the leaf page table entry corresponding to the virtual address in rs1, for all address spaces. * If rs1!=x0 and rs2!=x0, the fence orders only reads and writes made to the leaf page table entry corresponding to the virtual address in rs1, for the address space identified by integer register rs2. Accesses to global mappings are not ordered. * }}} / class SFenceReq(implicit p: Parameters) extends CoreBundle()(p) { val rs1 = Bool() val rs2 = Bool() val addr = UInt(vaddrBits.W) val asid = UInt((asIdBits max 1).W) // TODO zero-width val hv = Bool() val hg = Bool() } class TLBReq(lgMaxSize: Int)(implicit p: Parameters) extends CoreBundle()(p) { /* request address from CPU. / val vaddr = UInt(vaddrBitsExtended.W) /* don't lookup TLB, bypass vaddr as paddr / val passthrough = Bool() /* granularity / val size = UInt(log2Ceil(lgMaxSize + 1).W) /* memory command. / val cmd = Bits(M_SZ.W) val prv = UInt(PRV.SZ.W) /* virtualization mode / val v = Bool() } class TLBExceptions extends Bundle { val ld = Bool() val st = Bool() val inst = Bool() } class TLBResp(lgMaxSize: Int = 3)(implicit p: Parameters) extends CoreBundle()(p) { // lookup responses val miss = Bool() /* physical address / val paddr = UInt(paddrBits.W) val gpa = UInt(vaddrBitsExtended.W) val gpa_is_pte = Bool() /* page fault exception / val pf = new TLBExceptions /* guest page fault exception / val gf = new TLBExceptions /* access exception / val ae = new TLBExceptions /* misaligned access exception / val ma = new TLBExceptions /* if this address is cacheable / val cacheable = Bool() /* if caches must allocate this address / val must_alloc = Bool() /* if this address is prefetchable for caches/ val prefetchable = Bool() /* size/cmd of request that generated this response/ val size = UInt(log2Ceil(lgMaxSize + 1).W) val cmd = UInt(M_SZ.W) } class TLBEntryData(implicit p: Parameters) extends CoreBundle()(p) { val ppn = UInt(ppnBits.W) /* pte.u user / val u = Bool() /* pte.g global / val g = Bool() /* access exception. * D$ -> PTW -> TLB AE * Alignment failed. / val ae_ptw = Bool() val ae_final = Bool() val ae_stage2 = Bool() /* page fault / val pf = Bool() /* guest page fault / val gf = Bool() /* supervisor write / val sw = Bool() /* supervisor execute / val sx = Bool() /* supervisor read / val sr = Bool() /* hypervisor write / val hw = Bool() /* hypervisor excute / val hx = Bool() /* hypervisor read / val hr = Bool() /* prot_w / val pw = Bool() /* prot_x / val px = Bool() /* prot_r / val pr = Bool() /* PutPartial / val ppp = Bool() /* AMO logical / val pal = Bool() /* AMO arithmetic / val paa = Bool() /* get/put effects / val eff = Bool() /* cacheable / val c = Bool() /* fragmented_superpage support / val fragmented_superpage = Bool() } /* basic cell for TLB data / class TLBEntry(val nSectors: Int, val superpage: Boolean, val superpageOnly: Boolean)(implicit p: Parameters) extends CoreBundle()(p) { require(nSectors == 1 \|\| !superpage) require(!superpageOnly \|\| superpage) val level = UInt(log2Ceil(pgLevels).W) /* use vpn as tag / val tag_vpn = UInt(vpnBits.W) /* tag in vitualization mode / val tag_v = Bool() /* entry data / val data = Vec(nSectors, UInt(new TLBEntryData().getWidth.W)) /* valid bit / val valid = Vec(nSectors, Bool()) /* returns all entry data in this entry / def entry_data = data.map(_.asTypeOf(new TLBEntryData)) /* returns the index of sector / private def sectorIdx(vpn: UInt) = vpn.extract(nSectors.log2-1, 0) /* returns the entry data matched with this vpn/ def getData(vpn: UInt) = OptimizationBarrier(data(sectorIdx(vpn)).asTypeOf(new TLBEntryData)) /* returns whether a sector hits / def sectorHit(vpn: UInt, virtual: Bool) = valid.orR && sectorTagMatch(vpn, virtual) /* returns whether tag matches vpn / def sectorTagMatch(vpn: UInt, virtual: Bool) = (((tag_vpn ^ vpn) >> nSectors.log2) === 0.U) && (tag_v === virtual) /* returns hit signal / def hit(vpn: UInt, virtual: Bool): Bool = { if (superpage && usingVM) { var tagMatch = valid.head && (tag_v === virtual) for (j <- 0 until pgLevels) { val base = (pgLevels - 1 - j) pgLevelBits val n = pgLevelBits + (if (j == 0) hypervisorExtraAddrBits else 0) val ignore = level < j.U \|\| (superpageOnly && j == pgLevels - 1).B tagMatch = tagMatch && (ignore \|\| (tag_vpn ^ vpn)(base + n - 1, base) === 0.U) } tagMatch } else { val idx = sectorIdx(vpn) valid(idx) && sectorTagMatch(vpn, virtual) } } /** returns the ppn of the input TLBEntryData / def ppn(vpn: UInt, data: TLBEntryData) = { val supervisorVPNBits = pgLevels pgLevelBits if (superpage && usingVM) { var res = data.ppn >> pgLevelBits(pgLevels - 1) for (j <- 1 until pgLevels) { val ignore = level < j.U \|\| (superpageOnly && j == pgLevels - 1).B res = Cat(res, (Mux(ignore, vpn, 0.U) \| data.ppn)(supervisorVPNBits - jpgLevelBits - 1, supervisorVPNBits - (j + 1)pgLevelBits)) } res } else { data.ppn } } /* does the refill * * find the target entry with vpn tag * and replace the target entry with the input entry data / def insert(vpn: UInt, virtual: Bool, level: UInt, entry: TLBEntryData): Unit = { this.tag_vpn := vpn this.tag_v := virtual this.level := level.extract(log2Ceil(pgLevels - superpageOnly.toInt)-1, 0) val idx = sectorIdx(vpn) valid(idx) := true.B data(idx) := entry.asUInt } def invalidate(): Unit = { valid.foreach(_ := false.B) } def invalidate(virtual: Bool): Unit = { for ((v, e) <- valid zip entry_data) when (tag_v === virtual) { v := false.B } } def invalidateVPN(vpn: UInt, virtual: Bool): Unit = { if (superpage) { when (hit(vpn, virtual)) { invalidate() } } else { when (sectorTagMatch(vpn, virtual)) { for (((v, e), i) <- (valid zip entry_data).zipWithIndex) when (tag_v === virtual && i.U === sectorIdx(vpn)) { v := false.B } } } // For fragmented superpage mappings, we assume the worst (largest) // case, and zap entries whose most-significant VPNs match when (((tag_vpn ^ vpn) >> (pgLevelBits (pgLevels - 1))) === 0.U) { for ((v, e) <- valid zip entry_data) when (tag_v === virtual && e.fragmented_superpage) { v := false.B } } } def invalidateNonGlobal(virtual: Bool): Unit = { for ((v, e) <- valid zip entry_data) when (tag_v === virtual && !e.g) { v := false.B } } } /** TLB config * * @param nSets the number of sets of PTE, follow [[ICacheParams.nSets]] * @param nWays the total number of wayss of PTE, follow [[ICacheParams.nWays]] * @param nSectors the number of ways in a single PTE TLBEntry * @param nSuperpageEntries the number of SuperpageEntries / case class TLBConfig( nSets: Int, nWays: Int, nSectors: Int = 4, nSuperpageEntries: Int = 4) /* =Overview= * [[TLB]] is a TLB template which contains PMA logic and PMP checker. * * TLB caches PTE and accelerates the address translation process. * When tlb miss happens, ask PTW(L2TLB) for Page Table Walk. * Perform PMP and PMA check during the translation and throw exception if there were any. * * ==Cache Structure== * - Sectored Entry (PTE) * - set-associative or direct-mapped * - nsets = [[TLBConfig.nSets]] * - nways = [[TLBConfig.nWays]] / [[TLBConfig.nSectors]] * - PTEEntry( sectors = [[TLBConfig.nSectors]] ) * - LRU(if set-associative) * * - Superpage Entry(superpage PTE) * - fully associative * - nsets = [[TLBConfig.nSuperpageEntries]] * - PTEEntry(sectors = 1) * - PseudoLRU * * - Special Entry(PTE across PMP) * - nsets = 1 * - PTEEntry(sectors = 1) * * ==Address structure== * {{{ * \|vaddr \| * \|ppn/vpn \| pgIndex \| * \| \| \| * \| \|nSets \|nSector \| \|}}} * * ==State Machine== * {{{ * s_ready: ready to accept request from CPU. * s_request: when L1TLB(this) miss, send request to PTW(L2TLB), . * s_wait: wait for PTW to refill L1TLB. * s_wait_invalidate: L1TLB is waiting for respond from PTW, but L1TLB will invalidate respond from PTW.}}} * * ==PMP== * pmp check * - special_entry: always check * - other entry: check on refill * * ==Note== * PMA consume diplomacy parameter generate physical memory address checking logic * * Boom use Rocket ITLB, and its own DTLB. * * Accelerators:{{{ * sha3: DTLB * gemmini: DTLB * hwacha: DTLB2+ITLB}}} @param instruction true for ITLB, false for DTLB * @param lgMaxSize @todo seems granularity * @param cfg [[TLBConfig]] * @param edge collect SoC metadata. / class TLB(instruction: Boolean, lgMaxSize: Int, cfg: TLBConfig)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(p) { override def desiredName = if (instruction) "ITLB" else "DTLB" val io = IO(new Bundle { /* request from Core / val req = Flipped(Decoupled(new TLBReq(lgMaxSize))) /* response to Core / val resp = Output(new TLBResp(lgMaxSize)) /* SFence Input / val sfence = Flipped(Valid(new SFenceReq)) /* IO to PTW / val ptw = new TLBPTWIO /* suppress a TLB refill, one cycle after a miss / val kill = Input(Bool()) }) io.ptw.customCSRs := DontCare val pageGranularityPMPs = pmpGranularity >= (1 << pgIdxBits) val vpn = io.req.bits.vaddr(vaddrBits-1, pgIdxBits) /* index for sectored_Entry / val memIdx = vpn.extract(cfg.nSectors.log2 + cfg.nSets.log2 - 1, cfg.nSectors.log2) /* TLB Entry / val sectored_entries = Reg(Vec(cfg.nSets, Vec(cfg.nWays / cfg.nSectors, new TLBEntry(cfg.nSectors, false, false)))) /* Superpage Entry / val superpage_entries = Reg(Vec(cfg.nSuperpageEntries, new TLBEntry(1, true, true))) /* Special Entry * * If PMP granularity is less than page size, thus need additional "special" entry manage PMP. / val special_entry = (!pageGranularityPMPs).option(Reg(new TLBEntry(1, true, false))) def ordinary_entries = sectored_entries(memIdx) ++ superpage_entries def all_entries = ordinary_entries ++ special_entry def all_real_entries = sectored_entries.flatten ++ superpage_entries ++ special_entry val s_ready :: s_request :: s_wait :: s_wait_invalidate :: Nil = Enum(4) val state = RegInit(s_ready) // use vpn as refill_tag val r_refill_tag = Reg(UInt(vpnBits.W)) val r_superpage_repl_addr = Reg(UInt(log2Ceil(superpage_entries.size).W)) val r_sectored_repl_addr = Reg(UInt(log2Ceil(sectored_entries.head.size).W)) val r_sectored_hit = Reg(Valid(UInt(log2Ceil(sectored_entries.head.size).W))) val r_superpage_hit = Reg(Valid(UInt(log2Ceil(superpage_entries.size).W))) val r_vstage1_en = Reg(Bool()) val r_stage2_en = Reg(Bool()) val r_need_gpa = Reg(Bool()) val r_gpa_valid = Reg(Bool()) val r_gpa = Reg(UInt(vaddrBits.W)) val r_gpa_vpn = Reg(UInt(vpnBits.W)) val r_gpa_is_pte = Reg(Bool()) /* privilege mode / val priv = io.req.bits.prv val priv_v = usingHypervisor.B && io.req.bits.v val priv_s = priv(0) // user mode and supervisor mode val priv_uses_vm = priv <= PRV.S.U val satp = Mux(priv_v, io.ptw.vsatp, io.ptw.ptbr) val stage1_en = usingVM.B && satp.mode(satp.mode.getWidth-1) /* VS-stage translation enable / val vstage1_en = usingHypervisor.B && priv_v && io.ptw.vsatp.mode(io.ptw.vsatp.mode.getWidth-1) /* G-stage translation enable / val stage2_en = usingHypervisor.B && priv_v && io.ptw.hgatp.mode(io.ptw.hgatp.mode.getWidth-1) /* Enable Virtual Memory when: * 1. statically configured * 1. satp highest bits enabled * i. RV32: * - 0 -> Bare * - 1 -> SV32 * i. RV64: * - 0000 -> Bare * - 1000 -> SV39 * - 1001 -> SV48 * - 1010 -> SV57 * - 1011 -> SV64 * 1. In virtualization mode, vsatp highest bits enabled * 1. priv mode in U and S. * 1. in H & M mode, disable VM. * 1. no passthrough(micro-arch defined.) * * @see RV-priv spec 4.1.11 Supervisor Address Translation and Protection (satp) Register * @see RV-priv spec 8.2.18 Virtual Supervisor Address Translation and Protection Register (vsatp) / val vm_enabled = (stage1_en \|\| stage2_en) && priv_uses_vm && !io.req.bits.passthrough // flush guest entries on vsatp.MODE Bare <-> SvXX transitions val v_entries_use_stage1 = RegInit(false.B) val vsatp_mode_mismatch = priv_v && (vstage1_en =/= v_entries_use_stage1) && !io.req.bits.passthrough // share a single physical memory attribute checker (unshare if critical path) val refill_ppn = io.ptw.resp.bits.pte.ppn(ppnBits-1, 0) /* refill signal / val do_refill = usingVM.B && io.ptw.resp.valid /* sfence invalidate refill / val invalidate_refill = state.isOneOf(s_request / don't care /, s_wait_invalidate) \|\| io.sfence.valid // PMP val mpu_ppn = Mux(do_refill, refill_ppn, Mux(vm_enabled && special_entry.nonEmpty.B, special_entry.map(e => e.ppn(vpn, e.getData(vpn))).getOrElse(0.U), io.req.bits.vaddr >> pgIdxBits)) val mpu_physaddr = Cat(mpu_ppn, io.req.bits.vaddr(pgIdxBits-1, 0)) val mpu_priv = Mux[UInt](usingVM.B && (do_refill \|\| io.req.bits.passthrough / PTW /), PRV.S.U, Cat(io.ptw.status.debug, priv)) val pmp = Module(new PMPChecker(lgMaxSize)) pmp.io.addr := mpu_physaddr pmp.io.size := io.req.bits.size pmp.io.pmp := (io.ptw.pmp: Seq[PMP]) pmp.io.prv := mpu_priv val pma = Module(new PMAChecker(edge.manager)(p)) pma.io.paddr := mpu_physaddr // todo: using DataScratchpad doesn't support cacheable. val cacheable = pma.io.resp.cacheable && (instruction \|\| !usingDataScratchpad).B val homogeneous = TLBPageLookup(edge.manager.managers, xLen, p(CacheBlockBytes), BigInt(1) << pgIdxBits, 1 << lgMaxSize)(mpu_physaddr).homogeneous // In M mode, if access DM address(debug module program buffer) val deny_access_to_debug = mpu_priv <= PRV.M.U && p(DebugModuleKey).map(dmp => dmp.address.contains(mpu_physaddr)).getOrElse(false.B) val prot_r = pma.io.resp.r && !deny_access_to_debug && pmp.io.r val prot_w = pma.io.resp.w && !deny_access_to_debug && pmp.io.w val prot_pp = pma.io.resp.pp val prot_al = pma.io.resp.al val prot_aa = pma.io.resp.aa val prot_x = pma.io.resp.x && !deny_access_to_debug && pmp.io.x val prot_eff = pma.io.resp.eff // hit check val sector_hits = sectored_entries(memIdx).map(_.sectorHit(vpn, priv_v)) val superpage_hits = superpage_entries.map(_.hit(vpn, priv_v)) val hitsVec = all_entries.map(vm_enabled && _.hit(vpn, priv_v)) val real_hits = hitsVec.asUInt val hits = Cat(!vm_enabled, real_hits) // use ptw response to refill // permission bit arrays when (do_refill) { val pte = io.ptw.resp.bits.pte val refill_v = r_vstage1_en \|\| r_stage2_en val newEntry = Wire(new TLBEntryData) newEntry.ppn := pte.ppn newEntry.c := cacheable newEntry.u := pte.u newEntry.g := pte.g && pte.v newEntry.ae_ptw := io.ptw.resp.bits.ae_ptw newEntry.ae_final := io.ptw.resp.bits.ae_final newEntry.ae_stage2 := io.ptw.resp.bits.ae_final && io.ptw.resp.bits.gpa_is_pte && r_stage2_en newEntry.pf := io.ptw.resp.bits.pf newEntry.gf := io.ptw.resp.bits.gf newEntry.hr := io.ptw.resp.bits.hr newEntry.hw := io.ptw.resp.bits.hw newEntry.hx := io.ptw.resp.bits.hx newEntry.sr := pte.sr() newEntry.sw := pte.sw() newEntry.sx := pte.sx() newEntry.pr := prot_r newEntry.pw := prot_w newEntry.px := prot_x newEntry.ppp := prot_pp newEntry.pal := prot_al newEntry.paa := prot_aa newEntry.eff := prot_eff newEntry.fragmented_superpage := io.ptw.resp.bits.fragmented_superpage // refill special_entry when (special_entry.nonEmpty.B && !io.ptw.resp.bits.homogeneous) { special_entry.foreach(_.insert(r_refill_tag, refill_v, io.ptw.resp.bits.level, newEntry)) }.elsewhen (io.ptw.resp.bits.level < (pgLevels-1).U) { val waddr = Mux(r_superpage_hit.valid && usingHypervisor.B, r_superpage_hit.bits, r_superpage_repl_addr) for ((e, i) <- superpage_entries.zipWithIndex) when (r_superpage_repl_addr === i.U) { e.insert(r_refill_tag, refill_v, io.ptw.resp.bits.level, newEntry) when (invalidate_refill) { e.invalidate() } } // refill sectored_hit }.otherwise { val r_memIdx = r_refill_tag.extract(cfg.nSectors.log2 + cfg.nSets.log2 - 1, cfg.nSectors.log2) val waddr = Mux(r_sectored_hit.valid, r_sectored_hit.bits, r_sectored_repl_addr) for ((e, i) <- sectored_entries(r_memIdx).zipWithIndex) when (waddr === i.U) { when (!r_sectored_hit.valid) { e.invalidate() } e.insert(r_refill_tag, refill_v, 0.U, newEntry) when (invalidate_refill) { e.invalidate() } } } r_gpa_valid := io.ptw.resp.bits.gpa.valid r_gpa := io.ptw.resp.bits.gpa.bits r_gpa_is_pte := io.ptw.resp.bits.gpa_is_pte } // get all entries data. val entries = all_entries.map(_.getData(vpn)) val normal_entries = entries.take(ordinary_entries.size) // parallel query PPN from [[all_entries]], if VM not enabled return VPN instead val ppn = Mux1H(hitsVec :+ !vm_enabled, (all_entries zip entries).map{ case (entry, data) => entry.ppn(vpn, data) } :+ vpn(ppnBits-1, 0)) val nPhysicalEntries = 1 + special_entry.size // generally PTW misaligned load exception. val ptw_ae_array = Cat(false.B, entries.map(_.ae_ptw).asUInt) val final_ae_array = Cat(false.B, entries.map(_.ae_final).asUInt) val ptw_pf_array = Cat(false.B, entries.map(_.pf).asUInt) val ptw_gf_array = Cat(false.B, entries.map(_.gf).asUInt) val sum = Mux(priv_v, io.ptw.gstatus.sum, io.ptw.status.sum) // if in hypervisor/machine mode, cannot read/write user entries. // if in superviosr/user mode, "If the SUM bit in the sstatus register is set, supervisor mode software may also access pages with U=1.(from spec)" val priv_rw_ok = Mux(!priv_s \|\| sum, entries.map(_.u).asUInt, 0.U) \| Mux(priv_s, ~entries.map(_.u).asUInt, 0.U) // if in hypervisor/machine mode, other than user pages, all pages are executable. // if in superviosr/user mode, only user page can execute. val priv_x_ok = Mux(priv_s, ~entries.map(_.u).asUInt, entries.map(_.u).asUInt) val stage1_bypass = Fill(entries.size, usingHypervisor.B) & (Fill(entries.size, !stage1_en) \| entries.map(_.ae_stage2).asUInt) val mxr = io.ptw.status.mxr \| Mux(priv_v, io.ptw.gstatus.mxr, false.B) // "The vsstatus field MXR, which makes execute-only pages readable, only overrides VS-stage page protection.(from spec)" val r_array = Cat(true.B, (priv_rw_ok & (entries.map(_.sr).asUInt \| Mux(mxr, entries.map(_.sx).asUInt, 0.U))) \| stage1_bypass) val w_array = Cat(true.B, (priv_rw_ok & entries.map(_.sw).asUInt) \| stage1_bypass) val x_array = Cat(true.B, (priv_x_ok & entries.map(_.sx).asUInt) \| stage1_bypass) val stage2_bypass = Fill(entries.size, !stage2_en) val hr_array = Cat(true.B, entries.map(_.hr).asUInt \| Mux(io.ptw.status.mxr, entries.map(_.hx).asUInt, 0.U) \| stage2_bypass) val hw_array = Cat(true.B, entries.map(_.hw).asUInt \| stage2_bypass) val hx_array = Cat(true.B, entries.map(_.hx).asUInt \| stage2_bypass) // These array is for each TLB entries. // user mode can read: PMA OK, TLB OK, AE OK val pr_array = Cat(Fill(nPhysicalEntries, prot_r), normal_entries.map(_.pr).asUInt) & ~(ptw_ae_array \| final_ae_array) // user mode can write: PMA OK, TLB OK, AE OK val pw_array = Cat(Fill(nPhysicalEntries, prot_w), normal_entries.map(_.pw).asUInt) & ~(ptw_ae_array \| final_ae_array) // user mode can write: PMA OK, TLB OK, AE OK val px_array = Cat(Fill(nPhysicalEntries, prot_x), normal_entries.map(_.px).asUInt) & ~(ptw_ae_array \| final_ae_array) // put effect val eff_array = Cat(Fill(nPhysicalEntries, prot_eff), normal_entries.map(_.eff).asUInt) // cacheable val c_array = Cat(Fill(nPhysicalEntries, cacheable), normal_entries.map(_.c).asUInt) // put partial val ppp_array = Cat(Fill(nPhysicalEntries, prot_pp), normal_entries.map(_.ppp).asUInt) // atomic arithmetic val paa_array = Cat(Fill(nPhysicalEntries, prot_aa), normal_entries.map(_.paa).asUInt) // atomic logic val pal_array = Cat(Fill(nPhysicalEntries, prot_al), normal_entries.map(_.pal).asUInt) val ppp_array_if_cached = ppp_array \| c_array val paa_array_if_cached = paa_array \| (if(usingAtomicsInCache) c_array else 0.U) val pal_array_if_cached = pal_array \| (if(usingAtomicsInCache) c_array else 0.U) val prefetchable_array = Cat((cacheable && homogeneous) << (nPhysicalEntries-1), normal_entries.map(_.c).asUInt) // vaddr misaligned: vaddr[1:0]=b00 val misaligned = (io.req.bits.vaddr & (UIntToOH(io.req.bits.size) - 1.U)).orR def badVA(guestPA: Boolean): Bool = { val additionalPgLevels = (if (guestPA) io.ptw.hgatp else satp).additionalPgLevels val extraBits = if (guestPA) hypervisorExtraAddrBits else 0 val signed = !guestPA val nPgLevelChoices = pgLevels - minPgLevels + 1 val minVAddrBits = pgIdxBits + minPgLevels pgLevelBits + extraBits (for (i <- 0 until nPgLevelChoices) yield { val mask = ((BigInt(1) << vaddrBitsExtended) - (BigInt(1) << (minVAddrBits + i * pgLevelBits - signed.toInt))).U val maskedVAddr = io.req.bits.vaddr & mask additionalPgLevels === i.U && !(maskedVAddr === 0.U \|\| signed.B && maskedVAddr === mask) }).orR } val bad_gpa = if (!usingHypervisor) false.B else vm_enabled && !stage1_en && badVA(true) val bad_va = if (!usingVM \|\| (minPgLevels == pgLevels && vaddrBits == vaddrBitsExtended)) false.B else vm_enabled && stage1_en && badVA(false) val cmd_lrsc = usingAtomics.B && io.req.bits.cmd.isOneOf(M_XLR, M_XSC) val cmd_amo_logical = usingAtomics.B && isAMOLogical(io.req.bits.cmd) val cmd_amo_arithmetic = usingAtomics.B && isAMOArithmetic(io.req.bits.cmd) val cmd_put_partial = io.req.bits.cmd === M_PWR val cmd_read = isRead(io.req.bits.cmd) val cmd_readx = usingHypervisor.B && io.req.bits.cmd === M_HLVX val cmd_write = isWrite(io.req.bits.cmd) val cmd_write_perms = cmd_write \|\| io.req.bits.cmd.isOneOf(M_FLUSH_ALL, M_WOK) // not a write, but needs write permissions val lrscAllowed = Mux((usingDataScratchpad \|\| usingAtomicsOnlyForIO).B, 0.U, c_array) val ae_array = Mux(misaligned, eff_array, 0.U) \| Mux(cmd_lrsc, ~lrscAllowed, 0.U) // access exception needs SoC information from PMA val ae_ld_array = Mux(cmd_read, ae_array \| ~pr_array, 0.U) val ae_st_array = Mux(cmd_write_perms, ae_array \| ~pw_array, 0.U) \| Mux(cmd_put_partial, ~ppp_array_if_cached, 0.U) \| Mux(cmd_amo_logical, ~pal_array_if_cached, 0.U) \| Mux(cmd_amo_arithmetic, ~paa_array_if_cached, 0.U) val must_alloc_array = Mux(cmd_put_partial, ~ppp_array, 0.U) \| Mux(cmd_amo_logical, ~pal_array, 0.U) \| Mux(cmd_amo_arithmetic, ~paa_array, 0.U) \| Mux(cmd_lrsc, ~0.U(pal_array.getWidth.W), 0.U) val pf_ld_array = Mux(cmd_read, ((~Mux(cmd_readx, x_array, r_array) & ~ptw_ae_array) \| ptw_pf_array) & ~ptw_gf_array, 0.U) val pf_st_array = Mux(cmd_write_perms, ((~w_array & ~ptw_ae_array) \| ptw_pf_array) & ~ptw_gf_array, 0.U) val pf_inst_array = ((~x_array & ~ptw_ae_array) \| ptw_pf_array) & ~ptw_gf_array val gf_ld_array = Mux(priv_v && cmd_read, (~Mux(cmd_readx, hx_array, hr_array) \| ptw_gf_array) & ~ptw_ae_array, 0.U) val gf_st_array = Mux(priv_v && cmd_write_perms, (~hw_array \| ptw_gf_array) & ~ptw_ae_array, 0.U) val gf_inst_array = Mux(priv_v, (~hx_array \| ptw_gf_array) & ~ptw_ae_array, 0.U) val gpa_hits = { val need_gpa_mask = if (instruction) gf_inst_array else gf_ld_array \| gf_st_array val hit_mask = Fill(ordinary_entries.size, r_gpa_valid && r_gpa_vpn === vpn) \| Fill(all_entries.size, !vstage1_en) hit_mask \| ~need_gpa_mask(all_entries.size-1, 0) } val tlb_hit_if_not_gpa_miss = real_hits.orR val tlb_hit = (real_hits & gpa_hits).orR // leads to s_request val tlb_miss = vm_enabled && !vsatp_mode_mismatch && !bad_va && !tlb_hit val sectored_plru = new SetAssocLRU(cfg.nSets, sectored_entries.head.size, "plru") val superpage_plru = new PseudoLRU(superpage_entries.size) when (io.req.valid && vm_enabled) { // replace when (sector_hits.orR) { sectored_plru.access(memIdx, OHToUInt(sector_hits)) } when (superpage_hits.orR) { superpage_plru.access(OHToUInt(superpage_hits)) } } // Superpages create the possibility that two entries in the TLB may match. // This corresponds to a software bug, but we can't return complete garbage; // we must return either the old translation or the new translation. This // isn't compatible with the Mux1H approach. So, flush the TLB and report // a miss on duplicate entries. val multipleHits = PopCountAtLeast(real_hits, 2) // only pull up req.ready when this is s_ready state. io.req.ready := state === s_ready // page fault io.resp.pf.ld := (bad_va && cmd_read) \|\| (pf_ld_array & hits).orR io.resp.pf.st := (bad_va && cmd_write_perms) \|\| (pf_st_array & hits).orR io.resp.pf.inst := bad_va \|\| (pf_inst_array & hits).orR // guest page fault io.resp.gf.ld := (bad_gpa && cmd_read) \|\| (gf_ld_array & hits).orR io.resp.gf.st := (bad_gpa && cmd_write_perms) \|\| (gf_st_array & hits).orR io.resp.gf.inst := bad_gpa \|\| (gf_inst_array & hits).orR // access exception io.resp.ae.ld := (ae_ld_array & hits).orR io.resp.ae.st := (ae_st_array & hits).orR io.resp.ae.inst := (~px_array & hits).orR // misaligned io.resp.ma.ld := misaligned && cmd_read io.resp.ma.st := misaligned && cmd_write io.resp.ma.inst := false.B // this is up to the pipeline to figure out io.resp.cacheable := (c_array & hits).orR io.resp.must_alloc := (must_alloc_array & hits).orR io.resp.prefetchable := (prefetchable_array & hits).orR && edge.manager.managers.forall(m => !m.supportsAcquireB \|\| m.supportsHint).B io.resp.miss := do_refill \|\| vsatp_mode_mismatch \|\| tlb_miss \|\| multipleHits io.resp.paddr := Cat(ppn, io.req.bits.vaddr(pgIdxBits-1, 0)) io.resp.size := io.req.bits.size io.resp.cmd := io.req.bits.cmd io.resp.gpa_is_pte := vstage1_en && r_gpa_is_pte io.resp.gpa := { val page = Mux(!vstage1_en, Cat(bad_gpa, vpn), r_gpa >> pgIdxBits) val offset = Mux(io.resp.gpa_is_pte, r_gpa(pgIdxBits-1, 0), io.req.bits.vaddr(pgIdxBits-1, 0)) Cat(page, offset) } io.ptw.req.valid := state === s_request io.ptw.req.bits.valid := !io.kill io.ptw.req.bits.bits.addr := r_refill_tag io.ptw.req.bits.bits.vstage1 := r_vstage1_en io.ptw.req.bits.bits.stage2 := r_stage2_en io.ptw.req.bits.bits.need_gpa := r_need_gpa if (usingVM) { when(io.ptw.req.fire && io.ptw.req.bits.valid) { r_gpa_valid := false.B r_gpa_vpn := r_refill_tag } val sfence = io.sfence.valid // this is [[s_ready]] // handle miss/hit at the first cycle. // if miss, request PTW(L2TLB). when (io.req.fire && tlb_miss) { state := s_request r_refill_tag := vpn r_need_gpa := tlb_hit_if_not_gpa_miss r_vstage1_en := vstage1_en r_stage2_en := stage2_en r_superpage_repl_addr := replacementEntry(superpage_entries, superpage_plru.way) r_sectored_repl_addr := replacementEntry(sectored_entries(memIdx), sectored_plru.way(memIdx)) r_sectored_hit.valid := sector_hits.orR r_sectored_hit.bits := OHToUInt(sector_hits) r_superpage_hit.valid := superpage_hits.orR r_superpage_hit.bits := OHToUInt(superpage_hits) } // Handle SFENCE.VMA when send request to PTW. // SFENCE.VMA io.ptw.req.ready kill // ? ? 1 // 0 0 0 // 0 1 0 -> s_wait // 1 0 0 -> s_wait_invalidate // 1 0 0 -> s_ready when (state === s_request) { // SFENCE.VMA will kill TLB entries based on rs1 and rs2. It will take 1 cycle. when (sfence) { state := s_ready } // here should be io.ptw.req.fire, but assert(io.ptw.req.ready === true.B) // fire -> s_wait when (io.ptw.req.ready) { state := Mux(sfence, s_wait_invalidate, s_wait) } // If CPU kills request(frontend.s2_redirect) when (io.kill) { state := s_ready } } // sfence in refill will results in invalidate when (state === s_wait && sfence) { state := s_wait_invalidate } // after CPU acquire response, go back to s_ready. when (io.ptw.resp.valid) { state := s_ready } // SFENCE processing logic. when (sfence) { assert(!io.sfence.bits.rs1 \|\| (io.sfence.bits.addr >> pgIdxBits) === vpn) for (e <- all_real_entries) { val hv = usingHypervisor.B && io.sfence.bits.hv val hg = usingHypervisor.B && io.sfence.bits.hg when (!hg && io.sfence.bits.rs1) { e.invalidateVPN(vpn, hv) } .elsewhen (!hg && io.sfence.bits.rs2) { e.invalidateNonGlobal(hv) } .otherwise { e.invalidate(hv \|\| hg) } } } when(io.req.fire && vsatp_mode_mismatch) { all_real_entries.foreach(_.invalidate(true.B)) v_entries_use_stage1 := vstage1_en } when (multipleHits \|\| reset.asBool) { all_real_entries.foreach(_.invalidate()) } ccover(io.ptw.req.fire, "MISS", "TLB miss") ccover(io.ptw.req.valid && !io.ptw.req.ready, "PTW_STALL", "TLB miss, but PTW busy") ccover(state === s_wait_invalidate, "SFENCE_DURING_REFILL", "flush TLB during TLB refill") ccover(sfence && !io.sfence.bits.rs1 && !io.sfence.bits.rs2, "SFENCE_ALL", "flush TLB") ccover(sfence && !io.sfence.bits.rs1 && io.sfence.bits.rs2, "SFENCE_ASID", "flush TLB ASID") ccover(sfence && io.sfence.bits.rs1 && !io.sfence.bits.rs2, "SFENCE_LINE", "flush TLB line") ccover(sfence && io.sfence.bits.rs1 && io.sfence.bits.rs2, "SFENCE_LINE_ASID", "flush TLB line/ASID") ccover(multipleHits, "MULTIPLE_HITS", "Two matching translations in TLB") } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = property.cover(cond, s"${if (instruction) "I" else "D"}TLB_$label", "MemorySystem;;" + desc) /** Decides which entry to be replaced * * If there is a invalid entry, replace it with priorityencoder; * if not, replace the alt entry * * @return mask for TLBEntry replacement / def replacementEntry(set: Seq[TLBEntry], alt: UInt) = { val valids = set.map(_.valid.orR).asUInt Mux(valids.andR, alt, PriorityEncoder(~valids)) } } File TLBPermissions.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes, RegionType, AddressDecoder} import freechips.rocketchip.tilelink.TLManagerParameters case class TLBPermissions( homogeneous: Bool, // if false, the below are undefined r: Bool, // readable w: Bool, // writeable x: Bool, // executable c: Bool, // cacheable a: Bool, // arithmetic ops l: Bool) // logical ops object TLBPageLookup { private case class TLBFixedPermissions( e: Boolean, // get-/put-effects r: Boolean, // readable w: Boolean, // writeable x: Boolean, // executable c: Boolean, // cacheable a: Boolean, // arithmetic ops l: Boolean) { // logical ops val useful = r \|\| w \|\| x \|\| c \|\| a \|\| l } private def groupRegions(managers: Seq[TLManagerParameters]): Map[TLBFixedPermissions, Seq[AddressSet]] = { val permissions = managers.map { m => (m.address, TLBFixedPermissions( e = Seq(RegionType.PUT_EFFECTS, RegionType.GET_EFFECTS) contains m.regionType, r = m.supportsGet \|\| m.supportsAcquireB, // if cached, never uses Get w = m.supportsPutFull \|\| m.supportsAcquireT, // if cached, never uses Put x = m.executable, c = m.supportsAcquireB, a = m.supportsArithmetic, l = m.supportsLogical)) } permissions .filter(_._2.useful) // get rid of no-permission devices .groupBy(_._2) // group by permission type .mapValues(seq => AddressSet.unify(seq.flatMap(_._1))) // coalesce same-permission regions .toMap } // Unmapped memory is considered to be inhomogeneous def apply(managers: Seq[TLManagerParameters], xLen: Int, cacheBlockBytes: Int, pageSize: BigInt, maxRequestBytes: Int): UInt => TLBPermissions = { require (isPow2(xLen) && xLen >= 8) require (isPow2(cacheBlockBytes) && cacheBlockBytes >= xLen/8) require (isPow2(pageSize) && pageSize >= cacheBlockBytes) val xferSizes = TransferSizes(cacheBlockBytes, cacheBlockBytes) val allSizes = TransferSizes(1, maxRequestBytes) val amoSizes = TransferSizes(4, xLen/8) val permissions = managers.foreach { m => require (!m.supportsGet \|\| m.supportsGet .contains(allSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsGet} Get, but must support ${allSizes}") require (!m.supportsPutFull \|\| m.supportsPutFull .contains(allSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsPutFull} PutFull, but must support ${allSizes}") require (!m.supportsPutPartial \|\| m.supportsPutPartial.contains(allSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsPutPartial} PutPartial, but must support ${allSizes}") require (!m.supportsAcquireB \|\| m.supportsAcquireB .contains(xferSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsAcquireB} AcquireB, but must support ${xferSizes}") require (!m.supportsAcquireT \|\| m.supportsAcquireT .contains(xferSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsAcquireT} AcquireT, but must support ${xferSizes}") require (!m.supportsLogical \|\| m.supportsLogical .contains(amoSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsLogical} Logical, but must support ${amoSizes}") require (!m.supportsArithmetic \|\| m.supportsArithmetic.contains(amoSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsArithmetic} Arithmetic, but must support ${amoSizes}") require (!(m.supportsAcquireB && m.supportsPutFull && !m.supportsAcquireT), s"Memory region '${m.name}' supports AcquireB (cached read) and PutFull (un-cached write) but not AcquireT (cached write)") } val grouped = groupRegions(managers) .mapValues(_.filter(_.alignment >= pageSize)) // discard any region that's not big enough def lowCostProperty(prop: TLBFixedPermissions => Boolean): UInt => Bool = { val (yesm, nom) = grouped.partition { case (k, eq) => prop(k) } val (yes, no) = (yesm.values.flatten.toList, nom.values.flatten.toList) // Find the minimal bits needed to distinguish between yes and no val decisionMask = AddressDecoder(Seq(yes, no)) def simplify(x: Seq[AddressSet]) = AddressSet.unify(x.map(_.widen(~decisionMask)).distinct) val (yesf, nof) = (simplify(yes), simplify(no)) if (yesf.size < no.size) { (x: UInt) => yesf.map(_.contains(x)).foldLeft(false.B)(_ \|\| _) } else { (x: UInt) => !nof.map(_.contains(x)).foldLeft(false.B)(_ \|\| _) } } // Derive simplified property circuits (don't care when !homo) val rfn = lowCostProperty(_.r) val wfn = lowCostProperty(_.w) val xfn = lowCostProperty(_.x) val cfn = lowCostProperty(_.c) val afn = lowCostProperty(_.a) val lfn = lowCostProperty(_.l) val homo = AddressSet.unify(grouped.values.flatten.toList) (x: UInt) => TLBPermissions( homogeneous = homo.map(_.contains(x)).foldLeft(false.B)(_ \|\| _), r = rfn(x), w = wfn(x), x = xfn(x), c = cfn(x), a = afn(x), l = lfn(x)) } // Are all pageSize intervals of mapped regions homogeneous? def homogeneous(managers: Seq[TLManagerParameters], pageSize: BigInt): Boolean = { groupRegions(managers).values.forall(_.forall(_.alignment >= pageSize)) } } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /* Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File PTW.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.{Arbiter, Cat, Decoupled, Enum, Mux1H, OHToUInt, PopCount, PriorityEncoder, PriorityEncoderOH, RegEnable, UIntToOH, Valid, is, isPow2, log2Ceil, switch} import chisel3.withClock import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.subsystem.CacheBlockBytes import freechips.rocketchip.tile._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property import scala.collection.mutable.ListBuffer /* PTE request from TLB to PTW * * TLB send a PTE request to PTW when L1TLB miss / class PTWReq(implicit p: Parameters) extends CoreBundle()(p) { val addr = UInt(vpnBits.W) val need_gpa = Bool() val vstage1 = Bool() val stage2 = Bool() } /* PTE info from L2TLB to TLB * * containing: target PTE, exceptions, two-satge tanslation info / class PTWResp(implicit p: Parameters) extends CoreBundle()(p) { /* ptw access exception / val ae_ptw = Bool() /* final access exception / val ae_final = Bool() /* page fault / val pf = Bool() /* guest page fault / val gf = Bool() /* hypervisor read / val hr = Bool() /* hypervisor write / val hw = Bool() /* hypervisor execute / val hx = Bool() /* PTE to refill L1TLB * * source: L2TLB / val pte = new PTE /* pte pglevel / val level = UInt(log2Ceil(pgLevels).W) /* fragmented_superpage support / val fragmented_superpage = Bool() /* homogeneous for both pma and pmp / val homogeneous = Bool() val gpa = Valid(UInt(vaddrBits.W)) val gpa_is_pte = Bool() } /* IO between TLB and PTW * * PTW receives : * - PTE request * - CSRs info * - pmp results from PMP(in TLB) / class TLBPTWIO(implicit p: Parameters) extends CoreBundle()(p) with HasCoreParameters { val req = Decoupled(Valid(new PTWReq)) val resp = Flipped(Valid(new PTWResp)) val ptbr = Input(new PTBR()) val hgatp = Input(new PTBR()) val vsatp = Input(new PTBR()) val status = Input(new MStatus()) val hstatus = Input(new HStatus()) val gstatus = Input(new MStatus()) val pmp = Input(Vec(nPMPs, new PMP)) val customCSRs = Flipped(coreParams.customCSRs) } /* PTW performance statistics / class PTWPerfEvents extends Bundle { val l2miss = Bool() val l2hit = Bool() val pte_miss = Bool() val pte_hit = Bool() } /* Datapath IO between PTW and Core * * PTW receives CSRs info, pmp checks, sfence instruction info * * PTW sends its performance statistics to core / class DatapathPTWIO(implicit p: Parameters) extends CoreBundle()(p) with HasCoreParameters { val ptbr = Input(new PTBR()) val hgatp = Input(new PTBR()) val vsatp = Input(new PTBR()) val sfence = Flipped(Valid(new SFenceReq)) val status = Input(new MStatus()) val hstatus = Input(new HStatus()) val gstatus = Input(new MStatus()) val pmp = Input(Vec(nPMPs, new PMP)) val perf = Output(new PTWPerfEvents()) val customCSRs = Flipped(coreParams.customCSRs) /* enable clock generated by ptw / val clock_enabled = Output(Bool()) } /* PTE template for transmission * * contains useful methods to check PTE attributes * @see RV-priv spec 4.3.1 for pgae table entry format / class PTE(implicit p: Parameters) extends CoreBundle()(p) { val reserved_for_future = UInt(10.W) val ppn = UInt(44.W) val reserved_for_software = Bits(2.W) /* dirty bit / val d = Bool() /* access bit / val a = Bool() /* global mapping / val g = Bool() /* user mode accessible / val u = Bool() /* whether the page is executable / val x = Bool() /* whether the page is writable / val w = Bool() /* whether the page is readable / val r = Bool() /* valid bit / val v = Bool() /* return true if find a pointer to next level page table / def table(dummy: Int = 0) = v && !r && !w && !x && !d && !a && !u && reserved_for_future === 0.U /* return true if find a leaf PTE / def leaf(dummy: Int = 0) = v && (r \|\| (x && !w)) && a /* user read / def ur(dummy: Int = 0) = sr() && u /* user write/ def uw(dummy: Int = 0) = sw() && u /* user execute / def ux(dummy: Int = 0) = sx() && u /* supervisor read / def sr(dummy: Int = 0) = leaf() && r /* supervisor write / def sw(dummy: Int = 0) = leaf() && w && d /* supervisor execute / def sx(dummy: Int = 0) = leaf() && x /* full permission: writable and executable in user mode / def isFullPerm(dummy: Int = 0) = uw() && ux() } /* L2TLB PTE template * * contains tag bits * @param nSets number of sets in L2TLB * @see RV-priv spec 4.3.1 for page table entry format / class L2TLBEntry(nSets: Int)(implicit p: Parameters) extends CoreBundle()(p) with HasCoreParameters { val idxBits = log2Ceil(nSets) val tagBits = maxSVAddrBits - pgIdxBits - idxBits + (if (usingHypervisor) 1 else 0) val tag = UInt(tagBits.W) val ppn = UInt(ppnBits.W) /* dirty bit / val d = Bool() /* access bit / val a = Bool() /* user mode accessible / val u = Bool() /* whether the page is executable / val x = Bool() /* whether the page is writable / val w = Bool() /* whether the page is readable / val r = Bool() } /* PTW contains L2TLB, and performs page table walk for high level TLB, and cache queries from L1 TLBs(I$, D$, RoCC) * * It performs hierarchy page table query to mem for the desired leaf PTE and cache them in l2tlb. * Besides leaf PTEs, it also caches non-leaf PTEs in pte_cache to accerlerate the process. * * ==Structure== * - l2tlb : for leaf PTEs * - set-associative (configurable with [[CoreParams.nL2TLBEntries]]and [[CoreParams.nL2TLBWays]])) * - PLRU * - pte_cache: for non-leaf PTEs * - set-associative * - LRU * - s2_pte_cache: for non-leaf PTEs in 2-stage translation * - set-associative * - PLRU * * l2tlb Pipeline: 3 stage * {{{ * stage 0 : read * stage 1 : decode * stage 2 : hit check * }}} * ==State Machine== * s_ready: ready to reveive request from TLB * s_req: request mem; pte_cache hit judge * s_wait1: deal with l2tlb error * s_wait2: final hit judge * s_wait3: receive mem response * s_fragment_superpage: for superpage PTE * * @note l2tlb hit happens in s_req or s_wait1 * @see RV-priv spec 4.3-4.6 for Virtual-Memory System * @see RV-priv spec 8.5 for Two-Stage Address Translation * @todo details in two-stage translation / class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(p) { val io = IO(new Bundle { /* to n TLB / val requestor = Flipped(Vec(n, new TLBPTWIO)) /* to HellaCache / val mem = new HellaCacheIO /* to Core * * contains CSRs info and performance statistics / val dpath = new DatapathPTWIO }) val s_ready :: s_req :: s_wait1 :: s_dummy1 :: s_wait2 :: s_wait3 :: s_dummy2 :: s_fragment_superpage :: Nil = Enum(8) val state = RegInit(s_ready) val l2_refill_wire = Wire(Bool()) /* Arbiter to arbite request from n TLB / val arb = Module(new Arbiter(Valid(new PTWReq), n)) // use TLB req as arbitor's input arb.io.in <> io.requestor.map(_.req) // receive req only when s_ready and not in refill arb.io.out.ready := (state === s_ready) && !l2_refill_wire val resp_valid = RegNext(VecInit(Seq.fill(io.requestor.size)(false.B))) val clock_en = state =/= s_ready \|\| l2_refill_wire \|\| arb.io.out.valid \|\| io.dpath.sfence.valid \|\| io.dpath.customCSRs.disableDCacheClockGate io.dpath.clock_enabled := usingVM.B && clock_en val gated_clock = if (!usingVM \|\| !tileParams.dcache.get.clockGate) clock else ClockGate(clock, clock_en, "ptw_clock_gate") withClock (gated_clock) { // entering gated-clock domain val invalidated = Reg(Bool()) /* current PTE level * {{{ * 0 <= count <= pgLevel-1 * count = pgLevel - 1 : leaf PTE * count < pgLevel - 1 : non-leaf PTE * }}} / val count = Reg(UInt(log2Ceil(pgLevels).W)) val resp_ae_ptw = Reg(Bool()) val resp_ae_final = Reg(Bool()) val resp_pf = Reg(Bool()) val resp_gf = Reg(Bool()) val resp_hr = Reg(Bool()) val resp_hw = Reg(Bool()) val resp_hx = Reg(Bool()) val resp_fragmented_superpage = Reg(Bool()) /* tlb request / val r_req = Reg(new PTWReq) /* current selected way in arbitor / val r_req_dest = Reg(Bits()) // to respond to L1TLB : l2_hit // to construct mem.req.addr val r_pte = Reg(new PTE) val r_hgatp = Reg(new PTBR) // 2-stage pageLevel val aux_count = Reg(UInt(log2Ceil(pgLevels).W)) /* pte for 2-stage translation / val aux_pte = Reg(new PTE) val gpa_pgoff = Reg(UInt(pgIdxBits.W)) // only valid in resp_gf case val stage2 = Reg(Bool()) val stage2_final = Reg(Bool()) val satp = Mux(arb.io.out.bits.bits.vstage1, io.dpath.vsatp, io.dpath.ptbr) val r_hgatp_initial_count = pgLevels.U - minPgLevels.U - r_hgatp.additionalPgLevels /* 2-stage translation both enable / val do_both_stages = r_req.vstage1 && r_req.stage2 val max_count = count max aux_count val vpn = Mux(r_req.vstage1 && stage2, aux_pte.ppn, r_req.addr) val mem_resp_valid = RegNext(io.mem.resp.valid) val mem_resp_data = RegNext(io.mem.resp.bits.data) io.mem.uncached_resp.map { resp => assert(!(resp.valid && io.mem.resp.valid)) resp.ready := true.B when (resp.valid) { mem_resp_valid := true.B mem_resp_data := resp.bits.data } } // construct pte from mem.resp val (pte, invalid_paddr, invalid_gpa) = { val tmp = mem_resp_data.asTypeOf(new PTE()) val res = WireDefault(tmp) res.ppn := Mux(do_both_stages && !stage2, tmp.ppn(vpnBits.min(tmp.ppn.getWidth)-1, 0), tmp.ppn(ppnBits-1, 0)) when (tmp.r \|\| tmp.w \|\| tmp.x) { // for superpage mappings, make sure PPN LSBs are zero for (i <- 0 until pgLevels-1) when (count <= i.U && tmp.ppn((pgLevels-1-i)pgLevelBits-1, (pgLevels-2-i)pgLevelBits) =/= 0.U) { res.v := false.B } } (res, Mux(do_both_stages && !stage2, (tmp.ppn >> vpnBits) =/= 0.U, (tmp.ppn >> ppnBits) =/= 0.U), do_both_stages && !stage2 && checkInvalidHypervisorGPA(r_hgatp, tmp.ppn)) } // find non-leaf PTE, need traverse val traverse = pte.table() && !invalid_paddr && !invalid_gpa && count < (pgLevels-1).U /* address send to mem for enquerry / val pte_addr = if (!usingVM) 0.U else { val vpn_idxs = (0 until pgLevels).map { i => val width = pgLevelBits + (if (i <= pgLevels - minPgLevels) hypervisorExtraAddrBits else 0) (vpn >> (pgLevels - i - 1) pgLevelBits)(width - 1, 0) } val mask = Mux(stage2 && count === r_hgatp_initial_count, ((1 << (hypervisorExtraAddrBits + pgLevelBits)) - 1).U, ((1 << pgLevelBits) - 1).U) val vpn_idx = vpn_idxs(count) & mask val raw_pte_addr = ((r_pte.ppn << pgLevelBits) \| vpn_idx) << log2Ceil(xLen / 8) val size = if (usingHypervisor) vaddrBits else paddrBits //use r_pte.ppn as page table base address //use vpn slice as offset raw_pte_addr.apply(size.min(raw_pte_addr.getWidth) - 1, 0) } /** stage2_pte_cache input addr / val stage2_pte_cache_addr = if (!usingHypervisor) 0.U else { val vpn_idxs = (0 until pgLevels - 1).map { i => (r_req.addr >> (pgLevels - i - 1) pgLevelBits)(pgLevelBits - 1, 0) } val vpn_idx = vpn_idxs(aux_count) val raw_s2_pte_cache_addr = Cat(aux_pte.ppn, vpn_idx) << log2Ceil(xLen / 8) raw_s2_pte_cache_addr(vaddrBits.min(raw_s2_pte_cache_addr.getWidth) - 1, 0) } def makeFragmentedSuperpagePPN(ppn: UInt): Seq[UInt] = { (pgLevels-1 until 0 by -1).map(i => Cat(ppn >> (pgLevelBitsi), r_req.addr(((pgLevelBitsi) min vpnBits)-1, 0).padTo(pgLevelBitsi))) } /* PTECache caches non-leaf PTE * @param s2 true: 2-stage address translation / def makePTECache(s2: Boolean): (Bool, UInt) = if (coreParams.nPTECacheEntries == 0) { (false.B, 0.U) } else { val plru = new PseudoLRU(coreParams.nPTECacheEntries) val valid = RegInit(0.U(coreParams.nPTECacheEntries.W)) val tags = Reg(Vec(coreParams.nPTECacheEntries, UInt((if (usingHypervisor) 1 + vaddrBits else paddrBits).W))) // not include full pte, only ppn val data = Reg(Vec(coreParams.nPTECacheEntries, UInt((if (usingHypervisor && s2) vpnBits else ppnBits).W))) val can_hit = if (s2) count === r_hgatp_initial_count && aux_count < (pgLevels-1).U && r_req.vstage1 && stage2 && !stage2_final else count < (pgLevels-1).U && Mux(r_req.vstage1, stage2, !r_req.stage2) val can_refill = if (s2) do_both_stages && !stage2 && !stage2_final else can_hit val tag = if (s2) Cat(true.B, stage2_pte_cache_addr.padTo(vaddrBits)) else Cat(r_req.vstage1, pte_addr.padTo(if (usingHypervisor) vaddrBits else paddrBits)) val hits = tags.map(_ === tag).asUInt & valid val hit = hits.orR && can_hit // refill with mem response when (mem_resp_valid && traverse && can_refill && !hits.orR && !invalidated) { val r = Mux(valid.andR, plru.way, PriorityEncoder(~valid)) valid := valid \| UIntToOH(r) tags(r) := tag data(r) := pte.ppn plru.access(r) } // replace when (hit && state === s_req) { plru.access(OHToUInt(hits)) } when (io.dpath.sfence.valid && (!io.dpath.sfence.bits.rs1 \|\| usingHypervisor.B && io.dpath.sfence.bits.hg)) { valid := 0.U } val lcount = if (s2) aux_count else count for (i <- 0 until pgLevels-1) { ccover(hit && state === s_req && lcount === i.U, s"PTE_CACHE_HIT_L$i", s"PTE cache hit, level $i") } (hit, Mux1H(hits, data)) } // generate pte_cache val (pte_cache_hit, pte_cache_data) = makePTECache(false) // generate pte_cache with 2-stage translation val (stage2_pte_cache_hit, stage2_pte_cache_data) = makePTECache(true) // pte_cache hit or 2-stage pte_cache hit val pte_hit = RegNext(false.B) io.dpath.perf.pte_miss := false.B io.dpath.perf.pte_hit := pte_hit && (state === s_req) && !io.dpath.perf.l2hit assert(!(io.dpath.perf.l2hit && (io.dpath.perf.pte_miss \|\| io.dpath.perf.pte_hit)), "PTE Cache Hit/Miss Performance Monitor Events are lower priority than L2TLB Hit event") // l2_refill happens when find the leaf pte val l2_refill = RegNext(false.B) l2_refill_wire := l2_refill io.dpath.perf.l2miss := false.B io.dpath.perf.l2hit := false.B // l2tlb val (l2_hit, l2_error, l2_pte, l2_tlb_ram) = if (coreParams.nL2TLBEntries == 0) (false.B, false.B, WireDefault(0.U.asTypeOf(new PTE)), None) else { val code = new ParityCode require(isPow2(coreParams.nL2TLBEntries)) require(isPow2(coreParams.nL2TLBWays)) require(coreParams.nL2TLBEntries >= coreParams.nL2TLBWays) val nL2TLBSets = coreParams.nL2TLBEntries / coreParams.nL2TLBWays require(isPow2(nL2TLBSets)) val idxBits = log2Ceil(nL2TLBSets) val l2_plru = new SetAssocLRU(nL2TLBSets, coreParams.nL2TLBWays, "plru") val ram = DescribedSRAM( name = "l2_tlb_ram", desc = "L2 TLB", size = nL2TLBSets, data = Vec(coreParams.nL2TLBWays, UInt(code.width(new L2TLBEntry(nL2TLBSets).getWidth).W)) ) val g = Reg(Vec(coreParams.nL2TLBWays, UInt(nL2TLBSets.W))) val valid = RegInit(VecInit(Seq.fill(coreParams.nL2TLBWays)(0.U(nL2TLBSets.W)))) // use r_req to construct tag val (r_tag, r_idx) = Split(Cat(r_req.vstage1, r_req.addr(maxSVAddrBits-pgIdxBits-1, 0)), idxBits) /* the valid vec for the selected set(including n ways) / val r_valid_vec = valid.map(_(r_idx)).asUInt val r_valid_vec_q = Reg(UInt(coreParams.nL2TLBWays.W)) val r_l2_plru_way = Reg(UInt(log2Ceil(coreParams.nL2TLBWays max 1).W)) r_valid_vec_q := r_valid_vec // replacement way r_l2_plru_way := (if (coreParams.nL2TLBWays > 1) l2_plru.way(r_idx) else 0.U) // refill with r_pte(leaf pte) when (l2_refill && !invalidated) { val entry = Wire(new L2TLBEntry(nL2TLBSets)) entry.ppn := r_pte.ppn entry.d := r_pte.d entry.a := r_pte.a entry.u := r_pte.u entry.x := r_pte.x entry.w := r_pte.w entry.r := r_pte.r entry.tag := r_tag // if all the way are valid, use plru to select one way to be replaced, // otherwise use PriorityEncoderOH to select one val wmask = if (coreParams.nL2TLBWays > 1) Mux(r_valid_vec_q.andR, UIntToOH(r_l2_plru_way, coreParams.nL2TLBWays), PriorityEncoderOH(~r_valid_vec_q)) else 1.U(1.W) ram.write(r_idx, VecInit(Seq.fill(coreParams.nL2TLBWays)(code.encode(entry.asUInt))), wmask.asBools) val mask = UIntToOH(r_idx) for (way <- 0 until coreParams.nL2TLBWays) { when (wmask(way)) { valid(way) := valid(way) \| mask g(way) := Mux(r_pte.g, g(way) \| mask, g(way) & ~mask) } } } // sfence happens when (io.dpath.sfence.valid) { val hg = usingHypervisor.B && io.dpath.sfence.bits.hg for (way <- 0 until coreParams.nL2TLBWays) { valid(way) := Mux(!hg && io.dpath.sfence.bits.rs1, valid(way) & ~UIntToOH(io.dpath.sfence.bits.addr(idxBits+pgIdxBits-1, pgIdxBits)), Mux(!hg && io.dpath.sfence.bits.rs2, valid(way) & g(way), 0.U)) } } val s0_valid = !l2_refill && arb.io.out.fire val s0_suitable = arb.io.out.bits.bits.vstage1 === arb.io.out.bits.bits.stage2 && !arb.io.out.bits.bits.need_gpa val s1_valid = RegNext(s0_valid && s0_suitable && arb.io.out.bits.valid) val s2_valid = RegNext(s1_valid) // read from tlb idx val s1_rdata = ram.read(arb.io.out.bits.bits.addr(idxBits-1, 0), s0_valid) val s2_rdata = s1_rdata.map(s1_rdway => code.decode(RegEnable(s1_rdway, s1_valid))) val s2_valid_vec = RegEnable(r_valid_vec, s1_valid) val s2_g_vec = RegEnable(VecInit(g.map(_(r_idx))), s1_valid) val s2_error = (0 until coreParams.nL2TLBWays).map(way => s2_valid_vec(way) && s2_rdata(way).error).orR when (s2_valid && s2_error) { valid.foreach { _ := 0.U }} // decode val s2_entry_vec = s2_rdata.map(_.uncorrected.asTypeOf(new L2TLBEntry(nL2TLBSets))) val s2_hit_vec = (0 until coreParams.nL2TLBWays).map(way => s2_valid_vec(way) && (r_tag === s2_entry_vec(way).tag)) val s2_hit = s2_valid && s2_hit_vec.orR io.dpath.perf.l2miss := s2_valid && !(s2_hit_vec.orR) io.dpath.perf.l2hit := s2_hit when (s2_hit) { l2_plru.access(r_idx, OHToUInt(s2_hit_vec)) assert((PopCount(s2_hit_vec) === 1.U) \|\| s2_error, "L2 TLB multi-hit") } val s2_pte = Wire(new PTE) val s2_hit_entry = Mux1H(s2_hit_vec, s2_entry_vec) s2_pte.ppn := s2_hit_entry.ppn s2_pte.d := s2_hit_entry.d s2_pte.a := s2_hit_entry.a s2_pte.g := Mux1H(s2_hit_vec, s2_g_vec) s2_pte.u := s2_hit_entry.u s2_pte.x := s2_hit_entry.x s2_pte.w := s2_hit_entry.w s2_pte.r := s2_hit_entry.r s2_pte.v := true.B s2_pte.reserved_for_future := 0.U s2_pte.reserved_for_software := 0.U for (way <- 0 until coreParams.nL2TLBWays) { ccover(s2_hit && s2_hit_vec(way), s"L2_TLB_HIT_WAY$way", s"L2 TLB hit way$way") } (s2_hit, s2_error, s2_pte, Some(ram)) } // if SFENCE occurs during walk, don't refill PTE cache or L2 TLB until next walk invalidated := io.dpath.sfence.valid \|\| (invalidated && state =/= s_ready) // mem request io.mem.keep_clock_enabled := false.B io.mem.req.valid := state === s_req \|\| state === s_dummy1 io.mem.req.bits.phys := true.B io.mem.req.bits.cmd := M_XRD io.mem.req.bits.size := log2Ceil(xLen/8).U io.mem.req.bits.signed := false.B io.mem.req.bits.addr := pte_addr io.mem.req.bits.idx.foreach(_ := pte_addr) io.mem.req.bits.dprv := PRV.S.U // PTW accesses are S-mode by definition io.mem.req.bits.dv := do_both_stages && !stage2 io.mem.req.bits.tag := DontCare io.mem.req.bits.no_resp := false.B io.mem.req.bits.no_alloc := DontCare io.mem.req.bits.no_xcpt := DontCare io.mem.req.bits.data := DontCare io.mem.req.bits.mask := DontCare io.mem.s1_kill := l2_hit \|\| (state =/= s_wait1) \|\| resp_gf io.mem.s1_data := DontCare io.mem.s2_kill := false.B val pageGranularityPMPs = pmpGranularity >= (1 << pgIdxBits) require(!usingHypervisor \|\| pageGranularityPMPs, s"hypervisor requires pmpGranularity >= ${1<<pgIdxBits}") val pmaPgLevelHomogeneous = (0 until pgLevels) map { i => val pgSize = BigInt(1) << (pgIdxBits + ((pgLevels - 1 - i) pgLevelBits)) if (pageGranularityPMPs && i == pgLevels - 1) { require(TLBPageLookup.homogeneous(edge.manager.managers, pgSize), s"All memory regions must be $pgSize-byte aligned") true.B } else { TLBPageLookup(edge.manager.managers, xLen, p(CacheBlockBytes), pgSize, xLen/8)(r_pte.ppn << pgIdxBits).homogeneous } } val pmaHomogeneous = pmaPgLevelHomogeneous(count) val pmpHomogeneous = new PMPHomogeneityChecker(io.dpath.pmp).apply(r_pte.ppn << pgIdxBits, count) val homogeneous = pmaHomogeneous && pmpHomogeneous // response to tlb for (i <- 0 until io.requestor.size) { io.requestor(i).resp.valid := resp_valid(i) io.requestor(i).resp.bits.ae_ptw := resp_ae_ptw io.requestor(i).resp.bits.ae_final := resp_ae_final io.requestor(i).resp.bits.pf := resp_pf io.requestor(i).resp.bits.gf := resp_gf io.requestor(i).resp.bits.hr := resp_hr io.requestor(i).resp.bits.hw := resp_hw io.requestor(i).resp.bits.hx := resp_hx io.requestor(i).resp.bits.pte := r_pte io.requestor(i).resp.bits.level := max_count io.requestor(i).resp.bits.homogeneous := homogeneous \|\| pageGranularityPMPs.B io.requestor(i).resp.bits.fragmented_superpage := resp_fragmented_superpage && pageGranularityPMPs.B io.requestor(i).resp.bits.gpa.valid := r_req.need_gpa io.requestor(i).resp.bits.gpa.bits := Cat(Mux(!stage2_final \|\| !r_req.vstage1 \|\| aux_count === (pgLevels - 1).U, aux_pte.ppn, makeFragmentedSuperpagePPN(aux_pte.ppn)(aux_count)), gpa_pgoff) io.requestor(i).resp.bits.gpa_is_pte := !stage2_final io.requestor(i).ptbr := io.dpath.ptbr io.requestor(i).hgatp := io.dpath.hgatp io.requestor(i).vsatp := io.dpath.vsatp io.requestor(i).customCSRs <> io.dpath.customCSRs io.requestor(i).status := io.dpath.status io.requestor(i).hstatus := io.dpath.hstatus io.requestor(i).gstatus := io.dpath.gstatus io.requestor(i).pmp := io.dpath.pmp } // control state machine val next_state = WireDefault(state) state := OptimizationBarrier(next_state) val do_switch = WireDefault(false.B) switch (state) { is (s_ready) { when (arb.io.out.fire) { val satp_initial_count = pgLevels.U - minPgLevels.U - satp.additionalPgLevels val vsatp_initial_count = pgLevels.U - minPgLevels.U - io.dpath.vsatp.additionalPgLevels val hgatp_initial_count = pgLevels.U - minPgLevels.U - io.dpath.hgatp.additionalPgLevels val aux_ppn = Mux(arb.io.out.bits.bits.vstage1, io.dpath.vsatp.ppn, arb.io.out.bits.bits.addr) r_req := arb.io.out.bits.bits r_req_dest := arb.io.chosen next_state := Mux(arb.io.out.bits.valid, s_req, s_ready) stage2 := arb.io.out.bits.bits.stage2 stage2_final := arb.io.out.bits.bits.stage2 && !arb.io.out.bits.bits.vstage1 count := Mux(arb.io.out.bits.bits.stage2, hgatp_initial_count, satp_initial_count) aux_count := Mux(arb.io.out.bits.bits.vstage1, vsatp_initial_count, 0.U) aux_pte.ppn := aux_ppn aux_pte.reserved_for_future := 0.U resp_ae_ptw := false.B resp_ae_final := false.B resp_pf := false.B resp_gf := checkInvalidHypervisorGPA(io.dpath.hgatp, aux_ppn) && arb.io.out.bits.bits.stage2 resp_hr := true.B resp_hw := true.B resp_hx := true.B resp_fragmented_superpage := false.B r_hgatp := io.dpath.hgatp assert(!arb.io.out.bits.bits.need_gpa \|\| arb.io.out.bits.bits.stage2) } } is (s_req) { when(stage2 && count === r_hgatp_initial_count) { gpa_pgoff := Mux(aux_count === (pgLevels-1).U, r_req.addr << (xLen/8).log2, stage2_pte_cache_addr) } // pte_cache hit when (stage2_pte_cache_hit) { aux_count := aux_count + 1.U aux_pte.ppn := stage2_pte_cache_data aux_pte.reserved_for_future := 0.U pte_hit := true.B }.elsewhen (pte_cache_hit) { count := count + 1.U pte_hit := true.B }.otherwise { next_state := Mux(io.mem.req.ready, s_wait1, s_req) } when(resp_gf) { next_state := s_ready resp_valid(r_req_dest) := true.B } } is (s_wait1) { // This Mux is for the l2_error case; the l2_hit && !l2_error case is overriden below next_state := Mux(l2_hit, s_req, s_wait2) } is (s_wait2) { next_state := s_wait3 io.dpath.perf.pte_miss := count < (pgLevels-1).U when (io.mem.s2_xcpt.ae.ld) { resp_ae_ptw := true.B next_state := s_ready resp_valid(r_req_dest) := true.B } } is (s_fragment_superpage) { next_state := s_ready resp_valid(r_req_dest) := true.B when (!homogeneous) { count := (pgLevels-1).U resp_fragmented_superpage := true.B } when (do_both_stages) { resp_fragmented_superpage := true.B } } } val merged_pte = { val superpage_masks = (0 until pgLevels).map(i => ((BigInt(1) << pte.ppn.getWidth) - (BigInt(1) << (pgLevels-1-i)pgLevelBits)).U) val superpage_mask = superpage_masks(Mux(stage2_final, max_count, (pgLevels-1).U)) val stage1_ppns = (0 until pgLevels-1).map(i => Cat(pte.ppn(pte.ppn.getWidth-1, (pgLevels-i-1)pgLevelBits), aux_pte.ppn((pgLevels-i-1)pgLevelBits-1,0))) :+ pte.ppn val stage1_ppn = stage1_ppns(count) makePTE(stage1_ppn & superpage_mask, aux_pte) } r_pte := OptimizationBarrier( // l2tlb hit->find a leaf PTE(l2_pte), respond to L1TLB Mux(l2_hit && !l2_error && !resp_gf, l2_pte, // S2 PTE cache hit -> proceed to the next level of walking, update the r_pte with hgatp Mux(state === s_req && stage2_pte_cache_hit, makeHypervisorRootPTE(r_hgatp, stage2_pte_cache_data, l2_pte), // pte cache hit->find a non-leaf PTE(pte_cache),continue to request mem Mux(state === s_req && pte_cache_hit, makePTE(pte_cache_data, l2_pte), // 2-stage translation Mux(do_switch, makeHypervisorRootPTE(r_hgatp, pte.ppn, r_pte), // when mem respond, store mem.resp.pte Mux(mem_resp_valid, Mux(!traverse && r_req.vstage1 && stage2, merged_pte, pte), // fragment_superpage Mux(state === s_fragment_superpage && !homogeneous && count =/= (pgLevels - 1).U, makePTE(makeFragmentedSuperpagePPN(r_pte.ppn)(count), r_pte), // when tlb request come->request mem, use root address in satp(or vsatp,hgatp) Mux(arb.io.out.fire, Mux(arb.io.out.bits.bits.stage2, makeHypervisorRootPTE(io.dpath.hgatp, io.dpath.vsatp.ppn, r_pte), makePTE(satp.ppn, r_pte)), r_pte)))))))) when (l2_hit && !l2_error && !resp_gf) { assert(state === s_req \|\| state === s_wait1) next_state := s_ready resp_valid(r_req_dest) := true.B count := (pgLevels-1).U } when (mem_resp_valid) { assert(state === s_wait3) next_state := s_req when (traverse) { when (do_both_stages && !stage2) { do_switch := true.B } count := count + 1.U }.otherwise { val gf = (stage2 && !stage2_final && !pte.ur()) \|\| (pte.leaf() && pte.reserved_for_future === 0.U && invalid_gpa) val ae = pte.v && invalid_paddr val pf = pte.v && pte.reserved_for_future =/= 0.U val success = pte.v && !ae && !pf && !gf when (do_both_stages && !stage2_final && success) { when (stage2) { stage2 := false.B count := aux_count }.otherwise { stage2_final := true.B do_switch := true.B } }.otherwise { // find a leaf pte, start l2 refill l2_refill := success && count === (pgLevels-1).U && !r_req.need_gpa && (!r_req.vstage1 && !r_req.stage2 \|\| do_both_stages && aux_count === (pgLevels-1).U && pte.isFullPerm()) count := max_count when (pageGranularityPMPs.B && !(count === (pgLevels-1).U && (!do_both_stages \|\| aux_count === (pgLevels-1).U))) { next_state := s_fragment_superpage }.otherwise { next_state := s_ready resp_valid(r_req_dest) := true.B } resp_ae_ptw := ae && count < (pgLevels-1).U && pte.table() resp_ae_final := ae && pte.leaf() resp_pf := pf && !stage2 resp_gf := gf \|\| (pf && stage2) resp_hr := !stage2 \|\| (!pf && !gf && pte.ur()) resp_hw := !stage2 \|\| (!pf && !gf && pte.uw()) resp_hx := !stage2 \|\| (!pf && !gf && pte.ux()) } } } when (io.mem.s2_nack) { assert(state === s_wait2) next_state := s_req } when (do_switch) { aux_count := Mux(traverse, count + 1.U, count) count := r_hgatp_initial_count aux_pte := Mux(traverse, pte, { val s1_ppns = (0 until pgLevels-1).map(i => Cat(pte.ppn(pte.ppn.getWidth-1, (pgLevels-i-1)pgLevelBits), r_req.addr(((pgLevels-i-1)pgLevelBits min vpnBits)-1,0).padTo((pgLevels-i-1)pgLevelBits))) :+ pte.ppn makePTE(s1_ppns(count), pte) }) stage2 := true.B } for (i <- 0 until pgLevels) { val leaf = mem_resp_valid && !traverse && count === i.U ccover(leaf && pte.v && !invalid_paddr && !invalid_gpa && pte.reserved_for_future === 0.U, s"L$i", s"successful page-table access, level $i") ccover(leaf && pte.v && invalid_paddr, s"L${i}_BAD_PPN_MSB", s"PPN too large, level $i") ccover(leaf && pte.v && invalid_gpa, s"L${i}_BAD_GPA_MSB", s"GPA too large, level $i") ccover(leaf && pte.v && pte.reserved_for_future =/= 0.U, s"L${i}_BAD_RSV_MSB", s"reserved MSBs set, level $i") ccover(leaf && !mem_resp_data(0), s"L${i}_INVALID_PTE", s"page not present, level $i") if (i != pgLevels-1) ccover(leaf && !pte.v && mem_resp_data(0), s"L${i}_BAD_PPN_LSB", s"PPN LSBs not zero, level $i") } ccover(mem_resp_valid && count === (pgLevels-1).U && pte.table(), s"TOO_DEEP", s"page table too deep") ccover(io.mem.s2_nack, "NACK", "D$ nacked page-table access") ccover(state === s_wait2 && io.mem.s2_xcpt.ae.ld, "AE", "access exception while walking page table") } // leaving gated-clock domain private def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = if (usingVM) property.cover(cond, s"PTW_$label", "MemorySystem;;" + desc) /** Relace PTE.ppn with ppn / private def makePTE(ppn: UInt, default: PTE) = { val pte = WireDefault(default) pte.ppn := ppn pte } /* use hgatp and vpn to construct a new ppn / private def makeHypervisorRootPTE(hgatp: PTBR, vpn: UInt, default: PTE) = { val count = pgLevels.U - minPgLevels.U - hgatp.additionalPgLevels val idxs = (0 to pgLevels-minPgLevels).map(i => (vpn >> (pgLevels-i)pgLevelBits)) val lsbs = WireDefault(UInt(maxHypervisorExtraAddrBits.W), idxs(count)) val pte = WireDefault(default) pte.ppn := Cat(hgatp.ppn >> maxHypervisorExtraAddrBits, lsbs) pte } /** use hgatp and vpn to check for gpa out of range / private def checkInvalidHypervisorGPA(hgatp: PTBR, vpn: UInt) = { val count = pgLevels.U - minPgLevels.U - hgatp.additionalPgLevels val idxs = (0 to pgLevels-minPgLevels).map(i => (vpn >> ((pgLevels-i)pgLevelBits)+maxHypervisorExtraAddrBits)) idxs.extract(count) =/= 0.U } } /** Mix-ins for constructing tiles that might have a PTW */ trait CanHavePTW extends HasTileParameters with HasHellaCache { this: BaseTile => val module: CanHavePTWModule var nPTWPorts = 1 nDCachePorts += usingPTW.toInt } trait CanHavePTWModule extends HasHellaCacheModule { val outer: CanHavePTW val ptwPorts = ListBuffer(outer.dcache.module.io.ptw) val ptw = Module(new PTW(outer.nPTWPorts)(outer.dcache.node.edges.out(0), outer.p)) ptw.io.mem <> DontCare if (outer.usingPTW) { dcachePorts += ptw.io.mem } }	module DTLB_13( // @[TLB.scala:318:7] input clock, // @[TLB.scala:318:7] input reset, // @[TLB.scala:318:7] output io_req_ready, // @[TLB.scala:320:14] input io_req_valid, // @[TLB.scala:320:14] input [39:0] io_req_bits_vaddr, // @[TLB.scala:320:14] input [1:0] io_req_bits_size, // @[TLB.scala:320:14] input [4:0] io_req_bits_cmd, // @[TLB.scala:320:14] output io_resp_miss, // @[TLB.scala:320:14] output [31:0] io_resp_paddr, // @[TLB.scala:320:14] input io_sfence_valid, // @[TLB.scala:320:14] input io_ptw_req_ready, // @[TLB.scala:320:14] output io_ptw_req_valid, // @[TLB.scala:320:14] output [26:0] io_ptw_req_bits_bits_addr, // @[TLB.scala:320:14] output io_ptw_req_bits_bits_need_gpa, // @[TLB.scala:320:14] input io_ptw_resp_valid, // @[TLB.scala:320:14] input io_ptw_resp_bits_ae_ptw, // @[TLB.scala:320:14] input io_ptw_resp_bits_ae_final, // @[TLB.scala:320:14] input io_ptw_resp_bits_pf, // @[TLB.scala:320:14] input io_ptw_resp_bits_gf, // @[TLB.scala:320:14] input io_ptw_resp_bits_hr, // @[TLB.scala:320:14] input io_ptw_resp_bits_hw, // @[TLB.scala:320:14] input io_ptw_resp_bits_hx, // @[TLB.scala:320:14] input [9:0] io_ptw_resp_bits_pte_reserved_for_future, // @[TLB.scala:320:14] input [43:0] io_ptw_resp_bits_pte_ppn, // @[TLB.scala:320:14] input [1:0] io_ptw_resp_bits_pte_reserved_for_software, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_d, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_a, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_g, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_u, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_x, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_w, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_r, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_v, // @[TLB.scala:320:14] input [1:0] io_ptw_resp_bits_level, // @[TLB.scala:320:14] input io_ptw_resp_bits_homogeneous, // @[TLB.scala:320:14] input io_ptw_resp_bits_gpa_valid, // @[TLB.scala:320:14] input [38:0] io_ptw_resp_bits_gpa_bits, // @[TLB.scala:320:14] input io_ptw_resp_bits_gpa_is_pte, // @[TLB.scala:320:14] input [3:0] io_ptw_ptbr_mode, // @[TLB.scala:320:14] input [43:0] io_ptw_ptbr_ppn, // @[TLB.scala:320:14] input io_ptw_status_debug, // @[TLB.scala:320:14] input io_ptw_status_cease, // @[TLB.scala:320:14] input io_ptw_status_wfi, // @[TLB.scala:320:14] input [31:0] io_ptw_status_isa, // @[TLB.scala:320:14] input [1:0] io_ptw_status_dprv, // @[TLB.scala:320:14] input io_ptw_status_dv, // @[TLB.scala:320:14] input [1:0] io_ptw_status_prv, // @[TLB.scala:320:14] input io_ptw_status_v, // @[TLB.scala:320:14] input io_ptw_status_sd, // @[TLB.scala:320:14] input [22:0] io_ptw_status_zero2, // @[TLB.scala:320:14] input io_ptw_status_mpv, // @[TLB.scala:320:14] input io_ptw_status_gva, // @[TLB.scala:320:14] input io_ptw_status_mbe, // @[TLB.scala:320:14] input io_ptw_status_sbe, // @[TLB.scala:320:14] input [1:0] io_ptw_status_sxl, // @[TLB.scala:320:14] input [1:0] io_ptw_status_uxl, // @[TLB.scala:320:14] input io_ptw_status_sd_rv32, // @[TLB.scala:320:14] input [7:0] io_ptw_status_zero1, // @[TLB.scala:320:14] input io_ptw_status_tsr, // @[TLB.scala:320:14] input io_ptw_status_tw, // @[TLB.scala:320:14] input io_ptw_status_tvm, // @[TLB.scala:320:14] input io_ptw_status_mxr, // @[TLB.scala:320:14] input io_ptw_status_sum, // @[TLB.scala:320:14] input io_ptw_status_mprv, // @[TLB.scala:320:14] input [1:0] io_ptw_status_xs, // @[TLB.scala:320:14] input [1:0] io_ptw_status_fs, // @[TLB.scala:320:14] input [1:0] io_ptw_status_mpp, // @[TLB.scala:320:14] input [1:0] io_ptw_status_vs, // @[TLB.scala:320:14] input io_ptw_status_spp, // @[TLB.scala:320:14] input io_ptw_status_mpie, // @[TLB.scala:320:14] input io_ptw_status_ube, // @[TLB.scala:320:14] input io_ptw_status_spie, // @[TLB.scala:320:14] input io_ptw_status_upie, // @[TLB.scala:320:14] input io_ptw_status_mie, // @[TLB.scala:320:14] input io_ptw_status_hie, // @[TLB.scala:320:14] input io_ptw_status_sie, // @[TLB.scala:320:14] input io_ptw_status_uie, // @[TLB.scala:320:14] input io_ptw_hstatus_spvp, // @[TLB.scala:320:14] input io_ptw_hstatus_spv, // @[TLB.scala:320:14] input io_ptw_hstatus_gva, // @[TLB.scala:320:14] input io_ptw_gstatus_debug, // @[TLB.scala:320:14] input io_ptw_gstatus_cease, // @[TLB.scala:320:14] input io_ptw_gstatus_wfi, // @[TLB.scala:320:14] input [31:0] io_ptw_gstatus_isa, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_dprv, // @[TLB.scala:320:14] input io_ptw_gstatus_dv, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_prv, // @[TLB.scala:320:14] input io_ptw_gstatus_v, // @[TLB.scala:320:14] input [22:0] io_ptw_gstatus_zero2, // @[TLB.scala:320:14] input io_ptw_gstatus_mpv, // @[TLB.scala:320:14] input io_ptw_gstatus_gva, // @[TLB.scala:320:14] input io_ptw_gstatus_mbe, // @[TLB.scala:320:14] input io_ptw_gstatus_sbe, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_sxl, // @[TLB.scala:320:14] input [7:0] io_ptw_gstatus_zero1, // @[TLB.scala:320:14] input io_ptw_gstatus_tsr, // @[TLB.scala:320:14] input io_ptw_gstatus_tw, // @[TLB.scala:320:14] input io_ptw_gstatus_tvm, // @[TLB.scala:320:14] input io_ptw_gstatus_mxr, // @[TLB.scala:320:14] input io_ptw_gstatus_sum, // @[TLB.scala:320:14] input io_ptw_gstatus_mprv, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_fs, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_mpp, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_vs, // @[TLB.scala:320:14] input io_ptw_gstatus_spp, // @[TLB.scala:320:14] input io_ptw_gstatus_mpie, // @[TLB.scala:320:14] input io_ptw_gstatus_ube, // @[TLB.scala:320:14] input io_ptw_gstatus_spie, // @[TLB.scala:320:14] input io_ptw_gstatus_upie, // @[TLB.scala:320:14] input io_ptw_gstatus_mie, // @[TLB.scala:320:14] input io_ptw_gstatus_hie, // @[TLB.scala:320:14] input io_ptw_gstatus_sie, // @[TLB.scala:320:14] input io_ptw_gstatus_uie, // @[TLB.scala:320:14] input io_ptw_pmp_0_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_0_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_0_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_0_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_0_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_0_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_0_mask, // @[TLB.scala:320:14] input io_ptw_pmp_1_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_1_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_1_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_1_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_1_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_1_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_1_mask, // @[TLB.scala:320:14] input io_ptw_pmp_2_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_2_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_2_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_2_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_2_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_2_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_2_mask, // @[TLB.scala:320:14] input io_ptw_pmp_3_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_3_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_3_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_3_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_3_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_3_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_3_mask, // @[TLB.scala:320:14] input io_ptw_pmp_4_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_4_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_4_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_4_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_4_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_4_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_4_mask, // @[TLB.scala:320:14] input io_ptw_pmp_5_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_5_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_5_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_5_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_5_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_5_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_5_mask, // @[TLB.scala:320:14] input io_ptw_pmp_6_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_6_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_6_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_6_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_6_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_6_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_6_mask, // @[TLB.scala:320:14] input io_ptw_pmp_7_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_7_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_7_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_7_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_7_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_7_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_7_mask, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_0_ren, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_0_wen, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_0_wdata, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_0_value, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_1_ren, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_1_wen, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_1_wdata, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_1_value, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_2_ren, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_2_wen, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_2_wdata, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_2_value, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_3_ren, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_3_wen, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_3_wdata, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_3_value // @[TLB.scala:320:14] ); wire [19:0] _entries_barrier_5_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_5_io_y_u; // @[package.scala:267:25] wire _entries_barrier_5_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_5_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_5_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_5_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_5_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_5_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_5_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_5_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_5_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_5_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_5_io_y_hr; // @[package.scala:267:25] wire [19:0] _entries_barrier_4_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_4_io_y_u; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_4_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_4_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_4_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_4_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_4_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_px; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_4_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_4_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_4_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_3_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_3_io_y_u; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_3_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_3_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_3_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_3_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_3_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_px; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_3_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_3_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_3_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_2_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_2_io_y_u; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_2_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_2_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_2_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_2_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_2_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_px; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_2_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_2_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_2_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_1_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_1_io_y_u; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_1_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_1_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_1_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_1_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_1_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_px; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_1_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_1_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_1_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_io_y_u; // @[package.scala:267:25] wire _entries_barrier_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_io_y_px; // @[package.scala:267:25] wire _entries_barrier_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_io_y_c; // @[package.scala:267:25] wire _pma_io_resp_r; // @[TLB.scala:422:19] wire _pma_io_resp_w; // @[TLB.scala:422:19] wire _pma_io_resp_pp; // @[TLB.scala:422:19] wire _pma_io_resp_al; // @[TLB.scala:422:19] wire _pma_io_resp_aa; // @[TLB.scala:422:19] wire _pma_io_resp_x; // @[TLB.scala:422:19] wire _pma_io_resp_eff; // @[TLB.scala:422:19] wire _pmp_io_r; // @[TLB.scala:416:19] wire _pmp_io_w; // @[TLB.scala:416:19] wire _pmp_io_x; // @[TLB.scala:416:19] wire [19:0] _mpu_ppn_barrier_io_y_ppn; // @[package.scala:267:25] wire io_req_valid_0 = io_req_valid; // @[TLB.scala:318:7] wire [39:0] io_req_bits_vaddr_0 = io_req_bits_vaddr; // @[TLB.scala:318:7] wire [1:0] io_req_bits_size_0 = io_req_bits_size; // @[TLB.scala:318:7] wire [4:0] io_req_bits_cmd_0 = io_req_bits_cmd; // @[TLB.scala:318:7] wire io_sfence_valid_0 = io_sfence_valid; // @[TLB.scala:318:7] wire io_ptw_req_ready_0 = io_ptw_req_ready; // @[TLB.scala:318:7] wire io_ptw_resp_valid_0 = io_ptw_resp_valid; // @[TLB.scala:318:7] wire io_ptw_resp_bits_ae_ptw_0 = io_ptw_resp_bits_ae_ptw; // @[TLB.scala:318:7] wire io_ptw_resp_bits_ae_final_0 = io_ptw_resp_bits_ae_final; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pf_0 = io_ptw_resp_bits_pf; // @[TLB.scala:318:7] wire io_ptw_resp_bits_gf_0 = io_ptw_resp_bits_gf; // @[TLB.scala:318:7] wire io_ptw_resp_bits_hr_0 = io_ptw_resp_bits_hr; // @[TLB.scala:318:7] wire io_ptw_resp_bits_hw_0 = io_ptw_resp_bits_hw; // @[TLB.scala:318:7] wire io_ptw_resp_bits_hx_0 = io_ptw_resp_bits_hx; // @[TLB.scala:318:7] wire [9:0] io_ptw_resp_bits_pte_reserved_for_future_0 = io_ptw_resp_bits_pte_reserved_for_future; // @[TLB.scala:318:7] wire [43:0] io_ptw_resp_bits_pte_ppn_0 = io_ptw_resp_bits_pte_ppn; // @[TLB.scala:318:7] wire [1:0] io_ptw_resp_bits_pte_reserved_for_software_0 = io_ptw_resp_bits_pte_reserved_for_software; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_d_0 = io_ptw_resp_bits_pte_d; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_a_0 = io_ptw_resp_bits_pte_a; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_g_0 = io_ptw_resp_bits_pte_g; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_u_0 = io_ptw_resp_bits_pte_u; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_x_0 = io_ptw_resp_bits_pte_x; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_w_0 = io_ptw_resp_bits_pte_w; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_r_0 = io_ptw_resp_bits_pte_r; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_v_0 = io_ptw_resp_bits_pte_v; // @[TLB.scala:318:7] wire [1:0] io_ptw_resp_bits_level_0 = io_ptw_resp_bits_level; // @[TLB.scala:318:7] wire io_ptw_resp_bits_homogeneous_0 = io_ptw_resp_bits_homogeneous; // @[TLB.scala:318:7] wire io_ptw_resp_bits_gpa_valid_0 = io_ptw_resp_bits_gpa_valid; // @[TLB.scala:318:7] wire [38:0] io_ptw_resp_bits_gpa_bits_0 = io_ptw_resp_bits_gpa_bits; // @[TLB.scala:318:7] wire io_ptw_resp_bits_gpa_is_pte_0 = io_ptw_resp_bits_gpa_is_pte; // @[TLB.scala:318:7] wire [3:0] io_ptw_ptbr_mode_0 = io_ptw_ptbr_mode; // @[TLB.scala:318:7] wire [43:0] io_ptw_ptbr_ppn_0 = io_ptw_ptbr_ppn; // @[TLB.scala:318:7] wire io_ptw_status_debug_0 = io_ptw_status_debug; // @[TLB.scala:318:7] wire io_ptw_status_cease_0 = io_ptw_status_cease; // @[TLB.scala:318:7] wire io_ptw_status_wfi_0 = io_ptw_status_wfi; // @[TLB.scala:318:7] wire [31:0] io_ptw_status_isa_0 = io_ptw_status_isa; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_dprv_0 = io_ptw_status_dprv; // @[TLB.scala:318:7] wire io_ptw_status_dv_0 = io_ptw_status_dv; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_prv_0 = io_ptw_status_prv; // @[TLB.scala:318:7] wire io_ptw_status_v_0 = io_ptw_status_v; // @[TLB.scala:318:7] wire io_ptw_status_sd_0 = io_ptw_status_sd; // @[TLB.scala:318:7] wire [22:0] io_ptw_status_zero2_0 = io_ptw_status_zero2; // @[TLB.scala:318:7] wire io_ptw_status_mpv_0 = io_ptw_status_mpv; // @[TLB.scala:318:7] wire io_ptw_status_gva_0 = io_ptw_status_gva; // @[TLB.scala:318:7] wire io_ptw_status_mbe_0 = io_ptw_status_mbe; // @[TLB.scala:318:7] wire io_ptw_status_sbe_0 = io_ptw_status_sbe; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_sxl_0 = io_ptw_status_sxl; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_uxl_0 = io_ptw_status_uxl; // @[TLB.scala:318:7] wire io_ptw_status_sd_rv32_0 = io_ptw_status_sd_rv32; // @[TLB.scala:318:7] wire [7:0] io_ptw_status_zero1_0 = io_ptw_status_zero1; // @[TLB.scala:318:7] wire io_ptw_status_tsr_0 = io_ptw_status_tsr; // @[TLB.scala:318:7] wire io_ptw_status_tw_0 = io_ptw_status_tw; // @[TLB.scala:318:7] wire io_ptw_status_tvm_0 = io_ptw_status_tvm; // @[TLB.scala:318:7] wire io_ptw_status_mxr_0 = io_ptw_status_mxr; // @[TLB.scala:318:7] wire io_ptw_status_sum_0 = io_ptw_status_sum; // @[TLB.scala:318:7] wire io_ptw_status_mprv_0 = io_ptw_status_mprv; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_xs_0 = io_ptw_status_xs; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_fs_0 = io_ptw_status_fs; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_mpp_0 = io_ptw_status_mpp; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_vs_0 = io_ptw_status_vs; // @[TLB.scala:318:7] wire io_ptw_status_spp_0 = io_ptw_status_spp; // @[TLB.scala:318:7] wire io_ptw_status_mpie_0 = io_ptw_status_mpie; // @[TLB.scala:318:7] wire io_ptw_status_ube_0 = io_ptw_status_ube; // @[TLB.scala:318:7] wire io_ptw_status_spie_0 = io_ptw_status_spie; // @[TLB.scala:318:7] wire io_ptw_status_upie_0 = io_ptw_status_upie; // @[TLB.scala:318:7] wire io_ptw_status_mie_0 = io_ptw_status_mie; // @[TLB.scala:318:7] wire io_ptw_status_hie_0 = io_ptw_status_hie; // @[TLB.scala:318:7] wire io_ptw_status_sie_0 = io_ptw_status_sie; // @[TLB.scala:318:7] wire io_ptw_status_uie_0 = io_ptw_status_uie; // @[TLB.scala:318:7] wire io_ptw_hstatus_spvp_0 = io_ptw_hstatus_spvp; // @[TLB.scala:318:7] wire io_ptw_hstatus_spv_0 = io_ptw_hstatus_spv; // @[TLB.scala:318:7] wire io_ptw_hstatus_gva_0 = io_ptw_hstatus_gva; // @[TLB.scala:318:7] wire io_ptw_gstatus_debug_0 = io_ptw_gstatus_debug; // @[TLB.scala:318:7] wire io_ptw_gstatus_cease_0 = io_ptw_gstatus_cease; // @[TLB.scala:318:7] wire io_ptw_gstatus_wfi_0 = io_ptw_gstatus_wfi; // @[TLB.scala:318:7] wire [31:0] io_ptw_gstatus_isa_0 = io_ptw_gstatus_isa; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_dprv_0 = io_ptw_gstatus_dprv; // @[TLB.scala:318:7] wire io_ptw_gstatus_dv_0 = io_ptw_gstatus_dv; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_prv_0 = io_ptw_gstatus_prv; // @[TLB.scala:318:7] wire io_ptw_gstatus_v_0 = io_ptw_gstatus_v; // @[TLB.scala:318:7] wire [22:0] io_ptw_gstatus_zero2_0 = io_ptw_gstatus_zero2; // @[TLB.scala:318:7] wire io_ptw_gstatus_mpv_0 = io_ptw_gstatus_mpv; // @[TLB.scala:318:7] wire io_ptw_gstatus_gva_0 = io_ptw_gstatus_gva; // @[TLB.scala:318:7] wire io_ptw_gstatus_mbe_0 = io_ptw_gstatus_mbe; // @[TLB.scala:318:7] wire io_ptw_gstatus_sbe_0 = io_ptw_gstatus_sbe; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_sxl_0 = io_ptw_gstatus_sxl; // @[TLB.scala:318:7] wire [7:0] io_ptw_gstatus_zero1_0 = io_ptw_gstatus_zero1; // @[TLB.scala:318:7] wire io_ptw_gstatus_tsr_0 = io_ptw_gstatus_tsr; // @[TLB.scala:318:7] wire io_ptw_gstatus_tw_0 = io_ptw_gstatus_tw; // @[TLB.scala:318:7] wire io_ptw_gstatus_tvm_0 = io_ptw_gstatus_tvm; // @[TLB.scala:318:7] wire io_ptw_gstatus_mxr_0 = io_ptw_gstatus_mxr; // @[TLB.scala:318:7] wire io_ptw_gstatus_sum_0 = io_ptw_gstatus_sum; // @[TLB.scala:318:7] wire io_ptw_gstatus_mprv_0 = io_ptw_gstatus_mprv; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_fs_0 = io_ptw_gstatus_fs; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_mpp_0 = io_ptw_gstatus_mpp; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_vs_0 = io_ptw_gstatus_vs; // @[TLB.scala:318:7] wire io_ptw_gstatus_spp_0 = io_ptw_gstatus_spp; // @[TLB.scala:318:7] wire io_ptw_gstatus_mpie_0 = io_ptw_gstatus_mpie; // @[TLB.scala:318:7] wire io_ptw_gstatus_ube_0 = io_ptw_gstatus_ube; // @[TLB.scala:318:7] wire io_ptw_gstatus_spie_0 = io_ptw_gstatus_spie; // @[TLB.scala:318:7] wire io_ptw_gstatus_upie_0 = io_ptw_gstatus_upie; // @[TLB.scala:318:7] wire io_ptw_gstatus_mie_0 = io_ptw_gstatus_mie; // @[TLB.scala:318:7] wire io_ptw_gstatus_hie_0 = io_ptw_gstatus_hie; // @[TLB.scala:318:7] wire io_ptw_gstatus_sie_0 = io_ptw_gstatus_sie; // @[TLB.scala:318:7] wire io_ptw_gstatus_uie_0 = io_ptw_gstatus_uie; // @[TLB.scala:318:7] wire io_ptw_pmp_0_cfg_l_0 = io_ptw_pmp_0_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_0_cfg_a_0 = io_ptw_pmp_0_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_0_cfg_x_0 = io_ptw_pmp_0_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_0_cfg_w_0 = io_ptw_pmp_0_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_0_cfg_r_0 = io_ptw_pmp_0_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_0_addr_0 = io_ptw_pmp_0_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_0_mask_0 = io_ptw_pmp_0_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_1_cfg_l_0 = io_ptw_pmp_1_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_1_cfg_a_0 = io_ptw_pmp_1_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_1_cfg_x_0 = io_ptw_pmp_1_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_1_cfg_w_0 = io_ptw_pmp_1_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_1_cfg_r_0 = io_ptw_pmp_1_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_1_addr_0 = io_ptw_pmp_1_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_1_mask_0 = io_ptw_pmp_1_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_2_cfg_l_0 = io_ptw_pmp_2_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_2_cfg_a_0 = io_ptw_pmp_2_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_2_cfg_x_0 = io_ptw_pmp_2_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_2_cfg_w_0 = io_ptw_pmp_2_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_2_cfg_r_0 = io_ptw_pmp_2_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_2_addr_0 = io_ptw_pmp_2_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_2_mask_0 = io_ptw_pmp_2_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_3_cfg_l_0 = io_ptw_pmp_3_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_3_cfg_a_0 = io_ptw_pmp_3_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_3_cfg_x_0 = io_ptw_pmp_3_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_3_cfg_w_0 = io_ptw_pmp_3_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_3_cfg_r_0 = io_ptw_pmp_3_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_3_addr_0 = io_ptw_pmp_3_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_3_mask_0 = io_ptw_pmp_3_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_4_cfg_l_0 = io_ptw_pmp_4_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_4_cfg_a_0 = io_ptw_pmp_4_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_4_cfg_x_0 = io_ptw_pmp_4_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_4_cfg_w_0 = io_ptw_pmp_4_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_4_cfg_r_0 = io_ptw_pmp_4_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_4_addr_0 = io_ptw_pmp_4_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_4_mask_0 = io_ptw_pmp_4_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_5_cfg_l_0 = io_ptw_pmp_5_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_5_cfg_a_0 = io_ptw_pmp_5_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_5_cfg_x_0 = io_ptw_pmp_5_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_5_cfg_w_0 = io_ptw_pmp_5_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_5_cfg_r_0 = io_ptw_pmp_5_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_5_addr_0 = io_ptw_pmp_5_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_5_mask_0 = io_ptw_pmp_5_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_6_cfg_l_0 = io_ptw_pmp_6_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_6_cfg_a_0 = io_ptw_pmp_6_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_6_cfg_x_0 = io_ptw_pmp_6_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_6_cfg_w_0 = io_ptw_pmp_6_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_6_cfg_r_0 = io_ptw_pmp_6_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_6_addr_0 = io_ptw_pmp_6_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_6_mask_0 = io_ptw_pmp_6_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_7_cfg_l_0 = io_ptw_pmp_7_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_7_cfg_a_0 = io_ptw_pmp_7_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_7_cfg_x_0 = io_ptw_pmp_7_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_7_cfg_w_0 = io_ptw_pmp_7_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_7_cfg_r_0 = io_ptw_pmp_7_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_7_addr_0 = io_ptw_pmp_7_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_7_mask_0 = io_ptw_pmp_7_mask; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_0_ren_0 = io_ptw_customCSRs_csrs_0_ren; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_0_wen_0 = io_ptw_customCSRs_csrs_0_wen; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_0_wdata_0 = io_ptw_customCSRs_csrs_0_wdata; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_0_value_0 = io_ptw_customCSRs_csrs_0_value; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_1_ren_0 = io_ptw_customCSRs_csrs_1_ren; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_1_wen_0 = io_ptw_customCSRs_csrs_1_wen; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_1_wdata_0 = io_ptw_customCSRs_csrs_1_wdata; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_1_value_0 = io_ptw_customCSRs_csrs_1_value; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_2_ren_0 = io_ptw_customCSRs_csrs_2_ren; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_2_wen_0 = io_ptw_customCSRs_csrs_2_wen; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_2_wdata_0 = io_ptw_customCSRs_csrs_2_wdata; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_2_value_0 = io_ptw_customCSRs_csrs_2_value; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_3_ren_0 = io_ptw_customCSRs_csrs_3_ren; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_3_wen_0 = io_ptw_customCSRs_csrs_3_wen; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_3_wdata_0 = io_ptw_customCSRs_csrs_3_wdata; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_3_value_0 = io_ptw_customCSRs_csrs_3_value; // @[TLB.scala:318:7] wire [6:0] hr_array = 7'h7F; // @[TLB.scala:524:21] wire [6:0] hw_array = 7'h7F; // @[TLB.scala:525:21] wire [6:0] hx_array = 7'h7F; // @[TLB.scala:526:21] wire [6:0] _must_alloc_array_T_8 = 7'h7F; // @[TLB.scala:596:19] wire [6:0] _gf_ld_array_T_1 = 7'h7F; // @[TLB.scala:600:50] wire [5:0] stage2_bypass = 6'h3F; // @[TLB.scala:523:27] wire [5:0] _hr_array_T_4 = 6'h3F; // @[TLB.scala:524:111] wire [5:0] _hw_array_T_1 = 6'h3F; // @[TLB.scala:525:55] wire [5:0] _hx_array_T_1 = 6'h3F; // @[TLB.scala:526:55] wire [5:0] _gpa_hits_hit_mask_T_4 = 6'h3F; // @[TLB.scala:606:88] wire [5:0] gpa_hits_hit_mask = 6'h3F; // @[TLB.scala:606:82] wire [5:0] _gpa_hits_T_1 = 6'h3F; // @[TLB.scala:607:16] wire [5:0] gpa_hits = 6'h3F; // @[TLB.scala:607:14] wire [2:0] _state_vec_WIRE_0 = 3'h0; // @[Replacement.scala:305:25] wire [2:0] _state_vec_WIRE_1 = 3'h0; // @[Replacement.scala:305:25] wire [2:0] _state_vec_WIRE_2 = 3'h0; // @[Replacement.scala:305:25] wire [2:0] _state_vec_WIRE_3 = 3'h0; // @[Replacement.scala:305:25] wire [6:0] _gf_ld_array_T_2 = 7'h0; // @[TLB.scala:600:46] wire [6:0] gf_ld_array = 7'h0; // @[TLB.scala:600:24] wire [6:0] _gf_st_array_T_1 = 7'h0; // @[TLB.scala:601:53] wire [6:0] gf_st_array = 7'h0; // @[TLB.scala:601:24] wire [6:0] _gf_inst_array_T = 7'h0; // @[TLB.scala:602:36] wire [6:0] gf_inst_array = 7'h0; // @[TLB.scala:602:26] wire [6:0] gpa_hits_need_gpa_mask = 7'h0; // @[TLB.scala:605:73] wire [6:0] _io_resp_gf_ld_T_1 = 7'h0; // @[TLB.scala:637:58] wire [6:0] _io_resp_gf_st_T_1 = 7'h0; // @[TLB.scala:638:65] wire [6:0] _io_resp_gf_inst_T = 7'h0; // @[TLB.scala:639:48] wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_2_sdata = 64'h0; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_3_sdata = 64'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_hstatus_vsxl = 2'h2; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_uxl = 2'h2; // @[TLB.scala:318:7] wire [38:0] io_sfence_bits_addr = 39'h0; // @[TLB.scala:318:7, :320:14] wire [1:0] io_ptw_gstatus_xs = 2'h3; // @[TLB.scala:318:7] wire io_ptw_req_bits_valid = 1'h1; // @[TLB.scala:318:7] wire io_ptw_gstatus_sd = 1'h1; // @[TLB.scala:318:7] wire priv_uses_vm = 1'h1; // @[TLB.scala:372:27] wire _vm_enabled_T_2 = 1'h1; // @[TLB.scala:399:64] wire _vsatp_mode_mismatch_T_2 = 1'h1; // @[TLB.scala:403:81] wire _homogeneous_T_59 = 1'h1; // @[TLBPermissions.scala:87:22] wire superpage_hits_ignore_2 = 1'h1; // @[TLB.scala:182:34] wire _superpage_hits_T_13 = 1'h1; // @[TLB.scala:183:40] wire hitsVec_ignore_2 = 1'h1; // @[TLB.scala:182:34] wire _hitsVec_T_37 = 1'h1; // @[TLB.scala:183:40] wire ppn_ignore_1 = 1'h1; // @[TLB.scala:197:34] wire _priv_rw_ok_T = 1'h1; // @[TLB.scala:513:24] wire _priv_rw_ok_T_1 = 1'h1; // @[TLB.scala:513:32] wire _stage2_bypass_T = 1'h1; // @[TLB.scala:523:42] wire _bad_va_T_1 = 1'h1; // @[TLB.scala:560:26] wire _gpa_hits_hit_mask_T_3 = 1'h1; // @[TLB.scala:606:107] wire _tlb_miss_T = 1'h1; // @[TLB.scala:613:32] wire _io_resp_gpa_page_T = 1'h1; // @[TLB.scala:657:20] wire _io_ptw_req_bits_valid_T = 1'h1; // @[TLB.scala:663:28] wire ignore_2 = 1'h1; // @[TLB.scala:182:34] wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[TLB.scala:318:7] wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[TLB.scala:318:7] wire [5:0] _priv_rw_ok_T_6 = 6'h0; // @[TLB.scala:513:75] wire [5:0] _stage1_bypass_T = 6'h0; // @[TLB.scala:517:27] wire [5:0] stage1_bypass = 6'h0; // @[TLB.scala:517:61] wire [5:0] _gpa_hits_T = 6'h0; // @[TLB.scala:607:30] wire [1:0] io_req_bits_prv = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_0_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_1_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_2_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_3_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_4_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_5_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_6_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_7_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[TLB.scala:318:7, :320:14] wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[TLB.scala:318:7, :320:14] wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[TLB.scala:318:7, :320:14] wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[TLB.scala:318:7, :320:14] wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[TLB.scala:318:7, :320:14] wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[TLB.scala:318:7, :320:14] wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[TLB.scala:318:7, :320:14, :373:17] wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[TLB.scala:318:7, :320:14, :373:17] wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[TLB.scala:318:7, :320:14, :373:17] wire [15:0] satp_asid = 16'h0; // @[TLB.scala:318:7, :320:14, :373:17] wire io_req_bits_passthrough = 1'h0; // @[TLB.scala:318:7] wire io_req_bits_v = 1'h0; // @[TLB.scala:318:7] wire io_resp_gpa_is_pte = 1'h0; // @[TLB.scala:318:7] wire io_resp_gf_ld = 1'h0; // @[TLB.scala:318:7] wire io_resp_gf_st = 1'h0; // @[TLB.scala:318:7] wire io_resp_gf_inst = 1'h0; // @[TLB.scala:318:7] wire io_resp_ma_inst = 1'h0; // @[TLB.scala:318:7] wire io_sfence_bits_rs1 = 1'h0; // @[TLB.scala:318:7] wire io_sfence_bits_rs2 = 1'h0; // @[TLB.scala:318:7] wire io_sfence_bits_asid = 1'h0; // @[TLB.scala:318:7] wire io_sfence_bits_hv = 1'h0; // @[TLB.scala:318:7] wire io_sfence_bits_hg = 1'h0; // @[TLB.scala:318:7] wire io_ptw_req_bits_bits_vstage1 = 1'h0; // @[TLB.scala:318:7] wire io_ptw_req_bits_bits_stage2 = 1'h0; // @[TLB.scala:318:7] wire io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_vtsr = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_vtw = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_vtvm = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_hu = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_vsbe = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_2_stall = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_2_set = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_3_stall = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_3_set = 1'h0; // @[TLB.scala:318:7] wire io_kill = 1'h0; // @[TLB.scala:318:7] wire priv_v = 1'h0; // @[TLB.scala:369:34] wire priv_s = 1'h0; // @[TLB.scala:370:20] wire _vstage1_en_T = 1'h0; // @[TLB.scala:376:38] wire _vstage1_en_T_1 = 1'h0; // @[TLB.scala:376:68] wire vstage1_en = 1'h0; // @[TLB.scala:376:48] wire _stage2_en_T = 1'h0; // @[TLB.scala:378:38] wire _stage2_en_T_1 = 1'h0; // @[TLB.scala:378:68] wire stage2_en = 1'h0; // @[TLB.scala:378:48] wire _vsatp_mode_mismatch_T = 1'h0; // @[TLB.scala:403:52] wire _vsatp_mode_mismatch_T_1 = 1'h0; // @[TLB.scala:403:37] wire vsatp_mode_mismatch = 1'h0; // @[TLB.scala:403:78] wire _superpage_hits_ignore_T = 1'h0; // @[TLB.scala:182:28] wire superpage_hits_ignore = 1'h0; // @[TLB.scala:182:34] wire _hitsVec_ignore_T = 1'h0; // @[TLB.scala:182:28] wire hitsVec_ignore = 1'h0; // @[TLB.scala:182:34] wire _hitsVec_ignore_T_3 = 1'h0; // @[TLB.scala:182:28] wire hitsVec_ignore_3 = 1'h0; // @[TLB.scala:182:34] wire refill_v = 1'h0; // @[TLB.scala:448:33] wire newEntry_ae_stage2 = 1'h0; // @[TLB.scala:449:24] wire newEntry_fragmented_superpage = 1'h0; // @[TLB.scala:449:24] wire _newEntry_ae_stage2_T_1 = 1'h0; // @[TLB.scala:456:84] wire _waddr_T = 1'h0; // @[TLB.scala:477:45] wire _mxr_T = 1'h0; // @[TLB.scala:518:36] wire cmd_readx = 1'h0; // @[TLB.scala:575:37] wire _gf_ld_array_T = 1'h0; // @[TLB.scala:600:32] wire _gf_st_array_T = 1'h0; // @[TLB.scala:601:32] wire _multipleHits_T_5 = 1'h0; // @[Misc.scala:183:37] wire _multipleHits_T_14 = 1'h0; // @[Misc.scala:183:37] wire _io_req_ready_T; // @[TLB.scala:631:25] wire _io_resp_gf_ld_T = 1'h0; // @[TLB.scala:637:29] wire _io_resp_gf_ld_T_2 = 1'h0; // @[TLB.scala:637:66] wire _io_resp_gf_ld_T_3 = 1'h0; // @[TLB.scala:637:42] wire _io_resp_gf_st_T = 1'h0; // @[TLB.scala:638:29] wire _io_resp_gf_st_T_2 = 1'h0; // @[TLB.scala:638:73] wire _io_resp_gf_st_T_3 = 1'h0; // @[TLB.scala:638:49] wire _io_resp_gf_inst_T_1 = 1'h0; // @[TLB.scala:639:56] wire _io_resp_gf_inst_T_2 = 1'h0; // @[TLB.scala:639:30] wire _io_resp_gpa_is_pte_T = 1'h0; // @[TLB.scala:655:36] wire _r_superpage_repl_addr_T_3 = 1'h0; // @[TLB.scala:757:8] wire hv = 1'h0; // @[TLB.scala:721:36] wire hg = 1'h0; // @[TLB.scala:722:36] wire hv_1 = 1'h0; // @[TLB.scala:721:36] wire hg_1 = 1'h0; // @[TLB.scala:722:36] wire hv_2 = 1'h0; // @[TLB.scala:721:36] wire hg_2 = 1'h0; // @[TLB.scala:722:36] wire hv_3 = 1'h0; // @[TLB.scala:721:36] wire hg_3 = 1'h0; // @[TLB.scala:722:36] wire hv_4 = 1'h0; // @[TLB.scala:721:36] wire hg_4 = 1'h0; // @[TLB.scala:722:36] wire hv_5 = 1'h0; // @[TLB.scala:721:36] wire hg_5 = 1'h0; // @[TLB.scala:722:36] wire hv_6 = 1'h0; // @[TLB.scala:721:36] wire hg_6 = 1'h0; // @[TLB.scala:722:36] wire hv_7 = 1'h0; // @[TLB.scala:721:36] wire hg_7 = 1'h0; // @[TLB.scala:722:36] wire hv_8 = 1'h0; // @[TLB.scala:721:36] wire hg_8 = 1'h0; // @[TLB.scala:722:36] wire hv_9 = 1'h0; // @[TLB.scala:721:36] wire hg_9 = 1'h0; // @[TLB.scala:722:36] wire hv_10 = 1'h0; // @[TLB.scala:721:36] wire hg_10 = 1'h0; // @[TLB.scala:722:36] wire hv_11 = 1'h0; // @[TLB.scala:721:36] wire hg_11 = 1'h0; // @[TLB.scala:722:36] wire hv_12 = 1'h0; // @[TLB.scala:721:36] wire hg_12 = 1'h0; // @[TLB.scala:722:36] wire hv_13 = 1'h0; // @[TLB.scala:721:36] wire hg_13 = 1'h0; // @[TLB.scala:722:36] wire hv_14 = 1'h0; // @[TLB.scala:721:36] wire hg_14 = 1'h0; // @[TLB.scala:722:36] wire hv_15 = 1'h0; // @[TLB.scala:721:36] wire hg_15 = 1'h0; // @[TLB.scala:722:36] wire hv_16 = 1'h0; // @[TLB.scala:721:36] wire hg_16 = 1'h0; // @[TLB.scala:722:36] wire _ignore_T = 1'h0; // @[TLB.scala:182:28] wire ignore = 1'h0; // @[TLB.scala:182:34] wire hv_17 = 1'h0; // @[TLB.scala:721:36] wire hg_17 = 1'h0; // @[TLB.scala:722:36] wire _ignore_T_3 = 1'h0; // @[TLB.scala:182:28] wire ignore_3 = 1'h0; // @[TLB.scala:182:34] wire [1:0] io_resp_size = io_req_bits_size_0; // @[TLB.scala:318:7] wire [4:0] io_resp_cmd = io_req_bits_cmd_0; // @[TLB.scala:318:7] wire _io_resp_miss_T_2; // @[TLB.scala:651:64] wire [31:0] _io_resp_paddr_T_1; // @[TLB.scala:652:23] wire [39:0] _io_resp_gpa_T; // @[TLB.scala:659:8] wire _io_resp_pf_ld_T_3; // @[TLB.scala:633:41] wire _io_resp_pf_st_T_3; // @[TLB.scala:634:48] wire _io_resp_pf_inst_T_2; // @[TLB.scala:635:29] wire _io_resp_ae_ld_T_1; // @[TLB.scala:641:41] wire _io_resp_ae_st_T_1; // @[TLB.scala:642:41] wire _io_resp_ae_inst_T_2; // @[TLB.scala:643:41] wire _io_resp_ma_ld_T; // @[TLB.scala:645:31] wire _io_resp_ma_st_T; // @[TLB.scala:646:31] wire _io_resp_cacheable_T_1; // @[TLB.scala:648:41] wire _io_resp_must_alloc_T_1; // @[TLB.scala:649:51] wire _io_resp_prefetchable_T_2; // @[TLB.scala:650:59] wire _io_ptw_req_valid_T; // @[TLB.scala:662:29] wire do_refill = io_ptw_resp_valid_0; // @[TLB.scala:318:7, :408:29] wire newEntry_ae_ptw = io_ptw_resp_bits_ae_ptw_0; // @[TLB.scala:318:7, :449:24] wire newEntry_ae_final = io_ptw_resp_bits_ae_final_0; // @[TLB.scala:318:7, :449:24] wire newEntry_pf = io_ptw_resp_bits_pf_0; // @[TLB.scala:318:7, :449:24] wire newEntry_gf = io_ptw_resp_bits_gf_0; // @[TLB.scala:318:7, :449:24] wire newEntry_hr = io_ptw_resp_bits_hr_0; // @[TLB.scala:318:7, :449:24] wire newEntry_hw = io_ptw_resp_bits_hw_0; // @[TLB.scala:318:7, :449:24] wire newEntry_hx = io_ptw_resp_bits_hx_0; // @[TLB.scala:318:7, :449:24] wire newEntry_u = io_ptw_resp_bits_pte_u_0; // @[TLB.scala:318:7, :449:24] wire [1:0] _special_entry_level_T = io_ptw_resp_bits_level_0; // @[package.scala:163:13] wire [3:0] satp_mode = io_ptw_ptbr_mode_0; // @[TLB.scala:318:7, :373:17] wire [43:0] satp_ppn = io_ptw_ptbr_ppn_0; // @[TLB.scala:318:7, :373:17] wire mxr = io_ptw_status_mxr_0; // @[TLB.scala:318:7, :518:31] wire sum = io_ptw_status_sum_0; // @[TLB.scala:318:7, :510:16] wire io_req_ready_0; // @[TLB.scala:318:7] wire io_resp_pf_ld; // @[TLB.scala:318:7] wire io_resp_pf_st; // @[TLB.scala:318:7] wire io_resp_pf_inst; // @[TLB.scala:318:7] wire io_resp_ae_ld; // @[TLB.scala:318:7] wire io_resp_ae_st; // @[TLB.scala:318:7] wire io_resp_ae_inst; // @[TLB.scala:318:7] wire io_resp_ma_ld; // @[TLB.scala:318:7] wire io_resp_ma_st; // @[TLB.scala:318:7] wire io_resp_miss_0; // @[TLB.scala:318:7] wire [31:0] io_resp_paddr_0; // @[TLB.scala:318:7] wire [39:0] io_resp_gpa; // @[TLB.scala:318:7] wire io_resp_cacheable; // @[TLB.scala:318:7] wire io_resp_must_alloc; // @[TLB.scala:318:7] wire io_resp_prefetchable; // @[TLB.scala:318:7] wire [26:0] io_ptw_req_bits_bits_addr_0; // @[TLB.scala:318:7] wire io_ptw_req_bits_bits_need_gpa_0; // @[TLB.scala:318:7] wire io_ptw_req_valid_0; // @[TLB.scala:318:7] wire [26:0] vpn = io_req_bits_vaddr_0[38:12]; // @[TLB.scala:318:7, :335:30] wire [26:0] _ppn_T_5 = vpn; // @[TLB.scala:198:28, :335:30] wire [1:0] memIdx = vpn[1:0]; // @[package.scala:163:13] reg [1:0] sectored_entries_0_0_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_0_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_0_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_0_data_0; // @[TLB.scala:339:29] reg sectored_entries_0_0_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_1_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_1_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_1_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_1_data_0; // @[TLB.scala:339:29] reg sectored_entries_0_1_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_2_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_2_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_2_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_2_data_0; // @[TLB.scala:339:29] reg sectored_entries_0_2_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_3_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_3_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_3_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_3_data_0; // @[TLB.scala:339:29] reg sectored_entries_0_3_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_1_0_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_1_0_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_1_0_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_1_0_data_0; // @[TLB.scala:339:29] reg sectored_entries_1_0_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_1_1_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_1_1_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_1_1_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_1_1_data_0; // @[TLB.scala:339:29] reg sectored_entries_1_1_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_1_2_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_1_2_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_1_2_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_1_2_data_0; // @[TLB.scala:339:29] reg sectored_entries_1_2_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_1_3_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_1_3_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_1_3_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_1_3_data_0; // @[TLB.scala:339:29] reg sectored_entries_1_3_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_2_0_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_2_0_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_2_0_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_2_0_data_0; // @[TLB.scala:339:29] reg sectored_entries_2_0_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_2_1_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_2_1_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_2_1_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_2_1_data_0; // @[TLB.scala:339:29] reg sectored_entries_2_1_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_2_2_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_2_2_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_2_2_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_2_2_data_0; // @[TLB.scala:339:29] reg sectored_entries_2_2_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_2_3_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_2_3_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_2_3_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_2_3_data_0; // @[TLB.scala:339:29] reg sectored_entries_2_3_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_3_0_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_3_0_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_3_0_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_3_0_data_0; // @[TLB.scala:339:29] reg sectored_entries_3_0_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_3_1_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_3_1_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_3_1_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_3_1_data_0; // @[TLB.scala:339:29] reg sectored_entries_3_1_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_3_2_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_3_2_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_3_2_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_3_2_data_0; // @[TLB.scala:339:29] reg sectored_entries_3_2_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_3_3_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_3_3_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_3_3_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_3_3_data_0; // @[TLB.scala:339:29] reg sectored_entries_3_3_valid_0; // @[TLB.scala:339:29] reg [1:0] superpage_entries_0_level; // @[TLB.scala:341:30] reg [26:0] superpage_entries_0_tag_vpn; // @[TLB.scala:341:30] reg superpage_entries_0_tag_v; // @[TLB.scala:341:30] reg [41:0] superpage_entries_0_data_0; // @[TLB.scala:341:30] wire [41:0] _entries_WIRE_9 = superpage_entries_0_data_0; // @[TLB.scala:170:77, :341:30] reg superpage_entries_0_valid_0; // @[TLB.scala:341:30] wire _r_superpage_repl_addr_T = superpage_entries_0_valid_0; // @[TLB.scala:341:30, :757:16] reg [1:0] special_entry_level; // @[TLB.scala:346:56] reg [26:0] special_entry_tag_vpn; // @[TLB.scala:346:56] reg special_entry_tag_v; // @[TLB.scala:346:56] reg [41:0] special_entry_data_0; // @[TLB.scala:346:56] wire [41:0] _mpu_ppn_WIRE_1 = special_entry_data_0; // @[TLB.scala:170:77, :346:56] wire [41:0] _entries_WIRE_11 = special_entry_data_0; // @[TLB.scala:170:77, :346:56] reg special_entry_valid_0; // @[TLB.scala:346:56] reg [1:0] state; // @[TLB.scala:352:22] reg [26:0] r_refill_tag; // @[TLB.scala:354:25] assign io_ptw_req_bits_bits_addr_0 = r_refill_tag; // @[TLB.scala:318:7, :354:25] reg [1:0] r_sectored_repl_addr; // @[TLB.scala:356:33] reg r_sectored_hit_valid; // @[TLB.scala:357:27] reg [1:0] r_sectored_hit_bits; // @[TLB.scala:357:27] reg r_superpage_hit_valid; // @[TLB.scala:358:28] reg r_need_gpa; // @[TLB.scala:361:23] assign io_ptw_req_bits_bits_need_gpa_0 = r_need_gpa; // @[TLB.scala:318:7, :361:23] reg r_gpa_valid; // @[TLB.scala:362:24] reg [38:0] r_gpa; // @[TLB.scala:363:18] reg [26:0] r_gpa_vpn; // @[TLB.scala:364:22] reg r_gpa_is_pte; // @[TLB.scala:365:25] wire _stage1_en_T = satp_mode[3]; // @[TLB.scala:373:17, :374:41] wire stage1_en = _stage1_en_T; // @[TLB.scala:374:{29,41}] wire _vm_enabled_T = stage1_en; // @[TLB.scala:374:29, :399:31] wire _vm_enabled_T_1 = _vm_enabled_T; // @[TLB.scala:399:{31,45}] wire vm_enabled = _vm_enabled_T_1; // @[TLB.scala:399:{45,61}] wire _mpu_ppn_T = vm_enabled; // @[TLB.scala:399:61, :413:32] wire _tlb_miss_T_1 = vm_enabled; // @[TLB.scala:399:61, :613:29] wire [19:0] refill_ppn = io_ptw_resp_bits_pte_ppn_0[19:0]; // @[TLB.scala:318:7, :406:44] wire [19:0] newEntry_ppn = io_ptw_resp_bits_pte_ppn_0[19:0]; // @[TLB.scala:318:7, :406:44, :449:24] wire _mpu_priv_T = do_refill; // @[TLB.scala:408:29, :415:52] wire _io_resp_miss_T = do_refill; // @[TLB.scala:408:29, :651:29] wire _T_25 = state == 2'h1; // @[package.scala:16:47] wire _invalidate_refill_T; // @[package.scala:16:47] assign _invalidate_refill_T = _T_25; // @[package.scala:16:47] assign _io_ptw_req_valid_T = _T_25; // @[package.scala:16:47] wire _invalidate_refill_T_1 = &state; // @[package.scala:16:47] wire _invalidate_refill_T_2 = _invalidate_refill_T \| _invalidate_refill_T_1; // @[package.scala:16:47, :81:59] wire invalidate_refill = _invalidate_refill_T_2 \| io_sfence_valid_0; // @[package.scala:81:59] wire [19:0] _mpu_ppn_T_23; // @[TLB.scala:170:77] wire _mpu_ppn_T_22; // @[TLB.scala:170:77] wire _mpu_ppn_T_21; // @[TLB.scala:170:77] wire _mpu_ppn_T_20; // @[TLB.scala:170:77] wire _mpu_ppn_T_19; // @[TLB.scala:170:77] wire _mpu_ppn_T_18; // @[TLB.scala:170:77] wire _mpu_ppn_T_17; // @[TLB.scala:170:77] wire _mpu_ppn_T_16; // @[TLB.scala:170:77] wire _mpu_ppn_T_15; // @[TLB.scala:170:77] wire _mpu_ppn_T_14; // @[TLB.scala:170:77] wire _mpu_ppn_T_13; // @[TLB.scala:170:77] wire _mpu_ppn_T_12; // @[TLB.scala:170:77] wire _mpu_ppn_T_11; // @[TLB.scala:170:77] wire _mpu_ppn_T_10; // @[TLB.scala:170:77] wire _mpu_ppn_T_9; // @[TLB.scala:170:77] wire _mpu_ppn_T_8; // @[TLB.scala:170:77] wire _mpu_ppn_T_7; // @[TLB.scala:170:77] wire _mpu_ppn_T_6; // @[TLB.scala:170:77] wire _mpu_ppn_T_5; // @[TLB.scala:170:77] wire _mpu_ppn_T_4; // @[TLB.scala:170:77] wire _mpu_ppn_T_3; // @[TLB.scala:170:77] wire _mpu_ppn_T_2; // @[TLB.scala:170:77] wire _mpu_ppn_T_1; // @[TLB.scala:170:77] assign _mpu_ppn_T_1 = _mpu_ppn_WIRE_1[0]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_fragmented_superpage = _mpu_ppn_T_1; // @[TLB.scala:170:77] assign _mpu_ppn_T_2 = _mpu_ppn_WIRE_1[1]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_c = _mpu_ppn_T_2; // @[TLB.scala:170:77] assign _mpu_ppn_T_3 = _mpu_ppn_WIRE_1[2]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_eff = _mpu_ppn_T_3; // @[TLB.scala:170:77] assign _mpu_ppn_T_4 = _mpu_ppn_WIRE_1[3]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_paa = _mpu_ppn_T_4; // @[TLB.scala:170:77] assign _mpu_ppn_T_5 = _mpu_ppn_WIRE_1[4]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_pal = _mpu_ppn_T_5; // @[TLB.scala:170:77] assign _mpu_ppn_T_6 = _mpu_ppn_WIRE_1[5]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_ppp = _mpu_ppn_T_6; // @[TLB.scala:170:77] assign _mpu_ppn_T_7 = _mpu_ppn_WIRE_1[6]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_pr = _mpu_ppn_T_7; // @[TLB.scala:170:77] assign _mpu_ppn_T_8 = _mpu_ppn_WIRE_1[7]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_px = _mpu_ppn_T_8; // @[TLB.scala:170:77] assign _mpu_ppn_T_9 = _mpu_ppn_WIRE_1[8]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_pw = _mpu_ppn_T_9; // @[TLB.scala:170:77] assign _mpu_ppn_T_10 = _mpu_ppn_WIRE_1[9]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_hr = _mpu_ppn_T_10; // @[TLB.scala:170:77] assign _mpu_ppn_T_11 = _mpu_ppn_WIRE_1[10]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_hx = _mpu_ppn_T_11; // @[TLB.scala:170:77] assign _mpu_ppn_T_12 = _mpu_ppn_WIRE_1[11]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_hw = _mpu_ppn_T_12; // @[TLB.scala:170:77] assign _mpu_ppn_T_13 = _mpu_ppn_WIRE_1[12]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_sr = _mpu_ppn_T_13; // @[TLB.scala:170:77] assign _mpu_ppn_T_14 = _mpu_ppn_WIRE_1[13]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_sx = _mpu_ppn_T_14; // @[TLB.scala:170:77] assign _mpu_ppn_T_15 = _mpu_ppn_WIRE_1[14]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_sw = _mpu_ppn_T_15; // @[TLB.scala:170:77] assign _mpu_ppn_T_16 = _mpu_ppn_WIRE_1[15]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_gf = _mpu_ppn_T_16; // @[TLB.scala:170:77] assign _mpu_ppn_T_17 = _mpu_ppn_WIRE_1[16]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_pf = _mpu_ppn_T_17; // @[TLB.scala:170:77] assign _mpu_ppn_T_18 = _mpu_ppn_WIRE_1[17]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_ae_stage2 = _mpu_ppn_T_18; // @[TLB.scala:170:77] assign _mpu_ppn_T_19 = _mpu_ppn_WIRE_1[18]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_ae_final = _mpu_ppn_T_19; // @[TLB.scala:170:77] assign _mpu_ppn_T_20 = _mpu_ppn_WIRE_1[19]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_ae_ptw = _mpu_ppn_T_20; // @[TLB.scala:170:77] assign _mpu_ppn_T_21 = _mpu_ppn_WIRE_1[20]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_g = _mpu_ppn_T_21; // @[TLB.scala:170:77] assign _mpu_ppn_T_22 = _mpu_ppn_WIRE_1[21]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_u = _mpu_ppn_T_22; // @[TLB.scala:170:77] assign _mpu_ppn_T_23 = _mpu_ppn_WIRE_1[41:22]; // @[TLB.scala:170:77] wire [19:0] _mpu_ppn_WIRE_ppn = _mpu_ppn_T_23; // @[TLB.scala:170:77] wire [1:0] mpu_ppn_res = _mpu_ppn_barrier_io_y_ppn[19:18]; // @[package.scala:267:25] wire _GEN = special_entry_level == 2'h0; // @[TLB.scala:197:28, :346:56] wire _mpu_ppn_ignore_T; // @[TLB.scala:197:28] assign _mpu_ppn_ignore_T = _GEN; // @[TLB.scala:197:28] wire _hitsVec_ignore_T_4; // @[TLB.scala:182:28] assign _hitsVec_ignore_T_4 = _GEN; // @[TLB.scala:182:28, :197:28] wire _ppn_ignore_T_2; // @[TLB.scala:197:28] assign _ppn_ignore_T_2 = _GEN; // @[TLB.scala:197:28] wire _ignore_T_4; // @[TLB.scala:182:28] assign _ignore_T_4 = _GEN; // @[TLB.scala:182:28, :197:28] wire mpu_ppn_ignore = _mpu_ppn_ignore_T; // @[TLB.scala:197:{28,34}] wire [26:0] _mpu_ppn_T_24 = mpu_ppn_ignore ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _mpu_ppn_T_25 = {_mpu_ppn_T_24[26:20], _mpu_ppn_T_24[19:0] \| _mpu_ppn_barrier_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _mpu_ppn_T_26 = _mpu_ppn_T_25[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _mpu_ppn_T_27 = {mpu_ppn_res, _mpu_ppn_T_26}; // @[TLB.scala:195:26, :198:{18,58}] wire _mpu_ppn_ignore_T_1 = ~(special_entry_level[1]); // @[TLB.scala:197:28, :346:56] wire mpu_ppn_ignore_1 = _mpu_ppn_ignore_T_1; // @[TLB.scala:197:{28,34}] wire [26:0] _mpu_ppn_T_28 = mpu_ppn_ignore_1 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _mpu_ppn_T_29 = {_mpu_ppn_T_28[26:20], _mpu_ppn_T_28[19:0] \| _mpu_ppn_barrier_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _mpu_ppn_T_30 = _mpu_ppn_T_29[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _mpu_ppn_T_31 = {_mpu_ppn_T_27, _mpu_ppn_T_30}; // @[TLB.scala:198:{18,58}] wire [27:0] _mpu_ppn_T_32 = io_req_bits_vaddr_0[39:12]; // @[TLB.scala:318:7, :413:146] wire [27:0] _mpu_ppn_T_33 = _mpu_ppn_T ? {8'h0, _mpu_ppn_T_31} : _mpu_ppn_T_32; // @[TLB.scala:198:18, :413:{20,32,146}] wire [27:0] mpu_ppn = do_refill ? {8'h0, refill_ppn} : _mpu_ppn_T_33; // @[TLB.scala:406:44, :408:29, :412:20, :413:20] wire [11:0] _mpu_physaddr_T = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52] wire [11:0] _io_resp_paddr_T = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52, :652:46] wire [11:0] _io_resp_gpa_offset_T_1 = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52, :658:82] wire [39:0] mpu_physaddr = {mpu_ppn, _mpu_physaddr_T}; // @[TLB.scala:412:20, :414:{25,52}] wire [39:0] _homogeneous_T = mpu_physaddr; // @[TLB.scala:414:25] wire [39:0] _homogeneous_T_67 = mpu_physaddr; // @[TLB.scala:414:25] wire [39:0] _deny_access_to_debug_T_1 = mpu_physaddr; // @[TLB.scala:414:25] wire _mpu_priv_T_1 = _mpu_priv_T; // @[TLB.scala:415:{38,52}] wire [2:0] _mpu_priv_T_2 = {io_ptw_status_debug_0, 2'h0}; // @[TLB.scala:318:7, :415:103] wire [2:0] mpu_priv = _mpu_priv_T_1 ? 3'h1 : _mpu_priv_T_2; // @[TLB.scala:415:{27,38,103}] wire cacheable; // @[TLB.scala:425:41] wire newEntry_c = cacheable; // @[TLB.scala:425:41, :449:24] wire [40:0] _homogeneous_T_1 = {1'h0, _homogeneous_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_2 = _homogeneous_T_1 & 41'h1FFFFFFE000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_3 = _homogeneous_T_2; // @[Parameters.scala:137:46] wire _homogeneous_T_4 = _homogeneous_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_50 = _homogeneous_T_4; // @[TLBPermissions.scala:101:65] wire [39:0] _GEN_0 = {mpu_physaddr[39:14], mpu_physaddr[13:0] ^ 14'h3000}; // @[TLB.scala:414:25] wire [39:0] _homogeneous_T_5; // @[Parameters.scala:137:31] assign _homogeneous_T_5 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_72; // @[Parameters.scala:137:31] assign _homogeneous_T_72 = _GEN_0; // @[Parameters.scala:137:31] wire [40:0] _homogeneous_T_6 = {1'h0, _homogeneous_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_7 = _homogeneous_T_6 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_8 = _homogeneous_T_7; // @[Parameters.scala:137:46] wire _homogeneous_T_9 = _homogeneous_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_1 = {mpu_physaddr[39:17], mpu_physaddr[16:0] ^ 17'h10000}; // @[TLB.scala:414:25] wire [39:0] _homogeneous_T_10; // @[Parameters.scala:137:31] assign _homogeneous_T_10 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_60; // @[Parameters.scala:137:31] assign _homogeneous_T_60 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_77; // @[Parameters.scala:137:31] assign _homogeneous_T_77 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_109; // @[Parameters.scala:137:31] assign _homogeneous_T_109 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_116; // @[Parameters.scala:137:31] assign _homogeneous_T_116 = _GEN_1; // @[Parameters.scala:137:31] wire [40:0] _homogeneous_T_11 = {1'h0, _homogeneous_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_12 = _homogeneous_T_11 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_13 = _homogeneous_T_12; // @[Parameters.scala:137:46] wire _homogeneous_T_14 = _homogeneous_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_15 = {mpu_physaddr[39:21], mpu_physaddr[20:0] ^ 21'h100000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_16 = {1'h0, _homogeneous_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_17 = _homogeneous_T_16 & 41'h1FFFFFEF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_18 = _homogeneous_T_17; // @[Parameters.scala:137:46] wire _homogeneous_T_19 = _homogeneous_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_20 = {mpu_physaddr[39:26], mpu_physaddr[25:0] ^ 26'h2000000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_21 = {1'h0, _homogeneous_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_22 = _homogeneous_T_21 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_23 = _homogeneous_T_22; // @[Parameters.scala:137:46] wire _homogeneous_T_24 = _homogeneous_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_25 = {mpu_physaddr[39:26], mpu_physaddr[25:0] ^ 26'h2010000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_26 = {1'h0, _homogeneous_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_27 = _homogeneous_T_26 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_28 = _homogeneous_T_27; // @[Parameters.scala:137:46] wire _homogeneous_T_29 = _homogeneous_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_2 = {mpu_physaddr[39:28], mpu_physaddr[27:0] ^ 28'h8000000}; // @[TLB.scala:414:25] wire [39:0] _homogeneous_T_30; // @[Parameters.scala:137:31] assign _homogeneous_T_30 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_82; // @[Parameters.scala:137:31] assign _homogeneous_T_82 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_97; // @[Parameters.scala:137:31] assign _homogeneous_T_97 = _GEN_2; // @[Parameters.scala:137:31] wire [40:0] _homogeneous_T_31 = {1'h0, _homogeneous_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_32 = _homogeneous_T_31 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_33 = _homogeneous_T_32; // @[Parameters.scala:137:46] wire _homogeneous_T_34 = _homogeneous_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_35 = {mpu_physaddr[39:28], mpu_physaddr[27:0] ^ 28'hC000000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_36 = {1'h0, _homogeneous_T_35}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_37 = _homogeneous_T_36 & 41'h1FFFC000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_38 = _homogeneous_T_37; // @[Parameters.scala:137:46] wire _homogeneous_T_39 = _homogeneous_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_40 = {mpu_physaddr[39:29], mpu_physaddr[28:0] ^ 29'h10020000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_41 = {1'h0, _homogeneous_T_40}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_42 = _homogeneous_T_41 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_43 = _homogeneous_T_42; // @[Parameters.scala:137:46] wire _homogeneous_T_44 = _homogeneous_T_43 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_3 = {mpu_physaddr[39:32], mpu_physaddr[31:0] ^ 32'h80000000}; // @[TLB.scala:414:25, :417:15] wire [39:0] _homogeneous_T_45; // @[Parameters.scala:137:31] assign _homogeneous_T_45 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_87; // @[Parameters.scala:137:31] assign _homogeneous_T_87 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_102; // @[Parameters.scala:137:31] assign _homogeneous_T_102 = _GEN_3; // @[Parameters.scala:137:31] wire [40:0] _homogeneous_T_46 = {1'h0, _homogeneous_T_45}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_47 = _homogeneous_T_46 & 41'h1FFF0000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_48 = _homogeneous_T_47; // @[Parameters.scala:137:46] wire _homogeneous_T_49 = _homogeneous_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_51 = _homogeneous_T_50 \| _homogeneous_T_9; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_52 = _homogeneous_T_51 \| _homogeneous_T_14; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_53 = _homogeneous_T_52 \| _homogeneous_T_19; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_54 = _homogeneous_T_53 \| _homogeneous_T_24; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_55 = _homogeneous_T_54 \| _homogeneous_T_29; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_56 = _homogeneous_T_55 \| _homogeneous_T_34; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_57 = _homogeneous_T_56 \| _homogeneous_T_39; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_58 = _homogeneous_T_57 \| _homogeneous_T_44; // @[TLBPermissions.scala:101:65] wire homogeneous = _homogeneous_T_58 \| _homogeneous_T_49; // @[TLBPermissions.scala:101:65] wire [40:0] _homogeneous_T_61 = {1'h0, _homogeneous_T_60}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_62 = _homogeneous_T_61 & 41'h8A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_63 = _homogeneous_T_62; // @[Parameters.scala:137:46] wire _homogeneous_T_64 = _homogeneous_T_63 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_65 = _homogeneous_T_64; // @[TLBPermissions.scala:87:66] wire _homogeneous_T_66 = ~_homogeneous_T_65; // @[TLBPermissions.scala:87:{22,66}] wire [40:0] _homogeneous_T_68 = {1'h0, _homogeneous_T_67}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_69 = _homogeneous_T_68 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_70 = _homogeneous_T_69; // @[Parameters.scala:137:46] wire _homogeneous_T_71 = _homogeneous_T_70 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_92 = _homogeneous_T_71; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_73 = {1'h0, _homogeneous_T_72}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_74 = _homogeneous_T_73 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_75 = _homogeneous_T_74; // @[Parameters.scala:137:46] wire _homogeneous_T_76 = _homogeneous_T_75 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_78 = {1'h0, _homogeneous_T_77}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_79 = _homogeneous_T_78 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_80 = _homogeneous_T_79; // @[Parameters.scala:137:46] wire _homogeneous_T_81 = _homogeneous_T_80 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_83 = {1'h0, _homogeneous_T_82}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_84 = _homogeneous_T_83 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_85 = _homogeneous_T_84; // @[Parameters.scala:137:46] wire _homogeneous_T_86 = _homogeneous_T_85 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_88 = {1'h0, _homogeneous_T_87}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_89 = _homogeneous_T_88 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_90 = _homogeneous_T_89; // @[Parameters.scala:137:46] wire _homogeneous_T_91 = _homogeneous_T_90 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_93 = _homogeneous_T_92 \| _homogeneous_T_76; // @[TLBPermissions.scala:85:66] wire _homogeneous_T_94 = _homogeneous_T_93 \| _homogeneous_T_81; // @[TLBPermissions.scala:85:66] wire _homogeneous_T_95 = _homogeneous_T_94 \| _homogeneous_T_86; // @[TLBPermissions.scala:85:66] wire _homogeneous_T_96 = _homogeneous_T_95 \| _homogeneous_T_91; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_98 = {1'h0, _homogeneous_T_97}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_99 = _homogeneous_T_98 & 41'h8E000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_100 = _homogeneous_T_99; // @[Parameters.scala:137:46] wire _homogeneous_T_101 = _homogeneous_T_100 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_107 = _homogeneous_T_101; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_103 = {1'h0, _homogeneous_T_102}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_104 = _homogeneous_T_103 & 41'h80000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_105 = _homogeneous_T_104; // @[Parameters.scala:137:46] wire _homogeneous_T_106 = _homogeneous_T_105 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_108 = _homogeneous_T_107 \| _homogeneous_T_106; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_110 = {1'h0, _homogeneous_T_109}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_111 = _homogeneous_T_110 & 41'h8A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_112 = _homogeneous_T_111; // @[Parameters.scala:137:46] wire _homogeneous_T_113 = _homogeneous_T_112 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_114 = _homogeneous_T_113; // @[TLBPermissions.scala:87:66] wire _homogeneous_T_115 = ~_homogeneous_T_114; // @[TLBPermissions.scala:87:{22,66}] wire [40:0] _homogeneous_T_117 = {1'h0, _homogeneous_T_116}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_118 = _homogeneous_T_117 & 41'h8A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_119 = _homogeneous_T_118; // @[Parameters.scala:137:46] wire _homogeneous_T_120 = _homogeneous_T_119 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_121 = _homogeneous_T_120; // @[TLBPermissions.scala:87:66] wire _homogeneous_T_122 = ~_homogeneous_T_121; // @[TLBPermissions.scala:87:{22,66}] wire _deny_access_to_debug_T = ~(mpu_priv[2]); // @[TLB.scala:415:27, :428:39] wire [40:0] _deny_access_to_debug_T_2 = {1'h0, _deny_access_to_debug_T_1}; // @[Parameters.scala:137:{31,41}] wire [40:0] _deny_access_to_debug_T_3 = _deny_access_to_debug_T_2 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _deny_access_to_debug_T_4 = _deny_access_to_debug_T_3; // @[Parameters.scala:137:46] wire _deny_access_to_debug_T_5 = _deny_access_to_debug_T_4 == 41'h0; // @[Parameters.scala:137:{46,59}] wire deny_access_to_debug = _deny_access_to_debug_T & _deny_access_to_debug_T_5; // @[TLB.scala:428:{39,50}] wire _prot_r_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33] wire _prot_r_T_1 = _pma_io_resp_r & _prot_r_T; // @[TLB.scala:422:19, :429:{30,33}] wire prot_r = _prot_r_T_1 & _pmp_io_r; // @[TLB.scala:416:19, :429:{30,55}] wire newEntry_pr = prot_r; // @[TLB.scala:429:55, :449:24] wire _prot_w_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33, :430:33] wire _prot_w_T_1 = _pma_io_resp_w & _prot_w_T; // @[TLB.scala:422:19, :430:{30,33}] wire prot_w = _prot_w_T_1 & _pmp_io_w; // @[TLB.scala:416:19, :430:{30,55}] wire newEntry_pw = prot_w; // @[TLB.scala:430:55, :449:24] wire _prot_x_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33, :434:33] wire _prot_x_T_1 = _pma_io_resp_x & _prot_x_T; // @[TLB.scala:422:19, :434:{30,33}] wire prot_x = _prot_x_T_1 & _pmp_io_x; // @[TLB.scala:416:19, :434:{30,55}] wire newEntry_px = prot_x; // @[TLB.scala:434:55, :449:24] wire [3:0][26:0] _GEN_4 = {{sectored_entries_3_0_tag_vpn}, {sectored_entries_2_0_tag_vpn}, {sectored_entries_1_0_tag_vpn}, {sectored_entries_0_0_tag_vpn}}; // @[TLB.scala:174:61, :339:29] wire [3:0] _GEN_5 = {{sectored_entries_3_0_tag_v}, {sectored_entries_2_0_tag_v}, {sectored_entries_1_0_tag_v}, {sectored_entries_0_0_tag_v}}; // @[TLB.scala:174:61, :339:29] wire [3:0][41:0] _GEN_6 = {{sectored_entries_3_0_data_0}, {sectored_entries_2_0_data_0}, {sectored_entries_1_0_data_0}, {sectored_entries_0_0_data_0}}; // @[TLB.scala:174:61, :339:29] wire [41:0] _entries_WIRE_1 = _GEN_6[memIdx]; // @[package.scala:163:13] wire [3:0] _GEN_7 = {{sectored_entries_3_0_valid_0}, {sectored_entries_2_0_valid_0}, {sectored_entries_1_0_valid_0}, {sectored_entries_0_0_valid_0}}; // @[TLB.scala:174:61, :339:29] wire [3:0][26:0] _GEN_8 = {{sectored_entries_3_1_tag_vpn}, {sectored_entries_2_1_tag_vpn}, {sectored_entries_1_1_tag_vpn}, {sectored_entries_0_1_tag_vpn}}; // @[TLB.scala:174:61, :339:29] wire [3:0] _GEN_9 = {{sectored_entries_3_1_tag_v}, {sectored_entries_2_1_tag_v}, {sectored_entries_1_1_tag_v}, {sectored_entries_0_1_tag_v}}; // @[TLB.scala:174:61, :339:29] wire [3:0][41:0] _GEN_10 = {{sectored_entries_3_1_data_0}, {sectored_entries_2_1_data_0}, {sectored_entries_1_1_data_0}, {sectored_entries_0_1_data_0}}; // @[TLB.scala:174:61, :339:29] wire [41:0] _entries_WIRE_3 = _GEN_10[memIdx]; // @[package.scala:163:13] wire [3:0] _GEN_11 = {{sectored_entries_3_1_valid_0}, {sectored_entries_2_1_valid_0}, {sectored_entries_1_1_valid_0}, {sectored_entries_0_1_valid_0}}; // @[TLB.scala:174:61, :339:29] wire [3:0][26:0] _GEN_12 = {{sectored_entries_3_2_tag_vpn}, {sectored_entries_2_2_tag_vpn}, {sectored_entries_1_2_tag_vpn}, {sectored_entries_0_2_tag_vpn}}; // @[TLB.scala:174:61, :339:29] wire [3:0] _GEN_13 = {{sectored_entries_3_2_tag_v}, {sectored_entries_2_2_tag_v}, {sectored_entries_1_2_tag_v}, {sectored_entries_0_2_tag_v}}; // @[TLB.scala:174:61, :339:29] wire [3:0][41:0] _GEN_14 = {{sectored_entries_3_2_data_0}, {sectored_entries_2_2_data_0}, {sectored_entries_1_2_data_0}, {sectored_entries_0_2_data_0}}; // @[TLB.scala:174:61, :339:29] wire [41:0] _entries_WIRE_5 = _GEN_14[memIdx]; // @[package.scala:163:13] wire [3:0] _GEN_15 = {{sectored_entries_3_2_valid_0}, {sectored_entries_2_2_valid_0}, {sectored_entries_1_2_valid_0}, {sectored_entries_0_2_valid_0}}; // @[TLB.scala:174:61, :339:29] wire [3:0][26:0] _GEN_16 = {{sectored_entries_3_3_tag_vpn}, {sectored_entries_2_3_tag_vpn}, {sectored_entries_1_3_tag_vpn}, {sectored_entries_0_3_tag_vpn}}; // @[TLB.scala:174:61, :339:29] wire [3:0] _GEN_17 = {{sectored_entries_3_3_tag_v}, {sectored_entries_2_3_tag_v}, {sectored_entries_1_3_tag_v}, {sectored_entries_0_3_tag_v}}; // @[TLB.scala:174:61, :339:29] wire [3:0][41:0] _GEN_18 = {{sectored_entries_3_3_data_0}, {sectored_entries_2_3_data_0}, {sectored_entries_1_3_data_0}, {sectored_entries_0_3_data_0}}; // @[TLB.scala:174:61, :339:29] wire [41:0] _entries_WIRE_7 = _GEN_18[memIdx]; // @[package.scala:163:13] wire [3:0] _GEN_19 = {{sectored_entries_3_3_valid_0}, {sectored_entries_2_3_valid_0}, {sectored_entries_1_3_valid_0}, {sectored_entries_0_3_valid_0}}; // @[TLB.scala:174:61, :339:29] wire [26:0] _GEN_20 = _GEN_4[memIdx] ^ vpn; // @[package.scala:163:13] wire [26:0] _sector_hits_T; // @[TLB.scala:174:61] assign _sector_hits_T = _GEN_20; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T; // @[TLB.scala:174:61] assign _hitsVec_T = _GEN_20; // @[TLB.scala:174:61] wire [26:0] _sector_hits_T_1 = _sector_hits_T; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_2 = _sector_hits_T_1 == 27'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_3 = ~_GEN_5[memIdx]; // @[package.scala:163:13] wire _sector_hits_T_4 = _sector_hits_T_2 & _sector_hits_T_3; // @[TLB.scala:174:{86,95,105}] wire sector_hits_0 = _GEN_7[memIdx] & _sector_hits_T_4; // @[package.scala:163:13] wire [26:0] _GEN_21 = _GEN_8[memIdx] ^ vpn; // @[package.scala:163:13] wire [26:0] _sector_hits_T_5; // @[TLB.scala:174:61] assign _sector_hits_T_5 = _GEN_21; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_6; // @[TLB.scala:174:61] assign _hitsVec_T_6 = _GEN_21; // @[TLB.scala:174:61] wire [26:0] _sector_hits_T_6 = _sector_hits_T_5; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_7 = _sector_hits_T_6 == 27'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_8 = ~_GEN_9[memIdx]; // @[package.scala:163:13] wire _sector_hits_T_9 = _sector_hits_T_7 & _sector_hits_T_8; // @[TLB.scala:174:{86,95,105}] wire sector_hits_1 = _GEN_11[memIdx] & _sector_hits_T_9; // @[package.scala:163:13] wire [26:0] _GEN_22 = _GEN_12[memIdx] ^ vpn; // @[package.scala:163:13] wire [26:0] _sector_hits_T_10; // @[TLB.scala:174:61] assign _sector_hits_T_10 = _GEN_22; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_12; // @[TLB.scala:174:61] assign _hitsVec_T_12 = _GEN_22; // @[TLB.scala:174:61] wire [26:0] _sector_hits_T_11 = _sector_hits_T_10; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_12 = _sector_hits_T_11 == 27'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_13 = ~_GEN_13[memIdx]; // @[package.scala:163:13] wire _sector_hits_T_14 = _sector_hits_T_12 & _sector_hits_T_13; // @[TLB.scala:174:{86,95,105}] wire sector_hits_2 = _GEN_15[memIdx] & _sector_hits_T_14; // @[package.scala:163:13] wire [26:0] _GEN_23 = _GEN_16[memIdx] ^ vpn; // @[package.scala:163:13] wire [26:0] _sector_hits_T_15; // @[TLB.scala:174:61] assign _sector_hits_T_15 = _GEN_23; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_18; // @[TLB.scala:174:61] assign _hitsVec_T_18 = _GEN_23; // @[TLB.scala:174:61] wire [26:0] _sector_hits_T_16 = _sector_hits_T_15; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_17 = _sector_hits_T_16 == 27'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_18 = ~_GEN_17[memIdx]; // @[package.scala:163:13] wire _sector_hits_T_19 = _sector_hits_T_17 & _sector_hits_T_18; // @[TLB.scala:174:{86,95,105}] wire sector_hits_3 = _GEN_19[memIdx] & _sector_hits_T_19; // @[package.scala:163:13] wire _superpage_hits_tagMatch_T = ~superpage_entries_0_tag_v; // @[TLB.scala:178:43, :341:30] wire superpage_hits_tagMatch = superpage_entries_0_valid_0 & _superpage_hits_tagMatch_T; // @[TLB.scala:178:{33,43}, :341:30] wire [26:0] _T_1876 = superpage_entries_0_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :341:30] wire [26:0] _superpage_hits_T; // @[TLB.scala:183:52] assign _superpage_hits_T = _T_1876; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_5; // @[TLB.scala:183:52] assign _superpage_hits_T_5 = _T_1876; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_10; // @[TLB.scala:183:52] assign _superpage_hits_T_10 = _T_1876; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_24; // @[TLB.scala:183:52] assign _hitsVec_T_24 = _T_1876; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_29; // @[TLB.scala:183:52] assign _hitsVec_T_29 = _T_1876; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_34; // @[TLB.scala:183:52] assign _hitsVec_T_34 = _T_1876; // @[TLB.scala:183:52] wire [8:0] _superpage_hits_T_1 = _superpage_hits_T[26:18]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_2 = _superpage_hits_T_1 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire _superpage_hits_T_3 = _superpage_hits_T_2; // @[TLB.scala:183:{40,79}] wire _superpage_hits_T_4 = superpage_hits_tagMatch & _superpage_hits_T_3; // @[TLB.scala:178:33, :183:{29,40}] wire _GEN_24 = superpage_entries_0_level == 2'h0; // @[TLB.scala:182:28, :341:30] wire _superpage_hits_ignore_T_1; // @[TLB.scala:182:28] assign _superpage_hits_ignore_T_1 = _GEN_24; // @[TLB.scala:182:28] wire _hitsVec_ignore_T_1; // @[TLB.scala:182:28] assign _hitsVec_ignore_T_1 = _GEN_24; // @[TLB.scala:182:28] wire _ppn_ignore_T; // @[TLB.scala:197:28] assign _ppn_ignore_T = _GEN_24; // @[TLB.scala:182:28, :197:28] wire _ignore_T_1; // @[TLB.scala:182:28] assign _ignore_T_1 = _GEN_24; // @[TLB.scala:182:28] wire superpage_hits_ignore_1 = _superpage_hits_ignore_T_1; // @[TLB.scala:182:{28,34}] wire [8:0] _superpage_hits_T_6 = _superpage_hits_T_5[17:9]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_7 = _superpage_hits_T_6 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire _superpage_hits_T_8 = superpage_hits_ignore_1 \| _superpage_hits_T_7; // @[TLB.scala:182:34, :183:{40,79}] wire _superpage_hits_T_9 = _superpage_hits_T_4 & _superpage_hits_T_8; // @[TLB.scala:183:{29,40}] wire superpage_hits_0 = _superpage_hits_T_9; // @[TLB.scala:183:29] wire _superpage_hits_ignore_T_2 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _superpage_hits_T_11 = _superpage_hits_T_10[8:0]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_12 = _superpage_hits_T_11 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire [26:0] _hitsVec_T_1 = _hitsVec_T; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_2 = _hitsVec_T_1 == 27'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_3 = ~_GEN_5[memIdx]; // @[package.scala:163:13] wire _hitsVec_T_4 = _hitsVec_T_2 & _hitsVec_T_3; // @[TLB.scala:174:{86,95,105}] wire _hitsVec_T_5 = _GEN_7[memIdx] & _hitsVec_T_4; // @[package.scala:163:13] wire hitsVec_0 = vm_enabled & _hitsVec_T_5; // @[TLB.scala:188:18, :399:61, :440:44] wire [26:0] _hitsVec_T_7 = _hitsVec_T_6; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_8 = _hitsVec_T_7 == 27'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_9 = ~_GEN_9[memIdx]; // @[package.scala:163:13] wire _hitsVec_T_10 = _hitsVec_T_8 & _hitsVec_T_9; // @[TLB.scala:174:{86,95,105}] wire _hitsVec_T_11 = _GEN_11[memIdx] & _hitsVec_T_10; // @[package.scala:163:13] wire hitsVec_1 = vm_enabled & _hitsVec_T_11; // @[TLB.scala:188:18, :399:61, :440:44] wire [26:0] _hitsVec_T_13 = _hitsVec_T_12; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_14 = _hitsVec_T_13 == 27'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_15 = ~_GEN_13[memIdx]; // @[package.scala:163:13] wire _hitsVec_T_16 = _hitsVec_T_14 & _hitsVec_T_15; // @[TLB.scala:174:{86,95,105}] wire _hitsVec_T_17 = _GEN_15[memIdx] & _hitsVec_T_16; // @[package.scala:163:13] wire hitsVec_2 = vm_enabled & _hitsVec_T_17; // @[TLB.scala:188:18, :399:61, :440:44] wire [26:0] _hitsVec_T_19 = _hitsVec_T_18; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_20 = _hitsVec_T_19 == 27'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_21 = ~_GEN_17[memIdx]; // @[package.scala:163:13] wire _hitsVec_T_22 = _hitsVec_T_20 & _hitsVec_T_21; // @[TLB.scala:174:{86,95,105}] wire _hitsVec_T_23 = _GEN_19[memIdx] & _hitsVec_T_22; // @[package.scala:163:13] wire hitsVec_3 = vm_enabled & _hitsVec_T_23; // @[TLB.scala:188:18, :399:61, :440:44] wire _hitsVec_tagMatch_T = ~superpage_entries_0_tag_v; // @[TLB.scala:178:43, :341:30] wire hitsVec_tagMatch = superpage_entries_0_valid_0 & _hitsVec_tagMatch_T; // @[TLB.scala:178:{33,43}, :341:30] wire [8:0] _hitsVec_T_25 = _hitsVec_T_24[26:18]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_26 = _hitsVec_T_25 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire _hitsVec_T_27 = _hitsVec_T_26; // @[TLB.scala:183:{40,79}] wire _hitsVec_T_28 = hitsVec_tagMatch & _hitsVec_T_27; // @[TLB.scala:178:33, :183:{29,40}] wire hitsVec_ignore_1 = _hitsVec_ignore_T_1; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_30 = _hitsVec_T_29[17:9]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_31 = _hitsVec_T_30 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire _hitsVec_T_32 = hitsVec_ignore_1 \| _hitsVec_T_31; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_33 = _hitsVec_T_28 & _hitsVec_T_32; // @[TLB.scala:183:{29,40}] wire _hitsVec_T_38 = _hitsVec_T_33; // @[TLB.scala:183:29] wire _hitsVec_ignore_T_2 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _hitsVec_T_35 = _hitsVec_T_34[8:0]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_36 = _hitsVec_T_35 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire hitsVec_4 = vm_enabled & _hitsVec_T_38; // @[TLB.scala:183:29, :399:61, :440:44] wire _hitsVec_tagMatch_T_1 = ~special_entry_tag_v; // @[TLB.scala:178:43, :346:56] wire hitsVec_tagMatch_1 = special_entry_valid_0 & _hitsVec_tagMatch_T_1; // @[TLB.scala:178:{33,43}, :346:56] wire [26:0] _T_1974 = special_entry_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :346:56] wire [26:0] _hitsVec_T_39; // @[TLB.scala:183:52] assign _hitsVec_T_39 = _T_1974; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_44; // @[TLB.scala:183:52] assign _hitsVec_T_44 = _T_1974; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_49; // @[TLB.scala:183:52] assign _hitsVec_T_49 = _T_1974; // @[TLB.scala:183:52] wire [8:0] _hitsVec_T_40 = _hitsVec_T_39[26:18]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_41 = _hitsVec_T_40 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire _hitsVec_T_42 = _hitsVec_T_41; // @[TLB.scala:183:{40,79}] wire _hitsVec_T_43 = hitsVec_tagMatch_1 & _hitsVec_T_42; // @[TLB.scala:178:33, :183:{29,40}] wire hitsVec_ignore_4 = _hitsVec_ignore_T_4; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_45 = _hitsVec_T_44[17:9]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_46 = _hitsVec_T_45 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire _hitsVec_T_47 = hitsVec_ignore_4 \| _hitsVec_T_46; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_48 = _hitsVec_T_43 & _hitsVec_T_47; // @[TLB.scala:183:{29,40}] wire _hitsVec_ignore_T_5 = ~(special_entry_level[1]); // @[TLB.scala:182:28, :197:28, :346:56] wire hitsVec_ignore_5 = _hitsVec_ignore_T_5; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_50 = _hitsVec_T_49[8:0]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_51 = _hitsVec_T_50 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire _hitsVec_T_52 = hitsVec_ignore_5 \| _hitsVec_T_51; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_53 = _hitsVec_T_48 & _hitsVec_T_52; // @[TLB.scala:183:{29,40}] wire hitsVec_5 = vm_enabled & _hitsVec_T_53; // @[TLB.scala:183:29, :399:61, :440:44] wire [1:0] real_hits_lo_hi = {hitsVec_2, hitsVec_1}; // @[package.scala:45:27] wire [2:0] real_hits_lo = {real_hits_lo_hi, hitsVec_0}; // @[package.scala:45:27] wire [1:0] real_hits_hi_hi = {hitsVec_5, hitsVec_4}; // @[package.scala:45:27] wire [2:0] real_hits_hi = {real_hits_hi_hi, hitsVec_3}; // @[package.scala:45:27] wire [5:0] real_hits = {real_hits_hi, real_hits_lo}; // @[package.scala:45:27] wire [5:0] _tlb_hit_T = real_hits; // @[package.scala:45:27] wire _hits_T = ~vm_enabled; // @[TLB.scala:399:61, :442:18] wire [6:0] hits = {_hits_T, real_hits}; // @[package.scala:45:27] wire _newEntry_g_T; // @[TLB.scala:453:25] wire _newEntry_sw_T_6; // @[PTW.scala:151:40] wire _newEntry_sx_T_5; // @[PTW.scala:153:35] wire _newEntry_sr_T_5; // @[PTW.scala:149:35] wire newEntry_g; // @[TLB.scala:449:24] wire newEntry_sw; // @[TLB.scala:449:24] wire newEntry_sx; // @[TLB.scala:449:24] wire newEntry_sr; // @[TLB.scala:449:24] wire newEntry_ppp; // @[TLB.scala:449:24] wire newEntry_pal; // @[TLB.scala:449:24] wire newEntry_paa; // @[TLB.scala:449:24] wire newEntry_eff; // @[TLB.scala:449:24] assign _newEntry_g_T = io_ptw_resp_bits_pte_g_0 & io_ptw_resp_bits_pte_v_0; // @[TLB.scala:318:7, :453:25] assign newEntry_g = _newEntry_g_T; // @[TLB.scala:449:24, :453:25] wire _newEntry_ae_stage2_T = io_ptw_resp_bits_ae_final_0 & io_ptw_resp_bits_gpa_is_pte_0; // @[TLB.scala:318:7, :456:53] wire _newEntry_sr_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7] wire _newEntry_sr_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sr_T; // @[TLB.scala:318:7] wire _newEntry_sr_T_2 = io_ptw_resp_bits_pte_r_0 \| _newEntry_sr_T_1; // @[TLB.scala:318:7] wire _newEntry_sr_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sr_T_2; // @[TLB.scala:318:7] wire _newEntry_sr_T_4 = _newEntry_sr_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7] assign _newEntry_sr_T_5 = _newEntry_sr_T_4 & io_ptw_resp_bits_pte_r_0; // @[TLB.scala:318:7] assign newEntry_sr = _newEntry_sr_T_5; // @[TLB.scala:449:24] wire _newEntry_sw_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7] wire _newEntry_sw_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sw_T; // @[TLB.scala:318:7] wire _newEntry_sw_T_2 = io_ptw_resp_bits_pte_r_0 \| _newEntry_sw_T_1; // @[TLB.scala:318:7] wire _newEntry_sw_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sw_T_2; // @[TLB.scala:318:7] wire _newEntry_sw_T_4 = _newEntry_sw_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7] wire _newEntry_sw_T_5 = _newEntry_sw_T_4 & io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7] assign _newEntry_sw_T_6 = _newEntry_sw_T_5 & io_ptw_resp_bits_pte_d_0; // @[TLB.scala:318:7] assign newEntry_sw = _newEntry_sw_T_6; // @[TLB.scala:449:24] wire _newEntry_sx_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7] wire _newEntry_sx_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sx_T; // @[TLB.scala:318:7] wire _newEntry_sx_T_2 = io_ptw_resp_bits_pte_r_0 \| _newEntry_sx_T_1; // @[TLB.scala:318:7] wire _newEntry_sx_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sx_T_2; // @[TLB.scala:318:7] wire _newEntry_sx_T_4 = _newEntry_sx_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7] assign _newEntry_sx_T_5 = _newEntry_sx_T_4 & io_ptw_resp_bits_pte_x_0; // @[TLB.scala:318:7] assign newEntry_sx = _newEntry_sx_T_5; // @[TLB.scala:449:24] wire [1:0] _GEN_25 = {newEntry_c, 1'h0}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign special_entry_data_0_lo_lo_lo = _GEN_25; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_lo_lo_lo = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_data_0_lo_lo_lo = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_1_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_1_data_0_lo_lo_lo = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_2_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_2_data_0_lo_lo_lo = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_3_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_3_data_0_lo_lo_lo = _GEN_25; // @[TLB.scala:217:24] wire [1:0] _GEN_26 = {newEntry_pal, newEntry_paa}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign special_entry_data_0_lo_lo_hi_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_lo_lo_hi_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_data_0_lo_lo_hi_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_1_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_1_data_0_lo_lo_hi_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_2_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_2_data_0_lo_lo_hi_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_3_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_3_data_0_lo_lo_hi_hi = _GEN_26; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_lo_lo_hi = {special_entry_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] special_entry_data_0_lo_lo = {special_entry_data_0_lo_lo_hi, special_entry_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [1:0] _GEN_27 = {newEntry_px, newEntry_pr}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign special_entry_data_0_lo_hi_lo_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_lo_hi_lo_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_data_0_lo_hi_lo_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_1_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_1_data_0_lo_hi_lo_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_2_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_2_data_0_lo_hi_lo_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_3_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_3_data_0_lo_hi_lo_hi = _GEN_27; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_lo_hi_lo = {special_entry_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [1:0] _GEN_28 = {newEntry_hx, newEntry_hr}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign special_entry_data_0_lo_hi_hi_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_lo_hi_hi_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_data_0_lo_hi_hi_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_1_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_1_data_0_lo_hi_hi_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_2_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_2_data_0_lo_hi_hi_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_3_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_3_data_0_lo_hi_hi_hi = _GEN_28; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_lo_hi_hi = {special_entry_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] special_entry_data_0_lo_hi = {special_entry_data_0_lo_hi_hi, special_entry_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] special_entry_data_0_lo = {special_entry_data_0_lo_hi, special_entry_data_0_lo_lo}; // @[TLB.scala:217:24] wire [1:0] _GEN_29 = {newEntry_sx, newEntry_sr}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign special_entry_data_0_hi_lo_lo_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_hi_lo_lo_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_data_0_hi_lo_lo_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_1_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_1_data_0_hi_lo_lo_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_2_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_2_data_0_hi_lo_lo_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_3_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_3_data_0_hi_lo_lo_hi = _GEN_29; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_hi_lo_lo = {special_entry_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [1:0] _GEN_30 = {newEntry_pf, newEntry_gf}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign special_entry_data_0_hi_lo_hi_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_hi_lo_hi_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_data_0_hi_lo_hi_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_1_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_1_data_0_hi_lo_hi_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_2_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_2_data_0_hi_lo_hi_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_3_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_3_data_0_hi_lo_hi_hi = _GEN_30; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_hi_lo_hi = {special_entry_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] special_entry_data_0_hi_lo = {special_entry_data_0_hi_lo_hi, special_entry_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [1:0] _GEN_31 = {newEntry_ae_ptw, newEntry_ae_final}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign special_entry_data_0_hi_hi_lo_hi = _GEN_31; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_hi_hi_lo_hi = _GEN_31; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_data_0_hi_hi_lo_hi = _GEN_31; // @[TLB.scala:217:24] wire [1:0] sectored_entries_1_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_1_data_0_hi_hi_lo_hi = _GEN_31; // @[TLB.scala:217:24] wire [1:0] sectored_entries_2_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_2_data_0_hi_hi_lo_hi = _GEN_31; // @[TLB.scala:217:24] wire [1:0] sectored_entries_3_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_3_data_0_hi_hi_lo_hi = _GEN_31; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_hi_hi_lo = {special_entry_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [20:0] _GEN_32 = {newEntry_ppn, newEntry_u}; // @[TLB.scala:217:24, :449:24] wire [20:0] special_entry_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign special_entry_data_0_hi_hi_hi_hi = _GEN_32; // @[TLB.scala:217:24] wire [20:0] superpage_entries_0_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_hi_hi_hi_hi = _GEN_32; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_data_0_hi_hi_hi_hi = _GEN_32; // @[TLB.scala:217:24] wire [20:0] sectored_entries_1_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_1_data_0_hi_hi_hi_hi = _GEN_32; // @[TLB.scala:217:24] wire [20:0] sectored_entries_2_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_2_data_0_hi_hi_hi_hi = _GEN_32; // @[TLB.scala:217:24] wire [20:0] sectored_entries_3_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_3_data_0_hi_hi_hi_hi = _GEN_32; // @[TLB.scala:217:24] wire [21:0] special_entry_data_0_hi_hi_hi = {special_entry_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] special_entry_data_0_hi_hi = {special_entry_data_0_hi_hi_hi, special_entry_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] special_entry_data_0_hi = {special_entry_data_0_hi_hi, special_entry_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _special_entry_data_0_T = {special_entry_data_0_hi, special_entry_data_0_lo}; // @[TLB.scala:217:24] wire _superpage_entries_0_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13] wire [2:0] superpage_entries_0_data_0_lo_lo_hi = {superpage_entries_0_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] superpage_entries_0_data_0_lo_lo = {superpage_entries_0_data_0_lo_lo_hi, superpage_entries_0_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_0_data_0_lo_hi_lo = {superpage_entries_0_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_0_data_0_lo_hi_hi = {superpage_entries_0_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_0_data_0_lo_hi = {superpage_entries_0_data_0_lo_hi_hi, superpage_entries_0_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] superpage_entries_0_data_0_lo = {superpage_entries_0_data_0_lo_hi, superpage_entries_0_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_0_data_0_hi_lo_lo = {superpage_entries_0_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_0_data_0_hi_lo_hi = {superpage_entries_0_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_0_data_0_hi_lo = {superpage_entries_0_data_0_hi_lo_hi, superpage_entries_0_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_0_data_0_hi_hi_lo = {superpage_entries_0_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] superpage_entries_0_data_0_hi_hi_hi = {superpage_entries_0_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] superpage_entries_0_data_0_hi_hi = {superpage_entries_0_data_0_hi_hi_hi, superpage_entries_0_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] superpage_entries_0_data_0_hi = {superpage_entries_0_data_0_hi_hi, superpage_entries_0_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _superpage_entries_0_data_0_T = {superpage_entries_0_data_0_hi, superpage_entries_0_data_0_lo}; // @[TLB.scala:217:24] wire [1:0] r_memIdx = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] waddr_1 = r_sectored_hit_valid ? r_sectored_hit_bits : r_sectored_repl_addr; // @[TLB.scala:356:33, :357:27, :485:22] wire [2:0] sectored_entries_0_data_0_lo_lo_hi = {sectored_entries_0_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_data_0_lo_lo = {sectored_entries_0_data_0_lo_lo_hi, sectored_entries_0_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_data_0_lo_hi_lo = {sectored_entries_0_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_data_0_lo_hi_hi = {sectored_entries_0_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_data_0_lo_hi = {sectored_entries_0_data_0_lo_hi_hi, sectored_entries_0_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_data_0_lo = {sectored_entries_0_data_0_lo_hi, sectored_entries_0_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_data_0_hi_lo_lo = {sectored_entries_0_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_data_0_hi_lo_hi = {sectored_entries_0_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_data_0_hi_lo = {sectored_entries_0_data_0_hi_lo_hi, sectored_entries_0_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_data_0_hi_hi_lo = {sectored_entries_0_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_data_0_hi_hi_hi = {sectored_entries_0_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_data_0_hi_hi = {sectored_entries_0_data_0_hi_hi_hi, sectored_entries_0_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_data_0_hi = {sectored_entries_0_data_0_hi_hi, sectored_entries_0_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_data_0_T = {sectored_entries_0_data_0_hi, sectored_entries_0_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_1_data_0_lo_lo_hi = {sectored_entries_1_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_1_data_0_lo_lo = {sectored_entries_1_data_0_lo_lo_hi, sectored_entries_1_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_1_data_0_lo_hi_lo = {sectored_entries_1_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_1_data_0_lo_hi_hi = {sectored_entries_1_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_1_data_0_lo_hi = {sectored_entries_1_data_0_lo_hi_hi, sectored_entries_1_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_1_data_0_lo = {sectored_entries_1_data_0_lo_hi, sectored_entries_1_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_1_data_0_hi_lo_lo = {sectored_entries_1_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_1_data_0_hi_lo_hi = {sectored_entries_1_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_1_data_0_hi_lo = {sectored_entries_1_data_0_hi_lo_hi, sectored_entries_1_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_1_data_0_hi_hi_lo = {sectored_entries_1_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_1_data_0_hi_hi_hi = {sectored_entries_1_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_1_data_0_hi_hi = {sectored_entries_1_data_0_hi_hi_hi, sectored_entries_1_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_1_data_0_hi = {sectored_entries_1_data_0_hi_hi, sectored_entries_1_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_1_data_0_T = {sectored_entries_1_data_0_hi, sectored_entries_1_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_2_data_0_lo_lo_hi = {sectored_entries_2_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_2_data_0_lo_lo = {sectored_entries_2_data_0_lo_lo_hi, sectored_entries_2_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_2_data_0_lo_hi_lo = {sectored_entries_2_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_2_data_0_lo_hi_hi = {sectored_entries_2_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_2_data_0_lo_hi = {sectored_entries_2_data_0_lo_hi_hi, sectored_entries_2_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_2_data_0_lo = {sectored_entries_2_data_0_lo_hi, sectored_entries_2_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_2_data_0_hi_lo_lo = {sectored_entries_2_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_2_data_0_hi_lo_hi = {sectored_entries_2_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_2_data_0_hi_lo = {sectored_entries_2_data_0_hi_lo_hi, sectored_entries_2_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_2_data_0_hi_hi_lo = {sectored_entries_2_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_2_data_0_hi_hi_hi = {sectored_entries_2_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_2_data_0_hi_hi = {sectored_entries_2_data_0_hi_hi_hi, sectored_entries_2_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_2_data_0_hi = {sectored_entries_2_data_0_hi_hi, sectored_entries_2_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_2_data_0_T = {sectored_entries_2_data_0_hi, sectored_entries_2_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_3_data_0_lo_lo_hi = {sectored_entries_3_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_3_data_0_lo_lo = {sectored_entries_3_data_0_lo_lo_hi, sectored_entries_3_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_3_data_0_lo_hi_lo = {sectored_entries_3_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_3_data_0_lo_hi_hi = {sectored_entries_3_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_3_data_0_lo_hi = {sectored_entries_3_data_0_lo_hi_hi, sectored_entries_3_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_3_data_0_lo = {sectored_entries_3_data_0_lo_hi, sectored_entries_3_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_3_data_0_hi_lo_lo = {sectored_entries_3_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_3_data_0_hi_lo_hi = {sectored_entries_3_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_3_data_0_hi_lo = {sectored_entries_3_data_0_hi_lo_hi, sectored_entries_3_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_3_data_0_hi_hi_lo = {sectored_entries_3_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_3_data_0_hi_hi_hi = {sectored_entries_3_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_3_data_0_hi_hi = {sectored_entries_3_data_0_hi_hi_hi, sectored_entries_3_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_3_data_0_hi = {sectored_entries_3_data_0_hi_hi, sectored_entries_3_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_3_data_0_T = {sectored_entries_3_data_0_hi, sectored_entries_3_data_0_lo}; // @[TLB.scala:217:24] wire [19:0] _entries_T_22; // @[TLB.scala:170:77] wire _entries_T_21; // @[TLB.scala:170:77] wire _entries_T_20; // @[TLB.scala:170:77] wire _entries_T_19; // @[TLB.scala:170:77] wire _entries_T_18; // @[TLB.scala:170:77] wire _entries_T_17; // @[TLB.scala:170:77] wire _entries_T_16; // @[TLB.scala:170:77] wire _entries_T_15; // @[TLB.scala:170:77] wire _entries_T_14; // @[TLB.scala:170:77] wire _entries_T_13; // @[TLB.scala:170:77] wire _entries_T_12; // @[TLB.scala:170:77] wire _entries_T_11; // @[TLB.scala:170:77] wire _entries_T_10; // @[TLB.scala:170:77] wire _entries_T_9; // @[TLB.scala:170:77] wire _entries_T_8; // @[TLB.scala:170:77] wire _entries_T_7; // @[TLB.scala:170:77] wire _entries_T_6; // @[TLB.scala:170:77] wire _entries_T_5; // @[TLB.scala:170:77] wire _entries_T_4; // @[TLB.scala:170:77] wire _entries_T_3; // @[TLB.scala:170:77] wire _entries_T_2; // @[TLB.scala:170:77] wire _entries_T_1; // @[TLB.scala:170:77] wire _entries_T; // @[TLB.scala:170:77] assign _entries_T = _entries_WIRE_1[0]; // @[TLB.scala:170:77] wire _entries_WIRE_fragmented_superpage = _entries_T; // @[TLB.scala:170:77] assign _entries_T_1 = _entries_WIRE_1[1]; // @[TLB.scala:170:77] wire _entries_WIRE_c = _entries_T_1; // @[TLB.scala:170:77] assign _entries_T_2 = _entries_WIRE_1[2]; // @[TLB.scala:170:77] wire _entries_WIRE_eff = _entries_T_2; // @[TLB.scala:170:77] assign _entries_T_3 = _entries_WIRE_1[3]; // @[TLB.scala:170:77] wire _entries_WIRE_paa = _entries_T_3; // @[TLB.scala:170:77] assign _entries_T_4 = _entries_WIRE_1[4]; // @[TLB.scala:170:77] wire _entries_WIRE_pal = _entries_T_4; // @[TLB.scala:170:77] assign _entries_T_5 = _entries_WIRE_1[5]; // @[TLB.scala:170:77] wire _entries_WIRE_ppp = _entries_T_5; // @[TLB.scala:170:77] assign _entries_T_6 = _entries_WIRE_1[6]; // @[TLB.scala:170:77] wire _entries_WIRE_pr = _entries_T_6; // @[TLB.scala:170:77] assign _entries_T_7 = _entries_WIRE_1[7]; // @[TLB.scala:170:77] wire _entries_WIRE_px = _entries_T_7; // @[TLB.scala:170:77] assign _entries_T_8 = _entries_WIRE_1[8]; // @[TLB.scala:170:77] wire _entries_WIRE_pw = _entries_T_8; // @[TLB.scala:170:77] assign _entries_T_9 = _entries_WIRE_1[9]; // @[TLB.scala:170:77] wire _entries_WIRE_hr = _entries_T_9; // @[TLB.scala:170:77] assign _entries_T_10 = _entries_WIRE_1[10]; // @[TLB.scala:170:77] wire _entries_WIRE_hx = _entries_T_10; // @[TLB.scala:170:77] assign _entries_T_11 = _entries_WIRE_1[11]; // @[TLB.scala:170:77] wire _entries_WIRE_hw = _entries_T_11; // @[TLB.scala:170:77] assign _entries_T_12 = _entries_WIRE_1[12]; // @[TLB.scala:170:77] wire _entries_WIRE_sr = _entries_T_12; // @[TLB.scala:170:77] assign _entries_T_13 = _entries_WIRE_1[13]; // @[TLB.scala:170:77] wire _entries_WIRE_sx = _entries_T_13; // @[TLB.scala:170:77] assign _entries_T_14 = _entries_WIRE_1[14]; // @[TLB.scala:170:77] wire _entries_WIRE_sw = _entries_T_14; // @[TLB.scala:170:77] assign _entries_T_15 = _entries_WIRE_1[15]; // @[TLB.scala:170:77] wire _entries_WIRE_gf = _entries_T_15; // @[TLB.scala:170:77] assign _entries_T_16 = _entries_WIRE_1[16]; // @[TLB.scala:170:77] wire _entries_WIRE_pf = _entries_T_16; // @[TLB.scala:170:77] assign _entries_T_17 = _entries_WIRE_1[17]; // @[TLB.scala:170:77] wire _entries_WIRE_ae_stage2 = _entries_T_17; // @[TLB.scala:170:77] assign _entries_T_18 = _entries_WIRE_1[18]; // @[TLB.scala:170:77] wire _entries_WIRE_ae_final = _entries_T_18; // @[TLB.scala:170:77] assign _entries_T_19 = _entries_WIRE_1[19]; // @[TLB.scala:170:77] wire _entries_WIRE_ae_ptw = _entries_T_19; // @[TLB.scala:170:77] assign _entries_T_20 = _entries_WIRE_1[20]; // @[TLB.scala:170:77] wire _entries_WIRE_g = _entries_T_20; // @[TLB.scala:170:77] assign _entries_T_21 = _entries_WIRE_1[21]; // @[TLB.scala:170:77] wire _entries_WIRE_u = _entries_T_21; // @[TLB.scala:170:77] assign _entries_T_22 = _entries_WIRE_1[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_ppn = _entries_T_22; // @[TLB.scala:170:77] wire [19:0] _entries_T_45; // @[TLB.scala:170:77] wire _entries_T_44; // @[TLB.scala:170:77] wire _entries_T_43; // @[TLB.scala:170:77] wire _entries_T_42; // @[TLB.scala:170:77] wire _entries_T_41; // @[TLB.scala:170:77] wire _entries_T_40; // @[TLB.scala:170:77] wire _entries_T_39; // @[TLB.scala:170:77] wire _entries_T_38; // @[TLB.scala:170:77] wire _entries_T_37; // @[TLB.scala:170:77] wire _entries_T_36; // @[TLB.scala:170:77] wire _entries_T_35; // @[TLB.scala:170:77] wire _entries_T_34; // @[TLB.scala:170:77] wire _entries_T_33; // @[TLB.scala:170:77] wire _entries_T_32; // @[TLB.scala:170:77] wire _entries_T_31; // @[TLB.scala:170:77] wire _entries_T_30; // @[TLB.scala:170:77] wire _entries_T_29; // @[TLB.scala:170:77] wire _entries_T_28; // @[TLB.scala:170:77] wire _entries_T_27; // @[TLB.scala:170:77] wire _entries_T_26; // @[TLB.scala:170:77] wire _entries_T_25; // @[TLB.scala:170:77] wire _entries_T_24; // @[TLB.scala:170:77] wire _entries_T_23; // @[TLB.scala:170:77] assign _entries_T_23 = _entries_WIRE_3[0]; // @[TLB.scala:170:77] wire _entries_WIRE_2_fragmented_superpage = _entries_T_23; // @[TLB.scala:170:77] assign _entries_T_24 = _entries_WIRE_3[1]; // @[TLB.scala:170:77] wire _entries_WIRE_2_c = _entries_T_24; // @[TLB.scala:170:77] assign _entries_T_25 = _entries_WIRE_3[2]; // @[TLB.scala:170:77] wire _entries_WIRE_2_eff = _entries_T_25; // @[TLB.scala:170:77] assign _entries_T_26 = _entries_WIRE_3[3]; // @[TLB.scala:170:77] wire _entries_WIRE_2_paa = _entries_T_26; // @[TLB.scala:170:77] assign _entries_T_27 = _entries_WIRE_3[4]; // @[TLB.scala:170:77] wire _entries_WIRE_2_pal = _entries_T_27; // @[TLB.scala:170:77] assign _entries_T_28 = _entries_WIRE_3[5]; // @[TLB.scala:170:77] wire _entries_WIRE_2_ppp = _entries_T_28; // @[TLB.scala:170:77] assign _entries_T_29 = _entries_WIRE_3[6]; // @[TLB.scala:170:77] wire _entries_WIRE_2_pr = _entries_T_29; // @[TLB.scala:170:77] assign _entries_T_30 = _entries_WIRE_3[7]; // @[TLB.scala:170:77] wire _entries_WIRE_2_px = _entries_T_30; // @[TLB.scala:170:77] assign _entries_T_31 = _entries_WIRE_3[8]; // @[TLB.scala:170:77] wire _entries_WIRE_2_pw = _entries_T_31; // @[TLB.scala:170:77] assign _entries_T_32 = _entries_WIRE_3[9]; // @[TLB.scala:170:77] wire _entries_WIRE_2_hr = _entries_T_32; // @[TLB.scala:170:77] assign _entries_T_33 = _entries_WIRE_3[10]; // @[TLB.scala:170:77] wire _entries_WIRE_2_hx = _entries_T_33; // @[TLB.scala:170:77] assign _entries_T_34 = _entries_WIRE_3[11]; // @[TLB.scala:170:77] wire _entries_WIRE_2_hw = _entries_T_34; // @[TLB.scala:170:77] assign _entries_T_35 = _entries_WIRE_3[12]; // @[TLB.scala:170:77] wire _entries_WIRE_2_sr = _entries_T_35; // @[TLB.scala:170:77] assign _entries_T_36 = _entries_WIRE_3[13]; // @[TLB.scala:170:77] wire _entries_WIRE_2_sx = _entries_T_36; // @[TLB.scala:170:77] assign _entries_T_37 = _entries_WIRE_3[14]; // @[TLB.scala:170:77] wire _entries_WIRE_2_sw = _entries_T_37; // @[TLB.scala:170:77] assign _entries_T_38 = _entries_WIRE_3[15]; // @[TLB.scala:170:77] wire _entries_WIRE_2_gf = _entries_T_38; // @[TLB.scala:170:77] assign _entries_T_39 = _entries_WIRE_3[16]; // @[TLB.scala:170:77] wire _entries_WIRE_2_pf = _entries_T_39; // @[TLB.scala:170:77] assign _entries_T_40 = _entries_WIRE_3[17]; // @[TLB.scala:170:77] wire _entries_WIRE_2_ae_stage2 = _entries_T_40; // @[TLB.scala:170:77] assign _entries_T_41 = _entries_WIRE_3[18]; // @[TLB.scala:170:77] wire _entries_WIRE_2_ae_final = _entries_T_41; // @[TLB.scala:170:77] assign _entries_T_42 = _entries_WIRE_3[19]; // @[TLB.scala:170:77] wire _entries_WIRE_2_ae_ptw = _entries_T_42; // @[TLB.scala:170:77] assign _entries_T_43 = _entries_WIRE_3[20]; // @[TLB.scala:170:77] wire _entries_WIRE_2_g = _entries_T_43; // @[TLB.scala:170:77] assign _entries_T_44 = _entries_WIRE_3[21]; // @[TLB.scala:170:77] wire _entries_WIRE_2_u = _entries_T_44; // @[TLB.scala:170:77] assign _entries_T_45 = _entries_WIRE_3[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_2_ppn = _entries_T_45; // @[TLB.scala:170:77] wire [19:0] _entries_T_68; // @[TLB.scala:170:77] wire _entries_T_67; // @[TLB.scala:170:77] wire _entries_T_66; // @[TLB.scala:170:77] wire _entries_T_65; // @[TLB.scala:170:77] wire _entries_T_64; // @[TLB.scala:170:77] wire _entries_T_63; // @[TLB.scala:170:77] wire _entries_T_62; // @[TLB.scala:170:77] wire _entries_T_61; // @[TLB.scala:170:77] wire _entries_T_60; // @[TLB.scala:170:77] wire _entries_T_59; // @[TLB.scala:170:77] wire _entries_T_58; // @[TLB.scala:170:77] wire _entries_T_57; // @[TLB.scala:170:77] wire _entries_T_56; // @[TLB.scala:170:77] wire _entries_T_55; // @[TLB.scala:170:77] wire _entries_T_54; // @[TLB.scala:170:77] wire _entries_T_53; // @[TLB.scala:170:77] wire _entries_T_52; // @[TLB.scala:170:77] wire _entries_T_51; // @[TLB.scala:170:77] wire _entries_T_50; // @[TLB.scala:170:77] wire _entries_T_49; // @[TLB.scala:170:77] wire _entries_T_48; // @[TLB.scala:170:77] wire _entries_T_47; // @[TLB.scala:170:77] wire _entries_T_46; // @[TLB.scala:170:77] assign _entries_T_46 = _entries_WIRE_5[0]; // @[TLB.scala:170:77] wire _entries_WIRE_4_fragmented_superpage = _entries_T_46; // @[TLB.scala:170:77] assign _entries_T_47 = _entries_WIRE_5[1]; // @[TLB.scala:170:77] wire _entries_WIRE_4_c = _entries_T_47; // @[TLB.scala:170:77] assign _entries_T_48 = _entries_WIRE_5[2]; // @[TLB.scala:170:77] wire _entries_WIRE_4_eff = _entries_T_48; // @[TLB.scala:170:77] assign _entries_T_49 = _entries_WIRE_5[3]; // @[TLB.scala:170:77] wire _entries_WIRE_4_paa = _entries_T_49; // @[TLB.scala:170:77] assign _entries_T_50 = _entries_WIRE_5[4]; // @[TLB.scala:170:77] wire _entries_WIRE_4_pal = _entries_T_50; // @[TLB.scala:170:77] assign _entries_T_51 = _entries_WIRE_5[5]; // @[TLB.scala:170:77] wire _entries_WIRE_4_ppp = _entries_T_51; // @[TLB.scala:170:77] assign _entries_T_52 = _entries_WIRE_5[6]; // @[TLB.scala:170:77] wire _entries_WIRE_4_pr = _entries_T_52; // @[TLB.scala:170:77] assign _entries_T_53 = _entries_WIRE_5[7]; // @[TLB.scala:170:77] wire _entries_WIRE_4_px = _entries_T_53; // @[TLB.scala:170:77] assign _entries_T_54 = _entries_WIRE_5[8]; // @[TLB.scala:170:77] wire _entries_WIRE_4_pw = _entries_T_54; // @[TLB.scala:170:77] assign _entries_T_55 = _entries_WIRE_5[9]; // @[TLB.scala:170:77] wire _entries_WIRE_4_hr = _entries_T_55; // @[TLB.scala:170:77] assign _entries_T_56 = _entries_WIRE_5[10]; // @[TLB.scala:170:77] wire _entries_WIRE_4_hx = _entries_T_56; // @[TLB.scala:170:77] assign _entries_T_57 = _entries_WIRE_5[11]; // @[TLB.scala:170:77] wire _entries_WIRE_4_hw = _entries_T_57; // @[TLB.scala:170:77] assign _entries_T_58 = _entries_WIRE_5[12]; // @[TLB.scala:170:77] wire _entries_WIRE_4_sr = _entries_T_58; // @[TLB.scala:170:77] assign _entries_T_59 = _entries_WIRE_5[13]; // @[TLB.scala:170:77] wire _entries_WIRE_4_sx = _entries_T_59; // @[TLB.scala:170:77] assign _entries_T_60 = _entries_WIRE_5[14]; // @[TLB.scala:170:77] wire _entries_WIRE_4_sw = _entries_T_60; // @[TLB.scala:170:77] assign _entries_T_61 = _entries_WIRE_5[15]; // @[TLB.scala:170:77] wire _entries_WIRE_4_gf = _entries_T_61; // @[TLB.scala:170:77] assign _entries_T_62 = _entries_WIRE_5[16]; // @[TLB.scala:170:77] wire _entries_WIRE_4_pf = _entries_T_62; // @[TLB.scala:170:77] assign _entries_T_63 = _entries_WIRE_5[17]; // @[TLB.scala:170:77] wire _entries_WIRE_4_ae_stage2 = _entries_T_63; // @[TLB.scala:170:77] assign _entries_T_64 = _entries_WIRE_5[18]; // @[TLB.scala:170:77] wire _entries_WIRE_4_ae_final = _entries_T_64; // @[TLB.scala:170:77] assign _entries_T_65 = _entries_WIRE_5[19]; // @[TLB.scala:170:77] wire _entries_WIRE_4_ae_ptw = _entries_T_65; // @[TLB.scala:170:77] assign _entries_T_66 = _entries_WIRE_5[20]; // @[TLB.scala:170:77] wire _entries_WIRE_4_g = _entries_T_66; // @[TLB.scala:170:77] assign _entries_T_67 = _entries_WIRE_5[21]; // @[TLB.scala:170:77] wire _entries_WIRE_4_u = _entries_T_67; // @[TLB.scala:170:77] assign _entries_T_68 = _entries_WIRE_5[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_4_ppn = _entries_T_68; // @[TLB.scala:170:77] wire [19:0] _entries_T_91; // @[TLB.scala:170:77] wire _entries_T_90; // @[TLB.scala:170:77] wire _entries_T_89; // @[TLB.scala:170:77] wire _entries_T_88; // @[TLB.scala:170:77] wire _entries_T_87; // @[TLB.scala:170:77] wire _entries_T_86; // @[TLB.scala:170:77] wire _entries_T_85; // @[TLB.scala:170:77] wire _entries_T_84; // @[TLB.scala:170:77] wire _entries_T_83; // @[TLB.scala:170:77] wire _entries_T_82; // @[TLB.scala:170:77] wire _entries_T_81; // @[TLB.scala:170:77] wire _entries_T_80; // @[TLB.scala:170:77] wire _entries_T_79; // @[TLB.scala:170:77] wire _entries_T_78; // @[TLB.scala:170:77] wire _entries_T_77; // @[TLB.scala:170:77] wire _entries_T_76; // @[TLB.scala:170:77] wire _entries_T_75; // @[TLB.scala:170:77] wire _entries_T_74; // @[TLB.scala:170:77] wire _entries_T_73; // @[TLB.scala:170:77] wire _entries_T_72; // @[TLB.scala:170:77] wire _entries_T_71; // @[TLB.scala:170:77] wire _entries_T_70; // @[TLB.scala:170:77] wire _entries_T_69; // @[TLB.scala:170:77] assign _entries_T_69 = _entries_WIRE_7[0]; // @[TLB.scala:170:77] wire _entries_WIRE_6_fragmented_superpage = _entries_T_69; // @[TLB.scala:170:77] assign _entries_T_70 = _entries_WIRE_7[1]; // @[TLB.scala:170:77] wire _entries_WIRE_6_c = _entries_T_70; // @[TLB.scala:170:77] assign _entries_T_71 = _entries_WIRE_7[2]; // @[TLB.scala:170:77] wire _entries_WIRE_6_eff = _entries_T_71; // @[TLB.scala:170:77] assign _entries_T_72 = _entries_WIRE_7[3]; // @[TLB.scala:170:77] wire _entries_WIRE_6_paa = _entries_T_72; // @[TLB.scala:170:77] assign _entries_T_73 = _entries_WIRE_7[4]; // @[TLB.scala:170:77] wire _entries_WIRE_6_pal = _entries_T_73; // @[TLB.scala:170:77] assign _entries_T_74 = _entries_WIRE_7[5]; // @[TLB.scala:170:77] wire _entries_WIRE_6_ppp = _entries_T_74; // @[TLB.scala:170:77] assign _entries_T_75 = _entries_WIRE_7[6]; // @[TLB.scala:170:77] wire _entries_WIRE_6_pr = _entries_T_75; // @[TLB.scala:170:77] assign _entries_T_76 = _entries_WIRE_7[7]; // @[TLB.scala:170:77] wire _entries_WIRE_6_px = _entries_T_76; // @[TLB.scala:170:77] assign _entries_T_77 = _entries_WIRE_7[8]; // @[TLB.scala:170:77] wire _entries_WIRE_6_pw = _entries_T_77; // @[TLB.scala:170:77] assign _entries_T_78 = _entries_WIRE_7[9]; // @[TLB.scala:170:77] wire _entries_WIRE_6_hr = _entries_T_78; // @[TLB.scala:170:77] assign _entries_T_79 = _entries_WIRE_7[10]; // @[TLB.scala:170:77] wire _entries_WIRE_6_hx = _entries_T_79; // @[TLB.scala:170:77] assign _entries_T_80 = _entries_WIRE_7[11]; // @[TLB.scala:170:77] wire _entries_WIRE_6_hw = _entries_T_80; // @[TLB.scala:170:77] assign _entries_T_81 = _entries_WIRE_7[12]; // @[TLB.scala:170:77] wire _entries_WIRE_6_sr = _entries_T_81; // @[TLB.scala:170:77] assign _entries_T_82 = _entries_WIRE_7[13]; // @[TLB.scala:170:77] wire _entries_WIRE_6_sx = _entries_T_82; // @[TLB.scala:170:77] assign _entries_T_83 = _entries_WIRE_7[14]; // @[TLB.scala:170:77] wire _entries_WIRE_6_sw = _entries_T_83; // @[TLB.scala:170:77] assign _entries_T_84 = _entries_WIRE_7[15]; // @[TLB.scala:170:77] wire _entries_WIRE_6_gf = _entries_T_84; // @[TLB.scala:170:77] assign _entries_T_85 = _entries_WIRE_7[16]; // @[TLB.scala:170:77] wire _entries_WIRE_6_pf = _entries_T_85; // @[TLB.scala:170:77] assign _entries_T_86 = _entries_WIRE_7[17]; // @[TLB.scala:170:77] wire _entries_WIRE_6_ae_stage2 = _entries_T_86; // @[TLB.scala:170:77] assign _entries_T_87 = _entries_WIRE_7[18]; // @[TLB.scala:170:77] wire _entries_WIRE_6_ae_final = _entries_T_87; // @[TLB.scala:170:77] assign _entries_T_88 = _entries_WIRE_7[19]; // @[TLB.scala:170:77] wire _entries_WIRE_6_ae_ptw = _entries_T_88; // @[TLB.scala:170:77] assign _entries_T_89 = _entries_WIRE_7[20]; // @[TLB.scala:170:77] wire _entries_WIRE_6_g = _entries_T_89; // @[TLB.scala:170:77] assign _entries_T_90 = _entries_WIRE_7[21]; // @[TLB.scala:170:77] wire _entries_WIRE_6_u = _entries_T_90; // @[TLB.scala:170:77] assign _entries_T_91 = _entries_WIRE_7[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_6_ppn = _entries_T_91; // @[TLB.scala:170:77] wire [19:0] _entries_T_114; // @[TLB.scala:170:77] wire _entries_T_113; // @[TLB.scala:170:77] wire _entries_T_112; // @[TLB.scala:170:77] wire _entries_T_111; // @[TLB.scala:170:77] wire _entries_T_110; // @[TLB.scala:170:77] wire _entries_T_109; // @[TLB.scala:170:77] wire _entries_T_108; // @[TLB.scala:170:77] wire _entries_T_107; // @[TLB.scala:170:77] wire _entries_T_106; // @[TLB.scala:170:77] wire _entries_T_105; // @[TLB.scala:170:77] wire _entries_T_104; // @[TLB.scala:170:77] wire _entries_T_103; // @[TLB.scala:170:77] wire _entries_T_102; // @[TLB.scala:170:77] wire _entries_T_101; // @[TLB.scala:170:77] wire _entries_T_100; // @[TLB.scala:170:77] wire _entries_T_99; // @[TLB.scala:170:77] wire _entries_T_98; // @[TLB.scala:170:77] wire _entries_T_97; // @[TLB.scala:170:77] wire _entries_T_96; // @[TLB.scala:170:77] wire _entries_T_95; // @[TLB.scala:170:77] wire _entries_T_94; // @[TLB.scala:170:77] wire _entries_T_93; // @[TLB.scala:170:77] wire _entries_T_92; // @[TLB.scala:170:77] assign _entries_T_92 = _entries_WIRE_9[0]; // @[TLB.scala:170:77] wire _entries_WIRE_8_fragmented_superpage = _entries_T_92; // @[TLB.scala:170:77] assign _entries_T_93 = _entries_WIRE_9[1]; // @[TLB.scala:170:77] wire _entries_WIRE_8_c = _entries_T_93; // @[TLB.scala:170:77] assign _entries_T_94 = _entries_WIRE_9[2]; // @[TLB.scala:170:77] wire _entries_WIRE_8_eff = _entries_T_94; // @[TLB.scala:170:77] assign _entries_T_95 = _entries_WIRE_9[3]; // @[TLB.scala:170:77] wire _entries_WIRE_8_paa = _entries_T_95; // @[TLB.scala:170:77] assign _entries_T_96 = _entries_WIRE_9[4]; // @[TLB.scala:170:77] wire _entries_WIRE_8_pal = _entries_T_96; // @[TLB.scala:170:77] assign _entries_T_97 = _entries_WIRE_9[5]; // @[TLB.scala:170:77] wire _entries_WIRE_8_ppp = _entries_T_97; // @[TLB.scala:170:77] assign _entries_T_98 = _entries_WIRE_9[6]; // @[TLB.scala:170:77] wire _entries_WIRE_8_pr = _entries_T_98; // @[TLB.scala:170:77] assign _entries_T_99 = _entries_WIRE_9[7]; // @[TLB.scala:170:77] wire _entries_WIRE_8_px = _entries_T_99; // @[TLB.scala:170:77] assign _entries_T_100 = _entries_WIRE_9[8]; // @[TLB.scala:170:77] wire _entries_WIRE_8_pw = _entries_T_100; // @[TLB.scala:170:77] assign _entries_T_101 = _entries_WIRE_9[9]; // @[TLB.scala:170:77] wire _entries_WIRE_8_hr = _entries_T_101; // @[TLB.scala:170:77] assign _entries_T_102 = _entries_WIRE_9[10]; // @[TLB.scala:170:77] wire _entries_WIRE_8_hx = _entries_T_102; // @[TLB.scala:170:77] assign _entries_T_103 = _entries_WIRE_9[11]; // @[TLB.scala:170:77] wire _entries_WIRE_8_hw = _entries_T_103; // @[TLB.scala:170:77] assign _entries_T_104 = _entries_WIRE_9[12]; // @[TLB.scala:170:77] wire _entries_WIRE_8_sr = _entries_T_104; // @[TLB.scala:170:77] assign _entries_T_105 = _entries_WIRE_9[13]; // @[TLB.scala:170:77] wire _entries_WIRE_8_sx = _entries_T_105; // @[TLB.scala:170:77] assign _entries_T_106 = _entries_WIRE_9[14]; // @[TLB.scala:170:77] wire _entries_WIRE_8_sw = _entries_T_106; // @[TLB.scala:170:77] assign _entries_T_107 = _entries_WIRE_9[15]; // @[TLB.scala:170:77] wire _entries_WIRE_8_gf = _entries_T_107; // @[TLB.scala:170:77] assign _entries_T_108 = _entries_WIRE_9[16]; // @[TLB.scala:170:77] wire _entries_WIRE_8_pf = _entries_T_108; // @[TLB.scala:170:77] assign _entries_T_109 = _entries_WIRE_9[17]; // @[TLB.scala:170:77] wire _entries_WIRE_8_ae_stage2 = _entries_T_109; // @[TLB.scala:170:77] assign _entries_T_110 = _entries_WIRE_9[18]; // @[TLB.scala:170:77] wire _entries_WIRE_8_ae_final = _entries_T_110; // @[TLB.scala:170:77] assign _entries_T_111 = _entries_WIRE_9[19]; // @[TLB.scala:170:77] wire _entries_WIRE_8_ae_ptw = _entries_T_111; // @[TLB.scala:170:77] assign _entries_T_112 = _entries_WIRE_9[20]; // @[TLB.scala:170:77] wire _entries_WIRE_8_g = _entries_T_112; // @[TLB.scala:170:77] assign _entries_T_113 = _entries_WIRE_9[21]; // @[TLB.scala:170:77] wire _entries_WIRE_8_u = _entries_T_113; // @[TLB.scala:170:77] assign _entries_T_114 = _entries_WIRE_9[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_8_ppn = _entries_T_114; // @[TLB.scala:170:77] wire [19:0] _entries_T_137; // @[TLB.scala:170:77] wire _entries_T_136; // @[TLB.scala:170:77] wire _entries_T_135; // @[TLB.scala:170:77] wire _entries_T_134; // @[TLB.scala:170:77] wire _entries_T_133; // @[TLB.scala:170:77] wire _entries_T_132; // @[TLB.scala:170:77] wire _entries_T_131; // @[TLB.scala:170:77] wire _entries_T_130; // @[TLB.scala:170:77] wire _entries_T_129; // @[TLB.scala:170:77] wire _entries_T_128; // @[TLB.scala:170:77] wire _entries_T_127; // @[TLB.scala:170:77] wire _entries_T_126; // @[TLB.scala:170:77] wire _entries_T_125; // @[TLB.scala:170:77] wire _entries_T_124; // @[TLB.scala:170:77] wire _entries_T_123; // @[TLB.scala:170:77] wire _entries_T_122; // @[TLB.scala:170:77] wire _entries_T_121; // @[TLB.scala:170:77] wire _entries_T_120; // @[TLB.scala:170:77] wire _entries_T_119; // @[TLB.scala:170:77] wire _entries_T_118; // @[TLB.scala:170:77] wire _entries_T_117; // @[TLB.scala:170:77] wire _entries_T_116; // @[TLB.scala:170:77] wire _entries_T_115; // @[TLB.scala:170:77] assign _entries_T_115 = _entries_WIRE_11[0]; // @[TLB.scala:170:77] wire _entries_WIRE_10_fragmented_superpage = _entries_T_115; // @[TLB.scala:170:77] assign _entries_T_116 = _entries_WIRE_11[1]; // @[TLB.scala:170:77] wire _entries_WIRE_10_c = _entries_T_116; // @[TLB.scala:170:77] assign _entries_T_117 = _entries_WIRE_11[2]; // @[TLB.scala:170:77] wire _entries_WIRE_10_eff = _entries_T_117; // @[TLB.scala:170:77] assign _entries_T_118 = _entries_WIRE_11[3]; // @[TLB.scala:170:77] wire _entries_WIRE_10_paa = _entries_T_118; // @[TLB.scala:170:77] assign _entries_T_119 = _entries_WIRE_11[4]; // @[TLB.scala:170:77] wire _entries_WIRE_10_pal = _entries_T_119; // @[TLB.scala:170:77] assign _entries_T_120 = _entries_WIRE_11[5]; // @[TLB.scala:170:77] wire _entries_WIRE_10_ppp = _entries_T_120; // @[TLB.scala:170:77] assign _entries_T_121 = _entries_WIRE_11[6]; // @[TLB.scala:170:77] wire _entries_WIRE_10_pr = _entries_T_121; // @[TLB.scala:170:77] assign _entries_T_122 = _entries_WIRE_11[7]; // @[TLB.scala:170:77] wire _entries_WIRE_10_px = _entries_T_122; // @[TLB.scala:170:77] assign _entries_T_123 = _entries_WIRE_11[8]; // @[TLB.scala:170:77] wire _entries_WIRE_10_pw = _entries_T_123; // @[TLB.scala:170:77] assign _entries_T_124 = _entries_WIRE_11[9]; // @[TLB.scala:170:77] wire _entries_WIRE_10_hr = _entries_T_124; // @[TLB.scala:170:77] assign _entries_T_125 = _entries_WIRE_11[10]; // @[TLB.scala:170:77] wire _entries_WIRE_10_hx = _entries_T_125; // @[TLB.scala:170:77] assign _entries_T_126 = _entries_WIRE_11[11]; // @[TLB.scala:170:77] wire _entries_WIRE_10_hw = _entries_T_126; // @[TLB.scala:170:77] assign _entries_T_127 = _entries_WIRE_11[12]; // @[TLB.scala:170:77] wire _entries_WIRE_10_sr = _entries_T_127; // @[TLB.scala:170:77] assign _entries_T_128 = _entries_WIRE_11[13]; // @[TLB.scala:170:77] wire _entries_WIRE_10_sx = _entries_T_128; // @[TLB.scala:170:77] assign _entries_T_129 = _entries_WIRE_11[14]; // @[TLB.scala:170:77] wire _entries_WIRE_10_sw = _entries_T_129; // @[TLB.scala:170:77] assign _entries_T_130 = _entries_WIRE_11[15]; // @[TLB.scala:170:77] wire _entries_WIRE_10_gf = _entries_T_130; // @[TLB.scala:170:77] assign _entries_T_131 = _entries_WIRE_11[16]; // @[TLB.scala:170:77] wire _entries_WIRE_10_pf = _entries_T_131; // @[TLB.scala:170:77] assign _entries_T_132 = _entries_WIRE_11[17]; // @[TLB.scala:170:77] wire _entries_WIRE_10_ae_stage2 = _entries_T_132; // @[TLB.scala:170:77] assign _entries_T_133 = _entries_WIRE_11[18]; // @[TLB.scala:170:77] wire _entries_WIRE_10_ae_final = _entries_T_133; // @[TLB.scala:170:77] assign _entries_T_134 = _entries_WIRE_11[19]; // @[TLB.scala:170:77] wire _entries_WIRE_10_ae_ptw = _entries_T_134; // @[TLB.scala:170:77] assign _entries_T_135 = _entries_WIRE_11[20]; // @[TLB.scala:170:77] wire _entries_WIRE_10_g = _entries_T_135; // @[TLB.scala:170:77] assign _entries_T_136 = _entries_WIRE_11[21]; // @[TLB.scala:170:77] wire _entries_WIRE_10_u = _entries_T_136; // @[TLB.scala:170:77] assign _entries_T_137 = _entries_WIRE_11[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_10_ppn = _entries_T_137; // @[TLB.scala:170:77] wire _ppn_T = ~vm_enabled; // @[TLB.scala:399:61, :442:18, :502:30] wire [1:0] ppn_res = _entries_barrier_4_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore = _ppn_ignore_T; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_1 = ppn_ignore ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_2 = {_ppn_T_1[26:20], _ppn_T_1[19:0] \| _entries_barrier_4_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_3 = _ppn_T_2[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _ppn_T_4 = {ppn_res, _ppn_T_3}; // @[TLB.scala:195:26, :198:{18,58}] wire _ppn_ignore_T_1 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :197:28, :341:30] wire [26:0] _ppn_T_6 = {_ppn_T_5[26:20], _ppn_T_5[19:0] \| _entries_barrier_4_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_7 = _ppn_T_6[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _ppn_T_8 = {_ppn_T_4, _ppn_T_7}; // @[TLB.scala:198:{18,58}] wire [1:0] ppn_res_1 = _entries_barrier_5_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore_2 = _ppn_ignore_T_2; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_9 = ppn_ignore_2 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_10 = {_ppn_T_9[26:20], _ppn_T_9[19:0] \| _entries_barrier_5_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_11 = _ppn_T_10[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _ppn_T_12 = {ppn_res_1, _ppn_T_11}; // @[TLB.scala:195:26, :198:{18,58}] wire _ppn_ignore_T_3 = ~(special_entry_level[1]); // @[TLB.scala:197:28, :346:56] wire ppn_ignore_3 = _ppn_ignore_T_3; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_13 = ppn_ignore_3 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_14 = {_ppn_T_13[26:20], _ppn_T_13[19:0] \| _entries_barrier_5_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_15 = _ppn_T_14[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _ppn_T_16 = {_ppn_T_12, _ppn_T_15}; // @[TLB.scala:198:{18,58}] wire [19:0] _ppn_T_17 = vpn[19:0]; // @[TLB.scala:335:30, :502:125] wire [19:0] _ppn_T_18 = hitsVec_0 ? _entries_barrier_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_19 = hitsVec_1 ? _entries_barrier_1_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_20 = hitsVec_2 ? _entries_barrier_2_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_21 = hitsVec_3 ? _entries_barrier_3_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_22 = hitsVec_4 ? _ppn_T_8 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_23 = hitsVec_5 ? _ppn_T_16 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_24 = _ppn_T ? _ppn_T_17 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_25 = _ppn_T_18 \| _ppn_T_19; // @[Mux.scala:30:73] wire [19:0] _ppn_T_26 = _ppn_T_25 \| _ppn_T_20; // @[Mux.scala:30:73] wire [19:0] _ppn_T_27 = _ppn_T_26 \| _ppn_T_21; // @[Mux.scala:30:73] wire [19:0] _ppn_T_28 = _ppn_T_27 \| _ppn_T_22; // @[Mux.scala:30:73] wire [19:0] _ppn_T_29 = _ppn_T_28 \| _ppn_T_23; // @[Mux.scala:30:73] wire [19:0] _ppn_T_30 = _ppn_T_29 \| _ppn_T_24; // @[Mux.scala:30:73] wire [19:0] ppn = _ppn_T_30; // @[Mux.scala:30:73] wire [1:0] ptw_ae_array_lo_hi = {_entries_barrier_2_io_y_ae_ptw, _entries_barrier_1_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_ae_array_lo = {ptw_ae_array_lo_hi, _entries_barrier_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_ae_array_hi_hi = {_entries_barrier_5_io_y_ae_ptw, _entries_barrier_4_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_ae_array_hi = {ptw_ae_array_hi_hi, _entries_barrier_3_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [5:0] _ptw_ae_array_T = {ptw_ae_array_hi, ptw_ae_array_lo}; // @[package.scala:45:27] wire [6:0] ptw_ae_array = {1'h0, _ptw_ae_array_T}; // @[package.scala:45:27] wire [1:0] final_ae_array_lo_hi = {_entries_barrier_2_io_y_ae_final, _entries_barrier_1_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [2:0] final_ae_array_lo = {final_ae_array_lo_hi, _entries_barrier_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [1:0] final_ae_array_hi_hi = {_entries_barrier_5_io_y_ae_final, _entries_barrier_4_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [2:0] final_ae_array_hi = {final_ae_array_hi_hi, _entries_barrier_3_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [5:0] _final_ae_array_T = {final_ae_array_hi, final_ae_array_lo}; // @[package.scala:45:27] wire [6:0] final_ae_array = {1'h0, _final_ae_array_T}; // @[package.scala:45:27] wire [1:0] ptw_pf_array_lo_hi = {_entries_barrier_2_io_y_pf, _entries_barrier_1_io_y_pf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_pf_array_lo = {ptw_pf_array_lo_hi, _entries_barrier_io_y_pf}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_pf_array_hi_hi = {_entries_barrier_5_io_y_pf, _entries_barrier_4_io_y_pf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_pf_array_hi = {ptw_pf_array_hi_hi, _entries_barrier_3_io_y_pf}; // @[package.scala:45:27, :267:25] wire [5:0] _ptw_pf_array_T = {ptw_pf_array_hi, ptw_pf_array_lo}; // @[package.scala:45:27] wire [6:0] ptw_pf_array = {1'h0, _ptw_pf_array_T}; // @[package.scala:45:27] wire [1:0] ptw_gf_array_lo_hi = {_entries_barrier_2_io_y_gf, _entries_barrier_1_io_y_gf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_gf_array_lo = {ptw_gf_array_lo_hi, _entries_barrier_io_y_gf}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_gf_array_hi_hi = {_entries_barrier_5_io_y_gf, _entries_barrier_4_io_y_gf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_gf_array_hi = {ptw_gf_array_hi_hi, _entries_barrier_3_io_y_gf}; // @[package.scala:45:27, :267:25] wire [5:0] _ptw_gf_array_T = {ptw_gf_array_hi, ptw_gf_array_lo}; // @[package.scala:45:27] wire [6:0] ptw_gf_array = {1'h0, _ptw_gf_array_T}; // @[package.scala:45:27] wire [6:0] _gf_ld_array_T_3 = ptw_gf_array; // @[TLB.scala:509:25, :600:82] wire [6:0] _gf_st_array_T_2 = ptw_gf_array; // @[TLB.scala:509:25, :601:63] wire [6:0] _gf_inst_array_T_1 = ptw_gf_array; // @[TLB.scala:509:25, :602:46] wire [1:0] _GEN_33 = {_entries_barrier_2_io_y_u, _entries_barrier_1_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] priv_rw_ok_lo_hi; // @[package.scala:45:27] assign priv_rw_ok_lo_hi = _GEN_33; // @[package.scala:45:27] wire [1:0] priv_rw_ok_lo_hi_1; // @[package.scala:45:27] assign priv_rw_ok_lo_hi_1 = _GEN_33; // @[package.scala:45:27] wire [1:0] priv_x_ok_lo_hi; // @[package.scala:45:27] assign priv_x_ok_lo_hi = _GEN_33; // @[package.scala:45:27] wire [1:0] priv_x_ok_lo_hi_1; // @[package.scala:45:27] assign priv_x_ok_lo_hi_1 = _GEN_33; // @[package.scala:45:27] wire [2:0] priv_rw_ok_lo = {priv_rw_ok_lo_hi, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_34 = {_entries_barrier_5_io_y_u, _entries_barrier_4_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] priv_rw_ok_hi_hi; // @[package.scala:45:27] assign priv_rw_ok_hi_hi = _GEN_34; // @[package.scala:45:27] wire [1:0] priv_rw_ok_hi_hi_1; // @[package.scala:45:27] assign priv_rw_ok_hi_hi_1 = _GEN_34; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_hi; // @[package.scala:45:27] assign priv_x_ok_hi_hi = _GEN_34; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_hi_1; // @[package.scala:45:27] assign priv_x_ok_hi_hi_1 = _GEN_34; // @[package.scala:45:27] wire [2:0] priv_rw_ok_hi = {priv_rw_ok_hi_hi, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] _priv_rw_ok_T_2 = {priv_rw_ok_hi, priv_rw_ok_lo}; // @[package.scala:45:27] wire [5:0] _priv_rw_ok_T_3 = _priv_rw_ok_T_2; // @[package.scala:45:27] wire [5:0] priv_rw_ok = _priv_rw_ok_T_3; // @[TLB.scala:513:{23,70}] wire [2:0] priv_rw_ok_lo_1 = {priv_rw_ok_lo_hi_1, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] priv_rw_ok_hi_1 = {priv_rw_ok_hi_hi_1, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] _priv_rw_ok_T_4 = {priv_rw_ok_hi_1, priv_rw_ok_lo_1}; // @[package.scala:45:27] wire [5:0] _priv_rw_ok_T_5 = ~_priv_rw_ok_T_4; // @[package.scala:45:27] wire [2:0] priv_x_ok_lo = {priv_x_ok_lo_hi, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] priv_x_ok_hi = {priv_x_ok_hi_hi, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] _priv_x_ok_T = {priv_x_ok_hi, priv_x_ok_lo}; // @[package.scala:45:27] wire [5:0] _priv_x_ok_T_1 = ~_priv_x_ok_T; // @[package.scala:45:27] wire [2:0] priv_x_ok_lo_1 = {priv_x_ok_lo_hi_1, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] priv_x_ok_hi_1 = {priv_x_ok_hi_hi_1, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] _priv_x_ok_T_2 = {priv_x_ok_hi_1, priv_x_ok_lo_1}; // @[package.scala:45:27] wire [5:0] priv_x_ok = _priv_x_ok_T_2; // @[package.scala:45:27] wire _stage1_bypass_T_1 = ~stage1_en; // @[TLB.scala:374:29, :517:83] wire [5:0] _stage1_bypass_T_2 = {6{_stage1_bypass_T_1}}; // @[TLB.scala:517:{68,83}] wire [1:0] stage1_bypass_lo_hi = {_entries_barrier_2_io_y_ae_stage2, _entries_barrier_1_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [2:0] stage1_bypass_lo = {stage1_bypass_lo_hi, _entries_barrier_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [1:0] stage1_bypass_hi_hi = {_entries_barrier_5_io_y_ae_stage2, _entries_barrier_4_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [2:0] stage1_bypass_hi = {stage1_bypass_hi_hi, _entries_barrier_3_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [5:0] _stage1_bypass_T_3 = {stage1_bypass_hi, stage1_bypass_lo}; // @[package.scala:45:27] wire [5:0] _stage1_bypass_T_4 = _stage1_bypass_T_2 \| _stage1_bypass_T_3; // @[package.scala:45:27] wire [1:0] r_array_lo_hi = {_entries_barrier_2_io_y_sr, _entries_barrier_1_io_y_sr}; // @[package.scala:45:27, :267:25] wire [2:0] r_array_lo = {r_array_lo_hi, _entries_barrier_io_y_sr}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_hi_hi = {_entries_barrier_5_io_y_sr, _entries_barrier_4_io_y_sr}; // @[package.scala:45:27, :267:25] wire [2:0] r_array_hi = {r_array_hi_hi, _entries_barrier_3_io_y_sr}; // @[package.scala:45:27, :267:25] wire [5:0] _r_array_T = {r_array_hi, r_array_lo}; // @[package.scala:45:27] wire [1:0] _GEN_35 = {_entries_barrier_2_io_y_sx, _entries_barrier_1_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_lo_hi_1; // @[package.scala:45:27] assign r_array_lo_hi_1 = _GEN_35; // @[package.scala:45:27] wire [1:0] x_array_lo_hi; // @[package.scala:45:27] assign x_array_lo_hi = _GEN_35; // @[package.scala:45:27] wire [2:0] r_array_lo_1 = {r_array_lo_hi_1, _entries_barrier_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_36 = {_entries_barrier_5_io_y_sx, _entries_barrier_4_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_hi_hi_1; // @[package.scala:45:27] assign r_array_hi_hi_1 = _GEN_36; // @[package.scala:45:27] wire [1:0] x_array_hi_hi; // @[package.scala:45:27] assign x_array_hi_hi = _GEN_36; // @[package.scala:45:27] wire [2:0] r_array_hi_1 = {r_array_hi_hi_1, _entries_barrier_3_io_y_sx}; // @[package.scala:45:27, :267:25] wire [5:0] _r_array_T_1 = {r_array_hi_1, r_array_lo_1}; // @[package.scala:45:27] wire [5:0] _r_array_T_2 = mxr ? _r_array_T_1 : 6'h0; // @[package.scala:45:27] wire [5:0] _r_array_T_3 = _r_array_T \| _r_array_T_2; // @[package.scala:45:27] wire [5:0] _r_array_T_4 = priv_rw_ok & _r_array_T_3; // @[TLB.scala:513:70, :520:{41,69}] wire [5:0] _r_array_T_5 = _r_array_T_4; // @[TLB.scala:520:{41,113}] wire [6:0] r_array = {1'h1, _r_array_T_5}; // @[TLB.scala:520:{20,113}] wire [6:0] _pf_ld_array_T = r_array; // @[TLB.scala:520:20, :597:41] wire [1:0] w_array_lo_hi = {_entries_barrier_2_io_y_sw, _entries_barrier_1_io_y_sw}; // @[package.scala:45:27, :267:25] wire [2:0] w_array_lo = {w_array_lo_hi, _entries_barrier_io_y_sw}; // @[package.scala:45:27, :267:25] wire [1:0] w_array_hi_hi = {_entries_barrier_5_io_y_sw, _entries_barrier_4_io_y_sw}; // @[package.scala:45:27, :267:25] wire [2:0] w_array_hi = {w_array_hi_hi, _entries_barrier_3_io_y_sw}; // @[package.scala:45:27, :267:25] wire [5:0] _w_array_T = {w_array_hi, w_array_lo}; // @[package.scala:45:27] wire [5:0] _w_array_T_1 = priv_rw_ok & _w_array_T; // @[package.scala:45:27] wire [5:0] _w_array_T_2 = _w_array_T_1; // @[TLB.scala:521:{41,69}] wire [6:0] w_array = {1'h1, _w_array_T_2}; // @[TLB.scala:521:{20,69}] wire [2:0] x_array_lo = {x_array_lo_hi, _entries_barrier_io_y_sx}; // @[package.scala:45:27, :267:25] wire [2:0] x_array_hi = {x_array_hi_hi, _entries_barrier_3_io_y_sx}; // @[package.scala:45:27, :267:25] wire [5:0] _x_array_T = {x_array_hi, x_array_lo}; // @[package.scala:45:27] wire [5:0] _x_array_T_1 = priv_x_ok & _x_array_T; // @[package.scala:45:27] wire [5:0] _x_array_T_2 = _x_array_T_1; // @[TLB.scala:522:{40,68}] wire [6:0] x_array = {1'h1, _x_array_T_2}; // @[TLB.scala:522:{20,68}] wire [1:0] hr_array_lo_hi = {_entries_barrier_2_io_y_hr, _entries_barrier_1_io_y_hr}; // @[package.scala:45:27, :267:25] wire [2:0] hr_array_lo = {hr_array_lo_hi, _entries_barrier_io_y_hr}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_hi_hi = {_entries_barrier_5_io_y_hr, _entries_barrier_4_io_y_hr}; // @[package.scala:45:27, :267:25] wire [2:0] hr_array_hi = {hr_array_hi_hi, _entries_barrier_3_io_y_hr}; // @[package.scala:45:27, :267:25] wire [5:0] _hr_array_T = {hr_array_hi, hr_array_lo}; // @[package.scala:45:27] wire [1:0] _GEN_37 = {_entries_barrier_2_io_y_hx, _entries_barrier_1_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_lo_hi_1; // @[package.scala:45:27] assign hr_array_lo_hi_1 = _GEN_37; // @[package.scala:45:27] wire [1:0] hx_array_lo_hi; // @[package.scala:45:27] assign hx_array_lo_hi = _GEN_37; // @[package.scala:45:27] wire [2:0] hr_array_lo_1 = {hr_array_lo_hi_1, _entries_barrier_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_38 = {_entries_barrier_5_io_y_hx, _entries_barrier_4_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_hi_hi_1; // @[package.scala:45:27] assign hr_array_hi_hi_1 = _GEN_38; // @[package.scala:45:27] wire [1:0] hx_array_hi_hi; // @[package.scala:45:27] assign hx_array_hi_hi = _GEN_38; // @[package.scala:45:27] wire [2:0] hr_array_hi_1 = {hr_array_hi_hi_1, _entries_barrier_3_io_y_hx}; // @[package.scala:45:27, :267:25] wire [5:0] _hr_array_T_1 = {hr_array_hi_1, hr_array_lo_1}; // @[package.scala:45:27] wire [5:0] _hr_array_T_2 = io_ptw_status_mxr_0 ? _hr_array_T_1 : 6'h0; // @[package.scala:45:27] wire [5:0] _hr_array_T_3 = _hr_array_T \| _hr_array_T_2; // @[package.scala:45:27] wire [1:0] hw_array_lo_hi = {_entries_barrier_2_io_y_hw, _entries_barrier_1_io_y_hw}; // @[package.scala:45:27, :267:25] wire [2:0] hw_array_lo = {hw_array_lo_hi, _entries_barrier_io_y_hw}; // @[package.scala:45:27, :267:25] wire [1:0] hw_array_hi_hi = {_entries_barrier_5_io_y_hw, _entries_barrier_4_io_y_hw}; // @[package.scala:45:27, :267:25] wire [2:0] hw_array_hi = {hw_array_hi_hi, _entries_barrier_3_io_y_hw}; // @[package.scala:45:27, :267:25] wire [5:0] _hw_array_T = {hw_array_hi, hw_array_lo}; // @[package.scala:45:27] wire [2:0] hx_array_lo = {hx_array_lo_hi, _entries_barrier_io_y_hx}; // @[package.scala:45:27, :267:25] wire [2:0] hx_array_hi = {hx_array_hi_hi, _entries_barrier_3_io_y_hx}; // @[package.scala:45:27, :267:25] wire [5:0] _hx_array_T = {hx_array_hi, hx_array_lo}; // @[package.scala:45:27] wire [1:0] _pr_array_T = {2{prot_r}}; // @[TLB.scala:429:55, :529:26] wire [1:0] pr_array_lo = {_entries_barrier_1_io_y_pr, _entries_barrier_io_y_pr}; // @[package.scala:45:27, :267:25] wire [1:0] pr_array_hi_hi = {_entries_barrier_4_io_y_pr, _entries_barrier_3_io_y_pr}; // @[package.scala:45:27, :267:25] wire [2:0] pr_array_hi = {pr_array_hi_hi, _entries_barrier_2_io_y_pr}; // @[package.scala:45:27, :267:25] wire [4:0] _pr_array_T_1 = {pr_array_hi, pr_array_lo}; // @[package.scala:45:27] wire [6:0] _pr_array_T_2 = {_pr_array_T, _pr_array_T_1}; // @[package.scala:45:27] wire [6:0] _GEN_39 = ptw_ae_array \| final_ae_array; // @[TLB.scala:506:25, :507:27, :529:104] wire [6:0] _pr_array_T_3; // @[TLB.scala:529:104] assign _pr_array_T_3 = _GEN_39; // @[TLB.scala:529:104] wire [6:0] _pw_array_T_3; // @[TLB.scala:531:104] assign _pw_array_T_3 = _GEN_39; // @[TLB.scala:529:104, :531:104] wire [6:0] _px_array_T_3; // @[TLB.scala:533:104] assign _px_array_T_3 = _GEN_39; // @[TLB.scala:529:104, :533:104] wire [6:0] _pr_array_T_4 = ~_pr_array_T_3; // @[TLB.scala:529:{89,104}] wire [6:0] pr_array = _pr_array_T_2 & _pr_array_T_4; // @[TLB.scala:529:{21,87,89}] wire [1:0] _pw_array_T = {2{prot_w}}; // @[TLB.scala:430:55, :531:26] wire [1:0] pw_array_lo = {_entries_barrier_1_io_y_pw, _entries_barrier_io_y_pw}; // @[package.scala:45:27, :267:25] wire [1:0] pw_array_hi_hi = {_entries_barrier_4_io_y_pw, _entries_barrier_3_io_y_pw}; // @[package.scala:45:27, :267:25] wire [2:0] pw_array_hi = {pw_array_hi_hi, _entries_barrier_2_io_y_pw}; // @[package.scala:45:27, :267:25] wire [4:0] _pw_array_T_1 = {pw_array_hi, pw_array_lo}; // @[package.scala:45:27] wire [6:0] _pw_array_T_2 = {_pw_array_T, _pw_array_T_1}; // @[package.scala:45:27] wire [6:0] _pw_array_T_4 = ~_pw_array_T_3; // @[TLB.scala:531:{89,104}] wire [6:0] pw_array = _pw_array_T_2 & _pw_array_T_4; // @[TLB.scala:531:{21,87,89}] wire [1:0] _px_array_T = {2{prot_x}}; // @[TLB.scala:434:55, :533:26] wire [1:0] px_array_lo = {_entries_barrier_1_io_y_px, _entries_barrier_io_y_px}; // @[package.scala:45:27, :267:25] wire [1:0] px_array_hi_hi = {_entries_barrier_4_io_y_px, _entries_barrier_3_io_y_px}; // @[package.scala:45:27, :267:25] wire [2:0] px_array_hi = {px_array_hi_hi, _entries_barrier_2_io_y_px}; // @[package.scala:45:27, :267:25] wire [4:0] _px_array_T_1 = {px_array_hi, px_array_lo}; // @[package.scala:45:27] wire [6:0] _px_array_T_2 = {_px_array_T, _px_array_T_1}; // @[package.scala:45:27] wire [6:0] _px_array_T_4 = ~_px_array_T_3; // @[TLB.scala:533:{89,104}] wire [6:0] px_array = _px_array_T_2 & _px_array_T_4; // @[TLB.scala:533:{21,87,89}] wire [1:0] _eff_array_T = {2{_pma_io_resp_eff}}; // @[TLB.scala:422:19, :535:27] wire [1:0] eff_array_lo = {_entries_barrier_1_io_y_eff, _entries_barrier_io_y_eff}; // @[package.scala:45:27, :267:25] wire [1:0] eff_array_hi_hi = {_entries_barrier_4_io_y_eff, _entries_barrier_3_io_y_eff}; // @[package.scala:45:27, :267:25] wire [2:0] eff_array_hi = {eff_array_hi_hi, _entries_barrier_2_io_y_eff}; // @[package.scala:45:27, :267:25] wire [4:0] _eff_array_T_1 = {eff_array_hi, eff_array_lo}; // @[package.scala:45:27] wire [6:0] eff_array = {_eff_array_T, _eff_array_T_1}; // @[package.scala:45:27] wire [1:0] _c_array_T = {2{cacheable}}; // @[TLB.scala:425:41, :537:25] wire [1:0] _GEN_40 = {_entries_barrier_1_io_y_c, _entries_barrier_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] c_array_lo; // @[package.scala:45:27] assign c_array_lo = _GEN_40; // @[package.scala:45:27] wire [1:0] prefetchable_array_lo; // @[package.scala:45:27] assign prefetchable_array_lo = _GEN_40; // @[package.scala:45:27] wire [1:0] _GEN_41 = {_entries_barrier_4_io_y_c, _entries_barrier_3_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] c_array_hi_hi; // @[package.scala:45:27] assign c_array_hi_hi = _GEN_41; // @[package.scala:45:27] wire [1:0] prefetchable_array_hi_hi; // @[package.scala:45:27] assign prefetchable_array_hi_hi = _GEN_41; // @[package.scala:45:27] wire [2:0] c_array_hi = {c_array_hi_hi, _entries_barrier_2_io_y_c}; // @[package.scala:45:27, :267:25] wire [4:0] _c_array_T_1 = {c_array_hi, c_array_lo}; // @[package.scala:45:27] wire [6:0] c_array = {_c_array_T, _c_array_T_1}; // @[package.scala:45:27] wire [6:0] lrscAllowed = c_array; // @[TLB.scala:537:20, :580:24] wire [1:0] _ppp_array_T = {2{_pma_io_resp_pp}}; // @[TLB.scala:422:19, :539:27] wire [1:0] ppp_array_lo = {_entries_barrier_1_io_y_ppp, _entries_barrier_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [1:0] ppp_array_hi_hi = {_entries_barrier_4_io_y_ppp, _entries_barrier_3_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [2:0] ppp_array_hi = {ppp_array_hi_hi, _entries_barrier_2_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [4:0] _ppp_array_T_1 = {ppp_array_hi, ppp_array_lo}; // @[package.scala:45:27] wire [6:0] ppp_array = {_ppp_array_T, _ppp_array_T_1}; // @[package.scala:45:27] wire [1:0] _paa_array_T = {2{_pma_io_resp_aa}}; // @[TLB.scala:422:19, :541:27] wire [1:0] paa_array_lo = {_entries_barrier_1_io_y_paa, _entries_barrier_io_y_paa}; // @[package.scala:45:27, :267:25] wire [1:0] paa_array_hi_hi = {_entries_barrier_4_io_y_paa, _entries_barrier_3_io_y_paa}; // @[package.scala:45:27, :267:25] wire [2:0] paa_array_hi = {paa_array_hi_hi, _entries_barrier_2_io_y_paa}; // @[package.scala:45:27, :267:25] wire [4:0] _paa_array_T_1 = {paa_array_hi, paa_array_lo}; // @[package.scala:45:27] wire [6:0] paa_array = {_paa_array_T, _paa_array_T_1}; // @[package.scala:45:27] wire [1:0] _pal_array_T = {2{_pma_io_resp_al}}; // @[TLB.scala:422:19, :543:27] wire [1:0] pal_array_lo = {_entries_barrier_1_io_y_pal, _entries_barrier_io_y_pal}; // @[package.scala:45:27, :267:25] wire [1:0] pal_array_hi_hi = {_entries_barrier_4_io_y_pal, _entries_barrier_3_io_y_pal}; // @[package.scala:45:27, :267:25] wire [2:0] pal_array_hi = {pal_array_hi_hi, _entries_barrier_2_io_y_pal}; // @[package.scala:45:27, :267:25] wire [4:0] _pal_array_T_1 = {pal_array_hi, pal_array_lo}; // @[package.scala:45:27] wire [6:0] pal_array = {_pal_array_T, _pal_array_T_1}; // @[package.scala:45:27] wire [6:0] ppp_array_if_cached = ppp_array \| c_array; // @[TLB.scala:537:20, :539:22, :544:39] wire [6:0] paa_array_if_cached = paa_array \| c_array; // @[TLB.scala:537:20, :541:22, :545:39] wire [6:0] pal_array_if_cached = pal_array \| c_array; // @[TLB.scala:537:20, :543:22, :546:39] wire _prefetchable_array_T = cacheable & homogeneous; // @[TLBPermissions.scala:101:65] wire [1:0] _prefetchable_array_T_1 = {_prefetchable_array_T, 1'h0}; // @[TLB.scala:547:{43,59}] wire [2:0] prefetchable_array_hi = {prefetchable_array_hi_hi, _entries_barrier_2_io_y_c}; // @[package.scala:45:27, :267:25] wire [4:0] _prefetchable_array_T_2 = {prefetchable_array_hi, prefetchable_array_lo}; // @[package.scala:45:27] wire [6:0] prefetchable_array = {_prefetchable_array_T_1, _prefetchable_array_T_2}; // @[package.scala:45:27] wire [3:0] _misaligned_T = 4'h1 << io_req_bits_size_0; // @[OneHot.scala:58:35] wire [4:0] _misaligned_T_1 = {1'h0, _misaligned_T} - 5'h1; // @[OneHot.scala:58:35] wire [3:0] _misaligned_T_2 = _misaligned_T_1[3:0]; // @[TLB.scala:550:69] wire [39:0] _misaligned_T_3 = {36'h0, io_req_bits_vaddr_0[3:0] & _misaligned_T_2}; // @[TLB.scala:318:7, :550:{39,69}] wire misaligned = \|_misaligned_T_3; // @[TLB.scala:550:{39,77}] wire _bad_va_T = vm_enabled & stage1_en; // @[TLB.scala:374:29, :399:61, :568:21] wire [39:0] bad_va_maskedVAddr = io_req_bits_vaddr_0 & 40'hC000000000; // @[TLB.scala:318:7, :559:43] wire _bad_va_T_2 = bad_va_maskedVAddr == 40'h0; // @[TLB.scala:550:77, :559:43, :560:51] wire _bad_va_T_3 = bad_va_maskedVAddr == 40'hC000000000; // @[TLB.scala:559:43, :560:86] wire _bad_va_T_4 = _bad_va_T_3; // @[TLB.scala:560:{71,86}] wire _bad_va_T_5 = _bad_va_T_2 \| _bad_va_T_4; // @[TLB.scala:560:{51,59,71}] wire _bad_va_T_6 = ~_bad_va_T_5; // @[TLB.scala:560:{37,59}] wire _bad_va_T_7 = _bad_va_T_6; // @[TLB.scala:560:{34,37}] wire bad_va = _bad_va_T & _bad_va_T_7; // @[TLB.scala:560:34, :568:{21,34}] wire _GEN_42 = io_req_bits_cmd_0 == 5'h6; // @[package.scala:16:47] wire _cmd_lrsc_T; // @[package.scala:16:47] assign _cmd_lrsc_T = _GEN_42; // @[package.scala:16:47] wire _cmd_read_T_2; // @[package.scala:16:47] assign _cmd_read_T_2 = _GEN_42; // @[package.scala:16:47] wire _GEN_43 = io_req_bits_cmd_0 == 5'h7; // @[package.scala:16:47] wire _cmd_lrsc_T_1; // @[package.scala:16:47] assign _cmd_lrsc_T_1 = _GEN_43; // @[package.scala:16:47] wire _cmd_read_T_3; // @[package.scala:16:47] assign _cmd_read_T_3 = _GEN_43; // @[package.scala:16:47] wire _cmd_write_T_3; // @[Consts.scala:90:66] assign _cmd_write_T_3 = _GEN_43; // @[package.scala:16:47] wire _cmd_lrsc_T_2 = _cmd_lrsc_T \| _cmd_lrsc_T_1; // @[package.scala:16:47, :81:59] wire cmd_lrsc = _cmd_lrsc_T_2; // @[package.scala:81:59] wire _GEN_44 = io_req_bits_cmd_0 == 5'h4; // @[package.scala:16:47] wire _cmd_amo_logical_T; // @[package.scala:16:47] assign _cmd_amo_logical_T = _GEN_44; // @[package.scala:16:47] wire _cmd_read_T_7; // @[package.scala:16:47] assign _cmd_read_T_7 = _GEN_44; // @[package.scala:16:47] wire _cmd_write_T_5; // @[package.scala:16:47] assign _cmd_write_T_5 = _GEN_44; // @[package.scala:16:47] wire _GEN_45 = io_req_bits_cmd_0 == 5'h9; // @[package.scala:16:47] wire _cmd_amo_logical_T_1; // @[package.scala:16:47] assign _cmd_amo_logical_T_1 = _GEN_45; // @[package.scala:16:47] wire _cmd_read_T_8; // @[package.scala:16:47] assign _cmd_read_T_8 = _GEN_45; // @[package.scala:16:47] wire _cmd_write_T_6; // @[package.scala:16:47] assign _cmd_write_T_6 = _GEN_45; // @[package.scala:16:47] wire _GEN_46 = io_req_bits_cmd_0 == 5'hA; // @[package.scala:16:47] wire _cmd_amo_logical_T_2; // @[package.scala:16:47] assign _cmd_amo_logical_T_2 = _GEN_46; // @[package.scala:16:47] wire _cmd_read_T_9; // @[package.scala:16:47] assign _cmd_read_T_9 = _GEN_46; // @[package.scala:16:47] wire _cmd_write_T_7; // @[package.scala:16:47] assign _cmd_write_T_7 = _GEN_46; // @[package.scala:16:47] wire _GEN_47 = io_req_bits_cmd_0 == 5'hB; // @[package.scala:16:47] wire _cmd_amo_logical_T_3; // @[package.scala:16:47] assign _cmd_amo_logical_T_3 = _GEN_47; // @[package.scala:16:47] wire _cmd_read_T_10; // @[package.scala:16:47] assign _cmd_read_T_10 = _GEN_47; // @[package.scala:16:47] wire _cmd_write_T_8; // @[package.scala:16:47] assign _cmd_write_T_8 = _GEN_47; // @[package.scala:16:47] wire _cmd_amo_logical_T_4 = _cmd_amo_logical_T \| _cmd_amo_logical_T_1; // @[package.scala:16:47, :81:59] wire _cmd_amo_logical_T_5 = _cmd_amo_logical_T_4 \| _cmd_amo_logical_T_2; // @[package.scala:16:47, :81:59] wire _cmd_amo_logical_T_6 = _cmd_amo_logical_T_5 \| _cmd_amo_logical_T_3; // @[package.scala:16:47, :81:59] wire cmd_amo_logical = _cmd_amo_logical_T_6; // @[package.scala:81:59] wire _GEN_48 = io_req_bits_cmd_0 == 5'h8; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T = _GEN_48; // @[package.scala:16:47] wire _cmd_read_T_14; // @[package.scala:16:47] assign _cmd_read_T_14 = _GEN_48; // @[package.scala:16:47] wire _cmd_write_T_12; // @[package.scala:16:47] assign _cmd_write_T_12 = _GEN_48; // @[package.scala:16:47] wire _GEN_49 = io_req_bits_cmd_0 == 5'hC; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_1; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T_1 = _GEN_49; // @[package.scala:16:47] wire _cmd_read_T_15; // @[package.scala:16:47] assign _cmd_read_T_15 = _GEN_49; // @[package.scala:16:47] wire _cmd_write_T_13; // @[package.scala:16:47] assign _cmd_write_T_13 = _GEN_49; // @[package.scala:16:47] wire _GEN_50 = io_req_bits_cmd_0 == 5'hD; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_2; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T_2 = _GEN_50; // @[package.scala:16:47] wire _cmd_read_T_16; // @[package.scala:16:47] assign _cmd_read_T_16 = _GEN_50; // @[package.scala:16:47] wire _cmd_write_T_14; // @[package.scala:16:47] assign _cmd_write_T_14 = _GEN_50; // @[package.scala:16:47] wire _GEN_51 = io_req_bits_cmd_0 == 5'hE; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_3; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T_3 = _GEN_51; // @[package.scala:16:47] wire _cmd_read_T_17; // @[package.scala:16:47] assign _cmd_read_T_17 = _GEN_51; // @[package.scala:16:47] wire _cmd_write_T_15; // @[package.scala:16:47] assign _cmd_write_T_15 = _GEN_51; // @[package.scala:16:47] wire _GEN_52 = io_req_bits_cmd_0 == 5'hF; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_4; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T_4 = _GEN_52; // @[package.scala:16:47] wire _cmd_read_T_18; // @[package.scala:16:47] assign _cmd_read_T_18 = _GEN_52; // @[package.scala:16:47] wire _cmd_write_T_16; // @[package.scala:16:47] assign _cmd_write_T_16 = _GEN_52; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_5 = _cmd_amo_arithmetic_T \| _cmd_amo_arithmetic_T_1; // @[package.scala:16:47, :81:59] wire _cmd_amo_arithmetic_T_6 = _cmd_amo_arithmetic_T_5 \| _cmd_amo_arithmetic_T_2; // @[package.scala:16:47, :81:59] wire _cmd_amo_arithmetic_T_7 = _cmd_amo_arithmetic_T_6 \| _cmd_amo_arithmetic_T_3; // @[package.scala:16:47, :81:59] wire _cmd_amo_arithmetic_T_8 = _cmd_amo_arithmetic_T_7 \| _cmd_amo_arithmetic_T_4; // @[package.scala:16:47, :81:59] wire cmd_amo_arithmetic = _cmd_amo_arithmetic_T_8; // @[package.scala:81:59] wire _GEN_53 = io_req_bits_cmd_0 == 5'h11; // @[TLB.scala:318:7, :573:41] wire cmd_put_partial; // @[TLB.scala:573:41] assign cmd_put_partial = _GEN_53; // @[TLB.scala:573:41] wire _cmd_write_T_1; // @[Consts.scala:90:49] assign _cmd_write_T_1 = _GEN_53; // @[TLB.scala:573:41] wire _cmd_read_T = io_req_bits_cmd_0 == 5'h0; // @[package.scala:16:47] wire _GEN_54 = io_req_bits_cmd_0 == 5'h10; // @[package.scala:16:47] wire _cmd_read_T_1; // @[package.scala:16:47] assign _cmd_read_T_1 = _GEN_54; // @[package.scala:16:47] wire _cmd_readx_T; // @[TLB.scala:575:56] assign _cmd_readx_T = _GEN_54; // @[package.scala:16:47] wire _cmd_read_T_4 = _cmd_read_T \| _cmd_read_T_1; // @[package.scala:16:47, :81:59] wire _cmd_read_T_5 = _cmd_read_T_4 \| _cmd_read_T_2; // @[package.scala:16:47, :81:59] wire _cmd_read_T_6 = _cmd_read_T_5 \| _cmd_read_T_3; // @[package.scala:16:47, :81:59] wire _cmd_read_T_11 = _cmd_read_T_7 \| _cmd_read_T_8; // @[package.scala:16:47, :81:59] wire _cmd_read_T_12 = _cmd_read_T_11 \| _cmd_read_T_9; // @[package.scala:16:47, :81:59] wire _cmd_read_T_13 = _cmd_read_T_12 \| _cmd_read_T_10; // @[package.scala:16:47, :81:59] wire _cmd_read_T_19 = _cmd_read_T_14 \| _cmd_read_T_15; // @[package.scala:16:47, :81:59] wire _cmd_read_T_20 = _cmd_read_T_19 \| _cmd_read_T_16; // @[package.scala:16:47, :81:59] wire _cmd_read_T_21 = _cmd_read_T_20 \| _cmd_read_T_17; // @[package.scala:16:47, :81:59] wire _cmd_read_T_22 = _cmd_read_T_21 \| _cmd_read_T_18; // @[package.scala:16:47, :81:59] wire _cmd_read_T_23 = _cmd_read_T_13 \| _cmd_read_T_22; // @[package.scala:81:59] wire cmd_read = _cmd_read_T_6 \| _cmd_read_T_23; // @[package.scala:81:59] wire _cmd_write_T = io_req_bits_cmd_0 == 5'h1; // @[TLB.scala:318:7] wire _cmd_write_T_2 = _cmd_write_T \| _cmd_write_T_1; // @[Consts.scala:90:{32,42,49}] wire _cmd_write_T_4 = _cmd_write_T_2 \| _cmd_write_T_3; // @[Consts.scala:90:{42,59,66}] wire _cmd_write_T_9 = _cmd_write_T_5 \| _cmd_write_T_6; // @[package.scala:16:47, :81:59] wire _cmd_write_T_10 = _cmd_write_T_9 \| _cmd_write_T_7; // @[package.scala:16:47, :81:59] wire _cmd_write_T_11 = _cmd_write_T_10 \| _cmd_write_T_8; // @[package.scala:16:47, :81:59] wire _cmd_write_T_17 = _cmd_write_T_12 \| _cmd_write_T_13; // @[package.scala:16:47, :81:59] wire _cmd_write_T_18 = _cmd_write_T_17 \| _cmd_write_T_14; // @[package.scala:16:47, :81:59] wire _cmd_write_T_19 = _cmd_write_T_18 \| _cmd_write_T_15; // @[package.scala:16:47, :81:59] wire _cmd_write_T_20 = _cmd_write_T_19 \| _cmd_write_T_16; // @[package.scala:16:47, :81:59] wire _cmd_write_T_21 = _cmd_write_T_11 \| _cmd_write_T_20; // @[package.scala:81:59] wire cmd_write = _cmd_write_T_4 \| _cmd_write_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _cmd_write_perms_T = io_req_bits_cmd_0 == 5'h5; // @[package.scala:16:47] wire _cmd_write_perms_T_1 = io_req_bits_cmd_0 == 5'h17; // @[package.scala:16:47] wire _cmd_write_perms_T_2 = _cmd_write_perms_T \| _cmd_write_perms_T_1; // @[package.scala:16:47, :81:59] wire cmd_write_perms = cmd_write \| _cmd_write_perms_T_2; // @[package.scala:81:59] wire [6:0] _ae_array_T = misaligned ? eff_array : 7'h0; // @[TLB.scala:535:22, :550:77, :582:8] wire [6:0] _ae_array_T_1 = ~lrscAllowed; // @[TLB.scala:580:24, :583:19] wire [6:0] _ae_array_T_2 = cmd_lrsc ? _ae_array_T_1 : 7'h0; // @[TLB.scala:570:33, :583:{8,19}] wire [6:0] ae_array = _ae_array_T \| _ae_array_T_2; // @[TLB.scala:582:{8,37}, :583:8] wire [6:0] _ae_ld_array_T = ~pr_array; // @[TLB.scala:529:87, :586:46] wire [6:0] _ae_ld_array_T_1 = ae_array \| _ae_ld_array_T; // @[TLB.scala:582:37, :586:{44,46}] wire [6:0] ae_ld_array = cmd_read ? _ae_ld_array_T_1 : 7'h0; // @[TLB.scala:586:{24,44}] wire [6:0] _ae_st_array_T = ~pw_array; // @[TLB.scala:531:87, :588:37] wire [6:0] _ae_st_array_T_1 = ae_array \| _ae_st_array_T; // @[TLB.scala:582:37, :588:{35,37}] wire [6:0] _ae_st_array_T_2 = cmd_write_perms ? _ae_st_array_T_1 : 7'h0; // @[TLB.scala:577:35, :588:{8,35}] wire [6:0] _ae_st_array_T_3 = ~ppp_array_if_cached; // @[TLB.scala:544:39, :589:26] wire [6:0] _ae_st_array_T_4 = cmd_put_partial ? _ae_st_array_T_3 : 7'h0; // @[TLB.scala:573:41, :589:{8,26}] wire [6:0] _ae_st_array_T_5 = _ae_st_array_T_2 \| _ae_st_array_T_4; // @[TLB.scala:588:{8,53}, :589:8] wire [6:0] _ae_st_array_T_6 = ~pal_array_if_cached; // @[TLB.scala:546:39, :590:26] wire [6:0] _ae_st_array_T_7 = cmd_amo_logical ? _ae_st_array_T_6 : 7'h0; // @[TLB.scala:571:40, :590:{8,26}] wire [6:0] _ae_st_array_T_8 = _ae_st_array_T_5 \| _ae_st_array_T_7; // @[TLB.scala:588:53, :589:53, :590:8] wire [6:0] _ae_st_array_T_9 = ~paa_array_if_cached; // @[TLB.scala:545:39, :591:29] wire [6:0] _ae_st_array_T_10 = cmd_amo_arithmetic ? _ae_st_array_T_9 : 7'h0; // @[TLB.scala:572:43, :591:{8,29}] wire [6:0] ae_st_array = _ae_st_array_T_8 \| _ae_st_array_T_10; // @[TLB.scala:589:53, :590:53, :591:8] wire [6:0] _must_alloc_array_T = ~ppp_array; // @[TLB.scala:539:22, :593:26] wire [6:0] _must_alloc_array_T_1 = cmd_put_partial ? _must_alloc_array_T : 7'h0; // @[TLB.scala:573:41, :593:{8,26}] wire [6:0] _must_alloc_array_T_2 = ~pal_array; // @[TLB.scala:543:22, :594:26] wire [6:0] _must_alloc_array_T_3 = cmd_amo_logical ? _must_alloc_array_T_2 : 7'h0; // @[TLB.scala:571:40, :594:{8,26}] wire [6:0] _must_alloc_array_T_4 = _must_alloc_array_T_1 \| _must_alloc_array_T_3; // @[TLB.scala:593:{8,43}, :594:8] wire [6:0] _must_alloc_array_T_5 = ~paa_array; // @[TLB.scala:541:22, :595:29] wire [6:0] _must_alloc_array_T_6 = cmd_amo_arithmetic ? _must_alloc_array_T_5 : 7'h0; // @[TLB.scala:572:43, :595:{8,29}] wire [6:0] _must_alloc_array_T_7 = _must_alloc_array_T_4 \| _must_alloc_array_T_6; // @[TLB.scala:593:43, :594:43, :595:8] wire [6:0] _must_alloc_array_T_9 = {7{cmd_lrsc}}; // @[TLB.scala:570:33, :596:8] wire [6:0] must_alloc_array = _must_alloc_array_T_7 \| _must_alloc_array_T_9; // @[TLB.scala:594:43, :595:46, :596:8] wire [6:0] _pf_ld_array_T_1 = ~_pf_ld_array_T; // @[TLB.scala:597:{37,41}] wire [6:0] _pf_ld_array_T_2 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73] wire [6:0] _pf_ld_array_T_3 = _pf_ld_array_T_1 & _pf_ld_array_T_2; // @[TLB.scala:597:{37,71,73}] wire [6:0] _pf_ld_array_T_4 = _pf_ld_array_T_3 \| ptw_pf_array; // @[TLB.scala:508:25, :597:{71,88}] wire [6:0] _pf_ld_array_T_5 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106] wire [6:0] _pf_ld_array_T_6 = _pf_ld_array_T_4 & _pf_ld_array_T_5; // @[TLB.scala:597:{88,104,106}] wire [6:0] pf_ld_array = cmd_read ? _pf_ld_array_T_6 : 7'h0; // @[TLB.scala:597:{24,104}] wire [6:0] _pf_st_array_T = ~w_array; // @[TLB.scala:521:20, :598:44] wire [6:0] _pf_st_array_T_1 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :598:55] wire [6:0] _pf_st_array_T_2 = _pf_st_array_T & _pf_st_array_T_1; // @[TLB.scala:598:{44,53,55}] wire [6:0] _pf_st_array_T_3 = _pf_st_array_T_2 \| ptw_pf_array; // @[TLB.scala:508:25, :598:{53,70}] wire [6:0] _pf_st_array_T_4 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106, :598:88] wire [6:0] _pf_st_array_T_5 = _pf_st_array_T_3 & _pf_st_array_T_4; // @[TLB.scala:598:{70,86,88}] wire [6:0] pf_st_array = cmd_write_perms ? _pf_st_array_T_5 : 7'h0; // @[TLB.scala:577:35, :598:{24,86}] wire [6:0] _pf_inst_array_T = ~x_array; // @[TLB.scala:522:20, :599:25] wire [6:0] _pf_inst_array_T_1 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :599:36] wire [6:0] _pf_inst_array_T_2 = _pf_inst_array_T & _pf_inst_array_T_1; // @[TLB.scala:599:{25,34,36}] wire [6:0] _pf_inst_array_T_3 = _pf_inst_array_T_2 \| ptw_pf_array; // @[TLB.scala:508:25, :599:{34,51}] wire [6:0] _pf_inst_array_T_4 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106, :599:69] wire [6:0] pf_inst_array = _pf_inst_array_T_3 & _pf_inst_array_T_4; // @[TLB.scala:599:{51,67,69}] wire [6:0] _gf_ld_array_T_4 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :600:100] wire [6:0] _gf_ld_array_T_5 = _gf_ld_array_T_3 & _gf_ld_array_T_4; // @[TLB.scala:600:{82,98,100}] wire [6:0] _gf_st_array_T_3 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :601:81] wire [6:0] _gf_st_array_T_4 = _gf_st_array_T_2 & _gf_st_array_T_3; // @[TLB.scala:601:{63,79,81}] wire [6:0] _gf_inst_array_T_2 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :602:64] wire [6:0] _gf_inst_array_T_3 = _gf_inst_array_T_1 & _gf_inst_array_T_2; // @[TLB.scala:602:{46,62,64}] wire _gpa_hits_hit_mask_T = r_gpa_vpn == vpn; // @[TLB.scala:335:30, :364:22, :606:73] wire _gpa_hits_hit_mask_T_1 = r_gpa_valid & _gpa_hits_hit_mask_T; // @[TLB.scala:362:24, :606:{60,73}] wire [4:0] _gpa_hits_hit_mask_T_2 = {5{_gpa_hits_hit_mask_T_1}}; // @[TLB.scala:606:{24,60}] wire tlb_hit_if_not_gpa_miss = \|real_hits; // @[package.scala:45:27] wire tlb_hit = \|_tlb_hit_T; // @[TLB.scala:611:{28,40}] wire _tlb_miss_T_2 = ~bad_va; // @[TLB.scala:568:34, :613:56] wire _tlb_miss_T_3 = _tlb_miss_T_1 & _tlb_miss_T_2; // @[TLB.scala:613:{29,53,56}] wire _tlb_miss_T_4 = ~tlb_hit; // @[TLB.scala:611:40, :613:67] wire tlb_miss = _tlb_miss_T_3 & _tlb_miss_T_4; // @[TLB.scala:613:{53,64,67}] reg [2:0] state_vec_0; // @[Replacement.scala:305:17] reg [2:0] state_vec_1; // @[Replacement.scala:305:17] reg [2:0] state_vec_2; // @[Replacement.scala:305:17] reg [2:0] state_vec_3; // @[Replacement.scala:305:17] wire [1:0] _GEN_55 = {sector_hits_1, sector_hits_0}; // @[OneHot.scala:21:45] wire [1:0] lo; // @[OneHot.scala:21:45] assign lo = _GEN_55; // @[OneHot.scala:21:45] wire [1:0] r_sectored_hit_bits_lo; // @[OneHot.scala:21:45] assign r_sectored_hit_bits_lo = _GEN_55; // @[OneHot.scala:21:45] wire [1:0] lo_1 = lo; // @[OneHot.scala:21:45, :31:18] wire [1:0] _GEN_56 = {sector_hits_3, sector_hits_2}; // @[OneHot.scala:21:45] wire [1:0] hi; // @[OneHot.scala:21:45] assign hi = _GEN_56; // @[OneHot.scala:21:45] wire [1:0] r_sectored_hit_bits_hi; // @[OneHot.scala:21:45] assign r_sectored_hit_bits_hi = _GEN_56; // @[OneHot.scala:21:45] wire [1:0] hi_1 = hi; // @[OneHot.scala:21:45, :30:18] wire [1:0] state_vec_touch_way_sized = {\|hi_1, hi_1[1] \| lo_1[1]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}] wire _state_vec_set_left_older_T = state_vec_touch_way_sized[1]; // @[package.scala:163:13] wire state_vec_set_left_older = ~_state_vec_set_left_older_T; // @[Replacement.scala:196:{33,43}] wire [3:0][2:0] _GEN_57 = {{state_vec_3}, {state_vec_2}, {state_vec_1}, {state_vec_0}}; // @[package.scala:163:13] wire state_vec_left_subtree_state = _GEN_57[memIdx][1]; // @[package.scala:163:13] wire r_sectored_repl_addr_left_subtree_state = _GEN_57[memIdx][1]; // @[package.scala:163:13] wire state_vec_right_subtree_state = _GEN_57[memIdx][0]; // @[package.scala:163:13] wire r_sectored_repl_addr_right_subtree_state = _GEN_57[memIdx][0]; // @[package.scala:163:13] wire _state_vec_T = state_vec_touch_way_sized[0]; // @[package.scala:163:13] wire _state_vec_T_4 = state_vec_touch_way_sized[0]; // @[package.scala:163:13] wire _state_vec_T_1 = _state_vec_T; // @[package.scala:163:13] wire _state_vec_T_2 = ~_state_vec_T_1; // @[Replacement.scala:218:{7,17}] wire _state_vec_T_3 = state_vec_set_left_older ? state_vec_left_subtree_state : _state_vec_T_2; // @[package.scala:163:13] wire _state_vec_T_5 = _state_vec_T_4; // @[Replacement.scala:207:62, :218:17] wire _state_vec_T_6 = ~_state_vec_T_5; // @[Replacement.scala:218:{7,17}] wire _state_vec_T_7 = state_vec_set_left_older ? _state_vec_T_6 : state_vec_right_subtree_state; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_vec_hi = {state_vec_set_left_older, _state_vec_T_3}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_vec_T_8 = {state_vec_hi, _state_vec_T_7}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _multipleHits_T = real_hits[2:0]; // @[package.scala:45:27] wire _multipleHits_T_1 = _multipleHits_T[0]; // @[Misc.scala:181:37] wire multipleHits_leftOne = _multipleHits_T_1; // @[Misc.scala:178:18, :181:37] wire [1:0] _multipleHits_T_2 = _multipleHits_T[2:1]; // @[Misc.scala:181:37, :182:39] wire _multipleHits_T_3 = _multipleHits_T_2[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_1 = _multipleHits_T_3; // @[Misc.scala:178:18, :181:37] wire _multipleHits_T_4 = _multipleHits_T_2[1]; // @[Misc.scala:182:39] wire multipleHits_rightOne = _multipleHits_T_4; // @[Misc.scala:178:18, :182:39] wire multipleHits_rightOne_1 = multipleHits_leftOne_1 \| multipleHits_rightOne; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_6 = multipleHits_leftOne_1 & multipleHits_rightOne; // @[Misc.scala:178:18, :183:61] wire multipleHits_rightTwo = _multipleHits_T_6; // @[Misc.scala:183:{49,61}] wire _multipleHits_T_7 = multipleHits_rightTwo; // @[Misc.scala:183:{37,49}] wire multipleHits_leftOne_2 = multipleHits_leftOne \| multipleHits_rightOne_1; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_8 = multipleHits_leftOne & multipleHits_rightOne_1; // @[Misc.scala:178:18, :183:{16,61}] wire multipleHits_leftTwo = _multipleHits_T_7 \| _multipleHits_T_8; // @[Misc.scala:183:{37,49,61}] wire [2:0] _multipleHits_T_9 = real_hits[5:3]; // @[package.scala:45:27] wire _multipleHits_T_10 = _multipleHits_T_9[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_3 = _multipleHits_T_10; // @[Misc.scala:178:18, :181:37] wire [1:0] _multipleHits_T_11 = _multipleHits_T_9[2:1]; // @[Misc.scala:182:39] wire _multipleHits_T_12 = _multipleHits_T_11[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_4 = _multipleHits_T_12; // @[Misc.scala:178:18, :181:37] wire _multipleHits_T_13 = _multipleHits_T_11[1]; // @[Misc.scala:182:39] wire multipleHits_rightOne_2 = _multipleHits_T_13; // @[Misc.scala:178:18, :182:39] wire multipleHits_rightOne_3 = multipleHits_leftOne_4 \| multipleHits_rightOne_2; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_15 = multipleHits_leftOne_4 & multipleHits_rightOne_2; // @[Misc.scala:178:18, :183:61] wire multipleHits_rightTwo_1 = _multipleHits_T_15; // @[Misc.scala:183:{49,61}] wire _multipleHits_T_16 = multipleHits_rightTwo_1; // @[Misc.scala:183:{37,49}] wire multipleHits_rightOne_4 = multipleHits_leftOne_3 \| multipleHits_rightOne_3; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_17 = multipleHits_leftOne_3 & multipleHits_rightOne_3; // @[Misc.scala:178:18, :183:{16,61}] wire multipleHits_rightTwo_2 = _multipleHits_T_16 \| _multipleHits_T_17; // @[Misc.scala:183:{37,49,61}] wire _multipleHits_T_18 = multipleHits_leftOne_2 \| multipleHits_rightOne_4; // @[Misc.scala:183:16] wire _multipleHits_T_19 = multipleHits_leftTwo \| multipleHits_rightTwo_2; // @[Misc.scala:183:{37,49}] wire _multipleHits_T_20 = multipleHits_leftOne_2 & multipleHits_rightOne_4; // @[Misc.scala:183:{16,61}] wire multipleHits = _multipleHits_T_19 \| _multipleHits_T_20; // @[Misc.scala:183:{37,49,61}] assign _io_req_ready_T = state == 2'h0; // @[TLB.scala:352:22, :631:25] assign io_req_ready_0 = _io_req_ready_T; // @[TLB.scala:318:7, :631:25] wire _io_resp_pf_ld_T = bad_va & cmd_read; // @[TLB.scala:568:34, :633:28] wire [6:0] _io_resp_pf_ld_T_1 = pf_ld_array & hits; // @[TLB.scala:442:17, :597:24, :633:57] wire _io_resp_pf_ld_T_2 = \|_io_resp_pf_ld_T_1; // @[TLB.scala:633:{57,65}] assign _io_resp_pf_ld_T_3 = _io_resp_pf_ld_T \| _io_resp_pf_ld_T_2; // @[TLB.scala:633:{28,41,65}] assign io_resp_pf_ld = _io_resp_pf_ld_T_3; // @[TLB.scala:318:7, :633:41] wire _io_resp_pf_st_T = bad_va & cmd_write_perms; // @[TLB.scala:568:34, :577:35, :634:28] wire [6:0] _io_resp_pf_st_T_1 = pf_st_array & hits; // @[TLB.scala:442:17, :598:24, :634:64] wire _io_resp_pf_st_T_2 = \|_io_resp_pf_st_T_1; // @[TLB.scala:634:{64,72}] assign _io_resp_pf_st_T_3 = _io_resp_pf_st_T \| _io_resp_pf_st_T_2; // @[TLB.scala:634:{28,48,72}] assign io_resp_pf_st = _io_resp_pf_st_T_3; // @[TLB.scala:318:7, :634:48] wire [6:0] _io_resp_pf_inst_T = pf_inst_array & hits; // @[TLB.scala:442:17, :599:67, :635:47] wire _io_resp_pf_inst_T_1 = \|_io_resp_pf_inst_T; // @[TLB.scala:635:{47,55}] assign _io_resp_pf_inst_T_2 = bad_va \| _io_resp_pf_inst_T_1; // @[TLB.scala:568:34, :635:{29,55}] assign io_resp_pf_inst = _io_resp_pf_inst_T_2; // @[TLB.scala:318:7, :635:29] wire [6:0] _io_resp_ae_ld_T = ae_ld_array & hits; // @[TLB.scala:442:17, :586:24, :641:33] assign _io_resp_ae_ld_T_1 = \|_io_resp_ae_ld_T; // @[TLB.scala:641:{33,41}] assign io_resp_ae_ld = _io_resp_ae_ld_T_1; // @[TLB.scala:318:7, :641:41] wire [6:0] _io_resp_ae_st_T = ae_st_array & hits; // @[TLB.scala:442:17, :590:53, :642:33] assign _io_resp_ae_st_T_1 = \|_io_resp_ae_st_T; // @[TLB.scala:642:{33,41}] assign io_resp_ae_st = _io_resp_ae_st_T_1; // @[TLB.scala:318:7, :642:41] wire [6:0] _io_resp_ae_inst_T = ~px_array; // @[TLB.scala:533:87, :643:23] wire [6:0] _io_resp_ae_inst_T_1 = _io_resp_ae_inst_T & hits; // @[TLB.scala:442:17, :643:{23,33}] assign _io_resp_ae_inst_T_2 = \|_io_resp_ae_inst_T_1; // @[TLB.scala:643:{33,41}] assign io_resp_ae_inst = _io_resp_ae_inst_T_2; // @[TLB.scala:318:7, :643:41] assign _io_resp_ma_ld_T = misaligned & cmd_read; // @[TLB.scala:550:77, :645:31] assign io_resp_ma_ld = _io_resp_ma_ld_T; // @[TLB.scala:318:7, :645:31] assign _io_resp_ma_st_T = misaligned & cmd_write; // @[TLB.scala:550:77, :646:31] assign io_resp_ma_st = _io_resp_ma_st_T; // @[TLB.scala:318:7, :646:31] wire [6:0] _io_resp_cacheable_T = c_array & hits; // @[TLB.scala:442:17, :537:20, :648:33] assign _io_resp_cacheable_T_1 = \|_io_resp_cacheable_T; // @[TLB.scala:648:{33,41}] assign io_resp_cacheable = _io_resp_cacheable_T_1; // @[TLB.scala:318:7, :648:41] wire [6:0] _io_resp_must_alloc_T = must_alloc_array & hits; // @[TLB.scala:442:17, :595:46, :649:43] assign _io_resp_must_alloc_T_1 = \|_io_resp_must_alloc_T; // @[TLB.scala:649:{43,51}] assign io_resp_must_alloc = _io_resp_must_alloc_T_1; // @[TLB.scala:318:7, :649:51] wire [6:0] _io_resp_prefetchable_T = prefetchable_array & hits; // @[TLB.scala:442:17, :547:31, :650:47] wire _io_resp_prefetchable_T_1 = \|_io_resp_prefetchable_T; // @[TLB.scala:650:{47,55}] assign _io_resp_prefetchable_T_2 = _io_resp_prefetchable_T_1; // @[TLB.scala:650:{55,59}] assign io_resp_prefetchable = _io_resp_prefetchable_T_2; // @[TLB.scala:318:7, :650:59] wire _io_resp_miss_T_1 = _io_resp_miss_T \| tlb_miss; // @[TLB.scala:613:64, :651:{29,52}] assign _io_resp_miss_T_2 = _io_resp_miss_T_1 \| multipleHits; // @[Misc.scala:183:49] assign io_resp_miss_0 = _io_resp_miss_T_2; // @[TLB.scala:318:7, :651:64] assign _io_resp_paddr_T_1 = {ppn, _io_resp_paddr_T}; // @[Mux.scala:30:73] assign io_resp_paddr_0 = _io_resp_paddr_T_1; // @[TLB.scala:318:7, :652:23] wire [27:0] _io_resp_gpa_page_T_1 = {1'h0, vpn}; // @[TLB.scala:335:30, :657:36] wire [27:0] io_resp_gpa_page = _io_resp_gpa_page_T_1; // @[TLB.scala:657:{19,36}] wire [26:0] _io_resp_gpa_page_T_2 = r_gpa[38:12]; // @[TLB.scala:363:18, :657:58] wire [11:0] _io_resp_gpa_offset_T = r_gpa[11:0]; // @[TLB.scala:363:18, :658:47] wire [11:0] io_resp_gpa_offset = _io_resp_gpa_offset_T_1; // @[TLB.scala:658:{21,82}] assign _io_resp_gpa_T = {io_resp_gpa_page, io_resp_gpa_offset}; // @[TLB.scala:657:19, :658:21, :659:8] assign io_resp_gpa = _io_resp_gpa_T; // @[TLB.scala:318:7, :659:8] assign io_ptw_req_valid_0 = _io_ptw_req_valid_T; // @[TLB.scala:318:7, :662:29] wire _r_superpage_repl_addr_T_1 = ~superpage_entries_0_valid_0; // @[TLB.scala:341:30, :757:43] wire _r_superpage_repl_addr_T_2 = _r_superpage_repl_addr_T_1; // @[OneHot.scala:48:45] wire r_sectored_repl_addr_left_subtree_older = _GEN_57[memIdx][2]; // @[package.scala:163:13] wire _r_sectored_repl_addr_T = r_sectored_repl_addr_left_subtree_state; // @[package.scala:163:13] wire _r_sectored_repl_addr_T_1 = r_sectored_repl_addr_right_subtree_state; // @[Replacement.scala:245:38, :262:12] wire _r_sectored_repl_addr_T_2 = r_sectored_repl_addr_left_subtree_older ? _r_sectored_repl_addr_T : _r_sectored_repl_addr_T_1; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _r_sectored_repl_addr_T_3 = {r_sectored_repl_addr_left_subtree_older, _r_sectored_repl_addr_T_2}; // @[Replacement.scala:243:38, :249:12, :250:16] wire [1:0] r_sectored_repl_addr_valids_lo = {_GEN_11[memIdx], _GEN_7[memIdx]}; // @[package.scala:45:27, :163:13] wire [1:0] r_sectored_repl_addr_valids_hi = {_GEN_19[memIdx], _GEN_15[memIdx]}; // @[package.scala:45:27, :163:13] wire [3:0] r_sectored_repl_addr_valids = {r_sectored_repl_addr_valids_hi, r_sectored_repl_addr_valids_lo}; // @[package.scala:45:27] wire _r_sectored_repl_addr_T_4 = &r_sectored_repl_addr_valids; // @[package.scala:45:27] wire [3:0] _r_sectored_repl_addr_T_5 = ~r_sectored_repl_addr_valids; // @[package.scala:45:27] wire _r_sectored_repl_addr_T_6 = _r_sectored_repl_addr_T_5[0]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_7 = _r_sectored_repl_addr_T_5[1]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_8 = _r_sectored_repl_addr_T_5[2]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_9 = _r_sectored_repl_addr_T_5[3]; // @[OneHot.scala:48:45] wire [1:0] _r_sectored_repl_addr_T_10 = {1'h1, ~_r_sectored_repl_addr_T_8}; // @[OneHot.scala:48:45] wire [1:0] _r_sectored_repl_addr_T_11 = _r_sectored_repl_addr_T_7 ? 2'h1 : _r_sectored_repl_addr_T_10; // @[OneHot.scala:48:45] wire [1:0] _r_sectored_repl_addr_T_12 = _r_sectored_repl_addr_T_6 ? 2'h0 : _r_sectored_repl_addr_T_11; // @[OneHot.scala:48:45] wire [1:0] _r_sectored_repl_addr_T_13 = _r_sectored_repl_addr_T_4 ? _r_sectored_repl_addr_T_3 : _r_sectored_repl_addr_T_12; // @[Mux.scala:50:70] wire _r_sectored_hit_valid_T = sector_hits_0 \| sector_hits_1; // @[package.scala:81:59] wire _r_sectored_hit_valid_T_1 = _r_sectored_hit_valid_T \| sector_hits_2; // @[package.scala:81:59] wire _r_sectored_hit_valid_T_2 = _r_sectored_hit_valid_T_1 \| sector_hits_3; // @[package.scala:81:59] wire [3:0] _r_sectored_hit_bits_T = {r_sectored_hit_bits_hi, r_sectored_hit_bits_lo}; // @[OneHot.scala:21:45] wire [1:0] r_sectored_hit_bits_hi_1 = _r_sectored_hit_bits_T[3:2]; // @[OneHot.scala:21:45, :30:18] wire [1:0] r_sectored_hit_bits_lo_1 = _r_sectored_hit_bits_T[1:0]; // @[OneHot.scala:21:45, :31:18] wire _r_sectored_hit_bits_T_1 = \|r_sectored_hit_bits_hi_1; // @[OneHot.scala:30:18, :32:14] wire [1:0] _r_sectored_hit_bits_T_2 = r_sectored_hit_bits_hi_1 \| r_sectored_hit_bits_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire _r_sectored_hit_bits_T_3 = _r_sectored_hit_bits_T_2[1]; // @[OneHot.scala:32:28] wire [1:0] _r_sectored_hit_bits_T_4 = {_r_sectored_hit_bits_T_1, _r_sectored_hit_bits_T_3}; // @[OneHot.scala:32:{10,14}] wire [1:0] _state_T = {1'h1, io_sfence_valid_0}; // @[TLB.scala:318:7, :704:45] wire _tagMatch_T = ~superpage_entries_0_tag_v; // @[TLB.scala:178:43, :341:30] wire tagMatch = superpage_entries_0_valid_0 & _tagMatch_T; // @[TLB.scala:178:{33,43}, :341:30] wire ignore_1 = _ignore_T_1; // @[TLB.scala:182:{28,34}] wire _ignore_T_2 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :341:30] wire _tagMatch_T_1 = ~special_entry_tag_v; // @[TLB.scala:178:43, :346:56] wire tagMatch_1 = special_entry_valid_0 & _tagMatch_T_1; // @[TLB.scala:178:{33,43}, :346:56] wire ignore_4 = _ignore_T_4; // @[TLB.scala:182:{28,34}] wire _ignore_T_5 = ~(special_entry_level[1]); // @[TLB.scala:182:28, :197:28, :346:56] wire ignore_5 = _ignore_T_5; // @[TLB.scala:182:{28,34}] wire _T_12 = io_req_valid_0 & vm_enabled; // @[TLB.scala:318:7, :399:61, :617:22] wire _T_15 = sector_hits_0 \| sector_hits_1 \| sector_hits_2 \| sector_hits_3; // @[package.scala:81:59] wire _GEN_58 = do_refill & ~io_ptw_resp_bits_homogeneous_0; // @[TLB.scala:211:18, :318:7, :346:56, :408:29, :446:20, :474:{39,70}] wire _GEN_59 = ~do_refill \| ~io_ptw_resp_bits_homogeneous_0 \| io_ptw_resp_bits_level_0[1]; // @[TLB.scala:318:7, :341:30, :408:29, :446:20, :474:70, :476:{40,58}] wire _T_4 = waddr_1 == 2'h0; // @[TLB.scala:485:22, :486:75] wire _GEN_60 = r_memIdx == 2'h0; // @[package.scala:163:13] wire _GEN_61 = r_memIdx == 2'h1; // @[package.scala:163:13] wire _GEN_62 = r_memIdx == 2'h2; // @[package.scala:163:13] wire _GEN_63 = ~io_ptw_resp_bits_homogeneous_0 \| ~(io_ptw_resp_bits_level_0[1]); // @[TLB.scala:318:7, :339:29, :474:{39,70}, :476:{40,58}, :486:84] wire _GEN_64 = ~do_refill \| _GEN_63 \| ~(_T_4 & _GEN_60); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_65 = ~do_refill \| _GEN_63 \| ~(_T_4 & _GEN_61); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_66 = ~do_refill \| _GEN_63 \| ~(_T_4 & _GEN_62); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_67 = ~do_refill \| _GEN_63 \| ~(_T_4 & (&r_memIdx)); // @[package.scala:163:13] wire _GEN_68 = invalidate_refill & _GEN_60; // @[TLB.scala:216:16, :220:46, :410:88, :489:34] wire _GEN_69 = ~do_refill \| _GEN_63 \| ~_T_4; // @[TLB.scala:339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_70 = invalidate_refill & _GEN_61; // @[TLB.scala:216:16, :220:46, :410:88, :489:34] wire _GEN_71 = invalidate_refill & _GEN_62; // @[TLB.scala:216:16, :220:46, :410:88, :489:34] wire _GEN_72 = invalidate_refill & (&r_memIdx); // @[package.scala:163:13] wire _T_6 = waddr_1 == 2'h1; // @[TLB.scala:197:28, :485:22, :486:75] wire _GEN_73 = ~do_refill \| _GEN_63 \| ~(_T_6 & _GEN_60); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_74 = ~do_refill \| _GEN_63 \| ~(_T_6 & _GEN_61); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_75 = ~do_refill \| _GEN_63 \| ~(_T_6 & _GEN_62); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_76 = ~do_refill \| _GEN_63 \| ~(_T_6 & (&r_memIdx)); // @[package.scala:163:13] wire _GEN_77 = ~do_refill \| _GEN_63 \| ~_T_6; // @[TLB.scala:339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _T_8 = waddr_1 == 2'h2; // @[TLB.scala:485:22, :486:75] wire _GEN_78 = ~do_refill \| _GEN_63 \| ~(_T_8 & _GEN_60); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_79 = ~do_refill \| _GEN_63 \| ~(_T_8 & _GEN_61); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_80 = ~do_refill \| _GEN_63 \| ~(_T_8 & _GEN_62); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_81 = ~do_refill \| _GEN_63 \| ~(_T_8 & (&r_memIdx)); // @[package.scala:163:13] wire _GEN_82 = ~do_refill \| _GEN_63 \| ~_T_8; // @[TLB.scala:339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_83 = ~do_refill \| _GEN_63 \| ~((&waddr_1) & _GEN_60); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :485:22, :486:{75,84}] wire _GEN_84 = ~do_refill \| _GEN_63 \| ~((&waddr_1) & _GEN_61); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :485:22, :486:{75,84}] wire _GEN_85 = ~do_refill \| _GEN_63 \| ~((&waddr_1) & _GEN_62); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :485:22, :486:{75,84}] wire _GEN_86 = ~do_refill \| _GEN_63 \| ~((&waddr_1) & (&r_memIdx)); // @[package.scala:163:13] wire _GEN_87 = ~do_refill \| _GEN_63 \| ~(&waddr_1); // @[TLB.scala:339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :485:22, :486:{75,84}] wire _T_2491 = io_ptw_req_ready_0 & io_ptw_req_valid_0; // @[Decoupled.scala:51:35] wire _T_24 = io_req_ready_0 & io_req_valid_0 & tlb_miss; // @[Decoupled.scala:51:35] wire _T_2490 = multipleHits \| reset; // @[Misc.scala:183:49] always @(posedge clock) begin // @[TLB.scala:318:7] if (_GEN_64) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_0_0_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_0_0_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_0_0_tag_v <= _GEN_64 & sectored_entries_0_0_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_64) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_0_0_data_0 <= _sectored_entries_0_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_0_0_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_0_0_tag_v) & (_GEN_69 ? sectored_entries_0_0_valid_0 : ~_GEN_68 & (_GEN_60 \| ~(~r_sectored_hit_valid & _GEN_60) & sectored_entries_0_0_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_73) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_0_1_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_0_1_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_0_1_tag_v <= _GEN_73 & sectored_entries_0_1_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_73) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_0_1_data_0 <= _sectored_entries_1_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_0_1_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_0_1_tag_v) & (_GEN_77 ? sectored_entries_0_1_valid_0 : ~_GEN_68 & (_GEN_60 \| ~(~r_sectored_hit_valid & _GEN_60) & sectored_entries_0_1_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_78) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_0_2_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_0_2_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_0_2_tag_v <= _GEN_78 & sectored_entries_0_2_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_78) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_0_2_data_0 <= _sectored_entries_2_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_0_2_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_0_2_tag_v) & (_GEN_82 ? sectored_entries_0_2_valid_0 : ~_GEN_68 & (_GEN_60 \| ~(~r_sectored_hit_valid & _GEN_60) & sectored_entries_0_2_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_83) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_0_3_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_0_3_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_0_3_tag_v <= _GEN_83 & sectored_entries_0_3_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_83) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_0_3_data_0 <= _sectored_entries_3_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_0_3_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_0_3_tag_v) & (_GEN_87 ? sectored_entries_0_3_valid_0 : ~_GEN_68 & (_GEN_60 \| ~(~r_sectored_hit_valid & _GEN_60) & sectored_entries_0_3_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_65) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_1_0_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_1_0_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_1_0_tag_v <= _GEN_65 & sectored_entries_1_0_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_65) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_1_0_data_0 <= _sectored_entries_0_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_1_0_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_1_0_tag_v) & (_GEN_69 ? sectored_entries_1_0_valid_0 : ~_GEN_70 & (_GEN_61 \| ~(~r_sectored_hit_valid & _GEN_61) & sectored_entries_1_0_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_74) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_1_1_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_1_1_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_1_1_tag_v <= _GEN_74 & sectored_entries_1_1_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_74) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_1_1_data_0 <= _sectored_entries_1_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_1_1_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_1_1_tag_v) & (_GEN_77 ? sectored_entries_1_1_valid_0 : ~_GEN_70 & (_GEN_61 \| ~(~r_sectored_hit_valid & _GEN_61) & sectored_entries_1_1_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_79) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_1_2_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_1_2_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_1_2_tag_v <= _GEN_79 & sectored_entries_1_2_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_79) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_1_2_data_0 <= _sectored_entries_2_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_1_2_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_1_2_tag_v) & (_GEN_82 ? sectored_entries_1_2_valid_0 : ~_GEN_70 & (_GEN_61 \| ~(~r_sectored_hit_valid & _GEN_61) & sectored_entries_1_2_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_84) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_1_3_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_1_3_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_1_3_tag_v <= _GEN_84 & sectored_entries_1_3_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_84) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_1_3_data_0 <= _sectored_entries_3_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_1_3_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_1_3_tag_v) & (_GEN_87 ? sectored_entries_1_3_valid_0 : ~_GEN_70 & (_GEN_61 \| ~(~r_sectored_hit_valid & _GEN_61) & sectored_entries_1_3_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_66) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_2_0_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_2_0_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_2_0_tag_v <= _GEN_66 & sectored_entries_2_0_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_66) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_2_0_data_0 <= _sectored_entries_0_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_2_0_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_2_0_tag_v) & (_GEN_69 ? sectored_entries_2_0_valid_0 : ~_GEN_71 & (_GEN_62 \| ~(~r_sectored_hit_valid & _GEN_62) & sectored_entries_2_0_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_75) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_2_1_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_2_1_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_2_1_tag_v <= _GEN_75 & sectored_entries_2_1_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_75) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_2_1_data_0 <= _sectored_entries_1_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_2_1_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_2_1_tag_v) & (_GEN_77 ? sectored_entries_2_1_valid_0 : ~_GEN_71 & (_GEN_62 \| ~(~r_sectored_hit_valid & _GEN_62) & sectored_entries_2_1_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_80) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_2_2_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_2_2_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_2_2_tag_v <= _GEN_80 & sectored_entries_2_2_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_80) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_2_2_data_0 <= _sectored_entries_2_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_2_2_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_2_2_tag_v) & (_GEN_82 ? sectored_entries_2_2_valid_0 : ~_GEN_71 & (_GEN_62 \| ~(~r_sectored_hit_valid & _GEN_62) & sectored_entries_2_2_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_85) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_2_3_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_2_3_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_2_3_tag_v <= _GEN_85 & sectored_entries_2_3_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_85) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_2_3_data_0 <= _sectored_entries_3_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_2_3_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_2_3_tag_v) & (_GEN_87 ? sectored_entries_2_3_valid_0 : ~_GEN_71 & (_GEN_62 \| ~(~r_sectored_hit_valid & _GEN_62) & sectored_entries_2_3_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_67) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_3_0_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_3_0_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_3_0_tag_v <= _GEN_67 & sectored_entries_3_0_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_67) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_3_0_data_0 <= _sectored_entries_0_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_3_0_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_3_0_tag_v) & (_GEN_69 ? sectored_entries_3_0_valid_0 : ~_GEN_72 & ((&r_memIdx) \| ~(~r_sectored_hit_valid & (&r_memIdx)) & sectored_entries_3_0_valid_0)); // @[package.scala:163:13] if (_GEN_76) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_3_1_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_3_1_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_3_1_tag_v <= _GEN_76 & sectored_entries_3_1_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_76) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_3_1_data_0 <= _sectored_entries_1_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_3_1_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_3_1_tag_v) & (_GEN_77 ? sectored_entries_3_1_valid_0 : ~_GEN_72 & ((&r_memIdx) \| ~(~r_sectored_hit_valid & (&r_memIdx)) & sectored_entries_3_1_valid_0)); // @[package.scala:163:13] if (_GEN_81) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_3_2_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_3_2_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_3_2_tag_v <= _GEN_81 & sectored_entries_3_2_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_81) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_3_2_data_0 <= _sectored_entries_2_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_3_2_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_3_2_tag_v) & (_GEN_82 ? sectored_entries_3_2_valid_0 : ~_GEN_72 & ((&r_memIdx) \| ~(~r_sectored_hit_valid & (&r_memIdx)) & sectored_entries_3_2_valid_0)); // @[package.scala:163:13] if (_GEN_86) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_3_3_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_3_3_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_3_3_tag_v <= _GEN_86 & sectored_entries_3_3_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_86) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_3_3_data_0 <= _sectored_entries_3_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_3_3_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_3_3_tag_v) & (_GEN_87 ? sectored_entries_3_3_valid_0 : ~_GEN_72 & ((&r_memIdx) \| ~(~r_sectored_hit_valid & (&r_memIdx)) & sectored_entries_3_3_valid_0)); // @[package.scala:163:13] if (_GEN_59) begin // @[TLB.scala:341:30, :446:20, :474:70, :476:58] end else begin // @[TLB.scala:341:30, :446:20, :474:70, :476:58] superpage_entries_0_level <= {1'h0, _superpage_entries_0_level_T}; // @[package.scala:163:13] superpage_entries_0_tag_vpn <= r_refill_tag; // @[TLB.scala:341:30, :354:25] end superpage_entries_0_tag_v <= _GEN_59 & superpage_entries_0_tag_v; // @[TLB.scala:341:30, :446:20, :474:70, :476:58] if (_GEN_59) begin // @[TLB.scala:341:30, :446:20, :474:70, :476:58] end else // @[TLB.scala:341:30, :446:20, :474:70, :476:58] superpage_entries_0_data_0 <= _superpage_entries_0_data_0_T; // @[TLB.scala:217:24, :341:30] superpage_entries_0_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~superpage_entries_0_tag_v) & (_GEN_59 ? superpage_entries_0_valid_0 : ~invalidate_refill); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :341:30, :410:88, :446:20, :474:70, :476:58, :480:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_58) begin // @[TLB.scala:211:18, :346:56, :446:20, :474:70] special_entry_level <= _special_entry_level_T; // @[package.scala:163:13] special_entry_tag_vpn <= r_refill_tag; // @[TLB.scala:346:56, :354:25] special_entry_data_0 <= _special_entry_data_0_T; // @[TLB.scala:217:24, :346:56] end special_entry_tag_v <= ~_GEN_58 & special_entry_tag_v; // @[TLB.scala:211:18, :212:16, :346:56, :446:20, :474:70] special_entry_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~special_entry_tag_v) & (_GEN_58 \| special_entry_valid_0); // @[TLB.scala:211:18, :216:16, :220:46, :223:{19,32,36}, :318:7, :346:56, :446:20, :474:70, :718:19, :723:42, :728:46, :732:{24,41}] if (_T_24) begin // @[Decoupled.scala:51:35] r_refill_tag <= vpn; // @[TLB.scala:335:30, :354:25] r_sectored_repl_addr <= _r_sectored_repl_addr_T_13; // @[TLB.scala:356:33, :757:8] r_sectored_hit_valid <= _r_sectored_hit_valid_T_2; // @[package.scala:81:59] r_sectored_hit_bits <= _r_sectored_hit_bits_T_4; // @[OneHot.scala:32:10] r_superpage_hit_valid <= superpage_hits_0; // @[TLB.scala:183:29, :358:28] r_need_gpa <= tlb_hit_if_not_gpa_miss; // @[TLB.scala:361:23, :610:43] end r_gpa_valid <= ~_T_2491 & (do_refill ? io_ptw_resp_bits_gpa_valid_0 : r_gpa_valid); // @[Decoupled.scala:51:35] if (do_refill) begin // @[TLB.scala:408:29] r_gpa <= io_ptw_resp_bits_gpa_bits_0; // @[TLB.scala:318:7, :363:18] r_gpa_is_pte <= io_ptw_resp_bits_gpa_is_pte_0; // @[TLB.scala:318:7, :365:25] end if (_T_2491) // @[Decoupled.scala:51:35] r_gpa_vpn <= r_refill_tag; // @[TLB.scala:354:25, :364:22] if (reset) begin // @[TLB.scala:318:7] state <= 2'h0; // @[TLB.scala:352:22] state_vec_0 <= 3'h0; // @[Replacement.scala:305:17] state_vec_1 <= 3'h0; // @[Replacement.scala:305:17] state_vec_2 <= 3'h0; // @[Replacement.scala:305:17] state_vec_3 <= 3'h0; // @[Replacement.scala:305:17] end else begin // @[TLB.scala:318:7] if (io_ptw_resp_valid_0) // @[TLB.scala:318:7] state <= 2'h0; // @[TLB.scala:352:22] else if (state == 2'h2 & io_sfence_valid_0) // @[TLB.scala:318:7, :352:22, :709:{17,28}] state <= 2'h3; // @[TLB.scala:352:22] else if (_T_25) begin // @[package.scala:16:47] if (io_ptw_req_ready_0) // @[TLB.scala:318:7] state <= _state_T; // @[TLB.scala:352:22, :704:45] else if (io_sfence_valid_0) // @[TLB.scala:318:7] state <= 2'h0; // @[TLB.scala:352:22] else if (_T_24) // @[Decoupled.scala:51:35] state <= 2'h1; // @[TLB.scala:197:28, :352:22] end else if (_T_24) // @[Decoupled.scala:51:35] state <= 2'h1; // @[TLB.scala:197:28, :352:22] if (_T_12 & _T_15 & memIdx == 2'h0) // @[package.scala:81:59, :163:13] state_vec_0 <= _state_vec_T_8; // @[Replacement.scala:202:12, :305:17] if (_T_12 & _T_15 & memIdx == 2'h1) // @[package.scala:81:59, :163:13] state_vec_1 <= _state_vec_T_8; // @[Replacement.scala:202:12, :305:17] if (_T_12 & _T_15 & memIdx == 2'h2) // @[package.scala:81:59, :163:13] state_vec_2 <= _state_vec_T_8; // @[Replacement.scala:202:12, :305:17] if (_T_12 & _T_15 & (&memIdx)) // @[package.scala:81:59, :163:13] state_vec_3 <= _state_vec_T_8; // @[Replacement.scala:202:12, :305:17] end always @(posedge) OptimizationBarrier_TLBEntryData_105 mpu_ppn_barrier ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_mpu_ppn_WIRE_ppn), // @[TLB.scala:170:77] .io_x_u (_mpu_ppn_WIRE_u), // @[TLB.scala:170:77] .io_x_g (_mpu_ppn_WIRE_g), // @[TLB.scala:170:77] .io_x_ae_ptw (_mpu_ppn_WIRE_ae_ptw), // @[TLB.scala:170:77] .io_x_ae_final (_mpu_ppn_WIRE_ae_final), // @[TLB.scala:170:77] .io_x_ae_stage2 (_mpu_ppn_WIRE_ae_stage2), // @[TLB.scala:170:77] .io_x_pf (_mpu_ppn_WIRE_pf), // @[TLB.scala:170:77] .io_x_gf (_mpu_ppn_WIRE_gf), // @[TLB.scala:170:77] .io_x_sw (_mpu_ppn_WIRE_sw), // @[TLB.scala:170:77] .io_x_sx (_mpu_ppn_WIRE_sx), // @[TLB.scala:170:77] .io_x_sr (_mpu_ppn_WIRE_sr), // @[TLB.scala:170:77] .io_x_hw (_mpu_ppn_WIRE_hw), // @[TLB.scala:170:77] .io_x_hx (_mpu_ppn_WIRE_hx), // @[TLB.scala:170:77] .io_x_hr (_mpu_ppn_WIRE_hr), // @[TLB.scala:170:77] .io_x_pw (_mpu_ppn_WIRE_pw), // @[TLB.scala:170:77] .io_x_px (_mpu_ppn_WIRE_px), // @[TLB.scala:170:77] .io_x_pr (_mpu_ppn_WIRE_pr), // @[TLB.scala:170:77] .io_x_ppp (_mpu_ppn_WIRE_ppp), // @[TLB.scala:170:77] .io_x_pal (_mpu_ppn_WIRE_pal), // @[TLB.scala:170:77] .io_x_paa (_mpu_ppn_WIRE_paa), // @[TLB.scala:170:77] .io_x_eff (_mpu_ppn_WIRE_eff), // @[TLB.scala:170:77] .io_x_c (_mpu_ppn_WIRE_c), // @[TLB.scala:170:77] .io_x_fragmented_superpage (_mpu_ppn_WIRE_fragmented_superpage), // @[TLB.scala:170:77] .io_y_ppn (_mpu_ppn_barrier_io_y_ppn) ); // @[package.scala:267:25] PMPChecker_s3_13 pmp ( // @[TLB.scala:416:19] .clock (clock), .reset (reset), .io_prv (mpu_priv[1:0]), // @[TLB.scala:415:27, :420:14] .io_pmp_0_cfg_l (io_ptw_pmp_0_cfg_l_0), // @[TLB.scala:318:7] .io_pmp_0_cfg_a (io_ptw_pmp_0_cfg_a_0), // @[TLB.scala:318:7] .io_pmp_0_cfg_x (io_ptw_pmp_0_cfg_x_0), // @[TLB.scala:318:7] .io_pmp_0_cfg_w (io_ptw_pmp_0_cfg_w_0), // @[TLB.scala:318:7] .io_pmp_0_cfg_r (io_ptw_pmp_0_cfg_r_0), // @[TLB.scala:318:7] .io_pmp_0_addr (io_ptw_pmp_0_addr_0), // @[TLB.scala:318:7] .io_pmp_0_mask (io_ptw_pmp_0_mask_0), // @[TLB.scala:318:7] .io_pmp_1_cfg_l (io_ptw_pmp_1_cfg_l_0), // @[TLB.scala:318:7] .io_pmp_1_cfg_a (io_ptw_pmp_1_cfg_a_0), // @[TLB.scala:318:7] .io_pmp_1_cfg_x (io_ptw_pmp_1_cfg_x_0), // @[TLB.scala:318:7] .io_pmp_1_cfg_w (io_ptw_pmp_1_cfg_w_0), // @[TLB.scala:318:7] .io_pmp_1_cfg_r (io_ptw_pmp_1_cfg_r_0), // @[TLB.scala:318:7] .io_pmp_1_addr (io_ptw_pmp_1_addr_0), // @[TLB.scala:318:7] .io_pmp_1_mask (io_ptw_pmp_1_mask_0), // @[TLB.scala:318:7] .io_pmp_2_cfg_l (io_ptw_pmp_2_cfg_l_0), // @[TLB.scala:318:7] .io_pmp_2_cfg_a (io_ptw_pmp_2_cfg_a_0), // @[TLB.scala:318:7] .io_pmp_2_cfg_x (io_ptw_pmp_2_cfg_x_0), // @[TLB.scala:318:7] .io_pmp_2_cfg_w (io_ptw_pmp_2_cfg_w_0), // @[TLB.scala:318:7] .io_pmp_2_cfg_r (io_ptw_pmp_2_cfg_r_0), // @[TLB.scala:318:7] .io_pmp_2_addr (io_ptw_pmp_2_addr_0), // @[TLB.scala:318:7] .io_pmp_2_mask (io_ptw_pmp_2_mask_0), // @[TLB.scala:318:7] .io_pmp_3_cfg_l (io_ptw_pmp_3_cfg_l_0), // @[TLB.scala:318:7] .io_pmp_3_cfg_a (io_ptw_pmp_3_cfg_a_0), // @[TLB.scala:318:7] .io_pmp_3_cfg_x (io_ptw_pmp_3_cfg_x_0), // @[TLB.scala:318:7] .io_pmp_3_cfg_w (io_ptw_pmp_3_cfg_w_0), // @[TLB.scala:318:7] .io_pmp_3_cfg_r (io_ptw_pmp_3_cfg_r_0), // @[TLB.scala:318:7] .io_pmp_3_addr (io_ptw_pmp_3_addr_0), // @[TLB.scala:318:7] .io_pmp_3_mask (io_ptw_pmp_3_mask_0), // @[TLB.scala:318:7] .io_pmp_4_cfg_l (io_ptw_pmp_4_cfg_l_0), // @[TLB.scala:318:7] .io_pmp_4_cfg_a (io_ptw_pmp_4_cfg_a_0), // @[TLB.scala:318:7] .io_pmp_4_cfg_x (io_ptw_pmp_4_cfg_x_0), // @[TLB.scala:318:7] .io_pmp_4_cfg_w (io_ptw_pmp_4_cfg_w_0), // @[TLB.scala:318:7] .io_pmp_4_cfg_r (io_ptw_pmp_4_cfg_r_0), // @[TLB.scala:318:7] .io_pmp_4_addr (io_ptw_pmp_4_addr_0), // @[TLB.scala:318:7] .io_pmp_4_mask (io_ptw_pmp_4_mask_0), // @[TLB.scala:318:7] .io_pmp_5_cfg_l (io_ptw_pmp_5_cfg_l_0), // @[TLB.scala:318:7] .io_pmp_5_cfg_a (io_ptw_pmp_5_cfg_a_0), // @[TLB.scala:318:7] .io_pmp_5_cfg_x (io_ptw_pmp_5_cfg_x_0), // @[TLB.scala:318:7] .io_pmp_5_cfg_w (io_ptw_pmp_5_cfg_w_0), // @[TLB.scala:318:7] .io_pmp_5_cfg_r (io_ptw_pmp_5_cfg_r_0), // @[TLB.scala:318:7] .io_pmp_5_addr (io_ptw_pmp_5_addr_0), // @[TLB.scala:318:7] .io_pmp_5_mask (io_ptw_pmp_5_mask_0), // @[TLB.scala:318:7] .io_pmp_6_cfg_l (io_ptw_pmp_6_cfg_l_0), // @[TLB.scala:318:7] .io_pmp_6_cfg_a (io_ptw_pmp_6_cfg_a_0), // @[TLB.scala:318:7] .io_pmp_6_cfg_x (io_ptw_pmp_6_cfg_x_0), // @[TLB.scala:318:7] .io_pmp_6_cfg_w (io_ptw_pmp_6_cfg_w_0), // @[TLB.scala:318:7] .io_pmp_6_cfg_r (io_ptw_pmp_6_cfg_r_0), // @[TLB.scala:318:7] .io_pmp_6_addr (io_ptw_pmp_6_addr_0), // @[TLB.scala:318:7] .io_pmp_6_mask (io_ptw_pmp_6_mask_0), // @[TLB.scala:318:7] .io_pmp_7_cfg_l (io_ptw_pmp_7_cfg_l_0), // @[TLB.scala:318:7] .io_pmp_7_cfg_a (io_ptw_pmp_7_cfg_a_0), // @[TLB.scala:318:7] .io_pmp_7_cfg_x (io_ptw_pmp_7_cfg_x_0), // @[TLB.scala:318:7] .io_pmp_7_cfg_w (io_ptw_pmp_7_cfg_w_0), // @[TLB.scala:318:7] .io_pmp_7_cfg_r (io_ptw_pmp_7_cfg_r_0), // @[TLB.scala:318:7] .io_pmp_7_addr (io_ptw_pmp_7_addr_0), // @[TLB.scala:318:7] .io_pmp_7_mask (io_ptw_pmp_7_mask_0), // @[TLB.scala:318:7] .io_addr (mpu_physaddr[31:0]), // @[TLB.scala:414:25, :417:15] .io_size (io_req_bits_size_0), // @[TLB.scala:318:7] .io_r (_pmp_io_r), .io_w (_pmp_io_w), .io_x (_pmp_io_x) ); // @[TLB.scala:416:19] PMAChecker_13 pma ( // @[TLB.scala:422:19] .clock (clock), .reset (reset), .io_paddr (mpu_physaddr), // @[TLB.scala:414:25] .io_resp_cacheable (cacheable), .io_resp_r (_pma_io_resp_r), .io_resp_w (_pma_io_resp_w), .io_resp_pp (_pma_io_resp_pp), .io_resp_al (_pma_io_resp_al), .io_resp_aa (_pma_io_resp_aa), .io_resp_x (_pma_io_resp_x), .io_resp_eff (_pma_io_resp_eff) ); // @[TLB.scala:422:19] assign newEntry_ppp = _pma_io_resp_pp; // @[TLB.scala:422:19, :449:24] assign newEntry_pal = _pma_io_resp_al; // @[TLB.scala:422:19, :449:24] assign newEntry_paa = _pma_io_resp_aa; // @[TLB.scala:422:19, :449:24] assign newEntry_eff = _pma_io_resp_eff; // @[TLB.scala:422:19, :449:24] OptimizationBarrier_TLBEntryData_106 entries_barrier ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_ppn), // @[TLB.scala:170:77] .io_x_u (_entries_WIRE_u), // @[TLB.scala:170:77] .io_x_g (_entries_WIRE_g), // @[TLB.scala:170:77] .io_x_ae_ptw (_entries_WIRE_ae_ptw), // @[TLB.scala:170:77] .io_x_ae_final (_entries_WIRE_ae_final), // @[TLB.scala:170:77] .io_x_ae_stage2 (_entries_WIRE_ae_stage2), // @[TLB.scala:170:77] .io_x_pf (_entries_WIRE_pf), // @[TLB.scala:170:77] .io_x_gf (_entries_WIRE_gf), // @[TLB.scala:170:77] .io_x_sw (_entries_WIRE_sw), // @[TLB.scala:170:77] .io_x_sx (_entries_WIRE_sx), // @[TLB.scala:170:77] .io_x_sr (_entries_WIRE_sr), // @[TLB.scala:170:77] .io_x_hw (_entries_WIRE_hw), // @[TLB.scala:170:77] .io_x_hx (_entries_WIRE_hx), // @[TLB.scala:170:77] .io_x_hr (_entries_WIRE_hr), // @[TLB.scala:170:77] .io_x_pw (_entries_WIRE_pw), // @[TLB.scala:170:77] .io_x_px (_entries_WIRE_px), // @[TLB.scala:170:77] .io_x_pr (_entries_WIRE_pr), // @[TLB.scala:170:77] .io_x_ppp (_entries_WIRE_ppp), // @[TLB.scala:170:77] .io_x_pal (_entries_WIRE_pal), // @[TLB.scala:170:77] .io_x_paa (_entries_WIRE_paa), // @[TLB.scala:170:77] .io_x_eff (_entries_WIRE_eff), // @[TLB.scala:170:77] .io_x_c (_entries_WIRE_c), // @[TLB.scala:170:77] .io_x_fragmented_superpage (_entries_WIRE_fragmented_superpage), // @[TLB.scala:170:77] .io_y_ppn (_entries_barrier_io_y_ppn), .io_y_u (_entries_barrier_io_y_u), .io_y_ae_ptw (_entries_barrier_io_y_ae_ptw), .io_y_ae_final (_entries_barrier_io_y_ae_final), .io_y_ae_stage2 (_entries_barrier_io_y_ae_stage2), .io_y_pf (_entries_barrier_io_y_pf), .io_y_gf (_entries_barrier_io_y_gf), .io_y_sw (_entries_barrier_io_y_sw), .io_y_sx (_entries_barrier_io_y_sx), .io_y_sr (_entries_barrier_io_y_sr), .io_y_hw (_entries_barrier_io_y_hw), .io_y_hx (_entries_barrier_io_y_hx), .io_y_hr (_entries_barrier_io_y_hr), .io_y_pw (_entries_barrier_io_y_pw), .io_y_px (_entries_barrier_io_y_px), .io_y_pr (_entries_barrier_io_y_pr), .io_y_ppp (_entries_barrier_io_y_ppp), .io_y_pal (_entries_barrier_io_y_pal), .io_y_paa (_entries_barrier_io_y_paa), .io_y_eff (_entries_barrier_io_y_eff), .io_y_c (_entries_barrier_io_y_c) ); // @[package.scala:267:25] OptimizationBarrier_TLBEntryData_107 entries_barrier_1 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_2_ppn), // @[TLB.scala:170:77] .io_x_u (_entries_WIRE_2_u), // @[TLB.scala:170:77] .io_x_g (_entries_WIRE_2_g), // @[TLB.scala:170:77] .io_x_ae_ptw (_entries_WIRE_2_ae_ptw), // @[TLB.scala:170:77] .io_x_ae_final (_entries_WIRE_2_ae_final), // @[TLB.scala:170:77] .io_x_ae_stage2 (_entries_WIRE_2_ae_stage2), // @[TLB.scala:170:77] .io_x_pf (_entries_WIRE_2_pf), // @[TLB.scala:170:77] .io_x_gf (_entries_WIRE_2_gf), // @[TLB.scala:170:77] .io_x_sw (_entries_WIRE_2_sw), // @[TLB.scala:170:77] .io_x_sx (_entries_WIRE_2_sx), // @[TLB.scala:170:77] .io_x_sr (_entries_WIRE_2_sr), // @[TLB.scala:170:77] .io_x_hw (_entries_WIRE_2_hw), // @[TLB.scala:170:77] .io_x_hx (_entries_WIRE_2_hx), // @[TLB.scala:170:77] .io_x_hr (_entries_WIRE_2_hr), // @[TLB.scala:170:77] .io_x_pw (_entries_WIRE_2_pw), // @[TLB.scala:170:77] .io_x_px (_entries_WIRE_2_px), // @[TLB.scala:170:77] .io_x_pr (_entries_WIRE_2_pr), // @[TLB.scala:170:77] .io_x_ppp (_entries_WIRE_2_ppp), // @[TLB.scala:170:77] .io_x_pal (_entries_WIRE_2_pal), // @[TLB.scala:170:77] .io_x_paa (_entries_WIRE_2_paa), // @[TLB.scala:170:77] .io_x_eff (_entries_WIRE_2_eff), // @[TLB.scala:170:77] .io_x_c (_entries_WIRE_2_c), // @[TLB.scala:170:77] .io_x_fragmented_superpage (_entries_WIRE_2_fragmented_superpage), // @[TLB.scala:170:77] .io_y_ppn (_entries_barrier_1_io_y_ppn), .io_y_u (_entries_barrier_1_io_y_u), .io_y_ae_ptw (_entries_barrier_1_io_y_ae_ptw), .io_y_ae_final (_entries_barrier_1_io_y_ae_final), .io_y_ae_stage2 (_entries_barrier_1_io_y_ae_stage2), .io_y_pf (_entries_barrier_1_io_y_pf), .io_y_gf (_entries_barrier_1_io_y_gf), .io_y_sw (_entries_barrier_1_io_y_sw), .io_y_sx (_entries_barrier_1_io_y_sx), .io_y_sr (_entries_barrier_1_io_y_sr), .io_y_hw (_entries_barrier_1_io_y_hw), .io_y_hx (_entries_barrier_1_io_y_hx), .io_y_hr (_entries_barrier_1_io_y_hr), .io_y_pw (_entries_barrier_1_io_y_pw), .io_y_px (_entries_barrier_1_io_y_px), .io_y_pr (_entries_barrier_1_io_y_pr), .io_y_ppp (_entries_barrier_1_io_y_ppp), .io_y_pal (_entries_barrier_1_io_y_pal), .io_y_paa (_entries_barrier_1_io_y_paa), .io_y_eff (_entries_barrier_1_io_y_eff), .io_y_c (_entries_barrier_1_io_y_c) ); // @[package.scala:267:25] OptimizationBarrier_TLBEntryData_108 entries_barrier_2 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_4_ppn), // @[TLB.scala:170:77] .io_x_u (_entries_WIRE_4_u), // @[TLB.scala:170:77] .io_x_g (_entries_WIRE_4_g), // @[TLB.scala:170:77] .io_x_ae_ptw (_entries_WIRE_4_ae_ptw), // @[TLB.scala:170:77] .io_x_ae_final (_entries_WIRE_4_ae_final), // @[TLB.scala:170:77] .io_x_ae_stage2 (_entries_WIRE_4_ae_stage2), // @[TLB.scala:170:77] .io_x_pf (_entries_WIRE_4_pf), // @[TLB.scala:170:77] .io_x_gf (_entries_WIRE_4_gf), // @[TLB.scala:170:77] .io_x_sw (_entries_WIRE_4_sw), // @[TLB.scala:170:77] .io_x_sx (_entries_WIRE_4_sx), // @[TLB.scala:170:77] .io_x_sr (_entries_WIRE_4_sr), // @[TLB.scala:170:77] .io_x_hw (_entries_WIRE_4_hw), // @[TLB.scala:170:77] .io_x_hx (_entries_WIRE_4_hx), // @[TLB.scala:170:77] .io_x_hr (_entries_WIRE_4_hr), // @[TLB.scala:170:77] .io_x_pw (_entries_WIRE_4_pw), // @[TLB.scala:170:77] .io_x_px (_entries_WIRE_4_px), // @[TLB.scala:170:77] .io_x_pr (_entries_WIRE_4_pr), // @[TLB.scala:170:77] .io_x_ppp (_entries_WIRE_4_ppp), // @[TLB.scala:170:77] .io_x_pal (_entries_WIRE_4_pal), // @[TLB.scala:170:77] .io_x_paa (_entries_WIRE_4_paa), // @[TLB.scala:170:77] .io_x_eff (_entries_WIRE_4_eff), // @[TLB.scala:170:77] .io_x_c (_entries_WIRE_4_c), // @[TLB.scala:170:77] .io_x_fragmented_superpage (_entries_WIRE_4_fragmented_superpage), // @[TLB.scala:170:77] .io_y_ppn (_entries_barrier_2_io_y_ppn), .io_y_u (_entries_barrier_2_io_y_u), .io_y_ae_ptw (_entries_barrier_2_io_y_ae_ptw), .io_y_ae_final (_entries_barrier_2_io_y_ae_final), .io_y_ae_stage2 (_entries_barrier_2_io_y_ae_stage2), .io_y_pf (_entries_barrier_2_io_y_pf), .io_y_gf (_entries_barrier_2_io_y_gf), .io_y_sw (_entries_barrier_2_io_y_sw), .io_y_sx (_entries_barrier_2_io_y_sx), .io_y_sr (_entries_barrier_2_io_y_sr), .io_y_hw (_entries_barrier_2_io_y_hw), .io_y_hx (_entries_barrier_2_io_y_hx), .io_y_hr (_entries_barrier_2_io_y_hr), .io_y_pw (_entries_barrier_2_io_y_pw), .io_y_px (_entries_barrier_2_io_y_px), .io_y_pr (_entries_barrier_2_io_y_pr), .io_y_ppp (_entries_barrier_2_io_y_ppp), .io_y_pal (_entries_barrier_2_io_y_pal), .io_y_paa (_entries_barrier_2_io_y_paa), .io_y_eff (_entries_barrier_2_io_y_eff), .io_y_c (_entries_barrier_2_io_y_c) ); // @[package.scala:267:25] OptimizationBarrier_TLBEntryData_109 entries_barrier_3 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_6_ppn), // @[TLB.scala:170:77] .io_x_u (_entries_WIRE_6_u), // @[TLB.scala:170:77] .io_x_g (_entries_WIRE_6_g), // @[TLB.scala:170:77] .io_x_ae_ptw (_entries_WIRE_6_ae_ptw), // @[TLB.scala:170:77] .io_x_ae_final (_entries_WIRE_6_ae_final), // @[TLB.scala:170:77] .io_x_ae_stage2 (_entries_WIRE_6_ae_stage2), // @[TLB.scala:170:77] .io_x_pf (_entries_WIRE_6_pf), // @[TLB.scala:170:77] .io_x_gf (_entries_WIRE_6_gf), // @[TLB.scala:170:77] .io_x_sw (_entries_WIRE_6_sw), // @[TLB.scala:170:77] .io_x_sx (_entries_WIRE_6_sx), // @[TLB.scala:170:77] .io_x_sr (_entries_WIRE_6_sr), // @[TLB.scala:170:77] .io_x_hw (_entries_WIRE_6_hw), // @[TLB.scala:170:77] .io_x_hx (_entries_WIRE_6_hx), // @[TLB.scala:170:77] .io_x_hr (_entries_WIRE_6_hr), // @[TLB.scala:170:77] .io_x_pw (_entries_WIRE_6_pw), // @[TLB.scala:170:77] .io_x_px (_entries_WIRE_6_px), // @[TLB.scala:170:77] .io_x_pr (_entries_WIRE_6_pr), // @[TLB.scala:170:77] .io_x_ppp (_entries_WIRE_6_ppp), // @[TLB.scala:170:77] .io_x_pal (_entries_WIRE_6_pal), // @[TLB.scala:170:77] .io_x_paa (_entries_WIRE_6_paa), // @[TLB.scala:170:77] .io_x_eff (_entries_WIRE_6_eff), // @[TLB.scala:170:77] .io_x_c (_entries_WIRE_6_c), // @[TLB.scala:170:77] .io_x_fragmented_superpage (_entries_WIRE_6_fragmented_superpage), // @[TLB.scala:170:77] .io_y_ppn (_entries_barrier_3_io_y_ppn), .io_y_u (_entries_barrier_3_io_y_u), .io_y_ae_ptw (_entries_barrier_3_io_y_ae_ptw), .io_y_ae_final (_entries_barrier_3_io_y_ae_final), .io_y_ae_stage2 (_entries_barrier_3_io_y_ae_stage2), .io_y_pf (_entries_barrier_3_io_y_pf), .io_y_gf (_entries_barrier_3_io_y_gf), .io_y_sw (_entries_barrier_3_io_y_sw), .io_y_sx (_entries_barrier_3_io_y_sx), .io_y_sr (_entries_barrier_3_io_y_sr), .io_y_hw (_entries_barrier_3_io_y_hw), .io_y_hx (_entries_barrier_3_io_y_hx), .io_y_hr (_entries_barrier_3_io_y_hr), .io_y_pw (_entries_barrier_3_io_y_pw), .io_y_px (_entries_barrier_3_io_y_px), .io_y_pr (_entries_barrier_3_io_y_pr), .io_y_ppp (_entries_barrier_3_io_y_ppp), .io_y_pal (_entries_barrier_3_io_y_pal), .io_y_paa (_entries_barrier_3_io_y_paa), .io_y_eff (_entries_barrier_3_io_y_eff), .io_y_c (_entries_barrier_3_io_y_c) ); // @[package.scala:267:25] OptimizationBarrier_TLBEntryData_110 entries_barrier_4 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_8_ppn), // @[TLB.scala:170:77] .io_x_u (_entries_WIRE_8_u), // @[TLB.scala:170:77] .io_x_g (_entries_WIRE_8_g), // @[TLB.scala:170:77] .io_x_ae_ptw (_entries_WIRE_8_ae_ptw), // @[TLB.scala:170:77] .io_x_ae_final (_entries_WIRE_8_ae_final), // @[TLB.scala:170:77] .io_x_ae_stage2 (_entries_WIRE_8_ae_stage2), // @[TLB.scala:170:77] .io_x_pf (_entries_WIRE_8_pf), // @[TLB.scala:170:77] .io_x_gf (_entries_WIRE_8_gf), // @[TLB.scala:170:77] .io_x_sw (_entries_WIRE_8_sw), // @[TLB.scala:170:77] .io_x_sx (_entries_WIRE_8_sx), // @[TLB.scala:170:77] .io_x_sr (_entries_WIRE_8_sr), // @[TLB.scala:170:77] .io_x_hw (_entries_WIRE_8_hw), // @[TLB.scala:170:77] .io_x_hx (_entries_WIRE_8_hx), // @[TLB.scala:170:77] .io_x_hr (_entries_WIRE_8_hr), // @[TLB.scala:170:77] .io_x_pw (_entries_WIRE_8_pw), // @[TLB.scala:170:77] .io_x_px (_entries_WIRE_8_px), // @[TLB.scala:170:77] .io_x_pr (_entries_WIRE_8_pr), // @[TLB.scala:170:77] .io_x_ppp (_entries_WIRE_8_ppp), // @[TLB.scala:170:77] .io_x_pal (_entries_WIRE_8_pal), // @[TLB.scala:170:77] .io_x_paa (_entries_WIRE_8_paa), // @[TLB.scala:170:77] .io_x_eff (_entries_WIRE_8_eff), // @[TLB.scala:170:77] .io_x_c (_entries_WIRE_8_c), // @[TLB.scala:170:77] .io_x_fragmented_superpage (_entries_WIRE_8_fragmented_superpage), // @[TLB.scala:170:77] .io_y_ppn (_entries_barrier_4_io_y_ppn), .io_y_u (_entries_barrier_4_io_y_u), .io_y_ae_ptw (_entries_barrier_4_io_y_ae_ptw), .io_y_ae_final (_entries_barrier_4_io_y_ae_final), .io_y_ae_stage2 (_entries_barrier_4_io_y_ae_stage2), .io_y_pf (_entries_barrier_4_io_y_pf), .io_y_gf (_entries_barrier_4_io_y_gf), .io_y_sw (_entries_barrier_4_io_y_sw), .io_y_sx (_entries_barrier_4_io_y_sx), .io_y_sr (_entries_barrier_4_io_y_sr), .io_y_hw (_entries_barrier_4_io_y_hw), .io_y_hx (_entries_barrier_4_io_y_hx), .io_y_hr (_entries_barrier_4_io_y_hr), .io_y_pw (_entries_barrier_4_io_y_pw), .io_y_px (_entries_barrier_4_io_y_px), .io_y_pr (_entries_barrier_4_io_y_pr), .io_y_ppp (_entries_barrier_4_io_y_ppp), .io_y_pal (_entries_barrier_4_io_y_pal), .io_y_paa (_entries_barrier_4_io_y_paa), .io_y_eff (_entries_barrier_4_io_y_eff), .io_y_c (_entries_barrier_4_io_y_c) ); // @[package.scala:267:25] OptimizationBarrier_TLBEntryData_111 entries_barrier_5 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_10_ppn), // @[TLB.scala:170:77] .io_x_u (_entries_WIRE_10_u), // @[TLB.scala:170:77] .io_x_g (_entries_WIRE_10_g), // @[TLB.scala:170:77] .io_x_ae_ptw (_entries_WIRE_10_ae_ptw), // @[TLB.scala:170:77] .io_x_ae_final (_entries_WIRE_10_ae_final), // @[TLB.scala:170:77] .io_x_ae_stage2 (_entries_WIRE_10_ae_stage2), // @[TLB.scala:170:77] .io_x_pf (_entries_WIRE_10_pf), // @[TLB.scala:170:77] .io_x_gf (_entries_WIRE_10_gf), // @[TLB.scala:170:77] .io_x_sw (_entries_WIRE_10_sw), // @[TLB.scala:170:77] .io_x_sx (_entries_WIRE_10_sx), // @[TLB.scala:170:77] .io_x_sr (_entries_WIRE_10_sr), // @[TLB.scala:170:77] .io_x_hw (_entries_WIRE_10_hw), // @[TLB.scala:170:77] .io_x_hx (_entries_WIRE_10_hx), // @[TLB.scala:170:77] .io_x_hr (_entries_WIRE_10_hr), // @[TLB.scala:170:77] .io_x_pw (_entries_WIRE_10_pw), // @[TLB.scala:170:77] .io_x_px (_entries_WIRE_10_px), // @[TLB.scala:170:77] .io_x_pr (_entries_WIRE_10_pr), // @[TLB.scala:170:77] .io_x_ppp (_entries_WIRE_10_ppp), // @[TLB.scala:170:77] .io_x_pal (_entries_WIRE_10_pal), // @[TLB.scala:170:77] .io_x_paa (_entries_WIRE_10_paa), // @[TLB.scala:170:77] .io_x_eff (_entries_WIRE_10_eff), // @[TLB.scala:170:77] .io_x_c (_entries_WIRE_10_c), // @[TLB.scala:170:77] .io_x_fragmented_superpage (_entries_WIRE_10_fragmented_superpage), // @[TLB.scala:170:77] .io_y_ppn (_entries_barrier_5_io_y_ppn), .io_y_u (_entries_barrier_5_io_y_u), .io_y_ae_ptw (_entries_barrier_5_io_y_ae_ptw), .io_y_ae_final (_entries_barrier_5_io_y_ae_final), .io_y_ae_stage2 (_entries_barrier_5_io_y_ae_stage2), .io_y_pf (_entries_barrier_5_io_y_pf), .io_y_gf (_entries_barrier_5_io_y_gf), .io_y_sw (_entries_barrier_5_io_y_sw), .io_y_sx (_entries_barrier_5_io_y_sx), .io_y_sr (_entries_barrier_5_io_y_sr), .io_y_hw (_entries_barrier_5_io_y_hw), .io_y_hx (_entries_barrier_5_io_y_hx), .io_y_hr (_entries_barrier_5_io_y_hr) ); // @[package.scala:267:25] assign io_req_ready = io_req_ready_0; // @[TLB.scala:318:7] assign io_resp_miss = io_resp_miss_0; // @[TLB.scala:318:7] assign io_resp_paddr = io_resp_paddr_0; // @[TLB.scala:318:7] assign io_ptw_req_valid = io_ptw_req_valid_0; // @[TLB.scala:318:7] assign io_ptw_req_bits_bits_addr = io_ptw_req_bits_bits_addr_0; // @[TLB.scala:318:7] assign io_ptw_req_bits_bits_need_gpa = io_ptw_req_bits_bits_need_gpa_0; // @[TLB.scala:318:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth \| params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset \|\| !sio.sink_reset_n) \|\| !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise \|\| prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready \|\| !sio.source_reset_n \|\| reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise \|\| prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }	module AsyncQueueSink_DebugInternalBundle( // @[AsyncQueue.scala:136:7] input clock, // @[AsyncQueue.scala:136:7] input reset, // @[AsyncQueue.scala:136:7] output io_deq_valid, // @[AsyncQueue.scala:139:14] output io_deq_bits_resumereq, // @[AsyncQueue.scala:139:14] output [9:0] io_deq_bits_hartsel, // @[AsyncQueue.scala:139:14] output io_deq_bits_ackhavereset, // @[AsyncQueue.scala:139:14] output io_deq_bits_hrmask_0, // @[AsyncQueue.scala:139:14] input io_async_mem_0_resumereq, // @[AsyncQueue.scala:139:14] input [9:0] io_async_mem_0_hartsel, // @[AsyncQueue.scala:139:14] input io_async_mem_0_ackhavereset, // @[AsyncQueue.scala:139:14] input io_async_mem_0_hrmask_0, // @[AsyncQueue.scala:139:14] output io_async_ridx, // @[AsyncQueue.scala:139:14] input io_async_widx, // @[AsyncQueue.scala:139:14] output io_async_safe_ridx_valid, // @[AsyncQueue.scala:139:14] input io_async_safe_widx_valid, // @[AsyncQueue.scala:139:14] input io_async_safe_source_reset_n, // @[AsyncQueue.scala:139:14] output io_async_safe_sink_reset_n // @[AsyncQueue.scala:139:14] ); wire io_deq_valid_0; // @[AsyncQueue.scala:166:29] wire _source_valid_io_out; // @[AsyncQueue.scala:176:31] wire _source_extend_io_out; // @[AsyncQueue.scala:175:31] wire _sink_valid_0_io_out; // @[AsyncQueue.scala:172:33] wire [14:0] _io_deq_bits_deq_bits_reg_io_q; // @[SynchronizerReg.scala:207:25] wire _widx_widx_gray_io_q; // @[ShiftReg.scala:45:23] reg ridx_ridx_bin; // @[AsyncQueue.scala:52:25] wire ridx = _source_valid_io_out & ridx_ridx_bin + io_deq_valid_0; // @[AsyncQueue.scala:52:25, :53:{23,43}, :166:29, :176:31] wire valid = _source_valid_io_out & ridx != _widx_widx_gray_io_q; // @[ShiftReg.scala:45:23] reg valid_reg; // @[AsyncQueue.scala:165:56] assign io_deq_valid_0 = valid_reg & _source_valid_io_out; // @[AsyncQueue.scala:165:56, :166:29, :176:31] reg ridx_gray; // @[AsyncQueue.scala:168:55] always @(posedge clock or posedge reset) begin // @[AsyncQueue.scala:136:7] if (reset) begin // @[AsyncQueue.scala:136:7] ridx_ridx_bin <= 1'h0; // @[AsyncQueue.scala:52:25, :136:7] valid_reg <= 1'h0; // @[AsyncQueue.scala:136:7, :165:56] ridx_gray <= 1'h0; // @[AsyncQueue.scala:136:7, :168:55] end else begin // @[AsyncQueue.scala:136:7] ridx_ridx_bin <= ridx; // @[AsyncQueue.scala:52:25, :53:23] valid_reg <= valid; // @[AsyncQueue.scala:150:28, :165:56] ridx_gray <= ridx; // @[AsyncQueue.scala:53:23, :168:55] end always @(posedge, posedge)
Generate the Verilog code corresponding to the following Chisel files. File Crossing.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.interrupts import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg} @deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2") class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val intnode = IntAdapterNode() lazy val module = new Impl class Impl extends LazyModuleImp(this) { (intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) => out := SynchronizerShiftReg(in, sync) } } } object IntSyncCrossingSource { def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) = { val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered)) intsource.node } } class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule { val node = IntSyncSourceNode(alreadyRegistered) lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl) class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := AsyncResetReg(Cat(in.reverse)).asBools } } class ImplRegistered extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}_Registered" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := in } } } object IntSyncCrossingSink { @deprecated("IntSyncCrossingSink which used the `sync` parameter to determine crossing type is deprecated. Use IntSyncAsyncCrossingSink, IntSyncRationalCrossingSink, or IntSyncSyncCrossingSink instead for > 1, 1, and 0 sync values respectively", "rocket-chip 1.2") def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncAsyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(sync) lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = s"IntSyncAsyncCrossingSink_n${node.out.size}x${node.out.head._1.size}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := SynchronizerShiftReg(in.sync, sync) } } } object IntSyncAsyncCrossingSink { def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncSyncCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(0) lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncSyncCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := in.sync } } } object IntSyncSyncCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncSyncCrossingSink()) intsink.node } } class IntSyncRationalCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(1) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncRationalCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := RegNext(in.sync) } } } object IntSyncRationalCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncRationalCrossingSink()) intsink.node } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File AsyncResetReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ /* This black-boxes an Async Reset * (or Set) * Register. * * Because Chisel doesn't support * parameterized black boxes, * we unfortunately have to * instantiate a number of these. * * We also have to hard-code the set/ * reset behavior. * * Do not confuse an asynchronous * reset signal with an asynchronously * reset reg. You should still * properly synchronize your reset * deassertion. * * @param d Data input * @param q Data Output * @param clk Clock Input * @param rst Reset Input * @param en Write Enable Input * */ class AsyncResetReg(resetValue: Int = 0) extends RawModule { val io = IO(new Bundle { val d = Input(Bool()) val q = Output(Bool()) val en = Input(Bool()) val clk = Input(Clock()) val rst = Input(Reset()) }) val reg = withClockAndReset(io.clk, io.rst.asAsyncReset)(RegInit(resetValue.U(1.W))) when (io.en) { reg := io.d } io.q := reg } class SimpleRegIO(val w: Int) extends Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) } class AsyncResetRegVec(val w: Int, val init: BigInt) extends Module { override def desiredName = s"AsyncResetRegVec_w${w}_i${init}" val io = IO(new SimpleRegIO(w)) val reg = withReset(reset.asAsyncReset)(RegInit(init.U(w.W))) when (io.en) { reg := io.d } io.q := reg } object AsyncResetReg { // Create Single Registers def apply(d: Bool, clk: Clock, rst: Bool, init: Boolean, name: Option[String]): Bool = { val reg = Module(new AsyncResetReg(if (init) 1 else 0)) reg.io.d := d reg.io.clk := clk reg.io.rst := rst reg.io.en := true.B name.foreach(reg.suggestName(_)) reg.io.q } def apply(d: Bool, clk: Clock, rst: Bool): Bool = apply(d, clk, rst, false, None) def apply(d: Bool, clk: Clock, rst: Bool, name: String): Bool = apply(d, clk, rst, false, Some(name)) // Create Vectors of Registers def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: Option[String] = None): UInt = { val w = updateData.getWidth max resetData.bitLength val reg = Module(new AsyncResetRegVec(w, resetData)) name.foreach(reg.suggestName(_)) reg.io.d := updateData reg.io.en := enable reg.io.q } def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: String): UInt = apply(updateData, resetData, enable, Some(name)) def apply(updateData: UInt, resetData: BigInt): UInt = apply(updateData, resetData, enable = true.B) def apply(updateData: UInt, resetData: BigInt, name: String): UInt = apply(updateData, resetData, enable = true.B, Some(name)) def apply(updateData: UInt, enable: Bool): UInt = apply(updateData, resetData=BigInt(0), enable) def apply(updateData: UInt, enable: Bool, name: String): UInt = apply(updateData, resetData = BigInt(0), enable, Some(name)) def apply(updateData: UInt): UInt = apply(updateData, resetData = BigInt(0), enable = true.B) def apply(updateData: UInt, name:String): UInt = apply(updateData, resetData = BigInt(0), enable = true.B, Some(name)) }	module IntSyncCrossingSource_n1x2( // @[Crossing.scala:41:9] input clock, // @[Crossing.scala:41:9] input reset, // @[Crossing.scala:41:9] input auto_in_0, // @[LazyModuleImp.scala:107:25] input auto_in_1, // @[LazyModuleImp.scala:107:25] output auto_out_sync_0, // @[LazyModuleImp.scala:107:25] output auto_out_sync_1 // @[LazyModuleImp.scala:107:25] ); wire [1:0] _reg_io_q; // @[AsyncResetReg.scala:86:21] AsyncResetRegVec_w2_i0 reg_0 ( // @[AsyncResetReg.scala:86:21] .clock (clock), .reset (reset), .io_d ({auto_in_1, auto_in_0}), // @[Crossing.scala:45:36] .io_q (_reg_io_q) ); // @[AsyncResetReg.scala:86:21] assign auto_out_sync_0 = _reg_io_q[0]; // @[AsyncResetReg.scala:86:21] assign auto_out_sync_1 = _reg_io_q[1]; // @[AsyncResetReg.scala:86:21] endmodule
Generate the Verilog code corresponding to the following Chisel files. File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File Nodes.scala: package constellation.channel import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Parameters, Field} import freechips.rocketchip.diplomacy._ case class EmptyParams() case class ChannelEdgeParams(cp: ChannelParams, p: Parameters) object ChannelImp extends SimpleNodeImp[EmptyParams, ChannelParams, ChannelEdgeParams, Channel] { def edge(pd: EmptyParams, pu: ChannelParams, p: Parameters, sourceInfo: SourceInfo) = { ChannelEdgeParams(pu, p) } def bundle(e: ChannelEdgeParams) = new Channel(e.cp)(e.p) def render(e: ChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) { RenderedEdge(colour = "ffffff", label = "X") } else { RenderedEdge(colour = "#0000ff", label = e.cp.payloadBits.toString) } override def monitor(bundle: Channel, edge: ChannelEdgeParams): Unit = { val monitor = Module(new NoCMonitor(edge.cp)(edge.p)) monitor.io.in := bundle } // TODO: Add nodepath stuff? override def mixO, override def mixI } case class ChannelSourceNode(val destId: Int)(implicit valName: ValName) extends SourceNode(ChannelImp)(Seq(EmptyParams())) case class ChannelDestNode(val destParams: ChannelParams)(implicit valName: ValName) extends SinkNode(ChannelImp)(Seq(destParams)) case class ChannelAdapterNode( slaveFn: ChannelParams => ChannelParams = { d => d })( implicit valName: ValName) extends AdapterNode(ChannelImp)((e: EmptyParams) => e, slaveFn) case class ChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(ChannelImp)() case class ChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(ChannelImp)() case class IngressChannelEdgeParams(cp: IngressChannelParams, p: Parameters) case class EgressChannelEdgeParams(cp: EgressChannelParams, p: Parameters) object IngressChannelImp extends SimpleNodeImp[EmptyParams, IngressChannelParams, IngressChannelEdgeParams, IngressChannel] { def edge(pd: EmptyParams, pu: IngressChannelParams, p: Parameters, sourceInfo: SourceInfo) = { IngressChannelEdgeParams(pu, p) } def bundle(e: IngressChannelEdgeParams) = new IngressChannel(e.cp)(e.p) def render(e: IngressChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) { RenderedEdge(colour = "ffffff", label = "X") } else { RenderedEdge(colour = "#00ff00", label = e.cp.payloadBits.toString) } } object EgressChannelImp extends SimpleNodeImp[EmptyParams, EgressChannelParams, EgressChannelEdgeParams, EgressChannel] { def edge(pd: EmptyParams, pu: EgressChannelParams, p: Parameters, sourceInfo: SourceInfo) = { EgressChannelEdgeParams(pu, p) } def bundle(e: EgressChannelEdgeParams) = new EgressChannel(e.cp)(e.p) def render(e: EgressChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) { RenderedEdge(colour = "ffffff", label = "X") } else { RenderedEdge(colour = "#ff0000", label = e.cp.payloadBits.toString) } } case class IngressChannelSourceNode(val destId: Int)(implicit valName: ValName) extends SourceNode(IngressChannelImp)(Seq(EmptyParams())) case class IngressChannelDestNode(val destParams: IngressChannelParams)(implicit valName: ValName) extends SinkNode(IngressChannelImp)(Seq(destParams)) case class EgressChannelSourceNode(val egressId: Int)(implicit valName: ValName) extends SourceNode(EgressChannelImp)(Seq(EmptyParams())) case class EgressChannelDestNode(val destParams: EgressChannelParams)(implicit valName: ValName) extends SinkNode(EgressChannelImp)(Seq(destParams)) case class IngressChannelAdapterNode( slaveFn: IngressChannelParams => IngressChannelParams = { d => d })( implicit valName: ValName) extends AdapterNode(IngressChannelImp)(m => m, slaveFn) case class EgressChannelAdapterNode( slaveFn: EgressChannelParams => EgressChannelParams = { d => d })( implicit valName: ValName) extends AdapterNode(EgressChannelImp)(m => m, slaveFn) case class IngressChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(IngressChannelImp)() case class EgressChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(EgressChannelImp)() case class IngressChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(IngressChannelImp)() case class EgressChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(EgressChannelImp)() File Router.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{RoutingRelation} import constellation.noc.{HasNoCParams} case class UserRouterParams( // Payload width. Must match payload width on all channels attached to this routing node payloadBits: Int = 64, // Combines SA and ST stages (removes pipeline register) combineSAST: Boolean = false, // Combines RC and VA stages (removes pipeline register) combineRCVA: Boolean = false, // Adds combinational path from SA to VA coupleSAVA: Boolean = false, vcAllocator: VCAllocatorParams => Parameters => VCAllocator = (vP) => (p) => new RotatingSingleVCAllocator(vP)(p) ) case class RouterParams( nodeId: Int, nIngress: Int, nEgress: Int, user: UserRouterParams ) trait HasRouterOutputParams { def outParams: Seq[ChannelParams] def egressParams: Seq[EgressChannelParams] def allOutParams = outParams ++ egressParams def nOutputs = outParams.size def nEgress = egressParams.size def nAllOutputs = allOutParams.size } trait HasRouterInputParams { def inParams: Seq[ChannelParams] def ingressParams: Seq[IngressChannelParams] def allInParams = inParams ++ ingressParams def nInputs = inParams.size def nIngress = ingressParams.size def nAllInputs = allInParams.size } trait HasRouterParams { def routerParams: RouterParams def nodeId = routerParams.nodeId def payloadBits = routerParams.user.payloadBits } class DebugBundle(val nIn: Int) extends Bundle { val va_stall = Vec(nIn, UInt()) val sa_stall = Vec(nIn, UInt()) } class Router( val routerParams: RouterParams, preDiplomaticInParams: Seq[ChannelParams], preDiplomaticIngressParams: Seq[IngressChannelParams], outDests: Seq[Int], egressIds: Seq[Int] )(implicit p: Parameters) extends LazyModule with HasNoCParams with HasRouterParams { val allPreDiplomaticInParams = preDiplomaticInParams ++ preDiplomaticIngressParams val destNodes = preDiplomaticInParams.map(u => ChannelDestNode(u)) val sourceNodes = outDests.map(u => ChannelSourceNode(u)) val ingressNodes = preDiplomaticIngressParams.map(u => IngressChannelDestNode(u)) val egressNodes = egressIds.map(u => EgressChannelSourceNode(u)) val debugNode = BundleBridgeSource(() => new DebugBundle(allPreDiplomaticInParams.size)) val ctrlNode = if (hasCtrl) Some(BundleBridgeSource(() => new RouterCtrlBundle)) else None def inParams = module.inParams def outParams = module.outParams def ingressParams = module.ingressParams def egressParams = module.egressParams lazy val module = new LazyModuleImp(this) with HasRouterInputParams with HasRouterOutputParams { val (io_in, edgesIn) = destNodes.map(_.in(0)).unzip val (io_out, edgesOut) = sourceNodes.map(_.out(0)).unzip val (io_ingress, edgesIngress) = ingressNodes.map(_.in(0)).unzip val (io_egress, edgesEgress) = egressNodes.map(_.out(0)).unzip val io_debug = debugNode.out(0)._1 val inParams = edgesIn.map(_.cp) val outParams = edgesOut.map(_.cp) val ingressParams = edgesIngress.map(_.cp) val egressParams = edgesEgress.map(_.cp) allOutParams.foreach(u => require(u.srcId == nodeId && u.payloadBits == routerParams.user.payloadBits)) allInParams.foreach(u => require(u.destId == nodeId && u.payloadBits == routerParams.user.payloadBits)) require(nIngress == routerParams.nIngress) require(nEgress == routerParams.nEgress) require(nAllInputs >= 1) require(nAllOutputs >= 1) require(nodeId < (1 << nodeIdBits)) val input_units = inParams.zipWithIndex.map { case (u,i) => Module(new InputUnit(u, outParams, egressParams, routerParams.user.combineRCVA, routerParams.user.combineSAST)) .suggestName(s"input_unit_${i}_from_${u.srcId}") } val ingress_units = ingressParams.zipWithIndex.map { case (u,i) => Module(new IngressUnit(i, u, outParams, egressParams, routerParams.user.combineRCVA, routerParams.user.combineSAST)) .suggestName(s"ingress_unit_${i+nInputs}_from_${u.ingressId}") } val all_input_units = input_units ++ ingress_units val output_units = outParams.zipWithIndex.map { case (u,i) => Module(new OutputUnit(inParams, ingressParams, u)) .suggestName(s"output_unit_${i}_to_${u.destId}")} val egress_units = egressParams.zipWithIndex.map { case (u,i) => Module(new EgressUnit(routerParams.user.coupleSAVA && all_input_units.size == 1, routerParams.user.combineSAST, inParams, ingressParams, u)) .suggestName(s"egress_unit_${i+nOutputs}_to_${u.egressId}")} val all_output_units = output_units ++ egress_units val switch = Module(new Switch(routerParams, inParams, outParams, ingressParams, egressParams)) val switch_allocator = Module(new SwitchAllocator(routerParams, inParams, outParams, ingressParams, egressParams)) val vc_allocator = Module(routerParams.user.vcAllocator( VCAllocatorParams(routerParams, inParams, outParams, ingressParams, egressParams) )(p)) val route_computer = Module(new RouteComputer(routerParams, inParams, outParams, ingressParams, egressParams)) val fires_count = WireInit(PopCount(vc_allocator.io.req.map(_.fire))) dontTouch(fires_count) (io_in zip input_units ).foreach { case (i,u) => u.io.in <> i } (io_ingress zip ingress_units).foreach { case (i,u) => u.io.in <> i.flit } (output_units zip io_out ).foreach { case (u,o) => o <> u.io.out } (egress_units zip io_egress).foreach { case (u,o) => o.flit <> u.io.out } (route_computer.io.req zip all_input_units).foreach { case (i,u) => i <> u.io.router_req } (all_input_units zip route_computer.io.resp).foreach { case (u,o) => u.io.router_resp <> o } (vc_allocator.io.req zip all_input_units).foreach { case (i,u) => i <> u.io.vcalloc_req } (all_input_units zip vc_allocator.io.resp).foreach { case (u,o) => u.io.vcalloc_resp <> o } (all_output_units zip vc_allocator.io.out_allocs).foreach { case (u,a) => u.io.allocs <> a } (vc_allocator.io.channel_status zip all_output_units).foreach { case (a,u) => a := u.io.channel_status } all_input_units.foreach(in => all_output_units.zipWithIndex.foreach { case (out,outIdx) => in.io.out_credit_available(outIdx) := out.io.credit_available }) (all_input_units zip switch_allocator.io.req).foreach { case (u,r) => r <> u.io.salloc_req } (all_output_units zip switch_allocator.io.credit_alloc).foreach { case (u,a) => u.io.credit_alloc := a } (switch.io.in zip all_input_units).foreach { case (i,u) => i <> u.io.out } (all_output_units zip switch.io.out).foreach { case (u,o) => u.io.in <> o } switch.io.sel := (if (routerParams.user.combineSAST) { switch_allocator.io.switch_sel } else { RegNext(switch_allocator.io.switch_sel) }) if (hasCtrl) { val io_ctrl = ctrlNode.get.out(0)._1 val ctrl = Module(new RouterControlUnit(routerParams, inParams, outParams, ingressParams, egressParams)) io_ctrl <> ctrl.io.ctrl (all_input_units zip ctrl.io.in_block ).foreach { case (l,r) => l.io.block := r } (all_input_units zip ctrl.io.in_fire ).foreach { case (l,r) => r := l.io.out.map(_.valid) } } else { input_units.foreach(_.io.block := false.B) ingress_units.foreach(_.io.block := false.B) } (io_debug.va_stall zip all_input_units.map(_.io.debug.va_stall)).map { case (l,r) => l := r } (io_debug.sa_stall zip all_input_units.map(_.io.debug.sa_stall)).map { case (l,r) => l := r } val debug_tsc = RegInit(0.U(64.W)) debug_tsc := debug_tsc + 1.U val debug_sample = RegInit(0.U(64.W)) debug_sample := debug_sample + 1.U val sample_rate = PlusArg("noc_util_sample_rate", width=20) when (debug_sample === sample_rate - 1.U) { debug_sample := 0.U } def sample(fire: Bool, s: String) = { val util_ctr = RegInit(0.U(64.W)) val fired = RegInit(false.B) util_ctr := util_ctr + fire fired := fired \|\| fire when (sample_rate =/= 0.U && debug_sample === sample_rate - 1.U && fired) { val fmtStr = s"nocsample %d $s %d\n" printf(fmtStr, debug_tsc, util_ctr); fired := fire } } destNodes.map(_.in(0)).foreach { case (in, edge) => in.flit.map { f => sample(f.fire, s"${edge.cp.srcId} $nodeId") } } ingressNodes.map(_.in(0)).foreach { case (in, edge) => sample(in.flit.fire, s"i${edge.cp.asInstanceOf[IngressChannelParams].ingressId} $nodeId") } egressNodes.map(_.out(0)).foreach { case (out, edge) => sample(out.flit.fire, s"$nodeId e${edge.cp.asInstanceOf[EgressChannelParams].egressId}") } } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } }	module Router_22( // @[Router.scala:89:25] input clock, // @[Router.scala:89:25] input reset, // @[Router.scala:89:25] output [4:0] auto_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25] output [4:0] auto_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25] output [4:0] auto_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25] output [4:0] auto_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_source_nodes_out_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [5:0] auto_source_nodes_out_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [5:0] auto_source_nodes_out_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [21:0] auto_source_nodes_out_1_credit_return, // @[LazyModuleImp.scala:107:25] input [21:0] auto_source_nodes_out_1_vc_free, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_source_nodes_out_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [5:0] auto_source_nodes_out_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [5:0] auto_source_nodes_out_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [21:0] auto_source_nodes_out_0_credit_return, // @[LazyModuleImp.scala:107:25] input [21:0] auto_source_nodes_out_0_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_dest_nodes_in_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [5:0] auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [5:0] auto_dest_nodes_in_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [21:0] auto_dest_nodes_in_1_credit_return, // @[LazyModuleImp.scala:107:25] output [21:0] auto_dest_nodes_in_1_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_dest_nodes_in_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [5:0] auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [5:0] auto_dest_nodes_in_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [21:0] auto_dest_nodes_in_0_credit_return, // @[LazyModuleImp.scala:107:25] output [21:0] auto_dest_nodes_in_0_vc_free // @[LazyModuleImp.scala:107:25] ); wire [19:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire _route_computer_io_resp_1_vc_sel_0_11; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_15; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_19; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_20; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_21; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_12; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_13; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_16; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_17; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_20; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_21; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_0_2; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_0_3; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_0_8; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_0_9; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_0_10; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_0_11; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_0_12; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_0_13; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_0_14; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_0_15; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_0_17; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_0_18; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_0_19; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_0_20; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_0_21; // @[Router.scala:136:32] wire _vc_allocator_io_req_1_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_0_ready; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_11; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_15; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_19; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_20; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_21; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_12; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_13; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_16; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_17; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_20; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_21; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_0_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_0_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_0_8; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_0_9; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_0_10; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_0_11; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_0_12; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_0_13; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_0_14; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_0_15; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_0_17; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_0_18; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_0_19; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_0_20; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_0_21; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_12_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_13_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_16_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_17_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_20_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_21_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_2_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_3_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_8_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_9_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_10_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_11_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_12_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_13_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_14_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_15_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_17_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_18_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_19_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_20_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_21_alloc; // @[Router.scala:133:30] wire _switch_allocator_io_req_1_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_0_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_12_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_13_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_16_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_17_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_20_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_21_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_2_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_3_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_8_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_9_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_10_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_11_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_12_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_13_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_14_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_15_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_17_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_18_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_19_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_20_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_21_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_0_0; // @[Router.scala:132:34] wire _switch_io_out_1_0_valid; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_1_0_bits_payload; // @[Router.scala:131:24] wire [3:0] _switch_io_out_1_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [5:0] _switch_io_out_1_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [2:0] _switch_io_out_1_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [5:0] _switch_io_out_1_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [2:0] _switch_io_out_1_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_1_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _switch_io_out_0_0_valid; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_0_0_bits_payload; // @[Router.scala:131:24] wire [3:0] _switch_io_out_0_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [5:0] _switch_io_out_0_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [2:0] _switch_io_out_0_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [5:0] _switch_io_out_0_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [2:0] _switch_io_out_0_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_0_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _output_unit_1_to_37_io_credit_available_12; // @[Router.scala:122:13] wire _output_unit_1_to_37_io_credit_available_13; // @[Router.scala:122:13] wire _output_unit_1_to_37_io_credit_available_16; // @[Router.scala:122:13] wire _output_unit_1_to_37_io_credit_available_17; // @[Router.scala:122:13] wire _output_unit_1_to_37_io_credit_available_20; // @[Router.scala:122:13] wire _output_unit_1_to_37_io_credit_available_21; // @[Router.scala:122:13] wire _output_unit_1_to_37_io_channel_status_12_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_37_io_channel_status_13_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_37_io_channel_status_16_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_37_io_channel_status_17_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_37_io_channel_status_20_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_37_io_channel_status_21_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_28_io_credit_available_2; // @[Router.scala:122:13] wire _output_unit_0_to_28_io_credit_available_3; // @[Router.scala:122:13] wire _output_unit_0_to_28_io_credit_available_8; // @[Router.scala:122:13] wire _output_unit_0_to_28_io_credit_available_9; // @[Router.scala:122:13] wire _output_unit_0_to_28_io_credit_available_10; // @[Router.scala:122:13] wire _output_unit_0_to_28_io_credit_available_11; // @[Router.scala:122:13] wire _output_unit_0_to_28_io_credit_available_12; // @[Router.scala:122:13] wire _output_unit_0_to_28_io_credit_available_13; // @[Router.scala:122:13] wire _output_unit_0_to_28_io_credit_available_14; // @[Router.scala:122:13] wire _output_unit_0_to_28_io_credit_available_15; // @[Router.scala:122:13] wire _output_unit_0_to_28_io_credit_available_17; // @[Router.scala:122:13] wire _output_unit_0_to_28_io_credit_available_18; // @[Router.scala:122:13] wire _output_unit_0_to_28_io_credit_available_19; // @[Router.scala:122:13] wire _output_unit_0_to_28_io_credit_available_20; // @[Router.scala:122:13] wire _output_unit_0_to_28_io_credit_available_21; // @[Router.scala:122:13] wire _output_unit_0_to_28_io_channel_status_2_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_28_io_channel_status_3_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_28_io_channel_status_8_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_28_io_channel_status_9_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_28_io_channel_status_10_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_28_io_channel_status_11_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_28_io_channel_status_12_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_28_io_channel_status_13_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_28_io_channel_status_14_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_28_io_channel_status_15_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_28_io_channel_status_17_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_28_io_channel_status_18_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_28_io_channel_status_19_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_28_io_channel_status_20_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_28_io_channel_status_21_occupied; // @[Router.scala:122:13] wire [4:0] _input_unit_1_from_37_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire [3:0] _input_unit_1_from_37_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [5:0] _input_unit_1_from_37_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_37_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [5:0] _input_unit_1_from_37_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_37_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_vcalloc_req_bits_vc_sel_0_11; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_vcalloc_req_bits_vc_sel_0_15; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_vcalloc_req_bits_vc_sel_0_19; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_vcalloc_req_bits_vc_sel_0_20; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_vcalloc_req_bits_vc_sel_0_21; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_salloc_req_0_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_salloc_req_0_bits_vc_sel_1_3; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_salloc_req_0_bits_vc_sel_1_8; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_salloc_req_0_bits_vc_sel_1_9; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_salloc_req_0_bits_vc_sel_1_10; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_salloc_req_0_bits_vc_sel_1_11; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_salloc_req_0_bits_vc_sel_1_12; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_salloc_req_0_bits_vc_sel_1_13; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_salloc_req_0_bits_vc_sel_1_14; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_salloc_req_0_bits_vc_sel_1_15; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_salloc_req_0_bits_vc_sel_1_16; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_salloc_req_0_bits_vc_sel_1_17; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_salloc_req_0_bits_vc_sel_1_18; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_salloc_req_0_bits_vc_sel_1_19; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_salloc_req_0_bits_vc_sel_1_20; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_salloc_req_0_bits_vc_sel_1_21; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_salloc_req_0_bits_vc_sel_0_8; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_salloc_req_0_bits_vc_sel_0_9; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_salloc_req_0_bits_vc_sel_0_10; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_salloc_req_0_bits_vc_sel_0_11; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_salloc_req_0_bits_vc_sel_0_12; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_salloc_req_0_bits_vc_sel_0_13; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_salloc_req_0_bits_vc_sel_0_14; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_salloc_req_0_bits_vc_sel_0_15; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_salloc_req_0_bits_vc_sel_0_16; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_salloc_req_0_bits_vc_sel_0_17; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_salloc_req_0_bits_vc_sel_0_18; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_salloc_req_0_bits_vc_sel_0_19; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_salloc_req_0_bits_vc_sel_0_20; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_salloc_req_0_bits_vc_sel_0_21; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [72:0] _input_unit_1_from_37_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [3:0] _input_unit_1_from_37_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [5:0] _input_unit_1_from_37_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_37_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [5:0] _input_unit_1_from_37_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_37_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_1_from_37_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [4:0] _input_unit_0_from_26_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_26_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [5:0] _input_unit_0_from_26_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_26_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [5:0] _input_unit_0_from_26_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_26_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_vcalloc_req_bits_vc_sel_1_12; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_vcalloc_req_bits_vc_sel_1_13; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_vcalloc_req_bits_vc_sel_1_16; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_vcalloc_req_bits_vc_sel_1_17; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_vcalloc_req_bits_vc_sel_1_20; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_vcalloc_req_bits_vc_sel_1_21; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_vcalloc_req_bits_vc_sel_0_8; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_vcalloc_req_bits_vc_sel_0_9; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_vcalloc_req_bits_vc_sel_0_10; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_vcalloc_req_bits_vc_sel_0_11; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_vcalloc_req_bits_vc_sel_0_12; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_vcalloc_req_bits_vc_sel_0_13; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_vcalloc_req_bits_vc_sel_0_14; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_vcalloc_req_bits_vc_sel_0_15; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_vcalloc_req_bits_vc_sel_0_17; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_vcalloc_req_bits_vc_sel_0_18; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_vcalloc_req_bits_vc_sel_0_19; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_vcalloc_req_bits_vc_sel_0_20; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_vcalloc_req_bits_vc_sel_0_21; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_salloc_req_0_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_salloc_req_0_bits_vc_sel_1_3; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_salloc_req_0_bits_vc_sel_1_8; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_salloc_req_0_bits_vc_sel_1_9; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_salloc_req_0_bits_vc_sel_1_10; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_salloc_req_0_bits_vc_sel_1_11; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_salloc_req_0_bits_vc_sel_1_12; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_salloc_req_0_bits_vc_sel_1_13; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_salloc_req_0_bits_vc_sel_1_14; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_salloc_req_0_bits_vc_sel_1_15; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_salloc_req_0_bits_vc_sel_1_16; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_salloc_req_0_bits_vc_sel_1_17; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_salloc_req_0_bits_vc_sel_1_18; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_salloc_req_0_bits_vc_sel_1_19; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_salloc_req_0_bits_vc_sel_1_20; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_salloc_req_0_bits_vc_sel_1_21; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_salloc_req_0_bits_vc_sel_0_8; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_salloc_req_0_bits_vc_sel_0_9; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_salloc_req_0_bits_vc_sel_0_10; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_salloc_req_0_bits_vc_sel_0_11; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_salloc_req_0_bits_vc_sel_0_12; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_salloc_req_0_bits_vc_sel_0_13; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_salloc_req_0_bits_vc_sel_0_14; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_salloc_req_0_bits_vc_sel_0_15; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_salloc_req_0_bits_vc_sel_0_16; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_salloc_req_0_bits_vc_sel_0_17; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_salloc_req_0_bits_vc_sel_0_18; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_salloc_req_0_bits_vc_sel_0_19; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_salloc_req_0_bits_vc_sel_0_20; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_salloc_req_0_bits_vc_sel_0_21; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [72:0] _input_unit_0_from_26_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_26_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [5:0] _input_unit_0_from_26_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_26_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [5:0] _input_unit_0_from_26_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_26_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_0_from_26_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [1:0] fires_count = {1'h0, _vc_allocator_io_req_0_ready & _input_unit_0_from_26_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_1_ready & _input_unit_1_from_37_io_vcalloc_req_valid}; // @[Decoupled.scala:51:35] reg REG_1_0_1_0; // @[Router.scala:178:14] reg REG_1_0_0_0; // @[Router.scala:178:14] reg REG_0_0_1_0; // @[Router.scala:178:14] reg REG_0_0_0_0; // @[Router.scala:178:14] reg [63:0] debug_tsc; // @[Router.scala:195:28] reg [63:0] debug_sample; // @[Router.scala:197:31] wire _GEN = debug_sample == {44'h0, _plusarg_reader_out - 20'h1}; // @[PlusArg.scala:80:11] reg [63:0] util_ctr; // @[Router.scala:203:29] reg fired; // @[Router.scala:204:26] wire _GEN_0 = (\|_plusarg_reader_out) & _GEN; // @[PlusArg.scala:80:11] wire _GEN_1 = _GEN_0 & fired; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_1; // @[Router.scala:203:29] reg fired_1; // @[Router.scala:204:26] wire _GEN_2 = _GEN_0 & fired_1; // @[Router.scala:204:26, :207:{33,71}]
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_49( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [11:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [25:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [11:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [11:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [25:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [11:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [25:0] _c_first_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_first_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_first_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_first_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_set_wo_ready_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_set_wo_ready_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_opcodes_set_interm_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_opcodes_set_interm_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_sizes_set_interm_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_sizes_set_interm_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_opcodes_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_opcodes_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_sizes_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_sizes_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_probe_ack_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_probe_ack_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_probe_ack_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_probe_ack_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _same_cycle_resp_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _same_cycle_resp_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _same_cycle_resp_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _same_cycle_resp_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _same_cycle_resp_WIRE_4_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _same_cycle_resp_WIRE_5_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_2_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_3_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_wo_ready_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_wo_ready_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_interm_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_interm_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_interm_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_interm_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_2_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_3_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_2_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_3_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_4_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_5_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [32769:0] _c_sizes_set_T_1 = 32770'h0; // @[Monitor.scala:768:52] wire [14:0] _c_opcodes_set_T = 15'h0; // @[Monitor.scala:767:79] wire [14:0] _c_sizes_set_T = 15'h0; // @[Monitor.scala:768:77] wire [32770:0] _c_opcodes_set_T_1 = 32771'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [4095:0] _c_set_wo_ready_T = 4096'h1; // @[OneHot.scala:58:35] wire [4095:0] _c_set_T = 4096'h1; // @[OneHot.scala:58:35] wire [8255:0] c_opcodes_set = 8256'h0; // @[Monitor.scala:740:34] wire [8255:0] c_sizes_set = 8256'h0; // @[Monitor.scala:741:34] wire [2063:0] c_set = 2064'h0; // @[Monitor.scala:738:34] wire [2063:0] c_set_wo_ready = 2064'h0; // @[Monitor.scala:739:34] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [11:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 12'h810; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [25:0] _is_aligned_T = {23'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 26'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [11:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [11:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 12'h810; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_665 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_665; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_665; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [11:0] source; // @[Monitor.scala:390:22] reg [25:0] address; // @[Monitor.scala:391:22] wire _T_733 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_733; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [11:0] source_1; // @[Monitor.scala:541:22] reg [2063:0] inflight; // @[Monitor.scala:614:27] reg [8255:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [8255:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [2063:0] a_set; // @[Monitor.scala:626:34] wire [2063:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [8255:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [8255:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [14:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [14:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [14:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [14:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [14:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [14:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [14:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [14:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [14:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [8255:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [8255:0] _a_opcode_lookup_T_6 = {8252'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [8255:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[8255:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [8255:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [8255:0] _a_size_lookup_T_6 = {8252'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [8255:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[8255:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [4095:0] _GEN_2 = 4096'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [4095:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [4095:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_665 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [14:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [14:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [14:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [32770:0] _a_opcodes_set_T_1 = {32767'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[8255:0] : 8256'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [32769:0] _a_sizes_set_T_1 = {32767'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[8255:0] : 8256'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [2063:0] d_clr; // @[Monitor.scala:664:34] wire [2063:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [8255:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [8255:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [4095:0] _GEN_5 = 4096'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [4095:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [4095:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [4095:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [4095:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_733 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire [32782:0] _d_opcodes_clr_T_5 = 32783'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[8255:0] : 8256'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [32782:0] _d_sizes_clr_T_5 = 32783'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[8255:0] : 8256'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [2063:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [2063:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [2063:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [8255:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [8255:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [8255:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [8255:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [8255:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [8255:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [2063:0] inflight_1; // @[Monitor.scala:726:35] wire [2063:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [8255:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [8255:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [8255:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [8255:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [8255:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [8255:0] _c_opcode_lookup_T_6 = {8252'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [8255:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[8255:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [8255:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [8255:0] _c_size_lookup_T_6 = {8252'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [8255:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[8255:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [2063:0] d_clr_1; // @[Monitor.scala:774:34] wire [2063:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [8255:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [8255:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_709 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_709 & d_release_ack_1 ? _d_clr_wo_ready_T_1[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire _T_691 = _T_733 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_691 ? _d_clr_T_1[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire [32782:0] _d_opcodes_clr_T_11 = 32783'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_691 ? _d_opcodes_clr_T_11[8255:0] : 8256'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [32782:0] _d_sizes_clr_T_11 = 32783'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_691 ? _d_sizes_clr_T_11[8255:0] : 8256'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 12'h0; // @[Monitor.scala:36:7, :795:113] wire [2063:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [2063:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [8255:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [8255:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [8255:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [8255:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /* Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_49( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [15:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [127:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [2:0] io_in_b_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_b_bits_size, // @[Monitor.scala:20:14] input [2:0] io_in_b_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input [15:0] io_in_b_bits_mask, // @[Monitor.scala:20:14] input [127:0] io_in_b_bits_data, // @[Monitor.scala:20:14] input io_in_b_bits_corrupt, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input [127:0] io_in_c_bits_data, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [127:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_ready, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [3:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [15:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [127:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7] wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_b_bits_opcode_0 = io_in_b_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_b_bits_size_0 = io_in_b_bits_size; // @[Monitor.scala:36:7] wire [2:0] io_in_b_bits_source_0 = io_in_b_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7] wire [15:0] io_in_b_bits_mask_0 = io_in_b_bits_mask; // @[Monitor.scala:36:7] wire [127:0] io_in_b_bits_data_0 = io_in_b_bits_data; // @[Monitor.scala:36:7] wire io_in_b_bits_corrupt_0 = io_in_b_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7] wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7] wire [127:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [127:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_e_ready_0 = io_in_e_ready; // @[Monitor.scala:36:7] wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7] wire [3:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire io_in_c_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_7 = 1'h0; // @[Parameters.scala:54:10] wire _legal_source_T = 1'h0; // @[Parameters.scala:54:10] wire _legal_source_T_7 = 1'h0; // @[Mux.scala:30:73] wire _source_ok_T_14 = 1'h0; // @[Parameters.scala:54:10] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [7:0] b_first_beats1 = 8'h0; // @[Edges.scala:221:14] wire [7:0] b_first_count = 8'h0; // @[Edges.scala:234:25] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_10 = 1'h1; // @[Parameters.scala:54:67] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire _legal_source_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _legal_source_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_16 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:54:67] wire sink_ok_1 = 1'h1; // @[Monitor.scala:367:31] wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire b_first_last = 1'h1; // @[Edges.scala:232:33] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [2:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _mask_sizeOH_T_3 = io_in_b_bits_size_0; // @[Misc.scala:202:34] wire [2:0] _uncommonBits_T_11 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _legal_source_uncommonBits_T = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_12 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T = io_in_b_bits_address_0; // @[Monitor.scala:36:7] wire [2:0] _source_ok_uncommonBits_T_2 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_13 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_14 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_15 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_16 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_17 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_70 = io_in_c_bits_address_0; // @[Monitor.scala:36:7] wire [2:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire _source_ok_T_6 = io_in_a_bits_source_0 == 3'h5; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire source_ok = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire [3:0] mask_sizeOH = {_mask_sizeOH_T_2[3:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_sub_0_1 = \|(io_in_a_bits_size_0[3:2]); // @[Misc.scala:206:21] wire mask_sub_sub_sub_size = mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_sub_bit = io_in_a_bits_address_0[3]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_1_2 = mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_nbit = ~mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_0_2 = mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_acc_T = mask_sub_sub_sub_size & mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_0_1 \| _mask_sub_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_size & mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_0_1 \| _mask_sub_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_1_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_2_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size & mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_2_1 = mask_sub_sub_sub_1_1 \| _mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_3_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size & mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_3_1 = mask_sub_sub_sub_1_1 \| _mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_4_2 = mask_sub_sub_2_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_4 = mask_sub_size & mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_4_1 = mask_sub_sub_2_1 \| _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_5_2 = mask_sub_sub_2_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_5 = mask_sub_size & mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_5_1 = mask_sub_sub_2_1 \| _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_6_2 = mask_sub_sub_3_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_6 = mask_sub_size & mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_6_1 = mask_sub_sub_3_1 \| _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_7_2 = mask_sub_sub_3_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_7 = mask_sub_size & mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_7_1 = mask_sub_sub_3_1 \| _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_eq_8 = mask_sub_4_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_size & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_8 = mask_sub_4_1 \| _mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_eq_9 = mask_sub_4_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_size & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_9 = mask_sub_4_1 \| _mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_eq_10 = mask_sub_5_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_size & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_10 = mask_sub_5_1 \| _mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_eq_11 = mask_sub_5_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_size & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_11 = mask_sub_5_1 \| _mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_eq_12 = mask_sub_6_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_size & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_12 = mask_sub_6_1 \| _mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_eq_13 = mask_sub_6_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_size & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_13 = mask_sub_6_1 \| _mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_eq_14 = mask_sub_7_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_size & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_14 = mask_sub_7_1 \| _mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_eq_15 = mask_sub_7_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_size & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_15 = mask_sub_7_1 \| _mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_lo = {mask_lo_lo_hi, mask_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_hi = {mask_lo_hi_hi, mask_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_lo_hi = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_lo = {mask_hi_lo_hi, mask_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_hi = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_hi = {mask_hi_hi_hi, mask_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [15:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [2:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_9 = _uncommonBits_T_9; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_10 = _uncommonBits_T_10; // @[Parameters.scala:52:{29,56}] wire [2:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_11 = source_ok_uncommonBits_1 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_12 = _source_ok_T_11; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire _source_ok_T_13 = io_in_d_bits_source_0 == 3'h5; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_1 = _source_ok_T_13; // @[Parameters.scala:1138:31] wire source_ok_1 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire [2:0] uncommonBits_11 = _uncommonBits_T_11; // @[Parameters.scala:52:{29,56}] wire _legal_source_T_6 = io_in_b_bits_source_0 == 3'h5; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46] wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_5 = {io_in_b_bits_address_0[31:13], io_in_b_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46] wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1 = _address_ok_T_9; // @[Parameters.scala:612:40] wire [13:0] _GEN_0 = io_in_b_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_10 = {io_in_b_bits_address_0[31:14], _GEN_0}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46] wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_2 = _address_ok_T_14; // @[Parameters.scala:612:40] wire [16:0] _GEN_1 = io_in_b_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_15 = {io_in_b_bits_address_0[31:17], _GEN_1}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46] wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_3 = _address_ok_T_19; // @[Parameters.scala:612:40] wire [20:0] _GEN_2 = io_in_b_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_20 = {io_in_b_bits_address_0[31:21], _GEN_2}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_21 = {1'h0, _address_ok_T_20}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_22 = _address_ok_T_21 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_23 = _address_ok_T_22; // @[Parameters.scala:137:46] wire _address_ok_T_24 = _address_ok_T_23 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_4 = _address_ok_T_24; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_25 = {io_in_b_bits_address_0[31:21], io_in_b_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_26 = {1'h0, _address_ok_T_25}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_27 = _address_ok_T_26 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_28 = _address_ok_T_27; // @[Parameters.scala:137:46] wire _address_ok_T_29 = _address_ok_T_28 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_5 = _address_ok_T_29; // @[Parameters.scala:612:40] wire [25:0] _GEN_3 = io_in_b_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_30 = {io_in_b_bits_address_0[31:26], _GEN_3}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_31 = {1'h0, _address_ok_T_30}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_32 = _address_ok_T_31 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_33 = _address_ok_T_32; // @[Parameters.scala:137:46] wire _address_ok_T_34 = _address_ok_T_33 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_6 = _address_ok_T_34; // @[Parameters.scala:612:40] wire [25:0] _GEN_4 = io_in_b_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_35 = {io_in_b_bits_address_0[31:26], _GEN_4}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_36 = {1'h0, _address_ok_T_35}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_37 = _address_ok_T_36 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_38 = _address_ok_T_37; // @[Parameters.scala:137:46] wire _address_ok_T_39 = _address_ok_T_38 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_7 = _address_ok_T_39; // @[Parameters.scala:612:40] wire [27:0] _GEN_5 = io_in_b_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_40 = {io_in_b_bits_address_0[31:28], _GEN_5}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_41 = {1'h0, _address_ok_T_40}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_42 = _address_ok_T_41 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_43 = _address_ok_T_42; // @[Parameters.scala:137:46] wire _address_ok_T_44 = _address_ok_T_43 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_8 = _address_ok_T_44; // @[Parameters.scala:612:40] wire [27:0] _GEN_6 = io_in_b_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_45 = {io_in_b_bits_address_0[31:28], _GEN_6}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_46 = {1'h0, _address_ok_T_45}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_47 = _address_ok_T_46 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_48 = _address_ok_T_47; // @[Parameters.scala:137:46] wire _address_ok_T_49 = _address_ok_T_48 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_9 = _address_ok_T_49; // @[Parameters.scala:612:40] wire [28:0] _GEN_7 = io_in_b_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_50 = {io_in_b_bits_address_0[31:29], _GEN_7}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_51 = {1'h0, _address_ok_T_50}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_52 = _address_ok_T_51 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_53 = _address_ok_T_52; // @[Parameters.scala:137:46] wire _address_ok_T_54 = _address_ok_T_53 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_10 = _address_ok_T_54; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_55 = io_in_b_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_56 = {1'h0, _address_ok_T_55}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_57 = _address_ok_T_56 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_58 = _address_ok_T_57; // @[Parameters.scala:137:46] wire _address_ok_T_59 = _address_ok_T_58 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_11 = _address_ok_T_59; // @[Parameters.scala:612:40] wire _address_ok_T_60 = _address_ok_WIRE_0 \| _address_ok_WIRE_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_61 = _address_ok_T_60 \| _address_ok_WIRE_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_62 = _address_ok_T_61 \| _address_ok_WIRE_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_63 = _address_ok_T_62 \| _address_ok_WIRE_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_64 = _address_ok_T_63 \| _address_ok_WIRE_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_65 = _address_ok_T_64 \| _address_ok_WIRE_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_66 = _address_ok_T_65 \| _address_ok_WIRE_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_67 = _address_ok_T_66 \| _address_ok_WIRE_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_68 = _address_ok_T_67 \| _address_ok_WIRE_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_69 = _address_ok_T_68 \| _address_ok_WIRE_10; // @[Parameters.scala:612:40, :636:64] wire address_ok = _address_ok_T_69 \| _address_ok_WIRE_11; // @[Parameters.scala:612:40, :636:64] wire [26:0] _GEN_8 = 27'hFFF << io_in_b_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_2; // @[package.scala:243:71] assign _is_aligned_mask_T_2 = _GEN_8; // @[package.scala:243:71] wire [26:0] _b_first_beats1_decode_T; // @[package.scala:243:71] assign _b_first_beats1_decode_T = _GEN_8; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_3 = _is_aligned_mask_T_2[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_1 = ~_is_aligned_mask_T_3; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_1 = {20'h0, io_in_b_bits_address_0[11:0] & is_aligned_mask_1}; // @[package.scala:243:46] wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount_1 = _mask_sizeOH_T_3[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_4 = 4'h1 << mask_sizeOH_shiftAmount_1; // @[OneHot.scala:64:49, :65:12] wire [3:0] _mask_sizeOH_T_5 = _mask_sizeOH_T_4; // @[OneHot.scala:65:{12,27}] wire [3:0] mask_sizeOH_1 = {_mask_sizeOH_T_5[3:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_sub_0_1_1 = \|(io_in_b_bits_size_0[3:2]); // @[Misc.scala:206:21] wire mask_sub_sub_sub_size_1 = mask_sizeOH_1[3]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_sub_bit_1 = io_in_b_bits_address_0[3]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_1_2_1 = mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_nbit_1 = ~mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_0_2_1 = mask_sub_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_acc_T_2 = mask_sub_sub_sub_size_1 & mask_sub_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_0_1_1 = mask_sub_sub_sub_sub_0_1_1 \| _mask_sub_sub_sub_acc_T_2; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_sub_acc_T_3 = mask_sub_sub_sub_size_1 & mask_sub_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_1_1_1 = mask_sub_sub_sub_sub_0_1_1 \| _mask_sub_sub_sub_acc_T_3; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_sub_size_1 = mask_sizeOH_1[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2_1 = mask_sub_sub_sub_0_2_1 & mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_4 = mask_sub_sub_size_1 & mask_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1_1 = mask_sub_sub_sub_0_1_1 \| _mask_sub_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_1_2_1 = mask_sub_sub_sub_0_2_1 & mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_5 = mask_sub_sub_size_1 & mask_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1_1 = mask_sub_sub_sub_0_1_1 \| _mask_sub_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_2_2_1 = mask_sub_sub_sub_1_2_1 & mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_6 = mask_sub_sub_size_1 & mask_sub_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_2_1_1 = mask_sub_sub_sub_1_1_1 \| _mask_sub_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_3_2_1 = mask_sub_sub_sub_1_2_1 & mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_7 = mask_sub_sub_size_1 & mask_sub_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_3_1_1 = mask_sub_sub_sub_1_1_1 \| _mask_sub_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_sub_size_1 = mask_sizeOH_1[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_8 = mask_sub_size_1 & mask_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1_1 = mask_sub_sub_0_1_1 \| _mask_sub_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_9 = mask_sub_size_1 & mask_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1_1 = mask_sub_sub_0_1_1 \| _mask_sub_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_10 = mask_sub_size_1 & mask_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1_1 = mask_sub_sub_1_1_1 \| _mask_sub_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_11 = mask_sub_size_1 & mask_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1_1 = mask_sub_sub_1_1_1 \| _mask_sub_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_sub_4_2_1 = mask_sub_sub_2_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_12 = mask_sub_size_1 & mask_sub_4_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_4_1_1 = mask_sub_sub_2_1_1 \| _mask_sub_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_sub_5_2_1 = mask_sub_sub_2_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_13 = mask_sub_size_1 & mask_sub_5_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_5_1_1 = mask_sub_sub_2_1_1 \| _mask_sub_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_sub_6_2_1 = mask_sub_sub_3_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_14 = mask_sub_size_1 & mask_sub_6_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_6_1_1 = mask_sub_sub_3_1_1 \| _mask_sub_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_sub_7_2_1 = mask_sub_sub_3_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_15 = mask_sub_size_1 & mask_sub_7_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_7_1_1 = mask_sub_sub_3_1_1 \| _mask_sub_acc_T_15; // @[Misc.scala:215:{29,38}] wire mask_size_1 = mask_sizeOH_1[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_eq_16 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_16 = mask_size_1 & mask_eq_16; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_16 = mask_sub_0_1_1 \| _mask_acc_T_16; // @[Misc.scala:215:{29,38}] wire mask_eq_17 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_17 = mask_size_1 & mask_eq_17; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_17 = mask_sub_0_1_1 \| _mask_acc_T_17; // @[Misc.scala:215:{29,38}] wire mask_eq_18 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_18 = mask_size_1 & mask_eq_18; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_18 = mask_sub_1_1_1 \| _mask_acc_T_18; // @[Misc.scala:215:{29,38}] wire mask_eq_19 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_19 = mask_size_1 & mask_eq_19; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_19 = mask_sub_1_1_1 \| _mask_acc_T_19; // @[Misc.scala:215:{29,38}] wire mask_eq_20 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_20 = mask_size_1 & mask_eq_20; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_20 = mask_sub_2_1_1 \| _mask_acc_T_20; // @[Misc.scala:215:{29,38}] wire mask_eq_21 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_21 = mask_size_1 & mask_eq_21; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_21 = mask_sub_2_1_1 \| _mask_acc_T_21; // @[Misc.scala:215:{29,38}] wire mask_eq_22 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_22 = mask_size_1 & mask_eq_22; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_22 = mask_sub_3_1_1 \| _mask_acc_T_22; // @[Misc.scala:215:{29,38}] wire mask_eq_23 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_23 = mask_size_1 & mask_eq_23; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_23 = mask_sub_3_1_1 \| _mask_acc_T_23; // @[Misc.scala:215:{29,38}] wire mask_eq_24 = mask_sub_4_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_24 = mask_size_1 & mask_eq_24; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_24 = mask_sub_4_1_1 \| _mask_acc_T_24; // @[Misc.scala:215:{29,38}] wire mask_eq_25 = mask_sub_4_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_25 = mask_size_1 & mask_eq_25; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_25 = mask_sub_4_1_1 \| _mask_acc_T_25; // @[Misc.scala:215:{29,38}] wire mask_eq_26 = mask_sub_5_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_26 = mask_size_1 & mask_eq_26; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_26 = mask_sub_5_1_1 \| _mask_acc_T_26; // @[Misc.scala:215:{29,38}] wire mask_eq_27 = mask_sub_5_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_27 = mask_size_1 & mask_eq_27; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_27 = mask_sub_5_1_1 \| _mask_acc_T_27; // @[Misc.scala:215:{29,38}] wire mask_eq_28 = mask_sub_6_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_28 = mask_size_1 & mask_eq_28; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_28 = mask_sub_6_1_1 \| _mask_acc_T_28; // @[Misc.scala:215:{29,38}] wire mask_eq_29 = mask_sub_6_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_29 = mask_size_1 & mask_eq_29; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_29 = mask_sub_6_1_1 \| _mask_acc_T_29; // @[Misc.scala:215:{29,38}] wire mask_eq_30 = mask_sub_7_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_30 = mask_size_1 & mask_eq_30; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_30 = mask_sub_7_1_1 \| _mask_acc_T_30; // @[Misc.scala:215:{29,38}] wire mask_eq_31 = mask_sub_7_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_31 = mask_size_1 & mask_eq_31; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_31 = mask_sub_7_1_1 \| _mask_acc_T_31; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo_lo_1 = {mask_acc_17, mask_acc_16}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_lo_hi_1 = {mask_acc_19, mask_acc_18}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_lo_1 = {mask_lo_lo_hi_1, mask_lo_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo_1 = {mask_acc_21, mask_acc_20}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_hi_1 = {mask_acc_23, mask_acc_22}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_hi_1 = {mask_lo_hi_hi_1, mask_lo_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] mask_lo_1 = {mask_lo_hi_1, mask_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo_1 = {mask_acc_25, mask_acc_24}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_lo_hi_1 = {mask_acc_27, mask_acc_26}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_lo_1 = {mask_hi_lo_hi_1, mask_hi_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo_1 = {mask_acc_29, mask_acc_28}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_hi_1 = {mask_acc_31, mask_acc_30}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_hi_1 = {mask_hi_hi_hi_1, mask_hi_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] mask_hi_1 = {mask_hi_hi_1, mask_hi_lo_1}; // @[Misc.scala:222:10] wire [15:0] mask_1 = {mask_hi_1, mask_lo_1}; // @[Misc.scala:222:10] wire [2:0] legal_source_uncommonBits = _legal_source_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _legal_source_T_4 = legal_source_uncommonBits < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _legal_source_T_5 = _legal_source_T_4; // @[Parameters.scala:56:48, :57:20] wire _legal_source_WIRE_0 = _legal_source_T_5; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_1 = _legal_source_T_6; // @[Parameters.scala:1138:31] wire [2:0] _legal_source_T_8 = _legal_source_WIRE_1 ? 3'h5 : 3'h0; // @[Mux.scala:30:73] wire [2:0] _legal_source_T_9 = _legal_source_T_8; // @[Mux.scala:30:73] wire [2:0] _legal_source_WIRE_1_0 = _legal_source_T_9; // @[Mux.scala:30:73] wire legal_source = _legal_source_WIRE_1_0 == io_in_b_bits_source_0; // @[Mux.scala:30:73] wire [2:0] uncommonBits_12 = _uncommonBits_T_12; // @[Parameters.scala:52:{29,56}] wire [2:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_18 = source_ok_uncommonBits_2 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_19 = _source_ok_T_18; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_2_0 = _source_ok_T_19; // @[Parameters.scala:1138:31] wire _source_ok_T_20 = io_in_c_bits_source_0 == 3'h5; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_1 = _source_ok_T_20; // @[Parameters.scala:1138:31] wire source_ok_2 = _source_ok_WIRE_2_0 \| _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN_9 = 27'hFFF << io_in_c_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_4; // @[package.scala:243:71] assign _is_aligned_mask_T_4 = _GEN_9; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T; // @[package.scala:243:71] assign _c_first_beats1_decode_T = _GEN_9; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71] assign _c_first_beats1_decode_T_3 = _GEN_9; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_2 = {20'h0, io_in_c_bits_address_0[11:0] & is_aligned_mask_2}; // @[package.scala:243:46] wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}] wire [32:0] _address_ok_T_71 = {1'h0, _address_ok_T_70}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_72 = _address_ok_T_71 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_73 = _address_ok_T_72; // @[Parameters.scala:137:46] wire _address_ok_T_74 = _address_ok_T_73 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_0 = _address_ok_T_74; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_75 = {io_in_c_bits_address_0[31:13], io_in_c_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_76 = {1'h0, _address_ok_T_75}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_77 = _address_ok_T_76 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_78 = _address_ok_T_77; // @[Parameters.scala:137:46] wire _address_ok_T_79 = _address_ok_T_78 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_1 = _address_ok_T_79; // @[Parameters.scala:612:40] wire [13:0] _GEN_10 = io_in_c_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_80 = {io_in_c_bits_address_0[31:14], _GEN_10}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_81 = {1'h0, _address_ok_T_80}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_82 = _address_ok_T_81 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_83 = _address_ok_T_82; // @[Parameters.scala:137:46] wire _address_ok_T_84 = _address_ok_T_83 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_2 = _address_ok_T_84; // @[Parameters.scala:612:40] wire [16:0] _GEN_11 = io_in_c_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_85 = {io_in_c_bits_address_0[31:17], _GEN_11}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_86 = {1'h0, _address_ok_T_85}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_87 = _address_ok_T_86 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_88 = _address_ok_T_87; // @[Parameters.scala:137:46] wire _address_ok_T_89 = _address_ok_T_88 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_3 = _address_ok_T_89; // @[Parameters.scala:612:40] wire [20:0] _GEN_12 = io_in_c_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_90 = {io_in_c_bits_address_0[31:21], _GEN_12}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_91 = {1'h0, _address_ok_T_90}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_92 = _address_ok_T_91 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_93 = _address_ok_T_92; // @[Parameters.scala:137:46] wire _address_ok_T_94 = _address_ok_T_93 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_4 = _address_ok_T_94; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_95 = {io_in_c_bits_address_0[31:21], io_in_c_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_96 = {1'h0, _address_ok_T_95}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_97 = _address_ok_T_96 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_98 = _address_ok_T_97; // @[Parameters.scala:137:46] wire _address_ok_T_99 = _address_ok_T_98 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_5 = _address_ok_T_99; // @[Parameters.scala:612:40] wire [25:0] _GEN_13 = io_in_c_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_100 = {io_in_c_bits_address_0[31:26], _GEN_13}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_101 = {1'h0, _address_ok_T_100}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_102 = _address_ok_T_101 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_103 = _address_ok_T_102; // @[Parameters.scala:137:46] wire _address_ok_T_104 = _address_ok_T_103 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_6 = _address_ok_T_104; // @[Parameters.scala:612:40] wire [25:0] _GEN_14 = io_in_c_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_105 = {io_in_c_bits_address_0[31:26], _GEN_14}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_106 = {1'h0, _address_ok_T_105}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_107 = _address_ok_T_106 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_108 = _address_ok_T_107; // @[Parameters.scala:137:46] wire _address_ok_T_109 = _address_ok_T_108 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_7 = _address_ok_T_109; // @[Parameters.scala:612:40] wire [27:0] _GEN_15 = io_in_c_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_110 = {io_in_c_bits_address_0[31:28], _GEN_15}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_111 = {1'h0, _address_ok_T_110}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_112 = _address_ok_T_111 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_113 = _address_ok_T_112; // @[Parameters.scala:137:46] wire _address_ok_T_114 = _address_ok_T_113 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_8 = _address_ok_T_114; // @[Parameters.scala:612:40] wire [27:0] _GEN_16 = io_in_c_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_115 = {io_in_c_bits_address_0[31:28], _GEN_16}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_116 = {1'h0, _address_ok_T_115}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_117 = _address_ok_T_116 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_118 = _address_ok_T_117; // @[Parameters.scala:137:46] wire _address_ok_T_119 = _address_ok_T_118 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_9 = _address_ok_T_119; // @[Parameters.scala:612:40] wire [28:0] _GEN_17 = io_in_c_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_120 = {io_in_c_bits_address_0[31:29], _GEN_17}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_121 = {1'h0, _address_ok_T_120}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_122 = _address_ok_T_121 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_123 = _address_ok_T_122; // @[Parameters.scala:137:46] wire _address_ok_T_124 = _address_ok_T_123 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_10 = _address_ok_T_124; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_125 = io_in_c_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_126 = {1'h0, _address_ok_T_125}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_127 = _address_ok_T_126 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_128 = _address_ok_T_127; // @[Parameters.scala:137:46] wire _address_ok_T_129 = _address_ok_T_128 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_11 = _address_ok_T_129; // @[Parameters.scala:612:40] wire _address_ok_T_130 = _address_ok_WIRE_1_0 \| _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_131 = _address_ok_T_130 \| _address_ok_WIRE_1_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_132 = _address_ok_T_131 \| _address_ok_WIRE_1_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_133 = _address_ok_T_132 \| _address_ok_WIRE_1_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_134 = _address_ok_T_133 \| _address_ok_WIRE_1_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_135 = _address_ok_T_134 \| _address_ok_WIRE_1_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_136 = _address_ok_T_135 \| _address_ok_WIRE_1_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_137 = _address_ok_T_136 \| _address_ok_WIRE_1_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_138 = _address_ok_T_137 \| _address_ok_WIRE_1_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_139 = _address_ok_T_138 \| _address_ok_WIRE_1_10; // @[Parameters.scala:612:40, :636:64] wire address_ok_1 = _address_ok_T_139 \| _address_ok_WIRE_1_11; // @[Parameters.scala:612:40, :636:64] wire [2:0] uncommonBits_13 = _uncommonBits_T_13; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_14 = _uncommonBits_T_14; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_15 = _uncommonBits_T_15; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_16 = _uncommonBits_T_16; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_17 = _uncommonBits_T_17; // @[Parameters.scala:52:{29,56}] wire _T_2489 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_2489; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_2489; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [7:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [7:0] a_first_counter; // @[Edges.scala:229:27] wire [8:0] _a_first_counter1_T = {1'h0, a_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] a_first_counter1 = _a_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [7:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [2:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_2563 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_2563; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_2563; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_2563; // @[Decoupled.scala:51:35] wire _d_first_T_3; // @[Decoupled.scala:51:35] assign _d_first_T_3 = _T_2563; // @[Decoupled.scala:51:35] wire [26:0] _GEN_18 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71] assign _d_first_beats1_decode_T_9 = _GEN_18; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [7:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T = {1'h0, d_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1 = _d_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [2:0] source_1; // @[Monitor.scala:541:22] reg [3:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35] wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35] wire [11:0] _b_first_beats1_decode_T_1 = _b_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _b_first_beats1_decode_T_2 = ~_b_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] b_first_beats1_decode = _b_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire _b_first_beats1_opdata_T = io_in_b_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire b_first_beats1_opdata = ~_b_first_beats1_opdata_T; // @[Edges.scala:97:{28,37}] reg [7:0] b_first_counter; // @[Edges.scala:229:27] wire [8:0] _b_first_counter1_T = {1'h0, b_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] b_first_counter1 = _b_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire b_first = b_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _b_first_last_T = b_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire [7:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] _b_first_counter_T = b_first ? 8'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_2; // @[Monitor.scala:410:22] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [3:0] size_2; // @[Monitor.scala:412:22] reg [2:0] source_2; // @[Monitor.scala:413:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _T_2560 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35] wire _c_first_T; // @[Decoupled.scala:51:35] assign _c_first_T = _T_2560; // @[Decoupled.scala:51:35] wire _c_first_T_1; // @[Decoupled.scala:51:35] assign _c_first_T_1 = _T_2560; // @[Decoupled.scala:51:35] wire [11:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [7:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 8'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [7:0] c_first_counter; // @[Edges.scala:229:27] wire [8:0] _c_first_counter1_T = {1'h0, c_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] c_first_counter1 = _c_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire c_first = c_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T = c_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_1 = c_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last = _c_first_last_T \| _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35] wire [7:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [3:0] size_3; // @[Monitor.scala:517:22] reg [2:0] source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [5:0] inflight; // @[Monitor.scala:614:27] reg [23:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [47:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [7:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [7:0] a_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] a_first_counter1_1 = _a_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [7:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_1 = _d_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] a_set; // @[Monitor.scala:626:34] wire [5:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [23:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [47:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [5:0] _GEN_19 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [5:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_19; // @[Monitor.scala:637:69] wire [5:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_19; // @[Monitor.scala:637:69, :680:101] wire [5:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_19; // @[Monitor.scala:637:69, :749:69] wire [5:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_19; // @[Monitor.scala:637:69, :790:101] wire [23:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [23:0] _a_opcode_lookup_T_6 = {20'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [23:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[23:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [5:0] _GEN_20 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [5:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_20; // @[Monitor.scala:641:65] wire [5:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_20; // @[Monitor.scala:641:65, :681:99] wire [5:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_20; // @[Monitor.scala:641:65, :750:67] wire [5:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_20; // @[Monitor.scala:641:65, :791:99] wire [47:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [47:0] _a_size_lookup_T_6 = {40'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [47:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[47:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [7:0] _GEN_21 = 8'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [7:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_21; // @[OneHot.scala:58:35] wire [7:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_21; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[5:0] : 6'h0; // @[OneHot.scala:58:35] wire _T_2415 = _T_2489 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_2415 ? _a_set_T[5:0] : 6'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_2415 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_2415 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [5:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [66:0] _a_opcodes_set_T_1 = {63'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_2415 ? _a_opcodes_set_T_1[23:0] : 24'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [5:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [67:0] _a_sizes_set_T_1 = {63'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_2415 ? _a_sizes_set_T_1[47:0] : 48'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [5:0] d_clr; // @[Monitor.scala:664:34] wire [5:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [23:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [47:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_22 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_22; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_22; // @[Monitor.scala:673:46, :783:46] wire _T_2461 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [7:0] _GEN_23 = 8'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [7:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_23; // @[OneHot.scala:58:35] wire [7:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_23; // @[OneHot.scala:58:35] wire [7:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_23; // @[OneHot.scala:58:35] wire [7:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_23; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_2461 & ~d_release_ack ? _d_clr_wo_ready_T[5:0] : 6'h0; // @[OneHot.scala:58:35] wire _T_2430 = _T_2563 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_2430 ? _d_clr_T[5:0] : 6'h0; // @[OneHot.scala:58:35] wire [78:0] _d_opcodes_clr_T_5 = 79'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_2430 ? _d_opcodes_clr_T_5[23:0] : 24'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [78:0] _d_sizes_clr_T_5 = 79'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_2430 ? _d_sizes_clr_T_5[47:0] : 48'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [5:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [5:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [5:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [23:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [23:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [23:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [47:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [47:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [47:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [5:0] inflight_1; // @[Monitor.scala:726:35] reg [23:0] inflight_opcodes_1; // @[Monitor.scala:727:35] reg [47:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [11:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire [7:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 8'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [7:0] c_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] c_first_counter1_1 = _c_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire c_first_1 = c_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T_2 = c_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_3 = c_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last_1 = _c_first_last_T_2 \| _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35] wire [7:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_2; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_2 = _d_first_counter1_T_2[7:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] c_set; // @[Monitor.scala:738:34] wire [5:0] c_set_wo_ready; // @[Monitor.scala:739:34] wire [23:0] c_opcodes_set; // @[Monitor.scala:740:34] wire [47:0] c_sizes_set; // @[Monitor.scala:741:34] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [23:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [23:0] _c_opcode_lookup_T_6 = {20'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [23:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[23:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [47:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [47:0] _c_size_lookup_T_6 = {40'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [47:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[47:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40] wire [4:0] c_sizes_set_interm; // @[Monitor.scala:755:40] wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44] wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7] wire [7:0] _GEN_24 = 8'h1 << io_in_c_bits_source_0; // @[OneHot.scala:58:35] wire [7:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35] assign _c_set_wo_ready_T = _GEN_24; // @[OneHot.scala:58:35] wire [7:0] _c_set_T; // @[OneHot.scala:58:35] assign _c_set_T = _GEN_24; // @[OneHot.scala:58:35] assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T[5:0] : 6'h0; // @[OneHot.scala:58:35] wire _T_2502 = _T_2560 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35] assign c_set = _T_2502 ? _c_set_T[5:0] : 6'h0; // @[OneHot.scala:58:35] wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53] wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}] assign c_opcodes_set_interm = _T_2502 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}] wire [4:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51] wire [4:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:766:{51,59}] assign c_sizes_set_interm = _T_2502 ? _c_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}] wire [5:0] _c_opcodes_set_T = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79] wire [66:0] _c_opcodes_set_T_1 = {63'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:659:54, :754:40, :767:{54,79}] assign c_opcodes_set = _T_2502 ? _c_opcodes_set_T_1[23:0] : 24'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}] wire [5:0] _c_sizes_set_T = {io_in_c_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :768:77] wire [67:0] _c_sizes_set_T_1 = {63'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:659:54, :755:40, :768:{52,77}] assign c_sizes_set = _T_2502 ? _c_sizes_set_T_1[47:0] : 48'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}] wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47] wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95] wire c_probe_ack = _c_probe_ack_T \| _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}] wire [5:0] d_clr_1; // @[Monitor.scala:774:34] wire [5:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [23:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [47:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_2533 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_2533 & d_release_ack_1 ? _d_clr_wo_ready_T_1[5:0] : 6'h0; // @[OneHot.scala:58:35] wire _T_2515 = _T_2563 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_2515 ? _d_clr_T_1[5:0] : 6'h0; // @[OneHot.scala:58:35] wire [78:0] _d_opcodes_clr_T_11 = 79'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_2515 ? _d_opcodes_clr_T_11[23:0] : 24'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [78:0] _d_sizes_clr_T_11 = 79'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_2515 ? _d_sizes_clr_T_11[47:0] : 48'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}] wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}] wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}] wire [5:0] _inflight_T_3 = inflight_1 \| c_set; // @[Monitor.scala:726:35, :738:34, :814:35] wire [5:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [5:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [23:0] _inflight_opcodes_T_3 = inflight_opcodes_1 \| c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43] wire [23:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [23:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [47:0] _inflight_sizes_T_3 = inflight_sizes_1 \| c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41] wire [47:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [47:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26] wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26] reg [15:0] inflight_2; // @[Monitor.scala:828:27] wire [11:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_3; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_3 = _d_first_counter1_T_3[7:0]; // @[Edges.scala:230:28] wire d_first_3 = d_first_counter_3 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_6 = d_first_counter_3 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_7 = d_first_beats1_3 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_3 = _d_first_last_T_6 \| _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}] wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [15:0] d_set; // @[Monitor.scala:833:25] wire _T_2569 = _T_2563 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35] wire [15:0] _GEN_25 = {12'h0, io_in_d_bits_sink_0}; // @[OneHot.scala:58:35] wire [15:0] _d_set_T = 16'h1 << _GEN_25; // @[OneHot.scala:58:35] assign d_set = _T_2569 ? _d_set_T : 16'h0; // @[OneHot.scala:58:35] wire [15:0] e_clr; // @[Monitor.scala:839:25] wire _T_2578 = io_in_e_ready_0 & io_in_e_valid_0; // @[Decoupled.scala:51:35] wire [15:0] _GEN_26 = {12'h0, io_in_e_bits_sink_0}; // @[OneHot.scala:58:35] wire [15:0] _e_clr_T = 16'h1 << _GEN_26; // @[OneHot.scala:58:35] assign e_clr = _T_2578 ? _e_clr_T : 16'h0; // @[OneHot.scala:58:35]
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /* Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_55( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [7:0] source; // @[Monitor.scala:390:22] reg [27:0] address; // @[Monitor.scala:391:22] reg d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [7:0] source_1; // @[Monitor.scala:541:22] reg [159:0] inflight; // @[Monitor.scala:614:27] reg [639:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [639:0] inflight_sizes; // @[Monitor.scala:618:33] reg a_first_counter_1; // @[Edges.scala:229:27] reg d_first_counter_1; // @[Edges.scala:229:27] wire [255:0] _GEN = {248'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_0 = a_first_done & ~a_first_counter_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_1 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [255:0] _GEN_2 = {248'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [159:0] inflight_1; // @[Monitor.scala:726:35] reg [639:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg d_first_counter_2; // @[Edges.scala:229:27] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_20( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [13:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [13:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire io_in_d_bits_denied = 1'h1; // @[Monitor.scala:36:7] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_81 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_83 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_87 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_89 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_93 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_95 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_99 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_101 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data = 64'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [13:0] _c_first_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_first_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_first_WIRE_2_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_first_WIRE_3_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_set_wo_ready_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_set_wo_ready_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_set_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_set_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_opcodes_set_interm_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_opcodes_set_interm_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_sizes_set_interm_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_sizes_set_interm_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_opcodes_set_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_opcodes_set_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_sizes_set_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_sizes_set_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_probe_ack_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_probe_ack_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_probe_ack_WIRE_2_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_probe_ack_WIRE_3_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _same_cycle_resp_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _same_cycle_resp_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _same_cycle_resp_WIRE_2_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _same_cycle_resp_WIRE_3_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _same_cycle_resp_WIRE_4_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _same_cycle_resp_WIRE_5_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1027:0] _c_sizes_set_T_1 = 1028'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [519:0] c_sizes_set = 520'h0; // @[Monitor.scala:741:34] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h3C; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 7'h3D; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire _source_ok_T_27 = io_in_a_bits_source_0 == 7'h3E; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31] wire _source_ok_T_28 = io_in_a_bits_source_0 == 7'h38; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_28; // @[Parameters.scala:1138:31] wire _source_ok_T_29 = io_in_a_bits_source_0 == 7'h39; // @[Monitor.scala:36:7] wire _source_ok_WIRE_9 = _source_ok_T_29; // @[Parameters.scala:1138:31] wire _source_ok_T_30 = io_in_a_bits_source_0 == 7'h3A; // @[Monitor.scala:36:7] wire _source_ok_WIRE_10 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire _source_ok_T_31 = io_in_a_bits_source_0 == 7'h34; // @[Monitor.scala:36:7] wire _source_ok_WIRE_11 = _source_ok_T_31; // @[Parameters.scala:1138:31] wire _source_ok_T_32 = io_in_a_bits_source_0 == 7'h35; // @[Monitor.scala:36:7] wire _source_ok_WIRE_12 = _source_ok_T_32; // @[Parameters.scala:1138:31] wire _source_ok_T_33 = io_in_a_bits_source_0 == 7'h36; // @[Monitor.scala:36:7] wire _source_ok_WIRE_13 = _source_ok_T_33; // @[Parameters.scala:1138:31] wire _source_ok_T_34 = io_in_a_bits_source_0 == 7'h30; // @[Monitor.scala:36:7] wire _source_ok_WIRE_14 = _source_ok_T_34; // @[Parameters.scala:1138:31] wire _source_ok_T_35 = io_in_a_bits_source_0 == 7'h31; // @[Monitor.scala:36:7] wire _source_ok_WIRE_15 = _source_ok_T_35; // @[Parameters.scala:1138:31] wire _source_ok_T_36 = io_in_a_bits_source_0 == 7'h32; // @[Monitor.scala:36:7] wire _source_ok_WIRE_16 = _source_ok_T_36; // @[Parameters.scala:1138:31] wire _source_ok_T_37 = io_in_a_bits_source_0 == 7'h2C; // @[Monitor.scala:36:7] wire _source_ok_WIRE_17 = _source_ok_T_37; // @[Parameters.scala:1138:31] wire _source_ok_T_38 = io_in_a_bits_source_0 == 7'h2D; // @[Monitor.scala:36:7] wire _source_ok_WIRE_18 = _source_ok_T_38; // @[Parameters.scala:1138:31] wire _source_ok_T_39 = io_in_a_bits_source_0 == 7'h2E; // @[Monitor.scala:36:7] wire _source_ok_WIRE_19 = _source_ok_T_39; // @[Parameters.scala:1138:31] wire _source_ok_T_40 = io_in_a_bits_source_0 == 7'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_20 = _source_ok_T_40; // @[Parameters.scala:1138:31] wire _source_ok_T_41 = io_in_a_bits_source_0 == 7'h29; // @[Monitor.scala:36:7] wire _source_ok_WIRE_21 = _source_ok_T_41; // @[Parameters.scala:1138:31] wire _source_ok_T_42 = io_in_a_bits_source_0 == 7'h2A; // @[Monitor.scala:36:7] wire _source_ok_WIRE_22 = _source_ok_T_42; // @[Parameters.scala:1138:31] wire _source_ok_T_43 = io_in_a_bits_source_0 == 7'h24; // @[Monitor.scala:36:7] wire _source_ok_WIRE_23 = _source_ok_T_43; // @[Parameters.scala:1138:31] wire _source_ok_T_44 = io_in_a_bits_source_0 == 7'h25; // @[Monitor.scala:36:7] wire _source_ok_WIRE_24 = _source_ok_T_44; // @[Parameters.scala:1138:31] wire _source_ok_T_45 = io_in_a_bits_source_0 == 7'h26; // @[Monitor.scala:36:7] wire _source_ok_WIRE_25 = _source_ok_T_45; // @[Parameters.scala:1138:31] wire _source_ok_T_46 = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_26 = _source_ok_T_46; // @[Parameters.scala:1138:31] wire _source_ok_T_47 = io_in_a_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_27 = _source_ok_T_47; // @[Parameters.scala:1138:31] wire _source_ok_T_48 = io_in_a_bits_source_0 == 7'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_28 = _source_ok_T_48; // @[Parameters.scala:1138:31] wire _source_ok_T_49 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_29 = _source_ok_T_49; // @[Parameters.scala:1138:31] wire _source_ok_T_50 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_51 = _source_ok_T_50 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_52 = _source_ok_T_51 \| _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_53 = _source_ok_T_52 \| _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_54 = _source_ok_T_53 \| _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_55 = _source_ok_T_54 \| _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_56 = _source_ok_T_55 \| _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_57 = _source_ok_T_56 \| _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_58 = _source_ok_T_57 \| _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_59 = _source_ok_T_58 \| _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_60 = _source_ok_T_59 \| _source_ok_WIRE_11; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_61 = _source_ok_T_60 \| _source_ok_WIRE_12; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_62 = _source_ok_T_61 \| _source_ok_WIRE_13; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_63 = _source_ok_T_62 \| _source_ok_WIRE_14; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_64 = _source_ok_T_63 \| _source_ok_WIRE_15; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_65 = _source_ok_T_64 \| _source_ok_WIRE_16; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_66 = _source_ok_T_65 \| _source_ok_WIRE_17; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_67 = _source_ok_T_66 \| _source_ok_WIRE_18; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_68 = _source_ok_T_67 \| _source_ok_WIRE_19; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_69 = _source_ok_T_68 \| _source_ok_WIRE_20; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_70 = _source_ok_T_69 \| _source_ok_WIRE_21; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_71 = _source_ok_T_70 \| _source_ok_WIRE_22; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_72 = _source_ok_T_71 \| _source_ok_WIRE_23; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_73 = _source_ok_T_72 \| _source_ok_WIRE_24; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_74 = _source_ok_T_73 \| _source_ok_WIRE_25; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_75 = _source_ok_T_74 \| _source_ok_WIRE_26; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_76 = _source_ok_T_75 \| _source_ok_WIRE_27; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_77 = _source_ok_T_76 \| _source_ok_WIRE_28; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_77 \| _source_ok_WIRE_29; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [13:0] _is_aligned_T = {2'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 14'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_78 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_78; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_79 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_85 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_91 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_97 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_80 = _source_ok_T_79 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_82 = _source_ok_T_80; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_84 = _source_ok_T_82; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_84; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_86 = _source_ok_T_85 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_88 = _source_ok_T_86; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_90 = _source_ok_T_88; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_90; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_92 = _source_ok_T_91 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_94 = _source_ok_T_92; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_96 = _source_ok_T_94; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_96; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_98 = _source_ok_T_97 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_100 = _source_ok_T_98; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_102 = _source_ok_T_100; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_102; // @[Parameters.scala:1138:31] wire _source_ok_T_103 = io_in_d_bits_source_0 == 7'h3C; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_103; // @[Parameters.scala:1138:31] wire _source_ok_T_104 = io_in_d_bits_source_0 == 7'h3D; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_104; // @[Parameters.scala:1138:31] wire _source_ok_T_105 = io_in_d_bits_source_0 == 7'h3E; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_105; // @[Parameters.scala:1138:31] wire _source_ok_T_106 = io_in_d_bits_source_0 == 7'h38; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_106; // @[Parameters.scala:1138:31] wire _source_ok_T_107 = io_in_d_bits_source_0 == 7'h39; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_9 = _source_ok_T_107; // @[Parameters.scala:1138:31] wire _source_ok_T_108 = io_in_d_bits_source_0 == 7'h3A; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_10 = _source_ok_T_108; // @[Parameters.scala:1138:31] wire _source_ok_T_109 = io_in_d_bits_source_0 == 7'h34; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_11 = _source_ok_T_109; // @[Parameters.scala:1138:31] wire _source_ok_T_110 = io_in_d_bits_source_0 == 7'h35; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_12 = _source_ok_T_110; // @[Parameters.scala:1138:31] wire _source_ok_T_111 = io_in_d_bits_source_0 == 7'h36; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_13 = _source_ok_T_111; // @[Parameters.scala:1138:31] wire _source_ok_T_112 = io_in_d_bits_source_0 == 7'h30; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_14 = _source_ok_T_112; // @[Parameters.scala:1138:31] wire _source_ok_T_113 = io_in_d_bits_source_0 == 7'h31; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_15 = _source_ok_T_113; // @[Parameters.scala:1138:31] wire _source_ok_T_114 = io_in_d_bits_source_0 == 7'h32; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_16 = _source_ok_T_114; // @[Parameters.scala:1138:31] wire _source_ok_T_115 = io_in_d_bits_source_0 == 7'h2C; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_17 = _source_ok_T_115; // @[Parameters.scala:1138:31] wire _source_ok_T_116 = io_in_d_bits_source_0 == 7'h2D; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_18 = _source_ok_T_116; // @[Parameters.scala:1138:31] wire _source_ok_T_117 = io_in_d_bits_source_0 == 7'h2E; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_19 = _source_ok_T_117; // @[Parameters.scala:1138:31] wire _source_ok_T_118 = io_in_d_bits_source_0 == 7'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_20 = _source_ok_T_118; // @[Parameters.scala:1138:31] wire _source_ok_T_119 = io_in_d_bits_source_0 == 7'h29; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_21 = _source_ok_T_119; // @[Parameters.scala:1138:31] wire _source_ok_T_120 = io_in_d_bits_source_0 == 7'h2A; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_22 = _source_ok_T_120; // @[Parameters.scala:1138:31] wire _source_ok_T_121 = io_in_d_bits_source_0 == 7'h24; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_23 = _source_ok_T_121; // @[Parameters.scala:1138:31] wire _source_ok_T_122 = io_in_d_bits_source_0 == 7'h25; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_24 = _source_ok_T_122; // @[Parameters.scala:1138:31] wire _source_ok_T_123 = io_in_d_bits_source_0 == 7'h26; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_25 = _source_ok_T_123; // @[Parameters.scala:1138:31] wire _source_ok_T_124 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_26 = _source_ok_T_124; // @[Parameters.scala:1138:31] wire _source_ok_T_125 = io_in_d_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_27 = _source_ok_T_125; // @[Parameters.scala:1138:31] wire _source_ok_T_126 = io_in_d_bits_source_0 == 7'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_28 = _source_ok_T_126; // @[Parameters.scala:1138:31] wire _source_ok_T_127 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_29 = _source_ok_T_127; // @[Parameters.scala:1138:31] wire _source_ok_T_128 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_129 = _source_ok_T_128 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_130 = _source_ok_T_129 \| _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_131 = _source_ok_T_130 \| _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_132 = _source_ok_T_131 \| _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_133 = _source_ok_T_132 \| _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_134 = _source_ok_T_133 \| _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_135 = _source_ok_T_134 \| _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_136 = _source_ok_T_135 \| _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_137 = _source_ok_T_136 \| _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_138 = _source_ok_T_137 \| _source_ok_WIRE_1_11; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_139 = _source_ok_T_138 \| _source_ok_WIRE_1_12; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_140 = _source_ok_T_139 \| _source_ok_WIRE_1_13; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_141 = _source_ok_T_140 \| _source_ok_WIRE_1_14; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_142 = _source_ok_T_141 \| _source_ok_WIRE_1_15; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_143 = _source_ok_T_142 \| _source_ok_WIRE_1_16; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_144 = _source_ok_T_143 \| _source_ok_WIRE_1_17; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_145 = _source_ok_T_144 \| _source_ok_WIRE_1_18; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_146 = _source_ok_T_145 \| _source_ok_WIRE_1_19; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_147 = _source_ok_T_146 \| _source_ok_WIRE_1_20; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_148 = _source_ok_T_147 \| _source_ok_WIRE_1_21; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_149 = _source_ok_T_148 \| _source_ok_WIRE_1_22; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_150 = _source_ok_T_149 \| _source_ok_WIRE_1_23; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_151 = _source_ok_T_150 \| _source_ok_WIRE_1_24; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_152 = _source_ok_T_151 \| _source_ok_WIRE_1_25; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_153 = _source_ok_T_152 \| _source_ok_WIRE_1_26; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_154 = _source_ok_T_153 \| _source_ok_WIRE_1_27; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_155 = _source_ok_T_154 \| _source_ok_WIRE_1_28; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_155 \| _source_ok_WIRE_1_29; // @[Parameters.scala:1138:31, :1139:46] wire _T_1775 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1775; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1775; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [13:0] address; // @[Monitor.scala:391:22] wire _T_1848 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1848; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1848; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1848; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [519:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [519:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [9:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [519:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [519:0] _a_size_lookup_T_6 = {512'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [519:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[519:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_3 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1701 = _T_1775 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1701 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1701 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1701 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1701 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [9:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [1027:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1701 ? _a_sizes_set_T_1[519:0] : 520'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [519:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1747 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1747 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1716 = _T_1848 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1716 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1716 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1716 ? _d_sizes_clr_T_5[519:0] : 520'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [519:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [519:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [519:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [519:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [519:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [519:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [519:0] _c_size_lookup_T_6 = {512'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [519:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[519:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [519:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1819 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1819 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1801 = _T_1848 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1801 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1801 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1801 ? _d_sizes_clr_T_11[519:0] : 520'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [519:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [519:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands / class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B \|\| ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B \|\| ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def (t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def (t: UInt) = self t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros \| ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def (t: SInt) = self t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros \| ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid \|\| output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid \|\| output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid \|\| output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def (t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def (t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }	module MacUnit_248( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [31:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7] wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54] wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /* Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_3( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input io_in_b_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input [63:0] io_in_c_bits_data, // @[Monitor.scala:20:14] input io_in_c_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_ready, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7] wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7] wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7] wire io_in_b_bits_source_0 = io_in_b_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7] wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7] wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7] wire io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7] wire [63:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7] wire io_in_c_bits_corrupt_0 = io_in_c_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_e_ready_0 = io_in_e_ready; // @[Monitor.scala:36:7] wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire mask_sub_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:206:21] wire mask_sub_sub_size_1 = 1'h1; // @[Misc.scala:209:26] wire mask_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_2_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_3_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_size_1 = 1'h1; // @[Misc.scala:209:26] wire mask_acc_8 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_9 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_10 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_11 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_12 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_13 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_14 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_15 = 1'h1; // @[Misc.scala:215:29] wire sink_ok_1 = 1'h1; // @[Monitor.scala:367:31] wire _b_first_beats1_opdata_T = 1'h1; // @[Edges.scala:97:37] wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire b_first_last = 1'h1; // @[Edges.scala:232:33] wire [3:0] io_in_b_bits_size = 4'h6; // @[Monitor.scala:36:7] wire [3:0] _mask_sizeOH_T_3 = 4'h6; // @[Misc.scala:202:34] wire [2:0] io_in_b_bits_opcode = 3'h6; // @[Monitor.scala:36:7] wire [7:0] io_in_b_bits_mask = 8'hFF; // @[Monitor.scala:36:7] wire [7:0] mask_1 = 8'hFF; // @[Misc.scala:222:10] wire [63:0] io_in_b_bits_data = 64'h0; // @[Monitor.scala:36:7] wire io_in_b_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire mask_sub_size_1 = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38] wire _legal_source_T_2 = 1'h0; // @[Mux.scala:30:73] wire b_first_beats1_opdata = 1'h0; // @[Edges.scala:97:28] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [3:0] _mask_sizeOH_T_4 = 4'h4; // @[OneHot.scala:65:12] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [2:0] _mask_sizeOH_T_5 = 3'h4; // @[OneHot.scala:65:27] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] mask_sizeOH_1 = 3'h5; // @[Misc.scala:202:81] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [8:0] b_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] b_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] b_first_beats1_decode = 9'h7; // @[Edges.scala:220:59] wire [11:0] is_aligned_mask_1 = 12'h3F; // @[package.scala:243:46] wire [11:0] _b_first_beats1_decode_T_2 = 12'h3F; // @[package.scala:243:46] wire [11:0] _is_aligned_mask_T_3 = 12'hFC0; // @[package.scala:243:76] wire [11:0] _b_first_beats1_decode_T_1 = 12'hFC0; // @[package.scala:243:76] wire [26:0] _is_aligned_mask_T_2 = 27'h3FFC0; // @[package.scala:243:71] wire [26:0] _b_first_beats1_decode_T = 27'h3FFC0; // @[package.scala:243:71] wire [3:0] mask_lo_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi_1 = 4'hF; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_sizeOH_shiftAmount_1 = 2'h2; // @[OneHot.scala:64:49] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire _source_ok_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire _legal_source_T_1 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T = io_in_b_bits_address_0; // @[Monitor.scala:36:7] wire _source_ok_T_5 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_100 = io_in_c_bits_address_0; // @[Monitor.scala:36:7] wire _source_ok_T_3 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = ~io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire _source_ok_WIRE_1 = _source_ok_T_1; // @[Parameters.scala:1138:31] wire source_ok = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire _source_ok_T_2 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_2; // @[Parameters.scala:1138:31] wire _source_ok_WIRE_1_1 = _source_ok_T_3; // @[Parameters.scala:1138:31] wire source_ok_1 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46] wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_5 = {io_in_b_bits_address_0[31:13], io_in_b_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46] wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1 = _address_ok_T_9; // @[Parameters.scala:612:40] wire [13:0] _GEN_0 = io_in_b_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_10 = {io_in_b_bits_address_0[31:14], _GEN_0}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46] wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_2 = _address_ok_T_14; // @[Parameters.scala:612:40] wire [16:0] _GEN_1 = io_in_b_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_15 = {io_in_b_bits_address_0[31:17], _GEN_1}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46] wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_3 = _address_ok_T_19; // @[Parameters.scala:612:40] wire [17:0] _GEN_2 = io_in_b_bits_address_0[17:0] ^ 18'h20000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_20 = {io_in_b_bits_address_0[31:18], _GEN_2}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_21 = {1'h0, _address_ok_T_20}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_22 = _address_ok_T_21 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_23 = _address_ok_T_22; // @[Parameters.scala:137:46] wire _address_ok_T_24 = _address_ok_T_23 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_4 = _address_ok_T_24; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_25 = {io_in_b_bits_address_0[31:18], io_in_b_bits_address_0[17:0] ^ 18'h21000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_26 = {1'h0, _address_ok_T_25}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_27 = _address_ok_T_26 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_28 = _address_ok_T_27; // @[Parameters.scala:137:46] wire _address_ok_T_29 = _address_ok_T_28 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_5 = _address_ok_T_29; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_30 = {io_in_b_bits_address_0[31:18], io_in_b_bits_address_0[17:0] ^ 18'h22000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_31 = {1'h0, _address_ok_T_30}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_32 = _address_ok_T_31 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_33 = _address_ok_T_32; // @[Parameters.scala:137:46] wire _address_ok_T_34 = _address_ok_T_33 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_6 = _address_ok_T_34; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_35 = {io_in_b_bits_address_0[31:18], io_in_b_bits_address_0[17:0] ^ 18'h23000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_36 = {1'h0, _address_ok_T_35}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_37 = _address_ok_T_36 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_38 = _address_ok_T_37; // @[Parameters.scala:137:46] wire _address_ok_T_39 = _address_ok_T_38 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_7 = _address_ok_T_39; // @[Parameters.scala:612:40] wire [17:0] _GEN_3 = io_in_b_bits_address_0[17:0] ^ 18'h24000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_40 = {io_in_b_bits_address_0[31:18], _GEN_3}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_41 = {1'h0, _address_ok_T_40}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_42 = _address_ok_T_41 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_43 = _address_ok_T_42; // @[Parameters.scala:137:46] wire _address_ok_T_44 = _address_ok_T_43 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_8 = _address_ok_T_44; // @[Parameters.scala:612:40] wire [20:0] _GEN_4 = io_in_b_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_45 = {io_in_b_bits_address_0[31:21], _GEN_4}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_46 = {1'h0, _address_ok_T_45}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_47 = _address_ok_T_46 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_48 = _address_ok_T_47; // @[Parameters.scala:137:46] wire _address_ok_T_49 = _address_ok_T_48 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_9 = _address_ok_T_49; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_50 = {io_in_b_bits_address_0[31:21], io_in_b_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_51 = {1'h0, _address_ok_T_50}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_52 = _address_ok_T_51 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_53 = _address_ok_T_52; // @[Parameters.scala:137:46] wire _address_ok_T_54 = _address_ok_T_53 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_10 = _address_ok_T_54; // @[Parameters.scala:612:40] wire [25:0] _GEN_5 = io_in_b_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_55 = {io_in_b_bits_address_0[31:26], _GEN_5}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_56 = {1'h0, _address_ok_T_55}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_57 = _address_ok_T_56 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_58 = _address_ok_T_57; // @[Parameters.scala:137:46] wire _address_ok_T_59 = _address_ok_T_58 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_11 = _address_ok_T_59; // @[Parameters.scala:612:40] wire [25:0] _GEN_6 = io_in_b_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_60 = {io_in_b_bits_address_0[31:26], _GEN_6}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_61 = {1'h0, _address_ok_T_60}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_62 = _address_ok_T_61 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_63 = _address_ok_T_62; // @[Parameters.scala:137:46] wire _address_ok_T_64 = _address_ok_T_63 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_12 = _address_ok_T_64; // @[Parameters.scala:612:40] wire [27:0] _GEN_7 = io_in_b_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_65 = {io_in_b_bits_address_0[31:28], _GEN_7}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_66 = {1'h0, _address_ok_T_65}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_67 = _address_ok_T_66 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_68 = _address_ok_T_67; // @[Parameters.scala:137:46] wire _address_ok_T_69 = _address_ok_T_68 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_13 = _address_ok_T_69; // @[Parameters.scala:612:40] wire [27:0] _GEN_8 = io_in_b_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_70 = {io_in_b_bits_address_0[31:28], _GEN_8}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_71 = {1'h0, _address_ok_T_70}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_72 = _address_ok_T_71 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_73 = _address_ok_T_72; // @[Parameters.scala:137:46] wire _address_ok_T_74 = _address_ok_T_73 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_14 = _address_ok_T_74; // @[Parameters.scala:612:40] wire [28:0] _GEN_9 = io_in_b_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_75 = {io_in_b_bits_address_0[31:29], _GEN_9}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_76 = {1'h0, _address_ok_T_75}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_77 = _address_ok_T_76 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_78 = _address_ok_T_77; // @[Parameters.scala:137:46] wire _address_ok_T_79 = _address_ok_T_78 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_15 = _address_ok_T_79; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_80 = io_in_b_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_81 = {1'h0, _address_ok_T_80}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_82 = _address_ok_T_81 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_83 = _address_ok_T_82; // @[Parameters.scala:137:46] wire _address_ok_T_84 = _address_ok_T_83 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_16 = _address_ok_T_84; // @[Parameters.scala:612:40] wire _address_ok_T_85 = _address_ok_WIRE_0 \| _address_ok_WIRE_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_86 = _address_ok_T_85 \| _address_ok_WIRE_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_87 = _address_ok_T_86 \| _address_ok_WIRE_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_88 = _address_ok_T_87 \| _address_ok_WIRE_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_89 = _address_ok_T_88 \| _address_ok_WIRE_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_90 = _address_ok_T_89 \| _address_ok_WIRE_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_91 = _address_ok_T_90 \| _address_ok_WIRE_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_92 = _address_ok_T_91 \| _address_ok_WIRE_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_93 = _address_ok_T_92 \| _address_ok_WIRE_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_94 = _address_ok_T_93 \| _address_ok_WIRE_10; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_95 = _address_ok_T_94 \| _address_ok_WIRE_11; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_96 = _address_ok_T_95 \| _address_ok_WIRE_12; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_97 = _address_ok_T_96 \| _address_ok_WIRE_13; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_98 = _address_ok_T_97 \| _address_ok_WIRE_14; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_99 = _address_ok_T_98 \| _address_ok_WIRE_15; // @[Parameters.scala:612:40, :636:64] wire address_ok = _address_ok_T_99 \| _address_ok_WIRE_16; // @[Parameters.scala:612:40, :636:64] wire [31:0] _is_aligned_T_1 = {26'h0, io_in_b_bits_address_0[5:0]}; // @[Monitor.scala:36:7] wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2_1 = mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2_1 = mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_0_2_1; // @[Misc.scala:214:27, :215:38] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_1_2_1; // @[Misc.scala:214:27, :215:38] wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_eq_8 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_eq_8; // @[Misc.scala:214:27, :215:38] wire mask_eq_9 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_eq_9; // @[Misc.scala:214:27, :215:38] wire mask_eq_10 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_eq_10; // @[Misc.scala:214:27, :215:38] wire mask_eq_11 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_eq_11; // @[Misc.scala:214:27, :215:38] wire mask_eq_12 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_eq_12; // @[Misc.scala:214:27, :215:38] wire mask_eq_13 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_eq_13; // @[Misc.scala:214:27, :215:38] wire mask_eq_14 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_eq_14; // @[Misc.scala:214:27, :215:38] wire mask_eq_15 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_eq_15; // @[Misc.scala:214:27, :215:38] wire _legal_source_T = ~io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire _legal_source_WIRE_0 = _legal_source_T; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_1 = _legal_source_T_1; // @[Parameters.scala:1138:31] wire _legal_source_T_3 = _legal_source_WIRE_1; // @[Mux.scala:30:73] wire _legal_source_T_4 = _legal_source_T_3; // @[Mux.scala:30:73] wire _legal_source_WIRE_1_0 = _legal_source_T_4; // @[Mux.scala:30:73] wire legal_source = _legal_source_WIRE_1_0 == io_in_b_bits_source_0; // @[Mux.scala:30:73] wire _source_ok_T_4 = ~io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_0 = _source_ok_T_4; // @[Parameters.scala:1138:31] wire _source_ok_WIRE_2_1 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire source_ok_2 = _source_ok_WIRE_2_0 \| _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN_10 = 27'hFFF << io_in_c_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_4; // @[package.scala:243:71] assign _is_aligned_mask_T_4 = _GEN_10; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T; // @[package.scala:243:71] assign _c_first_beats1_decode_T = _GEN_10; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71] assign _c_first_beats1_decode_T_3 = _GEN_10; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_2 = {20'h0, io_in_c_bits_address_0[11:0] & is_aligned_mask_2}; // @[package.scala:243:46] wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}] wire [32:0] _address_ok_T_101 = {1'h0, _address_ok_T_100}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_102 = _address_ok_T_101 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_103 = _address_ok_T_102; // @[Parameters.scala:137:46] wire _address_ok_T_104 = _address_ok_T_103 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_0 = _address_ok_T_104; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_105 = {io_in_c_bits_address_0[31:13], io_in_c_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_106 = {1'h0, _address_ok_T_105}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_107 = _address_ok_T_106 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_108 = _address_ok_T_107; // @[Parameters.scala:137:46] wire _address_ok_T_109 = _address_ok_T_108 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_1 = _address_ok_T_109; // @[Parameters.scala:612:40] wire [13:0] _GEN_11 = io_in_c_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_110 = {io_in_c_bits_address_0[31:14], _GEN_11}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_111 = {1'h0, _address_ok_T_110}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_112 = _address_ok_T_111 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_113 = _address_ok_T_112; // @[Parameters.scala:137:46] wire _address_ok_T_114 = _address_ok_T_113 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_2 = _address_ok_T_114; // @[Parameters.scala:612:40] wire [16:0] _GEN_12 = io_in_c_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_115 = {io_in_c_bits_address_0[31:17], _GEN_12}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_116 = {1'h0, _address_ok_T_115}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_117 = _address_ok_T_116 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_118 = _address_ok_T_117; // @[Parameters.scala:137:46] wire _address_ok_T_119 = _address_ok_T_118 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_3 = _address_ok_T_119; // @[Parameters.scala:612:40] wire [17:0] _GEN_13 = io_in_c_bits_address_0[17:0] ^ 18'h20000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_120 = {io_in_c_bits_address_0[31:18], _GEN_13}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_121 = {1'h0, _address_ok_T_120}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_122 = _address_ok_T_121 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_123 = _address_ok_T_122; // @[Parameters.scala:137:46] wire _address_ok_T_124 = _address_ok_T_123 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_4 = _address_ok_T_124; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_125 = {io_in_c_bits_address_0[31:18], io_in_c_bits_address_0[17:0] ^ 18'h21000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_126 = {1'h0, _address_ok_T_125}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_127 = _address_ok_T_126 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_128 = _address_ok_T_127; // @[Parameters.scala:137:46] wire _address_ok_T_129 = _address_ok_T_128 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_5 = _address_ok_T_129; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_130 = {io_in_c_bits_address_0[31:18], io_in_c_bits_address_0[17:0] ^ 18'h22000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_131 = {1'h0, _address_ok_T_130}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_132 = _address_ok_T_131 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_133 = _address_ok_T_132; // @[Parameters.scala:137:46] wire _address_ok_T_134 = _address_ok_T_133 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_6 = _address_ok_T_134; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_135 = {io_in_c_bits_address_0[31:18], io_in_c_bits_address_0[17:0] ^ 18'h23000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_136 = {1'h0, _address_ok_T_135}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_137 = _address_ok_T_136 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_138 = _address_ok_T_137; // @[Parameters.scala:137:46] wire _address_ok_T_139 = _address_ok_T_138 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_7 = _address_ok_T_139; // @[Parameters.scala:612:40] wire [17:0] _GEN_14 = io_in_c_bits_address_0[17:0] ^ 18'h24000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_140 = {io_in_c_bits_address_0[31:18], _GEN_14}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_141 = {1'h0, _address_ok_T_140}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_142 = _address_ok_T_141 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_143 = _address_ok_T_142; // @[Parameters.scala:137:46] wire _address_ok_T_144 = _address_ok_T_143 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_8 = _address_ok_T_144; // @[Parameters.scala:612:40] wire [20:0] _GEN_15 = io_in_c_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_145 = {io_in_c_bits_address_0[31:21], _GEN_15}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_146 = {1'h0, _address_ok_T_145}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_147 = _address_ok_T_146 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_148 = _address_ok_T_147; // @[Parameters.scala:137:46] wire _address_ok_T_149 = _address_ok_T_148 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_9 = _address_ok_T_149; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_150 = {io_in_c_bits_address_0[31:21], io_in_c_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_151 = {1'h0, _address_ok_T_150}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_152 = _address_ok_T_151 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_153 = _address_ok_T_152; // @[Parameters.scala:137:46] wire _address_ok_T_154 = _address_ok_T_153 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_10 = _address_ok_T_154; // @[Parameters.scala:612:40] wire [25:0] _GEN_16 = io_in_c_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_155 = {io_in_c_bits_address_0[31:26], _GEN_16}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_156 = {1'h0, _address_ok_T_155}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_157 = _address_ok_T_156 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_158 = _address_ok_T_157; // @[Parameters.scala:137:46] wire _address_ok_T_159 = _address_ok_T_158 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_11 = _address_ok_T_159; // @[Parameters.scala:612:40] wire [25:0] _GEN_17 = io_in_c_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_160 = {io_in_c_bits_address_0[31:26], _GEN_17}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_161 = {1'h0, _address_ok_T_160}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_162 = _address_ok_T_161 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_163 = _address_ok_T_162; // @[Parameters.scala:137:46] wire _address_ok_T_164 = _address_ok_T_163 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_12 = _address_ok_T_164; // @[Parameters.scala:612:40] wire [27:0] _GEN_18 = io_in_c_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_165 = {io_in_c_bits_address_0[31:28], _GEN_18}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_166 = {1'h0, _address_ok_T_165}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_167 = _address_ok_T_166 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_168 = _address_ok_T_167; // @[Parameters.scala:137:46] wire _address_ok_T_169 = _address_ok_T_168 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_13 = _address_ok_T_169; // @[Parameters.scala:612:40] wire [27:0] _GEN_19 = io_in_c_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_170 = {io_in_c_bits_address_0[31:28], _GEN_19}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_171 = {1'h0, _address_ok_T_170}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_172 = _address_ok_T_171 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_173 = _address_ok_T_172; // @[Parameters.scala:137:46] wire _address_ok_T_174 = _address_ok_T_173 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_14 = _address_ok_T_174; // @[Parameters.scala:612:40] wire [28:0] _GEN_20 = io_in_c_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_175 = {io_in_c_bits_address_0[31:29], _GEN_20}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_176 = {1'h0, _address_ok_T_175}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_177 = _address_ok_T_176 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_178 = _address_ok_T_177; // @[Parameters.scala:137:46] wire _address_ok_T_179 = _address_ok_T_178 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_15 = _address_ok_T_179; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_180 = io_in_c_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_181 = {1'h0, _address_ok_T_180}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_182 = _address_ok_T_181 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_183 = _address_ok_T_182; // @[Parameters.scala:137:46] wire _address_ok_T_184 = _address_ok_T_183 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_16 = _address_ok_T_184; // @[Parameters.scala:612:40] wire _address_ok_T_185 = _address_ok_WIRE_1_0 \| _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_186 = _address_ok_T_185 \| _address_ok_WIRE_1_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_187 = _address_ok_T_186 \| _address_ok_WIRE_1_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_188 = _address_ok_T_187 \| _address_ok_WIRE_1_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_189 = _address_ok_T_188 \| _address_ok_WIRE_1_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_190 = _address_ok_T_189 \| _address_ok_WIRE_1_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_191 = _address_ok_T_190 \| _address_ok_WIRE_1_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_192 = _address_ok_T_191 \| _address_ok_WIRE_1_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_193 = _address_ok_T_192 \| _address_ok_WIRE_1_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_194 = _address_ok_T_193 \| _address_ok_WIRE_1_10; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_195 = _address_ok_T_194 \| _address_ok_WIRE_1_11; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_196 = _address_ok_T_195 \| _address_ok_WIRE_1_12; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_197 = _address_ok_T_196 \| _address_ok_WIRE_1_13; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_198 = _address_ok_T_197 \| _address_ok_WIRE_1_14; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_199 = _address_ok_T_198 \| _address_ok_WIRE_1_15; // @[Parameters.scala:612:40, :636:64] wire address_ok_1 = _address_ok_T_199 \| _address_ok_WIRE_1_16; // @[Parameters.scala:612:40, :636:64] wire _T_2656 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_2656; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_2656; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_2730 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_2730; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_2730; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_2730; // @[Decoupled.scala:51:35] wire _d_first_T_3; // @[Decoupled.scala:51:35] assign _d_first_T_3 = _T_2730; // @[Decoupled.scala:51:35] wire [26:0] _GEN_21 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_21; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_21; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_21; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71] assign _d_first_beats1_decode_T_9 = _GEN_21; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35] wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35] reg [8:0] b_first_counter; // @[Edges.scala:229:27] wire [9:0] _b_first_counter1_T = {1'h0, b_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] b_first_counter1 = _b_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire b_first = b_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _b_first_last_T = b_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire [8:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] _b_first_counter_T = b_first ? 9'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [1:0] param_2; // @[Monitor.scala:411:22] reg source_2; // @[Monitor.scala:413:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _T_2727 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35] wire _c_first_T; // @[Decoupled.scala:51:35] assign _c_first_T = _T_2727; // @[Decoupled.scala:51:35] wire _c_first_T_1; // @[Decoupled.scala:51:35] assign _c_first_T_1 = _T_2727; // @[Decoupled.scala:51:35] wire [11:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [8:0] c_first_counter; // @[Edges.scala:229:27] wire [9:0] _c_first_counter1_T = {1'h0, c_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] c_first_counter1 = _c_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire c_first = c_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T = c_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_1 = c_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last = _c_first_last_T \| _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35] wire [8:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [3:0] size_3; // @[Monitor.scala:517:22] reg source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [7:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [15:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [1:0] a_set; // @[Monitor.scala:626:34] wire [1:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [7:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [15:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [3:0] _GEN_22 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [3:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_22; // @[Monitor.scala:637:69] wire [3:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_22; // @[Monitor.scala:637:69, :680:101] wire [3:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_22; // @[Monitor.scala:637:69, :749:69] wire [3:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_22; // @[Monitor.scala:637:69, :790:101] wire [7:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [15:0] _a_opcode_lookup_T_6 = {8'h0, _a_opcode_lookup_T_1 & 8'hF}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [3:0] _GEN_23 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [3:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_23; // @[Monitor.scala:641:65] wire [3:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_23; // @[Monitor.scala:641:65, :681:99] wire [3:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_23; // @[Monitor.scala:641:65, :750:67] wire [3:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_23; // @[Monitor.scala:641:65, :791:99] wire [15:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [15:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & 16'hFF; // @[Monitor.scala:641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [1:0] _GEN_24 = {1'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_25 = 2'h1 << _GEN_24; // @[OneHot.scala:58:35] wire [1:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_25; // @[OneHot.scala:58:35] wire [1:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_25; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 2'h0; // @[OneHot.scala:58:35] wire _T_2582 = _T_2656 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_2582 ? _a_set_T : 2'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_2582 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_2582 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [3:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_2582 ? _a_opcodes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [3:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :660:{52,77}] assign a_sizes_set = _T_2582 ? _a_sizes_set_T_1[15:0] : 16'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [1:0] d_clr; // @[Monitor.scala:664:34] wire [1:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [7:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [15:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_26 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_26; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_26; // @[Monitor.scala:673:46, :783:46] wire _T_2628 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [1:0] _GEN_27 = {1'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_28 = 2'h1 << _GEN_27; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_28; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_28; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_28; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_28; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_2628 & ~d_release_ack ? _d_clr_wo_ready_T : 2'h0; // @[OneHot.scala:58:35] wire _T_2597 = _T_2730 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_2597 ? _d_clr_T : 2'h0; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_5 = 31'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_2597 ? _d_opcodes_clr_T_5[7:0] : 8'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [30:0] _d_sizes_clr_T_5 = 31'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_2597 ? _d_sizes_clr_T_5[15:0] : 16'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [1:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [7:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [7:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [7:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [15:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [15:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [15:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] reg [7:0] inflight_opcodes_1; // @[Monitor.scala:727:35] reg [15:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [11:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [8:0] c_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] c_first_counter1_1 = _c_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire c_first_1 = c_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T_2 = c_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_3 = c_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last_1 = _c_first_last_T_2 \| _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [1:0] c_set; // @[Monitor.scala:738:34] wire [1:0] c_set_wo_ready; // @[Monitor.scala:739:34] wire [7:0] c_opcodes_set; // @[Monitor.scala:740:34] wire [15:0] c_sizes_set; // @[Monitor.scala:741:34] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [7:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [15:0] _c_opcode_lookup_T_6 = {8'h0, _c_opcode_lookup_T_1 & 8'hF}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [15:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & 16'hFF; // @[Monitor.scala:750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40] wire [4:0] c_sizes_set_interm; // @[Monitor.scala:755:40] wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44] wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7] wire [1:0] _GEN_29 = {1'h0, io_in_c_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_30 = 2'h1 << _GEN_29; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35] assign _c_set_wo_ready_T = _GEN_30; // @[OneHot.scala:58:35] wire [1:0] _c_set_T; // @[OneHot.scala:58:35] assign _c_set_T = _GEN_30; // @[OneHot.scala:58:35] assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T : 2'h0; // @[OneHot.scala:58:35] wire _T_2669 = _T_2727 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35] assign c_set = _T_2669 ? _c_set_T : 2'h0; // @[OneHot.scala:58:35] wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53] wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}] assign c_opcodes_set_interm = _T_2669 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}] wire [4:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51] wire [4:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:766:{51,59}] assign c_sizes_set_interm = _T_2669 ? _c_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}] wire [3:0] _c_opcodes_set_T = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79] wire [18:0] _c_opcodes_set_T_1 = {15'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:754:40, :767:{54,79}] assign c_opcodes_set = _T_2669 ? _c_opcodes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}] wire [3:0] _c_sizes_set_T = {io_in_c_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :768:77] wire [19:0] _c_sizes_set_T_1 = {15'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:755:40, :768:{52,77}] assign c_sizes_set = _T_2669 ? _c_sizes_set_T_1[15:0] : 16'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}] wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47] wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95] wire c_probe_ack = _c_probe_ack_T \| _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}] wire [1:0] d_clr_1; // @[Monitor.scala:774:34] wire [1:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [7:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [15:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_2700 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_2700 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 2'h0; // @[OneHot.scala:58:35] wire _T_2682 = _T_2730 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_2682 ? _d_clr_T_1 : 2'h0; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_11 = 31'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_2682 ? _d_opcodes_clr_T_11[7:0] : 8'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [30:0] _d_sizes_clr_T_11 = 31'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_2682 ? _d_sizes_clr_T_11[15:0] : 16'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}] wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}] wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}] wire [1:0] _inflight_T_3 = inflight_1 \| c_set; // @[Monitor.scala:726:35, :738:34, :814:35] wire [1:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [7:0] _inflight_opcodes_T_3 = inflight_opcodes_1 \| c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43] wire [7:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [7:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [15:0] _inflight_sizes_T_3 = inflight_sizes_1 \| c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41] wire [15:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [15:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26] wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26] reg [7:0] inflight_2; // @[Monitor.scala:828:27] wire [11:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_3; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_3 = _d_first_counter1_T_3[8:0]; // @[Edges.scala:230:28] wire d_first_3 = d_first_counter_3 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_6 = d_first_counter_3 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_7 = d_first_beats1_3 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_3 = _d_first_last_T_6 \| _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}] wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [7:0] d_set; // @[Monitor.scala:833:25] wire _T_2736 = _T_2730 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35] wire [7:0] _GEN_31 = {5'h0, io_in_d_bits_sink_0}; // @[OneHot.scala:58:35] wire [7:0] _d_set_T = 8'h1 << _GEN_31; // @[OneHot.scala:58:35] assign d_set = _T_2736 ? _d_set_T : 8'h0; // @[OneHot.scala:58:35] wire [7:0] e_clr; // @[Monitor.scala:839:25] wire _T_2745 = io_in_e_ready_0 & io_in_e_valid_0; // @[Decoupled.scala:51:35] wire [7:0] _GEN_32 = {5'h0, io_in_e_bits_sink_0}; // @[OneHot.scala:58:35] wire [7:0] _e_clr_T = 8'h1 << _GEN_32; // @[OneHot.scala:58:35] assign e_clr = _T_2745 ? _e_clr_T : 8'h0; // @[OneHot.scala:58:35]
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth \| params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset \|\| !sio.sink_reset_n) \|\| !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise \|\| prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready \|\| !sio.source_reset_n \|\| reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise \|\| prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }	module AsyncQueueSink_TLBundleA_a32d64s2k3z4c( // @[AsyncQueue.scala:136:7] input clock, // @[AsyncQueue.scala:136:7] input reset, // @[AsyncQueue.scala:136:7] input io_deq_ready, // @[AsyncQueue.scala:139:14] output io_deq_valid, // @[AsyncQueue.scala:139:14] output [2:0] io_deq_bits_opcode, // @[AsyncQueue.scala:139:14] output [2:0] io_deq_bits_param, // @[AsyncQueue.scala:139:14] output [3:0] io_deq_bits_size, // @[AsyncQueue.scala:139:14] output [1:0] io_deq_bits_source, // @[AsyncQueue.scala:139:14] output [31:0] io_deq_bits_address, // @[AsyncQueue.scala:139:14] output [7:0] io_deq_bits_mask, // @[AsyncQueue.scala:139:14] output [63:0] io_deq_bits_data, // @[AsyncQueue.scala:139:14] output io_deq_bits_corrupt, // @[AsyncQueue.scala:139:14] input [2:0] io_async_mem_0_opcode, // @[AsyncQueue.scala:139:14] input [2:0] io_async_mem_0_param, // @[AsyncQueue.scala:139:14] input [3:0] io_async_mem_0_size, // @[AsyncQueue.scala:139:14] input [1:0] io_async_mem_0_source, // @[AsyncQueue.scala:139:14] input [31:0] io_async_mem_0_address, // @[AsyncQueue.scala:139:14] input [7:0] io_async_mem_0_mask, // @[AsyncQueue.scala:139:14] input [63:0] io_async_mem_0_data, // @[AsyncQueue.scala:139:14] input [2:0] io_async_mem_1_opcode, // @[AsyncQueue.scala:139:14] input [2:0] io_async_mem_1_param, // @[AsyncQueue.scala:139:14] input [3:0] io_async_mem_1_size, // @[AsyncQueue.scala:139:14] input [1:0] io_async_mem_1_source, // @[AsyncQueue.scala:139:14] input [31:0] io_async_mem_1_address, // @[AsyncQueue.scala:139:14] input [7:0] io_async_mem_1_mask, // @[AsyncQueue.scala:139:14] input [63:0] io_async_mem_1_data, // @[AsyncQueue.scala:139:14] input [2:0] io_async_mem_2_opcode, // @[AsyncQueue.scala:139:14] input [2:0] io_async_mem_2_param, // @[AsyncQueue.scala:139:14] input [3:0] io_async_mem_2_size, // @[AsyncQueue.scala:139:14] input [1:0] io_async_mem_2_source, // @[AsyncQueue.scala:139:14] input [31:0] io_async_mem_2_address, // @[AsyncQueue.scala:139:14] input [7:0] io_async_mem_2_mask, // @[AsyncQueue.scala:139:14] input [63:0] io_async_mem_2_data, // @[AsyncQueue.scala:139:14] input [2:0] io_async_mem_3_opcode, // @[AsyncQueue.scala:139:14] input [2:0] io_async_mem_3_param, // @[AsyncQueue.scala:139:14] input [3:0] io_async_mem_3_size, // @[AsyncQueue.scala:139:14] input [1:0] io_async_mem_3_source, // @[AsyncQueue.scala:139:14] input [31:0] io_async_mem_3_address, // @[AsyncQueue.scala:139:14] input [7:0] io_async_mem_3_mask, // @[AsyncQueue.scala:139:14] input [63:0] io_async_mem_3_data, // @[AsyncQueue.scala:139:14] input [2:0] io_async_mem_4_opcode, // @[AsyncQueue.scala:139:14] input [2:0] io_async_mem_4_param, // @[AsyncQueue.scala:139:14] input [3:0] io_async_mem_4_size, // @[AsyncQueue.scala:139:14] input [1:0] io_async_mem_4_source, // @[AsyncQueue.scala:139:14] input [31:0] io_async_mem_4_address, // @[AsyncQueue.scala:139:14] input [7:0] io_async_mem_4_mask, // @[AsyncQueue.scala:139:14] input [63:0] io_async_mem_4_data, // @[AsyncQueue.scala:139:14] input [2:0] io_async_mem_5_opcode, // @[AsyncQueue.scala:139:14] input [2:0] io_async_mem_5_param, // @[AsyncQueue.scala:139:14] input [3:0] io_async_mem_5_size, // @[AsyncQueue.scala:139:14] input [1:0] io_async_mem_5_source, // @[AsyncQueue.scala:139:14] input [31:0] io_async_mem_5_address, // @[AsyncQueue.scala:139:14] input [7:0] io_async_mem_5_mask, // @[AsyncQueue.scala:139:14] input [63:0] io_async_mem_5_data, // @[AsyncQueue.scala:139:14] input [2:0] io_async_mem_6_opcode, // @[AsyncQueue.scala:139:14] input [2:0] io_async_mem_6_param, // @[AsyncQueue.scala:139:14] input [3:0] io_async_mem_6_size, // @[AsyncQueue.scala:139:14] input [1:0] io_async_mem_6_source, // @[AsyncQueue.scala:139:14] input [31:0] io_async_mem_6_address, // @[AsyncQueue.scala:139:14] input [7:0] io_async_mem_6_mask, // @[AsyncQueue.scala:139:14] input [63:0] io_async_mem_6_data, // @[AsyncQueue.scala:139:14] input [2:0] io_async_mem_7_opcode, // @[AsyncQueue.scala:139:14] input [2:0] io_async_mem_7_param, // @[AsyncQueue.scala:139:14] input [3:0] io_async_mem_7_size, // @[AsyncQueue.scala:139:14] input [1:0] io_async_mem_7_source, // @[AsyncQueue.scala:139:14] input [31:0] io_async_mem_7_address, // @[AsyncQueue.scala:139:14] input [7:0] io_async_mem_7_mask, // @[AsyncQueue.scala:139:14] input [63:0] io_async_mem_7_data, // @[AsyncQueue.scala:139:14] output [3:0] io_async_ridx, // @[AsyncQueue.scala:139:14] input [3:0] io_async_widx, // @[AsyncQueue.scala:139:14] output io_async_safe_ridx_valid, // @[AsyncQueue.scala:139:14] input io_async_safe_widx_valid, // @[AsyncQueue.scala:139:14] input io_async_safe_source_reset_n, // @[AsyncQueue.scala:139:14] output io_async_safe_sink_reset_n // @[AsyncQueue.scala:139:14] ); wire _source_extend_io_out; // @[AsyncQueue.scala:175:31] wire _sink_valid_0_io_out; // @[AsyncQueue.scala:172:33] wire io_deq_ready_0 = io_deq_ready; // @[AsyncQueue.scala:136:7] wire [2:0] io_async_mem_0_opcode_0 = io_async_mem_0_opcode; // @[AsyncQueue.scala:136:7] wire [2:0] io_async_mem_0_param_0 = io_async_mem_0_param; // @[AsyncQueue.scala:136:7] wire [3:0] io_async_mem_0_size_0 = io_async_mem_0_size; // @[AsyncQueue.scala:136:7] wire [1:0] io_async_mem_0_source_0 = io_async_mem_0_source; // @[AsyncQueue.scala:136:7] wire [31:0] io_async_mem_0_address_0 = io_async_mem_0_address; // @[AsyncQueue.scala:136:7] wire [7:0] io_async_mem_0_mask_0 = io_async_mem_0_mask; // @[AsyncQueue.scala:136:7] wire [63:0] io_async_mem_0_data_0 = io_async_mem_0_data; // @[AsyncQueue.scala:136:7] wire [2:0] io_async_mem_1_opcode_0 = io_async_mem_1_opcode; // @[AsyncQueue.scala:136:7] wire [2:0] io_async_mem_1_param_0 = io_async_mem_1_param; // @[AsyncQueue.scala:136:7] wire [3:0] io_async_mem_1_size_0 = io_async_mem_1_size; // @[AsyncQueue.scala:136:7] wire [1:0] io_async_mem_1_source_0 = io_async_mem_1_source; // @[AsyncQueue.scala:136:7] wire [31:0] io_async_mem_1_address_0 = io_async_mem_1_address; // @[AsyncQueue.scala:136:7] wire [7:0] io_async_mem_1_mask_0 = io_async_mem_1_mask; // @[AsyncQueue.scala:136:7] wire [63:0] io_async_mem_1_data_0 = io_async_mem_1_data; // @[AsyncQueue.scala:136:7] wire [2:0] io_async_mem_2_opcode_0 = io_async_mem_2_opcode; // @[AsyncQueue.scala:136:7] wire [2:0] io_async_mem_2_param_0 = io_async_mem_2_param; // @[AsyncQueue.scala:136:7] wire [3:0] io_async_mem_2_size_0 = io_async_mem_2_size; // @[AsyncQueue.scala:136:7] wire [1:0] io_async_mem_2_source_0 = io_async_mem_2_source; // @[AsyncQueue.scala:136:7] wire [31:0] io_async_mem_2_address_0 = io_async_mem_2_address; // @[AsyncQueue.scala:136:7] wire [7:0] io_async_mem_2_mask_0 = io_async_mem_2_mask; // @[AsyncQueue.scala:136:7] wire [63:0] io_async_mem_2_data_0 = io_async_mem_2_data; // @[AsyncQueue.scala:136:7] wire [2:0] io_async_mem_3_opcode_0 = io_async_mem_3_opcode; // @[AsyncQueue.scala:136:7] wire [2:0] io_async_mem_3_param_0 = io_async_mem_3_param; // @[AsyncQueue.scala:136:7] wire [3:0] io_async_mem_3_size_0 = io_async_mem_3_size; // @[AsyncQueue.scala:136:7] wire [1:0] io_async_mem_3_source_0 = io_async_mem_3_source; // @[AsyncQueue.scala:136:7] wire [31:0] io_async_mem_3_address_0 = io_async_mem_3_address; // @[AsyncQueue.scala:136:7] wire [7:0] io_async_mem_3_mask_0 = io_async_mem_3_mask; // @[AsyncQueue.scala:136:7] wire [63:0] io_async_mem_3_data_0 = io_async_mem_3_data; // @[AsyncQueue.scala:136:7] wire [2:0] io_async_mem_4_opcode_0 = io_async_mem_4_opcode; // @[AsyncQueue.scala:136:7] wire [2:0] io_async_mem_4_param_0 = io_async_mem_4_param; // @[AsyncQueue.scala:136:7] wire [3:0] io_async_mem_4_size_0 = io_async_mem_4_size; // @[AsyncQueue.scala:136:7] wire [1:0] io_async_mem_4_source_0 = io_async_mem_4_source; // @[AsyncQueue.scala:136:7] wire [31:0] io_async_mem_4_address_0 = io_async_mem_4_address; // @[AsyncQueue.scala:136:7] wire [7:0] io_async_mem_4_mask_0 = io_async_mem_4_mask; // @[AsyncQueue.scala:136:7] wire [63:0] io_async_mem_4_data_0 = io_async_mem_4_data; // @[AsyncQueue.scala:136:7] wire [2:0] io_async_mem_5_opcode_0 = io_async_mem_5_opcode; // @[AsyncQueue.scala:136:7] wire [2:0] io_async_mem_5_param_0 = io_async_mem_5_param; // @[AsyncQueue.scala:136:7] wire [3:0] io_async_mem_5_size_0 = io_async_mem_5_size; // @[AsyncQueue.scala:136:7] wire [1:0] io_async_mem_5_source_0 = io_async_mem_5_source; // @[AsyncQueue.scala:136:7] wire [31:0] io_async_mem_5_address_0 = io_async_mem_5_address; // @[AsyncQueue.scala:136:7] wire [7:0] io_async_mem_5_mask_0 = io_async_mem_5_mask; // @[AsyncQueue.scala:136:7] wire [63:0] io_async_mem_5_data_0 = io_async_mem_5_data; // @[AsyncQueue.scala:136:7] wire [2:0] io_async_mem_6_opcode_0 = io_async_mem_6_opcode; // @[AsyncQueue.scala:136:7] wire [2:0] io_async_mem_6_param_0 = io_async_mem_6_param; // @[AsyncQueue.scala:136:7] wire [3:0] io_async_mem_6_size_0 = io_async_mem_6_size; // @[AsyncQueue.scala:136:7] wire [1:0] io_async_mem_6_source_0 = io_async_mem_6_source; // @[AsyncQueue.scala:136:7] wire [31:0] io_async_mem_6_address_0 = io_async_mem_6_address; // @[AsyncQueue.scala:136:7] wire [7:0] io_async_mem_6_mask_0 = io_async_mem_6_mask; // @[AsyncQueue.scala:136:7] wire [63:0] io_async_mem_6_data_0 = io_async_mem_6_data; // @[AsyncQueue.scala:136:7] wire [2:0] io_async_mem_7_opcode_0 = io_async_mem_7_opcode; // @[AsyncQueue.scala:136:7] wire [2:0] io_async_mem_7_param_0 = io_async_mem_7_param; // @[AsyncQueue.scala:136:7] wire [3:0] io_async_mem_7_size_0 = io_async_mem_7_size; // @[AsyncQueue.scala:136:7] wire [1:0] io_async_mem_7_source_0 = io_async_mem_7_source; // @[AsyncQueue.scala:136:7] wire [31:0] io_async_mem_7_address_0 = io_async_mem_7_address; // @[AsyncQueue.scala:136:7] wire [7:0] io_async_mem_7_mask_0 = io_async_mem_7_mask; // @[AsyncQueue.scala:136:7] wire [63:0] io_async_mem_7_data_0 = io_async_mem_7_data; // @[AsyncQueue.scala:136:7] wire [3:0] io_async_widx_0 = io_async_widx; // @[AsyncQueue.scala:136:7] wire io_async_safe_widx_valid_0 = io_async_safe_widx_valid; // @[AsyncQueue.scala:136:7] wire io_async_safe_source_reset_n_0 = io_async_safe_source_reset_n; // @[AsyncQueue.scala:136:7] wire _ridx_T = reset; // @[AsyncQueue.scala:148:30] wire _valid_reg_T = reset; // @[AsyncQueue.scala:165:35] wire _ridx_reg_T = reset; // @[AsyncQueue.scala:168:34] wire _sink_valid_0_reset_T = reset; // @[AsyncQueue.scala:177:35] wire _sink_valid_1_reset_T = reset; // @[AsyncQueue.scala:178:35] wire _source_extend_reset_T = reset; // @[AsyncQueue.scala:179:35] wire _source_valid_reset_T = reset; // @[AsyncQueue.scala:180:34] wire _io_async_safe_sink_reset_n_T = reset; // @[AsyncQueue.scala:193:32] wire io_async_mem_0_corrupt = 1'h0; // @[AsyncQueue.scala:136:7] wire io_async_mem_1_corrupt = 1'h0; // @[AsyncQueue.scala:136:7] wire io_async_mem_2_corrupt = 1'h0; // @[AsyncQueue.scala:136:7] wire io_async_mem_3_corrupt = 1'h0; // @[AsyncQueue.scala:136:7] wire io_async_mem_4_corrupt = 1'h0; // @[AsyncQueue.scala:136:7] wire io_async_mem_5_corrupt = 1'h0; // @[AsyncQueue.scala:136:7] wire io_async_mem_6_corrupt = 1'h0; // @[AsyncQueue.scala:136:7] wire io_async_mem_7_corrupt = 1'h0; // @[AsyncQueue.scala:136:7] wire _io_deq_valid_T; // @[AsyncQueue.scala:166:29] wire [2:0] _io_deq_bits_WIRE_opcode; // @[SynchronizerReg.scala:211:26] wire [2:0] _io_deq_bits_WIRE_param; // @[SynchronizerReg.scala:211:26] wire [3:0] _io_deq_bits_WIRE_size; // @[SynchronizerReg.scala:211:26] wire [1:0] _io_deq_bits_WIRE_source; // @[SynchronizerReg.scala:211:26] wire [31:0] _io_deq_bits_WIRE_address; // @[SynchronizerReg.scala:211:26] wire [7:0] _io_deq_bits_WIRE_mask; // @[SynchronizerReg.scala:211:26] wire [63:0] _io_deq_bits_WIRE_data; // @[SynchronizerReg.scala:211:26] wire _io_deq_bits_WIRE_corrupt; // @[SynchronizerReg.scala:211:26] wire _io_async_safe_sink_reset_n_T_1; // @[AsyncQueue.scala:193:25] wire [2:0] io_deq_bits_opcode_0; // @[AsyncQueue.scala:136:7] wire [2:0] io_deq_bits_param_0; // @[AsyncQueue.scala:136:7] wire [3:0] io_deq_bits_size_0; // @[AsyncQueue.scala:136:7] wire [1:0] io_deq_bits_source_0; // @[AsyncQueue.scala:136:7] wire [31:0] io_deq_bits_address_0; // @[AsyncQueue.scala:136:7] wire [7:0] io_deq_bits_mask_0; // @[AsyncQueue.scala:136:7] wire [63:0] io_deq_bits_data_0; // @[AsyncQueue.scala:136:7] wire io_deq_bits_corrupt_0; // @[AsyncQueue.scala:136:7] wire io_deq_valid_0; // @[AsyncQueue.scala:136:7] wire io_async_safe_ridx_valid_0; // @[AsyncQueue.scala:136:7] wire io_async_safe_sink_reset_n_0; // @[AsyncQueue.scala:136:7] wire [3:0] io_async_ridx_0; // @[AsyncQueue.scala:136:7] wire source_ready; // @[AsyncQueue.scala:147:30] wire _ridx_T_1 = io_deq_ready_0 & io_deq_valid_0; // @[Decoupled.scala:51:35] wire _ridx_T_2 = ~source_ready; // @[AsyncQueue.scala:147:30, :148:77] wire [3:0] _ridx_incremented_T_2; // @[AsyncQueue.scala:53:23] wire [3:0] ridx_incremented; // @[AsyncQueue.scala:51:27] reg [3:0] ridx_ridx_bin; // @[AsyncQueue.scala:52:25] wire [4:0] _ridx_incremented_T = {1'h0, ridx_ridx_bin} + {4'h0, _ridx_T_1}; // @[Decoupled.scala:51:35] wire [3:0] _ridx_incremented_T_1 = _ridx_incremented_T[3:0]; // @[AsyncQueue.scala:53:43] assign _ridx_incremented_T_2 = _ridx_T_2 ? 4'h0 : _ridx_incremented_T_1; // @[AsyncQueue.scala:52:25, :53:{23,43}, :148:77] assign ridx_incremented = _ridx_incremented_T_2; // @[AsyncQueue.scala:51:27, :53:23] wire [2:0] _ridx_T_3 = ridx_incremented[3:1]; // @[AsyncQueue.scala:51:27, :54:32] wire [3:0] ridx = {ridx_incremented[3], ridx_incremented[2:0] ^ _ridx_T_3}; // @[AsyncQueue.scala:51:27, :54:{17,32}] wire [3:0] widx; // @[ShiftReg.scala:48:24] wire _valid_T = ridx != widx; // @[ShiftReg.scala:48:24] wire valid = source_ready & _valid_T; // @[AsyncQueue.scala:147:30, :150:{28,36}] wire [2:0] _index_T = ridx[2:0]; // @[AsyncQueue.scala:54:17, :156:43] wire _index_T_1 = ridx[3]; // @[AsyncQueue.scala:54:17, :156:62] wire [2:0] _index_T_2 = {_index_T_1, 2'h0}; // @[AsyncQueue.scala:156:{62,75}] wire [2:0] index = _index_T ^ _index_T_2; // @[AsyncQueue.scala:156:{43,55,75}] wire [7:0][2:0] _GEN = {{io_async_mem_7_opcode_0}, {io_async_mem_6_opcode_0}, {io_async_mem_5_opcode_0}, {io_async_mem_4_opcode_0}, {io_async_mem_3_opcode_0}, {io_async_mem_2_opcode_0}, {io_async_mem_1_opcode_0}, {io_async_mem_0_opcode_0}}; // @[SynchronizerReg.scala:209:24] wire [7:0][2:0] _GEN_0 = {{io_async_mem_7_param_0}, {io_async_mem_6_param_0}, {io_async_mem_5_param_0}, {io_async_mem_4_param_0}, {io_async_mem_3_param_0}, {io_async_mem_2_param_0}, {io_async_mem_1_param_0}, {io_async_mem_0_param_0}}; // @[SynchronizerReg.scala:209:24] wire [7:0][3:0] _GEN_1 = {{io_async_mem_7_size_0}, {io_async_mem_6_size_0}, {io_async_mem_5_size_0}, {io_async_mem_4_size_0}, {io_async_mem_3_size_0}, {io_async_mem_2_size_0}, {io_async_mem_1_size_0}, {io_async_mem_0_size_0}}; // @[SynchronizerReg.scala:209:24] wire [7:0][1:0] _GEN_2 = {{io_async_mem_7_source_0}, {io_async_mem_6_source_0}, {io_async_mem_5_source_0}, {io_async_mem_4_source_0}, {io_async_mem_3_source_0}, {io_async_mem_2_source_0}, {io_async_mem_1_source_0}, {io_async_mem_0_source_0}}; // @[SynchronizerReg.scala:209:24] wire [7:0][31:0] _GEN_3 = {{io_async_mem_7_address_0}, {io_async_mem_6_address_0}, {io_async_mem_5_address_0}, {io_async_mem_4_address_0}, {io_async_mem_3_address_0}, {io_async_mem_2_address_0}, {io_async_mem_1_address_0}, {io_async_mem_0_address_0}}; // @[SynchronizerReg.scala:209:24] wire [7:0][7:0] _GEN_4 = {{io_async_mem_7_mask_0}, {io_async_mem_6_mask_0}, {io_async_mem_5_mask_0}, {io_async_mem_4_mask_0}, {io_async_mem_3_mask_0}, {io_async_mem_2_mask_0}, {io_async_mem_1_mask_0}, {io_async_mem_0_mask_0}}; // @[SynchronizerReg.scala:209:24] wire [7:0] io_deq_bits_deq_bits_reg_io_d_lo_hi = _GEN_4[index]; // @[SynchronizerReg.scala:209:24] wire [7:0][63:0] _GEN_5 = {{io_async_mem_7_data_0}, {io_async_mem_6_data_0}, {io_async_mem_5_data_0}, {io_async_mem_4_data_0}, {io_async_mem_3_data_0}, {io_async_mem_2_data_0}, {io_async_mem_1_data_0}, {io_async_mem_0_data_0}}; // @[SynchronizerReg.scala:209:24] wire [64:0] io_deq_bits_deq_bits_reg_io_d_lo_lo = {_GEN_5[index], 1'h0}; // @[SynchronizerReg.scala:209:24] wire [72:0] io_deq_bits_deq_bits_reg_io_d_lo = {io_deq_bits_deq_bits_reg_io_d_lo_hi, io_deq_bits_deq_bits_reg_io_d_lo_lo}; // @[SynchronizerReg.scala:209:24] wire [33:0] io_deq_bits_deq_bits_reg_io_d_hi_lo = {_GEN_2[index], _GEN_3[index]}; // @[SynchronizerReg.scala:209:24] wire [5:0] io_deq_bits_deq_bits_reg_io_d_hi_hi_hi = {_GEN[index], _GEN_0[index]}; // @[SynchronizerReg.scala:209:24] wire [9:0] io_deq_bits_deq_bits_reg_io_d_hi_hi = {io_deq_bits_deq_bits_reg_io_d_hi_hi_hi, _GEN_1[index]}; // @[SynchronizerReg.scala:209:24] wire [43:0] io_deq_bits_deq_bits_reg_io_d_hi = {io_deq_bits_deq_bits_reg_io_d_hi_hi, io_deq_bits_deq_bits_reg_io_d_hi_lo}; // @[SynchronizerReg.scala:209:24] wire [116:0] _io_deq_bits_deq_bits_reg_io_d_T = {io_deq_bits_deq_bits_reg_io_d_hi, io_deq_bits_deq_bits_reg_io_d_lo}; // @[SynchronizerReg.scala:209:24] wire [2:0] _io_deq_bits_T_7; // @[SynchronizerReg.scala:211:26] assign io_deq_bits_opcode_0 = _io_deq_bits_WIRE_opcode; // @[SynchronizerReg.scala:211:26] wire [2:0] _io_deq_bits_T_6; // @[SynchronizerReg.scala:211:26] assign io_deq_bits_param_0 = _io_deq_bits_WIRE_param; // @[SynchronizerReg.scala:211:26] wire [3:0] _io_deq_bits_T_5; // @[SynchronizerReg.scala:211:26] assign io_deq_bits_size_0 = _io_deq_bits_WIRE_size; // @[SynchronizerReg.scala:211:26] wire [1:0] _io_deq_bits_T_4; // @[SynchronizerReg.scala:211:26] assign io_deq_bits_source_0 = _io_deq_bits_WIRE_source; // @[SynchronizerReg.scala:211:26] wire [31:0] _io_deq_bits_T_3; // @[SynchronizerReg.scala:211:26] assign io_deq_bits_address_0 = _io_deq_bits_WIRE_address; // @[SynchronizerReg.scala:211:26] wire [7:0] _io_deq_bits_T_2; // @[SynchronizerReg.scala:211:26] assign io_deq_bits_mask_0 = _io_deq_bits_WIRE_mask; // @[SynchronizerReg.scala:211:26] wire [63:0] _io_deq_bits_T_1; // @[SynchronizerReg.scala:211:26] assign io_deq_bits_data_0 = _io_deq_bits_WIRE_data; // @[SynchronizerReg.scala:211:26] wire _io_deq_bits_T; // @[SynchronizerReg.scala:211:26] assign io_deq_bits_corrupt_0 = _io_deq_bits_WIRE_corrupt; // @[SynchronizerReg.scala:211:26] wire [116:0] _io_deq_bits_WIRE_1; // @[SynchronizerReg.scala:211:26] assign _io_deq_bits_T = _io_deq_bits_WIRE_1[0]; // @[SynchronizerReg.scala:211:26] assign _io_deq_bits_WIRE_corrupt = _io_deq_bits_T; // @[SynchronizerReg.scala:211:26] assign _io_deq_bits_T_1 = _io_deq_bits_WIRE_1[64:1]; // @[SynchronizerReg.scala:211:26] assign _io_deq_bits_WIRE_data = _io_deq_bits_T_1; // @[SynchronizerReg.scala:211:26] assign _io_deq_bits_T_2 = _io_deq_bits_WIRE_1[72:65]; // @[SynchronizerReg.scala:211:26] assign _io_deq_bits_WIRE_mask = _io_deq_bits_T_2; // @[SynchronizerReg.scala:211:26] assign _io_deq_bits_T_3 = _io_deq_bits_WIRE_1[104:73]; // @[SynchronizerReg.scala:211:26] assign _io_deq_bits_WIRE_address = _io_deq_bits_T_3; // @[SynchronizerReg.scala:211:26] assign _io_deq_bits_T_4 = _io_deq_bits_WIRE_1[106:105]; // @[SynchronizerReg.scala:211:26] assign _io_deq_bits_WIRE_source = _io_deq_bits_T_4; // @[SynchronizerReg.scala:211:26] assign _io_deq_bits_T_5 = _io_deq_bits_WIRE_1[110:107]; // @[SynchronizerReg.scala:211:26] assign _io_deq_bits_WIRE_size = _io_deq_bits_T_5; // @[SynchronizerReg.scala:211:26] assign _io_deq_bits_T_6 = _io_deq_bits_WIRE_1[113:111]; // @[SynchronizerReg.scala:211:26] assign _io_deq_bits_WIRE_param = _io_deq_bits_T_6; // @[SynchronizerReg.scala:211:26] assign _io_deq_bits_T_7 = _io_deq_bits_WIRE_1[116:114]; // @[SynchronizerReg.scala:211:26] assign _io_deq_bits_WIRE_opcode = _io_deq_bits_T_7; // @[SynchronizerReg.scala:211:26] reg valid_reg; // @[AsyncQueue.scala:165:56] assign _io_deq_valid_T = valid_reg & source_ready; // @[AsyncQueue.scala:147:30, :165:56, :166:29] assign io_deq_valid_0 = _io_deq_valid_T; // @[AsyncQueue.scala:136:7, :166:29] reg [3:0] ridx_gray; // @[AsyncQueue.scala:168:55] assign io_async_ridx_0 = ridx_gray; // @[AsyncQueue.scala:136:7, :168:55] wire _sink_valid_0_reset_T_1 = ~io_async_safe_source_reset_n_0; // @[AsyncQueue.scala:136:7, :177:45] wire _sink_valid_0_reset_T_2 = _sink_valid_0_reset_T \| _sink_valid_0_reset_T_1; // @[AsyncQueue.scala:177:{35,42,45}] wire _sink_valid_0_reset_T_3 = _sink_valid_0_reset_T_2; // @[AsyncQueue.scala:177:{42,66}] wire _sink_valid_1_reset_T_1 = ~io_async_safe_source_reset_n_0; // @[AsyncQueue.scala:136:7, :177:45, :178:45] wire _sink_valid_1_reset_T_2 = _sink_valid_1_reset_T \| _sink_valid_1_reset_T_1; // @[AsyncQueue.scala:178:{35,42,45}] wire _sink_valid_1_reset_T_3 = _sink_valid_1_reset_T_2; // @[AsyncQueue.scala:178:{42,66}] wire _source_extend_reset_T_1 = ~io_async_safe_source_reset_n_0; // @[AsyncQueue.scala:136:7, :177:45, :179:45] wire _source_extend_reset_T_2 = _source_extend_reset_T \| _source_extend_reset_T_1; // @[AsyncQueue.scala:179:{35,42,45}] wire _source_extend_reset_T_3 = _source_extend_reset_T_2; // @[AsyncQueue.scala:179:{42,66}] assign _io_async_safe_sink_reset_n_T_1 = ~_io_async_safe_sink_reset_n_T; // @[AsyncQueue.scala:193:{25,32}] assign io_async_safe_sink_reset_n_0 = _io_async_safe_sink_reset_n_T_1; // @[AsyncQueue.scala:136:7, :193:25] always @(posedge clock or posedge _ridx_T) begin // @[AsyncQueue.scala:136:7, :148:30] if (_ridx_T) // @[AsyncQueue.scala:136:7, :148:30] ridx_ridx_bin <= 4'h0; // @[AsyncQueue.scala:52:25] else // @[AsyncQueue.scala:136:7] ridx_ridx_bin <= ridx_incremented; // @[AsyncQueue.scala:51:27, :52:25] always @(posedge, posedge) always @(posedge clock or posedge _valid_reg_T) begin // @[AsyncQueue.scala:136:7, :165:35] if (_valid_reg_T) // @[AsyncQueue.scala:136:7, :165:35] valid_reg <= 1'h0; // @[AsyncQueue.scala:165:56] else // @[AsyncQueue.scala:136:7] valid_reg <= valid; // @[AsyncQueue.scala:150:28, :165:56] always @(posedge, posedge) always @(posedge clock or posedge _ridx_reg_T) begin // @[AsyncQueue.scala:136:7, :168:34] if (_ridx_reg_T) // @[AsyncQueue.scala:136:7, :168:34] ridx_gray <= 4'h0; // @[AsyncQueue.scala:52:25, :168:55] else // @[AsyncQueue.scala:136:7] ridx_gray <= ridx; // @[AsyncQueue.scala:54:17, :168:55] always @(posedge, posedge)
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: package constellation.channel import chisel3._ import chisel3.util._ import freechips.rocketchip.diplomacy._ import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.util._ import constellation.noc.{HasNoCParams} class NoCMonitor(val cParam: ChannelParams)(implicit val p: Parameters) extends Module with HasNoCParams { val io = IO(new Bundle { val in = Input(new Channel(cParam)) }) val in_flight = RegInit(VecInit(Seq.fill(cParam.nVirtualChannels) { false.B })) for (i <- 0 until cParam.srcSpeedup) { val flit = io.in.flit(i) when (flit.valid) { when (flit.bits.head) { in_flight(flit.bits.virt_channel_id) := true.B assert (!in_flight(flit.bits.virt_channel_id), "Flit head/tail sequencing is broken") } when (flit.bits.tail) { in_flight(flit.bits.virt_channel_id) := false.B } } val possibleFlows = cParam.possibleFlows when (flit.valid && flit.bits.head) { cParam match { case n: ChannelParams => n.virtualChannelParams.zipWithIndex.foreach { case (v,i) => assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR) } case _ => assert(cParam.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR) } } } } File Types.scala: package constellation.routing import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Parameters} import constellation.noc.{HasNoCParams} import constellation.channel.{Flit} /** A representation for 1 specific virtual channel in wormhole routing * * @param src the source node * @param vc ID for the virtual channel * @param dst the destination node * @param n_vc the number of virtual channels / // BEGIN: ChannelRoutingInfo case class ChannelRoutingInfo( src: Int, dst: Int, vc: Int, n_vc: Int ) { // END: ChannelRoutingInfo require (src >= -1 && dst >= -1 && vc >= 0, s"Illegal $this") require (!(src == -1 && dst == -1), s"Illegal $this") require (vc < n_vc, s"Illegal $this") val isIngress = src == -1 val isEgress = dst == -1 } /* Represents the properties of a packet that are relevant for routing * ingressId and egressId uniquely identify a flow, but vnet and dst are used here * to simplify the implementation of routingrelations * * @param ingressId packet's source ingress point * @param egressId packet's destination egress point * @param vNet virtual subnetwork identifier * @param dst packet's destination node ID */ // BEGIN: FlowRoutingInfo case class FlowRoutingInfo( ingressId: Int, egressId: Int, vNetId: Int, ingressNode: Int, ingressNodeId: Int, egressNode: Int, egressNodeId: Int, fifo: Boolean ) { // END: FlowRoutingInfo def isFlow(f: FlowRoutingBundle): Bool = { (f.ingress_node === ingressNode.U && f.egress_node === egressNode.U && f.ingress_node_id === ingressNodeId.U && f.egress_node_id === egressNodeId.U) } def asLiteral(b: FlowRoutingBundle): BigInt = { Seq( (vNetId , b.vnet_id), (ingressNode , b.ingress_node), (ingressNodeId , b.ingress_node_id), (egressNode , b.egress_node), (egressNodeId , b.egress_node_id) ).foldLeft(0)((l, t) => { (l << t._2.getWidth) \| t._1 }) } } class FlowRoutingBundle(implicit val p: Parameters) extends Bundle with HasNoCParams { // Instead of tracking ingress/egress ID, track the physical destination id and the offset at the destination // This simplifies the routing tables val vnet_id = UInt(log2Ceil(nVirtualNetworks).W) val ingress_node = UInt(log2Ceil(nNodes).W) val ingress_node_id = UInt(log2Ceil(maxIngressesAtNode).W) val egress_node = UInt(log2Ceil(nNodes).W) val egress_node_id = UInt(log2Ceil(maxEgressesAtNode).W) }	module NoCMonitor_83( // @[Monitor.scala:11:7] input clock, // @[Monitor.scala:11:7] input reset, // @[Monitor.scala:11:7] input io_in_flit_0_valid, // @[Monitor.scala:12:14] input io_in_flit_0_bits_head, // @[Monitor.scala:12:14] input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14] input io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14] ); reg in_flight_0; // @[Monitor.scala:16:26] reg in_flight_1; // @[Monitor.scala:16:26]
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [15:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [127:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [127:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [15:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [127:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [127:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [7:0] c_first_beats1_decode = 8'h0; // @[Edges.scala:220:59] wire [7:0] c_first_beats1 = 8'h0; // @[Edges.scala:221:14] wire [7:0] _c_first_count_T = 8'h0; // @[Edges.scala:234:27] wire [7:0] c_first_count = 8'h0; // @[Edges.scala:234:25] wire [7:0] _c_first_counter_T = 8'h0; // @[Edges.scala:236:21] wire [7:0] _c_opcodes_set_T = 8'h0; // @[Monitor.scala:767:79] wire [7:0] _c_sizes_set_T = 8'h0; // @[Monitor.scala:768:77] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_31 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_37 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_43 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_49 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:57:20] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [7:0] c_first_counter1 = 8'hFF; // @[Edges.scala:230:28] wire [8:0] _c_first_counter1_T = 9'h1FF; // @[Edges.scala:230:28] wire [127:0] _c_first_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_first_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_first_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_first_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_set_wo_ready_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_set_wo_ready_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_opcodes_set_interm_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_opcodes_set_interm_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_sizes_set_interm_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_sizes_set_interm_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_opcodes_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_opcodes_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_sizes_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_sizes_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_probe_ack_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_probe_ack_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_probe_ack_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_probe_ack_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_4_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_5_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_set_wo_ready_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_wo_ready_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_opcodes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [4:0] _c_opcodes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_4_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_5_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [259:0] _c_sizes_set_T_1 = 260'h0; // @[Monitor.scala:768:52] wire [258:0] _c_opcodes_set_T_1 = 259'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [31:0] _c_set_wo_ready_T = 32'h1; // @[OneHot.scala:58:35] wire [31:0] _c_set_T = 32'h1; // @[OneHot.scala:58:35] wire [135:0] c_sizes_set = 136'h0; // @[Monitor.scala:741:34] wire [67:0] c_opcodes_set = 68'h0; // @[Monitor.scala:740:34] wire [16:0] c_set = 17'h0; // @[Monitor.scala:738:34] wire [16:0] c_set_wo_ready = 17'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [4:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 5'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _source_ok_T_1 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_7 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_13 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_19 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 3'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 3'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 3'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 3'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_26 = _source_ok_T_25 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_27 = _source_ok_T_26 \| _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_27 \| _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire [3:0] mask_sizeOH = {_mask_sizeOH_T_2[3:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_sub_0_1 = \|(io_in_a_bits_size_0[3:2]); // @[Misc.scala:206:21] wire mask_sub_sub_sub_size = mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_sub_bit = io_in_a_bits_address_0[3]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_1_2 = mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_nbit = ~mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_0_2 = mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_acc_T = mask_sub_sub_sub_size & mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_0_1 \| _mask_sub_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_size & mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_0_1 \| _mask_sub_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_1_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_2_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size & mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_2_1 = mask_sub_sub_sub_1_1 \| _mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_3_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size & mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_3_1 = mask_sub_sub_sub_1_1 \| _mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_4_2 = mask_sub_sub_2_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_4 = mask_sub_size & mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_4_1 = mask_sub_sub_2_1 \| _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_5_2 = mask_sub_sub_2_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_5 = mask_sub_size & mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_5_1 = mask_sub_sub_2_1 \| _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_6_2 = mask_sub_sub_3_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_6 = mask_sub_size & mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_6_1 = mask_sub_sub_3_1 \| _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_7_2 = mask_sub_sub_3_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_7 = mask_sub_size & mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_7_1 = mask_sub_sub_3_1 \| _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_eq_8 = mask_sub_4_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_size & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_8 = mask_sub_4_1 \| _mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_eq_9 = mask_sub_4_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_size & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_9 = mask_sub_4_1 \| _mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_eq_10 = mask_sub_5_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_size & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_10 = mask_sub_5_1 \| _mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_eq_11 = mask_sub_5_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_size & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_11 = mask_sub_5_1 \| _mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_eq_12 = mask_sub_6_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_size & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_12 = mask_sub_6_1 \| _mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_eq_13 = mask_sub_6_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_size & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_13 = mask_sub_6_1 \| _mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_eq_14 = mask_sub_7_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_size & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_14 = mask_sub_7_1 \| _mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_eq_15 = mask_sub_7_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_size & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_15 = mask_sub_7_1 \| _mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_lo = {mask_lo_lo_hi, mask_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_hi = {mask_lo_hi_hi, mask_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_lo_hi = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_lo = {mask_hi_lo_hi, mask_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_hi = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_hi = {mask_hi_hi_hi, mask_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [15:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_28 = io_in_d_bits_source_0 == 5'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_28; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _source_ok_T_29 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_35 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_41 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_47 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire _source_ok_T_30 = _source_ok_T_29 == 3'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_32 = _source_ok_T_30; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_34; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_36 = _source_ok_T_35 == 3'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_38 = _source_ok_T_36; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_40; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_42 = _source_ok_T_41 == 3'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_44 = _source_ok_T_42; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_46; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_48 = _source_ok_T_47 == 3'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_50 = _source_ok_T_48; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_52; // @[Parameters.scala:1138:31] wire _source_ok_T_53 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_54 = _source_ok_T_53 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_55 = _source_ok_T_54 \| _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_55 \| _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _T_1502 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1502; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1502; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [7:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [7:0] a_first_counter; // @[Edges.scala:229:27] wire [8:0] _a_first_counter1_T = {1'h0, a_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] a_first_counter1 = _a_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [7:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [4:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1575 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1575; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1575; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1575; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [7:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T = {1'h0, d_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1 = _d_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [4:0] source_1; // @[Monitor.scala:541:22] reg [6:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [16:0] inflight; // @[Monitor.scala:614:27] reg [67:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [135:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [7:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [7:0] a_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] a_first_counter1_1 = _a_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [7:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_1 = _d_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [16:0] a_set; // @[Monitor.scala:626:34] wire [16:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [67:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [135:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [7:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [7:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [7:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [7:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [7:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [67:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [67:0] _a_opcode_lookup_T_6 = {64'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [67:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[67:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [7:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [7:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [7:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [7:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [7:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [135:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [135:0] _a_size_lookup_T_6 = {128'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [135:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[135:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [31:0] _GEN_3 = 32'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [31:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [31:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[16:0] : 17'h0; // @[OneHot.scala:58:35] wire _T_1428 = _T_1502 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1428 ? _a_set_T[16:0] : 17'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1428 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1428 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [7:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [258:0] _a_opcodes_set_T_1 = {255'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1428 ? _a_opcodes_set_T_1[67:0] : 68'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [7:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [259:0] _a_sizes_set_T_1 = {255'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1428 ? _a_sizes_set_T_1[135:0] : 136'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [16:0] d_clr; // @[Monitor.scala:664:34] wire [16:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [67:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [135:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1474 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [31:0] _GEN_5 = 32'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1474 & ~d_release_ack ? _d_clr_wo_ready_T[16:0] : 17'h0; // @[OneHot.scala:58:35] wire _T_1443 = _T_1575 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1443 ? _d_clr_T[16:0] : 17'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_5 = 271'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1443 ? _d_opcodes_clr_T_5[67:0] : 68'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [270:0] _d_sizes_clr_T_5 = 271'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1443 ? _d_sizes_clr_T_5[135:0] : 136'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [16:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [16:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [16:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [67:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [67:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [67:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [135:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [135:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [135:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [16:0] inflight_1; // @[Monitor.scala:726:35] wire [16:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [67:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [67:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [135:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [135:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_2; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_2 = _d_first_counter1_T_2[7:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [67:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [67:0] _c_opcode_lookup_T_6 = {64'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [67:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[67:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [135:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [135:0] _c_size_lookup_T_6 = {128'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [135:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[135:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [16:0] d_clr_1; // @[Monitor.scala:774:34] wire [16:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [67:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [135:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1546 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1546 & d_release_ack_1 ? _d_clr_wo_ready_T_1[16:0] : 17'h0; // @[OneHot.scala:58:35] wire _T_1528 = _T_1575 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1528 ? _d_clr_T_1[16:0] : 17'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_11 = 271'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1528 ? _d_opcodes_clr_T_11[67:0] : 68'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [270:0] _d_sizes_clr_T_11 = 271'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1528 ? _d_sizes_clr_T_11[135:0] : 136'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 5'h0; // @[Monitor.scala:36:7, :795:113] wire [16:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [16:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [67:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [67:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [135:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [135:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands / class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B \|\| ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B \|\| ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def (t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def (t: UInt) = self t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros \| ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def (t: SInt) = self t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros \| ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid \|\| output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid \|\| output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid \|\| output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def (t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def (t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }	module MacUnit_56( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [19:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54] assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Serdes.scala: package testchipip.serdes import chisel3._ import chisel3.util._ import freechips.rocketchip.diplomacy._ import org.chipsalliance.cde.config._ class GenericSerializer[T <: Data](t: T, flitWidth: Int) extends Module { override def desiredName = s"GenericSerializer_${t.typeName}w${t.getWidth}_f${flitWidth}" val io = IO(new Bundle { val in = Flipped(Decoupled(t)) val out = Decoupled(new Flit(flitWidth)) val busy = Output(Bool()) }) val dataBits = t.getWidth.max(flitWidth) val dataBeats = (dataBits - 1) / flitWidth + 1 require(dataBeats >= 1) val data = Reg(Vec(dataBeats, UInt(flitWidth.W))) val beat = RegInit(0.U(log2Ceil(dataBeats).W)) io.in.ready := io.out.ready && beat === 0.U io.out.valid := io.in.valid \|\| beat =/= 0.U io.out.bits.flit := Mux(beat === 0.U, io.in.bits.asUInt, data(beat)) when (io.out.fire) { beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U) when (beat === 0.U) { data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(flitWidth.W))) data(0) := DontCare // unused, DCE this } } io.busy := io.out.valid } class GenericDeserializer[T <: Data](t: T, flitWidth: Int) extends Module { override def desiredName = s"GenericDeserializer_${t.typeName}w${t.getWidth}_f${flitWidth}" val io = IO(new Bundle { val in = Flipped(Decoupled(new Flit(flitWidth))) val out = Decoupled(t) val busy = Output(Bool()) }) val dataBits = t.getWidth.max(flitWidth) val dataBeats = (dataBits - 1) / flitWidth + 1 require(dataBeats >= 1) val data = Reg(Vec(dataBeats-1, UInt(flitWidth.W))) val beat = RegInit(0.U(log2Ceil(dataBeats).W)) io.in.ready := io.out.ready \|\| beat =/= (dataBeats-1).U io.out.valid := io.in.valid && beat === (dataBeats-1).U io.out.bits := (if (dataBeats == 1) { io.in.bits.flit.asTypeOf(t) } else { Cat(io.in.bits.flit, data.asUInt).asTypeOf(t) }) when (io.in.fire) { beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U) if (dataBeats > 1) { when (beat =/= (dataBeats-1).U) { data(beat(log2Ceil(dataBeats-1)-1,0)) := io.in.bits.flit } } } io.busy := beat =/= 0.U } class FlitToPhit(flitWidth: Int, phitWidth: Int) extends Module { override def desiredName = s"FlitToPhit_f${flitWidth}_p${phitWidth}" val io = IO(new Bundle { val in = Flipped(Decoupled(new Flit(flitWidth))) val out = Decoupled(new Phit(phitWidth)) }) require(flitWidth >= phitWidth) val dataBeats = (flitWidth - 1) / phitWidth + 1 val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W))) val beat = RegInit(0.U(log2Ceil(dataBeats).W)) io.in.ready := io.out.ready && beat === 0.U io.out.valid := io.in.valid \|\| beat =/= 0.U io.out.bits.phit := (if (dataBeats == 1) io.in.bits.flit else Mux(beat === 0.U, io.in.bits.flit, data(beat-1.U))) when (io.out.fire) { beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U) when (beat === 0.U) { data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(phitWidth.W))).tail } } } object FlitToPhit { def apply(flit: DecoupledIO[Flit], phitWidth: Int): DecoupledIO[Phit] = { val flit2phit = Module(new FlitToPhit(flit.bits.flitWidth, phitWidth)) flit2phit.io.in <> flit flit2phit.io.out } } class PhitToFlit(flitWidth: Int, phitWidth: Int) extends Module { override def desiredName = s"PhitToFlit_p${phitWidth}_f${flitWidth}" val io = IO(new Bundle { val in = Flipped(Decoupled(new Phit(phitWidth))) val out = Decoupled(new Flit(flitWidth)) }) require(flitWidth >= phitWidth) val dataBeats = (flitWidth - 1) / phitWidth + 1 val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W))) val beat = RegInit(0.U(log2Ceil(dataBeats).W)) io.in.ready := io.out.ready \|\| beat =/= (dataBeats-1).U io.out.valid := io.in.valid && beat === (dataBeats-1).U io.out.bits.flit := (if (dataBeats == 1) io.in.bits.phit else Cat(io.in.bits.phit, data.asUInt)) when (io.in.fire) { beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U) if (dataBeats > 1) { when (beat =/= (dataBeats-1).U) { data(beat) := io.in.bits.phit } } } } object PhitToFlit { def apply(phit: DecoupledIO[Phit], flitWidth: Int): DecoupledIO[Flit] = { val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth)) phit2flit.io.in <> phit phit2flit.io.out } def apply(phit: ValidIO[Phit], flitWidth: Int): ValidIO[Flit] = { val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth)) phit2flit.io.in.valid := phit.valid phit2flit.io.in.bits := phit.bits when (phit.valid) { assert(phit2flit.io.in.ready) } val out = Wire(Valid(new Flit(flitWidth))) out.valid := phit2flit.io.out.valid out.bits := phit2flit.io.out.bits phit2flit.io.out.ready := true.B out } } class PhitArbiter(phitWidth: Int, flitWidth: Int, channels: Int) extends Module { override def desiredName = s"PhitArbiter_p${phitWidth}_f${flitWidth}_n${channels}" val io = IO(new Bundle { val in = Flipped(Vec(channels, Decoupled(new Phit(phitWidth)))) val out = Decoupled(new Phit(phitWidth)) }) if (channels == 1) { io.out <> io.in(0) } else { val headerWidth = log2Ceil(channels) val headerBeats = (headerWidth - 1) / phitWidth + 1 val flitBeats = (flitWidth - 1) / phitWidth + 1 val beats = headerBeats + flitBeats val beat = RegInit(0.U(log2Ceil(beats).W)) val chosen_reg = Reg(UInt(headerWidth.W)) val chosen_prio = PriorityEncoder(io.in.map(_.valid)) val chosen = Mux(beat === 0.U, chosen_prio, chosen_reg) val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0) io.out.valid := VecInit(io.in.map(_.valid))(chosen) io.out.bits.phit := Mux(beat < headerBeats.U, chosen.asTypeOf(Vec(headerBeats, UInt(phitWidth.W)))(header_idx), VecInit(io.in.map(_.bits.phit))(chosen)) for (i <- 0 until channels) { io.in(i).ready := io.out.ready && beat >= headerBeats.U && chosen_reg === i.U } when (io.out.fire) { beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U) when (beat === 0.U) { chosen_reg := chosen_prio } } } } class PhitDemux(phitWidth: Int, flitWidth: Int, channels: Int) extends Module { override def desiredName = s"PhitDemux_p${phitWidth}_f${flitWidth}_n${channels}" val io = IO(new Bundle { val in = Flipped(Decoupled(new Phit(phitWidth))) val out = Vec(channels, Decoupled(new Phit(phitWidth))) }) if (channels == 1) { io.out(0) <> io.in } else { val headerWidth = log2Ceil(channels) val headerBeats = (headerWidth - 1) / phitWidth + 1 val flitBeats = (flitWidth - 1) / phitWidth + 1 val beats = headerBeats + flitBeats val beat = RegInit(0.U(log2Ceil(beats).W)) val channel_vec = Reg(Vec(headerBeats, UInt(phitWidth.W))) val channel = channel_vec.asUInt(log2Ceil(channels)-1,0) val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0) io.in.ready := beat < headerBeats.U \|\| VecInit(io.out.map(_.ready))(channel) for (c <- 0 until channels) { io.out(c).valid := io.in.valid && beat >= headerBeats.U && channel === c.U io.out(c).bits.phit := io.in.bits.phit } when (io.in.fire) { beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U) when (beat < headerBeats.U) { channel_vec(header_idx) := io.in.bits.phit } } } } class DecoupledFlitToCreditedFlit(flitWidth: Int, bufferSz: Int) extends Module { override def desiredName = s"DecoupledFlitToCreditedFlit_f${flitWidth}_b${bufferSz}" val io = IO(new Bundle { val in = Flipped(Decoupled(new Flit(flitWidth))) val out = Decoupled(new Flit(flitWidth)) val credit = Flipped(Decoupled(new Flit(flitWidth))) }) val creditWidth = log2Ceil(bufferSz) require(creditWidth <= flitWidth) val credits = RegInit(0.U((creditWidth+1).W)) val credit_incr = io.out.fire val credit_decr = io.credit.fire when (credit_incr \|\| credit_decr) { credits := credits + credit_incr - Mux(io.credit.valid, io.credit.bits.flit +& 1.U, 0.U) } io.out.valid := io.in.valid && credits < bufferSz.U io.out.bits.flit := io.in.bits.flit io.in.ready := io.out.ready && credits < bufferSz.U io.credit.ready := true.B } class CreditedFlitToDecoupledFlit(flitWidth: Int, bufferSz: Int) extends Module { override def desiredName = s"CreditedFlitToDecoupledFlit_f${flitWidth}_b${bufferSz}" val io = IO(new Bundle { val in = Flipped(Decoupled(new Flit(flitWidth))) val out = Decoupled(new Flit(flitWidth)) val credit = Decoupled(new Flit(flitWidth)) }) val creditWidth = log2Ceil(bufferSz) require(creditWidth <= flitWidth) val buffer = Module(new Queue(new Flit(flitWidth), bufferSz)) val credits = RegInit(0.U((creditWidth+1).W)) val credit_incr = buffer.io.deq.fire val credit_decr = io.credit.fire when (credit_incr \|\| credit_decr) { credits := credit_incr + Mux(credit_decr, 0.U, credits) } buffer.io.enq.valid := io.in.valid buffer.io.enq.bits := io.in.bits io.in.ready := true.B when (io.in.valid) { assert(buffer.io.enq.ready) } io.out <> buffer.io.deq io.credit.valid := credits =/= 0.U io.credit.bits.flit := credits - 1.U }	module FlitToPhit_f32_p32_6( // @[Serdes.scala:71:7] input clock, // @[Serdes.scala:71:7] input reset, // @[Serdes.scala:71:7] output io_in_ready, // @[Serdes.scala:73:14] input io_in_valid, // @[Serdes.scala:73:14] input [31:0] io_in_bits_flit, // @[Serdes.scala:73:14] input io_out_ready, // @[Serdes.scala:73:14] output io_out_valid, // @[Serdes.scala:73:14] output [31:0] io_out_bits_phit // @[Serdes.scala:73:14] ); wire io_in_valid_0 = io_in_valid; // @[Serdes.scala:71:7] wire [31:0] io_in_bits_flit_0 = io_in_bits_flit; // @[Serdes.scala:71:7] wire io_out_ready_0 = io_out_ready; // @[Serdes.scala:71:7] wire [1:0] _beat_T_1 = 2'h1; // @[Serdes.scala:88:53] wire _io_in_ready_T = 1'h1; // @[Serdes.scala:83:39] wire _beat_T = 1'h1; // @[Serdes.scala:88:22] wire _beat_T_2 = 1'h1; // @[Serdes.scala:88:53] wire _io_in_ready_T_1; // @[Serdes.scala:83:31] wire _io_out_valid_T = 1'h0; // @[Serdes.scala:84:39] wire _beat_T_3 = 1'h0; // @[Serdes.scala:88:16] wire _io_out_valid_T_1 = io_in_valid_0; // @[Serdes.scala:71:7, :84:31] wire [31:0] io_out_bits_phit_0 = io_in_bits_flit_0; // @[Serdes.scala:71:7] assign _io_in_ready_T_1 = io_out_ready_0; // @[Serdes.scala:71:7, :83:31] wire io_in_ready_0; // @[Serdes.scala:71:7] wire io_out_valid_0; // @[Serdes.scala:71:7] assign io_in_ready_0 = _io_in_ready_T_1; // @[Serdes.scala:71:7, :83:31] assign io_out_valid_0 = _io_out_valid_T_1; // @[Serdes.scala:71:7, :84:31] assign io_in_ready = io_in_ready_0; // @[Serdes.scala:71:7] assign io_out_valid = io_out_valid_0; // @[Serdes.scala:71:7] assign io_out_bits_phit = io_out_bits_phit_0; // @[Serdes.scala:71:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerShiftReg_w1_d3_i0_115( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_191 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ /** Implements the same interface as chisel3.util.Queue, but uses a shift * register internally. It is less energy efficient whenever the queue * has more than one entry populated, but is faster on the dequeue side. * It is efficient for usually-empty flow-through queues. */ class ShiftQueue[T <: Data](gen: T, val entries: Int, pipe: Boolean = false, flow: Boolean = false) extends Module { val io = IO(new QueueIO(gen, entries) { val mask = Output(UInt(entries.W)) }) private val valid = RegInit(VecInit(Seq.fill(entries) { false.B })) private val elts = Reg(Vec(entries, gen)) for (i <- 0 until entries) { def paddedValid(i: Int) = if (i == -1) true.B else if (i == entries) false.B else valid(i) val wdata = if (i == entries-1) io.enq.bits else Mux(valid(i+1), elts(i+1), io.enq.bits) val wen = Mux(io.deq.ready, paddedValid(i+1) \|\| io.enq.fire && ((i == 0 && !flow).B \|\| valid(i)), io.enq.fire && paddedValid(i-1) && !valid(i)) when (wen) { elts(i) := wdata } valid(i) := Mux(io.deq.ready, paddedValid(i+1) \|\| io.enq.fire && ((i == 0 && !flow).B \|\| valid(i)), io.enq.fire && paddedValid(i-1) \|\| valid(i)) } io.enq.ready := !valid(entries-1) io.deq.valid := valid(0) io.deq.bits := elts.head if (flow) { when (io.enq.valid) { io.deq.valid := true.B } when (!valid(0)) { io.deq.bits := io.enq.bits } } if (pipe) { when (io.deq.ready) { io.enq.ready := true.B } } io.mask := valid.asUInt io.count := PopCount(io.mask) } object ShiftQueue { def apply[T <: Data](enq: DecoupledIO[T], entries: Int = 2, pipe: Boolean = false, flow: Boolean = false): DecoupledIO[T] = { val q = Module(new ShiftQueue(enq.bits.cloneType, entries, pipe, flow)) q.io.enq <> enq q.io.deq } }	module ShiftQueue( // @[ShiftQueue.scala:12:7] input clock, // @[ShiftQueue.scala:12:7] input reset, // @[ShiftQueue.scala:12:7] output io_enq_ready, // @[ShiftQueue.scala:17:14] input io_enq_valid, // @[ShiftQueue.scala:17:14] input [1:0] io_enq_bits_btb_cfiType, // @[ShiftQueue.scala:17:14] input [1:0] io_enq_bits_btb_mask, // @[ShiftQueue.scala:17:14] input io_enq_bits_btb_bridx, // @[ShiftQueue.scala:17:14] input [31:0] io_enq_bits_btb_target, // @[ShiftQueue.scala:17:14] input io_enq_bits_btb_entry, // @[ShiftQueue.scala:17:14] input [7:0] io_enq_bits_btb_bht_history, // @[ShiftQueue.scala:17:14] input io_enq_bits_btb_bht_value, // @[ShiftQueue.scala:17:14] input [31:0] io_enq_bits_pc, // @[ShiftQueue.scala:17:14] input [31:0] io_enq_bits_data, // @[ShiftQueue.scala:17:14] input [1:0] io_enq_bits_mask, // @[ShiftQueue.scala:17:14] input io_enq_bits_xcpt_pf_inst, // @[ShiftQueue.scala:17:14] input io_enq_bits_xcpt_ae_inst, // @[ShiftQueue.scala:17:14] input io_enq_bits_replay, // @[ShiftQueue.scala:17:14] input io_deq_ready, // @[ShiftQueue.scala:17:14] output io_deq_valid, // @[ShiftQueue.scala:17:14] output [1:0] io_deq_bits_btb_cfiType, // @[ShiftQueue.scala:17:14] output io_deq_bits_btb_taken, // @[ShiftQueue.scala:17:14] output [1:0] io_deq_bits_btb_mask, // @[ShiftQueue.scala:17:14] output io_deq_bits_btb_bridx, // @[ShiftQueue.scala:17:14] output [31:0] io_deq_bits_btb_target, // @[ShiftQueue.scala:17:14] output io_deq_bits_btb_entry, // @[ShiftQueue.scala:17:14] output [7:0] io_deq_bits_btb_bht_history, // @[ShiftQueue.scala:17:14] output io_deq_bits_btb_bht_value, // @[ShiftQueue.scala:17:14] output [31:0] io_deq_bits_pc, // @[ShiftQueue.scala:17:14] output [31:0] io_deq_bits_data, // @[ShiftQueue.scala:17:14] output [1:0] io_deq_bits_mask, // @[ShiftQueue.scala:17:14] output io_deq_bits_xcpt_pf_inst, // @[ShiftQueue.scala:17:14] output io_deq_bits_xcpt_gf_inst, // @[ShiftQueue.scala:17:14] output io_deq_bits_xcpt_ae_inst, // @[ShiftQueue.scala:17:14] output io_deq_bits_replay, // @[ShiftQueue.scala:17:14] output [4:0] io_mask // @[ShiftQueue.scala:17:14] ); wire io_enq_valid_0 = io_enq_valid; // @[ShiftQueue.scala:12:7] wire [1:0] io_enq_bits_btb_cfiType_0 = io_enq_bits_btb_cfiType; // @[ShiftQueue.scala:12:7] wire [1:0] io_enq_bits_btb_mask_0 = io_enq_bits_btb_mask; // @[ShiftQueue.scala:12:7] wire io_enq_bits_btb_bridx_0 = io_enq_bits_btb_bridx; // @[ShiftQueue.scala:12:7] wire [31:0] io_enq_bits_btb_target_0 = io_enq_bits_btb_target; // @[ShiftQueue.scala:12:7] wire io_enq_bits_btb_entry_0 = io_enq_bits_btb_entry; // @[ShiftQueue.scala:12:7] wire [7:0] io_enq_bits_btb_bht_history_0 = io_enq_bits_btb_bht_history; // @[ShiftQueue.scala:12:7] wire io_enq_bits_btb_bht_value_0 = io_enq_bits_btb_bht_value; // @[ShiftQueue.scala:12:7] wire [31:0] io_enq_bits_pc_0 = io_enq_bits_pc; // @[ShiftQueue.scala:12:7] wire [31:0] io_enq_bits_data_0 = io_enq_bits_data; // @[ShiftQueue.scala:12:7] wire [1:0] io_enq_bits_mask_0 = io_enq_bits_mask; // @[ShiftQueue.scala:12:7] wire io_enq_bits_xcpt_pf_inst_0 = io_enq_bits_xcpt_pf_inst; // @[ShiftQueue.scala:12:7] wire io_enq_bits_xcpt_ae_inst_0 = io_enq_bits_xcpt_ae_inst; // @[ShiftQueue.scala:12:7] wire io_enq_bits_replay_0 = io_enq_bits_replay; // @[ShiftQueue.scala:12:7] wire io_deq_ready_0 = io_deq_ready; // @[ShiftQueue.scala:12:7] wire io_enq_bits_btb_taken = 1'h0; // @[ShiftQueue.scala:12:7] wire io_enq_bits_xcpt_gf_inst = 1'h0; // @[ShiftQueue.scala:12:7] wire _valid_WIRE_0 = 1'h0; // @[ShiftQueue.scala:21:38] wire _valid_WIRE_1 = 1'h0; // @[ShiftQueue.scala:21:38] wire _valid_WIRE_2 = 1'h0; // @[ShiftQueue.scala:21:38] wire _valid_WIRE_3 = 1'h0; // @[ShiftQueue.scala:21:38] wire _valid_WIRE_4 = 1'h0; // @[ShiftQueue.scala:21:38] wire wdata_3_btb_taken = 1'h0; // @[ShiftQueue.scala:27:57] wire _io_enq_ready_T; // @[ShiftQueue.scala:40:19] wire [2:0] _io_count_T_12; // @[ShiftQueue.scala:54:23] wire [4:0] _io_mask_T; // @[ShiftQueue.scala:53:20] wire io_enq_ready_0; // @[ShiftQueue.scala:12:7] wire [7:0] io_deq_bits_btb_bht_history_0; // @[ShiftQueue.scala:12:7] wire io_deq_bits_btb_bht_value_0; // @[ShiftQueue.scala:12:7] wire [1:0] io_deq_bits_btb_cfiType_0; // @[ShiftQueue.scala:12:7] wire io_deq_bits_btb_taken_0; // @[ShiftQueue.scala:12:7] wire [1:0] io_deq_bits_btb_mask_0; // @[ShiftQueue.scala:12:7] wire io_deq_bits_btb_bridx_0; // @[ShiftQueue.scala:12:7] wire [31:0] io_deq_bits_btb_target_0; // @[ShiftQueue.scala:12:7] wire io_deq_bits_btb_entry_0; // @[ShiftQueue.scala:12:7] wire io_deq_bits_xcpt_pf_inst_0; // @[ShiftQueue.scala:12:7] wire io_deq_bits_xcpt_gf_inst_0; // @[ShiftQueue.scala:12:7] wire io_deq_bits_xcpt_ae_inst_0; // @[ShiftQueue.scala:12:7] wire [31:0] io_deq_bits_pc_0; // @[ShiftQueue.scala:12:7] wire [31:0] io_deq_bits_data_0; // @[ShiftQueue.scala:12:7] wire [1:0] io_deq_bits_mask_0; // @[ShiftQueue.scala:12:7] wire io_deq_bits_replay_0; // @[ShiftQueue.scala:12:7] wire io_deq_valid_0; // @[ShiftQueue.scala:12:7] wire [2:0] io_count; // @[ShiftQueue.scala:12:7] wire [4:0] io_mask_0; // @[ShiftQueue.scala:12:7] reg valid_0; // @[ShiftQueue.scala:21:30] wire _wen_T_1 = valid_0; // @[ShiftQueue.scala:21:30, :30:67] wire _valid_0_T_1 = valid_0; // @[ShiftQueue.scala:21:30, :36:67] reg valid_1; // @[ShiftQueue.scala:21:30] wire _wen_T_9 = valid_1; // @[ShiftQueue.scala:21:30, :30:67] wire _valid_1_T_1 = valid_1; // @[ShiftQueue.scala:21:30, :36:67] reg valid_2; // @[ShiftQueue.scala:21:30] wire _wen_T_17 = valid_2; // @[ShiftQueue.scala:21:30, :30:67] wire _valid_2_T_1 = valid_2; // @[ShiftQueue.scala:21:30, :36:67] reg valid_3; // @[ShiftQueue.scala:21:30] wire _wen_T_25 = valid_3; // @[ShiftQueue.scala:21:30, :30:67] wire _valid_3_T_1 = valid_3; // @[ShiftQueue.scala:21:30, :36:67] reg valid_4; // @[ShiftQueue.scala:21:30] wire _wen_T_33 = valid_4; // @[ShiftQueue.scala:21:30, :30:67] wire _valid_4_T_1 = valid_4; // @[ShiftQueue.scala:21:30, :36:67] reg [1:0] elts_0_btb_cfiType; // @[ShiftQueue.scala:22:25] reg elts_0_btb_taken; // @[ShiftQueue.scala:22:25] reg [1:0] elts_0_btb_mask; // @[ShiftQueue.scala:22:25] reg elts_0_btb_bridx; // @[ShiftQueue.scala:22:25] reg [31:0] elts_0_btb_target; // @[ShiftQueue.scala:22:25] reg elts_0_btb_entry; // @[ShiftQueue.scala:22:25] reg [7:0] elts_0_btb_bht_history; // @[ShiftQueue.scala:22:25] reg elts_0_btb_bht_value; // @[ShiftQueue.scala:22:25] reg [31:0] elts_0_pc; // @[ShiftQueue.scala:22:25] reg [31:0] elts_0_data; // @[ShiftQueue.scala:22:25] reg [1:0] elts_0_mask; // @[ShiftQueue.scala:22:25] reg elts_0_xcpt_pf_inst; // @[ShiftQueue.scala:22:25] reg elts_0_xcpt_gf_inst; // @[ShiftQueue.scala:22:25] reg elts_0_xcpt_ae_inst; // @[ShiftQueue.scala:22:25] reg elts_0_replay; // @[ShiftQueue.scala:22:25] reg [1:0] elts_1_btb_cfiType; // @[ShiftQueue.scala:22:25] reg elts_1_btb_taken; // @[ShiftQueue.scala:22:25] reg [1:0] elts_1_btb_mask; // @[ShiftQueue.scala:22:25] reg elts_1_btb_bridx; // @[ShiftQueue.scala:22:25] reg [31:0] elts_1_btb_target; // @[ShiftQueue.scala:22:25] reg elts_1_btb_entry; // @[ShiftQueue.scala:22:25] reg [7:0] elts_1_btb_bht_history; // @[ShiftQueue.scala:22:25] reg elts_1_btb_bht_value; // @[ShiftQueue.scala:22:25] reg [31:0] elts_1_pc; // @[ShiftQueue.scala:22:25] reg [31:0] elts_1_data; // @[ShiftQueue.scala:22:25] reg [1:0] elts_1_mask; // @[ShiftQueue.scala:22:25] reg elts_1_xcpt_pf_inst; // @[ShiftQueue.scala:22:25] reg elts_1_xcpt_gf_inst; // @[ShiftQueue.scala:22:25] reg elts_1_xcpt_ae_inst; // @[ShiftQueue.scala:22:25] reg elts_1_replay; // @[ShiftQueue.scala:22:25] reg [1:0] elts_2_btb_cfiType; // @[ShiftQueue.scala:22:25] reg elts_2_btb_taken; // @[ShiftQueue.scala:22:25] reg [1:0] elts_2_btb_mask; // @[ShiftQueue.scala:22:25] reg elts_2_btb_bridx; // @[ShiftQueue.scala:22:25] reg [31:0] elts_2_btb_target; // @[ShiftQueue.scala:22:25] reg elts_2_btb_entry; // @[ShiftQueue.scala:22:25] reg [7:0] elts_2_btb_bht_history; // @[ShiftQueue.scala:22:25] reg elts_2_btb_bht_value; // @[ShiftQueue.scala:22:25] reg [31:0] elts_2_pc; // @[ShiftQueue.scala:22:25] reg [31:0] elts_2_data; // @[ShiftQueue.scala:22:25] reg [1:0] elts_2_mask; // @[ShiftQueue.scala:22:25] reg elts_2_xcpt_pf_inst; // @[ShiftQueue.scala:22:25] reg elts_2_xcpt_gf_inst; // @[ShiftQueue.scala:22:25] reg elts_2_xcpt_ae_inst; // @[ShiftQueue.scala:22:25] reg elts_2_replay; // @[ShiftQueue.scala:22:25] reg [1:0] elts_3_btb_cfiType; // @[ShiftQueue.scala:22:25] reg elts_3_btb_taken; // @[ShiftQueue.scala:22:25] reg [1:0] elts_3_btb_mask; // @[ShiftQueue.scala:22:25] reg elts_3_btb_bridx; // @[ShiftQueue.scala:22:25] reg [31:0] elts_3_btb_target; // @[ShiftQueue.scala:22:25] reg elts_3_btb_entry; // @[ShiftQueue.scala:22:25] reg [7:0] elts_3_btb_bht_history; // @[ShiftQueue.scala:22:25] reg elts_3_btb_bht_value; // @[ShiftQueue.scala:22:25] reg [31:0] elts_3_pc; // @[ShiftQueue.scala:22:25] reg [31:0] elts_3_data; // @[ShiftQueue.scala:22:25] reg [1:0] elts_3_mask; // @[ShiftQueue.scala:22:25] reg elts_3_xcpt_pf_inst; // @[ShiftQueue.scala:22:25] reg elts_3_xcpt_gf_inst; // @[ShiftQueue.scala:22:25] reg elts_3_xcpt_ae_inst; // @[ShiftQueue.scala:22:25] reg elts_3_replay; // @[ShiftQueue.scala:22:25] reg [1:0] elts_4_btb_cfiType; // @[ShiftQueue.scala:22:25] reg [1:0] elts_4_btb_mask; // @[ShiftQueue.scala:22:25] reg elts_4_btb_bridx; // @[ShiftQueue.scala:22:25] reg [31:0] elts_4_btb_target; // @[ShiftQueue.scala:22:25] reg elts_4_btb_entry; // @[ShiftQueue.scala:22:25] reg [7:0] elts_4_btb_bht_history; // @[ShiftQueue.scala:22:25] reg elts_4_btb_bht_value; // @[ShiftQueue.scala:22:25] reg [31:0] elts_4_pc; // @[ShiftQueue.scala:22:25] reg [31:0] elts_4_data; // @[ShiftQueue.scala:22:25] reg [1:0] elts_4_mask; // @[ShiftQueue.scala:22:25] reg elts_4_xcpt_pf_inst; // @[ShiftQueue.scala:22:25] reg elts_4_xcpt_gf_inst; // @[ShiftQueue.scala:22:25] reg elts_4_xcpt_ae_inst; // @[ShiftQueue.scala:22:25] reg elts_4_replay; // @[ShiftQueue.scala:22:25] wire [1:0] wdata_btb_cfiType = valid_1 ? elts_1_btb_cfiType : io_enq_bits_btb_cfiType_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_btb_taken = valid_1 & elts_1_btb_taken; // @[ShiftQueue.scala:21:30, :22:25, :27:57] wire [1:0] wdata_btb_mask = valid_1 ? elts_1_btb_mask : io_enq_bits_btb_mask_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_btb_bridx = valid_1 ? elts_1_btb_bridx : io_enq_bits_btb_bridx_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [31:0] wdata_btb_target = valid_1 ? elts_1_btb_target : io_enq_bits_btb_target_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_btb_entry = valid_1 ? elts_1_btb_entry : io_enq_bits_btb_entry_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [7:0] wdata_btb_bht_history = valid_1 ? elts_1_btb_bht_history : io_enq_bits_btb_bht_history_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_btb_bht_value = valid_1 ? elts_1_btb_bht_value : io_enq_bits_btb_bht_value_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [31:0] wdata_pc = valid_1 ? elts_1_pc : io_enq_bits_pc_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [31:0] wdata_data = valid_1 ? elts_1_data : io_enq_bits_data_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [1:0] wdata_mask = valid_1 ? elts_1_mask : io_enq_bits_mask_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_xcpt_pf_inst = valid_1 ? elts_1_xcpt_pf_inst : io_enq_bits_xcpt_pf_inst_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_xcpt_gf_inst = valid_1 & elts_1_xcpt_gf_inst; // @[ShiftQueue.scala:21:30, :22:25, :27:57] wire wdata_xcpt_ae_inst = valid_1 ? elts_1_xcpt_ae_inst : io_enq_bits_xcpt_ae_inst_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_replay = valid_1 ? elts_1_replay : io_enq_bits_replay_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire _GEN = io_enq_ready_0 & io_enq_valid_0; // @[Decoupled.scala:51:35] wire _wen_T; // @[Decoupled.scala:51:35] assign _wen_T = _GEN; // @[Decoupled.scala:51:35] wire _wen_T_4; // @[Decoupled.scala:51:35] assign _wen_T_4 = _GEN; // @[Decoupled.scala:51:35] wire _valid_0_T; // @[Decoupled.scala:51:35] assign _valid_0_T = _GEN; // @[Decoupled.scala:51:35] wire _valid_0_T_4; // @[Decoupled.scala:51:35] assign _valid_0_T_4 = _GEN; // @[Decoupled.scala:51:35] wire _wen_T_8; // @[Decoupled.scala:51:35] assign _wen_T_8 = _GEN; // @[Decoupled.scala:51:35] wire _wen_T_12; // @[Decoupled.scala:51:35] assign _wen_T_12 = _GEN; // @[Decoupled.scala:51:35] wire _valid_1_T; // @[Decoupled.scala:51:35] assign _valid_1_T = _GEN; // @[Decoupled.scala:51:35] wire _valid_1_T_4; // @[Decoupled.scala:51:35] assign _valid_1_T_4 = _GEN; // @[Decoupled.scala:51:35] wire _wen_T_16; // @[Decoupled.scala:51:35] assign _wen_T_16 = _GEN; // @[Decoupled.scala:51:35] wire _wen_T_20; // @[Decoupled.scala:51:35] assign _wen_T_20 = _GEN; // @[Decoupled.scala:51:35] wire _valid_2_T; // @[Decoupled.scala:51:35] assign _valid_2_T = _GEN; // @[Decoupled.scala:51:35] wire _valid_2_T_4; // @[Decoupled.scala:51:35] assign _valid_2_T_4 = _GEN; // @[Decoupled.scala:51:35] wire _wen_T_24; // @[Decoupled.scala:51:35] assign _wen_T_24 = _GEN; // @[Decoupled.scala:51:35] wire _wen_T_28; // @[Decoupled.scala:51:35] assign _wen_T_28 = _GEN; // @[Decoupled.scala:51:35] wire _valid_3_T; // @[Decoupled.scala:51:35] assign _valid_3_T = _GEN; // @[Decoupled.scala:51:35] wire _valid_3_T_4; // @[Decoupled.scala:51:35] assign _valid_3_T_4 = _GEN; // @[Decoupled.scala:51:35] wire _wen_T_32; // @[Decoupled.scala:51:35] assign _wen_T_32 = _GEN; // @[Decoupled.scala:51:35] wire _wen_T_36; // @[Decoupled.scala:51:35] assign _wen_T_36 = _GEN; // @[Decoupled.scala:51:35] wire _valid_4_T; // @[Decoupled.scala:51:35] assign _valid_4_T = _GEN; // @[Decoupled.scala:51:35] wire _valid_4_T_4; // @[Decoupled.scala:51:35] assign _valid_4_T_4 = _GEN; // @[Decoupled.scala:51:35] wire _wen_T_2 = _wen_T & _wen_T_1; // @[Decoupled.scala:51:35] wire _wen_T_3 = valid_1 \| _wen_T_2; // @[ShiftQueue.scala:21:30, :30:{28,43}] wire _wen_T_5 = _wen_T_4; // @[Decoupled.scala:51:35] wire _wen_T_6 = ~valid_0; // @[ShiftQueue.scala:21:30, :31:46] wire _wen_T_7 = _wen_T_5 & _wen_T_6; // @[ShiftQueue.scala:31:{23,43,46}] wire wen = io_deq_ready_0 ? _wen_T_3 : _wen_T_7; // @[ShiftQueue.scala:12:7, :29:10, :30:28, :31:43] wire _valid_0_T_2 = _valid_0_T & _valid_0_T_1; // @[Decoupled.scala:51:35] wire _valid_0_T_3 = valid_1 \| _valid_0_T_2; // @[ShiftQueue.scala:21:30, :36:{28,43}] wire _valid_0_T_5 = _valid_0_T_4; // @[Decoupled.scala:51:35] wire _valid_0_T_6 = _valid_0_T_5 \| valid_0; // @[ShiftQueue.scala:21:30, :37:{23,43}] wire _valid_0_T_7 = io_deq_ready_0 ? _valid_0_T_3 : _valid_0_T_6; // @[ShiftQueue.scala:12:7, :35:10, :36:28, :37:43] wire [1:0] wdata_1_btb_cfiType = valid_2 ? elts_2_btb_cfiType : io_enq_bits_btb_cfiType_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_1_btb_taken = valid_2 & elts_2_btb_taken; // @[ShiftQueue.scala:21:30, :22:25, :27:57] wire [1:0] wdata_1_btb_mask = valid_2 ? elts_2_btb_mask : io_enq_bits_btb_mask_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_1_btb_bridx = valid_2 ? elts_2_btb_bridx : io_enq_bits_btb_bridx_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [31:0] wdata_1_btb_target = valid_2 ? elts_2_btb_target : io_enq_bits_btb_target_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_1_btb_entry = valid_2 ? elts_2_btb_entry : io_enq_bits_btb_entry_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [7:0] wdata_1_btb_bht_history = valid_2 ? elts_2_btb_bht_history : io_enq_bits_btb_bht_history_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_1_btb_bht_value = valid_2 ? elts_2_btb_bht_value : io_enq_bits_btb_bht_value_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [31:0] wdata_1_pc = valid_2 ? elts_2_pc : io_enq_bits_pc_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [31:0] wdata_1_data = valid_2 ? elts_2_data : io_enq_bits_data_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [1:0] wdata_1_mask = valid_2 ? elts_2_mask : io_enq_bits_mask_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_1_xcpt_pf_inst = valid_2 ? elts_2_xcpt_pf_inst : io_enq_bits_xcpt_pf_inst_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_1_xcpt_gf_inst = valid_2 & elts_2_xcpt_gf_inst; // @[ShiftQueue.scala:21:30, :22:25, :27:57] wire wdata_1_xcpt_ae_inst = valid_2 ? elts_2_xcpt_ae_inst : io_enq_bits_xcpt_ae_inst_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_1_replay = valid_2 ? elts_2_replay : io_enq_bits_replay_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire _wen_T_10 = _wen_T_8 & _wen_T_9; // @[Decoupled.scala:51:35] wire _wen_T_11 = valid_2 \| _wen_T_10; // @[ShiftQueue.scala:21:30, :30:{28,43}] wire _wen_T_13 = _wen_T_12 & valid_0; // @[Decoupled.scala:51:35] wire _wen_T_14 = ~valid_1; // @[ShiftQueue.scala:21:30, :31:46] wire _wen_T_15 = _wen_T_13 & _wen_T_14; // @[ShiftQueue.scala:31:{23,43,46}] wire wen_1 = io_deq_ready_0 ? _wen_T_11 : _wen_T_15; // @[ShiftQueue.scala:12:7, :29:10, :30:28, :31:43] wire _valid_1_T_2 = _valid_1_T & _valid_1_T_1; // @[Decoupled.scala:51:35] wire _valid_1_T_3 = valid_2 \| _valid_1_T_2; // @[ShiftQueue.scala:21:30, :36:{28,43}] wire _valid_1_T_5 = _valid_1_T_4 & valid_0; // @[Decoupled.scala:51:35] wire _valid_1_T_6 = _valid_1_T_5 \| valid_1; // @[ShiftQueue.scala:21:30, :37:{23,43}] wire _valid_1_T_7 = io_deq_ready_0 ? _valid_1_T_3 : _valid_1_T_6; // @[ShiftQueue.scala:12:7, :35:10, :36:28, :37:43] wire [1:0] wdata_2_btb_cfiType = valid_3 ? elts_3_btb_cfiType : io_enq_bits_btb_cfiType_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_2_btb_taken = valid_3 & elts_3_btb_taken; // @[ShiftQueue.scala:21:30, :22:25, :27:57] wire [1:0] wdata_2_btb_mask = valid_3 ? elts_3_btb_mask : io_enq_bits_btb_mask_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_2_btb_bridx = valid_3 ? elts_3_btb_bridx : io_enq_bits_btb_bridx_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [31:0] wdata_2_btb_target = valid_3 ? elts_3_btb_target : io_enq_bits_btb_target_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_2_btb_entry = valid_3 ? elts_3_btb_entry : io_enq_bits_btb_entry_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [7:0] wdata_2_btb_bht_history = valid_3 ? elts_3_btb_bht_history : io_enq_bits_btb_bht_history_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_2_btb_bht_value = valid_3 ? elts_3_btb_bht_value : io_enq_bits_btb_bht_value_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [31:0] wdata_2_pc = valid_3 ? elts_3_pc : io_enq_bits_pc_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [31:0] wdata_2_data = valid_3 ? elts_3_data : io_enq_bits_data_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [1:0] wdata_2_mask = valid_3 ? elts_3_mask : io_enq_bits_mask_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_2_xcpt_pf_inst = valid_3 ? elts_3_xcpt_pf_inst : io_enq_bits_xcpt_pf_inst_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_2_xcpt_gf_inst = valid_3 & elts_3_xcpt_gf_inst; // @[ShiftQueue.scala:21:30, :22:25, :27:57] wire wdata_2_xcpt_ae_inst = valid_3 ? elts_3_xcpt_ae_inst : io_enq_bits_xcpt_ae_inst_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_2_replay = valid_3 ? elts_3_replay : io_enq_bits_replay_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire _wen_T_18 = _wen_T_16 & _wen_T_17; // @[Decoupled.scala:51:35] wire _wen_T_19 = valid_3 \| _wen_T_18; // @[ShiftQueue.scala:21:30, :30:{28,43}] wire _wen_T_21 = _wen_T_20 & valid_1; // @[Decoupled.scala:51:35] wire _wen_T_22 = ~valid_2; // @[ShiftQueue.scala:21:30, :31:46] wire _wen_T_23 = _wen_T_21 & _wen_T_22; // @[ShiftQueue.scala:31:{23,43,46}] wire wen_2 = io_deq_ready_0 ? _wen_T_19 : _wen_T_23; // @[ShiftQueue.scala:12:7, :29:10, :30:28, :31:43] wire _valid_2_T_2 = _valid_2_T & _valid_2_T_1; // @[Decoupled.scala:51:35] wire _valid_2_T_3 = valid_3 \| _valid_2_T_2; // @[ShiftQueue.scala:21:30, :36:{28,43}] wire _valid_2_T_5 = _valid_2_T_4 & valid_1; // @[Decoupled.scala:51:35] wire _valid_2_T_6 = _valid_2_T_5 \| valid_2; // @[ShiftQueue.scala:21:30, :37:{23,43}] wire _valid_2_T_7 = io_deq_ready_0 ? _valid_2_T_3 : _valid_2_T_6; // @[ShiftQueue.scala:12:7, :35:10, :36:28, :37:43] wire [1:0] wdata_3_btb_cfiType = valid_4 ? elts_4_btb_cfiType : io_enq_bits_btb_cfiType_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [1:0] wdata_3_btb_mask = valid_4 ? elts_4_btb_mask : io_enq_bits_btb_mask_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_3_btb_bridx = valid_4 ? elts_4_btb_bridx : io_enq_bits_btb_bridx_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [31:0] wdata_3_btb_target = valid_4 ? elts_4_btb_target : io_enq_bits_btb_target_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_3_btb_entry = valid_4 ? elts_4_btb_entry : io_enq_bits_btb_entry_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [7:0] wdata_3_btb_bht_history = valid_4 ? elts_4_btb_bht_history : io_enq_bits_btb_bht_history_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_3_btb_bht_value = valid_4 ? elts_4_btb_bht_value : io_enq_bits_btb_bht_value_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [31:0] wdata_3_pc = valid_4 ? elts_4_pc : io_enq_bits_pc_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [31:0] wdata_3_data = valid_4 ? elts_4_data : io_enq_bits_data_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [1:0] wdata_3_mask = valid_4 ? elts_4_mask : io_enq_bits_mask_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_3_xcpt_pf_inst = valid_4 ? elts_4_xcpt_pf_inst : io_enq_bits_xcpt_pf_inst_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_3_xcpt_gf_inst = valid_4 & elts_4_xcpt_gf_inst; // @[ShiftQueue.scala:21:30, :22:25, :27:57] wire wdata_3_xcpt_ae_inst = valid_4 ? elts_4_xcpt_ae_inst : io_enq_bits_xcpt_ae_inst_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_3_replay = valid_4 ? elts_4_replay : io_enq_bits_replay_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire _wen_T_26 = _wen_T_24 & _wen_T_25; // @[Decoupled.scala:51:35] wire _wen_T_27 = valid_4 \| _wen_T_26; // @[ShiftQueue.scala:21:30, :30:{28,43}] wire _wen_T_29 = _wen_T_28 & valid_2; // @[Decoupled.scala:51:35] wire _wen_T_30 = ~valid_3; // @[ShiftQueue.scala:21:30, :31:46] wire _wen_T_31 = _wen_T_29 & _wen_T_30; // @[ShiftQueue.scala:31:{23,43,46}] wire wen_3 = io_deq_ready_0 ? _wen_T_27 : _wen_T_31; // @[ShiftQueue.scala:12:7, :29:10, :30:28, :31:43] wire _valid_3_T_2 = _valid_3_T & _valid_3_T_1; // @[Decoupled.scala:51:35] wire _valid_3_T_3 = valid_4 \| _valid_3_T_2; // @[ShiftQueue.scala:21:30, :36:{28,43}] wire _valid_3_T_5 = _valid_3_T_4 & valid_2; // @[Decoupled.scala:51:35] wire _valid_3_T_6 = _valid_3_T_5 \| valid_3; // @[ShiftQueue.scala:21:30, :37:{23,43}] wire _valid_3_T_7 = io_deq_ready_0 ? _valid_3_T_3 : _valid_3_T_6; // @[ShiftQueue.scala:12:7, :35:10, :36:28, :37:43] wire _wen_T_34 = _wen_T_32 & _wen_T_33; // @[Decoupled.scala:51:35] wire _wen_T_35 = _wen_T_34; // @[ShiftQueue.scala:30:{28,43}] wire _wen_T_37 = _wen_T_36 & valid_3; // @[Decoupled.scala:51:35] wire _wen_T_38 = ~valid_4; // @[ShiftQueue.scala:21:30, :31:46] wire _wen_T_39 = _wen_T_37 & _wen_T_38; // @[ShiftQueue.scala:31:{23,43,46}] wire wen_4 = io_deq_ready_0 ? _wen_T_35 : _wen_T_39; // @[ShiftQueue.scala:12:7, :29:10, :30:28, :31:43] wire _valid_4_T_2 = _valid_4_T & _valid_4_T_1; // @[Decoupled.scala:51:35] wire _valid_4_T_3 = _valid_4_T_2; // @[ShiftQueue.scala:36:{28,43}] wire _valid_4_T_5 = _valid_4_T_4 & valid_3; // @[Decoupled.scala:51:35] wire _valid_4_T_6 = _valid_4_T_5 \| valid_4; // @[ShiftQueue.scala:21:30, :37:{23,43}] wire _valid_4_T_7 = io_deq_ready_0 ? _valid_4_T_3 : _valid_4_T_6; // @[ShiftQueue.scala:12:7, :35:10, :36:28, :37:43] assign _io_enq_ready_T = ~valid_4; // @[ShiftQueue.scala:21:30, :31:46, :40:19] assign io_enq_ready_0 = _io_enq_ready_T; // @[ShiftQueue.scala:12:7, :40:19] assign io_deq_valid_0 = io_enq_valid_0 \| valid_0; // @[ShiftQueue.scala:12:7, :21:30, :41:16, :45:{25,40}] assign io_deq_bits_btb_cfiType_0 = valid_0 ? elts_0_btb_cfiType : io_enq_bits_btb_cfiType_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_btb_taken_0 = valid_0 & elts_0_btb_taken; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_btb_mask_0 = valid_0 ? elts_0_btb_mask : io_enq_bits_btb_mask_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_btb_bridx_0 = valid_0 ? elts_0_btb_bridx : io_enq_bits_btb_bridx_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_btb_target_0 = valid_0 ? elts_0_btb_target : io_enq_bits_btb_target_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_btb_entry_0 = valid_0 ? elts_0_btb_entry : io_enq_bits_btb_entry_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_btb_bht_history_0 = valid_0 ? elts_0_btb_bht_history : io_enq_bits_btb_bht_history_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_btb_bht_value_0 = valid_0 ? elts_0_btb_bht_value : io_enq_bits_btb_bht_value_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_pc_0 = valid_0 ? elts_0_pc : io_enq_bits_pc_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_data_0 = valid_0 ? elts_0_data : io_enq_bits_data_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_mask_0 = valid_0 ? elts_0_mask : io_enq_bits_mask_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_xcpt_pf_inst_0 = valid_0 ? elts_0_xcpt_pf_inst : io_enq_bits_xcpt_pf_inst_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_xcpt_gf_inst_0 = valid_0 & elts_0_xcpt_gf_inst; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_xcpt_ae_inst_0 = valid_0 ? elts_0_xcpt_ae_inst : io_enq_bits_xcpt_ae_inst_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_replay_0 = valid_0 ? elts_0_replay : io_enq_bits_replay_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] wire [1:0] io_mask_lo = {valid_1, valid_0}; // @[ShiftQueue.scala:21:30, :53:20] wire [1:0] io_mask_hi_hi = {valid_4, valid_3}; // @[ShiftQueue.scala:21:30, :53:20] wire [2:0] io_mask_hi = {io_mask_hi_hi, valid_2}; // @[ShiftQueue.scala:21:30, :53:20] assign _io_mask_T = {io_mask_hi, io_mask_lo}; // @[ShiftQueue.scala:53:20] assign io_mask_0 = _io_mask_T; // @[ShiftQueue.scala:12:7, :53:20] wire _io_count_T = io_mask_0[0]; // @[ShiftQueue.scala:12:7, :54:23] wire _io_count_T_1 = io_mask_0[1]; // @[ShiftQueue.scala:12:7, :54:23] wire _io_count_T_2 = io_mask_0[2]; // @[ShiftQueue.scala:12:7, :54:23] wire _io_count_T_3 = io_mask_0[3]; // @[ShiftQueue.scala:12:7, :54:23] wire _io_count_T_4 = io_mask_0[4]; // @[ShiftQueue.scala:12:7, :54:23] wire [1:0] _io_count_T_5 = {1'h0, _io_count_T} + {1'h0, _io_count_T_1}; // @[ShiftQueue.scala:54:23] wire [1:0] _io_count_T_6 = _io_count_T_5; // @[ShiftQueue.scala:54:23] wire [1:0] _io_count_T_7 = {1'h0, _io_count_T_3} + {1'h0, _io_count_T_4}; // @[ShiftQueue.scala:54:23] wire [1:0] _io_count_T_8 = _io_count_T_7; // @[ShiftQueue.scala:54:23] wire [2:0] _io_count_T_9 = {2'h0, _io_count_T_2} + {1'h0, _io_count_T_8}; // @[ShiftQueue.scala:54:23] wire [1:0] _io_count_T_10 = _io_count_T_9[1:0]; // @[ShiftQueue.scala:54:23] wire [2:0] _io_count_T_11 = {1'h0, _io_count_T_6} + {1'h0, _io_count_T_10}; // @[ShiftQueue.scala:54:23] assign _io_count_T_12 = _io_count_T_11; // @[ShiftQueue.scala:54:23] assign io_count = _io_count_T_12; // @[ShiftQueue.scala:12:7, :54:23] always @(posedge clock) begin // @[ShiftQueue.scala:12:7] if (reset) begin // @[ShiftQueue.scala:12:7] valid_0 <= 1'h0; // @[ShiftQueue.scala:21:30] valid_1 <= 1'h0; // @[ShiftQueue.scala:21:30] valid_2 <= 1'h0; // @[ShiftQueue.scala:21:30] valid_3 <= 1'h0; // @[ShiftQueue.scala:21:30] valid_4 <= 1'h0; // @[ShiftQueue.scala:21:30] end else begin // @[ShiftQueue.scala:12:7] valid_0 <= _valid_0_T_7; // @[ShiftQueue.scala:21:30, :35:10] valid_1 <= _valid_1_T_7; // @[ShiftQueue.scala:21:30, :35:10] valid_2 <= _valid_2_T_7; // @[ShiftQueue.scala:21:30, :35:10] valid_3 <= _valid_3_T_7; // @[ShiftQueue.scala:21:30, :35:10] valid_4 <= _valid_4_T_7; // @[ShiftQueue.scala:21:30, :35:10] end if (wen) begin // @[ShiftQueue.scala:29:10] elts_0_btb_cfiType <= wdata_btb_cfiType; // @[ShiftQueue.scala:22:25, :27:57] elts_0_btb_taken <= wdata_btb_taken; // @[ShiftQueue.scala:22:25, :27:57] elts_0_btb_mask <= wdata_btb_mask; // @[ShiftQueue.scala:22:25, :27:57] elts_0_btb_bridx <= wdata_btb_bridx; // @[ShiftQueue.scala:22:25, :27:57] elts_0_btb_target <= wdata_btb_target; // @[ShiftQueue.scala:22:25, :27:57] elts_0_btb_entry <= wdata_btb_entry; // @[ShiftQueue.scala:22:25, :27:57] elts_0_btb_bht_history <= wdata_btb_bht_history; // @[ShiftQueue.scala:22:25, :27:57] elts_0_btb_bht_value <= wdata_btb_bht_value; // @[ShiftQueue.scala:22:25, :27:57] elts_0_pc <= wdata_pc; // @[ShiftQueue.scala:22:25, :27:57] elts_0_data <= wdata_data; // @[ShiftQueue.scala:22:25, :27:57] elts_0_mask <= wdata_mask; // @[ShiftQueue.scala:22:25, :27:57] elts_0_xcpt_pf_inst <= wdata_xcpt_pf_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_0_xcpt_gf_inst <= wdata_xcpt_gf_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_0_xcpt_ae_inst <= wdata_xcpt_ae_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_0_replay <= wdata_replay; // @[ShiftQueue.scala:22:25, :27:57] end if (wen_1) begin // @[ShiftQueue.scala:29:10] elts_1_btb_cfiType <= wdata_1_btb_cfiType; // @[ShiftQueue.scala:22:25, :27:57] elts_1_btb_taken <= wdata_1_btb_taken; // @[ShiftQueue.scala:22:25, :27:57] elts_1_btb_mask <= wdata_1_btb_mask; // @[ShiftQueue.scala:22:25, :27:57] elts_1_btb_bridx <= wdata_1_btb_bridx; // @[ShiftQueue.scala:22:25, :27:57] elts_1_btb_target <= wdata_1_btb_target; // @[ShiftQueue.scala:22:25, :27:57] elts_1_btb_entry <= wdata_1_btb_entry; // @[ShiftQueue.scala:22:25, :27:57] elts_1_btb_bht_history <= wdata_1_btb_bht_history; // @[ShiftQueue.scala:22:25, :27:57] elts_1_btb_bht_value <= wdata_1_btb_bht_value; // @[ShiftQueue.scala:22:25, :27:57] elts_1_pc <= wdata_1_pc; // @[ShiftQueue.scala:22:25, :27:57] elts_1_data <= wdata_1_data; // @[ShiftQueue.scala:22:25, :27:57] elts_1_mask <= wdata_1_mask; // @[ShiftQueue.scala:22:25, :27:57] elts_1_xcpt_pf_inst <= wdata_1_xcpt_pf_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_1_xcpt_gf_inst <= wdata_1_xcpt_gf_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_1_xcpt_ae_inst <= wdata_1_xcpt_ae_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_1_replay <= wdata_1_replay; // @[ShiftQueue.scala:22:25, :27:57] end if (wen_2) begin // @[ShiftQueue.scala:29:10] elts_2_btb_cfiType <= wdata_2_btb_cfiType; // @[ShiftQueue.scala:22:25, :27:57] elts_2_btb_taken <= wdata_2_btb_taken; // @[ShiftQueue.scala:22:25, :27:57] elts_2_btb_mask <= wdata_2_btb_mask; // @[ShiftQueue.scala:22:25, :27:57] elts_2_btb_bridx <= wdata_2_btb_bridx; // @[ShiftQueue.scala:22:25, :27:57] elts_2_btb_target <= wdata_2_btb_target; // @[ShiftQueue.scala:22:25, :27:57] elts_2_btb_entry <= wdata_2_btb_entry; // @[ShiftQueue.scala:22:25, :27:57] elts_2_btb_bht_history <= wdata_2_btb_bht_history; // @[ShiftQueue.scala:22:25, :27:57] elts_2_btb_bht_value <= wdata_2_btb_bht_value; // @[ShiftQueue.scala:22:25, :27:57] elts_2_pc <= wdata_2_pc; // @[ShiftQueue.scala:22:25, :27:57] elts_2_data <= wdata_2_data; // @[ShiftQueue.scala:22:25, :27:57] elts_2_mask <= wdata_2_mask; // @[ShiftQueue.scala:22:25, :27:57] elts_2_xcpt_pf_inst <= wdata_2_xcpt_pf_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_2_xcpt_gf_inst <= wdata_2_xcpt_gf_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_2_xcpt_ae_inst <= wdata_2_xcpt_ae_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_2_replay <= wdata_2_replay; // @[ShiftQueue.scala:22:25, :27:57] end if (wen_3) begin // @[ShiftQueue.scala:29:10] elts_3_btb_cfiType <= wdata_3_btb_cfiType; // @[ShiftQueue.scala:22:25, :27:57] elts_3_btb_mask <= wdata_3_btb_mask; // @[ShiftQueue.scala:22:25, :27:57] elts_3_btb_bridx <= wdata_3_btb_bridx; // @[ShiftQueue.scala:22:25, :27:57] elts_3_btb_target <= wdata_3_btb_target; // @[ShiftQueue.scala:22:25, :27:57] elts_3_btb_entry <= wdata_3_btb_entry; // @[ShiftQueue.scala:22:25, :27:57] elts_3_btb_bht_history <= wdata_3_btb_bht_history; // @[ShiftQueue.scala:22:25, :27:57] elts_3_btb_bht_value <= wdata_3_btb_bht_value; // @[ShiftQueue.scala:22:25, :27:57] elts_3_pc <= wdata_3_pc; // @[ShiftQueue.scala:22:25, :27:57] elts_3_data <= wdata_3_data; // @[ShiftQueue.scala:22:25, :27:57] elts_3_mask <= wdata_3_mask; // @[ShiftQueue.scala:22:25, :27:57] elts_3_xcpt_pf_inst <= wdata_3_xcpt_pf_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_3_xcpt_gf_inst <= wdata_3_xcpt_gf_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_3_xcpt_ae_inst <= wdata_3_xcpt_ae_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_3_replay <= wdata_3_replay; // @[ShiftQueue.scala:22:25, :27:57] end elts_3_btb_taken <= ~wen_3 & elts_3_btb_taken; // @[ShiftQueue.scala:22:25, :29:10, :32:{16,26}] if (wen_4) begin // @[ShiftQueue.scala:29:10] elts_4_btb_cfiType <= io_enq_bits_btb_cfiType_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_btb_mask <= io_enq_bits_btb_mask_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_btb_bridx <= io_enq_bits_btb_bridx_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_btb_target <= io_enq_bits_btb_target_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_btb_entry <= io_enq_bits_btb_entry_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_btb_bht_history <= io_enq_bits_btb_bht_history_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_btb_bht_value <= io_enq_bits_btb_bht_value_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_pc <= io_enq_bits_pc_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_data <= io_enq_bits_data_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_mask <= io_enq_bits_mask_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_xcpt_pf_inst <= io_enq_bits_xcpt_pf_inst_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_xcpt_ae_inst <= io_enq_bits_xcpt_ae_inst_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_replay <= io_enq_bits_replay_0; // @[ShiftQueue.scala:12:7, :22:25] end elts_4_xcpt_gf_inst <= ~wen_4 & elts_4_xcpt_gf_inst; // @[ShiftQueue.scala:22:25, :29:10, :32:{16,26}] always @(posedge) assign io_enq_ready = io_enq_ready_0; // @[ShiftQueue.scala:12:7] assign io_deq_valid = io_deq_valid_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_btb_cfiType = io_deq_bits_btb_cfiType_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_btb_taken = io_deq_bits_btb_taken_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_btb_mask = io_deq_bits_btb_mask_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_btb_bridx = io_deq_bits_btb_bridx_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_btb_target = io_deq_bits_btb_target_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_btb_entry = io_deq_bits_btb_entry_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_btb_bht_history = io_deq_bits_btb_bht_history_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_btb_bht_value = io_deq_bits_btb_bht_value_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_pc = io_deq_bits_pc_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_data = io_deq_bits_data_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_mask = io_deq_bits_mask_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_xcpt_pf_inst = io_deq_bits_xcpt_pf_inst_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_xcpt_gf_inst = io_deq_bits_xcpt_gf_inst_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_xcpt_ae_inst = io_deq_bits_xcpt_ae_inst_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_replay = io_deq_bits_replay_0; // @[ShiftQueue.scala:12:7] assign io_mask = io_mask_0; // @[ShiftQueue.scala:12:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_4( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_37 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_43 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_49 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire _source_ok_T_27 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31] wire _source_ok_T_28 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_29 = _source_ok_T_28 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_30 = _source_ok_T_29 \| _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_31 = _source_ok_T_30 \| _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_32 = _source_ok_T_31 \| _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_33 = _source_ok_T_32 \| _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_33 \| _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [28:0] _is_aligned_T = {23'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_34 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_34; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_35 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_41 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_47 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_53 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_36 = _source_ok_T_35 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_38 = _source_ok_T_36; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_40; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_42 = _source_ok_T_41 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_44 = _source_ok_T_42; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_46; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_48 = _source_ok_T_47 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_50 = _source_ok_T_48; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_52; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_54 = _source_ok_T_53 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_58; // @[Parameters.scala:1138:31] wire _source_ok_T_59 = io_in_d_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_59; // @[Parameters.scala:1138:31] wire _source_ok_T_60 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_60; // @[Parameters.scala:1138:31] wire _source_ok_T_61 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_61; // @[Parameters.scala:1138:31] wire _source_ok_T_62 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_63 = _source_ok_T_62 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_64 = _source_ok_T_63 \| _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_65 = _source_ok_T_64 \| _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_66 = _source_ok_T_65 \| _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_67 = _source_ok_T_66 \| _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_67 \| _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _T_1035 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1035; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1035; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [28:0] address; // @[Monitor.scala:391:22] wire _T_1103 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1103; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1103; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1103; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [259:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [259:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_968 = _T_1035 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_968 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_968 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_968 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_968 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_968 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1014 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1014 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_983 = _T_1103 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_983 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_983 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_983 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [259:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1079 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1079 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1061 = _T_1103 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1061 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1061 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1061 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_56( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [16:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [16:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_release_ack = 1'h0; // @[Monitor.scala:673:46] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire d_release_ack_1 = 1'h0; // @[Monitor.scala:783:46] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire d_first_beats1_opdata = 1'h1; // @[Edges.scala:106:36] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire d_first_beats1_opdata_1 = 1'h1; // @[Edges.scala:106:36] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire d_first_beats1_opdata_2 = 1'h1; // @[Edges.scala:106:36] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [2:0] io_in_d_bits_opcode = 3'h1; // @[Monitor.scala:36:7] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [4159:0] _inflight_opcodes_T_4 = 4160'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[Monitor.scala:815:62] wire [4159:0] _inflight_sizes_T_4 = 4160'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[Monitor.scala:816:58] wire [1039:0] _inflight_T_4 = 1040'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[Monitor.scala:814:46] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [16:0] _c_first_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_first_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_first_WIRE_2_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_first_WIRE_3_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_set_wo_ready_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_set_wo_ready_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_set_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_set_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_opcodes_set_interm_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_opcodes_set_interm_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_sizes_set_interm_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_sizes_set_interm_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_opcodes_set_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_opcodes_set_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_sizes_set_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_sizes_set_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_probe_ack_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_probe_ack_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_probe_ack_WIRE_2_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_probe_ack_WIRE_3_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _same_cycle_resp_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _same_cycle_resp_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _same_cycle_resp_WIRE_2_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _same_cycle_resp_WIRE_3_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _same_cycle_resp_WIRE_4_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _same_cycle_resp_WIRE_5_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_wo_ready_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_wo_ready_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_4_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_5_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [4159:0] c_opcodes_set = 4160'h0; // @[Monitor.scala:740:34] wire [4159:0] c_sizes_set = 4160'h0; // @[Monitor.scala:741:34] wire [4159:0] d_opcodes_clr_1 = 4160'h0; // @[Monitor.scala:776:34] wire [4159:0] d_sizes_clr_1 = 4160'h0; // @[Monitor.scala:777:34] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1039:0] c_set = 1040'h0; // @[Monitor.scala:738:34] wire [1039:0] c_set_wo_ready = 1040'h0; // @[Monitor.scala:739:34] wire [1039:0] d_clr_1 = 1040'h0; // @[Monitor.scala:774:34] wire [1039:0] d_clr_wo_ready_1 = 1040'h0; // @[Monitor.scala:775:34] wire [16385:0] _c_sizes_set_T_1 = 16386'h0; // @[Monitor.scala:768:52] wire [13:0] _c_opcodes_set_T = 14'h0; // @[Monitor.scala:767:79] wire [13:0] _c_sizes_set_T = 14'h0; // @[Monitor.scala:768:77] wire [16386:0] _c_opcodes_set_T_1 = 16387'h0; // @[Monitor.scala:767:54] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [2047:0] _c_set_wo_ready_T = 2048'h1; // @[OneHot.scala:58:35] wire [2047:0] _c_set_T = 2048'h1; // @[OneHot.scala:58:35] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [10:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [16:0] _is_aligned_T = {14'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 17'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [10:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [10:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_659 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_659; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_659; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [10:0] source; // @[Monitor.scala:390:22] reg [16:0] address; // @[Monitor.scala:391:22] wire _T_727 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_727; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_727; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_727; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [10:0] source_1; // @[Monitor.scala:541:22] reg [1039:0] inflight; // @[Monitor.scala:614:27] reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [1039:0] a_set; // @[Monitor.scala:626:34] wire [1039:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [4159:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [4159:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [13:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [13:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [13:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [13:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [13:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [13:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [13:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [13:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [13:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [4159:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [4159:0] _a_opcode_lookup_T_6 = {4156'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [4159:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [4159:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [4159:0] _a_size_lookup_T_6 = {4156'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [4159:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[4159:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [2047:0] _GEN_2 = 2048'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [2047:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_592 = _T_659 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_592 ? _a_set_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_592 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_592 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [13:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [13:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [13:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [16386:0] _a_opcodes_set_T_1 = {16383'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_592 ? _a_opcodes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [16385:0] _a_sizes_set_T_1 = {16383'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_592 ? _a_sizes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [1039:0] d_clr; // @[Monitor.scala:664:34] wire [1039:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [4159:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [4159:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _T_638 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [2047:0] _GEN_4 = 2048'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_4; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_4; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_4; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_638 ? _d_clr_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_605 = _T_727 & d_first_1; // @[Decoupled.scala:51:35] assign d_clr = _T_605 ? _d_clr_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_5 = 16399'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_605 ? _d_opcodes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:668:33, :678:{25,89}, :680:{21,76}] wire [16398:0] _d_sizes_clr_T_5 = 16399'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_605 ? _d_sizes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:670:31, :678:{25,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1039:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [1039:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1039:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [4159:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [4159:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [4159:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [4159:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [4159:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [4159:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1039:0] inflight_1; // @[Monitor.scala:726:35] wire [1039:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [4159:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [4159:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [4159:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [4159:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [4159:0] _c_opcode_lookup_T_6 = {4156'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [4159:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [4159:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [4159:0] _c_size_lookup_T_6 = {4156'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [4159:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[4159:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [16398:0] _d_opcodes_clr_T_11 = 16399'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] wire [16398:0] _d_sizes_clr_T_11 = 16399'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 11'h0; // @[Monitor.scala:36:7, :795:113] wire [1039:0] _inflight_T_5 = _inflight_T_3; // @[Monitor.scala:814:{35,44}] wire [4159:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3; // @[Monitor.scala:815:{43,60}] wire [4159:0] _inflight_sizes_T_5 = _inflight_sizes_T_3; // @[Monitor.scala:816:{41,56}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File Repeater.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{Decoupled, DecoupledIO} // A Repeater passes its input to its output, unless repeat is asserted. // When repeat is asserted, the Repeater copies the input and repeats it next cycle. class Repeater[T <: Data](gen: T) extends Module { override def desiredName = s"Repeater_${gen.typeName}" val io = IO( new Bundle { val repeat = Input(Bool()) val full = Output(Bool()) val enq = Flipped(Decoupled(gen.cloneType)) val deq = Decoupled(gen.cloneType) } ) val full = RegInit(false.B) val saved = Reg(gen.cloneType) // When !full, a repeater is pass-through io.deq.valid := io.enq.valid \|\| full io.enq.ready := io.deq.ready && !full io.deq.bits := Mux(full, saved, io.enq.bits) io.full := full when (io.enq.fire && io.repeat) { full := true.B; saved := io.enq.bits } when (io.deq.fire && !io.repeat) { full := false.B } } object Repeater { def apply[T <: Data](enq: DecoupledIO[T], repeat: Bool): DecoupledIO[T] = { val repeater = Module(new Repeater(chiselTypeOf(enq.bits))) repeater.io.repeat := repeat repeater.io.enq <> enq repeater.io.deq } }	module Repeater_TLBundleA_a21d64s8k1z3u_1( // @[Repeater.scala:10:7] input clock, // @[Repeater.scala:10:7] input reset, // @[Repeater.scala:10:7] input io_repeat, // @[Repeater.scala:13:14] output io_full, // @[Repeater.scala:13:14] output io_enq_ready, // @[Repeater.scala:13:14] input io_enq_valid, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_opcode, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_param, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_size, // @[Repeater.scala:13:14] input [7:0] io_enq_bits_source, // @[Repeater.scala:13:14] input [20:0] io_enq_bits_address, // @[Repeater.scala:13:14] input [7:0] io_enq_bits_mask, // @[Repeater.scala:13:14] input [63:0] io_enq_bits_data, // @[Repeater.scala:13:14] input io_enq_bits_corrupt, // @[Repeater.scala:13:14] input io_deq_ready, // @[Repeater.scala:13:14] output io_deq_valid, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_opcode, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_param, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_size, // @[Repeater.scala:13:14] output [7:0] io_deq_bits_source, // @[Repeater.scala:13:14] output [20:0] io_deq_bits_address, // @[Repeater.scala:13:14] output [7:0] io_deq_bits_mask, // @[Repeater.scala:13:14] output io_deq_bits_corrupt // @[Repeater.scala:13:14] ); wire io_repeat_0 = io_repeat; // @[Repeater.scala:10:7] wire io_enq_valid_0 = io_enq_valid; // @[Repeater.scala:10:7] wire [2:0] io_enq_bits_opcode_0 = io_enq_bits_opcode; // @[Repeater.scala:10:7] wire [2:0] io_enq_bits_param_0 = io_enq_bits_param; // @[Repeater.scala:10:7] wire [2:0] io_enq_bits_size_0 = io_enq_bits_size; // @[Repeater.scala:10:7] wire [7:0] io_enq_bits_source_0 = io_enq_bits_source; // @[Repeater.scala:10:7] wire [20:0] io_enq_bits_address_0 = io_enq_bits_address; // @[Repeater.scala:10:7] wire [7:0] io_enq_bits_mask_0 = io_enq_bits_mask; // @[Repeater.scala:10:7] wire [63:0] io_enq_bits_data_0 = io_enq_bits_data; // @[Repeater.scala:10:7] wire io_enq_bits_corrupt_0 = io_enq_bits_corrupt; // @[Repeater.scala:10:7] wire io_deq_ready_0 = io_deq_ready; // @[Repeater.scala:10:7] wire _io_enq_ready_T_1; // @[Repeater.scala:25:32] wire _io_deq_valid_T; // @[Repeater.scala:24:32] wire [2:0] _io_deq_bits_T_opcode; // @[Repeater.scala:26:21] wire [2:0] _io_deq_bits_T_param; // @[Repeater.scala:26:21] wire [2:0] _io_deq_bits_T_size; // @[Repeater.scala:26:21] wire [7:0] _io_deq_bits_T_source; // @[Repeater.scala:26:21] wire [20:0] _io_deq_bits_T_address; // @[Repeater.scala:26:21] wire [7:0] _io_deq_bits_T_mask; // @[Repeater.scala:26:21] wire [63:0] _io_deq_bits_T_data; // @[Repeater.scala:26:21] wire _io_deq_bits_T_corrupt; // @[Repeater.scala:26:21] wire io_enq_ready_0; // @[Repeater.scala:10:7] wire [2:0] io_deq_bits_opcode_0; // @[Repeater.scala:10:7] wire [2:0] io_deq_bits_param_0; // @[Repeater.scala:10:7] wire [2:0] io_deq_bits_size_0; // @[Repeater.scala:10:7] wire [7:0] io_deq_bits_source_0; // @[Repeater.scala:10:7] wire [20:0] io_deq_bits_address_0; // @[Repeater.scala:10:7] wire [7:0] io_deq_bits_mask_0; // @[Repeater.scala:10:7] wire [63:0] io_deq_bits_data; // @[Repeater.scala:10:7] wire io_deq_bits_corrupt_0; // @[Repeater.scala:10:7] wire io_deq_valid_0; // @[Repeater.scala:10:7] wire io_full_0; // @[Repeater.scala:10:7] reg full; // @[Repeater.scala:20:21] assign io_full_0 = full; // @[Repeater.scala:10:7, :20:21] reg [2:0] saved_opcode; // @[Repeater.scala:21:18] reg [2:0] saved_param; // @[Repeater.scala:21:18] reg [2:0] saved_size; // @[Repeater.scala:21:18] reg [7:0] saved_source; // @[Repeater.scala:21:18] reg [20:0] saved_address; // @[Repeater.scala:21:18] reg [7:0] saved_mask; // @[Repeater.scala:21:18] reg [63:0] saved_data; // @[Repeater.scala:21:18] reg saved_corrupt; // @[Repeater.scala:21:18] assign _io_deq_valid_T = io_enq_valid_0 \| full; // @[Repeater.scala:10:7, :20:21, :24:32] assign io_deq_valid_0 = _io_deq_valid_T; // @[Repeater.scala:10:7, :24:32] wire _io_enq_ready_T = ~full; // @[Repeater.scala:20:21, :25:35] assign _io_enq_ready_T_1 = io_deq_ready_0 & _io_enq_ready_T; // @[Repeater.scala:10:7, :25:{32,35}] assign io_enq_ready_0 = _io_enq_ready_T_1; // @[Repeater.scala:10:7, :25:32] assign _io_deq_bits_T_opcode = full ? saved_opcode : io_enq_bits_opcode_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_param = full ? saved_param : io_enq_bits_param_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_size = full ? saved_size : io_enq_bits_size_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_source = full ? saved_source : io_enq_bits_source_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_address = full ? saved_address : io_enq_bits_address_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_mask = full ? saved_mask : io_enq_bits_mask_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_data = full ? saved_data : io_enq_bits_data_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_corrupt = full ? saved_corrupt : io_enq_bits_corrupt_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign io_deq_bits_opcode_0 = _io_deq_bits_T_opcode; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_param_0 = _io_deq_bits_T_param; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_size_0 = _io_deq_bits_T_size; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_source_0 = _io_deq_bits_T_source; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_address_0 = _io_deq_bits_T_address; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_mask_0 = _io_deq_bits_T_mask; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_data = _io_deq_bits_T_data; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_corrupt_0 = _io_deq_bits_T_corrupt; // @[Repeater.scala:10:7, :26:21] wire _T_1 = io_enq_ready_0 & io_enq_valid_0 & io_repeat_0; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[Repeater.scala:10:7] if (reset) // @[Repeater.scala:10:7] full <= 1'h0; // @[Repeater.scala:20:21] else // @[Repeater.scala:10:7] full <= ~(io_deq_ready_0 & io_deq_valid_0 & ~io_repeat_0) & (_T_1 \| full); // @[Decoupled.scala:51:35] if (_T_1) begin // @[Decoupled.scala:51:35] saved_opcode <= io_enq_bits_opcode_0; // @[Repeater.scala:10:7, :21:18] saved_param <= io_enq_bits_param_0; // @[Repeater.scala:10:7, :21:18] saved_size <= io_enq_bits_size_0; // @[Repeater.scala:10:7, :21:18] saved_source <= io_enq_bits_source_0; // @[Repeater.scala:10:7, :21:18] saved_address <= io_enq_bits_address_0; // @[Repeater.scala:10:7, :21:18] saved_mask <= io_enq_bits_mask_0; // @[Repeater.scala:10:7, :21:18] saved_data <= io_enq_bits_data_0; // @[Repeater.scala:10:7, :21:18] saved_corrupt <= io_enq_bits_corrupt_0; // @[Repeater.scala:10:7, :21:18] end always @(posedge) assign io_full = io_full_0; // @[Repeater.scala:10:7] assign io_enq_ready = io_enq_ready_0; // @[Repeater.scala:10:7] assign io_deq_valid = io_deq_valid_0; // @[Repeater.scala:10:7] assign io_deq_bits_opcode = io_deq_bits_opcode_0; // @[Repeater.scala:10:7] assign io_deq_bits_param = io_deq_bits_param_0; // @[Repeater.scala:10:7] assign io_deq_bits_size = io_deq_bits_size_0; // @[Repeater.scala:10:7] assign io_deq_bits_source = io_deq_bits_source_0; // @[Repeater.scala:10:7] assign io_deq_bits_address = io_deq_bits_address_0; // @[Repeater.scala:10:7] assign io_deq_bits_mask = io_deq_bits_mask_0; // @[Repeater.scala:10:7] assign io_deq_bits_corrupt = io_deq_bits_corrupt_0; // @[Repeater.scala:10:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands / class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B \|\| ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B \|\| ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def (t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def (t: UInt) = self t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros \| ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def (t: SInt) = self t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros \| ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid \|\| output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid \|\| output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid \|\| output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def (t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def (t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }	module MacUnit_234( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [31:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7] wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54] wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Scheduler.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. / package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import freechips.rocketchip.diplomacy.AddressSet import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import chisel3.experimental.dataview._ class InclusiveCacheBankScheduler(params: InclusiveCacheParameters) extends Module { val io = IO(new Bundle { val in = Flipped(TLBundle(params.inner.bundle)) val out = TLBundle(params.outer.bundle) // Way permissions val ways = Flipped(Vec(params.allClients, UInt(params.cache.ways.W))) val divs = Flipped(Vec(params.allClients, UInt((InclusiveCacheParameters.lfsrBits + 1).W))) // Control port val req = Flipped(Decoupled(new SinkXRequest(params))) val resp = Decoupled(new SourceXRequest(params)) }) val sourceA = Module(new SourceA(params)) val sourceB = Module(new SourceB(params)) val sourceC = Module(new SourceC(params)) val sourceD = Module(new SourceD(params)) val sourceE = Module(new SourceE(params)) val sourceX = Module(new SourceX(params)) io.out.a <> sourceA.io.a io.out.c <> sourceC.io.c io.out.e <> sourceE.io.e io.in.b <> sourceB.io.b io.in.d <> sourceD.io.d io.resp <> sourceX.io.x val sinkA = Module(new SinkA(params)) val sinkC = Module(new SinkC(params)) val sinkD = Module(new SinkD(params)) val sinkE = Module(new SinkE(params)) val sinkX = Module(new SinkX(params)) sinkA.io.a <> io.in.a sinkC.io.c <> io.in.c sinkE.io.e <> io.in.e sinkD.io.d <> io.out.d sinkX.io.x <> io.req io.out.b.ready := true.B // disconnected val directory = Module(new Directory(params)) val bankedStore = Module(new BankedStore(params)) val requests = Module(new ListBuffer(ListBufferParameters(new QueuedRequest(params), 3params.mshrs, params.secondary, false))) val mshrs = Seq.fill(params.mshrs) { Module(new MSHR(params)) } val abc_mshrs = mshrs.init.init val bc_mshr = mshrs.init.last val c_mshr = mshrs.last val nestedwb = Wire(new NestedWriteback(params)) // Deliver messages from Sinks to MSHRs mshrs.zipWithIndex.foreach { case (m, i) => m.io.sinkc.valid := sinkC.io.resp.valid && sinkC.io.resp.bits.set === m.io.status.bits.set m.io.sinkd.valid := sinkD.io.resp.valid && sinkD.io.resp.bits.source === i.U m.io.sinke.valid := sinkE.io.resp.valid && sinkE.io.resp.bits.sink === i.U m.io.sinkc.bits := sinkC.io.resp.bits m.io.sinkd.bits := sinkD.io.resp.bits m.io.sinke.bits := sinkE.io.resp.bits m.io.nestedwb := nestedwb } // If the pre-emption BC or C MSHR have a matching set, the normal MSHR must be blocked val mshr_stall_abc = abc_mshrs.map { m => (bc_mshr.io.status.valid && m.io.status.bits.set === bc_mshr.io.status.bits.set) \|\| ( c_mshr.io.status.valid && m.io.status.bits.set === c_mshr.io.status.bits.set) } val mshr_stall_bc = c_mshr.io.status.valid && bc_mshr.io.status.bits.set === c_mshr.io.status.bits.set val mshr_stall_c = false.B val mshr_stall = mshr_stall_abc :+ mshr_stall_bc :+ mshr_stall_c val stall_abc = (mshr_stall_abc zip abc_mshrs) map { case (s, m) => s && m.io.status.valid } if (!params.lastLevel \|\| !params.firstLevel) params.ccover(stall_abc.reduce(_\|\|_), "SCHEDULER_ABC_INTERLOCK", "ABC MSHR interlocked due to pre-emption") if (!params.lastLevel) params.ccover(mshr_stall_bc && bc_mshr.io.status.valid, "SCHEDULER_BC_INTERLOCK", "BC MSHR interlocked due to pre-emption") // Consider scheduling an MSHR only if all the resources it requires are available val mshr_request = Cat((mshrs zip mshr_stall).map { case (m, s) => m.io.schedule.valid && !s && (sourceA.io.req.ready \|\| !m.io.schedule.bits.a.valid) && (sourceB.io.req.ready \|\| !m.io.schedule.bits.b.valid) && (sourceC.io.req.ready \|\| !m.io.schedule.bits.c.valid) && (sourceD.io.req.ready \|\| !m.io.schedule.bits.d.valid) && (sourceE.io.req.ready \|\| !m.io.schedule.bits.e.valid) && (sourceX.io.req.ready \|\| !m.io.schedule.bits.x.valid) && (directory.io.write.ready \|\| !m.io.schedule.bits.dir.valid) }.reverse) // Round-robin arbitration of MSHRs val robin_filter = RegInit(0.U(params.mshrs.W)) val robin_request = Cat(mshr_request, mshr_request & robin_filter) val mshr_selectOH2 = ~(leftOR(robin_request) << 1) & robin_request val mshr_selectOH = mshr_selectOH2(2params.mshrs-1, params.mshrs) \| mshr_selectOH2(params.mshrs-1, 0) val mshr_select = OHToUInt(mshr_selectOH) val schedule = Mux1H(mshr_selectOH, mshrs.map(_.io.schedule.bits)) val scheduleTag = Mux1H(mshr_selectOH, mshrs.map(_.io.status.bits.tag)) val scheduleSet = Mux1H(mshr_selectOH, mshrs.map(_.io.status.bits.set)) // When an MSHR wins the schedule, it has lowest priority next time when (mshr_request.orR) { robin_filter := ~rightOR(mshr_selectOH) } // Fill in which MSHR sends the request schedule.a.bits.source := mshr_select schedule.c.bits.source := Mux(schedule.c.bits.opcode(1), mshr_select, 0.U) // only set for Release[Data] not ProbeAck[Data] schedule.d.bits.sink := mshr_select sourceA.io.req.valid := schedule.a.valid sourceB.io.req.valid := schedule.b.valid sourceC.io.req.valid := schedule.c.valid sourceD.io.req.valid := schedule.d.valid sourceE.io.req.valid := schedule.e.valid sourceX.io.req.valid := schedule.x.valid sourceA.io.req.bits.viewAsSupertype(chiselTypeOf(schedule.a.bits)) := schedule.a.bits sourceB.io.req.bits.viewAsSupertype(chiselTypeOf(schedule.b.bits)) := schedule.b.bits sourceC.io.req.bits.viewAsSupertype(chiselTypeOf(schedule.c.bits)) := schedule.c.bits sourceD.io.req.bits.viewAsSupertype(chiselTypeOf(schedule.d.bits)) := schedule.d.bits sourceE.io.req.bits.viewAsSupertype(chiselTypeOf(schedule.e.bits)) := schedule.e.bits sourceX.io.req.bits.viewAsSupertype(chiselTypeOf(schedule.x.bits)) := schedule.x.bits directory.io.write.valid := schedule.dir.valid directory.io.write.bits.viewAsSupertype(chiselTypeOf(schedule.dir.bits)) := schedule.dir.bits // Forward meta-data changes from nested transaction completion val select_c = mshr_selectOH(params.mshrs-1) val select_bc = mshr_selectOH(params.mshrs-2) nestedwb.set := Mux(select_c, c_mshr.io.status.bits.set, bc_mshr.io.status.bits.set) nestedwb.tag := Mux(select_c, c_mshr.io.status.bits.tag, bc_mshr.io.status.bits.tag) nestedwb.b_toN := select_bc && bc_mshr.io.schedule.bits.dir.valid && bc_mshr.io.schedule.bits.dir.bits.data.state === MetaData.INVALID nestedwb.b_toB := select_bc && bc_mshr.io.schedule.bits.dir.valid && bc_mshr.io.schedule.bits.dir.bits.data.state === MetaData.BRANCH nestedwb.b_clr_dirty := select_bc && bc_mshr.io.schedule.bits.dir.valid nestedwb.c_set_dirty := select_c && c_mshr.io.schedule.bits.dir.valid && c_mshr.io.schedule.bits.dir.bits.data.dirty // Pick highest priority request val request = Wire(Decoupled(new FullRequest(params))) request.valid := directory.io.ready && (sinkA.io.req.valid \|\| sinkX.io.req.valid \|\| sinkC.io.req.valid) request.bits := Mux(sinkC.io.req.valid, sinkC.io.req.bits, Mux(sinkX.io.req.valid, sinkX.io.req.bits, sinkA.io.req.bits)) sinkC.io.req.ready := directory.io.ready && request.ready sinkX.io.req.ready := directory.io.ready && request.ready && !sinkC.io.req.valid sinkA.io.req.ready := directory.io.ready && request.ready && !sinkC.io.req.valid && !sinkX.io.req.valid // If no MSHR has been assigned to this set, we need to allocate one val setMatches = Cat(mshrs.map { m => m.io.status.valid && m.io.status.bits.set === request.bits.set }.reverse) val alloc = !setMatches.orR // NOTE: no matches also means no BC or C pre-emption on this set // If a same-set MSHR says that requests of this type must be blocked (for bounded time), do it val blockB = Mux1H(setMatches, mshrs.map(_.io.status.bits.blockB)) && request.bits.prio(1) val blockC = Mux1H(setMatches, mshrs.map(_.io.status.bits.blockC)) && request.bits.prio(2) // If a same-set MSHR says that requests of this type must be handled out-of-band, use special BC\|C MSHR // ... these special MSHRs interlock the MSHR that said it should be pre-empted. val nestB = Mux1H(setMatches, mshrs.map(_.io.status.bits.nestB)) && request.bits.prio(1) val nestC = Mux1H(setMatches, mshrs.map(_.io.status.bits.nestC)) && request.bits.prio(2) // Prevent priority inversion; we may not queue to MSHRs beyond our level val prioFilter = Cat(request.bits.prio(2), !request.bits.prio(0), ~0.U((params.mshrs-2).W)) val lowerMatches = setMatches & prioFilter // If we match an MSHR <= our priority that neither blocks nor nests us, queue to it. val queue = lowerMatches.orR && !nestB && !nestC && !blockB && !blockC if (!params.lastLevel) { params.ccover(request.valid && blockB, "SCHEDULER_BLOCKB", "Interlock B request while resolving set conflict") params.ccover(request.valid && nestB, "SCHEDULER_NESTB", "Priority escalation from channel B") } if (!params.firstLevel) { params.ccover(request.valid && blockC, "SCHEDULER_BLOCKC", "Interlock C request while resolving set conflict") params.ccover(request.valid && nestC, "SCHEDULER_NESTC", "Priority escalation from channel C") } params.ccover(request.valid && queue, "SCHEDULER_SECONDARY", "Enqueue secondary miss") // It might happen that lowerMatches has >1 bit if the two special MSHRs are in-use // We want to Q to the highest matching priority MSHR. val lowerMatches1 = Mux(lowerMatches(params.mshrs-1), 1.U << (params.mshrs-1), Mux(lowerMatches(params.mshrs-2), 1.U << (params.mshrs-2), lowerMatches)) // If this goes to the scheduled MSHR, it may need to be bypassed // Alternatively, the MSHR may be refilled from a request queued in the ListBuffer val selected_requests = Cat(mshr_selectOH, mshr_selectOH, mshr_selectOH) & requests.io.valid val a_pop = selected_requests((0 + 1) params.mshrs - 1, 0 * params.mshrs).orR val b_pop = selected_requests((1 + 1) * params.mshrs - 1, 1 * params.mshrs).orR val c_pop = selected_requests((2 + 1) * params.mshrs - 1, 2 * params.mshrs).orR val bypassMatches = (mshr_selectOH & lowerMatches1).orR && Mux(c_pop \|\| request.bits.prio(2), !c_pop, Mux(b_pop \|\| request.bits.prio(1), !b_pop, !a_pop)) val may_pop = a_pop \|\| b_pop \|\| c_pop val bypass = request.valid && queue && bypassMatches val will_reload = schedule.reload && (may_pop \|\| bypass) val will_pop = schedule.reload && may_pop && !bypass params.ccover(mshr_selectOH.orR && bypass, "SCHEDULER_BYPASS", "Bypass new request directly to conflicting MSHR") params.ccover(mshr_selectOH.orR && will_reload, "SCHEDULER_RELOAD", "Back-to-back service of two requests") params.ccover(mshr_selectOH.orR && will_pop, "SCHEDULER_POP", "Service of a secondary miss") // Repeat the above logic, but without the fan-in mshrs.zipWithIndex.foreach { case (m, i) => val sel = mshr_selectOH(i) m.io.schedule.ready := sel val a_pop = requests.io.valid(params.mshrs * 0 + i) val b_pop = requests.io.valid(params.mshrs * 1 + i) val c_pop = requests.io.valid(params.mshrs * 2 + i) val bypassMatches = lowerMatches1(i) && Mux(c_pop \|\| request.bits.prio(2), !c_pop, Mux(b_pop \|\| request.bits.prio(1), !b_pop, !a_pop)) val may_pop = a_pop \|\| b_pop \|\| c_pop val bypass = request.valid && queue && bypassMatches val will_reload = m.io.schedule.bits.reload && (may_pop \|\| bypass) m.io.allocate.bits.viewAsSupertype(chiselTypeOf(requests.io.data)) := Mux(bypass, WireInit(new QueuedRequest(params), init = request.bits), requests.io.data) m.io.allocate.bits.set := m.io.status.bits.set m.io.allocate.bits.repeat := m.io.allocate.bits.tag === m.io.status.bits.tag m.io.allocate.valid := sel && will_reload } // Determine which of the queued requests to pop (supposing will_pop) val prio_requests = ~(~requests.io.valid \| (requests.io.valid >> params.mshrs) \| (requests.io.valid >> 2params.mshrs)) val pop_index = OHToUInt(Cat(mshr_selectOH, mshr_selectOH, mshr_selectOH) & prio_requests) requests.io.pop.valid := will_pop requests.io.pop.bits := pop_index // Reload from the Directory if the next MSHR operation changes tags val lb_tag_mismatch = scheduleTag =/= requests.io.data.tag val mshr_uses_directory_assuming_no_bypass = schedule.reload && may_pop && lb_tag_mismatch val mshr_uses_directory_for_lb = will_pop && lb_tag_mismatch val mshr_uses_directory = will_reload && scheduleTag =/= Mux(bypass, request.bits.tag, requests.io.data.tag) // Is there an MSHR free for this request? val mshr_validOH = Cat(mshrs.map(_.io.status.valid).reverse) val mshr_free = (~mshr_validOH & prioFilter).orR // Fanout the request to the appropriate handler (if any) val bypassQueue = schedule.reload && bypassMatches val request_alloc_cases = (alloc && !mshr_uses_directory_assuming_no_bypass && mshr_free) \|\| (nestB && !mshr_uses_directory_assuming_no_bypass && !bc_mshr.io.status.valid && !c_mshr.io.status.valid) \|\| (nestC && !mshr_uses_directory_assuming_no_bypass && !c_mshr.io.status.valid) request.ready := request_alloc_cases \|\| (queue && (bypassQueue \|\| requests.io.push.ready)) val alloc_uses_directory = request.valid && request_alloc_cases // When a request goes through, it will need to hit the Directory directory.io.read.valid := mshr_uses_directory \|\| alloc_uses_directory directory.io.read.bits.set := Mux(mshr_uses_directory_for_lb, scheduleSet, request.bits.set) directory.io.read.bits.tag := Mux(mshr_uses_directory_for_lb, requests.io.data.tag, request.bits.tag) // Enqueue the request if not bypassed directly into an MSHR requests.io.push.valid := request.valid && queue && !bypassQueue requests.io.push.bits.data := request.bits requests.io.push.bits.index := Mux1H( request.bits.prio, Seq( OHToUInt(lowerMatches1 << params.mshrs0), OHToUInt(lowerMatches1 << params.mshrs1), OHToUInt(lowerMatches1 << params.mshrs2))) val mshr_insertOH = ~(leftOR(~mshr_validOH) << 1) & ~mshr_validOH & prioFilter (mshr_insertOH.asBools zip mshrs) map { case (s, m) => when (request.valid && alloc && s && !mshr_uses_directory_assuming_no_bypass) { m.io.allocate.valid := true.B m.io.allocate.bits.viewAsSupertype(chiselTypeOf(request.bits)) := request.bits m.io.allocate.bits.repeat := false.B } } when (request.valid && nestB && !bc_mshr.io.status.valid && !c_mshr.io.status.valid && !mshr_uses_directory_assuming_no_bypass) { bc_mshr.io.allocate.valid := true.B bc_mshr.io.allocate.bits.viewAsSupertype(chiselTypeOf(request.bits)) := request.bits bc_mshr.io.allocate.bits.repeat := false.B assert (!request.bits.prio(0)) } bc_mshr.io.allocate.bits.prio(0) := false.B when (request.valid && nestC && !c_mshr.io.status.valid && !mshr_uses_directory_assuming_no_bypass) { c_mshr.io.allocate.valid := true.B c_mshr.io.allocate.bits.viewAsSupertype(chiselTypeOf(request.bits)) := request.bits c_mshr.io.allocate.bits.repeat := false.B assert (!request.bits.prio(0)) assert (!request.bits.prio(1)) } c_mshr.io.allocate.bits.prio(0) := false.B c_mshr.io.allocate.bits.prio(1) := false.B // Fanout the result of the Directory lookup val dirTarget = Mux(alloc, mshr_insertOH, Mux(nestB,(BigInt(1) << (params.mshrs-2)).U,(BigInt(1) << (params.mshrs-1)).U)) val directoryFanout = params.dirReg(RegNext(Mux(mshr_uses_directory, mshr_selectOH, Mux(alloc_uses_directory, dirTarget, 0.U)))) mshrs.zipWithIndex.foreach { case (m, i) => m.io.directory.valid := directoryFanout(i) m.io.directory.bits := directory.io.result.bits } // MSHR response meta-data fetch sinkC.io.way := Mux(bc_mshr.io.status.valid && bc_mshr.io.status.bits.set === sinkC.io.set, bc_mshr.io.status.bits.way, Mux1H(abc_mshrs.map(m => m.io.status.valid && m.io.status.bits.set === sinkC.io.set), abc_mshrs.map(_.io.status.bits.way))) sinkD.io.way := VecInit(mshrs.map(_.io.status.bits.way))(sinkD.io.source) sinkD.io.set := VecInit(mshrs.map(_.io.status.bits.set))(sinkD.io.source) // Beat buffer connections between components sinkA.io.pb_pop <> sourceD.io.pb_pop sourceD.io.pb_beat := sinkA.io.pb_beat sinkC.io.rel_pop <> sourceD.io.rel_pop sourceD.io.rel_beat := sinkC.io.rel_beat // BankedStore ports bankedStore.io.sinkC_adr <> sinkC.io.bs_adr bankedStore.io.sinkC_dat := sinkC.io.bs_dat bankedStore.io.sinkD_adr <> sinkD.io.bs_adr bankedStore.io.sinkD_dat := sinkD.io.bs_dat bankedStore.io.sourceC_adr <> sourceC.io.bs_adr bankedStore.io.sourceD_radr <> sourceD.io.bs_radr bankedStore.io.sourceD_wadr <> sourceD.io.bs_wadr bankedStore.io.sourceD_wdat := sourceD.io.bs_wdat sourceC.io.bs_dat := bankedStore.io.sourceC_dat sourceD.io.bs_rdat := bankedStore.io.sourceD_rdat // SourceD data hazard interlock sourceD.io.evict_req := sourceC.io.evict_req sourceD.io.grant_req := sinkD .io.grant_req sourceC.io.evict_safe := sourceD.io.evict_safe sinkD .io.grant_safe := sourceD.io.grant_safe private def afmt(x: AddressSet) = s"""{"base":${x.base},"mask":${x.mask}}""" private def addresses = params.inner.manager.managers.flatMap(_.address).map(afmt _).mkString(",") private def setBits = params.addressMapping.drop(params.offsetBits).take(params.setBits).mkString(",") private def tagBits = params.addressMapping.drop(params.offsetBits + params.setBits).take(params.tagBits).mkString(",") private def simple = s""""reset":"${reset.pathName}","tagBits":[${tagBits}],"setBits":[${setBits}],"blockBytes":${params.cache.blockBytes},"ways":${params.cache.ways}""" def json: String = s"""{"addresses":[${addresses}],${simple},"directory":${directory.json},"subbanks":${bankedStore.json}}""" }	module InclusiveCacheBankScheduler( // @[Scheduler.scala:27:7] input clock, // @[Scheduler.scala:27:7] input reset, // @[Scheduler.scala:27:7] output io_in_a_ready, // @[Scheduler.scala:29:14] input io_in_a_valid, // @[Scheduler.scala:29:14] input [2:0] io_in_a_bits_opcode, // @[Scheduler.scala:29:14] input [2:0] io_in_a_bits_param, // @[Scheduler.scala:29:14] input [2:0] io_in_a_bits_size, // @[Scheduler.scala:29:14] input [5:0] io_in_a_bits_source, // @[Scheduler.scala:29:14] input [31:0] io_in_a_bits_address, // @[Scheduler.scala:29:14] input [7:0] io_in_a_bits_mask, // @[Scheduler.scala:29:14] input [63:0] io_in_a_bits_data, // @[Scheduler.scala:29:14] input io_in_a_bits_corrupt, // @[Scheduler.scala:29:14] input io_in_b_ready, // @[Scheduler.scala:29:14] output io_in_b_valid, // @[Scheduler.scala:29:14] output [1:0] io_in_b_bits_param, // @[Scheduler.scala:29:14] output [5:0] io_in_b_bits_source, // @[Scheduler.scala:29:14] output [31:0] io_in_b_bits_address, // @[Scheduler.scala:29:14] output io_in_c_ready, // @[Scheduler.scala:29:14] input io_in_c_valid, // @[Scheduler.scala:29:14] input [2:0] io_in_c_bits_opcode, // @[Scheduler.scala:29:14] input [2:0] io_in_c_bits_param, // @[Scheduler.scala:29:14] input [2:0] io_in_c_bits_size, // @[Scheduler.scala:29:14] input [5:0] io_in_c_bits_source, // @[Scheduler.scala:29:14] input [31:0] io_in_c_bits_address, // @[Scheduler.scala:29:14] input [63:0] io_in_c_bits_data, // @[Scheduler.scala:29:14] input io_in_c_bits_corrupt, // @[Scheduler.scala:29:14] input io_in_d_ready, // @[Scheduler.scala:29:14] output io_in_d_valid, // @[Scheduler.scala:29:14] output [2:0] io_in_d_bits_opcode, // @[Scheduler.scala:29:14] output [1:0] io_in_d_bits_param, // @[Scheduler.scala:29:14] output [2:0] io_in_d_bits_size, // @[Scheduler.scala:29:14] output [5:0] io_in_d_bits_source, // @[Scheduler.scala:29:14] output [2:0] io_in_d_bits_sink, // @[Scheduler.scala:29:14] output io_in_d_bits_denied, // @[Scheduler.scala:29:14] output [63:0] io_in_d_bits_data, // @[Scheduler.scala:29:14] output io_in_d_bits_corrupt, // @[Scheduler.scala:29:14] input io_in_e_valid, // @[Scheduler.scala:29:14] input [2:0] io_in_e_bits_sink, // @[Scheduler.scala:29:14] input io_out_a_ready, // @[Scheduler.scala:29:14] output io_out_a_valid, // @[Scheduler.scala:29:14] output [2:0] io_out_a_bits_opcode, // @[Scheduler.scala:29:14] output [2:0] io_out_a_bits_param, // @[Scheduler.scala:29:14] output [2:0] io_out_a_bits_size, // @[Scheduler.scala:29:14] output [2:0] io_out_a_bits_source, // @[Scheduler.scala:29:14] output [31:0] io_out_a_bits_address, // @[Scheduler.scala:29:14] output [7:0] io_out_a_bits_mask, // @[Scheduler.scala:29:14] output [63:0] io_out_a_bits_data, // @[Scheduler.scala:29:14] output io_out_a_bits_corrupt, // @[Scheduler.scala:29:14] input io_out_c_ready, // @[Scheduler.scala:29:14] output io_out_c_valid, // @[Scheduler.scala:29:14] output [2:0] io_out_c_bits_opcode, // @[Scheduler.scala:29:14] output [2:0] io_out_c_bits_param, // @[Scheduler.scala:29:14] output [2:0] io_out_c_bits_size, // @[Scheduler.scala:29:14] output [2:0] io_out_c_bits_source, // @[Scheduler.scala:29:14] output [31:0] io_out_c_bits_address, // @[Scheduler.scala:29:14] output [63:0] io_out_c_bits_data, // @[Scheduler.scala:29:14] output io_out_c_bits_corrupt, // @[Scheduler.scala:29:14] output io_out_d_ready, // @[Scheduler.scala:29:14] input io_out_d_valid, // @[Scheduler.scala:29:14] input [2:0] io_out_d_bits_opcode, // @[Scheduler.scala:29:14] input [1:0] io_out_d_bits_param, // @[Scheduler.scala:29:14] input [2:0] io_out_d_bits_size, // @[Scheduler.scala:29:14] input [2:0] io_out_d_bits_source, // @[Scheduler.scala:29:14] input [2:0] io_out_d_bits_sink, // @[Scheduler.scala:29:14] input io_out_d_bits_denied, // @[Scheduler.scala:29:14] input [63:0] io_out_d_bits_data, // @[Scheduler.scala:29:14] input io_out_d_bits_corrupt, // @[Scheduler.scala:29:14] output io_out_e_valid, // @[Scheduler.scala:29:14] output [2:0] io_out_e_bits_sink, // @[Scheduler.scala:29:14] output io_req_ready, // @[Scheduler.scala:29:14] input io_req_valid, // @[Scheduler.scala:29:14] input [31:0] io_req_bits_address, // @[Scheduler.scala:29:14] output io_resp_valid // @[Scheduler.scala:29:14] ); wire [12:0] mshrs_6_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70, :295:103, :297:73] wire [12:0] mshrs_5_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70, :287:131, :289:74] wire [12:0] mshrs_4_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70] wire [12:0] mshrs_3_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70] wire [12:0] mshrs_2_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70] wire [12:0] mshrs_1_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70] wire [12:0] mshrs_0_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70] wire [5:0] request_bits_put; // @[Scheduler.scala:163:21] wire [5:0] request_bits_offset; // @[Scheduler.scala:163:21] wire [12:0] request_bits_tag; // @[Scheduler.scala:163:21] wire [5:0] request_bits_source; // @[Scheduler.scala:163:21] wire [2:0] request_bits_size; // @[Scheduler.scala:163:21] wire [2:0] request_bits_param; // @[Scheduler.scala:163:21] wire [2:0] request_bits_opcode; // @[Scheduler.scala:163:21] wire request_bits_control; // @[Scheduler.scala:163:21] wire request_bits_prio_2; // @[Scheduler.scala:163:21] wire request_bits_prio_0; // @[Scheduler.scala:163:21] wire _mshrs_6_io_status_valid; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_6_io_status_bits_set; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_6_io_status_bits_tag; // @[Scheduler.scala:71:46] wire _mshrs_6_io_status_bits_blockB; // @[Scheduler.scala:71:46] wire _mshrs_6_io_status_bits_nestB; // @[Scheduler.scala:71:46] wire _mshrs_6_io_status_bits_blockC; // @[Scheduler.scala:71:46] wire _mshrs_6_io_status_bits_nestC; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_6_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_6_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_6_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_6_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_6_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_6_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_6_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_6_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_6_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_6_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_6_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_6_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_6_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_6_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_6_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_6_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_6_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_6_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_6_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_6_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_6_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_6_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_6_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_6_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_6_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_6_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_6_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_reload; // @[Scheduler.scala:71:46] wire _mshrs_5_io_status_valid; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_5_io_status_bits_set; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_5_io_status_bits_tag; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_5_io_status_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_5_io_status_bits_blockB; // @[Scheduler.scala:71:46] wire _mshrs_5_io_status_bits_nestB; // @[Scheduler.scala:71:46] wire _mshrs_5_io_status_bits_blockC; // @[Scheduler.scala:71:46] wire _mshrs_5_io_status_bits_nestC; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_valid; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_5_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_5_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_5_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_5_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_5_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_5_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_5_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_5_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_5_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_5_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_5_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_5_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_5_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_5_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_5_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_5_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_5_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_5_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_5_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_5_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_5_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_5_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_5_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_5_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_5_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_5_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_5_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_reload; // @[Scheduler.scala:71:46] wire _mshrs_4_io_status_valid; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_4_io_status_bits_set; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_4_io_status_bits_tag; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_4_io_status_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_4_io_status_bits_blockB; // @[Scheduler.scala:71:46] wire _mshrs_4_io_status_bits_nestB; // @[Scheduler.scala:71:46] wire _mshrs_4_io_status_bits_blockC; // @[Scheduler.scala:71:46] wire _mshrs_4_io_status_bits_nestC; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_valid; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_4_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_4_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_4_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_4_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_4_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_4_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_4_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_4_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_4_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_4_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_4_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_4_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_4_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_4_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_4_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_4_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_4_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_4_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_4_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_4_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_4_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_4_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_4_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_4_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_4_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_4_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_4_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_reload; // @[Scheduler.scala:71:46] wire _mshrs_3_io_status_valid; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_3_io_status_bits_set; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_3_io_status_bits_tag; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_3_io_status_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_3_io_status_bits_blockB; // @[Scheduler.scala:71:46] wire _mshrs_3_io_status_bits_nestB; // @[Scheduler.scala:71:46] wire _mshrs_3_io_status_bits_blockC; // @[Scheduler.scala:71:46] wire _mshrs_3_io_status_bits_nestC; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_valid; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_3_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_3_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_3_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_3_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_3_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_3_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_3_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_3_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_3_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_3_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_3_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_3_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_3_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_3_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_3_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_3_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_3_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_3_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_3_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_3_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_3_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_3_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_3_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_3_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_3_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_3_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_3_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_reload; // @[Scheduler.scala:71:46] wire _mshrs_2_io_status_valid; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_2_io_status_bits_set; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_2_io_status_bits_tag; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_2_io_status_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_2_io_status_bits_blockB; // @[Scheduler.scala:71:46] wire _mshrs_2_io_status_bits_nestB; // @[Scheduler.scala:71:46] wire _mshrs_2_io_status_bits_blockC; // @[Scheduler.scala:71:46] wire _mshrs_2_io_status_bits_nestC; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_valid; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_2_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_2_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_2_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_2_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_2_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_2_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_2_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_2_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_2_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_2_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_2_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_2_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_2_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_2_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_2_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_2_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_2_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_2_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_2_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_2_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_2_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_2_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_2_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_2_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_2_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_2_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_2_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_reload; // @[Scheduler.scala:71:46] wire _mshrs_1_io_status_valid; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_1_io_status_bits_set; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_1_io_status_bits_tag; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_1_io_status_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_1_io_status_bits_blockB; // @[Scheduler.scala:71:46] wire _mshrs_1_io_status_bits_nestB; // @[Scheduler.scala:71:46] wire _mshrs_1_io_status_bits_blockC; // @[Scheduler.scala:71:46] wire _mshrs_1_io_status_bits_nestC; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_valid; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_1_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_1_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_1_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_1_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_1_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_1_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_1_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_1_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_1_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_1_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_1_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_1_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_1_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_1_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_1_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_1_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_1_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_1_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_1_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_1_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_1_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_1_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_1_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_1_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_1_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_1_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_1_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_reload; // @[Scheduler.scala:71:46] wire _mshrs_0_io_status_valid; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_0_io_status_bits_set; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_0_io_status_bits_tag; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_0_io_status_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_0_io_status_bits_blockB; // @[Scheduler.scala:71:46] wire _mshrs_0_io_status_bits_nestB; // @[Scheduler.scala:71:46] wire _mshrs_0_io_status_bits_blockC; // @[Scheduler.scala:71:46] wire _mshrs_0_io_status_bits_nestC; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_valid; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_0_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_0_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_0_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_0_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_0_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_0_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_0_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_0_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_0_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_0_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_0_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_0_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_0_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_0_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_0_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_0_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_0_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_0_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_0_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_0_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_0_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_0_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_0_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_0_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_0_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_0_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_0_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_reload; // @[Scheduler.scala:71:46] wire _requests_io_push_ready; // @[Scheduler.scala:70:24] wire [20:0] _requests_io_valid; // @[Scheduler.scala:70:24] wire _requests_io_data_prio_0; // @[Scheduler.scala:70:24] wire _requests_io_data_prio_1; // @[Scheduler.scala:70:24] wire _requests_io_data_prio_2; // @[Scheduler.scala:70:24] wire _requests_io_data_control; // @[Scheduler.scala:70:24] wire [2:0] _requests_io_data_opcode; // @[Scheduler.scala:70:24] wire [2:0] _requests_io_data_param; // @[Scheduler.scala:70:24] wire [2:0] _requests_io_data_size; // @[Scheduler.scala:70:24] wire [5:0] _requests_io_data_source; // @[Scheduler.scala:70:24] wire [12:0] _requests_io_data_tag; // @[Scheduler.scala:70:24] wire [5:0] _requests_io_data_offset; // @[Scheduler.scala:70:24] wire [5:0] _requests_io_data_put; // @[Scheduler.scala:70:24] wire _bankedStore_io_sinkC_adr_ready; // @[Scheduler.scala:69:27] wire _bankedStore_io_sinkD_adr_ready; // @[Scheduler.scala:69:27] wire _bankedStore_io_sourceC_adr_ready; // @[Scheduler.scala:69:27] wire [63:0] _bankedStore_io_sourceC_dat_data; // @[Scheduler.scala:69:27] wire _bankedStore_io_sourceD_radr_ready; // @[Scheduler.scala:69:27] wire [63:0] _bankedStore_io_sourceD_rdat_data; // @[Scheduler.scala:69:27] wire _bankedStore_io_sourceD_wadr_ready; // @[Scheduler.scala:69:27] wire _directory_io_write_ready; // @[Scheduler.scala:68:25] wire _directory_io_result_bits_dirty; // @[Scheduler.scala:68:25] wire [1:0] _directory_io_result_bits_state; // @[Scheduler.scala:68:25] wire [1:0] _directory_io_result_bits_clients; // @[Scheduler.scala:68:25] wire [12:0] _directory_io_result_bits_tag; // @[Scheduler.scala:68:25] wire _directory_io_result_bits_hit; // @[Scheduler.scala:68:25] wire [2:0] _directory_io_result_bits_way; // @[Scheduler.scala:68:25] wire _directory_io_ready; // @[Scheduler.scala:68:25] wire _sinkX_io_req_valid; // @[Scheduler.scala:58:21] wire [12:0] _sinkX_io_req_bits_tag; // @[Scheduler.scala:58:21] wire [9:0] _sinkX_io_req_bits_set; // @[Scheduler.scala:58:21] wire _sinkE_io_resp_valid; // @[Scheduler.scala:57:21] wire [2:0] _sinkE_io_resp_bits_sink; // @[Scheduler.scala:57:21] wire _sinkD_io_resp_valid; // @[Scheduler.scala:56:21] wire _sinkD_io_resp_bits_last; // @[Scheduler.scala:56:21] wire [2:0] _sinkD_io_resp_bits_opcode; // @[Scheduler.scala:56:21] wire [2:0] _sinkD_io_resp_bits_param; // @[Scheduler.scala:56:21] wire [2:0] _sinkD_io_resp_bits_source; // @[Scheduler.scala:56:21] wire [2:0] _sinkD_io_resp_bits_sink; // @[Scheduler.scala:56:21] wire _sinkD_io_resp_bits_denied; // @[Scheduler.scala:56:21] wire [2:0] _sinkD_io_source; // @[Scheduler.scala:56:21] wire _sinkD_io_bs_adr_valid; // @[Scheduler.scala:56:21] wire _sinkD_io_bs_adr_bits_noop; // @[Scheduler.scala:56:21] wire [2:0] _sinkD_io_bs_adr_bits_way; // @[Scheduler.scala:56:21] wire [9:0] _sinkD_io_bs_adr_bits_set; // @[Scheduler.scala:56:21] wire [2:0] _sinkD_io_bs_adr_bits_beat; // @[Scheduler.scala:56:21] wire [63:0] _sinkD_io_bs_dat_data; // @[Scheduler.scala:56:21] wire [9:0] _sinkD_io_grant_req_set; // @[Scheduler.scala:56:21] wire [2:0] _sinkD_io_grant_req_way; // @[Scheduler.scala:56:21] wire _sinkC_io_req_valid; // @[Scheduler.scala:55:21] wire [2:0] _sinkC_io_req_bits_opcode; // @[Scheduler.scala:55:21] wire [2:0] _sinkC_io_req_bits_param; // @[Scheduler.scala:55:21] wire [2:0] _sinkC_io_req_bits_size; // @[Scheduler.scala:55:21] wire [5:0] _sinkC_io_req_bits_source; // @[Scheduler.scala:55:21] wire [12:0] _sinkC_io_req_bits_tag; // @[Scheduler.scala:55:21] wire [5:0] _sinkC_io_req_bits_offset; // @[Scheduler.scala:55:21] wire [5:0] _sinkC_io_req_bits_put; // @[Scheduler.scala:55:21] wire [9:0] _sinkC_io_req_bits_set; // @[Scheduler.scala:55:21] wire _sinkC_io_resp_valid; // @[Scheduler.scala:55:21] wire _sinkC_io_resp_bits_last; // @[Scheduler.scala:55:21] wire [9:0] _sinkC_io_resp_bits_set; // @[Scheduler.scala:55:21] wire [12:0] _sinkC_io_resp_bits_tag; // @[Scheduler.scala:55:21] wire [5:0] _sinkC_io_resp_bits_source; // @[Scheduler.scala:55:21] wire [2:0] _sinkC_io_resp_bits_param; // @[Scheduler.scala:55:21] wire _sinkC_io_resp_bits_data; // @[Scheduler.scala:55:21] wire [9:0] _sinkC_io_set; // @[Scheduler.scala:55:21] wire _sinkC_io_bs_adr_valid; // @[Scheduler.scala:55:21] wire _sinkC_io_bs_adr_bits_noop; // @[Scheduler.scala:55:21] wire [2:0] _sinkC_io_bs_adr_bits_way; // @[Scheduler.scala:55:21] wire [9:0] _sinkC_io_bs_adr_bits_set; // @[Scheduler.scala:55:21] wire [2:0] _sinkC_io_bs_adr_bits_beat; // @[Scheduler.scala:55:21] wire _sinkC_io_bs_adr_bits_mask; // @[Scheduler.scala:55:21] wire [63:0] _sinkC_io_bs_dat_data; // @[Scheduler.scala:55:21] wire _sinkC_io_rel_pop_ready; // @[Scheduler.scala:55:21] wire [63:0] _sinkC_io_rel_beat_data; // @[Scheduler.scala:55:21] wire _sinkC_io_rel_beat_corrupt; // @[Scheduler.scala:55:21] wire _sinkA_io_req_valid; // @[Scheduler.scala:54:21] wire [2:0] _sinkA_io_req_bits_opcode; // @[Scheduler.scala:54:21] wire [2:0] _sinkA_io_req_bits_param; // @[Scheduler.scala:54:21] wire [2:0] _sinkA_io_req_bits_size; // @[Scheduler.scala:54:21] wire [5:0] _sinkA_io_req_bits_source; // @[Scheduler.scala:54:21] wire [12:0] _sinkA_io_req_bits_tag; // @[Scheduler.scala:54:21] wire [5:0] _sinkA_io_req_bits_offset; // @[Scheduler.scala:54:21] wire [5:0] _sinkA_io_req_bits_put; // @[Scheduler.scala:54:21] wire [9:0] _sinkA_io_req_bits_set; // @[Scheduler.scala:54:21] wire _sinkA_io_pb_pop_ready; // @[Scheduler.scala:54:21] wire [63:0] _sinkA_io_pb_beat_data; // @[Scheduler.scala:54:21] wire [7:0] _sinkA_io_pb_beat_mask; // @[Scheduler.scala:54:21] wire _sinkA_io_pb_beat_corrupt; // @[Scheduler.scala:54:21] wire _sourceX_io_req_ready; // @[Scheduler.scala:45:23] wire _sourceE_io_req_ready; // @[Scheduler.scala:44:23] wire _sourceD_io_req_ready; // @[Scheduler.scala:43:23] wire _sourceD_io_pb_pop_valid; // @[Scheduler.scala:43:23] wire [5:0] _sourceD_io_pb_pop_bits_index; // @[Scheduler.scala:43:23] wire _sourceD_io_pb_pop_bits_last; // @[Scheduler.scala:43:23] wire _sourceD_io_rel_pop_valid; // @[Scheduler.scala:43:23] wire [5:0] _sourceD_io_rel_pop_bits_index; // @[Scheduler.scala:43:23] wire _sourceD_io_rel_pop_bits_last; // @[Scheduler.scala:43:23] wire _sourceD_io_bs_radr_valid; // @[Scheduler.scala:43:23] wire [2:0] _sourceD_io_bs_radr_bits_way; // @[Scheduler.scala:43:23] wire [9:0] _sourceD_io_bs_radr_bits_set; // @[Scheduler.scala:43:23] wire [2:0] _sourceD_io_bs_radr_bits_beat; // @[Scheduler.scala:43:23] wire _sourceD_io_bs_radr_bits_mask; // @[Scheduler.scala:43:23] wire _sourceD_io_bs_wadr_valid; // @[Scheduler.scala:43:23] wire [2:0] _sourceD_io_bs_wadr_bits_way; // @[Scheduler.scala:43:23] wire [9:0] _sourceD_io_bs_wadr_bits_set; // @[Scheduler.scala:43:23] wire [2:0] _sourceD_io_bs_wadr_bits_beat; // @[Scheduler.scala:43:23] wire _sourceD_io_bs_wadr_bits_mask; // @[Scheduler.scala:43:23] wire [63:0] _sourceD_io_bs_wdat_data; // @[Scheduler.scala:43:23] wire _sourceD_io_evict_safe; // @[Scheduler.scala:43:23] wire _sourceD_io_grant_safe; // @[Scheduler.scala:43:23] wire _sourceC_io_req_ready; // @[Scheduler.scala:42:23] wire _sourceC_io_bs_adr_valid; // @[Scheduler.scala:42:23] wire [2:0] _sourceC_io_bs_adr_bits_way; // @[Scheduler.scala:42:23] wire [9:0] _sourceC_io_bs_adr_bits_set; // @[Scheduler.scala:42:23] wire [2:0] _sourceC_io_bs_adr_bits_beat; // @[Scheduler.scala:42:23] wire [9:0] _sourceC_io_evict_req_set; // @[Scheduler.scala:42:23] wire [2:0] _sourceC_io_evict_req_way; // @[Scheduler.scala:42:23] wire _sourceB_io_req_ready; // @[Scheduler.scala:41:23] wire _sourceA_io_req_ready; // @[Scheduler.scala:40:23] wire io_in_a_valid_0 = io_in_a_valid; // @[Scheduler.scala:27:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Scheduler.scala:27:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Scheduler.scala:27:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Scheduler.scala:27:7] wire [5:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Scheduler.scala:27:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Scheduler.scala:27:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Scheduler.scala:27:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Scheduler.scala:27:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Scheduler.scala:27:7] wire io_in_b_ready_0 = io_in_b_ready; // @[Scheduler.scala:27:7] wire io_in_c_valid_0 = io_in_c_valid; // @[Scheduler.scala:27:7] wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Scheduler.scala:27:7] wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Scheduler.scala:27:7] wire [2:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Scheduler.scala:27:7] wire [5:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Scheduler.scala:27:7] wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Scheduler.scala:27:7] wire [63:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Scheduler.scala:27:7] wire io_in_c_bits_corrupt_0 = io_in_c_bits_corrupt; // @[Scheduler.scala:27:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Scheduler.scala:27:7] wire io_in_e_valid_0 = io_in_e_valid; // @[Scheduler.scala:27:7] wire [2:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Scheduler.scala:27:7] wire io_out_a_ready_0 = io_out_a_ready; // @[Scheduler.scala:27:7] wire io_out_c_ready_0 = io_out_c_ready; // @[Scheduler.scala:27:7] wire io_out_d_valid_0 = io_out_d_valid; // @[Scheduler.scala:27:7] wire [2:0] io_out_d_bits_opcode_0 = io_out_d_bits_opcode; // @[Scheduler.scala:27:7] wire [1:0] io_out_d_bits_param_0 = io_out_d_bits_param; // @[Scheduler.scala:27:7] wire [2:0] io_out_d_bits_size_0 = io_out_d_bits_size; // @[Scheduler.scala:27:7] wire [2:0] io_out_d_bits_source_0 = io_out_d_bits_source; // @[Scheduler.scala:27:7] wire [2:0] io_out_d_bits_sink_0 = io_out_d_bits_sink; // @[Scheduler.scala:27:7] wire io_out_d_bits_denied_0 = io_out_d_bits_denied; // @[Scheduler.scala:27:7] wire [63:0] io_out_d_bits_data_0 = io_out_d_bits_data; // @[Scheduler.scala:27:7] wire io_out_d_bits_corrupt_0 = io_out_d_bits_corrupt; // @[Scheduler.scala:27:7] wire io_req_valid_0 = io_req_valid; // @[Scheduler.scala:27:7] wire [31:0] io_req_bits_address_0 = io_req_bits_address; // @[Scheduler.scala:27:7] wire io_in_b_bits_corrupt = 1'h0; // @[Scheduler.scala:27:7] wire io_out_b_valid = 1'h0; // @[Scheduler.scala:27:7] wire io_out_b_bits_corrupt = 1'h0; // @[Scheduler.scala:27:7] wire io_resp_bits_fail = 1'h0; // @[Scheduler.scala:27:7] wire schedule_x_bits_fail = 1'h0; // @[Mux.scala:30:73] wire _schedule_WIRE_11_bits_fail = 1'h0; // @[Mux.scala:30:73] wire _schedule_WIRE_12_fail = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_111 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_112 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_113 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_114 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_115 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_116 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_117 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_118 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_119 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_120 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_121 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_122 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_123 = 1'h0; // @[Mux.scala:30:73] wire _schedule_WIRE_13 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_324 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_325 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_338 = 1'h0; // @[Mux.scala:30:73] wire request_bits_prio_1 = 1'h0; // @[Scheduler.scala:163:21] wire _request_bits_T_prio_1 = 1'h0; // @[Scheduler.scala:166:22] wire _request_bits_T_prio_2 = 1'h0; // @[Scheduler.scala:166:22] wire _request_bits_T_1_prio_1 = 1'h0; // @[Scheduler.scala:165:22] wire blockB = 1'h0; // @[Scheduler.scala:175:70] wire nestB = 1'h0; // @[Scheduler.scala:179:70] wire _view__WIRE_prio_1 = 1'h0; // @[Scheduler.scala:233:95] wire _view__WIRE_1_prio_1 = 1'h0; // @[Scheduler.scala:233:95] wire _view__WIRE_2_prio_1 = 1'h0; // @[Scheduler.scala:233:95] wire _view__WIRE_3_prio_1 = 1'h0; // @[Scheduler.scala:233:95] wire _view__WIRE_4_prio_1 = 1'h0; // @[Scheduler.scala:233:95] wire _view__WIRE_5_prio_1 = 1'h0; // @[Scheduler.scala:233:95] wire _view__WIRE_6_prio_1 = 1'h0; // @[Scheduler.scala:233:95] wire _request_alloc_cases_T_4 = 1'h0; // @[Scheduler.scala:259:13] wire _request_alloc_cases_T_6 = 1'h0; // @[Scheduler.scala:259:56] wire _request_alloc_cases_T_8 = 1'h0; // @[Scheduler.scala:259:84] wire [2:0] io_in_b_bits_opcode = 3'h6; // @[Scheduler.scala:27:7] wire [2:0] io_in_b_bits_size = 3'h6; // @[Scheduler.scala:27:7] wire [7:0] io_in_b_bits_mask = 8'hFF; // @[Scheduler.scala:27:7] wire [63:0] io_in_b_bits_data = 64'h0; // @[Scheduler.scala:27:7] wire [63:0] io_out_b_bits_data = 64'h0; // @[Scheduler.scala:27:7] wire io_in_e_ready = 1'h1; // @[Scheduler.scala:27:7] wire io_out_b_ready = 1'h1; // @[Scheduler.scala:27:7] wire io_out_e_ready = 1'h1; // @[Scheduler.scala:27:7] wire io_resp_ready = 1'h1; // @[Scheduler.scala:27:7] wire _mshr_request_T_138 = 1'h1; // @[Scheduler.scala:107:28] wire _request_bits_T_prio_0 = 1'h1; // @[Scheduler.scala:166:22] wire _queue_T_1 = 1'h1; // @[Scheduler.scala:185:35] wire _queue_T_5 = 1'h1; // @[Scheduler.scala:185:55] wire [2:0] io_out_b_bits_opcode = 3'h0; // @[Scheduler.scala:27:7] wire [2:0] io_out_b_bits_size = 3'h0; // @[Scheduler.scala:27:7] wire [2:0] io_out_b_bits_source = 3'h0; // @[Scheduler.scala:27:7] wire [2:0] _schedule_WIRE_19_bits_sink = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_20_sink = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_189 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_190 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_191 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_192 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_193 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_194 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_195 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_196 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_197 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_198 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_199 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_200 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_201 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_23 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_38_bits_source = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_39_source = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_423 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_424 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_425 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_426 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_427 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_428 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_429 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_430 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_431 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_432 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_433 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_434 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_435 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_44 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_55_bits_source = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_56_source = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_553 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_554 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_555 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_556 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_557 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_558 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_559 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_560 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_561 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_562 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_563 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_564 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_565 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_58 = 3'h0; // @[Mux.scala:30:73] wire [1:0] io_out_b_bits_param = 2'h0; // @[Scheduler.scala:27:7] wire [31:0] io_out_b_bits_address = 32'h0; // @[Scheduler.scala:27:7] wire [7:0] io_out_b_bits_mask = 8'h0; // @[Scheduler.scala:27:7] wire [7:0] io_ways_0 = 8'h0; // @[Scheduler.scala:27:7] wire [7:0] io_ways_1 = 8'h0; // @[Scheduler.scala:27:7] wire [7:0] io_ways_2 = 8'h0; // @[Scheduler.scala:27:7] wire [7:0] io_ways_3 = 8'h0; // @[Scheduler.scala:27:7] wire [7:0] io_ways_4 = 8'h0; // @[Scheduler.scala:27:7] wire [7:0] io_ways_5 = 8'h0; // @[Scheduler.scala:27:7] wire [7:0] io_ways_6 = 8'h0; // @[Scheduler.scala:27:7] wire [7:0] io_ways_7 = 8'h0; // @[Scheduler.scala:27:7] wire [7:0] io_ways_8 = 8'h0; // @[Scheduler.scala:27:7] wire [10:0] io_divs_0 = 11'h0; // @[Scheduler.scala:27:7] wire [10:0] io_divs_1 = 11'h0; // @[Scheduler.scala:27:7] wire [10:0] io_divs_2 = 11'h0; // @[Scheduler.scala:27:7] wire [10:0] io_divs_3 = 11'h0; // @[Scheduler.scala:27:7] wire [10:0] io_divs_4 = 11'h0; // @[Scheduler.scala:27:7] wire [10:0] io_divs_5 = 11'h0; // @[Scheduler.scala:27:7] wire [10:0] io_divs_6 = 11'h0; // @[Scheduler.scala:27:7] wire [10:0] io_divs_7 = 11'h0; // @[Scheduler.scala:27:7] wire [10:0] io_divs_8 = 11'h0; // @[Scheduler.scala:27:7] wire [6:0] _lowerMatches1_T_1 = 7'h40; // @[Scheduler.scala:200:43] wire [6:0] _dirTarget_T = 7'h40; // @[Scheduler.scala:306:48] wire [3:0] _requests_io_push_bits_index_T_34 = 4'h0; // @[Mux.scala:30:73] wire [4:0] _prioFilter_T_1 = 5'h1F; // @[Scheduler.scala:182:69] wire [5:0] _lowerMatches1_T_3 = 6'h20; // @[Scheduler.scala:201:43] wire io_in_a_ready_0; // @[Scheduler.scala:27:7] wire [1:0] io_in_b_bits_param_0; // @[Scheduler.scala:27:7] wire [5:0] io_in_b_bits_source_0; // @[Scheduler.scala:27:7] wire [31:0] io_in_b_bits_address_0; // @[Scheduler.scala:27:7] wire io_in_b_valid_0; // @[Scheduler.scala:27:7] wire io_in_c_ready_0; // @[Scheduler.scala:27:7] wire [2:0] io_in_d_bits_opcode_0; // @[Scheduler.scala:27:7] wire [1:0] io_in_d_bits_param_0; // @[Scheduler.scala:27:7] wire [2:0] io_in_d_bits_size_0; // @[Scheduler.scala:27:7] wire [5:0] io_in_d_bits_source_0; // @[Scheduler.scala:27:7] wire [2:0] io_in_d_bits_sink_0; // @[Scheduler.scala:27:7] wire io_in_d_bits_denied_0; // @[Scheduler.scala:27:7] wire [63:0] io_in_d_bits_data_0; // @[Scheduler.scala:27:7] wire io_in_d_bits_corrupt_0; // @[Scheduler.scala:27:7] wire io_in_d_valid_0; // @[Scheduler.scala:27:7] wire [2:0] io_out_a_bits_opcode_0; // @[Scheduler.scala:27:7] wire [2:0] io_out_a_bits_param_0; // @[Scheduler.scala:27:7] wire [2:0] io_out_a_bits_size_0; // @[Scheduler.scala:27:7] wire [2:0] io_out_a_bits_source_0; // @[Scheduler.scala:27:7] wire [31:0] io_out_a_bits_address_0; // @[Scheduler.scala:27:7] wire [7:0] io_out_a_bits_mask_0; // @[Scheduler.scala:27:7] wire [63:0] io_out_a_bits_data_0; // @[Scheduler.scala:27:7] wire io_out_a_bits_corrupt_0; // @[Scheduler.scala:27:7] wire io_out_a_valid_0; // @[Scheduler.scala:27:7] wire [2:0] io_out_c_bits_opcode_0; // @[Scheduler.scala:27:7] wire [2:0] io_out_c_bits_param_0; // @[Scheduler.scala:27:7] wire [2:0] io_out_c_bits_size_0; // @[Scheduler.scala:27:7] wire [2:0] io_out_c_bits_source_0; // @[Scheduler.scala:27:7] wire [31:0] io_out_c_bits_address_0; // @[Scheduler.scala:27:7] wire [63:0] io_out_c_bits_data_0; // @[Scheduler.scala:27:7] wire io_out_c_bits_corrupt_0; // @[Scheduler.scala:27:7] wire io_out_c_valid_0; // @[Scheduler.scala:27:7] wire io_out_d_ready_0; // @[Scheduler.scala:27:7] wire [2:0] io_out_e_bits_sink_0; // @[Scheduler.scala:27:7] wire io_out_e_valid_0; // @[Scheduler.scala:27:7] wire io_req_ready_0; // @[Scheduler.scala:27:7] wire io_resp_valid_0; // @[Scheduler.scala:27:7] wire [9:0] _nestedwb_set_T; // @[Scheduler.scala:155:24] wire [12:0] _nestedwb_tag_T; // @[Scheduler.scala:156:24] wire _nestedwb_b_toN_T_2; // @[Scheduler.scala:157:75] wire _nestedwb_b_toB_T_2; // @[Scheduler.scala:158:75] wire _nestedwb_b_clr_dirty_T; // @[Scheduler.scala:159:37] wire _nestedwb_c_set_dirty_T_1; // @[Scheduler.scala:160:75] wire [9:0] nestedwb_set; // @[Scheduler.scala:75:22] wire [12:0] nestedwb_tag; // @[Scheduler.scala:75:22] wire nestedwb_b_toN; // @[Scheduler.scala:75:22] wire nestedwb_b_toB; // @[Scheduler.scala:75:22] wire nestedwb_b_clr_dirty; // @[Scheduler.scala:75:22] wire nestedwb_c_set_dirty; // @[Scheduler.scala:75:22] wire _mshrs_0_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_0_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71] wire _mshrs_0_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_0_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}] wire _mshrs_0_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 3'h0; // @[Scheduler.scala:56:21, :80:74] wire _mshrs_0_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_0_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}] wire _mshrs_0_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 3'h0; // @[Scheduler.scala:57:21, :81:74] wire _mshrs_0_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_0_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}] wire _mshrs_1_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_1_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71] wire _mshrs_1_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_1_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}] wire _mshrs_1_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 3'h1; // @[Scheduler.scala:56:21, :80:74] wire _mshrs_1_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_1_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}] wire _mshrs_1_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 3'h1; // @[Scheduler.scala:57:21, :81:74] wire _mshrs_1_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_1_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}] wire _mshrs_2_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_2_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71] wire _mshrs_2_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_2_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}] wire _mshrs_2_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 3'h2; // @[Scheduler.scala:56:21, :80:74] wire _mshrs_2_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_2_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}] wire _mshrs_2_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 3'h2; // @[Scheduler.scala:57:21, :81:74] wire _mshrs_2_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_2_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}] wire _mshrs_3_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_3_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71] wire _mshrs_3_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_3_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}] wire _mshrs_3_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 3'h3; // @[Scheduler.scala:56:21, :80:74] wire _mshrs_3_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_3_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}] wire _mshrs_3_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 3'h3; // @[Scheduler.scala:57:21, :81:74] wire _mshrs_3_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_3_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}] wire _mshrs_4_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_4_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71] wire _mshrs_4_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_4_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}] wire _mshrs_4_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 3'h4; // @[Scheduler.scala:56:21, :80:74] wire _mshrs_4_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_4_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}] wire _mshrs_4_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 3'h4; // @[Scheduler.scala:57:21, :81:74] wire _mshrs_4_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_4_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}] wire _mshrs_5_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_5_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71] wire _mshrs_5_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_5_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}] wire _mshrs_5_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 3'h5; // @[Scheduler.scala:56:21, :80:74] wire _mshrs_5_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_5_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}] wire _mshrs_5_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 3'h5; // @[Scheduler.scala:57:21, :81:74] wire _mshrs_5_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_5_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}] wire _mshrs_6_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_6_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71] wire _mshrs_6_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_6_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}] wire _mshrs_6_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 3'h6; // @[Scheduler.scala:56:21, :80:74] wire _mshrs_6_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_6_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}] wire _mshrs_6_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 3'h6; // @[Scheduler.scala:57:21, :81:74] wire _mshrs_6_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_6_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}] wire _mshr_stall_abc_T = _mshrs_0_io_status_bits_set == _mshrs_5_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54] wire _mshr_stall_abc_T_1 = _mshrs_5_io_status_valid & _mshr_stall_abc_T; // @[Scheduler.scala:71:46, :90:{30,54}] wire _mshr_stall_abc_T_2 = _mshrs_0_io_status_bits_set == _mshrs_6_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54] wire _mshr_stall_abc_T_3 = _mshrs_6_io_status_valid & _mshr_stall_abc_T_2; // @[Scheduler.scala:71:46, :91:{30,54}] wire mshr_stall_abc_0 = _mshr_stall_abc_T_1 \| _mshr_stall_abc_T_3; // @[Scheduler.scala:90:{30,86}, :91:30] wire _mshr_stall_abc_T_4 = _mshrs_1_io_status_bits_set == _mshrs_5_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54] wire _mshr_stall_abc_T_5 = _mshrs_5_io_status_valid & _mshr_stall_abc_T_4; // @[Scheduler.scala:71:46, :90:{30,54}] wire _mshr_stall_abc_T_6 = _mshrs_1_io_status_bits_set == _mshrs_6_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54] wire _mshr_stall_abc_T_7 = _mshrs_6_io_status_valid & _mshr_stall_abc_T_6; // @[Scheduler.scala:71:46, :91:{30,54}] wire mshr_stall_abc_1 = _mshr_stall_abc_T_5 \| _mshr_stall_abc_T_7; // @[Scheduler.scala:90:{30,86}, :91:30] wire _mshr_stall_abc_T_8 = _mshrs_2_io_status_bits_set == _mshrs_5_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54] wire _mshr_stall_abc_T_9 = _mshrs_5_io_status_valid & _mshr_stall_abc_T_8; // @[Scheduler.scala:71:46, :90:{30,54}] wire _mshr_stall_abc_T_10 = _mshrs_2_io_status_bits_set == _mshrs_6_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54] wire _mshr_stall_abc_T_11 = _mshrs_6_io_status_valid & _mshr_stall_abc_T_10; // @[Scheduler.scala:71:46, :91:{30,54}] wire mshr_stall_abc_2 = _mshr_stall_abc_T_9 \| _mshr_stall_abc_T_11; // @[Scheduler.scala:90:{30,86}, :91:30] wire _mshr_stall_abc_T_12 = _mshrs_3_io_status_bits_set == _mshrs_5_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54] wire _mshr_stall_abc_T_13 = _mshrs_5_io_status_valid & _mshr_stall_abc_T_12; // @[Scheduler.scala:71:46, :90:{30,54}] wire _mshr_stall_abc_T_14 = _mshrs_3_io_status_bits_set == _mshrs_6_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54] wire _mshr_stall_abc_T_15 = _mshrs_6_io_status_valid & _mshr_stall_abc_T_14; // @[Scheduler.scala:71:46, :91:{30,54}] wire mshr_stall_abc_3 = _mshr_stall_abc_T_13 \| _mshr_stall_abc_T_15; // @[Scheduler.scala:90:{30,86}, :91:30] wire _mshr_stall_abc_T_16 = _mshrs_4_io_status_bits_set == _mshrs_5_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54] wire _mshr_stall_abc_T_17 = _mshrs_5_io_status_valid & _mshr_stall_abc_T_16; // @[Scheduler.scala:71:46, :90:{30,54}] wire _mshr_stall_abc_T_18 = _mshrs_4_io_status_bits_set == _mshrs_6_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54] wire _mshr_stall_abc_T_19 = _mshrs_6_io_status_valid & _mshr_stall_abc_T_18; // @[Scheduler.scala:71:46, :91:{30,54}] wire mshr_stall_abc_4 = _mshr_stall_abc_T_17 \| _mshr_stall_abc_T_19; // @[Scheduler.scala:90:{30,86}, :91:30] wire _mshr_stall_bc_T = _mshrs_5_io_status_bits_set == _mshrs_6_io_status_bits_set; // @[Scheduler.scala:71:46, :94:58] wire mshr_stall_bc = _mshrs_6_io_status_valid & _mshr_stall_bc_T; // @[Scheduler.scala:71:46, :94:{28,58}] wire stall_abc_0 = mshr_stall_abc_0 & _mshrs_0_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73] wire stall_abc_1 = mshr_stall_abc_1 & _mshrs_1_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73] wire stall_abc_2 = mshr_stall_abc_2 & _mshrs_2_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73] wire stall_abc_3 = mshr_stall_abc_3 & _mshrs_3_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73] wire stall_abc_4 = mshr_stall_abc_4 & _mshrs_4_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73] wire _mshr_request_T = ~mshr_stall_abc_0; // @[Scheduler.scala:90:86, :107:28] wire _mshr_request_T_1 = _mshrs_0_io_schedule_valid & _mshr_request_T; // @[Scheduler.scala:71:46, :107:{25,28}] wire _mshr_request_T_2 = ~_mshrs_0_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32] wire _mshr_request_T_3 = _sourceA_io_req_ready \| _mshr_request_T_2; // @[Scheduler.scala:40:23, :108:{29,32}] wire _mshr_request_T_4 = _mshr_request_T_1 & _mshr_request_T_3; // @[Scheduler.scala:107:{25,31}, :108:29] wire _mshr_request_T_5 = ~_mshrs_0_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32] wire _mshr_request_T_6 = _sourceB_io_req_ready \| _mshr_request_T_5; // @[Scheduler.scala:41:23, :109:{29,32}] wire _mshr_request_T_7 = _mshr_request_T_4 & _mshr_request_T_6; // @[Scheduler.scala:107:31, :108:61, :109:29] wire _mshr_request_T_8 = ~_mshrs_0_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32] wire _mshr_request_T_9 = _sourceC_io_req_ready \| _mshr_request_T_8; // @[Scheduler.scala:42:23, :110:{29,32}] wire _mshr_request_T_10 = _mshr_request_T_7 & _mshr_request_T_9; // @[Scheduler.scala:108:61, :109:61, :110:29] wire _mshr_request_T_11 = ~_mshrs_0_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32] wire _mshr_request_T_12 = _sourceD_io_req_ready \| _mshr_request_T_11; // @[Scheduler.scala:43:23, :111:{29,32}] wire _mshr_request_T_13 = _mshr_request_T_10 & _mshr_request_T_12; // @[Scheduler.scala:109:61, :110:61, :111:29] wire _mshr_request_T_14 = ~_mshrs_0_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32] wire _mshr_request_T_15 = _sourceE_io_req_ready \| _mshr_request_T_14; // @[Scheduler.scala:44:23, :112:{29,32}] wire _mshr_request_T_16 = _mshr_request_T_13 & _mshr_request_T_15; // @[Scheduler.scala:110:61, :111:61, :112:29] wire _mshr_request_T_17 = ~_mshrs_0_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32] wire _mshr_request_T_18 = _sourceX_io_req_ready \| _mshr_request_T_17; // @[Scheduler.scala:45:23, :113:{29,32}] wire _mshr_request_T_19 = _mshr_request_T_16 & _mshr_request_T_18; // @[Scheduler.scala:111:61, :112:61, :113:29] wire _mshr_request_T_20 = ~_mshrs_0_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36] wire _mshr_request_T_21 = _directory_io_write_ready \| _mshr_request_T_20; // @[Scheduler.scala:68:25, :114:{33,36}] wire _mshr_request_T_22 = _mshr_request_T_19 & _mshr_request_T_21; // @[Scheduler.scala:112:61, :113:61, :114:33] wire _mshr_request_T_23 = ~mshr_stall_abc_1; // @[Scheduler.scala:90:86, :107:28] wire _mshr_request_T_24 = _mshrs_1_io_schedule_valid & _mshr_request_T_23; // @[Scheduler.scala:71:46, :107:{25,28}] wire _mshr_request_T_25 = ~_mshrs_1_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32] wire _mshr_request_T_26 = _sourceA_io_req_ready \| _mshr_request_T_25; // @[Scheduler.scala:40:23, :108:{29,32}] wire _mshr_request_T_27 = _mshr_request_T_24 & _mshr_request_T_26; // @[Scheduler.scala:107:{25,31}, :108:29] wire _mshr_request_T_28 = ~_mshrs_1_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32] wire _mshr_request_T_29 = _sourceB_io_req_ready \| _mshr_request_T_28; // @[Scheduler.scala:41:23, :109:{29,32}] wire _mshr_request_T_30 = _mshr_request_T_27 & _mshr_request_T_29; // @[Scheduler.scala:107:31, :108:61, :109:29] wire _mshr_request_T_31 = ~_mshrs_1_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32] wire _mshr_request_T_32 = _sourceC_io_req_ready \| _mshr_request_T_31; // @[Scheduler.scala:42:23, :110:{29,32}] wire _mshr_request_T_33 = _mshr_request_T_30 & _mshr_request_T_32; // @[Scheduler.scala:108:61, :109:61, :110:29] wire _mshr_request_T_34 = ~_mshrs_1_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32] wire _mshr_request_T_35 = _sourceD_io_req_ready \| _mshr_request_T_34; // @[Scheduler.scala:43:23, :111:{29,32}] wire _mshr_request_T_36 = _mshr_request_T_33 & _mshr_request_T_35; // @[Scheduler.scala:109:61, :110:61, :111:29] wire _mshr_request_T_37 = ~_mshrs_1_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32] wire _mshr_request_T_38 = _sourceE_io_req_ready \| _mshr_request_T_37; // @[Scheduler.scala:44:23, :112:{29,32}] wire _mshr_request_T_39 = _mshr_request_T_36 & _mshr_request_T_38; // @[Scheduler.scala:110:61, :111:61, :112:29] wire _mshr_request_T_40 = ~_mshrs_1_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32] wire _mshr_request_T_41 = _sourceX_io_req_ready \| _mshr_request_T_40; // @[Scheduler.scala:45:23, :113:{29,32}] wire _mshr_request_T_42 = _mshr_request_T_39 & _mshr_request_T_41; // @[Scheduler.scala:111:61, :112:61, :113:29] wire _mshr_request_T_43 = ~_mshrs_1_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36] wire _mshr_request_T_44 = _directory_io_write_ready \| _mshr_request_T_43; // @[Scheduler.scala:68:25, :114:{33,36}] wire _mshr_request_T_45 = _mshr_request_T_42 & _mshr_request_T_44; // @[Scheduler.scala:112:61, :113:61, :114:33] wire _mshr_request_T_46 = ~mshr_stall_abc_2; // @[Scheduler.scala:90:86, :107:28] wire _mshr_request_T_47 = _mshrs_2_io_schedule_valid & _mshr_request_T_46; // @[Scheduler.scala:71:46, :107:{25,28}] wire _mshr_request_T_48 = ~_mshrs_2_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32] wire _mshr_request_T_49 = _sourceA_io_req_ready \| _mshr_request_T_48; // @[Scheduler.scala:40:23, :108:{29,32}] wire _mshr_request_T_50 = _mshr_request_T_47 & _mshr_request_T_49; // @[Scheduler.scala:107:{25,31}, :108:29] wire _mshr_request_T_51 = ~_mshrs_2_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32] wire _mshr_request_T_52 = _sourceB_io_req_ready \| _mshr_request_T_51; // @[Scheduler.scala:41:23, :109:{29,32}] wire _mshr_request_T_53 = _mshr_request_T_50 & _mshr_request_T_52; // @[Scheduler.scala:107:31, :108:61, :109:29] wire _mshr_request_T_54 = ~_mshrs_2_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32] wire _mshr_request_T_55 = _sourceC_io_req_ready \| _mshr_request_T_54; // @[Scheduler.scala:42:23, :110:{29,32}] wire _mshr_request_T_56 = _mshr_request_T_53 & _mshr_request_T_55; // @[Scheduler.scala:108:61, :109:61, :110:29] wire _mshr_request_T_57 = ~_mshrs_2_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32] wire _mshr_request_T_58 = _sourceD_io_req_ready \| _mshr_request_T_57; // @[Scheduler.scala:43:23, :111:{29,32}] wire _mshr_request_T_59 = _mshr_request_T_56 & _mshr_request_T_58; // @[Scheduler.scala:109:61, :110:61, :111:29] wire _mshr_request_T_60 = ~_mshrs_2_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32] wire _mshr_request_T_61 = _sourceE_io_req_ready \| _mshr_request_T_60; // @[Scheduler.scala:44:23, :112:{29,32}] wire _mshr_request_T_62 = _mshr_request_T_59 & _mshr_request_T_61; // @[Scheduler.scala:110:61, :111:61, :112:29] wire _mshr_request_T_63 = ~_mshrs_2_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32] wire _mshr_request_T_64 = _sourceX_io_req_ready \| _mshr_request_T_63; // @[Scheduler.scala:45:23, :113:{29,32}] wire _mshr_request_T_65 = _mshr_request_T_62 & _mshr_request_T_64; // @[Scheduler.scala:111:61, :112:61, :113:29] wire _mshr_request_T_66 = ~_mshrs_2_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36] wire _mshr_request_T_67 = _directory_io_write_ready \| _mshr_request_T_66; // @[Scheduler.scala:68:25, :114:{33,36}] wire _mshr_request_T_68 = _mshr_request_T_65 & _mshr_request_T_67; // @[Scheduler.scala:112:61, :113:61, :114:33] wire _mshr_request_T_69 = ~mshr_stall_abc_3; // @[Scheduler.scala:90:86, :107:28] wire _mshr_request_T_70 = _mshrs_3_io_schedule_valid & _mshr_request_T_69; // @[Scheduler.scala:71:46, :107:{25,28}] wire _mshr_request_T_71 = ~_mshrs_3_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32] wire _mshr_request_T_72 = _sourceA_io_req_ready \| _mshr_request_T_71; // @[Scheduler.scala:40:23, :108:{29,32}] wire _mshr_request_T_73 = _mshr_request_T_70 & _mshr_request_T_72; // @[Scheduler.scala:107:{25,31}, :108:29] wire _mshr_request_T_74 = ~_mshrs_3_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32] wire _mshr_request_T_75 = _sourceB_io_req_ready \| _mshr_request_T_74; // @[Scheduler.scala:41:23, :109:{29,32}] wire _mshr_request_T_76 = _mshr_request_T_73 & _mshr_request_T_75; // @[Scheduler.scala:107:31, :108:61, :109:29] wire _mshr_request_T_77 = ~_mshrs_3_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32] wire _mshr_request_T_78 = _sourceC_io_req_ready \| _mshr_request_T_77; // @[Scheduler.scala:42:23, :110:{29,32}] wire _mshr_request_T_79 = _mshr_request_T_76 & _mshr_request_T_78; // @[Scheduler.scala:108:61, :109:61, :110:29] wire _mshr_request_T_80 = ~_mshrs_3_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32] wire _mshr_request_T_81 = _sourceD_io_req_ready \| _mshr_request_T_80; // @[Scheduler.scala:43:23, :111:{29,32}] wire _mshr_request_T_82 = _mshr_request_T_79 & _mshr_request_T_81; // @[Scheduler.scala:109:61, :110:61, :111:29] wire _mshr_request_T_83 = ~_mshrs_3_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32] wire _mshr_request_T_84 = _sourceE_io_req_ready \| _mshr_request_T_83; // @[Scheduler.scala:44:23, :112:{29,32}] wire _mshr_request_T_85 = _mshr_request_T_82 & _mshr_request_T_84; // @[Scheduler.scala:110:61, :111:61, :112:29] wire _mshr_request_T_86 = ~_mshrs_3_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32] wire _mshr_request_T_87 = _sourceX_io_req_ready \| _mshr_request_T_86; // @[Scheduler.scala:45:23, :113:{29,32}] wire _mshr_request_T_88 = _mshr_request_T_85 & _mshr_request_T_87; // @[Scheduler.scala:111:61, :112:61, :113:29] wire _mshr_request_T_89 = ~_mshrs_3_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36] wire _mshr_request_T_90 = _directory_io_write_ready \| _mshr_request_T_89; // @[Scheduler.scala:68:25, :114:{33,36}] wire _mshr_request_T_91 = _mshr_request_T_88 & _mshr_request_T_90; // @[Scheduler.scala:112:61, :113:61, :114:33] wire _mshr_request_T_92 = ~mshr_stall_abc_4; // @[Scheduler.scala:90:86, :107:28] wire _mshr_request_T_93 = _mshrs_4_io_schedule_valid & _mshr_request_T_92; // @[Scheduler.scala:71:46, :107:{25,28}] wire _mshr_request_T_94 = ~_mshrs_4_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32] wire _mshr_request_T_95 = _sourceA_io_req_ready \| _mshr_request_T_94; // @[Scheduler.scala:40:23, :108:{29,32}] wire _mshr_request_T_96 = _mshr_request_T_93 & _mshr_request_T_95; // @[Scheduler.scala:107:{25,31}, :108:29] wire _mshr_request_T_97 = ~_mshrs_4_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32] wire _mshr_request_T_98 = _sourceB_io_req_ready \| _mshr_request_T_97; // @[Scheduler.scala:41:23, :109:{29,32}] wire _mshr_request_T_99 = _mshr_request_T_96 & _mshr_request_T_98; // @[Scheduler.scala:107:31, :108:61, :109:29] wire _mshr_request_T_100 = ~_mshrs_4_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32] wire _mshr_request_T_101 = _sourceC_io_req_ready \| _mshr_request_T_100; // @[Scheduler.scala:42:23, :110:{29,32}] wire _mshr_request_T_102 = _mshr_request_T_99 & _mshr_request_T_101; // @[Scheduler.scala:108:61, :109:61, :110:29] wire _mshr_request_T_103 = ~_mshrs_4_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32] wire _mshr_request_T_104 = _sourceD_io_req_ready \| _mshr_request_T_103; // @[Scheduler.scala:43:23, :111:{29,32}] wire _mshr_request_T_105 = _mshr_request_T_102 & _mshr_request_T_104; // @[Scheduler.scala:109:61, :110:61, :111:29] wire _mshr_request_T_106 = ~_mshrs_4_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32] wire _mshr_request_T_107 = _sourceE_io_req_ready \| _mshr_request_T_106; // @[Scheduler.scala:44:23, :112:{29,32}] wire _mshr_request_T_108 = _mshr_request_T_105 & _mshr_request_T_107; // @[Scheduler.scala:110:61, :111:61, :112:29] wire _mshr_request_T_109 = ~_mshrs_4_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32] wire _mshr_request_T_110 = _sourceX_io_req_ready \| _mshr_request_T_109; // @[Scheduler.scala:45:23, :113:{29,32}] wire _mshr_request_T_111 = _mshr_request_T_108 & _mshr_request_T_110; // @[Scheduler.scala:111:61, :112:61, :113:29] wire _mshr_request_T_112 = ~_mshrs_4_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36] wire _mshr_request_T_113 = _directory_io_write_ready \| _mshr_request_T_112; // @[Scheduler.scala:68:25, :114:{33,36}] wire _mshr_request_T_114 = _mshr_request_T_111 & _mshr_request_T_113; // @[Scheduler.scala:112:61, :113:61, :114:33] wire _mshr_request_T_115 = ~mshr_stall_bc; // @[Scheduler.scala:94:28, :107:28] wire _mshr_request_T_116 = _mshrs_5_io_schedule_valid & _mshr_request_T_115; // @[Scheduler.scala:71:46, :107:{25,28}] wire _mshr_request_T_117 = ~_mshrs_5_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32] wire _mshr_request_T_118 = _sourceA_io_req_ready \| _mshr_request_T_117; // @[Scheduler.scala:40:23, :108:{29,32}] wire _mshr_request_T_119 = _mshr_request_T_116 & _mshr_request_T_118; // @[Scheduler.scala:107:{25,31}, :108:29] wire _mshr_request_T_120 = ~_mshrs_5_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32] wire _mshr_request_T_121 = _sourceB_io_req_ready \| _mshr_request_T_120; // @[Scheduler.scala:41:23, :109:{29,32}] wire _mshr_request_T_122 = _mshr_request_T_119 & _mshr_request_T_121; // @[Scheduler.scala:107:31, :108:61, :109:29] wire _mshr_request_T_123 = ~_mshrs_5_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32] wire _mshr_request_T_124 = _sourceC_io_req_ready \| _mshr_request_T_123; // @[Scheduler.scala:42:23, :110:{29,32}] wire _mshr_request_T_125 = _mshr_request_T_122 & _mshr_request_T_124; // @[Scheduler.scala:108:61, :109:61, :110:29] wire _mshr_request_T_126 = ~_mshrs_5_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32] wire _mshr_request_T_127 = _sourceD_io_req_ready \| _mshr_request_T_126; // @[Scheduler.scala:43:23, :111:{29,32}] wire _mshr_request_T_128 = _mshr_request_T_125 & _mshr_request_T_127; // @[Scheduler.scala:109:61, :110:61, :111:29] wire _mshr_request_T_129 = ~_mshrs_5_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32] wire _mshr_request_T_130 = _sourceE_io_req_ready \| _mshr_request_T_129; // @[Scheduler.scala:44:23, :112:{29,32}] wire _mshr_request_T_131 = _mshr_request_T_128 & _mshr_request_T_130; // @[Scheduler.scala:110:61, :111:61, :112:29] wire _mshr_request_T_132 = ~_mshrs_5_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32] wire _mshr_request_T_133 = _sourceX_io_req_ready \| _mshr_request_T_132; // @[Scheduler.scala:45:23, :113:{29,32}] wire _mshr_request_T_134 = _mshr_request_T_131 & _mshr_request_T_133; // @[Scheduler.scala:111:61, :112:61, :113:29] wire _mshr_request_T_135 = ~_mshrs_5_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36] wire _mshr_request_T_136 = _directory_io_write_ready \| _mshr_request_T_135; // @[Scheduler.scala:68:25, :114:{33,36}] wire _mshr_request_T_137 = _mshr_request_T_134 & _mshr_request_T_136; // @[Scheduler.scala:112:61, :113:61, :114:33] wire _mshr_request_T_140 = ~_mshrs_6_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32] wire _mshr_request_T_141 = _sourceA_io_req_ready \| _mshr_request_T_140; // @[Scheduler.scala:40:23, :108:{29,32}] wire _mshr_request_T_139; // @[Scheduler.scala:107:25] wire _mshr_request_T_142 = _mshr_request_T_139 & _mshr_request_T_141; // @[Scheduler.scala:107:{25,31}, :108:29] wire _mshr_request_T_143 = ~_mshrs_6_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32] wire _mshr_request_T_144 = _sourceB_io_req_ready \| _mshr_request_T_143; // @[Scheduler.scala:41:23, :109:{29,32}] wire _mshr_request_T_145 = _mshr_request_T_142 & _mshr_request_T_144; // @[Scheduler.scala:107:31, :108:61, :109:29] wire _mshr_request_T_146 = ~_mshrs_6_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32] wire _mshr_request_T_147 = _sourceC_io_req_ready \| _mshr_request_T_146; // @[Scheduler.scala:42:23, :110:{29,32}] wire _mshr_request_T_148 = _mshr_request_T_145 & _mshr_request_T_147; // @[Scheduler.scala:108:61, :109:61, :110:29] wire _mshr_request_T_149 = ~_mshrs_6_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32] wire _mshr_request_T_150 = _sourceD_io_req_ready \| _mshr_request_T_149; // @[Scheduler.scala:43:23, :111:{29,32}] wire _mshr_request_T_151 = _mshr_request_T_148 & _mshr_request_T_150; // @[Scheduler.scala:109:61, :110:61, :111:29] wire _mshr_request_T_152 = ~_mshrs_6_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32] wire _mshr_request_T_153 = _sourceE_io_req_ready \| _mshr_request_T_152; // @[Scheduler.scala:44:23, :112:{29,32}] wire _mshr_request_T_154 = _mshr_request_T_151 & _mshr_request_T_153; // @[Scheduler.scala:110:61, :111:61, :112:29] wire _mshr_request_T_155 = ~_mshrs_6_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32] wire _mshr_request_T_156 = _sourceX_io_req_ready \| _mshr_request_T_155; // @[Scheduler.scala:45:23, :113:{29,32}] wire _mshr_request_T_157 = _mshr_request_T_154 & _mshr_request_T_156; // @[Scheduler.scala:111:61, :112:61, :113:29] wire _mshr_request_T_158 = ~_mshrs_6_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36] wire _mshr_request_T_159 = _directory_io_write_ready \| _mshr_request_T_158; // @[Scheduler.scala:68:25, :114:{33,36}] wire _mshr_request_T_160 = _mshr_request_T_157 & _mshr_request_T_159; // @[Scheduler.scala:112:61, :113:61, :114:33] wire [1:0] mshr_request_lo_hi = {_mshr_request_T_68, _mshr_request_T_45}; // @[Scheduler.scala:106:25, :113:61] wire [2:0] mshr_request_lo = {mshr_request_lo_hi, _mshr_request_T_22}; // @[Scheduler.scala:106:25, :113:61] wire [1:0] mshr_request_hi_lo = {_mshr_request_T_114, _mshr_request_T_91}; // @[Scheduler.scala:106:25, :113:61] wire [1:0] mshr_request_hi_hi = {_mshr_request_T_160, _mshr_request_T_137}; // @[Scheduler.scala:106:25, :113:61] wire [3:0] mshr_request_hi = {mshr_request_hi_hi, mshr_request_hi_lo}; // @[Scheduler.scala:106:25] wire [6:0] mshr_request = {mshr_request_hi, mshr_request_lo}; // @[Scheduler.scala:106:25] reg [6:0] robin_filter; // @[Scheduler.scala:118:29] wire [6:0] _robin_request_T = mshr_request & robin_filter; // @[Scheduler.scala:106:25, :118:29, :119:54] wire [13:0] robin_request = {mshr_request, _robin_request_T}; // @[Scheduler.scala:106:25, :119:{26,54}] wire [14:0] _mshr_selectOH2_T = {robin_request, 1'h0}; // @[package.scala:253:48] wire [13:0] _mshr_selectOH2_T_1 = _mshr_selectOH2_T[13:0]; // @[package.scala:253:{48,53}] wire [13:0] _mshr_selectOH2_T_2 = robin_request \| _mshr_selectOH2_T_1; // @[package.scala:253:{43,53}] wire [15:0] _mshr_selectOH2_T_3 = {_mshr_selectOH2_T_2, 2'h0}; // @[package.scala:253:{43,48}] wire [13:0] _mshr_selectOH2_T_4 = _mshr_selectOH2_T_3[13:0]; // @[package.scala:253:{48,53}] wire [13:0] _mshr_selectOH2_T_5 = _mshr_selectOH2_T_2 \| _mshr_selectOH2_T_4; // @[package.scala:253:{43,53}] wire [17:0] _mshr_selectOH2_T_6 = {_mshr_selectOH2_T_5, 4'h0}; // @[package.scala:253:{43,48}] wire [13:0] _mshr_selectOH2_T_7 = _mshr_selectOH2_T_6[13:0]; // @[package.scala:253:{48,53}] wire [13:0] _mshr_selectOH2_T_8 = _mshr_selectOH2_T_5 \| _mshr_selectOH2_T_7; // @[package.scala:253:{43,53}] wire [21:0] _mshr_selectOH2_T_9 = {_mshr_selectOH2_T_8, 8'h0}; // @[package.scala:253:{43,48}] wire [13:0] _mshr_selectOH2_T_10 = _mshr_selectOH2_T_9[13:0]; // @[package.scala:253:{48,53}] wire [13:0] _mshr_selectOH2_T_11 = _mshr_selectOH2_T_8 \| _mshr_selectOH2_T_10; // @[package.scala:253:{43,53}] wire [13:0] _mshr_selectOH2_T_12 = _mshr_selectOH2_T_11; // @[package.scala:253:43, :254:17] wire [14:0] _mshr_selectOH2_T_13 = {_mshr_selectOH2_T_12, 1'h0}; // @[package.scala:254:17] wire [14:0] _mshr_selectOH2_T_14 = ~_mshr_selectOH2_T_13; // @[Scheduler.scala:120:{24,48}] wire [14:0] mshr_selectOH2 = {1'h0, _mshr_selectOH2_T_14[13:0] & robin_request}; // @[Scheduler.scala:119:26, :120:{24,54}] wire [6:0] _mshr_selectOH_T = mshr_selectOH2[13:7]; // @[Scheduler.scala:120:54, :121:37] wire [6:0] _mshr_selectOH_T_1 = mshr_selectOH2[6:0]; // @[Scheduler.scala:120:54, :121:86] wire [6:0] mshr_selectOH = _mshr_selectOH_T \| _mshr_selectOH_T_1; // @[Scheduler.scala:121:{37,70,86}] wire [2:0] mshr_select_hi = mshr_selectOH[6:4]; // @[OneHot.scala:30:18] wire [3:0] mshr_select_lo = mshr_selectOH[3:0]; // @[OneHot.scala:31:18] wire _mshr_select_T = \|mshr_select_hi; // @[OneHot.scala:30:18, :32:14] wire [3:0] _mshr_select_T_1 = {1'h0, mshr_select_hi} \| mshr_select_lo; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] mshr_select_hi_1 = _mshr_select_T_1[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] mshr_select_lo_1 = _mshr_select_T_1[1:0]; // @[OneHot.scala:31:18, :32:28] wire _mshr_select_T_2 = \|mshr_select_hi_1; // @[OneHot.scala:30:18, :32:14] wire [1:0] _mshr_select_T_3 = mshr_select_hi_1 \| mshr_select_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire _mshr_select_T_4 = _mshr_select_T_3[1]; // @[OneHot.scala:32:28] wire [1:0] _mshr_select_T_5 = {_mshr_select_T_2, _mshr_select_T_4}; // @[OneHot.scala:32:{10,14}] wire [2:0] mshr_select = {_mshr_select_T, _mshr_select_T_5}; // @[OneHot.scala:32:{10,14}] wire [2:0] schedule_a_bits_source = mshr_select; // @[OneHot.scala:32:10] wire [2:0] schedule_d_bits_sink = mshr_select; // @[OneHot.scala:32:10] wire _schedule_T = mshr_selectOH[0]; // @[Mux.scala:32:36] wire _scheduleTag_T = mshr_selectOH[0]; // @[Mux.scala:32:36] wire _scheduleSet_T = mshr_selectOH[0]; // @[Mux.scala:32:36] wire sel = mshr_selectOH[0]; // @[Mux.scala:32:36] wire _schedule_T_1 = mshr_selectOH[1]; // @[Mux.scala:32:36] wire _scheduleTag_T_1 = mshr_selectOH[1]; // @[Mux.scala:32:36] wire _scheduleSet_T_1 = mshr_selectOH[1]; // @[Mux.scala:32:36] wire sel_1 = mshr_selectOH[1]; // @[Mux.scala:32:36] wire _schedule_T_2 = mshr_selectOH[2]; // @[Mux.scala:32:36] wire _scheduleTag_T_2 = mshr_selectOH[2]; // @[Mux.scala:32:36] wire _scheduleSet_T_2 = mshr_selectOH[2]; // @[Mux.scala:32:36] wire sel_2 = mshr_selectOH[2]; // @[Mux.scala:32:36] wire _schedule_T_3 = mshr_selectOH[3]; // @[Mux.scala:32:36] wire _scheduleTag_T_3 = mshr_selectOH[3]; // @[Mux.scala:32:36] wire _scheduleSet_T_3 = mshr_selectOH[3]; // @[Mux.scala:32:36] wire sel_3 = mshr_selectOH[3]; // @[Mux.scala:32:36] wire _schedule_T_4 = mshr_selectOH[4]; // @[Mux.scala:32:36] wire _scheduleTag_T_4 = mshr_selectOH[4]; // @[Mux.scala:32:36] wire _scheduleSet_T_4 = mshr_selectOH[4]; // @[Mux.scala:32:36] wire sel_4 = mshr_selectOH[4]; // @[Mux.scala:32:36] wire _schedule_T_5 = mshr_selectOH[5]; // @[Mux.scala:32:36] wire _scheduleTag_T_5 = mshr_selectOH[5]; // @[Mux.scala:32:36] wire _scheduleSet_T_5 = mshr_selectOH[5]; // @[Mux.scala:32:36] wire select_bc = mshr_selectOH[5]; // @[Mux.scala:32:36] wire sel_5 = mshr_selectOH[5]; // @[Mux.scala:32:36] wire _schedule_T_6 = mshr_selectOH[6]; // @[Mux.scala:32:36] wire _scheduleTag_T_6 = mshr_selectOH[6]; // @[Mux.scala:32:36] wire _scheduleSet_T_6 = mshr_selectOH[6]; // @[Mux.scala:32:36] wire select_c = mshr_selectOH[6]; // @[Mux.scala:32:36] wire sel_6 = mshr_selectOH[6]; // @[Mux.scala:32:36] wire _schedule_WIRE_55_valid; // @[Mux.scala:30:73] wire [12:0] _schedule_WIRE_55_bits_tag; // @[Mux.scala:30:73] wire [9:0] _schedule_WIRE_55_bits_set; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_55_bits_param; // @[Mux.scala:30:73] wire _schedule_WIRE_55_bits_block; // @[Mux.scala:30:73] wire _schedule_WIRE_48_valid; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_48_bits_param; // @[Mux.scala:30:73] wire [12:0] _schedule_WIRE_48_bits_tag; // @[Mux.scala:30:73] wire [9:0] _schedule_WIRE_48_bits_set; // @[Mux.scala:30:73] wire [1:0] _schedule_WIRE_48_bits_clients; // @[Mux.scala:30:73] wire _schedule_WIRE_38_valid; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_38_bits_opcode; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_38_bits_param; // @[Mux.scala:30:73] wire [2:0] _schedule_c_bits_source_T_1; // @[Scheduler.scala:132:32] wire [12:0] _schedule_WIRE_38_bits_tag; // @[Mux.scala:30:73] wire [9:0] _schedule_WIRE_38_bits_set; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_38_bits_way; // @[Mux.scala:30:73] wire _schedule_WIRE_38_bits_dirty; // @[Mux.scala:30:73] wire _schedule_WIRE_19_valid; // @[Mux.scala:30:73] wire _schedule_WIRE_19_bits_prio_0; // @[Mux.scala:30:73] wire _schedule_WIRE_19_bits_prio_1; // @[Mux.scala:30:73] wire _schedule_WIRE_19_bits_prio_2; // @[Mux.scala:30:73] wire _schedule_WIRE_19_bits_control; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_19_bits_opcode; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_19_bits_param; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_19_bits_size; // @[Mux.scala:30:73] wire [5:0] _schedule_WIRE_19_bits_source; // @[Mux.scala:30:73] wire [12:0] _schedule_WIRE_19_bits_tag; // @[Mux.scala:30:73] wire [5:0] _schedule_WIRE_19_bits_offset; // @[Mux.scala:30:73] wire [5:0] _schedule_WIRE_19_bits_put; // @[Mux.scala:30:73] wire [9:0] _schedule_WIRE_19_bits_set; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_19_bits_way; // @[Mux.scala:30:73] wire _schedule_WIRE_19_bits_bad; // @[Mux.scala:30:73] wire _schedule_WIRE_15_valid; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_15_bits_sink; // @[Mux.scala:30:73] wire _schedule_WIRE_11_valid; // @[Mux.scala:30:73] wire _schedule_WIRE_1_valid; // @[Mux.scala:30:73] wire [9:0] _schedule_WIRE_1_bits_set; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_1_bits_way; // @[Mux.scala:30:73] wire _schedule_WIRE_1_bits_data_dirty; // @[Mux.scala:30:73] wire [1:0] _schedule_WIRE_1_bits_data_state; // @[Mux.scala:30:73] wire [1:0] _schedule_WIRE_1_bits_data_clients; // @[Mux.scala:30:73] wire [12:0] _schedule_WIRE_1_bits_data_tag; // @[Mux.scala:30:73] wire _schedule_WIRE; // @[Mux.scala:30:73] wire [12:0] schedule_a_bits_tag; // @[Mux.scala:30:73] wire [9:0] schedule_a_bits_set; // @[Mux.scala:30:73] wire [2:0] schedule_a_bits_param; // @[Mux.scala:30:73] wire schedule_a_bits_block; // @[Mux.scala:30:73] wire schedule_a_valid; // @[Mux.scala:30:73] wire [2:0] schedule_b_bits_param; // @[Mux.scala:30:73] wire [12:0] schedule_b_bits_tag; // @[Mux.scala:30:73] wire [9:0] schedule_b_bits_set; // @[Mux.scala:30:73] wire [1:0] schedule_b_bits_clients; // @[Mux.scala:30:73] wire schedule_b_valid; // @[Mux.scala:30:73] wire [2:0] schedule_c_bits_opcode; // @[Mux.scala:30:73] wire [2:0] schedule_c_bits_param; // @[Mux.scala:30:73] wire [2:0] schedule_c_bits_source; // @[Mux.scala:30:73] wire [12:0] schedule_c_bits_tag; // @[Mux.scala:30:73] wire [9:0] schedule_c_bits_set; // @[Mux.scala:30:73] wire [2:0] schedule_c_bits_way; // @[Mux.scala:30:73] wire schedule_c_bits_dirty; // @[Mux.scala:30:73] wire schedule_c_valid; // @[Mux.scala:30:73] wire schedule_d_bits_prio_0; // @[Mux.scala:30:73] wire schedule_d_bits_prio_1; // @[Mux.scala:30:73] wire schedule_d_bits_prio_2; // @[Mux.scala:30:73] wire schedule_d_bits_control; // @[Mux.scala:30:73] wire [2:0] schedule_d_bits_opcode; // @[Mux.scala:30:73] wire [2:0] schedule_d_bits_param; // @[Mux.scala:30:73] wire [2:0] schedule_d_bits_size; // @[Mux.scala:30:73] wire [5:0] schedule_d_bits_source; // @[Mux.scala:30:73] wire [12:0] schedule_d_bits_tag; // @[Mux.scala:30:73] wire [5:0] schedule_d_bits_offset; // @[Mux.scala:30:73] wire [5:0] schedule_d_bits_put; // @[Mux.scala:30:73] wire [9:0] schedule_d_bits_set; // @[Mux.scala:30:73] wire [2:0] schedule_d_bits_way; // @[Mux.scala:30:73] wire schedule_d_bits_bad; // @[Mux.scala:30:73] wire schedule_d_valid; // @[Mux.scala:30:73] wire [2:0] schedule_e_bits_sink; // @[Mux.scala:30:73] wire schedule_e_valid; // @[Mux.scala:30:73] wire schedule_x_valid; // @[Mux.scala:30:73] wire schedule_dir_bits_data_dirty; // @[Mux.scala:30:73] wire [1:0] schedule_dir_bits_data_state; // @[Mux.scala:30:73] wire [1:0] schedule_dir_bits_data_clients; // @[Mux.scala:30:73] wire [12:0] schedule_dir_bits_data_tag; // @[Mux.scala:30:73] wire [9:0] schedule_dir_bits_set; // @[Mux.scala:30:73] wire [2:0] schedule_dir_bits_way; // @[Mux.scala:30:73] wire schedule_dir_valid; // @[Mux.scala:30:73] wire schedule_reload; // @[Mux.scala:30:73] wire _schedule_T_7 = _schedule_T & _mshrs_0_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36] wire _schedule_T_8 = _schedule_T_1 & _mshrs_1_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36] wire _schedule_T_9 = _schedule_T_2 & _mshrs_2_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36] wire _schedule_T_10 = _schedule_T_3 & _mshrs_3_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36] wire _schedule_T_11 = _schedule_T_4 & _mshrs_4_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36] wire _schedule_T_12 = _schedule_T_5 & _mshrs_5_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36] wire _schedule_T_13 = _schedule_T_6 & _mshrs_6_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36] wire _schedule_T_14 = _schedule_T_7 \| _schedule_T_8; // @[Mux.scala:30:73] wire _schedule_T_15 = _schedule_T_14 \| _schedule_T_9; // @[Mux.scala:30:73] wire _schedule_T_16 = _schedule_T_15 \| _schedule_T_10; // @[Mux.scala:30:73] wire _schedule_T_17 = _schedule_T_16 \| _schedule_T_11; // @[Mux.scala:30:73] wire _schedule_T_18 = _schedule_T_17 \| _schedule_T_12; // @[Mux.scala:30:73] wire _schedule_T_19 = _schedule_T_18 \| _schedule_T_13; // @[Mux.scala:30:73] assign _schedule_WIRE = _schedule_T_19; // @[Mux.scala:30:73] assign schedule_reload = _schedule_WIRE; // @[Mux.scala:30:73] wire _schedule_WIRE_10; // @[Mux.scala:30:73] assign schedule_dir_valid = _schedule_WIRE_1_valid; // @[Mux.scala:30:73] wire [9:0] _schedule_WIRE_2_set; // @[Mux.scala:30:73] assign schedule_dir_bits_set = _schedule_WIRE_1_bits_set; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_2_way; // @[Mux.scala:30:73] assign schedule_dir_bits_way = _schedule_WIRE_1_bits_way; // @[Mux.scala:30:73] wire _schedule_WIRE_2_data_dirty; // @[Mux.scala:30:73] assign schedule_dir_bits_data_dirty = _schedule_WIRE_1_bits_data_dirty; // @[Mux.scala:30:73] wire [1:0] _schedule_WIRE_2_data_state; // @[Mux.scala:30:73] assign schedule_dir_bits_data_state = _schedule_WIRE_1_bits_data_state; // @[Mux.scala:30:73] wire [1:0] _schedule_WIRE_2_data_clients; // @[Mux.scala:30:73] assign schedule_dir_bits_data_clients = _schedule_WIRE_1_bits_data_clients; // @[Mux.scala:30:73] wire [12:0] _schedule_WIRE_2_data_tag; // @[Mux.scala:30:73] assign schedule_dir_bits_data_tag = _schedule_WIRE_1_bits_data_tag; // @[Mux.scala:30:73] wire [9:0] _schedule_WIRE_9; // @[Mux.scala:30:73] assign _schedule_WIRE_1_bits_set = _schedule_WIRE_2_set; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_8; // @[Mux.scala:30:73] assign _schedule_WIRE_1_bits_way = _schedule_WIRE_2_way; // @[Mux.scala:30:73] wire _schedule_WIRE_3_dirty; // @[Mux.scala:30:73] assign _schedule_WIRE_1_bits_data_dirty = _schedule_WIRE_2_data_dirty; // @[Mux.scala:30:73] wire [1:0] _schedule_WIRE_3_state; // @[Mux.scala:30:73] assign _schedule_WIRE_1_bits_data_state = _schedule_WIRE_2_data_state; // @[Mux.scala:30:73] wire [1:0] _schedule_WIRE_3_clients; // @[Mux.scala:30:73] assign _schedule_WIRE_1_bits_data_clients = _schedule_WIRE_2_data_clients; // @[Mux.scala:30:73] wire [12:0] _schedule_WIRE_3_tag; // @[Mux.scala:30:73] assign _schedule_WIRE_1_bits_data_tag = _schedule_WIRE_2_data_tag; // @[Mux.scala:30:73] wire _schedule_WIRE_7; // @[Mux.scala:30:73] assign _schedule_WIRE_2_data_dirty = _schedule_WIRE_3_dirty; // @[Mux.scala:30:73] wire [1:0] _schedule_WIRE_6; // @[Mux.scala:30:73] assign _schedule_WIRE_2_data_state = _schedule_WIRE_3_state; // @[Mux.scala:30:73] wire [1:0] _schedule_WIRE_5; // @[Mux.scala:30:73] assign _schedule_WIRE_2_data_clients = _schedule_WIRE_3_clients; // @[Mux.scala:30:73] wire [12:0] _schedule_WIRE_4; // @[Mux.scala:30:73] assign _schedule_WIRE_2_data_tag = _schedule_WIRE_3_tag; // @[Mux.scala:30:73] wire [12:0] _schedule_T_20 = _schedule_T ? _mshrs_0_io_schedule_bits_dir_bits_data_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_21 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_dir_bits_data_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_22 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_dir_bits_data_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_23 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_dir_bits_data_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_24 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_dir_bits_data_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_25 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_dir_bits_data_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_26 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_dir_bits_data_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_27 = _schedule_T_20 \| _schedule_T_21; // @[Mux.scala:30:73] wire [12:0] _schedule_T_28 = _schedule_T_27 \| _schedule_T_22; // @[Mux.scala:30:73] wire [12:0] _schedule_T_29 = _schedule_T_28 \| _schedule_T_23; // @[Mux.scala:30:73] wire [12:0] _schedule_T_30 = _schedule_T_29 \| _schedule_T_24; // @[Mux.scala:30:73] wire [12:0] _schedule_T_31 = _schedule_T_30 \| _schedule_T_25; // @[Mux.scala:30:73] wire [12:0] _schedule_T_32 = _schedule_T_31 \| _schedule_T_26; // @[Mux.scala:30:73] assign _schedule_WIRE_4 = _schedule_T_32; // @[Mux.scala:30:73] assign _schedule_WIRE_3_tag = _schedule_WIRE_4; // @[Mux.scala:30:73] wire [1:0] _schedule_T_33 = _schedule_T ? _mshrs_0_io_schedule_bits_dir_bits_data_clients : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _schedule_T_34 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_dir_bits_data_clients : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _schedule_T_35 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_dir_bits_data_clients : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _schedule_T_36 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_dir_bits_data_clients : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _schedule_T_37 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_dir_bits_data_clients : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _schedule_T_38 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_dir_bits_data_clients : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _schedule_T_39 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_dir_bits_data_clients : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _schedule_T_40 = _schedule_T_33 \| _schedule_T_34; // @[Mux.scala:30:73] wire [1:0] _schedule_T_41 = _schedule_T_40 \| _schedule_T_35; // @[Mux.scala:30:73] wire [1:0] _schedule_T_42 = _schedule_T_41 \| _schedule_T_36; // @[Mux.scala:30:73] wire [1:0] _schedule_T_43 = _schedule_T_42 \| _schedule_T_37; // @[Mux.scala:30:73] wire [1:0] _schedule_T_44 = _schedule_T_43 \| _schedule_T_38; // @[Mux.scala:30:73] wire [1:0] _schedule_T_45 = _schedule_T_44 \| _schedule_T_39; // @[Mux.scala:30:73] assign _schedule_WIRE_5 = _schedule_T_45; // @[Mux.scala:30:73] assign _schedule_WIRE_3_clients = _schedule_WIRE_5; // @[Mux.scala:30:73] wire [1:0] _schedule_T_46 = _schedule_T ? _mshrs_0_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _schedule_T_47 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _schedule_T_48 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _schedule_T_49 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _schedule_T_50 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _schedule_T_51 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _schedule_T_52 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _schedule_T_53 = _schedule_T_46 \| _schedule_T_47; // @[Mux.scala:30:73] wire [1:0] _schedule_T_54 = _schedule_T_53 \| _schedule_T_48; // @[Mux.scala:30:73] wire [1:0] _schedule_T_55 = _schedule_T_54 \| _schedule_T_49; // @[Mux.scala:30:73] wire [1:0] _schedule_T_56 = _schedule_T_55 \| _schedule_T_50; // @[Mux.scala:30:73] wire [1:0] _schedule_T_57 = _schedule_T_56 \| _schedule_T_51; // @[Mux.scala:30:73] wire [1:0] _schedule_T_58 = _schedule_T_57 \| _schedule_T_52; // @[Mux.scala:30:73] assign _schedule_WIRE_6 = _schedule_T_58; // @[Mux.scala:30:73] assign _schedule_WIRE_3_state = _schedule_WIRE_6; // @[Mux.scala:30:73] wire _schedule_T_59 = _schedule_T & _mshrs_0_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_60 = _schedule_T_1 & _mshrs_1_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_61 = _schedule_T_2 & _mshrs_2_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_62 = _schedule_T_3 & _mshrs_3_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_63 = _schedule_T_4 & _mshrs_4_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_64 = _schedule_T_5 & _mshrs_5_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_65 = _schedule_T_6 & _mshrs_6_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_66 = _schedule_T_59 \| _schedule_T_60; // @[Mux.scala:30:73] wire _schedule_T_67 = _schedule_T_66 \| _schedule_T_61; // @[Mux.scala:30:73] wire _schedule_T_68 = _schedule_T_67 \| _schedule_T_62; // @[Mux.scala:30:73] wire _schedule_T_69 = _schedule_T_68 \| _schedule_T_63; // @[Mux.scala:30:73] wire _schedule_T_70 = _schedule_T_69 \| _schedule_T_64; // @[Mux.scala:30:73] wire _schedule_T_71 = _schedule_T_70 \| _schedule_T_65; // @[Mux.scala:30:73] assign _schedule_WIRE_7 = _schedule_T_71; // @[Mux.scala:30:73] assign _schedule_WIRE_3_dirty = _schedule_WIRE_7; // @[Mux.scala:30:73] wire [2:0] _schedule_T_72 = _schedule_T ? _mshrs_0_io_schedule_bits_dir_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_73 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_dir_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_74 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_dir_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_75 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_dir_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_76 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_dir_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_77 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_dir_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_78 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_dir_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_79 = _schedule_T_72 \| _schedule_T_73; // @[Mux.scala:30:73] wire [2:0] _schedule_T_80 = _schedule_T_79 \| _schedule_T_74; // @[Mux.scala:30:73] wire [2:0] _schedule_T_81 = _schedule_T_80 \| _schedule_T_75; // @[Mux.scala:30:73] wire [2:0] _schedule_T_82 = _schedule_T_81 \| _schedule_T_76; // @[Mux.scala:30:73] wire [2:0] _schedule_T_83 = _schedule_T_82 \| _schedule_T_77; // @[Mux.scala:30:73] wire [2:0] _schedule_T_84 = _schedule_T_83 \| _schedule_T_78; // @[Mux.scala:30:73] assign _schedule_WIRE_8 = _schedule_T_84; // @[Mux.scala:30:73] assign _schedule_WIRE_2_way = _schedule_WIRE_8; // @[Mux.scala:30:73] wire [9:0] _schedule_T_85 = _schedule_T ? _mshrs_0_io_schedule_bits_dir_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_86 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_dir_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_87 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_dir_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_88 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_dir_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_89 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_dir_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_90 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_dir_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_91 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_dir_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_92 = _schedule_T_85 \| _schedule_T_86; // @[Mux.scala:30:73] wire [9:0] _schedule_T_93 = _schedule_T_92 \| _schedule_T_87; // @[Mux.scala:30:73] wire [9:0] _schedule_T_94 = _schedule_T_93 \| _schedule_T_88; // @[Mux.scala:30:73] wire [9:0] _schedule_T_95 = _schedule_T_94 \| _schedule_T_89; // @[Mux.scala:30:73] wire [9:0] _schedule_T_96 = _schedule_T_95 \| _schedule_T_90; // @[Mux.scala:30:73] wire [9:0] _schedule_T_97 = _schedule_T_96 \| _schedule_T_91; // @[Mux.scala:30:73] assign _schedule_WIRE_9 = _schedule_T_97; // @[Mux.scala:30:73] assign _schedule_WIRE_2_set = _schedule_WIRE_9; // @[Mux.scala:30:73] wire _schedule_T_98 = _schedule_T & _mshrs_0_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_99 = _schedule_T_1 & _mshrs_1_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_100 = _schedule_T_2 & _mshrs_2_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_101 = _schedule_T_3 & _mshrs_3_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_102 = _schedule_T_4 & _mshrs_4_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_103 = _schedule_T_5 & _mshrs_5_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_104 = _schedule_T_6 & _mshrs_6_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_105 = _schedule_T_98 \| _schedule_T_99; // @[Mux.scala:30:73] wire _schedule_T_106 = _schedule_T_105 \| _schedule_T_100; // @[Mux.scala:30:73] wire _schedule_T_107 = _schedule_T_106 \| _schedule_T_101; // @[Mux.scala:30:73] wire _schedule_T_108 = _schedule_T_107 \| _schedule_T_102; // @[Mux.scala:30:73] wire _schedule_T_109 = _schedule_T_108 \| _schedule_T_103; // @[Mux.scala:30:73] wire _schedule_T_110 = _schedule_T_109 \| _schedule_T_104; // @[Mux.scala:30:73] assign _schedule_WIRE_10 = _schedule_T_110; // @[Mux.scala:30:73] assign _schedule_WIRE_1_valid = _schedule_WIRE_10; // @[Mux.scala:30:73] wire _schedule_WIRE_14; // @[Mux.scala:30:73] assign schedule_x_valid = _schedule_WIRE_11_valid; // @[Mux.scala:30:73] wire _schedule_T_124 = _schedule_T & _mshrs_0_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_125 = _schedule_T_1 & _mshrs_1_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_126 = _schedule_T_2 & _mshrs_2_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_127 = _schedule_T_3 & _mshrs_3_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_128 = _schedule_T_4 & _mshrs_4_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_129 = _schedule_T_5 & _mshrs_5_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_130 = _schedule_T_6 & _mshrs_6_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_131 = _schedule_T_124 \| _schedule_T_125; // @[Mux.scala:30:73] wire _schedule_T_132 = _schedule_T_131 \| _schedule_T_126; // @[Mux.scala:30:73] wire _schedule_T_133 = _schedule_T_132 \| _schedule_T_127; // @[Mux.scala:30:73] wire _schedule_T_134 = _schedule_T_133 \| _schedule_T_128; // @[Mux.scala:30:73] wire _schedule_T_135 = _schedule_T_134 \| _schedule_T_129; // @[Mux.scala:30:73] wire _schedule_T_136 = _schedule_T_135 \| _schedule_T_130; // @[Mux.scala:30:73] assign _schedule_WIRE_14 = _schedule_T_136; // @[Mux.scala:30:73] assign _schedule_WIRE_11_valid = _schedule_WIRE_14; // @[Mux.scala:30:73] wire _schedule_WIRE_18; // @[Mux.scala:30:73] assign schedule_e_valid = _schedule_WIRE_15_valid; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_16_sink; // @[Mux.scala:30:73] assign schedule_e_bits_sink = _schedule_WIRE_15_bits_sink; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_17; // @[Mux.scala:30:73] assign _schedule_WIRE_15_bits_sink = _schedule_WIRE_16_sink; // @[Mux.scala:30:73] wire [2:0] _schedule_T_137 = _schedule_T ? _mshrs_0_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_138 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_139 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_140 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_141 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_142 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_143 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_144 = _schedule_T_137 \| _schedule_T_138; // @[Mux.scala:30:73] wire [2:0] _schedule_T_145 = _schedule_T_144 \| _schedule_T_139; // @[Mux.scala:30:73] wire [2:0] _schedule_T_146 = _schedule_T_145 \| _schedule_T_140; // @[Mux.scala:30:73] wire [2:0] _schedule_T_147 = _schedule_T_146 \| _schedule_T_141; // @[Mux.scala:30:73] wire [2:0] _schedule_T_148 = _schedule_T_147 \| _schedule_T_142; // @[Mux.scala:30:73] wire [2:0] _schedule_T_149 = _schedule_T_148 \| _schedule_T_143; // @[Mux.scala:30:73] assign _schedule_WIRE_17 = _schedule_T_149; // @[Mux.scala:30:73] assign _schedule_WIRE_16_sink = _schedule_WIRE_17; // @[Mux.scala:30:73] wire _schedule_T_150 = _schedule_T & _mshrs_0_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_151 = _schedule_T_1 & _mshrs_1_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_152 = _schedule_T_2 & _mshrs_2_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_153 = _schedule_T_3 & _mshrs_3_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_154 = _schedule_T_4 & _mshrs_4_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_155 = _schedule_T_5 & _mshrs_5_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_156 = _schedule_T_6 & _mshrs_6_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_157 = _schedule_T_150 \| _schedule_T_151; // @[Mux.scala:30:73] wire _schedule_T_158 = _schedule_T_157 \| _schedule_T_152; // @[Mux.scala:30:73] wire _schedule_T_159 = _schedule_T_158 \| _schedule_T_153; // @[Mux.scala:30:73] wire _schedule_T_160 = _schedule_T_159 \| _schedule_T_154; // @[Mux.scala:30:73] wire _schedule_T_161 = _schedule_T_160 \| _schedule_T_155; // @[Mux.scala:30:73] wire _schedule_T_162 = _schedule_T_161 \| _schedule_T_156; // @[Mux.scala:30:73] assign _schedule_WIRE_18 = _schedule_T_162; // @[Mux.scala:30:73] assign _schedule_WIRE_15_valid = _schedule_WIRE_18; // @[Mux.scala:30:73] wire _schedule_WIRE_37; // @[Mux.scala:30:73] assign schedule_d_valid = _schedule_WIRE_19_valid; // @[Mux.scala:30:73] wire _schedule_WIRE_20_prio_0; // @[Mux.scala:30:73] assign schedule_d_bits_prio_0 = _schedule_WIRE_19_bits_prio_0; // @[Mux.scala:30:73] wire _schedule_WIRE_20_prio_1; // @[Mux.scala:30:73] assign schedule_d_bits_prio_1 = _schedule_WIRE_19_bits_prio_1; // @[Mux.scala:30:73] wire _schedule_WIRE_20_prio_2; // @[Mux.scala:30:73] assign schedule_d_bits_prio_2 = _schedule_WIRE_19_bits_prio_2; // @[Mux.scala:30:73] wire _schedule_WIRE_20_control; // @[Mux.scala:30:73] assign schedule_d_bits_control = _schedule_WIRE_19_bits_control; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_20_opcode; // @[Mux.scala:30:73] assign schedule_d_bits_opcode = _schedule_WIRE_19_bits_opcode; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_20_param; // @[Mux.scala:30:73] assign schedule_d_bits_param = _schedule_WIRE_19_bits_param; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_20_size; // @[Mux.scala:30:73] assign schedule_d_bits_size = _schedule_WIRE_19_bits_size; // @[Mux.scala:30:73] wire [5:0] _schedule_WIRE_20_source; // @[Mux.scala:30:73] assign schedule_d_bits_source = _schedule_WIRE_19_bits_source; // @[Mux.scala:30:73] wire [12:0] _schedule_WIRE_20_tag; // @[Mux.scala:30:73] assign schedule_d_bits_tag = _schedule_WIRE_19_bits_tag; // @[Mux.scala:30:73] wire [5:0] _schedule_WIRE_20_offset; // @[Mux.scala:30:73] assign schedule_d_bits_offset = _schedule_WIRE_19_bits_offset; // @[Mux.scala:30:73] wire [5:0] _schedule_WIRE_20_put; // @[Mux.scala:30:73] assign schedule_d_bits_put = _schedule_WIRE_19_bits_put; // @[Mux.scala:30:73] wire [9:0] _schedule_WIRE_20_set; // @[Mux.scala:30:73] assign schedule_d_bits_set = _schedule_WIRE_19_bits_set; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_20_way; // @[Mux.scala:30:73] assign schedule_d_bits_way = _schedule_WIRE_19_bits_way; // @[Mux.scala:30:73] wire _schedule_WIRE_20_bad; // @[Mux.scala:30:73] assign schedule_d_bits_bad = _schedule_WIRE_19_bits_bad; // @[Mux.scala:30:73] wire _schedule_WIRE_33_0; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_prio_0 = _schedule_WIRE_20_prio_0; // @[Mux.scala:30:73] wire _schedule_WIRE_33_1; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_prio_1 = _schedule_WIRE_20_prio_1; // @[Mux.scala:30:73] wire _schedule_WIRE_33_2; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_prio_2 = _schedule_WIRE_20_prio_2; // @[Mux.scala:30:73] wire _schedule_WIRE_32; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_control = _schedule_WIRE_20_control; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_31; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_opcode = _schedule_WIRE_20_opcode; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_30; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_param = _schedule_WIRE_20_param; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_29; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_size = _schedule_WIRE_20_size; // @[Mux.scala:30:73] wire [5:0] _schedule_WIRE_28; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_source = _schedule_WIRE_20_source; // @[Mux.scala:30:73] wire [12:0] _schedule_WIRE_27; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_tag = _schedule_WIRE_20_tag; // @[Mux.scala:30:73] wire [5:0] _schedule_WIRE_26; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_offset = _schedule_WIRE_20_offset; // @[Mux.scala:30:73] wire [5:0] _schedule_WIRE_25; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_put = _schedule_WIRE_20_put; // @[Mux.scala:30:73] wire [9:0] _schedule_WIRE_24; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_set = _schedule_WIRE_20_set; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_22; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_way = _schedule_WIRE_20_way; // @[Mux.scala:30:73] wire _schedule_WIRE_21; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_bad = _schedule_WIRE_20_bad; // @[Mux.scala:30:73] wire _schedule_T_163 = _schedule_T & _mshrs_0_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36] wire _schedule_T_164 = _schedule_T_1 & _mshrs_1_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36] wire _schedule_T_165 = _schedule_T_2 & _mshrs_2_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36] wire _schedule_T_166 = _schedule_T_3 & _mshrs_3_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36] wire _schedule_T_167 = _schedule_T_4 & _mshrs_4_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36] wire _schedule_T_168 = _schedule_T_5 & _mshrs_5_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36] wire _schedule_T_169 = _schedule_T_6 & _mshrs_6_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36] wire _schedule_T_170 = _schedule_T_163 \| _schedule_T_164; // @[Mux.scala:30:73] wire _schedule_T_171 = _schedule_T_170 \| _schedule_T_165; // @[Mux.scala:30:73] wire _schedule_T_172 = _schedule_T_171 \| _schedule_T_166; // @[Mux.scala:30:73] wire _schedule_T_173 = _schedule_T_172 \| _schedule_T_167; // @[Mux.scala:30:73] wire _schedule_T_174 = _schedule_T_173 \| _schedule_T_168; // @[Mux.scala:30:73] wire _schedule_T_175 = _schedule_T_174 \| _schedule_T_169; // @[Mux.scala:30:73] assign _schedule_WIRE_21 = _schedule_T_175; // @[Mux.scala:30:73] assign _schedule_WIRE_20_bad = _schedule_WIRE_21; // @[Mux.scala:30:73] wire [2:0] _schedule_T_176 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_177 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_178 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_179 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_180 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_181 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_182 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_183 = _schedule_T_176 \| _schedule_T_177; // @[Mux.scala:30:73] wire [2:0] _schedule_T_184 = _schedule_T_183 \| _schedule_T_178; // @[Mux.scala:30:73] wire [2:0] _schedule_T_185 = _schedule_T_184 \| _schedule_T_179; // @[Mux.scala:30:73] wire [2:0] _schedule_T_186 = _schedule_T_185 \| _schedule_T_180; // @[Mux.scala:30:73] wire [2:0] _schedule_T_187 = _schedule_T_186 \| _schedule_T_181; // @[Mux.scala:30:73] wire [2:0] _schedule_T_188 = _schedule_T_187 \| _schedule_T_182; // @[Mux.scala:30:73] assign _schedule_WIRE_22 = _schedule_T_188; // @[Mux.scala:30:73] assign _schedule_WIRE_20_way = _schedule_WIRE_22; // @[Mux.scala:30:73] wire [9:0] _schedule_T_202 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_203 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_204 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_205 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_206 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_207 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_208 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_209 = _schedule_T_202 \| _schedule_T_203; // @[Mux.scala:30:73] wire [9:0] _schedule_T_210 = _schedule_T_209 \| _schedule_T_204; // @[Mux.scala:30:73] wire [9:0] _schedule_T_211 = _schedule_T_210 \| _schedule_T_205; // @[Mux.scala:30:73] wire [9:0] _schedule_T_212 = _schedule_T_211 \| _schedule_T_206; // @[Mux.scala:30:73] wire [9:0] _schedule_T_213 = _schedule_T_212 \| _schedule_T_207; // @[Mux.scala:30:73] wire [9:0] _schedule_T_214 = _schedule_T_213 \| _schedule_T_208; // @[Mux.scala:30:73] assign _schedule_WIRE_24 = _schedule_T_214; // @[Mux.scala:30:73] assign _schedule_WIRE_20_set = _schedule_WIRE_24; // @[Mux.scala:30:73] wire [5:0] _schedule_T_215 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_216 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_217 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_218 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_219 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_220 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_221 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_222 = _schedule_T_215 \| _schedule_T_216; // @[Mux.scala:30:73] wire [5:0] _schedule_T_223 = _schedule_T_222 \| _schedule_T_217; // @[Mux.scala:30:73] wire [5:0] _schedule_T_224 = _schedule_T_223 \| _schedule_T_218; // @[Mux.scala:30:73] wire [5:0] _schedule_T_225 = _schedule_T_224 \| _schedule_T_219; // @[Mux.scala:30:73] wire [5:0] _schedule_T_226 = _schedule_T_225 \| _schedule_T_220; // @[Mux.scala:30:73] wire [5:0] _schedule_T_227 = _schedule_T_226 \| _schedule_T_221; // @[Mux.scala:30:73] assign _schedule_WIRE_25 = _schedule_T_227; // @[Mux.scala:30:73] assign _schedule_WIRE_20_put = _schedule_WIRE_25; // @[Mux.scala:30:73] wire [5:0] _schedule_T_228 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_229 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_230 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_231 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_232 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_233 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_234 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_235 = _schedule_T_228 \| _schedule_T_229; // @[Mux.scala:30:73] wire [5:0] _schedule_T_236 = _schedule_T_235 \| _schedule_T_230; // @[Mux.scala:30:73] wire [5:0] _schedule_T_237 = _schedule_T_236 \| _schedule_T_231; // @[Mux.scala:30:73] wire [5:0] _schedule_T_238 = _schedule_T_237 \| _schedule_T_232; // @[Mux.scala:30:73] wire [5:0] _schedule_T_239 = _schedule_T_238 \| _schedule_T_233; // @[Mux.scala:30:73] wire [5:0] _schedule_T_240 = _schedule_T_239 \| _schedule_T_234; // @[Mux.scala:30:73] assign _schedule_WIRE_26 = _schedule_T_240; // @[Mux.scala:30:73] assign _schedule_WIRE_20_offset = _schedule_WIRE_26; // @[Mux.scala:30:73] wire [12:0] _schedule_T_241 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_242 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_243 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_244 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_245 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_246 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_247 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_248 = _schedule_T_241 \| _schedule_T_242; // @[Mux.scala:30:73] wire [12:0] _schedule_T_249 = _schedule_T_248 \| _schedule_T_243; // @[Mux.scala:30:73] wire [12:0] _schedule_T_250 = _schedule_T_249 \| _schedule_T_244; // @[Mux.scala:30:73] wire [12:0] _schedule_T_251 = _schedule_T_250 \| _schedule_T_245; // @[Mux.scala:30:73] wire [12:0] _schedule_T_252 = _schedule_T_251 \| _schedule_T_246; // @[Mux.scala:30:73] wire [12:0] _schedule_T_253 = _schedule_T_252 \| _schedule_T_247; // @[Mux.scala:30:73] assign _schedule_WIRE_27 = _schedule_T_253; // @[Mux.scala:30:73] assign _schedule_WIRE_20_tag = _schedule_WIRE_27; // @[Mux.scala:30:73] wire [5:0] _schedule_T_254 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_255 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_256 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_257 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_258 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_259 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_260 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_261 = _schedule_T_254 \| _schedule_T_255; // @[Mux.scala:30:73] wire [5:0] _schedule_T_262 = _schedule_T_261 \| _schedule_T_256; // @[Mux.scala:30:73] wire [5:0] _schedule_T_263 = _schedule_T_262 \| _schedule_T_257; // @[Mux.scala:30:73] wire [5:0] _schedule_T_264 = _schedule_T_263 \| _schedule_T_258; // @[Mux.scala:30:73] wire [5:0] _schedule_T_265 = _schedule_T_264 \| _schedule_T_259; // @[Mux.scala:30:73] wire [5:0] _schedule_T_266 = _schedule_T_265 \| _schedule_T_260; // @[Mux.scala:30:73] assign _schedule_WIRE_28 = _schedule_T_266; // @[Mux.scala:30:73] assign _schedule_WIRE_20_source = _schedule_WIRE_28; // @[Mux.scala:30:73] wire [2:0] _schedule_T_267 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_268 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_269 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_270 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_271 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_272 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_273 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_274 = _schedule_T_267 \| _schedule_T_268; // @[Mux.scala:30:73] wire [2:0] _schedule_T_275 = _schedule_T_274 \| _schedule_T_269; // @[Mux.scala:30:73] wire [2:0] _schedule_T_276 = _schedule_T_275 \| _schedule_T_270; // @[Mux.scala:30:73] wire [2:0] _schedule_T_277 = _schedule_T_276 \| _schedule_T_271; // @[Mux.scala:30:73] wire [2:0] _schedule_T_278 = _schedule_T_277 \| _schedule_T_272; // @[Mux.scala:30:73] wire [2:0] _schedule_T_279 = _schedule_T_278 \| _schedule_T_273; // @[Mux.scala:30:73] assign _schedule_WIRE_29 = _schedule_T_279; // @[Mux.scala:30:73] assign _schedule_WIRE_20_size = _schedule_WIRE_29; // @[Mux.scala:30:73] wire [2:0] _schedule_T_280 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_281 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_282 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_283 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_284 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_285 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_286 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_287 = _schedule_T_280 \| _schedule_T_281; // @[Mux.scala:30:73] wire [2:0] _schedule_T_288 = _schedule_T_287 \| _schedule_T_282; // @[Mux.scala:30:73] wire [2:0] _schedule_T_289 = _schedule_T_288 \| _schedule_T_283; // @[Mux.scala:30:73] wire [2:0] _schedule_T_290 = _schedule_T_289 \| _schedule_T_284; // @[Mux.scala:30:73] wire [2:0] _schedule_T_291 = _schedule_T_290 \| _schedule_T_285; // @[Mux.scala:30:73] wire [2:0] _schedule_T_292 = _schedule_T_291 \| _schedule_T_286; // @[Mux.scala:30:73] assign _schedule_WIRE_30 = _schedule_T_292; // @[Mux.scala:30:73] assign _schedule_WIRE_20_param = _schedule_WIRE_30; // @[Mux.scala:30:73] wire [2:0] _schedule_T_293 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_294 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_295 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_296 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_297 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_298 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_299 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_300 = _schedule_T_293 \| _schedule_T_294; // @[Mux.scala:30:73] wire [2:0] _schedule_T_301 = _schedule_T_300 \| _schedule_T_295; // @[Mux.scala:30:73] wire [2:0] _schedule_T_302 = _schedule_T_301 \| _schedule_T_296; // @[Mux.scala:30:73] wire [2:0] _schedule_T_303 = _schedule_T_302 \| _schedule_T_297; // @[Mux.scala:30:73] wire [2:0] _schedule_T_304 = _schedule_T_303 \| _schedule_T_298; // @[Mux.scala:30:73] wire [2:0] _schedule_T_305 = _schedule_T_304 \| _schedule_T_299; // @[Mux.scala:30:73] assign _schedule_WIRE_31 = _schedule_T_305; // @[Mux.scala:30:73] assign _schedule_WIRE_20_opcode = _schedule_WIRE_31; // @[Mux.scala:30:73] wire _schedule_T_306 = _schedule_T & _mshrs_0_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36] wire _schedule_T_307 = _schedule_T_1 & _mshrs_1_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36] wire _schedule_T_308 = _schedule_T_2 & _mshrs_2_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36] wire _schedule_T_309 = _schedule_T_3 & _mshrs_3_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36] wire _schedule_T_310 = _schedule_T_4 & _mshrs_4_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36] wire _schedule_T_311 = _schedule_T_5 & _mshrs_5_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36] wire _schedule_T_312 = _schedule_T_6 & _mshrs_6_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36] wire _schedule_T_313 = _schedule_T_306 \| _schedule_T_307; // @[Mux.scala:30:73] wire _schedule_T_314 = _schedule_T_313 \| _schedule_T_308; // @[Mux.scala:30:73] wire _schedule_T_315 = _schedule_T_314 \| _schedule_T_309; // @[Mux.scala:30:73] wire _schedule_T_316 = _schedule_T_315 \| _schedule_T_310; // @[Mux.scala:30:73] wire _schedule_T_317 = _schedule_T_316 \| _schedule_T_311; // @[Mux.scala:30:73] wire _schedule_T_318 = _schedule_T_317 \| _schedule_T_312; // @[Mux.scala:30:73] assign _schedule_WIRE_32 = _schedule_T_318; // @[Mux.scala:30:73] assign _schedule_WIRE_20_control = _schedule_WIRE_32; // @[Mux.scala:30:73] wire _schedule_WIRE_34; // @[Mux.scala:30:73] assign _schedule_WIRE_20_prio_0 = _schedule_WIRE_33_0; // @[Mux.scala:30:73] wire _schedule_WIRE_35; // @[Mux.scala:30:73] assign _schedule_WIRE_20_prio_1 = _schedule_WIRE_33_1; // @[Mux.scala:30:73] wire _schedule_WIRE_36; // @[Mux.scala:30:73] assign _schedule_WIRE_20_prio_2 = _schedule_WIRE_33_2; // @[Mux.scala:30:73] wire _schedule_T_319 = _schedule_T & _mshrs_0_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36] wire _schedule_T_320 = _schedule_T_1 & _mshrs_1_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36] wire _schedule_T_321 = _schedule_T_2 & _mshrs_2_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36] wire _schedule_T_322 = _schedule_T_3 & _mshrs_3_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36] wire _schedule_T_323 = _schedule_T_4 & _mshrs_4_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36] wire _schedule_T_326 = _schedule_T_319 \| _schedule_T_320; // @[Mux.scala:30:73] wire _schedule_T_327 = _schedule_T_326 \| _schedule_T_321; // @[Mux.scala:30:73] wire _schedule_T_328 = _schedule_T_327 \| _schedule_T_322; // @[Mux.scala:30:73] wire _schedule_T_329 = _schedule_T_328 \| _schedule_T_323; // @[Mux.scala:30:73] wire _schedule_T_330 = _schedule_T_329; // @[Mux.scala:30:73] wire _schedule_T_331 = _schedule_T_330; // @[Mux.scala:30:73] assign _schedule_WIRE_34 = _schedule_T_331; // @[Mux.scala:30:73] assign _schedule_WIRE_33_0 = _schedule_WIRE_34; // @[Mux.scala:30:73] wire _schedule_T_332 = _schedule_T & _mshrs_0_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36] wire _schedule_T_333 = _schedule_T_1 & _mshrs_1_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36] wire _schedule_T_334 = _schedule_T_2 & _mshrs_2_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36] wire _schedule_T_335 = _schedule_T_3 & _mshrs_3_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36] wire _schedule_T_336 = _schedule_T_4 & _mshrs_4_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36] wire _schedule_T_337 = _schedule_T_5 & _mshrs_5_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36] wire _schedule_T_339 = _schedule_T_332 \| _schedule_T_333; // @[Mux.scala:30:73] wire _schedule_T_340 = _schedule_T_339 \| _schedule_T_334; // @[Mux.scala:30:73] wire _schedule_T_341 = _schedule_T_340 \| _schedule_T_335; // @[Mux.scala:30:73] wire _schedule_T_342 = _schedule_T_341 \| _schedule_T_336; // @[Mux.scala:30:73] wire _schedule_T_343 = _schedule_T_342 \| _schedule_T_337; // @[Mux.scala:30:73] wire _schedule_T_344 = _schedule_T_343; // @[Mux.scala:30:73] assign _schedule_WIRE_35 = _schedule_T_344; // @[Mux.scala:30:73] assign _schedule_WIRE_33_1 = _schedule_WIRE_35; // @[Mux.scala:30:73] wire _schedule_T_345 = _schedule_T & _mshrs_0_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36] wire _schedule_T_346 = _schedule_T_1 & _mshrs_1_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36] wire _schedule_T_347 = _schedule_T_2 & _mshrs_2_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36] wire _schedule_T_348 = _schedule_T_3 & _mshrs_3_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36] wire _schedule_T_349 = _schedule_T_4 & _mshrs_4_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36] wire _schedule_T_350 = _schedule_T_5 & _mshrs_5_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36] wire _schedule_T_351 = _schedule_T_6 & _mshrs_6_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36] wire _schedule_T_352 = _schedule_T_345 \| _schedule_T_346; // @[Mux.scala:30:73] wire _schedule_T_353 = _schedule_T_352 \| _schedule_T_347; // @[Mux.scala:30:73] wire _schedule_T_354 = _schedule_T_353 \| _schedule_T_348; // @[Mux.scala:30:73] wire _schedule_T_355 = _schedule_T_354 \| _schedule_T_349; // @[Mux.scala:30:73] wire _schedule_T_356 = _schedule_T_355 \| _schedule_T_350; // @[Mux.scala:30:73] wire _schedule_T_357 = _schedule_T_356 \| _schedule_T_351; // @[Mux.scala:30:73] assign _schedule_WIRE_36 = _schedule_T_357; // @[Mux.scala:30:73] assign _schedule_WIRE_33_2 = _schedule_WIRE_36; // @[Mux.scala:30:73] wire _schedule_T_358 = _schedule_T & _mshrs_0_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_359 = _schedule_T_1 & _mshrs_1_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_360 = _schedule_T_2 & _mshrs_2_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_361 = _schedule_T_3 & _mshrs_3_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_362 = _schedule_T_4 & _mshrs_4_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_363 = _schedule_T_5 & _mshrs_5_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_364 = _schedule_T_6 & _mshrs_6_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_365 = _schedule_T_358 \| _schedule_T_359; // @[Mux.scala:30:73] wire _schedule_T_366 = _schedule_T_365 \| _schedule_T_360; // @[Mux.scala:30:73] wire _schedule_T_367 = _schedule_T_366 \| _schedule_T_361; // @[Mux.scala:30:73] wire _schedule_T_368 = _schedule_T_367 \| _schedule_T_362; // @[Mux.scala:30:73] wire _schedule_T_369 = _schedule_T_368 \| _schedule_T_363; // @[Mux.scala:30:73] wire _schedule_T_370 = _schedule_T_369 \| _schedule_T_364; // @[Mux.scala:30:73] assign _schedule_WIRE_37 = _schedule_T_370; // @[Mux.scala:30:73] assign _schedule_WIRE_19_valid = _schedule_WIRE_37; // @[Mux.scala:30:73] wire _schedule_WIRE_47; // @[Mux.scala:30:73] assign schedule_c_valid = _schedule_WIRE_38_valid; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_39_opcode; // @[Mux.scala:30:73] assign schedule_c_bits_opcode = _schedule_WIRE_38_bits_opcode; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_39_param; // @[Mux.scala:30:73] assign schedule_c_bits_param = _schedule_WIRE_38_bits_param; // @[Mux.scala:30:73] wire [12:0] _schedule_WIRE_39_tag; // @[Mux.scala:30:73] assign schedule_c_bits_tag = _schedule_WIRE_38_bits_tag; // @[Mux.scala:30:73] wire [9:0] _schedule_WIRE_39_set; // @[Mux.scala:30:73] assign schedule_c_bits_set = _schedule_WIRE_38_bits_set; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_39_way; // @[Mux.scala:30:73] assign schedule_c_bits_way = _schedule_WIRE_38_bits_way; // @[Mux.scala:30:73] wire _schedule_WIRE_39_dirty; // @[Mux.scala:30:73] assign schedule_c_bits_dirty = _schedule_WIRE_38_bits_dirty; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_46; // @[Mux.scala:30:73] assign _schedule_WIRE_38_bits_opcode = _schedule_WIRE_39_opcode; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_45; // @[Mux.scala:30:73] assign _schedule_WIRE_38_bits_param = _schedule_WIRE_39_param; // @[Mux.scala:30:73] wire [12:0] _schedule_WIRE_43; // @[Mux.scala:30:73] assign _schedule_WIRE_38_bits_tag = _schedule_WIRE_39_tag; // @[Mux.scala:30:73] wire [9:0] _schedule_WIRE_42; // @[Mux.scala:30:73] assign _schedule_WIRE_38_bits_set = _schedule_WIRE_39_set; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_41; // @[Mux.scala:30:73] assign _schedule_WIRE_38_bits_way = _schedule_WIRE_39_way; // @[Mux.scala:30:73] wire _schedule_WIRE_40; // @[Mux.scala:30:73] assign _schedule_WIRE_38_bits_dirty = _schedule_WIRE_39_dirty; // @[Mux.scala:30:73] wire _schedule_T_371 = _schedule_T & _mshrs_0_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_372 = _schedule_T_1 & _mshrs_1_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_373 = _schedule_T_2 & _mshrs_2_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_374 = _schedule_T_3 & _mshrs_3_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_375 = _schedule_T_4 & _mshrs_4_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_376 = _schedule_T_5 & _mshrs_5_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_377 = _schedule_T_6 & _mshrs_6_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_378 = _schedule_T_371 \| _schedule_T_372; // @[Mux.scala:30:73] wire _schedule_T_379 = _schedule_T_378 \| _schedule_T_373; // @[Mux.scala:30:73] wire _schedule_T_380 = _schedule_T_379 \| _schedule_T_374; // @[Mux.scala:30:73] wire _schedule_T_381 = _schedule_T_380 \| _schedule_T_375; // @[Mux.scala:30:73] wire _schedule_T_382 = _schedule_T_381 \| _schedule_T_376; // @[Mux.scala:30:73] wire _schedule_T_383 = _schedule_T_382 \| _schedule_T_377; // @[Mux.scala:30:73] assign _schedule_WIRE_40 = _schedule_T_383; // @[Mux.scala:30:73] assign _schedule_WIRE_39_dirty = _schedule_WIRE_40; // @[Mux.scala:30:73] wire [2:0] _schedule_T_384 = _schedule_T ? _mshrs_0_io_schedule_bits_c_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_385 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_c_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_386 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_c_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_387 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_c_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_388 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_c_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_389 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_c_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_390 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_c_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_391 = _schedule_T_384 \| _schedule_T_385; // @[Mux.scala:30:73] wire [2:0] _schedule_T_392 = _schedule_T_391 \| _schedule_T_386; // @[Mux.scala:30:73] wire [2:0] _schedule_T_393 = _schedule_T_392 \| _schedule_T_387; // @[Mux.scala:30:73] wire [2:0] _schedule_T_394 = _schedule_T_393 \| _schedule_T_388; // @[Mux.scala:30:73] wire [2:0] _schedule_T_395 = _schedule_T_394 \| _schedule_T_389; // @[Mux.scala:30:73] wire [2:0] _schedule_T_396 = _schedule_T_395 \| _schedule_T_390; // @[Mux.scala:30:73] assign _schedule_WIRE_41 = _schedule_T_396; // @[Mux.scala:30:73] assign _schedule_WIRE_39_way = _schedule_WIRE_41; // @[Mux.scala:30:73] wire [9:0] _schedule_T_397 = _schedule_T ? _mshrs_0_io_schedule_bits_c_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_398 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_c_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_399 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_c_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_400 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_c_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_401 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_c_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_402 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_c_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_403 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_c_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_404 = _schedule_T_397 \| _schedule_T_398; // @[Mux.scala:30:73] wire [9:0] _schedule_T_405 = _schedule_T_404 \| _schedule_T_399; // @[Mux.scala:30:73] wire [9:0] _schedule_T_406 = _schedule_T_405 \| _schedule_T_400; // @[Mux.scala:30:73] wire [9:0] _schedule_T_407 = _schedule_T_406 \| _schedule_T_401; // @[Mux.scala:30:73] wire [9:0] _schedule_T_408 = _schedule_T_407 \| _schedule_T_402; // @[Mux.scala:30:73] wire [9:0] _schedule_T_409 = _schedule_T_408 \| _schedule_T_403; // @[Mux.scala:30:73] assign _schedule_WIRE_42 = _schedule_T_409; // @[Mux.scala:30:73] assign _schedule_WIRE_39_set = _schedule_WIRE_42; // @[Mux.scala:30:73] wire [12:0] _schedule_T_410 = _schedule_T ? _mshrs_0_io_schedule_bits_c_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_411 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_c_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_412 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_c_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_413 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_c_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_414 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_c_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_415 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_c_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_416 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_c_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_417 = _schedule_T_410 \| _schedule_T_411; // @[Mux.scala:30:73] wire [12:0] _schedule_T_418 = _schedule_T_417 \| _schedule_T_412; // @[Mux.scala:30:73] wire [12:0] _schedule_T_419 = _schedule_T_418 \| _schedule_T_413; // @[Mux.scala:30:73] wire [12:0] _schedule_T_420 = _schedule_T_419 \| _schedule_T_414; // @[Mux.scala:30:73] wire [12:0] _schedule_T_421 = _schedule_T_420 \| _schedule_T_415; // @[Mux.scala:30:73] wire [12:0] _schedule_T_422 = _schedule_T_421 \| _schedule_T_416; // @[Mux.scala:30:73] assign _schedule_WIRE_43 = _schedule_T_422; // @[Mux.scala:30:73] assign _schedule_WIRE_39_tag = _schedule_WIRE_43; // @[Mux.scala:30:73] wire [2:0] _schedule_T_436 = _schedule_T ? _mshrs_0_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_437 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_438 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_439 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_440 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_441 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_442 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_443 = _schedule_T_436 \| _schedule_T_437; // @[Mux.scala:30:73] wire [2:0] _schedule_T_444 = _schedule_T_443 \| _schedule_T_438; // @[Mux.scala:30:73] wire [2:0] _schedule_T_445 = _schedule_T_444 \| _schedule_T_439; // @[Mux.scala:30:73] wire [2:0] _schedule_T_446 = _schedule_T_445 \| _schedule_T_440; // @[Mux.scala:30:73] wire [2:0] _schedule_T_447 = _schedule_T_446 \| _schedule_T_441; // @[Mux.scala:30:73] wire [2:0] _schedule_T_448 = _schedule_T_447 \| _schedule_T_442; // @[Mux.scala:30:73] assign _schedule_WIRE_45 = _schedule_T_448; // @[Mux.scala:30:73] assign _schedule_WIRE_39_param = _schedule_WIRE_45; // @[Mux.scala:30:73] wire [2:0] _schedule_T_449 = _schedule_T ? _mshrs_0_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_450 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_451 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_452 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_453 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_454 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_455 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_456 = _schedule_T_449 \| _schedule_T_450; // @[Mux.scala:30:73] wire [2:0] _schedule_T_457 = _schedule_T_456 \| _schedule_T_451; // @[Mux.scala:30:73] wire [2:0] _schedule_T_458 = _schedule_T_457 \| _schedule_T_452; // @[Mux.scala:30:73] wire [2:0] _schedule_T_459 = _schedule_T_458 \| _schedule_T_453; // @[Mux.scala:30:73] wire [2:0] _schedule_T_460 = _schedule_T_459 \| _schedule_T_454; // @[Mux.scala:30:73] wire [2:0] _schedule_T_461 = _schedule_T_460 \| _schedule_T_455; // @[Mux.scala:30:73] assign _schedule_WIRE_46 = _schedule_T_461; // @[Mux.scala:30:73] assign _schedule_WIRE_39_opcode = _schedule_WIRE_46; // @[Mux.scala:30:73] wire _schedule_T_462 = _schedule_T & _mshrs_0_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_463 = _schedule_T_1 & _mshrs_1_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_464 = _schedule_T_2 & _mshrs_2_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_465 = _schedule_T_3 & _mshrs_3_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_466 = _schedule_T_4 & _mshrs_4_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_467 = _schedule_T_5 & _mshrs_5_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_468 = _schedule_T_6 & _mshrs_6_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_469 = _schedule_T_462 \| _schedule_T_463; // @[Mux.scala:30:73] wire _schedule_T_470 = _schedule_T_469 \| _schedule_T_464; // @[Mux.scala:30:73] wire _schedule_T_471 = _schedule_T_470 \| _schedule_T_465; // @[Mux.scala:30:73] wire _schedule_T_472 = _schedule_T_471 \| _schedule_T_466; // @[Mux.scala:30:73] wire _schedule_T_473 = _schedule_T_472 \| _schedule_T_467; // @[Mux.scala:30:73] wire _schedule_T_474 = _schedule_T_473 \| _schedule_T_468; // @[Mux.scala:30:73] assign _schedule_WIRE_47 = _schedule_T_474; // @[Mux.scala:30:73] assign _schedule_WIRE_38_valid = _schedule_WIRE_47; // @[Mux.scala:30:73] wire _schedule_WIRE_54; // @[Mux.scala:30:73] assign schedule_b_valid = _schedule_WIRE_48_valid; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_49_param; // @[Mux.scala:30:73] assign schedule_b_bits_param = _schedule_WIRE_48_bits_param; // @[Mux.scala:30:73] wire [12:0] _schedule_WIRE_49_tag; // @[Mux.scala:30:73] assign schedule_b_bits_tag = _schedule_WIRE_48_bits_tag; // @[Mux.scala:30:73] wire [9:0] _schedule_WIRE_49_set; // @[Mux.scala:30:73] assign schedule_b_bits_set = _schedule_WIRE_48_bits_set; // @[Mux.scala:30:73] wire [1:0] _schedule_WIRE_49_clients; // @[Mux.scala:30:73] assign schedule_b_bits_clients = _schedule_WIRE_48_bits_clients; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_53; // @[Mux.scala:30:73] assign _schedule_WIRE_48_bits_param = _schedule_WIRE_49_param; // @[Mux.scala:30:73] wire [12:0] _schedule_WIRE_52; // @[Mux.scala:30:73] assign _schedule_WIRE_48_bits_tag = _schedule_WIRE_49_tag; // @[Mux.scala:30:73] wire [9:0] _schedule_WIRE_51; // @[Mux.scala:30:73] assign _schedule_WIRE_48_bits_set = _schedule_WIRE_49_set; // @[Mux.scala:30:73] wire [1:0] _schedule_WIRE_50; // @[Mux.scala:30:73] assign _schedule_WIRE_48_bits_clients = _schedule_WIRE_49_clients; // @[Mux.scala:30:73] wire [1:0] _schedule_T_475 = _schedule_T ? _mshrs_0_io_schedule_bits_b_bits_clients : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _schedule_T_476 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_b_bits_clients : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _schedule_T_477 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_b_bits_clients : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _schedule_T_478 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_b_bits_clients : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _schedule_T_479 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_b_bits_clients : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _schedule_T_480 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_b_bits_clients : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _schedule_T_481 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_b_bits_clients : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _schedule_T_482 = _schedule_T_475 \| _schedule_T_476; // @[Mux.scala:30:73] wire [1:0] _schedule_T_483 = _schedule_T_482 \| _schedule_T_477; // @[Mux.scala:30:73] wire [1:0] _schedule_T_484 = _schedule_T_483 \| _schedule_T_478; // @[Mux.scala:30:73] wire [1:0] _schedule_T_485 = _schedule_T_484 \| _schedule_T_479; // @[Mux.scala:30:73] wire [1:0] _schedule_T_486 = _schedule_T_485 \| _schedule_T_480; // @[Mux.scala:30:73] wire [1:0] _schedule_T_487 = _schedule_T_486 \| _schedule_T_481; // @[Mux.scala:30:73] assign _schedule_WIRE_50 = _schedule_T_487; // @[Mux.scala:30:73] assign _schedule_WIRE_49_clients = _schedule_WIRE_50; // @[Mux.scala:30:73] wire [9:0] _schedule_T_488 = _schedule_T ? _mshrs_0_io_schedule_bits_b_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_489 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_b_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_490 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_b_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_491 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_b_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_492 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_b_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_493 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_b_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_494 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_b_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_495 = _schedule_T_488 \| _schedule_T_489; // @[Mux.scala:30:73] wire [9:0] _schedule_T_496 = _schedule_T_495 \| _schedule_T_490; // @[Mux.scala:30:73] wire [9:0] _schedule_T_497 = _schedule_T_496 \| _schedule_T_491; // @[Mux.scala:30:73] wire [9:0] _schedule_T_498 = _schedule_T_497 \| _schedule_T_492; // @[Mux.scala:30:73] wire [9:0] _schedule_T_499 = _schedule_T_498 \| _schedule_T_493; // @[Mux.scala:30:73] wire [9:0] _schedule_T_500 = _schedule_T_499 \| _schedule_T_494; // @[Mux.scala:30:73] assign _schedule_WIRE_51 = _schedule_T_500; // @[Mux.scala:30:73] assign _schedule_WIRE_49_set = _schedule_WIRE_51; // @[Mux.scala:30:73] wire [12:0] _schedule_T_501 = _schedule_T ? _mshrs_0_io_schedule_bits_b_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_502 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_b_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_503 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_b_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_504 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_b_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_505 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_b_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_506 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_b_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_507 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_b_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_508 = _schedule_T_501 \| _schedule_T_502; // @[Mux.scala:30:73] wire [12:0] _schedule_T_509 = _schedule_T_508 \| _schedule_T_503; // @[Mux.scala:30:73] wire [12:0] _schedule_T_510 = _schedule_T_509 \| _schedule_T_504; // @[Mux.scala:30:73] wire [12:0] _schedule_T_511 = _schedule_T_510 \| _schedule_T_505; // @[Mux.scala:30:73] wire [12:0] _schedule_T_512 = _schedule_T_511 \| _schedule_T_506; // @[Mux.scala:30:73] wire [12:0] _schedule_T_513 = _schedule_T_512 \| _schedule_T_507; // @[Mux.scala:30:73] assign _schedule_WIRE_52 = _schedule_T_513; // @[Mux.scala:30:73] assign _schedule_WIRE_49_tag = _schedule_WIRE_52; // @[Mux.scala:30:73] wire [2:0] _schedule_T_514 = _schedule_T ? _mshrs_0_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_515 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_516 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_517 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_518 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_519 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_520 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_521 = _schedule_T_514 \| _schedule_T_515; // @[Mux.scala:30:73] wire [2:0] _schedule_T_522 = _schedule_T_521 \| _schedule_T_516; // @[Mux.scala:30:73] wire [2:0] _schedule_T_523 = _schedule_T_522 \| _schedule_T_517; // @[Mux.scala:30:73] wire [2:0] _schedule_T_524 = _schedule_T_523 \| _schedule_T_518; // @[Mux.scala:30:73] wire [2:0] _schedule_T_525 = _schedule_T_524 \| _schedule_T_519; // @[Mux.scala:30:73] wire [2:0] _schedule_T_526 = _schedule_T_525 \| _schedule_T_520; // @[Mux.scala:30:73] assign _schedule_WIRE_53 = _schedule_T_526; // @[Mux.scala:30:73] assign _schedule_WIRE_49_param = _schedule_WIRE_53; // @[Mux.scala:30:73] wire _schedule_T_527 = _schedule_T & _mshrs_0_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_528 = _schedule_T_1 & _mshrs_1_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_529 = _schedule_T_2 & _mshrs_2_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_530 = _schedule_T_3 & _mshrs_3_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_531 = _schedule_T_4 & _mshrs_4_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_532 = _schedule_T_5 & _mshrs_5_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_533 = _schedule_T_6 & _mshrs_6_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_534 = _schedule_T_527 \| _schedule_T_528; // @[Mux.scala:30:73] wire _schedule_T_535 = _schedule_T_534 \| _schedule_T_529; // @[Mux.scala:30:73] wire _schedule_T_536 = _schedule_T_535 \| _schedule_T_530; // @[Mux.scala:30:73] wire _schedule_T_537 = _schedule_T_536 \| _schedule_T_531; // @[Mux.scala:30:73] wire _schedule_T_538 = _schedule_T_537 \| _schedule_T_532; // @[Mux.scala:30:73] wire _schedule_T_539 = _schedule_T_538 \| _schedule_T_533; // @[Mux.scala:30:73] assign _schedule_WIRE_54 = _schedule_T_539; // @[Mux.scala:30:73] assign _schedule_WIRE_48_valid = _schedule_WIRE_54; // @[Mux.scala:30:73] wire _schedule_WIRE_62; // @[Mux.scala:30:73] assign schedule_a_valid = _schedule_WIRE_55_valid; // @[Mux.scala:30:73] wire [12:0] _schedule_WIRE_56_tag; // @[Mux.scala:30:73] assign schedule_a_bits_tag = _schedule_WIRE_55_bits_tag; // @[Mux.scala:30:73] wire [9:0] _schedule_WIRE_56_set; // @[Mux.scala:30:73] assign schedule_a_bits_set = _schedule_WIRE_55_bits_set; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_56_param; // @[Mux.scala:30:73] assign schedule_a_bits_param = _schedule_WIRE_55_bits_param; // @[Mux.scala:30:73] wire _schedule_WIRE_56_block; // @[Mux.scala:30:73] assign schedule_a_bits_block = _schedule_WIRE_55_bits_block; // @[Mux.scala:30:73] wire [12:0] _schedule_WIRE_61; // @[Mux.scala:30:73] assign _schedule_WIRE_55_bits_tag = _schedule_WIRE_56_tag; // @[Mux.scala:30:73] wire [9:0] _schedule_WIRE_60; // @[Mux.scala:30:73] assign _schedule_WIRE_55_bits_set = _schedule_WIRE_56_set; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_59; // @[Mux.scala:30:73] assign _schedule_WIRE_55_bits_param = _schedule_WIRE_56_param; // @[Mux.scala:30:73] wire _schedule_WIRE_57; // @[Mux.scala:30:73] assign _schedule_WIRE_55_bits_block = _schedule_WIRE_56_block; // @[Mux.scala:30:73] wire _schedule_T_540 = _schedule_T & _mshrs_0_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36] wire _schedule_T_541 = _schedule_T_1 & _mshrs_1_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36] wire _schedule_T_542 = _schedule_T_2 & _mshrs_2_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36] wire _schedule_T_543 = _schedule_T_3 & _mshrs_3_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36] wire _schedule_T_544 = _schedule_T_4 & _mshrs_4_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36] wire _schedule_T_545 = _schedule_T_5 & _mshrs_5_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36] wire _schedule_T_546 = _schedule_T_6 & _mshrs_6_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36] wire _schedule_T_547 = _schedule_T_540 \| _schedule_T_541; // @[Mux.scala:30:73] wire _schedule_T_548 = _schedule_T_547 \| _schedule_T_542; // @[Mux.scala:30:73] wire _schedule_T_549 = _schedule_T_548 \| _schedule_T_543; // @[Mux.scala:30:73] wire _schedule_T_550 = _schedule_T_549 \| _schedule_T_544; // @[Mux.scala:30:73] wire _schedule_T_551 = _schedule_T_550 \| _schedule_T_545; // @[Mux.scala:30:73] wire _schedule_T_552 = _schedule_T_551 \| _schedule_T_546; // @[Mux.scala:30:73] assign _schedule_WIRE_57 = _schedule_T_552; // @[Mux.scala:30:73] assign _schedule_WIRE_56_block = _schedule_WIRE_57; // @[Mux.scala:30:73] wire [2:0] _schedule_T_566 = _schedule_T ? _mshrs_0_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_567 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_568 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_569 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_570 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_571 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_572 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_573 = _schedule_T_566 \| _schedule_T_567; // @[Mux.scala:30:73] wire [2:0] _schedule_T_574 = _schedule_T_573 \| _schedule_T_568; // @[Mux.scala:30:73] wire [2:0] _schedule_T_575 = _schedule_T_574 \| _schedule_T_569; // @[Mux.scala:30:73] wire [2:0] _schedule_T_576 = _schedule_T_575 \| _schedule_T_570; // @[Mux.scala:30:73] wire [2:0] _schedule_T_577 = _schedule_T_576 \| _schedule_T_571; // @[Mux.scala:30:73] wire [2:0] _schedule_T_578 = _schedule_T_577 \| _schedule_T_572; // @[Mux.scala:30:73] assign _schedule_WIRE_59 = _schedule_T_578; // @[Mux.scala:30:73] assign _schedule_WIRE_56_param = _schedule_WIRE_59; // @[Mux.scala:30:73] wire [9:0] _schedule_T_579 = _schedule_T ? _mshrs_0_io_schedule_bits_a_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_580 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_a_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_581 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_a_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_582 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_a_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_583 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_a_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_584 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_a_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_585 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_a_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_586 = _schedule_T_579 \| _schedule_T_580; // @[Mux.scala:30:73] wire [9:0] _schedule_T_587 = _schedule_T_586 \| _schedule_T_581; // @[Mux.scala:30:73] wire [9:0] _schedule_T_588 = _schedule_T_587 \| _schedule_T_582; // @[Mux.scala:30:73] wire [9:0] _schedule_T_589 = _schedule_T_588 \| _schedule_T_583; // @[Mux.scala:30:73] wire [9:0] _schedule_T_590 = _schedule_T_589 \| _schedule_T_584; // @[Mux.scala:30:73] wire [9:0] _schedule_T_591 = _schedule_T_590 \| _schedule_T_585; // @[Mux.scala:30:73] assign _schedule_WIRE_60 = _schedule_T_591; // @[Mux.scala:30:73] assign _schedule_WIRE_56_set = _schedule_WIRE_60; // @[Mux.scala:30:73] wire [12:0] _schedule_T_592 = _schedule_T ? _mshrs_0_io_schedule_bits_a_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_593 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_a_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_594 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_a_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_595 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_a_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_596 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_a_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_597 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_a_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_598 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_a_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_599 = _schedule_T_592 \| _schedule_T_593; // @[Mux.scala:30:73] wire [12:0] _schedule_T_600 = _schedule_T_599 \| _schedule_T_594; // @[Mux.scala:30:73] wire [12:0] _schedule_T_601 = _schedule_T_600 \| _schedule_T_595; // @[Mux.scala:30:73] wire [12:0] _schedule_T_602 = _schedule_T_601 \| _schedule_T_596; // @[Mux.scala:30:73] wire [12:0] _schedule_T_603 = _schedule_T_602 \| _schedule_T_597; // @[Mux.scala:30:73] wire [12:0] _schedule_T_604 = _schedule_T_603 \| _schedule_T_598; // @[Mux.scala:30:73] assign _schedule_WIRE_61 = _schedule_T_604; // @[Mux.scala:30:73] assign _schedule_WIRE_56_tag = _schedule_WIRE_61; // @[Mux.scala:30:73] wire _schedule_T_605 = _schedule_T & _mshrs_0_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_606 = _schedule_T_1 & _mshrs_1_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_607 = _schedule_T_2 & _mshrs_2_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_608 = _schedule_T_3 & _mshrs_3_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_609 = _schedule_T_4 & _mshrs_4_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_610 = _schedule_T_5 & _mshrs_5_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_611 = _schedule_T_6 & _mshrs_6_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_612 = _schedule_T_605 \| _schedule_T_606; // @[Mux.scala:30:73] wire _schedule_T_613 = _schedule_T_612 \| _schedule_T_607; // @[Mux.scala:30:73] wire _schedule_T_614 = _schedule_T_613 \| _schedule_T_608; // @[Mux.scala:30:73] wire _schedule_T_615 = _schedule_T_614 \| _schedule_T_609; // @[Mux.scala:30:73] wire _schedule_T_616 = _schedule_T_615 \| _schedule_T_610; // @[Mux.scala:30:73] wire _schedule_T_617 = _schedule_T_616 \| _schedule_T_611; // @[Mux.scala:30:73] assign _schedule_WIRE_62 = _schedule_T_617; // @[Mux.scala:30:73] assign _schedule_WIRE_55_valid = _schedule_WIRE_62; // @[Mux.scala:30:73] wire [12:0] _scheduleTag_T_7 = _scheduleTag_T ? _mshrs_0_io_status_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _scheduleTag_T_8 = _scheduleTag_T_1 ? _mshrs_1_io_status_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _scheduleTag_T_9 = _scheduleTag_T_2 ? _mshrs_2_io_status_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _scheduleTag_T_10 = _scheduleTag_T_3 ? _mshrs_3_io_status_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _scheduleTag_T_11 = _scheduleTag_T_4 ? _mshrs_4_io_status_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _scheduleTag_T_12 = _scheduleTag_T_5 ? _mshrs_5_io_status_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _scheduleTag_T_13 = _scheduleTag_T_6 ? _mshrs_6_io_status_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _scheduleTag_T_14 = _scheduleTag_T_7 \| _scheduleTag_T_8; // @[Mux.scala:30:73] wire [12:0] _scheduleTag_T_15 = _scheduleTag_T_14 \| _scheduleTag_T_9; // @[Mux.scala:30:73] wire [12:0] _scheduleTag_T_16 = _scheduleTag_T_15 \| _scheduleTag_T_10; // @[Mux.scala:30:73] wire [12:0] _scheduleTag_T_17 = _scheduleTag_T_16 \| _scheduleTag_T_11; // @[Mux.scala:30:73] wire [12:0] _scheduleTag_T_18 = _scheduleTag_T_17 \| _scheduleTag_T_12; // @[Mux.scala:30:73] wire [12:0] _scheduleTag_T_19 = _scheduleTag_T_18 \| _scheduleTag_T_13; // @[Mux.scala:30:73] wire [12:0] scheduleTag = _scheduleTag_T_19; // @[Mux.scala:30:73] wire [9:0] _scheduleSet_T_7 = _scheduleSet_T ? _mshrs_0_io_status_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _scheduleSet_T_8 = _scheduleSet_T_1 ? _mshrs_1_io_status_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _scheduleSet_T_9 = _scheduleSet_T_2 ? _mshrs_2_io_status_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _scheduleSet_T_10 = _scheduleSet_T_3 ? _mshrs_3_io_status_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _scheduleSet_T_11 = _scheduleSet_T_4 ? _mshrs_4_io_status_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _scheduleSet_T_12 = _scheduleSet_T_5 ? _mshrs_5_io_status_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _scheduleSet_T_13 = _scheduleSet_T_6 ? _mshrs_6_io_status_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _scheduleSet_T_14 = _scheduleSet_T_7 \| _scheduleSet_T_8; // @[Mux.scala:30:73] wire [9:0] _scheduleSet_T_15 = _scheduleSet_T_14 \| _scheduleSet_T_9; // @[Mux.scala:30:73] wire [9:0] _scheduleSet_T_16 = _scheduleSet_T_15 \| _scheduleSet_T_10; // @[Mux.scala:30:73] wire [9:0] _scheduleSet_T_17 = _scheduleSet_T_16 \| _scheduleSet_T_11; // @[Mux.scala:30:73] wire [9:0] _scheduleSet_T_18 = _scheduleSet_T_17 \| _scheduleSet_T_12; // @[Mux.scala:30:73] wire [9:0] _scheduleSet_T_19 = _scheduleSet_T_18 \| _scheduleSet_T_13; // @[Mux.scala:30:73] wire [9:0] scheduleSet = _scheduleSet_T_19; // @[Mux.scala:30:73] wire [5:0] _robin_filter_T = mshr_selectOH[6:1]; // @[package.scala:262:48] wire [6:0] _robin_filter_T_1 = {mshr_selectOH[6], mshr_selectOH[5:0] \| _robin_filter_T}; // @[Mux.scala:32:36] wire [4:0] _robin_filter_T_2 = _robin_filter_T_1[6:2]; // @[package.scala:262:{43,48}] wire [6:0] _robin_filter_T_3 = {_robin_filter_T_1[6:5], _robin_filter_T_1[4:0] \| _robin_filter_T_2}; // @[package.scala:262:{43,48}] wire [2:0] _robin_filter_T_4 = _robin_filter_T_3[6:4]; // @[package.scala:262:{43,48}] wire [6:0] _robin_filter_T_5 = {_robin_filter_T_3[6:3], _robin_filter_T_3[2:0] \| _robin_filter_T_4}; // @[package.scala:262:{43,48}] wire [6:0] _robin_filter_T_6 = _robin_filter_T_5; // @[package.scala:262:43, :263:17] wire [6:0] _robin_filter_T_7 = ~_robin_filter_T_6; // @[package.scala:263:17] wire _schedule_c_bits_source_T = schedule_c_bits_opcode[1]; // @[Mux.scala:30:73] assign _schedule_c_bits_source_T_1 = _schedule_c_bits_source_T ? mshr_select : 3'h0; // @[OneHot.scala:32:10] assign schedule_c_bits_source = _schedule_c_bits_source_T_1; // @[Mux.scala:30:73] assign _nestedwb_set_T = select_c ? _mshrs_6_io_status_bits_set : _mshrs_5_io_status_bits_set; // @[Scheduler.scala:71:46, :153:32, :155:24] assign nestedwb_set = _nestedwb_set_T; // @[Scheduler.scala:75:22, :155:24] assign _nestedwb_tag_T = select_c ? _mshrs_6_io_status_bits_tag : _mshrs_5_io_status_bits_tag; // @[Scheduler.scala:71:46, :153:32, :156:24] assign nestedwb_tag = _nestedwb_tag_T; // @[Scheduler.scala:75:22, :156:24] wire _GEN = select_bc & _mshrs_5_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :154:32, :157:37] wire _nestedwb_b_toN_T; // @[Scheduler.scala:157:37] assign _nestedwb_b_toN_T = _GEN; // @[Scheduler.scala:157:37] wire _nestedwb_b_toB_T; // @[Scheduler.scala:158:37] assign _nestedwb_b_toB_T = _GEN; // @[Scheduler.scala:157:37, :158:37] assign _nestedwb_b_clr_dirty_T = _GEN; // @[Scheduler.scala:157:37, :159:37] wire _nestedwb_b_toN_T_1 = _mshrs_5_io_schedule_bits_dir_bits_data_state == 2'h0; // @[Scheduler.scala:71:46, :157:123] assign _nestedwb_b_toN_T_2 = _nestedwb_b_toN_T & _nestedwb_b_toN_T_1; // @[Scheduler.scala:157:{37,75,123}] assign nestedwb_b_toN = _nestedwb_b_toN_T_2; // @[Scheduler.scala:75:22, :157:75] wire _nestedwb_b_toB_T_1 = _mshrs_5_io_schedule_bits_dir_bits_data_state == 2'h1; // @[Scheduler.scala:71:46, :158:123] assign _nestedwb_b_toB_T_2 = _nestedwb_b_toB_T & _nestedwb_b_toB_T_1; // @[Scheduler.scala:158:{37,75,123}] assign nestedwb_b_toB = _nestedwb_b_toB_T_2; // @[Scheduler.scala:75:22, :158:75] assign nestedwb_b_clr_dirty = _nestedwb_b_clr_dirty_T; // @[Scheduler.scala:75:22, :159:37] wire _nestedwb_c_set_dirty_T = select_c & _mshrs_6_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :153:32, :160:37] assign _nestedwb_c_set_dirty_T_1 = _nestedwb_c_set_dirty_T & _mshrs_6_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46, :160:{37,75}] assign nestedwb_c_set_dirty = _nestedwb_c_set_dirty_T_1; // @[Scheduler.scala:75:22, :160:75] wire _request_ready_T_2; // @[Scheduler.scala:261:40] wire _request_valid_T_2; // @[Scheduler.scala:164:39] wire _request_bits_T_1_prio_0; // @[Scheduler.scala:165:22] wire _view__WIRE_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_1_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_2_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_3_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_4_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_5_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_6_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95] wire _request_bits_T_1_prio_2; // @[Scheduler.scala:165:22] wire _request_bits_T_1_control; // @[Scheduler.scala:165:22] wire _view__WIRE_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_1_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_2_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_3_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_4_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_5_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_6_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _request_bits_T_1_opcode; // @[Scheduler.scala:165:22] wire _view__WIRE_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_1_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_2_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_3_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_4_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_5_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_6_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _request_bits_T_1_param; // @[Scheduler.scala:165:22] wire [2:0] _view__WIRE_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_1_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_2_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_3_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_4_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_5_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_6_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _request_bits_T_1_size; // @[Scheduler.scala:165:22] wire [2:0] _view__WIRE_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_1_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_2_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_3_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_4_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_5_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_6_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _request_bits_T_1_source; // @[Scheduler.scala:165:22] wire [2:0] _view__WIRE_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_1_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_2_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_3_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_4_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_5_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_6_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95] wire [12:0] _request_bits_T_1_tag; // @[Scheduler.scala:165:22] wire [5:0] _view__WIRE_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_1_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_2_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_3_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_4_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_5_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_6_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _request_bits_T_1_offset; // @[Scheduler.scala:165:22] wire [12:0] _view__WIRE_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95] wire [12:0] _view__WIRE_1_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95] wire [12:0] _view__WIRE_2_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95] wire [12:0] _view__WIRE_3_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95] wire [12:0] _view__WIRE_4_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95] wire [12:0] _view__WIRE_5_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95] wire [12:0] _view__WIRE_6_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _request_bits_T_1_put; // @[Scheduler.scala:165:22] wire [5:0] _view__WIRE_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_1_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_2_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_3_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_4_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_5_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_6_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95] wire [9:0] _request_bits_T_1_set; // @[Scheduler.scala:165:22] wire [5:0] _view__WIRE_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_1_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_2_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_3_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_4_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_5_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_6_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95] wire [9:0] request_bits_set; // @[Scheduler.scala:163:21] wire request_ready; // @[Scheduler.scala:163:21] wire request_valid; // @[Scheduler.scala:163:21] wire _request_valid_T = _sinkA_io_req_valid \| _sinkX_io_req_valid; // @[Scheduler.scala:54:21, :58:21, :164:62] wire _request_valid_T_1 = _request_valid_T \| _sinkC_io_req_valid; // @[Scheduler.scala:55:21, :164:{62,84}] assign _request_valid_T_2 = _directory_io_ready & _request_valid_T_1; // @[Scheduler.scala:68:25, :164:{39,84}] assign request_valid = _request_valid_T_2; // @[Scheduler.scala:163:21, :164:39] wire [2:0] _request_bits_T_opcode = _sinkX_io_req_valid ? 3'h0 : _sinkA_io_req_bits_opcode; // @[Scheduler.scala:54:21, :58:21, :166:22] wire [2:0] _request_bits_T_param = _sinkX_io_req_valid ? 3'h0 : _sinkA_io_req_bits_param; // @[Scheduler.scala:54:21, :58:21, :166:22] wire [2:0] _request_bits_T_size = _sinkX_io_req_valid ? 3'h6 : _sinkA_io_req_bits_size; // @[Scheduler.scala:54:21, :58:21, :166:22] wire [5:0] _request_bits_T_source = _sinkX_io_req_valid ? 6'h0 : _sinkA_io_req_bits_source; // @[Scheduler.scala:54:21, :58:21, :166:22] wire [12:0] _request_bits_T_tag = _sinkX_io_req_valid ? _sinkX_io_req_bits_tag : _sinkA_io_req_bits_tag; // @[Scheduler.scala:54:21, :58:21, :166:22] wire [5:0] _request_bits_T_offset = _sinkX_io_req_valid ? 6'h0 : _sinkA_io_req_bits_offset; // @[Scheduler.scala:54:21, :58:21, :166:22] wire [5:0] _request_bits_T_put = _sinkX_io_req_valid ? 6'h0 : _sinkA_io_req_bits_put; // @[Scheduler.scala:54:21, :58:21, :166:22] wire [9:0] _request_bits_T_set = _sinkX_io_req_valid ? _sinkX_io_req_bits_set : _sinkA_io_req_bits_set; // @[Scheduler.scala:54:21, :58:21, :166:22] wire _request_bits_T_control; // @[Scheduler.scala:166:22] assign _request_bits_T_1_control = ~_sinkC_io_req_valid & _request_bits_T_control; // @[Scheduler.scala:55:21, :165:22, :166:22] assign _request_bits_T_1_opcode = _sinkC_io_req_valid ? _sinkC_io_req_bits_opcode : _request_bits_T_opcode; // @[Scheduler.scala:55:21, :165:22, :166:22] assign _request_bits_T_1_param = _sinkC_io_req_valid ? _sinkC_io_req_bits_param : _request_bits_T_param; // @[Scheduler.scala:55:21, :165:22, :166:22] assign _request_bits_T_1_size = _sinkC_io_req_valid ? _sinkC_io_req_bits_size : _request_bits_T_size; // @[Scheduler.scala:55:21, :165:22, :166:22] assign _request_bits_T_1_source = _sinkC_io_req_valid ? _sinkC_io_req_bits_source : _request_bits_T_source; // @[Scheduler.scala:55:21, :165:22, :166:22] assign _request_bits_T_1_tag = _sinkC_io_req_valid ? _sinkC_io_req_bits_tag : _request_bits_T_tag; // @[Scheduler.scala:55:21, :165:22, :166:22] assign _request_bits_T_1_offset = _sinkC_io_req_valid ? _sinkC_io_req_bits_offset : _request_bits_T_offset; // @[Scheduler.scala:55:21, :165:22, :166:22] assign _request_bits_T_1_put = _sinkC_io_req_valid ? _sinkC_io_req_bits_put : _request_bits_T_put; // @[Scheduler.scala:55:21, :165:22, :166:22] assign _request_bits_T_1_set = _sinkC_io_req_valid ? _sinkC_io_req_bits_set : _request_bits_T_set; // @[Scheduler.scala:55:21, :165:22, :166:22] assign _request_bits_T_1_prio_0 = ~_sinkC_io_req_valid; // @[Scheduler.scala:55:21, :165:22] assign request_bits_prio_0 = _request_bits_T_1_prio_0; // @[Scheduler.scala:163:21, :165:22] assign request_bits_prio_2 = _request_bits_T_1_prio_2; // @[Scheduler.scala:163:21, :165:22] assign request_bits_control = _request_bits_T_1_control; // @[Scheduler.scala:163:21, :165:22] assign request_bits_opcode = _request_bits_T_1_opcode; // @[Scheduler.scala:163:21, :165:22] assign request_bits_param = _request_bits_T_1_param; // @[Scheduler.scala:163:21, :165:22] assign request_bits_size = _request_bits_T_1_size; // @[Scheduler.scala:163:21, :165:22] assign request_bits_source = _request_bits_T_1_source; // @[Scheduler.scala:163:21, :165:22] assign request_bits_tag = _request_bits_T_1_tag; // @[Scheduler.scala:163:21, :165:22] assign request_bits_offset = _request_bits_T_1_offset; // @[Scheduler.scala:163:21, :165:22] assign request_bits_put = _request_bits_T_1_put; // @[Scheduler.scala:163:21, :165:22] assign request_bits_set = _request_bits_T_1_set; // @[Scheduler.scala:163:21, :165:22] wire _GEN_0 = _directory_io_ready & request_ready; // @[Scheduler.scala:68:25, :163:21, :167:44] wire _sinkC_io_req_ready_T; // @[Scheduler.scala:167:44] assign _sinkC_io_req_ready_T = _GEN_0; // @[Scheduler.scala:167:44] wire _sinkX_io_req_ready_T; // @[Scheduler.scala:168:44] assign _sinkX_io_req_ready_T = _GEN_0; // @[Scheduler.scala:167:44, :168:44] wire _sinkA_io_req_ready_T; // @[Scheduler.scala:169:44] assign _sinkA_io_req_ready_T = _GEN_0; // @[Scheduler.scala:167:44, :169:44] wire _sinkX_io_req_ready_T_1 = ~_sinkC_io_req_valid; // @[Scheduler.scala:55:21, :165:22, :168:64] wire _sinkX_io_req_ready_T_2 = _sinkX_io_req_ready_T & _sinkX_io_req_ready_T_1; // @[Scheduler.scala:168:{44,61,64}] wire _sinkA_io_req_ready_T_1 = ~_sinkC_io_req_valid; // @[Scheduler.scala:55:21, :165:22, :169:64] wire _sinkA_io_req_ready_T_2 = _sinkA_io_req_ready_T & _sinkA_io_req_ready_T_1; // @[Scheduler.scala:169:{44,61,64}] wire _sinkA_io_req_ready_T_3 = ~_sinkX_io_req_valid; // @[Scheduler.scala:58:21, :169:87] wire _sinkA_io_req_ready_T_4 = _sinkA_io_req_ready_T_2 & _sinkA_io_req_ready_T_3; // @[Scheduler.scala:169:{61,84,87}] wire _setMatches_T = _mshrs_0_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83] wire _setMatches_T_1 = _mshrs_0_io_status_valid & _setMatches_T; // @[Scheduler.scala:71:46, :172:{59,83}] wire _setMatches_T_2 = _mshrs_1_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83] wire _setMatches_T_3 = _mshrs_1_io_status_valid & _setMatches_T_2; // @[Scheduler.scala:71:46, :172:{59,83}] wire _setMatches_T_4 = _mshrs_2_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83] wire _setMatches_T_5 = _mshrs_2_io_status_valid & _setMatches_T_4; // @[Scheduler.scala:71:46, :172:{59,83}] wire _setMatches_T_6 = _mshrs_3_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83] wire _setMatches_T_7 = _mshrs_3_io_status_valid & _setMatches_T_6; // @[Scheduler.scala:71:46, :172:{59,83}] wire _setMatches_T_8 = _mshrs_4_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83] wire _setMatches_T_9 = _mshrs_4_io_status_valid & _setMatches_T_8; // @[Scheduler.scala:71:46, :172:{59,83}] wire _setMatches_T_10 = _mshrs_5_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83] wire _setMatches_T_11 = _mshrs_5_io_status_valid & _setMatches_T_10; // @[Scheduler.scala:71:46, :172:{59,83}] wire _setMatches_T_12 = _mshrs_6_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83] wire _setMatches_T_13 = _mshrs_6_io_status_valid & _setMatches_T_12; // @[Scheduler.scala:71:46, :172:{59,83}] wire [1:0] setMatches_lo_hi = {_setMatches_T_5, _setMatches_T_3}; // @[Scheduler.scala:172:{23,59}] wire [2:0] setMatches_lo = {setMatches_lo_hi, _setMatches_T_1}; // @[Scheduler.scala:172:{23,59}] wire [1:0] setMatches_hi_lo = {_setMatches_T_9, _setMatches_T_7}; // @[Scheduler.scala:172:{23,59}] wire [1:0] setMatches_hi_hi = {_setMatches_T_13, _setMatches_T_11}; // @[Scheduler.scala:172:{23,59}] wire [3:0] setMatches_hi = {setMatches_hi_hi, setMatches_hi_lo}; // @[Scheduler.scala:172:23] wire [6:0] setMatches = {setMatches_hi, setMatches_lo}; // @[Scheduler.scala:172:23] wire _alloc_T = \|setMatches; // @[Scheduler.scala:172:23, :173:27] wire alloc = ~_alloc_T; // @[Scheduler.scala:173:{15,27}] wire _blockB_T = setMatches[0]; // @[Mux.scala:32:36] wire _blockC_T = setMatches[0]; // @[Mux.scala:32:36] wire _nestB_T = setMatches[0]; // @[Mux.scala:32:36] wire _nestC_T = setMatches[0]; // @[Mux.scala:32:36] wire _blockB_T_1 = setMatches[1]; // @[Mux.scala:32:36] wire _blockC_T_1 = setMatches[1]; // @[Mux.scala:32:36] wire _nestB_T_1 = setMatches[1]; // @[Mux.scala:32:36] wire _nestC_T_1 = setMatches[1]; // @[Mux.scala:32:36] wire _blockB_T_2 = setMatches[2]; // @[Mux.scala:32:36] wire _blockC_T_2 = setMatches[2]; // @[Mux.scala:32:36] wire _nestB_T_2 = setMatches[2]; // @[Mux.scala:32:36] wire _nestC_T_2 = setMatches[2]; // @[Mux.scala:32:36] wire _blockB_T_3 = setMatches[3]; // @[Mux.scala:32:36] wire _blockC_T_3 = setMatches[3]; // @[Mux.scala:32:36] wire _nestB_T_3 = setMatches[3]; // @[Mux.scala:32:36] wire _nestC_T_3 = setMatches[3]; // @[Mux.scala:32:36] wire _blockB_T_4 = setMatches[4]; // @[Mux.scala:32:36] wire _blockC_T_4 = setMatches[4]; // @[Mux.scala:32:36] wire _nestB_T_4 = setMatches[4]; // @[Mux.scala:32:36] wire _nestC_T_4 = setMatches[4]; // @[Mux.scala:32:36] wire _blockB_T_5 = setMatches[5]; // @[Mux.scala:32:36] wire _blockC_T_5 = setMatches[5]; // @[Mux.scala:32:36] wire _nestB_T_5 = setMatches[5]; // @[Mux.scala:32:36] wire _nestC_T_5 = setMatches[5]; // @[Mux.scala:32:36] wire _blockB_T_6 = setMatches[6]; // @[Mux.scala:32:36] wire _blockC_T_6 = setMatches[6]; // @[Mux.scala:32:36] wire _nestB_T_6 = setMatches[6]; // @[Mux.scala:32:36] wire _nestC_T_6 = setMatches[6]; // @[Mux.scala:32:36] wire _blockB_T_7 = _blockB_T & _mshrs_0_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36] wire _blockB_T_8 = _blockB_T_1 & _mshrs_1_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36] wire _blockB_T_9 = _blockB_T_2 & _mshrs_2_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36] wire _blockB_T_10 = _blockB_T_3 & _mshrs_3_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36] wire _blockB_T_11 = _blockB_T_4 & _mshrs_4_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36] wire _blockB_T_12 = _blockB_T_5 & _mshrs_5_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36] wire _blockB_T_13 = _blockB_T_6 & _mshrs_6_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36] wire _blockB_T_14 = _blockB_T_7 \| _blockB_T_8; // @[Mux.scala:30:73] wire _blockB_T_15 = _blockB_T_14 \| _blockB_T_9; // @[Mux.scala:30:73] wire _blockB_T_16 = _blockB_T_15 \| _blockB_T_10; // @[Mux.scala:30:73] wire _blockB_T_17 = _blockB_T_16 \| _blockB_T_11; // @[Mux.scala:30:73] wire _blockB_T_18 = _blockB_T_17 \| _blockB_T_12; // @[Mux.scala:30:73] wire _blockB_T_19 = _blockB_T_18 \| _blockB_T_13; // @[Mux.scala:30:73] wire _blockB_WIRE = _blockB_T_19; // @[Mux.scala:30:73] wire _blockC_T_7 = _blockC_T & _mshrs_0_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36] wire _blockC_T_8 = _blockC_T_1 & _mshrs_1_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36] wire _blockC_T_9 = _blockC_T_2 & _mshrs_2_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36] wire _blockC_T_10 = _blockC_T_3 & _mshrs_3_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36] wire _blockC_T_11 = _blockC_T_4 & _mshrs_4_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36] wire _blockC_T_12 = _blockC_T_5 & _mshrs_5_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36] wire _blockC_T_13 = _blockC_T_6 & _mshrs_6_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36] wire _blockC_T_14 = _blockC_T_7 \| _blockC_T_8; // @[Mux.scala:30:73] wire _blockC_T_15 = _blockC_T_14 \| _blockC_T_9; // @[Mux.scala:30:73] wire _blockC_T_16 = _blockC_T_15 \| _blockC_T_10; // @[Mux.scala:30:73] wire _blockC_T_17 = _blockC_T_16 \| _blockC_T_11; // @[Mux.scala:30:73] wire _blockC_T_18 = _blockC_T_17 \| _blockC_T_12; // @[Mux.scala:30:73] wire _blockC_T_19 = _blockC_T_18 \| _blockC_T_13; // @[Mux.scala:30:73] wire _blockC_WIRE = _blockC_T_19; // @[Mux.scala:30:73] wire blockC = _blockC_WIRE & request_bits_prio_2; // @[Mux.scala:30:73] wire _nestB_T_7 = _nestB_T & _mshrs_0_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36] wire _nestB_T_8 = _nestB_T_1 & _mshrs_1_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36] wire _nestB_T_9 = _nestB_T_2 & _mshrs_2_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36] wire _nestB_T_10 = _nestB_T_3 & _mshrs_3_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36] wire _nestB_T_11 = _nestB_T_4 & _mshrs_4_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36] wire _nestB_T_12 = _nestB_T_5 & _mshrs_5_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36] wire _nestB_T_13 = _nestB_T_6 & _mshrs_6_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36] wire _nestB_T_14 = _nestB_T_7 \| _nestB_T_8; // @[Mux.scala:30:73] wire _nestB_T_15 = _nestB_T_14 \| _nestB_T_9; // @[Mux.scala:30:73] wire _nestB_T_16 = _nestB_T_15 \| _nestB_T_10; // @[Mux.scala:30:73] wire _nestB_T_17 = _nestB_T_16 \| _nestB_T_11; // @[Mux.scala:30:73] wire _nestB_T_18 = _nestB_T_17 \| _nestB_T_12; // @[Mux.scala:30:73] wire _nestB_T_19 = _nestB_T_18 \| _nestB_T_13; // @[Mux.scala:30:73] wire _nestB_WIRE = _nestB_T_19; // @[Mux.scala:30:73] wire _nestC_T_7 = _nestC_T & _mshrs_0_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36] wire _nestC_T_8 = _nestC_T_1 & _mshrs_1_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36] wire _nestC_T_9 = _nestC_T_2 & _mshrs_2_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36] wire _nestC_T_10 = _nestC_T_3 & _mshrs_3_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36] wire _nestC_T_11 = _nestC_T_4 & _mshrs_4_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36] wire _nestC_T_12 = _nestC_T_5 & _mshrs_5_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36] wire _nestC_T_13 = _nestC_T_6 & _mshrs_6_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36] wire _nestC_T_14 = _nestC_T_7 \| _nestC_T_8; // @[Mux.scala:30:73] wire _nestC_T_15 = _nestC_T_14 \| _nestC_T_9; // @[Mux.scala:30:73] wire _nestC_T_16 = _nestC_T_15 \| _nestC_T_10; // @[Mux.scala:30:73] wire _nestC_T_17 = _nestC_T_16 \| _nestC_T_11; // @[Mux.scala:30:73] wire _nestC_T_18 = _nestC_T_17 \| _nestC_T_12; // @[Mux.scala:30:73] wire _nestC_T_19 = _nestC_T_18 \| _nestC_T_13; // @[Mux.scala:30:73] wire _nestC_WIRE = _nestC_T_19; // @[Mux.scala:30:73] wire nestC = _nestC_WIRE & request_bits_prio_2; // @[Mux.scala:30:73] wire _prioFilter_T = ~request_bits_prio_0; // @[Scheduler.scala:163:21, :182:46] wire [1:0] prioFilter_hi = {request_bits_prio_2, _prioFilter_T}; // @[Scheduler.scala:163:21, :182:{23,46}] wire [6:0] prioFilter = {prioFilter_hi, 5'h1F}; // @[Scheduler.scala:182:23] wire [6:0] lowerMatches = setMatches & prioFilter; // @[Scheduler.scala:172:23, :182:23, :183:33] wire _queue_T = \|lowerMatches; // @[Scheduler.scala:183:33, :185:28] wire _queue_T_2 = _queue_T; // @[Scheduler.scala:185:{28,32}] wire _queue_T_3 = ~nestC; // @[Scheduler.scala:180:70, :185:45] wire _queue_T_4 = _queue_T_2 & _queue_T_3; // @[Scheduler.scala:185:{32,42,45}] wire _queue_T_6 = _queue_T_4; // @[Scheduler.scala:185:{42,52}] wire _queue_T_7 = ~blockC; // @[Scheduler.scala:176:70, :185:66] wire queue = _queue_T_6 & _queue_T_7; // @[Scheduler.scala:185:{52,63,66}] wire _T_7 = request_valid & queue; // @[Scheduler.scala:163:21, :185:63, :195:31] wire _bypass_T; // @[Scheduler.scala:213:30] assign _bypass_T = _T_7; // @[Scheduler.scala:195:31, :213:30] wire _bypass_T_1; // @[Scheduler.scala:231:32] assign _bypass_T_1 = _T_7; // @[Scheduler.scala:195:31, :231:32] wire _bypass_T_2; // @[Scheduler.scala:231:32] assign _bypass_T_2 = _T_7; // @[Scheduler.scala:195:31, :231:32] wire _bypass_T_3; // @[Scheduler.scala:231:32] assign _bypass_T_3 = _T_7; // @[Scheduler.scala:195:31, :231:32] wire _bypass_T_4; // @[Scheduler.scala:231:32] assign _bypass_T_4 = _T_7; // @[Scheduler.scala:195:31, :231:32] wire _bypass_T_5; // @[Scheduler.scala:231:32] assign _bypass_T_5 = _T_7; // @[Scheduler.scala:195:31, :231:32] wire _bypass_T_6; // @[Scheduler.scala:231:32] assign _bypass_T_6 = _T_7; // @[Scheduler.scala:195:31, :231:32] wire _bypass_T_7; // @[Scheduler.scala:231:32] assign _bypass_T_7 = _T_7; // @[Scheduler.scala:195:31, :231:32] wire _requests_io_push_valid_T; // @[Scheduler.scala:270:43] assign _requests_io_push_valid_T = _T_7; // @[Scheduler.scala:195:31, :270:43] wire _lowerMatches1_T = lowerMatches[6]; // @[Scheduler.scala:183:33, :200:21] wire _lowerMatches1_T_2 = lowerMatches[5]; // @[Scheduler.scala:183:33, :201:21] wire [6:0] _lowerMatches1_T_4 = _lowerMatches1_T_2 ? 7'h20 : lowerMatches; // @[Scheduler.scala:183:33, :201:{8,21}] wire [6:0] lowerMatches1 = _lowerMatches1_T ? 7'h40 : _lowerMatches1_T_4; // @[Scheduler.scala:200:{8,21}, :201:8] wire [6:0] _requests_io_push_bits_index_T = lowerMatches1; // @[Scheduler.scala:200:8, :274:30] wire [13:0] _GEN_1 = {2{mshr_selectOH}}; // @[Scheduler.scala:121:70, :206:30] wire [13:0] selected_requests_hi; // @[Scheduler.scala:206:30] assign selected_requests_hi = _GEN_1; // @[Scheduler.scala:206:30] wire [13:0] pop_index_hi; // @[Scheduler.scala:241:31] assign pop_index_hi = _GEN_1; // @[Scheduler.scala:206:30, :241:31] wire [20:0] _selected_requests_T = {selected_requests_hi, mshr_selectOH}; // @[Scheduler.scala:121:70, :206:30] wire [20:0] selected_requests = _selected_requests_T & _requests_io_valid; // @[Scheduler.scala:70:24, :206:{30,76}] wire [6:0] _a_pop_T = selected_requests[6:0]; // @[Scheduler.scala:206:76, :207:32] wire a_pop = \|_a_pop_T; // @[Scheduler.scala:207:{32,79}] wire [6:0] _b_pop_T = selected_requests[13:7]; // @[Scheduler.scala:206:76, :208:32] wire b_pop = \|_b_pop_T; // @[Scheduler.scala:208:{32,79}] wire _bypassMatches_T_4 = b_pop; // @[Scheduler.scala:208:79, :211:76] wire [6:0] _c_pop_T = selected_requests[20:14]; // @[Scheduler.scala:206:76, :209:32] wire c_pop = \|_c_pop_T; // @[Scheduler.scala:209:{32,79}] wire [6:0] _bypassMatches_T = mshr_selectOH & lowerMatches1; // @[Scheduler.scala:121:70, :200:8, :210:38] wire _bypassMatches_T_1 = \|_bypassMatches_T; // @[Scheduler.scala:210:{38,55}] wire _bypassMatches_T_2 = c_pop \| request_bits_prio_2; // @[Scheduler.scala:163:21, :209:79, :211:33] wire _bypassMatches_T_3 = ~c_pop; // @[Scheduler.scala:209:79, :211:58] wire _bypassMatches_T_5 = ~b_pop; // @[Scheduler.scala:208:79, :211:101] wire _bypassMatches_T_6 = ~a_pop; // @[Scheduler.scala:207:79, :211:109] wire _bypassMatches_T_7 = _bypassMatches_T_4 ? _bypassMatches_T_5 : _bypassMatches_T_6; // @[Scheduler.scala:211:{69,76,101,109}] wire _bypassMatches_T_8 = _bypassMatches_T_2 ? _bypassMatches_T_3 : _bypassMatches_T_7; // @[Scheduler.scala:211:{26,33,58,69}] wire bypassMatches = _bypassMatches_T_1 & _bypassMatches_T_8; // @[Scheduler.scala:210:{55,59}, :211:26] wire _may_pop_T = a_pop \| b_pop; // @[Scheduler.scala:207:79, :208:79, :212:23] wire may_pop = _may_pop_T \| c_pop; // @[Scheduler.scala:209:79, :212:{23,32}] wire bypass = _bypass_T & bypassMatches; // @[Scheduler.scala:210:59, :213:{30,39}] wire _will_reload_T = may_pop \| bypass; // @[Scheduler.scala:212:32, :213:39, :214:49] wire will_reload = schedule_reload & _will_reload_T; // @[Mux.scala:30:73] wire _GEN_2 = schedule_reload & may_pop; // @[Mux.scala:30:73] wire _will_pop_T; // @[Scheduler.scala:215:34] assign _will_pop_T = _GEN_2; // @[Scheduler.scala:215:34] wire _mshr_uses_directory_assuming_no_bypass_T; // @[Scheduler.scala:247:64] assign _mshr_uses_directory_assuming_no_bypass_T = _GEN_2; // @[Scheduler.scala:215:34, :247:64] wire _will_pop_T_1 = ~bypass; // @[Scheduler.scala:213:39, :215:48] wire will_pop = _will_pop_T & _will_pop_T_1; // @[Scheduler.scala:215:{34,45,48}] wire a_pop_1 = _requests_io_valid[0]; // @[Scheduler.scala:70:24, :225:34] wire b_pop_1 = _requests_io_valid[7]; // @[Scheduler.scala:70:24, :226:34] wire _bypassMatches_T_12 = b_pop_1; // @[Scheduler.scala:226:34, :229:78] wire c_pop_1 = _requests_io_valid[14]; // @[Scheduler.scala:70:24, :227:34] wire _bypassMatches_T_9 = lowerMatches1[0]; // @[Scheduler.scala:200:8, :228:38] wire _bypassMatches_T_10 = c_pop_1 \| request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35] wire _bypassMatches_T_11 = ~c_pop_1; // @[Scheduler.scala:227:34, :229:60] wire _bypassMatches_T_13 = ~b_pop_1; // @[Scheduler.scala:226:34, :229:103] wire _bypassMatches_T_14 = ~a_pop_1; // @[Scheduler.scala:225:34, :229:111] wire _bypassMatches_T_15 = _bypassMatches_T_12 ? _bypassMatches_T_13 : _bypassMatches_T_14; // @[Scheduler.scala:229:{71,78,103,111}] wire _bypassMatches_T_16 = _bypassMatches_T_10 ? _bypassMatches_T_11 : _bypassMatches_T_15; // @[Scheduler.scala:229:{28,35,60,71}] wire bypassMatches_1 = _bypassMatches_T_9 & _bypassMatches_T_16; // @[Scheduler.scala:228:{38,42}, :229:28] wire _may_pop_T_1 = a_pop_1 \| b_pop_1; // @[Scheduler.scala:225:34, :226:34, :230:25] wire may_pop_1 = _may_pop_T_1 \| c_pop_1; // @[Scheduler.scala:227:34, :230:{25,34}] wire bypass_1 = _bypass_T_1 & bypassMatches_1; // @[Scheduler.scala:228:42, :231:{32,41}] wire _will_reload_T_1 = may_pop_1 \| bypass_1; // @[Scheduler.scala:230:34, :231:41, :232:61] wire will_reload_1 = _mshrs_0_io_schedule_bits_reload & _will_reload_T_1; // @[Scheduler.scala:71:46, :232:{49,61}] wire _view__T_prio_0 = bypass_1 ? _view__WIRE_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_prio_1 = ~bypass_1 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78] wire _view__T_prio_2 = bypass_1 ? _view__WIRE_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_control = bypass_1 ? _view__WIRE_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_opcode = bypass_1 ? _view__WIRE_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_param = bypass_1 ? _view__WIRE_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_size = bypass_1 ? _view__WIRE_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_source = bypass_1 ? _view__WIRE_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [12:0] _view__T_tag = bypass_1 ? _view__WIRE_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_offset = bypass_1 ? _view__WIRE_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_put = bypass_1 ? _view__WIRE_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _mshrs_0_io_allocate_bits_repeat_T = mshrs_0_io_allocate_bits_tag == _mshrs_0_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70] wire _mshrs_0_io_allocate_valid_T = sel & will_reload_1; // @[Scheduler.scala:223:28, :232:49, :236:32] wire a_pop_2 = _requests_io_valid[1]; // @[Scheduler.scala:70:24, :225:34] wire b_pop_2 = _requests_io_valid[8]; // @[Scheduler.scala:70:24, :226:34] wire _bypassMatches_T_20 = b_pop_2; // @[Scheduler.scala:226:34, :229:78] wire c_pop_2 = _requests_io_valid[15]; // @[Scheduler.scala:70:24, :227:34] wire _bypassMatches_T_17 = lowerMatches1[1]; // @[Scheduler.scala:200:8, :228:38] wire _bypassMatches_T_18 = c_pop_2 \| request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35] wire _bypassMatches_T_19 = ~c_pop_2; // @[Scheduler.scala:227:34, :229:60] wire _bypassMatches_T_21 = ~b_pop_2; // @[Scheduler.scala:226:34, :229:103] wire _bypassMatches_T_22 = ~a_pop_2; // @[Scheduler.scala:225:34, :229:111] wire _bypassMatches_T_23 = _bypassMatches_T_20 ? _bypassMatches_T_21 : _bypassMatches_T_22; // @[Scheduler.scala:229:{71,78,103,111}] wire _bypassMatches_T_24 = _bypassMatches_T_18 ? _bypassMatches_T_19 : _bypassMatches_T_23; // @[Scheduler.scala:229:{28,35,60,71}] wire bypassMatches_2 = _bypassMatches_T_17 & _bypassMatches_T_24; // @[Scheduler.scala:228:{38,42}, :229:28] wire _may_pop_T_2 = a_pop_2 \| b_pop_2; // @[Scheduler.scala:225:34, :226:34, :230:25] wire may_pop_2 = _may_pop_T_2 \| c_pop_2; // @[Scheduler.scala:227:34, :230:{25,34}] wire bypass_2 = _bypass_T_2 & bypassMatches_2; // @[Scheduler.scala:228:42, :231:{32,41}] wire _will_reload_T_2 = may_pop_2 \| bypass_2; // @[Scheduler.scala:230:34, :231:41, :232:61] wire will_reload_2 = _mshrs_1_io_schedule_bits_reload & _will_reload_T_2; // @[Scheduler.scala:71:46, :232:{49,61}] wire _view__T_1_prio_0 = bypass_2 ? _view__WIRE_1_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_1_prio_1 = ~bypass_2 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78] wire _view__T_1_prio_2 = bypass_2 ? _view__WIRE_1_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_1_control = bypass_2 ? _view__WIRE_1_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_1_opcode = bypass_2 ? _view__WIRE_1_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_1_param = bypass_2 ? _view__WIRE_1_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_1_size = bypass_2 ? _view__WIRE_1_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_1_source = bypass_2 ? _view__WIRE_1_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [12:0] _view__T_1_tag = bypass_2 ? _view__WIRE_1_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_1_offset = bypass_2 ? _view__WIRE_1_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_1_put = bypass_2 ? _view__WIRE_1_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _mshrs_1_io_allocate_bits_repeat_T = mshrs_1_io_allocate_bits_tag == _mshrs_1_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70] wire _mshrs_1_io_allocate_valid_T = sel_1 & will_reload_2; // @[Scheduler.scala:223:28, :232:49, :236:32] wire a_pop_3 = _requests_io_valid[2]; // @[Scheduler.scala:70:24, :225:34] wire b_pop_3 = _requests_io_valid[9]; // @[Scheduler.scala:70:24, :226:34] wire _bypassMatches_T_28 = b_pop_3; // @[Scheduler.scala:226:34, :229:78] wire c_pop_3 = _requests_io_valid[16]; // @[Scheduler.scala:70:24, :227:34] wire _bypassMatches_T_25 = lowerMatches1[2]; // @[Scheduler.scala:200:8, :228:38] wire _bypassMatches_T_26 = c_pop_3 \| request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35] wire _bypassMatches_T_27 = ~c_pop_3; // @[Scheduler.scala:227:34, :229:60] wire _bypassMatches_T_29 = ~b_pop_3; // @[Scheduler.scala:226:34, :229:103] wire _bypassMatches_T_30 = ~a_pop_3; // @[Scheduler.scala:225:34, :229:111] wire _bypassMatches_T_31 = _bypassMatches_T_28 ? _bypassMatches_T_29 : _bypassMatches_T_30; // @[Scheduler.scala:229:{71,78,103,111}] wire _bypassMatches_T_32 = _bypassMatches_T_26 ? _bypassMatches_T_27 : _bypassMatches_T_31; // @[Scheduler.scala:229:{28,35,60,71}] wire bypassMatches_3 = _bypassMatches_T_25 & _bypassMatches_T_32; // @[Scheduler.scala:228:{38,42}, :229:28] wire _may_pop_T_3 = a_pop_3 \| b_pop_3; // @[Scheduler.scala:225:34, :226:34, :230:25] wire may_pop_3 = _may_pop_T_3 \| c_pop_3; // @[Scheduler.scala:227:34, :230:{25,34}] wire bypass_3 = _bypass_T_3 & bypassMatches_3; // @[Scheduler.scala:228:42, :231:{32,41}] wire _will_reload_T_3 = may_pop_3 \| bypass_3; // @[Scheduler.scala:230:34, :231:41, :232:61] wire will_reload_3 = _mshrs_2_io_schedule_bits_reload & _will_reload_T_3; // @[Scheduler.scala:71:46, :232:{49,61}] wire _view__T_2_prio_0 = bypass_3 ? _view__WIRE_2_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_2_prio_1 = ~bypass_3 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78] wire _view__T_2_prio_2 = bypass_3 ? _view__WIRE_2_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_2_control = bypass_3 ? _view__WIRE_2_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_2_opcode = bypass_3 ? _view__WIRE_2_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_2_param = bypass_3 ? _view__WIRE_2_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_2_size = bypass_3 ? _view__WIRE_2_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_2_source = bypass_3 ? _view__WIRE_2_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [12:0] _view__T_2_tag = bypass_3 ? _view__WIRE_2_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_2_offset = bypass_3 ? _view__WIRE_2_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_2_put = bypass_3 ? _view__WIRE_2_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _mshrs_2_io_allocate_bits_repeat_T = mshrs_2_io_allocate_bits_tag == _mshrs_2_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70] wire _mshrs_2_io_allocate_valid_T = sel_2 & will_reload_3; // @[Scheduler.scala:223:28, :232:49, :236:32] wire a_pop_4 = _requests_io_valid[3]; // @[Scheduler.scala:70:24, :225:34] wire b_pop_4 = _requests_io_valid[10]; // @[Scheduler.scala:70:24, :226:34] wire _bypassMatches_T_36 = b_pop_4; // @[Scheduler.scala:226:34, :229:78] wire c_pop_4 = _requests_io_valid[17]; // @[Scheduler.scala:70:24, :227:34] wire _bypassMatches_T_33 = lowerMatches1[3]; // @[Scheduler.scala:200:8, :228:38] wire _bypassMatches_T_34 = c_pop_4 \| request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35] wire _bypassMatches_T_35 = ~c_pop_4; // @[Scheduler.scala:227:34, :229:60] wire _bypassMatches_T_37 = ~b_pop_4; // @[Scheduler.scala:226:34, :229:103] wire _bypassMatches_T_38 = ~a_pop_4; // @[Scheduler.scala:225:34, :229:111] wire _bypassMatches_T_39 = _bypassMatches_T_36 ? _bypassMatches_T_37 : _bypassMatches_T_38; // @[Scheduler.scala:229:{71,78,103,111}] wire _bypassMatches_T_40 = _bypassMatches_T_34 ? _bypassMatches_T_35 : _bypassMatches_T_39; // @[Scheduler.scala:229:{28,35,60,71}] wire bypassMatches_4 = _bypassMatches_T_33 & _bypassMatches_T_40; // @[Scheduler.scala:228:{38,42}, :229:28] wire _may_pop_T_4 = a_pop_4 \| b_pop_4; // @[Scheduler.scala:225:34, :226:34, :230:25] wire may_pop_4 = _may_pop_T_4 \| c_pop_4; // @[Scheduler.scala:227:34, :230:{25,34}] wire bypass_4 = _bypass_T_4 & bypassMatches_4; // @[Scheduler.scala:228:42, :231:{32,41}] wire _will_reload_T_4 = may_pop_4 \| bypass_4; // @[Scheduler.scala:230:34, :231:41, :232:61] wire will_reload_4 = _mshrs_3_io_schedule_bits_reload & _will_reload_T_4; // @[Scheduler.scala:71:46, :232:{49,61}] wire _view__T_3_prio_0 = bypass_4 ? _view__WIRE_3_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_3_prio_1 = ~bypass_4 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78] wire _view__T_3_prio_2 = bypass_4 ? _view__WIRE_3_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_3_control = bypass_4 ? _view__WIRE_3_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_3_opcode = bypass_4 ? _view__WIRE_3_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_3_param = bypass_4 ? _view__WIRE_3_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_3_size = bypass_4 ? _view__WIRE_3_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_3_source = bypass_4 ? _view__WIRE_3_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [12:0] _view__T_3_tag = bypass_4 ? _view__WIRE_3_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_3_offset = bypass_4 ? _view__WIRE_3_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_3_put = bypass_4 ? _view__WIRE_3_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _mshrs_3_io_allocate_bits_repeat_T = mshrs_3_io_allocate_bits_tag == _mshrs_3_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70] wire _mshrs_3_io_allocate_valid_T = sel_3 & will_reload_4; // @[Scheduler.scala:223:28, :232:49, :236:32] wire a_pop_5 = _requests_io_valid[4]; // @[Scheduler.scala:70:24, :225:34] wire b_pop_5 = _requests_io_valid[11]; // @[Scheduler.scala:70:24, :226:34] wire _bypassMatches_T_44 = b_pop_5; // @[Scheduler.scala:226:34, :229:78] wire c_pop_5 = _requests_io_valid[18]; // @[Scheduler.scala:70:24, :227:34] wire _bypassMatches_T_41 = lowerMatches1[4]; // @[Scheduler.scala:200:8, :228:38] wire _bypassMatches_T_42 = c_pop_5 \| request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35] wire _bypassMatches_T_43 = ~c_pop_5; // @[Scheduler.scala:227:34, :229:60] wire _bypassMatches_T_45 = ~b_pop_5; // @[Scheduler.scala:226:34, :229:103] wire _bypassMatches_T_46 = ~a_pop_5; // @[Scheduler.scala:225:34, :229:111] wire _bypassMatches_T_47 = _bypassMatches_T_44 ? _bypassMatches_T_45 : _bypassMatches_T_46; // @[Scheduler.scala:229:{71,78,103,111}] wire _bypassMatches_T_48 = _bypassMatches_T_42 ? _bypassMatches_T_43 : _bypassMatches_T_47; // @[Scheduler.scala:229:{28,35,60,71}] wire bypassMatches_5 = _bypassMatches_T_41 & _bypassMatches_T_48; // @[Scheduler.scala:228:{38,42}, :229:28] wire _may_pop_T_5 = a_pop_5 \| b_pop_5; // @[Scheduler.scala:225:34, :226:34, :230:25] wire may_pop_5 = _may_pop_T_5 \| c_pop_5; // @[Scheduler.scala:227:34, :230:{25,34}] wire bypass_5 = _bypass_T_5 & bypassMatches_5; // @[Scheduler.scala:228:42, :231:{32,41}] wire _will_reload_T_5 = may_pop_5 \| bypass_5; // @[Scheduler.scala:230:34, :231:41, :232:61] wire will_reload_5 = _mshrs_4_io_schedule_bits_reload & _will_reload_T_5; // @[Scheduler.scala:71:46, :232:{49,61}] wire _view__T_4_prio_0 = bypass_5 ? _view__WIRE_4_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_4_prio_1 = ~bypass_5 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78] wire _view__T_4_prio_2 = bypass_5 ? _view__WIRE_4_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_4_control = bypass_5 ? _view__WIRE_4_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_4_opcode = bypass_5 ? _view__WIRE_4_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_4_param = bypass_5 ? _view__WIRE_4_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_4_size = bypass_5 ? _view__WIRE_4_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_4_source = bypass_5 ? _view__WIRE_4_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [12:0] _view__T_4_tag = bypass_5 ? _view__WIRE_4_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_4_offset = bypass_5 ? _view__WIRE_4_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_4_put = bypass_5 ? _view__WIRE_4_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _mshrs_4_io_allocate_bits_repeat_T = mshrs_4_io_allocate_bits_tag == _mshrs_4_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70] wire _mshrs_4_io_allocate_valid_T = sel_4 & will_reload_5; // @[Scheduler.scala:223:28, :232:49, :236:32] wire a_pop_6 = _requests_io_valid[5]; // @[Scheduler.scala:70:24, :225:34] wire b_pop_6 = _requests_io_valid[12]; // @[Scheduler.scala:70:24, :226:34] wire _bypassMatches_T_52 = b_pop_6; // @[Scheduler.scala:226:34, :229:78] wire c_pop_6 = _requests_io_valid[19]; // @[Scheduler.scala:70:24, :227:34] wire _bypassMatches_T_49 = lowerMatches1[5]; // @[Scheduler.scala:200:8, :228:38] wire _bypassMatches_T_50 = c_pop_6 \| request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35] wire _bypassMatches_T_51 = ~c_pop_6; // @[Scheduler.scala:227:34, :229:60] wire _bypassMatches_T_53 = ~b_pop_6; // @[Scheduler.scala:226:34, :229:103] wire _bypassMatches_T_54 = ~a_pop_6; // @[Scheduler.scala:225:34, :229:111] wire _bypassMatches_T_55 = _bypassMatches_T_52 ? _bypassMatches_T_53 : _bypassMatches_T_54; // @[Scheduler.scala:229:{71,78,103,111}] wire _bypassMatches_T_56 = _bypassMatches_T_50 ? _bypassMatches_T_51 : _bypassMatches_T_55; // @[Scheduler.scala:229:{28,35,60,71}] wire bypassMatches_6 = _bypassMatches_T_49 & _bypassMatches_T_56; // @[Scheduler.scala:228:{38,42}, :229:28] wire _may_pop_T_6 = a_pop_6 \| b_pop_6; // @[Scheduler.scala:225:34, :226:34, :230:25] wire may_pop_6 = _may_pop_T_6 \| c_pop_6; // @[Scheduler.scala:227:34, :230:{25,34}] wire bypass_6 = _bypass_T_6 & bypassMatches_6; // @[Scheduler.scala:228:42, :231:{32,41}] wire _will_reload_T_6 = may_pop_6 \| bypass_6; // @[Scheduler.scala:230:34, :231:41, :232:61] wire will_reload_6 = _mshrs_5_io_schedule_bits_reload & _will_reload_T_6; // @[Scheduler.scala:71:46, :232:{49,61}] wire _view__T_5_prio_0 = bypass_6 ? _view__WIRE_5_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_5_prio_1 = ~bypass_6 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78] wire _view__T_5_prio_2 = bypass_6 ? _view__WIRE_5_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_5_control = bypass_6 ? _view__WIRE_5_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_5_opcode = bypass_6 ? _view__WIRE_5_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_5_param = bypass_6 ? _view__WIRE_5_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_5_size = bypass_6 ? _view__WIRE_5_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_5_source = bypass_6 ? _view__WIRE_5_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [12:0] _view__T_5_tag = bypass_6 ? _view__WIRE_5_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_5_offset = bypass_6 ? _view__WIRE_5_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_5_put = bypass_6 ? _view__WIRE_5_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _mshrs_5_io_allocate_bits_repeat_T = mshrs_5_io_allocate_bits_tag == _mshrs_5_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70, :287:131, :289:74] wire _mshrs_5_io_allocate_valid_T = sel_5 & will_reload_6; // @[Scheduler.scala:223:28, :232:49, :236:32] wire a_pop_7 = _requests_io_valid[6]; // @[Scheduler.scala:70:24, :225:34] wire b_pop_7 = _requests_io_valid[13]; // @[Scheduler.scala:70:24, :226:34] wire _bypassMatches_T_60 = b_pop_7; // @[Scheduler.scala:226:34, :229:78] wire c_pop_7 = _requests_io_valid[20]; // @[Scheduler.scala:70:24, :227:34] wire _bypassMatches_T_57 = lowerMatches1[6]; // @[Scheduler.scala:200:8, :228:38] wire _bypassMatches_T_58 = c_pop_7 \| request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35] wire _bypassMatches_T_59 = ~c_pop_7; // @[Scheduler.scala:227:34, :229:60] wire _bypassMatches_T_61 = ~b_pop_7; // @[Scheduler.scala:226:34, :229:103] wire _bypassMatches_T_62 = ~a_pop_7; // @[Scheduler.scala:225:34, :229:111] wire _bypassMatches_T_63 = _bypassMatches_T_60 ? _bypassMatches_T_61 : _bypassMatches_T_62; // @[Scheduler.scala:229:{71,78,103,111}] wire _bypassMatches_T_64 = _bypassMatches_T_58 ? _bypassMatches_T_59 : _bypassMatches_T_63; // @[Scheduler.scala:229:{28,35,60,71}] wire bypassMatches_7 = _bypassMatches_T_57 & _bypassMatches_T_64; // @[Scheduler.scala:228:{38,42}, :229:28] wire _may_pop_T_7 = a_pop_7 \| b_pop_7; // @[Scheduler.scala:225:34, :226:34, :230:25] wire may_pop_7 = _may_pop_T_7 \| c_pop_7; // @[Scheduler.scala:227:34, :230:{25,34}] wire bypass_7 = _bypass_T_7 & bypassMatches_7; // @[Scheduler.scala:228:42, :231:{32,41}] wire _will_reload_T_7 = may_pop_7 \| bypass_7; // @[Scheduler.scala:230:34, :231:41, :232:61] wire will_reload_7 = _mshrs_6_io_schedule_bits_reload & _will_reload_T_7; // @[Scheduler.scala:71:46, :232:{49,61}] wire _view__T_6_prio_0 = bypass_7 ? _view__WIRE_6_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_6_prio_1 = ~bypass_7 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78] wire _view__T_6_prio_2 = bypass_7 ? _view__WIRE_6_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_6_control = bypass_7 ? _view__WIRE_6_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_6_opcode = bypass_7 ? _view__WIRE_6_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_6_param = bypass_7 ? _view__WIRE_6_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_6_size = bypass_7 ? _view__WIRE_6_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_6_source = bypass_7 ? _view__WIRE_6_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [12:0] _view__T_6_tag = bypass_7 ? _view__WIRE_6_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_6_offset = bypass_7 ? _view__WIRE_6_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_6_put = bypass_7 ? _view__WIRE_6_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _mshrs_6_io_allocate_bits_repeat_T = mshrs_6_io_allocate_bits_tag == _mshrs_6_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70, :295:103, :297:73] wire _mshrs_6_io_allocate_valid_T = sel_6 & will_reload_7; // @[Scheduler.scala:223:28, :232:49, :236:32] wire [20:0] _prio_requests_T = ~_requests_io_valid; // @[Scheduler.scala:70:24, :240:25] wire [13:0] _prio_requests_T_1 = _requests_io_valid[20:7]; // @[Scheduler.scala:70:24, :240:65] wire [20:0] _prio_requests_T_2 = {_prio_requests_T[20:14], _prio_requests_T[13:0] \| _prio_requests_T_1}; // @[Scheduler.scala:240:{25,44,65}] wire [6:0] _prio_requests_T_3 = _requests_io_valid[20:14]; // @[Scheduler.scala:70:24, :240:103] wire [20:0] _prio_requests_T_4 = {_prio_requests_T_2[20:7], _prio_requests_T_2[6:0] \| _prio_requests_T_3}; // @[Scheduler.scala:240:{44,82,103}] wire [20:0] prio_requests = ~_prio_requests_T_4; // @[Scheduler.scala:240:{23,82}] wire [20:0] _pop_index_T = {pop_index_hi, mshr_selectOH}; // @[Scheduler.scala:121:70, :241:31] wire [20:0] _pop_index_T_1 = _pop_index_T & prio_requests; // @[Scheduler.scala:240:23, :241:{31,77}] wire [4:0] pop_index_hi_1 = _pop_index_T_1[20:16]; // @[OneHot.scala:30:18] wire [15:0] pop_index_lo = _pop_index_T_1[15:0]; // @[OneHot.scala:31:18] wire _pop_index_T_2 = \|pop_index_hi_1; // @[OneHot.scala:30:18, :32:14] wire [15:0] _pop_index_T_3 = {11'h0, pop_index_hi_1} \| pop_index_lo; // @[OneHot.scala:30:18, :31:18, :32:28] wire [7:0] pop_index_hi_2 = _pop_index_T_3[15:8]; // @[OneHot.scala:30:18, :32:28] wire [7:0] pop_index_lo_1 = _pop_index_T_3[7:0]; // @[OneHot.scala:31:18, :32:28] wire _pop_index_T_4 = \|pop_index_hi_2; // @[OneHot.scala:30:18, :32:14] wire [7:0] _pop_index_T_5 = pop_index_hi_2 \| pop_index_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire [3:0] pop_index_hi_3 = _pop_index_T_5[7:4]; // @[OneHot.scala:30:18, :32:28] wire [3:0] pop_index_lo_2 = _pop_index_T_5[3:0]; // @[OneHot.scala:31:18, :32:28] wire _pop_index_T_6 = \|pop_index_hi_3; // @[OneHot.scala:30:18, :32:14] wire [3:0] _pop_index_T_7 = pop_index_hi_3 \| pop_index_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] pop_index_hi_4 = _pop_index_T_7[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] pop_index_lo_3 = _pop_index_T_7[1:0]; // @[OneHot.scala:31:18, :32:28] wire _pop_index_T_8 = \|pop_index_hi_4; // @[OneHot.scala:30:18, :32:14] wire [1:0] _pop_index_T_9 = pop_index_hi_4 \| pop_index_lo_3; // @[OneHot.scala:30:18, :31:18, :32:28] wire _pop_index_T_10 = _pop_index_T_9[1]; // @[OneHot.scala:32:28] wire [1:0] _pop_index_T_11 = {_pop_index_T_8, _pop_index_T_10}; // @[OneHot.scala:32:{10,14}] wire [2:0] _pop_index_T_12 = {_pop_index_T_6, _pop_index_T_11}; // @[OneHot.scala:32:{10,14}] wire [3:0] _pop_index_T_13 = {_pop_index_T_4, _pop_index_T_12}; // @[OneHot.scala:32:{10,14}] wire [4:0] pop_index = {_pop_index_T_2, _pop_index_T_13}; // @[OneHot.scala:32:{10,14}] wire lb_tag_mismatch = scheduleTag != _requests_io_data_tag; // @[Mux.scala:30:73] wire mshr_uses_directory_assuming_no_bypass = _mshr_uses_directory_assuming_no_bypass_T & lb_tag_mismatch; // @[Scheduler.scala:246:37, :247:{64,75}] wire mshr_uses_directory_for_lb = will_pop & lb_tag_mismatch; // @[Scheduler.scala:215:45, :246:37, :248:45] wire [12:0] _mshr_uses_directory_T = bypass ? request_bits_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :163:21, :213:39, :249:63] wire _mshr_uses_directory_T_1 = scheduleTag != _mshr_uses_directory_T; // @[Mux.scala:30:73] wire mshr_uses_directory = will_reload & _mshr_uses_directory_T_1; // @[Scheduler.scala:214:37, :249:{41,56}] wire [1:0] mshr_validOH_lo_hi = {_mshrs_2_io_status_valid, _mshrs_1_io_status_valid}; // @[Scheduler.scala:71:46, :252:25] wire [2:0] mshr_validOH_lo = {mshr_validOH_lo_hi, _mshrs_0_io_status_valid}; // @[Scheduler.scala:71:46, :252:25] wire [1:0] mshr_validOH_hi_lo = {_mshrs_4_io_status_valid, _mshrs_3_io_status_valid}; // @[Scheduler.scala:71:46, :252:25] wire [1:0] mshr_validOH_hi_hi = {_mshrs_6_io_status_valid, _mshrs_5_io_status_valid}; // @[Scheduler.scala:71:46, :252:25] wire [3:0] mshr_validOH_hi = {mshr_validOH_hi_hi, mshr_validOH_hi_lo}; // @[Scheduler.scala:252:25] wire [6:0] mshr_validOH = {mshr_validOH_hi, mshr_validOH_lo}; // @[Scheduler.scala:252:25] wire [6:0] _mshr_free_T = ~mshr_validOH; // @[Scheduler.scala:252:25, :253:20] wire [6:0] _mshr_free_T_1 = _mshr_free_T & prioFilter; // @[Scheduler.scala:182:23, :253:{20,34}] wire mshr_free = \|_mshr_free_T_1; // @[Scheduler.scala:253:{34,48}] wire bypassQueue = schedule_reload & bypassMatches; // @[Mux.scala:30:73] wire _request_alloc_cases_T = ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16] wire _request_alloc_cases_T_1 = alloc & _request_alloc_cases_T; // @[Scheduler.scala:173:15, :258:{13,16}] wire _request_alloc_cases_T_2 = _request_alloc_cases_T_1 & mshr_free; // @[Scheduler.scala:253:48, :258:{13,56}] wire _request_alloc_cases_T_9 = _request_alloc_cases_T_2; // @[Scheduler.scala:258:{56,70}] wire _request_alloc_cases_T_3 = ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :259:16] wire _request_alloc_cases_T_5 = ~_mshrs_5_io_status_valid; // @[Scheduler.scala:71:46, :259:59] wire _request_alloc_cases_T_7 = ~_mshrs_6_io_status_valid; // @[Scheduler.scala:71:46, :259:87] wire _request_alloc_cases_T_10 = ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :260:16] wire _request_alloc_cases_T_11 = nestC & _request_alloc_cases_T_10; // @[Scheduler.scala:180:70, :260:{13,16}] wire _request_alloc_cases_T_12 = ~_mshrs_6_io_status_valid; // @[Scheduler.scala:71:46, :259:87, :260:59] wire _request_alloc_cases_T_13 = _request_alloc_cases_T_11 & _request_alloc_cases_T_12; // @[Scheduler.scala:260:{13,56,59}] wire request_alloc_cases = _request_alloc_cases_T_9 \| _request_alloc_cases_T_13; // @[Scheduler.scala:258:70, :259:112, :260:56] wire _request_ready_T = bypassQueue \| _requests_io_push_ready; // @[Scheduler.scala:70:24, :256:37, :261:66] wire _request_ready_T_1 = queue & _request_ready_T; // @[Scheduler.scala:185:63, :261:{50,66}] assign _request_ready_T_2 = request_alloc_cases \| _request_ready_T_1; // @[Scheduler.scala:259:112, :261:{40,50}] assign request_ready = _request_ready_T_2; // @[Scheduler.scala:163:21, :261:40] wire alloc_uses_directory = request_valid & request_alloc_cases; // @[Scheduler.scala:163:21, :259:112, :262:44] wire _directory_io_read_valid_T = mshr_uses_directory \| alloc_uses_directory; // @[Scheduler.scala:249:41, :262:44, :265:50] wire [9:0] _directory_io_read_bits_set_T = mshr_uses_directory_for_lb ? scheduleSet : request_bits_set; // @[Mux.scala:30:73] wire [12:0] _directory_io_read_bits_tag_T = mshr_uses_directory_for_lb ? _requests_io_data_tag : request_bits_tag; // @[Scheduler.scala:70:24, :163:21, :248:45, :267:36] wire _requests_io_push_valid_T_1 = ~bypassQueue; // @[Scheduler.scala:256:37, :270:55] wire _requests_io_push_valid_T_2 = _requests_io_push_valid_T & _requests_io_push_valid_T_1; // @[Scheduler.scala:270:{43,52,55}] wire [2:0] requests_io_push_bits_index_hi = _requests_io_push_bits_index_T[6:4]; // @[OneHot.scala:30:18] wire [3:0] requests_io_push_bits_index_lo = _requests_io_push_bits_index_T[3:0]; // @[OneHot.scala:31:18] wire _requests_io_push_bits_index_T_1 = \|requests_io_push_bits_index_hi; // @[OneHot.scala:30:18, :32:14] wire [3:0] _requests_io_push_bits_index_T_2 = {1'h0, requests_io_push_bits_index_hi} \| requests_io_push_bits_index_lo; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] requests_io_push_bits_index_hi_1 = _requests_io_push_bits_index_T_2[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] requests_io_push_bits_index_lo_1 = _requests_io_push_bits_index_T_2[1:0]; // @[OneHot.scala:31:18, :32:28] wire _requests_io_push_bits_index_T_3 = \|requests_io_push_bits_index_hi_1; // @[OneHot.scala:30:18, :32:14] wire [1:0] _requests_io_push_bits_index_T_4 = requests_io_push_bits_index_hi_1 \| requests_io_push_bits_index_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire _requests_io_push_bits_index_T_5 = _requests_io_push_bits_index_T_4[1]; // @[OneHot.scala:32:28] wire [1:0] _requests_io_push_bits_index_T_6 = {_requests_io_push_bits_index_T_3, _requests_io_push_bits_index_T_5}; // @[OneHot.scala:32:{10,14}] wire [2:0] _requests_io_push_bits_index_T_7 = {_requests_io_push_bits_index_T_1, _requests_io_push_bits_index_T_6}; // @[OneHot.scala:32:{10,14}] wire [13:0] _requests_io_push_bits_index_T_8 = {lowerMatches1, 7'h0}; // @[Scheduler.scala:200:8, :275:30] wire [5:0] requests_io_push_bits_index_hi_2 = _requests_io_push_bits_index_T_8[13:8]; // @[OneHot.scala:30:18] wire [7:0] requests_io_push_bits_index_lo_2 = _requests_io_push_bits_index_T_8[7:0]; // @[OneHot.scala:31:18] wire _requests_io_push_bits_index_T_9 = \|requests_io_push_bits_index_hi_2; // @[OneHot.scala:30:18, :32:14] wire [7:0] _requests_io_push_bits_index_T_10 = {2'h0, requests_io_push_bits_index_hi_2} \| requests_io_push_bits_index_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28] wire [3:0] requests_io_push_bits_index_hi_3 = _requests_io_push_bits_index_T_10[7:4]; // @[OneHot.scala:30:18, :32:28] wire [3:0] requests_io_push_bits_index_lo_3 = _requests_io_push_bits_index_T_10[3:0]; // @[OneHot.scala:31:18, :32:28] wire _requests_io_push_bits_index_T_11 = \|requests_io_push_bits_index_hi_3; // @[OneHot.scala:30:18, :32:14] wire [3:0] _requests_io_push_bits_index_T_12 = requests_io_push_bits_index_hi_3 \| requests_io_push_bits_index_lo_3; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] requests_io_push_bits_index_hi_4 = _requests_io_push_bits_index_T_12[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] requests_io_push_bits_index_lo_4 = _requests_io_push_bits_index_T_12[1:0]; // @[OneHot.scala:31:18, :32:28] wire _requests_io_push_bits_index_T_13 = \|requests_io_push_bits_index_hi_4; // @[OneHot.scala:30:18, :32:14] wire [1:0] _requests_io_push_bits_index_T_14 = requests_io_push_bits_index_hi_4 \| requests_io_push_bits_index_lo_4; // @[OneHot.scala:30:18, :31:18, :32:28] wire _requests_io_push_bits_index_T_15 = _requests_io_push_bits_index_T_14[1]; // @[OneHot.scala:32:28] wire [1:0] _requests_io_push_bits_index_T_16 = {_requests_io_push_bits_index_T_13, _requests_io_push_bits_index_T_15}; // @[OneHot.scala:32:{10,14}] wire [2:0] _requests_io_push_bits_index_T_17 = {_requests_io_push_bits_index_T_11, _requests_io_push_bits_index_T_16}; // @[OneHot.scala:32:{10,14}] wire [3:0] _requests_io_push_bits_index_T_18 = {_requests_io_push_bits_index_T_9, _requests_io_push_bits_index_T_17}; // @[OneHot.scala:32:{10,14}] wire [20:0] _requests_io_push_bits_index_T_19 = {lowerMatches1, 14'h0}; // @[Scheduler.scala:200:8, :276:30] wire [4:0] requests_io_push_bits_index_hi_5 = _requests_io_push_bits_index_T_19[20:16]; // @[OneHot.scala:30:18] wire [15:0] requests_io_push_bits_index_lo_5 = _requests_io_push_bits_index_T_19[15:0]; // @[OneHot.scala:31:18] wire _requests_io_push_bits_index_T_20 = \|requests_io_push_bits_index_hi_5; // @[OneHot.scala:30:18, :32:14] wire [15:0] _requests_io_push_bits_index_T_21 = {11'h0, requests_io_push_bits_index_hi_5} \| requests_io_push_bits_index_lo_5; // @[OneHot.scala:30:18, :31:18, :32:28] wire [7:0] requests_io_push_bits_index_hi_6 = _requests_io_push_bits_index_T_21[15:8]; // @[OneHot.scala:30:18, :32:28] wire [7:0] requests_io_push_bits_index_lo_6 = _requests_io_push_bits_index_T_21[7:0]; // @[OneHot.scala:31:18, :32:28] wire _requests_io_push_bits_index_T_22 = \|requests_io_push_bits_index_hi_6; // @[OneHot.scala:30:18, :32:14] wire [7:0] _requests_io_push_bits_index_T_23 = requests_io_push_bits_index_hi_6 \| requests_io_push_bits_index_lo_6; // @[OneHot.scala:30:18, :31:18, :32:28] wire [3:0] requests_io_push_bits_index_hi_7 = _requests_io_push_bits_index_T_23[7:4]; // @[OneHot.scala:30:18, :32:28] wire [3:0] requests_io_push_bits_index_lo_7 = _requests_io_push_bits_index_T_23[3:0]; // @[OneHot.scala:31:18, :32:28] wire _requests_io_push_bits_index_T_24 = \|requests_io_push_bits_index_hi_7; // @[OneHot.scala:30:18, :32:14] wire [3:0] _requests_io_push_bits_index_T_25 = requests_io_push_bits_index_hi_7 \| requests_io_push_bits_index_lo_7; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] requests_io_push_bits_index_hi_8 = _requests_io_push_bits_index_T_25[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] requests_io_push_bits_index_lo_8 = _requests_io_push_bits_index_T_25[1:0]; // @[OneHot.scala:31:18, :32:28] wire _requests_io_push_bits_index_T_26 = \|requests_io_push_bits_index_hi_8; // @[OneHot.scala:30:18, :32:14] wire [1:0] _requests_io_push_bits_index_T_27 = requests_io_push_bits_index_hi_8 \| requests_io_push_bits_index_lo_8; // @[OneHot.scala:30:18, :31:18, :32:28] wire _requests_io_push_bits_index_T_28 = _requests_io_push_bits_index_T_27[1]; // @[OneHot.scala:32:28] wire [1:0] _requests_io_push_bits_index_T_29 = {_requests_io_push_bits_index_T_26, _requests_io_push_bits_index_T_28}; // @[OneHot.scala:32:{10,14}] wire [2:0] _requests_io_push_bits_index_T_30 = {_requests_io_push_bits_index_T_24, _requests_io_push_bits_index_T_29}; // @[OneHot.scala:32:{10,14}] wire [3:0] _requests_io_push_bits_index_T_31 = {_requests_io_push_bits_index_T_22, _requests_io_push_bits_index_T_30}; // @[OneHot.scala:32:{10,14}] wire [4:0] _requests_io_push_bits_index_T_32 = {_requests_io_push_bits_index_T_20, _requests_io_push_bits_index_T_31}; // @[OneHot.scala:32:{10,14}] wire [2:0] _requests_io_push_bits_index_T_33 = request_bits_prio_0 ? _requests_io_push_bits_index_T_7 : 3'h0; // @[OneHot.scala:32:10] wire [4:0] _requests_io_push_bits_index_T_35 = request_bits_prio_2 ? _requests_io_push_bits_index_T_32 : 5'h0; // @[OneHot.scala:32:10] wire [3:0] _requests_io_push_bits_index_T_36 = {1'h0, _requests_io_push_bits_index_T_33}; // @[Mux.scala:30:73] wire [4:0] _requests_io_push_bits_index_T_37 = {1'h0, _requests_io_push_bits_index_T_36} \| _requests_io_push_bits_index_T_35; // @[Mux.scala:30:73] wire [4:0] _requests_io_push_bits_index_WIRE = _requests_io_push_bits_index_T_37; // @[Mux.scala:30:73] wire [6:0] _mshr_insertOH_T = ~mshr_validOH; // @[Scheduler.scala:252:25, :253:20, :278:32] wire [7:0] _mshr_insertOH_T_1 = {_mshr_insertOH_T, 1'h0}; // @[package.scala:253:48] wire [6:0] _mshr_insertOH_T_2 = _mshr_insertOH_T_1[6:0]; // @[package.scala:253:{48,53}] wire [6:0] _mshr_insertOH_T_3 = _mshr_insertOH_T \| _mshr_insertOH_T_2; // @[package.scala:253:{43,53}] wire [8:0] _mshr_insertOH_T_4 = {_mshr_insertOH_T_3, 2'h0}; // @[package.scala:253:{43,48}] wire [6:0] _mshr_insertOH_T_5 = _mshr_insertOH_T_4[6:0]; // @[package.scala:253:{48,53}] wire [6:0] _mshr_insertOH_T_6 = _mshr_insertOH_T_3 \| _mshr_insertOH_T_5; // @[package.scala:253:{43,53}] wire [10:0] _mshr_insertOH_T_7 = {_mshr_insertOH_T_6, 4'h0}; // @[package.scala:253:{43,48}] wire [6:0] _mshr_insertOH_T_8 = _mshr_insertOH_T_7[6:0]; // @[package.scala:253:{48,53}] wire [6:0] _mshr_insertOH_T_9 = _mshr_insertOH_T_6 \| _mshr_insertOH_T_8; // @[package.scala:253:{43,53}] wire [6:0] _mshr_insertOH_T_10 = _mshr_insertOH_T_9; // @[package.scala:253:43, :254:17] wire [7:0] _mshr_insertOH_T_11 = {_mshr_insertOH_T_10, 1'h0}; // @[package.scala:254:17] wire [7:0] _mshr_insertOH_T_12 = ~_mshr_insertOH_T_11; // @[Scheduler.scala:278:{23,47}] wire [6:0] _mshr_insertOH_T_13 = ~mshr_validOH; // @[Scheduler.scala:252:25, :253:20, :278:55] wire [7:0] _mshr_insertOH_T_14 = {1'h0, _mshr_insertOH_T_12[6:0] & _mshr_insertOH_T_13}; // @[Scheduler.scala:278:{23,53,55}] wire [7:0] mshr_insertOH = {1'h0, _mshr_insertOH_T_14[6:0] & prioFilter}; // @[Scheduler.scala:182:23, :278:{53,69}] wire _T_46 = request_valid & alloc; // @[Scheduler.scala:163:21, :173:15, :280:25] wire _T_25 = _T_46 & mshr_insertOH[0] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}] assign mshrs_0_io_allocate_bits_tag = _T_25 ? request_bits_tag : _view__T_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70] wire _T_29 = _T_46 & mshr_insertOH[1] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}] assign mshrs_1_io_allocate_bits_tag = _T_29 ? request_bits_tag : _view__T_1_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70] wire _T_33 = _T_46 & mshr_insertOH[2] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}] assign mshrs_2_io_allocate_bits_tag = _T_33 ? request_bits_tag : _view__T_2_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70] wire _T_37 = _T_46 & mshr_insertOH[3] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}] assign mshrs_3_io_allocate_bits_tag = _T_37 ? request_bits_tag : _view__T_3_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70] wire _T_41 = _T_46 & mshr_insertOH[4] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}] assign mshrs_4_io_allocate_bits_tag = _T_41 ? request_bits_tag : _view__T_4_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70] wire _T_45 = _T_46 & mshr_insertOH[5] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}] assign mshrs_5_io_allocate_bits_tag = _T_45 ? request_bits_tag : _view__T_5_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70, :287:131, :289:74] wire _T_65 = request_valid & nestC & ~_mshrs_6_io_status_valid & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:71:46, :163:21, :180:70, :193:33, :247:75, :258:16, :259:87, :295:{32,59}] wire _GEN_3 = _T_65 \| _T_46 & mshr_insertOH[6] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:193:33, :236:25, :247:75, :258:16, :278:69, :279:18, :280:{25,34,39,83}, :281:27, :295:{32,59,103}, :296:30] assign mshrs_6_io_allocate_bits_tag = _GEN_3 ? request_bits_tag : _view__T_6_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :236:25, :280:83, :281:27, :282:70, :295:103, :296:30, :297:73]
Generate the Verilog code corresponding to the following Chisel files. File Buffer.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.BufferParams class TLBufferNode ( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit valName: ValName) extends TLAdapterNode( clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) }, managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) } ) { override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}" override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none) } class TLBuffer( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters) extends LazyModule { def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace) def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde) def this()(implicit p: Parameters) = this(BufferParams.default) val node = new TLBufferNode(a, b, c, d, e) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def headBundle = node.out.head._2.bundle override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.a <> a(in .a) in .d <> d(out.d) if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) { in .b <> b(out.b) out.c <> c(in .c) out.e <> e(in .e) } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLBuffer { def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default) def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde) def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace) def apply( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters): TLNode = { val buffer = LazyModule(new TLBuffer(a, b, c, d, e)) buffer.node } def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = { val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) } name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } } buffers.map(_.node) } def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = { chain(depth, name) .reduceLeftOption(_ := _) .getOrElse(TLNameNode("no_buffer")) } } File Crossing.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.interrupts import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg} @deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2") class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val intnode = IntAdapterNode() lazy val module = new Impl class Impl extends LazyModuleImp(this) { (intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) => out := SynchronizerShiftReg(in, sync) } } } object IntSyncCrossingSource { def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) = { val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered)) intsource.node } } class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule { val node = IntSyncSourceNode(alreadyRegistered) lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl) class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := AsyncResetReg(Cat(in.reverse)).asBools } } class ImplRegistered extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}_Registered" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := in } } } object IntSyncCrossingSink { @deprecated("IntSyncCrossingSink which used the `sync` parameter to determine crossing type is deprecated. Use IntSyncAsyncCrossingSink, IntSyncRationalCrossingSink, or IntSyncSyncCrossingSink instead for > 1, 1, and 0 sync values respectively", "rocket-chip 1.2") def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncAsyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(sync) lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = s"IntSyncAsyncCrossingSink_n${node.out.size}x${node.out.head._1.size}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := SynchronizerShiftReg(in.sync, sync) } } } object IntSyncAsyncCrossingSink { def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncSyncCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(0) lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncSyncCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := in.sync } } } object IntSyncSyncCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncSyncCrossingSink()) intsink.node } } class IntSyncRationalCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(1) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncRationalCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := RegNext(in.sync) } } } object IntSyncRationalCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncRationalCrossingSink()) intsink.node } } File ClockDomain.scala: package freechips.rocketchip.prci import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ abstract class Domain(implicit p: Parameters) extends LazyModule with HasDomainCrossing { def clockBundle: ClockBundle lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { childClock := clockBundle.clock childReset := clockBundle.reset override def provideImplicitClockToLazyChildren = true // these are just for backwards compatibility with external devices // that were manually wiring themselves to the domain's clock/reset input: val clock = IO(Output(chiselTypeOf(clockBundle.clock))) val reset = IO(Output(chiselTypeOf(clockBundle.reset))) clock := clockBundle.clock reset := clockBundle.reset } } abstract class ClockDomain(implicit p: Parameters) extends Domain with HasClockDomainCrossing class ClockSinkDomain(val clockSinkParams: ClockSinkParameters)(implicit p: Parameters) extends ClockDomain { def this(take: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSinkParameters(take = take, name = name)) val clockNode = ClockSinkNode(Seq(clockSinkParams)) def clockBundle = clockNode.in.head._1 override lazy val desiredName = (clockSinkParams.name.toSeq :+ "ClockSinkDomain").mkString } class ClockSourceDomain(val clockSourceParams: ClockSourceParameters)(implicit p: Parameters) extends ClockDomain { def this(give: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSourceParameters(give = give, name = name)) val clockNode = ClockSourceNode(Seq(clockSourceParams)) def clockBundle = clockNode.out.head._1 override lazy val desiredName = (clockSourceParams.name.toSeq :+ "ClockSourceDomain").mkString } abstract class ResetDomain(implicit p: Parameters) extends Domain with HasResetDomainCrossing File HasTiles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.subsystem import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.bundlebridge._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.devices.debug.TLDebugModule import freechips.rocketchip.diplomacy.{DisableMonitors, FlipRendering} import freechips.rocketchip.interrupts.{IntXbar, IntSinkNode, IntSinkPortSimple, IntSyncAsyncCrossingSink} import freechips.rocketchip.tile.{MaxHartIdBits, BaseTile, InstantiableTileParams, TileParams, TilePRCIDomain, TraceBundle, PriorityMuxHartIdFromSeq} import freechips.rocketchip.tilelink.TLWidthWidget import freechips.rocketchip.prci.{ClockGroup, BundleBridgeBlockDuringReset, NoCrossing, SynchronousCrossing, CreditedCrossing, RationalCrossing, AsynchronousCrossing} import freechips.rocketchip.rocket.TracedInstruction import freechips.rocketchip.util.TraceCoreInterface import scala.collection.immutable.SortedMap /** Entry point for Config-uring the presence of Tiles / case class TilesLocated(loc: HierarchicalLocation) extends Field[Seq[CanAttachTile]](Nil) /* List of HierarchicalLocations which might contain a Tile / case object PossibleTileLocations extends Field[Seq[HierarchicalLocation]](Nil) /* For determining static tile id / case object NumTiles extends Field[Int](0) /* Whether to add timing-closure registers along the path of the hart id * as it propagates through the subsystem and into the tile. * * These are typically only desirable when a dynamically programmable prefix is being combined * with the static hart id via [[freechips.rocketchip.subsystem.HasTiles.tileHartIdNexusNode]]. / case object InsertTimingClosureRegistersOnHartIds extends Field[Boolean](false) /* Whether per-tile hart ids are going to be driven as inputs into a HasTiles block, * and if so, what their width should be. / case object HasTilesExternalHartIdWidthKey extends Field[Option[Int]](None) /* Whether per-tile reset vectors are going to be driven as inputs into a HasTiles block. * * Unlike the hart ids, the reset vector width is determined by the sinks within the tiles, * based on the size of the address map visible to the tiles. / case object HasTilesExternalResetVectorKey extends Field[Boolean](true) /* These are sources of "constants" that are driven into the tile. * * While they are not expected to change dyanmically while the tile is executing code, * they may be either tied to a contant value or programmed during boot or reset. * They need to be instantiated before tiles are attached within the subsystem containing them. / trait HasTileInputConstants { this: LazyModule with Attachable with InstantiatesHierarchicalElements => /* tileHartIdNode is used to collect publishers and subscribers of hartids. / val tileHartIdNodes: SortedMap[Int, BundleBridgeEphemeralNode[UInt]] = (0 until nTotalTiles).map { i => (i, BundleBridgeEphemeralNode[UInt]()) }.to(SortedMap) /* tileHartIdNexusNode is a BundleBridgeNexus that collects dynamic hart prefixes. * * Each "prefix" input is actually the same full width as the outer hart id; the expected usage * is that each prefix source would set only some non-overlapping portion of the bits to non-zero values. * This node orReduces them, and further combines the reduction with the static ids assigned to each tile, * producing a unique, dynamic hart id for each tile. * * If p(InsertTimingClosureRegistersOnHartIds) is set, the input and output values are registered. * * The output values are [[dontTouch]]'d to prevent constant propagation from pulling the values into * the tiles if they are constant, which would ruin deduplication of tiles that are otherwise homogeneous. / val tileHartIdNexusNode = LazyModule(new BundleBridgeNexus[UInt]( inputFn = BundleBridgeNexus.orReduction[UInt](registered = p(InsertTimingClosureRegistersOnHartIds)) _, outputFn = (prefix: UInt, n: Int) => Seq.tabulate(n) { i => val y = dontTouch(prefix \| totalTileIdList(i).U(p(MaxHartIdBits).W)) // dontTouch to keep constant prop from breaking tile dedup if (p(InsertTimingClosureRegistersOnHartIds)) BundleBridgeNexus.safeRegNext(y) else y }, default = Some(() => 0.U(p(MaxHartIdBits).W)), inputRequiresOutput = true, // guard against this being driven but then ignored in tileHartIdIONodes below shouldBeInlined = false // can't inline something whose output we are are dontTouching )).node // TODO: Replace the DebugModuleHartSelFuncs config key with logic to consume the dynamic hart IDs /* tileResetVectorNode is used to collect publishers and subscribers of tile reset vector addresses. / val tileResetVectorNodes: SortedMap[Int, BundleBridgeEphemeralNode[UInt]] = (0 until nTotalTiles).map { i => (i, BundleBridgeEphemeralNode[UInt]()) }.to(SortedMap) /* tileResetVectorNexusNode is a BundleBridgeNexus that accepts a single reset vector source, and broadcasts it to all tiles. / val tileResetVectorNexusNode = BundleBroadcast[UInt]( inputRequiresOutput = true // guard against this being driven but ignored in tileResetVectorIONodes below ) /* tileHartIdIONodes may generate subsystem IOs, one per tile, allowing the parent to assign unique hart ids. * * Or, if such IOs are not configured to exist, tileHartIdNexusNode is used to supply an id to each tile. / val tileHartIdIONodes: Seq[BundleBridgeSource[UInt]] = p(HasTilesExternalHartIdWidthKey) match { case Some(w) => (0 until nTotalTiles).map { i => val hartIdSource = BundleBridgeSource(() => UInt(w.W)) tileHartIdNodes(i) := hartIdSource hartIdSource } case None => { (0 until nTotalTiles).map { i => tileHartIdNodes(i) := tileHartIdNexusNode } Nil } } /** tileResetVectorIONodes may generate subsystem IOs, one per tile, allowing the parent to assign unique reset vectors. * * Or, if such IOs are not configured to exist, tileResetVectorNexusNode is used to supply a single reset vector to every tile. / val tileResetVectorIONodes: Seq[BundleBridgeSource[UInt]] = p(HasTilesExternalResetVectorKey) match { case true => (0 until nTotalTiles).map { i => val resetVectorSource = BundleBridgeSource[UInt]() tileResetVectorNodes(i) := resetVectorSource resetVectorSource } case false => { (0 until nTotalTiles).map { i => tileResetVectorNodes(i) := tileResetVectorNexusNode } Nil } } } /** These are sinks of notifications that are driven out from the tile. * * They need to be instantiated before tiles are attached to the subsystem containing them. / trait HasTileNotificationSinks { this: LazyModule => val tileHaltXbarNode = IntXbar() val tileHaltSinkNode = IntSinkNode(IntSinkPortSimple()) tileHaltSinkNode := tileHaltXbarNode val tileWFIXbarNode = IntXbar() val tileWFISinkNode = IntSinkNode(IntSinkPortSimple()) tileWFISinkNode := tileWFIXbarNode val tileCeaseXbarNode = IntXbar() val tileCeaseSinkNode = IntSinkNode(IntSinkPortSimple()) tileCeaseSinkNode := tileCeaseXbarNode } /* Standardized interface by which parameterized tiles can be attached to contexts containing interconnect resources. * * Sub-classes of this trait can optionally override the individual connect functions in order to specialize * their attachment behaviors, but most use cases should be be handled simply by changing the implementation * of the injectNode functions in crossingParams. / trait CanAttachTile { type TileType <: BaseTile type TileContextType <: DefaultHierarchicalElementContextType def tileParams: InstantiableTileParams[TileType] def crossingParams: HierarchicalElementCrossingParamsLike /* Narrow waist through which all tiles are intended to pass while being instantiated. / def instantiate(allTileParams: Seq[TileParams], instantiatedTiles: SortedMap[Int, TilePRCIDomain[_]])(implicit p: Parameters): TilePRCIDomain[TileType] = { val clockSinkParams = tileParams.clockSinkParams.copy(name = Some(tileParams.uniqueName)) val tile_prci_domain = LazyModule(new TilePRCIDomain[TileType](clockSinkParams, crossingParams) { self => val element = self.element_reset_domain { LazyModule(tileParams.instantiate(crossingParams, PriorityMuxHartIdFromSeq(allTileParams))) } }) tile_prci_domain } /* A default set of connections that need to occur for most tile types / def connect(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = { connectMasterPorts(domain, context) connectSlavePorts(domain, context) connectInterrupts(domain, context) connectPRC(domain, context) connectOutputNotifications(domain, context) connectInputConstants(domain, context) connectTrace(domain, context) } /* Connect the port where the tile is the master to a TileLink interconnect. / def connectMasterPorts(domain: TilePRCIDomain[TileType], context: Attachable): Unit = { implicit val p = context.p val dataBus = context.locateTLBusWrapper(crossingParams.master.where) dataBus.coupleFrom(tileParams.baseName) { bus => bus := crossingParams.master.injectNode(context) :=* domain.crossMasterPort(crossingParams.crossingType) } } /** Connect the port where the tile is the slave to a TileLink interconnect. / def connectSlavePorts(domain: TilePRCIDomain[TileType], context: Attachable): Unit = { implicit val p = context.p DisableMonitors { implicit p => val controlBus = context.locateTLBusWrapper(crossingParams.slave.where) controlBus.coupleTo(tileParams.baseName) { bus => domain.crossSlavePort(crossingParams.crossingType) := crossingParams.slave.injectNode(context) := TLWidthWidget(controlBus.beatBytes) := bus } } } /** Connect the various interrupts sent to and and raised by the tile. / def connectInterrupts(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = { implicit val p = context.p // NOTE: The order of calls to := matters! They must match how interrupts // are decoded from tile.intInwardNode inside the tile. For this reason, // we stub out missing interrupts with constant sources here. // 1. Debug interrupt is definitely asynchronous in all cases. domain.element.intInwardNode := domain { IntSyncAsyncCrossingSink(3) } := context.debugNodes(domain.element.tileId) // 2. The CLINT and PLIC output interrupts are synchronous to the CLINT/PLIC respectively, // so might need to be synchronized depending on the Tile's crossing type. // From CLINT: "msip" and "mtip" context.msipDomain { domain.crossIntIn(crossingParams.crossingType, domain.element.intInwardNode) := context.msipNodes(domain.element.tileId) } // From PLIC: "meip" context.meipDomain { domain.crossIntIn(crossingParams.crossingType, domain.element.intInwardNode) := context.meipNodes(domain.element.tileId) } // From PLIC: "seip" (only if supervisor mode is enabled) if (domain.element.tileParams.core.hasSupervisorMode) { context.seipDomain { domain.crossIntIn(crossingParams.crossingType, domain.element.intInwardNode) := context.seipNodes(domain.element.tileId) } } // 3. Local Interrupts ("lip") are required to already be synchronous to the Tile's clock. // (they are connected to domain.element.intInwardNode in a seperate trait) // 4. Interrupts coming out of the tile are sent to the PLIC, // so might need to be synchronized depending on the Tile's crossing type. context.tileToPlicNodes.get(domain.element.tileId).foreach { node => FlipRendering { implicit p => domain.element.intOutwardNode.foreach { out => context.toPlicDomain { node := domain.crossIntOut(crossingParams.crossingType, out) } }} } // 5. Connect NMI inputs to the tile. These inputs are synchronous to the respective core_clock. domain.element.nmiNode.foreach(_ := context.nmiNodes(domain.element.tileId)) } /* Notifications of tile status are connected to be broadcast without needing to be clock-crossed. / def connectOutputNotifications(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = { implicit val p = context.p domain { context.tileHaltXbarNode := domain.crossIntOut(NoCrossing, domain.element.haltNode) context.tileWFIXbarNode :=* domain.crossIntOut(NoCrossing, domain.element.wfiNode) context.tileCeaseXbarNode :=* domain.crossIntOut(NoCrossing, domain.element.ceaseNode) } // TODO should context be forced to have a trace sink connected here? // for now this just ensures domain.trace[Core]Node has been crossed without connecting it externally } /** Connect inputs to the tile that are assumed to be constant during normal operation, and so are not clock-crossed. / def connectInputConstants(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = { implicit val p = context.p val tlBusToGetPrefixFrom = context.locateTLBusWrapper(crossingParams.mmioBaseAddressPrefixWhere) domain.element.hartIdNode := context.tileHartIdNodes(domain.element.tileId) domain.element.resetVectorNode := context.tileResetVectorNodes(domain.element.tileId) tlBusToGetPrefixFrom.prefixNode.foreach { domain.element.mmioAddressPrefixNode := _ } } /* Connect power/reset/clock resources. / def connectPRC(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = { implicit val p = context.p val tlBusToGetClockDriverFrom = context.locateTLBusWrapper(crossingParams.master.where) (crossingParams.crossingType match { case _: SynchronousCrossing \| _: CreditedCrossing => if (crossingParams.forceSeparateClockReset) { domain.clockNode := tlBusToGetClockDriverFrom.clockNode } else { domain.clockNode := tlBusToGetClockDriverFrom.fixedClockNode } case _: RationalCrossing => domain.clockNode := tlBusToGetClockDriverFrom.clockNode case _: AsynchronousCrossing => { val tileClockGroup = ClockGroup() tileClockGroup := context.allClockGroupsNode domain.clockNode := tileClockGroup } }) domain { domain.element_reset_domain.clockNode := crossingParams.resetCrossingType.injectClockNode := domain.clockNode } } /* Function to handle all trace crossings when tile is instantiated inside domains / def connectTrace(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = { implicit val p = context.p val traceCrossingNode = BundleBridgeBlockDuringReset[TraceBundle]( resetCrossingType = crossingParams.resetCrossingType) context.traceNodes(domain.element.tileId) := traceCrossingNode := domain.element.traceNode val traceCoreCrossingNode = BundleBridgeBlockDuringReset[TraceCoreInterface]( resetCrossingType = crossingParams.resetCrossingType) context.traceCoreNodes(domain.element.tileId) := traceCoreCrossingNode := domain.element.traceCoreNode } } case class CloneTileAttachParams( sourceTileId: Int, cloneParams: CanAttachTile ) extends CanAttachTile { type TileType = cloneParams.TileType type TileContextType = cloneParams.TileContextType def tileParams = cloneParams.tileParams def crossingParams = cloneParams.crossingParams override def instantiate(allTileParams: Seq[TileParams], instantiatedTiles: SortedMap[Int, TilePRCIDomain[_]])(implicit p: Parameters): TilePRCIDomain[TileType] = { require(instantiatedTiles.contains(sourceTileId)) val clockSinkParams = tileParams.clockSinkParams.copy(name = Some(tileParams.uniqueName)) val tile_prci_domain = CloneLazyModule( new TilePRCIDomain[TileType](clockSinkParams, crossingParams) { self => val element = self.element_reset_domain { LazyModule(tileParams.instantiate(crossingParams, PriorityMuxHartIdFromSeq(allTileParams))) } }, instantiatedTiles(sourceTileId).asInstanceOf[TilePRCIDomain[TileType]] ) tile_prci_domain } } File ClockGroup.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.prci import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.resources.FixedClockResource case class ClockGroupingNode(groupName: String)(implicit valName: ValName) extends MixedNexusNode(ClockGroupImp, ClockImp)( dFn = { _ => ClockSourceParameters() }, uFn = { seq => ClockGroupSinkParameters(name = groupName, members = seq) }) { override def circuitIdentity = outputs.size == 1 } class ClockGroup(groupName: String)(implicit p: Parameters) extends LazyModule { val node = ClockGroupingNode(groupName) lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { val (in, _) = node.in(0) val (out, _) = node.out.unzip require (node.in.size == 1) require (in.member.size == out.size) (in.member.data zip out) foreach { case (i, o) => o := i } } } object ClockGroup { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ClockGroup(valName.name)).node } case class ClockGroupAggregateNode(groupName: String)(implicit valName: ValName) extends NexusNode(ClockGroupImp)( dFn = { _ => ClockGroupSourceParameters() }, uFn = { seq => ClockGroupSinkParameters(name = groupName, members = seq.flatMap(_.members))}) { override def circuitIdentity = outputs.size == 1 } class ClockGroupAggregator(groupName: String)(implicit p: Parameters) extends LazyModule { val node = ClockGroupAggregateNode(groupName) override lazy val desiredName = s"ClockGroupAggregator_$groupName" lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { val (in, _) = node.in.unzip val (out, _) = node.out.unzip val outputs = out.flatMap(_.member.data) require (node.in.size == 1, s"Aggregator for groupName: ${groupName} had ${node.in.size} inward edges instead of 1") require (in.head.member.size == outputs.size) in.head.member.data.zip(outputs).foreach { case (i, o) => o := i } } } object ClockGroupAggregator { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ClockGroupAggregator(valName.name)).node } class SimpleClockGroupSource(numSources: Int = 1)(implicit p: Parameters) extends LazyModule { val node = ClockGroupSourceNode(List.fill(numSources) { ClockGroupSourceParameters() }) lazy val module = new Impl class Impl extends LazyModuleImp(this) { val (out, _) = node.out.unzip out.map { out: ClockGroupBundle => out.member.data.foreach { o => o.clock := clock; o.reset := reset } } } } object SimpleClockGroupSource { def apply(num: Int = 1)(implicit p: Parameters, valName: ValName) = LazyModule(new SimpleClockGroupSource(num)).node } case class FixedClockBroadcastNode(fixedClockOpt: Option[ClockParameters])(implicit valName: ValName) extends NexusNode(ClockImp)( dFn = { seq => fixedClockOpt.map(_ => ClockSourceParameters(give = fixedClockOpt)).orElse(seq.headOption).getOrElse(ClockSourceParameters()) }, uFn = { seq => fixedClockOpt.map(_ => ClockSinkParameters(take = fixedClockOpt)).orElse(seq.headOption).getOrElse(ClockSinkParameters()) }, inputRequiresOutput = false) { def fixedClockResources(name: String, prefix: String = "soc/"): Seq[Option[FixedClockResource]] = Seq(fixedClockOpt.map(t => new FixedClockResource(name, t.freqMHz, prefix))) } class FixedClockBroadcast(fixedClockOpt: Option[ClockParameters])(implicit p: Parameters) extends LazyModule { val node = new FixedClockBroadcastNode(fixedClockOpt) { override def circuitIdentity = outputs.size == 1 } lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { val (in, _) = node.in(0) val (out, _) = node.out.unzip override def desiredName = s"FixedClockBroadcast_${out.size}" require (node.in.size == 1, "FixedClockBroadcast can only broadcast a single clock") out.foreach { _ := in } } } object FixedClockBroadcast { def apply(fixedClockOpt: Option[ClockParameters] = None)(implicit p: Parameters, valName: ValName) = LazyModule(new FixedClockBroadcast(fixedClockOpt)).node } case class PRCIClockGroupNode()(implicit valName: ValName) extends NexusNode(ClockGroupImp)( dFn = { _ => ClockGroupSourceParameters() }, uFn = { _ => ClockGroupSinkParameters("prci", Nil) }, outputRequiresInput = false) File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } }	module TilePRCIDomain_7( // @[ClockDomain.scala:14:9] output auto_intsink_out_1_0, // @[LazyModuleImp.scala:107:25] input auto_intsink_in_sync_0, // @[LazyModuleImp.scala:107:25] output auto_element_reset_domain_rockettile_trace_source_out_insns_0_valid, // @[LazyModuleImp.scala:107:25] output [39:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_iaddr, // @[LazyModuleImp.scala:107:25] output [31:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_insn, // @[LazyModuleImp.scala:107:25] output [2:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_priv, // @[LazyModuleImp.scala:107:25] output auto_element_reset_domain_rockettile_trace_source_out_insns_0_exception, // @[LazyModuleImp.scala:107:25] output auto_element_reset_domain_rockettile_trace_source_out_insns_0_interrupt, // @[LazyModuleImp.scala:107:25] output [63:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_cause, // @[LazyModuleImp.scala:107:25] output [39:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_tval, // @[LazyModuleImp.scala:107:25] output [63:0] auto_element_reset_domain_rockettile_trace_source_out_time, // @[LazyModuleImp.scala:107:25] input [2:0] auto_element_reset_domain_rockettile_hartid_in, // @[LazyModuleImp.scala:107:25] input auto_int_in_clock_xing_in_2_sync_0, // @[LazyModuleImp.scala:107:25] input auto_int_in_clock_xing_in_1_sync_0, // @[LazyModuleImp.scala:107:25] input auto_int_in_clock_xing_in_0_sync_0, // @[LazyModuleImp.scala:107:25] input auto_int_in_clock_xing_in_0_sync_1, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_master_clock_xing_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_master_clock_xing_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_tl_master_clock_xing_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_tl_master_clock_xing_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_tl_master_clock_xing_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_tl_master_clock_xing_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_tl_master_clock_xing_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_b_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_master_clock_xing_out_b_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_tl_master_clock_xing_out_b_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_tl_master_clock_xing_out_b_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_tl_master_clock_xing_out_b_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_tl_master_clock_xing_out_b_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_tl_master_clock_xing_out_b_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_tl_master_clock_xing_out_b_bits_data, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_b_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_c_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_master_clock_xing_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_master_clock_xing_out_c_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_tl_master_clock_xing_out_c_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_tl_master_clock_xing_out_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_tl_master_clock_xing_out_c_bits_address, // @[LazyModuleImp.scala:107:25] output [63:0] auto_tl_master_clock_xing_out_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_master_clock_xing_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_tl_master_clock_xing_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_tl_master_clock_xing_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_tl_master_clock_xing_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_master_clock_xing_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_tl_master_clock_xing_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_e_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_e_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_master_clock_xing_out_e_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_tap_clock_in_clock, // @[LazyModuleImp.scala:107:25] input auto_tap_clock_in_reset // @[LazyModuleImp.scala:107:25] ); wire clockNode_auto_anon_in_reset; // @[ClockGroup.scala:104:9] wire clockNode_auto_anon_in_clock; // @[ClockGroup.scala:104:9] wire element_reset_domain_auto_clock_in_reset; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_clock_in_clock; // @[ClockDomain.scala:14:9] wire auto_intsink_in_sync_0_0 = auto_intsink_in_sync_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_element_reset_domain_rockettile_hartid_in_0 = auto_element_reset_domain_rockettile_hartid_in; // @[ClockDomain.scala:14:9] wire auto_int_in_clock_xing_in_2_sync_0_0 = auto_int_in_clock_xing_in_2_sync_0; // @[ClockDomain.scala:14:9] wire auto_int_in_clock_xing_in_1_sync_0_0 = auto_int_in_clock_xing_in_1_sync_0; // @[ClockDomain.scala:14:9] wire auto_int_in_clock_xing_in_0_sync_0_0 = auto_int_in_clock_xing_in_0_sync_0; // @[ClockDomain.scala:14:9] wire auto_int_in_clock_xing_in_0_sync_1_0 = auto_int_in_clock_xing_in_0_sync_1; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_a_ready_0 = auto_tl_master_clock_xing_out_a_ready; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_b_valid_0 = auto_tl_master_clock_xing_out_b_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_b_bits_opcode_0 = auto_tl_master_clock_xing_out_b_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_tl_master_clock_xing_out_b_bits_param_0 = auto_tl_master_clock_xing_out_b_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] auto_tl_master_clock_xing_out_b_bits_size_0 = auto_tl_master_clock_xing_out_b_bits_size; // @[ClockDomain.scala:14:9] wire [1:0] auto_tl_master_clock_xing_out_b_bits_source_0 = auto_tl_master_clock_xing_out_b_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] auto_tl_master_clock_xing_out_b_bits_address_0 = auto_tl_master_clock_xing_out_b_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] auto_tl_master_clock_xing_out_b_bits_mask_0 = auto_tl_master_clock_xing_out_b_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] auto_tl_master_clock_xing_out_b_bits_data_0 = auto_tl_master_clock_xing_out_b_bits_data; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_b_bits_corrupt_0 = auto_tl_master_clock_xing_out_b_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_c_ready_0 = auto_tl_master_clock_xing_out_c_ready; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_d_valid_0 = auto_tl_master_clock_xing_out_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_d_bits_opcode_0 = auto_tl_master_clock_xing_out_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_tl_master_clock_xing_out_d_bits_param_0 = auto_tl_master_clock_xing_out_d_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] auto_tl_master_clock_xing_out_d_bits_size_0 = auto_tl_master_clock_xing_out_d_bits_size; // @[ClockDomain.scala:14:9] wire [1:0] auto_tl_master_clock_xing_out_d_bits_source_0 = auto_tl_master_clock_xing_out_d_bits_source; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_d_bits_sink_0 = auto_tl_master_clock_xing_out_d_bits_sink; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_d_bits_denied_0 = auto_tl_master_clock_xing_out_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] auto_tl_master_clock_xing_out_d_bits_data_0 = auto_tl_master_clock_xing_out_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_d_bits_corrupt_0 = auto_tl_master_clock_xing_out_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_e_ready_0 = auto_tl_master_clock_xing_out_e_ready; // @[ClockDomain.scala:14:9] wire auto_tap_clock_in_clock_0 = auto_tap_clock_in_clock; // @[ClockDomain.scala:14:9] wire auto_tap_clock_in_reset_0 = auto_tap_clock_in_reset; // @[ClockDomain.scala:14:9] wire [31:0] auto_element_reset_domain_rockettile_trace_core_source_out_group_0_iaddr = 32'h0; // @[ClockDomain.scala:14:9] wire [31:0] auto_element_reset_domain_rockettile_trace_core_source_out_tval = 32'h0; // @[ClockDomain.scala:14:9] wire [31:0] auto_element_reset_domain_rockettile_trace_core_source_out_cause = 32'h0; // @[ClockDomain.scala:14:9] wire [31:0] element_reset_domain_auto_rockettile_trace_core_source_out_group_0_iaddr = 32'h0; // @[ClockDomain.scala:14:9] wire [31:0] element_reset_domain_auto_rockettile_trace_core_source_out_tval = 32'h0; // @[ClockDomain.scala:14:9] wire [31:0] element_reset_domain_auto_rockettile_trace_core_source_out_cause = 32'h0; // @[ClockDomain.scala:14:9] wire [3:0] auto_element_reset_domain_rockettile_trace_core_source_out_group_0_itype = 4'h0; // @[ClockDomain.scala:14:9] wire [3:0] auto_element_reset_domain_rockettile_trace_core_source_out_priv = 4'h0; // @[ClockDomain.scala:14:9] wire [3:0] element_reset_domain_auto_rockettile_trace_core_source_out_group_0_itype = 4'h0; // @[ClockDomain.scala:14:9] wire [3:0] element_reset_domain_auto_rockettile_trace_core_source_out_priv = 4'h0; // @[ClockDomain.scala:14:9] wire [31:0] auto_element_reset_domain_rockettile_reset_vector_in = 32'h10000; // @[ClockDomain.scala:14:9] wire [31:0] element_reset_domain_auto_rockettile_reset_vector_in = 32'h10000; // @[ClockDomain.scala:14:9] wire auto_intsink_out_2_0 = 1'h0; // @[ClockDomain.scala:14:9] wire auto_intsink_out_0_0 = 1'h0; // @[ClockDomain.scala:14:9] wire auto_element_reset_domain_rockettile_trace_core_source_out_group_0_iretire = 1'h0; // @[ClockDomain.scala:14:9] wire auto_element_reset_domain_rockettile_trace_core_source_out_group_0_ilastsize = 1'h0; // @[ClockDomain.scala:14:9] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire element_reset_domain_auto_rockettile_buffer_out_a_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_c_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_cease_out_0 = 1'h0; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_halt_out_0 = 1'h0; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_trace_core_source_out_group_0_iretire = 1'h0; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_trace_core_source_out_group_0_ilastsize = 1'h0; // @[ClockDomain.scala:14:9] wire element_reset_domain__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire clockNode_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire clockNode_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire clockNode__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire intOutClockXingOut_sync_0 = 1'h0; // @[MixedNode.scala:542:17] wire intOutClockXingIn_sync_0 = 1'h0; // @[MixedNode.scala:551:17] wire intOutClockXingOut_1_sync_0 = 1'h0; // @[MixedNode.scala:542:17] wire intOutClockXingIn_1_sync_0 = 1'h0; // @[MixedNode.scala:551:17] wire intOutClockXingOut_4_sync_0 = 1'h0; // @[MixedNode.scala:542:17] wire intOutClockXingIn_4_sync_0 = 1'h0; // @[MixedNode.scala:551:17] wire intOutClockXingOut_5_sync_0 = 1'h0; // @[MixedNode.scala:542:17] wire intOutClockXingIn_5_sync_0 = 1'h0; // @[MixedNode.scala:551:17] wire element_reset_domain_auto_rockettile_trace_source_out_insns_0_valid; // @[ClockDomain.scala:14:9] wire [39:0] element_reset_domain_auto_rockettile_trace_source_out_insns_0_iaddr; // @[ClockDomain.scala:14:9] wire [31:0] element_reset_domain_auto_rockettile_trace_source_out_insns_0_insn; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_trace_source_out_insns_0_priv; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_trace_source_out_insns_0_exception; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_trace_source_out_insns_0_interrupt; // @[ClockDomain.scala:14:9] wire [63:0] element_reset_domain_auto_rockettile_trace_source_out_insns_0_cause; // @[ClockDomain.scala:14:9] wire [39:0] element_reset_domain_auto_rockettile_trace_source_out_insns_0_tval; // @[ClockDomain.scala:14:9] wire [63:0] element_reset_domain_auto_rockettile_trace_source_out_time; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_hartid_in = auto_element_reset_domain_rockettile_hartid_in_0; // @[ClockDomain.scala:14:9] wire intInClockXingIn_2_sync_0 = auto_int_in_clock_xing_in_2_sync_0_0; // @[ClockDomain.scala:14:9] wire intInClockXingIn_1_sync_0 = auto_int_in_clock_xing_in_1_sync_0_0; // @[ClockDomain.scala:14:9] wire intInClockXingIn_sync_0 = auto_int_in_clock_xing_in_0_sync_0_0; // @[ClockDomain.scala:14:9] wire intInClockXingIn_sync_1 = auto_int_in_clock_xing_in_0_sync_1_0; // @[ClockDomain.scala:14:9] wire tlMasterClockXingOut_a_ready = auto_tl_master_clock_xing_out_a_ready_0; // @[ClockDomain.scala:14:9] wire tlMasterClockXingOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] tlMasterClockXingOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] tlMasterClockXingOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] tlMasterClockXingOut_a_bits_size; // @[MixedNode.scala:542:17] wire [1:0] tlMasterClockXingOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] tlMasterClockXingOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] tlMasterClockXingOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] tlMasterClockXingOut_a_bits_data; // @[MixedNode.scala:542:17] wire tlMasterClockXingOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire tlMasterClockXingOut_b_ready; // @[MixedNode.scala:542:17] wire tlMasterClockXingOut_b_valid = auto_tl_master_clock_xing_out_b_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] tlMasterClockXingOut_b_bits_opcode = auto_tl_master_clock_xing_out_b_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] tlMasterClockXingOut_b_bits_param = auto_tl_master_clock_xing_out_b_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] tlMasterClockXingOut_b_bits_size = auto_tl_master_clock_xing_out_b_bits_size_0; // @[ClockDomain.scala:14:9] wire [1:0] tlMasterClockXingOut_b_bits_source = auto_tl_master_clock_xing_out_b_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] tlMasterClockXingOut_b_bits_address = auto_tl_master_clock_xing_out_b_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] tlMasterClockXingOut_b_bits_mask = auto_tl_master_clock_xing_out_b_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] tlMasterClockXingOut_b_bits_data = auto_tl_master_clock_xing_out_b_bits_data_0; // @[ClockDomain.scala:14:9] wire tlMasterClockXingOut_b_bits_corrupt = auto_tl_master_clock_xing_out_b_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire tlMasterClockXingOut_c_ready = auto_tl_master_clock_xing_out_c_ready_0; // @[ClockDomain.scala:14:9] wire tlMasterClockXingOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] tlMasterClockXingOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] tlMasterClockXingOut_c_bits_param; // @[MixedNode.scala:542:17] wire [3:0] tlMasterClockXingOut_c_bits_size; // @[MixedNode.scala:542:17] wire [1:0] tlMasterClockXingOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] tlMasterClockXingOut_c_bits_address; // @[MixedNode.scala:542:17] wire [63:0] tlMasterClockXingOut_c_bits_data; // @[MixedNode.scala:542:17] wire tlMasterClockXingOut_c_bits_corrupt; // @[MixedNode.scala:542:17] wire tlMasterClockXingOut_d_ready; // @[MixedNode.scala:542:17] wire tlMasterClockXingOut_d_valid = auto_tl_master_clock_xing_out_d_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] tlMasterClockXingOut_d_bits_opcode = auto_tl_master_clock_xing_out_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] tlMasterClockXingOut_d_bits_param = auto_tl_master_clock_xing_out_d_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] tlMasterClockXingOut_d_bits_size = auto_tl_master_clock_xing_out_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [1:0] tlMasterClockXingOut_d_bits_source = auto_tl_master_clock_xing_out_d_bits_source_0; // @[ClockDomain.scala:14:9] wire [2:0] tlMasterClockXingOut_d_bits_sink = auto_tl_master_clock_xing_out_d_bits_sink_0; // @[ClockDomain.scala:14:9] wire tlMasterClockXingOut_d_bits_denied = auto_tl_master_clock_xing_out_d_bits_denied_0; // @[ClockDomain.scala:14:9] wire [63:0] tlMasterClockXingOut_d_bits_data = auto_tl_master_clock_xing_out_d_bits_data_0; // @[ClockDomain.scala:14:9] wire tlMasterClockXingOut_d_bits_corrupt = auto_tl_master_clock_xing_out_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire tlMasterClockXingOut_e_ready = auto_tl_master_clock_xing_out_e_ready_0; // @[ClockDomain.scala:14:9] wire tlMasterClockXingOut_e_valid; // @[MixedNode.scala:542:17] wire [2:0] tlMasterClockXingOut_e_bits_sink; // @[MixedNode.scala:542:17] wire tapClockNodeIn_clock = auto_tap_clock_in_clock_0; // @[ClockDomain.scala:14:9] wire tapClockNodeIn_reset = auto_tap_clock_in_reset_0; // @[ClockDomain.scala:14:9] wire auto_intsink_out_1_0_0; // @[ClockDomain.scala:14:9] wire auto_element_reset_domain_rockettile_trace_source_out_insns_0_valid_0; // @[ClockDomain.scala:14:9] wire [39:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_iaddr_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_insn_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_priv_0; // @[ClockDomain.scala:14:9] wire auto_element_reset_domain_rockettile_trace_source_out_insns_0_exception_0; // @[ClockDomain.scala:14:9] wire auto_element_reset_domain_rockettile_trace_source_out_insns_0_interrupt_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_cause_0; // @[ClockDomain.scala:14:9] wire [39:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_tval_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_element_reset_domain_rockettile_trace_source_out_time_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_tl_master_clock_xing_out_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_tl_master_clock_xing_out_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_tl_master_clock_xing_out_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_tl_master_clock_xing_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_tl_master_clock_xing_out_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_b_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_c_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_c_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_tl_master_clock_xing_out_c_bits_size_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_tl_master_clock_xing_out_c_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_tl_master_clock_xing_out_c_bits_address_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_tl_master_clock_xing_out_c_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_c_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_c_valid_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_d_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_e_bits_sink_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_e_valid_0; // @[ClockDomain.scala:14:9] wire childClock; // @[LazyModuleImp.scala:155:31] wire childReset; // @[LazyModuleImp.scala:158:31] assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_valid_0 = element_reset_domain_auto_rockettile_trace_source_out_insns_0_valid; // @[ClockDomain.scala:14:9] assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_iaddr_0 = element_reset_domain_auto_rockettile_trace_source_out_insns_0_iaddr; // @[ClockDomain.scala:14:9] assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_insn_0 = element_reset_domain_auto_rockettile_trace_source_out_insns_0_insn; // @[ClockDomain.scala:14:9] assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_priv_0 = element_reset_domain_auto_rockettile_trace_source_out_insns_0_priv; // @[ClockDomain.scala:14:9] assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_exception_0 = element_reset_domain_auto_rockettile_trace_source_out_insns_0_exception; // @[ClockDomain.scala:14:9] assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_interrupt_0 = element_reset_domain_auto_rockettile_trace_source_out_insns_0_interrupt; // @[ClockDomain.scala:14:9] assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_cause_0 = element_reset_domain_auto_rockettile_trace_source_out_insns_0_cause; // @[ClockDomain.scala:14:9] assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_tval_0 = element_reset_domain_auto_rockettile_trace_source_out_insns_0_tval; // @[ClockDomain.scala:14:9] assign auto_element_reset_domain_rockettile_trace_source_out_time_0 = element_reset_domain_auto_rockettile_trace_source_out_time; // @[ClockDomain.scala:14:9] wire clockNode_auto_anon_out_clock; // @[ClockGroup.scala:104:9] wire element_reset_domain_clockNodeIn_clock = element_reset_domain_auto_clock_in_clock; // @[ClockDomain.scala:14:9] wire clockNode_auto_anon_out_reset; // @[ClockGroup.scala:104:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_a_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] element_reset_domain_auto_rockettile_buffer_out_a_bits_size; // @[ClockDomain.scala:14:9] wire [1:0] element_reset_domain_auto_rockettile_buffer_out_a_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] element_reset_domain_auto_rockettile_buffer_out_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] element_reset_domain_auto_rockettile_buffer_out_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] element_reset_domain_auto_rockettile_buffer_out_a_bits_data; // @[ClockDomain.scala:14:9] wire element_reset_domain_clockNodeIn_reset = element_reset_domain_auto_clock_in_reset; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_a_ready; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_b_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] element_reset_domain_auto_rockettile_buffer_out_b_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] element_reset_domain_auto_rockettile_buffer_out_b_bits_size; // @[ClockDomain.scala:14:9] wire [1:0] element_reset_domain_auto_rockettile_buffer_out_b_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] element_reset_domain_auto_rockettile_buffer_out_b_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] element_reset_domain_auto_rockettile_buffer_out_b_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] element_reset_domain_auto_rockettile_buffer_out_b_bits_data; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_b_bits_corrupt; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_b_ready; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_b_valid; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_c_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_c_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] element_reset_domain_auto_rockettile_buffer_out_c_bits_size; // @[ClockDomain.scala:14:9] wire [1:0] element_reset_domain_auto_rockettile_buffer_out_c_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] element_reset_domain_auto_rockettile_buffer_out_c_bits_address; // @[ClockDomain.scala:14:9] wire [63:0] element_reset_domain_auto_rockettile_buffer_out_c_bits_data; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_c_ready; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_c_valid; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] element_reset_domain_auto_rockettile_buffer_out_d_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] element_reset_domain_auto_rockettile_buffer_out_d_bits_size; // @[ClockDomain.scala:14:9] wire [1:0] element_reset_domain_auto_rockettile_buffer_out_d_bits_source; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_d_bits_sink; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] element_reset_domain_auto_rockettile_buffer_out_d_bits_data; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_d_ready; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_e_bits_sink; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_e_ready; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_e_valid; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_wfi_out_0; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_int_local_in_3_0; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_int_local_in_2_0; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_int_local_in_1_0; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_int_local_in_1_1; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_int_local_in_0_0; // @[ClockDomain.scala:14:9] wire element_reset_domain_childClock; // @[LazyModuleImp.scala:155:31] wire element_reset_domain_childReset; // @[LazyModuleImp.scala:158:31] assign element_reset_domain_childClock = element_reset_domain_clockNodeIn_clock; // @[MixedNode.scala:551:17] assign element_reset_domain_childReset = element_reset_domain_clockNodeIn_reset; // @[MixedNode.scala:551:17] wire tapClockNodeOut_clock; // @[MixedNode.scala:542:17] wire clockNode_anonIn_clock = clockNode_auto_anon_in_clock; // @[ClockGroup.scala:104:9] wire tapClockNodeOut_reset; // @[MixedNode.scala:542:17] wire clockNode_anonOut_clock; // @[MixedNode.scala:542:17] wire clockNode_anonIn_reset = clockNode_auto_anon_in_reset; // @[ClockGroup.scala:104:9] assign element_reset_domain_auto_clock_in_clock = clockNode_auto_anon_out_clock; // @[ClockGroup.scala:104:9] wire clockNode_anonOut_reset; // @[MixedNode.scala:542:17] assign element_reset_domain_auto_clock_in_reset = clockNode_auto_anon_out_reset; // @[ClockGroup.scala:104:9] assign clockNode_auto_anon_out_clock = clockNode_anonOut_clock; // @[ClockGroup.scala:104:9] assign clockNode_auto_anon_out_reset = clockNode_anonOut_reset; // @[ClockGroup.scala:104:9] assign clockNode_anonOut_clock = clockNode_anonIn_clock; // @[MixedNode.scala:542:17, :551:17] assign clockNode_anonOut_reset = clockNode_anonIn_reset; // @[MixedNode.scala:542:17, :551:17] assign clockNode_auto_anon_in_clock = tapClockNodeOut_clock; // @[ClockGroup.scala:104:9] assign clockNode_auto_anon_in_reset = tapClockNodeOut_reset; // @[ClockGroup.scala:104:9] assign childClock = tapClockNodeIn_clock; // @[MixedNode.scala:551:17] assign tapClockNodeOut_clock = tapClockNodeIn_clock; // @[MixedNode.scala:542:17, :551:17] assign childReset = tapClockNodeIn_reset; // @[MixedNode.scala:551:17] assign tapClockNodeOut_reset = tapClockNodeIn_reset; // @[MixedNode.scala:542:17, :551:17] wire tlMasterClockXingIn_a_ready = tlMasterClockXingOut_a_ready; // @[MixedNode.scala:542:17, :551:17] wire tlMasterClockXingIn_a_valid; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_a_valid_0 = tlMasterClockXingOut_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] tlMasterClockXingIn_a_bits_opcode; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_a_bits_opcode_0 = tlMasterClockXingOut_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] tlMasterClockXingIn_a_bits_param; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_a_bits_param_0 = tlMasterClockXingOut_a_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] tlMasterClockXingIn_a_bits_size; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_a_bits_size_0 = tlMasterClockXingOut_a_bits_size; // @[ClockDomain.scala:14:9] wire [1:0] tlMasterClockXingIn_a_bits_source; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_a_bits_source_0 = tlMasterClockXingOut_a_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] tlMasterClockXingIn_a_bits_address; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_a_bits_address_0 = tlMasterClockXingOut_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] tlMasterClockXingIn_a_bits_mask; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_a_bits_mask_0 = tlMasterClockXingOut_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] tlMasterClockXingIn_a_bits_data; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_a_bits_data_0 = tlMasterClockXingOut_a_bits_data; // @[ClockDomain.scala:14:9] wire tlMasterClockXingIn_a_bits_corrupt; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_a_bits_corrupt_0 = tlMasterClockXingOut_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire tlMasterClockXingIn_b_ready; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_b_ready_0 = tlMasterClockXingOut_b_ready; // @[ClockDomain.scala:14:9] wire tlMasterClockXingIn_b_valid = tlMasterClockXingOut_b_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] tlMasterClockXingIn_b_bits_opcode = tlMasterClockXingOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] tlMasterClockXingIn_b_bits_param = tlMasterClockXingOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] tlMasterClockXingIn_b_bits_size = tlMasterClockXingOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] tlMasterClockXingIn_b_bits_source = tlMasterClockXingOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] tlMasterClockXingIn_b_bits_address = tlMasterClockXingOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [7:0] tlMasterClockXingIn_b_bits_mask = tlMasterClockXingOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire [63:0] tlMasterClockXingIn_b_bits_data = tlMasterClockXingOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17] wire tlMasterClockXingIn_b_bits_corrupt = tlMasterClockXingOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire tlMasterClockXingIn_c_ready = tlMasterClockXingOut_c_ready; // @[MixedNode.scala:542:17, :551:17] wire tlMasterClockXingIn_c_valid; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_c_valid_0 = tlMasterClockXingOut_c_valid; // @[ClockDomain.scala:14:9] wire [2:0] tlMasterClockXingIn_c_bits_opcode; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_c_bits_opcode_0 = tlMasterClockXingOut_c_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] tlMasterClockXingIn_c_bits_param; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_c_bits_param_0 = tlMasterClockXingOut_c_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] tlMasterClockXingIn_c_bits_size; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_c_bits_size_0 = tlMasterClockXingOut_c_bits_size; // @[ClockDomain.scala:14:9] wire [1:0] tlMasterClockXingIn_c_bits_source; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_c_bits_source_0 = tlMasterClockXingOut_c_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] tlMasterClockXingIn_c_bits_address; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_c_bits_address_0 = tlMasterClockXingOut_c_bits_address; // @[ClockDomain.scala:14:9] wire [63:0] tlMasterClockXingIn_c_bits_data; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_c_bits_data_0 = tlMasterClockXingOut_c_bits_data; // @[ClockDomain.scala:14:9] wire tlMasterClockXingIn_c_bits_corrupt; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_c_bits_corrupt_0 = tlMasterClockXingOut_c_bits_corrupt; // @[ClockDomain.scala:14:9] wire tlMasterClockXingIn_d_ready; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_d_ready_0 = tlMasterClockXingOut_d_ready; // @[ClockDomain.scala:14:9] wire tlMasterClockXingIn_d_valid = tlMasterClockXingOut_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] tlMasterClockXingIn_d_bits_opcode = tlMasterClockXingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] tlMasterClockXingIn_d_bits_param = tlMasterClockXingOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] tlMasterClockXingIn_d_bits_size = tlMasterClockXingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] tlMasterClockXingIn_d_bits_source = tlMasterClockXingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] tlMasterClockXingIn_d_bits_sink = tlMasterClockXingOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire tlMasterClockXingIn_d_bits_denied = tlMasterClockXingOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] tlMasterClockXingIn_d_bits_data = tlMasterClockXingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire tlMasterClockXingIn_d_bits_corrupt = tlMasterClockXingOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire tlMasterClockXingIn_e_ready = tlMasterClockXingOut_e_ready; // @[MixedNode.scala:542:17, :551:17] wire tlMasterClockXingIn_e_valid; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_e_valid_0 = tlMasterClockXingOut_e_valid; // @[ClockDomain.scala:14:9] wire [2:0] tlMasterClockXingIn_e_bits_sink; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_e_bits_sink_0 = tlMasterClockXingOut_e_bits_sink; // @[ClockDomain.scala:14:9] assign tlMasterClockXingOut_a_valid = tlMasterClockXingIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_a_bits_opcode = tlMasterClockXingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_a_bits_param = tlMasterClockXingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_a_bits_size = tlMasterClockXingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_a_bits_source = tlMasterClockXingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_a_bits_address = tlMasterClockXingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_a_bits_mask = tlMasterClockXingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_a_bits_data = tlMasterClockXingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_a_bits_corrupt = tlMasterClockXingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_b_ready = tlMasterClockXingIn_b_ready; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_c_valid = tlMasterClockXingIn_c_valid; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_c_bits_opcode = tlMasterClockXingIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_c_bits_param = tlMasterClockXingIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_c_bits_size = tlMasterClockXingIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_c_bits_source = tlMasterClockXingIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_c_bits_address = tlMasterClockXingIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_c_bits_data = tlMasterClockXingIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_c_bits_corrupt = tlMasterClockXingIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_d_ready = tlMasterClockXingIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_e_valid = tlMasterClockXingIn_e_valid; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_e_bits_sink = tlMasterClockXingIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire intInClockXingOut_sync_0; // @[MixedNode.scala:542:17] wire intInClockXingOut_sync_1; // @[MixedNode.scala:542:17] assign intInClockXingOut_sync_0 = intInClockXingIn_sync_0; // @[MixedNode.scala:542:17, :551:17] assign intInClockXingOut_sync_1 = intInClockXingIn_sync_1; // @[MixedNode.scala:542:17, :551:17] wire intInClockXingOut_1_sync_0; // @[MixedNode.scala:542:17] assign intInClockXingOut_1_sync_0 = intInClockXingIn_1_sync_0; // @[MixedNode.scala:542:17, :551:17] wire intInClockXingOut_2_sync_0; // @[MixedNode.scala:542:17] assign intInClockXingOut_2_sync_0 = intInClockXingIn_2_sync_0; // @[MixedNode.scala:542:17, :551:17] wire intOutClockXingIn_2_sync_0; // @[MixedNode.scala:551:17] wire intOutClockXingOut_2_sync_0; // @[MixedNode.scala:542:17] wire intOutClockXingOut_3_sync_0; // @[MixedNode.scala:542:17] assign intOutClockXingOut_2_sync_0 = intOutClockXingIn_2_sync_0; // @[MixedNode.scala:542:17, :551:17] wire intOutClockXingIn_3_sync_0; // @[MixedNode.scala:551:17] assign intOutClockXingIn_2_sync_0 = intOutClockXingOut_3_sync_0; // @[MixedNode.scala:542:17, :551:17] assign intOutClockXingOut_3_sync_0 = intOutClockXingIn_3_sync_0; // @[MixedNode.scala:542:17, :551:17] RocketTile_7 element_reset_domain_rockettile ( // @[HasTiles.scala:164:59] .clock (element_reset_domain_childClock), // @[LazyModuleImp.scala:155:31] .reset (element_reset_domain_childReset), // @[LazyModuleImp.scala:158:31] .auto_buffer_out_a_ready (element_reset_domain_auto_rockettile_buffer_out_a_ready), // @[ClockDomain.scala:14:9] .auto_buffer_out_a_valid (element_reset_domain_auto_rockettile_buffer_out_a_valid), .auto_buffer_out_a_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_a_bits_opcode), .auto_buffer_out_a_bits_param (element_reset_domain_auto_rockettile_buffer_out_a_bits_param), .auto_buffer_out_a_bits_size (element_reset_domain_auto_rockettile_buffer_out_a_bits_size), .auto_buffer_out_a_bits_source (element_reset_domain_auto_rockettile_buffer_out_a_bits_source), .auto_buffer_out_a_bits_address (element_reset_domain_auto_rockettile_buffer_out_a_bits_address), .auto_buffer_out_a_bits_mask (element_reset_domain_auto_rockettile_buffer_out_a_bits_mask), .auto_buffer_out_a_bits_data (element_reset_domain_auto_rockettile_buffer_out_a_bits_data), .auto_buffer_out_b_ready (element_reset_domain_auto_rockettile_buffer_out_b_ready), .auto_buffer_out_b_valid (element_reset_domain_auto_rockettile_buffer_out_b_valid), // @[ClockDomain.scala:14:9] .auto_buffer_out_b_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_b_bits_opcode), // @[ClockDomain.scala:14:9] .auto_buffer_out_b_bits_param (element_reset_domain_auto_rockettile_buffer_out_b_bits_param), // @[ClockDomain.scala:14:9] .auto_buffer_out_b_bits_size (element_reset_domain_auto_rockettile_buffer_out_b_bits_size), // @[ClockDomain.scala:14:9] .auto_buffer_out_b_bits_source (element_reset_domain_auto_rockettile_buffer_out_b_bits_source), // @[ClockDomain.scala:14:9] .auto_buffer_out_b_bits_address (element_reset_domain_auto_rockettile_buffer_out_b_bits_address), // @[ClockDomain.scala:14:9] .auto_buffer_out_b_bits_mask (element_reset_domain_auto_rockettile_buffer_out_b_bits_mask), // @[ClockDomain.scala:14:9] .auto_buffer_out_b_bits_data (element_reset_domain_auto_rockettile_buffer_out_b_bits_data), // @[ClockDomain.scala:14:9] .auto_buffer_out_b_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_b_bits_corrupt), // @[ClockDomain.scala:14:9] .auto_buffer_out_c_ready (element_reset_domain_auto_rockettile_buffer_out_c_ready), // @[ClockDomain.scala:14:9] .auto_buffer_out_c_valid (element_reset_domain_auto_rockettile_buffer_out_c_valid), .auto_buffer_out_c_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_c_bits_opcode), .auto_buffer_out_c_bits_param (element_reset_domain_auto_rockettile_buffer_out_c_bits_param), .auto_buffer_out_c_bits_size (element_reset_domain_auto_rockettile_buffer_out_c_bits_size), .auto_buffer_out_c_bits_source (element_reset_domain_auto_rockettile_buffer_out_c_bits_source), .auto_buffer_out_c_bits_address (element_reset_domain_auto_rockettile_buffer_out_c_bits_address), .auto_buffer_out_c_bits_data (element_reset_domain_auto_rockettile_buffer_out_c_bits_data), .auto_buffer_out_d_ready (element_reset_domain_auto_rockettile_buffer_out_d_ready), .auto_buffer_out_d_valid (element_reset_domain_auto_rockettile_buffer_out_d_valid), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_d_bits_opcode), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_param (element_reset_domain_auto_rockettile_buffer_out_d_bits_param), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_size (element_reset_domain_auto_rockettile_buffer_out_d_bits_size), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_source (element_reset_domain_auto_rockettile_buffer_out_d_bits_source), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_sink (element_reset_domain_auto_rockettile_buffer_out_d_bits_sink), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_denied (element_reset_domain_auto_rockettile_buffer_out_d_bits_denied), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_data (element_reset_domain_auto_rockettile_buffer_out_d_bits_data), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_d_bits_corrupt), // @[ClockDomain.scala:14:9] .auto_buffer_out_e_ready (element_reset_domain_auto_rockettile_buffer_out_e_ready), // @[ClockDomain.scala:14:9] .auto_buffer_out_e_valid (element_reset_domain_auto_rockettile_buffer_out_e_valid), .auto_buffer_out_e_bits_sink (element_reset_domain_auto_rockettile_buffer_out_e_bits_sink), .auto_wfi_out_0 (element_reset_domain_auto_rockettile_wfi_out_0), .auto_int_local_in_3_0 (element_reset_domain_auto_rockettile_int_local_in_3_0), // @[ClockDomain.scala:14:9] .auto_int_local_in_2_0 (element_reset_domain_auto_rockettile_int_local_in_2_0), // @[ClockDomain.scala:14:9] .auto_int_local_in_1_0 (element_reset_domain_auto_rockettile_int_local_in_1_0), // @[ClockDomain.scala:14:9] .auto_int_local_in_1_1 (element_reset_domain_auto_rockettile_int_local_in_1_1), // @[ClockDomain.scala:14:9] .auto_int_local_in_0_0 (element_reset_domain_auto_rockettile_int_local_in_0_0), // @[ClockDomain.scala:14:9] .auto_trace_source_out_insns_0_valid (element_reset_domain_auto_rockettile_trace_source_out_insns_0_valid), .auto_trace_source_out_insns_0_iaddr (element_reset_domain_auto_rockettile_trace_source_out_insns_0_iaddr), .auto_trace_source_out_insns_0_insn (element_reset_domain_auto_rockettile_trace_source_out_insns_0_insn), .auto_trace_source_out_insns_0_priv (element_reset_domain_auto_rockettile_trace_source_out_insns_0_priv), .auto_trace_source_out_insns_0_exception (element_reset_domain_auto_rockettile_trace_source_out_insns_0_exception), .auto_trace_source_out_insns_0_interrupt (element_reset_domain_auto_rockettile_trace_source_out_insns_0_interrupt), .auto_trace_source_out_insns_0_cause (element_reset_domain_auto_rockettile_trace_source_out_insns_0_cause), .auto_trace_source_out_insns_0_tval (element_reset_domain_auto_rockettile_trace_source_out_insns_0_tval), .auto_trace_source_out_time (element_reset_domain_auto_rockettile_trace_source_out_time), .auto_hartid_in (element_reset_domain_auto_rockettile_hartid_in) // @[ClockDomain.scala:14:9] ); // @[HasTiles.scala:164:59] TLBuffer_a32d64s2k3z4c_15 buffer ( // @[Buffer.scala:75:28] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_a_ready (element_reset_domain_auto_rockettile_buffer_out_a_ready), .auto_in_a_valid (element_reset_domain_auto_rockettile_buffer_out_a_valid), // @[ClockDomain.scala:14:9] .auto_in_a_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_a_bits_opcode), // @[ClockDomain.scala:14:9] .auto_in_a_bits_param (element_reset_domain_auto_rockettile_buffer_out_a_bits_param), // @[ClockDomain.scala:14:9] .auto_in_a_bits_size (element_reset_domain_auto_rockettile_buffer_out_a_bits_size), // @[ClockDomain.scala:14:9] .auto_in_a_bits_source (element_reset_domain_auto_rockettile_buffer_out_a_bits_source), // @[ClockDomain.scala:14:9] .auto_in_a_bits_address (element_reset_domain_auto_rockettile_buffer_out_a_bits_address), // @[ClockDomain.scala:14:9] .auto_in_a_bits_mask (element_reset_domain_auto_rockettile_buffer_out_a_bits_mask), // @[ClockDomain.scala:14:9] .auto_in_a_bits_data (element_reset_domain_auto_rockettile_buffer_out_a_bits_data), // @[ClockDomain.scala:14:9] .auto_in_b_ready (element_reset_domain_auto_rockettile_buffer_out_b_ready), // @[ClockDomain.scala:14:9] .auto_in_b_valid (element_reset_domain_auto_rockettile_buffer_out_b_valid), .auto_in_b_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_b_bits_opcode), .auto_in_b_bits_param (element_reset_domain_auto_rockettile_buffer_out_b_bits_param), .auto_in_b_bits_size (element_reset_domain_auto_rockettile_buffer_out_b_bits_size), .auto_in_b_bits_source (element_reset_domain_auto_rockettile_buffer_out_b_bits_source), .auto_in_b_bits_address (element_reset_domain_auto_rockettile_buffer_out_b_bits_address), .auto_in_b_bits_mask (element_reset_domain_auto_rockettile_buffer_out_b_bits_mask), .auto_in_b_bits_data (element_reset_domain_auto_rockettile_buffer_out_b_bits_data), .auto_in_b_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_b_bits_corrupt), .auto_in_c_ready (element_reset_domain_auto_rockettile_buffer_out_c_ready), .auto_in_c_valid (element_reset_domain_auto_rockettile_buffer_out_c_valid), // @[ClockDomain.scala:14:9] .auto_in_c_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_c_bits_opcode), // @[ClockDomain.scala:14:9] .auto_in_c_bits_param (element_reset_domain_auto_rockettile_buffer_out_c_bits_param), // @[ClockDomain.scala:14:9] .auto_in_c_bits_size (element_reset_domain_auto_rockettile_buffer_out_c_bits_size), // @[ClockDomain.scala:14:9] .auto_in_c_bits_source (element_reset_domain_auto_rockettile_buffer_out_c_bits_source), // @[ClockDomain.scala:14:9] .auto_in_c_bits_address (element_reset_domain_auto_rockettile_buffer_out_c_bits_address), // @[ClockDomain.scala:14:9] .auto_in_c_bits_data (element_reset_domain_auto_rockettile_buffer_out_c_bits_data), // @[ClockDomain.scala:14:9] .auto_in_d_ready (element_reset_domain_auto_rockettile_buffer_out_d_ready), // @[ClockDomain.scala:14:9] .auto_in_d_valid (element_reset_domain_auto_rockettile_buffer_out_d_valid), .auto_in_d_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_d_bits_opcode), .auto_in_d_bits_param (element_reset_domain_auto_rockettile_buffer_out_d_bits_param), .auto_in_d_bits_size (element_reset_domain_auto_rockettile_buffer_out_d_bits_size), .auto_in_d_bits_source (element_reset_domain_auto_rockettile_buffer_out_d_bits_source), .auto_in_d_bits_sink (element_reset_domain_auto_rockettile_buffer_out_d_bits_sink), .auto_in_d_bits_denied (element_reset_domain_auto_rockettile_buffer_out_d_bits_denied), .auto_in_d_bits_data (element_reset_domain_auto_rockettile_buffer_out_d_bits_data), .auto_in_d_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_d_bits_corrupt), .auto_in_e_ready (element_reset_domain_auto_rockettile_buffer_out_e_ready), .auto_in_e_valid (element_reset_domain_auto_rockettile_buffer_out_e_valid), // @[ClockDomain.scala:14:9] .auto_in_e_bits_sink (element_reset_domain_auto_rockettile_buffer_out_e_bits_sink), // @[ClockDomain.scala:14:9] .auto_out_a_ready (tlMasterClockXingIn_a_ready), // @[MixedNode.scala:551:17] .auto_out_a_valid (tlMasterClockXingIn_a_valid), .auto_out_a_bits_opcode (tlMasterClockXingIn_a_bits_opcode), .auto_out_a_bits_param (tlMasterClockXingIn_a_bits_param), .auto_out_a_bits_size (tlMasterClockXingIn_a_bits_size), .auto_out_a_bits_source (tlMasterClockXingIn_a_bits_source), .auto_out_a_bits_address (tlMasterClockXingIn_a_bits_address), .auto_out_a_bits_mask (tlMasterClockXingIn_a_bits_mask), .auto_out_a_bits_data (tlMasterClockXingIn_a_bits_data), .auto_out_a_bits_corrupt (tlMasterClockXingIn_a_bits_corrupt), .auto_out_b_ready (tlMasterClockXingIn_b_ready), .auto_out_b_valid (tlMasterClockXingIn_b_valid), // @[MixedNode.scala:551:17] .auto_out_b_bits_opcode (tlMasterClockXingIn_b_bits_opcode), // @[MixedNode.scala:551:17] .auto_out_b_bits_param (tlMasterClockXingIn_b_bits_param), // @[MixedNode.scala:551:17] .auto_out_b_bits_size (tlMasterClockXingIn_b_bits_size), // @[MixedNode.scala:551:17] .auto_out_b_bits_source (tlMasterClockXingIn_b_bits_source), // @[MixedNode.scala:551:17] .auto_out_b_bits_address (tlMasterClockXingIn_b_bits_address), // @[MixedNode.scala:551:17] .auto_out_b_bits_mask (tlMasterClockXingIn_b_bits_mask), // @[MixedNode.scala:551:17] .auto_out_b_bits_data (tlMasterClockXingIn_b_bits_data), // @[MixedNode.scala:551:17] .auto_out_b_bits_corrupt (tlMasterClockXingIn_b_bits_corrupt), // @[MixedNode.scala:551:17] .auto_out_c_ready (tlMasterClockXingIn_c_ready), // @[MixedNode.scala:551:17] .auto_out_c_valid (tlMasterClockXingIn_c_valid), .auto_out_c_bits_opcode (tlMasterClockXingIn_c_bits_opcode), .auto_out_c_bits_param (tlMasterClockXingIn_c_bits_param), .auto_out_c_bits_size (tlMasterClockXingIn_c_bits_size), .auto_out_c_bits_source (tlMasterClockXingIn_c_bits_source), .auto_out_c_bits_address (tlMasterClockXingIn_c_bits_address), .auto_out_c_bits_data (tlMasterClockXingIn_c_bits_data), .auto_out_c_bits_corrupt (tlMasterClockXingIn_c_bits_corrupt), .auto_out_d_ready (tlMasterClockXingIn_d_ready), .auto_out_d_valid (tlMasterClockXingIn_d_valid), // @[MixedNode.scala:551:17] .auto_out_d_bits_opcode (tlMasterClockXingIn_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_out_d_bits_param (tlMasterClockXingIn_d_bits_param), // @[MixedNode.scala:551:17] .auto_out_d_bits_size (tlMasterClockXingIn_d_bits_size), // @[MixedNode.scala:551:17] .auto_out_d_bits_source (tlMasterClockXingIn_d_bits_source), // @[MixedNode.scala:551:17] .auto_out_d_bits_sink (tlMasterClockXingIn_d_bits_sink), // @[MixedNode.scala:551:17] .auto_out_d_bits_denied (tlMasterClockXingIn_d_bits_denied), // @[MixedNode.scala:551:17] .auto_out_d_bits_data (tlMasterClockXingIn_d_bits_data), // @[MixedNode.scala:551:17] .auto_out_d_bits_corrupt (tlMasterClockXingIn_d_bits_corrupt), // @[MixedNode.scala:551:17] .auto_out_e_ready (tlMasterClockXingIn_e_ready), // @[MixedNode.scala:551:17] .auto_out_e_valid (tlMasterClockXingIn_e_valid), .auto_out_e_bits_sink (tlMasterClockXingIn_e_bits_sink) ); // @[Buffer.scala:75:28] TLBuffer_20 buffer_1 ( // @[Buffer.scala:75:28] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset) // @[LazyModuleImp.scala:158:31] ); // @[Buffer.scala:75:28] IntSyncAsyncCrossingSink_n1x1_7 intsink ( // @[Crossing.scala:86:29] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_sync_0 (auto_intsink_in_sync_0_0), // @[ClockDomain.scala:14:9] .auto_out_0 (element_reset_domain_auto_rockettile_int_local_in_0_0) ); // @[Crossing.scala:86:29] IntSyncSyncCrossingSink_n1x2_11 intsink_1 ( // @[Crossing.scala:109:29] .auto_in_sync_0 (intInClockXingOut_sync_0), // @[MixedNode.scala:542:17] .auto_in_sync_1 (intInClockXingOut_sync_1), // @[MixedNode.scala:542:17] .auto_out_0 (element_reset_domain_auto_rockettile_int_local_in_1_0), .auto_out_1 (element_reset_domain_auto_rockettile_int_local_in_1_1) ); // @[Crossing.scala:109:29] IntSyncSyncCrossingSink_n1x1_43 intsink_2 ( // @[Crossing.scala:109:29] .auto_in_sync_0 (intInClockXingOut_1_sync_0), // @[MixedNode.scala:542:17] .auto_out_0 (element_reset_domain_auto_rockettile_int_local_in_2_0) ); // @[Crossing.scala:109:29] IntSyncSyncCrossingSink_n1x1_44 intsink_3 ( // @[Crossing.scala:109:29] .auto_in_sync_0 (intInClockXingOut_2_sync_0), // @[MixedNode.scala:542:17] .auto_out_0 (element_reset_domain_auto_rockettile_int_local_in_3_0) ); // @[Crossing.scala:109:29] IntSyncSyncCrossingSink_n1x1_45 intsink_4 (); // @[Crossing.scala:109:29] IntSyncCrossingSource_n1x1_29 intsource ( // @[Crossing.scala:29:31] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset) // @[LazyModuleImp.scala:158:31] ); // @[Crossing.scala:29:31] IntSyncSyncCrossingSink_n1x1_46 intsink_5 ( // @[Crossing.scala:109:29] .auto_in_sync_0 (intOutClockXingOut_2_sync_0), // @[MixedNode.scala:542:17] .auto_out_0 (auto_intsink_out_1_0_0) ); // @[Crossing.scala:109:29] IntSyncCrossingSource_n1x1_30 intsource_1 ( // @[Crossing.scala:29:31] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_0 (element_reset_domain_auto_rockettile_wfi_out_0), // @[ClockDomain.scala:14:9] .auto_out_sync_0 (intOutClockXingIn_3_sync_0) ); // @[Crossing.scala:29:31] IntSyncSyncCrossingSink_n1x1_47 intsink_6 (); // @[Crossing.scala:109:29] IntSyncCrossingSource_n1x1_31 intsource_2 ( // @[Crossing.scala:29:31] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset) // @[LazyModuleImp.scala:158:31] ); // @[Crossing.scala:29:31] assign auto_intsink_out_1_0 = auto_intsink_out_1_0_0; // @[ClockDomain.scala:14:9] assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_valid = auto_element_reset_domain_rockettile_trace_source_out_insns_0_valid_0; // @[ClockDomain.scala:14:9] assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_iaddr = auto_element_reset_domain_rockettile_trace_source_out_insns_0_iaddr_0; // @[ClockDomain.scala:14:9] assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_insn = auto_element_reset_domain_rockettile_trace_source_out_insns_0_insn_0; // @[ClockDomain.scala:14:9] assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_priv = auto_element_reset_domain_rockettile_trace_source_out_insns_0_priv_0; // @[ClockDomain.scala:14:9] assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_exception = auto_element_reset_domain_rockettile_trace_source_out_insns_0_exception_0; // @[ClockDomain.scala:14:9] assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_interrupt = auto_element_reset_domain_rockettile_trace_source_out_insns_0_interrupt_0; // @[ClockDomain.scala:14:9] assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_cause = auto_element_reset_domain_rockettile_trace_source_out_insns_0_cause_0; // @[ClockDomain.scala:14:9] assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_tval = auto_element_reset_domain_rockettile_trace_source_out_insns_0_tval_0; // @[ClockDomain.scala:14:9] assign auto_element_reset_domain_rockettile_trace_source_out_time = auto_element_reset_domain_rockettile_trace_source_out_time_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_a_valid = auto_tl_master_clock_xing_out_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_a_bits_opcode = auto_tl_master_clock_xing_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_a_bits_param = auto_tl_master_clock_xing_out_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_a_bits_size = auto_tl_master_clock_xing_out_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_a_bits_source = auto_tl_master_clock_xing_out_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_a_bits_address = auto_tl_master_clock_xing_out_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_a_bits_mask = auto_tl_master_clock_xing_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_a_bits_data = auto_tl_master_clock_xing_out_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_a_bits_corrupt = auto_tl_master_clock_xing_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_b_ready = auto_tl_master_clock_xing_out_b_ready_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_c_valid = auto_tl_master_clock_xing_out_c_valid_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_c_bits_opcode = auto_tl_master_clock_xing_out_c_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_c_bits_param = auto_tl_master_clock_xing_out_c_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_c_bits_size = auto_tl_master_clock_xing_out_c_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_c_bits_source = auto_tl_master_clock_xing_out_c_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_c_bits_address = auto_tl_master_clock_xing_out_c_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_c_bits_data = auto_tl_master_clock_xing_out_c_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_c_bits_corrupt = auto_tl_master_clock_xing_out_c_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_d_ready = auto_tl_master_clock_xing_out_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_e_valid = auto_tl_master_clock_xing_out_e_valid_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_e_bits_sink = auto_tl_master_clock_xing_out_e_bits_sink_0; // @[ClockDomain.scala:14:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Tile.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ import Util._ /** * A Tile is a purely combinational 2D array of passThrough PEs. * a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs * @param width The data width of each PE in bits * @param rows Number of PEs on each row * @param columns Number of PEs on each column */ class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module { val io = IO(new Bundle { val in_a = Input(Vec(rows, inputType)) val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it val in_d = Input(Vec(columns, outputType)) val in_control = Input(Vec(columns, new PEControl(accType))) val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val in_last = Input(Vec(columns, Bool())) val out_a = Output(Vec(rows, inputType)) val out_c = Output(Vec(columns, outputType)) val out_b = Output(Vec(columns, outputType)) val out_control = Output(Vec(columns, new PEControl(accType))) val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val out_last = Output(Vec(columns, Bool())) val in_valid = Input(Vec(columns, Bool())) val out_valid = Output(Vec(columns, Bool())) val bad_dataflow = Output(Bool()) }) import ev._ val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls))) val tileT = tile.transpose // TODO: abstract hori/vert broadcast, all these connections look the same // Broadcast 'a' horizontally across the Tile for (r <- 0 until rows) { tile(r).foldLeft(io.in_a(r)) { case (in_a, pe) => pe.io.in_a := in_a pe.io.out_a } } // Broadcast 'b' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_b(c)) { case (in_b, pe) => pe.io.in_b := (if (tree_reduction) in_b.zero else in_b) pe.io.out_b } } // Broadcast 'd' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_d(c)) { case (in_d, pe) => pe.io.in_d := in_d pe.io.out_c } } // Broadcast 'control' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_control(c)) { case (in_ctrl, pe) => pe.io.in_control := in_ctrl pe.io.out_control } } // Broadcast 'garbage' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_valid(c)) { case (v, pe) => pe.io.in_valid := v pe.io.out_valid } } // Broadcast 'id' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_id(c)) { case (id, pe) => pe.io.in_id := id pe.io.out_id } } // Broadcast 'last' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_last(c)) { case (last, pe) => pe.io.in_last := last pe.io.out_last } } // Drive the Tile's bottom IO for (c <- 0 until columns) { io.out_c(c) := tile(rows-1)(c).io.out_c io.out_control(c) := tile(rows-1)(c).io.out_control io.out_id(c) := tile(rows-1)(c).io.out_id io.out_last(c) := tile(rows-1)(c).io.out_last io.out_valid(c) := tile(rows-1)(c).io.out_valid io.out_b(c) := { if (tree_reduction) { val prods = tileT(c).map(_.io.out_b) accumulateTree(prods :+ io.in_b(c)) } else { tile(rows - 1)(c).io.out_b } } } io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_\|\|_)).reduce(_\|\|_) // Drive the Tile's right IO for (r <- 0 until rows) { io.out_a(r) := tile(r)(columns-1).io.out_a } }	module Tile_1( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_257 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" / black /, label = (ei.manager.beatBytes 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red /, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" / green /) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" / yellow /, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /* Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph / def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } } File Arbiter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ object TLArbiter { // (valids, select) => readys type Policy = (Integer, UInt, Bool) => UInt val lowestIndexFirst: Policy = (width, valids, select) => ~(leftOR(valids) << 1)(width-1, 0) val highestIndexFirst: Policy = (width, valids, select) => ~((rightOR(valids) >> 1).pad(width)) val roundRobin: Policy = (width, valids, select) => if (width == 1) 1.U(1.W) else { val valid = valids(width-1, 0) assert (valid === valids) val mask = RegInit(((BigInt(1) << width)-1).U(width-1,0)) val filter = Cat(valid & ~mask, valid) val unready = (rightOR(filter, width2, width) >> 1) \| (mask << width) val readys = ~((unready >> width) & unready(width-1, 0)) when (select && valid.orR) { mask := leftOR(readys & valid, width) } readys(width-1, 0) } def lowestFromSeq[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: Seq[DecoupledIO[T]]): Unit = { apply(lowestIndexFirst)(sink, sources.map(s => (edge.numBeats1(s.bits), s)):_) } def lowest[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]): Unit = { apply(lowestIndexFirst)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_) } def highest[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]): Unit = { apply(highestIndexFirst)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_) } def robin[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]): Unit = { apply(roundRobin)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_) } def apply[T <: Data](policy: Policy)(sink: DecoupledIO[T], sources: (UInt, DecoupledIO[T])): Unit = { if (sources.isEmpty) { sink.bits := DontCare } else if (sources.size == 1) { sink :<>= sources.head._2 } else { val pairs = sources.toList val beatsIn = pairs.map(_._1) val sourcesIn = pairs.map(_._2) // The number of beats which remain to be sent val beatsLeft = RegInit(0.U) val idle = beatsLeft === 0.U val latch = idle && sink.ready // winner (if any) claims sink // Who wants access to the sink? val valids = sourcesIn.map(_.valid) // Arbitrate amongst the requests val readys = VecInit(policy(valids.size, Cat(valids.reverse), latch).asBools) // Which request wins arbitration? val winner = VecInit((readys zip valids) map { case (r,v) => r&&v }) // Confirm the policy works properly require (readys.size == valids.size) // Never two winners val prefixOR = winner.scanLeft(false.B)(_\|\|_).init assert((prefixOR zip winner) map { case (p,w) => !p \|\| !w } reduce {_ && _}) // If there was any request, there is a winner assert (!valids.reduce(_\|\|_) \|\| winner.reduce(_\|\|_)) // Track remaining beats val maskedBeats = (winner zip beatsIn) map { case (w,b) => Mux(w, b, 0.U) } val initBeats = maskedBeats.reduce(_ \| _) // no winner => 0 beats beatsLeft := Mux(latch, initBeats, beatsLeft - sink.fire) // The one-hot source granted access in the previous cycle val state = RegInit(VecInit(Seq.fill(sources.size)(false.B))) val muxState = Mux(idle, winner, state) state := muxState val allowed = Mux(idle, readys, state) (sourcesIn zip allowed) foreach { case (s, r) => s.ready := sink.ready && r } sink.valid := Mux(idle, valids.reduce(_\|\|_), Mux1H(state, valids)) sink.bits :<= Mux1H(muxState, sourcesIn.map(_.bits)) } } } // Synthesizable unit tests import freechips.rocketchip.unittest._ abstract class DecoupledArbiterTest( policy: TLArbiter.Policy, txns: Int, timeout: Int, val numSources: Int, beatsLeftFromIdx: Int => UInt) (implicit p: Parameters) extends UnitTest(timeout) { val sources = Wire(Vec(numSources, DecoupledIO(UInt(log2Ceil(numSources).W)))) dontTouch(sources.suggestName("sources")) val sink = Wire(DecoupledIO(UInt(log2Ceil(numSources).W))) dontTouch(sink.suggestName("sink")) val count = RegInit(0.U(log2Ceil(txns).W)) val lfsr = LFSR(16, true.B) sources.zipWithIndex.map { case (z, i) => z.bits := i.U } TLArbiter(policy)(sink, sources.zipWithIndex.map { case (z, i) => (beatsLeftFromIdx(i), z) }:_) count := count + 1.U io.finished := count >= txns.U } /** This tests that when a specific pattern of source valids are driven, * a new index from amongst that pattern is always selected, * unless one of those sources takes multiple beats, * in which case the same index should be selected until the arbiter goes idle. / class TLDecoupledArbiterRobinTest(txns: Int = 128, timeout: Int = 500000, print: Boolean = false) (implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.roundRobin, txns, timeout, 6, i => i.U) { val lastWinner = RegInit((numSources+1).U) val beatsLeft = RegInit(0.U(log2Ceil(numSources).W)) val first = lastWinner > numSources.U val valid = lfsr(0) val ready = lfsr(15) sink.ready := ready sources.zipWithIndex.map { // pattern: every even-indexed valid is driven the same random way case (s, i) => s.valid := (if (i % 2 == 1) false.B else valid) } when (sink.fire) { if (print) { printf("TestRobin: %d\n", sink.bits) } when (beatsLeft === 0.U) { assert(lastWinner =/= sink.bits, "Round robin did not pick a new idx despite one being valid.") lastWinner := sink.bits beatsLeft := sink.bits } .otherwise { assert(lastWinner === sink.bits, "Round robin did not pick the same index over multiple beats") beatsLeft := beatsLeft - 1.U } } if (print) { when (!sink.fire) { printf("TestRobin: idle (%d %d)\n", valid, ready) } } } /* This tests that the lowest index is always selected across random single cycle transactions. / class TLDecoupledArbiterLowestTest(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.lowestIndexFirst, txns, timeout, 15, _ => 0.U) { def assertLowest(id: Int): Unit = { when (sources(id).valid) { assert((numSources-1 until id by -1).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a higher valid source was granted ready.") } } sources.zipWithIndex.map { case (s, i) => s.valid := lfsr(i) } sink.ready := lfsr(15) when (sink.fire) { (0 until numSources).foreach(assertLowest(_)) } } /* This tests that the highest index is always selected across random single cycle transactions. / class TLDecoupledArbiterHighestTest(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.highestIndexFirst, txns, timeout, 15, _ => 0.U) { def assertHighest(id: Int): Unit = { when (sources(id).valid) { assert((0 until id).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a lower valid source was granted ready.") } } sources.zipWithIndex.map { case (s, i) => s.valid := lfsr(i) } sink.ready := lfsr(15) when (sink.fire) { (0 until numSources).foreach(assertHighest(_)) } } File Xbar.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressDecoder, AddressSet, RegionType, IdRange, TriStateValue} import freechips.rocketchip.util.BundleField // Trades off slave port proximity against routing resource cost object ForceFanout { def apply[T]( a: TriStateValue = TriStateValue.unset, b: TriStateValue = TriStateValue.unset, c: TriStateValue = TriStateValue.unset, d: TriStateValue = TriStateValue.unset, e: TriStateValue = TriStateValue.unset)(body: Parameters => T)(implicit p: Parameters) = { body(p.alterPartial { case ForceFanoutKey => p(ForceFanoutKey) match { case ForceFanoutParams(pa, pb, pc, pd, pe) => ForceFanoutParams(a.update(pa), b.update(pb), c.update(pc), d.update(pd), e.update(pe)) } }) } } private case class ForceFanoutParams(a: Boolean, b: Boolean, c: Boolean, d: Boolean, e: Boolean) private case object ForceFanoutKey extends Field(ForceFanoutParams(false, false, false, false, false)) class TLXbar(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule { val node = new TLNexusNode( clientFn = { seq => seq(0).v1copy( echoFields = BundleField.union(seq.flatMap(_.echoFields)), requestFields = BundleField.union(seq.flatMap(_.requestFields)), responseKeys = seq.flatMap(_.responseKeys).distinct, minLatency = seq.map(_.minLatency).min, clients = (TLXbar.mapInputIds(seq) zip seq) flatMap { case (range, port) => port.clients map { client => client.v1copy( sourceId = client.sourceId.shift(range.start) )} } ) }, managerFn = { seq => val fifoIdFactory = TLXbar.relabeler() seq(0).v1copy( responseFields = BundleField.union(seq.flatMap(_.responseFields)), requestKeys = seq.flatMap(_.requestKeys).distinct, minLatency = seq.map(_.minLatency).min, endSinkId = TLXbar.mapOutputIds(seq).map(_.end).max, managers = seq.flatMap { port => require (port.beatBytes == seq(0).beatBytes, s"Xbar ($name with parent $parent) data widths don't match: ${port.managers.map(_.name)} has ${port.beatBytes}B vs ${seq(0).managers.map(_.name)} has ${seq(0).beatBytes}B") val fifoIdMapper = fifoIdFactory() port.managers map { manager => manager.v1copy( fifoId = manager.fifoId.map(fifoIdMapper(_)) )} } ) } ){ override def circuitIdentity = outputs.size == 1 && inputs.size == 1 } lazy val module = new Impl class Impl extends LazyModuleImp(this) { if ((node.in.size node.out.size) > (832)) { println (s"!!! WARNING !!!") println (s" Your TLXbar ($name with parent $parent) is very large, with ${node.in.size} Masters and ${node.out.size} Slaves.") println (s"!!! WARNING !!!") } val wide_bundle = TLBundleParameters.union((node.in ++ node.out).map(_._2.bundle)) override def desiredName = (Seq("TLXbar") ++ nameSuffix ++ Seq(s"i${node.in.size}_o${node.out.size}_${wide_bundle.shortName}")).mkString("_") TLXbar.circuit(policy, node.in, node.out) } } object TLXbar { def mapInputIds(ports: Seq[TLMasterPortParameters]) = assignRanges(ports.map(_.endSourceId)) def mapOutputIds(ports: Seq[TLSlavePortParameters]) = assignRanges(ports.map(_.endSinkId)) def assignRanges(sizes: Seq[Int]) = { val pow2Sizes = sizes.map { z => if (z == 0) 0 else 1 << log2Ceil(z) } val tuples = pow2Sizes.zipWithIndex.sortBy(_._1) // record old index, then sort by increasing size val starts = tuples.scanRight(0)(_._1 + _).tail // suffix-sum of the sizes = the start positions val ranges = (tuples zip starts) map { case ((sz, i), st) => (if (sz == 0) IdRange(0, 0) else IdRange(st, st + sz), i) } ranges.sortBy(_._2).map(_._1) // Restore orignal order } def relabeler() = { var idFactory = 0 () => { val fifoMap = scala.collection.mutable.HashMap.empty[Int, Int] (x: Int) => { if (fifoMap.contains(x)) fifoMap(x) else { val out = idFactory idFactory = idFactory + 1 fifoMap += (x -> out) out } } } } def circuit(policy: TLArbiter.Policy, seqIn: Seq[(TLBundle, TLEdge)], seqOut: Seq[(TLBundle, TLEdge)]) { val (io_in, edgesIn) = seqIn.unzip val (io_out, edgesOut) = seqOut.unzip // Not every master need connect to every slave on every channel; determine which connections are necessary val reachableIO = edgesIn.map { cp => edgesOut.map { mp => cp.client.clients.exists { c => mp.manager.managers.exists { m => c.visibility.exists { ca => m.address.exists { ma => ca.overlaps(ma)}}}} }.toVector}.toVector val probeIO = (edgesIn zip reachableIO).map { case (cp, reachableO) => (edgesOut zip reachableO).map { case (mp, reachable) => reachable && cp.client.anySupportProbe && mp.manager.managers.exists(_.regionType >= RegionType.TRACKED) }.toVector}.toVector val releaseIO = (edgesIn zip reachableIO).map { case (cp, reachableO) => (edgesOut zip reachableO).map { case (mp, reachable) => reachable && cp.client.anySupportProbe && mp.manager.anySupportAcquireB }.toVector}.toVector val connectAIO = reachableIO val connectBIO = probeIO val connectCIO = releaseIO val connectDIO = reachableIO val connectEIO = releaseIO def transpose[T](x: Seq[Seq[T]]) = if (x.isEmpty) Nil else Vector.tabulate(x(0).size) { i => Vector.tabulate(x.size) { j => x(j)(i) } } val connectAOI = transpose(connectAIO) val connectBOI = transpose(connectBIO) val connectCOI = transpose(connectCIO) val connectDOI = transpose(connectDIO) val connectEOI = transpose(connectEIO) // Grab the port ID mapping val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client)) val outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager)) // We need an intermediate size of bundle with the widest possible identifiers val wide_bundle = TLBundleParameters.union(io_in.map(_.params) ++ io_out.map(_.params)) // Handle size = 1 gracefully (Chisel3 empty range is broken) def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0) // Transform input bundle sources (sinks use global namespace on both sides) val in = Wire(Vec(io_in.size, TLBundle(wide_bundle))) for (i <- 0 until in.size) { val r = inputIdRanges(i) if (connectAIO(i).exists(x=>x)) { in(i).a.bits.user := DontCare in(i).a.squeezeAll.waiveAll :<>= io_in(i).a.squeezeAll.waiveAll in(i).a.bits.source := io_in(i).a.bits.source \| r.start.U } else { in(i).a := DontCare io_in(i).a := DontCare in(i).a.valid := false.B io_in(i).a.ready := true.B } if (connectBIO(i).exists(x=>x)) { io_in(i).b.squeezeAll :<>= in(i).b.squeezeAll io_in(i).b.bits.source := trim(in(i).b.bits.source, r.size) } else { in(i).b := DontCare io_in(i).b := DontCare in(i).b.ready := true.B io_in(i).b.valid := false.B } if (connectCIO(i).exists(x=>x)) { in(i).c.bits.user := DontCare in(i).c.squeezeAll.waiveAll :<>= io_in(i).c.squeezeAll.waiveAll in(i).c.bits.source := io_in(i).c.bits.source \| r.start.U } else { in(i).c := DontCare io_in(i).c := DontCare in(i).c.valid := false.B io_in(i).c.ready := true.B } if (connectDIO(i).exists(x=>x)) { io_in(i).d.squeezeAll.waiveAll :<>= in(i).d.squeezeAll.waiveAll io_in(i).d.bits.source := trim(in(i).d.bits.source, r.size) } else { in(i).d := DontCare io_in(i).d := DontCare in(i).d.ready := true.B io_in(i).d.valid := false.B } if (connectEIO(i).exists(x=>x)) { in(i).e.squeezeAll :<>= io_in(i).e.squeezeAll } else { in(i).e := DontCare io_in(i).e := DontCare in(i).e.valid := false.B io_in(i).e.ready := true.B } } // Transform output bundle sinks (sources use global namespace on both sides) val out = Wire(Vec(io_out.size, TLBundle(wide_bundle))) for (o <- 0 until out.size) { val r = outputIdRanges(o) if (connectAOI(o).exists(x=>x)) { out(o).a.bits.user := DontCare io_out(o).a.squeezeAll.waiveAll :<>= out(o).a.squeezeAll.waiveAll } else { out(o).a := DontCare io_out(o).a := DontCare out(o).a.ready := true.B io_out(o).a.valid := false.B } if (connectBOI(o).exists(x=>x)) { out(o).b.squeezeAll :<>= io_out(o).b.squeezeAll } else { out(o).b := DontCare io_out(o).b := DontCare out(o).b.valid := false.B io_out(o).b.ready := true.B } if (connectCOI(o).exists(x=>x)) { out(o).c.bits.user := DontCare io_out(o).c.squeezeAll.waiveAll :<>= out(o).c.squeezeAll.waiveAll } else { out(o).c := DontCare io_out(o).c := DontCare out(o).c.ready := true.B io_out(o).c.valid := false.B } if (connectDOI(o).exists(x=>x)) { out(o).d.squeezeAll :<>= io_out(o).d.squeezeAll out(o).d.bits.sink := io_out(o).d.bits.sink \| r.start.U } else { out(o).d := DontCare io_out(o).d := DontCare out(o).d.valid := false.B io_out(o).d.ready := true.B } if (connectEOI(o).exists(x=>x)) { io_out(o).e.squeezeAll :<>= out(o).e.squeezeAll io_out(o).e.bits.sink := trim(out(o).e.bits.sink, r.size) } else { out(o).e := DontCare io_out(o).e := DontCare out(o).e.ready := true.B io_out(o).e.valid := false.B } } // Filter a list to only those elements selected def filter[T](data: Seq[T], mask: Seq[Boolean]) = (data zip mask).filter(_._2).map(_._1) // Based on input=>output connectivity, create per-input minimal address decode circuits val requiredAC = (connectAIO ++ connectCIO).distinct val outputPortFns: Map[Vector[Boolean], Seq[UInt => Bool]] = requiredAC.map { connectO => val port_addrs = edgesOut.map(_.manager.managers.flatMap(_.address)) val routingMask = AddressDecoder(filter(port_addrs, connectO)) val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct)) // Print the address mapping if (false) { println("Xbar mapping:") route_addrs.foreach { p => print(" ") p.foreach { a => print(s" ${a}") } println("") } println("--") } (connectO, route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_ \|\| _))) }.toMap // Print the ID mapping if (false) { println(s"XBar mapping:") (edgesIn zip inputIdRanges).zipWithIndex.foreach { case ((edge, id), i) => println(s"\t$i assigned ${id} for ${edge.client.clients.map(_.name).mkString(", ")}") } println("") } val addressA = (in zip edgesIn) map { case (i, e) => e.address(i.a.bits) } val addressC = (in zip edgesIn) map { case (i, e) => e.address(i.c.bits) } def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B val requestAIO = (connectAIO zip addressA) map { case (c, i) => outputPortFns(c).map { o => unique(c) \|\| o(i) } } val requestCIO = (connectCIO zip addressC) map { case (c, i) => outputPortFns(c).map { o => unique(c) \|\| o(i) } } val requestBOI = out.map { o => inputIdRanges.map { i => i.contains(o.b.bits.source) } } val requestDOI = out.map { o => inputIdRanges.map { i => i.contains(o.d.bits.source) } } val requestEIO = in.map { i => outputIdRanges.map { o => o.contains(i.e.bits.sink) } } val beatsAI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.a.bits) } val beatsBO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.b.bits) } val beatsCI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.c.bits) } val beatsDO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.d.bits) } val beatsEI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.e.bits) } // Fanout the input sources to the output sinks val portsAOI = transpose((in zip requestAIO) map { case (i, r) => TLXbar.fanout(i.a, r, edgesOut.map(_.params(ForceFanoutKey).a)) }) val portsBIO = transpose((out zip requestBOI) map { case (o, r) => TLXbar.fanout(o.b, r, edgesIn .map(_.params(ForceFanoutKey).b)) }) val portsCOI = transpose((in zip requestCIO) map { case (i, r) => TLXbar.fanout(i.c, r, edgesOut.map(_.params(ForceFanoutKey).c)) }) val portsDIO = transpose((out zip requestDOI) map { case (o, r) => TLXbar.fanout(o.d, r, edgesIn .map(_.params(ForceFanoutKey).d)) }) val portsEOI = transpose((in zip requestEIO) map { case (i, r) => TLXbar.fanout(i.e, r, edgesOut.map(_.params(ForceFanoutKey).e)) }) // Arbitrate amongst the sources for (o <- 0 until out.size) { TLArbiter(policy)(out(o).a, filter(beatsAI zip portsAOI(o), connectAOI(o)):_) TLArbiter(policy)(out(o).c, filter(beatsCI zip portsCOI(o), connectCOI(o)):_) TLArbiter(policy)(out(o).e, filter(beatsEI zip portsEOI(o), connectEOI(o)):_) filter(portsAOI(o), connectAOI(o).map(!_)) foreach { r => r.ready := false.B } filter(portsCOI(o), connectCOI(o).map(!_)) foreach { r => r.ready := false.B } filter(portsEOI(o), connectEOI(o).map(!_)) foreach { r => r.ready := false.B } } for (i <- 0 until in.size) { TLArbiter(policy)(in(i).b, filter(beatsBO zip portsBIO(i), connectBIO(i)):_) TLArbiter(policy)(in(i).d, filter(beatsDO zip portsDIO(i), connectDIO(i)):_) filter(portsBIO(i), connectBIO(i).map(!_)) foreach { r => r.ready := false.B } filter(portsDIO(i), connectDIO(i).map(!_)) foreach { r => r.ready := false.B } } } def apply(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode = { val xbar = LazyModule(new TLXbar(policy, nameSuffix)) xbar.node } // Replicate an input port to each output port def fanout[T <: TLChannel](input: DecoupledIO[T], select: Seq[Bool], force: Seq[Boolean] = Nil): Seq[DecoupledIO[T]] = { val filtered = Wire(Vec(select.size, chiselTypeOf(input))) for (i <- 0 until select.size) { filtered(i).bits := (if (force.lift(i).getOrElse(false)) IdentityModule(input.bits) else input.bits) filtered(i).valid := input.valid && (select(i) \|\| (select.size == 1).B) } input.ready := Mux1H(select, filtered.map(_.ready)) filtered } } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMXbar(nManagers: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("Xbar")) val xbar = LazyModule(new TLXbar) xbar.node := TLDelayer(0.1) := model.node := fuzz.node (0 until nManagers) foreach { n => val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400n, 0x3ff))) ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node } lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMXbarTest(nManagers: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMXbar(nManagers,txns)).module) dut.io.start := io.start io.finished := dut.io.finished } class TLMulticlientXbar(nManagers: Int, nClients: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val xbar = LazyModule(new TLXbar) val fuzzers = (0 until nClients) map { n => val fuzz = LazyModule(new TLFuzzer(txns)) xbar.node := TLDelayer(0.1) := fuzz.node fuzz } (0 until nManagers) foreach { n => val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400n, 0x3ff))) ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node } lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzzers.last.module.io.finished } } class TLMulticlientXbarTest(nManagers: Int, nClients: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLMulticlientXbar(nManagers, nClients, txns)).module) dut.io.start := io.start io.finished := dut.io.finished }	module TLXbar_cbus_in_i2_o1_a29d64s10k1z4u( // @[Xbar.scala:74:9] input clock, // @[Xbar.scala:74:9] input reset, // @[Xbar.scala:74:9] output auto_anon_in_1_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_a_valid, // @[LazyModuleImp.scala:107:25] input [28:0] auto_anon_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_1_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_1_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_0_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_0_a_bits_size, // @[LazyModuleImp.scala:107:25] input [8:0] auto_anon_in_0_a_bits_source, // @[LazyModuleImp.scala:107:25] input [28:0] auto_anon_in_0_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_0_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_0_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_0_d_bits_size, // @[LazyModuleImp.scala:107:25] output [8:0] auto_anon_in_0_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_0_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [9:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [28:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [9:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire out_0_d_bits_sink; // @[Xbar.scala:216:19] wire [9:0] in_0_a_bits_source; // @[Xbar.scala:159:18] wire auto_anon_in_1_a_valid_0 = auto_anon_in_1_a_valid; // @[Xbar.scala:74:9] wire [28:0] auto_anon_in_1_a_bits_address_0 = auto_anon_in_1_a_bits_address; // @[Xbar.scala:74:9] wire [63:0] auto_anon_in_1_a_bits_data_0 = auto_anon_in_1_a_bits_data; // @[Xbar.scala:74:9] wire auto_anon_in_0_a_valid_0 = auto_anon_in_0_a_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_a_bits_opcode_0 = auto_anon_in_0_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_a_bits_param_0 = auto_anon_in_0_a_bits_param; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_0_a_bits_size_0 = auto_anon_in_0_a_bits_size; // @[Xbar.scala:74:9] wire [8:0] auto_anon_in_0_a_bits_source_0 = auto_anon_in_0_a_bits_source; // @[Xbar.scala:74:9] wire [28:0] auto_anon_in_0_a_bits_address_0 = auto_anon_in_0_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] auto_anon_in_0_a_bits_mask_0 = auto_anon_in_0_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] auto_anon_in_0_a_bits_data_0 = auto_anon_in_0_a_bits_data; // @[Xbar.scala:74:9] wire auto_anon_in_0_a_bits_corrupt_0 = auto_anon_in_0_a_bits_corrupt; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_ready_0 = auto_anon_in_0_d_ready; // @[Xbar.scala:74:9] wire auto_anon_out_a_ready_0 = auto_anon_out_a_ready; // @[Xbar.scala:74:9] wire auto_anon_out_d_valid_0 = auto_anon_out_d_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_d_bits_opcode_0 = auto_anon_out_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] auto_anon_out_d_bits_param_0 = auto_anon_out_d_bits_param; // @[Xbar.scala:74:9] wire [3:0] auto_anon_out_d_bits_size_0 = auto_anon_out_d_bits_size; // @[Xbar.scala:74:9] wire [9:0] auto_anon_out_d_bits_source_0 = auto_anon_out_d_bits_source; // @[Xbar.scala:74:9] wire auto_anon_out_d_bits_sink_0 = auto_anon_out_d_bits_sink; // @[Xbar.scala:74:9] wire auto_anon_out_d_bits_denied_0 = auto_anon_out_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_d_bits_data_0 = auto_anon_out_d_bits_data; // @[Xbar.scala:74:9] wire auto_anon_out_d_bits_corrupt_0 = auto_anon_out_d_bits_corrupt; // @[Xbar.scala:74:9] wire _readys_T_2 = reset; // @[Arbiter.scala:22:12] wire [2:0] auto_anon_in_1_a_bits_opcode = 3'h0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_1_a_bits_param = 3'h0; // @[Xbar.scala:74:9] wire [2:0] anonIn_1_a_bits_opcode = 3'h0; // @[MixedNode.scala:551:17] wire [2:0] anonIn_1_a_bits_param = 3'h0; // @[MixedNode.scala:551:17] wire [2:0] in_1_a_bits_opcode = 3'h0; // @[Xbar.scala:159:18] wire [2:0] in_1_a_bits_param = 3'h0; // @[Xbar.scala:159:18] wire [2:0] _addressC_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _addressC_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _addressC_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _addressC_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _addressC_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _addressC_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _addressC_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _addressC_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _requestBOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _requestBOI_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _beatsBO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _beatsBO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _beatsCI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _beatsCI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _beatsCI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _beatsCI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _beatsCI_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _beatsCI_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _beatsCI_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _beatsCI_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] portsAOI_filtered_1_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsAOI_filtered_1_0_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] _portsBIO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _portsBIO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] portsBIO_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsBIO_filtered_1_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] _portsCOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _portsCOI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _portsCOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _portsCOI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] portsCOI_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_0_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] _portsCOI_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _portsCOI_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _portsCOI_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _portsCOI_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] portsCOI_filtered_1_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_0_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] _out_0_a_bits_T_19 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_0_a_bits_T_22 = 3'h0; // @[Mux.scala:30:73] wire [3:0] auto_anon_in_1_a_bits_size = 4'h2; // @[Xbar.scala:74:9] wire [3:0] anonIn_1_a_bits_size = 4'h2; // @[MixedNode.scala:551:17] wire [3:0] in_1_a_bits_size = 4'h2; // @[Xbar.scala:159:18] wire [3:0] portsAOI_filtered_1_0_bits_size = 4'h2; // @[Xbar.scala:352:24] wire auto_anon_in_1_a_bits_source = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_in_1_a_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_bits_source = 1'h0; // @[Xbar.scala:74:9] wire anonIn_1_a_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_1_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_1_d_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire in_1_a_bits_corrupt = 1'h0; // @[Xbar.scala:159:18] wire _addressC_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _requestBOI_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_T = 1'h0; // @[Parameters.scala:54:10] wire _requestBOI_WIRE_2_ready = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_2_valid = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_3_ready = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_3_valid = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire requestBOI_0_1 = 1'h0; // @[Parameters.scala:46:9] wire _requestEIO_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_2_ready = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_2_valid = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_2_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_3_ready = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_3_valid = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_3_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _beatsAI_opdata_T_1 = 1'h0; // @[Edges.scala:92:37] wire _beatsBO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_opdata_T = 1'h0; // @[Edges.scala:97:37] wire _beatsCI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire beatsCI_opdata = 1'h0; // @[Edges.scala:102:36] wire _beatsCI_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire beatsCI_opdata_1 = 1'h0; // @[Edges.scala:102:36] wire _beatsEI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _beatsEI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _beatsEI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _beatsEI_WIRE_2_ready = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_2_valid = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_2_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_3_ready = 1'h0; // @[Bundles.scala:267:61] wire _beatsEI_WIRE_3_valid = 1'h0; // @[Bundles.scala:267:61] wire _beatsEI_WIRE_3_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire portsAOI_filtered_1_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsBIO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire portsBIO_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_ready = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_valid = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsBIO_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsBIO_filtered_1_valid_T = 1'h0; // @[Xbar.scala:355:54] wire _portsBIO_filtered_1_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsBIO_T = 1'h0; // @[Mux.scala:30:73] wire _portsBIO_T_1 = 1'h0; // @[Mux.scala:30:73] wire _portsBIO_T_2 = 1'h0; // @[Mux.scala:30:73] wire _portsBIO_WIRE_2 = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire portsCOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsCOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsCOI_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire portsCOI_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsCOI_filtered_0_valid_T_3 = 1'h0; // @[Xbar.scala:355:40] wire _portsEOI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _portsEOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _portsEOI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire portsEOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_0_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire _portsEOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsEOI_WIRE_2_ready = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_2_valid = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_2_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_3_ready = 1'h0; // @[Bundles.scala:267:61] wire _portsEOI_WIRE_3_valid = 1'h0; // @[Bundles.scala:267:61] wire _portsEOI_WIRE_3_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire portsEOI_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_0_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire _portsEOI_filtered_0_valid_T_3 = 1'h0; // @[Xbar.scala:355:40] wire _state_WIRE_0 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_1 = 1'h0; // @[Arbiter.scala:88:34] wire _out_0_a_bits_T_1 = 1'h0; // @[Mux.scala:30:73] wire [7:0] auto_anon_in_1_a_bits_mask = 8'hF; // @[Xbar.scala:74:9] wire [7:0] anonIn_1_a_bits_mask = 8'hF; // @[MixedNode.scala:551:17] wire [7:0] in_1_a_bits_mask = 8'hF; // @[Xbar.scala:159:18] wire [7:0] portsAOI_filtered_1_0_bits_mask = 8'hF; // @[Xbar.scala:352:24] wire auto_anon_in_1_d_ready = 1'h1; // @[Xbar.scala:74:9] wire anonIn_1_d_ready = 1'h1; // @[MixedNode.scala:551:17] wire in_1_d_ready = 1'h1; // @[Xbar.scala:159:18] wire _requestAIO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire requestAIO_0_0 = 1'h1; // @[Xbar.scala:307:107] wire _requestAIO_T_9 = 1'h1; // @[Parameters.scala:137:59] wire requestAIO_1_0 = 1'h1; // @[Xbar.scala:307:107] wire _requestCIO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_0_0 = 1'h1; // @[Xbar.scala:308:107] wire _requestCIO_T_9 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_1_0 = 1'h1; // @[Xbar.scala:308:107] wire _requestBOI_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _requestBOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _requestBOI_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _requestBOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire requestBOI_0_0 = 1'h1; // @[Parameters.scala:56:48] wire _requestDOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _requestDOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire beatsAI_opdata_1 = 1'h1; // @[Edges.scala:92:28] wire beatsBO_opdata = 1'h1; // @[Edges.scala:97:28] wire _portsAOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsAOI_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire _portsBIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire portsDIO_filtered_1_ready = 1'h1; // @[Xbar.scala:352:24] wire _portsEOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsEOI_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire [8:0] requestBOI_uncommonBits = 9'h0; // @[Parameters.scala:52:56] wire [8:0] beatsAI_decode_1 = 9'h0; // @[Edges.scala:220:59] wire [8:0] beatsAI_1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] beatsBO_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] beatsBO_0 = 9'h0; // @[Edges.scala:221:14] wire [8:0] beatsCI_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] beatsCI_0 = 9'h0; // @[Edges.scala:221:14] wire [8:0] beatsCI_decode_1 = 9'h0; // @[Edges.scala:220:59] wire [8:0] beatsCI_1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] maskedBeats_1 = 9'h0; // @[Arbiter.scala:82:69] wire [63:0] _addressC_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _addressC_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _addressC_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _addressC_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _requestBOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _requestBOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _requestBOI_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _requestBOI_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _beatsBO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _beatsBO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _beatsCI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _beatsCI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _beatsCI_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _beatsCI_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _portsBIO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _portsBIO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] portsBIO_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] portsBIO_filtered_1_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] _portsCOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _portsCOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] portsCOI_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] _portsCOI_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _portsCOI_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] portsCOI_filtered_1_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [28:0] _addressC_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _addressC_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _addressC_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _addressC_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _requestCIO_T = 29'h0; // @[Parameters.scala:137:31] wire [28:0] _requestCIO_T_5 = 29'h0; // @[Parameters.scala:137:31] wire [28:0] _requestBOI_WIRE_bits_address = 29'h0; // @[Bundles.scala:264:74] wire [28:0] _requestBOI_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:264:61] wire [28:0] _requestBOI_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:264:74] wire [28:0] _requestBOI_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:264:61] wire [28:0] _beatsBO_WIRE_bits_address = 29'h0; // @[Bundles.scala:264:74] wire [28:0] _beatsBO_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:264:61] wire [28:0] _beatsCI_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _beatsCI_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _beatsCI_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _beatsCI_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _portsBIO_WIRE_bits_address = 29'h0; // @[Bundles.scala:264:74] wire [28:0] _portsBIO_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:264:61] wire [28:0] portsBIO_filtered_0_bits_address = 29'h0; // @[Xbar.scala:352:24] wire [28:0] portsBIO_filtered_1_bits_address = 29'h0; // @[Xbar.scala:352:24] wire [28:0] _portsCOI_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _portsCOI_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] portsCOI_filtered_0_bits_address = 29'h0; // @[Xbar.scala:352:24] wire [28:0] _portsCOI_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _portsCOI_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] portsCOI_filtered_1_0_bits_address = 29'h0; // @[Xbar.scala:352:24] wire [9:0] _addressC_WIRE_bits_source = 10'h0; // @[Bundles.scala:265:74] wire [9:0] _addressC_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:265:61] wire [9:0] _addressC_WIRE_2_bits_source = 10'h0; // @[Bundles.scala:265:74] wire [9:0] _addressC_WIRE_3_bits_source = 10'h0; // @[Bundles.scala:265:61] wire [9:0] _requestBOI_WIRE_bits_source = 10'h0; // @[Bundles.scala:264:74] wire [9:0] _requestBOI_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:264:61] wire [9:0] _requestBOI_uncommonBits_T = 10'h0; // @[Parameters.scala:52:29] wire [9:0] _requestBOI_WIRE_2_bits_source = 10'h0; // @[Bundles.scala:264:74] wire [9:0] _requestBOI_WIRE_3_bits_source = 10'h0; // @[Bundles.scala:264:61] wire [9:0] _beatsBO_WIRE_bits_source = 10'h0; // @[Bundles.scala:264:74] wire [9:0] _beatsBO_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:264:61] wire [9:0] _beatsCI_WIRE_bits_source = 10'h0; // @[Bundles.scala:265:74] wire [9:0] _beatsCI_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:265:61] wire [9:0] _beatsCI_WIRE_2_bits_source = 10'h0; // @[Bundles.scala:265:74] wire [9:0] _beatsCI_WIRE_3_bits_source = 10'h0; // @[Bundles.scala:265:61] wire [9:0] _portsBIO_WIRE_bits_source = 10'h0; // @[Bundles.scala:264:74] wire [9:0] _portsBIO_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:264:61] wire [9:0] portsBIO_filtered_0_bits_source = 10'h0; // @[Xbar.scala:352:24] wire [9:0] portsBIO_filtered_1_bits_source = 10'h0; // @[Xbar.scala:352:24] wire [9:0] _portsCOI_WIRE_bits_source = 10'h0; // @[Bundles.scala:265:74] wire [9:0] _portsCOI_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:265:61] wire [9:0] portsCOI_filtered_0_bits_source = 10'h0; // @[Xbar.scala:352:24] wire [9:0] _portsCOI_WIRE_2_bits_source = 10'h0; // @[Bundles.scala:265:74] wire [9:0] _portsCOI_WIRE_3_bits_source = 10'h0; // @[Bundles.scala:265:61] wire [9:0] portsCOI_filtered_1_0_bits_source = 10'h0; // @[Xbar.scala:352:24] wire [3:0] _addressC_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _addressC_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _addressC_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _addressC_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _requestBOI_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _requestBOI_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _requestBOI_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _requestBOI_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _beatsBO_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _beatsBO_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _beatsCI_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _beatsCI_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _beatsCI_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _beatsCI_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _portsBIO_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _portsBIO_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] portsBIO_filtered_0_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [3:0] portsBIO_filtered_1_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [3:0] _portsCOI_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _portsCOI_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] portsCOI_filtered_0_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [3:0] _portsCOI_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _portsCOI_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] portsCOI_filtered_1_0_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [7:0] _requestBOI_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _requestBOI_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _requestBOI_WIRE_2_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _requestBOI_WIRE_3_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _beatsBO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _beatsBO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _portsBIO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _portsBIO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] portsBIO_filtered_0_bits_mask = 8'h0; // @[Xbar.scala:352:24] wire [7:0] portsBIO_filtered_1_bits_mask = 8'h0; // @[Xbar.scala:352:24] wire [1:0] _requestBOI_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _requestBOI_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _requestBOI_WIRE_2_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _requestBOI_WIRE_3_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _beatsBO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _beatsBO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _portsBIO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _portsBIO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] portsBIO_filtered_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] portsBIO_filtered_1_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [9:0] in_1_a_bits_source = 10'h200; // @[Xbar.scala:159:18] wire [9:0] _in_1_a_bits_source_T = 10'h200; // @[Xbar.scala:166:55] wire [9:0] portsAOI_filtered_1_0_bits_source = 10'h200; // @[Xbar.scala:352:24] wire [11:0] _beatsBO_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _beatsCI_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _beatsCI_decode_T_5 = 12'h0; // @[package.scala:243:46] wire [11:0] _beatsBO_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [11:0] _beatsCI_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [11:0] _beatsCI_decode_T_4 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _beatsBO_decode_T = 27'hFFF; // @[package.scala:243:71] wire [26:0] _beatsCI_decode_T = 27'hFFF; // @[package.scala:243:71] wire [26:0] _beatsCI_decode_T_3 = 27'hFFF; // @[package.scala:243:71] wire [11:0] _beatsAI_decode_T_5 = 12'h3; // @[package.scala:243:46] wire [11:0] _beatsAI_decode_T_4 = 12'hFFC; // @[package.scala:243:76] wire [26:0] _beatsAI_decode_T_3 = 27'h3FFC; // @[package.scala:243:71] wire [29:0] _requestAIO_T_2 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] _requestAIO_T_3 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] _requestAIO_T_7 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] _requestAIO_T_8 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] _requestCIO_T_1 = 30'h0; // @[Parameters.scala:137:41] wire [29:0] _requestCIO_T_2 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] _requestCIO_T_3 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] _requestCIO_T_6 = 30'h0; // @[Parameters.scala:137:41] wire [29:0] _requestCIO_T_7 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] _requestCIO_T_8 = 30'h0; // @[Parameters.scala:137:46] wire anonIn_1_a_ready; // @[MixedNode.scala:551:17] wire anonIn_1_a_valid = auto_anon_in_1_a_valid_0; // @[Xbar.scala:74:9] wire [28:0] anonIn_1_a_bits_address = auto_anon_in_1_a_bits_address_0; // @[Xbar.scala:74:9] wire [63:0] anonIn_1_a_bits_data = auto_anon_in_1_a_bits_data_0; // @[Xbar.scala:74:9] wire anonIn_1_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_1_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] anonIn_1_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] anonIn_1_d_bits_size; // @[MixedNode.scala:551:17] wire anonIn_1_d_bits_sink; // @[MixedNode.scala:551:17] wire anonIn_1_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] anonIn_1_d_bits_data; // @[MixedNode.scala:551:17] wire anonIn_1_d_bits_corrupt; // @[MixedNode.scala:551:17] wire anonIn_a_ready; // @[MixedNode.scala:551:17] wire anonIn_a_valid = auto_anon_in_0_a_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_a_bits_opcode = auto_anon_in_0_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_a_bits_param = auto_anon_in_0_a_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] anonIn_a_bits_size = auto_anon_in_0_a_bits_size_0; // @[Xbar.scala:74:9] wire [8:0] anonIn_a_bits_source = auto_anon_in_0_a_bits_source_0; // @[Xbar.scala:74:9] wire [28:0] anonIn_a_bits_address = auto_anon_in_0_a_bits_address_0; // @[Xbar.scala:74:9] wire [7:0] anonIn_a_bits_mask = auto_anon_in_0_a_bits_mask_0; // @[Xbar.scala:74:9] wire [63:0] anonIn_a_bits_data = auto_anon_in_0_a_bits_data_0; // @[Xbar.scala:74:9] wire anonIn_a_bits_corrupt = auto_anon_in_0_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire anonIn_d_ready = auto_anon_in_0_d_ready_0; // @[Xbar.scala:74:9] wire anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [8:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire anonOut_a_ready = auto_anon_out_a_ready_0; // @[Xbar.scala:74:9] wire anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [9:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [28:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire anonOut_d_ready; // @[MixedNode.scala:542:17] wire anonOut_d_valid = auto_anon_out_d_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonOut_d_bits_opcode = auto_anon_out_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] anonOut_d_bits_param = auto_anon_out_d_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] anonOut_d_bits_size = auto_anon_out_d_bits_size_0; // @[Xbar.scala:74:9] wire [9:0] anonOut_d_bits_source = auto_anon_out_d_bits_source_0; // @[Xbar.scala:74:9] wire anonOut_d_bits_sink = auto_anon_out_d_bits_sink_0; // @[Xbar.scala:74:9] wire anonOut_d_bits_denied = auto_anon_out_d_bits_denied_0; // @[Xbar.scala:74:9] wire [63:0] anonOut_d_bits_data = auto_anon_out_d_bits_data_0; // @[Xbar.scala:74:9] wire anonOut_d_bits_corrupt = auto_anon_out_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_a_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_1_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_1_d_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_1_d_bits_size_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_bits_sink_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_bits_denied_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_in_1_d_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_valid_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_a_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_0_d_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_0_d_bits_size_0; // @[Xbar.scala:74:9] wire [8:0] auto_anon_in_0_d_bits_source_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_bits_sink_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_bits_denied_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_in_0_d_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_valid_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_a_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_out_a_bits_size_0; // @[Xbar.scala:74:9] wire [9:0] auto_anon_out_a_bits_source_0; // @[Xbar.scala:74:9] wire [28:0] auto_anon_out_a_bits_address_0; // @[Xbar.scala:74:9] wire [7:0] auto_anon_out_a_bits_mask_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_a_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_out_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_out_a_valid_0; // @[Xbar.scala:74:9] wire auto_anon_out_d_ready_0; // @[Xbar.scala:74:9] wire in_0_a_ready; // @[Xbar.scala:159:18] assign auto_anon_in_0_a_ready_0 = anonIn_a_ready; // @[Xbar.scala:74:9] wire in_0_a_valid = anonIn_a_valid; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_opcode = anonIn_a_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_param = anonIn_a_bits_param; // @[Xbar.scala:159:18] wire [3:0] in_0_a_bits_size = anonIn_a_bits_size; // @[Xbar.scala:159:18] wire [8:0] _in_0_a_bits_source_T = anonIn_a_bits_source; // @[Xbar.scala:166:55] wire [28:0] in_0_a_bits_address = anonIn_a_bits_address; // @[Xbar.scala:159:18] wire [7:0] in_0_a_bits_mask = anonIn_a_bits_mask; // @[Xbar.scala:159:18] wire [63:0] in_0_a_bits_data = anonIn_a_bits_data; // @[Xbar.scala:159:18] wire in_0_a_bits_corrupt = anonIn_a_bits_corrupt; // @[Xbar.scala:159:18] wire in_0_d_ready = anonIn_d_ready; // @[Xbar.scala:159:18] wire in_0_d_valid; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_valid_0 = anonIn_d_valid; // @[Xbar.scala:74:9] wire [2:0] in_0_d_bits_opcode; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] in_0_d_bits_param; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_param_0 = anonIn_d_bits_param; // @[Xbar.scala:74:9] wire [3:0] in_0_d_bits_size; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_size_0 = anonIn_d_bits_size; // @[Xbar.scala:74:9] wire [8:0] _anonIn_d_bits_source_T; // @[Xbar.scala:156:69] assign auto_anon_in_0_d_bits_source_0 = anonIn_d_bits_source; // @[Xbar.scala:74:9] wire in_0_d_bits_sink; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_sink_0 = anonIn_d_bits_sink; // @[Xbar.scala:74:9] wire in_0_d_bits_denied; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_denied_0 = anonIn_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] in_0_d_bits_data; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_data_0 = anonIn_d_bits_data; // @[Xbar.scala:74:9] wire in_0_d_bits_corrupt; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_corrupt_0 = anonIn_d_bits_corrupt; // @[Xbar.scala:74:9] wire in_1_a_ready; // @[Xbar.scala:159:18] assign auto_anon_in_1_a_ready_0 = anonIn_1_a_ready; // @[Xbar.scala:74:9] wire in_1_a_valid = anonIn_1_a_valid; // @[Xbar.scala:159:18] wire [28:0] in_1_a_bits_address = anonIn_1_a_bits_address; // @[Xbar.scala:159:18] wire [63:0] in_1_a_bits_data = anonIn_1_a_bits_data; // @[Xbar.scala:159:18] wire in_1_d_valid; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_valid_0 = anonIn_1_d_valid; // @[Xbar.scala:74:9] wire [2:0] in_1_d_bits_opcode; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_opcode_0 = anonIn_1_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] in_1_d_bits_param; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_param_0 = anonIn_1_d_bits_param; // @[Xbar.scala:74:9] wire [3:0] in_1_d_bits_size; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_size_0 = anonIn_1_d_bits_size; // @[Xbar.scala:74:9] wire in_1_d_bits_sink; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_sink_0 = anonIn_1_d_bits_sink; // @[Xbar.scala:74:9] wire in_1_d_bits_denied; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_denied_0 = anonIn_1_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] in_1_d_bits_data; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_data_0 = anonIn_1_d_bits_data; // @[Xbar.scala:74:9] wire in_1_d_bits_corrupt; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_corrupt_0 = anonIn_1_d_bits_corrupt; // @[Xbar.scala:74:9] wire out_0_a_ready = anonOut_a_ready; // @[Xbar.scala:216:19] wire out_0_a_valid; // @[Xbar.scala:216:19] assign auto_anon_out_a_valid_0 = anonOut_a_valid; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_opcode; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_param; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_param_0 = anonOut_a_bits_param; // @[Xbar.scala:74:9] wire [3:0] out_0_a_bits_size; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size; // @[Xbar.scala:74:9] wire [9:0] out_0_a_bits_source; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_source_0 = anonOut_a_bits_source; // @[Xbar.scala:74:9] wire [28:0] out_0_a_bits_address; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] out_0_a_bits_mask; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] out_0_a_bits_data; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data; // @[Xbar.scala:74:9] wire out_0_a_bits_corrupt; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[Xbar.scala:74:9] wire out_0_d_ready; // @[Xbar.scala:216:19] assign auto_anon_out_d_ready_0 = anonOut_d_ready; // @[Xbar.scala:74:9] wire out_0_d_valid = anonOut_d_valid; // @[Xbar.scala:216:19] wire [2:0] out_0_d_bits_opcode = anonOut_d_bits_opcode; // @[Xbar.scala:216:19] wire [1:0] out_0_d_bits_param = anonOut_d_bits_param; // @[Xbar.scala:216:19] wire [3:0] out_0_d_bits_size = anonOut_d_bits_size; // @[Xbar.scala:216:19] wire [9:0] out_0_d_bits_source = anonOut_d_bits_source; // @[Xbar.scala:216:19] wire _out_0_d_bits_sink_T = anonOut_d_bits_sink; // @[Xbar.scala:251:53] wire out_0_d_bits_denied = anonOut_d_bits_denied; // @[Xbar.scala:216:19] wire [63:0] out_0_d_bits_data = anonOut_d_bits_data; // @[Xbar.scala:216:19] wire out_0_d_bits_corrupt = anonOut_d_bits_corrupt; // @[Xbar.scala:216:19] wire portsAOI_filtered_0_ready; // @[Xbar.scala:352:24] assign anonIn_a_ready = in_0_a_ready; // @[Xbar.scala:159:18] wire _portsAOI_filtered_0_valid_T_1 = in_0_a_valid; // @[Xbar.scala:159:18, :355:40] wire [2:0] portsAOI_filtered_0_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_0_bits_param = in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsAOI_filtered_0_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [9:0] portsAOI_filtered_0_bits_source = in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [28:0] _requestAIO_T = in_0_a_bits_address; // @[Xbar.scala:159:18] wire [28:0] portsAOI_filtered_0_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [7:0] portsAOI_filtered_0_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [63:0] portsAOI_filtered_0_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_0_bits_corrupt = in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire portsDIO_filtered_0_ready = in_0_d_ready; // @[Xbar.scala:159:18, :352:24] wire portsDIO_filtered_0_valid; // @[Xbar.scala:352:24] assign anonIn_d_valid = in_0_d_valid; // @[Xbar.scala:159:18] wire [2:0] portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:352:24] assign anonIn_d_bits_opcode = in_0_d_bits_opcode; // @[Xbar.scala:159:18] wire [1:0] portsDIO_filtered_0_bits_param; // @[Xbar.scala:352:24] assign anonIn_d_bits_param = in_0_d_bits_param; // @[Xbar.scala:159:18] wire [3:0] portsDIO_filtered_0_bits_size; // @[Xbar.scala:352:24] assign anonIn_d_bits_size = in_0_d_bits_size; // @[Xbar.scala:159:18] wire [9:0] portsDIO_filtered_0_bits_source; // @[Xbar.scala:352:24] wire portsDIO_filtered_0_bits_sink; // @[Xbar.scala:352:24] assign anonIn_d_bits_sink = in_0_d_bits_sink; // @[Xbar.scala:159:18] wire portsDIO_filtered_0_bits_denied; // @[Xbar.scala:352:24] assign anonIn_d_bits_denied = in_0_d_bits_denied; // @[Xbar.scala:159:18] wire [63:0] portsDIO_filtered_0_bits_data; // @[Xbar.scala:352:24] assign anonIn_d_bits_data = in_0_d_bits_data; // @[Xbar.scala:159:18] wire portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:352:24] assign anonIn_d_bits_corrupt = in_0_d_bits_corrupt; // @[Xbar.scala:159:18] wire portsAOI_filtered_1_0_ready; // @[Xbar.scala:352:24] assign anonIn_1_a_ready = in_1_a_ready; // @[Xbar.scala:159:18] wire _portsAOI_filtered_0_valid_T_3 = in_1_a_valid; // @[Xbar.scala:159:18, :355:40] wire [28:0] _requestAIO_T_5 = in_1_a_bits_address; // @[Xbar.scala:159:18] wire [28:0] portsAOI_filtered_1_0_bits_address = in_1_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [63:0] portsAOI_filtered_1_0_bits_data = in_1_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire portsDIO_filtered_1_valid; // @[Xbar.scala:352:24] assign anonIn_1_d_valid = in_1_d_valid; // @[Xbar.scala:159:18] wire [2:0] portsDIO_filtered_1_bits_opcode; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_opcode = in_1_d_bits_opcode; // @[Xbar.scala:159:18] wire [1:0] portsDIO_filtered_1_bits_param; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_param = in_1_d_bits_param; // @[Xbar.scala:159:18] wire [3:0] portsDIO_filtered_1_bits_size; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_size = in_1_d_bits_size; // @[Xbar.scala:159:18] wire [9:0] portsDIO_filtered_1_bits_source; // @[Xbar.scala:352:24] wire portsDIO_filtered_1_bits_sink; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_sink = in_1_d_bits_sink; // @[Xbar.scala:159:18] wire portsDIO_filtered_1_bits_denied; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_denied = in_1_d_bits_denied; // @[Xbar.scala:159:18] wire [63:0] portsDIO_filtered_1_bits_data; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_data = in_1_d_bits_data; // @[Xbar.scala:159:18] wire portsDIO_filtered_1_bits_corrupt; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_corrupt = in_1_d_bits_corrupt; // @[Xbar.scala:159:18] wire [9:0] in_0_d_bits_source; // @[Xbar.scala:159:18] wire [9:0] in_1_d_bits_source; // @[Xbar.scala:159:18] assign in_0_a_bits_source = {1'h0, _in_0_a_bits_source_T}; // @[Xbar.scala:159:18, :166:{29,55}] assign _anonIn_d_bits_source_T = in_0_d_bits_source[8:0]; // @[Xbar.scala:156:69, :159:18] assign anonIn_d_bits_source = _anonIn_d_bits_source_T; // @[Xbar.scala:156:69] wire _out_0_a_valid_T_4; // @[Arbiter.scala:96:24] assign anonOut_a_valid = out_0_a_valid; // @[Xbar.scala:216:19] wire [2:0] _out_0_a_bits_WIRE_opcode; // @[Mux.scala:30:73] assign anonOut_a_bits_opcode = out_0_a_bits_opcode; // @[Xbar.scala:216:19] wire [2:0] _out_0_a_bits_WIRE_param; // @[Mux.scala:30:73] assign anonOut_a_bits_param = out_0_a_bits_param; // @[Xbar.scala:216:19] wire [3:0] _out_0_a_bits_WIRE_size; // @[Mux.scala:30:73] assign anonOut_a_bits_size = out_0_a_bits_size; // @[Xbar.scala:216:19] wire [9:0] _out_0_a_bits_WIRE_source; // @[Mux.scala:30:73] assign anonOut_a_bits_source = out_0_a_bits_source; // @[Xbar.scala:216:19] wire [28:0] _out_0_a_bits_WIRE_address; // @[Mux.scala:30:73] assign anonOut_a_bits_address = out_0_a_bits_address; // @[Xbar.scala:216:19] wire [7:0] _out_0_a_bits_WIRE_mask; // @[Mux.scala:30:73] assign anonOut_a_bits_mask = out_0_a_bits_mask; // @[Xbar.scala:216:19] wire [63:0] _out_0_a_bits_WIRE_data; // @[Mux.scala:30:73] assign anonOut_a_bits_data = out_0_a_bits_data; // @[Xbar.scala:216:19] wire _out_0_a_bits_WIRE_corrupt; // @[Mux.scala:30:73] assign anonOut_a_bits_corrupt = out_0_a_bits_corrupt; // @[Xbar.scala:216:19] wire _portsDIO_out_0_d_ready_WIRE; // @[Mux.scala:30:73] assign anonOut_d_ready = out_0_d_ready; // @[Xbar.scala:216:19] assign portsDIO_filtered_0_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_0_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_0_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [9:0] _requestDOI_uncommonBits_T = out_0_d_bits_source; // @[Xbar.scala:216:19] assign portsDIO_filtered_0_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_0_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_0_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_0_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_0_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] assign out_0_d_bits_sink = _out_0_d_bits_sink_T; // @[Xbar.scala:216:19, :251:53] wire [29:0] _requestAIO_T_1 = {1'h0, _requestAIO_T}; // @[Parameters.scala:137:{31,41}] wire [29:0] _requestAIO_T_6 = {1'h0, _requestAIO_T_5}; // @[Parameters.scala:137:{31,41}] wire [8:0] requestDOI_uncommonBits = _requestDOI_uncommonBits_T[8:0]; // @[Parameters.scala:52:{29,56}] wire _requestDOI_T = out_0_d_bits_source[9]; // @[Xbar.scala:216:19] wire _requestDOI_T_1 = ~_requestDOI_T; // @[Parameters.scala:54:{10,32}] wire _requestDOI_T_3 = _requestDOI_T_1; // @[Parameters.scala:54:{32,67}] wire requestDOI_0_0 = _requestDOI_T_3; // @[Parameters.scala:54:67, :56:48] wire _portsDIO_filtered_0_valid_T = requestDOI_0_0; // @[Xbar.scala:355:54] wire requestDOI_0_1 = out_0_d_bits_source == 10'h200; // @[Xbar.scala:216:19] wire _portsDIO_filtered_1_valid_T = requestDOI_0_1; // @[Xbar.scala:355:54] wire _portsDIO_out_0_d_ready_T_1 = requestDOI_0_1; // @[Mux.scala:30:73] wire [26:0] _beatsAI_decode_T = 27'hFFF << in_0_a_bits_size; // @[package.scala:243:71] wire [11:0] _beatsAI_decode_T_1 = _beatsAI_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _beatsAI_decode_T_2 = ~_beatsAI_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] beatsAI_decode = _beatsAI_decode_T_2[11:3]; // @[package.scala:243:46] wire _beatsAI_opdata_T = in_0_a_bits_opcode[2]; // @[Xbar.scala:159:18] wire beatsAI_opdata = ~_beatsAI_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] beatsAI_0 = beatsAI_opdata ? beatsAI_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] wire [26:0] _beatsDO_decode_T = 27'hFFF << out_0_d_bits_size; // @[package.scala:243:71] wire [11:0] _beatsDO_decode_T_1 = _beatsDO_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _beatsDO_decode_T_2 = ~_beatsDO_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] beatsDO_decode = _beatsDO_decode_T_2[11:3]; // @[package.scala:243:46] wire beatsDO_opdata = out_0_d_bits_opcode[0]; // @[Xbar.scala:216:19] wire [8:0] beatsDO_0 = beatsDO_opdata ? beatsDO_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] wire _filtered_0_ready_T; // @[Arbiter.scala:94:31] assign in_0_a_ready = portsAOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_0_valid; // @[Xbar.scala:352:24] assign portsAOI_filtered_0_valid = _portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire _filtered_0_ready_T_1; // @[Arbiter.scala:94:31] assign in_1_a_ready = portsAOI_filtered_1_0_ready; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24] assign portsAOI_filtered_1_0_valid = _portsAOI_filtered_0_valid_T_3; // @[Xbar.scala:352:24, :355:40] wire _portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:355:40] assign in_0_d_valid = portsDIO_filtered_0_valid; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_opcode = portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_param = portsDIO_filtered_0_bits_param; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_size = portsDIO_filtered_0_bits_size; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_source = portsDIO_filtered_0_bits_source; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_sink = portsDIO_filtered_0_bits_sink; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_denied = portsDIO_filtered_0_bits_denied; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_data = portsDIO_filtered_0_bits_data; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_corrupt = portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire _portsDIO_filtered_1_valid_T_1; // @[Xbar.scala:355:40] assign in_1_d_valid = portsDIO_filtered_1_valid; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_opcode = portsDIO_filtered_1_bits_opcode; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_param = portsDIO_filtered_1_bits_param; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_size = portsDIO_filtered_1_bits_size; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_source = portsDIO_filtered_1_bits_source; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_sink = portsDIO_filtered_1_bits_sink; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_denied = portsDIO_filtered_1_bits_denied; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_data = portsDIO_filtered_1_bits_data; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_corrupt = portsDIO_filtered_1_bits_corrupt; // @[Xbar.scala:159:18, :352:24] assign _portsDIO_filtered_0_valid_T_1 = out_0_d_valid & _portsDIO_filtered_0_valid_T; // @[Xbar.scala:216:19, :355:{40,54}] assign portsDIO_filtered_0_valid = _portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign _portsDIO_filtered_1_valid_T_1 = out_0_d_valid & _portsDIO_filtered_1_valid_T; // @[Xbar.scala:216:19, :355:{40,54}] assign portsDIO_filtered_1_valid = _portsDIO_filtered_1_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire _portsDIO_out_0_d_ready_T = requestDOI_0_0 & portsDIO_filtered_0_ready; // @[Mux.scala:30:73] wire _portsDIO_out_0_d_ready_T_2 = _portsDIO_out_0_d_ready_T \| _portsDIO_out_0_d_ready_T_1; // @[Mux.scala:30:73] assign _portsDIO_out_0_d_ready_WIRE = _portsDIO_out_0_d_ready_T_2; // @[Mux.scala:30:73] assign out_0_d_ready = _portsDIO_out_0_d_ready_WIRE; // @[Mux.scala:30:73] reg [8:0] beatsLeft; // @[Arbiter.scala:60:30] wire idle = beatsLeft == 9'h0; // @[Arbiter.scala:60:30, :61:28] wire latch = idle & out_0_a_ready; // @[Xbar.scala:216:19] wire [1:0] _readys_T = {portsAOI_filtered_1_0_valid, portsAOI_filtered_0_valid}; // @[Xbar.scala:352:24] wire [1:0] readys_valid = _readys_T; // @[Arbiter.scala:21:23, :68:51] wire _readys_T_1 = readys_valid == _readys_T; // @[Arbiter.scala:21:23, :22:19, :68:51] wire _readys_T_3 = ~_readys_T_2; // @[Arbiter.scala:22:12] wire _readys_T_4 = ~_readys_T_1; // @[Arbiter.scala:22:{12,19}] reg [1:0] readys_mask; // @[Arbiter.scala:23:23] wire [1:0] _readys_filter_T = ~readys_mask; // @[Arbiter.scala:23:23, :24:30] wire [1:0] _readys_filter_T_1 = readys_valid & _readys_filter_T; // @[Arbiter.scala:21:23, :24:{28,30}] wire [3:0] readys_filter = {_readys_filter_T_1, readys_valid}; // @[Arbiter.scala:21:23, :24:{21,28}] wire [2:0] _readys_unready_T = readys_filter[3:1]; // @[package.scala:262:48] wire [3:0] _readys_unready_T_1 = {readys_filter[3], readys_filter[2:0] \| _readys_unready_T}; // @[package.scala:262:{43,48}] wire [3:0] _readys_unready_T_2 = _readys_unready_T_1; // @[package.scala:262:43, :263:17] wire [2:0] _readys_unready_T_3 = _readys_unready_T_2[3:1]; // @[package.scala:263:17] wire [3:0] _readys_unready_T_4 = {readys_mask, 2'h0}; // @[Arbiter.scala:23:23, :25:66] wire [3:0] readys_unready = {1'h0, _readys_unready_T_3} \| _readys_unready_T_4; // @[Arbiter.scala:25:{52,58,66}] wire [1:0] _readys_readys_T = readys_unready[3:2]; // @[Arbiter.scala:25:58, :26:29] wire [1:0] _readys_readys_T_1 = readys_unready[1:0]; // @[Arbiter.scala:25:58, :26:48] wire [1:0] _readys_readys_T_2 = _readys_readys_T & _readys_readys_T_1; // @[Arbiter.scala:26:{29,39,48}] wire [1:0] readys_readys = ~_readys_readys_T_2; // @[Arbiter.scala:26:{18,39}] wire [1:0] _readys_T_7 = readys_readys; // @[Arbiter.scala:26:18, :30:11] wire _readys_T_5 = \|readys_valid; // @[Arbiter.scala:21:23, :27:27] wire _readys_T_6 = latch & _readys_T_5; // @[Arbiter.scala:27:{18,27}, :62:24] wire [1:0] _readys_mask_T = readys_readys & readys_valid; // @[Arbiter.scala:21:23, :26:18, :28:29] wire [2:0] _readys_mask_T_1 = {_readys_mask_T, 1'h0}; // @[package.scala:253:48] wire [1:0] _readys_mask_T_2 = _readys_mask_T_1[1:0]; // @[package.scala:253:{48,53}] wire [1:0] _readys_mask_T_3 = _readys_mask_T \| _readys_mask_T_2; // @[package.scala:253:{43,53}] wire [1:0] _readys_mask_T_4 = _readys_mask_T_3; // @[package.scala:253:43, :254:17] wire _readys_T_8 = _readys_T_7[0]; // @[Arbiter.scala:30:11, :68:76] wire readys_0 = _readys_T_8; // @[Arbiter.scala:68:{27,76}] wire _readys_T_9 = _readys_T_7[1]; // @[Arbiter.scala:30:11, :68:76] wire readys_1 = _readys_T_9; // @[Arbiter.scala:68:{27,76}] wire _winner_T = readys_0 & portsAOI_filtered_0_valid; // @[Xbar.scala:352:24] wire winner_0 = _winner_T; // @[Arbiter.scala:71:{27,69}] wire _winner_T_1 = readys_1 & portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24] wire winner_1 = _winner_T_1; // @[Arbiter.scala:71:{27,69}] wire prefixOR_1 = winner_0; // @[Arbiter.scala:71:27, :76:48] wire _prefixOR_T = prefixOR_1 \| winner_1; // @[Arbiter.scala:71:27, :76:48] wire _out_0_a_valid_T = portsAOI_filtered_0_valid \| portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24]
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerShiftReg_w4_d3_i0_32( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input [3:0] io_d, // @[ShiftReg.scala:36:14] output [3:0] io_q // @[ShiftReg.scala:36:14] ); wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21] wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14] wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7] wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_1; // @[ShiftReg.scala:48:24] wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_2; // @[ShiftReg.scala:48:24] wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_3; // @[ShiftReg.scala:48:24] wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14] wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14] assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14] assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_297 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_298 output_chain_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_2), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_3), // @[SynchronizerReg.scala:87:41] .io_q (output_1) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_299 output_chain_2 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_4), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_5), // @[SynchronizerReg.scala:87:41] .io_q (output_2) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_300 output_chain_3 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_6), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_7), // @[SynchronizerReg.scala:87:41] .io_q (output_3) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File INToRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import consts._ class INToRecFN(intWidth: Int, expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"INToRecFN_i${intWidth}_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val signedIn = Input(Bool()) val in = Input(Bits(intWidth.W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val intAsRawFloat = rawFloatFromIN(io.signedIn, io.in); val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( intAsRawFloat.expWidth, intWidth, expWidth, sigWidth, flRoundOpt_sigMSBitAlwaysZero \| flRoundOpt_neverUnderflows )) roundAnyRawFNToRecFN.io.invalidExc := false.B roundAnyRawFNToRecFN.io.infiniteExc := false.B roundAnyRawFNToRecFN.io.in := intAsRawFloat roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags } File rawFloatFromIN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util._ object rawFloatFromIN { def apply(signedIn: Bool, in: Bits): RawFloat = { val expWidth = log2Up(in.getWidth) + 1 //*** CHANGE THIS; CAN BE VERY LARGE: val extIntWidth = 1<<(expWidth - 1) val sign = signedIn && in(in.getWidth - 1) val absIn = Mux(sign, -in.asUInt, in.asUInt) val extAbsIn = (0.U(extIntWidth.W) ## absIn)(extIntWidth - 1, 0) val adjustedNormDist = countLeadingZeros(extAbsIn) val sig = (extAbsIn<<adjustedNormDist)( extIntWidth - 1, extIntWidth - in.getWidth) val out = Wire(new RawFloat(expWidth, in.getWidth)) out.isNaN := false.B out.isInf := false.B out.isZero := ! sig(in.getWidth - 1) out.sign := sign out.sExp := (2.U(2.W) ## ~adjustedNormDist(expWidth - 2, 0)).zext out.sig := sig out } }	module INToRecFN_i64_e8_s24_3( // @[INToRecFN.scala:43:7] input io_signedIn, // @[INToRecFN.scala:46:16] input [63:0] io_in, // @[INToRecFN.scala:46:16] input [2:0] io_roundingMode, // @[INToRecFN.scala:46:16] output [32:0] io_out, // @[INToRecFN.scala:46:16] output [4:0] io_exceptionFlags // @[INToRecFN.scala:46:16] ); wire io_signedIn_0 = io_signedIn; // @[INToRecFN.scala:43:7] wire [63:0] io_in_0 = io_in; // @[INToRecFN.scala:43:7] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[INToRecFN.scala:43:7] wire intAsRawFloat_isNaN = 1'h0; // @[rawFloatFromIN.scala:59:23] wire intAsRawFloat_isInf = 1'h0; // @[rawFloatFromIN.scala:59:23] wire io_detectTininess = 1'h1; // @[INToRecFN.scala:43:7] wire [32:0] io_out_0; // @[INToRecFN.scala:43:7] wire [4:0] io_exceptionFlags_0; // @[INToRecFN.scala:43:7] wire _intAsRawFloat_sign_T = io_in_0[63]; // @[rawFloatFromIN.scala:51:34] wire intAsRawFloat_sign = io_signedIn_0 & _intAsRawFloat_sign_T; // @[rawFloatFromIN.scala:51:{29,34}] wire intAsRawFloat_sign_0 = intAsRawFloat_sign; // @[rawFloatFromIN.scala:51:29, :59:23] wire [64:0] _intAsRawFloat_absIn_T = 65'h0 - {1'h0, io_in_0}; // @[rawFloatFromIN.scala:52:31] wire [63:0] _intAsRawFloat_absIn_T_1 = _intAsRawFloat_absIn_T[63:0]; // @[rawFloatFromIN.scala:52:31] wire [63:0] intAsRawFloat_absIn = intAsRawFloat_sign ? _intAsRawFloat_absIn_T_1 : io_in_0; // @[rawFloatFromIN.scala:51:29, :52:{24,31}] wire [127:0] _intAsRawFloat_extAbsIn_T = {64'h0, intAsRawFloat_absIn}; // @[rawFloatFromIN.scala:52:24, :53:44] wire [63:0] intAsRawFloat_extAbsIn = _intAsRawFloat_extAbsIn_T[63:0]; // @[rawFloatFromIN.scala:53:{44,53}] wire _intAsRawFloat_adjustedNormDist_T = intAsRawFloat_extAbsIn[0]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_1 = intAsRawFloat_extAbsIn[1]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_2 = intAsRawFloat_extAbsIn[2]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_3 = intAsRawFloat_extAbsIn[3]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_4 = intAsRawFloat_extAbsIn[4]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_5 = intAsRawFloat_extAbsIn[5]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_6 = intAsRawFloat_extAbsIn[6]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_7 = intAsRawFloat_extAbsIn[7]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_8 = intAsRawFloat_extAbsIn[8]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_9 = intAsRawFloat_extAbsIn[9]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_10 = intAsRawFloat_extAbsIn[10]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_11 = intAsRawFloat_extAbsIn[11]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_12 = intAsRawFloat_extAbsIn[12]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_13 = intAsRawFloat_extAbsIn[13]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_14 = intAsRawFloat_extAbsIn[14]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_15 = intAsRawFloat_extAbsIn[15]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_16 = intAsRawFloat_extAbsIn[16]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_17 = intAsRawFloat_extAbsIn[17]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_18 = intAsRawFloat_extAbsIn[18]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_19 = intAsRawFloat_extAbsIn[19]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_20 = intAsRawFloat_extAbsIn[20]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_21 = intAsRawFloat_extAbsIn[21]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_22 = intAsRawFloat_extAbsIn[22]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_23 = intAsRawFloat_extAbsIn[23]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_24 = intAsRawFloat_extAbsIn[24]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_25 = intAsRawFloat_extAbsIn[25]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_26 = intAsRawFloat_extAbsIn[26]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_27 = intAsRawFloat_extAbsIn[27]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_28 = intAsRawFloat_extAbsIn[28]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_29 = intAsRawFloat_extAbsIn[29]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_30 = intAsRawFloat_extAbsIn[30]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_31 = intAsRawFloat_extAbsIn[31]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_32 = intAsRawFloat_extAbsIn[32]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_33 = intAsRawFloat_extAbsIn[33]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_34 = intAsRawFloat_extAbsIn[34]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_35 = intAsRawFloat_extAbsIn[35]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_36 = intAsRawFloat_extAbsIn[36]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_37 = intAsRawFloat_extAbsIn[37]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_38 = intAsRawFloat_extAbsIn[38]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_39 = intAsRawFloat_extAbsIn[39]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_40 = intAsRawFloat_extAbsIn[40]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_41 = intAsRawFloat_extAbsIn[41]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_42 = intAsRawFloat_extAbsIn[42]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_43 = intAsRawFloat_extAbsIn[43]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_44 = intAsRawFloat_extAbsIn[44]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_45 = intAsRawFloat_extAbsIn[45]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_46 = intAsRawFloat_extAbsIn[46]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_47 = intAsRawFloat_extAbsIn[47]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_48 = intAsRawFloat_extAbsIn[48]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_49 = intAsRawFloat_extAbsIn[49]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_50 = intAsRawFloat_extAbsIn[50]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_51 = intAsRawFloat_extAbsIn[51]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_52 = intAsRawFloat_extAbsIn[52]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_53 = intAsRawFloat_extAbsIn[53]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_54 = intAsRawFloat_extAbsIn[54]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_55 = intAsRawFloat_extAbsIn[55]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_56 = intAsRawFloat_extAbsIn[56]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_57 = intAsRawFloat_extAbsIn[57]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_58 = intAsRawFloat_extAbsIn[58]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_59 = intAsRawFloat_extAbsIn[59]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_60 = intAsRawFloat_extAbsIn[60]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_61 = intAsRawFloat_extAbsIn[61]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_62 = intAsRawFloat_extAbsIn[62]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_63 = intAsRawFloat_extAbsIn[63]; // @[rawFloatFromIN.scala:53:53] wire [5:0] _intAsRawFloat_adjustedNormDist_T_64 = {5'h1F, ~_intAsRawFloat_adjustedNormDist_T_1}; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_65 = _intAsRawFloat_adjustedNormDist_T_2 ? 6'h3D : _intAsRawFloat_adjustedNormDist_T_64; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_66 = _intAsRawFloat_adjustedNormDist_T_3 ? 6'h3C : _intAsRawFloat_adjustedNormDist_T_65; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_67 = _intAsRawFloat_adjustedNormDist_T_4 ? 6'h3B : _intAsRawFloat_adjustedNormDist_T_66; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_68 = _intAsRawFloat_adjustedNormDist_T_5 ? 6'h3A : _intAsRawFloat_adjustedNormDist_T_67; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_69 = _intAsRawFloat_adjustedNormDist_T_6 ? 6'h39 : _intAsRawFloat_adjustedNormDist_T_68; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_70 = _intAsRawFloat_adjustedNormDist_T_7 ? 6'h38 : _intAsRawFloat_adjustedNormDist_T_69; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_71 = _intAsRawFloat_adjustedNormDist_T_8 ? 6'h37 : _intAsRawFloat_adjustedNormDist_T_70; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_72 = _intAsRawFloat_adjustedNormDist_T_9 ? 6'h36 : _intAsRawFloat_adjustedNormDist_T_71; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_73 = _intAsRawFloat_adjustedNormDist_T_10 ? 6'h35 : _intAsRawFloat_adjustedNormDist_T_72; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_74 = _intAsRawFloat_adjustedNormDist_T_11 ? 6'h34 : _intAsRawFloat_adjustedNormDist_T_73; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_75 = _intAsRawFloat_adjustedNormDist_T_12 ? 6'h33 : _intAsRawFloat_adjustedNormDist_T_74; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_76 = _intAsRawFloat_adjustedNormDist_T_13 ? 6'h32 : _intAsRawFloat_adjustedNormDist_T_75; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_77 = _intAsRawFloat_adjustedNormDist_T_14 ? 6'h31 : _intAsRawFloat_adjustedNormDist_T_76; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_78 = _intAsRawFloat_adjustedNormDist_T_15 ? 6'h30 : _intAsRawFloat_adjustedNormDist_T_77; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_79 = _intAsRawFloat_adjustedNormDist_T_16 ? 6'h2F : _intAsRawFloat_adjustedNormDist_T_78; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_80 = _intAsRawFloat_adjustedNormDist_T_17 ? 6'h2E : _intAsRawFloat_adjustedNormDist_T_79; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_81 = _intAsRawFloat_adjustedNormDist_T_18 ? 6'h2D : _intAsRawFloat_adjustedNormDist_T_80; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_82 = _intAsRawFloat_adjustedNormDist_T_19 ? 6'h2C : _intAsRawFloat_adjustedNormDist_T_81; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_83 = _intAsRawFloat_adjustedNormDist_T_20 ? 6'h2B : _intAsRawFloat_adjustedNormDist_T_82; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_84 = _intAsRawFloat_adjustedNormDist_T_21 ? 6'h2A : _intAsRawFloat_adjustedNormDist_T_83; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_85 = _intAsRawFloat_adjustedNormDist_T_22 ? 6'h29 : _intAsRawFloat_adjustedNormDist_T_84; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_86 = _intAsRawFloat_adjustedNormDist_T_23 ? 6'h28 : _intAsRawFloat_adjustedNormDist_T_85; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_87 = _intAsRawFloat_adjustedNormDist_T_24 ? 6'h27 : _intAsRawFloat_adjustedNormDist_T_86; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_88 = _intAsRawFloat_adjustedNormDist_T_25 ? 6'h26 : _intAsRawFloat_adjustedNormDist_T_87; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_89 = _intAsRawFloat_adjustedNormDist_T_26 ? 6'h25 : _intAsRawFloat_adjustedNormDist_T_88; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_90 = _intAsRawFloat_adjustedNormDist_T_27 ? 6'h24 : _intAsRawFloat_adjustedNormDist_T_89; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_91 = _intAsRawFloat_adjustedNormDist_T_28 ? 6'h23 : _intAsRawFloat_adjustedNormDist_T_90; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_92 = _intAsRawFloat_adjustedNormDist_T_29 ? 6'h22 : _intAsRawFloat_adjustedNormDist_T_91; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_93 = _intAsRawFloat_adjustedNormDist_T_30 ? 6'h21 : _intAsRawFloat_adjustedNormDist_T_92; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_94 = _intAsRawFloat_adjustedNormDist_T_31 ? 6'h20 : _intAsRawFloat_adjustedNormDist_T_93; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_95 = _intAsRawFloat_adjustedNormDist_T_32 ? 6'h1F : _intAsRawFloat_adjustedNormDist_T_94; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_96 = _intAsRawFloat_adjustedNormDist_T_33 ? 6'h1E : _intAsRawFloat_adjustedNormDist_T_95; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_97 = _intAsRawFloat_adjustedNormDist_T_34 ? 6'h1D : _intAsRawFloat_adjustedNormDist_T_96; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_98 = _intAsRawFloat_adjustedNormDist_T_35 ? 6'h1C : _intAsRawFloat_adjustedNormDist_T_97; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_99 = _intAsRawFloat_adjustedNormDist_T_36 ? 6'h1B : _intAsRawFloat_adjustedNormDist_T_98; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_100 = _intAsRawFloat_adjustedNormDist_T_37 ? 6'h1A : _intAsRawFloat_adjustedNormDist_T_99; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_101 = _intAsRawFloat_adjustedNormDist_T_38 ? 6'h19 : _intAsRawFloat_adjustedNormDist_T_100; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_102 = _intAsRawFloat_adjustedNormDist_T_39 ? 6'h18 : _intAsRawFloat_adjustedNormDist_T_101; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_103 = _intAsRawFloat_adjustedNormDist_T_40 ? 6'h17 : _intAsRawFloat_adjustedNormDist_T_102; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_104 = _intAsRawFloat_adjustedNormDist_T_41 ? 6'h16 : _intAsRawFloat_adjustedNormDist_T_103; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_105 = _intAsRawFloat_adjustedNormDist_T_42 ? 6'h15 : _intAsRawFloat_adjustedNormDist_T_104; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_106 = _intAsRawFloat_adjustedNormDist_T_43 ? 6'h14 : _intAsRawFloat_adjustedNormDist_T_105; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_107 = _intAsRawFloat_adjustedNormDist_T_44 ? 6'h13 : _intAsRawFloat_adjustedNormDist_T_106; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_108 = _intAsRawFloat_adjustedNormDist_T_45 ? 6'h12 : _intAsRawFloat_adjustedNormDist_T_107; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_109 = _intAsRawFloat_adjustedNormDist_T_46 ? 6'h11 : _intAsRawFloat_adjustedNormDist_T_108; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_110 = _intAsRawFloat_adjustedNormDist_T_47 ? 6'h10 : _intAsRawFloat_adjustedNormDist_T_109; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_111 = _intAsRawFloat_adjustedNormDist_T_48 ? 6'hF : _intAsRawFloat_adjustedNormDist_T_110; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_112 = _intAsRawFloat_adjustedNormDist_T_49 ? 6'hE : _intAsRawFloat_adjustedNormDist_T_111; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_113 = _intAsRawFloat_adjustedNormDist_T_50 ? 6'hD : _intAsRawFloat_adjustedNormDist_T_112; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_114 = _intAsRawFloat_adjustedNormDist_T_51 ? 6'hC : _intAsRawFloat_adjustedNormDist_T_113; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_115 = _intAsRawFloat_adjustedNormDist_T_52 ? 6'hB : _intAsRawFloat_adjustedNormDist_T_114; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_116 = _intAsRawFloat_adjustedNormDist_T_53 ? 6'hA : _intAsRawFloat_adjustedNormDist_T_115; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_117 = _intAsRawFloat_adjustedNormDist_T_54 ? 6'h9 : _intAsRawFloat_adjustedNormDist_T_116; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_118 = _intAsRawFloat_adjustedNormDist_T_55 ? 6'h8 : _intAsRawFloat_adjustedNormDist_T_117; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_119 = _intAsRawFloat_adjustedNormDist_T_56 ? 6'h7 : _intAsRawFloat_adjustedNormDist_T_118; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_120 = _intAsRawFloat_adjustedNormDist_T_57 ? 6'h6 : _intAsRawFloat_adjustedNormDist_T_119; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_121 = _intAsRawFloat_adjustedNormDist_T_58 ? 6'h5 : _intAsRawFloat_adjustedNormDist_T_120; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_122 = _intAsRawFloat_adjustedNormDist_T_59 ? 6'h4 : _intAsRawFloat_adjustedNormDist_T_121; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_123 = _intAsRawFloat_adjustedNormDist_T_60 ? 6'h3 : _intAsRawFloat_adjustedNormDist_T_122; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_124 = _intAsRawFloat_adjustedNormDist_T_61 ? 6'h2 : _intAsRawFloat_adjustedNormDist_T_123; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_125 = _intAsRawFloat_adjustedNormDist_T_62 ? 6'h1 : _intAsRawFloat_adjustedNormDist_T_124; // @[Mux.scala:50:70] wire [5:0] intAsRawFloat_adjustedNormDist = _intAsRawFloat_adjustedNormDist_T_63 ? 6'h0 : _intAsRawFloat_adjustedNormDist_T_125; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_out_sExp_T = intAsRawFloat_adjustedNormDist; // @[Mux.scala:50:70] wire [126:0] _intAsRawFloat_sig_T = {63'h0, intAsRawFloat_extAbsIn} << intAsRawFloat_adjustedNormDist; // @[Mux.scala:50:70] wire [63:0] intAsRawFloat_sig = _intAsRawFloat_sig_T[63:0]; // @[rawFloatFromIN.scala:56:{22,41}] wire _intAsRawFloat_out_isZero_T_1; // @[rawFloatFromIN.scala:62:23] wire [8:0] _intAsRawFloat_out_sExp_T_3; // @[rawFloatFromIN.scala:64:72] wire intAsRawFloat_isZero; // @[rawFloatFromIN.scala:59:23] wire [8:0] intAsRawFloat_sExp; // @[rawFloatFromIN.scala:59:23] wire [64:0] intAsRawFloat_sig_0; // @[rawFloatFromIN.scala:59:23] wire _intAsRawFloat_out_isZero_T = intAsRawFloat_sig[63]; // @[rawFloatFromIN.scala:56:41, :62:28] assign _intAsRawFloat_out_isZero_T_1 = ~_intAsRawFloat_out_isZero_T; // @[rawFloatFromIN.scala:62:{23,28}] assign intAsRawFloat_isZero = _intAsRawFloat_out_isZero_T_1; // @[rawFloatFromIN.scala:59:23, :62:23] wire [5:0] _intAsRawFloat_out_sExp_T_1 = ~_intAsRawFloat_out_sExp_T; // @[rawFloatFromIN.scala:64:{36,53}] wire [7:0] _intAsRawFloat_out_sExp_T_2 = {2'h2, _intAsRawFloat_out_sExp_T_1}; // @[rawFloatFromIN.scala:64:{33,36}] assign _intAsRawFloat_out_sExp_T_3 = {1'h0, _intAsRawFloat_out_sExp_T_2}; // @[rawFloatFromIN.scala:64:{33,72}] assign intAsRawFloat_sExp = _intAsRawFloat_out_sExp_T_3; // @[rawFloatFromIN.scala:59:23, :64:72] assign intAsRawFloat_sig_0 = {1'h0, intAsRawFloat_sig}; // @[rawFloatFromIN.scala:56:41, :59:23, :65:20] RoundAnyRawFNToRecFN_ie7_is64_oe8_os24_3 roundAnyRawFNToRecFN ( // @[INToRecFN.scala:60:15] .io_in_isZero (intAsRawFloat_isZero), // @[rawFloatFromIN.scala:59:23] .io_in_sign (intAsRawFloat_sign_0), // @[rawFloatFromIN.scala:59:23] .io_in_sExp (intAsRawFloat_sExp), // @[rawFloatFromIN.scala:59:23] .io_in_sig (intAsRawFloat_sig_0), // @[rawFloatFromIN.scala:59:23] .io_roundingMode (io_roundingMode_0), // @[INToRecFN.scala:43:7] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[INToRecFN.scala:60:15] assign io_out = io_out_0; // @[INToRecFN.scala:43:7] assign io_exceptionFlags = io_exceptionFlags_0; // @[INToRecFN.scala:43:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File RoundAnyRawFNToRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util.Fill import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundAnyRawFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int, options: Int ) extends RawModule { override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(inExpWidth, inSigWidth)) // (allowed exponent range has limits) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0) val effectiveInSigWidth = if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1 val neverUnderflows = ((options & (flRoundOpt_neverUnderflows \| flRoundOpt_subnormsAlwaysExact) ) != 0) \|\| (inExpWidth < outExpWidth) val neverOverflows = ((options & flRoundOpt_neverOverflows) != 0) \|\| (inExpWidth < outExpWidth) val outNaNExp = BigInt(7)<<(outExpWidth - 2) val outInfExp = BigInt(6)<<(outExpWidth - 2) val outMaxFiniteExp = outInfExp - 1 val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2 val outMinNonzeroExp = outMinNormExp - outSigWidth + 1 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_near_even = (io.roundingMode === round_near_even) val roundingMode_minMag = (io.roundingMode === round_minMag) val roundingMode_min = (io.roundingMode === round_min) val roundingMode_max = (io.roundingMode === round_max) val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag) val roundingMode_odd = (io.roundingMode === round_odd) val roundMagUp = (roundingMode_min && io.in.sign) \|\| (roundingMode_max && ! io.in.sign) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sAdjustedExp = if (inExpWidth < outExpWidth) (io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S )(outExpWidth, 0).zext else if (inExpWidth == outExpWidth) io.in.sExp else io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S val adjustedSig = if (inSigWidth <= outSigWidth + 2) io.in.sig<<(outSigWidth - inSigWidth + 2) else (io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ## io.in.sig(inSigWidth - outSigWidth - 2, 0).orR ) val doShiftSigDown1 = if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2) val common_expOut = Wire(UInt((outExpWidth + 1).W)) val common_fractOut = Wire(UInt((outSigWidth - 1).W)) val common_overflow = Wire(Bool()) val common_totalUnderflow = Wire(Bool()) val common_underflow = Wire(Bool()) val common_inexact = Wire(Bool()) if ( neverOverflows && neverUnderflows && (effectiveInSigWidth <= outSigWidth) ) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1 common_fractOut := Mux(doShiftSigDown1, adjustedSig(outSigWidth + 1, 3), adjustedSig(outSigWidth, 2) ) common_overflow := false.B common_totalUnderflow := false.B common_underflow := false.B common_inexact := false.B } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundMask = if (neverUnderflows) 0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W) else (lowMask( sAdjustedExp(outExpWidth, 0), outMinNormExp - outSigWidth - 1, outMinNormExp ) \| doShiftSigDown1) ## 3.U(2.W) val shiftedRoundMask = 0.U(1.W) ## roundMask>>1 val roundPosMask = ~shiftedRoundMask & roundMask val roundPosBit = (adjustedSig & roundPosMask).orR val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR val anyRound = roundPosBit \|\| anyRoundExtra val roundIncr = ((roundingMode_near_even \|\| roundingMode_near_maxMag) && roundPosBit) \|\| (roundMagUp && anyRound) val roundedSig: Bits = Mux(roundIncr, (((adjustedSig \| roundMask)>>2) +& 1.U) & ~Mux(roundingMode_near_even && roundPosBit && ! anyRoundExtra, roundMask>>1, 0.U((outSigWidth + 2).W) ), (adjustedSig & ~roundMask)>>2 \| Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U) ) //* IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //* M.S. BIT OF SUBNORMAL SIG? val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext common_expOut := sRoundedExp(outExpWidth, 0) common_fractOut := Mux(doShiftSigDown1, roundedSig(outSigWidth - 1, 1), roundedSig(outSigWidth - 2, 0) ) common_overflow := (if (neverOverflows) false.B else //* REWRITE BASED ON BEFORE-ROUNDING EXPONENT?: (sRoundedExp>>(outExpWidth - 1) >= 3.S)) common_totalUnderflow := (if (neverUnderflows) false.B else //* WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?: (sRoundedExp < outMinNonzeroExp.S)) val unboundedRange_roundPosBit = Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1)) val unboundedRange_anyRound = (doShiftSigDown1 && adjustedSig(2)) \|\| adjustedSig(1, 0).orR val unboundedRange_roundIncr = ((roundingMode_near_even \|\| roundingMode_near_maxMag) && unboundedRange_roundPosBit) \|\| (roundMagUp && unboundedRange_anyRound) val roundCarry = Mux(doShiftSigDown1, roundedSig(outSigWidth + 1), roundedSig(outSigWidth) ) common_underflow := (if (neverUnderflows) false.B else common_totalUnderflow \|\| //* IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //* M.S. BIT OF SUBNORMAL SIG? (anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) && Mux(doShiftSigDown1, roundMask(3), roundMask(2)) && ! ((io.detectTininess === tininess_afterRounding) && ! Mux(doShiftSigDown1, roundMask(4), roundMask(3) ) && roundCarry && roundPosBit && unboundedRange_roundIncr))) common_inexact := common_totalUnderflow \|\| anyRound } //------------------------------------------------------------------------ //------------------------------------------------------------------------ val isNaNOut = io.invalidExc \|\| io.in.isNaN val notNaN_isSpecialInfOut = io.infiniteExc \|\| io.in.isInf val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero val overflow = commonCase && common_overflow val underflow = commonCase && common_underflow val inexact = overflow \|\| (commonCase && common_inexact) val overflow_roundMagUp = roundingMode_near_even \|\| roundingMode_near_maxMag \|\| roundMagUp val pegMinNonzeroMagOut = commonCase && common_totalUnderflow && (roundMagUp \|\| roundingMode_odd) val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp val notNaN_isInfOut = notNaN_isSpecialInfOut \|\| (overflow && overflow_roundMagUp) val signOut = Mux(isNaNOut, false.B, io.in.sign) val expOut = (common_expOut & ~Mux(io.in.isZero \|\| common_totalUnderflow, (BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMinNonzeroMagOut, ~outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMaxFiniteMagOut, (BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W), 0.U ) & ~Mux(notNaN_isInfOut, (BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U )) \| Mux(pegMinNonzeroMagOut, outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) \| Mux(pegMaxFiniteMagOut, outMaxFiniteExp.U((outExpWidth + 1).W), 0.U ) \| Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) \| Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U) val fractOut = Mux(isNaNOut \|\| io.in.isZero \|\| common_totalUnderflow, Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U), common_fractOut ) \| Fill(outSigWidth - 1, pegMaxFiniteMagOut) io.out := signOut ## expOut ## fractOut io.exceptionFlags := io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int) extends RawModule { override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(expWidth, sigWidth + 2)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( expWidth, sigWidth + 2, expWidth, sigWidth, options)) roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc roundAnyRawFNToRecFN.io.in := io.in roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags }	module RoundRawFNToRecFN_e8_s24_21( // @[RoundAnyRawFNToRecFN.scala:295:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_21 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15] .io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[RoundAnyRawFNToRecFN.scala:310:15] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth \| params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset \|\| !sio.sink_reset_n) \|\| !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise \|\| prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready \|\| !sio.source_reset_n \|\| reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise \|\| prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }	module AsyncValidSync_176( // @[AsyncQueue.scala:58:7] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in = 1'h1; // @[ShiftReg.scala:45:23] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_191 io_out_source_valid_0 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands / class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B \|\| ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B \|\| ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def (t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def (t: UInt) = self t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros \| ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def (t: SInt) = self t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros \| ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid \|\| output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid \|\| output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid \|\| output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def (t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def (t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }	module PE_314( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid, // @[PE.scala:35:14] output io_bad_dataflow // @[PE.scala:35:14] ); wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24] wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [31:0] c1; // @[PE.scala:70:15] wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [31:0] c2; // @[PE.scala:71:15] wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = \|_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25] wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros \| io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = \|_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 \| io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61] wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38] wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38] assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16] assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10] wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10] c1 <= _GEN_7; // @[PE.scala:70:15, :124:10] if (~io_in_control_dataflow_0 \| io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30] end else // @[PE.scala:71:15, :118:101, :119:30] c2 <= _GEN_7; // @[PE.scala:71:15, :124:10] end else begin // @[PE.scala:31:7] c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10] c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10] end last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] end always @(posedge) MacUnit_58 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24] .io_out_d (_mac_unit_io_out_d) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands / class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B \|\| ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B \|\| ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def (t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def (t: UInt) = self t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros \| ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def (t: SInt) = self t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros \| ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid \|\| output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid \|\| output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid \|\| output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def (t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def (t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }	module PE_438( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = \|_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros \| io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = \|_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 \| io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 \| io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_182 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File util.scala: //**************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v4.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v4.common.{MicroOp} import boom.v4.exu.{BrUpdateInfo} / * Object to XOR fold a input register of fullLength into a compressedLength. / object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /* * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks / object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, flush: Bool, uop: MicroOp): Bool = { return apply(brupdate, flush, uop.br_mask) } def apply(brupdate: BrUpdateInfo, flush: Bool, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) \|\| flush } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: T): Bool = { return apply(brupdate, flush, bundle.uop) } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Bool = { return apply(brupdate, flush, bundle.bits) } } /* * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. / object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /* * Object to return a BR mask given a MicroOp mask and old BR mask. / object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, flush, bundle.bits.uop.br_mask) out } } /* * Object to check if at least 1 bit matches in two masks / object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /* * Object to clear one bit in a mask given an index / object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /* * Object to shift a register over by one bit and concat a new one / object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /* * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. / object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /* * Object to increment an input value, wrapping it if * necessary. / object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /* * Object to decrement an input value, wrapping it if * necessary. / object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /* * Object to increment an input value, wrapping it if * necessary. / object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /* * Object to decrement an input value, wrapping it if * necessary. / object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /* * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. / object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc \| (b-1).U) } } /* * Object to rotate a signal left by one / object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /* * Object to sext a value to a particular length. / object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /* * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. / object ImmGen { import boom.v4.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U, IS_N} def apply(i: UInt, isel: UInt): UInt = { val ip = Mux(isel === IS_N, 0.U(LONGEST_IMM_SZ.W), i) val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U \|\| isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J \|\| isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S \|\| isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0) } } /* * Object to see if an instruction is a JALR. / object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /* * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). / object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /* * Object to return the lowest bit position after the head. / object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /* * Object to determine whether queue * index i0 is older than index i1. / object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } object IsYoungerMask { def apply(i: UInt, head: UInt, n: Integer): UInt = { val hi_mask = ~MaskLower(UIntToOH(i)(n-1,0)) val lo_mask = ~MaskUpper(UIntToOH(head)(n-1,0)) Mux(i < head, hi_mask & lo_mask, hi_mask \| lo_mask)(n-1,0) } } /* * Set all bits at or below the highest order '1'. / object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_\|_) } } /* * Set all bits at or above the lowest order '1'. / object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_\|_) } } /* * Transpose a matrix of Chisel Vecs. / object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /* * N-wide one-hot priority encoder. / object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /* * Connect the first k of n valid input interfaces to k output interfaces. / class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_\|\|_)) val out_valids = sels map (col => col.reduce(_\|\|_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /* * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). / class BranchKillableQueue[T <: boom.v4.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v4.common.MicroOp => Bool = u => true.B, fastDeq: Boolean = false) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) if (fastDeq && entries > 1) { // Pipeline dequeue selection so the mux gets an entire cycle val main = Module(new BranchKillableQueue(gen, entries-1, flush_fn, false)) val out_reg = Reg(gen) val out_valid = RegInit(false.B) val out_uop = Reg(new MicroOp) main.io.enq <> io.enq main.io.brupdate := io.brupdate main.io.flush := io.flush io.empty := main.io.empty && !out_valid io.count := main.io.count + out_valid io.deq.valid := out_valid io.deq.bits := out_reg io.deq.bits.uop := out_uop out_uop := UpdateBrMask(io.brupdate, out_uop) out_valid := out_valid && !IsKilledByBranch(io.brupdate, false.B, out_uop) && !(io.flush && flush_fn(out_uop)) main.io.deq.ready := false.B when (io.deq.fire \|\| !out_valid) { out_valid := main.io.deq.valid && !IsKilledByBranch(io.brupdate, false.B, main.io.deq.bits.uop) && !(io.flush && flush_fn(main.io.deq.bits.uop)) out_reg := main.io.deq.bits out_uop := UpdateBrMask(io.brupdate, main.io.deq.bits.uop) main.io.deq.ready := true.B } } else { val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire && !IsKilledByBranch(io.brupdate, false.B, io.enq.bits.uop) && !(io.flush && flush_fn(io.enq.bits.uop))) val do_deq = WireInit((io.deq.ready \|\| !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, false.B, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) io.deq.bits := out val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /* * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" / def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) / def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) / def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) / def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /* * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) / def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /* * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) / def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /* * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line / def apply(strs: String)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } class BranchKillablePipeline[T <: boom.v4.common.HasBoomUOP](gen: T, stages: Int) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val req = Input(Valid(gen)) val flush = Input(Bool()) val brupdate = Input(new BrUpdateInfo) val resp = Output(Vec(stages, Valid(gen))) }) require(stages > 0) val uops = Reg(Vec(stages, Valid(gen))) uops(0).valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.flush, io.req.bits) uops(0).bits := UpdateBrMask(io.brupdate, io.req.bits) for (i <- 1 until stages) { uops(i).valid := uops(i-1).valid && !IsKilledByBranch(io.brupdate, io.flush, uops(i-1).bits) uops(i).bits := UpdateBrMask(io.brupdate, uops(i-1).bits) } for (i <- 0 until stages) { when (reset.asBool) { uops(i).valid := false.B } } io.resp := uops } File tage.scala: package boom.v4.ifu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import boom.v4.common._ import boom.v4.util.{BoomCoreStringPrefix, MaskLower, WrapInc} import scala.math.min class TageResp extends Bundle { val ctr = UInt(3.W) val u = UInt(2.W) } class TageTable(val nRows: Int, val tagSz: Int, val histLength: Int, val uBitPeriod: Int, val singlePorted: Boolean) (implicit p: Parameters) extends BoomModule()(p) with HasBoomFrontendParameters { require(histLength <= globalHistoryLength) val nWrBypassEntries = 2 val io = IO( new Bundle { val f1_req_valid = Input(Bool()) val f1_req_pc = Input(UInt(vaddrBitsExtended.W)) val f1_req_ghist = Input(UInt(globalHistoryLength.W)) val f2_resp = Output(Vec(bankWidth, Valid(new TageResp))) val update_mask = Input(Vec(bankWidth, Bool())) val update_taken = Input(Vec(bankWidth, Bool())) val update_alloc = Input(Vec(bankWidth, Bool())) val update_old_ctr = Input(Vec(bankWidth, UInt(3.W))) val update_pc = Input(UInt()) val update_hist = Input(UInt()) val update_u_mask = Input(Vec(bankWidth, Bool())) val update_u = Input(Vec(bankWidth, UInt(2.W))) }) def compute_folded_hist(hist: UInt, l: Int) = { val nChunks = (histLength + l - 1) / l val hist_chunks = (0 until nChunks) map {i => hist(min((i+1)l, histLength)-1, il) } hist_chunks.reduce(_^_) } def compute_tag_and_hash(unhashed_idx: UInt, hist: UInt) = { val idx_history = compute_folded_hist(hist, log2Ceil(nRows)) val idx = (unhashed_idx ^ idx_history)(log2Ceil(nRows)-1,0) val tag_history = compute_folded_hist(hist, tagSz) val tag = ((unhashed_idx >> log2Ceil(nRows)) ^ tag_history)(tagSz-1,0) (idx, tag) } def inc_ctr(ctr: UInt, taken: Bool): UInt = { Mux(!taken, Mux(ctr === 0.U, 0.U, ctr - 1.U), Mux(ctr === 7.U, 7.U, ctr + 1.U)) } val doing_reset = RegInit(true.B) val reset_idx = RegInit(0.U(log2Ceil(nRows).W)) reset_idx := reset_idx + doing_reset when (reset_idx === (nRows-1).U) { doing_reset := false.B } class TageEntry extends Bundle { val valid = Bool() // TODO: Remove this valid bit val tag = UInt(tagSz.W) val ctr = UInt(3.W) } val tageEntrySz = 1 + tagSz + 3 val (s1_hashed_idx, s1_tag) = compute_tag_and_hash(fetchIdx(io.f1_req_pc), io.f1_req_ghist) val us = SyncReadMem(nRows, Vec(bankWidth2, Bool())) val table = SyncReadMem(nRows, Vec(bankWidth, UInt(tageEntrySz.W))) us.suggestName(s"tage_u_${histLength}") table.suggestName(s"tage_table_${histLength}") val mems = Seq((f"tage_l$histLength", nRows, bankWidth tageEntrySz)) val s2_tag = RegNext(s1_tag) val s2_req_rtage = Wire(Vec(bankWidth, new TageEntry)) val s2_req_rus = Wire(Vec(bankWidth2, Bool())) val s2_req_rhits = VecInit(s2_req_rtage.map(e => e.valid && e.tag === s2_tag && !doing_reset)) for (w <- 0 until bankWidth) { // This bit indicates the TAGE table matched here io.f2_resp(w).valid := s2_req_rhits(w) io.f2_resp(w).bits.u := Cat(s2_req_rus(w2+1), s2_req_rus(w2)) io.f2_resp(w).bits.ctr := s2_req_rtage(w).ctr } val clear_u_ctr = RegInit(0.U((log2Ceil(uBitPeriod) + log2Ceil(nRows) + 1).W)) when (doing_reset) { clear_u_ctr := 1.U } .otherwise { clear_u_ctr := clear_u_ctr + 1.U } val doing_clear_u = clear_u_ctr(log2Ceil(uBitPeriod)-1,0) === 0.U val clear_u_hi = clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 1.U val clear_u_lo = clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 0.U val clear_u_idx = clear_u_ctr >> log2Ceil(uBitPeriod) val clear_u_mask = VecInit((0 until bankWidth2) map { i => if (i % 2 == 0) clear_u_lo else clear_u_hi }).asUInt val (update_idx, update_tag) = compute_tag_and_hash(fetchIdx(io.update_pc), io.update_hist) val update_wdata = Wire(Vec(bankWidth, new TageEntry)) val wen = WireInit(doing_reset \|\| io.update_mask.reduce(_\|\|_)) val rdata = if (singlePorted) table.read(s1_hashed_idx, !wen && io.f1_req_valid) else table.read(s1_hashed_idx, io.f1_req_valid) when (RegNext(wen) && singlePorted.B) { s2_req_rtage := 0.U.asTypeOf(Vec(bankWidth, new TageEntry)) } .otherwise { s2_req_rtage := VecInit(rdata.map(_.asTypeOf(new TageEntry))) } when (wen) { val widx = Mux(doing_reset, reset_idx, update_idx) val wdata = Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(tageEntrySz.W) }), VecInit(update_wdata.map(_.asUInt))) val wmask = Mux(doing_reset, ~(0.U(bankWidth.W)), io.update_mask.asUInt) table.write(widx, wdata, wmask.asBools) } val update_u_mask = VecInit((0 until bankWidth2) map {i => io.update_u_mask(i / 2)}) val update_u_wen = WireInit(doing_reset \|\| doing_clear_u \|\| update_u_mask.reduce(_\|\|_)) val u_rdata = if (singlePorted) { us.read(s1_hashed_idx, !update_u_wen && io.f1_req_valid) } else { us.read(s1_hashed_idx, io.f1_req_valid) } s2_req_rus := u_rdata when (update_u_wen) { val widx = Mux(doing_reset, reset_idx, Mux(doing_clear_u, clear_u_idx, update_idx)) val wdata = Mux(doing_reset \|\| doing_clear_u, VecInit(0.U((bankWidth2).W).asBools), VecInit(io.update_u.asUInt.asBools)) val wmask = Mux(doing_reset, ~(0.U((bankWidth*2).W)), Mux(doing_clear_u, clear_u_mask, update_u_mask.asUInt)) us.write(widx, wdata, wmask.asBools) } val wrbypass_tags = Reg(Vec(nWrBypassEntries, UInt(tagSz.W))) val wrbypass_idxs = Reg(Vec(nWrBypassEntries, UInt(log2Ceil(nRows).W))) val wrbypass = Reg(Vec(nWrBypassEntries, Vec(bankWidth, UInt(3.W)))) val wrbypass_enq_idx = RegInit(0.U(log2Ceil(nWrBypassEntries).W)) val wrbypass_hits = VecInit((0 until nWrBypassEntries) map { i => !doing_reset && wrbypass_tags(i) === update_tag && wrbypass_idxs(i) === update_idx }) val wrbypass_hit = wrbypass_hits.reduce(_\|\|_) val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits) for (w <- 0 until bankWidth) { update_wdata(w).ctr := Mux(io.update_alloc(w), Mux(io.update_taken(w), 4.U, 3.U ), Mux(wrbypass_hit, inc_ctr(wrbypass(wrbypass_hit_idx)(w), io.update_taken(w)), inc_ctr(io.update_old_ctr(w), io.update_taken(w)) ) ) update_wdata(w).valid := true.B update_wdata(w).tag := update_tag } when (io.update_mask.reduce(_\|\|_)) { when (wrbypass_hits.reduce(_\|\|_)) { wrbypass(wrbypass_hit_idx) := VecInit(update_wdata.map(_.ctr)) } .otherwise { wrbypass (wrbypass_enq_idx) := VecInit(update_wdata.map(_.ctr)) wrbypass_tags(wrbypass_enq_idx) := update_tag wrbypass_idxs(wrbypass_enq_idx) := update_idx wrbypass_enq_idx := WrapInc(wrbypass_enq_idx, nWrBypassEntries) } } } case class BoomTageParams( // nSets, histLen, tagSz tableInfo: Seq[Tuple3[Int, Int, Int]] = Seq(( 128, 2, 7), ( 128, 4, 7), ( 256, 8, 8), ( 256, 16, 8), ( 128, 32, 9), ( 128, 64, 9)), uBitPeriod: Int = 2048, singlePorted: Boolean = false ) class TageBranchPredictorBank(params: BoomTageParams = BoomTageParams())(implicit p: Parameters) extends BranchPredictorBank()(p) { val tageUBitPeriod = params.uBitPeriod val tageNTables = params.tableInfo.size class TageMeta extends Bundle { val provider = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W))) val alt_differs = Vec(bankWidth, Output(Bool())) val provider_u = Vec(bankWidth, Output(UInt(2.W))) val provider_ctr = Vec(bankWidth, Output(UInt(3.W))) val allocate = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W))) } val f3_meta = Wire(new TageMeta) override val metaSz = f3_meta.asUInt.getWidth require(metaSz <= bpdMaxMetaLength) def inc_u(u: UInt, alt_differs: Bool, mispredict: Bool): UInt = { Mux(!alt_differs, u, Mux(mispredict, Mux(u === 0.U, 0.U, u - 1.U), Mux(u === 3.U, 3.U, u + 1.U))) } val tt = params.tableInfo map { case (n, l, s) => { val t = Module(new TageTable(n, s, l, params.uBitPeriod, params.singlePorted)) t.io.f1_req_valid := RegNext(io.f0_valid) t.io.f1_req_pc := RegNext(bankAlign(io.f0_pc)) t.io.f1_req_ghist := io.f1_ghist (t, t.mems) } } val tables = tt.map(_._1) val mems = tt.map(_._2).flatten val f2_resps = VecInit(tables.map(_.io.f2_resp)) val f3_resps = RegNext(f2_resps) val s1_update_meta = s1_update.bits.meta.asTypeOf(new TageMeta) val s1_update_mispredict_mask = UIntToOH(s1_update.bits.cfi_idx.bits) & Fill(bankWidth, s1_update.bits.cfi_mispredicted) val s1_update_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, Bool())))) val s1_update_u_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, UInt(1.W))))) val s1_update_taken = Wire(Vec(tageNTables, Vec(bankWidth, Bool()))) val s1_update_old_ctr = Wire(Vec(tageNTables, Vec(bankWidth, UInt(3.W)))) val s1_update_alloc = Wire(Vec(tageNTables, Vec(bankWidth, Bool()))) val s1_update_u = Wire(Vec(tageNTables, Vec(bankWidth, UInt(2.W)))) s1_update_taken := DontCare s1_update_old_ctr := DontCare s1_update_alloc := DontCare s1_update_u := DontCare for (w <- 0 until bankWidth) { var s2_provided = false.B var s2_provider = 0.U var s2_alt_provided = false.B var s2_alt_provider = 0.U for (i <- 0 until tageNTables) { val hit = f2_resps(i)(w).valid s2_alt_provided = s2_alt_provided \|\| (s2_provided && hit) s2_provided = s2_provided \|\| hit s2_alt_provider = Mux(hit, s2_provider, s2_alt_provider) s2_provider = Mux(hit, i.U, s2_provider) } val s3_provided = RegNext(s2_provided) val s3_provider = RegNext(s2_provider) val s3_alt_provided = RegNext(s2_alt_provided) val s3_alt_provider = RegNext(s2_alt_provider) val prov = RegNext(f2_resps(s2_provider)(w).bits) val alt = RegNext(f2_resps(s2_alt_provider)(w).bits) io.resp.f3(w).taken := Mux(s3_provided, Mux(prov.ctr === 3.U \|\| prov.ctr === 4.U, Mux(s3_alt_provided, alt.ctr(2), io.resp_in(0).f3(w).taken), prov.ctr(2)), io.resp_in(0).f3(w).taken ) f3_meta.provider(w).valid := s3_provided f3_meta.provider(w).bits := s3_provider f3_meta.alt_differs(w) := s3_alt_provided && alt.ctr(2) =/= io.resp.f3(w).taken f3_meta.provider_u(w) := prov.u f3_meta.provider_ctr(w) := prov.ctr // Create a mask of tables which did not hit our query, and also contain useless entries // and also uses a longer history than the provider val allocatable_slots = ( VecInit(f3_resps.map(r => !r(w).valid && r(w).bits.u === 0.U)).asUInt & ~(MaskLower(UIntToOH(f3_meta.provider(w).bits)) & Fill(tageNTables, f3_meta.provider(w).valid)) ) val alloc_lfsr = random.LFSR(tageNTables max 2) val first_entry = PriorityEncoder(allocatable_slots) val masked_entry = PriorityEncoder(allocatable_slots & alloc_lfsr) val alloc_entry = Mux(allocatable_slots(masked_entry), masked_entry, first_entry) f3_meta.allocate(w).valid := allocatable_slots =/= 0.U f3_meta.allocate(w).bits := alloc_entry val update_was_taken = (s1_update.bits.cfi_idx.valid && (s1_update.bits.cfi_idx.bits === w.U) && s1_update.bits.cfi_taken) when (s1_update.bits.br_mask(w) && s1_update.valid && s1_update.bits.is_commit_update) { when (s1_update_meta.provider(w).valid) { val provider = s1_update_meta.provider(w).bits s1_update_mask(provider)(w) := true.B s1_update_u_mask(provider)(w) := true.B val new_u = inc_u(s1_update_meta.provider_u(w), s1_update_meta.alt_differs(w), s1_update_mispredict_mask(w)) s1_update_u (provider)(w) := new_u s1_update_taken (provider)(w) := update_was_taken s1_update_old_ctr(provider)(w) := s1_update_meta.provider_ctr(w) s1_update_alloc (provider)(w) := false.B } } } when (s1_update.valid && s1_update.bits.is_commit_update && s1_update.bits.cfi_mispredicted && s1_update.bits.cfi_idx.valid) { val idx = s1_update.bits.cfi_idx.bits val allocate = s1_update_meta.allocate(idx) when (allocate.valid) { s1_update_mask (allocate.bits)(idx) := true.B s1_update_taken(allocate.bits)(idx) := s1_update.bits.cfi_taken s1_update_alloc(allocate.bits)(idx) := true.B s1_update_u_mask(allocate.bits)(idx) := true.B s1_update_u (allocate.bits)(idx) := 0.U } .otherwise { val provider = s1_update_meta.provider(idx) val decr_mask = Mux(provider.valid, ~MaskLower(UIntToOH(provider.bits)), 0.U) for (i <- 0 until tageNTables) { when (decr_mask(i)) { s1_update_u_mask(i)(idx) := true.B s1_update_u (i)(idx) := 0.U } } } } for (i <- 0 until tageNTables) { for (w <- 0 until bankWidth) { tables(i).io.update_mask(w) := RegNext(s1_update_mask(i)(w)) tables(i).io.update_taken(w) := RegNext(s1_update_taken(i)(w)) tables(i).io.update_alloc(w) := RegNext(s1_update_alloc(i)(w)) tables(i).io.update_old_ctr(w) := RegNext(s1_update_old_ctr(i)(w)) tables(i).io.update_u_mask(w) := RegNext(s1_update_u_mask(i)(w)) tables(i).io.update_u(w) := RegNext(s1_update_u(i)(w)) } tables(i).io.update_pc := RegNext(s1_update.bits.pc) tables(i).io.update_hist := RegNext(s1_update.bits.ghist) } //io.f3_meta := Cat(f3_meta.asUInt, micro.io.f3_meta(micro.metaSz-1,0), base.io.f3_meta(base.metaSz-1, 0)) io.f3_meta := f3_meta.asUInt }	module TageTable_5( // @[tage.scala:24:7] input clock, // @[tage.scala:24:7] input reset, // @[tage.scala:24:7] input io_f1_req_valid, // @[tage.scala:31:14] input [39:0] io_f1_req_pc, // @[tage.scala:31:14] input [63:0] io_f1_req_ghist, // @[tage.scala:31:14] output io_f2_resp_0_valid, // @[tage.scala:31:14] output [2:0] io_f2_resp_0_bits_ctr, // @[tage.scala:31:14] output [1:0] io_f2_resp_0_bits_u, // @[tage.scala:31:14] output io_f2_resp_1_valid, // @[tage.scala:31:14] output [2:0] io_f2_resp_1_bits_ctr, // @[tage.scala:31:14] output [1:0] io_f2_resp_1_bits_u, // @[tage.scala:31:14] output io_f2_resp_2_valid, // @[tage.scala:31:14] output [2:0] io_f2_resp_2_bits_ctr, // @[tage.scala:31:14] output [1:0] io_f2_resp_2_bits_u, // @[tage.scala:31:14] output io_f2_resp_3_valid, // @[tage.scala:31:14] output [2:0] io_f2_resp_3_bits_ctr, // @[tage.scala:31:14] output [1:0] io_f2_resp_3_bits_u, // @[tage.scala:31:14] input io_update_mask_0, // @[tage.scala:31:14] input io_update_mask_1, // @[tage.scala:31:14] input io_update_mask_2, // @[tage.scala:31:14] input io_update_mask_3, // @[tage.scala:31:14] input io_update_taken_0, // @[tage.scala:31:14] input io_update_taken_1, // @[tage.scala:31:14] input io_update_taken_2, // @[tage.scala:31:14] input io_update_taken_3, // @[tage.scala:31:14] input io_update_alloc_0, // @[tage.scala:31:14] input io_update_alloc_1, // @[tage.scala:31:14] input io_update_alloc_2, // @[tage.scala:31:14] input io_update_alloc_3, // @[tage.scala:31:14] input [2:0] io_update_old_ctr_0, // @[tage.scala:31:14] input [2:0] io_update_old_ctr_1, // @[tage.scala:31:14] input [2:0] io_update_old_ctr_2, // @[tage.scala:31:14] input [2:0] io_update_old_ctr_3, // @[tage.scala:31:14] input [39:0] io_update_pc, // @[tage.scala:31:14] input [63:0] io_update_hist, // @[tage.scala:31:14] input io_update_u_mask_0, // @[tage.scala:31:14] input io_update_u_mask_1, // @[tage.scala:31:14] input io_update_u_mask_2, // @[tage.scala:31:14] input io_update_u_mask_3, // @[tage.scala:31:14] input [1:0] io_update_u_0, // @[tage.scala:31:14] input [1:0] io_update_u_1, // @[tage.scala:31:14] input [1:0] io_update_u_2, // @[tage.scala:31:14] input [1:0] io_update_u_3 // @[tage.scala:31:14] ); wire [51:0] _tage_table_64_R0_data; // @[tage.scala:90:27] wire [7:0] _tage_u_64_R0_data; // @[tage.scala:89:27] wire io_f1_req_valid_0 = io_f1_req_valid; // @[tage.scala:24:7] wire [39:0] io_f1_req_pc_0 = io_f1_req_pc; // @[tage.scala:24:7] wire [63:0] io_f1_req_ghist_0 = io_f1_req_ghist; // @[tage.scala:24:7] wire io_update_mask_0_0 = io_update_mask_0; // @[tage.scala:24:7] wire io_update_mask_1_0 = io_update_mask_1; // @[tage.scala:24:7] wire io_update_mask_2_0 = io_update_mask_2; // @[tage.scala:24:7] wire io_update_mask_3_0 = io_update_mask_3; // @[tage.scala:24:7] wire io_update_taken_0_0 = io_update_taken_0; // @[tage.scala:24:7] wire io_update_taken_1_0 = io_update_taken_1; // @[tage.scala:24:7] wire io_update_taken_2_0 = io_update_taken_2; // @[tage.scala:24:7] wire io_update_taken_3_0 = io_update_taken_3; // @[tage.scala:24:7] wire io_update_alloc_0_0 = io_update_alloc_0; // @[tage.scala:24:7] wire io_update_alloc_1_0 = io_update_alloc_1; // @[tage.scala:24:7] wire io_update_alloc_2_0 = io_update_alloc_2; // @[tage.scala:24:7] wire io_update_alloc_3_0 = io_update_alloc_3; // @[tage.scala:24:7] wire [2:0] io_update_old_ctr_0_0 = io_update_old_ctr_0; // @[tage.scala:24:7] wire [2:0] io_update_old_ctr_1_0 = io_update_old_ctr_1; // @[tage.scala:24:7] wire [2:0] io_update_old_ctr_2_0 = io_update_old_ctr_2; // @[tage.scala:24:7] wire [2:0] io_update_old_ctr_3_0 = io_update_old_ctr_3; // @[tage.scala:24:7] wire [39:0] io_update_pc_0 = io_update_pc; // @[tage.scala:24:7] wire [63:0] io_update_hist_0 = io_update_hist; // @[tage.scala:24:7] wire io_update_u_mask_0_0 = io_update_u_mask_0; // @[tage.scala:24:7] wire io_update_u_mask_1_0 = io_update_u_mask_1; // @[tage.scala:24:7] wire io_update_u_mask_2_0 = io_update_u_mask_2; // @[tage.scala:24:7] wire io_update_u_mask_3_0 = io_update_u_mask_3; // @[tage.scala:24:7] wire [1:0] io_update_u_0_0 = io_update_u_0; // @[tage.scala:24:7] wire [1:0] io_update_u_1_0 = io_update_u_1; // @[tage.scala:24:7] wire [1:0] io_update_u_2_0 = io_update_u_2; // @[tage.scala:24:7] wire [1:0] io_update_u_3_0 = io_update_u_3; // @[tage.scala:24:7] wire update_wdata_0_valid = 1'h1; // @[tage.scala:120:26] wire update_wdata_1_valid = 1'h1; // @[tage.scala:120:26] wire update_wdata_2_valid = 1'h1; // @[tage.scala:120:26] wire update_wdata_3_valid = 1'h1; // @[tage.scala:120:26] wire [12:0] _wdata_WIRE_0 = 13'h0; // @[tage.scala:130:41] wire [12:0] _wdata_WIRE_1 = 13'h0; // @[tage.scala:130:41] wire [12:0] _wdata_WIRE_2 = 13'h0; // @[tage.scala:130:41] wire [12:0] _wdata_WIRE_3 = 13'h0; // @[tage.scala:130:41] wire [3:0] _wmask_T = 4'hF; // @[tage.scala:131:34] wire _wdata_WIRE_2_0 = 1'h0; // @[tage.scala:145:58] wire _wdata_WIRE_2_1 = 1'h0; // @[tage.scala:145:58] wire _wdata_WIRE_2_2 = 1'h0; // @[tage.scala:145:58] wire _wdata_WIRE_2_3 = 1'h0; // @[tage.scala:145:58] wire _wdata_WIRE_2_4 = 1'h0; // @[tage.scala:145:58] wire _wdata_WIRE_2_5 = 1'h0; // @[tage.scala:145:58] wire _wdata_WIRE_2_6 = 1'h0; // @[tage.scala:145:58] wire _wdata_WIRE_2_7 = 1'h0; // @[tage.scala:145:58] wire [7:0] _wmask_T_2 = 8'hFF; // @[tage.scala:146:34] wire s2_req_rhits_0; // @[tage.scala:100:29] wire [2:0] s2_req_rtage_0_ctr; // @[tage.scala:98:26] wire [1:0] _io_f2_resp_0_bits_u_T; // @[tage.scala:105:34] wire s2_req_rhits_1; // @[tage.scala:100:29] wire [2:0] s2_req_rtage_1_ctr; // @[tage.scala:98:26] wire [1:0] _io_f2_resp_1_bits_u_T; // @[tage.scala:105:34] wire s2_req_rhits_2; // @[tage.scala:100:29] wire [2:0] s2_req_rtage_2_ctr; // @[tage.scala:98:26] wire [1:0] _io_f2_resp_2_bits_u_T; // @[tage.scala:105:34] wire s2_req_rhits_3; // @[tage.scala:100:29] wire [2:0] s2_req_rtage_3_ctr; // @[tage.scala:98:26] wire [1:0] _io_f2_resp_3_bits_u_T; // @[tage.scala:105:34] wire update_u_mask_0 = io_update_u_mask_0_0; // @[tage.scala:24:7, :135:30] wire update_u_mask_1 = io_update_u_mask_0_0; // @[tage.scala:24:7, :135:30] wire update_u_mask_2 = io_update_u_mask_1_0; // @[tage.scala:24:7, :135:30] wire update_u_mask_3 = io_update_u_mask_1_0; // @[tage.scala:24:7, :135:30] wire update_u_mask_4 = io_update_u_mask_2_0; // @[tage.scala:24:7, :135:30] wire update_u_mask_5 = io_update_u_mask_2_0; // @[tage.scala:24:7, :135:30] wire update_u_mask_6 = io_update_u_mask_3_0; // @[tage.scala:24:7, :135:30] wire update_u_mask_7 = io_update_u_mask_3_0; // @[tage.scala:24:7, :135:30] wire [2:0] io_f2_resp_0_bits_ctr_0; // @[tage.scala:24:7] wire [1:0] io_f2_resp_0_bits_u_0; // @[tage.scala:24:7] wire io_f2_resp_0_valid_0; // @[tage.scala:24:7] wire [2:0] io_f2_resp_1_bits_ctr_0; // @[tage.scala:24:7] wire [1:0] io_f2_resp_1_bits_u_0; // @[tage.scala:24:7] wire io_f2_resp_1_valid_0; // @[tage.scala:24:7] wire [2:0] io_f2_resp_2_bits_ctr_0; // @[tage.scala:24:7] wire [1:0] io_f2_resp_2_bits_u_0; // @[tage.scala:24:7] wire io_f2_resp_2_valid_0; // @[tage.scala:24:7] wire [2:0] io_f2_resp_3_bits_ctr_0; // @[tage.scala:24:7] wire [1:0] io_f2_resp_3_bits_u_0; // @[tage.scala:24:7] wire io_f2_resp_3_valid_0; // @[tage.scala:24:7] reg doing_reset; // @[tage.scala:72:28] reg [6:0] reset_idx; // @[tage.scala:73:26] wire [7:0] _GEN = {1'h0, reset_idx}; // @[tage.scala:73:26, :74:26] wire [7:0] _reset_idx_T = _GEN + {7'h0, doing_reset}; // @[tage.scala:72:28, :74:26] wire [6:0] _reset_idx_T_1 = _reset_idx_T[6:0]; // @[tage.scala:74:26] wire [6:0] idx_history_hist_chunks_0 = io_f1_req_ghist_0[6:0]; // @[tage.scala:24:7, :53:11] wire [6:0] idx_history_hist_chunks_1 = io_f1_req_ghist_0[13:7]; // @[tage.scala:24:7, :53:11] wire [6:0] idx_history_hist_chunks_2 = io_f1_req_ghist_0[20:14]; // @[tage.scala:24:7, :53:11] wire [6:0] idx_history_hist_chunks_3 = io_f1_req_ghist_0[27:21]; // @[tage.scala:24:7, :53:11] wire [6:0] idx_history_hist_chunks_4 = io_f1_req_ghist_0[34:28]; // @[tage.scala:24:7, :53:11] wire [6:0] idx_history_hist_chunks_5 = io_f1_req_ghist_0[41:35]; // @[tage.scala:24:7, :53:11] wire [6:0] idx_history_hist_chunks_6 = io_f1_req_ghist_0[48:42]; // @[tage.scala:24:7, :53:11] wire [6:0] idx_history_hist_chunks_7 = io_f1_req_ghist_0[55:49]; // @[tage.scala:24:7, :53:11] wire [6:0] idx_history_hist_chunks_8 = io_f1_req_ghist_0[62:56]; // @[tage.scala:24:7, :53:11] wire idx_history_hist_chunks_9 = io_f1_req_ghist_0[63]; // @[tage.scala:24:7, :53:11] wire tag_history_hist_chunks_7 = io_f1_req_ghist_0[63]; // @[tage.scala:24:7, :53:11] wire [6:0] _idx_history_T = idx_history_hist_chunks_0 ^ idx_history_hist_chunks_1; // @[tage.scala:53:11, :55:25] wire [6:0] _idx_history_T_1 = _idx_history_T ^ idx_history_hist_chunks_2; // @[tage.scala:53:11, :55:25] wire [6:0] _idx_history_T_2 = _idx_history_T_1 ^ idx_history_hist_chunks_3; // @[tage.scala:53:11, :55:25] wire [6:0] _idx_history_T_3 = _idx_history_T_2 ^ idx_history_hist_chunks_4; // @[tage.scala:53:11, :55:25] wire [6:0] _idx_history_T_4 = _idx_history_T_3 ^ idx_history_hist_chunks_5; // @[tage.scala:53:11, :55:25] wire [6:0] _idx_history_T_5 = _idx_history_T_4 ^ idx_history_hist_chunks_6; // @[tage.scala:53:11, :55:25] wire [6:0] _idx_history_T_6 = _idx_history_T_5 ^ idx_history_hist_chunks_7; // @[tage.scala:53:11, :55:25] wire [6:0] _idx_history_T_7 = _idx_history_T_6 ^ idx_history_hist_chunks_8; // @[tage.scala:53:11, :55:25] wire [6:0] idx_history = {_idx_history_T_7[6:1], _idx_history_T_7[0] ^ idx_history_hist_chunks_9}; // @[tage.scala:53:11, :55:25] wire [28:0] _tag_T = io_f1_req_pc_0[39:11]; // @[frontend.scala:149:35] wire [35:0] _idx_T = {_tag_T, io_f1_req_pc_0[10:4] ^ idx_history}; // @[frontend.scala:149:35] wire [6:0] s1_hashed_idx = _idx_T[6:0]; // @[tage.scala:60:{29,43}] wire [6:0] _rdata_WIRE = s1_hashed_idx; // @[tage.scala:60:43, :122:99] wire [6:0] _u_rdata_WIRE = s1_hashed_idx; // @[tage.scala:60:43, :140:12] wire [8:0] tag_history_hist_chunks_0 = io_f1_req_ghist_0[8:0]; // @[tage.scala:24:7, :53:11] wire [8:0] tag_history_hist_chunks_1 = io_f1_req_ghist_0[17:9]; // @[tage.scala:24:7, :53:11] wire [8:0] tag_history_hist_chunks_2 = io_f1_req_ghist_0[26:18]; // @[tage.scala:24:7, :53:11] wire [8:0] tag_history_hist_chunks_3 = io_f1_req_ghist_0[35:27]; // @[tage.scala:24:7, :53:11] wire [8:0] tag_history_hist_chunks_4 = io_f1_req_ghist_0[44:36]; // @[tage.scala:24:7, :53:11] wire [8:0] tag_history_hist_chunks_5 = io_f1_req_ghist_0[53:45]; // @[tage.scala:24:7, :53:11] wire [8:0] tag_history_hist_chunks_6 = io_f1_req_ghist_0[62:54]; // @[tage.scala:24:7, :53:11] wire [8:0] _tag_history_T = tag_history_hist_chunks_0 ^ tag_history_hist_chunks_1; // @[tage.scala:53:11, :55:25] wire [8:0] _tag_history_T_1 = _tag_history_T ^ tag_history_hist_chunks_2; // @[tage.scala:53:11, :55:25] wire [8:0] _tag_history_T_2 = _tag_history_T_1 ^ tag_history_hist_chunks_3; // @[tage.scala:53:11, :55:25] wire [8:0] _tag_history_T_3 = _tag_history_T_2 ^ tag_history_hist_chunks_4; // @[tage.scala:53:11, :55:25] wire [8:0] _tag_history_T_4 = _tag_history_T_3 ^ tag_history_hist_chunks_5; // @[tage.scala:53:11, :55:25] wire [8:0] _tag_history_T_5 = _tag_history_T_4 ^ tag_history_hist_chunks_6; // @[tage.scala:53:11, :55:25] wire [8:0] tag_history = {_tag_history_T_5[8:1], _tag_history_T_5[0] ^ tag_history_hist_chunks_7}; // @[tage.scala:53:11, :55:25] wire [28:0] _tag_T_1 = {_tag_T[28:9], _tag_T[8:0] ^ tag_history}; // @[tage.scala:55:25, :62:{30,50}] wire [8:0] s1_tag = _tag_T_1[8:0]; // @[tage.scala:62:{50,64}] wire wdata_1_0; // @[tage.scala:145:20] wire wdata_1_1; // @[tage.scala:145:20] wire wdata_1_2; // @[tage.scala:145:20] wire wdata_1_3; // @[tage.scala:145:20] wire wdata_1_4; // @[tage.scala:145:20] wire wdata_1_5; // @[tage.scala:145:20] wire wdata_1_6; // @[tage.scala:145:20] wire wdata_1_7; // @[tage.scala:145:20] wire s2_req_rus_0 = _tage_u_64_R0_data[0]; // @[tage.scala:89:27, :99:24] wire s2_req_rus_1 = _tage_u_64_R0_data[1]; // @[tage.scala:89:27, :99:24] wire s2_req_rus_2 = _tage_u_64_R0_data[2]; // @[tage.scala:89:27, :99:24] wire s2_req_rus_3 = _tage_u_64_R0_data[3]; // @[tage.scala:89:27, :99:24] wire s2_req_rus_4 = _tage_u_64_R0_data[4]; // @[tage.scala:89:27, :99:24] wire s2_req_rus_5 = _tage_u_64_R0_data[5]; // @[tage.scala:89:27, :99:24] wire s2_req_rus_6 = _tage_u_64_R0_data[6]; // @[tage.scala:89:27, :99:24] wire s2_req_rus_7 = _tage_u_64_R0_data[7]; // @[tage.scala:89:27, :99:24] wire [12:0] wdata_0; // @[tage.scala:130:20] wire [12:0] wdata_1; // @[tage.scala:130:20] wire [12:0] wdata_2; // @[tage.scala:130:20] wire [12:0] wdata_3; // @[tage.scala:130:20] reg [8:0] s2_tag; // @[tage.scala:96:29] assign io_f2_resp_0_bits_ctr_0 = s2_req_rtage_0_ctr; // @[tage.scala:24:7, :98:26] assign io_f2_resp_1_bits_ctr_0 = s2_req_rtage_1_ctr; // @[tage.scala:24:7, :98:26] assign io_f2_resp_2_bits_ctr_0 = s2_req_rtage_2_ctr; // @[tage.scala:24:7, :98:26] assign io_f2_resp_3_bits_ctr_0 = s2_req_rtage_3_ctr; // @[tage.scala:24:7, :98:26] wire s2_req_rtage_0_valid; // @[tage.scala:98:26] wire [8:0] s2_req_rtage_0_tag; // @[tage.scala:98:26] wire s2_req_rtage_1_valid; // @[tage.scala:98:26] wire [8:0] s2_req_rtage_1_tag; // @[tage.scala:98:26] wire s2_req_rtage_2_valid; // @[tage.scala:98:26] wire [8:0] s2_req_rtage_2_tag; // @[tage.scala:98:26] wire s2_req_rtage_3_valid; // @[tage.scala:98:26] wire [8:0] s2_req_rtage_3_tag; // @[tage.scala:98:26] wire _s2_req_rhits_T = s2_req_rtage_0_tag == s2_tag; // @[tage.scala:96:29, :98:26, :100:69] wire _s2_req_rhits_T_1 = s2_req_rtage_0_valid & _s2_req_rhits_T; // @[tage.scala:98:26, :100:{60,69}] wire _s2_req_rhits_T_2 = ~doing_reset; // @[tage.scala:72:28, :100:83] wire _s2_req_rhits_T_3 = _s2_req_rhits_T_1 & _s2_req_rhits_T_2; // @[tage.scala:100:{60,80,83}] assign s2_req_rhits_0 = _s2_req_rhits_T_3; // @[tage.scala:100:{29,80}] wire _s2_req_rhits_T_4 = s2_req_rtage_1_tag == s2_tag; // @[tage.scala:96:29, :98:26, :100:69] wire _s2_req_rhits_T_5 = s2_req_rtage_1_valid & _s2_req_rhits_T_4; // @[tage.scala:98:26, :100:{60,69}] wire _s2_req_rhits_T_6 = ~doing_reset; // @[tage.scala:72:28, :100:83] wire _s2_req_rhits_T_7 = _s2_req_rhits_T_5 & _s2_req_rhits_T_6; // @[tage.scala:100:{60,80,83}] assign s2_req_rhits_1 = _s2_req_rhits_T_7; // @[tage.scala:100:{29,80}] wire _s2_req_rhits_T_8 = s2_req_rtage_2_tag == s2_tag; // @[tage.scala:96:29, :98:26, :100:69] wire _s2_req_rhits_T_9 = s2_req_rtage_2_valid & _s2_req_rhits_T_8; // @[tage.scala:98:26, :100:{60,69}] wire _s2_req_rhits_T_10 = ~doing_reset; // @[tage.scala:72:28, :100:83] wire _s2_req_rhits_T_11 = _s2_req_rhits_T_9 & _s2_req_rhits_T_10; // @[tage.scala:100:{60,80,83}] assign s2_req_rhits_2 = _s2_req_rhits_T_11; // @[tage.scala:100:{29,80}] wire _s2_req_rhits_T_12 = s2_req_rtage_3_tag == s2_tag; // @[tage.scala:96:29, :98:26, :100:69] wire _s2_req_rhits_T_13 = s2_req_rtage_3_valid & _s2_req_rhits_T_12; // @[tage.scala:98:26, :100:{60,69}] wire _s2_req_rhits_T_14 = ~doing_reset; // @[tage.scala:72:28, :100:83] wire _s2_req_rhits_T_15 = _s2_req_rhits_T_13 & _s2_req_rhits_T_14; // @[tage.scala:100:{60,80,83}] assign s2_req_rhits_3 = _s2_req_rhits_T_15; // @[tage.scala:100:{29,80}] assign io_f2_resp_0_valid_0 = s2_req_rhits_0; // @[tage.scala:24:7, :100:29] assign io_f2_resp_1_valid_0 = s2_req_rhits_1; // @[tage.scala:24:7, :100:29] assign io_f2_resp_2_valid_0 = s2_req_rhits_2; // @[tage.scala:24:7, :100:29] assign io_f2_resp_3_valid_0 = s2_req_rhits_3; // @[tage.scala:24:7, :100:29] assign _io_f2_resp_0_bits_u_T = {s2_req_rus_1, s2_req_rus_0}; // @[tage.scala:99:24, :105:34] assign io_f2_resp_0_bits_u_0 = _io_f2_resp_0_bits_u_T; // @[tage.scala:24:7, :105:34] assign _io_f2_resp_1_bits_u_T = {s2_req_rus_3, s2_req_rus_2}; // @[tage.scala:99:24, :105:34] assign io_f2_resp_1_bits_u_0 = _io_f2_resp_1_bits_u_T; // @[tage.scala:24:7, :105:34] assign _io_f2_resp_2_bits_u_T = {s2_req_rus_5, s2_req_rus_4}; // @[tage.scala:99:24, :105:34] assign io_f2_resp_2_bits_u_0 = _io_f2_resp_2_bits_u_T; // @[tage.scala:24:7, :105:34] assign _io_f2_resp_3_bits_u_T = {s2_req_rus_7, s2_req_rus_6}; // @[tage.scala:99:24, :105:34] assign io_f2_resp_3_bits_u_0 = _io_f2_resp_3_bits_u_T; // @[tage.scala:24:7, :105:34] reg [18:0] clear_u_ctr; // @[tage.scala:109:28] wire [19:0] _clear_u_ctr_T = {1'h0, clear_u_ctr} + 20'h1; // @[tage.scala:109:28, :110:85] wire [18:0] _clear_u_ctr_T_1 = _clear_u_ctr_T[18:0]; // @[tage.scala:110:85] wire [10:0] _doing_clear_u_T = clear_u_ctr[10:0]; // @[tage.scala:109:28, :112:34] wire doing_clear_u = _doing_clear_u_T == 11'h0; // @[tage.scala:112:{34,61}] wire _clear_u_hi_T = clear_u_ctr[18]; // @[tage.scala:109:28, :113:31] wire _clear_u_lo_T = clear_u_ctr[18]; // @[tage.scala:109:28, :113:31, :114:31] wire clear_u_hi = _clear_u_hi_T; // @[tage.scala:113:{31,72}] wire _clear_u_mask_WIRE_1 = clear_u_hi; // @[tage.scala:113:72, :116:29] wire _clear_u_mask_WIRE_3 = clear_u_hi; // @[tage.scala:113:72, :116:29] wire _clear_u_mask_WIRE_5 = clear_u_hi; // @[tage.scala:113:72, :116:29] wire _clear_u_mask_WIRE_7 = clear_u_hi; // @[tage.scala:113:72, :116:29] wire clear_u_lo = ~_clear_u_lo_T; // @[tage.scala:114:{31,72}] wire _clear_u_mask_WIRE_0 = clear_u_lo; // @[tage.scala:114:72, :116:29] wire _clear_u_mask_WIRE_2 = clear_u_lo; // @[tage.scala:114:72, :116:29] wire _clear_u_mask_WIRE_4 = clear_u_lo; // @[tage.scala:114:72, :116:29] wire _clear_u_mask_WIRE_6 = clear_u_lo; // @[tage.scala:114:72, :116:29] wire [7:0] clear_u_idx = clear_u_ctr[18:11]; // @[tage.scala:109:28, :115:33] wire [1:0] clear_u_mask_lo_lo = {_clear_u_mask_WIRE_1, _clear_u_mask_WIRE_0}; // @[tage.scala:116:{29,109}] wire [1:0] clear_u_mask_lo_hi = {_clear_u_mask_WIRE_3, _clear_u_mask_WIRE_2}; // @[tage.scala:116:{29,109}] wire [3:0] clear_u_mask_lo = {clear_u_mask_lo_hi, clear_u_mask_lo_lo}; // @[tage.scala:116:109] wire [1:0] clear_u_mask_hi_lo = {_clear_u_mask_WIRE_5, _clear_u_mask_WIRE_4}; // @[tage.scala:116:{29,109}] wire [1:0] clear_u_mask_hi_hi = {_clear_u_mask_WIRE_7, _clear_u_mask_WIRE_6}; // @[tage.scala:116:{29,109}] wire [3:0] clear_u_mask_hi = {clear_u_mask_hi_hi, clear_u_mask_hi_lo}; // @[tage.scala:116:109] wire [7:0] clear_u_mask = {clear_u_mask_hi, clear_u_mask_lo}; // @[tage.scala:116:109] wire [6:0] idx_history_hist_chunks_0_1 = io_update_hist_0[6:0]; // @[tage.scala:24:7, :53:11] wire [6:0] idx_history_hist_chunks_1_1 = io_update_hist_0[13:7]; // @[tage.scala:24:7, :53:11] wire [6:0] idx_history_hist_chunks_2_1 = io_update_hist_0[20:14]; // @[tage.scala:24:7, :53:11] wire [6:0] idx_history_hist_chunks_3_1 = io_update_hist_0[27:21]; // @[tage.scala:24:7, :53:11] wire [6:0] idx_history_hist_chunks_4_1 = io_update_hist_0[34:28]; // @[tage.scala:24:7, :53:11] wire [6:0] idx_history_hist_chunks_5_1 = io_update_hist_0[41:35]; // @[tage.scala:24:7, :53:11] wire [6:0] idx_history_hist_chunks_6_1 = io_update_hist_0[48:42]; // @[tage.scala:24:7, :53:11] wire [6:0] idx_history_hist_chunks_7_1 = io_update_hist_0[55:49]; // @[tage.scala:24:7, :53:11] wire [6:0] idx_history_hist_chunks_8_1 = io_update_hist_0[62:56]; // @[tage.scala:24:7, :53:11] wire idx_history_hist_chunks_9_1 = io_update_hist_0[63]; // @[tage.scala:24:7, :53:11] wire tag_history_hist_chunks_7_1 = io_update_hist_0[63]; // @[tage.scala:24:7, :53:11] wire [6:0] _idx_history_T_8 = idx_history_hist_chunks_0_1 ^ idx_history_hist_chunks_1_1; // @[tage.scala:53:11, :55:25] wire [6:0] _idx_history_T_9 = _idx_history_T_8 ^ idx_history_hist_chunks_2_1; // @[tage.scala:53:11, :55:25] wire [6:0] _idx_history_T_10 = _idx_history_T_9 ^ idx_history_hist_chunks_3_1; // @[tage.scala:53:11, :55:25] wire [6:0] _idx_history_T_11 = _idx_history_T_10 ^ idx_history_hist_chunks_4_1; // @[tage.scala:53:11, :55:25] wire [6:0] _idx_history_T_12 = _idx_history_T_11 ^ idx_history_hist_chunks_5_1; // @[tage.scala:53:11, :55:25] wire [6:0] _idx_history_T_13 = _idx_history_T_12 ^ idx_history_hist_chunks_6_1; // @[tage.scala:53:11, :55:25] wire [6:0] _idx_history_T_14 = _idx_history_T_13 ^ idx_history_hist_chunks_7_1; // @[tage.scala:53:11, :55:25] wire [6:0] _idx_history_T_15 = _idx_history_T_14 ^ idx_history_hist_chunks_8_1; // @[tage.scala:53:11, :55:25] wire [6:0] idx_history_1 = {_idx_history_T_15[6:1], _idx_history_T_15[0] ^ idx_history_hist_chunks_9_1}; // @[tage.scala:53:11, :55:25] wire [28:0] _tag_T_2 = io_update_pc_0[39:11]; // @[frontend.scala:149:35] wire [35:0] _idx_T_1 = {_tag_T_2, io_update_pc_0[10:4] ^ idx_history_1}; // @[frontend.scala:149:35] wire [6:0] update_idx = _idx_T_1[6:0]; // @[tage.scala:60:{29,43}] wire [8:0] tag_history_hist_chunks_0_1 = io_update_hist_0[8:0]; // @[tage.scala:24:7, :53:11] wire [8:0] tag_history_hist_chunks_1_1 = io_update_hist_0[17:9]; // @[tage.scala:24:7, :53:11] wire [8:0] tag_history_hist_chunks_2_1 = io_update_hist_0[26:18]; // @[tage.scala:24:7, :53:11] wire [8:0] tag_history_hist_chunks_3_1 = io_update_hist_0[35:27]; // @[tage.scala:24:7, :53:11] wire [8:0] tag_history_hist_chunks_4_1 = io_update_hist_0[44:36]; // @[tage.scala:24:7, :53:11] wire [8:0] tag_history_hist_chunks_5_1 = io_update_hist_0[53:45]; // @[tage.scala:24:7, :53:11] wire [8:0] tag_history_hist_chunks_6_1 = io_update_hist_0[62:54]; // @[tage.scala:24:7, :53:11] wire [8:0] _tag_history_T_6 = tag_history_hist_chunks_0_1 ^ tag_history_hist_chunks_1_1; // @[tage.scala:53:11, :55:25] wire [8:0] _tag_history_T_7 = _tag_history_T_6 ^ tag_history_hist_chunks_2_1; // @[tage.scala:53:11, :55:25] wire [8:0] _tag_history_T_8 = _tag_history_T_7 ^ tag_history_hist_chunks_3_1; // @[tage.scala:53:11, :55:25] wire [8:0] _tag_history_T_9 = _tag_history_T_8 ^ tag_history_hist_chunks_4_1; // @[tage.scala:53:11, :55:25] wire [8:0] _tag_history_T_10 = _tag_history_T_9 ^ tag_history_hist_chunks_5_1; // @[tage.scala:53:11, :55:25] wire [8:0] _tag_history_T_11 = _tag_history_T_10 ^ tag_history_hist_chunks_6_1; // @[tage.scala:53:11, :55:25] wire [8:0] tag_history_1 = {_tag_history_T_11[8:1], _tag_history_T_11[0] ^ tag_history_hist_chunks_7_1}; // @[tage.scala:53:11, :55:25] wire [28:0] _tag_T_3 = {_tag_T_2[28:9], _tag_T_2[8:0] ^ tag_history_1}; // @[tage.scala:55:25, :62:{30,50}] wire [8:0] update_tag = _tag_T_3[8:0]; // @[tage.scala:62:{50,64}] wire [8:0] update_wdata_0_tag = update_tag; // @[tage.scala:62:64, :120:26] wire [8:0] update_wdata_1_tag = update_tag; // @[tage.scala:62:64, :120:26] wire [8:0] update_wdata_2_tag = update_tag; // @[tage.scala:62:64, :120:26] wire [8:0] update_wdata_3_tag = update_tag; // @[tage.scala:62:64, :120:26] wire [2:0] _update_wdata_0_ctr_T_22; // @[tage.scala:168:33] wire [2:0] _update_wdata_1_ctr_T_22; // @[tage.scala:168:33] wire [2:0] _update_wdata_2_ctr_T_22; // @[tage.scala:168:33] wire [2:0] _update_wdata_3_ctr_T_22; // @[tage.scala:168:33] wire [2:0] update_wdata_0_ctr; // @[tage.scala:120:26] wire [2:0] update_wdata_1_ctr; // @[tage.scala:120:26] wire [2:0] update_wdata_2_ctr; // @[tage.scala:120:26] wire [2:0] update_wdata_3_ctr; // @[tage.scala:120:26] wire _wen_T = io_update_mask_0_0 \| io_update_mask_1_0; // @[tage.scala:24:7, :121:60] wire _wen_T_1 = _wen_T \| io_update_mask_2_0; // @[tage.scala:24:7, :121:60] wire _wen_T_2 = _wen_T_1 \| io_update_mask_3_0; // @[tage.scala:24:7, :121:60] wire _wen_T_3 = doing_reset \| _wen_T_2; // @[tage.scala:72:28, :121:{34,60}] wire wen = _wen_T_3; // @[tage.scala:121:{21,34}] reg REG; // @[tage.scala:123:16] assign s2_req_rtage_0_ctr = _tage_table_64_R0_data[2:0]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_0_tag = _tage_table_64_R0_data[11:3]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_0_valid = _tage_table_64_R0_data[12]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_1_ctr = _tage_table_64_R0_data[15:13]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_1_tag = _tage_table_64_R0_data[24:16]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_1_valid = _tage_table_64_R0_data[25]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_2_ctr = _tage_table_64_R0_data[28:26]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_2_tag = _tage_table_64_R0_data[37:29]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_2_valid = _tage_table_64_R0_data[38]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_3_ctr = _tage_table_64_R0_data[41:39]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_3_tag = _tage_table_64_R0_data[50:42]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_3_valid = _tage_table_64_R0_data[51]; // @[tage.scala:90:27, :98:26, :126:49] wire [6:0] widx = doing_reset ? reset_idx : update_idx; // @[tage.scala:60:43, :72:28, :73:26, :129:19] wire [9:0] wdata_hi = {1'h1, update_wdata_0_tag}; // @[tage.scala:120:26, :130:114] wire [12:0] _wdata_T = {wdata_hi, update_wdata_0_ctr}; // @[tage.scala:120:26, :130:114] wire [12:0] _wdata_WIRE_1_0 = _wdata_T; // @[tage.scala:130:{94,114}] wire [9:0] wdata_hi_1 = {1'h1, update_wdata_1_tag}; // @[tage.scala:120:26, :130:114] wire [12:0] _wdata_T_1 = {wdata_hi_1, update_wdata_1_ctr}; // @[tage.scala:120:26, :130:114] wire [12:0] _wdata_WIRE_1_1 = _wdata_T_1; // @[tage.scala:130:{94,114}] wire [9:0] wdata_hi_2 = {1'h1, update_wdata_2_tag}; // @[tage.scala:120:26, :130:114] wire [12:0] _wdata_T_2 = {wdata_hi_2, update_wdata_2_ctr}; // @[tage.scala:120:26, :130:114] wire [12:0] _wdata_WIRE_1_2 = _wdata_T_2; // @[tage.scala:130:{94,114}] wire [9:0] wdata_hi_3 = {1'h1, update_wdata_3_tag}; // @[tage.scala:120:26, :130:114] wire [12:0] _wdata_T_3 = {wdata_hi_3, update_wdata_3_ctr}; // @[tage.scala:120:26, :130:114] wire [12:0] _wdata_WIRE_1_3 = _wdata_T_3; // @[tage.scala:130:{94,114}] assign wdata_0 = doing_reset ? 13'h0 : _wdata_WIRE_1_0; // @[tage.scala:72:28, :130:{20,94}] assign wdata_1 = doing_reset ? 13'h0 : _wdata_WIRE_1_1; // @[tage.scala:72:28, :130:{20,94}] assign wdata_2 = doing_reset ? 13'h0 : _wdata_WIRE_1_2; // @[tage.scala:72:28, :130:{20,94}] assign wdata_3 = doing_reset ? 13'h0 : _wdata_WIRE_1_3; // @[tage.scala:72:28, :130:{20,94}] wire [1:0] wmask_lo = {io_update_mask_1_0, io_update_mask_0_0}; // @[tage.scala:24:7, :131:70] wire [1:0] wmask_hi = {io_update_mask_3_0, io_update_mask_2_0}; // @[tage.scala:24:7, :131:70] wire [3:0] _wmask_T_1 = {wmask_hi, wmask_lo}; // @[tage.scala:131:70] wire [3:0] wmask = doing_reset ? 4'hF : _wmask_T_1; // @[tage.scala:72:28, :131:{20,70}] wire _GEN_0 = doing_reset \| doing_clear_u; // @[tage.scala:72:28, :112:61, :136:43] wire _update_u_wen_T; // @[tage.scala:136:43] assign _update_u_wen_T = _GEN_0; // @[tage.scala:136:43] wire _wdata_T_4; // @[tage.scala:145:33] assign _wdata_T_4 = _GEN_0; // @[tage.scala:136:43, :145:33] wire _update_u_wen_T_1 = update_u_mask_0 \| update_u_mask_1; // @[tage.scala:135:30, :136:85] wire _update_u_wen_T_2 = _update_u_wen_T_1 \| update_u_mask_2; // @[tage.scala:135:30, :136:85] wire _update_u_wen_T_3 = _update_u_wen_T_2 \| update_u_mask_3; // @[tage.scala:135:30, :136:85] wire _update_u_wen_T_4 = _update_u_wen_T_3 \| update_u_mask_4; // @[tage.scala:135:30, :136:85] wire _update_u_wen_T_5 = _update_u_wen_T_4 \| update_u_mask_5; // @[tage.scala:135:30, :136:85] wire _update_u_wen_T_6 = _update_u_wen_T_5 \| update_u_mask_6; // @[tage.scala:135:30, :136:85] wire _update_u_wen_T_7 = _update_u_wen_T_6 \| update_u_mask_7; // @[tage.scala:135:30, :136:85] wire _update_u_wen_T_8 = _update_u_wen_T \| _update_u_wen_T_7; // @[tage.scala:136:{43,60,85}] wire update_u_wen = _update_u_wen_T_8; // @[tage.scala:136:{30,60}] wire [7:0] _widx_T = doing_clear_u ? clear_u_idx : {1'h0, update_idx}; // @[tage.scala:60:43, :112:61, :115:33, :144:47] wire [7:0] widx_1 = doing_reset ? _GEN : _widx_T; // @[tage.scala:72:28, :74:26, :144:{19,47}] wire [3:0] wdata_lo = {io_update_u_1_0, io_update_u_0_0}; // @[tage.scala:24:7, :145:110] wire [3:0] wdata_hi_4 = {io_update_u_3_0, io_update_u_2_0}; // @[tage.scala:24:7, :145:110] wire [7:0] _wdata_T_5 = {wdata_hi_4, wdata_lo}; // @[tage.scala:145:110] wire _wdata_T_6 = _wdata_T_5[0]; // @[tage.scala:145:{110,117}] wire _wdata_WIRE_3_0 = _wdata_T_6; // @[tage.scala:145:{97,117}] wire _wdata_T_7 = _wdata_T_5[1]; // @[tage.scala:145:{110,117}] wire _wdata_WIRE_3_1 = _wdata_T_7; // @[tage.scala:145:{97,117}] wire _wdata_T_8 = _wdata_T_5[2]; // @[tage.scala:145:{110,117}] wire _wdata_WIRE_3_2 = _wdata_T_8; // @[tage.scala:145:{97,117}] wire _wdata_T_9 = _wdata_T_5[3]; // @[tage.scala:145:{110,117}] wire _wdata_WIRE_3_3 = _wdata_T_9; // @[tage.scala:145:{97,117}] wire _wdata_T_10 = _wdata_T_5[4]; // @[tage.scala:145:{110,117}] wire _wdata_WIRE_3_4 = _wdata_T_10; // @[tage.scala:145:{97,117}] wire _wdata_T_11 = _wdata_T_5[5]; // @[tage.scala:145:{110,117}] wire _wdata_WIRE_3_5 = _wdata_T_11; // @[tage.scala:145:{97,117}] wire _wdata_T_12 = _wdata_T_5[6]; // @[tage.scala:145:{110,117}] wire _wdata_WIRE_3_6 = _wdata_T_12; // @[tage.scala:145:{97,117}] wire _wdata_T_13 = _wdata_T_5[7]; // @[tage.scala:145:{110,117}] wire _wdata_WIRE_3_7 = _wdata_T_13; // @[tage.scala:145:{97,117}] assign wdata_1_0 = ~_wdata_T_4 & _wdata_WIRE_3_0; // @[tage.scala:145:{20,33,97}] assign wdata_1_1 = ~_wdata_T_4 & _wdata_WIRE_3_1; // @[tage.scala:145:{20,33,97}] assign wdata_1_2 = ~_wdata_T_4 & _wdata_WIRE_3_2; // @[tage.scala:145:{20,33,97}] assign wdata_1_3 = ~_wdata_T_4 & _wdata_WIRE_3_3; // @[tage.scala:145:{20,33,97}] assign wdata_1_4 = ~_wdata_T_4 & _wdata_WIRE_3_4; // @[tage.scala:145:{20,33,97}] assign wdata_1_5 = ~_wdata_T_4 & _wdata_WIRE_3_5; // @[tage.scala:145:{20,33,97}] assign wdata_1_6 = ~_wdata_T_4 & _wdata_WIRE_3_6; // @[tage.scala:145:{20,33,97}] assign wdata_1_7 = ~_wdata_T_4 & _wdata_WIRE_3_7; // @[tage.scala:145:{20,33,97}] wire [1:0] wmask_lo_lo = {update_u_mask_1, update_u_mask_0}; // @[tage.scala:135:30, :146:106] wire [1:0] wmask_lo_hi = {update_u_mask_3, update_u_mask_2}; // @[tage.scala:135:30, :146:106] wire [3:0] wmask_lo_1 = {wmask_lo_hi, wmask_lo_lo}; // @[tage.scala:146:106] wire [1:0] wmask_hi_lo = {update_u_mask_5, update_u_mask_4}; // @[tage.scala:135:30, :146:106] wire [1:0] wmask_hi_hi = {update_u_mask_7, update_u_mask_6}; // @[tage.scala:135:30, :146:106] wire [3:0] wmask_hi_1 = {wmask_hi_hi, wmask_hi_lo}; // @[tage.scala:146:106] wire [7:0] _wmask_T_3 = {wmask_hi_1, wmask_lo_1}; // @[tage.scala:146:106] wire [7:0] _wmask_T_4 = doing_clear_u ? clear_u_mask : _wmask_T_3; // @[tage.scala:112:61, :116:109, :146:{62,106}] wire [7:0] wmask_1 = doing_reset ? 8'hFF : _wmask_T_4; // @[tage.scala:72:28, :146:{20,62}] reg [8:0] wrbypass_tags_0; // @[tage.scala:154:29] reg [8:0] wrbypass_tags_1; // @[tage.scala:154:29] reg [6:0] wrbypass_idxs_0; // @[tage.scala:155:29] reg [6:0] wrbypass_idxs_1; // @[tage.scala:155:29] reg [2:0] wrbypass_0_0; // @[tage.scala:156:29] reg [2:0] wrbypass_0_1; // @[tage.scala:156:29] reg [2:0] wrbypass_0_2; // @[tage.scala:156:29] reg [2:0] wrbypass_0_3; // @[tage.scala:156:29] reg [2:0] wrbypass_1_0; // @[tage.scala:156:29] reg [2:0] wrbypass_1_1; // @[tage.scala:156:29] reg [2:0] wrbypass_1_2; // @[tage.scala:156:29] reg [2:0] wrbypass_1_3; // @[tage.scala:156:29] reg wrbypass_enq_idx; // @[tage.scala:157:33] wire _wrbypass_hits_T = ~doing_reset; // @[tage.scala:72:28, :100:83, :160:5] wire _wrbypass_hits_T_1 = wrbypass_tags_0 == update_tag; // @[tage.scala:62:64, :154:29, :161:22] wire _wrbypass_hits_T_2 = _wrbypass_hits_T & _wrbypass_hits_T_1; // @[tage.scala:160:{5,18}, :161:22] wire _wrbypass_hits_T_3 = wrbypass_idxs_0 == update_idx; // @[tage.scala:60:43, :155:29, :162:22] wire _wrbypass_hits_T_4 = _wrbypass_hits_T_2 & _wrbypass_hits_T_3; // @[tage.scala:160:18, :161:37, :162:22] wire wrbypass_hits_0 = _wrbypass_hits_T_4; // @[tage.scala:159:33, :161:37] wire _wrbypass_hits_T_5 = ~doing_reset; // @[tage.scala:72:28, :100:83, :160:5] wire _wrbypass_hits_T_6 = wrbypass_tags_1 == update_tag; // @[tage.scala:62:64, :154:29, :161:22] wire _wrbypass_hits_T_7 = _wrbypass_hits_T_5 & _wrbypass_hits_T_6; // @[tage.scala:160:{5,18}, :161:22] wire _wrbypass_hits_T_8 = wrbypass_idxs_1 == update_idx; // @[tage.scala:60:43, :155:29, :162:22] wire _wrbypass_hits_T_9 = _wrbypass_hits_T_7 & _wrbypass_hits_T_8; // @[tage.scala:160:18, :161:37, :162:22] wire wrbypass_hits_1 = _wrbypass_hits_T_9; // @[tage.scala:159:33, :161:37] wire wrbypass_hit = wrbypass_hits_0 \| wrbypass_hits_1; // @[tage.scala:159:33, :164:48] wire wrbypass_hit_idx = ~wrbypass_hits_0; // @[Mux.scala:50:70] wire [2:0] _update_wdata_0_ctr_T = io_update_taken_0_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :169:10] wire _update_wdata_0_ctr_T_1 = ~io_update_taken_0_0; // @[tage.scala:24:7, :67:9] wire [2:0] _GEN_1 = wrbypass_hit_idx ? wrbypass_1_0 : wrbypass_0_0; // @[Mux.scala:50:70] wire [2:0] _GEN_2 = wrbypass_hit_idx ? wrbypass_1_1 : wrbypass_0_1; // @[Mux.scala:50:70] wire [2:0] _GEN_3 = wrbypass_hit_idx ? wrbypass_1_2 : wrbypass_0_2; // @[Mux.scala:50:70] wire [2:0] _GEN_4 = wrbypass_hit_idx ? wrbypass_1_3 : wrbypass_0_3; // @[Mux.scala:50:70] wire _update_wdata_0_ctr_T_2 = _GEN_1 == 3'h0; // @[tage.scala:67:25] wire [3:0] _GEN_5 = {1'h0, _GEN_1}; // @[tage.scala:67:{25,43}] wire [3:0] _update_wdata_0_ctr_T_3 = _GEN_5 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_0_ctr_T_4 = _update_wdata_0_ctr_T_3[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_0_ctr_T_5 = _update_wdata_0_ctr_T_2 ? 3'h0 : _update_wdata_0_ctr_T_4; // @[tage.scala:67:{20,25,43}] wire _update_wdata_0_ctr_T_6 = &_GEN_1; // @[tage.scala:67:25, :68:25] wire [3:0] _update_wdata_0_ctr_T_7 = _GEN_5 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_0_ctr_T_8 = _update_wdata_0_ctr_T_7[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_0_ctr_T_9 = _update_wdata_0_ctr_T_6 ? 3'h7 : _update_wdata_0_ctr_T_8; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_0_ctr_T_10 = _update_wdata_0_ctr_T_1 ? _update_wdata_0_ctr_T_5 : _update_wdata_0_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20] wire _update_wdata_0_ctr_T_11 = ~io_update_taken_0_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_0_ctr_T_12 = io_update_old_ctr_0_0 == 3'h0; // @[tage.scala:24:7, :67:25] wire [3:0] _GEN_6 = {1'h0, io_update_old_ctr_0_0}; // @[tage.scala:24:7, :67:43] wire [3:0] _update_wdata_0_ctr_T_13 = _GEN_6 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_0_ctr_T_14 = _update_wdata_0_ctr_T_13[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_0_ctr_T_15 = _update_wdata_0_ctr_T_12 ? 3'h0 : _update_wdata_0_ctr_T_14; // @[tage.scala:67:{20,25,43}] wire _update_wdata_0_ctr_T_16 = &io_update_old_ctr_0_0; // @[tage.scala:24:7, :68:25] wire [3:0] _update_wdata_0_ctr_T_17 = _GEN_6 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_0_ctr_T_18 = _update_wdata_0_ctr_T_17[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_0_ctr_T_19 = _update_wdata_0_ctr_T_16 ? 3'h7 : _update_wdata_0_ctr_T_18; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_0_ctr_T_20 = _update_wdata_0_ctr_T_11 ? _update_wdata_0_ctr_T_15 : _update_wdata_0_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20] wire [2:0] _update_wdata_0_ctr_T_21 = wrbypass_hit ? _update_wdata_0_ctr_T_10 : _update_wdata_0_ctr_T_20; // @[tage.scala:67:8, :164:48, :172:10] assign _update_wdata_0_ctr_T_22 = io_update_alloc_0_0 ? _update_wdata_0_ctr_T : _update_wdata_0_ctr_T_21; // @[tage.scala:24:7, :168:33, :169:10, :172:10] assign update_wdata_0_ctr = _update_wdata_0_ctr_T_22; // @[tage.scala:120:26, :168:33] wire [2:0] _update_wdata_1_ctr_T = io_update_taken_1_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :169:10] wire _update_wdata_1_ctr_T_1 = ~io_update_taken_1_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_1_ctr_T_2 = _GEN_2 == 3'h0; // @[tage.scala:67:25] wire [3:0] _GEN_7 = {1'h0, _GEN_2}; // @[tage.scala:67:{25,43}] wire [3:0] _update_wdata_1_ctr_T_3 = _GEN_7 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_1_ctr_T_4 = _update_wdata_1_ctr_T_3[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_1_ctr_T_5 = _update_wdata_1_ctr_T_2 ? 3'h0 : _update_wdata_1_ctr_T_4; // @[tage.scala:67:{20,25,43}] wire _update_wdata_1_ctr_T_6 = &_GEN_2; // @[tage.scala:67:25, :68:25] wire [3:0] _update_wdata_1_ctr_T_7 = _GEN_7 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_1_ctr_T_8 = _update_wdata_1_ctr_T_7[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_1_ctr_T_9 = _update_wdata_1_ctr_T_6 ? 3'h7 : _update_wdata_1_ctr_T_8; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_1_ctr_T_10 = _update_wdata_1_ctr_T_1 ? _update_wdata_1_ctr_T_5 : _update_wdata_1_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20] wire _update_wdata_1_ctr_T_11 = ~io_update_taken_1_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_1_ctr_T_12 = io_update_old_ctr_1_0 == 3'h0; // @[tage.scala:24:7, :67:25] wire [3:0] _GEN_8 = {1'h0, io_update_old_ctr_1_0}; // @[tage.scala:24:7, :67:43] wire [3:0] _update_wdata_1_ctr_T_13 = _GEN_8 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_1_ctr_T_14 = _update_wdata_1_ctr_T_13[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_1_ctr_T_15 = _update_wdata_1_ctr_T_12 ? 3'h0 : _update_wdata_1_ctr_T_14; // @[tage.scala:67:{20,25,43}] wire _update_wdata_1_ctr_T_16 = &io_update_old_ctr_1_0; // @[tage.scala:24:7, :68:25] wire [3:0] _update_wdata_1_ctr_T_17 = _GEN_8 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_1_ctr_T_18 = _update_wdata_1_ctr_T_17[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_1_ctr_T_19 = _update_wdata_1_ctr_T_16 ? 3'h7 : _update_wdata_1_ctr_T_18; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_1_ctr_T_20 = _update_wdata_1_ctr_T_11 ? _update_wdata_1_ctr_T_15 : _update_wdata_1_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20] wire [2:0] _update_wdata_1_ctr_T_21 = wrbypass_hit ? _update_wdata_1_ctr_T_10 : _update_wdata_1_ctr_T_20; // @[tage.scala:67:8, :164:48, :172:10] assign _update_wdata_1_ctr_T_22 = io_update_alloc_1_0 ? _update_wdata_1_ctr_T : _update_wdata_1_ctr_T_21; // @[tage.scala:24:7, :168:33, :169:10, :172:10] assign update_wdata_1_ctr = _update_wdata_1_ctr_T_22; // @[tage.scala:120:26, :168:33] wire [2:0] _update_wdata_2_ctr_T = io_update_taken_2_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :169:10] wire _update_wdata_2_ctr_T_1 = ~io_update_taken_2_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_2_ctr_T_2 = _GEN_3 == 3'h0; // @[tage.scala:67:25] wire [3:0] _GEN_9 = {1'h0, _GEN_3}; // @[tage.scala:67:{25,43}] wire [3:0] _update_wdata_2_ctr_T_3 = _GEN_9 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_2_ctr_T_4 = _update_wdata_2_ctr_T_3[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_2_ctr_T_5 = _update_wdata_2_ctr_T_2 ? 3'h0 : _update_wdata_2_ctr_T_4; // @[tage.scala:67:{20,25,43}] wire _update_wdata_2_ctr_T_6 = &_GEN_3; // @[tage.scala:67:25, :68:25] wire [3:0] _update_wdata_2_ctr_T_7 = _GEN_9 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_2_ctr_T_8 = _update_wdata_2_ctr_T_7[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_2_ctr_T_9 = _update_wdata_2_ctr_T_6 ? 3'h7 : _update_wdata_2_ctr_T_8; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_2_ctr_T_10 = _update_wdata_2_ctr_T_1 ? _update_wdata_2_ctr_T_5 : _update_wdata_2_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20] wire _update_wdata_2_ctr_T_11 = ~io_update_taken_2_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_2_ctr_T_12 = io_update_old_ctr_2_0 == 3'h0; // @[tage.scala:24:7, :67:25] wire [3:0] _GEN_10 = {1'h0, io_update_old_ctr_2_0}; // @[tage.scala:24:7, :67:43] wire [3:0] _update_wdata_2_ctr_T_13 = _GEN_10 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_2_ctr_T_14 = _update_wdata_2_ctr_T_13[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_2_ctr_T_15 = _update_wdata_2_ctr_T_12 ? 3'h0 : _update_wdata_2_ctr_T_14; // @[tage.scala:67:{20,25,43}] wire _update_wdata_2_ctr_T_16 = &io_update_old_ctr_2_0; // @[tage.scala:24:7, :68:25] wire [3:0] _update_wdata_2_ctr_T_17 = _GEN_10 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_2_ctr_T_18 = _update_wdata_2_ctr_T_17[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_2_ctr_T_19 = _update_wdata_2_ctr_T_16 ? 3'h7 : _update_wdata_2_ctr_T_18; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_2_ctr_T_20 = _update_wdata_2_ctr_T_11 ? _update_wdata_2_ctr_T_15 : _update_wdata_2_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20] wire [2:0] _update_wdata_2_ctr_T_21 = wrbypass_hit ? _update_wdata_2_ctr_T_10 : _update_wdata_2_ctr_T_20; // @[tage.scala:67:8, :164:48, :172:10] assign _update_wdata_2_ctr_T_22 = io_update_alloc_2_0 ? _update_wdata_2_ctr_T : _update_wdata_2_ctr_T_21; // @[tage.scala:24:7, :168:33, :169:10, :172:10] assign update_wdata_2_ctr = _update_wdata_2_ctr_T_22; // @[tage.scala:120:26, :168:33] wire [2:0] _update_wdata_3_ctr_T = io_update_taken_3_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :169:10] wire _update_wdata_3_ctr_T_1 = ~io_update_taken_3_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_3_ctr_T_2 = _GEN_4 == 3'h0; // @[tage.scala:67:25] wire [3:0] _GEN_11 = {1'h0, _GEN_4}; // @[tage.scala:67:{25,43}] wire [3:0] _update_wdata_3_ctr_T_3 = _GEN_11 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_3_ctr_T_4 = _update_wdata_3_ctr_T_3[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_3_ctr_T_5 = _update_wdata_3_ctr_T_2 ? 3'h0 : _update_wdata_3_ctr_T_4; // @[tage.scala:67:{20,25,43}] wire _update_wdata_3_ctr_T_6 = &_GEN_4; // @[tage.scala:67:25, :68:25] wire [3:0] _update_wdata_3_ctr_T_7 = _GEN_11 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_3_ctr_T_8 = _update_wdata_3_ctr_T_7[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_3_ctr_T_9 = _update_wdata_3_ctr_T_6 ? 3'h7 : _update_wdata_3_ctr_T_8; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_3_ctr_T_10 = _update_wdata_3_ctr_T_1 ? _update_wdata_3_ctr_T_5 : _update_wdata_3_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20] wire _update_wdata_3_ctr_T_11 = ~io_update_taken_3_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_3_ctr_T_12 = io_update_old_ctr_3_0 == 3'h0; // @[tage.scala:24:7, :67:25] wire [3:0] _GEN_12 = {1'h0, io_update_old_ctr_3_0}; // @[tage.scala:24:7, :67:43] wire [3:0] _update_wdata_3_ctr_T_13 = _GEN_12 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_3_ctr_T_14 = _update_wdata_3_ctr_T_13[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_3_ctr_T_15 = _update_wdata_3_ctr_T_12 ? 3'h0 : _update_wdata_3_ctr_T_14; // @[tage.scala:67:{20,25,43}] wire _update_wdata_3_ctr_T_16 = &io_update_old_ctr_3_0; // @[tage.scala:24:7, :68:25] wire [3:0] _update_wdata_3_ctr_T_17 = _GEN_12 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_3_ctr_T_18 = _update_wdata_3_ctr_T_17[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_3_ctr_T_19 = _update_wdata_3_ctr_T_16 ? 3'h7 : _update_wdata_3_ctr_T_18; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_3_ctr_T_20 = _update_wdata_3_ctr_T_11 ? _update_wdata_3_ctr_T_15 : _update_wdata_3_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20] wire [2:0] _update_wdata_3_ctr_T_21 = wrbypass_hit ? _update_wdata_3_ctr_T_10 : _update_wdata_3_ctr_T_20; // @[tage.scala:67:8, :164:48, :172:10] assign _update_wdata_3_ctr_T_22 = io_update_alloc_3_0 ? _update_wdata_3_ctr_T : _update_wdata_3_ctr_T_21; // @[tage.scala:24:7, :168:33, :169:10, :172:10] assign update_wdata_3_ctr = _update_wdata_3_ctr_T_22; // @[tage.scala:120:26, :168:33] wire [1:0] _wrbypass_enq_idx_T = {1'h0, wrbypass_enq_idx} + 2'h1; // @[util.scala:211:14] wire _wrbypass_enq_idx_T_1 = _wrbypass_enq_idx_T[0]; // @[util.scala:211:14] wire _wrbypass_enq_idx_T_2 = _wrbypass_enq_idx_T_1; // @[util.scala:211:{14,20}] wire _T_31 = _wen_T \| io_update_mask_2_0 \| io_update_mask_3_0; // @[tage.scala:24:7, :121:60, :180:32] wire _GEN_13 = wrbypass_hit ? wrbypass_hit_idx : wrbypass_enq_idx; // @[Mux.scala:50:70] wire _GEN_14 = ~_T_31 \| wrbypass_hit \| wrbypass_enq_idx; // @[tage.scala:154:29, :156:29, :157:33, :164:48, :180:{32,38}, :181:39, :185:39] wire _GEN_15 = ~_T_31 \| wrbypass_hit \| ~wrbypass_enq_idx; // @[tage.scala:154:29, :156:29, :157:33, :164:48, :180:{32,38}, :181:39, :185:39] always @(posedge clock) begin // @[tage.scala:24:7] if (reset) begin // @[tage.scala:24:7] doing_reset <= 1'h1; // @[tage.scala:72:28] reset_idx <= 7'h0; // @[tage.scala:73:26] clear_u_ctr <= 19'h0; // @[tage.scala:109:28] wrbypass_enq_idx <= 1'h0; // @[tage.scala:157:33] end else begin // @[tage.scala:24:7] doing_reset <= reset_idx != 7'h7F & doing_reset; // @[tage.scala:72:28, :73:26, :75:{19,36,50}] reset_idx <= _reset_idx_T_1; // @[tage.scala:73:26, :74:26] clear_u_ctr <= doing_reset ? 19'h1 : _clear_u_ctr_T_1; // @[tage.scala:72:28, :109:28, :110:{22,36,70,85}] if (~_T_31 \| wrbypass_hit) begin // @[tage.scala:156:29, :157:33, :164:48, :180:{32,38}, :181:39] end else // @[tage.scala:157:33, :180:38, :181:39] wrbypass_enq_idx <= _wrbypass_enq_idx_T_2; // @[util.scala:211:20] end s2_tag <= s1_tag; // @[tage.scala:62:64, :96:29] REG <= wen; // @[tage.scala:121:21, :123:16] if (_GEN_14) begin // @[tage.scala:154:29, :180:38, :181:39, :185:39] end else // @[tage.scala:154:29, :180:38, :181:39, :185:39] wrbypass_tags_0 <= update_tag; // @[tage.scala:62:64, :154:29] if (_GEN_15) begin // @[tage.scala:154:29, :180:38, :181:39, :185:39] end else // @[tage.scala:154:29, :180:38, :181:39, :185:39] wrbypass_tags_1 <= update_tag; // @[tage.scala:62:64, :154:29] if (_GEN_14) begin // @[tage.scala:154:29, :155:29, :180:38, :181:39, :185:39, :186:39] end else // @[tage.scala:155:29, :180:38, :181:39, :186:39] wrbypass_idxs_0 <= update_idx; // @[tage.scala:60:43, :155:29] if (_GEN_15) begin // @[tage.scala:154:29, :155:29, :180:38, :181:39, :185:39, :186:39] end else // @[tage.scala:155:29, :180:38, :181:39, :186:39] wrbypass_idxs_1 <= update_idx; // @[tage.scala:60:43, :155:29] if (~_T_31 \| _GEN_13) begin // @[tage.scala:156:29, :180:{32,38}, :181:39, :182:34, :184:39] end else begin // @[tage.scala:156:29, :180:38, :181:39] wrbypass_0_0 <= update_wdata_0_ctr; // @[tage.scala:120:26, :156:29] wrbypass_0_1 <= update_wdata_1_ctr; // @[tage.scala:120:26, :156:29] wrbypass_0_2 <= update_wdata_2_ctr; // @[tage.scala:120:26, :156:29] wrbypass_0_3 <= update_wdata_3_ctr; // @[tage.scala:120:26, :156:29] end if (_T_31 & _GEN_13) begin // @[tage.scala:156:29, :180:{32,38}, :181:39, :182:34, :184:39] wrbypass_1_0 <= update_wdata_0_ctr; // @[tage.scala:120:26, :156:29] wrbypass_1_1 <= update_wdata_1_ctr; // @[tage.scala:120:26, :156:29] wrbypass_1_2 <= update_wdata_2_ctr; // @[tage.scala:120:26, :156:29] wrbypass_1_3 <= update_wdata_3_ctr; // @[tage.scala:120:26, :156:29] end always @(posedge) tage_u_64 tage_u_64 ( // @[tage.scala:89:27] .R0_addr (_u_rdata_WIRE), // @[tage.scala:140:12] .R0_en (io_f1_req_valid_0), // @[tage.scala:24:7] .R0_clk (clock), .R0_data (_tage_u_64_R0_data), .W0_addr (widx_1[6:0]), // @[tage.scala:144:19, :147:13] .W0_en (update_u_wen), // @[tage.scala:136:30] .W0_clk (clock), .W0_data ({wdata_1_7, wdata_1_6, wdata_1_5, wdata_1_4, wdata_1_3, wdata_1_2, wdata_1_1, wdata_1_0}), // @[tage.scala:89:27, :145:20] .W0_mask (wmask_1) // @[tage.scala:146:20] ); // @[tage.scala:89:27] tage_table_64 tage_table_64 ( // @[tage.scala:90:27] .R0_addr (_rdata_WIRE), // @[tage.scala:122:99] .R0_en (io_f1_req_valid_0), // @[tage.scala:24:7] .R0_clk (clock), .R0_data (_tage_table_64_R0_data), .W0_addr (widx), // @[tage.scala:129:19] .W0_en (wen), // @[tage.scala:121:21] .W0_clk (clock), .W0_data ({wdata_3, wdata_2, wdata_1, wdata_0}), // @[tage.scala:90:27, :130:20] .W0_mask (wmask) // @[tage.scala:131:20] ); // @[tage.scala:90:27] assign io_f2_resp_0_valid = io_f2_resp_0_valid_0; // @[tage.scala:24:7] assign io_f2_resp_0_bits_ctr = io_f2_resp_0_bits_ctr_0; // @[tage.scala:24:7] assign io_f2_resp_0_bits_u = io_f2_resp_0_bits_u_0; // @[tage.scala:24:7] assign io_f2_resp_1_valid = io_f2_resp_1_valid_0; // @[tage.scala:24:7] assign io_f2_resp_1_bits_ctr = io_f2_resp_1_bits_ctr_0; // @[tage.scala:24:7] assign io_f2_resp_1_bits_u = io_f2_resp_1_bits_u_0; // @[tage.scala:24:7] assign io_f2_resp_2_valid = io_f2_resp_2_valid_0; // @[tage.scala:24:7] assign io_f2_resp_2_bits_ctr = io_f2_resp_2_bits_ctr_0; // @[tage.scala:24:7] assign io_f2_resp_2_bits_u = io_f2_resp_2_bits_u_0; // @[tage.scala:24:7] assign io_f2_resp_3_valid = io_f2_resp_3_valid_0; // @[tage.scala:24:7] assign io_f2_resp_3_bits_ctr = io_f2_resp_3_bits_ctr_0; // @[tage.scala:24:7] assign io_f2_resp_3_bits_u = io_f2_resp_3_bits_u_0; // @[tage.scala:24:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands / class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B \|\| ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B \|\| ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def (t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def (t: UInt) = self t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros \| ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def (t: SInt) = self t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros \| ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid \|\| output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid \|\| output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid \|\| output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def (t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def (t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }	module PE_504( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid, // @[PE.scala:35:14] output io_bad_dataflow // @[PE.scala:35:14] ); wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24] wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [31:0] c1; // @[PE.scala:70:15] wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [31:0] c2; // @[PE.scala:71:15] wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = \|_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25] wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros \| io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = \|_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 \| io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61] wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38] wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38] assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16] assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10] wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10] c1 <= _GEN_7; // @[PE.scala:70:15, :124:10] if (~io_in_control_dataflow_0 \| io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30] end else // @[PE.scala:71:15, :118:101, :119:30] c2 <= _GEN_7; // @[PE.scala:71:15, :124:10] end else begin // @[PE.scala:31:7] c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10] c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10] end last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] end always @(posedge) MacUnit_248 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24] .io_out_d (_mac_unit_io_out_d) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black /, label = (ei.manager.beatBytes 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red /, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" / green /) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" / yellow /, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File RegisterRouter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes} import freechips.rocketchip.resources.{Device, Resource, ResourceBindings} import freechips.rocketchip.prci.{NoCrossing} import freechips.rocketchip.regmapper.{RegField, RegMapper, RegMapperParams, RegMapperInput, RegisterRouter} import freechips.rocketchip.util.{BundleField, ControlKey, ElaborationArtefacts, GenRegDescsAnno} import scala.math.min class TLRegisterRouterExtraBundle(val sourceBits: Int, val sizeBits: Int) extends Bundle { val source = UInt((sourceBits max 1).W) val size = UInt((sizeBits max 1).W) } case object TLRegisterRouterExtra extends ControlKey[TLRegisterRouterExtraBundle]("tlrr_extra") case class TLRegisterRouterExtraField(sourceBits: Int, sizeBits: Int) extends BundleField[TLRegisterRouterExtraBundle](TLRegisterRouterExtra, Output(new TLRegisterRouterExtraBundle(sourceBits, sizeBits)), x => { x.size := 0.U x.source := 0.U }) /* TLRegisterNode is a specialized TL SinkNode that encapsulates MMIO registers. * It provides functionality for describing and outputting metdata about the registers in several formats. * It also provides a concrete implementation of a regmap function that will be used * to wire a map of internal registers associated with this node to the node's interconnect port. / case class TLRegisterNode( address: Seq[AddressSet], device: Device, deviceKey: String = "reg/control", concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false)( implicit valName: ValName) extends SinkNode(TLImp)(Seq(TLSlavePortParameters.v1( Seq(TLSlaveParameters.v1( address = address, resources = Seq(Resource(device, deviceKey)), executable = executable, supportsGet = TransferSizes(1, beatBytes), supportsPutPartial = TransferSizes(1, beatBytes), supportsPutFull = TransferSizes(1, beatBytes), fifoId = Some(0))), // requests are handled in order beatBytes = beatBytes, minLatency = min(concurrency, 1)))) with TLFormatNode // the Queue adds at most one cycle { val size = 1 << log2Ceil(1 + address.map(_.max).max - address.map(_.base).min) require (size >= beatBytes) address.foreach { case a => require (a.widen(size-1).base == address.head.widen(size-1).base, s"TLRegisterNode addresses (${address}) must be aligned to its size ${size}") } // Calling this method causes the matching TL2 bundle to be // configured to route all requests to the listed RegFields. def regmap(mapping: RegField.Map) = { val (bundleIn, edge) = this.in(0) val a = bundleIn.a val d = bundleIn.d val fields = TLRegisterRouterExtraField(edge.bundle.sourceBits, edge.bundle.sizeBits) +: a.bits.params.echoFields val params = RegMapperParams(log2Up(size/beatBytes), beatBytes, fields) val in = Wire(Decoupled(new RegMapperInput(params))) in.bits.read := a.bits.opcode === TLMessages.Get in.bits.index := edge.addr_hi(a.bits) in.bits.data := a.bits.data in.bits.mask := a.bits.mask Connectable.waiveUnmatched(in.bits.extra, a.bits.echo) match { case (lhs, rhs) => lhs :<= rhs } val a_extra = in.bits.extra(TLRegisterRouterExtra) a_extra.source := a.bits.source a_extra.size := a.bits.size // Invoke the register map builder val out = RegMapper(beatBytes, concurrency, undefZero, in, mapping:_) // No flow control needed in.valid := a.valid a.ready := in.ready d.valid := out.valid out.ready := d.ready // We must restore the size to enable width adapters to work val d_extra = out.bits.extra(TLRegisterRouterExtra) d.bits := edge.AccessAck(toSource = d_extra.source, lgSize = d_extra.size) // avoid a Mux on the data bus by manually overriding two fields d.bits.data := out.bits.data Connectable.waiveUnmatched(d.bits.echo, out.bits.extra) match { case (lhs, rhs) => lhs :<= rhs } d.bits.opcode := Mux(out.bits.read, TLMessages.AccessAckData, TLMessages.AccessAck) // Tie off unused channels bundleIn.b.valid := false.B bundleIn.c.ready := true.B bundleIn.e.ready := true.B genRegDescsJson(mapping:_) } def genRegDescsJson(mapping: RegField.Map): Unit = { // Dump out the register map for documentation purposes. val base = address.head.base val baseHex = s"0x${base.toInt.toHexString}" val name = s"${device.describe(ResourceBindings()).name}.At${baseHex}" val json = GenRegDescsAnno.serialize(base, name, mapping:_) var suffix = 0 while( ElaborationArtefacts.contains(s"${baseHex}.${suffix}.regmap.json")) { suffix = suffix + 1 } ElaborationArtefacts.add(s"${baseHex}.${suffix}.regmap.json", json) val module = Module.currentModule.get.asInstanceOf[RawModule] GenRegDescsAnno.anno( module, base, mapping:_) } } /* Mix HasTLControlRegMap into any subclass of RegisterRouter to gain helper functions for attaching a device control register map to TileLink. * - The intended use case is that controlNode will diplomatically publish a SW-visible device's memory-mapped control registers. * - Use the clock crossing helper controlXing to externally connect controlNode to a TileLink interconnect. * - Use the mapping helper function regmap to internally fill out the space of device control registers. / trait HasTLControlRegMap { this: RegisterRouter => protected val controlNode = TLRegisterNode( address = address, device = device, deviceKey = "reg/control", concurrency = concurrency, beatBytes = beatBytes, undefZero = undefZero, executable = executable) // Externally, this helper should be used to connect the register control port to a bus val controlXing: TLInwardClockCrossingHelper = this.crossIn(controlNode) // Backwards-compatibility default node accessor with no clock crossing lazy val node: TLInwardNode = controlXing(NoCrossing) // Internally, this function should be used to populate the control port with registers protected def regmap(mapping: RegField.Map): Unit = { controlNode.regmap(mapping:_) } } File RegField.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.regmapper import chisel3._ import chisel3.util.{DecoupledIO, ReadyValidIO} import org.json4s.JsonDSL._ import org.json4s.JsonAST.JValue import freechips.rocketchip.util.{SimpleRegIO} case class RegReadFn private(combinational: Boolean, fn: (Bool, Bool) => (Bool, Bool, UInt)) object RegReadFn { // (ivalid: Bool, oready: Bool) => (iready: Bool, ovalid: Bool, data: UInt) // iready may combinationally depend on oready // all other combinational dependencies forbidden (e.g. ovalid <= ivalid) // effects must become visible on the cycle after ovalid && oready // data is only inspected when ovalid && oready implicit def apply(x: (Bool, Bool) => (Bool, Bool, UInt)) = new RegReadFn(false, x) implicit def apply(x: RegisterReadIO[UInt]): RegReadFn = RegReadFn((ivalid, oready) => { x.request.valid := ivalid x.response.ready := oready (x.request.ready, x.response.valid, x.response.bits) }) // (ready: Bool) => (valid: Bool, data: UInt) // valid must not combinationally depend on ready // effects must become visible on the cycle after valid && ready implicit def apply(x: Bool => (Bool, UInt)) = new RegReadFn(true, { case (_, oready) => val (ovalid, data) = x(oready) (true.B, ovalid, data) }) // read from a ReadyValidIO (only safe if there is a consistent source of data) implicit def apply(x: ReadyValidIO[UInt]):RegReadFn = RegReadFn(ready => { x.ready := ready; (x.valid, x.bits) }) // read from a register implicit def apply(x: UInt):RegReadFn = RegReadFn(ready => (true.B, x)) // noop implicit def apply(x: Unit):RegReadFn = RegReadFn(0.U) } case class RegWriteFn private(combinational: Boolean, fn: (Bool, Bool, UInt) => (Bool, Bool)) object RegWriteFn { // (ivalid: Bool, oready: Bool, data: UInt) => (iready: Bool, ovalid: Bool) // iready may combinationally depend on both oready and data // all other combinational dependencies forbidden (e.g. ovalid <= ivalid) // effects must become visible on the cycle after ovalid && oready // data should only be used for an effect when ivalid && iready implicit def apply(x: (Bool, Bool, UInt) => (Bool, Bool)) = new RegWriteFn(false, x) implicit def apply(x: RegisterWriteIO[UInt]): RegWriteFn = RegWriteFn((ivalid, oready, data) => { x.request.valid := ivalid x.request.bits := data x.response.ready := oready (x.request.ready, x.response.valid) }) // (valid: Bool, data: UInt) => (ready: Bool) // ready may combinationally depend on data (but not valid) // effects must become visible on the cycle after valid && ready implicit def apply(x: (Bool, UInt) => Bool) = // combinational => data valid on oready new RegWriteFn(true, { case (_, oready, data) => (true.B, x(oready, data)) }) // write to a DecoupledIO (only safe if there is a consistent sink draining data) // NOTE: this is not an IrrevocableIO (even on TL2) because other fields could cause a lowered valid implicit def apply(x: DecoupledIO[UInt]): RegWriteFn = RegWriteFn((valid, data) => { x.valid := valid; x.bits := data; x.ready }) // updates a register (or adds a mux to a wire) implicit def apply(x: UInt): RegWriteFn = RegWriteFn((valid, data) => { when (valid) { x := data }; true.B }) // noop implicit def apply(x: Unit): RegWriteFn = RegWriteFn((valid, data) => { true.B }) } case class RegField(width: Int, read: RegReadFn, write: RegWriteFn, desc: Option[RegFieldDesc]) { require (width >= 0, s"RegField width must be >= 0, not $width") def pipelined = !read.combinational \|\| !write.combinational def readOnly = this.copy(write = (), desc = this.desc.map(_.copy(access = RegFieldAccessType.R))) def toJson(byteOffset: Int, bitOffset: Int): JValue = { ( ("byteOffset" -> s"0x${byteOffset.toHexString}") ~ ("bitOffset" -> bitOffset) ~ ("bitWidth" -> width) ~ ("name" -> desc.map(_.name)) ~ ("description" -> desc.map{ d=> if (d.desc == "") None else Some(d.desc)}) ~ ("resetValue" -> desc.map{_.reset}) ~ ("group" -> desc.map{_.group}) ~ ("groupDesc" -> desc.map{_.groupDesc}) ~ ("accessType" -> desc.map {d => d.access.toString}) ~ ("writeType" -> desc.map {d => d.wrType.map(_.toString)}) ~ ("readAction" -> desc.map {d => d.rdAction.map(_.toString)}) ~ ("volatile" -> desc.map {d => if (d.volatile) Some(true) else None}) ~ ("enumerations" -> desc.map {d => Option(d.enumerations.map { case (key, (name, edesc)) => (("value" -> key) ~ ("name" -> name) ~ ("description" -> edesc)) }).filter(_.nonEmpty)}) ) } } object RegField { // Byte address => sequence of bitfields, lowest index => lowest address type Map = (Int, Seq[RegField]) def apply(n: Int) : RegField = apply(n, (), (), Some(RegFieldDesc.reserved)) def apply(n: Int, desc: RegFieldDesc) : RegField = apply(n, (), (), Some(desc)) def apply(n: Int, r: RegReadFn, w: RegWriteFn) : RegField = apply(n, r, w, None) def apply(n: Int, r: RegReadFn, w: RegWriteFn, desc: RegFieldDesc) : RegField = apply(n, r, w, Some(desc)) def apply(n: Int, rw: UInt) : RegField = apply(n, rw, rw, None) def apply(n: Int, rw: UInt, desc: RegFieldDesc) : RegField = apply(n, rw, rw, Some(desc)) def r(n: Int, r: RegReadFn) : RegField = apply(n, r, (), None) def r(n: Int, r: RegReadFn, desc: RegFieldDesc) : RegField = apply(n, r, (), Some(desc.copy(access = RegFieldAccessType.R))) def w(n: Int, w: RegWriteFn) : RegField = apply(n, (), w, None) def w(n: Int, w: RegWriteFn, desc: RegFieldDesc) : RegField = apply(n, (), w, Some(desc.copy(access = RegFieldAccessType.W))) // This RegField allows 'set' to set bits in 'reg'. // and to clear bits when the bus writes bits of value 1. // Setting takes priority over clearing. def w1ToClear(n: Int, reg: UInt, set: UInt, desc: Option[RegFieldDesc] = None): RegField = RegField(n, reg, RegWriteFn((valid, data) => { reg := (~((~reg) \| Mux(valid, data, 0.U))) \| set; true.B }), desc.map{_.copy(access = RegFieldAccessType.RW, wrType=Some(RegFieldWrType.ONE_TO_CLEAR), volatile = true)}) // This RegField wraps an explicit register // (e.g. Black-Boxed Register) to create a R/W register. def rwReg(n: Int, bb: SimpleRegIO, desc: Option[RegFieldDesc] = None) : RegField = RegField(n, bb.q, RegWriteFn((valid, data) => { bb.en := valid bb.d := data true.B }), desc) // Create byte-sized read-write RegFields out of a large UInt register. // It is updated when any of the (implemented) bytes are written, the non-written // bytes are just copied over from their current value. // Because the RegField are all byte-sized, this is also suitable when a register is larger // than the intended bus width of the device (atomic updates are impossible). def bytes(reg: UInt, numBytes: Int, desc: Option[RegFieldDesc]): Seq[RegField] = { require(reg.getWidth 8 >= numBytes, "Can't break a ${reg.getWidth}-bit-wide register into only ${numBytes} bytes.") val numFullBytes = reg.getWidth/8 val numPartialBytes = if ((reg.getWidth % 8) > 0) 1 else 0 val numPadBytes = numBytes - numFullBytes - numPartialBytes val pad = reg \| 0.U((8numBytes).W) val oldBytes = VecInit.tabulate(numBytes) { i => pad(8(i+1)-1, 8i) } val newBytes = WireDefault(oldBytes) val valids = WireDefault(VecInit.fill(numBytes) { false.B }) when (valids.reduce(_ \|\| _)) { reg := newBytes.asUInt } def wrFn(i: Int): RegWriteFn = RegWriteFn((valid, data) => { valids(i) := valid when (valid) {newBytes(i) := data} true.B }) val fullBytes = Seq.tabulate(numFullBytes) { i => val newDesc = desc.map {d => d.copy(name = d.name + s"_$i")} RegField(8, oldBytes(i), wrFn(i), newDesc)} val partialBytes = if (numPartialBytes > 0) { val newDesc = desc.map {d => d.copy(name = d.name + s"_$numFullBytes")} Seq(RegField(reg.getWidth % 8, oldBytes(numFullBytes), wrFn(numFullBytes), newDesc), RegField(8 - (reg.getWidth % 8))) } else Nil val padBytes = Seq.fill(numPadBytes){RegField(8)} fullBytes ++ partialBytes ++ padBytes } def bytes(reg: UInt, desc: Option[RegFieldDesc]): Seq[RegField] = { val width = reg.getWidth require (width % 8 == 0, s"RegField.bytes must be called on byte-sized reg, not ${width} bits") bytes(reg, width/8, desc) } def bytes(reg: UInt, numBytes: Int): Seq[RegField] = bytes(reg, numBytes, None) def bytes(reg: UInt): Seq[RegField] = bytes(reg, None) } trait HasRegMap { def regmap(mapping: RegField.Map): Unit val interrupts: Vec[Bool] } // See Example.scala for an example of how to use regmap File MuxLiteral.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.log2Ceil import scala.reflect.ClassTag /* MuxLiteral creates a lookup table from a key to a list of values. * Unlike MuxLookup, the table keys must be exclusive literals. / object MuxLiteral { def apply[T <: Data:ClassTag](index: UInt, default: T, first: (UInt, T), rest: (UInt, T)): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[(UInt, T)]): T = MuxTable(index, default, cases.map { case (k, v) => (k.litValue, v) }) } object MuxSeq { def apply[T <: Data:ClassTag](index: UInt, default: T, first: T, rest: T): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[T]): T = MuxTable(index, default, cases.zipWithIndex.map { case (v, i) => (BigInt(i), v) }) } object MuxTable { def apply[T <: Data:ClassTag](index: UInt, default: T, first: (BigInt, T), rest: (BigInt, T)): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[(BigInt, T)]): T = { /* All keys must be >= 0 and distinct / cases.foreach { case (k, _) => require (k >= 0) } require (cases.map(_._1).distinct.size == cases.size) / Filter out any cases identical to the default / val simple = cases.filter { case (k, v) => !default.isLit \|\| !v.isLit \|\| v.litValue != default.litValue } val maxKey = (BigInt(0) +: simple.map(_._1)).max val endIndex = BigInt(1) << log2Ceil(maxKey+1) if (simple.isEmpty) { default } else if (endIndex <= 2simple.size) { /* The dense encoding case uses a Vec / val table = Array.fill(endIndex.toInt) { default } simple.foreach { case (k, v) => table(k.toInt) = v } Mux(index >= endIndex.U, default, VecInit(table)(index)) } else { / The sparse encoding case uses switch / val out = WireDefault(default) simple.foldLeft(new chisel3.util.SwitchContext(index, None, Set.empty)) { case (acc, (k, v)) => acc.is (k.U) { out := v } } out } } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /* Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph / def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } } File CLINT.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.devices.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet} import freechips.rocketchip.resources.{Resource, SimpleDevice} import freechips.rocketchip.interrupts.{IntNexusNode, IntSinkParameters, IntSinkPortParameters, IntSourceParameters, IntSourcePortParameters} import freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldGroup} import freechips.rocketchip.subsystem.{BaseSubsystem, CBUS, TLBusWrapperLocation} import freechips.rocketchip.tilelink.{TLFragmenter, TLRegisterNode} import freechips.rocketchip.util.Annotated object CLINTConsts { def msipOffset(hart: Int) = hart * msipBytes def timecmpOffset(hart: Int) = 0x4000 + hart * timecmpBytes def timeOffset = 0xbff8 def msipBytes = 4 def timecmpBytes = 8 def size = 0x10000 def timeWidth = 64 def ipiWidth = 32 def ints = 2 } case class CLINTParams(baseAddress: BigInt = 0x02000000, intStages: Int = 0) { def address = AddressSet(baseAddress, CLINTConsts.size-1) } case object CLINTKey extends Field[Option[CLINTParams]](None) case class CLINTAttachParams( slaveWhere: TLBusWrapperLocation = CBUS ) case object CLINTAttachKey extends Field(CLINTAttachParams()) class CLINT(params: CLINTParams, beatBytes: Int)(implicit p: Parameters) extends LazyModule { import CLINTConsts._ // clint0 => at most 4095 devices val device = new SimpleDevice("clint", Seq("riscv,clint0")) { override val alwaysExtended = true } val node: TLRegisterNode = TLRegisterNode( address = Seq(params.address), device = device, beatBytes = beatBytes) val intnode : IntNexusNode = IntNexusNode( sourceFn = { _ => IntSourcePortParameters(Seq(IntSourceParameters(ints, Seq(Resource(device, "int"))))) }, sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) }, outputRequiresInput = false) lazy val module = new Impl class Impl extends LazyModuleImp(this) { Annotated.params(this, params) require (intnode.edges.in.size == 0, "CLINT only produces interrupts; it does not accept them") val io = IO(new Bundle { val rtcTick = Input(Bool()) }) val time = RegInit(0.U(timeWidth.W)) when (io.rtcTick) { time := time + 1.U } val nTiles = intnode.out.size val timecmp = Seq.fill(nTiles) { Reg(UInt(timeWidth.W)) } val ipi = Seq.fill(nTiles) { RegInit(0.U(1.W)) } val (intnode_out, _) = intnode.out.unzip intnode_out.zipWithIndex.foreach { case (int, i) => int(0) := ShiftRegister(ipi(i)(0), params.intStages) // msip int(1) := ShiftRegister(time.asUInt >= timecmp(i).asUInt, params.intStages) // mtip } /* 0000 msip hart 0 * 0004 msip hart 1 * 4000 mtimecmp hart 0 lo * 4004 mtimecmp hart 0 hi * 4008 mtimecmp hart 1 lo * 400c mtimecmp hart 1 hi * bff8 mtime lo * bffc mtime hi / node.regmap( 0 -> RegFieldGroup ("msip", Some("MSIP Bits"), ipi.zipWithIndex.flatMap{ case (r, i) => RegField(1, r, RegFieldDesc(s"msip_$i", s"MSIP bit for Hart $i", reset=Some(0))) :: RegField(ipiWidth - 1) :: Nil }), timecmpOffset(0) -> timecmp.zipWithIndex.flatMap{ case (t, i) => RegFieldGroup(s"mtimecmp_$i", Some(s"MTIMECMP for hart $i"), RegField.bytes(t, Some(RegFieldDesc(s"mtimecmp_$i", "", reset=None))))}, timeOffset -> RegFieldGroup("mtime", Some("Timer Register"), RegField.bytes(time, Some(RegFieldDesc("mtime", "", reset=Some(0), volatile=true)))) ) } } /* Trait that will connect a CLINT to a subsystem */ trait CanHavePeripheryCLINT { this: BaseSubsystem => val (clintOpt, clintDomainOpt, clintTickOpt) = p(CLINTKey).map { params => val tlbus = locateTLBusWrapper(p(CLINTAttachKey).slaveWhere) val clintDomainWrapper = tlbus.generateSynchronousDomain("CLINT").suggestName("clint_domain") val clint = clintDomainWrapper { LazyModule(new CLINT(params, tlbus.beatBytes)) } clintDomainWrapper { clint.node := tlbus.coupleTo("clint") { TLFragmenter(tlbus, Some("CLINT")) := _ } } val clintTick = clintDomainWrapper { InModuleBody { val tick = IO(Input(Bool())) clint.module.io.rtcTick := tick tick }} (clint, clintDomainWrapper, clintTick) }.unzip3 }	module CLINT( // @[CLINT.scala:65:9] input clock, // @[CLINT.scala:65:9] input reset, // @[CLINT.scala:65:9] output auto_int_out_0, // @[LazyModuleImp.scala:107:25] output auto_int_out_1, // @[LazyModuleImp.scala:107:25] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [25:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input io_rtcTick // @[CLINT.scala:69:16] ); wire out_front_valid; // @[RegisterRouter.scala:87:24] wire out_front_ready; // @[RegisterRouter.scala:87:24] wire out_bits_read; // @[RegisterRouter.scala:87:24] wire [10:0] out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [12:0] in_bits_index; // @[RegisterRouter.scala:73:18] wire in_bits_read; // @[RegisterRouter.scala:73:18] wire auto_in_a_valid_0 = auto_in_a_valid; // @[CLINT.scala:65:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[CLINT.scala:65:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[CLINT.scala:65:9] wire [1:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[CLINT.scala:65:9] wire [10:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[CLINT.scala:65:9] wire [25:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[CLINT.scala:65:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[CLINT.scala:65:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[CLINT.scala:65:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[CLINT.scala:65:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[CLINT.scala:65:9] wire io_rtcTick_0 = io_rtcTick; // @[CLINT.scala:65:9] wire [12:0] out_maskMatch = 13'h7FF; // @[RegisterRouter.scala:87:24] wire [2:0] nodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17] wire [63:0] _out_out_bits_data_WIRE_1_3 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] nodeIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17] wire auto_in_d_bits_sink = 1'h0; // @[CLINT.scala:65:9] wire auto_in_d_bits_denied = 1'h0; // @[CLINT.scala:65:9] wire auto_in_d_bits_corrupt = 1'h0; // @[CLINT.scala:65:9] wire nodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire _valids_WIRE_0 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_2 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_3 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_4 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_5 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_6 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_7 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_0 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_1 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_2 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_3 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_4 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_5 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_6 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_7 = 1'h0; // @[RegField.scala:153:53] wire _out_rifireMux_T_16 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_18 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wifireMux_T_17 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_19 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_rofireMux_T_16 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_18 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wofireMux_T_17 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_19 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T_2 = 1'h0; // @[MuxLiteral.scala:49:17] wire nodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17] wire nodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17] wire nodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17] wire [1:0] auto_in_d_bits_param = 2'h0; // @[CLINT.scala:65:9] wire [1:0] nodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17] wire intnodeOut_0; // @[MixedNode.scala:542:17] wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_iready = 1'h1; // @[RegisterRouter.scala:87:24] wire out_oready = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire intnodeOut_1; // @[MixedNode.scala:542:17] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[CLINT.scala:65:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[CLINT.scala:65:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[CLINT.scala:65:9] wire [1:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[CLINT.scala:65:9] wire [10:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[CLINT.scala:65:9] wire [25:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[CLINT.scala:65:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[CLINT.scala:65:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[CLINT.scala:65:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[CLINT.scala:65:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[CLINT.scala:65:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [10:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire auto_int_out_0_0; // @[CLINT.scala:65:9] wire auto_int_out_1_0; // @[CLINT.scala:65:9] wire auto_in_a_ready_0; // @[CLINT.scala:65:9] wire [2:0] auto_in_d_bits_opcode_0; // @[CLINT.scala:65:9] wire [1:0] auto_in_d_bits_size_0; // @[CLINT.scala:65:9] wire [10:0] auto_in_d_bits_source_0; // @[CLINT.scala:65:9] wire [63:0] auto_in_d_bits_data_0; // @[CLINT.scala:65:9] wire auto_in_d_valid_0; // @[CLINT.scala:65:9] wire in_ready; // @[RegisterRouter.scala:73:18] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[CLINT.scala:65:9] wire in_valid = nodeIn_a_valid; // @[RegisterRouter.scala:73:18] wire [1:0] in_bits_extra_tlrr_extra_size = nodeIn_a_bits_size; // @[RegisterRouter.scala:73:18] wire [10:0] in_bits_extra_tlrr_extra_source = nodeIn_a_bits_source; // @[RegisterRouter.scala:73:18] wire [7:0] in_bits_mask = nodeIn_a_bits_mask; // @[RegisterRouter.scala:73:18] wire [63:0] in_bits_data = nodeIn_a_bits_data; // @[RegisterRouter.scala:73:18] wire out_ready = nodeIn_d_ready; // @[RegisterRouter.scala:87:24] wire out_valid; // @[RegisterRouter.scala:87:24] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[CLINT.scala:65:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[CLINT.scala:65:9] wire [1:0] nodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[CLINT.scala:65:9] wire [10:0] nodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[CLINT.scala:65:9] wire [63:0] out_bits_data; // @[RegisterRouter.scala:87:24] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[CLINT.scala:65:9] wire _intnodeOut_0_T; // @[CLINT.scala:82:37] assign auto_int_out_0_0 = intnodeOut_0; // @[CLINT.scala:65:9] wire _intnodeOut_1_T; // @[CLINT.scala:83:43] assign auto_int_out_1_0 = intnodeOut_1; // @[CLINT.scala:65:9] reg [63:0] time_0; // @[CLINT.scala:73:23] wire [63:0] pad_1 = time_0; // @[RegField.scala:150:19] wire [64:0] _time_T = {1'h0, time_0} + 65'h1; // @[CLINT.scala:73:23, :74:38] wire [63:0] _time_T_1 = _time_T[63:0]; // @[CLINT.scala:74:38] reg [63:0] timecmp_0; // @[CLINT.scala:77:41] wire [63:0] pad = timecmp_0; // @[RegField.scala:150:19] reg ipi_0; // @[CLINT.scala:78:41] assign _intnodeOut_0_T = ipi_0; // @[CLINT.scala:78:41, :82:37] wire _out_T_15 = ipi_0; // @[RegisterRouter.scala:87:24] assign intnodeOut_0 = _intnodeOut_0_T; // @[CLINT.scala:82:37] assign _intnodeOut_1_T = time_0 >= timecmp_0; // @[CLINT.scala:73:23, :77:41, :83:43] assign intnodeOut_1 = _intnodeOut_1_T; // @[CLINT.scala:83:43] wire [7:0] _oldBytes_T = pad[7:0]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_0 = _oldBytes_T; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_1 = pad[15:8]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1 = _oldBytes_T_1; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_2 = pad[23:16]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_2 = _oldBytes_T_2; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_3 = pad[31:24]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_3 = _oldBytes_T_3; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_4 = pad[39:32]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_4 = _oldBytes_T_4; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_5 = pad[47:40]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_5 = _oldBytes_T_5; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_6 = pad[55:48]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_6 = _oldBytes_T_6; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_7 = pad[63:56]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_7 = _oldBytes_T_7; // @[RegField.scala:151:{47,57}] wire [7:0] _out_T_123 = oldBytes_0; // @[RegisterRouter.scala:87:24] wire [7:0] newBytes_0; // @[RegField.scala:152:31] wire [7:0] newBytes_1; // @[RegField.scala:152:31] wire [7:0] newBytes_2; // @[RegField.scala:152:31] wire [7:0] newBytes_3; // @[RegField.scala:152:31] wire [7:0] newBytes_4; // @[RegField.scala:152:31] wire [7:0] newBytes_5; // @[RegField.scala:152:31] wire [7:0] newBytes_6; // @[RegField.scala:152:31] wire [7:0] newBytes_7; // @[RegField.scala:152:31] wire out_f_woready_10; // @[RegisterRouter.scala:87:24] wire out_f_woready_11; // @[RegisterRouter.scala:87:24] wire out_f_woready_12; // @[RegisterRouter.scala:87:24] wire out_f_woready_13; // @[RegisterRouter.scala:87:24] wire out_f_woready_14; // @[RegisterRouter.scala:87:24] wire out_f_woready_15; // @[RegisterRouter.scala:87:24] wire out_f_woready_16; // @[RegisterRouter.scala:87:24] wire out_f_woready_17; // @[RegisterRouter.scala:87:24] wire valids_0; // @[RegField.scala:153:29] wire valids_1; // @[RegField.scala:153:29] wire valids_2; // @[RegField.scala:153:29] wire valids_3; // @[RegField.scala:153:29] wire valids_4; // @[RegField.scala:153:29] wire valids_5; // @[RegField.scala:153:29] wire valids_6; // @[RegField.scala:153:29] wire valids_7; // @[RegField.scala:153:29] wire [15:0] timecmp_0_lo_lo = {newBytes_1, newBytes_0}; // @[RegField.scala:152:31, :154:52] wire [15:0] timecmp_0_lo_hi = {newBytes_3, newBytes_2}; // @[RegField.scala:152:31, :154:52] wire [31:0] timecmp_0_lo = {timecmp_0_lo_hi, timecmp_0_lo_lo}; // @[RegField.scala:154:52] wire [15:0] timecmp_0_hi_lo = {newBytes_5, newBytes_4}; // @[RegField.scala:152:31, :154:52] wire [15:0] timecmp_0_hi_hi = {newBytes_7, newBytes_6}; // @[RegField.scala:152:31, :154:52] wire [31:0] timecmp_0_hi = {timecmp_0_hi_hi, timecmp_0_hi_lo}; // @[RegField.scala:154:52] wire [63:0] _timecmp_0_T = {timecmp_0_hi, timecmp_0_lo}; // @[RegField.scala:154:52] wire [7:0] _oldBytes_T_8 = pad_1[7:0]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_0 = _oldBytes_T_8; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_9 = pad_1[15:8]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_1 = _oldBytes_T_9; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_10 = pad_1[23:16]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_2 = _oldBytes_T_10; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_11 = pad_1[31:24]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_3 = _oldBytes_T_11; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_12 = pad_1[39:32]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_4 = _oldBytes_T_12; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_13 = pad_1[47:40]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_5 = _oldBytes_T_13; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_14 = pad_1[55:48]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_6 = _oldBytes_T_14; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_15 = pad_1[63:56]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_7 = _oldBytes_T_15; // @[RegField.scala:151:{47,57}] wire [7:0] _out_T_35 = oldBytes_1_0; // @[RegisterRouter.scala:87:24] wire [7:0] newBytes_1_0; // @[RegField.scala:152:31] wire [7:0] newBytes_1_1; // @[RegField.scala:152:31] wire [7:0] newBytes_1_2; // @[RegField.scala:152:31] wire [7:0] newBytes_1_3; // @[RegField.scala:152:31] wire [7:0] newBytes_1_4; // @[RegField.scala:152:31] wire [7:0] newBytes_1_5; // @[RegField.scala:152:31] wire [7:0] newBytes_1_6; // @[RegField.scala:152:31] wire [7:0] newBytes_1_7; // @[RegField.scala:152:31] wire out_f_woready_2; // @[RegisterRouter.scala:87:24] wire out_f_woready_3; // @[RegisterRouter.scala:87:24] wire out_f_woready_4; // @[RegisterRouter.scala:87:24] wire out_f_woready_5; // @[RegisterRouter.scala:87:24] wire out_f_woready_6; // @[RegisterRouter.scala:87:24] wire out_f_woready_7; // @[RegisterRouter.scala:87:24] wire out_f_woready_8; // @[RegisterRouter.scala:87:24] wire out_f_woready_9; // @[RegisterRouter.scala:87:24] wire valids_1_0; // @[RegField.scala:153:29] wire valids_1_1; // @[RegField.scala:153:29] wire valids_1_2; // @[RegField.scala:153:29] wire valids_1_3; // @[RegField.scala:153:29] wire valids_1_4; // @[RegField.scala:153:29] wire valids_1_5; // @[RegField.scala:153:29] wire valids_1_6; // @[RegField.scala:153:29] wire valids_1_7; // @[RegField.scala:153:29] wire [15:0] time_lo_lo = {newBytes_1_1, newBytes_1_0}; // @[RegField.scala:152:31, :154:52] wire [15:0] time_lo_hi = {newBytes_1_3, newBytes_1_2}; // @[RegField.scala:152:31, :154:52] wire [31:0] time_lo = {time_lo_hi, time_lo_lo}; // @[RegField.scala:154:52] wire [15:0] time_hi_lo = {newBytes_1_5, newBytes_1_4}; // @[RegField.scala:152:31, :154:52] wire [15:0] time_hi_hi = {newBytes_1_7, newBytes_1_6}; // @[RegField.scala:152:31, :154:52] wire [31:0] time_hi = {time_hi_hi, time_hi_lo}; // @[RegField.scala:154:52] wire [63:0] _time_T_2 = {time_hi, time_lo}; // @[RegField.scala:154:52] wire _out_in_ready_T; // @[RegisterRouter.scala:87:24] assign nodeIn_a_ready = in_ready; // @[RegisterRouter.scala:73:18] wire _in_bits_read_T; // @[RegisterRouter.scala:74:36] wire _out_front_valid_T = in_valid; // @[RegisterRouter.scala:73:18, :87:24] wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24] wire [12:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24] wire [63:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24] wire [7:0] out_front_bits_mask = in_bits_mask; // @[RegisterRouter.scala:73:18, :87:24] wire [10:0] out_front_bits_extra_tlrr_extra_source = in_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24] wire [1:0] out_front_bits_extra_tlrr_extra_size = in_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24] assign _in_bits_read_T = nodeIn_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36] wire [22:0] _in_bits_index_T = nodeIn_a_bits_address[25:3]; // @[Edges.scala:192:34] assign in_bits_index = _in_bits_index_T[12:0]; // @[RegisterRouter.scala:73:18, :75:19] wire _out_front_ready_T = out_ready; // @[RegisterRouter.scala:87:24] wire _out_out_valid_T; // @[RegisterRouter.scala:87:24] assign nodeIn_d_valid = out_valid; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24] wire _nodeIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25] assign nodeIn_d_bits_data = out_bits_data; // @[RegisterRouter.scala:87:24] assign nodeIn_d_bits_d_source = out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [1:0] out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign nodeIn_d_bits_d_size = out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign _out_in_ready_T = out_front_ready; // @[RegisterRouter.scala:87:24] assign _out_out_valid_T = out_front_valid; // @[RegisterRouter.scala:87:24] assign out_bits_read = out_front_bits_read; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_source = out_front_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_size = out_front_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] wire [12:0] _GEN = out_front_bits_index & 13'h7FF; // @[RegisterRouter.scala:87:24] wire [12:0] out_findex; // @[RegisterRouter.scala:87:24] assign out_findex = _GEN; // @[RegisterRouter.scala:87:24] wire [12:0] out_bindex; // @[RegisterRouter.scala:87:24] assign out_bindex = _GEN; // @[RegisterRouter.scala:87:24] wire _GEN_0 = out_findex == 13'h0; // @[RegisterRouter.scala:87:24] wire _out_T; // @[RegisterRouter.scala:87:24] assign _out_T = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_T_4; // @[RegisterRouter.scala:87:24] assign _out_T_4 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _GEN_1 = out_bindex == 13'h0; // @[RegisterRouter.scala:87:24] wire _out_T_1; // @[RegisterRouter.scala:87:24] assign _out_T_1 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_T_5; // @[RegisterRouter.scala:87:24] assign _out_T_5 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_0 = _out_T_1; // @[MuxLiteral.scala:49:48] wire _out_T_2 = out_findex == 13'h7FF; // @[RegisterRouter.scala:87:24] wire _out_T_3 = out_bindex == 13'h7FF; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_2 = _out_T_3; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_1 = _out_T_5; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] wire out_rivalid_0; // @[RegisterRouter.scala:87:24] wire out_rivalid_1; // @[RegisterRouter.scala:87:24] wire out_rivalid_2; // @[RegisterRouter.scala:87:24] wire out_rivalid_3; // @[RegisterRouter.scala:87:24] wire out_rivalid_4; // @[RegisterRouter.scala:87:24] wire out_rivalid_5; // @[RegisterRouter.scala:87:24] wire out_rivalid_6; // @[RegisterRouter.scala:87:24] wire out_rivalid_7; // @[RegisterRouter.scala:87:24] wire out_rivalid_8; // @[RegisterRouter.scala:87:24] wire out_rivalid_9; // @[RegisterRouter.scala:87:24] wire out_rivalid_10; // @[RegisterRouter.scala:87:24] wire out_rivalid_11; // @[RegisterRouter.scala:87:24] wire out_rivalid_12; // @[RegisterRouter.scala:87:24] wire out_rivalid_13; // @[RegisterRouter.scala:87:24] wire out_rivalid_14; // @[RegisterRouter.scala:87:24] wire out_rivalid_15; // @[RegisterRouter.scala:87:24] wire out_rivalid_16; // @[RegisterRouter.scala:87:24] wire out_rivalid_17; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] wire out_wivalid_0; // @[RegisterRouter.scala:87:24] wire out_wivalid_1; // @[RegisterRouter.scala:87:24] wire out_wivalid_2; // @[RegisterRouter.scala:87:24] wire out_wivalid_3; // @[RegisterRouter.scala:87:24] wire out_wivalid_4; // @[RegisterRouter.scala:87:24] wire out_wivalid_5; // @[RegisterRouter.scala:87:24] wire out_wivalid_6; // @[RegisterRouter.scala:87:24] wire out_wivalid_7; // @[RegisterRouter.scala:87:24] wire out_wivalid_8; // @[RegisterRouter.scala:87:24] wire out_wivalid_9; // @[RegisterRouter.scala:87:24] wire out_wivalid_10; // @[RegisterRouter.scala:87:24] wire out_wivalid_11; // @[RegisterRouter.scala:87:24] wire out_wivalid_12; // @[RegisterRouter.scala:87:24] wire out_wivalid_13; // @[RegisterRouter.scala:87:24] wire out_wivalid_14; // @[RegisterRouter.scala:87:24] wire out_wivalid_15; // @[RegisterRouter.scala:87:24] wire out_wivalid_16; // @[RegisterRouter.scala:87:24] wire out_wivalid_17; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] wire out_roready_0; // @[RegisterRouter.scala:87:24] wire out_roready_1; // @[RegisterRouter.scala:87:24] wire out_roready_2; // @[RegisterRouter.scala:87:24] wire out_roready_3; // @[RegisterRouter.scala:87:24] wire out_roready_4; // @[RegisterRouter.scala:87:24] wire out_roready_5; // @[RegisterRouter.scala:87:24] wire out_roready_6; // @[RegisterRouter.scala:87:24] wire out_roready_7; // @[RegisterRouter.scala:87:24] wire out_roready_8; // @[RegisterRouter.scala:87:24] wire out_roready_9; // @[RegisterRouter.scala:87:24] wire out_roready_10; // @[RegisterRouter.scala:87:24] wire out_roready_11; // @[RegisterRouter.scala:87:24] wire out_roready_12; // @[RegisterRouter.scala:87:24] wire out_roready_13; // @[RegisterRouter.scala:87:24] wire out_roready_14; // @[RegisterRouter.scala:87:24] wire out_roready_15; // @[RegisterRouter.scala:87:24] wire out_roready_16; // @[RegisterRouter.scala:87:24] wire out_roready_17; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] wire out_woready_0; // @[RegisterRouter.scala:87:24] wire out_woready_1; // @[RegisterRouter.scala:87:24] wire out_woready_2; // @[RegisterRouter.scala:87:24] wire out_woready_3; // @[RegisterRouter.scala:87:24] wire out_woready_4; // @[RegisterRouter.scala:87:24] wire out_woready_5; // @[RegisterRouter.scala:87:24] wire out_woready_6; // @[RegisterRouter.scala:87:24] wire out_woready_7; // @[RegisterRouter.scala:87:24] wire out_woready_8; // @[RegisterRouter.scala:87:24] wire out_woready_9; // @[RegisterRouter.scala:87:24] wire out_woready_10; // @[RegisterRouter.scala:87:24] wire out_woready_11; // @[RegisterRouter.scala:87:24] wire out_woready_12; // @[RegisterRouter.scala:87:24] wire out_woready_13; // @[RegisterRouter.scala:87:24] wire out_woready_14; // @[RegisterRouter.scala:87:24] wire out_woready_15; // @[RegisterRouter.scala:87:24] wire out_woready_16; // @[RegisterRouter.scala:87:24] wire out_woready_17; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_8 = {8{_out_frontMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_9 = {8{_out_frontMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_10 = {8{_out_frontMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_11 = {8{_out_frontMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_12 = {8{_out_frontMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_13 = {8{_out_frontMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_14 = {8{_out_frontMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_15 = {8{_out_frontMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_lo = {_out_frontMask_T_9, _out_frontMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_hi = {_out_frontMask_T_11, _out_frontMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_lo = {out_frontMask_lo_hi, out_frontMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_lo = {_out_frontMask_T_13, _out_frontMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_hi = {_out_frontMask_T_15, _out_frontMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_hi = {out_frontMask_hi_hi, out_frontMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_frontMask = {out_frontMask_hi, out_frontMask_lo}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_8 = {8{_out_backMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_9 = {8{_out_backMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_10 = {8{_out_backMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_11 = {8{_out_backMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_12 = {8{_out_backMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_13 = {8{_out_backMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_14 = {8{_out_backMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_15 = {8{_out_backMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_lo = {_out_backMask_T_9, _out_backMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_hi = {_out_backMask_T_11, _out_backMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_lo = {out_backMask_lo_hi, out_backMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_lo = {_out_backMask_T_13, _out_backMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_hi = {_out_backMask_T_15, _out_backMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_hi = {out_backMask_hi_hi, out_backMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_backMask = {out_backMask_hi, out_backMask_lo}; // @[RegisterRouter.scala:87:24] wire _out_rimask_T = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire out_rimask = _out_rimask_T; // @[RegisterRouter.scala:87:24] wire out_wimask = _out_wimask_T; // @[RegisterRouter.scala:87:24] wire _out_romask_T = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire out_romask = _out_romask_T; // @[RegisterRouter.scala:87:24] wire out_womask = _out_womask_T; // @[RegisterRouter.scala:87:24] wire out_f_rivalid = out_rivalid_0 & out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_7 = out_f_rivalid; // @[RegisterRouter.scala:87:24] wire out_f_roready = out_roready_0 & out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_8 = out_f_roready; // @[RegisterRouter.scala:87:24] wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_9 = out_f_wivalid; // @[RegisterRouter.scala:87:24] wire out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala:87:24] wire _out_T_10 = out_f_woready; // @[RegisterRouter.scala:87:24] wire _out_T_6 = out_front_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_11 = ~out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_12 = ~out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_13 = ~out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_14 = ~out_womask; // @[RegisterRouter.scala:87:24] wire _out_T_16 = _out_T_15; // @[RegisterRouter.scala:87:24] wire _out_prepend_T = _out_T_16; // @[RegisterRouter.scala:87:24] wire [30:0] _out_rimask_T_1 = out_frontMask[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_wimask_T_1 = out_frontMask[31:1]; // @[RegisterRouter.scala:87:24] wire out_rimask_1 = \|_out_rimask_T_1; // @[RegisterRouter.scala:87:24] wire out_wimask_1 = &_out_wimask_T_1; // @[RegisterRouter.scala:87:24] wire [30:0] _out_romask_T_1 = out_backMask[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_womask_T_1 = out_backMask[31:1]; // @[RegisterRouter.scala:87:24] wire out_romask_1 = \|_out_romask_T_1; // @[RegisterRouter.scala:87:24] wire out_womask_1 = &_out_womask_T_1; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1 = out_rivalid_1 & out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_18 = out_f_rivalid_1; // @[RegisterRouter.scala:87:24] wire out_f_roready_1 = out_roready_1 & out_romask_1; // @[RegisterRouter.scala:87:24] wire _out_T_19 = out_f_roready_1; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1 = out_wivalid_1 & out_wimask_1; // @[RegisterRouter.scala:87:24] wire out_f_woready_1 = out_woready_1 & out_womask_1; // @[RegisterRouter.scala:87:24] wire [30:0] _out_T_17 = out_front_bits_data[31:1]; // @[RegisterRouter.scala:87:24] wire _out_T_20 = ~out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_21 = ~out_wimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_22 = ~out_romask_1; // @[RegisterRouter.scala:87:24] wire _out_T_23 = ~out_womask_1; // @[RegisterRouter.scala:87:24] wire [1:0] out_prepend = {1'h0, _out_prepend_T}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_24 = {30'h0, out_prepend}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_25 = _out_T_24; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_2 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_2 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_10 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_10 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire out_rimask_2 = \|_out_rimask_T_2; // @[RegisterRouter.scala:87:24] wire out_wimask_2 = &_out_wimask_T_2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_2 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_2 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_10 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_10 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire out_romask_2 = \|_out_romask_T_2; // @[RegisterRouter.scala:87:24] wire out_womask_2 = &_out_womask_T_2; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_2 = out_rivalid_2 & out_rimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_27 = out_f_rivalid_2; // @[RegisterRouter.scala:87:24] wire out_f_roready_2 = out_roready_2 & out_romask_2; // @[RegisterRouter.scala:87:24] wire _out_T_28 = out_f_roready_2; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_2 = out_wivalid_2 & out_wimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_29 = out_f_wivalid_2; // @[RegisterRouter.scala:87:24] assign out_f_woready_2 = out_woready_2 & out_womask_2; // @[RegisterRouter.scala:87:24] assign valids_1_0 = out_f_woready_2; // @[RegisterRouter.scala:87:24] wire _out_T_30 = out_f_woready_2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_26 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_114 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] assign newBytes_1_0 = out_f_woready_2 ? _out_T_26 : oldBytes_1_0; // @[RegisterRouter.scala:87:24] wire _out_T_31 = ~out_rimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_32 = ~out_wimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_33 = ~out_romask_2; // @[RegisterRouter.scala:87:24] wire _out_T_34 = ~out_womask_2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_36 = _out_T_35; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1 = _out_T_36; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_3 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_3 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_11 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_11 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire out_rimask_3 = \|_out_rimask_T_3; // @[RegisterRouter.scala:87:24] wire out_wimask_3 = &_out_wimask_T_3; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_3 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_3 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_11 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_11 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire out_romask_3 = \|_out_romask_T_3; // @[RegisterRouter.scala:87:24] wire out_womask_3 = &_out_womask_T_3; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_3 = out_rivalid_3 & out_rimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_38 = out_f_rivalid_3; // @[RegisterRouter.scala:87:24] wire out_f_roready_3 = out_roready_3 & out_romask_3; // @[RegisterRouter.scala:87:24] wire _out_T_39 = out_f_roready_3; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_3 = out_wivalid_3 & out_wimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_40 = out_f_wivalid_3; // @[RegisterRouter.scala:87:24] assign out_f_woready_3 = out_woready_3 & out_womask_3; // @[RegisterRouter.scala:87:24] assign valids_1_1 = out_f_woready_3; // @[RegisterRouter.scala:87:24] wire _out_T_41 = out_f_woready_3; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_37 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_125 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] assign newBytes_1_1 = out_f_woready_3 ? _out_T_37 : oldBytes_1_1; // @[RegisterRouter.scala:87:24] wire _out_T_42 = ~out_rimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_43 = ~out_wimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_44 = ~out_romask_3; // @[RegisterRouter.scala:87:24] wire _out_T_45 = ~out_womask_3; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1 = {oldBytes_1_1, _out_prepend_T_1}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_46 = out_prepend_1; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_47 = _out_T_46; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_2 = _out_T_47; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_4 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_4 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_12 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_12 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire out_rimask_4 = \|_out_rimask_T_4; // @[RegisterRouter.scala:87:24] wire out_wimask_4 = &_out_wimask_T_4; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_4 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_4 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_12 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_12 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire out_romask_4 = \|_out_romask_T_4; // @[RegisterRouter.scala:87:24] wire out_womask_4 = &_out_womask_T_4; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_4 = out_rivalid_4 & out_rimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_49 = out_f_rivalid_4; // @[RegisterRouter.scala:87:24] wire out_f_roready_4 = out_roready_4 & out_romask_4; // @[RegisterRouter.scala:87:24] wire _out_T_50 = out_f_roready_4; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_4 = out_wivalid_4 & out_wimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_51 = out_f_wivalid_4; // @[RegisterRouter.scala:87:24] assign out_f_woready_4 = out_woready_4 & out_womask_4; // @[RegisterRouter.scala:87:24] assign valids_1_2 = out_f_woready_4; // @[RegisterRouter.scala:87:24] wire _out_T_52 = out_f_woready_4; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_48 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_136 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] assign newBytes_1_2 = out_f_woready_4 ? _out_T_48 : oldBytes_1_2; // @[RegisterRouter.scala:87:24] wire _out_T_53 = ~out_rimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_54 = ~out_wimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_55 = ~out_romask_4; // @[RegisterRouter.scala:87:24] wire _out_T_56 = ~out_womask_4; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_2 = {oldBytes_1_2, _out_prepend_T_2}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_57 = out_prepend_2; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_58 = _out_T_57; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_3 = _out_T_58; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_5 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_5 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_13 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_13 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire out_rimask_5 = \|_out_rimask_T_5; // @[RegisterRouter.scala:87:24] wire out_wimask_5 = &_out_wimask_T_5; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_5 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_5 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_13 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_13 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire out_romask_5 = \|_out_romask_T_5; // @[RegisterRouter.scala:87:24] wire out_womask_5 = &_out_womask_T_5; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_5 = out_rivalid_5 & out_rimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_60 = out_f_rivalid_5; // @[RegisterRouter.scala:87:24] wire out_f_roready_5 = out_roready_5 & out_romask_5; // @[RegisterRouter.scala:87:24] wire _out_T_61 = out_f_roready_5; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_5 = out_wivalid_5 & out_wimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_62 = out_f_wivalid_5; // @[RegisterRouter.scala:87:24] assign out_f_woready_5 = out_woready_5 & out_womask_5; // @[RegisterRouter.scala:87:24] assign valids_1_3 = out_f_woready_5; // @[RegisterRouter.scala:87:24] wire _out_T_63 = out_f_woready_5; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_59 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_147 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] assign newBytes_1_3 = out_f_woready_5 ? _out_T_59 : oldBytes_1_3; // @[RegisterRouter.scala:87:24] wire _out_T_64 = ~out_rimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_65 = ~out_wimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_66 = ~out_romask_5; // @[RegisterRouter.scala:87:24] wire _out_T_67 = ~out_womask_5; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_3 = {oldBytes_1_3, _out_prepend_T_3}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_68 = out_prepend_3; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_69 = _out_T_68; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_4 = _out_T_69; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_6 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_6 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_14 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_14 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24] wire out_rimask_6 = \|_out_rimask_T_6; // @[RegisterRouter.scala:87:24] wire out_wimask_6 = &_out_wimask_T_6; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_6 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_6 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_14 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_14 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24] wire out_romask_6 = \|_out_romask_T_6; // @[RegisterRouter.scala:87:24] wire out_womask_6 = &_out_womask_T_6; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_6 = out_rivalid_6 & out_rimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_71 = out_f_rivalid_6; // @[RegisterRouter.scala:87:24] wire out_f_roready_6 = out_roready_6 & out_romask_6; // @[RegisterRouter.scala:87:24] wire _out_T_72 = out_f_roready_6; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_6 = out_wivalid_6 & out_wimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_73 = out_f_wivalid_6; // @[RegisterRouter.scala:87:24] assign out_f_woready_6 = out_woready_6 & out_womask_6; // @[RegisterRouter.scala:87:24] assign valids_1_4 = out_f_woready_6; // @[RegisterRouter.scala:87:24] wire _out_T_74 = out_f_woready_6; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_70 = out_front_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_158 = out_front_bits_data[39:32]; // @[RegisterRouter.scala:87:24] assign newBytes_1_4 = out_f_woready_6 ? _out_T_70 : oldBytes_1_4; // @[RegisterRouter.scala:87:24] wire _out_T_75 = ~out_rimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_76 = ~out_wimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_77 = ~out_romask_6; // @[RegisterRouter.scala:87:24] wire _out_T_78 = ~out_womask_6; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_4 = {oldBytes_1_4, _out_prepend_T_4}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_79 = out_prepend_4; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_80 = _out_T_79; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_5 = _out_T_80; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_7 = out_frontMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_7 = out_frontMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_15 = out_frontMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_15 = out_frontMask[47:40]; // @[RegisterRouter.scala:87:24] wire out_rimask_7 = \|_out_rimask_T_7; // @[RegisterRouter.scala:87:24] wire out_wimask_7 = &_out_wimask_T_7; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_7 = out_backMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_7 = out_backMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_15 = out_backMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_15 = out_backMask[47:40]; // @[RegisterRouter.scala:87:24] wire out_romask_7 = \|_out_romask_T_7; // @[RegisterRouter.scala:87:24] wire out_womask_7 = &_out_womask_T_7; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_7 = out_rivalid_7 & out_rimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_82 = out_f_rivalid_7; // @[RegisterRouter.scala:87:24] wire out_f_roready_7 = out_roready_7 & out_romask_7; // @[RegisterRouter.scala:87:24] wire _out_T_83 = out_f_roready_7; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_7 = out_wivalid_7 & out_wimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_84 = out_f_wivalid_7; // @[RegisterRouter.scala:87:24] assign out_f_woready_7 = out_woready_7 & out_womask_7; // @[RegisterRouter.scala:87:24] assign valids_1_5 = out_f_woready_7; // @[RegisterRouter.scala:87:24] wire _out_T_85 = out_f_woready_7; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_81 = out_front_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_169 = out_front_bits_data[47:40]; // @[RegisterRouter.scala:87:24] assign newBytes_1_5 = out_f_woready_7 ? _out_T_81 : oldBytes_1_5; // @[RegisterRouter.scala:87:24] wire _out_T_86 = ~out_rimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_87 = ~out_wimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_88 = ~out_romask_7; // @[RegisterRouter.scala:87:24] wire _out_T_89 = ~out_womask_7; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_5 = {oldBytes_1_5, _out_prepend_T_5}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_90 = out_prepend_5; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_91 = _out_T_90; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_6 = _out_T_91; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_8 = out_frontMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_8 = out_frontMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_16 = out_frontMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_16 = out_frontMask[55:48]; // @[RegisterRouter.scala:87:24] wire out_rimask_8 = \|_out_rimask_T_8; // @[RegisterRouter.scala:87:24] wire out_wimask_8 = &_out_wimask_T_8; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_8 = out_backMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_8 = out_backMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_16 = out_backMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_16 = out_backMask[55:48]; // @[RegisterRouter.scala:87:24] wire out_romask_8 = \|_out_romask_T_8; // @[RegisterRouter.scala:87:24] wire out_womask_8 = &_out_womask_T_8; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_8 = out_rivalid_8 & out_rimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_93 = out_f_rivalid_8; // @[RegisterRouter.scala:87:24] wire out_f_roready_8 = out_roready_8 & out_romask_8; // @[RegisterRouter.scala:87:24] wire _out_T_94 = out_f_roready_8; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_8 = out_wivalid_8 & out_wimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_95 = out_f_wivalid_8; // @[RegisterRouter.scala:87:24] assign out_f_woready_8 = out_woready_8 & out_womask_8; // @[RegisterRouter.scala:87:24] assign valids_1_6 = out_f_woready_8; // @[RegisterRouter.scala:87:24] wire _out_T_96 = out_f_woready_8; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_92 = out_front_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_180 = out_front_bits_data[55:48]; // @[RegisterRouter.scala:87:24] assign newBytes_1_6 = out_f_woready_8 ? _out_T_92 : oldBytes_1_6; // @[RegisterRouter.scala:87:24] wire _out_T_97 = ~out_rimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_98 = ~out_wimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_99 = ~out_romask_8; // @[RegisterRouter.scala:87:24] wire _out_T_100 = ~out_womask_8; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_6 = {oldBytes_1_6, _out_prepend_T_6}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_101 = out_prepend_6; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_102 = _out_T_101; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_7 = _out_T_102; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_9 = out_frontMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_9 = out_frontMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_17 = out_frontMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_17 = out_frontMask[63:56]; // @[RegisterRouter.scala:87:24] wire out_rimask_9 = \|_out_rimask_T_9; // @[RegisterRouter.scala:87:24] wire out_wimask_9 = &_out_wimask_T_9; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_9 = out_backMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_9 = out_backMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_17 = out_backMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_17 = out_backMask[63:56]; // @[RegisterRouter.scala:87:24] wire out_romask_9 = \|_out_romask_T_9; // @[RegisterRouter.scala:87:24] wire out_womask_9 = &_out_womask_T_9; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_9 = out_rivalid_9 & out_rimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_104 = out_f_rivalid_9; // @[RegisterRouter.scala:87:24] wire out_f_roready_9 = out_roready_9 & out_romask_9; // @[RegisterRouter.scala:87:24] wire _out_T_105 = out_f_roready_9; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_9 = out_wivalid_9 & out_wimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_106 = out_f_wivalid_9; // @[RegisterRouter.scala:87:24] assign out_f_woready_9 = out_woready_9 & out_womask_9; // @[RegisterRouter.scala:87:24] assign valids_1_7 = out_f_woready_9; // @[RegisterRouter.scala:87:24] wire _out_T_107 = out_f_woready_9; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_103 = out_front_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_191 = out_front_bits_data[63:56]; // @[RegisterRouter.scala:87:24] assign newBytes_1_7 = out_f_woready_9 ? _out_T_103 : oldBytes_1_7; // @[RegisterRouter.scala:87:24] wire _out_T_108 = ~out_rimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_109 = ~out_wimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_110 = ~out_romask_9; // @[RegisterRouter.scala:87:24] wire _out_T_111 = ~out_womask_9; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_7 = {oldBytes_1_7, _out_prepend_T_7}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_112 = out_prepend_7; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_113 = _out_T_112; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_1_2 = _out_T_113; // @[MuxLiteral.scala:49:48] wire out_rimask_10 = \|_out_rimask_T_10; // @[RegisterRouter.scala:87:24] wire out_wimask_10 = &_out_wimask_T_10; // @[RegisterRouter.scala:87:24] wire out_romask_10 = \|_out_romask_T_10; // @[RegisterRouter.scala:87:24] wire out_womask_10 = &_out_womask_T_10; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_10 = out_rivalid_10 & out_rimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_115 = out_f_rivalid_10; // @[RegisterRouter.scala:87:24] wire out_f_roready_10 = out_roready_10 & out_romask_10; // @[RegisterRouter.scala:87:24] wire _out_T_116 = out_f_roready_10; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_10 = out_wivalid_10 & out_wimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_117 = out_f_wivalid_10; // @[RegisterRouter.scala:87:24] assign out_f_woready_10 = out_woready_10 & out_womask_10; // @[RegisterRouter.scala:87:24] assign valids_0 = out_f_woready_10; // @[RegisterRouter.scala:87:24] wire _out_T_118 = out_f_woready_10; // @[RegisterRouter.scala:87:24] assign newBytes_0 = out_f_woready_10 ? _out_T_114 : oldBytes_0; // @[RegisterRouter.scala:87:24] wire _out_T_119 = ~out_rimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_120 = ~out_wimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_121 = ~out_romask_10; // @[RegisterRouter.scala:87:24] wire _out_T_122 = ~out_womask_10; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_124 = _out_T_123; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_8 = _out_T_124; // @[RegisterRouter.scala:87:24] wire out_rimask_11 = \|_out_rimask_T_11; // @[RegisterRouter.scala:87:24] wire out_wimask_11 = &_out_wimask_T_11; // @[RegisterRouter.scala:87:24] wire out_romask_11 = \|_out_romask_T_11; // @[RegisterRouter.scala:87:24] wire out_womask_11 = &_out_womask_T_11; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_11 = out_rivalid_11 & out_rimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_126 = out_f_rivalid_11; // @[RegisterRouter.scala:87:24] wire out_f_roready_11 = out_roready_11 & out_romask_11; // @[RegisterRouter.scala:87:24] wire _out_T_127 = out_f_roready_11; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_11 = out_wivalid_11 & out_wimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_128 = out_f_wivalid_11; // @[RegisterRouter.scala:87:24] assign out_f_woready_11 = out_woready_11 & out_womask_11; // @[RegisterRouter.scala:87:24] assign valids_1 = out_f_woready_11; // @[RegisterRouter.scala:87:24] wire _out_T_129 = out_f_woready_11; // @[RegisterRouter.scala:87:24] assign newBytes_1 = out_f_woready_11 ? _out_T_125 : oldBytes_1; // @[RegisterRouter.scala:87:24] wire _out_T_130 = ~out_rimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_131 = ~out_wimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_132 = ~out_romask_11; // @[RegisterRouter.scala:87:24] wire _out_T_133 = ~out_womask_11; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_8 = {oldBytes_1, _out_prepend_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_134 = out_prepend_8; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_135 = _out_T_134; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_9 = _out_T_135; // @[RegisterRouter.scala:87:24] wire out_rimask_12 = \|_out_rimask_T_12; // @[RegisterRouter.scala:87:24] wire out_wimask_12 = &_out_wimask_T_12; // @[RegisterRouter.scala:87:24] wire out_romask_12 = \|_out_romask_T_12; // @[RegisterRouter.scala:87:24] wire out_womask_12 = &_out_womask_T_12; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_12 = out_rivalid_12 & out_rimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_137 = out_f_rivalid_12; // @[RegisterRouter.scala:87:24] wire out_f_roready_12 = out_roready_12 & out_romask_12; // @[RegisterRouter.scala:87:24] wire _out_T_138 = out_f_roready_12; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_12 = out_wivalid_12 & out_wimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_139 = out_f_wivalid_12; // @[RegisterRouter.scala:87:24] assign out_f_woready_12 = out_woready_12 & out_womask_12; // @[RegisterRouter.scala:87:24] assign valids_2 = out_f_woready_12; // @[RegisterRouter.scala:87:24] wire _out_T_140 = out_f_woready_12; // @[RegisterRouter.scala:87:24] assign newBytes_2 = out_f_woready_12 ? _out_T_136 : oldBytes_2; // @[RegisterRouter.scala:87:24] wire _out_T_141 = ~out_rimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_142 = ~out_wimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_143 = ~out_romask_12; // @[RegisterRouter.scala:87:24] wire _out_T_144 = ~out_womask_12; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_9 = {oldBytes_2, _out_prepend_T_9}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_145 = out_prepend_9; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_146 = _out_T_145; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_10 = _out_T_146; // @[RegisterRouter.scala:87:24] wire out_rimask_13 = \|_out_rimask_T_13; // @[RegisterRouter.scala:87:24] wire out_wimask_13 = &_out_wimask_T_13; // @[RegisterRouter.scala:87:24] wire out_romask_13 = \|_out_romask_T_13; // @[RegisterRouter.scala:87:24] wire out_womask_13 = &_out_womask_T_13; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_13 = out_rivalid_13 & out_rimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_148 = out_f_rivalid_13; // @[RegisterRouter.scala:87:24] wire out_f_roready_13 = out_roready_13 & out_romask_13; // @[RegisterRouter.scala:87:24] wire _out_T_149 = out_f_roready_13; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_13 = out_wivalid_13 & out_wimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_150 = out_f_wivalid_13; // @[RegisterRouter.scala:87:24] assign out_f_woready_13 = out_woready_13 & out_womask_13; // @[RegisterRouter.scala:87:24] assign valids_3 = out_f_woready_13; // @[RegisterRouter.scala:87:24] wire _out_T_151 = out_f_woready_13; // @[RegisterRouter.scala:87:24] assign newBytes_3 = out_f_woready_13 ? _out_T_147 : oldBytes_3; // @[RegisterRouter.scala:87:24] wire _out_T_152 = ~out_rimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_153 = ~out_wimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_154 = ~out_romask_13; // @[RegisterRouter.scala:87:24] wire _out_T_155 = ~out_womask_13; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_10 = {oldBytes_3, _out_prepend_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_156 = out_prepend_10; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_157 = _out_T_156; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_11 = _out_T_157; // @[RegisterRouter.scala:87:24] wire out_rimask_14 = \|_out_rimask_T_14; // @[RegisterRouter.scala:87:24] wire out_wimask_14 = &_out_wimask_T_14; // @[RegisterRouter.scala:87:24] wire out_romask_14 = \|_out_romask_T_14; // @[RegisterRouter.scala:87:24] wire out_womask_14 = &_out_womask_T_14; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_14 = out_rivalid_14 & out_rimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_159 = out_f_rivalid_14; // @[RegisterRouter.scala:87:24] wire out_f_roready_14 = out_roready_14 & out_romask_14; // @[RegisterRouter.scala:87:24] wire _out_T_160 = out_f_roready_14; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_14 = out_wivalid_14 & out_wimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_161 = out_f_wivalid_14; // @[RegisterRouter.scala:87:24] assign out_f_woready_14 = out_woready_14 & out_womask_14; // @[RegisterRouter.scala:87:24] assign valids_4 = out_f_woready_14; // @[RegisterRouter.scala:87:24] wire _out_T_162 = out_f_woready_14; // @[RegisterRouter.scala:87:24] assign newBytes_4 = out_f_woready_14 ? _out_T_158 : oldBytes_4; // @[RegisterRouter.scala:87:24] wire _out_T_163 = ~out_rimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_164 = ~out_wimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_165 = ~out_romask_14; // @[RegisterRouter.scala:87:24] wire _out_T_166 = ~out_womask_14; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_11 = {oldBytes_4, _out_prepend_T_11}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_167 = out_prepend_11; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_168 = _out_T_167; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_12 = _out_T_168; // @[RegisterRouter.scala:87:24] wire out_rimask_15 = \|_out_rimask_T_15; // @[RegisterRouter.scala:87:24] wire out_wimask_15 = &_out_wimask_T_15; // @[RegisterRouter.scala:87:24] wire out_romask_15 = \|_out_romask_T_15; // @[RegisterRouter.scala:87:24] wire out_womask_15 = &_out_womask_T_15; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_15 = out_rivalid_15 & out_rimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_170 = out_f_rivalid_15; // @[RegisterRouter.scala:87:24] wire out_f_roready_15 = out_roready_15 & out_romask_15; // @[RegisterRouter.scala:87:24] wire _out_T_171 = out_f_roready_15; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_15 = out_wivalid_15 & out_wimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_172 = out_f_wivalid_15; // @[RegisterRouter.scala:87:24] assign out_f_woready_15 = out_woready_15 & out_womask_15; // @[RegisterRouter.scala:87:24] assign valids_5 = out_f_woready_15; // @[RegisterRouter.scala:87:24] wire _out_T_173 = out_f_woready_15; // @[RegisterRouter.scala:87:24] assign newBytes_5 = out_f_woready_15 ? _out_T_169 : oldBytes_5; // @[RegisterRouter.scala:87:24] wire _out_T_174 = ~out_rimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_175 = ~out_wimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_176 = ~out_romask_15; // @[RegisterRouter.scala:87:24] wire _out_T_177 = ~out_womask_15; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_12 = {oldBytes_5, _out_prepend_T_12}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_178 = out_prepend_12; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_179 = _out_T_178; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_13 = _out_T_179; // @[RegisterRouter.scala:87:24] wire out_rimask_16 = \|_out_rimask_T_16; // @[RegisterRouter.scala:87:24] wire out_wimask_16 = &_out_wimask_T_16; // @[RegisterRouter.scala:87:24] wire out_romask_16 = \|_out_romask_T_16; // @[RegisterRouter.scala:87:24] wire out_womask_16 = &_out_womask_T_16; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_16 = out_rivalid_16 & out_rimask_16; // @[RegisterRouter.scala:87:24] wire _out_T_181 = out_f_rivalid_16; // @[RegisterRouter.scala:87:24] wire out_f_roready_16 = out_roready_16 & out_romask_16; // @[RegisterRouter.scala:87:24] wire _out_T_182 = out_f_roready_16; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_16 = out_wivalid_16 & out_wimask_16; // @[RegisterRouter.scala:87:24] wire _out_T_183 = out_f_wivalid_16; // @[RegisterRouter.scala:87:24] assign out_f_woready_16 = out_woready_16 & out_womask_16; // @[RegisterRouter.scala:87:24] assign valids_6 = out_f_woready_16; // @[RegisterRouter.scala:87:24] wire _out_T_184 = out_f_woready_16; // @[RegisterRouter.scala:87:24] assign newBytes_6 = out_f_woready_16 ? _out_T_180 : oldBytes_6; // @[RegisterRouter.scala:87:24] wire _out_T_185 = ~out_rimask_16; // @[RegisterRouter.scala:87:24] wire _out_T_186 = ~out_wimask_16; // @[RegisterRouter.scala:87:24] wire _out_T_187 = ~out_romask_16; // @[RegisterRouter.scala:87:24] wire _out_T_188 = ~out_womask_16; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_13 = {oldBytes_6, _out_prepend_T_13}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_189 = out_prepend_13; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_190 = _out_T_189; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_14 = _out_T_190; // @[RegisterRouter.scala:87:24] wire out_rimask_17 = \|_out_rimask_T_17; // @[RegisterRouter.scala:87:24] wire out_wimask_17 = &_out_wimask_T_17; // @[RegisterRouter.scala:87:24] wire out_romask_17 = \|_out_romask_T_17; // @[RegisterRouter.scala:87:24] wire out_womask_17 = &_out_womask_T_17; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_17 = out_rivalid_17 & out_rimask_17; // @[RegisterRouter.scala:87:24] wire _out_T_192 = out_f_rivalid_17; // @[RegisterRouter.scala:87:24] wire out_f_roready_17 = out_roready_17 & out_romask_17; // @[RegisterRouter.scala:87:24] wire _out_T_193 = out_f_roready_17; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_17 = out_wivalid_17 & out_wimask_17; // @[RegisterRouter.scala:87:24] wire _out_T_194 = out_f_wivalid_17; // @[RegisterRouter.scala:87:24] assign out_f_woready_17 = out_woready_17 & out_womask_17; // @[RegisterRouter.scala:87:24] assign valids_7 = out_f_woready_17; // @[RegisterRouter.scala:87:24] wire _out_T_195 = out_f_woready_17; // @[RegisterRouter.scala:87:24] assign newBytes_7 = out_f_woready_17 ? _out_T_191 : oldBytes_7; // @[RegisterRouter.scala:87:24] wire _out_T_196 = ~out_rimask_17; // @[RegisterRouter.scala:87:24] wire _out_T_197 = ~out_wimask_17; // @[RegisterRouter.scala:87:24] wire _out_T_198 = ~out_romask_17; // @[RegisterRouter.scala:87:24] wire _out_T_199 = ~out_womask_17; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_14 = {oldBytes_7, _out_prepend_T_14}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_200 = out_prepend_14; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_201 = _out_T_200; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_1_1 = _out_T_201; // @[MuxLiteral.scala:49:48] wire _out_iindex_T = out_front_bits_index[0]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T = out_front_bits_index[0]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_1 = out_front_bits_index[1]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_1 = out_front_bits_index[1]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_2 = out_front_bits_index[2]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_2 = out_front_bits_index[2]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_3 = out_front_bits_index[3]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_3 = out_front_bits_index[3]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_4 = out_front_bits_index[4]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_4 = out_front_bits_index[4]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_5 = out_front_bits_index[5]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_5 = out_front_bits_index[5]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_6 = out_front_bits_index[6]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_6 = out_front_bits_index[6]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_7 = out_front_bits_index[7]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_7 = out_front_bits_index[7]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_8 = out_front_bits_index[8]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_8 = out_front_bits_index[8]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_9 = out_front_bits_index[9]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_9 = out_front_bits_index[9]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_10 = out_front_bits_index[10]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_10 = out_front_bits_index[10]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_11 = out_front_bits_index[11]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_11 = out_front_bits_index[11]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_12 = out_front_bits_index[12]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_12 = out_front_bits_index[12]; // @[RegisterRouter.scala:87:24] wire [1:0] out_iindex = {_out_iindex_T_12, _out_iindex_T_11}; // @[RegisterRouter.scala:87:24] wire [1:0] out_oindex = {_out_oindex_T_12, _out_oindex_T_11}; // @[RegisterRouter.scala:87:24] wire [3:0] _out_frontSel_T = 4'h1 << out_iindex; // @[OneHot.scala:58:35] wire out_frontSel_0 = _out_frontSel_T[0]; // @[OneHot.scala:58:35] wire out_frontSel_1 = _out_frontSel_T[1]; // @[OneHot.scala:58:35] wire out_frontSel_2 = _out_frontSel_T[2]; // @[OneHot.scala:58:35] wire out_frontSel_3 = _out_frontSel_T[3]; // @[OneHot.scala:58:35] wire [3:0] _out_backSel_T = 4'h1 << out_oindex; // @[OneHot.scala:58:35] wire out_backSel_0 = _out_backSel_T[0]; // @[OneHot.scala:58:35] wire out_backSel_1 = _out_backSel_T[1]; // @[OneHot.scala:58:35] wire out_backSel_2 = _out_backSel_T[2]; // @[OneHot.scala:58:35] wire out_backSel_3 = _out_backSel_T[3]; // @[OneHot.scala:58:35] wire _GEN_2 = in_valid & out_front_ready; // @[RegisterRouter.scala:73:18, :87:24] wire _out_rifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T = _GEN_2; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T = _GEN_2; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1 = _out_rifireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_2 = _out_rifireMux_T_1 & out_frontSel_0; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_3 = _out_rifireMux_T_2 & _out_T; // @[RegisterRouter.scala:87:24] assign out_rivalid_0 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_1 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_4 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_6 = _out_rifireMux_T_1 & out_frontSel_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_7 = _out_rifireMux_T_6 & _out_T_4; // @[RegisterRouter.scala:87:24] assign out_rivalid_10 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_11 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_12 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_13 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_14 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_15 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_16 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_17 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_8 = ~_out_T_4; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_10 = _out_rifireMux_T_1 & out_frontSel_2; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_11 = _out_rifireMux_T_10 & _out_T_2; // @[RegisterRouter.scala:87:24] assign out_rivalid_2 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_3 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_4 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_5 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_6 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_7 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_8 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_9 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_12 = ~_out_T_2; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_14 = _out_rifireMux_T_1 & out_frontSel_3; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_15 = _out_rifireMux_T_14; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_2 = _out_wifireMux_T & _out_wifireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_3 = _out_wifireMux_T_2 & out_frontSel_0; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_4 = _out_wifireMux_T_3 & _out_T; // @[RegisterRouter.scala:87:24] assign out_wivalid_0 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_1 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_5 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_7 = _out_wifireMux_T_2 & out_frontSel_1; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_8 = _out_wifireMux_T_7 & _out_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_10 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_11 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_12 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_13 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_14 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_15 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_16 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_17 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_9 = ~_out_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_11 = _out_wifireMux_T_2 & out_frontSel_2; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_12 = _out_wifireMux_T_11 & _out_T_2; // @[RegisterRouter.scala:87:24] assign out_wivalid_2 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_3 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_4 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_5 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_6 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_7 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_8 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_9 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_13 = ~_out_T_2; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_15 = _out_wifireMux_T_2 & out_frontSel_3; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_16 = _out_wifireMux_T_15; // @[RegisterRouter.scala:87:24] wire _GEN_3 = out_front_valid & out_ready; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T = _GEN_3; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T = _GEN_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1 = _out_rofireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_2 = _out_rofireMux_T_1 & out_backSel_0; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_3 = _out_rofireMux_T_2 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_roready_0 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_1 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_4 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_6 = _out_rofireMux_T_1 & out_backSel_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_7 = _out_rofireMux_T_6 & _out_T_5; // @[RegisterRouter.scala:87:24] assign out_roready_10 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_11 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_12 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_13 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_14 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_15 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_16 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_17 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_8 = ~_out_T_5; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_10 = _out_rofireMux_T_1 & out_backSel_2; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_11 = _out_rofireMux_T_10 & _out_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_2 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_3 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_4 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_5 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_6 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_7 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_8 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_9 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_12 = ~_out_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_14 = _out_rofireMux_T_1 & out_backSel_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_15 = _out_rofireMux_T_14; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_2 = _out_wofireMux_T & _out_wofireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_3 = _out_wofireMux_T_2 & out_backSel_0; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_4 = _out_wofireMux_T_3 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_woready_0 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_1 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_5 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_7 = _out_wofireMux_T_2 & out_backSel_1; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_8 = _out_wofireMux_T_7 & _out_T_5; // @[RegisterRouter.scala:87:24] assign out_woready_10 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_11 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_12 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_13 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_14 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_15 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_16 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_17 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_9 = ~_out_T_5; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_11 = _out_wofireMux_T_2 & out_backSel_2; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_12 = _out_wofireMux_T_11 & _out_T_3; // @[RegisterRouter.scala:87:24] assign out_woready_2 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_3 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_4 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_5 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_6 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_7 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_8 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_9 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_13 = ~_out_T_3; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_15 = _out_wofireMux_T_2 & out_backSel_3; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_16 = _out_wofireMux_T_15; // @[RegisterRouter.scala:87:24] assign in_ready = _out_in_ready_T; // @[RegisterRouter.scala:73:18, :87:24] assign out_front_valid = _out_front_valid_T; // @[RegisterRouter.scala:87:24] assign out_front_ready = _out_front_ready_T; // @[RegisterRouter.scala:87:24] assign out_valid = _out_out_valid_T; // @[RegisterRouter.scala:87:24] wire [3:0] _GEN_4 = {{1'h1}, {_out_out_bits_data_WIRE_2}, {_out_out_bits_data_WIRE_1}, {_out_out_bits_data_WIRE_0}}; // @[MuxLiteral.scala:49:{10,48}] wire _out_out_bits_data_T_1 = _GEN_4[out_oindex]; // @[MuxLiteral.scala:49:10] wire [63:0] _out_out_bits_data_WIRE_1_0 = {32'h0, _out_T_25}; // @[MuxLiteral.scala:49:48] wire [3:0][63:0] _GEN_5 = {{64'h0}, {_out_out_bits_data_WIRE_1_2}, {_out_out_bits_data_WIRE_1_1}, {_out_out_bits_data_WIRE_1_0}}; // @[MuxLiteral.scala:49:{10,48}] wire [63:0] _out_out_bits_data_T_3 = _GEN_5[out_oindex]; // @[MuxLiteral.scala:49:10] assign _out_out_bits_data_T_4 = _out_out_bits_data_T_1 ? _out_out_bits_data_T_3 : 64'h0; // @[MuxLiteral.scala:49:10] assign out_bits_data = _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24] assign nodeIn_d_bits_size = nodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign nodeIn_d_bits_source = nodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign nodeIn_d_bits_opcode = {2'h0, _nodeIn_d_bits_opcode_T}; // @[RegisterRouter.scala:105:{19,25}] always @(posedge clock) begin // @[CLINT.scala:65:9] if (reset) begin // @[CLINT.scala:65:9] time_0 <= 64'h0; // @[CLINT.scala:73:23] ipi_0 <= 1'h0; // @[CLINT.scala:78:41] end else begin // @[CLINT.scala:65:9] if (valids_1_0 \| valids_1_1 \| valids_1_2 \| valids_1_3 \| valids_1_4 \| valids_1_5 \| valids_1_6 \| valids_1_7) // @[RegField.scala:153:29, :154:27] time_0 <= _time_T_2; // @[RegField.scala:154:52] else if (io_rtcTick_0) // @[CLINT.scala:65:9] time_0 <= _time_T_1; // @[CLINT.scala:73:23, :74:38] if (out_f_woready) // @[RegisterRouter.scala:87:24] ipi_0 <= _out_T_6; // @[RegisterRouter.scala:87:24] end if (valids_0 \| valids_1 \| valids_2 \| valids_3 \| valids_4 \| valids_5 \| valids_6 \| valids_7) // @[RegField.scala:153:29, :154:27] timecmp_0 <= _timecmp_0_T; // @[RegField.scala:154:52] always @(posedge) TLMonitor_42 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] assign auto_int_out_0 = auto_int_out_0_0; // @[CLINT.scala:65:9] assign auto_int_out_1 = auto_int_out_1_0; // @[CLINT.scala:65:9] assign auto_in_a_ready = auto_in_a_ready_0; // @[CLINT.scala:65:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[CLINT.scala:65:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[CLINT.scala:65:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[CLINT.scala:65:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[CLINT.scala:65:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[CLINT.scala:65:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File util.scala: //**************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v3.common.{MicroOp} import boom.v3.exu.{BrUpdateInfo} / * Object to XOR fold a input register of fullLength into a compressedLength. / object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /* * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks / object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask) } def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) } } /* * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. / object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /* * Object to return a BR mask given a MicroOp mask and old BR mask. / object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask) out } } /* * Object to check if at least 1 bit matches in two masks / object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /* * Object to clear one bit in a mask given an index / object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /* * Object to shift a register over by one bit and concat a new one / object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /* * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. / object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /* * Object to increment an input value, wrapping it if * necessary. / object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /* * Object to decrement an input value, wrapping it if * necessary. / object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /* * Object to increment an input value, wrapping it if * necessary. / object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /* * Object to decrement an input value, wrapping it if * necessary. / object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /* * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. / object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc \| (b-1).U) } } /* * Object to rotate a signal left by one / object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /* * Object to sext a value to a particular length. / object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /* * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. / object ImmGen { import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U} def apply(ip: UInt, isel: UInt): SInt = { val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U \|\| isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J \|\| isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S \|\| isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt } } /* * Object to get the FP rounding mode out of a packed immediate. / object ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } } /* * Object to get the FP function fype from a packed immediate. * Note: only works if !(IS_B or IS_S) / object ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } } /* * Object to see if an instruction is a JALR. / object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /* * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). / object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /* * Object to return the lowest bit position after the head. / object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /* * Object to determine whether queue * index i0 is older than index i1. / object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } /* * Set all bits at or below the highest order '1'. / object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_\|_) } } /* * Set all bits at or above the lowest order '1'. / object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_\|_) } } /* * Transpose a matrix of Chisel Vecs. / object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /* * N-wide one-hot priority encoder. / object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /* * Connect the first k of n valid input interfaces to k output interfaces. / class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_\|\|_)) val out_valids = sels map (col => col.reduce(_\|\|_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /* * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). / class BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v3.common.BoomModule()(p) with boom.v3.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire) val do_deq = WireInit((io.deq.ready \|\| !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop) uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop)) io.deq.bits := out io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop) // For flow queue behavior. if (flow) { when (io.empty) { io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop) io.deq.bits := io.enq.bits io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) do_deq := false.B when (io.deq.ready) { do_enq := false.B } } } private val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /* * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" / def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) / def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) / def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) / def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /* * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) / def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /* * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) / def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /* * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line / def apply(strs: String)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } File consts.scala: //**************************************************************************** // Copyright (c) 2011 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Constants //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.common.constants import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util.Str import freechips.rocketchip.rocket.RVCExpander / * Mixin for issue queue types / trait IQType { val IQT_SZ = 3 val IQT_INT = 1.U(IQT_SZ.W) val IQT_MEM = 2.U(IQT_SZ.W) val IQT_FP = 4.U(IQT_SZ.W) val IQT_MFP = 6.U(IQT_SZ.W) } /* * Mixin for scalar operation constants / trait ScalarOpConstants { val X = BitPat("b?") val Y = BitPat("b1") val N = BitPat("b0") //********************************* // Extra Constants // Which branch predictor predicted us val BSRC_SZ = 2 val BSRC_1 = 0.U(BSRC_SZ.W) // 1-cycle branch pred val BSRC_2 = 1.U(BSRC_SZ.W) // 2-cycle branch pred val BSRC_3 = 2.U(BSRC_SZ.W) // 3-cycle branch pred val BSRC_C = 3.U(BSRC_SZ.W) // core branch resolution //******************************** // Control Signals // CFI types val CFI_SZ = 3 val CFI_X = 0.U(CFI_SZ.W) // Not a CFI instruction val CFI_BR = 1.U(CFI_SZ.W) // Branch val CFI_JAL = 2.U(CFI_SZ.W) // JAL val CFI_JALR = 3.U(CFI_SZ.W) // JALR // PC Select Signal val PC_PLUS4 = 0.U(2.W) // PC + 4 val PC_BRJMP = 1.U(2.W) // brjmp_target val PC_JALR = 2.U(2.W) // jump_reg_target // Branch Type val BR_N = 0.U(4.W) // Next val BR_NE = 1.U(4.W) // Branch on NotEqual val BR_EQ = 2.U(4.W) // Branch on Equal val BR_GE = 3.U(4.W) // Branch on Greater/Equal val BR_GEU = 4.U(4.W) // Branch on Greater/Equal Unsigned val BR_LT = 5.U(4.W) // Branch on Less Than val BR_LTU = 6.U(4.W) // Branch on Less Than Unsigned val BR_J = 7.U(4.W) // Jump val BR_JR = 8.U(4.W) // Jump Register // RS1 Operand Select Signal val OP1_RS1 = 0.U(2.W) // Register Source #1 val OP1_ZERO= 1.U(2.W) val OP1_PC = 2.U(2.W) val OP1_X = BitPat("b??") // RS2 Operand Select Signal val OP2_RS2 = 0.U(3.W) // Register Source #2 val OP2_IMM = 1.U(3.W) // immediate val OP2_ZERO= 2.U(3.W) // constant 0 val OP2_NEXT= 3.U(3.W) // constant 2/4 (for PC+2/4) val OP2_IMMC= 4.U(3.W) // for CSR imm found in RS1 val OP2_X = BitPat("b???") // Register File Write Enable Signal val REN_0 = false.B val REN_1 = true.B // Is 32b Word or 64b Doubldword? val SZ_DW = 1 val DW_X = true.B // Bool(xLen==64) val DW_32 = false.B val DW_64 = true.B val DW_XPR = true.B // Bool(xLen==64) // Memory Enable Signal val MEN_0 = false.B val MEN_1 = true.B val MEN_X = false.B // Immediate Extend Select val IS_I = 0.U(3.W) // I-Type (LD,ALU) val IS_S = 1.U(3.W) // S-Type (ST) val IS_B = 2.U(3.W) // SB-Type (BR) val IS_U = 3.U(3.W) // U-Type (LUI/AUIPC) val IS_J = 4.U(3.W) // UJ-Type (J/JAL) val IS_X = BitPat("b???") // Decode Stage Control Signals val RT_FIX = 0.U(2.W) val RT_FLT = 1.U(2.W) val RT_PAS = 3.U(2.W) // pass-through (prs1 := lrs1, etc) val RT_X = 2.U(2.W) // not-a-register (but shouldn't get a busy-bit, etc.) // TODO rename RT_NAR // Micro-op opcodes // TODO change micro-op opcodes into using enum val UOPC_SZ = 7 val uopX = BitPat.dontCare(UOPC_SZ) val uopNOP = 0.U(UOPC_SZ.W) val uopLD = 1.U(UOPC_SZ.W) val uopSTA = 2.U(UOPC_SZ.W) // store address generation val uopSTD = 3.U(UOPC_SZ.W) // store data generation val uopLUI = 4.U(UOPC_SZ.W) val uopADDI = 5.U(UOPC_SZ.W) val uopANDI = 6.U(UOPC_SZ.W) val uopORI = 7.U(UOPC_SZ.W) val uopXORI = 8.U(UOPC_SZ.W) val uopSLTI = 9.U(UOPC_SZ.W) val uopSLTIU= 10.U(UOPC_SZ.W) val uopSLLI = 11.U(UOPC_SZ.W) val uopSRAI = 12.U(UOPC_SZ.W) val uopSRLI = 13.U(UOPC_SZ.W) val uopSLL = 14.U(UOPC_SZ.W) val uopADD = 15.U(UOPC_SZ.W) val uopSUB = 16.U(UOPC_SZ.W) val uopSLT = 17.U(UOPC_SZ.W) val uopSLTU = 18.U(UOPC_SZ.W) val uopAND = 19.U(UOPC_SZ.W) val uopOR = 20.U(UOPC_SZ.W) val uopXOR = 21.U(UOPC_SZ.W) val uopSRA = 22.U(UOPC_SZ.W) val uopSRL = 23.U(UOPC_SZ.W) val uopBEQ = 24.U(UOPC_SZ.W) val uopBNE = 25.U(UOPC_SZ.W) val uopBGE = 26.U(UOPC_SZ.W) val uopBGEU = 27.U(UOPC_SZ.W) val uopBLT = 28.U(UOPC_SZ.W) val uopBLTU = 29.U(UOPC_SZ.W) val uopCSRRW= 30.U(UOPC_SZ.W) val uopCSRRS= 31.U(UOPC_SZ.W) val uopCSRRC= 32.U(UOPC_SZ.W) val uopCSRRWI=33.U(UOPC_SZ.W) val uopCSRRSI=34.U(UOPC_SZ.W) val uopCSRRCI=35.U(UOPC_SZ.W) val uopJ = 36.U(UOPC_SZ.W) val uopJAL = 37.U(UOPC_SZ.W) val uopJALR = 38.U(UOPC_SZ.W) val uopAUIPC= 39.U(UOPC_SZ.W) //val uopSRET = 40.U(UOPC_SZ.W) val uopCFLSH= 41.U(UOPC_SZ.W) val uopFENCE= 42.U(UOPC_SZ.W) val uopADDIW= 43.U(UOPC_SZ.W) val uopADDW = 44.U(UOPC_SZ.W) val uopSUBW = 45.U(UOPC_SZ.W) val uopSLLIW= 46.U(UOPC_SZ.W) val uopSLLW = 47.U(UOPC_SZ.W) val uopSRAIW= 48.U(UOPC_SZ.W) val uopSRAW = 49.U(UOPC_SZ.W) val uopSRLIW= 50.U(UOPC_SZ.W) val uopSRLW = 51.U(UOPC_SZ.W) val uopMUL = 52.U(UOPC_SZ.W) val uopMULH = 53.U(UOPC_SZ.W) val uopMULHU= 54.U(UOPC_SZ.W) val uopMULHSU=55.U(UOPC_SZ.W) val uopMULW = 56.U(UOPC_SZ.W) val uopDIV = 57.U(UOPC_SZ.W) val uopDIVU = 58.U(UOPC_SZ.W) val uopREM = 59.U(UOPC_SZ.W) val uopREMU = 60.U(UOPC_SZ.W) val uopDIVW = 61.U(UOPC_SZ.W) val uopDIVUW= 62.U(UOPC_SZ.W) val uopREMW = 63.U(UOPC_SZ.W) val uopREMUW= 64.U(UOPC_SZ.W) val uopFENCEI = 65.U(UOPC_SZ.W) // = 66.U(UOPC_SZ.W) val uopAMO_AG = 67.U(UOPC_SZ.W) // AMO-address gen (use normal STD for datagen) val uopFMV_W_X = 68.U(UOPC_SZ.W) val uopFMV_D_X = 69.U(UOPC_SZ.W) val uopFMV_X_W = 70.U(UOPC_SZ.W) val uopFMV_X_D = 71.U(UOPC_SZ.W) val uopFSGNJ_S = 72.U(UOPC_SZ.W) val uopFSGNJ_D = 73.U(UOPC_SZ.W) val uopFCVT_S_D = 74.U(UOPC_SZ.W) val uopFCVT_D_S = 75.U(UOPC_SZ.W) val uopFCVT_S_X = 76.U(UOPC_SZ.W) val uopFCVT_D_X = 77.U(UOPC_SZ.W) val uopFCVT_X_S = 78.U(UOPC_SZ.W) val uopFCVT_X_D = 79.U(UOPC_SZ.W) val uopCMPR_S = 80.U(UOPC_SZ.W) val uopCMPR_D = 81.U(UOPC_SZ.W) val uopFCLASS_S = 82.U(UOPC_SZ.W) val uopFCLASS_D = 83.U(UOPC_SZ.W) val uopFMINMAX_S = 84.U(UOPC_SZ.W) val uopFMINMAX_D = 85.U(UOPC_SZ.W) // = 86.U(UOPC_SZ.W) val uopFADD_S = 87.U(UOPC_SZ.W) val uopFSUB_S = 88.U(UOPC_SZ.W) val uopFMUL_S = 89.U(UOPC_SZ.W) val uopFADD_D = 90.U(UOPC_SZ.W) val uopFSUB_D = 91.U(UOPC_SZ.W) val uopFMUL_D = 92.U(UOPC_SZ.W) val uopFMADD_S = 93.U(UOPC_SZ.W) val uopFMSUB_S = 94.U(UOPC_SZ.W) val uopFNMADD_S = 95.U(UOPC_SZ.W) val uopFNMSUB_S = 96.U(UOPC_SZ.W) val uopFMADD_D = 97.U(UOPC_SZ.W) val uopFMSUB_D = 98.U(UOPC_SZ.W) val uopFNMADD_D = 99.U(UOPC_SZ.W) val uopFNMSUB_D = 100.U(UOPC_SZ.W) val uopFDIV_S = 101.U(UOPC_SZ.W) val uopFDIV_D = 102.U(UOPC_SZ.W) val uopFSQRT_S = 103.U(UOPC_SZ.W) val uopFSQRT_D = 104.U(UOPC_SZ.W) val uopWFI = 105.U(UOPC_SZ.W) // pass uop down the CSR pipeline val uopERET = 106.U(UOPC_SZ.W) // pass uop down the CSR pipeline, also is ERET val uopSFENCE = 107.U(UOPC_SZ.W) val uopROCC = 108.U(UOPC_SZ.W) val uopMOV = 109.U(UOPC_SZ.W) // conditional mov decoded from "add rd, x0, rs2" // The Bubble Instruction (Machine generated NOP) // Insert (XOR x0,x0,x0) which is different from software compiler // generated NOPs which are (ADDI x0, x0, 0). // Reasoning for this is to let visualizers and stat-trackers differentiate // between software NOPs and machine-generated Bubbles in the pipeline. val BUBBLE = (0x4033).U(32.W) def NullMicroOp()(implicit p: Parameters): boom.v3.common.MicroOp = { val uop = Wire(new boom.v3.common.MicroOp) uop := DontCare // Overridden in the following lines uop.uopc := uopNOP // maybe not required, but helps on asserts that try to catch spurious behavior uop.bypassable := false.B uop.fp_val := false.B uop.uses_stq := false.B uop.uses_ldq := false.B uop.pdst := 0.U uop.dst_rtype := RT_X val cs = Wire(new boom.v3.common.CtrlSignals()) cs := DontCare // Overridden in the following lines cs.br_type := BR_N cs.csr_cmd := freechips.rocketchip.rocket.CSR.N cs.is_load := false.B cs.is_sta := false.B cs.is_std := false.B uop.ctrl := cs uop } } / * Mixin for RISCV constants / trait RISCVConstants { // abstract out instruction decode magic numbers val RD_MSB = 11 val RD_LSB = 7 val RS1_MSB = 19 val RS1_LSB = 15 val RS2_MSB = 24 val RS2_LSB = 20 val RS3_MSB = 31 val RS3_LSB = 27 val CSR_ADDR_MSB = 31 val CSR_ADDR_LSB = 20 val CSR_ADDR_SZ = 12 // location of the fifth bit in the shamt (for checking for illegal ops for SRAIW,etc.) val SHAMT_5_BIT = 25 val LONGEST_IMM_SZ = 20 val X0 = 0.U val RA = 1.U // return address register // memory consistency model // The C/C++ atomics MCM requires that two loads to the same address maintain program order. // The Cortex A9 does NOT enforce load/load ordering (which leads to buggy behavior). val MCM_ORDER_DEPENDENT_LOADS = true val jal_opc = (0x6f).U val jalr_opc = (0x67).U def GetUop(inst: UInt): UInt = inst(6,0) def GetRd (inst: UInt): UInt = inst(RD_MSB,RD_LSB) def GetRs1(inst: UInt): UInt = inst(RS1_MSB,RS1_LSB) def ExpandRVC(inst: UInt)(implicit p: Parameters): UInt = { val rvc_exp = Module(new RVCExpander) rvc_exp.io.in := inst Mux(rvc_exp.io.rvc, rvc_exp.io.out.bits, inst) } // Note: Accepts only EXPANDED rvc instructions def ComputeBranchTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = { val b_imm32 = Cat(Fill(20,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) ((pc.asSInt + b_imm32.asSInt).asSInt & (-2).S).asUInt } // Note: Accepts only EXPANDED rvc instructions def ComputeJALTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = { val j_imm32 = Cat(Fill(12,inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) ((pc.asSInt + j_imm32.asSInt).asSInt & (-2).S).asUInt } // Note: Accepts only EXPANDED rvc instructions def GetCfiType(inst: UInt)(implicit p: Parameters): UInt = { val bdecode = Module(new boom.v3.exu.BranchDecode) bdecode.io.inst := inst bdecode.io.pc := 0.U bdecode.io.out.cfi_type } } /* * Mixin for exception cause constants / trait ExcCauseConstants { // a memory disambigious misspeculation occurred val MINI_EXCEPTION_MEM_ORDERING = 16.U val MINI_EXCEPTION_CSR_REPLAY = 17.U require (!freechips.rocketchip.rocket.Causes.all.contains(16)) require (!freechips.rocketchip.rocket.Causes.all.contains(17)) } File issue-slot.scala: //*************************************************************************** // Copyright (c) 2015 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Issue Slot Logic //-------------------------------------------------------------------------- //------------------------------------------------------------------------------ // // Note: stores (and AMOs) are "broken down" into 2 uops, but stored within a single issue-slot. // TODO XXX make a separate issueSlot for MemoryIssueSlots, and only they break apart stores. // TODO Disable ldspec for FP queue. package boom.v3.exu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import boom.v3.common._ import boom.v3.util._ import FUConstants._ / * IO bundle to interact with Issue slot * * @param numWakeupPorts number of wakeup ports for the slot / class IssueSlotIO(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomBundle { val valid = Output(Bool()) val will_be_valid = Output(Bool()) // TODO code review, do we need this signal so explicitely? val request = Output(Bool()) val request_hp = Output(Bool()) val grant = Input(Bool()) val brupdate = Input(new BrUpdateInfo()) val kill = Input(Bool()) // pipeline flush val clear = Input(Bool()) // entry being moved elsewhere (not mutually exclusive with grant) val ldspec_miss = Input(Bool()) // Previous cycle's speculative load wakeup was mispredicted. val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new IqWakeup(maxPregSz)))) val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W))) val spec_ld_wakeup = Flipped(Vec(memWidth, Valid(UInt(width=maxPregSz.W)))) val in_uop = Flipped(Valid(new MicroOp())) // if valid, this WILL overwrite an entry! val out_uop = Output(new MicroOp()) // the updated slot uop; will be shifted upwards in a collasping queue. val uop = Output(new MicroOp()) // the current Slot's uop. Sent down the pipeline when issued. val debug = { val result = new Bundle { val p1 = Bool() val p2 = Bool() val p3 = Bool() val ppred = Bool() val state = UInt(width=2.W) } Output(result) } } /* * Single issue slot. Holds a uop within the issue queue * * @param numWakeupPorts number of wakeup ports / class IssueSlot(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomModule with IssueUnitConstants { val io = IO(new IssueSlotIO(numWakeupPorts)) // slot invalid? // slot is valid, holding 1 uop // slot is valid, holds 2 uops (like a store) def is_invalid = state === s_invalid def is_valid = state =/= s_invalid val next_state = Wire(UInt()) // the next state of this slot (which might then get moved to a new slot) val next_uopc = Wire(UInt()) // the next uopc of this slot (which might then get moved to a new slot) val next_lrs1_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot) val next_lrs2_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot) val state = RegInit(s_invalid) val p1 = RegInit(false.B) val p2 = RegInit(false.B) val p3 = RegInit(false.B) val ppred = RegInit(false.B) // Poison if woken up by speculative load. // Poison lasts 1 cycle (as ldMiss will come on the next cycle). // SO if poisoned is true, set it to false! val p1_poisoned = RegInit(false.B) val p2_poisoned = RegInit(false.B) p1_poisoned := false.B p2_poisoned := false.B val next_p1_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned) val next_p2_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned) val slot_uop = RegInit(NullMicroOp) val next_uop = Mux(io.in_uop.valid, io.in_uop.bits, slot_uop) //----------------------------------------------------------------------------- // next slot state computation // compute the next state for THIS entry slot (in a collasping queue, the // current uop may get moved elsewhere, and a new uop can enter when (io.kill) { state := s_invalid } .elsewhen (io.in_uop.valid) { state := io.in_uop.bits.iw_state } .elsewhen (io.clear) { state := s_invalid } .otherwise { state := next_state } //----------------------------------------------------------------------------- // "update" state // compute the next state for the micro-op in this slot. This micro-op may // be moved elsewhere, so the "next_state" travels with it. // defaults next_state := state next_uopc := slot_uop.uopc next_lrs1_rtype := slot_uop.lrs1_rtype next_lrs2_rtype := slot_uop.lrs2_rtype when (io.kill) { next_state := s_invalid } .elsewhen ((io.grant && (state === s_valid_1)) \|\| (io.grant && (state === s_valid_2) && p1 && p2 && ppred)) { // try to issue this uop. when (!(io.ldspec_miss && (p1_poisoned \|\| p2_poisoned))) { next_state := s_invalid } } .elsewhen (io.grant && (state === s_valid_2)) { when (!(io.ldspec_miss && (p1_poisoned \|\| p2_poisoned))) { next_state := s_valid_1 when (p1) { slot_uop.uopc := uopSTD next_uopc := uopSTD slot_uop.lrs1_rtype := RT_X next_lrs1_rtype := RT_X } .otherwise { slot_uop.lrs2_rtype := RT_X next_lrs2_rtype := RT_X } } } when (io.in_uop.valid) { slot_uop := io.in_uop.bits assert (is_invalid \|\| io.clear \|\| io.kill, "trying to overwrite a valid issue slot.") } // Wakeup Compare Logic // these signals are the "next_p" for the current slot's micro-op. // they are important for shifting the current slot_uop up to an other entry. val next_p1 = WireInit(p1) val next_p2 = WireInit(p2) val next_p3 = WireInit(p3) val next_ppred = WireInit(ppred) when (io.in_uop.valid) { p1 := !(io.in_uop.bits.prs1_busy) p2 := !(io.in_uop.bits.prs2_busy) p3 := !(io.in_uop.bits.prs3_busy) ppred := !(io.in_uop.bits.ppred_busy) } when (io.ldspec_miss && next_p1_poisoned) { assert(next_uop.prs1 =/= 0.U, "Poison bit can't be set for prs1=x0!") p1 := false.B } when (io.ldspec_miss && next_p2_poisoned) { assert(next_uop.prs2 =/= 0.U, "Poison bit can't be set for prs2=x0!") p2 := false.B } for (i <- 0 until numWakeupPorts) { when (io.wakeup_ports(i).valid && (io.wakeup_ports(i).bits.pdst === next_uop.prs1)) { p1 := true.B } when (io.wakeup_ports(i).valid && (io.wakeup_ports(i).bits.pdst === next_uop.prs2)) { p2 := true.B } when (io.wakeup_ports(i).valid && (io.wakeup_ports(i).bits.pdst === next_uop.prs3)) { p3 := true.B } } when (io.pred_wakeup_port.valid && io.pred_wakeup_port.bits === next_uop.ppred) { ppred := true.B } for (w <- 0 until memWidth) { assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U), "Loads to x0 should never speculatively wakeup other instructions") } // TODO disable if FP IQ. for (w <- 0 until memWidth) { when (io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === next_uop.prs1 && next_uop.lrs1_rtype === RT_FIX) { p1 := true.B p1_poisoned := true.B assert (!next_p1_poisoned) } when (io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === next_uop.prs2 && next_uop.lrs2_rtype === RT_FIX) { p2 := true.B p2_poisoned := true.B assert (!next_p2_poisoned) } } // Handle branch misspeculations val next_br_mask = GetNewBrMask(io.brupdate, slot_uop) // was this micro-op killed by a branch? if yes, we can't let it be valid if // we compact it into an other entry when (IsKilledByBranch(io.brupdate, slot_uop)) { next_state := s_invalid } when (!io.in_uop.valid) { slot_uop.br_mask := next_br_mask } //------------------------------------------------------------- // Request Logic io.request := is_valid && p1 && p2 && p3 && ppred && !io.kill val high_priority = slot_uop.is_br \|\| slot_uop.is_jal \|\| slot_uop.is_jalr io.request_hp := io.request && high_priority when (state === s_valid_1) { io.request := p1 && p2 && p3 && ppred && !io.kill } .elsewhen (state === s_valid_2) { io.request := (p1 \|\| p2) && ppred && !io.kill } .otherwise { io.request := false.B } //assign outputs io.valid := is_valid io.uop := slot_uop io.uop.iw_p1_poisoned := p1_poisoned io.uop.iw_p2_poisoned := p2_poisoned // micro-op will vacate due to grant. val may_vacate = io.grant && ((state === s_valid_1) \|\| (state === s_valid_2) && p1 && p2 && ppred) val squash_grant = io.ldspec_miss && (p1_poisoned \|\| p2_poisoned) io.will_be_valid := is_valid && !(may_vacate && !squash_grant) io.out_uop := slot_uop io.out_uop.iw_state := next_state io.out_uop.uopc := next_uopc io.out_uop.lrs1_rtype := next_lrs1_rtype io.out_uop.lrs2_rtype := next_lrs2_rtype io.out_uop.br_mask := next_br_mask io.out_uop.prs1_busy := !p1 io.out_uop.prs2_busy := !p2 io.out_uop.prs3_busy := !p3 io.out_uop.ppred_busy := !ppred io.out_uop.iw_p1_poisoned := p1_poisoned io.out_uop.iw_p2_poisoned := p2_poisoned when (state === s_valid_2) { when (p1 && p2 && ppred) { ; // send out the entire instruction as one uop } .elsewhen (p1 && ppred) { io.uop.uopc := slot_uop.uopc io.uop.lrs2_rtype := RT_X } .elsewhen (p2 && ppred) { io.uop.uopc := uopSTD io.uop.lrs1_rtype := RT_X } } // debug outputs io.debug.p1 := p1 io.debug.p2 := p2 io.debug.p3 := p3 io.debug.ppred := ppred io.debug.state := state }	module IssueSlot_140( // @[issue-slot.scala:69:7] input clock, // @[issue-slot.scala:69:7] input reset, // @[issue-slot.scala:69:7] output io_valid, // @[issue-slot.scala:73:14] output io_will_be_valid, // @[issue-slot.scala:73:14] output io_request, // @[issue-slot.scala:73:14] output io_request_hp, // @[issue-slot.scala:73:14] input io_grant, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14] input io_brupdate_b2_valid, // @[issue-slot.scala:73:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14] input io_brupdate_b2_taken, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14] input io_kill, // @[issue-slot.scala:73:14] input io_clear, // @[issue-slot.scala:73:14] input io_ldspec_miss, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_2_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_2_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_2_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_3_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_3_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_3_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_4_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_4_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_4_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_5_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_5_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_5_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_6_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_6_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_6_bits_poisoned, // @[issue-slot.scala:73:14] input io_spec_ld_wakeup_0_valid, // @[issue-slot.scala:73:14] input [6:0] io_spec_ld_wakeup_0_bits, // @[issue-slot.scala:73:14] input io_in_uop_valid, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14] input io_in_uop_bits_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_in_uop_bits_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14] input io_in_uop_bits_taken, // @[issue-slot.scala:73:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14] input io_in_uop_bits_exception, // @[issue-slot.scala:73:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14] input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14] output io_out_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14] output io_out_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] output io_out_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] output io_out_uop_is_br, // @[issue-slot.scala:73:14] output io_out_uop_is_jalr, // @[issue-slot.scala:73:14] output io_out_uop_is_jal, // @[issue-slot.scala:73:14] output io_out_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_out_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14] output io_out_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:73:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_out_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14] output io_out_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14] output io_out_uop_mem_signed, // @[issue-slot.scala:73:14] output io_out_uop_is_fence, // @[issue-slot.scala:73:14] output io_out_uop_is_fencei, // @[issue-slot.scala:73:14] output io_out_uop_is_amo, // @[issue-slot.scala:73:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_out_uop_uses_stq, // @[issue-slot.scala:73:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_out_uop_is_unique, // @[issue-slot.scala:73:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14] output io_out_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_out_uop_frs3_en, // @[issue-slot.scala:73:14] output io_out_uop_fp_val, // @[issue-slot.scala:73:14] output io_out_uop_fp_single, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14] output io_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14] output io_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] output io_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] output io_uop_is_br, // @[issue-slot.scala:73:14] output io_uop_is_jalr, // @[issue-slot.scala:73:14] output io_uop_is_jal, // @[issue-slot.scala:73:14] output io_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14] output io_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_uop_ppred, // @[issue-slot.scala:73:14] output io_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14] output io_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14] output io_uop_mem_signed, // @[issue-slot.scala:73:14] output io_uop_is_fence, // @[issue-slot.scala:73:14] output io_uop_is_fencei, // @[issue-slot.scala:73:14] output io_uop_is_amo, // @[issue-slot.scala:73:14] output io_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_uop_uses_stq, // @[issue-slot.scala:73:14] output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_uop_is_unique, // @[issue-slot.scala:73:14] output io_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14] output io_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_uop_frs3_en, // @[issue-slot.scala:73:14] output io_uop_fp_val, // @[issue-slot.scala:73:14] output io_uop_fp_single, // @[issue-slot.scala:73:14] output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14] output io_debug_p1, // @[issue-slot.scala:73:14] output io_debug_p2, // @[issue-slot.scala:73:14] output io_debug_p3, // @[issue-slot.scala:73:14] output io_debug_ppred, // @[issue-slot.scala:73:14] output [1:0] io_debug_state // @[issue-slot.scala:73:14] ); wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7] wire io_ldspec_miss_0 = io_ldspec_miss; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_bits_poisoned_0 = io_wakeup_ports_0_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_bits_poisoned_0 = io_wakeup_ports_1_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_2_bits_pdst_0 = io_wakeup_ports_2_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_2_bits_poisoned_0 = io_wakeup_ports_2_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_3_bits_pdst_0 = io_wakeup_ports_3_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_3_bits_poisoned_0 = io_wakeup_ports_3_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_4_bits_pdst_0 = io_wakeup_ports_4_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_4_bits_poisoned_0 = io_wakeup_ports_4_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_5_valid_0 = io_wakeup_ports_5_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_5_bits_pdst_0 = io_wakeup_ports_5_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_5_bits_poisoned_0 = io_wakeup_ports_5_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_6_valid_0 = io_wakeup_ports_6_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_6_bits_pdst_0 = io_wakeup_ports_6_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_6_bits_poisoned_0 = io_wakeup_ports_6_bits_poisoned; // @[issue-slot.scala:69:7] wire io_spec_ld_wakeup_0_valid_0 = io_spec_ld_wakeup_0_valid; // @[issue-slot.scala:69:7] wire [6:0] io_spec_ld_wakeup_0_bits_0 = io_spec_ld_wakeup_0_bits; // @[issue-slot.scala:69:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p1_poisoned_0 = io_in_uop_bits_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p2_poisoned_0 = io_in_uop_bits_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7] wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:69:7] wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19] wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [15:0] slot_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19] wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire _io_valid_T; // @[issue-slot.scala:79:24] wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32] wire _io_request_hp_T; // @[issue-slot.scala:243:31] wire [6:0] next_uopc; // @[issue-slot.scala:82:29] wire [1:0] next_state; // @[issue-slot.scala:81:29] wire [15:0] next_br_mask; // @[util.scala:85:25] wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28] wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28] wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28] wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28] wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29] wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29] wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_out_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_out_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7] wire io_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7] wire io_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire io_debug_p1_0; // @[issue-slot.scala:69:7] wire io_debug_p2_0; // @[issue-slot.scala:69:7] wire io_debug_p3_0; // @[issue-slot.scala:69:7] wire io_debug_ppred_0; // @[issue-slot.scala:69:7] wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7] wire io_valid_0; // @[issue-slot.scala:69:7] wire io_will_be_valid_0; // @[issue-slot.scala:69:7] wire io_request_0; // @[issue-slot.scala:69:7] wire io_request_hp_0; // @[issue-slot.scala:69:7] assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29] assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29] assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29] assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29] reg [1:0] state; // @[issue-slot.scala:86:22] assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22] reg p1; // @[issue-slot.scala:87:22] assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22] wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25] reg p2; // @[issue-slot.scala:88:22] assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22] wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25] reg p3; // @[issue-slot.scala:89:22] assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22] wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25] reg ppred; // @[issue-slot.scala:90:22] assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22] wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28] reg p1_poisoned; // @[issue-slot.scala:95:28] assign io_out_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28] assign io_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28] reg p2_poisoned; // @[issue-slot.scala:96:28] assign io_out_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28] assign io_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28] wire next_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : p1_poisoned; // @[issue-slot.scala:69:7, :95:28, :99:29] wire next_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : p2_poisoned; // @[issue-slot.scala:69:7, :96:28, :100:29] reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25] reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25] assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25] assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_rvc; // @[issue-slot.scala:102:25] assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25] assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25] assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25] assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_is_br; // @[issue-slot.scala:102:25] assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jalr; // @[issue-slot.scala:102:25] assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jal; // @[issue-slot.scala:102:25] assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sfb; // @[issue-slot.scala:102:25] assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:102:25] assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:102:25] assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_edge_inst; // @[issue-slot.scala:102:25] assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25] assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_taken; // @[issue-slot.scala:102:25] assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25] assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25] assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:102:25] assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:102:25] assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:102:25] assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:102:25] assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25] assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25] assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25] assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25] assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_exception; // @[issue-slot.scala:102:25] assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25] assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bypassable; // @[issue-slot.scala:102:25] assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25] assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_mem_signed; // @[issue-slot.scala:102:25] assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fence; // @[issue-slot.scala:102:25] assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fencei; // @[issue-slot.scala:102:25] assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_amo; // @[issue-slot.scala:102:25] assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_stq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25] assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_unique; // @[issue-slot.scala:102:25] assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25] assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25] assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25] assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25] assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_val; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25] assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25] reg slot_uop_frs3_en; // @[issue-slot.scala:102:25] assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_val; // @[issue-slot.scala:102:25] assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_single; // @[issue-slot.scala:102:25] assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [15:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25] wire _T_7 = io_grant_0 & state == 2'h1 \| io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}] wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25] wire _T_14 = io_ldspec_miss_0 & (p1_poisoned \| p2_poisoned); // @[issue-slot.scala:69:7, :95:28, :96:28, :140:{28,44}] wire _GEN = _T_12 & ~_T_14; // @[issue-slot.scala:126:14, :139:{25,51}, :140:{11,28,62}, :141:18] wire _GEN_0 = io_kill_0 \| _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51] wire _GEN_1 = _GEN_0 \| ~(_T_12 & ~_T_14 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:{11,28,62}, :142:17, :143:23] assign next_uopc = _GEN_1 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51] assign next_lrs1_rtype = _GEN_1 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51] wire _GEN_2 = _GEN_0 \| ~_GEN \| p1; // @[issue-slot.scala:87:22, :102:25, :126:14, :131:18, :134:63, :139:51, :140:62, :141:18, :142:17] assign next_lrs2_rtype = _GEN_2 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17] wire _p1_T = ~io_in_uop_bits_prs1_busy_0; // @[issue-slot.scala:69:7, :169:11] wire _p2_T = ~io_in_uop_bits_prs2_busy_0; // @[issue-slot.scala:69:7, :170:11] wire _p3_T = ~io_in_uop_bits_prs3_busy_0; // @[issue-slot.scala:69:7, :171:11] wire _ppred_T = ~io_in_uop_bits_ppred_busy_0; // @[issue-slot.scala:69:7, :172:14] wire _T_22 = io_ldspec_miss_0 & next_p1_poisoned; // @[issue-slot.scala:69:7, :99:29, :175:24] wire _T_27 = io_ldspec_miss_0 & next_p2_poisoned; // @[issue-slot.scala:69:7, :100:29, :179:24] wire _T_85 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs1 & next_uop_lrs1_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :209:38, :210:{33,51}, :211:27] wire _T_93 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs2 & next_uop_lrs2_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :216:38, :217:{33,51}, :218:27]
Generate the Verilog code corresponding to the following Chisel files. File Pipeline.scala: package gemmini import chisel3._ import chisel3.util._ class Pipeline[T <: Data] (gen: T, latency: Int)(comb: Seq[T => T] = Seq.fill(latency+1)((x: T) => x)) extends Module { val io = IO(new Bundle { val in = Flipped(Decoupled(gen)) val out = Decoupled(gen) val busy = Output(Bool()) }) require(comb.size == latency+1, "length of combinational is incorrect") if (latency == 0) { io.in.ready := io.out.ready io.out.valid := io.in.valid io.out.bits := comb.head(io.in.bits) io.busy := io.in.valid } else { val stages = Reg(Vec(latency, gen)) val valids = RegInit(VecInit(Seq.fill(latency)(false.B))) val stalling = VecInit(Seq.fill(latency)(false.B)) io.busy := io.in.valid \|\| valids.reduce(_\|\|_) // Stall signals io.in.ready := !stalling.head stalling.last := valids.last && !io.out.ready (stalling.init, stalling.tail, valids.init).zipped.foreach { case (s1, s2, v1) => s1 := v1 && s2 } // Valid signals // When the pipeline stage ahead of you isn't stalling, then make yourself invalid io.out.valid := valids.last when(io.out.ready) { valids.last := false.B } (valids.init, stalling.tail).zipped.foreach { case (v1, s2) => when(!s2) { v1 := false.B } } // When the pipeline stage behind you is valid then become true when(io.in.fire) { valids.head := true.B } (valids.tail, valids.init).zipped.foreach { case (v2, v1) => when(v1) { v2 := true.B } } // Stages when(io.in.fire) { stages.head := comb.head(io.in.bits) } io.out.bits := comb.last(stages.last) ((stages.tail zip stages.init) zip (stalling.tail zip comb.tail.init)).foreach { case ((st2, st1), (s2, c1)) => when(!s2) { st2 := c1(st1) } } } } object Pipeline { def apply[T <: Data](in: ReadyValidIO[T], latency: Int, comb: Seq[T => T]): DecoupledIO[T] = { val p = Module(new Pipeline(in.bits.cloneType, latency)(comb)) p.io.in <> in p.io.out } def apply[T <: Data](in: ReadyValidIO[T], latency: Int): DecoupledIO[T] = { val p = Module(new Pipeline(in.bits.cloneType, latency)()) p.io.in <> in p.io.out } }	module Pipeline_5( // @[Pipeline.scala:6:7] input clock, // @[Pipeline.scala:6:7] input reset, // @[Pipeline.scala:6:7] output io_in_ready, // @[Pipeline.scala:7:14] input io_in_valid, // @[Pipeline.scala:7:14] input [127:0] io_in_bits_data, // @[Pipeline.scala:7:14] input io_in_bits_fromDMA, // @[Pipeline.scala:7:14] input io_out_ready, // @[Pipeline.scala:7:14] output io_out_valid, // @[Pipeline.scala:7:14] output [127:0] io_out_bits_data // @[Pipeline.scala:7:14] ); wire io_in_valid_0 = io_in_valid; // @[Pipeline.scala:6:7] wire [127:0] io_in_bits_data_0 = io_in_bits_data; // @[Pipeline.scala:6:7] wire io_in_bits_fromDMA_0 = io_in_bits_fromDMA; // @[Pipeline.scala:6:7] wire io_out_ready_0 = io_out_ready; // @[Pipeline.scala:6:7] wire _valids_WIRE_0 = 1'h0; // @[Pipeline.scala:22:33] wire _valids_WIRE_1 = 1'h0; // @[Pipeline.scala:22:33] wire _valids_WIRE_2 = 1'h0; // @[Pipeline.scala:22:33] wire _valids_WIRE_3 = 1'h0; // @[Pipeline.scala:22:33] wire _io_in_ready_T; // @[Pipeline.scala:27:20] wire _io_busy_T_3; // @[Pipeline.scala:24:28] wire io_in_ready_0; // @[Pipeline.scala:6:7] wire [127:0] io_out_bits_data_0; // @[Pipeline.scala:6:7] wire io_out_bits_fromDMA; // @[Pipeline.scala:6:7] wire io_out_valid_0; // @[Pipeline.scala:6:7] wire io_busy; // @[Pipeline.scala:6:7] reg [127:0] stages_0_data; // @[Pipeline.scala:21:21] reg stages_0_fromDMA; // @[Pipeline.scala:21:21] reg [127:0] stages_1_data; // @[Pipeline.scala:21:21] reg stages_1_fromDMA; // @[Pipeline.scala:21:21] reg [127:0] stages_2_data; // @[Pipeline.scala:21:21] reg stages_2_fromDMA; // @[Pipeline.scala:21:21] reg [127:0] stages_3_data; // @[Pipeline.scala:21:21] assign io_out_bits_data_0 = stages_3_data; // @[Pipeline.scala:6:7, :21:21] reg stages_3_fromDMA; // @[Pipeline.scala:21:21] assign io_out_bits_fromDMA = stages_3_fromDMA; // @[Pipeline.scala:6:7, :21:21] reg valids_0; // @[Pipeline.scala:22:25] reg valids_1; // @[Pipeline.scala:22:25] reg valids_2; // @[Pipeline.scala:22:25] reg valids_3; // @[Pipeline.scala:22:25] assign io_out_valid_0 = valids_3; // @[Pipeline.scala:6:7, :22:25] wire _stalling_0_T; // @[Pipeline.scala:30:16] wire _stalling_1_T; // @[Pipeline.scala:30:16] wire _stalling_2_T; // @[Pipeline.scala:30:16] wire _stalling_3_T_1; // @[Pipeline.scala:28:34] wire stalling_0; // @[Pipeline.scala:23:27] wire stalling_1; // @[Pipeline.scala:23:27] wire stalling_2; // @[Pipeline.scala:23:27] wire stalling_3; // @[Pipeline.scala:23:27] wire _io_busy_T = valids_0 \| valids_1; // @[Pipeline.scala:22:25, :24:46] wire _io_busy_T_1 = _io_busy_T \| valids_2; // @[Pipeline.scala:22:25, :24:46] wire _io_busy_T_2 = _io_busy_T_1 \| valids_3; // @[Pipeline.scala:22:25, :24:46] assign _io_busy_T_3 = io_in_valid_0 \| _io_busy_T_2; // @[Pipeline.scala:6:7, :24:{28,46}] assign io_busy = _io_busy_T_3; // @[Pipeline.scala:6:7, :24:28] assign _io_in_ready_T = ~stalling_0; // @[Pipeline.scala:23:27, :27:20] assign io_in_ready_0 = _io_in_ready_T; // @[Pipeline.scala:6:7, :27:20] wire _stalling_3_T = ~io_out_ready_0; // @[Pipeline.scala:6:7, :28:37] assign _stalling_3_T_1 = valids_3 & _stalling_3_T; // @[Pipeline.scala:22:25, :28:{34,37}] assign stalling_3 = _stalling_3_T_1; // @[Pipeline.scala:23:27, :28:34] assign _stalling_0_T = valids_0 & stalling_1; // @[Pipeline.scala:22:25, :23:27, :30:16] assign stalling_0 = _stalling_0_T; // @[Pipeline.scala:23:27, :30:16] assign _stalling_1_T = valids_1 & stalling_2; // @[Pipeline.scala:22:25, :23:27, :30:16] assign stalling_1 = _stalling_1_T; // @[Pipeline.scala:23:27, :30:16] assign _stalling_2_T = valids_2 & stalling_3; // @[Pipeline.scala:22:25, :23:27, :30:16] assign stalling_2 = _stalling_2_T; // @[Pipeline.scala:23:27, :30:16] wire _T_4 = io_in_ready_0 & io_in_valid_0; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[Pipeline.scala:6:7] if (_T_4) begin // @[Decoupled.scala:51:35] stages_0_data <= io_in_bits_data_0; // @[Pipeline.scala:6:7, :21:21] stages_0_fromDMA <= io_in_bits_fromDMA_0; // @[Pipeline.scala:6:7, :21:21] end if (stalling_1) begin // @[Pipeline.scala:23:27] end else begin // @[Pipeline.scala:23:27] stages_1_data <= stages_0_data; // @[Pipeline.scala:21:21] stages_1_fromDMA <= stages_0_fromDMA; // @[Pipeline.scala:21:21] end if (stalling_2) begin // @[Pipeline.scala:23:27] end else begin // @[Pipeline.scala:23:27] stages_2_data <= stages_1_data; // @[Pipeline.scala:21:21] stages_2_fromDMA <= stages_1_fromDMA; // @[Pipeline.scala:21:21] end if (stalling_3) begin // @[Pipeline.scala:23:27] end else begin // @[Pipeline.scala:23:27] stages_3_data <= stages_2_data; // @[Pipeline.scala:21:21] stages_3_fromDMA <= stages_2_fromDMA; // @[Pipeline.scala:21:21] end if (reset) begin // @[Pipeline.scala:6:7] valids_0 <= 1'h0; // @[Pipeline.scala:22:25] valids_1 <= 1'h0; // @[Pipeline.scala:22:25] valids_2 <= 1'h0; // @[Pipeline.scala:22:25] valids_3 <= 1'h0; // @[Pipeline.scala:22:25] end else begin // @[Pipeline.scala:6:7] valids_0 <= _T_4 \| stalling_1 & valids_0; // @[Decoupled.scala:51:35] valids_1 <= valids_0 \| stalling_2 & valids_1; // @[Pipeline.scala:22:25, :23:27, :40:17, :41:12, :49:16, :50:12] valids_2 <= valids_1 \| stalling_3 & valids_2; // @[Pipeline.scala:22:25, :23:27, :40:17, :41:12, :49:16, :50:12] valids_3 <= valids_2 \| ~io_out_ready_0 & valids_3; // @[Pipeline.scala:6:7, :22:25, :36:24, :37:19, :49:16, :50:12] end always @(posedge) assign io_in_ready = io_in_ready_0; // @[Pipeline.scala:6:7] assign io_out_valid = io_out_valid_0; // @[Pipeline.scala:6:7] assign io_out_bits_data = io_out_bits_data_0; // @[Pipeline.scala:6:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File primitives.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object lowMask { def apply(in: UInt, topBound: BigInt, bottomBound: BigInt): UInt = { require(topBound != bottomBound) val numInVals = BigInt(1)<<in.getWidth if (topBound < bottomBound) { lowMask(~in, numInVals - 1 - topBound, numInVals - 1 - bottomBound) } else if (numInVals > 64 /* Empirical /) { // For simulation performance, we should avoid generating // exteremely wide shifters, so we divide and conquer. // Empirically, this does not impact synthesis QoR. val mid = numInVals / 2 val msb = in(in.getWidth - 1) val lsbs = in(in.getWidth - 2, 0) if (mid < topBound) { if (mid <= bottomBound) { Mux(msb, lowMask(lsbs, topBound - mid, bottomBound - mid), 0.U ) } else { Mux(msb, lowMask(lsbs, topBound - mid, 0) ## ((BigInt(1)<<(mid - bottomBound).toInt) - 1).U, lowMask(lsbs, mid, bottomBound) ) } } else { ~Mux(msb, 0.U, ~lowMask(lsbs, topBound, bottomBound)) } } else { val shift = (BigInt(-1)<<numInVals.toInt).S>>in Reverse( shift( (numInVals - 1 - bottomBound).toInt, (numInVals - topBound).toInt ) ) } } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object countLeadingZeros { def apply(in: UInt): UInt = PriorityEncoder(in.asBools.reverse) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy2 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 1)>>1 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix 2 + 1, ix * 2).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 2).orR reducedVec.asUInt } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy4 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 3)>>2 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 4 + 3, ix * 4).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 4).orR reducedVec.asUInt } } File MulAddRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util._ import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFN_interIo(expWidth: Int, sigWidth: Int) extends Bundle { //*** ENCODE SOME OF THESE CASES IN FEWER BITS?: val isSigNaNAny = Bool() val isNaNAOrB = Bool() val isInfA = Bool() val isZeroA = Bool() val isInfB = Bool() val isZeroB = Bool() val signProd = Bool() val isNaNC = Bool() val isInfC = Bool() val isZeroC = Bool() val sExpSum = SInt((expWidth + 2).W) val doSubMags = Bool() val CIsDominant = Bool() val CDom_CAlignDist = UInt(log2Ceil(sigWidth + 1).W) val highAlignedSigC = UInt((sigWidth + 2).W) val bit0AlignedSigC = UInt(1.W) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFNToRaw_preMul(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFNToRaw_preMul_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val mulAddA = Output(UInt(sigWidth.W)) val mulAddB = Output(UInt(sigWidth.W)) val mulAddC = Output(UInt((sigWidth * 2).W)) val toPostMul = Output(new MulAddRecFN_interIo(expWidth, sigWidth)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ //* POSSIBLE TO REDUCE THIS BY 1 OR 2 BITS? (CURRENTLY 2 BITS BETWEEN //* UNSHIFTED C AND PRODUCT): val sigSumWidth = sigWidth * 3 + 3 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val rawA = rawFloatFromRecFN(expWidth, sigWidth, io.a) val rawB = rawFloatFromRecFN(expWidth, sigWidth, io.b) val rawC = rawFloatFromRecFN(expWidth, sigWidth, io.c) val signProd = rawA.sign ^ rawB.sign ^ io.op(1) //* REVIEW THE BIAS FOR 'sExpAlignedProd': val sExpAlignedProd = rawA.sExp +& rawB.sExp + (-(BigInt(1)<<expWidth) + sigWidth + 3).S val doSubMags = signProd ^ rawC.sign ^ io.op(0) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sNatCAlignDist = sExpAlignedProd - rawC.sExp val posNatCAlignDist = sNatCAlignDist(expWidth + 1, 0) val isMinCAlign = rawA.isZero \|\| rawB.isZero \|\| (sNatCAlignDist < 0.S) val CIsDominant = ! rawC.isZero && (isMinCAlign \|\| (posNatCAlignDist <= sigWidth.U)) val CAlignDist = Mux(isMinCAlign, 0.U, Mux(posNatCAlignDist < (sigSumWidth - 1).U, posNatCAlignDist(log2Ceil(sigSumWidth) - 1, 0), (sigSumWidth - 1).U ) ) val mainAlignedSigC = (Mux(doSubMags, ~rawC.sig, rawC.sig) ## Fill(sigSumWidth - sigWidth + 2, doSubMags)).asSInt>>CAlignDist val reduced4CExtra = (orReduceBy4(rawC.sig<<((sigSumWidth - sigWidth - 1) & 3)) & lowMask( CAlignDist>>2, //* NOT NEEDED?: // (sigSumWidth + 2)>>2, (sigSumWidth - 1)>>2, (sigSumWidth - sigWidth - 1)>>2 ) ).orR val alignedSigC = Cat(mainAlignedSigC>>3, Mux(doSubMags, mainAlignedSigC(2, 0).andR && ! reduced4CExtra, mainAlignedSigC(2, 0).orR \|\| reduced4CExtra ) ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ io.mulAddA := rawA.sig io.mulAddB := rawB.sig io.mulAddC := alignedSigC(sigWidth * 2, 1) io.toPostMul.isSigNaNAny := isSigNaNRawFloat(rawA) \|\| isSigNaNRawFloat(rawB) \|\| isSigNaNRawFloat(rawC) io.toPostMul.isNaNAOrB := rawA.isNaN \|\| rawB.isNaN io.toPostMul.isInfA := rawA.isInf io.toPostMul.isZeroA := rawA.isZero io.toPostMul.isInfB := rawB.isInf io.toPostMul.isZeroB := rawB.isZero io.toPostMul.signProd := signProd io.toPostMul.isNaNC := rawC.isNaN io.toPostMul.isInfC := rawC.isInf io.toPostMul.isZeroC := rawC.isZero io.toPostMul.sExpSum := Mux(CIsDominant, rawC.sExp, sExpAlignedProd - sigWidth.S) io.toPostMul.doSubMags := doSubMags io.toPostMul.CIsDominant := CIsDominant io.toPostMul.CDom_CAlignDist := CAlignDist(log2Ceil(sigWidth + 1) - 1, 0) io.toPostMul.highAlignedSigC := alignedSigC(sigSumWidth - 1, sigWidth * 2 + 1) io.toPostMul.bit0AlignedSigC := alignedSigC(0) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFNToRaw_postMul(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFNToRaw_postMul_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val fromPreMul = Input(new MulAddRecFN_interIo(expWidth, sigWidth)) val mulAddResult = Input(UInt((sigWidth * 2 + 1).W)) val roundingMode = Input(UInt(3.W)) val invalidExc = Output(Bool()) val rawOut = Output(new RawFloat(expWidth, sigWidth + 2)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigSumWidth = sigWidth * 3 + 3 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_min = (io.roundingMode === round_min) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val opSignC = io.fromPreMul.signProd ^ io.fromPreMul.doSubMags val sigSum = Cat(Mux(io.mulAddResult(sigWidth * 2), io.fromPreMul.highAlignedSigC + 1.U, io.fromPreMul.highAlignedSigC ), io.mulAddResult(sigWidth * 2 - 1, 0), io.fromPreMul.bit0AlignedSigC ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val CDom_sign = opSignC val CDom_sExp = io.fromPreMul.sExpSum - io.fromPreMul.doSubMags.zext val CDom_absSigSum = Mux(io.fromPreMul.doSubMags, ~sigSum(sigSumWidth - 1, sigWidth + 1), 0.U(1.W) ## //*** IF GAP IS REDUCED TO 1 BIT, MUST REDUCE THIS COMPONENT TO 1 BIT TOO: io.fromPreMul.highAlignedSigC(sigWidth + 1, sigWidth) ## sigSum(sigSumWidth - 3, sigWidth + 2) ) val CDom_absSigSumExtra = Mux(io.fromPreMul.doSubMags, (~sigSum(sigWidth, 1)).orR, sigSum(sigWidth + 1, 1).orR ) val CDom_mainSig = (CDom_absSigSum<<io.fromPreMul.CDom_CAlignDist)( sigWidth * 2 + 1, sigWidth - 3) val CDom_reduced4SigExtra = (orReduceBy4(CDom_absSigSum(sigWidth - 1, 0)<<(~sigWidth & 3)) & lowMask(io.fromPreMul.CDom_CAlignDist>>2, 0, sigWidth>>2)).orR val CDom_sig = Cat(CDom_mainSig>>3, CDom_mainSig(2, 0).orR \|\| CDom_reduced4SigExtra \|\| CDom_absSigSumExtra ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val notCDom_signSigSum = sigSum(sigWidth * 2 + 3) val notCDom_absSigSum = Mux(notCDom_signSigSum, ~sigSum(sigWidth * 2 + 2, 0), sigSum(sigWidth * 2 + 2, 0) + io.fromPreMul.doSubMags ) val notCDom_reduced2AbsSigSum = orReduceBy2(notCDom_absSigSum) val notCDom_normDistReduced2 = countLeadingZeros(notCDom_reduced2AbsSigSum) val notCDom_nearNormDist = notCDom_normDistReduced2<<1 val notCDom_sExp = io.fromPreMul.sExpSum - notCDom_nearNormDist.asUInt.zext val notCDom_mainSig = (notCDom_absSigSum<<notCDom_nearNormDist)( sigWidth * 2 + 3, sigWidth - 1) val notCDom_reduced4SigExtra = (orReduceBy2( notCDom_reduced2AbsSigSum(sigWidth>>1, 0)<<((sigWidth>>1) & 1)) & lowMask(notCDom_normDistReduced2>>1, 0, (sigWidth + 2)>>2) ).orR val notCDom_sig = Cat(notCDom_mainSig>>3, notCDom_mainSig(2, 0).orR \|\| notCDom_reduced4SigExtra ) val notCDom_completeCancellation = (notCDom_sig(sigWidth + 2, sigWidth + 1) === 0.U) val notCDom_sign = Mux(notCDom_completeCancellation, roundingMode_min, io.fromPreMul.signProd ^ notCDom_signSigSum ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val notNaN_isInfProd = io.fromPreMul.isInfA \|\| io.fromPreMul.isInfB val notNaN_isInfOut = notNaN_isInfProd \|\| io.fromPreMul.isInfC val notNaN_addZeros = (io.fromPreMul.isZeroA \|\| io.fromPreMul.isZeroB) && io.fromPreMul.isZeroC io.invalidExc := io.fromPreMul.isSigNaNAny \|\| (io.fromPreMul.isInfA && io.fromPreMul.isZeroB) \|\| (io.fromPreMul.isZeroA && io.fromPreMul.isInfB) \|\| (! io.fromPreMul.isNaNAOrB && (io.fromPreMul.isInfA \|\| io.fromPreMul.isInfB) && io.fromPreMul.isInfC && io.fromPreMul.doSubMags) io.rawOut.isNaN := io.fromPreMul.isNaNAOrB \|\| io.fromPreMul.isNaNC io.rawOut.isInf := notNaN_isInfOut //*** IMPROVE?: io.rawOut.isZero := notNaN_addZeros \|\| (! io.fromPreMul.CIsDominant && notCDom_completeCancellation) io.rawOut.sign := (notNaN_isInfProd && io.fromPreMul.signProd) \|\| (io.fromPreMul.isInfC && opSignC) \|\| (notNaN_addZeros && ! roundingMode_min && io.fromPreMul.signProd && opSignC) \|\| (notNaN_addZeros && roundingMode_min && (io.fromPreMul.signProd \|\| opSignC)) \|\| (! notNaN_isInfOut && ! notNaN_addZeros && Mux(io.fromPreMul.CIsDominant, CDom_sign, notCDom_sign)) io.rawOut.sExp := Mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp) io.rawOut.sig := Mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFN(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val mulAddRecFNToRaw_preMul = Module(new MulAddRecFNToRaw_preMul(expWidth, sigWidth)) val mulAddRecFNToRaw_postMul = Module(new MulAddRecFNToRaw_postMul(expWidth, sigWidth)) mulAddRecFNToRaw_preMul.io.op := io.op mulAddRecFNToRaw_preMul.io.a := io.a mulAddRecFNToRaw_preMul.io.b := io.b mulAddRecFNToRaw_preMul.io.c := io.c val mulAddResult = (mulAddRecFNToRaw_preMul.io.mulAddA * mulAddRecFNToRaw_preMul.io.mulAddB) +& mulAddRecFNToRaw_preMul.io.mulAddC mulAddRecFNToRaw_postMul.io.fromPreMul := mulAddRecFNToRaw_preMul.io.toPostMul mulAddRecFNToRaw_postMul.io.mulAddResult := mulAddResult mulAddRecFNToRaw_postMul.io.roundingMode := io.roundingMode //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundRawFNToRecFN = Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0)) roundRawFNToRecFN.io.invalidExc := mulAddRecFNToRaw_postMul.io.invalidExc roundRawFNToRecFN.io.infiniteExc := false.B roundRawFNToRecFN.io.in := mulAddRecFNToRaw_postMul.io.rawOut roundRawFNToRecFN.io.roundingMode := io.roundingMode roundRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundRawFNToRecFN.io.out io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags }	module MulAddRecFNToRaw_postMul_e5_s11( // @[MulAddRecFN.scala:169:7] input io_fromPreMul_isSigNaNAny, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isNaNAOrB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfA, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroA, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_signProd, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isNaNC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroC, // @[MulAddRecFN.scala:172:16] input [6:0] io_fromPreMul_sExpSum, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_doSubMags, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_CIsDominant, // @[MulAddRecFN.scala:172:16] input [3:0] io_fromPreMul_CDom_CAlignDist, // @[MulAddRecFN.scala:172:16] input [12:0] io_fromPreMul_highAlignedSigC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_bit0AlignedSigC, // @[MulAddRecFN.scala:172:16] input [22:0] io_mulAddResult, // @[MulAddRecFN.scala:172:16] input [2:0] io_roundingMode, // @[MulAddRecFN.scala:172:16] output io_invalidExc, // @[MulAddRecFN.scala:172:16] output io_rawOut_isNaN, // @[MulAddRecFN.scala:172:16] output io_rawOut_isInf, // @[MulAddRecFN.scala:172:16] output io_rawOut_isZero, // @[MulAddRecFN.scala:172:16] output io_rawOut_sign, // @[MulAddRecFN.scala:172:16] output [6:0] io_rawOut_sExp, // @[MulAddRecFN.scala:172:16] output [13:0] io_rawOut_sig // @[MulAddRecFN.scala:172:16] ); wire io_fromPreMul_isSigNaNAny_0 = io_fromPreMul_isSigNaNAny; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isNaNAOrB_0 = io_fromPreMul_isNaNAOrB; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfA_0 = io_fromPreMul_isInfA; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroA_0 = io_fromPreMul_isZeroA; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfB_0 = io_fromPreMul_isInfB; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroB_0 = io_fromPreMul_isZeroB; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_signProd_0 = io_fromPreMul_signProd; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isNaNC_0 = io_fromPreMul_isNaNC; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfC_0 = io_fromPreMul_isInfC; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroC_0 = io_fromPreMul_isZeroC; // @[MulAddRecFN.scala:169:7] wire [6:0] io_fromPreMul_sExpSum_0 = io_fromPreMul_sExpSum; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_doSubMags_0 = io_fromPreMul_doSubMags; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_CIsDominant_0 = io_fromPreMul_CIsDominant; // @[MulAddRecFN.scala:169:7] wire [3:0] io_fromPreMul_CDom_CAlignDist_0 = io_fromPreMul_CDom_CAlignDist; // @[MulAddRecFN.scala:169:7] wire [12:0] io_fromPreMul_highAlignedSigC_0 = io_fromPreMul_highAlignedSigC; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_bit0AlignedSigC_0 = io_fromPreMul_bit0AlignedSigC; // @[MulAddRecFN.scala:169:7] wire [22:0] io_mulAddResult_0 = io_mulAddResult; // @[MulAddRecFN.scala:169:7] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[MulAddRecFN.scala:169:7] wire _io_invalidExc_T_9; // @[MulAddRecFN.scala:273:57] wire _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:278:48] wire notNaN_isInfOut; // @[MulAddRecFN.scala:265:44] wire _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:282:25] wire _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:290:50] wire [6:0] _io_rawOut_sExp_T; // @[MulAddRecFN.scala:293:26] wire [13:0] _io_rawOut_sig_T; // @[MulAddRecFN.scala:294:25] wire io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7] wire [6:0] io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7] wire [13:0] io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7] wire io_invalidExc_0; // @[MulAddRecFN.scala:169:7] wire roundingMode_min = io_roundingMode_0 == 3'h2; // @[MulAddRecFN.scala:169:7, :186:45] wire opSignC = io_fromPreMul_signProd_0 ^ io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :190:42] wire _sigSum_T = io_mulAddResult_0[22]; // @[MulAddRecFN.scala:169:7, :192:32] wire [13:0] _sigSum_T_1 = {1'h0, io_fromPreMul_highAlignedSigC_0} + 14'h1; // @[MulAddRecFN.scala:169:7, :193:47] wire [12:0] _sigSum_T_2 = _sigSum_T_1[12:0]; // @[MulAddRecFN.scala:193:47] wire [12:0] _sigSum_T_3 = _sigSum_T ? _sigSum_T_2 : io_fromPreMul_highAlignedSigC_0; // @[MulAddRecFN.scala:169:7, :192:{16,32}, :193:47] wire [21:0] _sigSum_T_4 = io_mulAddResult_0[21:0]; // @[MulAddRecFN.scala:169:7, :196:28] wire [34:0] sigSum_hi = {_sigSum_T_3, _sigSum_T_4}; // @[MulAddRecFN.scala:192:{12,16}, :196:28] wire [35:0] sigSum = {sigSum_hi, io_fromPreMul_bit0AlignedSigC_0}; // @[MulAddRecFN.scala:169:7, :192:12] wire [1:0] _CDom_sExp_T = {1'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :203:69] wire [7:0] _GEN = {io_fromPreMul_sExpSum_0[6], io_fromPreMul_sExpSum_0}; // @[MulAddRecFN.scala:169:7, :203:43] wire [7:0] _CDom_sExp_T_1 = _GEN - {{6{_CDom_sExp_T[1]}}, _CDom_sExp_T}; // @[MulAddRecFN.scala:203:{43,69}] wire [6:0] _CDom_sExp_T_2 = _CDom_sExp_T_1[6:0]; // @[MulAddRecFN.scala:203:43] wire [6:0] CDom_sExp = _CDom_sExp_T_2; // @[MulAddRecFN.scala:203:43] wire [23:0] _CDom_absSigSum_T = sigSum[35:12]; // @[MulAddRecFN.scala:192:12, :206:20] wire [23:0] _CDom_absSigSum_T_1 = ~_CDom_absSigSum_T; // @[MulAddRecFN.scala:206:{13,20}] wire [1:0] _CDom_absSigSum_T_2 = io_fromPreMul_highAlignedSigC_0[12:11]; // @[MulAddRecFN.scala:169:7, :209:46] wire [2:0] _CDom_absSigSum_T_3 = {1'h0, _CDom_absSigSum_T_2}; // @[MulAddRecFN.scala:207:22, :209:46] wire [20:0] _CDom_absSigSum_T_4 = sigSum[33:13]; // @[MulAddRecFN.scala:192:12, :210:23] wire [23:0] _CDom_absSigSum_T_5 = {_CDom_absSigSum_T_3, _CDom_absSigSum_T_4}; // @[MulAddRecFN.scala:207:22, :209:71, :210:23] wire [23:0] CDom_absSigSum = io_fromPreMul_doSubMags_0 ? _CDom_absSigSum_T_1 : _CDom_absSigSum_T_5; // @[MulAddRecFN.scala:169:7, :205:12, :206:13, :209:71] wire [10:0] _CDom_absSigSumExtra_T = sigSum[11:1]; // @[MulAddRecFN.scala:192:12, :215:21] wire [10:0] _CDom_absSigSumExtra_T_1 = ~_CDom_absSigSumExtra_T; // @[MulAddRecFN.scala:215:{14,21}] wire _CDom_absSigSumExtra_T_2 = \|_CDom_absSigSumExtra_T_1; // @[MulAddRecFN.scala:215:{14,36}] wire [11:0] _CDom_absSigSumExtra_T_3 = sigSum[12:1]; // @[MulAddRecFN.scala:192:12, :216:19] wire _CDom_absSigSumExtra_T_4 = \|_CDom_absSigSumExtra_T_3; // @[MulAddRecFN.scala:216:{19,37}] wire CDom_absSigSumExtra = io_fromPreMul_doSubMags_0 ? _CDom_absSigSumExtra_T_2 : _CDom_absSigSumExtra_T_4; // @[MulAddRecFN.scala:169:7, :214:12, :215:36, :216:37] wire [38:0] _CDom_mainSig_T = {15'h0, CDom_absSigSum} << io_fromPreMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:169:7, :205:12, :219:24] wire [15:0] CDom_mainSig = _CDom_mainSig_T[23:8]; // @[MulAddRecFN.scala:219:{24,56}] wire [10:0] _CDom_reduced4SigExtra_T = CDom_absSigSum[10:0]; // @[MulAddRecFN.scala:205:12, :222:36] wire [10:0] _CDom_reduced4SigExtra_T_1 = _CDom_reduced4SigExtra_T; // @[MulAddRecFN.scala:222:{36,53}] wire _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:123:57] wire CDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:118:30] wire [3:0] _CDom_reduced4SigExtra_reducedVec_0_T = _CDom_reduced4SigExtra_T_1[3:0]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_0_T_1 = \|_CDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_0 = _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_1_T = _CDom_reduced4SigExtra_T_1[7:4]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_1_T_1 = \|_CDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_1 = _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54] wire [2:0] _CDom_reduced4SigExtra_reducedVec_2_T = _CDom_reduced4SigExtra_T_1[10:8]; // @[primitives.scala:123:15] assign _CDom_reduced4SigExtra_reducedVec_2_T_1 = \|_CDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:123:{15,57}] assign CDom_reduced4SigExtra_reducedVec_2 = _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :123:57] wire [1:0] CDom_reduced4SigExtra_hi = {CDom_reduced4SigExtra_reducedVec_2, CDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20] wire [2:0] _CDom_reduced4SigExtra_T_2 = {CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20] wire [1:0] _CDom_reduced4SigExtra_T_3 = io_fromPreMul_CDom_CAlignDist_0[3:2]; // @[MulAddRecFN.scala:169:7, :223:51] wire [1:0] _CDom_reduced4SigExtra_T_4 = ~_CDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21] wire [4:0] CDom_reduced4SigExtra_shift = $signed(5'sh10 >>> _CDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56] wire [1:0] _CDom_reduced4SigExtra_T_5 = CDom_reduced4SigExtra_shift[2:1]; // @[primitives.scala:76:56, :78:22] wire _CDom_reduced4SigExtra_T_6 = _CDom_reduced4SigExtra_T_5[0]; // @[primitives.scala:77:20, :78:22] wire _CDom_reduced4SigExtra_T_7 = _CDom_reduced4SigExtra_T_5[1]; // @[primitives.scala:77:20, :78:22] wire [1:0] _CDom_reduced4SigExtra_T_8 = {_CDom_reduced4SigExtra_T_6, _CDom_reduced4SigExtra_T_7}; // @[primitives.scala:77:20] wire [2:0] _CDom_reduced4SigExtra_T_9 = {1'h0, _CDom_reduced4SigExtra_T_2[1:0] & _CDom_reduced4SigExtra_T_8}; // @[primitives.scala:77:20, :124:20] wire CDom_reduced4SigExtra = \|_CDom_reduced4SigExtra_T_9; // @[MulAddRecFN.scala:222:72, :223:73] wire [12:0] _CDom_sig_T = CDom_mainSig[15:3]; // @[MulAddRecFN.scala:219:56, :225:25] wire [2:0] _CDom_sig_T_1 = CDom_mainSig[2:0]; // @[MulAddRecFN.scala:219:56, :226:25] wire _CDom_sig_T_2 = \|_CDom_sig_T_1; // @[MulAddRecFN.scala:226:{25,32}] wire _CDom_sig_T_3 = _CDom_sig_T_2 \| CDom_reduced4SigExtra; // @[MulAddRecFN.scala:223:73, :226:{32,36}] wire _CDom_sig_T_4 = _CDom_sig_T_3 \| CDom_absSigSumExtra; // @[MulAddRecFN.scala:214:12, :226:{36,61}] wire [13:0] CDom_sig = {_CDom_sig_T, _CDom_sig_T_4}; // @[MulAddRecFN.scala:225:{12,25}, :226:61] wire notCDom_signSigSum = sigSum[25]; // @[MulAddRecFN.scala:192:12, :232:36] wire [24:0] _notCDom_absSigSum_T = sigSum[24:0]; // @[MulAddRecFN.scala:192:12, :235:20] wire [24:0] _notCDom_absSigSum_T_2 = sigSum[24:0]; // @[MulAddRecFN.scala:192:12, :235:20, :236:19] wire [24:0] _notCDom_absSigSum_T_1 = ~_notCDom_absSigSum_T; // @[MulAddRecFN.scala:235:{13,20}] wire [25:0] _notCDom_absSigSum_T_3 = {1'h0, _notCDom_absSigSum_T_2} + {25'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :236:{19,41}] wire [24:0] _notCDom_absSigSum_T_4 = _notCDom_absSigSum_T_3[24:0]; // @[MulAddRecFN.scala:236:41] wire [24:0] notCDom_absSigSum = notCDom_signSigSum ? _notCDom_absSigSum_T_1 : _notCDom_absSigSum_T_4; // @[MulAddRecFN.scala:232:36, :234:12, :235:13, :236:41] wire _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:106:57] wire notCDom_reduced2AbsSigSum_reducedVec_0; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_1; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_2; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_3; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_4; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_5; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_6; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_7; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_8; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_9; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_10; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_11; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_12; // @[primitives.scala:101:30] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_0_T = notCDom_absSigSum[1:0]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_0_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_0 = _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_1_T = notCDom_absSigSum[3:2]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_1_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_1 = _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_2_T = notCDom_absSigSum[5:4]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_2_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_2 = _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_3_T = notCDom_absSigSum[7:6]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_3_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_3 = _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_4_T = notCDom_absSigSum[9:8]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_4_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_4 = _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_5_T = notCDom_absSigSum[11:10]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_5_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_5 = _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_6_T = notCDom_absSigSum[13:12]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_6_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_6 = _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_7_T = notCDom_absSigSum[15:14]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_7_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_7 = _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_8_T = notCDom_absSigSum[17:16]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_8_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_8 = _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_9_T = notCDom_absSigSum[19:18]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_9_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_9 = _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_10_T = notCDom_absSigSum[21:20]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_10_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_10 = _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_11_T = notCDom_absSigSum[23:22]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_11_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_11 = _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:101:30, :103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_12_T = notCDom_absSigSum[24]; // @[primitives.scala:106:15] assign _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = _notCDom_reduced2AbsSigSum_reducedVec_12_T; // @[primitives.scala:106:{15,57}] assign notCDom_reduced2AbsSigSum_reducedVec_12 = _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:101:30, :106:57] wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_2, notCDom_reduced2AbsSigSum_reducedVec_1}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_0}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_5, notCDom_reduced2AbsSigSum_reducedVec_4}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_3}; // @[primitives.scala:101:30, :107:20] wire [5:0] notCDom_reduced2AbsSigSum_lo = {notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_8, notCDom_reduced2AbsSigSum_reducedVec_7}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_lo = {notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_6}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_10, notCDom_reduced2AbsSigSum_reducedVec_9}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_12, notCDom_reduced2AbsSigSum_reducedVec_11}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced2AbsSigSum_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo}; // @[primitives.scala:107:20] wire [6:0] notCDom_reduced2AbsSigSum_hi = {notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo}; // @[primitives.scala:107:20] wire [12:0] notCDom_reduced2AbsSigSum = {notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo}; // @[primitives.scala:107:20] wire _notCDom_normDistReduced2_T = notCDom_reduced2AbsSigSum[0]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_1 = notCDom_reduced2AbsSigSum[1]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_2 = notCDom_reduced2AbsSigSum[2]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_3 = notCDom_reduced2AbsSigSum[3]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_4 = notCDom_reduced2AbsSigSum[4]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_5 = notCDom_reduced2AbsSigSum[5]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_6 = notCDom_reduced2AbsSigSum[6]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_7 = notCDom_reduced2AbsSigSum[7]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_8 = notCDom_reduced2AbsSigSum[8]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_9 = notCDom_reduced2AbsSigSum[9]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_10 = notCDom_reduced2AbsSigSum[10]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_11 = notCDom_reduced2AbsSigSum[11]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_12 = notCDom_reduced2AbsSigSum[12]; // @[primitives.scala:91:52, :107:20] wire [3:0] _notCDom_normDistReduced2_T_13 = _notCDom_normDistReduced2_T_1 ? 4'hB : 4'hC; // @[Mux.scala:50:70] wire [3:0] _notCDom_normDistReduced2_T_14 = _notCDom_normDistReduced2_T_2 ? 4'hA : _notCDom_normDistReduced2_T_13; // @[Mux.scala:50:70] wire [3:0] _notCDom_normDistReduced2_T_15 = _notCDom_normDistReduced2_T_3 ? 4'h9 : _notCDom_normDistReduced2_T_14; // @[Mux.scala:50:70] wire [3:0] _notCDom_normDistReduced2_T_16 = _notCDom_normDistReduced2_T_4 ? 4'h8 : _notCDom_normDistReduced2_T_15; // @[Mux.scala:50:70] wire [3:0] _notCDom_normDistReduced2_T_17 = _notCDom_normDistReduced2_T_5 ? 4'h7 : _notCDom_normDistReduced2_T_16; // @[Mux.scala:50:70] wire [3:0] _notCDom_normDistReduced2_T_18 = _notCDom_normDistReduced2_T_6 ? 4'h6 : _notCDom_normDistReduced2_T_17; // @[Mux.scala:50:70] wire [3:0] _notCDom_normDistReduced2_T_19 = _notCDom_normDistReduced2_T_7 ? 4'h5 : _notCDom_normDistReduced2_T_18; // @[Mux.scala:50:70] wire [3:0] _notCDom_normDistReduced2_T_20 = _notCDom_normDistReduced2_T_8 ? 4'h4 : _notCDom_normDistReduced2_T_19; // @[Mux.scala:50:70] wire [3:0] _notCDom_normDistReduced2_T_21 = _notCDom_normDistReduced2_T_9 ? 4'h3 : _notCDom_normDistReduced2_T_20; // @[Mux.scala:50:70] wire [3:0] _notCDom_normDistReduced2_T_22 = _notCDom_normDistReduced2_T_10 ? 4'h2 : _notCDom_normDistReduced2_T_21; // @[Mux.scala:50:70] wire [3:0] _notCDom_normDistReduced2_T_23 = _notCDom_normDistReduced2_T_11 ? 4'h1 : _notCDom_normDistReduced2_T_22; // @[Mux.scala:50:70] wire [3:0] notCDom_normDistReduced2 = _notCDom_normDistReduced2_T_12 ? 4'h0 : _notCDom_normDistReduced2_T_23; // @[Mux.scala:50:70] wire [4:0] notCDom_nearNormDist = {notCDom_normDistReduced2, 1'h0}; // @[Mux.scala:50:70] wire [5:0] _notCDom_sExp_T = {1'h0, notCDom_nearNormDist}; // @[MulAddRecFN.scala:240:56, :241:76] wire [7:0] _notCDom_sExp_T_1 = _GEN - {{2{_notCDom_sExp_T[5]}}, _notCDom_sExp_T}; // @[MulAddRecFN.scala:203:43, :241:{46,76}] wire [6:0] _notCDom_sExp_T_2 = _notCDom_sExp_T_1[6:0]; // @[MulAddRecFN.scala:241:46] wire [6:0] notCDom_sExp = _notCDom_sExp_T_2; // @[MulAddRecFN.scala:241:46] wire [55:0] _notCDom_mainSig_T = {31'h0, notCDom_absSigSum} << notCDom_nearNormDist; // @[MulAddRecFN.scala:234:12, :240:56, :243:27] wire [15:0] notCDom_mainSig = _notCDom_mainSig_T[25:10]; // @[MulAddRecFN.scala:243:{27,50}] wire [5:0] _notCDom_reduced4SigExtra_T = notCDom_reduced2AbsSigSum[5:0]; // @[primitives.scala:107:20] wire [6:0] _notCDom_reduced4SigExtra_T_1 = {_notCDom_reduced4SigExtra_T, 1'h0}; // @[MulAddRecFN.scala:247:{39,55}] wire _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:106:57] wire notCDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:101:30] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_0_T = _notCDom_reduced4SigExtra_T_1[1:0]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_0_T_1 = \|_notCDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_0 = _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_1_T = _notCDom_reduced4SigExtra_T_1[3:2]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_1_T_1 = \|_notCDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_1 = _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_2_T = _notCDom_reduced4SigExtra_T_1[5:4]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_2_T_1 = \|_notCDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_2 = _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54] wire _notCDom_reduced4SigExtra_reducedVec_3_T = _notCDom_reduced4SigExtra_T_1[6]; // @[primitives.scala:106:15] assign _notCDom_reduced4SigExtra_reducedVec_3_T_1 = _notCDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:106:{15,57}] assign notCDom_reduced4SigExtra_reducedVec_3 = _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:101:30, :106:57] wire [1:0] notCDom_reduced4SigExtra_lo = {notCDom_reduced4SigExtra_reducedVec_1, notCDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced4SigExtra_hi = {notCDom_reduced4SigExtra_reducedVec_3, notCDom_reduced4SigExtra_reducedVec_2}; // @[primitives.scala:101:30, :107:20] wire [3:0] _notCDom_reduced4SigExtra_T_2 = {notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo}; // @[primitives.scala:107:20] wire [2:0] _notCDom_reduced4SigExtra_T_3 = notCDom_normDistReduced2[3:1]; // @[Mux.scala:50:70] wire [2:0] _notCDom_reduced4SigExtra_T_4 = ~_notCDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21] wire [8:0] notCDom_reduced4SigExtra_shift = $signed(9'sh100 >>> _notCDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56] wire [2:0] _notCDom_reduced4SigExtra_T_5 = notCDom_reduced4SigExtra_shift[3:1]; // @[primitives.scala:76:56, :78:22] wire [1:0] _notCDom_reduced4SigExtra_T_6 = _notCDom_reduced4SigExtra_T_5[1:0]; // @[primitives.scala:77:20, :78:22] wire _notCDom_reduced4SigExtra_T_7 = _notCDom_reduced4SigExtra_T_6[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_8 = _notCDom_reduced4SigExtra_T_6[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_9 = {_notCDom_reduced4SigExtra_T_7, _notCDom_reduced4SigExtra_T_8}; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_10 = _notCDom_reduced4SigExtra_T_5[2]; // @[primitives.scala:77:20, :78:22] wire [2:0] _notCDom_reduced4SigExtra_T_11 = {_notCDom_reduced4SigExtra_T_9, _notCDom_reduced4SigExtra_T_10}; // @[primitives.scala:77:20] wire [3:0] _notCDom_reduced4SigExtra_T_12 = {1'h0, _notCDom_reduced4SigExtra_T_2[2:0] & _notCDom_reduced4SigExtra_T_11}; // @[primitives.scala:77:20, :107:20] wire notCDom_reduced4SigExtra = \|_notCDom_reduced4SigExtra_T_12; // @[MulAddRecFN.scala:247:78, :249:11] wire [12:0] _notCDom_sig_T = notCDom_mainSig[15:3]; // @[MulAddRecFN.scala:243:50, :251:28] wire [2:0] _notCDom_sig_T_1 = notCDom_mainSig[2:0]; // @[MulAddRecFN.scala:243:50, :252:28] wire _notCDom_sig_T_2 = \|_notCDom_sig_T_1; // @[MulAddRecFN.scala:252:{28,35}] wire _notCDom_sig_T_3 = _notCDom_sig_T_2 \| notCDom_reduced4SigExtra; // @[MulAddRecFN.scala:249:11, :252:{35,39}] wire [13:0] notCDom_sig = {_notCDom_sig_T, _notCDom_sig_T_3}; // @[MulAddRecFN.scala:251:{12,28}, :252:39] wire [1:0] _notCDom_completeCancellation_T = notCDom_sig[13:12]; // @[MulAddRecFN.scala:251:12, :255:21] wire notCDom_completeCancellation = _notCDom_completeCancellation_T == 2'h0; // @[primitives.scala:103:54] wire _notCDom_sign_T = io_fromPreMul_signProd_0 ^ notCDom_signSigSum; // @[MulAddRecFN.scala:169:7, :232:36, :259:36] wire notCDom_sign = notCDom_completeCancellation ? roundingMode_min : _notCDom_sign_T; // @[MulAddRecFN.scala:186:45, :255:50, :257:12, :259:36] wire _GEN_0 = io_fromPreMul_isInfA_0 \| io_fromPreMul_isInfB_0; // @[MulAddRecFN.scala:169:7, :264:49] wire notNaN_isInfProd; // @[MulAddRecFN.scala:264:49] assign notNaN_isInfProd = _GEN_0; // @[MulAddRecFN.scala:264:49] wire _io_invalidExc_T_5; // @[MulAddRecFN.scala:275:36] assign _io_invalidExc_T_5 = _GEN_0; // @[MulAddRecFN.scala:264:49, :275:36] assign notNaN_isInfOut = notNaN_isInfProd \| io_fromPreMul_isInfC_0; // @[MulAddRecFN.scala:169:7, :264:49, :265:44] assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulAddRecFN.scala:169:7, :265:44] wire _notNaN_addZeros_T = io_fromPreMul_isZeroA_0 \| io_fromPreMul_isZeroB_0; // @[MulAddRecFN.scala:169:7, :267:32] wire notNaN_addZeros = _notNaN_addZeros_T & io_fromPreMul_isZeroC_0; // @[MulAddRecFN.scala:169:7, :267:{32,58}] wire _io_invalidExc_T = io_fromPreMul_isInfA_0 & io_fromPreMul_isZeroB_0; // @[MulAddRecFN.scala:169:7, :272:31] wire _io_invalidExc_T_1 = io_fromPreMul_isSigNaNAny_0 \| _io_invalidExc_T; // @[MulAddRecFN.scala:169:7, :271:35, :272:31] wire _io_invalidExc_T_2 = io_fromPreMul_isZeroA_0 & io_fromPreMul_isInfB_0; // @[MulAddRecFN.scala:169:7, :273:32] wire _io_invalidExc_T_3 = _io_invalidExc_T_1 \| _io_invalidExc_T_2; // @[MulAddRecFN.scala:271:35, :272:57, :273:32] wire _io_invalidExc_T_4 = ~io_fromPreMul_isNaNAOrB_0; // @[MulAddRecFN.scala:169:7, :274:10] wire _io_invalidExc_T_6 = _io_invalidExc_T_4 & _io_invalidExc_T_5; // @[MulAddRecFN.scala:274:{10,36}, :275:36] wire _io_invalidExc_T_7 = _io_invalidExc_T_6 & io_fromPreMul_isInfC_0; // @[MulAddRecFN.scala:169:7, :274:36, :275:61] wire _io_invalidExc_T_8 = _io_invalidExc_T_7 & io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :275:61, :276:35] assign _io_invalidExc_T_9 = _io_invalidExc_T_3 \| _io_invalidExc_T_8; // @[MulAddRecFN.scala:272:57, :273:57, :276:35] assign io_invalidExc_0 = _io_invalidExc_T_9; // @[MulAddRecFN.scala:169:7, :273:57] assign _io_rawOut_isNaN_T = io_fromPreMul_isNaNAOrB_0 \| io_fromPreMul_isNaNC_0; // @[MulAddRecFN.scala:169:7, :278:48] assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:169:7, :278:48] wire _io_rawOut_isZero_T = ~io_fromPreMul_CIsDominant_0; // @[MulAddRecFN.scala:169:7, :283:14] wire _io_rawOut_isZero_T_1 = _io_rawOut_isZero_T & notCDom_completeCancellation; // @[MulAddRecFN.scala:255:50, :283:{14,42}] assign _io_rawOut_isZero_T_2 = notNaN_addZeros \| _io_rawOut_isZero_T_1; // @[MulAddRecFN.scala:267:58, :282:25, :283:42] assign io_rawOut_isZero_0 = _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:169:7, :282:25] wire _io_rawOut_sign_T = notNaN_isInfProd & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :264:49, :285:27] wire _io_rawOut_sign_T_1 = io_fromPreMul_isInfC_0 & opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :286:31] wire _io_rawOut_sign_T_2 = _io_rawOut_sign_T \| _io_rawOut_sign_T_1; // @[MulAddRecFN.scala:285:{27,54}, :286:31] wire _io_rawOut_sign_T_3 = ~roundingMode_min; // @[MulAddRecFN.scala:186:45, :287:29] wire _io_rawOut_sign_T_4 = notNaN_addZeros & _io_rawOut_sign_T_3; // @[MulAddRecFN.scala:267:58, :287:{26,29}] wire _io_rawOut_sign_T_5 = _io_rawOut_sign_T_4 & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :287:{26,48}] wire _io_rawOut_sign_T_6 = _io_rawOut_sign_T_5 & opSignC; // @[MulAddRecFN.scala:190:42, :287:48, :288:36] wire _io_rawOut_sign_T_7 = _io_rawOut_sign_T_2 \| _io_rawOut_sign_T_6; // @[MulAddRecFN.scala:285:54, :286:43, :288:36] wire _io_rawOut_sign_T_8 = notNaN_addZeros & roundingMode_min; // @[MulAddRecFN.scala:186:45, :267:58, :289:26] wire _io_rawOut_sign_T_9 = io_fromPreMul_signProd_0 \| opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :290:37] wire _io_rawOut_sign_T_10 = _io_rawOut_sign_T_8 & _io_rawOut_sign_T_9; // @[MulAddRecFN.scala:289:{26,46}, :290:37] wire _io_rawOut_sign_T_11 = _io_rawOut_sign_T_7 \| _io_rawOut_sign_T_10; // @[MulAddRecFN.scala:286:43, :288:48, :289:46] wire _io_rawOut_sign_T_12 = ~notNaN_isInfOut; // @[MulAddRecFN.scala:265:44, :291:10] wire _io_rawOut_sign_T_13 = ~notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :291:31] wire _io_rawOut_sign_T_14 = _io_rawOut_sign_T_12 & _io_rawOut_sign_T_13; // @[MulAddRecFN.scala:291:{10,28,31}] wire _io_rawOut_sign_T_15 = io_fromPreMul_CIsDominant_0 ? opSignC : notCDom_sign; // @[MulAddRecFN.scala:169:7, :190:42, :257:12, :292:17] wire _io_rawOut_sign_T_16 = _io_rawOut_sign_T_14 & _io_rawOut_sign_T_15; // @[MulAddRecFN.scala:291:{28,49}, :292:17] assign _io_rawOut_sign_T_17 = _io_rawOut_sign_T_11 \| _io_rawOut_sign_T_16; // @[MulAddRecFN.scala:288:48, :290:50, :291:49] assign io_rawOut_sign_0 = _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:169:7, :290:50] assign _io_rawOut_sExp_T = io_fromPreMul_CIsDominant_0 ? CDom_sExp : notCDom_sExp; // @[MulAddRecFN.scala:169:7, :203:43, :241:46, :293:26] assign io_rawOut_sExp_0 = _io_rawOut_sExp_T; // @[MulAddRecFN.scala:169:7, :293:26] assign _io_rawOut_sig_T = io_fromPreMul_CIsDominant_0 ? CDom_sig : notCDom_sig; // @[MulAddRecFN.scala:169:7, :225:12, :251:12, :294:25] assign io_rawOut_sig_0 = _io_rawOut_sig_T; // @[MulAddRecFN.scala:169:7, :294:25] assign io_invalidExc = io_invalidExc_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sign = io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sig = io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerShiftReg_w4_d3_i0_18( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input [3:0] io_d, // @[ShiftReg.scala:36:14] output [3:0] io_q // @[ShiftReg.scala:36:14] ); wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21] wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14] wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7] wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_1; // @[ShiftReg.scala:48:24] wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_2; // @[ShiftReg.scala:48:24] wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_3; // @[ShiftReg.scala:48:24] wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14] wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14] assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14] assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_181 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_182 output_chain_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_2), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_3), // @[SynchronizerReg.scala:87:41] .io_q (output_1) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_183 output_chain_2 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_4), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_5), // @[SynchronizerReg.scala:87:41] .io_q (output_2) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_184 output_chain_3 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_6), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_7), // @[SynchronizerReg.scala:87:41] .io_q (output_3) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag }	module OptimizationBarrier_TLBEntryData_249( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Fragmenter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet, BufferParams, IdRange, TransferSizes} import freechips.rocketchip.util.{Repeater, OH1ToUInt, UIntToOH1} import scala.math.min import freechips.rocketchip.util.DataToAugmentedData object EarlyAck { sealed trait T case object AllPuts extends T case object PutFulls extends T case object None extends T } // minSize: minimum size of transfers supported by all outward managers // maxSize: maximum size of transfers supported after the Fragmenter is applied // alwaysMin: fragment all requests down to minSize (else fragment to maximum supported by manager) // earlyAck: should a multibeat Put should be acknowledged on the first beat or last beat // holdFirstDeny: allow the Fragmenter to unsafely combine multibeat Gets by taking the first denied for the whole burst // nameSuffix: appends a suffix to the module name // Fragmenter modifies: PutFull, PutPartial, LogicalData, Get, Hint // Fragmenter passes: ArithmeticData (truncated to minSize if alwaysMin) // Fragmenter cannot modify acquire (could livelock); thus it is unsafe to put caches on both sides class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean = false, val earlyAck: EarlyAck.T = EarlyAck.None, val holdFirstDeny: Boolean = false, val nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule { require(isPow2 (maxSize), s"TLFragmenter expects pow2(maxSize), but got $maxSize") require(isPow2 (minSize), s"TLFragmenter expects pow2(minSize), but got $minSize") require(minSize <= maxSize, s"TLFragmenter expects min <= max, but got $minSize > $maxSize") val fragmentBits = log2Ceil(maxSize / minSize) val fullBits = if (earlyAck == EarlyAck.PutFulls) 1 else 0 val toggleBits = 1 val addedBits = fragmentBits + toggleBits + fullBits def expandTransfer(x: TransferSizes, op: String) = if (!x) x else { // validate that we can apply the fragmenter correctly require (x.max >= minSize, s"TLFragmenter (with parent $parent) max transfer size $op(${x.max}) must be >= min transfer size (${minSize})") TransferSizes(x.min, maxSize) } private def noChangeRequired = minSize == maxSize private def shrinkTransfer(x: TransferSizes) = if (!alwaysMin) x else if (x.min <= minSize) TransferSizes(x.min, min(minSize, x.max)) else TransferSizes.none private def mapManager(m: TLSlaveParameters) = m.v1copy( supportsArithmetic = shrinkTransfer(m.supportsArithmetic), supportsLogical = shrinkTransfer(m.supportsLogical), supportsGet = expandTransfer(m.supportsGet, "Get"), supportsPutFull = expandTransfer(m.supportsPutFull, "PutFull"), supportsPutPartial = expandTransfer(m.supportsPutPartial, "PutParital"), supportsHint = expandTransfer(m.supportsHint, "Hint")) val node = new TLAdapterNode( // We require that all the responses are mutually FIFO // Thus we need to compact all of the masters into one big master clientFn = { c => (if (noChangeRequired) c else c.v2copy( masters = Seq(TLMasterParameters.v2( name = "TLFragmenter", sourceId = IdRange(0, if (minSize == maxSize) c.endSourceId else (c.endSourceId << addedBits)), requestFifo = true, emits = TLMasterToSlaveTransferSizes( acquireT = shrinkTransfer(c.masters.map(_.emits.acquireT) .reduce(_ mincover _)), acquireB = shrinkTransfer(c.masters.map(_.emits.acquireB) .reduce(_ mincover _)), arithmetic = shrinkTransfer(c.masters.map(_.emits.arithmetic).reduce(_ mincover _)), logical = shrinkTransfer(c.masters.map(_.emits.logical) .reduce(_ mincover _)), get = shrinkTransfer(c.masters.map(_.emits.get) .reduce(_ mincover _)), putFull = shrinkTransfer(c.masters.map(_.emits.putFull) .reduce(_ mincover _)), putPartial = shrinkTransfer(c.masters.map(_.emits.putPartial).reduce(_ mincover _)), hint = shrinkTransfer(c.masters.map(_.emits.hint) .reduce(_ mincover _)) ) )) ))}, managerFn = { m => if (noChangeRequired) m else m.v2copy(slaves = m.slaves.map(mapManager)) } ) { override def circuitIdentity = noChangeRequired } lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = (Seq("TLFragmenter") ++ nameSuffix).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => if (noChangeRequired) { out <> in } else { // All managers must share a common FIFO domain (responses might end up interleaved) val manager = edgeOut.manager val managers = manager.managers val beatBytes = manager.beatBytes val fifoId = managers(0).fifoId require (fifoId.isDefined && managers.map(_.fifoId == fifoId).reduce(_ && _)) require (!manager.anySupportAcquireB \|\| !edgeOut.client.anySupportProbe, s"TLFragmenter (with parent $parent) can't fragment a caching client's requests into a cacheable region") require (minSize >= beatBytes, s"TLFragmenter (with parent $parent) can't support fragmenting ($minSize) to sub-beat ($beatBytes) accesses") // We can't support devices which are cached on both sides of us require (!edgeOut.manager.anySupportAcquireB \|\| !edgeIn.client.anySupportProbe) // We can't support denied because we reassemble fragments require (!edgeOut.manager.mayDenyGet \|\| holdFirstDeny, s"TLFragmenter (with parent $parent) can't support denials without holdFirstDeny=true") require (!edgeOut.manager.mayDenyPut \|\| earlyAck == EarlyAck.None) /* The Fragmenter is a bit tricky, because there are 5 sizes in play: * max size -- the maximum transfer size possible * orig size -- the original pre-fragmenter size * frag size -- the modified post-fragmenter size * min size -- the threshold below which frag=orig * beat size -- the amount transfered on any given beat * * The relationships are as follows: * max >= orig >= frag * max > min >= beat * It IS possible that orig <= min (then frag=orig; ie: no fragmentation) * * The fragment# (sent via TL.source) is measured in multiples of min size. * Meanwhile, to track the progress, counters measure in multiples of beat size. * * Here is an example of a bus with max=256, min=8, beat=4 and a device supporting 16. * * in.A out.A (frag#) out.D (frag#) in.D gen# ack# * get64 get16 6 ackD16 6 ackD64 12 15 * ackD16 6 ackD64 14 * ackD16 6 ackD64 13 * ackD16 6 ackD64 12 * get16 4 ackD16 4 ackD64 8 11 * ackD16 4 ackD64 10 * ackD16 4 ackD64 9 * ackD16 4 ackD64 8 * get16 2 ackD16 2 ackD64 4 7 * ackD16 2 ackD64 6 * ackD16 2 ackD64 5 * ackD16 2 ackD64 4 * get16 0 ackD16 0 ackD64 0 3 * ackD16 0 ackD64 2 * ackD16 0 ackD64 1 * ackD16 0 ackD64 0 * * get8 get8 0 ackD8 0 ackD8 0 1 * ackD8 0 ackD8 0 * * get4 get4 0 ackD4 0 ackD4 0 0 * get1 get1 0 ackD1 0 ackD1 0 0 * * put64 put16 6 15 * put64 put16 6 14 * put64 put16 6 13 * put64 put16 6 ack16 6 12 12 * put64 put16 4 11 * put64 put16 4 10 * put64 put16 4 9 * put64 put16 4 ack16 4 8 8 * put64 put16 2 7 * put64 put16 2 6 * put64 put16 2 5 * put64 put16 2 ack16 2 4 4 * put64 put16 0 3 * put64 put16 0 2 * put64 put16 0 1 * put64 put16 0 ack16 0 ack64 0 0 * * put8 put8 0 1 * put8 put8 0 ack8 0 ack8 0 0 * * put4 put4 0 ack4 0 ack4 0 0 * put1 put1 0 ack1 0 ack1 0 0 / val counterBits = log2Up(maxSize/beatBytes) val maxDownSize = if (alwaysMin) minSize else min(manager.maxTransfer, maxSize) // Consider the following waveform for two 4-beat bursts: // ---A----A------------ // -------D-----DDD-DDDD // Under TL rules, the second A can use the same source as the first A, // because the source is released for reuse on the first response beat. // // However, if we fragment the requests, it looks like this: // ---3210-3210--------- // -------3-----210-3210 // ... now we've broken the rules because 210 are twice inflight. // // This phenomenon means we can have essentially 2maxSize/minSize-1 // fragmented transactions in flight per original transaction source. // // To keep the source unique, we encode the beat counter in the low // bits of the source. To solve the overlap, we use a toggle bit. // Whatever toggle bit the D is reassembling, A will use the opposite. // First, handle the return path val acknum = RegInit(0.U(counterBits.W)) val dOrig = Reg(UInt()) val dToggle = RegInit(false.B) val dFragnum = out.d.bits.source(fragmentBits-1, 0) val dFirst = acknum === 0.U val dLast = dFragnum === 0.U // only for AccessAck (!Data) val dsizeOH = UIntToOH (out.d.bits.size, log2Ceil(maxDownSize)+1) val dsizeOH1 = UIntToOH1(out.d.bits.size, log2Up(maxDownSize)) val dHasData = edgeOut.hasData(out.d.bits) // calculate new acknum val acknum_fragment = dFragnum << log2Ceil(minSize/beatBytes) val acknum_size = dsizeOH1 >> log2Ceil(beatBytes) assert (!out.d.valid \|\| (acknum_fragment & acknum_size) === 0.U) val dFirst_acknum = acknum_fragment \| Mux(dHasData, acknum_size, 0.U) val ack_decrement = Mux(dHasData, 1.U, dsizeOH >> log2Ceil(beatBytes)) // calculate the original size val dFirst_size = OH1ToUInt((dFragnum << log2Ceil(minSize)) \| dsizeOH1) when (out.d.fire) { acknum := Mux(dFirst, dFirst_acknum, acknum - ack_decrement) when (dFirst) { dOrig := dFirst_size dToggle := out.d.bits.source(fragmentBits) } } // Swallow up non-data ack fragments val doEarlyAck = earlyAck match { case EarlyAck.AllPuts => true.B case EarlyAck.PutFulls => out.d.bits.source(fragmentBits+1) case EarlyAck.None => false.B } val drop = !dHasData && !Mux(doEarlyAck, dFirst, dLast) out.d.ready := in.d.ready \|\| drop in.d.valid := out.d.valid && !drop in.d.bits := out.d.bits // pass most stuff unchanged in.d.bits.source := out.d.bits.source >> addedBits in.d.bits.size := Mux(dFirst, dFirst_size, dOrig) if (edgeOut.manager.mayDenyPut) { val r_denied = Reg(Bool()) val d_denied = (!dFirst && r_denied) \|\| out.d.bits.denied when (out.d.fire) { r_denied := d_denied } in.d.bits.denied := d_denied } if (edgeOut.manager.mayDenyGet) { // Take denied only from the first beat and hold that value val d_denied = out.d.bits.denied holdUnless dFirst when (dHasData) { in.d.bits.denied := d_denied in.d.bits.corrupt := d_denied \|\| out.d.bits.corrupt } } // What maximum transfer sizes do downstream devices support? val maxArithmetics = managers.map(_.supportsArithmetic.max) val maxLogicals = managers.map(_.supportsLogical.max) val maxGets = managers.map(_.supportsGet.max) val maxPutFulls = managers.map(_.supportsPutFull.max) val maxPutPartials = managers.map(_.supportsPutPartial.max) val maxHints = managers.map(m => if (m.supportsHint) maxDownSize else 0) // We assume that the request is valid => size 0 is impossible val lgMinSize = log2Ceil(minSize).U val maxLgArithmetics = maxArithmetics.map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgLogicals = maxLogicals .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgGets = maxGets .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgPutFulls = maxPutFulls .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgPutPartials = maxPutPartials.map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgHints = maxHints .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) // Make the request repeatable val repeater = Module(new Repeater(in.a.bits)) repeater.io.enq <> in.a val in_a = repeater.io.deq // If this is infront of a single manager, these become constants val find = manager.findFast(edgeIn.address(in_a.bits)) val maxLgArithmetic = Mux1H(find, maxLgArithmetics) val maxLgLogical = Mux1H(find, maxLgLogicals) val maxLgGet = Mux1H(find, maxLgGets) val maxLgPutFull = Mux1H(find, maxLgPutFulls) val maxLgPutPartial = Mux1H(find, maxLgPutPartials) val maxLgHint = Mux1H(find, maxLgHints) val limit = if (alwaysMin) lgMinSize else MuxLookup(in_a.bits.opcode, lgMinSize)(Array( TLMessages.PutFullData -> maxLgPutFull, TLMessages.PutPartialData -> maxLgPutPartial, TLMessages.ArithmeticData -> maxLgArithmetic, TLMessages.LogicalData -> maxLgLogical, TLMessages.Get -> maxLgGet, TLMessages.Hint -> maxLgHint)) val aOrig = in_a.bits.size val aFrag = Mux(aOrig > limit, limit, aOrig) val aOrigOH1 = UIntToOH1(aOrig, log2Ceil(maxSize)) val aFragOH1 = UIntToOH1(aFrag, log2Up(maxDownSize)) val aHasData = edgeIn.hasData(in_a.bits) val aMask = Mux(aHasData, 0.U, aFragOH1) val gennum = RegInit(0.U(counterBits.W)) val aFirst = gennum === 0.U val old_gennum1 = Mux(aFirst, aOrigOH1 >> log2Ceil(beatBytes), gennum - 1.U) val new_gennum = ~(~old_gennum1 \| (aMask >> log2Ceil(beatBytes))) // ~(~x\|y) is width safe val aFragnum = ~(~(old_gennum1 >> log2Ceil(minSize/beatBytes)) \| (aFragOH1 >> log2Ceil(minSize))) val aLast = aFragnum === 0.U val aToggle = !Mux(aFirst, dToggle, RegEnable(dToggle, aFirst)) val aFull = if (earlyAck == EarlyAck.PutFulls) Some(in_a.bits.opcode === TLMessages.PutFullData) else None when (out.a.fire) { gennum := new_gennum } repeater.io.repeat := !aHasData && aFragnum =/= 0.U out.a <> in_a out.a.bits.address := in_a.bits.address \| ~(old_gennum1 << log2Ceil(beatBytes) \| ~aOrigOH1 \| aFragOH1 \| (minSize-1).U) out.a.bits.source := Cat(Seq(in_a.bits.source) ++ aFull ++ Seq(aToggle.asUInt, aFragnum)) out.a.bits.size := aFrag // Optimize away some of the Repeater's registers assert (!repeater.io.full \|\| !aHasData) out.a.bits.data := in.a.bits.data val fullMask = ((BigInt(1) << beatBytes) - 1).U assert (!repeater.io.full \|\| in_a.bits.mask === fullMask) out.a.bits.mask := Mux(repeater.io.full, fullMask, in.a.bits.mask) out.a.bits.user.waiveAll :<= in.a.bits.user.subset(_.isData) // Tie off unused channels in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLFragmenter { def apply(minSize: Int, maxSize: Int, alwaysMin: Boolean = false, earlyAck: EarlyAck.T = EarlyAck.None, holdFirstDeny: Boolean = false, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode = { if (minSize <= maxSize) { val fragmenter = LazyModule(new TLFragmenter(minSize, maxSize, alwaysMin, earlyAck, holdFirstDeny, nameSuffix)) fragmenter.node } else { TLEphemeralNode()(ValName("no_fragmenter")) } } def apply(wrapper: TLBusWrapper, nameSuffix: Option[String])(implicit p: Parameters): TLNode = apply(wrapper.beatBytes, wrapper.blockBytes, nameSuffix = nameSuffix) def apply(wrapper: TLBusWrapper)(implicit p: Parameters): TLNode = apply(wrapper, None) } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMFragmenter(ramBeatBytes: Int, maxSize: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("Fragmenter")) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes)) (ram.node := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := TLDelayer(0.1) := TLFragmenter(ramBeatBytes, maxSize, earlyAck = EarlyAck.AllPuts) := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := TLFragmenter(ramBeatBytes, maxSize/2) := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := model.node := fuzz.node) lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMFragmenterTest(ramBeatBytes: Int, maxSize: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMFragmenter(ramBeatBytes,maxSize,txns)).module) io.finished := dut.io.finished dut.io.start := io.start } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } }	module TLInterconnectCoupler_cbus_to_plic( // @[LazyModuleImp.scala:138:7] input clock, // @[LazyModuleImp.scala:138:7] input reset, // @[LazyModuleImp.scala:138:7] input auto_fragmenter_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_fragmenter_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_fragmenter_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_fragmenter_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_fragmenter_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [11:0] auto_fragmenter_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [27:0] auto_fragmenter_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_fragmenter_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_fragmenter_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_fragmenter_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_fragmenter_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_fragmenter_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_fragmenter_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_fragmenter_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [11:0] auto_fragmenter_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_fragmenter_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_tl_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [7:0] auto_tl_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [27:0] auto_tl_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_tl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_tl_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_tl_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [7:0] auto_tl_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_tl_in_d_bits_data // @[LazyModuleImp.scala:107:25] ); TLFragmenter_PLIC fragmenter ( // @[Fragmenter.scala:345:34] .clock (clock), .reset (reset), .auto_anon_in_a_ready (auto_tl_in_a_ready), .auto_anon_in_a_valid (auto_tl_in_a_valid), .auto_anon_in_a_bits_opcode (auto_tl_in_a_bits_opcode), .auto_anon_in_a_bits_param (auto_tl_in_a_bits_param), .auto_anon_in_a_bits_size (auto_tl_in_a_bits_size), .auto_anon_in_a_bits_source (auto_tl_in_a_bits_source), .auto_anon_in_a_bits_address (auto_tl_in_a_bits_address), .auto_anon_in_a_bits_mask (auto_tl_in_a_bits_mask), .auto_anon_in_a_bits_data (auto_tl_in_a_bits_data), .auto_anon_in_a_bits_corrupt (auto_tl_in_a_bits_corrupt), .auto_anon_in_d_ready (auto_tl_in_d_ready), .auto_anon_in_d_valid (auto_tl_in_d_valid), .auto_anon_in_d_bits_opcode (auto_tl_in_d_bits_opcode), .auto_anon_in_d_bits_size (auto_tl_in_d_bits_size), .auto_anon_in_d_bits_source (auto_tl_in_d_bits_source), .auto_anon_in_d_bits_data (auto_tl_in_d_bits_data), .auto_anon_out_a_ready (auto_fragmenter_anon_out_a_ready), .auto_anon_out_a_valid (auto_fragmenter_anon_out_a_valid), .auto_anon_out_a_bits_opcode (auto_fragmenter_anon_out_a_bits_opcode), .auto_anon_out_a_bits_param (auto_fragmenter_anon_out_a_bits_param), .auto_anon_out_a_bits_size (auto_fragmenter_anon_out_a_bits_size), .auto_anon_out_a_bits_source (auto_fragmenter_anon_out_a_bits_source), .auto_anon_out_a_bits_address (auto_fragmenter_anon_out_a_bits_address), .auto_anon_out_a_bits_mask (auto_fragmenter_anon_out_a_bits_mask), .auto_anon_out_a_bits_data (auto_fragmenter_anon_out_a_bits_data), .auto_anon_out_a_bits_corrupt (auto_fragmenter_anon_out_a_bits_corrupt), .auto_anon_out_d_ready (auto_fragmenter_anon_out_d_ready), .auto_anon_out_d_valid (auto_fragmenter_anon_out_d_valid), .auto_anon_out_d_bits_opcode (auto_fragmenter_anon_out_d_bits_opcode), .auto_anon_out_d_bits_size (auto_fragmenter_anon_out_d_bits_size), .auto_anon_out_d_bits_source (auto_fragmenter_anon_out_d_bits_source), .auto_anon_out_d_bits_data (auto_fragmenter_anon_out_d_bits_data) ); // @[Fragmenter.scala:345:34] endmodule
Generate the Verilog code corresponding to the following Chisel files. File DescribedSRAM.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3.{Data, SyncReadMem, Vec} import chisel3.util.log2Ceil object DescribedSRAM { def apply[T <: Data]( name: String, desc: String, size: BigInt, // depth data: T ): SyncReadMem[T] = { val mem = SyncReadMem(size, data) mem.suggestName(name) val granWidth = data match { case v: Vec[_] => v.head.getWidth case d => d.getWidth } val uid = 0 Annotated.srams( component = mem, name = name, address_width = log2Ceil(size), data_width = data.getWidth, depth = size, description = desc, write_mask_granularity = granWidth ) mem } }	module dataArrayB0Way_7_0( // @[DescribedSRAM.scala:17:26] input [7:0] RW0_addr, input RW0_en, input RW0_clk, input RW0_wmode, input [63:0] RW0_wdata, output [63:0] RW0_rdata ); dataArrayB0Way_0_ext dataArrayB0Way_0_ext ( // @[DescribedSRAM.scala:17:26] .RW0_addr (RW0_addr), .RW0_en (RW0_en), .RW0_clk (RW0_clk), .RW0_wmode (RW0_wmode), .RW0_wdata (RW0_wdata), .RW0_rdata (RW0_rdata) ); // @[DescribedSRAM.scala:17:26] endmodule
Generate the Verilog code corresponding to the following Chisel files. File TilelinkAdapters.scala: package constellation.protocol import chisel3._ import chisel3.util._ import constellation.channel._ import constellation.noc._ import constellation.soc.{CanAttachToGlobalNoC} import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.util._ import freechips.rocketchip.tilelink._ import scala.collection.immutable.{ListMap} abstract class TLChannelToNoC[T <: TLChannel](gen: => T, edge: TLEdge, idToEgress: Int => Int)(implicit val p: Parameters) extends Module with TLFieldHelper { val flitWidth = minTLPayloadWidth(gen) val io = IO(new Bundle { val protocol = Flipped(Decoupled(gen)) val flit = Decoupled(new IngressFlit(flitWidth)) }) def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B // convert decoupled to irrevocable val q = Module(new Queue(gen, 1, pipe=true, flow=true)) val protocol = q.io.deq val has_body = Wire(Bool()) val body_fields = getBodyFields(protocol.bits) val const_fields = getConstFields(protocol.bits) val head = edge.first(protocol.bits, protocol.fire) val tail = edge.last(protocol.bits, protocol.fire) def requestOH: Seq[Bool] val body = Cat( body_fields.filter(_.getWidth > 0).map(_.asUInt)) val const = Cat(const_fields.filter(_.getWidth > 0).map(_.asUInt)) val is_body = RegInit(false.B) io.flit.valid := protocol.valid protocol.ready := io.flit.ready && (is_body \|\| !has_body) io.flit.bits.head := head && !is_body io.flit.bits.tail := tail && (is_body \|\| !has_body) io.flit.bits.egress_id := Mux1H(requestOH.zipWithIndex.map { case (r, i) => r -> idToEgress(i).U }) io.flit.bits.payload := Mux(is_body, body, const) when (io.flit.fire && io.flit.bits.head) { is_body := true.B } when (io.flit.fire && io.flit.bits.tail) { is_body := false.B } } abstract class TLChannelFromNoC[T <: TLChannel](gen: => T)(implicit val p: Parameters) extends Module with TLFieldHelper { val flitWidth = minTLPayloadWidth(gen) val io = IO(new Bundle { val protocol = Decoupled(gen) val flit = Flipped(Decoupled(new EgressFlit(flitWidth))) }) // Handle size = 1 gracefully (Chisel3 empty range is broken) def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0) val protocol = Wire(Decoupled(gen)) val body_fields = getBodyFields(protocol.bits) val const_fields = getConstFields(protocol.bits) val is_const = RegInit(true.B) val const_reg = Reg(UInt(const_fields.map(_.getWidth).sum.W)) val const = Mux(io.flit.bits.head, io.flit.bits.payload, const_reg) io.flit.ready := (is_const && !io.flit.bits.tail) \|\| protocol.ready protocol.valid := (!is_const \|\| io.flit.bits.tail) && io.flit.valid def assign(i: UInt, sigs: Seq[Data]) = { var t = i for (s <- sigs.reverse) { s := t.asTypeOf(s.cloneType) t = t >> s.getWidth } } assign(const, const_fields) assign(io.flit.bits.payload, body_fields) when (io.flit.fire && io.flit.bits.head) { is_const := false.B; const_reg := io.flit.bits.payload } when (io.flit.fire && io.flit.bits.tail) { is_const := true.B } } trait HasAddressDecoder { // Filter a list to only those elements selected def filter[T](data: Seq[T], mask: Seq[Boolean]) = (data zip mask).filter(_._2).map(_._1) val edgeIn: TLEdge val edgesOut: Seq[TLEdge] lazy val reacheableIO = edgesOut.map { mp => edgeIn.client.clients.exists { c => mp.manager.managers.exists { m => c.visibility.exists { ca => m.address.exists { ma => ca.overlaps(ma) }} }} }.toVector lazy val releaseIO = (edgesOut zip reacheableIO).map { case (mp, reachable) => reachable && edgeIn.client.anySupportProbe && mp.manager.anySupportAcquireB }.toVector def outputPortFn(connectIO: Seq[Boolean]) = { val port_addrs = edgesOut.map(_.manager.managers.flatMap(_.address)) val routingMask = AddressDecoder(filter(port_addrs, connectIO)) val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct)) route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_\|\|_)) } } class TLAToNoC( val edgeIn: TLEdge, val edgesOut: Seq[TLEdge], bundle: TLBundleParameters, slaveToAEgress: Int => Int, sourceStart: Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleA(bundle), edgeIn, slaveToAEgress)(p) with HasAddressDecoder { has_body := edgeIn.hasData(protocol.bits) \|\| (~protocol.bits.mask =/= 0.U) lazy val connectAIO = reacheableIO lazy val requestOH = outputPortFn(connectAIO).zipWithIndex.map { case (o, j) => connectAIO(j).B && (unique(connectAIO) \|\| o(protocol.bits.address)) } q.io.enq <> io.protocol q.io.enq.bits.source := io.protocol.bits.source \| sourceStart.U } class TLAFromNoC(edgeOut: TLEdge, bundle: TLBundleParameters)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleA(bundle))(p) { io.protocol <> protocol when (io.flit.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) } } class TLBToNoC( edgeOut: TLEdge, edgesIn: Seq[TLEdge], bundle: TLBundleParameters, masterToBIngress: Int => Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleB(bundle), edgeOut, masterToBIngress)(p) { has_body := edgeOut.hasData(protocol.bits) \|\| (~protocol.bits.mask =/= 0.U) lazy val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client)) lazy val requestOH = inputIdRanges.map { i => i.contains(protocol.bits.source) } q.io.enq <> io.protocol } class TLBFromNoC(edgeIn: TLEdge, bundle: TLBundleParameters, sourceSize: Int)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleB(bundle))(p) { io.protocol <> protocol io.protocol.bits.source := trim(protocol.bits.source, sourceSize) when (io.flit.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) } } class TLCToNoC( val edgeIn: TLEdge, val edgesOut: Seq[TLEdge], bundle: TLBundleParameters, slaveToCEgress: Int => Int, sourceStart: Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleC(bundle), edgeIn, slaveToCEgress)(p) with HasAddressDecoder { has_body := edgeIn.hasData(protocol.bits) lazy val connectCIO = releaseIO lazy val requestOH = outputPortFn(connectCIO).zipWithIndex.map { case (o, j) => connectCIO(j).B && (unique(connectCIO) \|\| o(protocol.bits.address)) } q.io.enq <> io.protocol q.io.enq.bits.source := io.protocol.bits.source \| sourceStart.U } class TLCFromNoC(edgeOut: TLEdge, bundle: TLBundleParameters)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleC(bundle))(p) { io.protocol <> protocol } class TLDToNoC( edgeOut: TLEdge, edgesIn: Seq[TLEdge], bundle: TLBundleParameters, masterToDIngress: Int => Int, sourceStart: Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleD(bundle), edgeOut, masterToDIngress)(p) { has_body := edgeOut.hasData(protocol.bits) lazy val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client)) lazy val requestOH = inputIdRanges.map { i => i.contains(protocol.bits.source) } q.io.enq <> io.protocol q.io.enq.bits.sink := io.protocol.bits.sink \| sourceStart.U } class TLDFromNoC(edgeIn: TLEdge, bundle: TLBundleParameters, sourceSize: Int)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleD(bundle))(p) { io.protocol <> protocol io.protocol.bits.source := trim(protocol.bits.source, sourceSize) } class TLEToNoC( val edgeIn: TLEdge, val edgesOut: Seq[TLEdge], bundle: TLBundleParameters, slaveToEEgress: Int => Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleE(bundle), edgeIn, slaveToEEgress)(p) { has_body := edgeIn.hasData(protocol.bits) lazy val outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager)) lazy val requestOH = outputIdRanges.map { o => o.contains(protocol.bits.sink) } q.io.enq <> io.protocol } class TLEFromNoC(edgeOut: TLEdge, bundle: TLBundleParameters, sourceSize: Int)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleE(bundle))(p) { io.protocol <> protocol io.protocol.bits.sink := trim(protocol.bits.sink, sourceSize) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLCToNoC_5( // @[TilelinkAdapters.scala:151:7] input clock, // @[TilelinkAdapters.scala:151:7] input reset, // @[TilelinkAdapters.scala:151:7] output io_protocol_ready, // @[TilelinkAdapters.scala:19:14] input io_protocol_valid, // @[TilelinkAdapters.scala:19:14] input [2:0] io_protocol_bits_opcode, // @[TilelinkAdapters.scala:19:14] input [2:0] io_protocol_bits_param, // @[TilelinkAdapters.scala:19:14] input [3:0] io_protocol_bits_size, // @[TilelinkAdapters.scala:19:14] input [5:0] io_protocol_bits_source, // @[TilelinkAdapters.scala:19:14] input [31:0] io_protocol_bits_address, // @[TilelinkAdapters.scala:19:14] input [63:0] io_protocol_bits_data, // @[TilelinkAdapters.scala:19:14] input io_protocol_bits_corrupt, // @[TilelinkAdapters.scala:19:14] input io_flit_ready, // @[TilelinkAdapters.scala:19:14] output io_flit_valid, // @[TilelinkAdapters.scala:19:14] output io_flit_bits_head, // @[TilelinkAdapters.scala:19:14] output io_flit_bits_tail, // @[TilelinkAdapters.scala:19:14] output [64:0] io_flit_bits_payload, // @[TilelinkAdapters.scala:19:14] output [4:0] io_flit_bits_egress_id // @[TilelinkAdapters.scala:19:14] ); wire _q_io_deq_valid; // @[TilelinkAdapters.scala:26:17] wire [2:0] _q_io_deq_bits_opcode; // @[TilelinkAdapters.scala:26:17] wire [2:0] _q_io_deq_bits_param; // @[TilelinkAdapters.scala:26:17] wire [3:0] _q_io_deq_bits_size; // @[TilelinkAdapters.scala:26:17] wire [5:0] _q_io_deq_bits_source; // @[TilelinkAdapters.scala:26:17] wire [31:0] _q_io_deq_bits_address; // @[TilelinkAdapters.scala:26:17] wire [63:0] _q_io_deq_bits_data; // @[TilelinkAdapters.scala:26:17] wire _q_io_deq_bits_corrupt; // @[TilelinkAdapters.scala:26:17] wire [26:0] _tail_beats1_decode_T = 27'hFFF << _q_io_deq_bits_size; // @[package.scala:243:71] reg [8:0] head_counter; // @[Edges.scala:229:27] wire head = head_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire [8:0] tail_beats1 = _q_io_deq_bits_opcode[0] ? ~(_tail_beats1_decode_T[11:3]) : 9'h0; // @[package.scala:243:{46,71,76}] reg [8:0] tail_counter; // @[Edges.scala:229:27] reg is_body; // @[TilelinkAdapters.scala:39:24] wire q_io_deq_ready = io_flit_ready & (is_body \| ~(_q_io_deq_bits_opcode[0])); // @[Edges.scala:102:36] wire io_flit_bits_head_0 = head & ~is_body; // @[Edges.scala:231:25] wire io_flit_bits_tail_0 = (tail_counter == 9'h1 \| tail_beats1 == 9'h0) & (is_body \| ~(_q_io_deq_bits_opcode[0])); // @[Edges.scala:102:36, :221:14, :229:27, :232:{25,33,43}] wire _GEN = io_flit_ready & _q_io_deq_valid; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[TilelinkAdapters.scala:151:7] if (reset) begin // @[TilelinkAdapters.scala:151:7] head_counter <= 9'h0; // @[Edges.scala:229:27] tail_counter <= 9'h0; // @[Edges.scala:229:27] is_body <= 1'h0; // @[TilelinkAdapters.scala:39:24, :151:7] end else begin // @[TilelinkAdapters.scala:151:7] if (q_io_deq_ready & _q_io_deq_valid) begin // @[Decoupled.scala:51:35] head_counter <= head ? (_q_io_deq_bits_opcode[0] ? ~(_tail_beats1_decode_T[11:3]) : 9'h0) : head_counter - 9'h1; // @[package.scala:243:{46,71,76}] tail_counter <= tail_counter == 9'h0 ? tail_beats1 : tail_counter - 9'h1; // @[Edges.scala:221:14, :229:27, :230:28, :231:25, :236:21] end is_body <= ~(_GEN & io_flit_bits_tail_0) & (_GEN & io_flit_bits_head_0 \| is_body); // @[Decoupled.scala:51:35] end always @(posedge)
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag }	module OptimizationBarrier_TLBEntryData_212( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_97( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)
Generate the Verilog code corresponding to the following Chisel files. File INToRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import consts._ class INToRecFN(intWidth: Int, expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"INToRecFN_i${intWidth}_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val signedIn = Input(Bool()) val in = Input(Bits(intWidth.W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val intAsRawFloat = rawFloatFromIN(io.signedIn, io.in); val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( intAsRawFloat.expWidth, intWidth, expWidth, sigWidth, flRoundOpt_sigMSBitAlwaysZero \| flRoundOpt_neverUnderflows )) roundAnyRawFNToRecFN.io.invalidExc := false.B roundAnyRawFNToRecFN.io.infiniteExc := false.B roundAnyRawFNToRecFN.io.in := intAsRawFloat roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags } File primitives.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object lowMask { def apply(in: UInt, topBound: BigInt, bottomBound: BigInt): UInt = { require(topBound != bottomBound) val numInVals = BigInt(1)<<in.getWidth if (topBound < bottomBound) { lowMask(~in, numInVals - 1 - topBound, numInVals - 1 - bottomBound) } else if (numInVals > 64 /* Empirical /) { // For simulation performance, we should avoid generating // exteremely wide shifters, so we divide and conquer. // Empirically, this does not impact synthesis QoR. val mid = numInVals / 2 val msb = in(in.getWidth - 1) val lsbs = in(in.getWidth - 2, 0) if (mid < topBound) { if (mid <= bottomBound) { Mux(msb, lowMask(lsbs, topBound - mid, bottomBound - mid), 0.U ) } else { Mux(msb, lowMask(lsbs, topBound - mid, 0) ## ((BigInt(1)<<(mid - bottomBound).toInt) - 1).U, lowMask(lsbs, mid, bottomBound) ) } } else { ~Mux(msb, 0.U, ~lowMask(lsbs, topBound, bottomBound)) } } else { val shift = (BigInt(-1)<<numInVals.toInt).S>>in Reverse( shift( (numInVals - 1 - bottomBound).toInt, (numInVals - topBound).toInt ) ) } } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object countLeadingZeros { def apply(in: UInt): UInt = PriorityEncoder(in.asBools.reverse) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy2 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 1)>>1 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix 2 + 1, ix * 2).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 2).orR reducedVec.asUInt } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy4 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 3)>>2 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 4 + 3, ix * 4).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 4).orR reducedVec.asUInt } } File rawFloatFromIN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util._ object rawFloatFromIN { def apply(signedIn: Bool, in: Bits): RawFloat = { val expWidth = log2Up(in.getWidth) + 1 //*** CHANGE THIS; CAN BE VERY LARGE: val extIntWidth = 1<<(expWidth - 1) val sign = signedIn && in(in.getWidth - 1) val absIn = Mux(sign, -in.asUInt, in.asUInt) val extAbsIn = (0.U(extIntWidth.W) ## absIn)(extIntWidth - 1, 0) val adjustedNormDist = countLeadingZeros(extAbsIn) val sig = (extAbsIn<<adjustedNormDist)( extIntWidth - 1, extIntWidth - in.getWidth) val out = Wire(new RawFloat(expWidth, in.getWidth)) out.isNaN := false.B out.isInf := false.B out.isZero := ! sig(in.getWidth - 1) out.sign := sign out.sExp := (2.U(2.W) ## ~adjustedNormDist(expWidth - 2, 0)).zext out.sig := sig out } }	module INToRecFN_i1_e8_s24_7(); // @[INToRecFN.scala:43:7] wire [1:0] _intAsRawFloat_absIn_T = 2'h3; // @[rawFloatFromIN.scala:52:31] wire [2:0] _intAsRawFloat_extAbsIn_T = 3'h1; // @[rawFloatFromIN.scala:53:44] wire [2:0] _intAsRawFloat_sig_T = 3'h2; // @[rawFloatFromIN.scala:56:22] wire [2:0] _intAsRawFloat_out_sExp_T_2 = 3'h4; // @[rawFloatFromIN.scala:64:33] wire [3:0] intAsRawFloat_sExp = 4'h4; // @[rawFloatFromIN.scala:59:23, :64:72] wire [3:0] _intAsRawFloat_out_sExp_T_3 = 4'h4; // @[rawFloatFromIN.scala:59:23, :64:72] wire [1:0] intAsRawFloat_extAbsIn = 2'h1; // @[rawFloatFromIN.scala:53:53, :59:23, :65:20] wire [1:0] intAsRawFloat_sig = 2'h1; // @[rawFloatFromIN.scala:53:53, :59:23, :65:20] wire [4:0] io_exceptionFlags = 5'h0; // @[INToRecFN.scala:43:7, :46:16, :60:15] wire [32:0] io_out = 33'h80000000; // @[INToRecFN.scala:43:7, :46:16, :60:15] wire [2:0] io_roundingMode = 3'h0; // @[INToRecFN.scala:43:7, :46:16, :60:15] wire io_in = 1'h1; // @[Mux.scala:50:70] wire io_detectTininess = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_sign_T = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_absIn_T_1 = 1'h1; // @[Mux.scala:50:70] wire intAsRawFloat_absIn = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_adjustedNormDist_T = 1'h1; // @[Mux.scala:50:70] wire intAsRawFloat_adjustedNormDist = 1'h1; // @[Mux.scala:50:70] wire intAsRawFloat_sig_0 = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_out_isZero_T = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_out_sExp_T = 1'h1; // @[Mux.scala:50:70] wire io_signedIn = 1'h0; // @[INToRecFN.scala:43:7] wire intAsRawFloat_sign = 1'h0; // @[rawFloatFromIN.scala:51:29] wire _intAsRawFloat_adjustedNormDist_T_1 = 1'h0; // @[primitives.scala:91:52] wire intAsRawFloat_isNaN = 1'h0; // @[rawFloatFromIN.scala:59:23] wire intAsRawFloat_isInf = 1'h0; // @[rawFloatFromIN.scala:59:23] wire intAsRawFloat_isZero = 1'h0; // @[rawFloatFromIN.scala:59:23] wire intAsRawFloat_sign_0 = 1'h0; // @[rawFloatFromIN.scala:59:23] wire _intAsRawFloat_out_isZero_T_1 = 1'h0; // @[rawFloatFromIN.scala:62:23] wire _intAsRawFloat_out_sExp_T_1 = 1'h0; // @[rawFloatFromIN.scala:64:36] RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_7 roundAnyRawFNToRecFN (); // @[INToRecFN.scala:60:15] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Arbiter.scala: package shuttle.dmem import chisel3._ import chisel3.util.{Cat,log2Up} import org.chipsalliance.cde.config.Parameters class ShuttleDCacheArbiter(n: Int)(implicit p: Parameters) extends Module { val io = IO(new Bundle { val requestor = Flipped(Vec(n, new ShuttleDCacheIO)) val mem = new ShuttleDCacheIO }) if (n == 1) { io.mem <> io.requestor.head } else { val s1_id = Reg(UInt()) val s2_id = RegNext(s1_id) io.mem.keep_clock_enabled := io.requestor.map(_.keep_clock_enabled).reduce(_\|\|_) io.mem.req.valid := io.requestor.map(_.req.valid).reduce(_\|\|_) io.requestor(0).req.ready := io.mem.req.ready for (i <- 1 until n) io.requestor(i).req.ready := io.requestor(i-1).req.ready && !io.requestor(i-1).req.valid for (i <- n-1 to 0 by -1) { val req = io.requestor(i).req def connect_s0() = { io.mem.req.bits := req.bits io.mem.req.bits.tag := Cat(req.bits.tag, i.U(log2Up(n).W)) s1_id := i.U } def connect_s1() = { io.mem.s1_paddr := io.requestor(i).s1_paddr io.mem.s1_kill := io.requestor(i).s1_kill io.mem.s1_data := io.requestor(i).s1_data } def connect_s2() = { io.mem.s2_kill := io.requestor(i).s2_kill } if (i == n-1) { connect_s0() connect_s1() connect_s2() } else { when (req.valid) { connect_s0() } when (s1_id === i.U) { connect_s1() } when (s2_id === i.U) { connect_s2() } } } for (i <- 0 until n) { val resp = io.requestor(i).resp val tag_hit = io.mem.resp.bits.tag(log2Up(n)-1,0) === i.U resp.valid := io.mem.resp.valid && tag_hit io.requestor(i).ordered := io.mem.ordered io.requestor(i).store_pending := io.mem.store_pending io.requestor(i).perf := io.mem.perf io.requestor(i).s2_nack := io.mem.s2_nack && s2_id === i.U io.requestor(i).clock_enabled := io.mem.clock_enabled io.requestor(i).s2_hit := io.mem.s2_hit && s2_id === i.U resp.bits := io.mem.resp.bits resp.bits.tag := io.mem.resp.bits.tag >> log2Up(n) } } }	module ShuttleDCacheArbiter( // @[Arbiter.scala:7:7] input clock, // @[Arbiter.scala:7:7] input reset, // @[Arbiter.scala:7:7] output io_requestor_0_req_ready, // @[Arbiter.scala:9:14] input io_requestor_0_req_valid, // @[Arbiter.scala:9:14] input [39:0] io_requestor_0_req_bits_addr, // @[Arbiter.scala:9:14] input [31:0] io_requestor_0_s1_paddr, // @[Arbiter.scala:9:14] input io_requestor_0_s1_kill, // @[Arbiter.scala:9:14] output io_requestor_0_s2_nack, // @[Arbiter.scala:9:14] output io_requestor_0_resp_valid, // @[Arbiter.scala:9:14] output io_requestor_0_resp_bits_has_data, // @[Arbiter.scala:9:14] output [6:0] io_requestor_0_resp_bits_tag, // @[Arbiter.scala:9:14] output [63:0] io_requestor_0_resp_bits_data, // @[Arbiter.scala:9:14] output [1:0] io_requestor_0_resp_bits_size, // @[Arbiter.scala:9:14] output io_requestor_0_s2_hit, // @[Arbiter.scala:9:14] output io_requestor_0_ordered, // @[Arbiter.scala:9:14] output io_requestor_0_store_pending, // @[Arbiter.scala:9:14] output io_requestor_0_perf_acquire, // @[Arbiter.scala:9:14] output io_requestor_0_perf_release, // @[Arbiter.scala:9:14] output io_requestor_0_perf_grant, // @[Arbiter.scala:9:14] output io_requestor_1_req_ready, // @[Arbiter.scala:9:14] input io_requestor_1_req_valid, // @[Arbiter.scala:9:14] input [39:0] io_requestor_1_req_bits_addr, // @[Arbiter.scala:9:14] input [6:0] io_requestor_1_req_bits_tag, // @[Arbiter.scala:9:14] input [4:0] io_requestor_1_req_bits_cmd, // @[Arbiter.scala:9:14] input [1:0] io_requestor_1_req_bits_size, // @[Arbiter.scala:9:14] input io_requestor_1_req_bits_signed, // @[Arbiter.scala:9:14] input [31:0] io_requestor_1_s1_paddr, // @[Arbiter.scala:9:14] input io_requestor_1_s1_kill, // @[Arbiter.scala:9:14] input [63:0] io_requestor_1_s1_data_data, // @[Arbiter.scala:9:14] output io_requestor_1_s2_nack, // @[Arbiter.scala:9:14] input io_requestor_1_s2_kill, // @[Arbiter.scala:9:14] output io_requestor_1_resp_valid, // @[Arbiter.scala:9:14] output io_requestor_1_resp_bits_has_data, // @[Arbiter.scala:9:14] output [6:0] io_requestor_1_resp_bits_tag, // @[Arbiter.scala:9:14] output [63:0] io_requestor_1_resp_bits_data, // @[Arbiter.scala:9:14] output [1:0] io_requestor_1_resp_bits_size, // @[Arbiter.scala:9:14] output io_requestor_1_s2_hit, // @[Arbiter.scala:9:14] output io_requestor_1_ordered, // @[Arbiter.scala:9:14] output io_requestor_1_store_pending, // @[Arbiter.scala:9:14] output io_requestor_1_perf_acquire, // @[Arbiter.scala:9:14] output io_requestor_1_perf_release, // @[Arbiter.scala:9:14] output io_requestor_1_perf_grant, // @[Arbiter.scala:9:14] input io_mem_req_ready, // @[Arbiter.scala:9:14] output io_mem_req_valid, // @[Arbiter.scala:9:14] output [39:0] io_mem_req_bits_addr, // @[Arbiter.scala:9:14] output [6:0] io_mem_req_bits_tag, // @[Arbiter.scala:9:14] output [4:0] io_mem_req_bits_cmd, // @[Arbiter.scala:9:14] output [1:0] io_mem_req_bits_size, // @[Arbiter.scala:9:14] output io_mem_req_bits_signed, // @[Arbiter.scala:9:14] output [31:0] io_mem_s1_paddr, // @[Arbiter.scala:9:14] output io_mem_s1_kill, // @[Arbiter.scala:9:14] output [63:0] io_mem_s1_data_data, // @[Arbiter.scala:9:14] input io_mem_s2_nack, // @[Arbiter.scala:9:14] output io_mem_s2_kill, // @[Arbiter.scala:9:14] input io_mem_resp_valid, // @[Arbiter.scala:9:14] input io_mem_resp_bits_has_data, // @[Arbiter.scala:9:14] input [6:0] io_mem_resp_bits_tag, // @[Arbiter.scala:9:14] input [63:0] io_mem_resp_bits_data, // @[Arbiter.scala:9:14] input [1:0] io_mem_resp_bits_size, // @[Arbiter.scala:9:14] input io_mem_s2_hit, // @[Arbiter.scala:9:14] input io_mem_ordered, // @[Arbiter.scala:9:14] input io_mem_store_pending, // @[Arbiter.scala:9:14] input io_mem_perf_acquire, // @[Arbiter.scala:9:14] input io_mem_perf_release, // @[Arbiter.scala:9:14] input io_mem_perf_grant // @[Arbiter.scala:9:14] ); wire io_requestor_0_req_valid_0 = io_requestor_0_req_valid; // @[Arbiter.scala:7:7] wire [39:0] io_requestor_0_req_bits_addr_0 = io_requestor_0_req_bits_addr; // @[Arbiter.scala:7:7] wire [31:0] io_requestor_0_s1_paddr_0 = io_requestor_0_s1_paddr; // @[Arbiter.scala:7:7] wire io_requestor_0_s1_kill_0 = io_requestor_0_s1_kill; // @[Arbiter.scala:7:7] wire io_requestor_1_req_valid_0 = io_requestor_1_req_valid; // @[Arbiter.scala:7:7] wire [39:0] io_requestor_1_req_bits_addr_0 = io_requestor_1_req_bits_addr; // @[Arbiter.scala:7:7] wire [6:0] io_requestor_1_req_bits_tag_0 = io_requestor_1_req_bits_tag; // @[Arbiter.scala:7:7] wire [4:0] io_requestor_1_req_bits_cmd_0 = io_requestor_1_req_bits_cmd; // @[Arbiter.scala:7:7] wire [1:0] io_requestor_1_req_bits_size_0 = io_requestor_1_req_bits_size; // @[Arbiter.scala:7:7] wire io_requestor_1_req_bits_signed_0 = io_requestor_1_req_bits_signed; // @[Arbiter.scala:7:7] wire [31:0] io_requestor_1_s1_paddr_0 = io_requestor_1_s1_paddr; // @[Arbiter.scala:7:7] wire io_requestor_1_s1_kill_0 = io_requestor_1_s1_kill; // @[Arbiter.scala:7:7] wire [63:0] io_requestor_1_s1_data_data_0 = io_requestor_1_s1_data_data; // @[Arbiter.scala:7:7] wire io_requestor_1_s2_kill_0 = io_requestor_1_s2_kill; // @[Arbiter.scala:7:7] wire io_mem_req_ready_0 = io_mem_req_ready; // @[Arbiter.scala:7:7] wire io_mem_s2_nack_0 = io_mem_s2_nack; // @[Arbiter.scala:7:7] wire io_mem_resp_valid_0 = io_mem_resp_valid; // @[Arbiter.scala:7:7] wire io_mem_resp_bits_has_data_0 = io_mem_resp_bits_has_data; // @[Arbiter.scala:7:7] wire [6:0] io_mem_resp_bits_tag_0 = io_mem_resp_bits_tag; // @[Arbiter.scala:7:7] wire [63:0] io_mem_resp_bits_data_0 = io_mem_resp_bits_data; // @[Arbiter.scala:7:7] wire [1:0] io_mem_resp_bits_size_0 = io_mem_resp_bits_size; // @[Arbiter.scala:7:7] wire io_mem_s2_hit_0 = io_mem_s2_hit; // @[Arbiter.scala:7:7] wire io_mem_ordered_0 = io_mem_ordered; // @[Arbiter.scala:7:7] wire io_mem_store_pending_0 = io_mem_store_pending; // @[Arbiter.scala:7:7] wire io_mem_perf_acquire_0 = io_mem_perf_acquire; // @[Arbiter.scala:7:7] wire io_mem_perf_release_0 = io_mem_perf_release; // @[Arbiter.scala:7:7] wire io_mem_perf_grant_0 = io_mem_perf_grant; // @[Arbiter.scala:7:7] wire io_requestor_0_clock_enabled = 1'h1; // @[Arbiter.scala:7:7] wire io_requestor_1_keep_clock_enabled = 1'h1; // @[Arbiter.scala:7:7] wire io_requestor_1_clock_enabled = 1'h1; // @[Arbiter.scala:7:7] wire io_mem_keep_clock_enabled = 1'h1; // @[Arbiter.scala:7:7] wire io_mem_clock_enabled = 1'h1; // @[Arbiter.scala:7:7] wire _io_mem_keep_clock_enabled_T = 1'h1; // @[Arbiter.scala:20:81] wire [7:0] io_requestor_0_req_bits_mask = 8'h0; // @[Arbiter.scala:7:7, :9:14, :30:25, :31:35, :37:24, :48:26, :49:30] wire [7:0] io_requestor_0_s1_data_mask = 8'h0; // @[Arbiter.scala:7:7, :9:14, :30:25, :31:35, :37:24, :48:26, :49:30] wire [7:0] io_requestor_1_req_bits_mask = 8'h0; // @[Arbiter.scala:7:7, :9:14, :30:25, :31:35, :37:24, :48:26, :49:30] wire [7:0] io_requestor_1_s1_data_mask = 8'h0; // @[Arbiter.scala:7:7, :9:14, :30:25, :31:35, :37:24, :48:26, :49:30] wire [7:0] io_mem_req_bits_mask = 8'h0; // @[Arbiter.scala:7:7, :9:14, :30:25, :31:35, :37:24, :48:26, :49:30] wire [7:0] io_mem_s1_data_mask = 8'h0; // @[Arbiter.scala:7:7, :9:14, :30:25, :31:35, :37:24, :48:26, :49:30] wire [7:0] _io_mem_req_bits_tag_T_1 = 8'h0; // @[Arbiter.scala:7:7, :9:14, :30:25, :31:35, :37:24, :48:26, :49:30] wire [63:0] io_requestor_0_req_bits_data = 64'h0; // @[Arbiter.scala:7:7, :9:14, :30:25, :48:26] wire [63:0] io_requestor_0_s1_data_data = 64'h0; // @[Arbiter.scala:7:7, :9:14, :30:25, :48:26] wire [63:0] io_requestor_1_req_bits_data = 64'h0; // @[Arbiter.scala:7:7, :9:14, :30:25, :48:26] wire [63:0] io_mem_req_bits_data = 64'h0; // @[Arbiter.scala:7:7, :9:14, :30:25, :48:26] wire io_requestor_0_req_bits_signed = 1'h0; // @[Arbiter.scala:7:7, :9:14] wire io_requestor_0_s2_kill = 1'h0; // @[Arbiter.scala:7:7, :9:14] wire io_requestor_0_keep_clock_enabled = 1'h0; // @[Arbiter.scala:7:7, :9:14] wire io_requestor_0_perf_tlbMiss = 1'h0; // @[Arbiter.scala:7:7, :9:14] wire io_requestor_0_perf_blocked = 1'h0; // @[Arbiter.scala:7:7, :9:14] wire io_requestor_0_perf_canAcceptStoreThenLoad = 1'h0; // @[Arbiter.scala:7:7, :9:14] wire io_requestor_0_perf_canAcceptStoreThenRMW = 1'h0; // @[Arbiter.scala:7:7, :9:14] wire io_requestor_0_perf_canAcceptLoadThenLoad = 1'h0; // @[Arbiter.scala:7:7, :9:14] wire io_requestor_0_perf_storeBufferEmptyAfterLoad = 1'h0; // @[Arbiter.scala:7:7, :9:14] wire io_requestor_0_perf_storeBufferEmptyAfterStore = 1'h0; // @[Arbiter.scala:7:7, :9:14] wire io_requestor_1_perf_tlbMiss = 1'h0; // @[Arbiter.scala:7:7, :9:14] wire io_requestor_1_perf_blocked = 1'h0; // @[Arbiter.scala:7:7, :9:14] wire io_requestor_1_perf_canAcceptStoreThenLoad = 1'h0; // @[Arbiter.scala:7:7, :9:14] wire io_requestor_1_perf_canAcceptStoreThenRMW = 1'h0; // @[Arbiter.scala:7:7, :9:14] wire io_requestor_1_perf_canAcceptLoadThenLoad = 1'h0; // @[Arbiter.scala:7:7, :9:14] wire io_requestor_1_perf_storeBufferEmptyAfterLoad = 1'h0; // @[Arbiter.scala:7:7, :9:14] wire io_requestor_1_perf_storeBufferEmptyAfterStore = 1'h0; // @[Arbiter.scala:7:7, :9:14] wire io_mem_perf_tlbMiss = 1'h0; // @[Arbiter.scala:7:7, :9:14] wire io_mem_perf_blocked = 1'h0; // @[Arbiter.scala:7:7, :9:14] wire io_mem_perf_canAcceptStoreThenLoad = 1'h0; // @[Arbiter.scala:7:7, :9:14] wire io_mem_perf_canAcceptStoreThenRMW = 1'h0; // @[Arbiter.scala:7:7, :9:14] wire io_mem_perf_canAcceptLoadThenLoad = 1'h0; // @[Arbiter.scala:7:7, :9:14] wire io_mem_perf_storeBufferEmptyAfterLoad = 1'h0; // @[Arbiter.scala:7:7, :9:14] wire io_mem_perf_storeBufferEmptyAfterStore = 1'h0; // @[Arbiter.scala:7:7, :9:14] wire [1:0] io_requestor_0_req_bits_size = 2'h3; // @[Arbiter.scala:7:7, :9:14] wire [4:0] io_requestor_0_req_bits_cmd = 5'h0; // @[Arbiter.scala:7:7, :9:14] wire [6:0] io_requestor_0_req_bits_tag = 7'h0; // @[Arbiter.scala:7:7, :9:14, :31:29] wire _io_requestor_0_s2_nack_T_1; // @[Arbiter.scala:62:49] wire _io_requestor_0_resp_valid_T; // @[Arbiter.scala:58:39] wire _io_requestor_0_s2_hit_T_1; // @[Arbiter.scala:64:47] wire _io_requestor_1_req_ready_T_1; // @[Arbiter.scala:25:64] wire _io_requestor_1_s2_nack_T_1; // @[Arbiter.scala:62:49] wire _io_requestor_1_resp_valid_T; // @[Arbiter.scala:58:39] wire _io_requestor_1_s2_hit_T_1; // @[Arbiter.scala:64:47] wire io_requestor_0_req_ready_0 = io_mem_req_ready_0; // @[Arbiter.scala:7:7] wire _io_mem_req_valid_T; // @[Arbiter.scala:22:63] wire io_requestor_0_resp_bits_has_data_0 = io_mem_resp_bits_has_data_0; // @[Arbiter.scala:7:7] wire io_requestor_1_resp_bits_has_data_0 = io_mem_resp_bits_has_data_0; // @[Arbiter.scala:7:7] wire [63:0] io_requestor_0_resp_bits_data_0 = io_mem_resp_bits_data_0; // @[Arbiter.scala:7:7] wire [63:0] io_requestor_1_resp_bits_data_0 = io_mem_resp_bits_data_0; // @[Arbiter.scala:7:7] wire [1:0] io_requestor_0_resp_bits_size_0 = io_mem_resp_bits_size_0; // @[Arbiter.scala:7:7] wire [1:0] io_requestor_1_resp_bits_size_0 = io_mem_resp_bits_size_0; // @[Arbiter.scala:7:7] wire io_requestor_0_ordered_0 = io_mem_ordered_0; // @[Arbiter.scala:7:7] wire io_requestor_1_ordered_0 = io_mem_ordered_0; // @[Arbiter.scala:7:7] wire io_requestor_0_store_pending_0 = io_mem_store_pending_0; // @[Arbiter.scala:7:7] wire io_requestor_1_store_pending_0 = io_mem_store_pending_0; // @[Arbiter.scala:7:7] wire io_requestor_0_perf_acquire_0 = io_mem_perf_acquire_0; // @[Arbiter.scala:7:7] wire io_requestor_1_perf_acquire_0 = io_mem_perf_acquire_0; // @[Arbiter.scala:7:7] wire io_requestor_0_perf_release_0 = io_mem_perf_release_0; // @[Arbiter.scala:7:7] wire io_requestor_1_perf_release_0 = io_mem_perf_release_0; // @[Arbiter.scala:7:7] wire io_requestor_0_perf_grant_0 = io_mem_perf_grant_0; // @[Arbiter.scala:7:7] wire io_requestor_1_perf_grant_0 = io_mem_perf_grant_0; // @[Arbiter.scala:7:7] wire [6:0] io_requestor_0_resp_bits_tag_0; // @[Arbiter.scala:7:7] wire io_requestor_0_resp_valid_0; // @[Arbiter.scala:7:7] wire io_requestor_0_s2_nack_0; // @[Arbiter.scala:7:7] wire io_requestor_0_s2_hit_0; // @[Arbiter.scala:7:7] wire io_requestor_1_req_ready_0; // @[Arbiter.scala:7:7] wire [6:0] io_requestor_1_resp_bits_tag_0; // @[Arbiter.scala:7:7] wire io_requestor_1_resp_valid_0; // @[Arbiter.scala:7:7] wire io_requestor_1_s2_nack_0; // @[Arbiter.scala:7:7] wire io_requestor_1_s2_hit_0; // @[Arbiter.scala:7:7] wire [39:0] io_mem_req_bits_addr_0; // @[Arbiter.scala:7:7] wire [6:0] io_mem_req_bits_tag_0; // @[Arbiter.scala:7:7] wire [4:0] io_mem_req_bits_cmd_0; // @[Arbiter.scala:7:7] wire [1:0] io_mem_req_bits_size_0; // @[Arbiter.scala:7:7] wire io_mem_req_bits_signed_0; // @[Arbiter.scala:7:7] wire io_mem_req_valid_0; // @[Arbiter.scala:7:7] wire [63:0] io_mem_s1_data_data_0; // @[Arbiter.scala:7:7] wire [31:0] io_mem_s1_paddr_0; // @[Arbiter.scala:7:7] wire io_mem_s1_kill_0; // @[Arbiter.scala:7:7] wire io_mem_s2_kill_0; // @[Arbiter.scala:7:7] reg s1_id; // @[Arbiter.scala:17:20] reg s2_id; // @[Arbiter.scala:18:24] wire _io_requestor_1_s2_nack_T = s2_id; // @[Arbiter.scala:18:24, :62:58] wire _io_requestor_1_s2_hit_T = s2_id; // @[Arbiter.scala:18:24, :64:56] assign _io_mem_req_valid_T = io_requestor_0_req_valid_0 \| io_requestor_1_req_valid_0; // @[Arbiter.scala:7:7, :22:63] assign io_mem_req_valid_0 = _io_mem_req_valid_T; // @[Arbiter.scala:7:7, :22:63] wire _io_requestor_1_req_ready_T = ~io_requestor_0_req_valid_0; // @[Arbiter.scala:7:7, :25:67] assign _io_requestor_1_req_ready_T_1 = io_requestor_0_req_ready_0 & _io_requestor_1_req_ready_T; // @[Arbiter.scala:7:7, :25:{64,67}] assign io_requestor_1_req_ready_0 = _io_requestor_1_req_ready_T_1; // @[Arbiter.scala:7:7, :25:64] wire [7:0] _io_mem_req_bits_tag_T = {io_requestor_1_req_bits_tag_0, 1'h1}; // @[Arbiter.scala:7:7, :31:35] assign io_mem_req_bits_addr_0 = io_requestor_0_req_valid_0 ? io_requestor_0_req_bits_addr_0 : io_requestor_1_req_bits_addr_0; // @[Arbiter.scala:7:7, :30:25, :48:26] assign io_mem_req_bits_cmd_0 = io_requestor_0_req_valid_0 ? 5'h0 : io_requestor_1_req_bits_cmd_0; // @[Arbiter.scala:7:7, :9:14, :30:25, :48:26] assign io_mem_req_bits_size_0 = io_requestor_0_req_valid_0 ? 2'h3 : io_requestor_1_req_bits_size_0; // @[Arbiter.scala:7:7, :9:14, :30:25, :48:26] assign io_mem_req_bits_signed_0 = ~io_requestor_0_req_valid_0 & io_requestor_1_req_bits_signed_0; // @[Arbiter.scala:7:7, :30:25, :48:26] assign io_mem_req_bits_tag_0 = io_requestor_0_req_valid_0 ? 7'h0 : _io_mem_req_bits_tag_T[6:0]; // @[Arbiter.scala:7:7, :9:14, :31:{29,35}, :48:26] assign io_mem_s1_paddr_0 = s1_id ? io_requestor_1_s1_paddr_0 : io_requestor_0_s1_paddr_0; // @[Arbiter.scala:7:7, :17:20, :35:25, :49:30] assign io_mem_s1_kill_0 = s1_id ? io_requestor_1_s1_kill_0 : io_requestor_0_s1_kill_0; // @[Arbiter.scala:7:7, :17:20, :36:24, :49:30] assign io_mem_s1_data_data_0 = s1_id ? io_requestor_1_s1_data_data_0 : 64'h0; // @[Arbiter.scala:7:7, :9:14, :17:20, :30:25, :37:24, :48:26, :49:30] assign io_mem_s2_kill_0 = s2_id & io_requestor_1_s2_kill_0; // @[Arbiter.scala:7:7, :18:24, :40:24, :50:30] wire _tag_hit_T = io_mem_resp_bits_tag_0[0]; // @[Arbiter.scala:7:7, :57:41] wire _tag_hit_T_1 = io_mem_resp_bits_tag_0[0]; // @[Arbiter.scala:7:7, :57:41] wire tag_hit = ~_tag_hit_T; // @[Arbiter.scala:57:{41,57}] assign _io_requestor_0_resp_valid_T = io_mem_resp_valid_0 & tag_hit; // @[Arbiter.scala:7:7, :57:57, :58:39] assign io_requestor_0_resp_valid_0 = _io_requestor_0_resp_valid_T; // @[Arbiter.scala:7:7, :58:39] wire _io_requestor_0_s2_nack_T = ~s2_id; // @[Arbiter.scala:18:24, :50:21, :62:58] assign _io_requestor_0_s2_nack_T_1 = io_mem_s2_nack_0 & _io_requestor_0_s2_nack_T; // @[Arbiter.scala:7:7, :62:{49,58}] assign io_requestor_0_s2_nack_0 = _io_requestor_0_s2_nack_T_1; // @[Arbiter.scala:7:7, :62:49] wire _io_requestor_0_s2_hit_T = ~s2_id; // @[Arbiter.scala:18:24, :50:21, :64:56] assign _io_requestor_0_s2_hit_T_1 = io_mem_s2_hit_0 & _io_requestor_0_s2_hit_T; // @[Arbiter.scala:7:7, :64:{47,56}] assign io_requestor_0_s2_hit_0 = _io_requestor_0_s2_hit_T_1; // @[Arbiter.scala:7:7, :64:47] wire [5:0] _io_requestor_0_resp_bits_tag_T = io_mem_resp_bits_tag_0[6:1]; // @[Arbiter.scala:7:7, :66:45] wire [5:0] _io_requestor_1_resp_bits_tag_T = io_mem_resp_bits_tag_0[6:1]; // @[Arbiter.scala:7:7, :66:45] assign io_requestor_0_resp_bits_tag_0 = {1'h0, _io_requestor_0_resp_bits_tag_T}; // @[Arbiter.scala:7:7, :9:14, :66:{21,45}] wire tag_hit_1 = _tag_hit_T_1; // @[Arbiter.scala:57:{41,57}] assign _io_requestor_1_resp_valid_T = io_mem_resp_valid_0 & tag_hit_1; // @[Arbiter.scala:7:7, :57:57, :58:39] assign io_requestor_1_resp_valid_0 = _io_requestor_1_resp_valid_T; // @[Arbiter.scala:7:7, :58:39] assign _io_requestor_1_s2_nack_T_1 = io_mem_s2_nack_0 & _io_requestor_1_s2_nack_T; // @[Arbiter.scala:7:7, :62:{49,58}] assign io_requestor_1_s2_nack_0 = _io_requestor_1_s2_nack_T_1; // @[Arbiter.scala:7:7, :62:49] assign _io_requestor_1_s2_hit_T_1 = io_mem_s2_hit_0 & _io_requestor_1_s2_hit_T; // @[Arbiter.scala:7:7, :64:{47,56}] assign io_requestor_1_s2_hit_0 = _io_requestor_1_s2_hit_T_1; // @[Arbiter.scala:7:7, :64:47] assign io_requestor_1_resp_bits_tag_0 = {1'h0, _io_requestor_1_resp_bits_tag_T}; // @[Arbiter.scala:7:7, :9:14, :66:{21,45}] always @(posedge clock) begin // @[Arbiter.scala:7:7] s1_id <= ~io_requestor_0_req_valid_0; // @[Arbiter.scala:7:7, :17:20, :25:67] s2_id <= s1_id; // @[Arbiter.scala:17:20, :18:24] always @(posedge) assign io_requestor_0_req_ready = io_requestor_0_req_ready_0; // @[Arbiter.scala:7:7] assign io_requestor_0_s2_nack = io_requestor_0_s2_nack_0; // @[Arbiter.scala:7:7] assign io_requestor_0_resp_valid = io_requestor_0_resp_valid_0; // @[Arbiter.scala:7:7] assign io_requestor_0_resp_bits_has_data = io_requestor_0_resp_bits_has_data_0; // @[Arbiter.scala:7:7] assign io_requestor_0_resp_bits_tag = io_requestor_0_resp_bits_tag_0; // @[Arbiter.scala:7:7] assign io_requestor_0_resp_bits_data = io_requestor_0_resp_bits_data_0; // @[Arbiter.scala:7:7] assign io_requestor_0_resp_bits_size = io_requestor_0_resp_bits_size_0; // @[Arbiter.scala:7:7] assign io_requestor_0_s2_hit = io_requestor_0_s2_hit_0; // @[Arbiter.scala:7:7] assign io_requestor_0_ordered = io_requestor_0_ordered_0; // @[Arbiter.scala:7:7] assign io_requestor_0_store_pending = io_requestor_0_store_pending_0; // @[Arbiter.scala:7:7] assign io_requestor_0_perf_acquire = io_requestor_0_perf_acquire_0; // @[Arbiter.scala:7:7] assign io_requestor_0_perf_release = io_requestor_0_perf_release_0; // @[Arbiter.scala:7:7] assign io_requestor_0_perf_grant = io_requestor_0_perf_grant_0; // @[Arbiter.scala:7:7] assign io_requestor_1_req_ready = io_requestor_1_req_ready_0; // @[Arbiter.scala:7:7] assign io_requestor_1_s2_nack = io_requestor_1_s2_nack_0; // @[Arbiter.scala:7:7] assign io_requestor_1_resp_valid = io_requestor_1_resp_valid_0; // @[Arbiter.scala:7:7] assign io_requestor_1_resp_bits_has_data = io_requestor_1_resp_bits_has_data_0; // @[Arbiter.scala:7:7] assign io_requestor_1_resp_bits_tag = io_requestor_1_resp_bits_tag_0; // @[Arbiter.scala:7:7] assign io_requestor_1_resp_bits_data = io_requestor_1_resp_bits_data_0; // @[Arbiter.scala:7:7] assign io_requestor_1_resp_bits_size = io_requestor_1_resp_bits_size_0; // @[Arbiter.scala:7:7] assign io_requestor_1_s2_hit = io_requestor_1_s2_hit_0; // @[Arbiter.scala:7:7] assign io_requestor_1_ordered = io_requestor_1_ordered_0; // @[Arbiter.scala:7:7] assign io_requestor_1_store_pending = io_requestor_1_store_pending_0; // @[Arbiter.scala:7:7] assign io_requestor_1_perf_acquire = io_requestor_1_perf_acquire_0; // @[Arbiter.scala:7:7] assign io_requestor_1_perf_release = io_requestor_1_perf_release_0; // @[Arbiter.scala:7:7] assign io_requestor_1_perf_grant = io_requestor_1_perf_grant_0; // @[Arbiter.scala:7:7] assign io_mem_req_valid = io_mem_req_valid_0; // @[Arbiter.scala:7:7] assign io_mem_req_bits_addr = io_mem_req_bits_addr_0; // @[Arbiter.scala:7:7] assign io_mem_req_bits_tag = io_mem_req_bits_tag_0; // @[Arbiter.scala:7:7] assign io_mem_req_bits_cmd = io_mem_req_bits_cmd_0; // @[Arbiter.scala:7:7] assign io_mem_req_bits_size = io_mem_req_bits_size_0; // @[Arbiter.scala:7:7] assign io_mem_req_bits_signed = io_mem_req_bits_signed_0; // @[Arbiter.scala:7:7] assign io_mem_s1_paddr = io_mem_s1_paddr_0; // @[Arbiter.scala:7:7] assign io_mem_s1_kill = io_mem_s1_kill_0; // @[Arbiter.scala:7:7] assign io_mem_s1_data_data = io_mem_s1_data_data_0; // @[Arbiter.scala:7:7] assign io_mem_s2_kill = io_mem_s2_kill_0; // @[Arbiter.scala:7:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Buffer.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.BufferParams class TLBufferNode ( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit valName: ValName) extends TLAdapterNode( clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) }, managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) } ) { override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}" override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none) } class TLBuffer( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters) extends LazyModule { def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace) def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde) def this()(implicit p: Parameters) = this(BufferParams.default) val node = new TLBufferNode(a, b, c, d, e) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def headBundle = node.out.head._2.bundle override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.a <> a(in .a) in .d <> d(out.d) if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) { in .b <> b(out.b) out.c <> c(in .c) out.e <> e(in .e) } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLBuffer { def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default) def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde) def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace) def apply( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters): TLNode = { val buffer = LazyModule(new TLBuffer(a, b, c, d, e)) buffer.node } def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = { val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) } name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } } buffers.map(_.node) } def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = { chain(depth, name) .reduceLeftOption(_ := _) .getOrElse(TLNameNode("no_buffer")) } } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black /, label = (ei.manager.beatBytes 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red /, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" / green /) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" / yellow /, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /* Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } }	module TLBuffer_a28d64s4k1z3u( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [27:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [27:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [3:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [27:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [3:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9] wire auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9] wire [27:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [27:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9] wire [3:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9] wire [27:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_d_ready_0; // @[Buffer.scala:40:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9] TLMonitor_50 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a28d64s4k1z3u nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_a_valid), .io_deq_bits_opcode (nodeOut_a_bits_opcode), .io_deq_bits_param (nodeOut_a_bits_param), .io_deq_bits_size (nodeOut_a_bits_size), .io_deq_bits_source (nodeOut_a_bits_source), .io_deq_bits_address (nodeOut_a_bits_address), .io_deq_bits_mask (nodeOut_a_bits_mask), .io_deq_bits_data (nodeOut_a_bits_data), .io_deq_bits_corrupt (nodeOut_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a28d64s4k1z3u nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_d_ready), .io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black /, label = (ei.manager.beatBytes 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red /, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" / green /) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" / yellow /, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /* Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Arbiter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ object TLArbiter { // (valids, select) => readys type Policy = (Integer, UInt, Bool) => UInt val lowestIndexFirst: Policy = (width, valids, select) => ~(leftOR(valids) << 1)(width-1, 0) val highestIndexFirst: Policy = (width, valids, select) => ~((rightOR(valids) >> 1).pad(width)) val roundRobin: Policy = (width, valids, select) => if (width == 1) 1.U(1.W) else { val valid = valids(width-1, 0) assert (valid === valids) val mask = RegInit(((BigInt(1) << width)-1).U(width-1,0)) val filter = Cat(valid & ~mask, valid) val unready = (rightOR(filter, width2, width) >> 1) \| (mask << width) val readys = ~((unready >> width) & unready(width-1, 0)) when (select && valid.orR) { mask := leftOR(readys & valid, width) } readys(width-1, 0) } def lowestFromSeq[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: Seq[DecoupledIO[T]]): Unit = { apply(lowestIndexFirst)(sink, sources.map(s => (edge.numBeats1(s.bits), s)):_) } def lowest[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]): Unit = { apply(lowestIndexFirst)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_) } def highest[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]): Unit = { apply(highestIndexFirst)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_) } def robin[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]): Unit = { apply(roundRobin)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_) } def apply[T <: Data](policy: Policy)(sink: DecoupledIO[T], sources: (UInt, DecoupledIO[T])): Unit = { if (sources.isEmpty) { sink.bits := DontCare } else if (sources.size == 1) { sink :<>= sources.head._2 } else { val pairs = sources.toList val beatsIn = pairs.map(_._1) val sourcesIn = pairs.map(_._2) // The number of beats which remain to be sent val beatsLeft = RegInit(0.U) val idle = beatsLeft === 0.U val latch = idle && sink.ready // winner (if any) claims sink // Who wants access to the sink? val valids = sourcesIn.map(_.valid) // Arbitrate amongst the requests val readys = VecInit(policy(valids.size, Cat(valids.reverse), latch).asBools) // Which request wins arbitration? val winner = VecInit((readys zip valids) map { case (r,v) => r&&v }) // Confirm the policy works properly require (readys.size == valids.size) // Never two winners val prefixOR = winner.scanLeft(false.B)(_\|\|_).init assert((prefixOR zip winner) map { case (p,w) => !p \|\| !w } reduce {_ && _}) // If there was any request, there is a winner assert (!valids.reduce(_\|\|_) \|\| winner.reduce(_\|\|_)) // Track remaining beats val maskedBeats = (winner zip beatsIn) map { case (w,b) => Mux(w, b, 0.U) } val initBeats = maskedBeats.reduce(_ \| _) // no winner => 0 beats beatsLeft := Mux(latch, initBeats, beatsLeft - sink.fire) // The one-hot source granted access in the previous cycle val state = RegInit(VecInit(Seq.fill(sources.size)(false.B))) val muxState = Mux(idle, winner, state) state := muxState val allowed = Mux(idle, readys, state) (sourcesIn zip allowed) foreach { case (s, r) => s.ready := sink.ready && r } sink.valid := Mux(idle, valids.reduce(_\|\|_), Mux1H(state, valids)) sink.bits :<= Mux1H(muxState, sourcesIn.map(_.bits)) } } } // Synthesizable unit tests import freechips.rocketchip.unittest._ abstract class DecoupledArbiterTest( policy: TLArbiter.Policy, txns: Int, timeout: Int, val numSources: Int, beatsLeftFromIdx: Int => UInt) (implicit p: Parameters) extends UnitTest(timeout) { val sources = Wire(Vec(numSources, DecoupledIO(UInt(log2Ceil(numSources).W)))) dontTouch(sources.suggestName("sources")) val sink = Wire(DecoupledIO(UInt(log2Ceil(numSources).W))) dontTouch(sink.suggestName("sink")) val count = RegInit(0.U(log2Ceil(txns).W)) val lfsr = LFSR(16, true.B) sources.zipWithIndex.map { case (z, i) => z.bits := i.U } TLArbiter(policy)(sink, sources.zipWithIndex.map { case (z, i) => (beatsLeftFromIdx(i), z) }:_) count := count + 1.U io.finished := count >= txns.U } /* This tests that when a specific pattern of source valids are driven, * a new index from amongst that pattern is always selected, * unless one of those sources takes multiple beats, * in which case the same index should be selected until the arbiter goes idle. / class TLDecoupledArbiterRobinTest(txns: Int = 128, timeout: Int = 500000, print: Boolean = false) (implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.roundRobin, txns, timeout, 6, i => i.U) { val lastWinner = RegInit((numSources+1).U) val beatsLeft = RegInit(0.U(log2Ceil(numSources).W)) val first = lastWinner > numSources.U val valid = lfsr(0) val ready = lfsr(15) sink.ready := ready sources.zipWithIndex.map { // pattern: every even-indexed valid is driven the same random way case (s, i) => s.valid := (if (i % 2 == 1) false.B else valid) } when (sink.fire) { if (print) { printf("TestRobin: %d\n", sink.bits) } when (beatsLeft === 0.U) { assert(lastWinner =/= sink.bits, "Round robin did not pick a new idx despite one being valid.") lastWinner := sink.bits beatsLeft := sink.bits } .otherwise { assert(lastWinner === sink.bits, "Round robin did not pick the same index over multiple beats") beatsLeft := beatsLeft - 1.U } } if (print) { when (!sink.fire) { printf("TestRobin: idle (%d %d)\n", valid, ready) } } } /* This tests that the lowest index is always selected across random single cycle transactions. / class TLDecoupledArbiterLowestTest(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.lowestIndexFirst, txns, timeout, 15, _ => 0.U) { def assertLowest(id: Int): Unit = { when (sources(id).valid) { assert((numSources-1 until id by -1).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a higher valid source was granted ready.") } } sources.zipWithIndex.map { case (s, i) => s.valid := lfsr(i) } sink.ready := lfsr(15) when (sink.fire) { (0 until numSources).foreach(assertLowest(_)) } } /* This tests that the highest index is always selected across random single cycle transactions. / class TLDecoupledArbiterHighestTest(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.highestIndexFirst, txns, timeout, 15, _ => 0.U) { def assertHighest(id: Int): Unit = { when (sources(id).valid) { assert((0 until id).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a lower valid source was granted ready.") } } sources.zipWithIndex.map { case (s, i) => s.valid := lfsr(i) } sink.ready := lfsr(15) when (sink.fire) { (0 until numSources).foreach(assertHighest(_)) } } File Xbar.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressDecoder, AddressSet, RegionType, IdRange, TriStateValue} import freechips.rocketchip.util.BundleField // Trades off slave port proximity against routing resource cost object ForceFanout { def apply[T]( a: TriStateValue = TriStateValue.unset, b: TriStateValue = TriStateValue.unset, c: TriStateValue = TriStateValue.unset, d: TriStateValue = TriStateValue.unset, e: TriStateValue = TriStateValue.unset)(body: Parameters => T)(implicit p: Parameters) = { body(p.alterPartial { case ForceFanoutKey => p(ForceFanoutKey) match { case ForceFanoutParams(pa, pb, pc, pd, pe) => ForceFanoutParams(a.update(pa), b.update(pb), c.update(pc), d.update(pd), e.update(pe)) } }) } } private case class ForceFanoutParams(a: Boolean, b: Boolean, c: Boolean, d: Boolean, e: Boolean) private case object ForceFanoutKey extends Field(ForceFanoutParams(false, false, false, false, false)) class TLXbar(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule { val node = new TLNexusNode( clientFn = { seq => seq(0).v1copy( echoFields = BundleField.union(seq.flatMap(_.echoFields)), requestFields = BundleField.union(seq.flatMap(_.requestFields)), responseKeys = seq.flatMap(_.responseKeys).distinct, minLatency = seq.map(_.minLatency).min, clients = (TLXbar.mapInputIds(seq) zip seq) flatMap { case (range, port) => port.clients map { client => client.v1copy( sourceId = client.sourceId.shift(range.start) )} } ) }, managerFn = { seq => val fifoIdFactory = TLXbar.relabeler() seq(0).v1copy( responseFields = BundleField.union(seq.flatMap(_.responseFields)), requestKeys = seq.flatMap(_.requestKeys).distinct, minLatency = seq.map(_.minLatency).min, endSinkId = TLXbar.mapOutputIds(seq).map(_.end).max, managers = seq.flatMap { port => require (port.beatBytes == seq(0).beatBytes, s"Xbar ($name with parent $parent) data widths don't match: ${port.managers.map(_.name)} has ${port.beatBytes}B vs ${seq(0).managers.map(_.name)} has ${seq(0).beatBytes}B") val fifoIdMapper = fifoIdFactory() port.managers map { manager => manager.v1copy( fifoId = manager.fifoId.map(fifoIdMapper(_)) )} } ) } ){ override def circuitIdentity = outputs.size == 1 && inputs.size == 1 } lazy val module = new Impl class Impl extends LazyModuleImp(this) { if ((node.in.size node.out.size) > (832)) { println (s"!!! WARNING !!!") println (s" Your TLXbar ($name with parent $parent) is very large, with ${node.in.size} Masters and ${node.out.size} Slaves.") println (s"!!! WARNING !!!") } val wide_bundle = TLBundleParameters.union((node.in ++ node.out).map(_._2.bundle)) override def desiredName = (Seq("TLXbar") ++ nameSuffix ++ Seq(s"i${node.in.size}_o${node.out.size}_${wide_bundle.shortName}")).mkString("_") TLXbar.circuit(policy, node.in, node.out) } } object TLXbar { def mapInputIds(ports: Seq[TLMasterPortParameters]) = assignRanges(ports.map(_.endSourceId)) def mapOutputIds(ports: Seq[TLSlavePortParameters]) = assignRanges(ports.map(_.endSinkId)) def assignRanges(sizes: Seq[Int]) = { val pow2Sizes = sizes.map { z => if (z == 0) 0 else 1 << log2Ceil(z) } val tuples = pow2Sizes.zipWithIndex.sortBy(_._1) // record old index, then sort by increasing size val starts = tuples.scanRight(0)(_._1 + _).tail // suffix-sum of the sizes = the start positions val ranges = (tuples zip starts) map { case ((sz, i), st) => (if (sz == 0) IdRange(0, 0) else IdRange(st, st + sz), i) } ranges.sortBy(_._2).map(_._1) // Restore orignal order } def relabeler() = { var idFactory = 0 () => { val fifoMap = scala.collection.mutable.HashMap.empty[Int, Int] (x: Int) => { if (fifoMap.contains(x)) fifoMap(x) else { val out = idFactory idFactory = idFactory + 1 fifoMap += (x -> out) out } } } } def circuit(policy: TLArbiter.Policy, seqIn: Seq[(TLBundle, TLEdge)], seqOut: Seq[(TLBundle, TLEdge)]) { val (io_in, edgesIn) = seqIn.unzip val (io_out, edgesOut) = seqOut.unzip // Not every master need connect to every slave on every channel; determine which connections are necessary val reachableIO = edgesIn.map { cp => edgesOut.map { mp => cp.client.clients.exists { c => mp.manager.managers.exists { m => c.visibility.exists { ca => m.address.exists { ma => ca.overlaps(ma)}}}} }.toVector}.toVector val probeIO = (edgesIn zip reachableIO).map { case (cp, reachableO) => (edgesOut zip reachableO).map { case (mp, reachable) => reachable && cp.client.anySupportProbe && mp.manager.managers.exists(_.regionType >= RegionType.TRACKED) }.toVector}.toVector val releaseIO = (edgesIn zip reachableIO).map { case (cp, reachableO) => (edgesOut zip reachableO).map { case (mp, reachable) => reachable && cp.client.anySupportProbe && mp.manager.anySupportAcquireB }.toVector}.toVector val connectAIO = reachableIO val connectBIO = probeIO val connectCIO = releaseIO val connectDIO = reachableIO val connectEIO = releaseIO def transpose[T](x: Seq[Seq[T]]) = if (x.isEmpty) Nil else Vector.tabulate(x(0).size) { i => Vector.tabulate(x.size) { j => x(j)(i) } } val connectAOI = transpose(connectAIO) val connectBOI = transpose(connectBIO) val connectCOI = transpose(connectCIO) val connectDOI = transpose(connectDIO) val connectEOI = transpose(connectEIO) // Grab the port ID mapping val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client)) val outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager)) // We need an intermediate size of bundle with the widest possible identifiers val wide_bundle = TLBundleParameters.union(io_in.map(_.params) ++ io_out.map(_.params)) // Handle size = 1 gracefully (Chisel3 empty range is broken) def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0) // Transform input bundle sources (sinks use global namespace on both sides) val in = Wire(Vec(io_in.size, TLBundle(wide_bundle))) for (i <- 0 until in.size) { val r = inputIdRanges(i) if (connectAIO(i).exists(x=>x)) { in(i).a.bits.user := DontCare in(i).a.squeezeAll.waiveAll :<>= io_in(i).a.squeezeAll.waiveAll in(i).a.bits.source := io_in(i).a.bits.source \| r.start.U } else { in(i).a := DontCare io_in(i).a := DontCare in(i).a.valid := false.B io_in(i).a.ready := true.B } if (connectBIO(i).exists(x=>x)) { io_in(i).b.squeezeAll :<>= in(i).b.squeezeAll io_in(i).b.bits.source := trim(in(i).b.bits.source, r.size) } else { in(i).b := DontCare io_in(i).b := DontCare in(i).b.ready := true.B io_in(i).b.valid := false.B } if (connectCIO(i).exists(x=>x)) { in(i).c.bits.user := DontCare in(i).c.squeezeAll.waiveAll :<>= io_in(i).c.squeezeAll.waiveAll in(i).c.bits.source := io_in(i).c.bits.source \| r.start.U } else { in(i).c := DontCare io_in(i).c := DontCare in(i).c.valid := false.B io_in(i).c.ready := true.B } if (connectDIO(i).exists(x=>x)) { io_in(i).d.squeezeAll.waiveAll :<>= in(i).d.squeezeAll.waiveAll io_in(i).d.bits.source := trim(in(i).d.bits.source, r.size) } else { in(i).d := DontCare io_in(i).d := DontCare in(i).d.ready := true.B io_in(i).d.valid := false.B } if (connectEIO(i).exists(x=>x)) { in(i).e.squeezeAll :<>= io_in(i).e.squeezeAll } else { in(i).e := DontCare io_in(i).e := DontCare in(i).e.valid := false.B io_in(i).e.ready := true.B } } // Transform output bundle sinks (sources use global namespace on both sides) val out = Wire(Vec(io_out.size, TLBundle(wide_bundle))) for (o <- 0 until out.size) { val r = outputIdRanges(o) if (connectAOI(o).exists(x=>x)) { out(o).a.bits.user := DontCare io_out(o).a.squeezeAll.waiveAll :<>= out(o).a.squeezeAll.waiveAll } else { out(o).a := DontCare io_out(o).a := DontCare out(o).a.ready := true.B io_out(o).a.valid := false.B } if (connectBOI(o).exists(x=>x)) { out(o).b.squeezeAll :<>= io_out(o).b.squeezeAll } else { out(o).b := DontCare io_out(o).b := DontCare out(o).b.valid := false.B io_out(o).b.ready := true.B } if (connectCOI(o).exists(x=>x)) { out(o).c.bits.user := DontCare io_out(o).c.squeezeAll.waiveAll :<>= out(o).c.squeezeAll.waiveAll } else { out(o).c := DontCare io_out(o).c := DontCare out(o).c.ready := true.B io_out(o).c.valid := false.B } if (connectDOI(o).exists(x=>x)) { out(o).d.squeezeAll :<>= io_out(o).d.squeezeAll out(o).d.bits.sink := io_out(o).d.bits.sink \| r.start.U } else { out(o).d := DontCare io_out(o).d := DontCare out(o).d.valid := false.B io_out(o).d.ready := true.B } if (connectEOI(o).exists(x=>x)) { io_out(o).e.squeezeAll :<>= out(o).e.squeezeAll io_out(o).e.bits.sink := trim(out(o).e.bits.sink, r.size) } else { out(o).e := DontCare io_out(o).e := DontCare out(o).e.ready := true.B io_out(o).e.valid := false.B } } // Filter a list to only those elements selected def filter[T](data: Seq[T], mask: Seq[Boolean]) = (data zip mask).filter(_._2).map(_._1) // Based on input=>output connectivity, create per-input minimal address decode circuits val requiredAC = (connectAIO ++ connectCIO).distinct val outputPortFns: Map[Vector[Boolean], Seq[UInt => Bool]] = requiredAC.map { connectO => val port_addrs = edgesOut.map(_.manager.managers.flatMap(_.address)) val routingMask = AddressDecoder(filter(port_addrs, connectO)) val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct)) // Print the address mapping if (false) { println("Xbar mapping:") route_addrs.foreach { p => print(" ") p.foreach { a => print(s" ${a}") } println("") } println("--") } (connectO, route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_ \|\| _))) }.toMap // Print the ID mapping if (false) { println(s"XBar mapping:") (edgesIn zip inputIdRanges).zipWithIndex.foreach { case ((edge, id), i) => println(s"\t$i assigned ${id} for ${edge.client.clients.map(_.name).mkString(", ")}") } println("") } val addressA = (in zip edgesIn) map { case (i, e) => e.address(i.a.bits) } val addressC = (in zip edgesIn) map { case (i, e) => e.address(i.c.bits) } def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B val requestAIO = (connectAIO zip addressA) map { case (c, i) => outputPortFns(c).map { o => unique(c) \|\| o(i) } } val requestCIO = (connectCIO zip addressC) map { case (c, i) => outputPortFns(c).map { o => unique(c) \|\| o(i) } } val requestBOI = out.map { o => inputIdRanges.map { i => i.contains(o.b.bits.source) } } val requestDOI = out.map { o => inputIdRanges.map { i => i.contains(o.d.bits.source) } } val requestEIO = in.map { i => outputIdRanges.map { o => o.contains(i.e.bits.sink) } } val beatsAI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.a.bits) } val beatsBO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.b.bits) } val beatsCI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.c.bits) } val beatsDO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.d.bits) } val beatsEI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.e.bits) } // Fanout the input sources to the output sinks val portsAOI = transpose((in zip requestAIO) map { case (i, r) => TLXbar.fanout(i.a, r, edgesOut.map(_.params(ForceFanoutKey).a)) }) val portsBIO = transpose((out zip requestBOI) map { case (o, r) => TLXbar.fanout(o.b, r, edgesIn .map(_.params(ForceFanoutKey).b)) }) val portsCOI = transpose((in zip requestCIO) map { case (i, r) => TLXbar.fanout(i.c, r, edgesOut.map(_.params(ForceFanoutKey).c)) }) val portsDIO = transpose((out zip requestDOI) map { case (o, r) => TLXbar.fanout(o.d, r, edgesIn .map(_.params(ForceFanoutKey).d)) }) val portsEOI = transpose((in zip requestEIO) map { case (i, r) => TLXbar.fanout(i.e, r, edgesOut.map(_.params(ForceFanoutKey).e)) }) // Arbitrate amongst the sources for (o <- 0 until out.size) { TLArbiter(policy)(out(o).a, filter(beatsAI zip portsAOI(o), connectAOI(o)):_) TLArbiter(policy)(out(o).c, filter(beatsCI zip portsCOI(o), connectCOI(o)):_) TLArbiter(policy)(out(o).e, filter(beatsEI zip portsEOI(o), connectEOI(o)):_) filter(portsAOI(o), connectAOI(o).map(!_)) foreach { r => r.ready := false.B } filter(portsCOI(o), connectCOI(o).map(!_)) foreach { r => r.ready := false.B } filter(portsEOI(o), connectEOI(o).map(!_)) foreach { r => r.ready := false.B } } for (i <- 0 until in.size) { TLArbiter(policy)(in(i).b, filter(beatsBO zip portsBIO(i), connectBIO(i)):_) TLArbiter(policy)(in(i).d, filter(beatsDO zip portsDIO(i), connectDIO(i)):_) filter(portsBIO(i), connectBIO(i).map(!_)) foreach { r => r.ready := false.B } filter(portsDIO(i), connectDIO(i).map(!_)) foreach { r => r.ready := false.B } } } def apply(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode = { val xbar = LazyModule(new TLXbar(policy, nameSuffix)) xbar.node } // Replicate an input port to each output port def fanout[T <: TLChannel](input: DecoupledIO[T], select: Seq[Bool], force: Seq[Boolean] = Nil): Seq[DecoupledIO[T]] = { val filtered = Wire(Vec(select.size, chiselTypeOf(input))) for (i <- 0 until select.size) { filtered(i).bits := (if (force.lift(i).getOrElse(false)) IdentityModule(input.bits) else input.bits) filtered(i).valid := input.valid && (select(i) \|\| (select.size == 1).B) } input.ready := Mux1H(select, filtered.map(_.ready)) filtered } } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMXbar(nManagers: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("Xbar")) val xbar = LazyModule(new TLXbar) xbar.node := TLDelayer(0.1) := model.node := fuzz.node (0 until nManagers) foreach { n => val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400n, 0x3ff))) ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node } lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMXbarTest(nManagers: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMXbar(nManagers,txns)).module) dut.io.start := io.start io.finished := dut.io.finished } class TLMulticlientXbar(nManagers: Int, nClients: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val xbar = LazyModule(new TLXbar) val fuzzers = (0 until nClients) map { n => val fuzz = LazyModule(new TLFuzzer(txns)) xbar.node := TLDelayer(0.1) := fuzz.node fuzz } (0 until nManagers) foreach { n => val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400n, 0x3ff))) ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node } lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzzers.last.module.io.finished } } class TLMulticlientXbarTest(nManagers: Int, nClients: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLMulticlientXbar(nManagers, nClients, txns)).module) dut.io.start := io.start io.finished := dut.io.finished }	module TLXbar_i1_o2_a14d64s11k1z2u_1( // @[Xbar.scala:74:9] input clock, // @[Xbar.scala:74:9] input reset, // @[Xbar.scala:74:9] output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [13:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_out_1_a_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_anon_out_1_a_bits_source, // @[LazyModuleImp.scala:107:25] output [13:0] auto_anon_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_anon_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_0_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_out_0_a_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_anon_out_0_a_bits_source, // @[LazyModuleImp.scala:107:25] output [13:0] auto_anon_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_anon_out_0_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_0_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire _portsAOI_in_0_a_ready_T_2 = ~(auto_anon_in_a_bits_address[8]) & auto_anon_out_0_a_ready \| auto_anon_in_a_bits_address[8] & auto_anon_out_1_a_ready; // @[Mux.scala:30:73] reg beatsLeft; // @[Arbiter.scala:60:30] wire [1:0] readys_valid = {auto_anon_out_1_d_valid, auto_anon_out_0_d_valid}; // @[Arbiter.scala:68:51] reg [1:0] readys_mask; // @[Arbiter.scala:23:23] wire [1:0] _readys_filter_T_1 = readys_valid & ~readys_mask; // @[Arbiter.scala:23:23, :24:{28,30}, :68:51] wire [1:0] readys_readys = ~({readys_mask[1], _readys_filter_T_1[1] \| readys_mask[0]} & ({_readys_filter_T_1[0], auto_anon_out_1_d_valid} \| _readys_filter_T_1)); // @[package.scala:262:43] wire winner_0 = readys_readys[0] & auto_anon_out_0_d_valid; // @[Arbiter.scala:26:18, :68:76, :71:69] wire winner_1 = readys_readys[1] & auto_anon_out_1_d_valid; // @[Arbiter.scala:26:18, :68:76, :71:69] wire _in_0_d_valid_T = auto_anon_out_0_d_valid \| auto_anon_out_1_d_valid; // @[Arbiter.scala:79:31]

Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }

module AsyncResetSynchronizerShiftReg_w1_d3_i0_138( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_238 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module TLMonitor_42( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [2:0] io_in_b_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_b_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_b_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_b_bits_data, // @[Monitor.scala:20:14] input io_in_b_bits_corrupt, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input [63:0] io_in_c_bits_data, // @[Monitor.scala:20:14] input io_in_c_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_ready, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7] wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_b_bits_opcode_0 = io_in_b_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_b_bits_size_0 = io_in_b_bits_size; // @[Monitor.scala:36:7] wire [1:0] io_in_b_bits_source_0 = io_in_b_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_b_bits_mask_0 = io_in_b_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_b_bits_data_0 = io_in_b_bits_data; // @[Monitor.scala:36:7] wire io_in_b_bits_corrupt_0 = io_in_b_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7] wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7] wire [1:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7] wire [63:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7] wire io_in_c_bits_corrupt_0 = io_in_c_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_e_ready_0 = io_in_e_ready; // @[Monitor.scala:36:7] wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [8:0] b_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] b_first_count = 9'h0; // @[Edges.scala:234:25] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire sink_ok_1 = 1'h1; // @[Monitor.scala:367:31] wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire b_first_last = 1'h1; // @[Edges.scala:232:33] wire _legal_source_T_3 = 1'h0; // @[Mux.scala:30:73] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [3:0] _mask_sizeOH_T_3 = io_in_b_bits_size_0; // @[Misc.scala:202:34] wire [31:0] _address_ok_T = io_in_b_bits_address_0; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_70 = io_in_c_bits_address_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 2'h0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire _source_ok_T_1 = io_in_a_bits_source_0 == 2'h1; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1 = _source_ok_T_1; // @[Parameters.scala:1138:31] wire _source_ok_T_2 = io_in_a_bits_source_0 == 2'h2; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2 = _source_ok_T_2; // @[Parameters.scala:1138:31] wire _source_ok_T_3 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_3 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire _source_ok_T_4 = io_in_d_bits_source_0 == 2'h0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_4; // @[Parameters.scala:1138:31] wire _source_ok_T_5 = io_in_d_bits_source_0 == 2'h1; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_1 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire _source_ok_T_6 = io_in_d_bits_source_0 == 2'h2; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_2 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire _source_ok_T_7 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_7 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _legal_source_T = io_in_b_bits_source_0 == 2'h0; // @[Monitor.scala:36:7] wire _legal_source_T_1 = io_in_b_bits_source_0 == 2'h1; // @[Monitor.scala:36:7] wire _legal_source_T_2 = io_in_b_bits_source_0 == 2'h2; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46] wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_5 = {io_in_b_bits_address_0[31:13], io_in_b_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46] wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1 = _address_ok_T_9; // @[Parameters.scala:612:40] wire [13:0] _GEN_0 = io_in_b_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_10 = {io_in_b_bits_address_0[31:14], _GEN_0}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46] wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_2 = _address_ok_T_14; // @[Parameters.scala:612:40] wire [16:0] _GEN_1 = io_in_b_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_15 = {io_in_b_bits_address_0[31:17], _GEN_1}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46] wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_3 = _address_ok_T_19; // @[Parameters.scala:612:40] wire [20:0] _GEN_2 = io_in_b_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_20 = {io_in_b_bits_address_0[31:21], _GEN_2}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_21 = {1'h0, _address_ok_T_20}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_22 = _address_ok_T_21 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_23 = _address_ok_T_22; // @[Parameters.scala:137:46] wire _address_ok_T_24 = _address_ok_T_23 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_4 = _address_ok_T_24; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_25 = {io_in_b_bits_address_0[31:21], io_in_b_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_26 = {1'h0, _address_ok_T_25}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_27 = _address_ok_T_26 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_28 = _address_ok_T_27; // @[Parameters.scala:137:46] wire _address_ok_T_29 = _address_ok_T_28 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_5 = _address_ok_T_29; // @[Parameters.scala:612:40] wire [25:0] _GEN_3 = io_in_b_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_30 = {io_in_b_bits_address_0[31:26], _GEN_3}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_31 = {1'h0, _address_ok_T_30}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_32 = _address_ok_T_31 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_33 = _address_ok_T_32; // @[Parameters.scala:137:46] wire _address_ok_T_34 = _address_ok_T_33 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_6 = _address_ok_T_34; // @[Parameters.scala:612:40] wire [25:0] _GEN_4 = io_in_b_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_35 = {io_in_b_bits_address_0[31:26], _GEN_4}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_36 = {1'h0, _address_ok_T_35}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_37 = _address_ok_T_36 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_38 = _address_ok_T_37; // @[Parameters.scala:137:46] wire _address_ok_T_39 = _address_ok_T_38 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_7 = _address_ok_T_39; // @[Parameters.scala:612:40] wire [27:0] _GEN_5 = io_in_b_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_40 = {io_in_b_bits_address_0[31:28], _GEN_5}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_41 = {1'h0, _address_ok_T_40}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_42 = _address_ok_T_41 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_43 = _address_ok_T_42; // @[Parameters.scala:137:46] wire _address_ok_T_44 = _address_ok_T_43 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_8 = _address_ok_T_44; // @[Parameters.scala:612:40] wire [27:0] _GEN_6 = io_in_b_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_45 = {io_in_b_bits_address_0[31:28], _GEN_6}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_46 = {1'h0, _address_ok_T_45}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_47 = _address_ok_T_46 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_48 = _address_ok_T_47; // @[Parameters.scala:137:46] wire _address_ok_T_49 = _address_ok_T_48 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_9 = _address_ok_T_49; // @[Parameters.scala:612:40] wire [28:0] _GEN_7 = io_in_b_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_50 = {io_in_b_bits_address_0[31:29], _GEN_7}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_51 = {1'h0, _address_ok_T_50}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_52 = _address_ok_T_51 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_53 = _address_ok_T_52; // @[Parameters.scala:137:46] wire _address_ok_T_54 = _address_ok_T_53 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_10 = _address_ok_T_54; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_55 = io_in_b_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_56 = {1'h0, _address_ok_T_55}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_57 = _address_ok_T_56 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_58 = _address_ok_T_57; // @[Parameters.scala:137:46] wire _address_ok_T_59 = _address_ok_T_58 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_11 = _address_ok_T_59; // @[Parameters.scala:612:40] wire _address_ok_T_60 = _address_ok_WIRE_0 | _address_ok_WIRE_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_61 = _address_ok_T_60 | _address_ok_WIRE_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_62 = _address_ok_T_61 | _address_ok_WIRE_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_63 = _address_ok_T_62 | _address_ok_WIRE_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_64 = _address_ok_T_63 | _address_ok_WIRE_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_65 = _address_ok_T_64 | _address_ok_WIRE_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_66 = _address_ok_T_65 | _address_ok_WIRE_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_67 = _address_ok_T_66 | _address_ok_WIRE_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_68 = _address_ok_T_67 | _address_ok_WIRE_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_69 = _address_ok_T_68 | _address_ok_WIRE_10; // @[Parameters.scala:612:40, :636:64] wire address_ok = _address_ok_T_69 | _address_ok_WIRE_11; // @[Parameters.scala:612:40, :636:64] wire [26:0] _GEN_8 = 27'hFFF << io_in_b_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_2; // @[package.scala:243:71] assign _is_aligned_mask_T_2 = _GEN_8; // @[package.scala:243:71] wire [26:0] _b_first_beats1_decode_T; // @[package.scala:243:71] assign _b_first_beats1_decode_T = _GEN_8; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_3 = _is_aligned_mask_T_2[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_1 = ~_is_aligned_mask_T_3; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_1 = {20'h0, io_in_b_bits_address_0[11:0] & is_aligned_mask_1}; // @[package.scala:243:46] wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount_1 = _mask_sizeOH_T_3[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_4 = 4'h1 << mask_sizeOH_shiftAmount_1; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_5 = _mask_sizeOH_T_4[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH_1 = {_mask_sizeOH_T_5[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1_1 = io_in_b_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size_1 = mask_sizeOH_1[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2_1 = mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2_1 = mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size_1 & mask_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1_1 = mask_sub_sub_sub_0_1_1 | _mask_sub_sub_acc_T_2; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size_1 & mask_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1_1 = mask_sub_sub_sub_0_1_1 | _mask_sub_sub_acc_T_3; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size_1 = mask_sizeOH_1[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_4 = mask_sub_size_1 & mask_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1_1 = mask_sub_sub_0_1_1 | _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_5 = mask_sub_size_1 & mask_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1_1 = mask_sub_sub_0_1_1 | _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_6 = mask_sub_size_1 & mask_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1_1 = mask_sub_sub_1_1_1 | _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_7 = mask_sub_size_1 & mask_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1_1 = mask_sub_sub_1_1_1 | _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_size_1 = mask_sizeOH_1[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_eq_8 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_size_1 & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_8 = mask_sub_0_1_1 | _mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_eq_9 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_size_1 & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_9 = mask_sub_0_1_1 | _mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_eq_10 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_size_1 & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_10 = mask_sub_1_1_1 | _mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_eq_11 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_size_1 & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_11 = mask_sub_1_1_1 | _mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_eq_12 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_size_1 & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_12 = mask_sub_2_1_1 | _mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_eq_13 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_size_1 & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_13 = mask_sub_2_1_1 | _mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_eq_14 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_size_1 & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_14 = mask_sub_3_1_1 | _mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_eq_15 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_size_1 & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_15 = mask_sub_3_1_1 | _mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo_1 = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_1 = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_1 = {mask_lo_hi_1, mask_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_1 = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_1 = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_1 = {mask_hi_hi_1, mask_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] mask_1 = {mask_hi_1, mask_lo_1}; // @[Misc.scala:222:10] wire _legal_source_WIRE_0 = _legal_source_T; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_1 = _legal_source_T_1; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_2 = _legal_source_T_2; // @[Parameters.scala:1138:31] wire _legal_source_T_4 = _legal_source_WIRE_1; // @[Mux.scala:30:73] wire _legal_source_T_6 = _legal_source_T_4; // @[Mux.scala:30:73] wire [1:0] _legal_source_T_5 = {_legal_source_WIRE_2, 1'h0}; // @[Mux.scala:30:73] wire [1:0] _legal_source_T_7 = {1'h0, _legal_source_T_6} | _legal_source_T_5; // @[Mux.scala:30:73] wire [1:0] _legal_source_WIRE_1_0 = _legal_source_T_7; // @[Mux.scala:30:73] wire legal_source = _legal_source_WIRE_1_0 == io_in_b_bits_source_0; // @[Mux.scala:30:73] wire _source_ok_T_8 = io_in_c_bits_source_0 == 2'h0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_0 = _source_ok_T_8; // @[Parameters.scala:1138:31] wire _source_ok_T_9 = io_in_c_bits_source_0 == 2'h1; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_1 = _source_ok_T_9; // @[Parameters.scala:1138:31] wire _source_ok_T_10 = io_in_c_bits_source_0 == 2'h2; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_2 = _source_ok_T_10; // @[Parameters.scala:1138:31] wire _source_ok_T_11 = _source_ok_WIRE_2_0 | _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_2 = _source_ok_T_11 | _source_ok_WIRE_2_2; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN_9 = 27'hFFF << io_in_c_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_4; // @[package.scala:243:71] assign _is_aligned_mask_T_4 = _GEN_9; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T; // @[package.scala:243:71] assign _c_first_beats1_decode_T = _GEN_9; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71] assign _c_first_beats1_decode_T_3 = _GEN_9; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_2 = {20'h0, io_in_c_bits_address_0[11:0] & is_aligned_mask_2}; // @[package.scala:243:46] wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}] wire [32:0] _address_ok_T_71 = {1'h0, _address_ok_T_70}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_72 = _address_ok_T_71 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_73 = _address_ok_T_72; // @[Parameters.scala:137:46] wire _address_ok_T_74 = _address_ok_T_73 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_0 = _address_ok_T_74; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_75 = {io_in_c_bits_address_0[31:13], io_in_c_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_76 = {1'h0, _address_ok_T_75}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_77 = _address_ok_T_76 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_78 = _address_ok_T_77; // @[Parameters.scala:137:46] wire _address_ok_T_79 = _address_ok_T_78 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_1 = _address_ok_T_79; // @[Parameters.scala:612:40] wire [13:0] _GEN_10 = io_in_c_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_80 = {io_in_c_bits_address_0[31:14], _GEN_10}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_81 = {1'h0, _address_ok_T_80}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_82 = _address_ok_T_81 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_83 = _address_ok_T_82; // @[Parameters.scala:137:46] wire _address_ok_T_84 = _address_ok_T_83 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_2 = _address_ok_T_84; // @[Parameters.scala:612:40] wire [16:0] _GEN_11 = io_in_c_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_85 = {io_in_c_bits_address_0[31:17], _GEN_11}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_86 = {1'h0, _address_ok_T_85}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_87 = _address_ok_T_86 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_88 = _address_ok_T_87; // @[Parameters.scala:137:46] wire _address_ok_T_89 = _address_ok_T_88 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_3 = _address_ok_T_89; // @[Parameters.scala:612:40] wire [20:0] _GEN_12 = io_in_c_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_90 = {io_in_c_bits_address_0[31:21], _GEN_12}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_91 = {1'h0, _address_ok_T_90}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_92 = _address_ok_T_91 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_93 = _address_ok_T_92; // @[Parameters.scala:137:46] wire _address_ok_T_94 = _address_ok_T_93 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_4 = _address_ok_T_94; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_95 = {io_in_c_bits_address_0[31:21], io_in_c_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_96 = {1'h0, _address_ok_T_95}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_97 = _address_ok_T_96 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_98 = _address_ok_T_97; // @[Parameters.scala:137:46] wire _address_ok_T_99 = _address_ok_T_98 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_5 = _address_ok_T_99; // @[Parameters.scala:612:40] wire [25:0] _GEN_13 = io_in_c_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_100 = {io_in_c_bits_address_0[31:26], _GEN_13}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_101 = {1'h0, _address_ok_T_100}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_102 = _address_ok_T_101 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_103 = _address_ok_T_102; // @[Parameters.scala:137:46] wire _address_ok_T_104 = _address_ok_T_103 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_6 = _address_ok_T_104; // @[Parameters.scala:612:40] wire [25:0] _GEN_14 = io_in_c_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_105 = {io_in_c_bits_address_0[31:26], _GEN_14}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_106 = {1'h0, _address_ok_T_105}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_107 = _address_ok_T_106 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_108 = _address_ok_T_107; // @[Parameters.scala:137:46] wire _address_ok_T_109 = _address_ok_T_108 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_7 = _address_ok_T_109; // @[Parameters.scala:612:40] wire [27:0] _GEN_15 = io_in_c_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_110 = {io_in_c_bits_address_0[31:28], _GEN_15}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_111 = {1'h0, _address_ok_T_110}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_112 = _address_ok_T_111 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_113 = _address_ok_T_112; // @[Parameters.scala:137:46] wire _address_ok_T_114 = _address_ok_T_113 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_8 = _address_ok_T_114; // @[Parameters.scala:612:40] wire [27:0] _GEN_16 = io_in_c_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_115 = {io_in_c_bits_address_0[31:28], _GEN_16}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_116 = {1'h0, _address_ok_T_115}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_117 = _address_ok_T_116 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_118 = _address_ok_T_117; // @[Parameters.scala:137:46] wire _address_ok_T_119 = _address_ok_T_118 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_9 = _address_ok_T_119; // @[Parameters.scala:612:40] wire [28:0] _GEN_17 = io_in_c_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_120 = {io_in_c_bits_address_0[31:29], _GEN_17}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_121 = {1'h0, _address_ok_T_120}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_122 = _address_ok_T_121 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_123 = _address_ok_T_122; // @[Parameters.scala:137:46] wire _address_ok_T_124 = _address_ok_T_123 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_10 = _address_ok_T_124; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_125 = io_in_c_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_126 = {1'h0, _address_ok_T_125}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_127 = _address_ok_T_126 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_128 = _address_ok_T_127; // @[Parameters.scala:137:46] wire _address_ok_T_129 = _address_ok_T_128 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_11 = _address_ok_T_129; // @[Parameters.scala:612:40] wire _address_ok_T_130 = _address_ok_WIRE_1_0 | _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_131 = _address_ok_T_130 | _address_ok_WIRE_1_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_132 = _address_ok_T_131 | _address_ok_WIRE_1_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_133 = _address_ok_T_132 | _address_ok_WIRE_1_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_134 = _address_ok_T_133 | _address_ok_WIRE_1_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_135 = _address_ok_T_134 | _address_ok_WIRE_1_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_136 = _address_ok_T_135 | _address_ok_WIRE_1_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_137 = _address_ok_T_136 | _address_ok_WIRE_1_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_138 = _address_ok_T_137 | _address_ok_WIRE_1_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_139 = _address_ok_T_138 | _address_ok_WIRE_1_10; // @[Parameters.scala:612:40, :636:64] wire address_ok_1 = _address_ok_T_139 | _address_ok_WIRE_1_11; // @[Parameters.scala:612:40, :636:64] wire _T_2451 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_2451; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_2451; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [1:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_2525 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_2525; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_2525; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_2525; // @[Decoupled.scala:51:35] wire _d_first_T_3; // @[Decoupled.scala:51:35] assign _d_first_T_3 = _T_2525; // @[Decoupled.scala:51:35] wire [26:0] _GEN_18 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71] assign _d_first_beats1_decode_T_9 = _GEN_18; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [1:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35] wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35] wire [11:0] _b_first_beats1_decode_T_1 = _b_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _b_first_beats1_decode_T_2 = ~_b_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] b_first_beats1_decode = _b_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _b_first_beats1_opdata_T = io_in_b_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire b_first_beats1_opdata = ~_b_first_beats1_opdata_T; // @[Edges.scala:97:{28,37}] reg [8:0] b_first_counter; // @[Edges.scala:229:27] wire [9:0] _b_first_counter1_T = {1'h0, b_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] b_first_counter1 = _b_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire b_first = b_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _b_first_last_T = b_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire [8:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] _b_first_counter_T = b_first ? 9'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_2; // @[Monitor.scala:410:22] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [3:0] size_2; // @[Monitor.scala:412:22] reg [1:0] source_2; // @[Monitor.scala:413:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _T_2522 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35] wire _c_first_T; // @[Decoupled.scala:51:35] assign _c_first_T = _T_2522; // @[Decoupled.scala:51:35] wire _c_first_T_1; // @[Decoupled.scala:51:35] assign _c_first_T_1 = _T_2522; // @[Decoupled.scala:51:35] wire [11:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [8:0] c_first_counter; // @[Edges.scala:229:27] wire [9:0] _c_first_counter1_T = {1'h0, c_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] c_first_counter1 = _c_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire c_first = c_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T = c_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_1 = c_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last = _c_first_last_T | _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35] wire [8:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [3:0] size_3; // @[Monitor.scala:517:22] reg [1:0] source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [2:0] inflight; // @[Monitor.scala:614:27] reg [11:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [23:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [2:0] a_set; // @[Monitor.scala:626:34] wire [2:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [11:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [23:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [4:0] _GEN_19 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [4:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_19; // @[Monitor.scala:637:69] wire [4:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_19; // @[Monitor.scala:637:69, :680:101] wire [4:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_19; // @[Monitor.scala:637:69, :749:69] wire [4:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_19; // @[Monitor.scala:637:69, :790:101] wire [11:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [15:0] _a_opcode_lookup_T_6 = {4'h0, _a_opcode_lookup_T_1 & 12'hF}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [4:0] _GEN_20 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [4:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_20; // @[Monitor.scala:641:65] wire [4:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_20; // @[Monitor.scala:641:65, :681:99] wire [4:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_20; // @[Monitor.scala:641:65, :750:67] wire [4:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_20; // @[Monitor.scala:641:65, :791:99] wire [23:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [23:0] _a_size_lookup_T_6 = {16'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [23:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[23:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [3:0] _GEN_21 = 4'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [3:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_21; // @[OneHot.scala:58:35] wire [3:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_21; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire _T_2377 = _T_2451 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_2377 ? _a_set_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_2377 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_2377 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [4:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [34:0] _a_opcodes_set_T_1 = {31'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_2377 ? _a_opcodes_set_T_1[11:0] : 12'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [4:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [35:0] _a_sizes_set_T_1 = {31'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_2377 ? _a_sizes_set_T_1[23:0] : 24'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [2:0] d_clr; // @[Monitor.scala:664:34] wire [2:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [11:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [23:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_22 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_22; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_22; // @[Monitor.scala:673:46, :783:46] wire _T_2423 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [3:0] _GEN_23 = 4'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [3:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_23; // @[OneHot.scala:58:35] wire [3:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_23; // @[OneHot.scala:58:35] wire [3:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_23; // @[OneHot.scala:58:35] wire [3:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_23; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_2423 & ~d_release_ack ? _d_clr_wo_ready_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire _T_2392 = _T_2525 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_2392 ? _d_clr_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire [46:0] _d_opcodes_clr_T_5 = 47'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_2392 ? _d_opcodes_clr_T_5[11:0] : 12'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [46:0] _d_sizes_clr_T_5 = 47'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_2392 ? _d_sizes_clr_T_5[23:0] : 24'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [2:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [2:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [2:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [11:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [11:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [11:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [23:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [23:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [23:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [2:0] inflight_1; // @[Monitor.scala:726:35] reg [11:0] inflight_opcodes_1; // @[Monitor.scala:727:35] reg [23:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [11:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [8:0] c_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] c_first_counter1_1 = _c_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire c_first_1 = c_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T_2 = c_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_3 = c_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last_1 = _c_first_last_T_2 | _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [2:0] c_set; // @[Monitor.scala:738:34] wire [2:0] c_set_wo_ready; // @[Monitor.scala:739:34] wire [11:0] c_opcodes_set; // @[Monitor.scala:740:34] wire [23:0] c_sizes_set; // @[Monitor.scala:741:34] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [11:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [15:0] _c_opcode_lookup_T_6 = {4'h0, _c_opcode_lookup_T_1 & 12'hF}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [23:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [23:0] _c_size_lookup_T_6 = {16'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [23:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[23:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40] wire [4:0] c_sizes_set_interm; // @[Monitor.scala:755:40] wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44] wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7] wire [3:0] _GEN_24 = 4'h1 << io_in_c_bits_source_0; // @[OneHot.scala:58:35] wire [3:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35] assign _c_set_wo_ready_T = _GEN_24; // @[OneHot.scala:58:35] wire [3:0] _c_set_T; // @[OneHot.scala:58:35] assign _c_set_T = _GEN_24; // @[OneHot.scala:58:35] assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire _T_2464 = _T_2522 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35] assign c_set = _T_2464 ? _c_set_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53] wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}] assign c_opcodes_set_interm = _T_2464 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}] wire [4:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51] wire [4:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:766:{51,59}] assign c_sizes_set_interm = _T_2464 ? _c_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}] wire [4:0] _c_opcodes_set_T = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79] wire [34:0] _c_opcodes_set_T_1 = {31'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:659:54, :754:40, :767:{54,79}] assign c_opcodes_set = _T_2464 ? _c_opcodes_set_T_1[11:0] : 12'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}] wire [4:0] _c_sizes_set_T = {io_in_c_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :768:77] wire [35:0] _c_sizes_set_T_1 = {31'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:659:54, :755:40, :768:{52,77}] assign c_sizes_set = _T_2464 ? _c_sizes_set_T_1[23:0] : 24'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}] wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47] wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95] wire c_probe_ack = _c_probe_ack_T | _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}] wire [2:0] d_clr_1; // @[Monitor.scala:774:34] wire [2:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [11:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [23:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_2495 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_2495 & d_release_ack_1 ? _d_clr_wo_ready_T_1[2:0] : 3'h0; // @[OneHot.scala:58:35] wire _T_2477 = _T_2525 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_2477 ? _d_clr_T_1[2:0] : 3'h0; // @[OneHot.scala:58:35] wire [46:0] _d_opcodes_clr_T_11 = 47'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_2477 ? _d_opcodes_clr_T_11[11:0] : 12'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [46:0] _d_sizes_clr_T_11 = 47'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_2477 ? _d_sizes_clr_T_11[23:0] : 24'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}] wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}] wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}] wire [2:0] _inflight_T_3 = inflight_1 | c_set; // @[Monitor.scala:726:35, :738:34, :814:35] wire [2:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [2:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [11:0] _inflight_opcodes_T_3 = inflight_opcodes_1 | c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43] wire [11:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [11:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [23:0] _inflight_sizes_T_3 = inflight_sizes_1 | c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41] wire [23:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [23:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26] wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26] reg [7:0] inflight_2; // @[Monitor.scala:828:27] wire [11:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_3; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_3 = _d_first_counter1_T_3[8:0]; // @[Edges.scala:230:28] wire d_first_3 = d_first_counter_3 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_6 = d_first_counter_3 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_7 = d_first_beats1_3 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_3 = _d_first_last_T_6 | _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}] wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [7:0] d_set; // @[Monitor.scala:833:25] wire _T_2531 = _T_2525 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35] wire [7:0] _GEN_25 = {5'h0, io_in_d_bits_sink_0}; // @[OneHot.scala:58:35] wire [7:0] _d_set_T = 8'h1 << _GEN_25; // @[OneHot.scala:58:35] assign d_set = _T_2531 ? _d_set_T : 8'h0; // @[OneHot.scala:58:35] wire [7:0] e_clr; // @[Monitor.scala:839:25] wire _T_2540 = io_in_e_ready_0 & io_in_e_valid_0; // @[Decoupled.scala:51:35] wire [7:0] _GEN_26 = {5'h0, io_in_e_bits_sink_0}; // @[OneHot.scala:58:35] wire [7:0] _e_clr_T = 8'h1 << _GEN_26; // @[OneHot.scala:58:35] assign e_clr = _T_2540 ? _e_clr_T : 8'h0; // @[OneHot.scala:58:35]

Generate the Verilog code corresponding to the following Chisel files. File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File RocketCore.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import chisel3.withClock import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.tile._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property import scala.collection.mutable.ArrayBuffer case class RocketCoreParams( xLen: Int = 64, pgLevels: Int = 3, // sv39 default bootFreqHz: BigInt = 0, useVM: Boolean = true, useUser: Boolean = false, useSupervisor: Boolean = false, useHypervisor: Boolean = false, useDebug: Boolean = true, useAtomics: Boolean = true, useAtomicsOnlyForIO: Boolean = false, useCompressed: Boolean = true, useRVE: Boolean = false, useConditionalZero: Boolean = false, useZba: Boolean = false, useZbb: Boolean = false, useZbs: Boolean = false, nLocalInterrupts: Int = 0, useNMI: Boolean = false, nBreakpoints: Int = 1, useBPWatch: Boolean = false, mcontextWidth: Int = 0, scontextWidth: Int = 0, nPMPs: Int = 8, nPerfCounters: Int = 0, haveBasicCounters: Boolean = true, haveCFlush: Boolean = false, misaWritable: Boolean = true, nL2TLBEntries: Int = 0, nL2TLBWays: Int = 1, nPTECacheEntries: Int = 8, mtvecInit: Option[BigInt] = Some(BigInt(0)), mtvecWritable: Boolean = true, fastLoadWord: Boolean = true, fastLoadByte: Boolean = false, branchPredictionModeCSR: Boolean = false, clockGate: Boolean = false, mvendorid: Int = 0, // 0 means non-commercial implementation mimpid: Int = 0x20181004, // release date in BCD mulDiv: Option[MulDivParams] = Some(MulDivParams()), fpu: Option[FPUParams] = Some(FPUParams()), debugROB: Option[DebugROBParams] = None, // if size < 1, SW ROB, else HW ROB haveCease: Boolean = true, // non-standard CEASE instruction haveSimTimeout: Boolean = true, // add plusarg for simulation timeout vector: Option[RocketCoreVectorParams] = None ) extends CoreParams { val lgPauseCycles = 5 val haveFSDirty = false val pmpGranularity: Int = if (useHypervisor) 4096 else 4 val fetchWidth: Int = if (useCompressed) 2 else 1 // fetchWidth doubled, but coreInstBytes halved, for RVC: val decodeWidth: Int = fetchWidth / (if (useCompressed) 2 else 1) val retireWidth: Int = 1 val instBits: Int = if (useCompressed) 16 else 32 val lrscCycles: Int = 80 // worst case is 14 mispredicted branches + slop val traceHasWdata: Boolean = debugROB.isDefined // ooo wb, so no wdata in trace override val useVector = vector.isDefined override val vectorUseDCache = vector.map(_.useDCache).getOrElse(false) override def vLen = vector.map(_.vLen).getOrElse(0) override def eLen = vector.map(_.eLen).getOrElse(0) override def vfLen = vector.map(_.vfLen).getOrElse(0) override def vfh = vector.map(_.vfh).getOrElse(false) override def vExts = vector.map(_.vExts).getOrElse(Nil) override def vMemDataBits = vector.map(_.vMemDataBits).getOrElse(0) override val customIsaExt = Option.when(haveCease)("xrocket") // CEASE instruction override def minFLen: Int = fpu.map(_.minFLen).getOrElse(32) override def customCSRs(implicit p: Parameters) = new RocketCustomCSRs } trait HasRocketCoreParameters extends HasCoreParameters { lazy val rocketParams: RocketCoreParams = tileParams.core.asInstanceOf[RocketCoreParams] val fastLoadWord = rocketParams.fastLoadWord val fastLoadByte = rocketParams.fastLoadByte val mulDivParams = rocketParams.mulDiv.getOrElse(MulDivParams()) // TODO ask andrew about this require(!fastLoadByte || fastLoadWord) require(!rocketParams.haveFSDirty, "rocket doesn't support setting fs dirty from outside, please disable haveFSDirty") } class RocketCustomCSRs(implicit p: Parameters) extends CustomCSRs with HasRocketCoreParameters { override def bpmCSR = { rocketParams.branchPredictionModeCSR.option(CustomCSR(bpmCSRId, BigInt(1), Some(BigInt(0)))) } private def haveDCache = tileParams.dcache.get.scratch.isEmpty override def chickenCSR = { val mask = BigInt( tileParams.dcache.get.clockGate.toInt << 0 | rocketParams.clockGate.toInt << 1 | rocketParams.clockGate.toInt << 2 | 1 << 3 | // disableSpeculativeICacheRefill haveDCache.toInt << 9 | // suppressCorruptOnGrantData tileParams.icache.get.prefetch.toInt << 17 ) Some(CustomCSR(chickenCSRId, mask, Some(mask))) } def disableICachePrefetch = getOrElse(chickenCSR, _.value(17), true.B) def marchid = CustomCSR.constant(CSRs.marchid, BigInt(1)) def mvendorid = CustomCSR.constant(CSRs.mvendorid, BigInt(rocketParams.mvendorid)) // mimpid encodes a release version in the form of a BCD-encoded datestamp. def mimpid = CustomCSR.constant(CSRs.mimpid, BigInt(rocketParams.mimpid)) override def decls = super.decls :+ marchid :+ mvendorid :+ mimpid } class CoreInterrupts(val hasBeu: Boolean)(implicit p: Parameters) extends TileInterrupts()(p) { val buserror = Option.when(hasBeu)(Bool()) } trait HasRocketCoreIO extends HasRocketCoreParameters { implicit val p: Parameters def nTotalRoCCCSRs: Int val io = IO(new CoreBundle()(p) { val hartid = Input(UInt(hartIdLen.W)) val reset_vector = Input(UInt(resetVectorLen.W)) val interrupts = Input(new CoreInterrupts(tileParams.asInstanceOf[RocketTileParams].beuAddr.isDefined)) val imem = new FrontendIO val dmem = new HellaCacheIO val ptw = Flipped(new DatapathPTWIO()) val fpu = Flipped(new FPUCoreIO()) val rocc = Flipped(new RoCCCoreIO(nTotalRoCCCSRs)) val trace = Output(new TraceBundle) val bpwatch = Output(Vec(coreParams.nBreakpoints, new BPWatch(coreParams.retireWidth))) val cease = Output(Bool()) val wfi = Output(Bool()) val traceStall = Input(Bool()) val vector = if (usingVector) Some(Flipped(new VectorCoreIO)) else None }) } class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p) with HasRocketCoreParameters with HasRocketCoreIO { def nTotalRoCCCSRs = tile.roccCSRs.flatten.size import ALU._ val clock_en_reg = RegInit(true.B) val long_latency_stall = Reg(Bool()) val id_reg_pause = Reg(Bool()) val imem_might_request_reg = Reg(Bool()) val clock_en = WireDefault(true.B) val gated_clock = if (!rocketParams.clockGate) clock else ClockGate(clock, clock_en, "rocket_clock_gate") class RocketImpl { // entering gated-clock domain // performance counters def pipelineIDToWB[T <: Data](x: T): T = RegEnable(RegEnable(RegEnable(x, !ctrl_killd), ex_pc_valid), mem_pc_valid) val perfEvents = new EventSets(Seq( new EventSet((mask, hits) => Mux(wb_xcpt, mask(0), wb_valid && pipelineIDToWB((mask & hits).orR)), Seq( ("exception", () => false.B), ("load", () => id_ctrl.mem && id_ctrl.mem_cmd === M_XRD && !id_ctrl.fp), ("store", () => id_ctrl.mem && id_ctrl.mem_cmd === M_XWR && !id_ctrl.fp), ("amo", () => usingAtomics.B && id_ctrl.mem && (isAMO(id_ctrl.mem_cmd) || id_ctrl.mem_cmd.isOneOf(M_XLR, M_XSC))), ("system", () => id_ctrl.csr =/= CSR.N), ("arith", () => id_ctrl.wxd && !(id_ctrl.jal || id_ctrl.jalr || id_ctrl.mem || id_ctrl.fp || id_ctrl.mul || id_ctrl.div || id_ctrl.csr =/= CSR.N)), ("branch", () => id_ctrl.branch), ("jal", () => id_ctrl.jal), ("jalr", () => id_ctrl.jalr)) ++ (if (!usingMulDiv) Seq() else Seq( ("mul", () => if (pipelinedMul) id_ctrl.mul else id_ctrl.div && (id_ctrl.alu_fn & FN_DIV) =/= FN_DIV), ("div", () => if (pipelinedMul) id_ctrl.div else id_ctrl.div && (id_ctrl.alu_fn & FN_DIV) === FN_DIV))) ++ (if (!usingFPU) Seq() else Seq( ("fp load", () => id_ctrl.fp && io.fpu.dec.ldst && io.fpu.dec.wen), ("fp store", () => id_ctrl.fp && io.fpu.dec.ldst && !io.fpu.dec.wen), ("fp add", () => id_ctrl.fp && io.fpu.dec.fma && io.fpu.dec.swap23), ("fp mul", () => id_ctrl.fp && io.fpu.dec.fma && !io.fpu.dec.swap23 && !io.fpu.dec.ren3), ("fp mul-add", () => id_ctrl.fp && io.fpu.dec.fma && io.fpu.dec.ren3), ("fp div/sqrt", () => id_ctrl.fp && (io.fpu.dec.div || io.fpu.dec.sqrt)), ("fp other", () => id_ctrl.fp && !(io.fpu.dec.ldst || io.fpu.dec.fma || io.fpu.dec.div || io.fpu.dec.sqrt))))), new EventSet((mask, hits) => (mask & hits).orR, Seq( ("load-use interlock", () => id_ex_hazard && ex_ctrl.mem || id_mem_hazard && mem_ctrl.mem || id_wb_hazard && wb_ctrl.mem), ("long-latency interlock", () => id_sboard_hazard), ("csr interlock", () => id_ex_hazard && ex_ctrl.csr =/= CSR.N || id_mem_hazard && mem_ctrl.csr =/= CSR.N || id_wb_hazard && wb_ctrl.csr =/= CSR.N), ("I$ blocked", () => icache_blocked), ("D$ blocked", () => id_ctrl.mem && dcache_blocked), ("branch misprediction", () => take_pc_mem && mem_direction_misprediction), ("control-flow target misprediction", () => take_pc_mem && mem_misprediction && mem_cfi && !mem_direction_misprediction && !icache_blocked), ("flush", () => wb_reg_flush_pipe), ("replay", () => replay_wb)) ++ (if (!usingMulDiv) Seq() else Seq( ("mul/div interlock", () => id_ex_hazard && (ex_ctrl.mul || ex_ctrl.div) || id_mem_hazard && (mem_ctrl.mul || mem_ctrl.div) || id_wb_hazard && wb_ctrl.div))) ++ (if (!usingFPU) Seq() else Seq( ("fp interlock", () => id_ex_hazard && ex_ctrl.fp || id_mem_hazard && mem_ctrl.fp || id_wb_hazard && wb_ctrl.fp || id_ctrl.fp && id_stall_fpu)))), new EventSet((mask, hits) => (mask & hits).orR, Seq( ("I$ miss", () => io.imem.perf.acquire), ("D$ miss", () => io.dmem.perf.acquire), ("D$ release", () => io.dmem.perf.release), ("ITLB miss", () => io.imem.perf.tlbMiss), ("DTLB miss", () => io.dmem.perf.tlbMiss), ("L2 TLB miss", () => io.ptw.perf.l2miss))))) val pipelinedMul = usingMulDiv && mulDivParams.mulUnroll == xLen val decode_table = { (if (usingMulDiv) new MDecode(pipelinedMul) +: (xLen > 32).option(new M64Decode(pipelinedMul)).toSeq else Nil) ++: (if (usingAtomics) new ADecode +: (xLen > 32).option(new A64Decode).toSeq else Nil) ++: (if (fLen >= 32) new FDecode +: (xLen > 32).option(new F64Decode).toSeq else Nil) ++: (if (fLen >= 64) new DDecode +: (xLen > 32).option(new D64Decode).toSeq else Nil) ++: (if (minFLen == 16) new HDecode +: (xLen > 32).option(new H64Decode).toSeq ++: (fLen >= 64).option(new HDDecode).toSeq else Nil) ++: (usingRoCC.option(new RoCCDecode)) ++: (if (xLen == 32) new I32Decode else new I64Decode) +: (usingVM.option(new SVMDecode)) ++: (usingSupervisor.option(new SDecode)) ++: (usingHypervisor.option(new HypervisorDecode)) ++: ((usingHypervisor && (xLen == 64)).option(new Hypervisor64Decode)) ++: (usingDebug.option(new DebugDecode)) ++: (usingNMI.option(new NMIDecode)) ++: (usingConditionalZero.option(new ConditionalZeroDecode)) ++: Seq(new FenceIDecode(tile.dcache.flushOnFenceI)) ++: coreParams.haveCFlush.option(new CFlushDecode(tile.dcache.canSupportCFlushLine)) ++: rocketParams.haveCease.option(new CeaseDecode) ++: usingVector.option(new VCFGDecode) ++: (if (coreParams.useZba) new ZbaDecode +: (xLen > 32).option(new Zba64Decode).toSeq else Nil) ++: (if (coreParams.useZbb) Seq(new ZbbDecode, if (xLen == 32) new Zbb32Decode else new Zbb64Decode) else Nil) ++: coreParams.useZbs.option(new ZbsDecode) ++: Seq(new IDecode) } flatMap(_.table) val ex_ctrl = Reg(new IntCtrlSigs) val mem_ctrl = Reg(new IntCtrlSigs) val wb_ctrl = Reg(new IntCtrlSigs) val ex_reg_xcpt_interrupt = Reg(Bool()) val ex_reg_valid = Reg(Bool()) val ex_reg_rvc = Reg(Bool()) val ex_reg_btb_resp = Reg(new BTBResp) val ex_reg_xcpt = Reg(Bool()) val ex_reg_flush_pipe = Reg(Bool()) val ex_reg_load_use = Reg(Bool()) val ex_reg_cause = Reg(UInt()) val ex_reg_replay = Reg(Bool()) val ex_reg_pc = Reg(UInt()) val ex_reg_mem_size = Reg(UInt()) val ex_reg_hls = Reg(Bool()) val ex_reg_inst = Reg(Bits()) val ex_reg_raw_inst = Reg(UInt()) val ex_reg_wphit = Reg(Vec(nBreakpoints, Bool())) val ex_reg_set_vconfig = Reg(Bool()) val mem_reg_xcpt_interrupt = Reg(Bool()) val mem_reg_valid = Reg(Bool()) val mem_reg_rvc = Reg(Bool()) val mem_reg_btb_resp = Reg(new BTBResp) val mem_reg_xcpt = Reg(Bool()) val mem_reg_replay = Reg(Bool()) val mem_reg_flush_pipe = Reg(Bool()) val mem_reg_cause = Reg(UInt()) val mem_reg_slow_bypass = Reg(Bool()) val mem_reg_load = Reg(Bool()) val mem_reg_store = Reg(Bool()) val mem_reg_set_vconfig = Reg(Bool()) val mem_reg_sfence = Reg(Bool()) val mem_reg_pc = Reg(UInt()) val mem_reg_inst = Reg(Bits()) val mem_reg_mem_size = Reg(UInt()) val mem_reg_hls_or_dv = Reg(Bool()) val mem_reg_raw_inst = Reg(UInt()) val mem_reg_wdata = Reg(Bits()) val mem_reg_rs2 = Reg(Bits()) val mem_br_taken = Reg(Bool()) val take_pc_mem = Wire(Bool()) val mem_reg_wphit = Reg(Vec(nBreakpoints, Bool())) val wb_reg_valid = Reg(Bool()) val wb_reg_xcpt = Reg(Bool()) val wb_reg_replay = Reg(Bool()) val wb_reg_flush_pipe = Reg(Bool()) val wb_reg_cause = Reg(UInt()) val wb_reg_set_vconfig = Reg(Bool()) val wb_reg_sfence = Reg(Bool()) val wb_reg_pc = Reg(UInt()) val wb_reg_mem_size = Reg(UInt()) val wb_reg_hls_or_dv = Reg(Bool()) val wb_reg_hfence_v = Reg(Bool()) val wb_reg_hfence_g = Reg(Bool()) val wb_reg_inst = Reg(Bits()) val wb_reg_raw_inst = Reg(UInt()) val wb_reg_wdata = Reg(Bits()) val wb_reg_rs2 = Reg(Bits()) val take_pc_wb = Wire(Bool()) val wb_reg_wphit = Reg(Vec(nBreakpoints, Bool())) val take_pc_mem_wb = take_pc_wb || take_pc_mem val take_pc = take_pc_mem_wb // decode stage val ibuf = Module(new IBuf) val id_expanded_inst = ibuf.io.inst.map(_.bits.inst) val id_raw_inst = ibuf.io.inst.map(_.bits.raw) val id_inst = id_expanded_inst.map(_.bits) ibuf.io.imem <> io.imem.resp ibuf.io.kill := take_pc require(decodeWidth == 1 /* TODO */ && retireWidth == decodeWidth) require(!(coreParams.useRVE && coreParams.fpu.nonEmpty), "Can't select both RVE and floating-point") require(!(coreParams.useRVE && coreParams.useHypervisor), "Can't select both RVE and Hypervisor") val id_ctrl = Wire(new IntCtrlSigs).decode(id_inst(0), decode_table) val lgNXRegs = if (coreParams.useRVE) 4 else 5 val regAddrMask = (1 << lgNXRegs) - 1 def decodeReg(x: UInt) = (x.extract(x.getWidth-1, lgNXRegs).asBool, x(lgNXRegs-1, 0)) val (id_raddr3_illegal, id_raddr3) = decodeReg(id_expanded_inst(0).rs3) val (id_raddr2_illegal, id_raddr2) = decodeReg(id_expanded_inst(0).rs2) val (id_raddr1_illegal, id_raddr1) = decodeReg(id_expanded_inst(0).rs1) val (id_waddr_illegal, id_waddr) = decodeReg(id_expanded_inst(0).rd) val id_load_use = Wire(Bool()) val id_reg_fence = RegInit(false.B) val id_ren = IndexedSeq(id_ctrl.rxs1, id_ctrl.rxs2) val id_raddr = IndexedSeq(id_raddr1, id_raddr2) val rf = new RegFile(regAddrMask, xLen) val id_rs = id_raddr.map(rf.read _) val ctrl_killd = Wire(Bool()) val id_npc = (ibuf.io.pc.asSInt + ImmGen(IMM_UJ, id_inst(0))).asUInt val csr = Module(new CSRFile(perfEvents, coreParams.customCSRs.decls, tile.roccCSRs.flatten, tile.rocketParams.beuAddr.isDefined)) val id_csr_en = id_ctrl.csr.isOneOf(CSR.S, CSR.C, CSR.W) val id_system_insn = id_ctrl.csr === CSR.I val id_csr_ren = id_ctrl.csr.isOneOf(CSR.S, CSR.C) && id_expanded_inst(0).rs1 === 0.U val id_csr = Mux(id_system_insn && id_ctrl.mem, CSR.N, Mux(id_csr_ren, CSR.R, id_ctrl.csr)) val id_csr_flush = id_system_insn || (id_csr_en && !id_csr_ren && csr.io.decode(0).write_flush) val id_set_vconfig = Seq(Instructions.VSETVLI, Instructions.VSETIVLI, Instructions.VSETVL).map(_ === id_inst(0)).orR && usingVector.B id_ctrl.vec := false.B if (usingVector) { val v_decode = rocketParams.vector.get.decoder(p) v_decode.io.inst := id_inst(0) v_decode.io.vconfig := csr.io.vector.get.vconfig when (v_decode.io.legal) { id_ctrl.legal := !csr.io.vector.get.vconfig.vtype.vill id_ctrl.fp := v_decode.io.fp id_ctrl.rocc := false.B id_ctrl.branch := false.B id_ctrl.jal := false.B id_ctrl.jalr := false.B id_ctrl.rxs2 := v_decode.io.read_rs2 id_ctrl.rxs1 := v_decode.io.read_rs1 id_ctrl.mem := false.B id_ctrl.rfs1 := v_decode.io.read_frs1 id_ctrl.rfs2 := false.B id_ctrl.rfs3 := false.B id_ctrl.wfd := v_decode.io.write_frd id_ctrl.mul := false.B id_ctrl.div := false.B id_ctrl.wxd := v_decode.io.write_rd id_ctrl.csr := CSR.N id_ctrl.fence_i := false.B id_ctrl.fence := false.B id_ctrl.amo := false.B id_ctrl.dp := false.B id_ctrl.vec := true.B } } val id_illegal_insn = !id_ctrl.legal || (id_ctrl.mul || id_ctrl.div) && !csr.io.status.isa('m'-'a') || id_ctrl.amo && !csr.io.status.isa('a'-'a') || id_ctrl.fp && (csr.io.decode(0).fp_illegal || (io.fpu.illegal_rm && !id_ctrl.vec)) || (id_ctrl.vec) && (csr.io.decode(0).vector_illegal || csr.io.vector.map(_.vconfig.vtype.vill).getOrElse(false.B)) || id_ctrl.dp && !csr.io.status.isa('d'-'a') || ibuf.io.inst(0).bits.rvc && !csr.io.status.isa('c'-'a') || id_raddr2_illegal && id_ctrl.rxs2 || id_raddr1_illegal && id_ctrl.rxs1 || id_waddr_illegal && id_ctrl.wxd || id_ctrl.rocc && csr.io.decode(0).rocc_illegal || id_csr_en && (csr.io.decode(0).read_illegal || !id_csr_ren && csr.io.decode(0).write_illegal) || !ibuf.io.inst(0).bits.rvc && (id_system_insn && csr.io.decode(0).system_illegal) val id_virtual_insn = id_ctrl.legal && ((id_csr_en && !(!id_csr_ren && csr.io.decode(0).write_illegal) && csr.io.decode(0).virtual_access_illegal) || (!ibuf.io.inst(0).bits.rvc && id_system_insn && csr.io.decode(0).virtual_system_illegal)) // stall decode for fences (now, for AMO.rl; later, for AMO.aq and FENCE) val id_amo_aq = id_inst(0)(26) val id_amo_rl = id_inst(0)(25) val id_fence_pred = id_inst(0)(27,24) val id_fence_succ = id_inst(0)(23,20) val id_fence_next = id_ctrl.fence || id_ctrl.amo && id_amo_aq val id_mem_busy = !io.dmem.ordered || io.dmem.req.valid when (!id_mem_busy) { id_reg_fence := false.B } val id_rocc_busy = usingRoCC.B && (io.rocc.busy || ex_reg_valid && ex_ctrl.rocc || mem_reg_valid && mem_ctrl.rocc || wb_reg_valid && wb_ctrl.rocc) val id_csr_rocc_write = tile.roccCSRs.flatten.map(_.id.U === id_inst(0)(31,20)).orR && id_csr_en && !id_csr_ren val id_vec_busy = io.vector.map(v => v.backend_busy || v.trap_check_busy).getOrElse(false.B) val id_do_fence = WireDefault(id_rocc_busy && (id_ctrl.fence || id_csr_rocc_write) || id_vec_busy && id_ctrl.fence || id_mem_busy && (id_ctrl.amo && id_amo_rl || id_ctrl.fence_i || id_reg_fence && (id_ctrl.mem || id_ctrl.rocc))) val bpu = Module(new BreakpointUnit(nBreakpoints)) bpu.io.status := csr.io.status bpu.io.bp := csr.io.bp bpu.io.pc := ibuf.io.pc bpu.io.ea := mem_reg_wdata bpu.io.mcontext := csr.io.mcontext bpu.io.scontext := csr.io.scontext val id_xcpt0 = ibuf.io.inst(0).bits.xcpt0 val id_xcpt1 = ibuf.io.inst(0).bits.xcpt1 val (id_xcpt, id_cause) = checkExceptions(List( (csr.io.interrupt, csr.io.interrupt_cause), (bpu.io.debug_if, CSR.debugTriggerCause.U), (bpu.io.xcpt_if, Causes.breakpoint.U), (id_xcpt0.pf.inst, Causes.fetch_page_fault.U), (id_xcpt0.gf.inst, Causes.fetch_guest_page_fault.U), (id_xcpt0.ae.inst, Causes.fetch_access.U), (id_xcpt1.pf.inst, Causes.fetch_page_fault.U), (id_xcpt1.gf.inst, Causes.fetch_guest_page_fault.U), (id_xcpt1.ae.inst, Causes.fetch_access.U), (id_virtual_insn, Causes.virtual_instruction.U), (id_illegal_insn, Causes.illegal_instruction.U))) val idCoverCauses = List( (CSR.debugTriggerCause, "DEBUG_TRIGGER"), (Causes.breakpoint, "BREAKPOINT"), (Causes.fetch_access, "FETCH_ACCESS"), (Causes.illegal_instruction, "ILLEGAL_INSTRUCTION") ) ++ (if (usingVM) List( (Causes.fetch_page_fault, "FETCH_PAGE_FAULT") ) else Nil) coverExceptions(id_xcpt, id_cause, "DECODE", idCoverCauses) val dcache_bypass_data = if (fastLoadByte) io.dmem.resp.bits.data(xLen-1, 0) else if (fastLoadWord) io.dmem.resp.bits.data_word_bypass(xLen-1, 0) else wb_reg_wdata // detect bypass opportunities val ex_waddr = ex_reg_inst(11,7) & regAddrMask.U val mem_waddr = mem_reg_inst(11,7) & regAddrMask.U val wb_waddr = wb_reg_inst(11,7) & regAddrMask.U val bypass_sources = IndexedSeq( (true.B, 0.U, 0.U), // treat reading x0 as a bypass (ex_reg_valid && ex_ctrl.wxd, ex_waddr, mem_reg_wdata), (mem_reg_valid && mem_ctrl.wxd && !mem_ctrl.mem, mem_waddr, wb_reg_wdata), (mem_reg_valid && mem_ctrl.wxd, mem_waddr, dcache_bypass_data)) val id_bypass_src = id_raddr.map(raddr => bypass_sources.map(s => s._1 && s._2 === raddr)) // execute stage val bypass_mux = bypass_sources.map(_._3) val ex_reg_rs_bypass = Reg(Vec(id_raddr.size, Bool())) val ex_reg_rs_lsb = Reg(Vec(id_raddr.size, UInt(log2Ceil(bypass_sources.size).W))) val ex_reg_rs_msb = Reg(Vec(id_raddr.size, UInt())) val ex_rs = for (i <- 0 until id_raddr.size) yield Mux(ex_reg_rs_bypass(i), bypass_mux(ex_reg_rs_lsb(i)), Cat(ex_reg_rs_msb(i), ex_reg_rs_lsb(i))) val ex_imm = ImmGen(ex_ctrl.sel_imm, ex_reg_inst) val ex_rs1shl = Mux(ex_reg_inst(3), ex_rs(0)(31,0), ex_rs(0)) << ex_reg_inst(14,13) val ex_op1 = MuxLookup(ex_ctrl.sel_alu1, 0.S)(Seq( A1_RS1 -> ex_rs(0).asSInt, A1_PC -> ex_reg_pc.asSInt, A1_RS1SHL -> (if (rocketParams.useZba) ex_rs1shl.asSInt else 0.S) )) val ex_op2_oh = UIntToOH(Mux(ex_ctrl.sel_alu2(0), (ex_reg_inst >> 20).asUInt, ex_rs(1))(log2Ceil(xLen)-1,0)).asSInt val ex_op2 = MuxLookup(ex_ctrl.sel_alu2, 0.S)(Seq( A2_RS2 -> ex_rs(1).asSInt, A2_IMM -> ex_imm, A2_SIZE -> Mux(ex_reg_rvc, 2.S, 4.S), ) ++ (if (coreParams.useZbs) Seq( A2_RS2OH -> ex_op2_oh, A2_IMMOH -> ex_op2_oh, ) else Nil)) val (ex_new_vl, ex_new_vconfig) = if (usingVector) { val ex_new_vtype = VType.fromUInt(MuxCase(ex_rs(1), Seq( ex_reg_inst(31,30).andR -> ex_reg_inst(29,20), !ex_reg_inst(31) -> ex_reg_inst(30,20)))) val ex_avl = Mux(ex_ctrl.rxs1, Mux(ex_reg_inst(19,15) === 0.U, Mux(ex_reg_inst(11,7) === 0.U, csr.io.vector.get.vconfig.vl, ex_new_vtype.vlMax), ex_rs(0) ), ex_reg_inst(19,15)) val ex_new_vl = ex_new_vtype.vl(ex_avl, csr.io.vector.get.vconfig.vl, false.B, false.B, false.B) val ex_new_vconfig = Wire(new VConfig) ex_new_vconfig.vtype := ex_new_vtype ex_new_vconfig.vl := ex_new_vl (Some(ex_new_vl), Some(ex_new_vconfig)) } else { (None, None) } val alu = Module(new ALU) alu.io.dw := ex_ctrl.alu_dw alu.io.fn := ex_ctrl.alu_fn alu.io.in2 := ex_op2.asUInt alu.io.in1 := ex_op1.asUInt // multiplier and divider val div = Module(new MulDiv(if (pipelinedMul) mulDivParams.copy(mulUnroll = 0) else mulDivParams, width = xLen)) div.io.req.valid := ex_reg_valid && ex_ctrl.div div.io.req.bits.dw := ex_ctrl.alu_dw div.io.req.bits.fn := ex_ctrl.alu_fn div.io.req.bits.in1 := ex_rs(0) div.io.req.bits.in2 := ex_rs(1) div.io.req.bits.tag := ex_waddr val mul = pipelinedMul.option { val m = Module(new PipelinedMultiplier(xLen, 2)) m.io.req.valid := ex_reg_valid && ex_ctrl.mul m.io.req.bits := div.io.req.bits m } ex_reg_valid := !ctrl_killd ex_reg_replay := !take_pc && ibuf.io.inst(0).valid && ibuf.io.inst(0).bits.replay ex_reg_xcpt := !ctrl_killd && id_xcpt ex_reg_xcpt_interrupt := !take_pc && ibuf.io.inst(0).valid && csr.io.interrupt when (!ctrl_killd) { ex_ctrl := id_ctrl ex_reg_rvc := ibuf.io.inst(0).bits.rvc ex_ctrl.csr := id_csr when (id_ctrl.fence && id_fence_succ === 0.U) { id_reg_pause := true.B } when (id_fence_next) { id_reg_fence := true.B } when (id_xcpt) { // pass PC down ALU writeback pipeline for badaddr ex_ctrl.alu_fn := FN_ADD ex_ctrl.alu_dw := DW_XPR ex_ctrl.sel_alu1 := A1_RS1 // badaddr := instruction ex_ctrl.sel_alu2 := A2_ZERO when (id_xcpt1.asUInt.orR) { // badaddr := PC+2 ex_ctrl.sel_alu1 := A1_PC ex_ctrl.sel_alu2 := A2_SIZE ex_reg_rvc := true.B } when (bpu.io.xcpt_if || id_xcpt0.asUInt.orR) { // badaddr := PC ex_ctrl.sel_alu1 := A1_PC ex_ctrl.sel_alu2 := A2_ZERO } } ex_reg_flush_pipe := id_ctrl.fence_i || id_csr_flush ex_reg_load_use := id_load_use ex_reg_hls := usingHypervisor.B && id_system_insn && id_ctrl.mem_cmd.isOneOf(M_XRD, M_XWR, M_HLVX) ex_reg_mem_size := Mux(usingHypervisor.B && id_system_insn, id_inst(0)(27, 26), id_inst(0)(13, 12)) when (id_ctrl.mem_cmd.isOneOf(M_SFENCE, M_HFENCEV, M_HFENCEG, M_FLUSH_ALL)) { ex_reg_mem_size := Cat(id_raddr2 =/= 0.U, id_raddr1 =/= 0.U) } when (id_ctrl.mem_cmd === M_SFENCE && csr.io.status.v) { ex_ctrl.mem_cmd := M_HFENCEV } if (tile.dcache.flushOnFenceI) { when (id_ctrl.fence_i) { ex_reg_mem_size := 0.U } } for (i <- 0 until id_raddr.size) { val do_bypass = id_bypass_src(i).reduce(_||_) val bypass_src = PriorityEncoder(id_bypass_src(i)) ex_reg_rs_bypass(i) := do_bypass ex_reg_rs_lsb(i) := bypass_src when (id_ren(i) && !do_bypass) { ex_reg_rs_lsb(i) := id_rs(i)(log2Ceil(bypass_sources.size)-1, 0) ex_reg_rs_msb(i) := id_rs(i) >> log2Ceil(bypass_sources.size) } } when (id_illegal_insn || id_virtual_insn) { val inst = Mux(ibuf.io.inst(0).bits.rvc, id_raw_inst(0)(15, 0), id_raw_inst(0)) ex_reg_rs_bypass(0) := false.B ex_reg_rs_lsb(0) := inst(log2Ceil(bypass_sources.size)-1, 0) ex_reg_rs_msb(0) := inst >> log2Ceil(bypass_sources.size) } } when (!ctrl_killd || csr.io.interrupt || ibuf.io.inst(0).bits.replay) { ex_reg_cause := id_cause ex_reg_inst := id_inst(0) ex_reg_raw_inst := id_raw_inst(0) ex_reg_pc := ibuf.io.pc ex_reg_btb_resp := ibuf.io.btb_resp ex_reg_wphit := bpu.io.bpwatch.map { bpw => bpw.ivalid(0) } ex_reg_set_vconfig := id_set_vconfig && !id_xcpt } // replay inst in ex stage? val ex_pc_valid = ex_reg_valid || ex_reg_replay || ex_reg_xcpt_interrupt val wb_dcache_miss = wb_ctrl.mem && !io.dmem.resp.valid val replay_ex_structural = ex_ctrl.mem && !io.dmem.req.ready || ex_ctrl.div && !div.io.req.ready || ex_ctrl.vec && !io.vector.map(_.ex.ready).getOrElse(true.B) val replay_ex_load_use = wb_dcache_miss && ex_reg_load_use val replay_ex = ex_reg_replay || (ex_reg_valid && (replay_ex_structural || replay_ex_load_use)) val ctrl_killx = take_pc_mem_wb || replay_ex || !ex_reg_valid // detect 2-cycle load-use delay for LB/LH/SC val ex_slow_bypass = ex_ctrl.mem_cmd === M_XSC || ex_reg_mem_size < 2.U val ex_sfence = usingVM.B && ex_ctrl.mem && (ex_ctrl.mem_cmd === M_SFENCE || ex_ctrl.mem_cmd === M_HFENCEV || ex_ctrl.mem_cmd === M_HFENCEG) val (ex_xcpt, ex_cause) = checkExceptions(List( (ex_reg_xcpt_interrupt || ex_reg_xcpt, ex_reg_cause))) val exCoverCauses = idCoverCauses coverExceptions(ex_xcpt, ex_cause, "EXECUTE", exCoverCauses) // memory stage val mem_pc_valid = mem_reg_valid || mem_reg_replay || mem_reg_xcpt_interrupt val mem_br_target = mem_reg_pc.asSInt + Mux(mem_ctrl.branch && mem_br_taken, ImmGen(IMM_SB, mem_reg_inst), Mux(mem_ctrl.jal, ImmGen(IMM_UJ, mem_reg_inst), Mux(mem_reg_rvc, 2.S, 4.S))) val mem_npc = (Mux(mem_ctrl.jalr || mem_reg_sfence, encodeVirtualAddress(mem_reg_wdata, mem_reg_wdata).asSInt, mem_br_target) & (-2).S).asUInt val mem_wrong_npc = Mux(ex_pc_valid, mem_npc =/= ex_reg_pc, Mux(ibuf.io.inst(0).valid || ibuf.io.imem.valid, mem_npc =/= ibuf.io.pc, true.B)) val mem_npc_misaligned = !csr.io.status.isa('c'-'a') && mem_npc(1) && !mem_reg_sfence val mem_int_wdata = Mux(!mem_reg_xcpt && (mem_ctrl.jalr ^ mem_npc_misaligned), mem_br_target, mem_reg_wdata.asSInt).asUInt val mem_cfi = mem_ctrl.branch || mem_ctrl.jalr || mem_ctrl.jal val mem_cfi_taken = (mem_ctrl.branch && mem_br_taken) || mem_ctrl.jalr || mem_ctrl.jal val mem_direction_misprediction = mem_ctrl.branch && mem_br_taken =/= (usingBTB.B && mem_reg_btb_resp.taken) val mem_misprediction = if (usingBTB) mem_wrong_npc else mem_cfi_taken take_pc_mem := mem_reg_valid && !mem_reg_xcpt && (mem_misprediction || mem_reg_sfence) mem_reg_valid := !ctrl_killx mem_reg_replay := !take_pc_mem_wb && replay_ex mem_reg_xcpt := !ctrl_killx && ex_xcpt mem_reg_xcpt_interrupt := !take_pc_mem_wb && ex_reg_xcpt_interrupt // on pipeline flushes, cause mem_npc to hold the sequential npc, which // will drive the W-stage npc mux when (mem_reg_valid && mem_reg_flush_pipe) { mem_reg_sfence := false.B }.elsewhen (ex_pc_valid) { mem_ctrl := ex_ctrl mem_reg_rvc := ex_reg_rvc mem_reg_load := ex_ctrl.mem && isRead(ex_ctrl.mem_cmd) mem_reg_store := ex_ctrl.mem && isWrite(ex_ctrl.mem_cmd) mem_reg_sfence := ex_sfence mem_reg_btb_resp := ex_reg_btb_resp mem_reg_flush_pipe := ex_reg_flush_pipe mem_reg_slow_bypass := ex_slow_bypass mem_reg_wphit := ex_reg_wphit mem_reg_set_vconfig := ex_reg_set_vconfig mem_reg_cause := ex_cause mem_reg_inst := ex_reg_inst mem_reg_raw_inst := ex_reg_raw_inst mem_reg_mem_size := ex_reg_mem_size mem_reg_hls_or_dv := io.dmem.req.bits.dv mem_reg_pc := ex_reg_pc // IDecode ensured they are 1H mem_reg_wdata := Mux(ex_reg_set_vconfig, ex_new_vl.getOrElse(alu.io.out), alu.io.out) mem_br_taken := alu.io.cmp_out when (ex_ctrl.rxs2 && (ex_ctrl.mem || ex_ctrl.rocc || ex_sfence)) { val size = Mux(ex_ctrl.rocc, log2Ceil(xLen/8).U, ex_reg_mem_size) mem_reg_rs2 := new StoreGen(size, 0.U, ex_rs(1), coreDataBytes).data } if (usingVector) { when (ex_reg_set_vconfig) { mem_reg_rs2 := ex_new_vconfig.get.asUInt } } when (ex_ctrl.jalr && csr.io.status.debug) { // flush I$ on D-mode JALR to effect uncached fetch without D$ flush mem_ctrl.fence_i := true.B mem_reg_flush_pipe := true.B } } val mem_breakpoint = (mem_reg_load && bpu.io.xcpt_ld) || (mem_reg_store && bpu.io.xcpt_st) val mem_debug_breakpoint = (mem_reg_load && bpu.io.debug_ld) || (mem_reg_store && bpu.io.debug_st) val (mem_ldst_xcpt, mem_ldst_cause) = checkExceptions(List( (mem_debug_breakpoint, CSR.debugTriggerCause.U), (mem_breakpoint, Causes.breakpoint.U))) val (mem_xcpt, mem_cause) = checkExceptions(List( (mem_reg_xcpt_interrupt || mem_reg_xcpt, mem_reg_cause), (mem_reg_valid && mem_npc_misaligned, Causes.misaligned_fetch.U), (mem_reg_valid && mem_ldst_xcpt, mem_ldst_cause))) val memCoverCauses = (exCoverCauses ++ List( (CSR.debugTriggerCause, "DEBUG_TRIGGER"), (Causes.breakpoint, "BREAKPOINT"), (Causes.misaligned_fetch, "MISALIGNED_FETCH") )).distinct coverExceptions(mem_xcpt, mem_cause, "MEMORY", memCoverCauses) val dcache_kill_mem = mem_reg_valid && mem_ctrl.wxd && io.dmem.replay_next // structural hazard on writeback port val fpu_kill_mem = mem_reg_valid && mem_ctrl.fp && io.fpu.nack_mem val vec_kill_mem = mem_reg_valid && mem_ctrl.mem && io.vector.map(_.mem.block_mem).getOrElse(false.B) val vec_kill_all = mem_reg_valid && io.vector.map(_.mem.block_all).getOrElse(false.B) val replay_mem = dcache_kill_mem || mem_reg_replay || fpu_kill_mem || vec_kill_mem || vec_kill_all val killm_common = dcache_kill_mem || take_pc_wb || mem_reg_xcpt || !mem_reg_valid div.io.kill := killm_common && RegNext(div.io.req.fire) val ctrl_killm = killm_common || mem_xcpt || fpu_kill_mem || vec_kill_mem // writeback stage wb_reg_valid := !ctrl_killm wb_reg_replay := replay_mem && !take_pc_wb wb_reg_xcpt := mem_xcpt && !take_pc_wb && !io.vector.map(_.mem.block_all).getOrElse(false.B) wb_reg_flush_pipe := !ctrl_killm && mem_reg_flush_pipe when (mem_pc_valid) { wb_ctrl := mem_ctrl wb_reg_sfence := mem_reg_sfence wb_reg_wdata := Mux(!mem_reg_xcpt && mem_ctrl.fp && mem_ctrl.wxd, io.fpu.toint_data, mem_int_wdata) when (mem_ctrl.rocc || mem_reg_sfence || mem_reg_set_vconfig) { wb_reg_rs2 := mem_reg_rs2 } wb_reg_cause := mem_cause wb_reg_inst := mem_reg_inst wb_reg_raw_inst := mem_reg_raw_inst wb_reg_mem_size := mem_reg_mem_size wb_reg_hls_or_dv := mem_reg_hls_or_dv wb_reg_hfence_v := mem_ctrl.mem_cmd === M_HFENCEV wb_reg_hfence_g := mem_ctrl.mem_cmd === M_HFENCEG wb_reg_pc := mem_reg_pc wb_reg_wphit := mem_reg_wphit | bpu.io.bpwatch.map { bpw => (bpw.rvalid(0) && mem_reg_load) || (bpw.wvalid(0) && mem_reg_store) } wb_reg_set_vconfig := mem_reg_set_vconfig } val (wb_xcpt, wb_cause) = checkExceptions(List( (wb_reg_xcpt, wb_reg_cause), (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.pf.st, Causes.store_page_fault.U), (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.pf.ld, Causes.load_page_fault.U), (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.gf.st, Causes.store_guest_page_fault.U), (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.gf.ld, Causes.load_guest_page_fault.U), (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.ae.st, Causes.store_access.U), (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.ae.ld, Causes.load_access.U), (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.ma.st, Causes.misaligned_store.U), (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.ma.ld, Causes.misaligned_load.U) )) val wbCoverCauses = List( (Causes.misaligned_store, "MISALIGNED_STORE"), (Causes.misaligned_load, "MISALIGNED_LOAD"), (Causes.store_access, "STORE_ACCESS"), (Causes.load_access, "LOAD_ACCESS") ) ++ (if(usingVM) List( (Causes.store_page_fault, "STORE_PAGE_FAULT"), (Causes.load_page_fault, "LOAD_PAGE_FAULT") ) else Nil) ++ (if (usingHypervisor) List( (Causes.store_guest_page_fault, "STORE_GUEST_PAGE_FAULT"), (Causes.load_guest_page_fault, "LOAD_GUEST_PAGE_FAULT"), ) else Nil) coverExceptions(wb_xcpt, wb_cause, "WRITEBACK", wbCoverCauses) val wb_pc_valid = wb_reg_valid || wb_reg_replay || wb_reg_xcpt val wb_wxd = wb_reg_valid && wb_ctrl.wxd val wb_set_sboard = wb_ctrl.div || wb_dcache_miss || wb_ctrl.rocc || wb_ctrl.vec val replay_wb_common = io.dmem.s2_nack || wb_reg_replay val replay_wb_rocc = wb_reg_valid && wb_ctrl.rocc && !io.rocc.cmd.ready val replay_wb_csr: Bool = wb_reg_valid && csr.io.rw_stall val replay_wb_vec = wb_reg_valid && io.vector.map(_.wb.replay).getOrElse(false.B) val replay_wb = replay_wb_common || replay_wb_rocc || replay_wb_csr || replay_wb_vec take_pc_wb := replay_wb || wb_xcpt || csr.io.eret || wb_reg_flush_pipe // writeback arbitration val dmem_resp_xpu = !io.dmem.resp.bits.tag(0).asBool val dmem_resp_fpu = io.dmem.resp.bits.tag(0).asBool val dmem_resp_waddr = io.dmem.resp.bits.tag(5, 1) val dmem_resp_valid = io.dmem.resp.valid && io.dmem.resp.bits.has_data val dmem_resp_replay = dmem_resp_valid && io.dmem.resp.bits.replay class LLWB extends Bundle { val data = UInt(xLen.W) val tag = UInt(5.W) } val ll_arb = Module(new Arbiter(new LLWB, 3)) // div, rocc, vec ll_arb.io.in.foreach(_.valid := false.B) ll_arb.io.in.foreach(_.bits := DontCare) val ll_wdata = WireInit(ll_arb.io.out.bits.data) val ll_waddr = WireInit(ll_arb.io.out.bits.tag) val ll_wen = WireInit(ll_arb.io.out.fire) ll_arb.io.out.ready := !wb_wxd div.io.resp.ready := ll_arb.io.in(0).ready ll_arb.io.in(0).valid := div.io.resp.valid ll_arb.io.in(0).bits.data := div.io.resp.bits.data ll_arb.io.in(0).bits.tag := div.io.resp.bits.tag if (usingRoCC) { io.rocc.resp.ready := ll_arb.io.in(1).ready ll_arb.io.in(1).valid := io.rocc.resp.valid ll_arb.io.in(1).bits.data := io.rocc.resp.bits.data ll_arb.io.in(1).bits.tag := io.rocc.resp.bits.rd } else { // tie off RoCC io.rocc.resp.ready := false.B io.rocc.mem.req.ready := false.B } io.vector.map { v => v.resp.ready := Mux(v.resp.bits.fp, !(dmem_resp_valid && dmem_resp_fpu), ll_arb.io.in(2).ready) ll_arb.io.in(2).valid := v.resp.valid && !v.resp.bits.fp ll_arb.io.in(2).bits.data := v.resp.bits.data ll_arb.io.in(2).bits.tag := v.resp.bits.rd } // Dont care mem since not all RoCC need accessing memory io.rocc.mem := DontCare when (dmem_resp_replay && dmem_resp_xpu) { ll_arb.io.out.ready := false.B ll_waddr := dmem_resp_waddr ll_wen := true.B } val wb_valid = wb_reg_valid && !replay_wb && !wb_xcpt val wb_wen = wb_valid && wb_ctrl.wxd val rf_wen = wb_wen || ll_wen val rf_waddr = Mux(ll_wen, ll_waddr, wb_waddr) val rf_wdata = Mux(dmem_resp_valid && dmem_resp_xpu, io.dmem.resp.bits.data(xLen-1, 0), Mux(ll_wen, ll_wdata, Mux(wb_ctrl.csr =/= CSR.N, csr.io.rw.rdata, Mux(wb_ctrl.mul, mul.map(_.io.resp.bits.data).getOrElse(wb_reg_wdata), wb_reg_wdata)))) when (rf_wen) { rf.write(rf_waddr, rf_wdata) } // hook up control/status regfile csr.io.ungated_clock := clock csr.io.decode(0).inst := id_inst(0) csr.io.exception := wb_xcpt csr.io.cause := wb_cause csr.io.retire := wb_valid csr.io.inst(0) := (if (usingCompressed) Cat(Mux(wb_reg_raw_inst(1, 0).andR, wb_reg_inst >> 16, 0.U), wb_reg_raw_inst(15, 0)) else wb_reg_inst) csr.io.interrupts := io.interrupts csr.io.hartid := io.hartid io.fpu.fcsr_rm := csr.io.fcsr_rm val vector_fcsr_flags = io.vector.map(_.set_fflags.bits).getOrElse(0.U(5.W)) val vector_fcsr_flags_valid = io.vector.map(_.set_fflags.valid).getOrElse(false.B) csr.io.fcsr_flags.valid := io.fpu.fcsr_flags.valid | vector_fcsr_flags_valid csr.io.fcsr_flags.bits := (io.fpu.fcsr_flags.bits & Fill(5, io.fpu.fcsr_flags.valid)) | (vector_fcsr_flags & Fill(5, vector_fcsr_flags_valid)) io.fpu.time := csr.io.time(31,0) io.fpu.hartid := io.hartid csr.io.rocc_interrupt := io.rocc.interrupt csr.io.pc := wb_reg_pc val tval_dmem_addr = !wb_reg_xcpt val tval_any_addr = tval_dmem_addr || wb_reg_cause.isOneOf(Causes.breakpoint.U, Causes.fetch_access.U, Causes.fetch_page_fault.U, Causes.fetch_guest_page_fault.U) val tval_inst = wb_reg_cause === Causes.illegal_instruction.U val tval_valid = wb_xcpt && (tval_any_addr || tval_inst) csr.io.gva := wb_xcpt && (tval_any_addr && csr.io.status.v || tval_dmem_addr && wb_reg_hls_or_dv) csr.io.tval := Mux(tval_valid, encodeVirtualAddress(wb_reg_wdata, wb_reg_wdata), 0.U) val (htval, mhtinst_read_pseudo) = { val htval_valid_imem = wb_reg_xcpt && wb_reg_cause === Causes.fetch_guest_page_fault.U val htval_imem = Mux(htval_valid_imem, io.imem.gpa.bits, 0.U) assert(!htval_valid_imem || io.imem.gpa.valid) val htval_valid_dmem = wb_xcpt && tval_dmem_addr && io.dmem.s2_xcpt.gf.asUInt.orR && !io.dmem.s2_xcpt.pf.asUInt.orR val htval_dmem = Mux(htval_valid_dmem, io.dmem.s2_gpa, 0.U) val htval = (htval_dmem | htval_imem) >> hypervisorExtraAddrBits // read pseudoinstruction if a guest-page fault is caused by an implicit memory access for VS-stage address translation val mhtinst_read_pseudo = (io.imem.gpa_is_pte && htval_valid_imem) || (io.dmem.s2_gpa_is_pte && htval_valid_dmem) (htval, mhtinst_read_pseudo) } csr.io.vector.foreach { v => v.set_vconfig.valid := wb_reg_set_vconfig && wb_reg_valid v.set_vconfig.bits := wb_reg_rs2.asTypeOf(new VConfig) v.set_vs_dirty := wb_valid && wb_ctrl.vec v.set_vstart.valid := wb_valid && wb_reg_set_vconfig v.set_vstart.bits := 0.U } io.vector.foreach { v => when (v.wb.retire || v.wb.xcpt || wb_ctrl.vec) { csr.io.pc := v.wb.pc csr.io.retire := v.wb.retire csr.io.inst(0) := v.wb.inst when (v.wb.xcpt && !wb_reg_xcpt) { wb_xcpt := true.B wb_cause := v.wb.cause csr.io.tval := v.wb.tval } } v.wb.store_pending := io.dmem.store_pending v.wb.vxrm := csr.io.vector.get.vxrm v.wb.frm := csr.io.fcsr_rm csr.io.vector.get.set_vxsat := v.set_vxsat when (v.set_vconfig.valid) { csr.io.vector.get.set_vconfig.valid := true.B csr.io.vector.get.set_vconfig.bits := v.set_vconfig.bits } when (v.set_vstart.valid) { csr.io.vector.get.set_vstart.valid := true.B csr.io.vector.get.set_vstart.bits := v.set_vstart.bits } } csr.io.htval := htval csr.io.mhtinst_read_pseudo := mhtinst_read_pseudo io.ptw.ptbr := csr.io.ptbr io.ptw.hgatp := csr.io.hgatp io.ptw.vsatp := csr.io.vsatp (io.ptw.customCSRs.csrs zip csr.io.customCSRs).map { case (lhs, rhs) => lhs <> rhs } io.ptw.status := csr.io.status io.ptw.hstatus := csr.io.hstatus io.ptw.gstatus := csr.io.gstatus io.ptw.pmp := csr.io.pmp csr.io.rw.addr := wb_reg_inst(31,20) csr.io.rw.cmd := CSR.maskCmd(wb_reg_valid, wb_ctrl.csr) csr.io.rw.wdata := wb_reg_wdata io.rocc.csrs <> csr.io.roccCSRs io.trace.time := csr.io.time io.trace.insns := csr.io.trace if (rocketParams.debugROB.isDefined) { val sz = rocketParams.debugROB.get.size if (sz < 1) { // use unsynthesizable ROB val csr_trace_with_wdata = WireInit(csr.io.trace(0)) csr_trace_with_wdata.wdata.get := rf_wdata val should_wb = WireInit((wb_ctrl.wfd || (wb_ctrl.wxd && wb_waddr =/= 0.U)) && !csr.io.trace(0).exception) val has_wb = WireInit(wb_ctrl.wxd && wb_wen && !wb_set_sboard) val wb_addr = WireInit(wb_waddr + Mux(wb_ctrl.wfd, 32.U, 0.U)) io.vector.foreach { v => when (v.wb.retire) { should_wb := v.wb.rob_should_wb has_wb := false.B wb_addr := Cat(v.wb.rob_should_wb_fp, csr_trace_with_wdata.insn(11,7)) }} DebugROB.pushTrace(clock, reset, io.hartid, csr_trace_with_wdata, should_wb, has_wb, wb_addr) io.trace.insns(0) := DebugROB.popTrace(clock, reset, io.hartid) DebugROB.pushWb(clock, reset, io.hartid, ll_wen, rf_waddr, rf_wdata) } else { // synthesizable ROB (no FPRs) require(!usingVector, "Synthesizable ROB does not support vector implementations") val csr_trace_with_wdata = WireInit(csr.io.trace(0)) csr_trace_with_wdata.wdata.get := rf_wdata val debug_rob = Module(new HardDebugROB(sz, 32)) debug_rob.io.i_insn := csr_trace_with_wdata debug_rob.io.should_wb := (wb_ctrl.wfd || (wb_ctrl.wxd && wb_waddr =/= 0.U)) && !csr.io.trace(0).exception debug_rob.io.has_wb := wb_ctrl.wxd && wb_wen && !wb_set_sboard debug_rob.io.tag := wb_waddr + Mux(wb_ctrl.wfd, 32.U, 0.U) debug_rob.io.wb_val := ll_wen debug_rob.io.wb_tag := rf_waddr debug_rob.io.wb_data := rf_wdata io.trace.insns(0) := debug_rob.io.o_insn } } else { io.trace.insns := csr.io.trace } for (((iobpw, wphit), bp) <- io.bpwatch zip wb_reg_wphit zip csr.io.bp) { iobpw.valid(0) := wphit iobpw.action := bp.control.action // tie off bpwatch valids iobpw.rvalid.foreach(_ := false.B) iobpw.wvalid.foreach(_ := false.B) iobpw.ivalid.foreach(_ := false.B) } val hazard_targets = Seq((id_ctrl.rxs1 && id_raddr1 =/= 0.U, id_raddr1), (id_ctrl.rxs2 && id_raddr2 =/= 0.U, id_raddr2), (id_ctrl.wxd && id_waddr =/= 0.U, id_waddr)) val fp_hazard_targets = Seq((io.fpu.dec.ren1, id_raddr1), (io.fpu.dec.ren2, id_raddr2), (io.fpu.dec.ren3, id_raddr3), (io.fpu.dec.wen, id_waddr)) val sboard = new Scoreboard(32, true) sboard.clear(ll_wen, ll_waddr) def id_sboard_clear_bypass(r: UInt) = { // ll_waddr arrives late when D$ has ECC, so reshuffle the hazard check if (!tileParams.dcache.get.dataECC.isDefined) ll_wen && ll_waddr === r else div.io.resp.fire && div.io.resp.bits.tag === r || dmem_resp_replay && dmem_resp_xpu && dmem_resp_waddr === r } val id_sboard_hazard = checkHazards(hazard_targets, rd => sboard.read(rd) && !id_sboard_clear_bypass(rd)) sboard.set(wb_set_sboard && wb_wen, wb_waddr) // stall for RAW/WAW hazards on CSRs, loads, AMOs, and mul/div in execute stage. val ex_cannot_bypass = ex_ctrl.csr =/= CSR.N || ex_ctrl.jalr || ex_ctrl.mem || ex_ctrl.mul || ex_ctrl.div || ex_ctrl.fp || ex_ctrl.rocc || ex_ctrl.vec val data_hazard_ex = ex_ctrl.wxd && checkHazards(hazard_targets, _ === ex_waddr) val fp_data_hazard_ex = id_ctrl.fp && ex_ctrl.wfd && checkHazards(fp_hazard_targets, _ === ex_waddr) val id_ex_hazard = ex_reg_valid && (data_hazard_ex && ex_cannot_bypass || fp_data_hazard_ex) // stall for RAW/WAW hazards on CSRs, LB/LH, and mul/div in memory stage. val mem_mem_cmd_bh = if (fastLoadWord) (!fastLoadByte).B && mem_reg_slow_bypass else true.B val mem_cannot_bypass = mem_ctrl.csr =/= CSR.N || mem_ctrl.mem && mem_mem_cmd_bh || mem_ctrl.mul || mem_ctrl.div || mem_ctrl.fp || mem_ctrl.rocc || mem_ctrl.vec val data_hazard_mem = mem_ctrl.wxd && checkHazards(hazard_targets, _ === mem_waddr) val fp_data_hazard_mem = id_ctrl.fp && mem_ctrl.wfd && checkHazards(fp_hazard_targets, _ === mem_waddr) val id_mem_hazard = mem_reg_valid && (data_hazard_mem && mem_cannot_bypass || fp_data_hazard_mem) id_load_use := mem_reg_valid && data_hazard_mem && mem_ctrl.mem val id_vconfig_hazard = id_ctrl.vec && ( (ex_reg_valid && ex_reg_set_vconfig) || (mem_reg_valid && mem_reg_set_vconfig) || (wb_reg_valid && wb_reg_set_vconfig)) // stall for RAW/WAW hazards on load/AMO misses and mul/div in writeback. val data_hazard_wb = wb_ctrl.wxd && checkHazards(hazard_targets, _ === wb_waddr) val fp_data_hazard_wb = id_ctrl.fp && wb_ctrl.wfd && checkHazards(fp_hazard_targets, _ === wb_waddr) val id_wb_hazard = wb_reg_valid && (data_hazard_wb && wb_set_sboard || fp_data_hazard_wb) val id_stall_fpu = if (usingFPU) { val fp_sboard = new Scoreboard(32) fp_sboard.set(((wb_dcache_miss || wb_ctrl.vec) && wb_ctrl.wfd || io.fpu.sboard_set) && wb_valid, wb_waddr) val v_ll = io.vector.map(v => v.resp.fire && v.resp.bits.fp).getOrElse(false.B) fp_sboard.clear((dmem_resp_replay && dmem_resp_fpu) || v_ll, io.fpu.ll_resp_tag) fp_sboard.clear(io.fpu.sboard_clr, io.fpu.sboard_clra) checkHazards(fp_hazard_targets, fp_sboard.read _) } else false.B val dcache_blocked = { // speculate that a blocked D$ will unblock the cycle after a Grant val blocked = Reg(Bool()) blocked := !io.dmem.req.ready && io.dmem.clock_enabled && !io.dmem.perf.grant && (blocked || io.dmem.req.valid || io.dmem.s2_nack) blocked && !io.dmem.perf.grant } val rocc_blocked = Reg(Bool()) rocc_blocked := !wb_xcpt && !io.rocc.cmd.ready && (io.rocc.cmd.valid || rocc_blocked) val ctrl_stalld = id_ex_hazard || id_mem_hazard || id_wb_hazard || id_sboard_hazard || id_vconfig_hazard || csr.io.singleStep && (ex_reg_valid || mem_reg_valid || wb_reg_valid) || id_csr_en && csr.io.decode(0).fp_csr && !io.fpu.fcsr_rdy || id_csr_en && csr.io.decode(0).vector_csr && id_vec_busy || id_ctrl.fp && id_stall_fpu || id_ctrl.mem && dcache_blocked || // reduce activity during D$ misses id_ctrl.rocc && rocc_blocked || // reduce activity while RoCC is busy id_ctrl.div && (!(div.io.req.ready || (div.io.resp.valid && !wb_wxd)) || div.io.req.valid) || // reduce odds of replay !clock_en || id_do_fence || csr.io.csr_stall || id_reg_pause || io.traceStall ctrl_killd := !ibuf.io.inst(0).valid || ibuf.io.inst(0).bits.replay || take_pc_mem_wb || ctrl_stalld || csr.io.interrupt io.imem.req.valid := take_pc io.imem.req.bits.speculative := !take_pc_wb io.imem.req.bits.pc := Mux(wb_xcpt || csr.io.eret, csr.io.evec, // exception or [m|s]ret Mux(replay_wb, wb_reg_pc, // replay mem_npc)) // flush or branch misprediction io.imem.flush_icache := wb_reg_valid && wb_ctrl.fence_i && !io.dmem.s2_nack io.imem.might_request := { imem_might_request_reg := ex_pc_valid || mem_pc_valid || io.ptw.customCSRs.disableICacheClockGate || io.vector.map(_.trap_check_busy).getOrElse(false.B) imem_might_request_reg } io.imem.progress := RegNext(wb_reg_valid && !replay_wb_common) io.imem.sfence.valid := wb_reg_valid && wb_reg_sfence io.imem.sfence.bits.rs1 := wb_reg_mem_size(0) io.imem.sfence.bits.rs2 := wb_reg_mem_size(1) io.imem.sfence.bits.addr := wb_reg_wdata io.imem.sfence.bits.asid := wb_reg_rs2 io.imem.sfence.bits.hv := wb_reg_hfence_v io.imem.sfence.bits.hg := wb_reg_hfence_g io.ptw.sfence := io.imem.sfence ibuf.io.inst(0).ready := !ctrl_stalld io.imem.btb_update.valid := mem_reg_valid && !take_pc_wb && mem_wrong_npc && (!mem_cfi || mem_cfi_taken) io.imem.btb_update.bits.isValid := mem_cfi io.imem.btb_update.bits.cfiType := Mux((mem_ctrl.jal || mem_ctrl.jalr) && mem_waddr(0), CFIType.call, Mux(mem_ctrl.jalr && (mem_reg_inst(19,15) & regAddrMask.U) === BitPat("b00?01"), CFIType.ret, Mux(mem_ctrl.jal || mem_ctrl.jalr, CFIType.jump, CFIType.branch))) io.imem.btb_update.bits.target := io.imem.req.bits.pc io.imem.btb_update.bits.br_pc := (if (usingCompressed) mem_reg_pc + Mux(mem_reg_rvc, 0.U, 2.U) else mem_reg_pc) io.imem.btb_update.bits.pc := ~(~io.imem.btb_update.bits.br_pc | (coreInstBytes*fetchWidth-1).U) io.imem.btb_update.bits.prediction := mem_reg_btb_resp io.imem.btb_update.bits.taken := DontCare io.imem.bht_update.valid := mem_reg_valid && !take_pc_wb io.imem.bht_update.bits.pc := io.imem.btb_update.bits.pc io.imem.bht_update.bits.taken := mem_br_taken io.imem.bht_update.bits.mispredict := mem_wrong_npc io.imem.bht_update.bits.branch := mem_ctrl.branch io.imem.bht_update.bits.prediction := mem_reg_btb_resp.bht // Connect RAS in Frontend io.imem.ras_update := DontCare io.fpu.valid := !ctrl_killd && id_ctrl.fp io.fpu.killx := ctrl_killx io.fpu.killm := killm_common io.fpu.inst := id_inst(0) io.fpu.fromint_data := ex_rs(0) io.fpu.ll_resp_val := dmem_resp_valid && dmem_resp_fpu io.fpu.ll_resp_data := (if (minFLen == 32) io.dmem.resp.bits.data_word_bypass else io.dmem.resp.bits.data) io.fpu.ll_resp_type := io.dmem.resp.bits.size io.fpu.ll_resp_tag := dmem_resp_waddr io.fpu.keep_clock_enabled := io.ptw.customCSRs.disableCoreClockGate io.fpu.v_sew := csr.io.vector.map(_.vconfig.vtype.vsew).getOrElse(0.U) io.vector.map { v => when (!(dmem_resp_valid && dmem_resp_fpu)) { io.fpu.ll_resp_val := v.resp.valid && v.resp.bits.fp io.fpu.ll_resp_data := v.resp.bits.data io.fpu.ll_resp_type := v.resp.bits.size io.fpu.ll_resp_tag := v.resp.bits.rd } } io.vector.foreach { v => v.ex.valid := ex_reg_valid && (ex_ctrl.vec || rocketParams.vector.get.issueVConfig.B && ex_reg_set_vconfig) && !ctrl_killx v.ex.inst := ex_reg_inst v.ex.vconfig := csr.io.vector.get.vconfig v.ex.vstart := Mux(mem_reg_valid && mem_ctrl.vec || wb_reg_valid && wb_ctrl.vec, 0.U, csr.io.vector.get.vstart) v.ex.rs1 := ex_rs(0) v.ex.rs2 := ex_rs(1) v.ex.pc := ex_reg_pc v.mem.frs1 := io.fpu.store_data v.killm := killm_common v.status := csr.io.status } io.dmem.req.valid := ex_reg_valid && ex_ctrl.mem val ex_dcache_tag = Cat(ex_waddr, ex_ctrl.fp) require(coreParams.dcacheReqTagBits >= ex_dcache_tag.getWidth) io.dmem.req.bits.tag := ex_dcache_tag io.dmem.req.bits.cmd := ex_ctrl.mem_cmd io.dmem.req.bits.size := ex_reg_mem_size io.dmem.req.bits.signed := !Mux(ex_reg_hls, ex_reg_inst(20), ex_reg_inst(14)) io.dmem.req.bits.phys := false.B io.dmem.req.bits.addr := encodeVirtualAddress(ex_rs(0), alu.io.adder_out) io.dmem.req.bits.idx.foreach(_ := io.dmem.req.bits.addr) io.dmem.req.bits.dprv := Mux(ex_reg_hls, csr.io.hstatus.spvp, csr.io.status.dprv) io.dmem.req.bits.dv := ex_reg_hls || csr.io.status.dv io.dmem.req.bits.no_resp := !isRead(ex_ctrl.mem_cmd) || (!ex_ctrl.fp && ex_waddr === 0.U) io.dmem.req.bits.no_alloc := DontCare io.dmem.req.bits.no_xcpt := DontCare io.dmem.req.bits.data := DontCare io.dmem.req.bits.mask := DontCare io.dmem.s1_data.data := (if (fLen == 0) mem_reg_rs2 else Mux(mem_ctrl.fp, Fill(coreDataBits / fLen, io.fpu.store_data), mem_reg_rs2)) io.dmem.s1_data.mask := DontCare io.dmem.s1_kill := killm_common || mem_ldst_xcpt || fpu_kill_mem || vec_kill_mem io.dmem.s2_kill := false.B // don't let D$ go to sleep if we're probably going to use it soon io.dmem.keep_clock_enabled := ibuf.io.inst(0).valid && id_ctrl.mem && !csr.io.csr_stall io.rocc.cmd.valid := wb_reg_valid && wb_ctrl.rocc && !replay_wb_common io.rocc.exception := wb_xcpt && csr.io.status.xs.orR io.rocc.cmd.bits.status := csr.io.status io.rocc.cmd.bits.inst := wb_reg_inst.asTypeOf(new RoCCInstruction()) io.rocc.cmd.bits.rs1 := wb_reg_wdata io.rocc.cmd.bits.rs2 := wb_reg_rs2 // gate the clock val unpause = csr.io.time(rocketParams.lgPauseCycles-1, 0) === 0.U || csr.io.inhibit_cycle || io.dmem.perf.release || take_pc when (unpause) { id_reg_pause := false.B } io.cease := csr.io.status.cease && !clock_en_reg io.wfi := csr.io.status.wfi if (rocketParams.clockGate) { long_latency_stall := csr.io.csr_stall || io.dmem.perf.blocked || id_reg_pause && !unpause clock_en := clock_en_reg || ex_pc_valid || (!long_latency_stall && io.imem.resp.valid) clock_en_reg := ex_pc_valid || mem_pc_valid || wb_pc_valid || // instruction in flight io.ptw.customCSRs.disableCoreClockGate || // chicken bit !div.io.req.ready || // mul/div in flight usingFPU.B && !io.fpu.fcsr_rdy || // long-latency FPU in flight io.dmem.replay_next || // long-latency load replaying (!long_latency_stall && (ibuf.io.inst(0).valid || io.imem.resp.valid)) // instruction pending assert(!(ex_pc_valid || mem_pc_valid || wb_pc_valid) || clock_en) } // evaluate performance counters val icache_blocked = !(io.imem.resp.valid || RegNext(io.imem.resp.valid)) csr.io.counters foreach { c => c.inc := RegNext(perfEvents.evaluate(c.eventSel)) } val coreMonitorBundle = Wire(new CoreMonitorBundle(xLen, fLen)) coreMonitorBundle.clock := clock coreMonitorBundle.reset := reset coreMonitorBundle.hartid := io.hartid coreMonitorBundle.timer := csr.io.time(31,0) coreMonitorBundle.valid := csr.io.trace(0).valid && !csr.io.trace(0).exception coreMonitorBundle.pc := csr.io.trace(0).iaddr(vaddrBitsExtended-1, 0).sextTo(xLen) coreMonitorBundle.wrenx := wb_wen && !wb_set_sboard coreMonitorBundle.wrenf := false.B coreMonitorBundle.wrdst := wb_waddr coreMonitorBundle.wrdata := rf_wdata coreMonitorBundle.rd0src := wb_reg_inst(19,15) coreMonitorBundle.rd0val := RegNext(RegNext(ex_rs(0))) coreMonitorBundle.rd1src := wb_reg_inst(24,20) coreMonitorBundle.rd1val := RegNext(RegNext(ex_rs(1))) coreMonitorBundle.inst := csr.io.trace(0).insn coreMonitorBundle.excpt := csr.io.trace(0).exception coreMonitorBundle.priv_mode := csr.io.trace(0).priv if (enableCommitLog) { val t = csr.io.trace(0) val rd = wb_waddr val wfd = wb_ctrl.wfd val wxd = wb_ctrl.wxd val has_data = wb_wen && !wb_set_sboard when (t.valid && !t.exception) { when (wfd) { printf ("%d 0x%x (0x%x) f%d p%d 0xXXXXXXXXXXXXXXXX\n", t.priv, t.iaddr, t.insn, rd, rd+32.U) } .elsewhen (wxd && rd =/= 0.U && has_data) { printf ("%d 0x%x (0x%x) x%d 0x%x\n", t.priv, t.iaddr, t.insn, rd, rf_wdata) } .elsewhen (wxd && rd =/= 0.U && !has_data) { printf ("%d 0x%x (0x%x) x%d p%d 0xXXXXXXXXXXXXXXXX\n", t.priv, t.iaddr, t.insn, rd, rd) } .otherwise { printf ("%d 0x%x (0x%x)\n", t.priv, t.iaddr, t.insn) } } when (ll_wen && rf_waddr =/= 0.U) { printf ("x%d p%d 0x%x\n", rf_waddr, rf_waddr, rf_wdata) } } else { when (csr.io.trace(0).valid) { printf("C%d: %d [%d] pc=[%x] W[r%d=%x][%d] R[r%d=%x] R[r%d=%x] inst=[%x] DASM(%x)\n", io.hartid, coreMonitorBundle.timer, coreMonitorBundle.valid, coreMonitorBundle.pc, Mux(wb_ctrl.wxd || wb_ctrl.wfd, coreMonitorBundle.wrdst, 0.U), Mux(coreMonitorBundle.wrenx, coreMonitorBundle.wrdata, 0.U), coreMonitorBundle.wrenx, Mux(wb_ctrl.rxs1 || wb_ctrl.rfs1, coreMonitorBundle.rd0src, 0.U), Mux(wb_ctrl.rxs1 || wb_ctrl.rfs1, coreMonitorBundle.rd0val, 0.U), Mux(wb_ctrl.rxs2 || wb_ctrl.rfs2, coreMonitorBundle.rd1src, 0.U), Mux(wb_ctrl.rxs2 || wb_ctrl.rfs2, coreMonitorBundle.rd1val, 0.U), coreMonitorBundle.inst, coreMonitorBundle.inst) } } // CoreMonitorBundle for late latency writes val xrfWriteBundle = Wire(new CoreMonitorBundle(xLen, fLen)) xrfWriteBundle.clock := clock xrfWriteBundle.reset := reset xrfWriteBundle.hartid := io.hartid xrfWriteBundle.timer := csr.io.time(31,0) xrfWriteBundle.valid := false.B xrfWriteBundle.pc := 0.U xrfWriteBundle.wrdst := rf_waddr xrfWriteBundle.wrenx := rf_wen && !(csr.io.trace(0).valid && wb_wen && (wb_waddr === rf_waddr)) xrfWriteBundle.wrenf := false.B xrfWriteBundle.wrdata := rf_wdata xrfWriteBundle.rd0src := 0.U xrfWriteBundle.rd0val := 0.U xrfWriteBundle.rd1src := 0.U xrfWriteBundle.rd1val := 0.U xrfWriteBundle.inst := 0.U xrfWriteBundle.excpt := false.B xrfWriteBundle.priv_mode := csr.io.trace(0).priv if (rocketParams.haveSimTimeout) PlusArg.timeout( name = "max_core_cycles", docstring = "Kill the emulation after INT rdtime cycles. Off if 0." )(csr.io.time) } // leaving gated-clock domain val rocketImpl = withClock (gated_clock) { new RocketImpl } def checkExceptions(x: Seq[(Bool, UInt)]) = (WireInit(x.map(_._1).reduce(_||_)), WireInit(PriorityMux(x))) def coverExceptions(exceptionValid: Bool, cause: UInt, labelPrefix: String, coverCausesLabels: Seq[(Int, String)]): Unit = { for ((coverCause, label) <- coverCausesLabels) { property.cover(exceptionValid && (cause === coverCause.U), s"${labelPrefix}_${label}") } } def checkHazards(targets: Seq[(Bool, UInt)], cond: UInt => Bool) = targets.map(h => h._1 && cond(h._2)).reduce(_||_) def encodeVirtualAddress(a0: UInt, ea: UInt) = if (vaddrBitsExtended == vaddrBits) ea else { // efficient means to compress 64-bit VA into vaddrBits+1 bits // (VA is bad if VA(vaddrBits) != VA(vaddrBits-1)) val b = vaddrBitsExtended-1 val a = (a0 >> b).asSInt val msb = Mux(a === 0.S || a === -1.S, ea(b), !ea(b-1)) Cat(msb, ea(b-1, 0)) } class Scoreboard(n: Int, zero: Boolean = false) { def set(en: Bool, addr: UInt): Unit = update(en, _next | mask(en, addr)) def clear(en: Bool, addr: UInt): Unit = update(en, _next & ~mask(en, addr)) def read(addr: UInt): Bool = r(addr) def readBypassed(addr: UInt): Bool = _next(addr) private val _r = RegInit(0.U(n.W)) private val r = if (zero) (_r >> 1 << 1) else _r private var _next = r private var ens = false.B private def mask(en: Bool, addr: UInt) = Mux(en, 1.U << addr, 0.U) private def update(en: Bool, update: UInt) = { _next = update ens = ens || en when (ens) { _r := _next } } } } class RegFile(n: Int, w: Int, zero: Boolean = false) { val rf = Mem(n, UInt(w.W)) private def access(addr: UInt) = rf(~addr(log2Up(n)-1,0)) private val reads = ArrayBuffer[(UInt,UInt)]() private var canRead = true def read(addr: UInt) = { require(canRead) reads += addr -> Wire(UInt()) reads.last._2 := Mux(zero.B && addr === 0.U, 0.U, access(addr)) reads.last._2 } def write(addr: UInt, data: UInt) = { canRead = false when (addr =/= 0.U) { access(addr) := data for ((raddr, rdata) <- reads) when (addr === raddr) { rdata := data } } } } object ImmGen { def apply(sel: UInt, inst: UInt) = { val sign = Mux(sel === IMM_Z, 0.S, inst(31).asSInt) val b30_20 = Mux(sel === IMM_U, inst(30,20).asSInt, sign) val b19_12 = Mux(sel =/= IMM_U && sel =/= IMM_UJ, sign, inst(19,12).asSInt) val b11 = Mux(sel === IMM_U || sel === IMM_Z, 0.S, Mux(sel === IMM_UJ, inst(20).asSInt, Mux(sel === IMM_SB, inst(7).asSInt, sign))) val b10_5 = Mux(sel === IMM_U || sel === IMM_Z, 0.U, inst(30,25)) val b4_1 = Mux(sel === IMM_U, 0.U, Mux(sel === IMM_S || sel === IMM_SB, inst(11,8), Mux(sel === IMM_Z, inst(19,16), inst(24,21)))) val b0 = Mux(sel === IMM_S, inst(7), Mux(sel === IMM_I, inst(20), Mux(sel === IMM_Z, inst(15), 0.U))) Cat(sign, b30_20, b19_12, b11, b10_5, b4_1, b0).asSInt } }

module Rocket( // @[RocketCore.scala:153:7] input clock, // @[RocketCore.scala:153:7] input reset, // @[RocketCore.scala:153:7] input [1:0] io_hartid, // @[RocketCore.scala:134:14] input io_interrupts_debug, // @[RocketCore.scala:134:14] input io_interrupts_mtip, // @[RocketCore.scala:134:14] input io_interrupts_msip, // @[RocketCore.scala:134:14] input io_interrupts_meip, // @[RocketCore.scala:134:14] input io_interrupts_seip, // @[RocketCore.scala:134:14] output io_imem_might_request, // @[RocketCore.scala:134:14] output io_imem_req_valid, // @[RocketCore.scala:134:14] output [39:0] io_imem_req_bits_pc, // @[RocketCore.scala:134:14] output io_imem_req_bits_speculative, // @[RocketCore.scala:134:14] output io_imem_sfence_valid, // @[RocketCore.scala:134:14] output io_imem_sfence_bits_rs1, // @[RocketCore.scala:134:14] output io_imem_sfence_bits_rs2, // @[RocketCore.scala:134:14] output [38:0] io_imem_sfence_bits_addr, // @[RocketCore.scala:134:14] output io_imem_resp_ready, // @[RocketCore.scala:134:14] input io_imem_resp_valid, // @[RocketCore.scala:134:14] input io_imem_resp_bits_btb_taken, // @[RocketCore.scala:134:14] input io_imem_resp_bits_btb_bridx, // @[RocketCore.scala:134:14] input [4:0] io_imem_resp_bits_btb_entry, // @[RocketCore.scala:134:14] input [7:0] io_imem_resp_bits_btb_bht_history, // @[RocketCore.scala:134:14] input [39:0] io_imem_resp_bits_pc, // @[RocketCore.scala:134:14] input [31:0] io_imem_resp_bits_data, // @[RocketCore.scala:134:14] input io_imem_resp_bits_xcpt_pf_inst, // @[RocketCore.scala:134:14] input io_imem_resp_bits_xcpt_gf_inst, // @[RocketCore.scala:134:14] input io_imem_resp_bits_xcpt_ae_inst, // @[RocketCore.scala:134:14] input io_imem_resp_bits_replay, // @[RocketCore.scala:134:14] output io_imem_btb_update_valid, // @[RocketCore.scala:134:14] output [4:0] io_imem_btb_update_bits_prediction_entry, // @[RocketCore.scala:134:14] output [38:0] io_imem_btb_update_bits_pc, // @[RocketCore.scala:134:14] output io_imem_btb_update_bits_isValid, // @[RocketCore.scala:134:14] output [38:0] io_imem_btb_update_bits_br_pc, // @[RocketCore.scala:134:14] output [1:0] io_imem_btb_update_bits_cfiType, // @[RocketCore.scala:134:14] output io_imem_bht_update_valid, // @[RocketCore.scala:134:14] output [7:0] io_imem_bht_update_bits_prediction_history, // @[RocketCore.scala:134:14] output [38:0] io_imem_bht_update_bits_pc, // @[RocketCore.scala:134:14] output io_imem_bht_update_bits_branch, // @[RocketCore.scala:134:14] output io_imem_bht_update_bits_taken, // @[RocketCore.scala:134:14] output io_imem_bht_update_bits_mispredict, // @[RocketCore.scala:134:14] output io_imem_flush_icache, // @[RocketCore.scala:134:14] output io_imem_progress, // @[RocketCore.scala:134:14] input io_dmem_req_ready, // @[RocketCore.scala:134:14] output io_dmem_req_valid, // @[RocketCore.scala:134:14] output [39:0] io_dmem_req_bits_addr, // @[RocketCore.scala:134:14] output [6:0] io_dmem_req_bits_tag, // @[RocketCore.scala:134:14] output [4:0] io_dmem_req_bits_cmd, // @[RocketCore.scala:134:14] output [1:0] io_dmem_req_bits_size, // @[RocketCore.scala:134:14] output io_dmem_req_bits_signed, // @[RocketCore.scala:134:14] output [1:0] io_dmem_req_bits_dprv, // @[RocketCore.scala:134:14] output io_dmem_req_bits_dv, // @[RocketCore.scala:134:14] output io_dmem_s1_kill, // @[RocketCore.scala:134:14] output [63:0] io_dmem_s1_data_data, // @[RocketCore.scala:134:14] input io_dmem_s2_nack, // @[RocketCore.scala:134:14] input io_dmem_resp_valid, // @[RocketCore.scala:134:14] input [6:0] io_dmem_resp_bits_tag, // @[RocketCore.scala:134:14] input [1:0] io_dmem_resp_bits_size, // @[RocketCore.scala:134:14] input [63:0] io_dmem_resp_bits_data, // @[RocketCore.scala:134:14] input io_dmem_resp_bits_replay, // @[RocketCore.scala:134:14] input io_dmem_resp_bits_has_data, // @[RocketCore.scala:134:14] input [63:0] io_dmem_resp_bits_data_word_bypass, // @[RocketCore.scala:134:14] input io_dmem_replay_next, // @[RocketCore.scala:134:14] input io_dmem_s2_xcpt_ma_ld, // @[RocketCore.scala:134:14] input io_dmem_s2_xcpt_ma_st, // @[RocketCore.scala:134:14] input io_dmem_s2_xcpt_pf_ld, // @[RocketCore.scala:134:14] input io_dmem_s2_xcpt_pf_st, // @[RocketCore.scala:134:14] input io_dmem_s2_xcpt_ae_ld, // @[RocketCore.scala:134:14] input io_dmem_s2_xcpt_ae_st, // @[RocketCore.scala:134:14] input io_dmem_ordered, // @[RocketCore.scala:134:14] input io_dmem_perf_release, // @[RocketCore.scala:134:14] input io_dmem_perf_grant, // @[RocketCore.scala:134:14] output [3:0] io_ptw_ptbr_mode, // @[RocketCore.scala:134:14] output [43:0] io_ptw_ptbr_ppn, // @[RocketCore.scala:134:14] output io_ptw_sfence_valid, // @[RocketCore.scala:134:14] output io_ptw_sfence_bits_rs1, // @[RocketCore.scala:134:14] output io_ptw_status_debug, // @[RocketCore.scala:134:14] output [1:0] io_ptw_status_prv, // @[RocketCore.scala:134:14] output io_ptw_status_mxr, // @[RocketCore.scala:134:14] output io_ptw_status_sum, // @[RocketCore.scala:134:14] output io_ptw_pmp_0_cfg_l, // @[RocketCore.scala:134:14] output [1:0] io_ptw_pmp_0_cfg_a, // @[RocketCore.scala:134:14] output io_ptw_pmp_0_cfg_x, // @[RocketCore.scala:134:14] output io_ptw_pmp_0_cfg_w, // @[RocketCore.scala:134:14] output io_ptw_pmp_0_cfg_r, // @[RocketCore.scala:134:14] output [29:0] io_ptw_pmp_0_addr, // @[RocketCore.scala:134:14] output [31:0] io_ptw_pmp_0_mask, // @[RocketCore.scala:134:14] output io_ptw_pmp_1_cfg_l, // @[RocketCore.scala:134:14] output [1:0] io_ptw_pmp_1_cfg_a, // @[RocketCore.scala:134:14] output io_ptw_pmp_1_cfg_x, // @[RocketCore.scala:134:14] output io_ptw_pmp_1_cfg_w, // @[RocketCore.scala:134:14] output io_ptw_pmp_1_cfg_r, // @[RocketCore.scala:134:14] output [29:0] io_ptw_pmp_1_addr, // @[RocketCore.scala:134:14] output [31:0] io_ptw_pmp_1_mask, // @[RocketCore.scala:134:14] output io_ptw_pmp_2_cfg_l, // @[RocketCore.scala:134:14] output [1:0] io_ptw_pmp_2_cfg_a, // @[RocketCore.scala:134:14] output io_ptw_pmp_2_cfg_x, // @[RocketCore.scala:134:14] output io_ptw_pmp_2_cfg_w, // @[RocketCore.scala:134:14] output io_ptw_pmp_2_cfg_r, // @[RocketCore.scala:134:14] output [29:0] io_ptw_pmp_2_addr, // @[RocketCore.scala:134:14] output [31:0] io_ptw_pmp_2_mask, // @[RocketCore.scala:134:14] output io_ptw_pmp_3_cfg_l, // @[RocketCore.scala:134:14] output [1:0] io_ptw_pmp_3_cfg_a, // @[RocketCore.scala:134:14] output io_ptw_pmp_3_cfg_x, // @[RocketCore.scala:134:14] output io_ptw_pmp_3_cfg_w, // @[RocketCore.scala:134:14] output io_ptw_pmp_3_cfg_r, // @[RocketCore.scala:134:14] output [29:0] io_ptw_pmp_3_addr, // @[RocketCore.scala:134:14] output [31:0] io_ptw_pmp_3_mask, // @[RocketCore.scala:134:14] output io_ptw_pmp_4_cfg_l, // @[RocketCore.scala:134:14] output [1:0] io_ptw_pmp_4_cfg_a, // @[RocketCore.scala:134:14] output io_ptw_pmp_4_cfg_x, // @[RocketCore.scala:134:14] output io_ptw_pmp_4_cfg_w, // @[RocketCore.scala:134:14] output io_ptw_pmp_4_cfg_r, // @[RocketCore.scala:134:14] output [29:0] io_ptw_pmp_4_addr, // @[RocketCore.scala:134:14] output [31:0] io_ptw_pmp_4_mask, // @[RocketCore.scala:134:14] output io_ptw_pmp_5_cfg_l, // @[RocketCore.scala:134:14] output [1:0] io_ptw_pmp_5_cfg_a, // @[RocketCore.scala:134:14] output io_ptw_pmp_5_cfg_x, // @[RocketCore.scala:134:14] output io_ptw_pmp_5_cfg_w, // @[RocketCore.scala:134:14] output io_ptw_pmp_5_cfg_r, // @[RocketCore.scala:134:14] output [29:0] io_ptw_pmp_5_addr, // @[RocketCore.scala:134:14] output [31:0] io_ptw_pmp_5_mask, // @[RocketCore.scala:134:14] output io_ptw_pmp_6_cfg_l, // @[RocketCore.scala:134:14] output [1:0] io_ptw_pmp_6_cfg_a, // @[RocketCore.scala:134:14] output io_ptw_pmp_6_cfg_x, // @[RocketCore.scala:134:14] output io_ptw_pmp_6_cfg_w, // @[RocketCore.scala:134:14] output io_ptw_pmp_6_cfg_r, // @[RocketCore.scala:134:14] output [29:0] io_ptw_pmp_6_addr, // @[RocketCore.scala:134:14] output [31:0] io_ptw_pmp_6_mask, // @[RocketCore.scala:134:14] output io_ptw_pmp_7_cfg_l, // @[RocketCore.scala:134:14] output [1:0] io_ptw_pmp_7_cfg_a, // @[RocketCore.scala:134:14] output io_ptw_pmp_7_cfg_x, // @[RocketCore.scala:134:14] output io_ptw_pmp_7_cfg_w, // @[RocketCore.scala:134:14] output io_ptw_pmp_7_cfg_r, // @[RocketCore.scala:134:14] output [29:0] io_ptw_pmp_7_addr, // @[RocketCore.scala:134:14] output [31:0] io_ptw_pmp_7_mask, // @[RocketCore.scala:134:14] output [63:0] io_ptw_customCSRs_csrs_0_value, // @[RocketCore.scala:134:14] output [31:0] io_fpu_inst, // @[RocketCore.scala:134:14] output [63:0] io_fpu_fromint_data, // @[RocketCore.scala:134:14] output [2:0] io_fpu_fcsr_rm, // @[RocketCore.scala:134:14] input io_fpu_fcsr_flags_valid, // @[RocketCore.scala:134:14] input [4:0] io_fpu_fcsr_flags_bits, // @[RocketCore.scala:134:14] input [63:0] io_fpu_store_data, // @[RocketCore.scala:134:14] input [63:0] io_fpu_toint_data, // @[RocketCore.scala:134:14] output io_fpu_ll_resp_val, // @[RocketCore.scala:134:14] output [2:0] io_fpu_ll_resp_type, // @[RocketCore.scala:134:14] output [4:0] io_fpu_ll_resp_tag, // @[RocketCore.scala:134:14] output [63:0] io_fpu_ll_resp_data, // @[RocketCore.scala:134:14] output io_fpu_valid, // @[RocketCore.scala:134:14] input io_fpu_fcsr_rdy, // @[RocketCore.scala:134:14] input io_fpu_nack_mem, // @[RocketCore.scala:134:14] input io_fpu_illegal_rm, // @[RocketCore.scala:134:14] output io_fpu_killx, // @[RocketCore.scala:134:14] output io_fpu_killm, // @[RocketCore.scala:134:14] input io_fpu_dec_wen, // @[RocketCore.scala:134:14] input io_fpu_dec_ren1, // @[RocketCore.scala:134:14] input io_fpu_dec_ren2, // @[RocketCore.scala:134:14] input io_fpu_dec_ren3, // @[RocketCore.scala:134:14] input io_fpu_sboard_set, // @[RocketCore.scala:134:14] input io_fpu_sboard_clr, // @[RocketCore.scala:134:14] input [4:0] io_fpu_sboard_clra, // @[RocketCore.scala:134:14] output io_wfi // @[RocketCore.scala:134:14] ); wire io_dmem_req_valid_0; // @[RocketCore.scala:1130:41] wire ll_arb_io_out_ready; // @[RocketCore.scala:782:23, :809:44, :810:25] wire take_pc_wb; // @[RocketCore.scala:762:{27,38,53}] wire take_pc_mem; // @[RocketCore.scala:629:{32,49}] wire _ll_arb_io_in_0_ready; // @[RocketCore.scala:776:22] wire _ll_arb_io_out_valid; // @[RocketCore.scala:776:22] wire [63:0] _ll_arb_io_out_bits_data; // @[RocketCore.scala:776:22] wire [4:0] _ll_arb_io_out_bits_tag; // @[RocketCore.scala:776:22] wire _div_io_req_ready; // @[RocketCore.scala:511:19] wire _div_io_resp_valid; // @[RocketCore.scala:511:19] wire [63:0] _div_io_resp_bits_data; // @[RocketCore.scala:511:19] wire [4:0] _div_io_resp_bits_tag; // @[RocketCore.scala:511:19] wire [63:0] _alu_io_out; // @[RocketCore.scala:504:19] wire [63:0] _alu_io_adder_out; // @[RocketCore.scala:504:19] wire _alu_io_cmp_out; // @[RocketCore.scala:504:19] wire _bpu_io_xcpt_if; // @[RocketCore.scala:414:19] wire _bpu_io_xcpt_ld; // @[RocketCore.scala:414:19] wire _bpu_io_xcpt_st; // @[RocketCore.scala:414:19] wire _bpu_io_debug_if; // @[RocketCore.scala:414:19] wire _bpu_io_debug_ld; // @[RocketCore.scala:414:19] wire _bpu_io_debug_st; // @[RocketCore.scala:414:19] wire [63:0] _csr_io_rw_rdata; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_fp_illegal; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_fp_csr; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_read_illegal; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_write_illegal; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_write_flush; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_system_illegal; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_virtual_access_illegal; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_virtual_system_illegal; // @[RocketCore.scala:341:19] wire _csr_io_csr_stall; // @[RocketCore.scala:341:19] wire _csr_io_eret; // @[RocketCore.scala:341:19] wire _csr_io_singleStep; // @[RocketCore.scala:341:19] wire _csr_io_status_debug; // @[RocketCore.scala:341:19] wire [31:0] _csr_io_status_isa; // @[RocketCore.scala:341:19] wire _csr_io_status_dv; // @[RocketCore.scala:341:19] wire [1:0] _csr_io_status_prv; // @[RocketCore.scala:341:19] wire _csr_io_status_v; // @[RocketCore.scala:341:19] wire [39:0] _csr_io_evec; // @[RocketCore.scala:341:19] wire [63:0] _csr_io_time; // @[RocketCore.scala:341:19] wire _csr_io_interrupt; // @[RocketCore.scala:341:19] wire [63:0] _csr_io_interrupt_cause; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_control_action; // @[RocketCore.scala:341:19] wire [1:0] _csr_io_bp_0_control_tmatch; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_control_m; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_control_s; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_control_u; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_control_x; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_control_w; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_control_r; // @[RocketCore.scala:341:19] wire [38:0] _csr_io_bp_0_address; // @[RocketCore.scala:341:19] wire _csr_io_inhibit_cycle; // @[RocketCore.scala:341:19] wire _csr_io_trace_0_valid; // @[RocketCore.scala:341:19] wire [39:0] _csr_io_trace_0_iaddr; // @[RocketCore.scala:341:19] wire [31:0] _csr_io_trace_0_insn; // @[RocketCore.scala:341:19] wire _csr_io_trace_0_exception; // @[RocketCore.scala:341:19] wire [63:0] _csr_io_customCSRs_0_value; // @[RocketCore.scala:341:19] wire [63:0] _rf_ext_R0_data; // @[RocketCore.scala:1319:15] wire [63:0] _rf_ext_R1_data; // @[RocketCore.scala:1319:15] wire [39:0] _ibuf_io_pc; // @[RocketCore.scala:311:20] wire [4:0] _ibuf_io_btb_resp_entry; // @[RocketCore.scala:311:20] wire [7:0] _ibuf_io_btb_resp_bht_history; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_valid; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_bits_xcpt0_pf_inst; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_bits_xcpt0_gf_inst; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_bits_xcpt0_ae_inst; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_bits_xcpt1_pf_inst; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_bits_xcpt1_gf_inst; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_bits_xcpt1_ae_inst; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_bits_replay; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_bits_rvc; // @[RocketCore.scala:311:20] wire [31:0] _ibuf_io_inst_0_bits_inst_bits; // @[RocketCore.scala:311:20] wire [4:0] _ibuf_io_inst_0_bits_inst_rd; // @[RocketCore.scala:311:20] wire [4:0] _ibuf_io_inst_0_bits_inst_rs1; // @[RocketCore.scala:311:20] wire [4:0] _ibuf_io_inst_0_bits_inst_rs2; // @[RocketCore.scala:311:20] wire [4:0] _ibuf_io_inst_0_bits_inst_rs3; // @[RocketCore.scala:311:20] wire [31:0] _ibuf_io_inst_0_bits_raw; // @[RocketCore.scala:311:20] reg id_reg_pause; // @[RocketCore.scala:161:25] reg imem_might_request_reg; // @[RocketCore.scala:162:35] reg ex_ctrl_fp; // @[RocketCore.scala:243:20] reg ex_ctrl_rocc; // @[RocketCore.scala:243:20] reg ex_ctrl_branch; // @[RocketCore.scala:243:20] reg ex_ctrl_jal; // @[RocketCore.scala:243:20] reg ex_ctrl_jalr; // @[RocketCore.scala:243:20] reg ex_ctrl_rxs2; // @[RocketCore.scala:243:20] reg ex_ctrl_rxs1; // @[RocketCore.scala:243:20] reg [2:0] ex_ctrl_sel_alu2; // @[RocketCore.scala:243:20] reg [1:0] ex_ctrl_sel_alu1; // @[RocketCore.scala:243:20] reg [2:0] ex_ctrl_sel_imm; // @[RocketCore.scala:243:20] reg ex_ctrl_alu_dw; // @[RocketCore.scala:243:20] reg [4:0] ex_ctrl_alu_fn; // @[RocketCore.scala:243:20] reg ex_ctrl_mem; // @[RocketCore.scala:243:20] reg [4:0] ex_ctrl_mem_cmd; // @[RocketCore.scala:243:20] reg ex_ctrl_rfs1; // @[RocketCore.scala:243:20] reg ex_ctrl_rfs2; // @[RocketCore.scala:243:20] reg ex_ctrl_wfd; // @[RocketCore.scala:243:20] reg ex_ctrl_mul; // @[RocketCore.scala:243:20] reg ex_ctrl_div; // @[RocketCore.scala:243:20] reg ex_ctrl_wxd; // @[RocketCore.scala:243:20] reg [2:0] ex_ctrl_csr; // @[RocketCore.scala:243:20] reg ex_ctrl_fence_i; // @[RocketCore.scala:243:20] reg mem_ctrl_fp; // @[RocketCore.scala:244:21] reg mem_ctrl_rocc; // @[RocketCore.scala:244:21] reg mem_ctrl_branch; // @[RocketCore.scala:244:21] reg mem_ctrl_jal; // @[RocketCore.scala:244:21] reg mem_ctrl_jalr; // @[RocketCore.scala:244:21] reg mem_ctrl_rxs2; // @[RocketCore.scala:244:21] reg mem_ctrl_rxs1; // @[RocketCore.scala:244:21] reg mem_ctrl_mem; // @[RocketCore.scala:244:21] reg mem_ctrl_rfs1; // @[RocketCore.scala:244:21] reg mem_ctrl_rfs2; // @[RocketCore.scala:244:21] reg mem_ctrl_wfd; // @[RocketCore.scala:244:21] reg mem_ctrl_mul; // @[RocketCore.scala:244:21] reg mem_ctrl_div; // @[RocketCore.scala:244:21] reg mem_ctrl_wxd; // @[RocketCore.scala:244:21] reg [2:0] mem_ctrl_csr; // @[RocketCore.scala:244:21] reg mem_ctrl_fence_i; // @[RocketCore.scala:244:21] reg mem_ctrl_vec; // @[RocketCore.scala:244:21] reg wb_ctrl_rocc; // @[RocketCore.scala:245:20] reg wb_ctrl_rxs2; // @[RocketCore.scala:245:20] reg wb_ctrl_rxs1; // @[RocketCore.scala:245:20] reg wb_ctrl_mem; // @[RocketCore.scala:245:20] reg wb_ctrl_rfs1; // @[RocketCore.scala:245:20] reg wb_ctrl_rfs2; // @[RocketCore.scala:245:20] reg wb_ctrl_wfd; // @[RocketCore.scala:245:20] reg wb_ctrl_div; // @[RocketCore.scala:245:20] reg wb_ctrl_wxd; // @[RocketCore.scala:245:20] reg [2:0] wb_ctrl_csr; // @[RocketCore.scala:245:20] reg wb_ctrl_fence_i; // @[RocketCore.scala:245:20] reg wb_ctrl_vec; // @[RocketCore.scala:245:20] reg ex_reg_xcpt_interrupt; // @[RocketCore.scala:247:35] reg ex_reg_valid; // @[RocketCore.scala:248:35] reg ex_reg_rvc; // @[RocketCore.scala:249:35] reg [4:0] ex_reg_btb_resp_entry; // @[RocketCore.scala:250:35] reg [7:0] ex_reg_btb_resp_bht_history; // @[RocketCore.scala:250:35] reg ex_reg_xcpt; // @[RocketCore.scala:251:35] reg ex_reg_flush_pipe; // @[RocketCore.scala:252:35] reg ex_reg_load_use; // @[RocketCore.scala:253:35] reg [63:0] ex_reg_cause; // @[RocketCore.scala:254:35] reg ex_reg_replay; // @[RocketCore.scala:255:26] reg [39:0] ex_reg_pc; // @[RocketCore.scala:256:22] reg [1:0] ex_reg_mem_size; // @[RocketCore.scala:257:28] reg [31:0] ex_reg_inst; // @[RocketCore.scala:259:24] reg [31:0] ex_reg_raw_inst; // @[RocketCore.scala:260:28] reg mem_reg_xcpt_interrupt; // @[RocketCore.scala:264:36] reg mem_reg_valid; // @[RocketCore.scala:265:36] reg mem_reg_rvc; // @[RocketCore.scala:266:36] reg [4:0] mem_reg_btb_resp_entry; // @[RocketCore.scala:267:36] reg [7:0] mem_reg_btb_resp_bht_history; // @[RocketCore.scala:267:36] reg mem_reg_xcpt; // @[RocketCore.scala:268:36] reg mem_reg_replay; // @[RocketCore.scala:269:36] reg mem_reg_flush_pipe; // @[RocketCore.scala:270:36] reg [63:0] mem_reg_cause; // @[RocketCore.scala:271:36] reg mem_mem_cmd_bh; // @[RocketCore.scala:272:36] reg mem_reg_load; // @[RocketCore.scala:273:36] reg mem_reg_store; // @[RocketCore.scala:274:36] reg mem_reg_sfence; // @[RocketCore.scala:276:27] reg [39:0] mem_reg_pc; // @[RocketCore.scala:277:23] reg [31:0] mem_reg_inst; // @[RocketCore.scala:278:25] reg [1:0] mem_reg_mem_size; // @[RocketCore.scala:279:29] reg mem_reg_hls_or_dv; // @[RocketCore.scala:280:30] reg [31:0] mem_reg_raw_inst; // @[RocketCore.scala:281:29] reg [63:0] mem_reg_wdata; // @[RocketCore.scala:282:26] reg [63:0] mem_reg_rs2; // @[RocketCore.scala:283:24] reg mem_br_taken; // @[RocketCore.scala:284:25] reg wb_reg_valid; // @[RocketCore.scala:288:35] reg wb_reg_xcpt; // @[RocketCore.scala:289:35] reg wb_reg_replay; // @[RocketCore.scala:290:35] reg wb_reg_flush_pipe; // @[RocketCore.scala:291:35] reg [63:0] wb_reg_cause; // @[RocketCore.scala:292:35] reg wb_reg_sfence; // @[RocketCore.scala:294:26] reg [39:0] wb_reg_pc; // @[RocketCore.scala:295:22] reg [1:0] wb_reg_mem_size; // @[RocketCore.scala:296:28] reg wb_reg_hls_or_dv; // @[RocketCore.scala:297:29] reg [31:0] wb_reg_inst; // @[RocketCore.scala:300:24] reg [31:0] wb_reg_raw_inst; // @[RocketCore.scala:301:28] reg [63:0] wb_reg_wdata; // @[RocketCore.scala:302:25] wire ibuf_io_kill = take_pc_wb | take_pc_mem; // @[RocketCore.scala:307:35, :629:{32,49}, :762:{27,38,53}] wire [29:0] id_ctrl_decoder_decoded_invInputs = ~(_ibuf_io_inst_0_bits_inst_bits[31:2]); // @[pla.scala:78:21] wire [6:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], id_ctrl_decoder_decoded_invInputs[3], id_ctrl_decoder_decoded_invInputs[4], id_ctrl_decoder_decoded_invInputs[10]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_2 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], id_ctrl_decoder_decoded_invInputs[2], id_ctrl_decoder_decoded_invInputs[3], id_ctrl_decoder_decoded_invInputs[4], id_ctrl_decoder_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [6:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_3 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], id_ctrl_decoder_decoded_invInputs[2], id_ctrl_decoder_decoded_invInputs[4], id_ctrl_decoder_decoded_invInputs[12]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_6 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], id_ctrl_decoder_decoded_invInputs[4], id_ctrl_decoder_decoded_invInputs[10], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [5:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_7 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], _ibuf_io_inst_0_bits_inst_bits[2], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[4]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_9 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], id_ctrl_decoder_decoded_invInputs[2], _ibuf_io_inst_0_bits_inst_bits[5], id_ctrl_decoder_decoded_invInputs[4], id_ctrl_decoder_decoded_invInputs[12]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_12 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], _ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], id_ctrl_decoder_decoded_invInputs[4], id_ctrl_decoder_decoded_invInputs[10], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], id_ctrl_decoder_decoded_invInputs[27], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [12:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_13 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], id_ctrl_decoder_decoded_invInputs[4], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], id_ctrl_decoder_decoded_invInputs[27], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_14 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], _ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], id_ctrl_decoder_decoded_invInputs[4], id_ctrl_decoder_decoded_invInputs[10], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], id_ctrl_decoder_decoded_invInputs[27], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_16 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], _ibuf_io_inst_0_bits_inst_bits[3], _ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], id_ctrl_decoder_decoded_invInputs[4], id_ctrl_decoder_decoded_invInputs[10], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[26], id_ctrl_decoder_decoded_invInputs[27], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [4:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_17 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[2], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [10:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_20 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[27], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [10:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_21 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[27], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_24 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[1], id_ctrl_decoder_decoded_invInputs[2], _ibuf_io_inst_0_bits_inst_bits[5], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[10], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [9:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_25 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], _ibuf_io_inst_0_bits_inst_bits[2], id_ctrl_decoder_decoded_invInputs[1], id_ctrl_decoder_decoded_invInputs[2], _ibuf_io_inst_0_bits_inst_bits[5], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[10], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [6:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_26 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], _ibuf_io_inst_0_bits_inst_bits[2], _ibuf_io_inst_0_bits_inst_bits[3], id_ctrl_decoder_decoded_invInputs[2], _ibuf_io_inst_0_bits_inst_bits[5], _ibuf_io_inst_0_bits_inst_bits[6]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [6:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_29 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[1], id_ctrl_decoder_decoded_invInputs[2], id_ctrl_decoder_decoded_invInputs[4], _ibuf_io_inst_0_bits_inst_bits[12], id_ctrl_decoder_decoded_invInputs[12]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [9:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_33 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], _ibuf_io_inst_0_bits_inst_bits[2], _ibuf_io_inst_0_bits_inst_bits[3], id_ctrl_decoder_decoded_invInputs[2], id_ctrl_decoder_decoded_invInputs[3], id_ctrl_decoder_decoded_invInputs[4], _ibuf_io_inst_0_bits_inst_bits[12], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_34 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[4], _ibuf_io_inst_0_bits_inst_bits[12], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], id_ctrl_decoder_decoded_invInputs[27], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_36 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], _ibuf_io_inst_0_bits_inst_bits[3], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[4], _ibuf_io_inst_0_bits_inst_bits[12], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], id_ctrl_decoder_decoded_invInputs[27], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_42 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[5], _ibuf_io_inst_0_bits_inst_bits[6], _ibuf_io_inst_0_bits_inst_bits[12], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_43 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], _ibuf_io_inst_0_bits_inst_bits[6], _ibuf_io_inst_0_bits_inst_bits[12]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [6:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_44 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[1], id_ctrl_decoder_decoded_invInputs[2], id_ctrl_decoder_decoded_invInputs[4], _ibuf_io_inst_0_bits_inst_bits[13], id_ctrl_decoder_decoded_invInputs[12]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_48 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], id_ctrl_decoder_decoded_invInputs[4], _ibuf_io_inst_0_bits_inst_bits[13]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [10:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_52 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], _ibuf_io_inst_0_bits_inst_bits[2], _ibuf_io_inst_0_bits_inst_bits[3], id_ctrl_decoder_decoded_invInputs[2], _ibuf_io_inst_0_bits_inst_bits[5], id_ctrl_decoder_decoded_invInputs[4], _ibuf_io_inst_0_bits_inst_bits[13], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_55 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], _ibuf_io_inst_0_bits_inst_bits[6], _ibuf_io_inst_0_bits_inst_bits[13]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_56 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], _ibuf_io_inst_0_bits_inst_bits[6], _ibuf_io_inst_0_bits_inst_bits[13], id_ctrl_decoder_decoded_invInputs[12]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_61 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], id_ctrl_decoder_decoded_invInputs[4], _ibuf_io_inst_0_bits_inst_bits[14], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], id_ctrl_decoder_decoded_invInputs[27], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_63 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], id_ctrl_decoder_decoded_invInputs[2], _ibuf_io_inst_0_bits_inst_bits[5], _ibuf_io_inst_0_bits_inst_bits[6], _ibuf_io_inst_0_bits_inst_bits[14]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_84 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], id_ctrl_decoder_decoded_invInputs[4], _ibuf_io_inst_0_bits_inst_bits[14], _ibuf_io_inst_0_bits_inst_bits[25], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[26], id_ctrl_decoder_decoded_invInputs[27], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_85 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], _ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], id_ctrl_decoder_decoded_invInputs[4], _ibuf_io_inst_0_bits_inst_bits[14], _ibuf_io_inst_0_bits_inst_bits[25], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], id_ctrl_decoder_decoded_invInputs[27], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_89 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], _ibuf_io_inst_0_bits_inst_bits[3], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], id_ctrl_decoder_decoded_invInputs[4], _ibuf_io_inst_0_bits_inst_bits[12], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[24], _ibuf_io_inst_0_bits_inst_bits[27], id_ctrl_decoder_decoded_invInputs[26], id_ctrl_decoder_decoded_invInputs[27], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [12:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_90 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], _ibuf_io_inst_0_bits_inst_bits[2], _ibuf_io_inst_0_bits_inst_bits[3], id_ctrl_decoder_decoded_invInputs[2], _ibuf_io_inst_0_bits_inst_bits[5], id_ctrl_decoder_decoded_invInputs[4], _ibuf_io_inst_0_bits_inst_bits[13], id_ctrl_decoder_decoded_invInputs[12], _ibuf_io_inst_0_bits_inst_bits[27], id_ctrl_decoder_decoded_invInputs[27], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [21:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_91 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], _ibuf_io_inst_0_bits_inst_bits[3], _ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], id_ctrl_decoder_decoded_invInputs[4], id_ctrl_decoder_decoded_invInputs[10], id_ctrl_decoder_decoded_invInputs[11], _ibuf_io_inst_0_bits_inst_bits[14], id_ctrl_decoder_decoded_invInputs[18], id_ctrl_decoder_decoded_invInputs[19], id_ctrl_decoder_decoded_invInputs[20], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[24], _ibuf_io_inst_0_bits_inst_bits[27], id_ctrl_decoder_decoded_invInputs[26], id_ctrl_decoder_decoded_invInputs[27], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_95 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], _ibuf_io_inst_0_bits_inst_bits[2], _ibuf_io_inst_0_bits_inst_bits[3], id_ctrl_decoder_decoded_invInputs[2], _ibuf_io_inst_0_bits_inst_bits[5], id_ctrl_decoder_decoded_invInputs[4], id_ctrl_decoder_decoded_invInputs[18], id_ctrl_decoder_decoded_invInputs[19], id_ctrl_decoder_decoded_invInputs[20], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[25], _ibuf_io_inst_0_bits_inst_bits[28], id_ctrl_decoder_decoded_invInputs[27], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [18:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_96 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], _ibuf_io_inst_0_bits_inst_bits[2], _ibuf_io_inst_0_bits_inst_bits[3], id_ctrl_decoder_decoded_invInputs[2], _ibuf_io_inst_0_bits_inst_bits[5], id_ctrl_decoder_decoded_invInputs[4], _ibuf_io_inst_0_bits_inst_bits[13], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[18], id_ctrl_decoder_decoded_invInputs[19], id_ctrl_decoder_decoded_invInputs[20], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[25], _ibuf_io_inst_0_bits_inst_bits[28], id_ctrl_decoder_decoded_invInputs[27], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_101 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[5], id_ctrl_decoder_decoded_invInputs[6], id_ctrl_decoder_decoded_invInputs[7], _ibuf_io_inst_0_bits_inst_bits[25], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], _ibuf_io_inst_0_bits_inst_bits[28], id_ctrl_decoder_decoded_invInputs[27], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [17:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_102 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[5], id_ctrl_decoder_decoded_invInputs[6], id_ctrl_decoder_decoded_invInputs[7], id_ctrl_decoder_decoded_invInputs[12], _ibuf_io_inst_0_bits_inst_bits[25], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], _ibuf_io_inst_0_bits_inst_bits[28], id_ctrl_decoder_decoded_invInputs[27], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [21:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_104 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[5], id_ctrl_decoder_decoded_invInputs[6], id_ctrl_decoder_decoded_invInputs[7], id_ctrl_decoder_decoded_invInputs[8], id_ctrl_decoder_decoded_invInputs[9], id_ctrl_decoder_decoded_invInputs[10], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12], _ibuf_io_inst_0_bits_inst_bits[25], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], _ibuf_io_inst_0_bits_inst_bits[28], id_ctrl_decoder_decoded_invInputs[27], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_106 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[10], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], _ibuf_io_inst_0_bits_inst_bits[29], id_ctrl_decoder_decoded_invInputs[28]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_107 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], _ibuf_io_inst_0_bits_inst_bits[29], id_ctrl_decoder_decoded_invInputs[28]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_108 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[10], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], _ibuf_io_inst_0_bits_inst_bits[29], id_ctrl_decoder_decoded_invInputs[28]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_109 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], _ibuf_io_inst_0_bits_inst_bits[29], id_ctrl_decoder_decoded_invInputs[28]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_110 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[26], _ibuf_io_inst_0_bits_inst_bits[29], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_111 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[26], _ibuf_io_inst_0_bits_inst_bits[29], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_115 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], _ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], id_ctrl_decoder_decoded_invInputs[4], id_ctrl_decoder_decoded_invInputs[10], _ibuf_io_inst_0_bits_inst_bits[13], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], _ibuf_io_inst_0_bits_inst_bits[29], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_116 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], _ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], id_ctrl_decoder_decoded_invInputs[4], id_ctrl_decoder_decoded_invInputs[10], _ibuf_io_inst_0_bits_inst_bits[14], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], _ibuf_io_inst_0_bits_inst_bits[29], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_120 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], id_ctrl_decoder_decoded_invInputs[4], _ibuf_io_inst_0_bits_inst_bits[12], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[24], _ibuf_io_inst_0_bits_inst_bits[27], id_ctrl_decoder_decoded_invInputs[26], _ibuf_io_inst_0_bits_inst_bits[29], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_122 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], id_ctrl_decoder_decoded_invInputs[4], _ibuf_io_inst_0_bits_inst_bits[12], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[24], _ibuf_io_inst_0_bits_inst_bits[27], id_ctrl_decoder_decoded_invInputs[26], _ibuf_io_inst_0_bits_inst_bits[29], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [21:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_124 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], id_ctrl_decoder_decoded_invInputs[4], _ibuf_io_inst_0_bits_inst_bits[12], id_ctrl_decoder_decoded_invInputs[11], _ibuf_io_inst_0_bits_inst_bits[14], _ibuf_io_inst_0_bits_inst_bits[20], _ibuf_io_inst_0_bits_inst_bits[21], _ibuf_io_inst_0_bits_inst_bits[22], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[24], _ibuf_io_inst_0_bits_inst_bits[27], id_ctrl_decoder_decoded_invInputs[26], _ibuf_io_inst_0_bits_inst_bits[29], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_130 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], id_ctrl_decoder_decoded_invInputs[4], _ibuf_io_inst_0_bits_inst_bits[12], id_ctrl_decoder_decoded_invInputs[11], _ibuf_io_inst_0_bits_inst_bits[14], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], _ibuf_io_inst_0_bits_inst_bits[30], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_133 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], _ibuf_io_inst_0_bits_inst_bits[3], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[4], _ibuf_io_inst_0_bits_inst_bits[12], id_ctrl_decoder_decoded_invInputs[11], _ibuf_io_inst_0_bits_inst_bits[14], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], _ibuf_io_inst_0_bits_inst_bits[30], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_140 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], _ibuf_io_inst_0_bits_inst_bits[20], id_ctrl_decoder_decoded_invInputs[19], id_ctrl_decoder_decoded_invInputs[20], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], id_ctrl_decoder_decoded_invInputs[27], _ibuf_io_inst_0_bits_inst_bits[30]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_142 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[18], _ibuf_io_inst_0_bits_inst_bits[21], id_ctrl_decoder_decoded_invInputs[20], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], id_ctrl_decoder_decoded_invInputs[27], _ibuf_io_inst_0_bits_inst_bits[30]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_144 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[18], id_ctrl_decoder_decoded_invInputs[20], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], _ibuf_io_inst_0_bits_inst_bits[25], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], id_ctrl_decoder_decoded_invInputs[27], _ibuf_io_inst_0_bits_inst_bits[30]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_146 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[19], id_ctrl_decoder_decoded_invInputs[20], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[23], _ibuf_io_inst_0_bits_inst_bits[26], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], id_ctrl_decoder_decoded_invInputs[27], _ibuf_io_inst_0_bits_inst_bits[30]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_149 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], id_ctrl_decoder_decoded_invInputs[4], _ibuf_io_inst_0_bits_inst_bits[12], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[24], _ibuf_io_inst_0_bits_inst_bits[27], id_ctrl_decoder_decoded_invInputs[26], id_ctrl_decoder_decoded_invInputs[27], _ibuf_io_inst_0_bits_inst_bits[30], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_152 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], id_ctrl_decoder_decoded_invInputs[4], _ibuf_io_inst_0_bits_inst_bits[12], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[24], _ibuf_io_inst_0_bits_inst_bits[27], id_ctrl_decoder_decoded_invInputs[26], id_ctrl_decoder_decoded_invInputs[27], _ibuf_io_inst_0_bits_inst_bits[30], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [17:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_154 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[18], id_ctrl_decoder_decoded_invInputs[19], id_ctrl_decoder_decoded_invInputs[20], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[23], _ibuf_io_inst_0_bits_inst_bits[27], _ibuf_io_inst_0_bits_inst_bits[28], id_ctrl_decoder_decoded_invInputs[27], _ibuf_io_inst_0_bits_inst_bits[30], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [17:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_155 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[18], id_ctrl_decoder_decoded_invInputs[19], id_ctrl_decoder_decoded_invInputs[20], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[24], _ibuf_io_inst_0_bits_inst_bits[27], _ibuf_io_inst_0_bits_inst_bits[28], id_ctrl_decoder_decoded_invInputs[27], _ibuf_io_inst_0_bits_inst_bits[30], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_157 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], id_ctrl_decoder_decoded_invInputs[4], id_ctrl_decoder_decoded_invInputs[19], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], _ibuf_io_inst_0_bits_inst_bits[29], _ibuf_io_inst_0_bits_inst_bits[30], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_158 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], id_ctrl_decoder_decoded_invInputs[4], id_ctrl_decoder_decoded_invInputs[18], id_ctrl_decoder_decoded_invInputs[20], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], _ibuf_io_inst_0_bits_inst_bits[29], _ibuf_io_inst_0_bits_inst_bits[30], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_159 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], id_ctrl_decoder_decoded_invInputs[4], id_ctrl_decoder_decoded_invInputs[19], id_ctrl_decoder_decoded_invInputs[20], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], _ibuf_io_inst_0_bits_inst_bits[29], _ibuf_io_inst_0_bits_inst_bits[30], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_164 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], _ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], id_ctrl_decoder_decoded_invInputs[4], _ibuf_io_inst_0_bits_inst_bits[12], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], _ibuf_io_inst_0_bits_inst_bits[29], _ibuf_io_inst_0_bits_inst_bits[30], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [21:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_169 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], id_ctrl_decoder_decoded_invInputs[4], _ibuf_io_inst_0_bits_inst_bits[12], id_ctrl_decoder_decoded_invInputs[11], _ibuf_io_inst_0_bits_inst_bits[14], id_ctrl_decoder_decoded_invInputs[18], id_ctrl_decoder_decoded_invInputs[19], id_ctrl_decoder_decoded_invInputs[20], _ibuf_io_inst_0_bits_inst_bits[23], _ibuf_io_inst_0_bits_inst_bits[24], _ibuf_io_inst_0_bits_inst_bits[25], id_ctrl_decoder_decoded_invInputs[24], _ibuf_io_inst_0_bits_inst_bits[27], id_ctrl_decoder_decoded_invInputs[26], _ibuf_io_inst_0_bits_inst_bits[29], _ibuf_io_inst_0_bits_inst_bits[30], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_179 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[20], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[27], _ibuf_io_inst_0_bits_inst_bits[30], _ibuf_io_inst_0_bits_inst_bits[31]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_180 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[20], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[27], _ibuf_io_inst_0_bits_inst_bits[30], _ibuf_io_inst_0_bits_inst_bits[31]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_181 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[20], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], id_ctrl_decoder_decoded_invInputs[27], _ibuf_io_inst_0_bits_inst_bits[30], _ibuf_io_inst_0_bits_inst_bits[31]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_182 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[20], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], id_ctrl_decoder_decoded_invInputs[27], _ibuf_io_inst_0_bits_inst_bits[30], _ibuf_io_inst_0_bits_inst_bits[31]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_184 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[20], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[25], _ibuf_io_inst_0_bits_inst_bits[28], id_ctrl_decoder_decoded_invInputs[27], _ibuf_io_inst_0_bits_inst_bits[30], _ibuf_io_inst_0_bits_inst_bits[31]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_185 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[20], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], _ibuf_io_inst_0_bits_inst_bits[28], id_ctrl_decoder_decoded_invInputs[27], _ibuf_io_inst_0_bits_inst_bits[30], _ibuf_io_inst_0_bits_inst_bits[31]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [19:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_188 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[18], id_ctrl_decoder_decoded_invInputs[19], id_ctrl_decoder_decoded_invInputs[20], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], _ibuf_io_inst_0_bits_inst_bits[29], _ibuf_io_inst_0_bits_inst_bits[30], _ibuf_io_inst_0_bits_inst_bits[31]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [19:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_189 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[18], id_ctrl_decoder_decoded_invInputs[19], id_ctrl_decoder_decoded_invInputs[20], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], _ibuf_io_inst_0_bits_inst_bits[29], _ibuf_io_inst_0_bits_inst_bits[30], _ibuf_io_inst_0_bits_inst_bits[31]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [20:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_192 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[10], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[18], id_ctrl_decoder_decoded_invInputs[19], id_ctrl_decoder_decoded_invInputs[20], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[25], _ibuf_io_inst_0_bits_inst_bits[28], _ibuf_io_inst_0_bits_inst_bits[29], _ibuf_io_inst_0_bits_inst_bits[30], _ibuf_io_inst_0_bits_inst_bits[31]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [20:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_193 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[10], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[18], id_ctrl_decoder_decoded_invInputs[19], id_ctrl_decoder_decoded_invInputs[20], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], _ibuf_io_inst_0_bits_inst_bits[28], _ibuf_io_inst_0_bits_inst_bits[29], _ibuf_io_inst_0_bits_inst_bits[30], _ibuf_io_inst_0_bits_inst_bits[31]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [2:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_2 = {&_id_ctrl_decoder_decoded_andMatrixOutputs_T_52, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_90, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_95}; // @[pla.scala:98:{53,70}, :114:19] wire [45:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_10 = {&_id_ctrl_decoder_decoded_andMatrixOutputs_T, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_2, &{_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], id_ctrl_decoder_decoded_invInputs[2], id_ctrl_decoder_decoded_invInputs[3], id_ctrl_decoder_decoded_invInputs[4], id_ctrl_decoder_decoded_invInputs[12]}, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_6, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_7, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_12, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_13, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_14, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_16, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_25, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_26, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_34, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_36, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_43, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_48, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_52, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_55, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_61, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_84, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_85, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_89, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_90, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_91, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_95, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_115, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_116, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_120, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_122, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_124, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_130, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_133, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_149, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_152, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_157, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_158, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_159, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_164, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_169, &{_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[10], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], _ibuf_io_inst_0_bits_inst_bits[29], id_ctrl_decoder_decoded_invInputs[28], _ibuf_io_inst_0_bits_inst_bits[31]}, &{_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], _ibuf_io_inst_0_bits_inst_bits[29], id_ctrl_decoder_decoded_invInputs[28], _ibuf_io_inst_0_bits_inst_bits[31]}, &{_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[10], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], _ibuf_io_inst_0_bits_inst_bits[29], id_ctrl_decoder_decoded_invInputs[28], _ibuf_io_inst_0_bits_inst_bits[31]}, &{_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], _ibuf_io_inst_0_bits_inst_bits[29], id_ctrl_decoder_decoded_invInputs[28], _ibuf_io_inst_0_bits_inst_bits[31]}, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_181, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_182, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_188, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_189}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:19] wire [2:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_12 = {&{_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], id_ctrl_decoder_decoded_invInputs[4], _ibuf_io_inst_0_bits_inst_bits[25], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], id_ctrl_decoder_decoded_invInputs[27], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}, &{_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], _ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], id_ctrl_decoder_decoded_invInputs[4], id_ctrl_decoder_decoded_invInputs[10], id_ctrl_decoder_decoded_invInputs[11], _ibuf_io_inst_0_bits_inst_bits[25], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], id_ctrl_decoder_decoded_invInputs[27], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_85}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:19] wire [8:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_29 = {&{_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], id_ctrl_decoder_decoded_invInputs[2], id_ctrl_decoder_decoded_invInputs[3], id_ctrl_decoder_decoded_invInputs[4], id_ctrl_decoder_decoded_invInputs[10]}, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_2, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_3, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_29, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_44, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_52, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_90, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_96, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_104}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:19] wire [43:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_59 = {&_id_ctrl_decoder_decoded_andMatrixOutputs_T, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_2, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_3, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_6, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_12, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_13, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_14, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_16, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_24, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_29, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_34, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_36, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_42, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_44, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_48, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_52, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_56, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_61, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_63, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_84, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_85, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_89, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_90, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_91, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_95, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_102, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_115, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_116, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_120, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_122, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_124, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_130, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_133, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_149, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_152, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_157, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_158, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_159, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_164, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_169, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_184, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_185, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_192, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_193}; // @[pla.scala:98:{53,70}, :114:19] wire [21:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_61 = {&_id_ctrl_decoder_decoded_andMatrixOutputs_T_9, &{_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], id_ctrl_decoder_decoded_invInputs[2], _ibuf_io_inst_0_bits_inst_bits[5], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12]}, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_12, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_13, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_14, &{_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], _ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], id_ctrl_decoder_decoded_invInputs[4], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], id_ctrl_decoder_decoded_invInputs[27], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_16, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_52, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_61, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_63, &{_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], _ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], id_ctrl_decoder_decoded_invInputs[4], _ibuf_io_inst_0_bits_inst_bits[12], id_ctrl_decoder_decoded_invInputs[11], _ibuf_io_inst_0_bits_inst_bits[14], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], id_ctrl_decoder_decoded_invInputs[27], id_ctrl_decoder_decoded_invInputs[29]}, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_84, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_85, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_89, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_90, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_95, &{_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[5], id_ctrl_decoder_decoded_invInputs[6], id_ctrl_decoder_decoded_invInputs[7], id_ctrl_decoder_decoded_invInputs[10], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12], _ibuf_io_inst_0_bits_inst_bits[25], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], _ibuf_io_inst_0_bits_inst_bits[28], id_ctrl_decoder_decoded_invInputs[27], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_115, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_116, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_122, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_152, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_164}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:19] wire [20:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_67 = {&_id_ctrl_decoder_decoded_andMatrixOutputs_T_17, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_20, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_21, &{_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], _ibuf_io_inst_0_bits_inst_bits[2], id_ctrl_decoder_decoded_invInputs[1], id_ctrl_decoder_decoded_invInputs[2], id_ctrl_decoder_decoded_invInputs[4], _ibuf_io_inst_0_bits_inst_bits[12], id_ctrl_decoder_decoded_invInputs[12]}, &{_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], _ibuf_io_inst_0_bits_inst_bits[2], id_ctrl_decoder_decoded_invInputs[1], id_ctrl_decoder_decoded_invInputs[2], id_ctrl_decoder_decoded_invInputs[4], _ibuf_io_inst_0_bits_inst_bits[13], id_ctrl_decoder_decoded_invInputs[12]}, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_106, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_107, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_108, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_109, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_110, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_111, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_140, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_142, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_144, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_146, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_154, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_155, &{_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[18], id_ctrl_decoder_decoded_invInputs[19], id_ctrl_decoder_decoded_invInputs[20], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[25], _ibuf_io_inst_0_bits_inst_bits[30], _ibuf_io_inst_0_bits_inst_bits[31]}, &{_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[18], id_ctrl_decoder_decoded_invInputs[19], id_ctrl_decoder_decoded_invInputs[20], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], _ibuf_io_inst_0_bits_inst_bits[30], _ibuf_io_inst_0_bits_inst_bits[31]}, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_179, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_180}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:19] wire [2:0] id_ctrl_csr = {|{&{_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[5], id_ctrl_decoder_decoded_invInputs[6], id_ctrl_decoder_decoded_invInputs[7], id_ctrl_decoder_decoded_invInputs[8], id_ctrl_decoder_decoded_invInputs[9], id_ctrl_decoder_decoded_invInputs[10], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[13], id_ctrl_decoder_decoded_invInputs[14], id_ctrl_decoder_decoded_invInputs[15], id_ctrl_decoder_decoded_invInputs[16], id_ctrl_decoder_decoded_invInputs[17], id_ctrl_decoder_decoded_invInputs[19], id_ctrl_decoder_decoded_invInputs[20], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], id_ctrl_decoder_decoded_invInputs[27], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_43, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_55, &{_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[5], id_ctrl_decoder_decoded_invInputs[6], id_ctrl_decoder_decoded_invInputs[7], id_ctrl_decoder_decoded_invInputs[8], id_ctrl_decoder_decoded_invInputs[9], id_ctrl_decoder_decoded_invInputs[10], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[13], id_ctrl_decoder_decoded_invInputs[14], id_ctrl_decoder_decoded_invInputs[15], id_ctrl_decoder_decoded_invInputs[16], id_ctrl_decoder_decoded_invInputs[17], id_ctrl_decoder_decoded_invInputs[18], _ibuf_io_inst_0_bits_inst_bits[21], id_ctrl_decoder_decoded_invInputs[20], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], _ibuf_io_inst_0_bits_inst_bits[28], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}, &{_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[5], id_ctrl_decoder_decoded_invInputs[6], id_ctrl_decoder_decoded_invInputs[7], id_ctrl_decoder_decoded_invInputs[8], id_ctrl_decoder_decoded_invInputs[9], id_ctrl_decoder_decoded_invInputs[10], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[13], id_ctrl_decoder_decoded_invInputs[14], id_ctrl_decoder_decoded_invInputs[15], id_ctrl_decoder_decoded_invInputs[16], id_ctrl_decoder_decoded_invInputs[17], _ibuf_io_inst_0_bits_inst_bits[20], id_ctrl_decoder_decoded_invInputs[19], _ibuf_io_inst_0_bits_inst_bits[22], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], _ibuf_io_inst_0_bits_inst_bits[28], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_101, &{_ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[5], id_ctrl_decoder_decoded_invInputs[6], id_ctrl_decoder_decoded_invInputs[7], id_ctrl_decoder_decoded_invInputs[8], id_ctrl_decoder_decoded_invInputs[9], id_ctrl_decoder_decoded_invInputs[10], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[13], id_ctrl_decoder_decoded_invInputs[14], id_ctrl_decoder_decoded_invInputs[15], id_ctrl_decoder_decoded_invInputs[16], id_ctrl_decoder_decoded_invInputs[17], id_ctrl_decoder_decoded_invInputs[18], _ibuf_io_inst_0_bits_inst_bits[21], id_ctrl_decoder_decoded_invInputs[20], id_ctrl_decoder_decoded_invInputs[21], _ibuf_io_inst_0_bits_inst_bits[24], _ibuf_io_inst_0_bits_inst_bits[25], id_ctrl_decoder_decoded_invInputs[24], _ibuf_io_inst_0_bits_inst_bits[27], _ibuf_io_inst_0_bits_inst_bits[28], _ibuf_io_inst_0_bits_inst_bits[29], _ibuf_io_inst_0_bits_inst_bits[30], id_ctrl_decoder_decoded_invInputs[29]}}, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_55, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_43}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] reg id_reg_fence; // @[RocketCore.scala:333:29] wire _id_csr_ren_T = id_ctrl_csr == 3'h6; // @[package.scala:16:47] wire id_csr_en = _id_csr_ren_T | (&id_ctrl_csr) | id_ctrl_csr == 3'h5; // @[package.scala:16:47, :81:59] wire id_mem_busy = ~io_dmem_ordered | io_dmem_req_valid_0; // @[RocketCore.scala:403:{21,38}, :1130:41] wire _io_rocc_cmd_valid_T = wb_reg_valid & wb_ctrl_rocc; // @[RocketCore.scala:245:20, :288:35, :407:53] wire bypass_sources_3_1 = mem_reg_valid & mem_ctrl_wxd; // @[RocketCore.scala:244:21, :265:36, :459:20] wire _fp_data_hazard_ex_T_1 = ex_reg_inst[11:7] == _ibuf_io_inst_0_bits_inst_rs1; // @[RocketCore.scala:259:24, :311:20, :453:29, :461:82] wire _fp_data_hazard_mem_T_1 = mem_reg_inst[11:7] == _ibuf_io_inst_0_bits_inst_rs1; // @[RocketCore.scala:278:25, :311:20, :454:31, :461:82] wire _fp_data_hazard_ex_T_3 = ex_reg_inst[11:7] == _ibuf_io_inst_0_bits_inst_rs2; // @[RocketCore.scala:259:24, :311:20, :453:29, :461:82] wire _fp_data_hazard_mem_T_3 = mem_reg_inst[11:7] == _ibuf_io_inst_0_bits_inst_rs2; // @[RocketCore.scala:278:25, :311:20, :454:31, :461:82] reg ex_reg_rs_bypass_0; // @[RocketCore.scala:465:29] reg ex_reg_rs_bypass_1; // @[RocketCore.scala:465:29] reg [1:0] ex_reg_rs_lsb_0; // @[RocketCore.scala:466:26] reg [1:0] ex_reg_rs_lsb_1; // @[RocketCore.scala:466:26] reg [61:0] ex_reg_rs_msb_0; // @[RocketCore.scala:467:26] reg [61:0] ex_reg_rs_msb_1; // @[RocketCore.scala:467:26] wire [3:0][63:0] _GEN = {{io_dmem_resp_bits_data_word_bypass}, {wb_reg_wdata}, {mem_reg_wdata}, {64'h0}}; // @[package.scala:39:{76,86}] wire [63:0] ex_rs_0 = ex_reg_rs_bypass_0 ? _GEN[ex_reg_rs_lsb_0] : {ex_reg_rs_msb_0, ex_reg_rs_lsb_0}; // @[package.scala:39:{76,86}] wire [63:0] ex_rs_1 = ex_reg_rs_bypass_1 ? _GEN[ex_reg_rs_lsb_1] : {ex_reg_rs_msb_1, ex_reg_rs_lsb_1}; // @[package.scala:39:{76,86}] wire _ex_imm_b0_T_4 = ex_ctrl_sel_imm == 3'h5; // @[RocketCore.scala:243:20, :1341:24] wire ex_imm_sign = ~_ex_imm_b0_T_4 & ex_reg_inst[31]; // @[RocketCore.scala:259:24, :1341:{19,24,44}] wire _ex_imm_b4_1_T = ex_ctrl_sel_imm == 3'h2; // @[RocketCore.scala:243:20, :1342:26] wire _ex_imm_b4_1_T_2 = ex_ctrl_sel_imm == 3'h1; // @[RocketCore.scala:243:20, :1346:23] wire _ex_imm_b0_T = ex_ctrl_sel_imm == 3'h0; // @[RocketCore.scala:243:20, :1349:24] wire [66:0] ex_rs1shl = {3'h0, ex_reg_inst[3] ? {32'h0, ex_rs_0[31:0]} : ex_rs_0} << ex_reg_inst[14:13]; // @[RocketCore.scala:259:24, :469:14, :471:{22,34,47,65,79}] wire [3:0][63:0] _GEN_0 = {{ex_rs1shl[63:0]}, {{{24{ex_reg_pc[39]}}, ex_reg_pc}}, {ex_rs_0}, {64'h0}}; // @[RocketCore.scala:256:22, :469:14, :471:65, :472:48] wire [3:0] _ex_op2_T_1 = ex_reg_rvc ? 4'h2 : 4'h4; // @[RocketCore.scala:249:35, :481:19] wire div_io_req_valid = ex_reg_valid & ex_ctrl_div; // @[RocketCore.scala:243:20, :248:35, :512:36] wire ex_pc_valid = ex_reg_valid | ex_reg_replay | ex_reg_xcpt_interrupt; // @[RocketCore.scala:247:35, :248:35, :255:26, :595:{34,51}] wire wb_dcache_miss = wb_ctrl_mem & ~io_dmem_resp_valid; // @[RocketCore.scala:245:20, :596:{36,39}] wire replay_ex = ex_reg_replay | ex_reg_valid & (ex_ctrl_mem & ~io_dmem_req_ready | ex_ctrl_div & ~_div_io_req_ready | wb_dcache_miss & ex_reg_load_use); // @[RocketCore.scala:243:20, :248:35, :253:35, :255:26, :511:19, :596:36, :597:{42,45,64}, :598:{42,45}, :600:43, :601:{33,50,75}] wire ctrl_killx = ibuf_io_kill | replay_ex | ~ex_reg_valid; // @[RocketCore.scala:248:35, :307:35, :601:33, :602:{35,48,51}] wire _mem_cfi_taken_T = mem_ctrl_branch & mem_br_taken; // @[RocketCore.scala:244:21, :284:25, :616:25] wire [3:0] _mem_br_target_T_6 = mem_reg_rvc ? 4'h2 : 4'h4; // @[RocketCore.scala:266:36, :618:8] wire [31:0] _mem_br_target_T_8 = _mem_cfi_taken_T ? {{20{mem_reg_inst[31]}}, mem_reg_inst[7], mem_reg_inst[30:25], mem_reg_inst[11:8], 1'h0} : mem_ctrl_jal ? {{12{mem_reg_inst[31]}}, mem_reg_inst[19:12], mem_reg_inst[20], mem_reg_inst[30:21], 1'h0} : {{28{_mem_br_target_T_6[3]}}, _mem_br_target_T_6}; // @[RocketCore.scala:244:21, :278:25, :616:{8,25}, :617:8, :618:8, :1341:44, :1343:65, :1345:39, :1346:39, :1347:62, :1349:57, :1355:8] wire [39:0] _mem_br_target_T_9 = mem_reg_pc + {{8{_mem_br_target_T_8[31]}}, _mem_br_target_T_8}; // @[RocketCore.scala:277:23, :615:41, :616:8] wire [39:0] _mem_npc_T_4 = mem_ctrl_jalr | mem_reg_sfence ? {mem_reg_wdata[63:39] == 25'h0 | (&(mem_reg_wdata[63:39])) ? mem_reg_wdata[39] : ~(mem_reg_wdata[38]), mem_reg_wdata[38:0]} : _mem_br_target_T_9; // @[RocketCore.scala:244:21, :276:27, :282:26, :615:41, :619:{21,36}, :1293:{17,23}, :1294:{18,21,29,34,46,51,54}, :1295:{8,16}] wire [39:0] mem_npc = _mem_npc_T_4 & 40'hFFFFFFFFFE; // @[RocketCore.scala:619:{21,129}] wire mem_wrong_npc = ex_pc_valid ? mem_npc != ex_reg_pc : ~(_ibuf_io_inst_0_valid | io_imem_resp_valid) | mem_npc != _ibuf_io_pc; // @[RocketCore.scala:256:22, :311:20, :595:{34,51}, :619:129, :621:{8,30}, :622:{8,31,62}] wire mem_cfi = mem_ctrl_branch | mem_ctrl_jalr | mem_ctrl_jal; // @[RocketCore.scala:244:21, :625:{33,50}] assign take_pc_mem = mem_reg_valid & ~mem_reg_xcpt & (mem_wrong_npc | mem_reg_sfence); // @[RocketCore.scala:265:36, :268:36, :276:27, :621:8, :624:27, :629:{32,49,71}] wire mem_debug_breakpoint = mem_reg_load & _bpu_io_debug_ld | mem_reg_store & _bpu_io_debug_st; // @[RocketCore.scala:273:36, :274:36, :414:19, :678:{44,64,82}] wire mem_ldst_xcpt = mem_debug_breakpoint | mem_reg_load & _bpu_io_xcpt_ld | mem_reg_store & _bpu_io_xcpt_st; // @[RocketCore.scala:273:36, :274:36, :414:19, :677:{38,57,75}, :678:64, :1278:35] wire dcache_kill_mem = bypass_sources_3_1 & io_dmem_replay_next; // @[RocketCore.scala:459:20, :695:55] wire fpu_kill_mem = mem_reg_valid & mem_ctrl_fp & io_fpu_nack_mem; // @[RocketCore.scala:244:21, :265:36, :696:{36,51}] wire killm_common = dcache_kill_mem | take_pc_wb | mem_reg_xcpt | ~mem_reg_valid; // @[RocketCore.scala:265:36, :268:36, :695:55, :700:{38,52,68,71}, :762:{27,38,53}] reg div_io_kill_REG; // @[RocketCore.scala:701:41] wire _GEN_1 = wb_reg_valid & wb_ctrl_mem; // @[RocketCore.scala:245:20, :288:35, :730:19] wire _GEN_2 = _GEN_1 & io_dmem_s2_xcpt_pf_st; // @[RocketCore.scala:730:{19,34}] wire _GEN_3 = _GEN_1 & io_dmem_s2_xcpt_pf_ld; // @[RocketCore.scala:730:19, :731:34] wire _GEN_4 = _GEN_1 & io_dmem_s2_xcpt_ae_st; // @[RocketCore.scala:730:19, :734:34] wire _GEN_5 = _GEN_1 & io_dmem_s2_xcpt_ae_ld; // @[RocketCore.scala:730:19, :735:34] wire _GEN_6 = _GEN_1 & io_dmem_s2_xcpt_ma_st; // @[RocketCore.scala:730:19, :736:34] wire wb_xcpt = wb_reg_xcpt | _GEN_2 | _GEN_3 | _GEN_4 | _GEN_5 | _GEN_6 | _GEN_1 & io_dmem_s2_xcpt_ma_ld; // @[RocketCore.scala:289:35, :730:{19,34}, :731:34, :734:34, :735:34, :736:34, :737:34, :1278:35] wire wb_wxd = wb_reg_valid & wb_ctrl_wxd; // @[RocketCore.scala:245:20, :288:35, :755:29] wire wb_set_sboard = wb_ctrl_div | wb_dcache_miss | wb_ctrl_rocc | wb_ctrl_vec; // @[RocketCore.scala:245:20, :596:36, :756:{35,53,69}] wire replay_wb_common = io_dmem_s2_nack | wb_reg_replay; // @[RocketCore.scala:290:35, :757:42] wire _replay_wb_T = replay_wb_common | _io_rocc_cmd_valid_T; // @[RocketCore.scala:407:53, :757:42, :761:36] assign take_pc_wb = _replay_wb_T | wb_xcpt | _csr_io_eret | wb_reg_flush_pipe; // @[RocketCore.scala:291:35, :341:19, :761:36, :762:{27,38,53}, :1278:35] wire dmem_resp_valid = io_dmem_resp_valid & io_dmem_resp_bits_has_data; // @[RocketCore.scala:768:44] wire dmem_resp_replay = dmem_resp_valid & io_dmem_resp_bits_replay; // @[RocketCore.scala:768:44, :769:42] wire _GEN_7 = dmem_resp_replay & ~(io_dmem_resp_bits_tag[0]); // @[RocketCore.scala:765:{23,45}, :769:42, :809:26] assign ll_arb_io_out_ready = ~_GEN_7 & ~wb_wxd; // @[RocketCore.scala:755:29, :782:{23,26}, :809:{26,44}, :810:25] wire [4:0] ll_waddr = _GEN_7 ? io_dmem_resp_bits_tag[5:1] : _ll_arb_io_out_bits_tag; // @[RocketCore.scala:767:46, :776:22, :780:26, :809:{26,44}, :811:14] wire ll_wen = _GEN_7 | ll_arb_io_out_ready & _ll_arb_io_out_valid; // @[Decoupled.scala:51:35] wire wb_valid = wb_reg_valid & ~_replay_wb_T & ~wb_xcpt; // @[RocketCore.scala:288:35, :761:36, :815:{31,34,45,48}, :1278:35] wire wb_wen = wb_valid & wb_ctrl_wxd; // @[RocketCore.scala:245:20, :815:{31,45}, :816:25] wire rf_wen = wb_wen | ll_wen; // @[RocketCore.scala:781:24, :809:44, :812:12, :816:25, :817:23] wire [4:0] rf_waddr = ll_wen ? ll_waddr : wb_reg_inst[11:7]; // @[RocketCore.scala:300:24, :455:29, :780:26, :781:24, :809:44, :811:14, :812:12, :818:21] wire [63:0] rf_wdata = dmem_resp_valid & ~(io_dmem_resp_bits_tag[0]) ? io_dmem_resp_bits_data : ll_wen ? _ll_arb_io_out_bits_data : (|wb_ctrl_csr) ? _csr_io_rw_rdata : wb_reg_wdata; // @[RocketCore.scala:245:20, :302:25, :341:19, :765:{23,45}, :768:44, :776:22, :781:24, :809:44, :812:12, :819:{21,38}, :820:21, :821:{21,34}] wire [63:0] id_rs_0 = rf_wen & (|rf_waddr) & rf_waddr == _ibuf_io_inst_0_bits_inst_rs1 ? rf_wdata : _rf_ext_R1_data; // @[RocketCore.scala:311:20, :817:23, :818:21, :819:21, :824:17, :1319:15, :1326:19, :1331:{16,25}, :1334:{20,31,39}] wire [63:0] id_rs_1 = rf_wen & (|rf_waddr) & rf_waddr == _ibuf_io_inst_0_bits_inst_rs2 ? rf_wdata : _rf_ext_R0_data; // @[RocketCore.scala:311:20, :817:23, :818:21, :819:21, :824:17, :1319:15, :1326:19, :1331:{16,25}, :1334:{20,31,39}] wire _htval_valid_imem_T = wb_reg_cause == 64'h14; // @[package.scala:16:47] wire tval_any_addr = ~wb_reg_xcpt | wb_reg_cause == 64'h3 | wb_reg_cause == 64'h1 | wb_reg_cause == 64'hC | _htval_valid_imem_T; // @[package.scala:16:47, :81:59] wire hazard_targets_0_1 = (|_id_ctrl_decoder_decoded_orMatrixOutputs_T_59) & (|_ibuf_io_inst_0_bits_inst_rs1); // @[pla.scala:114:{19,36}] wire hazard_targets_1_1 = (|_id_ctrl_decoder_decoded_orMatrixOutputs_T_61) & (|_ibuf_io_inst_0_bits_inst_rs2); // @[pla.scala:114:{19,36}] wire hazard_targets_2_1 = (|_id_ctrl_decoder_decoded_orMatrixOutputs_T_10) & (|_ibuf_io_inst_0_bits_inst_rd); // @[pla.scala:114:{19,36}] reg [31:0] _r; // @[RocketCore.scala:1305:29] wire [31:0] r = {_r[31:1], 1'h0}; // @[RocketCore.scala:1305:29, :1306:{35,40}] wire [31:0] _GEN_8 = {27'h0, _ibuf_io_inst_0_bits_inst_rs1}; // @[RocketCore.scala:311:20, :1302:35, :1309:58] wire [31:0] _id_sboard_hazard_T = r >> _GEN_8; // @[RocketCore.scala:1302:35, :1306:40] wire [31:0] _GEN_9 = {27'h0, _ibuf_io_inst_0_bits_inst_rs2}; // @[RocketCore.scala:311:20, :1302:35, :1309:58] wire [31:0] _id_sboard_hazard_T_7 = r >> _GEN_9; // @[RocketCore.scala:1302:35, :1306:40] wire [31:0] _GEN_10 = {27'h0, _ibuf_io_inst_0_bits_inst_rd}; // @[RocketCore.scala:311:20, :1302:35, :1309:58] wire [31:0] _id_sboard_hazard_T_14 = r >> _GEN_10; // @[RocketCore.scala:1302:35, :1306:40] wire _fp_data_hazard_ex_T_7 = _ibuf_io_inst_0_bits_inst_rd == ex_reg_inst[11:7]; // @[RocketCore.scala:259:24, :311:20, :453:29, :989:70] wire _fp_data_hazard_mem_T_7 = _ibuf_io_inst_0_bits_inst_rd == mem_reg_inst[11:7]; // @[RocketCore.scala:278:25, :311:20, :454:31, :998:72] wire data_hazard_mem = mem_ctrl_wxd & (hazard_targets_0_1 & _fp_data_hazard_mem_T_1 | hazard_targets_1_1 & _fp_data_hazard_mem_T_3 | hazard_targets_2_1 & _fp_data_hazard_mem_T_7); // @[RocketCore.scala:244:21, :461:82, :969:42, :970:42, :971:42, :998:{38,72}, :1287:{27,50}] wire _fp_data_hazard_wb_T_1 = _ibuf_io_inst_0_bits_inst_rs1 == wb_reg_inst[11:7]; // @[RocketCore.scala:300:24, :311:20, :455:29, :1008:70] wire _fp_data_hazard_wb_T_3 = _ibuf_io_inst_0_bits_inst_rs2 == wb_reg_inst[11:7]; // @[RocketCore.scala:300:24, :311:20, :455:29, :1008:70] wire _fp_data_hazard_wb_T_7 = _ibuf_io_inst_0_bits_inst_rd == wb_reg_inst[11:7]; // @[RocketCore.scala:300:24, :311:20, :455:29, :1008:70] reg [31:0] _id_stall_fpu_r; // @[RocketCore.scala:1305:29] wire [31:0] _id_stall_fpu_T_20 = _id_stall_fpu_r >> _GEN_8; // @[RocketCore.scala:1302:35, :1305:29] wire [31:0] _id_stall_fpu_T_23 = _id_stall_fpu_r >> _GEN_9; // @[RocketCore.scala:1302:35, :1305:29] wire [31:0] _id_stall_fpu_T_26 = _id_stall_fpu_r >> _ibuf_io_inst_0_bits_inst_rs3; // @[RocketCore.scala:311:20, :1302:35, :1305:29] wire [31:0] _id_stall_fpu_T_29 = _id_stall_fpu_r >> _GEN_10; // @[RocketCore.scala:1302:35, :1305:29] reg dcache_blocked_blocked; // @[RocketCore.scala:1024:22] reg rocc_blocked; // @[RocketCore.scala:1028:25] wire _ctrl_stalld_T_32 = ex_reg_valid & (ex_ctrl_wxd & (hazard_targets_0_1 & _fp_data_hazard_ex_T_1 | hazard_targets_1_1 & _fp_data_hazard_ex_T_3 | hazard_targets_2_1 & _fp_data_hazard_ex_T_7) & ((|ex_ctrl_csr) | ex_ctrl_jalr | ex_ctrl_mem | ex_ctrl_mul | ex_ctrl_div | ex_ctrl_fp | ex_ctrl_rocc) | (|_id_ctrl_decoder_decoded_orMatrixOutputs_T_67) & ex_ctrl_wfd & (io_fpu_dec_ren1 & _fp_data_hazard_ex_T_1 | io_fpu_dec_ren2 & _fp_data_hazard_ex_T_3 | io_fpu_dec_ren3 & _ibuf_io_inst_0_bits_inst_rs3 == ex_reg_inst[11:7] | io_fpu_dec_wen & _fp_data_hazard_ex_T_7)) | mem_reg_valid & (data_hazard_mem & ((|mem_ctrl_csr) | mem_ctrl_mem & mem_mem_cmd_bh | mem_ctrl_mul | mem_ctrl_div | mem_ctrl_fp | mem_ctrl_rocc | mem_ctrl_vec) | (|_id_ctrl_decoder_decoded_orMatrixOutputs_T_67) & mem_ctrl_wfd & (io_fpu_dec_ren1 & _fp_data_hazard_mem_T_1 | io_fpu_dec_ren2 & _fp_data_hazard_mem_T_3 | io_fpu_dec_ren3 & _ibuf_io_inst_0_bits_inst_rs3 == mem_reg_inst[11:7] | io_fpu_dec_wen & _fp_data_hazard_mem_T_7)) | wb_reg_valid & (wb_ctrl_wxd & (hazard_targets_0_1 & _fp_data_hazard_wb_T_1 | hazard_targets_1_1 & _fp_data_hazard_wb_T_3 | hazard_targets_2_1 & _fp_data_hazard_wb_T_7) & wb_set_sboard | (|_id_ctrl_decoder_decoded_orMatrixOutputs_T_67) & wb_ctrl_wfd & (io_fpu_dec_ren1 & _fp_data_hazard_wb_T_1 | io_fpu_dec_ren2 & _fp_data_hazard_wb_T_3 | io_fpu_dec_ren3 & _ibuf_io_inst_0_bits_inst_rs3 == wb_reg_inst[11:7] | io_fpu_dec_wen & _fp_data_hazard_wb_T_7)) | hazard_targets_0_1 & _id_sboard_hazard_T[0] & ~(ll_wen & ll_waddr == _ibuf_io_inst_0_bits_inst_rs1) | hazard_targets_1_1 & _id_sboard_hazard_T_7[0] & ~(ll_wen & ll_waddr == _ibuf_io_inst_0_bits_inst_rs2) | hazard_targets_2_1 & _id_sboard_hazard_T_14[0] & ~(ll_wen & ll_waddr == _ibuf_io_inst_0_bits_inst_rd) | _csr_io_singleStep & (ex_reg_valid | mem_reg_valid | wb_reg_valid) | id_csr_en & _csr_io_decode_0_fp_csr & ~io_fpu_fcsr_rdy | (|_id_ctrl_decoder_decoded_orMatrixOutputs_T_67) & (io_fpu_dec_ren1 & _id_stall_fpu_T_20[0] | io_fpu_dec_ren2 & _id_stall_fpu_T_23[0] | io_fpu_dec_ren3 & _id_stall_fpu_T_26[0] | io_fpu_dec_wen & _id_stall_fpu_T_29[0]) | (|_id_ctrl_decoder_decoded_orMatrixOutputs_T_29) & dcache_blocked_blocked & ~io_dmem_perf_grant | (|_id_ctrl_decoder_decoded_orMatrixOutputs_T_12) & (~(_div_io_req_ready | _div_io_resp_valid & ~wb_wxd) | div_io_req_valid) | id_mem_busy & ((|_id_ctrl_decoder_decoded_orMatrixOutputs_T_2) & _ibuf_io_inst_0_bits_inst_bits[25] | (&_id_ctrl_decoder_decoded_andMatrixOutputs_T_33) | id_reg_fence & (|_id_ctrl_decoder_decoded_orMatrixOutputs_T_29)) | _csr_io_csr_stall | id_reg_pause; // @[pla.scala:98:{53,70}, :114:{19,36}] wire ctrl_killd = ~_ibuf_io_inst_0_valid | _ibuf_io_inst_0_bits_replay | ibuf_io_kill | _ctrl_stalld_T_32 | _csr_io_interrupt; // @[RocketCore.scala:307:35, :311:20, :341:19, :1032:{18,35,51}, :1033:23, :1034:74, :1036:61, :1037:32, :1039:34, :1041:15, :1042:17, :1043:22, :1046:{17,40,71,89,104}, :1287:50] reg io_imem_progress_REG; // @[RocketCore.scala:1059:30] wire io_ptw_sfence_valid_0 = wb_reg_valid & wb_reg_sfence; // @[RocketCore.scala:288:35, :294:26, :1060:40] wire _io_imem_btb_update_bits_cfiType_T_9 = mem_ctrl_jal | mem_ctrl_jalr; // @[RocketCore.scala:244:21, :1074:23] wire [38:0] _io_imem_btb_update_bits_br_pc_T_1 = mem_reg_pc[38:0] + {37'h0, ~mem_reg_rvc, 1'h0}; // @[RocketCore.scala:266:36, :277:23, :1079:{69,74}] wire [38:0] io_imem_bht_update_bits_pc_0 = {_io_imem_btb_update_bits_br_pc_T_1[38:2], 2'h0}; // @[RocketCore.scala:1079:69, :1080:66] assign io_dmem_req_valid_0 = ex_reg_valid & ex_ctrl_mem; // @[RocketCore.scala:243:20, :248:35, :1130:41] reg [63:0] coreMonitorBundle_rd0val_REG; // @[RocketCore.scala:1199:46] reg [63:0] coreMonitorBundle_rd0val_REG_1; // @[RocketCore.scala:1199:38] reg [63:0] coreMonitorBundle_rd1val_REG; // @[RocketCore.scala:1201:46] reg [63:0] coreMonitorBundle_rd1val_REG_1; // @[RocketCore.scala:1201:38]

Generate the Verilog code corresponding to the following Chisel files. File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }

module ClockCrossingReg_w43( // @[SynchronizerReg.scala:191:7] input clock, // @[SynchronizerReg.scala:191:7] input reset, // @[SynchronizerReg.scala:191:7] input [42:0] io_d, // @[SynchronizerReg.scala:195:14] output [42:0] io_q, // @[SynchronizerReg.scala:195:14] input io_en // @[SynchronizerReg.scala:195:14] ); wire [42:0] io_d_0 = io_d; // @[SynchronizerReg.scala:191:7] wire io_en_0 = io_en; // @[SynchronizerReg.scala:191:7] wire [42:0] io_q_0; // @[SynchronizerReg.scala:191:7] reg [42:0] cdc_reg; // @[SynchronizerReg.scala:201:76] assign io_q_0 = cdc_reg; // @[SynchronizerReg.scala:191:7, :201:76] always @(posedge clock) begin // @[SynchronizerReg.scala:191:7] if (io_en_0) // @[SynchronizerReg.scala:191:7] cdc_reg <= io_d_0; // @[SynchronizerReg.scala:191:7, :201:76] always @(posedge) assign io_q = io_q_0; // @[SynchronizerReg.scala:191:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File WidthWidget.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.AddressSet import freechips.rocketchip.util.{Repeater, UIntToOH1} // innBeatBytes => the new client-facing bus width class TLWidthWidget(innerBeatBytes: Int)(implicit p: Parameters) extends LazyModule { private def noChangeRequired(manager: TLManagerPortParameters) = manager.beatBytes == innerBeatBytes val node = new TLAdapterNode( clientFn = { case c => c }, managerFn = { case m => m.v1copy(beatBytes = innerBeatBytes) }){ override def circuitIdentity = edges.out.map(_.manager).forall(noChangeRequired) } override lazy val desiredName = s"TLWidthWidget$innerBeatBytes" lazy val module = new Impl class Impl extends LazyModuleImp(this) { def merge[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T]) = { val inBytes = edgeIn.manager.beatBytes val outBytes = edgeOut.manager.beatBytes val ratio = outBytes / inBytes val keepBits = log2Ceil(outBytes) val dropBits = log2Ceil(inBytes) val countBits = log2Ceil(ratio) val size = edgeIn.size(in.bits) val hasData = edgeIn.hasData(in.bits) val limit = UIntToOH1(size, keepBits) >> dropBits val count = RegInit(0.U(countBits.W)) val first = count === 0.U val last = count === limit || !hasData val enable = Seq.tabulate(ratio) { i => !((count ^ i.U) & limit).orR } val corrupt_reg = RegInit(false.B) val corrupt_in = edgeIn.corrupt(in.bits) val corrupt_out = corrupt_in || corrupt_reg when (in.fire) { count := count + 1.U corrupt_reg := corrupt_out when (last) { count := 0.U corrupt_reg := false.B } } def helper(idata: UInt): UInt = { // rdata is X until the first time a multi-beat write occurs. // Prevent the X from leaking outside by jamming the mux control until // the first time rdata is written (and hence no longer X). val rdata_written_once = RegInit(false.B) val masked_enable = enable.map(_ || !rdata_written_once) val odata = Seq.fill(ratio) { WireInit(idata) } val rdata = Reg(Vec(ratio-1, chiselTypeOf(idata))) val pdata = rdata :+ idata val mdata = (masked_enable zip (odata zip pdata)) map { case (e, (o, p)) => Mux(e, o, p) } when (in.fire && !last) { rdata_written_once := true.B (rdata zip mdata) foreach { case (r, m) => r := m } } Cat(mdata.reverse) } in.ready := out.ready || !last out.valid := in.valid && last out.bits := in.bits // Don't put down hardware if we never carry data edgeOut.data(out.bits) := (if (edgeIn.staticHasData(in.bits) == Some(false)) 0.U else helper(edgeIn.data(in.bits))) edgeOut.corrupt(out.bits) := corrupt_out (out.bits, in.bits) match { case (o: TLBundleA, i: TLBundleA) => o.mask := edgeOut.mask(o.address, o.size) & Mux(hasData, helper(i.mask), ~0.U(outBytes.W)) case (o: TLBundleB, i: TLBundleB) => o.mask := edgeOut.mask(o.address, o.size) & Mux(hasData, helper(i.mask), ~0.U(outBytes.W)) case (o: TLBundleC, i: TLBundleC) => () case (o: TLBundleD, i: TLBundleD) => () case _ => require(false, "Impossible bundle combination in WidthWidget") } } def split[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T], sourceMap: UInt => UInt) = { val inBytes = edgeIn.manager.beatBytes val outBytes = edgeOut.manager.beatBytes val ratio = inBytes / outBytes val keepBits = log2Ceil(inBytes) val dropBits = log2Ceil(outBytes) val countBits = log2Ceil(ratio) val size = edgeIn.size(in.bits) val hasData = edgeIn.hasData(in.bits) val limit = UIntToOH1(size, keepBits) >> dropBits val count = RegInit(0.U(countBits.W)) val first = count === 0.U val last = count === limit || !hasData when (out.fire) { count := count + 1.U when (last) { count := 0.U } } // For sub-beat transfer, extract which part matters val sel = in.bits match { case a: TLBundleA => a.address(keepBits-1, dropBits) case b: TLBundleB => b.address(keepBits-1, dropBits) case c: TLBundleC => c.address(keepBits-1, dropBits) case d: TLBundleD => { val sel = sourceMap(d.source) val hold = Mux(first, sel, RegEnable(sel, first)) // a_first is not for whole xfer hold & ~limit // if more than one a_first/xfer, the address must be aligned anyway } } val index = sel | count def helper(idata: UInt, width: Int): UInt = { val mux = VecInit.tabulate(ratio) { i => idata((i+1)*outBytes*width-1, i*outBytes*width) } mux(index) } out.bits := in.bits out.valid := in.valid in.ready := out.ready // Don't put down hardware if we never carry data edgeOut.data(out.bits) := (if (edgeIn.staticHasData(in.bits) == Some(false)) 0.U else helper(edgeIn.data(in.bits), 8)) (out.bits, in.bits) match { case (o: TLBundleA, i: TLBundleA) => o.mask := helper(i.mask, 1) case (o: TLBundleB, i: TLBundleB) => o.mask := helper(i.mask, 1) case (o: TLBundleC, i: TLBundleC) => () // replicating corrupt to all beats is ok case (o: TLBundleD, i: TLBundleD) => () case _ => require(false, "Impossbile bundle combination in WidthWidget") } // Repeat the input if we're not last !last } def splice[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T], sourceMap: UInt => UInt) = { if (edgeIn.manager.beatBytes == edgeOut.manager.beatBytes) { // nothing to do; pass it through out.bits := in.bits out.valid := in.valid in.ready := out.ready } else if (edgeIn.manager.beatBytes > edgeOut.manager.beatBytes) { // split input to output val repeat = Wire(Bool()) val repeated = Repeater(in, repeat) val cated = Wire(chiselTypeOf(repeated)) cated <> repeated edgeIn.data(cated.bits) := Cat( edgeIn.data(repeated.bits)(edgeIn.manager.beatBytes*8-1, edgeOut.manager.beatBytes*8), edgeIn.data(in.bits)(edgeOut.manager.beatBytes*8-1, 0)) repeat := split(edgeIn, cated, edgeOut, out, sourceMap) } else { // merge input to output merge(edgeIn, in, edgeOut, out) } } (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => // If the master is narrower than the slave, the D channel must be narrowed. // This is tricky, because the D channel has no address data. // Thus, you don't know which part of a sub-beat transfer to extract. // To fix this, we record the relevant address bits for all sources. // The assumption is that this sort of situation happens only where // you connect a narrow master to the system bus, so there are few sources. def sourceMap(source_bits: UInt) = { val source = if (edgeIn.client.endSourceId == 1) 0.U(0.W) else source_bits require (edgeOut.manager.beatBytes > edgeIn.manager.beatBytes) val keepBits = log2Ceil(edgeOut.manager.beatBytes) val dropBits = log2Ceil(edgeIn.manager.beatBytes) val sources = Reg(Vec(edgeIn.client.endSourceId, UInt((keepBits-dropBits).W))) val a_sel = in.a.bits.address(keepBits-1, dropBits) when (in.a.fire) { if (edgeIn.client.endSourceId == 1) { // avoid extraction-index-width warning sources(0) := a_sel } else { sources(in.a.bits.source) := a_sel } } // depopulate unused source registers: edgeIn.client.unusedSources.foreach { id => sources(id) := 0.U } val bypass = in.a.valid && in.a.bits.source === source if (edgeIn.manager.minLatency > 0) sources(source) else Mux(bypass, a_sel, sources(source)) } splice(edgeIn, in.a, edgeOut, out.a, sourceMap) splice(edgeOut, out.d, edgeIn, in.d, sourceMap) if (edgeOut.manager.anySupportAcquireB && edgeIn.client.anySupportProbe) { splice(edgeOut, out.b, edgeIn, in.b, sourceMap) splice(edgeIn, in.c, edgeOut, out.c, sourceMap) out.e.valid := in.e.valid out.e.bits := in.e.bits in.e.ready := out.e.ready } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLWidthWidget { def apply(innerBeatBytes: Int)(implicit p: Parameters): TLNode = { val widget = LazyModule(new TLWidthWidget(innerBeatBytes)) widget.node } def apply(wrapper: TLBusWrapper)(implicit p: Parameters): TLNode = apply(wrapper.beatBytes) } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMWidthWidget(first: Int, second: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("WidthWidget")) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff))) (ram.node := TLDelayer(0.1) := TLFragmenter(4, 256) := TLWidthWidget(second) := TLWidthWidget(first) := TLDelayer(0.1) := model.node := fuzz.node) lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMWidthWidgetTest(little: Int, big: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMWidthWidget(little,big,txns)).module) dut.io.start := DontCare io.finished := dut.io.finished } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } }

module TLInterconnectCoupler_sbus_to_bus_named_cbus( // @[LazyModuleImp.scala:138:7] input clock, // @[LazyModuleImp.scala:138:7] input reset, // @[LazyModuleImp.scala:138:7] output auto_widget_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_widget_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_widget_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_widget_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_widget_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_widget_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [28:0] auto_widget_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [15:0] auto_widget_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [127:0] auto_widget_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_widget_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_widget_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_widget_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_widget_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_widget_anon_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_widget_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_widget_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_widget_anon_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_widget_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [127:0] auto_widget_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_widget_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_bus_xing_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_bus_xing_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_bus_xing_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_bus_xing_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [28:0] auto_bus_xing_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_bus_xing_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_bus_xing_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_bus_xing_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_bus_xing_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_bus_xing_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_bus_xing_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire auto_widget_anon_in_a_valid_0 = auto_widget_anon_in_a_valid; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_widget_anon_in_a_bits_opcode_0 = auto_widget_anon_in_a_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_widget_anon_in_a_bits_param_0 = auto_widget_anon_in_a_bits_param; // @[LazyModuleImp.scala:138:7] wire [3:0] auto_widget_anon_in_a_bits_size_0 = auto_widget_anon_in_a_bits_size; // @[LazyModuleImp.scala:138:7] wire [5:0] auto_widget_anon_in_a_bits_source_0 = auto_widget_anon_in_a_bits_source; // @[LazyModuleImp.scala:138:7] wire [28:0] auto_widget_anon_in_a_bits_address_0 = auto_widget_anon_in_a_bits_address; // @[LazyModuleImp.scala:138:7] wire [15:0] auto_widget_anon_in_a_bits_mask_0 = auto_widget_anon_in_a_bits_mask; // @[LazyModuleImp.scala:138:7] wire [127:0] auto_widget_anon_in_a_bits_data_0 = auto_widget_anon_in_a_bits_data; // @[LazyModuleImp.scala:138:7] wire auto_widget_anon_in_a_bits_corrupt_0 = auto_widget_anon_in_a_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire auto_widget_anon_in_d_ready_0 = auto_widget_anon_in_d_ready; // @[LazyModuleImp.scala:138:7] wire auto_bus_xing_out_a_ready_0 = auto_bus_xing_out_a_ready; // @[LazyModuleImp.scala:138:7] wire auto_bus_xing_out_d_valid_0 = auto_bus_xing_out_d_valid; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_bus_xing_out_d_bits_opcode_0 = auto_bus_xing_out_d_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [1:0] auto_bus_xing_out_d_bits_param_0 = auto_bus_xing_out_d_bits_param; // @[LazyModuleImp.scala:138:7] wire [3:0] auto_bus_xing_out_d_bits_size_0 = auto_bus_xing_out_d_bits_size; // @[LazyModuleImp.scala:138:7] wire [5:0] auto_bus_xing_out_d_bits_source_0 = auto_bus_xing_out_d_bits_source; // @[LazyModuleImp.scala:138:7] wire auto_bus_xing_out_d_bits_sink_0 = auto_bus_xing_out_d_bits_sink; // @[LazyModuleImp.scala:138:7] wire auto_bus_xing_out_d_bits_denied_0 = auto_bus_xing_out_d_bits_denied; // @[LazyModuleImp.scala:138:7] wire [63:0] auto_bus_xing_out_d_bits_data_0 = auto_bus_xing_out_d_bits_data; // @[LazyModuleImp.scala:138:7] wire auto_bus_xing_out_d_bits_corrupt_0 = auto_bus_xing_out_d_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire bus_xingOut_a_ready = auto_bus_xing_out_a_ready_0; // @[MixedNode.scala:542:17] wire bus_xingOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] bus_xingOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] bus_xingOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] bus_xingOut_a_bits_size; // @[MixedNode.scala:542:17] wire [5:0] bus_xingOut_a_bits_source; // @[MixedNode.scala:542:17] wire [28:0] bus_xingOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] bus_xingOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] bus_xingOut_a_bits_data; // @[MixedNode.scala:542:17] wire bus_xingOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire bus_xingOut_d_ready; // @[MixedNode.scala:542:17] wire bus_xingOut_d_valid = auto_bus_xing_out_d_valid_0; // @[MixedNode.scala:542:17] wire [2:0] bus_xingOut_d_bits_opcode = auto_bus_xing_out_d_bits_opcode_0; // @[MixedNode.scala:542:17] wire [1:0] bus_xingOut_d_bits_param = auto_bus_xing_out_d_bits_param_0; // @[MixedNode.scala:542:17] wire [3:0] bus_xingOut_d_bits_size = auto_bus_xing_out_d_bits_size_0; // @[MixedNode.scala:542:17] wire [5:0] bus_xingOut_d_bits_source = auto_bus_xing_out_d_bits_source_0; // @[MixedNode.scala:542:17] wire bus_xingOut_d_bits_sink = auto_bus_xing_out_d_bits_sink_0; // @[MixedNode.scala:542:17] wire bus_xingOut_d_bits_denied = auto_bus_xing_out_d_bits_denied_0; // @[MixedNode.scala:542:17] wire [63:0] bus_xingOut_d_bits_data = auto_bus_xing_out_d_bits_data_0; // @[MixedNode.scala:542:17] wire bus_xingOut_d_bits_corrupt = auto_bus_xing_out_d_bits_corrupt_0; // @[MixedNode.scala:542:17] wire auto_widget_anon_in_a_ready_0; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_widget_anon_in_d_bits_opcode_0; // @[LazyModuleImp.scala:138:7] wire [1:0] auto_widget_anon_in_d_bits_param_0; // @[LazyModuleImp.scala:138:7] wire [3:0] auto_widget_anon_in_d_bits_size_0; // @[LazyModuleImp.scala:138:7] wire [5:0] auto_widget_anon_in_d_bits_source_0; // @[LazyModuleImp.scala:138:7] wire auto_widget_anon_in_d_bits_sink_0; // @[LazyModuleImp.scala:138:7] wire auto_widget_anon_in_d_bits_denied_0; // @[LazyModuleImp.scala:138:7] wire [127:0] auto_widget_anon_in_d_bits_data_0; // @[LazyModuleImp.scala:138:7] wire auto_widget_anon_in_d_bits_corrupt_0; // @[LazyModuleImp.scala:138:7] wire auto_widget_anon_in_d_valid_0; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_bus_xing_out_a_bits_opcode_0; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_bus_xing_out_a_bits_param_0; // @[LazyModuleImp.scala:138:7] wire [3:0] auto_bus_xing_out_a_bits_size_0; // @[LazyModuleImp.scala:138:7] wire [5:0] auto_bus_xing_out_a_bits_source_0; // @[LazyModuleImp.scala:138:7] wire [28:0] auto_bus_xing_out_a_bits_address_0; // @[LazyModuleImp.scala:138:7] wire [7:0] auto_bus_xing_out_a_bits_mask_0; // @[LazyModuleImp.scala:138:7] wire [63:0] auto_bus_xing_out_a_bits_data_0; // @[LazyModuleImp.scala:138:7] wire auto_bus_xing_out_a_bits_corrupt_0; // @[LazyModuleImp.scala:138:7] wire auto_bus_xing_out_a_valid_0; // @[LazyModuleImp.scala:138:7] wire auto_bus_xing_out_d_ready_0; // @[LazyModuleImp.scala:138:7] wire bus_xingIn_a_ready = bus_xingOut_a_ready; // @[MixedNode.scala:542:17, :551:17] wire bus_xingIn_a_valid; // @[MixedNode.scala:551:17] assign auto_bus_xing_out_a_valid_0 = bus_xingOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] bus_xingIn_a_bits_opcode; // @[MixedNode.scala:551:17] assign auto_bus_xing_out_a_bits_opcode_0 = bus_xingOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] bus_xingIn_a_bits_param; // @[MixedNode.scala:551:17] assign auto_bus_xing_out_a_bits_param_0 = bus_xingOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] bus_xingIn_a_bits_size; // @[MixedNode.scala:551:17] assign auto_bus_xing_out_a_bits_size_0 = bus_xingOut_a_bits_size; // @[MixedNode.scala:542:17] wire [5:0] bus_xingIn_a_bits_source; // @[MixedNode.scala:551:17] assign auto_bus_xing_out_a_bits_source_0 = bus_xingOut_a_bits_source; // @[MixedNode.scala:542:17] wire [28:0] bus_xingIn_a_bits_address; // @[MixedNode.scala:551:17] assign auto_bus_xing_out_a_bits_address_0 = bus_xingOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] bus_xingIn_a_bits_mask; // @[MixedNode.scala:551:17] assign auto_bus_xing_out_a_bits_mask_0 = bus_xingOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] bus_xingIn_a_bits_data; // @[MixedNode.scala:551:17] assign auto_bus_xing_out_a_bits_data_0 = bus_xingOut_a_bits_data; // @[MixedNode.scala:542:17] wire bus_xingIn_a_bits_corrupt; // @[MixedNode.scala:551:17] assign auto_bus_xing_out_a_bits_corrupt_0 = bus_xingOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire bus_xingIn_d_ready; // @[MixedNode.scala:551:17] assign auto_bus_xing_out_d_ready_0 = bus_xingOut_d_ready; // @[MixedNode.scala:542:17] wire bus_xingIn_d_valid = bus_xingOut_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] bus_xingIn_d_bits_opcode = bus_xingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] bus_xingIn_d_bits_param = bus_xingOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] bus_xingIn_d_bits_size = bus_xingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [5:0] bus_xingIn_d_bits_source = bus_xingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire bus_xingIn_d_bits_sink = bus_xingOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire bus_xingIn_d_bits_denied = bus_xingOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] bus_xingIn_d_bits_data = bus_xingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire bus_xingIn_d_bits_corrupt = bus_xingOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_valid = bus_xingIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_opcode = bus_xingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_param = bus_xingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_size = bus_xingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_source = bus_xingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_address = bus_xingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_mask = bus_xingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_data = bus_xingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_corrupt = bus_xingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_d_ready = bus_xingIn_d_ready; // @[MixedNode.scala:542:17, :551:17] TLWidthWidget16 widget ( // @[WidthWidget.scala:230:28] .clock (clock), .reset (reset), .auto_anon_in_a_ready (auto_widget_anon_in_a_ready_0), .auto_anon_in_a_valid (auto_widget_anon_in_a_valid_0), // @[LazyModuleImp.scala:138:7] .auto_anon_in_a_bits_opcode (auto_widget_anon_in_a_bits_opcode_0), // @[LazyModuleImp.scala:138:7] .auto_anon_in_a_bits_param (auto_widget_anon_in_a_bits_param_0), // @[LazyModuleImp.scala:138:7] .auto_anon_in_a_bits_size (auto_widget_anon_in_a_bits_size_0), // @[LazyModuleImp.scala:138:7] .auto_anon_in_a_bits_source (auto_widget_anon_in_a_bits_source_0), // @[LazyModuleImp.scala:138:7] .auto_anon_in_a_bits_address (auto_widget_anon_in_a_bits_address_0), // @[LazyModuleImp.scala:138:7] .auto_anon_in_a_bits_mask (auto_widget_anon_in_a_bits_mask_0), // @[LazyModuleImp.scala:138:7] .auto_anon_in_a_bits_data (auto_widget_anon_in_a_bits_data_0), // @[LazyModuleImp.scala:138:7] .auto_anon_in_a_bits_corrupt (auto_widget_anon_in_a_bits_corrupt_0), // @[LazyModuleImp.scala:138:7] .auto_anon_in_d_ready (auto_widget_anon_in_d_ready_0), // @[LazyModuleImp.scala:138:7] .auto_anon_in_d_valid (auto_widget_anon_in_d_valid_0), .auto_anon_in_d_bits_opcode (auto_widget_anon_in_d_bits_opcode_0), .auto_anon_in_d_bits_param (auto_widget_anon_in_d_bits_param_0), .auto_anon_in_d_bits_size (auto_widget_anon_in_d_bits_size_0), .auto_anon_in_d_bits_source (auto_widget_anon_in_d_bits_source_0), .auto_anon_in_d_bits_sink (auto_widget_anon_in_d_bits_sink_0), .auto_anon_in_d_bits_denied (auto_widget_anon_in_d_bits_denied_0), .auto_anon_in_d_bits_data (auto_widget_anon_in_d_bits_data_0), .auto_anon_in_d_bits_corrupt (auto_widget_anon_in_d_bits_corrupt_0), .auto_anon_out_a_ready (bus_xingIn_a_ready), // @[MixedNode.scala:551:17] .auto_anon_out_a_valid (bus_xingIn_a_valid), .auto_anon_out_a_bits_opcode (bus_xingIn_a_bits_opcode), .auto_anon_out_a_bits_param (bus_xingIn_a_bits_param), .auto_anon_out_a_bits_size (bus_xingIn_a_bits_size), .auto_anon_out_a_bits_source (bus_xingIn_a_bits_source), .auto_anon_out_a_bits_address (bus_xingIn_a_bits_address), .auto_anon_out_a_bits_mask (bus_xingIn_a_bits_mask), .auto_anon_out_a_bits_data (bus_xingIn_a_bits_data), .auto_anon_out_a_bits_corrupt (bus_xingIn_a_bits_corrupt), .auto_anon_out_d_ready (bus_xingIn_d_ready), .auto_anon_out_d_valid (bus_xingIn_d_valid), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_opcode (bus_xingIn_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_param (bus_xingIn_d_bits_param), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_size (bus_xingIn_d_bits_size), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_source (bus_xingIn_d_bits_source), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_sink (bus_xingIn_d_bits_sink), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_denied (bus_xingIn_d_bits_denied), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_data (bus_xingIn_d_bits_data), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_corrupt (bus_xingIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[WidthWidget.scala:230:28] assign auto_widget_anon_in_a_ready = auto_widget_anon_in_a_ready_0; // @[LazyModuleImp.scala:138:7] assign auto_widget_anon_in_d_valid = auto_widget_anon_in_d_valid_0; // @[LazyModuleImp.scala:138:7] assign auto_widget_anon_in_d_bits_opcode = auto_widget_anon_in_d_bits_opcode_0; // @[LazyModuleImp.scala:138:7] assign auto_widget_anon_in_d_bits_param = auto_widget_anon_in_d_bits_param_0; // @[LazyModuleImp.scala:138:7] assign auto_widget_anon_in_d_bits_size = auto_widget_anon_in_d_bits_size_0; // @[LazyModuleImp.scala:138:7] assign auto_widget_anon_in_d_bits_source = auto_widget_anon_in_d_bits_source_0; // @[LazyModuleImp.scala:138:7] assign auto_widget_anon_in_d_bits_sink = auto_widget_anon_in_d_bits_sink_0; // @[LazyModuleImp.scala:138:7] assign auto_widget_anon_in_d_bits_denied = auto_widget_anon_in_d_bits_denied_0; // @[LazyModuleImp.scala:138:7] assign auto_widget_anon_in_d_bits_data = auto_widget_anon_in_d_bits_data_0; // @[LazyModuleImp.scala:138:7] assign auto_widget_anon_in_d_bits_corrupt = auto_widget_anon_in_d_bits_corrupt_0; // @[LazyModuleImp.scala:138:7] assign auto_bus_xing_out_a_valid = auto_bus_xing_out_a_valid_0; // @[LazyModuleImp.scala:138:7] assign auto_bus_xing_out_a_bits_opcode = auto_bus_xing_out_a_bits_opcode_0; // @[LazyModuleImp.scala:138:7] assign auto_bus_xing_out_a_bits_param = auto_bus_xing_out_a_bits_param_0; // @[LazyModuleImp.scala:138:7] assign auto_bus_xing_out_a_bits_size = auto_bus_xing_out_a_bits_size_0; // @[LazyModuleImp.scala:138:7] assign auto_bus_xing_out_a_bits_source = auto_bus_xing_out_a_bits_source_0; // @[LazyModuleImp.scala:138:7] assign auto_bus_xing_out_a_bits_address = auto_bus_xing_out_a_bits_address_0; // @[LazyModuleImp.scala:138:7] assign auto_bus_xing_out_a_bits_mask = auto_bus_xing_out_a_bits_mask_0; // @[LazyModuleImp.scala:138:7] assign auto_bus_xing_out_a_bits_data = auto_bus_xing_out_a_bits_data_0; // @[LazyModuleImp.scala:138:7] assign auto_bus_xing_out_a_bits_corrupt = auto_bus_xing_out_a_bits_corrupt_0; // @[LazyModuleImp.scala:138:7] assign auto_bus_xing_out_d_ready = auto_bus_xing_out_d_ready_0; // @[LazyModuleImp.scala:138:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{ AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry, IdRange, RegionType, TransferSizes } import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions} import freechips.rocketchip.util.{ AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase, CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct } import scala.math.max //These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel case class TLMasterToSlaveTransferSizes( // Supports both Acquire+Release of the following two sizes: acquireT: TransferSizes = TransferSizes.none, acquireB: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none) extends TLCommonTransferSizes { def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .intersect(rhs.acquireT), acquireB = acquireB .intersect(rhs.acquireB), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint)) def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .mincover(rhs.acquireT), acquireB = acquireB .mincover(rhs.acquireB), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint)) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(acquireT, "T"), str(acquireB, "B"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""acquireT = ${acquireT} |acquireB = ${acquireB} |arithmetic = ${arithmetic} |logical = ${logical} |get = ${get} |putFull = ${putFull} |putPartial = ${putPartial} |hint = ${hint} | |""".stripMargin } } object TLMasterToSlaveTransferSizes { def unknownEmits = TLMasterToSlaveTransferSizes( acquireT = TransferSizes(1, 4096), acquireB = TransferSizes(1, 4096), arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096)) def unknownSupports = TLMasterToSlaveTransferSizes() } //These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel case class TLSlaveToMasterTransferSizes( probe: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none ) extends TLCommonTransferSizes { def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .intersect(rhs.probe), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint) ) def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .mincover(rhs.probe), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint) ) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(probe, "P"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""probe = ${probe} |arithmetic = ${arithmetic} |logical = ${logical} |get = ${get} |putFull = ${putFull} |putPartial = ${putPartial} |hint = ${hint} | |""".stripMargin } } object TLSlaveToMasterTransferSizes { def unknownEmits = TLSlaveToMasterTransferSizes( arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096), probe = TransferSizes(1, 4096)) def unknownSupports = TLSlaveToMasterTransferSizes() } trait TLCommonTransferSizes { def arithmetic: TransferSizes def logical: TransferSizes def get: TransferSizes def putFull: TransferSizes def putPartial: TransferSizes def hint: TransferSizes } class TLSlaveParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], setName: Option[String], val address: Seq[AddressSet], val regionType: RegionType.T, val executable: Boolean, val fifoId: Option[Int], val supports: TLMasterToSlaveTransferSizes, val emits: TLSlaveToMasterTransferSizes, // By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation) val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData // If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order // Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck // ReleaseAck may NEVER be denied extends SimpleProduct { def sortedAddress = address.sorted override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters] override def productPrefix = "TLSlaveParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 11 def productElement(n: Int): Any = n match { case 0 => name case 1 => address case 2 => resources case 3 => regionType case 4 => executable case 5 => fifoId case 6 => supports case 7 => emits case 8 => alwaysGrantsT case 9 => mayDenyGet case 10 => mayDenyPut case _ => throw new IndexOutOfBoundsException(n.toString) } def supportsAcquireT: TransferSizes = supports.acquireT def supportsAcquireB: TransferSizes = supports.acquireB def supportsArithmetic: TransferSizes = supports.arithmetic def supportsLogical: TransferSizes = supports.logical def supportsGet: TransferSizes = supports.get def supportsPutFull: TransferSizes = supports.putFull def supportsPutPartial: TransferSizes = supports.putPartial def supportsHint: TransferSizes = supports.hint require (!address.isEmpty, "Address cannot be empty") address.foreach { a => require (a.finite, "Address must be finite") } address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)") require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)") require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)") require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)") require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)") require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)") require (!alwaysGrantsT || supportsAcquireT, s"Must supportAcquireT if promising to always grantT") // Make sure that the regionType agrees with the capabilities require (!supportsAcquireB || regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached require (regionType <= RegionType.UNCACHED || supportsAcquireB) // tracked, cached -> acquire require (regionType != RegionType.UNCACHED || supportsGet) // uncached -> supportsGet val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected") val maxTransfer = List( // Largest supported transfer of all types supportsAcquireT.max, supportsAcquireB.max, supportsArithmetic.max, supportsLogical.max, supportsGet.max, supportsPutFull.max, supportsPutPartial.max).max val maxAddress = address.map(_.max).max val minAlignment = address.map(_.alignment).min // The device had better not support a transfer larger than its alignment require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)") def toResource: ResourceAddress = { ResourceAddress(address, ResourcePermissions( r = supportsAcquireB || supportsGet, w = supportsAcquireT || supportsPutFull, x = executable, c = supportsAcquireB, a = supportsArithmetic && supportsLogical)) } def findTreeViolation() = nodePath.find { case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false case _: SinkNode[_, _, _, _, _] => false case node => node.inputs.size != 1 } def isTree = findTreeViolation() == None def infoString = { s"""Slave Name = ${name} |Slave Address = ${address} |supports = ${supports.infoString} | |""".stripMargin } def v1copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { new TLSlaveParameters( setName = setName, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = emits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: Option[String] = setName, address: Seq[AddressSet] = address, regionType: RegionType.T = regionType, executable: Boolean = executable, fifoId: Option[Int] = fifoId, supports: TLMasterToSlaveTransferSizes = supports, emits: TLSlaveToMasterTransferSizes = emits, alwaysGrantsT: Boolean = alwaysGrantsT, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } @deprecated("Use v1copy instead of copy","") def copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { v1copy( address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supportsAcquireT = supportsAcquireT, supportsAcquireB = supportsAcquireB, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } } object TLSlaveParameters { def v1( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = { new TLSlaveParameters( setName = None, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLSlaveToMasterTransferSizes.unknownEmits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2( address: Seq[AddressSet], nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Seq(), name: Option[String] = None, regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, fifoId: Option[Int] = None, supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports, emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits, alwaysGrantsT: Boolean = false, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } } object TLManagerParameters { @deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","") def apply( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = TLSlaveParameters.v1( address, resources, regionType, executable, nodePath, supportsAcquireT, supportsAcquireB, supportsArithmetic, supportsLogical, supportsGet, supportsPutFull, supportsPutPartial, supportsHint, mayDenyGet, mayDenyPut, alwaysGrantsT, fifoId, ) } case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int]) { def members = Seq(a, b, c, d) members.collect { case Some(beatBytes) => require (isPow2(beatBytes), "Data channel width must be a power of 2") } } object TLChannelBeatBytes{ def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes( Some(beatBytes), Some(beatBytes), Some(beatBytes), Some(beatBytes)) def apply(): TLChannelBeatBytes = TLChannelBeatBytes( None, None, None, None) } class TLSlavePortParameters private( val slaves: Seq[TLSlaveParameters], val channelBytes: TLChannelBeatBytes, val endSinkId: Int, val minLatency: Int, val responseFields: Seq[BundleFieldBase], val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct { def sortedSlaves = slaves.sortBy(_.sortedAddress.head) override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters] override def productPrefix = "TLSlavePortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => slaves case 1 => channelBytes case 2 => endSinkId case 3 => minLatency case 4 => responseFields case 5 => requestKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!slaves.isEmpty, "Slave ports must have slaves") require (endSinkId >= 0, "Sink ids cannot be negative") require (minLatency >= 0, "Minimum required latency cannot be negative") // Using this API implies you cannot handle mixed-width busses def beatBytes = { channelBytes.members.foreach { width => require (width.isDefined && width == channelBytes.a) } channelBytes.a.get } // TODO this should be deprecated def managers = slaves def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = { val relevant = slaves.filter(m => policy(m)) relevant.foreach { m => require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ") } } // Bounds on required sizes def maxAddress = slaves.map(_.maxAddress).max def maxTransfer = slaves.map(_.maxTransfer).max def mayDenyGet = slaves.exists(_.mayDenyGet) def mayDenyPut = slaves.exists(_.mayDenyPut) // Diplomatically determined operation sizes emitted by all outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _) // Operation Emitted by at least one outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _) val allSupportAcquireT = allSupportClaims.acquireT val allSupportAcquireB = allSupportClaims.acquireB val allSupportArithmetic = allSupportClaims.arithmetic val allSupportLogical = allSupportClaims.logical val allSupportGet = allSupportClaims.get val allSupportPutFull = allSupportClaims.putFull val allSupportPutPartial = allSupportClaims.putPartial val allSupportHint = allSupportClaims.hint // Operation supported by at least one outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _) val anySupportAcquireT = !anySupportClaims.acquireT.none val anySupportAcquireB = !anySupportClaims.acquireB.none val anySupportArithmetic = !anySupportClaims.arithmetic.none val anySupportLogical = !anySupportClaims.logical.none val anySupportGet = !anySupportClaims.get.none val anySupportPutFull = !anySupportClaims.putFull.none val anySupportPutPartial = !anySupportClaims.putPartial.none val anySupportHint = !anySupportClaims.hint.none // Supporting Acquire means being routable for GrantAck require ((endSinkId == 0) == !anySupportAcquireB) // These return Option[TLSlaveParameters] for your convenience def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address))) // The safe version will check the entire address def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ || _))) // The fast version assumes the address is valid (you probably want fastProperty instead of this function) def findFast(address: UInt) = { val routingMask = AddressDecoder(slaves.map(_.address)) VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ || _))) } // Compute the simplest AddressSets that decide a key def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = { val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) => k -> vs.flatMap(_._2) } val reductionMask = AddressDecoder(groups.map(_._2)) groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) } } // Select a property def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D = Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_||_), d(v)) }) // Note: returns the actual fifoId + 1 or 0 if None def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U) def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B) // Does this Port manage this ID/address? def containsSafe(address: UInt) = findSafe(address).reduce(_ || _) private def addressHelper( // setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity safe: Boolean, // member filters out the sizes being checked based on the opcode being emitted or supported member: TLSlaveParameters => TransferSizes, address: UInt, lgSize: UInt, // range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity range: Option[TransferSizes]): Bool = { // trim reduces circuit complexity by intersecting checked sizes with the range argument def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x) // groupBy returns an unordered map, convert back to Seq and sort the result for determinism // groupByIntoSeq is turning slaves into trimmed membership sizes // We are grouping all the slaves by their transfer size where // if they support the trimmed size then // member is the type of transfer that you are looking for (What you are trying to filter on) // When you consider membership, you are trimming the sizes to only the ones that you care about // you are filtering the slaves based on both whether they support a particular opcode and the size // Grouping the slaves based on the actual transfer size range they support // intersecting the range and checking their membership // FOR SUPPORTCASES instead of returning the list of slaves, // you are returning a map from transfer size to the set of // address sets that are supported for that transfer size // find all the slaves that support a certain type of operation and then group their addresses by the supported size // for every size there could be multiple address ranges // safety is a trade off between checking between all possible addresses vs only the addresses // that are known to have supported sizes // the trade off is 'checking all addresses is a more expensive circuit but will always give you // the right answer even if you give it an illegal address' // the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer // fast presumes address legality // This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies. // In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size. val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) => k -> vs.flatMap(_.address) } // safe produces a circuit that compares against all possible addresses, // whereas fast presumes that the address is legal but uses an efficient address decoder val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2)) // Simplified creates the most concise possible representation of each cases' address sets based on the mask. val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) } simplified.map { case (s, a) => // s is a size, you are checking for this size either the size of the operation is in s // We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire. ((Some(s) == range).B || s.containsLg(lgSize)) && a.map(_.contains(address)).reduce(_||_) }.foldLeft(false.B)(_||_) } def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range) def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range) def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range) def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range) def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range) def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range) def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range) def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range) def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range) def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range) def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range) def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range) def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range) def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range) def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range) def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range) def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range) def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range) def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range) def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range) def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range) def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range) def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range) def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption def isTree = !slaves.exists(!_.isTree) def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString def v1copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = managers, channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } def v2copy( slaves: Seq[TLSlaveParameters] = slaves, channelBytes: TLChannelBeatBytes = channelBytes, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = slaves, channelBytes = channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } @deprecated("Use v1copy instead of copy","") def copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { v1copy( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } object TLSlavePortParameters { def v1( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { new TLSlavePortParameters( slaves = managers, channelBytes = TLChannelBeatBytes(beatBytes), endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } } object TLManagerPortParameters { @deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","") def apply( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { TLSlavePortParameters.v1( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } class TLMasterParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], val name: String, val visibility: Seq[AddressSet], val unusedRegionTypes: Set[RegionType.T], val executesOnly: Boolean, val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C. val supports: TLSlaveToMasterTransferSizes, val emits: TLMasterToSlaveTransferSizes, val neverReleasesData: Boolean, val sourceId: IdRange) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters] override def productPrefix = "TLMasterParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 10 def productElement(n: Int): Any = n match { case 0 => name case 1 => sourceId case 2 => resources case 3 => visibility case 4 => unusedRegionTypes case 5 => executesOnly case 6 => requestFifo case 7 => supports case 8 => emits case 9 => neverReleasesData case _ => throw new IndexOutOfBoundsException(n.toString) } require (!sourceId.isEmpty) require (!visibility.isEmpty) require (supports.putFull.contains(supports.putPartial)) // We only support these operations if we support Probe (ie: we're a cache) require (supports.probe.contains(supports.arithmetic)) require (supports.probe.contains(supports.logical)) require (supports.probe.contains(supports.get)) require (supports.probe.contains(supports.putFull)) require (supports.probe.contains(supports.putPartial)) require (supports.probe.contains(supports.hint)) visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } val maxTransfer = List( supports.probe.max, supports.arithmetic.max, supports.logical.max, supports.get.max, supports.putFull.max, supports.putPartial.max).max def infoString = { s"""Master Name = ${name} |visibility = ${visibility} |emits = ${emits.infoString} |sourceId = ${sourceId} | |""".stripMargin } def v1copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { new TLMasterParameters( nodePath = nodePath, resources = this.resources, name = name, visibility = visibility, unusedRegionTypes = this.unusedRegionTypes, executesOnly = this.executesOnly, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = this.emits, neverReleasesData = this.neverReleasesData, sourceId = sourceId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: String = name, visibility: Seq[AddressSet] = visibility, unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes, executesOnly: Boolean = executesOnly, requestFifo: Boolean = requestFifo, supports: TLSlaveToMasterTransferSizes = supports, emits: TLMasterToSlaveTransferSizes = emits, neverReleasesData: Boolean = neverReleasesData, sourceId: IdRange = sourceId) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } @deprecated("Use v1copy instead of copy","") def copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { v1copy( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } object TLMasterParameters { def v1( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { new TLMasterParameters( nodePath = nodePath, resources = Nil, name = name, visibility = visibility, unusedRegionTypes = Set(), executesOnly = false, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData = false, sourceId = sourceId) } def v2( nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Nil, name: String, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), unusedRegionTypes: Set[RegionType.T] = Set(), executesOnly: Boolean = false, requestFifo: Boolean = false, supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports, emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData: Boolean = false, sourceId: IdRange = IdRange(0,1)) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } } object TLClientParameters { @deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","") def apply( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet.everything), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { TLMasterParameters.v1( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } class TLMasterPortParameters private( val masters: Seq[TLMasterParameters], val channelBytes: TLChannelBeatBytes, val minLatency: Int, val echoFields: Seq[BundleFieldBase], val requestFields: Seq[BundleFieldBase], val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters] override def productPrefix = "TLMasterPortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => masters case 1 => channelBytes case 2 => minLatency case 3 => echoFields case 4 => requestFields case 5 => responseKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!masters.isEmpty) require (minLatency >= 0) def clients = masters // Require disjoint ranges for Ids IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) => require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}") } // Bounds on required sizes def endSourceId = masters.map(_.sourceId.end).max def maxTransfer = masters.map(_.maxTransfer).max // The unused sources < endSourceId def unusedSources: Seq[Int] = { val usedSources = masters.map(_.sourceId).sortBy(_.start) ((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) => end until start } } // Diplomatically determined operation sizes emitted by all inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = masters.map(_.emits).reduce( _ intersect _) // Diplomatically determined operation sizes Emitted by at least one inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all inward Masters // as opposed to supports* which generate circuitry to check which specific addresses val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _) val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _) val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _) val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _) val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _) val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _) val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _) // Diplomatically determined operation sizes supported by at least one master // as opposed to supports* which generate circuitry to check which specific addresses val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ || _) val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ || _) val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ || _) val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ || _) val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ || _) val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ || _) val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ || _) // These return Option[TLMasterParameters] for your convenience def find(id: Int) = masters.find(_.sourceId.contains(id)) // Synthesizable lookup methods def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id))) def contains(id: UInt) = find(id).reduce(_ || _) def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B)) // Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = { val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _) // this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version; // the case where there is only one group. if (allSame) member(masters(0)).containsLg(lgSize) else { // Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize Mux1H(find(id), masters.map(member(_).containsLg(lgSize))) } } // Check for support of a given operation at a specific id val supportsProbe = sourceIdHelper(_.supports.probe) _ val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _ val supportsLogical = sourceIdHelper(_.supports.logical) _ val supportsGet = sourceIdHelper(_.supports.get) _ val supportsPutFull = sourceIdHelper(_.supports.putFull) _ val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _ val supportsHint = sourceIdHelper(_.supports.hint) _ // TODO: Merge sourceIdHelper2 with sourceIdHelper private def sourceIdHelper2( member: TLMasterParameters => TransferSizes, sourceId: UInt, lgSize: UInt): Bool = { // Because sourceIds are uniquely owned by each master, we use them to group the // cases that have to be checked. val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) => k -> vs.map(_.sourceId) } emitCases.map { case (s, a) => (s.containsLg(lgSize)) && a.map(_.contains(sourceId)).reduce(_||_) }.foldLeft(false.B)(_||_) } // Check for emit of a given operation at a specific id def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize) def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize) def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize) def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize) def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize) def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize) def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize) def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize) def infoString = masters.map(_.infoString).mkString def v1copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = clients, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2copy( masters: Seq[TLMasterParameters] = masters, channelBytes: TLChannelBeatBytes = channelBytes, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } @deprecated("Use v1copy instead of copy","") def copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { v1copy( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLClientPortParameters { @deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","") def apply( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { TLMasterPortParameters.v1( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLMasterPortParameters { def v1( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = clients, channelBytes = TLChannelBeatBytes(), minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2( masters: Seq[TLMasterParameters], channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(), minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } } case class TLBundleParameters( addressBits: Int, dataBits: Int, sourceBits: Int, sinkBits: Int, sizeBits: Int, echoFields: Seq[BundleFieldBase], requestFields: Seq[BundleFieldBase], responseFields: Seq[BundleFieldBase], hasBCE: Boolean) { // Chisel has issues with 0-width wires require (addressBits >= 1) require (dataBits >= 8) require (sourceBits >= 1) require (sinkBits >= 1) require (sizeBits >= 1) require (isPow2(dataBits)) echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") } val addrLoBits = log2Up(dataBits/8) // Used to uniquify bus IP names def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u") def union(x: TLBundleParameters) = TLBundleParameters( max(addressBits, x.addressBits), max(dataBits, x.dataBits), max(sourceBits, x.sourceBits), max(sinkBits, x.sinkBits), max(sizeBits, x.sizeBits), echoFields = BundleField.union(echoFields ++ x.echoFields), requestFields = BundleField.union(requestFields ++ x.requestFields), responseFields = BundleField.union(responseFields ++ x.responseFields), hasBCE || x.hasBCE) } object TLBundleParameters { val emptyBundleParams = TLBundleParameters( addressBits = 1, dataBits = 8, sourceBits = 1, sinkBits = 1, sizeBits = 1, echoFields = Nil, requestFields = Nil, responseFields = Nil, hasBCE = false) def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y)) def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) = new TLBundleParameters( addressBits = log2Up(slave.maxAddress + 1), dataBits = slave.beatBytes * 8, sourceBits = log2Up(master.endSourceId), sinkBits = log2Up(slave.endSinkId), sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1), echoFields = master.echoFields, requestFields = BundleField.accept(master.requestFields, slave.requestKeys), responseFields = BundleField.accept(slave.responseFields, master.responseKeys), hasBCE = master.anySupportProbe && slave.anySupportAcquireB) } case class TLEdgeParameters( master: TLMasterPortParameters, slave: TLSlavePortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { // legacy names: def manager = slave def client = master val maxTransfer = max(master.maxTransfer, slave.maxTransfer) val maxLgSize = log2Ceil(maxTransfer) // Sanity check the link... require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})") def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims) val bundle = TLBundleParameters(master, slave) def formatEdge = master.infoString + "\n" + slave.infoString } case class TLCreditedDelay( a: CreditedDelay, b: CreditedDelay, c: CreditedDelay, d: CreditedDelay, e: CreditedDelay) { def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay( a = a + that.a, b = b + that.b, c = c + that.c, d = d + that.d, e = e + that.e) override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})" } object TLCreditedDelay { def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay) } case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString} case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val delay = client.delay + manager.delay val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters) case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base)) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } // To be unified, devices must agree on all of these terms case class ManagerUnificationKey( resources: Seq[Resource], regionType: RegionType.T, executable: Boolean, supportsAcquireT: TransferSizes, supportsAcquireB: TransferSizes, supportsArithmetic: TransferSizes, supportsLogical: TransferSizes, supportsGet: TransferSizes, supportsPutFull: TransferSizes, supportsPutPartial: TransferSizes, supportsHint: TransferSizes) object ManagerUnificationKey { def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey( resources = x.resources, regionType = x.regionType, executable = x.executable, supportsAcquireT = x.supportsAcquireT, supportsAcquireB = x.supportsAcquireB, supportsArithmetic = x.supportsArithmetic, supportsLogical = x.supportsLogical, supportsGet = x.supportsGet, supportsPutFull = x.supportsPutFull, supportsPutPartial = x.supportsPutPartial, supportsHint = x.supportsHint) } object ManagerUnification { def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = { slaves.groupBy(ManagerUnificationKey.apply).values.map { seq => val agree = seq.forall(_.fifoId == seq.head.fifoId) seq(0).v1copy( address = AddressSet.unify(seq.flatMap(_.address)), fifoId = if (agree) seq(0).fifoId else None) }.toList } } case class TLBufferParams( a: BufferParams = BufferParams.none, b: BufferParams = BufferParams.none, c: BufferParams = BufferParams.none, d: BufferParams = BufferParams.none, e: BufferParams = BufferParams.none ) extends DirectedBuffers[TLBufferParams] { def copyIn(x: BufferParams) = this.copy(b = x, d = x) def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x) def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x) } /** Pretty printing of TL source id maps */ class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] { private val tlDigits = String.valueOf(tl.endSourceId-1).length() protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s" private val sorted = tl.masters.sortBy(_.sourceId) val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c => TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo) } } case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean) extends IdMapEntry { val from = tlId val to = tlId val maxTransactionsInFlight = Some(tlId.size) } File mshrs.scala: //****************************************************************************** // Ported from Rocket-Chip // See LICENSE.Berkeley and LICENSE.SiFive in Rocket-Chip for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.lsu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.tile._ import freechips.rocketchip.util._ import freechips.rocketchip.rocket._ import boom.v3.common._ import boom.v3.exu.BrUpdateInfo import boom.v3.util.{IsKilledByBranch, GetNewBrMask, BranchKillableQueue, IsOlder, UpdateBrMask, AgePriorityEncoder, WrapInc} class BoomDCacheReqInternal(implicit p: Parameters) extends BoomDCacheReq()(p) with HasL1HellaCacheParameters { // miss info val tag_match = Bool() val old_meta = new L1Metadata val way_en = UInt(nWays.W) // Used in the MSHRs val sdq_id = UInt(log2Ceil(cfg.nSDQ).W) } class BoomMSHR(implicit edge: TLEdgeOut, p: Parameters) extends BoomModule()(p) with HasL1HellaCacheParameters { val io = IO(new Bundle { val id = Input(UInt()) val req_pri_val = Input(Bool()) val req_pri_rdy = Output(Bool()) val req_sec_val = Input(Bool()) val req_sec_rdy = Output(Bool()) val clear_prefetch = Input(Bool()) val brupdate = Input(new BrUpdateInfo) val exception = Input(Bool()) val rob_pnr_idx = Input(UInt(robAddrSz.W)) val rob_head_idx = Input(UInt(robAddrSz.W)) val req = Input(new BoomDCacheReqInternal) val req_is_probe = Input(Bool()) val idx = Output(Valid(UInt())) val way = Output(Valid(UInt())) val tag = Output(Valid(UInt())) val mem_acquire = Decoupled(new TLBundleA(edge.bundle)) val mem_grant = Flipped(Decoupled(new TLBundleD(edge.bundle))) val mem_finish = Decoupled(new TLBundleE(edge.bundle)) val prober_state = Input(Valid(UInt(coreMaxAddrBits.W))) val refill = Decoupled(new L1DataWriteReq) val meta_write = Decoupled(new L1MetaWriteReq) val meta_read = Decoupled(new L1MetaReadReq) val meta_resp = Input(Valid(new L1Metadata)) val wb_req = Decoupled(new WritebackReq(edge.bundle)) // To inform the prefetcher when we are commiting the fetch of this line val commit_val = Output(Bool()) val commit_addr = Output(UInt(coreMaxAddrBits.W)) val commit_coh = Output(new ClientMetadata) // Reading from the line buffer val lb_read = Decoupled(new LineBufferReadReq) val lb_resp = Input(UInt(encRowBits.W)) val lb_write = Decoupled(new LineBufferWriteReq) // Replays go through the cache pipeline again val replay = Decoupled(new BoomDCacheReqInternal) // Resp go straight out to the core val resp = Decoupled(new BoomDCacheResp) // Writeback unit tells us when it is done processing our wb val wb_resp = Input(Bool()) val probe_rdy = Output(Bool()) }) // TODO: Optimize this. We don't want to mess with cache during speculation // s_refill_req : Make a request for a new cache line // s_refill_resp : Store the refill response into our buffer // s_drain_rpq_loads : Drain out loads from the rpq // : If miss was misspeculated, go to s_invalid // s_wb_req : Write back the evicted cache line // s_wb_resp : Finish writing back the evicted cache line // s_meta_write_req : Write the metadata for new cache lne // s_meta_write_resp : val s_invalid :: s_refill_req :: s_refill_resp :: s_drain_rpq_loads :: s_meta_read :: s_meta_resp_1 :: s_meta_resp_2 :: s_meta_clear :: s_wb_meta_read :: s_wb_req :: s_wb_resp :: s_commit_line :: s_drain_rpq :: s_meta_write_req :: s_mem_finish_1 :: s_mem_finish_2 :: s_prefetched :: s_prefetch :: Nil = Enum(18) val state = RegInit(s_invalid) val req = Reg(new BoomDCacheReqInternal) val req_idx = req.addr(untagBits-1, blockOffBits) val req_tag = req.addr >> untagBits val req_block_addr = (req.addr >> blockOffBits) << blockOffBits val req_needs_wb = RegInit(false.B) val new_coh = RegInit(ClientMetadata.onReset) val (_, shrink_param, coh_on_clear) = req.old_meta.coh.onCacheControl(M_FLUSH) val grow_param = new_coh.onAccess(req.uop.mem_cmd)._2 val coh_on_grant = new_coh.onGrant(req.uop.mem_cmd, io.mem_grant.bits.param) // We only accept secondary misses if the original request had sufficient permissions val (cmd_requires_second_acquire, is_hit_again, _, dirtier_coh, dirtier_cmd) = new_coh.onSecondaryAccess(req.uop.mem_cmd, io.req.uop.mem_cmd) val (_, _, refill_done, refill_address_inc) = edge.addr_inc(io.mem_grant) val sec_rdy = (!cmd_requires_second_acquire && !io.req_is_probe && !state.isOneOf(s_invalid, s_meta_write_req, s_mem_finish_1, s_mem_finish_2))// Always accept secondary misses val rpq = Module(new BranchKillableQueue(new BoomDCacheReqInternal, cfg.nRPQ, u => u.uses_ldq, false)) rpq.io.brupdate := io.brupdate rpq.io.flush := io.exception assert(!(state === s_invalid && !rpq.io.empty)) rpq.io.enq.valid := ((io.req_pri_val && io.req_pri_rdy) || (io.req_sec_val && io.req_sec_rdy)) && !isPrefetch(io.req.uop.mem_cmd) rpq.io.enq.bits := io.req rpq.io.deq.ready := false.B val grantack = Reg(Valid(new TLBundleE(edge.bundle))) val refill_ctr = Reg(UInt(log2Ceil(cacheDataBeats).W)) val commit_line = Reg(Bool()) val grant_had_data = Reg(Bool()) val finish_to_prefetch = Reg(Bool()) // Block probes if a tag write we started is still in the pipeline val meta_hazard = RegInit(0.U(2.W)) when (meta_hazard =/= 0.U) { meta_hazard := meta_hazard + 1.U } when (io.meta_write.fire) { meta_hazard := 1.U } io.probe_rdy := (meta_hazard === 0.U && (state.isOneOf(s_invalid, s_refill_req, s_refill_resp, s_drain_rpq_loads) || (state === s_meta_read && grantack.valid))) io.idx.valid := state =/= s_invalid io.tag.valid := state =/= s_invalid io.way.valid := !state.isOneOf(s_invalid, s_prefetch) io.idx.bits := req_idx io.tag.bits := req_tag io.way.bits := req.way_en io.meta_write.valid := false.B io.meta_write.bits := DontCare io.req_pri_rdy := false.B io.req_sec_rdy := sec_rdy && rpq.io.enq.ready io.mem_acquire.valid := false.B io.mem_acquire.bits := DontCare io.refill.valid := false.B io.refill.bits := DontCare io.replay.valid := false.B io.replay.bits := DontCare io.wb_req.valid := false.B io.wb_req.bits := DontCare io.resp.valid := false.B io.resp.bits := DontCare io.commit_val := false.B io.commit_addr := req.addr io.commit_coh := coh_on_grant io.meta_read.valid := false.B io.meta_read.bits := DontCare io.mem_finish.valid := false.B io.mem_finish.bits := DontCare io.lb_write.valid := false.B io.lb_write.bits := DontCare io.lb_read.valid := false.B io.lb_read.bits := DontCare io.mem_grant.ready := false.B when (io.req_sec_val && io.req_sec_rdy) { req.uop.mem_cmd := dirtier_cmd when (is_hit_again) { new_coh := dirtier_coh } } def handle_pri_req(old_state: UInt): UInt = { val new_state = WireInit(old_state) grantack.valid := false.B refill_ctr := 0.U assert(rpq.io.enq.ready) req := io.req val old_coh = io.req.old_meta.coh req_needs_wb := old_coh.onCacheControl(M_FLUSH)._1 // does the line we are evicting need to be written back when (io.req.tag_match) { val (is_hit, _, coh_on_hit) = old_coh.onAccess(io.req.uop.mem_cmd) when (is_hit) { // set dirty bit assert(isWrite(io.req.uop.mem_cmd)) new_coh := coh_on_hit new_state := s_drain_rpq } .otherwise { // upgrade permissions new_coh := old_coh new_state := s_refill_req } } .otherwise { // refill and writeback if necessary new_coh := ClientMetadata.onReset new_state := s_refill_req } new_state } when (state === s_invalid) { io.req_pri_rdy := true.B grant_had_data := false.B when (io.req_pri_val && io.req_pri_rdy) { state := handle_pri_req(state) } } .elsewhen (state === s_refill_req) { io.mem_acquire.valid := true.B // TODO: Use AcquirePerm if just doing permissions acquire io.mem_acquire.bits := edge.AcquireBlock( fromSource = io.id, toAddress = Cat(req_tag, req_idx) << blockOffBits, lgSize = lgCacheBlockBytes.U, growPermissions = grow_param)._2 when (io.mem_acquire.fire) { state := s_refill_resp } } .elsewhen (state === s_refill_resp) { when (edge.hasData(io.mem_grant.bits)) { io.mem_grant.ready := io.lb_write.ready io.lb_write.valid := io.mem_grant.valid io.lb_write.bits.id := io.id io.lb_write.bits.offset := refill_address_inc >> rowOffBits io.lb_write.bits.data := io.mem_grant.bits.data } .otherwise { io.mem_grant.ready := true.B } when (io.mem_grant.fire) { grant_had_data := edge.hasData(io.mem_grant.bits) } when (refill_done) { grantack.valid := edge.isRequest(io.mem_grant.bits) grantack.bits := edge.GrantAck(io.mem_grant.bits) state := Mux(grant_had_data, s_drain_rpq_loads, s_drain_rpq) assert(!(!grant_had_data && req_needs_wb)) commit_line := false.B new_coh := coh_on_grant } } .elsewhen (state === s_drain_rpq_loads) { val drain_load = (isRead(rpq.io.deq.bits.uop.mem_cmd) && !isWrite(rpq.io.deq.bits.uop.mem_cmd) && (rpq.io.deq.bits.uop.mem_cmd =/= M_XLR)) // LR should go through replay // drain all loads for now val rp_addr = Cat(req_tag, req_idx, rpq.io.deq.bits.addr(blockOffBits-1,0)) val word_idx = if (rowWords == 1) 0.U else rp_addr(log2Up(rowWords*coreDataBytes)-1, log2Up(wordBytes)) val data = io.lb_resp val data_word = data >> Cat(word_idx, 0.U(log2Up(coreDataBits).W)) val loadgen = new LoadGen(rpq.io.deq.bits.uop.mem_size, rpq.io.deq.bits.uop.mem_signed, Cat(req_tag, req_idx, rpq.io.deq.bits.addr(blockOffBits-1,0)), data_word, false.B, wordBytes) rpq.io.deq.ready := io.resp.ready && io.lb_read.ready && drain_load io.lb_read.valid := rpq.io.deq.valid && drain_load io.lb_read.bits.id := io.id io.lb_read.bits.offset := rpq.io.deq.bits.addr >> rowOffBits io.resp.valid := rpq.io.deq.valid && io.lb_read.fire && drain_load io.resp.bits.uop := rpq.io.deq.bits.uop io.resp.bits.data := loadgen.data io.resp.bits.is_hella := rpq.io.deq.bits.is_hella when (rpq.io.deq.fire) { commit_line := true.B } .elsewhen (rpq.io.empty && !commit_line) { when (!rpq.io.enq.fire) { state := s_mem_finish_1 finish_to_prefetch := enablePrefetching.B } } .elsewhen (rpq.io.empty || (rpq.io.deq.valid && !drain_load)) { // io.commit_val is for the prefetcher. it tells the prefetcher that this line was correctly acquired // The prefetcher should consider fetching the next line io.commit_val := true.B state := s_meta_read } } .elsewhen (state === s_meta_read) { io.meta_read.valid := !io.prober_state.valid || !grantack.valid || (io.prober_state.bits(untagBits-1,blockOffBits) =/= req_idx) io.meta_read.bits.idx := req_idx io.meta_read.bits.tag := req_tag io.meta_read.bits.way_en := req.way_en when (io.meta_read.fire) { state := s_meta_resp_1 } } .elsewhen (state === s_meta_resp_1) { state := s_meta_resp_2 } .elsewhen (state === s_meta_resp_2) { val needs_wb = io.meta_resp.bits.coh.onCacheControl(M_FLUSH)._1 state := Mux(!io.meta_resp.valid, s_meta_read, // Prober could have nack'd this read Mux(needs_wb, s_meta_clear, s_commit_line)) } .elsewhen (state === s_meta_clear) { io.meta_write.valid := true.B io.meta_write.bits.idx := req_idx io.meta_write.bits.data.coh := coh_on_clear io.meta_write.bits.data.tag := req_tag io.meta_write.bits.way_en := req.way_en when (io.meta_write.fire) { state := s_wb_req } } .elsewhen (state === s_wb_req) { io.wb_req.valid := true.B io.wb_req.bits.tag := req.old_meta.tag io.wb_req.bits.idx := req_idx io.wb_req.bits.param := shrink_param io.wb_req.bits.way_en := req.way_en io.wb_req.bits.source := io.id io.wb_req.bits.voluntary := true.B when (io.wb_req.fire) { state := s_wb_resp } } .elsewhen (state === s_wb_resp) { when (io.wb_resp) { state := s_commit_line } } .elsewhen (state === s_commit_line) { io.lb_read.valid := true.B io.lb_read.bits.id := io.id io.lb_read.bits.offset := refill_ctr io.refill.valid := io.lb_read.fire io.refill.bits.addr := req_block_addr | (refill_ctr << rowOffBits) io.refill.bits.way_en := req.way_en io.refill.bits.wmask := ~(0.U(rowWords.W)) io.refill.bits.data := io.lb_resp when (io.refill.fire) { refill_ctr := refill_ctr + 1.U when (refill_ctr === (cacheDataBeats - 1).U) { state := s_drain_rpq } } } .elsewhen (state === s_drain_rpq) { io.replay <> rpq.io.deq io.replay.bits.way_en := req.way_en io.replay.bits.addr := Cat(req_tag, req_idx, rpq.io.deq.bits.addr(blockOffBits-1,0)) when (io.replay.fire && isWrite(rpq.io.deq.bits.uop.mem_cmd)) { // Set dirty bit val (is_hit, _, coh_on_hit) = new_coh.onAccess(rpq.io.deq.bits.uop.mem_cmd) assert(is_hit, "We still don't have permissions for this store") new_coh := coh_on_hit } when (rpq.io.empty && !rpq.io.enq.valid) { state := s_meta_write_req } } .elsewhen (state === s_meta_write_req) { io.meta_write.valid := true.B io.meta_write.bits.idx := req_idx io.meta_write.bits.data.coh := new_coh io.meta_write.bits.data.tag := req_tag io.meta_write.bits.way_en := req.way_en when (io.meta_write.fire) { state := s_mem_finish_1 finish_to_prefetch := false.B } } .elsewhen (state === s_mem_finish_1) { io.mem_finish.valid := grantack.valid io.mem_finish.bits := grantack.bits when (io.mem_finish.fire || !grantack.valid) { grantack.valid := false.B state := s_mem_finish_2 } } .elsewhen (state === s_mem_finish_2) { state := Mux(finish_to_prefetch, s_prefetch, s_invalid) } .elsewhen (state === s_prefetch) { io.req_pri_rdy := true.B when ((io.req_sec_val && !io.req_sec_rdy) || io.clear_prefetch) { state := s_invalid } .elsewhen (io.req_sec_val && io.req_sec_rdy) { val (is_hit, _, coh_on_hit) = new_coh.onAccess(io.req.uop.mem_cmd) when (is_hit) { // Proceed with refill new_coh := coh_on_hit state := s_meta_read } .otherwise { // Reacquire this line new_coh := ClientMetadata.onReset state := s_refill_req } } .elsewhen (io.req_pri_val && io.req_pri_rdy) { grant_had_data := false.B state := handle_pri_req(state) } } } class BoomIOMSHR(id: Int)(implicit edge: TLEdgeOut, p: Parameters) extends BoomModule()(p) with HasL1HellaCacheParameters { val io = IO(new Bundle { val req = Flipped(Decoupled(new BoomDCacheReq)) val resp = Decoupled(new BoomDCacheResp) val mem_access = Decoupled(new TLBundleA(edge.bundle)) val mem_ack = Flipped(Valid(new TLBundleD(edge.bundle))) // We don't need brupdate in here because uncacheable operations are guaranteed non-speculative }) def beatOffset(addr: UInt) = addr.extract(beatOffBits-1, wordOffBits) def wordFromBeat(addr: UInt, dat: UInt) = { val shift = Cat(beatOffset(addr), 0.U((wordOffBits+log2Ceil(wordBytes)).W)) (dat >> shift)(wordBits-1, 0) } val req = Reg(new BoomDCacheReq) val grant_word = Reg(UInt(wordBits.W)) val s_idle :: s_mem_access :: s_mem_ack :: s_resp :: Nil = Enum(4) val state = RegInit(s_idle) io.req.ready := state === s_idle val loadgen = new LoadGen(req.uop.mem_size, req.uop.mem_signed, req.addr, grant_word, false.B, wordBytes) val a_source = id.U val a_address = req.addr val a_size = req.uop.mem_size val a_data = Fill(beatWords, req.data) val get = edge.Get(a_source, a_address, a_size)._2 val put = edge.Put(a_source, a_address, a_size, a_data)._2 val atomics = if (edge.manager.anySupportLogical) { MuxLookup(req.uop.mem_cmd, (0.U).asTypeOf(new TLBundleA(edge.bundle)))(Array( M_XA_SWAP -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.SWAP)._2, M_XA_XOR -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.XOR) ._2, M_XA_OR -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.OR) ._2, M_XA_AND -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.AND) ._2, M_XA_ADD -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.ADD)._2, M_XA_MIN -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.MIN)._2, M_XA_MAX -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.MAX)._2, M_XA_MINU -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.MINU)._2, M_XA_MAXU -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.MAXU)._2)) } else { // If no managers support atomics, assert fail if processor asks for them assert(state === s_idle || !isAMO(req.uop.mem_cmd)) (0.U).asTypeOf(new TLBundleA(edge.bundle)) } assert(state === s_idle || req.uop.mem_cmd =/= M_XSC) io.mem_access.valid := state === s_mem_access io.mem_access.bits := Mux(isAMO(req.uop.mem_cmd), atomics, Mux(isRead(req.uop.mem_cmd), get, put)) val send_resp = isRead(req.uop.mem_cmd) io.resp.valid := (state === s_resp) && send_resp io.resp.bits.is_hella := req.is_hella io.resp.bits.uop := req.uop io.resp.bits.data := loadgen.data when (io.req.fire) { req := io.req.bits state := s_mem_access } when (io.mem_access.fire) { state := s_mem_ack } when (state === s_mem_ack && io.mem_ack.valid) { state := s_resp when (isRead(req.uop.mem_cmd)) { grant_word := wordFromBeat(req.addr, io.mem_ack.bits.data) } } when (state === s_resp) { when (!send_resp || io.resp.fire) { state := s_idle } } } class LineBufferReadReq(implicit p: Parameters) extends BoomBundle()(p) with HasL1HellaCacheParameters { val id = UInt(log2Ceil(nLBEntries).W) val offset = UInt(log2Ceil(cacheDataBeats).W) def lb_addr = Cat(id, offset) } class LineBufferWriteReq(implicit p: Parameters) extends LineBufferReadReq()(p) { val data = UInt(encRowBits.W) } class LineBufferMetaWriteReq(implicit p: Parameters) extends BoomBundle()(p) { val id = UInt(log2Ceil(nLBEntries).W) val coh = new ClientMetadata val addr = UInt(coreMaxAddrBits.W) } class LineBufferMeta(implicit p: Parameters) extends BoomBundle()(p) with HasL1HellaCacheParameters { val coh = new ClientMetadata val addr = UInt(coreMaxAddrBits.W) } class BoomMSHRFile(implicit edge: TLEdgeOut, p: Parameters) extends BoomModule()(p) with HasL1HellaCacheParameters { val io = IO(new Bundle { val req = Flipped(Vec(memWidth, Decoupled(new BoomDCacheReqInternal))) // Req from s2 of DCache pipe val req_is_probe = Input(Vec(memWidth, Bool())) val resp = Decoupled(new BoomDCacheResp) val secondary_miss = Output(Vec(memWidth, Bool())) val block_hit = Output(Vec(memWidth, Bool())) val brupdate = Input(new BrUpdateInfo) val exception = Input(Bool()) val rob_pnr_idx = Input(UInt(robAddrSz.W)) val rob_head_idx = Input(UInt(robAddrSz.W)) val mem_acquire = Decoupled(new TLBundleA(edge.bundle)) val mem_grant = Flipped(Decoupled(new TLBundleD(edge.bundle))) val mem_finish = Decoupled(new TLBundleE(edge.bundle)) val refill = Decoupled(new L1DataWriteReq) val meta_write = Decoupled(new L1MetaWriteReq) val meta_read = Decoupled(new L1MetaReadReq) val meta_resp = Input(Valid(new L1Metadata)) val replay = Decoupled(new BoomDCacheReqInternal) val prefetch = Decoupled(new BoomDCacheReq) val wb_req = Decoupled(new WritebackReq(edge.bundle)) val prober_state = Input(Valid(UInt(coreMaxAddrBits.W))) val clear_all = Input(Bool()) // Clears all uncommitted MSHRs to prepare for fence val wb_resp = Input(Bool()) val fence_rdy = Output(Bool()) val probe_rdy = Output(Bool()) }) val req_idx = OHToUInt(io.req.map(_.valid)) val req = io.req(req_idx) val req_is_probe = io.req_is_probe(0) for (w <- 0 until memWidth) io.req(w).ready := false.B val prefetcher: DataPrefetcher = if (enablePrefetching) Module(new NLPrefetcher) else Module(new NullPrefetcher) io.prefetch <> prefetcher.io.prefetch val cacheable = edge.manager.supportsAcquireBFast(req.bits.addr, lgCacheBlockBytes.U) // -------------------- // The MSHR SDQ val sdq_val = RegInit(0.U(cfg.nSDQ.W)) val sdq_alloc_id = PriorityEncoder(~sdq_val(cfg.nSDQ-1,0)) val sdq_rdy = !sdq_val.andR val sdq_enq = req.fire && cacheable && isWrite(req.bits.uop.mem_cmd) val sdq = Mem(cfg.nSDQ, UInt(coreDataBits.W)) when (sdq_enq) { sdq(sdq_alloc_id) := req.bits.data } // -------------------- // The LineBuffer Data // Holds refilling lines, prefetched lines val lb = Mem(nLBEntries * cacheDataBeats, UInt(encRowBits.W)) val lb_read_arb = Module(new Arbiter(new LineBufferReadReq, cfg.nMSHRs)) val lb_write_arb = Module(new Arbiter(new LineBufferWriteReq, cfg.nMSHRs)) lb_read_arb.io.out.ready := false.B lb_write_arb.io.out.ready := true.B val lb_read_data = WireInit(0.U(encRowBits.W)) when (lb_write_arb.io.out.fire) { lb.write(lb_write_arb.io.out.bits.lb_addr, lb_write_arb.io.out.bits.data) } .otherwise { lb_read_arb.io.out.ready := true.B when (lb_read_arb.io.out.fire) { lb_read_data := lb.read(lb_read_arb.io.out.bits.lb_addr) } } def widthMap[T <: Data](f: Int => T) = VecInit((0 until memWidth).map(f)) val idx_matches = Wire(Vec(memWidth, Vec(cfg.nMSHRs, Bool()))) val tag_matches = Wire(Vec(memWidth, Vec(cfg.nMSHRs, Bool()))) val way_matches = Wire(Vec(memWidth, Vec(cfg.nMSHRs, Bool()))) val tag_match = widthMap(w => Mux1H(idx_matches(w), tag_matches(w))) val idx_match = widthMap(w => idx_matches(w).reduce(_||_)) val way_match = widthMap(w => Mux1H(idx_matches(w), way_matches(w))) val wb_tag_list = Wire(Vec(cfg.nMSHRs, UInt(tagBits.W))) val meta_write_arb = Module(new Arbiter(new L1MetaWriteReq , cfg.nMSHRs)) val meta_read_arb = Module(new Arbiter(new L1MetaReadReq , cfg.nMSHRs)) val wb_req_arb = Module(new Arbiter(new WritebackReq(edge.bundle), cfg.nMSHRs)) val replay_arb = Module(new Arbiter(new BoomDCacheReqInternal , cfg.nMSHRs)) val resp_arb = Module(new Arbiter(new BoomDCacheResp , cfg.nMSHRs + nIOMSHRs)) val refill_arb = Module(new Arbiter(new L1DataWriteReq , cfg.nMSHRs)) val commit_vals = Wire(Vec(cfg.nMSHRs, Bool())) val commit_addrs = Wire(Vec(cfg.nMSHRs, UInt(coreMaxAddrBits.W))) val commit_cohs = Wire(Vec(cfg.nMSHRs, new ClientMetadata)) var sec_rdy = false.B io.fence_rdy := true.B io.probe_rdy := true.B io.mem_grant.ready := false.B val mshr_alloc_idx = Wire(UInt()) val pri_rdy = WireInit(false.B) val pri_val = req.valid && sdq_rdy && cacheable && !idx_match(req_idx) val mshrs = (0 until cfg.nMSHRs) map { i => val mshr = Module(new BoomMSHR) mshr.io.id := i.U(log2Ceil(cfg.nMSHRs).W) for (w <- 0 until memWidth) { idx_matches(w)(i) := mshr.io.idx.valid && mshr.io.idx.bits === io.req(w).bits.addr(untagBits-1,blockOffBits) tag_matches(w)(i) := mshr.io.tag.valid && mshr.io.tag.bits === io.req(w).bits.addr >> untagBits way_matches(w)(i) := mshr.io.way.valid && mshr.io.way.bits === io.req(w).bits.way_en } wb_tag_list(i) := mshr.io.wb_req.bits.tag mshr.io.req_pri_val := (i.U === mshr_alloc_idx) && pri_val when (i.U === mshr_alloc_idx) { pri_rdy := mshr.io.req_pri_rdy } mshr.io.req_sec_val := req.valid && sdq_rdy && tag_match(req_idx) && idx_matches(req_idx)(i) && cacheable mshr.io.req := req.bits mshr.io.req_is_probe := req_is_probe mshr.io.req.sdq_id := sdq_alloc_id // Clear because of a FENCE, a request to the same idx as a prefetched line, // a probe to that prefetched line, all mshrs are in use mshr.io.clear_prefetch := ((io.clear_all && !req.valid)|| (req.valid && idx_matches(req_idx)(i) && cacheable && !tag_match(req_idx)) || (req_is_probe && idx_matches(req_idx)(i))) mshr.io.brupdate := io.brupdate mshr.io.exception := io.exception mshr.io.rob_pnr_idx := io.rob_pnr_idx mshr.io.rob_head_idx := io.rob_head_idx mshr.io.prober_state := io.prober_state mshr.io.wb_resp := io.wb_resp meta_write_arb.io.in(i) <> mshr.io.meta_write meta_read_arb.io.in(i) <> mshr.io.meta_read mshr.io.meta_resp := io.meta_resp wb_req_arb.io.in(i) <> mshr.io.wb_req replay_arb.io.in(i) <> mshr.io.replay refill_arb.io.in(i) <> mshr.io.refill lb_read_arb.io.in(i) <> mshr.io.lb_read mshr.io.lb_resp := lb_read_data lb_write_arb.io.in(i) <> mshr.io.lb_write commit_vals(i) := mshr.io.commit_val commit_addrs(i) := mshr.io.commit_addr commit_cohs(i) := mshr.io.commit_coh mshr.io.mem_grant.valid := false.B mshr.io.mem_grant.bits := DontCare when (io.mem_grant.bits.source === i.U) { mshr.io.mem_grant <> io.mem_grant } sec_rdy = sec_rdy || (mshr.io.req_sec_rdy && mshr.io.req_sec_val) resp_arb.io.in(i) <> mshr.io.resp when (!mshr.io.req_pri_rdy) { io.fence_rdy := false.B } for (w <- 0 until memWidth) { when (!mshr.io.probe_rdy && idx_matches(w)(i) && io.req_is_probe(w)) { io.probe_rdy := false.B } } mshr } // Try to round-robin the MSHRs val mshr_head = RegInit(0.U(log2Ceil(cfg.nMSHRs).W)) mshr_alloc_idx := RegNext(AgePriorityEncoder(mshrs.map(m=>m.io.req_pri_rdy), mshr_head)) when (pri_rdy && pri_val) { mshr_head := WrapInc(mshr_head, cfg.nMSHRs) } io.meta_write <> meta_write_arb.io.out io.meta_read <> meta_read_arb.io.out io.wb_req <> wb_req_arb.io.out val mmio_alloc_arb = Module(new Arbiter(Bool(), nIOMSHRs)) var mmio_rdy = false.B val mmios = (0 until nIOMSHRs) map { i => val id = cfg.nMSHRs + 1 + i // +1 for wb unit val mshr = Module(new BoomIOMSHR(id)) mmio_alloc_arb.io.in(i).valid := mshr.io.req.ready mmio_alloc_arb.io.in(i).bits := DontCare mshr.io.req.valid := mmio_alloc_arb.io.in(i).ready mshr.io.req.bits := req.bits mmio_rdy = mmio_rdy || mshr.io.req.ready mshr.io.mem_ack.bits := io.mem_grant.bits mshr.io.mem_ack.valid := io.mem_grant.valid && io.mem_grant.bits.source === id.U when (io.mem_grant.bits.source === id.U) { io.mem_grant.ready := true.B } resp_arb.io.in(cfg.nMSHRs + i) <> mshr.io.resp when (!mshr.io.req.ready) { io.fence_rdy := false.B } mshr } mmio_alloc_arb.io.out.ready := req.valid && !cacheable TLArbiter.lowestFromSeq(edge, io.mem_acquire, mshrs.map(_.io.mem_acquire) ++ mmios.map(_.io.mem_access)) TLArbiter.lowestFromSeq(edge, io.mem_finish, mshrs.map(_.io.mem_finish)) val respq = Module(new BranchKillableQueue(new BoomDCacheResp, 4, u => u.uses_ldq, flow = false)) respq.io.brupdate := io.brupdate respq.io.flush := io.exception respq.io.enq <> resp_arb.io.out io.resp <> respq.io.deq for (w <- 0 until memWidth) { io.req(w).ready := (w.U === req_idx) && Mux(!cacheable, mmio_rdy, sdq_rdy && Mux(idx_match(w), tag_match(w) && sec_rdy, pri_rdy)) io.secondary_miss(w) := idx_match(w) && way_match(w) && !tag_match(w) io.block_hit(w) := idx_match(w) && tag_match(w) } io.refill <> refill_arb.io.out val free_sdq = io.replay.fire && isWrite(io.replay.bits.uop.mem_cmd) io.replay <> replay_arb.io.out io.replay.bits.data := sdq(replay_arb.io.out.bits.sdq_id) when (io.replay.valid || sdq_enq) { sdq_val := sdq_val & ~(UIntToOH(replay_arb.io.out.bits.sdq_id) & Fill(cfg.nSDQ, free_sdq)) | PriorityEncoderOH(~sdq_val(cfg.nSDQ-1,0)) & Fill(cfg.nSDQ, sdq_enq) } prefetcher.io.mshr_avail := RegNext(pri_rdy) prefetcher.io.req_val := RegNext(commit_vals.reduce(_||_)) prefetcher.io.req_addr := RegNext(Mux1H(commit_vals, commit_addrs)) prefetcher.io.req_coh := RegNext(Mux1H(commit_vals, commit_cohs)) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } } File AMOALU.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters class StoreGen(typ: UInt, addr: UInt, dat: UInt, maxSize: Int) { val size = Wire(UInt(log2Up(log2Up(maxSize)+1).W)) size := typ val dat_padded = dat.pad(maxSize*8) def misaligned: Bool = (addr & ((1.U << size) - 1.U)(log2Up(maxSize)-1,0)).orR def mask = { var res = 1.U for (i <- 0 until log2Up(maxSize)) { val upper = Mux(addr(i), res, 0.U) | Mux(size >= (i+1).U, ((BigInt(1) << (1 << i))-1).U, 0.U) val lower = Mux(addr(i), 0.U, res) res = Cat(upper, lower) } res } protected def genData(i: Int): UInt = if (i >= log2Up(maxSize)) dat_padded else Mux(size === i.U, Fill(1 << (log2Up(maxSize)-i), dat_padded((8 << i)-1,0)), genData(i+1)) def data = genData(0) def wordData = genData(2) } class LoadGen(typ: UInt, signed: Bool, addr: UInt, dat: UInt, zero: Bool, maxSize: Int) { private val size = new StoreGen(typ, addr, dat, maxSize).size private def genData(logMinSize: Int): UInt = { var res = dat for (i <- log2Up(maxSize)-1 to logMinSize by -1) { val pos = 8 << i val shifted = Mux(addr(i), res(2*pos-1,pos), res(pos-1,0)) val doZero = (i == 0).B && zero val zeroed = Mux(doZero, 0.U, shifted) res = Cat(Mux(size === i.U || doZero, Fill(8*maxSize-pos, signed && zeroed(pos-1)), res(8*maxSize-1,pos)), zeroed) } res } def wordData = genData(2) def data = genData(0) } class AMOALU(operandBits: Int)(implicit p: Parameters) extends Module { val minXLen = 32 val widths = (0 to log2Ceil(operandBits / minXLen)).map(minXLen << _) val io = IO(new Bundle { val mask = Input(UInt((operandBits / 8).W)) val cmd = Input(UInt(M_SZ.W)) val lhs = Input(UInt(operandBits.W)) val rhs = Input(UInt(operandBits.W)) val out = Output(UInt(operandBits.W)) val out_unmasked = Output(UInt(operandBits.W)) }) val max = io.cmd === M_XA_MAX || io.cmd === M_XA_MAXU val min = io.cmd === M_XA_MIN || io.cmd === M_XA_MINU val add = io.cmd === M_XA_ADD val logic_and = io.cmd === M_XA_OR || io.cmd === M_XA_AND val logic_xor = io.cmd === M_XA_XOR || io.cmd === M_XA_OR val adder_out = { // partition the carry chain to support sub-xLen addition val mask = ~(0.U(operandBits.W) +: widths.init.map(w => !io.mask(w/8-1) << (w-1))).reduce(_|_) (io.lhs & mask) + (io.rhs & mask) } val less = { // break up the comparator so the lower parts will be CSE'd def isLessUnsigned(x: UInt, y: UInt, n: Int): Bool = { if (n == minXLen) x(n-1, 0) < y(n-1, 0) else x(n-1, n/2) < y(n-1, n/2) || x(n-1, n/2) === y(n-1, n/2) && isLessUnsigned(x, y, n/2) } def isLess(x: UInt, y: UInt, n: Int): Bool = { val signed = { val mask = M_XA_MIN ^ M_XA_MINU (io.cmd & mask) === (M_XA_MIN & mask) } Mux(x(n-1) === y(n-1), isLessUnsigned(x, y, n), Mux(signed, x(n-1), y(n-1))) } PriorityMux(widths.reverse.map(w => (io.mask(w/8/2), isLess(io.lhs, io.rhs, w)))) } val minmax = Mux(Mux(less, min, max), io.lhs, io.rhs) val logic = Mux(logic_and, io.lhs & io.rhs, 0.U) | Mux(logic_xor, io.lhs ^ io.rhs, 0.U) val out = Mux(add, adder_out, Mux(logic_and || logic_xor, logic, minmax)) val wmask = FillInterleaved(8, io.mask) io.out := wmask & out | ~wmask & io.lhs io.out_unmasked := out }

module BoomIOMSHR_1( // @[mshrs.scala:402:7] input clock, // @[mshrs.scala:402:7] input reset, // @[mshrs.scala:402:7] output io_req_ready, // @[mshrs.scala:405:14] input io_req_valid, // @[mshrs.scala:405:14] input [6:0] io_req_bits_uop_uopc, // @[mshrs.scala:405:14] input [31:0] io_req_bits_uop_inst, // @[mshrs.scala:405:14] input [31:0] io_req_bits_uop_debug_inst, // @[mshrs.scala:405:14] input io_req_bits_uop_is_rvc, // @[mshrs.scala:405:14] input [33:0] io_req_bits_uop_debug_pc, // @[mshrs.scala:405:14] input [2:0] io_req_bits_uop_iq_type, // @[mshrs.scala:405:14] input [9:0] io_req_bits_uop_fu_code, // @[mshrs.scala:405:14] input [3:0] io_req_bits_uop_ctrl_br_type, // @[mshrs.scala:405:14] input [1:0] io_req_bits_uop_ctrl_op1_sel, // @[mshrs.scala:405:14] input [2:0] io_req_bits_uop_ctrl_op2_sel, // @[mshrs.scala:405:14] input [2:0] io_req_bits_uop_ctrl_imm_sel, // @[mshrs.scala:405:14] input [4:0] io_req_bits_uop_ctrl_op_fcn, // @[mshrs.scala:405:14] input io_req_bits_uop_ctrl_fcn_dw, // @[mshrs.scala:405:14] input [2:0] io_req_bits_uop_ctrl_csr_cmd, // @[mshrs.scala:405:14] input io_req_bits_uop_ctrl_is_load, // @[mshrs.scala:405:14] input io_req_bits_uop_ctrl_is_sta, // @[mshrs.scala:405:14] input io_req_bits_uop_ctrl_is_std, // @[mshrs.scala:405:14] input [1:0] io_req_bits_uop_iw_state, // @[mshrs.scala:405:14] input io_req_bits_uop_iw_p1_poisoned, // @[mshrs.scala:405:14] input io_req_bits_uop_iw_p2_poisoned, // @[mshrs.scala:405:14] input io_req_bits_uop_is_br, // @[mshrs.scala:405:14] input io_req_bits_uop_is_jalr, // @[mshrs.scala:405:14] input io_req_bits_uop_is_jal, // @[mshrs.scala:405:14] input io_req_bits_uop_is_sfb, // @[mshrs.scala:405:14] input [3:0] io_req_bits_uop_br_mask, // @[mshrs.scala:405:14] input [1:0] io_req_bits_uop_br_tag, // @[mshrs.scala:405:14] input [3:0] io_req_bits_uop_ftq_idx, // @[mshrs.scala:405:14] input io_req_bits_uop_edge_inst, // @[mshrs.scala:405:14] input [5:0] io_req_bits_uop_pc_lob, // @[mshrs.scala:405:14] input io_req_bits_uop_taken, // @[mshrs.scala:405:14] input [19:0] io_req_bits_uop_imm_packed, // @[mshrs.scala:405:14] input [11:0] io_req_bits_uop_csr_addr, // @[mshrs.scala:405:14] input [5:0] io_req_bits_uop_rob_idx, // @[mshrs.scala:405:14] input [3:0] io_req_bits_uop_ldq_idx, // @[mshrs.scala:405:14] input [3:0] io_req_bits_uop_stq_idx, // @[mshrs.scala:405:14] input [1:0] io_req_bits_uop_rxq_idx, // @[mshrs.scala:405:14] input [6:0] io_req_bits_uop_pdst, // @[mshrs.scala:405:14] input [6:0] io_req_bits_uop_prs1, // @[mshrs.scala:405:14] input [6:0] io_req_bits_uop_prs2, // @[mshrs.scala:405:14] input [6:0] io_req_bits_uop_prs3, // @[mshrs.scala:405:14] input [3:0] io_req_bits_uop_ppred, // @[mshrs.scala:405:14] input io_req_bits_uop_prs1_busy, // @[mshrs.scala:405:14] input io_req_bits_uop_prs2_busy, // @[mshrs.scala:405:14] input io_req_bits_uop_prs3_busy, // @[mshrs.scala:405:14] input io_req_bits_uop_ppred_busy, // @[mshrs.scala:405:14] input [6:0] io_req_bits_uop_stale_pdst, // @[mshrs.scala:405:14] input io_req_bits_uop_exception, // @[mshrs.scala:405:14] input [63:0] io_req_bits_uop_exc_cause, // @[mshrs.scala:405:14] input io_req_bits_uop_bypassable, // @[mshrs.scala:405:14] input [4:0] io_req_bits_uop_mem_cmd, // @[mshrs.scala:405:14] input [1:0] io_req_bits_uop_mem_size, // @[mshrs.scala:405:14] input io_req_bits_uop_mem_signed, // @[mshrs.scala:405:14] input io_req_bits_uop_is_fence, // @[mshrs.scala:405:14] input io_req_bits_uop_is_fencei, // @[mshrs.scala:405:14] input io_req_bits_uop_is_amo, // @[mshrs.scala:405:14] input io_req_bits_uop_uses_ldq, // @[mshrs.scala:405:14] input io_req_bits_uop_uses_stq, // @[mshrs.scala:405:14] input io_req_bits_uop_is_sys_pc2epc, // @[mshrs.scala:405:14] input io_req_bits_uop_is_unique, // @[mshrs.scala:405:14] input io_req_bits_uop_flush_on_commit, // @[mshrs.scala:405:14] input io_req_bits_uop_ldst_is_rs1, // @[mshrs.scala:405:14] input [5:0] io_req_bits_uop_ldst, // @[mshrs.scala:405:14] input [5:0] io_req_bits_uop_lrs1, // @[mshrs.scala:405:14] input [5:0] io_req_bits_uop_lrs2, // @[mshrs.scala:405:14] input [5:0] io_req_bits_uop_lrs3, // @[mshrs.scala:405:14] input io_req_bits_uop_ldst_val, // @[mshrs.scala:405:14] input [1:0] io_req_bits_uop_dst_rtype, // @[mshrs.scala:405:14] input [1:0] io_req_bits_uop_lrs1_rtype, // @[mshrs.scala:405:14] input [1:0] io_req_bits_uop_lrs2_rtype, // @[mshrs.scala:405:14] input io_req_bits_uop_frs3_en, // @[mshrs.scala:405:14] input io_req_bits_uop_fp_val, // @[mshrs.scala:405:14] input io_req_bits_uop_fp_single, // @[mshrs.scala:405:14] input io_req_bits_uop_xcpt_pf_if, // @[mshrs.scala:405:14] input io_req_bits_uop_xcpt_ae_if, // @[mshrs.scala:405:14] input io_req_bits_uop_xcpt_ma_if, // @[mshrs.scala:405:14] input io_req_bits_uop_bp_debug_if, // @[mshrs.scala:405:14] input io_req_bits_uop_bp_xcpt_if, // @[mshrs.scala:405:14] input [1:0] io_req_bits_uop_debug_fsrc, // @[mshrs.scala:405:14] input [1:0] io_req_bits_uop_debug_tsrc, // @[mshrs.scala:405:14] input [33:0] io_req_bits_addr, // @[mshrs.scala:405:14] input [63:0] io_req_bits_data, // @[mshrs.scala:405:14] input io_req_bits_is_hella, // @[mshrs.scala:405:14] input io_resp_ready, // @[mshrs.scala:405:14] output io_resp_valid, // @[mshrs.scala:405:14] output [6:0] io_resp_bits_uop_uopc, // @[mshrs.scala:405:14] output [31:0] io_resp_bits_uop_inst, // @[mshrs.scala:405:14] output [31:0] io_resp_bits_uop_debug_inst, // @[mshrs.scala:405:14] output io_resp_bits_uop_is_rvc, // @[mshrs.scala:405:14] output [33:0] io_resp_bits_uop_debug_pc, // @[mshrs.scala:405:14] output [2:0] io_resp_bits_uop_iq_type, // @[mshrs.scala:405:14] output [9:0] io_resp_bits_uop_fu_code, // @[mshrs.scala:405:14] output [3:0] io_resp_bits_uop_ctrl_br_type, // @[mshrs.scala:405:14] output [1:0] io_resp_bits_uop_ctrl_op1_sel, // @[mshrs.scala:405:14] output [2:0] io_resp_bits_uop_ctrl_op2_sel, // @[mshrs.scala:405:14] output [2:0] io_resp_bits_uop_ctrl_imm_sel, // @[mshrs.scala:405:14] output [4:0] io_resp_bits_uop_ctrl_op_fcn, // @[mshrs.scala:405:14] output io_resp_bits_uop_ctrl_fcn_dw, // @[mshrs.scala:405:14] output [2:0] io_resp_bits_uop_ctrl_csr_cmd, // @[mshrs.scala:405:14] output io_resp_bits_uop_ctrl_is_load, // @[mshrs.scala:405:14] output io_resp_bits_uop_ctrl_is_sta, // @[mshrs.scala:405:14] output io_resp_bits_uop_ctrl_is_std, // @[mshrs.scala:405:14] output [1:0] io_resp_bits_uop_iw_state, // @[mshrs.scala:405:14] output io_resp_bits_uop_iw_p1_poisoned, // @[mshrs.scala:405:14] output io_resp_bits_uop_iw_p2_poisoned, // @[mshrs.scala:405:14] output io_resp_bits_uop_is_br, // @[mshrs.scala:405:14] output io_resp_bits_uop_is_jalr, // @[mshrs.scala:405:14] output io_resp_bits_uop_is_jal, // @[mshrs.scala:405:14] output io_resp_bits_uop_is_sfb, // @[mshrs.scala:405:14] output [3:0] io_resp_bits_uop_br_mask, // @[mshrs.scala:405:14] output [1:0] io_resp_bits_uop_br_tag, // @[mshrs.scala:405:14] output [3:0] io_resp_bits_uop_ftq_idx, // @[mshrs.scala:405:14] output io_resp_bits_uop_edge_inst, // @[mshrs.scala:405:14] output [5:0] io_resp_bits_uop_pc_lob, // @[mshrs.scala:405:14] output io_resp_bits_uop_taken, // @[mshrs.scala:405:14] output [19:0] io_resp_bits_uop_imm_packed, // @[mshrs.scala:405:14] output [11:0] io_resp_bits_uop_csr_addr, // @[mshrs.scala:405:14] output [5:0] io_resp_bits_uop_rob_idx, // @[mshrs.scala:405:14] output [3:0] io_resp_bits_uop_ldq_idx, // @[mshrs.scala:405:14] output [3:0] io_resp_bits_uop_stq_idx, // @[mshrs.scala:405:14] output [1:0] io_resp_bits_uop_rxq_idx, // @[mshrs.scala:405:14] output [6:0] io_resp_bits_uop_pdst, // @[mshrs.scala:405:14] output [6:0] io_resp_bits_uop_prs1, // @[mshrs.scala:405:14] output [6:0] io_resp_bits_uop_prs2, // @[mshrs.scala:405:14] output [6:0] io_resp_bits_uop_prs3, // @[mshrs.scala:405:14] output [3:0] io_resp_bits_uop_ppred, // @[mshrs.scala:405:14] output io_resp_bits_uop_prs1_busy, // @[mshrs.scala:405:14] output io_resp_bits_uop_prs2_busy, // @[mshrs.scala:405:14] output io_resp_bits_uop_prs3_busy, // @[mshrs.scala:405:14] output io_resp_bits_uop_ppred_busy, // @[mshrs.scala:405:14] output [6:0] io_resp_bits_uop_stale_pdst, // @[mshrs.scala:405:14] output io_resp_bits_uop_exception, // @[mshrs.scala:405:14] output [63:0] io_resp_bits_uop_exc_cause, // @[mshrs.scala:405:14] output io_resp_bits_uop_bypassable, // @[mshrs.scala:405:14] output [4:0] io_resp_bits_uop_mem_cmd, // @[mshrs.scala:405:14] output [1:0] io_resp_bits_uop_mem_size, // @[mshrs.scala:405:14] output io_resp_bits_uop_mem_signed, // @[mshrs.scala:405:14] output io_resp_bits_uop_is_fence, // @[mshrs.scala:405:14] output io_resp_bits_uop_is_fencei, // @[mshrs.scala:405:14] output io_resp_bits_uop_is_amo, // @[mshrs.scala:405:14] output io_resp_bits_uop_uses_ldq, // @[mshrs.scala:405:14] output io_resp_bits_uop_uses_stq, // @[mshrs.scala:405:14] output io_resp_bits_uop_is_sys_pc2epc, // @[mshrs.scala:405:14] output io_resp_bits_uop_is_unique, // @[mshrs.scala:405:14] output io_resp_bits_uop_flush_on_commit, // @[mshrs.scala:405:14] output io_resp_bits_uop_ldst_is_rs1, // @[mshrs.scala:405:14] output [5:0] io_resp_bits_uop_ldst, // @[mshrs.scala:405:14] output [5:0] io_resp_bits_uop_lrs1, // @[mshrs.scala:405:14] output [5:0] io_resp_bits_uop_lrs2, // @[mshrs.scala:405:14] output [5:0] io_resp_bits_uop_lrs3, // @[mshrs.scala:405:14] output io_resp_bits_uop_ldst_val, // @[mshrs.scala:405:14] output [1:0] io_resp_bits_uop_dst_rtype, // @[mshrs.scala:405:14] output [1:0] io_resp_bits_uop_lrs1_rtype, // @[mshrs.scala:405:14] output [1:0] io_resp_bits_uop_lrs2_rtype, // @[mshrs.scala:405:14] output io_resp_bits_uop_frs3_en, // @[mshrs.scala:405:14] output io_resp_bits_uop_fp_val, // @[mshrs.scala:405:14] output io_resp_bits_uop_fp_single, // @[mshrs.scala:405:14] output io_resp_bits_uop_xcpt_pf_if, // @[mshrs.scala:405:14] output io_resp_bits_uop_xcpt_ae_if, // @[mshrs.scala:405:14] output io_resp_bits_uop_xcpt_ma_if, // @[mshrs.scala:405:14] output io_resp_bits_uop_bp_debug_if, // @[mshrs.scala:405:14] output io_resp_bits_uop_bp_xcpt_if, // @[mshrs.scala:405:14] output [1:0] io_resp_bits_uop_debug_fsrc, // @[mshrs.scala:405:14] output [1:0] io_resp_bits_uop_debug_tsrc, // @[mshrs.scala:405:14] output [63:0] io_resp_bits_data, // @[mshrs.scala:405:14] output io_resp_bits_is_hella, // @[mshrs.scala:405:14] input io_mem_access_ready, // @[mshrs.scala:405:14] output io_mem_access_valid, // @[mshrs.scala:405:14] output [2:0] io_mem_access_bits_opcode, // @[mshrs.scala:405:14] output [2:0] io_mem_access_bits_param, // @[mshrs.scala:405:14] output [3:0] io_mem_access_bits_size, // @[mshrs.scala:405:14] output [3:0] io_mem_access_bits_source, // @[mshrs.scala:405:14] output [31:0] io_mem_access_bits_address, // @[mshrs.scala:405:14] output [7:0] io_mem_access_bits_mask, // @[mshrs.scala:405:14] output [63:0] io_mem_access_bits_data, // @[mshrs.scala:405:14] input io_mem_ack_valid, // @[mshrs.scala:405:14] input [2:0] io_mem_ack_bits_opcode, // @[mshrs.scala:405:14] input [1:0] io_mem_ack_bits_param, // @[mshrs.scala:405:14] input [3:0] io_mem_ack_bits_size, // @[mshrs.scala:405:14] input [3:0] io_mem_ack_bits_source, // @[mshrs.scala:405:14] input [2:0] io_mem_ack_bits_sink, // @[mshrs.scala:405:14] input io_mem_ack_bits_denied, // @[mshrs.scala:405:14] input [63:0] io_mem_ack_bits_data, // @[mshrs.scala:405:14] input io_mem_ack_bits_corrupt // @[mshrs.scala:405:14] ); wire io_req_valid_0 = io_req_valid; // @[mshrs.scala:402:7] wire [6:0] io_req_bits_uop_uopc_0 = io_req_bits_uop_uopc; // @[mshrs.scala:402:7] wire [31:0] io_req_bits_uop_inst_0 = io_req_bits_uop_inst; // @[mshrs.scala:402:7] wire [31:0] io_req_bits_uop_debug_inst_0 = io_req_bits_uop_debug_inst; // @[mshrs.scala:402:7] wire io_req_bits_uop_is_rvc_0 = io_req_bits_uop_is_rvc; // @[mshrs.scala:402:7] wire [33:0] io_req_bits_uop_debug_pc_0 = io_req_bits_uop_debug_pc; // @[mshrs.scala:402:7] wire [2:0] io_req_bits_uop_iq_type_0 = io_req_bits_uop_iq_type; // @[mshrs.scala:402:7] wire [9:0] io_req_bits_uop_fu_code_0 = io_req_bits_uop_fu_code; // @[mshrs.scala:402:7] wire [3:0] io_req_bits_uop_ctrl_br_type_0 = io_req_bits_uop_ctrl_br_type; // @[mshrs.scala:402:7] wire [1:0] io_req_bits_uop_ctrl_op1_sel_0 = io_req_bits_uop_ctrl_op1_sel; // @[mshrs.scala:402:7] wire [2:0] io_req_bits_uop_ctrl_op2_sel_0 = io_req_bits_uop_ctrl_op2_sel; // @[mshrs.scala:402:7] wire [2:0] io_req_bits_uop_ctrl_imm_sel_0 = io_req_bits_uop_ctrl_imm_sel; // @[mshrs.scala:402:7] wire [4:0] io_req_bits_uop_ctrl_op_fcn_0 = io_req_bits_uop_ctrl_op_fcn; // @[mshrs.scala:402:7] wire io_req_bits_uop_ctrl_fcn_dw_0 = io_req_bits_uop_ctrl_fcn_dw; // @[mshrs.scala:402:7] wire [2:0] io_req_bits_uop_ctrl_csr_cmd_0 = io_req_bits_uop_ctrl_csr_cmd; // @[mshrs.scala:402:7] wire io_req_bits_uop_ctrl_is_load_0 = io_req_bits_uop_ctrl_is_load; // @[mshrs.scala:402:7] wire io_req_bits_uop_ctrl_is_sta_0 = io_req_bits_uop_ctrl_is_sta; // @[mshrs.scala:402:7] wire io_req_bits_uop_ctrl_is_std_0 = io_req_bits_uop_ctrl_is_std; // @[mshrs.scala:402:7] wire [1:0] io_req_bits_uop_iw_state_0 = io_req_bits_uop_iw_state; // @[mshrs.scala:402:7] wire io_req_bits_uop_iw_p1_poisoned_0 = io_req_bits_uop_iw_p1_poisoned; // @[mshrs.scala:402:7] wire io_req_bits_uop_iw_p2_poisoned_0 = io_req_bits_uop_iw_p2_poisoned; // @[mshrs.scala:402:7] wire io_req_bits_uop_is_br_0 = io_req_bits_uop_is_br; // @[mshrs.scala:402:7] wire io_req_bits_uop_is_jalr_0 = io_req_bits_uop_is_jalr; // @[mshrs.scala:402:7] wire io_req_bits_uop_is_jal_0 = io_req_bits_uop_is_jal; // @[mshrs.scala:402:7] wire io_req_bits_uop_is_sfb_0 = io_req_bits_uop_is_sfb; // @[mshrs.scala:402:7] wire [3:0] io_req_bits_uop_br_mask_0 = io_req_bits_uop_br_mask; // @[mshrs.scala:402:7] wire [1:0] io_req_bits_uop_br_tag_0 = io_req_bits_uop_br_tag; // @[mshrs.scala:402:7] wire [3:0] io_req_bits_uop_ftq_idx_0 = io_req_bits_uop_ftq_idx; // @[mshrs.scala:402:7] wire io_req_bits_uop_edge_inst_0 = io_req_bits_uop_edge_inst; // @[mshrs.scala:402:7] wire [5:0] io_req_bits_uop_pc_lob_0 = io_req_bits_uop_pc_lob; // @[mshrs.scala:402:7] wire io_req_bits_uop_taken_0 = io_req_bits_uop_taken; // @[mshrs.scala:402:7] wire [19:0] io_req_bits_uop_imm_packed_0 = io_req_bits_uop_imm_packed; // @[mshrs.scala:402:7] wire [11:0] io_req_bits_uop_csr_addr_0 = io_req_bits_uop_csr_addr; // @[mshrs.scala:402:7] wire [5:0] io_req_bits_uop_rob_idx_0 = io_req_bits_uop_rob_idx; // @[mshrs.scala:402:7] wire [3:0] io_req_bits_uop_ldq_idx_0 = io_req_bits_uop_ldq_idx; // @[mshrs.scala:402:7] wire [3:0] io_req_bits_uop_stq_idx_0 = io_req_bits_uop_stq_idx; // @[mshrs.scala:402:7] wire [1:0] io_req_bits_uop_rxq_idx_0 = io_req_bits_uop_rxq_idx; // @[mshrs.scala:402:7] wire [6:0] io_req_bits_uop_pdst_0 = io_req_bits_uop_pdst; // @[mshrs.scala:402:7] wire [6:0] io_req_bits_uop_prs1_0 = io_req_bits_uop_prs1; // @[mshrs.scala:402:7] wire [6:0] io_req_bits_uop_prs2_0 = io_req_bits_uop_prs2; // @[mshrs.scala:402:7] wire [6:0] io_req_bits_uop_prs3_0 = io_req_bits_uop_prs3; // @[mshrs.scala:402:7] wire [3:0] io_req_bits_uop_ppred_0 = io_req_bits_uop_ppred; // @[mshrs.scala:402:7] wire io_req_bits_uop_prs1_busy_0 = io_req_bits_uop_prs1_busy; // @[mshrs.scala:402:7] wire io_req_bits_uop_prs2_busy_0 = io_req_bits_uop_prs2_busy; // @[mshrs.scala:402:7] wire io_req_bits_uop_prs3_busy_0 = io_req_bits_uop_prs3_busy; // @[mshrs.scala:402:7] wire io_req_bits_uop_ppred_busy_0 = io_req_bits_uop_ppred_busy; // @[mshrs.scala:402:7] wire [6:0] io_req_bits_uop_stale_pdst_0 = io_req_bits_uop_stale_pdst; // @[mshrs.scala:402:7] wire io_req_bits_uop_exception_0 = io_req_bits_uop_exception; // @[mshrs.scala:402:7] wire [63:0] io_req_bits_uop_exc_cause_0 = io_req_bits_uop_exc_cause; // @[mshrs.scala:402:7] wire io_req_bits_uop_bypassable_0 = io_req_bits_uop_bypassable; // @[mshrs.scala:402:7] wire [4:0] io_req_bits_uop_mem_cmd_0 = io_req_bits_uop_mem_cmd; // @[mshrs.scala:402:7] wire [1:0] io_req_bits_uop_mem_size_0 = io_req_bits_uop_mem_size; // @[mshrs.scala:402:7] wire io_req_bits_uop_mem_signed_0 = io_req_bits_uop_mem_signed; // @[mshrs.scala:402:7] wire io_req_bits_uop_is_fence_0 = io_req_bits_uop_is_fence; // @[mshrs.scala:402:7] wire io_req_bits_uop_is_fencei_0 = io_req_bits_uop_is_fencei; // @[mshrs.scala:402:7] wire io_req_bits_uop_is_amo_0 = io_req_bits_uop_is_amo; // @[mshrs.scala:402:7] wire io_req_bits_uop_uses_ldq_0 = io_req_bits_uop_uses_ldq; // @[mshrs.scala:402:7] wire io_req_bits_uop_uses_stq_0 = io_req_bits_uop_uses_stq; // @[mshrs.scala:402:7] wire io_req_bits_uop_is_sys_pc2epc_0 = io_req_bits_uop_is_sys_pc2epc; // @[mshrs.scala:402:7] wire io_req_bits_uop_is_unique_0 = io_req_bits_uop_is_unique; // @[mshrs.scala:402:7] wire io_req_bits_uop_flush_on_commit_0 = io_req_bits_uop_flush_on_commit; // @[mshrs.scala:402:7] wire io_req_bits_uop_ldst_is_rs1_0 = io_req_bits_uop_ldst_is_rs1; // @[mshrs.scala:402:7] wire [5:0] io_req_bits_uop_ldst_0 = io_req_bits_uop_ldst; // @[mshrs.scala:402:7] wire [5:0] io_req_bits_uop_lrs1_0 = io_req_bits_uop_lrs1; // @[mshrs.scala:402:7] wire [5:0] io_req_bits_uop_lrs2_0 = io_req_bits_uop_lrs2; // @[mshrs.scala:402:7] wire [5:0] io_req_bits_uop_lrs3_0 = io_req_bits_uop_lrs3; // @[mshrs.scala:402:7] wire io_req_bits_uop_ldst_val_0 = io_req_bits_uop_ldst_val; // @[mshrs.scala:402:7] wire [1:0] io_req_bits_uop_dst_rtype_0 = io_req_bits_uop_dst_rtype; // @[mshrs.scala:402:7] wire [1:0] io_req_bits_uop_lrs1_rtype_0 = io_req_bits_uop_lrs1_rtype; // @[mshrs.scala:402:7] wire [1:0] io_req_bits_uop_lrs2_rtype_0 = io_req_bits_uop_lrs2_rtype; // @[mshrs.scala:402:7] wire io_req_bits_uop_frs3_en_0 = io_req_bits_uop_frs3_en; // @[mshrs.scala:402:7] wire io_req_bits_uop_fp_val_0 = io_req_bits_uop_fp_val; // @[mshrs.scala:402:7] wire io_req_bits_uop_fp_single_0 = io_req_bits_uop_fp_single; // @[mshrs.scala:402:7] wire io_req_bits_uop_xcpt_pf_if_0 = io_req_bits_uop_xcpt_pf_if; // @[mshrs.scala:402:7] wire io_req_bits_uop_xcpt_ae_if_0 = io_req_bits_uop_xcpt_ae_if; // @[mshrs.scala:402:7] wire io_req_bits_uop_xcpt_ma_if_0 = io_req_bits_uop_xcpt_ma_if; // @[mshrs.scala:402:7] wire io_req_bits_uop_bp_debug_if_0 = io_req_bits_uop_bp_debug_if; // @[mshrs.scala:402:7] wire io_req_bits_uop_bp_xcpt_if_0 = io_req_bits_uop_bp_xcpt_if; // @[mshrs.scala:402:7] wire [1:0] io_req_bits_uop_debug_fsrc_0 = io_req_bits_uop_debug_fsrc; // @[mshrs.scala:402:7] wire [1:0] io_req_bits_uop_debug_tsrc_0 = io_req_bits_uop_debug_tsrc; // @[mshrs.scala:402:7] wire [33:0] io_req_bits_addr_0 = io_req_bits_addr; // @[mshrs.scala:402:7] wire [63:0] io_req_bits_data_0 = io_req_bits_data; // @[mshrs.scala:402:7] wire io_req_bits_is_hella_0 = io_req_bits_is_hella; // @[mshrs.scala:402:7] wire io_resp_ready_0 = io_resp_ready; // @[mshrs.scala:402:7] wire io_mem_access_ready_0 = io_mem_access_ready; // @[mshrs.scala:402:7] wire io_mem_ack_valid_0 = io_mem_ack_valid; // @[mshrs.scala:402:7] wire [2:0] io_mem_ack_bits_opcode_0 = io_mem_ack_bits_opcode; // @[mshrs.scala:402:7] wire [1:0] io_mem_ack_bits_param_0 = io_mem_ack_bits_param; // @[mshrs.scala:402:7] wire [3:0] io_mem_ack_bits_size_0 = io_mem_ack_bits_size; // @[mshrs.scala:402:7] wire [3:0] io_mem_ack_bits_source_0 = io_mem_ack_bits_source; // @[mshrs.scala:402:7] wire [2:0] io_mem_ack_bits_sink_0 = io_mem_ack_bits_sink; // @[mshrs.scala:402:7] wire io_mem_ack_bits_denied_0 = io_mem_ack_bits_denied; // @[mshrs.scala:402:7] wire [63:0] io_mem_ack_bits_data_0 = io_mem_ack_bits_data; // @[mshrs.scala:402:7] wire io_mem_ack_bits_corrupt_0 = io_mem_ack_bits_corrupt; // @[mshrs.scala:402:7] wire io_mem_access_bits_corrupt = 1'h0; // @[mshrs.scala:402:7] wire get_corrupt = 1'h0; // @[Edges.scala:460:17] wire put_corrupt = 1'h0; // @[Edges.scala:480:17] wire _atomics_WIRE_corrupt = 1'h0; // @[mshrs.scala:439:46] wire atomics_a_corrupt = 1'h0; // @[Edges.scala:534:17] wire atomics_a_1_corrupt = 1'h0; // @[Edges.scala:534:17] wire atomics_a_2_corrupt = 1'h0; // @[Edges.scala:534:17] wire atomics_a_3_corrupt = 1'h0; // @[Edges.scala:534:17] wire atomics_a_4_corrupt = 1'h0; // @[Edges.scala:517:17] wire atomics_a_5_corrupt = 1'h0; // @[Edges.scala:517:17] wire atomics_a_6_corrupt = 1'h0; // @[Edges.scala:517:17] wire atomics_a_7_corrupt = 1'h0; // @[Edges.scala:517:17] wire atomics_a_8_corrupt = 1'h0; // @[Edges.scala:517:17] wire _atomics_T_1_corrupt = 1'h0; // @[mshrs.scala:439:75] wire _atomics_T_3_corrupt = 1'h0; // @[mshrs.scala:439:75] wire _atomics_T_5_corrupt = 1'h0; // @[mshrs.scala:439:75] wire _atomics_T_7_corrupt = 1'h0; // @[mshrs.scala:439:75] wire _atomics_T_9_corrupt = 1'h0; // @[mshrs.scala:439:75] wire _atomics_T_11_corrupt = 1'h0; // @[mshrs.scala:439:75] wire _atomics_T_13_corrupt = 1'h0; // @[mshrs.scala:439:75] wire _atomics_T_15_corrupt = 1'h0; // @[mshrs.scala:439:75] wire atomics_corrupt = 1'h0; // @[mshrs.scala:439:75] wire _io_mem_access_bits_T_42_corrupt = 1'h0; // @[mshrs.scala:457:66] wire _io_mem_access_bits_T_43_corrupt = 1'h0; // @[mshrs.scala:457:29] wire io_resp_bits_data_doZero = 1'h0; // @[AMOALU.scala:43:31] wire io_resp_bits_data_doZero_1 = 1'h0; // @[AMOALU.scala:43:31] wire io_resp_bits_data_doZero_2 = 1'h0; // @[AMOALU.scala:43:31] wire [6:0] grant_word_shift = 7'h0; // @[mshrs.scala:417:20] wire [3:0] get_source = 4'h9; // @[Edges.scala:460:17] wire [3:0] put_source = 4'h9; // @[Edges.scala:480:17] wire [3:0] atomics_a_source = 4'h9; // @[Edges.scala:534:17] wire [3:0] atomics_a_1_source = 4'h9; // @[Edges.scala:534:17] wire [3:0] atomics_a_2_source = 4'h9; // @[Edges.scala:534:17] wire [3:0] atomics_a_3_source = 4'h9; // @[Edges.scala:534:17] wire [3:0] atomics_a_4_source = 4'h9; // @[Edges.scala:517:17] wire [3:0] atomics_a_5_source = 4'h9; // @[Edges.scala:517:17] wire [3:0] atomics_a_6_source = 4'h9; // @[Edges.scala:517:17] wire [3:0] atomics_a_7_source = 4'h9; // @[Edges.scala:517:17] wire [3:0] atomics_a_8_source = 4'h9; // @[Edges.scala:517:17] wire [3:0] _io_mem_access_bits_T_42_source = 4'h9; // @[mshrs.scala:457:66] wire [2:0] get_param = 3'h0; // @[Edges.scala:460:17] wire [2:0] put_opcode = 3'h0; // @[Edges.scala:480:17] wire [2:0] put_param = 3'h0; // @[Edges.scala:480:17] wire [2:0] _atomics_WIRE_opcode = 3'h0; // @[mshrs.scala:439:46] wire [2:0] _atomics_WIRE_param = 3'h0; // @[mshrs.scala:439:46] wire [2:0] atomics_a_1_param = 3'h0; // @[Edges.scala:534:17] wire [2:0] atomics_a_5_param = 3'h0; // @[Edges.scala:517:17] wire [2:0] _io_mem_access_bits_T_42_param = 3'h0; // @[mshrs.scala:457:66] wire [2:0] atomics_a_opcode = 3'h3; // @[Edges.scala:534:17] wire [2:0] atomics_a_param = 3'h3; // @[Edges.scala:534:17] wire [2:0] atomics_a_1_opcode = 3'h3; // @[Edges.scala:534:17] wire [2:0] atomics_a_2_opcode = 3'h3; // @[Edges.scala:534:17] wire [2:0] atomics_a_3_opcode = 3'h3; // @[Edges.scala:534:17] wire [2:0] atomics_a_8_param = 3'h3; // @[Edges.scala:517:17] wire [2:0] atomics_a_3_param = 3'h2; // @[Edges.scala:534:17] wire [2:0] atomics_a_4_opcode = 3'h2; // @[Edges.scala:517:17] wire [2:0] atomics_a_5_opcode = 3'h2; // @[Edges.scala:517:17] wire [2:0] atomics_a_6_opcode = 3'h2; // @[Edges.scala:517:17] wire [2:0] atomics_a_7_opcode = 3'h2; // @[Edges.scala:517:17] wire [2:0] atomics_a_7_param = 3'h2; // @[Edges.scala:517:17] wire [2:0] atomics_a_8_opcode = 3'h2; // @[Edges.scala:517:17] wire _get_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _get_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _get_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _get_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _get_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _get_legal_T_11 = 1'h1; // @[Parameters.scala:92:38] wire _get_legal_T_12 = 1'h1; // @[Parameters.scala:92:33] wire _get_legal_T_13 = 1'h1; // @[Parameters.scala:684:29] wire _put_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _put_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _put_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _put_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _put_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _put_legal_T_11 = 1'h1; // @[Parameters.scala:92:38] wire _put_legal_T_12 = 1'h1; // @[Parameters.scala:92:33] wire _put_legal_T_13 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_8 = 1'h1; // @[Parameters.scala:137:59] wire _atomics_legal_T_9 = 1'h1; // @[Parameters.scala:684:54] wire atomics_legal = 1'h1; // @[Parameters.scala:686:26] wire _atomics_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_11 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_12 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_13 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_18 = 1'h1; // @[Parameters.scala:137:59] wire _atomics_legal_T_19 = 1'h1; // @[Parameters.scala:684:54] wire atomics_legal_1 = 1'h1; // @[Parameters.scala:686:26] wire _atomics_legal_T_20 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_21 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_22 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_23 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_28 = 1'h1; // @[Parameters.scala:137:59] wire _atomics_legal_T_29 = 1'h1; // @[Parameters.scala:684:54] wire atomics_legal_2 = 1'h1; // @[Parameters.scala:686:26] wire _atomics_legal_T_30 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_31 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_32 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_33 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_38 = 1'h1; // @[Parameters.scala:137:59] wire _atomics_legal_T_39 = 1'h1; // @[Parameters.scala:684:54] wire atomics_legal_3 = 1'h1; // @[Parameters.scala:686:26] wire _atomics_legal_T_40 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_41 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_42 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_43 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_48 = 1'h1; // @[Parameters.scala:137:59] wire _atomics_legal_T_49 = 1'h1; // @[Parameters.scala:684:54] wire atomics_legal_4 = 1'h1; // @[Parameters.scala:686:26] wire _atomics_legal_T_50 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_51 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_52 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_53 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_58 = 1'h1; // @[Parameters.scala:137:59] wire _atomics_legal_T_59 = 1'h1; // @[Parameters.scala:684:54] wire atomics_legal_5 = 1'h1; // @[Parameters.scala:686:26] wire _atomics_legal_T_60 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_61 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_62 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_63 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_68 = 1'h1; // @[Parameters.scala:137:59] wire _atomics_legal_T_69 = 1'h1; // @[Parameters.scala:684:54] wire atomics_legal_6 = 1'h1; // @[Parameters.scala:686:26] wire _atomics_legal_T_70 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_71 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_72 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_73 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_78 = 1'h1; // @[Parameters.scala:137:59] wire _atomics_legal_T_79 = 1'h1; // @[Parameters.scala:684:54] wire atomics_legal_7 = 1'h1; // @[Parameters.scala:686:26] wire _atomics_legal_T_80 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_81 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_82 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_83 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_88 = 1'h1; // @[Parameters.scala:137:59] wire _atomics_legal_T_89 = 1'h1; // @[Parameters.scala:684:54] wire atomics_legal_8 = 1'h1; // @[Parameters.scala:686:26] wire [34:0] _atomics_legal_T_6 = 35'h0; // @[Parameters.scala:137:46] wire [34:0] _atomics_legal_T_7 = 35'h0; // @[Parameters.scala:137:46] wire [34:0] _atomics_legal_T_16 = 35'h0; // @[Parameters.scala:137:46] wire [34:0] _atomics_legal_T_17 = 35'h0; // @[Parameters.scala:137:46] wire [34:0] _atomics_legal_T_26 = 35'h0; // @[Parameters.scala:137:46] wire [34:0] _atomics_legal_T_27 = 35'h0; // @[Parameters.scala:137:46] wire [34:0] _atomics_legal_T_36 = 35'h0; // @[Parameters.scala:137:46] wire [34:0] _atomics_legal_T_37 = 35'h0; // @[Parameters.scala:137:46] wire [34:0] _atomics_legal_T_46 = 35'h0; // @[Parameters.scala:137:46] wire [34:0] _atomics_legal_T_47 = 35'h0; // @[Parameters.scala:137:46] wire [34:0] _atomics_legal_T_56 = 35'h0; // @[Parameters.scala:137:46] wire [34:0] _atomics_legal_T_57 = 35'h0; // @[Parameters.scala:137:46] wire [34:0] _atomics_legal_T_66 = 35'h0; // @[Parameters.scala:137:46] wire [34:0] _atomics_legal_T_67 = 35'h0; // @[Parameters.scala:137:46] wire [34:0] _atomics_legal_T_76 = 35'h0; // @[Parameters.scala:137:46] wire [34:0] _atomics_legal_T_77 = 35'h0; // @[Parameters.scala:137:46] wire [34:0] _atomics_legal_T_86 = 35'h0; // @[Parameters.scala:137:46] wire [34:0] _atomics_legal_T_87 = 35'h0; // @[Parameters.scala:137:46] wire [2:0] atomics_a_2_param = 3'h1; // @[Edges.scala:534:17] wire [2:0] atomics_a_6_param = 3'h1; // @[Edges.scala:517:17] wire [2:0] get_opcode = 3'h4; // @[Edges.scala:460:17] wire [2:0] atomics_a_4_param = 3'h4; // @[Edges.scala:517:17] wire [63:0] get_data = 64'h0; // @[Edges.scala:460:17] wire [63:0] _atomics_WIRE_data = 64'h0; // @[mshrs.scala:439:46] wire [7:0] _atomics_WIRE_mask = 8'h0; // @[mshrs.scala:439:46] wire [31:0] _atomics_WIRE_address = 32'h0; // @[mshrs.scala:439:46] wire [3:0] _atomics_WIRE_size = 4'h0; // @[mshrs.scala:439:46] wire [3:0] _atomics_WIRE_source = 4'h0; // @[mshrs.scala:439:46] wire _io_req_ready_T; // @[mshrs.scala:427:25] wire _io_resp_valid_T_1; // @[mshrs.scala:461:43] wire [63:0] _io_resp_bits_data_T_23; // @[AMOALU.scala:45:16] wire _io_mem_access_valid_T; // @[mshrs.scala:456:32] wire [2:0] _io_mem_access_bits_T_43_opcode; // @[mshrs.scala:457:29] wire [2:0] _io_mem_access_bits_T_43_param; // @[mshrs.scala:457:29] wire [3:0] _io_mem_access_bits_T_43_size; // @[mshrs.scala:457:29] wire [3:0] _io_mem_access_bits_T_43_source; // @[mshrs.scala:457:29] wire [31:0] _io_mem_access_bits_T_43_address; // @[mshrs.scala:457:29] wire [7:0] _io_mem_access_bits_T_43_mask; // @[mshrs.scala:457:29] wire [63:0] _io_mem_access_bits_T_43_data; // @[mshrs.scala:457:29] wire [63:0] _grant_word_T = io_mem_ack_bits_data_0; // @[mshrs.scala:402:7, :418:10] wire io_req_ready_0; // @[mshrs.scala:402:7] wire [3:0] io_resp_bits_uop_ctrl_br_type_0; // @[mshrs.scala:402:7] wire [1:0] io_resp_bits_uop_ctrl_op1_sel_0; // @[mshrs.scala:402:7] wire [2:0] io_resp_bits_uop_ctrl_op2_sel_0; // @[mshrs.scala:402:7] wire [2:0] io_resp_bits_uop_ctrl_imm_sel_0; // @[mshrs.scala:402:7] wire [4:0] io_resp_bits_uop_ctrl_op_fcn_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_ctrl_fcn_dw_0; // @[mshrs.scala:402:7] wire [2:0] io_resp_bits_uop_ctrl_csr_cmd_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_ctrl_is_load_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_ctrl_is_sta_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_ctrl_is_std_0; // @[mshrs.scala:402:7] wire [6:0] io_resp_bits_uop_uopc_0; // @[mshrs.scala:402:7] wire [31:0] io_resp_bits_uop_inst_0; // @[mshrs.scala:402:7] wire [31:0] io_resp_bits_uop_debug_inst_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_is_rvc_0; // @[mshrs.scala:402:7] wire [33:0] io_resp_bits_uop_debug_pc_0; // @[mshrs.scala:402:7] wire [2:0] io_resp_bits_uop_iq_type_0; // @[mshrs.scala:402:7] wire [9:0] io_resp_bits_uop_fu_code_0; // @[mshrs.scala:402:7] wire [1:0] io_resp_bits_uop_iw_state_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_iw_p1_poisoned_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_iw_p2_poisoned_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_is_br_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_is_jalr_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_is_jal_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_is_sfb_0; // @[mshrs.scala:402:7] wire [3:0] io_resp_bits_uop_br_mask_0; // @[mshrs.scala:402:7] wire [1:0] io_resp_bits_uop_br_tag_0; // @[mshrs.scala:402:7] wire [3:0] io_resp_bits_uop_ftq_idx_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_edge_inst_0; // @[mshrs.scala:402:7] wire [5:0] io_resp_bits_uop_pc_lob_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_taken_0; // @[mshrs.scala:402:7] wire [19:0] io_resp_bits_uop_imm_packed_0; // @[mshrs.scala:402:7] wire [11:0] io_resp_bits_uop_csr_addr_0; // @[mshrs.scala:402:7] wire [5:0] io_resp_bits_uop_rob_idx_0; // @[mshrs.scala:402:7] wire [3:0] io_resp_bits_uop_ldq_idx_0; // @[mshrs.scala:402:7] wire [3:0] io_resp_bits_uop_stq_idx_0; // @[mshrs.scala:402:7] wire [1:0] io_resp_bits_uop_rxq_idx_0; // @[mshrs.scala:402:7] wire [6:0] io_resp_bits_uop_pdst_0; // @[mshrs.scala:402:7] wire [6:0] io_resp_bits_uop_prs1_0; // @[mshrs.scala:402:7] wire [6:0] io_resp_bits_uop_prs2_0; // @[mshrs.scala:402:7] wire [6:0] io_resp_bits_uop_prs3_0; // @[mshrs.scala:402:7] wire [3:0] io_resp_bits_uop_ppred_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_prs1_busy_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_prs2_busy_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_prs3_busy_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_ppred_busy_0; // @[mshrs.scala:402:7] wire [6:0] io_resp_bits_uop_stale_pdst_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_exception_0; // @[mshrs.scala:402:7] wire [63:0] io_resp_bits_uop_exc_cause_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_bypassable_0; // @[mshrs.scala:402:7] wire [4:0] io_resp_bits_uop_mem_cmd_0; // @[mshrs.scala:402:7] wire [1:0] io_resp_bits_uop_mem_size_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_mem_signed_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_is_fence_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_is_fencei_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_is_amo_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_uses_ldq_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_uses_stq_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_is_sys_pc2epc_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_is_unique_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_flush_on_commit_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_ldst_is_rs1_0; // @[mshrs.scala:402:7] wire [5:0] io_resp_bits_uop_ldst_0; // @[mshrs.scala:402:7] wire [5:0] io_resp_bits_uop_lrs1_0; // @[mshrs.scala:402:7] wire [5:0] io_resp_bits_uop_lrs2_0; // @[mshrs.scala:402:7] wire [5:0] io_resp_bits_uop_lrs3_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_ldst_val_0; // @[mshrs.scala:402:7] wire [1:0] io_resp_bits_uop_dst_rtype_0; // @[mshrs.scala:402:7] wire [1:0] io_resp_bits_uop_lrs1_rtype_0; // @[mshrs.scala:402:7] wire [1:0] io_resp_bits_uop_lrs2_rtype_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_frs3_en_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_fp_val_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_fp_single_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_xcpt_pf_if_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_xcpt_ae_if_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_xcpt_ma_if_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_bp_debug_if_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_bp_xcpt_if_0; // @[mshrs.scala:402:7] wire [1:0] io_resp_bits_uop_debug_fsrc_0; // @[mshrs.scala:402:7] wire [1:0] io_resp_bits_uop_debug_tsrc_0; // @[mshrs.scala:402:7] wire [63:0] io_resp_bits_data_0; // @[mshrs.scala:402:7] wire io_resp_bits_is_hella_0; // @[mshrs.scala:402:7] wire io_resp_valid_0; // @[mshrs.scala:402:7] wire [2:0] io_mem_access_bits_opcode_0; // @[mshrs.scala:402:7] wire [2:0] io_mem_access_bits_param_0; // @[mshrs.scala:402:7] wire [3:0] io_mem_access_bits_size_0; // @[mshrs.scala:402:7] wire [3:0] io_mem_access_bits_source_0; // @[mshrs.scala:402:7] wire [31:0] io_mem_access_bits_address_0; // @[mshrs.scala:402:7] wire [7:0] io_mem_access_bits_mask_0; // @[mshrs.scala:402:7] wire [63:0] io_mem_access_bits_data_0; // @[mshrs.scala:402:7] wire io_mem_access_valid_0; // @[mshrs.scala:402:7] reg [6:0] req_uop_uopc; // @[mshrs.scala:421:16] assign io_resp_bits_uop_uopc_0 = req_uop_uopc; // @[mshrs.scala:402:7, :421:16] reg [31:0] req_uop_inst; // @[mshrs.scala:421:16] assign io_resp_bits_uop_inst_0 = req_uop_inst; // @[mshrs.scala:402:7, :421:16] reg [31:0] req_uop_debug_inst; // @[mshrs.scala:421:16] assign io_resp_bits_uop_debug_inst_0 = req_uop_debug_inst; // @[mshrs.scala:402:7, :421:16] reg req_uop_is_rvc; // @[mshrs.scala:421:16] assign io_resp_bits_uop_is_rvc_0 = req_uop_is_rvc; // @[mshrs.scala:402:7, :421:16] reg [33:0] req_uop_debug_pc; // @[mshrs.scala:421:16] assign io_resp_bits_uop_debug_pc_0 = req_uop_debug_pc; // @[mshrs.scala:402:7, :421:16] reg [2:0] req_uop_iq_type; // @[mshrs.scala:421:16] assign io_resp_bits_uop_iq_type_0 = req_uop_iq_type; // @[mshrs.scala:402:7, :421:16] reg [9:0] req_uop_fu_code; // @[mshrs.scala:421:16] assign io_resp_bits_uop_fu_code_0 = req_uop_fu_code; // @[mshrs.scala:402:7, :421:16] reg [3:0] req_uop_ctrl_br_type; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ctrl_br_type_0 = req_uop_ctrl_br_type; // @[mshrs.scala:402:7, :421:16] reg [1:0] req_uop_ctrl_op1_sel; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ctrl_op1_sel_0 = req_uop_ctrl_op1_sel; // @[mshrs.scala:402:7, :421:16] reg [2:0] req_uop_ctrl_op2_sel; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ctrl_op2_sel_0 = req_uop_ctrl_op2_sel; // @[mshrs.scala:402:7, :421:16] reg [2:0] req_uop_ctrl_imm_sel; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ctrl_imm_sel_0 = req_uop_ctrl_imm_sel; // @[mshrs.scala:402:7, :421:16] reg [4:0] req_uop_ctrl_op_fcn; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ctrl_op_fcn_0 = req_uop_ctrl_op_fcn; // @[mshrs.scala:402:7, :421:16] reg req_uop_ctrl_fcn_dw; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ctrl_fcn_dw_0 = req_uop_ctrl_fcn_dw; // @[mshrs.scala:402:7, :421:16] reg [2:0] req_uop_ctrl_csr_cmd; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ctrl_csr_cmd_0 = req_uop_ctrl_csr_cmd; // @[mshrs.scala:402:7, :421:16] reg req_uop_ctrl_is_load; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ctrl_is_load_0 = req_uop_ctrl_is_load; // @[mshrs.scala:402:7, :421:16] reg req_uop_ctrl_is_sta; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ctrl_is_sta_0 = req_uop_ctrl_is_sta; // @[mshrs.scala:402:7, :421:16] reg req_uop_ctrl_is_std; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ctrl_is_std_0 = req_uop_ctrl_is_std; // @[mshrs.scala:402:7, :421:16] reg [1:0] req_uop_iw_state; // @[mshrs.scala:421:16] assign io_resp_bits_uop_iw_state_0 = req_uop_iw_state; // @[mshrs.scala:402:7, :421:16] reg req_uop_iw_p1_poisoned; // @[mshrs.scala:421:16] assign io_resp_bits_uop_iw_p1_poisoned_0 = req_uop_iw_p1_poisoned; // @[mshrs.scala:402:7, :421:16] reg req_uop_iw_p2_poisoned; // @[mshrs.scala:421:16] assign io_resp_bits_uop_iw_p2_poisoned_0 = req_uop_iw_p2_poisoned; // @[mshrs.scala:402:7, :421:16] reg req_uop_is_br; // @[mshrs.scala:421:16] assign io_resp_bits_uop_is_br_0 = req_uop_is_br; // @[mshrs.scala:402:7, :421:16] reg req_uop_is_jalr; // @[mshrs.scala:421:16] assign io_resp_bits_uop_is_jalr_0 = req_uop_is_jalr; // @[mshrs.scala:402:7, :421:16] reg req_uop_is_jal; // @[mshrs.scala:421:16] assign io_resp_bits_uop_is_jal_0 = req_uop_is_jal; // @[mshrs.scala:402:7, :421:16] reg req_uop_is_sfb; // @[mshrs.scala:421:16] assign io_resp_bits_uop_is_sfb_0 = req_uop_is_sfb; // @[mshrs.scala:402:7, :421:16] reg [3:0] req_uop_br_mask; // @[mshrs.scala:421:16] assign io_resp_bits_uop_br_mask_0 = req_uop_br_mask; // @[mshrs.scala:402:7, :421:16] reg [1:0] req_uop_br_tag; // @[mshrs.scala:421:16] assign io_resp_bits_uop_br_tag_0 = req_uop_br_tag; // @[mshrs.scala:402:7, :421:16] reg [3:0] req_uop_ftq_idx; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ftq_idx_0 = req_uop_ftq_idx; // @[mshrs.scala:402:7, :421:16] reg req_uop_edge_inst; // @[mshrs.scala:421:16] assign io_resp_bits_uop_edge_inst_0 = req_uop_edge_inst; // @[mshrs.scala:402:7, :421:16] reg [5:0] req_uop_pc_lob; // @[mshrs.scala:421:16] assign io_resp_bits_uop_pc_lob_0 = req_uop_pc_lob; // @[mshrs.scala:402:7, :421:16] reg req_uop_taken; // @[mshrs.scala:421:16] assign io_resp_bits_uop_taken_0 = req_uop_taken; // @[mshrs.scala:402:7, :421:16] reg [19:0] req_uop_imm_packed; // @[mshrs.scala:421:16] assign io_resp_bits_uop_imm_packed_0 = req_uop_imm_packed; // @[mshrs.scala:402:7, :421:16] reg [11:0] req_uop_csr_addr; // @[mshrs.scala:421:16] assign io_resp_bits_uop_csr_addr_0 = req_uop_csr_addr; // @[mshrs.scala:402:7, :421:16] reg [5:0] req_uop_rob_idx; // @[mshrs.scala:421:16] assign io_resp_bits_uop_rob_idx_0 = req_uop_rob_idx; // @[mshrs.scala:402:7, :421:16] reg [3:0] req_uop_ldq_idx; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ldq_idx_0 = req_uop_ldq_idx; // @[mshrs.scala:402:7, :421:16] reg [3:0] req_uop_stq_idx; // @[mshrs.scala:421:16] assign io_resp_bits_uop_stq_idx_0 = req_uop_stq_idx; // @[mshrs.scala:402:7, :421:16] reg [1:0] req_uop_rxq_idx; // @[mshrs.scala:421:16] assign io_resp_bits_uop_rxq_idx_0 = req_uop_rxq_idx; // @[mshrs.scala:402:7, :421:16] reg [6:0] req_uop_pdst; // @[mshrs.scala:421:16] assign io_resp_bits_uop_pdst_0 = req_uop_pdst; // @[mshrs.scala:402:7, :421:16] reg [6:0] req_uop_prs1; // @[mshrs.scala:421:16] assign io_resp_bits_uop_prs1_0 = req_uop_prs1; // @[mshrs.scala:402:7, :421:16] reg [6:0] req_uop_prs2; // @[mshrs.scala:421:16] assign io_resp_bits_uop_prs2_0 = req_uop_prs2; // @[mshrs.scala:402:7, :421:16] reg [6:0] req_uop_prs3; // @[mshrs.scala:421:16] assign io_resp_bits_uop_prs3_0 = req_uop_prs3; // @[mshrs.scala:402:7, :421:16] reg [3:0] req_uop_ppred; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ppred_0 = req_uop_ppred; // @[mshrs.scala:402:7, :421:16] reg req_uop_prs1_busy; // @[mshrs.scala:421:16] assign io_resp_bits_uop_prs1_busy_0 = req_uop_prs1_busy; // @[mshrs.scala:402:7, :421:16] reg req_uop_prs2_busy; // @[mshrs.scala:421:16] assign io_resp_bits_uop_prs2_busy_0 = req_uop_prs2_busy; // @[mshrs.scala:402:7, :421:16] reg req_uop_prs3_busy; // @[mshrs.scala:421:16] assign io_resp_bits_uop_prs3_busy_0 = req_uop_prs3_busy; // @[mshrs.scala:402:7, :421:16] reg req_uop_ppred_busy; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ppred_busy_0 = req_uop_ppred_busy; // @[mshrs.scala:402:7, :421:16] reg [6:0] req_uop_stale_pdst; // @[mshrs.scala:421:16] assign io_resp_bits_uop_stale_pdst_0 = req_uop_stale_pdst; // @[mshrs.scala:402:7, :421:16] reg req_uop_exception; // @[mshrs.scala:421:16] assign io_resp_bits_uop_exception_0 = req_uop_exception; // @[mshrs.scala:402:7, :421:16] reg [63:0] req_uop_exc_cause; // @[mshrs.scala:421:16] assign io_resp_bits_uop_exc_cause_0 = req_uop_exc_cause; // @[mshrs.scala:402:7, :421:16] reg req_uop_bypassable; // @[mshrs.scala:421:16] assign io_resp_bits_uop_bypassable_0 = req_uop_bypassable; // @[mshrs.scala:402:7, :421:16] reg [4:0] req_uop_mem_cmd; // @[mshrs.scala:421:16] assign io_resp_bits_uop_mem_cmd_0 = req_uop_mem_cmd; // @[mshrs.scala:402:7, :421:16] reg [1:0] req_uop_mem_size; // @[mshrs.scala:421:16] assign io_resp_bits_uop_mem_size_0 = req_uop_mem_size; // @[mshrs.scala:402:7, :421:16] wire [1:0] size = req_uop_mem_size; // @[AMOALU.scala:11:18] reg req_uop_mem_signed; // @[mshrs.scala:421:16] assign io_resp_bits_uop_mem_signed_0 = req_uop_mem_signed; // @[mshrs.scala:402:7, :421:16] reg req_uop_is_fence; // @[mshrs.scala:421:16] assign io_resp_bits_uop_is_fence_0 = req_uop_is_fence; // @[mshrs.scala:402:7, :421:16] reg req_uop_is_fencei; // @[mshrs.scala:421:16] assign io_resp_bits_uop_is_fencei_0 = req_uop_is_fencei; // @[mshrs.scala:402:7, :421:16] reg req_uop_is_amo; // @[mshrs.scala:421:16] assign io_resp_bits_uop_is_amo_0 = req_uop_is_amo; // @[mshrs.scala:402:7, :421:16] reg req_uop_uses_ldq; // @[mshrs.scala:421:16] assign io_resp_bits_uop_uses_ldq_0 = req_uop_uses_ldq; // @[mshrs.scala:402:7, :421:16] reg req_uop_uses_stq; // @[mshrs.scala:421:16] assign io_resp_bits_uop_uses_stq_0 = req_uop_uses_stq; // @[mshrs.scala:402:7, :421:16] reg req_uop_is_sys_pc2epc; // @[mshrs.scala:421:16] assign io_resp_bits_uop_is_sys_pc2epc_0 = req_uop_is_sys_pc2epc; // @[mshrs.scala:402:7, :421:16] reg req_uop_is_unique; // @[mshrs.scala:421:16] assign io_resp_bits_uop_is_unique_0 = req_uop_is_unique; // @[mshrs.scala:402:7, :421:16] reg req_uop_flush_on_commit; // @[mshrs.scala:421:16] assign io_resp_bits_uop_flush_on_commit_0 = req_uop_flush_on_commit; // @[mshrs.scala:402:7, :421:16] reg req_uop_ldst_is_rs1; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ldst_is_rs1_0 = req_uop_ldst_is_rs1; // @[mshrs.scala:402:7, :421:16] reg [5:0] req_uop_ldst; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ldst_0 = req_uop_ldst; // @[mshrs.scala:402:7, :421:16] reg [5:0] req_uop_lrs1; // @[mshrs.scala:421:16] assign io_resp_bits_uop_lrs1_0 = req_uop_lrs1; // @[mshrs.scala:402:7, :421:16] reg [5:0] req_uop_lrs2; // @[mshrs.scala:421:16] assign io_resp_bits_uop_lrs2_0 = req_uop_lrs2; // @[mshrs.scala:402:7, :421:16] reg [5:0] req_uop_lrs3; // @[mshrs.scala:421:16] assign io_resp_bits_uop_lrs3_0 = req_uop_lrs3; // @[mshrs.scala:402:7, :421:16] reg req_uop_ldst_val; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ldst_val_0 = req_uop_ldst_val; // @[mshrs.scala:402:7, :421:16] reg [1:0] req_uop_dst_rtype; // @[mshrs.scala:421:16] assign io_resp_bits_uop_dst_rtype_0 = req_uop_dst_rtype; // @[mshrs.scala:402:7, :421:16] reg [1:0] req_uop_lrs1_rtype; // @[mshrs.scala:421:16] assign io_resp_bits_uop_lrs1_rtype_0 = req_uop_lrs1_rtype; // @[mshrs.scala:402:7, :421:16] reg [1:0] req_uop_lrs2_rtype; // @[mshrs.scala:421:16] assign io_resp_bits_uop_lrs2_rtype_0 = req_uop_lrs2_rtype; // @[mshrs.scala:402:7, :421:16] reg req_uop_frs3_en; // @[mshrs.scala:421:16] assign io_resp_bits_uop_frs3_en_0 = req_uop_frs3_en; // @[mshrs.scala:402:7, :421:16] reg req_uop_fp_val; // @[mshrs.scala:421:16] assign io_resp_bits_uop_fp_val_0 = req_uop_fp_val; // @[mshrs.scala:402:7, :421:16] reg req_uop_fp_single; // @[mshrs.scala:421:16] assign io_resp_bits_uop_fp_single_0 = req_uop_fp_single; // @[mshrs.scala:402:7, :421:16] reg req_uop_xcpt_pf_if; // @[mshrs.scala:421:16] assign io_resp_bits_uop_xcpt_pf_if_0 = req_uop_xcpt_pf_if; // @[mshrs.scala:402:7, :421:16] reg req_uop_xcpt_ae_if; // @[mshrs.scala:421:16] assign io_resp_bits_uop_xcpt_ae_if_0 = req_uop_xcpt_ae_if; // @[mshrs.scala:402:7, :421:16] reg req_uop_xcpt_ma_if; // @[mshrs.scala:421:16] assign io_resp_bits_uop_xcpt_ma_if_0 = req_uop_xcpt_ma_if; // @[mshrs.scala:402:7, :421:16] reg req_uop_bp_debug_if; // @[mshrs.scala:421:16] assign io_resp_bits_uop_bp_debug_if_0 = req_uop_bp_debug_if; // @[mshrs.scala:402:7, :421:16] reg req_uop_bp_xcpt_if; // @[mshrs.scala:421:16] assign io_resp_bits_uop_bp_xcpt_if_0 = req_uop_bp_xcpt_if; // @[mshrs.scala:402:7, :421:16] reg [1:0] req_uop_debug_fsrc; // @[mshrs.scala:421:16] assign io_resp_bits_uop_debug_fsrc_0 = req_uop_debug_fsrc; // @[mshrs.scala:402:7, :421:16] reg [1:0] req_uop_debug_tsrc; // @[mshrs.scala:421:16] assign io_resp_bits_uop_debug_tsrc_0 = req_uop_debug_tsrc; // @[mshrs.scala:402:7, :421:16] reg [33:0] req_addr; // @[mshrs.scala:421:16] wire [33:0] _get_legal_T_4 = req_addr; // @[Parameters.scala:137:31] wire [33:0] _put_legal_T_4 = req_addr; // @[Parameters.scala:137:31] wire [33:0] _atomics_legal_T_4 = req_addr; // @[Parameters.scala:137:31] wire [33:0] _atomics_legal_T_14 = req_addr; // @[Parameters.scala:137:31] wire [33:0] _atomics_legal_T_24 = req_addr; // @[Parameters.scala:137:31] wire [33:0] _atomics_legal_T_34 = req_addr; // @[Parameters.scala:137:31] wire [33:0] _atomics_legal_T_44 = req_addr; // @[Parameters.scala:137:31] wire [33:0] _atomics_legal_T_54 = req_addr; // @[Parameters.scala:137:31] wire [33:0] _atomics_legal_T_64 = req_addr; // @[Parameters.scala:137:31] wire [33:0] _atomics_legal_T_74 = req_addr; // @[Parameters.scala:137:31] wire [33:0] _atomics_legal_T_84 = req_addr; // @[Parameters.scala:137:31] reg [63:0] req_data; // @[mshrs.scala:421:16] wire [63:0] put_data = req_data; // @[Edges.scala:480:17] wire [63:0] atomics_a_data = req_data; // @[Edges.scala:534:17] wire [63:0] atomics_a_1_data = req_data; // @[Edges.scala:534:17] wire [63:0] atomics_a_2_data = req_data; // @[Edges.scala:534:17] wire [63:0] atomics_a_3_data = req_data; // @[Edges.scala:534:17] wire [63:0] atomics_a_4_data = req_data; // @[Edges.scala:517:17] wire [63:0] atomics_a_5_data = req_data; // @[Edges.scala:517:17] wire [63:0] atomics_a_6_data = req_data; // @[Edges.scala:517:17] wire [63:0] atomics_a_7_data = req_data; // @[Edges.scala:517:17] wire [63:0] atomics_a_8_data = req_data; // @[Edges.scala:517:17] reg req_is_hella; // @[mshrs.scala:421:16] assign io_resp_bits_is_hella_0 = req_is_hella; // @[mshrs.scala:402:7, :421:16] reg [63:0] grant_word; // @[mshrs.scala:422:23] reg [1:0] state; // @[mshrs.scala:426:22] assign _io_req_ready_T = state == 2'h0; // @[mshrs.scala:426:22, :427:25] assign io_req_ready_0 = _io_req_ready_T; // @[mshrs.scala:402:7, :427:25] wire [34:0] _get_legal_T_5 = {1'h0, _get_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [34:0] _get_legal_T_6 = _get_legal_T_5 & 35'h80110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _get_legal_T_7 = _get_legal_T_6; // @[Parameters.scala:137:46] wire _get_legal_T_8 = _get_legal_T_7 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _get_legal_T_9 = _get_legal_T_8; // @[Parameters.scala:684:54] wire _get_legal_T_32 = _get_legal_T_9; // @[Parameters.scala:684:54, :686:26] wire [33:0] _GEN = {req_addr[33:17], req_addr[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31] wire [33:0] _get_legal_T_14; // @[Parameters.scala:137:31] assign _get_legal_T_14 = _GEN; // @[Parameters.scala:137:31] wire [33:0] _put_legal_T_14; // @[Parameters.scala:137:31] assign _put_legal_T_14 = _GEN; // @[Parameters.scala:137:31] wire [34:0] _get_legal_T_15 = {1'h0, _get_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [34:0] _get_legal_T_16 = _get_legal_T_15 & 35'h80110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _get_legal_T_17 = _get_legal_T_16; // @[Parameters.scala:137:46] wire _get_legal_T_18 = _get_legal_T_17 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [33:0] _GEN_0 = {req_addr[33:21], req_addr[20:0] ^ 21'h100000}; // @[Parameters.scala:137:31] wire [33:0] _get_legal_T_19; // @[Parameters.scala:137:31] assign _get_legal_T_19 = _GEN_0; // @[Parameters.scala:137:31] wire [33:0] _put_legal_T_19; // @[Parameters.scala:137:31] assign _put_legal_T_19 = _GEN_0; // @[Parameters.scala:137:31] wire [34:0] _get_legal_T_20 = {1'h0, _get_legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [34:0] _get_legal_T_21 = _get_legal_T_20 & 35'h80100000; // @[Parameters.scala:137:{41,46}] wire [34:0] _get_legal_T_22 = _get_legal_T_21; // @[Parameters.scala:137:46] wire _get_legal_T_23 = _get_legal_T_22 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] get_address = req_addr[31:0]; // @[Edges.scala:460:17] wire [31:0] put_address = req_addr[31:0]; // @[Edges.scala:480:17] wire [31:0] atomics_a_address = req_addr[31:0]; // @[Edges.scala:534:17] wire [31:0] atomics_a_1_address = req_addr[31:0]; // @[Edges.scala:534:17] wire [31:0] atomics_a_2_address = req_addr[31:0]; // @[Edges.scala:534:17] wire [31:0] atomics_a_3_address = req_addr[31:0]; // @[Edges.scala:534:17] wire [31:0] atomics_a_4_address = req_addr[31:0]; // @[Edges.scala:517:17] wire [31:0] atomics_a_5_address = req_addr[31:0]; // @[Edges.scala:517:17] wire [31:0] atomics_a_6_address = req_addr[31:0]; // @[Edges.scala:517:17] wire [31:0] atomics_a_7_address = req_addr[31:0]; // @[Edges.scala:517:17] wire [31:0] atomics_a_8_address = req_addr[31:0]; // @[Edges.scala:517:17] wire [33:0] _GEN_1 = {req_addr[33:32], req_addr[31:0] ^ 32'h80000000}; // @[Parameters.scala:137:31] wire [33:0] _get_legal_T_24; // @[Parameters.scala:137:31] assign _get_legal_T_24 = _GEN_1; // @[Parameters.scala:137:31] wire [33:0] _put_legal_T_24; // @[Parameters.scala:137:31] assign _put_legal_T_24 = _GEN_1; // @[Parameters.scala:137:31] wire [34:0] _get_legal_T_25 = {1'h0, _get_legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [34:0] _get_legal_T_26 = _get_legal_T_25 & 35'h80000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _get_legal_T_27 = _get_legal_T_26; // @[Parameters.scala:137:46] wire _get_legal_T_28 = _get_legal_T_27 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _get_legal_T_29 = _get_legal_T_18 | _get_legal_T_23; // @[Parameters.scala:685:42] wire _get_legal_T_30 = _get_legal_T_29 | _get_legal_T_28; // @[Parameters.scala:685:42] wire _get_legal_T_31 = _get_legal_T_30; // @[Parameters.scala:684:54, :685:42] wire get_legal = _get_legal_T_32 | _get_legal_T_31; // @[Parameters.scala:684:54, :686:26] wire [7:0] _get_a_mask_T; // @[Misc.scala:222:10] wire [3:0] get_size; // @[Edges.scala:460:17] wire [7:0] get_mask; // @[Edges.scala:460:17] wire [3:0] _GEN_2 = {2'h0, req_uop_mem_size}; // @[Edges.scala:463:15] assign get_size = _GEN_2; // @[Edges.scala:460:17, :463:15] wire [3:0] put_size; // @[Edges.scala:480:17] assign put_size = _GEN_2; // @[Edges.scala:463:15, :480:17] wire [3:0] atomics_a_size; // @[Edges.scala:534:17] assign atomics_a_size = _GEN_2; // @[Edges.scala:463:15, :534:17] wire [3:0] atomics_a_1_size; // @[Edges.scala:534:17] assign atomics_a_1_size = _GEN_2; // @[Edges.scala:463:15, :534:17] wire [3:0] atomics_a_2_size; // @[Edges.scala:534:17] assign atomics_a_2_size = _GEN_2; // @[Edges.scala:463:15, :534:17] wire [3:0] atomics_a_3_size; // @[Edges.scala:534:17] assign atomics_a_3_size = _GEN_2; // @[Edges.scala:463:15, :534:17] wire [3:0] atomics_a_4_size; // @[Edges.scala:517:17] assign atomics_a_4_size = _GEN_2; // @[Edges.scala:463:15, :517:17] wire [3:0] atomics_a_5_size; // @[Edges.scala:517:17] assign atomics_a_5_size = _GEN_2; // @[Edges.scala:463:15, :517:17] wire [3:0] atomics_a_6_size; // @[Edges.scala:517:17] assign atomics_a_6_size = _GEN_2; // @[Edges.scala:463:15, :517:17] wire [3:0] atomics_a_7_size; // @[Edges.scala:517:17] assign atomics_a_7_size = _GEN_2; // @[Edges.scala:463:15, :517:17] wire [3:0] atomics_a_8_size; // @[Edges.scala:517:17] assign atomics_a_8_size = _GEN_2; // @[Edges.scala:463:15, :517:17] wire [2:0] _GEN_3 = {1'h0, req_uop_mem_size}; // @[Misc.scala:202:34] wire [2:0] _get_a_mask_sizeOH_T; // @[Misc.scala:202:34] assign _get_a_mask_sizeOH_T = _GEN_3; // @[Misc.scala:202:34] wire [2:0] _put_a_mask_sizeOH_T; // @[Misc.scala:202:34] assign _put_a_mask_sizeOH_T = _GEN_3; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T = _GEN_3; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T_3; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_3 = _GEN_3; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T_6; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_6 = _GEN_3; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T_9; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_9 = _GEN_3; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T_12; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_12 = _GEN_3; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T_15; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_15 = _GEN_3; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T_18; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_18 = _GEN_3; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T_21; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_21 = _GEN_3; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T_24; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_24 = _GEN_3; // @[Misc.scala:202:34] wire [1:0] get_a_mask_sizeOH_shiftAmount = _get_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _get_a_mask_sizeOH_T_1 = 4'h1 << get_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _get_a_mask_sizeOH_T_2 = _get_a_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] get_a_mask_sizeOH = {_get_a_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire get_a_mask_sub_sub_sub_0_1 = &req_uop_mem_size; // @[Misc.scala:206:21] wire get_a_mask_sub_sub_size = get_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire get_a_mask_sub_sub_bit = req_addr[2]; // @[Misc.scala:210:26] wire put_a_mask_sub_sub_bit = req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit = req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_1 = req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_2 = req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_3 = req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_4 = req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_5 = req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_6 = req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_7 = req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_8 = req_addr[2]; // @[Misc.scala:210:26] wire _io_resp_bits_data_shifted_T = req_addr[2]; // @[Misc.scala:210:26] wire get_a_mask_sub_sub_1_2 = get_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire get_a_mask_sub_sub_nbit = ~get_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire get_a_mask_sub_sub_0_2 = get_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_sub_sub_acc_T = get_a_mask_sub_sub_size & get_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_sub_0_1 = get_a_mask_sub_sub_sub_0_1 | _get_a_mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _get_a_mask_sub_sub_acc_T_1 = get_a_mask_sub_sub_size & get_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_sub_1_1 = get_a_mask_sub_sub_sub_0_1 | _get_a_mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire get_a_mask_sub_size = get_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire get_a_mask_sub_bit = req_addr[1]; // @[Misc.scala:210:26] wire put_a_mask_sub_bit = req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit = req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_1 = req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_2 = req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_3 = req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_4 = req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_5 = req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_6 = req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_7 = req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_8 = req_addr[1]; // @[Misc.scala:210:26] wire _io_resp_bits_data_shifted_T_3 = req_addr[1]; // @[Misc.scala:210:26] wire get_a_mask_sub_nbit = ~get_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire get_a_mask_sub_0_2 = get_a_mask_sub_sub_0_2 & get_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_sub_acc_T = get_a_mask_sub_size & get_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_0_1 = get_a_mask_sub_sub_0_1 | _get_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_1_2 = get_a_mask_sub_sub_0_2 & get_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_sub_acc_T_1 = get_a_mask_sub_size & get_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_1_1 = get_a_mask_sub_sub_0_1 | _get_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_2_2 = get_a_mask_sub_sub_1_2 & get_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_sub_acc_T_2 = get_a_mask_sub_size & get_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_2_1 = get_a_mask_sub_sub_1_1 | _get_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_3_2 = get_a_mask_sub_sub_1_2 & get_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_sub_acc_T_3 = get_a_mask_sub_size & get_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_3_1 = get_a_mask_sub_sub_1_1 | _get_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire get_a_mask_size = get_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire get_a_mask_bit = req_addr[0]; // @[Misc.scala:210:26] wire put_a_mask_bit = req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit = req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_1 = req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_2 = req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_3 = req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_4 = req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_5 = req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_6 = req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_7 = req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_8 = req_addr[0]; // @[Misc.scala:210:26] wire _io_resp_bits_data_shifted_T_6 = req_addr[0]; // @[Misc.scala:210:26] wire get_a_mask_nbit = ~get_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire get_a_mask_eq = get_a_mask_sub_0_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T = get_a_mask_size & get_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc = get_a_mask_sub_0_1 | _get_a_mask_acc_T; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_1 = get_a_mask_sub_0_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_1 = get_a_mask_size & get_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_1 = get_a_mask_sub_0_1 | _get_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_2 = get_a_mask_sub_1_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T_2 = get_a_mask_size & get_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_2 = get_a_mask_sub_1_1 | _get_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_3 = get_a_mask_sub_1_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_3 = get_a_mask_size & get_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_3 = get_a_mask_sub_1_1 | _get_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_4 = get_a_mask_sub_2_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T_4 = get_a_mask_size & get_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_4 = get_a_mask_sub_2_1 | _get_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_5 = get_a_mask_sub_2_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_5 = get_a_mask_size & get_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_5 = get_a_mask_sub_2_1 | _get_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_6 = get_a_mask_sub_3_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T_6 = get_a_mask_size & get_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_6 = get_a_mask_sub_3_1 | _get_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_7 = get_a_mask_sub_3_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_7 = get_a_mask_size & get_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_7 = get_a_mask_sub_3_1 | _get_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] get_a_mask_lo_lo = {get_a_mask_acc_1, get_a_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] get_a_mask_lo_hi = {get_a_mask_acc_3, get_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] get_a_mask_lo = {get_a_mask_lo_hi, get_a_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] get_a_mask_hi_lo = {get_a_mask_acc_5, get_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] get_a_mask_hi_hi = {get_a_mask_acc_7, get_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] get_a_mask_hi = {get_a_mask_hi_hi, get_a_mask_hi_lo}; // @[Misc.scala:222:10] assign _get_a_mask_T = {get_a_mask_hi, get_a_mask_lo}; // @[Misc.scala:222:10] assign get_mask = _get_a_mask_T; // @[Misc.scala:222:10] wire [34:0] _put_legal_T_5 = {1'h0, _put_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [34:0] _put_legal_T_6 = _put_legal_T_5 & 35'h80110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _put_legal_T_7 = _put_legal_T_6; // @[Parameters.scala:137:46] wire _put_legal_T_8 = _put_legal_T_7 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _put_legal_T_9 = _put_legal_T_8; // @[Parameters.scala:684:54] wire _put_legal_T_32 = _put_legal_T_9; // @[Parameters.scala:684:54, :686:26] wire [34:0] _put_legal_T_15 = {1'h0, _put_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [34:0] _put_legal_T_16 = _put_legal_T_15 & 35'h80110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _put_legal_T_17 = _put_legal_T_16; // @[Parameters.scala:137:46] wire _put_legal_T_18 = _put_legal_T_17 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _put_legal_T_20 = {1'h0, _put_legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [34:0] _put_legal_T_21 = _put_legal_T_20 & 35'h80100000; // @[Parameters.scala:137:{41,46}] wire [34:0] _put_legal_T_22 = _put_legal_T_21; // @[Parameters.scala:137:46] wire _put_legal_T_23 = _put_legal_T_22 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _put_legal_T_25 = {1'h0, _put_legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [34:0] _put_legal_T_26 = _put_legal_T_25 & 35'h80000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _put_legal_T_27 = _put_legal_T_26; // @[Parameters.scala:137:46] wire _put_legal_T_28 = _put_legal_T_27 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _put_legal_T_29 = _put_legal_T_18 | _put_legal_T_23; // @[Parameters.scala:685:42] wire _put_legal_T_30 = _put_legal_T_29 | _put_legal_T_28; // @[Parameters.scala:685:42] wire _put_legal_T_31 = _put_legal_T_30; // @[Parameters.scala:684:54, :685:42] wire put_legal = _put_legal_T_32 | _put_legal_T_31; // @[Parameters.scala:684:54, :686:26] wire [7:0] _put_a_mask_T; // @[Misc.scala:222:10] wire [7:0] put_mask; // @[Edges.scala:480:17] wire [1:0] put_a_mask_sizeOH_shiftAmount = _put_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _put_a_mask_sizeOH_T_1 = 4'h1 << put_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _put_a_mask_sizeOH_T_2 = _put_a_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] put_a_mask_sizeOH = {_put_a_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire put_a_mask_sub_sub_sub_0_1 = &req_uop_mem_size; // @[Misc.scala:206:21] wire put_a_mask_sub_sub_size = put_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire put_a_mask_sub_sub_1_2 = put_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire put_a_mask_sub_sub_nbit = ~put_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire put_a_mask_sub_sub_0_2 = put_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_sub_sub_acc_T = put_a_mask_sub_sub_size & put_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_sub_0_1 = put_a_mask_sub_sub_sub_0_1 | _put_a_mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _put_a_mask_sub_sub_acc_T_1 = put_a_mask_sub_sub_size & put_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_sub_1_1 = put_a_mask_sub_sub_sub_0_1 | _put_a_mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire put_a_mask_sub_size = put_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire put_a_mask_sub_nbit = ~put_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire put_a_mask_sub_0_2 = put_a_mask_sub_sub_0_2 & put_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_sub_acc_T = put_a_mask_sub_size & put_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_0_1 = put_a_mask_sub_sub_0_1 | _put_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_1_2 = put_a_mask_sub_sub_0_2 & put_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_sub_acc_T_1 = put_a_mask_sub_size & put_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_1_1 = put_a_mask_sub_sub_0_1 | _put_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_2_2 = put_a_mask_sub_sub_1_2 & put_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_sub_acc_T_2 = put_a_mask_sub_size & put_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_2_1 = put_a_mask_sub_sub_1_1 | _put_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_3_2 = put_a_mask_sub_sub_1_2 & put_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_sub_acc_T_3 = put_a_mask_sub_size & put_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_3_1 = put_a_mask_sub_sub_1_1 | _put_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire put_a_mask_size = put_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire put_a_mask_nbit = ~put_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire put_a_mask_eq = put_a_mask_sub_0_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T = put_a_mask_size & put_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc = put_a_mask_sub_0_1 | _put_a_mask_acc_T; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_1 = put_a_mask_sub_0_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_1 = put_a_mask_size & put_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_1 = put_a_mask_sub_0_1 | _put_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_2 = put_a_mask_sub_1_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T_2 = put_a_mask_size & put_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_2 = put_a_mask_sub_1_1 | _put_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_3 = put_a_mask_sub_1_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_3 = put_a_mask_size & put_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_3 = put_a_mask_sub_1_1 | _put_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_4 = put_a_mask_sub_2_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T_4 = put_a_mask_size & put_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_4 = put_a_mask_sub_2_1 | _put_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_5 = put_a_mask_sub_2_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_5 = put_a_mask_size & put_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_5 = put_a_mask_sub_2_1 | _put_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_6 = put_a_mask_sub_3_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T_6 = put_a_mask_size & put_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_6 = put_a_mask_sub_3_1 | _put_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_7 = put_a_mask_sub_3_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_7 = put_a_mask_size & put_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_7 = put_a_mask_sub_3_1 | _put_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] put_a_mask_lo_lo = {put_a_mask_acc_1, put_a_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] put_a_mask_lo_hi = {put_a_mask_acc_3, put_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] put_a_mask_lo = {put_a_mask_lo_hi, put_a_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] put_a_mask_hi_lo = {put_a_mask_acc_5, put_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] put_a_mask_hi_hi = {put_a_mask_acc_7, put_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] put_a_mask_hi = {put_a_mask_hi_hi, put_a_mask_hi_lo}; // @[Misc.scala:222:10] assign _put_a_mask_T = {put_a_mask_hi, put_a_mask_lo}; // @[Misc.scala:222:10] assign put_mask = _put_a_mask_T; // @[Misc.scala:222:10] wire [34:0] _atomics_legal_T_5 = {1'h0, _atomics_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [7:0] _atomics_a_mask_T; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask; // @[Edges.scala:534:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount = _atomics_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_1 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_2 = _atomics_a_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH = {_atomics_a_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1 = &req_uop_mem_size; // @[Misc.scala:206:21] wire atomics_a_mask_sub_sub_size = atomics_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2 = atomics_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit = ~atomics_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2 = atomics_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T = atomics_a_mask_sub_sub_size & atomics_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1 = atomics_a_mask_sub_sub_sub_0_1 | _atomics_a_mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_1 = atomics_a_mask_sub_sub_size & atomics_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1 = atomics_a_mask_sub_sub_sub_0_1 | _atomics_a_mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size = atomics_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit = ~atomics_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2 = atomics_a_mask_sub_sub_0_2 & atomics_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T = atomics_a_mask_sub_size & atomics_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1 = atomics_a_mask_sub_sub_0_1 | _atomics_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2 = atomics_a_mask_sub_sub_0_2 & atomics_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_1 = atomics_a_mask_sub_size & atomics_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1 = atomics_a_mask_sub_sub_0_1 | _atomics_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2 = atomics_a_mask_sub_sub_1_2 & atomics_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_2 = atomics_a_mask_sub_size & atomics_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1 = atomics_a_mask_sub_sub_1_1 | _atomics_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2 = atomics_a_mask_sub_sub_1_2 & atomics_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_3 = atomics_a_mask_sub_size & atomics_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1 = atomics_a_mask_sub_sub_1_1 | _atomics_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size = atomics_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit = ~atomics_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq = atomics_a_mask_sub_0_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T = atomics_a_mask_size & atomics_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc = atomics_a_mask_sub_0_1 | _atomics_a_mask_acc_T; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_1 = atomics_a_mask_sub_0_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_1 = atomics_a_mask_size & atomics_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_1 = atomics_a_mask_sub_0_1 | _atomics_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_2 = atomics_a_mask_sub_1_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_2 = atomics_a_mask_size & atomics_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_2 = atomics_a_mask_sub_1_1 | _atomics_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_3 = atomics_a_mask_sub_1_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_3 = atomics_a_mask_size & atomics_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_3 = atomics_a_mask_sub_1_1 | _atomics_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_4 = atomics_a_mask_sub_2_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_4 = atomics_a_mask_size & atomics_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_4 = atomics_a_mask_sub_2_1 | _atomics_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_5 = atomics_a_mask_sub_2_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_5 = atomics_a_mask_size & atomics_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_5 = atomics_a_mask_sub_2_1 | _atomics_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_6 = atomics_a_mask_sub_3_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_6 = atomics_a_mask_size & atomics_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_6 = atomics_a_mask_sub_3_1 | _atomics_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_7 = atomics_a_mask_sub_3_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_7 = atomics_a_mask_size & atomics_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_7 = atomics_a_mask_sub_3_1 | _atomics_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo = {atomics_a_mask_acc_1, atomics_a_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi = {atomics_a_mask_acc_3, atomics_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo = {atomics_a_mask_lo_hi, atomics_a_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo = {atomics_a_mask_acc_5, atomics_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi = {atomics_a_mask_acc_7, atomics_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi = {atomics_a_mask_hi_hi, atomics_a_mask_hi_lo}; // @[Misc.scala:222:10] assign _atomics_a_mask_T = {atomics_a_mask_hi, atomics_a_mask_lo}; // @[Misc.scala:222:10] assign atomics_a_mask = _atomics_a_mask_T; // @[Misc.scala:222:10] wire [34:0] _atomics_legal_T_15 = {1'h0, _atomics_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [7:0] _atomics_a_mask_T_1; // @[Misc.scala:222:10] wire [7:0] atomics_a_1_mask; // @[Edges.scala:534:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_1 = _atomics_a_mask_sizeOH_T_3[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_4 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_1; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_5 = _atomics_a_mask_sizeOH_T_4[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH_1 = {_atomics_a_mask_sizeOH_T_5[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1_1 = &req_uop_mem_size; // @[Misc.scala:206:21] wire atomics_a_mask_sub_sub_size_1 = atomics_a_mask_sizeOH_1[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2_1 = atomics_a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit_1 = ~atomics_a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_1 = atomics_a_mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_2 = atomics_a_mask_sub_sub_size_1 & atomics_a_mask_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_1 = atomics_a_mask_sub_sub_sub_0_1_1 | _atomics_a_mask_sub_sub_acc_T_2; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_3 = atomics_a_mask_sub_sub_size_1 & atomics_a_mask_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_1 = atomics_a_mask_sub_sub_sub_0_1_1 | _atomics_a_mask_sub_sub_acc_T_3; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size_1 = atomics_a_mask_sizeOH_1[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_1 = ~atomics_a_mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_1 = atomics_a_mask_sub_sub_0_2_1 & atomics_a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_4 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_1 = atomics_a_mask_sub_sub_0_1_1 | _atomics_a_mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_1 = atomics_a_mask_sub_sub_0_2_1 & atomics_a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_5 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_1 = atomics_a_mask_sub_sub_0_1_1 | _atomics_a_mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_1 = atomics_a_mask_sub_sub_1_2_1 & atomics_a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_6 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_1 = atomics_a_mask_sub_sub_1_1_1 | _atomics_a_mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_1 = atomics_a_mask_sub_sub_1_2_1 & atomics_a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_7 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_1 = atomics_a_mask_sub_sub_1_1_1 | _atomics_a_mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_1 = atomics_a_mask_sizeOH_1[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_1 = ~atomics_a_mask_bit_1; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_8 = atomics_a_mask_sub_0_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_8 = atomics_a_mask_size_1 & atomics_a_mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_8 = atomics_a_mask_sub_0_1_1 | _atomics_a_mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_9 = atomics_a_mask_sub_0_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_9 = atomics_a_mask_size_1 & atomics_a_mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_9 = atomics_a_mask_sub_0_1_1 | _atomics_a_mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_10 = atomics_a_mask_sub_1_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_10 = atomics_a_mask_size_1 & atomics_a_mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_10 = atomics_a_mask_sub_1_1_1 | _atomics_a_mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_11 = atomics_a_mask_sub_1_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_11 = atomics_a_mask_size_1 & atomics_a_mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_11 = atomics_a_mask_sub_1_1_1 | _atomics_a_mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_12 = atomics_a_mask_sub_2_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_12 = atomics_a_mask_size_1 & atomics_a_mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_12 = atomics_a_mask_sub_2_1_1 | _atomics_a_mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_13 = atomics_a_mask_sub_2_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_13 = atomics_a_mask_size_1 & atomics_a_mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_13 = atomics_a_mask_sub_2_1_1 | _atomics_a_mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_14 = atomics_a_mask_sub_3_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_14 = atomics_a_mask_size_1 & atomics_a_mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_14 = atomics_a_mask_sub_3_1_1 | _atomics_a_mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_15 = atomics_a_mask_sub_3_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_15 = atomics_a_mask_size_1 & atomics_a_mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_15 = atomics_a_mask_sub_3_1_1 | _atomics_a_mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_1 = {atomics_a_mask_acc_9, atomics_a_mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_1 = {atomics_a_mask_acc_11, atomics_a_mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_1 = {atomics_a_mask_lo_hi_1, atomics_a_mask_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_1 = {atomics_a_mask_acc_13, atomics_a_mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_1 = {atomics_a_mask_acc_15, atomics_a_mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_1 = {atomics_a_mask_hi_hi_1, atomics_a_mask_hi_lo_1}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_1 = {atomics_a_mask_hi_1, atomics_a_mask_lo_1}; // @[Misc.scala:222:10] assign atomics_a_1_mask = _atomics_a_mask_T_1; // @[Misc.scala:222:10] wire [34:0] _atomics_legal_T_25 = {1'h0, _atomics_legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [7:0] _atomics_a_mask_T_2; // @[Misc.scala:222:10] wire [7:0] atomics_a_2_mask; // @[Edges.scala:534:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_2 = _atomics_a_mask_sizeOH_T_6[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_7 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_2; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_8 = _atomics_a_mask_sizeOH_T_7[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH_2 = {_atomics_a_mask_sizeOH_T_8[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1_2 = &req_uop_mem_size; // @[Misc.scala:206:21] wire atomics_a_mask_sub_sub_size_2 = atomics_a_mask_sizeOH_2[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2_2 = atomics_a_mask_sub_sub_bit_2; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit_2 = ~atomics_a_mask_sub_sub_bit_2; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_2 = atomics_a_mask_sub_sub_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_4 = atomics_a_mask_sub_sub_size_2 & atomics_a_mask_sub_sub_0_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_2 = atomics_a_mask_sub_sub_sub_0_1_2 | _atomics_a_mask_sub_sub_acc_T_4; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_5 = atomics_a_mask_sub_sub_size_2 & atomics_a_mask_sub_sub_1_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_2 = atomics_a_mask_sub_sub_sub_0_1_2 | _atomics_a_mask_sub_sub_acc_T_5; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size_2 = atomics_a_mask_sizeOH_2[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_2 = ~atomics_a_mask_sub_bit_2; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_2 = atomics_a_mask_sub_sub_0_2_2 & atomics_a_mask_sub_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_8 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_0_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_2 = atomics_a_mask_sub_sub_0_1_2 | _atomics_a_mask_sub_acc_T_8; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_2 = atomics_a_mask_sub_sub_0_2_2 & atomics_a_mask_sub_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_9 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_1_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_2 = atomics_a_mask_sub_sub_0_1_2 | _atomics_a_mask_sub_acc_T_9; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_2 = atomics_a_mask_sub_sub_1_2_2 & atomics_a_mask_sub_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_10 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_2_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_2 = atomics_a_mask_sub_sub_1_1_2 | _atomics_a_mask_sub_acc_T_10; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_2 = atomics_a_mask_sub_sub_1_2_2 & atomics_a_mask_sub_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_11 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_3_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_2 = atomics_a_mask_sub_sub_1_1_2 | _atomics_a_mask_sub_acc_T_11; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_2 = atomics_a_mask_sizeOH_2[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_2 = ~atomics_a_mask_bit_2; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_16 = atomics_a_mask_sub_0_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_16 = atomics_a_mask_size_2 & atomics_a_mask_eq_16; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_16 = atomics_a_mask_sub_0_1_2 | _atomics_a_mask_acc_T_16; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_17 = atomics_a_mask_sub_0_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_17 = atomics_a_mask_size_2 & atomics_a_mask_eq_17; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_17 = atomics_a_mask_sub_0_1_2 | _atomics_a_mask_acc_T_17; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_18 = atomics_a_mask_sub_1_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_18 = atomics_a_mask_size_2 & atomics_a_mask_eq_18; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_18 = atomics_a_mask_sub_1_1_2 | _atomics_a_mask_acc_T_18; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_19 = atomics_a_mask_sub_1_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_19 = atomics_a_mask_size_2 & atomics_a_mask_eq_19; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_19 = atomics_a_mask_sub_1_1_2 | _atomics_a_mask_acc_T_19; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_20 = atomics_a_mask_sub_2_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_20 = atomics_a_mask_size_2 & atomics_a_mask_eq_20; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_20 = atomics_a_mask_sub_2_1_2 | _atomics_a_mask_acc_T_20; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_21 = atomics_a_mask_sub_2_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_21 = atomics_a_mask_size_2 & atomics_a_mask_eq_21; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_21 = atomics_a_mask_sub_2_1_2 | _atomics_a_mask_acc_T_21; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_22 = atomics_a_mask_sub_3_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_22 = atomics_a_mask_size_2 & atomics_a_mask_eq_22; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_22 = atomics_a_mask_sub_3_1_2 | _atomics_a_mask_acc_T_22; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_23 = atomics_a_mask_sub_3_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_23 = atomics_a_mask_size_2 & atomics_a_mask_eq_23; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_23 = atomics_a_mask_sub_3_1_2 | _atomics_a_mask_acc_T_23; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_2 = {atomics_a_mask_acc_17, atomics_a_mask_acc_16}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_2 = {atomics_a_mask_acc_19, atomics_a_mask_acc_18}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_2 = {atomics_a_mask_lo_hi_2, atomics_a_mask_lo_lo_2}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_2 = {atomics_a_mask_acc_21, atomics_a_mask_acc_20}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_2 = {atomics_a_mask_acc_23, atomics_a_mask_acc_22}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_2 = {atomics_a_mask_hi_hi_2, atomics_a_mask_hi_lo_2}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_2 = {atomics_a_mask_hi_2, atomics_a_mask_lo_2}; // @[Misc.scala:222:10] assign atomics_a_2_mask = _atomics_a_mask_T_2; // @[Misc.scala:222:10] wire [34:0] _atomics_legal_T_35 = {1'h0, _atomics_legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [7:0] _atomics_a_mask_T_3; // @[Misc.scala:222:10] wire [7:0] atomics_a_3_mask; // @[Edges.scala:534:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_3 = _atomics_a_mask_sizeOH_T_9[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_10 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_3; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_11 = _atomics_a_mask_sizeOH_T_10[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH_3 = {_atomics_a_mask_sizeOH_T_11[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1_3 = &req_uop_mem_size; // @[Misc.scala:206:21] wire atomics_a_mask_sub_sub_size_3 = atomics_a_mask_sizeOH_3[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2_3 = atomics_a_mask_sub_sub_bit_3; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit_3 = ~atomics_a_mask_sub_sub_bit_3; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_3 = atomics_a_mask_sub_sub_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_6 = atomics_a_mask_sub_sub_size_3 & atomics_a_mask_sub_sub_0_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_3 = atomics_a_mask_sub_sub_sub_0_1_3 | _atomics_a_mask_sub_sub_acc_T_6; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_7 = atomics_a_mask_sub_sub_size_3 & atomics_a_mask_sub_sub_1_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_3 = atomics_a_mask_sub_sub_sub_0_1_3 | _atomics_a_mask_sub_sub_acc_T_7; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size_3 = atomics_a_mask_sizeOH_3[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_3 = ~atomics_a_mask_sub_bit_3; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_3 = atomics_a_mask_sub_sub_0_2_3 & atomics_a_mask_sub_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_12 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_0_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_3 = atomics_a_mask_sub_sub_0_1_3 | _atomics_a_mask_sub_acc_T_12; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_3 = atomics_a_mask_sub_sub_0_2_3 & atomics_a_mask_sub_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_13 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_1_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_3 = atomics_a_mask_sub_sub_0_1_3 | _atomics_a_mask_sub_acc_T_13; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_3 = atomics_a_mask_sub_sub_1_2_3 & atomics_a_mask_sub_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_14 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_2_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_3 = atomics_a_mask_sub_sub_1_1_3 | _atomics_a_mask_sub_acc_T_14; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_3 = atomics_a_mask_sub_sub_1_2_3 & atomics_a_mask_sub_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_15 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_3_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_3 = atomics_a_mask_sub_sub_1_1_3 | _atomics_a_mask_sub_acc_T_15; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_3 = atomics_a_mask_sizeOH_3[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_3 = ~atomics_a_mask_bit_3; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_24 = atomics_a_mask_sub_0_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_24 = atomics_a_mask_size_3 & atomics_a_mask_eq_24; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_24 = atomics_a_mask_sub_0_1_3 | _atomics_a_mask_acc_T_24; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_25 = atomics_a_mask_sub_0_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_25 = atomics_a_mask_size_3 & atomics_a_mask_eq_25; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_25 = atomics_a_mask_sub_0_1_3 | _atomics_a_mask_acc_T_25; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_26 = atomics_a_mask_sub_1_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_26 = atomics_a_mask_size_3 & atomics_a_mask_eq_26; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_26 = atomics_a_mask_sub_1_1_3 | _atomics_a_mask_acc_T_26; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_27 = atomics_a_mask_sub_1_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_27 = atomics_a_mask_size_3 & atomics_a_mask_eq_27; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_27 = atomics_a_mask_sub_1_1_3 | _atomics_a_mask_acc_T_27; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_28 = atomics_a_mask_sub_2_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_28 = atomics_a_mask_size_3 & atomics_a_mask_eq_28; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_28 = atomics_a_mask_sub_2_1_3 | _atomics_a_mask_acc_T_28; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_29 = atomics_a_mask_sub_2_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_29 = atomics_a_mask_size_3 & atomics_a_mask_eq_29; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_29 = atomics_a_mask_sub_2_1_3 | _atomics_a_mask_acc_T_29; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_30 = atomics_a_mask_sub_3_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_30 = atomics_a_mask_size_3 & atomics_a_mask_eq_30; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_30 = atomics_a_mask_sub_3_1_3 | _atomics_a_mask_acc_T_30; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_31 = atomics_a_mask_sub_3_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_31 = atomics_a_mask_size_3 & atomics_a_mask_eq_31; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_31 = atomics_a_mask_sub_3_1_3 | _atomics_a_mask_acc_T_31; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_3 = {atomics_a_mask_acc_25, atomics_a_mask_acc_24}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_3 = {atomics_a_mask_acc_27, atomics_a_mask_acc_26}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_3 = {atomics_a_mask_lo_hi_3, atomics_a_mask_lo_lo_3}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_3 = {atomics_a_mask_acc_29, atomics_a_mask_acc_28}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_3 = {atomics_a_mask_acc_31, atomics_a_mask_acc_30}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_3 = {atomics_a_mask_hi_hi_3, atomics_a_mask_hi_lo_3}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_3 = {atomics_a_mask_hi_3, atomics_a_mask_lo_3}; // @[Misc.scala:222:10] assign atomics_a_3_mask = _atomics_a_mask_T_3; // @[Misc.scala:222:10] wire [34:0] _atomics_legal_T_45 = {1'h0, _atomics_legal_T_44}; // @[Parameters.scala:137:{31,41}] wire [7:0] _atomics_a_mask_T_4; // @[Misc.scala:222:10] wire [7:0] atomics_a_4_mask; // @[Edges.scala:517:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_4 = _atomics_a_mask_sizeOH_T_12[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_13 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_4; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_14 = _atomics_a_mask_sizeOH_T_13[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH_4 = {_atomics_a_mask_sizeOH_T_14[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1_4 = &req_uop_mem_size; // @[Misc.scala:206:21] wire atomics_a_mask_sub_sub_size_4 = atomics_a_mask_sizeOH_4[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2_4 = atomics_a_mask_sub_sub_bit_4; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit_4 = ~atomics_a_mask_sub_sub_bit_4; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_4 = atomics_a_mask_sub_sub_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_8 = atomics_a_mask_sub_sub_size_4 & atomics_a_mask_sub_sub_0_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_4 = atomics_a_mask_sub_sub_sub_0_1_4 | _atomics_a_mask_sub_sub_acc_T_8; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_9 = atomics_a_mask_sub_sub_size_4 & atomics_a_mask_sub_sub_1_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_4 = atomics_a_mask_sub_sub_sub_0_1_4 | _atomics_a_mask_sub_sub_acc_T_9; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size_4 = atomics_a_mask_sizeOH_4[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_4 = ~atomics_a_mask_sub_bit_4; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_4 = atomics_a_mask_sub_sub_0_2_4 & atomics_a_mask_sub_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_16 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_0_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_4 = atomics_a_mask_sub_sub_0_1_4 | _atomics_a_mask_sub_acc_T_16; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_4 = atomics_a_mask_sub_sub_0_2_4 & atomics_a_mask_sub_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_17 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_1_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_4 = atomics_a_mask_sub_sub_0_1_4 | _atomics_a_mask_sub_acc_T_17; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_4 = atomics_a_mask_sub_sub_1_2_4 & atomics_a_mask_sub_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_18 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_2_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_4 = atomics_a_mask_sub_sub_1_1_4 | _atomics_a_mask_sub_acc_T_18; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_4 = atomics_a_mask_sub_sub_1_2_4 & atomics_a_mask_sub_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_19 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_3_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_4 = atomics_a_mask_sub_sub_1_1_4 | _atomics_a_mask_sub_acc_T_19; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_4 = atomics_a_mask_sizeOH_4[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_4 = ~atomics_a_mask_bit_4; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_32 = atomics_a_mask_sub_0_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_32 = atomics_a_mask_size_4 & atomics_a_mask_eq_32; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_32 = atomics_a_mask_sub_0_1_4 | _atomics_a_mask_acc_T_32; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_33 = atomics_a_mask_sub_0_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_33 = atomics_a_mask_size_4 & atomics_a_mask_eq_33; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_33 = atomics_a_mask_sub_0_1_4 | _atomics_a_mask_acc_T_33; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_34 = atomics_a_mask_sub_1_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_34 = atomics_a_mask_size_4 & atomics_a_mask_eq_34; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_34 = atomics_a_mask_sub_1_1_4 | _atomics_a_mask_acc_T_34; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_35 = atomics_a_mask_sub_1_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_35 = atomics_a_mask_size_4 & atomics_a_mask_eq_35; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_35 = atomics_a_mask_sub_1_1_4 | _atomics_a_mask_acc_T_35; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_36 = atomics_a_mask_sub_2_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_36 = atomics_a_mask_size_4 & atomics_a_mask_eq_36; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_36 = atomics_a_mask_sub_2_1_4 | _atomics_a_mask_acc_T_36; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_37 = atomics_a_mask_sub_2_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_37 = atomics_a_mask_size_4 & atomics_a_mask_eq_37; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_37 = atomics_a_mask_sub_2_1_4 | _atomics_a_mask_acc_T_37; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_38 = atomics_a_mask_sub_3_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_38 = atomics_a_mask_size_4 & atomics_a_mask_eq_38; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_38 = atomics_a_mask_sub_3_1_4 | _atomics_a_mask_acc_T_38; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_39 = atomics_a_mask_sub_3_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_39 = atomics_a_mask_size_4 & atomics_a_mask_eq_39; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_39 = atomics_a_mask_sub_3_1_4 | _atomics_a_mask_acc_T_39; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_4 = {atomics_a_mask_acc_33, atomics_a_mask_acc_32}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_4 = {atomics_a_mask_acc_35, atomics_a_mask_acc_34}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_4 = {atomics_a_mask_lo_hi_4, atomics_a_mask_lo_lo_4}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_4 = {atomics_a_mask_acc_37, atomics_a_mask_acc_36}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_4 = {atomics_a_mask_acc_39, atomics_a_mask_acc_38}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_4 = {atomics_a_mask_hi_hi_4, atomics_a_mask_hi_lo_4}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_4 = {atomics_a_mask_hi_4, atomics_a_mask_lo_4}; // @[Misc.scala:222:10] assign atomics_a_4_mask = _atomics_a_mask_T_4; // @[Misc.scala:222:10] wire [34:0] _atomics_legal_T_55 = {1'h0, _atomics_legal_T_54}; // @[Parameters.scala:137:{31,41}] wire [7:0] _atomics_a_mask_T_5; // @[Misc.scala:222:10] wire [7:0] atomics_a_5_mask; // @[Edges.scala:517:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_5 = _atomics_a_mask_sizeOH_T_15[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_16 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_5; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_17 = _atomics_a_mask_sizeOH_T_16[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH_5 = {_atomics_a_mask_sizeOH_T_17[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1_5 = &req_uop_mem_size; // @[Misc.scala:206:21] wire atomics_a_mask_sub_sub_size_5 = atomics_a_mask_sizeOH_5[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2_5 = atomics_a_mask_sub_sub_bit_5; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit_5 = ~atomics_a_mask_sub_sub_bit_5; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_5 = atomics_a_mask_sub_sub_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_10 = atomics_a_mask_sub_sub_size_5 & atomics_a_mask_sub_sub_0_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_5 = atomics_a_mask_sub_sub_sub_0_1_5 | _atomics_a_mask_sub_sub_acc_T_10; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_11 = atomics_a_mask_sub_sub_size_5 & atomics_a_mask_sub_sub_1_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_5 = atomics_a_mask_sub_sub_sub_0_1_5 | _atomics_a_mask_sub_sub_acc_T_11; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size_5 = atomics_a_mask_sizeOH_5[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_5 = ~atomics_a_mask_sub_bit_5; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_5 = atomics_a_mask_sub_sub_0_2_5 & atomics_a_mask_sub_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_20 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_0_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_5 = atomics_a_mask_sub_sub_0_1_5 | _atomics_a_mask_sub_acc_T_20; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_5 = atomics_a_mask_sub_sub_0_2_5 & atomics_a_mask_sub_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_21 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_1_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_5 = atomics_a_mask_sub_sub_0_1_5 | _atomics_a_mask_sub_acc_T_21; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_5 = atomics_a_mask_sub_sub_1_2_5 & atomics_a_mask_sub_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_22 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_2_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_5 = atomics_a_mask_sub_sub_1_1_5 | _atomics_a_mask_sub_acc_T_22; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_5 = atomics_a_mask_sub_sub_1_2_5 & atomics_a_mask_sub_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_23 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_3_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_5 = atomics_a_mask_sub_sub_1_1_5 | _atomics_a_mask_sub_acc_T_23; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_5 = atomics_a_mask_sizeOH_5[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_5 = ~atomics_a_mask_bit_5; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_40 = atomics_a_mask_sub_0_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_40 = atomics_a_mask_size_5 & atomics_a_mask_eq_40; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_40 = atomics_a_mask_sub_0_1_5 | _atomics_a_mask_acc_T_40; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_41 = atomics_a_mask_sub_0_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_41 = atomics_a_mask_size_5 & atomics_a_mask_eq_41; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_41 = atomics_a_mask_sub_0_1_5 | _atomics_a_mask_acc_T_41; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_42 = atomics_a_mask_sub_1_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_42 = atomics_a_mask_size_5 & atomics_a_mask_eq_42; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_42 = atomics_a_mask_sub_1_1_5 | _atomics_a_mask_acc_T_42; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_43 = atomics_a_mask_sub_1_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_43 = atomics_a_mask_size_5 & atomics_a_mask_eq_43; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_43 = atomics_a_mask_sub_1_1_5 | _atomics_a_mask_acc_T_43; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_44 = atomics_a_mask_sub_2_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_44 = atomics_a_mask_size_5 & atomics_a_mask_eq_44; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_44 = atomics_a_mask_sub_2_1_5 | _atomics_a_mask_acc_T_44; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_45 = atomics_a_mask_sub_2_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_45 = atomics_a_mask_size_5 & atomics_a_mask_eq_45; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_45 = atomics_a_mask_sub_2_1_5 | _atomics_a_mask_acc_T_45; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_46 = atomics_a_mask_sub_3_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_46 = atomics_a_mask_size_5 & atomics_a_mask_eq_46; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_46 = atomics_a_mask_sub_3_1_5 | _atomics_a_mask_acc_T_46; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_47 = atomics_a_mask_sub_3_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_47 = atomics_a_mask_size_5 & atomics_a_mask_eq_47; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_47 = atomics_a_mask_sub_3_1_5 | _atomics_a_mask_acc_T_47; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_5 = {atomics_a_mask_acc_41, atomics_a_mask_acc_40}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_5 = {atomics_a_mask_acc_43, atomics_a_mask_acc_42}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_5 = {atomics_a_mask_lo_hi_5, atomics_a_mask_lo_lo_5}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_5 = {atomics_a_mask_acc_45, atomics_a_mask_acc_44}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_5 = {atomics_a_mask_acc_47, atomics_a_mask_acc_46}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_5 = {atomics_a_mask_hi_hi_5, atomics_a_mask_hi_lo_5}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_5 = {atomics_a_mask_hi_5, atomics_a_mask_lo_5}; // @[Misc.scala:222:10] assign atomics_a_5_mask = _atomics_a_mask_T_5; // @[Misc.scala:222:10] wire [34:0] _atomics_legal_T_65 = {1'h0, _atomics_legal_T_64}; // @[Parameters.scala:137:{31,41}] wire [7:0] _atomics_a_mask_T_6; // @[Misc.scala:222:10] wire [7:0] atomics_a_6_mask; // @[Edges.scala:517:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_6 = _atomics_a_mask_sizeOH_T_18[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_19 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_6; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_20 = _atomics_a_mask_sizeOH_T_19[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH_6 = {_atomics_a_mask_sizeOH_T_20[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1_6 = &req_uop_mem_size; // @[Misc.scala:206:21] wire atomics_a_mask_sub_sub_size_6 = atomics_a_mask_sizeOH_6[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2_6 = atomics_a_mask_sub_sub_bit_6; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit_6 = ~atomics_a_mask_sub_sub_bit_6; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_6 = atomics_a_mask_sub_sub_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_12 = atomics_a_mask_sub_sub_size_6 & atomics_a_mask_sub_sub_0_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_6 = atomics_a_mask_sub_sub_sub_0_1_6 | _atomics_a_mask_sub_sub_acc_T_12; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_13 = atomics_a_mask_sub_sub_size_6 & atomics_a_mask_sub_sub_1_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_6 = atomics_a_mask_sub_sub_sub_0_1_6 | _atomics_a_mask_sub_sub_acc_T_13; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size_6 = atomics_a_mask_sizeOH_6[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_6 = ~atomics_a_mask_sub_bit_6; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_6 = atomics_a_mask_sub_sub_0_2_6 & atomics_a_mask_sub_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_24 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_0_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_6 = atomics_a_mask_sub_sub_0_1_6 | _atomics_a_mask_sub_acc_T_24; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_6 = atomics_a_mask_sub_sub_0_2_6 & atomics_a_mask_sub_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_25 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_1_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_6 = atomics_a_mask_sub_sub_0_1_6 | _atomics_a_mask_sub_acc_T_25; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_6 = atomics_a_mask_sub_sub_1_2_6 & atomics_a_mask_sub_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_26 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_2_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_6 = atomics_a_mask_sub_sub_1_1_6 | _atomics_a_mask_sub_acc_T_26; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_6 = atomics_a_mask_sub_sub_1_2_6 & atomics_a_mask_sub_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_27 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_3_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_6 = atomics_a_mask_sub_sub_1_1_6 | _atomics_a_mask_sub_acc_T_27; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_6 = atomics_a_mask_sizeOH_6[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_6 = ~atomics_a_mask_bit_6; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_48 = atomics_a_mask_sub_0_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_48 = atomics_a_mask_size_6 & atomics_a_mask_eq_48; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_48 = atomics_a_mask_sub_0_1_6 | _atomics_a_mask_acc_T_48; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_49 = atomics_a_mask_sub_0_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_49 = atomics_a_mask_size_6 & atomics_a_mask_eq_49; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_49 = atomics_a_mask_sub_0_1_6 | _atomics_a_mask_acc_T_49; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_50 = atomics_a_mask_sub_1_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_50 = atomics_a_mask_size_6 & atomics_a_mask_eq_50; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_50 = atomics_a_mask_sub_1_1_6 | _atomics_a_mask_acc_T_50; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_51 = atomics_a_mask_sub_1_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_51 = atomics_a_mask_size_6 & atomics_a_mask_eq_51; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_51 = atomics_a_mask_sub_1_1_6 | _atomics_a_mask_acc_T_51; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_52 = atomics_a_mask_sub_2_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_52 = atomics_a_mask_size_6 & atomics_a_mask_eq_52; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_52 = atomics_a_mask_sub_2_1_6 | _atomics_a_mask_acc_T_52; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_53 = atomics_a_mask_sub_2_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_53 = atomics_a_mask_size_6 & atomics_a_mask_eq_53; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_53 = atomics_a_mask_sub_2_1_6 | _atomics_a_mask_acc_T_53; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_54 = atomics_a_mask_sub_3_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_54 = atomics_a_mask_size_6 & atomics_a_mask_eq_54; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_54 = atomics_a_mask_sub_3_1_6 | _atomics_a_mask_acc_T_54; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_55 = atomics_a_mask_sub_3_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_55 = atomics_a_mask_size_6 & atomics_a_mask_eq_55; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_55 = atomics_a_mask_sub_3_1_6 | _atomics_a_mask_acc_T_55; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_6 = {atomics_a_mask_acc_49, atomics_a_mask_acc_48}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_6 = {atomics_a_mask_acc_51, atomics_a_mask_acc_50}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_6 = {atomics_a_mask_lo_hi_6, atomics_a_mask_lo_lo_6}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_6 = {atomics_a_mask_acc_53, atomics_a_mask_acc_52}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_6 = {atomics_a_mask_acc_55, atomics_a_mask_acc_54}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_6 = {atomics_a_mask_hi_hi_6, atomics_a_mask_hi_lo_6}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_6 = {atomics_a_mask_hi_6, atomics_a_mask_lo_6}; // @[Misc.scala:222:10] assign atomics_a_6_mask = _atomics_a_mask_T_6; // @[Misc.scala:222:10] wire [34:0] _atomics_legal_T_75 = {1'h0, _atomics_legal_T_74}; // @[Parameters.scala:137:{31,41}] wire [7:0] _atomics_a_mask_T_7; // @[Misc.scala:222:10] wire [7:0] atomics_a_7_mask; // @[Edges.scala:517:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_7 = _atomics_a_mask_sizeOH_T_21[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_22 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_7; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_23 = _atomics_a_mask_sizeOH_T_22[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH_7 = {_atomics_a_mask_sizeOH_T_23[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1_7 = &req_uop_mem_size; // @[Misc.scala:206:21] wire atomics_a_mask_sub_sub_size_7 = atomics_a_mask_sizeOH_7[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2_7 = atomics_a_mask_sub_sub_bit_7; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit_7 = ~atomics_a_mask_sub_sub_bit_7; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_7 = atomics_a_mask_sub_sub_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_14 = atomics_a_mask_sub_sub_size_7 & atomics_a_mask_sub_sub_0_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_7 = atomics_a_mask_sub_sub_sub_0_1_7 | _atomics_a_mask_sub_sub_acc_T_14; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_15 = atomics_a_mask_sub_sub_size_7 & atomics_a_mask_sub_sub_1_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_7 = atomics_a_mask_sub_sub_sub_0_1_7 | _atomics_a_mask_sub_sub_acc_T_15; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size_7 = atomics_a_mask_sizeOH_7[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_7 = ~atomics_a_mask_sub_bit_7; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_7 = atomics_a_mask_sub_sub_0_2_7 & atomics_a_mask_sub_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_28 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_0_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_7 = atomics_a_mask_sub_sub_0_1_7 | _atomics_a_mask_sub_acc_T_28; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_7 = atomics_a_mask_sub_sub_0_2_7 & atomics_a_mask_sub_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_29 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_1_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_7 = atomics_a_mask_sub_sub_0_1_7 | _atomics_a_mask_sub_acc_T_29; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_7 = atomics_a_mask_sub_sub_1_2_7 & atomics_a_mask_sub_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_30 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_2_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_7 = atomics_a_mask_sub_sub_1_1_7 | _atomics_a_mask_sub_acc_T_30; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_7 = atomics_a_mask_sub_sub_1_2_7 & atomics_a_mask_sub_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_31 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_3_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_7 = atomics_a_mask_sub_sub_1_1_7 | _atomics_a_mask_sub_acc_T_31; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_7 = atomics_a_mask_sizeOH_7[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_7 = ~atomics_a_mask_bit_7; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_56 = atomics_a_mask_sub_0_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_56 = atomics_a_mask_size_7 & atomics_a_mask_eq_56; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_56 = atomics_a_mask_sub_0_1_7 | _atomics_a_mask_acc_T_56; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_57 = atomics_a_mask_sub_0_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_57 = atomics_a_mask_size_7 & atomics_a_mask_eq_57; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_57 = atomics_a_mask_sub_0_1_7 | _atomics_a_mask_acc_T_57; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_58 = atomics_a_mask_sub_1_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_58 = atomics_a_mask_size_7 & atomics_a_mask_eq_58; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_58 = atomics_a_mask_sub_1_1_7 | _atomics_a_mask_acc_T_58; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_59 = atomics_a_mask_sub_1_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_59 = atomics_a_mask_size_7 & atomics_a_mask_eq_59; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_59 = atomics_a_mask_sub_1_1_7 | _atomics_a_mask_acc_T_59; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_60 = atomics_a_mask_sub_2_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_60 = atomics_a_mask_size_7 & atomics_a_mask_eq_60; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_60 = atomics_a_mask_sub_2_1_7 | _atomics_a_mask_acc_T_60; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_61 = atomics_a_mask_sub_2_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_61 = atomics_a_mask_size_7 & atomics_a_mask_eq_61; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_61 = atomics_a_mask_sub_2_1_7 | _atomics_a_mask_acc_T_61; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_62 = atomics_a_mask_sub_3_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_62 = atomics_a_mask_size_7 & atomics_a_mask_eq_62; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_62 = atomics_a_mask_sub_3_1_7 | _atomics_a_mask_acc_T_62; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_63 = atomics_a_mask_sub_3_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_63 = atomics_a_mask_size_7 & atomics_a_mask_eq_63; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_63 = atomics_a_mask_sub_3_1_7 | _atomics_a_mask_acc_T_63; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_7 = {atomics_a_mask_acc_57, atomics_a_mask_acc_56}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_7 = {atomics_a_mask_acc_59, atomics_a_mask_acc_58}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_7 = {atomics_a_mask_lo_hi_7, atomics_a_mask_lo_lo_7}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_7 = {atomics_a_mask_acc_61, atomics_a_mask_acc_60}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_7 = {atomics_a_mask_acc_63, atomics_a_mask_acc_62}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_7 = {atomics_a_mask_hi_hi_7, atomics_a_mask_hi_lo_7}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_7 = {atomics_a_mask_hi_7, atomics_a_mask_lo_7}; // @[Misc.scala:222:10] assign atomics_a_7_mask = _atomics_a_mask_T_7; // @[Misc.scala:222:10] wire [34:0] _atomics_legal_T_85 = {1'h0, _atomics_legal_T_84}; // @[Parameters.scala:137:{31,41}] wire [7:0] _atomics_a_mask_T_8; // @[Misc.scala:222:10] wire [7:0] atomics_a_8_mask; // @[Edges.scala:517:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_8 = _atomics_a_mask_sizeOH_T_24[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_25 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_8; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_26 = _atomics_a_mask_sizeOH_T_25[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH_8 = {_atomics_a_mask_sizeOH_T_26[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1_8 = &req_uop_mem_size; // @[Misc.scala:206:21] wire atomics_a_mask_sub_sub_size_8 = atomics_a_mask_sizeOH_8[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2_8 = atomics_a_mask_sub_sub_bit_8; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit_8 = ~atomics_a_mask_sub_sub_bit_8; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_8 = atomics_a_mask_sub_sub_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_16 = atomics_a_mask_sub_sub_size_8 & atomics_a_mask_sub_sub_0_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_8 = atomics_a_mask_sub_sub_sub_0_1_8 | _atomics_a_mask_sub_sub_acc_T_16; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_17 = atomics_a_mask_sub_sub_size_8 & atomics_a_mask_sub_sub_1_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_8 = atomics_a_mask_sub_sub_sub_0_1_8 | _atomics_a_mask_sub_sub_acc_T_17; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size_8 = atomics_a_mask_sizeOH_8[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_8 = ~atomics_a_mask_sub_bit_8; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_8 = atomics_a_mask_sub_sub_0_2_8 & atomics_a_mask_sub_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_32 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_0_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_8 = atomics_a_mask_sub_sub_0_1_8 | _atomics_a_mask_sub_acc_T_32; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_8 = atomics_a_mask_sub_sub_0_2_8 & atomics_a_mask_sub_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_33 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_1_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_8 = atomics_a_mask_sub_sub_0_1_8 | _atomics_a_mask_sub_acc_T_33; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_8 = atomics_a_mask_sub_sub_1_2_8 & atomics_a_mask_sub_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_34 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_2_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_8 = atomics_a_mask_sub_sub_1_1_8 | _atomics_a_mask_sub_acc_T_34; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_8 = atomics_a_mask_sub_sub_1_2_8 & atomics_a_mask_sub_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_35 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_3_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_8 = atomics_a_mask_sub_sub_1_1_8 | _atomics_a_mask_sub_acc_T_35; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_8 = atomics_a_mask_sizeOH_8[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_8 = ~atomics_a_mask_bit_8; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_64 = atomics_a_mask_sub_0_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_64 = atomics_a_mask_size_8 & atomics_a_mask_eq_64; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_64 = atomics_a_mask_sub_0_1_8 | _atomics_a_mask_acc_T_64; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_65 = atomics_a_mask_sub_0_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_65 = atomics_a_mask_size_8 & atomics_a_mask_eq_65; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_65 = atomics_a_mask_sub_0_1_8 | _atomics_a_mask_acc_T_65; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_66 = atomics_a_mask_sub_1_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_66 = atomics_a_mask_size_8 & atomics_a_mask_eq_66; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_66 = atomics_a_mask_sub_1_1_8 | _atomics_a_mask_acc_T_66; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_67 = atomics_a_mask_sub_1_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_67 = atomics_a_mask_size_8 & atomics_a_mask_eq_67; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_67 = atomics_a_mask_sub_1_1_8 | _atomics_a_mask_acc_T_67; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_68 = atomics_a_mask_sub_2_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_68 = atomics_a_mask_size_8 & atomics_a_mask_eq_68; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_68 = atomics_a_mask_sub_2_1_8 | _atomics_a_mask_acc_T_68; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_69 = atomics_a_mask_sub_2_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_69 = atomics_a_mask_size_8 & atomics_a_mask_eq_69; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_69 = atomics_a_mask_sub_2_1_8 | _atomics_a_mask_acc_T_69; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_70 = atomics_a_mask_sub_3_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_70 = atomics_a_mask_size_8 & atomics_a_mask_eq_70; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_70 = atomics_a_mask_sub_3_1_8 | _atomics_a_mask_acc_T_70; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_71 = atomics_a_mask_sub_3_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_71 = atomics_a_mask_size_8 & atomics_a_mask_eq_71; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_71 = atomics_a_mask_sub_3_1_8 | _atomics_a_mask_acc_T_71; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_8 = {atomics_a_mask_acc_65, atomics_a_mask_acc_64}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_8 = {atomics_a_mask_acc_67, atomics_a_mask_acc_66}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_8 = {atomics_a_mask_lo_hi_8, atomics_a_mask_lo_lo_8}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_8 = {atomics_a_mask_acc_69, atomics_a_mask_acc_68}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_8 = {atomics_a_mask_acc_71, atomics_a_mask_acc_70}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_8 = {atomics_a_mask_hi_hi_8, atomics_a_mask_hi_lo_8}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_8 = {atomics_a_mask_hi_8, atomics_a_mask_lo_8}; // @[Misc.scala:222:10] assign atomics_a_8_mask = _atomics_a_mask_T_8; // @[Misc.scala:222:10] wire _T_17 = req_uop_mem_cmd == 5'h4; // @[mshrs.scala:421:16, :439:75] wire _atomics_T; // @[mshrs.scala:439:75] assign _atomics_T = _T_17; // @[mshrs.scala:439:75] wire _io_mem_access_bits_T; // @[package.scala:16:47] assign _io_mem_access_bits_T = _T_17; // @[package.scala:16:47] wire _io_mem_access_bits_T_24; // @[package.scala:16:47] assign _io_mem_access_bits_T_24 = _T_17; // @[package.scala:16:47] wire _send_resp_T_7; // @[package.scala:16:47] assign _send_resp_T_7 = _T_17; // @[package.scala:16:47] wire [2:0] _GEN_4 = _atomics_T ? 3'h3 : 3'h0; // @[mshrs.scala:439:75] wire [2:0] _atomics_T_1_opcode; // @[mshrs.scala:439:75] assign _atomics_T_1_opcode = _GEN_4; // @[mshrs.scala:439:75] wire [2:0] _atomics_T_1_param; // @[mshrs.scala:439:75] assign _atomics_T_1_param = _GEN_4; // @[mshrs.scala:439:75] wire [3:0] _atomics_T_1_size = _atomics_T ? atomics_a_size : 4'h0; // @[Edges.scala:534:17] wire [3:0] _atomics_T_1_source = _atomics_T ? 4'h9 : 4'h0; // @[mshrs.scala:439:75] wire [31:0] _atomics_T_1_address = _atomics_T ? atomics_a_address : 32'h0; // @[Edges.scala:534:17] wire [7:0] _atomics_T_1_mask = _atomics_T ? atomics_a_mask : 8'h0; // @[Edges.scala:534:17] wire [63:0] _atomics_T_1_data = _atomics_T ? atomics_a_data : 64'h0; // @[Edges.scala:534:17] wire _T_18 = req_uop_mem_cmd == 5'h9; // @[mshrs.scala:421:16, :439:75] wire _atomics_T_2; // @[mshrs.scala:439:75] assign _atomics_T_2 = _T_18; // @[mshrs.scala:439:75] wire _io_mem_access_bits_T_1; // @[package.scala:16:47] assign _io_mem_access_bits_T_1 = _T_18; // @[package.scala:16:47] wire _io_mem_access_bits_T_25; // @[package.scala:16:47] assign _io_mem_access_bits_T_25 = _T_18; // @[package.scala:16:47] wire _send_resp_T_8; // @[package.scala:16:47] assign _send_resp_T_8 = _T_18; // @[package.scala:16:47] wire [2:0] _atomics_T_3_opcode = _atomics_T_2 ? 3'h3 : _atomics_T_1_opcode; // @[mshrs.scala:439:75] wire [2:0] _atomics_T_3_param = _atomics_T_2 ? 3'h0 : _atomics_T_1_param; // @[mshrs.scala:439:75] wire [3:0] _atomics_T_3_size = _atomics_T_2 ? atomics_a_1_size : _atomics_T_1_size; // @[Edges.scala:534:17] wire [3:0] _atomics_T_3_source = _atomics_T_2 ? 4'h9 : _atomics_T_1_source; // @[mshrs.scala:439:75] wire [31:0] _atomics_T_3_address = _atomics_T_2 ? atomics_a_1_address : _atomics_T_1_address; // @[Edges.scala:534:17] wire [7:0] _atomics_T_3_mask = _atomics_T_2 ? atomics_a_1_mask : _atomics_T_1_mask; // @[Edges.scala:534:17] wire [63:0] _atomics_T_3_data = _atomics_T_2 ? atomics_a_1_data : _atomics_T_1_data; // @[Edges.scala:534:17] wire _T_19 = req_uop_mem_cmd == 5'hA; // @[mshrs.scala:421:16, :439:75] wire _atomics_T_4; // @[mshrs.scala:439:75] assign _atomics_T_4 = _T_19; // @[mshrs.scala:439:75] wire _io_mem_access_bits_T_2; // @[package.scala:16:47] assign _io_mem_access_bits_T_2 = _T_19; // @[package.scala:16:47] wire _io_mem_access_bits_T_26; // @[package.scala:16:47] assign _io_mem_access_bits_T_26 = _T_19; // @[package.scala:16:47] wire _send_resp_T_9; // @[package.scala:16:47] assign _send_resp_T_9 = _T_19; // @[package.scala:16:47] wire [2:0] _atomics_T_5_opcode = _atomics_T_4 ? 3'h3 : _atomics_T_3_opcode; // @[mshrs.scala:439:75] wire [2:0] _atomics_T_5_param = _atomics_T_4 ? 3'h1 : _atomics_T_3_param; // @[mshrs.scala:439:75] wire [3:0] _atomics_T_5_size = _atomics_T_4 ? atomics_a_2_size : _atomics_T_3_size; // @[Edges.scala:534:17] wire [3:0] _atomics_T_5_source = _atomics_T_4 ? 4'h9 : _atomics_T_3_source; // @[mshrs.scala:439:75] wire [31:0] _atomics_T_5_address = _atomics_T_4 ? atomics_a_2_address : _atomics_T_3_address; // @[Edges.scala:534:17] wire [7:0] _atomics_T_5_mask = _atomics_T_4 ? atomics_a_2_mask : _atomics_T_3_mask; // @[Edges.scala:534:17] wire [63:0] _atomics_T_5_data = _atomics_T_4 ? atomics_a_2_data : _atomics_T_3_data; // @[Edges.scala:534:17] wire _T_20 = req_uop_mem_cmd == 5'hB; // @[mshrs.scala:421:16, :439:75] wire _atomics_T_6; // @[mshrs.scala:439:75] assign _atomics_T_6 = _T_20; // @[mshrs.scala:439:75] wire _io_mem_access_bits_T_3; // @[package.scala:16:47] assign _io_mem_access_bits_T_3 = _T_20; // @[package.scala:16:47] wire _io_mem_access_bits_T_27; // @[package.scala:16:47] assign _io_mem_access_bits_T_27 = _T_20; // @[package.scala:16:47] wire _send_resp_T_10; // @[package.scala:16:47] assign _send_resp_T_10 = _T_20; // @[package.scala:16:47] wire [2:0] _atomics_T_7_opcode = _atomics_T_6 ? 3'h3 : _atomics_T_5_opcode; // @[mshrs.scala:439:75] wire [2:0] _atomics_T_7_param = _atomics_T_6 ? 3'h2 : _atomics_T_5_param; // @[mshrs.scala:439:75] wire [3:0] _atomics_T_7_size = _atomics_T_6 ? atomics_a_3_size : _atomics_T_5_size; // @[Edges.scala:534:17] wire [3:0] _atomics_T_7_source = _atomics_T_6 ? 4'h9 : _atomics_T_5_source; // @[mshrs.scala:439:75] wire [31:0] _atomics_T_7_address = _atomics_T_6 ? atomics_a_3_address : _atomics_T_5_address; // @[Edges.scala:534:17] wire [7:0] _atomics_T_7_mask = _atomics_T_6 ? atomics_a_3_mask : _atomics_T_5_mask; // @[Edges.scala:534:17] wire [63:0] _atomics_T_7_data = _atomics_T_6 ? atomics_a_3_data : _atomics_T_5_data; // @[Edges.scala:534:17] wire _T_24 = req_uop_mem_cmd == 5'h8; // @[mshrs.scala:421:16, :439:75] wire _atomics_T_8; // @[mshrs.scala:439:75] assign _atomics_T_8 = _T_24; // @[mshrs.scala:439:75] wire _io_mem_access_bits_T_7; // @[package.scala:16:47] assign _io_mem_access_bits_T_7 = _T_24; // @[package.scala:16:47] wire _io_mem_access_bits_T_31; // @[package.scala:16:47] assign _io_mem_access_bits_T_31 = _T_24; // @[package.scala:16:47] wire _send_resp_T_14; // @[package.scala:16:47] assign _send_resp_T_14 = _T_24; // @[package.scala:16:47] wire [2:0] _atomics_T_9_opcode = _atomics_T_8 ? 3'h2 : _atomics_T_7_opcode; // @[mshrs.scala:439:75] wire [2:0] _atomics_T_9_param = _atomics_T_8 ? 3'h4 : _atomics_T_7_param; // @[mshrs.scala:439:75] wire [3:0] _atomics_T_9_size = _atomics_T_8 ? atomics_a_4_size : _atomics_T_7_size; // @[Edges.scala:517:17] wire [3:0] _atomics_T_9_source = _atomics_T_8 ? 4'h9 : _atomics_T_7_source; // @[mshrs.scala:439:75] wire [31:0] _atomics_T_9_address = _atomics_T_8 ? atomics_a_4_address : _atomics_T_7_address; // @[Edges.scala:517:17] wire [7:0] _atomics_T_9_mask = _atomics_T_8 ? atomics_a_4_mask : _atomics_T_7_mask; // @[Edges.scala:517:17] wire [63:0] _atomics_T_9_data = _atomics_T_8 ? atomics_a_4_data : _atomics_T_7_data; // @[Edges.scala:517:17] wire _T_25 = req_uop_mem_cmd == 5'hC; // @[mshrs.scala:421:16, :439:75] wire _atomics_T_10; // @[mshrs.scala:439:75] assign _atomics_T_10 = _T_25; // @[mshrs.scala:439:75] wire _io_mem_access_bits_T_8; // @[package.scala:16:47] assign _io_mem_access_bits_T_8 = _T_25; // @[package.scala:16:47] wire _io_mem_access_bits_T_32; // @[package.scala:16:47] assign _io_mem_access_bits_T_32 = _T_25; // @[package.scala:16:47] wire _send_resp_T_15; // @[package.scala:16:47] assign _send_resp_T_15 = _T_25; // @[package.scala:16:47] wire [2:0] _atomics_T_11_opcode = _atomics_T_10 ? 3'h2 : _atomics_T_9_opcode; // @[mshrs.scala:439:75] wire [2:0] _atomics_T_11_param = _atomics_T_10 ? 3'h0 : _atomics_T_9_param; // @[mshrs.scala:439:75] wire [3:0] _atomics_T_11_size = _atomics_T_10 ? atomics_a_5_size : _atomics_T_9_size; // @[Edges.scala:517:17] wire [3:0] _atomics_T_11_source = _atomics_T_10 ? 4'h9 : _atomics_T_9_source; // @[mshrs.scala:439:75] wire [31:0] _atomics_T_11_address = _atomics_T_10 ? atomics_a_5_address : _atomics_T_9_address; // @[Edges.scala:517:17] wire [7:0] _atomics_T_11_mask = _atomics_T_10 ? atomics_a_5_mask : _atomics_T_9_mask; // @[Edges.scala:517:17] wire [63:0] _atomics_T_11_data = _atomics_T_10 ? atomics_a_5_data : _atomics_T_9_data; // @[Edges.scala:517:17] wire _T_26 = req_uop_mem_cmd == 5'hD; // @[mshrs.scala:421:16, :439:75] wire _atomics_T_12; // @[mshrs.scala:439:75] assign _atomics_T_12 = _T_26; // @[mshrs.scala:439:75] wire _io_mem_access_bits_T_9; // @[package.scala:16:47] assign _io_mem_access_bits_T_9 = _T_26; // @[package.scala:16:47] wire _io_mem_access_bits_T_33; // @[package.scala:16:47] assign _io_mem_access_bits_T_33 = _T_26; // @[package.scala:16:47] wire _send_resp_T_16; // @[package.scala:16:47] assign _send_resp_T_16 = _T_26; // @[package.scala:16:47] wire [2:0] _atomics_T_13_opcode = _atomics_T_12 ? 3'h2 : _atomics_T_11_opcode; // @[mshrs.scala:439:75] wire [2:0] _atomics_T_13_param = _atomics_T_12 ? 3'h1 : _atomics_T_11_param; // @[mshrs.scala:439:75] wire [3:0] _atomics_T_13_size = _atomics_T_12 ? atomics_a_6_size : _atomics_T_11_size; // @[Edges.scala:517:17] wire [3:0] _atomics_T_13_source = _atomics_T_12 ? 4'h9 : _atomics_T_11_source; // @[mshrs.scala:439:75] wire [31:0] _atomics_T_13_address = _atomics_T_12 ? atomics_a_6_address : _atomics_T_11_address; // @[Edges.scala:517:17] wire [7:0] _atomics_T_13_mask = _atomics_T_12 ? atomics_a_6_mask : _atomics_T_11_mask; // @[Edges.scala:517:17] wire [63:0] _atomics_T_13_data = _atomics_T_12 ? atomics_a_6_data : _atomics_T_11_data; // @[Edges.scala:517:17] wire _T_27 = req_uop_mem_cmd == 5'hE; // @[mshrs.scala:421:16, :439:75] wire _atomics_T_14; // @[mshrs.scala:439:75] assign _atomics_T_14 = _T_27; // @[mshrs.scala:439:75] wire _io_mem_access_bits_T_10; // @[package.scala:16:47] assign _io_mem_access_bits_T_10 = _T_27; // @[package.scala:16:47] wire _io_mem_access_bits_T_34; // @[package.scala:16:47] assign _io_mem_access_bits_T_34 = _T_27; // @[package.scala:16:47] wire _send_resp_T_17; // @[package.scala:16:47] assign _send_resp_T_17 = _T_27; // @[package.scala:16:47] wire [2:0] _atomics_T_15_opcode = _atomics_T_14 ? 3'h2 : _atomics_T_13_opcode; // @[mshrs.scala:439:75] wire [2:0] _atomics_T_15_param = _atomics_T_14 ? 3'h2 : _atomics_T_13_param; // @[mshrs.scala:439:75] wire [3:0] _atomics_T_15_size = _atomics_T_14 ? atomics_a_7_size : _atomics_T_13_size; // @[Edges.scala:517:17] wire [3:0] _atomics_T_15_source = _atomics_T_14 ? 4'h9 : _atomics_T_13_source; // @[mshrs.scala:439:75] wire [31:0] _atomics_T_15_address = _atomics_T_14 ? atomics_a_7_address : _atomics_T_13_address; // @[Edges.scala:517:17] wire [7:0] _atomics_T_15_mask = _atomics_T_14 ? atomics_a_7_mask : _atomics_T_13_mask; // @[Edges.scala:517:17] wire [63:0] _atomics_T_15_data = _atomics_T_14 ? atomics_a_7_data : _atomics_T_13_data; // @[Edges.scala:517:17] wire _T_28 = req_uop_mem_cmd == 5'hF; // @[mshrs.scala:421:16, :439:75] wire _atomics_T_16; // @[mshrs.scala:439:75] assign _atomics_T_16 = _T_28; // @[mshrs.scala:439:75] wire _io_mem_access_bits_T_11; // @[package.scala:16:47] assign _io_mem_access_bits_T_11 = _T_28; // @[package.scala:16:47] wire _io_mem_access_bits_T_35; // @[package.scala:16:47] assign _io_mem_access_bits_T_35 = _T_28; // @[package.scala:16:47] wire _send_resp_T_18; // @[package.scala:16:47] assign _send_resp_T_18 = _T_28; // @[package.scala:16:47] wire [2:0] atomics_opcode = _atomics_T_16 ? 3'h2 : _atomics_T_15_opcode; // @[mshrs.scala:439:75] wire [2:0] atomics_param = _atomics_T_16 ? 3'h3 : _atomics_T_15_param; // @[mshrs.scala:439:75] wire [3:0] atomics_size = _atomics_T_16 ? atomics_a_8_size : _atomics_T_15_size; // @[Edges.scala:517:17] wire [3:0] atomics_source = _atomics_T_16 ? 4'h9 : _atomics_T_15_source; // @[mshrs.scala:439:75] wire [31:0] atomics_address = _atomics_T_16 ? atomics_a_8_address : _atomics_T_15_address; // @[Edges.scala:517:17] wire [7:0] atomics_mask = _atomics_T_16 ? atomics_a_8_mask : _atomics_T_15_mask; // @[Edges.scala:517:17] wire [63:0] atomics_data = _atomics_T_16 ? atomics_a_8_data : _atomics_T_15_data; // @[Edges.scala:517:17]

Generate the Verilog code corresponding to the following Chisel files. File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File CacheCork.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{IdRange, RegionType, TransferSizes} import freechips.rocketchip.tilelink.TLMessages.{ AcquireBlock, AcquirePerm, Get, PutFullData, PutPartialData, Release, ReleaseData, Grant, GrantData, AccessAck, AccessAckData, ReleaseAck } import freechips.rocketchip.util.IDPool import freechips.rocketchip.util.DataToAugmentedData case class TLCacheCorkParams( unsafe: Boolean = false, sinkIds: Int = 8) class TLCacheCork(params: TLCacheCorkParams = TLCacheCorkParams())(implicit p: Parameters) extends LazyModule { val unsafe = params.unsafe val sinkIds = params.sinkIds val node = TLAdapterNode( clientFn = { case cp => cp.v1copy(clients = cp.clients.map { c => c.v1copy( supportsProbe = TransferSizes.none, sourceId = IdRange(c.sourceId.start*2, c.sourceId.end*2))})}, managerFn = { case mp => mp.v1copy( endSinkId = if (mp.managers.exists(_.regionType == RegionType.UNCACHED)) sinkIds else 0, managers = mp.managers.map { m => m.v1copy( supportsAcquireB = if (m.regionType == RegionType.UNCACHED) m.supportsGet else m.supportsAcquireB, supportsAcquireT = if (m.regionType == RegionType.UNCACHED) m.supportsPutFull.intersect(m.supportsGet) else m.supportsAcquireT, alwaysGrantsT = if (m.regionType == RegionType.UNCACHED) m.supportsPutFull else m.alwaysGrantsT)})}) lazy val module = new Impl class Impl extends LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => // If this adapter does not need to do anything, toss all the above work and just directly connect if (!edgeIn.manager.anySupportAcquireB) { out <> in } else { val clients = edgeIn.client.clients val caches = clients.filter(_.supports.probe) require (clients.size == 1 || caches.size == 0 || unsafe, s"Only one client can safely use a TLCacheCork; ${clients.map(_.name)}") require (caches.size <= 1 || unsafe, s"Only one caching client allowed; ${clients.map(_.name)}") edgeOut.manager.managers.foreach { case m => require (!m.supportsAcquireB || unsafe, s"Cannot support caches beyond the Cork; ${m.name}") require (m.regionType <= RegionType.UNCACHED) } // The Cork turns [Acquire=>Get] => [AccessAckData=>GrantData] // and [ReleaseData=>PutFullData] => [AccessAck=>ReleaseAck] // We need to encode information sufficient to reverse the transformation in output. // A caveat is that we get Acquire+Release with the same source and must keep the // source unique after transformation onto the A channel. // The coding scheme is: // Release, AcquireBlock.BtoT, AcquirePerm => instant response // Put{Full,Partial}Data: 1, ReleaseData: 0 => AccessAck // {Arithmetic,Logical}Data,Get: 0, Acquire: 1 => AccessAckData // Hint:0 => HintAck // The CacheCork can potentially send the same source twice if a client sends // simultaneous Release and AMO/Get with the same source. It will still correctly // decode the messages based on the D.opcode, but the double use violates the spec. // Fortunately, no masters we know of behave this way! // Take requests from A to A or D (if BtoT Acquire) val a_a = Wire(chiselTypeOf(out.a)) val a_d = Wire(chiselTypeOf(in.d)) val isPut = in.a.bits.opcode === PutFullData || in.a.bits.opcode === PutPartialData val toD = (in.a.bits.opcode === AcquireBlock && in.a.bits.param === TLPermissions.BtoT) || (in.a.bits.opcode === AcquirePerm) in.a.ready := Mux(toD, a_d.ready, a_a.ready) a_a.valid := in.a.valid && !toD a_a.bits := in.a.bits a_a.bits.source := in.a.bits.source << 1 | Mux(isPut, 1.U, 0.U) // Transform Acquire into Get when (in.a.bits.opcode === AcquireBlock || in.a.bits.opcode === AcquirePerm) { a_a.bits.opcode := Get a_a.bits.param := 0.U a_a.bits.source := in.a.bits.source << 1 | 1.U } // Upgrades are instantly successful a_d.valid := in.a.valid && toD a_d.bits := edgeIn.Grant( fromSink = 0.U, toSource = in.a.bits.source, lgSize = in.a.bits.size, capPermissions = TLPermissions.toT) // Take ReleaseData from C to A; Release from C to D val c_a = Wire(chiselTypeOf(out.a)) c_a.valid := in.c.valid && in.c.bits.opcode === ReleaseData c_a.bits := edgeOut.Put( fromSource = in.c.bits.source << 1, toAddress = in.c.bits.address, lgSize = in.c.bits.size, data = in.c.bits.data, corrupt = in.c.bits.corrupt)._2 c_a.bits.user :<= in.c.bits.user // Releases without Data succeed instantly val c_d = Wire(chiselTypeOf(in.d)) c_d.valid := in.c.valid && in.c.bits.opcode === Release c_d.bits := edgeIn.ReleaseAck(in.c.bits) assert (!in.c.valid || in.c.bits.opcode === Release || in.c.bits.opcode === ReleaseData) in.c.ready := Mux(in.c.bits.opcode === Release, c_d.ready, c_a.ready) // Discard E in.e.ready := true.B // Block B; should never happen out.b.ready := false.B assert (!out.b.valid) // Track in-flight sinkIds val pool = Module(new IDPool(sinkIds)) pool.io.free.valid := in.e.fire pool.io.free.bits := in.e.bits.sink val in_d = Wire(chiselTypeOf(in.d)) val d_first = edgeOut.first(in_d) val d_grant = in_d.bits.opcode === GrantData || in_d.bits.opcode === Grant pool.io.alloc.ready := in.d.fire && d_first && d_grant in.d.valid := in_d.valid && (pool.io.alloc.valid || !d_first || !d_grant) in_d.ready := in.d.ready && (pool.io.alloc.valid || !d_first || !d_grant) in.d.bits := in_d.bits in.d.bits.sink := pool.io.alloc.bits holdUnless d_first // Take responses from D and transform them val d_d = Wire(chiselTypeOf(in.d)) d_d <> out.d d_d.bits.source := out.d.bits.source >> 1 // Record if a target was writable and auto-promote toT if it was // This is structured so that the vector can be constant prop'd away val wSourceVec = Reg(Vec(edgeIn.client.endSourceId, Bool())) val aWOk = edgeIn.manager.fastProperty(in.a.bits.address, !_.supportsPutFull.none, (b:Boolean) => b.B) val dWOk = wSourceVec(d_d.bits.source) val bypass = (edgeIn.manager.minLatency == 0).B && in.a.valid && in.a.bits.source === d_d.bits.source val dWHeld = Mux(bypass, aWOk, dWOk) holdUnless d_first when (in.a.fire) { wSourceVec(in.a.bits.source) := aWOk } // Wipe out any unused registers edgeIn.client.unusedSources.foreach { id => wSourceVec(id) := edgeIn.manager.anySupportPutFull.B } when (out.d.bits.opcode === AccessAckData && out.d.bits.source(0)) { d_d.bits.opcode := GrantData d_d.bits.param := Mux(dWHeld, TLPermissions.toT, TLPermissions.toB) } when (out.d.bits.opcode === AccessAck && !out.d.bits.source(0)) { d_d.bits.opcode := ReleaseAck } // Combine the sources of messages into the channels TLArbiter(TLArbiter.lowestIndexFirst)(out.a, (edgeOut.numBeats1(c_a.bits), c_a), (edgeOut.numBeats1(a_a.bits), a_a)) TLArbiter(TLArbiter.lowestIndexFirst)(in_d, (edgeIn .numBeats1(d_d.bits), d_d), (0.U, Queue(c_d, 2)), (0.U, Queue(a_d, 2))) // Tie off unused ports in.b.valid := false.B out.c.valid := false.B out.e.valid := false.B } } } } object TLCacheCork { def apply(params: TLCacheCorkParams)(implicit p: Parameters): TLNode = { val cork = LazyModule(new TLCacheCork(params)) cork.node } def apply(unsafe: Boolean = false, sinkIds: Int = 8)(implicit p: Parameters): TLNode = { apply(TLCacheCorkParams(unsafe, sinkIds)) } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } } File Arbiter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ object TLArbiter { // (valids, select) => readys type Policy = (Integer, UInt, Bool) => UInt val lowestIndexFirst: Policy = (width, valids, select) => ~(leftOR(valids) << 1)(width-1, 0) val highestIndexFirst: Policy = (width, valids, select) => ~((rightOR(valids) >> 1).pad(width)) val roundRobin: Policy = (width, valids, select) => if (width == 1) 1.U(1.W) else { val valid = valids(width-1, 0) assert (valid === valids) val mask = RegInit(((BigInt(1) << width)-1).U(width-1,0)) val filter = Cat(valid & ~mask, valid) val unready = (rightOR(filter, width*2, width) >> 1) | (mask << width) val readys = ~((unready >> width) & unready(width-1, 0)) when (select && valid.orR) { mask := leftOR(readys & valid, width) } readys(width-1, 0) } def lowestFromSeq[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: Seq[DecoupledIO[T]]): Unit = { apply(lowestIndexFirst)(sink, sources.map(s => (edge.numBeats1(s.bits), s)):_*) } def lowest[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]*): Unit = { apply(lowestIndexFirst)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_*) } def highest[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]*): Unit = { apply(highestIndexFirst)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_*) } def robin[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]*): Unit = { apply(roundRobin)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_*) } def apply[T <: Data](policy: Policy)(sink: DecoupledIO[T], sources: (UInt, DecoupledIO[T])*): Unit = { if (sources.isEmpty) { sink.bits := DontCare } else if (sources.size == 1) { sink :<>= sources.head._2 } else { val pairs = sources.toList val beatsIn = pairs.map(_._1) val sourcesIn = pairs.map(_._2) // The number of beats which remain to be sent val beatsLeft = RegInit(0.U) val idle = beatsLeft === 0.U val latch = idle && sink.ready // winner (if any) claims sink // Who wants access to the sink? val valids = sourcesIn.map(_.valid) // Arbitrate amongst the requests val readys = VecInit(policy(valids.size, Cat(valids.reverse), latch).asBools) // Which request wins arbitration? val winner = VecInit((readys zip valids) map { case (r,v) => r&&v }) // Confirm the policy works properly require (readys.size == valids.size) // Never two winners val prefixOR = winner.scanLeft(false.B)(_||_).init assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _}) // If there was any request, there is a winner assert (!valids.reduce(_||_) || winner.reduce(_||_)) // Track remaining beats val maskedBeats = (winner zip beatsIn) map { case (w,b) => Mux(w, b, 0.U) } val initBeats = maskedBeats.reduce(_ | _) // no winner => 0 beats beatsLeft := Mux(latch, initBeats, beatsLeft - sink.fire) // The one-hot source granted access in the previous cycle val state = RegInit(VecInit(Seq.fill(sources.size)(false.B))) val muxState = Mux(idle, winner, state) state := muxState val allowed = Mux(idle, readys, state) (sourcesIn zip allowed) foreach { case (s, r) => s.ready := sink.ready && r } sink.valid := Mux(idle, valids.reduce(_||_), Mux1H(state, valids)) sink.bits :<= Mux1H(muxState, sourcesIn.map(_.bits)) } } } // Synthesizable unit tests import freechips.rocketchip.unittest._ abstract class DecoupledArbiterTest( policy: TLArbiter.Policy, txns: Int, timeout: Int, val numSources: Int, beatsLeftFromIdx: Int => UInt) (implicit p: Parameters) extends UnitTest(timeout) { val sources = Wire(Vec(numSources, DecoupledIO(UInt(log2Ceil(numSources).W)))) dontTouch(sources.suggestName("sources")) val sink = Wire(DecoupledIO(UInt(log2Ceil(numSources).W))) dontTouch(sink.suggestName("sink")) val count = RegInit(0.U(log2Ceil(txns).W)) val lfsr = LFSR(16, true.B) sources.zipWithIndex.map { case (z, i) => z.bits := i.U } TLArbiter(policy)(sink, sources.zipWithIndex.map { case (z, i) => (beatsLeftFromIdx(i), z) }:_*) count := count + 1.U io.finished := count >= txns.U } /** This tests that when a specific pattern of source valids are driven, * a new index from amongst that pattern is always selected, * unless one of those sources takes multiple beats, * in which case the same index should be selected until the arbiter goes idle. */ class TLDecoupledArbiterRobinTest(txns: Int = 128, timeout: Int = 500000, print: Boolean = false) (implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.roundRobin, txns, timeout, 6, i => i.U) { val lastWinner = RegInit((numSources+1).U) val beatsLeft = RegInit(0.U(log2Ceil(numSources).W)) val first = lastWinner > numSources.U val valid = lfsr(0) val ready = lfsr(15) sink.ready := ready sources.zipWithIndex.map { // pattern: every even-indexed valid is driven the same random way case (s, i) => s.valid := (if (i % 2 == 1) false.B else valid) } when (sink.fire) { if (print) { printf("TestRobin: %d\n", sink.bits) } when (beatsLeft === 0.U) { assert(lastWinner =/= sink.bits, "Round robin did not pick a new idx despite one being valid.") lastWinner := sink.bits beatsLeft := sink.bits } .otherwise { assert(lastWinner === sink.bits, "Round robin did not pick the same index over multiple beats") beatsLeft := beatsLeft - 1.U } } if (print) { when (!sink.fire) { printf("TestRobin: idle (%d %d)\n", valid, ready) } } } /** This tests that the lowest index is always selected across random single cycle transactions. */ class TLDecoupledArbiterLowestTest(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.lowestIndexFirst, txns, timeout, 15, _ => 0.U) { def assertLowest(id: Int): Unit = { when (sources(id).valid) { assert((numSources-1 until id by -1).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a higher valid source was granted ready.") } } sources.zipWithIndex.map { case (s, i) => s.valid := lfsr(i) } sink.ready := lfsr(15) when (sink.fire) { (0 until numSources).foreach(assertLowest(_)) } } /** This tests that the highest index is always selected across random single cycle transactions. */ class TLDecoupledArbiterHighestTest(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.highestIndexFirst, txns, timeout, 15, _ => 0.U) { def assertHighest(id: Int): Unit = { when (sources(id).valid) { assert((0 until id).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a lower valid source was granted ready.") } } sources.zipWithIndex.map { case (s, i) => s.valid := lfsr(i) } sink.ready := lfsr(15) when (sink.fire) { (0 until numSources).foreach(assertHighest(_)) } }

module TLCacheCork( // @[CacheCork.scala:42:9] input clock, // @[CacheCork.scala:42:9] input reset, // @[CacheCork.scala:42:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_in_c_ready, // @[LazyModuleImp.scala:107:25] input auto_in_c_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_in_c_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_c_bits_address, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_c_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_e_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_e_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire _q_1_io_deq_valid; // @[Decoupled.scala:362:21] wire [2:0] _q_1_io_deq_bits_opcode; // @[Decoupled.scala:362:21] wire [1:0] _q_1_io_deq_bits_param; // @[Decoupled.scala:362:21] wire [2:0] _q_1_io_deq_bits_size; // @[Decoupled.scala:362:21] wire [4:0] _q_1_io_deq_bits_source; // @[Decoupled.scala:362:21] wire [2:0] _q_1_io_deq_bits_sink; // @[Decoupled.scala:362:21] wire _q_1_io_deq_bits_denied; // @[Decoupled.scala:362:21] wire [63:0] _q_1_io_deq_bits_data; // @[Decoupled.scala:362:21] wire _q_1_io_deq_bits_corrupt; // @[Decoupled.scala:362:21] wire _q_io_deq_valid; // @[Decoupled.scala:362:21] wire [2:0] _q_io_deq_bits_opcode; // @[Decoupled.scala:362:21] wire [1:0] _q_io_deq_bits_param; // @[Decoupled.scala:362:21] wire [2:0] _q_io_deq_bits_size; // @[Decoupled.scala:362:21] wire [4:0] _q_io_deq_bits_source; // @[Decoupled.scala:362:21] wire [2:0] _q_io_deq_bits_sink; // @[Decoupled.scala:362:21] wire _q_io_deq_bits_denied; // @[Decoupled.scala:362:21] wire [63:0] _q_io_deq_bits_data; // @[Decoupled.scala:362:21] wire _q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21] wire _pool_io_alloc_valid; // @[CacheCork.scala:127:26] wire [2:0] _pool_io_alloc_bits; // @[CacheCork.scala:127:26] wire auto_in_a_valid_0 = auto_in_a_valid; // @[CacheCork.scala:42:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[CacheCork.scala:42:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[CacheCork.scala:42:9] wire [2:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[CacheCork.scala:42:9] wire [4:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[CacheCork.scala:42:9] wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[CacheCork.scala:42:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[CacheCork.scala:42:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[CacheCork.scala:42:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[CacheCork.scala:42:9] wire auto_in_c_valid_0 = auto_in_c_valid; // @[CacheCork.scala:42:9] wire [2:0] auto_in_c_bits_opcode_0 = auto_in_c_bits_opcode; // @[CacheCork.scala:42:9] wire [2:0] auto_in_c_bits_param_0 = auto_in_c_bits_param; // @[CacheCork.scala:42:9] wire [2:0] auto_in_c_bits_size_0 = auto_in_c_bits_size; // @[CacheCork.scala:42:9] wire [4:0] auto_in_c_bits_source_0 = auto_in_c_bits_source; // @[CacheCork.scala:42:9] wire [31:0] auto_in_c_bits_address_0 = auto_in_c_bits_address; // @[CacheCork.scala:42:9] wire [63:0] auto_in_c_bits_data_0 = auto_in_c_bits_data; // @[CacheCork.scala:42:9] wire auto_in_c_bits_corrupt_0 = auto_in_c_bits_corrupt; // @[CacheCork.scala:42:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[CacheCork.scala:42:9] wire auto_in_e_valid_0 = auto_in_e_valid; // @[CacheCork.scala:42:9] wire [2:0] auto_in_e_bits_sink_0 = auto_in_e_bits_sink; // @[CacheCork.scala:42:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[CacheCork.scala:42:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[CacheCork.scala:42:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[CacheCork.scala:42:9] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[CacheCork.scala:42:9] wire [2:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[CacheCork.scala:42:9] wire [5:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[CacheCork.scala:42:9] wire auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[CacheCork.scala:42:9] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[CacheCork.scala:42:9] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[CacheCork.scala:42:9] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[CacheCork.scala:42:9] wire auto_in_b_ready = 1'h1; // @[CacheCork.scala:42:9] wire auto_in_e_ready = 1'h1; // @[CacheCork.scala:42:9] wire nodeIn_b_ready = 1'h1; // @[MixedNode.scala:551:17] wire nodeIn_e_ready = 1'h1; // @[MixedNode.scala:551:17] wire _c_a_bits_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _c_a_bits_legal_T_8 = 1'h1; // @[Parameters.scala:137:59] wire _aWOk_T_4 = 1'h1; // @[Parameters.scala:137:59] wire _dWHeld_T = 1'h1; // @[CacheCork.scala:151:25] wire opdata = 1'h1; // @[Edges.scala:92:28] wire auto_in_b_valid = 1'h0; // @[CacheCork.scala:42:9] wire auto_in_b_bits_corrupt = 1'h0; // @[CacheCork.scala:42:9] wire nodeIn_b_valid = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_b_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire a_d_bits_denied = 1'h0; // @[CacheCork.scala:75:23] wire a_d_bits_corrupt = 1'h0; // @[CacheCork.scala:75:23] wire a_d_bits_d_denied = 1'h0; // @[Edges.scala:645:17] wire a_d_bits_d_corrupt = 1'h0; // @[Edges.scala:645:17] wire c_d_bits_denied = 1'h0; // @[CacheCork.scala:112:23] wire c_d_bits_corrupt = 1'h0; // @[CacheCork.scala:112:23] wire c_d_bits_d_denied = 1'h0; // @[Edges.scala:677:17] wire c_d_bits_d_corrupt = 1'h0; // @[Edges.scala:677:17] wire _bypass_T = 1'h0; // @[CacheCork.scala:150:57] wire bypass = 1'h0; // @[CacheCork.scala:150:71] wire _opdata_T = 1'h0; // @[Edges.scala:92:37] wire _state_WIRE_0 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_1 = 1'h0; // @[Arbiter.scala:88:34] wire maskedBeats_1_1 = 1'h0; // @[Arbiter.scala:82:69] wire maskedBeats_2 = 1'h0; // @[Arbiter.scala:82:69] wire _state_WIRE_1_0 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_1_1 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_1_2 = 1'h0; // @[Arbiter.scala:88:34] wire [2:0] auto_in_b_bits_opcode = 3'h0; // @[CacheCork.scala:42:9] wire [2:0] auto_in_b_bits_size = 3'h0; // @[CacheCork.scala:42:9] wire [2:0] nodeIn_b_bits_opcode = 3'h0; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_b_bits_size = 3'h0; // @[MixedNode.scala:551:17] wire [2:0] a_d_bits_sink = 3'h0; // @[CacheCork.scala:75:23] wire [2:0] a_d_bits_d_sink = 3'h0; // @[Edges.scala:645:17] wire [2:0] c_a_bits_opcode = 3'h0; // @[CacheCork.scala:101:23] wire [2:0] c_a_bits_param = 3'h0; // @[CacheCork.scala:101:23] wire [2:0] c_a_bits_a_opcode = 3'h0; // @[Edges.scala:480:17] wire [2:0] c_a_bits_a_param = 3'h0; // @[Edges.scala:480:17] wire [2:0] c_d_bits_sink = 3'h0; // @[CacheCork.scala:112:23] wire [2:0] c_d_bits_d_sink = 3'h0; // @[Edges.scala:677:17] wire [2:0] _nodeOut_a_bits_T_18 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _nodeOut_a_bits_T_21 = 3'h0; // @[Mux.scala:30:73] wire [1:0] auto_in_b_bits_param = 2'h0; // @[CacheCork.scala:42:9] wire [1:0] nodeIn_b_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] a_d_bits_param = 2'h0; // @[CacheCork.scala:75:23] wire [1:0] a_d_bits_d_param = 2'h0; // @[Edges.scala:645:17] wire [1:0] c_d_bits_param = 2'h0; // @[CacheCork.scala:112:23] wire [1:0] c_d_bits_d_param = 2'h0; // @[Edges.scala:677:17] wire [4:0] auto_in_b_bits_source = 5'h0; // @[CacheCork.scala:42:9] wire [4:0] nodeIn_b_bits_source = 5'h0; // @[MixedNode.scala:551:17] wire [31:0] auto_in_b_bits_address = 32'h0; // @[CacheCork.scala:42:9] wire [31:0] nodeIn_b_bits_address = 32'h0; // @[MixedNode.scala:551:17] wire [7:0] auto_in_b_bits_mask = 8'h0; // @[CacheCork.scala:42:9] wire [7:0] nodeIn_b_bits_mask = 8'h0; // @[MixedNode.scala:551:17] wire [63:0] auto_in_b_bits_data = 64'h0; // @[CacheCork.scala:42:9] wire [63:0] nodeIn_b_bits_data = 64'h0; // @[MixedNode.scala:551:17] wire [63:0] a_d_bits_data = 64'h0; // @[CacheCork.scala:75:23] wire [63:0] a_d_bits_d_data = 64'h0; // @[Edges.scala:645:17] wire [63:0] c_d_bits_data = 64'h0; // @[CacheCork.scala:112:23] wire [63:0] c_d_bits_d_data = 64'h0; // @[Edges.scala:677:17] wire [2:0] a_d_bits_opcode = 3'h4; // @[CacheCork.scala:75:23] wire [2:0] a_d_bits_d_opcode = 3'h4; // @[Edges.scala:645:17] wire [2:0] c_d_bits_opcode = 3'h6; // @[CacheCork.scala:112:23] wire [2:0] c_d_bits_d_opcode = 3'h6; // @[Edges.scala:677:17] wire [32:0] _c_a_bits_legal_T_6 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _c_a_bits_legal_T_7 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _aWOk_T_2 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _aWOk_T_3 = 33'h0; // @[Parameters.scala:137:46] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[CacheCork.scala:42:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[CacheCork.scala:42:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[CacheCork.scala:42:9] wire [2:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[CacheCork.scala:42:9] wire [4:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[CacheCork.scala:42:9] wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[CacheCork.scala:42:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[CacheCork.scala:42:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[CacheCork.scala:42:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[CacheCork.scala:42:9] wire nodeIn_c_ready; // @[MixedNode.scala:551:17] wire nodeIn_c_valid = auto_in_c_valid_0; // @[CacheCork.scala:42:9] wire [2:0] nodeIn_c_bits_opcode = auto_in_c_bits_opcode_0; // @[CacheCork.scala:42:9] wire [2:0] nodeIn_c_bits_param = auto_in_c_bits_param_0; // @[CacheCork.scala:42:9] wire [2:0] nodeIn_c_bits_size = auto_in_c_bits_size_0; // @[CacheCork.scala:42:9] wire [4:0] nodeIn_c_bits_source = auto_in_c_bits_source_0; // @[CacheCork.scala:42:9] wire [31:0] nodeIn_c_bits_address = auto_in_c_bits_address_0; // @[CacheCork.scala:42:9] wire [63:0] nodeIn_c_bits_data = auto_in_c_bits_data_0; // @[CacheCork.scala:42:9] wire nodeIn_c_bits_corrupt = auto_in_c_bits_corrupt_0; // @[CacheCork.scala:42:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[CacheCork.scala:42:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [4:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeIn_e_valid = auto_in_e_valid_0; // @[CacheCork.scala:42:9] wire [2:0] nodeIn_e_bits_sink = auto_in_e_bits_sink_0; // @[CacheCork.scala:42:9] wire nodeOut_a_ready = auto_out_a_ready_0; // @[CacheCork.scala:42:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [5:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[CacheCork.scala:42:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[CacheCork.scala:42:9] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[CacheCork.scala:42:9] wire [2:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[CacheCork.scala:42:9] wire [5:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[CacheCork.scala:42:9] wire nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[CacheCork.scala:42:9] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[CacheCork.scala:42:9] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[CacheCork.scala:42:9] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[CacheCork.scala:42:9] wire auto_in_a_ready_0; // @[CacheCork.scala:42:9] wire auto_in_c_ready_0; // @[CacheCork.scala:42:9] wire [2:0] auto_in_d_bits_opcode_0; // @[CacheCork.scala:42:9] wire [1:0] auto_in_d_bits_param_0; // @[CacheCork.scala:42:9] wire [2:0] auto_in_d_bits_size_0; // @[CacheCork.scala:42:9] wire [4:0] auto_in_d_bits_source_0; // @[CacheCork.scala:42:9] wire [2:0] auto_in_d_bits_sink_0; // @[CacheCork.scala:42:9] wire auto_in_d_bits_denied_0; // @[CacheCork.scala:42:9] wire [63:0] auto_in_d_bits_data_0; // @[CacheCork.scala:42:9] wire auto_in_d_bits_corrupt_0; // @[CacheCork.scala:42:9] wire auto_in_d_valid_0; // @[CacheCork.scala:42:9] wire [2:0] auto_out_a_bits_opcode_0; // @[CacheCork.scala:42:9] wire [2:0] auto_out_a_bits_param_0; // @[CacheCork.scala:42:9] wire [2:0] auto_out_a_bits_size_0; // @[CacheCork.scala:42:9] wire [5:0] auto_out_a_bits_source_0; // @[CacheCork.scala:42:9] wire [31:0] auto_out_a_bits_address_0; // @[CacheCork.scala:42:9] wire [7:0] auto_out_a_bits_mask_0; // @[CacheCork.scala:42:9] wire [63:0] auto_out_a_bits_data_0; // @[CacheCork.scala:42:9] wire auto_out_a_bits_corrupt_0; // @[CacheCork.scala:42:9] wire auto_out_a_valid_0; // @[CacheCork.scala:42:9] wire auto_out_d_ready_0; // @[CacheCork.scala:42:9] wire _nodeIn_a_ready_T; // @[CacheCork.scala:79:26] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[CacheCork.scala:42:9] wire [2:0] a_a_bits_size = nodeIn_a_bits_size; // @[CacheCork.scala:74:23] wire [2:0] a_d_bits_d_size = nodeIn_a_bits_size; // @[Edges.scala:645:17] wire [4:0] a_d_bits_d_source = nodeIn_a_bits_source; // @[Edges.scala:645:17] wire [31:0] a_a_bits_address = nodeIn_a_bits_address; // @[CacheCork.scala:74:23] wire [31:0] _aWOk_T = nodeIn_a_bits_address; // @[Parameters.scala:137:31] wire [7:0] a_a_bits_mask = nodeIn_a_bits_mask; // @[CacheCork.scala:74:23] wire [63:0] a_a_bits_data = nodeIn_a_bits_data; // @[CacheCork.scala:74:23] wire a_a_bits_corrupt = nodeIn_a_bits_corrupt; // @[CacheCork.scala:74:23] wire _nodeIn_c_ready_T_1; // @[CacheCork.scala:117:26] assign auto_in_c_ready_0 = nodeIn_c_ready; // @[CacheCork.scala:42:9] wire [2:0] c_a_bits_a_size = nodeIn_c_bits_size; // @[Edges.scala:480:17] wire [2:0] _c_a_bits_a_mask_sizeOH_T = nodeIn_c_bits_size; // @[Misc.scala:202:34] wire [2:0] c_d_bits_d_size = nodeIn_c_bits_size; // @[Edges.scala:677:17] wire [4:0] c_d_bits_d_source = nodeIn_c_bits_source; // @[Edges.scala:677:17] wire [31:0] _c_a_bits_legal_T_4 = nodeIn_c_bits_address; // @[Parameters.scala:137:31] wire [31:0] c_a_bits_a_address = nodeIn_c_bits_address; // @[Edges.scala:480:17] wire [63:0] c_a_bits_a_data = nodeIn_c_bits_data; // @[Edges.scala:480:17] wire c_a_bits_a_corrupt = nodeIn_c_bits_corrupt; // @[Edges.scala:480:17] wire _nodeIn_d_valid_T_4; // @[CacheCork.scala:135:34] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[CacheCork.scala:42:9] wire [2:0] in_d_bits_opcode; // @[CacheCork.scala:131:24] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[CacheCork.scala:42:9] wire [1:0] in_d_bits_param; // @[CacheCork.scala:131:24] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[CacheCork.scala:42:9] wire [2:0] in_d_bits_size; // @[CacheCork.scala:131:24] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[CacheCork.scala:42:9] wire [4:0] in_d_bits_source; // @[CacheCork.scala:131:24] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[CacheCork.scala:42:9] wire [2:0] _nodeIn_d_bits_sink_T; // @[package.scala:88:42] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[CacheCork.scala:42:9] wire in_d_bits_denied; // @[CacheCork.scala:131:24] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[CacheCork.scala:42:9] wire [63:0] in_d_bits_data; // @[CacheCork.scala:131:24] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[CacheCork.scala:42:9] wire in_d_bits_corrupt; // @[CacheCork.scala:131:24] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[CacheCork.scala:42:9] wire _pool_io_free_valid_T = nodeIn_e_valid; // @[Decoupled.scala:51:35] wire _nodeOut_a_valid_T_4; // @[Arbiter.scala:96:24] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[CacheCork.scala:42:9] wire [2:0] _nodeOut_a_bits_WIRE_opcode; // @[Mux.scala:30:73] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[CacheCork.scala:42:9] wire [2:0] _nodeOut_a_bits_WIRE_param; // @[Mux.scala:30:73] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[CacheCork.scala:42:9] wire [2:0] _nodeOut_a_bits_WIRE_size; // @[Mux.scala:30:73] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[CacheCork.scala:42:9] wire [5:0] _nodeOut_a_bits_WIRE_source; // @[Mux.scala:30:73] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[CacheCork.scala:42:9] wire [31:0] _nodeOut_a_bits_WIRE_address; // @[Mux.scala:30:73] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[CacheCork.scala:42:9] wire [7:0] _nodeOut_a_bits_WIRE_mask; // @[Mux.scala:30:73] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[CacheCork.scala:42:9] wire [63:0] _nodeOut_a_bits_WIRE_data; // @[Mux.scala:30:73] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[CacheCork.scala:42:9] wire _nodeOut_a_bits_WIRE_corrupt; // @[Mux.scala:30:73] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[CacheCork.scala:42:9] wire d_d_ready; // @[CacheCork.scala:141:23] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[CacheCork.scala:42:9] wire d_d_valid = nodeOut_d_valid; // @[CacheCork.scala:141:23] wire [2:0] d_d_bits_size = nodeOut_d_bits_size; // @[CacheCork.scala:141:23] wire d_d_bits_denied = nodeOut_d_bits_denied; // @[CacheCork.scala:141:23] wire [63:0] d_d_bits_data = nodeOut_d_bits_data; // @[CacheCork.scala:141:23] wire d_d_bits_corrupt = nodeOut_d_bits_corrupt; // @[CacheCork.scala:141:23] wire _a_a_ready_T; // @[Arbiter.scala:94:31] wire _a_a_valid_T_1; // @[CacheCork.scala:81:33] wire [2:0] a_a_bits_opcode; // @[CacheCork.scala:74:23] wire [2:0] a_a_bits_param; // @[CacheCork.scala:74:23] wire [5:0] a_a_bits_source; // @[CacheCork.scala:74:23] wire a_a_ready; // @[CacheCork.scala:74:23] wire a_a_valid; // @[CacheCork.scala:74:23] wire _a_d_valid_T; // @[CacheCork.scala:93:33] wire [2:0] a_d_bits_size; // @[CacheCork.scala:75:23] wire [4:0] a_d_bits_source; // @[CacheCork.scala:75:23] wire a_d_ready; // @[CacheCork.scala:75:23] wire a_d_valid; // @[CacheCork.scala:75:23] wire _isPut_T = nodeIn_a_bits_opcode == 3'h0; // @[CacheCork.scala:76:38] wire _isPut_T_1 = nodeIn_a_bits_opcode == 3'h1; // @[CacheCork.scala:76:74] wire isPut = _isPut_T | _isPut_T_1; // @[CacheCork.scala:76:{38,54,74}] wire _a_a_bits_source_T_1 = isPut; // @[CacheCork.scala:76:54, :83:55] wire _toD_T = nodeIn_a_bits_opcode == 3'h6; // @[CacheCork.scala:77:37] wire _toD_T_1 = nodeIn_a_bits_param == 3'h2; // @[CacheCork.scala:77:73] wire _toD_T_2 = _toD_T & _toD_T_1; // @[CacheCork.scala:77:{37,54,73}] wire _toD_T_3 = &nodeIn_a_bits_opcode; // @[CacheCork.scala:78:37] wire toD = _toD_T_2 | _toD_T_3; // @[CacheCork.scala:77:{54,97}, :78:37] assign _nodeIn_a_ready_T = toD ? a_d_ready : a_a_ready; // @[CacheCork.scala:74:23, :75:23, :77:97, :79:26] assign nodeIn_a_ready = _nodeIn_a_ready_T; // @[CacheCork.scala:79:26] wire _a_a_valid_T = ~toD; // @[CacheCork.scala:77:97, :81:36] assign _a_a_valid_T_1 = nodeIn_a_valid & _a_a_valid_T; // @[CacheCork.scala:81:{33,36}] assign a_a_valid = _a_a_valid_T_1; // @[CacheCork.scala:74:23, :81:33] wire [5:0] _GEN = {nodeIn_a_bits_source, 1'h0}; // @[CacheCork.scala:83:45] wire [5:0] _a_a_bits_source_T; // @[CacheCork.scala:83:45] assign _a_a_bits_source_T = _GEN; // @[CacheCork.scala:83:45] wire [5:0] _a_a_bits_source_T_3; // @[CacheCork.scala:89:47] assign _a_a_bits_source_T_3 = _GEN; // @[CacheCork.scala:83:45, :89:47] wire [5:0] _a_a_bits_source_T_2 = {_a_a_bits_source_T[5:1], _a_a_bits_source_T[0] | _a_a_bits_source_T_1}; // @[CacheCork.scala:83:{45,50,55}] wire _T_2 = _toD_T | (&nodeIn_a_bits_opcode); // @[CacheCork.scala:77:37, :78:37, :86:49] assign a_a_bits_opcode = _T_2 ? 3'h4 : nodeIn_a_bits_opcode; // @[CacheCork.scala:74:23, :82:18, :86:{49,86}, :87:27] assign a_a_bits_param = _T_2 ? 3'h0 : nodeIn_a_bits_param; // @[CacheCork.scala:74:23, :82:18, :86:{49,86}, :88:27] wire [5:0] _a_a_bits_source_T_4 = {_a_a_bits_source_T_3[5:1], 1'h1}; // @[CacheCork.scala:89:{47,52}] assign a_a_bits_source = _T_2 ? _a_a_bits_source_T_4 : _a_a_bits_source_T_2; // @[CacheCork.scala:74:23, :83:{25,50}, :86:{49,86}, :89:{27,52}] assign _a_d_valid_T = nodeIn_a_valid & toD; // @[CacheCork.scala:77:97, :93:33] assign a_d_valid = _a_d_valid_T; // @[CacheCork.scala:75:23, :93:33] assign a_d_bits_size = a_d_bits_d_size; // @[Edges.scala:645:17] assign a_d_bits_source = a_d_bits_d_source; // @[Edges.scala:645:17] wire _c_a_ready_T; // @[Arbiter.scala:94:31] wire _c_a_valid_T_1; // @[CacheCork.scala:102:33] wire [5:0] c_a_bits_a_source; // @[Edges.scala:480:17] wire [7:0] c_a_bits_a_mask; // @[Edges.scala:480:17] wire [2:0] c_a_bits_size; // @[CacheCork.scala:101:23] wire [5:0] c_a_bits_source; // @[CacheCork.scala:101:23] wire [31:0] c_a_bits_address; // @[CacheCork.scala:101:23] wire [7:0] c_a_bits_mask; // @[CacheCork.scala:101:23] wire [63:0] c_a_bits_data; // @[CacheCork.scala:101:23] wire c_a_bits_corrupt; // @[CacheCork.scala:101:23] wire c_a_ready; // @[CacheCork.scala:101:23] wire c_a_valid; // @[CacheCork.scala:101:23] wire _c_a_valid_T = &nodeIn_c_bits_opcode; // @[CacheCork.scala:102:53] assign _c_a_valid_T_1 = nodeIn_c_valid & _c_a_valid_T; // @[CacheCork.scala:102:{33,53}] assign c_a_valid = _c_a_valid_T_1; // @[CacheCork.scala:101:23, :102:33] wire [5:0] _c_a_bits_T = {nodeIn_c_bits_source, 1'h0}; // @[CacheCork.scala:104:41] assign c_a_bits_a_source = _c_a_bits_T; // @[Edges.scala:480:17] wire _c_a_bits_legal_T_1 = nodeIn_c_bits_size != 3'h7; // @[Parameters.scala:92:38] wire _c_a_bits_legal_T_2 = _c_a_bits_legal_T_1; // @[Parameters.scala:92:{33,38}] wire _c_a_bits_legal_T_3 = _c_a_bits_legal_T_2; // @[Parameters.scala:684:29] wire _c_a_bits_legal_T_9 = _c_a_bits_legal_T_3; // @[Parameters.scala:684:{29,54}] wire [32:0] _c_a_bits_legal_T_5 = {1'h0, _c_a_bits_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire c_a_bits_legal = _c_a_bits_legal_T_9; // @[Parameters.scala:684:54, :686:26] assign c_a_bits_size = c_a_bits_a_size; // @[Edges.scala:480:17] assign c_a_bits_source = c_a_bits_a_source; // @[Edges.scala:480:17] assign c_a_bits_address = c_a_bits_a_address; // @[Edges.scala:480:17] wire [7:0] _c_a_bits_a_mask_T; // @[Misc.scala:222:10] assign c_a_bits_mask = c_a_bits_a_mask; // @[Edges.scala:480:17] assign c_a_bits_data = c_a_bits_a_data; // @[Edges.scala:480:17] assign c_a_bits_corrupt = c_a_bits_a_corrupt; // @[Edges.scala:480:17] wire [1:0] c_a_bits_a_mask_sizeOH_shiftAmount = _c_a_bits_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _c_a_bits_a_mask_sizeOH_T_1 = 4'h1 << c_a_bits_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _c_a_bits_a_mask_sizeOH_T_2 = _c_a_bits_a_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] c_a_bits_a_mask_sizeOH = {_c_a_bits_a_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire c_a_bits_a_mask_sub_sub_sub_0_1 = nodeIn_c_bits_size > 3'h2; // @[Misc.scala:206:21] wire c_a_bits_a_mask_sub_sub_size = c_a_bits_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire c_a_bits_a_mask_sub_sub_bit = nodeIn_c_bits_address[2]; // @[Misc.scala:210:26] wire c_a_bits_a_mask_sub_sub_1_2 = c_a_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire c_a_bits_a_mask_sub_sub_nbit = ~c_a_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire c_a_bits_a_mask_sub_sub_0_2 = c_a_bits_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _c_a_bits_a_mask_sub_sub_acc_T = c_a_bits_a_mask_sub_sub_size & c_a_bits_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire c_a_bits_a_mask_sub_sub_0_1 = c_a_bits_a_mask_sub_sub_sub_0_1 | _c_a_bits_a_mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _c_a_bits_a_mask_sub_sub_acc_T_1 = c_a_bits_a_mask_sub_sub_size & c_a_bits_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire c_a_bits_a_mask_sub_sub_1_1 = c_a_bits_a_mask_sub_sub_sub_0_1 | _c_a_bits_a_mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire c_a_bits_a_mask_sub_size = c_a_bits_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire c_a_bits_a_mask_sub_bit = nodeIn_c_bits_address[1]; // @[Misc.scala:210:26] wire c_a_bits_a_mask_sub_nbit = ~c_a_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire c_a_bits_a_mask_sub_0_2 = c_a_bits_a_mask_sub_sub_0_2 & c_a_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _c_a_bits_a_mask_sub_acc_T = c_a_bits_a_mask_sub_size & c_a_bits_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire c_a_bits_a_mask_sub_0_1 = c_a_bits_a_mask_sub_sub_0_1 | _c_a_bits_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire c_a_bits_a_mask_sub_1_2 = c_a_bits_a_mask_sub_sub_0_2 & c_a_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _c_a_bits_a_mask_sub_acc_T_1 = c_a_bits_a_mask_sub_size & c_a_bits_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire c_a_bits_a_mask_sub_1_1 = c_a_bits_a_mask_sub_sub_0_1 | _c_a_bits_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire c_a_bits_a_mask_sub_2_2 = c_a_bits_a_mask_sub_sub_1_2 & c_a_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _c_a_bits_a_mask_sub_acc_T_2 = c_a_bits_a_mask_sub_size & c_a_bits_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire c_a_bits_a_mask_sub_2_1 = c_a_bits_a_mask_sub_sub_1_1 | _c_a_bits_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire c_a_bits_a_mask_sub_3_2 = c_a_bits_a_mask_sub_sub_1_2 & c_a_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _c_a_bits_a_mask_sub_acc_T_3 = c_a_bits_a_mask_sub_size & c_a_bits_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire c_a_bits_a_mask_sub_3_1 = c_a_bits_a_mask_sub_sub_1_1 | _c_a_bits_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire c_a_bits_a_mask_size = c_a_bits_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire c_a_bits_a_mask_bit = nodeIn_c_bits_address[0]; // @[Misc.scala:210:26] wire c_a_bits_a_mask_nbit = ~c_a_bits_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire c_a_bits_a_mask_eq = c_a_bits_a_mask_sub_0_2 & c_a_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _c_a_bits_a_mask_acc_T = c_a_bits_a_mask_size & c_a_bits_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire c_a_bits_a_mask_acc = c_a_bits_a_mask_sub_0_1 | _c_a_bits_a_mask_acc_T; // @[Misc.scala:215:{29,38}] wire c_a_bits_a_mask_eq_1 = c_a_bits_a_mask_sub_0_2 & c_a_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _c_a_bits_a_mask_acc_T_1 = c_a_bits_a_mask_size & c_a_bits_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire c_a_bits_a_mask_acc_1 = c_a_bits_a_mask_sub_0_1 | _c_a_bits_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire c_a_bits_a_mask_eq_2 = c_a_bits_a_mask_sub_1_2 & c_a_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _c_a_bits_a_mask_acc_T_2 = c_a_bits_a_mask_size & c_a_bits_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire c_a_bits_a_mask_acc_2 = c_a_bits_a_mask_sub_1_1 | _c_a_bits_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire c_a_bits_a_mask_eq_3 = c_a_bits_a_mask_sub_1_2 & c_a_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _c_a_bits_a_mask_acc_T_3 = c_a_bits_a_mask_size & c_a_bits_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire c_a_bits_a_mask_acc_3 = c_a_bits_a_mask_sub_1_1 | _c_a_bits_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire c_a_bits_a_mask_eq_4 = c_a_bits_a_mask_sub_2_2 & c_a_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _c_a_bits_a_mask_acc_T_4 = c_a_bits_a_mask_size & c_a_bits_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire c_a_bits_a_mask_acc_4 = c_a_bits_a_mask_sub_2_1 | _c_a_bits_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire c_a_bits_a_mask_eq_5 = c_a_bits_a_mask_sub_2_2 & c_a_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _c_a_bits_a_mask_acc_T_5 = c_a_bits_a_mask_size & c_a_bits_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire c_a_bits_a_mask_acc_5 = c_a_bits_a_mask_sub_2_1 | _c_a_bits_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire c_a_bits_a_mask_eq_6 = c_a_bits_a_mask_sub_3_2 & c_a_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _c_a_bits_a_mask_acc_T_6 = c_a_bits_a_mask_size & c_a_bits_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire c_a_bits_a_mask_acc_6 = c_a_bits_a_mask_sub_3_1 | _c_a_bits_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire c_a_bits_a_mask_eq_7 = c_a_bits_a_mask_sub_3_2 & c_a_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _c_a_bits_a_mask_acc_T_7 = c_a_bits_a_mask_size & c_a_bits_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire c_a_bits_a_mask_acc_7 = c_a_bits_a_mask_sub_3_1 | _c_a_bits_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] c_a_bits_a_mask_lo_lo = {c_a_bits_a_mask_acc_1, c_a_bits_a_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] c_a_bits_a_mask_lo_hi = {c_a_bits_a_mask_acc_3, c_a_bits_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] c_a_bits_a_mask_lo = {c_a_bits_a_mask_lo_hi, c_a_bits_a_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] c_a_bits_a_mask_hi_lo = {c_a_bits_a_mask_acc_5, c_a_bits_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] c_a_bits_a_mask_hi_hi = {c_a_bits_a_mask_acc_7, c_a_bits_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] c_a_bits_a_mask_hi = {c_a_bits_a_mask_hi_hi, c_a_bits_a_mask_hi_lo}; // @[Misc.scala:222:10] assign _c_a_bits_a_mask_T = {c_a_bits_a_mask_hi, c_a_bits_a_mask_lo}; // @[Misc.scala:222:10] assign c_a_bits_a_mask = _c_a_bits_a_mask_T; // @[Misc.scala:222:10] wire _c_d_valid_T_1; // @[CacheCork.scala:113:33] wire [2:0] c_d_bits_size; // @[CacheCork.scala:112:23] wire [4:0] c_d_bits_source; // @[CacheCork.scala:112:23] wire c_d_ready; // @[CacheCork.scala:112:23] wire c_d_valid; // @[CacheCork.scala:112:23] wire _T_4 = nodeIn_c_bits_opcode == 3'h6; // @[CacheCork.scala:113:53] wire _c_d_valid_T; // @[CacheCork.scala:113:53] assign _c_d_valid_T = _T_4; // @[CacheCork.scala:113:53] wire _nodeIn_c_ready_T; // @[CacheCork.scala:117:44] assign _nodeIn_c_ready_T = _T_4; // @[CacheCork.scala:113:53, :117:44] assign _c_d_valid_T_1 = nodeIn_c_valid & _c_d_valid_T; // @[CacheCork.scala:113:{33,53}] assign c_d_valid = _c_d_valid_T_1; // @[CacheCork.scala:112:23, :113:33] assign c_d_bits_size = c_d_bits_d_size; // @[Edges.scala:677:17] assign c_d_bits_source = c_d_bits_d_source; // @[Edges.scala:677:17] assign _nodeIn_c_ready_T_1 = _nodeIn_c_ready_T ? c_d_ready : c_a_ready; // @[CacheCork.scala:101:23, :112:23, :117:{26,44}] assign nodeIn_c_ready = _nodeIn_c_ready_T_1; // @[CacheCork.scala:117:26] wire _in_d_ready_T_4; // @[CacheCork.scala:136:34] wire _in_d_valid_T_7; // @[Arbiter.scala:96:24] wire [2:0] _in_d_bits_WIRE_opcode; // @[Mux.scala:30:73] assign nodeIn_d_bits_opcode = in_d_bits_opcode; // @[CacheCork.scala:131:24] wire [1:0] _in_d_bits_WIRE_param; // @[Mux.scala:30:73] assign nodeIn_d_bits_param = in_d_bits_param; // @[CacheCork.scala:131:24] wire [2:0] _in_d_bits_WIRE_size; // @[Mux.scala:30:73] assign nodeIn_d_bits_size = in_d_bits_size; // @[CacheCork.scala:131:24] wire [4:0] _in_d_bits_WIRE_source; // @[Mux.scala:30:73] assign nodeIn_d_bits_source = in_d_bits_source; // @[CacheCork.scala:131:24] wire [2:0] _in_d_bits_WIRE_sink; // @[Mux.scala:30:73] wire _in_d_bits_WIRE_denied; // @[Mux.scala:30:73] assign nodeIn_d_bits_denied = in_d_bits_denied; // @[CacheCork.scala:131:24] wire [63:0] _in_d_bits_WIRE_data; // @[Mux.scala:30:73] assign nodeIn_d_bits_data = in_d_bits_data; // @[CacheCork.scala:131:24] wire _in_d_bits_WIRE_corrupt; // @[Mux.scala:30:73] assign nodeIn_d_bits_corrupt = in_d_bits_corrupt; // @[CacheCork.scala:131:24] wire [2:0] in_d_bits_sink; // @[CacheCork.scala:131:24] wire in_d_ready; // @[CacheCork.scala:131:24] wire in_d_valid; // @[CacheCork.scala:131:24] wire _GEN_0 = in_d_ready & in_d_valid; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _GEN_0; // @[Decoupled.scala:51:35] wire _beatsLeft_T_4; // @[Decoupled.scala:51:35] assign _beatsLeft_T_4 = _GEN_0; // @[Decoupled.scala:51:35] wire [12:0] _d_first_beats1_decode_T = 13'h3F << in_d_bits_size; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = in_d_bits_opcode[0]; // @[Edges.scala:106:36] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire _d_grant_T = in_d_bits_opcode == 3'h5; // @[CacheCork.scala:131:24, :133:40] wire _d_grant_T_1 = in_d_bits_opcode == 3'h4; // @[CacheCork.scala:131:24, :133:74] wire d_grant = _d_grant_T | _d_grant_T_1; // @[CacheCork.scala:133:{40,54,74}] wire _pool_io_alloc_ready_T = nodeIn_d_ready & nodeIn_d_valid; // @[Decoupled.scala:51:35] wire _pool_io_alloc_ready_T_1 = _pool_io_alloc_ready_T & d_first; // @[Decoupled.scala:51:35] wire _pool_io_alloc_ready_T_2 = _pool_io_alloc_ready_T_1 & d_grant; // @[CacheCork.scala:133:54, :134:{42,53}] wire _nodeIn_d_valid_T = ~d_first; // @[Edges.scala:231:25] wire _nodeIn_d_valid_T_1 = _pool_io_alloc_valid | _nodeIn_d_valid_T; // @[CacheCork.scala:127:26, :135:{58,61}] wire _nodeIn_d_valid_T_2 = ~d_grant; // @[CacheCork.scala:133:54, :135:73] wire _nodeIn_d_valid_T_3 = _nodeIn_d_valid_T_1 | _nodeIn_d_valid_T_2; // @[CacheCork.scala:135:{58,70,73}] assign _nodeIn_d_valid_T_4 = in_d_valid & _nodeIn_d_valid_T_3; // @[CacheCork.scala:131:24, :135:{34,70}] assign nodeIn_d_valid = _nodeIn_d_valid_T_4; // @[CacheCork.scala:135:34] wire _in_d_ready_T = ~d_first; // @[Edges.scala:231:25] wire _in_d_ready_T_1 = _pool_io_alloc_valid | _in_d_ready_T; // @[CacheCork.scala:127:26, :136:{58,61}] wire _in_d_ready_T_2 = ~d_grant; // @[CacheCork.scala:133:54, :135:73, :136:73] wire _in_d_ready_T_3 = _in_d_ready_T_1 | _in_d_ready_T_2; // @[CacheCork.scala:136:{58,70,73}] assign _in_d_ready_T_4 = nodeIn_d_ready & _in_d_ready_T_3; // @[CacheCork.scala:136:{34,70}] assign in_d_ready = _in_d_ready_T_4; // @[CacheCork.scala:131:24, :136:34] reg [2:0] nodeIn_d_bits_sink_r; // @[package.scala:88:63] assign _nodeIn_d_bits_sink_T = d_first ? _pool_io_alloc_bits : nodeIn_d_bits_sink_r; // @[package.scala:88:{42,63}] assign nodeIn_d_bits_sink = _nodeIn_d_bits_sink_T; // @[package.scala:88:42] wire _d_d_ready_T; // @[Arbiter.scala:94:31] assign nodeOut_d_ready = d_d_ready; // @[CacheCork.scala:141:23] wire [4:0] _d_d_bits_source_T; // @[CacheCork.scala:143:46] wire [2:0] d_d_bits_opcode; // @[CacheCork.scala:141:23] wire [1:0] d_d_bits_param; // @[CacheCork.scala:141:23] wire [4:0] d_d_bits_source; // @[CacheCork.scala:141:23] wire [2:0] d_d_bits_sink; // @[CacheCork.scala:141:23] assign d_d_bits_sink = {2'h0, nodeOut_d_bits_sink}; // @[CacheCork.scala:141:23, :142:13] assign _d_d_bits_source_T = nodeOut_d_bits_source[5:1]; // @[CacheCork.scala:143:46] assign d_d_bits_source = _d_d_bits_source_T; // @[CacheCork.scala:141:23, :143:46] wire [32:0] _aWOk_T_1 = {1'h0, _aWOk_T}; // @[Parameters.scala:137:{31,41}] wire _bypass_T_1 = nodeIn_a_bits_source == d_d_bits_source; // @[CacheCork.scala:141:23, :150:91] reg dWHeld_r; // @[package.scala:88:63] wire dWHeld = d_first ? _dWHeld_T : dWHeld_r; // @[package.scala:88:{42,63}] wire _T_18 = nodeOut_d_bits_opcode == 3'h1 & nodeOut_d_bits_source[0]; // @[CacheCork.scala:162:{33,51,71}] wire [1:0] _d_d_bits_param_T = {1'h0, ~dWHeld}; // @[package.scala:88:42] assign d_d_bits_param = _T_18 ? _d_d_bits_param_T : nodeOut_d_bits_param; // @[CacheCork.scala:141:23, :142:13, :162:{51,76}, :164:{26,32}] assign d_d_bits_opcode = nodeOut_d_bits_opcode == 3'h0 & ~(nodeOut_d_bits_source[0]) ? 3'h6 : _T_18 ? 3'h5 : nodeOut_d_bits_opcode; // @[CacheCork.scala:141:23, :142:13, :162:{51,71,76}, :163:27, :166:{33,47,50,73}, :167:27] wire [12:0] _decode_T = 13'h3F << c_a_bits_size; // @[package.scala:243:71] wire [5:0] _decode_T_1 = _decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _decode_T_2 = ~_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] decode = _decode_T_2[5:3]; // @[package.scala:243:46] wire [12:0] _decode_T_3 = 13'h3F << a_a_bits_size; // @[package.scala:243:71] wire [5:0] _decode_T_4 = _decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _decode_T_5 = ~_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] decode_1 = _decode_T_5[5:3]; // @[package.scala:243:46] wire _opdata_T_1 = a_a_bits_opcode[2]; // @[Edges.scala:92:37] wire opdata_1 = ~_opdata_T_1; // @[Edges.scala:92:{28,37}] reg [2:0] beatsLeft; // @[Arbiter.scala:60:30] wire idle = beatsLeft == 3'h0; // @[Arbiter.scala:60:30, :61:28] wire latch = idle & nodeOut_a_ready; // @[Arbiter.scala:61:28, :62:24] wire [1:0] _readys_T = {a_a_valid, c_a_valid}; // @[CacheCork.scala:74:23, :101:23] wire [2:0] _readys_T_1 = {_readys_T, 1'h0}; // @[package.scala:253:48] wire [1:0] _readys_T_2 = _readys_T_1[1:0]; // @[package.scala:253:{48,53}] wire [1:0] _readys_T_3 = _readys_T | _readys_T_2; // @[package.scala:253:{43,53}] wire [1:0] _readys_T_4 = _readys_T_3; // @[package.scala:253:43, :254:17] wire [2:0] _readys_T_5 = {_readys_T_4, 1'h0}; // @[package.scala:254:17] wire [1:0] _readys_T_6 = _readys_T_5[1:0]; // @[Arbiter.scala:16:{78,83}] wire [1:0] _readys_T_7 = ~_readys_T_6; // @[Arbiter.scala:16:{61,83}] wire _readys_T_8 = _readys_T_7[0]; // @[Arbiter.scala:16:61, :68:76] wire readys_0 = _readys_T_8; // @[Arbiter.scala:68:{27,76}] wire _readys_T_9 = _readys_T_7[1]; // @[Arbiter.scala:16:61, :68:76] wire readys_1 = _readys_T_9; // @[Arbiter.scala:68:{27,76}] wire _winner_T = readys_0 & c_a_valid; // @[CacheCork.scala:101:23] wire winner_0 = _winner_T; // @[Arbiter.scala:71:{27,69}] wire _winner_T_1 = readys_1 & a_a_valid; // @[CacheCork.scala:74:23] wire winner_1 = _winner_T_1; // @[Arbiter.scala:71:{27,69}] wire prefixOR_1 = winner_0; // @[Arbiter.scala:71:27, :76:48] wire _prefixOR_T = prefixOR_1 | winner_1; // @[Arbiter.scala:71:27, :76:48] wire _nodeOut_a_valid_T = c_a_valid | a_a_valid; // @[CacheCork.scala:74:23, :101:23] wire [2:0] maskedBeats_0 = winner_0 ? decode : 3'h0; // @[Edges.scala:220:59, :221:14] wire [2:0] maskedBeats_1 = winner_1 & opdata_1 ? decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] wire [2:0] initBeats = maskedBeats_0 | maskedBeats_1; // @[Arbiter.scala:82:69, :84:44] wire _beatsLeft_T = nodeOut_a_ready & nodeOut_a_valid; // @[Decoupled.scala:51:35] wire [3:0] _beatsLeft_T_1 = {1'h0, beatsLeft} - {3'h0, _beatsLeft_T}; // @[Decoupled.scala:51:35] wire [2:0] _beatsLeft_T_2 = _beatsLeft_T_1[2:0]; // @[Arbiter.scala:85:52] wire [2:0] _beatsLeft_T_3 = latch ? initBeats : _beatsLeft_T_2; // @[Arbiter.scala:62:24, :84:44, :85:{23,52}] reg state_0; // @[Arbiter.scala:88:26] reg state_1; // @[Arbiter.scala:88:26] wire muxState_0 = idle ? winner_0 : state_0; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire muxState_1 = idle ? winner_1 : state_1; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire allowed_0 = idle ? readys_0 : state_0; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] wire allowed_1 = idle ? readys_1 : state_1; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] assign _c_a_ready_T = nodeOut_a_ready & allowed_0; // @[Arbiter.scala:92:24, :94:31] assign c_a_ready = _c_a_ready_T; // @[CacheCork.scala:101:23] assign _a_a_ready_T = nodeOut_a_ready & allowed_1; // @[Arbiter.scala:92:24, :94:31] assign a_a_ready = _a_a_ready_T; // @[CacheCork.scala:74:23] wire _nodeOut_a_valid_T_1 = state_0 & c_a_valid; // @[Mux.scala:30:73] wire _nodeOut_a_valid_T_2 = state_1 & a_a_valid; // @[Mux.scala:30:73] wire _nodeOut_a_valid_T_3 = _nodeOut_a_valid_T_1 | _nodeOut_a_valid_T_2; // @[Mux.scala:30:73] wire _nodeOut_a_valid_WIRE = _nodeOut_a_valid_T_3; // @[Mux.scala:30:73] assign _nodeOut_a_valid_T_4 = idle ? _nodeOut_a_valid_T : _nodeOut_a_valid_WIRE; // @[Mux.scala:30:73] assign nodeOut_a_valid = _nodeOut_a_valid_T_4; // @[Arbiter.scala:96:24] wire [2:0] _nodeOut_a_bits_WIRE_10; // @[Mux.scala:30:73] assign nodeOut_a_bits_opcode = _nodeOut_a_bits_WIRE_opcode; // @[Mux.scala:30:73] wire [2:0] _nodeOut_a_bits_WIRE_9; // @[Mux.scala:30:73] assign nodeOut_a_bits_param = _nodeOut_a_bits_WIRE_param; // @[Mux.scala:30:73] wire [2:0] _nodeOut_a_bits_WIRE_8; // @[Mux.scala:30:73] assign nodeOut_a_bits_size = _nodeOut_a_bits_WIRE_size; // @[Mux.scala:30:73] wire [5:0] _nodeOut_a_bits_WIRE_7; // @[Mux.scala:30:73] assign nodeOut_a_bits_source = _nodeOut_a_bits_WIRE_source; // @[Mux.scala:30:73] wire [31:0] _nodeOut_a_bits_WIRE_6; // @[Mux.scala:30:73] assign nodeOut_a_bits_address = _nodeOut_a_bits_WIRE_address; // @[Mux.scala:30:73] wire [7:0] _nodeOut_a_bits_WIRE_3; // @[Mux.scala:30:73] assign nodeOut_a_bits_mask = _nodeOut_a_bits_WIRE_mask; // @[Mux.scala:30:73] wire [63:0] _nodeOut_a_bits_WIRE_2; // @[Mux.scala:30:73] assign nodeOut_a_bits_data = _nodeOut_a_bits_WIRE_data; // @[Mux.scala:30:73] wire _nodeOut_a_bits_WIRE_1; // @[Mux.scala:30:73] assign nodeOut_a_bits_corrupt = _nodeOut_a_bits_WIRE_corrupt; // @[Mux.scala:30:73] wire _nodeOut_a_bits_T = muxState_0 & c_a_bits_corrupt; // @[Mux.scala:30:73] wire _nodeOut_a_bits_T_1 = muxState_1 & a_a_bits_corrupt; // @[Mux.scala:30:73] wire _nodeOut_a_bits_T_2 = _nodeOut_a_bits_T | _nodeOut_a_bits_T_1; // @[Mux.scala:30:73] assign _nodeOut_a_bits_WIRE_1 = _nodeOut_a_bits_T_2; // @[Mux.scala:30:73] assign _nodeOut_a_bits_WIRE_corrupt = _nodeOut_a_bits_WIRE_1; // @[Mux.scala:30:73] wire [63:0] _nodeOut_a_bits_T_3 = muxState_0 ? c_a_bits_data : 64'h0; // @[Mux.scala:30:73] wire [63:0] _nodeOut_a_bits_T_4 = muxState_1 ? a_a_bits_data : 64'h0; // @[Mux.scala:30:73] wire [63:0] _nodeOut_a_bits_T_5 = _nodeOut_a_bits_T_3 | _nodeOut_a_bits_T_4; // @[Mux.scala:30:73] assign _nodeOut_a_bits_WIRE_2 = _nodeOut_a_bits_T_5; // @[Mux.scala:30:73] assign _nodeOut_a_bits_WIRE_data = _nodeOut_a_bits_WIRE_2; // @[Mux.scala:30:73] wire [7:0] _nodeOut_a_bits_T_6 = muxState_0 ? c_a_bits_mask : 8'h0; // @[Mux.scala:30:73] wire [7:0] _nodeOut_a_bits_T_7 = muxState_1 ? a_a_bits_mask : 8'h0; // @[Mux.scala:30:73] wire [7:0] _nodeOut_a_bits_T_8 = _nodeOut_a_bits_T_6 | _nodeOut_a_bits_T_7; // @[Mux.scala:30:73] assign _nodeOut_a_bits_WIRE_3 = _nodeOut_a_bits_T_8; // @[Mux.scala:30:73] assign _nodeOut_a_bits_WIRE_mask = _nodeOut_a_bits_WIRE_3; // @[Mux.scala:30:73] wire [31:0] _nodeOut_a_bits_T_9 = muxState_0 ? c_a_bits_address : 32'h0; // @[Mux.scala:30:73] wire [31:0] _nodeOut_a_bits_T_10 = muxState_1 ? a_a_bits_address : 32'h0; // @[Mux.scala:30:73] wire [31:0] _nodeOut_a_bits_T_11 = _nodeOut_a_bits_T_9 | _nodeOut_a_bits_T_10; // @[Mux.scala:30:73] assign _nodeOut_a_bits_WIRE_6 = _nodeOut_a_bits_T_11; // @[Mux.scala:30:73] assign _nodeOut_a_bits_WIRE_address = _nodeOut_a_bits_WIRE_6; // @[Mux.scala:30:73] wire [5:0] _nodeOut_a_bits_T_12 = muxState_0 ? c_a_bits_source : 6'h0; // @[Mux.scala:30:73] wire [5:0] _nodeOut_a_bits_T_13 = muxState_1 ? a_a_bits_source : 6'h0; // @[Mux.scala:30:73] wire [5:0] _nodeOut_a_bits_T_14 = _nodeOut_a_bits_T_12 | _nodeOut_a_bits_T_13; // @[Mux.scala:30:73] assign _nodeOut_a_bits_WIRE_7 = _nodeOut_a_bits_T_14; // @[Mux.scala:30:73] assign _nodeOut_a_bits_WIRE_source = _nodeOut_a_bits_WIRE_7; // @[Mux.scala:30:73] wire [2:0] _nodeOut_a_bits_T_15 = muxState_0 ? c_a_bits_size : 3'h0; // @[Mux.scala:30:73] wire [2:0] _nodeOut_a_bits_T_16 = muxState_1 ? a_a_bits_size : 3'h0; // @[Mux.scala:30:73] wire [2:0] _nodeOut_a_bits_T_17 = _nodeOut_a_bits_T_15 | _nodeOut_a_bits_T_16; // @[Mux.scala:30:73] assign _nodeOut_a_bits_WIRE_8 = _nodeOut_a_bits_T_17; // @[Mux.scala:30:73] assign _nodeOut_a_bits_WIRE_size = _nodeOut_a_bits_WIRE_8; // @[Mux.scala:30:73] wire [2:0] _nodeOut_a_bits_T_19 = muxState_1 ? a_a_bits_param : 3'h0; // @[Mux.scala:30:73] wire [2:0] _nodeOut_a_bits_T_20 = _nodeOut_a_bits_T_19; // @[Mux.scala:30:73] assign _nodeOut_a_bits_WIRE_9 = _nodeOut_a_bits_T_20; // @[Mux.scala:30:73] assign _nodeOut_a_bits_WIRE_param = _nodeOut_a_bits_WIRE_9; // @[Mux.scala:30:73] wire [2:0] _nodeOut_a_bits_T_22 = muxState_1 ? a_a_bits_opcode : 3'h0; // @[Mux.scala:30:73] wire [2:0] _nodeOut_a_bits_T_23 = _nodeOut_a_bits_T_22; // @[Mux.scala:30:73] assign _nodeOut_a_bits_WIRE_10 = _nodeOut_a_bits_T_23; // @[Mux.scala:30:73] assign _nodeOut_a_bits_WIRE_opcode = _nodeOut_a_bits_WIRE_10; // @[Mux.scala:30:73] wire [12:0] _decode_T_6 = 13'h3F << d_d_bits_size; // @[package.scala:243:71] wire [5:0] _decode_T_7 = _decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _decode_T_8 = ~_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] decode_2 = _decode_T_8[5:3]; // @[package.scala:243:46] wire opdata_2 = d_d_bits_opcode[0]; // @[Edges.scala:106:36] reg [2:0] beatsLeft_1; // @[Arbiter.scala:60:30] wire idle_1 = beatsLeft_1 == 3'h0; // @[Arbiter.scala:60:30, :61:28] wire latch_1 = idle_1 & in_d_ready; // @[CacheCork.scala:131:24] wire [1:0] readys_hi = {_q_1_io_deq_valid, _q_io_deq_valid}; // @[Decoupled.scala:362:21] wire [2:0] _readys_T_10 = {readys_hi, d_d_valid}; // @[CacheCork.scala:141:23] wire [3:0] _readys_T_11 = {_readys_T_10, 1'h0}; // @[package.scala:253:48] wire [2:0] _readys_T_12 = _readys_T_11[2:0]; // @[package.scala:253:{48,53}] wire [2:0] _readys_T_13 = _readys_T_10 | _readys_T_12; // @[package.scala:253:{43,53}] wire [4:0] _readys_T_14 = {_readys_T_13, 2'h0}; // @[package.scala:253:{43,48}] wire [2:0] _readys_T_15 = _readys_T_14[2:0]; // @[package.scala:253:{48,53}] wire [2:0] _readys_T_16 = _readys_T_13 | _readys_T_15; // @[package.scala:253:{43,53}] wire [2:0] _readys_T_17 = _readys_T_16; // @[package.scala:253:43, :254:17] wire [3:0] _readys_T_18 = {_readys_T_17, 1'h0}; // @[package.scala:254:17] wire [2:0] _readys_T_19 = _readys_T_18[2:0]; // @[Arbiter.scala:16:{78,83}] wire [2:0] _readys_T_20 = ~_readys_T_19; // @[Arbiter.scala:16:{61,83}] wire _readys_T_21 = _readys_T_20[0]; // @[Arbiter.scala:16:61, :68:76] wire readys_1_0 = _readys_T_21; // @[Arbiter.scala:68:{27,76}] wire _readys_T_22 = _readys_T_20[1]; // @[Arbiter.scala:16:61, :68:76] wire readys_1_1 = _readys_T_22; // @[Arbiter.scala:68:{27,76}] wire _readys_T_23 = _readys_T_20[2]; // @[Arbiter.scala:16:61, :68:76] wire readys_1_2 = _readys_T_23; // @[Arbiter.scala:68:{27,76}] wire _winner_T_2 = readys_1_0 & d_d_valid; // @[CacheCork.scala:141:23] wire winner_1_0 = _winner_T_2; // @[Arbiter.scala:71:{27,69}] wire _winner_T_3 = readys_1_1 & _q_io_deq_valid; // @[Decoupled.scala:362:21] wire winner_1_1 = _winner_T_3; // @[Arbiter.scala:71:{27,69}] wire _winner_T_4 = readys_1_2 & _q_1_io_deq_valid; // @[Decoupled.scala:362:21] wire winner_1_2 = _winner_T_4; // @[Arbiter.scala:71:{27,69}] wire prefixOR_1_1 = winner_1_0; // @[Arbiter.scala:71:27, :76:48] wire prefixOR_2 = prefixOR_1_1 | winner_1_1; // @[Arbiter.scala:71:27, :76:48] wire _prefixOR_T_1 = prefixOR_2 | winner_1_2; // @[Arbiter.scala:71:27, :76:48] wire _in_d_valid_T = d_d_valid | _q_io_deq_valid; // @[Decoupled.scala:362:21]

Generate the Verilog code corresponding to the following Chisel files. File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File Nodes.scala: package constellation.channel import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Parameters, Field} import freechips.rocketchip.diplomacy._ case class EmptyParams() case class ChannelEdgeParams(cp: ChannelParams, p: Parameters) object ChannelImp extends SimpleNodeImp[EmptyParams, ChannelParams, ChannelEdgeParams, Channel] { def edge(pd: EmptyParams, pu: ChannelParams, p: Parameters, sourceInfo: SourceInfo) = { ChannelEdgeParams(pu, p) } def bundle(e: ChannelEdgeParams) = new Channel(e.cp)(e.p) def render(e: ChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) { RenderedEdge(colour = "ffffff", label = "X") } else { RenderedEdge(colour = "#0000ff", label = e.cp.payloadBits.toString) } override def monitor(bundle: Channel, edge: ChannelEdgeParams): Unit = { val monitor = Module(new NoCMonitor(edge.cp)(edge.p)) monitor.io.in := bundle } // TODO: Add nodepath stuff? override def mixO, override def mixI } case class ChannelSourceNode(val destId: Int)(implicit valName: ValName) extends SourceNode(ChannelImp)(Seq(EmptyParams())) case class ChannelDestNode(val destParams: ChannelParams)(implicit valName: ValName) extends SinkNode(ChannelImp)(Seq(destParams)) case class ChannelAdapterNode( slaveFn: ChannelParams => ChannelParams = { d => d })( implicit valName: ValName) extends AdapterNode(ChannelImp)((e: EmptyParams) => e, slaveFn) case class ChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(ChannelImp)() case class ChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(ChannelImp)() case class IngressChannelEdgeParams(cp: IngressChannelParams, p: Parameters) case class EgressChannelEdgeParams(cp: EgressChannelParams, p: Parameters) object IngressChannelImp extends SimpleNodeImp[EmptyParams, IngressChannelParams, IngressChannelEdgeParams, IngressChannel] { def edge(pd: EmptyParams, pu: IngressChannelParams, p: Parameters, sourceInfo: SourceInfo) = { IngressChannelEdgeParams(pu, p) } def bundle(e: IngressChannelEdgeParams) = new IngressChannel(e.cp)(e.p) def render(e: IngressChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) { RenderedEdge(colour = "ffffff", label = "X") } else { RenderedEdge(colour = "#00ff00", label = e.cp.payloadBits.toString) } } object EgressChannelImp extends SimpleNodeImp[EmptyParams, EgressChannelParams, EgressChannelEdgeParams, EgressChannel] { def edge(pd: EmptyParams, pu: EgressChannelParams, p: Parameters, sourceInfo: SourceInfo) = { EgressChannelEdgeParams(pu, p) } def bundle(e: EgressChannelEdgeParams) = new EgressChannel(e.cp)(e.p) def render(e: EgressChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) { RenderedEdge(colour = "ffffff", label = "X") } else { RenderedEdge(colour = "#ff0000", label = e.cp.payloadBits.toString) } } case class IngressChannelSourceNode(val destId: Int)(implicit valName: ValName) extends SourceNode(IngressChannelImp)(Seq(EmptyParams())) case class IngressChannelDestNode(val destParams: IngressChannelParams)(implicit valName: ValName) extends SinkNode(IngressChannelImp)(Seq(destParams)) case class EgressChannelSourceNode(val egressId: Int)(implicit valName: ValName) extends SourceNode(EgressChannelImp)(Seq(EmptyParams())) case class EgressChannelDestNode(val destParams: EgressChannelParams)(implicit valName: ValName) extends SinkNode(EgressChannelImp)(Seq(destParams)) case class IngressChannelAdapterNode( slaveFn: IngressChannelParams => IngressChannelParams = { d => d })( implicit valName: ValName) extends AdapterNode(IngressChannelImp)(m => m, slaveFn) case class EgressChannelAdapterNode( slaveFn: EgressChannelParams => EgressChannelParams = { d => d })( implicit valName: ValName) extends AdapterNode(EgressChannelImp)(m => m, slaveFn) case class IngressChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(IngressChannelImp)() case class EgressChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(EgressChannelImp)() case class IngressChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(IngressChannelImp)() case class EgressChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(EgressChannelImp)() File Router.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{RoutingRelation} import constellation.noc.{HasNoCParams} case class UserRouterParams( // Payload width. Must match payload width on all channels attached to this routing node payloadBits: Int = 64, // Combines SA and ST stages (removes pipeline register) combineSAST: Boolean = false, // Combines RC and VA stages (removes pipeline register) combineRCVA: Boolean = false, // Adds combinational path from SA to VA coupleSAVA: Boolean = false, vcAllocator: VCAllocatorParams => Parameters => VCAllocator = (vP) => (p) => new RotatingSingleVCAllocator(vP)(p) ) case class RouterParams( nodeId: Int, nIngress: Int, nEgress: Int, user: UserRouterParams ) trait HasRouterOutputParams { def outParams: Seq[ChannelParams] def egressParams: Seq[EgressChannelParams] def allOutParams = outParams ++ egressParams def nOutputs = outParams.size def nEgress = egressParams.size def nAllOutputs = allOutParams.size } trait HasRouterInputParams { def inParams: Seq[ChannelParams] def ingressParams: Seq[IngressChannelParams] def allInParams = inParams ++ ingressParams def nInputs = inParams.size def nIngress = ingressParams.size def nAllInputs = allInParams.size } trait HasRouterParams { def routerParams: RouterParams def nodeId = routerParams.nodeId def payloadBits = routerParams.user.payloadBits } class DebugBundle(val nIn: Int) extends Bundle { val va_stall = Vec(nIn, UInt()) val sa_stall = Vec(nIn, UInt()) } class Router( val routerParams: RouterParams, preDiplomaticInParams: Seq[ChannelParams], preDiplomaticIngressParams: Seq[IngressChannelParams], outDests: Seq[Int], egressIds: Seq[Int] )(implicit p: Parameters) extends LazyModule with HasNoCParams with HasRouterParams { val allPreDiplomaticInParams = preDiplomaticInParams ++ preDiplomaticIngressParams val destNodes = preDiplomaticInParams.map(u => ChannelDestNode(u)) val sourceNodes = outDests.map(u => ChannelSourceNode(u)) val ingressNodes = preDiplomaticIngressParams.map(u => IngressChannelDestNode(u)) val egressNodes = egressIds.map(u => EgressChannelSourceNode(u)) val debugNode = BundleBridgeSource(() => new DebugBundle(allPreDiplomaticInParams.size)) val ctrlNode = if (hasCtrl) Some(BundleBridgeSource(() => new RouterCtrlBundle)) else None def inParams = module.inParams def outParams = module.outParams def ingressParams = module.ingressParams def egressParams = module.egressParams lazy val module = new LazyModuleImp(this) with HasRouterInputParams with HasRouterOutputParams { val (io_in, edgesIn) = destNodes.map(_.in(0)).unzip val (io_out, edgesOut) = sourceNodes.map(_.out(0)).unzip val (io_ingress, edgesIngress) = ingressNodes.map(_.in(0)).unzip val (io_egress, edgesEgress) = egressNodes.map(_.out(0)).unzip val io_debug = debugNode.out(0)._1 val inParams = edgesIn.map(_.cp) val outParams = edgesOut.map(_.cp) val ingressParams = edgesIngress.map(_.cp) val egressParams = edgesEgress.map(_.cp) allOutParams.foreach(u => require(u.srcId == nodeId && u.payloadBits == routerParams.user.payloadBits)) allInParams.foreach(u => require(u.destId == nodeId && u.payloadBits == routerParams.user.payloadBits)) require(nIngress == routerParams.nIngress) require(nEgress == routerParams.nEgress) require(nAllInputs >= 1) require(nAllOutputs >= 1) require(nodeId < (1 << nodeIdBits)) val input_units = inParams.zipWithIndex.map { case (u,i) => Module(new InputUnit(u, outParams, egressParams, routerParams.user.combineRCVA, routerParams.user.combineSAST)) .suggestName(s"input_unit_${i}_from_${u.srcId}") } val ingress_units = ingressParams.zipWithIndex.map { case (u,i) => Module(new IngressUnit(i, u, outParams, egressParams, routerParams.user.combineRCVA, routerParams.user.combineSAST)) .suggestName(s"ingress_unit_${i+nInputs}_from_${u.ingressId}") } val all_input_units = input_units ++ ingress_units val output_units = outParams.zipWithIndex.map { case (u,i) => Module(new OutputUnit(inParams, ingressParams, u)) .suggestName(s"output_unit_${i}_to_${u.destId}")} val egress_units = egressParams.zipWithIndex.map { case (u,i) => Module(new EgressUnit(routerParams.user.coupleSAVA && all_input_units.size == 1, routerParams.user.combineSAST, inParams, ingressParams, u)) .suggestName(s"egress_unit_${i+nOutputs}_to_${u.egressId}")} val all_output_units = output_units ++ egress_units val switch = Module(new Switch(routerParams, inParams, outParams, ingressParams, egressParams)) val switch_allocator = Module(new SwitchAllocator(routerParams, inParams, outParams, ingressParams, egressParams)) val vc_allocator = Module(routerParams.user.vcAllocator( VCAllocatorParams(routerParams, inParams, outParams, ingressParams, egressParams) )(p)) val route_computer = Module(new RouteComputer(routerParams, inParams, outParams, ingressParams, egressParams)) val fires_count = WireInit(PopCount(vc_allocator.io.req.map(_.fire))) dontTouch(fires_count) (io_in zip input_units ).foreach { case (i,u) => u.io.in <> i } (io_ingress zip ingress_units).foreach { case (i,u) => u.io.in <> i.flit } (output_units zip io_out ).foreach { case (u,o) => o <> u.io.out } (egress_units zip io_egress).foreach { case (u,o) => o.flit <> u.io.out } (route_computer.io.req zip all_input_units).foreach { case (i,u) => i <> u.io.router_req } (all_input_units zip route_computer.io.resp).foreach { case (u,o) => u.io.router_resp <> o } (vc_allocator.io.req zip all_input_units).foreach { case (i,u) => i <> u.io.vcalloc_req } (all_input_units zip vc_allocator.io.resp).foreach { case (u,o) => u.io.vcalloc_resp <> o } (all_output_units zip vc_allocator.io.out_allocs).foreach { case (u,a) => u.io.allocs <> a } (vc_allocator.io.channel_status zip all_output_units).foreach { case (a,u) => a := u.io.channel_status } all_input_units.foreach(in => all_output_units.zipWithIndex.foreach { case (out,outIdx) => in.io.out_credit_available(outIdx) := out.io.credit_available }) (all_input_units zip switch_allocator.io.req).foreach { case (u,r) => r <> u.io.salloc_req } (all_output_units zip switch_allocator.io.credit_alloc).foreach { case (u,a) => u.io.credit_alloc := a } (switch.io.in zip all_input_units).foreach { case (i,u) => i <> u.io.out } (all_output_units zip switch.io.out).foreach { case (u,o) => u.io.in <> o } switch.io.sel := (if (routerParams.user.combineSAST) { switch_allocator.io.switch_sel } else { RegNext(switch_allocator.io.switch_sel) }) if (hasCtrl) { val io_ctrl = ctrlNode.get.out(0)._1 val ctrl = Module(new RouterControlUnit(routerParams, inParams, outParams, ingressParams, egressParams)) io_ctrl <> ctrl.io.ctrl (all_input_units zip ctrl.io.in_block ).foreach { case (l,r) => l.io.block := r } (all_input_units zip ctrl.io.in_fire ).foreach { case (l,r) => r := l.io.out.map(_.valid) } } else { input_units.foreach(_.io.block := false.B) ingress_units.foreach(_.io.block := false.B) } (io_debug.va_stall zip all_input_units.map(_.io.debug.va_stall)).map { case (l,r) => l := r } (io_debug.sa_stall zip all_input_units.map(_.io.debug.sa_stall)).map { case (l,r) => l := r } val debug_tsc = RegInit(0.U(64.W)) debug_tsc := debug_tsc + 1.U val debug_sample = RegInit(0.U(64.W)) debug_sample := debug_sample + 1.U val sample_rate = PlusArg("noc_util_sample_rate", width=20) when (debug_sample === sample_rate - 1.U) { debug_sample := 0.U } def sample(fire: Bool, s: String) = { val util_ctr = RegInit(0.U(64.W)) val fired = RegInit(false.B) util_ctr := util_ctr + fire fired := fired || fire when (sample_rate =/= 0.U && debug_sample === sample_rate - 1.U && fired) { val fmtStr = s"nocsample %d $s %d\n" printf(fmtStr, debug_tsc, util_ctr); fired := fire } } destNodes.map(_.in(0)).foreach { case (in, edge) => in.flit.map { f => sample(f.fire, s"${edge.cp.srcId} $nodeId") } } ingressNodes.map(_.in(0)).foreach { case (in, edge) => sample(in.flit.fire, s"i${edge.cp.asInstanceOf[IngressChannelParams].ingressId} $nodeId") } egressNodes.map(_.out(0)).foreach { case (out, edge) => sample(out.flit.fire, s"$nodeId e${edge.cp.asInstanceOf[EgressChannelParams].egressId}") } } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } }

module Router_15( // @[Router.scala:89:25] input clock, // @[Router.scala:89:25] input reset, // @[Router.scala:89:25] output [2:0] auto_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_va_stall_3, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_sa_stall_3, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_3_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_3_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_3_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_source_nodes_out_3_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_3_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_3_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_3_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_3_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_3_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_3_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [7:0] auto_source_nodes_out_3_credit_return, // @[LazyModuleImp.scala:107:25] input [7:0] auto_source_nodes_out_3_vc_free, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_2_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_source_nodes_out_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [7:0] auto_source_nodes_out_2_credit_return, // @[LazyModuleImp.scala:107:25] input [7:0] auto_source_nodes_out_2_vc_free, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_source_nodes_out_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [7:0] auto_source_nodes_out_1_credit_return, // @[LazyModuleImp.scala:107:25] input [7:0] auto_source_nodes_out_1_vc_free, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_source_nodes_out_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [7:0] auto_source_nodes_out_0_credit_return, // @[LazyModuleImp.scala:107:25] input [7:0] auto_source_nodes_out_0_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_3_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_3_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_3_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_dest_nodes_in_3_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_3_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_3_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_3_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_3_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_3_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_3_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [7:0] auto_dest_nodes_in_3_credit_return, // @[LazyModuleImp.scala:107:25] output [7:0] auto_dest_nodes_in_3_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_2_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_dest_nodes_in_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [7:0] auto_dest_nodes_in_2_credit_return, // @[LazyModuleImp.scala:107:25] output [7:0] auto_dest_nodes_in_2_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_dest_nodes_in_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [7:0] auto_dest_nodes_in_1_credit_return, // @[LazyModuleImp.scala:107:25] output [7:0] auto_dest_nodes_in_1_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_dest_nodes_in_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [7:0] auto_dest_nodes_in_0_credit_return, // @[LazyModuleImp.scala:107:25] output [7:0] auto_dest_nodes_in_0_vc_free // @[LazyModuleImp.scala:107:25] ); wire [19:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire _route_computer_io_resp_3_vc_sel_2_1; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_2_2; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_2_3; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_2_4; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_2_5; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_2_6; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_2_7; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_1_1; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_1_2; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_1_3; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_1_4; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_1_5; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_1_6; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_1_7; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_0_1; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_0_2; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_0_3; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_0_4; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_0_5; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_0_6; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_0_7; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_3_0; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_3_1; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_3_2; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_3_3; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_3_4; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_3_5; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_3_6; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_3_7; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_1_1; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_1_2; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_1_3; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_1_4; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_1_5; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_1_6; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_1_7; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_1; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_2; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_3; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_4; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_5; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_6; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_7; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_3_4; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_3_5; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_3_6; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_3_7; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_2_4; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_2_5; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_2_6; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_2_7; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_3_0; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_3_1; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_3_2; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_3_3; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_3_4; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_3_5; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_3_6; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_3_7; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_2_0; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_2_1; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_2_2; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_2_3; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_2_4; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_2_5; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_2_6; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_2_7; // @[Router.scala:136:32] wire _vc_allocator_io_req_3_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_2_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_1_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_0_ready; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_2_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_2_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_2_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_2_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_2_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_2_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_2_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_1_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_1_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_1_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_1_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_1_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_1_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_1_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_3_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_3_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_3_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_3_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_3_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_3_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_3_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_3_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_1_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_1_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_1_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_1_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_1_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_1_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_1_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_3_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_3_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_3_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_3_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_2_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_2_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_2_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_2_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_3_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_3_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_3_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_3_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_3_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_3_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_3_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_3_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_2_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_2_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_2_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_2_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_2_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_2_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_2_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_2_7; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_3_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_3_1_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_3_2_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_3_3_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_3_4_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_3_5_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_3_6_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_3_7_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_1_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_2_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_3_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_4_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_5_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_6_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_7_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_1_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_2_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_3_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_4_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_5_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_6_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_7_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_1_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_2_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_3_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_4_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_5_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_6_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_7_alloc; // @[Router.scala:133:30] wire _switch_allocator_io_req_3_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_2_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_1_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_0_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_3_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_3_1_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_3_2_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_3_3_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_3_4_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_3_5_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_3_6_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_3_7_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_1_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_2_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_3_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_4_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_5_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_6_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_7_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_1_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_2_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_3_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_4_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_5_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_6_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_7_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_1_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_2_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_3_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_4_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_5_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_6_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_7_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_3_0_3_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_3_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_3_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_3_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_3_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_3_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_3_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_0_0; // @[Router.scala:132:34] wire _switch_io_out_3_0_valid; // @[Router.scala:131:24] wire _switch_io_out_3_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_3_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_3_0_bits_payload; // @[Router.scala:131:24] wire [2:0] _switch_io_out_3_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_3_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_3_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_3_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_3_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [2:0] _switch_io_out_3_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _switch_io_out_2_0_valid; // @[Router.scala:131:24] wire _switch_io_out_2_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_2_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_2_0_bits_payload; // @[Router.scala:131:24] wire [2:0] _switch_io_out_2_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_2_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_2_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_2_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_2_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [2:0] _switch_io_out_2_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _switch_io_out_1_0_valid; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_1_0_bits_payload; // @[Router.scala:131:24] wire [2:0] _switch_io_out_1_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_1_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_1_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_1_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_1_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [2:0] _switch_io_out_1_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _switch_io_out_0_0_valid; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_0_0_bits_payload; // @[Router.scala:131:24] wire [2:0] _switch_io_out_0_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_0_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_0_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_0_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_0_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [2:0] _switch_io_out_0_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _output_unit_3_to_21_io_credit_available_0; // @[Router.scala:122:13] wire _output_unit_3_to_21_io_credit_available_1; // @[Router.scala:122:13] wire _output_unit_3_to_21_io_credit_available_2; // @[Router.scala:122:13] wire _output_unit_3_to_21_io_credit_available_3; // @[Router.scala:122:13] wire _output_unit_3_to_21_io_credit_available_4; // @[Router.scala:122:13] wire _output_unit_3_to_21_io_credit_available_5; // @[Router.scala:122:13] wire _output_unit_3_to_21_io_credit_available_6; // @[Router.scala:122:13] wire _output_unit_3_to_21_io_credit_available_7; // @[Router.scala:122:13] wire _output_unit_3_to_21_io_channel_status_0_occupied; // @[Router.scala:122:13] wire _output_unit_3_to_21_io_channel_status_1_occupied; // @[Router.scala:122:13] wire _output_unit_3_to_21_io_channel_status_2_occupied; // @[Router.scala:122:13] wire _output_unit_3_to_21_io_channel_status_3_occupied; // @[Router.scala:122:13] wire _output_unit_3_to_21_io_channel_status_4_occupied; // @[Router.scala:122:13] wire _output_unit_3_to_21_io_channel_status_5_occupied; // @[Router.scala:122:13] wire _output_unit_3_to_21_io_channel_status_6_occupied; // @[Router.scala:122:13] wire _output_unit_3_to_21_io_channel_status_7_occupied; // @[Router.scala:122:13] wire _output_unit_2_to_18_io_credit_available_0; // @[Router.scala:122:13] wire _output_unit_2_to_18_io_credit_available_1; // @[Router.scala:122:13] wire _output_unit_2_to_18_io_credit_available_2; // @[Router.scala:122:13] wire _output_unit_2_to_18_io_credit_available_3; // @[Router.scala:122:13] wire _output_unit_2_to_18_io_credit_available_4; // @[Router.scala:122:13] wire _output_unit_2_to_18_io_credit_available_5; // @[Router.scala:122:13] wire _output_unit_2_to_18_io_credit_available_6; // @[Router.scala:122:13] wire _output_unit_2_to_18_io_credit_available_7; // @[Router.scala:122:13] wire _output_unit_2_to_18_io_channel_status_0_occupied; // @[Router.scala:122:13] wire _output_unit_2_to_18_io_channel_status_1_occupied; // @[Router.scala:122:13] wire _output_unit_2_to_18_io_channel_status_2_occupied; // @[Router.scala:122:13] wire _output_unit_2_to_18_io_channel_status_3_occupied; // @[Router.scala:122:13] wire _output_unit_2_to_18_io_channel_status_4_occupied; // @[Router.scala:122:13] wire _output_unit_2_to_18_io_channel_status_5_occupied; // @[Router.scala:122:13] wire _output_unit_2_to_18_io_channel_status_6_occupied; // @[Router.scala:122:13] wire _output_unit_2_to_18_io_channel_status_7_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_16_io_credit_available_1; // @[Router.scala:122:13] wire _output_unit_1_to_16_io_credit_available_2; // @[Router.scala:122:13] wire _output_unit_1_to_16_io_credit_available_3; // @[Router.scala:122:13] wire _output_unit_1_to_16_io_credit_available_4; // @[Router.scala:122:13] wire _output_unit_1_to_16_io_credit_available_5; // @[Router.scala:122:13] wire _output_unit_1_to_16_io_credit_available_6; // @[Router.scala:122:13] wire _output_unit_1_to_16_io_credit_available_7; // @[Router.scala:122:13] wire _output_unit_1_to_16_io_channel_status_1_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_16_io_channel_status_2_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_16_io_channel_status_3_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_16_io_channel_status_4_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_16_io_channel_status_5_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_16_io_channel_status_6_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_16_io_channel_status_7_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_1_io_credit_available_1; // @[Router.scala:122:13] wire _output_unit_0_to_1_io_credit_available_2; // @[Router.scala:122:13] wire _output_unit_0_to_1_io_credit_available_3; // @[Router.scala:122:13] wire _output_unit_0_to_1_io_credit_available_4; // @[Router.scala:122:13] wire _output_unit_0_to_1_io_credit_available_5; // @[Router.scala:122:13] wire _output_unit_0_to_1_io_credit_available_6; // @[Router.scala:122:13] wire _output_unit_0_to_1_io_credit_available_7; // @[Router.scala:122:13] wire _output_unit_0_to_1_io_channel_status_1_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_1_io_channel_status_2_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_1_io_channel_status_3_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_1_io_channel_status_4_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_1_io_channel_status_5_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_1_io_channel_status_6_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_1_io_channel_status_7_occupied; // @[Router.scala:122:13] wire [2:0] _input_unit_3_from_21_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire [2:0] _input_unit_3_from_21_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [4:0] _input_unit_3_from_21_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_3_from_21_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_3_from_21_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_3_from_21_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_vcalloc_req_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_vcalloc_req_bits_vc_sel_2_2; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_vcalloc_req_bits_vc_sel_2_3; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_vcalloc_req_bits_vc_sel_2_4; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_vcalloc_req_bits_vc_sel_2_5; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_vcalloc_req_bits_vc_sel_2_6; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_vcalloc_req_bits_vc_sel_2_7; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_vcalloc_req_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_vcalloc_req_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_vcalloc_req_bits_vc_sel_1_3; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_vcalloc_req_bits_vc_sel_1_4; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_vcalloc_req_bits_vc_sel_1_5; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_vcalloc_req_bits_vc_sel_1_6; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_vcalloc_req_bits_vc_sel_1_7; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_vcalloc_req_bits_vc_sel_0_4; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_vcalloc_req_bits_vc_sel_0_5; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_vcalloc_req_bits_vc_sel_0_6; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_vcalloc_req_bits_vc_sel_0_7; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_salloc_req_0_bits_vc_sel_3_1; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_salloc_req_0_bits_vc_sel_3_2; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_salloc_req_0_bits_vc_sel_3_3; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_salloc_req_0_bits_vc_sel_3_4; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_salloc_req_0_bits_vc_sel_3_5; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_salloc_req_0_bits_vc_sel_3_6; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_salloc_req_0_bits_vc_sel_3_7; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_salloc_req_0_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_salloc_req_0_bits_vc_sel_2_2; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_salloc_req_0_bits_vc_sel_2_3; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_salloc_req_0_bits_vc_sel_2_4; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_salloc_req_0_bits_vc_sel_2_5; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_salloc_req_0_bits_vc_sel_2_6; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_salloc_req_0_bits_vc_sel_2_7; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_salloc_req_0_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_salloc_req_0_bits_vc_sel_1_3; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_salloc_req_0_bits_vc_sel_1_4; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_salloc_req_0_bits_vc_sel_1_5; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_salloc_req_0_bits_vc_sel_1_6; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_salloc_req_0_bits_vc_sel_1_7; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_salloc_req_0_bits_vc_sel_0_6; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_salloc_req_0_bits_vc_sel_0_7; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_3_from_21_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [72:0] _input_unit_3_from_21_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [2:0] _input_unit_3_from_21_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [4:0] _input_unit_3_from_21_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_3_from_21_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_3_from_21_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_3_from_21_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [2:0] _input_unit_3_from_21_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [2:0] _input_unit_2_from_18_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire [2:0] _input_unit_2_from_18_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [4:0] _input_unit_2_from_18_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_2_from_18_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_2_from_18_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_2_from_18_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_vcalloc_req_bits_vc_sel_3_1; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_vcalloc_req_bits_vc_sel_3_2; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_vcalloc_req_bits_vc_sel_3_3; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_vcalloc_req_bits_vc_sel_3_4; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_vcalloc_req_bits_vc_sel_3_5; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_vcalloc_req_bits_vc_sel_3_6; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_vcalloc_req_bits_vc_sel_3_7; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_vcalloc_req_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_vcalloc_req_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_vcalloc_req_bits_vc_sel_1_3; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_vcalloc_req_bits_vc_sel_1_4; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_vcalloc_req_bits_vc_sel_1_5; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_vcalloc_req_bits_vc_sel_1_6; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_vcalloc_req_bits_vc_sel_1_7; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_vcalloc_req_bits_vc_sel_0_4; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_vcalloc_req_bits_vc_sel_0_5; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_vcalloc_req_bits_vc_sel_0_6; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_vcalloc_req_bits_vc_sel_0_7; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_salloc_req_0_bits_vc_sel_3_1; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_salloc_req_0_bits_vc_sel_3_2; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_salloc_req_0_bits_vc_sel_3_3; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_salloc_req_0_bits_vc_sel_3_4; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_salloc_req_0_bits_vc_sel_3_5; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_salloc_req_0_bits_vc_sel_3_6; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_salloc_req_0_bits_vc_sel_3_7; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_salloc_req_0_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_salloc_req_0_bits_vc_sel_2_2; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_salloc_req_0_bits_vc_sel_2_3; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_salloc_req_0_bits_vc_sel_2_4; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_salloc_req_0_bits_vc_sel_2_5; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_salloc_req_0_bits_vc_sel_2_6; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_salloc_req_0_bits_vc_sel_2_7; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_salloc_req_0_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_salloc_req_0_bits_vc_sel_1_3; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_salloc_req_0_bits_vc_sel_1_4; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_salloc_req_0_bits_vc_sel_1_5; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_salloc_req_0_bits_vc_sel_1_6; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_salloc_req_0_bits_vc_sel_1_7; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_salloc_req_0_bits_vc_sel_0_6; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_salloc_req_0_bits_vc_sel_0_7; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_2_from_18_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [72:0] _input_unit_2_from_18_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [2:0] _input_unit_2_from_18_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [4:0] _input_unit_2_from_18_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_2_from_18_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_2_from_18_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_2_from_18_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [2:0] _input_unit_2_from_18_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_16_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_16_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [4:0] _input_unit_1_from_16_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_16_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_1_from_16_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_16_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_vcalloc_req_bits_vc_sel_3_4; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_vcalloc_req_bits_vc_sel_3_5; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_vcalloc_req_bits_vc_sel_3_6; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_vcalloc_req_bits_vc_sel_3_7; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_vcalloc_req_bits_vc_sel_2_4; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_vcalloc_req_bits_vc_sel_2_5; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_vcalloc_req_bits_vc_sel_2_6; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_vcalloc_req_bits_vc_sel_2_7; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_salloc_req_0_bits_vc_sel_3_1; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_salloc_req_0_bits_vc_sel_3_2; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_salloc_req_0_bits_vc_sel_3_3; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_salloc_req_0_bits_vc_sel_3_4; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_salloc_req_0_bits_vc_sel_3_5; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_salloc_req_0_bits_vc_sel_3_6; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_salloc_req_0_bits_vc_sel_3_7; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_salloc_req_0_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_salloc_req_0_bits_vc_sel_2_2; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_salloc_req_0_bits_vc_sel_2_3; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_salloc_req_0_bits_vc_sel_2_4; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_salloc_req_0_bits_vc_sel_2_5; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_salloc_req_0_bits_vc_sel_2_6; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_salloc_req_0_bits_vc_sel_2_7; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_salloc_req_0_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_salloc_req_0_bits_vc_sel_1_3; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_salloc_req_0_bits_vc_sel_1_4; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_salloc_req_0_bits_vc_sel_1_5; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_salloc_req_0_bits_vc_sel_1_6; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_salloc_req_0_bits_vc_sel_1_7; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_salloc_req_0_bits_vc_sel_0_6; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_salloc_req_0_bits_vc_sel_0_7; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_1_from_16_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [72:0] _input_unit_1_from_16_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_16_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [4:0] _input_unit_1_from_16_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_16_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_1_from_16_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_16_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_16_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_1_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_1_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [4:0] _input_unit_0_from_1_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_1_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_0_from_1_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_1_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_vcalloc_req_bits_vc_sel_3_1; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_vcalloc_req_bits_vc_sel_3_2; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_vcalloc_req_bits_vc_sel_3_3; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_vcalloc_req_bits_vc_sel_3_4; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_vcalloc_req_bits_vc_sel_3_5; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_vcalloc_req_bits_vc_sel_3_6; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_vcalloc_req_bits_vc_sel_3_7; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_vcalloc_req_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_vcalloc_req_bits_vc_sel_2_2; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_vcalloc_req_bits_vc_sel_2_3; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_vcalloc_req_bits_vc_sel_2_4; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_vcalloc_req_bits_vc_sel_2_5; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_vcalloc_req_bits_vc_sel_2_6; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_vcalloc_req_bits_vc_sel_2_7; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_salloc_req_0_bits_vc_sel_3_1; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_salloc_req_0_bits_vc_sel_3_2; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_salloc_req_0_bits_vc_sel_3_3; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_salloc_req_0_bits_vc_sel_3_4; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_salloc_req_0_bits_vc_sel_3_5; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_salloc_req_0_bits_vc_sel_3_6; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_salloc_req_0_bits_vc_sel_3_7; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_salloc_req_0_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_salloc_req_0_bits_vc_sel_2_2; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_salloc_req_0_bits_vc_sel_2_3; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_salloc_req_0_bits_vc_sel_2_4; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_salloc_req_0_bits_vc_sel_2_5; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_salloc_req_0_bits_vc_sel_2_6; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_salloc_req_0_bits_vc_sel_2_7; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_salloc_req_0_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_salloc_req_0_bits_vc_sel_1_3; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_salloc_req_0_bits_vc_sel_1_4; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_salloc_req_0_bits_vc_sel_1_5; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_salloc_req_0_bits_vc_sel_1_6; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_salloc_req_0_bits_vc_sel_1_7; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_salloc_req_0_bits_vc_sel_0_6; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_salloc_req_0_bits_vc_sel_0_7; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [72:0] _input_unit_0_from_1_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_1_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [4:0] _input_unit_0_from_1_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_1_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_0_from_1_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_1_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_1_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [2:0] fires_count = {1'h0, {1'h0, _vc_allocator_io_req_0_ready & _input_unit_0_from_1_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_1_ready & _input_unit_1_from_16_io_vcalloc_req_valid}} + {1'h0, {1'h0, _vc_allocator_io_req_2_ready & _input_unit_2_from_18_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_3_ready & _input_unit_3_from_21_io_vcalloc_req_valid}}; // @[Decoupled.scala:51:35] reg REG_3_0_3_0; // @[Router.scala:178:14] reg REG_3_0_2_0; // @[Router.scala:178:14] reg REG_3_0_1_0; // @[Router.scala:178:14] reg REG_3_0_0_0; // @[Router.scala:178:14] reg REG_2_0_3_0; // @[Router.scala:178:14] reg REG_2_0_2_0; // @[Router.scala:178:14] reg REG_2_0_1_0; // @[Router.scala:178:14] reg REG_2_0_0_0; // @[Router.scala:178:14] reg REG_1_0_3_0; // @[Router.scala:178:14] reg REG_1_0_2_0; // @[Router.scala:178:14] reg REG_1_0_1_0; // @[Router.scala:178:14] reg REG_1_0_0_0; // @[Router.scala:178:14] reg REG_0_0_3_0; // @[Router.scala:178:14] reg REG_0_0_2_0; // @[Router.scala:178:14] reg REG_0_0_1_0; // @[Router.scala:178:14] reg REG_0_0_0_0; // @[Router.scala:178:14] reg [63:0] debug_tsc; // @[Router.scala:195:28] reg [63:0] debug_sample; // @[Router.scala:197:31] wire _GEN = debug_sample == {44'h0, _plusarg_reader_out - 20'h1}; // @[PlusArg.scala:80:11] reg [63:0] util_ctr; // @[Router.scala:203:29] reg fired; // @[Router.scala:204:26] wire _GEN_0 = (|_plusarg_reader_out) & _GEN; // @[PlusArg.scala:80:11] wire _GEN_1 = _GEN_0 & fired; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_1; // @[Router.scala:203:29] reg fired_1; // @[Router.scala:204:26] wire _GEN_2 = _GEN_0 & fired_1; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_2; // @[Router.scala:203:29] reg fired_2; // @[Router.scala:204:26] wire _GEN_3 = _GEN_0 & fired_2; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_3; // @[Router.scala:203:29] reg fired_3; // @[Router.scala:204:26] wire _GEN_4 = _GEN_0 & fired_3; // @[Router.scala:204:26, :207:{33,71}]

Generate the Verilog code corresponding to the following Chisel files. File RoundAnyRawFNToRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util.Fill import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundAnyRawFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int, options: Int ) extends RawModule { override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(inExpWidth, inSigWidth)) // (allowed exponent range has limits) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0) val effectiveInSigWidth = if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1 val neverUnderflows = ((options & (flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact) ) != 0) || (inExpWidth < outExpWidth) val neverOverflows = ((options & flRoundOpt_neverOverflows) != 0) || (inExpWidth < outExpWidth) val outNaNExp = BigInt(7)<<(outExpWidth - 2) val outInfExp = BigInt(6)<<(outExpWidth - 2) val outMaxFiniteExp = outInfExp - 1 val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2 val outMinNonzeroExp = outMinNormExp - outSigWidth + 1 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_near_even = (io.roundingMode === round_near_even) val roundingMode_minMag = (io.roundingMode === round_minMag) val roundingMode_min = (io.roundingMode === round_min) val roundingMode_max = (io.roundingMode === round_max) val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag) val roundingMode_odd = (io.roundingMode === round_odd) val roundMagUp = (roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sAdjustedExp = if (inExpWidth < outExpWidth) (io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S )(outExpWidth, 0).zext else if (inExpWidth == outExpWidth) io.in.sExp else io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S val adjustedSig = if (inSigWidth <= outSigWidth + 2) io.in.sig<<(outSigWidth - inSigWidth + 2) else (io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ## io.in.sig(inSigWidth - outSigWidth - 2, 0).orR ) val doShiftSigDown1 = if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2) val common_expOut = Wire(UInt((outExpWidth + 1).W)) val common_fractOut = Wire(UInt((outSigWidth - 1).W)) val common_overflow = Wire(Bool()) val common_totalUnderflow = Wire(Bool()) val common_underflow = Wire(Bool()) val common_inexact = Wire(Bool()) if ( neverOverflows && neverUnderflows && (effectiveInSigWidth <= outSigWidth) ) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1 common_fractOut := Mux(doShiftSigDown1, adjustedSig(outSigWidth + 1, 3), adjustedSig(outSigWidth, 2) ) common_overflow := false.B common_totalUnderflow := false.B common_underflow := false.B common_inexact := false.B } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundMask = if (neverUnderflows) 0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W) else (lowMask( sAdjustedExp(outExpWidth, 0), outMinNormExp - outSigWidth - 1, outMinNormExp ) | doShiftSigDown1) ## 3.U(2.W) val shiftedRoundMask = 0.U(1.W) ## roundMask>>1 val roundPosMask = ~shiftedRoundMask & roundMask val roundPosBit = (adjustedSig & roundPosMask).orR val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR val anyRound = roundPosBit || anyRoundExtra val roundIncr = ((roundingMode_near_even || roundingMode_near_maxMag) && roundPosBit) || (roundMagUp && anyRound) val roundedSig: Bits = Mux(roundIncr, (((adjustedSig | roundMask)>>2) +& 1.U) & ~Mux(roundingMode_near_even && roundPosBit && ! anyRoundExtra, roundMask>>1, 0.U((outSigWidth + 2).W) ), (adjustedSig & ~roundMask)>>2 | Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U) ) //*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //*** M.S. BIT OF SUBNORMAL SIG? val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext common_expOut := sRoundedExp(outExpWidth, 0) common_fractOut := Mux(doShiftSigDown1, roundedSig(outSigWidth - 1, 1), roundedSig(outSigWidth - 2, 0) ) common_overflow := (if (neverOverflows) false.B else //*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?: (sRoundedExp>>(outExpWidth - 1) >= 3.S)) common_totalUnderflow := (if (neverUnderflows) false.B else //*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?: (sRoundedExp < outMinNonzeroExp.S)) val unboundedRange_roundPosBit = Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1)) val unboundedRange_anyRound = (doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR val unboundedRange_roundIncr = ((roundingMode_near_even || roundingMode_near_maxMag) && unboundedRange_roundPosBit) || (roundMagUp && unboundedRange_anyRound) val roundCarry = Mux(doShiftSigDown1, roundedSig(outSigWidth + 1), roundedSig(outSigWidth) ) common_underflow := (if (neverUnderflows) false.B else common_totalUnderflow || //*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //*** M.S. BIT OF SUBNORMAL SIG? (anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) && Mux(doShiftSigDown1, roundMask(3), roundMask(2)) && ! ((io.detectTininess === tininess_afterRounding) && ! Mux(doShiftSigDown1, roundMask(4), roundMask(3) ) && roundCarry && roundPosBit && unboundedRange_roundIncr))) common_inexact := common_totalUnderflow || anyRound } //------------------------------------------------------------------------ //------------------------------------------------------------------------ val isNaNOut = io.invalidExc || io.in.isNaN val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero val overflow = commonCase && common_overflow val underflow = commonCase && common_underflow val inexact = overflow || (commonCase && common_inexact) val overflow_roundMagUp = roundingMode_near_even || roundingMode_near_maxMag || roundMagUp val pegMinNonzeroMagOut = commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd) val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp val notNaN_isInfOut = notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp) val signOut = Mux(isNaNOut, false.B, io.in.sign) val expOut = (common_expOut & ~Mux(io.in.isZero || common_totalUnderflow, (BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMinNonzeroMagOut, ~outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMaxFiniteMagOut, (BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W), 0.U ) & ~Mux(notNaN_isInfOut, (BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U )) | Mux(pegMinNonzeroMagOut, outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) | Mux(pegMaxFiniteMagOut, outMaxFiniteExp.U((outExpWidth + 1).W), 0.U ) | Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) | Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U) val fractOut = Mux(isNaNOut || io.in.isZero || common_totalUnderflow, Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U), common_fractOut ) | Fill(outSigWidth - 1, pegMaxFiniteMagOut) io.out := signOut ## expOut ## fractOut io.exceptionFlags := io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int) extends RawModule { override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(expWidth, sigWidth + 2)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( expWidth, sigWidth + 2, expWidth, sigWidth, options)) roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc roundAnyRawFNToRecFN.io.in := io.in roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags }

module RoundRawFNToRecFN_e8_s24_62( // @[RoundAnyRawFNToRecFN.scala:295:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_62 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15] .io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[RoundAnyRawFNToRecFN.scala:310:15] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{ AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry, IdRange, RegionType, TransferSizes } import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions} import freechips.rocketchip.util.{ AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase, CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct } import scala.math.max //These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel case class TLMasterToSlaveTransferSizes( // Supports both Acquire+Release of the following two sizes: acquireT: TransferSizes = TransferSizes.none, acquireB: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none) extends TLCommonTransferSizes { def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .intersect(rhs.acquireT), acquireB = acquireB .intersect(rhs.acquireB), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint)) def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .mincover(rhs.acquireT), acquireB = acquireB .mincover(rhs.acquireB), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint)) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(acquireT, "T"), str(acquireB, "B"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""acquireT = ${acquireT} |acquireB = ${acquireB} |arithmetic = ${arithmetic} |logical = ${logical} |get = ${get} |putFull = ${putFull} |putPartial = ${putPartial} |hint = ${hint} | |""".stripMargin } } object TLMasterToSlaveTransferSizes { def unknownEmits = TLMasterToSlaveTransferSizes( acquireT = TransferSizes(1, 4096), acquireB = TransferSizes(1, 4096), arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096)) def unknownSupports = TLMasterToSlaveTransferSizes() } //These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel case class TLSlaveToMasterTransferSizes( probe: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none ) extends TLCommonTransferSizes { def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .intersect(rhs.probe), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint) ) def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .mincover(rhs.probe), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint) ) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(probe, "P"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""probe = ${probe} |arithmetic = ${arithmetic} |logical = ${logical} |get = ${get} |putFull = ${putFull} |putPartial = ${putPartial} |hint = ${hint} | |""".stripMargin } } object TLSlaveToMasterTransferSizes { def unknownEmits = TLSlaveToMasterTransferSizes( arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096), probe = TransferSizes(1, 4096)) def unknownSupports = TLSlaveToMasterTransferSizes() } trait TLCommonTransferSizes { def arithmetic: TransferSizes def logical: TransferSizes def get: TransferSizes def putFull: TransferSizes def putPartial: TransferSizes def hint: TransferSizes } class TLSlaveParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], setName: Option[String], val address: Seq[AddressSet], val regionType: RegionType.T, val executable: Boolean, val fifoId: Option[Int], val supports: TLMasterToSlaveTransferSizes, val emits: TLSlaveToMasterTransferSizes, // By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation) val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData // If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order // Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck // ReleaseAck may NEVER be denied extends SimpleProduct { def sortedAddress = address.sorted override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters] override def productPrefix = "TLSlaveParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 11 def productElement(n: Int): Any = n match { case 0 => name case 1 => address case 2 => resources case 3 => regionType case 4 => executable case 5 => fifoId case 6 => supports case 7 => emits case 8 => alwaysGrantsT case 9 => mayDenyGet case 10 => mayDenyPut case _ => throw new IndexOutOfBoundsException(n.toString) } def supportsAcquireT: TransferSizes = supports.acquireT def supportsAcquireB: TransferSizes = supports.acquireB def supportsArithmetic: TransferSizes = supports.arithmetic def supportsLogical: TransferSizes = supports.logical def supportsGet: TransferSizes = supports.get def supportsPutFull: TransferSizes = supports.putFull def supportsPutPartial: TransferSizes = supports.putPartial def supportsHint: TransferSizes = supports.hint require (!address.isEmpty, "Address cannot be empty") address.foreach { a => require (a.finite, "Address must be finite") } address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)") require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)") require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)") require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)") require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)") require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)") require (!alwaysGrantsT || supportsAcquireT, s"Must supportAcquireT if promising to always grantT") // Make sure that the regionType agrees with the capabilities require (!supportsAcquireB || regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached require (regionType <= RegionType.UNCACHED || supportsAcquireB) // tracked, cached -> acquire require (regionType != RegionType.UNCACHED || supportsGet) // uncached -> supportsGet val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected") val maxTransfer = List( // Largest supported transfer of all types supportsAcquireT.max, supportsAcquireB.max, supportsArithmetic.max, supportsLogical.max, supportsGet.max, supportsPutFull.max, supportsPutPartial.max).max val maxAddress = address.map(_.max).max val minAlignment = address.map(_.alignment).min // The device had better not support a transfer larger than its alignment require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)") def toResource: ResourceAddress = { ResourceAddress(address, ResourcePermissions( r = supportsAcquireB || supportsGet, w = supportsAcquireT || supportsPutFull, x = executable, c = supportsAcquireB, a = supportsArithmetic && supportsLogical)) } def findTreeViolation() = nodePath.find { case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false case _: SinkNode[_, _, _, _, _] => false case node => node.inputs.size != 1 } def isTree = findTreeViolation() == None def infoString = { s"""Slave Name = ${name} |Slave Address = ${address} |supports = ${supports.infoString} | |""".stripMargin } def v1copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { new TLSlaveParameters( setName = setName, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = emits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: Option[String] = setName, address: Seq[AddressSet] = address, regionType: RegionType.T = regionType, executable: Boolean = executable, fifoId: Option[Int] = fifoId, supports: TLMasterToSlaveTransferSizes = supports, emits: TLSlaveToMasterTransferSizes = emits, alwaysGrantsT: Boolean = alwaysGrantsT, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } @deprecated("Use v1copy instead of copy","") def copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { v1copy( address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supportsAcquireT = supportsAcquireT, supportsAcquireB = supportsAcquireB, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } } object TLSlaveParameters { def v1( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = { new TLSlaveParameters( setName = None, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLSlaveToMasterTransferSizes.unknownEmits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2( address: Seq[AddressSet], nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Seq(), name: Option[String] = None, regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, fifoId: Option[Int] = None, supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports, emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits, alwaysGrantsT: Boolean = false, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } } object TLManagerParameters { @deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","") def apply( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = TLSlaveParameters.v1( address, resources, regionType, executable, nodePath, supportsAcquireT, supportsAcquireB, supportsArithmetic, supportsLogical, supportsGet, supportsPutFull, supportsPutPartial, supportsHint, mayDenyGet, mayDenyPut, alwaysGrantsT, fifoId, ) } case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int]) { def members = Seq(a, b, c, d) members.collect { case Some(beatBytes) => require (isPow2(beatBytes), "Data channel width must be a power of 2") } } object TLChannelBeatBytes{ def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes( Some(beatBytes), Some(beatBytes), Some(beatBytes), Some(beatBytes)) def apply(): TLChannelBeatBytes = TLChannelBeatBytes( None, None, None, None) } class TLSlavePortParameters private( val slaves: Seq[TLSlaveParameters], val channelBytes: TLChannelBeatBytes, val endSinkId: Int, val minLatency: Int, val responseFields: Seq[BundleFieldBase], val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct { def sortedSlaves = slaves.sortBy(_.sortedAddress.head) override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters] override def productPrefix = "TLSlavePortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => slaves case 1 => channelBytes case 2 => endSinkId case 3 => minLatency case 4 => responseFields case 5 => requestKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!slaves.isEmpty, "Slave ports must have slaves") require (endSinkId >= 0, "Sink ids cannot be negative") require (minLatency >= 0, "Minimum required latency cannot be negative") // Using this API implies you cannot handle mixed-width busses def beatBytes = { channelBytes.members.foreach { width => require (width.isDefined && width == channelBytes.a) } channelBytes.a.get } // TODO this should be deprecated def managers = slaves def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = { val relevant = slaves.filter(m => policy(m)) relevant.foreach { m => require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ") } } // Bounds on required sizes def maxAddress = slaves.map(_.maxAddress).max def maxTransfer = slaves.map(_.maxTransfer).max def mayDenyGet = slaves.exists(_.mayDenyGet) def mayDenyPut = slaves.exists(_.mayDenyPut) // Diplomatically determined operation sizes emitted by all outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _) // Operation Emitted by at least one outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _) val allSupportAcquireT = allSupportClaims.acquireT val allSupportAcquireB = allSupportClaims.acquireB val allSupportArithmetic = allSupportClaims.arithmetic val allSupportLogical = allSupportClaims.logical val allSupportGet = allSupportClaims.get val allSupportPutFull = allSupportClaims.putFull val allSupportPutPartial = allSupportClaims.putPartial val allSupportHint = allSupportClaims.hint // Operation supported by at least one outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _) val anySupportAcquireT = !anySupportClaims.acquireT.none val anySupportAcquireB = !anySupportClaims.acquireB.none val anySupportArithmetic = !anySupportClaims.arithmetic.none val anySupportLogical = !anySupportClaims.logical.none val anySupportGet = !anySupportClaims.get.none val anySupportPutFull = !anySupportClaims.putFull.none val anySupportPutPartial = !anySupportClaims.putPartial.none val anySupportHint = !anySupportClaims.hint.none // Supporting Acquire means being routable for GrantAck require ((endSinkId == 0) == !anySupportAcquireB) // These return Option[TLSlaveParameters] for your convenience def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address))) // The safe version will check the entire address def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ || _))) // The fast version assumes the address is valid (you probably want fastProperty instead of this function) def findFast(address: UInt) = { val routingMask = AddressDecoder(slaves.map(_.address)) VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ || _))) } // Compute the simplest AddressSets that decide a key def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = { val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) => k -> vs.flatMap(_._2) } val reductionMask = AddressDecoder(groups.map(_._2)) groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) } } // Select a property def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D = Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_||_), d(v)) }) // Note: returns the actual fifoId + 1 or 0 if None def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U) def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B) // Does this Port manage this ID/address? def containsSafe(address: UInt) = findSafe(address).reduce(_ || _) private def addressHelper( // setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity safe: Boolean, // member filters out the sizes being checked based on the opcode being emitted or supported member: TLSlaveParameters => TransferSizes, address: UInt, lgSize: UInt, // range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity range: Option[TransferSizes]): Bool = { // trim reduces circuit complexity by intersecting checked sizes with the range argument def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x) // groupBy returns an unordered map, convert back to Seq and sort the result for determinism // groupByIntoSeq is turning slaves into trimmed membership sizes // We are grouping all the slaves by their transfer size where // if they support the trimmed size then // member is the type of transfer that you are looking for (What you are trying to filter on) // When you consider membership, you are trimming the sizes to only the ones that you care about // you are filtering the slaves based on both whether they support a particular opcode and the size // Grouping the slaves based on the actual transfer size range they support // intersecting the range and checking their membership // FOR SUPPORTCASES instead of returning the list of slaves, // you are returning a map from transfer size to the set of // address sets that are supported for that transfer size // find all the slaves that support a certain type of operation and then group their addresses by the supported size // for every size there could be multiple address ranges // safety is a trade off between checking between all possible addresses vs only the addresses // that are known to have supported sizes // the trade off is 'checking all addresses is a more expensive circuit but will always give you // the right answer even if you give it an illegal address' // the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer // fast presumes address legality // This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies. // In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size. val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) => k -> vs.flatMap(_.address) } // safe produces a circuit that compares against all possible addresses, // whereas fast presumes that the address is legal but uses an efficient address decoder val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2)) // Simplified creates the most concise possible representation of each cases' address sets based on the mask. val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) } simplified.map { case (s, a) => // s is a size, you are checking for this size either the size of the operation is in s // We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire. ((Some(s) == range).B || s.containsLg(lgSize)) && a.map(_.contains(address)).reduce(_||_) }.foldLeft(false.B)(_||_) } def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range) def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range) def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range) def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range) def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range) def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range) def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range) def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range) def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range) def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range) def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range) def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range) def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range) def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range) def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range) def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range) def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range) def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range) def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range) def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range) def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range) def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range) def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range) def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption def isTree = !slaves.exists(!_.isTree) def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString def v1copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = managers, channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } def v2copy( slaves: Seq[TLSlaveParameters] = slaves, channelBytes: TLChannelBeatBytes = channelBytes, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = slaves, channelBytes = channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } @deprecated("Use v1copy instead of copy","") def copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { v1copy( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } object TLSlavePortParameters { def v1( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { new TLSlavePortParameters( slaves = managers, channelBytes = TLChannelBeatBytes(beatBytes), endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } } object TLManagerPortParameters { @deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","") def apply( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { TLSlavePortParameters.v1( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } class TLMasterParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], val name: String, val visibility: Seq[AddressSet], val unusedRegionTypes: Set[RegionType.T], val executesOnly: Boolean, val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C. val supports: TLSlaveToMasterTransferSizes, val emits: TLMasterToSlaveTransferSizes, val neverReleasesData: Boolean, val sourceId: IdRange) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters] override def productPrefix = "TLMasterParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 10 def productElement(n: Int): Any = n match { case 0 => name case 1 => sourceId case 2 => resources case 3 => visibility case 4 => unusedRegionTypes case 5 => executesOnly case 6 => requestFifo case 7 => supports case 8 => emits case 9 => neverReleasesData case _ => throw new IndexOutOfBoundsException(n.toString) } require (!sourceId.isEmpty) require (!visibility.isEmpty) require (supports.putFull.contains(supports.putPartial)) // We only support these operations if we support Probe (ie: we're a cache) require (supports.probe.contains(supports.arithmetic)) require (supports.probe.contains(supports.logical)) require (supports.probe.contains(supports.get)) require (supports.probe.contains(supports.putFull)) require (supports.probe.contains(supports.putPartial)) require (supports.probe.contains(supports.hint)) visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } val maxTransfer = List( supports.probe.max, supports.arithmetic.max, supports.logical.max, supports.get.max, supports.putFull.max, supports.putPartial.max).max def infoString = { s"""Master Name = ${name} |visibility = ${visibility} |emits = ${emits.infoString} |sourceId = ${sourceId} | |""".stripMargin } def v1copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { new TLMasterParameters( nodePath = nodePath, resources = this.resources, name = name, visibility = visibility, unusedRegionTypes = this.unusedRegionTypes, executesOnly = this.executesOnly, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = this.emits, neverReleasesData = this.neverReleasesData, sourceId = sourceId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: String = name, visibility: Seq[AddressSet] = visibility, unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes, executesOnly: Boolean = executesOnly, requestFifo: Boolean = requestFifo, supports: TLSlaveToMasterTransferSizes = supports, emits: TLMasterToSlaveTransferSizes = emits, neverReleasesData: Boolean = neverReleasesData, sourceId: IdRange = sourceId) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } @deprecated("Use v1copy instead of copy","") def copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { v1copy( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } object TLMasterParameters { def v1( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { new TLMasterParameters( nodePath = nodePath, resources = Nil, name = name, visibility = visibility, unusedRegionTypes = Set(), executesOnly = false, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData = false, sourceId = sourceId) } def v2( nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Nil, name: String, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), unusedRegionTypes: Set[RegionType.T] = Set(), executesOnly: Boolean = false, requestFifo: Boolean = false, supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports, emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData: Boolean = false, sourceId: IdRange = IdRange(0,1)) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } } object TLClientParameters { @deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","") def apply( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet.everything), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { TLMasterParameters.v1( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } class TLMasterPortParameters private( val masters: Seq[TLMasterParameters], val channelBytes: TLChannelBeatBytes, val minLatency: Int, val echoFields: Seq[BundleFieldBase], val requestFields: Seq[BundleFieldBase], val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters] override def productPrefix = "TLMasterPortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => masters case 1 => channelBytes case 2 => minLatency case 3 => echoFields case 4 => requestFields case 5 => responseKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!masters.isEmpty) require (minLatency >= 0) def clients = masters // Require disjoint ranges for Ids IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) => require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}") } // Bounds on required sizes def endSourceId = masters.map(_.sourceId.end).max def maxTransfer = masters.map(_.maxTransfer).max // The unused sources < endSourceId def unusedSources: Seq[Int] = { val usedSources = masters.map(_.sourceId).sortBy(_.start) ((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) => end until start } } // Diplomatically determined operation sizes emitted by all inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = masters.map(_.emits).reduce( _ intersect _) // Diplomatically determined operation sizes Emitted by at least one inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all inward Masters // as opposed to supports* which generate circuitry to check which specific addresses val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _) val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _) val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _) val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _) val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _) val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _) val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _) // Diplomatically determined operation sizes supported by at least one master // as opposed to supports* which generate circuitry to check which specific addresses val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ || _) val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ || _) val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ || _) val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ || _) val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ || _) val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ || _) val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ || _) // These return Option[TLMasterParameters] for your convenience def find(id: Int) = masters.find(_.sourceId.contains(id)) // Synthesizable lookup methods def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id))) def contains(id: UInt) = find(id).reduce(_ || _) def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B)) // Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = { val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _) // this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version; // the case where there is only one group. if (allSame) member(masters(0)).containsLg(lgSize) else { // Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize Mux1H(find(id), masters.map(member(_).containsLg(lgSize))) } } // Check for support of a given operation at a specific id val supportsProbe = sourceIdHelper(_.supports.probe) _ val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _ val supportsLogical = sourceIdHelper(_.supports.logical) _ val supportsGet = sourceIdHelper(_.supports.get) _ val supportsPutFull = sourceIdHelper(_.supports.putFull) _ val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _ val supportsHint = sourceIdHelper(_.supports.hint) _ // TODO: Merge sourceIdHelper2 with sourceIdHelper private def sourceIdHelper2( member: TLMasterParameters => TransferSizes, sourceId: UInt, lgSize: UInt): Bool = { // Because sourceIds are uniquely owned by each master, we use them to group the // cases that have to be checked. val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) => k -> vs.map(_.sourceId) } emitCases.map { case (s, a) => (s.containsLg(lgSize)) && a.map(_.contains(sourceId)).reduce(_||_) }.foldLeft(false.B)(_||_) } // Check for emit of a given operation at a specific id def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize) def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize) def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize) def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize) def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize) def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize) def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize) def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize) def infoString = masters.map(_.infoString).mkString def v1copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = clients, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2copy( masters: Seq[TLMasterParameters] = masters, channelBytes: TLChannelBeatBytes = channelBytes, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } @deprecated("Use v1copy instead of copy","") def copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { v1copy( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLClientPortParameters { @deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","") def apply( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { TLMasterPortParameters.v1( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLMasterPortParameters { def v1( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = clients, channelBytes = TLChannelBeatBytes(), minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2( masters: Seq[TLMasterParameters], channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(), minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } } case class TLBundleParameters( addressBits: Int, dataBits: Int, sourceBits: Int, sinkBits: Int, sizeBits: Int, echoFields: Seq[BundleFieldBase], requestFields: Seq[BundleFieldBase], responseFields: Seq[BundleFieldBase], hasBCE: Boolean) { // Chisel has issues with 0-width wires require (addressBits >= 1) require (dataBits >= 8) require (sourceBits >= 1) require (sinkBits >= 1) require (sizeBits >= 1) require (isPow2(dataBits)) echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") } val addrLoBits = log2Up(dataBits/8) // Used to uniquify bus IP names def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u") def union(x: TLBundleParameters) = TLBundleParameters( max(addressBits, x.addressBits), max(dataBits, x.dataBits), max(sourceBits, x.sourceBits), max(sinkBits, x.sinkBits), max(sizeBits, x.sizeBits), echoFields = BundleField.union(echoFields ++ x.echoFields), requestFields = BundleField.union(requestFields ++ x.requestFields), responseFields = BundleField.union(responseFields ++ x.responseFields), hasBCE || x.hasBCE) } object TLBundleParameters { val emptyBundleParams = TLBundleParameters( addressBits = 1, dataBits = 8, sourceBits = 1, sinkBits = 1, sizeBits = 1, echoFields = Nil, requestFields = Nil, responseFields = Nil, hasBCE = false) def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y)) def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) = new TLBundleParameters( addressBits = log2Up(slave.maxAddress + 1), dataBits = slave.beatBytes * 8, sourceBits = log2Up(master.endSourceId), sinkBits = log2Up(slave.endSinkId), sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1), echoFields = master.echoFields, requestFields = BundleField.accept(master.requestFields, slave.requestKeys), responseFields = BundleField.accept(slave.responseFields, master.responseKeys), hasBCE = master.anySupportProbe && slave.anySupportAcquireB) } case class TLEdgeParameters( master: TLMasterPortParameters, slave: TLSlavePortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { // legacy names: def manager = slave def client = master val maxTransfer = max(master.maxTransfer, slave.maxTransfer) val maxLgSize = log2Ceil(maxTransfer) // Sanity check the link... require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})") def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims) val bundle = TLBundleParameters(master, slave) def formatEdge = master.infoString + "\n" + slave.infoString } case class TLCreditedDelay( a: CreditedDelay, b: CreditedDelay, c: CreditedDelay, d: CreditedDelay, e: CreditedDelay) { def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay( a = a + that.a, b = b + that.b, c = c + that.c, d = d + that.d, e = e + that.e) override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})" } object TLCreditedDelay { def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay) } case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString} case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val delay = client.delay + manager.delay val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters) case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base)) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } // To be unified, devices must agree on all of these terms case class ManagerUnificationKey( resources: Seq[Resource], regionType: RegionType.T, executable: Boolean, supportsAcquireT: TransferSizes, supportsAcquireB: TransferSizes, supportsArithmetic: TransferSizes, supportsLogical: TransferSizes, supportsGet: TransferSizes, supportsPutFull: TransferSizes, supportsPutPartial: TransferSizes, supportsHint: TransferSizes) object ManagerUnificationKey { def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey( resources = x.resources, regionType = x.regionType, executable = x.executable, supportsAcquireT = x.supportsAcquireT, supportsAcquireB = x.supportsAcquireB, supportsArithmetic = x.supportsArithmetic, supportsLogical = x.supportsLogical, supportsGet = x.supportsGet, supportsPutFull = x.supportsPutFull, supportsPutPartial = x.supportsPutPartial, supportsHint = x.supportsHint) } object ManagerUnification { def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = { slaves.groupBy(ManagerUnificationKey.apply).values.map { seq => val agree = seq.forall(_.fifoId == seq.head.fifoId) seq(0).v1copy( address = AddressSet.unify(seq.flatMap(_.address)), fifoId = if (agree) seq(0).fifoId else None) }.toList } } case class TLBufferParams( a: BufferParams = BufferParams.none, b: BufferParams = BufferParams.none, c: BufferParams = BufferParams.none, d: BufferParams = BufferParams.none, e: BufferParams = BufferParams.none ) extends DirectedBuffers[TLBufferParams] { def copyIn(x: BufferParams) = this.copy(b = x, d = x) def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x) def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x) } /** Pretty printing of TL source id maps */ class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] { private val tlDigits = String.valueOf(tl.endSourceId-1).length() protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s" private val sorted = tl.masters.sortBy(_.sourceId) val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c => TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo) } } case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean) extends IdMapEntry { val from = tlId val to = tlId val maxTransactionsInFlight = Some(tlId.size) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module TLMonitor_46( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [15:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [127:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [127:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [5:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [15:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [127:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [5:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [127:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [7:0] c_first_beats1_decode = 8'h0; // @[Edges.scala:220:59] wire [7:0] c_first_beats1 = 8'h0; // @[Edges.scala:221:14] wire [7:0] _c_first_count_T = 8'h0; // @[Edges.scala:234:27] wire [7:0] c_first_count = 8'h0; // @[Edges.scala:234:25] wire [7:0] _c_first_counter_T = 8'h0; // @[Edges.scala:236:21] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_4 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:56:48] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_10 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:56:48] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [7:0] c_first_counter1 = 8'hFF; // @[Edges.scala:230:28] wire [8:0] _c_first_counter1_T = 9'h1FF; // @[Edges.scala:230:28] wire [127:0] _c_first_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_first_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_first_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_first_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_set_wo_ready_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_set_wo_ready_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_opcodes_set_interm_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_opcodes_set_interm_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_sizes_set_interm_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_sizes_set_interm_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_opcodes_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_opcodes_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_sizes_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_sizes_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_probe_ack_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_probe_ack_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_probe_ack_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_probe_ack_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_4_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_5_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [5:0] _c_first_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_first_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_first_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_first_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_set_wo_ready_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_set_wo_ready_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_set_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_set_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_opcodes_set_interm_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_opcodes_set_interm_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_sizes_set_interm_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_sizes_set_interm_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_opcodes_set_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_opcodes_set_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_sizes_set_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_sizes_set_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_probe_ack_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_probe_ack_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_probe_ack_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_probe_ack_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _same_cycle_resp_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _same_cycle_resp_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _same_cycle_resp_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _same_cycle_resp_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _same_cycle_resp_WIRE_4_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _same_cycle_resp_WIRE_5_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [515:0] _c_sizes_set_T_1 = 516'h0; // @[Monitor.scala:768:52] wire [8:0] _c_opcodes_set_T = 9'h0; // @[Monitor.scala:767:79] wire [8:0] _c_sizes_set_T = 9'h0; // @[Monitor.scala:768:77] wire [514:0] _c_opcodes_set_T_1 = 515'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [63:0] _c_set_wo_ready_T = 64'h1; // @[OneHot.scala:58:35] wire [63:0] _c_set_T = 64'h1; // @[OneHot.scala:58:35] wire [511:0] c_sizes_set = 512'h0; // @[Monitor.scala:741:34] wire [255:0] c_opcodes_set = 256'h0; // @[Monitor.scala:740:34] wire [63:0] c_set = 64'h0; // @[Monitor.scala:738:34] wire [63:0] c_set_wo_ready = 64'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [5:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire [3:0] mask_sizeOH = {_mask_sizeOH_T_2[3:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_sub_0_1 = |(io_in_a_bits_size_0[3:2]); // @[Misc.scala:206:21] wire mask_sub_sub_sub_size = mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_sub_bit = io_in_a_bits_address_0[3]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_1_2 = mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_nbit = ~mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_0_2 = mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_acc_T = mask_sub_sub_sub_size & mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_size & mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_1_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_2_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size & mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_2_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_3_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size & mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_3_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_4_2 = mask_sub_sub_2_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_4 = mask_sub_size & mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_4_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_5_2 = mask_sub_sub_2_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_5 = mask_sub_size & mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_5_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_6_2 = mask_sub_sub_3_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_6 = mask_sub_size & mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_6_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_7_2 = mask_sub_sub_3_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_7 = mask_sub_size & mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_7_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_eq_8 = mask_sub_4_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_size & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_8 = mask_sub_4_1 | _mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_eq_9 = mask_sub_4_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_size & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_9 = mask_sub_4_1 | _mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_eq_10 = mask_sub_5_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_size & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_10 = mask_sub_5_1 | _mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_eq_11 = mask_sub_5_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_size & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_11 = mask_sub_5_1 | _mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_eq_12 = mask_sub_6_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_size & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_12 = mask_sub_6_1 | _mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_eq_13 = mask_sub_6_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_size & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_13 = mask_sub_6_1 | _mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_eq_14 = mask_sub_7_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_size & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_14 = mask_sub_7_1 | _mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_eq_15 = mask_sub_7_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_size & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_15 = mask_sub_7_1 | _mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_lo = {mask_lo_lo_hi, mask_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_hi = {mask_lo_hi_hi, mask_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_lo_hi = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_lo = {mask_hi_lo_hi, mask_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_hi = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_hi = {mask_hi_hi_hi, mask_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [15:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [5:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [5:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _T_1267 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1267; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1267; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [7:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [7:0] a_first_counter; // @[Edges.scala:229:27] wire [8:0] _a_first_counter1_T = {1'h0, a_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] a_first_counter1 = _a_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [7:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [5:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1340 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1340; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1340; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1340; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [7:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T = {1'h0, d_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1 = _d_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [5:0] source_1; // @[Monitor.scala:541:22] reg [3:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [63:0] inflight; // @[Monitor.scala:614:27] reg [255:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [511:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [7:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [7:0] a_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] a_first_counter1_1 = _a_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [7:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_1 = _d_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [63:0] a_set; // @[Monitor.scala:626:34] wire [63:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [255:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [511:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [8:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [8:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [8:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [8:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [8:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [255:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [255:0] _a_opcode_lookup_T_6 = {252'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [255:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[255:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [8:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [8:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [8:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [8:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [8:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [511:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [511:0] _a_size_lookup_T_6 = {504'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [511:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[511:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [63:0] _GEN_3 = {58'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35] wire [63:0] _GEN_4 = 64'h1 << _GEN_3; // @[OneHot.scala:58:35] wire [63:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35] wire [63:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 64'h0; // @[OneHot.scala:58:35] wire _T_1193 = _T_1267 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1193 ? _a_set_T : 64'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1193 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1193 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [8:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [514:0] _a_opcodes_set_T_1 = {511'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1193 ? _a_opcodes_set_T_1[255:0] : 256'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [8:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [515:0] _a_sizes_set_T_1 = {511'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1193 ? _a_sizes_set_T_1[511:0] : 512'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [63:0] d_clr; // @[Monitor.scala:664:34] wire [63:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [255:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [511:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46] wire _T_1239 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [63:0] _GEN_6 = {58'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [63:0] _GEN_7 = 64'h1 << _GEN_6; // @[OneHot.scala:58:35] wire [63:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35] wire [63:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35] wire [63:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35] wire [63:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1239 & ~d_release_ack ? _d_clr_wo_ready_T : 64'h0; // @[OneHot.scala:58:35] wire _T_1208 = _T_1340 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1208 ? _d_clr_T : 64'h0; // @[OneHot.scala:58:35] wire [526:0] _d_opcodes_clr_T_5 = 527'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1208 ? _d_opcodes_clr_T_5[255:0] : 256'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [526:0] _d_sizes_clr_T_5 = 527'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1208 ? _d_sizes_clr_T_5[511:0] : 512'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [63:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [63:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [63:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [255:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [255:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [255:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [511:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [511:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [511:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [63:0] inflight_1; // @[Monitor.scala:726:35] wire [63:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [255:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [255:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [511:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [511:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_2; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_2 = _d_first_counter1_T_2[7:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [255:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [255:0] _c_opcode_lookup_T_6 = {252'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [255:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[255:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [511:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [511:0] _c_size_lookup_T_6 = {504'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [511:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[511:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [63:0] d_clr_1; // @[Monitor.scala:774:34] wire [63:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [255:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [511:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1311 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1311 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 64'h0; // @[OneHot.scala:58:35] wire _T_1293 = _T_1340 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1293 ? _d_clr_T_1 : 64'h0; // @[OneHot.scala:58:35] wire [526:0] _d_opcodes_clr_T_11 = 527'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1293 ? _d_opcodes_clr_T_11[255:0] : 256'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [526:0] _d_sizes_clr_T_11 = 527'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1293 ? _d_sizes_clr_T_11[511:0] : 512'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 6'h0; // @[Monitor.scala:36:7, :795:113] wire [63:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [63:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [255:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [255:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [511:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [511:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module TLMonitor_40( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [20:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_37 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_43 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_49 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_wo_ready_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_wo_ready_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_4_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_5_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire _source_ok_T_27 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31] wire _source_ok_T_28 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_29 = _source_ok_T_28 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_30 = _source_ok_T_29 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_31 = _source_ok_T_30 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_32 = _source_ok_T_31 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_33 = _source_ok_T_32 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_33 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [20:0] _is_aligned_T = {15'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 21'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_34 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_34; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_35 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_41 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_47 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_53 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_36 = _source_ok_T_35 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_38 = _source_ok_T_36; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_40; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_42 = _source_ok_T_41 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_44 = _source_ok_T_42; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_46; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_48 = _source_ok_T_47 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_50 = _source_ok_T_48; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_52; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_54 = _source_ok_T_53 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_58; // @[Parameters.scala:1138:31] wire _source_ok_T_59 = io_in_d_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_59; // @[Parameters.scala:1138:31] wire _source_ok_T_60 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_60; // @[Parameters.scala:1138:31] wire _source_ok_T_61 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_61; // @[Parameters.scala:1138:31] wire _source_ok_T_62 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_63 = _source_ok_T_62 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_64 = _source_ok_T_63 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_65 = _source_ok_T_64 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_66 = _source_ok_T_65 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_67 = _source_ok_T_66 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_67 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _T_975 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_975; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_975; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [20:0] address; // @[Monitor.scala:391:22] wire _T_1043 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1043; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1043; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1043; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [259:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [259:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_908 = _T_975 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_908 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_908 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_908 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_908 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_908 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_954 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_954 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_923 = _T_1043 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_923 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_923 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_923 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [259:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1019 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1019 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1001 = _T_1043 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1001 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1001 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1001 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands */ class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def *(t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def *(t: UInt) = self * t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros | ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def *(t: SInt) = self * t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros | ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid || output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def *(t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def *(t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }

module PE_478( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_222 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Metadata.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.constants.MemoryOpConstants import freechips.rocketchip.util._ object ClientStates { val width = 2 def Nothing = 0.U(width.W) def Branch = 1.U(width.W) def Trunk = 2.U(width.W) def Dirty = 3.U(width.W) def hasReadPermission(state: UInt): Bool = state > Nothing def hasWritePermission(state: UInt): Bool = state > Branch } object MemoryOpCategories extends MemoryOpConstants { def wr = Cat(true.B, true.B) // Op actually writes def wi = Cat(false.B, true.B) // Future op will write def rd = Cat(false.B, false.B) // Op only reads def categorize(cmd: UInt): UInt = { val cat = Cat(isWrite(cmd), isWriteIntent(cmd)) //assert(cat.isOneOf(wr,wi,rd), "Could not categorize command.") cat } } /** Stores the client-side coherence information, * such as permissions on the data and whether the data is dirty. * Its API can be used to make TileLink messages in response to * memory operations, cache control oeprations, or Probe messages. */ class ClientMetadata extends Bundle { /** Actual state information stored in this bundle */ val state = UInt(ClientStates.width.W) /** Metadata equality */ def ===(rhs: UInt): Bool = state === rhs def ===(rhs: ClientMetadata): Bool = state === rhs.state def =/=(rhs: ClientMetadata): Bool = !this.===(rhs) /** Is the block's data present in this cache */ def isValid(dummy: Int = 0): Bool = state > ClientStates.Nothing /** Determine whether this cmd misses, and the new state (on hit) or param to be sent (on miss) */ private def growStarter(cmd: UInt): (Bool, UInt) = { import MemoryOpCategories._ import TLPermissions._ import ClientStates._ val c = categorize(cmd) MuxTLookup(Cat(c, state), (false.B, 0.U), Seq( //(effect, am now) -> (was a hit, next) Cat(rd, Dirty) -> (true.B, Dirty), Cat(rd, Trunk) -> (true.B, Trunk), Cat(rd, Branch) -> (true.B, Branch), Cat(wi, Dirty) -> (true.B, Dirty), Cat(wi, Trunk) -> (true.B, Trunk), Cat(wr, Dirty) -> (true.B, Dirty), Cat(wr, Trunk) -> (true.B, Dirty), //(effect, am now) -> (was a miss, param) Cat(rd, Nothing) -> (false.B, NtoB), Cat(wi, Branch) -> (false.B, BtoT), Cat(wi, Nothing) -> (false.B, NtoT), Cat(wr, Branch) -> (false.B, BtoT), Cat(wr, Nothing) -> (false.B, NtoT))) } /** Determine what state to go to after miss based on Grant param * For now, doesn't depend on state (which may have been Probed). */ private def growFinisher(cmd: UInt, param: UInt): UInt = { import MemoryOpCategories._ import TLPermissions._ import ClientStates._ val c = categorize(cmd) //assert(c === rd || param === toT, "Client was expecting trunk permissions.") MuxLookup(Cat(c, param), Nothing)(Seq( //(effect param) -> (next) Cat(rd, toB) -> Branch, Cat(rd, toT) -> Trunk, Cat(wi, toT) -> Trunk, Cat(wr, toT) -> Dirty)) } /** Does this cache have permissions on this block sufficient to perform op, * and what to do next (Acquire message param or updated metadata). */ def onAccess(cmd: UInt): (Bool, UInt, ClientMetadata) = { val r = growStarter(cmd) (r._1, r._2, ClientMetadata(r._2)) } /** Does a secondary miss on the block require another Acquire message */ def onSecondaryAccess(first_cmd: UInt, second_cmd: UInt): (Bool, Bool, UInt, ClientMetadata, UInt) = { import MemoryOpCategories._ val r1 = growStarter(first_cmd) val r2 = growStarter(second_cmd) val needs_second_acq = isWriteIntent(second_cmd) && !isWriteIntent(first_cmd) val hit_again = r1._1 && r2._1 val dirties = categorize(second_cmd) === wr val biggest_grow_param = Mux(dirties, r2._2, r1._2) val dirtiest_state = ClientMetadata(biggest_grow_param) val dirtiest_cmd = Mux(dirties, second_cmd, first_cmd) (needs_second_acq, hit_again, biggest_grow_param, dirtiest_state, dirtiest_cmd) } /** Metadata change on a returned Grant */ def onGrant(cmd: UInt, param: UInt): ClientMetadata = ClientMetadata(growFinisher(cmd, param)) /** Determine what state to go to based on Probe param */ private def shrinkHelper(param: UInt): (Bool, UInt, UInt) = { import ClientStates._ import TLPermissions._ MuxTLookup(Cat(param, state), (false.B, 0.U, 0.U), Seq( //(wanted, am now) -> (hasDirtyData resp, next) Cat(toT, Dirty) -> (true.B, TtoT, Trunk), Cat(toT, Trunk) -> (false.B, TtoT, Trunk), Cat(toT, Branch) -> (false.B, BtoB, Branch), Cat(toT, Nothing) -> (false.B, NtoN, Nothing), Cat(toB, Dirty) -> (true.B, TtoB, Branch), Cat(toB, Trunk) -> (false.B, TtoB, Branch), // Policy: Don't notify on clean downgrade Cat(toB, Branch) -> (false.B, BtoB, Branch), Cat(toB, Nothing) -> (false.B, NtoN, Nothing), Cat(toN, Dirty) -> (true.B, TtoN, Nothing), Cat(toN, Trunk) -> (false.B, TtoN, Nothing), // Policy: Don't notify on clean downgrade Cat(toN, Branch) -> (false.B, BtoN, Nothing), // Policy: Don't notify on clean downgrade Cat(toN, Nothing) -> (false.B, NtoN, Nothing))) } /** Translate cache control cmds into Probe param */ private def cmdToPermCap(cmd: UInt): UInt = { import MemoryOpCategories._ import TLPermissions._ MuxLookup(cmd, toN)(Seq( M_FLUSH -> toN, M_PRODUCE -> toB, M_CLEAN -> toT)) } def onCacheControl(cmd: UInt): (Bool, UInt, ClientMetadata) = { val r = shrinkHelper(cmdToPermCap(cmd)) (r._1, r._2, ClientMetadata(r._3)) } def onProbe(param: UInt): (Bool, UInt, ClientMetadata) = { val r = shrinkHelper(param) (r._1, r._2, ClientMetadata(r._3)) } } /** Factories for ClientMetadata, including on reset */ object ClientMetadata { def apply(perm: UInt) = { val meta = Wire(new ClientMetadata) meta.state := perm meta } def onReset = ClientMetadata(ClientStates.Nothing) def maximum = ClientMetadata(ClientStates.Dirty) } File Consts.scala: // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket.constants import chisel3._ import chisel3.util._ import freechips.rocketchip.util._ trait ScalarOpConstants { val SZ_BR = 3 def BR_X = BitPat("b???") def BR_EQ = 0.U(3.W) def BR_NE = 1.U(3.W) def BR_J = 2.U(3.W) def BR_N = 3.U(3.W) def BR_LT = 4.U(3.W) def BR_GE = 5.U(3.W) def BR_LTU = 6.U(3.W) def BR_GEU = 7.U(3.W) def A1_X = BitPat("b??") def A1_ZERO = 0.U(2.W) def A1_RS1 = 1.U(2.W) def A1_PC = 2.U(2.W) def A1_RS1SHL = 3.U(2.W) def IMM_X = BitPat("b???") def IMM_S = 0.U(3.W) def IMM_SB = 1.U(3.W) def IMM_U = 2.U(3.W) def IMM_UJ = 3.U(3.W) def IMM_I = 4.U(3.W) def IMM_Z = 5.U(3.W) def A2_X = BitPat("b???") def A2_ZERO = 0.U(3.W) def A2_SIZE = 1.U(3.W) def A2_RS2 = 2.U(3.W) def A2_IMM = 3.U(3.W) def A2_RS2OH = 4.U(3.W) def A2_IMMOH = 5.U(3.W) def X = BitPat("b?") def N = BitPat("b0") def Y = BitPat("b1") val SZ_DW = 1 def DW_X = X def DW_32 = false.B def DW_64 = true.B def DW_XPR = DW_64 } trait MemoryOpConstants { val NUM_XA_OPS = 9 val M_SZ = 5 def M_X = BitPat("b?????"); def M_XRD = "b00000".U; // int load def M_XWR = "b00001".U; // int store def M_PFR = "b00010".U; // prefetch with intent to read def M_PFW = "b00011".U; // prefetch with intent to write def M_XA_SWAP = "b00100".U def M_FLUSH_ALL = "b00101".U // flush all lines def M_XLR = "b00110".U def M_XSC = "b00111".U def M_XA_ADD = "b01000".U def M_XA_XOR = "b01001".U def M_XA_OR = "b01010".U def M_XA_AND = "b01011".U def M_XA_MIN = "b01100".U def M_XA_MAX = "b01101".U def M_XA_MINU = "b01110".U def M_XA_MAXU = "b01111".U def M_FLUSH = "b10000".U // write back dirty data and cede R/W permissions def M_PWR = "b10001".U // partial (masked) store def M_PRODUCE = "b10010".U // write back dirty data and cede W permissions def M_CLEAN = "b10011".U // write back dirty data and retain R/W permissions def M_SFENCE = "b10100".U // SFENCE.VMA def M_HFENCEV = "b10101".U // HFENCE.VVMA def M_HFENCEG = "b10110".U // HFENCE.GVMA def M_WOK = "b10111".U // check write permissions but don't perform a write def M_HLVX = "b10000".U // HLVX instruction def isAMOLogical(cmd: UInt) = cmd.isOneOf(M_XA_SWAP, M_XA_XOR, M_XA_OR, M_XA_AND) def isAMOArithmetic(cmd: UInt) = cmd.isOneOf(M_XA_ADD, M_XA_MIN, M_XA_MAX, M_XA_MINU, M_XA_MAXU) def isAMO(cmd: UInt) = isAMOLogical(cmd) || isAMOArithmetic(cmd) def isPrefetch(cmd: UInt) = cmd === M_PFR || cmd === M_PFW def isRead(cmd: UInt) = cmd.isOneOf(M_XRD, M_HLVX, M_XLR, M_XSC) || isAMO(cmd) def isWrite(cmd: UInt) = cmd === M_XWR || cmd === M_PWR || cmd === M_XSC || isAMO(cmd) def isWriteIntent(cmd: UInt) = isWrite(cmd) || cmd === M_PFW || cmd === M_XLR } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File mshrs.scala: //****************************************************************************** // Ported from Rocket-Chip // See LICENSE.Berkeley and LICENSE.SiFive in Rocket-Chip for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.lsu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.tile._ import freechips.rocketchip.util._ import freechips.rocketchip.rocket._ import boom.v3.common._ import boom.v3.exu.BrUpdateInfo import boom.v3.util.{IsKilledByBranch, GetNewBrMask, BranchKillableQueue, IsOlder, UpdateBrMask, AgePriorityEncoder, WrapInc} class BoomDCacheReqInternal(implicit p: Parameters) extends BoomDCacheReq()(p) with HasL1HellaCacheParameters { // miss info val tag_match = Bool() val old_meta = new L1Metadata val way_en = UInt(nWays.W) // Used in the MSHRs val sdq_id = UInt(log2Ceil(cfg.nSDQ).W) } class BoomMSHR(implicit edge: TLEdgeOut, p: Parameters) extends BoomModule()(p) with HasL1HellaCacheParameters { val io = IO(new Bundle { val id = Input(UInt()) val req_pri_val = Input(Bool()) val req_pri_rdy = Output(Bool()) val req_sec_val = Input(Bool()) val req_sec_rdy = Output(Bool()) val clear_prefetch = Input(Bool()) val brupdate = Input(new BrUpdateInfo) val exception = Input(Bool()) val rob_pnr_idx = Input(UInt(robAddrSz.W)) val rob_head_idx = Input(UInt(robAddrSz.W)) val req = Input(new BoomDCacheReqInternal) val req_is_probe = Input(Bool()) val idx = Output(Valid(UInt())) val way = Output(Valid(UInt())) val tag = Output(Valid(UInt())) val mem_acquire = Decoupled(new TLBundleA(edge.bundle)) val mem_grant = Flipped(Decoupled(new TLBundleD(edge.bundle))) val mem_finish = Decoupled(new TLBundleE(edge.bundle)) val prober_state = Input(Valid(UInt(coreMaxAddrBits.W))) val refill = Decoupled(new L1DataWriteReq) val meta_write = Decoupled(new L1MetaWriteReq) val meta_read = Decoupled(new L1MetaReadReq) val meta_resp = Input(Valid(new L1Metadata)) val wb_req = Decoupled(new WritebackReq(edge.bundle)) // To inform the prefetcher when we are commiting the fetch of this line val commit_val = Output(Bool()) val commit_addr = Output(UInt(coreMaxAddrBits.W)) val commit_coh = Output(new ClientMetadata) // Reading from the line buffer val lb_read = Decoupled(new LineBufferReadReq) val lb_resp = Input(UInt(encRowBits.W)) val lb_write = Decoupled(new LineBufferWriteReq) // Replays go through the cache pipeline again val replay = Decoupled(new BoomDCacheReqInternal) // Resp go straight out to the core val resp = Decoupled(new BoomDCacheResp) // Writeback unit tells us when it is done processing our wb val wb_resp = Input(Bool()) val probe_rdy = Output(Bool()) }) // TODO: Optimize this. We don't want to mess with cache during speculation // s_refill_req : Make a request for a new cache line // s_refill_resp : Store the refill response into our buffer // s_drain_rpq_loads : Drain out loads from the rpq // : If miss was misspeculated, go to s_invalid // s_wb_req : Write back the evicted cache line // s_wb_resp : Finish writing back the evicted cache line // s_meta_write_req : Write the metadata for new cache lne // s_meta_write_resp : val s_invalid :: s_refill_req :: s_refill_resp :: s_drain_rpq_loads :: s_meta_read :: s_meta_resp_1 :: s_meta_resp_2 :: s_meta_clear :: s_wb_meta_read :: s_wb_req :: s_wb_resp :: s_commit_line :: s_drain_rpq :: s_meta_write_req :: s_mem_finish_1 :: s_mem_finish_2 :: s_prefetched :: s_prefetch :: Nil = Enum(18) val state = RegInit(s_invalid) val req = Reg(new BoomDCacheReqInternal) val req_idx = req.addr(untagBits-1, blockOffBits) val req_tag = req.addr >> untagBits val req_block_addr = (req.addr >> blockOffBits) << blockOffBits val req_needs_wb = RegInit(false.B) val new_coh = RegInit(ClientMetadata.onReset) val (_, shrink_param, coh_on_clear) = req.old_meta.coh.onCacheControl(M_FLUSH) val grow_param = new_coh.onAccess(req.uop.mem_cmd)._2 val coh_on_grant = new_coh.onGrant(req.uop.mem_cmd, io.mem_grant.bits.param) // We only accept secondary misses if the original request had sufficient permissions val (cmd_requires_second_acquire, is_hit_again, _, dirtier_coh, dirtier_cmd) = new_coh.onSecondaryAccess(req.uop.mem_cmd, io.req.uop.mem_cmd) val (_, _, refill_done, refill_address_inc) = edge.addr_inc(io.mem_grant) val sec_rdy = (!cmd_requires_second_acquire && !io.req_is_probe && !state.isOneOf(s_invalid, s_meta_write_req, s_mem_finish_1, s_mem_finish_2))// Always accept secondary misses val rpq = Module(new BranchKillableQueue(new BoomDCacheReqInternal, cfg.nRPQ, u => u.uses_ldq, false)) rpq.io.brupdate := io.brupdate rpq.io.flush := io.exception assert(!(state === s_invalid && !rpq.io.empty)) rpq.io.enq.valid := ((io.req_pri_val && io.req_pri_rdy) || (io.req_sec_val && io.req_sec_rdy)) && !isPrefetch(io.req.uop.mem_cmd) rpq.io.enq.bits := io.req rpq.io.deq.ready := false.B val grantack = Reg(Valid(new TLBundleE(edge.bundle))) val refill_ctr = Reg(UInt(log2Ceil(cacheDataBeats).W)) val commit_line = Reg(Bool()) val grant_had_data = Reg(Bool()) val finish_to_prefetch = Reg(Bool()) // Block probes if a tag write we started is still in the pipeline val meta_hazard = RegInit(0.U(2.W)) when (meta_hazard =/= 0.U) { meta_hazard := meta_hazard + 1.U } when (io.meta_write.fire) { meta_hazard := 1.U } io.probe_rdy := (meta_hazard === 0.U && (state.isOneOf(s_invalid, s_refill_req, s_refill_resp, s_drain_rpq_loads) || (state === s_meta_read && grantack.valid))) io.idx.valid := state =/= s_invalid io.tag.valid := state =/= s_invalid io.way.valid := !state.isOneOf(s_invalid, s_prefetch) io.idx.bits := req_idx io.tag.bits := req_tag io.way.bits := req.way_en io.meta_write.valid := false.B io.meta_write.bits := DontCare io.req_pri_rdy := false.B io.req_sec_rdy := sec_rdy && rpq.io.enq.ready io.mem_acquire.valid := false.B io.mem_acquire.bits := DontCare io.refill.valid := false.B io.refill.bits := DontCare io.replay.valid := false.B io.replay.bits := DontCare io.wb_req.valid := false.B io.wb_req.bits := DontCare io.resp.valid := false.B io.resp.bits := DontCare io.commit_val := false.B io.commit_addr := req.addr io.commit_coh := coh_on_grant io.meta_read.valid := false.B io.meta_read.bits := DontCare io.mem_finish.valid := false.B io.mem_finish.bits := DontCare io.lb_write.valid := false.B io.lb_write.bits := DontCare io.lb_read.valid := false.B io.lb_read.bits := DontCare io.mem_grant.ready := false.B when (io.req_sec_val && io.req_sec_rdy) { req.uop.mem_cmd := dirtier_cmd when (is_hit_again) { new_coh := dirtier_coh } } def handle_pri_req(old_state: UInt): UInt = { val new_state = WireInit(old_state) grantack.valid := false.B refill_ctr := 0.U assert(rpq.io.enq.ready) req := io.req val old_coh = io.req.old_meta.coh req_needs_wb := old_coh.onCacheControl(M_FLUSH)._1 // does the line we are evicting need to be written back when (io.req.tag_match) { val (is_hit, _, coh_on_hit) = old_coh.onAccess(io.req.uop.mem_cmd) when (is_hit) { // set dirty bit assert(isWrite(io.req.uop.mem_cmd)) new_coh := coh_on_hit new_state := s_drain_rpq } .otherwise { // upgrade permissions new_coh := old_coh new_state := s_refill_req } } .otherwise { // refill and writeback if necessary new_coh := ClientMetadata.onReset new_state := s_refill_req } new_state } when (state === s_invalid) { io.req_pri_rdy := true.B grant_had_data := false.B when (io.req_pri_val && io.req_pri_rdy) { state := handle_pri_req(state) } } .elsewhen (state === s_refill_req) { io.mem_acquire.valid := true.B // TODO: Use AcquirePerm if just doing permissions acquire io.mem_acquire.bits := edge.AcquireBlock( fromSource = io.id, toAddress = Cat(req_tag, req_idx) << blockOffBits, lgSize = lgCacheBlockBytes.U, growPermissions = grow_param)._2 when (io.mem_acquire.fire) { state := s_refill_resp } } .elsewhen (state === s_refill_resp) { when (edge.hasData(io.mem_grant.bits)) { io.mem_grant.ready := io.lb_write.ready io.lb_write.valid := io.mem_grant.valid io.lb_write.bits.id := io.id io.lb_write.bits.offset := refill_address_inc >> rowOffBits io.lb_write.bits.data := io.mem_grant.bits.data } .otherwise { io.mem_grant.ready := true.B } when (io.mem_grant.fire) { grant_had_data := edge.hasData(io.mem_grant.bits) } when (refill_done) { grantack.valid := edge.isRequest(io.mem_grant.bits) grantack.bits := edge.GrantAck(io.mem_grant.bits) state := Mux(grant_had_data, s_drain_rpq_loads, s_drain_rpq) assert(!(!grant_had_data && req_needs_wb)) commit_line := false.B new_coh := coh_on_grant } } .elsewhen (state === s_drain_rpq_loads) { val drain_load = (isRead(rpq.io.deq.bits.uop.mem_cmd) && !isWrite(rpq.io.deq.bits.uop.mem_cmd) && (rpq.io.deq.bits.uop.mem_cmd =/= M_XLR)) // LR should go through replay // drain all loads for now val rp_addr = Cat(req_tag, req_idx, rpq.io.deq.bits.addr(blockOffBits-1,0)) val word_idx = if (rowWords == 1) 0.U else rp_addr(log2Up(rowWords*coreDataBytes)-1, log2Up(wordBytes)) val data = io.lb_resp val data_word = data >> Cat(word_idx, 0.U(log2Up(coreDataBits).W)) val loadgen = new LoadGen(rpq.io.deq.bits.uop.mem_size, rpq.io.deq.bits.uop.mem_signed, Cat(req_tag, req_idx, rpq.io.deq.bits.addr(blockOffBits-1,0)), data_word, false.B, wordBytes) rpq.io.deq.ready := io.resp.ready && io.lb_read.ready && drain_load io.lb_read.valid := rpq.io.deq.valid && drain_load io.lb_read.bits.id := io.id io.lb_read.bits.offset := rpq.io.deq.bits.addr >> rowOffBits io.resp.valid := rpq.io.deq.valid && io.lb_read.fire && drain_load io.resp.bits.uop := rpq.io.deq.bits.uop io.resp.bits.data := loadgen.data io.resp.bits.is_hella := rpq.io.deq.bits.is_hella when (rpq.io.deq.fire) { commit_line := true.B } .elsewhen (rpq.io.empty && !commit_line) { when (!rpq.io.enq.fire) { state := s_mem_finish_1 finish_to_prefetch := enablePrefetching.B } } .elsewhen (rpq.io.empty || (rpq.io.deq.valid && !drain_load)) { // io.commit_val is for the prefetcher. it tells the prefetcher that this line was correctly acquired // The prefetcher should consider fetching the next line io.commit_val := true.B state := s_meta_read } } .elsewhen (state === s_meta_read) { io.meta_read.valid := !io.prober_state.valid || !grantack.valid || (io.prober_state.bits(untagBits-1,blockOffBits) =/= req_idx) io.meta_read.bits.idx := req_idx io.meta_read.bits.tag := req_tag io.meta_read.bits.way_en := req.way_en when (io.meta_read.fire) { state := s_meta_resp_1 } } .elsewhen (state === s_meta_resp_1) { state := s_meta_resp_2 } .elsewhen (state === s_meta_resp_2) { val needs_wb = io.meta_resp.bits.coh.onCacheControl(M_FLUSH)._1 state := Mux(!io.meta_resp.valid, s_meta_read, // Prober could have nack'd this read Mux(needs_wb, s_meta_clear, s_commit_line)) } .elsewhen (state === s_meta_clear) { io.meta_write.valid := true.B io.meta_write.bits.idx := req_idx io.meta_write.bits.data.coh := coh_on_clear io.meta_write.bits.data.tag := req_tag io.meta_write.bits.way_en := req.way_en when (io.meta_write.fire) { state := s_wb_req } } .elsewhen (state === s_wb_req) { io.wb_req.valid := true.B io.wb_req.bits.tag := req.old_meta.tag io.wb_req.bits.idx := req_idx io.wb_req.bits.param := shrink_param io.wb_req.bits.way_en := req.way_en io.wb_req.bits.source := io.id io.wb_req.bits.voluntary := true.B when (io.wb_req.fire) { state := s_wb_resp } } .elsewhen (state === s_wb_resp) { when (io.wb_resp) { state := s_commit_line } } .elsewhen (state === s_commit_line) { io.lb_read.valid := true.B io.lb_read.bits.id := io.id io.lb_read.bits.offset := refill_ctr io.refill.valid := io.lb_read.fire io.refill.bits.addr := req_block_addr | (refill_ctr << rowOffBits) io.refill.bits.way_en := req.way_en io.refill.bits.wmask := ~(0.U(rowWords.W)) io.refill.bits.data := io.lb_resp when (io.refill.fire) { refill_ctr := refill_ctr + 1.U when (refill_ctr === (cacheDataBeats - 1).U) { state := s_drain_rpq } } } .elsewhen (state === s_drain_rpq) { io.replay <> rpq.io.deq io.replay.bits.way_en := req.way_en io.replay.bits.addr := Cat(req_tag, req_idx, rpq.io.deq.bits.addr(blockOffBits-1,0)) when (io.replay.fire && isWrite(rpq.io.deq.bits.uop.mem_cmd)) { // Set dirty bit val (is_hit, _, coh_on_hit) = new_coh.onAccess(rpq.io.deq.bits.uop.mem_cmd) assert(is_hit, "We still don't have permissions for this store") new_coh := coh_on_hit } when (rpq.io.empty && !rpq.io.enq.valid) { state := s_meta_write_req } } .elsewhen (state === s_meta_write_req) { io.meta_write.valid := true.B io.meta_write.bits.idx := req_idx io.meta_write.bits.data.coh := new_coh io.meta_write.bits.data.tag := req_tag io.meta_write.bits.way_en := req.way_en when (io.meta_write.fire) { state := s_mem_finish_1 finish_to_prefetch := false.B } } .elsewhen (state === s_mem_finish_1) { io.mem_finish.valid := grantack.valid io.mem_finish.bits := grantack.bits when (io.mem_finish.fire || !grantack.valid) { grantack.valid := false.B state := s_mem_finish_2 } } .elsewhen (state === s_mem_finish_2) { state := Mux(finish_to_prefetch, s_prefetch, s_invalid) } .elsewhen (state === s_prefetch) { io.req_pri_rdy := true.B when ((io.req_sec_val && !io.req_sec_rdy) || io.clear_prefetch) { state := s_invalid } .elsewhen (io.req_sec_val && io.req_sec_rdy) { val (is_hit, _, coh_on_hit) = new_coh.onAccess(io.req.uop.mem_cmd) when (is_hit) { // Proceed with refill new_coh := coh_on_hit state := s_meta_read } .otherwise { // Reacquire this line new_coh := ClientMetadata.onReset state := s_refill_req } } .elsewhen (io.req_pri_val && io.req_pri_rdy) { grant_had_data := false.B state := handle_pri_req(state) } } } class BoomIOMSHR(id: Int)(implicit edge: TLEdgeOut, p: Parameters) extends BoomModule()(p) with HasL1HellaCacheParameters { val io = IO(new Bundle { val req = Flipped(Decoupled(new BoomDCacheReq)) val resp = Decoupled(new BoomDCacheResp) val mem_access = Decoupled(new TLBundleA(edge.bundle)) val mem_ack = Flipped(Valid(new TLBundleD(edge.bundle))) // We don't need brupdate in here because uncacheable operations are guaranteed non-speculative }) def beatOffset(addr: UInt) = addr.extract(beatOffBits-1, wordOffBits) def wordFromBeat(addr: UInt, dat: UInt) = { val shift = Cat(beatOffset(addr), 0.U((wordOffBits+log2Ceil(wordBytes)).W)) (dat >> shift)(wordBits-1, 0) } val req = Reg(new BoomDCacheReq) val grant_word = Reg(UInt(wordBits.W)) val s_idle :: s_mem_access :: s_mem_ack :: s_resp :: Nil = Enum(4) val state = RegInit(s_idle) io.req.ready := state === s_idle val loadgen = new LoadGen(req.uop.mem_size, req.uop.mem_signed, req.addr, grant_word, false.B, wordBytes) val a_source = id.U val a_address = req.addr val a_size = req.uop.mem_size val a_data = Fill(beatWords, req.data) val get = edge.Get(a_source, a_address, a_size)._2 val put = edge.Put(a_source, a_address, a_size, a_data)._2 val atomics = if (edge.manager.anySupportLogical) { MuxLookup(req.uop.mem_cmd, (0.U).asTypeOf(new TLBundleA(edge.bundle)))(Array( M_XA_SWAP -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.SWAP)._2, M_XA_XOR -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.XOR) ._2, M_XA_OR -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.OR) ._2, M_XA_AND -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.AND) ._2, M_XA_ADD -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.ADD)._2, M_XA_MIN -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.MIN)._2, M_XA_MAX -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.MAX)._2, M_XA_MINU -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.MINU)._2, M_XA_MAXU -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.MAXU)._2)) } else { // If no managers support atomics, assert fail if processor asks for them assert(state === s_idle || !isAMO(req.uop.mem_cmd)) (0.U).asTypeOf(new TLBundleA(edge.bundle)) } assert(state === s_idle || req.uop.mem_cmd =/= M_XSC) io.mem_access.valid := state === s_mem_access io.mem_access.bits := Mux(isAMO(req.uop.mem_cmd), atomics, Mux(isRead(req.uop.mem_cmd), get, put)) val send_resp = isRead(req.uop.mem_cmd) io.resp.valid := (state === s_resp) && send_resp io.resp.bits.is_hella := req.is_hella io.resp.bits.uop := req.uop io.resp.bits.data := loadgen.data when (io.req.fire) { req := io.req.bits state := s_mem_access } when (io.mem_access.fire) { state := s_mem_ack } when (state === s_mem_ack && io.mem_ack.valid) { state := s_resp when (isRead(req.uop.mem_cmd)) { grant_word := wordFromBeat(req.addr, io.mem_ack.bits.data) } } when (state === s_resp) { when (!send_resp || io.resp.fire) { state := s_idle } } } class LineBufferReadReq(implicit p: Parameters) extends BoomBundle()(p) with HasL1HellaCacheParameters { val id = UInt(log2Ceil(nLBEntries).W) val offset = UInt(log2Ceil(cacheDataBeats).W) def lb_addr = Cat(id, offset) } class LineBufferWriteReq(implicit p: Parameters) extends LineBufferReadReq()(p) { val data = UInt(encRowBits.W) } class LineBufferMetaWriteReq(implicit p: Parameters) extends BoomBundle()(p) { val id = UInt(log2Ceil(nLBEntries).W) val coh = new ClientMetadata val addr = UInt(coreMaxAddrBits.W) } class LineBufferMeta(implicit p: Parameters) extends BoomBundle()(p) with HasL1HellaCacheParameters { val coh = new ClientMetadata val addr = UInt(coreMaxAddrBits.W) } class BoomMSHRFile(implicit edge: TLEdgeOut, p: Parameters) extends BoomModule()(p) with HasL1HellaCacheParameters { val io = IO(new Bundle { val req = Flipped(Vec(memWidth, Decoupled(new BoomDCacheReqInternal))) // Req from s2 of DCache pipe val req_is_probe = Input(Vec(memWidth, Bool())) val resp = Decoupled(new BoomDCacheResp) val secondary_miss = Output(Vec(memWidth, Bool())) val block_hit = Output(Vec(memWidth, Bool())) val brupdate = Input(new BrUpdateInfo) val exception = Input(Bool()) val rob_pnr_idx = Input(UInt(robAddrSz.W)) val rob_head_idx = Input(UInt(robAddrSz.W)) val mem_acquire = Decoupled(new TLBundleA(edge.bundle)) val mem_grant = Flipped(Decoupled(new TLBundleD(edge.bundle))) val mem_finish = Decoupled(new TLBundleE(edge.bundle)) val refill = Decoupled(new L1DataWriteReq) val meta_write = Decoupled(new L1MetaWriteReq) val meta_read = Decoupled(new L1MetaReadReq) val meta_resp = Input(Valid(new L1Metadata)) val replay = Decoupled(new BoomDCacheReqInternal) val prefetch = Decoupled(new BoomDCacheReq) val wb_req = Decoupled(new WritebackReq(edge.bundle)) val prober_state = Input(Valid(UInt(coreMaxAddrBits.W))) val clear_all = Input(Bool()) // Clears all uncommitted MSHRs to prepare for fence val wb_resp = Input(Bool()) val fence_rdy = Output(Bool()) val probe_rdy = Output(Bool()) }) val req_idx = OHToUInt(io.req.map(_.valid)) val req = io.req(req_idx) val req_is_probe = io.req_is_probe(0) for (w <- 0 until memWidth) io.req(w).ready := false.B val prefetcher: DataPrefetcher = if (enablePrefetching) Module(new NLPrefetcher) else Module(new NullPrefetcher) io.prefetch <> prefetcher.io.prefetch val cacheable = edge.manager.supportsAcquireBFast(req.bits.addr, lgCacheBlockBytes.U) // -------------------- // The MSHR SDQ val sdq_val = RegInit(0.U(cfg.nSDQ.W)) val sdq_alloc_id = PriorityEncoder(~sdq_val(cfg.nSDQ-1,0)) val sdq_rdy = !sdq_val.andR val sdq_enq = req.fire && cacheable && isWrite(req.bits.uop.mem_cmd) val sdq = Mem(cfg.nSDQ, UInt(coreDataBits.W)) when (sdq_enq) { sdq(sdq_alloc_id) := req.bits.data } // -------------------- // The LineBuffer Data // Holds refilling lines, prefetched lines val lb = Mem(nLBEntries * cacheDataBeats, UInt(encRowBits.W)) val lb_read_arb = Module(new Arbiter(new LineBufferReadReq, cfg.nMSHRs)) val lb_write_arb = Module(new Arbiter(new LineBufferWriteReq, cfg.nMSHRs)) lb_read_arb.io.out.ready := false.B lb_write_arb.io.out.ready := true.B val lb_read_data = WireInit(0.U(encRowBits.W)) when (lb_write_arb.io.out.fire) { lb.write(lb_write_arb.io.out.bits.lb_addr, lb_write_arb.io.out.bits.data) } .otherwise { lb_read_arb.io.out.ready := true.B when (lb_read_arb.io.out.fire) { lb_read_data := lb.read(lb_read_arb.io.out.bits.lb_addr) } } def widthMap[T <: Data](f: Int => T) = VecInit((0 until memWidth).map(f)) val idx_matches = Wire(Vec(memWidth, Vec(cfg.nMSHRs, Bool()))) val tag_matches = Wire(Vec(memWidth, Vec(cfg.nMSHRs, Bool()))) val way_matches = Wire(Vec(memWidth, Vec(cfg.nMSHRs, Bool()))) val tag_match = widthMap(w => Mux1H(idx_matches(w), tag_matches(w))) val idx_match = widthMap(w => idx_matches(w).reduce(_||_)) val way_match = widthMap(w => Mux1H(idx_matches(w), way_matches(w))) val wb_tag_list = Wire(Vec(cfg.nMSHRs, UInt(tagBits.W))) val meta_write_arb = Module(new Arbiter(new L1MetaWriteReq , cfg.nMSHRs)) val meta_read_arb = Module(new Arbiter(new L1MetaReadReq , cfg.nMSHRs)) val wb_req_arb = Module(new Arbiter(new WritebackReq(edge.bundle), cfg.nMSHRs)) val replay_arb = Module(new Arbiter(new BoomDCacheReqInternal , cfg.nMSHRs)) val resp_arb = Module(new Arbiter(new BoomDCacheResp , cfg.nMSHRs + nIOMSHRs)) val refill_arb = Module(new Arbiter(new L1DataWriteReq , cfg.nMSHRs)) val commit_vals = Wire(Vec(cfg.nMSHRs, Bool())) val commit_addrs = Wire(Vec(cfg.nMSHRs, UInt(coreMaxAddrBits.W))) val commit_cohs = Wire(Vec(cfg.nMSHRs, new ClientMetadata)) var sec_rdy = false.B io.fence_rdy := true.B io.probe_rdy := true.B io.mem_grant.ready := false.B val mshr_alloc_idx = Wire(UInt()) val pri_rdy = WireInit(false.B) val pri_val = req.valid && sdq_rdy && cacheable && !idx_match(req_idx) val mshrs = (0 until cfg.nMSHRs) map { i => val mshr = Module(new BoomMSHR) mshr.io.id := i.U(log2Ceil(cfg.nMSHRs).W) for (w <- 0 until memWidth) { idx_matches(w)(i) := mshr.io.idx.valid && mshr.io.idx.bits === io.req(w).bits.addr(untagBits-1,blockOffBits) tag_matches(w)(i) := mshr.io.tag.valid && mshr.io.tag.bits === io.req(w).bits.addr >> untagBits way_matches(w)(i) := mshr.io.way.valid && mshr.io.way.bits === io.req(w).bits.way_en } wb_tag_list(i) := mshr.io.wb_req.bits.tag mshr.io.req_pri_val := (i.U === mshr_alloc_idx) && pri_val when (i.U === mshr_alloc_idx) { pri_rdy := mshr.io.req_pri_rdy } mshr.io.req_sec_val := req.valid && sdq_rdy && tag_match(req_idx) && idx_matches(req_idx)(i) && cacheable mshr.io.req := req.bits mshr.io.req_is_probe := req_is_probe mshr.io.req.sdq_id := sdq_alloc_id // Clear because of a FENCE, a request to the same idx as a prefetched line, // a probe to that prefetched line, all mshrs are in use mshr.io.clear_prefetch := ((io.clear_all && !req.valid)|| (req.valid && idx_matches(req_idx)(i) && cacheable && !tag_match(req_idx)) || (req_is_probe && idx_matches(req_idx)(i))) mshr.io.brupdate := io.brupdate mshr.io.exception := io.exception mshr.io.rob_pnr_idx := io.rob_pnr_idx mshr.io.rob_head_idx := io.rob_head_idx mshr.io.prober_state := io.prober_state mshr.io.wb_resp := io.wb_resp meta_write_arb.io.in(i) <> mshr.io.meta_write meta_read_arb.io.in(i) <> mshr.io.meta_read mshr.io.meta_resp := io.meta_resp wb_req_arb.io.in(i) <> mshr.io.wb_req replay_arb.io.in(i) <> mshr.io.replay refill_arb.io.in(i) <> mshr.io.refill lb_read_arb.io.in(i) <> mshr.io.lb_read mshr.io.lb_resp := lb_read_data lb_write_arb.io.in(i) <> mshr.io.lb_write commit_vals(i) := mshr.io.commit_val commit_addrs(i) := mshr.io.commit_addr commit_cohs(i) := mshr.io.commit_coh mshr.io.mem_grant.valid := false.B mshr.io.mem_grant.bits := DontCare when (io.mem_grant.bits.source === i.U) { mshr.io.mem_grant <> io.mem_grant } sec_rdy = sec_rdy || (mshr.io.req_sec_rdy && mshr.io.req_sec_val) resp_arb.io.in(i) <> mshr.io.resp when (!mshr.io.req_pri_rdy) { io.fence_rdy := false.B } for (w <- 0 until memWidth) { when (!mshr.io.probe_rdy && idx_matches(w)(i) && io.req_is_probe(w)) { io.probe_rdy := false.B } } mshr } // Try to round-robin the MSHRs val mshr_head = RegInit(0.U(log2Ceil(cfg.nMSHRs).W)) mshr_alloc_idx := RegNext(AgePriorityEncoder(mshrs.map(m=>m.io.req_pri_rdy), mshr_head)) when (pri_rdy && pri_val) { mshr_head := WrapInc(mshr_head, cfg.nMSHRs) } io.meta_write <> meta_write_arb.io.out io.meta_read <> meta_read_arb.io.out io.wb_req <> wb_req_arb.io.out val mmio_alloc_arb = Module(new Arbiter(Bool(), nIOMSHRs)) var mmio_rdy = false.B val mmios = (0 until nIOMSHRs) map { i => val id = cfg.nMSHRs + 1 + i // +1 for wb unit val mshr = Module(new BoomIOMSHR(id)) mmio_alloc_arb.io.in(i).valid := mshr.io.req.ready mmio_alloc_arb.io.in(i).bits := DontCare mshr.io.req.valid := mmio_alloc_arb.io.in(i).ready mshr.io.req.bits := req.bits mmio_rdy = mmio_rdy || mshr.io.req.ready mshr.io.mem_ack.bits := io.mem_grant.bits mshr.io.mem_ack.valid := io.mem_grant.valid && io.mem_grant.bits.source === id.U when (io.mem_grant.bits.source === id.U) { io.mem_grant.ready := true.B } resp_arb.io.in(cfg.nMSHRs + i) <> mshr.io.resp when (!mshr.io.req.ready) { io.fence_rdy := false.B } mshr } mmio_alloc_arb.io.out.ready := req.valid && !cacheable TLArbiter.lowestFromSeq(edge, io.mem_acquire, mshrs.map(_.io.mem_acquire) ++ mmios.map(_.io.mem_access)) TLArbiter.lowestFromSeq(edge, io.mem_finish, mshrs.map(_.io.mem_finish)) val respq = Module(new BranchKillableQueue(new BoomDCacheResp, 4, u => u.uses_ldq, flow = false)) respq.io.brupdate := io.brupdate respq.io.flush := io.exception respq.io.enq <> resp_arb.io.out io.resp <> respq.io.deq for (w <- 0 until memWidth) { io.req(w).ready := (w.U === req_idx) && Mux(!cacheable, mmio_rdy, sdq_rdy && Mux(idx_match(w), tag_match(w) && sec_rdy, pri_rdy)) io.secondary_miss(w) := idx_match(w) && way_match(w) && !tag_match(w) io.block_hit(w) := idx_match(w) && tag_match(w) } io.refill <> refill_arb.io.out val free_sdq = io.replay.fire && isWrite(io.replay.bits.uop.mem_cmd) io.replay <> replay_arb.io.out io.replay.bits.data := sdq(replay_arb.io.out.bits.sdq_id) when (io.replay.valid || sdq_enq) { sdq_val := sdq_val & ~(UIntToOH(replay_arb.io.out.bits.sdq_id) & Fill(cfg.nSDQ, free_sdq)) | PriorityEncoderOH(~sdq_val(cfg.nSDQ-1,0)) & Fill(cfg.nSDQ, sdq_enq) } prefetcher.io.mshr_avail := RegNext(pri_rdy) prefetcher.io.req_val := RegNext(commit_vals.reduce(_||_)) prefetcher.io.req_addr := RegNext(Mux1H(commit_vals, commit_addrs)) prefetcher.io.req_coh := RegNext(Mux1H(commit_vals, commit_cohs)) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } } File AMOALU.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters class StoreGen(typ: UInt, addr: UInt, dat: UInt, maxSize: Int) { val size = Wire(UInt(log2Up(log2Up(maxSize)+1).W)) size := typ val dat_padded = dat.pad(maxSize*8) def misaligned: Bool = (addr & ((1.U << size) - 1.U)(log2Up(maxSize)-1,0)).orR def mask = { var res = 1.U for (i <- 0 until log2Up(maxSize)) { val upper = Mux(addr(i), res, 0.U) | Mux(size >= (i+1).U, ((BigInt(1) << (1 << i))-1).U, 0.U) val lower = Mux(addr(i), 0.U, res) res = Cat(upper, lower) } res } protected def genData(i: Int): UInt = if (i >= log2Up(maxSize)) dat_padded else Mux(size === i.U, Fill(1 << (log2Up(maxSize)-i), dat_padded((8 << i)-1,0)), genData(i+1)) def data = genData(0) def wordData = genData(2) } class LoadGen(typ: UInt, signed: Bool, addr: UInt, dat: UInt, zero: Bool, maxSize: Int) { private val size = new StoreGen(typ, addr, dat, maxSize).size private def genData(logMinSize: Int): UInt = { var res = dat for (i <- log2Up(maxSize)-1 to logMinSize by -1) { val pos = 8 << i val shifted = Mux(addr(i), res(2*pos-1,pos), res(pos-1,0)) val doZero = (i == 0).B && zero val zeroed = Mux(doZero, 0.U, shifted) res = Cat(Mux(size === i.U || doZero, Fill(8*maxSize-pos, signed && zeroed(pos-1)), res(8*maxSize-1,pos)), zeroed) } res } def wordData = genData(2) def data = genData(0) } class AMOALU(operandBits: Int)(implicit p: Parameters) extends Module { val minXLen = 32 val widths = (0 to log2Ceil(operandBits / minXLen)).map(minXLen << _) val io = IO(new Bundle { val mask = Input(UInt((operandBits / 8).W)) val cmd = Input(UInt(M_SZ.W)) val lhs = Input(UInt(operandBits.W)) val rhs = Input(UInt(operandBits.W)) val out = Output(UInt(operandBits.W)) val out_unmasked = Output(UInt(operandBits.W)) }) val max = io.cmd === M_XA_MAX || io.cmd === M_XA_MAXU val min = io.cmd === M_XA_MIN || io.cmd === M_XA_MINU val add = io.cmd === M_XA_ADD val logic_and = io.cmd === M_XA_OR || io.cmd === M_XA_AND val logic_xor = io.cmd === M_XA_XOR || io.cmd === M_XA_OR val adder_out = { // partition the carry chain to support sub-xLen addition val mask = ~(0.U(operandBits.W) +: widths.init.map(w => !io.mask(w/8-1) << (w-1))).reduce(_|_) (io.lhs & mask) + (io.rhs & mask) } val less = { // break up the comparator so the lower parts will be CSE'd def isLessUnsigned(x: UInt, y: UInt, n: Int): Bool = { if (n == minXLen) x(n-1, 0) < y(n-1, 0) else x(n-1, n/2) < y(n-1, n/2) || x(n-1, n/2) === y(n-1, n/2) && isLessUnsigned(x, y, n/2) } def isLess(x: UInt, y: UInt, n: Int): Bool = { val signed = { val mask = M_XA_MIN ^ M_XA_MINU (io.cmd & mask) === (M_XA_MIN & mask) } Mux(x(n-1) === y(n-1), isLessUnsigned(x, y, n), Mux(signed, x(n-1), y(n-1))) } PriorityMux(widths.reverse.map(w => (io.mask(w/8/2), isLess(io.lhs, io.rhs, w)))) } val minmax = Mux(Mux(less, min, max), io.lhs, io.rhs) val logic = Mux(logic_and, io.lhs & io.rhs, 0.U) | Mux(logic_xor, io.lhs ^ io.rhs, 0.U) val out = Mux(add, adder_out, Mux(logic_and || logic_xor, logic, minmax)) val wmask = FillInterleaved(8, io.mask) io.out := wmask & out | ~wmask & io.lhs io.out_unmasked := out }

module BoomMSHR_5( // @[mshrs.scala:36:7] input clock, // @[mshrs.scala:36:7] input reset, // @[mshrs.scala:36:7] input io_req_pri_val, // @[mshrs.scala:39:14] output io_req_pri_rdy, // @[mshrs.scala:39:14] input io_req_sec_val, // @[mshrs.scala:39:14] output io_req_sec_rdy, // @[mshrs.scala:39:14] input io_clear_prefetch, // @[mshrs.scala:39:14] input [15:0] io_brupdate_b1_resolve_mask, // @[mshrs.scala:39:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[mshrs.scala:39:14] input [6:0] io_brupdate_b2_uop_uopc, // @[mshrs.scala:39:14] input [31:0] io_brupdate_b2_uop_inst, // @[mshrs.scala:39:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_is_rvc, // @[mshrs.scala:39:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[mshrs.scala:39:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[mshrs.scala:39:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[mshrs.scala:39:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[mshrs.scala:39:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[mshrs.scala:39:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[mshrs.scala:39:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[mshrs.scala:39:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[mshrs.scala:39:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_ctrl_is_load, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_ctrl_is_std, // @[mshrs.scala:39:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_is_br, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_is_jalr, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_is_jal, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_is_sfb, // @[mshrs.scala:39:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[mshrs.scala:39:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[mshrs.scala:39:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_edge_inst, // @[mshrs.scala:39:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_taken, // @[mshrs.scala:39:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[mshrs.scala:39:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[mshrs.scala:39:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[mshrs.scala:39:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[mshrs.scala:39:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[mshrs.scala:39:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[mshrs.scala:39:14] input [6:0] io_brupdate_b2_uop_pdst, // @[mshrs.scala:39:14] input [6:0] io_brupdate_b2_uop_prs1, // @[mshrs.scala:39:14] input [6:0] io_brupdate_b2_uop_prs2, // @[mshrs.scala:39:14] input [6:0] io_brupdate_b2_uop_prs3, // @[mshrs.scala:39:14] input [4:0] io_brupdate_b2_uop_ppred, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_prs1_busy, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_prs2_busy, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_prs3_busy, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_ppred_busy, // @[mshrs.scala:39:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_exception, // @[mshrs.scala:39:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_bypassable, // @[mshrs.scala:39:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[mshrs.scala:39:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_mem_signed, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_is_fence, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_is_fencei, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_is_amo, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_uses_ldq, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_uses_stq, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_is_unique, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_flush_on_commit, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[mshrs.scala:39:14] input [5:0] io_brupdate_b2_uop_ldst, // @[mshrs.scala:39:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[mshrs.scala:39:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[mshrs.scala:39:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_ldst_val, // @[mshrs.scala:39:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[mshrs.scala:39:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[mshrs.scala:39:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_frs3_en, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_fp_val, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_fp_single, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_bp_debug_if, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[mshrs.scala:39:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[mshrs.scala:39:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[mshrs.scala:39:14] input io_brupdate_b2_valid, // @[mshrs.scala:39:14] input io_brupdate_b2_mispredict, // @[mshrs.scala:39:14] input io_brupdate_b2_taken, // @[mshrs.scala:39:14] input [2:0] io_brupdate_b2_cfi_type, // @[mshrs.scala:39:14] input [1:0] io_brupdate_b2_pc_sel, // @[mshrs.scala:39:14] input [39:0] io_brupdate_b2_jalr_target, // @[mshrs.scala:39:14] input [20:0] io_brupdate_b2_target_offset, // @[mshrs.scala:39:14] input io_exception, // @[mshrs.scala:39:14] input [6:0] io_rob_pnr_idx, // @[mshrs.scala:39:14] input [6:0] io_rob_head_idx, // @[mshrs.scala:39:14] input [6:0] io_req_uop_uopc, // @[mshrs.scala:39:14] input [31:0] io_req_uop_inst, // @[mshrs.scala:39:14] input [31:0] io_req_uop_debug_inst, // @[mshrs.scala:39:14] input io_req_uop_is_rvc, // @[mshrs.scala:39:14] input [39:0] io_req_uop_debug_pc, // @[mshrs.scala:39:14] input [2:0] io_req_uop_iq_type, // @[mshrs.scala:39:14] input [9:0] io_req_uop_fu_code, // @[mshrs.scala:39:14] input [3:0] io_req_uop_ctrl_br_type, // @[mshrs.scala:39:14] input [1:0] io_req_uop_ctrl_op1_sel, // @[mshrs.scala:39:14] input [2:0] io_req_uop_ctrl_op2_sel, // @[mshrs.scala:39:14] input [2:0] io_req_uop_ctrl_imm_sel, // @[mshrs.scala:39:14] input [4:0] io_req_uop_ctrl_op_fcn, // @[mshrs.scala:39:14] input io_req_uop_ctrl_fcn_dw, // @[mshrs.scala:39:14] input [2:0] io_req_uop_ctrl_csr_cmd, // @[mshrs.scala:39:14] input io_req_uop_ctrl_is_load, // @[mshrs.scala:39:14] input io_req_uop_ctrl_is_sta, // @[mshrs.scala:39:14] input io_req_uop_ctrl_is_std, // @[mshrs.scala:39:14] input [1:0] io_req_uop_iw_state, // @[mshrs.scala:39:14] input io_req_uop_iw_p1_poisoned, // @[mshrs.scala:39:14] input io_req_uop_iw_p2_poisoned, // @[mshrs.scala:39:14] input io_req_uop_is_br, // @[mshrs.scala:39:14] input io_req_uop_is_jalr, // @[mshrs.scala:39:14] input io_req_uop_is_jal, // @[mshrs.scala:39:14] input io_req_uop_is_sfb, // @[mshrs.scala:39:14] input [15:0] io_req_uop_br_mask, // @[mshrs.scala:39:14] input [3:0] io_req_uop_br_tag, // @[mshrs.scala:39:14] input [4:0] io_req_uop_ftq_idx, // @[mshrs.scala:39:14] input io_req_uop_edge_inst, // @[mshrs.scala:39:14] input [5:0] io_req_uop_pc_lob, // @[mshrs.scala:39:14] input io_req_uop_taken, // @[mshrs.scala:39:14] input [19:0] io_req_uop_imm_packed, // @[mshrs.scala:39:14] input [11:0] io_req_uop_csr_addr, // @[mshrs.scala:39:14] input [6:0] io_req_uop_rob_idx, // @[mshrs.scala:39:14] input [4:0] io_req_uop_ldq_idx, // @[mshrs.scala:39:14] input [4:0] io_req_uop_stq_idx, // @[mshrs.scala:39:14] input [1:0] io_req_uop_rxq_idx, // @[mshrs.scala:39:14] input [6:0] io_req_uop_pdst, // @[mshrs.scala:39:14] input [6:0] io_req_uop_prs1, // @[mshrs.scala:39:14] input [6:0] io_req_uop_prs2, // @[mshrs.scala:39:14] input [6:0] io_req_uop_prs3, // @[mshrs.scala:39:14] input [4:0] io_req_uop_ppred, // @[mshrs.scala:39:14] input io_req_uop_prs1_busy, // @[mshrs.scala:39:14] input io_req_uop_prs2_busy, // @[mshrs.scala:39:14] input io_req_uop_prs3_busy, // @[mshrs.scala:39:14] input io_req_uop_ppred_busy, // @[mshrs.scala:39:14] input [6:0] io_req_uop_stale_pdst, // @[mshrs.scala:39:14] input io_req_uop_exception, // @[mshrs.scala:39:14] input [63:0] io_req_uop_exc_cause, // @[mshrs.scala:39:14] input io_req_uop_bypassable, // @[mshrs.scala:39:14] input [4:0] io_req_uop_mem_cmd, // @[mshrs.scala:39:14] input [1:0] io_req_uop_mem_size, // @[mshrs.scala:39:14] input io_req_uop_mem_signed, // @[mshrs.scala:39:14] input io_req_uop_is_fence, // @[mshrs.scala:39:14] input io_req_uop_is_fencei, // @[mshrs.scala:39:14] input io_req_uop_is_amo, // @[mshrs.scala:39:14] input io_req_uop_uses_ldq, // @[mshrs.scala:39:14] input io_req_uop_uses_stq, // @[mshrs.scala:39:14] input io_req_uop_is_sys_pc2epc, // @[mshrs.scala:39:14] input io_req_uop_is_unique, // @[mshrs.scala:39:14] input io_req_uop_flush_on_commit, // @[mshrs.scala:39:14] input io_req_uop_ldst_is_rs1, // @[mshrs.scala:39:14] input [5:0] io_req_uop_ldst, // @[mshrs.scala:39:14] input [5:0] io_req_uop_lrs1, // @[mshrs.scala:39:14] input [5:0] io_req_uop_lrs2, // @[mshrs.scala:39:14] input [5:0] io_req_uop_lrs3, // @[mshrs.scala:39:14] input io_req_uop_ldst_val, // @[mshrs.scala:39:14] input [1:0] io_req_uop_dst_rtype, // @[mshrs.scala:39:14] input [1:0] io_req_uop_lrs1_rtype, // @[mshrs.scala:39:14] input [1:0] io_req_uop_lrs2_rtype, // @[mshrs.scala:39:14] input io_req_uop_frs3_en, // @[mshrs.scala:39:14] input io_req_uop_fp_val, // @[mshrs.scala:39:14] input io_req_uop_fp_single, // @[mshrs.scala:39:14] input io_req_uop_xcpt_pf_if, // @[mshrs.scala:39:14] input io_req_uop_xcpt_ae_if, // @[mshrs.scala:39:14] input io_req_uop_xcpt_ma_if, // @[mshrs.scala:39:14] input io_req_uop_bp_debug_if, // @[mshrs.scala:39:14] input io_req_uop_bp_xcpt_if, // @[mshrs.scala:39:14] input [1:0] io_req_uop_debug_fsrc, // @[mshrs.scala:39:14] input [1:0] io_req_uop_debug_tsrc, // @[mshrs.scala:39:14] input [39:0] io_req_addr, // @[mshrs.scala:39:14] input [63:0] io_req_data, // @[mshrs.scala:39:14] input io_req_is_hella, // @[mshrs.scala:39:14] input io_req_tag_match, // @[mshrs.scala:39:14] input [1:0] io_req_old_meta_coh_state, // @[mshrs.scala:39:14] input [19:0] io_req_old_meta_tag, // @[mshrs.scala:39:14] input [7:0] io_req_way_en, // @[mshrs.scala:39:14] input [4:0] io_req_sdq_id, // @[mshrs.scala:39:14] input io_req_is_probe, // @[mshrs.scala:39:14] output io_idx_valid, // @[mshrs.scala:39:14] output [5:0] io_idx_bits, // @[mshrs.scala:39:14] output io_way_valid, // @[mshrs.scala:39:14] output [7:0] io_way_bits, // @[mshrs.scala:39:14] output io_tag_valid, // @[mshrs.scala:39:14] output [27:0] io_tag_bits, // @[mshrs.scala:39:14] input io_mem_acquire_ready, // @[mshrs.scala:39:14] output io_mem_acquire_valid, // @[mshrs.scala:39:14] output [2:0] io_mem_acquire_bits_param, // @[mshrs.scala:39:14] output [31:0] io_mem_acquire_bits_address, // @[mshrs.scala:39:14] output io_mem_grant_ready, // @[mshrs.scala:39:14] input io_mem_grant_valid, // @[mshrs.scala:39:14] input [2:0] io_mem_grant_bits_opcode, // @[mshrs.scala:39:14] input [1:0] io_mem_grant_bits_param, // @[mshrs.scala:39:14] input [3:0] io_mem_grant_bits_size, // @[mshrs.scala:39:14] input [2:0] io_mem_grant_bits_source, // @[mshrs.scala:39:14] input [3:0] io_mem_grant_bits_sink, // @[mshrs.scala:39:14] input io_mem_grant_bits_denied, // @[mshrs.scala:39:14] input [127:0] io_mem_grant_bits_data, // @[mshrs.scala:39:14] input io_mem_grant_bits_corrupt, // @[mshrs.scala:39:14] input io_mem_finish_ready, // @[mshrs.scala:39:14] output io_mem_finish_valid, // @[mshrs.scala:39:14] output [3:0] io_mem_finish_bits_sink, // @[mshrs.scala:39:14] input io_prober_state_valid, // @[mshrs.scala:39:14] input [39:0] io_prober_state_bits, // @[mshrs.scala:39:14] input io_refill_ready, // @[mshrs.scala:39:14] output io_refill_valid, // @[mshrs.scala:39:14] output [7:0] io_refill_bits_way_en, // @[mshrs.scala:39:14] output [11:0] io_refill_bits_addr, // @[mshrs.scala:39:14] output [127:0] io_refill_bits_data, // @[mshrs.scala:39:14] input io_meta_write_ready, // @[mshrs.scala:39:14] output io_meta_write_valid, // @[mshrs.scala:39:14] output [5:0] io_meta_write_bits_idx, // @[mshrs.scala:39:14] output [7:0] io_meta_write_bits_way_en, // @[mshrs.scala:39:14] output [1:0] io_meta_write_bits_data_coh_state, // @[mshrs.scala:39:14] output [19:0] io_meta_write_bits_data_tag, // @[mshrs.scala:39:14] input io_meta_read_ready, // @[mshrs.scala:39:14] output io_meta_read_valid, // @[mshrs.scala:39:14] output [5:0] io_meta_read_bits_idx, // @[mshrs.scala:39:14] output [7:0] io_meta_read_bits_way_en, // @[mshrs.scala:39:14] output [19:0] io_meta_read_bits_tag, // @[mshrs.scala:39:14] input io_meta_resp_valid, // @[mshrs.scala:39:14] input [1:0] io_meta_resp_bits_coh_state, // @[mshrs.scala:39:14] input [19:0] io_meta_resp_bits_tag, // @[mshrs.scala:39:14] input io_wb_req_ready, // @[mshrs.scala:39:14] output io_wb_req_valid, // @[mshrs.scala:39:14] output [19:0] io_wb_req_bits_tag, // @[mshrs.scala:39:14] output [5:0] io_wb_req_bits_idx, // @[mshrs.scala:39:14] output [2:0] io_wb_req_bits_param, // @[mshrs.scala:39:14] output [7:0] io_wb_req_bits_way_en, // @[mshrs.scala:39:14] output io_commit_val, // @[mshrs.scala:39:14] output [39:0] io_commit_addr, // @[mshrs.scala:39:14] output [1:0] io_commit_coh_state, // @[mshrs.scala:39:14] input io_lb_read_ready, // @[mshrs.scala:39:14] output io_lb_read_valid, // @[mshrs.scala:39:14] output [1:0] io_lb_read_bits_offset, // @[mshrs.scala:39:14] input [127:0] io_lb_resp, // @[mshrs.scala:39:14] input io_lb_write_ready, // @[mshrs.scala:39:14] output io_lb_write_valid, // @[mshrs.scala:39:14] output [1:0] io_lb_write_bits_offset, // @[mshrs.scala:39:14] output [127:0] io_lb_write_bits_data, // @[mshrs.scala:39:14] input io_replay_ready, // @[mshrs.scala:39:14] output io_replay_valid, // @[mshrs.scala:39:14] output [6:0] io_replay_bits_uop_uopc, // @[mshrs.scala:39:14] output [31:0] io_replay_bits_uop_inst, // @[mshrs.scala:39:14] output [31:0] io_replay_bits_uop_debug_inst, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_rvc, // @[mshrs.scala:39:14] output [39:0] io_replay_bits_uop_debug_pc, // @[mshrs.scala:39:14] output [2:0] io_replay_bits_uop_iq_type, // @[mshrs.scala:39:14] output [9:0] io_replay_bits_uop_fu_code, // @[mshrs.scala:39:14] output [3:0] io_replay_bits_uop_ctrl_br_type, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_ctrl_op1_sel, // @[mshrs.scala:39:14] output [2:0] io_replay_bits_uop_ctrl_op2_sel, // @[mshrs.scala:39:14] output [2:0] io_replay_bits_uop_ctrl_imm_sel, // @[mshrs.scala:39:14] output [4:0] io_replay_bits_uop_ctrl_op_fcn, // @[mshrs.scala:39:14] output io_replay_bits_uop_ctrl_fcn_dw, // @[mshrs.scala:39:14] output [2:0] io_replay_bits_uop_ctrl_csr_cmd, // @[mshrs.scala:39:14] output io_replay_bits_uop_ctrl_is_load, // @[mshrs.scala:39:14] output io_replay_bits_uop_ctrl_is_sta, // @[mshrs.scala:39:14] output io_replay_bits_uop_ctrl_is_std, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_iw_state, // @[mshrs.scala:39:14] output io_replay_bits_uop_iw_p1_poisoned, // @[mshrs.scala:39:14] output io_replay_bits_uop_iw_p2_poisoned, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_br, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_jalr, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_jal, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_sfb, // @[mshrs.scala:39:14] output [15:0] io_replay_bits_uop_br_mask, // @[mshrs.scala:39:14] output [3:0] io_replay_bits_uop_br_tag, // @[mshrs.scala:39:14] output [4:0] io_replay_bits_uop_ftq_idx, // @[mshrs.scala:39:14] output io_replay_bits_uop_edge_inst, // @[mshrs.scala:39:14] output [5:0] io_replay_bits_uop_pc_lob, // @[mshrs.scala:39:14] output io_replay_bits_uop_taken, // @[mshrs.scala:39:14] output [19:0] io_replay_bits_uop_imm_packed, // @[mshrs.scala:39:14] output [11:0] io_replay_bits_uop_csr_addr, // @[mshrs.scala:39:14] output [6:0] io_replay_bits_uop_rob_idx, // @[mshrs.scala:39:14] output [4:0] io_replay_bits_uop_ldq_idx, // @[mshrs.scala:39:14] output [4:0] io_replay_bits_uop_stq_idx, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_rxq_idx, // @[mshrs.scala:39:14] output [6:0] io_replay_bits_uop_pdst, // @[mshrs.scala:39:14] output [6:0] io_replay_bits_uop_prs1, // @[mshrs.scala:39:14] output [6:0] io_replay_bits_uop_prs2, // @[mshrs.scala:39:14] output [6:0] io_replay_bits_uop_prs3, // @[mshrs.scala:39:14] output [4:0] io_replay_bits_uop_ppred, // @[mshrs.scala:39:14] output io_replay_bits_uop_prs1_busy, // @[mshrs.scala:39:14] output io_replay_bits_uop_prs2_busy, // @[mshrs.scala:39:14] output io_replay_bits_uop_prs3_busy, // @[mshrs.scala:39:14] output io_replay_bits_uop_ppred_busy, // @[mshrs.scala:39:14] output [6:0] io_replay_bits_uop_stale_pdst, // @[mshrs.scala:39:14] output io_replay_bits_uop_exception, // @[mshrs.scala:39:14] output [63:0] io_replay_bits_uop_exc_cause, // @[mshrs.scala:39:14] output io_replay_bits_uop_bypassable, // @[mshrs.scala:39:14] output [4:0] io_replay_bits_uop_mem_cmd, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_mem_size, // @[mshrs.scala:39:14] output io_replay_bits_uop_mem_signed, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_fence, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_fencei, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_amo, // @[mshrs.scala:39:14] output io_replay_bits_uop_uses_ldq, // @[mshrs.scala:39:14] output io_replay_bits_uop_uses_stq, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_sys_pc2epc, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_unique, // @[mshrs.scala:39:14] output io_replay_bits_uop_flush_on_commit, // @[mshrs.scala:39:14] output io_replay_bits_uop_ldst_is_rs1, // @[mshrs.scala:39:14] output [5:0] io_replay_bits_uop_ldst, // @[mshrs.scala:39:14] output [5:0] io_replay_bits_uop_lrs1, // @[mshrs.scala:39:14] output [5:0] io_replay_bits_uop_lrs2, // @[mshrs.scala:39:14] output [5:0] io_replay_bits_uop_lrs3, // @[mshrs.scala:39:14] output io_replay_bits_uop_ldst_val, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_dst_rtype, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_lrs1_rtype, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_lrs2_rtype, // @[mshrs.scala:39:14] output io_replay_bits_uop_frs3_en, // @[mshrs.scala:39:14] output io_replay_bits_uop_fp_val, // @[mshrs.scala:39:14] output io_replay_bits_uop_fp_single, // @[mshrs.scala:39:14] output io_replay_bits_uop_xcpt_pf_if, // @[mshrs.scala:39:14] output io_replay_bits_uop_xcpt_ae_if, // @[mshrs.scala:39:14] output io_replay_bits_uop_xcpt_ma_if, // @[mshrs.scala:39:14] output io_replay_bits_uop_bp_debug_if, // @[mshrs.scala:39:14] output io_replay_bits_uop_bp_xcpt_if, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_debug_fsrc, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_debug_tsrc, // @[mshrs.scala:39:14] output [39:0] io_replay_bits_addr, // @[mshrs.scala:39:14] output [63:0] io_replay_bits_data, // @[mshrs.scala:39:14] output io_replay_bits_is_hella, // @[mshrs.scala:39:14] output io_replay_bits_tag_match, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_old_meta_coh_state, // @[mshrs.scala:39:14] output [19:0] io_replay_bits_old_meta_tag, // @[mshrs.scala:39:14] output [7:0] io_replay_bits_way_en, // @[mshrs.scala:39:14] output [4:0] io_replay_bits_sdq_id, // @[mshrs.scala:39:14] input io_resp_ready, // @[mshrs.scala:39:14] output io_resp_valid, // @[mshrs.scala:39:14] output [6:0] io_resp_bits_uop_uopc, // @[mshrs.scala:39:14] output [31:0] io_resp_bits_uop_inst, // @[mshrs.scala:39:14] output [31:0] io_resp_bits_uop_debug_inst, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_rvc, // @[mshrs.scala:39:14] output [39:0] io_resp_bits_uop_debug_pc, // @[mshrs.scala:39:14] output [2:0] io_resp_bits_uop_iq_type, // @[mshrs.scala:39:14] output [9:0] io_resp_bits_uop_fu_code, // @[mshrs.scala:39:14] output [3:0] io_resp_bits_uop_ctrl_br_type, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_ctrl_op1_sel, // @[mshrs.scala:39:14] output [2:0] io_resp_bits_uop_ctrl_op2_sel, // @[mshrs.scala:39:14] output [2:0] io_resp_bits_uop_ctrl_imm_sel, // @[mshrs.scala:39:14] output [4:0] io_resp_bits_uop_ctrl_op_fcn, // @[mshrs.scala:39:14] output io_resp_bits_uop_ctrl_fcn_dw, // @[mshrs.scala:39:14] output [2:0] io_resp_bits_uop_ctrl_csr_cmd, // @[mshrs.scala:39:14] output io_resp_bits_uop_ctrl_is_load, // @[mshrs.scala:39:14] output io_resp_bits_uop_ctrl_is_sta, // @[mshrs.scala:39:14] output io_resp_bits_uop_ctrl_is_std, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_iw_state, // @[mshrs.scala:39:14] output io_resp_bits_uop_iw_p1_poisoned, // @[mshrs.scala:39:14] output io_resp_bits_uop_iw_p2_poisoned, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_br, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_jalr, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_jal, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_sfb, // @[mshrs.scala:39:14] output [15:0] io_resp_bits_uop_br_mask, // @[mshrs.scala:39:14] output [3:0] io_resp_bits_uop_br_tag, // @[mshrs.scala:39:14] output [4:0] io_resp_bits_uop_ftq_idx, // @[mshrs.scala:39:14] output io_resp_bits_uop_edge_inst, // @[mshrs.scala:39:14] output [5:0] io_resp_bits_uop_pc_lob, // @[mshrs.scala:39:14] output io_resp_bits_uop_taken, // @[mshrs.scala:39:14] output [19:0] io_resp_bits_uop_imm_packed, // @[mshrs.scala:39:14] output [11:0] io_resp_bits_uop_csr_addr, // @[mshrs.scala:39:14] output [6:0] io_resp_bits_uop_rob_idx, // @[mshrs.scala:39:14] output [4:0] io_resp_bits_uop_ldq_idx, // @[mshrs.scala:39:14] output [4:0] io_resp_bits_uop_stq_idx, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_rxq_idx, // @[mshrs.scala:39:14] output [6:0] io_resp_bits_uop_pdst, // @[mshrs.scala:39:14] output [6:0] io_resp_bits_uop_prs1, // @[mshrs.scala:39:14] output [6:0] io_resp_bits_uop_prs2, // @[mshrs.scala:39:14] output [6:0] io_resp_bits_uop_prs3, // @[mshrs.scala:39:14] output [4:0] io_resp_bits_uop_ppred, // @[mshrs.scala:39:14] output io_resp_bits_uop_prs1_busy, // @[mshrs.scala:39:14] output io_resp_bits_uop_prs2_busy, // @[mshrs.scala:39:14] output io_resp_bits_uop_prs3_busy, // @[mshrs.scala:39:14] output io_resp_bits_uop_ppred_busy, // @[mshrs.scala:39:14] output [6:0] io_resp_bits_uop_stale_pdst, // @[mshrs.scala:39:14] output io_resp_bits_uop_exception, // @[mshrs.scala:39:14] output [63:0] io_resp_bits_uop_exc_cause, // @[mshrs.scala:39:14] output io_resp_bits_uop_bypassable, // @[mshrs.scala:39:14] output [4:0] io_resp_bits_uop_mem_cmd, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_mem_size, // @[mshrs.scala:39:14] output io_resp_bits_uop_mem_signed, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_fence, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_fencei, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_amo, // @[mshrs.scala:39:14] output io_resp_bits_uop_uses_ldq, // @[mshrs.scala:39:14] output io_resp_bits_uop_uses_stq, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_sys_pc2epc, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_unique, // @[mshrs.scala:39:14] output io_resp_bits_uop_flush_on_commit, // @[mshrs.scala:39:14] output io_resp_bits_uop_ldst_is_rs1, // @[mshrs.scala:39:14] output [5:0] io_resp_bits_uop_ldst, // @[mshrs.scala:39:14] output [5:0] io_resp_bits_uop_lrs1, // @[mshrs.scala:39:14] output [5:0] io_resp_bits_uop_lrs2, // @[mshrs.scala:39:14] output [5:0] io_resp_bits_uop_lrs3, // @[mshrs.scala:39:14] output io_resp_bits_uop_ldst_val, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_dst_rtype, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_lrs1_rtype, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_lrs2_rtype, // @[mshrs.scala:39:14] output io_resp_bits_uop_frs3_en, // @[mshrs.scala:39:14] output io_resp_bits_uop_fp_val, // @[mshrs.scala:39:14] output io_resp_bits_uop_fp_single, // @[mshrs.scala:39:14] output io_resp_bits_uop_xcpt_pf_if, // @[mshrs.scala:39:14] output io_resp_bits_uop_xcpt_ae_if, // @[mshrs.scala:39:14] output io_resp_bits_uop_xcpt_ma_if, // @[mshrs.scala:39:14] output io_resp_bits_uop_bp_debug_if, // @[mshrs.scala:39:14] output io_resp_bits_uop_bp_xcpt_if, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_debug_fsrc, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_debug_tsrc, // @[mshrs.scala:39:14] output [63:0] io_resp_bits_data, // @[mshrs.scala:39:14] output io_resp_bits_is_hella, // @[mshrs.scala:39:14] input io_wb_resp, // @[mshrs.scala:39:14] output io_probe_rdy // @[mshrs.scala:39:14] ); wire rpq_io_deq_ready; // @[mshrs.scala:135:20, :215:30, :222:40, :233:41, :256:45] wire _rpq_io_enq_ready; // @[mshrs.scala:128:19] wire _rpq_io_deq_valid; // @[mshrs.scala:128:19] wire [6:0] _rpq_io_deq_bits_uop_uopc; // @[mshrs.scala:128:19] wire [31:0] _rpq_io_deq_bits_uop_inst; // @[mshrs.scala:128:19] wire [31:0] _rpq_io_deq_bits_uop_debug_inst; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_rvc; // @[mshrs.scala:128:19] wire [39:0] _rpq_io_deq_bits_uop_debug_pc; // @[mshrs.scala:128:19] wire [2:0] _rpq_io_deq_bits_uop_iq_type; // @[mshrs.scala:128:19] wire [9:0] _rpq_io_deq_bits_uop_fu_code; // @[mshrs.scala:128:19] wire [3:0] _rpq_io_deq_bits_uop_ctrl_br_type; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_ctrl_op1_sel; // @[mshrs.scala:128:19] wire [2:0] _rpq_io_deq_bits_uop_ctrl_op2_sel; // @[mshrs.scala:128:19] wire [2:0] _rpq_io_deq_bits_uop_ctrl_imm_sel; // @[mshrs.scala:128:19] wire [4:0] _rpq_io_deq_bits_uop_ctrl_op_fcn; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_ctrl_fcn_dw; // @[mshrs.scala:128:19] wire [2:0] _rpq_io_deq_bits_uop_ctrl_csr_cmd; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_ctrl_is_load; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_ctrl_is_sta; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_ctrl_is_std; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_iw_state; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_iw_p1_poisoned; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_iw_p2_poisoned; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_br; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_jalr; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_jal; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_sfb; // @[mshrs.scala:128:19] wire [15:0] _rpq_io_deq_bits_uop_br_mask; // @[mshrs.scala:128:19] wire [3:0] _rpq_io_deq_bits_uop_br_tag; // @[mshrs.scala:128:19] wire [4:0] _rpq_io_deq_bits_uop_ftq_idx; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_edge_inst; // @[mshrs.scala:128:19] wire [5:0] _rpq_io_deq_bits_uop_pc_lob; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_taken; // @[mshrs.scala:128:19] wire [19:0] _rpq_io_deq_bits_uop_imm_packed; // @[mshrs.scala:128:19] wire [11:0] _rpq_io_deq_bits_uop_csr_addr; // @[mshrs.scala:128:19] wire [6:0] _rpq_io_deq_bits_uop_rob_idx; // @[mshrs.scala:128:19] wire [4:0] _rpq_io_deq_bits_uop_ldq_idx; // @[mshrs.scala:128:19] wire [4:0] _rpq_io_deq_bits_uop_stq_idx; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_rxq_idx; // @[mshrs.scala:128:19] wire [6:0] _rpq_io_deq_bits_uop_pdst; // @[mshrs.scala:128:19] wire [6:0] _rpq_io_deq_bits_uop_prs1; // @[mshrs.scala:128:19] wire [6:0] _rpq_io_deq_bits_uop_prs2; // @[mshrs.scala:128:19] wire [6:0] _rpq_io_deq_bits_uop_prs3; // @[mshrs.scala:128:19] wire [4:0] _rpq_io_deq_bits_uop_ppred; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_prs1_busy; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_prs2_busy; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_prs3_busy; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_ppred_busy; // @[mshrs.scala:128:19] wire [6:0] _rpq_io_deq_bits_uop_stale_pdst; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_exception; // @[mshrs.scala:128:19] wire [63:0] _rpq_io_deq_bits_uop_exc_cause; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_bypassable; // @[mshrs.scala:128:19] wire [4:0] _rpq_io_deq_bits_uop_mem_cmd; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_mem_size; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_mem_signed; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_fence; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_fencei; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_amo; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_uses_ldq; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_uses_stq; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_sys_pc2epc; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_unique; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_flush_on_commit; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_ldst_is_rs1; // @[mshrs.scala:128:19] wire [5:0] _rpq_io_deq_bits_uop_ldst; // @[mshrs.scala:128:19] wire [5:0] _rpq_io_deq_bits_uop_lrs1; // @[mshrs.scala:128:19] wire [5:0] _rpq_io_deq_bits_uop_lrs2; // @[mshrs.scala:128:19] wire [5:0] _rpq_io_deq_bits_uop_lrs3; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_ldst_val; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_dst_rtype; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_lrs1_rtype; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_lrs2_rtype; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_frs3_en; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fp_val; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fp_single; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_xcpt_pf_if; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_xcpt_ae_if; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_xcpt_ma_if; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_bp_debug_if; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_bp_xcpt_if; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_debug_fsrc; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_debug_tsrc; // @[mshrs.scala:128:19] wire [39:0] _rpq_io_deq_bits_addr; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_is_hella; // @[mshrs.scala:128:19] wire _rpq_io_empty; // @[mshrs.scala:128:19] wire io_req_pri_val_0 = io_req_pri_val; // @[mshrs.scala:36:7] wire io_req_sec_val_0 = io_req_sec_val; // @[mshrs.scala:36:7] wire io_clear_prefetch_0 = io_clear_prefetch; // @[mshrs.scala:36:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[mshrs.scala:36:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[mshrs.scala:36:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[mshrs.scala:36:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[mshrs.scala:36:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[mshrs.scala:36:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[mshrs.scala:36:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[mshrs.scala:36:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[mshrs.scala:36:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[mshrs.scala:36:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[mshrs.scala:36:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[mshrs.scala:36:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[mshrs.scala:36:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[mshrs.scala:36:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[mshrs.scala:36:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[mshrs.scala:36:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[mshrs.scala:36:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[mshrs.scala:36:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[mshrs.scala:36:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[mshrs.scala:36:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[mshrs.scala:36:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[mshrs.scala:36:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[mshrs.scala:36:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[mshrs.scala:36:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[mshrs.scala:36:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[mshrs.scala:36:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[mshrs.scala:36:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[mshrs.scala:36:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[mshrs.scala:36:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[mshrs.scala:36:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[mshrs.scala:36:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[mshrs.scala:36:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[mshrs.scala:36:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[mshrs.scala:36:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[mshrs.scala:36:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[mshrs.scala:36:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[mshrs.scala:36:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[mshrs.scala:36:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[mshrs.scala:36:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[mshrs.scala:36:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[mshrs.scala:36:7] wire io_exception_0 = io_exception; // @[mshrs.scala:36:7] wire [6:0] io_rob_pnr_idx_0 = io_rob_pnr_idx; // @[mshrs.scala:36:7] wire [6:0] io_rob_head_idx_0 = io_rob_head_idx; // @[mshrs.scala:36:7] wire [6:0] io_req_uop_uopc_0 = io_req_uop_uopc; // @[mshrs.scala:36:7] wire [31:0] io_req_uop_inst_0 = io_req_uop_inst; // @[mshrs.scala:36:7] wire [31:0] io_req_uop_debug_inst_0 = io_req_uop_debug_inst; // @[mshrs.scala:36:7] wire io_req_uop_is_rvc_0 = io_req_uop_is_rvc; // @[mshrs.scala:36:7] wire [39:0] io_req_uop_debug_pc_0 = io_req_uop_debug_pc; // @[mshrs.scala:36:7] wire [2:0] io_req_uop_iq_type_0 = io_req_uop_iq_type; // @[mshrs.scala:36:7] wire [9:0] io_req_uop_fu_code_0 = io_req_uop_fu_code; // @[mshrs.scala:36:7] wire [3:0] io_req_uop_ctrl_br_type_0 = io_req_uop_ctrl_br_type; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_ctrl_op1_sel_0 = io_req_uop_ctrl_op1_sel; // @[mshrs.scala:36:7] wire [2:0] io_req_uop_ctrl_op2_sel_0 = io_req_uop_ctrl_op2_sel; // @[mshrs.scala:36:7] wire [2:0] io_req_uop_ctrl_imm_sel_0 = io_req_uop_ctrl_imm_sel; // @[mshrs.scala:36:7] wire [4:0] io_req_uop_ctrl_op_fcn_0 = io_req_uop_ctrl_op_fcn; // @[mshrs.scala:36:7] wire io_req_uop_ctrl_fcn_dw_0 = io_req_uop_ctrl_fcn_dw; // @[mshrs.scala:36:7] wire [2:0] io_req_uop_ctrl_csr_cmd_0 = io_req_uop_ctrl_csr_cmd; // @[mshrs.scala:36:7] wire io_req_uop_ctrl_is_load_0 = io_req_uop_ctrl_is_load; // @[mshrs.scala:36:7] wire io_req_uop_ctrl_is_sta_0 = io_req_uop_ctrl_is_sta; // @[mshrs.scala:36:7] wire io_req_uop_ctrl_is_std_0 = io_req_uop_ctrl_is_std; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_iw_state_0 = io_req_uop_iw_state; // @[mshrs.scala:36:7] wire io_req_uop_iw_p1_poisoned_0 = io_req_uop_iw_p1_poisoned; // @[mshrs.scala:36:7] wire io_req_uop_iw_p2_poisoned_0 = io_req_uop_iw_p2_poisoned; // @[mshrs.scala:36:7] wire io_req_uop_is_br_0 = io_req_uop_is_br; // @[mshrs.scala:36:7] wire io_req_uop_is_jalr_0 = io_req_uop_is_jalr; // @[mshrs.scala:36:7] wire io_req_uop_is_jal_0 = io_req_uop_is_jal; // @[mshrs.scala:36:7] wire io_req_uop_is_sfb_0 = io_req_uop_is_sfb; // @[mshrs.scala:36:7] wire [15:0] io_req_uop_br_mask_0 = io_req_uop_br_mask; // @[mshrs.scala:36:7] wire [3:0] io_req_uop_br_tag_0 = io_req_uop_br_tag; // @[mshrs.scala:36:7] wire [4:0] io_req_uop_ftq_idx_0 = io_req_uop_ftq_idx; // @[mshrs.scala:36:7] wire io_req_uop_edge_inst_0 = io_req_uop_edge_inst; // @[mshrs.scala:36:7] wire [5:0] io_req_uop_pc_lob_0 = io_req_uop_pc_lob; // @[mshrs.scala:36:7] wire io_req_uop_taken_0 = io_req_uop_taken; // @[mshrs.scala:36:7] wire [19:0] io_req_uop_imm_packed_0 = io_req_uop_imm_packed; // @[mshrs.scala:36:7] wire [11:0] io_req_uop_csr_addr_0 = io_req_uop_csr_addr; // @[mshrs.scala:36:7] wire [6:0] io_req_uop_rob_idx_0 = io_req_uop_rob_idx; // @[mshrs.scala:36:7] wire [4:0] io_req_uop_ldq_idx_0 = io_req_uop_ldq_idx; // @[mshrs.scala:36:7] wire [4:0] io_req_uop_stq_idx_0 = io_req_uop_stq_idx; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_rxq_idx_0 = io_req_uop_rxq_idx; // @[mshrs.scala:36:7] wire [6:0] io_req_uop_pdst_0 = io_req_uop_pdst; // @[mshrs.scala:36:7] wire [6:0] io_req_uop_prs1_0 = io_req_uop_prs1; // @[mshrs.scala:36:7] wire [6:0] io_req_uop_prs2_0 = io_req_uop_prs2; // @[mshrs.scala:36:7] wire [6:0] io_req_uop_prs3_0 = io_req_uop_prs3; // @[mshrs.scala:36:7] wire [4:0] io_req_uop_ppred_0 = io_req_uop_ppred; // @[mshrs.scala:36:7] wire io_req_uop_prs1_busy_0 = io_req_uop_prs1_busy; // @[mshrs.scala:36:7] wire io_req_uop_prs2_busy_0 = io_req_uop_prs2_busy; // @[mshrs.scala:36:7] wire io_req_uop_prs3_busy_0 = io_req_uop_prs3_busy; // @[mshrs.scala:36:7] wire io_req_uop_ppred_busy_0 = io_req_uop_ppred_busy; // @[mshrs.scala:36:7] wire [6:0] io_req_uop_stale_pdst_0 = io_req_uop_stale_pdst; // @[mshrs.scala:36:7] wire io_req_uop_exception_0 = io_req_uop_exception; // @[mshrs.scala:36:7] wire [63:0] io_req_uop_exc_cause_0 = io_req_uop_exc_cause; // @[mshrs.scala:36:7] wire io_req_uop_bypassable_0 = io_req_uop_bypassable; // @[mshrs.scala:36:7] wire [4:0] io_req_uop_mem_cmd_0 = io_req_uop_mem_cmd; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_mem_size_0 = io_req_uop_mem_size; // @[mshrs.scala:36:7] wire io_req_uop_mem_signed_0 = io_req_uop_mem_signed; // @[mshrs.scala:36:7] wire io_req_uop_is_fence_0 = io_req_uop_is_fence; // @[mshrs.scala:36:7] wire io_req_uop_is_fencei_0 = io_req_uop_is_fencei; // @[mshrs.scala:36:7] wire io_req_uop_is_amo_0 = io_req_uop_is_amo; // @[mshrs.scala:36:7] wire io_req_uop_uses_ldq_0 = io_req_uop_uses_ldq; // @[mshrs.scala:36:7] wire io_req_uop_uses_stq_0 = io_req_uop_uses_stq; // @[mshrs.scala:36:7] wire io_req_uop_is_sys_pc2epc_0 = io_req_uop_is_sys_pc2epc; // @[mshrs.scala:36:7] wire io_req_uop_is_unique_0 = io_req_uop_is_unique; // @[mshrs.scala:36:7] wire io_req_uop_flush_on_commit_0 = io_req_uop_flush_on_commit; // @[mshrs.scala:36:7] wire io_req_uop_ldst_is_rs1_0 = io_req_uop_ldst_is_rs1; // @[mshrs.scala:36:7] wire [5:0] io_req_uop_ldst_0 = io_req_uop_ldst; // @[mshrs.scala:36:7] wire [5:0] io_req_uop_lrs1_0 = io_req_uop_lrs1; // @[mshrs.scala:36:7] wire [5:0] io_req_uop_lrs2_0 = io_req_uop_lrs2; // @[mshrs.scala:36:7] wire [5:0] io_req_uop_lrs3_0 = io_req_uop_lrs3; // @[mshrs.scala:36:7] wire io_req_uop_ldst_val_0 = io_req_uop_ldst_val; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_dst_rtype_0 = io_req_uop_dst_rtype; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_lrs1_rtype_0 = io_req_uop_lrs1_rtype; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_lrs2_rtype_0 = io_req_uop_lrs2_rtype; // @[mshrs.scala:36:7] wire io_req_uop_frs3_en_0 = io_req_uop_frs3_en; // @[mshrs.scala:36:7] wire io_req_uop_fp_val_0 = io_req_uop_fp_val; // @[mshrs.scala:36:7] wire io_req_uop_fp_single_0 = io_req_uop_fp_single; // @[mshrs.scala:36:7] wire io_req_uop_xcpt_pf_if_0 = io_req_uop_xcpt_pf_if; // @[mshrs.scala:36:7] wire io_req_uop_xcpt_ae_if_0 = io_req_uop_xcpt_ae_if; // @[mshrs.scala:36:7] wire io_req_uop_xcpt_ma_if_0 = io_req_uop_xcpt_ma_if; // @[mshrs.scala:36:7] wire io_req_uop_bp_debug_if_0 = io_req_uop_bp_debug_if; // @[mshrs.scala:36:7] wire io_req_uop_bp_xcpt_if_0 = io_req_uop_bp_xcpt_if; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_debug_fsrc_0 = io_req_uop_debug_fsrc; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_debug_tsrc_0 = io_req_uop_debug_tsrc; // @[mshrs.scala:36:7] wire [39:0] io_req_addr_0 = io_req_addr; // @[mshrs.scala:36:7] wire [63:0] io_req_data_0 = io_req_data; // @[mshrs.scala:36:7] wire io_req_is_hella_0 = io_req_is_hella; // @[mshrs.scala:36:7] wire io_req_tag_match_0 = io_req_tag_match; // @[mshrs.scala:36:7] wire [1:0] io_req_old_meta_coh_state_0 = io_req_old_meta_coh_state; // @[mshrs.scala:36:7] wire [19:0] io_req_old_meta_tag_0 = io_req_old_meta_tag; // @[mshrs.scala:36:7] wire [7:0] io_req_way_en_0 = io_req_way_en; // @[mshrs.scala:36:7] wire [4:0] io_req_sdq_id_0 = io_req_sdq_id; // @[mshrs.scala:36:7] wire io_req_is_probe_0 = io_req_is_probe; // @[mshrs.scala:36:7] wire io_mem_acquire_ready_0 = io_mem_acquire_ready; // @[mshrs.scala:36:7] wire io_mem_grant_valid_0 = io_mem_grant_valid; // @[mshrs.scala:36:7] wire [2:0] io_mem_grant_bits_opcode_0 = io_mem_grant_bits_opcode; // @[mshrs.scala:36:7] wire [1:0] io_mem_grant_bits_param_0 = io_mem_grant_bits_param; // @[mshrs.scala:36:7] wire [3:0] io_mem_grant_bits_size_0 = io_mem_grant_bits_size; // @[mshrs.scala:36:7] wire [2:0] io_mem_grant_bits_source_0 = io_mem_grant_bits_source; // @[mshrs.scala:36:7] wire [3:0] io_mem_grant_bits_sink_0 = io_mem_grant_bits_sink; // @[mshrs.scala:36:7] wire io_mem_grant_bits_denied_0 = io_mem_grant_bits_denied; // @[mshrs.scala:36:7] wire [127:0] io_mem_grant_bits_data_0 = io_mem_grant_bits_data; // @[mshrs.scala:36:7] wire io_mem_grant_bits_corrupt_0 = io_mem_grant_bits_corrupt; // @[mshrs.scala:36:7] wire io_mem_finish_ready_0 = io_mem_finish_ready; // @[mshrs.scala:36:7] wire io_prober_state_valid_0 = io_prober_state_valid; // @[mshrs.scala:36:7] wire [39:0] io_prober_state_bits_0 = io_prober_state_bits; // @[mshrs.scala:36:7] wire io_refill_ready_0 = io_refill_ready; // @[mshrs.scala:36:7] wire io_meta_write_ready_0 = io_meta_write_ready; // @[mshrs.scala:36:7] wire io_meta_read_ready_0 = io_meta_read_ready; // @[mshrs.scala:36:7] wire io_meta_resp_valid_0 = io_meta_resp_valid; // @[mshrs.scala:36:7] wire [1:0] io_meta_resp_bits_coh_state_0 = io_meta_resp_bits_coh_state; // @[mshrs.scala:36:7] wire [19:0] io_meta_resp_bits_tag_0 = io_meta_resp_bits_tag; // @[mshrs.scala:36:7] wire io_wb_req_ready_0 = io_wb_req_ready; // @[mshrs.scala:36:7] wire io_lb_read_ready_0 = io_lb_read_ready; // @[mshrs.scala:36:7] wire [127:0] io_lb_resp_0 = io_lb_resp; // @[mshrs.scala:36:7] wire io_lb_write_ready_0 = io_lb_write_ready; // @[mshrs.scala:36:7] wire io_replay_ready_0 = io_replay_ready; // @[mshrs.scala:36:7] wire io_resp_ready_0 = io_resp_ready; // @[mshrs.scala:36:7] wire io_wb_resp_0 = io_wb_resp; // @[mshrs.scala:36:7] wire _state_T = reset; // @[mshrs.scala:194:11] wire _state_T_26 = reset; // @[mshrs.scala:201:15] wire _state_T_34 = reset; // @[mshrs.scala:194:11] wire _state_T_60 = reset; // @[mshrs.scala:201:15] wire [1:0] io_id = 2'h1; // @[mshrs.scala:36:7] wire [1:0] io_lb_read_bits_id = 2'h1; // @[mshrs.scala:36:7] wire [1:0] io_lb_write_bits_id = 2'h1; // @[mshrs.scala:36:7] wire [1:0] _grow_param_r_T_7 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _grow_param_r_T_9 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _grow_param_r_T_17 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _grow_param_r_T_19 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _coh_on_grant_T_5 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r1_T_7 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r1_T_9 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r1_T_17 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r1_T_19 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r2_T_7 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r2_T_9 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r2_T_17 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r2_T_19 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_7 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_9 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_17 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_19 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_71 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_73 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_81 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_83 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_130 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_132 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_140 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_142 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_66 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_68 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_76 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_78 = 2'h1; // @[Metadata.scala:25:15] wire [2:0] io_mem_acquire_bits_opcode = 3'h6; // @[mshrs.scala:36:7] wire [2:0] io_mem_acquire_bits_a_opcode = 3'h6; // @[Edges.scala:346:17] wire [3:0] io_mem_acquire_bits_size = 4'h6; // @[mshrs.scala:36:7] wire [3:0] _r_T_12 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] _grow_param_r_T_10 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _r1_T_10 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _r2_T_10 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _state_req_needs_wb_r_T_12 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] _state_r_T_10 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] io_mem_acquire_bits_a_size = 4'h6; // @[Edges.scala:346:17] wire [3:0] _io_mem_acquire_bits_a_mask_sizeOH_T = 4'h6; // @[Misc.scala:202:34] wire [3:0] _needs_wb_r_T_12 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] _r_T_74 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _r_T_133 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _state_req_needs_wb_r_T_76 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] _state_r_T_69 = 4'h6; // @[Metadata.scala:64:10] wire [2:0] io_mem_acquire_bits_source = 3'h1; // @[mshrs.scala:36:7] wire [2:0] io_wb_req_bits_source = 3'h1; // @[mshrs.scala:36:7] wire [2:0] io_mem_acquire_bits_a_source = 3'h1; // @[Edges.scala:346:17] wire [15:0] io_mem_acquire_bits_mask = 16'hFFFF; // @[mshrs.scala:36:7] wire [15:0] io_mem_acquire_bits_a_mask = 16'hFFFF; // @[Edges.scala:346:17] wire [15:0] _io_mem_acquire_bits_a_mask_T = 16'hFFFF; // @[Misc.scala:222:10] wire [127:0] io_mem_acquire_bits_data = 128'h0; // @[mshrs.scala:36:7] wire [127:0] io_mem_acquire_bits_a_data = 128'h0; // @[Edges.scala:346:17] wire io_mem_acquire_bits_corrupt = 1'h0; // @[mshrs.scala:36:7] wire _r_T_2 = 1'h0; // @[Metadata.scala:140:24] wire _r_T_4 = 1'h0; // @[Metadata.scala:140:24] wire _r_T_20 = 1'h0; // @[Misc.scala:38:9] wire _r_T_24 = 1'h0; // @[Misc.scala:38:9] wire _r_T_28 = 1'h0; // @[Misc.scala:38:9] wire _grow_param_r_T_26 = 1'h0; // @[Misc.scala:35:9] wire _grow_param_r_T_29 = 1'h0; // @[Misc.scala:35:9] wire _grow_param_r_T_32 = 1'h0; // @[Misc.scala:35:9] wire _grow_param_r_T_35 = 1'h0; // @[Misc.scala:35:9] wire _grow_param_r_T_38 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_26 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_29 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_32 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_35 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_38 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_26 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_29 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_32 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_35 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_38 = 1'h0; // @[Misc.scala:35:9] wire _state_req_needs_wb_r_T_2 = 1'h0; // @[Metadata.scala:140:24] wire _state_req_needs_wb_r_T_4 = 1'h0; // @[Metadata.scala:140:24] wire _state_req_needs_wb_r_T_20 = 1'h0; // @[Misc.scala:38:9] wire _state_req_needs_wb_r_T_24 = 1'h0; // @[Misc.scala:38:9] wire _state_req_needs_wb_r_T_28 = 1'h0; // @[Misc.scala:38:9] wire _state_r_T_26 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_29 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_32 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_35 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_38 = 1'h0; // @[Misc.scala:35:9] wire _io_mem_acquire_bits_legal_T = 1'h0; // @[Parameters.scala:684:29] wire _io_mem_acquire_bits_legal_T_18 = 1'h0; // @[Parameters.scala:684:54] wire _io_mem_acquire_bits_legal_T_33 = 1'h0; // @[Parameters.scala:686:26] wire io_mem_acquire_bits_a_corrupt = 1'h0; // @[Edges.scala:346:17] wire io_mem_acquire_bits_a_mask_sub_sub_sub_size = 1'h0; // @[Misc.scala:209:26] wire _io_mem_acquire_bits_a_mask_sub_sub_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_sub_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire io_mem_acquire_bits_a_mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _io_mem_acquire_bits_a_mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38] wire io_resp_bits_data_doZero = 1'h0; // @[AMOALU.scala:43:31] wire io_resp_bits_data_doZero_1 = 1'h0; // @[AMOALU.scala:43:31] wire io_resp_bits_data_doZero_2 = 1'h0; // @[AMOALU.scala:43:31] wire _needs_wb_r_T_2 = 1'h0; // @[Metadata.scala:140:24] wire _needs_wb_r_T_4 = 1'h0; // @[Metadata.scala:140:24] wire _needs_wb_r_T_20 = 1'h0; // @[Misc.scala:38:9] wire _needs_wb_r_T_24 = 1'h0; // @[Misc.scala:38:9] wire _needs_wb_r_T_28 = 1'h0; // @[Misc.scala:38:9] wire _r_T_90 = 1'h0; // @[Misc.scala:35:9] wire _r_T_93 = 1'h0; // @[Misc.scala:35:9] wire _r_T_96 = 1'h0; // @[Misc.scala:35:9] wire _r_T_99 = 1'h0; // @[Misc.scala:35:9] wire _r_T_102 = 1'h0; // @[Misc.scala:35:9] wire _r_T_149 = 1'h0; // @[Misc.scala:35:9] wire _r_T_152 = 1'h0; // @[Misc.scala:35:9] wire _r_T_155 = 1'h0; // @[Misc.scala:35:9] wire _r_T_158 = 1'h0; // @[Misc.scala:35:9] wire _r_T_161 = 1'h0; // @[Misc.scala:35:9] wire _state_req_needs_wb_r_T_66 = 1'h0; // @[Metadata.scala:140:24] wire _state_req_needs_wb_r_T_68 = 1'h0; // @[Metadata.scala:140:24] wire _state_req_needs_wb_r_T_84 = 1'h0; // @[Misc.scala:38:9] wire _state_req_needs_wb_r_T_88 = 1'h0; // @[Misc.scala:38:9] wire _state_req_needs_wb_r_T_92 = 1'h0; // @[Misc.scala:38:9] wire _state_r_T_85 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_88 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_91 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_94 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_97 = 1'h0; // @[Misc.scala:35:9] wire [1:0] io_refill_bits_wmask = 2'h3; // @[mshrs.scala:36:7] wire [1:0] _grow_param_r_T_11 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _grow_param_r_T_13 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _grow_param_r_T_21 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _grow_param_r_T_23 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _coh_on_grant_T_7 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r1_T_11 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r1_T_13 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r1_T_21 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r1_T_23 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r2_T_11 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r2_T_13 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r2_T_21 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r2_T_23 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _dirties_T = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_11 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_13 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_21 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_23 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] io_mem_acquire_bits_a_mask_lo_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_lo_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_lo_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_lo_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_hi_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_hi_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_hi_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_hi_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] _io_refill_bits_wmask_T = 2'h3; // @[mshrs.scala:342:30] wire [1:0] _r_T_75 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_77 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_85 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_87 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_134 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_136 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_144 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_146 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_70 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_72 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_80 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_82 = 2'h3; // @[Metadata.scala:24:15] wire [19:0] io_meta_write_bits_tag = 20'h0; // @[mshrs.scala:36:7] wire io_wb_req_bits_voluntary = 1'h1; // @[mshrs.scala:36:7] wire _r_T = 1'h1; // @[Metadata.scala:140:24] wire _state_req_needs_wb_r_T = 1'h1; // @[Metadata.scala:140:24] wire _io_mem_acquire_bits_legal_T_19 = 1'h1; // @[Parameters.scala:91:44] wire _io_mem_acquire_bits_legal_T_20 = 1'h1; // @[Parameters.scala:684:29] wire io_mem_acquire_bits_a_mask_sub_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire io_mem_acquire_bits_a_mask_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_sub_size = 1'h1; // @[Misc.scala:209:26] wire io_mem_acquire_bits_a_mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_sub_2_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_sub_3_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_2_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_3_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_4_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_5_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_6_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_7_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_size = 1'h1; // @[Misc.scala:209:26] wire io_mem_acquire_bits_a_mask_acc = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_4 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_5 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_6 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_7 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_8 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_9 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_10 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_11 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_12 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_13 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_14 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_15 = 1'h1; // @[Misc.scala:215:29] wire _needs_wb_r_T = 1'h1; // @[Metadata.scala:140:24] wire _state_req_needs_wb_r_T_64 = 1'h1; // @[Metadata.scala:140:24] wire [1:0] new_coh_meta_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] _r_T_22 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_26 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_30 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_34 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_38 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _grow_param_r_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _grow_param_r_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _grow_param_r_T_5 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _grow_param_r_T_15 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _coh_on_grant_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _coh_on_grant_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r1_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r1_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r1_T_5 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r1_T_15 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r2_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r2_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r2_T_5 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r2_T_15 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_req_needs_wb_r_T_22 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_26 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_30 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_34 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_38 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_r_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_r_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_r_T_5 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_r_T_15 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] state_new_coh_meta_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] _needs_wb_r_T_22 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _needs_wb_r_T_26 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _needs_wb_r_T_30 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _needs_wb_r_T_34 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _needs_wb_r_T_38 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_65 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_67 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_69 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_79 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_124 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_126 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_128 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_138 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] new_coh_meta_1_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] _state_req_needs_wb_r_T_86 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_90 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_94 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_98 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_102 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_r_T_60 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_r_T_62 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_r_T_64 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_r_T_74 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] state_new_coh_meta_1_state = 2'h0; // @[Metadata.scala:160:20] wire [3:0] _grow_param_r_T_24 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _coh_on_grant_T_8 = 4'hC; // @[Metadata.scala:89:10] wire [3:0] _r1_T_24 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _r2_T_24 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _state_r_T_24 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _r_T_88 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _r_T_147 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _state_r_T_83 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _grow_param_r_T_22 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r1_T_22 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r2_T_22 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _state_r_T_22 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r_T_86 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r_T_145 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _state_r_T_81 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r_T_14 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _grow_param_r_T_20 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _coh_on_grant_T_6 = 4'h4; // @[Metadata.scala:88:10] wire [3:0] _r1_T_20 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _r2_T_20 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _state_req_needs_wb_r_T_14 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _state_r_T_20 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _io_mem_acquire_bits_a_mask_sizeOH_T_1 = 4'h4; // @[OneHot.scala:65:12] wire [3:0] _io_mem_acquire_bits_a_mask_sizeOH_T_2 = 4'h4; // @[OneHot.scala:65:27] wire [3:0] _needs_wb_r_T_14 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _r_T_84 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _r_T_143 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _state_req_needs_wb_r_T_78 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _state_r_T_79 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _r_T_13 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] _grow_param_r_T_18 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _r1_T_18 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _r2_T_18 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _state_req_needs_wb_r_T_13 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] _state_r_T_18 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] io_mem_acquire_bits_a_mask_sizeOH = 4'h5; // @[Misc.scala:202:81] wire [3:0] _needs_wb_r_T_13 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] _r_T_82 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _r_T_141 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _state_req_needs_wb_r_T_77 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] _state_r_T_77 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _r_T_10 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _grow_param_r_T_16 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _coh_on_grant_T_4 = 4'h0; // @[Metadata.scala:87:10] wire [3:0] _r1_T_16 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _r2_T_16 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _state_req_needs_wb_r_T_10 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _state_r_T_16 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _needs_wb_r_T_10 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _r_T_80 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _r_T_139 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _state_req_needs_wb_r_T_74 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _state_r_T_75 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _grow_param_r_T_14 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _r1_T_14 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _r2_T_14 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _state_r_T_14 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _r_T_78 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _r_T_137 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _state_r_T_73 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _grow_param_r_T_12 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _r1_T_12 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _r2_T_12 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _state_r_T_12 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] io_mem_acquire_bits_a_mask_lo_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] io_mem_acquire_bits_a_mask_lo_hi = 4'hF; // @[Misc.scala:222:10] wire [3:0] io_mem_acquire_bits_a_mask_hi_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] io_mem_acquire_bits_a_mask_hi_hi = 4'hF; // @[Misc.scala:222:10] wire [3:0] _r_T_76 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _r_T_135 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _state_r_T_71 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _r_T_11 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _grow_param_r_T_8 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _r1_T_8 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _r2_T_8 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _state_req_needs_wb_r_T_11 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _state_r_T_8 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _needs_wb_r_T_11 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _r_T_72 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _r_T_131 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _state_req_needs_wb_r_T_75 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _state_r_T_67 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _r_T_9 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _grow_param_r_T_6 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _coh_on_grant_T_2 = 4'h1; // @[Metadata.scala:86:10] wire [3:0] _r1_T_6 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _r2_T_6 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _state_req_needs_wb_r_T_9 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _state_r_T_6 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _needs_wb_r_T_9 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _r_T_70 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _r_T_129 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _state_req_needs_wb_r_T_73 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _state_r_T_65 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _r_T_8 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _grow_param_r_T_4 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _r1_T_4 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _r2_T_4 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _state_req_needs_wb_r_T_8 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _state_r_T_4 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _needs_wb_r_T_8 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _r_T_68 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _r_T_127 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _state_req_needs_wb_r_T_72 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _state_r_T_63 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _r_T_7 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _grow_param_r_T_2 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _r1_T_2 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _r2_T_2 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _state_req_needs_wb_r_T_7 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _state_r_T_2 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _needs_wb_r_T_7 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _r_T_66 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _r_T_125 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _state_req_needs_wb_r_T_71 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _state_r_T_61 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _r_T_18 = 4'h8; // @[Metadata.scala:133:10] wire [3:0] _state_req_needs_wb_r_T_18 = 4'h8; // @[Metadata.scala:133:10] wire [3:0] _needs_wb_r_T_18 = 4'h8; // @[Metadata.scala:133:10] wire [3:0] _state_req_needs_wb_r_T_82 = 4'h8; // @[Metadata.scala:133:10] wire [3:0] _r_T_17 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _state_req_needs_wb_r_T_17 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _needs_wb_r_T_17 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _state_req_needs_wb_r_T_81 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _r_T_16 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _state_req_needs_wb_r_T_16 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _needs_wb_r_T_16 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _state_req_needs_wb_r_T_80 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _r_T_15 = 4'hB; // @[Metadata.scala:130:10] wire [3:0] _state_req_needs_wb_r_T_15 = 4'hB; // @[Metadata.scala:130:10] wire [3:0] _needs_wb_r_T_15 = 4'hB; // @[Metadata.scala:130:10] wire [3:0] _state_req_needs_wb_r_T_79 = 4'hB; // @[Metadata.scala:130:10] wire [1:0] _r_T_1 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _r_T_3 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _r_T_5 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _state_req_needs_wb_r_T_1 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _state_req_needs_wb_r_T_3 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _state_req_needs_wb_r_T_5 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] io_mem_acquire_bits_a_mask_sizeOH_shiftAmount = 2'h2; // @[OneHot.scala:64:49] wire [1:0] _needs_wb_r_T_1 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _needs_wb_r_T_3 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _needs_wb_r_T_5 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _state_req_needs_wb_r_T_65 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _state_req_needs_wb_r_T_67 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _state_req_needs_wb_r_T_69 = 2'h2; // @[Metadata.scala:140:24] wire [7:0] io_mem_acquire_bits_a_mask_lo = 8'hFF; // @[Misc.scala:222:10] wire [7:0] io_mem_acquire_bits_a_mask_hi = 8'hFF; // @[Misc.scala:222:10] wire _io_req_sec_rdy_T; // @[mshrs.scala:159:37] wire _io_idx_valid_T; // @[mshrs.scala:149:25] wire [5:0] req_idx; // @[mshrs.scala:110:25] wire _io_way_valid_T_3; // @[mshrs.scala:151:19] wire _io_tag_valid_T; // @[mshrs.scala:150:25] wire [27:0] req_tag; // @[mshrs.scala:111:26] wire [2:0] io_mem_acquire_bits_a_param; // @[Edges.scala:346:17] wire [31:0] io_mem_acquire_bits_a_address; // @[Edges.scala:346:17] wire [3:0] grantack_bits_e_sink = io_mem_grant_bits_sink_0; // @[Edges.scala:451:17] wire [127:0] io_lb_write_bits_data_0 = io_mem_grant_bits_data_0; // @[mshrs.scala:36:7] wire [2:0] shrink_param; // @[Misc.scala:38:36] wire [1:0] coh_on_grant_state; // @[Metadata.scala:160:20] wire [127:0] io_refill_bits_data_0 = io_lb_resp_0; // @[mshrs.scala:36:7] wire [39:0] _io_replay_bits_addr_T_1; // @[mshrs.scala:353:31] wire [63:0] _io_resp_bits_data_T_23; // @[AMOALU.scala:45:16] wire _io_probe_rdy_T_11; // @[mshrs.scala:148:42] wire io_idx_valid_0; // @[mshrs.scala:36:7] wire [5:0] io_idx_bits_0; // @[mshrs.scala:36:7] wire io_way_valid_0; // @[mshrs.scala:36:7] wire [7:0] io_way_bits_0; // @[mshrs.scala:36:7] wire io_tag_valid_0; // @[mshrs.scala:36:7] wire [27:0] io_tag_bits_0; // @[mshrs.scala:36:7] wire [2:0] io_mem_acquire_bits_param_0; // @[mshrs.scala:36:7] wire [31:0] io_mem_acquire_bits_address_0; // @[mshrs.scala:36:7] wire io_mem_acquire_valid_0; // @[mshrs.scala:36:7] wire io_mem_grant_ready_0; // @[mshrs.scala:36:7] wire [3:0] io_mem_finish_bits_sink_0; // @[mshrs.scala:36:7] wire io_mem_finish_valid_0; // @[mshrs.scala:36:7] wire [7:0] io_refill_bits_way_en_0; // @[mshrs.scala:36:7] wire [11:0] io_refill_bits_addr_0; // @[mshrs.scala:36:7] wire io_refill_valid_0; // @[mshrs.scala:36:7] wire [1:0] io_meta_write_bits_data_coh_state_0; // @[mshrs.scala:36:7] wire [19:0] io_meta_write_bits_data_tag_0; // @[mshrs.scala:36:7] wire [5:0] io_meta_write_bits_idx_0; // @[mshrs.scala:36:7] wire [7:0] io_meta_write_bits_way_en_0; // @[mshrs.scala:36:7] wire io_meta_write_valid_0; // @[mshrs.scala:36:7] wire [5:0] io_meta_read_bits_idx_0; // @[mshrs.scala:36:7] wire [7:0] io_meta_read_bits_way_en_0; // @[mshrs.scala:36:7] wire [19:0] io_meta_read_bits_tag_0; // @[mshrs.scala:36:7] wire io_meta_read_valid_0; // @[mshrs.scala:36:7] wire [19:0] io_wb_req_bits_tag_0; // @[mshrs.scala:36:7] wire [5:0] io_wb_req_bits_idx_0; // @[mshrs.scala:36:7] wire [2:0] io_wb_req_bits_param_0; // @[mshrs.scala:36:7] wire [7:0] io_wb_req_bits_way_en_0; // @[mshrs.scala:36:7] wire io_wb_req_valid_0; // @[mshrs.scala:36:7] wire [1:0] io_commit_coh_state_0; // @[mshrs.scala:36:7] wire [1:0] io_lb_read_bits_offset_0; // @[mshrs.scala:36:7] wire io_lb_read_valid_0; // @[mshrs.scala:36:7] wire [1:0] io_lb_write_bits_offset_0; // @[mshrs.scala:36:7] wire io_lb_write_valid_0; // @[mshrs.scala:36:7] wire [3:0] io_replay_bits_uop_ctrl_br_type_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_ctrl_op1_sel_0; // @[mshrs.scala:36:7] wire [2:0] io_replay_bits_uop_ctrl_op2_sel_0; // @[mshrs.scala:36:7] wire [2:0] io_replay_bits_uop_ctrl_imm_sel_0; // @[mshrs.scala:36:7] wire [4:0] io_replay_bits_uop_ctrl_op_fcn_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_ctrl_fcn_dw_0; // @[mshrs.scala:36:7] wire [2:0] io_replay_bits_uop_ctrl_csr_cmd_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_ctrl_is_load_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_ctrl_is_sta_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_ctrl_is_std_0; // @[mshrs.scala:36:7] wire [6:0] io_replay_bits_uop_uopc_0; // @[mshrs.scala:36:7] wire [31:0] io_replay_bits_uop_inst_0; // @[mshrs.scala:36:7] wire [31:0] io_replay_bits_uop_debug_inst_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_rvc_0; // @[mshrs.scala:36:7] wire [39:0] io_replay_bits_uop_debug_pc_0; // @[mshrs.scala:36:7] wire [2:0] io_replay_bits_uop_iq_type_0; // @[mshrs.scala:36:7] wire [9:0] io_replay_bits_uop_fu_code_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_iw_state_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_iw_p1_poisoned_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_iw_p2_poisoned_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_br_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_jalr_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_jal_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_sfb_0; // @[mshrs.scala:36:7] wire [15:0] io_replay_bits_uop_br_mask_0; // @[mshrs.scala:36:7] wire [3:0] io_replay_bits_uop_br_tag_0; // @[mshrs.scala:36:7] wire [4:0] io_replay_bits_uop_ftq_idx_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_edge_inst_0; // @[mshrs.scala:36:7] wire [5:0] io_replay_bits_uop_pc_lob_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_taken_0; // @[mshrs.scala:36:7] wire [19:0] io_replay_bits_uop_imm_packed_0; // @[mshrs.scala:36:7] wire [11:0] io_replay_bits_uop_csr_addr_0; // @[mshrs.scala:36:7] wire [6:0] io_replay_bits_uop_rob_idx_0; // @[mshrs.scala:36:7] wire [4:0] io_replay_bits_uop_ldq_idx_0; // @[mshrs.scala:36:7] wire [4:0] io_replay_bits_uop_stq_idx_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_rxq_idx_0; // @[mshrs.scala:36:7] wire [6:0] io_replay_bits_uop_pdst_0; // @[mshrs.scala:36:7] wire [6:0] io_replay_bits_uop_prs1_0; // @[mshrs.scala:36:7] wire [6:0] io_replay_bits_uop_prs2_0; // @[mshrs.scala:36:7] wire [6:0] io_replay_bits_uop_prs3_0; // @[mshrs.scala:36:7] wire [4:0] io_replay_bits_uop_ppred_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_prs1_busy_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_prs2_busy_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_prs3_busy_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_ppred_busy_0; // @[mshrs.scala:36:7] wire [6:0] io_replay_bits_uop_stale_pdst_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_exception_0; // @[mshrs.scala:36:7] wire [63:0] io_replay_bits_uop_exc_cause_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_bypassable_0; // @[mshrs.scala:36:7] wire [4:0] io_replay_bits_uop_mem_cmd_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_mem_size_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_mem_signed_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_fence_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_fencei_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_amo_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_uses_ldq_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_uses_stq_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_sys_pc2epc_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_unique_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_flush_on_commit_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_ldst_is_rs1_0; // @[mshrs.scala:36:7] wire [5:0] io_replay_bits_uop_ldst_0; // @[mshrs.scala:36:7] wire [5:0] io_replay_bits_uop_lrs1_0; // @[mshrs.scala:36:7] wire [5:0] io_replay_bits_uop_lrs2_0; // @[mshrs.scala:36:7] wire [5:0] io_replay_bits_uop_lrs3_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_ldst_val_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_dst_rtype_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_lrs1_rtype_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_lrs2_rtype_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_frs3_en_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fp_val_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fp_single_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_xcpt_pf_if_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_xcpt_ae_if_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_xcpt_ma_if_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_bp_debug_if_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_bp_xcpt_if_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_debug_fsrc_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_debug_tsrc_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_old_meta_coh_state_0; // @[mshrs.scala:36:7] wire [19:0] io_replay_bits_old_meta_tag_0; // @[mshrs.scala:36:7] wire [39:0] io_replay_bits_addr_0; // @[mshrs.scala:36:7] wire [63:0] io_replay_bits_data_0; // @[mshrs.scala:36:7] wire io_replay_bits_is_hella_0; // @[mshrs.scala:36:7] wire io_replay_bits_tag_match_0; // @[mshrs.scala:36:7] wire [7:0] io_replay_bits_way_en_0; // @[mshrs.scala:36:7] wire [4:0] io_replay_bits_sdq_id_0; // @[mshrs.scala:36:7] wire io_replay_valid_0; // @[mshrs.scala:36:7] wire [3:0] io_resp_bits_uop_ctrl_br_type_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_ctrl_op1_sel_0; // @[mshrs.scala:36:7] wire [2:0] io_resp_bits_uop_ctrl_op2_sel_0; // @[mshrs.scala:36:7] wire [2:0] io_resp_bits_uop_ctrl_imm_sel_0; // @[mshrs.scala:36:7] wire [4:0] io_resp_bits_uop_ctrl_op_fcn_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_ctrl_fcn_dw_0; // @[mshrs.scala:36:7] wire [2:0] io_resp_bits_uop_ctrl_csr_cmd_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_ctrl_is_load_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_ctrl_is_sta_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_ctrl_is_std_0; // @[mshrs.scala:36:7] wire [6:0] io_resp_bits_uop_uopc_0; // @[mshrs.scala:36:7] wire [31:0] io_resp_bits_uop_inst_0; // @[mshrs.scala:36:7] wire [31:0] io_resp_bits_uop_debug_inst_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_rvc_0; // @[mshrs.scala:36:7] wire [39:0] io_resp_bits_uop_debug_pc_0; // @[mshrs.scala:36:7] wire [2:0] io_resp_bits_uop_iq_type_0; // @[mshrs.scala:36:7] wire [9:0] io_resp_bits_uop_fu_code_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_iw_state_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_iw_p1_poisoned_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_iw_p2_poisoned_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_br_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_jalr_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_jal_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_sfb_0; // @[mshrs.scala:36:7] wire [15:0] io_resp_bits_uop_br_mask_0; // @[mshrs.scala:36:7] wire [3:0] io_resp_bits_uop_br_tag_0; // @[mshrs.scala:36:7] wire [4:0] io_resp_bits_uop_ftq_idx_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_edge_inst_0; // @[mshrs.scala:36:7] wire [5:0] io_resp_bits_uop_pc_lob_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_taken_0; // @[mshrs.scala:36:7] wire [19:0] io_resp_bits_uop_imm_packed_0; // @[mshrs.scala:36:7] wire [11:0] io_resp_bits_uop_csr_addr_0; // @[mshrs.scala:36:7] wire [6:0] io_resp_bits_uop_rob_idx_0; // @[mshrs.scala:36:7] wire [4:0] io_resp_bits_uop_ldq_idx_0; // @[mshrs.scala:36:7] wire [4:0] io_resp_bits_uop_stq_idx_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_rxq_idx_0; // @[mshrs.scala:36:7] wire [6:0] io_resp_bits_uop_pdst_0; // @[mshrs.scala:36:7] wire [6:0] io_resp_bits_uop_prs1_0; // @[mshrs.scala:36:7] wire [6:0] io_resp_bits_uop_prs2_0; // @[mshrs.scala:36:7] wire [6:0] io_resp_bits_uop_prs3_0; // @[mshrs.scala:36:7] wire [4:0] io_resp_bits_uop_ppred_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_prs1_busy_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_prs2_busy_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_prs3_busy_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_ppred_busy_0; // @[mshrs.scala:36:7] wire [6:0] io_resp_bits_uop_stale_pdst_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_exception_0; // @[mshrs.scala:36:7] wire [63:0] io_resp_bits_uop_exc_cause_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_bypassable_0; // @[mshrs.scala:36:7] wire [4:0] io_resp_bits_uop_mem_cmd_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_mem_size_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_mem_signed_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_fence_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_fencei_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_amo_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_uses_ldq_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_uses_stq_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_sys_pc2epc_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_unique_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_flush_on_commit_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_ldst_is_rs1_0; // @[mshrs.scala:36:7] wire [5:0] io_resp_bits_uop_ldst_0; // @[mshrs.scala:36:7] wire [5:0] io_resp_bits_uop_lrs1_0; // @[mshrs.scala:36:7] wire [5:0] io_resp_bits_uop_lrs2_0; // @[mshrs.scala:36:7] wire [5:0] io_resp_bits_uop_lrs3_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_ldst_val_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_dst_rtype_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_lrs1_rtype_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_lrs2_rtype_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_frs3_en_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fp_val_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fp_single_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_xcpt_pf_if_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_xcpt_ae_if_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_xcpt_ma_if_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_bp_debug_if_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_bp_xcpt_if_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_debug_fsrc_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_debug_tsrc_0; // @[mshrs.scala:36:7] wire [63:0] io_resp_bits_data_0; // @[mshrs.scala:36:7] wire io_resp_bits_is_hella_0; // @[mshrs.scala:36:7] wire io_resp_valid_0; // @[mshrs.scala:36:7] wire io_req_pri_rdy_0; // @[mshrs.scala:36:7] wire io_req_sec_rdy_0; // @[mshrs.scala:36:7] wire io_commit_val_0; // @[mshrs.scala:36:7] wire [39:0] io_commit_addr_0; // @[mshrs.scala:36:7] wire io_probe_rdy_0; // @[mshrs.scala:36:7] reg [4:0] state; // @[mshrs.scala:107:22] reg [6:0] req_uop_uopc; // @[mshrs.scala:109:20] reg [31:0] req_uop_inst; // @[mshrs.scala:109:20] reg [31:0] req_uop_debug_inst; // @[mshrs.scala:109:20] reg req_uop_is_rvc; // @[mshrs.scala:109:20] reg [39:0] req_uop_debug_pc; // @[mshrs.scala:109:20] reg [2:0] req_uop_iq_type; // @[mshrs.scala:109:20] reg [9:0] req_uop_fu_code; // @[mshrs.scala:109:20] reg [3:0] req_uop_ctrl_br_type; // @[mshrs.scala:109:20] reg [1:0] req_uop_ctrl_op1_sel; // @[mshrs.scala:109:20] reg [2:0] req_uop_ctrl_op2_sel; // @[mshrs.scala:109:20] reg [2:0] req_uop_ctrl_imm_sel; // @[mshrs.scala:109:20] reg [4:0] req_uop_ctrl_op_fcn; // @[mshrs.scala:109:20] reg req_uop_ctrl_fcn_dw; // @[mshrs.scala:109:20] reg [2:0] req_uop_ctrl_csr_cmd; // @[mshrs.scala:109:20] reg req_uop_ctrl_is_load; // @[mshrs.scala:109:20] reg req_uop_ctrl_is_sta; // @[mshrs.scala:109:20] reg req_uop_ctrl_is_std; // @[mshrs.scala:109:20] reg [1:0] req_uop_iw_state; // @[mshrs.scala:109:20] reg req_uop_iw_p1_poisoned; // @[mshrs.scala:109:20] reg req_uop_iw_p2_poisoned; // @[mshrs.scala:109:20] reg req_uop_is_br; // @[mshrs.scala:109:20] reg req_uop_is_jalr; // @[mshrs.scala:109:20] reg req_uop_is_jal; // @[mshrs.scala:109:20] reg req_uop_is_sfb; // @[mshrs.scala:109:20] reg [15:0] req_uop_br_mask; // @[mshrs.scala:109:20] reg [3:0] req_uop_br_tag; // @[mshrs.scala:109:20] reg [4:0] req_uop_ftq_idx; // @[mshrs.scala:109:20] reg req_uop_edge_inst; // @[mshrs.scala:109:20] reg [5:0] req_uop_pc_lob; // @[mshrs.scala:109:20] reg req_uop_taken; // @[mshrs.scala:109:20] reg [19:0] req_uop_imm_packed; // @[mshrs.scala:109:20] reg [11:0] req_uop_csr_addr; // @[mshrs.scala:109:20] reg [6:0] req_uop_rob_idx; // @[mshrs.scala:109:20] reg [4:0] req_uop_ldq_idx; // @[mshrs.scala:109:20] reg [4:0] req_uop_stq_idx; // @[mshrs.scala:109:20] reg [1:0] req_uop_rxq_idx; // @[mshrs.scala:109:20] reg [6:0] req_uop_pdst; // @[mshrs.scala:109:20] reg [6:0] req_uop_prs1; // @[mshrs.scala:109:20] reg [6:0] req_uop_prs2; // @[mshrs.scala:109:20] reg [6:0] req_uop_prs3; // @[mshrs.scala:109:20] reg [4:0] req_uop_ppred; // @[mshrs.scala:109:20] reg req_uop_prs1_busy; // @[mshrs.scala:109:20] reg req_uop_prs2_busy; // @[mshrs.scala:109:20] reg req_uop_prs3_busy; // @[mshrs.scala:109:20] reg req_uop_ppred_busy; // @[mshrs.scala:109:20] reg [6:0] req_uop_stale_pdst; // @[mshrs.scala:109:20] reg req_uop_exception; // @[mshrs.scala:109:20] reg [63:0] req_uop_exc_cause; // @[mshrs.scala:109:20] reg req_uop_bypassable; // @[mshrs.scala:109:20] reg [4:0] req_uop_mem_cmd; // @[mshrs.scala:109:20] reg [1:0] req_uop_mem_size; // @[mshrs.scala:109:20] reg req_uop_mem_signed; // @[mshrs.scala:109:20] reg req_uop_is_fence; // @[mshrs.scala:109:20] reg req_uop_is_fencei; // @[mshrs.scala:109:20] reg req_uop_is_amo; // @[mshrs.scala:109:20] reg req_uop_uses_ldq; // @[mshrs.scala:109:20] reg req_uop_uses_stq; // @[mshrs.scala:109:20] reg req_uop_is_sys_pc2epc; // @[mshrs.scala:109:20] reg req_uop_is_unique; // @[mshrs.scala:109:20] reg req_uop_flush_on_commit; // @[mshrs.scala:109:20] reg req_uop_ldst_is_rs1; // @[mshrs.scala:109:20] reg [5:0] req_uop_ldst; // @[mshrs.scala:109:20] reg [5:0] req_uop_lrs1; // @[mshrs.scala:109:20] reg [5:0] req_uop_lrs2; // @[mshrs.scala:109:20] reg [5:0] req_uop_lrs3; // @[mshrs.scala:109:20] reg req_uop_ldst_val; // @[mshrs.scala:109:20] reg [1:0] req_uop_dst_rtype; // @[mshrs.scala:109:20] reg [1:0] req_uop_lrs1_rtype; // @[mshrs.scala:109:20] reg [1:0] req_uop_lrs2_rtype; // @[mshrs.scala:109:20] reg req_uop_frs3_en; // @[mshrs.scala:109:20] reg req_uop_fp_val; // @[mshrs.scala:109:20] reg req_uop_fp_single; // @[mshrs.scala:109:20] reg req_uop_xcpt_pf_if; // @[mshrs.scala:109:20] reg req_uop_xcpt_ae_if; // @[mshrs.scala:109:20] reg req_uop_xcpt_ma_if; // @[mshrs.scala:109:20] reg req_uop_bp_debug_if; // @[mshrs.scala:109:20] reg req_uop_bp_xcpt_if; // @[mshrs.scala:109:20] reg [1:0] req_uop_debug_fsrc; // @[mshrs.scala:109:20] reg [1:0] req_uop_debug_tsrc; // @[mshrs.scala:109:20] reg [39:0] req_addr; // @[mshrs.scala:109:20] assign io_commit_addr_0 = req_addr; // @[mshrs.scala:36:7, :109:20] reg [63:0] req_data; // @[mshrs.scala:109:20] reg req_is_hella; // @[mshrs.scala:109:20] reg req_tag_match; // @[mshrs.scala:109:20] reg [1:0] req_old_meta_coh_state; // @[mshrs.scala:109:20] reg [19:0] req_old_meta_tag; // @[mshrs.scala:109:20] assign io_wb_req_bits_tag_0 = req_old_meta_tag; // @[mshrs.scala:36:7, :109:20] reg [7:0] req_way_en; // @[mshrs.scala:109:20] assign io_way_bits_0 = req_way_en; // @[mshrs.scala:36:7, :109:20] assign io_refill_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20] assign io_meta_write_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20] assign io_meta_read_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20] assign io_wb_req_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20] assign io_replay_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20] reg [4:0] req_sdq_id; // @[mshrs.scala:109:20] assign req_idx = req_addr[11:6]; // @[mshrs.scala:109:20, :110:25] assign io_idx_bits_0 = req_idx; // @[mshrs.scala:36:7, :110:25] assign io_meta_write_bits_idx_0 = req_idx; // @[mshrs.scala:36:7, :110:25] assign io_meta_read_bits_idx_0 = req_idx; // @[mshrs.scala:36:7, :110:25] assign io_wb_req_bits_idx_0 = req_idx; // @[mshrs.scala:36:7, :110:25] assign req_tag = req_addr[39:12]; // @[mshrs.scala:109:20, :111:26] assign io_tag_bits_0 = req_tag; // @[mshrs.scala:36:7, :111:26] wire [33:0] _req_block_addr_T = req_addr[39:6]; // @[mshrs.scala:109:20, :112:34] wire [39:0] req_block_addr = {_req_block_addr_T, 6'h0}; // @[mshrs.scala:112:{34,51}] reg req_needs_wb; // @[mshrs.scala:113:29] reg [1:0] new_coh_state; // @[mshrs.scala:115:24] wire [3:0] _r_T_6 = {2'h2, req_old_meta_coh_state}; // @[Metadata.scala:120:19] wire _r_T_19 = _r_T_6 == 4'h8; // @[Misc.scala:56:20] wire [2:0] _r_T_21 = _r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _r_T_23 = _r_T_6 == 4'h9; // @[Misc.scala:56:20] wire [2:0] _r_T_25 = _r_T_23 ? 3'h2 : _r_T_21; // @[Misc.scala:38:36, :56:20] wire _r_T_27 = _r_T_6 == 4'hA; // @[Misc.scala:56:20] wire [2:0] _r_T_29 = _r_T_27 ? 3'h1 : _r_T_25; // @[Misc.scala:38:36, :56:20] wire _r_T_31 = _r_T_6 == 4'hB; // @[Misc.scala:56:20] wire _r_T_32 = _r_T_31; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_33 = _r_T_31 ? 3'h1 : _r_T_29; // @[Misc.scala:38:36, :56:20] wire _r_T_35 = _r_T_6 == 4'h4; // @[Misc.scala:56:20] wire _r_T_36 = ~_r_T_35 & _r_T_32; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_37 = _r_T_35 ? 3'h5 : _r_T_33; // @[Misc.scala:38:36, :56:20] wire _r_T_39 = _r_T_6 == 4'h5; // @[Misc.scala:56:20] wire _r_T_40 = ~_r_T_39 & _r_T_36; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_41 = _r_T_39 ? 3'h4 : _r_T_37; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_42 = {1'h0, _r_T_39}; // @[Misc.scala:38:63, :56:20] wire _r_T_43 = _r_T_6 == 4'h6; // @[Misc.scala:56:20] wire _r_T_44 = ~_r_T_43 & _r_T_40; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_45 = _r_T_43 ? 3'h0 : _r_T_41; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_46 = _r_T_43 ? 2'h1 : _r_T_42; // @[Misc.scala:38:63, :56:20] wire _r_T_47 = _r_T_6 == 4'h7; // @[Misc.scala:56:20] wire _r_T_48 = _r_T_47 | _r_T_44; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_49 = _r_T_47 ? 3'h0 : _r_T_45; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_50 = _r_T_47 ? 2'h1 : _r_T_46; // @[Misc.scala:38:63, :56:20] wire _r_T_51 = _r_T_6 == 4'h0; // @[Misc.scala:56:20] wire _r_T_52 = ~_r_T_51 & _r_T_48; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_53 = _r_T_51 ? 3'h5 : _r_T_49; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_54 = _r_T_51 ? 2'h0 : _r_T_50; // @[Misc.scala:38:63, :56:20] wire _r_T_55 = _r_T_6 == 4'h1; // @[Misc.scala:56:20] wire _r_T_56 = ~_r_T_55 & _r_T_52; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_57 = _r_T_55 ? 3'h4 : _r_T_53; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_58 = _r_T_55 ? 2'h1 : _r_T_54; // @[Misc.scala:38:63, :56:20] wire _r_T_59 = _r_T_6 == 4'h2; // @[Misc.scala:56:20] wire _r_T_60 = ~_r_T_59 & _r_T_56; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_61 = _r_T_59 ? 3'h3 : _r_T_57; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_62 = _r_T_59 ? 2'h2 : _r_T_58; // @[Misc.scala:38:63, :56:20] wire _r_T_63 = _r_T_6 == 4'h3; // @[Misc.scala:56:20] wire r_1 = _r_T_63 | _r_T_60; // @[Misc.scala:38:9, :56:20] assign shrink_param = _r_T_63 ? 3'h3 : _r_T_61; // @[Misc.scala:38:36, :56:20] assign io_wb_req_bits_param_0 = shrink_param; // @[Misc.scala:38:36] wire [1:0] r_3 = _r_T_63 ? 2'h2 : _r_T_62; // @[Misc.scala:38:63, :56:20] wire [1:0] coh_on_clear_state = r_3; // @[Misc.scala:38:63] wire _GEN = req_uop_mem_cmd == 5'h1; // @[Consts.scala:90:32] wire _grow_param_r_c_cat_T; // @[Consts.scala:90:32] assign _grow_param_r_c_cat_T = _GEN; // @[Consts.scala:90:32] wire _grow_param_r_c_cat_T_23; // @[Consts.scala:90:32] assign _grow_param_r_c_cat_T_23 = _GEN; // @[Consts.scala:90:32] wire _coh_on_grant_c_cat_T; // @[Consts.scala:90:32] assign _coh_on_grant_c_cat_T = _GEN; // @[Consts.scala:90:32] wire _coh_on_grant_c_cat_T_23; // @[Consts.scala:90:32] assign _coh_on_grant_c_cat_T_23 = _GEN; // @[Consts.scala:90:32] wire _r1_c_cat_T; // @[Consts.scala:90:32] assign _r1_c_cat_T = _GEN; // @[Consts.scala:90:32] wire _r1_c_cat_T_23; // @[Consts.scala:90:32] assign _r1_c_cat_T_23 = _GEN; // @[Consts.scala:90:32] wire _needs_second_acq_T_27; // @[Consts.scala:90:32] assign _needs_second_acq_T_27 = _GEN; // @[Consts.scala:90:32] wire _GEN_0 = req_uop_mem_cmd == 5'h11; // @[Consts.scala:90:49] wire _grow_param_r_c_cat_T_1; // @[Consts.scala:90:49] assign _grow_param_r_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49] wire _grow_param_r_c_cat_T_24; // @[Consts.scala:90:49] assign _grow_param_r_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49] wire _coh_on_grant_c_cat_T_1; // @[Consts.scala:90:49] assign _coh_on_grant_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49] wire _coh_on_grant_c_cat_T_24; // @[Consts.scala:90:49] assign _coh_on_grant_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49] wire _r1_c_cat_T_1; // @[Consts.scala:90:49] assign _r1_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49] wire _r1_c_cat_T_24; // @[Consts.scala:90:49] assign _r1_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49] wire _needs_second_acq_T_28; // @[Consts.scala:90:49] assign _needs_second_acq_T_28 = _GEN_0; // @[Consts.scala:90:49] wire _grow_param_r_c_cat_T_2 = _grow_param_r_c_cat_T | _grow_param_r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _GEN_1 = req_uop_mem_cmd == 5'h7; // @[Consts.scala:90:66] wire _grow_param_r_c_cat_T_3; // @[Consts.scala:90:66] assign _grow_param_r_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66] wire _grow_param_r_c_cat_T_26; // @[Consts.scala:90:66] assign _grow_param_r_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66] wire _coh_on_grant_c_cat_T_3; // @[Consts.scala:90:66] assign _coh_on_grant_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66] wire _coh_on_grant_c_cat_T_26; // @[Consts.scala:90:66] assign _coh_on_grant_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66] wire _r1_c_cat_T_3; // @[Consts.scala:90:66] assign _r1_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66] wire _r1_c_cat_T_26; // @[Consts.scala:90:66] assign _r1_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66] wire _needs_second_acq_T_30; // @[Consts.scala:90:66] assign _needs_second_acq_T_30 = _GEN_1; // @[Consts.scala:90:66] wire _grow_param_r_c_cat_T_4 = _grow_param_r_c_cat_T_2 | _grow_param_r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _GEN_2 = req_uop_mem_cmd == 5'h4; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_5; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_5 = _GEN_2; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_28; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_28 = _GEN_2; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_5; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_5 = _GEN_2; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_28; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_28 = _GEN_2; // @[package.scala:16:47] wire _r1_c_cat_T_5; // @[package.scala:16:47] assign _r1_c_cat_T_5 = _GEN_2; // @[package.scala:16:47] wire _r1_c_cat_T_28; // @[package.scala:16:47] assign _r1_c_cat_T_28 = _GEN_2; // @[package.scala:16:47] wire _needs_second_acq_T_32; // @[package.scala:16:47] assign _needs_second_acq_T_32 = _GEN_2; // @[package.scala:16:47] wire _GEN_3 = req_uop_mem_cmd == 5'h9; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_6; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_6 = _GEN_3; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_29; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_29 = _GEN_3; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_6; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_6 = _GEN_3; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_29; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_29 = _GEN_3; // @[package.scala:16:47] wire _r1_c_cat_T_6; // @[package.scala:16:47] assign _r1_c_cat_T_6 = _GEN_3; // @[package.scala:16:47] wire _r1_c_cat_T_29; // @[package.scala:16:47] assign _r1_c_cat_T_29 = _GEN_3; // @[package.scala:16:47] wire _needs_second_acq_T_33; // @[package.scala:16:47] assign _needs_second_acq_T_33 = _GEN_3; // @[package.scala:16:47] wire _GEN_4 = req_uop_mem_cmd == 5'hA; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_7; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_7 = _GEN_4; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_30; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_30 = _GEN_4; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_7; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_7 = _GEN_4; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_30; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_30 = _GEN_4; // @[package.scala:16:47] wire _r1_c_cat_T_7; // @[package.scala:16:47] assign _r1_c_cat_T_7 = _GEN_4; // @[package.scala:16:47] wire _r1_c_cat_T_30; // @[package.scala:16:47] assign _r1_c_cat_T_30 = _GEN_4; // @[package.scala:16:47] wire _needs_second_acq_T_34; // @[package.scala:16:47] assign _needs_second_acq_T_34 = _GEN_4; // @[package.scala:16:47] wire _GEN_5 = req_uop_mem_cmd == 5'hB; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_8; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_8 = _GEN_5; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_31; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_31 = _GEN_5; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_8; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_8 = _GEN_5; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_31; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_31 = _GEN_5; // @[package.scala:16:47] wire _r1_c_cat_T_8; // @[package.scala:16:47] assign _r1_c_cat_T_8 = _GEN_5; // @[package.scala:16:47] wire _r1_c_cat_T_31; // @[package.scala:16:47] assign _r1_c_cat_T_31 = _GEN_5; // @[package.scala:16:47] wire _needs_second_acq_T_35; // @[package.scala:16:47] assign _needs_second_acq_T_35 = _GEN_5; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_9 = _grow_param_r_c_cat_T_5 | _grow_param_r_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_10 = _grow_param_r_c_cat_T_9 | _grow_param_r_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_11 = _grow_param_r_c_cat_T_10 | _grow_param_r_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _GEN_6 = req_uop_mem_cmd == 5'h8; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_12; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_12 = _GEN_6; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_35; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_35 = _GEN_6; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_12; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_12 = _GEN_6; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_35; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_35 = _GEN_6; // @[package.scala:16:47] wire _r1_c_cat_T_12; // @[package.scala:16:47] assign _r1_c_cat_T_12 = _GEN_6; // @[package.scala:16:47] wire _r1_c_cat_T_35; // @[package.scala:16:47] assign _r1_c_cat_T_35 = _GEN_6; // @[package.scala:16:47] wire _needs_second_acq_T_39; // @[package.scala:16:47] assign _needs_second_acq_T_39 = _GEN_6; // @[package.scala:16:47] wire _GEN_7 = req_uop_mem_cmd == 5'hC; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_13; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_13 = _GEN_7; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_36; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_36 = _GEN_7; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_13; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_13 = _GEN_7; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_36; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_36 = _GEN_7; // @[package.scala:16:47] wire _r1_c_cat_T_13; // @[package.scala:16:47] assign _r1_c_cat_T_13 = _GEN_7; // @[package.scala:16:47] wire _r1_c_cat_T_36; // @[package.scala:16:47] assign _r1_c_cat_T_36 = _GEN_7; // @[package.scala:16:47] wire _needs_second_acq_T_40; // @[package.scala:16:47] assign _needs_second_acq_T_40 = _GEN_7; // @[package.scala:16:47] wire _GEN_8 = req_uop_mem_cmd == 5'hD; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_14; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_14 = _GEN_8; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_37; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_37 = _GEN_8; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_14; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_14 = _GEN_8; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_37; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_37 = _GEN_8; // @[package.scala:16:47] wire _r1_c_cat_T_14; // @[package.scala:16:47] assign _r1_c_cat_T_14 = _GEN_8; // @[package.scala:16:47] wire _r1_c_cat_T_37; // @[package.scala:16:47] assign _r1_c_cat_T_37 = _GEN_8; // @[package.scala:16:47] wire _needs_second_acq_T_41; // @[package.scala:16:47] assign _needs_second_acq_T_41 = _GEN_8; // @[package.scala:16:47] wire _GEN_9 = req_uop_mem_cmd == 5'hE; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_15; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_15 = _GEN_9; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_38; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_38 = _GEN_9; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_15; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_15 = _GEN_9; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_38; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_38 = _GEN_9; // @[package.scala:16:47] wire _r1_c_cat_T_15; // @[package.scala:16:47] assign _r1_c_cat_T_15 = _GEN_9; // @[package.scala:16:47] wire _r1_c_cat_T_38; // @[package.scala:16:47] assign _r1_c_cat_T_38 = _GEN_9; // @[package.scala:16:47] wire _needs_second_acq_T_42; // @[package.scala:16:47] assign _needs_second_acq_T_42 = _GEN_9; // @[package.scala:16:47] wire _GEN_10 = req_uop_mem_cmd == 5'hF; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_16; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_16 = _GEN_10; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_39; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_39 = _GEN_10; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_16; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_16 = _GEN_10; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_39; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_39 = _GEN_10; // @[package.scala:16:47] wire _r1_c_cat_T_16; // @[package.scala:16:47] assign _r1_c_cat_T_16 = _GEN_10; // @[package.scala:16:47] wire _r1_c_cat_T_39; // @[package.scala:16:47] assign _r1_c_cat_T_39 = _GEN_10; // @[package.scala:16:47] wire _needs_second_acq_T_43; // @[package.scala:16:47] assign _needs_second_acq_T_43 = _GEN_10; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_17 = _grow_param_r_c_cat_T_12 | _grow_param_r_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_18 = _grow_param_r_c_cat_T_17 | _grow_param_r_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_19 = _grow_param_r_c_cat_T_18 | _grow_param_r_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_20 = _grow_param_r_c_cat_T_19 | _grow_param_r_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_21 = _grow_param_r_c_cat_T_11 | _grow_param_r_c_cat_T_20; // @[package.scala:81:59] wire _grow_param_r_c_cat_T_22 = _grow_param_r_c_cat_T_4 | _grow_param_r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _grow_param_r_c_cat_T_25 = _grow_param_r_c_cat_T_23 | _grow_param_r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _grow_param_r_c_cat_T_27 = _grow_param_r_c_cat_T_25 | _grow_param_r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _grow_param_r_c_cat_T_32 = _grow_param_r_c_cat_T_28 | _grow_param_r_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_33 = _grow_param_r_c_cat_T_32 | _grow_param_r_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_34 = _grow_param_r_c_cat_T_33 | _grow_param_r_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_40 = _grow_param_r_c_cat_T_35 | _grow_param_r_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_41 = _grow_param_r_c_cat_T_40 | _grow_param_r_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_42 = _grow_param_r_c_cat_T_41 | _grow_param_r_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_43 = _grow_param_r_c_cat_T_42 | _grow_param_r_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_44 = _grow_param_r_c_cat_T_34 | _grow_param_r_c_cat_T_43; // @[package.scala:81:59] wire _grow_param_r_c_cat_T_45 = _grow_param_r_c_cat_T_27 | _grow_param_r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _GEN_11 = req_uop_mem_cmd == 5'h3; // @[Consts.scala:91:54] wire _grow_param_r_c_cat_T_46; // @[Consts.scala:91:54] assign _grow_param_r_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54] wire _coh_on_grant_c_cat_T_46; // @[Consts.scala:91:54] assign _coh_on_grant_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54] wire _r1_c_cat_T_46; // @[Consts.scala:91:54] assign _r1_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54] wire _needs_second_acq_T_50; // @[Consts.scala:91:54] assign _needs_second_acq_T_50 = _GEN_11; // @[Consts.scala:91:54] wire _grow_param_r_c_cat_T_47 = _grow_param_r_c_cat_T_45 | _grow_param_r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _GEN_12 = req_uop_mem_cmd == 5'h6; // @[Consts.scala:91:71] wire _grow_param_r_c_cat_T_48; // @[Consts.scala:91:71] assign _grow_param_r_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71] wire _coh_on_grant_c_cat_T_48; // @[Consts.scala:91:71] assign _coh_on_grant_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71] wire _r1_c_cat_T_48; // @[Consts.scala:91:71] assign _r1_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71] wire _needs_second_acq_T_52; // @[Consts.scala:91:71] assign _needs_second_acq_T_52 = _GEN_12; // @[Consts.scala:91:71] wire _grow_param_r_c_cat_T_49 = _grow_param_r_c_cat_T_47 | _grow_param_r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] grow_param_r_c = {_grow_param_r_c_cat_T_22, _grow_param_r_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _grow_param_r_T = {grow_param_r_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19] wire _grow_param_r_T_25 = _grow_param_r_T == 4'hC; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_27 = {1'h0, _grow_param_r_T_25}; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_28 = _grow_param_r_T == 4'hD; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_30 = _grow_param_r_T_28 ? 2'h2 : _grow_param_r_T_27; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_31 = _grow_param_r_T == 4'h4; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_33 = _grow_param_r_T_31 ? 2'h1 : _grow_param_r_T_30; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_34 = _grow_param_r_T == 4'h5; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_36 = _grow_param_r_T_34 ? 2'h2 : _grow_param_r_T_33; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_37 = _grow_param_r_T == 4'h0; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_39 = _grow_param_r_T_37 ? 2'h0 : _grow_param_r_T_36; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_40 = _grow_param_r_T == 4'hE; // @[Misc.scala:49:20] wire _grow_param_r_T_41 = _grow_param_r_T_40; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_42 = _grow_param_r_T_40 ? 2'h3 : _grow_param_r_T_39; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_43 = &_grow_param_r_T; // @[Misc.scala:49:20] wire _grow_param_r_T_44 = _grow_param_r_T_43 | _grow_param_r_T_41; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_45 = _grow_param_r_T_43 ? 2'h3 : _grow_param_r_T_42; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_46 = _grow_param_r_T == 4'h6; // @[Misc.scala:49:20] wire _grow_param_r_T_47 = _grow_param_r_T_46 | _grow_param_r_T_44; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_48 = _grow_param_r_T_46 ? 2'h2 : _grow_param_r_T_45; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_49 = _grow_param_r_T == 4'h7; // @[Misc.scala:49:20] wire _grow_param_r_T_50 = _grow_param_r_T_49 | _grow_param_r_T_47; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_51 = _grow_param_r_T_49 ? 2'h3 : _grow_param_r_T_48; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_52 = _grow_param_r_T == 4'h1; // @[Misc.scala:49:20] wire _grow_param_r_T_53 = _grow_param_r_T_52 | _grow_param_r_T_50; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_54 = _grow_param_r_T_52 ? 2'h1 : _grow_param_r_T_51; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_55 = _grow_param_r_T == 4'h2; // @[Misc.scala:49:20] wire _grow_param_r_T_56 = _grow_param_r_T_55 | _grow_param_r_T_53; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_57 = _grow_param_r_T_55 ? 2'h2 : _grow_param_r_T_54; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_58 = _grow_param_r_T == 4'h3; // @[Misc.scala:49:20] wire grow_param_r_1 = _grow_param_r_T_58 | _grow_param_r_T_56; // @[Misc.scala:35:9, :49:20] wire [1:0] grow_param = _grow_param_r_T_58 ? 2'h3 : _grow_param_r_T_57; // @[Misc.scala:35:36, :49:20] wire [1:0] grow_param_meta_state = grow_param; // @[Misc.scala:35:36] wire _coh_on_grant_c_cat_T_2 = _coh_on_grant_c_cat_T | _coh_on_grant_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _coh_on_grant_c_cat_T_4 = _coh_on_grant_c_cat_T_2 | _coh_on_grant_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _coh_on_grant_c_cat_T_9 = _coh_on_grant_c_cat_T_5 | _coh_on_grant_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_10 = _coh_on_grant_c_cat_T_9 | _coh_on_grant_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_11 = _coh_on_grant_c_cat_T_10 | _coh_on_grant_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_17 = _coh_on_grant_c_cat_T_12 | _coh_on_grant_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_18 = _coh_on_grant_c_cat_T_17 | _coh_on_grant_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_19 = _coh_on_grant_c_cat_T_18 | _coh_on_grant_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_20 = _coh_on_grant_c_cat_T_19 | _coh_on_grant_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_21 = _coh_on_grant_c_cat_T_11 | _coh_on_grant_c_cat_T_20; // @[package.scala:81:59] wire _coh_on_grant_c_cat_T_22 = _coh_on_grant_c_cat_T_4 | _coh_on_grant_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _coh_on_grant_c_cat_T_25 = _coh_on_grant_c_cat_T_23 | _coh_on_grant_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _coh_on_grant_c_cat_T_27 = _coh_on_grant_c_cat_T_25 | _coh_on_grant_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _coh_on_grant_c_cat_T_32 = _coh_on_grant_c_cat_T_28 | _coh_on_grant_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_33 = _coh_on_grant_c_cat_T_32 | _coh_on_grant_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_34 = _coh_on_grant_c_cat_T_33 | _coh_on_grant_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_40 = _coh_on_grant_c_cat_T_35 | _coh_on_grant_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_41 = _coh_on_grant_c_cat_T_40 | _coh_on_grant_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_42 = _coh_on_grant_c_cat_T_41 | _coh_on_grant_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_43 = _coh_on_grant_c_cat_T_42 | _coh_on_grant_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_44 = _coh_on_grant_c_cat_T_34 | _coh_on_grant_c_cat_T_43; // @[package.scala:81:59] wire _coh_on_grant_c_cat_T_45 = _coh_on_grant_c_cat_T_27 | _coh_on_grant_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _coh_on_grant_c_cat_T_47 = _coh_on_grant_c_cat_T_45 | _coh_on_grant_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _coh_on_grant_c_cat_T_49 = _coh_on_grant_c_cat_T_47 | _coh_on_grant_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] coh_on_grant_c = {_coh_on_grant_c_cat_T_22, _coh_on_grant_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _coh_on_grant_T = {coh_on_grant_c, io_mem_grant_bits_param_0}; // @[Metadata.scala:29:18, :84:18] wire _coh_on_grant_T_9 = _coh_on_grant_T == 4'h1; // @[Metadata.scala:84:{18,38}] wire [1:0] _coh_on_grant_T_10 = {1'h0, _coh_on_grant_T_9}; // @[Metadata.scala:84:38] wire _coh_on_grant_T_11 = _coh_on_grant_T == 4'h0; // @[Metadata.scala:84:{18,38}] wire [1:0] _coh_on_grant_T_12 = _coh_on_grant_T_11 ? 2'h2 : _coh_on_grant_T_10; // @[Metadata.scala:84:38] wire _coh_on_grant_T_13 = _coh_on_grant_T == 4'h4; // @[Metadata.scala:84:{18,38}] wire [1:0] _coh_on_grant_T_14 = _coh_on_grant_T_13 ? 2'h2 : _coh_on_grant_T_12; // @[Metadata.scala:84:38] wire _coh_on_grant_T_15 = _coh_on_grant_T == 4'hC; // @[Metadata.scala:84:{18,38}] wire [1:0] _coh_on_grant_T_16 = _coh_on_grant_T_15 ? 2'h3 : _coh_on_grant_T_14; // @[Metadata.scala:84:38] assign coh_on_grant_state = _coh_on_grant_T_16; // @[Metadata.scala:84:38, :160:20] assign io_commit_coh_state_0 = coh_on_grant_state; // @[Metadata.scala:160:20] wire _r1_c_cat_T_2 = _r1_c_cat_T | _r1_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _r1_c_cat_T_4 = _r1_c_cat_T_2 | _r1_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _r1_c_cat_T_9 = _r1_c_cat_T_5 | _r1_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_10 = _r1_c_cat_T_9 | _r1_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_11 = _r1_c_cat_T_10 | _r1_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_17 = _r1_c_cat_T_12 | _r1_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_18 = _r1_c_cat_T_17 | _r1_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_19 = _r1_c_cat_T_18 | _r1_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_20 = _r1_c_cat_T_19 | _r1_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_21 = _r1_c_cat_T_11 | _r1_c_cat_T_20; // @[package.scala:81:59] wire _r1_c_cat_T_22 = _r1_c_cat_T_4 | _r1_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _r1_c_cat_T_25 = _r1_c_cat_T_23 | _r1_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _r1_c_cat_T_27 = _r1_c_cat_T_25 | _r1_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _r1_c_cat_T_32 = _r1_c_cat_T_28 | _r1_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_33 = _r1_c_cat_T_32 | _r1_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_34 = _r1_c_cat_T_33 | _r1_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_40 = _r1_c_cat_T_35 | _r1_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_41 = _r1_c_cat_T_40 | _r1_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_42 = _r1_c_cat_T_41 | _r1_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_43 = _r1_c_cat_T_42 | _r1_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_44 = _r1_c_cat_T_34 | _r1_c_cat_T_43; // @[package.scala:81:59] wire _r1_c_cat_T_45 = _r1_c_cat_T_27 | _r1_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _r1_c_cat_T_47 = _r1_c_cat_T_45 | _r1_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _r1_c_cat_T_49 = _r1_c_cat_T_47 | _r1_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] r1_c = {_r1_c_cat_T_22, _r1_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _r1_T = {r1_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19] wire _r1_T_25 = _r1_T == 4'hC; // @[Misc.scala:49:20] wire [1:0] _r1_T_27 = {1'h0, _r1_T_25}; // @[Misc.scala:35:36, :49:20] wire _r1_T_28 = _r1_T == 4'hD; // @[Misc.scala:49:20] wire [1:0] _r1_T_30 = _r1_T_28 ? 2'h2 : _r1_T_27; // @[Misc.scala:35:36, :49:20] wire _r1_T_31 = _r1_T == 4'h4; // @[Misc.scala:49:20] wire [1:0] _r1_T_33 = _r1_T_31 ? 2'h1 : _r1_T_30; // @[Misc.scala:35:36, :49:20] wire _r1_T_34 = _r1_T == 4'h5; // @[Misc.scala:49:20] wire [1:0] _r1_T_36 = _r1_T_34 ? 2'h2 : _r1_T_33; // @[Misc.scala:35:36, :49:20] wire _r1_T_37 = _r1_T == 4'h0; // @[Misc.scala:49:20] wire [1:0] _r1_T_39 = _r1_T_37 ? 2'h0 : _r1_T_36; // @[Misc.scala:35:36, :49:20] wire _r1_T_40 = _r1_T == 4'hE; // @[Misc.scala:49:20] wire _r1_T_41 = _r1_T_40; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_42 = _r1_T_40 ? 2'h3 : _r1_T_39; // @[Misc.scala:35:36, :49:20] wire _r1_T_43 = &_r1_T; // @[Misc.scala:49:20] wire _r1_T_44 = _r1_T_43 | _r1_T_41; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_45 = _r1_T_43 ? 2'h3 : _r1_T_42; // @[Misc.scala:35:36, :49:20] wire _r1_T_46 = _r1_T == 4'h6; // @[Misc.scala:49:20] wire _r1_T_47 = _r1_T_46 | _r1_T_44; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_48 = _r1_T_46 ? 2'h2 : _r1_T_45; // @[Misc.scala:35:36, :49:20] wire _r1_T_49 = _r1_T == 4'h7; // @[Misc.scala:49:20] wire _r1_T_50 = _r1_T_49 | _r1_T_47; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_51 = _r1_T_49 ? 2'h3 : _r1_T_48; // @[Misc.scala:35:36, :49:20] wire _r1_T_52 = _r1_T == 4'h1; // @[Misc.scala:49:20] wire _r1_T_53 = _r1_T_52 | _r1_T_50; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_54 = _r1_T_52 ? 2'h1 : _r1_T_51; // @[Misc.scala:35:36, :49:20] wire _r1_T_55 = _r1_T == 4'h2; // @[Misc.scala:49:20] wire _r1_T_56 = _r1_T_55 | _r1_T_53; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_57 = _r1_T_55 ? 2'h2 : _r1_T_54; // @[Misc.scala:35:36, :49:20] wire _r1_T_58 = _r1_T == 4'h3; // @[Misc.scala:49:20] wire r1_1 = _r1_T_58 | _r1_T_56; // @[Misc.scala:35:9, :49:20] wire [1:0] r1_2 = _r1_T_58 ? 2'h3 : _r1_T_57; // @[Misc.scala:35:36, :49:20] wire _GEN_13 = io_req_uop_mem_cmd_0 == 5'h1; // @[Consts.scala:90:32] wire _r2_c_cat_T; // @[Consts.scala:90:32] assign _r2_c_cat_T = _GEN_13; // @[Consts.scala:90:32] wire _r2_c_cat_T_23; // @[Consts.scala:90:32] assign _r2_c_cat_T_23 = _GEN_13; // @[Consts.scala:90:32] wire _needs_second_acq_T; // @[Consts.scala:90:32] assign _needs_second_acq_T = _GEN_13; // @[Consts.scala:90:32] wire _dirties_cat_T; // @[Consts.scala:90:32] assign _dirties_cat_T = _GEN_13; // @[Consts.scala:90:32] wire _dirties_cat_T_23; // @[Consts.scala:90:32] assign _dirties_cat_T_23 = _GEN_13; // @[Consts.scala:90:32] wire _state_r_c_cat_T; // @[Consts.scala:90:32] assign _state_r_c_cat_T = _GEN_13; // @[Consts.scala:90:32] wire _state_r_c_cat_T_23; // @[Consts.scala:90:32] assign _state_r_c_cat_T_23 = _GEN_13; // @[Consts.scala:90:32] wire _state_T_3; // @[Consts.scala:90:32] assign _state_T_3 = _GEN_13; // @[Consts.scala:90:32] wire _r_c_cat_T_50; // @[Consts.scala:90:32] assign _r_c_cat_T_50 = _GEN_13; // @[Consts.scala:90:32] wire _r_c_cat_T_73; // @[Consts.scala:90:32] assign _r_c_cat_T_73 = _GEN_13; // @[Consts.scala:90:32] wire _state_r_c_cat_T_50; // @[Consts.scala:90:32] assign _state_r_c_cat_T_50 = _GEN_13; // @[Consts.scala:90:32] wire _state_r_c_cat_T_73; // @[Consts.scala:90:32] assign _state_r_c_cat_T_73 = _GEN_13; // @[Consts.scala:90:32] wire _state_T_37; // @[Consts.scala:90:32] assign _state_T_37 = _GEN_13; // @[Consts.scala:90:32] wire _GEN_14 = io_req_uop_mem_cmd_0 == 5'h11; // @[Consts.scala:90:49] wire _r2_c_cat_T_1; // @[Consts.scala:90:49] assign _r2_c_cat_T_1 = _GEN_14; // @[Consts.scala:90:49] wire _r2_c_cat_T_24; // @[Consts.scala:90:49] assign _r2_c_cat_T_24 = _GEN_14; // @[Consts.scala:90:49] wire _needs_second_acq_T_1; // @[Consts.scala:90:49] assign _needs_second_acq_T_1 = _GEN_14; // @[Consts.scala:90:49] wire _dirties_cat_T_1; // @[Consts.scala:90:49] assign _dirties_cat_T_1 = _GEN_14; // @[Consts.scala:90:49] wire _dirties_cat_T_24; // @[Consts.scala:90:49] assign _dirties_cat_T_24 = _GEN_14; // @[Consts.scala:90:49] wire _state_r_c_cat_T_1; // @[Consts.scala:90:49] assign _state_r_c_cat_T_1 = _GEN_14; // @[Consts.scala:90:49] wire _state_r_c_cat_T_24; // @[Consts.scala:90:49] assign _state_r_c_cat_T_24 = _GEN_14; // @[Consts.scala:90:49] wire _state_T_4; // @[Consts.scala:90:49] assign _state_T_4 = _GEN_14; // @[Consts.scala:90:49] wire _r_c_cat_T_51; // @[Consts.scala:90:49] assign _r_c_cat_T_51 = _GEN_14; // @[Consts.scala:90:49] wire _r_c_cat_T_74; // @[Consts.scala:90:49] assign _r_c_cat_T_74 = _GEN_14; // @[Consts.scala:90:49] wire _state_r_c_cat_T_51; // @[Consts.scala:90:49] assign _state_r_c_cat_T_51 = _GEN_14; // @[Consts.scala:90:49] wire _state_r_c_cat_T_74; // @[Consts.scala:90:49] assign _state_r_c_cat_T_74 = _GEN_14; // @[Consts.scala:90:49] wire _state_T_38; // @[Consts.scala:90:49] assign _state_T_38 = _GEN_14; // @[Consts.scala:90:49] wire _r2_c_cat_T_2 = _r2_c_cat_T | _r2_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _GEN_15 = io_req_uop_mem_cmd_0 == 5'h7; // @[Consts.scala:90:66] wire _r2_c_cat_T_3; // @[Consts.scala:90:66] assign _r2_c_cat_T_3 = _GEN_15; // @[Consts.scala:90:66] wire _r2_c_cat_T_26; // @[Consts.scala:90:66] assign _r2_c_cat_T_26 = _GEN_15; // @[Consts.scala:90:66] wire _needs_second_acq_T_3; // @[Consts.scala:90:66] assign _needs_second_acq_T_3 = _GEN_15; // @[Consts.scala:90:66] wire _dirties_cat_T_3; // @[Consts.scala:90:66] assign _dirties_cat_T_3 = _GEN_15; // @[Consts.scala:90:66] wire _dirties_cat_T_26; // @[Consts.scala:90:66] assign _dirties_cat_T_26 = _GEN_15; // @[Consts.scala:90:66] wire _state_r_c_cat_T_3; // @[Consts.scala:90:66] assign _state_r_c_cat_T_3 = _GEN_15; // @[Consts.scala:90:66] wire _state_r_c_cat_T_26; // @[Consts.scala:90:66] assign _state_r_c_cat_T_26 = _GEN_15; // @[Consts.scala:90:66] wire _state_T_6; // @[Consts.scala:90:66] assign _state_T_6 = _GEN_15; // @[Consts.scala:90:66] wire _r_c_cat_T_53; // @[Consts.scala:90:66] assign _r_c_cat_T_53 = _GEN_15; // @[Consts.scala:90:66] wire _r_c_cat_T_76; // @[Consts.scala:90:66] assign _r_c_cat_T_76 = _GEN_15; // @[Consts.scala:90:66] wire _state_r_c_cat_T_53; // @[Consts.scala:90:66] assign _state_r_c_cat_T_53 = _GEN_15; // @[Consts.scala:90:66] wire _state_r_c_cat_T_76; // @[Consts.scala:90:66] assign _state_r_c_cat_T_76 = _GEN_15; // @[Consts.scala:90:66] wire _state_T_40; // @[Consts.scala:90:66] assign _state_T_40 = _GEN_15; // @[Consts.scala:90:66] wire _r2_c_cat_T_4 = _r2_c_cat_T_2 | _r2_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _GEN_16 = io_req_uop_mem_cmd_0 == 5'h4; // @[package.scala:16:47] wire _r2_c_cat_T_5; // @[package.scala:16:47] assign _r2_c_cat_T_5 = _GEN_16; // @[package.scala:16:47] wire _r2_c_cat_T_28; // @[package.scala:16:47] assign _r2_c_cat_T_28 = _GEN_16; // @[package.scala:16:47] wire _needs_second_acq_T_5; // @[package.scala:16:47] assign _needs_second_acq_T_5 = _GEN_16; // @[package.scala:16:47] wire _dirties_cat_T_5; // @[package.scala:16:47] assign _dirties_cat_T_5 = _GEN_16; // @[package.scala:16:47] wire _dirties_cat_T_28; // @[package.scala:16:47] assign _dirties_cat_T_28 = _GEN_16; // @[package.scala:16:47] wire _state_r_c_cat_T_5; // @[package.scala:16:47] assign _state_r_c_cat_T_5 = _GEN_16; // @[package.scala:16:47] wire _state_r_c_cat_T_28; // @[package.scala:16:47] assign _state_r_c_cat_T_28 = _GEN_16; // @[package.scala:16:47] wire _state_T_8; // @[package.scala:16:47] assign _state_T_8 = _GEN_16; // @[package.scala:16:47] wire _r_c_cat_T_55; // @[package.scala:16:47] assign _r_c_cat_T_55 = _GEN_16; // @[package.scala:16:47] wire _r_c_cat_T_78; // @[package.scala:16:47] assign _r_c_cat_T_78 = _GEN_16; // @[package.scala:16:47] wire _state_r_c_cat_T_55; // @[package.scala:16:47] assign _state_r_c_cat_T_55 = _GEN_16; // @[package.scala:16:47] wire _state_r_c_cat_T_78; // @[package.scala:16:47] assign _state_r_c_cat_T_78 = _GEN_16; // @[package.scala:16:47] wire _state_T_42; // @[package.scala:16:47] assign _state_T_42 = _GEN_16; // @[package.scala:16:47] wire _GEN_17 = io_req_uop_mem_cmd_0 == 5'h9; // @[package.scala:16:47] wire _r2_c_cat_T_6; // @[package.scala:16:47] assign _r2_c_cat_T_6 = _GEN_17; // @[package.scala:16:47] wire _r2_c_cat_T_29; // @[package.scala:16:47] assign _r2_c_cat_T_29 = _GEN_17; // @[package.scala:16:47] wire _needs_second_acq_T_6; // @[package.scala:16:47] assign _needs_second_acq_T_6 = _GEN_17; // @[package.scala:16:47] wire _dirties_cat_T_6; // @[package.scala:16:47] assign _dirties_cat_T_6 = _GEN_17; // @[package.scala:16:47] wire _dirties_cat_T_29; // @[package.scala:16:47] assign _dirties_cat_T_29 = _GEN_17; // @[package.scala:16:47] wire _state_r_c_cat_T_6; // @[package.scala:16:47] assign _state_r_c_cat_T_6 = _GEN_17; // @[package.scala:16:47] wire _state_r_c_cat_T_29; // @[package.scala:16:47] assign _state_r_c_cat_T_29 = _GEN_17; // @[package.scala:16:47] wire _state_T_9; // @[package.scala:16:47] assign _state_T_9 = _GEN_17; // @[package.scala:16:47] wire _r_c_cat_T_56; // @[package.scala:16:47] assign _r_c_cat_T_56 = _GEN_17; // @[package.scala:16:47] wire _r_c_cat_T_79; // @[package.scala:16:47] assign _r_c_cat_T_79 = _GEN_17; // @[package.scala:16:47] wire _state_r_c_cat_T_56; // @[package.scala:16:47] assign _state_r_c_cat_T_56 = _GEN_17; // @[package.scala:16:47] wire _state_r_c_cat_T_79; // @[package.scala:16:47] assign _state_r_c_cat_T_79 = _GEN_17; // @[package.scala:16:47] wire _state_T_43; // @[package.scala:16:47] assign _state_T_43 = _GEN_17; // @[package.scala:16:47] wire _GEN_18 = io_req_uop_mem_cmd_0 == 5'hA; // @[package.scala:16:47] wire _r2_c_cat_T_7; // @[package.scala:16:47] assign _r2_c_cat_T_7 = _GEN_18; // @[package.scala:16:47] wire _r2_c_cat_T_30; // @[package.scala:16:47] assign _r2_c_cat_T_30 = _GEN_18; // @[package.scala:16:47] wire _needs_second_acq_T_7; // @[package.scala:16:47] assign _needs_second_acq_T_7 = _GEN_18; // @[package.scala:16:47] wire _dirties_cat_T_7; // @[package.scala:16:47] assign _dirties_cat_T_7 = _GEN_18; // @[package.scala:16:47] wire _dirties_cat_T_30; // @[package.scala:16:47] assign _dirties_cat_T_30 = _GEN_18; // @[package.scala:16:47] wire _state_r_c_cat_T_7; // @[package.scala:16:47] assign _state_r_c_cat_T_7 = _GEN_18; // @[package.scala:16:47] wire _state_r_c_cat_T_30; // @[package.scala:16:47] assign _state_r_c_cat_T_30 = _GEN_18; // @[package.scala:16:47] wire _state_T_10; // @[package.scala:16:47] assign _state_T_10 = _GEN_18; // @[package.scala:16:47] wire _r_c_cat_T_57; // @[package.scala:16:47] assign _r_c_cat_T_57 = _GEN_18; // @[package.scala:16:47] wire _r_c_cat_T_80; // @[package.scala:16:47] assign _r_c_cat_T_80 = _GEN_18; // @[package.scala:16:47] wire _state_r_c_cat_T_57; // @[package.scala:16:47] assign _state_r_c_cat_T_57 = _GEN_18; // @[package.scala:16:47] wire _state_r_c_cat_T_80; // @[package.scala:16:47] assign _state_r_c_cat_T_80 = _GEN_18; // @[package.scala:16:47] wire _state_T_44; // @[package.scala:16:47] assign _state_T_44 = _GEN_18; // @[package.scala:16:47] wire _GEN_19 = io_req_uop_mem_cmd_0 == 5'hB; // @[package.scala:16:47] wire _r2_c_cat_T_8; // @[package.scala:16:47] assign _r2_c_cat_T_8 = _GEN_19; // @[package.scala:16:47] wire _r2_c_cat_T_31; // @[package.scala:16:47] assign _r2_c_cat_T_31 = _GEN_19; // @[package.scala:16:47] wire _needs_second_acq_T_8; // @[package.scala:16:47] assign _needs_second_acq_T_8 = _GEN_19; // @[package.scala:16:47] wire _dirties_cat_T_8; // @[package.scala:16:47] assign _dirties_cat_T_8 = _GEN_19; // @[package.scala:16:47] wire _dirties_cat_T_31; // @[package.scala:16:47] assign _dirties_cat_T_31 = _GEN_19; // @[package.scala:16:47] wire _state_r_c_cat_T_8; // @[package.scala:16:47] assign _state_r_c_cat_T_8 = _GEN_19; // @[package.scala:16:47] wire _state_r_c_cat_T_31; // @[package.scala:16:47] assign _state_r_c_cat_T_31 = _GEN_19; // @[package.scala:16:47] wire _state_T_11; // @[package.scala:16:47] assign _state_T_11 = _GEN_19; // @[package.scala:16:47] wire _r_c_cat_T_58; // @[package.scala:16:47] assign _r_c_cat_T_58 = _GEN_19; // @[package.scala:16:47] wire _r_c_cat_T_81; // @[package.scala:16:47] assign _r_c_cat_T_81 = _GEN_19; // @[package.scala:16:47] wire _state_r_c_cat_T_58; // @[package.scala:16:47] assign _state_r_c_cat_T_58 = _GEN_19; // @[package.scala:16:47] wire _state_r_c_cat_T_81; // @[package.scala:16:47] assign _state_r_c_cat_T_81 = _GEN_19; // @[package.scala:16:47] wire _state_T_45; // @[package.scala:16:47] assign _state_T_45 = _GEN_19; // @[package.scala:16:47] wire _r2_c_cat_T_9 = _r2_c_cat_T_5 | _r2_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_10 = _r2_c_cat_T_9 | _r2_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_11 = _r2_c_cat_T_10 | _r2_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _GEN_20 = io_req_uop_mem_cmd_0 == 5'h8; // @[package.scala:16:47] wire _r2_c_cat_T_12; // @[package.scala:16:47] assign _r2_c_cat_T_12 = _GEN_20; // @[package.scala:16:47] wire _r2_c_cat_T_35; // @[package.scala:16:47] assign _r2_c_cat_T_35 = _GEN_20; // @[package.scala:16:47] wire _needs_second_acq_T_12; // @[package.scala:16:47] assign _needs_second_acq_T_12 = _GEN_20; // @[package.scala:16:47] wire _dirties_cat_T_12; // @[package.scala:16:47] assign _dirties_cat_T_12 = _GEN_20; // @[package.scala:16:47] wire _dirties_cat_T_35; // @[package.scala:16:47] assign _dirties_cat_T_35 = _GEN_20; // @[package.scala:16:47] wire _state_r_c_cat_T_12; // @[package.scala:16:47] assign _state_r_c_cat_T_12 = _GEN_20; // @[package.scala:16:47] wire _state_r_c_cat_T_35; // @[package.scala:16:47] assign _state_r_c_cat_T_35 = _GEN_20; // @[package.scala:16:47] wire _state_T_15; // @[package.scala:16:47] assign _state_T_15 = _GEN_20; // @[package.scala:16:47] wire _r_c_cat_T_62; // @[package.scala:16:47] assign _r_c_cat_T_62 = _GEN_20; // @[package.scala:16:47] wire _r_c_cat_T_85; // @[package.scala:16:47] assign _r_c_cat_T_85 = _GEN_20; // @[package.scala:16:47] wire _state_r_c_cat_T_62; // @[package.scala:16:47] assign _state_r_c_cat_T_62 = _GEN_20; // @[package.scala:16:47] wire _state_r_c_cat_T_85; // @[package.scala:16:47] assign _state_r_c_cat_T_85 = _GEN_20; // @[package.scala:16:47] wire _state_T_49; // @[package.scala:16:47] assign _state_T_49 = _GEN_20; // @[package.scala:16:47] wire _GEN_21 = io_req_uop_mem_cmd_0 == 5'hC; // @[package.scala:16:47] wire _r2_c_cat_T_13; // @[package.scala:16:47] assign _r2_c_cat_T_13 = _GEN_21; // @[package.scala:16:47] wire _r2_c_cat_T_36; // @[package.scala:16:47] assign _r2_c_cat_T_36 = _GEN_21; // @[package.scala:16:47] wire _needs_second_acq_T_13; // @[package.scala:16:47] assign _needs_second_acq_T_13 = _GEN_21; // @[package.scala:16:47] wire _dirties_cat_T_13; // @[package.scala:16:47] assign _dirties_cat_T_13 = _GEN_21; // @[package.scala:16:47] wire _dirties_cat_T_36; // @[package.scala:16:47] assign _dirties_cat_T_36 = _GEN_21; // @[package.scala:16:47] wire _state_r_c_cat_T_13; // @[package.scala:16:47] assign _state_r_c_cat_T_13 = _GEN_21; // @[package.scala:16:47] wire _state_r_c_cat_T_36; // @[package.scala:16:47] assign _state_r_c_cat_T_36 = _GEN_21; // @[package.scala:16:47] wire _state_T_16; // @[package.scala:16:47] assign _state_T_16 = _GEN_21; // @[package.scala:16:47] wire _r_c_cat_T_63; // @[package.scala:16:47] assign _r_c_cat_T_63 = _GEN_21; // @[package.scala:16:47] wire _r_c_cat_T_86; // @[package.scala:16:47] assign _r_c_cat_T_86 = _GEN_21; // @[package.scala:16:47] wire _state_r_c_cat_T_63; // @[package.scala:16:47] assign _state_r_c_cat_T_63 = _GEN_21; // @[package.scala:16:47] wire _state_r_c_cat_T_86; // @[package.scala:16:47] assign _state_r_c_cat_T_86 = _GEN_21; // @[package.scala:16:47] wire _state_T_50; // @[package.scala:16:47] assign _state_T_50 = _GEN_21; // @[package.scala:16:47] wire _GEN_22 = io_req_uop_mem_cmd_0 == 5'hD; // @[package.scala:16:47] wire _r2_c_cat_T_14; // @[package.scala:16:47] assign _r2_c_cat_T_14 = _GEN_22; // @[package.scala:16:47] wire _r2_c_cat_T_37; // @[package.scala:16:47] assign _r2_c_cat_T_37 = _GEN_22; // @[package.scala:16:47] wire _needs_second_acq_T_14; // @[package.scala:16:47] assign _needs_second_acq_T_14 = _GEN_22; // @[package.scala:16:47] wire _dirties_cat_T_14; // @[package.scala:16:47] assign _dirties_cat_T_14 = _GEN_22; // @[package.scala:16:47] wire _dirties_cat_T_37; // @[package.scala:16:47] assign _dirties_cat_T_37 = _GEN_22; // @[package.scala:16:47] wire _state_r_c_cat_T_14; // @[package.scala:16:47] assign _state_r_c_cat_T_14 = _GEN_22; // @[package.scala:16:47] wire _state_r_c_cat_T_37; // @[package.scala:16:47] assign _state_r_c_cat_T_37 = _GEN_22; // @[package.scala:16:47] wire _state_T_17; // @[package.scala:16:47] assign _state_T_17 = _GEN_22; // @[package.scala:16:47] wire _r_c_cat_T_64; // @[package.scala:16:47] assign _r_c_cat_T_64 = _GEN_22; // @[package.scala:16:47] wire _r_c_cat_T_87; // @[package.scala:16:47] assign _r_c_cat_T_87 = _GEN_22; // @[package.scala:16:47] wire _state_r_c_cat_T_64; // @[package.scala:16:47] assign _state_r_c_cat_T_64 = _GEN_22; // @[package.scala:16:47] wire _state_r_c_cat_T_87; // @[package.scala:16:47] assign _state_r_c_cat_T_87 = _GEN_22; // @[package.scala:16:47] wire _state_T_51; // @[package.scala:16:47] assign _state_T_51 = _GEN_22; // @[package.scala:16:47] wire _GEN_23 = io_req_uop_mem_cmd_0 == 5'hE; // @[package.scala:16:47] wire _r2_c_cat_T_15; // @[package.scala:16:47] assign _r2_c_cat_T_15 = _GEN_23; // @[package.scala:16:47] wire _r2_c_cat_T_38; // @[package.scala:16:47] assign _r2_c_cat_T_38 = _GEN_23; // @[package.scala:16:47] wire _needs_second_acq_T_15; // @[package.scala:16:47] assign _needs_second_acq_T_15 = _GEN_23; // @[package.scala:16:47] wire _dirties_cat_T_15; // @[package.scala:16:47] assign _dirties_cat_T_15 = _GEN_23; // @[package.scala:16:47] wire _dirties_cat_T_38; // @[package.scala:16:47] assign _dirties_cat_T_38 = _GEN_23; // @[package.scala:16:47] wire _state_r_c_cat_T_15; // @[package.scala:16:47] assign _state_r_c_cat_T_15 = _GEN_23; // @[package.scala:16:47] wire _state_r_c_cat_T_38; // @[package.scala:16:47] assign _state_r_c_cat_T_38 = _GEN_23; // @[package.scala:16:47] wire _state_T_18; // @[package.scala:16:47] assign _state_T_18 = _GEN_23; // @[package.scala:16:47] wire _r_c_cat_T_65; // @[package.scala:16:47] assign _r_c_cat_T_65 = _GEN_23; // @[package.scala:16:47] wire _r_c_cat_T_88; // @[package.scala:16:47] assign _r_c_cat_T_88 = _GEN_23; // @[package.scala:16:47] wire _state_r_c_cat_T_65; // @[package.scala:16:47] assign _state_r_c_cat_T_65 = _GEN_23; // @[package.scala:16:47] wire _state_r_c_cat_T_88; // @[package.scala:16:47] assign _state_r_c_cat_T_88 = _GEN_23; // @[package.scala:16:47] wire _state_T_52; // @[package.scala:16:47] assign _state_T_52 = _GEN_23; // @[package.scala:16:47] wire _GEN_24 = io_req_uop_mem_cmd_0 == 5'hF; // @[package.scala:16:47] wire _r2_c_cat_T_16; // @[package.scala:16:47] assign _r2_c_cat_T_16 = _GEN_24; // @[package.scala:16:47] wire _r2_c_cat_T_39; // @[package.scala:16:47] assign _r2_c_cat_T_39 = _GEN_24; // @[package.scala:16:47] wire _needs_second_acq_T_16; // @[package.scala:16:47] assign _needs_second_acq_T_16 = _GEN_24; // @[package.scala:16:47] wire _dirties_cat_T_16; // @[package.scala:16:47] assign _dirties_cat_T_16 = _GEN_24; // @[package.scala:16:47] wire _dirties_cat_T_39; // @[package.scala:16:47] assign _dirties_cat_T_39 = _GEN_24; // @[package.scala:16:47] wire _state_r_c_cat_T_16; // @[package.scala:16:47] assign _state_r_c_cat_T_16 = _GEN_24; // @[package.scala:16:47] wire _state_r_c_cat_T_39; // @[package.scala:16:47] assign _state_r_c_cat_T_39 = _GEN_24; // @[package.scala:16:47] wire _state_T_19; // @[package.scala:16:47] assign _state_T_19 = _GEN_24; // @[package.scala:16:47] wire _r_c_cat_T_66; // @[package.scala:16:47] assign _r_c_cat_T_66 = _GEN_24; // @[package.scala:16:47] wire _r_c_cat_T_89; // @[package.scala:16:47] assign _r_c_cat_T_89 = _GEN_24; // @[package.scala:16:47] wire _state_r_c_cat_T_66; // @[package.scala:16:47] assign _state_r_c_cat_T_66 = _GEN_24; // @[package.scala:16:47] wire _state_r_c_cat_T_89; // @[package.scala:16:47] assign _state_r_c_cat_T_89 = _GEN_24; // @[package.scala:16:47] wire _state_T_53; // @[package.scala:16:47] assign _state_T_53 = _GEN_24; // @[package.scala:16:47] wire _r2_c_cat_T_17 = _r2_c_cat_T_12 | _r2_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_18 = _r2_c_cat_T_17 | _r2_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_19 = _r2_c_cat_T_18 | _r2_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_20 = _r2_c_cat_T_19 | _r2_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_21 = _r2_c_cat_T_11 | _r2_c_cat_T_20; // @[package.scala:81:59] wire _r2_c_cat_T_22 = _r2_c_cat_T_4 | _r2_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _r2_c_cat_T_25 = _r2_c_cat_T_23 | _r2_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _r2_c_cat_T_27 = _r2_c_cat_T_25 | _r2_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _r2_c_cat_T_32 = _r2_c_cat_T_28 | _r2_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_33 = _r2_c_cat_T_32 | _r2_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_34 = _r2_c_cat_T_33 | _r2_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_40 = _r2_c_cat_T_35 | _r2_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_41 = _r2_c_cat_T_40 | _r2_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_42 = _r2_c_cat_T_41 | _r2_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_43 = _r2_c_cat_T_42 | _r2_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_44 = _r2_c_cat_T_34 | _r2_c_cat_T_43; // @[package.scala:81:59] wire _r2_c_cat_T_45 = _r2_c_cat_T_27 | _r2_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _GEN_25 = io_req_uop_mem_cmd_0 == 5'h3; // @[Consts.scala:91:54] wire _r2_c_cat_T_46; // @[Consts.scala:91:54] assign _r2_c_cat_T_46 = _GEN_25; // @[Consts.scala:91:54] wire _needs_second_acq_T_23; // @[Consts.scala:91:54] assign _needs_second_acq_T_23 = _GEN_25; // @[Consts.scala:91:54] wire _dirties_cat_T_46; // @[Consts.scala:91:54] assign _dirties_cat_T_46 = _GEN_25; // @[Consts.scala:91:54] wire _rpq_io_enq_valid_T_4; // @[Consts.scala:88:52] assign _rpq_io_enq_valid_T_4 = _GEN_25; // @[Consts.scala:88:52, :91:54] wire _state_r_c_cat_T_46; // @[Consts.scala:91:54] assign _state_r_c_cat_T_46 = _GEN_25; // @[Consts.scala:91:54] wire _r_c_cat_T_96; // @[Consts.scala:91:54] assign _r_c_cat_T_96 = _GEN_25; // @[Consts.scala:91:54] wire _state_r_c_cat_T_96; // @[Consts.scala:91:54] assign _state_r_c_cat_T_96 = _GEN_25; // @[Consts.scala:91:54] wire _r2_c_cat_T_47 = _r2_c_cat_T_45 | _r2_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _GEN_26 = io_req_uop_mem_cmd_0 == 5'h6; // @[Consts.scala:91:71] wire _r2_c_cat_T_48; // @[Consts.scala:91:71] assign _r2_c_cat_T_48 = _GEN_26; // @[Consts.scala:91:71] wire _needs_second_acq_T_25; // @[Consts.scala:91:71] assign _needs_second_acq_T_25 = _GEN_26; // @[Consts.scala:91:71] wire _dirties_cat_T_48; // @[Consts.scala:91:71] assign _dirties_cat_T_48 = _GEN_26; // @[Consts.scala:91:71] wire _state_r_c_cat_T_48; // @[Consts.scala:91:71] assign _state_r_c_cat_T_48 = _GEN_26; // @[Consts.scala:91:71] wire _r_c_cat_T_98; // @[Consts.scala:91:71] assign _r_c_cat_T_98 = _GEN_26; // @[Consts.scala:91:71] wire _state_r_c_cat_T_98; // @[Consts.scala:91:71] assign _state_r_c_cat_T_98 = _GEN_26; // @[Consts.scala:91:71] wire _r2_c_cat_T_49 = _r2_c_cat_T_47 | _r2_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] r2_c = {_r2_c_cat_T_22, _r2_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _r2_T = {r2_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19] wire _r2_T_25 = _r2_T == 4'hC; // @[Misc.scala:49:20] wire [1:0] _r2_T_27 = {1'h0, _r2_T_25}; // @[Misc.scala:35:36, :49:20] wire _r2_T_28 = _r2_T == 4'hD; // @[Misc.scala:49:20] wire [1:0] _r2_T_30 = _r2_T_28 ? 2'h2 : _r2_T_27; // @[Misc.scala:35:36, :49:20] wire _r2_T_31 = _r2_T == 4'h4; // @[Misc.scala:49:20] wire [1:0] _r2_T_33 = _r2_T_31 ? 2'h1 : _r2_T_30; // @[Misc.scala:35:36, :49:20] wire _r2_T_34 = _r2_T == 4'h5; // @[Misc.scala:49:20] wire [1:0] _r2_T_36 = _r2_T_34 ? 2'h2 : _r2_T_33; // @[Misc.scala:35:36, :49:20] wire _r2_T_37 = _r2_T == 4'h0; // @[Misc.scala:49:20] wire [1:0] _r2_T_39 = _r2_T_37 ? 2'h0 : _r2_T_36; // @[Misc.scala:35:36, :49:20] wire _r2_T_40 = _r2_T == 4'hE; // @[Misc.scala:49:20] wire _r2_T_41 = _r2_T_40; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_42 = _r2_T_40 ? 2'h3 : _r2_T_39; // @[Misc.scala:35:36, :49:20] wire _r2_T_43 = &_r2_T; // @[Misc.scala:49:20] wire _r2_T_44 = _r2_T_43 | _r2_T_41; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_45 = _r2_T_43 ? 2'h3 : _r2_T_42; // @[Misc.scala:35:36, :49:20] wire _r2_T_46 = _r2_T == 4'h6; // @[Misc.scala:49:20] wire _r2_T_47 = _r2_T_46 | _r2_T_44; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_48 = _r2_T_46 ? 2'h2 : _r2_T_45; // @[Misc.scala:35:36, :49:20] wire _r2_T_49 = _r2_T == 4'h7; // @[Misc.scala:49:20] wire _r2_T_50 = _r2_T_49 | _r2_T_47; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_51 = _r2_T_49 ? 2'h3 : _r2_T_48; // @[Misc.scala:35:36, :49:20] wire _r2_T_52 = _r2_T == 4'h1; // @[Misc.scala:49:20] wire _r2_T_53 = _r2_T_52 | _r2_T_50; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_54 = _r2_T_52 ? 2'h1 : _r2_T_51; // @[Misc.scala:35:36, :49:20] wire _r2_T_55 = _r2_T == 4'h2; // @[Misc.scala:49:20] wire _r2_T_56 = _r2_T_55 | _r2_T_53; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_57 = _r2_T_55 ? 2'h2 : _r2_T_54; // @[Misc.scala:35:36, :49:20] wire _r2_T_58 = _r2_T == 4'h3; // @[Misc.scala:49:20] wire r2_1 = _r2_T_58 | _r2_T_56; // @[Misc.scala:35:9, :49:20] wire [1:0] r2_2 = _r2_T_58 ? 2'h3 : _r2_T_57; // @[Misc.scala:35:36, :49:20] wire _needs_second_acq_T_2 = _needs_second_acq_T | _needs_second_acq_T_1; // @[Consts.scala:90:{32,42,49}] wire _needs_second_acq_T_4 = _needs_second_acq_T_2 | _needs_second_acq_T_3; // @[Consts.scala:90:{42,59,66}] wire _needs_second_acq_T_9 = _needs_second_acq_T_5 | _needs_second_acq_T_6; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_10 = _needs_second_acq_T_9 | _needs_second_acq_T_7; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_11 = _needs_second_acq_T_10 | _needs_second_acq_T_8; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_17 = _needs_second_acq_T_12 | _needs_second_acq_T_13; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_18 = _needs_second_acq_T_17 | _needs_second_acq_T_14; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_19 = _needs_second_acq_T_18 | _needs_second_acq_T_15; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_20 = _needs_second_acq_T_19 | _needs_second_acq_T_16; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_21 = _needs_second_acq_T_11 | _needs_second_acq_T_20; // @[package.scala:81:59] wire _needs_second_acq_T_22 = _needs_second_acq_T_4 | _needs_second_acq_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _needs_second_acq_T_24 = _needs_second_acq_T_22 | _needs_second_acq_T_23; // @[Consts.scala:90:76, :91:{47,54}] wire _needs_second_acq_T_26 = _needs_second_acq_T_24 | _needs_second_acq_T_25; // @[Consts.scala:91:{47,64,71}] wire _needs_second_acq_T_29 = _needs_second_acq_T_27 | _needs_second_acq_T_28; // @[Consts.scala:90:{32,42,49}] wire _needs_second_acq_T_31 = _needs_second_acq_T_29 | _needs_second_acq_T_30; // @[Consts.scala:90:{42,59,66}] wire _needs_second_acq_T_36 = _needs_second_acq_T_32 | _needs_second_acq_T_33; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_37 = _needs_second_acq_T_36 | _needs_second_acq_T_34; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_38 = _needs_second_acq_T_37 | _needs_second_acq_T_35; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_44 = _needs_second_acq_T_39 | _needs_second_acq_T_40; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_45 = _needs_second_acq_T_44 | _needs_second_acq_T_41; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_46 = _needs_second_acq_T_45 | _needs_second_acq_T_42; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_47 = _needs_second_acq_T_46 | _needs_second_acq_T_43; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_48 = _needs_second_acq_T_38 | _needs_second_acq_T_47; // @[package.scala:81:59] wire _needs_second_acq_T_49 = _needs_second_acq_T_31 | _needs_second_acq_T_48; // @[Consts.scala:87:44, :90:{59,76}] wire _needs_second_acq_T_51 = _needs_second_acq_T_49 | _needs_second_acq_T_50; // @[Consts.scala:90:76, :91:{47,54}] wire _needs_second_acq_T_53 = _needs_second_acq_T_51 | _needs_second_acq_T_52; // @[Consts.scala:91:{47,64,71}] wire _needs_second_acq_T_54 = ~_needs_second_acq_T_53; // @[Metadata.scala:104:57] wire cmd_requires_second_acquire = _needs_second_acq_T_26 & _needs_second_acq_T_54; // @[Metadata.scala:104:{54,57}] wire is_hit_again = r1_1 & r2_1; // @[Misc.scala:35:9] wire _dirties_cat_T_2 = _dirties_cat_T | _dirties_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _dirties_cat_T_4 = _dirties_cat_T_2 | _dirties_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _dirties_cat_T_9 = _dirties_cat_T_5 | _dirties_cat_T_6; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_10 = _dirties_cat_T_9 | _dirties_cat_T_7; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_11 = _dirties_cat_T_10 | _dirties_cat_T_8; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_17 = _dirties_cat_T_12 | _dirties_cat_T_13; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_18 = _dirties_cat_T_17 | _dirties_cat_T_14; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_19 = _dirties_cat_T_18 | _dirties_cat_T_15; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_20 = _dirties_cat_T_19 | _dirties_cat_T_16; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_21 = _dirties_cat_T_11 | _dirties_cat_T_20; // @[package.scala:81:59] wire _dirties_cat_T_22 = _dirties_cat_T_4 | _dirties_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _dirties_cat_T_25 = _dirties_cat_T_23 | _dirties_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _dirties_cat_T_27 = _dirties_cat_T_25 | _dirties_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _dirties_cat_T_32 = _dirties_cat_T_28 | _dirties_cat_T_29; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_33 = _dirties_cat_T_32 | _dirties_cat_T_30; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_34 = _dirties_cat_T_33 | _dirties_cat_T_31; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_40 = _dirties_cat_T_35 | _dirties_cat_T_36; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_41 = _dirties_cat_T_40 | _dirties_cat_T_37; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_42 = _dirties_cat_T_41 | _dirties_cat_T_38; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_43 = _dirties_cat_T_42 | _dirties_cat_T_39; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_44 = _dirties_cat_T_34 | _dirties_cat_T_43; // @[package.scala:81:59] wire _dirties_cat_T_45 = _dirties_cat_T_27 | _dirties_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _dirties_cat_T_47 = _dirties_cat_T_45 | _dirties_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _dirties_cat_T_49 = _dirties_cat_T_47 | _dirties_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] dirties_cat = {_dirties_cat_T_22, _dirties_cat_T_49}; // @[Metadata.scala:29:18] wire dirties = &dirties_cat; // @[Metadata.scala:29:18, :106:42] wire [1:0] biggest_grow_param = dirties ? r2_2 : r1_2; // @[Misc.scala:35:36] wire [1:0] dirtier_coh_state = biggest_grow_param; // @[Metadata.scala:107:33, :160:20] wire [4:0] dirtier_cmd = dirties ? io_req_uop_mem_cmd_0 : req_uop_mem_cmd; // @[Metadata.scala:106:42, :109:27] wire _T_16 = io_mem_grant_ready_0 & io_mem_grant_valid_0; // @[Decoupled.scala:51:35] wire [26:0] _r_beats1_decode_T = 27'hFFF << io_mem_grant_bits_size_0; // @[package.scala:243:71] wire [11:0] _r_beats1_decode_T_1 = _r_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _r_beats1_decode_T_2 = ~_r_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] r_beats1_decode = _r_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire r_beats1_opdata = io_mem_grant_bits_opcode_0[0]; // @[Edges.scala:106:36] wire opdata = io_mem_grant_bits_opcode_0[0]; // @[Edges.scala:106:36] wire grant_had_data_opdata = io_mem_grant_bits_opcode_0[0]; // @[Edges.scala:106:36] wire [7:0] r_beats1 = r_beats1_opdata ? r_beats1_decode : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] r_counter; // @[Edges.scala:229:27] wire [8:0] _r_counter1_T = {1'h0, r_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] r_counter1 = _r_counter1_T[7:0]; // @[Edges.scala:230:28] wire r_1_1 = r_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _r_last_T = r_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _r_last_T_1 = r_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire r_2 = _r_last_T | _r_last_T_1; // @[Edges.scala:232:{25,33,43}] wire refill_done = r_2 & _T_16; // @[Decoupled.scala:51:35] wire [7:0] _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] r_4 = r_beats1 & _r_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _r_counter_T = r_1_1 ? r_beats1 : r_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] refill_address_inc = {r_4, 4'h0}; // @[Edges.scala:234:25, :269:29] wire _sec_rdy_T = ~cmd_requires_second_acquire; // @[Metadata.scala:104:54] wire _sec_rdy_T_1 = ~io_req_is_probe_0; // @[mshrs.scala:36:7, :125:50] wire _sec_rdy_T_2 = _sec_rdy_T & _sec_rdy_T_1; // @[mshrs.scala:125:{18,47,50}] wire _sec_rdy_T_3 = ~(|state); // @[package.scala:16:47] wire _sec_rdy_T_4 = state == 5'hD; // @[package.scala:16:47] wire _sec_rdy_T_5 = state == 5'hE; // @[package.scala:16:47] wire _sec_rdy_T_6 = state == 5'hF; // @[package.scala:16:47] wire _sec_rdy_T_7 = _sec_rdy_T_3 | _sec_rdy_T_4; // @[package.scala:16:47, :81:59] wire _sec_rdy_T_8 = _sec_rdy_T_7 | _sec_rdy_T_5; // @[package.scala:16:47, :81:59] wire _sec_rdy_T_9 = _sec_rdy_T_8 | _sec_rdy_T_6; // @[package.scala:16:47, :81:59] wire _sec_rdy_T_10 = ~_sec_rdy_T_9; // @[package.scala:81:59] wire sec_rdy = _sec_rdy_T_2 & _sec_rdy_T_10; // @[mshrs.scala:125:{47,67}, :126:18] wire _rpq_io_enq_valid_T = io_req_pri_val_0 & io_req_pri_rdy_0; // @[mshrs.scala:36:7, :133:40] wire _rpq_io_enq_valid_T_1 = io_req_sec_val_0 & io_req_sec_rdy_0; // @[mshrs.scala:36:7, :133:78] wire _rpq_io_enq_valid_T_2 = _rpq_io_enq_valid_T | _rpq_io_enq_valid_T_1; // @[mshrs.scala:133:{40,59,78}] wire _rpq_io_enq_valid_T_3 = io_req_uop_mem_cmd_0 == 5'h2; // @[Consts.scala:88:35] wire _rpq_io_enq_valid_T_5 = _rpq_io_enq_valid_T_3 | _rpq_io_enq_valid_T_4; // @[Consts.scala:88:{35,45,52}] wire _rpq_io_enq_valid_T_6 = ~_rpq_io_enq_valid_T_5; // @[Consts.scala:88:45] wire _rpq_io_enq_valid_T_7 = _rpq_io_enq_valid_T_2 & _rpq_io_enq_valid_T_6; // @[mshrs.scala:133:{59,98,101}] reg grantack_valid; // @[mshrs.scala:138:21] reg [3:0] grantack_bits_sink; // @[mshrs.scala:138:21] assign io_mem_finish_bits_sink_0 = grantack_bits_sink; // @[mshrs.scala:36:7, :138:21] reg [1:0] refill_ctr; // @[mshrs.scala:139:24] reg commit_line; // @[mshrs.scala:140:24] reg grant_had_data; // @[mshrs.scala:141:27] reg finish_to_prefetch; // @[mshrs.scala:142:31] reg [1:0] meta_hazard; // @[mshrs.scala:145:28] wire [2:0] _meta_hazard_T = {1'h0, meta_hazard} + 3'h1; // @[mshrs.scala:145:28, :146:59] wire [1:0] _meta_hazard_T_1 = _meta_hazard_T[1:0]; // @[mshrs.scala:146:59] wire _io_probe_rdy_T = meta_hazard == 2'h0; // @[mshrs.scala:145:28, :148:34] wire _io_probe_rdy_T_1 = ~(|state); // @[package.scala:16:47] wire _io_probe_rdy_T_2 = state == 5'h1; // @[package.scala:16:47] wire _io_probe_rdy_T_3 = state == 5'h2; // @[package.scala:16:47] wire _io_probe_rdy_T_4 = state == 5'h3; // @[package.scala:16:47] wire _io_probe_rdy_T_5 = _io_probe_rdy_T_1 | _io_probe_rdy_T_2; // @[package.scala:16:47, :81:59] wire _io_probe_rdy_T_6 = _io_probe_rdy_T_5 | _io_probe_rdy_T_3; // @[package.scala:16:47, :81:59] wire _io_probe_rdy_T_7 = _io_probe_rdy_T_6 | _io_probe_rdy_T_4; // @[package.scala:16:47, :81:59] wire _io_probe_rdy_T_8 = state == 5'h4; // @[mshrs.scala:107:22, :148:129] wire _io_probe_rdy_T_9 = _io_probe_rdy_T_8 & grantack_valid; // @[mshrs.scala:138:21, :148:{129,145}] wire _io_probe_rdy_T_10 = _io_probe_rdy_T_7 | _io_probe_rdy_T_9; // @[package.scala:81:59] assign _io_probe_rdy_T_11 = _io_probe_rdy_T & _io_probe_rdy_T_10; // @[mshrs.scala:148:{34,42,119}] assign io_probe_rdy_0 = _io_probe_rdy_T_11; // @[mshrs.scala:36:7, :148:42] assign _io_idx_valid_T = |state; // @[package.scala:16:47] assign io_idx_valid_0 = _io_idx_valid_T; // @[mshrs.scala:36:7, :149:25] assign _io_tag_valid_T = |state; // @[package.scala:16:47] assign io_tag_valid_0 = _io_tag_valid_T; // @[mshrs.scala:36:7, :150:25] wire _io_way_valid_T = ~(|state); // @[package.scala:16:47] wire _io_way_valid_T_1 = state == 5'h11; // @[package.scala:16:47] wire _io_way_valid_T_2 = _io_way_valid_T | _io_way_valid_T_1; // @[package.scala:16:47, :81:59] assign _io_way_valid_T_3 = ~_io_way_valid_T_2; // @[package.scala:81:59] assign io_way_valid_0 = _io_way_valid_T_3; // @[mshrs.scala:36:7, :151:19] assign _io_req_sec_rdy_T = sec_rdy & _rpq_io_enq_ready; // @[mshrs.scala:125:67, :128:19, :159:37] assign io_req_sec_rdy_0 = _io_req_sec_rdy_T; // @[mshrs.scala:36:7, :159:37] wire [4:0] state_new_state; // @[mshrs.scala:191:29] wire _state_T_1 = ~_state_T; // @[mshrs.scala:194:11] wire _state_T_2 = ~_rpq_io_enq_ready; // @[mshrs.scala:128:19, :194:11] wire [3:0] _GEN_27 = {2'h2, io_req_old_meta_coh_state_0}; // @[Metadata.scala:120:19] wire [3:0] _state_req_needs_wb_r_T_6; // @[Metadata.scala:120:19] assign _state_req_needs_wb_r_T_6 = _GEN_27; // @[Metadata.scala:120:19] wire [3:0] _state_req_needs_wb_r_T_70; // @[Metadata.scala:120:19] assign _state_req_needs_wb_r_T_70 = _GEN_27; // @[Metadata.scala:120:19] wire _state_req_needs_wb_r_T_19 = _state_req_needs_wb_r_T_6 == 4'h8; // @[Misc.scala:56:20] wire [2:0] _state_req_needs_wb_r_T_21 = _state_req_needs_wb_r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_23 = _state_req_needs_wb_r_T_6 == 4'h9; // @[Misc.scala:56:20] wire [2:0] _state_req_needs_wb_r_T_25 = _state_req_needs_wb_r_T_23 ? 3'h2 : _state_req_needs_wb_r_T_21; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_27 = _state_req_needs_wb_r_T_6 == 4'hA; // @[Misc.scala:56:20] wire [2:0] _state_req_needs_wb_r_T_29 = _state_req_needs_wb_r_T_27 ? 3'h1 : _state_req_needs_wb_r_T_25; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_31 = _state_req_needs_wb_r_T_6 == 4'hB; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_32 = _state_req_needs_wb_r_T_31; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_33 = _state_req_needs_wb_r_T_31 ? 3'h1 : _state_req_needs_wb_r_T_29; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_35 = _state_req_needs_wb_r_T_6 == 4'h4; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_36 = ~_state_req_needs_wb_r_T_35 & _state_req_needs_wb_r_T_32; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_37 = _state_req_needs_wb_r_T_35 ? 3'h5 : _state_req_needs_wb_r_T_33; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_39 = _state_req_needs_wb_r_T_6 == 4'h5; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_40 = ~_state_req_needs_wb_r_T_39 & _state_req_needs_wb_r_T_36; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_41 = _state_req_needs_wb_r_T_39 ? 3'h4 : _state_req_needs_wb_r_T_37; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_42 = {1'h0, _state_req_needs_wb_r_T_39}; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_43 = _state_req_needs_wb_r_T_6 == 4'h6; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_44 = ~_state_req_needs_wb_r_T_43 & _state_req_needs_wb_r_T_40; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_45 = _state_req_needs_wb_r_T_43 ? 3'h0 : _state_req_needs_wb_r_T_41; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_46 = _state_req_needs_wb_r_T_43 ? 2'h1 : _state_req_needs_wb_r_T_42; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_47 = _state_req_needs_wb_r_T_6 == 4'h7; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_48 = _state_req_needs_wb_r_T_47 | _state_req_needs_wb_r_T_44; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_49 = _state_req_needs_wb_r_T_47 ? 3'h0 : _state_req_needs_wb_r_T_45; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_50 = _state_req_needs_wb_r_T_47 ? 2'h1 : _state_req_needs_wb_r_T_46; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_51 = _state_req_needs_wb_r_T_6 == 4'h0; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_52 = ~_state_req_needs_wb_r_T_51 & _state_req_needs_wb_r_T_48; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_53 = _state_req_needs_wb_r_T_51 ? 3'h5 : _state_req_needs_wb_r_T_49; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_54 = _state_req_needs_wb_r_T_51 ? 2'h0 : _state_req_needs_wb_r_T_50; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_55 = _state_req_needs_wb_r_T_6 == 4'h1; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_56 = ~_state_req_needs_wb_r_T_55 & _state_req_needs_wb_r_T_52; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_57 = _state_req_needs_wb_r_T_55 ? 3'h4 : _state_req_needs_wb_r_T_53; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_58 = _state_req_needs_wb_r_T_55 ? 2'h1 : _state_req_needs_wb_r_T_54; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_59 = _state_req_needs_wb_r_T_6 == 4'h2; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_60 = ~_state_req_needs_wb_r_T_59 & _state_req_needs_wb_r_T_56; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_61 = _state_req_needs_wb_r_T_59 ? 3'h3 : _state_req_needs_wb_r_T_57; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_62 = _state_req_needs_wb_r_T_59 ? 2'h2 : _state_req_needs_wb_r_T_58; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_63 = _state_req_needs_wb_r_T_6 == 4'h3; // @[Misc.scala:56:20] wire state_req_needs_wb_r_1 = _state_req_needs_wb_r_T_63 | _state_req_needs_wb_r_T_60; // @[Misc.scala:38:9, :56:20] wire [2:0] state_req_needs_wb_r_2 = _state_req_needs_wb_r_T_63 ? 3'h3 : _state_req_needs_wb_r_T_61; // @[Misc.scala:38:36, :56:20] wire [1:0] state_req_needs_wb_r_3 = _state_req_needs_wb_r_T_63 ? 2'h2 : _state_req_needs_wb_r_T_62; // @[Misc.scala:38:63, :56:20] wire [1:0] state_req_needs_wb_meta_state = state_req_needs_wb_r_3; // @[Misc.scala:38:63] wire _state_r_c_cat_T_2 = _state_r_c_cat_T | _state_r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _state_r_c_cat_T_4 = _state_r_c_cat_T_2 | _state_r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _state_r_c_cat_T_9 = _state_r_c_cat_T_5 | _state_r_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_10 = _state_r_c_cat_T_9 | _state_r_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_11 = _state_r_c_cat_T_10 | _state_r_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_17 = _state_r_c_cat_T_12 | _state_r_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_18 = _state_r_c_cat_T_17 | _state_r_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_19 = _state_r_c_cat_T_18 | _state_r_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_20 = _state_r_c_cat_T_19 | _state_r_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_21 = _state_r_c_cat_T_11 | _state_r_c_cat_T_20; // @[package.scala:81:59] wire _state_r_c_cat_T_22 = _state_r_c_cat_T_4 | _state_r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _state_r_c_cat_T_25 = _state_r_c_cat_T_23 | _state_r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _state_r_c_cat_T_27 = _state_r_c_cat_T_25 | _state_r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _state_r_c_cat_T_32 = _state_r_c_cat_T_28 | _state_r_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_33 = _state_r_c_cat_T_32 | _state_r_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_34 = _state_r_c_cat_T_33 | _state_r_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_40 = _state_r_c_cat_T_35 | _state_r_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_41 = _state_r_c_cat_T_40 | _state_r_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_42 = _state_r_c_cat_T_41 | _state_r_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_43 = _state_r_c_cat_T_42 | _state_r_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_44 = _state_r_c_cat_T_34 | _state_r_c_cat_T_43; // @[package.scala:81:59] wire _state_r_c_cat_T_45 = _state_r_c_cat_T_27 | _state_r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _state_r_c_cat_T_47 = _state_r_c_cat_T_45 | _state_r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _state_r_c_cat_T_49 = _state_r_c_cat_T_47 | _state_r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] state_r_c = {_state_r_c_cat_T_22, _state_r_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _state_r_T = {state_r_c, io_req_old_meta_coh_state_0}; // @[Metadata.scala:29:18, :58:19] wire _state_r_T_25 = _state_r_T == 4'hC; // @[Misc.scala:49:20] wire [1:0] _state_r_T_27 = {1'h0, _state_r_T_25}; // @[Misc.scala:35:36, :49:20] wire _state_r_T_28 = _state_r_T == 4'hD; // @[Misc.scala:49:20] wire [1:0] _state_r_T_30 = _state_r_T_28 ? 2'h2 : _state_r_T_27; // @[Misc.scala:35:36, :49:20] wire _state_r_T_31 = _state_r_T == 4'h4; // @[Misc.scala:49:20] wire [1:0] _state_r_T_33 = _state_r_T_31 ? 2'h1 : _state_r_T_30; // @[Misc.scala:35:36, :49:20] wire _state_r_T_34 = _state_r_T == 4'h5; // @[Misc.scala:49:20] wire [1:0] _state_r_T_36 = _state_r_T_34 ? 2'h2 : _state_r_T_33; // @[Misc.scala:35:36, :49:20] wire _state_r_T_37 = _state_r_T == 4'h0; // @[Misc.scala:49:20] wire [1:0] _state_r_T_39 = _state_r_T_37 ? 2'h0 : _state_r_T_36; // @[Misc.scala:35:36, :49:20] wire _state_r_T_40 = _state_r_T == 4'hE; // @[Misc.scala:49:20] wire _state_r_T_41 = _state_r_T_40; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_42 = _state_r_T_40 ? 2'h3 : _state_r_T_39; // @[Misc.scala:35:36, :49:20] wire _state_r_T_43 = &_state_r_T; // @[Misc.scala:49:20] wire _state_r_T_44 = _state_r_T_43 | _state_r_T_41; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_45 = _state_r_T_43 ? 2'h3 : _state_r_T_42; // @[Misc.scala:35:36, :49:20] wire _state_r_T_46 = _state_r_T == 4'h6; // @[Misc.scala:49:20] wire _state_r_T_47 = _state_r_T_46 | _state_r_T_44; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_48 = _state_r_T_46 ? 2'h2 : _state_r_T_45; // @[Misc.scala:35:36, :49:20] wire _state_r_T_49 = _state_r_T == 4'h7; // @[Misc.scala:49:20] wire _state_r_T_50 = _state_r_T_49 | _state_r_T_47; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_51 = _state_r_T_49 ? 2'h3 : _state_r_T_48; // @[Misc.scala:35:36, :49:20] wire _state_r_T_52 = _state_r_T == 4'h1; // @[Misc.scala:49:20] wire _state_r_T_53 = _state_r_T_52 | _state_r_T_50; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_54 = _state_r_T_52 ? 2'h1 : _state_r_T_51; // @[Misc.scala:35:36, :49:20] wire _state_r_T_55 = _state_r_T == 4'h2; // @[Misc.scala:49:20] wire _state_r_T_56 = _state_r_T_55 | _state_r_T_53; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_57 = _state_r_T_55 ? 2'h2 : _state_r_T_54; // @[Misc.scala:35:36, :49:20] wire _state_r_T_58 = _state_r_T == 4'h3; // @[Misc.scala:49:20] wire state_is_hit = _state_r_T_58 | _state_r_T_56; // @[Misc.scala:35:9, :49:20] wire [1:0] state_r_2 = _state_r_T_58 ? 2'h3 : _state_r_T_57; // @[Misc.scala:35:36, :49:20] wire [1:0] state_coh_on_hit_state = state_r_2; // @[Misc.scala:35:36] wire _state_T_5 = _state_T_3 | _state_T_4; // @[Consts.scala:90:{32,42,49}] wire _state_T_7 = _state_T_5 | _state_T_6; // @[Consts.scala:90:{42,59,66}] wire _state_T_12 = _state_T_8 | _state_T_9; // @[package.scala:16:47, :81:59] wire _state_T_13 = _state_T_12 | _state_T_10; // @[package.scala:16:47, :81:59] wire _state_T_14 = _state_T_13 | _state_T_11; // @[package.scala:16:47, :81:59] wire _state_T_20 = _state_T_15 | _state_T_16; // @[package.scala:16:47, :81:59] wire _state_T_21 = _state_T_20 | _state_T_17; // @[package.scala:16:47, :81:59] wire _state_T_22 = _state_T_21 | _state_T_18; // @[package.scala:16:47, :81:59] wire _state_T_23 = _state_T_22 | _state_T_19; // @[package.scala:16:47, :81:59] wire _state_T_24 = _state_T_14 | _state_T_23; // @[package.scala:81:59] wire _state_T_25 = _state_T_7 | _state_T_24; // @[Consts.scala:87:44, :90:{59,76}] wire _state_T_27 = ~_state_T_26; // @[mshrs.scala:201:15] wire _state_T_28 = ~_state_T_25; // @[Consts.scala:90:76] assign state_new_state = io_req_tag_match_0 & state_is_hit ? 5'hC : 5'h1; // @[Misc.scala:35:9] assign io_mem_acquire_valid_0 = (|state) & _io_probe_rdy_T_2; // @[package.scala:16:47] wire [33:0] _GEN_28 = {req_tag, req_idx}; // @[mshrs.scala:110:25, :111:26, :227:28] wire [33:0] _io_mem_acquire_bits_T; // @[mshrs.scala:227:28] assign _io_mem_acquire_bits_T = _GEN_28; // @[mshrs.scala:227:28] wire [33:0] rp_addr_hi; // @[mshrs.scala:261:22] assign rp_addr_hi = _GEN_28; // @[mshrs.scala:227:28, :261:22] wire [33:0] hi; // @[mshrs.scala:266:10] assign hi = _GEN_28; // @[mshrs.scala:227:28, :266:10] wire [33:0] io_replay_bits_addr_hi; // @[mshrs.scala:353:31] assign io_replay_bits_addr_hi = _GEN_28; // @[mshrs.scala:227:28, :353:31] wire [39:0] _io_mem_acquire_bits_T_1 = {_io_mem_acquire_bits_T, 6'h0}; // @[mshrs.scala:227:{28,47}] wire [39:0] _io_mem_acquire_bits_legal_T_1 = _io_mem_acquire_bits_T_1; // @[Parameters.scala:137:31] wire [40:0] _io_mem_acquire_bits_legal_T_2 = {1'h0, _io_mem_acquire_bits_legal_T_1}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_mem_acquire_bits_legal_T_3 = _io_mem_acquire_bits_legal_T_2 & 41'h8C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_mem_acquire_bits_legal_T_4 = _io_mem_acquire_bits_legal_T_3; // @[Parameters.scala:137:46] wire _io_mem_acquire_bits_legal_T_5 = _io_mem_acquire_bits_legal_T_4 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _io_mem_acquire_bits_legal_T_6 = {_io_mem_acquire_bits_T_1[39:17], _io_mem_acquire_bits_T_1[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31] wire [40:0] _io_mem_acquire_bits_legal_T_7 = {1'h0, _io_mem_acquire_bits_legal_T_6}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_mem_acquire_bits_legal_T_8 = _io_mem_acquire_bits_legal_T_7 & 41'h8C011000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_mem_acquire_bits_legal_T_9 = _io_mem_acquire_bits_legal_T_8; // @[Parameters.scala:137:46] wire _io_mem_acquire_bits_legal_T_10 = _io_mem_acquire_bits_legal_T_9 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _io_mem_acquire_bits_legal_T_11 = {_io_mem_acquire_bits_T_1[39:28], _io_mem_acquire_bits_T_1[27:0] ^ 28'hC000000}; // @[Parameters.scala:137:31] wire [40:0] _io_mem_acquire_bits_legal_T_12 = {1'h0, _io_mem_acquire_bits_legal_T_11}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_mem_acquire_bits_legal_T_13 = _io_mem_acquire_bits_legal_T_12 & 41'h8C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_mem_acquire_bits_legal_T_14 = _io_mem_acquire_bits_legal_T_13; // @[Parameters.scala:137:46] wire _io_mem_acquire_bits_legal_T_15 = _io_mem_acquire_bits_legal_T_14 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_mem_acquire_bits_legal_T_16 = _io_mem_acquire_bits_legal_T_5 | _io_mem_acquire_bits_legal_T_10; // @[Parameters.scala:685:42] wire _io_mem_acquire_bits_legal_T_17 = _io_mem_acquire_bits_legal_T_16 | _io_mem_acquire_bits_legal_T_15; // @[Parameters.scala:685:42] wire [39:0] _io_mem_acquire_bits_legal_T_21 = {_io_mem_acquire_bits_T_1[39:28], _io_mem_acquire_bits_T_1[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31] wire [40:0] _io_mem_acquire_bits_legal_T_22 = {1'h0, _io_mem_acquire_bits_legal_T_21}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_mem_acquire_bits_legal_T_23 = _io_mem_acquire_bits_legal_T_22 & 41'h8C010000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_mem_acquire_bits_legal_T_24 = _io_mem_acquire_bits_legal_T_23; // @[Parameters.scala:137:46] wire _io_mem_acquire_bits_legal_T_25 = _io_mem_acquire_bits_legal_T_24 == 41'h0; // @[Parameters.scala:137:{46,59}] assign io_mem_acquire_bits_a_address = _io_mem_acquire_bits_T_1[31:0]; // @[Edges.scala:346:17] wire [39:0] _io_mem_acquire_bits_legal_T_26 = {_io_mem_acquire_bits_T_1[39:32], io_mem_acquire_bits_a_address ^ 32'h80000000}; // @[Edges.scala:346:17] wire [40:0] _io_mem_acquire_bits_legal_T_27 = {1'h0, _io_mem_acquire_bits_legal_T_26}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_mem_acquire_bits_legal_T_28 = _io_mem_acquire_bits_legal_T_27 & 41'h80000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_mem_acquire_bits_legal_T_29 = _io_mem_acquire_bits_legal_T_28; // @[Parameters.scala:137:46] wire _io_mem_acquire_bits_legal_T_30 = _io_mem_acquire_bits_legal_T_29 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_mem_acquire_bits_legal_T_31 = _io_mem_acquire_bits_legal_T_25 | _io_mem_acquire_bits_legal_T_30; // @[Parameters.scala:685:42] wire _io_mem_acquire_bits_legal_T_32 = _io_mem_acquire_bits_legal_T_31; // @[Parameters.scala:684:54, :685:42] wire io_mem_acquire_bits_legal = _io_mem_acquire_bits_legal_T_32; // @[Parameters.scala:684:54, :686:26] assign io_mem_acquire_bits_param_0 = io_mem_acquire_bits_a_param; // @[Edges.scala:346:17] assign io_mem_acquire_bits_address_0 = io_mem_acquire_bits_a_address; // @[Edges.scala:346:17] assign io_mem_acquire_bits_a_param = {1'h0, grow_param}; // @[Misc.scala:35:36] wire io_mem_acquire_bits_a_mask_sub_sub_sub_bit = _io_mem_acquire_bits_T_1[3]; // @[Misc.scala:210:26] wire io_mem_acquire_bits_a_mask_sub_sub_sub_1_2 = io_mem_acquire_bits_a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire io_mem_acquire_bits_a_mask_sub_sub_sub_nbit = ~io_mem_acquire_bits_a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire io_mem_acquire_bits_a_mask_sub_sub_sub_0_2 = io_mem_acquire_bits_a_mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire io_mem_acquire_bits_a_mask_sub_sub_bit = _io_mem_acquire_bits_T_1[2]; // @[Misc.scala:210:26] wire io_mem_acquire_bits_a_mask_sub_sub_nbit = ~io_mem_acquire_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire io_mem_acquire_bits_a_mask_sub_sub_0_2 = io_mem_acquire_bits_a_mask_sub_sub_sub_0_2 & io_mem_acquire_bits_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_sub_sub_acc_T = io_mem_acquire_bits_a_mask_sub_sub_0_2; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_sub_sub_1_2 = io_mem_acquire_bits_a_mask_sub_sub_sub_0_2 & io_mem_acquire_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_sub_sub_acc_T_1 = io_mem_acquire_bits_a_mask_sub_sub_1_2; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_sub_sub_2_2 = io_mem_acquire_bits_a_mask_sub_sub_sub_1_2 & io_mem_acquire_bits_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_sub_sub_acc_T_2 = io_mem_acquire_bits_a_mask_sub_sub_2_2; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_sub_sub_3_2 = io_mem_acquire_bits_a_mask_sub_sub_sub_1_2 & io_mem_acquire_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_sub_sub_acc_T_3 = io_mem_acquire_bits_a_mask_sub_sub_3_2; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_sub_bit = _io_mem_acquire_bits_T_1[1]; // @[Misc.scala:210:26] wire io_mem_acquire_bits_a_mask_sub_nbit = ~io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire io_mem_acquire_bits_a_mask_sub_0_2 = io_mem_acquire_bits_a_mask_sub_sub_0_2 & io_mem_acquire_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire io_mem_acquire_bits_a_mask_sub_1_2 = io_mem_acquire_bits_a_mask_sub_sub_0_2 & io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire io_mem_acquire_bits_a_mask_sub_2_2 = io_mem_acquire_bits_a_mask_sub_sub_1_2 & io_mem_acquire_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire io_mem_acquire_bits_a_mask_sub_3_2 = io_mem_acquire_bits_a_mask_sub_sub_1_2 & io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire io_mem_acquire_bits_a_mask_sub_4_2 = io_mem_acquire_bits_a_mask_sub_sub_2_2 & io_mem_acquire_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire io_mem_acquire_bits_a_mask_sub_5_2 = io_mem_acquire_bits_a_mask_sub_sub_2_2 & io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire io_mem_acquire_bits_a_mask_sub_6_2 = io_mem_acquire_bits_a_mask_sub_sub_3_2 & io_mem_acquire_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire io_mem_acquire_bits_a_mask_sub_7_2 = io_mem_acquire_bits_a_mask_sub_sub_3_2 & io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire io_mem_acquire_bits_a_mask_bit = _io_mem_acquire_bits_T_1[0]; // @[Misc.scala:210:26] wire io_mem_acquire_bits_a_mask_nbit = ~io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire io_mem_acquire_bits_a_mask_eq = io_mem_acquire_bits_a_mask_sub_0_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T = io_mem_acquire_bits_a_mask_eq; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_1 = io_mem_acquire_bits_a_mask_sub_0_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_1 = io_mem_acquire_bits_a_mask_eq_1; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_2 = io_mem_acquire_bits_a_mask_sub_1_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_2 = io_mem_acquire_bits_a_mask_eq_2; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_3 = io_mem_acquire_bits_a_mask_sub_1_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_3 = io_mem_acquire_bits_a_mask_eq_3; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_4 = io_mem_acquire_bits_a_mask_sub_2_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_4 = io_mem_acquire_bits_a_mask_eq_4; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_5 = io_mem_acquire_bits_a_mask_sub_2_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_5 = io_mem_acquire_bits_a_mask_eq_5; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_6 = io_mem_acquire_bits_a_mask_sub_3_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_6 = io_mem_acquire_bits_a_mask_eq_6; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_7 = io_mem_acquire_bits_a_mask_sub_3_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_7 = io_mem_acquire_bits_a_mask_eq_7; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_8 = io_mem_acquire_bits_a_mask_sub_4_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_8 = io_mem_acquire_bits_a_mask_eq_8; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_9 = io_mem_acquire_bits_a_mask_sub_4_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_9 = io_mem_acquire_bits_a_mask_eq_9; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_10 = io_mem_acquire_bits_a_mask_sub_5_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_10 = io_mem_acquire_bits_a_mask_eq_10; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_11 = io_mem_acquire_bits_a_mask_sub_5_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_11 = io_mem_acquire_bits_a_mask_eq_11; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_12 = io_mem_acquire_bits_a_mask_sub_6_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_12 = io_mem_acquire_bits_a_mask_eq_12; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_13 = io_mem_acquire_bits_a_mask_sub_6_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_13 = io_mem_acquire_bits_a_mask_eq_13; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_14 = io_mem_acquire_bits_a_mask_sub_7_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_14 = io_mem_acquire_bits_a_mask_eq_14; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_15 = io_mem_acquire_bits_a_mask_sub_7_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_15 = io_mem_acquire_bits_a_mask_eq_15; // @[Misc.scala:214:27, :215:38] wire _GEN_29 = ~(|state) | _io_probe_rdy_T_2; // @[package.scala:16:47] assign io_lb_write_valid_0 = ~_GEN_29 & _io_probe_rdy_T_3 & opdata & io_mem_grant_valid_0; // @[package.scala:16:47] wire [7:0] _io_lb_write_bits_offset_T = refill_address_inc[11:4]; // @[Edges.scala:269:29] assign io_lb_write_bits_offset_0 = _io_lb_write_bits_offset_T[1:0]; // @[mshrs.scala:36:7, :238:{31,53}] assign io_mem_grant_ready_0 = ~_GEN_29 & _io_probe_rdy_T_3 & (~opdata | io_lb_write_ready_0); // @[package.scala:16:47] wire _grantack_valid_T = io_mem_grant_bits_opcode_0[2]; // @[Edges.scala:71:36] wire _grantack_valid_T_1 = io_mem_grant_bits_opcode_0[1]; // @[Edges.scala:71:52] wire _grantack_valid_T_2 = ~_grantack_valid_T_1; // @[Edges.scala:71:{43,52}] wire _grantack_valid_T_3 = _grantack_valid_T & _grantack_valid_T_2; // @[Edges.scala:71:{36,40,43}] wire [4:0] _state_T_29 = grant_had_data ? 5'h3 : 5'hC; // @[mshrs.scala:141:27, :250:19] wire _drain_load_T = _rpq_io_deq_bits_uop_mem_cmd == 5'h0; // @[package.scala:16:47] wire _drain_load_T_1 = _rpq_io_deq_bits_uop_mem_cmd == 5'h10; // @[package.scala:16:47] wire _GEN_30 = _rpq_io_deq_bits_uop_mem_cmd == 5'h6; // @[package.scala:16:47] wire _drain_load_T_2; // @[package.scala:16:47] assign _drain_load_T_2 = _GEN_30; // @[package.scala:16:47] wire _r_c_cat_T_48; // @[Consts.scala:91:71] assign _r_c_cat_T_48 = _GEN_30; // @[package.scala:16:47] wire _GEN_31 = _rpq_io_deq_bits_uop_mem_cmd == 5'h7; // @[package.scala:16:47] wire _drain_load_T_3; // @[package.scala:16:47] assign _drain_load_T_3 = _GEN_31; // @[package.scala:16:47] wire _drain_load_T_28; // @[Consts.scala:90:66] assign _drain_load_T_28 = _GEN_31; // @[package.scala:16:47] wire _drain_load_T_4 = _drain_load_T | _drain_load_T_1; // @[package.scala:16:47, :81:59] wire _drain_load_T_5 = _drain_load_T_4 | _drain_load_T_2; // @[package.scala:16:47, :81:59] wire _drain_load_T_6 = _drain_load_T_5 | _drain_load_T_3; // @[package.scala:16:47, :81:59] wire _GEN_32 = _rpq_io_deq_bits_uop_mem_cmd == 5'h4; // @[package.scala:16:47] wire _drain_load_T_7; // @[package.scala:16:47] assign _drain_load_T_7 = _GEN_32; // @[package.scala:16:47] wire _drain_load_T_30; // @[package.scala:16:47] assign _drain_load_T_30 = _GEN_32; // @[package.scala:16:47] wire _GEN_33 = _rpq_io_deq_bits_uop_mem_cmd == 5'h9; // @[package.scala:16:47] wire _drain_load_T_8; // @[package.scala:16:47] assign _drain_load_T_8 = _GEN_33; // @[package.scala:16:47] wire _drain_load_T_31; // @[package.scala:16:47] assign _drain_load_T_31 = _GEN_33; // @[package.scala:16:47] wire _GEN_34 = _rpq_io_deq_bits_uop_mem_cmd == 5'hA; // @[package.scala:16:47] wire _drain_load_T_9; // @[package.scala:16:47] assign _drain_load_T_9 = _GEN_34; // @[package.scala:16:47] wire _drain_load_T_32; // @[package.scala:16:47] assign _drain_load_T_32 = _GEN_34; // @[package.scala:16:47] wire _GEN_35 = _rpq_io_deq_bits_uop_mem_cmd == 5'hB; // @[package.scala:16:47] wire _drain_load_T_10; // @[package.scala:16:47] assign _drain_load_T_10 = _GEN_35; // @[package.scala:16:47] wire _drain_load_T_33; // @[package.scala:16:47] assign _drain_load_T_33 = _GEN_35; // @[package.scala:16:47] wire _drain_load_T_11 = _drain_load_T_7 | _drain_load_T_8; // @[package.scala:16:47, :81:59] wire _drain_load_T_12 = _drain_load_T_11 | _drain_load_T_9; // @[package.scala:16:47, :81:59] wire _drain_load_T_13 = _drain_load_T_12 | _drain_load_T_10; // @[package.scala:16:47, :81:59] wire _GEN_36 = _rpq_io_deq_bits_uop_mem_cmd == 5'h8; // @[package.scala:16:47] wire _drain_load_T_14; // @[package.scala:16:47] assign _drain_load_T_14 = _GEN_36; // @[package.scala:16:47] wire _drain_load_T_37; // @[package.scala:16:47] assign _drain_load_T_37 = _GEN_36; // @[package.scala:16:47] wire _GEN_37 = _rpq_io_deq_bits_uop_mem_cmd == 5'hC; // @[package.scala:16:47] wire _drain_load_T_15; // @[package.scala:16:47] assign _drain_load_T_15 = _GEN_37; // @[package.scala:16:47] wire _drain_load_T_38; // @[package.scala:16:47] assign _drain_load_T_38 = _GEN_37; // @[package.scala:16:47] wire _GEN_38 = _rpq_io_deq_bits_uop_mem_cmd == 5'hD; // @[package.scala:16:47] wire _drain_load_T_16; // @[package.scala:16:47] assign _drain_load_T_16 = _GEN_38; // @[package.scala:16:47] wire _drain_load_T_39; // @[package.scala:16:47] assign _drain_load_T_39 = _GEN_38; // @[package.scala:16:47] wire _GEN_39 = _rpq_io_deq_bits_uop_mem_cmd == 5'hE; // @[package.scala:16:47] wire _drain_load_T_17; // @[package.scala:16:47] assign _drain_load_T_17 = _GEN_39; // @[package.scala:16:47] wire _drain_load_T_40; // @[package.scala:16:47] assign _drain_load_T_40 = _GEN_39; // @[package.scala:16:47] wire _GEN_40 = _rpq_io_deq_bits_uop_mem_cmd == 5'hF; // @[package.scala:16:47] wire _drain_load_T_18; // @[package.scala:16:47] assign _drain_load_T_18 = _GEN_40; // @[package.scala:16:47] wire _drain_load_T_41; // @[package.scala:16:47] assign _drain_load_T_41 = _GEN_40; // @[package.scala:16:47] wire _drain_load_T_19 = _drain_load_T_14 | _drain_load_T_15; // @[package.scala:16:47, :81:59] wire _drain_load_T_20 = _drain_load_T_19 | _drain_load_T_16; // @[package.scala:16:47, :81:59] wire _drain_load_T_21 = _drain_load_T_20 | _drain_load_T_17; // @[package.scala:16:47, :81:59] wire _drain_load_T_22 = _drain_load_T_21 | _drain_load_T_18; // @[package.scala:16:47, :81:59] wire _drain_load_T_23 = _drain_load_T_13 | _drain_load_T_22; // @[package.scala:81:59] wire _drain_load_T_24 = _drain_load_T_6 | _drain_load_T_23; // @[package.scala:81:59] wire _drain_load_T_25 = _rpq_io_deq_bits_uop_mem_cmd == 5'h1; // @[Consts.scala:90:32] wire _drain_load_T_26 = _rpq_io_deq_bits_uop_mem_cmd == 5'h11; // @[Consts.scala:90:49] wire _drain_load_T_27 = _drain_load_T_25 | _drain_load_T_26; // @[Consts.scala:90:{32,42,49}] wire _drain_load_T_29 = _drain_load_T_27 | _drain_load_T_28; // @[Consts.scala:90:{42,59,66}] wire _drain_load_T_34 = _drain_load_T_30 | _drain_load_T_31; // @[package.scala:16:47, :81:59] wire _drain_load_T_35 = _drain_load_T_34 | _drain_load_T_32; // @[package.scala:16:47, :81:59] wire _drain_load_T_36 = _drain_load_T_35 | _drain_load_T_33; // @[package.scala:16:47, :81:59] wire _drain_load_T_42 = _drain_load_T_37 | _drain_load_T_38; // @[package.scala:16:47, :81:59] wire _drain_load_T_43 = _drain_load_T_42 | _drain_load_T_39; // @[package.scala:16:47, :81:59] wire _drain_load_T_44 = _drain_load_T_43 | _drain_load_T_40; // @[package.scala:16:47, :81:59] wire _drain_load_T_45 = _drain_load_T_44 | _drain_load_T_41; // @[package.scala:16:47, :81:59] wire _drain_load_T_46 = _drain_load_T_36 | _drain_load_T_45; // @[package.scala:81:59] wire _drain_load_T_47 = _drain_load_T_29 | _drain_load_T_46; // @[Consts.scala:87:44, :90:{59,76}] wire _drain_load_T_48 = ~_drain_load_T_47; // @[Consts.scala:90:76] wire _drain_load_T_49 = _drain_load_T_24 & _drain_load_T_48; // @[Consts.scala:89:68] wire _drain_load_T_50 = _rpq_io_deq_bits_uop_mem_cmd != 5'h6; // @[mshrs.scala:128:19, :259:51] wire drain_load = _drain_load_T_49 & _drain_load_T_50; // @[mshrs.scala:257:59, :258:60, :259:51] wire [5:0] _rp_addr_T = _rpq_io_deq_bits_addr[5:0]; // @[mshrs.scala:128:19, :261:61] wire [39:0] rp_addr = {rp_addr_hi, _rp_addr_T}; // @[mshrs.scala:261:{22,61}] wire word_idx = rp_addr[3]; // @[mshrs.scala:261:22, :262:56] wire [6:0] _data_word_T = {word_idx, 6'h0}; // @[mshrs.scala:262:56, :264:32] wire [127:0] data_word = io_lb_resp_0 >> _data_word_T; // @[mshrs.scala:36:7, :264:{26,32}] wire [1:0] size; // @[AMOALU.scala:11:18] wire _rpq_io_deq_ready_T = io_resp_ready_0 & io_lb_read_ready_0; // @[mshrs.scala:36:7, :270:45] wire _rpq_io_deq_ready_T_1 = _rpq_io_deq_ready_T & drain_load; // @[mshrs.scala:258:60, :270:{45,65}] wire _io_lb_read_valid_T = _rpq_io_deq_valid & drain_load; // @[mshrs.scala:128:19, :258:60, :271:48] wire [35:0] _io_lb_read_bits_offset_T = _rpq_io_deq_bits_addr[39:4]; // @[mshrs.scala:128:19, :273:52] wire _GEN_41 = io_lb_read_ready_0 & io_lb_read_valid_0; // @[Decoupled.scala:51:35] wire _io_resp_valid_T; // @[Decoupled.scala:51:35] assign _io_resp_valid_T = _GEN_41; // @[Decoupled.scala:51:35] wire _io_refill_valid_T; // @[Decoupled.scala:51:35] assign _io_refill_valid_T = _GEN_41; // @[Decoupled.scala:51:35] wire _io_resp_valid_T_1 = _rpq_io_deq_valid & _io_resp_valid_T; // @[Decoupled.scala:51:35] wire _io_resp_valid_T_2 = _io_resp_valid_T_1 & drain_load; // @[mshrs.scala:258:60, :275:{43,62}] wire _GEN_42 = ~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3; // @[package.scala:16:47] assign io_resp_valid_0 = ~_GEN_42 & _io_probe_rdy_T_4 & _io_resp_valid_T_2; // @[package.scala:16:47] wire _io_resp_bits_data_shifted_T = _rpq_io_deq_bits_addr[2]; // @[AMOALU.scala:42:29] wire [31:0] _io_resp_bits_data_shifted_T_1 = data_word[63:32]; // @[AMOALU.scala:42:37] wire [31:0] _io_resp_bits_data_T_5 = data_word[63:32]; // @[AMOALU.scala:42:37, :45:94] wire [31:0] _io_resp_bits_data_shifted_T_2 = data_word[31:0]; // @[AMOALU.scala:42:55] wire [31:0] io_resp_bits_data_shifted = _io_resp_bits_data_shifted_T ? _io_resp_bits_data_shifted_T_1 : _io_resp_bits_data_shifted_T_2; // @[AMOALU.scala:42:{24,29,37,55}] wire [31:0] io_resp_bits_data_zeroed = io_resp_bits_data_shifted; // @[AMOALU.scala:42:24, :44:23] wire _io_resp_bits_data_T = size == 2'h2; // @[AMOALU.scala:11:18, :45:26] wire _io_resp_bits_data_T_1 = _io_resp_bits_data_T; // @[AMOALU.scala:45:{26,34}] wire _io_resp_bits_data_T_2 = io_resp_bits_data_zeroed[31]; // @[AMOALU.scala:44:23, :45:81] wire _io_resp_bits_data_T_3 = _rpq_io_deq_bits_uop_mem_signed & _io_resp_bits_data_T_2; // @[AMOALU.scala:45:{72,81}] wire [31:0] _io_resp_bits_data_T_4 = {32{_io_resp_bits_data_T_3}}; // @[AMOALU.scala:45:{49,72}] wire [31:0] _io_resp_bits_data_T_6 = _io_resp_bits_data_T_1 ? _io_resp_bits_data_T_4 : _io_resp_bits_data_T_5; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _io_resp_bits_data_T_7 = {_io_resp_bits_data_T_6, io_resp_bits_data_zeroed}; // @[AMOALU.scala:44:23, :45:{16,20}] wire _io_resp_bits_data_shifted_T_3 = _rpq_io_deq_bits_addr[1]; // @[AMOALU.scala:42:29] wire [15:0] _io_resp_bits_data_shifted_T_4 = _io_resp_bits_data_T_7[31:16]; // @[AMOALU.scala:42:37, :45:16] wire [15:0] _io_resp_bits_data_shifted_T_5 = _io_resp_bits_data_T_7[15:0]; // @[AMOALU.scala:42:55, :45:16] wire [15:0] io_resp_bits_data_shifted_1 = _io_resp_bits_data_shifted_T_3 ? _io_resp_bits_data_shifted_T_4 : _io_resp_bits_data_shifted_T_5; // @[AMOALU.scala:42:{24,29,37,55}] wire [15:0] io_resp_bits_data_zeroed_1 = io_resp_bits_data_shifted_1; // @[AMOALU.scala:42:24, :44:23] wire _io_resp_bits_data_T_8 = size == 2'h1; // @[AMOALU.scala:11:18, :45:26] wire _io_resp_bits_data_T_9 = _io_resp_bits_data_T_8; // @[AMOALU.scala:45:{26,34}] wire _io_resp_bits_data_T_10 = io_resp_bits_data_zeroed_1[15]; // @[AMOALU.scala:44:23, :45:81] wire _io_resp_bits_data_T_11 = _rpq_io_deq_bits_uop_mem_signed & _io_resp_bits_data_T_10; // @[AMOALU.scala:45:{72,81}] wire [47:0] _io_resp_bits_data_T_12 = {48{_io_resp_bits_data_T_11}}; // @[AMOALU.scala:45:{49,72}] wire [47:0] _io_resp_bits_data_T_13 = _io_resp_bits_data_T_7[63:16]; // @[AMOALU.scala:45:{16,94}] wire [47:0] _io_resp_bits_data_T_14 = _io_resp_bits_data_T_9 ? _io_resp_bits_data_T_12 : _io_resp_bits_data_T_13; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _io_resp_bits_data_T_15 = {_io_resp_bits_data_T_14, io_resp_bits_data_zeroed_1}; // @[AMOALU.scala:44:23, :45:{16,20}] wire _io_resp_bits_data_shifted_T_6 = _rpq_io_deq_bits_addr[0]; // @[AMOALU.scala:42:29] wire [7:0] _io_resp_bits_data_shifted_T_7 = _io_resp_bits_data_T_15[15:8]; // @[AMOALU.scala:42:37, :45:16] wire [7:0] _io_resp_bits_data_shifted_T_8 = _io_resp_bits_data_T_15[7:0]; // @[AMOALU.scala:42:55, :45:16] wire [7:0] io_resp_bits_data_shifted_2 = _io_resp_bits_data_shifted_T_6 ? _io_resp_bits_data_shifted_T_7 : _io_resp_bits_data_shifted_T_8; // @[AMOALU.scala:42:{24,29,37,55}] wire [7:0] io_resp_bits_data_zeroed_2 = io_resp_bits_data_shifted_2; // @[AMOALU.scala:42:24, :44:23] wire _io_resp_bits_data_T_16 = size == 2'h0; // @[AMOALU.scala:11:18, :45:26] wire _io_resp_bits_data_T_17 = _io_resp_bits_data_T_16; // @[AMOALU.scala:45:{26,34}] wire _io_resp_bits_data_T_18 = io_resp_bits_data_zeroed_2[7]; // @[AMOALU.scala:44:23, :45:81] wire _io_resp_bits_data_T_19 = _rpq_io_deq_bits_uop_mem_signed & _io_resp_bits_data_T_18; // @[AMOALU.scala:45:{72,81}] wire [55:0] _io_resp_bits_data_T_20 = {56{_io_resp_bits_data_T_19}}; // @[AMOALU.scala:45:{49,72}] wire [55:0] _io_resp_bits_data_T_21 = _io_resp_bits_data_T_15[63:8]; // @[AMOALU.scala:45:{16,94}] wire [55:0] _io_resp_bits_data_T_22 = _io_resp_bits_data_T_17 ? _io_resp_bits_data_T_20 : _io_resp_bits_data_T_21; // @[AMOALU.scala:45:{20,34,49,94}] assign _io_resp_bits_data_T_23 = {_io_resp_bits_data_T_22, io_resp_bits_data_zeroed_2}; // @[AMOALU.scala:44:23, :45:{16,20}] assign io_resp_bits_data_0 = _io_resp_bits_data_T_23; // @[AMOALU.scala:45:16] wire _T_26 = rpq_io_deq_ready & _rpq_io_deq_valid; // @[Decoupled.scala:51:35] wire _T_28 = _rpq_io_empty & ~commit_line; // @[mshrs.scala:128:19, :140:24, :282:{31,34}] wire _T_33 = _rpq_io_empty | _rpq_io_deq_valid & ~drain_load; // @[mshrs.scala:128:19, :258:60, :288:{31,52,55}] assign io_commit_val_0 = ~_GEN_42 & _io_probe_rdy_T_4 & ~(_T_26 | _T_28) & _T_33; // @[Decoupled.scala:51:35] wire _io_meta_read_valid_T = ~io_prober_state_valid_0; // @[mshrs.scala:36:7, :295:27] wire _io_meta_read_valid_T_1 = ~grantack_valid; // @[mshrs.scala:138:21, :295:53] wire _io_meta_read_valid_T_2 = _io_meta_read_valid_T | _io_meta_read_valid_T_1; // @[mshrs.scala:295:{27,50,53}] wire [5:0] _io_meta_read_valid_T_3 = io_prober_state_bits_0[11:6]; // @[mshrs.scala:36:7, :295:93] wire _io_meta_read_valid_T_4 = _io_meta_read_valid_T_3 != req_idx; // @[mshrs.scala:110:25, :295:{93,120}] wire _io_meta_read_valid_T_5 = _io_meta_read_valid_T_2 | _io_meta_read_valid_T_4; // @[mshrs.scala:295:{50,69,120}] assign io_meta_read_valid_0 = ~(~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _io_probe_rdy_T_4) & _io_probe_rdy_T_8 & _io_meta_read_valid_T_5; // @[package.scala:16:47] assign io_meta_write_bits_data_tag_0 = req_tag[19:0]; // @[mshrs.scala:36:7, :111:26, :297:27] assign io_meta_read_bits_tag_0 = req_tag[19:0]; // @[mshrs.scala:36:7, :111:26, :297:27] wire _T_36 = state == 5'h5; // @[mshrs.scala:107:22, :302:22] wire _T_37 = state == 5'h6; // @[mshrs.scala:107:22, :304:22] wire [3:0] _needs_wb_r_T_6 = {2'h2, io_meta_resp_bits_coh_state_0}; // @[Metadata.scala:120:19] wire _needs_wb_r_T_19 = _needs_wb_r_T_6 == 4'h8; // @[Misc.scala:56:20] wire [2:0] _needs_wb_r_T_21 = _needs_wb_r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_23 = _needs_wb_r_T_6 == 4'h9; // @[Misc.scala:56:20] wire [2:0] _needs_wb_r_T_25 = _needs_wb_r_T_23 ? 3'h2 : _needs_wb_r_T_21; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_27 = _needs_wb_r_T_6 == 4'hA; // @[Misc.scala:56:20] wire [2:0] _needs_wb_r_T_29 = _needs_wb_r_T_27 ? 3'h1 : _needs_wb_r_T_25; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_31 = _needs_wb_r_T_6 == 4'hB; // @[Misc.scala:56:20] wire _needs_wb_r_T_32 = _needs_wb_r_T_31; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_33 = _needs_wb_r_T_31 ? 3'h1 : _needs_wb_r_T_29; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_35 = _needs_wb_r_T_6 == 4'h4; // @[Misc.scala:56:20] wire _needs_wb_r_T_36 = ~_needs_wb_r_T_35 & _needs_wb_r_T_32; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_37 = _needs_wb_r_T_35 ? 3'h5 : _needs_wb_r_T_33; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_39 = _needs_wb_r_T_6 == 4'h5; // @[Misc.scala:56:20] wire _needs_wb_r_T_40 = ~_needs_wb_r_T_39 & _needs_wb_r_T_36; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_41 = _needs_wb_r_T_39 ? 3'h4 : _needs_wb_r_T_37; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_42 = {1'h0, _needs_wb_r_T_39}; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_43 = _needs_wb_r_T_6 == 4'h6; // @[Misc.scala:56:20] wire _needs_wb_r_T_44 = ~_needs_wb_r_T_43 & _needs_wb_r_T_40; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_45 = _needs_wb_r_T_43 ? 3'h0 : _needs_wb_r_T_41; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_46 = _needs_wb_r_T_43 ? 2'h1 : _needs_wb_r_T_42; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_47 = _needs_wb_r_T_6 == 4'h7; // @[Misc.scala:56:20] wire _needs_wb_r_T_48 = _needs_wb_r_T_47 | _needs_wb_r_T_44; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_49 = _needs_wb_r_T_47 ? 3'h0 : _needs_wb_r_T_45; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_50 = _needs_wb_r_T_47 ? 2'h1 : _needs_wb_r_T_46; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_51 = _needs_wb_r_T_6 == 4'h0; // @[Misc.scala:56:20] wire _needs_wb_r_T_52 = ~_needs_wb_r_T_51 & _needs_wb_r_T_48; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_53 = _needs_wb_r_T_51 ? 3'h5 : _needs_wb_r_T_49; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_54 = _needs_wb_r_T_51 ? 2'h0 : _needs_wb_r_T_50; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_55 = _needs_wb_r_T_6 == 4'h1; // @[Misc.scala:56:20] wire _needs_wb_r_T_56 = ~_needs_wb_r_T_55 & _needs_wb_r_T_52; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_57 = _needs_wb_r_T_55 ? 3'h4 : _needs_wb_r_T_53; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_58 = _needs_wb_r_T_55 ? 2'h1 : _needs_wb_r_T_54; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_59 = _needs_wb_r_T_6 == 4'h2; // @[Misc.scala:56:20] wire _needs_wb_r_T_60 = ~_needs_wb_r_T_59 & _needs_wb_r_T_56; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_61 = _needs_wb_r_T_59 ? 3'h3 : _needs_wb_r_T_57; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_62 = _needs_wb_r_T_59 ? 2'h2 : _needs_wb_r_T_58; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_63 = _needs_wb_r_T_6 == 4'h3; // @[Misc.scala:56:20] wire needs_wb = _needs_wb_r_T_63 | _needs_wb_r_T_60; // @[Misc.scala:38:9, :56:20] wire [2:0] needs_wb_r_2 = _needs_wb_r_T_63 ? 3'h3 : _needs_wb_r_T_61; // @[Misc.scala:38:36, :56:20] wire [1:0] needs_wb_r_3 = _needs_wb_r_T_63 ? 2'h2 : _needs_wb_r_T_62; // @[Misc.scala:38:63, :56:20] wire [1:0] needs_wb_meta_state = needs_wb_r_3; // @[Misc.scala:38:63] wire _state_T_30 = ~io_meta_resp_valid_0; // @[mshrs.scala:36:7, :306:18] wire [4:0] _state_T_31 = needs_wb ? 5'h7 : 5'hB; // @[Misc.scala:38:9] wire [4:0] _state_T_32 = _state_T_30 ? 5'h4 : _state_T_31; // @[mshrs.scala:306:{17,18}, :307:17] wire _T_38 = state == 5'h7; // @[mshrs.scala:107:22, :308:22] wire _T_40 = state == 5'h9; // @[mshrs.scala:107:22, :318:22] assign io_wb_req_valid_0 = ~(~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _io_probe_rdy_T_4 | _io_probe_rdy_T_8 | _T_36 | _T_37 | _T_38) & _T_40; // @[package.scala:16:47] wire _T_42 = state == 5'hA; // @[mshrs.scala:107:22, :330:22] wire _T_43 = state == 5'hB; // @[mshrs.scala:107:22, :334:22] wire _GEN_43 = _io_probe_rdy_T_8 | _T_36 | _T_37 | _T_38 | _T_40 | _T_42; // @[mshrs.scala:148:129, :179:26, :294:39, :302:{22,41}, :304:{22,41}, :308:{22,40}, :318:{22,36}, :330:{22,37}, :334:41] assign io_lb_read_valid_0 = ~_GEN_42 & (_io_probe_rdy_T_4 ? _io_lb_read_valid_T : ~_GEN_43 & _T_43); // @[package.scala:16:47] assign io_lb_read_bits_offset_0 = _io_probe_rdy_T_4 ? _io_lb_read_bits_offset_T[1:0] : refill_ctr; // @[package.scala:16:47] wire _GEN_44 = _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _io_probe_rdy_T_4 | _GEN_43; // @[package.scala:16:47] assign io_refill_valid_0 = ~(~(|state) | _GEN_44) & _T_43 & _io_refill_valid_T; // @[Decoupled.scala:51:35] wire [5:0] _io_refill_bits_addr_T = {refill_ctr, 4'h0}; // @[mshrs.scala:139:24, :340:59] wire [39:0] _io_refill_bits_addr_T_1 = {req_block_addr[39:6], req_block_addr[5:0] | _io_refill_bits_addr_T}; // @[mshrs.scala:112:51, :340:{45,59}] assign io_refill_bits_addr_0 = _io_refill_bits_addr_T_1[11:0]; // @[mshrs.scala:36:7, :340:{27,45}] wire [2:0] _refill_ctr_T = {1'h0, refill_ctr} + 3'h1; // @[mshrs.scala:139:24, :345:32] wire [1:0] _refill_ctr_T_1 = _refill_ctr_T[1:0]; // @[mshrs.scala:345:32] wire _T_46 = state == 5'hC; // @[mshrs.scala:107:22, :350:22] wire _GEN_45 = _io_probe_rdy_T_8 | _T_36 | _T_37 | _T_38 | _T_40 | _T_42 | _T_43; // @[mshrs.scala:148:129, :164:26, :294:39, :302:{22,41}, :304:{22,41}, :308:{22,40}, :318:{22,36}, :330:{22,37}, :334:{22,41}, :350:39] wire _GEN_46 = _io_probe_rdy_T_4 | _GEN_45; // @[package.scala:16:47] assign io_replay_valid_0 = ~(~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _GEN_46) & _T_46 & _rpq_io_deq_valid; // @[package.scala:16:47] assign rpq_io_deq_ready = ~_GEN_42 & (_io_probe_rdy_T_4 ? _rpq_io_deq_ready_T_1 : ~_GEN_45 & _T_46 & io_replay_ready_0); // @[package.scala:16:47] wire [5:0] _io_replay_bits_addr_T = _rpq_io_deq_bits_addr[5:0]; // @[mshrs.scala:128:19, :353:70] assign _io_replay_bits_addr_T_1 = {io_replay_bits_addr_hi, _io_replay_bits_addr_T}; // @[mshrs.scala:353:{31,70}] assign io_replay_bits_addr_0 = _io_replay_bits_addr_T_1; // @[mshrs.scala:36:7, :353:31] wire _T_48 = _rpq_io_deq_bits_uop_mem_cmd == 5'h1; // @[Consts.scala:90:32] wire _r_c_cat_T; // @[Consts.scala:90:32] assign _r_c_cat_T = _T_48; // @[Consts.scala:90:32] wire _r_c_cat_T_23; // @[Consts.scala:90:32] assign _r_c_cat_T_23 = _T_48; // @[Consts.scala:90:32] wire _T_49 = _rpq_io_deq_bits_uop_mem_cmd == 5'h11; // @[Consts.scala:90:49] wire _r_c_cat_T_1; // @[Consts.scala:90:49] assign _r_c_cat_T_1 = _T_49; // @[Consts.scala:90:49] wire _r_c_cat_T_24; // @[Consts.scala:90:49] assign _r_c_cat_T_24 = _T_49; // @[Consts.scala:90:49] wire _T_51 = _rpq_io_deq_bits_uop_mem_cmd == 5'h7; // @[Consts.scala:90:66] wire _r_c_cat_T_3; // @[Consts.scala:90:66] assign _r_c_cat_T_3 = _T_51; // @[Consts.scala:90:66] wire _r_c_cat_T_26; // @[Consts.scala:90:66] assign _r_c_cat_T_26 = _T_51; // @[Consts.scala:90:66] wire _T_53 = _rpq_io_deq_bits_uop_mem_cmd == 5'h4; // @[package.scala:16:47] wire _r_c_cat_T_5; // @[package.scala:16:47] assign _r_c_cat_T_5 = _T_53; // @[package.scala:16:47] wire _r_c_cat_T_28; // @[package.scala:16:47] assign _r_c_cat_T_28 = _T_53; // @[package.scala:16:47] wire _T_54 = _rpq_io_deq_bits_uop_mem_cmd == 5'h9; // @[package.scala:16:47] wire _r_c_cat_T_6; // @[package.scala:16:47] assign _r_c_cat_T_6 = _T_54; // @[package.scala:16:47] wire _r_c_cat_T_29; // @[package.scala:16:47] assign _r_c_cat_T_29 = _T_54; // @[package.scala:16:47] wire _T_55 = _rpq_io_deq_bits_uop_mem_cmd == 5'hA; // @[package.scala:16:47] wire _r_c_cat_T_7; // @[package.scala:16:47] assign _r_c_cat_T_7 = _T_55; // @[package.scala:16:47] wire _r_c_cat_T_30; // @[package.scala:16:47] assign _r_c_cat_T_30 = _T_55; // @[package.scala:16:47] wire _T_56 = _rpq_io_deq_bits_uop_mem_cmd == 5'hB; // @[package.scala:16:47] wire _r_c_cat_T_8; // @[package.scala:16:47] assign _r_c_cat_T_8 = _T_56; // @[package.scala:16:47] wire _r_c_cat_T_31; // @[package.scala:16:47] assign _r_c_cat_T_31 = _T_56; // @[package.scala:16:47] wire _T_60 = _rpq_io_deq_bits_uop_mem_cmd == 5'h8; // @[package.scala:16:47] wire _r_c_cat_T_12; // @[package.scala:16:47] assign _r_c_cat_T_12 = _T_60; // @[package.scala:16:47] wire _r_c_cat_T_35; // @[package.scala:16:47] assign _r_c_cat_T_35 = _T_60; // @[package.scala:16:47] wire _T_61 = _rpq_io_deq_bits_uop_mem_cmd == 5'hC; // @[package.scala:16:47] wire _r_c_cat_T_13; // @[package.scala:16:47] assign _r_c_cat_T_13 = _T_61; // @[package.scala:16:47] wire _r_c_cat_T_36; // @[package.scala:16:47] assign _r_c_cat_T_36 = _T_61; // @[package.scala:16:47] wire _T_62 = _rpq_io_deq_bits_uop_mem_cmd == 5'hD; // @[package.scala:16:47] wire _r_c_cat_T_14; // @[package.scala:16:47] assign _r_c_cat_T_14 = _T_62; // @[package.scala:16:47] wire _r_c_cat_T_37; // @[package.scala:16:47] assign _r_c_cat_T_37 = _T_62; // @[package.scala:16:47] wire _T_63 = _rpq_io_deq_bits_uop_mem_cmd == 5'hE; // @[package.scala:16:47] wire _r_c_cat_T_15; // @[package.scala:16:47] assign _r_c_cat_T_15 = _T_63; // @[package.scala:16:47] wire _r_c_cat_T_38; // @[package.scala:16:47] assign _r_c_cat_T_38 = _T_63; // @[package.scala:16:47] wire _T_64 = _rpq_io_deq_bits_uop_mem_cmd == 5'hF; // @[package.scala:16:47] wire _r_c_cat_T_16; // @[package.scala:16:47] assign _r_c_cat_T_16 = _T_64; // @[package.scala:16:47] wire _r_c_cat_T_39; // @[package.scala:16:47] assign _r_c_cat_T_39 = _T_64; // @[package.scala:16:47] wire _T_71 = io_replay_ready_0 & io_replay_valid_0 & (_T_48 | _T_49 | _T_51 | _T_53 | _T_54 | _T_55 | _T_56 | _T_60 | _T_61 | _T_62 | _T_63 | _T_64); // @[Decoupled.scala:51:35] wire _r_c_cat_T_2 = _r_c_cat_T | _r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _r_c_cat_T_4 = _r_c_cat_T_2 | _r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _r_c_cat_T_9 = _r_c_cat_T_5 | _r_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_10 = _r_c_cat_T_9 | _r_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_11 = _r_c_cat_T_10 | _r_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_17 = _r_c_cat_T_12 | _r_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_18 = _r_c_cat_T_17 | _r_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_19 = _r_c_cat_T_18 | _r_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_20 = _r_c_cat_T_19 | _r_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_21 = _r_c_cat_T_11 | _r_c_cat_T_20; // @[package.scala:81:59] wire _r_c_cat_T_22 = _r_c_cat_T_4 | _r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _r_c_cat_T_25 = _r_c_cat_T_23 | _r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _r_c_cat_T_27 = _r_c_cat_T_25 | _r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _r_c_cat_T_32 = _r_c_cat_T_28 | _r_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_33 = _r_c_cat_T_32 | _r_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_34 = _r_c_cat_T_33 | _r_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_40 = _r_c_cat_T_35 | _r_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_41 = _r_c_cat_T_40 | _r_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_42 = _r_c_cat_T_41 | _r_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_43 = _r_c_cat_T_42 | _r_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_44 = _r_c_cat_T_34 | _r_c_cat_T_43; // @[package.scala:81:59] wire _r_c_cat_T_45 = _r_c_cat_T_27 | _r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _r_c_cat_T_46 = _rpq_io_deq_bits_uop_mem_cmd == 5'h3; // @[Consts.scala:91:54] wire _r_c_cat_T_47 = _r_c_cat_T_45 | _r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _r_c_cat_T_49 = _r_c_cat_T_47 | _r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] r_c = {_r_c_cat_T_22, _r_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _r_T_64 = {r_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19] wire _r_T_89 = _r_T_64 == 4'hC; // @[Misc.scala:49:20] wire [1:0] _r_T_91 = {1'h0, _r_T_89}; // @[Misc.scala:35:36, :49:20] wire _r_T_92 = _r_T_64 == 4'hD; // @[Misc.scala:49:20] wire [1:0] _r_T_94 = _r_T_92 ? 2'h2 : _r_T_91; // @[Misc.scala:35:36, :49:20] wire _r_T_95 = _r_T_64 == 4'h4; // @[Misc.scala:49:20] wire [1:0] _r_T_97 = _r_T_95 ? 2'h1 : _r_T_94; // @[Misc.scala:35:36, :49:20] wire _r_T_98 = _r_T_64 == 4'h5; // @[Misc.scala:49:20] wire [1:0] _r_T_100 = _r_T_98 ? 2'h2 : _r_T_97; // @[Misc.scala:35:36, :49:20] wire _r_T_101 = _r_T_64 == 4'h0; // @[Misc.scala:49:20] wire [1:0] _r_T_103 = _r_T_101 ? 2'h0 : _r_T_100; // @[Misc.scala:35:36, :49:20] wire _r_T_104 = _r_T_64 == 4'hE; // @[Misc.scala:49:20] wire _r_T_105 = _r_T_104; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_106 = _r_T_104 ? 2'h3 : _r_T_103; // @[Misc.scala:35:36, :49:20] wire _r_T_107 = &_r_T_64; // @[Misc.scala:49:20] wire _r_T_108 = _r_T_107 | _r_T_105; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_109 = _r_T_107 ? 2'h3 : _r_T_106; // @[Misc.scala:35:36, :49:20] wire _r_T_110 = _r_T_64 == 4'h6; // @[Misc.scala:49:20] wire _r_T_111 = _r_T_110 | _r_T_108; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_112 = _r_T_110 ? 2'h2 : _r_T_109; // @[Misc.scala:35:36, :49:20] wire _r_T_113 = _r_T_64 == 4'h7; // @[Misc.scala:49:20] wire _r_T_114 = _r_T_113 | _r_T_111; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_115 = _r_T_113 ? 2'h3 : _r_T_112; // @[Misc.scala:35:36, :49:20] wire _r_T_116 = _r_T_64 == 4'h1; // @[Misc.scala:49:20] wire _r_T_117 = _r_T_116 | _r_T_114; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_118 = _r_T_116 ? 2'h1 : _r_T_115; // @[Misc.scala:35:36, :49:20] wire _r_T_119 = _r_T_64 == 4'h2; // @[Misc.scala:49:20] wire _r_T_120 = _r_T_119 | _r_T_117; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_121 = _r_T_119 ? 2'h2 : _r_T_118; // @[Misc.scala:35:36, :49:20] wire _r_T_122 = _r_T_64 == 4'h3; // @[Misc.scala:49:20] wire is_hit = _r_T_122 | _r_T_120; // @[Misc.scala:35:9, :49:20] wire [1:0] r_2_1 = _r_T_122 ? 2'h3 : _r_T_121; // @[Misc.scala:35:36, :49:20] wire [1:0] coh_on_hit_state = r_2_1; // @[Misc.scala:35:36] wire _GEN_47 = _T_40 | _T_42 | _T_43 | _T_46; // @[mshrs.scala:156:26, :318:{22,36}, :330:{22,37}, :334:{22,41}, :350:{22,39}, :363:44] assign io_meta_write_valid_0 = ~(~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _io_probe_rdy_T_4 | _io_probe_rdy_T_8 | _T_36 | _T_37) & (_T_38 | ~_GEN_47 & _sec_rdy_T_4); // @[package.scala:16:47] assign io_meta_write_bits_data_coh_state_0 = _T_38 ? coh_on_clear_state : new_coh_state; // @[Metadata.scala:160:20] wire _GEN_48 = _io_probe_rdy_T_4 | _io_probe_rdy_T_8 | _T_36 | _T_37 | _T_38 | _T_40 | _T_42 | _T_43 | _T_46 | _sec_rdy_T_4; // @[package.scala:16:47] assign io_mem_finish_valid_0 = ~(~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _GEN_48) & _sec_rdy_T_5 & grantack_valid; // @[package.scala:16:47] wire [4:0] _state_T_33 = finish_to_prefetch ? 5'h11 : 5'h0; // @[mshrs.scala:142:31, :381:17] wire _GEN_49 = _sec_rdy_T_4 | _sec_rdy_T_5 | _sec_rdy_T_6; // @[package.scala:16:47] wire _GEN_50 = _T_46 | _GEN_49; // @[mshrs.scala:158:26, :350:{22,39}, :363:44, :373:42, :380:42, :382:38] wire _GEN_51 = _io_probe_rdy_T_4 | _io_probe_rdy_T_8 | _T_36 | _T_37 | _T_38 | _T_40 | _T_42 | _T_43 | _GEN_50; // @[package.scala:16:47] wire _GEN_52 = _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _GEN_51; // @[package.scala:16:47] assign io_req_pri_rdy_0 = ~(|state) | ~_GEN_52 & _io_way_valid_T_1; // @[package.scala:16:47] wire _T_87 = io_req_sec_val_0 & ~io_req_sec_rdy_0 | io_clear_prefetch_0; // @[mshrs.scala:36:7, :384:{27,30,47}] wire _r_c_cat_T_52 = _r_c_cat_T_50 | _r_c_cat_T_51; // @[Consts.scala:90:{32,42,49}] wire _r_c_cat_T_54 = _r_c_cat_T_52 | _r_c_cat_T_53; // @[Consts.scala:90:{42,59,66}] wire _r_c_cat_T_59 = _r_c_cat_T_55 | _r_c_cat_T_56; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_60 = _r_c_cat_T_59 | _r_c_cat_T_57; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_61 = _r_c_cat_T_60 | _r_c_cat_T_58; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_67 = _r_c_cat_T_62 | _r_c_cat_T_63; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_68 = _r_c_cat_T_67 | _r_c_cat_T_64; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_69 = _r_c_cat_T_68 | _r_c_cat_T_65; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_70 = _r_c_cat_T_69 | _r_c_cat_T_66; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_71 = _r_c_cat_T_61 | _r_c_cat_T_70; // @[package.scala:81:59] wire _r_c_cat_T_72 = _r_c_cat_T_54 | _r_c_cat_T_71; // @[Consts.scala:87:44, :90:{59,76}] wire _r_c_cat_T_75 = _r_c_cat_T_73 | _r_c_cat_T_74; // @[Consts.scala:90:{32,42,49}] wire _r_c_cat_T_77 = _r_c_cat_T_75 | _r_c_cat_T_76; // @[Consts.scala:90:{42,59,66}] wire _r_c_cat_T_82 = _r_c_cat_T_78 | _r_c_cat_T_79; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_83 = _r_c_cat_T_82 | _r_c_cat_T_80; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_84 = _r_c_cat_T_83 | _r_c_cat_T_81; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_90 = _r_c_cat_T_85 | _r_c_cat_T_86; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_91 = _r_c_cat_T_90 | _r_c_cat_T_87; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_92 = _r_c_cat_T_91 | _r_c_cat_T_88; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_93 = _r_c_cat_T_92 | _r_c_cat_T_89; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_94 = _r_c_cat_T_84 | _r_c_cat_T_93; // @[package.scala:81:59] wire _r_c_cat_T_95 = _r_c_cat_T_77 | _r_c_cat_T_94; // @[Consts.scala:87:44, :90:{59,76}] wire _r_c_cat_T_97 = _r_c_cat_T_95 | _r_c_cat_T_96; // @[Consts.scala:90:76, :91:{47,54}] wire _r_c_cat_T_99 = _r_c_cat_T_97 | _r_c_cat_T_98; // @[Consts.scala:91:{47,64,71}] wire [1:0] r_c_1 = {_r_c_cat_T_72, _r_c_cat_T_99}; // @[Metadata.scala:29:18] wire [3:0] _r_T_123 = {r_c_1, new_coh_state}; // @[Metadata.scala:29:18, :58:19] wire _r_T_148 = _r_T_123 == 4'hC; // @[Misc.scala:49:20] wire [1:0] _r_T_150 = {1'h0, _r_T_148}; // @[Misc.scala:35:36, :49:20] wire _r_T_151 = _r_T_123 == 4'hD; // @[Misc.scala:49:20] wire [1:0] _r_T_153 = _r_T_151 ? 2'h2 : _r_T_150; // @[Misc.scala:35:36, :49:20] wire _r_T_154 = _r_T_123 == 4'h4; // @[Misc.scala:49:20] wire [1:0] _r_T_156 = _r_T_154 ? 2'h1 : _r_T_153; // @[Misc.scala:35:36, :49:20] wire _r_T_157 = _r_T_123 == 4'h5; // @[Misc.scala:49:20] wire [1:0] _r_T_159 = _r_T_157 ? 2'h2 : _r_T_156; // @[Misc.scala:35:36, :49:20] wire _r_T_160 = _r_T_123 == 4'h0; // @[Misc.scala:49:20] wire [1:0] _r_T_162 = _r_T_160 ? 2'h0 : _r_T_159; // @[Misc.scala:35:36, :49:20] wire _r_T_163 = _r_T_123 == 4'hE; // @[Misc.scala:49:20] wire _r_T_164 = _r_T_163; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_165 = _r_T_163 ? 2'h3 : _r_T_162; // @[Misc.scala:35:36, :49:20] wire _r_T_166 = &_r_T_123; // @[Misc.scala:49:20] wire _r_T_167 = _r_T_166 | _r_T_164; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_168 = _r_T_166 ? 2'h3 : _r_T_165; // @[Misc.scala:35:36, :49:20] wire _r_T_169 = _r_T_123 == 4'h6; // @[Misc.scala:49:20] wire _r_T_170 = _r_T_169 | _r_T_167; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_171 = _r_T_169 ? 2'h2 : _r_T_168; // @[Misc.scala:35:36, :49:20] wire _r_T_172 = _r_T_123 == 4'h7; // @[Misc.scala:49:20] wire _r_T_173 = _r_T_172 | _r_T_170; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_174 = _r_T_172 ? 2'h3 : _r_T_171; // @[Misc.scala:35:36, :49:20] wire _r_T_175 = _r_T_123 == 4'h1; // @[Misc.scala:49:20] wire _r_T_176 = _r_T_175 | _r_T_173; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_177 = _r_T_175 ? 2'h1 : _r_T_174; // @[Misc.scala:35:36, :49:20] wire _r_T_178 = _r_T_123 == 4'h2; // @[Misc.scala:49:20] wire _r_T_179 = _r_T_178 | _r_T_176; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_180 = _r_T_178 ? 2'h2 : _r_T_177; // @[Misc.scala:35:36, :49:20] wire _r_T_181 = _r_T_123 == 4'h3; // @[Misc.scala:49:20] wire is_hit_1 = _r_T_181 | _r_T_179; // @[Misc.scala:35:9, :49:20] wire [1:0] r_2_2 = _r_T_181 ? 2'h3 : _r_T_180; // @[Misc.scala:35:36, :49:20] wire [1:0] coh_on_hit_1_state = r_2_2; // @[Misc.scala:35:36] wire [4:0] state_new_state_1; // @[mshrs.scala:191:29] wire _state_T_35 = ~_state_T_34; // @[mshrs.scala:194:11] wire _state_T_36 = ~_rpq_io_enq_ready; // @[mshrs.scala:128:19, :194:11] wire _state_req_needs_wb_r_T_83 = _state_req_needs_wb_r_T_70 == 4'h8; // @[Misc.scala:56:20] wire [2:0] _state_req_needs_wb_r_T_85 = _state_req_needs_wb_r_T_83 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_87 = _state_req_needs_wb_r_T_70 == 4'h9; // @[Misc.scala:56:20] wire [2:0] _state_req_needs_wb_r_T_89 = _state_req_needs_wb_r_T_87 ? 3'h2 : _state_req_needs_wb_r_T_85; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_91 = _state_req_needs_wb_r_T_70 == 4'hA; // @[Misc.scala:56:20] wire [2:0] _state_req_needs_wb_r_T_93 = _state_req_needs_wb_r_T_91 ? 3'h1 : _state_req_needs_wb_r_T_89; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_95 = _state_req_needs_wb_r_T_70 == 4'hB; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_96 = _state_req_needs_wb_r_T_95; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_97 = _state_req_needs_wb_r_T_95 ? 3'h1 : _state_req_needs_wb_r_T_93; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_99 = _state_req_needs_wb_r_T_70 == 4'h4; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_100 = ~_state_req_needs_wb_r_T_99 & _state_req_needs_wb_r_T_96; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_101 = _state_req_needs_wb_r_T_99 ? 3'h5 : _state_req_needs_wb_r_T_97; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_103 = _state_req_needs_wb_r_T_70 == 4'h5; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_104 = ~_state_req_needs_wb_r_T_103 & _state_req_needs_wb_r_T_100; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_105 = _state_req_needs_wb_r_T_103 ? 3'h4 : _state_req_needs_wb_r_T_101; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_106 = {1'h0, _state_req_needs_wb_r_T_103}; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_107 = _state_req_needs_wb_r_T_70 == 4'h6; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_108 = ~_state_req_needs_wb_r_T_107 & _state_req_needs_wb_r_T_104; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_109 = _state_req_needs_wb_r_T_107 ? 3'h0 : _state_req_needs_wb_r_T_105; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_110 = _state_req_needs_wb_r_T_107 ? 2'h1 : _state_req_needs_wb_r_T_106; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_111 = _state_req_needs_wb_r_T_70 == 4'h7; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_112 = _state_req_needs_wb_r_T_111 | _state_req_needs_wb_r_T_108; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_113 = _state_req_needs_wb_r_T_111 ? 3'h0 : _state_req_needs_wb_r_T_109; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_114 = _state_req_needs_wb_r_T_111 ? 2'h1 : _state_req_needs_wb_r_T_110; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_115 = _state_req_needs_wb_r_T_70 == 4'h0; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_116 = ~_state_req_needs_wb_r_T_115 & _state_req_needs_wb_r_T_112; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_117 = _state_req_needs_wb_r_T_115 ? 3'h5 : _state_req_needs_wb_r_T_113; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_118 = _state_req_needs_wb_r_T_115 ? 2'h0 : _state_req_needs_wb_r_T_114; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_119 = _state_req_needs_wb_r_T_70 == 4'h1; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_120 = ~_state_req_needs_wb_r_T_119 & _state_req_needs_wb_r_T_116; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_121 = _state_req_needs_wb_r_T_119 ? 3'h4 : _state_req_needs_wb_r_T_117; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_122 = _state_req_needs_wb_r_T_119 ? 2'h1 : _state_req_needs_wb_r_T_118; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_123 = _state_req_needs_wb_r_T_70 == 4'h2; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_124 = ~_state_req_needs_wb_r_T_123 & _state_req_needs_wb_r_T_120; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_125 = _state_req_needs_wb_r_T_123 ? 3'h3 : _state_req_needs_wb_r_T_121; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_126 = _state_req_needs_wb_r_T_123 ? 2'h2 : _state_req_needs_wb_r_T_122; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_127 = _state_req_needs_wb_r_T_70 == 4'h3; // @[Misc.scala:56:20] wire state_req_needs_wb_r_1_1 = _state_req_needs_wb_r_T_127 | _state_req_needs_wb_r_T_124; // @[Misc.scala:38:9, :56:20] wire [2:0] state_req_needs_wb_r_2_1 = _state_req_needs_wb_r_T_127 ? 3'h3 : _state_req_needs_wb_r_T_125; // @[Misc.scala:38:36, :56:20] wire [1:0] state_req_needs_wb_r_3_1 = _state_req_needs_wb_r_T_127 ? 2'h2 : _state_req_needs_wb_r_T_126; // @[Misc.scala:38:63, :56:20] wire [1:0] state_req_needs_wb_meta_1_state = state_req_needs_wb_r_3_1; // @[Misc.scala:38:63] wire _state_r_c_cat_T_52 = _state_r_c_cat_T_50 | _state_r_c_cat_T_51; // @[Consts.scala:90:{32,42,49}] wire _state_r_c_cat_T_54 = _state_r_c_cat_T_52 | _state_r_c_cat_T_53; // @[Consts.scala:90:{42,59,66}] wire _state_r_c_cat_T_59 = _state_r_c_cat_T_55 | _state_r_c_cat_T_56; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_60 = _state_r_c_cat_T_59 | _state_r_c_cat_T_57; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_61 = _state_r_c_cat_T_60 | _state_r_c_cat_T_58; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_67 = _state_r_c_cat_T_62 | _state_r_c_cat_T_63; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_68 = _state_r_c_cat_T_67 | _state_r_c_cat_T_64; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_69 = _state_r_c_cat_T_68 | _state_r_c_cat_T_65; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_70 = _state_r_c_cat_T_69 | _state_r_c_cat_T_66; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_71 = _state_r_c_cat_T_61 | _state_r_c_cat_T_70; // @[package.scala:81:59] wire _state_r_c_cat_T_72 = _state_r_c_cat_T_54 | _state_r_c_cat_T_71; // @[Consts.scala:87:44, :90:{59,76}] wire _state_r_c_cat_T_75 = _state_r_c_cat_T_73 | _state_r_c_cat_T_74; // @[Consts.scala:90:{32,42,49}] wire _state_r_c_cat_T_77 = _state_r_c_cat_T_75 | _state_r_c_cat_T_76; // @[Consts.scala:90:{42,59,66}] wire _state_r_c_cat_T_82 = _state_r_c_cat_T_78 | _state_r_c_cat_T_79; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_83 = _state_r_c_cat_T_82 | _state_r_c_cat_T_80; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_84 = _state_r_c_cat_T_83 | _state_r_c_cat_T_81; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_90 = _state_r_c_cat_T_85 | _state_r_c_cat_T_86; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_91 = _state_r_c_cat_T_90 | _state_r_c_cat_T_87; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_92 = _state_r_c_cat_T_91 | _state_r_c_cat_T_88; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_93 = _state_r_c_cat_T_92 | _state_r_c_cat_T_89; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_94 = _state_r_c_cat_T_84 | _state_r_c_cat_T_93; // @[package.scala:81:59] wire _state_r_c_cat_T_95 = _state_r_c_cat_T_77 | _state_r_c_cat_T_94; // @[Consts.scala:87:44, :90:{59,76}] wire _state_r_c_cat_T_97 = _state_r_c_cat_T_95 | _state_r_c_cat_T_96; // @[Consts.scala:90:76, :91:{47,54}] wire _state_r_c_cat_T_99 = _state_r_c_cat_T_97 | _state_r_c_cat_T_98; // @[Consts.scala:91:{47,64,71}] wire [1:0] state_r_c_1 = {_state_r_c_cat_T_72, _state_r_c_cat_T_99}; // @[Metadata.scala:29:18] wire [3:0] _state_r_T_59 = {state_r_c_1, io_req_old_meta_coh_state_0}; // @[Metadata.scala:29:18, :58:19] wire _state_r_T_84 = _state_r_T_59 == 4'hC; // @[Misc.scala:49:20] wire [1:0] _state_r_T_86 = {1'h0, _state_r_T_84}; // @[Misc.scala:35:36, :49:20] wire _state_r_T_87 = _state_r_T_59 == 4'hD; // @[Misc.scala:49:20] wire [1:0] _state_r_T_89 = _state_r_T_87 ? 2'h2 : _state_r_T_86; // @[Misc.scala:35:36, :49:20] wire _state_r_T_90 = _state_r_T_59 == 4'h4; // @[Misc.scala:49:20] wire [1:0] _state_r_T_92 = _state_r_T_90 ? 2'h1 : _state_r_T_89; // @[Misc.scala:35:36, :49:20] wire _state_r_T_93 = _state_r_T_59 == 4'h5; // @[Misc.scala:49:20] wire [1:0] _state_r_T_95 = _state_r_T_93 ? 2'h2 : _state_r_T_92; // @[Misc.scala:35:36, :49:20] wire _state_r_T_96 = _state_r_T_59 == 4'h0; // @[Misc.scala:49:20] wire [1:0] _state_r_T_98 = _state_r_T_96 ? 2'h0 : _state_r_T_95; // @[Misc.scala:35:36, :49:20] wire _state_r_T_99 = _state_r_T_59 == 4'hE; // @[Misc.scala:49:20] wire _state_r_T_100 = _state_r_T_99; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_101 = _state_r_T_99 ? 2'h3 : _state_r_T_98; // @[Misc.scala:35:36, :49:20] wire _state_r_T_102 = &_state_r_T_59; // @[Misc.scala:49:20] wire _state_r_T_103 = _state_r_T_102 | _state_r_T_100; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_104 = _state_r_T_102 ? 2'h3 : _state_r_T_101; // @[Misc.scala:35:36, :49:20] wire _state_r_T_105 = _state_r_T_59 == 4'h6; // @[Misc.scala:49:20] wire _state_r_T_106 = _state_r_T_105 | _state_r_T_103; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_107 = _state_r_T_105 ? 2'h2 : _state_r_T_104; // @[Misc.scala:35:36, :49:20] wire _state_r_T_108 = _state_r_T_59 == 4'h7; // @[Misc.scala:49:20] wire _state_r_T_109 = _state_r_T_108 | _state_r_T_106; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_110 = _state_r_T_108 ? 2'h3 : _state_r_T_107; // @[Misc.scala:35:36, :49:20] wire _state_r_T_111 = _state_r_T_59 == 4'h1; // @[Misc.scala:49:20] wire _state_r_T_112 = _state_r_T_111 | _state_r_T_109; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_113 = _state_r_T_111 ? 2'h1 : _state_r_T_110; // @[Misc.scala:35:36, :49:20] wire _state_r_T_114 = _state_r_T_59 == 4'h2; // @[Misc.scala:49:20] wire _state_r_T_115 = _state_r_T_114 | _state_r_T_112; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_116 = _state_r_T_114 ? 2'h2 : _state_r_T_113; // @[Misc.scala:35:36, :49:20] wire _state_r_T_117 = _state_r_T_59 == 4'h3; // @[Misc.scala:49:20] wire state_is_hit_1 = _state_r_T_117 | _state_r_T_115; // @[Misc.scala:35:9, :49:20] wire [1:0] state_r_2_1 = _state_r_T_117 ? 2'h3 : _state_r_T_116; // @[Misc.scala:35:36, :49:20] wire [1:0] state_coh_on_hit_1_state = state_r_2_1; // @[Misc.scala:35:36] wire _state_T_39 = _state_T_37 | _state_T_38; // @[Consts.scala:90:{32,42,49}] wire _state_T_41 = _state_T_39 | _state_T_40; // @[Consts.scala:90:{42,59,66}] wire _state_T_46 = _state_T_42 | _state_T_43; // @[package.scala:16:47, :81:59] wire _state_T_47 = _state_T_46 | _state_T_44; // @[package.scala:16:47, :81:59] wire _state_T_48 = _state_T_47 | _state_T_45; // @[package.scala:16:47, :81:59] wire _state_T_54 = _state_T_49 | _state_T_50; // @[package.scala:16:47, :81:59] wire _state_T_55 = _state_T_54 | _state_T_51; // @[package.scala:16:47, :81:59] wire _state_T_56 = _state_T_55 | _state_T_52; // @[package.scala:16:47, :81:59] wire _state_T_57 = _state_T_56 | _state_T_53; // @[package.scala:16:47, :81:59] wire _state_T_58 = _state_T_48 | _state_T_57; // @[package.scala:81:59] wire _state_T_59 = _state_T_41 | _state_T_58; // @[Consts.scala:87:44, :90:{59,76}] wire _state_T_61 = ~_state_T_60; // @[mshrs.scala:201:15] wire _state_T_62 = ~_state_T_59; // @[Consts.scala:90:76]

Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }

module AsyncValidSync_13( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_13 io_out_source_valid_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File bim.scala: package boom.v4.ifu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import boom.v4.common._ import boom.v4.util.{BoomCoreStringPrefix, WrapInc} import scala.math.min class BIMMeta(implicit p: Parameters) extends BoomBundle()(p) with HasBoomFrontendParameters { val bims = Vec(bankWidth, UInt(2.W)) } case class BoomBIMParams( nSets: Int = 2048, nCols: Int = 8, singlePorted: Boolean = true, useFlops: Boolean = false, slow: Boolean = false ) class BIMBranchPredictorBank(params: BoomBIMParams = BoomBIMParams())(implicit p: Parameters) extends BranchPredictorBank()(p) { override val nSets = params.nSets val nCols = params.nCols val nSetsPerCol = nSets / nCols require(isPow2(nSets)) require(isPow2(nCols)) require(nCols < nSets) require(nCols > 1) val nWrBypassEntries = 2 def bimWrite(v: UInt, taken: Bool): UInt = { val old_bim_sat_taken = v === 3.U val old_bim_sat_ntaken = v === 0.U Mux(old_bim_sat_taken && taken, 3.U, Mux(old_bim_sat_ntaken && !taken, 0.U, Mux(taken, v + 1.U, v - 1.U))) } val s2_meta = Wire(new BIMMeta) override val metaSz = s2_meta.asUInt.getWidth val doing_reset = RegInit(true.B) val reset_idx = RegInit(0.U(log2Ceil(nSetsPerCol).W)) reset_idx := reset_idx + doing_reset when (reset_idx === (nSetsPerCol-1).U) { doing_reset := false.B } val mems = (0 until nCols) map {c => (f"bim_col$c", nSetsPerCol, bankWidth * 2)} val s0_col_mask = UIntToOH(s0_idx(log2Ceil(nCols)-1,0)) & Fill(nCols, s0_valid) val s1_col_mask = RegNext(s0_col_mask) val s0_col_idx = s0_idx >> log2Ceil(nCols) val s1_col_idx = RegNext(s0_col_idx) val s2_req_rdata_all = Wire(Vec(nCols, Vec(bankWidth, UInt(2.W)))) val s2_req_rdata = Mux1H(RegNext(s1_col_mask), s2_req_rdata_all) val s2_resp = Wire(Vec(bankWidth, Bool())) for (w <- 0 until bankWidth) { s2_resp(w) := s2_valid && s2_req_rdata(w)(1) && !doing_reset s2_meta.bims(w) := s2_req_rdata(w) if (!params.slow) { io.resp.f2(w).taken := s2_resp(w) } io.resp.f3(w).taken := RegNext(s2_resp(w)) } io.f3_meta := RegNext(s2_meta.asUInt) val s1_update_wdata = Wire(Vec(bankWidth, UInt(2.W))) val s1_update_wmask = Wire(Vec(bankWidth, Bool())) val s1_update_meta = s1_update.bits.meta.asTypeOf(new BIMMeta) val s1_update_col_mask = UIntToOH(s1_update_idx(log2Ceil(nCols)-1,0)) val s1_update_col_idx = s1_update_idx >> log2Ceil(nCols) val wrbypass_idxs = Reg(Vec(nWrBypassEntries, UInt(log2Ceil(nSets).W))) val wrbypass = Reg(Vec(nWrBypassEntries, Vec(bankWidth, UInt(2.W)))) val wrbypass_enq_idx = RegInit(0.U(log2Ceil(nWrBypassEntries).W)) val wrbypass_hits = VecInit((0 until nWrBypassEntries) map { i => !doing_reset && wrbypass_idxs(i) === s1_update_idx(log2Ceil(nSets)-1,0) }) val wrbypass_hit = wrbypass_hits.reduce(_||_) val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits) for (w <- 0 until bankWidth) { s1_update_wmask(w) := false.B s1_update_wdata(w) := DontCare val update_pc = s1_update.bits.pc + (w << 1).U when (s1_update.bits.br_mask(w) || (s1_update.bits.cfi_idx.valid && s1_update.bits.cfi_idx.bits === w.U)) { val was_taken = ( s1_update.bits.cfi_idx.valid && (s1_update.bits.cfi_idx.bits === w.U) && ( (s1_update.bits.cfi_is_br && s1_update.bits.br_mask(w) && s1_update.bits.cfi_taken) || s1_update.bits.cfi_is_jal ) ) val old_bim_value = Mux(wrbypass_hit, wrbypass(wrbypass_hit_idx)(w), s1_update_meta.bims(w)) s1_update_wmask(w) := true.B s1_update_wdata(w) := bimWrite(old_bim_value, was_taken) } } for (c <- 0 until nCols) { val rdata = Wire(Vec(bankWidth, UInt(2.W))) rdata := DontCare val (ren, ridx) = if (params.slow) (s1_col_mask(c), s1_col_idx) else (s0_col_mask(c), s0_col_idx) val wen = WireInit(doing_reset || (s1_update.valid && s1_update.bits.is_commit_update && s1_update_col_mask(c) && !ren)) if (params.slow) { s2_req_rdata_all(c) := rdata } else { s2_req_rdata_all(c) := RegNext(rdata) } if (params.useFlops) { val data = Reg(Vec(nSetsPerCol, Vec(bankWidth, UInt(2.W)))) when (wen && doing_reset) { data(reset_idx) := VecInit(Seq.fill(bankWidth) { 2.U }) } .elsewhen (wen) { for (i <- 0 until bankWidth) { when (s1_update_wmask(i)) { data(s1_update_col_idx)(i) := s1_update_wdata(i) } } } when (RegNext(ren) && !(wen && params.singlePorted.B)) { rdata := data(RegNext(ridx)) } } else { val data = SyncReadMem(nSetsPerCol, Vec(bankWidth, UInt(2.W))) data.suggestName(s"bim_col_${c}") val r = if (params.singlePorted) data.read(ridx, ren && !wen) else data.read(ridx, ren) rdata := r when (wen) { val widx = Mux(doing_reset, reset_idx, s1_update_col_idx) val wdata = Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 2.U }), s1_update_wdata) val wmask = Mux(doing_reset, (~(0.U(bankWidth.W))), s1_update_wmask.asUInt) data.write(widx, wdata, wmask.asBools) } } } when (s1_update_wmask.reduce(_||_) && s1_update.valid && s1_update.bits.is_commit_update) { when (wrbypass_hit) { wrbypass(wrbypass_hit_idx) := s1_update_wdata } .otherwise { wrbypass(wrbypass_enq_idx) := s1_update_wdata wrbypass_idxs(wrbypass_enq_idx) := s1_update_idx wrbypass_enq_idx := WrapInc(wrbypass_enq_idx, nWrBypassEntries) } } }

module bim_col_2_0( // @[bim.scala:157:29] input [7:0] RW0_addr, input RW0_en, input RW0_clk, input RW0_wmode, input [7:0] RW0_wdata, output [7:0] RW0_rdata, input [3:0] RW0_wmask ); bim_col_0_ext bim_col_0_ext ( // @[bim.scala:157:29] .RW0_addr (RW0_addr), .RW0_en (RW0_en), .RW0_clk (RW0_clk), .RW0_wmode (RW0_wmode), .RW0_wdata (RW0_wdata), .RW0_rdata (RW0_rdata), .RW0_wmask (RW0_wmask) ); // @[bim.scala:157:29] endmodule

Generate the Verilog code corresponding to the following Chisel files. File ShiftRegisterPriorityQueue.scala: package compressacc import chisel3._ import chisel3.util._ import chisel3.util._ // TODO : support enq & deq at the same cycle class PriorityQueueStageIO(keyWidth: Int, value: ValueInfo) extends Bundle { val output_prev = KeyValue(keyWidth, value) val output_nxt = KeyValue(keyWidth, value) val input_prev = Flipped(KeyValue(keyWidth, value)) val input_nxt = Flipped(KeyValue(keyWidth, value)) val cmd = Flipped(Valid(UInt(1.W))) val insert_here = Input(Bool()) val cur_input_keyval = Flipped(KeyValue(keyWidth, value)) val cur_output_keyval = KeyValue(keyWidth, value) } class PriorityQueueStage(keyWidth: Int, value: ValueInfo) extends Module { val io = IO(new PriorityQueueStageIO(keyWidth, value)) dontTouch(io) val CMD_DEQ = 0.U val CMD_ENQ = 1.U val MAX_VALUE = (1 << keyWidth) - 1 val key_reg = RegInit(MAX_VALUE.U(keyWidth.W)) val value_reg = Reg(value) io.output_prev.key := key_reg io.output_prev.value := value_reg io.output_nxt.key := key_reg io.output_nxt.value := value_reg io.cur_output_keyval.key := key_reg io.cur_output_keyval.value := value_reg when (io.cmd.valid) { switch (io.cmd.bits) { is (CMD_DEQ) { key_reg := io.input_nxt.key value_reg := io.input_nxt.value } is (CMD_ENQ) { when (io.insert_here) { key_reg := io.cur_input_keyval.key value_reg := io.cur_input_keyval.value } .elsewhen (key_reg >= io.cur_input_keyval.key) { key_reg := io.input_prev.key value_reg := io.input_prev.value } .otherwise { // do nothing } } } } } object PriorityQueueStage { def apply(keyWidth: Int, v: ValueInfo): PriorityQueueStage = new PriorityQueueStage(keyWidth, v) } // TODO // - This design is not scalable as the enqued_keyval is broadcasted to all the stages // - Add pipeline registers later class PriorityQueueIO(queSize: Int, keyWidth: Int, value: ValueInfo) extends Bundle { val cnt_bits = log2Ceil(queSize+1) val counter = Output(UInt(cnt_bits.W)) val enq = Flipped(Decoupled(KeyValue(keyWidth, value))) val deq = Decoupled(KeyValue(keyWidth, value)) } class PriorityQueue(queSize: Int, keyWidth: Int, value: ValueInfo) extends Module { val keyWidthInternal = keyWidth + 1 val CMD_DEQ = 0.U val CMD_ENQ = 1.U val io = IO(new PriorityQueueIO(queSize, keyWidthInternal, value)) dontTouch(io) val MAX_VALUE = ((1 << keyWidthInternal) - 1).U val cnt_bits = log2Ceil(queSize+1) // do not consider cases where we are inserting more entries then the queSize val counter = RegInit(0.U(cnt_bits.W)) io.counter := counter val full = (counter === queSize.U) val empty = (counter === 0.U) io.deq.valid := !empty io.enq.ready := !full when (io.enq.fire) { counter := counter + 1.U } when (io.deq.fire) { counter := counter - 1.U } val cmd_valid = io.enq.valid || io.deq.ready val cmd = Mux(io.enq.valid, CMD_ENQ, CMD_DEQ) assert(!(io.enq.valid && io.deq.ready)) val stages = Seq.fill(queSize)(Module(new PriorityQueueStage(keyWidthInternal, value))) for (i <- 0 until (queSize - 1)) { stages(i+1).io.input_prev <> stages(i).io.output_nxt stages(i).io.input_nxt <> stages(i+1).io.output_prev } stages(queSize-1).io.input_nxt.key := MAX_VALUE // stages(queSize-1).io.input_nxt.value := stages(queSize-1).io.input_nxt.value.symbol := 0.U // stages(queSize-1).io.input_nxt.value.child(0) := 0.U // stages(queSize-1).io.input_nxt.value.child(1) := 0.U stages(0).io.input_prev.key := io.enq.bits.key stages(0).io.input_prev.value <> io.enq.bits.value for (i <- 0 until queSize) { stages(i).io.cmd.valid := cmd_valid stages(i).io.cmd.bits := cmd stages(i).io.cur_input_keyval <> io.enq.bits } val is_large_or_equal = WireInit(VecInit(Seq.fill(queSize)(false.B))) for (i <- 0 until queSize) { is_large_or_equal(i) := (stages(i).io.cur_output_keyval.key >= io.enq.bits.key) } val is_large_or_equal_cat = Wire(UInt(queSize.W)) is_large_or_equal_cat := Cat(is_large_or_equal.reverse) val insert_here_idx = PriorityEncoder(is_large_or_equal_cat) for (i <- 0 until queSize) { when (i.U === insert_here_idx) { stages(i).io.insert_here := true.B } .otherwise { stages(i).io.insert_here := false.B } } io.deq.bits <> stages(0).io.output_prev }

module PriorityQueueStage_54( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: package constellation.channel import chisel3._ import chisel3.util._ import freechips.rocketchip.diplomacy._ import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.util._ import constellation.noc.{HasNoCParams} class NoCMonitor(val cParam: ChannelParams)(implicit val p: Parameters) extends Module with HasNoCParams { val io = IO(new Bundle { val in = Input(new Channel(cParam)) }) val in_flight = RegInit(VecInit(Seq.fill(cParam.nVirtualChannels) { false.B })) for (i <- 0 until cParam.srcSpeedup) { val flit = io.in.flit(i) when (flit.valid) { when (flit.bits.head) { in_flight(flit.bits.virt_channel_id) := true.B assert (!in_flight(flit.bits.virt_channel_id), "Flit head/tail sequencing is broken") } when (flit.bits.tail) { in_flight(flit.bits.virt_channel_id) := false.B } } val possibleFlows = cParam.possibleFlows when (flit.valid && flit.bits.head) { cParam match { case n: ChannelParams => n.virtualChannelParams.zipWithIndex.foreach { case (v,i) => assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR) } case _ => assert(cParam.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR) } } } } File Types.scala: package constellation.routing import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Parameters} import constellation.noc.{HasNoCParams} import constellation.channel.{Flit} /** A representation for 1 specific virtual channel in wormhole routing * * @param src the source node * @param vc ID for the virtual channel * @param dst the destination node * @param n_vc the number of virtual channels */ // BEGIN: ChannelRoutingInfo case class ChannelRoutingInfo( src: Int, dst: Int, vc: Int, n_vc: Int ) { // END: ChannelRoutingInfo require (src >= -1 && dst >= -1 && vc >= 0, s"Illegal $this") require (!(src == -1 && dst == -1), s"Illegal $this") require (vc < n_vc, s"Illegal $this") val isIngress = src == -1 val isEgress = dst == -1 } /** Represents the properties of a packet that are relevant for routing * ingressId and egressId uniquely identify a flow, but vnet and dst are used here * to simplify the implementation of routingrelations * * @param ingressId packet's source ingress point * @param egressId packet's destination egress point * @param vNet virtual subnetwork identifier * @param dst packet's destination node ID */ // BEGIN: FlowRoutingInfo case class FlowRoutingInfo( ingressId: Int, egressId: Int, vNetId: Int, ingressNode: Int, ingressNodeId: Int, egressNode: Int, egressNodeId: Int, fifo: Boolean ) { // END: FlowRoutingInfo def isFlow(f: FlowRoutingBundle): Bool = { (f.ingress_node === ingressNode.U && f.egress_node === egressNode.U && f.ingress_node_id === ingressNodeId.U && f.egress_node_id === egressNodeId.U) } def asLiteral(b: FlowRoutingBundle): BigInt = { Seq( (vNetId , b.vnet_id), (ingressNode , b.ingress_node), (ingressNodeId , b.ingress_node_id), (egressNode , b.egress_node), (egressNodeId , b.egress_node_id) ).foldLeft(0)((l, t) => { (l << t._2.getWidth) | t._1 }) } } class FlowRoutingBundle(implicit val p: Parameters) extends Bundle with HasNoCParams { // Instead of tracking ingress/egress ID, track the physical destination id and the offset at the destination // This simplifies the routing tables val vnet_id = UInt(log2Ceil(nVirtualNetworks).W) val ingress_node = UInt(log2Ceil(nNodes).W) val ingress_node_id = UInt(log2Ceil(maxIngressesAtNode).W) val egress_node = UInt(log2Ceil(nNodes).W) val egress_node_id = UInt(log2Ceil(maxEgressesAtNode).W) }

module NoCMonitor_55( // @[Monitor.scala:11:7] input clock, // @[Monitor.scala:11:7] input reset, // @[Monitor.scala:11:7] input io_in_flit_0_valid, // @[Monitor.scala:12:14] input io_in_flit_0_bits_head, // @[Monitor.scala:12:14] input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14] input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14] input [4:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14] input [2:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14] ); reg in_flight_0; // @[Monitor.scala:16:26] reg in_flight_1; // @[Monitor.scala:16:26] reg in_flight_2; // @[Monitor.scala:16:26] reg in_flight_3; // @[Monitor.scala:16:26] reg in_flight_4; // @[Monitor.scala:16:26] reg in_flight_5; // @[Monitor.scala:16:26] reg in_flight_6; // @[Monitor.scala:16:26] reg in_flight_7; // @[Monitor.scala:16:26]

Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module TLMonitor_53( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input io_in_a_bits_source, // @[Monitor.scala:20:14] input [8:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [8:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_beats1_decode_T_1 = 2'h3; // @[package.scala:243:76] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_beats1_decode_T_2 = 2'h0; // @[package.scala:243:46] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [8:0] _c_first_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_first_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_first_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_first_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_set_wo_ready_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_set_wo_ready_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_opcodes_set_interm_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_opcodes_set_interm_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_sizes_set_interm_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_sizes_set_interm_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_opcodes_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_opcodes_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_sizes_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_sizes_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_probe_ack_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_probe_ack_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_probe_ack_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_probe_ack_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_4_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_5_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [17:0] _c_sizes_set_T_1 = 18'h0; // @[Monitor.scala:768:52] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] c_sizes_set = 4'h0; // @[Monitor.scala:741:34] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [4:0] _c_first_beats1_decode_T = 5'h3; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [1:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire _source_ok_T = ~io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [4:0] _GEN = 5'h3 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [4:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [4:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [4:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [1:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[1:0]; // @[package.scala:243:{71,76}] wire [1:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [8:0] _is_aligned_T = {7'h0, io_in_a_bits_address_0[1:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 9'h0; // @[Edges.scala:21:{16,24}] wire mask_sizeOH_shiftAmount = _mask_sizeOH_T[0]; // @[OneHot.scala:64:49] wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [1:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire [1:0] mask_sizeOH = {_mask_sizeOH_T_2[1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_0_1 = io_in_a_bits_size_0[1]; // @[Misc.scala:206:21] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_1_2 = mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire _source_ok_T_1 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_1; // @[Parameters.scala:1138:31] wire _T_898 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_898; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_898; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [1:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg source; // @[Monitor.scala:390:22] reg [8:0] address; // @[Monitor.scala:391:22] wire _T_966 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_966; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_966; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_966; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [4:0] _GEN_0 = 5'h3 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [1:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg source_1; // @[Monitor.scala:541:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [3:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [1:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [1:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [3:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [3:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [3:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [3:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [3:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [3:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [3:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [3:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [3:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [3:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [3:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [15:0] _a_size_lookup_T_6 = {12'h0, _a_size_lookup_T_1}; // @[Monitor.scala:637:97, :641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [1:0] _GEN_2 = {1'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_3 = 2'h1 << _GEN_2; // @[OneHot.scala:58:35] wire [1:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [1:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T & _a_set_wo_ready_T[0]; // @[OneHot.scala:58:35] wire _T_831 = _T_898 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_831 & _a_set_T[0]; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_831 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_831 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [3:0] _GEN_4 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [3:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_4; // @[Monitor.scala:659:79] wire [3:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_4; // @[Monitor.scala:659:79, :660:77] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_831 ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [17:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_831 ? _a_sizes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [3:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46] wire _T_877 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [1:0] _GEN_6 = {1'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_7 = 2'h1 << _GEN_6; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_877 & ~d_release_ack & _d_clr_wo_ready_T[0]; // @[OneHot.scala:58:35] wire _T_846 = _T_966 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_846 & _d_clr_T[0]; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_5 = 31'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_846 ? _d_opcodes_clr_T_5[3:0] : 4'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [30:0] _d_sizes_clr_T_5 = 31'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_846 ? _d_sizes_clr_T_5[3:0] : 4'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [3:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [3:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [3:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [3:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [1:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:637:97, :749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [3:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [15:0] _c_size_lookup_T_6 = {12'h0, _c_size_lookup_T_1}; // @[Monitor.scala:637:97, :750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [3:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_942 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_942 & d_release_ack_1 & _d_clr_wo_ready_T_1[0]; // @[OneHot.scala:58:35] wire _T_924 = _T_966 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_924 & _d_clr_T_1[0]; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_11 = 31'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_924 ? _d_opcodes_clr_T_11[3:0] : 4'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [30:0] _d_sizes_clr_T_11 = 31'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_924 ? _d_sizes_clr_T_11[3:0] : 4'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [3:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [3:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module TLMonitor_3( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_44 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_46 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_50 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_52 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_56 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_58 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_62 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_64 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_68 = 1'h1; // @[Parameters.scala:56:32] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_25 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_26 = _source_ok_T_25 == 5'h8; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_29 = source_ok_uncommonBits_4 != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_30 = _source_ok_T_28 & _source_ok_T_29; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire _source_ok_T_31 = io_in_a_bits_source_0 == 7'h23; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_31; // @[Parameters.scala:1138:31] wire _source_ok_T_32 = io_in_a_bits_source_0 == 7'h24; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_32; // @[Parameters.scala:1138:31] wire _source_ok_T_33 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_33; // @[Parameters.scala:1138:31] wire _source_ok_T_34 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_35 = _source_ok_T_34 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_36 = _source_ok_T_35 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_37 = _source_ok_T_36 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_38 = _source_ok_T_37 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_39 = _source_ok_T_38 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_40 = _source_ok_T_39 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_40 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [28:0] _is_aligned_T = {23'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_46 = _uncommonBits_T_46[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_47 = _uncommonBits_T_47[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_53 = _uncommonBits_T_53[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_41 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_41; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_42 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_48 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_54 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_60 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_66 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_43 = _source_ok_T_42 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_45 = _source_ok_T_43; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_47 = _source_ok_T_45; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_47; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_49 = _source_ok_T_48 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_51 = _source_ok_T_49; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_53 = _source_ok_T_51; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_53; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_55 = _source_ok_T_54 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_57 = _source_ok_T_55; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_59 = _source_ok_T_57; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_59; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_61 = _source_ok_T_60 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_63 = _source_ok_T_61; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_65 = _source_ok_T_63; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_65; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_67 = _source_ok_T_66 == 5'h8; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_69 = _source_ok_T_67; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_70 = source_ok_uncommonBits_9 != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_71 = _source_ok_T_69 & _source_ok_T_70; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_5 = _source_ok_T_71; // @[Parameters.scala:1138:31] wire _source_ok_T_72 = io_in_d_bits_source_0 == 7'h23; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_72; // @[Parameters.scala:1138:31] wire _source_ok_T_73 = io_in_d_bits_source_0 == 7'h24; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_73; // @[Parameters.scala:1138:31] wire _source_ok_T_74 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_74; // @[Parameters.scala:1138:31] wire _source_ok_T_75 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_76 = _source_ok_T_75 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_77 = _source_ok_T_76 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_78 = _source_ok_T_77 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_79 = _source_ok_T_78 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_80 = _source_ok_T_79 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_81 = _source_ok_T_80 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_81 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _T_1216 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1216; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1216; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [28:0] address; // @[Monitor.scala:391:22] wire _T_1289 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1289; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1289; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1289; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [259:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [259:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1142 = _T_1216 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1142 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1142 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1142 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1142 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1142 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1188 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1188 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1157 = _T_1289 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1157 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1157 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1157 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [259:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1260 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1260 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1242 = _T_1289 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1242 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1242 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1242 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to the following Chisel files. File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Metadata.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.constants.MemoryOpConstants import freechips.rocketchip.util._ object ClientStates { val width = 2 def Nothing = 0.U(width.W) def Branch = 1.U(width.W) def Trunk = 2.U(width.W) def Dirty = 3.U(width.W) def hasReadPermission(state: UInt): Bool = state > Nothing def hasWritePermission(state: UInt): Bool = state > Branch } object MemoryOpCategories extends MemoryOpConstants { def wr = Cat(true.B, true.B) // Op actually writes def wi = Cat(false.B, true.B) // Future op will write def rd = Cat(false.B, false.B) // Op only reads def categorize(cmd: UInt): UInt = { val cat = Cat(isWrite(cmd), isWriteIntent(cmd)) //assert(cat.isOneOf(wr,wi,rd), "Could not categorize command.") cat } } /** Stores the client-side coherence information, * such as permissions on the data and whether the data is dirty. * Its API can be used to make TileLink messages in response to * memory operations, cache control oeprations, or Probe messages. */ class ClientMetadata extends Bundle { /** Actual state information stored in this bundle */ val state = UInt(ClientStates.width.W) /** Metadata equality */ def ===(rhs: UInt): Bool = state === rhs def ===(rhs: ClientMetadata): Bool = state === rhs.state def =/=(rhs: ClientMetadata): Bool = !this.===(rhs) /** Is the block's data present in this cache */ def isValid(dummy: Int = 0): Bool = state > ClientStates.Nothing /** Determine whether this cmd misses, and the new state (on hit) or param to be sent (on miss) */ private def growStarter(cmd: UInt): (Bool, UInt) = { import MemoryOpCategories._ import TLPermissions._ import ClientStates._ val c = categorize(cmd) MuxTLookup(Cat(c, state), (false.B, 0.U), Seq( //(effect, am now) -> (was a hit, next) Cat(rd, Dirty) -> (true.B, Dirty), Cat(rd, Trunk) -> (true.B, Trunk), Cat(rd, Branch) -> (true.B, Branch), Cat(wi, Dirty) -> (true.B, Dirty), Cat(wi, Trunk) -> (true.B, Trunk), Cat(wr, Dirty) -> (true.B, Dirty), Cat(wr, Trunk) -> (true.B, Dirty), //(effect, am now) -> (was a miss, param) Cat(rd, Nothing) -> (false.B, NtoB), Cat(wi, Branch) -> (false.B, BtoT), Cat(wi, Nothing) -> (false.B, NtoT), Cat(wr, Branch) -> (false.B, BtoT), Cat(wr, Nothing) -> (false.B, NtoT))) } /** Determine what state to go to after miss based on Grant param * For now, doesn't depend on state (which may have been Probed). */ private def growFinisher(cmd: UInt, param: UInt): UInt = { import MemoryOpCategories._ import TLPermissions._ import ClientStates._ val c = categorize(cmd) //assert(c === rd || param === toT, "Client was expecting trunk permissions.") MuxLookup(Cat(c, param), Nothing)(Seq( //(effect param) -> (next) Cat(rd, toB) -> Branch, Cat(rd, toT) -> Trunk, Cat(wi, toT) -> Trunk, Cat(wr, toT) -> Dirty)) } /** Does this cache have permissions on this block sufficient to perform op, * and what to do next (Acquire message param or updated metadata). */ def onAccess(cmd: UInt): (Bool, UInt, ClientMetadata) = { val r = growStarter(cmd) (r._1, r._2, ClientMetadata(r._2)) } /** Does a secondary miss on the block require another Acquire message */ def onSecondaryAccess(first_cmd: UInt, second_cmd: UInt): (Bool, Bool, UInt, ClientMetadata, UInt) = { import MemoryOpCategories._ val r1 = growStarter(first_cmd) val r2 = growStarter(second_cmd) val needs_second_acq = isWriteIntent(second_cmd) && !isWriteIntent(first_cmd) val hit_again = r1._1 && r2._1 val dirties = categorize(second_cmd) === wr val biggest_grow_param = Mux(dirties, r2._2, r1._2) val dirtiest_state = ClientMetadata(biggest_grow_param) val dirtiest_cmd = Mux(dirties, second_cmd, first_cmd) (needs_second_acq, hit_again, biggest_grow_param, dirtiest_state, dirtiest_cmd) } /** Metadata change on a returned Grant */ def onGrant(cmd: UInt, param: UInt): ClientMetadata = ClientMetadata(growFinisher(cmd, param)) /** Determine what state to go to based on Probe param */ private def shrinkHelper(param: UInt): (Bool, UInt, UInt) = { import ClientStates._ import TLPermissions._ MuxTLookup(Cat(param, state), (false.B, 0.U, 0.U), Seq( //(wanted, am now) -> (hasDirtyData resp, next) Cat(toT, Dirty) -> (true.B, TtoT, Trunk), Cat(toT, Trunk) -> (false.B, TtoT, Trunk), Cat(toT, Branch) -> (false.B, BtoB, Branch), Cat(toT, Nothing) -> (false.B, NtoN, Nothing), Cat(toB, Dirty) -> (true.B, TtoB, Branch), Cat(toB, Trunk) -> (false.B, TtoB, Branch), // Policy: Don't notify on clean downgrade Cat(toB, Branch) -> (false.B, BtoB, Branch), Cat(toB, Nothing) -> (false.B, NtoN, Nothing), Cat(toN, Dirty) -> (true.B, TtoN, Nothing), Cat(toN, Trunk) -> (false.B, TtoN, Nothing), // Policy: Don't notify on clean downgrade Cat(toN, Branch) -> (false.B, BtoN, Nothing), // Policy: Don't notify on clean downgrade Cat(toN, Nothing) -> (false.B, NtoN, Nothing))) } /** Translate cache control cmds into Probe param */ private def cmdToPermCap(cmd: UInt): UInt = { import MemoryOpCategories._ import TLPermissions._ MuxLookup(cmd, toN)(Seq( M_FLUSH -> toN, M_PRODUCE -> toB, M_CLEAN -> toT)) } def onCacheControl(cmd: UInt): (Bool, UInt, ClientMetadata) = { val r = shrinkHelper(cmdToPermCap(cmd)) (r._1, r._2, ClientMetadata(r._3)) } def onProbe(param: UInt): (Bool, UInt, ClientMetadata) = { val r = shrinkHelper(param) (r._1, r._2, ClientMetadata(r._3)) } } /** Factories for ClientMetadata, including on reset */ object ClientMetadata { def apply(perm: UInt) = { val meta = Wire(new ClientMetadata) meta.state := perm meta } def onReset = ClientMetadata(ClientStates.Nothing) def maximum = ClientMetadata(ClientStates.Dirty) } File MSHR.scala: package shuttle.dmem import chisel3._ import chisel3.util._ import chisel3.experimental.dataview._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import freechips.rocketchip.rocket._ class ShuttleDCacheMSHR(id: Int)(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCacheModule()(p) { val io = IO(new Bundle { val req_pri_val = Input(Bool()) val req_pri_rdy = Output(Bool()) val req_sec_val = Input(Bool()) val req_sec_rdy = Output(Bool()) val req_bits = Input(new ShuttleMSHRReq()) val probe_addr = Input(UInt(paddrBits.W)) val idx_match = Output(Bool()) val tag = Output(Bits(tagBits.W)) val mem_acquire = Decoupled(new TLBundleA(edge.bundle)) val mem_grant = Flipped(Valid(new TLBundleD(edge.bundle))) val mem_finish = Decoupled(new TLBundleE(edge.bundle)) val refill = Output(new L1RefillReq()) // Data is bypassed val meta_write = Decoupled(new L1MetaWriteReq) val replay = Decoupled(new ShuttleMSHRReq) val wb_req = Decoupled(new WritebackReq(edge.bundle)) val probe_rdy = Output(Bool()) }) val s_invalid :: s_wb_req :: s_wb_resp :: s_meta_clear :: s_refill_req :: s_refill_resp :: s_meta_write_req :: s_meta_write_resp :: s_drain_rpq :: Nil = Enum(9) val state = RegInit(s_invalid) val req = Reg(new ShuttleMSHRReq) val req_idx = req.addr(untagBits-1,blockOffBits) val req_tag = req.addr >> untagBits val req_block_addr = (req.addr >> blockOffBits) << blockOffBits val idx_match = req_idx === io.req_bits.addr(untagBits-1,blockOffBits) val probe_idx_match = req_idx === io.probe_addr(untagBits-1,blockOffBits) val new_coh = RegInit(ClientMetadata.onReset) val (_, shrink_param, coh_on_clear) = req.old_meta.coh.onCacheControl(M_FLUSH) val grow_param = new_coh.onAccess(req.cmd)._2 val coh_on_grant = new_coh.onGrant(req.cmd, io.mem_grant.bits.param) // We only accept secondary misses if we haven't yet sent an Acquire to outer memory // or if the Acquire that was sent will obtain a Grant with sufficient permissions // to let us replay this new request. I.e. we don't handle multiple outstanding // Acquires on the same block for now. val (cmd_requires_second_acquire, is_hit_again, _, dirtier_coh, dirtier_cmd) = new_coh.onSecondaryAccess(req.cmd, io.req_bits.cmd) val states_before_refill = Seq(s_wb_req, s_wb_resp, s_meta_clear) val (_, _, refill_done, refill_address_inc) = edge.addr_inc(io.mem_grant) val sec_rdy = idx_match && (state.isOneOf(states_before_refill) || (state.isOneOf(s_refill_req, s_refill_resp) && !cmd_requires_second_acquire && !refill_done)) val rpq = Module(new Queue(new ShuttleMSHRReq, cfg.nRPQ)) rpq.io.enq.valid := (io.req_pri_val && io.req_pri_rdy || io.req_sec_val && sec_rdy) && !isPrefetch(io.req_bits.cmd) rpq.io.enq.bits := io.req_bits rpq.io.deq.ready := (io.replay.ready && state === s_drain_rpq) || state === s_invalid val acked = Reg(Bool()) when (io.mem_grant.valid) { acked := true.B } when (state === s_drain_rpq && !rpq.io.deq.valid) { state := s_invalid } when (state === s_meta_write_resp) { // this wait state allows us to catch RAW hazards on the tags via nack_victim state := s_drain_rpq } when (state === s_meta_write_req && io.meta_write.ready) { state := s_meta_write_resp } when (state === s_refill_resp && refill_done) { new_coh := coh_on_grant state := s_meta_write_req } when (io.mem_acquire.fire) { // s_refill_req state := s_refill_resp } when (state === s_meta_clear && io.meta_write.ready) { state := s_refill_req } when (state === s_wb_resp && io.wb_req.ready && acked) { state := s_meta_clear } when (io.wb_req.fire) { // s_wb_req state := s_wb_resp } when (io.req_sec_val && io.req_sec_rdy) { // s_wb_req, s_wb_resp, s_refill_req //If we get a secondary miss that needs more permissions before we've sent // out the primary miss's Acquire, we can upgrade the permissions we're // going to ask for in s_refill_req req.cmd := dirtier_cmd when (is_hit_again) { new_coh := dirtier_coh } } when (io.req_pri_val && io.req_pri_rdy) { req := io.req_bits acked := false.B val old_coh = io.req_bits.old_meta.coh val needs_wb = old_coh.onCacheControl(M_FLUSH)._1 val (is_hit, _, coh_on_hit) = old_coh.onAccess(io.req_bits.cmd) when (io.req_bits.tag_match) { when (is_hit) { // set dirty bit new_coh := coh_on_hit state := s_meta_write_req }.otherwise { // upgrade permissions new_coh := old_coh state := s_refill_req } }.otherwise { // writback if necessary and refill new_coh := ClientMetadata.onReset state := Mux(needs_wb, s_wb_req, s_meta_clear) } } val grantackq = Module(new Queue(new TLBundleE(edge.bundle), 1)) val can_finish = state.isOneOf(s_invalid, s_refill_req) grantackq.io.enq.valid := refill_done && edge.isRequest(io.mem_grant.bits) grantackq.io.enq.bits := edge.GrantAck(io.mem_grant.bits) io.mem_finish.valid := grantackq.io.deq.valid && can_finish io.mem_finish.bits := grantackq.io.deq.bits grantackq.io.deq.ready := io.mem_finish.ready && can_finish io.idx_match := (state =/= s_invalid) && idx_match io.refill.way_en := req.way_en io.refill.addr := req_block_addr | refill_address_inc io.tag := req_tag io.req_pri_rdy := state === s_invalid io.req_sec_rdy := sec_rdy && rpq.io.enq.ready val meta_hazard = RegInit(0.U(2.W)) when (meta_hazard =/= 0.U) { meta_hazard := meta_hazard + 1.U } when (io.meta_write.fire) { meta_hazard := 1.U } io.probe_rdy := !(state =/= s_invalid && probe_idx_match) || (!state.isOneOf(states_before_refill) && meta_hazard === 0.U) io.meta_write.valid := state.isOneOf(s_meta_write_req, s_meta_clear) io.meta_write.bits.idx := req_idx io.meta_write.bits.tag := io.tag io.meta_write.bits.data.coh := Mux(state === s_meta_clear, coh_on_clear, new_coh) io.meta_write.bits.data.tag := io.tag io.meta_write.bits.way_en := req.way_en io.wb_req.valid := state === s_wb_req io.wb_req.bits.source := id.U io.wb_req.bits.tag := req.old_meta.tag io.wb_req.bits.idx := req_idx io.wb_req.bits.param := shrink_param io.wb_req.bits.way_en := req.way_en io.wb_req.bits.voluntary := true.B io.mem_acquire.valid := state === s_refill_req && grantackq.io.enq.ready io.mem_acquire.bits := edge.AcquireBlock( fromSource = id.U, toAddress = Cat(io.tag, req_idx) << blockOffBits, lgSize = lgCacheBlockBytes.U, growPermissions = grow_param)._2 io.replay.valid := state === s_drain_rpq && rpq.io.deq.valid io.replay.bits := rpq.io.deq.bits io.replay.bits.addr := Cat(io.tag, req_idx, rpq.io.deq.bits.addr(blockOffBits-1,0)) io.replay.bits.cmd := rpq.io.deq.bits.cmd when (state === s_drain_rpq && !rpq.io.deq.valid) { state := Mux(RegNext(!rpq.io.deq.valid), s_invalid, state) } rpq.io.deq.ready := io.replay.ready && state === s_drain_rpq } File Consts.scala: // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket.constants import chisel3._ import chisel3.util._ import freechips.rocketchip.util._ trait ScalarOpConstants { val SZ_BR = 3 def BR_X = BitPat("b???") def BR_EQ = 0.U(3.W) def BR_NE = 1.U(3.W) def BR_J = 2.U(3.W) def BR_N = 3.U(3.W) def BR_LT = 4.U(3.W) def BR_GE = 5.U(3.W) def BR_LTU = 6.U(3.W) def BR_GEU = 7.U(3.W) def A1_X = BitPat("b??") def A1_ZERO = 0.U(2.W) def A1_RS1 = 1.U(2.W) def A1_PC = 2.U(2.W) def A1_RS1SHL = 3.U(2.W) def IMM_X = BitPat("b???") def IMM_S = 0.U(3.W) def IMM_SB = 1.U(3.W) def IMM_U = 2.U(3.W) def IMM_UJ = 3.U(3.W) def IMM_I = 4.U(3.W) def IMM_Z = 5.U(3.W) def A2_X = BitPat("b???") def A2_ZERO = 0.U(3.W) def A2_SIZE = 1.U(3.W) def A2_RS2 = 2.U(3.W) def A2_IMM = 3.U(3.W) def A2_RS2OH = 4.U(3.W) def A2_IMMOH = 5.U(3.W) def X = BitPat("b?") def N = BitPat("b0") def Y = BitPat("b1") val SZ_DW = 1 def DW_X = X def DW_32 = false.B def DW_64 = true.B def DW_XPR = DW_64 } trait MemoryOpConstants { val NUM_XA_OPS = 9 val M_SZ = 5 def M_X = BitPat("b?????"); def M_XRD = "b00000".U; // int load def M_XWR = "b00001".U; // int store def M_PFR = "b00010".U; // prefetch with intent to read def M_PFW = "b00011".U; // prefetch with intent to write def M_XA_SWAP = "b00100".U def M_FLUSH_ALL = "b00101".U // flush all lines def M_XLR = "b00110".U def M_XSC = "b00111".U def M_XA_ADD = "b01000".U def M_XA_XOR = "b01001".U def M_XA_OR = "b01010".U def M_XA_AND = "b01011".U def M_XA_MIN = "b01100".U def M_XA_MAX = "b01101".U def M_XA_MINU = "b01110".U def M_XA_MAXU = "b01111".U def M_FLUSH = "b10000".U // write back dirty data and cede R/W permissions def M_PWR = "b10001".U // partial (masked) store def M_PRODUCE = "b10010".U // write back dirty data and cede W permissions def M_CLEAN = "b10011".U // write back dirty data and retain R/W permissions def M_SFENCE = "b10100".U // SFENCE.VMA def M_HFENCEV = "b10101".U // HFENCE.VVMA def M_HFENCEG = "b10110".U // HFENCE.GVMA def M_WOK = "b10111".U // check write permissions but don't perform a write def M_HLVX = "b10000".U // HLVX instruction def isAMOLogical(cmd: UInt) = cmd.isOneOf(M_XA_SWAP, M_XA_XOR, M_XA_OR, M_XA_AND) def isAMOArithmetic(cmd: UInt) = cmd.isOneOf(M_XA_ADD, M_XA_MIN, M_XA_MAX, M_XA_MINU, M_XA_MAXU) def isAMO(cmd: UInt) = isAMOLogical(cmd) || isAMOArithmetic(cmd) def isPrefetch(cmd: UInt) = cmd === M_PFR || cmd === M_PFW def isRead(cmd: UInt) = cmd.isOneOf(M_XRD, M_HLVX, M_XLR, M_XSC) || isAMO(cmd) def isWrite(cmd: UInt) = cmd === M_XWR || cmd === M_PWR || cmd === M_XSC || isAMO(cmd) def isWriteIntent(cmd: UInt) = isWrite(cmd) || cmd === M_PFW || cmd === M_XLR } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{ AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry, IdRange, RegionType, TransferSizes } import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions} import freechips.rocketchip.util.{ AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase, CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct } import scala.math.max //These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel case class TLMasterToSlaveTransferSizes( // Supports both Acquire+Release of the following two sizes: acquireT: TransferSizes = TransferSizes.none, acquireB: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none) extends TLCommonTransferSizes { def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .intersect(rhs.acquireT), acquireB = acquireB .intersect(rhs.acquireB), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint)) def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .mincover(rhs.acquireT), acquireB = acquireB .mincover(rhs.acquireB), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint)) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(acquireT, "T"), str(acquireB, "B"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""acquireT = ${acquireT} |acquireB = ${acquireB} |arithmetic = ${arithmetic} |logical = ${logical} |get = ${get} |putFull = ${putFull} |putPartial = ${putPartial} |hint = ${hint} | |""".stripMargin } } object TLMasterToSlaveTransferSizes { def unknownEmits = TLMasterToSlaveTransferSizes( acquireT = TransferSizes(1, 4096), acquireB = TransferSizes(1, 4096), arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096)) def unknownSupports = TLMasterToSlaveTransferSizes() } //These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel case class TLSlaveToMasterTransferSizes( probe: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none ) extends TLCommonTransferSizes { def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .intersect(rhs.probe), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint) ) def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .mincover(rhs.probe), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint) ) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(probe, "P"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""probe = ${probe} |arithmetic = ${arithmetic} |logical = ${logical} |get = ${get} |putFull = ${putFull} |putPartial = ${putPartial} |hint = ${hint} | |""".stripMargin } } object TLSlaveToMasterTransferSizes { def unknownEmits = TLSlaveToMasterTransferSizes( arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096), probe = TransferSizes(1, 4096)) def unknownSupports = TLSlaveToMasterTransferSizes() } trait TLCommonTransferSizes { def arithmetic: TransferSizes def logical: TransferSizes def get: TransferSizes def putFull: TransferSizes def putPartial: TransferSizes def hint: TransferSizes } class TLSlaveParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], setName: Option[String], val address: Seq[AddressSet], val regionType: RegionType.T, val executable: Boolean, val fifoId: Option[Int], val supports: TLMasterToSlaveTransferSizes, val emits: TLSlaveToMasterTransferSizes, // By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation) val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData // If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order // Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck // ReleaseAck may NEVER be denied extends SimpleProduct { def sortedAddress = address.sorted override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters] override def productPrefix = "TLSlaveParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 11 def productElement(n: Int): Any = n match { case 0 => name case 1 => address case 2 => resources case 3 => regionType case 4 => executable case 5 => fifoId case 6 => supports case 7 => emits case 8 => alwaysGrantsT case 9 => mayDenyGet case 10 => mayDenyPut case _ => throw new IndexOutOfBoundsException(n.toString) } def supportsAcquireT: TransferSizes = supports.acquireT def supportsAcquireB: TransferSizes = supports.acquireB def supportsArithmetic: TransferSizes = supports.arithmetic def supportsLogical: TransferSizes = supports.logical def supportsGet: TransferSizes = supports.get def supportsPutFull: TransferSizes = supports.putFull def supportsPutPartial: TransferSizes = supports.putPartial def supportsHint: TransferSizes = supports.hint require (!address.isEmpty, "Address cannot be empty") address.foreach { a => require (a.finite, "Address must be finite") } address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)") require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)") require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)") require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)") require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)") require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)") require (!alwaysGrantsT || supportsAcquireT, s"Must supportAcquireT if promising to always grantT") // Make sure that the regionType agrees with the capabilities require (!supportsAcquireB || regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached require (regionType <= RegionType.UNCACHED || supportsAcquireB) // tracked, cached -> acquire require (regionType != RegionType.UNCACHED || supportsGet) // uncached -> supportsGet val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected") val maxTransfer = List( // Largest supported transfer of all types supportsAcquireT.max, supportsAcquireB.max, supportsArithmetic.max, supportsLogical.max, supportsGet.max, supportsPutFull.max, supportsPutPartial.max).max val maxAddress = address.map(_.max).max val minAlignment = address.map(_.alignment).min // The device had better not support a transfer larger than its alignment require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)") def toResource: ResourceAddress = { ResourceAddress(address, ResourcePermissions( r = supportsAcquireB || supportsGet, w = supportsAcquireT || supportsPutFull, x = executable, c = supportsAcquireB, a = supportsArithmetic && supportsLogical)) } def findTreeViolation() = nodePath.find { case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false case _: SinkNode[_, _, _, _, _] => false case node => node.inputs.size != 1 } def isTree = findTreeViolation() == None def infoString = { s"""Slave Name = ${name} |Slave Address = ${address} |supports = ${supports.infoString} | |""".stripMargin } def v1copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { new TLSlaveParameters( setName = setName, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = emits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: Option[String] = setName, address: Seq[AddressSet] = address, regionType: RegionType.T = regionType, executable: Boolean = executable, fifoId: Option[Int] = fifoId, supports: TLMasterToSlaveTransferSizes = supports, emits: TLSlaveToMasterTransferSizes = emits, alwaysGrantsT: Boolean = alwaysGrantsT, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } @deprecated("Use v1copy instead of copy","") def copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { v1copy( address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supportsAcquireT = supportsAcquireT, supportsAcquireB = supportsAcquireB, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } } object TLSlaveParameters { def v1( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = { new TLSlaveParameters( setName = None, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLSlaveToMasterTransferSizes.unknownEmits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2( address: Seq[AddressSet], nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Seq(), name: Option[String] = None, regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, fifoId: Option[Int] = None, supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports, emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits, alwaysGrantsT: Boolean = false, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } } object TLManagerParameters { @deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","") def apply( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = TLSlaveParameters.v1( address, resources, regionType, executable, nodePath, supportsAcquireT, supportsAcquireB, supportsArithmetic, supportsLogical, supportsGet, supportsPutFull, supportsPutPartial, supportsHint, mayDenyGet, mayDenyPut, alwaysGrantsT, fifoId, ) } case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int]) { def members = Seq(a, b, c, d) members.collect { case Some(beatBytes) => require (isPow2(beatBytes), "Data channel width must be a power of 2") } } object TLChannelBeatBytes{ def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes( Some(beatBytes), Some(beatBytes), Some(beatBytes), Some(beatBytes)) def apply(): TLChannelBeatBytes = TLChannelBeatBytes( None, None, None, None) } class TLSlavePortParameters private( val slaves: Seq[TLSlaveParameters], val channelBytes: TLChannelBeatBytes, val endSinkId: Int, val minLatency: Int, val responseFields: Seq[BundleFieldBase], val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct { def sortedSlaves = slaves.sortBy(_.sortedAddress.head) override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters] override def productPrefix = "TLSlavePortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => slaves case 1 => channelBytes case 2 => endSinkId case 3 => minLatency case 4 => responseFields case 5 => requestKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!slaves.isEmpty, "Slave ports must have slaves") require (endSinkId >= 0, "Sink ids cannot be negative") require (minLatency >= 0, "Minimum required latency cannot be negative") // Using this API implies you cannot handle mixed-width busses def beatBytes = { channelBytes.members.foreach { width => require (width.isDefined && width == channelBytes.a) } channelBytes.a.get } // TODO this should be deprecated def managers = slaves def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = { val relevant = slaves.filter(m => policy(m)) relevant.foreach { m => require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ") } } // Bounds on required sizes def maxAddress = slaves.map(_.maxAddress).max def maxTransfer = slaves.map(_.maxTransfer).max def mayDenyGet = slaves.exists(_.mayDenyGet) def mayDenyPut = slaves.exists(_.mayDenyPut) // Diplomatically determined operation sizes emitted by all outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _) // Operation Emitted by at least one outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _) val allSupportAcquireT = allSupportClaims.acquireT val allSupportAcquireB = allSupportClaims.acquireB val allSupportArithmetic = allSupportClaims.arithmetic val allSupportLogical = allSupportClaims.logical val allSupportGet = allSupportClaims.get val allSupportPutFull = allSupportClaims.putFull val allSupportPutPartial = allSupportClaims.putPartial val allSupportHint = allSupportClaims.hint // Operation supported by at least one outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _) val anySupportAcquireT = !anySupportClaims.acquireT.none val anySupportAcquireB = !anySupportClaims.acquireB.none val anySupportArithmetic = !anySupportClaims.arithmetic.none val anySupportLogical = !anySupportClaims.logical.none val anySupportGet = !anySupportClaims.get.none val anySupportPutFull = !anySupportClaims.putFull.none val anySupportPutPartial = !anySupportClaims.putPartial.none val anySupportHint = !anySupportClaims.hint.none // Supporting Acquire means being routable for GrantAck require ((endSinkId == 0) == !anySupportAcquireB) // These return Option[TLSlaveParameters] for your convenience def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address))) // The safe version will check the entire address def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ || _))) // The fast version assumes the address is valid (you probably want fastProperty instead of this function) def findFast(address: UInt) = { val routingMask = AddressDecoder(slaves.map(_.address)) VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ || _))) } // Compute the simplest AddressSets that decide a key def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = { val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) => k -> vs.flatMap(_._2) } val reductionMask = AddressDecoder(groups.map(_._2)) groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) } } // Select a property def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D = Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_||_), d(v)) }) // Note: returns the actual fifoId + 1 or 0 if None def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U) def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B) // Does this Port manage this ID/address? def containsSafe(address: UInt) = findSafe(address).reduce(_ || _) private def addressHelper( // setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity safe: Boolean, // member filters out the sizes being checked based on the opcode being emitted or supported member: TLSlaveParameters => TransferSizes, address: UInt, lgSize: UInt, // range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity range: Option[TransferSizes]): Bool = { // trim reduces circuit complexity by intersecting checked sizes with the range argument def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x) // groupBy returns an unordered map, convert back to Seq and sort the result for determinism // groupByIntoSeq is turning slaves into trimmed membership sizes // We are grouping all the slaves by their transfer size where // if they support the trimmed size then // member is the type of transfer that you are looking for (What you are trying to filter on) // When you consider membership, you are trimming the sizes to only the ones that you care about // you are filtering the slaves based on both whether they support a particular opcode and the size // Grouping the slaves based on the actual transfer size range they support // intersecting the range and checking their membership // FOR SUPPORTCASES instead of returning the list of slaves, // you are returning a map from transfer size to the set of // address sets that are supported for that transfer size // find all the slaves that support a certain type of operation and then group their addresses by the supported size // for every size there could be multiple address ranges // safety is a trade off between checking between all possible addresses vs only the addresses // that are known to have supported sizes // the trade off is 'checking all addresses is a more expensive circuit but will always give you // the right answer even if you give it an illegal address' // the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer // fast presumes address legality // This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies. // In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size. val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) => k -> vs.flatMap(_.address) } // safe produces a circuit that compares against all possible addresses, // whereas fast presumes that the address is legal but uses an efficient address decoder val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2)) // Simplified creates the most concise possible representation of each cases' address sets based on the mask. val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) } simplified.map { case (s, a) => // s is a size, you are checking for this size either the size of the operation is in s // We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire. ((Some(s) == range).B || s.containsLg(lgSize)) && a.map(_.contains(address)).reduce(_||_) }.foldLeft(false.B)(_||_) } def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range) def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range) def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range) def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range) def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range) def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range) def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range) def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range) def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range) def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range) def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range) def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range) def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range) def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range) def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range) def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range) def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range) def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range) def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range) def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range) def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range) def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range) def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range) def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption def isTree = !slaves.exists(!_.isTree) def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString def v1copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = managers, channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } def v2copy( slaves: Seq[TLSlaveParameters] = slaves, channelBytes: TLChannelBeatBytes = channelBytes, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = slaves, channelBytes = channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } @deprecated("Use v1copy instead of copy","") def copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { v1copy( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } object TLSlavePortParameters { def v1( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { new TLSlavePortParameters( slaves = managers, channelBytes = TLChannelBeatBytes(beatBytes), endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } } object TLManagerPortParameters { @deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","") def apply( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { TLSlavePortParameters.v1( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } class TLMasterParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], val name: String, val visibility: Seq[AddressSet], val unusedRegionTypes: Set[RegionType.T], val executesOnly: Boolean, val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C. val supports: TLSlaveToMasterTransferSizes, val emits: TLMasterToSlaveTransferSizes, val neverReleasesData: Boolean, val sourceId: IdRange) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters] override def productPrefix = "TLMasterParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 10 def productElement(n: Int): Any = n match { case 0 => name case 1 => sourceId case 2 => resources case 3 => visibility case 4 => unusedRegionTypes case 5 => executesOnly case 6 => requestFifo case 7 => supports case 8 => emits case 9 => neverReleasesData case _ => throw new IndexOutOfBoundsException(n.toString) } require (!sourceId.isEmpty) require (!visibility.isEmpty) require (supports.putFull.contains(supports.putPartial)) // We only support these operations if we support Probe (ie: we're a cache) require (supports.probe.contains(supports.arithmetic)) require (supports.probe.contains(supports.logical)) require (supports.probe.contains(supports.get)) require (supports.probe.contains(supports.putFull)) require (supports.probe.contains(supports.putPartial)) require (supports.probe.contains(supports.hint)) visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } val maxTransfer = List( supports.probe.max, supports.arithmetic.max, supports.logical.max, supports.get.max, supports.putFull.max, supports.putPartial.max).max def infoString = { s"""Master Name = ${name} |visibility = ${visibility} |emits = ${emits.infoString} |sourceId = ${sourceId} | |""".stripMargin } def v1copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { new TLMasterParameters( nodePath = nodePath, resources = this.resources, name = name, visibility = visibility, unusedRegionTypes = this.unusedRegionTypes, executesOnly = this.executesOnly, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = this.emits, neverReleasesData = this.neverReleasesData, sourceId = sourceId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: String = name, visibility: Seq[AddressSet] = visibility, unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes, executesOnly: Boolean = executesOnly, requestFifo: Boolean = requestFifo, supports: TLSlaveToMasterTransferSizes = supports, emits: TLMasterToSlaveTransferSizes = emits, neverReleasesData: Boolean = neverReleasesData, sourceId: IdRange = sourceId) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } @deprecated("Use v1copy instead of copy","") def copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { v1copy( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } object TLMasterParameters { def v1( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { new TLMasterParameters( nodePath = nodePath, resources = Nil, name = name, visibility = visibility, unusedRegionTypes = Set(), executesOnly = false, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData = false, sourceId = sourceId) } def v2( nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Nil, name: String, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), unusedRegionTypes: Set[RegionType.T] = Set(), executesOnly: Boolean = false, requestFifo: Boolean = false, supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports, emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData: Boolean = false, sourceId: IdRange = IdRange(0,1)) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } } object TLClientParameters { @deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","") def apply( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet.everything), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { TLMasterParameters.v1( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } class TLMasterPortParameters private( val masters: Seq[TLMasterParameters], val channelBytes: TLChannelBeatBytes, val minLatency: Int, val echoFields: Seq[BundleFieldBase], val requestFields: Seq[BundleFieldBase], val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters] override def productPrefix = "TLMasterPortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => masters case 1 => channelBytes case 2 => minLatency case 3 => echoFields case 4 => requestFields case 5 => responseKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!masters.isEmpty) require (minLatency >= 0) def clients = masters // Require disjoint ranges for Ids IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) => require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}") } // Bounds on required sizes def endSourceId = masters.map(_.sourceId.end).max def maxTransfer = masters.map(_.maxTransfer).max // The unused sources < endSourceId def unusedSources: Seq[Int] = { val usedSources = masters.map(_.sourceId).sortBy(_.start) ((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) => end until start } } // Diplomatically determined operation sizes emitted by all inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = masters.map(_.emits).reduce( _ intersect _) // Diplomatically determined operation sizes Emitted by at least one inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all inward Masters // as opposed to supports* which generate circuitry to check which specific addresses val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _) val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _) val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _) val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _) val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _) val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _) val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _) // Diplomatically determined operation sizes supported by at least one master // as opposed to supports* which generate circuitry to check which specific addresses val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ || _) val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ || _) val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ || _) val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ || _) val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ || _) val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ || _) val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ || _) // These return Option[TLMasterParameters] for your convenience def find(id: Int) = masters.find(_.sourceId.contains(id)) // Synthesizable lookup methods def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id))) def contains(id: UInt) = find(id).reduce(_ || _) def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B)) // Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = { val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _) // this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version; // the case where there is only one group. if (allSame) member(masters(0)).containsLg(lgSize) else { // Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize Mux1H(find(id), masters.map(member(_).containsLg(lgSize))) } } // Check for support of a given operation at a specific id val supportsProbe = sourceIdHelper(_.supports.probe) _ val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _ val supportsLogical = sourceIdHelper(_.supports.logical) _ val supportsGet = sourceIdHelper(_.supports.get) _ val supportsPutFull = sourceIdHelper(_.supports.putFull) _ val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _ val supportsHint = sourceIdHelper(_.supports.hint) _ // TODO: Merge sourceIdHelper2 with sourceIdHelper private def sourceIdHelper2( member: TLMasterParameters => TransferSizes, sourceId: UInt, lgSize: UInt): Bool = { // Because sourceIds are uniquely owned by each master, we use them to group the // cases that have to be checked. val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) => k -> vs.map(_.sourceId) } emitCases.map { case (s, a) => (s.containsLg(lgSize)) && a.map(_.contains(sourceId)).reduce(_||_) }.foldLeft(false.B)(_||_) } // Check for emit of a given operation at a specific id def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize) def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize) def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize) def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize) def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize) def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize) def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize) def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize) def infoString = masters.map(_.infoString).mkString def v1copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = clients, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2copy( masters: Seq[TLMasterParameters] = masters, channelBytes: TLChannelBeatBytes = channelBytes, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } @deprecated("Use v1copy instead of copy","") def copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { v1copy( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLClientPortParameters { @deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","") def apply( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { TLMasterPortParameters.v1( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLMasterPortParameters { def v1( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = clients, channelBytes = TLChannelBeatBytes(), minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2( masters: Seq[TLMasterParameters], channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(), minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } } case class TLBundleParameters( addressBits: Int, dataBits: Int, sourceBits: Int, sinkBits: Int, sizeBits: Int, echoFields: Seq[BundleFieldBase], requestFields: Seq[BundleFieldBase], responseFields: Seq[BundleFieldBase], hasBCE: Boolean) { // Chisel has issues with 0-width wires require (addressBits >= 1) require (dataBits >= 8) require (sourceBits >= 1) require (sinkBits >= 1) require (sizeBits >= 1) require (isPow2(dataBits)) echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") } val addrLoBits = log2Up(dataBits/8) // Used to uniquify bus IP names def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u") def union(x: TLBundleParameters) = TLBundleParameters( max(addressBits, x.addressBits), max(dataBits, x.dataBits), max(sourceBits, x.sourceBits), max(sinkBits, x.sinkBits), max(sizeBits, x.sizeBits), echoFields = BundleField.union(echoFields ++ x.echoFields), requestFields = BundleField.union(requestFields ++ x.requestFields), responseFields = BundleField.union(responseFields ++ x.responseFields), hasBCE || x.hasBCE) } object TLBundleParameters { val emptyBundleParams = TLBundleParameters( addressBits = 1, dataBits = 8, sourceBits = 1, sinkBits = 1, sizeBits = 1, echoFields = Nil, requestFields = Nil, responseFields = Nil, hasBCE = false) def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y)) def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) = new TLBundleParameters( addressBits = log2Up(slave.maxAddress + 1), dataBits = slave.beatBytes * 8, sourceBits = log2Up(master.endSourceId), sinkBits = log2Up(slave.endSinkId), sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1), echoFields = master.echoFields, requestFields = BundleField.accept(master.requestFields, slave.requestKeys), responseFields = BundleField.accept(slave.responseFields, master.responseKeys), hasBCE = master.anySupportProbe && slave.anySupportAcquireB) } case class TLEdgeParameters( master: TLMasterPortParameters, slave: TLSlavePortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { // legacy names: def manager = slave def client = master val maxTransfer = max(master.maxTransfer, slave.maxTransfer) val maxLgSize = log2Ceil(maxTransfer) // Sanity check the link... require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})") def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims) val bundle = TLBundleParameters(master, slave) def formatEdge = master.infoString + "\n" + slave.infoString } case class TLCreditedDelay( a: CreditedDelay, b: CreditedDelay, c: CreditedDelay, d: CreditedDelay, e: CreditedDelay) { def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay( a = a + that.a, b = b + that.b, c = c + that.c, d = d + that.d, e = e + that.e) override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})" } object TLCreditedDelay { def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay) } case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString} case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val delay = client.delay + manager.delay val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters) case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base)) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } // To be unified, devices must agree on all of these terms case class ManagerUnificationKey( resources: Seq[Resource], regionType: RegionType.T, executable: Boolean, supportsAcquireT: TransferSizes, supportsAcquireB: TransferSizes, supportsArithmetic: TransferSizes, supportsLogical: TransferSizes, supportsGet: TransferSizes, supportsPutFull: TransferSizes, supportsPutPartial: TransferSizes, supportsHint: TransferSizes) object ManagerUnificationKey { def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey( resources = x.resources, regionType = x.regionType, executable = x.executable, supportsAcquireT = x.supportsAcquireT, supportsAcquireB = x.supportsAcquireB, supportsArithmetic = x.supportsArithmetic, supportsLogical = x.supportsLogical, supportsGet = x.supportsGet, supportsPutFull = x.supportsPutFull, supportsPutPartial = x.supportsPutPartial, supportsHint = x.supportsHint) } object ManagerUnification { def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = { slaves.groupBy(ManagerUnificationKey.apply).values.map { seq => val agree = seq.forall(_.fifoId == seq.head.fifoId) seq(0).v1copy( address = AddressSet.unify(seq.flatMap(_.address)), fifoId = if (agree) seq(0).fifoId else None) }.toList } } case class TLBufferParams( a: BufferParams = BufferParams.none, b: BufferParams = BufferParams.none, c: BufferParams = BufferParams.none, d: BufferParams = BufferParams.none, e: BufferParams = BufferParams.none ) extends DirectedBuffers[TLBufferParams] { def copyIn(x: BufferParams) = this.copy(b = x, d = x) def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x) def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x) } /** Pretty printing of TL source id maps */ class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] { private val tlDigits = String.valueOf(tl.endSourceId-1).length() protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s" private val sorted = tl.masters.sortBy(_.sourceId) val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c => TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo) } } case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean) extends IdMapEntry { val from = tlId val to = tlId val maxTransactionsInFlight = Some(tlId.size) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module ShuttleDCacheMSHR_3( // @[MSHR.scala:12:7] input clock, // @[MSHR.scala:12:7] input reset, // @[MSHR.scala:12:7] input io_req_pri_val, // @[MSHR.scala:13:14] output io_req_pri_rdy, // @[MSHR.scala:13:14] input io_req_sec_val, // @[MSHR.scala:13:14] output io_req_sec_rdy, // @[MSHR.scala:13:14] input [39:0] io_req_bits_addr, // @[MSHR.scala:13:14] input [6:0] io_req_bits_tag, // @[MSHR.scala:13:14] input [4:0] io_req_bits_cmd, // @[MSHR.scala:13:14] input [1:0] io_req_bits_size, // @[MSHR.scala:13:14] input io_req_bits_signed, // @[MSHR.scala:13:14] input [63:0] io_req_bits_data, // @[MSHR.scala:13:14] input [7:0] io_req_bits_mask, // @[MSHR.scala:13:14] input io_req_bits_tag_match, // @[MSHR.scala:13:14] input [1:0] io_req_bits_old_meta_coh_state, // @[MSHR.scala:13:14] input [19:0] io_req_bits_old_meta_tag, // @[MSHR.scala:13:14] input [3:0] io_req_bits_way_en, // @[MSHR.scala:13:14] input [4:0] io_req_bits_sdq_id, // @[MSHR.scala:13:14] input [31:0] io_probe_addr, // @[MSHR.scala:13:14] output io_idx_match, // @[MSHR.scala:13:14] output [19:0] io_tag, // @[MSHR.scala:13:14] input io_mem_acquire_ready, // @[MSHR.scala:13:14] output io_mem_acquire_valid, // @[MSHR.scala:13:14] output [2:0] io_mem_acquire_bits_param, // @[MSHR.scala:13:14] output [31:0] io_mem_acquire_bits_address, // @[MSHR.scala:13:14] input io_mem_grant_valid, // @[MSHR.scala:13:14] input [2:0] io_mem_grant_bits_opcode, // @[MSHR.scala:13:14] input [1:0] io_mem_grant_bits_param, // @[MSHR.scala:13:14] input [3:0] io_mem_grant_bits_size, // @[MSHR.scala:13:14] input [2:0] io_mem_grant_bits_source, // @[MSHR.scala:13:14] input [2:0] io_mem_grant_bits_sink, // @[MSHR.scala:13:14] input io_mem_grant_bits_denied, // @[MSHR.scala:13:14] input [63:0] io_mem_grant_bits_data, // @[MSHR.scala:13:14] input io_mem_grant_bits_corrupt, // @[MSHR.scala:13:14] input io_mem_finish_ready, // @[MSHR.scala:13:14] output io_mem_finish_valid, // @[MSHR.scala:13:14] output [2:0] io_mem_finish_bits_sink, // @[MSHR.scala:13:14] output [3:0] io_refill_way_en, // @[MSHR.scala:13:14] output [11:0] io_refill_addr, // @[MSHR.scala:13:14] input io_meta_write_ready, // @[MSHR.scala:13:14] output io_meta_write_valid, // @[MSHR.scala:13:14] output [5:0] io_meta_write_bits_idx, // @[MSHR.scala:13:14] output [3:0] io_meta_write_bits_way_en, // @[MSHR.scala:13:14] output [19:0] io_meta_write_bits_tag, // @[MSHR.scala:13:14] output [1:0] io_meta_write_bits_data_coh_state, // @[MSHR.scala:13:14] output [19:0] io_meta_write_bits_data_tag, // @[MSHR.scala:13:14] input io_replay_ready, // @[MSHR.scala:13:14] output io_replay_valid, // @[MSHR.scala:13:14] output [39:0] io_replay_bits_addr, // @[MSHR.scala:13:14] output [6:0] io_replay_bits_tag, // @[MSHR.scala:13:14] output [4:0] io_replay_bits_cmd, // @[MSHR.scala:13:14] output [1:0] io_replay_bits_size, // @[MSHR.scala:13:14] output io_replay_bits_signed, // @[MSHR.scala:13:14] output [63:0] io_replay_bits_data, // @[MSHR.scala:13:14] output [7:0] io_replay_bits_mask, // @[MSHR.scala:13:14] output io_replay_bits_tag_match, // @[MSHR.scala:13:14] output [1:0] io_replay_bits_old_meta_coh_state, // @[MSHR.scala:13:14] output [19:0] io_replay_bits_old_meta_tag, // @[MSHR.scala:13:14] output [3:0] io_replay_bits_way_en, // @[MSHR.scala:13:14] output [4:0] io_replay_bits_sdq_id, // @[MSHR.scala:13:14] input io_wb_req_ready, // @[MSHR.scala:13:14] output io_wb_req_valid, // @[MSHR.scala:13:14] output [19:0] io_wb_req_bits_tag, // @[MSHR.scala:13:14] output [5:0] io_wb_req_bits_idx, // @[MSHR.scala:13:14] output [2:0] io_wb_req_bits_param, // @[MSHR.scala:13:14] output [3:0] io_wb_req_bits_way_en, // @[MSHR.scala:13:14] output io_probe_rdy // @[MSHR.scala:13:14] ); wire [19:0] io_tag_0; // @[MSHR.scala:12:7] wire _grantackq_io_enq_ready; // @[MSHR.scala:126:25] wire _grantackq_io_deq_valid; // @[MSHR.scala:126:25] wire _rpq_io_enq_ready; // @[MSHR.scala:63:19] wire _rpq_io_deq_valid; // @[MSHR.scala:63:19] wire [39:0] _rpq_io_deq_bits_addr; // @[MSHR.scala:63:19] wire io_req_pri_val_0 = io_req_pri_val; // @[MSHR.scala:12:7] wire io_req_sec_val_0 = io_req_sec_val; // @[MSHR.scala:12:7] wire [39:0] io_req_bits_addr_0 = io_req_bits_addr; // @[MSHR.scala:12:7] wire [6:0] io_req_bits_tag_0 = io_req_bits_tag; // @[MSHR.scala:12:7] wire [4:0] io_req_bits_cmd_0 = io_req_bits_cmd; // @[MSHR.scala:12:7] wire [1:0] io_req_bits_size_0 = io_req_bits_size; // @[MSHR.scala:12:7] wire io_req_bits_signed_0 = io_req_bits_signed; // @[MSHR.scala:12:7] wire [63:0] io_req_bits_data_0 = io_req_bits_data; // @[MSHR.scala:12:7] wire [7:0] io_req_bits_mask_0 = io_req_bits_mask; // @[MSHR.scala:12:7] wire io_req_bits_tag_match_0 = io_req_bits_tag_match; // @[MSHR.scala:12:7] wire [1:0] io_req_bits_old_meta_coh_state_0 = io_req_bits_old_meta_coh_state; // @[MSHR.scala:12:7] wire [19:0] io_req_bits_old_meta_tag_0 = io_req_bits_old_meta_tag; // @[MSHR.scala:12:7] wire [3:0] io_req_bits_way_en_0 = io_req_bits_way_en; // @[MSHR.scala:12:7] wire [4:0] io_req_bits_sdq_id_0 = io_req_bits_sdq_id; // @[MSHR.scala:12:7] wire [31:0] io_probe_addr_0 = io_probe_addr; // @[MSHR.scala:12:7] wire io_mem_acquire_ready_0 = io_mem_acquire_ready; // @[MSHR.scala:12:7] wire io_mem_grant_valid_0 = io_mem_grant_valid; // @[MSHR.scala:12:7] wire [2:0] io_mem_grant_bits_opcode_0 = io_mem_grant_bits_opcode; // @[MSHR.scala:12:7] wire [1:0] io_mem_grant_bits_param_0 = io_mem_grant_bits_param; // @[MSHR.scala:12:7] wire [3:0] io_mem_grant_bits_size_0 = io_mem_grant_bits_size; // @[MSHR.scala:12:7] wire [2:0] io_mem_grant_bits_source_0 = io_mem_grant_bits_source; // @[MSHR.scala:12:7] wire [2:0] io_mem_grant_bits_sink_0 = io_mem_grant_bits_sink; // @[MSHR.scala:12:7] wire io_mem_grant_bits_denied_0 = io_mem_grant_bits_denied; // @[MSHR.scala:12:7] wire [63:0] io_mem_grant_bits_data_0 = io_mem_grant_bits_data; // @[MSHR.scala:12:7] wire io_mem_grant_bits_corrupt_0 = io_mem_grant_bits_corrupt; // @[MSHR.scala:12:7] wire io_mem_finish_ready_0 = io_mem_finish_ready; // @[MSHR.scala:12:7] wire io_meta_write_ready_0 = io_meta_write_ready; // @[MSHR.scala:12:7] wire io_replay_ready_0 = io_replay_ready; // @[MSHR.scala:12:7] wire io_wb_req_ready_0 = io_wb_req_ready; // @[MSHR.scala:12:7] wire [1:0] _grow_param_r_T_7 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _grow_param_r_T_9 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _grow_param_r_T_17 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _grow_param_r_T_19 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _coh_on_grant_T_5 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r1_T_7 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r1_T_9 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r1_T_17 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r1_T_19 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r2_T_7 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r2_T_9 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r2_T_17 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r2_T_19 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_71 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_73 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_81 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_83 = 2'h1; // @[Metadata.scala:25:15] wire [3:0] _r_T_15 = 4'hB; // @[Metadata.scala:130:10] wire [3:0] _needs_wb_r_T_15 = 4'hB; // @[Metadata.scala:130:10] wire [3:0] _r_T_16 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _needs_wb_r_T_16 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _r_T_17 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _needs_wb_r_T_17 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _r_T_18 = 4'h8; // @[Metadata.scala:133:10] wire [3:0] _needs_wb_r_T_18 = 4'h8; // @[Metadata.scala:133:10] wire [3:0] _r_T_7 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _grow_param_r_T_2 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _r1_T_2 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _r2_T_2 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _needs_wb_r_T_7 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _r_T_66 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _r_T_8 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _grow_param_r_T_4 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _r1_T_4 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _r2_T_4 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _needs_wb_r_T_8 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _r_T_68 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _r_T_9 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _grow_param_r_T_6 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _coh_on_grant_T_2 = 4'h1; // @[Metadata.scala:86:10] wire [3:0] _r1_T_6 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _r2_T_6 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _needs_wb_r_T_9 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _r_T_70 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _r_T_11 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _grow_param_r_T_8 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _r1_T_8 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _r2_T_8 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _needs_wb_r_T_11 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _r_T_72 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _grow_param_r_T_14 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _r1_T_14 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _r2_T_14 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _r_T_78 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _r_T_10 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _grow_param_r_T_16 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _coh_on_grant_T_4 = 4'h0; // @[Metadata.scala:87:10] wire [3:0] _r1_T_16 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _r2_T_16 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _needs_wb_r_T_10 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _r_T_80 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _r_T_13 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] _grow_param_r_T_18 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _r1_T_18 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _r2_T_18 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _needs_wb_r_T_13 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] _r_T_82 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _grow_param_r_T_22 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r1_T_22 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r2_T_22 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r_T_86 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _grow_param_r_T_24 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _coh_on_grant_T_8 = 4'hC; // @[Metadata.scala:89:10] wire [3:0] _r1_T_24 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _r2_T_24 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _r_T_88 = 4'hC; // @[Metadata.scala:72:10] wire [1:0] new_coh_meta_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] _r_T_22 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_26 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_30 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_34 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_38 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _grow_param_r_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _grow_param_r_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _grow_param_r_T_5 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _grow_param_r_T_15 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _coh_on_grant_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _coh_on_grant_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r1_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r1_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r1_T_5 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r1_T_15 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r2_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r2_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r2_T_5 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r2_T_15 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _needs_wb_r_T_22 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _needs_wb_r_T_26 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _needs_wb_r_T_30 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _needs_wb_r_T_34 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _needs_wb_r_T_38 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_65 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_67 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_69 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_79 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] new_coh_meta_1_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] _r_T_1 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _r_T_3 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _r_T_5 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _needs_wb_r_T_1 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _needs_wb_r_T_3 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _needs_wb_r_T_5 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] io_mem_acquire_bits_a_mask_sizeOH_shiftAmount = 2'h2; // @[OneHot.scala:64:49] wire [3:0] _r_T_14 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _grow_param_r_T_20 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _coh_on_grant_T_6 = 4'h4; // @[Metadata.scala:88:10] wire [3:0] _r1_T_20 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _r2_T_20 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _needs_wb_r_T_14 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _r_T_84 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _io_mem_acquire_bits_a_mask_sizeOH_T_1 = 4'h4; // @[OneHot.scala:65:12] wire [2:0] _io_mem_acquire_bits_a_mask_sizeOH_T_2 = 3'h4; // @[OneHot.scala:65:27] wire [2:0] io_mem_acquire_bits_a_mask_sizeOH = 3'h5; // @[Misc.scala:202:81] wire [1:0] _grow_param_r_T_11 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _grow_param_r_T_13 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _grow_param_r_T_21 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _grow_param_r_T_23 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _coh_on_grant_T_7 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r1_T_11 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r1_T_13 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r1_T_21 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r1_T_23 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r2_T_11 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r2_T_13 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r2_T_21 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r2_T_23 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _dirties_T = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_75 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_77 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_85 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_87 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] io_mem_acquire_bits_a_mask_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [3:0] _grow_param_r_T_12 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _r1_T_12 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _r2_T_12 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _r_T_76 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] io_mem_acquire_bits_a_mask_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] io_mem_acquire_bits_a_mask_hi = 4'hF; // @[Misc.scala:222:10] wire io_wb_req_bits_voluntary = 1'h1; // @[MSHR.scala:12:7] wire _r_T = 1'h1; // @[Metadata.scala:140:24] wire _needs_wb_r_T = 1'h1; // @[Metadata.scala:140:24] wire _io_mem_acquire_bits_legal_T_19 = 1'h1; // @[Parameters.scala:91:44] wire _io_mem_acquire_bits_legal_T_20 = 1'h1; // @[Parameters.scala:684:29] wire io_mem_acquire_bits_a_mask_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire io_mem_acquire_bits_a_mask_sub_sub_size = 1'h1; // @[Misc.scala:209:26] wire io_mem_acquire_bits_a_mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_2_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_3_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_size = 1'h1; // @[Misc.scala:209:26] wire io_mem_acquire_bits_a_mask_acc = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_4 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_5 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_6 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_7 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_corrupt = 1'h0; // @[MSHR.scala:12:7] wire _r_T_2 = 1'h0; // @[Metadata.scala:140:24] wire _r_T_4 = 1'h0; // @[Metadata.scala:140:24] wire _r_T_20 = 1'h0; // @[Misc.scala:38:9] wire _r_T_24 = 1'h0; // @[Misc.scala:38:9] wire _r_T_28 = 1'h0; // @[Misc.scala:38:9] wire _grow_param_r_T_26 = 1'h0; // @[Misc.scala:35:9] wire _grow_param_r_T_29 = 1'h0; // @[Misc.scala:35:9] wire _grow_param_r_T_32 = 1'h0; // @[Misc.scala:35:9] wire _grow_param_r_T_35 = 1'h0; // @[Misc.scala:35:9] wire _grow_param_r_T_38 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_26 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_29 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_32 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_35 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_38 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_26 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_29 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_32 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_35 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_38 = 1'h0; // @[Misc.scala:35:9] wire _needs_wb_r_T_2 = 1'h0; // @[Metadata.scala:140:24] wire _needs_wb_r_T_4 = 1'h0; // @[Metadata.scala:140:24] wire _needs_wb_r_T_20 = 1'h0; // @[Misc.scala:38:9] wire _needs_wb_r_T_24 = 1'h0; // @[Misc.scala:38:9] wire _needs_wb_r_T_28 = 1'h0; // @[Misc.scala:38:9] wire _r_T_90 = 1'h0; // @[Misc.scala:35:9] wire _r_T_93 = 1'h0; // @[Misc.scala:35:9] wire _r_T_96 = 1'h0; // @[Misc.scala:35:9] wire _r_T_99 = 1'h0; // @[Misc.scala:35:9] wire _r_T_102 = 1'h0; // @[Misc.scala:35:9] wire _io_mem_acquire_bits_legal_T = 1'h0; // @[Parameters.scala:684:29] wire _io_mem_acquire_bits_legal_T_18 = 1'h0; // @[Parameters.scala:684:54] wire _io_mem_acquire_bits_legal_T_33 = 1'h0; // @[Parameters.scala:686:26] wire io_mem_acquire_bits_a_corrupt = 1'h0; // @[Edges.scala:346:17] wire io_mem_acquire_bits_a_mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _io_mem_acquire_bits_a_mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire [63:0] io_mem_acquire_bits_data = 64'h0; // @[MSHR.scala:12:7] wire [63:0] io_mem_acquire_bits_a_data = 64'h0; // @[Edges.scala:346:17] wire [7:0] io_mem_acquire_bits_mask = 8'hFF; // @[MSHR.scala:12:7, :13:14] wire [7:0] io_mem_acquire_bits_a_mask = 8'hFF; // @[MSHR.scala:12:7, :13:14] wire [7:0] _io_mem_acquire_bits_a_mask_T = 8'hFF; // @[MSHR.scala:12:7, :13:14] wire [2:0] io_mem_acquire_bits_source = 3'h3; // @[MSHR.scala:12:7] wire [2:0] io_wb_req_bits_source = 3'h3; // @[MSHR.scala:12:7] wire [2:0] io_mem_acquire_bits_a_source = 3'h3; // @[Edges.scala:346:17] wire [3:0] io_mem_acquire_bits_size = 4'h6; // @[MSHR.scala:12:7] wire [3:0] _r_T_12 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] _grow_param_r_T_10 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _r1_T_10 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _r2_T_10 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _needs_wb_r_T_12 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] _r_T_74 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] io_mem_acquire_bits_a_size = 4'h6; // @[Edges.scala:346:17] wire [2:0] io_mem_acquire_bits_opcode = 3'h6; // @[MSHR.scala:12:7] wire [2:0] io_mem_acquire_bits_a_opcode = 3'h6; // @[Edges.scala:346:17] wire [2:0] _io_mem_acquire_bits_a_mask_sizeOH_T = 3'h6; // @[Misc.scala:202:34] wire _io_req_pri_rdy_T; // @[MSHR.scala:138:27] wire _io_req_sec_rdy_T; // @[MSHR.scala:139:29] wire _io_idx_match_T_1; // @[MSHR.scala:134:41] wire [19:0] io_meta_write_bits_tag_0 = io_tag_0; // @[MSHR.scala:12:7] wire [19:0] io_meta_write_bits_data_tag_0 = io_tag_0; // @[MSHR.scala:12:7] wire _io_mem_acquire_valid_T_1; // @[MSHR.scala:161:50] wire [2:0] io_mem_acquire_bits_a_param; // @[Edges.scala:346:17] wire [31:0] io_mem_acquire_bits_a_address; // @[Edges.scala:346:17] wire [2:0] grantackq_io_enq_bits_e_sink = io_mem_grant_bits_sink_0; // @[MSHR.scala:12:7] wire _io_mem_finish_valid_T; // @[MSHR.scala:130:49] wire _io_meta_write_valid_T_2; // @[package.scala:81:59] wire [5:0] req_idx; // @[MSHR.scala:39:25] wire [1:0] _io_meta_write_bits_data_coh_T_1_state; // @[MSHR.scala:149:37] wire _io_replay_valid_T_1; // @[MSHR.scala:168:44] wire _io_wb_req_valid_T; // @[MSHR.scala:153:28] wire [2:0] shrink_param; // @[Misc.scala:38:36] wire _io_probe_rdy_T_11; // @[MSHR.scala:144:61] wire [2:0] io_mem_acquire_bits_param_0; // @[MSHR.scala:12:7] wire [31:0] io_mem_acquire_bits_address_0; // @[MSHR.scala:12:7] wire io_mem_acquire_valid_0; // @[MSHR.scala:12:7] wire [2:0] io_mem_finish_bits_sink_0; // @[MSHR.scala:12:7] wire io_mem_finish_valid_0; // @[MSHR.scala:12:7] wire [3:0] io_refill_way_en_0; // @[MSHR.scala:12:7] wire [11:0] io_refill_addr_0; // @[MSHR.scala:12:7] wire [1:0] io_meta_write_bits_data_coh_state_0; // @[MSHR.scala:12:7] wire [5:0] io_meta_write_bits_idx_0; // @[MSHR.scala:12:7] wire [3:0] io_meta_write_bits_way_en_0; // @[MSHR.scala:12:7] wire io_meta_write_valid_0; // @[MSHR.scala:12:7] wire [1:0] io_replay_bits_old_meta_coh_state_0; // @[MSHR.scala:12:7] wire [19:0] io_replay_bits_old_meta_tag_0; // @[MSHR.scala:12:7] wire [39:0] io_replay_bits_addr_0; // @[MSHR.scala:12:7] wire [6:0] io_replay_bits_tag_0; // @[MSHR.scala:12:7] wire [4:0] io_replay_bits_cmd_0; // @[MSHR.scala:12:7] wire [1:0] io_replay_bits_size_0; // @[MSHR.scala:12:7] wire io_replay_bits_signed_0; // @[MSHR.scala:12:7] wire [63:0] io_replay_bits_data_0; // @[MSHR.scala:12:7] wire [7:0] io_replay_bits_mask_0; // @[MSHR.scala:12:7] wire io_replay_bits_tag_match_0; // @[MSHR.scala:12:7] wire [3:0] io_replay_bits_way_en_0; // @[MSHR.scala:12:7] wire [4:0] io_replay_bits_sdq_id_0; // @[MSHR.scala:12:7] wire io_replay_valid_0; // @[MSHR.scala:12:7] wire [19:0] io_wb_req_bits_tag_0; // @[MSHR.scala:12:7] wire [5:0] io_wb_req_bits_idx_0; // @[MSHR.scala:12:7] wire [2:0] io_wb_req_bits_param_0; // @[MSHR.scala:12:7] wire [3:0] io_wb_req_bits_way_en_0; // @[MSHR.scala:12:7] wire io_wb_req_valid_0; // @[MSHR.scala:12:7] wire io_req_pri_rdy_0; // @[MSHR.scala:12:7] wire io_req_sec_rdy_0; // @[MSHR.scala:12:7] wire io_idx_match_0; // @[MSHR.scala:12:7] wire io_probe_rdy_0; // @[MSHR.scala:12:7] reg [3:0] state; // @[MSHR.scala:36:22] reg [39:0] req_addr; // @[MSHR.scala:38:16] reg [6:0] req_tag; // @[MSHR.scala:38:16] reg [4:0] req_cmd; // @[MSHR.scala:38:16] reg [1:0] req_size; // @[MSHR.scala:38:16] reg req_signed; // @[MSHR.scala:38:16] reg [63:0] req_data; // @[MSHR.scala:38:16] reg [7:0] req_mask; // @[MSHR.scala:38:16] reg req_tag_match; // @[MSHR.scala:38:16] reg [1:0] req_old_meta_coh_state; // @[MSHR.scala:38:16] reg [19:0] req_old_meta_tag; // @[MSHR.scala:38:16] assign io_wb_req_bits_tag_0 = req_old_meta_tag; // @[MSHR.scala:12:7, :38:16] reg [3:0] req_way_en; // @[MSHR.scala:38:16] assign io_refill_way_en_0 = req_way_en; // @[MSHR.scala:12:7, :38:16] assign io_meta_write_bits_way_en_0 = req_way_en; // @[MSHR.scala:12:7, :38:16] assign io_wb_req_bits_way_en_0 = req_way_en; // @[MSHR.scala:12:7, :38:16] reg [4:0] req_sdq_id; // @[MSHR.scala:38:16] assign req_idx = req_addr[11:6]; // @[MSHR.scala:38:16, :39:25] assign io_meta_write_bits_idx_0 = req_idx; // @[MSHR.scala:12:7, :39:25] assign io_wb_req_bits_idx_0 = req_idx; // @[MSHR.scala:12:7, :39:25] wire [27:0] req_tag_0 = req_addr[39:12]; // @[MSHR.scala:38:16, :40:26] wire [33:0] _req_block_addr_T = req_addr[39:6]; // @[MSHR.scala:38:16, :41:34] wire [39:0] req_block_addr = {_req_block_addr_T, 6'h0}; // @[MSHR.scala:41:{34,51}] wire [5:0] _idx_match_T = io_req_bits_addr_0[11:6]; // @[MSHR.scala:12:7, :42:47] wire idx_match = req_idx == _idx_match_T; // @[MSHR.scala:39:25, :42:{27,47}] wire [5:0] _probe_idx_match_T = io_probe_addr_0[11:6]; // @[MSHR.scala:12:7, :43:50] wire probe_idx_match = req_idx == _probe_idx_match_T; // @[MSHR.scala:39:25, :43:{33,50}] reg [1:0] new_coh_state; // @[MSHR.scala:45:24] wire [3:0] _r_T_6 = {2'h2, req_old_meta_coh_state}; // @[MSHR.scala:38:16] wire _r_T_19 = _r_T_6 == 4'h8; // @[Misc.scala:56:20] wire [2:0] _r_T_21 = _r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _r_T_23 = _r_T_6 == 4'h9; // @[Misc.scala:56:20] wire [2:0] _r_T_25 = _r_T_23 ? 3'h2 : _r_T_21; // @[Misc.scala:38:36, :56:20] wire _r_T_27 = _r_T_6 == 4'hA; // @[Misc.scala:56:20] wire [2:0] _r_T_29 = _r_T_27 ? 3'h1 : _r_T_25; // @[MSHR.scala:142:59] wire _r_T_31 = _r_T_6 == 4'hB; // @[Misc.scala:56:20] wire _r_T_32 = _r_T_31; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_33 = _r_T_31 ? 3'h1 : _r_T_29; // @[MSHR.scala:142:59] wire _r_T_35 = _r_T_6 == 4'h4; // @[Misc.scala:56:20] wire _r_T_36 = ~_r_T_35 & _r_T_32; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_37 = _r_T_35 ? 3'h5 : _r_T_33; // @[Misc.scala:38:36, :56:20] wire _r_T_39 = _r_T_6 == 4'h5; // @[Misc.scala:56:20] wire _r_T_40 = ~_r_T_39 & _r_T_36; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_41 = _r_T_39 ? 3'h4 : _r_T_37; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_42 = {1'h0, _r_T_39}; // @[Misc.scala:38:63, :56:20] wire _r_T_43 = _r_T_6 == 4'h6; // @[Misc.scala:56:20] wire _r_T_44 = ~_r_T_43 & _r_T_40; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_45 = _r_T_43 ? 3'h0 : _r_T_41; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_46 = _r_T_43 ? 2'h1 : _r_T_42; // @[Misc.scala:38:63, :56:20] wire _r_T_47 = _r_T_6 == 4'h7; // @[Misc.scala:56:20] wire _r_T_48 = _r_T_47 | _r_T_44; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_49 = _r_T_47 ? 3'h0 : _r_T_45; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_50 = _r_T_47 ? 2'h1 : _r_T_46; // @[Misc.scala:38:63, :56:20] wire _r_T_51 = _r_T_6 == 4'h0; // @[Misc.scala:56:20] wire _r_T_52 = ~_r_T_51 & _r_T_48; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_53 = _r_T_51 ? 3'h5 : _r_T_49; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_54 = _r_T_51 ? 2'h0 : _r_T_50; // @[Misc.scala:38:63, :56:20] wire _r_T_55 = _r_T_6 == 4'h1; // @[Misc.scala:56:20] wire _r_T_56 = ~_r_T_55 & _r_T_52; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_57 = _r_T_55 ? 3'h4 : _r_T_53; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_58 = _r_T_55 ? 2'h1 : _r_T_54; // @[Misc.scala:38:63, :56:20] wire _r_T_59 = _r_T_6 == 4'h2; // @[Misc.scala:56:20] wire _r_T_60 = ~_r_T_59 & _r_T_56; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_61 = _r_T_59 ? 3'h3 : _r_T_57; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_62 = _r_T_59 ? 2'h2 : _r_T_58; // @[Misc.scala:38:63, :56:20] wire _r_T_63 = _r_T_6 == 4'h3; // @[Misc.scala:56:20] wire r_1 = _r_T_63 | _r_T_60; // @[Misc.scala:38:9, :56:20] assign shrink_param = _r_T_63 ? 3'h3 : _r_T_61; // @[Misc.scala:38:36, :56:20] assign io_wb_req_bits_param_0 = shrink_param; // @[MSHR.scala:12:7] wire [1:0] r_3 = _r_T_63 ? 2'h2 : _r_T_62; // @[Misc.scala:38:63, :56:20] wire [1:0] coh_on_clear_state = r_3; // @[Misc.scala:38:63] wire _GEN = req_cmd == 5'h1; // @[MSHR.scala:38:16] wire _grow_param_r_c_cat_T; // @[Consts.scala:90:32] assign _grow_param_r_c_cat_T = _GEN; // @[Consts.scala:90:32] wire _grow_param_r_c_cat_T_23; // @[Consts.scala:90:32] assign _grow_param_r_c_cat_T_23 = _GEN; // @[Consts.scala:90:32] wire _coh_on_grant_c_cat_T; // @[Consts.scala:90:32] assign _coh_on_grant_c_cat_T = _GEN; // @[Consts.scala:90:32] wire _coh_on_grant_c_cat_T_23; // @[Consts.scala:90:32] assign _coh_on_grant_c_cat_T_23 = _GEN; // @[Consts.scala:90:32] wire _r1_c_cat_T; // @[Consts.scala:90:32] assign _r1_c_cat_T = _GEN; // @[Consts.scala:90:32] wire _r1_c_cat_T_23; // @[Consts.scala:90:32] assign _r1_c_cat_T_23 = _GEN; // @[Consts.scala:90:32] wire _needs_second_acq_T_27; // @[Consts.scala:90:32] assign _needs_second_acq_T_27 = _GEN; // @[Consts.scala:90:32] wire _GEN_0 = req_cmd == 5'h11; // @[MSHR.scala:38:16] wire _grow_param_r_c_cat_T_1; // @[Consts.scala:90:49] assign _grow_param_r_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49] wire _grow_param_r_c_cat_T_24; // @[Consts.scala:90:49] assign _grow_param_r_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49] wire _coh_on_grant_c_cat_T_1; // @[Consts.scala:90:49] assign _coh_on_grant_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49] wire _coh_on_grant_c_cat_T_24; // @[Consts.scala:90:49] assign _coh_on_grant_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49] wire _r1_c_cat_T_1; // @[Consts.scala:90:49] assign _r1_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49] wire _r1_c_cat_T_24; // @[Consts.scala:90:49] assign _r1_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49] wire _needs_second_acq_T_28; // @[Consts.scala:90:49] assign _needs_second_acq_T_28 = _GEN_0; // @[Consts.scala:90:49] wire _grow_param_r_c_cat_T_2 = _grow_param_r_c_cat_T | _grow_param_r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _GEN_1 = req_cmd == 5'h7; // @[MSHR.scala:38:16] wire _grow_param_r_c_cat_T_3; // @[Consts.scala:90:66] assign _grow_param_r_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66] wire _grow_param_r_c_cat_T_26; // @[Consts.scala:90:66] assign _grow_param_r_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66] wire _coh_on_grant_c_cat_T_3; // @[Consts.scala:90:66] assign _coh_on_grant_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66] wire _coh_on_grant_c_cat_T_26; // @[Consts.scala:90:66] assign _coh_on_grant_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66] wire _r1_c_cat_T_3; // @[Consts.scala:90:66] assign _r1_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66] wire _r1_c_cat_T_26; // @[Consts.scala:90:66] assign _r1_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66] wire _needs_second_acq_T_30; // @[Consts.scala:90:66] assign _needs_second_acq_T_30 = _GEN_1; // @[Consts.scala:90:66] wire _grow_param_r_c_cat_T_4 = _grow_param_r_c_cat_T_2 | _grow_param_r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _GEN_2 = req_cmd == 5'h4; // @[MSHR.scala:38:16] wire _grow_param_r_c_cat_T_5; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_5 = _GEN_2; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_28; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_28 = _GEN_2; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_5; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_5 = _GEN_2; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_28; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_28 = _GEN_2; // @[package.scala:16:47] wire _r1_c_cat_T_5; // @[package.scala:16:47] assign _r1_c_cat_T_5 = _GEN_2; // @[package.scala:16:47] wire _r1_c_cat_T_28; // @[package.scala:16:47] assign _r1_c_cat_T_28 = _GEN_2; // @[package.scala:16:47] wire _needs_second_acq_T_32; // @[package.scala:16:47] assign _needs_second_acq_T_32 = _GEN_2; // @[package.scala:16:47] wire _GEN_3 = req_cmd == 5'h9; // @[MSHR.scala:38:16] wire _grow_param_r_c_cat_T_6; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_6 = _GEN_3; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_29; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_29 = _GEN_3; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_6; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_6 = _GEN_3; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_29; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_29 = _GEN_3; // @[package.scala:16:47] wire _r1_c_cat_T_6; // @[package.scala:16:47] assign _r1_c_cat_T_6 = _GEN_3; // @[package.scala:16:47] wire _r1_c_cat_T_29; // @[package.scala:16:47] assign _r1_c_cat_T_29 = _GEN_3; // @[package.scala:16:47] wire _needs_second_acq_T_33; // @[package.scala:16:47] assign _needs_second_acq_T_33 = _GEN_3; // @[package.scala:16:47] wire _GEN_4 = req_cmd == 5'hA; // @[MSHR.scala:38:16] wire _grow_param_r_c_cat_T_7; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_7 = _GEN_4; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_30; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_30 = _GEN_4; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_7; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_7 = _GEN_4; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_30; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_30 = _GEN_4; // @[package.scala:16:47] wire _r1_c_cat_T_7; // @[package.scala:16:47] assign _r1_c_cat_T_7 = _GEN_4; // @[package.scala:16:47] wire _r1_c_cat_T_30; // @[package.scala:16:47] assign _r1_c_cat_T_30 = _GEN_4; // @[package.scala:16:47] wire _needs_second_acq_T_34; // @[package.scala:16:47] assign _needs_second_acq_T_34 = _GEN_4; // @[package.scala:16:47] wire _GEN_5 = req_cmd == 5'hB; // @[MSHR.scala:38:16] wire _grow_param_r_c_cat_T_8; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_8 = _GEN_5; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_31; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_31 = _GEN_5; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_8; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_8 = _GEN_5; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_31; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_31 = _GEN_5; // @[package.scala:16:47] wire _r1_c_cat_T_8; // @[package.scala:16:47] assign _r1_c_cat_T_8 = _GEN_5; // @[package.scala:16:47] wire _r1_c_cat_T_31; // @[package.scala:16:47] assign _r1_c_cat_T_31 = _GEN_5; // @[package.scala:16:47] wire _needs_second_acq_T_35; // @[package.scala:16:47] assign _needs_second_acq_T_35 = _GEN_5; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_9 = _grow_param_r_c_cat_T_5 | _grow_param_r_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_10 = _grow_param_r_c_cat_T_9 | _grow_param_r_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_11 = _grow_param_r_c_cat_T_10 | _grow_param_r_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _GEN_6 = req_cmd == 5'h8; // @[MSHR.scala:38:16] wire _grow_param_r_c_cat_T_12; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_12 = _GEN_6; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_35; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_35 = _GEN_6; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_12; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_12 = _GEN_6; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_35; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_35 = _GEN_6; // @[package.scala:16:47] wire _r1_c_cat_T_12; // @[package.scala:16:47] assign _r1_c_cat_T_12 = _GEN_6; // @[package.scala:16:47] wire _r1_c_cat_T_35; // @[package.scala:16:47] assign _r1_c_cat_T_35 = _GEN_6; // @[package.scala:16:47] wire _needs_second_acq_T_39; // @[package.scala:16:47] assign _needs_second_acq_T_39 = _GEN_6; // @[package.scala:16:47] wire _GEN_7 = req_cmd == 5'hC; // @[MSHR.scala:38:16] wire _grow_param_r_c_cat_T_13; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_13 = _GEN_7; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_36; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_36 = _GEN_7; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_13; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_13 = _GEN_7; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_36; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_36 = _GEN_7; // @[package.scala:16:47] wire _r1_c_cat_T_13; // @[package.scala:16:47] assign _r1_c_cat_T_13 = _GEN_7; // @[package.scala:16:47] wire _r1_c_cat_T_36; // @[package.scala:16:47] assign _r1_c_cat_T_36 = _GEN_7; // @[package.scala:16:47] wire _needs_second_acq_T_40; // @[package.scala:16:47] assign _needs_second_acq_T_40 = _GEN_7; // @[package.scala:16:47] wire _GEN_8 = req_cmd == 5'hD; // @[MSHR.scala:38:16] wire _grow_param_r_c_cat_T_14; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_14 = _GEN_8; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_37; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_37 = _GEN_8; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_14; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_14 = _GEN_8; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_37; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_37 = _GEN_8; // @[package.scala:16:47] wire _r1_c_cat_T_14; // @[package.scala:16:47] assign _r1_c_cat_T_14 = _GEN_8; // @[package.scala:16:47] wire _r1_c_cat_T_37; // @[package.scala:16:47] assign _r1_c_cat_T_37 = _GEN_8; // @[package.scala:16:47] wire _needs_second_acq_T_41; // @[package.scala:16:47] assign _needs_second_acq_T_41 = _GEN_8; // @[package.scala:16:47] wire _GEN_9 = req_cmd == 5'hE; // @[MSHR.scala:38:16] wire _grow_param_r_c_cat_T_15; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_15 = _GEN_9; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_38; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_38 = _GEN_9; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_15; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_15 = _GEN_9; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_38; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_38 = _GEN_9; // @[package.scala:16:47] wire _r1_c_cat_T_15; // @[package.scala:16:47] assign _r1_c_cat_T_15 = _GEN_9; // @[package.scala:16:47] wire _r1_c_cat_T_38; // @[package.scala:16:47] assign _r1_c_cat_T_38 = _GEN_9; // @[package.scala:16:47] wire _needs_second_acq_T_42; // @[package.scala:16:47] assign _needs_second_acq_T_42 = _GEN_9; // @[package.scala:16:47] wire _GEN_10 = req_cmd == 5'hF; // @[MSHR.scala:38:16] wire _grow_param_r_c_cat_T_16; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_16 = _GEN_10; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_39; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_39 = _GEN_10; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_16; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_16 = _GEN_10; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_39; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_39 = _GEN_10; // @[package.scala:16:47] wire _r1_c_cat_T_16; // @[package.scala:16:47] assign _r1_c_cat_T_16 = _GEN_10; // @[package.scala:16:47] wire _r1_c_cat_T_39; // @[package.scala:16:47] assign _r1_c_cat_T_39 = _GEN_10; // @[package.scala:16:47] wire _needs_second_acq_T_43; // @[package.scala:16:47] assign _needs_second_acq_T_43 = _GEN_10; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_17 = _grow_param_r_c_cat_T_12 | _grow_param_r_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_18 = _grow_param_r_c_cat_T_17 | _grow_param_r_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_19 = _grow_param_r_c_cat_T_18 | _grow_param_r_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_20 = _grow_param_r_c_cat_T_19 | _grow_param_r_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_21 = _grow_param_r_c_cat_T_11 | _grow_param_r_c_cat_T_20; // @[package.scala:81:59] wire _grow_param_r_c_cat_T_22 = _grow_param_r_c_cat_T_4 | _grow_param_r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _grow_param_r_c_cat_T_25 = _grow_param_r_c_cat_T_23 | _grow_param_r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _grow_param_r_c_cat_T_27 = _grow_param_r_c_cat_T_25 | _grow_param_r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _grow_param_r_c_cat_T_32 = _grow_param_r_c_cat_T_28 | _grow_param_r_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_33 = _grow_param_r_c_cat_T_32 | _grow_param_r_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_34 = _grow_param_r_c_cat_T_33 | _grow_param_r_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_40 = _grow_param_r_c_cat_T_35 | _grow_param_r_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_41 = _grow_param_r_c_cat_T_40 | _grow_param_r_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_42 = _grow_param_r_c_cat_T_41 | _grow_param_r_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_43 = _grow_param_r_c_cat_T_42 | _grow_param_r_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_44 = _grow_param_r_c_cat_T_34 | _grow_param_r_c_cat_T_43; // @[package.scala:81:59] wire _grow_param_r_c_cat_T_45 = _grow_param_r_c_cat_T_27 | _grow_param_r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _GEN_11 = req_cmd == 5'h3; // @[MSHR.scala:38:16] wire _grow_param_r_c_cat_T_46; // @[Consts.scala:91:54] assign _grow_param_r_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54] wire _coh_on_grant_c_cat_T_46; // @[Consts.scala:91:54] assign _coh_on_grant_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54] wire _r1_c_cat_T_46; // @[Consts.scala:91:54] assign _r1_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54] wire _needs_second_acq_T_50; // @[Consts.scala:91:54] assign _needs_second_acq_T_50 = _GEN_11; // @[Consts.scala:91:54] wire _grow_param_r_c_cat_T_47 = _grow_param_r_c_cat_T_45 | _grow_param_r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _GEN_12 = req_cmd == 5'h6; // @[MSHR.scala:38:16] wire _grow_param_r_c_cat_T_48; // @[Consts.scala:91:71] assign _grow_param_r_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71] wire _coh_on_grant_c_cat_T_48; // @[Consts.scala:91:71] assign _coh_on_grant_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71] wire _r1_c_cat_T_48; // @[Consts.scala:91:71] assign _r1_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71] wire _needs_second_acq_T_52; // @[Consts.scala:91:71] assign _needs_second_acq_T_52 = _GEN_12; // @[Consts.scala:91:71] wire _grow_param_r_c_cat_T_49 = _grow_param_r_c_cat_T_47 | _grow_param_r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] grow_param_r_c = {_grow_param_r_c_cat_T_22, _grow_param_r_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _grow_param_r_T = {grow_param_r_c, new_coh_state}; // @[MSHR.scala:45:24] wire _grow_param_r_T_25 = _grow_param_r_T == 4'hC; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_27 = {1'h0, _grow_param_r_T_25}; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_28 = _grow_param_r_T == 4'hD; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_30 = _grow_param_r_T_28 ? 2'h2 : _grow_param_r_T_27; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_31 = _grow_param_r_T == 4'h4; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_33 = _grow_param_r_T_31 ? 2'h1 : _grow_param_r_T_30; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_34 = _grow_param_r_T == 4'h5; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_36 = _grow_param_r_T_34 ? 2'h2 : _grow_param_r_T_33; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_37 = _grow_param_r_T == 4'h0; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_39 = _grow_param_r_T_37 ? 2'h0 : _grow_param_r_T_36; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_40 = _grow_param_r_T == 4'hE; // @[Misc.scala:49:20] wire _grow_param_r_T_41 = _grow_param_r_T_40; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_42 = _grow_param_r_T_40 ? 2'h3 : _grow_param_r_T_39; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_43 = &_grow_param_r_T; // @[Misc.scala:49:20] wire _grow_param_r_T_44 = _grow_param_r_T_43 | _grow_param_r_T_41; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_45 = _grow_param_r_T_43 ? 2'h3 : _grow_param_r_T_42; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_46 = _grow_param_r_T == 4'h6; // @[Misc.scala:49:20] wire _grow_param_r_T_47 = _grow_param_r_T_46 | _grow_param_r_T_44; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_48 = _grow_param_r_T_46 ? 2'h2 : _grow_param_r_T_45; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_49 = _grow_param_r_T == 4'h7; // @[Misc.scala:49:20] wire _grow_param_r_T_50 = _grow_param_r_T_49 | _grow_param_r_T_47; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_51 = _grow_param_r_T_49 ? 2'h3 : _grow_param_r_T_48; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_52 = _grow_param_r_T == 4'h1; // @[Misc.scala:49:20] wire _grow_param_r_T_53 = _grow_param_r_T_52 | _grow_param_r_T_50; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_54 = _grow_param_r_T_52 ? 2'h1 : _grow_param_r_T_51; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_55 = _grow_param_r_T == 4'h2; // @[Misc.scala:49:20] wire _grow_param_r_T_56 = _grow_param_r_T_55 | _grow_param_r_T_53; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_57 = _grow_param_r_T_55 ? 2'h2 : _grow_param_r_T_54; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_58 = _grow_param_r_T == 4'h3; // @[Misc.scala:49:20] wire grow_param_r_1 = _grow_param_r_T_58 | _grow_param_r_T_56; // @[Misc.scala:35:9, :49:20] wire [1:0] grow_param = _grow_param_r_T_58 ? 2'h3 : _grow_param_r_T_57; // @[Misc.scala:35:36, :49:20] wire [1:0] grow_param_meta_state = grow_param; // @[Misc.scala:35:36] wire _coh_on_grant_c_cat_T_2 = _coh_on_grant_c_cat_T | _coh_on_grant_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _coh_on_grant_c_cat_T_4 = _coh_on_grant_c_cat_T_2 | _coh_on_grant_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _coh_on_grant_c_cat_T_9 = _coh_on_grant_c_cat_T_5 | _coh_on_grant_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_10 = _coh_on_grant_c_cat_T_9 | _coh_on_grant_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_11 = _coh_on_grant_c_cat_T_10 | _coh_on_grant_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_17 = _coh_on_grant_c_cat_T_12 | _coh_on_grant_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_18 = _coh_on_grant_c_cat_T_17 | _coh_on_grant_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_19 = _coh_on_grant_c_cat_T_18 | _coh_on_grant_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_20 = _coh_on_grant_c_cat_T_19 | _coh_on_grant_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_21 = _coh_on_grant_c_cat_T_11 | _coh_on_grant_c_cat_T_20; // @[package.scala:81:59] wire _coh_on_grant_c_cat_T_22 = _coh_on_grant_c_cat_T_4 | _coh_on_grant_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _coh_on_grant_c_cat_T_25 = _coh_on_grant_c_cat_T_23 | _coh_on_grant_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _coh_on_grant_c_cat_T_27 = _coh_on_grant_c_cat_T_25 | _coh_on_grant_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _coh_on_grant_c_cat_T_32 = _coh_on_grant_c_cat_T_28 | _coh_on_grant_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_33 = _coh_on_grant_c_cat_T_32 | _coh_on_grant_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_34 = _coh_on_grant_c_cat_T_33 | _coh_on_grant_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_40 = _coh_on_grant_c_cat_T_35 | _coh_on_grant_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_41 = _coh_on_grant_c_cat_T_40 | _coh_on_grant_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_42 = _coh_on_grant_c_cat_T_41 | _coh_on_grant_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_43 = _coh_on_grant_c_cat_T_42 | _coh_on_grant_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_44 = _coh_on_grant_c_cat_T_34 | _coh_on_grant_c_cat_T_43; // @[package.scala:81:59] wire _coh_on_grant_c_cat_T_45 = _coh_on_grant_c_cat_T_27 | _coh_on_grant_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _coh_on_grant_c_cat_T_47 = _coh_on_grant_c_cat_T_45 | _coh_on_grant_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _coh_on_grant_c_cat_T_49 = _coh_on_grant_c_cat_T_47 | _coh_on_grant_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] coh_on_grant_c = {_coh_on_grant_c_cat_T_22, _coh_on_grant_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _coh_on_grant_T = {coh_on_grant_c, io_mem_grant_bits_param_0}; // @[MSHR.scala:12:7] wire _coh_on_grant_T_9 = _coh_on_grant_T == 4'h1; // @[Metadata.scala:84:{18,38}] wire [1:0] _coh_on_grant_T_10 = {1'h0, _coh_on_grant_T_9}; // @[Metadata.scala:84:38] wire _coh_on_grant_T_11 = _coh_on_grant_T == 4'h0; // @[Metadata.scala:84:{18,38}] wire [1:0] _coh_on_grant_T_12 = _coh_on_grant_T_11 ? 2'h2 : _coh_on_grant_T_10; // @[Metadata.scala:84:38] wire _coh_on_grant_T_13 = _coh_on_grant_T == 4'h4; // @[Metadata.scala:84:{18,38}] wire [1:0] _coh_on_grant_T_14 = _coh_on_grant_T_13 ? 2'h2 : _coh_on_grant_T_12; // @[Metadata.scala:84:38] wire _coh_on_grant_T_15 = _coh_on_grant_T == 4'hC; // @[Metadata.scala:84:{18,38}] wire [1:0] _coh_on_grant_T_16 = _coh_on_grant_T_15 ? 2'h3 : _coh_on_grant_T_14; // @[Metadata.scala:84:38] wire [1:0] coh_on_grant_state = _coh_on_grant_T_16; // @[Metadata.scala:84:38, :160:20] wire _r1_c_cat_T_2 = _r1_c_cat_T | _r1_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _r1_c_cat_T_4 = _r1_c_cat_T_2 | _r1_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _r1_c_cat_T_9 = _r1_c_cat_T_5 | _r1_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_10 = _r1_c_cat_T_9 | _r1_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_11 = _r1_c_cat_T_10 | _r1_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_17 = _r1_c_cat_T_12 | _r1_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_18 = _r1_c_cat_T_17 | _r1_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_19 = _r1_c_cat_T_18 | _r1_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_20 = _r1_c_cat_T_19 | _r1_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_21 = _r1_c_cat_T_11 | _r1_c_cat_T_20; // @[package.scala:81:59] wire _r1_c_cat_T_22 = _r1_c_cat_T_4 | _r1_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _r1_c_cat_T_25 = _r1_c_cat_T_23 | _r1_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _r1_c_cat_T_27 = _r1_c_cat_T_25 | _r1_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _r1_c_cat_T_32 = _r1_c_cat_T_28 | _r1_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_33 = _r1_c_cat_T_32 | _r1_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_34 = _r1_c_cat_T_33 | _r1_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_40 = _r1_c_cat_T_35 | _r1_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_41 = _r1_c_cat_T_40 | _r1_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_42 = _r1_c_cat_T_41 | _r1_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_43 = _r1_c_cat_T_42 | _r1_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_44 = _r1_c_cat_T_34 | _r1_c_cat_T_43; // @[package.scala:81:59] wire _r1_c_cat_T_45 = _r1_c_cat_T_27 | _r1_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _r1_c_cat_T_47 = _r1_c_cat_T_45 | _r1_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _r1_c_cat_T_49 = _r1_c_cat_T_47 | _r1_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] r1_c = {_r1_c_cat_T_22, _r1_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _r1_T = {r1_c, new_coh_state}; // @[MSHR.scala:45:24] wire _r1_T_25 = _r1_T == 4'hC; // @[Misc.scala:49:20] wire [1:0] _r1_T_27 = {1'h0, _r1_T_25}; // @[Misc.scala:35:36, :49:20] wire _r1_T_28 = _r1_T == 4'hD; // @[Misc.scala:49:20] wire [1:0] _r1_T_30 = _r1_T_28 ? 2'h2 : _r1_T_27; // @[Misc.scala:35:36, :49:20] wire _r1_T_31 = _r1_T == 4'h4; // @[Misc.scala:49:20] wire [1:0] _r1_T_33 = _r1_T_31 ? 2'h1 : _r1_T_30; // @[Misc.scala:35:36, :49:20] wire _r1_T_34 = _r1_T == 4'h5; // @[Misc.scala:49:20] wire [1:0] _r1_T_36 = _r1_T_34 ? 2'h2 : _r1_T_33; // @[Misc.scala:35:36, :49:20] wire _r1_T_37 = _r1_T == 4'h0; // @[Misc.scala:49:20] wire [1:0] _r1_T_39 = _r1_T_37 ? 2'h0 : _r1_T_36; // @[Misc.scala:35:36, :49:20] wire _r1_T_40 = _r1_T == 4'hE; // @[Misc.scala:49:20] wire _r1_T_41 = _r1_T_40; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_42 = _r1_T_40 ? 2'h3 : _r1_T_39; // @[Misc.scala:35:36, :49:20] wire _r1_T_43 = &_r1_T; // @[Misc.scala:49:20] wire _r1_T_44 = _r1_T_43 | _r1_T_41; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_45 = _r1_T_43 ? 2'h3 : _r1_T_42; // @[Misc.scala:35:36, :49:20] wire _r1_T_46 = _r1_T == 4'h6; // @[Misc.scala:49:20] wire _r1_T_47 = _r1_T_46 | _r1_T_44; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_48 = _r1_T_46 ? 2'h2 : _r1_T_45; // @[Misc.scala:35:36, :49:20] wire _r1_T_49 = _r1_T == 4'h7; // @[Misc.scala:49:20] wire _r1_T_50 = _r1_T_49 | _r1_T_47; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_51 = _r1_T_49 ? 2'h3 : _r1_T_48; // @[Misc.scala:35:36, :49:20] wire _r1_T_52 = _r1_T == 4'h1; // @[Misc.scala:49:20] wire _r1_T_53 = _r1_T_52 | _r1_T_50; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_54 = _r1_T_52 ? 2'h1 : _r1_T_51; // @[Misc.scala:35:36, :49:20] wire _r1_T_55 = _r1_T == 4'h2; // @[Misc.scala:49:20] wire _r1_T_56 = _r1_T_55 | _r1_T_53; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_57 = _r1_T_55 ? 2'h2 : _r1_T_54; // @[Misc.scala:35:36, :49:20] wire _r1_T_58 = _r1_T == 4'h3; // @[Misc.scala:49:20] wire r1_1 = _r1_T_58 | _r1_T_56; // @[Misc.scala:35:9, :49:20] wire [1:0] r1_2 = _r1_T_58 ? 2'h3 : _r1_T_57; // @[Misc.scala:35:36, :49:20] wire _GEN_13 = io_req_bits_cmd_0 == 5'h1; // @[MSHR.scala:12:7] wire _r2_c_cat_T; // @[Consts.scala:90:32] assign _r2_c_cat_T = _GEN_13; // @[Consts.scala:90:32] wire _r2_c_cat_T_23; // @[Consts.scala:90:32] assign _r2_c_cat_T_23 = _GEN_13; // @[Consts.scala:90:32] wire _needs_second_acq_T; // @[Consts.scala:90:32] assign _needs_second_acq_T = _GEN_13; // @[Consts.scala:90:32] wire _dirties_cat_T; // @[Consts.scala:90:32] assign _dirties_cat_T = _GEN_13; // @[Consts.scala:90:32] wire _dirties_cat_T_23; // @[Consts.scala:90:32] assign _dirties_cat_T_23 = _GEN_13; // @[Consts.scala:90:32] wire _r_c_cat_T; // @[Consts.scala:90:32] assign _r_c_cat_T = _GEN_13; // @[Consts.scala:90:32] wire _r_c_cat_T_23; // @[Consts.scala:90:32] assign _r_c_cat_T_23 = _GEN_13; // @[Consts.scala:90:32] wire _GEN_14 = io_req_bits_cmd_0 == 5'h11; // @[MSHR.scala:12:7] wire _r2_c_cat_T_1; // @[Consts.scala:90:49] assign _r2_c_cat_T_1 = _GEN_14; // @[Consts.scala:90:49] wire _r2_c_cat_T_24; // @[Consts.scala:90:49] assign _r2_c_cat_T_24 = _GEN_14; // @[Consts.scala:90:49] wire _needs_second_acq_T_1; // @[Consts.scala:90:49] assign _needs_second_acq_T_1 = _GEN_14; // @[Consts.scala:90:49] wire _dirties_cat_T_1; // @[Consts.scala:90:49] assign _dirties_cat_T_1 = _GEN_14; // @[Consts.scala:90:49] wire _dirties_cat_T_24; // @[Consts.scala:90:49] assign _dirties_cat_T_24 = _GEN_14; // @[Consts.scala:90:49] wire _r_c_cat_T_1; // @[Consts.scala:90:49] assign _r_c_cat_T_1 = _GEN_14; // @[Consts.scala:90:49] wire _r_c_cat_T_24; // @[Consts.scala:90:49] assign _r_c_cat_T_24 = _GEN_14; // @[Consts.scala:90:49] wire _r2_c_cat_T_2 = _r2_c_cat_T | _r2_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _GEN_15 = io_req_bits_cmd_0 == 5'h7; // @[MSHR.scala:12:7] wire _r2_c_cat_T_3; // @[Consts.scala:90:66] assign _r2_c_cat_T_3 = _GEN_15; // @[Consts.scala:90:66] wire _r2_c_cat_T_26; // @[Consts.scala:90:66] assign _r2_c_cat_T_26 = _GEN_15; // @[Consts.scala:90:66] wire _needs_second_acq_T_3; // @[Consts.scala:90:66] assign _needs_second_acq_T_3 = _GEN_15; // @[Consts.scala:90:66] wire _dirties_cat_T_3; // @[Consts.scala:90:66] assign _dirties_cat_T_3 = _GEN_15; // @[Consts.scala:90:66] wire _dirties_cat_T_26; // @[Consts.scala:90:66] assign _dirties_cat_T_26 = _GEN_15; // @[Consts.scala:90:66] wire _r_c_cat_T_3; // @[Consts.scala:90:66] assign _r_c_cat_T_3 = _GEN_15; // @[Consts.scala:90:66] wire _r_c_cat_T_26; // @[Consts.scala:90:66] assign _r_c_cat_T_26 = _GEN_15; // @[Consts.scala:90:66] wire _r2_c_cat_T_4 = _r2_c_cat_T_2 | _r2_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _GEN_16 = io_req_bits_cmd_0 == 5'h4; // @[MSHR.scala:12:7] wire _r2_c_cat_T_5; // @[package.scala:16:47] assign _r2_c_cat_T_5 = _GEN_16; // @[package.scala:16:47] wire _r2_c_cat_T_28; // @[package.scala:16:47] assign _r2_c_cat_T_28 = _GEN_16; // @[package.scala:16:47] wire _needs_second_acq_T_5; // @[package.scala:16:47] assign _needs_second_acq_T_5 = _GEN_16; // @[package.scala:16:47] wire _dirties_cat_T_5; // @[package.scala:16:47] assign _dirties_cat_T_5 = _GEN_16; // @[package.scala:16:47] wire _dirties_cat_T_28; // @[package.scala:16:47] assign _dirties_cat_T_28 = _GEN_16; // @[package.scala:16:47] wire _r_c_cat_T_5; // @[package.scala:16:47] assign _r_c_cat_T_5 = _GEN_16; // @[package.scala:16:47] wire _r_c_cat_T_28; // @[package.scala:16:47] assign _r_c_cat_T_28 = _GEN_16; // @[package.scala:16:47] wire _GEN_17 = io_req_bits_cmd_0 == 5'h9; // @[MSHR.scala:12:7] wire _r2_c_cat_T_6; // @[package.scala:16:47] assign _r2_c_cat_T_6 = _GEN_17; // @[package.scala:16:47] wire _r2_c_cat_T_29; // @[package.scala:16:47] assign _r2_c_cat_T_29 = _GEN_17; // @[package.scala:16:47] wire _needs_second_acq_T_6; // @[package.scala:16:47] assign _needs_second_acq_T_6 = _GEN_17; // @[package.scala:16:47] wire _dirties_cat_T_6; // @[package.scala:16:47] assign _dirties_cat_T_6 = _GEN_17; // @[package.scala:16:47] wire _dirties_cat_T_29; // @[package.scala:16:47] assign _dirties_cat_T_29 = _GEN_17; // @[package.scala:16:47] wire _r_c_cat_T_6; // @[package.scala:16:47] assign _r_c_cat_T_6 = _GEN_17; // @[package.scala:16:47] wire _r_c_cat_T_29; // @[package.scala:16:47] assign _r_c_cat_T_29 = _GEN_17; // @[package.scala:16:47] wire _GEN_18 = io_req_bits_cmd_0 == 5'hA; // @[MSHR.scala:12:7] wire _r2_c_cat_T_7; // @[package.scala:16:47] assign _r2_c_cat_T_7 = _GEN_18; // @[package.scala:16:47] wire _r2_c_cat_T_30; // @[package.scala:16:47] assign _r2_c_cat_T_30 = _GEN_18; // @[package.scala:16:47] wire _needs_second_acq_T_7; // @[package.scala:16:47] assign _needs_second_acq_T_7 = _GEN_18; // @[package.scala:16:47] wire _dirties_cat_T_7; // @[package.scala:16:47] assign _dirties_cat_T_7 = _GEN_18; // @[package.scala:16:47] wire _dirties_cat_T_30; // @[package.scala:16:47] assign _dirties_cat_T_30 = _GEN_18; // @[package.scala:16:47] wire _r_c_cat_T_7; // @[package.scala:16:47] assign _r_c_cat_T_7 = _GEN_18; // @[package.scala:16:47] wire _r_c_cat_T_30; // @[package.scala:16:47] assign _r_c_cat_T_30 = _GEN_18; // @[package.scala:16:47] wire _GEN_19 = io_req_bits_cmd_0 == 5'hB; // @[MSHR.scala:12:7] wire _r2_c_cat_T_8; // @[package.scala:16:47] assign _r2_c_cat_T_8 = _GEN_19; // @[package.scala:16:47] wire _r2_c_cat_T_31; // @[package.scala:16:47] assign _r2_c_cat_T_31 = _GEN_19; // @[package.scala:16:47] wire _needs_second_acq_T_8; // @[package.scala:16:47] assign _needs_second_acq_T_8 = _GEN_19; // @[package.scala:16:47] wire _dirties_cat_T_8; // @[package.scala:16:47] assign _dirties_cat_T_8 = _GEN_19; // @[package.scala:16:47] wire _dirties_cat_T_31; // @[package.scala:16:47] assign _dirties_cat_T_31 = _GEN_19; // @[package.scala:16:47] wire _r_c_cat_T_8; // @[package.scala:16:47] assign _r_c_cat_T_8 = _GEN_19; // @[package.scala:16:47] wire _r_c_cat_T_31; // @[package.scala:16:47] assign _r_c_cat_T_31 = _GEN_19; // @[package.scala:16:47] wire _r2_c_cat_T_9 = _r2_c_cat_T_5 | _r2_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_10 = _r2_c_cat_T_9 | _r2_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_11 = _r2_c_cat_T_10 | _r2_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _GEN_20 = io_req_bits_cmd_0 == 5'h8; // @[MSHR.scala:12:7] wire _r2_c_cat_T_12; // @[package.scala:16:47] assign _r2_c_cat_T_12 = _GEN_20; // @[package.scala:16:47] wire _r2_c_cat_T_35; // @[package.scala:16:47] assign _r2_c_cat_T_35 = _GEN_20; // @[package.scala:16:47] wire _needs_second_acq_T_12; // @[package.scala:16:47] assign _needs_second_acq_T_12 = _GEN_20; // @[package.scala:16:47] wire _dirties_cat_T_12; // @[package.scala:16:47] assign _dirties_cat_T_12 = _GEN_20; // @[package.scala:16:47] wire _dirties_cat_T_35; // @[package.scala:16:47] assign _dirties_cat_T_35 = _GEN_20; // @[package.scala:16:47] wire _r_c_cat_T_12; // @[package.scala:16:47] assign _r_c_cat_T_12 = _GEN_20; // @[package.scala:16:47] wire _r_c_cat_T_35; // @[package.scala:16:47] assign _r_c_cat_T_35 = _GEN_20; // @[package.scala:16:47] wire _GEN_21 = io_req_bits_cmd_0 == 5'hC; // @[MSHR.scala:12:7] wire _r2_c_cat_T_13; // @[package.scala:16:47] assign _r2_c_cat_T_13 = _GEN_21; // @[package.scala:16:47] wire _r2_c_cat_T_36; // @[package.scala:16:47] assign _r2_c_cat_T_36 = _GEN_21; // @[package.scala:16:47] wire _needs_second_acq_T_13; // @[package.scala:16:47] assign _needs_second_acq_T_13 = _GEN_21; // @[package.scala:16:47] wire _dirties_cat_T_13; // @[package.scala:16:47] assign _dirties_cat_T_13 = _GEN_21; // @[package.scala:16:47] wire _dirties_cat_T_36; // @[package.scala:16:47] assign _dirties_cat_T_36 = _GEN_21; // @[package.scala:16:47] wire _r_c_cat_T_13; // @[package.scala:16:47] assign _r_c_cat_T_13 = _GEN_21; // @[package.scala:16:47] wire _r_c_cat_T_36; // @[package.scala:16:47] assign _r_c_cat_T_36 = _GEN_21; // @[package.scala:16:47] wire _GEN_22 = io_req_bits_cmd_0 == 5'hD; // @[MSHR.scala:12:7] wire _r2_c_cat_T_14; // @[package.scala:16:47] assign _r2_c_cat_T_14 = _GEN_22; // @[package.scala:16:47] wire _r2_c_cat_T_37; // @[package.scala:16:47] assign _r2_c_cat_T_37 = _GEN_22; // @[package.scala:16:47] wire _needs_second_acq_T_14; // @[package.scala:16:47] assign _needs_second_acq_T_14 = _GEN_22; // @[package.scala:16:47] wire _dirties_cat_T_14; // @[package.scala:16:47] assign _dirties_cat_T_14 = _GEN_22; // @[package.scala:16:47] wire _dirties_cat_T_37; // @[package.scala:16:47] assign _dirties_cat_T_37 = _GEN_22; // @[package.scala:16:47] wire _r_c_cat_T_14; // @[package.scala:16:47] assign _r_c_cat_T_14 = _GEN_22; // @[package.scala:16:47] wire _r_c_cat_T_37; // @[package.scala:16:47] assign _r_c_cat_T_37 = _GEN_22; // @[package.scala:16:47] wire _GEN_23 = io_req_bits_cmd_0 == 5'hE; // @[MSHR.scala:12:7] wire _r2_c_cat_T_15; // @[package.scala:16:47] assign _r2_c_cat_T_15 = _GEN_23; // @[package.scala:16:47] wire _r2_c_cat_T_38; // @[package.scala:16:47] assign _r2_c_cat_T_38 = _GEN_23; // @[package.scala:16:47] wire _needs_second_acq_T_15; // @[package.scala:16:47] assign _needs_second_acq_T_15 = _GEN_23; // @[package.scala:16:47] wire _dirties_cat_T_15; // @[package.scala:16:47] assign _dirties_cat_T_15 = _GEN_23; // @[package.scala:16:47] wire _dirties_cat_T_38; // @[package.scala:16:47] assign _dirties_cat_T_38 = _GEN_23; // @[package.scala:16:47] wire _r_c_cat_T_15; // @[package.scala:16:47] assign _r_c_cat_T_15 = _GEN_23; // @[package.scala:16:47] wire _r_c_cat_T_38; // @[package.scala:16:47] assign _r_c_cat_T_38 = _GEN_23; // @[package.scala:16:47] wire _GEN_24 = io_req_bits_cmd_0 == 5'hF; // @[MSHR.scala:12:7] wire _r2_c_cat_T_16; // @[package.scala:16:47] assign _r2_c_cat_T_16 = _GEN_24; // @[package.scala:16:47] wire _r2_c_cat_T_39; // @[package.scala:16:47] assign _r2_c_cat_T_39 = _GEN_24; // @[package.scala:16:47] wire _needs_second_acq_T_16; // @[package.scala:16:47] assign _needs_second_acq_T_16 = _GEN_24; // @[package.scala:16:47] wire _dirties_cat_T_16; // @[package.scala:16:47] assign _dirties_cat_T_16 = _GEN_24; // @[package.scala:16:47] wire _dirties_cat_T_39; // @[package.scala:16:47] assign _dirties_cat_T_39 = _GEN_24; // @[package.scala:16:47] wire _r_c_cat_T_16; // @[package.scala:16:47] assign _r_c_cat_T_16 = _GEN_24; // @[package.scala:16:47] wire _r_c_cat_T_39; // @[package.scala:16:47] assign _r_c_cat_T_39 = _GEN_24; // @[package.scala:16:47] wire _r2_c_cat_T_17 = _r2_c_cat_T_12 | _r2_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_18 = _r2_c_cat_T_17 | _r2_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_19 = _r2_c_cat_T_18 | _r2_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_20 = _r2_c_cat_T_19 | _r2_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_21 = _r2_c_cat_T_11 | _r2_c_cat_T_20; // @[package.scala:81:59] wire _r2_c_cat_T_22 = _r2_c_cat_T_4 | _r2_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _r2_c_cat_T_25 = _r2_c_cat_T_23 | _r2_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _r2_c_cat_T_27 = _r2_c_cat_T_25 | _r2_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _r2_c_cat_T_32 = _r2_c_cat_T_28 | _r2_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_33 = _r2_c_cat_T_32 | _r2_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_34 = _r2_c_cat_T_33 | _r2_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_40 = _r2_c_cat_T_35 | _r2_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_41 = _r2_c_cat_T_40 | _r2_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_42 = _r2_c_cat_T_41 | _r2_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_43 = _r2_c_cat_T_42 | _r2_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_44 = _r2_c_cat_T_34 | _r2_c_cat_T_43; // @[package.scala:81:59] wire _r2_c_cat_T_45 = _r2_c_cat_T_27 | _r2_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _GEN_25 = io_req_bits_cmd_0 == 5'h3; // @[MSHR.scala:12:7] wire _r2_c_cat_T_46; // @[Consts.scala:91:54] assign _r2_c_cat_T_46 = _GEN_25; // @[Consts.scala:91:54] wire _needs_second_acq_T_23; // @[Consts.scala:91:54] assign _needs_second_acq_T_23 = _GEN_25; // @[Consts.scala:91:54] wire _dirties_cat_T_46; // @[Consts.scala:91:54] assign _dirties_cat_T_46 = _GEN_25; // @[Consts.scala:91:54] wire _rpq_io_enq_valid_T_4; // @[Consts.scala:88:52] assign _rpq_io_enq_valid_T_4 = _GEN_25; // @[Consts.scala:88:52, :91:54] wire _r_c_cat_T_46; // @[Consts.scala:91:54] assign _r_c_cat_T_46 = _GEN_25; // @[Consts.scala:91:54] wire _r2_c_cat_T_47 = _r2_c_cat_T_45 | _r2_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _GEN_26 = io_req_bits_cmd_0 == 5'h6; // @[MSHR.scala:12:7] wire _r2_c_cat_T_48; // @[Consts.scala:91:71] assign _r2_c_cat_T_48 = _GEN_26; // @[Consts.scala:91:71] wire _needs_second_acq_T_25; // @[Consts.scala:91:71] assign _needs_second_acq_T_25 = _GEN_26; // @[Consts.scala:91:71] wire _dirties_cat_T_48; // @[Consts.scala:91:71] assign _dirties_cat_T_48 = _GEN_26; // @[Consts.scala:91:71] wire _r_c_cat_T_48; // @[Consts.scala:91:71] assign _r_c_cat_T_48 = _GEN_26; // @[Consts.scala:91:71] wire _r2_c_cat_T_49 = _r2_c_cat_T_47 | _r2_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] r2_c = {_r2_c_cat_T_22, _r2_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _r2_T = {r2_c, new_coh_state}; // @[MSHR.scala:45:24] wire _r2_T_25 = _r2_T == 4'hC; // @[Misc.scala:49:20] wire [1:0] _r2_T_27 = {1'h0, _r2_T_25}; // @[Misc.scala:35:36, :49:20] wire _r2_T_28 = _r2_T == 4'hD; // @[Misc.scala:49:20] wire [1:0] _r2_T_30 = _r2_T_28 ? 2'h2 : _r2_T_27; // @[Misc.scala:35:36, :49:20] wire _r2_T_31 = _r2_T == 4'h4; // @[Misc.scala:49:20] wire [1:0] _r2_T_33 = _r2_T_31 ? 2'h1 : _r2_T_30; // @[Misc.scala:35:36, :49:20] wire _r2_T_34 = _r2_T == 4'h5; // @[Misc.scala:49:20] wire [1:0] _r2_T_36 = _r2_T_34 ? 2'h2 : _r2_T_33; // @[Misc.scala:35:36, :49:20] wire _r2_T_37 = _r2_T == 4'h0; // @[Misc.scala:49:20] wire [1:0] _r2_T_39 = _r2_T_37 ? 2'h0 : _r2_T_36; // @[Misc.scala:35:36, :49:20] wire _r2_T_40 = _r2_T == 4'hE; // @[Misc.scala:49:20] wire _r2_T_41 = _r2_T_40; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_42 = _r2_T_40 ? 2'h3 : _r2_T_39; // @[Misc.scala:35:36, :49:20] wire _r2_T_43 = &_r2_T; // @[Misc.scala:49:20] wire _r2_T_44 = _r2_T_43 | _r2_T_41; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_45 = _r2_T_43 ? 2'h3 : _r2_T_42; // @[Misc.scala:35:36, :49:20] wire _r2_T_46 = _r2_T == 4'h6; // @[Misc.scala:49:20] wire _r2_T_47 = _r2_T_46 | _r2_T_44; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_48 = _r2_T_46 ? 2'h2 : _r2_T_45; // @[Misc.scala:35:36, :49:20] wire _r2_T_49 = _r2_T == 4'h7; // @[Misc.scala:49:20] wire _r2_T_50 = _r2_T_49 | _r2_T_47; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_51 = _r2_T_49 ? 2'h3 : _r2_T_48; // @[Misc.scala:35:36, :49:20] wire _r2_T_52 = _r2_T == 4'h1; // @[Misc.scala:49:20] wire _r2_T_53 = _r2_T_52 | _r2_T_50; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_54 = _r2_T_52 ? 2'h1 : _r2_T_51; // @[Misc.scala:35:36, :49:20] wire _r2_T_55 = _r2_T == 4'h2; // @[Misc.scala:49:20] wire _r2_T_56 = _r2_T_55 | _r2_T_53; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_57 = _r2_T_55 ? 2'h2 : _r2_T_54; // @[Misc.scala:35:36, :49:20] wire _r2_T_58 = _r2_T == 4'h3; // @[Misc.scala:49:20] wire r2_1 = _r2_T_58 | _r2_T_56; // @[Misc.scala:35:9, :49:20] wire [1:0] r2_2 = _r2_T_58 ? 2'h3 : _r2_T_57; // @[Misc.scala:35:36, :49:20] wire _needs_second_acq_T_2 = _needs_second_acq_T | _needs_second_acq_T_1; // @[Consts.scala:90:{32,42,49}] wire _needs_second_acq_T_4 = _needs_second_acq_T_2 | _needs_second_acq_T_3; // @[Consts.scala:90:{42,59,66}] wire _needs_second_acq_T_9 = _needs_second_acq_T_5 | _needs_second_acq_T_6; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_10 = _needs_second_acq_T_9 | _needs_second_acq_T_7; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_11 = _needs_second_acq_T_10 | _needs_second_acq_T_8; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_17 = _needs_second_acq_T_12 | _needs_second_acq_T_13; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_18 = _needs_second_acq_T_17 | _needs_second_acq_T_14; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_19 = _needs_second_acq_T_18 | _needs_second_acq_T_15; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_20 = _needs_second_acq_T_19 | _needs_second_acq_T_16; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_21 = _needs_second_acq_T_11 | _needs_second_acq_T_20; // @[package.scala:81:59] wire _needs_second_acq_T_22 = _needs_second_acq_T_4 | _needs_second_acq_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _needs_second_acq_T_24 = _needs_second_acq_T_22 | _needs_second_acq_T_23; // @[Consts.scala:90:76, :91:{47,54}] wire _needs_second_acq_T_26 = _needs_second_acq_T_24 | _needs_second_acq_T_25; // @[Consts.scala:91:{47,64,71}] wire _needs_second_acq_T_29 = _needs_second_acq_T_27 | _needs_second_acq_T_28; // @[Consts.scala:90:{32,42,49}] wire _needs_second_acq_T_31 = _needs_second_acq_T_29 | _needs_second_acq_T_30; // @[Consts.scala:90:{42,59,66}] wire _needs_second_acq_T_36 = _needs_second_acq_T_32 | _needs_second_acq_T_33; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_37 = _needs_second_acq_T_36 | _needs_second_acq_T_34; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_38 = _needs_second_acq_T_37 | _needs_second_acq_T_35; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_44 = _needs_second_acq_T_39 | _needs_second_acq_T_40; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_45 = _needs_second_acq_T_44 | _needs_second_acq_T_41; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_46 = _needs_second_acq_T_45 | _needs_second_acq_T_42; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_47 = _needs_second_acq_T_46 | _needs_second_acq_T_43; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_48 = _needs_second_acq_T_38 | _needs_second_acq_T_47; // @[package.scala:81:59] wire _needs_second_acq_T_49 = _needs_second_acq_T_31 | _needs_second_acq_T_48; // @[Consts.scala:87:44, :90:{59,76}] wire _needs_second_acq_T_51 = _needs_second_acq_T_49 | _needs_second_acq_T_50; // @[Consts.scala:90:76, :91:{47,54}] wire _needs_second_acq_T_53 = _needs_second_acq_T_51 | _needs_second_acq_T_52; // @[Consts.scala:91:{47,64,71}] wire _needs_second_acq_T_54 = ~_needs_second_acq_T_53; // @[Metadata.scala:104:57] wire cmd_requires_second_acquire = _needs_second_acq_T_26 & _needs_second_acq_T_54; // @[Metadata.scala:104:{54,57}] wire is_hit_again = r1_1 & r2_1; // @[Misc.scala:35:9] wire _dirties_cat_T_2 = _dirties_cat_T | _dirties_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _dirties_cat_T_4 = _dirties_cat_T_2 | _dirties_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _dirties_cat_T_9 = _dirties_cat_T_5 | _dirties_cat_T_6; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_10 = _dirties_cat_T_9 | _dirties_cat_T_7; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_11 = _dirties_cat_T_10 | _dirties_cat_T_8; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_17 = _dirties_cat_T_12 | _dirties_cat_T_13; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_18 = _dirties_cat_T_17 | _dirties_cat_T_14; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_19 = _dirties_cat_T_18 | _dirties_cat_T_15; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_20 = _dirties_cat_T_19 | _dirties_cat_T_16; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_21 = _dirties_cat_T_11 | _dirties_cat_T_20; // @[package.scala:81:59] wire _dirties_cat_T_22 = _dirties_cat_T_4 | _dirties_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _dirties_cat_T_25 = _dirties_cat_T_23 | _dirties_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _dirties_cat_T_27 = _dirties_cat_T_25 | _dirties_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _dirties_cat_T_32 = _dirties_cat_T_28 | _dirties_cat_T_29; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_33 = _dirties_cat_T_32 | _dirties_cat_T_30; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_34 = _dirties_cat_T_33 | _dirties_cat_T_31; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_40 = _dirties_cat_T_35 | _dirties_cat_T_36; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_41 = _dirties_cat_T_40 | _dirties_cat_T_37; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_42 = _dirties_cat_T_41 | _dirties_cat_T_38; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_43 = _dirties_cat_T_42 | _dirties_cat_T_39; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_44 = _dirties_cat_T_34 | _dirties_cat_T_43; // @[package.scala:81:59] wire _dirties_cat_T_45 = _dirties_cat_T_27 | _dirties_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _dirties_cat_T_47 = _dirties_cat_T_45 | _dirties_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _dirties_cat_T_49 = _dirties_cat_T_47 | _dirties_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] dirties_cat = {_dirties_cat_T_22, _dirties_cat_T_49}; // @[Metadata.scala:29:18] wire dirties = &dirties_cat; // @[Metadata.scala:29:18, :106:42] wire [1:0] biggest_grow_param = dirties ? r2_2 : r1_2; // @[Misc.scala:35:36] wire [1:0] dirtier_coh_state = biggest_grow_param; // @[Metadata.scala:107:33, :160:20] wire [4:0] dirtier_cmd = dirties ? io_req_bits_cmd_0 : req_cmd; // @[MSHR.scala:12:7, :38:16] wire [26:0] _r_beats1_decode_T = 27'hFFF << io_mem_grant_bits_size_0; // @[MSHR.scala:12:7] wire [11:0] _r_beats1_decode_T_1 = _r_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _r_beats1_decode_T_2 = ~_r_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] r_beats1_decode = _r_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire r_beats1_opdata = io_mem_grant_bits_opcode_0[0]; // @[MSHR.scala:12:7] wire [8:0] r_beats1 = r_beats1_opdata ? r_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] r_counter; // @[Edges.scala:229:27] wire [9:0] _r_counter1_T = {1'h0, r_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] r_counter1 = _r_counter1_T[8:0]; // @[Edges.scala:230:28] wire r_1_1 = r_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _r_last_T = r_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _r_last_T_1 = r_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire r_2 = _r_last_T | _r_last_T_1; // @[Edges.scala:232:{25,33,43}] wire refill_done = r_2 & io_mem_grant_valid_0; // @[MSHR.scala:12:7] wire [8:0] _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] r_4 = r_beats1 & _r_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _r_counter_T = r_1_1 ? r_beats1 : r_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] refill_address_inc = {r_4, 3'h0}; // @[Edges.scala:234:25, :269:29] wire _GEN_27 = state == 4'h1; // @[MSHR.scala:36:22] wire _sec_rdy_T; // @[package.scala:16:47] assign _sec_rdy_T = _GEN_27; // @[package.scala:16:47] wire _io_probe_rdy_T_3; // @[package.scala:16:47] assign _io_probe_rdy_T_3 = _GEN_27; // @[package.scala:16:47] assign _io_wb_req_valid_T = _GEN_27; // @[MSHR.scala:153:28] wire _T_11 = state == 4'h2; // @[MSHR.scala:36:22] wire _sec_rdy_T_1; // @[package.scala:16:47] assign _sec_rdy_T_1 = _T_11; // @[package.scala:16:47] wire _io_probe_rdy_T_4; // @[package.scala:16:47] assign _io_probe_rdy_T_4 = _T_11; // @[package.scala:16:47] wire _T_9 = state == 4'h3; // @[MSHR.scala:36:22] wire _sec_rdy_T_2; // @[package.scala:16:47] assign _sec_rdy_T_2 = _T_9; // @[package.scala:16:47] wire _io_probe_rdy_T_5; // @[package.scala:16:47] assign _io_probe_rdy_T_5 = _T_9; // @[package.scala:16:47] wire _io_meta_write_valid_T_1; // @[package.scala:16:47] assign _io_meta_write_valid_T_1 = _T_9; // @[package.scala:16:47] wire _io_meta_write_bits_data_coh_T; // @[MSHR.scala:149:44] assign _io_meta_write_bits_data_coh_T = _T_9; // @[MSHR.scala:149:44] wire _sec_rdy_T_3 = _sec_rdy_T | _sec_rdy_T_1; // @[package.scala:16:47, :81:59] wire _sec_rdy_T_4 = _sec_rdy_T_3 | _sec_rdy_T_2; // @[package.scala:16:47, :81:59] wire _GEN_28 = state == 4'h4; // @[MSHR.scala:36:22] wire _sec_rdy_T_5; // @[package.scala:16:47] assign _sec_rdy_T_5 = _GEN_28; // @[package.scala:16:47] wire _can_finish_T_1; // @[package.scala:16:47] assign _can_finish_T_1 = _GEN_28; // @[package.scala:16:47] wire _io_mem_acquire_valid_T; // @[MSHR.scala:161:33] assign _io_mem_acquire_valid_T = _GEN_28; // @[MSHR.scala:161:33] wire _sec_rdy_T_6 = state == 4'h5; // @[MSHR.scala:36:22] wire _sec_rdy_T_7 = _sec_rdy_T_5 | _sec_rdy_T_6; // @[package.scala:16:47, :81:59] wire _sec_rdy_T_8 = ~cmd_requires_second_acquire; // @[MSHR.scala:61:23] wire _sec_rdy_T_9 = _sec_rdy_T_7 & _sec_rdy_T_8; // @[MSHR.scala:60:65, :61:23] wire _sec_rdy_T_10 = ~refill_done; // @[MSHR.scala:61:55] wire _sec_rdy_T_11 = _sec_rdy_T_9 & _sec_rdy_T_10; // @[MSHR.scala:60:65, :61:{52,55}] wire _sec_rdy_T_12 = _sec_rdy_T_4 | _sec_rdy_T_11; // @[MSHR.scala:59:56, :61:52] wire sec_rdy = idx_match & _sec_rdy_T_12; // @[MSHR.scala:42:27, :58:27, :59:56] wire _rpq_io_enq_valid_T = io_req_pri_val_0 & io_req_pri_rdy_0; // @[MSHR.scala:12:7, :64:39] wire _rpq_io_enq_valid_T_1 = io_req_sec_val_0 & sec_rdy; // @[MSHR.scala:12:7, :58:27, :64:75] wire _rpq_io_enq_valid_T_2 = _rpq_io_enq_valid_T | _rpq_io_enq_valid_T_1; // @[MSHR.scala:64:{39,57,75}] wire _rpq_io_enq_valid_T_3 = io_req_bits_cmd_0 == 5'h2; // @[MSHR.scala:12:7] wire _rpq_io_enq_valid_T_5 = _rpq_io_enq_valid_T_3 | _rpq_io_enq_valid_T_4; // @[Consts.scala:88:{35,45,52}] wire _rpq_io_enq_valid_T_6 = ~_rpq_io_enq_valid_T_5; // @[MSHR.scala:64:90] wire _rpq_io_enq_valid_T_7 = _rpq_io_enq_valid_T_2 & _rpq_io_enq_valid_T_6; // @[MSHR.scala:64:{57,87,90}] wire _T_19 = state == 4'h8; // @[MSHR.scala:36:22, :66:49] wire _rpq_io_deq_ready_T; // @[MSHR.scala:66:49] assign _rpq_io_deq_ready_T = _T_19; // @[MSHR.scala:66:49] wire _io_replay_valid_T; // @[MSHR.scala:168:28] assign _io_replay_valid_T = _T_19; // @[MSHR.scala:66:49, :168:28] wire _rpq_io_deq_ready_T_4; // @[MSHR.scala:176:48] assign _rpq_io_deq_ready_T_4 = _T_19; // @[MSHR.scala:66:49, :176:48] wire _rpq_io_deq_ready_T_1 = io_replay_ready_0 & _rpq_io_deq_ready_T; // @[MSHR.scala:12:7, :66:{40,49}] wire _rpq_io_deq_ready_T_2 = ~(|state); // @[MSHR.scala:36:22, :66:75] wire _rpq_io_deq_ready_T_3 = _rpq_io_deq_ready_T_1 | _rpq_io_deq_ready_T_2; // @[MSHR.scala:66:{40,66,75}] reg acked; // @[MSHR.scala:68:18] wire _io_meta_write_valid_T = state == 4'h6; // @[MSHR.scala:36:22, :78:15] wire [3:0] _needs_wb_r_T_6 = {2'h2, io_req_bits_old_meta_coh_state_0}; // @[MSHR.scala:12:7] wire _needs_wb_r_T_19 = _needs_wb_r_T_6 == 4'h8; // @[Misc.scala:56:20] wire [2:0] _needs_wb_r_T_21 = _needs_wb_r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_23 = _needs_wb_r_T_6 == 4'h9; // @[Misc.scala:56:20] wire [2:0] _needs_wb_r_T_25 = _needs_wb_r_T_23 ? 3'h2 : _needs_wb_r_T_21; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_27 = _needs_wb_r_T_6 == 4'hA; // @[Misc.scala:56:20] wire [2:0] _needs_wb_r_T_29 = _needs_wb_r_T_27 ? 3'h1 : _needs_wb_r_T_25; // @[MSHR.scala:142:59] wire _needs_wb_r_T_31 = _needs_wb_r_T_6 == 4'hB; // @[Misc.scala:56:20] wire _needs_wb_r_T_32 = _needs_wb_r_T_31; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_33 = _needs_wb_r_T_31 ? 3'h1 : _needs_wb_r_T_29; // @[MSHR.scala:142:59] wire _needs_wb_r_T_35 = _needs_wb_r_T_6 == 4'h4; // @[Misc.scala:56:20] wire _needs_wb_r_T_36 = ~_needs_wb_r_T_35 & _needs_wb_r_T_32; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_37 = _needs_wb_r_T_35 ? 3'h5 : _needs_wb_r_T_33; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_39 = _needs_wb_r_T_6 == 4'h5; // @[Misc.scala:56:20] wire _needs_wb_r_T_40 = ~_needs_wb_r_T_39 & _needs_wb_r_T_36; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_41 = _needs_wb_r_T_39 ? 3'h4 : _needs_wb_r_T_37; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_42 = {1'h0, _needs_wb_r_T_39}; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_43 = _needs_wb_r_T_6 == 4'h6; // @[Misc.scala:56:20] wire _needs_wb_r_T_44 = ~_needs_wb_r_T_43 & _needs_wb_r_T_40; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_45 = _needs_wb_r_T_43 ? 3'h0 : _needs_wb_r_T_41; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_46 = _needs_wb_r_T_43 ? 2'h1 : _needs_wb_r_T_42; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_47 = _needs_wb_r_T_6 == 4'h7; // @[Misc.scala:56:20] wire _needs_wb_r_T_48 = _needs_wb_r_T_47 | _needs_wb_r_T_44; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_49 = _needs_wb_r_T_47 ? 3'h0 : _needs_wb_r_T_45; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_50 = _needs_wb_r_T_47 ? 2'h1 : _needs_wb_r_T_46; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_51 = _needs_wb_r_T_6 == 4'h0; // @[Misc.scala:56:20] wire _needs_wb_r_T_52 = ~_needs_wb_r_T_51 & _needs_wb_r_T_48; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_53 = _needs_wb_r_T_51 ? 3'h5 : _needs_wb_r_T_49; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_54 = _needs_wb_r_T_51 ? 2'h0 : _needs_wb_r_T_50; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_55 = _needs_wb_r_T_6 == 4'h1; // @[Misc.scala:56:20] wire _needs_wb_r_T_56 = ~_needs_wb_r_T_55 & _needs_wb_r_T_52; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_57 = _needs_wb_r_T_55 ? 3'h4 : _needs_wb_r_T_53; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_58 = _needs_wb_r_T_55 ? 2'h1 : _needs_wb_r_T_54; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_59 = _needs_wb_r_T_6 == 4'h2; // @[Misc.scala:56:20] wire _needs_wb_r_T_60 = ~_needs_wb_r_T_59 & _needs_wb_r_T_56; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_61 = _needs_wb_r_T_59 ? 3'h3 : _needs_wb_r_T_57; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_62 = _needs_wb_r_T_59 ? 2'h2 : _needs_wb_r_T_58; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_63 = _needs_wb_r_T_6 == 4'h3; // @[Misc.scala:56:20] wire needs_wb = _needs_wb_r_T_63 | _needs_wb_r_T_60; // @[Misc.scala:38:9, :56:20] wire [2:0] needs_wb_r_2 = _needs_wb_r_T_63 ? 3'h3 : _needs_wb_r_T_61; // @[Misc.scala:38:36, :56:20] wire [1:0] needs_wb_r_3 = _needs_wb_r_T_63 ? 2'h2 : _needs_wb_r_T_62; // @[Misc.scala:38:63, :56:20] wire [1:0] needs_wb_meta_state = needs_wb_r_3; // @[Misc.scala:38:63] wire _r_c_cat_T_2 = _r_c_cat_T | _r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _r_c_cat_T_4 = _r_c_cat_T_2 | _r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _r_c_cat_T_9 = _r_c_cat_T_5 | _r_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_10 = _r_c_cat_T_9 | _r_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_11 = _r_c_cat_T_10 | _r_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_17 = _r_c_cat_T_12 | _r_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_18 = _r_c_cat_T_17 | _r_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_19 = _r_c_cat_T_18 | _r_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_20 = _r_c_cat_T_19 | _r_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_21 = _r_c_cat_T_11 | _r_c_cat_T_20; // @[package.scala:81:59] wire _r_c_cat_T_22 = _r_c_cat_T_4 | _r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _r_c_cat_T_25 = _r_c_cat_T_23 | _r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _r_c_cat_T_27 = _r_c_cat_T_25 | _r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _r_c_cat_T_32 = _r_c_cat_T_28 | _r_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_33 = _r_c_cat_T_32 | _r_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_34 = _r_c_cat_T_33 | _r_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_40 = _r_c_cat_T_35 | _r_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_41 = _r_c_cat_T_40 | _r_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_42 = _r_c_cat_T_41 | _r_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_43 = _r_c_cat_T_42 | _r_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_44 = _r_c_cat_T_34 | _r_c_cat_T_43; // @[package.scala:81:59] wire _r_c_cat_T_45 = _r_c_cat_T_27 | _r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _r_c_cat_T_47 = _r_c_cat_T_45 | _r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _r_c_cat_T_49 = _r_c_cat_T_47 | _r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] r_c = {_r_c_cat_T_22, _r_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _r_T_64 = {r_c, io_req_bits_old_meta_coh_state_0}; // @[MSHR.scala:12:7] wire _r_T_89 = _r_T_64 == 4'hC; // @[Misc.scala:49:20] wire [1:0] _r_T_91 = {1'h0, _r_T_89}; // @[Misc.scala:35:36, :49:20] wire _r_T_92 = _r_T_64 == 4'hD; // @[Misc.scala:49:20] wire [1:0] _r_T_94 = _r_T_92 ? 2'h2 : _r_T_91; // @[Misc.scala:35:36, :49:20] wire _r_T_95 = _r_T_64 == 4'h4; // @[Misc.scala:49:20] wire [1:0] _r_T_97 = _r_T_95 ? 2'h1 : _r_T_94; // @[Misc.scala:35:36, :49:20] wire _r_T_98 = _r_T_64 == 4'h5; // @[Misc.scala:49:20] wire [1:0] _r_T_100 = _r_T_98 ? 2'h2 : _r_T_97; // @[Misc.scala:35:36, :49:20] wire _r_T_101 = _r_T_64 == 4'h0; // @[Misc.scala:49:20] wire [1:0] _r_T_103 = _r_T_101 ? 2'h0 : _r_T_100; // @[Misc.scala:35:36, :49:20] wire _r_T_104 = _r_T_64 == 4'hE; // @[Misc.scala:49:20] wire _r_T_105 = _r_T_104; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_106 = _r_T_104 ? 2'h3 : _r_T_103; // @[Misc.scala:35:36, :49:20] wire _r_T_107 = &_r_T_64; // @[Misc.scala:49:20] wire _r_T_108 = _r_T_107 | _r_T_105; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_109 = _r_T_107 ? 2'h3 : _r_T_106; // @[Misc.scala:35:36, :49:20] wire _r_T_110 = _r_T_64 == 4'h6; // @[Misc.scala:49:20] wire _r_T_111 = _r_T_110 | _r_T_108; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_112 = _r_T_110 ? 2'h2 : _r_T_109; // @[Misc.scala:35:36, :49:20] wire _r_T_113 = _r_T_64 == 4'h7; // @[Misc.scala:49:20] wire _r_T_114 = _r_T_113 | _r_T_111; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_115 = _r_T_113 ? 2'h3 : _r_T_112; // @[Misc.scala:35:36, :49:20] wire _r_T_116 = _r_T_64 == 4'h1; // @[Misc.scala:49:20] wire _r_T_117 = _r_T_116 | _r_T_114; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_118 = _r_T_116 ? 2'h1 : _r_T_115; // @[Misc.scala:35:36, :49:20] wire _r_T_119 = _r_T_64 == 4'h2; // @[Misc.scala:49:20] wire _r_T_120 = _r_T_119 | _r_T_117; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_121 = _r_T_119 ? 2'h2 : _r_T_118; // @[Misc.scala:35:36, :49:20] wire _r_T_122 = _r_T_64 == 4'h3; // @[Misc.scala:49:20] wire is_hit = _r_T_122 | _r_T_120; // @[Misc.scala:35:9, :49:20] wire [1:0] r_2_1 = _r_T_122 ? 2'h3 : _r_T_121; // @[Misc.scala:35:36, :49:20] wire [1:0] coh_on_hit_state = r_2_1; // @[Misc.scala:35:36] wire [3:0] _state_T = {2'h0, ~needs_wb, 1'h1}; // @[MSHR.scala:122:19] wire _can_finish_T = ~(|state); // @[MSHR.scala:36:22, :66:75] wire can_finish = _can_finish_T | _can_finish_T_1; // @[package.scala:16:47, :81:59] wire _grantackq_io_enq_valid_T = io_mem_grant_bits_opcode_0[2]; // @[MSHR.scala:12:7] wire _grantackq_io_enq_valid_T_1 = io_mem_grant_bits_opcode_0[1]; // @[MSHR.scala:12:7] wire _grantackq_io_enq_valid_T_2 = ~_grantackq_io_enq_valid_T_1; // @[Edges.scala:71:{43,52}] wire _grantackq_io_enq_valid_T_3 = _grantackq_io_enq_valid_T & _grantackq_io_enq_valid_T_2; // @[Edges.scala:71:{36,40,43}] wire _grantackq_io_enq_valid_T_4 = refill_done & _grantackq_io_enq_valid_T_3; // @[MSHR.scala:128:41] assign _io_mem_finish_valid_T = _grantackq_io_deq_valid & can_finish; // @[MSHR.scala:126:25, :130:49] assign io_mem_finish_valid_0 = _io_mem_finish_valid_T; // @[MSHR.scala:12:7, :130:49] wire _grantackq_io_deq_ready_T = io_mem_finish_ready_0 & can_finish; // @[MSHR.scala:12:7, :132:49] wire _io_idx_match_T = |state; // @[MSHR.scala:36:22, :66:75, :134:26] assign _io_idx_match_T_1 = _io_idx_match_T & idx_match; // @[MSHR.scala:42:27, :134:{26,41}] assign io_idx_match_0 = _io_idx_match_T_1; // @[MSHR.scala:12:7, :134:41] wire [39:0] _io_refill_addr_T = {req_block_addr[39:12], req_block_addr[11:0] | refill_address_inc}; // @[MSHR.scala:41:51, :136:36] assign io_refill_addr_0 = _io_refill_addr_T[11:0]; // @[MSHR.scala:12:7, :136:{18,36}] assign io_tag_0 = req_tag_0[19:0]; // @[MSHR.scala:12:7, :40:26, :137:10] assign _io_req_pri_rdy_T = ~(|state); // @[MSHR.scala:36:22, :66:75, :138:27] assign io_req_pri_rdy_0 = _io_req_pri_rdy_T; // @[MSHR.scala:12:7, :138:27] assign _io_req_sec_rdy_T = sec_rdy & _rpq_io_enq_ready; // @[MSHR.scala:58:27, :63:19, :139:29] assign io_req_sec_rdy_0 = _io_req_sec_rdy_T; // @[MSHR.scala:12:7, :139:29] reg [1:0] meta_hazard; // @[MSHR.scala:141:28] wire [2:0] _meta_hazard_T = {1'h0, meta_hazard} + 3'h1; // @[MSHR.scala:141:28, :142:59] wire [1:0] _meta_hazard_T_1 = _meta_hazard_T[1:0]; // @[MSHR.scala:142:59] wire _io_probe_rdy_T = |state; // @[MSHR.scala:36:22, :66:75, :144:27] wire _io_probe_rdy_T_1 = _io_probe_rdy_T & probe_idx_match; // @[MSHR.scala:43:33, :144:{27,41}] wire _io_probe_rdy_T_2 = ~_io_probe_rdy_T_1; // @[MSHR.scala:144:{19,41}] wire _io_probe_rdy_T_6 = _io_probe_rdy_T_3 | _io_probe_rdy_T_4; // @[package.scala:16:47, :81:59] wire _io_probe_rdy_T_7 = _io_probe_rdy_T_6 | _io_probe_rdy_T_5; // @[package.scala:16:47, :81:59] wire _io_probe_rdy_T_8 = ~_io_probe_rdy_T_7; // @[MSHR.scala:144:65] wire _io_probe_rdy_T_9 = meta_hazard == 2'h0; // @[MSHR.scala:141:28, :144:117] wire _io_probe_rdy_T_10 = _io_probe_rdy_T_8 & _io_probe_rdy_T_9; // @[MSHR.scala:144:{65,102,117}] assign _io_probe_rdy_T_11 = _io_probe_rdy_T_2 | _io_probe_rdy_T_10; // @[MSHR.scala:144:{19,61,102}] assign io_probe_rdy_0 = _io_probe_rdy_T_11; // @[MSHR.scala:12:7, :144:61] assign _io_meta_write_valid_T_2 = _io_meta_write_valid_T | _io_meta_write_valid_T_1; // @[package.scala:16:47, :81:59] assign io_meta_write_valid_0 = _io_meta_write_valid_T_2; // @[MSHR.scala:12:7] assign _io_meta_write_bits_data_coh_T_1_state = _io_meta_write_bits_data_coh_T ? coh_on_clear_state : new_coh_state; // @[MSHR.scala:45:24, :149:{37,44}] assign io_meta_write_bits_data_coh_state_0 = _io_meta_write_bits_data_coh_T_1_state; // @[MSHR.scala:12:7, :149:37] assign io_wb_req_valid_0 = _io_wb_req_valid_T; // @[MSHR.scala:12:7, :153:28] assign _io_mem_acquire_valid_T_1 = _io_mem_acquire_valid_T & _grantackq_io_enq_ready; // @[MSHR.scala:126:25, :161:{33,50}] assign io_mem_acquire_valid_0 = _io_mem_acquire_valid_T_1; // @[MSHR.scala:12:7, :161:50] wire [25:0] _GEN_29 = {io_tag_0, req_idx}; // @[MSHR.scala:12:7, :39:25, :164:48] wire [25:0] _io_mem_acquire_bits_T; // @[MSHR.scala:164:48] assign _io_mem_acquire_bits_T = _GEN_29; // @[MSHR.scala:164:48] wire [25:0] io_replay_bits_addr_hi; // @[MSHR.scala:170:29] assign io_replay_bits_addr_hi = _GEN_29; // @[MSHR.scala:164:48, :170:29] wire [31:0] _io_mem_acquire_bits_T_1 = {_io_mem_acquire_bits_T, 6'h0}; // @[MSHR.scala:41:51, :164:{48,66}] wire [31:0] _io_mem_acquire_bits_legal_T_1 = _io_mem_acquire_bits_T_1; // @[MSHR.scala:164:66] assign io_mem_acquire_bits_a_address = _io_mem_acquire_bits_T_1; // @[MSHR.scala:164:66] wire [32:0] _io_mem_acquire_bits_legal_T_2 = {1'h0, _io_mem_acquire_bits_legal_T_1}; // @[Parameters.scala:137:{31,41}] wire [32:0] _io_mem_acquire_bits_legal_T_3 = _io_mem_acquire_bits_legal_T_2 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _io_mem_acquire_bits_legal_T_4 = _io_mem_acquire_bits_legal_T_3; // @[Parameters.scala:137:46] wire _io_mem_acquire_bits_legal_T_5 = _io_mem_acquire_bits_legal_T_4 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _io_mem_acquire_bits_legal_T_6 = {_io_mem_acquire_bits_T_1[31:17], _io_mem_acquire_bits_T_1[16:0] ^ 17'h10000}; // @[MSHR.scala:164:66] wire [32:0] _io_mem_acquire_bits_legal_T_7 = {1'h0, _io_mem_acquire_bits_legal_T_6}; // @[Parameters.scala:137:{31,41}] wire [32:0] _io_mem_acquire_bits_legal_T_8 = _io_mem_acquire_bits_legal_T_7 & 33'h8C011000; // @[Parameters.scala:137:{41,46}] wire [32:0] _io_mem_acquire_bits_legal_T_9 = _io_mem_acquire_bits_legal_T_8; // @[Parameters.scala:137:46] wire _io_mem_acquire_bits_legal_T_10 = _io_mem_acquire_bits_legal_T_9 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _io_mem_acquire_bits_legal_T_11 = {_io_mem_acquire_bits_T_1[31:28], _io_mem_acquire_bits_T_1[27:0] ^ 28'hC000000}; // @[MSHR.scala:164:66] wire [32:0] _io_mem_acquire_bits_legal_T_12 = {1'h0, _io_mem_acquire_bits_legal_T_11}; // @[Parameters.scala:137:{31,41}] wire [32:0] _io_mem_acquire_bits_legal_T_13 = _io_mem_acquire_bits_legal_T_12 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _io_mem_acquire_bits_legal_T_14 = _io_mem_acquire_bits_legal_T_13; // @[Parameters.scala:137:46] wire _io_mem_acquire_bits_legal_T_15 = _io_mem_acquire_bits_legal_T_14 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _io_mem_acquire_bits_legal_T_16 = _io_mem_acquire_bits_legal_T_5 | _io_mem_acquire_bits_legal_T_10; // @[Parameters.scala:685:42] wire _io_mem_acquire_bits_legal_T_17 = _io_mem_acquire_bits_legal_T_16 | _io_mem_acquire_bits_legal_T_15; // @[Parameters.scala:685:42] wire [31:0] _io_mem_acquire_bits_legal_T_21 = {_io_mem_acquire_bits_T_1[31:28], _io_mem_acquire_bits_T_1[27:0] ^ 28'h8000000}; // @[MSHR.scala:164:66] wire [32:0] _io_mem_acquire_bits_legal_T_22 = {1'h0, _io_mem_acquire_bits_legal_T_21}; // @[Parameters.scala:137:{31,41}] wire [32:0] _io_mem_acquire_bits_legal_T_23 = _io_mem_acquire_bits_legal_T_22 & 33'h8C010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _io_mem_acquire_bits_legal_T_24 = _io_mem_acquire_bits_legal_T_23; // @[Parameters.scala:137:46] wire _io_mem_acquire_bits_legal_T_25 = _io_mem_acquire_bits_legal_T_24 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _io_mem_acquire_bits_legal_T_26 = _io_mem_acquire_bits_T_1 ^ 32'h80000000; // @[MSHR.scala:164:66] wire [32:0] _io_mem_acquire_bits_legal_T_27 = {1'h0, _io_mem_acquire_bits_legal_T_26}; // @[Parameters.scala:137:{31,41}] wire [32:0] _io_mem_acquire_bits_legal_T_28 = _io_mem_acquire_bits_legal_T_27 & 33'h80000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _io_mem_acquire_bits_legal_T_29 = _io_mem_acquire_bits_legal_T_28; // @[Parameters.scala:137:46] wire _io_mem_acquire_bits_legal_T_30 = _io_mem_acquire_bits_legal_T_29 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _io_mem_acquire_bits_legal_T_31 = _io_mem_acquire_bits_legal_T_25 | _io_mem_acquire_bits_legal_T_30; // @[Parameters.scala:685:42] wire _io_mem_acquire_bits_legal_T_32 = _io_mem_acquire_bits_legal_T_31; // @[Parameters.scala:684:54, :685:42] wire io_mem_acquire_bits_legal = _io_mem_acquire_bits_legal_T_32; // @[Parameters.scala:684:54, :686:26] assign io_mem_acquire_bits_param_0 = io_mem_acquire_bits_a_param; // @[MSHR.scala:12:7] assign io_mem_acquire_bits_address_0 = io_mem_acquire_bits_a_address; // @[MSHR.scala:12:7] assign io_mem_acquire_bits_a_param = {1'h0, grow_param}; // @[Misc.scala:35:36] wire io_mem_acquire_bits_a_mask_sub_sub_bit = _io_mem_acquire_bits_T_1[2]; // @[MSHR.scala:164:66] wire io_mem_acquire_bits_a_mask_sub_sub_1_2 = io_mem_acquire_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire io_mem_acquire_bits_a_mask_sub_sub_nbit = ~io_mem_acquire_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire io_mem_acquire_bits_a_mask_sub_sub_0_2 = io_mem_acquire_bits_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_sub_sub_acc_T = io_mem_acquire_bits_a_mask_sub_sub_0_2; // @[Misc.scala:214:27, :215:38] wire _io_mem_acquire_bits_a_mask_sub_sub_acc_T_1 = io_mem_acquire_bits_a_mask_sub_sub_1_2; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_sub_bit = _io_mem_acquire_bits_T_1[1]; // @[MSHR.scala:164:66] wire io_mem_acquire_bits_a_mask_sub_nbit = ~io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire io_mem_acquire_bits_a_mask_sub_0_2 = io_mem_acquire_bits_a_mask_sub_sub_0_2 & io_mem_acquire_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire io_mem_acquire_bits_a_mask_sub_1_2 = io_mem_acquire_bits_a_mask_sub_sub_0_2 & io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire io_mem_acquire_bits_a_mask_sub_2_2 = io_mem_acquire_bits_a_mask_sub_sub_1_2 & io_mem_acquire_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire io_mem_acquire_bits_a_mask_sub_3_2 = io_mem_acquire_bits_a_mask_sub_sub_1_2 & io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire io_mem_acquire_bits_a_mask_bit = _io_mem_acquire_bits_T_1[0]; // @[MSHR.scala:164:66] wire io_mem_acquire_bits_a_mask_nbit = ~io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire io_mem_acquire_bits_a_mask_eq = io_mem_acquire_bits_a_mask_sub_0_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T = io_mem_acquire_bits_a_mask_eq; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_1 = io_mem_acquire_bits_a_mask_sub_0_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_1 = io_mem_acquire_bits_a_mask_eq_1; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_2 = io_mem_acquire_bits_a_mask_sub_1_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_2 = io_mem_acquire_bits_a_mask_eq_2; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_3 = io_mem_acquire_bits_a_mask_sub_1_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_3 = io_mem_acquire_bits_a_mask_eq_3; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_4 = io_mem_acquire_bits_a_mask_sub_2_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_4 = io_mem_acquire_bits_a_mask_eq_4; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_5 = io_mem_acquire_bits_a_mask_sub_2_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_5 = io_mem_acquire_bits_a_mask_eq_5; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_6 = io_mem_acquire_bits_a_mask_sub_3_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_6 = io_mem_acquire_bits_a_mask_eq_6; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_7 = io_mem_acquire_bits_a_mask_sub_3_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_7 = io_mem_acquire_bits_a_mask_eq_7; // @[Misc.scala:214:27, :215:38] assign _io_replay_valid_T_1 = _io_replay_valid_T & _rpq_io_deq_valid; // @[MSHR.scala:63:19, :168:{28,44}] assign io_replay_valid_0 = _io_replay_valid_T_1; // @[MSHR.scala:12:7, :168:44] wire [5:0] _io_replay_bits_addr_T = _rpq_io_deq_bits_addr[5:0]; // @[MSHR.scala:63:19, :170:67] wire [31:0] _io_replay_bits_addr_T_1 = {io_replay_bits_addr_hi, _io_replay_bits_addr_T}; // @[MSHR.scala:170:{29,67}] assign io_replay_bits_addr_0 = {8'h0, _io_replay_bits_addr_T_1}; // @[MSHR.scala:12:7, :170:{23,29}] wire _state_T_1 = ~_rpq_io_deq_valid; // @[MSHR.scala:63:19, :71:34, :174:26] reg state_REG; // @[MSHR.scala:174:25] wire [3:0] _state_T_2 = state_REG ? 4'h0 : state; // @[MSHR.scala:36:22, :174:{17,25}] wire _rpq_io_deq_ready_T_5 = io_replay_ready_0 & _rpq_io_deq_ready_T_4; // @[MSHR.scala:12:7, :176:{39,48}] wire _T_7 = _sec_rdy_T_6 & refill_done; // @[MSHR.scala:81:33] wire _T_15 = io_req_sec_val_0 & io_req_sec_rdy_0; // @[MSHR.scala:12:7, :97:24] always @(posedge clock) begin // @[MSHR.scala:12:7] if (reset) begin // @[MSHR.scala:12:7] state <= 4'h0; // @[MSHR.scala:36:22] new_coh_state <= 2'h0; // @[MSHR.scala:45:24] r_counter <= 9'h0; // @[Edges.scala:229:27] meta_hazard <= 2'h0; // @[MSHR.scala:141:28] end else begin // @[MSHR.scala:12:7] if (_T_19 & ~_rpq_io_deq_valid) // @[MSHR.scala:63:19, :66:49, :71:34, :173:31] state <= _state_T_2; // @[MSHR.scala:36:22, :174:17] else if (_rpq_io_enq_valid_T) // @[MSHR.scala:64:39] state <= io_req_bits_tag_match_0 ? {2'h1, is_hit, 1'h0} : _state_T; // @[MSHR.scala:12:7, :36:22, :112:34, :113:21, :115:15, :118:15, :122:{13,19}] else if (io_wb_req_ready_0 & io_wb_req_valid_0) // @[Decoupled.scala:51:35] state <= 4'h2; // @[MSHR.scala:36:22] else if (_T_11 & io_wb_req_ready_0 & acked) // @[MSHR.scala:12:7, :68:18, :91:{29,48}] state <= 4'h3; // @[MSHR.scala:36:22] else if (_T_9 & io_meta_write_ready_0) // @[MSHR.scala:12:7, :88:32] state <= 4'h4; // @[MSHR.scala:36:22] else if (io_mem_acquire_ready_0 & io_mem_acquire_valid_0) // @[Decoupled.scala:51:35] state <= 4'h5; // @[MSHR.scala:36:22] else if (_T_7) // @[MSHR.scala:81:33] state <= 4'h6; // @[MSHR.scala:36:22] else if (_io_meta_write_valid_T & io_meta_write_ready_0) // @[MSHR.scala:12:7, :78:36] state <= 4'h7; // @[MSHR.scala:36:22] else if (state == 4'h7) // @[MSHR.scala:36:22, :74:15] state <= 4'h8; // @[MSHR.scala:36:22] else if (_T_19 & ~_rpq_io_deq_valid) // @[MSHR.scala:63:19, :66:49, :71:{31,34}] state <= 4'h0; // @[MSHR.scala:36:22] if (_rpq_io_enq_valid_T) // @[MSHR.scala:64:39] new_coh_state <= io_req_bits_tag_match_0 ? (is_hit ? coh_on_hit_state : io_req_bits_old_meta_coh_state_0) : 2'h0; // @[MSHR.scala:12:7, :45:24, :112:34, :113:21, :114:17, :117:17, :121:15] else if (_T_15 & is_hit_again) // @[MSHR.scala:81:49, :97:{24,43}, :102:25, :103:15] new_coh_state <= dirtier_coh_state; // @[MSHR.scala:45:24] else if (_T_7) // @[MSHR.scala:81:33] new_coh_state <= coh_on_grant_state; // @[MSHR.scala:45:24] if (io_mem_grant_valid_0) // @[MSHR.scala:12:7] r_counter <= _r_counter_T; // @[Edges.scala:229:27, :236:21] if (io_meta_write_ready_0 & io_meta_write_valid_0) // @[Decoupled.scala:51:35] meta_hazard <= 2'h1; // @[MSHR.scala:141:28] else if (|meta_hazard) // @[MSHR.scala:141:28, :142:21] meta_hazard <= _meta_hazard_T_1; // @[MSHR.scala:141:28, :142:59] end if (_rpq_io_enq_valid_T) begin // @[MSHR.scala:64:39] req_addr <= io_req_bits_addr_0; // @[MSHR.scala:12:7, :38:16] req_tag <= io_req_bits_tag_0; // @[MSHR.scala:12:7, :38:16] req_cmd <= io_req_bits_cmd_0; // @[MSHR.scala:12:7, :38:16] req_size <= io_req_bits_size_0; // @[MSHR.scala:12:7, :38:16] req_signed <= io_req_bits_signed_0; // @[MSHR.scala:12:7, :38:16] req_data <= io_req_bits_data_0; // @[MSHR.scala:12:7, :38:16] req_mask <= io_req_bits_mask_0; // @[MSHR.scala:12:7, :38:16] req_tag_match <= io_req_bits_tag_match_0; // @[MSHR.scala:12:7, :38:16] req_old_meta_coh_state <= io_req_bits_old_meta_coh_state_0; // @[MSHR.scala:12:7, :38:16] req_old_meta_tag <= io_req_bits_old_meta_tag_0; // @[MSHR.scala:12:7, :38:16] req_way_en <= io_req_bits_way_en_0; // @[MSHR.scala:12:7, :38:16] req_sdq_id <= io_req_bits_sdq_id_0; // @[MSHR.scala:12:7, :38:16] end else if (_T_15) // @[MSHR.scala:97:24] req_cmd <= dirtier_cmd; // @[MSHR.scala:38:16] acked <= ~_rpq_io_enq_valid_T & (io_mem_grant_valid_0 | acked); // @[MSHR.scala:12:7, :64:39, :68:18, :69:{29,37}, :106:43, :108:11] state_REG <= _state_T_1; // @[MSHR.scala:174:{25,26}] always @(posedge) Queue16_ShuttleMSHRReq_3 rpq ( // @[MSHR.scala:63:19] .clock (clock), .reset (reset), .io_enq_ready (_rpq_io_enq_ready), .io_enq_valid (_rpq_io_enq_valid_T_7), // @[MSHR.scala:64:87] .io_enq_bits_addr (io_req_bits_addr_0), // @[MSHR.scala:12:7] .io_enq_bits_tag (io_req_bits_tag_0), // @[MSHR.scala:12:7] .io_enq_bits_cmd (io_req_bits_cmd_0), // @[MSHR.scala:12:7] .io_enq_bits_size (io_req_bits_size_0), // @[MSHR.scala:12:7] .io_enq_bits_signed (io_req_bits_signed_0), // @[MSHR.scala:12:7] .io_enq_bits_data (io_req_bits_data_0), // @[MSHR.scala:12:7] .io_enq_bits_mask (io_req_bits_mask_0), // @[MSHR.scala:12:7] .io_enq_bits_tag_match (io_req_bits_tag_match_0), // @[MSHR.scala:12:7] .io_enq_bits_old_meta_coh_state (io_req_bits_old_meta_coh_state_0), // @[MSHR.scala:12:7] .io_enq_bits_old_meta_tag (io_req_bits_old_meta_tag_0), // @[MSHR.scala:12:7] .io_enq_bits_way_en (io_req_bits_way_en_0), // @[MSHR.scala:12:7] .io_enq_bits_sdq_id (io_req_bits_sdq_id_0), // @[MSHR.scala:12:7] .io_deq_ready (_rpq_io_deq_ready_T_5), // @[MSHR.scala:176:39] .io_deq_valid (_rpq_io_deq_valid), .io_deq_bits_addr (_rpq_io_deq_bits_addr), .io_deq_bits_tag (io_replay_bits_tag_0), .io_deq_bits_cmd (io_replay_bits_cmd_0), .io_deq_bits_size (io_replay_bits_size_0), .io_deq_bits_signed (io_replay_bits_signed_0), .io_deq_bits_data (io_replay_bits_data_0), .io_deq_bits_mask (io_replay_bits_mask_0), .io_deq_bits_tag_match (io_replay_bits_tag_match_0), .io_deq_bits_old_meta_coh_state (io_replay_bits_old_meta_coh_state_0), .io_deq_bits_old_meta_tag (io_replay_bits_old_meta_tag_0), .io_deq_bits_way_en (io_replay_bits_way_en_0), .io_deq_bits_sdq_id (io_replay_bits_sdq_id_0) ); // @[MSHR.scala:63:19] Queue1_TLBundleE_a32d64s3k3z4c_3 grantackq ( // @[MSHR.scala:126:25] .clock (clock), .reset (reset), .io_enq_ready (_grantackq_io_enq_ready), .io_enq_valid (_grantackq_io_enq_valid_T_4), // @[MSHR.scala:128:41] .io_enq_bits_sink (grantackq_io_enq_bits_e_sink), // @[Edges.scala:451:17] .io_deq_ready (_grantackq_io_deq_ready_T), // @[MSHR.scala:132:49] .io_deq_valid (_grantackq_io_deq_valid), .io_deq_bits_sink (io_mem_finish_bits_sink_0) ); // @[MSHR.scala:126:25] assign io_req_pri_rdy = io_req_pri_rdy_0; // @[MSHR.scala:12:7] assign io_req_sec_rdy = io_req_sec_rdy_0; // @[MSHR.scala:12:7] assign io_idx_match = io_idx_match_0; // @[MSHR.scala:12:7] assign io_tag = io_tag_0; // @[MSHR.scala:12:7] assign io_mem_acquire_valid = io_mem_acquire_valid_0; // @[MSHR.scala:12:7] assign io_mem_acquire_bits_param = io_mem_acquire_bits_param_0; // @[MSHR.scala:12:7] assign io_mem_acquire_bits_address = io_mem_acquire_bits_address_0; // @[MSHR.scala:12:7] assign io_mem_finish_valid = io_mem_finish_valid_0; // @[MSHR.scala:12:7] assign io_mem_finish_bits_sink = io_mem_finish_bits_sink_0; // @[MSHR.scala:12:7] assign io_refill_way_en = io_refill_way_en_0; // @[MSHR.scala:12:7] assign io_refill_addr = io_refill_addr_0; // @[MSHR.scala:12:7] assign io_meta_write_valid = io_meta_write_valid_0; // @[MSHR.scala:12:7] assign io_meta_write_bits_idx = io_meta_write_bits_idx_0; // @[MSHR.scala:12:7] assign io_meta_write_bits_way_en = io_meta_write_bits_way_en_0; // @[MSHR.scala:12:7] assign io_meta_write_bits_tag = io_meta_write_bits_tag_0; // @[MSHR.scala:12:7] assign io_meta_write_bits_data_coh_state = io_meta_write_bits_data_coh_state_0; // @[MSHR.scala:12:7] assign io_meta_write_bits_data_tag = io_meta_write_bits_data_tag_0; // @[MSHR.scala:12:7] assign io_replay_valid = io_replay_valid_0; // @[MSHR.scala:12:7] assign io_replay_bits_addr = io_replay_bits_addr_0; // @[MSHR.scala:12:7] assign io_replay_bits_tag = io_replay_bits_tag_0; // @[MSHR.scala:12:7] assign io_replay_bits_cmd = io_replay_bits_cmd_0; // @[MSHR.scala:12:7] assign io_replay_bits_size = io_replay_bits_size_0; // @[MSHR.scala:12:7] assign io_replay_bits_signed = io_replay_bits_signed_0; // @[MSHR.scala:12:7] assign io_replay_bits_data = io_replay_bits_data_0; // @[MSHR.scala:12:7] assign io_replay_bits_mask = io_replay_bits_mask_0; // @[MSHR.scala:12:7] assign io_replay_bits_tag_match = io_replay_bits_tag_match_0; // @[MSHR.scala:12:7] assign io_replay_bits_old_meta_coh_state = io_replay_bits_old_meta_coh_state_0; // @[MSHR.scala:12:7] assign io_replay_bits_old_meta_tag = io_replay_bits_old_meta_tag_0; // @[MSHR.scala:12:7] assign io_replay_bits_way_en = io_replay_bits_way_en_0; // @[MSHR.scala:12:7] assign io_replay_bits_sdq_id = io_replay_bits_sdq_id_0; // @[MSHR.scala:12:7] assign io_wb_req_valid = io_wb_req_valid_0; // @[MSHR.scala:12:7] assign io_wb_req_bits_tag = io_wb_req_bits_tag_0; // @[MSHR.scala:12:7] assign io_wb_req_bits_idx = io_wb_req_bits_idx_0; // @[MSHR.scala:12:7] assign io_wb_req_bits_param = io_wb_req_bits_param_0; // @[MSHR.scala:12:7] assign io_wb_req_bits_way_en = io_wb_req_bits_way_en_0; // @[MSHR.scala:12:7] assign io_probe_rdy = io_probe_rdy_0; // @[MSHR.scala:12:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }

module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_40( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)

Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File FPU.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.tile import chisel3._ import chisel3.util._ import chisel3.{DontCare, WireInit, withClock, withReset} import chisel3.experimental.SourceInfo import chisel3.experimental.dataview._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.rocket._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property case class FPUParams( minFLen: Int = 32, fLen: Int = 64, divSqrt: Boolean = true, sfmaLatency: Int = 3, dfmaLatency: Int = 4, fpmuLatency: Int = 2, ifpuLatency: Int = 2 ) object FPConstants { val RM_SZ = 3 val FLAGS_SZ = 5 } trait HasFPUCtrlSigs { val ldst = Bool() val wen = Bool() val ren1 = Bool() val ren2 = Bool() val ren3 = Bool() val swap12 = Bool() val swap23 = Bool() val typeTagIn = UInt(2.W) val typeTagOut = UInt(2.W) val fromint = Bool() val toint = Bool() val fastpipe = Bool() val fma = Bool() val div = Bool() val sqrt = Bool() val wflags = Bool() val vec = Bool() } class FPUCtrlSigs extends Bundle with HasFPUCtrlSigs class FPUDecoder(implicit p: Parameters) extends FPUModule()(p) { val io = IO(new Bundle { val inst = Input(Bits(32.W)) val sigs = Output(new FPUCtrlSigs()) }) private val X2 = BitPat.dontCare(2) val default = List(X,X,X,X,X,X,X,X2,X2,X,X,X,X,X,X,X,N) val h: Array[(BitPat, List[BitPat])] = Array(FLH -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N), FSH -> List(Y,N,N,Y,N,Y,X, I, H,N,Y,N,N,N,N,N,N), FMV_H_X -> List(N,Y,N,N,N,X,X, H, I,Y,N,N,N,N,N,N,N), FCVT_H_W -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FCVT_H_WU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FCVT_H_L -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FCVT_H_LU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FMV_X_H -> List(N,N,Y,N,N,N,X, I, H,N,Y,N,N,N,N,N,N), FCLASS_H -> List(N,N,Y,N,N,N,X, H, H,N,Y,N,N,N,N,N,N), FCVT_W_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_WU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_L_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_LU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_S_H -> List(N,Y,Y,N,N,N,X, H, S,N,N,Y,N,N,N,Y,N), FCVT_H_S -> List(N,Y,Y,N,N,N,X, S, H,N,N,Y,N,N,N,Y,N), FEQ_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N), FLT_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N), FLE_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N), FSGNJ_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N), FSGNJN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N), FSGNJX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N), FMIN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N), FMAX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N), FADD_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N), FSUB_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N), FMUL_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,Y,N,N,Y,N), FMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FNMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FNMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FDIV_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,N,Y,N,Y,N), FSQRT_H -> List(N,Y,Y,N,N,N,X, H, H,N,N,N,N,N,Y,Y,N)) val f: Array[(BitPat, List[BitPat])] = Array(FLW -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N), FSW -> List(Y,N,N,Y,N,Y,X, I, S,N,Y,N,N,N,N,N,N), FMV_W_X -> List(N,Y,N,N,N,X,X, S, I,Y,N,N,N,N,N,N,N), FCVT_S_W -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FCVT_S_WU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FCVT_S_L -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FCVT_S_LU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FMV_X_W -> List(N,N,Y,N,N,N,X, I, S,N,Y,N,N,N,N,N,N), FCLASS_S -> List(N,N,Y,N,N,N,X, S, S,N,Y,N,N,N,N,N,N), FCVT_W_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FCVT_WU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FCVT_L_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FCVT_LU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FEQ_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N), FLT_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N), FLE_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N), FSGNJ_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N), FSGNJN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N), FSGNJX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N), FMIN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N), FMAX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N), FADD_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N), FSUB_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N), FMUL_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,Y,N,N,Y,N), FMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FNMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FNMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FDIV_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,N,Y,N,Y,N), FSQRT_S -> List(N,Y,Y,N,N,N,X, S, S,N,N,N,N,N,Y,Y,N)) val d: Array[(BitPat, List[BitPat])] = Array(FLD -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N), FSD -> List(Y,N,N,Y,N,Y,X, I, D,N,Y,N,N,N,N,N,N), FMV_D_X -> List(N,Y,N,N,N,X,X, D, I,Y,N,N,N,N,N,N,N), FCVT_D_W -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FCVT_D_WU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FCVT_D_L -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FCVT_D_LU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FMV_X_D -> List(N,N,Y,N,N,N,X, I, D,N,Y,N,N,N,N,N,N), FCLASS_D -> List(N,N,Y,N,N,N,X, D, D,N,Y,N,N,N,N,N,N), FCVT_W_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_WU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_L_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_LU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_S_D -> List(N,Y,Y,N,N,N,X, D, S,N,N,Y,N,N,N,Y,N), FCVT_D_S -> List(N,Y,Y,N,N,N,X, S, D,N,N,Y,N,N,N,Y,N), FEQ_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N), FLT_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N), FLE_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N), FSGNJ_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N), FSGNJN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N), FSGNJX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N), FMIN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N), FMAX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N), FADD_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N), FSUB_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N), FMUL_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,Y,N,N,Y,N), FMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FNMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FNMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FDIV_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,N,Y,N,Y,N), FSQRT_D -> List(N,Y,Y,N,N,N,X, D, D,N,N,N,N,N,Y,Y,N)) val fcvt_hd: Array[(BitPat, List[BitPat])] = Array(FCVT_H_D -> List(N,Y,Y,N,N,N,X, D, H,N,N,Y,N,N,N,Y,N), FCVT_D_H -> List(N,Y,Y,N,N,N,X, H, D,N,N,Y,N,N,N,Y,N)) val vfmv_f_s: Array[(BitPat, List[BitPat])] = Array(VFMV_F_S -> List(N,Y,N,N,N,N,X,X2,X2,N,N,N,N,N,N,N,Y)) val insns = ((minFLen, fLen) match { case (32, 32) => f case (16, 32) => h ++ f case (32, 64) => f ++ d case (16, 64) => h ++ f ++ d ++ fcvt_hd case other => throw new Exception(s"minFLen = ${minFLen} & fLen = ${fLen} is an unsupported configuration") }) ++ (if (usingVector) vfmv_f_s else Array[(BitPat, List[BitPat])]()) val decoder = DecodeLogic(io.inst, default, insns) val s = io.sigs val sigs = Seq(s.ldst, s.wen, s.ren1, s.ren2, s.ren3, s.swap12, s.swap23, s.typeTagIn, s.typeTagOut, s.fromint, s.toint, s.fastpipe, s.fma, s.div, s.sqrt, s.wflags, s.vec) sigs zip decoder map {case(s,d) => s := d} } class FPUCoreIO(implicit p: Parameters) extends CoreBundle()(p) { val hartid = Input(UInt(hartIdLen.W)) val time = Input(UInt(xLen.W)) val inst = Input(Bits(32.W)) val fromint_data = Input(Bits(xLen.W)) val fcsr_rm = Input(Bits(FPConstants.RM_SZ.W)) val fcsr_flags = Valid(Bits(FPConstants.FLAGS_SZ.W)) val v_sew = Input(UInt(3.W)) val store_data = Output(Bits(fLen.W)) val toint_data = Output(Bits(xLen.W)) val ll_resp_val = Input(Bool()) val ll_resp_type = Input(Bits(3.W)) val ll_resp_tag = Input(UInt(5.W)) val ll_resp_data = Input(Bits(fLen.W)) val valid = Input(Bool()) val fcsr_rdy = Output(Bool()) val nack_mem = Output(Bool()) val illegal_rm = Output(Bool()) val killx = Input(Bool()) val killm = Input(Bool()) val dec = Output(new FPUCtrlSigs()) val sboard_set = Output(Bool()) val sboard_clr = Output(Bool()) val sboard_clra = Output(UInt(5.W)) val keep_clock_enabled = Input(Bool()) } class FPUIO(implicit p: Parameters) extends FPUCoreIO ()(p) { val cp_req = Flipped(Decoupled(new FPInput())) //cp doesn't pay attn to kill sigs val cp_resp = Decoupled(new FPResult()) } class FPResult(implicit p: Parameters) extends CoreBundle()(p) { val data = Bits((fLen+1).W) val exc = Bits(FPConstants.FLAGS_SZ.W) } class IntToFPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs { val rm = Bits(FPConstants.RM_SZ.W) val typ = Bits(2.W) val in1 = Bits(xLen.W) } class FPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs { val rm = Bits(FPConstants.RM_SZ.W) val fmaCmd = Bits(2.W) val typ = Bits(2.W) val fmt = Bits(2.W) val in1 = Bits((fLen+1).W) val in2 = Bits((fLen+1).W) val in3 = Bits((fLen+1).W) } case class FType(exp: Int, sig: Int) { def ieeeWidth = exp + sig def recodedWidth = ieeeWidth + 1 def ieeeQNaN = ((BigInt(1) << (ieeeWidth - 1)) - (BigInt(1) << (sig - 2))).U(ieeeWidth.W) def qNaN = ((BigInt(7) << (exp + sig - 3)) + (BigInt(1) << (sig - 2))).U(recodedWidth.W) def isNaN(x: UInt) = x(sig + exp - 1, sig + exp - 3).andR def isSNaN(x: UInt) = isNaN(x) && !x(sig - 2) def classify(x: UInt) = { val sign = x(sig + exp) val code = x(exp + sig - 1, exp + sig - 3) val codeHi = code(2, 1) val isSpecial = codeHi === 3.U val isHighSubnormalIn = x(exp + sig - 3, sig - 1) < 2.U val isSubnormal = code === 1.U || codeHi === 1.U && isHighSubnormalIn val isNormal = codeHi === 1.U && !isHighSubnormalIn || codeHi === 2.U val isZero = code === 0.U val isInf = isSpecial && !code(0) val isNaN = code.andR val isSNaN = isNaN && !x(sig-2) val isQNaN = isNaN && x(sig-2) Cat(isQNaN, isSNaN, isInf && !sign, isNormal && !sign, isSubnormal && !sign, isZero && !sign, isZero && sign, isSubnormal && sign, isNormal && sign, isInf && sign) } // convert between formats, ignoring rounding, range, NaN def unsafeConvert(x: UInt, to: FType) = if (this == to) x else { val sign = x(sig + exp) val fractIn = x(sig - 2, 0) val expIn = x(sig + exp - 1, sig - 1) val fractOut = fractIn << to.sig >> sig val expOut = { val expCode = expIn(exp, exp - 2) val commonCase = (expIn + (1 << to.exp).U) - (1 << exp).U Mux(expCode === 0.U || expCode >= 6.U, Cat(expCode, commonCase(to.exp - 3, 0)), commonCase(to.exp, 0)) } Cat(sign, expOut, fractOut) } private def ieeeBundle = { val expWidth = exp class IEEEBundle extends Bundle { val sign = Bool() val exp = UInt(expWidth.W) val sig = UInt((ieeeWidth-expWidth-1).W) } new IEEEBundle } def unpackIEEE(x: UInt) = x.asTypeOf(ieeeBundle) def recode(x: UInt) = hardfloat.recFNFromFN(exp, sig, x) def ieee(x: UInt) = hardfloat.fNFromRecFN(exp, sig, x) } object FType { val H = new FType(5, 11) val S = new FType(8, 24) val D = new FType(11, 53) val all = List(H, S, D) } trait HasFPUParameters { require(fLen == 0 || FType.all.exists(_.ieeeWidth == fLen)) val minFLen: Int val fLen: Int def xLen: Int val minXLen = 32 val nIntTypes = log2Ceil(xLen/minXLen) + 1 def floatTypes = FType.all.filter(t => minFLen <= t.ieeeWidth && t.ieeeWidth <= fLen) def minType = floatTypes.head def maxType = floatTypes.last def prevType(t: FType) = floatTypes(typeTag(t) - 1) def maxExpWidth = maxType.exp def maxSigWidth = maxType.sig def typeTag(t: FType) = floatTypes.indexOf(t) def typeTagWbOffset = (FType.all.indexOf(minType) + 1).U def typeTagGroup(t: FType) = (if (floatTypes.contains(t)) typeTag(t) else typeTag(maxType)).U // typeTag def H = typeTagGroup(FType.H) def S = typeTagGroup(FType.S) def D = typeTagGroup(FType.D) def I = typeTag(maxType).U private def isBox(x: UInt, t: FType): Bool = x(t.sig + t.exp, t.sig + t.exp - 4).andR private def box(x: UInt, xt: FType, y: UInt, yt: FType): UInt = { require(xt.ieeeWidth == 2 * yt.ieeeWidth) val swizzledNaN = Cat( x(xt.sig + xt.exp, xt.sig + xt.exp - 3), x(xt.sig - 2, yt.recodedWidth - 1).andR, x(xt.sig + xt.exp - 5, xt.sig), y(yt.recodedWidth - 2), x(xt.sig - 2, yt.recodedWidth - 1), y(yt.recodedWidth - 1), y(yt.recodedWidth - 3, 0)) Mux(xt.isNaN(x), swizzledNaN, x) } // implement NaN unboxing for FU inputs def unbox(x: UInt, tag: UInt, exactType: Option[FType]): UInt = { val outType = exactType.getOrElse(maxType) def helper(x: UInt, t: FType): Seq[(Bool, UInt)] = { val prev = if (t == minType) { Seq() } else { val prevT = prevType(t) val unswizzled = Cat( x(prevT.sig + prevT.exp - 1), x(t.sig - 1), x(prevT.sig + prevT.exp - 2, 0)) val prev = helper(unswizzled, prevT) val isbox = isBox(x, t) prev.map(p => (isbox && p._1, p._2)) } prev :+ (true.B, t.unsafeConvert(x, outType)) } val (oks, floats) = helper(x, maxType).unzip if (exactType.isEmpty || floatTypes.size == 1) { Mux(oks(tag), floats(tag), maxType.qNaN) } else { val t = exactType.get floats(typeTag(t)) | Mux(oks(typeTag(t)), 0.U, t.qNaN) } } // make sure that the redundant bits in the NaN-boxed encoding are consistent def consistent(x: UInt): Bool = { def helper(x: UInt, t: FType): Bool = if (typeTag(t) == 0) true.B else { val prevT = prevType(t) val unswizzled = Cat( x(prevT.sig + prevT.exp - 1), x(t.sig - 1), x(prevT.sig + prevT.exp - 2, 0)) val prevOK = !isBox(x, t) || helper(unswizzled, prevT) val curOK = !t.isNaN(x) || x(t.sig + t.exp - 4) === x(t.sig - 2, prevT.recodedWidth - 1).andR prevOK && curOK } helper(x, maxType) } // generate a NaN box from an FU result def box(x: UInt, t: FType): UInt = { if (t == maxType) { x } else { val nt = floatTypes(typeTag(t) + 1) val bigger = box(((BigInt(1) << nt.recodedWidth)-1).U, nt, x, t) bigger | ((BigInt(1) << maxType.recodedWidth) - (BigInt(1) << nt.recodedWidth)).U } } // generate a NaN box from an FU result def box(x: UInt, tag: UInt): UInt = { val opts = floatTypes.map(t => box(x, t)) opts(tag) } // zap bits that hardfloat thinks are don't-cares, but we do care about def sanitizeNaN(x: UInt, t: FType): UInt = { if (typeTag(t) == 0) { x } else { val maskedNaN = x & ~((BigInt(1) << (t.sig-1)) | (BigInt(1) << (t.sig+t.exp-4))).U(t.recodedWidth.W) Mux(t.isNaN(x), maskedNaN, x) } } // implement NaN boxing and recoding for FL*/fmv.*.x def recode(x: UInt, tag: UInt): UInt = { def helper(x: UInt, t: FType): UInt = { if (typeTag(t) == 0) { t.recode(x) } else { val prevT = prevType(t) box(t.recode(x), t, helper(x, prevT), prevT) } } // fill MSBs of subword loads to emulate a wider load of a NaN-boxed value val boxes = floatTypes.map(t => ((BigInt(1) << maxType.ieeeWidth) - (BigInt(1) << t.ieeeWidth)).U) helper(boxes(tag) | x, maxType) } // implement NaN unboxing and un-recoding for FS*/fmv.x.* def ieee(x: UInt, t: FType = maxType): UInt = { if (typeTag(t) == 0) { t.ieee(x) } else { val unrecoded = t.ieee(x) val prevT = prevType(t) val prevRecoded = Cat( x(prevT.recodedWidth-2), x(t.sig-1), x(prevT.recodedWidth-3, 0)) val prevUnrecoded = ieee(prevRecoded, prevT) Cat(unrecoded >> prevT.ieeeWidth, Mux(t.isNaN(x), prevUnrecoded, unrecoded(prevT.ieeeWidth-1, 0))) } } } abstract class FPUModule(implicit val p: Parameters) extends Module with HasCoreParameters with HasFPUParameters class FPToInt(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { class Output extends Bundle { val in = new FPInput val lt = Bool() val store = Bits(fLen.W) val toint = Bits(xLen.W) val exc = Bits(FPConstants.FLAGS_SZ.W) } val io = IO(new Bundle { val in = Flipped(Valid(new FPInput)) val out = Valid(new Output) }) val in = RegEnable(io.in.bits, io.in.valid) val valid = RegNext(io.in.valid) val dcmp = Module(new hardfloat.CompareRecFN(maxExpWidth, maxSigWidth)) dcmp.io.a := in.in1 dcmp.io.b := in.in2 dcmp.io.signaling := !in.rm(1) val tag = in.typeTagOut val toint_ieee = (floatTypes.map(t => if (t == FType.H) Fill(maxType.ieeeWidth / minXLen, ieee(in.in1)(15, 0).sextTo(minXLen)) else Fill(maxType.ieeeWidth / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag) val toint = WireDefault(toint_ieee) val intType = WireDefault(in.fmt(0)) io.out.bits.store := (floatTypes.map(t => Fill(fLen / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag) io.out.bits.toint := ((0 until nIntTypes).map(i => toint((minXLen << i) - 1, 0).sextTo(xLen)): Seq[UInt])(intType) io.out.bits.exc := 0.U when (in.rm(0)) { val classify_out = (floatTypes.map(t => t.classify(maxType.unsafeConvert(in.in1, t))): Seq[UInt])(tag) toint := classify_out | (toint_ieee >> minXLen << minXLen) intType := false.B } when (in.wflags) { // feq/flt/fle, fcvt toint := (~in.rm & Cat(dcmp.io.lt, dcmp.io.eq)).orR | (toint_ieee >> minXLen << minXLen) io.out.bits.exc := dcmp.io.exceptionFlags intType := false.B when (!in.ren2) { // fcvt val cvtType = in.typ.extract(log2Ceil(nIntTypes), 1) intType := cvtType val conv = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, xLen)) conv.io.in := in.in1 conv.io.roundingMode := in.rm conv.io.signedOut := ~in.typ(0) toint := conv.io.out io.out.bits.exc := Cat(conv.io.intExceptionFlags(2, 1).orR, 0.U(3.W), conv.io.intExceptionFlags(0)) for (i <- 0 until nIntTypes-1) { val w = minXLen << i when (cvtType === i.U) { val narrow = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, w)) narrow.io.in := in.in1 narrow.io.roundingMode := in.rm narrow.io.signedOut := ~in.typ(0) val excSign = in.in1(maxExpWidth + maxSigWidth) && !maxType.isNaN(in.in1) val excOut = Cat(conv.io.signedOut === excSign, Fill(w-1, !excSign)) val invalid = conv.io.intExceptionFlags(2) || narrow.io.intExceptionFlags(1) when (invalid) { toint := Cat(conv.io.out >> w, excOut) } io.out.bits.exc := Cat(invalid, 0.U(3.W), !invalid && conv.io.intExceptionFlags(0)) } } } } io.out.valid := valid io.out.bits.lt := dcmp.io.lt || (dcmp.io.a.asSInt < 0.S && dcmp.io.b.asSInt >= 0.S) io.out.bits.in := in } class IntToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { val io = IO(new Bundle { val in = Flipped(Valid(new IntToFPInput)) val out = Valid(new FPResult) }) val in = Pipe(io.in) val tag = in.bits.typeTagIn val mux = Wire(new FPResult) mux.exc := 0.U mux.data := recode(in.bits.in1, tag) val intValue = { val res = WireDefault(in.bits.in1.asSInt) for (i <- 0 until nIntTypes-1) { val smallInt = in.bits.in1((minXLen << i) - 1, 0) when (in.bits.typ.extract(log2Ceil(nIntTypes), 1) === i.U) { res := Mux(in.bits.typ(0), smallInt.zext, smallInt.asSInt) } } res.asUInt } when (in.bits.wflags) { // fcvt // could be improved for RVD/RVQ with a single variable-position rounding // unit, rather than N fixed-position ones val i2fResults = for (t <- floatTypes) yield { val i2f = Module(new hardfloat.INToRecFN(xLen, t.exp, t.sig)) i2f.io.signedIn := ~in.bits.typ(0) i2f.io.in := intValue i2f.io.roundingMode := in.bits.rm i2f.io.detectTininess := hardfloat.consts.tininess_afterRounding (sanitizeNaN(i2f.io.out, t), i2f.io.exceptionFlags) } val (data, exc) = i2fResults.unzip val dataPadded = data.init.map(d => Cat(data.last >> d.getWidth, d)) :+ data.last mux.data := dataPadded(tag) mux.exc := exc(tag) } io.out <> Pipe(in.valid, mux, latency-1) } class FPToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { val io = IO(new Bundle { val in = Flipped(Valid(new FPInput)) val out = Valid(new FPResult) val lt = Input(Bool()) // from FPToInt }) val in = Pipe(io.in) val signNum = Mux(in.bits.rm(1), in.bits.in1 ^ in.bits.in2, Mux(in.bits.rm(0), ~in.bits.in2, in.bits.in2)) val fsgnj = Cat(signNum(fLen), in.bits.in1(fLen-1, 0)) val fsgnjMux = Wire(new FPResult) fsgnjMux.exc := 0.U fsgnjMux.data := fsgnj when (in.bits.wflags) { // fmin/fmax val isnan1 = maxType.isNaN(in.bits.in1) val isnan2 = maxType.isNaN(in.bits.in2) val isInvalid = maxType.isSNaN(in.bits.in1) || maxType.isSNaN(in.bits.in2) val isNaNOut = isnan1 && isnan2 val isLHS = isnan2 || in.bits.rm(0) =/= io.lt && !isnan1 fsgnjMux.exc := isInvalid << 4 fsgnjMux.data := Mux(isNaNOut, maxType.qNaN, Mux(isLHS, in.bits.in1, in.bits.in2)) } val inTag = in.bits.typeTagIn val outTag = in.bits.typeTagOut val mux = WireDefault(fsgnjMux) for (t <- floatTypes.init) { when (outTag === typeTag(t).U) { mux.data := Cat(fsgnjMux.data >> t.recodedWidth, maxType.unsafeConvert(fsgnjMux.data, t)) } } when (in.bits.wflags && !in.bits.ren2) { // fcvt if (floatTypes.size > 1) { // widening conversions simply canonicalize NaN operands val widened = Mux(maxType.isNaN(in.bits.in1), maxType.qNaN, in.bits.in1) fsgnjMux.data := widened fsgnjMux.exc := maxType.isSNaN(in.bits.in1) << 4 // narrowing conversions require rounding (for RVQ, this could be // optimized to use a single variable-position rounding unit, rather // than two fixed-position ones) for (outType <- floatTypes.init) when (outTag === typeTag(outType).U && ((typeTag(outType) == 0).B || outTag < inTag)) { val narrower = Module(new hardfloat.RecFNToRecFN(maxType.exp, maxType.sig, outType.exp, outType.sig)) narrower.io.in := in.bits.in1 narrower.io.roundingMode := in.bits.rm narrower.io.detectTininess := hardfloat.consts.tininess_afterRounding val narrowed = sanitizeNaN(narrower.io.out, outType) mux.data := Cat(fsgnjMux.data >> narrowed.getWidth, narrowed) mux.exc := narrower.io.exceptionFlags } } } io.out <> Pipe(in.valid, mux, latency-1) } class MulAddRecFNPipe(latency: Int, expWidth: Int, sigWidth: Int) extends Module { override def desiredName = s"MulAddRecFNPipe_l${latency}_e${expWidth}_s${sigWidth}" require(latency<=2) val io = IO(new Bundle { val validin = Input(Bool()) val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) val validout = Output(Bool()) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val mulAddRecFNToRaw_preMul = Module(new hardfloat.MulAddRecFNToRaw_preMul(expWidth, sigWidth)) val mulAddRecFNToRaw_postMul = Module(new hardfloat.MulAddRecFNToRaw_postMul(expWidth, sigWidth)) mulAddRecFNToRaw_preMul.io.op := io.op mulAddRecFNToRaw_preMul.io.a := io.a mulAddRecFNToRaw_preMul.io.b := io.b mulAddRecFNToRaw_preMul.io.c := io.c val mulAddResult = (mulAddRecFNToRaw_preMul.io.mulAddA * mulAddRecFNToRaw_preMul.io.mulAddB) +& mulAddRecFNToRaw_preMul.io.mulAddC val valid_stage0 = Wire(Bool()) val roundingMode_stage0 = Wire(UInt(3.W)) val detectTininess_stage0 = Wire(UInt(1.W)) val postmul_regs = if(latency>0) 1 else 0 mulAddRecFNToRaw_postMul.io.fromPreMul := Pipe(io.validin, mulAddRecFNToRaw_preMul.io.toPostMul, postmul_regs).bits mulAddRecFNToRaw_postMul.io.mulAddResult := Pipe(io.validin, mulAddResult, postmul_regs).bits mulAddRecFNToRaw_postMul.io.roundingMode := Pipe(io.validin, io.roundingMode, postmul_regs).bits roundingMode_stage0 := Pipe(io.validin, io.roundingMode, postmul_regs).bits detectTininess_stage0 := Pipe(io.validin, io.detectTininess, postmul_regs).bits valid_stage0 := Pipe(io.validin, false.B, postmul_regs).valid //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundRawFNToRecFN = Module(new hardfloat.RoundRawFNToRecFN(expWidth, sigWidth, 0)) val round_regs = if(latency==2) 1 else 0 roundRawFNToRecFN.io.invalidExc := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.invalidExc, round_regs).bits roundRawFNToRecFN.io.in := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.rawOut, round_regs).bits roundRawFNToRecFN.io.roundingMode := Pipe(valid_stage0, roundingMode_stage0, round_regs).bits roundRawFNToRecFN.io.detectTininess := Pipe(valid_stage0, detectTininess_stage0, round_regs).bits io.validout := Pipe(valid_stage0, false.B, round_regs).valid roundRawFNToRecFN.io.infiniteExc := false.B io.out := roundRawFNToRecFN.io.out io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags } class FPUFMAPipe(val latency: Int, val t: FType) (implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { override def desiredName = s"FPUFMAPipe_l${latency}_f${t.ieeeWidth}" require(latency>0) val io = IO(new Bundle { val in = Flipped(Valid(new FPInput)) val out = Valid(new FPResult) }) val valid = RegNext(io.in.valid) val in = Reg(new FPInput) when (io.in.valid) { val one = 1.U << (t.sig + t.exp - 1) val zero = (io.in.bits.in1 ^ io.in.bits.in2) & (1.U << (t.sig + t.exp)) val cmd_fma = io.in.bits.ren3 val cmd_addsub = io.in.bits.swap23 in := io.in.bits when (cmd_addsub) { in.in2 := one } when (!(cmd_fma || cmd_addsub)) { in.in3 := zero } } val fma = Module(new MulAddRecFNPipe((latency-1) min 2, t.exp, t.sig)) fma.io.validin := valid fma.io.op := in.fmaCmd fma.io.roundingMode := in.rm fma.io.detectTininess := hardfloat.consts.tininess_afterRounding fma.io.a := in.in1 fma.io.b := in.in2 fma.io.c := in.in3 val res = Wire(new FPResult) res.data := sanitizeNaN(fma.io.out, t) res.exc := fma.io.exceptionFlags io.out := Pipe(fma.io.validout, res, (latency-3) max 0) } class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) { val io = IO(new FPUIO) val (useClockGating, useDebugROB) = coreParams match { case r: RocketCoreParams => val sz = if (r.debugROB.isDefined) r.debugROB.get.size else 1 (r.clockGate, sz < 1) case _ => (false, false) } val clock_en_reg = Reg(Bool()) val clock_en = clock_en_reg || io.cp_req.valid val gated_clock = if (!useClockGating) clock else ClockGate(clock, clock_en, "fpu_clock_gate") val fp_decoder = Module(new FPUDecoder) fp_decoder.io.inst := io.inst val id_ctrl = WireInit(fp_decoder.io.sigs) coreParams match { case r: RocketCoreParams => r.vector.map(v => { val v_decode = v.decoder(p) // Only need to get ren1 v_decode.io.inst := io.inst v_decode.io.vconfig := DontCare // core deals with this when (v_decode.io.legal && v_decode.io.read_frs1) { id_ctrl.ren1 := true.B id_ctrl.swap12 := false.B id_ctrl.toint := true.B id_ctrl.typeTagIn := I id_ctrl.typeTagOut := Mux(io.v_sew === 3.U, D, S) } when (v_decode.io.write_frd) { id_ctrl.wen := true.B } })} val ex_reg_valid = RegNext(io.valid, false.B) val ex_reg_inst = RegEnable(io.inst, io.valid) val ex_reg_ctrl = RegEnable(id_ctrl, io.valid) val ex_ra = List.fill(3)(Reg(UInt())) // load/vector response val load_wb = RegNext(io.ll_resp_val) val load_wb_typeTag = RegEnable(io.ll_resp_type(1,0) - typeTagWbOffset, io.ll_resp_val) val load_wb_data = RegEnable(io.ll_resp_data, io.ll_resp_val) val load_wb_tag = RegEnable(io.ll_resp_tag, io.ll_resp_val) class FPUImpl { // entering gated-clock domain val req_valid = ex_reg_valid || io.cp_req.valid val ex_cp_valid = io.cp_req.fire val mem_cp_valid = RegNext(ex_cp_valid, false.B) val wb_cp_valid = RegNext(mem_cp_valid, false.B) val mem_reg_valid = RegInit(false.B) val killm = (io.killm || io.nack_mem) && !mem_cp_valid // Kill X-stage instruction if M-stage is killed. This prevents it from // speculatively being sent to the div-sqrt unit, which can cause priority // inversion for two back-to-back divides, the first of which is killed. val killx = io.killx || mem_reg_valid && killm mem_reg_valid := ex_reg_valid && !killx || ex_cp_valid val mem_reg_inst = RegEnable(ex_reg_inst, ex_reg_valid) val wb_reg_valid = RegNext(mem_reg_valid && (!killm || mem_cp_valid), false.B) val cp_ctrl = Wire(new FPUCtrlSigs) cp_ctrl :<>= io.cp_req.bits.viewAsSupertype(new FPUCtrlSigs) io.cp_resp.valid := false.B io.cp_resp.bits.data := 0.U io.cp_resp.bits.exc := DontCare val ex_ctrl = Mux(ex_cp_valid, cp_ctrl, ex_reg_ctrl) val mem_ctrl = RegEnable(ex_ctrl, req_valid) val wb_ctrl = RegEnable(mem_ctrl, mem_reg_valid) // CoreMonitorBundle to monitor fp register file writes val frfWriteBundle = Seq.fill(2)(WireInit(new CoreMonitorBundle(xLen, fLen), DontCare)) frfWriteBundle.foreach { i => i.clock := clock i.reset := reset i.hartid := io.hartid i.timer := io.time(31,0) i.valid := false.B i.wrenx := false.B i.wrenf := false.B i.excpt := false.B } // regfile val regfile = Mem(32, Bits((fLen+1).W)) when (load_wb) { val wdata = recode(load_wb_data, load_wb_typeTag) regfile(load_wb_tag) := wdata assert(consistent(wdata)) if (enableCommitLog) printf("f%d p%d 0x%x\n", load_wb_tag, load_wb_tag + 32.U, ieee(wdata)) if (useDebugROB) DebugROB.pushWb(clock, reset, io.hartid, load_wb, load_wb_tag + 32.U, ieee(wdata)) frfWriteBundle(0).wrdst := load_wb_tag frfWriteBundle(0).wrenf := true.B frfWriteBundle(0).wrdata := ieee(wdata) } val ex_rs = ex_ra.map(a => regfile(a)) when (io.valid) { when (id_ctrl.ren1) { when (!id_ctrl.swap12) { ex_ra(0) := io.inst(19,15) } when (id_ctrl.swap12) { ex_ra(1) := io.inst(19,15) } } when (id_ctrl.ren2) { when (id_ctrl.swap12) { ex_ra(0) := io.inst(24,20) } when (id_ctrl.swap23) { ex_ra(2) := io.inst(24,20) } when (!id_ctrl.swap12 && !id_ctrl.swap23) { ex_ra(1) := io.inst(24,20) } } when (id_ctrl.ren3) { ex_ra(2) := io.inst(31,27) } } val ex_rm = Mux(ex_reg_inst(14,12) === 7.U, io.fcsr_rm, ex_reg_inst(14,12)) def fuInput(minT: Option[FType]): FPInput = { val req = Wire(new FPInput) val tag = ex_ctrl.typeTagIn req.viewAsSupertype(new Bundle with HasFPUCtrlSigs) :#= ex_ctrl.viewAsSupertype(new Bundle with HasFPUCtrlSigs) req.rm := ex_rm req.in1 := unbox(ex_rs(0), tag, minT) req.in2 := unbox(ex_rs(1), tag, minT) req.in3 := unbox(ex_rs(2), tag, minT) req.typ := ex_reg_inst(21,20) req.fmt := ex_reg_inst(26,25) req.fmaCmd := ex_reg_inst(3,2) | (!ex_ctrl.ren3 && ex_reg_inst(27)) when (ex_cp_valid) { req := io.cp_req.bits when (io.cp_req.bits.swap12) { req.in1 := io.cp_req.bits.in2 req.in2 := io.cp_req.bits.in1 } when (io.cp_req.bits.swap23) { req.in2 := io.cp_req.bits.in3 req.in3 := io.cp_req.bits.in2 } } req } val sfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.S)) sfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === S sfma.io.in.bits := fuInput(Some(sfma.t)) val fpiu = Module(new FPToInt) fpiu.io.in.valid := req_valid && (ex_ctrl.toint || ex_ctrl.div || ex_ctrl.sqrt || (ex_ctrl.fastpipe && ex_ctrl.wflags)) fpiu.io.in.bits := fuInput(None) io.store_data := fpiu.io.out.bits.store io.toint_data := fpiu.io.out.bits.toint when(fpiu.io.out.valid && mem_cp_valid && mem_ctrl.toint){ io.cp_resp.bits.data := fpiu.io.out.bits.toint io.cp_resp.valid := true.B } val ifpu = Module(new IntToFP(cfg.ifpuLatency)) ifpu.io.in.valid := req_valid && ex_ctrl.fromint ifpu.io.in.bits := fpiu.io.in.bits ifpu.io.in.bits.in1 := Mux(ex_cp_valid, io.cp_req.bits.in1, io.fromint_data) val fpmu = Module(new FPToFP(cfg.fpmuLatency)) fpmu.io.in.valid := req_valid && ex_ctrl.fastpipe fpmu.io.in.bits := fpiu.io.in.bits fpmu.io.lt := fpiu.io.out.bits.lt val divSqrt_wen = WireDefault(false.B) val divSqrt_inFlight = WireDefault(false.B) val divSqrt_waddr = Reg(UInt(5.W)) val divSqrt_cp = Reg(Bool()) val divSqrt_typeTag = Wire(UInt(log2Up(floatTypes.size).W)) val divSqrt_wdata = Wire(UInt((fLen+1).W)) val divSqrt_flags = Wire(UInt(FPConstants.FLAGS_SZ.W)) divSqrt_typeTag := DontCare divSqrt_wdata := DontCare divSqrt_flags := DontCare // writeback arbitration case class Pipe(p: Module, lat: Int, cond: (FPUCtrlSigs) => Bool, res: FPResult) val pipes = List( Pipe(fpmu, fpmu.latency, (c: FPUCtrlSigs) => c.fastpipe, fpmu.io.out.bits), Pipe(ifpu, ifpu.latency, (c: FPUCtrlSigs) => c.fromint, ifpu.io.out.bits), Pipe(sfma, sfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === S, sfma.io.out.bits)) ++ (fLen > 32).option({ val dfma = Module(new FPUFMAPipe(cfg.dfmaLatency, FType.D)) dfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === D dfma.io.in.bits := fuInput(Some(dfma.t)) Pipe(dfma, dfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === D, dfma.io.out.bits) }) ++ (minFLen == 16).option({ val hfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.H)) hfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === H hfma.io.in.bits := fuInput(Some(hfma.t)) Pipe(hfma, hfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === H, hfma.io.out.bits) }) def latencyMask(c: FPUCtrlSigs, offset: Int) = { require(pipes.forall(_.lat >= offset)) pipes.map(p => Mux(p.cond(c), (1 << p.lat-offset).U, 0.U)).reduce(_|_) } def pipeid(c: FPUCtrlSigs) = pipes.zipWithIndex.map(p => Mux(p._1.cond(c), p._2.U, 0.U)).reduce(_|_) val maxLatency = pipes.map(_.lat).max val memLatencyMask = latencyMask(mem_ctrl, 2) class WBInfo extends Bundle { val rd = UInt(5.W) val typeTag = UInt(log2Up(floatTypes.size).W) val cp = Bool() val pipeid = UInt(log2Ceil(pipes.size).W) } val wen = RegInit(0.U((maxLatency-1).W)) val wbInfo = Reg(Vec(maxLatency-1, new WBInfo)) val mem_wen = mem_reg_valid && (mem_ctrl.fma || mem_ctrl.fastpipe || mem_ctrl.fromint) val write_port_busy = RegEnable(mem_wen && (memLatencyMask & latencyMask(ex_ctrl, 1)).orR || (wen & latencyMask(ex_ctrl, 0)).orR, req_valid) ccover(mem_reg_valid && write_port_busy, "WB_STRUCTURAL", "structural hazard on writeback") for (i <- 0 until maxLatency-2) { when (wen(i+1)) { wbInfo(i) := wbInfo(i+1) } } wen := wen >> 1 when (mem_wen) { when (!killm) { wen := wen >> 1 | memLatencyMask } for (i <- 0 until maxLatency-1) { when (!write_port_busy && memLatencyMask(i)) { wbInfo(i).cp := mem_cp_valid wbInfo(i).typeTag := mem_ctrl.typeTagOut wbInfo(i).pipeid := pipeid(mem_ctrl) wbInfo(i).rd := mem_reg_inst(11,7) } } } val waddr = Mux(divSqrt_wen, divSqrt_waddr, wbInfo(0).rd) val wb_cp = Mux(divSqrt_wen, divSqrt_cp, wbInfo(0).cp) val wtypeTag = Mux(divSqrt_wen, divSqrt_typeTag, wbInfo(0).typeTag) val wdata = box(Mux(divSqrt_wen, divSqrt_wdata, (pipes.map(_.res.data): Seq[UInt])(wbInfo(0).pipeid)), wtypeTag) val wexc = (pipes.map(_.res.exc): Seq[UInt])(wbInfo(0).pipeid) when ((!wbInfo(0).cp && wen(0)) || divSqrt_wen) { assert(consistent(wdata)) regfile(waddr) := wdata if (enableCommitLog) { printf("f%d p%d 0x%x\n", waddr, waddr + 32.U, ieee(wdata)) } frfWriteBundle(1).wrdst := waddr frfWriteBundle(1).wrenf := true.B frfWriteBundle(1).wrdata := ieee(wdata) } if (useDebugROB) { DebugROB.pushWb(clock, reset, io.hartid, (!wbInfo(0).cp && wen(0)) || divSqrt_wen, waddr + 32.U, ieee(wdata)) } when (wb_cp && (wen(0) || divSqrt_wen)) { io.cp_resp.bits.data := wdata io.cp_resp.valid := true.B } assert(!io.cp_req.valid || pipes.forall(_.lat == pipes.head.lat).B, s"FPU only supports coprocessor if FMA pipes have uniform latency ${pipes.map(_.lat)}") // Avoid structural hazards and nacking of external requests // toint responds in the MEM stage, so an incoming toint can induce a structural hazard against inflight FMAs io.cp_req.ready := !ex_reg_valid && !(cp_ctrl.toint && wen =/= 0.U) && !divSqrt_inFlight val wb_toint_valid = wb_reg_valid && wb_ctrl.toint val wb_toint_exc = RegEnable(fpiu.io.out.bits.exc, mem_ctrl.toint) io.fcsr_flags.valid := wb_toint_valid || divSqrt_wen || wen(0) io.fcsr_flags.bits := Mux(wb_toint_valid, wb_toint_exc, 0.U) | Mux(divSqrt_wen, divSqrt_flags, 0.U) | Mux(wen(0), wexc, 0.U) val divSqrt_write_port_busy = (mem_ctrl.div || mem_ctrl.sqrt) && wen.orR io.fcsr_rdy := !(ex_reg_valid && ex_ctrl.wflags || mem_reg_valid && mem_ctrl.wflags || wb_reg_valid && wb_ctrl.toint || wen.orR || divSqrt_inFlight) io.nack_mem := (write_port_busy || divSqrt_write_port_busy || divSqrt_inFlight) && !mem_cp_valid io.dec <> id_ctrl def useScoreboard(f: ((Pipe, Int)) => Bool) = pipes.zipWithIndex.filter(_._1.lat > 3).map(x => f(x)).fold(false.B)(_||_) io.sboard_set := wb_reg_valid && !wb_cp_valid && RegNext(useScoreboard(_._1.cond(mem_ctrl)) || mem_ctrl.div || mem_ctrl.sqrt || mem_ctrl.vec) io.sboard_clr := !wb_cp_valid && (divSqrt_wen || (wen(0) && useScoreboard(x => wbInfo(0).pipeid === x._2.U))) io.sboard_clra := waddr ccover(io.sboard_clr && load_wb, "DUAL_WRITEBACK", "load and FMA writeback on same cycle") // we don't currently support round-max-magnitude (rm=4) io.illegal_rm := io.inst(14,12).isOneOf(5.U, 6.U) || io.inst(14,12) === 7.U && io.fcsr_rm >= 5.U if (cfg.divSqrt) { val divSqrt_inValid = mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt) && !divSqrt_inFlight val divSqrt_killed = RegNext(divSqrt_inValid && killm, true.B) when (divSqrt_inValid) { divSqrt_waddr := mem_reg_inst(11,7) divSqrt_cp := mem_cp_valid } ccover(divSqrt_inFlight && divSqrt_killed, "DIV_KILLED", "divide killed after issued to divider") ccover(divSqrt_inFlight && mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt), "DIV_BUSY", "divider structural hazard") ccover(mem_reg_valid && divSqrt_write_port_busy, "DIV_WB_STRUCTURAL", "structural hazard on division writeback") for (t <- floatTypes) { val tag = mem_ctrl.typeTagOut val divSqrt = withReset(divSqrt_killed) { Module(new hardfloat.DivSqrtRecFN_small(t.exp, t.sig, 0)) } divSqrt.io.inValid := divSqrt_inValid && tag === typeTag(t).U divSqrt.io.sqrtOp := mem_ctrl.sqrt divSqrt.io.a := maxType.unsafeConvert(fpiu.io.out.bits.in.in1, t) divSqrt.io.b := maxType.unsafeConvert(fpiu.io.out.bits.in.in2, t) divSqrt.io.roundingMode := fpiu.io.out.bits.in.rm divSqrt.io.detectTininess := hardfloat.consts.tininess_afterRounding when (!divSqrt.io.inReady) { divSqrt_inFlight := true.B } // only 1 in flight when (divSqrt.io.outValid_div || divSqrt.io.outValid_sqrt) { divSqrt_wen := !divSqrt_killed divSqrt_wdata := sanitizeNaN(divSqrt.io.out, t) divSqrt_flags := divSqrt.io.exceptionFlags divSqrt_typeTag := typeTag(t).U } } when (divSqrt_killed) { divSqrt_inFlight := false.B } } else { when (id_ctrl.div || id_ctrl.sqrt) { io.illegal_rm := true.B } } // gate the clock clock_en_reg := !useClockGating.B || io.keep_clock_enabled || // chicken bit io.valid || // ID stage req_valid || // EX stage mem_reg_valid || mem_cp_valid || // MEM stage wb_reg_valid || wb_cp_valid || // WB stage wen.orR || divSqrt_inFlight || // post-WB stage io.ll_resp_val // load writeback } // leaving gated-clock domain val fpuImpl = withClock (gated_clock) { new FPUImpl } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = property.cover(cond, s"FPU_$label", "Core;;" + desc) } File util.scala: //****************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v3.common.{MicroOp} import boom.v3.exu.{BrUpdateInfo} /** * Object to XOR fold a input register of fullLength into a compressedLength. */ object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /** * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks */ object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask) } def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) } } /** * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. */ object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /** * Object to return a BR mask given a MicroOp mask and old BR mask. */ object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask) out } } /** * Object to check if at least 1 bit matches in two masks */ object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /** * Object to clear one bit in a mask given an index */ object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /** * Object to shift a register over by one bit and concat a new one */ object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /** * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. */ object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /** * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. */ object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc | (b-1).U) } } /** * Object to rotate a signal left by one */ object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /** * Object to sext a value to a particular length. */ object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /** * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. */ object ImmGen { import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U} def apply(ip: UInt, isel: UInt): SInt = { val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt } } /** * Object to get the FP rounding mode out of a packed immediate. */ object ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } } /** * Object to get the FP function fype from a packed immediate. * Note: only works if !(IS_B or IS_S) */ object ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } } /** * Object to see if an instruction is a JALR. */ object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /** * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). */ object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /** * Object to return the lowest bit position after the head. */ object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /** * Object to determine whether queue * index i0 is older than index i1. */ object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } /** * Set all bits at or below the highest order '1'. */ object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_|_) } } /** * Set all bits at or above the lowest order '1'. */ object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_) } } /** * Transpose a matrix of Chisel Vecs. */ object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /** * N-wide one-hot priority encoder. */ object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /** * Connect the first k of n valid input interfaces to k output interfaces. */ class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_)) val out_valids = sels map (col => col.reduce(_||_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /** * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). */ class BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v3.common.BoomModule()(p) with boom.v3.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire) val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop) uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop)) io.deq.bits := out io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop) // For flow queue behavior. if (flow) { when (io.empty) { io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop) io.deq.bits := io.enq.bits io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) do_deq := false.B when (io.deq.ready) { do_enq := false.B } } } private val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /** * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" */ def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) */ def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) */ def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) */ def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /** * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line */ def apply(strs: String*)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } File functional-unit.scala: //****************************************************************************** // Copyright (c) 2013 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Functional Units //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // // If regfile bypassing is disabled, then the functional unit must do its own // bypassing in here on the WB stage (i.e., bypassing the io.resp.data) // // TODO: explore possibility of conditional IO fields? if a branch unit... how to add extra to IO in subclass? package boom.v3.exu import chisel3._ import chisel3.util._ import chisel3.experimental.dataview._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ import freechips.rocketchip.tile import freechips.rocketchip.rocket.{PipelinedMultiplier,BP,BreakpointUnit,Causes,CSR} import boom.v3.common._ import boom.v3.ifu._ import boom.v3.util._ /**t * Functional unit constants */ object FUConstants { // bit mask, since a given execution pipeline may support multiple functional units val FUC_SZ = 10 val FU_X = BitPat.dontCare(FUC_SZ) val FU_ALU = 1.U(FUC_SZ.W) val FU_JMP = 2.U(FUC_SZ.W) val FU_MEM = 4.U(FUC_SZ.W) val FU_MUL = 8.U(FUC_SZ.W) val FU_DIV = 16.U(FUC_SZ.W) val FU_CSR = 32.U(FUC_SZ.W) val FU_FPU = 64.U(FUC_SZ.W) val FU_FDV = 128.U(FUC_SZ.W) val FU_I2F = 256.U(FUC_SZ.W) val FU_F2I = 512.U(FUC_SZ.W) // FP stores generate data through FP F2I, and generate address through MemAddrCalc val FU_F2IMEM = 516.U(FUC_SZ.W) } import FUConstants._ /** * Class to tell the FUDecoders what units it needs to support * * @param alu support alu unit? * @param bru support br unit? * @param mem support mem unit? * @param muld support multiple div unit? * @param fpu support FP unit? * @param csr support csr writing unit? * @param fdiv support FP div unit? * @param ifpu support int to FP unit? */ class SupportedFuncUnits( val alu: Boolean = false, val jmp: Boolean = false, val mem: Boolean = false, val muld: Boolean = false, val fpu: Boolean = false, val csr: Boolean = false, val fdiv: Boolean = false, val ifpu: Boolean = false) { } /** * Bundle for signals sent to the functional unit * * @param dataWidth width of the data sent to the functional unit */ class FuncUnitReq(val dataWidth: Int)(implicit p: Parameters) extends BoomBundle with HasBoomUOP { val numOperands = 3 val rs1_data = UInt(dataWidth.W) val rs2_data = UInt(dataWidth.W) val rs3_data = UInt(dataWidth.W) // only used for FMA units val pred_data = Bool() val kill = Bool() // kill everything } /** * Bundle for the signals sent out of the function unit * * @param dataWidth data sent from the functional unit */ class FuncUnitResp(val dataWidth: Int)(implicit p: Parameters) extends BoomBundle with HasBoomUOP { val predicated = Bool() // Was this response from a predicated-off instruction val data = UInt(dataWidth.W) val fflags = new ValidIO(new FFlagsResp) val addr = UInt((vaddrBits+1).W) // only for maddr -> LSU val mxcpt = new ValidIO(UInt((freechips.rocketchip.rocket.Causes.all.max+2).W)) //only for maddr->LSU val sfence = Valid(new freechips.rocketchip.rocket.SFenceReq) // only for mcalc } /** * Branch resolution information given from the branch unit */ class BrResolutionInfo(implicit p: Parameters) extends BoomBundle { val uop = new MicroOp val valid = Bool() val mispredict = Bool() val taken = Bool() // which direction did the branch go? val cfi_type = UInt(CFI_SZ.W) // Info for recalculating the pc for this branch val pc_sel = UInt(2.W) val jalr_target = UInt(vaddrBitsExtended.W) val target_offset = SInt() } class BrUpdateInfo(implicit p: Parameters) extends BoomBundle { // On the first cycle we get masks to kill registers val b1 = new BrUpdateMasks // On the second cycle we get indices to reset pointers val b2 = new BrResolutionInfo } class BrUpdateMasks(implicit p: Parameters) extends BoomBundle { val resolve_mask = UInt(maxBrCount.W) val mispredict_mask = UInt(maxBrCount.W) } /** * Abstract top level functional unit class that wraps a lower level hand made functional unit * * @param isPipelined is the functional unit pipelined? * @param numStages how many pipeline stages does the functional unit have * @param numBypassStages how many bypass stages does the function unit have * @param dataWidth width of the data being operated on in the functional unit * @param hasBranchUnit does this functional unit have a branch unit? */ abstract class FunctionalUnit( val isPipelined: Boolean, val numStages: Int, val numBypassStages: Int, val dataWidth: Int, val isJmpUnit: Boolean = false, val isAluUnit: Boolean = false, val isMemAddrCalcUnit: Boolean = false, val needsFcsr: Boolean = false) (implicit p: Parameters) extends BoomModule { val io = IO(new Bundle { val req = Flipped(new DecoupledIO(new FuncUnitReq(dataWidth))) val resp = (new DecoupledIO(new FuncUnitResp(dataWidth))) val brupdate = Input(new BrUpdateInfo()) val bypass = Output(Vec(numBypassStages, Valid(new ExeUnitResp(dataWidth)))) // only used by the fpu unit val fcsr_rm = if (needsFcsr) Input(UInt(tile.FPConstants.RM_SZ.W)) else null // only used by branch unit val brinfo = if (isAluUnit) Output(new BrResolutionInfo()) else null val get_ftq_pc = if (isJmpUnit) Flipped(new GetPCFromFtqIO()) else null val status = if (isMemAddrCalcUnit) Input(new freechips.rocketchip.rocket.MStatus()) else null // only used by memaddr calc unit val bp = if (isMemAddrCalcUnit) Input(Vec(nBreakpoints, new BP)) else null val mcontext = if (isMemAddrCalcUnit) Input(UInt(coreParams.mcontextWidth.W)) else null val scontext = if (isMemAddrCalcUnit) Input(UInt(coreParams.scontextWidth.W)) else null }) io.bypass.foreach { b => b.valid := false.B; b.bits := DontCare } io.resp.valid := false.B io.resp.bits := DontCare if (isJmpUnit) { io.get_ftq_pc.ftq_idx := DontCare } } /** * Abstract top level pipelined functional unit * * Note: this helps track which uops get killed while in intermediate stages, * but it is the job of the consumer to check for kills on the same cycle as consumption!!! * * @param numStages how many pipeline stages does the functional unit have * @param numBypassStages how many bypass stages does the function unit have * @param earliestBypassStage first stage that you can start bypassing from * @param dataWidth width of the data being operated on in the functional unit * @param hasBranchUnit does this functional unit have a branch unit? */ abstract class PipelinedFunctionalUnit( numStages: Int, numBypassStages: Int, earliestBypassStage: Int, dataWidth: Int, isJmpUnit: Boolean = false, isAluUnit: Boolean = false, isMemAddrCalcUnit: Boolean = false, needsFcsr: Boolean = false )(implicit p: Parameters) extends FunctionalUnit( isPipelined = true, numStages = numStages, numBypassStages = numBypassStages, dataWidth = dataWidth, isJmpUnit = isJmpUnit, isAluUnit = isAluUnit, isMemAddrCalcUnit = isMemAddrCalcUnit, needsFcsr = needsFcsr) { // Pipelined functional unit is always ready. io.req.ready := true.B if (numStages > 0) { val r_valids = RegInit(VecInit(Seq.fill(numStages) { false.B })) val r_uops = Reg(Vec(numStages, new MicroOp())) // handle incoming request r_valids(0) := io.req.valid && !IsKilledByBranch(io.brupdate, io.req.bits.uop) && !io.req.bits.kill r_uops(0) := io.req.bits.uop r_uops(0).br_mask := GetNewBrMask(io.brupdate, io.req.bits.uop) // handle middle of the pipeline for (i <- 1 until numStages) { r_valids(i) := r_valids(i-1) && !IsKilledByBranch(io.brupdate, r_uops(i-1)) && !io.req.bits.kill r_uops(i) := r_uops(i-1) r_uops(i).br_mask := GetNewBrMask(io.brupdate, r_uops(i-1)) if (numBypassStages > 0) { io.bypass(i-1).bits.uop := r_uops(i-1) } } // handle outgoing (branch could still kill it) // consumer must also check for pipeline flushes (kills) io.resp.valid := r_valids(numStages-1) && !IsKilledByBranch(io.brupdate, r_uops(numStages-1)) io.resp.bits.predicated := false.B io.resp.bits.uop := r_uops(numStages-1) io.resp.bits.uop.br_mask := GetNewBrMask(io.brupdate, r_uops(numStages-1)) // bypassing (TODO allow bypass vector to have a different size from numStages) if (numBypassStages > 0 && earliestBypassStage == 0) { io.bypass(0).bits.uop := io.req.bits.uop for (i <- 1 until numBypassStages) { io.bypass(i).bits.uop := r_uops(i-1) } } } else { require (numStages == 0) // pass req straight through to response // valid doesn't check kill signals, let consumer deal with it. // The LSU already handles it and this hurts critical path. io.resp.valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.req.bits.uop) io.resp.bits.predicated := false.B io.resp.bits.uop := io.req.bits.uop io.resp.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.req.bits.uop) } } /** * Functional unit that wraps RocketChips ALU * * @param isBranchUnit is this a branch unit? * @param numStages how many pipeline stages does the functional unit have * @param dataWidth width of the data being operated on in the functional unit */ class ALUUnit(isJmpUnit: Boolean = false, numStages: Int = 1, dataWidth: Int)(implicit p: Parameters) extends PipelinedFunctionalUnit( numStages = numStages, numBypassStages = numStages, isAluUnit = true, earliestBypassStage = 0, dataWidth = dataWidth, isJmpUnit = isJmpUnit) with boom.v3.ifu.HasBoomFrontendParameters { val uop = io.req.bits.uop // immediate generation val imm_xprlen = ImmGen(uop.imm_packed, uop.ctrl.imm_sel) // operand 1 select var op1_data: UInt = null if (isJmpUnit) { // Get the uop PC for jumps val block_pc = AlignPCToBoundary(io.get_ftq_pc.pc, icBlockBytes) val uop_pc = (block_pc | uop.pc_lob) - Mux(uop.edge_inst, 2.U, 0.U) op1_data = Mux(uop.ctrl.op1_sel.asUInt === OP1_RS1 , io.req.bits.rs1_data, Mux(uop.ctrl.op1_sel.asUInt === OP1_PC , Sext(uop_pc, xLen), 0.U)) } else { op1_data = Mux(uop.ctrl.op1_sel.asUInt === OP1_RS1 , io.req.bits.rs1_data, 0.U) } // operand 2 select val op2_data = Mux(uop.ctrl.op2_sel === OP2_IMM, Sext(imm_xprlen.asUInt, xLen), Mux(uop.ctrl.op2_sel === OP2_IMMC, io.req.bits.uop.prs1(4,0), Mux(uop.ctrl.op2_sel === OP2_RS2 , io.req.bits.rs2_data, Mux(uop.ctrl.op2_sel === OP2_NEXT, Mux(uop.is_rvc, 2.U, 4.U), 0.U)))) val alu = Module(new freechips.rocketchip.rocket.ALU()) alu.io.in1 := op1_data.asUInt alu.io.in2 := op2_data.asUInt alu.io.fn := uop.ctrl.op_fcn alu.io.dw := uop.ctrl.fcn_dw // Did I just get killed by the previous cycle's branch, // or by a flush pipeline? val killed = WireInit(false.B) when (io.req.bits.kill || IsKilledByBranch(io.brupdate, uop)) { killed := true.B } val rs1 = io.req.bits.rs1_data val rs2 = io.req.bits.rs2_data val br_eq = (rs1 === rs2) val br_ltu = (rs1.asUInt < rs2.asUInt) val br_lt = (~(rs1(xLen-1) ^ rs2(xLen-1)) & br_ltu | rs1(xLen-1) & ~rs2(xLen-1)).asBool val pc_sel = MuxLookup(uop.ctrl.br_type, PC_PLUS4)( Seq( BR_N -> PC_PLUS4, BR_NE -> Mux(!br_eq, PC_BRJMP, PC_PLUS4), BR_EQ -> Mux( br_eq, PC_BRJMP, PC_PLUS4), BR_GE -> Mux(!br_lt, PC_BRJMP, PC_PLUS4), BR_GEU -> Mux(!br_ltu, PC_BRJMP, PC_PLUS4), BR_LT -> Mux( br_lt, PC_BRJMP, PC_PLUS4), BR_LTU -> Mux( br_ltu, PC_BRJMP, PC_PLUS4), BR_J -> PC_BRJMP, BR_JR -> PC_JALR )) val is_taken = io.req.valid && !killed && (uop.is_br || uop.is_jalr || uop.is_jal) && (pc_sel =/= PC_PLUS4) // "mispredict" means that a branch has been resolved and it must be killed val mispredict = WireInit(false.B) val is_br = io.req.valid && !killed && uop.is_br && !uop.is_sfb val is_jal = io.req.valid && !killed && uop.is_jal val is_jalr = io.req.valid && !killed && uop.is_jalr when (is_br || is_jalr) { if (!isJmpUnit) { assert (pc_sel =/= PC_JALR) } when (pc_sel === PC_PLUS4) { mispredict := uop.taken } when (pc_sel === PC_BRJMP) { mispredict := !uop.taken } } val brinfo = Wire(new BrResolutionInfo) // note: jal doesn't allocate a branch-mask, so don't clear a br-mask bit brinfo.valid := is_br || is_jalr brinfo.mispredict := mispredict brinfo.uop := uop brinfo.cfi_type := Mux(is_jalr, CFI_JALR, Mux(is_br , CFI_BR, CFI_X)) brinfo.taken := is_taken brinfo.pc_sel := pc_sel brinfo.jalr_target := DontCare // Branch/Jump Target Calculation // For jumps we read the FTQ, and can calculate the target // For branches we emit the offset for the core to redirect if necessary val target_offset = imm_xprlen(20,0).asSInt brinfo.jalr_target := DontCare if (isJmpUnit) { def encodeVirtualAddress(a0: UInt, ea: UInt) = if (vaddrBitsExtended == vaddrBits) { ea } else { // Efficient means to compress 64-bit VA into vaddrBits+1 bits. // (VA is bad if VA(vaddrBits) != VA(vaddrBits-1)). val a = a0.asSInt >> vaddrBits val msb = Mux(a === 0.S || a === -1.S, ea(vaddrBits), !ea(vaddrBits-1)) Cat(msb, ea(vaddrBits-1,0)) } val jalr_target_base = io.req.bits.rs1_data.asSInt val jalr_target_xlen = Wire(UInt(xLen.W)) jalr_target_xlen := (jalr_target_base + target_offset).asUInt val jalr_target = (encodeVirtualAddress(jalr_target_xlen, jalr_target_xlen).asSInt & -2.S).asUInt brinfo.jalr_target := jalr_target val cfi_idx = ((uop.pc_lob ^ Mux(io.get_ftq_pc.entry.start_bank === 1.U, 1.U << log2Ceil(bankBytes), 0.U)))(log2Ceil(fetchWidth),1) when (pc_sel === PC_JALR) { mispredict := !io.get_ftq_pc.next_val || (io.get_ftq_pc.next_pc =/= jalr_target) || !io.get_ftq_pc.entry.cfi_idx.valid || (io.get_ftq_pc.entry.cfi_idx.bits =/= cfi_idx) } } brinfo.target_offset := target_offset io.brinfo := brinfo // Response // TODO add clock gate on resp bits from functional units // io.resp.bits.data := RegEnable(alu.io.out, io.req.valid) // val reg_data = Reg(outType = Bits(width = xLen)) // reg_data := alu.io.out // io.resp.bits.data := reg_data val r_val = RegInit(VecInit(Seq.fill(numStages) { false.B })) val r_data = Reg(Vec(numStages, UInt(xLen.W))) val r_pred = Reg(Vec(numStages, Bool())) val alu_out = Mux(io.req.bits.uop.is_sfb_shadow && io.req.bits.pred_data, Mux(io.req.bits.uop.ldst_is_rs1, io.req.bits.rs1_data, io.req.bits.rs2_data), Mux(io.req.bits.uop.uopc === uopMOV, io.req.bits.rs2_data, alu.io.out)) r_val (0) := io.req.valid r_data(0) := Mux(io.req.bits.uop.is_sfb_br, pc_sel === PC_BRJMP, alu_out) r_pred(0) := io.req.bits.uop.is_sfb_shadow && io.req.bits.pred_data for (i <- 1 until numStages) { r_val(i) := r_val(i-1) r_data(i) := r_data(i-1) r_pred(i) := r_pred(i-1) } io.resp.bits.data := r_data(numStages-1) io.resp.bits.predicated := r_pred(numStages-1) // Bypass // for the ALU, we can bypass same cycle as compute require (numStages >= 1) require (numBypassStages >= 1) io.bypass(0).valid := io.req.valid io.bypass(0).bits.data := Mux(io.req.bits.uop.is_sfb_br, pc_sel === PC_BRJMP, alu_out) for (i <- 1 until numStages) { io.bypass(i).valid := r_val(i-1) io.bypass(i).bits.data := r_data(i-1) } // Exceptions io.resp.bits.fflags.valid := false.B } /** * Functional unit that passes in base+imm to calculate addresses, and passes store data * to the LSU. * For floating point, 65bit FP store-data needs to be decoded into 64bit FP form */ class MemAddrCalcUnit(implicit p: Parameters) extends PipelinedFunctionalUnit( numStages = 0, numBypassStages = 0, earliestBypassStage = 0, dataWidth = 65, // TODO enable this only if FP is enabled? isMemAddrCalcUnit = true) with freechips.rocketchip.rocket.constants.MemoryOpConstants with freechips.rocketchip.rocket.constants.ScalarOpConstants { // perform address calculation val sum = (io.req.bits.rs1_data.asSInt + io.req.bits.uop.imm_packed(19,8).asSInt).asUInt val ea_sign = Mux(sum(vaddrBits-1), ~sum(63,vaddrBits) === 0.U, sum(63,vaddrBits) =/= 0.U) val effective_address = Cat(ea_sign, sum(vaddrBits-1,0)).asUInt val store_data = io.req.bits.rs2_data io.resp.bits.addr := effective_address io.resp.bits.data := store_data if (dataWidth > 63) { assert (!(io.req.valid && io.req.bits.uop.ctrl.is_std && io.resp.bits.data(64).asBool === true.B), "65th bit set in MemAddrCalcUnit.") assert (!(io.req.valid && io.req.bits.uop.ctrl.is_std && io.req.bits.uop.fp_val), "FP store-data should now be going through a different unit.") } assert (!(io.req.bits.uop.fp_val && io.req.valid && io.req.bits.uop.uopc =/= uopLD && io.req.bits.uop.uopc =/= uopSTA), "[maddrcalc] assert we never get store data in here.") // Handle misaligned exceptions val size = io.req.bits.uop.mem_size val misaligned = (size === 1.U && (effective_address(0) =/= 0.U)) || (size === 2.U && (effective_address(1,0) =/= 0.U)) || (size === 3.U && (effective_address(2,0) =/= 0.U)) val bkptu = Module(new BreakpointUnit(nBreakpoints)) bkptu.io.status := io.status bkptu.io.bp := io.bp bkptu.io.pc := DontCare bkptu.io.ea := effective_address bkptu.io.mcontext := io.mcontext bkptu.io.scontext := io.scontext val ma_ld = io.req.valid && io.req.bits.uop.uopc === uopLD && misaligned val ma_st = io.req.valid && (io.req.bits.uop.uopc === uopSTA || io.req.bits.uop.uopc === uopAMO_AG) && misaligned val dbg_bp = io.req.valid && ((io.req.bits.uop.uopc === uopLD && bkptu.io.debug_ld) || (io.req.bits.uop.uopc === uopSTA && bkptu.io.debug_st)) val bp = io.req.valid && ((io.req.bits.uop.uopc === uopLD && bkptu.io.xcpt_ld) || (io.req.bits.uop.uopc === uopSTA && bkptu.io.xcpt_st)) def checkExceptions(x: Seq[(Bool, UInt)]) = (x.map(_._1).reduce(_||_), PriorityMux(x)) val (xcpt_val, xcpt_cause) = checkExceptions(List( (ma_ld, (Causes.misaligned_load).U), (ma_st, (Causes.misaligned_store).U), (dbg_bp, (CSR.debugTriggerCause).U), (bp, (Causes.breakpoint).U))) io.resp.bits.mxcpt.valid := xcpt_val io.resp.bits.mxcpt.bits := xcpt_cause assert (!(ma_ld && ma_st), "Mutually-exclusive exceptions are firing.") io.resp.bits.sfence.valid := io.req.valid && io.req.bits.uop.mem_cmd === M_SFENCE io.resp.bits.sfence.bits.rs1 := io.req.bits.uop.mem_size(0) io.resp.bits.sfence.bits.rs2 := io.req.bits.uop.mem_size(1) io.resp.bits.sfence.bits.addr := io.req.bits.rs1_data io.resp.bits.sfence.bits.asid := io.req.bits.rs2_data } /** * Functional unit to wrap lower level FPU * * Currently, bypassing is unsupported! * All FP instructions are padded out to the max latency unit for easy * write-port scheduling. */ class FPUUnit(implicit p: Parameters) extends PipelinedFunctionalUnit( numStages = p(tile.TileKey).core.fpu.get.dfmaLatency, numBypassStages = 0, earliestBypassStage = 0, dataWidth = 65, needsFcsr = true) { val fpu = Module(new FPU()) fpu.io.req.valid := io.req.valid fpu.io.req.bits.uop := io.req.bits.uop fpu.io.req.bits.rs1_data := io.req.bits.rs1_data fpu.io.req.bits.rs2_data := io.req.bits.rs2_data fpu.io.req.bits.rs3_data := io.req.bits.rs3_data fpu.io.req.bits.fcsr_rm := io.fcsr_rm io.resp.bits.data := fpu.io.resp.bits.data io.resp.bits.fflags.valid := fpu.io.resp.bits.fflags.valid io.resp.bits.fflags.bits.uop := io.resp.bits.uop io.resp.bits.fflags.bits.flags := fpu.io.resp.bits.fflags.bits.flags // kill me now } /** * Int to FP conversion functional unit * * @param latency the amount of stages to delay by */ class IntToFPUnit(latency: Int)(implicit p: Parameters) extends PipelinedFunctionalUnit( numStages = latency, numBypassStages = 0, earliestBypassStage = 0, dataWidth = 65, needsFcsr = true) with tile.HasFPUParameters { val fp_decoder = Module(new UOPCodeFPUDecoder) // TODO use a simpler decoder val io_req = io.req.bits fp_decoder.io.uopc := io_req.uop.uopc val fp_ctrl = fp_decoder.io.sigs val fp_rm = Mux(ImmGenRm(io_req.uop.imm_packed) === 7.U, io.fcsr_rm, ImmGenRm(io_req.uop.imm_packed)) val req = Wire(new tile.FPInput) val tag = fp_ctrl.typeTagIn req.viewAsSupertype(new tile.FPUCtrlSigs) := fp_ctrl req.rm := fp_rm req.in1 := unbox(io_req.rs1_data, tag, None) req.in2 := unbox(io_req.rs2_data, tag, None) req.in3 := DontCare req.typ := ImmGenTyp(io_req.uop.imm_packed) req.fmt := DontCare // FIXME: this may not be the right thing to do here req.fmaCmd := DontCare assert (!(io.req.valid && fp_ctrl.fromint && req.in1(xLen).asBool), "[func] IntToFP integer input has 65th high-order bit set!") assert (!(io.req.valid && !fp_ctrl.fromint), "[func] Only support fromInt micro-ops.") val ifpu = Module(new tile.IntToFP(intToFpLatency)) ifpu.io.in.valid := io.req.valid ifpu.io.in.bits := req ifpu.io.in.bits.in1 := io_req.rs1_data val out_double = Pipe(io.req.valid, fp_ctrl.typeTagOut === D, intToFpLatency).bits //io.resp.bits.data := box(ifpu.io.out.bits.data, !io.resp.bits.uop.fp_single) io.resp.bits.data := box(ifpu.io.out.bits.data, out_double) io.resp.bits.fflags.valid := ifpu.io.out.valid io.resp.bits.fflags.bits.uop := io.resp.bits.uop io.resp.bits.fflags.bits.flags := ifpu.io.out.bits.exc } /** * Iterative/unpipelined functional unit, can only hold a single MicroOp at a time * assumes at least one register between request and response * * TODO allow up to N micro-ops simultaneously. * * @param dataWidth width of the data to be passed into the functional unit */ abstract class IterativeFunctionalUnit(dataWidth: Int)(implicit p: Parameters) extends FunctionalUnit( isPipelined = false, numStages = 1, numBypassStages = 0, dataWidth = dataWidth) { val r_uop = Reg(new MicroOp()) val do_kill = Wire(Bool()) do_kill := io.req.bits.kill // irrelevant default when (io.req.fire) { // update incoming uop do_kill := IsKilledByBranch(io.brupdate, io.req.bits.uop) || io.req.bits.kill r_uop := io.req.bits.uop r_uop.br_mask := GetNewBrMask(io.brupdate, io.req.bits.uop) } .otherwise { do_kill := IsKilledByBranch(io.brupdate, r_uop) || io.req.bits.kill r_uop.br_mask := GetNewBrMask(io.brupdate, r_uop) } // assumes at least one pipeline register between request and response io.resp.bits.uop := r_uop } /** * Divide functional unit. * * @param dataWidth data to be passed into the functional unit */ class DivUnit(dataWidth: Int)(implicit p: Parameters) extends IterativeFunctionalUnit(dataWidth) { // We don't use the iterative multiply functionality here. // Instead we use the PipelinedMultiplier val div = Module(new freechips.rocketchip.rocket.MulDiv(mulDivParams, width = dataWidth)) // request div.io.req.valid := io.req.valid && !this.do_kill div.io.req.bits.dw := io.req.bits.uop.ctrl.fcn_dw div.io.req.bits.fn := io.req.bits.uop.ctrl.op_fcn div.io.req.bits.in1 := io.req.bits.rs1_data div.io.req.bits.in2 := io.req.bits.rs2_data div.io.req.bits.tag := DontCare io.req.ready := div.io.req.ready // handle pipeline kills and branch misspeculations div.io.kill := this.do_kill // response io.resp.valid := div.io.resp.valid && !this.do_kill div.io.resp.ready := io.resp.ready io.resp.bits.data := div.io.resp.bits.data } /** * Pipelined multiplier functional unit that wraps around the RocketChip pipelined multiplier * * @param numStages number of pipeline stages * @param dataWidth size of the data being passed into the functional unit */ class PipelinedMulUnit(numStages: Int, dataWidth: Int)(implicit p: Parameters) extends PipelinedFunctionalUnit( numStages = numStages, numBypassStages = 0, earliestBypassStage = 0, dataWidth = dataWidth) { val imul = Module(new PipelinedMultiplier(xLen, numStages)) // request imul.io.req.valid := io.req.valid imul.io.req.bits.fn := io.req.bits.uop.ctrl.op_fcn imul.io.req.bits.dw := io.req.bits.uop.ctrl.fcn_dw imul.io.req.bits.in1 := io.req.bits.rs1_data imul.io.req.bits.in2 := io.req.bits.rs2_data imul.io.req.bits.tag := DontCare // response io.resp.bits.data := imul.io.resp.bits.data }

module IntToFPUnit( // @[functional-unit.scala:591:7] input clock, // @[functional-unit.scala:591:7] input reset, // @[functional-unit.scala:591:7] input io_req_valid, // @[functional-unit.scala:168:14] input [6:0] io_req_bits_uop_uopc, // @[functional-unit.scala:168:14] input [31:0] io_req_bits_uop_inst, // @[functional-unit.scala:168:14] input [31:0] io_req_bits_uop_debug_inst, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_rvc, // @[functional-unit.scala:168:14] input [39:0] io_req_bits_uop_debug_pc, // @[functional-unit.scala:168:14] input [2:0] io_req_bits_uop_iq_type, // @[functional-unit.scala:168:14] input [9:0] io_req_bits_uop_fu_code, // @[functional-unit.scala:168:14] input [3:0] io_req_bits_uop_ctrl_br_type, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14] input [2:0] io_req_bits_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14] input [2:0] io_req_bits_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14] input [4:0] io_req_bits_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14] input io_req_bits_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14] input [2:0] io_req_bits_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14] input io_req_bits_uop_ctrl_is_load, // @[functional-unit.scala:168:14] input io_req_bits_uop_ctrl_is_sta, // @[functional-unit.scala:168:14] input io_req_bits_uop_ctrl_is_std, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_iw_state, // @[functional-unit.scala:168:14] input io_req_bits_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14] input io_req_bits_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_br, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_jalr, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_jal, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_sfb, // @[functional-unit.scala:168:14] input [7:0] io_req_bits_uop_br_mask, // @[functional-unit.scala:168:14] input [2:0] io_req_bits_uop_br_tag, // @[functional-unit.scala:168:14] input [3:0] io_req_bits_uop_ftq_idx, // @[functional-unit.scala:168:14] input io_req_bits_uop_edge_inst, // @[functional-unit.scala:168:14] input [5:0] io_req_bits_uop_pc_lob, // @[functional-unit.scala:168:14] input io_req_bits_uop_taken, // @[functional-unit.scala:168:14] input [19:0] io_req_bits_uop_imm_packed, // @[functional-unit.scala:168:14] input [11:0] io_req_bits_uop_csr_addr, // @[functional-unit.scala:168:14] input [4:0] io_req_bits_uop_rob_idx, // @[functional-unit.scala:168:14] input [2:0] io_req_bits_uop_ldq_idx, // @[functional-unit.scala:168:14] input [2:0] io_req_bits_uop_stq_idx, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_rxq_idx, // @[functional-unit.scala:168:14] input [5:0] io_req_bits_uop_pdst, // @[functional-unit.scala:168:14] input [5:0] io_req_bits_uop_prs1, // @[functional-unit.scala:168:14] input [5:0] io_req_bits_uop_prs2, // @[functional-unit.scala:168:14] input [5:0] io_req_bits_uop_prs3, // @[functional-unit.scala:168:14] input [3:0] io_req_bits_uop_ppred, // @[functional-unit.scala:168:14] input io_req_bits_uop_prs1_busy, // @[functional-unit.scala:168:14] input io_req_bits_uop_prs2_busy, // @[functional-unit.scala:168:14] input io_req_bits_uop_prs3_busy, // @[functional-unit.scala:168:14] input io_req_bits_uop_ppred_busy, // @[functional-unit.scala:168:14] input [5:0] io_req_bits_uop_stale_pdst, // @[functional-unit.scala:168:14] input io_req_bits_uop_exception, // @[functional-unit.scala:168:14] input [63:0] io_req_bits_uop_exc_cause, // @[functional-unit.scala:168:14] input io_req_bits_uop_bypassable, // @[functional-unit.scala:168:14] input [4:0] io_req_bits_uop_mem_cmd, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_mem_size, // @[functional-unit.scala:168:14] input io_req_bits_uop_mem_signed, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_fence, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_fencei, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_amo, // @[functional-unit.scala:168:14] input io_req_bits_uop_uses_ldq, // @[functional-unit.scala:168:14] input io_req_bits_uop_uses_stq, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_unique, // @[functional-unit.scala:168:14] input io_req_bits_uop_flush_on_commit, // @[functional-unit.scala:168:14] input io_req_bits_uop_ldst_is_rs1, // @[functional-unit.scala:168:14] input [5:0] io_req_bits_uop_ldst, // @[functional-unit.scala:168:14] input [5:0] io_req_bits_uop_lrs1, // @[functional-unit.scala:168:14] input [5:0] io_req_bits_uop_lrs2, // @[functional-unit.scala:168:14] input [5:0] io_req_bits_uop_lrs3, // @[functional-unit.scala:168:14] input io_req_bits_uop_ldst_val, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_dst_rtype, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_lrs1_rtype, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_lrs2_rtype, // @[functional-unit.scala:168:14] input io_req_bits_uop_frs3_en, // @[functional-unit.scala:168:14] input io_req_bits_uop_fp_val, // @[functional-unit.scala:168:14] input io_req_bits_uop_fp_single, // @[functional-unit.scala:168:14] input io_req_bits_uop_xcpt_pf_if, // @[functional-unit.scala:168:14] input io_req_bits_uop_xcpt_ae_if, // @[functional-unit.scala:168:14] input io_req_bits_uop_xcpt_ma_if, // @[functional-unit.scala:168:14] input io_req_bits_uop_bp_debug_if, // @[functional-unit.scala:168:14] input io_req_bits_uop_bp_xcpt_if, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_debug_fsrc, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_debug_tsrc, // @[functional-unit.scala:168:14] input [64:0] io_req_bits_rs1_data, // @[functional-unit.scala:168:14] input [64:0] io_req_bits_rs2_data, // @[functional-unit.scala:168:14] input io_req_bits_kill, // @[functional-unit.scala:168:14] output io_resp_valid, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_uop_uopc, // @[functional-unit.scala:168:14] output [31:0] io_resp_bits_uop_inst, // @[functional-unit.scala:168:14] output [31:0] io_resp_bits_uop_debug_inst, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_rvc, // @[functional-unit.scala:168:14] output [39:0] io_resp_bits_uop_debug_pc, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_uop_iq_type, // @[functional-unit.scala:168:14] output [9:0] io_resp_bits_uop_fu_code, // @[functional-unit.scala:168:14] output [3:0] io_resp_bits_uop_ctrl_br_type, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14] output io_resp_bits_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14] output io_resp_bits_uop_ctrl_is_load, // @[functional-unit.scala:168:14] output io_resp_bits_uop_ctrl_is_sta, // @[functional-unit.scala:168:14] output io_resp_bits_uop_ctrl_is_std, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_iw_state, // @[functional-unit.scala:168:14] output io_resp_bits_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14] output io_resp_bits_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_br, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_jalr, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_jal, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_sfb, // @[functional-unit.scala:168:14] output [7:0] io_resp_bits_uop_br_mask, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_uop_br_tag, // @[functional-unit.scala:168:14] output [3:0] io_resp_bits_uop_ftq_idx, // @[functional-unit.scala:168:14] output io_resp_bits_uop_edge_inst, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_uop_pc_lob, // @[functional-unit.scala:168:14] output io_resp_bits_uop_taken, // @[functional-unit.scala:168:14] output [19:0] io_resp_bits_uop_imm_packed, // @[functional-unit.scala:168:14] output [11:0] io_resp_bits_uop_csr_addr, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_uop_rob_idx, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_uop_ldq_idx, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_uop_stq_idx, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_rxq_idx, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_uop_pdst, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_uop_prs1, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_uop_prs2, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_uop_prs3, // @[functional-unit.scala:168:14] output [3:0] io_resp_bits_uop_ppred, // @[functional-unit.scala:168:14] output io_resp_bits_uop_prs1_busy, // @[functional-unit.scala:168:14] output io_resp_bits_uop_prs2_busy, // @[functional-unit.scala:168:14] output io_resp_bits_uop_prs3_busy, // @[functional-unit.scala:168:14] output io_resp_bits_uop_ppred_busy, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_uop_stale_pdst, // @[functional-unit.scala:168:14] output io_resp_bits_uop_exception, // @[functional-unit.scala:168:14] output [63:0] io_resp_bits_uop_exc_cause, // @[functional-unit.scala:168:14] output io_resp_bits_uop_bypassable, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_uop_mem_cmd, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_mem_size, // @[functional-unit.scala:168:14] output io_resp_bits_uop_mem_signed, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_fence, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_fencei, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_amo, // @[functional-unit.scala:168:14] output io_resp_bits_uop_uses_ldq, // @[functional-unit.scala:168:14] output io_resp_bits_uop_uses_stq, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_unique, // @[functional-unit.scala:168:14] output io_resp_bits_uop_flush_on_commit, // @[functional-unit.scala:168:14] output io_resp_bits_uop_ldst_is_rs1, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_uop_ldst, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_uop_lrs1, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_uop_lrs2, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_uop_lrs3, // @[functional-unit.scala:168:14] output io_resp_bits_uop_ldst_val, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_dst_rtype, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_lrs1_rtype, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_lrs2_rtype, // @[functional-unit.scala:168:14] output io_resp_bits_uop_frs3_en, // @[functional-unit.scala:168:14] output io_resp_bits_uop_fp_val, // @[functional-unit.scala:168:14] output io_resp_bits_uop_fp_single, // @[functional-unit.scala:168:14] output io_resp_bits_uop_xcpt_pf_if, // @[functional-unit.scala:168:14] output io_resp_bits_uop_xcpt_ae_if, // @[functional-unit.scala:168:14] output io_resp_bits_uop_xcpt_ma_if, // @[functional-unit.scala:168:14] output io_resp_bits_uop_bp_debug_if, // @[functional-unit.scala:168:14] output io_resp_bits_uop_bp_xcpt_if, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_debug_fsrc, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_debug_tsrc, // @[functional-unit.scala:168:14] output [64:0] io_resp_bits_data, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_valid, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_fflags_bits_uop_uopc, // @[functional-unit.scala:168:14] output [31:0] io_resp_bits_fflags_bits_uop_inst, // @[functional-unit.scala:168:14] output [31:0] io_resp_bits_fflags_bits_uop_debug_inst, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_rvc, // @[functional-unit.scala:168:14] output [39:0] io_resp_bits_fflags_bits_uop_debug_pc, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_fflags_bits_uop_iq_type, // @[functional-unit.scala:168:14] output [9:0] io_resp_bits_fflags_bits_uop_fu_code, // @[functional-unit.scala:168:14] output [3:0] io_resp_bits_fflags_bits_uop_ctrl_br_type, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_fflags_bits_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_fflags_bits_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_fflags_bits_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_fflags_bits_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_ctrl_is_load, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_ctrl_is_sta, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_ctrl_is_std, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_iw_state, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_br, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_jalr, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_jal, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_sfb, // @[functional-unit.scala:168:14] output [7:0] io_resp_bits_fflags_bits_uop_br_mask, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_fflags_bits_uop_br_tag, // @[functional-unit.scala:168:14] output [3:0] io_resp_bits_fflags_bits_uop_ftq_idx, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_edge_inst, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_fflags_bits_uop_pc_lob, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_taken, // @[functional-unit.scala:168:14] output [19:0] io_resp_bits_fflags_bits_uop_imm_packed, // @[functional-unit.scala:168:14] output [11:0] io_resp_bits_fflags_bits_uop_csr_addr, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_fflags_bits_uop_rob_idx, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_fflags_bits_uop_ldq_idx, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_fflags_bits_uop_stq_idx, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_rxq_idx, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_fflags_bits_uop_pdst, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_fflags_bits_uop_prs1, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_fflags_bits_uop_prs2, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_fflags_bits_uop_prs3, // @[functional-unit.scala:168:14] output [3:0] io_resp_bits_fflags_bits_uop_ppred, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_prs1_busy, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_prs2_busy, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_prs3_busy, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_ppred_busy, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_fflags_bits_uop_stale_pdst, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_exception, // @[functional-unit.scala:168:14] output [63:0] io_resp_bits_fflags_bits_uop_exc_cause, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_bypassable, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_fflags_bits_uop_mem_cmd, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_mem_size, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_mem_signed, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_fence, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_fencei, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_amo, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_uses_ldq, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_uses_stq, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_unique, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_flush_on_commit, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_ldst_is_rs1, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_fflags_bits_uop_ldst, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_fflags_bits_uop_lrs1, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_fflags_bits_uop_lrs2, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_fflags_bits_uop_lrs3, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_ldst_val, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_dst_rtype, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_lrs1_rtype, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_lrs2_rtype, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_frs3_en, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_fp_val, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_fp_single, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_xcpt_pf_if, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_xcpt_ae_if, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_xcpt_ma_if, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_bp_debug_if, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_bp_xcpt_if, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_debug_fsrc, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_debug_tsrc, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_fflags_bits_flags, // @[functional-unit.scala:168:14] input [7:0] io_brupdate_b1_resolve_mask, // @[functional-unit.scala:168:14] input [7:0] io_brupdate_b1_mispredict_mask, // @[functional-unit.scala:168:14] input [6:0] io_brupdate_b2_uop_uopc, // @[functional-unit.scala:168:14] input [31:0] io_brupdate_b2_uop_inst, // @[functional-unit.scala:168:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_rvc, // @[functional-unit.scala:168:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[functional-unit.scala:168:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[functional-unit.scala:168:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[functional-unit.scala:168:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_ctrl_is_load, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_ctrl_is_std, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_br, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_jalr, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_jal, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_sfb, // @[functional-unit.scala:168:14] input [7:0] io_brupdate_b2_uop_br_mask, // @[functional-unit.scala:168:14] input [2:0] io_brupdate_b2_uop_br_tag, // @[functional-unit.scala:168:14] input [3:0] io_brupdate_b2_uop_ftq_idx, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_edge_inst, // @[functional-unit.scala:168:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_taken, // @[functional-unit.scala:168:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[functional-unit.scala:168:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[functional-unit.scala:168:14] input [4:0] io_brupdate_b2_uop_rob_idx, // @[functional-unit.scala:168:14] input [2:0] io_brupdate_b2_uop_ldq_idx, // @[functional-unit.scala:168:14] input [2:0] io_brupdate_b2_uop_stq_idx, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[functional-unit.scala:168:14] input [5:0] io_brupdate_b2_uop_pdst, // @[functional-unit.scala:168:14] input [5:0] io_brupdate_b2_uop_prs1, // @[functional-unit.scala:168:14] input [5:0] io_brupdate_b2_uop_prs2, // @[functional-unit.scala:168:14] input [5:0] io_brupdate_b2_uop_prs3, // @[functional-unit.scala:168:14] input [3:0] io_brupdate_b2_uop_ppred, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_prs1_busy, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_prs2_busy, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_prs3_busy, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_ppred_busy, // @[functional-unit.scala:168:14] input [5:0] io_brupdate_b2_uop_stale_pdst, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_exception, // @[functional-unit.scala:168:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_bypassable, // @[functional-unit.scala:168:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_mem_signed, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_fence, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_fencei, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_amo, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_uses_ldq, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_uses_stq, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_unique, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_flush_on_commit, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[functional-unit.scala:168:14] input [5:0] io_brupdate_b2_uop_ldst, // @[functional-unit.scala:168:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[functional-unit.scala:168:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[functional-unit.scala:168:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_ldst_val, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_frs3_en, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_fp_val, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_fp_single, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_bp_debug_if, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[functional-unit.scala:168:14] input io_brupdate_b2_valid, // @[functional-unit.scala:168:14] input io_brupdate_b2_mispredict, // @[functional-unit.scala:168:14] input io_brupdate_b2_taken, // @[functional-unit.scala:168:14] input [2:0] io_brupdate_b2_cfi_type, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_pc_sel, // @[functional-unit.scala:168:14] input [39:0] io_brupdate_b2_jalr_target, // @[functional-unit.scala:168:14] input [20:0] io_brupdate_b2_target_offset, // @[functional-unit.scala:168:14] input [2:0] io_fcsr_rm // @[functional-unit.scala:168:14] ); wire [1:0] io_resp_bits_uop_debug_tsrc_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_uop_debug_fsrc_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_bp_xcpt_if_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_bp_debug_if_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_xcpt_ma_if_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_xcpt_ae_if_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_xcpt_pf_if_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_fp_single_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_fp_val_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_frs3_en_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_uop_lrs2_rtype_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_uop_lrs1_rtype_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_uop_dst_rtype_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_ldst_val_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_uop_lrs3_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_uop_lrs2_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_uop_lrs1_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_uop_ldst_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_ldst_is_rs1_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_flush_on_commit_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_is_unique_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_is_sys_pc2epc_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_uses_stq_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_uses_ldq_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_is_amo_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_is_fencei_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_is_fence_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_mem_signed_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_uop_mem_size_0; // @[functional-unit.scala:591:7] wire [4:0] io_resp_bits_uop_mem_cmd_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_bypassable_0; // @[functional-unit.scala:591:7] wire [63:0] io_resp_bits_uop_exc_cause_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_exception_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_uop_stale_pdst_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_ppred_busy_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_prs3_busy_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_prs2_busy_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_prs1_busy_0; // @[functional-unit.scala:591:7] wire [3:0] io_resp_bits_uop_ppred_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_uop_prs3_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_uop_prs2_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_uop_prs1_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_uop_pdst_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_uop_rxq_idx_0; // @[functional-unit.scala:591:7] wire [2:0] io_resp_bits_uop_stq_idx_0; // @[functional-unit.scala:591:7] wire [2:0] io_resp_bits_uop_ldq_idx_0; // @[functional-unit.scala:591:7] wire [4:0] io_resp_bits_uop_rob_idx_0; // @[functional-unit.scala:591:7] wire [11:0] io_resp_bits_uop_csr_addr_0; // @[functional-unit.scala:591:7] wire [19:0] io_resp_bits_uop_imm_packed_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_taken_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_uop_pc_lob_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_edge_inst_0; // @[functional-unit.scala:591:7] wire [3:0] io_resp_bits_uop_ftq_idx_0; // @[functional-unit.scala:591:7] wire [2:0] io_resp_bits_uop_br_tag_0; // @[functional-unit.scala:591:7] wire [7:0] io_resp_bits_uop_br_mask_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_is_sfb_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_is_jal_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_is_jalr_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_is_br_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_iw_p2_poisoned_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_iw_p1_poisoned_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_uop_iw_state_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_ctrl_is_std_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_ctrl_is_sta_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_ctrl_is_load_0; // @[functional-unit.scala:591:7] wire [2:0] io_resp_bits_uop_ctrl_csr_cmd_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_ctrl_fcn_dw_0; // @[functional-unit.scala:591:7] wire [4:0] io_resp_bits_uop_ctrl_op_fcn_0; // @[functional-unit.scala:591:7] wire [2:0] io_resp_bits_uop_ctrl_imm_sel_0; // @[functional-unit.scala:591:7] wire [2:0] io_resp_bits_uop_ctrl_op2_sel_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_uop_ctrl_op1_sel_0; // @[functional-unit.scala:591:7] wire [3:0] io_resp_bits_uop_ctrl_br_type_0; // @[functional-unit.scala:591:7] wire [9:0] io_resp_bits_uop_fu_code_0; // @[functional-unit.scala:591:7] wire [2:0] io_resp_bits_uop_iq_type_0; // @[functional-unit.scala:591:7] wire [39:0] io_resp_bits_uop_debug_pc_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_is_rvc_0; // @[functional-unit.scala:591:7] wire [31:0] io_resp_bits_uop_debug_inst_0; // @[functional-unit.scala:591:7] wire [31:0] io_resp_bits_uop_inst_0; // @[functional-unit.scala:591:7] wire [6:0] io_resp_bits_uop_uopc_0; // @[functional-unit.scala:591:7] wire [64:0] _ifpu_io_out_bits_data; // @[functional-unit.scala:624:20] wire [1:0] _fp_decoder_io_sigs_typeTagIn; // @[functional-unit.scala:600:26] wire [1:0] _fp_decoder_io_sigs_typeTagOut; // @[functional-unit.scala:600:26] wire _fp_decoder_io_sigs_fromint; // @[functional-unit.scala:600:26] wire io_req_valid_0 = io_req_valid; // @[functional-unit.scala:591:7] wire [6:0] io_req_bits_uop_uopc_0 = io_req_bits_uop_uopc; // @[functional-unit.scala:591:7] wire [31:0] io_req_bits_uop_inst_0 = io_req_bits_uop_inst; // @[functional-unit.scala:591:7] wire [31:0] io_req_bits_uop_debug_inst_0 = io_req_bits_uop_debug_inst; // @[functional-unit.scala:591:7] wire io_req_bits_uop_is_rvc_0 = io_req_bits_uop_is_rvc; // @[functional-unit.scala:591:7] wire [39:0] io_req_bits_uop_debug_pc_0 = io_req_bits_uop_debug_pc; // @[functional-unit.scala:591:7] wire [2:0] io_req_bits_uop_iq_type_0 = io_req_bits_uop_iq_type; // @[functional-unit.scala:591:7] wire [9:0] io_req_bits_uop_fu_code_0 = io_req_bits_uop_fu_code; // @[functional-unit.scala:591:7] wire [3:0] io_req_bits_uop_ctrl_br_type_0 = io_req_bits_uop_ctrl_br_type; // @[functional-unit.scala:591:7] wire [1:0] io_req_bits_uop_ctrl_op1_sel_0 = io_req_bits_uop_ctrl_op1_sel; // @[functional-unit.scala:591:7] wire [2:0] io_req_bits_uop_ctrl_op2_sel_0 = io_req_bits_uop_ctrl_op2_sel; // @[functional-unit.scala:591:7] wire [2:0] io_req_bits_uop_ctrl_imm_sel_0 = io_req_bits_uop_ctrl_imm_sel; // @[functional-unit.scala:591:7] wire [4:0] io_req_bits_uop_ctrl_op_fcn_0 = io_req_bits_uop_ctrl_op_fcn; // @[functional-unit.scala:591:7] wire io_req_bits_uop_ctrl_fcn_dw_0 = io_req_bits_uop_ctrl_fcn_dw; // @[functional-unit.scala:591:7] wire [2:0] io_req_bits_uop_ctrl_csr_cmd_0 = io_req_bits_uop_ctrl_csr_cmd; // @[functional-unit.scala:591:7] wire io_req_bits_uop_ctrl_is_load_0 = io_req_bits_uop_ctrl_is_load; // @[functional-unit.scala:591:7] wire io_req_bits_uop_ctrl_is_sta_0 = io_req_bits_uop_ctrl_is_sta; // @[functional-unit.scala:591:7] wire io_req_bits_uop_ctrl_is_std_0 = io_req_bits_uop_ctrl_is_std; // @[functional-unit.scala:591:7] wire [1:0] io_req_bits_uop_iw_state_0 = io_req_bits_uop_iw_state; // @[functional-unit.scala:591:7] wire io_req_bits_uop_iw_p1_poisoned_0 = io_req_bits_uop_iw_p1_poisoned; // @[functional-unit.scala:591:7] wire io_req_bits_uop_iw_p2_poisoned_0 = io_req_bits_uop_iw_p2_poisoned; // @[functional-unit.scala:591:7] wire io_req_bits_uop_is_br_0 = io_req_bits_uop_is_br; // @[functional-unit.scala:591:7] wire io_req_bits_uop_is_jalr_0 = io_req_bits_uop_is_jalr; // @[functional-unit.scala:591:7] wire io_req_bits_uop_is_jal_0 = io_req_bits_uop_is_jal; // @[functional-unit.scala:591:7] wire io_req_bits_uop_is_sfb_0 = io_req_bits_uop_is_sfb; // @[functional-unit.scala:591:7] wire [7:0] io_req_bits_uop_br_mask_0 = io_req_bits_uop_br_mask; // @[functional-unit.scala:591:7] wire [2:0] io_req_bits_uop_br_tag_0 = io_req_bits_uop_br_tag; // @[functional-unit.scala:591:7] wire [3:0] io_req_bits_uop_ftq_idx_0 = io_req_bits_uop_ftq_idx; // @[functional-unit.scala:591:7] wire io_req_bits_uop_edge_inst_0 = io_req_bits_uop_edge_inst; // @[functional-unit.scala:591:7] wire [5:0] io_req_bits_uop_pc_lob_0 = io_req_bits_uop_pc_lob; // @[functional-unit.scala:591:7] wire io_req_bits_uop_taken_0 = io_req_bits_uop_taken; // @[functional-unit.scala:591:7] wire [19:0] io_req_bits_uop_imm_packed_0 = io_req_bits_uop_imm_packed; // @[functional-unit.scala:591:7] wire [11:0] io_req_bits_uop_csr_addr_0 = io_req_bits_uop_csr_addr; // @[functional-unit.scala:591:7] wire [4:0] io_req_bits_uop_rob_idx_0 = io_req_bits_uop_rob_idx; // @[functional-unit.scala:591:7] wire [2:0] io_req_bits_uop_ldq_idx_0 = io_req_bits_uop_ldq_idx; // @[functional-unit.scala:591:7] wire [2:0] io_req_bits_uop_stq_idx_0 = io_req_bits_uop_stq_idx; // @[functional-unit.scala:591:7] wire [1:0] io_req_bits_uop_rxq_idx_0 = io_req_bits_uop_rxq_idx; // @[functional-unit.scala:591:7] wire [5:0] io_req_bits_uop_pdst_0 = io_req_bits_uop_pdst; // @[functional-unit.scala:591:7] wire [5:0] io_req_bits_uop_prs1_0 = io_req_bits_uop_prs1; // @[functional-unit.scala:591:7] wire [5:0] io_req_bits_uop_prs2_0 = io_req_bits_uop_prs2; // @[functional-unit.scala:591:7] wire [5:0] io_req_bits_uop_prs3_0 = io_req_bits_uop_prs3; // @[functional-unit.scala:591:7] wire [3:0] io_req_bits_uop_ppred_0 = io_req_bits_uop_ppred; // @[functional-unit.scala:591:7] wire io_req_bits_uop_prs1_busy_0 = io_req_bits_uop_prs1_busy; // @[functional-unit.scala:591:7] wire io_req_bits_uop_prs2_busy_0 = io_req_bits_uop_prs2_busy; // @[functional-unit.scala:591:7] wire io_req_bits_uop_prs3_busy_0 = io_req_bits_uop_prs3_busy; // @[functional-unit.scala:591:7] wire io_req_bits_uop_ppred_busy_0 = io_req_bits_uop_ppred_busy; // @[functional-unit.scala:591:7] wire [5:0] io_req_bits_uop_stale_pdst_0 = io_req_bits_uop_stale_pdst; // @[functional-unit.scala:591:7] wire io_req_bits_uop_exception_0 = io_req_bits_uop_exception; // @[functional-unit.scala:591:7] wire [63:0] io_req_bits_uop_exc_cause_0 = io_req_bits_uop_exc_cause; // @[functional-unit.scala:591:7] wire io_req_bits_uop_bypassable_0 = io_req_bits_uop_bypassable; // @[functional-unit.scala:591:7] wire [4:0] io_req_bits_uop_mem_cmd_0 = io_req_bits_uop_mem_cmd; // @[functional-unit.scala:591:7] wire [1:0] io_req_bits_uop_mem_size_0 = io_req_bits_uop_mem_size; // @[functional-unit.scala:591:7] wire io_req_bits_uop_mem_signed_0 = io_req_bits_uop_mem_signed; // @[functional-unit.scala:591:7] wire io_req_bits_uop_is_fence_0 = io_req_bits_uop_is_fence; // @[functional-unit.scala:591:7] wire io_req_bits_uop_is_fencei_0 = io_req_bits_uop_is_fencei; // @[functional-unit.scala:591:7] wire io_req_bits_uop_is_amo_0 = io_req_bits_uop_is_amo; // @[functional-unit.scala:591:7] wire io_req_bits_uop_uses_ldq_0 = io_req_bits_uop_uses_ldq; // @[functional-unit.scala:591:7] wire io_req_bits_uop_uses_stq_0 = io_req_bits_uop_uses_stq; // @[functional-unit.scala:591:7] wire io_req_bits_uop_is_sys_pc2epc_0 = io_req_bits_uop_is_sys_pc2epc; // @[functional-unit.scala:591:7] wire io_req_bits_uop_is_unique_0 = io_req_bits_uop_is_unique; // @[functional-unit.scala:591:7] wire io_req_bits_uop_flush_on_commit_0 = io_req_bits_uop_flush_on_commit; // @[functional-unit.scala:591:7] wire io_req_bits_uop_ldst_is_rs1_0 = io_req_bits_uop_ldst_is_rs1; // @[functional-unit.scala:591:7] wire [5:0] io_req_bits_uop_ldst_0 = io_req_bits_uop_ldst; // @[functional-unit.scala:591:7] wire [5:0] io_req_bits_uop_lrs1_0 = io_req_bits_uop_lrs1; // @[functional-unit.scala:591:7] wire [5:0] io_req_bits_uop_lrs2_0 = io_req_bits_uop_lrs2; // @[functional-unit.scala:591:7] wire [5:0] io_req_bits_uop_lrs3_0 = io_req_bits_uop_lrs3; // @[functional-unit.scala:591:7] wire io_req_bits_uop_ldst_val_0 = io_req_bits_uop_ldst_val; // @[functional-unit.scala:591:7] wire [1:0] io_req_bits_uop_dst_rtype_0 = io_req_bits_uop_dst_rtype; // @[functional-unit.scala:591:7] wire [1:0] io_req_bits_uop_lrs1_rtype_0 = io_req_bits_uop_lrs1_rtype; // @[functional-unit.scala:591:7] wire [1:0] io_req_bits_uop_lrs2_rtype_0 = io_req_bits_uop_lrs2_rtype; // @[functional-unit.scala:591:7] wire io_req_bits_uop_frs3_en_0 = io_req_bits_uop_frs3_en; // @[functional-unit.scala:591:7] wire io_req_bits_uop_fp_val_0 = io_req_bits_uop_fp_val; // @[functional-unit.scala:591:7] wire io_req_bits_uop_fp_single_0 = io_req_bits_uop_fp_single; // @[functional-unit.scala:591:7] wire io_req_bits_uop_xcpt_pf_if_0 = io_req_bits_uop_xcpt_pf_if; // @[functional-unit.scala:591:7] wire io_req_bits_uop_xcpt_ae_if_0 = io_req_bits_uop_xcpt_ae_if; // @[functional-unit.scala:591:7] wire io_req_bits_uop_xcpt_ma_if_0 = io_req_bits_uop_xcpt_ma_if; // @[functional-unit.scala:591:7] wire io_req_bits_uop_bp_debug_if_0 = io_req_bits_uop_bp_debug_if; // @[functional-unit.scala:591:7] wire io_req_bits_uop_bp_xcpt_if_0 = io_req_bits_uop_bp_xcpt_if; // @[functional-unit.scala:591:7] wire [1:0] io_req_bits_uop_debug_fsrc_0 = io_req_bits_uop_debug_fsrc; // @[functional-unit.scala:591:7] wire [1:0] io_req_bits_uop_debug_tsrc_0 = io_req_bits_uop_debug_tsrc; // @[functional-unit.scala:591:7] wire [64:0] io_req_bits_rs1_data_0 = io_req_bits_rs1_data; // @[functional-unit.scala:591:7] wire [64:0] io_req_bits_rs2_data_0 = io_req_bits_rs2_data; // @[functional-unit.scala:591:7] wire io_req_bits_kill_0 = io_req_bits_kill; // @[functional-unit.scala:591:7] wire [7:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[functional-unit.scala:591:7] wire [7:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[functional-unit.scala:591:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[functional-unit.scala:591:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[functional-unit.scala:591:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[functional-unit.scala:591:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[functional-unit.scala:591:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[functional-unit.scala:591:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[functional-unit.scala:591:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[functional-unit.scala:591:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[functional-unit.scala:591:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[functional-unit.scala:591:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[functional-unit.scala:591:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[functional-unit.scala:591:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[functional-unit.scala:591:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[functional-unit.scala:591:7] wire [7:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[functional-unit.scala:591:7] wire [2:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[functional-unit.scala:591:7] wire [3:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[functional-unit.scala:591:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[functional-unit.scala:591:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[functional-unit.scala:591:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[functional-unit.scala:591:7] wire [4:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[functional-unit.scala:591:7] wire [2:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[functional-unit.scala:591:7] wire [2:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[functional-unit.scala:591:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[functional-unit.scala:591:7] wire [5:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[functional-unit.scala:591:7] wire [5:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[functional-unit.scala:591:7] wire [5:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[functional-unit.scala:591:7] wire [5:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[functional-unit.scala:591:7] wire [3:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[functional-unit.scala:591:7] wire [5:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[functional-unit.scala:591:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[functional-unit.scala:591:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[functional-unit.scala:591:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[functional-unit.scala:591:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[functional-unit.scala:591:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[functional-unit.scala:591:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[functional-unit.scala:591:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[functional-unit.scala:591:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[functional-unit.scala:591:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[functional-unit.scala:591:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[functional-unit.scala:591:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[functional-unit.scala:591:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[functional-unit.scala:591:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[functional-unit.scala:591:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[functional-unit.scala:591:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[functional-unit.scala:591:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[functional-unit.scala:591:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[functional-unit.scala:591:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[functional-unit.scala:591:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[functional-unit.scala:591:7] wire [2:0] io_fcsr_rm_0 = io_fcsr_rm; // @[functional-unit.scala:591:7] wire io_req_ready = 1'h1; // @[functional-unit.scala:591:7] wire _io_resp_bits_data_opts_bigger_swizzledNaN_T = 1'h1; // @[FPU.scala:338:42] wire _io_resp_bits_data_opts_bigger_T = 1'h1; // @[FPU.scala:249:56] wire [64:0] io_req_bits_rs3_data = 65'h0; // @[functional-unit.scala:591:7] wire [64:0] req_in3 = 65'h0; // @[functional-unit.scala:605:17] wire io_req_bits_pred_data = 1'h0; // @[functional-unit.scala:591:7] wire io_resp_ready = 1'h0; // @[functional-unit.scala:591:7] wire io_resp_bits_predicated = 1'h0; // @[functional-unit.scala:591:7] wire io_resp_bits_mxcpt_valid = 1'h0; // @[functional-unit.scala:591:7] wire io_resp_bits_sfence_valid = 1'h0; // @[functional-unit.scala:591:7] wire io_resp_bits_sfence_bits_rs1 = 1'h0; // @[functional-unit.scala:591:7] wire io_resp_bits_sfence_bits_rs2 = 1'h0; // @[functional-unit.scala:591:7] wire io_resp_bits_sfence_bits_asid = 1'h0; // @[functional-unit.scala:591:7] wire io_resp_bits_sfence_bits_hv = 1'h0; // @[functional-unit.scala:591:7] wire io_resp_bits_sfence_bits_hg = 1'h0; // @[functional-unit.scala:591:7] wire _r_valids_WIRE_0 = 1'h0; // @[functional-unit.scala:236:35] wire _r_valids_WIRE_1 = 1'h0; // @[functional-unit.scala:236:35] wire req_vec = 1'h0; // @[functional-unit.scala:605:17] wire [39:0] io_resp_bits_addr = 40'h0; // @[functional-unit.scala:591:7] wire [24:0] io_resp_bits_mxcpt_bits = 25'h0; // @[functional-unit.scala:591:7] wire [38:0] io_resp_bits_sfence_bits_addr = 39'h0; // @[functional-unit.scala:591:7] wire [4:0] io_resp_bits_data_opts_bigger_swizzledNaN_hi_hi = 5'h1F; // @[FPU.scala:336:26] wire [1:0] req_fmaCmd = 2'h0; // @[functional-unit.scala:605:17] wire [1:0] req_fmt = 2'h0; // @[functional-unit.scala:605:17] wire _io_resp_valid_T_3; // @[functional-unit.scala:257:47] wire [6:0] io_resp_bits_fflags_bits_uop_uopc_0 = io_resp_bits_uop_uopc_0; // @[functional-unit.scala:591:7] wire [31:0] io_resp_bits_fflags_bits_uop_inst_0 = io_resp_bits_uop_inst_0; // @[functional-unit.scala:591:7] wire [31:0] io_resp_bits_fflags_bits_uop_debug_inst_0 = io_resp_bits_uop_debug_inst_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_is_rvc_0 = io_resp_bits_uop_is_rvc_0; // @[functional-unit.scala:591:7] wire [39:0] io_resp_bits_fflags_bits_uop_debug_pc_0 = io_resp_bits_uop_debug_pc_0; // @[functional-unit.scala:591:7] wire [2:0] io_resp_bits_fflags_bits_uop_iq_type_0 = io_resp_bits_uop_iq_type_0; // @[functional-unit.scala:591:7] wire [9:0] io_resp_bits_fflags_bits_uop_fu_code_0 = io_resp_bits_uop_fu_code_0; // @[functional-unit.scala:591:7] wire [3:0] io_resp_bits_fflags_bits_uop_ctrl_br_type_0 = io_resp_bits_uop_ctrl_br_type_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_fflags_bits_uop_ctrl_op1_sel_0 = io_resp_bits_uop_ctrl_op1_sel_0; // @[functional-unit.scala:591:7] wire [2:0] io_resp_bits_fflags_bits_uop_ctrl_op2_sel_0 = io_resp_bits_uop_ctrl_op2_sel_0; // @[functional-unit.scala:591:7] wire [2:0] io_resp_bits_fflags_bits_uop_ctrl_imm_sel_0 = io_resp_bits_uop_ctrl_imm_sel_0; // @[functional-unit.scala:591:7] wire [4:0] io_resp_bits_fflags_bits_uop_ctrl_op_fcn_0 = io_resp_bits_uop_ctrl_op_fcn_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_ctrl_fcn_dw_0 = io_resp_bits_uop_ctrl_fcn_dw_0; // @[functional-unit.scala:591:7] wire [2:0] io_resp_bits_fflags_bits_uop_ctrl_csr_cmd_0 = io_resp_bits_uop_ctrl_csr_cmd_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_ctrl_is_load_0 = io_resp_bits_uop_ctrl_is_load_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_ctrl_is_sta_0 = io_resp_bits_uop_ctrl_is_sta_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_ctrl_is_std_0 = io_resp_bits_uop_ctrl_is_std_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_fflags_bits_uop_iw_state_0 = io_resp_bits_uop_iw_state_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_iw_p1_poisoned_0 = io_resp_bits_uop_iw_p1_poisoned_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_iw_p2_poisoned_0 = io_resp_bits_uop_iw_p2_poisoned_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_is_br_0 = io_resp_bits_uop_is_br_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_is_jalr_0 = io_resp_bits_uop_is_jalr_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_is_jal_0 = io_resp_bits_uop_is_jal_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_is_sfb_0 = io_resp_bits_uop_is_sfb_0; // @[functional-unit.scala:591:7] wire [7:0] _io_resp_bits_uop_br_mask_T_1; // @[util.scala:85:25] wire [7:0] io_resp_bits_fflags_bits_uop_br_mask_0 = io_resp_bits_uop_br_mask_0; // @[functional-unit.scala:591:7] wire [2:0] io_resp_bits_fflags_bits_uop_br_tag_0 = io_resp_bits_uop_br_tag_0; // @[functional-unit.scala:591:7] wire [3:0] io_resp_bits_fflags_bits_uop_ftq_idx_0 = io_resp_bits_uop_ftq_idx_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_edge_inst_0 = io_resp_bits_uop_edge_inst_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_fflags_bits_uop_pc_lob_0 = io_resp_bits_uop_pc_lob_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_taken_0 = io_resp_bits_uop_taken_0; // @[functional-unit.scala:591:7] wire [19:0] io_resp_bits_fflags_bits_uop_imm_packed_0 = io_resp_bits_uop_imm_packed_0; // @[functional-unit.scala:591:7] wire [11:0] io_resp_bits_fflags_bits_uop_csr_addr_0 = io_resp_bits_uop_csr_addr_0; // @[functional-unit.scala:591:7] wire [4:0] io_resp_bits_fflags_bits_uop_rob_idx_0 = io_resp_bits_uop_rob_idx_0; // @[functional-unit.scala:591:7] wire [2:0] io_resp_bits_fflags_bits_uop_ldq_idx_0 = io_resp_bits_uop_ldq_idx_0; // @[functional-unit.scala:591:7] wire [2:0] io_resp_bits_fflags_bits_uop_stq_idx_0 = io_resp_bits_uop_stq_idx_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_fflags_bits_uop_rxq_idx_0 = io_resp_bits_uop_rxq_idx_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_fflags_bits_uop_pdst_0 = io_resp_bits_uop_pdst_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_fflags_bits_uop_prs1_0 = io_resp_bits_uop_prs1_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_fflags_bits_uop_prs2_0 = io_resp_bits_uop_prs2_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_fflags_bits_uop_prs3_0 = io_resp_bits_uop_prs3_0; // @[functional-unit.scala:591:7] wire [3:0] io_resp_bits_fflags_bits_uop_ppred_0 = io_resp_bits_uop_ppred_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_prs1_busy_0 = io_resp_bits_uop_prs1_busy_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_prs2_busy_0 = io_resp_bits_uop_prs2_busy_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_prs3_busy_0 = io_resp_bits_uop_prs3_busy_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_ppred_busy_0 = io_resp_bits_uop_ppred_busy_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_fflags_bits_uop_stale_pdst_0 = io_resp_bits_uop_stale_pdst_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_exception_0 = io_resp_bits_uop_exception_0; // @[functional-unit.scala:591:7] wire [63:0] io_resp_bits_fflags_bits_uop_exc_cause_0 = io_resp_bits_uop_exc_cause_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_bypassable_0 = io_resp_bits_uop_bypassable_0; // @[functional-unit.scala:591:7] wire [4:0] io_resp_bits_fflags_bits_uop_mem_cmd_0 = io_resp_bits_uop_mem_cmd_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_fflags_bits_uop_mem_size_0 = io_resp_bits_uop_mem_size_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_mem_signed_0 = io_resp_bits_uop_mem_signed_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_is_fence_0 = io_resp_bits_uop_is_fence_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_is_fencei_0 = io_resp_bits_uop_is_fencei_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_is_amo_0 = io_resp_bits_uop_is_amo_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_uses_ldq_0 = io_resp_bits_uop_uses_ldq_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_uses_stq_0 = io_resp_bits_uop_uses_stq_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_is_sys_pc2epc_0 = io_resp_bits_uop_is_sys_pc2epc_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_is_unique_0 = io_resp_bits_uop_is_unique_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_flush_on_commit_0 = io_resp_bits_uop_flush_on_commit_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_ldst_is_rs1_0 = io_resp_bits_uop_ldst_is_rs1_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_fflags_bits_uop_ldst_0 = io_resp_bits_uop_ldst_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_fflags_bits_uop_lrs1_0 = io_resp_bits_uop_lrs1_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_fflags_bits_uop_lrs2_0 = io_resp_bits_uop_lrs2_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_fflags_bits_uop_lrs3_0 = io_resp_bits_uop_lrs3_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_ldst_val_0 = io_resp_bits_uop_ldst_val_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_fflags_bits_uop_dst_rtype_0 = io_resp_bits_uop_dst_rtype_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_fflags_bits_uop_lrs1_rtype_0 = io_resp_bits_uop_lrs1_rtype_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_fflags_bits_uop_lrs2_rtype_0 = io_resp_bits_uop_lrs2_rtype_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_frs3_en_0 = io_resp_bits_uop_frs3_en_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_fp_val_0 = io_resp_bits_uop_fp_val_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_fp_single_0 = io_resp_bits_uop_fp_single_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_xcpt_pf_if_0 = io_resp_bits_uop_xcpt_pf_if_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_xcpt_ae_if_0 = io_resp_bits_uop_xcpt_ae_if_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_xcpt_ma_if_0 = io_resp_bits_uop_xcpt_ma_if_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_bp_debug_if_0 = io_resp_bits_uop_bp_debug_if_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_bp_xcpt_if_0 = io_resp_bits_uop_bp_xcpt_if_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_fflags_bits_uop_debug_fsrc_0 = io_resp_bits_uop_debug_fsrc_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_fflags_bits_uop_debug_tsrc_0 = io_resp_bits_uop_debug_tsrc_0; // @[functional-unit.scala:591:7] wire [64:0] _io_resp_bits_data_T_1; // @[package.scala:39:76] wire [4:0] io_resp_bits_fflags_bits_flags_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_valid_0; // @[functional-unit.scala:591:7] wire [64:0] io_resp_bits_data_0; // @[functional-unit.scala:591:7] wire io_resp_valid_0; // @[functional-unit.scala:591:7] reg r_valids_0; // @[functional-unit.scala:236:27] reg r_valids_1; // @[functional-unit.scala:236:27] reg [6:0] r_uops_0_uopc; // @[functional-unit.scala:237:23] reg [31:0] r_uops_0_inst; // @[functional-unit.scala:237:23] reg [31:0] r_uops_0_debug_inst; // @[functional-unit.scala:237:23] reg r_uops_0_is_rvc; // @[functional-unit.scala:237:23] reg [39:0] r_uops_0_debug_pc; // @[functional-unit.scala:237:23] reg [2:0] r_uops_0_iq_type; // @[functional-unit.scala:237:23] reg [9:0] r_uops_0_fu_code; // @[functional-unit.scala:237:23] reg [3:0] r_uops_0_ctrl_br_type; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_ctrl_op1_sel; // @[functional-unit.scala:237:23] reg [2:0] r_uops_0_ctrl_op2_sel; // @[functional-unit.scala:237:23] reg [2:0] r_uops_0_ctrl_imm_sel; // @[functional-unit.scala:237:23] reg [4:0] r_uops_0_ctrl_op_fcn; // @[functional-unit.scala:237:23] reg r_uops_0_ctrl_fcn_dw; // @[functional-unit.scala:237:23] reg [2:0] r_uops_0_ctrl_csr_cmd; // @[functional-unit.scala:237:23] reg r_uops_0_ctrl_is_load; // @[functional-unit.scala:237:23] reg r_uops_0_ctrl_is_sta; // @[functional-unit.scala:237:23] reg r_uops_0_ctrl_is_std; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_iw_state; // @[functional-unit.scala:237:23] reg r_uops_0_iw_p1_poisoned; // @[functional-unit.scala:237:23] reg r_uops_0_iw_p2_poisoned; // @[functional-unit.scala:237:23] reg r_uops_0_is_br; // @[functional-unit.scala:237:23] reg r_uops_0_is_jalr; // @[functional-unit.scala:237:23] reg r_uops_0_is_jal; // @[functional-unit.scala:237:23] reg r_uops_0_is_sfb; // @[functional-unit.scala:237:23] reg [7:0] r_uops_0_br_mask; // @[functional-unit.scala:237:23] reg [2:0] r_uops_0_br_tag; // @[functional-unit.scala:237:23] reg [3:0] r_uops_0_ftq_idx; // @[functional-unit.scala:237:23] reg r_uops_0_edge_inst; // @[functional-unit.scala:237:23] reg [5:0] r_uops_0_pc_lob; // @[functional-unit.scala:237:23] reg r_uops_0_taken; // @[functional-unit.scala:237:23] reg [19:0] r_uops_0_imm_packed; // @[functional-unit.scala:237:23] reg [11:0] r_uops_0_csr_addr; // @[functional-unit.scala:237:23] reg [4:0] r_uops_0_rob_idx; // @[functional-unit.scala:237:23] reg [2:0] r_uops_0_ldq_idx; // @[functional-unit.scala:237:23] reg [2:0] r_uops_0_stq_idx; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_rxq_idx; // @[functional-unit.scala:237:23] reg [5:0] r_uops_0_pdst; // @[functional-unit.scala:237:23] reg [5:0] r_uops_0_prs1; // @[functional-unit.scala:237:23] reg [5:0] r_uops_0_prs2; // @[functional-unit.scala:237:23] reg [5:0] r_uops_0_prs3; // @[functional-unit.scala:237:23] reg [3:0] r_uops_0_ppred; // @[functional-unit.scala:237:23] reg r_uops_0_prs1_busy; // @[functional-unit.scala:237:23] reg r_uops_0_prs2_busy; // @[functional-unit.scala:237:23] reg r_uops_0_prs3_busy; // @[functional-unit.scala:237:23] reg r_uops_0_ppred_busy; // @[functional-unit.scala:237:23] reg [5:0] r_uops_0_stale_pdst; // @[functional-unit.scala:237:23] reg r_uops_0_exception; // @[functional-unit.scala:237:23] reg [63:0] r_uops_0_exc_cause; // @[functional-unit.scala:237:23] reg r_uops_0_bypassable; // @[functional-unit.scala:237:23] reg [4:0] r_uops_0_mem_cmd; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_mem_size; // @[functional-unit.scala:237:23] reg r_uops_0_mem_signed; // @[functional-unit.scala:237:23] reg r_uops_0_is_fence; // @[functional-unit.scala:237:23] reg r_uops_0_is_fencei; // @[functional-unit.scala:237:23] reg r_uops_0_is_amo; // @[functional-unit.scala:237:23] reg r_uops_0_uses_ldq; // @[functional-unit.scala:237:23] reg r_uops_0_uses_stq; // @[functional-unit.scala:237:23] reg r_uops_0_is_sys_pc2epc; // @[functional-unit.scala:237:23] reg r_uops_0_is_unique; // @[functional-unit.scala:237:23] reg r_uops_0_flush_on_commit; // @[functional-unit.scala:237:23] reg r_uops_0_ldst_is_rs1; // @[functional-unit.scala:237:23] reg [5:0] r_uops_0_ldst; // @[functional-unit.scala:237:23] reg [5:0] r_uops_0_lrs1; // @[functional-unit.scala:237:23] reg [5:0] r_uops_0_lrs2; // @[functional-unit.scala:237:23] reg [5:0] r_uops_0_lrs3; // @[functional-unit.scala:237:23] reg r_uops_0_ldst_val; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_dst_rtype; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_lrs1_rtype; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_lrs2_rtype; // @[functional-unit.scala:237:23] reg r_uops_0_frs3_en; // @[functional-unit.scala:237:23] reg r_uops_0_fp_val; // @[functional-unit.scala:237:23] reg r_uops_0_fp_single; // @[functional-unit.scala:237:23] reg r_uops_0_xcpt_pf_if; // @[functional-unit.scala:237:23] reg r_uops_0_xcpt_ae_if; // @[functional-unit.scala:237:23] reg r_uops_0_xcpt_ma_if; // @[functional-unit.scala:237:23] reg r_uops_0_bp_debug_if; // @[functional-unit.scala:237:23] reg r_uops_0_bp_xcpt_if; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_debug_fsrc; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_debug_tsrc; // @[functional-unit.scala:237:23] reg [6:0] r_uops_1_uopc; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_uopc_0 = r_uops_1_uopc; // @[functional-unit.scala:237:23, :591:7] reg [31:0] r_uops_1_inst; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_inst_0 = r_uops_1_inst; // @[functional-unit.scala:237:23, :591:7] reg [31:0] r_uops_1_debug_inst; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_debug_inst_0 = r_uops_1_debug_inst; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_is_rvc; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_rvc_0 = r_uops_1_is_rvc; // @[functional-unit.scala:237:23, :591:7] reg [39:0] r_uops_1_debug_pc; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_debug_pc_0 = r_uops_1_debug_pc; // @[functional-unit.scala:237:23, :591:7] reg [2:0] r_uops_1_iq_type; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_iq_type_0 = r_uops_1_iq_type; // @[functional-unit.scala:237:23, :591:7] reg [9:0] r_uops_1_fu_code; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_fu_code_0 = r_uops_1_fu_code; // @[functional-unit.scala:237:23, :591:7] reg [3:0] r_uops_1_ctrl_br_type; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_br_type_0 = r_uops_1_ctrl_br_type; // @[functional-unit.scala:237:23, :591:7] reg [1:0] r_uops_1_ctrl_op1_sel; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_op1_sel_0 = r_uops_1_ctrl_op1_sel; // @[functional-unit.scala:237:23, :591:7] reg [2:0] r_uops_1_ctrl_op2_sel; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_op2_sel_0 = r_uops_1_ctrl_op2_sel; // @[functional-unit.scala:237:23, :591:7] reg [2:0] r_uops_1_ctrl_imm_sel; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_imm_sel_0 = r_uops_1_ctrl_imm_sel; // @[functional-unit.scala:237:23, :591:7] reg [4:0] r_uops_1_ctrl_op_fcn; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_op_fcn_0 = r_uops_1_ctrl_op_fcn; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_ctrl_fcn_dw; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_fcn_dw_0 = r_uops_1_ctrl_fcn_dw; // @[functional-unit.scala:237:23, :591:7] reg [2:0] r_uops_1_ctrl_csr_cmd; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_csr_cmd_0 = r_uops_1_ctrl_csr_cmd; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_ctrl_is_load; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_is_load_0 = r_uops_1_ctrl_is_load; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_ctrl_is_sta; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_is_sta_0 = r_uops_1_ctrl_is_sta; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_ctrl_is_std; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_is_std_0 = r_uops_1_ctrl_is_std; // @[functional-unit.scala:237:23, :591:7] reg [1:0] r_uops_1_iw_state; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_iw_state_0 = r_uops_1_iw_state; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_iw_p1_poisoned; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_iw_p1_poisoned_0 = r_uops_1_iw_p1_poisoned; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_iw_p2_poisoned; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_iw_p2_poisoned_0 = r_uops_1_iw_p2_poisoned; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_is_br; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_br_0 = r_uops_1_is_br; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_is_jalr; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_jalr_0 = r_uops_1_is_jalr; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_is_jal; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_jal_0 = r_uops_1_is_jal; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_is_sfb; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_sfb_0 = r_uops_1_is_sfb; // @[functional-unit.scala:237:23, :591:7] reg [7:0] r_uops_1_br_mask; // @[functional-unit.scala:237:23] reg [2:0] r_uops_1_br_tag; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_br_tag_0 = r_uops_1_br_tag; // @[functional-unit.scala:237:23, :591:7] reg [3:0] r_uops_1_ftq_idx; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ftq_idx_0 = r_uops_1_ftq_idx; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_edge_inst; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_edge_inst_0 = r_uops_1_edge_inst; // @[functional-unit.scala:237:23, :591:7] reg [5:0] r_uops_1_pc_lob; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_pc_lob_0 = r_uops_1_pc_lob; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_taken; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_taken_0 = r_uops_1_taken; // @[functional-unit.scala:237:23, :591:7] reg [19:0] r_uops_1_imm_packed; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_imm_packed_0 = r_uops_1_imm_packed; // @[functional-unit.scala:237:23, :591:7] reg [11:0] r_uops_1_csr_addr; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_csr_addr_0 = r_uops_1_csr_addr; // @[functional-unit.scala:237:23, :591:7] reg [4:0] r_uops_1_rob_idx; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_rob_idx_0 = r_uops_1_rob_idx; // @[functional-unit.scala:237:23, :591:7] reg [2:0] r_uops_1_ldq_idx; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ldq_idx_0 = r_uops_1_ldq_idx; // @[functional-unit.scala:237:23, :591:7] reg [2:0] r_uops_1_stq_idx; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_stq_idx_0 = r_uops_1_stq_idx; // @[functional-unit.scala:237:23, :591:7] reg [1:0] r_uops_1_rxq_idx; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_rxq_idx_0 = r_uops_1_rxq_idx; // @[functional-unit.scala:237:23, :591:7] reg [5:0] r_uops_1_pdst; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_pdst_0 = r_uops_1_pdst; // @[functional-unit.scala:237:23, :591:7] reg [5:0] r_uops_1_prs1; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_prs1_0 = r_uops_1_prs1; // @[functional-unit.scala:237:23, :591:7] reg [5:0] r_uops_1_prs2; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_prs2_0 = r_uops_1_prs2; // @[functional-unit.scala:237:23, :591:7] reg [5:0] r_uops_1_prs3; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_prs3_0 = r_uops_1_prs3; // @[functional-unit.scala:237:23, :591:7] reg [3:0] r_uops_1_ppred; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ppred_0 = r_uops_1_ppred; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_prs1_busy; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_prs1_busy_0 = r_uops_1_prs1_busy; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_prs2_busy; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_prs2_busy_0 = r_uops_1_prs2_busy; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_prs3_busy; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_prs3_busy_0 = r_uops_1_prs3_busy; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_ppred_busy; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ppred_busy_0 = r_uops_1_ppred_busy; // @[functional-unit.scala:237:23, :591:7] reg [5:0] r_uops_1_stale_pdst; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_stale_pdst_0 = r_uops_1_stale_pdst; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_exception; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_exception_0 = r_uops_1_exception; // @[functional-unit.scala:237:23, :591:7] reg [63:0] r_uops_1_exc_cause; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_exc_cause_0 = r_uops_1_exc_cause; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_bypassable; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_bypassable_0 = r_uops_1_bypassable; // @[functional-unit.scala:237:23, :591:7] reg [4:0] r_uops_1_mem_cmd; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_mem_cmd_0 = r_uops_1_mem_cmd; // @[functional-unit.scala:237:23, :591:7] reg [1:0] r_uops_1_mem_size; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_mem_size_0 = r_uops_1_mem_size; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_mem_signed; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_mem_signed_0 = r_uops_1_mem_signed; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_is_fence; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_fence_0 = r_uops_1_is_fence; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_is_fencei; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_fencei_0 = r_uops_1_is_fencei; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_is_amo; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_amo_0 = r_uops_1_is_amo; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_uses_ldq; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_uses_ldq_0 = r_uops_1_uses_ldq; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_uses_stq; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_uses_stq_0 = r_uops_1_uses_stq; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_is_sys_pc2epc; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_sys_pc2epc_0 = r_uops_1_is_sys_pc2epc; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_is_unique; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_unique_0 = r_uops_1_is_unique; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_flush_on_commit; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_flush_on_commit_0 = r_uops_1_flush_on_commit; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_ldst_is_rs1; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ldst_is_rs1_0 = r_uops_1_ldst_is_rs1; // @[functional-unit.scala:237:23, :591:7] reg [5:0] r_uops_1_ldst; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ldst_0 = r_uops_1_ldst; // @[functional-unit.scala:237:23, :591:7] reg [5:0] r_uops_1_lrs1; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_lrs1_0 = r_uops_1_lrs1; // @[functional-unit.scala:237:23, :591:7] reg [5:0] r_uops_1_lrs2; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_lrs2_0 = r_uops_1_lrs2; // @[functional-unit.scala:237:23, :591:7] reg [5:0] r_uops_1_lrs3; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_lrs3_0 = r_uops_1_lrs3; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_ldst_val; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ldst_val_0 = r_uops_1_ldst_val; // @[functional-unit.scala:237:23, :591:7] reg [1:0] r_uops_1_dst_rtype; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_dst_rtype_0 = r_uops_1_dst_rtype; // @[functional-unit.scala:237:23, :591:7] reg [1:0] r_uops_1_lrs1_rtype; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_lrs1_rtype_0 = r_uops_1_lrs1_rtype; // @[functional-unit.scala:237:23, :591:7] reg [1:0] r_uops_1_lrs2_rtype; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_lrs2_rtype_0 = r_uops_1_lrs2_rtype; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_frs3_en; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_frs3_en_0 = r_uops_1_frs3_en; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_fp_val; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_fp_val_0 = r_uops_1_fp_val; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_fp_single; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_fp_single_0 = r_uops_1_fp_single; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_xcpt_pf_if; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_xcpt_pf_if_0 = r_uops_1_xcpt_pf_if; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_xcpt_ae_if; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_xcpt_ae_if_0 = r_uops_1_xcpt_ae_if; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_xcpt_ma_if; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_xcpt_ma_if_0 = r_uops_1_xcpt_ma_if; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_bp_debug_if; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_bp_debug_if_0 = r_uops_1_bp_debug_if; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_bp_xcpt_if; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_bp_xcpt_if_0 = r_uops_1_bp_xcpt_if; // @[functional-unit.scala:237:23, :591:7] reg [1:0] r_uops_1_debug_fsrc; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_debug_fsrc_0 = r_uops_1_debug_fsrc; // @[functional-unit.scala:237:23, :591:7] reg [1:0] r_uops_1_debug_tsrc; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_debug_tsrc_0 = r_uops_1_debug_tsrc; // @[functional-unit.scala:237:23, :591:7] wire [7:0] _r_valids_0_T = io_brupdate_b1_mispredict_mask_0 & io_req_bits_uop_br_mask_0; // @[util.scala:118:51] wire _r_valids_0_T_1 = |_r_valids_0_T; // @[util.scala:118:{51,59}] wire _r_valids_0_T_2 = ~_r_valids_0_T_1; // @[util.scala:118:59] wire _r_valids_0_T_3 = io_req_valid_0 & _r_valids_0_T_2; // @[functional-unit.scala:240:{33,36}, :591:7] wire _r_valids_0_T_4 = ~io_req_bits_kill_0; // @[functional-unit.scala:240:87, :591:7] wire _r_valids_0_T_5 = _r_valids_0_T_3 & _r_valids_0_T_4; // @[functional-unit.scala:240:{33,84,87}] wire [7:0] _r_uops_0_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27] wire [7:0] _r_uops_0_br_mask_T_1 = io_req_bits_uop_br_mask_0 & _r_uops_0_br_mask_T; // @[util.scala:85:{25,27}] wire [7:0] _r_valids_1_T = io_brupdate_b1_mispredict_mask_0 & r_uops_0_br_mask; // @[util.scala:118:51] wire _r_valids_1_T_1 = |_r_valids_1_T; // @[util.scala:118:{51,59}] wire _r_valids_1_T_2 = ~_r_valids_1_T_1; // @[util.scala:118:59] wire _r_valids_1_T_3 = r_valids_0 & _r_valids_1_T_2; // @[functional-unit.scala:236:27, :246:{36,39}] wire _r_valids_1_T_4 = ~io_req_bits_kill_0; // @[functional-unit.scala:240:87, :246:86, :591:7] wire _r_valids_1_T_5 = _r_valids_1_T_3 & _r_valids_1_T_4; // @[functional-unit.scala:246:{36,83,86}] wire [7:0] _r_uops_1_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27] wire [7:0] _r_uops_1_br_mask_T_1 = r_uops_0_br_mask & _r_uops_1_br_mask_T; // @[util.scala:85:{25,27}] wire [7:0] _io_resp_valid_T = io_brupdate_b1_mispredict_mask_0 & r_uops_1_br_mask; // @[util.scala:118:51] wire _io_resp_valid_T_1 = |_io_resp_valid_T; // @[util.scala:118:{51,59}] wire _io_resp_valid_T_2 = ~_io_resp_valid_T_1; // @[util.scala:118:59] assign _io_resp_valid_T_3 = r_valids_1 & _io_resp_valid_T_2; // @[functional-unit.scala:236:27, :257:{47,50}] assign io_resp_valid_0 = _io_resp_valid_T_3; // @[functional-unit.scala:257:47, :591:7] wire [7:0] _io_resp_bits_uop_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27] assign _io_resp_bits_uop_br_mask_T_1 = r_uops_1_br_mask & _io_resp_bits_uop_br_mask_T; // @[util.scala:85:{25,27}] assign io_resp_bits_uop_br_mask_0 = _io_resp_bits_uop_br_mask_T_1; // @[util.scala:85:25] wire [2:0] _fp_rm_T = io_req_bits_uop_imm_packed_0[2:0]; // @[util.scala:289:58] wire [2:0] _fp_rm_T_2 = io_req_bits_uop_imm_packed_0[2:0]; // @[util.scala:289:58] wire _fp_rm_T_1 = &_fp_rm_T; // @[util.scala:289:58] wire [2:0] fp_rm = _fp_rm_T_1 ? io_fcsr_rm_0 : _fp_rm_T_2; // @[util.scala:289:58] wire [2:0] req_rm = fp_rm; // @[functional-unit.scala:604:18, :605:17] wire [1:0] _req_typ_T; // @[util.scala:295:59] wire [64:0] _req_in1_T_4; // @[FPU.scala:369:10] wire [64:0] _req_in2_T_4; // @[FPU.scala:369:10] wire req_ldst; // @[functional-unit.scala:605:17] wire req_wen; // @[functional-unit.scala:605:17] wire req_ren1; // @[functional-unit.scala:605:17] wire req_ren2; // @[functional-unit.scala:605:17] wire req_ren3; // @[functional-unit.scala:605:17] wire req_swap12; // @[functional-unit.scala:605:17] wire req_swap23; // @[functional-unit.scala:605:17] wire [1:0] req_typeTagIn; // @[functional-unit.scala:605:17] wire [1:0] req_typeTagOut; // @[functional-unit.scala:605:17] wire req_fromint; // @[functional-unit.scala:605:17] wire req_toint; // @[functional-unit.scala:605:17] wire req_fastpipe; // @[functional-unit.scala:605:17] wire req_fma; // @[functional-unit.scala:605:17] wire req_div; // @[functional-unit.scala:605:17] wire req_sqrt; // @[functional-unit.scala:605:17] wire req_wflags; // @[functional-unit.scala:605:17] wire [1:0] req_typ; // @[functional-unit.scala:605:17] wire [64:0] req_in1; // @[functional-unit.scala:605:17] wire [64:0] req_in2; // @[functional-unit.scala:605:17] wire _req_in1_prev_unswizzled_T = io_req_bits_rs1_data_0[31]; // @[FPU.scala:357:14] wire _req_in1_prev_unswizzled_T_1 = io_req_bits_rs1_data_0[52]; // @[FPU.scala:358:14] wire [30:0] _req_in1_prev_unswizzled_T_2 = io_req_bits_rs1_data_0[30:0]; // @[FPU.scala:359:14] wire [1:0] req_in1_prev_unswizzled_hi = {_req_in1_prev_unswizzled_T, _req_in1_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] req_in1_prev_unswizzled = {req_in1_prev_unswizzled_hi, _req_in1_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire req_in1_prev_prev_sign = req_in1_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31] wire [22:0] req_in1_prev_prev_fractIn = req_in1_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31] wire [8:0] req_in1_prev_prev_expIn = req_in1_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31] wire [75:0] _req_in1_prev_prev_fractOut_T = {req_in1_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] req_in1_prev_prev_fractOut = _req_in1_prev_prev_fractOut_T[75:24]; // @[FPU.scala:277:{28,38}] wire [2:0] req_in1_prev_prev_expOut_expCode = req_in1_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26] wire [12:0] _req_in1_prev_prev_expOut_commonCase_T = {4'h0, req_in1_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _req_in1_prev_prev_expOut_commonCase_T_1 = _req_in1_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _req_in1_prev_prev_expOut_commonCase_T_2 = {1'h0, _req_in1_prev_prev_expOut_commonCase_T_1} - 13'h100; // @[FPU.scala:280:{31,50}] wire [11:0] req_in1_prev_prev_expOut_commonCase = _req_in1_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _req_in1_prev_prev_expOut_T_5 = req_in1_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _req_in1_prev_prev_expOut_T = req_in1_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _req_in1_prev_prev_expOut_T_1 = req_in1_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _req_in1_prev_prev_expOut_T_2 = _req_in1_prev_prev_expOut_T | _req_in1_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _req_in1_prev_prev_expOut_T_3 = req_in1_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _req_in1_prev_prev_expOut_T_4 = {req_in1_prev_prev_expOut_expCode, _req_in1_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] req_in1_prev_prev_expOut = _req_in1_prev_prev_expOut_T_2 ? _req_in1_prev_prev_expOut_T_4 : _req_in1_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] req_in1_prev_prev_hi = {req_in1_prev_prev_sign, req_in1_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] req_in1_floats_0 = {req_in1_prev_prev_hi, req_in1_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire [4:0] _req_in1_prev_isbox_T = io_req_bits_rs1_data_0[64:60]; // @[FPU.scala:332:49] wire req_in1_prev_isbox = &_req_in1_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire req_in1_oks_0 = req_in1_prev_isbox; // @[FPU.scala:332:84, :362:32] wire [1:0] _req_in1_truncIdx_T; // @[package.scala:38:21] wire req_in1_truncIdx = _req_in1_truncIdx_T[0]; // @[package.scala:38:{21,47}] wire _req_in1_T = req_in1_truncIdx; // @[package.scala:38:47, :39:86] wire _req_in1_T_1 = _req_in1_T | req_in1_oks_0; // @[package.scala:39:{76,86}] wire [1:0] _req_in1_truncIdx_T_1; // @[package.scala:38:21] wire req_in1_truncIdx_1 = _req_in1_truncIdx_T_1[0]; // @[package.scala:38:{21,47}] wire _req_in1_T_2 = req_in1_truncIdx_1; // @[package.scala:38:47, :39:86] wire [64:0] _req_in1_T_3 = _req_in1_T_2 ? io_req_bits_rs1_data_0 : req_in1_floats_0; // @[package.scala:39:{76,86}] assign _req_in1_T_4 = _req_in1_T_1 ? _req_in1_T_3 : 65'hE008000000000000; // @[package.scala:39:76] assign req_in1 = _req_in1_T_4; // @[FPU.scala:369:10] wire _req_in2_prev_unswizzled_T = io_req_bits_rs2_data_0[31]; // @[FPU.scala:357:14] wire _req_in2_prev_unswizzled_T_1 = io_req_bits_rs2_data_0[52]; // @[FPU.scala:358:14] wire [30:0] _req_in2_prev_unswizzled_T_2 = io_req_bits_rs2_data_0[30:0]; // @[FPU.scala:359:14] wire [1:0] req_in2_prev_unswizzled_hi = {_req_in2_prev_unswizzled_T, _req_in2_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] req_in2_prev_unswizzled = {req_in2_prev_unswizzled_hi, _req_in2_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire req_in2_prev_prev_sign = req_in2_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31] wire [22:0] req_in2_prev_prev_fractIn = req_in2_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31] wire [8:0] req_in2_prev_prev_expIn = req_in2_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31] wire [75:0] _req_in2_prev_prev_fractOut_T = {req_in2_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] req_in2_prev_prev_fractOut = _req_in2_prev_prev_fractOut_T[75:24]; // @[FPU.scala:277:{28,38}] wire [2:0] req_in2_prev_prev_expOut_expCode = req_in2_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26] wire [12:0] _req_in2_prev_prev_expOut_commonCase_T = {4'h0, req_in2_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _req_in2_prev_prev_expOut_commonCase_T_1 = _req_in2_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _req_in2_prev_prev_expOut_commonCase_T_2 = {1'h0, _req_in2_prev_prev_expOut_commonCase_T_1} - 13'h100; // @[FPU.scala:280:{31,50}] wire [11:0] req_in2_prev_prev_expOut_commonCase = _req_in2_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _req_in2_prev_prev_expOut_T_5 = req_in2_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _req_in2_prev_prev_expOut_T = req_in2_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _req_in2_prev_prev_expOut_T_1 = req_in2_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _req_in2_prev_prev_expOut_T_2 = _req_in2_prev_prev_expOut_T | _req_in2_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _req_in2_prev_prev_expOut_T_3 = req_in2_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _req_in2_prev_prev_expOut_T_4 = {req_in2_prev_prev_expOut_expCode, _req_in2_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] req_in2_prev_prev_expOut = _req_in2_prev_prev_expOut_T_2 ? _req_in2_prev_prev_expOut_T_4 : _req_in2_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] req_in2_prev_prev_hi = {req_in2_prev_prev_sign, req_in2_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] req_in2_floats_0 = {req_in2_prev_prev_hi, req_in2_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire [4:0] _req_in2_prev_isbox_T = io_req_bits_rs2_data_0[64:60]; // @[FPU.scala:332:49] wire req_in2_prev_isbox = &_req_in2_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire req_in2_oks_0 = req_in2_prev_isbox; // @[FPU.scala:332:84, :362:32] wire [1:0] _req_in2_truncIdx_T; // @[package.scala:38:21] wire req_in2_truncIdx = _req_in2_truncIdx_T[0]; // @[package.scala:38:{21,47}] wire _req_in2_T = req_in2_truncIdx; // @[package.scala:38:47, :39:86] wire _req_in2_T_1 = _req_in2_T | req_in2_oks_0; // @[package.scala:39:{76,86}] wire [1:0] _req_in2_truncIdx_T_1; // @[package.scala:38:21] wire req_in2_truncIdx_1 = _req_in2_truncIdx_T_1[0]; // @[package.scala:38:{21,47}] wire _req_in2_T_2 = req_in2_truncIdx_1; // @[package.scala:38:47, :39:86] wire [64:0] _req_in2_T_3 = _req_in2_T_2 ? io_req_bits_rs2_data_0 : req_in2_floats_0; // @[package.scala:39:{76,86}] assign _req_in2_T_4 = _req_in2_T_1 ? _req_in2_T_3 : 65'hE008000000000000; // @[package.scala:39:76] assign req_in2 = _req_in2_T_4; // @[FPU.scala:369:10] assign _req_typ_T = io_req_bits_uop_imm_packed_0[9:8]; // @[util.scala:295:59] assign req_typ = _req_typ_T; // @[util.scala:295:59]

Generate the Verilog code corresponding to the following Chisel files. File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Metadata.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.constants.MemoryOpConstants import freechips.rocketchip.util._ object ClientStates { val width = 2 def Nothing = 0.U(width.W) def Branch = 1.U(width.W) def Trunk = 2.U(width.W) def Dirty = 3.U(width.W) def hasReadPermission(state: UInt): Bool = state > Nothing def hasWritePermission(state: UInt): Bool = state > Branch } object MemoryOpCategories extends MemoryOpConstants { def wr = Cat(true.B, true.B) // Op actually writes def wi = Cat(false.B, true.B) // Future op will write def rd = Cat(false.B, false.B) // Op only reads def categorize(cmd: UInt): UInt = { val cat = Cat(isWrite(cmd), isWriteIntent(cmd)) //assert(cat.isOneOf(wr,wi,rd), "Could not categorize command.") cat } } /** Stores the client-side coherence information, * such as permissions on the data and whether the data is dirty. * Its API can be used to make TileLink messages in response to * memory operations, cache control oeprations, or Probe messages. */ class ClientMetadata extends Bundle { /** Actual state information stored in this bundle */ val state = UInt(ClientStates.width.W) /** Metadata equality */ def ===(rhs: UInt): Bool = state === rhs def ===(rhs: ClientMetadata): Bool = state === rhs.state def =/=(rhs: ClientMetadata): Bool = !this.===(rhs) /** Is the block's data present in this cache */ def isValid(dummy: Int = 0): Bool = state > ClientStates.Nothing /** Determine whether this cmd misses, and the new state (on hit) or param to be sent (on miss) */ private def growStarter(cmd: UInt): (Bool, UInt) = { import MemoryOpCategories._ import TLPermissions._ import ClientStates._ val c = categorize(cmd) MuxTLookup(Cat(c, state), (false.B, 0.U), Seq( //(effect, am now) -> (was a hit, next) Cat(rd, Dirty) -> (true.B, Dirty), Cat(rd, Trunk) -> (true.B, Trunk), Cat(rd, Branch) -> (true.B, Branch), Cat(wi, Dirty) -> (true.B, Dirty), Cat(wi, Trunk) -> (true.B, Trunk), Cat(wr, Dirty) -> (true.B, Dirty), Cat(wr, Trunk) -> (true.B, Dirty), //(effect, am now) -> (was a miss, param) Cat(rd, Nothing) -> (false.B, NtoB), Cat(wi, Branch) -> (false.B, BtoT), Cat(wi, Nothing) -> (false.B, NtoT), Cat(wr, Branch) -> (false.B, BtoT), Cat(wr, Nothing) -> (false.B, NtoT))) } /** Determine what state to go to after miss based on Grant param * For now, doesn't depend on state (which may have been Probed). */ private def growFinisher(cmd: UInt, param: UInt): UInt = { import MemoryOpCategories._ import TLPermissions._ import ClientStates._ val c = categorize(cmd) //assert(c === rd || param === toT, "Client was expecting trunk permissions.") MuxLookup(Cat(c, param), Nothing)(Seq( //(effect param) -> (next) Cat(rd, toB) -> Branch, Cat(rd, toT) -> Trunk, Cat(wi, toT) -> Trunk, Cat(wr, toT) -> Dirty)) } /** Does this cache have permissions on this block sufficient to perform op, * and what to do next (Acquire message param or updated metadata). */ def onAccess(cmd: UInt): (Bool, UInt, ClientMetadata) = { val r = growStarter(cmd) (r._1, r._2, ClientMetadata(r._2)) } /** Does a secondary miss on the block require another Acquire message */ def onSecondaryAccess(first_cmd: UInt, second_cmd: UInt): (Bool, Bool, UInt, ClientMetadata, UInt) = { import MemoryOpCategories._ val r1 = growStarter(first_cmd) val r2 = growStarter(second_cmd) val needs_second_acq = isWriteIntent(second_cmd) && !isWriteIntent(first_cmd) val hit_again = r1._1 && r2._1 val dirties = categorize(second_cmd) === wr val biggest_grow_param = Mux(dirties, r2._2, r1._2) val dirtiest_state = ClientMetadata(biggest_grow_param) val dirtiest_cmd = Mux(dirties, second_cmd, first_cmd) (needs_second_acq, hit_again, biggest_grow_param, dirtiest_state, dirtiest_cmd) } /** Metadata change on a returned Grant */ def onGrant(cmd: UInt, param: UInt): ClientMetadata = ClientMetadata(growFinisher(cmd, param)) /** Determine what state to go to based on Probe param */ private def shrinkHelper(param: UInt): (Bool, UInt, UInt) = { import ClientStates._ import TLPermissions._ MuxTLookup(Cat(param, state), (false.B, 0.U, 0.U), Seq( //(wanted, am now) -> (hasDirtyData resp, next) Cat(toT, Dirty) -> (true.B, TtoT, Trunk), Cat(toT, Trunk) -> (false.B, TtoT, Trunk), Cat(toT, Branch) -> (false.B, BtoB, Branch), Cat(toT, Nothing) -> (false.B, NtoN, Nothing), Cat(toB, Dirty) -> (true.B, TtoB, Branch), Cat(toB, Trunk) -> (false.B, TtoB, Branch), // Policy: Don't notify on clean downgrade Cat(toB, Branch) -> (false.B, BtoB, Branch), Cat(toB, Nothing) -> (false.B, NtoN, Nothing), Cat(toN, Dirty) -> (true.B, TtoN, Nothing), Cat(toN, Trunk) -> (false.B, TtoN, Nothing), // Policy: Don't notify on clean downgrade Cat(toN, Branch) -> (false.B, BtoN, Nothing), // Policy: Don't notify on clean downgrade Cat(toN, Nothing) -> (false.B, NtoN, Nothing))) } /** Translate cache control cmds into Probe param */ private def cmdToPermCap(cmd: UInt): UInt = { import MemoryOpCategories._ import TLPermissions._ MuxLookup(cmd, toN)(Seq( M_FLUSH -> toN, M_PRODUCE -> toB, M_CLEAN -> toT)) } def onCacheControl(cmd: UInt): (Bool, UInt, ClientMetadata) = { val r = shrinkHelper(cmdToPermCap(cmd)) (r._1, r._2, ClientMetadata(r._3)) } def onProbe(param: UInt): (Bool, UInt, ClientMetadata) = { val r = shrinkHelper(param) (r._1, r._2, ClientMetadata(r._3)) } } /** Factories for ClientMetadata, including on reset */ object ClientMetadata { def apply(perm: UInt) = { val meta = Wire(new ClientMetadata) meta.state := perm meta } def onReset = ClientMetadata(ClientStates.Nothing) def maximum = ClientMetadata(ClientStates.Dirty) } File Replacement.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import freechips.rocketchip.util.property.cover abstract class ReplacementPolicy { def nBits: Int def perSet: Boolean def way: UInt def miss: Unit def hit: Unit def access(touch_way: UInt): Unit def access(touch_ways: Seq[Valid[UInt]]): Unit def state_read: UInt def get_next_state(state: UInt, touch_way: UInt): UInt def get_next_state(state: UInt, touch_ways: Seq[Valid[UInt]]): UInt = { touch_ways.foldLeft(state)((prev, touch_way) => Mux(touch_way.valid, get_next_state(prev, touch_way.bits), prev)) } def get_replace_way(state: UInt): UInt } object ReplacementPolicy { def fromString(s: String, n_ways: Int): ReplacementPolicy = s.toLowerCase match { case "random" => new RandomReplacement(n_ways) case "lru" => new TrueLRU(n_ways) case "plru" => new PseudoLRU(n_ways) case t => throw new IllegalArgumentException(s"unknown Replacement Policy type $t") } } class RandomReplacement(n_ways: Int) extends ReplacementPolicy { private val replace = Wire(Bool()) replace := false.B def nBits = 16 def perSet = false private val lfsr = LFSR(nBits, replace) def state_read = WireDefault(lfsr) def way = Random(n_ways, lfsr) def miss = replace := true.B def hit = {} def access(touch_way: UInt) = {} def access(touch_ways: Seq[Valid[UInt]]) = {} def get_next_state(state: UInt, touch_way: UInt) = 0.U //DontCare def get_replace_way(state: UInt) = way } abstract class SeqReplacementPolicy { def access(set: UInt): Unit def update(valid: Bool, hit: Bool, set: UInt, way: UInt): Unit def way: UInt } abstract class SetAssocReplacementPolicy { def access(set: UInt, touch_way: UInt): Unit def access(sets: Seq[UInt], touch_ways: Seq[Valid[UInt]]): Unit def way(set: UInt): UInt } class SeqRandom(n_ways: Int) extends SeqReplacementPolicy { val logic = new RandomReplacement(n_ways) def access(set: UInt) = { } def update(valid: Bool, hit: Bool, set: UInt, way: UInt) = { when (valid && !hit) { logic.miss } } def way = logic.way } class TrueLRU(n_ways: Int) extends ReplacementPolicy { // True LRU replacement policy, using a triangular matrix to track which sets are more recently used than others. // The matrix is packed into a single UInt (or Bits). Example 4-way (6-bits): // [5] - 3 more recent than 2 // [4] - 3 more recent than 1 // [3] - 2 more recent than 1 // [2] - 3 more recent than 0 // [1] - 2 more recent than 0 // [0] - 1 more recent than 0 def nBits = (n_ways * (n_ways-1)) / 2 def perSet = true private val state_reg = RegInit(0.U(nBits.W)) def state_read = WireDefault(state_reg) private def extractMRUVec(state: UInt): Seq[UInt] = { // Extract per-way information about which higher-indexed ways are more recently used val moreRecentVec = Wire(Vec(n_ways-1, UInt(n_ways.W))) var lsb = 0 for (i <- 0 until n_ways-1) { moreRecentVec(i) := Cat(state(lsb+n_ways-i-2,lsb), 0.U((i+1).W)) lsb = lsb + (n_ways - i - 1) } moreRecentVec } def get_next_state(state: UInt, touch_way: UInt): UInt = { val nextState = Wire(Vec(n_ways-1, UInt(n_ways.W))) val moreRecentVec = extractMRUVec(state) // reconstruct lower triangular matrix val wayDec = UIntToOH(touch_way, n_ways) // Compute next value of triangular matrix // set the touched way as more recent than every other way nextState.zipWithIndex.map { case (e, i) => e := Mux(i.U === touch_way, 0.U(n_ways.W), moreRecentVec(i) | wayDec) } nextState.zipWithIndex.tail.foldLeft((nextState.head.apply(n_ways-1,1),0)) { case ((pe,pi),(ce,ci)) => (Cat(ce.apply(n_ways-1,ci+1), pe), ci) }._1 } def access(touch_way: UInt): Unit = { state_reg := get_next_state(state_reg, touch_way) } def access(touch_ways: Seq[Valid[UInt]]): Unit = { when (touch_ways.map(_.valid).orR) { state_reg := get_next_state(state_reg, touch_ways) } for (i <- 1 until touch_ways.size) { cover(PopCount(touch_ways.map(_.valid)) === i.U, s"LRU_UpdateCount$i", s"LRU Update $i simultaneous") } } def get_replace_way(state: UInt): UInt = { val moreRecentVec = extractMRUVec(state) // reconstruct lower triangular matrix // For each way, determine if all other ways are more recent val mruWayDec = (0 until n_ways).map { i => val upperMoreRecent = (if (i == n_ways-1) true.B else moreRecentVec(i).apply(n_ways-1,i+1).andR) val lowerMoreRecent = (if (i == 0) true.B else moreRecentVec.map(e => !e(i)).reduce(_ && _)) upperMoreRecent && lowerMoreRecent } OHToUInt(mruWayDec) } def way = get_replace_way(state_reg) def miss = access(way) def hit = {} @deprecated("replace 'replace' with 'way' from abstract class ReplacementPolicy","Rocket Chip 2020.05") def replace: UInt = way } class PseudoLRU(n_ways: Int) extends ReplacementPolicy { // Pseudo-LRU tree algorithm: https://en.wikipedia.org/wiki/Pseudo-LRU#Tree-PLRU // // // - bits storage example for 4-way PLRU binary tree: // bit[2]: ways 3+2 older than ways 1+0 // / \ // bit[1]: way 3 older than way 2 bit[0]: way 1 older than way 0 // // // - bits storage example for 3-way PLRU binary tree: // bit[1]: way 2 older than ways 1+0 // \ // bit[0]: way 1 older than way 0 // // // - bits storage example for 8-way PLRU binary tree: // bit[6]: ways 7-4 older than ways 3-0 // / \ // bit[5]: ways 7+6 > 5+4 bit[2]: ways 3+2 > 1+0 // / \ / \ // bit[4]: way 7>6 bit[3]: way 5>4 bit[1]: way 3>2 bit[0]: way 1>0 def nBits = n_ways - 1 def perSet = true private val state_reg = if (nBits == 0) Reg(UInt(0.W)) else RegInit(0.U(nBits.W)) def state_read = WireDefault(state_reg) def access(touch_way: UInt): Unit = { state_reg := get_next_state(state_reg, touch_way) } def access(touch_ways: Seq[Valid[UInt]]): Unit = { when (touch_ways.map(_.valid).orR) { state_reg := get_next_state(state_reg, touch_ways) } for (i <- 1 until touch_ways.size) { cover(PopCount(touch_ways.map(_.valid)) === i.U, s"PLRU_UpdateCount$i", s"PLRU Update $i simultaneous") } } /** @param state state_reg bits for this sub-tree * @param touch_way touched way encoded value bits for this sub-tree * @param tree_nways number of ways in this sub-tree */ def get_next_state(state: UInt, touch_way: UInt, tree_nways: Int): UInt = { require(state.getWidth == (tree_nways-1), s"wrong state bits width ${state.getWidth} for $tree_nways ways") require(touch_way.getWidth == (log2Ceil(tree_nways) max 1), s"wrong encoded way width ${touch_way.getWidth} for $tree_nways ways") if (tree_nways > 2) { // we are at a branching node in the tree, so recurse val right_nways: Int = 1 << (log2Ceil(tree_nways) - 1) // number of ways in the right sub-tree val left_nways: Int = tree_nways - right_nways // number of ways in the left sub-tree val set_left_older = !touch_way(log2Ceil(tree_nways)-1) val left_subtree_state = state.extract(tree_nways-3, right_nways-1) val right_subtree_state = state(right_nways-2, 0) if (left_nways > 1) { // we are at a branching node in the tree with both left and right sub-trees, so recurse both sub-trees Cat(set_left_older, Mux(set_left_older, left_subtree_state, // if setting left sub-tree as older, do NOT recurse into left sub-tree get_next_state(left_subtree_state, touch_way.extract(log2Ceil(left_nways)-1,0), left_nways)), // recurse left if newer Mux(set_left_older, get_next_state(right_subtree_state, touch_way(log2Ceil(right_nways)-1,0), right_nways), // recurse right if newer right_subtree_state)) // if setting right sub-tree as older, do NOT recurse into right sub-tree } else { // we are at a branching node in the tree with only a right sub-tree, so recurse only right sub-tree Cat(set_left_older, Mux(set_left_older, get_next_state(right_subtree_state, touch_way(log2Ceil(right_nways)-1,0), right_nways), // recurse right if newer right_subtree_state)) // if setting right sub-tree as older, do NOT recurse into right sub-tree } } else if (tree_nways == 2) { // we are at a leaf node at the end of the tree, so set the single state bit opposite of the lsb of the touched way encoded value !touch_way(0) } else { // tree_nways <= 1 // we are at an empty node in an empty tree for 1 way, so return single zero bit for Chisel (no zero-width wires) 0.U(1.W) } } def get_next_state(state: UInt, touch_way: UInt): UInt = { val touch_way_sized = if (touch_way.getWidth < log2Ceil(n_ways)) touch_way.padTo (log2Ceil(n_ways)) else touch_way.extract(log2Ceil(n_ways)-1,0) get_next_state(state, touch_way_sized, n_ways) } /** @param state state_reg bits for this sub-tree * @param tree_nways number of ways in this sub-tree */ def get_replace_way(state: UInt, tree_nways: Int): UInt = { require(state.getWidth == (tree_nways-1), s"wrong state bits width ${state.getWidth} for $tree_nways ways") // this algorithm recursively descends the binary tree, filling in the way-to-replace encoded value from msb to lsb if (tree_nways > 2) { // we are at a branching node in the tree, so recurse val right_nways: Int = 1 << (log2Ceil(tree_nways) - 1) // number of ways in the right sub-tree val left_nways: Int = tree_nways - right_nways // number of ways in the left sub-tree val left_subtree_older = state(tree_nways-2) val left_subtree_state = state.extract(tree_nways-3, right_nways-1) val right_subtree_state = state(right_nways-2, 0) if (left_nways > 1) { // we are at a branching node in the tree with both left and right sub-trees, so recurse both sub-trees Cat(left_subtree_older, // return the top state bit (current tree node) as msb of the way-to-replace encoded value Mux(left_subtree_older, // if left sub-tree is older, recurse left, else recurse right get_replace_way(left_subtree_state, left_nways), // recurse left get_replace_way(right_subtree_state, right_nways))) // recurse right } else { // we are at a branching node in the tree with only a right sub-tree, so recurse only right sub-tree Cat(left_subtree_older, // return the top state bit (current tree node) as msb of the way-to-replace encoded value Mux(left_subtree_older, // if left sub-tree is older, return and do not recurse right 0.U(1.W), get_replace_way(right_subtree_state, right_nways))) // recurse right } } else if (tree_nways == 2) { // we are at a leaf node at the end of the tree, so just return the single state bit as lsb of the way-to-replace encoded value state(0) } else { // tree_nways <= 1 // we are at an empty node in an unbalanced tree for non-power-of-2 ways, so return single zero bit as lsb of the way-to-replace encoded value 0.U(1.W) } } def get_replace_way(state: UInt): UInt = get_replace_way(state, n_ways) def way = get_replace_way(state_reg) def miss = access(way) def hit = {} } class SeqPLRU(n_sets: Int, n_ways: Int) extends SeqReplacementPolicy { val logic = new PseudoLRU(n_ways) val state = SyncReadMem(n_sets, UInt(logic.nBits.W)) val current_state = Wire(UInt(logic.nBits.W)) val next_state = Wire(UInt(logic.nBits.W)) val plru_way = logic.get_replace_way(current_state) def access(set: UInt) = { current_state := state.read(set) } def update(valid: Bool, hit: Bool, set: UInt, way: UInt) = { val update_way = Mux(hit, way, plru_way) next_state := logic.get_next_state(current_state, update_way) when (valid) { state.write(set, next_state) } } def way = plru_way } class SetAssocLRU(n_sets: Int, n_ways: Int, policy: String) extends SetAssocReplacementPolicy { val logic = policy.toLowerCase match { case "plru" => new PseudoLRU(n_ways) case "lru" => new TrueLRU(n_ways) case t => throw new IllegalArgumentException(s"unknown Replacement Policy type $t") } val state_vec = if (logic.nBits == 0) Reg(Vec(n_sets, UInt(logic.nBits.W))) // Work around elaboration error on following line else RegInit(VecInit(Seq.fill(n_sets)(0.U(logic.nBits.W)))) def access(set: UInt, touch_way: UInt) = { state_vec(set) := logic.get_next_state(state_vec(set), touch_way) } def access(sets: Seq[UInt], touch_ways: Seq[Valid[UInt]]) = { require(sets.size == touch_ways.size, "internal consistency check: should be same number of simultaneous updates for sets and touch_ways") for (set <- 0 until n_sets) { val set_touch_ways = (sets zip touch_ways).map { case (touch_set, touch_way) => Pipe(touch_way.valid && (touch_set === set.U), touch_way.bits, 0)} when (set_touch_ways.map(_.valid).orR) { state_vec(set) := logic.get_next_state(state_vec(set), set_touch_ways) } } } def way(set: UInt) = logic.get_replace_way(state_vec(set)) } // Synthesizable unit tests import freechips.rocketchip.unittest._ class PLRUTest(n_ways: Int, timeout: Int = 500) extends UnitTest(timeout) { val plru = new PseudoLRU(n_ways) // step io.finished := RegNext(true.B, false.B) val get_replace_ways = (0 until (1 << (n_ways-1))).map(state => plru.get_replace_way(state = state.U((n_ways-1).W))) val get_next_states = (0 until (1 << (n_ways-1))).map(state => (0 until n_ways).map(way => plru.get_next_state (state = state.U((n_ways-1).W), touch_way = way.U(log2Ceil(n_ways).W)))) n_ways match { case 2 => { assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0)) assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1)) assert(get_next_states(0)(0) === 1.U(plru.nBits.W), s"get_next_state state=0 way=0: expected=1 actual=%d", get_next_states(0)(0)) assert(get_next_states(0)(1) === 0.U(plru.nBits.W), s"get_next_state state=0 way=1: expected=0 actual=%d", get_next_states(0)(1)) assert(get_next_states(1)(0) === 1.U(plru.nBits.W), s"get_next_state state=1 way=0: expected=1 actual=%d", get_next_states(1)(0)) assert(get_next_states(1)(1) === 0.U(plru.nBits.W), s"get_next_state state=1 way=1: expected=0 actual=%d", get_next_states(1)(1)) } case 3 => { assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0)) assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1)) assert(get_replace_ways(2) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=2: expected=2 actual=%d", get_replace_ways(2)) assert(get_replace_ways(3) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=3: expected=2 actual=%d", get_replace_ways(3)) assert(get_next_states(0)(0) === 3.U(plru.nBits.W), s"get_next_state state=0 way=0: expected=3 actual=%d", get_next_states(0)(0)) assert(get_next_states(0)(1) === 2.U(plru.nBits.W), s"get_next_state state=0 way=1: expected=2 actual=%d", get_next_states(0)(1)) assert(get_next_states(0)(2) === 0.U(plru.nBits.W), s"get_next_state state=0 way=2: expected=0 actual=%d", get_next_states(0)(2)) assert(get_next_states(1)(0) === 3.U(plru.nBits.W), s"get_next_state state=1 way=0: expected=3 actual=%d", get_next_states(1)(0)) assert(get_next_states(1)(1) === 2.U(plru.nBits.W), s"get_next_state state=1 way=1: expected=2 actual=%d", get_next_states(1)(1)) assert(get_next_states(1)(2) === 1.U(plru.nBits.W), s"get_next_state state=1 way=2: expected=1 actual=%d", get_next_states(1)(2)) assert(get_next_states(2)(0) === 3.U(plru.nBits.W), s"get_next_state state=2 way=0: expected=3 actual=%d", get_next_states(2)(0)) assert(get_next_states(2)(1) === 2.U(plru.nBits.W), s"get_next_state state=2 way=1: expected=2 actual=%d", get_next_states(2)(1)) assert(get_next_states(2)(2) === 0.U(plru.nBits.W), s"get_next_state state=2 way=2: expected=0 actual=%d", get_next_states(2)(2)) assert(get_next_states(3)(0) === 3.U(plru.nBits.W), s"get_next_state state=3 way=0: expected=3 actual=%d", get_next_states(3)(0)) assert(get_next_states(3)(1) === 2.U(plru.nBits.W), s"get_next_state state=3 way=1: expected=2 actual=%d", get_next_states(3)(1)) assert(get_next_states(3)(2) === 1.U(plru.nBits.W), s"get_next_state state=3 way=2: expected=1 actual=%d", get_next_states(3)(2)) } case 4 => { assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0)) assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1)) assert(get_replace_ways(2) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=2: expected=0 actual=%d", get_replace_ways(2)) assert(get_replace_ways(3) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=3: expected=1 actual=%d", get_replace_ways(3)) assert(get_replace_ways(4) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=4: expected=2 actual=%d", get_replace_ways(4)) assert(get_replace_ways(5) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=5: expected=2 actual=%d", get_replace_ways(5)) assert(get_replace_ways(6) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=6: expected=3 actual=%d", get_replace_ways(6)) assert(get_replace_ways(7) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=7: expected=3 actual=%d", get_replace_ways(7)) assert(get_next_states(0)(0) === 5.U(plru.nBits.W), s"get_next_state state=0 way=0: expected=5 actual=%d", get_next_states(0)(0)) assert(get_next_states(0)(1) === 4.U(plru.nBits.W), s"get_next_state state=0 way=1: expected=4 actual=%d", get_next_states(0)(1)) assert(get_next_states(0)(2) === 2.U(plru.nBits.W), s"get_next_state state=0 way=2: expected=2 actual=%d", get_next_states(0)(2)) assert(get_next_states(0)(3) === 0.U(plru.nBits.W), s"get_next_state state=0 way=3: expected=0 actual=%d", get_next_states(0)(3)) assert(get_next_states(1)(0) === 5.U(plru.nBits.W), s"get_next_state state=1 way=0: expected=5 actual=%d", get_next_states(1)(0)) assert(get_next_states(1)(1) === 4.U(plru.nBits.W), s"get_next_state state=1 way=1: expected=4 actual=%d", get_next_states(1)(1)) assert(get_next_states(1)(2) === 3.U(plru.nBits.W), s"get_next_state state=1 way=2: expected=3 actual=%d", get_next_states(1)(2)) assert(get_next_states(1)(3) === 1.U(plru.nBits.W), s"get_next_state state=1 way=3: expected=1 actual=%d", get_next_states(1)(3)) assert(get_next_states(2)(0) === 7.U(plru.nBits.W), s"get_next_state state=2 way=0: expected=7 actual=%d", get_next_states(2)(0)) assert(get_next_states(2)(1) === 6.U(plru.nBits.W), s"get_next_state state=2 way=1: expected=6 actual=%d", get_next_states(2)(1)) assert(get_next_states(2)(2) === 2.U(plru.nBits.W), s"get_next_state state=2 way=2: expected=2 actual=%d", get_next_states(2)(2)) assert(get_next_states(2)(3) === 0.U(plru.nBits.W), s"get_next_state state=2 way=3: expected=0 actual=%d", get_next_states(2)(3)) assert(get_next_states(3)(0) === 7.U(plru.nBits.W), s"get_next_state state=3 way=0: expected=7 actual=%d", get_next_states(3)(0)) assert(get_next_states(3)(1) === 6.U(plru.nBits.W), s"get_next_state state=3 way=1: expected=6 actual=%d", get_next_states(3)(1)) assert(get_next_states(3)(2) === 3.U(plru.nBits.W), s"get_next_state state=3 way=2: expected=3 actual=%d", get_next_states(3)(2)) assert(get_next_states(3)(3) === 1.U(plru.nBits.W), s"get_next_state state=3 way=3: expected=1 actual=%d", get_next_states(3)(3)) assert(get_next_states(4)(0) === 5.U(plru.nBits.W), s"get_next_state state=4 way=0: expected=5 actual=%d", get_next_states(4)(0)) assert(get_next_states(4)(1) === 4.U(plru.nBits.W), s"get_next_state state=4 way=1: expected=4 actual=%d", get_next_states(4)(1)) assert(get_next_states(4)(2) === 2.U(plru.nBits.W), s"get_next_state state=4 way=2: expected=2 actual=%d", get_next_states(4)(2)) assert(get_next_states(4)(3) === 0.U(plru.nBits.W), s"get_next_state state=4 way=3: expected=0 actual=%d", get_next_states(4)(3)) assert(get_next_states(5)(0) === 5.U(plru.nBits.W), s"get_next_state state=5 way=0: expected=5 actual=%d", get_next_states(5)(0)) assert(get_next_states(5)(1) === 4.U(plru.nBits.W), s"get_next_state state=5 way=1: expected=4 actual=%d", get_next_states(5)(1)) assert(get_next_states(5)(2) === 3.U(plru.nBits.W), s"get_next_state state=5 way=2: expected=3 actual=%d", get_next_states(5)(2)) assert(get_next_states(5)(3) === 1.U(plru.nBits.W), s"get_next_state state=5 way=3: expected=1 actual=%d", get_next_states(5)(3)) assert(get_next_states(6)(0) === 7.U(plru.nBits.W), s"get_next_state state=6 way=0: expected=7 actual=%d", get_next_states(6)(0)) assert(get_next_states(6)(1) === 6.U(plru.nBits.W), s"get_next_state state=6 way=1: expected=6 actual=%d", get_next_states(6)(1)) assert(get_next_states(6)(2) === 2.U(plru.nBits.W), s"get_next_state state=6 way=2: expected=2 actual=%d", get_next_states(6)(2)) assert(get_next_states(6)(3) === 0.U(plru.nBits.W), s"get_next_state state=6 way=3: expected=0 actual=%d", get_next_states(6)(3)) assert(get_next_states(7)(0) === 7.U(plru.nBits.W), s"get_next_state state=7 way=0: expected=7 actual=%d", get_next_states(7)(0)) assert(get_next_states(7)(1) === 6.U(plru.nBits.W), s"get_next_state state=7 way=5: expected=6 actual=%d", get_next_states(7)(1)) assert(get_next_states(7)(2) === 3.U(plru.nBits.W), s"get_next_state state=7 way=2: expected=3 actual=%d", get_next_states(7)(2)) assert(get_next_states(7)(3) === 1.U(plru.nBits.W), s"get_next_state state=7 way=3: expected=1 actual=%d", get_next_states(7)(3)) } case 5 => { assert(get_replace_ways( 0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=00: expected=0 actual=%d", get_replace_ways( 0)) assert(get_replace_ways( 1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=01: expected=1 actual=%d", get_replace_ways( 1)) assert(get_replace_ways( 2) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=02: expected=0 actual=%d", get_replace_ways( 2)) assert(get_replace_ways( 3) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=03: expected=1 actual=%d", get_replace_ways( 3)) assert(get_replace_ways( 4) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=04: expected=2 actual=%d", get_replace_ways( 4)) assert(get_replace_ways( 5) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=05: expected=2 actual=%d", get_replace_ways( 5)) assert(get_replace_ways( 6) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=06: expected=3 actual=%d", get_replace_ways( 6)) assert(get_replace_ways( 7) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=07: expected=3 actual=%d", get_replace_ways( 7)) assert(get_replace_ways( 8) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=08: expected=4 actual=%d", get_replace_ways( 8)) assert(get_replace_ways( 9) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=09: expected=4 actual=%d", get_replace_ways( 9)) assert(get_replace_ways(10) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=10: expected=4 actual=%d", get_replace_ways(10)) assert(get_replace_ways(11) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=11: expected=4 actual=%d", get_replace_ways(11)) assert(get_replace_ways(12) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=12: expected=4 actual=%d", get_replace_ways(12)) assert(get_replace_ways(13) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=13: expected=4 actual=%d", get_replace_ways(13)) assert(get_replace_ways(14) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=14: expected=4 actual=%d", get_replace_ways(14)) assert(get_replace_ways(15) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=15: expected=4 actual=%d", get_replace_ways(15)) assert(get_next_states( 0)(0) === 13.U(plru.nBits.W), s"get_next_state state=00 way=0: expected=13 actual=%d", get_next_states( 0)(0)) assert(get_next_states( 0)(1) === 12.U(plru.nBits.W), s"get_next_state state=00 way=1: expected=12 actual=%d", get_next_states( 0)(1)) assert(get_next_states( 0)(2) === 10.U(plru.nBits.W), s"get_next_state state=00 way=2: expected=10 actual=%d", get_next_states( 0)(2)) assert(get_next_states( 0)(3) === 8.U(plru.nBits.W), s"get_next_state state=00 way=3: expected=08 actual=%d", get_next_states( 0)(3)) assert(get_next_states( 0)(4) === 0.U(plru.nBits.W), s"get_next_state state=00 way=4: expected=00 actual=%d", get_next_states( 0)(4)) assert(get_next_states( 1)(0) === 13.U(plru.nBits.W), s"get_next_state state=01 way=0: expected=13 actual=%d", get_next_states( 1)(0)) assert(get_next_states( 1)(1) === 12.U(plru.nBits.W), s"get_next_state state=01 way=1: expected=12 actual=%d", get_next_states( 1)(1)) assert(get_next_states( 1)(2) === 11.U(plru.nBits.W), s"get_next_state state=01 way=2: expected=11 actual=%d", get_next_states( 1)(2)) assert(get_next_states( 1)(3) === 9.U(plru.nBits.W), s"get_next_state state=01 way=3: expected=09 actual=%d", get_next_states( 1)(3)) assert(get_next_states( 1)(4) === 1.U(plru.nBits.W), s"get_next_state state=01 way=4: expected=01 actual=%d", get_next_states( 1)(4)) assert(get_next_states( 2)(0) === 15.U(plru.nBits.W), s"get_next_state state=02 way=0: expected=15 actual=%d", get_next_states( 2)(0)) assert(get_next_states( 2)(1) === 14.U(plru.nBits.W), s"get_next_state state=02 way=1: expected=14 actual=%d", get_next_states( 2)(1)) assert(get_next_states( 2)(2) === 10.U(plru.nBits.W), s"get_next_state state=02 way=2: expected=10 actual=%d", get_next_states( 2)(2)) assert(get_next_states( 2)(3) === 8.U(plru.nBits.W), s"get_next_state state=02 way=3: expected=08 actual=%d", get_next_states( 2)(3)) assert(get_next_states( 2)(4) === 2.U(plru.nBits.W), s"get_next_state state=02 way=4: expected=02 actual=%d", get_next_states( 2)(4)) assert(get_next_states( 3)(0) === 15.U(plru.nBits.W), s"get_next_state state=03 way=0: expected=15 actual=%d", get_next_states( 3)(0)) assert(get_next_states( 3)(1) === 14.U(plru.nBits.W), s"get_next_state state=03 way=1: expected=14 actual=%d", get_next_states( 3)(1)) assert(get_next_states( 3)(2) === 11.U(plru.nBits.W), s"get_next_state state=03 way=2: expected=11 actual=%d", get_next_states( 3)(2)) assert(get_next_states( 3)(3) === 9.U(plru.nBits.W), s"get_next_state state=03 way=3: expected=09 actual=%d", get_next_states( 3)(3)) assert(get_next_states( 3)(4) === 3.U(plru.nBits.W), s"get_next_state state=03 way=4: expected=03 actual=%d", get_next_states( 3)(4)) assert(get_next_states( 4)(0) === 13.U(plru.nBits.W), s"get_next_state state=04 way=0: expected=13 actual=%d", get_next_states( 4)(0)) assert(get_next_states( 4)(1) === 12.U(plru.nBits.W), s"get_next_state state=04 way=1: expected=12 actual=%d", get_next_states( 4)(1)) assert(get_next_states( 4)(2) === 10.U(plru.nBits.W), s"get_next_state state=04 way=2: expected=10 actual=%d", get_next_states( 4)(2)) assert(get_next_states( 4)(3) === 8.U(plru.nBits.W), s"get_next_state state=04 way=3: expected=08 actual=%d", get_next_states( 4)(3)) assert(get_next_states( 4)(4) === 4.U(plru.nBits.W), s"get_next_state state=04 way=4: expected=04 actual=%d", get_next_states( 4)(4)) assert(get_next_states( 5)(0) === 13.U(plru.nBits.W), s"get_next_state state=05 way=0: expected=13 actual=%d", get_next_states( 5)(0)) assert(get_next_states( 5)(1) === 12.U(plru.nBits.W), s"get_next_state state=05 way=1: expected=12 actual=%d", get_next_states( 5)(1)) assert(get_next_states( 5)(2) === 11.U(plru.nBits.W), s"get_next_state state=05 way=2: expected=11 actual=%d", get_next_states( 5)(2)) assert(get_next_states( 5)(3) === 9.U(plru.nBits.W), s"get_next_state state=05 way=3: expected=09 actual=%d", get_next_states( 5)(3)) assert(get_next_states( 5)(4) === 5.U(plru.nBits.W), s"get_next_state state=05 way=4: expected=05 actual=%d", get_next_states( 5)(4)) assert(get_next_states( 6)(0) === 15.U(plru.nBits.W), s"get_next_state state=06 way=0: expected=15 actual=%d", get_next_states( 6)(0)) assert(get_next_states( 6)(1) === 14.U(plru.nBits.W), s"get_next_state state=06 way=1: expected=14 actual=%d", get_next_states( 6)(1)) assert(get_next_states( 6)(2) === 10.U(plru.nBits.W), s"get_next_state state=06 way=2: expected=10 actual=%d", get_next_states( 6)(2)) assert(get_next_states( 6)(3) === 8.U(plru.nBits.W), s"get_next_state state=06 way=3: expected=08 actual=%d", get_next_states( 6)(3)) assert(get_next_states( 6)(4) === 6.U(plru.nBits.W), s"get_next_state state=06 way=4: expected=06 actual=%d", get_next_states( 6)(4)) assert(get_next_states( 7)(0) === 15.U(plru.nBits.W), s"get_next_state state=07 way=0: expected=15 actual=%d", get_next_states( 7)(0)) assert(get_next_states( 7)(1) === 14.U(plru.nBits.W), s"get_next_state state=07 way=5: expected=14 actual=%d", get_next_states( 7)(1)) assert(get_next_states( 7)(2) === 11.U(plru.nBits.W), s"get_next_state state=07 way=2: expected=11 actual=%d", get_next_states( 7)(2)) assert(get_next_states( 7)(3) === 9.U(plru.nBits.W), s"get_next_state state=07 way=3: expected=09 actual=%d", get_next_states( 7)(3)) assert(get_next_states( 7)(4) === 7.U(plru.nBits.W), s"get_next_state state=07 way=4: expected=07 actual=%d", get_next_states( 7)(4)) assert(get_next_states( 8)(0) === 13.U(plru.nBits.W), s"get_next_state state=08 way=0: expected=13 actual=%d", get_next_states( 8)(0)) assert(get_next_states( 8)(1) === 12.U(plru.nBits.W), s"get_next_state state=08 way=1: expected=12 actual=%d", get_next_states( 8)(1)) assert(get_next_states( 8)(2) === 10.U(plru.nBits.W), s"get_next_state state=08 way=2: expected=10 actual=%d", get_next_states( 8)(2)) assert(get_next_states( 8)(3) === 8.U(plru.nBits.W), s"get_next_state state=08 way=3: expected=08 actual=%d", get_next_states( 8)(3)) assert(get_next_states( 8)(4) === 0.U(plru.nBits.W), s"get_next_state state=08 way=4: expected=00 actual=%d", get_next_states( 8)(4)) assert(get_next_states( 9)(0) === 13.U(plru.nBits.W), s"get_next_state state=09 way=0: expected=13 actual=%d", get_next_states( 9)(0)) assert(get_next_states( 9)(1) === 12.U(plru.nBits.W), s"get_next_state state=09 way=1: expected=12 actual=%d", get_next_states( 9)(1)) assert(get_next_states( 9)(2) === 11.U(plru.nBits.W), s"get_next_state state=09 way=2: expected=11 actual=%d", get_next_states( 9)(2)) assert(get_next_states( 9)(3) === 9.U(plru.nBits.W), s"get_next_state state=09 way=3: expected=09 actual=%d", get_next_states( 9)(3)) assert(get_next_states( 9)(4) === 1.U(plru.nBits.W), s"get_next_state state=09 way=4: expected=01 actual=%d", get_next_states( 9)(4)) assert(get_next_states(10)(0) === 15.U(plru.nBits.W), s"get_next_state state=10 way=0: expected=15 actual=%d", get_next_states(10)(0)) assert(get_next_states(10)(1) === 14.U(plru.nBits.W), s"get_next_state state=10 way=1: expected=14 actual=%d", get_next_states(10)(1)) assert(get_next_states(10)(2) === 10.U(plru.nBits.W), s"get_next_state state=10 way=2: expected=10 actual=%d", get_next_states(10)(2)) assert(get_next_states(10)(3) === 8.U(plru.nBits.W), s"get_next_state state=10 way=3: expected=08 actual=%d", get_next_states(10)(3)) assert(get_next_states(10)(4) === 2.U(plru.nBits.W), s"get_next_state state=10 way=4: expected=02 actual=%d", get_next_states(10)(4)) assert(get_next_states(11)(0) === 15.U(plru.nBits.W), s"get_next_state state=11 way=0: expected=15 actual=%d", get_next_states(11)(0)) assert(get_next_states(11)(1) === 14.U(plru.nBits.W), s"get_next_state state=11 way=1: expected=14 actual=%d", get_next_states(11)(1)) assert(get_next_states(11)(2) === 11.U(plru.nBits.W), s"get_next_state state=11 way=2: expected=11 actual=%d", get_next_states(11)(2)) assert(get_next_states(11)(3) === 9.U(plru.nBits.W), s"get_next_state state=11 way=3: expected=09 actual=%d", get_next_states(11)(3)) assert(get_next_states(11)(4) === 3.U(plru.nBits.W), s"get_next_state state=11 way=4: expected=03 actual=%d", get_next_states(11)(4)) assert(get_next_states(12)(0) === 13.U(plru.nBits.W), s"get_next_state state=12 way=0: expected=13 actual=%d", get_next_states(12)(0)) assert(get_next_states(12)(1) === 12.U(plru.nBits.W), s"get_next_state state=12 way=1: expected=12 actual=%d", get_next_states(12)(1)) assert(get_next_states(12)(2) === 10.U(plru.nBits.W), s"get_next_state state=12 way=2: expected=10 actual=%d", get_next_states(12)(2)) assert(get_next_states(12)(3) === 8.U(plru.nBits.W), s"get_next_state state=12 way=3: expected=08 actual=%d", get_next_states(12)(3)) assert(get_next_states(12)(4) === 4.U(plru.nBits.W), s"get_next_state state=12 way=4: expected=04 actual=%d", get_next_states(12)(4)) assert(get_next_states(13)(0) === 13.U(plru.nBits.W), s"get_next_state state=13 way=0: expected=13 actual=%d", get_next_states(13)(0)) assert(get_next_states(13)(1) === 12.U(plru.nBits.W), s"get_next_state state=13 way=1: expected=12 actual=%d", get_next_states(13)(1)) assert(get_next_states(13)(2) === 11.U(plru.nBits.W), s"get_next_state state=13 way=2: expected=11 actual=%d", get_next_states(13)(2)) assert(get_next_states(13)(3) === 9.U(plru.nBits.W), s"get_next_state state=13 way=3: expected=09 actual=%d", get_next_states(13)(3)) assert(get_next_states(13)(4) === 5.U(plru.nBits.W), s"get_next_state state=13 way=4: expected=05 actual=%d", get_next_states(13)(4)) assert(get_next_states(14)(0) === 15.U(plru.nBits.W), s"get_next_state state=14 way=0: expected=15 actual=%d", get_next_states(14)(0)) assert(get_next_states(14)(1) === 14.U(plru.nBits.W), s"get_next_state state=14 way=1: expected=14 actual=%d", get_next_states(14)(1)) assert(get_next_states(14)(2) === 10.U(plru.nBits.W), s"get_next_state state=14 way=2: expected=10 actual=%d", get_next_states(14)(2)) assert(get_next_states(14)(3) === 8.U(plru.nBits.W), s"get_next_state state=14 way=3: expected=08 actual=%d", get_next_states(14)(3)) assert(get_next_states(14)(4) === 6.U(plru.nBits.W), s"get_next_state state=14 way=4: expected=06 actual=%d", get_next_states(14)(4)) assert(get_next_states(15)(0) === 15.U(plru.nBits.W), s"get_next_state state=15 way=0: expected=15 actual=%d", get_next_states(15)(0)) assert(get_next_states(15)(1) === 14.U(plru.nBits.W), s"get_next_state state=15 way=5: expected=14 actual=%d", get_next_states(15)(1)) assert(get_next_states(15)(2) === 11.U(plru.nBits.W), s"get_next_state state=15 way=2: expected=11 actual=%d", get_next_states(15)(2)) assert(get_next_states(15)(3) === 9.U(plru.nBits.W), s"get_next_state state=15 way=3: expected=09 actual=%d", get_next_states(15)(3)) assert(get_next_states(15)(4) === 7.U(plru.nBits.W), s"get_next_state state=15 way=4: expected=07 actual=%d", get_next_states(15)(4)) } case 6 => { assert(get_replace_ways( 0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=00: expected=0 actual=%d", get_replace_ways( 0)) assert(get_replace_ways( 1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=01: expected=1 actual=%d", get_replace_ways( 1)) assert(get_replace_ways( 2) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=02: expected=0 actual=%d", get_replace_ways( 2)) assert(get_replace_ways( 3) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=03: expected=1 actual=%d", get_replace_ways( 3)) assert(get_replace_ways( 4) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=04: expected=2 actual=%d", get_replace_ways( 4)) assert(get_replace_ways( 5) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=05: expected=2 actual=%d", get_replace_ways( 5)) assert(get_replace_ways( 6) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=06: expected=3 actual=%d", get_replace_ways( 6)) assert(get_replace_ways( 7) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=07: expected=3 actual=%d", get_replace_ways( 7)) assert(get_replace_ways( 8) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=08: expected=0 actual=%d", get_replace_ways( 8)) assert(get_replace_ways( 9) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=09: expected=1 actual=%d", get_replace_ways( 9)) assert(get_replace_ways(10) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=10: expected=0 actual=%d", get_replace_ways(10)) assert(get_replace_ways(11) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=11: expected=1 actual=%d", get_replace_ways(11)) assert(get_replace_ways(12) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=12: expected=2 actual=%d", get_replace_ways(12)) assert(get_replace_ways(13) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=13: expected=2 actual=%d", get_replace_ways(13)) assert(get_replace_ways(14) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=14: expected=3 actual=%d", get_replace_ways(14)) assert(get_replace_ways(15) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=15: expected=3 actual=%d", get_replace_ways(15)) assert(get_replace_ways(16) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=16: expected=4 actual=%d", get_replace_ways(16)) assert(get_replace_ways(17) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=17: expected=4 actual=%d", get_replace_ways(17)) assert(get_replace_ways(18) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=18: expected=4 actual=%d", get_replace_ways(18)) assert(get_replace_ways(19) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=19: expected=4 actual=%d", get_replace_ways(19)) assert(get_replace_ways(20) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=20: expected=4 actual=%d", get_replace_ways(20)) assert(get_replace_ways(21) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=21: expected=4 actual=%d", get_replace_ways(21)) assert(get_replace_ways(22) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=22: expected=4 actual=%d", get_replace_ways(22)) assert(get_replace_ways(23) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=23: expected=4 actual=%d", get_replace_ways(23)) assert(get_replace_ways(24) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=24: expected=5 actual=%d", get_replace_ways(24)) assert(get_replace_ways(25) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=25: expected=5 actual=%d", get_replace_ways(25)) assert(get_replace_ways(26) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=26: expected=5 actual=%d", get_replace_ways(26)) assert(get_replace_ways(27) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=27: expected=5 actual=%d", get_replace_ways(27)) assert(get_replace_ways(28) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=28: expected=5 actual=%d", get_replace_ways(28)) assert(get_replace_ways(29) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=29: expected=5 actual=%d", get_replace_ways(29)) assert(get_replace_ways(30) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=30: expected=5 actual=%d", get_replace_ways(30)) assert(get_replace_ways(31) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=31: expected=5 actual=%d", get_replace_ways(31)) } case _ => throw new IllegalArgumentException(s"no test pattern found for n_ways=$n_ways") } } File HellaCache.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3.{dontTouch, _} import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.bundlebridge._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.amba.AMBAProtField import freechips.rocketchip.diplomacy.{IdRange, TransferSizes, RegionType} import freechips.rocketchip.tile.{L1CacheParams, HasL1CacheParameters, HasCoreParameters, CoreBundle, HasNonDiplomaticTileParameters, BaseTile, HasTileParameters} import freechips.rocketchip.tilelink.{TLMasterParameters, TLClientNode, TLMasterPortParameters, TLEdgeOut, TLWidthWidget, TLFIFOFixer, ClientMetadata} import freechips.rocketchip.util.{Code, RandomReplacement, ParameterizedBundle} import freechips.rocketchip.util.{BooleanToAugmentedBoolean, IntToAugmentedInt} import scala.collection.mutable.ListBuffer case class DCacheParams( nSets: Int = 64, nWays: Int = 4, rowBits: Int = 64, subWordBits: Option[Int] = None, replacementPolicy: String = "random", nTLBSets: Int = 1, nTLBWays: Int = 32, nTLBBasePageSectors: Int = 4, nTLBSuperpages: Int = 4, tagECC: Option[String] = None, dataECC: Option[String] = None, dataECCBytes: Int = 1, nMSHRs: Int = 1, nSDQ: Int = 17, nRPQ: Int = 16, nMMIOs: Int = 1, blockBytes: Int = 64, separateUncachedResp: Boolean = false, acquireBeforeRelease: Boolean = false, pipelineWayMux: Boolean = false, clockGate: Boolean = false, scratch: Option[BigInt] = None) extends L1CacheParams { def tagCode: Code = Code.fromString(tagECC) def dataCode: Code = Code.fromString(dataECC) def dataScratchpadBytes: Int = scratch.map(_ => nSets*blockBytes).getOrElse(0) def replacement = new RandomReplacement(nWays) def silentDrop: Boolean = !acquireBeforeRelease require((!scratch.isDefined || nWays == 1), "Scratchpad only allowed in direct-mapped cache.") require((!scratch.isDefined || nMSHRs == 0), "Scratchpad only allowed in blocking cache.") if (scratch.isEmpty) require(isPow2(nSets), s"nSets($nSets) must be pow2") } trait HasL1HellaCacheParameters extends HasL1CacheParameters with HasCoreParameters { val cacheParams = tileParams.dcache.get val cfg = cacheParams def wordBits = coreDataBits def wordBytes = coreDataBytes def subWordBits = cacheParams.subWordBits.getOrElse(wordBits) def subWordBytes = subWordBits / 8 def wordOffBits = log2Up(wordBytes) def beatBytes = cacheBlockBytes / cacheDataBeats def beatWords = beatBytes / wordBytes def beatOffBits = log2Up(beatBytes) def idxMSB = untagBits-1 def idxLSB = blockOffBits def offsetmsb = idxLSB-1 def offsetlsb = wordOffBits def rowWords = rowBits/wordBits def doNarrowRead = coreDataBits * nWays % rowBits == 0 def eccBytes = cacheParams.dataECCBytes val eccBits = cacheParams.dataECCBytes * 8 val encBits = cacheParams.dataCode.width(eccBits) val encWordBits = encBits * (wordBits / eccBits) def encDataBits = cacheParams.dataCode.width(coreDataBits) // NBDCache only def encRowBits = encDataBits*rowWords def lrscCycles = coreParams.lrscCycles // ISA requires 16-insn LRSC sequences to succeed def lrscBackoff = 3 // disallow LRSC reacquisition briefly def blockProbeAfterGrantCycles = 8 // give the processor some time to issue a request after a grant def nIOMSHRs = cacheParams.nMMIOs def maxUncachedInFlight = cacheParams.nMMIOs def dataScratchpadSize = cacheParams.dataScratchpadBytes require(rowBits >= coreDataBits, s"rowBits($rowBits) < coreDataBits($coreDataBits)") if (!usingDataScratchpad) require(rowBits == cacheDataBits, s"rowBits($rowBits) != cacheDataBits($cacheDataBits)") // would need offset addr for puts if data width < xlen require(xLen <= cacheDataBits, s"xLen($xLen) > cacheDataBits($cacheDataBits)") } abstract class L1HellaCacheModule(implicit val p: Parameters) extends Module with HasL1HellaCacheParameters abstract class L1HellaCacheBundle(implicit val p: Parameters) extends ParameterizedBundle()(p) with HasL1HellaCacheParameters /** Bundle definitions for HellaCache interfaces */ trait HasCoreMemOp extends HasL1HellaCacheParameters { val addr = UInt(coreMaxAddrBits.W) val idx = (usingVM && untagBits > pgIdxBits).option(UInt(coreMaxAddrBits.W)) val tag = UInt((coreParams.dcacheReqTagBits + log2Ceil(dcacheArbPorts)).W) val cmd = UInt(M_SZ.W) val size = UInt(log2Ceil(coreDataBytes.log2 + 1).W) val signed = Bool() val dprv = UInt(PRV.SZ.W) val dv = Bool() } trait HasCoreData extends HasCoreParameters { val data = UInt(coreDataBits.W) val mask = UInt(coreDataBytes.W) } class HellaCacheReqInternal(implicit p: Parameters) extends CoreBundle()(p) with HasCoreMemOp { val phys = Bool() val no_resp = Bool() // The dcache may omit generating a response for this request val no_alloc = Bool() val no_xcpt = Bool() } class HellaCacheReq(implicit p: Parameters) extends HellaCacheReqInternal()(p) with HasCoreData class HellaCacheResp(implicit p: Parameters) extends CoreBundle()(p) with HasCoreMemOp with HasCoreData { val replay = Bool() val has_data = Bool() val data_word_bypass = UInt(coreDataBits.W) val data_raw = UInt(coreDataBits.W) val store_data = UInt(coreDataBits.W) } class AlignmentExceptions extends Bundle { val ld = Bool() val st = Bool() } class HellaCacheExceptions extends Bundle { val ma = new AlignmentExceptions val pf = new AlignmentExceptions val gf = new AlignmentExceptions val ae = new AlignmentExceptions } class HellaCacheWriteData(implicit p: Parameters) extends CoreBundle()(p) with HasCoreData class HellaCachePerfEvents extends Bundle { val acquire = Bool() val release = Bool() val grant = Bool() val tlbMiss = Bool() val blocked = Bool() val canAcceptStoreThenLoad = Bool() val canAcceptStoreThenRMW = Bool() val canAcceptLoadThenLoad = Bool() val storeBufferEmptyAfterLoad = Bool() val storeBufferEmptyAfterStore = Bool() } // interface between D$ and processor/DTLB class HellaCacheIO(implicit p: Parameters) extends CoreBundle()(p) { val req = Decoupled(new HellaCacheReq) val s1_kill = Output(Bool()) // kill previous cycle's req val s1_data = Output(new HellaCacheWriteData()) // data for previous cycle's req val s2_nack = Input(Bool()) // req from two cycles ago is rejected val s2_nack_cause_raw = Input(Bool()) // reason for nack is store-load RAW hazard (performance hint) val s2_kill = Output(Bool()) // kill req from two cycles ago val s2_uncached = Input(Bool()) // advisory signal that the access is MMIO val s2_paddr = Input(UInt(paddrBits.W)) // translated address val resp = Flipped(Valid(new HellaCacheResp)) val replay_next = Input(Bool()) val s2_xcpt = Input(new HellaCacheExceptions) val s2_gpa = Input(UInt(vaddrBitsExtended.W)) val s2_gpa_is_pte = Input(Bool()) val uncached_resp = tileParams.dcache.get.separateUncachedResp.option(Flipped(Decoupled(new HellaCacheResp))) val ordered = Input(Bool()) val store_pending = Input(Bool()) // there is a store in a store buffer somewhere val perf = Input(new HellaCachePerfEvents()) val keep_clock_enabled = Output(Bool()) // should D$ avoid clock-gating itself? val clock_enabled = Input(Bool()) // is D$ currently being clocked? } /** Base classes for Diplomatic TL2 HellaCaches */ abstract class HellaCache(tileId: Int)(implicit p: Parameters) extends LazyModule with HasNonDiplomaticTileParameters { protected val cfg = tileParams.dcache.get protected def cacheClientParameters = cfg.scratch.map(x => Seq()).getOrElse(Seq(TLMasterParameters.v1( name = s"Core ${tileId} DCache", sourceId = IdRange(0, 1 max cfg.nMSHRs), supportsProbe = TransferSizes(cfg.blockBytes, cfg.blockBytes)))) protected def mmioClientParameters = Seq(TLMasterParameters.v1( name = s"Core ${tileId} DCache MMIO", sourceId = IdRange(firstMMIO, firstMMIO + cfg.nMMIOs), requestFifo = true)) def firstMMIO = (cacheClientParameters.map(_.sourceId.end) :+ 0).max val node = TLClientNode(Seq(TLMasterPortParameters.v1( clients = cacheClientParameters ++ mmioClientParameters, minLatency = 1, requestFields = tileParams.core.useVM.option(Seq()).getOrElse(Seq(AMBAProtField()))))) val hartIdSinkNodeOpt = cfg.scratch.map(_ => BundleBridgeSink[UInt]()) val mmioAddressPrefixSinkNodeOpt = cfg.scratch.map(_ => BundleBridgeSink[UInt]()) val module: HellaCacheModule def flushOnFenceI = cfg.scratch.isEmpty && !node.edges.out(0).manager.managers.forall(m => !m.supportsAcquireB || !m.executable || m.regionType >= RegionType.TRACKED || m.regionType <= RegionType.IDEMPOTENT) def canSupportCFlushLine = !usingVM || cfg.blockBytes * cfg.nSets <= (1 << pgIdxBits) require(!tileParams.core.haveCFlush || cfg.scratch.isEmpty, "CFLUSH_D_L1 instruction requires a D$") } class HellaCacheBundle(implicit p: Parameters) extends CoreBundle()(p) { val cpu = Flipped(new HellaCacheIO) val ptw = new TLBPTWIO() val errors = new DCacheErrors val tlb_port = new DCacheTLBPort } class HellaCacheModule(outer: HellaCache) extends LazyModuleImp(outer) with HasL1HellaCacheParameters { implicit val edge: TLEdgeOut = outer.node.edges.out(0) val (tl_out, _) = outer.node.out(0) val io = IO(new HellaCacheBundle) val io_hartid = outer.hartIdSinkNodeOpt.map(_.bundle) val io_mmio_address_prefix = outer.mmioAddressPrefixSinkNodeOpt.map(_.bundle) dontTouch(io.cpu.resp) // Users like to monitor these fields even if the core ignores some signals dontTouch(io.cpu.s1_data) require(rowBits == edge.bundle.dataBits) private val fifoManagers = edge.manager.managers.filter(TLFIFOFixer.allVolatile) fifoManagers.foreach { m => require (m.fifoId == fifoManagers.head.fifoId, s"IOMSHRs must be FIFO for all regions with effects, but HellaCache sees\n"+ s"${m.nodePath.map(_.name)}\nversus\n${fifoManagers.head.nodePath.map(_.name)}") } } /** Support overriding which HellaCache is instantiated */ case object BuildHellaCache extends Field[BaseTile => Parameters => HellaCache](HellaCacheFactory.apply) object HellaCacheFactory { def apply(tile: BaseTile)(p: Parameters): HellaCache = { if (tile.tileParams.dcache.get.nMSHRs == 0) new DCache(tile.tileId, tile.crossing)(p) else new NonBlockingDCache(tile.tileId)(p) } } /** Mix-ins for constructing tiles that have a HellaCache */ trait HasHellaCache { this: BaseTile => val module: HasHellaCacheModule implicit val p: Parameters var nDCachePorts = 0 lazy val dcache: HellaCache = LazyModule(p(BuildHellaCache)(this)(p)) tlMasterXbar.node := TLWidthWidget(tileParams.dcache.get.rowBits/8) := dcache.node dcache.hartIdSinkNodeOpt.map { _ := hartIdNexusNode } dcache.mmioAddressPrefixSinkNodeOpt.map { _ := mmioAddressPrefixNexusNode } InModuleBody { dcache.module.io.tlb_port := DontCare } } trait HasHellaCacheModule { val outer: HasHellaCache with HasTileParameters implicit val p: Parameters val dcachePorts = ListBuffer[HellaCacheIO]() val dcacheArb = Module(new HellaCacheArbiter(outer.nDCachePorts)(outer.p)) outer.dcache.module.io.cpu <> dcacheArb.io.mem } /** Metadata array used for all HellaCaches */ class L1Metadata(implicit p: Parameters) extends L1HellaCacheBundle()(p) { val coh = new ClientMetadata val tag = UInt(tagBits.W) } object L1Metadata { def apply(tag: Bits, coh: ClientMetadata)(implicit p: Parameters) = { val meta = Wire(new L1Metadata) meta.tag := tag meta.coh := coh meta } } class L1MetaReadReq(implicit p: Parameters) extends L1HellaCacheBundle()(p) { val idx = UInt(idxBits.W) val way_en = UInt(nWays.W) val tag = UInt(tagBits.W) } class L1MetaWriteReq(implicit p: Parameters) extends L1MetaReadReq()(p) { val data = new L1Metadata } class L1MetadataArray[T <: L1Metadata](onReset: () => T)(implicit p: Parameters) extends L1HellaCacheModule()(p) { val rstVal = onReset() val io = IO(new Bundle { val read = Flipped(Decoupled(new L1MetaReadReq)) val write = Flipped(Decoupled(new L1MetaWriteReq)) val resp = Output(Vec(nWays, rstVal.cloneType)) }) val rst_cnt = RegInit(0.U(log2Up(nSets+1).W)) val rst = rst_cnt < nSets.U val waddr = Mux(rst, rst_cnt, io.write.bits.idx) val wdata = Mux(rst, rstVal, io.write.bits.data).asUInt val wmask = Mux(rst || (nWays == 1).B, (-1).S, io.write.bits.way_en.asSInt).asBools val rmask = Mux(rst || (nWays == 1).B, (-1).S, io.read.bits.way_en.asSInt).asBools when (rst) { rst_cnt := rst_cnt+1.U } val metabits = rstVal.getWidth val tag_array = SyncReadMem(nSets, Vec(nWays, UInt(metabits.W))) val wen = rst || io.write.valid when (wen) { tag_array.write(waddr, VecInit.fill(nWays)(wdata), wmask) } io.resp := tag_array.read(io.read.bits.idx, io.read.fire).map(_.asTypeOf(chiselTypeOf(rstVal))) io.read.ready := !wen // so really this could be a 6T RAM io.write.ready := !rst } File ECC.scala: // See LICENSE.Berkeley for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR abstract class Decoding { def uncorrected: UInt def corrected: UInt def correctable: Bool def uncorrectable: Bool // If true, correctable should be ignored def error = correctable || uncorrectable } abstract class Code { def canDetect: Boolean def canCorrect: Boolean def width(w0: Int): Int /** Takes the unencoded width and returns a list of indices indicating which * bits of the encoded value will be used for ecc */ def eccIndices(width: Int): Seq[Int] /** Encode x to a codeword suitable for decode. * If poison is true, the decoded value will report uncorrectable * error despite uncorrected == corrected == x. */ def encode(x: UInt, poison: Bool = false.B): UInt def decode(x: UInt): Decoding /** Copy the bits in x to the right bit positions in an encoded word, * so that x === decode(swizzle(x)).uncorrected; but don't generate * the other code bits, so decode(swizzle(x)).error might be true. * For codes for which this operation is not trivial, throw an * UnsupportedOperationException. */ def swizzle(x: UInt): UInt } class IdentityCode extends Code { def canDetect = false def canCorrect = false def width(w0: Int) = w0 def eccIndices(width: Int) = Seq.empty[Int] def encode(x: UInt, poison: Bool = false.B) = { require (poison.isLit && poison.litValue == 0, "IdentityCode can not be poisoned") x } def swizzle(x: UInt) = x def decode(y: UInt) = new Decoding { def uncorrected = y def corrected = y def correctable = false.B def uncorrectable = false.B } } class ParityCode extends Code { def canDetect = true def canCorrect = false def width(w0: Int) = w0+1 def eccIndices(w0: Int) = Seq(w0) def encode(x: UInt, poison: Bool = false.B) = Cat(x.xorR ^ poison, x) def swizzle(x: UInt) = Cat(false.B, x) def decode(y: UInt) = new Decoding { val uncorrected = y(y.getWidth-2,0) val corrected = uncorrected val correctable = false.B val uncorrectable = y.xorR } } class SECCode extends Code { def canDetect = true def canCorrect = true // SEC codes may or may not be poisonous depending on the length // If the code is perfect, every non-codeword is correctable def poisonous(n: Int) = !isPow2(n+1) def width(k: Int) = { val m = log2Floor(k) + 1 k + m + (if((1 << m) < m+k+1) 1 else 0) } def eccIndices(w0: Int) = { (0 until width(w0)).collect { case i if i >= w0 => i } } def swizzle(x: UInt) = { val k = x.getWidth val n = width(k) Cat(0.U((n-k).W), x) } // An (n=16, k=11) Hamming code is naturally encoded as: // PPxPxxxPxxxxxxxP where P are parity bits and x are data // Indexes typically start at 1, because then the P are on powers of two // In systematic coding, you put all the data in the front: // xxxxxxxxxxxPPPPP // Indexes typically start at 0, because Computer Science // For sanity when reading SRAMs, you want systematic form. private def impl(n: Int, k: Int) = { require (n >= 3 && k >= 1 && !isPow2(n)) val hamm2sys = IndexedSeq.tabulate(n+1) { i => if (i == 0) { n /* undefined */ } else if (isPow2(i)) { k + log2Ceil(i) } else { i - 1 - log2Ceil(i) } } val sys2hamm = hamm2sys.zipWithIndex.sortBy(_._1).map(_._2).toIndexedSeq def syndrome(j: Int) = { val bit = 1 << j ("b" + Seq.tabulate(n) { i => if ((sys2hamm(i) & bit) != 0) "1" else "0" }.reverse.mkString).U } (hamm2sys, sys2hamm, syndrome _) } def encode(x: UInt, poison: Bool = false.B) = { val k = x.getWidth val n = width(k) val (_, _, syndrome) = impl(n, k) require ((poison.isLit && poison.litValue == 0) || poisonous(n), s"SEC code of length ${n} cannot be poisoned") /* By setting the entire syndrome on poison, the corrected bit falls off the end of the code */ val syndromeUInt = VecInit.tabulate(n-k) { j => (syndrome(j)(k-1, 0) & x).xorR ^ poison }.asUInt Cat(syndromeUInt, x) } def decode(y: UInt) = new Decoding { val n = y.getWidth val k = n - log2Ceil(n) val (_, sys2hamm, syndrome) = impl(n, k) val syndromeUInt = VecInit.tabulate(n-k) { j => (syndrome(j) & y).xorR }.asUInt val hammBadBitOH = UIntToOH(syndromeUInt, n+1) val sysBadBitOH = VecInit.tabulate(k) { i => hammBadBitOH(sys2hamm(i)) }.asUInt val uncorrected = y(k-1, 0) val corrected = uncorrected ^ sysBadBitOH val correctable = syndromeUInt.orR val uncorrectable = if (poisonous(n)) { syndromeUInt > n.U } else { false.B } } } class SECDEDCode extends Code { def canDetect = true def canCorrect = true private val sec = new SECCode private val par = new ParityCode def width(k: Int) = sec.width(k)+1 def eccIndices(w0: Int) = { (0 until width(w0)).collect { case i if i >= w0 => i } } def encode(x: UInt, poison: Bool = false.B) = { // toggling two bits ensures the error is uncorrectable // to ensure corrected == uncorrected, we pick one redundant // bit from SEC (the highest); correcting it does not affect // corrected == uncorrected. the second toggled bit is the // parity bit, which also does not appear in the decoding val toggle_lo = Cat(poison.asUInt, poison.asUInt) val toggle_hi = toggle_lo << (sec.width(x.getWidth)-1) par.encode(sec.encode(x)) ^ toggle_hi } def swizzle(x: UInt) = par.swizzle(sec.swizzle(x)) def decode(x: UInt) = new Decoding { val secdec = sec.decode(x(x.getWidth-2,0)) val pardec = par.decode(x) val uncorrected = secdec.uncorrected val corrected = secdec.corrected val correctable = pardec.uncorrectable val uncorrectable = !pardec.uncorrectable && secdec.correctable } } object ErrGen { // generate a 1-bit error with approximate probability 2^-f def apply(width: Int, f: Int): UInt = { require(width > 0 && f >= 0 && log2Up(width) + f <= 16) UIntToOH(LFSR(16)(log2Up(width)+f-1,0))(width-1,0) } def apply(x: UInt, f: Int): UInt = x ^ apply(x.getWidth, f) } trait CanHaveErrors extends Bundle { val correctable: Option[ValidIO[UInt]] val uncorrectable: Option[ValidIO[UInt]] } case class ECCParams( bytes: Int = 1, code: Code = new IdentityCode, notifyErrors: Boolean = false, ) object Code { def fromString(s: Option[String]): Code = fromString(s.getOrElse("none")) def fromString(s: String): Code = s.toLowerCase match { case "none" => new IdentityCode case "identity" => new IdentityCode case "parity" => new ParityCode case "sec" => new SECCode case "secded" => new SECDEDCode case _ => throw new IllegalArgumentException("Unknown ECC type") } } // Synthesizable unit tests import freechips.rocketchip.unittest._ class ECCTest(k: Int, timeout: Int = 500000) extends UnitTest(timeout) { val code = new SECDEDCode val n = code.width(k) // Brute force the decode space val test = RegInit(0.U((n+1).W)) val last = test(n) test := test + !last io.finished := RegNext(last, false.B) // Confirm the decoding matches the encoding val decoded = code.decode(test(n-1, 0)) val recoded = code.encode(decoded.corrected) val distance = PopCount(recoded ^ test) // Count the cases val correct = RegInit(0.U(n.W)) val correctable = RegInit(0.U(n.W)) val uncorrectable = RegInit(0.U(n.W)) when (!last) { when (decoded.uncorrectable) { assert (distance >= 2.U) // uncorrectable uncorrectable := uncorrectable + 1.U } .elsewhen (decoded.correctable) { assert (distance(0)) // correctable => odd bit errors correctable := correctable + 1.U } .otherwise { assert (distance === 0.U) // correct assert (decoded.uncorrected === decoded.corrected) correct := correct + 1.U } } // Expected number of each case val nCodes = BigInt(1) << n val nCorrect = BigInt(1) << k val nCorrectable = nCodes / 2 val nUncorrectable = nCodes - nCorrectable - nCorrect when (last) { assert (correct === nCorrect.U) assert (correctable === nCorrectable.U) assert (uncorrectable === nUncorrectable.U) } } File Consts.scala: // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket.constants import chisel3._ import chisel3.util._ import freechips.rocketchip.util._ trait ScalarOpConstants { val SZ_BR = 3 def BR_X = BitPat("b???") def BR_EQ = 0.U(3.W) def BR_NE = 1.U(3.W) def BR_J = 2.U(3.W) def BR_N = 3.U(3.W) def BR_LT = 4.U(3.W) def BR_GE = 5.U(3.W) def BR_LTU = 6.U(3.W) def BR_GEU = 7.U(3.W) def A1_X = BitPat("b??") def A1_ZERO = 0.U(2.W) def A1_RS1 = 1.U(2.W) def A1_PC = 2.U(2.W) def A1_RS1SHL = 3.U(2.W) def IMM_X = BitPat("b???") def IMM_S = 0.U(3.W) def IMM_SB = 1.U(3.W) def IMM_U = 2.U(3.W) def IMM_UJ = 3.U(3.W) def IMM_I = 4.U(3.W) def IMM_Z = 5.U(3.W) def A2_X = BitPat("b???") def A2_ZERO = 0.U(3.W) def A2_SIZE = 1.U(3.W) def A2_RS2 = 2.U(3.W) def A2_IMM = 3.U(3.W) def A2_RS2OH = 4.U(3.W) def A2_IMMOH = 5.U(3.W) def X = BitPat("b?") def N = BitPat("b0") def Y = BitPat("b1") val SZ_DW = 1 def DW_X = X def DW_32 = false.B def DW_64 = true.B def DW_XPR = DW_64 } trait MemoryOpConstants { val NUM_XA_OPS = 9 val M_SZ = 5 def M_X = BitPat("b?????"); def M_XRD = "b00000".U; // int load def M_XWR = "b00001".U; // int store def M_PFR = "b00010".U; // prefetch with intent to read def M_PFW = "b00011".U; // prefetch with intent to write def M_XA_SWAP = "b00100".U def M_FLUSH_ALL = "b00101".U // flush all lines def M_XLR = "b00110".U def M_XSC = "b00111".U def M_XA_ADD = "b01000".U def M_XA_XOR = "b01001".U def M_XA_OR = "b01010".U def M_XA_AND = "b01011".U def M_XA_MIN = "b01100".U def M_XA_MAX = "b01101".U def M_XA_MINU = "b01110".U def M_XA_MAXU = "b01111".U def M_FLUSH = "b10000".U // write back dirty data and cede R/W permissions def M_PWR = "b10001".U // partial (masked) store def M_PRODUCE = "b10010".U // write back dirty data and cede W permissions def M_CLEAN = "b10011".U // write back dirty data and retain R/W permissions def M_SFENCE = "b10100".U // SFENCE.VMA def M_HFENCEV = "b10101".U // HFENCE.VVMA def M_HFENCEG = "b10110".U // HFENCE.GVMA def M_WOK = "b10111".U // check write permissions but don't perform a write def M_HLVX = "b10000".U // HLVX instruction def isAMOLogical(cmd: UInt) = cmd.isOneOf(M_XA_SWAP, M_XA_XOR, M_XA_OR, M_XA_AND) def isAMOArithmetic(cmd: UInt) = cmd.isOneOf(M_XA_ADD, M_XA_MIN, M_XA_MAX, M_XA_MINU, M_XA_MAXU) def isAMO(cmd: UInt) = isAMOLogical(cmd) || isAMOArithmetic(cmd) def isPrefetch(cmd: UInt) = cmd === M_PFR || cmd === M_PFW def isRead(cmd: UInt) = cmd.isOneOf(M_XRD, M_HLVX, M_XLR, M_XSC) || isAMO(cmd) def isWrite(cmd: UInt) = cmd === M_XWR || cmd === M_PWR || cmd === M_XSC || isAMO(cmd) def isWriteIntent(cmd: UInt) = isWrite(cmd) || cmd === M_PFW || cmd === M_XLR } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File TLB.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import freechips.rocketchip.devices.debug.DebugModuleKey import freechips.rocketchip.diplomacy.RegionType import freechips.rocketchip.subsystem.CacheBlockBytes import freechips.rocketchip.tile.{CoreModule, CoreBundle} import freechips.rocketchip.tilelink._ import freechips.rocketchip.util.{OptimizationBarrier, SetAssocLRU, PseudoLRU, PopCountAtLeast, property} import freechips.rocketchip.util.BooleanToAugmentedBoolean import freechips.rocketchip.util.IntToAugmentedInt import freechips.rocketchip.util.UIntToAugmentedUInt import freechips.rocketchip.util.UIntIsOneOf import freechips.rocketchip.util.SeqToAugmentedSeq import freechips.rocketchip.util.SeqBoolBitwiseOps case object ASIdBits extends Field[Int](0) case object VMIdBits extends Field[Int](0) /** =SFENCE= * rs1 rs2 * {{{ * 0 0 -> flush All * 0 1 -> flush by ASID * 1 1 -> flush by ADDR * 1 0 -> flush by ADDR and ASID * }}} * {{{ * If rs1=x0 and rs2=x0, the fence orders all reads and writes made to any level of the page tables, for all address spaces. * If rs1=x0 and rs2!=x0, the fence orders all reads and writes made to any level of the page tables, but only for the address space identified by integer register rs2. Accesses to global mappings (see Section 4.3.1) are not ordered. * If rs1!=x0 and rs2=x0, the fence orders only reads and writes made to the leaf page table entry corresponding to the virtual address in rs1, for all address spaces. * If rs1!=x0 and rs2!=x0, the fence orders only reads and writes made to the leaf page table entry corresponding to the virtual address in rs1, for the address space identified by integer register rs2. Accesses to global mappings are not ordered. * }}} */ class SFenceReq(implicit p: Parameters) extends CoreBundle()(p) { val rs1 = Bool() val rs2 = Bool() val addr = UInt(vaddrBits.W) val asid = UInt((asIdBits max 1).W) // TODO zero-width val hv = Bool() val hg = Bool() } class TLBReq(lgMaxSize: Int)(implicit p: Parameters) extends CoreBundle()(p) { /** request address from CPU. */ val vaddr = UInt(vaddrBitsExtended.W) /** don't lookup TLB, bypass vaddr as paddr */ val passthrough = Bool() /** granularity */ val size = UInt(log2Ceil(lgMaxSize + 1).W) /** memory command. */ val cmd = Bits(M_SZ.W) val prv = UInt(PRV.SZ.W) /** virtualization mode */ val v = Bool() } class TLBExceptions extends Bundle { val ld = Bool() val st = Bool() val inst = Bool() } class TLBResp(lgMaxSize: Int = 3)(implicit p: Parameters) extends CoreBundle()(p) { // lookup responses val miss = Bool() /** physical address */ val paddr = UInt(paddrBits.W) val gpa = UInt(vaddrBitsExtended.W) val gpa_is_pte = Bool() /** page fault exception */ val pf = new TLBExceptions /** guest page fault exception */ val gf = new TLBExceptions /** access exception */ val ae = new TLBExceptions /** misaligned access exception */ val ma = new TLBExceptions /** if this address is cacheable */ val cacheable = Bool() /** if caches must allocate this address */ val must_alloc = Bool() /** if this address is prefetchable for caches*/ val prefetchable = Bool() /** size/cmd of request that generated this response*/ val size = UInt(log2Ceil(lgMaxSize + 1).W) val cmd = UInt(M_SZ.W) } class TLBEntryData(implicit p: Parameters) extends CoreBundle()(p) { val ppn = UInt(ppnBits.W) /** pte.u user */ val u = Bool() /** pte.g global */ val g = Bool() /** access exception. * D$ -> PTW -> TLB AE * Alignment failed. */ val ae_ptw = Bool() val ae_final = Bool() val ae_stage2 = Bool() /** page fault */ val pf = Bool() /** guest page fault */ val gf = Bool() /** supervisor write */ val sw = Bool() /** supervisor execute */ val sx = Bool() /** supervisor read */ val sr = Bool() /** hypervisor write */ val hw = Bool() /** hypervisor excute */ val hx = Bool() /** hypervisor read */ val hr = Bool() /** prot_w */ val pw = Bool() /** prot_x */ val px = Bool() /** prot_r */ val pr = Bool() /** PutPartial */ val ppp = Bool() /** AMO logical */ val pal = Bool() /** AMO arithmetic */ val paa = Bool() /** get/put effects */ val eff = Bool() /** cacheable */ val c = Bool() /** fragmented_superpage support */ val fragmented_superpage = Bool() } /** basic cell for TLB data */ class TLBEntry(val nSectors: Int, val superpage: Boolean, val superpageOnly: Boolean)(implicit p: Parameters) extends CoreBundle()(p) { require(nSectors == 1 || !superpage) require(!superpageOnly || superpage) val level = UInt(log2Ceil(pgLevels).W) /** use vpn as tag */ val tag_vpn = UInt(vpnBits.W) /** tag in vitualization mode */ val tag_v = Bool() /** entry data */ val data = Vec(nSectors, UInt(new TLBEntryData().getWidth.W)) /** valid bit */ val valid = Vec(nSectors, Bool()) /** returns all entry data in this entry */ def entry_data = data.map(_.asTypeOf(new TLBEntryData)) /** returns the index of sector */ private def sectorIdx(vpn: UInt) = vpn.extract(nSectors.log2-1, 0) /** returns the entry data matched with this vpn*/ def getData(vpn: UInt) = OptimizationBarrier(data(sectorIdx(vpn)).asTypeOf(new TLBEntryData)) /** returns whether a sector hits */ def sectorHit(vpn: UInt, virtual: Bool) = valid.orR && sectorTagMatch(vpn, virtual) /** returns whether tag matches vpn */ def sectorTagMatch(vpn: UInt, virtual: Bool) = (((tag_vpn ^ vpn) >> nSectors.log2) === 0.U) && (tag_v === virtual) /** returns hit signal */ def hit(vpn: UInt, virtual: Bool): Bool = { if (superpage && usingVM) { var tagMatch = valid.head && (tag_v === virtual) for (j <- 0 until pgLevels) { val base = (pgLevels - 1 - j) * pgLevelBits val n = pgLevelBits + (if (j == 0) hypervisorExtraAddrBits else 0) val ignore = level < j.U || (superpageOnly && j == pgLevels - 1).B tagMatch = tagMatch && (ignore || (tag_vpn ^ vpn)(base + n - 1, base) === 0.U) } tagMatch } else { val idx = sectorIdx(vpn) valid(idx) && sectorTagMatch(vpn, virtual) } } /** returns the ppn of the input TLBEntryData */ def ppn(vpn: UInt, data: TLBEntryData) = { val supervisorVPNBits = pgLevels * pgLevelBits if (superpage && usingVM) { var res = data.ppn >> pgLevelBits*(pgLevels - 1) for (j <- 1 until pgLevels) { val ignore = level < j.U || (superpageOnly && j == pgLevels - 1).B res = Cat(res, (Mux(ignore, vpn, 0.U) | data.ppn)(supervisorVPNBits - j*pgLevelBits - 1, supervisorVPNBits - (j + 1)*pgLevelBits)) } res } else { data.ppn } } /** does the refill * * find the target entry with vpn tag * and replace the target entry with the input entry data */ def insert(vpn: UInt, virtual: Bool, level: UInt, entry: TLBEntryData): Unit = { this.tag_vpn := vpn this.tag_v := virtual this.level := level.extract(log2Ceil(pgLevels - superpageOnly.toInt)-1, 0) val idx = sectorIdx(vpn) valid(idx) := true.B data(idx) := entry.asUInt } def invalidate(): Unit = { valid.foreach(_ := false.B) } def invalidate(virtual: Bool): Unit = { for ((v, e) <- valid zip entry_data) when (tag_v === virtual) { v := false.B } } def invalidateVPN(vpn: UInt, virtual: Bool): Unit = { if (superpage) { when (hit(vpn, virtual)) { invalidate() } } else { when (sectorTagMatch(vpn, virtual)) { for (((v, e), i) <- (valid zip entry_data).zipWithIndex) when (tag_v === virtual && i.U === sectorIdx(vpn)) { v := false.B } } } // For fragmented superpage mappings, we assume the worst (largest) // case, and zap entries whose most-significant VPNs match when (((tag_vpn ^ vpn) >> (pgLevelBits * (pgLevels - 1))) === 0.U) { for ((v, e) <- valid zip entry_data) when (tag_v === virtual && e.fragmented_superpage) { v := false.B } } } def invalidateNonGlobal(virtual: Bool): Unit = { for ((v, e) <- valid zip entry_data) when (tag_v === virtual && !e.g) { v := false.B } } } /** TLB config * * @param nSets the number of sets of PTE, follow [[ICacheParams.nSets]] * @param nWays the total number of wayss of PTE, follow [[ICacheParams.nWays]] * @param nSectors the number of ways in a single PTE TLBEntry * @param nSuperpageEntries the number of SuperpageEntries */ case class TLBConfig( nSets: Int, nWays: Int, nSectors: Int = 4, nSuperpageEntries: Int = 4) /** =Overview= * [[TLB]] is a TLB template which contains PMA logic and PMP checker. * * TLB caches PTE and accelerates the address translation process. * When tlb miss happens, ask PTW(L2TLB) for Page Table Walk. * Perform PMP and PMA check during the translation and throw exception if there were any. * * ==Cache Structure== * - Sectored Entry (PTE) * - set-associative or direct-mapped * - nsets = [[TLBConfig.nSets]] * - nways = [[TLBConfig.nWays]] / [[TLBConfig.nSectors]] * - PTEEntry( sectors = [[TLBConfig.nSectors]] ) * - LRU(if set-associative) * * - Superpage Entry(superpage PTE) * - fully associative * - nsets = [[TLBConfig.nSuperpageEntries]] * - PTEEntry(sectors = 1) * - PseudoLRU * * - Special Entry(PTE across PMP) * - nsets = 1 * - PTEEntry(sectors = 1) * * ==Address structure== * {{{ * |vaddr | * |ppn/vpn | pgIndex | * | | | * | |nSets |nSector | |}}} * * ==State Machine== * {{{ * s_ready: ready to accept request from CPU. * s_request: when L1TLB(this) miss, send request to PTW(L2TLB), . * s_wait: wait for PTW to refill L1TLB. * s_wait_invalidate: L1TLB is waiting for respond from PTW, but L1TLB will invalidate respond from PTW.}}} * * ==PMP== * pmp check * - special_entry: always check * - other entry: check on refill * * ==Note== * PMA consume diplomacy parameter generate physical memory address checking logic * * Boom use Rocket ITLB, and its own DTLB. * * Accelerators:{{{ * sha3: DTLB * gemmini: DTLB * hwacha: DTLB*2+ITLB}}} * @param instruction true for ITLB, false for DTLB * @param lgMaxSize @todo seems granularity * @param cfg [[TLBConfig]] * @param edge collect SoC metadata. */ class TLB(instruction: Boolean, lgMaxSize: Int, cfg: TLBConfig)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(p) { override def desiredName = if (instruction) "ITLB" else "DTLB" val io = IO(new Bundle { /** request from Core */ val req = Flipped(Decoupled(new TLBReq(lgMaxSize))) /** response to Core */ val resp = Output(new TLBResp(lgMaxSize)) /** SFence Input */ val sfence = Flipped(Valid(new SFenceReq)) /** IO to PTW */ val ptw = new TLBPTWIO /** suppress a TLB refill, one cycle after a miss */ val kill = Input(Bool()) }) io.ptw.customCSRs := DontCare val pageGranularityPMPs = pmpGranularity >= (1 << pgIdxBits) val vpn = io.req.bits.vaddr(vaddrBits-1, pgIdxBits) /** index for sectored_Entry */ val memIdx = vpn.extract(cfg.nSectors.log2 + cfg.nSets.log2 - 1, cfg.nSectors.log2) /** TLB Entry */ val sectored_entries = Reg(Vec(cfg.nSets, Vec(cfg.nWays / cfg.nSectors, new TLBEntry(cfg.nSectors, false, false)))) /** Superpage Entry */ val superpage_entries = Reg(Vec(cfg.nSuperpageEntries, new TLBEntry(1, true, true))) /** Special Entry * * If PMP granularity is less than page size, thus need additional "special" entry manage PMP. */ val special_entry = (!pageGranularityPMPs).option(Reg(new TLBEntry(1, true, false))) def ordinary_entries = sectored_entries(memIdx) ++ superpage_entries def all_entries = ordinary_entries ++ special_entry def all_real_entries = sectored_entries.flatten ++ superpage_entries ++ special_entry val s_ready :: s_request :: s_wait :: s_wait_invalidate :: Nil = Enum(4) val state = RegInit(s_ready) // use vpn as refill_tag val r_refill_tag = Reg(UInt(vpnBits.W)) val r_superpage_repl_addr = Reg(UInt(log2Ceil(superpage_entries.size).W)) val r_sectored_repl_addr = Reg(UInt(log2Ceil(sectored_entries.head.size).W)) val r_sectored_hit = Reg(Valid(UInt(log2Ceil(sectored_entries.head.size).W))) val r_superpage_hit = Reg(Valid(UInt(log2Ceil(superpage_entries.size).W))) val r_vstage1_en = Reg(Bool()) val r_stage2_en = Reg(Bool()) val r_need_gpa = Reg(Bool()) val r_gpa_valid = Reg(Bool()) val r_gpa = Reg(UInt(vaddrBits.W)) val r_gpa_vpn = Reg(UInt(vpnBits.W)) val r_gpa_is_pte = Reg(Bool()) /** privilege mode */ val priv = io.req.bits.prv val priv_v = usingHypervisor.B && io.req.bits.v val priv_s = priv(0) // user mode and supervisor mode val priv_uses_vm = priv <= PRV.S.U val satp = Mux(priv_v, io.ptw.vsatp, io.ptw.ptbr) val stage1_en = usingVM.B && satp.mode(satp.mode.getWidth-1) /** VS-stage translation enable */ val vstage1_en = usingHypervisor.B && priv_v && io.ptw.vsatp.mode(io.ptw.vsatp.mode.getWidth-1) /** G-stage translation enable */ val stage2_en = usingHypervisor.B && priv_v && io.ptw.hgatp.mode(io.ptw.hgatp.mode.getWidth-1) /** Enable Virtual Memory when: * 1. statically configured * 1. satp highest bits enabled * i. RV32: * - 0 -> Bare * - 1 -> SV32 * i. RV64: * - 0000 -> Bare * - 1000 -> SV39 * - 1001 -> SV48 * - 1010 -> SV57 * - 1011 -> SV64 * 1. In virtualization mode, vsatp highest bits enabled * 1. priv mode in U and S. * 1. in H & M mode, disable VM. * 1. no passthrough(micro-arch defined.) * * @see RV-priv spec 4.1.11 Supervisor Address Translation and Protection (satp) Register * @see RV-priv spec 8.2.18 Virtual Supervisor Address Translation and Protection Register (vsatp) */ val vm_enabled = (stage1_en || stage2_en) && priv_uses_vm && !io.req.bits.passthrough // flush guest entries on vsatp.MODE Bare <-> SvXX transitions val v_entries_use_stage1 = RegInit(false.B) val vsatp_mode_mismatch = priv_v && (vstage1_en =/= v_entries_use_stage1) && !io.req.bits.passthrough // share a single physical memory attribute checker (unshare if critical path) val refill_ppn = io.ptw.resp.bits.pte.ppn(ppnBits-1, 0) /** refill signal */ val do_refill = usingVM.B && io.ptw.resp.valid /** sfence invalidate refill */ val invalidate_refill = state.isOneOf(s_request /* don't care */, s_wait_invalidate) || io.sfence.valid // PMP val mpu_ppn = Mux(do_refill, refill_ppn, Mux(vm_enabled && special_entry.nonEmpty.B, special_entry.map(e => e.ppn(vpn, e.getData(vpn))).getOrElse(0.U), io.req.bits.vaddr >> pgIdxBits)) val mpu_physaddr = Cat(mpu_ppn, io.req.bits.vaddr(pgIdxBits-1, 0)) val mpu_priv = Mux[UInt](usingVM.B && (do_refill || io.req.bits.passthrough /* PTW */), PRV.S.U, Cat(io.ptw.status.debug, priv)) val pmp = Module(new PMPChecker(lgMaxSize)) pmp.io.addr := mpu_physaddr pmp.io.size := io.req.bits.size pmp.io.pmp := (io.ptw.pmp: Seq[PMP]) pmp.io.prv := mpu_priv val pma = Module(new PMAChecker(edge.manager)(p)) pma.io.paddr := mpu_physaddr // todo: using DataScratchpad doesn't support cacheable. val cacheable = pma.io.resp.cacheable && (instruction || !usingDataScratchpad).B val homogeneous = TLBPageLookup(edge.manager.managers, xLen, p(CacheBlockBytes), BigInt(1) << pgIdxBits, 1 << lgMaxSize)(mpu_physaddr).homogeneous // In M mode, if access DM address(debug module program buffer) val deny_access_to_debug = mpu_priv <= PRV.M.U && p(DebugModuleKey).map(dmp => dmp.address.contains(mpu_physaddr)).getOrElse(false.B) val prot_r = pma.io.resp.r && !deny_access_to_debug && pmp.io.r val prot_w = pma.io.resp.w && !deny_access_to_debug && pmp.io.w val prot_pp = pma.io.resp.pp val prot_al = pma.io.resp.al val prot_aa = pma.io.resp.aa val prot_x = pma.io.resp.x && !deny_access_to_debug && pmp.io.x val prot_eff = pma.io.resp.eff // hit check val sector_hits = sectored_entries(memIdx).map(_.sectorHit(vpn, priv_v)) val superpage_hits = superpage_entries.map(_.hit(vpn, priv_v)) val hitsVec = all_entries.map(vm_enabled && _.hit(vpn, priv_v)) val real_hits = hitsVec.asUInt val hits = Cat(!vm_enabled, real_hits) // use ptw response to refill // permission bit arrays when (do_refill) { val pte = io.ptw.resp.bits.pte val refill_v = r_vstage1_en || r_stage2_en val newEntry = Wire(new TLBEntryData) newEntry.ppn := pte.ppn newEntry.c := cacheable newEntry.u := pte.u newEntry.g := pte.g && pte.v newEntry.ae_ptw := io.ptw.resp.bits.ae_ptw newEntry.ae_final := io.ptw.resp.bits.ae_final newEntry.ae_stage2 := io.ptw.resp.bits.ae_final && io.ptw.resp.bits.gpa_is_pte && r_stage2_en newEntry.pf := io.ptw.resp.bits.pf newEntry.gf := io.ptw.resp.bits.gf newEntry.hr := io.ptw.resp.bits.hr newEntry.hw := io.ptw.resp.bits.hw newEntry.hx := io.ptw.resp.bits.hx newEntry.sr := pte.sr() newEntry.sw := pte.sw() newEntry.sx := pte.sx() newEntry.pr := prot_r newEntry.pw := prot_w newEntry.px := prot_x newEntry.ppp := prot_pp newEntry.pal := prot_al newEntry.paa := prot_aa newEntry.eff := prot_eff newEntry.fragmented_superpage := io.ptw.resp.bits.fragmented_superpage // refill special_entry when (special_entry.nonEmpty.B && !io.ptw.resp.bits.homogeneous) { special_entry.foreach(_.insert(r_refill_tag, refill_v, io.ptw.resp.bits.level, newEntry)) }.elsewhen (io.ptw.resp.bits.level < (pgLevels-1).U) { val waddr = Mux(r_superpage_hit.valid && usingHypervisor.B, r_superpage_hit.bits, r_superpage_repl_addr) for ((e, i) <- superpage_entries.zipWithIndex) when (r_superpage_repl_addr === i.U) { e.insert(r_refill_tag, refill_v, io.ptw.resp.bits.level, newEntry) when (invalidate_refill) { e.invalidate() } } // refill sectored_hit }.otherwise { val r_memIdx = r_refill_tag.extract(cfg.nSectors.log2 + cfg.nSets.log2 - 1, cfg.nSectors.log2) val waddr = Mux(r_sectored_hit.valid, r_sectored_hit.bits, r_sectored_repl_addr) for ((e, i) <- sectored_entries(r_memIdx).zipWithIndex) when (waddr === i.U) { when (!r_sectored_hit.valid) { e.invalidate() } e.insert(r_refill_tag, refill_v, 0.U, newEntry) when (invalidate_refill) { e.invalidate() } } } r_gpa_valid := io.ptw.resp.bits.gpa.valid r_gpa := io.ptw.resp.bits.gpa.bits r_gpa_is_pte := io.ptw.resp.bits.gpa_is_pte } // get all entries data. val entries = all_entries.map(_.getData(vpn)) val normal_entries = entries.take(ordinary_entries.size) // parallel query PPN from [[all_entries]], if VM not enabled return VPN instead val ppn = Mux1H(hitsVec :+ !vm_enabled, (all_entries zip entries).map{ case (entry, data) => entry.ppn(vpn, data) } :+ vpn(ppnBits-1, 0)) val nPhysicalEntries = 1 + special_entry.size // generally PTW misaligned load exception. val ptw_ae_array = Cat(false.B, entries.map(_.ae_ptw).asUInt) val final_ae_array = Cat(false.B, entries.map(_.ae_final).asUInt) val ptw_pf_array = Cat(false.B, entries.map(_.pf).asUInt) val ptw_gf_array = Cat(false.B, entries.map(_.gf).asUInt) val sum = Mux(priv_v, io.ptw.gstatus.sum, io.ptw.status.sum) // if in hypervisor/machine mode, cannot read/write user entries. // if in superviosr/user mode, "If the SUM bit in the sstatus register is set, supervisor mode software may also access pages with U=1.(from spec)" val priv_rw_ok = Mux(!priv_s || sum, entries.map(_.u).asUInt, 0.U) | Mux(priv_s, ~entries.map(_.u).asUInt, 0.U) // if in hypervisor/machine mode, other than user pages, all pages are executable. // if in superviosr/user mode, only user page can execute. val priv_x_ok = Mux(priv_s, ~entries.map(_.u).asUInt, entries.map(_.u).asUInt) val stage1_bypass = Fill(entries.size, usingHypervisor.B) & (Fill(entries.size, !stage1_en) | entries.map(_.ae_stage2).asUInt) val mxr = io.ptw.status.mxr | Mux(priv_v, io.ptw.gstatus.mxr, false.B) // "The vsstatus field MXR, which makes execute-only pages readable, only overrides VS-stage page protection.(from spec)" val r_array = Cat(true.B, (priv_rw_ok & (entries.map(_.sr).asUInt | Mux(mxr, entries.map(_.sx).asUInt, 0.U))) | stage1_bypass) val w_array = Cat(true.B, (priv_rw_ok & entries.map(_.sw).asUInt) | stage1_bypass) val x_array = Cat(true.B, (priv_x_ok & entries.map(_.sx).asUInt) | stage1_bypass) val stage2_bypass = Fill(entries.size, !stage2_en) val hr_array = Cat(true.B, entries.map(_.hr).asUInt | Mux(io.ptw.status.mxr, entries.map(_.hx).asUInt, 0.U) | stage2_bypass) val hw_array = Cat(true.B, entries.map(_.hw).asUInt | stage2_bypass) val hx_array = Cat(true.B, entries.map(_.hx).asUInt | stage2_bypass) // These array is for each TLB entries. // user mode can read: PMA OK, TLB OK, AE OK val pr_array = Cat(Fill(nPhysicalEntries, prot_r), normal_entries.map(_.pr).asUInt) & ~(ptw_ae_array | final_ae_array) // user mode can write: PMA OK, TLB OK, AE OK val pw_array = Cat(Fill(nPhysicalEntries, prot_w), normal_entries.map(_.pw).asUInt) & ~(ptw_ae_array | final_ae_array) // user mode can write: PMA OK, TLB OK, AE OK val px_array = Cat(Fill(nPhysicalEntries, prot_x), normal_entries.map(_.px).asUInt) & ~(ptw_ae_array | final_ae_array) // put effect val eff_array = Cat(Fill(nPhysicalEntries, prot_eff), normal_entries.map(_.eff).asUInt) // cacheable val c_array = Cat(Fill(nPhysicalEntries, cacheable), normal_entries.map(_.c).asUInt) // put partial val ppp_array = Cat(Fill(nPhysicalEntries, prot_pp), normal_entries.map(_.ppp).asUInt) // atomic arithmetic val paa_array = Cat(Fill(nPhysicalEntries, prot_aa), normal_entries.map(_.paa).asUInt) // atomic logic val pal_array = Cat(Fill(nPhysicalEntries, prot_al), normal_entries.map(_.pal).asUInt) val ppp_array_if_cached = ppp_array | c_array val paa_array_if_cached = paa_array | (if(usingAtomicsInCache) c_array else 0.U) val pal_array_if_cached = pal_array | (if(usingAtomicsInCache) c_array else 0.U) val prefetchable_array = Cat((cacheable && homogeneous) << (nPhysicalEntries-1), normal_entries.map(_.c).asUInt) // vaddr misaligned: vaddr[1:0]=b00 val misaligned = (io.req.bits.vaddr & (UIntToOH(io.req.bits.size) - 1.U)).orR def badVA(guestPA: Boolean): Bool = { val additionalPgLevels = (if (guestPA) io.ptw.hgatp else satp).additionalPgLevels val extraBits = if (guestPA) hypervisorExtraAddrBits else 0 val signed = !guestPA val nPgLevelChoices = pgLevels - minPgLevels + 1 val minVAddrBits = pgIdxBits + minPgLevels * pgLevelBits + extraBits (for (i <- 0 until nPgLevelChoices) yield { val mask = ((BigInt(1) << vaddrBitsExtended) - (BigInt(1) << (minVAddrBits + i * pgLevelBits - signed.toInt))).U val maskedVAddr = io.req.bits.vaddr & mask additionalPgLevels === i.U && !(maskedVAddr === 0.U || signed.B && maskedVAddr === mask) }).orR } val bad_gpa = if (!usingHypervisor) false.B else vm_enabled && !stage1_en && badVA(true) val bad_va = if (!usingVM || (minPgLevels == pgLevels && vaddrBits == vaddrBitsExtended)) false.B else vm_enabled && stage1_en && badVA(false) val cmd_lrsc = usingAtomics.B && io.req.bits.cmd.isOneOf(M_XLR, M_XSC) val cmd_amo_logical = usingAtomics.B && isAMOLogical(io.req.bits.cmd) val cmd_amo_arithmetic = usingAtomics.B && isAMOArithmetic(io.req.bits.cmd) val cmd_put_partial = io.req.bits.cmd === M_PWR val cmd_read = isRead(io.req.bits.cmd) val cmd_readx = usingHypervisor.B && io.req.bits.cmd === M_HLVX val cmd_write = isWrite(io.req.bits.cmd) val cmd_write_perms = cmd_write || io.req.bits.cmd.isOneOf(M_FLUSH_ALL, M_WOK) // not a write, but needs write permissions val lrscAllowed = Mux((usingDataScratchpad || usingAtomicsOnlyForIO).B, 0.U, c_array) val ae_array = Mux(misaligned, eff_array, 0.U) | Mux(cmd_lrsc, ~lrscAllowed, 0.U) // access exception needs SoC information from PMA val ae_ld_array = Mux(cmd_read, ae_array | ~pr_array, 0.U) val ae_st_array = Mux(cmd_write_perms, ae_array | ~pw_array, 0.U) | Mux(cmd_put_partial, ~ppp_array_if_cached, 0.U) | Mux(cmd_amo_logical, ~pal_array_if_cached, 0.U) | Mux(cmd_amo_arithmetic, ~paa_array_if_cached, 0.U) val must_alloc_array = Mux(cmd_put_partial, ~ppp_array, 0.U) | Mux(cmd_amo_logical, ~pal_array, 0.U) | Mux(cmd_amo_arithmetic, ~paa_array, 0.U) | Mux(cmd_lrsc, ~0.U(pal_array.getWidth.W), 0.U) val pf_ld_array = Mux(cmd_read, ((~Mux(cmd_readx, x_array, r_array) & ~ptw_ae_array) | ptw_pf_array) & ~ptw_gf_array, 0.U) val pf_st_array = Mux(cmd_write_perms, ((~w_array & ~ptw_ae_array) | ptw_pf_array) & ~ptw_gf_array, 0.U) val pf_inst_array = ((~x_array & ~ptw_ae_array) | ptw_pf_array) & ~ptw_gf_array val gf_ld_array = Mux(priv_v && cmd_read, (~Mux(cmd_readx, hx_array, hr_array) | ptw_gf_array) & ~ptw_ae_array, 0.U) val gf_st_array = Mux(priv_v && cmd_write_perms, (~hw_array | ptw_gf_array) & ~ptw_ae_array, 0.U) val gf_inst_array = Mux(priv_v, (~hx_array | ptw_gf_array) & ~ptw_ae_array, 0.U) val gpa_hits = { val need_gpa_mask = if (instruction) gf_inst_array else gf_ld_array | gf_st_array val hit_mask = Fill(ordinary_entries.size, r_gpa_valid && r_gpa_vpn === vpn) | Fill(all_entries.size, !vstage1_en) hit_mask | ~need_gpa_mask(all_entries.size-1, 0) } val tlb_hit_if_not_gpa_miss = real_hits.orR val tlb_hit = (real_hits & gpa_hits).orR // leads to s_request val tlb_miss = vm_enabled && !vsatp_mode_mismatch && !bad_va && !tlb_hit val sectored_plru = new SetAssocLRU(cfg.nSets, sectored_entries.head.size, "plru") val superpage_plru = new PseudoLRU(superpage_entries.size) when (io.req.valid && vm_enabled) { // replace when (sector_hits.orR) { sectored_plru.access(memIdx, OHToUInt(sector_hits)) } when (superpage_hits.orR) { superpage_plru.access(OHToUInt(superpage_hits)) } } // Superpages create the possibility that two entries in the TLB may match. // This corresponds to a software bug, but we can't return complete garbage; // we must return either the old translation or the new translation. This // isn't compatible with the Mux1H approach. So, flush the TLB and report // a miss on duplicate entries. val multipleHits = PopCountAtLeast(real_hits, 2) // only pull up req.ready when this is s_ready state. io.req.ready := state === s_ready // page fault io.resp.pf.ld := (bad_va && cmd_read) || (pf_ld_array & hits).orR io.resp.pf.st := (bad_va && cmd_write_perms) || (pf_st_array & hits).orR io.resp.pf.inst := bad_va || (pf_inst_array & hits).orR // guest page fault io.resp.gf.ld := (bad_gpa && cmd_read) || (gf_ld_array & hits).orR io.resp.gf.st := (bad_gpa && cmd_write_perms) || (gf_st_array & hits).orR io.resp.gf.inst := bad_gpa || (gf_inst_array & hits).orR // access exception io.resp.ae.ld := (ae_ld_array & hits).orR io.resp.ae.st := (ae_st_array & hits).orR io.resp.ae.inst := (~px_array & hits).orR // misaligned io.resp.ma.ld := misaligned && cmd_read io.resp.ma.st := misaligned && cmd_write io.resp.ma.inst := false.B // this is up to the pipeline to figure out io.resp.cacheable := (c_array & hits).orR io.resp.must_alloc := (must_alloc_array & hits).orR io.resp.prefetchable := (prefetchable_array & hits).orR && edge.manager.managers.forall(m => !m.supportsAcquireB || m.supportsHint).B io.resp.miss := do_refill || vsatp_mode_mismatch || tlb_miss || multipleHits io.resp.paddr := Cat(ppn, io.req.bits.vaddr(pgIdxBits-1, 0)) io.resp.size := io.req.bits.size io.resp.cmd := io.req.bits.cmd io.resp.gpa_is_pte := vstage1_en && r_gpa_is_pte io.resp.gpa := { val page = Mux(!vstage1_en, Cat(bad_gpa, vpn), r_gpa >> pgIdxBits) val offset = Mux(io.resp.gpa_is_pte, r_gpa(pgIdxBits-1, 0), io.req.bits.vaddr(pgIdxBits-1, 0)) Cat(page, offset) } io.ptw.req.valid := state === s_request io.ptw.req.bits.valid := !io.kill io.ptw.req.bits.bits.addr := r_refill_tag io.ptw.req.bits.bits.vstage1 := r_vstage1_en io.ptw.req.bits.bits.stage2 := r_stage2_en io.ptw.req.bits.bits.need_gpa := r_need_gpa if (usingVM) { when(io.ptw.req.fire && io.ptw.req.bits.valid) { r_gpa_valid := false.B r_gpa_vpn := r_refill_tag } val sfence = io.sfence.valid // this is [[s_ready]] // handle miss/hit at the first cycle. // if miss, request PTW(L2TLB). when (io.req.fire && tlb_miss) { state := s_request r_refill_tag := vpn r_need_gpa := tlb_hit_if_not_gpa_miss r_vstage1_en := vstage1_en r_stage2_en := stage2_en r_superpage_repl_addr := replacementEntry(superpage_entries, superpage_plru.way) r_sectored_repl_addr := replacementEntry(sectored_entries(memIdx), sectored_plru.way(memIdx)) r_sectored_hit.valid := sector_hits.orR r_sectored_hit.bits := OHToUInt(sector_hits) r_superpage_hit.valid := superpage_hits.orR r_superpage_hit.bits := OHToUInt(superpage_hits) } // Handle SFENCE.VMA when send request to PTW. // SFENCE.VMA io.ptw.req.ready kill // ? ? 1 // 0 0 0 // 0 1 0 -> s_wait // 1 0 0 -> s_wait_invalidate // 1 0 0 -> s_ready when (state === s_request) { // SFENCE.VMA will kill TLB entries based on rs1 and rs2. It will take 1 cycle. when (sfence) { state := s_ready } // here should be io.ptw.req.fire, but assert(io.ptw.req.ready === true.B) // fire -> s_wait when (io.ptw.req.ready) { state := Mux(sfence, s_wait_invalidate, s_wait) } // If CPU kills request(frontend.s2_redirect) when (io.kill) { state := s_ready } } // sfence in refill will results in invalidate when (state === s_wait && sfence) { state := s_wait_invalidate } // after CPU acquire response, go back to s_ready. when (io.ptw.resp.valid) { state := s_ready } // SFENCE processing logic. when (sfence) { assert(!io.sfence.bits.rs1 || (io.sfence.bits.addr >> pgIdxBits) === vpn) for (e <- all_real_entries) { val hv = usingHypervisor.B && io.sfence.bits.hv val hg = usingHypervisor.B && io.sfence.bits.hg when (!hg && io.sfence.bits.rs1) { e.invalidateVPN(vpn, hv) } .elsewhen (!hg && io.sfence.bits.rs2) { e.invalidateNonGlobal(hv) } .otherwise { e.invalidate(hv || hg) } } } when(io.req.fire && vsatp_mode_mismatch) { all_real_entries.foreach(_.invalidate(true.B)) v_entries_use_stage1 := vstage1_en } when (multipleHits || reset.asBool) { all_real_entries.foreach(_.invalidate()) } ccover(io.ptw.req.fire, "MISS", "TLB miss") ccover(io.ptw.req.valid && !io.ptw.req.ready, "PTW_STALL", "TLB miss, but PTW busy") ccover(state === s_wait_invalidate, "SFENCE_DURING_REFILL", "flush TLB during TLB refill") ccover(sfence && !io.sfence.bits.rs1 && !io.sfence.bits.rs2, "SFENCE_ALL", "flush TLB") ccover(sfence && !io.sfence.bits.rs1 && io.sfence.bits.rs2, "SFENCE_ASID", "flush TLB ASID") ccover(sfence && io.sfence.bits.rs1 && !io.sfence.bits.rs2, "SFENCE_LINE", "flush TLB line") ccover(sfence && io.sfence.bits.rs1 && io.sfence.bits.rs2, "SFENCE_LINE_ASID", "flush TLB line/ASID") ccover(multipleHits, "MULTIPLE_HITS", "Two matching translations in TLB") } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = property.cover(cond, s"${if (instruction) "I" else "D"}TLB_$label", "MemorySystem;;" + desc) /** Decides which entry to be replaced * * If there is a invalid entry, replace it with priorityencoder; * if not, replace the alt entry * * @return mask for TLBEntry replacement */ def replacementEntry(set: Seq[TLBEntry], alt: UInt) = { val valids = set.map(_.valid.orR).asUInt Mux(valids.andR, alt, PriorityEncoder(~valids)) } } File TLBPermissions.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes, RegionType, AddressDecoder} import freechips.rocketchip.tilelink.TLManagerParameters case class TLBPermissions( homogeneous: Bool, // if false, the below are undefined r: Bool, // readable w: Bool, // writeable x: Bool, // executable c: Bool, // cacheable a: Bool, // arithmetic ops l: Bool) // logical ops object TLBPageLookup { private case class TLBFixedPermissions( e: Boolean, // get-/put-effects r: Boolean, // readable w: Boolean, // writeable x: Boolean, // executable c: Boolean, // cacheable a: Boolean, // arithmetic ops l: Boolean) { // logical ops val useful = r || w || x || c || a || l } private def groupRegions(managers: Seq[TLManagerParameters]): Map[TLBFixedPermissions, Seq[AddressSet]] = { val permissions = managers.map { m => (m.address, TLBFixedPermissions( e = Seq(RegionType.PUT_EFFECTS, RegionType.GET_EFFECTS) contains m.regionType, r = m.supportsGet || m.supportsAcquireB, // if cached, never uses Get w = m.supportsPutFull || m.supportsAcquireT, // if cached, never uses Put x = m.executable, c = m.supportsAcquireB, a = m.supportsArithmetic, l = m.supportsLogical)) } permissions .filter(_._2.useful) // get rid of no-permission devices .groupBy(_._2) // group by permission type .mapValues(seq => AddressSet.unify(seq.flatMap(_._1))) // coalesce same-permission regions .toMap } // Unmapped memory is considered to be inhomogeneous def apply(managers: Seq[TLManagerParameters], xLen: Int, cacheBlockBytes: Int, pageSize: BigInt, maxRequestBytes: Int): UInt => TLBPermissions = { require (isPow2(xLen) && xLen >= 8) require (isPow2(cacheBlockBytes) && cacheBlockBytes >= xLen/8) require (isPow2(pageSize) && pageSize >= cacheBlockBytes) val xferSizes = TransferSizes(cacheBlockBytes, cacheBlockBytes) val allSizes = TransferSizes(1, maxRequestBytes) val amoSizes = TransferSizes(4, xLen/8) val permissions = managers.foreach { m => require (!m.supportsGet || m.supportsGet .contains(allSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsGet} Get, but must support ${allSizes}") require (!m.supportsPutFull || m.supportsPutFull .contains(allSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsPutFull} PutFull, but must support ${allSizes}") require (!m.supportsPutPartial || m.supportsPutPartial.contains(allSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsPutPartial} PutPartial, but must support ${allSizes}") require (!m.supportsAcquireB || m.supportsAcquireB .contains(xferSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsAcquireB} AcquireB, but must support ${xferSizes}") require (!m.supportsAcquireT || m.supportsAcquireT .contains(xferSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsAcquireT} AcquireT, but must support ${xferSizes}") require (!m.supportsLogical || m.supportsLogical .contains(amoSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsLogical} Logical, but must support ${amoSizes}") require (!m.supportsArithmetic || m.supportsArithmetic.contains(amoSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsArithmetic} Arithmetic, but must support ${amoSizes}") require (!(m.supportsAcquireB && m.supportsPutFull && !m.supportsAcquireT), s"Memory region '${m.name}' supports AcquireB (cached read) and PutFull (un-cached write) but not AcquireT (cached write)") } val grouped = groupRegions(managers) .mapValues(_.filter(_.alignment >= pageSize)) // discard any region that's not big enough def lowCostProperty(prop: TLBFixedPermissions => Boolean): UInt => Bool = { val (yesm, nom) = grouped.partition { case (k, eq) => prop(k) } val (yes, no) = (yesm.values.flatten.toList, nom.values.flatten.toList) // Find the minimal bits needed to distinguish between yes and no val decisionMask = AddressDecoder(Seq(yes, no)) def simplify(x: Seq[AddressSet]) = AddressSet.unify(x.map(_.widen(~decisionMask)).distinct) val (yesf, nof) = (simplify(yes), simplify(no)) if (yesf.size < no.size) { (x: UInt) => yesf.map(_.contains(x)).foldLeft(false.B)(_ || _) } else { (x: UInt) => !nof.map(_.contains(x)).foldLeft(false.B)(_ || _) } } // Derive simplified property circuits (don't care when !homo) val rfn = lowCostProperty(_.r) val wfn = lowCostProperty(_.w) val xfn = lowCostProperty(_.x) val cfn = lowCostProperty(_.c) val afn = lowCostProperty(_.a) val lfn = lowCostProperty(_.l) val homo = AddressSet.unify(grouped.values.flatten.toList) (x: UInt) => TLBPermissions( homogeneous = homo.map(_.contains(x)).foldLeft(false.B)(_ || _), r = rfn(x), w = wfn(x), x = xfn(x), c = cfn(x), a = afn(x), l = lfn(x)) } // Are all pageSize intervals of mapped regions homogeneous? def homogeneous(managers: Seq[TLManagerParameters], pageSize: BigInt): Boolean = { groupRegions(managers).values.forall(_.forall(_.alignment >= pageSize)) } } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File PTW.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.{Arbiter, Cat, Decoupled, Enum, Mux1H, OHToUInt, PopCount, PriorityEncoder, PriorityEncoderOH, RegEnable, UIntToOH, Valid, is, isPow2, log2Ceil, switch} import chisel3.withClock import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.subsystem.CacheBlockBytes import freechips.rocketchip.tile._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property import scala.collection.mutable.ListBuffer /** PTE request from TLB to PTW * * TLB send a PTE request to PTW when L1TLB miss */ class PTWReq(implicit p: Parameters) extends CoreBundle()(p) { val addr = UInt(vpnBits.W) val need_gpa = Bool() val vstage1 = Bool() val stage2 = Bool() } /** PTE info from L2TLB to TLB * * containing: target PTE, exceptions, two-satge tanslation info */ class PTWResp(implicit p: Parameters) extends CoreBundle()(p) { /** ptw access exception */ val ae_ptw = Bool() /** final access exception */ val ae_final = Bool() /** page fault */ val pf = Bool() /** guest page fault */ val gf = Bool() /** hypervisor read */ val hr = Bool() /** hypervisor write */ val hw = Bool() /** hypervisor execute */ val hx = Bool() /** PTE to refill L1TLB * * source: L2TLB */ val pte = new PTE /** pte pglevel */ val level = UInt(log2Ceil(pgLevels).W) /** fragmented_superpage support */ val fragmented_superpage = Bool() /** homogeneous for both pma and pmp */ val homogeneous = Bool() val gpa = Valid(UInt(vaddrBits.W)) val gpa_is_pte = Bool() } /** IO between TLB and PTW * * PTW receives : * - PTE request * - CSRs info * - pmp results from PMP(in TLB) */ class TLBPTWIO(implicit p: Parameters) extends CoreBundle()(p) with HasCoreParameters { val req = Decoupled(Valid(new PTWReq)) val resp = Flipped(Valid(new PTWResp)) val ptbr = Input(new PTBR()) val hgatp = Input(new PTBR()) val vsatp = Input(new PTBR()) val status = Input(new MStatus()) val hstatus = Input(new HStatus()) val gstatus = Input(new MStatus()) val pmp = Input(Vec(nPMPs, new PMP)) val customCSRs = Flipped(coreParams.customCSRs) } /** PTW performance statistics */ class PTWPerfEvents extends Bundle { val l2miss = Bool() val l2hit = Bool() val pte_miss = Bool() val pte_hit = Bool() } /** Datapath IO between PTW and Core * * PTW receives CSRs info, pmp checks, sfence instruction info * * PTW sends its performance statistics to core */ class DatapathPTWIO(implicit p: Parameters) extends CoreBundle()(p) with HasCoreParameters { val ptbr = Input(new PTBR()) val hgatp = Input(new PTBR()) val vsatp = Input(new PTBR()) val sfence = Flipped(Valid(new SFenceReq)) val status = Input(new MStatus()) val hstatus = Input(new HStatus()) val gstatus = Input(new MStatus()) val pmp = Input(Vec(nPMPs, new PMP)) val perf = Output(new PTWPerfEvents()) val customCSRs = Flipped(coreParams.customCSRs) /** enable clock generated by ptw */ val clock_enabled = Output(Bool()) } /** PTE template for transmission * * contains useful methods to check PTE attributes * @see RV-priv spec 4.3.1 for pgae table entry format */ class PTE(implicit p: Parameters) extends CoreBundle()(p) { val reserved_for_future = UInt(10.W) val ppn = UInt(44.W) val reserved_for_software = Bits(2.W) /** dirty bit */ val d = Bool() /** access bit */ val a = Bool() /** global mapping */ val g = Bool() /** user mode accessible */ val u = Bool() /** whether the page is executable */ val x = Bool() /** whether the page is writable */ val w = Bool() /** whether the page is readable */ val r = Bool() /** valid bit */ val v = Bool() /** return true if find a pointer to next level page table */ def table(dummy: Int = 0) = v && !r && !w && !x && !d && !a && !u && reserved_for_future === 0.U /** return true if find a leaf PTE */ def leaf(dummy: Int = 0) = v && (r || (x && !w)) && a /** user read */ def ur(dummy: Int = 0) = sr() && u /** user write*/ def uw(dummy: Int = 0) = sw() && u /** user execute */ def ux(dummy: Int = 0) = sx() && u /** supervisor read */ def sr(dummy: Int = 0) = leaf() && r /** supervisor write */ def sw(dummy: Int = 0) = leaf() && w && d /** supervisor execute */ def sx(dummy: Int = 0) = leaf() && x /** full permission: writable and executable in user mode */ def isFullPerm(dummy: Int = 0) = uw() && ux() } /** L2TLB PTE template * * contains tag bits * @param nSets number of sets in L2TLB * @see RV-priv spec 4.3.1 for page table entry format */ class L2TLBEntry(nSets: Int)(implicit p: Parameters) extends CoreBundle()(p) with HasCoreParameters { val idxBits = log2Ceil(nSets) val tagBits = maxSVAddrBits - pgIdxBits - idxBits + (if (usingHypervisor) 1 else 0) val tag = UInt(tagBits.W) val ppn = UInt(ppnBits.W) /** dirty bit */ val d = Bool() /** access bit */ val a = Bool() /** user mode accessible */ val u = Bool() /** whether the page is executable */ val x = Bool() /** whether the page is writable */ val w = Bool() /** whether the page is readable */ val r = Bool() } /** PTW contains L2TLB, and performs page table walk for high level TLB, and cache queries from L1 TLBs(I$, D$, RoCC) * * It performs hierarchy page table query to mem for the desired leaf PTE and cache them in l2tlb. * Besides leaf PTEs, it also caches non-leaf PTEs in pte_cache to accerlerate the process. * * ==Structure== * - l2tlb : for leaf PTEs * - set-associative (configurable with [[CoreParams.nL2TLBEntries]]and [[CoreParams.nL2TLBWays]])) * - PLRU * - pte_cache: for non-leaf PTEs * - set-associative * - LRU * - s2_pte_cache: for non-leaf PTEs in 2-stage translation * - set-associative * - PLRU * * l2tlb Pipeline: 3 stage * {{{ * stage 0 : read * stage 1 : decode * stage 2 : hit check * }}} * ==State Machine== * s_ready: ready to reveive request from TLB * s_req: request mem; pte_cache hit judge * s_wait1: deal with l2tlb error * s_wait2: final hit judge * s_wait3: receive mem response * s_fragment_superpage: for superpage PTE * * @note l2tlb hit happens in s_req or s_wait1 * @see RV-priv spec 4.3-4.6 for Virtual-Memory System * @see RV-priv spec 8.5 for Two-Stage Address Translation * @todo details in two-stage translation */ class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(p) { val io = IO(new Bundle { /** to n TLB */ val requestor = Flipped(Vec(n, new TLBPTWIO)) /** to HellaCache */ val mem = new HellaCacheIO /** to Core * * contains CSRs info and performance statistics */ val dpath = new DatapathPTWIO }) val s_ready :: s_req :: s_wait1 :: s_dummy1 :: s_wait2 :: s_wait3 :: s_dummy2 :: s_fragment_superpage :: Nil = Enum(8) val state = RegInit(s_ready) val l2_refill_wire = Wire(Bool()) /** Arbiter to arbite request from n TLB */ val arb = Module(new Arbiter(Valid(new PTWReq), n)) // use TLB req as arbitor's input arb.io.in <> io.requestor.map(_.req) // receive req only when s_ready and not in refill arb.io.out.ready := (state === s_ready) && !l2_refill_wire val resp_valid = RegNext(VecInit(Seq.fill(io.requestor.size)(false.B))) val clock_en = state =/= s_ready || l2_refill_wire || arb.io.out.valid || io.dpath.sfence.valid || io.dpath.customCSRs.disableDCacheClockGate io.dpath.clock_enabled := usingVM.B && clock_en val gated_clock = if (!usingVM || !tileParams.dcache.get.clockGate) clock else ClockGate(clock, clock_en, "ptw_clock_gate") withClock (gated_clock) { // entering gated-clock domain val invalidated = Reg(Bool()) /** current PTE level * {{{ * 0 <= count <= pgLevel-1 * count = pgLevel - 1 : leaf PTE * count < pgLevel - 1 : non-leaf PTE * }}} */ val count = Reg(UInt(log2Ceil(pgLevels).W)) val resp_ae_ptw = Reg(Bool()) val resp_ae_final = Reg(Bool()) val resp_pf = Reg(Bool()) val resp_gf = Reg(Bool()) val resp_hr = Reg(Bool()) val resp_hw = Reg(Bool()) val resp_hx = Reg(Bool()) val resp_fragmented_superpage = Reg(Bool()) /** tlb request */ val r_req = Reg(new PTWReq) /** current selected way in arbitor */ val r_req_dest = Reg(Bits()) // to respond to L1TLB : l2_hit // to construct mem.req.addr val r_pte = Reg(new PTE) val r_hgatp = Reg(new PTBR) // 2-stage pageLevel val aux_count = Reg(UInt(log2Ceil(pgLevels).W)) /** pte for 2-stage translation */ val aux_pte = Reg(new PTE) val gpa_pgoff = Reg(UInt(pgIdxBits.W)) // only valid in resp_gf case val stage2 = Reg(Bool()) val stage2_final = Reg(Bool()) val satp = Mux(arb.io.out.bits.bits.vstage1, io.dpath.vsatp, io.dpath.ptbr) val r_hgatp_initial_count = pgLevels.U - minPgLevels.U - r_hgatp.additionalPgLevels /** 2-stage translation both enable */ val do_both_stages = r_req.vstage1 && r_req.stage2 val max_count = count max aux_count val vpn = Mux(r_req.vstage1 && stage2, aux_pte.ppn, r_req.addr) val mem_resp_valid = RegNext(io.mem.resp.valid) val mem_resp_data = RegNext(io.mem.resp.bits.data) io.mem.uncached_resp.map { resp => assert(!(resp.valid && io.mem.resp.valid)) resp.ready := true.B when (resp.valid) { mem_resp_valid := true.B mem_resp_data := resp.bits.data } } // construct pte from mem.resp val (pte, invalid_paddr, invalid_gpa) = { val tmp = mem_resp_data.asTypeOf(new PTE()) val res = WireDefault(tmp) res.ppn := Mux(do_both_stages && !stage2, tmp.ppn(vpnBits.min(tmp.ppn.getWidth)-1, 0), tmp.ppn(ppnBits-1, 0)) when (tmp.r || tmp.w || tmp.x) { // for superpage mappings, make sure PPN LSBs are zero for (i <- 0 until pgLevels-1) when (count <= i.U && tmp.ppn((pgLevels-1-i)*pgLevelBits-1, (pgLevels-2-i)*pgLevelBits) =/= 0.U) { res.v := false.B } } (res, Mux(do_both_stages && !stage2, (tmp.ppn >> vpnBits) =/= 0.U, (tmp.ppn >> ppnBits) =/= 0.U), do_both_stages && !stage2 && checkInvalidHypervisorGPA(r_hgatp, tmp.ppn)) } // find non-leaf PTE, need traverse val traverse = pte.table() && !invalid_paddr && !invalid_gpa && count < (pgLevels-1).U /** address send to mem for enquerry */ val pte_addr = if (!usingVM) 0.U else { val vpn_idxs = (0 until pgLevels).map { i => val width = pgLevelBits + (if (i <= pgLevels - minPgLevels) hypervisorExtraAddrBits else 0) (vpn >> (pgLevels - i - 1) * pgLevelBits)(width - 1, 0) } val mask = Mux(stage2 && count === r_hgatp_initial_count, ((1 << (hypervisorExtraAddrBits + pgLevelBits)) - 1).U, ((1 << pgLevelBits) - 1).U) val vpn_idx = vpn_idxs(count) & mask val raw_pte_addr = ((r_pte.ppn << pgLevelBits) | vpn_idx) << log2Ceil(xLen / 8) val size = if (usingHypervisor) vaddrBits else paddrBits //use r_pte.ppn as page table base address //use vpn slice as offset raw_pte_addr.apply(size.min(raw_pte_addr.getWidth) - 1, 0) } /** stage2_pte_cache input addr */ val stage2_pte_cache_addr = if (!usingHypervisor) 0.U else { val vpn_idxs = (0 until pgLevels - 1).map { i => (r_req.addr >> (pgLevels - i - 1) * pgLevelBits)(pgLevelBits - 1, 0) } val vpn_idx = vpn_idxs(aux_count) val raw_s2_pte_cache_addr = Cat(aux_pte.ppn, vpn_idx) << log2Ceil(xLen / 8) raw_s2_pte_cache_addr(vaddrBits.min(raw_s2_pte_cache_addr.getWidth) - 1, 0) } def makeFragmentedSuperpagePPN(ppn: UInt): Seq[UInt] = { (pgLevels-1 until 0 by -1).map(i => Cat(ppn >> (pgLevelBits*i), r_req.addr(((pgLevelBits*i) min vpnBits)-1, 0).padTo(pgLevelBits*i))) } /** PTECache caches non-leaf PTE * @param s2 true: 2-stage address translation */ def makePTECache(s2: Boolean): (Bool, UInt) = if (coreParams.nPTECacheEntries == 0) { (false.B, 0.U) } else { val plru = new PseudoLRU(coreParams.nPTECacheEntries) val valid = RegInit(0.U(coreParams.nPTECacheEntries.W)) val tags = Reg(Vec(coreParams.nPTECacheEntries, UInt((if (usingHypervisor) 1 + vaddrBits else paddrBits).W))) // not include full pte, only ppn val data = Reg(Vec(coreParams.nPTECacheEntries, UInt((if (usingHypervisor && s2) vpnBits else ppnBits).W))) val can_hit = if (s2) count === r_hgatp_initial_count && aux_count < (pgLevels-1).U && r_req.vstage1 && stage2 && !stage2_final else count < (pgLevels-1).U && Mux(r_req.vstage1, stage2, !r_req.stage2) val can_refill = if (s2) do_both_stages && !stage2 && !stage2_final else can_hit val tag = if (s2) Cat(true.B, stage2_pte_cache_addr.padTo(vaddrBits)) else Cat(r_req.vstage1, pte_addr.padTo(if (usingHypervisor) vaddrBits else paddrBits)) val hits = tags.map(_ === tag).asUInt & valid val hit = hits.orR && can_hit // refill with mem response when (mem_resp_valid && traverse && can_refill && !hits.orR && !invalidated) { val r = Mux(valid.andR, plru.way, PriorityEncoder(~valid)) valid := valid | UIntToOH(r) tags(r) := tag data(r) := pte.ppn plru.access(r) } // replace when (hit && state === s_req) { plru.access(OHToUInt(hits)) } when (io.dpath.sfence.valid && (!io.dpath.sfence.bits.rs1 || usingHypervisor.B && io.dpath.sfence.bits.hg)) { valid := 0.U } val lcount = if (s2) aux_count else count for (i <- 0 until pgLevels-1) { ccover(hit && state === s_req && lcount === i.U, s"PTE_CACHE_HIT_L$i", s"PTE cache hit, level $i") } (hit, Mux1H(hits, data)) } // generate pte_cache val (pte_cache_hit, pte_cache_data) = makePTECache(false) // generate pte_cache with 2-stage translation val (stage2_pte_cache_hit, stage2_pte_cache_data) = makePTECache(true) // pte_cache hit or 2-stage pte_cache hit val pte_hit = RegNext(false.B) io.dpath.perf.pte_miss := false.B io.dpath.perf.pte_hit := pte_hit && (state === s_req) && !io.dpath.perf.l2hit assert(!(io.dpath.perf.l2hit && (io.dpath.perf.pte_miss || io.dpath.perf.pte_hit)), "PTE Cache Hit/Miss Performance Monitor Events are lower priority than L2TLB Hit event") // l2_refill happens when find the leaf pte val l2_refill = RegNext(false.B) l2_refill_wire := l2_refill io.dpath.perf.l2miss := false.B io.dpath.perf.l2hit := false.B // l2tlb val (l2_hit, l2_error, l2_pte, l2_tlb_ram) = if (coreParams.nL2TLBEntries == 0) (false.B, false.B, WireDefault(0.U.asTypeOf(new PTE)), None) else { val code = new ParityCode require(isPow2(coreParams.nL2TLBEntries)) require(isPow2(coreParams.nL2TLBWays)) require(coreParams.nL2TLBEntries >= coreParams.nL2TLBWays) val nL2TLBSets = coreParams.nL2TLBEntries / coreParams.nL2TLBWays require(isPow2(nL2TLBSets)) val idxBits = log2Ceil(nL2TLBSets) val l2_plru = new SetAssocLRU(nL2TLBSets, coreParams.nL2TLBWays, "plru") val ram = DescribedSRAM( name = "l2_tlb_ram", desc = "L2 TLB", size = nL2TLBSets, data = Vec(coreParams.nL2TLBWays, UInt(code.width(new L2TLBEntry(nL2TLBSets).getWidth).W)) ) val g = Reg(Vec(coreParams.nL2TLBWays, UInt(nL2TLBSets.W))) val valid = RegInit(VecInit(Seq.fill(coreParams.nL2TLBWays)(0.U(nL2TLBSets.W)))) // use r_req to construct tag val (r_tag, r_idx) = Split(Cat(r_req.vstage1, r_req.addr(maxSVAddrBits-pgIdxBits-1, 0)), idxBits) /** the valid vec for the selected set(including n ways) */ val r_valid_vec = valid.map(_(r_idx)).asUInt val r_valid_vec_q = Reg(UInt(coreParams.nL2TLBWays.W)) val r_l2_plru_way = Reg(UInt(log2Ceil(coreParams.nL2TLBWays max 1).W)) r_valid_vec_q := r_valid_vec // replacement way r_l2_plru_way := (if (coreParams.nL2TLBWays > 1) l2_plru.way(r_idx) else 0.U) // refill with r_pte(leaf pte) when (l2_refill && !invalidated) { val entry = Wire(new L2TLBEntry(nL2TLBSets)) entry.ppn := r_pte.ppn entry.d := r_pte.d entry.a := r_pte.a entry.u := r_pte.u entry.x := r_pte.x entry.w := r_pte.w entry.r := r_pte.r entry.tag := r_tag // if all the way are valid, use plru to select one way to be replaced, // otherwise use PriorityEncoderOH to select one val wmask = if (coreParams.nL2TLBWays > 1) Mux(r_valid_vec_q.andR, UIntToOH(r_l2_plru_way, coreParams.nL2TLBWays), PriorityEncoderOH(~r_valid_vec_q)) else 1.U(1.W) ram.write(r_idx, VecInit(Seq.fill(coreParams.nL2TLBWays)(code.encode(entry.asUInt))), wmask.asBools) val mask = UIntToOH(r_idx) for (way <- 0 until coreParams.nL2TLBWays) { when (wmask(way)) { valid(way) := valid(way) | mask g(way) := Mux(r_pte.g, g(way) | mask, g(way) & ~mask) } } } // sfence happens when (io.dpath.sfence.valid) { val hg = usingHypervisor.B && io.dpath.sfence.bits.hg for (way <- 0 until coreParams.nL2TLBWays) { valid(way) := Mux(!hg && io.dpath.sfence.bits.rs1, valid(way) & ~UIntToOH(io.dpath.sfence.bits.addr(idxBits+pgIdxBits-1, pgIdxBits)), Mux(!hg && io.dpath.sfence.bits.rs2, valid(way) & g(way), 0.U)) } } val s0_valid = !l2_refill && arb.io.out.fire val s0_suitable = arb.io.out.bits.bits.vstage1 === arb.io.out.bits.bits.stage2 && !arb.io.out.bits.bits.need_gpa val s1_valid = RegNext(s0_valid && s0_suitable && arb.io.out.bits.valid) val s2_valid = RegNext(s1_valid) // read from tlb idx val s1_rdata = ram.read(arb.io.out.bits.bits.addr(idxBits-1, 0), s0_valid) val s2_rdata = s1_rdata.map(s1_rdway => code.decode(RegEnable(s1_rdway, s1_valid))) val s2_valid_vec = RegEnable(r_valid_vec, s1_valid) val s2_g_vec = RegEnable(VecInit(g.map(_(r_idx))), s1_valid) val s2_error = (0 until coreParams.nL2TLBWays).map(way => s2_valid_vec(way) && s2_rdata(way).error).orR when (s2_valid && s2_error) { valid.foreach { _ := 0.U }} // decode val s2_entry_vec = s2_rdata.map(_.uncorrected.asTypeOf(new L2TLBEntry(nL2TLBSets))) val s2_hit_vec = (0 until coreParams.nL2TLBWays).map(way => s2_valid_vec(way) && (r_tag === s2_entry_vec(way).tag)) val s2_hit = s2_valid && s2_hit_vec.orR io.dpath.perf.l2miss := s2_valid && !(s2_hit_vec.orR) io.dpath.perf.l2hit := s2_hit when (s2_hit) { l2_plru.access(r_idx, OHToUInt(s2_hit_vec)) assert((PopCount(s2_hit_vec) === 1.U) || s2_error, "L2 TLB multi-hit") } val s2_pte = Wire(new PTE) val s2_hit_entry = Mux1H(s2_hit_vec, s2_entry_vec) s2_pte.ppn := s2_hit_entry.ppn s2_pte.d := s2_hit_entry.d s2_pte.a := s2_hit_entry.a s2_pte.g := Mux1H(s2_hit_vec, s2_g_vec) s2_pte.u := s2_hit_entry.u s2_pte.x := s2_hit_entry.x s2_pte.w := s2_hit_entry.w s2_pte.r := s2_hit_entry.r s2_pte.v := true.B s2_pte.reserved_for_future := 0.U s2_pte.reserved_for_software := 0.U for (way <- 0 until coreParams.nL2TLBWays) { ccover(s2_hit && s2_hit_vec(way), s"L2_TLB_HIT_WAY$way", s"L2 TLB hit way$way") } (s2_hit, s2_error, s2_pte, Some(ram)) } // if SFENCE occurs during walk, don't refill PTE cache or L2 TLB until next walk invalidated := io.dpath.sfence.valid || (invalidated && state =/= s_ready) // mem request io.mem.keep_clock_enabled := false.B io.mem.req.valid := state === s_req || state === s_dummy1 io.mem.req.bits.phys := true.B io.mem.req.bits.cmd := M_XRD io.mem.req.bits.size := log2Ceil(xLen/8).U io.mem.req.bits.signed := false.B io.mem.req.bits.addr := pte_addr io.mem.req.bits.idx.foreach(_ := pte_addr) io.mem.req.bits.dprv := PRV.S.U // PTW accesses are S-mode by definition io.mem.req.bits.dv := do_both_stages && !stage2 io.mem.req.bits.tag := DontCare io.mem.req.bits.no_resp := false.B io.mem.req.bits.no_alloc := DontCare io.mem.req.bits.no_xcpt := DontCare io.mem.req.bits.data := DontCare io.mem.req.bits.mask := DontCare io.mem.s1_kill := l2_hit || (state =/= s_wait1) || resp_gf io.mem.s1_data := DontCare io.mem.s2_kill := false.B val pageGranularityPMPs = pmpGranularity >= (1 << pgIdxBits) require(!usingHypervisor || pageGranularityPMPs, s"hypervisor requires pmpGranularity >= ${1<<pgIdxBits}") val pmaPgLevelHomogeneous = (0 until pgLevels) map { i => val pgSize = BigInt(1) << (pgIdxBits + ((pgLevels - 1 - i) * pgLevelBits)) if (pageGranularityPMPs && i == pgLevels - 1) { require(TLBPageLookup.homogeneous(edge.manager.managers, pgSize), s"All memory regions must be $pgSize-byte aligned") true.B } else { TLBPageLookup(edge.manager.managers, xLen, p(CacheBlockBytes), pgSize, xLen/8)(r_pte.ppn << pgIdxBits).homogeneous } } val pmaHomogeneous = pmaPgLevelHomogeneous(count) val pmpHomogeneous = new PMPHomogeneityChecker(io.dpath.pmp).apply(r_pte.ppn << pgIdxBits, count) val homogeneous = pmaHomogeneous && pmpHomogeneous // response to tlb for (i <- 0 until io.requestor.size) { io.requestor(i).resp.valid := resp_valid(i) io.requestor(i).resp.bits.ae_ptw := resp_ae_ptw io.requestor(i).resp.bits.ae_final := resp_ae_final io.requestor(i).resp.bits.pf := resp_pf io.requestor(i).resp.bits.gf := resp_gf io.requestor(i).resp.bits.hr := resp_hr io.requestor(i).resp.bits.hw := resp_hw io.requestor(i).resp.bits.hx := resp_hx io.requestor(i).resp.bits.pte := r_pte io.requestor(i).resp.bits.level := max_count io.requestor(i).resp.bits.homogeneous := homogeneous || pageGranularityPMPs.B io.requestor(i).resp.bits.fragmented_superpage := resp_fragmented_superpage && pageGranularityPMPs.B io.requestor(i).resp.bits.gpa.valid := r_req.need_gpa io.requestor(i).resp.bits.gpa.bits := Cat(Mux(!stage2_final || !r_req.vstage1 || aux_count === (pgLevels - 1).U, aux_pte.ppn, makeFragmentedSuperpagePPN(aux_pte.ppn)(aux_count)), gpa_pgoff) io.requestor(i).resp.bits.gpa_is_pte := !stage2_final io.requestor(i).ptbr := io.dpath.ptbr io.requestor(i).hgatp := io.dpath.hgatp io.requestor(i).vsatp := io.dpath.vsatp io.requestor(i).customCSRs <> io.dpath.customCSRs io.requestor(i).status := io.dpath.status io.requestor(i).hstatus := io.dpath.hstatus io.requestor(i).gstatus := io.dpath.gstatus io.requestor(i).pmp := io.dpath.pmp } // control state machine val next_state = WireDefault(state) state := OptimizationBarrier(next_state) val do_switch = WireDefault(false.B) switch (state) { is (s_ready) { when (arb.io.out.fire) { val satp_initial_count = pgLevels.U - minPgLevels.U - satp.additionalPgLevels val vsatp_initial_count = pgLevels.U - minPgLevels.U - io.dpath.vsatp.additionalPgLevels val hgatp_initial_count = pgLevels.U - minPgLevels.U - io.dpath.hgatp.additionalPgLevels val aux_ppn = Mux(arb.io.out.bits.bits.vstage1, io.dpath.vsatp.ppn, arb.io.out.bits.bits.addr) r_req := arb.io.out.bits.bits r_req_dest := arb.io.chosen next_state := Mux(arb.io.out.bits.valid, s_req, s_ready) stage2 := arb.io.out.bits.bits.stage2 stage2_final := arb.io.out.bits.bits.stage2 && !arb.io.out.bits.bits.vstage1 count := Mux(arb.io.out.bits.bits.stage2, hgatp_initial_count, satp_initial_count) aux_count := Mux(arb.io.out.bits.bits.vstage1, vsatp_initial_count, 0.U) aux_pte.ppn := aux_ppn aux_pte.reserved_for_future := 0.U resp_ae_ptw := false.B resp_ae_final := false.B resp_pf := false.B resp_gf := checkInvalidHypervisorGPA(io.dpath.hgatp, aux_ppn) && arb.io.out.bits.bits.stage2 resp_hr := true.B resp_hw := true.B resp_hx := true.B resp_fragmented_superpage := false.B r_hgatp := io.dpath.hgatp assert(!arb.io.out.bits.bits.need_gpa || arb.io.out.bits.bits.stage2) } } is (s_req) { when(stage2 && count === r_hgatp_initial_count) { gpa_pgoff := Mux(aux_count === (pgLevels-1).U, r_req.addr << (xLen/8).log2, stage2_pte_cache_addr) } // pte_cache hit when (stage2_pte_cache_hit) { aux_count := aux_count + 1.U aux_pte.ppn := stage2_pte_cache_data aux_pte.reserved_for_future := 0.U pte_hit := true.B }.elsewhen (pte_cache_hit) { count := count + 1.U pte_hit := true.B }.otherwise { next_state := Mux(io.mem.req.ready, s_wait1, s_req) } when(resp_gf) { next_state := s_ready resp_valid(r_req_dest) := true.B } } is (s_wait1) { // This Mux is for the l2_error case; the l2_hit && !l2_error case is overriden below next_state := Mux(l2_hit, s_req, s_wait2) } is (s_wait2) { next_state := s_wait3 io.dpath.perf.pte_miss := count < (pgLevels-1).U when (io.mem.s2_xcpt.ae.ld) { resp_ae_ptw := true.B next_state := s_ready resp_valid(r_req_dest) := true.B } } is (s_fragment_superpage) { next_state := s_ready resp_valid(r_req_dest) := true.B when (!homogeneous) { count := (pgLevels-1).U resp_fragmented_superpage := true.B } when (do_both_stages) { resp_fragmented_superpage := true.B } } } val merged_pte = { val superpage_masks = (0 until pgLevels).map(i => ((BigInt(1) << pte.ppn.getWidth) - (BigInt(1) << (pgLevels-1-i)*pgLevelBits)).U) val superpage_mask = superpage_masks(Mux(stage2_final, max_count, (pgLevels-1).U)) val stage1_ppns = (0 until pgLevels-1).map(i => Cat(pte.ppn(pte.ppn.getWidth-1, (pgLevels-i-1)*pgLevelBits), aux_pte.ppn((pgLevels-i-1)*pgLevelBits-1,0))) :+ pte.ppn val stage1_ppn = stage1_ppns(count) makePTE(stage1_ppn & superpage_mask, aux_pte) } r_pte := OptimizationBarrier( // l2tlb hit->find a leaf PTE(l2_pte), respond to L1TLB Mux(l2_hit && !l2_error && !resp_gf, l2_pte, // S2 PTE cache hit -> proceed to the next level of walking, update the r_pte with hgatp Mux(state === s_req && stage2_pte_cache_hit, makeHypervisorRootPTE(r_hgatp, stage2_pte_cache_data, l2_pte), // pte cache hit->find a non-leaf PTE(pte_cache),continue to request mem Mux(state === s_req && pte_cache_hit, makePTE(pte_cache_data, l2_pte), // 2-stage translation Mux(do_switch, makeHypervisorRootPTE(r_hgatp, pte.ppn, r_pte), // when mem respond, store mem.resp.pte Mux(mem_resp_valid, Mux(!traverse && r_req.vstage1 && stage2, merged_pte, pte), // fragment_superpage Mux(state === s_fragment_superpage && !homogeneous && count =/= (pgLevels - 1).U, makePTE(makeFragmentedSuperpagePPN(r_pte.ppn)(count), r_pte), // when tlb request come->request mem, use root address in satp(or vsatp,hgatp) Mux(arb.io.out.fire, Mux(arb.io.out.bits.bits.stage2, makeHypervisorRootPTE(io.dpath.hgatp, io.dpath.vsatp.ppn, r_pte), makePTE(satp.ppn, r_pte)), r_pte)))))))) when (l2_hit && !l2_error && !resp_gf) { assert(state === s_req || state === s_wait1) next_state := s_ready resp_valid(r_req_dest) := true.B count := (pgLevels-1).U } when (mem_resp_valid) { assert(state === s_wait3) next_state := s_req when (traverse) { when (do_both_stages && !stage2) { do_switch := true.B } count := count + 1.U }.otherwise { val gf = (stage2 && !stage2_final && !pte.ur()) || (pte.leaf() && pte.reserved_for_future === 0.U && invalid_gpa) val ae = pte.v && invalid_paddr val pf = pte.v && pte.reserved_for_future =/= 0.U val success = pte.v && !ae && !pf && !gf when (do_both_stages && !stage2_final && success) { when (stage2) { stage2 := false.B count := aux_count }.otherwise { stage2_final := true.B do_switch := true.B } }.otherwise { // find a leaf pte, start l2 refill l2_refill := success && count === (pgLevels-1).U && !r_req.need_gpa && (!r_req.vstage1 && !r_req.stage2 || do_both_stages && aux_count === (pgLevels-1).U && pte.isFullPerm()) count := max_count when (pageGranularityPMPs.B && !(count === (pgLevels-1).U && (!do_both_stages || aux_count === (pgLevels-1).U))) { next_state := s_fragment_superpage }.otherwise { next_state := s_ready resp_valid(r_req_dest) := true.B } resp_ae_ptw := ae && count < (pgLevels-1).U && pte.table() resp_ae_final := ae && pte.leaf() resp_pf := pf && !stage2 resp_gf := gf || (pf && stage2) resp_hr := !stage2 || (!pf && !gf && pte.ur()) resp_hw := !stage2 || (!pf && !gf && pte.uw()) resp_hx := !stage2 || (!pf && !gf && pte.ux()) } } } when (io.mem.s2_nack) { assert(state === s_wait2) next_state := s_req } when (do_switch) { aux_count := Mux(traverse, count + 1.U, count) count := r_hgatp_initial_count aux_pte := Mux(traverse, pte, { val s1_ppns = (0 until pgLevels-1).map(i => Cat(pte.ppn(pte.ppn.getWidth-1, (pgLevels-i-1)*pgLevelBits), r_req.addr(((pgLevels-i-1)*pgLevelBits min vpnBits)-1,0).padTo((pgLevels-i-1)*pgLevelBits))) :+ pte.ppn makePTE(s1_ppns(count), pte) }) stage2 := true.B } for (i <- 0 until pgLevels) { val leaf = mem_resp_valid && !traverse && count === i.U ccover(leaf && pte.v && !invalid_paddr && !invalid_gpa && pte.reserved_for_future === 0.U, s"L$i", s"successful page-table access, level $i") ccover(leaf && pte.v && invalid_paddr, s"L${i}_BAD_PPN_MSB", s"PPN too large, level $i") ccover(leaf && pte.v && invalid_gpa, s"L${i}_BAD_GPA_MSB", s"GPA too large, level $i") ccover(leaf && pte.v && pte.reserved_for_future =/= 0.U, s"L${i}_BAD_RSV_MSB", s"reserved MSBs set, level $i") ccover(leaf && !mem_resp_data(0), s"L${i}_INVALID_PTE", s"page not present, level $i") if (i != pgLevels-1) ccover(leaf && !pte.v && mem_resp_data(0), s"L${i}_BAD_PPN_LSB", s"PPN LSBs not zero, level $i") } ccover(mem_resp_valid && count === (pgLevels-1).U && pte.table(), s"TOO_DEEP", s"page table too deep") ccover(io.mem.s2_nack, "NACK", "D$ nacked page-table access") ccover(state === s_wait2 && io.mem.s2_xcpt.ae.ld, "AE", "access exception while walking page table") } // leaving gated-clock domain private def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = if (usingVM) property.cover(cond, s"PTW_$label", "MemorySystem;;" + desc) /** Relace PTE.ppn with ppn */ private def makePTE(ppn: UInt, default: PTE) = { val pte = WireDefault(default) pte.ppn := ppn pte } /** use hgatp and vpn to construct a new ppn */ private def makeHypervisorRootPTE(hgatp: PTBR, vpn: UInt, default: PTE) = { val count = pgLevels.U - minPgLevels.U - hgatp.additionalPgLevels val idxs = (0 to pgLevels-minPgLevels).map(i => (vpn >> (pgLevels-i)*pgLevelBits)) val lsbs = WireDefault(UInt(maxHypervisorExtraAddrBits.W), idxs(count)) val pte = WireDefault(default) pte.ppn := Cat(hgatp.ppn >> maxHypervisorExtraAddrBits, lsbs) pte } /** use hgatp and vpn to check for gpa out of range */ private def checkInvalidHypervisorGPA(hgatp: PTBR, vpn: UInt) = { val count = pgLevels.U - minPgLevels.U - hgatp.additionalPgLevels val idxs = (0 to pgLevels-minPgLevels).map(i => (vpn >> ((pgLevels-i)*pgLevelBits)+maxHypervisorExtraAddrBits)) idxs.extract(count) =/= 0.U } } /** Mix-ins for constructing tiles that might have a PTW */ trait CanHavePTW extends HasTileParameters with HasHellaCache { this: BaseTile => val module: CanHavePTWModule var nPTWPorts = 1 nDCachePorts += usingPTW.toInt } trait CanHavePTWModule extends HasHellaCacheModule { val outer: CanHavePTW val ptwPorts = ListBuffer(outer.dcache.module.io.ptw) val ptw = Module(new PTW(outer.nPTWPorts)(outer.dcache.node.edges.out(0), outer.p)) ptw.io.mem <> DontCare if (outer.usingPTW) { dcachePorts += ptw.io.mem } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File DCache.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import freechips.rocketchip.amba.AMBAProt import freechips.rocketchip.diplomacy.{BufferParams} import freechips.rocketchip.prci.{ClockCrossingType, RationalCrossing, SynchronousCrossing, AsynchronousCrossing, CreditedCrossing} import freechips.rocketchip.tile.{CoreBundle, LookupByHartId} import freechips.rocketchip.tilelink.{TLFIFOFixer,ClientMetadata, TLBundleA, TLAtomics, TLBundleB, TLPermissions} import freechips.rocketchip.tilelink.TLMessages.{AccessAck, HintAck, AccessAckData, Grant, GrantData, ReleaseAck} import freechips.rocketchip.util.{CanHaveErrors, ClockGate, IdentityCode, ReplacementPolicy, DescribedSRAM, property} import freechips.rocketchip.util.BooleanToAugmentedBoolean import freechips.rocketchip.util.UIntToAugmentedUInt import freechips.rocketchip.util.UIntIsOneOf import freechips.rocketchip.util.IntToAugmentedInt import freechips.rocketchip.util.SeqToAugmentedSeq import freechips.rocketchip.util.SeqBoolBitwiseOps // TODO: delete this trait once deduplication is smart enough to avoid globally inlining matching circuits trait InlineInstance { self: chisel3.experimental.BaseModule => chisel3.experimental.annotate( new chisel3.experimental.ChiselAnnotation { def toFirrtl: firrtl.annotations.Annotation = firrtl.passes.InlineAnnotation(self.toNamed) } ) } class DCacheErrors(implicit p: Parameters) extends L1HellaCacheBundle()(p) with CanHaveErrors { val correctable = (cacheParams.tagCode.canCorrect || cacheParams.dataCode.canCorrect).option(Valid(UInt(paddrBits.W))) val uncorrectable = (cacheParams.tagCode.canDetect || cacheParams.dataCode.canDetect).option(Valid(UInt(paddrBits.W))) val bus = Valid(UInt(paddrBits.W)) } class DCacheDataReq(implicit p: Parameters) extends L1HellaCacheBundle()(p) { val addr = UInt(untagBits.W) val write = Bool() val wdata = UInt((encBits * rowBytes / eccBytes).W) val wordMask = UInt((rowBytes / subWordBytes).W) val eccMask = UInt((wordBytes / eccBytes).W) val way_en = UInt(nWays.W) } class DCacheDataArray(implicit p: Parameters) extends L1HellaCacheModule()(p) { val io = IO(new Bundle { val req = Flipped(Valid(new DCacheDataReq)) val resp = Output(Vec(nWays, UInt((req.bits.wdata.getWidth).W))) }) require(rowBits % subWordBits == 0, "rowBits must be a multiple of subWordBits") val eccMask = if (eccBits == subWordBits) Seq(true.B) else io.req.bits.eccMask.asBools val wMask = if (nWays == 1) eccMask else (0 until nWays).flatMap(i => eccMask.map(_ && io.req.bits.way_en(i))) val wWords = io.req.bits.wdata.grouped(encBits * (subWordBits / eccBits)) val addr = io.req.bits.addr >> rowOffBits val data_arrays = Seq.tabulate(rowBits / subWordBits) { i => DescribedSRAM( name = s"${tileParams.baseName}_dcache_data_arrays_${i}", desc = "DCache Data Array", size = nSets * cacheBlockBytes / rowBytes, data = Vec(nWays * (subWordBits / eccBits), UInt(encBits.W)) ) } val rdata = for ((array , i) <- data_arrays.zipWithIndex) yield { val valid = io.req.valid && ((data_arrays.size == 1).B || io.req.bits.wordMask(i)) when (valid && io.req.bits.write) { val wMaskSlice = (0 until wMask.size).filter(j => i % (wordBits/subWordBits) == (j % (wordBytes/eccBytes)) / (subWordBytes/eccBytes)).map(wMask(_)) val wData = wWords(i).grouped(encBits) array.write(addr, VecInit((0 until nWays).flatMap(i => wData)), wMaskSlice) } val data = array.read(addr, valid && !io.req.bits.write) data.grouped(subWordBits / eccBits).map(_.asUInt).toSeq } (io.resp zip rdata.transpose).foreach { case (resp, data) => resp := data.asUInt } } class DCacheMetadataReq(implicit p: Parameters) extends L1HellaCacheBundle()(p) { val write = Bool() val addr = UInt(vaddrBitsExtended.W) val idx = UInt(idxBits.W) val way_en = UInt(nWays.W) val data = UInt(cacheParams.tagCode.width(new L1Metadata().getWidth).W) } class DCache(staticIdForMetadataUseOnly: Int, val crossing: ClockCrossingType)(implicit p: Parameters) extends HellaCache(staticIdForMetadataUseOnly)(p) { override lazy val module = new DCacheModule(this) } class DCacheTLBPort(implicit p: Parameters) extends CoreBundle()(p) { val req = Flipped(Decoupled(new TLBReq(coreDataBytes.log2))) val s1_resp = Output(new TLBResp(coreDataBytes.log2)) val s2_kill = Input(Bool()) } class DCacheModule(outer: DCache) extends HellaCacheModule(outer) { val tECC = cacheParams.tagCode val dECC = cacheParams.dataCode require(subWordBits % eccBits == 0, "subWordBits must be a multiple of eccBits") require(eccBytes == 1 || !dECC.isInstanceOf[IdentityCode]) require(cacheParams.silentDrop || cacheParams.acquireBeforeRelease, "!silentDrop requires acquireBeforeRelease") val usingRMW = eccBytes > 1 || usingAtomicsInCache val mmioOffset = outer.firstMMIO edge.manager.requireFifo(TLFIFOFixer.allVolatile) // TileLink pipelining MMIO requests val clock_en_reg = Reg(Bool()) io.cpu.clock_enabled := clock_en_reg val gated_clock = if (!cacheParams.clockGate) clock else ClockGate(clock, clock_en_reg, "dcache_clock_gate") class DCacheModuleImpl { // entering gated-clock domain val tlb = Module(new TLB(false, log2Ceil(coreDataBytes), TLBConfig(nTLBSets, nTLBWays, cacheParams.nTLBBasePageSectors, cacheParams.nTLBSuperpages))) val pma_checker = Module(new TLB(false, log2Ceil(coreDataBytes), TLBConfig(nTLBSets, nTLBWays, cacheParams.nTLBBasePageSectors, cacheParams.nTLBSuperpages)) with InlineInstance) // tags val replacer = ReplacementPolicy.fromString(cacheParams.replacementPolicy, nWays) /** Metadata Arbiter: * 0: Tag update on reset * 1: Tag update on ECC error * 2: Tag update on hit * 3: Tag update on refill * 4: Tag update on release * 5: Tag update on flush * 6: Tag update on probe * 7: Tag update on CPU request */ val metaArb = Module(new Arbiter(new DCacheMetadataReq, 8) with InlineInstance) val tag_array = DescribedSRAM( name = s"${tileParams.baseName}_dcache_tag_array", desc = "DCache Tag Array", size = nSets, data = Vec(nWays, chiselTypeOf(metaArb.io.out.bits.data)) ) // data val data = Module(new DCacheDataArray) /** Data Arbiter * 0: data from pending store buffer * 1: data from TL-D refill * 2: release to TL-A * 3: hit path to CPU */ val dataArb = Module(new Arbiter(new DCacheDataReq, 4) with InlineInstance) dataArb.io.in.tail.foreach(_.bits.wdata := dataArb.io.in.head.bits.wdata) // tie off write ports by default data.io.req.bits <> dataArb.io.out.bits data.io.req.valid := dataArb.io.out.valid dataArb.io.out.ready := true.B metaArb.io.out.ready := clock_en_reg val tl_out_a = Wire(chiselTypeOf(tl_out.a)) tl_out.a <> { val a_queue_depth = outer.crossing match { case RationalCrossing(_) => // TODO make this depend on the actual ratio? if (cacheParams.separateUncachedResp) (maxUncachedInFlight + 1) / 2 else 2 min maxUncachedInFlight-1 case SynchronousCrossing(BufferParams.none) => 1 // Need some buffering to guarantee livelock freedom case SynchronousCrossing(_) => 0 // Adequate buffering within the crossing case _: AsynchronousCrossing => 0 // Adequate buffering within the crossing case _: CreditedCrossing => 0 // Adequate buffering within the crossing } Queue(tl_out_a, a_queue_depth, flow = true) } val (tl_out_c, release_queue_empty) = if (cacheParams.acquireBeforeRelease) { val q = Module(new Queue(chiselTypeOf(tl_out.c.bits), cacheDataBeats, flow = true)) tl_out.c <> q.io.deq (q.io.enq, q.io.count === 0.U) } else { (tl_out.c, true.B) } val s1_valid = RegNext(io.cpu.req.fire, false.B) val s1_probe = RegNext(tl_out.b.fire, false.B) val probe_bits = RegEnable(tl_out.b.bits, tl_out.b.fire) // TODO has data now :( val s1_nack = WireDefault(false.B) val s1_valid_masked = s1_valid && !io.cpu.s1_kill val s1_valid_not_nacked = s1_valid && !s1_nack val s1_tlb_req_valid = RegNext(io.tlb_port.req.fire, false.B) val s2_tlb_req_valid = RegNext(s1_tlb_req_valid, false.B) val s0_clk_en = metaArb.io.out.valid && !metaArb.io.out.bits.write val s0_req = WireInit(io.cpu.req.bits) s0_req.addr := Cat(metaArb.io.out.bits.addr >> blockOffBits, io.cpu.req.bits.addr(blockOffBits-1,0)) s0_req.idx.foreach(_ := Cat(metaArb.io.out.bits.idx, s0_req.addr(blockOffBits-1, 0))) when (!metaArb.io.in(7).ready) { s0_req.phys := true.B } val s1_req = RegEnable(s0_req, s0_clk_en) val s1_vaddr = Cat(s1_req.idx.getOrElse(s1_req.addr) >> tagLSB, s1_req.addr(tagLSB-1, 0)) val s0_tlb_req = WireInit(io.tlb_port.req.bits) when (!io.tlb_port.req.fire) { s0_tlb_req.passthrough := s0_req.phys s0_tlb_req.vaddr := s0_req.addr s0_tlb_req.size := s0_req.size s0_tlb_req.cmd := s0_req.cmd s0_tlb_req.prv := s0_req.dprv s0_tlb_req.v := s0_req.dv } val s1_tlb_req = RegEnable(s0_tlb_req, s0_clk_en || io.tlb_port.req.valid) val s1_read = isRead(s1_req.cmd) val s1_write = isWrite(s1_req.cmd) val s1_readwrite = s1_read || s1_write val s1_sfence = s1_req.cmd === M_SFENCE || s1_req.cmd === M_HFENCEV || s1_req.cmd === M_HFENCEG val s1_flush_line = s1_req.cmd === M_FLUSH_ALL && s1_req.size(0) val s1_flush_valid = Reg(Bool()) val s1_waw_hazard = Wire(Bool()) val s_ready :: s_voluntary_writeback :: s_probe_rep_dirty :: s_probe_rep_clean :: s_probe_retry :: s_probe_rep_miss :: s_voluntary_write_meta :: s_probe_write_meta :: s_dummy :: s_voluntary_release :: Nil = Enum(10) val supports_flush = outer.flushOnFenceI || coreParams.haveCFlush val flushed = RegInit(true.B) val flushing = RegInit(false.B) val flushing_req = Reg(chiselTypeOf(s1_req)) val cached_grant_wait = RegInit(false.B) val resetting = RegInit(false.B) val flushCounter = RegInit((nSets * (nWays-1)).U(log2Ceil(nSets * nWays).W)) val release_ack_wait = RegInit(false.B) val release_ack_addr = Reg(UInt(paddrBits.W)) val release_state = RegInit(s_ready) val refill_way = Reg(UInt()) val any_pstore_valid = Wire(Bool()) val inWriteback = release_state.isOneOf(s_voluntary_writeback, s_probe_rep_dirty) val releaseWay = Wire(UInt()) io.cpu.req.ready := (release_state === s_ready) && !cached_grant_wait && !s1_nack // I/O MSHRs val uncachedInFlight = RegInit(VecInit(Seq.fill(maxUncachedInFlight)(false.B))) val uncachedReqs = Reg(Vec(maxUncachedInFlight, new HellaCacheReq)) val uncachedResp = WireInit(new HellaCacheReq, DontCare) // hit initiation path val s0_read = isRead(io.cpu.req.bits.cmd) dataArb.io.in(3).valid := io.cpu.req.valid && likelyNeedsRead(io.cpu.req.bits) dataArb.io.in(3).bits := dataArb.io.in(1).bits dataArb.io.in(3).bits.write := false.B dataArb.io.in(3).bits.addr := Cat(io.cpu.req.bits.idx.getOrElse(io.cpu.req.bits.addr) >> tagLSB, io.cpu.req.bits.addr(tagLSB-1, 0)) dataArb.io.in(3).bits.wordMask := { val mask = (subWordBytes.log2 until rowOffBits).foldLeft(1.U) { case (in, i) => val upper_mask = Mux((i >= wordBytes.log2).B || io.cpu.req.bits.size <= i.U, 0.U, ((BigInt(1) << (1 << (i - subWordBytes.log2)))-1).U) val upper = Mux(io.cpu.req.bits.addr(i), in, 0.U) | upper_mask val lower = Mux(io.cpu.req.bits.addr(i), 0.U, in) upper ## lower } Fill(subWordBytes / eccBytes, mask) } dataArb.io.in(3).bits.eccMask := ~0.U((wordBytes / eccBytes).W) dataArb.io.in(3).bits.way_en := ~0.U(nWays.W) when (!dataArb.io.in(3).ready && s0_read) { io.cpu.req.ready := false.B } val s1_did_read = RegEnable(dataArb.io.in(3).ready && (io.cpu.req.valid && needsRead(io.cpu.req.bits)), s0_clk_en) val s1_read_mask = RegEnable(dataArb.io.in(3).bits.wordMask, s0_clk_en) metaArb.io.in(7).valid := io.cpu.req.valid metaArb.io.in(7).bits.write := false.B metaArb.io.in(7).bits.idx := dataArb.io.in(3).bits.addr(idxMSB, idxLSB) metaArb.io.in(7).bits.addr := io.cpu.req.bits.addr metaArb.io.in(7).bits.way_en := metaArb.io.in(4).bits.way_en metaArb.io.in(7).bits.data := metaArb.io.in(4).bits.data when (!metaArb.io.in(7).ready) { io.cpu.req.ready := false.B } // address translation val s1_cmd_uses_tlb = s1_readwrite || s1_flush_line || s1_req.cmd === M_WOK io.ptw <> tlb.io.ptw tlb.io.kill := io.cpu.s2_kill || s2_tlb_req_valid && io.tlb_port.s2_kill tlb.io.req.valid := s1_tlb_req_valid || s1_valid && !io.cpu.s1_kill && s1_cmd_uses_tlb tlb.io.req.bits := s1_tlb_req when (!tlb.io.req.ready && !tlb.io.ptw.resp.valid && !io.cpu.req.bits.phys) { io.cpu.req.ready := false.B } when (!s1_tlb_req_valid && s1_valid && s1_cmd_uses_tlb && tlb.io.resp.miss) { s1_nack := true.B } tlb.io.sfence.valid := s1_valid && !io.cpu.s1_kill && s1_sfence tlb.io.sfence.bits.rs1 := s1_req.size(0) tlb.io.sfence.bits.rs2 := s1_req.size(1) tlb.io.sfence.bits.asid := io.cpu.s1_data.data tlb.io.sfence.bits.addr := s1_req.addr tlb.io.sfence.bits.hv := s1_req.cmd === M_HFENCEV tlb.io.sfence.bits.hg := s1_req.cmd === M_HFENCEG io.tlb_port.req.ready := clock_en_reg io.tlb_port.s1_resp := tlb.io.resp when (s1_tlb_req_valid && s1_valid && !(s1_req.phys && s1_req.no_xcpt)) { s1_nack := true.B } pma_checker.io <> DontCare pma_checker.io.req.bits.passthrough := true.B pma_checker.io.req.bits.vaddr := s1_req.addr pma_checker.io.req.bits.size := s1_req.size pma_checker.io.req.bits.cmd := s1_req.cmd pma_checker.io.req.bits.prv := s1_req.dprv pma_checker.io.req.bits.v := s1_req.dv val s1_paddr = Cat(Mux(s1_tlb_req_valid, s1_req.addr(paddrBits-1, pgIdxBits), tlb.io.resp.paddr >> pgIdxBits), s1_req.addr(pgIdxBits-1, 0)) val s1_victim_way = Wire(UInt()) val (s1_hit_way, s1_hit_state, s1_meta) = if (usingDataScratchpad) { val baseAddr = p(LookupByHartId)(_.dcache.flatMap(_.scratch.map(_.U)), io_hartid.get) | io_mmio_address_prefix.get val inScratchpad = s1_paddr >= baseAddr && s1_paddr < baseAddr + (nSets * cacheBlockBytes).U val hitState = Mux(inScratchpad, ClientMetadata.maximum, ClientMetadata.onReset) val dummyMeta = L1Metadata(0.U, ClientMetadata.onReset) (inScratchpad, hitState, Seq(tECC.encode(dummyMeta.asUInt))) } else { val metaReq = metaArb.io.out val metaIdx = metaReq.bits.idx when (metaReq.valid && metaReq.bits.write) { val wmask = if (nWays == 1) Seq(true.B) else metaReq.bits.way_en.asBools tag_array.write(metaIdx, VecInit(Seq.fill(nWays)(metaReq.bits.data)), wmask) } val s1_meta = tag_array.read(metaIdx, metaReq.valid && !metaReq.bits.write) val s1_meta_uncorrected = s1_meta.map(tECC.decode(_).uncorrected.asTypeOf(new L1Metadata)) val s1_tag = s1_paddr >> tagLSB val s1_meta_hit_way = s1_meta_uncorrected.map(r => r.coh.isValid() && r.tag === s1_tag).asUInt val s1_meta_hit_state = ( s1_meta_uncorrected.map(r => Mux(r.tag === s1_tag && !s1_flush_valid, r.coh.asUInt, 0.U)) .reduce (_|_)).asTypeOf(chiselTypeOf(ClientMetadata.onReset)) (s1_meta_hit_way, s1_meta_hit_state, s1_meta) } val s1_data_way = WireDefault(if (nWays == 1) 1.U else Mux(inWriteback, releaseWay, s1_hit_way)) val tl_d_data_encoded = Wire(chiselTypeOf(encodeData(tl_out.d.bits.data, false.B))) val s1_all_data_ways = VecInit(data.io.resp ++ (!cacheParams.separateUncachedResp).option(tl_d_data_encoded)) val s1_mask_xwr = new StoreGen(s1_req.size, s1_req.addr, 0.U, wordBytes).mask val s1_mask = Mux(s1_req.cmd === M_PWR, io.cpu.s1_data.mask, s1_mask_xwr) // for partial writes, s1_data.mask must be a subset of s1_mask_xwr assert(!(s1_valid_masked && s1_req.cmd === M_PWR) || (s1_mask_xwr | ~io.cpu.s1_data.mask).andR) val s2_valid = RegNext(s1_valid_masked && !s1_sfence, init=false.B) val s2_valid_no_xcpt = s2_valid && !io.cpu.s2_xcpt.asUInt.orR val s2_probe = RegNext(s1_probe, init=false.B) val releaseInFlight = s1_probe || s2_probe || release_state =/= s_ready val s2_not_nacked_in_s1 = RegNext(!s1_nack) val s2_valid_not_nacked_in_s1 = s2_valid && s2_not_nacked_in_s1 val s2_valid_masked = s2_valid_no_xcpt && s2_not_nacked_in_s1 val s2_valid_not_killed = s2_valid_masked && !io.cpu.s2_kill val s2_req = Reg(chiselTypeOf(io.cpu.req.bits)) val s2_cmd_flush_all = s2_req.cmd === M_FLUSH_ALL && !s2_req.size(0) val s2_cmd_flush_line = s2_req.cmd === M_FLUSH_ALL && s2_req.size(0) val s2_tlb_xcpt = Reg(chiselTypeOf(tlb.io.resp)) val s2_pma = Reg(chiselTypeOf(tlb.io.resp)) val s2_uncached_resp_addr = Reg(chiselTypeOf(s2_req.addr)) // should be DCE'd in synthesis when (s1_valid_not_nacked || s1_flush_valid) { s2_req := s1_req s2_req.addr := s1_paddr s2_tlb_xcpt := tlb.io.resp s2_pma := Mux(s1_tlb_req_valid, pma_checker.io.resp, tlb.io.resp) } val s2_vaddr = Cat(RegEnable(s1_vaddr, s1_valid_not_nacked || s1_flush_valid) >> tagLSB, s2_req.addr(tagLSB-1, 0)) val s2_read = isRead(s2_req.cmd) val s2_write = isWrite(s2_req.cmd) val s2_readwrite = s2_read || s2_write val s2_flush_valid_pre_tag_ecc = RegNext(s1_flush_valid) val s1_meta_decoded = s1_meta.map(tECC.decode(_)) val s1_meta_clk_en = s1_valid_not_nacked || s1_flush_valid || s1_probe val s2_meta_correctable_errors = s1_meta_decoded.map(m => RegEnable(m.correctable, s1_meta_clk_en)).asUInt val s2_meta_uncorrectable_errors = s1_meta_decoded.map(m => RegEnable(m.uncorrectable, s1_meta_clk_en)).asUInt val s2_meta_error_uncorrectable = s2_meta_uncorrectable_errors.orR val s2_meta_corrected = s1_meta_decoded.map(m => RegEnable(m.corrected, s1_meta_clk_en).asTypeOf(new L1Metadata)) val s2_meta_error = (s2_meta_uncorrectable_errors | s2_meta_correctable_errors).orR val s2_flush_valid = s2_flush_valid_pre_tag_ecc && !s2_meta_error val s2_data = { val wordsPerRow = rowBits / subWordBits val en = s1_valid || inWriteback || io.cpu.replay_next val word_en = Mux(inWriteback, Fill(wordsPerRow, 1.U), Mux(s1_did_read, s1_read_mask, 0.U)) val s1_way_words = s1_all_data_ways.map(_.grouped(dECC.width(eccBits) * (subWordBits / eccBits))) if (cacheParams.pipelineWayMux) { val s1_word_en = Mux(io.cpu.replay_next, 0.U, word_en) (for (i <- 0 until wordsPerRow) yield { val s2_way_en = RegEnable(Mux(s1_word_en(i), s1_data_way, 0.U), en) val s2_way_words = (0 until nWays).map(j => RegEnable(s1_way_words(j)(i), en && word_en(i))) (0 until nWays).map(j => Mux(s2_way_en(j), s2_way_words(j), 0.U)).reduce(_|_) }).asUInt } else { val s1_word_en = Mux(!io.cpu.replay_next, word_en, UIntToOH(uncachedResp.addr.extract(log2Up(rowBits/8)-1, log2Up(wordBytes)), wordsPerRow)) (for (i <- 0 until wordsPerRow) yield { RegEnable(Mux1H(Mux(s1_word_en(i), s1_data_way, 0.U), s1_way_words.map(_(i))), en) }).asUInt } } val s2_probe_way = RegEnable(s1_hit_way, s1_probe) val s2_probe_state = RegEnable(s1_hit_state, s1_probe) val s2_hit_way = RegEnable(s1_hit_way, s1_valid_not_nacked) val s2_hit_state = RegEnable(s1_hit_state, s1_valid_not_nacked || s1_flush_valid) val s2_waw_hazard = RegEnable(s1_waw_hazard, s1_valid_not_nacked) val s2_store_merge = Wire(Bool()) val s2_hit_valid = s2_hit_state.isValid() val (s2_hit, s2_grow_param, s2_new_hit_state) = s2_hit_state.onAccess(s2_req.cmd) val s2_data_decoded = decodeData(s2_data) val s2_word_idx = s2_req.addr.extract(log2Up(rowBits/8)-1, log2Up(wordBytes)) val s2_data_error = s2_data_decoded.map(_.error).orR val s2_data_error_uncorrectable = s2_data_decoded.map(_.uncorrectable).orR val s2_data_corrected = (s2_data_decoded.map(_.corrected): Seq[UInt]).asUInt val s2_data_uncorrected = (s2_data_decoded.map(_.uncorrected): Seq[UInt]).asUInt val s2_valid_hit_maybe_flush_pre_data_ecc_and_waw = s2_valid_masked && !s2_meta_error && s2_hit val s2_no_alloc_hazard = if (!usingVM || pgIdxBits >= untagBits) false.B else { // make sure that any in-flight non-allocating accesses are ordered before // any allocating accesses. this can only happen if aliasing is possible. val any_no_alloc_in_flight = Reg(Bool()) when (!uncachedInFlight.asUInt.orR) { any_no_alloc_in_flight := false.B } when (s2_valid && s2_req.no_alloc) { any_no_alloc_in_flight := true.B } val s1_need_check = any_no_alloc_in_flight || s2_valid && s2_req.no_alloc val concerns = (uncachedInFlight zip uncachedReqs) :+ (s2_valid && s2_req.no_alloc, s2_req) val s1_uncached_hits = concerns.map { c => val concern_wmask = new StoreGen(c._2.size, c._2.addr, 0.U, wordBytes).mask val addr_match = (c._2.addr ^ s1_paddr)(pgIdxBits+pgLevelBits-1, wordBytes.log2) === 0.U val mask_match = (concern_wmask & s1_mask_xwr).orR || c._2.cmd === M_PWR || s1_req.cmd === M_PWR val cmd_match = isWrite(c._2.cmd) || isWrite(s1_req.cmd) c._1 && s1_need_check && cmd_match && addr_match && mask_match } val s2_uncached_hits = RegEnable(s1_uncached_hits.asUInt, s1_valid_not_nacked) s2_uncached_hits.orR } val s2_valid_hit_pre_data_ecc_and_waw = s2_valid_hit_maybe_flush_pre_data_ecc_and_waw && s2_readwrite && !s2_no_alloc_hazard val s2_valid_flush_line = s2_valid_hit_maybe_flush_pre_data_ecc_and_waw && s2_cmd_flush_line val s2_valid_hit_pre_data_ecc = s2_valid_hit_pre_data_ecc_and_waw && (!s2_waw_hazard || s2_store_merge) val s2_valid_data_error = s2_valid_hit_pre_data_ecc_and_waw && s2_data_error val s2_valid_hit = s2_valid_hit_pre_data_ecc && !s2_data_error val s2_valid_miss = s2_valid_masked && s2_readwrite && !s2_meta_error && !s2_hit val s2_uncached = !s2_pma.cacheable || s2_req.no_alloc && !s2_pma.must_alloc && !s2_hit_valid val s2_valid_cached_miss = s2_valid_miss && !s2_uncached && !uncachedInFlight.asUInt.orR dontTouch(s2_valid_cached_miss) val s2_want_victimize = (!usingDataScratchpad).B && (s2_valid_cached_miss || s2_valid_flush_line || s2_valid_data_error || s2_flush_valid) val s2_cannot_victimize = !s2_flush_valid && io.cpu.s2_kill val s2_victimize = s2_want_victimize && !s2_cannot_victimize val s2_valid_uncached_pending = s2_valid_miss && s2_uncached && !uncachedInFlight.asUInt.andR val s2_victim_way = UIntToOH(RegEnable(s1_victim_way, s1_valid_not_nacked || s1_flush_valid)) val s2_victim_or_hit_way = Mux(s2_hit_valid, s2_hit_way, s2_victim_way) val s2_victim_tag = Mux(s2_valid_data_error || s2_valid_flush_line, s2_req.addr(paddrBits-1, tagLSB), Mux1H(s2_victim_way, s2_meta_corrected).tag) val s2_victim_state = Mux(s2_hit_valid, s2_hit_state, Mux1H(s2_victim_way, s2_meta_corrected).coh) val (s2_prb_ack_data, s2_report_param, probeNewCoh)= s2_probe_state.onProbe(probe_bits.param) val (s2_victim_dirty, s2_shrink_param, voluntaryNewCoh) = s2_victim_state.onCacheControl(M_FLUSH) dontTouch(s2_victim_dirty) val s2_update_meta = s2_hit_state =/= s2_new_hit_state val s2_dont_nack_uncached = s2_valid_uncached_pending && tl_out_a.ready val s2_dont_nack_misc = s2_valid_masked && !s2_meta_error && (supports_flush.B && s2_cmd_flush_all && flushed && !flushing || supports_flush.B && s2_cmd_flush_line && !s2_hit || s2_req.cmd === M_WOK) io.cpu.s2_nack := s2_valid_no_xcpt && !s2_dont_nack_uncached && !s2_dont_nack_misc && !s2_valid_hit when (io.cpu.s2_nack || (s2_valid_hit_pre_data_ecc_and_waw && s2_update_meta)) { s1_nack := true.B } // tag updates on ECC errors val s2_first_meta_corrected = PriorityMux(s2_meta_correctable_errors, s2_meta_corrected) metaArb.io.in(1).valid := s2_meta_error && (s2_valid_masked || s2_flush_valid_pre_tag_ecc || s2_probe) metaArb.io.in(1).bits.write := true.B metaArb.io.in(1).bits.way_en := s2_meta_uncorrectable_errors | Mux(s2_meta_error_uncorrectable, 0.U, PriorityEncoderOH(s2_meta_correctable_errors)) metaArb.io.in(1).bits.idx := Mux(s2_probe, probeIdx(probe_bits), s2_vaddr(idxMSB, idxLSB)) metaArb.io.in(1).bits.addr := Cat(io.cpu.req.bits.addr >> untagBits, metaArb.io.in(1).bits.idx << blockOffBits) metaArb.io.in(1).bits.data := tECC.encode { val new_meta = WireDefault(s2_first_meta_corrected) when (s2_meta_error_uncorrectable) { new_meta.coh := ClientMetadata.onReset } new_meta.asUInt } // tag updates on hit metaArb.io.in(2).valid := s2_valid_hit_pre_data_ecc_and_waw && s2_update_meta metaArb.io.in(2).bits.write := !io.cpu.s2_kill metaArb.io.in(2).bits.way_en := s2_victim_or_hit_way metaArb.io.in(2).bits.idx := s2_vaddr(idxMSB, idxLSB) metaArb.io.in(2).bits.addr := Cat(io.cpu.req.bits.addr >> untagBits, s2_vaddr(idxMSB, 0)) metaArb.io.in(2).bits.data := tECC.encode(L1Metadata(s2_req.addr >> tagLSB, s2_new_hit_state).asUInt) // load reservations and TL error reporting val s2_lr = (usingAtomics && !usingDataScratchpad).B && s2_req.cmd === M_XLR val s2_sc = (usingAtomics && !usingDataScratchpad).B && s2_req.cmd === M_XSC val lrscCount = RegInit(0.U) val lrscValid = lrscCount > lrscBackoff.U val lrscBackingOff = lrscCount > 0.U && !lrscValid val lrscAddr = Reg(UInt()) val lrscAddrMatch = lrscAddr === (s2_req.addr >> blockOffBits) val s2_sc_fail = s2_sc && !(lrscValid && lrscAddrMatch) when ((s2_valid_hit && s2_lr && !cached_grant_wait || s2_valid_cached_miss) && !io.cpu.s2_kill) { lrscCount := Mux(s2_hit, (lrscCycles - 1).U, 0.U) lrscAddr := s2_req.addr >> blockOffBits } when (lrscCount > 0.U) { lrscCount := lrscCount - 1.U } when (s2_valid_not_killed && lrscValid) { lrscCount := lrscBackoff.U } when (s1_probe) { lrscCount := 0.U } // don't perform data correction if it might clobber a recent store val s2_correct = s2_data_error && !any_pstore_valid && !RegNext(any_pstore_valid || s2_valid) && usingDataScratchpad.B // pending store buffer val s2_valid_correct = s2_valid_hit_pre_data_ecc_and_waw && s2_correct && !io.cpu.s2_kill def s2_store_valid_pre_kill = s2_valid_hit && s2_write && !s2_sc_fail def s2_store_valid = s2_store_valid_pre_kill && !io.cpu.s2_kill val pstore1_cmd = RegEnable(s1_req.cmd, s1_valid_not_nacked && s1_write) val pstore1_addr = RegEnable(s1_vaddr, s1_valid_not_nacked && s1_write) val pstore1_data = RegEnable(io.cpu.s1_data.data, s1_valid_not_nacked && s1_write) val pstore1_way = RegEnable(s1_hit_way, s1_valid_not_nacked && s1_write) val pstore1_mask = RegEnable(s1_mask, s1_valid_not_nacked && s1_write) val pstore1_storegen_data = WireDefault(pstore1_data) val pstore1_rmw = usingRMW.B && RegEnable(needsRead(s1_req), s1_valid_not_nacked && s1_write) val pstore1_merge_likely = s2_valid_not_nacked_in_s1 && s2_write && s2_store_merge val pstore1_merge = s2_store_valid && s2_store_merge val pstore2_valid = RegInit(false.B) val pstore_drain_opportunistic = !(io.cpu.req.valid && likelyNeedsRead(io.cpu.req.bits)) && !(s1_valid && s1_waw_hazard) val pstore_drain_on_miss = releaseInFlight || RegNext(io.cpu.s2_nack) val pstore1_held = RegInit(false.B) val pstore1_valid_likely = s2_valid && s2_write || pstore1_held def pstore1_valid_not_rmw(s2_kill: Bool) = s2_valid_hit_pre_data_ecc && s2_write && !s2_kill || pstore1_held val pstore1_valid = s2_store_valid || pstore1_held any_pstore_valid := pstore1_held || pstore2_valid val pstore_drain_structural = pstore1_valid_likely && pstore2_valid && ((s1_valid && s1_write) || pstore1_rmw) assert(pstore1_rmw || pstore1_valid_not_rmw(io.cpu.s2_kill) === pstore1_valid) ccover(pstore_drain_structural, "STORE_STRUCTURAL_HAZARD", "D$ read-modify-write structural hazard") ccover(pstore1_valid && pstore_drain_on_miss, "STORE_DRAIN_ON_MISS", "D$ store buffer drain on miss") ccover(s1_valid_not_nacked && s1_waw_hazard, "WAW_HAZARD", "D$ write-after-write hazard") def should_pstore_drain(truly: Bool) = { val s2_kill = truly && io.cpu.s2_kill !pstore1_merge_likely && (usingRMW.B && pstore_drain_structural || (((pstore1_valid_not_rmw(s2_kill) && !pstore1_rmw) || pstore2_valid) && (pstore_drain_opportunistic || pstore_drain_on_miss))) } val pstore_drain = should_pstore_drain(true.B) pstore1_held := (s2_store_valid && !s2_store_merge || pstore1_held) && pstore2_valid && !pstore_drain val advance_pstore1 = (pstore1_valid || s2_valid_correct) && (pstore2_valid === pstore_drain) pstore2_valid := pstore2_valid && !pstore_drain || advance_pstore1 val pstore2_addr = RegEnable(Mux(s2_correct, s2_vaddr, pstore1_addr), advance_pstore1) val pstore2_way = RegEnable(Mux(s2_correct, s2_hit_way, pstore1_way), advance_pstore1) val pstore2_storegen_data = { for (i <- 0 until wordBytes) yield RegEnable(pstore1_storegen_data(8*(i+1)-1, 8*i), advance_pstore1 || pstore1_merge && pstore1_mask(i)) }.asUInt val pstore2_storegen_mask = { val mask = Reg(UInt(wordBytes.W)) when (advance_pstore1 || pstore1_merge) { val mergedMask = pstore1_mask | Mux(pstore1_merge, mask, 0.U) mask := ~Mux(s2_correct, 0.U, ~mergedMask) } mask } s2_store_merge := (if (eccBytes == 1) false.B else { ccover(pstore1_merge, "STORE_MERGED", "D$ store merged") // only merge stores to ECC granules that are already stored-to, to avoid // WAW hazards val wordMatch = (eccMask(pstore2_storegen_mask) | ~eccMask(pstore1_mask)).andR val idxMatch = s2_vaddr(untagBits-1, log2Ceil(wordBytes)) === pstore2_addr(untagBits-1, log2Ceil(wordBytes)) val tagMatch = (s2_hit_way & pstore2_way).orR pstore2_valid && wordMatch && idxMatch && tagMatch }) dataArb.io.in(0).valid := should_pstore_drain(false.B) dataArb.io.in(0).bits.write := pstore_drain dataArb.io.in(0).bits.addr := Mux(pstore2_valid, pstore2_addr, pstore1_addr) dataArb.io.in(0).bits.way_en := Mux(pstore2_valid, pstore2_way, pstore1_way) dataArb.io.in(0).bits.wdata := encodeData(Fill(rowWords, Mux(pstore2_valid, pstore2_storegen_data, pstore1_data)), false.B) dataArb.io.in(0).bits.wordMask := { val eccMask = dataArb.io.in(0).bits.eccMask.asBools.grouped(subWordBytes/eccBytes).map(_.orR).toSeq.asUInt val wordMask = UIntToOH(Mux(pstore2_valid, pstore2_addr, pstore1_addr).extract(rowOffBits-1, wordBytes.log2)) FillInterleaved(wordBytes/subWordBytes, wordMask) & Fill(rowBytes/wordBytes, eccMask) } dataArb.io.in(0).bits.eccMask := eccMask(Mux(pstore2_valid, pstore2_storegen_mask, pstore1_mask)) // store->load RAW hazard detection def s1Depends(addr: UInt, mask: UInt) = addr(idxMSB, wordOffBits) === s1_vaddr(idxMSB, wordOffBits) && Mux(s1_write, (eccByteMask(mask) & eccByteMask(s1_mask_xwr)).orR, (mask & s1_mask_xwr).orR) val s1_hazard = (pstore1_valid_likely && s1Depends(pstore1_addr, pstore1_mask)) || (pstore2_valid && s1Depends(pstore2_addr, pstore2_storegen_mask)) val s1_raw_hazard = s1_read && s1_hazard s1_waw_hazard := (if (eccBytes == 1) false.B else { ccover(s1_valid_not_nacked && s1_waw_hazard, "WAW_HAZARD", "D$ write-after-write hazard") s1_write && (s1_hazard || needsRead(s1_req) && !s1_did_read) }) when (s1_valid && s1_raw_hazard) { s1_nack := true.B } // performance hints to processor io.cpu.s2_nack_cause_raw := RegNext(s1_raw_hazard) || !(!s2_waw_hazard || s2_store_merge) // Prepare a TileLink request message that initiates a transaction val a_source = PriorityEncoder(~uncachedInFlight.asUInt << mmioOffset) // skip the MSHR val acquire_address = (s2_req.addr >> idxLSB) << idxLSB val access_address = s2_req.addr val a_size = s2_req.size val a_data = Fill(beatWords, pstore1_data) val a_mask = pstore1_mask << (access_address.extract(beatBytes.log2-1, wordBytes.log2) << 3) val get = edge.Get(a_source, access_address, a_size)._2 val put = edge.Put(a_source, access_address, a_size, a_data)._2 val putpartial = edge.Put(a_source, access_address, a_size, a_data, a_mask)._2 val atomics = if (edge.manager.anySupportLogical) { MuxLookup(s2_req.cmd, WireDefault(0.U.asTypeOf(new TLBundleA(edge.bundle))))(Array( M_XA_SWAP -> edge.Logical(a_source, access_address, a_size, a_data, TLAtomics.SWAP)._2, M_XA_XOR -> edge.Logical(a_source, access_address, a_size, a_data, TLAtomics.XOR) ._2, M_XA_OR -> edge.Logical(a_source, access_address, a_size, a_data, TLAtomics.OR) ._2, M_XA_AND -> edge.Logical(a_source, access_address, a_size, a_data, TLAtomics.AND) ._2, M_XA_ADD -> edge.Arithmetic(a_source, access_address, a_size, a_data, TLAtomics.ADD)._2, M_XA_MIN -> edge.Arithmetic(a_source, access_address, a_size, a_data, TLAtomics.MIN)._2, M_XA_MAX -> edge.Arithmetic(a_source, access_address, a_size, a_data, TLAtomics.MAX)._2, M_XA_MINU -> edge.Arithmetic(a_source, access_address, a_size, a_data, TLAtomics.MINU)._2, M_XA_MAXU -> edge.Arithmetic(a_source, access_address, a_size, a_data, TLAtomics.MAXU)._2)) } else { // If no managers support atomics, assert fail if processor asks for them assert (!(tl_out_a.valid && s2_read && s2_write && s2_uncached)) WireDefault(new TLBundleA(edge.bundle), DontCare) } tl_out_a.valid := !io.cpu.s2_kill && (s2_valid_uncached_pending || (s2_valid_cached_miss && !(release_ack_wait && (s2_req.addr ^ release_ack_addr)(((pgIdxBits + pgLevelBits) min paddrBits) - 1, idxLSB) === 0.U) && (cacheParams.acquireBeforeRelease.B && !release_ack_wait && release_queue_empty || !s2_victim_dirty))) tl_out_a.bits := Mux(!s2_uncached, acquire(s2_vaddr, s2_req.addr, s2_grow_param), Mux(!s2_write, get, Mux(s2_req.cmd === M_PWR, putpartial, Mux(!s2_read, put, atomics)))) // Drive APROT Bits tl_out_a.bits.user.lift(AMBAProt).foreach { x => val user_bit_cacheable = s2_pma.cacheable x.privileged := s2_req.dprv === PRV.M.U || user_bit_cacheable // if the address is cacheable, enable outer caches x.bufferable := user_bit_cacheable x.modifiable := user_bit_cacheable x.readalloc := user_bit_cacheable x.writealloc := user_bit_cacheable // Following are always tied off x.fetch := false.B x.secure := true.B } // Set pending bits for outstanding TileLink transaction val a_sel = UIntToOH(a_source, maxUncachedInFlight+mmioOffset) >> mmioOffset when (tl_out_a.fire) { when (s2_uncached) { (a_sel.asBools zip (uncachedInFlight zip uncachedReqs)) foreach { case (s, (f, r)) => when (s) { f := true.B r := s2_req r.cmd := Mux(s2_write, Mux(s2_req.cmd === M_PWR, M_PWR, M_XWR), M_XRD) } } }.otherwise { cached_grant_wait := true.B refill_way := s2_victim_or_hit_way } } // grant val (d_first, d_last, d_done, d_address_inc) = edge.addr_inc(tl_out.d) val (d_opc, grantIsUncached, grantIsUncachedData) = { val uncachedGrantOpcodesSansData = Seq(AccessAck, HintAck) val uncachedGrantOpcodesWithData = Seq(AccessAckData) val uncachedGrantOpcodes = uncachedGrantOpcodesWithData ++ uncachedGrantOpcodesSansData val whole_opc = tl_out.d.bits.opcode if (usingDataScratchpad) { assert(!tl_out.d.valid || whole_opc.isOneOf(uncachedGrantOpcodes)) // the only valid TL-D messages are uncached, so we can do some pruning val opc = whole_opc(uncachedGrantOpcodes.map(_.getWidth).max - 1, 0) val data = DecodeLogic(opc, uncachedGrantOpcodesWithData, uncachedGrantOpcodesSansData) (opc, true.B, data) } else { (whole_opc, whole_opc.isOneOf(uncachedGrantOpcodes), whole_opc.isOneOf(uncachedGrantOpcodesWithData)) } } tl_d_data_encoded := encodeData(tl_out.d.bits.data, tl_out.d.bits.corrupt && !io.ptw.customCSRs.suppressCorruptOnGrantData && !grantIsUncached) val grantIsCached = d_opc.isOneOf(Grant, GrantData) val grantIsVoluntary = d_opc === ReleaseAck // Clears a different pending bit val grantIsRefill = d_opc === GrantData // Writes the data array val grantInProgress = RegInit(false.B) val blockProbeAfterGrantCount = RegInit(0.U) when (blockProbeAfterGrantCount > 0.U) { blockProbeAfterGrantCount := blockProbeAfterGrantCount - 1.U } val canAcceptCachedGrant = !release_state.isOneOf(s_voluntary_writeback, s_voluntary_write_meta, s_voluntary_release) tl_out.d.ready := Mux(grantIsCached, (!d_first || tl_out.e.ready) && canAcceptCachedGrant, true.B) val uncachedRespIdxOH = UIntToOH(tl_out.d.bits.source, maxUncachedInFlight+mmioOffset) >> mmioOffset uncachedResp := Mux1H(uncachedRespIdxOH, uncachedReqs) when (tl_out.d.fire) { when (grantIsCached) { grantInProgress := true.B assert(cached_grant_wait, "A GrantData was unexpected by the dcache.") when(d_last) { cached_grant_wait := false.B grantInProgress := false.B blockProbeAfterGrantCount := (blockProbeAfterGrantCycles - 1).U replacer.miss } } .elsewhen (grantIsUncached) { (uncachedRespIdxOH.asBools zip uncachedInFlight) foreach { case (s, f) => when (s && d_last) { assert(f, "An AccessAck was unexpected by the dcache.") // TODO must handle Ack coming back on same cycle! f := false.B } } when (grantIsUncachedData) { if (!cacheParams.separateUncachedResp) { if (!cacheParams.pipelineWayMux) s1_data_way := 1.U << nWays s2_req.cmd := M_XRD s2_req.size := uncachedResp.size s2_req.signed := uncachedResp.signed s2_req.tag := uncachedResp.tag s2_req.addr := { require(rowOffBits >= beatOffBits) val dontCareBits = s1_paddr >> rowOffBits << rowOffBits dontCareBits | uncachedResp.addr(beatOffBits-1, 0) } s2_uncached_resp_addr := uncachedResp.addr } } } .elsewhen (grantIsVoluntary) { assert(release_ack_wait, "A ReleaseAck was unexpected by the dcache.") // TODO should handle Ack coming back on same cycle! release_ack_wait := false.B } } // Finish TileLink transaction by issuing a GrantAck tl_out.e.valid := tl_out.d.valid && d_first && grantIsCached && canAcceptCachedGrant tl_out.e.bits := edge.GrantAck(tl_out.d.bits) assert(tl_out.e.fire === (tl_out.d.fire && d_first && grantIsCached)) // data refill // note this ready-valid signaling ignores E-channel backpressure, which // benignly means the data RAM might occasionally be redundantly written dataArb.io.in(1).valid := tl_out.d.valid && grantIsRefill && canAcceptCachedGrant when (grantIsRefill && !dataArb.io.in(1).ready) { tl_out.e.valid := false.B tl_out.d.ready := false.B } if (!usingDataScratchpad) { dataArb.io.in(1).bits.write := true.B dataArb.io.in(1).bits.addr := (s2_vaddr >> idxLSB) << idxLSB | d_address_inc dataArb.io.in(1).bits.way_en := refill_way dataArb.io.in(1).bits.wdata := tl_d_data_encoded dataArb.io.in(1).bits.wordMask := ~0.U((rowBytes / subWordBytes).W) dataArb.io.in(1).bits.eccMask := ~0.U((wordBytes / eccBytes).W) } else { dataArb.io.in(1).bits := dataArb.io.in(0).bits } // tag updates on refill // ignore backpressure from metaArb, which can only be caused by tag ECC // errors on hit-under-miss. failing to write the new tag will leave the // line invalid, so we'll simply request the line again later. metaArb.io.in(3).valid := grantIsCached && d_done && !tl_out.d.bits.denied metaArb.io.in(3).bits.write := true.B metaArb.io.in(3).bits.way_en := refill_way metaArb.io.in(3).bits.idx := s2_vaddr(idxMSB, idxLSB) metaArb.io.in(3).bits.addr := Cat(io.cpu.req.bits.addr >> untagBits, s2_vaddr(idxMSB, 0)) metaArb.io.in(3).bits.data := tECC.encode(L1Metadata(s2_req.addr >> tagLSB, s2_hit_state.onGrant(s2_req.cmd, tl_out.d.bits.param)).asUInt) if (!cacheParams.separateUncachedResp) { // don't accept uncached grants if there's a structural hazard on s2_data... val blockUncachedGrant = Reg(Bool()) blockUncachedGrant := dataArb.io.out.valid when (grantIsUncachedData && (blockUncachedGrant || s1_valid)) { tl_out.d.ready := false.B // ...but insert bubble to guarantee grant's eventual forward progress when (tl_out.d.valid) { io.cpu.req.ready := false.B dataArb.io.in(1).valid := true.B dataArb.io.in(1).bits.write := false.B blockUncachedGrant := !dataArb.io.in(1).ready } } } ccover(tl_out.d.valid && !tl_out.d.ready, "BLOCK_D", "D$ D-channel blocked") // Handle an incoming TileLink Probe message val block_probe_for_core_progress = blockProbeAfterGrantCount > 0.U || lrscValid val block_probe_for_pending_release_ack = release_ack_wait && (tl_out.b.bits.address ^ release_ack_addr)(((pgIdxBits + pgLevelBits) min paddrBits) - 1, idxLSB) === 0.U val block_probe_for_ordering = releaseInFlight || block_probe_for_pending_release_ack || grantInProgress metaArb.io.in(6).valid := tl_out.b.valid && (!block_probe_for_core_progress || lrscBackingOff) tl_out.b.ready := metaArb.io.in(6).ready && !(block_probe_for_core_progress || block_probe_for_ordering || s1_valid || s2_valid) metaArb.io.in(6).bits.write := false.B metaArb.io.in(6).bits.idx := probeIdx(tl_out.b.bits) metaArb.io.in(6).bits.addr := Cat(io.cpu.req.bits.addr >> paddrBits, tl_out.b.bits.address) metaArb.io.in(6).bits.way_en := metaArb.io.in(4).bits.way_en metaArb.io.in(6).bits.data := metaArb.io.in(4).bits.data // replacement policy s1_victim_way := (if (replacer.perSet && nWays > 1) { val repl_array = Mem(nSets, UInt(replacer.nBits.W)) val s1_repl_idx = s1_req.addr(idxBits+blockOffBits-1, blockOffBits) val s2_repl_idx = s2_vaddr(idxBits+blockOffBits-1, blockOffBits) val s2_repl_state = Reg(UInt(replacer.nBits.W)) val s2_new_repl_state = replacer.get_next_state(s2_repl_state, OHToUInt(s2_hit_way)) val s2_repl_wen = s2_valid_masked && s2_hit_way.orR && s2_repl_state =/= s2_new_repl_state val s1_repl_state = Mux(s2_repl_wen && s2_repl_idx === s1_repl_idx, s2_new_repl_state, repl_array(s1_repl_idx)) when (s1_valid_not_nacked) { s2_repl_state := s1_repl_state } val waddr = Mux(resetting, flushCounter(idxBits-1, 0), s2_repl_idx) val wdata = Mux(resetting, 0.U, s2_new_repl_state) val wen = resetting || s2_repl_wen when (wen) { repl_array(waddr) := wdata } replacer.get_replace_way(s1_repl_state) } else { replacer.way }) // release val (c_first, c_last, releaseDone, c_count) = edge.count(tl_out_c) val releaseRejected = Wire(Bool()) val s1_release_data_valid = RegNext(dataArb.io.in(2).fire) val s2_release_data_valid = RegNext(s1_release_data_valid && !releaseRejected) releaseRejected := s2_release_data_valid && !tl_out_c.fire val releaseDataBeat = Cat(0.U, c_count) + Mux(releaseRejected, 0.U, s1_release_data_valid + Cat(0.U, s2_release_data_valid)) val nackResponseMessage = edge.ProbeAck(b = probe_bits, reportPermissions = TLPermissions.NtoN) val cleanReleaseMessage = edge.ProbeAck(b = probe_bits, reportPermissions = s2_report_param) val dirtyReleaseMessage = edge.ProbeAck(b = probe_bits, reportPermissions = s2_report_param, data = 0.U) tl_out_c.valid := (s2_release_data_valid || (!cacheParams.silentDrop.B && release_state === s_voluntary_release)) && !(c_first && release_ack_wait) tl_out_c.bits := nackResponseMessage val newCoh = WireDefault(probeNewCoh) releaseWay := s2_probe_way if (!usingDataScratchpad) { when (s2_victimize) { assert(s2_valid_flush_line || s2_flush_valid || io.cpu.s2_nack) val discard_line = s2_valid_flush_line && s2_req.size(1) || s2_flush_valid && flushing_req.size(1) release_state := Mux(s2_victim_dirty && !discard_line, s_voluntary_writeback, Mux(!cacheParams.silentDrop.B && !release_ack_wait && release_queue_empty && s2_victim_state.isValid() && (s2_valid_flush_line || s2_flush_valid || s2_readwrite && !s2_hit_valid), s_voluntary_release, s_voluntary_write_meta)) probe_bits := addressToProbe(s2_vaddr, Cat(s2_victim_tag, s2_req.addr(tagLSB-1, idxLSB)) << idxLSB) } when (s2_probe) { val probeNack = WireDefault(true.B) when (s2_meta_error) { release_state := s_probe_retry }.elsewhen (s2_prb_ack_data) { release_state := s_probe_rep_dirty }.elsewhen (s2_probe_state.isValid()) { tl_out_c.valid := true.B tl_out_c.bits := cleanReleaseMessage release_state := Mux(releaseDone, s_probe_write_meta, s_probe_rep_clean) }.otherwise { tl_out_c.valid := true.B probeNack := !releaseDone release_state := Mux(releaseDone, s_ready, s_probe_rep_miss) } when (probeNack) { s1_nack := true.B } } when (release_state === s_probe_retry) { metaArb.io.in(6).valid := true.B metaArb.io.in(6).bits.idx := probeIdx(probe_bits) metaArb.io.in(6).bits.addr := Cat(io.cpu.req.bits.addr >> paddrBits, probe_bits.address) when (metaArb.io.in(6).ready) { release_state := s_ready s1_probe := true.B } } when (release_state === s_probe_rep_miss) { tl_out_c.valid := true.B when (releaseDone) { release_state := s_ready } } when (release_state === s_probe_rep_clean) { tl_out_c.valid := true.B tl_out_c.bits := cleanReleaseMessage when (releaseDone) { release_state := s_probe_write_meta } } when (release_state === s_probe_rep_dirty) { tl_out_c.bits := dirtyReleaseMessage when (releaseDone) { release_state := s_probe_write_meta } } when (release_state.isOneOf(s_voluntary_writeback, s_voluntary_write_meta, s_voluntary_release)) { when (release_state === s_voluntary_release) { tl_out_c.bits := edge.Release(fromSource = 0.U, toAddress = 0.U, lgSize = lgCacheBlockBytes.U, shrinkPermissions = s2_shrink_param)._2 }.otherwise { tl_out_c.bits := edge.Release(fromSource = 0.U, toAddress = 0.U, lgSize = lgCacheBlockBytes.U, shrinkPermissions = s2_shrink_param, data = 0.U)._2 } newCoh := voluntaryNewCoh releaseWay := s2_victim_or_hit_way when (releaseDone) { release_state := s_voluntary_write_meta } when (tl_out_c.fire && c_first) { release_ack_wait := true.B release_ack_addr := probe_bits.address } } tl_out_c.bits.source := probe_bits.source tl_out_c.bits.address := probe_bits.address tl_out_c.bits.data := s2_data_corrected tl_out_c.bits.corrupt := inWriteback && s2_data_error_uncorrectable } tl_out_c.bits.user.lift(AMBAProt).foreach { x => x.fetch := false.B x.secure := true.B x.privileged := true.B x.bufferable := true.B x.modifiable := true.B x.readalloc := true.B x.writealloc := true.B } dataArb.io.in(2).valid := inWriteback && releaseDataBeat < refillCycles.U dataArb.io.in(2).bits := dataArb.io.in(1).bits dataArb.io.in(2).bits.write := false.B dataArb.io.in(2).bits.addr := (probeIdx(probe_bits) << blockOffBits) | (releaseDataBeat(log2Up(refillCycles)-1,0) << rowOffBits) dataArb.io.in(2).bits.wordMask := ~0.U((rowBytes / subWordBytes).W) dataArb.io.in(2).bits.eccMask := ~0.U((wordBytes / eccBytes).W) dataArb.io.in(2).bits.way_en := ~0.U(nWays.W) metaArb.io.in(4).valid := release_state.isOneOf(s_voluntary_write_meta, s_probe_write_meta) metaArb.io.in(4).bits.write := true.B metaArb.io.in(4).bits.way_en := releaseWay metaArb.io.in(4).bits.idx := probeIdx(probe_bits) metaArb.io.in(4).bits.addr := Cat(io.cpu.req.bits.addr >> untagBits, probe_bits.address(idxMSB, 0)) metaArb.io.in(4).bits.data := tECC.encode(L1Metadata(tl_out_c.bits.address >> tagLSB, newCoh).asUInt) when (metaArb.io.in(4).fire) { release_state := s_ready } // cached response (io.cpu.resp.bits: Data).waiveAll :<>= (s2_req: Data).waiveAll io.cpu.resp.bits.has_data := s2_read io.cpu.resp.bits.replay := false.B io.cpu.s2_uncached := s2_uncached && !s2_hit io.cpu.s2_paddr := s2_req.addr io.cpu.s2_gpa := s2_tlb_xcpt.gpa io.cpu.s2_gpa_is_pte := s2_tlb_xcpt.gpa_is_pte // report whether there are any outstanding accesses. disregard any // slave-port accesses, since they don't affect local memory ordering. val s1_isSlavePortAccess = s1_req.no_xcpt val s2_isSlavePortAccess = s2_req.no_xcpt io.cpu.ordered := !(s1_valid && !s1_isSlavePortAccess || s2_valid && !s2_isSlavePortAccess || cached_grant_wait || uncachedInFlight.asUInt.orR) io.cpu.store_pending := (cached_grant_wait && isWrite(s2_req.cmd)) || uncachedInFlight.asUInt.orR val s1_xcpt_valid = tlb.io.req.valid && !s1_isSlavePortAccess && !s1_nack io.cpu.s2_xcpt := Mux(RegNext(s1_xcpt_valid), s2_tlb_xcpt, 0.U.asTypeOf(s2_tlb_xcpt)) if (usingDataScratchpad) { assert(!(s2_valid_masked && s2_req.cmd.isOneOf(M_XLR, M_XSC))) } else { ccover(tl_out.b.valid && !tl_out.b.ready, "BLOCK_B", "D$ B-channel blocked") } // uncached response val s1_uncached_data_word = { val word_idx = uncachedResp.addr.extract(log2Up(rowBits/8)-1, log2Up(wordBytes)) val words = tl_out.d.bits.data.grouped(wordBits) words(word_idx) } val s2_uncached_data_word = RegEnable(s1_uncached_data_word, io.cpu.replay_next) val doUncachedResp = RegNext(io.cpu.replay_next) io.cpu.resp.valid := (s2_valid_hit_pre_data_ecc || doUncachedResp) && !s2_data_error io.cpu.replay_next := tl_out.d.fire && grantIsUncachedData && !cacheParams.separateUncachedResp.B when (doUncachedResp) { assert(!s2_valid_hit) io.cpu.resp.bits.replay := true.B io.cpu.resp.bits.addr := s2_uncached_resp_addr } io.cpu.uncached_resp.map { resp => resp.valid := tl_out.d.valid && grantIsUncachedData resp.bits.tag := uncachedResp.tag resp.bits.size := uncachedResp.size resp.bits.signed := uncachedResp.signed resp.bits.data := new LoadGen(uncachedResp.size, uncachedResp.signed, uncachedResp.addr, s1_uncached_data_word, false.B, wordBytes).data resp.bits.data_raw := s1_uncached_data_word when (grantIsUncachedData && !resp.ready) { tl_out.d.ready := false.B } } // load data subword mux/sign extension val s2_data_word = (0 until rowBits by wordBits).map(i => s2_data_uncorrected(wordBits+i-1,i)).reduce(_|_) val s2_data_word_corrected = (0 until rowBits by wordBits).map(i => s2_data_corrected(wordBits+i-1,i)).reduce(_|_) val s2_data_word_possibly_uncached = Mux(cacheParams.pipelineWayMux.B && doUncachedResp, s2_uncached_data_word, 0.U) | s2_data_word val loadgen = new LoadGen(s2_req.size, s2_req.signed, s2_req.addr, s2_data_word_possibly_uncached, s2_sc, wordBytes) io.cpu.resp.bits.data := loadgen.data | s2_sc_fail io.cpu.resp.bits.data_word_bypass := loadgen.wordData io.cpu.resp.bits.data_raw := s2_data_word io.cpu.resp.bits.store_data := pstore1_data // AMOs if (usingRMW) { val amoalus = (0 until coreDataBits / xLen).map { i => val amoalu = Module(new AMOALU(xLen)) amoalu.io.mask := pstore1_mask >> (i * xBytes) amoalu.io.cmd := (if (usingAtomicsInCache) pstore1_cmd else M_XWR) amoalu.io.lhs := s2_data_word >> (i * xLen) amoalu.io.rhs := pstore1_data >> (i * xLen) amoalu } pstore1_storegen_data := (if (!usingDataScratchpad) amoalus.map(_.io.out).asUInt else { val mask = FillInterleaved(8, Mux(s2_correct, 0.U, pstore1_mask)) amoalus.map(_.io.out_unmasked).asUInt & mask | s2_data_word_corrected & ~mask }) } else if (!usingAtomics) { assert(!(s1_valid_masked && s1_read && s1_write), "unsupported D$ operation") } if (coreParams.useVector) { edge.manager.managers.foreach { m => // Statically ensure that no-allocate accesses are permitted. // We could consider turning some of these into dynamic PMA checks. require(!m.supportsAcquireB || m.supportsGet, "With a vector unit, cacheable memory must support Get") require(!m.supportsAcquireT || m.supportsPutPartial, "With a vector unit, cacheable memory must support PutPartial") } } // flushes if (!usingDataScratchpad) when (RegNext(reset.asBool)) { resetting := true.B } val flushCounterNext = flushCounter +& 1.U val flushDone = (flushCounterNext >> log2Ceil(nSets)) === nWays.U val flushCounterWrap = flushCounterNext(log2Ceil(nSets)-1, 0) ccover(s2_valid_masked && s2_cmd_flush_all && s2_meta_error, "TAG_ECC_ERROR_DURING_FENCE_I", "D$ ECC error in tag array during cache flush") ccover(s2_valid_masked && s2_cmd_flush_all && s2_data_error, "DATA_ECC_ERROR_DURING_FENCE_I", "D$ ECC error in data array during cache flush") s1_flush_valid := metaArb.io.in(5).fire && !s1_flush_valid && !s2_flush_valid_pre_tag_ecc && release_state === s_ready && !release_ack_wait metaArb.io.in(5).valid := flushing && !flushed metaArb.io.in(5).bits.write := false.B metaArb.io.in(5).bits.idx := flushCounter(idxBits-1, 0) metaArb.io.in(5).bits.addr := Cat(io.cpu.req.bits.addr >> untagBits, metaArb.io.in(5).bits.idx << blockOffBits) metaArb.io.in(5).bits.way_en := metaArb.io.in(4).bits.way_en metaArb.io.in(5).bits.data := metaArb.io.in(4).bits.data // Only flush D$ on FENCE.I if some cached executable regions are untracked. if (supports_flush) { when (s2_valid_masked && s2_cmd_flush_all) { when (!flushed && !io.cpu.s2_kill && !release_ack_wait && !uncachedInFlight.asUInt.orR) { flushing := true.B flushing_req := s2_req } } when (tl_out_a.fire && !s2_uncached) { flushed := false.B } when (flushing) { s1_victim_way := flushCounter >> log2Up(nSets) when (s2_flush_valid) { flushCounter := flushCounterNext when (flushDone) { flushed := true.B if (!isPow2(nWays)) flushCounter := flushCounterWrap } } when (flushed && release_state === s_ready && !release_ack_wait) { flushing := false.B } } } metaArb.io.in(0).valid := resetting metaArb.io.in(0).bits := metaArb.io.in(5).bits metaArb.io.in(0).bits.write := true.B metaArb.io.in(0).bits.way_en := ~0.U(nWays.W) metaArb.io.in(0).bits.data := tECC.encode(L1Metadata(0.U, ClientMetadata.onReset).asUInt) when (resetting) { flushCounter := flushCounterNext when (flushDone) { resetting := false.B if (!isPow2(nWays)) flushCounter := flushCounterWrap } } // gate the clock clock_en_reg := !cacheParams.clockGate.B || io.ptw.customCSRs.disableDCacheClockGate || io.cpu.keep_clock_enabled || metaArb.io.out.valid || // subsumes resetting || flushing s1_probe || s2_probe || s1_valid || s2_valid || io.tlb_port.req.valid || s1_tlb_req_valid || s2_tlb_req_valid || pstore1_held || pstore2_valid || release_state =/= s_ready || release_ack_wait || !release_queue_empty || !tlb.io.req.ready || cached_grant_wait || uncachedInFlight.asUInt.orR || lrscCount > 0.U || blockProbeAfterGrantCount > 0.U // performance events io.cpu.perf.acquire := edge.done(tl_out_a) io.cpu.perf.release := edge.done(tl_out_c) io.cpu.perf.grant := tl_out.d.valid && d_last io.cpu.perf.tlbMiss := io.ptw.req.fire io.cpu.perf.storeBufferEmptyAfterLoad := !( (s1_valid && s1_write) || ((s2_valid && s2_write && !s2_waw_hazard) || pstore1_held) || pstore2_valid) io.cpu.perf.storeBufferEmptyAfterStore := !( (s1_valid && s1_write) || (s2_valid && s2_write && pstore1_rmw) || ((s2_valid && s2_write && !s2_waw_hazard || pstore1_held) && pstore2_valid)) io.cpu.perf.canAcceptStoreThenLoad := !( ((s2_valid && s2_write && pstore1_rmw) && (s1_valid && s1_write && !s1_waw_hazard)) || (pstore2_valid && pstore1_valid_likely && (s1_valid && s1_write))) io.cpu.perf.canAcceptStoreThenRMW := io.cpu.perf.canAcceptStoreThenLoad && !pstore2_valid io.cpu.perf.canAcceptLoadThenLoad := !((s1_valid && s1_write && needsRead(s1_req)) && ((s2_valid && s2_write && !s2_waw_hazard || pstore1_held) || pstore2_valid)) io.cpu.perf.blocked := { // stop reporting blocked just before unblocking to avoid overly conservative stalling val beatsBeforeEnd = outer.crossing match { case SynchronousCrossing(_) => 2 case RationalCrossing(_) => 1 // assumes 1 < ratio <= 2; need more bookkeeping for optimal handling of >2 case _: AsynchronousCrossing => 1 // likewise case _: CreditedCrossing => 1 // likewise } val near_end_of_refill = if (cacheBlockBytes / beatBytes <= beatsBeforeEnd) tl_out.d.valid else { val refill_count = RegInit(0.U((cacheBlockBytes / beatBytes).log2.W)) when (tl_out.d.fire && grantIsRefill) { refill_count := refill_count + 1.U } refill_count >= (cacheBlockBytes / beatBytes - beatsBeforeEnd).U } cached_grant_wait && !near_end_of_refill } // report errors val (data_error, data_error_uncorrectable, data_error_addr) = if (usingDataScratchpad) (s2_valid_data_error, s2_data_error_uncorrectable, s2_req.addr) else { (RegNext(tl_out_c.fire && inWriteback && s2_data_error), RegNext(s2_data_error_uncorrectable), probe_bits.address) // This is stable for a cycle after tl_out_c.fire, so don't need a register } { val error_addr = Mux(metaArb.io.in(1).valid, Cat(s2_first_meta_corrected.tag, metaArb.io.in(1).bits.addr(tagLSB-1, idxLSB)), data_error_addr >> idxLSB) << idxLSB io.errors.uncorrectable.foreach { u => u.valid := metaArb.io.in(1).valid && s2_meta_error_uncorrectable || data_error && data_error_uncorrectable u.bits := error_addr } io.errors.correctable.foreach { c => c.valid := metaArb.io.in(1).valid || data_error c.bits := error_addr io.errors.uncorrectable.foreach { u => when (u.valid) { c.valid := false.B } } } io.errors.bus.valid := tl_out.d.fire && (tl_out.d.bits.denied || tl_out.d.bits.corrupt) io.errors.bus.bits := Mux(grantIsCached, s2_req.addr >> idxLSB << idxLSB, 0.U) ccoverNotScratchpad(io.errors.bus.valid && grantIsCached, "D_ERROR_CACHED", "D$ D-channel error, cached") ccover(io.errors.bus.valid && !grantIsCached, "D_ERROR_UNCACHED", "D$ D-channel error, uncached") } if (usingDataScratchpad) { val data_error_cover = Seq( property.CoverBoolean(!data_error, Seq("no_data_error")), property.CoverBoolean(data_error && !data_error_uncorrectable, Seq("data_correctable_error")), property.CoverBoolean(data_error && data_error_uncorrectable, Seq("data_uncorrectable_error"))) val request_source = Seq( property.CoverBoolean(s2_isSlavePortAccess, Seq("from_TL")), property.CoverBoolean(!s2_isSlavePortAccess, Seq("from_CPU"))) property.cover(new property.CrossProperty( Seq(data_error_cover, request_source), Seq(), "MemorySystem;;Scratchpad Memory Bit Flip Cross Covers")) } else { val data_error_type = Seq( property.CoverBoolean(!s2_valid_data_error, Seq("no_data_error")), property.CoverBoolean(s2_valid_data_error && !s2_data_error_uncorrectable, Seq("data_correctable_error")), property.CoverBoolean(s2_valid_data_error && s2_data_error_uncorrectable, Seq("data_uncorrectable_error"))) val data_error_dirty = Seq( property.CoverBoolean(!s2_victim_dirty, Seq("data_clean")), property.CoverBoolean(s2_victim_dirty, Seq("data_dirty"))) val request_source = if (supports_flush) { Seq( property.CoverBoolean(!flushing, Seq("access")), property.CoverBoolean(flushing, Seq("during_flush"))) } else { Seq(property.CoverBoolean(true.B, Seq("never_flush"))) } val tag_error_cover = Seq( property.CoverBoolean( !s2_meta_error, Seq("no_tag_error")), property.CoverBoolean( s2_meta_error && !s2_meta_error_uncorrectable, Seq("tag_correctable_error")), property.CoverBoolean( s2_meta_error && s2_meta_error_uncorrectable, Seq("tag_uncorrectable_error"))) property.cover(new property.CrossProperty( Seq(data_error_type, data_error_dirty, request_source, tag_error_cover), Seq(), "MemorySystem;;Cache Memory Bit Flip Cross Covers")) } } // leaving gated-clock domain val dcacheImpl = withClock (gated_clock) { new DCacheModuleImpl } def encodeData(x: UInt, poison: Bool) = x.grouped(eccBits).map(dECC.encode(_, if (dECC.canDetect) poison else false.B)).asUInt def dummyEncodeData(x: UInt) = x.grouped(eccBits).map(dECC.swizzle(_)).asUInt def decodeData(x: UInt) = x.grouped(dECC.width(eccBits)).map(dECC.decode(_)) def eccMask(byteMask: UInt) = byteMask.grouped(eccBytes).map(_.orR).asUInt def eccByteMask(byteMask: UInt) = FillInterleaved(eccBytes, eccMask(byteMask)) def likelyNeedsRead(req: HellaCacheReq) = { val res = !req.cmd.isOneOf(M_XWR, M_PFW) || req.size < log2Ceil(eccBytes).U assert(!needsRead(req) || res) res } def needsRead(req: HellaCacheReq) = isRead(req.cmd) || (isWrite(req.cmd) && (req.cmd === M_PWR || req.size < log2Ceil(eccBytes).U)) def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = property.cover(cond, s"DCACHE_$label", "MemorySystem;;" + desc) def ccoverNotScratchpad(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = if (!usingDataScratchpad) ccover(cond, label, desc) require(!usingVM || tagLSB <= pgIdxBits, s"D$$ set size must not exceed ${1<<(pgIdxBits-10)} KiB; got ${(nSets * cacheBlockBytes)>>10} KiB") def tagLSB: Int = untagBits def probeIdx(b: TLBundleB): UInt = b.address(idxMSB, idxLSB) def addressToProbe(vaddr: UInt, paddr: UInt): TLBundleB = { val res = Wire(new TLBundleB(edge.bundle)) res :#= DontCare res.address := paddr res.source := (mmioOffset - 1).U res } def acquire(vaddr: UInt, paddr: UInt, param: UInt): TLBundleA = { if (!edge.manager.anySupportAcquireB) WireDefault(0.U.asTypeOf(new TLBundleA(edge.bundle))) else edge.AcquireBlock(0.U, paddr >> lgCacheBlockBytes << lgCacheBlockBytes, lgCacheBlockBytes.U, param)._2 } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } } File AMOALU.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters class StoreGen(typ: UInt, addr: UInt, dat: UInt, maxSize: Int) { val size = Wire(UInt(log2Up(log2Up(maxSize)+1).W)) size := typ val dat_padded = dat.pad(maxSize*8) def misaligned: Bool = (addr & ((1.U << size) - 1.U)(log2Up(maxSize)-1,0)).orR def mask = { var res = 1.U for (i <- 0 until log2Up(maxSize)) { val upper = Mux(addr(i), res, 0.U) | Mux(size >= (i+1).U, ((BigInt(1) << (1 << i))-1).U, 0.U) val lower = Mux(addr(i), 0.U, res) res = Cat(upper, lower) } res } protected def genData(i: Int): UInt = if (i >= log2Up(maxSize)) dat_padded else Mux(size === i.U, Fill(1 << (log2Up(maxSize)-i), dat_padded((8 << i)-1,0)), genData(i+1)) def data = genData(0) def wordData = genData(2) } class LoadGen(typ: UInt, signed: Bool, addr: UInt, dat: UInt, zero: Bool, maxSize: Int) { private val size = new StoreGen(typ, addr, dat, maxSize).size private def genData(logMinSize: Int): UInt = { var res = dat for (i <- log2Up(maxSize)-1 to logMinSize by -1) { val pos = 8 << i val shifted = Mux(addr(i), res(2*pos-1,pos), res(pos-1,0)) val doZero = (i == 0).B && zero val zeroed = Mux(doZero, 0.U, shifted) res = Cat(Mux(size === i.U || doZero, Fill(8*maxSize-pos, signed && zeroed(pos-1)), res(8*maxSize-1,pos)), zeroed) } res } def wordData = genData(2) def data = genData(0) } class AMOALU(operandBits: Int)(implicit p: Parameters) extends Module { val minXLen = 32 val widths = (0 to log2Ceil(operandBits / minXLen)).map(minXLen << _) val io = IO(new Bundle { val mask = Input(UInt((operandBits / 8).W)) val cmd = Input(UInt(M_SZ.W)) val lhs = Input(UInt(operandBits.W)) val rhs = Input(UInt(operandBits.W)) val out = Output(UInt(operandBits.W)) val out_unmasked = Output(UInt(operandBits.W)) }) val max = io.cmd === M_XA_MAX || io.cmd === M_XA_MAXU val min = io.cmd === M_XA_MIN || io.cmd === M_XA_MINU val add = io.cmd === M_XA_ADD val logic_and = io.cmd === M_XA_OR || io.cmd === M_XA_AND val logic_xor = io.cmd === M_XA_XOR || io.cmd === M_XA_OR val adder_out = { // partition the carry chain to support sub-xLen addition val mask = ~(0.U(operandBits.W) +: widths.init.map(w => !io.mask(w/8-1) << (w-1))).reduce(_|_) (io.lhs & mask) + (io.rhs & mask) } val less = { // break up the comparator so the lower parts will be CSE'd def isLessUnsigned(x: UInt, y: UInt, n: Int): Bool = { if (n == minXLen) x(n-1, 0) < y(n-1, 0) else x(n-1, n/2) < y(n-1, n/2) || x(n-1, n/2) === y(n-1, n/2) && isLessUnsigned(x, y, n/2) } def isLess(x: UInt, y: UInt, n: Int): Bool = { val signed = { val mask = M_XA_MIN ^ M_XA_MINU (io.cmd & mask) === (M_XA_MIN & mask) } Mux(x(n-1) === y(n-1), isLessUnsigned(x, y, n), Mux(signed, x(n-1), y(n-1))) } PriorityMux(widths.reverse.map(w => (io.mask(w/8/2), isLess(io.lhs, io.rhs, w)))) } val minmax = Mux(Mux(less, min, max), io.lhs, io.rhs) val logic = Mux(logic_and, io.lhs & io.rhs, 0.U) | Mux(logic_xor, io.lhs ^ io.rhs, 0.U) val out = Mux(add, adder_out, Mux(logic_and || logic_xor, logic, minmax)) val wmask = FillInterleaved(8, io.mask) io.out := wmask & out | ~wmask & io.lhs io.out_unmasked := out }

module DCache( // @[DCache.scala:101:7] input clock, // @[DCache.scala:101:7] input reset, // @[DCache.scala:101:7] input auto_hart_id_sink_in, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output io_cpu_req_ready, // @[HellaCache.scala:243:14] input io_cpu_req_valid, // @[HellaCache.scala:243:14] input [33:0] io_cpu_req_bits_addr, // @[HellaCache.scala:243:14] input [6:0] io_cpu_req_bits_tag, // @[HellaCache.scala:243:14] input [4:0] io_cpu_req_bits_cmd, // @[HellaCache.scala:243:14] input [1:0] io_cpu_req_bits_size, // @[HellaCache.scala:243:14] input io_cpu_req_bits_signed, // @[HellaCache.scala:243:14] input [1:0] io_cpu_req_bits_dprv, // @[HellaCache.scala:243:14] input io_cpu_req_bits_dv, // @[HellaCache.scala:243:14] input io_cpu_req_bits_phys, // @[HellaCache.scala:243:14] input io_cpu_req_bits_no_resp, // @[HellaCache.scala:243:14] input io_cpu_req_bits_no_xcpt, // @[HellaCache.scala:243:14] input io_cpu_s1_kill, // @[HellaCache.scala:243:14] input [63:0] io_cpu_s1_data_data, // @[HellaCache.scala:243:14] input [7:0] io_cpu_s1_data_mask, // @[HellaCache.scala:243:14] output io_cpu_s2_nack, // @[HellaCache.scala:243:14] output io_cpu_s2_nack_cause_raw, // @[HellaCache.scala:243:14] output io_cpu_s2_uncached, // @[HellaCache.scala:243:14] output [31:0] io_cpu_s2_paddr, // @[HellaCache.scala:243:14] output io_cpu_resp_valid, // @[HellaCache.scala:243:14] output [33:0] io_cpu_resp_bits_addr, // @[HellaCache.scala:243:14] output [6:0] io_cpu_resp_bits_tag, // @[HellaCache.scala:243:14] output [4:0] io_cpu_resp_bits_cmd, // @[HellaCache.scala:243:14] output [1:0] io_cpu_resp_bits_size, // @[HellaCache.scala:243:14] output io_cpu_resp_bits_signed, // @[HellaCache.scala:243:14] output [1:0] io_cpu_resp_bits_dprv, // @[HellaCache.scala:243:14] output io_cpu_resp_bits_dv, // @[HellaCache.scala:243:14] output [63:0] io_cpu_resp_bits_data, // @[HellaCache.scala:243:14] output [7:0] io_cpu_resp_bits_mask, // @[HellaCache.scala:243:14] output io_cpu_resp_bits_replay, // @[HellaCache.scala:243:14] output io_cpu_resp_bits_has_data, // @[HellaCache.scala:243:14] output [63:0] io_cpu_resp_bits_data_word_bypass, // @[HellaCache.scala:243:14] output [63:0] io_cpu_resp_bits_data_raw, // @[HellaCache.scala:243:14] output [63:0] io_cpu_resp_bits_store_data, // @[HellaCache.scala:243:14] output io_cpu_replay_next, // @[HellaCache.scala:243:14] output io_cpu_s2_xcpt_ma_ld, // @[HellaCache.scala:243:14] output io_cpu_s2_xcpt_ma_st, // @[HellaCache.scala:243:14] output io_cpu_s2_xcpt_pf_ld, // @[HellaCache.scala:243:14] output io_cpu_s2_xcpt_pf_st, // @[HellaCache.scala:243:14] output io_cpu_s2_xcpt_ae_ld, // @[HellaCache.scala:243:14] output io_cpu_s2_xcpt_ae_st, // @[HellaCache.scala:243:14] output [33:0] io_cpu_s2_gpa, // @[HellaCache.scala:243:14] output io_cpu_ordered, // @[HellaCache.scala:243:14] output io_cpu_store_pending, // @[HellaCache.scala:243:14] output io_cpu_perf_acquire, // @[HellaCache.scala:243:14] output io_cpu_perf_grant, // @[HellaCache.scala:243:14] output io_cpu_perf_blocked, // @[HellaCache.scala:243:14] output io_cpu_perf_canAcceptStoreThenLoad, // @[HellaCache.scala:243:14] output io_cpu_perf_canAcceptStoreThenRMW, // @[HellaCache.scala:243:14] output io_cpu_perf_canAcceptLoadThenLoad, // @[HellaCache.scala:243:14] output io_cpu_perf_storeBufferEmptyAfterLoad, // @[HellaCache.scala:243:14] output io_cpu_perf_storeBufferEmptyAfterStore, // @[HellaCache.scala:243:14] input io_cpu_keep_clock_enabled, // @[HellaCache.scala:243:14] input io_ptw_req_ready, // @[HellaCache.scala:243:14] output [20:0] io_ptw_req_bits_bits_addr, // @[HellaCache.scala:243:14] output io_ptw_req_bits_bits_need_gpa, // @[HellaCache.scala:243:14] output io_ptw_req_bits_bits_vstage1, // @[HellaCache.scala:243:14] output io_ptw_req_bits_bits_stage2, // @[HellaCache.scala:243:14] input io_ptw_resp_valid, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_ae_ptw, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_ae_final, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_pf, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_gf, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_hr, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_hw, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_hx, // @[HellaCache.scala:243:14] input [9:0] io_ptw_resp_bits_pte_reserved_for_future, // @[HellaCache.scala:243:14] input [43:0] io_ptw_resp_bits_pte_ppn, // @[HellaCache.scala:243:14] input [1:0] io_ptw_resp_bits_pte_reserved_for_software, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_pte_d, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_pte_a, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_pte_g, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_pte_u, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_pte_x, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_pte_w, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_pte_r, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_pte_v, // @[HellaCache.scala:243:14] input [1:0] io_ptw_resp_bits_level, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_homogeneous, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_gpa_valid, // @[HellaCache.scala:243:14] input [32:0] io_ptw_resp_bits_gpa_bits, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_gpa_is_pte, // @[HellaCache.scala:243:14] input io_ptw_status_debug, // @[HellaCache.scala:243:14] input io_ptw_status_cease, // @[HellaCache.scala:243:14] input io_ptw_status_wfi, // @[HellaCache.scala:243:14] input [31:0] io_ptw_status_isa, // @[HellaCache.scala:243:14] input io_ptw_status_dv, // @[HellaCache.scala:243:14] input io_ptw_status_v, // @[HellaCache.scala:243:14] input io_ptw_status_sd, // @[HellaCache.scala:243:14] input io_ptw_status_mpv, // @[HellaCache.scala:243:14] input io_ptw_status_gva, // @[HellaCache.scala:243:14] input [1:0] io_ptw_status_fs, // @[HellaCache.scala:243:14] input [1:0] io_ptw_status_mpp, // @[HellaCache.scala:243:14] input io_ptw_status_mpie, // @[HellaCache.scala:243:14] input io_ptw_status_mie, // @[HellaCache.scala:243:14] input io_ptw_gstatus_debug, // @[HellaCache.scala:243:14] input io_ptw_gstatus_cease, // @[HellaCache.scala:243:14] input io_ptw_gstatus_wfi, // @[HellaCache.scala:243:14] input [31:0] io_ptw_gstatus_isa, // @[HellaCache.scala:243:14] input [1:0] io_ptw_gstatus_dprv, // @[HellaCache.scala:243:14] input io_ptw_gstatus_dv, // @[HellaCache.scala:243:14] input [1:0] io_ptw_gstatus_prv, // @[HellaCache.scala:243:14] input io_ptw_gstatus_v, // @[HellaCache.scala:243:14] input io_ptw_gstatus_sd, // @[HellaCache.scala:243:14] input [22:0] io_ptw_gstatus_zero2, // @[HellaCache.scala:243:14] input io_ptw_gstatus_mpv, // @[HellaCache.scala:243:14] input io_ptw_gstatus_gva, // @[HellaCache.scala:243:14] input io_ptw_gstatus_mbe, // @[HellaCache.scala:243:14] input io_ptw_gstatus_sbe, // @[HellaCache.scala:243:14] input [1:0] io_ptw_gstatus_sxl, // @[HellaCache.scala:243:14] input [7:0] io_ptw_gstatus_zero1, // @[HellaCache.scala:243:14] input io_ptw_gstatus_tsr, // @[HellaCache.scala:243:14] input io_ptw_gstatus_tw, // @[HellaCache.scala:243:14] input io_ptw_gstatus_tvm, // @[HellaCache.scala:243:14] input io_ptw_gstatus_mxr, // @[HellaCache.scala:243:14] input io_ptw_gstatus_sum, // @[HellaCache.scala:243:14] input io_ptw_gstatus_mprv, // @[HellaCache.scala:243:14] input [1:0] io_ptw_gstatus_fs, // @[HellaCache.scala:243:14] input [1:0] io_ptw_gstatus_mpp, // @[HellaCache.scala:243:14] input [1:0] io_ptw_gstatus_vs, // @[HellaCache.scala:243:14] input io_ptw_gstatus_spp, // @[HellaCache.scala:243:14] input io_ptw_gstatus_mpie, // @[HellaCache.scala:243:14] input io_ptw_gstatus_ube, // @[HellaCache.scala:243:14] input io_ptw_gstatus_spie, // @[HellaCache.scala:243:14] input io_ptw_gstatus_upie, // @[HellaCache.scala:243:14] input io_ptw_gstatus_mie, // @[HellaCache.scala:243:14] input io_ptw_gstatus_hie, // @[HellaCache.scala:243:14] input io_ptw_gstatus_sie, // @[HellaCache.scala:243:14] input io_ptw_gstatus_uie, // @[HellaCache.scala:243:14] input io_ptw_pmp_0_cfg_l, // @[HellaCache.scala:243:14] input [1:0] io_ptw_pmp_0_cfg_a, // @[HellaCache.scala:243:14] input io_ptw_pmp_0_cfg_x, // @[HellaCache.scala:243:14] input io_ptw_pmp_0_cfg_w, // @[HellaCache.scala:243:14] input io_ptw_pmp_0_cfg_r, // @[HellaCache.scala:243:14] input [29:0] io_ptw_pmp_0_addr, // @[HellaCache.scala:243:14] input [31:0] io_ptw_pmp_0_mask, // @[HellaCache.scala:243:14] input io_ptw_pmp_1_cfg_l, // @[HellaCache.scala:243:14] input [1:0] io_ptw_pmp_1_cfg_a, // @[HellaCache.scala:243:14] input io_ptw_pmp_1_cfg_x, // @[HellaCache.scala:243:14] input io_ptw_pmp_1_cfg_w, // @[HellaCache.scala:243:14] input io_ptw_pmp_1_cfg_r, // @[HellaCache.scala:243:14] input [29:0] io_ptw_pmp_1_addr, // @[HellaCache.scala:243:14] input [31:0] io_ptw_pmp_1_mask, // @[HellaCache.scala:243:14] input io_ptw_pmp_2_cfg_l, // @[HellaCache.scala:243:14] input [1:0] io_ptw_pmp_2_cfg_a, // @[HellaCache.scala:243:14] input io_ptw_pmp_2_cfg_x, // @[HellaCache.scala:243:14] input io_ptw_pmp_2_cfg_w, // @[HellaCache.scala:243:14] input io_ptw_pmp_2_cfg_r, // @[HellaCache.scala:243:14] input [29:0] io_ptw_pmp_2_addr, // @[HellaCache.scala:243:14] input [31:0] io_ptw_pmp_2_mask, // @[HellaCache.scala:243:14] input io_ptw_pmp_3_cfg_l, // @[HellaCache.scala:243:14] input [1:0] io_ptw_pmp_3_cfg_a, // @[HellaCache.scala:243:14] input io_ptw_pmp_3_cfg_x, // @[HellaCache.scala:243:14] input io_ptw_pmp_3_cfg_w, // @[HellaCache.scala:243:14] input io_ptw_pmp_3_cfg_r, // @[HellaCache.scala:243:14] input [29:0] io_ptw_pmp_3_addr, // @[HellaCache.scala:243:14] input [31:0] io_ptw_pmp_3_mask, // @[HellaCache.scala:243:14] input io_ptw_pmp_4_cfg_l, // @[HellaCache.scala:243:14] input [1:0] io_ptw_pmp_4_cfg_a, // @[HellaCache.scala:243:14] input io_ptw_pmp_4_cfg_x, // @[HellaCache.scala:243:14] input io_ptw_pmp_4_cfg_w, // @[HellaCache.scala:243:14] input io_ptw_pmp_4_cfg_r, // @[HellaCache.scala:243:14] input [29:0] io_ptw_pmp_4_addr, // @[HellaCache.scala:243:14] input [31:0] io_ptw_pmp_4_mask, // @[HellaCache.scala:243:14] input io_ptw_pmp_5_cfg_l, // @[HellaCache.scala:243:14] input [1:0] io_ptw_pmp_5_cfg_a, // @[HellaCache.scala:243:14] input io_ptw_pmp_5_cfg_x, // @[HellaCache.scala:243:14] input io_ptw_pmp_5_cfg_w, // @[HellaCache.scala:243:14] input io_ptw_pmp_5_cfg_r, // @[HellaCache.scala:243:14] input [29:0] io_ptw_pmp_5_addr, // @[HellaCache.scala:243:14] input [31:0] io_ptw_pmp_5_mask, // @[HellaCache.scala:243:14] input io_ptw_pmp_6_cfg_l, // @[HellaCache.scala:243:14] input [1:0] io_ptw_pmp_6_cfg_a, // @[HellaCache.scala:243:14] input io_ptw_pmp_6_cfg_x, // @[HellaCache.scala:243:14] input io_ptw_pmp_6_cfg_w, // @[HellaCache.scala:243:14] input io_ptw_pmp_6_cfg_r, // @[HellaCache.scala:243:14] input [29:0] io_ptw_pmp_6_addr, // @[HellaCache.scala:243:14] input [31:0] io_ptw_pmp_6_mask, // @[HellaCache.scala:243:14] input io_ptw_pmp_7_cfg_l, // @[HellaCache.scala:243:14] input [1:0] io_ptw_pmp_7_cfg_a, // @[HellaCache.scala:243:14] input io_ptw_pmp_7_cfg_x, // @[HellaCache.scala:243:14] input io_ptw_pmp_7_cfg_w, // @[HellaCache.scala:243:14] input io_ptw_pmp_7_cfg_r, // @[HellaCache.scala:243:14] input [29:0] io_ptw_pmp_7_addr, // @[HellaCache.scala:243:14] input [31:0] io_ptw_pmp_7_mask, // @[HellaCache.scala:243:14] input io_ptw_customCSRs_csrs_0_ren, // @[HellaCache.scala:243:14] input io_ptw_customCSRs_csrs_0_wen, // @[HellaCache.scala:243:14] input [63:0] io_ptw_customCSRs_csrs_0_wdata, // @[HellaCache.scala:243:14] input [63:0] io_ptw_customCSRs_csrs_0_value, // @[HellaCache.scala:243:14] input io_ptw_customCSRs_csrs_1_ren, // @[HellaCache.scala:243:14] input io_ptw_customCSRs_csrs_1_wen, // @[HellaCache.scala:243:14] input [63:0] io_ptw_customCSRs_csrs_1_wdata, // @[HellaCache.scala:243:14] input [63:0] io_ptw_customCSRs_csrs_1_value, // @[HellaCache.scala:243:14] input io_ptw_customCSRs_csrs_2_ren, // @[HellaCache.scala:243:14] input io_ptw_customCSRs_csrs_2_wen, // @[HellaCache.scala:243:14] input [63:0] io_ptw_customCSRs_csrs_2_wdata, // @[HellaCache.scala:243:14] input [63:0] io_ptw_customCSRs_csrs_2_value, // @[HellaCache.scala:243:14] input io_ptw_customCSRs_csrs_3_ren, // @[HellaCache.scala:243:14] input io_ptw_customCSRs_csrs_3_wen, // @[HellaCache.scala:243:14] input [63:0] io_ptw_customCSRs_csrs_3_wdata, // @[HellaCache.scala:243:14] input [63:0] io_ptw_customCSRs_csrs_3_value // @[HellaCache.scala:243:14] ); wire [63:0] s1_all_data_ways_0; // @[DCache.scala:325:33] wire s0_req_phys; // @[DCache.scala:192:24] wire [33:0] s0_req_addr; // @[DCache.scala:192:24] wire tl_out_a_valid; // @[DCache.scala:159:22] wire [63:0] tl_out_a_bits_data; // @[DCache.scala:159:22] wire [7:0] tl_out_a_bits_mask; // @[DCache.scala:159:22] wire [31:0] tl_out_a_bits_address; // @[DCache.scala:159:22] wire [3:0] tl_out_a_bits_size; // @[DCache.scala:159:22] wire [2:0] tl_out_a_bits_param; // @[DCache.scala:159:22] wire [2:0] tl_out_a_bits_opcode; // @[DCache.scala:159:22] wire metaArb_io_in_2_valid; // @[DCache.scala:135:28] wire [4:0] pma_checker_io_req_bits_cmd; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_req_bits_size; // @[DCache.scala:120:32] wire [63:0] _amoalus_0_io_out_unmasked; // @[DCache.scala:982:26] wire _lfsr_prng_io_out_0; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_1; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_2; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_3; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_4; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_5; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_6; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_7; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_8; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_9; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_10; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_11; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_12; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_13; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_14; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_15; // @[PRNG.scala:91:22] wire _pma_checker_entries_barrier_12_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_c; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_c; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_c; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_c; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_c; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_c; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_c; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_c; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_c; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_c; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_c; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_c; // @[package.scala:267:25] wire _pma_checker_pma_io_resp_r; // @[TLB.scala:422:19] wire _pma_checker_pma_io_resp_w; // @[TLB.scala:422:19] wire _pma_checker_pma_io_resp_pp; // @[TLB.scala:422:19] wire _pma_checker_pma_io_resp_al; // @[TLB.scala:422:19] wire _pma_checker_pma_io_resp_aa; // @[TLB.scala:422:19] wire _pma_checker_pma_io_resp_x; // @[TLB.scala:422:19] wire _pma_checker_pma_io_resp_eff; // @[TLB.scala:422:19] wire _pma_checker_pmp_io_r; // @[TLB.scala:416:19] wire _pma_checker_pmp_io_w; // @[TLB.scala:416:19] wire _pma_checker_pmp_io_x; // @[TLB.scala:416:19] wire [31:0] _tlb_io_resp_paddr; // @[DCache.scala:119:19] wire [33:0] _tlb_io_resp_gpa; // @[DCache.scala:119:19] wire _tlb_io_resp_pf_ld; // @[DCache.scala:119:19] wire _tlb_io_resp_pf_st; // @[DCache.scala:119:19] wire _tlb_io_resp_pf_inst; // @[DCache.scala:119:19] wire _tlb_io_resp_ae_ld; // @[DCache.scala:119:19] wire _tlb_io_resp_ae_st; // @[DCache.scala:119:19] wire _tlb_io_resp_ae_inst; // @[DCache.scala:119:19] wire _tlb_io_resp_ma_ld; // @[DCache.scala:119:19] wire _tlb_io_resp_ma_st; // @[DCache.scala:119:19] wire _tlb_io_resp_cacheable; // @[DCache.scala:119:19] wire _tlb_io_resp_must_alloc; // @[DCache.scala:119:19] wire _tlb_io_resp_prefetchable; // @[DCache.scala:119:19] wire [1:0] _tlb_io_resp_size; // @[DCache.scala:119:19] wire [4:0] _tlb_io_resp_cmd; // @[DCache.scala:119:19] wire auto_hart_id_sink_in_0 = auto_hart_id_sink_in; // @[DCache.scala:101:7] wire auto_out_a_ready_0 = auto_out_a_ready; // @[DCache.scala:101:7] wire auto_out_d_valid_0 = auto_out_d_valid; // @[DCache.scala:101:7] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[DCache.scala:101:7] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[DCache.scala:101:7] wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[DCache.scala:101:7] wire auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[DCache.scala:101:7] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[DCache.scala:101:7] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[DCache.scala:101:7] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[DCache.scala:101:7] wire io_cpu_req_valid_0 = io_cpu_req_valid; // @[DCache.scala:101:7] wire [33:0] io_cpu_req_bits_addr_0 = io_cpu_req_bits_addr; // @[DCache.scala:101:7] wire [6:0] io_cpu_req_bits_tag_0 = io_cpu_req_bits_tag; // @[DCache.scala:101:7] wire [4:0] io_cpu_req_bits_cmd_0 = io_cpu_req_bits_cmd; // @[DCache.scala:101:7] wire [1:0] io_cpu_req_bits_size_0 = io_cpu_req_bits_size; // @[DCache.scala:101:7] wire io_cpu_req_bits_signed_0 = io_cpu_req_bits_signed; // @[DCache.scala:101:7] wire [1:0] io_cpu_req_bits_dprv_0 = io_cpu_req_bits_dprv; // @[DCache.scala:101:7] wire io_cpu_req_bits_dv_0 = io_cpu_req_bits_dv; // @[DCache.scala:101:7] wire io_cpu_req_bits_phys_0 = io_cpu_req_bits_phys; // @[DCache.scala:101:7] wire io_cpu_req_bits_no_resp_0 = io_cpu_req_bits_no_resp; // @[DCache.scala:101:7] wire io_cpu_req_bits_no_xcpt_0 = io_cpu_req_bits_no_xcpt; // @[DCache.scala:101:7] wire io_cpu_s1_kill_0 = io_cpu_s1_kill; // @[DCache.scala:101:7] wire [63:0] io_cpu_s1_data_data_0 = io_cpu_s1_data_data; // @[DCache.scala:101:7] wire [7:0] io_cpu_s1_data_mask_0 = io_cpu_s1_data_mask; // @[DCache.scala:101:7] wire io_cpu_keep_clock_enabled_0 = io_cpu_keep_clock_enabled; // @[DCache.scala:101:7] wire io_ptw_req_ready_0 = io_ptw_req_ready; // @[DCache.scala:101:7] wire io_ptw_resp_valid_0 = io_ptw_resp_valid; // @[DCache.scala:101:7] wire io_ptw_resp_bits_ae_ptw_0 = io_ptw_resp_bits_ae_ptw; // @[DCache.scala:101:7] wire io_ptw_resp_bits_ae_final_0 = io_ptw_resp_bits_ae_final; // @[DCache.scala:101:7] wire io_ptw_resp_bits_pf_0 = io_ptw_resp_bits_pf; // @[DCache.scala:101:7] wire io_ptw_resp_bits_gf_0 = io_ptw_resp_bits_gf; // @[DCache.scala:101:7] wire io_ptw_resp_bits_hr_0 = io_ptw_resp_bits_hr; // @[DCache.scala:101:7] wire io_ptw_resp_bits_hw_0 = io_ptw_resp_bits_hw; // @[DCache.scala:101:7] wire io_ptw_resp_bits_hx_0 = io_ptw_resp_bits_hx; // @[DCache.scala:101:7] wire [9:0] io_ptw_resp_bits_pte_reserved_for_future_0 = io_ptw_resp_bits_pte_reserved_for_future; // @[DCache.scala:101:7] wire [43:0] io_ptw_resp_bits_pte_ppn_0 = io_ptw_resp_bits_pte_ppn; // @[DCache.scala:101:7] wire [1:0] io_ptw_resp_bits_pte_reserved_for_software_0 = io_ptw_resp_bits_pte_reserved_for_software; // @[DCache.scala:101:7] wire io_ptw_resp_bits_pte_d_0 = io_ptw_resp_bits_pte_d; // @[DCache.scala:101:7] wire io_ptw_resp_bits_pte_a_0 = io_ptw_resp_bits_pte_a; // @[DCache.scala:101:7] wire io_ptw_resp_bits_pte_g_0 = io_ptw_resp_bits_pte_g; // @[DCache.scala:101:7] wire io_ptw_resp_bits_pte_u_0 = io_ptw_resp_bits_pte_u; // @[DCache.scala:101:7] wire io_ptw_resp_bits_pte_x_0 = io_ptw_resp_bits_pte_x; // @[DCache.scala:101:7] wire io_ptw_resp_bits_pte_w_0 = io_ptw_resp_bits_pte_w; // @[DCache.scala:101:7] wire io_ptw_resp_bits_pte_r_0 = io_ptw_resp_bits_pte_r; // @[DCache.scala:101:7] wire io_ptw_resp_bits_pte_v_0 = io_ptw_resp_bits_pte_v; // @[DCache.scala:101:7] wire [1:0] io_ptw_resp_bits_level_0 = io_ptw_resp_bits_level; // @[DCache.scala:101:7] wire io_ptw_resp_bits_homogeneous_0 = io_ptw_resp_bits_homogeneous; // @[DCache.scala:101:7] wire io_ptw_resp_bits_gpa_valid_0 = io_ptw_resp_bits_gpa_valid; // @[DCache.scala:101:7] wire [32:0] io_ptw_resp_bits_gpa_bits_0 = io_ptw_resp_bits_gpa_bits; // @[DCache.scala:101:7] wire io_ptw_resp_bits_gpa_is_pte_0 = io_ptw_resp_bits_gpa_is_pte; // @[DCache.scala:101:7] wire io_ptw_status_debug_0 = io_ptw_status_debug; // @[DCache.scala:101:7] wire io_ptw_status_cease_0 = io_ptw_status_cease; // @[DCache.scala:101:7] wire io_ptw_status_wfi_0 = io_ptw_status_wfi; // @[DCache.scala:101:7] wire [31:0] io_ptw_status_isa_0 = io_ptw_status_isa; // @[DCache.scala:101:7] wire io_ptw_status_dv_0 = io_ptw_status_dv; // @[DCache.scala:101:7] wire io_ptw_status_v_0 = io_ptw_status_v; // @[DCache.scala:101:7] wire io_ptw_status_sd_0 = io_ptw_status_sd; // @[DCache.scala:101:7] wire io_ptw_status_mpv_0 = io_ptw_status_mpv; // @[DCache.scala:101:7] wire io_ptw_status_gva_0 = io_ptw_status_gva; // @[DCache.scala:101:7] wire [1:0] io_ptw_status_fs_0 = io_ptw_status_fs; // @[DCache.scala:101:7] wire [1:0] io_ptw_status_mpp_0 = io_ptw_status_mpp; // @[DCache.scala:101:7] wire io_ptw_status_mpie_0 = io_ptw_status_mpie; // @[DCache.scala:101:7] wire io_ptw_status_mie_0 = io_ptw_status_mie; // @[DCache.scala:101:7] wire io_ptw_gstatus_debug_0 = io_ptw_gstatus_debug; // @[DCache.scala:101:7] wire io_ptw_gstatus_cease_0 = io_ptw_gstatus_cease; // @[DCache.scala:101:7] wire io_ptw_gstatus_wfi_0 = io_ptw_gstatus_wfi; // @[DCache.scala:101:7] wire [31:0] io_ptw_gstatus_isa_0 = io_ptw_gstatus_isa; // @[DCache.scala:101:7] wire [1:0] io_ptw_gstatus_dprv_0 = io_ptw_gstatus_dprv; // @[DCache.scala:101:7] wire io_ptw_gstatus_dv_0 = io_ptw_gstatus_dv; // @[DCache.scala:101:7] wire [1:0] io_ptw_gstatus_prv_0 = io_ptw_gstatus_prv; // @[DCache.scala:101:7] wire io_ptw_gstatus_v_0 = io_ptw_gstatus_v; // @[DCache.scala:101:7] wire io_ptw_gstatus_sd_0 = io_ptw_gstatus_sd; // @[DCache.scala:101:7] wire [22:0] io_ptw_gstatus_zero2_0 = io_ptw_gstatus_zero2; // @[DCache.scala:101:7] wire io_ptw_gstatus_mpv_0 = io_ptw_gstatus_mpv; // @[DCache.scala:101:7] wire io_ptw_gstatus_gva_0 = io_ptw_gstatus_gva; // @[DCache.scala:101:7] wire io_ptw_gstatus_mbe_0 = io_ptw_gstatus_mbe; // @[DCache.scala:101:7] wire io_ptw_gstatus_sbe_0 = io_ptw_gstatus_sbe; // @[DCache.scala:101:7] wire [1:0] io_ptw_gstatus_sxl_0 = io_ptw_gstatus_sxl; // @[DCache.scala:101:7] wire [7:0] io_ptw_gstatus_zero1_0 = io_ptw_gstatus_zero1; // @[DCache.scala:101:7] wire io_ptw_gstatus_tsr_0 = io_ptw_gstatus_tsr; // @[DCache.scala:101:7] wire io_ptw_gstatus_tw_0 = io_ptw_gstatus_tw; // @[DCache.scala:101:7] wire io_ptw_gstatus_tvm_0 = io_ptw_gstatus_tvm; // @[DCache.scala:101:7] wire io_ptw_gstatus_mxr_0 = io_ptw_gstatus_mxr; // @[DCache.scala:101:7] wire io_ptw_gstatus_sum_0 = io_ptw_gstatus_sum; // @[DCache.scala:101:7] wire io_ptw_gstatus_mprv_0 = io_ptw_gstatus_mprv; // @[DCache.scala:101:7] wire [1:0] io_ptw_gstatus_fs_0 = io_ptw_gstatus_fs; // @[DCache.scala:101:7] wire [1:0] io_ptw_gstatus_mpp_0 = io_ptw_gstatus_mpp; // @[DCache.scala:101:7] wire [1:0] io_ptw_gstatus_vs_0 = io_ptw_gstatus_vs; // @[DCache.scala:101:7] wire io_ptw_gstatus_spp_0 = io_ptw_gstatus_spp; // @[DCache.scala:101:7] wire io_ptw_gstatus_mpie_0 = io_ptw_gstatus_mpie; // @[DCache.scala:101:7] wire io_ptw_gstatus_ube_0 = io_ptw_gstatus_ube; // @[DCache.scala:101:7] wire io_ptw_gstatus_spie_0 = io_ptw_gstatus_spie; // @[DCache.scala:101:7] wire io_ptw_gstatus_upie_0 = io_ptw_gstatus_upie; // @[DCache.scala:101:7] wire io_ptw_gstatus_mie_0 = io_ptw_gstatus_mie; // @[DCache.scala:101:7] wire io_ptw_gstatus_hie_0 = io_ptw_gstatus_hie; // @[DCache.scala:101:7] wire io_ptw_gstatus_sie_0 = io_ptw_gstatus_sie; // @[DCache.scala:101:7] wire io_ptw_gstatus_uie_0 = io_ptw_gstatus_uie; // @[DCache.scala:101:7] wire io_ptw_pmp_0_cfg_l_0 = io_ptw_pmp_0_cfg_l; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_0_cfg_a_0 = io_ptw_pmp_0_cfg_a; // @[DCache.scala:101:7] wire io_ptw_pmp_0_cfg_x_0 = io_ptw_pmp_0_cfg_x; // @[DCache.scala:101:7] wire io_ptw_pmp_0_cfg_w_0 = io_ptw_pmp_0_cfg_w; // @[DCache.scala:101:7] wire io_ptw_pmp_0_cfg_r_0 = io_ptw_pmp_0_cfg_r; // @[DCache.scala:101:7] wire [29:0] io_ptw_pmp_0_addr_0 = io_ptw_pmp_0_addr; // @[DCache.scala:101:7] wire [31:0] io_ptw_pmp_0_mask_0 = io_ptw_pmp_0_mask; // @[DCache.scala:101:7] wire io_ptw_pmp_1_cfg_l_0 = io_ptw_pmp_1_cfg_l; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_1_cfg_a_0 = io_ptw_pmp_1_cfg_a; // @[DCache.scala:101:7] wire io_ptw_pmp_1_cfg_x_0 = io_ptw_pmp_1_cfg_x; // @[DCache.scala:101:7] wire io_ptw_pmp_1_cfg_w_0 = io_ptw_pmp_1_cfg_w; // @[DCache.scala:101:7] wire io_ptw_pmp_1_cfg_r_0 = io_ptw_pmp_1_cfg_r; // @[DCache.scala:101:7] wire [29:0] io_ptw_pmp_1_addr_0 = io_ptw_pmp_1_addr; // @[DCache.scala:101:7] wire [31:0] io_ptw_pmp_1_mask_0 = io_ptw_pmp_1_mask; // @[DCache.scala:101:7] wire io_ptw_pmp_2_cfg_l_0 = io_ptw_pmp_2_cfg_l; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_2_cfg_a_0 = io_ptw_pmp_2_cfg_a; // @[DCache.scala:101:7] wire io_ptw_pmp_2_cfg_x_0 = io_ptw_pmp_2_cfg_x; // @[DCache.scala:101:7] wire io_ptw_pmp_2_cfg_w_0 = io_ptw_pmp_2_cfg_w; // @[DCache.scala:101:7] wire io_ptw_pmp_2_cfg_r_0 = io_ptw_pmp_2_cfg_r; // @[DCache.scala:101:7] wire [29:0] io_ptw_pmp_2_addr_0 = io_ptw_pmp_2_addr; // @[DCache.scala:101:7] wire [31:0] io_ptw_pmp_2_mask_0 = io_ptw_pmp_2_mask; // @[DCache.scala:101:7] wire io_ptw_pmp_3_cfg_l_0 = io_ptw_pmp_3_cfg_l; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_3_cfg_a_0 = io_ptw_pmp_3_cfg_a; // @[DCache.scala:101:7] wire io_ptw_pmp_3_cfg_x_0 = io_ptw_pmp_3_cfg_x; // @[DCache.scala:101:7] wire io_ptw_pmp_3_cfg_w_0 = io_ptw_pmp_3_cfg_w; // @[DCache.scala:101:7] wire io_ptw_pmp_3_cfg_r_0 = io_ptw_pmp_3_cfg_r; // @[DCache.scala:101:7] wire [29:0] io_ptw_pmp_3_addr_0 = io_ptw_pmp_3_addr; // @[DCache.scala:101:7] wire [31:0] io_ptw_pmp_3_mask_0 = io_ptw_pmp_3_mask; // @[DCache.scala:101:7] wire io_ptw_pmp_4_cfg_l_0 = io_ptw_pmp_4_cfg_l; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_4_cfg_a_0 = io_ptw_pmp_4_cfg_a; // @[DCache.scala:101:7] wire io_ptw_pmp_4_cfg_x_0 = io_ptw_pmp_4_cfg_x; // @[DCache.scala:101:7] wire io_ptw_pmp_4_cfg_w_0 = io_ptw_pmp_4_cfg_w; // @[DCache.scala:101:7] wire io_ptw_pmp_4_cfg_r_0 = io_ptw_pmp_4_cfg_r; // @[DCache.scala:101:7] wire [29:0] io_ptw_pmp_4_addr_0 = io_ptw_pmp_4_addr; // @[DCache.scala:101:7] wire [31:0] io_ptw_pmp_4_mask_0 = io_ptw_pmp_4_mask; // @[DCache.scala:101:7] wire io_ptw_pmp_5_cfg_l_0 = io_ptw_pmp_5_cfg_l; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_5_cfg_a_0 = io_ptw_pmp_5_cfg_a; // @[DCache.scala:101:7] wire io_ptw_pmp_5_cfg_x_0 = io_ptw_pmp_5_cfg_x; // @[DCache.scala:101:7] wire io_ptw_pmp_5_cfg_w_0 = io_ptw_pmp_5_cfg_w; // @[DCache.scala:101:7] wire io_ptw_pmp_5_cfg_r_0 = io_ptw_pmp_5_cfg_r; // @[DCache.scala:101:7] wire [29:0] io_ptw_pmp_5_addr_0 = io_ptw_pmp_5_addr; // @[DCache.scala:101:7] wire [31:0] io_ptw_pmp_5_mask_0 = io_ptw_pmp_5_mask; // @[DCache.scala:101:7] wire io_ptw_pmp_6_cfg_l_0 = io_ptw_pmp_6_cfg_l; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_6_cfg_a_0 = io_ptw_pmp_6_cfg_a; // @[DCache.scala:101:7] wire io_ptw_pmp_6_cfg_x_0 = io_ptw_pmp_6_cfg_x; // @[DCache.scala:101:7] wire io_ptw_pmp_6_cfg_w_0 = io_ptw_pmp_6_cfg_w; // @[DCache.scala:101:7] wire io_ptw_pmp_6_cfg_r_0 = io_ptw_pmp_6_cfg_r; // @[DCache.scala:101:7] wire [29:0] io_ptw_pmp_6_addr_0 = io_ptw_pmp_6_addr; // @[DCache.scala:101:7] wire [31:0] io_ptw_pmp_6_mask_0 = io_ptw_pmp_6_mask; // @[DCache.scala:101:7] wire io_ptw_pmp_7_cfg_l_0 = io_ptw_pmp_7_cfg_l; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_7_cfg_a_0 = io_ptw_pmp_7_cfg_a; // @[DCache.scala:101:7] wire io_ptw_pmp_7_cfg_x_0 = io_ptw_pmp_7_cfg_x; // @[DCache.scala:101:7] wire io_ptw_pmp_7_cfg_w_0 = io_ptw_pmp_7_cfg_w; // @[DCache.scala:101:7] wire io_ptw_pmp_7_cfg_r_0 = io_ptw_pmp_7_cfg_r; // @[DCache.scala:101:7] wire [29:0] io_ptw_pmp_7_addr_0 = io_ptw_pmp_7_addr; // @[DCache.scala:101:7] wire [31:0] io_ptw_pmp_7_mask_0 = io_ptw_pmp_7_mask; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_0_ren_0 = io_ptw_customCSRs_csrs_0_ren; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_0_wen_0 = io_ptw_customCSRs_csrs_0_wen; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_0_wdata_0 = io_ptw_customCSRs_csrs_0_wdata; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_0_value_0 = io_ptw_customCSRs_csrs_0_value; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_1_ren_0 = io_ptw_customCSRs_csrs_1_ren; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_1_wen_0 = io_ptw_customCSRs_csrs_1_wen; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_1_wdata_0 = io_ptw_customCSRs_csrs_1_wdata; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_1_value_0 = io_ptw_customCSRs_csrs_1_value; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_2_ren_0 = io_ptw_customCSRs_csrs_2_ren; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_2_wen_0 = io_ptw_customCSRs_csrs_2_wen; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_2_wdata_0 = io_ptw_customCSRs_csrs_2_wdata; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_2_value_0 = io_ptw_customCSRs_csrs_2_value; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_3_ren_0 = io_ptw_customCSRs_csrs_3_ren; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_3_wen_0 = io_ptw_customCSRs_csrs_3_wen; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_3_wdata_0 = io_ptw_customCSRs_csrs_3_wdata; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_3_value_0 = io_ptw_customCSRs_csrs_3_value; // @[DCache.scala:101:7] wire _dataArb_io_in_3_valid_T_55 = reset; // @[DCache.scala:1186:11] wire _pstore_drain_opportunistic_T_55 = reset; // @[DCache.scala:1186:11] wire auto_mmio_address_prefix_sink_in = 1'h0; // @[DCache.scala:101:7] wire auto_out_a_bits_source = 1'h0; // @[DCache.scala:101:7] wire auto_out_a_bits_corrupt = 1'h0; // @[DCache.scala:101:7] wire auto_out_d_bits_source = 1'h0; // @[DCache.scala:101:7] wire io_cpu_req_bits_no_alloc = 1'h0; // @[DCache.scala:101:7] wire io_cpu_s2_kill = 1'h0; // @[DCache.scala:101:7] wire io_cpu_s2_xcpt_gf_ld = 1'h0; // @[DCache.scala:101:7] wire io_cpu_s2_xcpt_gf_st = 1'h0; // @[DCache.scala:101:7] wire io_cpu_s2_gpa_is_pte = 1'h0; // @[DCache.scala:101:7] wire io_cpu_perf_release = 1'h0; // @[DCache.scala:101:7] wire io_cpu_perf_tlbMiss = 1'h0; // @[DCache.scala:101:7] wire io_ptw_req_valid = 1'h0; // @[DCache.scala:101:7] wire io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[DCache.scala:101:7] wire io_ptw_status_mbe = 1'h0; // @[DCache.scala:101:7] wire io_ptw_status_sbe = 1'h0; // @[DCache.scala:101:7] wire io_ptw_status_sd_rv32 = 1'h0; // @[DCache.scala:101:7] wire io_ptw_status_tsr = 1'h0; // @[DCache.scala:101:7] wire io_ptw_status_tw = 1'h0; // @[DCache.scala:101:7] wire io_ptw_status_tvm = 1'h0; // @[DCache.scala:101:7] wire io_ptw_status_mxr = 1'h0; // @[DCache.scala:101:7] wire io_ptw_status_sum = 1'h0; // @[DCache.scala:101:7] wire io_ptw_status_mprv = 1'h0; // @[DCache.scala:101:7] wire io_ptw_status_spp = 1'h0; // @[DCache.scala:101:7] wire io_ptw_status_ube = 1'h0; // @[DCache.scala:101:7] wire io_ptw_status_spie = 1'h0; // @[DCache.scala:101:7] wire io_ptw_status_upie = 1'h0; // @[DCache.scala:101:7] wire io_ptw_status_hie = 1'h0; // @[DCache.scala:101:7] wire io_ptw_status_sie = 1'h0; // @[DCache.scala:101:7] wire io_ptw_status_uie = 1'h0; // @[DCache.scala:101:7] wire io_ptw_hstatus_vtsr = 1'h0; // @[DCache.scala:101:7] wire io_ptw_hstatus_vtw = 1'h0; // @[DCache.scala:101:7] wire io_ptw_hstatus_vtvm = 1'h0; // @[DCache.scala:101:7] wire io_ptw_hstatus_hu = 1'h0; // @[DCache.scala:101:7] wire io_ptw_hstatus_spvp = 1'h0; // @[DCache.scala:101:7] wire io_ptw_hstatus_spv = 1'h0; // @[DCache.scala:101:7] wire io_ptw_hstatus_gva = 1'h0; // @[DCache.scala:101:7] wire io_ptw_hstatus_vsbe = 1'h0; // @[DCache.scala:101:7] wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_2_stall = 1'h0; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_2_set = 1'h0; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_3_stall = 1'h0; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_3_set = 1'h0; // @[DCache.scala:101:7] wire io_tlb_port_req_valid = 1'h0; // @[DCache.scala:101:7] wire io_tlb_port_req_bits_passthrough = 1'h0; // @[DCache.scala:101:7] wire io_tlb_port_req_bits_v = 1'h0; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_miss = 1'h0; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_gpa_is_pte = 1'h0; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_gf_ld = 1'h0; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_gf_st = 1'h0; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_gf_inst = 1'h0; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_ma_inst = 1'h0; // @[DCache.scala:101:7] wire io_tlb_port_s2_kill = 1'h0; // @[DCache.scala:101:7] wire nodeOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_d_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire mmioAddressPrefixSinkNodeOptIn = 1'h0; // @[MixedNode.scala:551:17] wire pma_checker_io_req_valid = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_resp_miss = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_resp_gpa_is_pte = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_resp_gf_ld = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_resp_gf_st = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_resp_gf_inst = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_resp_ma_inst = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_sfence_valid = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_sfence_bits_rs1 = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_sfence_bits_rs2 = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_sfence_bits_asid = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_sfence_bits_hv = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_sfence_bits_hg = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_req_ready = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_req_valid = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_req_bits_bits_need_gpa = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_req_bits_bits_vstage1 = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_req_bits_bits_stage2 = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_valid = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_ae_ptw = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_ae_final = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_pf = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_gf = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_hr = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_hw = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_hx = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_pte_d = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_pte_a = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_pte_g = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_pte_u = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_pte_x = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_pte_w = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_pte_r = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_pte_v = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_homogeneous = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_gpa_valid = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_gpa_is_pte = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_debug = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_cease = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_wfi = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_dv = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_v = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_sd = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_mpv = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_gva = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_mbe = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_sbe = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_sd_rv32 = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_tsr = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_tw = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_tvm = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_mxr = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_sum = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_mprv = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_spp = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_mpie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_ube = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_spie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_upie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_mie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_hie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_sie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_uie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_hstatus_vtsr = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_hstatus_vtw = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_hstatus_vtvm = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_hstatus_hu = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_hstatus_spvp = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_hstatus_spv = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_hstatus_gva = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_hstatus_vsbe = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_debug = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_cease = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_wfi = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_dv = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_v = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_sd = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_mpv = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_gva = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_mbe = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_sbe = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_sd_rv32 = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_tsr = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_tw = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_tvm = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_mxr = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_sum = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_mprv = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_spp = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_mpie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_ube = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_spie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_upie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_mie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_hie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_sie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_uie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_0_cfg_l = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_0_cfg_x = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_0_cfg_w = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_0_cfg_r = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_1_cfg_l = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_1_cfg_x = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_1_cfg_w = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_1_cfg_r = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_2_cfg_l = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_2_cfg_x = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_2_cfg_w = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_2_cfg_r = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_3_cfg_l = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_3_cfg_x = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_3_cfg_w = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_3_cfg_r = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_4_cfg_l = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_4_cfg_x = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_4_cfg_w = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_4_cfg_r = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_5_cfg_l = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_5_cfg_x = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_5_cfg_w = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_5_cfg_r = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_6_cfg_l = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_6_cfg_x = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_6_cfg_w = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_6_cfg_r = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_7_cfg_l = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_7_cfg_x = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_7_cfg_w = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_7_cfg_r = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_0_ren = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_0_wen = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_0_set = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_1_ren = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_1_wen = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_1_set = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_2_ren = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_2_wen = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_2_stall = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_2_set = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_3_ren = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_3_wen = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_3_stall = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_3_set = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_kill = 1'h0; // @[DCache.scala:120:32] wire pma_checker_priv_v = 1'h0; // @[TLB.scala:369:34] wire pma_checker__stage1_en_T = 1'h0; // @[TLB.scala:374:41] wire pma_checker_stage1_en = 1'h0; // @[TLB.scala:374:29] wire pma_checker__vstage1_en_T = 1'h0; // @[TLB.scala:376:38] wire pma_checker__vstage1_en_T_1 = 1'h0; // @[TLB.scala:376:68] wire pma_checker_vstage1_en = 1'h0; // @[TLB.scala:376:48] wire pma_checker__stage2_en_T = 1'h0; // @[TLB.scala:378:38] wire pma_checker__stage2_en_T_1 = 1'h0; // @[TLB.scala:378:68] wire pma_checker_stage2_en = 1'h0; // @[TLB.scala:378:48] wire pma_checker__vm_enabled_T = 1'h0; // @[TLB.scala:399:31] wire pma_checker__vm_enabled_T_1 = 1'h0; // @[TLB.scala:399:45] wire pma_checker__vm_enabled_T_2 = 1'h0; // @[TLB.scala:399:64] wire pma_checker_vm_enabled = 1'h0; // @[TLB.scala:399:61] wire pma_checker__vsatp_mode_mismatch_T = 1'h0; // @[TLB.scala:403:52] wire pma_checker__vsatp_mode_mismatch_T_1 = 1'h0; // @[TLB.scala:403:37] wire pma_checker__vsatp_mode_mismatch_T_2 = 1'h0; // @[TLB.scala:403:81] wire pma_checker_vsatp_mode_mismatch = 1'h0; // @[TLB.scala:403:78] wire pma_checker_do_refill = 1'h0; // @[TLB.scala:408:29] wire pma_checker__invalidate_refill_T = 1'h0; // @[package.scala:16:47] wire pma_checker__invalidate_refill_T_1 = 1'h0; // @[package.scala:16:47] wire pma_checker__invalidate_refill_T_2 = 1'h0; // @[package.scala:81:59] wire pma_checker_invalidate_refill = 1'h0; // @[TLB.scala:410:88] wire pma_checker__mpu_ppn_T = 1'h0; // @[TLB.scala:413:32] wire pma_checker__mpu_priv_T_1 = 1'h0; // @[TLB.scala:415:38] wire pma_checker_cacheable = 1'h0; // @[TLB.scala:425:41] wire pma_checker__sector_hits_T = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_8 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_16 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_24 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_32 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_40 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_48 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_56 = 1'h0; // @[package.scala:81:59] wire pma_checker_superpage_hits_0 = 1'h0; // @[TLB.scala:188:18] wire pma_checker_superpage_hits_1 = 1'h0; // @[TLB.scala:188:18] wire pma_checker_superpage_hits_2 = 1'h0; // @[TLB.scala:188:18] wire pma_checker_superpage_hits_3 = 1'h0; // @[TLB.scala:188:18] wire pma_checker__hitsVec_T_5 = 1'h0; // @[TLB.scala:188:18] wire pma_checker_hitsVec_0 = 1'h0; // @[TLB.scala:440:44] wire pma_checker__hitsVec_T_11 = 1'h0; // @[TLB.scala:188:18] wire pma_checker_hitsVec_1 = 1'h0; // @[TLB.scala:440:44] wire pma_checker__hitsVec_T_17 = 1'h0; // @[TLB.scala:188:18] wire pma_checker_hitsVec_2 = 1'h0; // @[TLB.scala:440:44] wire pma_checker__hitsVec_T_23 = 1'h0; // @[TLB.scala:188:18] wire pma_checker_hitsVec_3 = 1'h0; // @[TLB.scala:440:44] wire pma_checker__hitsVec_T_29 = 1'h0; // @[TLB.scala:188:18] wire pma_checker_hitsVec_4 = 1'h0; // @[TLB.scala:440:44] wire pma_checker__hitsVec_T_35 = 1'h0; // @[TLB.scala:188:18] wire pma_checker_hitsVec_5 = 1'h0; // @[TLB.scala:440:44] wire pma_checker__hitsVec_T_41 = 1'h0; // @[TLB.scala:188:18] wire pma_checker_hitsVec_6 = 1'h0; // @[TLB.scala:440:44] wire pma_checker__hitsVec_T_47 = 1'h0; // @[TLB.scala:188:18] wire pma_checker_hitsVec_7 = 1'h0; // @[TLB.scala:440:44] wire pma_checker__hitsVec_T_53 = 1'h0; // @[TLB.scala:188:18] wire pma_checker_hitsVec_8 = 1'h0; // @[TLB.scala:440:44] wire pma_checker__hitsVec_T_59 = 1'h0; // @[TLB.scala:188:18] wire pma_checker_hitsVec_9 = 1'h0; // @[TLB.scala:440:44] wire pma_checker__hitsVec_T_65 = 1'h0; // @[TLB.scala:188:18] wire pma_checker_hitsVec_10 = 1'h0; // @[TLB.scala:440:44] wire pma_checker__hitsVec_T_71 = 1'h0; // @[TLB.scala:188:18] wire pma_checker_hitsVec_11 = 1'h0; // @[TLB.scala:440:44] wire pma_checker_hitsVec_12 = 1'h0; // @[TLB.scala:440:44] wire pma_checker_refill_v = 1'h0; // @[TLB.scala:448:33] wire pma_checker_newEntry_u = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_g = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_ae_ptw = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_ae_final = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_ae_stage2 = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_pf = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_gf = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_sw = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_sx = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_sr = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_hw = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_hx = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_hr = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_c = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_fragmented_superpage = 1'h0; // @[TLB.scala:449:24] wire pma_checker__newEntry_g_T = 1'h0; // @[TLB.scala:453:25] wire pma_checker__newEntry_ae_stage2_T = 1'h0; // @[TLB.scala:456:53] wire pma_checker__newEntry_ae_stage2_T_1 = 1'h0; // @[TLB.scala:456:84] wire pma_checker__newEntry_sr_T_1 = 1'h0; // @[PTW.scala:141:44] wire pma_checker__newEntry_sr_T_2 = 1'h0; // @[PTW.scala:141:38] wire pma_checker__newEntry_sr_T_3 = 1'h0; // @[PTW.scala:141:32] wire pma_checker__newEntry_sr_T_4 = 1'h0; // @[PTW.scala:141:52] wire pma_checker__newEntry_sr_T_5 = 1'h0; // @[PTW.scala:149:35] wire pma_checker__newEntry_sw_T_1 = 1'h0; // @[PTW.scala:141:44] wire pma_checker__newEntry_sw_T_2 = 1'h0; // @[PTW.scala:141:38] wire pma_checker__newEntry_sw_T_3 = 1'h0; // @[PTW.scala:141:32] wire pma_checker__newEntry_sw_T_4 = 1'h0; // @[PTW.scala:141:52] wire pma_checker__newEntry_sw_T_5 = 1'h0; // @[PTW.scala:151:35] wire pma_checker__newEntry_sw_T_6 = 1'h0; // @[PTW.scala:151:40] wire pma_checker__newEntry_sx_T_1 = 1'h0; // @[PTW.scala:141:44] wire pma_checker__newEntry_sx_T_2 = 1'h0; // @[PTW.scala:141:38] wire pma_checker__newEntry_sx_T_3 = 1'h0; // @[PTW.scala:141:32] wire pma_checker__newEntry_sx_T_4 = 1'h0; // @[PTW.scala:141:52] wire pma_checker__newEntry_sx_T_5 = 1'h0; // @[PTW.scala:153:35] wire pma_checker__waddr_T = 1'h0; // @[TLB.scala:477:45] wire pma_checker__superpage_entries_0_level_T = 1'h0; // @[package.scala:163:13] wire pma_checker__superpage_entries_1_level_T = 1'h0; // @[package.scala:163:13] wire pma_checker__superpage_entries_2_level_T = 1'h0; // @[package.scala:163:13] wire pma_checker__superpage_entries_3_level_T = 1'h0; // @[package.scala:163:13] wire pma_checker_sum = 1'h0; // @[TLB.scala:510:16] wire pma_checker__mxr_T = 1'h0; // @[TLB.scala:518:36] wire pma_checker_mxr = 1'h0; // @[TLB.scala:518:31] wire pma_checker__prefetchable_array_T = 1'h0; // @[TLB.scala:547:43] wire pma_checker_cmd_readx = 1'h0; // @[TLB.scala:575:37] wire pma_checker__gf_ld_array_T = 1'h0; // @[TLB.scala:600:32] wire pma_checker__gf_st_array_T = 1'h0; // @[TLB.scala:601:32] wire pma_checker__gpa_hits_hit_mask_T_1 = 1'h0; // @[TLB.scala:606:60] wire pma_checker_tlb_hit_if_not_gpa_miss = 1'h0; // @[TLB.scala:610:43] wire pma_checker_tlb_hit = 1'h0; // @[TLB.scala:611:40] wire pma_checker__tlb_miss_T_1 = 1'h0; // @[TLB.scala:613:29] wire pma_checker__tlb_miss_T_3 = 1'h0; // @[TLB.scala:613:53] wire pma_checker_tlb_miss = 1'h0; // @[TLB.scala:613:64] wire pma_checker_state_vec_0_left_subtree_state_1 = 1'h0; // @[package.scala:163:13] wire pma_checker_state_vec_0_right_subtree_state_1 = 1'h0; // @[Replacement.scala:198:38] wire pma_checker_state_vec_0_left_subtree_state_2 = 1'h0; // @[package.scala:163:13] wire pma_checker_state_vec_0_right_subtree_state_2 = 1'h0; // @[Replacement.scala:198:38] wire pma_checker_state_reg_left_subtree_state = 1'h0; // @[package.scala:163:13] wire pma_checker_state_reg_right_subtree_state = 1'h0; // @[Replacement.scala:198:38] wire pma_checker__multipleHits_T_2 = 1'h0; // @[Misc.scala:181:37] wire pma_checker_multipleHits_leftOne = 1'h0; // @[Misc.scala:178:18] wire pma_checker__multipleHits_T_4 = 1'h0; // @[Misc.scala:181:37] wire pma_checker_multipleHits_leftOne_1 = 1'h0; // @[Misc.scala:178:18] wire pma_checker__multipleHits_T_5 = 1'h0; // @[Misc.scala:182:39] wire pma_checker_multipleHits_rightOne = 1'h0; // @[Misc.scala:178:18] wire pma_checker_multipleHits_rightOne_1 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_6 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_7 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits_rightTwo = 1'h0; // @[Misc.scala:183:49] wire pma_checker_multipleHits_leftOne_2 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_8 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_9 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits_leftTwo = 1'h0; // @[Misc.scala:183:49] wire pma_checker__multipleHits_T_11 = 1'h0; // @[Misc.scala:181:37] wire pma_checker_multipleHits_leftOne_3 = 1'h0; // @[Misc.scala:178:18] wire pma_checker__multipleHits_T_13 = 1'h0; // @[Misc.scala:181:37] wire pma_checker_multipleHits_leftOne_4 = 1'h0; // @[Misc.scala:178:18] wire pma_checker__multipleHits_T_14 = 1'h0; // @[Misc.scala:182:39] wire pma_checker_multipleHits_rightOne_2 = 1'h0; // @[Misc.scala:178:18] wire pma_checker_multipleHits_rightOne_3 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_15 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_16 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits_rightTwo_1 = 1'h0; // @[Misc.scala:183:49] wire pma_checker_multipleHits_rightOne_4 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_17 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_18 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits_rightTwo_2 = 1'h0; // @[Misc.scala:183:49] wire pma_checker_multipleHits_leftOne_5 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_19 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_20 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits_leftTwo_1 = 1'h0; // @[Misc.scala:183:49] wire pma_checker__multipleHits_T_23 = 1'h0; // @[Misc.scala:181:37] wire pma_checker_multipleHits_leftOne_6 = 1'h0; // @[Misc.scala:178:18] wire pma_checker__multipleHits_T_25 = 1'h0; // @[Misc.scala:181:37] wire pma_checker_multipleHits_leftOne_7 = 1'h0; // @[Misc.scala:178:18] wire pma_checker__multipleHits_T_26 = 1'h0; // @[Misc.scala:182:39] wire pma_checker_multipleHits_rightOne_5 = 1'h0; // @[Misc.scala:178:18] wire pma_checker_multipleHits_rightOne_6 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_27 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_28 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits_rightTwo_3 = 1'h0; // @[Misc.scala:183:49] wire pma_checker_multipleHits_leftOne_8 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_29 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_30 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits_leftTwo_2 = 1'h0; // @[Misc.scala:183:49] wire pma_checker__multipleHits_T_33 = 1'h0; // @[Misc.scala:181:37] wire pma_checker_multipleHits_leftOne_9 = 1'h0; // @[Misc.scala:178:18] wire pma_checker__multipleHits_T_34 = 1'h0; // @[Misc.scala:182:39] wire pma_checker_multipleHits_rightOne_7 = 1'h0; // @[Misc.scala:178:18] wire pma_checker_multipleHits_leftOne_10 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_35 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_36 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits_leftTwo_3 = 1'h0; // @[Misc.scala:183:49] wire pma_checker__multipleHits_T_38 = 1'h0; // @[Misc.scala:181:37] wire pma_checker_multipleHits_leftOne_11 = 1'h0; // @[Misc.scala:178:18] wire pma_checker__multipleHits_T_39 = 1'h0; // @[Misc.scala:182:39] wire pma_checker_multipleHits_rightOne_8 = 1'h0; // @[Misc.scala:178:18] wire pma_checker_multipleHits_rightOne_9 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_40 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_41 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits_rightTwo_4 = 1'h0; // @[Misc.scala:183:49] wire pma_checker_multipleHits_rightOne_10 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_42 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_43 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits_rightTwo_5 = 1'h0; // @[Misc.scala:183:49] wire pma_checker_multipleHits_rightOne_11 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_44 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_45 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits_rightTwo_6 = 1'h0; // @[Misc.scala:183:49] wire pma_checker__multipleHits_T_46 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_47 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_48 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits = 1'h0; // @[Misc.scala:183:49] wire pma_checker__io_resp_pf_ld_T = 1'h0; // @[TLB.scala:633:28] wire pma_checker__io_resp_pf_st_T = 1'h0; // @[TLB.scala:634:28] wire pma_checker__io_resp_gf_ld_T = 1'h0; // @[TLB.scala:637:29] wire pma_checker__io_resp_gf_ld_T_2 = 1'h0; // @[TLB.scala:637:66] wire pma_checker__io_resp_gf_ld_T_3 = 1'h0; // @[TLB.scala:637:42] wire pma_checker__io_resp_gf_st_T = 1'h0; // @[TLB.scala:638:29] wire pma_checker__io_resp_gf_st_T_2 = 1'h0; // @[TLB.scala:638:73] wire pma_checker__io_resp_gf_st_T_3 = 1'h0; // @[TLB.scala:638:49] wire pma_checker__io_resp_gf_inst_T_1 = 1'h0; // @[TLB.scala:639:56] wire pma_checker__io_resp_gf_inst_T_2 = 1'h0; // @[TLB.scala:639:30] wire pma_checker__io_resp_miss_T = 1'h0; // @[TLB.scala:651:29] wire pma_checker__io_resp_miss_T_1 = 1'h0; // @[TLB.scala:651:52] wire pma_checker__io_resp_miss_T_2 = 1'h0; // @[TLB.scala:651:64] wire pma_checker__io_resp_gpa_is_pte_T = 1'h0; // @[TLB.scala:655:36] wire pma_checker__io_ptw_req_valid_T = 1'h0; // @[TLB.scala:662:29] wire metaArb_io_in_0_valid = 1'h0; // @[DCache.scala:135:28] wire metaArb_io_in_1_valid = 1'h0; // @[DCache.scala:135:28] wire metaArb_io_in_1_bits_way_en = 1'h0; // @[DCache.scala:135:28] wire metaArb_io_in_4_valid = 1'h0; // @[DCache.scala:135:28] wire metaArb_io_in_5_valid = 1'h0; // @[DCache.scala:135:28] wire metaArb_io_in_5_bits_write = 1'h0; // @[DCache.scala:135:28] wire metaArb_io_in_6_valid = 1'h0; // @[DCache.scala:135:28] wire metaArb_io_in_6_bits_write = 1'h0; // @[DCache.scala:135:28] wire metaArb_io_in_7_bits_write = 1'h0; // @[DCache.scala:135:28] wire metaArb__grant_T = 1'h0; // @[Arbiter.scala:45:68] wire dataArb_io_in_2_valid = 1'h0; // @[DCache.scala:152:28] wire dataArb_io_in_2_bits_write = 1'h0; // @[DCache.scala:152:28] wire dataArb_io_in_3_bits_write = 1'h0; // @[DCache.scala:152:28] wire tl_out_a_bits_source = 1'h0; // @[DCache.scala:159:22] wire tl_out_a_bits_corrupt = 1'h0; // @[DCache.scala:159:22] wire nodeOut_a_deq_bits_source = 1'h0; // @[Decoupled.scala:356:21] wire nodeOut_a_deq_bits_corrupt = 1'h0; // @[Decoupled.scala:356:21] wire tl_out_c_ready = 1'h0; // @[Bundles.scala:265:61] wire tl_out_c_bits_source = 1'h0; // @[Bundles.scala:265:61] wire tl_out_c_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _s1_probe_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _s1_probe_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _s1_probe_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74] wire _s1_probe_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _s1_probe_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _s1_probe_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _s1_probe_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:264:61] wire _s1_probe_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _s1_probe_T = 1'h0; // @[Decoupled.scala:51:35] wire _probe_bits_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _probe_bits_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _probe_bits_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74] wire _probe_bits_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _probe_bits_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _probe_bits_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _probe_bits_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:264:61] wire _probe_bits_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _probe_bits_WIRE_2_ready = 1'h0; // @[Bundles.scala:264:74] wire _probe_bits_WIRE_2_valid = 1'h0; // @[Bundles.scala:264:74] wire _probe_bits_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:264:74] wire _probe_bits_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _probe_bits_WIRE_3_ready = 1'h0; // @[Bundles.scala:264:61] wire _probe_bits_WIRE_3_valid = 1'h0; // @[Bundles.scala:264:61] wire _probe_bits_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:264:61] wire _probe_bits_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _probe_bits_T = 1'h0; // @[Decoupled.scala:51:35] wire _s1_tlb_req_valid_T = 1'h0; // @[Decoupled.scala:51:35] wire s0_req_no_alloc = 1'h0; // @[DCache.scala:192:24] wire s1_waw_hazard = 1'h0; // @[DCache.scala:216:27] wire _inWriteback_T = 1'h0; // @[package.scala:16:47] wire _inWriteback_T_1 = 1'h0; // @[package.scala:16:47] wire inWriteback = 1'h0; // @[package.scala:81:59] wire _uncachedInFlight_WIRE_0 = 1'h0; // @[DCache.scala:236:41] wire _dataArb_io_in_3_valid_res_T_4 = 1'h0; // @[DCache.scala:1185:58] wire _dataArb_io_in_3_valid_T_49 = 1'h0; // @[DCache.scala:1191:57] wire _s1_did_read_T_49 = 1'h0; // @[DCache.scala:1191:57] wire _tlb_io_kill_T = 1'h0; // @[DCache.scala:272:53] wire _tlb_io_kill_T_1 = 1'h0; // @[DCache.scala:272:33] wire s1_victim_way = 1'h0; // @[DCache.scala:299:27] wire _releaseInFlight_T = 1'h0; // @[DCache.scala:334:34] wire _releaseInFlight_T_1 = 1'h0; // @[DCache.scala:334:63] wire releaseInFlight = 1'h0; // @[DCache.scala:334:46] wire _s2_pma_T_miss = 1'h0; // @[DCache.scala:349:18] wire _s2_pma_T_gpa_is_pte = 1'h0; // @[DCache.scala:349:18] wire _s2_pma_T_gf_ld = 1'h0; // @[DCache.scala:349:18] wire _s2_pma_T_gf_st = 1'h0; // @[DCache.scala:349:18] wire _s2_pma_T_gf_inst = 1'h0; // @[DCache.scala:349:18] wire _s2_pma_T_ma_inst = 1'h0; // @[DCache.scala:349:18] wire s2_meta_error_uncorrectable = 1'h0; // @[DCache.scala:360:66] wire _s2_meta_error_T = 1'h0; // @[DCache.scala:362:53] wire s2_meta_error = 1'h0; // @[DCache.scala:362:83] wire s2_store_merge = 1'h0; // @[DCache.scala:388:28] wire _r_T_26 = 1'h0; // @[Misc.scala:35:9] wire _r_T_29 = 1'h0; // @[Misc.scala:35:9] wire _r_T_32 = 1'h0; // @[Misc.scala:35:9] wire _r_T_35 = 1'h0; // @[Misc.scala:35:9] wire _r_T_38 = 1'h0; // @[Misc.scala:35:9] wire _s2_data_error_T = 1'h0; // @[ECC.scala:15:27] wire _s2_data_error_T_1 = 1'h0; // @[ECC.scala:15:27] wire _s2_data_error_T_2 = 1'h0; // @[ECC.scala:15:27] wire _s2_data_error_T_3 = 1'h0; // @[ECC.scala:15:27] wire _s2_data_error_T_4 = 1'h0; // @[ECC.scala:15:27] wire _s2_data_error_T_5 = 1'h0; // @[ECC.scala:15:27] wire _s2_data_error_T_6 = 1'h0; // @[ECC.scala:15:27] wire _s2_data_error_T_7 = 1'h0; // @[ECC.scala:15:27] wire _s2_data_error_T_8 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_T_9 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_T_10 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_T_11 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_T_12 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_T_13 = 1'h0; // @[package.scala:81:59] wire s2_data_error = 1'h0; // @[package.scala:81:59] wire _s2_data_error_uncorrectable_T = 1'h0; // @[package.scala:81:59] wire _s2_data_error_uncorrectable_T_1 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_uncorrectable_T_2 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_uncorrectable_T_3 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_uncorrectable_T_4 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_uncorrectable_T_5 = 1'h0; // @[package.scala:81:59] wire s2_data_error_uncorrectable = 1'h0; // @[package.scala:81:59] wire s2_valid_data_error = 1'h0; // @[DCache.scala:421:63] wire s2_want_victimize = 1'h0; // @[DCache.scala:427:52] wire s2_cannot_victimize = 1'h0; // @[DCache.scala:428:45] wire s2_victimize = 1'h0; // @[DCache.scala:429:40] wire _r_T_73 = 1'h0; // @[Misc.scala:38:9] wire _r_T_77 = 1'h0; // @[Misc.scala:38:9] wire _r_T_81 = 1'h0; // @[Misc.scala:38:9] wire _r_T_119 = 1'h0; // @[Metadata.scala:140:24] wire _r_T_121 = 1'h0; // @[Metadata.scala:140:24] wire _r_T_137 = 1'h0; // @[Misc.scala:38:9] wire _r_T_141 = 1'h0; // @[Misc.scala:38:9] wire _r_T_145 = 1'h0; // @[Misc.scala:38:9] wire _s2_dont_nack_misc_T_2 = 1'h0; // @[DCache.scala:442:23] wire _s2_dont_nack_misc_T_3 = 1'h0; // @[DCache.scala:442:43] wire _s2_dont_nack_misc_T_5 = 1'h0; // @[DCache.scala:442:54] wire _s2_dont_nack_misc_T_6 = 1'h0; // @[DCache.scala:443:23] wire _s2_dont_nack_misc_T_8 = 1'h0; // @[DCache.scala:443:44] wire _s2_dont_nack_misc_T_9 = 1'h0; // @[DCache.scala:442:67] wire _s2_first_meta_corrected_T = 1'h0; // @[Mux.scala:52:83] wire _metaArb_io_in_1_valid_T_2 = 1'h0; // @[DCache.scala:450:43] wire _metaArb_io_in_1_bits_way_en_T = 1'h0; // @[OneHot.scala:85:71] wire _metaArb_io_in_1_bits_way_en_T_1 = 1'h0; // @[Mux.scala:50:70] wire _metaArb_io_in_1_bits_way_en_T_2 = 1'h0; // @[DCache.scala:452:69] wire _metaArb_io_in_1_bits_way_en_T_3 = 1'h0; // @[DCache.scala:452:64] wire s2_lr = 1'h0; // @[DCache.scala:470:56] wire s2_sc = 1'h0; // @[DCache.scala:471:56] wire s2_sc_fail = 1'h0; // @[DCache.scala:477:26] wire _s2_correct_T_1 = 1'h0; // @[DCache.scala:487:34] wire _s2_correct_T_4 = 1'h0; // @[DCache.scala:487:55] wire s2_correct = 1'h0; // @[DCache.scala:487:97] wire _s2_valid_correct_T = 1'h0; // @[DCache.scala:489:60] wire s2_valid_correct = 1'h0; // @[DCache.scala:489:74] wire _pstore1_rmw_T_49 = 1'h0; // @[DCache.scala:1191:57] wire pstore1_merge_likely = 1'h0; // @[DCache.scala:499:68] wire pstore1_merge = 1'h0; // @[DCache.scala:500:38] wire _pstore_drain_opportunistic_res_T_4 = 1'h0; // @[DCache.scala:1185:58] wire _pstore_drain_opportunistic_T_49 = 1'h0; // @[DCache.scala:1191:57] wire _pstore_drain_opportunistic_T_60 = 1'h0; // @[DCache.scala:502:106] wire pstore_drain_s2_kill = 1'h0; // @[DCache.scala:515:25] wire _pstore2_storegen_data_T_2 = 1'h0; // @[DCache.scala:528:95] wire _pstore2_storegen_data_T_6 = 1'h0; // @[DCache.scala:528:95] wire _pstore2_storegen_data_T_10 = 1'h0; // @[DCache.scala:528:95] wire _pstore2_storegen_data_T_14 = 1'h0; // @[DCache.scala:528:95] wire _pstore2_storegen_data_T_18 = 1'h0; // @[DCache.scala:528:95] wire _pstore2_storegen_data_T_22 = 1'h0; // @[DCache.scala:528:95] wire _pstore2_storegen_data_T_26 = 1'h0; // @[DCache.scala:528:95] wire _pstore2_storegen_data_T_30 = 1'h0; // @[DCache.scala:528:95] wire dataArb_io_in_0_valid_s2_kill = 1'h0; // @[DCache.scala:515:25] wire _dataArb_io_in_0_bits_wordMask_T_1 = 1'h0; // @[DCache.scala:555:20] wire _io_cpu_s2_nack_cause_raw_T_2 = 1'h0; // @[DCache.scala:574:57] wire get_source = 1'h0; // @[Edges.scala:460:17] wire get_corrupt = 1'h0; // @[Edges.scala:460:17] wire _put_legal_T_44 = 1'h0; // @[Parameters.scala:684:29] wire _put_legal_T_50 = 1'h0; // @[Parameters.scala:684:54] wire put_source = 1'h0; // @[Edges.scala:480:17] wire put_corrupt = 1'h0; // @[Edges.scala:480:17] wire _putpartial_legal_T_44 = 1'h0; // @[Parameters.scala:684:29] wire _putpartial_legal_T_50 = 1'h0; // @[Parameters.scala:684:54] wire putpartial_source = 1'h0; // @[Edges.scala:500:17] wire putpartial_corrupt = 1'h0; // @[Edges.scala:500:17] wire _atomics_WIRE_source = 1'h0; // @[DCache.scala:587:51] wire _atomics_WIRE_corrupt = 1'h0; // @[DCache.scala:587:51] wire _atomics_WIRE_1_source = 1'h0; // @[DCache.scala:587:38] wire _atomics_WIRE_1_corrupt = 1'h0; // @[DCache.scala:587:38] wire _atomics_legal_T_22 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_28 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_source = 1'h0; // @[Edges.scala:534:17] wire atomics_a_corrupt = 1'h0; // @[Edges.scala:534:17] wire _atomics_legal_T_52 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_58 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_1_source = 1'h0; // @[Edges.scala:534:17] wire atomics_a_1_corrupt = 1'h0; // @[Edges.scala:534:17] wire _atomics_legal_T_82 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_88 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_2_source = 1'h0; // @[Edges.scala:534:17] wire atomics_a_2_corrupt = 1'h0; // @[Edges.scala:534:17] wire _atomics_legal_T_112 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_118 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_3_source = 1'h0; // @[Edges.scala:534:17] wire atomics_a_3_corrupt = 1'h0; // @[Edges.scala:534:17] wire _atomics_legal_T_142 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_148 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_4_source = 1'h0; // @[Edges.scala:517:17] wire atomics_a_4_corrupt = 1'h0; // @[Edges.scala:517:17] wire _atomics_legal_T_172 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_178 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_5_source = 1'h0; // @[Edges.scala:517:17] wire atomics_a_5_corrupt = 1'h0; // @[Edges.scala:517:17] wire _atomics_legal_T_202 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_208 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_6_source = 1'h0; // @[Edges.scala:517:17] wire atomics_a_6_corrupt = 1'h0; // @[Edges.scala:517:17] wire _atomics_legal_T_232 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_238 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_7_source = 1'h0; // @[Edges.scala:517:17] wire atomics_a_7_corrupt = 1'h0; // @[Edges.scala:517:17] wire _atomics_legal_T_262 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_268 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_8_source = 1'h0; // @[Edges.scala:517:17] wire atomics_a_8_corrupt = 1'h0; // @[Edges.scala:517:17] wire _atomics_T_1_source = 1'h0; // @[DCache.scala:587:81] wire _atomics_T_1_corrupt = 1'h0; // @[DCache.scala:587:81] wire _atomics_T_3_source = 1'h0; // @[DCache.scala:587:81] wire _atomics_T_3_corrupt = 1'h0; // @[DCache.scala:587:81] wire _atomics_T_5_source = 1'h0; // @[DCache.scala:587:81] wire _atomics_T_5_corrupt = 1'h0; // @[DCache.scala:587:81] wire _atomics_T_7_source = 1'h0; // @[DCache.scala:587:81] wire _atomics_T_7_corrupt = 1'h0; // @[DCache.scala:587:81] wire _atomics_T_9_source = 1'h0; // @[DCache.scala:587:81] wire _atomics_T_9_corrupt = 1'h0; // @[DCache.scala:587:81] wire _atomics_T_11_source = 1'h0; // @[DCache.scala:587:81] wire _atomics_T_11_corrupt = 1'h0; // @[DCache.scala:587:81] wire _atomics_T_13_source = 1'h0; // @[DCache.scala:587:81] wire _atomics_T_13_corrupt = 1'h0; // @[DCache.scala:587:81] wire _atomics_T_15_source = 1'h0; // @[DCache.scala:587:81] wire _atomics_T_15_corrupt = 1'h0; // @[DCache.scala:587:81] wire atomics_source = 1'h0; // @[DCache.scala:587:81] wire atomics_corrupt = 1'h0; // @[DCache.scala:587:81] wire _tl_out_a_valid_T_4 = 1'h0; // @[DCache.scala:606:27] wire _tl_out_a_valid_T_8 = 1'h0; // @[DCache.scala:607:44] wire _tl_out_a_valid_T_9 = 1'h0; // @[DCache.scala:607:65] wire _tl_out_a_bits_WIRE_source = 1'h0; // @[DCache.scala:1209:67] wire _tl_out_a_bits_WIRE_corrupt = 1'h0; // @[DCache.scala:1209:67] wire _tl_out_a_bits_WIRE_1_source = 1'h0; // @[DCache.scala:1209:54] wire _tl_out_a_bits_WIRE_1_corrupt = 1'h0; // @[DCache.scala:1209:54] wire _tl_out_a_bits_T_4_source = 1'h0; // @[DCache.scala:611:8] wire _tl_out_a_bits_T_4_corrupt = 1'h0; // @[DCache.scala:611:8] wire _tl_out_a_bits_T_5_source = 1'h0; // @[DCache.scala:610:8] wire _tl_out_a_bits_T_5_corrupt = 1'h0; // @[DCache.scala:610:8] wire _tl_out_a_bits_T_6_source = 1'h0; // @[DCache.scala:609:8] wire _tl_out_a_bits_T_6_corrupt = 1'h0; // @[DCache.scala:609:8] wire _tl_out_a_bits_T_7_source = 1'h0; // @[DCache.scala:608:23] wire _tl_out_a_bits_T_7_corrupt = 1'h0; // @[DCache.scala:608:23] wire _tl_d_data_encoded_T_12 = 1'h0; // @[DCache.scala:663:129] wire _tl_d_data_encoded_T_13 = 1'h0; // @[DCache.scala:663:126] wire _grantIsCached_T = 1'h0; // @[package.scala:16:47] wire _grantIsCached_T_1 = 1'h0; // @[package.scala:16:47] wire grantIsVoluntary = 1'h0; // @[DCache.scala:665:32] wire grantIsRefill = 1'h0; // @[DCache.scala:666:29] wire _canAcceptCachedGrant_T = 1'h0; // @[package.scala:16:47] wire _canAcceptCachedGrant_T_1 = 1'h0; // @[package.scala:16:47] wire _canAcceptCachedGrant_T_2 = 1'h0; // @[package.scala:16:47] wire _canAcceptCachedGrant_T_3 = 1'h0; // @[package.scala:81:59] wire _canAcceptCachedGrant_T_4 = 1'h0; // @[package.scala:81:59] wire _nodeOut_d_ready_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _nodeOut_d_ready_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _nodeOut_d_ready_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _nodeOut_d_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _nodeOut_d_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _nodeOut_d_ready_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _block_probe_for_pending_release_ack_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _block_probe_for_pending_release_ack_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _block_probe_for_pending_release_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74] wire _block_probe_for_pending_release_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _block_probe_for_pending_release_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _block_probe_for_pending_release_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _block_probe_for_pending_release_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:264:61] wire _block_probe_for_pending_release_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire block_probe_for_pending_release_ack = 1'h0; // @[DCache.scala:767:62] wire _block_probe_for_ordering_T = 1'h0; // @[DCache.scala:768:50] wire _metaArb_io_in_6_valid_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _metaArb_io_in_6_valid_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _metaArb_io_in_6_valid_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74] wire _metaArb_io_in_6_valid_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _metaArb_io_in_6_valid_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _metaArb_io_in_6_valid_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _metaArb_io_in_6_valid_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:264:61] wire _metaArb_io_in_6_valid_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _metaArb_io_in_6_valid_T_2 = 1'h0; // @[DCache.scala:769:44] wire _metaArb_io_in_6_bits_idx_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _metaArb_io_in_6_bits_idx_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _metaArb_io_in_6_bits_idx_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74] wire _metaArb_io_in_6_bits_idx_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _metaArb_io_in_6_bits_idx_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _metaArb_io_in_6_bits_idx_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _metaArb_io_in_6_bits_idx_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:264:61] wire _metaArb_io_in_6_bits_idx_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _metaArb_io_in_6_bits_addr_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _metaArb_io_in_6_bits_addr_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _metaArb_io_in_6_bits_addr_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74] wire _metaArb_io_in_6_bits_addr_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _metaArb_io_in_6_bits_addr_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _metaArb_io_in_6_bits_addr_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _metaArb_io_in_6_bits_addr_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:264:61] wire _metaArb_io_in_6_bits_addr_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire r_beats1_opdata_1 = 1'h0; // @[Edges.scala:102:36] wire _r_last_T_2 = 1'h0; // @[Edges.scala:232:25] wire releaseDone = 1'h0; // @[Edges.scala:233:22] wire _s1_release_data_valid_T = 1'h0; // @[Decoupled.scala:51:35] wire _s2_release_data_valid_T_1 = 1'h0; // @[DCache.scala:802:61] wire _releaseRejected_T = 1'h0; // @[Decoupled.scala:51:35] wire nackResponseMessage_source = 1'h0; // @[Edges.scala:416:17] wire nackResponseMessage_corrupt = 1'h0; // @[Edges.scala:416:17] wire cleanReleaseMessage_source = 1'h0; // @[Edges.scala:416:17] wire cleanReleaseMessage_corrupt = 1'h0; // @[Edges.scala:416:17] wire dirtyReleaseMessage_source = 1'h0; // @[Edges.scala:433:17] wire dirtyReleaseMessage_corrupt = 1'h0; // @[Edges.scala:433:17] wire _tl_out_c_valid_T = 1'h0; // @[DCache.scala:810:48] wire _tl_out_c_valid_T_1 = 1'h0; // @[DCache.scala:810:91] wire _tl_out_c_valid_T_2 = 1'h0; // @[DCache.scala:810:74] wire _tl_out_c_valid_T_4 = 1'h0; // @[DCache.scala:810:130] wire _dataArb_io_in_2_valid_T_1 = 1'h0; // @[DCache.scala:900:41] wire _metaArb_io_in_4_valid_T = 1'h0; // @[package.scala:16:47] wire _metaArb_io_in_4_valid_T_1 = 1'h0; // @[package.scala:16:47] wire _metaArb_io_in_4_valid_T_2 = 1'h0; // @[package.scala:81:59] wire _io_cpu_s2_xcpt_WIRE_miss = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_gpa_is_pte = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_pf_ld = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_pf_st = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_pf_inst = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_gf_ld = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_gf_st = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_gf_inst = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_ae_ld = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_ae_st = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_ae_inst = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_ma_ld = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_ma_st = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_ma_inst = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_cacheable = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_must_alloc = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_prefetchable = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_T_miss = 1'h0; // @[DCache.scala:933:24] wire _io_cpu_s2_xcpt_T_gpa_is_pte = 1'h0; // @[DCache.scala:933:24] wire _io_cpu_s2_xcpt_T_gf_ld = 1'h0; // @[DCache.scala:933:24] wire _io_cpu_s2_xcpt_T_gf_st = 1'h0; // @[DCache.scala:933:24] wire _io_cpu_s2_xcpt_T_gf_inst = 1'h0; // @[DCache.scala:933:24] wire _io_cpu_s2_xcpt_T_ma_inst = 1'h0; // @[DCache.scala:933:24] wire _s2_data_word_possibly_uncached_T = 1'h0; // @[DCache.scala:972:73] wire io_cpu_resp_bits_data_doZero = 1'h0; // @[AMOALU.scala:43:31] wire io_cpu_resp_bits_data_doZero_1 = 1'h0; // @[AMOALU.scala:43:31] wire io_cpu_resp_bits_data_doZero_2 = 1'h0; // @[AMOALU.scala:43:31] wire io_cpu_resp_bits_data_word_bypass_doZero = 1'h0; // @[AMOALU.scala:43:31] wire _flushDone_T = 1'h0; // @[DCache.scala:1010:37] wire flushDone = 1'h0; // @[DCache.scala:1010:57] wire _s1_flush_valid_T = 1'h0; // @[Decoupled.scala:51:35] wire _s1_flush_valid_T_2 = 1'h0; // @[DCache.scala:1014:43] wire _s1_flush_valid_T_4 = 1'h0; // @[DCache.scala:1014:62] wire _s1_flush_valid_T_6 = 1'h0; // @[DCache.scala:1014:93] wire _s1_flush_valid_T_8 = 1'h0; // @[DCache.scala:1014:122] wire _metaArb_io_in_5_valid_T = 1'h0; // @[DCache.scala:1015:41] wire _metaArb_io_in_5_valid_T_1 = 1'h0; // @[DCache.scala:1015:38] wire _clock_en_reg_T_14 = 1'h0; // @[DCache.scala:1069:19] wire _clock_en_reg_T_17 = 1'h0; // @[DCache.scala:1070:25] wire _clock_en_reg_T_19 = 1'h0; // @[DCache.scala:1071:5] wire _io_cpu_perf_release_T = 1'h0; // @[Decoupled.scala:51:35] wire io_cpu_perf_release_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _io_cpu_perf_release_last_T = 1'h0; // @[Edges.scala:232:25] wire io_cpu_perf_release_done = 1'h0; // @[Edges.scala:233:22] wire _io_cpu_perf_tlbMiss_T = 1'h0; // @[Decoupled.scala:51:35] wire _io_cpu_perf_canAcceptLoadThenLoad_T_50 = 1'h0; // @[DCache.scala:1191:57] wire io_cpu_clock_enabled = 1'h1; // @[DCache.scala:101:7] wire io_ptw_req_bits_valid = 1'h1; // @[DCache.scala:101:7] wire io_tlb_port_req_ready = 1'h1; // @[DCache.scala:101:7] wire pma_checker_io_req_ready = 1'h1; // @[DCache.scala:120:32] wire pma_checker_io_req_bits_passthrough = 1'h1; // @[DCache.scala:120:32] wire pma_checker_io_ptw_req_bits_valid = 1'h1; // @[DCache.scala:120:32] wire pma_checker__mpu_priv_T = 1'h1; // @[TLB.scala:415:52] wire pma_checker__homogeneous_T_47 = 1'h1; // @[TLBPermissions.scala:87:22] wire pma_checker__sector_hits_T_6 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__sector_hits_T_14 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__sector_hits_T_22 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__sector_hits_T_30 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__sector_hits_T_38 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__sector_hits_T_46 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__sector_hits_T_54 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__sector_hits_T_62 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__superpage_hits_T_3 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__superpage_hits_T_8 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__superpage_hits_T_13 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__superpage_hits_T_18 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__hitsVec_T_3 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__hitsVec_T_9 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__hitsVec_T_15 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__hitsVec_T_21 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__hitsVec_T_27 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__hitsVec_T_33 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__hitsVec_T_39 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__hitsVec_T_45 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__hitsVec_T_51 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__hitsVec_T_57 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__hitsVec_T_63 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__hitsVec_T_69 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__hitsVec_T_75 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__hits_T = 1'h1; // @[TLB.scala:442:18] wire pma_checker__newEntry_sr_T = 1'h1; // @[PTW.scala:141:47] wire pma_checker__newEntry_sw_T = 1'h1; // @[PTW.scala:141:47] wire pma_checker__newEntry_sx_T = 1'h1; // @[PTW.scala:141:47] wire pma_checker__ppn_T = 1'h1; // @[TLB.scala:502:30] wire pma_checker__stage1_bypass_T_1 = 1'h1; // @[TLB.scala:517:83] wire pma_checker__stage2_bypass_T = 1'h1; // @[TLB.scala:523:42] wire pma_checker__gpa_hits_hit_mask_T_3 = 1'h1; // @[TLB.scala:606:107] wire pma_checker__tlb_miss_T = 1'h1; // @[TLB.scala:613:32] wire pma_checker__tlb_miss_T_2 = 1'h1; // @[TLB.scala:613:56] wire pma_checker__tlb_miss_T_4 = 1'h1; // @[TLB.scala:613:67] wire pma_checker__io_req_ready_T = 1'h1; // @[TLB.scala:631:25] wire pma_checker__io_resp_gpa_page_T = 1'h1; // @[TLB.scala:657:20] wire pma_checker__io_ptw_req_bits_valid_T = 1'h1; // @[TLB.scala:663:28] wire metaArb_io_in_0_ready = 1'h1; // @[DCache.scala:135:28] wire metaArb_io_in_0_bits_write = 1'h1; // @[DCache.scala:135:28] wire metaArb_io_in_0_bits_way_en = 1'h1; // @[DCache.scala:135:28] wire metaArb_io_in_1_ready = 1'h1; // @[DCache.scala:135:28] wire metaArb_io_in_1_bits_write = 1'h1; // @[DCache.scala:135:28] wire metaArb_io_in_2_ready = 1'h1; // @[DCache.scala:135:28] wire metaArb_io_in_2_bits_write = 1'h1; // @[DCache.scala:135:28] wire metaArb_io_in_3_bits_write = 1'h1; // @[DCache.scala:135:28] wire metaArb_io_in_4_bits_write = 1'h1; // @[DCache.scala:135:28] wire metaArb_io_out_ready = 1'h1; // @[DCache.scala:135:28] wire metaArb_grant_1 = 1'h1; // @[Arbiter.scala:45:78] wire metaArb_grant_2 = 1'h1; // @[Arbiter.scala:45:78] wire metaArb__io_in_0_ready_T = 1'h1; // @[Arbiter.scala:153:19] wire metaArb__io_in_1_ready_T = 1'h1; // @[Arbiter.scala:153:19] wire metaArb__io_in_2_ready_T = 1'h1; // @[Arbiter.scala:153:19] wire dataArb_io_in_0_ready = 1'h1; // @[DCache.scala:152:28] wire dataArb_io_in_2_bits_wordMask = 1'h1; // @[DCache.scala:152:28] wire dataArb_io_in_2_bits_way_en = 1'h1; // @[DCache.scala:152:28] wire dataArb_io_in_3_bits_wordMask = 1'h1; // @[DCache.scala:152:28] wire dataArb_io_in_3_bits_way_en = 1'h1; // @[DCache.scala:152:28] wire dataArb_io_out_ready = 1'h1; // @[DCache.scala:152:28] wire dataArb__io_in_0_ready_T = 1'h1; // @[Arbiter.scala:153:19] wire _io_cpu_req_ready_T = 1'h1; // @[DCache.scala:233:38] wire _dataArb_io_in_3_bits_way_en_T = 1'h1; // @[DCache.scala:257:35] wire _s2_valid_not_killed_T = 1'h1; // @[DCache.scala:338:48] wire _s2_flush_valid_T = 1'h1; // @[DCache.scala:363:54] wire _s2_valid_hit_maybe_flush_pre_data_ecc_and_waw_T = 1'h1; // @[DCache.scala:397:74] wire _s2_valid_hit_pre_data_ecc_and_waw_T_1 = 1'h1; // @[DCache.scala:418:108] wire _s2_valid_hit_pre_data_ecc_T = 1'h1; // @[DCache.scala:420:73] wire _s2_valid_hit_pre_data_ecc_T_1 = 1'h1; // @[DCache.scala:420:88] wire _s2_valid_hit_T = 1'h1; // @[DCache.scala:422:51] wire _s2_valid_miss_T_1 = 1'h1; // @[DCache.scala:423:58] wire _s2_victimize_T = 1'h1; // @[DCache.scala:429:43] wire _s2_victim_tag_T_2 = 1'h1; // @[Mux.scala:32:36] wire _s2_victim_state_T = 1'h1; // @[Mux.scala:32:36] wire _r_T_117 = 1'h1; // @[Metadata.scala:140:24] wire _s2_dont_nack_misc_T = 1'h1; // @[DCache.scala:441:46] wire _s2_dont_nack_misc_T_4 = 1'h1; // @[DCache.scala:442:57] wire _metaArb_io_in_2_bits_write_T = 1'h1; // @[DCache.scala:463:34] wire _s2_valid_correct_T_1 = 1'h1; // @[DCache.scala:489:77] wire _pstore1_merge_T_1 = 1'h1; // @[DCache.scala:490:61] wire _pstore1_merge_T_3 = 1'h1; // @[DCache.scala:491:51] wire _pstore_drain_opportunistic_T_61 = 1'h1; // @[DCache.scala:502:95] wire _pstore1_valid_T_1 = 1'h1; // @[DCache.scala:490:61] wire _pstore1_valid_T_3 = 1'h1; // @[DCache.scala:491:51] wire _pstore_drain_T = 1'h1; // @[DCache.scala:516:5] wire _pstore_drain_T_3 = 1'h1; // @[DCache.scala:506:87] wire _pstore1_held_T_1 = 1'h1; // @[DCache.scala:490:61] wire _pstore1_held_T_3 = 1'h1; // @[DCache.scala:491:51] wire _pstore1_held_T_5 = 1'h1; // @[DCache.scala:521:38] wire _dataArb_io_in_0_valid_T = 1'h1; // @[DCache.scala:516:5] wire _dataArb_io_in_0_valid_T_3 = 1'h1; // @[DCache.scala:506:87] wire _dataArb_io_in_0_bits_wordMask_T = 1'h1; // @[DCache.scala:555:20] wire _io_cpu_s2_nack_cause_raw_T = 1'h1; // @[DCache.scala:574:59] wire _io_cpu_s2_nack_cause_raw_T_1 = 1'h1; // @[DCache.scala:574:74] wire _get_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _get_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _get_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _get_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _get_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _get_legal_T_11 = 1'h1; // @[Parameters.scala:92:38] wire _get_legal_T_12 = 1'h1; // @[Parameters.scala:92:33] wire _get_legal_T_13 = 1'h1; // @[Parameters.scala:684:29] wire _put_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _put_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _put_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _put_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _put_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _put_legal_T_11 = 1'h1; // @[Parameters.scala:92:38] wire _put_legal_T_12 = 1'h1; // @[Parameters.scala:92:33] wire _put_legal_T_13 = 1'h1; // @[Parameters.scala:684:29] wire _putpartial_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _putpartial_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _putpartial_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _putpartial_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _putpartial_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _putpartial_legal_T_11 = 1'h1; // @[Parameters.scala:92:38] wire _putpartial_legal_T_12 = 1'h1; // @[Parameters.scala:92:33] wire _putpartial_legal_T_13 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_30 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_31 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_32 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_33 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_60 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_61 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_62 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_63 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_90 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_91 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_92 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_93 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_120 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_121 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_122 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_123 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_150 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_151 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_152 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_153 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_180 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_181 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_182 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_183 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_210 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_211 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_212 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_213 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_240 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_241 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_242 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_243 = 1'h1; // @[Parameters.scala:684:29] wire _tl_out_a_valid_T = 1'h1; // @[DCache.scala:603:21] wire _tl_out_a_valid_T_5 = 1'h1; // @[DCache.scala:606:8] wire _tl_out_a_valid_T_7 = 1'h1; // @[DCache.scala:607:47] wire a_sel = 1'h1; // @[DCache.scala:630:66] wire canAcceptCachedGrant = 1'h1; // @[DCache.scala:670:30] wire uncachedRespIdxOH = 1'h1; // @[DCache.scala:672:90] wire _uncachedResp_T = 1'h1; // @[Mux.scala:32:36] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _r_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire c_last = 1'h1; // @[Edges.scala:232:33] wire _releaseRejected_T_1 = 1'h1; // @[DCache.scala:803:47] wire _tl_out_c_valid_T_5 = 1'h1; // @[DCache.scala:810:120] wire _dataArb_io_in_2_bits_wordMask_T = 1'h1; // @[DCache.scala:904:37] wire _dataArb_io_in_2_bits_way_en_T = 1'h1; // @[DCache.scala:906:35] wire _io_cpu_resp_valid_T_1 = 1'h1; // @[DCache.scala:949:73] wire _io_cpu_replay_next_T_2 = 1'h1; // @[DCache.scala:950:65] wire _s1_flush_valid_T_5 = 1'h1; // @[DCache.scala:1014:110] wire _s1_flush_valid_T_7 = 1'h1; // @[DCache.scala:1014:125] wire _metaArb_io_in_0_bits_way_en_T = 1'h1; // @[DCache.scala:1049:35] wire _clock_en_reg_T = 1'h1; // @[DCache.scala:1060:19] wire _clock_en_reg_T_2 = 1'h1; // @[DCache.scala:1060:44] wire _clock_en_reg_T_3 = 1'h1; // @[DCache.scala:1061:46] wire _clock_en_reg_T_4 = 1'h1; // @[DCache.scala:1062:31] wire _clock_en_reg_T_5 = 1'h1; // @[DCache.scala:1063:26] wire _clock_en_reg_T_6 = 1'h1; // @[DCache.scala:1064:14] wire _clock_en_reg_T_7 = 1'h1; // @[DCache.scala:1064:26] wire _clock_en_reg_T_8 = 1'h1; // @[DCache.scala:1065:14] wire _clock_en_reg_T_9 = 1'h1; // @[DCache.scala:1065:26] wire _clock_en_reg_T_10 = 1'h1; // @[DCache.scala:1066:27] wire _clock_en_reg_T_11 = 1'h1; // @[DCache.scala:1067:22] wire _clock_en_reg_T_12 = 1'h1; // @[DCache.scala:1067:42] wire _clock_en_reg_T_13 = 1'h1; // @[DCache.scala:1068:18] wire _clock_en_reg_T_15 = 1'h1; // @[DCache.scala:1068:35] wire _clock_en_reg_T_16 = 1'h1; // @[DCache.scala:1069:31] wire _clock_en_reg_T_18 = 1'h1; // @[DCache.scala:1070:22] wire _clock_en_reg_T_20 = 1'h1; // @[DCache.scala:1070:46] wire _clock_en_reg_T_21 = 1'h1; // @[DCache.scala:1071:23] wire _clock_en_reg_T_23 = 1'h1; // @[DCache.scala:1072:23] wire _clock_en_reg_T_25 = 1'h1; // @[DCache.scala:1072:54] wire _clock_en_reg_T_27 = 1'h1; // @[DCache.scala:1073:21] wire io_cpu_perf_release_first = 1'h1; // @[Edges.scala:231:25] wire _io_cpu_perf_release_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire io_cpu_perf_release_last = 1'h1; // @[Edges.scala:232:33] wire _io_cpu_perf_storeBufferEmptyAfterLoad_T_2 = 1'h1; // @[DCache.scala:1082:31] wire _io_cpu_perf_storeBufferEmptyAfterStore_T_5 = 1'h1; // @[DCache.scala:1087:31] wire _io_cpu_perf_canAcceptStoreThenLoad_T_3 = 1'h1; // @[DCache.scala:1089:72] wire _io_cpu_perf_canAcceptLoadThenLoad_T_56 = 1'h1; // @[DCache.scala:1092:115] wire [3:0] io_ptw_ptbr_mode = 4'h0; // @[DCache.scala:101:7] wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[DCache.scala:101:7] wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[DCache.scala:101:7] wire [3:0] pma_checker_io_ptw_ptbr_mode = 4'h0; // @[DCache.scala:120:32] wire [3:0] pma_checker_io_ptw_hgatp_mode = 4'h0; // @[DCache.scala:120:32] wire [3:0] pma_checker_io_ptw_vsatp_mode = 4'h0; // @[DCache.scala:120:32] wire [3:0] pma_checker_satp_mode = 4'h0; // @[TLB.scala:373:17] wire [3:0] pma_checker_real_hits_hi_hi = 4'h0; // @[package.scala:45:27] wire [3:0] pma_checker__multipleHits_T_31 = 4'h0; // @[Misc.scala:182:39] wire [3:0] tl_out_c_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _s1_probe_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _s1_probe_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _probe_bits_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _probe_bits_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _probe_bits_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _probe_bits_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _r_T_16 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _r_T_63 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _r_T_127 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _a_mask_T = 4'h0; // @[DCache.scala:582:90] wire [3:0] _atomics_WIRE_size = 4'h0; // @[DCache.scala:587:51] wire [3:0] _atomics_WIRE_1_size = 4'h0; // @[DCache.scala:587:38] wire [3:0] _tl_out_a_bits_WIRE_size = 4'h0; // @[DCache.scala:1209:67] wire [3:0] _tl_out_a_bits_WIRE_1_size = 4'h0; // @[DCache.scala:1209:54] wire [3:0] _metaArb_io_in_3_bits_data_T_5 = 4'h0; // @[Metadata.scala:87:10] wire [3:0] _block_probe_for_pending_release_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _block_probe_for_pending_release_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _metaArb_io_in_6_valid_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _metaArb_io_in_6_valid_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _metaArb_io_in_6_bits_idx_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _metaArb_io_in_6_bits_idx_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _metaArb_io_in_6_bits_addr_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _metaArb_io_in_6_bits_addr_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] nackResponseMessage_size = 4'h0; // @[Edges.scala:416:17] wire [3:0] cleanReleaseMessage_size = 4'h0; // @[Edges.scala:416:17] wire [3:0] dirtyReleaseMessage_size = 4'h0; // @[Edges.scala:433:17] wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[DCache.scala:101:7] wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[DCache.scala:101:7] wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[DCache.scala:101:7] wire [15:0] pma_checker_io_ptw_ptbr_asid = 16'h0; // @[DCache.scala:120:32] wire [15:0] pma_checker_io_ptw_hgatp_asid = 16'h0; // @[DCache.scala:120:32] wire [15:0] pma_checker_io_ptw_vsatp_asid = 16'h0; // @[DCache.scala:120:32] wire [15:0] pma_checker_satp_asid = 16'h0; // @[TLB.scala:373:17] wire [43:0] io_ptw_ptbr_ppn = 44'h0; // @[DCache.scala:101:7] wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[DCache.scala:101:7] wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[DCache.scala:101:7] wire [43:0] pma_checker_io_ptw_resp_bits_pte_ppn = 44'h0; // @[DCache.scala:120:32] wire [43:0] pma_checker_io_ptw_ptbr_ppn = 44'h0; // @[DCache.scala:120:32] wire [43:0] pma_checker_io_ptw_hgatp_ppn = 44'h0; // @[DCache.scala:120:32] wire [43:0] pma_checker_io_ptw_vsatp_ppn = 44'h0; // @[DCache.scala:120:32] wire [43:0] pma_checker_satp_ppn = 44'h0; // @[TLB.scala:373:17] wire [1:0] io_ptw_status_dprv = 2'h3; // @[DCache.scala:101:7] wire [1:0] io_ptw_status_prv = 2'h3; // @[DCache.scala:101:7] wire [1:0] hitState_meta_state = 2'h3; // @[Metadata.scala:160:20] wire [1:0] _r_T_11 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_13 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_21 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_23 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _metaArb_io_in_3_bits_data_T_8 = 2'h3; // @[Metadata.scala:24:15] wire [22:0] io_ptw_status_zero2 = 23'h0; // @[DCache.scala:101:7] wire [22:0] pma_checker_io_ptw_status_zero2 = 23'h0; // @[DCache.scala:120:32] wire [22:0] pma_checker_io_ptw_gstatus_zero2 = 23'h0; // @[DCache.scala:120:32] wire [7:0] io_cpu_req_bits_mask = 8'h0; // @[DCache.scala:101:7] wire [7:0] io_ptw_status_zero1 = 8'h0; // @[DCache.scala:101:7] wire [7:0] pma_checker_io_ptw_status_zero1 = 8'h0; // @[DCache.scala:120:32] wire [7:0] pma_checker_io_ptw_gstatus_zero1 = 8'h0; // @[DCache.scala:120:32] wire [7:0] metaArb_io_in_0_bits_idx = 8'h0; // @[DCache.scala:135:28] wire [7:0] metaArb_io_in_4_bits_idx = 8'h0; // @[DCache.scala:135:28] wire [7:0] metaArb_io_in_5_bits_idx = 8'h0; // @[DCache.scala:135:28] wire [7:0] metaArb_io_in_6_bits_idx = 8'h0; // @[DCache.scala:135:28] wire [7:0] _s1_probe_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _s1_probe_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _probe_bits_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _probe_bits_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _probe_bits_WIRE_2_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _probe_bits_WIRE_3_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] s0_req_mask = 8'h0; // @[DCache.scala:192:24] wire [7:0] _metaArb_io_in_1_bits_idx_T = 8'h0; // @[DCache.scala:1200:47] wire [7:0] _pstore2_storegen_mask_mergedMask_T = 8'h0; // @[DCache.scala:533:42] wire [7:0] _atomics_WIRE_mask = 8'h0; // @[DCache.scala:587:51] wire [7:0] _atomics_WIRE_1_mask = 8'h0; // @[DCache.scala:587:38] wire [7:0] _tl_out_a_bits_WIRE_mask = 8'h0; // @[DCache.scala:1209:67] wire [7:0] _tl_out_a_bits_WIRE_1_mask = 8'h0; // @[DCache.scala:1209:54] wire [7:0] _block_probe_for_pending_release_ack_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _block_probe_for_pending_release_ack_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _metaArb_io_in_6_valid_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _metaArb_io_in_6_valid_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _metaArb_io_in_6_bits_idx_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _metaArb_io_in_6_bits_idx_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _metaArb_io_in_6_bits_idx_T = 8'h0; // @[DCache.scala:1200:47] wire [7:0] _metaArb_io_in_6_bits_addr_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _metaArb_io_in_6_bits_addr_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _dataArb_io_in_2_bits_addr_T = 8'h0; // @[DCache.scala:1200:47] wire [7:0] _metaArb_io_in_4_bits_idx_T = 8'h0; // @[DCache.scala:1200:47] wire [7:0] _metaArb_io_in_5_bits_idx_T = 8'h0; // @[DCache.scala:1017:44] wire [1:0] io_ptw_status_sxl = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_status_uxl = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_status_xs = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_status_vs = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_hstatus_vsxl = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_gstatus_uxl = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_gstatus_xs = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_0_cfg_res = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_1_cfg_res = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_2_cfg_res = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_3_cfg_res = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_4_cfg_res = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_5_cfg_res = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_6_cfg_res = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_7_cfg_res = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_tlb_port_req_bits_size = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_tlb_port_req_bits_prv = 2'h0; // @[DCache.scala:101:7] wire [1:0] pma_checker_io_ptw_resp_bits_pte_reserved_for_software = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_resp_bits_level = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_status_dprv = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_status_prv = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_status_sxl = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_status_uxl = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_status_xs = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_status_fs = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_status_mpp = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_status_vs = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_hstatus_vsxl = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_hstatus_zero3 = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_hstatus_zero2 = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_gstatus_dprv = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_gstatus_prv = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_gstatus_sxl = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_gstatus_uxl = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_gstatus_xs = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_gstatus_fs = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_gstatus_mpp = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_gstatus_vs = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_0_cfg_res = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_0_cfg_a = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_1_cfg_res = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_1_cfg_a = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_2_cfg_res = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_2_cfg_a = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_3_cfg_res = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_3_cfg_a = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_4_cfg_res = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_4_cfg_a = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_5_cfg_res = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_5_cfg_a = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_6_cfg_res = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_6_cfg_a = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_7_cfg_res = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_7_cfg_a = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_real_hits_lo_lo_hi = 2'h0; // @[package.scala:45:27] wire [1:0] pma_checker_real_hits_lo_hi_hi = 2'h0; // @[package.scala:45:27] wire [1:0] pma_checker_real_hits_hi_lo_hi = 2'h0; // @[package.scala:45:27] wire [1:0] pma_checker_real_hits_hi_hi_lo = 2'h0; // @[package.scala:45:27] wire [1:0] pma_checker_real_hits_hi_hi_hi = 2'h0; // @[package.scala:45:27] wire [1:0] pma_checker__special_entry_level_T = 2'h0; // @[package.scala:163:13] wire [1:0] pma_checker_special_entry_data_0_lo_lo_lo = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_special_entry_data_0_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_special_entry_data_0_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_special_entry_data_0_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_special_entry_data_0_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_waddr = 2'h0; // @[TLB.scala:477:22] wire [1:0] pma_checker_superpage_entries_0_data_0_lo_lo_lo = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_0_data_0_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_0_data_0_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_0_data_0_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_0_data_0_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_1_data_0_lo_lo_lo = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_1_data_0_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_1_data_0_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_1_data_0_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_1_data_0_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_2_data_0_lo_lo_lo = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_2_data_0_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_2_data_0_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_2_data_0_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_2_data_0_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_3_data_0_lo_lo_lo = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_3_data_0_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_3_data_0_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_3_data_0_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_3_data_0_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_idx = 2'h0; // @[package.scala:163:13] wire [1:0] pma_checker_sectored_entries_0_0_data_lo_lo_lo = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_0_data_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_0_data_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_0_data_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_0_data_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_idx_1 = 2'h0; // @[package.scala:163:13] wire [1:0] pma_checker_sectored_entries_0_1_data_lo_lo_lo = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_1_data_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_1_data_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_1_data_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_1_data_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_idx_2 = 2'h0; // @[package.scala:163:13] wire [1:0] pma_checker_sectored_entries_0_2_data_lo_lo_lo = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_2_data_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_2_data_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_2_data_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_2_data_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_idx_3 = 2'h0; // @[package.scala:163:13] wire [1:0] pma_checker_sectored_entries_0_3_data_lo_lo_lo = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_3_data_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_3_data_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_3_data_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_3_data_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_idx_4 = 2'h0; // @[package.scala:163:13] wire [1:0] pma_checker_sectored_entries_0_4_data_lo_lo_lo = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_4_data_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_4_data_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_4_data_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_4_data_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_idx_5 = 2'h0; // @[package.scala:163:13] wire [1:0] pma_checker_sectored_entries_0_5_data_lo_lo_lo = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_5_data_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_5_data_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_5_data_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_5_data_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_idx_6 = 2'h0; // @[package.scala:163:13] wire [1:0] pma_checker_sectored_entries_0_6_data_lo_lo_lo = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_6_data_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_6_data_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_6_data_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_6_data_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_idx_7 = 2'h0; // @[package.scala:163:13] wire [1:0] pma_checker_sectored_entries_0_7_data_lo_lo_lo = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_7_data_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_7_data_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_7_data_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_7_data_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker__c_array_T = 2'h0; // @[TLB.scala:537:25] wire [1:0] pma_checker__prefetchable_array_T_1 = 2'h0; // @[TLB.scala:547:59] wire [1:0] pma_checker__multipleHits_T_3 = 2'h0; // @[Misc.scala:182:39] wire [1:0] pma_checker__multipleHits_T_12 = 2'h0; // @[Misc.scala:182:39] wire [1:0] pma_checker__multipleHits_T_24 = 2'h0; // @[Misc.scala:182:39] wire [1:0] pma_checker__multipleHits_T_32 = 2'h0; // @[Misc.scala:181:37] wire [1:0] pma_checker__multipleHits_T_37 = 2'h0; // @[Misc.scala:182:39] wire [1:0] _s1_probe_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _s1_probe_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _probe_bits_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _probe_bits_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _probe_bits_WIRE_2_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _probe_bits_WIRE_3_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] hitState_meta_1_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] dummyMeta_meta_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] dummyMeta_coh_state = 2'h0; // @[HellaCache.scala:305:20] wire [1:0] _s2_valid_no_xcpt_T_1 = 2'h0; // @[DCache.scala:332:54] wire [1:0] s2_meta_corrected_0_coh_state = 2'h0; // @[DCache.scala:361:99] wire [1:0] _s2_meta_corrected_T_1 = 2'h0; // @[DCache.scala:361:99] wire [1:0] _r_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_5 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_15 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_75 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_79 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_83 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_87 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_91 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_139 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_143 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_147 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_151 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_155 = 2'h0; // @[Misc.scala:38:63] wire [1:0] metaArb_io_in_1_bits_data_new_meta_coh_state = 2'h0; // @[DCache.scala:456:31] wire [1:0] metaArb_io_in_1_bits_data_new_meta_coh_meta_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] _metaArb_io_in_3_bits_data_T_2 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _metaArb_io_in_3_bits_data_T_4 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _block_probe_for_pending_release_ack_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _block_probe_for_pending_release_ack_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _metaArb_io_in_6_valid_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _metaArb_io_in_6_valid_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _metaArb_io_in_6_bits_idx_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _metaArb_io_in_6_bits_idx_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _metaArb_io_in_6_bits_addr_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _metaArb_io_in_6_bits_addr_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _io_cpu_s2_xcpt_WIRE_size = 2'h0; // @[DCache.scala:933:74] wire [1:0] metaArb_io_in_0_bits_data_meta_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] metaArb_io_in_0_bits_data_meta_1_coh_state = 2'h0; // @[HellaCache.scala:305:20] wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[DCache.scala:101:7] wire [29:0] pma_checker_io_ptw_hstatus_zero6 = 30'h0; // @[DCache.scala:120:32] wire [29:0] pma_checker_io_ptw_pmp_0_addr = 30'h0; // @[DCache.scala:120:32] wire [29:0] pma_checker_io_ptw_pmp_1_addr = 30'h0; // @[DCache.scala:120:32] wire [29:0] pma_checker_io_ptw_pmp_2_addr = 30'h0; // @[DCache.scala:120:32] wire [29:0] pma_checker_io_ptw_pmp_3_addr = 30'h0; // @[DCache.scala:120:32] wire [29:0] pma_checker_io_ptw_pmp_4_addr = 30'h0; // @[DCache.scala:120:32] wire [29:0] pma_checker_io_ptw_pmp_5_addr = 30'h0; // @[DCache.scala:120:32] wire [29:0] pma_checker_io_ptw_pmp_6_addr = 30'h0; // @[DCache.scala:120:32] wire [29:0] pma_checker_io_ptw_pmp_7_addr = 30'h0; // @[DCache.scala:120:32] wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[DCache.scala:101:7] wire [8:0] pma_checker_io_ptw_hstatus_zero5 = 9'h0; // @[DCache.scala:120:32] wire [8:0] r_beats1_decode_1 = 9'h0; // @[Edges.scala:220:59] wire [8:0] r_beats1_1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _r_count_T_1 = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _r_counter_T_1 = 9'h0; // @[Edges.scala:236:21] wire [8:0] io_cpu_perf_release_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] io_cpu_perf_release_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _io_cpu_perf_release_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] io_cpu_perf_release_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _io_cpu_perf_release_counter_T = 9'h0; // @[Edges.scala:236:21] wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[DCache.scala:101:7] wire [5:0] pma_checker_io_ptw_hstatus_vgein = 6'h0; // @[DCache.scala:120:32] wire [5:0] pma_checker_real_hits_lo = 6'h0; // @[package.scala:45:27] wire [5:0] pma_checker_special_entry_data_0_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_superpage_entries_0_data_0_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_superpage_entries_1_data_0_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_superpage_entries_2_data_0_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_superpage_entries_3_data_0_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_0_data_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_1_data_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_2_data_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_3_data_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_4_data_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_5_data_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_6_data_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_7_data_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker__multipleHits_T = 6'h0; // @[Misc.scala:181:37] wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[DCache.scala:101:7] wire [4:0] io_tlb_port_req_bits_cmd = 5'h0; // @[DCache.scala:101:7] wire [4:0] pma_checker_io_ptw_hstatus_zero1 = 5'h0; // @[DCache.scala:120:32] wire [4:0] _io_cpu_s2_xcpt_WIRE_cmd = 5'h0; // @[DCache.scala:933:74] wire [8:0] r_counter1_1 = 9'h1FF; // @[Edges.scala:230:28] wire [8:0] io_cpu_perf_release_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _r_counter1_T_1 = 10'h3FF; // @[Edges.scala:230:28] wire [9:0] _io_cpu_perf_release_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [11:0] pma_checker__gpa_hits_hit_mask_T_2 = 12'h0; // @[TLB.scala:606:24] wire [11:0] pma_checker__io_resp_gpa_offset_T = 12'h0; // @[TLB.scala:658:47] wire [11:0] _r_beats1_decode_T_5 = 12'h0; // @[package.scala:243:46] wire [11:0] _io_cpu_perf_release_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _r_beats1_decode_T_4 = 12'hFFF; // @[package.scala:243:76] wire [11:0] _io_cpu_perf_release_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _r_beats1_decode_T_3 = 27'hFFF; // @[package.scala:243:71] wire [26:0] _io_cpu_perf_release_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [19:0] pma_checker_refill_ppn = 20'h0; // @[TLB.scala:406:44] wire [19:0] pma_checker_newEntry_ppn = 20'h0; // @[TLB.scala:449:24] wire [19:0] pma_checker__ppn_T_2 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_3 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_4 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_5 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_6 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_7 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_8 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_9 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_10 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_11 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_12 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_13 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_14 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_16 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_17 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_18 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_19 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_20 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_21 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_22 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_23 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_24 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_25 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_26 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_27 = 20'h0; // @[Mux.scala:30:73] wire [19:0] metaArb_io_in_0_bits_data = 20'h0; // @[DCache.scala:135:28] wire [19:0] metaArb_io_in_1_bits_data = 20'h0; // @[DCache.scala:135:28] wire [19:0] s1_meta_0 = 20'h0; // @[DCache.scala:306:58] wire [19:0] _s2_meta_corrected_WIRE = 20'h0; // @[DCache.scala:361:99] wire [19:0] _metaArb_io_in_1_bits_data_T = 20'h0; // @[DCache.scala:458:14] wire [19:0] _metaArb_io_in_0_bits_data_T = 20'h0; // @[DCache.scala:1050:85] wire [17:0] dummyMeta_tag = 18'h0; // @[HellaCache.scala:305:20] wire [17:0] s2_meta_corrected_0_tag = 18'h0; // @[DCache.scala:361:99] wire [17:0] _s2_meta_corrected_T = 18'h0; // @[DCache.scala:361:99] wire [17:0] metaArb_io_in_1_bits_data_new_meta_tag = 18'h0; // @[DCache.scala:456:31] wire [17:0] _metaArb_io_in_4_bits_data_T = 18'h0; // @[DCache.scala:913:78] wire [17:0] metaArb_io_in_4_bits_data_meta_tag = 18'h0; // @[HellaCache.scala:305:20] wire [17:0] metaArb_io_in_0_bits_data_meta_1_tag = 18'h0; // @[HellaCache.scala:305:20] wire [13:0] pma_checker_lrscAllowed = 14'h0; // @[TLB.scala:580:24] wire [13:0] pma_checker__gf_ld_array_T_2 = 14'h0; // @[TLB.scala:600:46] wire [13:0] pma_checker_gf_ld_array = 14'h0; // @[TLB.scala:600:24] wire [13:0] pma_checker__gf_st_array_T_1 = 14'h0; // @[TLB.scala:601:53] wire [13:0] pma_checker_gf_st_array = 14'h0; // @[TLB.scala:601:24] wire [13:0] pma_checker__gf_inst_array_T = 14'h0; // @[TLB.scala:602:36] wire [13:0] pma_checker_gf_inst_array = 14'h0; // @[TLB.scala:602:26] wire [13:0] pma_checker_gpa_hits_need_gpa_mask = 14'h0; // @[TLB.scala:605:73] wire [13:0] pma_checker__io_resp_gf_ld_T_1 = 14'h0; // @[TLB.scala:637:58] wire [13:0] pma_checker__io_resp_gf_st_T_1 = 14'h0; // @[TLB.scala:638:65] wire [13:0] pma_checker__io_resp_gf_inst_T = 14'h0; // @[TLB.scala:639:48] wire [13:0] _dataArb_io_in_2_bits_addr_T_1 = 14'h0; // @[DCache.scala:903:55] wire [13:0] _metaArb_io_in_4_bits_addr_T_1 = 14'h0; // @[DCache.scala:912:90] wire [13:0] _metaArb_io_in_5_bits_addr_T_1 = 14'h0; // @[DCache.scala:1018:98] wire [7:0] flushCounterWrap = 8'h1; // @[DCache.scala:1011:42] wire [8:0] flushCounterNext = 9'h1; // @[DCache.scala:1009:39] wire [31:0] pma_checker_io_ptw_status_isa = 32'h0; // @[DCache.scala:120:32] wire [31:0] pma_checker_io_ptw_gstatus_isa = 32'h0; // @[DCache.scala:120:32] wire [31:0] pma_checker_io_ptw_pmp_0_mask = 32'h0; // @[DCache.scala:120:32] wire [31:0] pma_checker_io_ptw_pmp_1_mask = 32'h0; // @[DCache.scala:120:32] wire [31:0] pma_checker_io_ptw_pmp_2_mask = 32'h0; // @[DCache.scala:120:32] wire [31:0] pma_checker_io_ptw_pmp_3_mask = 32'h0; // @[DCache.scala:120:32] wire [31:0] pma_checker_io_ptw_pmp_4_mask = 32'h0; // @[DCache.scala:120:32] wire [31:0] pma_checker_io_ptw_pmp_5_mask = 32'h0; // @[DCache.scala:120:32] wire [31:0] pma_checker_io_ptw_pmp_6_mask = 32'h0; // @[DCache.scala:120:32] wire [31:0] pma_checker_io_ptw_pmp_7_mask = 32'h0; // @[DCache.scala:120:32] wire [31:0] tl_out_c_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _s1_probe_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _s1_probe_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _probe_bits_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _probe_bits_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _probe_bits_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _probe_bits_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _atomics_WIRE_address = 32'h0; // @[DCache.scala:587:51] wire [31:0] _atomics_WIRE_1_address = 32'h0; // @[DCache.scala:587:38] wire [31:0] _tl_out_a_bits_WIRE_address = 32'h0; // @[DCache.scala:1209:67] wire [31:0] _tl_out_a_bits_WIRE_1_address = 32'h0; // @[DCache.scala:1209:54] wire [31:0] _block_probe_for_pending_release_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _block_probe_for_pending_release_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _block_probe_for_pending_release_ack_T = 32'h0; // @[DCache.scala:767:88] wire [31:0] _metaArb_io_in_6_valid_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _metaArb_io_in_6_valid_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _metaArb_io_in_6_bits_idx_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _metaArb_io_in_6_bits_idx_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _metaArb_io_in_6_bits_addr_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _metaArb_io_in_6_bits_addr_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] nackResponseMessage_address = 32'h0; // @[Edges.scala:416:17] wire [31:0] cleanReleaseMessage_address = 32'h0; // @[Edges.scala:416:17] wire [31:0] dirtyReleaseMessage_address = 32'h0; // @[Edges.scala:433:17] wire [31:0] _io_cpu_s2_xcpt_WIRE_paddr = 32'h0; // @[DCache.scala:933:74] wire [2:0] pma_checker_real_hits_lo_lo = 3'h0; // @[package.scala:45:27] wire [2:0] pma_checker_real_hits_lo_hi = 3'h0; // @[package.scala:45:27] wire [2:0] pma_checker_real_hits_hi_lo = 3'h0; // @[package.scala:45:27] wire [2:0] pma_checker_special_entry_data_0_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_special_entry_data_0_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_special_entry_data_0_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_0_data_0_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_0_data_0_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_0_data_0_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_1_data_0_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_1_data_0_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_1_data_0_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_2_data_0_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_2_data_0_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_2_data_0_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_3_data_0_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_3_data_0_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_3_data_0_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_waddr_1 = 3'h0; // @[TLB.scala:485:22] wire [2:0] pma_checker_sectored_entries_0_0_data_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_0_data_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_0_data_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_1_data_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_1_data_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_1_data_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_2_data_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_2_data_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_2_data_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_3_data_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_3_data_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_3_data_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_4_data_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_4_data_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_4_data_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_5_data_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_5_data_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_5_data_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_6_data_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_6_data_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_6_data_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_7_data_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_7_data_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_7_data_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_state_vec_0_left_subtree_state = 3'h0; // @[package.scala:163:13] wire [2:0] pma_checker_state_vec_0_right_subtree_state = 3'h0; // @[Replacement.scala:198:38] wire [2:0] pma_checker__multipleHits_T_1 = 3'h0; // @[Misc.scala:181:37] wire [2:0] pma_checker__multipleHits_T_10 = 3'h0; // @[Misc.scala:182:39] wire [2:0] pma_checker__multipleHits_T_22 = 3'h0; // @[Misc.scala:181:37] wire [2:0] _s1_probe_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _s1_probe_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _probe_bits_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _probe_bits_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _probe_bits_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _probe_bits_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] get_param = 3'h0; // @[Edges.scala:460:17] wire [2:0] put_opcode = 3'h0; // @[Edges.scala:480:17] wire [2:0] put_param = 3'h0; // @[Edges.scala:480:17] wire [2:0] putpartial_param = 3'h0; // @[Edges.scala:500:17] wire [2:0] _atomics_WIRE_opcode = 3'h0; // @[DCache.scala:587:51] wire [2:0] _atomics_WIRE_param = 3'h0; // @[DCache.scala:587:51] wire [2:0] _atomics_WIRE_1_opcode = 3'h0; // @[DCache.scala:587:38] wire [2:0] _atomics_WIRE_1_param = 3'h0; // @[DCache.scala:587:38] wire [2:0] atomics_a_1_param = 3'h0; // @[Edges.scala:534:17] wire [2:0] atomics_a_5_param = 3'h0; // @[Edges.scala:517:17] wire [2:0] _tl_out_a_bits_WIRE_opcode = 3'h0; // @[DCache.scala:1209:67] wire [2:0] _tl_out_a_bits_WIRE_param = 3'h0; // @[DCache.scala:1209:67] wire [2:0] _tl_out_a_bits_WIRE_1_opcode = 3'h0; // @[DCache.scala:1209:54] wire [2:0] _tl_out_a_bits_WIRE_1_param = 3'h0; // @[DCache.scala:1209:54] wire [2:0] _block_probe_for_pending_release_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _block_probe_for_pending_release_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _metaArb_io_in_6_valid_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _metaArb_io_in_6_valid_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _metaArb_io_in_6_bits_idx_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _metaArb_io_in_6_bits_idx_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _metaArb_io_in_6_bits_addr_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _metaArb_io_in_6_bits_addr_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [1:0] _r_T_7 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_9 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_17 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_19 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] s2_victim_way = 2'h1; // @[OneHot.scala:58:35] wire [1:0] dataArb_io_in_0_bits_wordMask_wordMask = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _dataArb_io_in_0_bits_wordMask_T_2 = 2'h1; // @[DCache.scala:555:20] wire [1:0] _metaArb_io_in_3_bits_data_T_6 = 2'h1; // @[Metadata.scala:25:15] wire [20:0] pma_checker_io_ptw_req_bits_bits_addr = 21'h0; // @[DCache.scala:120:32] wire [20:0] pma_checker_special_entry_data_0_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_superpage_entries_0_data_0_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_superpage_entries_1_data_0_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_superpage_entries_2_data_0_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_superpage_entries_3_data_0_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_sectored_entries_0_0_data_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_sectored_entries_0_1_data_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_sectored_entries_0_2_data_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_sectored_entries_0_3_data_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_sectored_entries_0_4_data_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_sectored_entries_0_5_data_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_sectored_entries_0_6_data_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_sectored_entries_0_7_data_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker__io_resp_gpa_page_T_2 = 21'h0; // @[TLB.scala:657:58] wire [63:0] io_cpu_req_bits_data = 64'h0; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_2_sdata = 64'h0; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_3_sdata = 64'h0; // @[DCache.scala:101:7] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_0_wdata = 64'h0; // @[DCache.scala:120:32] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_0_value = 64'h0; // @[DCache.scala:120:32] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[DCache.scala:120:32] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_1_wdata = 64'h0; // @[DCache.scala:120:32] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_1_value = 64'h0; // @[DCache.scala:120:32] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[DCache.scala:120:32] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_2_wdata = 64'h0; // @[DCache.scala:120:32] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_2_value = 64'h0; // @[DCache.scala:120:32] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_2_sdata = 64'h0; // @[DCache.scala:120:32] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_3_wdata = 64'h0; // @[DCache.scala:120:32] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_3_value = 64'h0; // @[DCache.scala:120:32] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_3_sdata = 64'h0; // @[DCache.scala:120:32] wire [63:0] tl_out_c_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _s1_probe_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _s1_probe_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _probe_bits_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _probe_bits_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _probe_bits_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _probe_bits_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] s0_req_data = 64'h0; // @[DCache.scala:192:24] wire [63:0] get_data = 64'h0; // @[Edges.scala:460:17] wire [63:0] _atomics_WIRE_data = 64'h0; // @[DCache.scala:587:51] wire [63:0] _atomics_WIRE_1_data = 64'h0; // @[DCache.scala:587:38] wire [63:0] _tl_out_a_bits_WIRE_data = 64'h0; // @[DCache.scala:1209:67] wire [63:0] _tl_out_a_bits_WIRE_1_data = 64'h0; // @[DCache.scala:1209:54] wire [63:0] _block_probe_for_pending_release_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _block_probe_for_pending_release_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _metaArb_io_in_6_valid_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _metaArb_io_in_6_valid_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _metaArb_io_in_6_bits_idx_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _metaArb_io_in_6_bits_idx_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _metaArb_io_in_6_bits_addr_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _metaArb_io_in_6_bits_addr_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] nackResponseMessage_data = 64'h0; // @[Edges.scala:416:17] wire [63:0] cleanReleaseMessage_data = 64'h0; // @[Edges.scala:416:17] wire [63:0] dirtyReleaseMessage_data = 64'h0; // @[Edges.scala:433:17] wire [63:0] _s2_data_word_possibly_uncached_T_1 = 64'h0; // @[DCache.scala:972:43] wire [32:0] pma_checker_io_sfence_bits_addr = 33'h0; // @[DCache.scala:120:32] wire [32:0] pma_checker_io_ptw_resp_bits_gpa_bits = 33'h0; // @[DCache.scala:120:32] wire [33:0] io_tlb_port_req_bits_vaddr = 34'h0; // @[DCache.scala:101:7] wire [33:0] _io_cpu_s2_xcpt_WIRE_gpa = 34'h0; // @[DCache.scala:933:74] wire [7:0] dataArb_io_in_2_bits_eccMask = 8'hFF; // @[DCache.scala:152:28] wire [7:0] dataArb_io_in_3_bits_eccMask = 8'hFF; // @[DCache.scala:152:28] wire [7:0] _dataArb_io_in_3_bits_wordMask_T = 8'hFF; // @[DCache.scala:254:9] wire [7:0] _dataArb_io_in_3_bits_eccMask_T = 8'hFF; // @[DCache.scala:256:36] wire [7:0] _dataArb_io_in_2_bits_eccMask_T = 8'hFF; // @[DCache.scala:905:36] wire [2:0] tl_out_c_bits_param = 3'h5; // @[Bundles.scala:265:61] wire [2:0] nackResponseMessage_param = 3'h5; // @[Edges.scala:416:17] wire [2:0] dirtyReleaseMessage_opcode = 3'h5; // @[Edges.scala:433:17] wire [2:0] tl_out_c_bits_opcode = 3'h4; // @[Bundles.scala:265:61] wire [2:0] get_opcode = 3'h4; // @[Edges.scala:460:17] wire [2:0] atomics_a_4_param = 3'h4; // @[Edges.scala:517:17] wire [2:0] nackResponseMessage_opcode = 3'h4; // @[Edges.scala:416:17] wire [2:0] cleanReleaseMessage_opcode = 3'h4; // @[Edges.scala:416:17] wire [9:0] pma_checker_io_ptw_resp_bits_pte_reserved_for_future = 10'h0; // @[DCache.scala:120:32] wire [9:0] _releaseDataBeat_T = 10'h0; // @[DCache.scala:804:28] wire [3:0] _r_T_24 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _metaArb_io_in_3_bits_data_T_9 = 4'hC; // @[Metadata.scala:89:10] wire [3:0] _r_T_20 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _r_T_67 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _r_T_131 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _metaArb_io_in_3_bits_data_T_7 = 4'h4; // @[Metadata.scala:88:10] wire [3:0] _r_T_6 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _r_T_62 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _r_T_126 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _metaArb_io_in_3_bits_data_T_3 = 4'h1; // @[Metadata.scala:86:10] wire [1:0] _r_T_118 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _r_T_120 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _r_T_122 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _s1_data_way_T = 2'h2; // @[DCache.scala:694:32] wire [2:0] atomics_a_opcode = 3'h3; // @[Edges.scala:534:17] wire [2:0] atomics_a_param = 3'h3; // @[Edges.scala:534:17] wire [2:0] atomics_a_1_opcode = 3'h3; // @[Edges.scala:534:17] wire [2:0] atomics_a_2_opcode = 3'h3; // @[Edges.scala:534:17] wire [2:0] atomics_a_3_opcode = 3'h3; // @[Edges.scala:534:17] wire [2:0] atomics_a_8_param = 3'h3; // @[Edges.scala:517:17] wire [2:0] atomics_a_3_param = 3'h2; // @[Edges.scala:534:17] wire [2:0] atomics_a_4_opcode = 3'h2; // @[Edges.scala:517:17] wire [2:0] atomics_a_5_opcode = 3'h2; // @[Edges.scala:517:17] wire [2:0] atomics_a_6_opcode = 3'h2; // @[Edges.scala:517:17] wire [2:0] atomics_a_7_opcode = 3'h2; // @[Edges.scala:517:17] wire [2:0] atomics_a_7_param = 3'h2; // @[Edges.scala:517:17] wire [2:0] atomics_a_8_opcode = 3'h2; // @[Edges.scala:517:17] wire [2:0] putpartial_opcode = 3'h1; // @[Edges.scala:500:17] wire [2:0] atomics_a_2_param = 3'h1; // @[Edges.scala:534:17] wire [2:0] atomics_a_6_param = 3'h1; // @[Edges.scala:517:17] wire [3:0] _r_T_71 = 4'h8; // @[Metadata.scala:133:10] wire [3:0] _r_T_135 = 4'h8; // @[Metadata.scala:133:10] wire [3:0] _r_T_70 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _r_T_134 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _r_T_69 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _r_T_133 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _r_T_68 = 4'hB; // @[Metadata.scala:130:10] wire [3:0] _r_T_132 = 4'hB; // @[Metadata.scala:130:10] wire [3:0] _r_T_18 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _r_T_66 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] _r_T_130 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] _r_T_10 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _r_T_65 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] _r_T_129 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] _r_T_8 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _r_T_64 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _r_T_128 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _r_T_4 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _r_T_61 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _r_T_125 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _r_T_2 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _r_T_60 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _r_T_124 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _r_T_22 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r_T_14 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _r_T_12 = 4'hF; // @[Metadata.scala:65:10] wire [31:0] _inScratchpad_T_2 = 32'h80004000; // @[DCache.scala:303:70] wire [32:0] _inScratchpad_T_1 = 33'h80004000; // @[DCache.scala:303:70] wire [31:0] baseAddr = 32'h80000000; // @[DCache.scala:302:93] wire [6:0] pma_checker_real_hits_hi = 7'h0; // @[package.scala:45:27] wire [6:0] pma_checker__state_vec_WIRE_0 = 7'h0; // @[Replacement.scala:305:25] wire [6:0] pma_checker__multipleHits_T_21 = 7'h0; // @[Misc.scala:182:39] wire [12:0] pma_checker_real_hits = 13'h0; // @[package.scala:45:27] wire [12:0] pma_checker__stage1_bypass_T = 13'h0; // @[TLB.scala:517:27] wire [12:0] pma_checker_stage1_bypass = 13'h0; // @[TLB.scala:517:61] wire [12:0] pma_checker__r_array_T_2 = 13'h0; // @[TLB.scala:520:74] wire [12:0] pma_checker__hr_array_T_2 = 13'h0; // @[TLB.scala:524:60] wire [12:0] pma_checker__gpa_hits_T = 13'h0; // @[TLB.scala:607:30] wire [12:0] pma_checker__tlb_hit_T = 13'h0; // @[TLB.scala:611:28] wire [12:0] pma_checker__stage1_bypass_T_2 = 13'h1FFF; // @[TLB.scala:517:68] wire [12:0] pma_checker__stage1_bypass_T_4 = 13'h1FFF; // @[TLB.scala:517:95] wire [12:0] pma_checker_stage2_bypass = 13'h1FFF; // @[TLB.scala:523:27] wire [12:0] pma_checker__hr_array_T_4 = 13'h1FFF; // @[TLB.scala:524:111] wire [12:0] pma_checker__hw_array_T_1 = 13'h1FFF; // @[TLB.scala:525:55] wire [12:0] pma_checker__hx_array_T_1 = 13'h1FFF; // @[TLB.scala:526:55] wire [12:0] pma_checker__gpa_hits_hit_mask_T_4 = 13'h1FFF; // @[TLB.scala:606:88] wire [12:0] pma_checker_gpa_hits_hit_mask = 13'h1FFF; // @[TLB.scala:606:82] wire [12:0] pma_checker__gpa_hits_T_1 = 13'h1FFF; // @[TLB.scala:607:16] wire [12:0] pma_checker_gpa_hits = 13'h1FFF; // @[TLB.scala:607:14] wire [13:0] pma_checker_hr_array = 14'h3FFF; // @[TLB.scala:524:21] wire [13:0] pma_checker_hw_array = 14'h3FFF; // @[TLB.scala:525:21] wire [13:0] pma_checker_hx_array = 14'h3FFF; // @[TLB.scala:526:21] wire [13:0] pma_checker__ae_array_T_1 = 14'h3FFF; // @[TLB.scala:583:19] wire [13:0] pma_checker__must_alloc_array_T_8 = 14'h3FFF; // @[TLB.scala:596:19] wire [13:0] pma_checker__gf_ld_array_T_1 = 14'h3FFF; // @[TLB.scala:600:50] wire [30:0] pma_checker_special_entry_data_0_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_superpage_entries_0_data_0_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_superpage_entries_1_data_0_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_superpage_entries_2_data_0_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_superpage_entries_3_data_0_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_sectored_entries_0_0_data_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_sectored_entries_0_1_data_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_sectored_entries_0_2_data_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_sectored_entries_0_3_data_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_sectored_entries_0_4_data_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_sectored_entries_0_5_data_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_sectored_entries_0_6_data_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_sectored_entries_0_7_data_hi = 31'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_special_entry_data_0_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_superpage_entries_0_data_0_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_superpage_entries_1_data_0_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_superpage_entries_2_data_0_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_superpage_entries_3_data_0_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_sectored_entries_0_0_data_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_sectored_entries_0_1_data_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_sectored_entries_0_2_data_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_sectored_entries_0_3_data_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_sectored_entries_0_4_data_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_sectored_entries_0_5_data_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_sectored_entries_0_6_data_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_sectored_entries_0_7_data_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_special_entry_data_0_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_superpage_entries_0_data_0_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_superpage_entries_1_data_0_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_superpage_entries_2_data_0_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_superpage_entries_3_data_0_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_sectored_entries_0_0_data_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_sectored_entries_0_1_data_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_sectored_entries_0_2_data_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_sectored_entries_0_3_data_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_sectored_entries_0_4_data_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_sectored_entries_0_5_data_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_sectored_entries_0_6_data_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_sectored_entries_0_7_data_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [13:0] pma_checker_hits = 14'h2000; // @[TLB.scala:442:17] wire [41:0] pma_checker__mpu_ppn_WIRE_1 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_1 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_3 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_5 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_7 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_9 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_11 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_13 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_15 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_17 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_19 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_21 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_23 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_25 = 42'h0; // @[TLB.scala:170:77] wire hartIdSinkNodeOptIn = auto_hart_id_sink_in_0; // @[DCache.scala:101:7] wire nodeOut_a_ready = auto_out_a_ready_0; // @[DCache.scala:101:7] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[DCache.scala:101:7] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[DCache.scala:101:7] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[DCache.scala:101:7] wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[DCache.scala:101:7] wire nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[DCache.scala:101:7] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[DCache.scala:101:7] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[DCache.scala:101:7] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[DCache.scala:101:7] wire metaArb_io_in_7_valid = io_cpu_req_valid_0; // @[DCache.scala:101:7, :135:28] wire [33:0] metaArb_io_in_7_bits_addr = io_cpu_req_bits_addr_0; // @[DCache.scala:101:7, :135:28] wire [6:0] s0_req_tag = io_cpu_req_bits_tag_0; // @[DCache.scala:101:7, :192:24] wire [4:0] s0_req_cmd = io_cpu_req_bits_cmd_0; // @[DCache.scala:101:7, :192:24] wire [1:0] s0_req_size = io_cpu_req_bits_size_0; // @[DCache.scala:101:7, :192:24] wire s0_req_signed = io_cpu_req_bits_signed_0; // @[DCache.scala:101:7, :192:24] wire [1:0] s0_req_dprv = io_cpu_req_bits_dprv_0; // @[DCache.scala:101:7, :192:24] wire s0_req_dv = io_cpu_req_bits_dv_0; // @[DCache.scala:101:7, :192:24] wire s0_req_no_resp = io_cpu_req_bits_no_resp_0; // @[DCache.scala:101:7, :192:24] wire s0_req_no_xcpt = io_cpu_req_bits_no_xcpt_0; // @[DCache.scala:101:7, :192:24] wire _io_cpu_s2_nack_T_5; // @[DCache.scala:445:86] wire _io_cpu_s2_nack_cause_raw_T_3; // @[DCache.scala:574:54] wire _io_cpu_s2_uncached_T_1; // @[DCache.scala:920:37] wire _io_cpu_resp_valid_T_2; // @[DCache.scala:949:70] wire [63:0] _io_cpu_resp_bits_data_T_24; // @[DCache.scala:974:41] wire s2_read; // @[Consts.scala:89:68] wire [63:0] _io_cpu_resp_bits_data_word_bypass_T_7; // @[AMOALU.scala:45:16] wire [63:0] s2_data_word; // @[DCache.scala:970:80] wire _io_cpu_replay_next_T_3; // @[DCache.scala:950:62] wire _io_cpu_s2_xcpt_T_ma_ld; // @[DCache.scala:933:24] wire _io_cpu_s2_xcpt_T_ma_st; // @[DCache.scala:933:24] wire _io_cpu_s2_xcpt_T_pf_ld; // @[DCache.scala:933:24] wire _io_cpu_s2_xcpt_T_pf_st; // @[DCache.scala:933:24] wire _io_cpu_s2_xcpt_T_ae_ld; // @[DCache.scala:933:24] wire _io_cpu_s2_xcpt_T_ae_st; // @[DCache.scala:933:24] wire _io_cpu_ordered_T_8; // @[DCache.scala:929:21] wire _io_cpu_store_pending_T_25; // @[DCache.scala:930:70] wire io_cpu_perf_acquire_done; // @[Edges.scala:233:22] wire _io_cpu_perf_grant_T; // @[DCache.scala:1078:39] wire _io_cpu_perf_blocked_T_1; // @[DCache.scala:1106:23] wire _io_cpu_perf_canAcceptStoreThenLoad_T_10; // @[DCache.scala:1088:41] wire _io_cpu_perf_canAcceptStoreThenRMW_T_1; // @[DCache.scala:1091:75] wire _io_cpu_perf_canAcceptLoadThenLoad_T_61; // @[DCache.scala:1092:40] wire _io_cpu_perf_storeBufferEmptyAfterLoad_T_7; // @[DCache.scala:1080:44] wire _io_cpu_perf_storeBufferEmptyAfterStore_T_10; // @[DCache.scala:1084:45] wire _io_errors_bus_valid_T_2; // @[DCache.scala:1129:42] wire [2:0] auto_out_a_bits_opcode_0; // @[DCache.scala:101:7] wire [2:0] auto_out_a_bits_param_0; // @[DCache.scala:101:7] wire [3:0] auto_out_a_bits_size_0; // @[DCache.scala:101:7] wire [31:0] auto_out_a_bits_address_0; // @[DCache.scala:101:7] wire [7:0] auto_out_a_bits_mask_0; // @[DCache.scala:101:7] wire [63:0] auto_out_a_bits_data_0; // @[DCache.scala:101:7] wire auto_out_a_valid_0; // @[DCache.scala:101:7] wire auto_out_d_ready_0; // @[DCache.scala:101:7] wire io_cpu_req_ready_0; // @[DCache.scala:101:7] wire [33:0] io_cpu_resp_bits_addr_0; // @[DCache.scala:101:7] wire [6:0] io_cpu_resp_bits_tag_0; // @[DCache.scala:101:7] wire [4:0] io_cpu_resp_bits_cmd_0; // @[DCache.scala:101:7] wire [1:0] io_cpu_resp_bits_size_0; // @[DCache.scala:101:7] wire io_cpu_resp_bits_signed_0; // @[DCache.scala:101:7] wire [1:0] io_cpu_resp_bits_dprv_0; // @[DCache.scala:101:7] wire io_cpu_resp_bits_dv_0; // @[DCache.scala:101:7] wire [63:0] io_cpu_resp_bits_data_0; // @[DCache.scala:101:7] wire [7:0] io_cpu_resp_bits_mask_0; // @[DCache.scala:101:7] wire io_cpu_resp_bits_replay_0; // @[DCache.scala:101:7] wire io_cpu_resp_bits_has_data_0; // @[DCache.scala:101:7] wire [63:0] io_cpu_resp_bits_data_word_bypass_0; // @[DCache.scala:101:7] wire [63:0] io_cpu_resp_bits_data_raw_0; // @[DCache.scala:101:7] wire [63:0] io_cpu_resp_bits_store_data_0; // @[DCache.scala:101:7] wire io_cpu_resp_valid_0; // @[DCache.scala:101:7] wire io_cpu_s2_xcpt_ma_ld_0; // @[DCache.scala:101:7] wire io_cpu_s2_xcpt_ma_st_0; // @[DCache.scala:101:7] wire io_cpu_s2_xcpt_pf_ld_0; // @[DCache.scala:101:7] wire io_cpu_s2_xcpt_pf_st_0; // @[DCache.scala:101:7] wire io_cpu_s2_xcpt_ae_ld_0; // @[DCache.scala:101:7] wire io_cpu_s2_xcpt_ae_st_0; // @[DCache.scala:101:7] wire io_cpu_perf_acquire_0; // @[DCache.scala:101:7] wire io_cpu_perf_grant_0; // @[DCache.scala:101:7] wire io_cpu_perf_blocked_0; // @[DCache.scala:101:7] wire io_cpu_perf_canAcceptStoreThenLoad_0; // @[DCache.scala:101:7] wire io_cpu_perf_canAcceptStoreThenRMW_0; // @[DCache.scala:101:7] wire io_cpu_perf_canAcceptLoadThenLoad_0; // @[DCache.scala:101:7] wire io_cpu_perf_storeBufferEmptyAfterLoad_0; // @[DCache.scala:101:7] wire io_cpu_perf_storeBufferEmptyAfterStore_0; // @[DCache.scala:101:7] wire io_cpu_s2_nack_0; // @[DCache.scala:101:7] wire io_cpu_s2_nack_cause_raw_0; // @[DCache.scala:101:7] wire io_cpu_s2_uncached_0; // @[DCache.scala:101:7] wire [31:0] io_cpu_s2_paddr_0; // @[DCache.scala:101:7] wire io_cpu_replay_next_0; // @[DCache.scala:101:7] wire [33:0] io_cpu_s2_gpa_0; // @[DCache.scala:101:7] wire io_cpu_ordered_0; // @[DCache.scala:101:7] wire io_cpu_store_pending_0; // @[DCache.scala:101:7] wire [20:0] io_ptw_req_bits_bits_addr_0; // @[DCache.scala:101:7] wire io_ptw_req_bits_bits_need_gpa_0; // @[DCache.scala:101:7] wire io_ptw_req_bits_bits_vstage1_0; // @[DCache.scala:101:7] wire io_ptw_req_bits_bits_stage2_0; // @[DCache.scala:101:7] wire io_errors_bus_valid; // @[DCache.scala:101:7] wire [31:0] io_errors_bus_bits; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_pf_ld; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_pf_st; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_pf_inst; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_ae_ld; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_ae_st; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_ae_inst; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_ma_ld; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_ma_st; // @[DCache.scala:101:7] wire [31:0] io_tlb_port_s1_resp_paddr; // @[DCache.scala:101:7] wire [33:0] io_tlb_port_s1_resp_gpa; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_cacheable; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_must_alloc; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_prefetchable; // @[DCache.scala:101:7] wire [1:0] io_tlb_port_s1_resp_size; // @[DCache.scala:101:7] wire [4:0] io_tlb_port_s1_resp_cmd; // @[DCache.scala:101:7] wire nodeOut_a_deq_ready = nodeOut_a_ready; // @[Decoupled.scala:356:21] wire nodeOut_a_deq_valid; // @[Decoupled.scala:356:21] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[DCache.scala:101:7] wire [2:0] nodeOut_a_deq_bits_opcode; // @[Decoupled.scala:356:21] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[DCache.scala:101:7] wire [2:0] nodeOut_a_deq_bits_param; // @[Decoupled.scala:356:21] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[DCache.scala:101:7] wire [3:0] nodeOut_a_deq_bits_size; // @[Decoupled.scala:356:21] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[DCache.scala:101:7] wire [31:0] nodeOut_a_deq_bits_address; // @[Decoupled.scala:356:21] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[DCache.scala:101:7] wire [7:0] nodeOut_a_deq_bits_mask; // @[Decoupled.scala:356:21] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[DCache.scala:101:7] wire [63:0] nodeOut_a_deq_bits_data; // @[Decoupled.scala:356:21] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[DCache.scala:101:7] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[DCache.scala:101:7] wire e_sink = nodeOut_d_bits_sink; // @[Edges.scala:451:17] wire [63:0] s1_uncached_data_word = nodeOut_d_bits_data; // @[package.scala:211:50] wire [1:0] pma_checker_io_resp_size = pma_checker_io_req_bits_size; // @[DCache.scala:120:32] wire [4:0] pma_checker_io_resp_cmd = pma_checker_io_req_bits_cmd; // @[DCache.scala:120:32] wire [31:0] pma_checker__io_resp_paddr_T_1; // @[TLB.scala:652:23] wire [33:0] pma_checker__io_resp_gpa_T; // @[TLB.scala:659:8] wire pma_checker__io_resp_pf_ld_T_3; // @[TLB.scala:633:41] wire pma_checker__io_resp_pf_st_T_3; // @[TLB.scala:634:48] wire pma_checker__io_resp_pf_inst_T_2; // @[TLB.scala:635:29] wire pma_checker__io_resp_ae_ld_T_1; // @[TLB.scala:641:41] wire pma_checker__io_resp_ae_st_T_1; // @[TLB.scala:642:41] wire pma_checker__io_resp_ae_inst_T_2; // @[TLB.scala:643:41] wire pma_checker__io_resp_ma_ld_T; // @[TLB.scala:645:31] wire pma_checker__io_resp_ma_st_T; // @[TLB.scala:646:31] wire pma_checker__io_resp_cacheable_T_1; // @[TLB.scala:648:41] wire pma_checker__io_resp_must_alloc_T_1; // @[TLB.scala:649:51] wire pma_checker__io_resp_prefetchable_T_2; // @[TLB.scala:650:59] wire [33:0] pma_checker_io_req_bits_vaddr; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_req_bits_prv; // @[DCache.scala:120:32] wire pma_checker_io_req_bits_v; // @[DCache.scala:120:32] wire pma_checker_io_resp_pf_ld; // @[DCache.scala:120:32] wire pma_checker_io_resp_pf_st; // @[DCache.scala:120:32] wire pma_checker_io_resp_pf_inst; // @[DCache.scala:120:32] wire pma_checker_io_resp_ae_ld; // @[DCache.scala:120:32] wire pma_checker_io_resp_ae_st; // @[DCache.scala:120:32] wire pma_checker_io_resp_ae_inst; // @[DCache.scala:120:32] wire pma_checker_io_resp_ma_ld; // @[DCache.scala:120:32] wire pma_checker_io_resp_ma_st; // @[DCache.scala:120:32] wire [31:0] pma_checker_io_resp_paddr; // @[DCache.scala:120:32] wire [33:0] pma_checker_io_resp_gpa; // @[DCache.scala:120:32] wire pma_checker_io_resp_cacheable; // @[DCache.scala:120:32] wire pma_checker_io_resp_must_alloc; // @[DCache.scala:120:32] wire pma_checker_io_resp_prefetchable; // @[DCache.scala:120:32] wire [20:0] pma_checker_vpn = pma_checker_io_req_bits_vaddr[32:12]; // @[TLB.scala:335:30] wire [20:0] pma_checker__sector_hits_T_3 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [20:0] pma_checker__sector_hits_T_11 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [20:0] pma_checker__sector_hits_T_19 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [20:0] pma_checker__sector_hits_T_27 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [20:0] pma_checker__sector_hits_T_35 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [20:0] pma_checker__sector_hits_T_43 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [20:0] pma_checker__sector_hits_T_51 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [20:0] pma_checker__sector_hits_T_59 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [20:0] pma_checker__superpage_hits_T = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [20:0] pma_checker__superpage_hits_T_5 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [20:0] pma_checker__superpage_hits_T_10 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [20:0] pma_checker__superpage_hits_T_15 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [20:0] pma_checker__hitsVec_T = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [20:0] pma_checker__hitsVec_T_6 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [20:0] pma_checker__hitsVec_T_12 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [20:0] pma_checker__hitsVec_T_18 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [20:0] pma_checker__hitsVec_T_24 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [20:0] pma_checker__hitsVec_T_30 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [20:0] pma_checker__hitsVec_T_36 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [20:0] pma_checker__hitsVec_T_42 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [20:0] pma_checker__hitsVec_T_48 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [20:0] pma_checker__hitsVec_T_54 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [20:0] pma_checker__hitsVec_T_60 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [20:0] pma_checker__hitsVec_T_66 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [20:0] pma_checker__hitsVec_T_72 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire pma_checker_priv_s = pma_checker_io_req_bits_prv[0]; // @[TLB.scala:370:20] wire pma_checker_priv_uses_vm = ~(pma_checker_io_req_bits_prv[1]); // @[TLB.scala:372:27] wire [19:0] pma_checker__mpu_ppn_T_23; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_22; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_21; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_20; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_19; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_18; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_17; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_16; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_15; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_14; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_13; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_12; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_11; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_10; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_9; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_8; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_7; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_6; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_5; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_4; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_3; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_2; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_1; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_1 = pma_checker__mpu_ppn_WIRE_1[0]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_fragmented_superpage = pma_checker__mpu_ppn_T_1; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_2 = pma_checker__mpu_ppn_WIRE_1[1]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_c = pma_checker__mpu_ppn_T_2; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_3 = pma_checker__mpu_ppn_WIRE_1[2]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_eff = pma_checker__mpu_ppn_T_3; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_4 = pma_checker__mpu_ppn_WIRE_1[3]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_paa = pma_checker__mpu_ppn_T_4; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_5 = pma_checker__mpu_ppn_WIRE_1[4]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_pal = pma_checker__mpu_ppn_T_5; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_6 = pma_checker__mpu_ppn_WIRE_1[5]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_ppp = pma_checker__mpu_ppn_T_6; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_7 = pma_checker__mpu_ppn_WIRE_1[6]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_pr = pma_checker__mpu_ppn_T_7; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_8 = pma_checker__mpu_ppn_WIRE_1[7]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_px = pma_checker__mpu_ppn_T_8; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_9 = pma_checker__mpu_ppn_WIRE_1[8]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_pw = pma_checker__mpu_ppn_T_9; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_10 = pma_checker__mpu_ppn_WIRE_1[9]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_hr = pma_checker__mpu_ppn_T_10; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_11 = pma_checker__mpu_ppn_WIRE_1[10]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_hx = pma_checker__mpu_ppn_T_11; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_12 = pma_checker__mpu_ppn_WIRE_1[11]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_hw = pma_checker__mpu_ppn_T_12; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_13 = pma_checker__mpu_ppn_WIRE_1[12]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_sr = pma_checker__mpu_ppn_T_13; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_14 = pma_checker__mpu_ppn_WIRE_1[13]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_sx = pma_checker__mpu_ppn_T_14; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_15 = pma_checker__mpu_ppn_WIRE_1[14]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_sw = pma_checker__mpu_ppn_T_15; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_16 = pma_checker__mpu_ppn_WIRE_1[15]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_gf = pma_checker__mpu_ppn_T_16; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_17 = pma_checker__mpu_ppn_WIRE_1[16]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_pf = pma_checker__mpu_ppn_T_17; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_18 = pma_checker__mpu_ppn_WIRE_1[17]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_ae_stage2 = pma_checker__mpu_ppn_T_18; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_19 = pma_checker__mpu_ppn_WIRE_1[18]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_ae_final = pma_checker__mpu_ppn_T_19; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_20 = pma_checker__mpu_ppn_WIRE_1[19]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_ae_ptw = pma_checker__mpu_ppn_T_20; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_21 = pma_checker__mpu_ppn_WIRE_1[20]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_g = pma_checker__mpu_ppn_T_21; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_22 = pma_checker__mpu_ppn_WIRE_1[21]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_u = pma_checker__mpu_ppn_T_22; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_23 = pma_checker__mpu_ppn_WIRE_1[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__mpu_ppn_WIRE_ppn = pma_checker__mpu_ppn_T_23; // @[TLB.scala:170:77] wire [21:0] pma_checker__mpu_ppn_T_24 = pma_checker_io_req_bits_vaddr[33:12]; // @[TLB.scala:413:146] wire [21:0] pma_checker__mpu_ppn_T_25 = pma_checker__mpu_ppn_T_24; // @[TLB.scala:413:{20,146}] wire [21:0] pma_checker_mpu_ppn = pma_checker__mpu_ppn_T_25; // @[TLB.scala:412:20, :413:20] wire [11:0] pma_checker__mpu_physaddr_T = pma_checker_io_req_bits_vaddr[11:0]; // @[TLB.scala:414:52] wire [11:0] pma_checker__io_resp_paddr_T = pma_checker_io_req_bits_vaddr[11:0]; // @[TLB.scala:414:52, :652:46] wire [11:0] pma_checker__io_resp_gpa_offset_T_1 = pma_checker_io_req_bits_vaddr[11:0]; // @[TLB.scala:414:52, :658:82] wire [33:0] pma_checker_mpu_physaddr = {pma_checker_mpu_ppn, pma_checker__mpu_physaddr_T}; // @[TLB.scala:412:20, :414:{25,52}] wire [33:0] pma_checker__homogeneous_T = pma_checker_mpu_physaddr; // @[TLB.scala:414:25] wire [33:0] pma_checker__homogeneous_T_55 = pma_checker_mpu_physaddr; // @[TLB.scala:414:25] wire [33:0] pma_checker__deny_access_to_debug_T_1 = pma_checker_mpu_physaddr; // @[TLB.scala:414:25] wire [2:0] pma_checker__mpu_priv_T_2 = {1'h0, pma_checker_io_req_bits_prv}; // @[TLB.scala:415:103] wire [2:0] pma_checker_mpu_priv = pma_checker__mpu_priv_T_2; // @[TLB.scala:415:{27,103}] wire [34:0] pma_checker__homogeneous_T_1 = {1'h0, pma_checker__homogeneous_T}; // @[Parameters.scala:137:{31,41}] wire [34:0] pma_checker__homogeneous_T_2 = pma_checker__homogeneous_T_1 & 35'h7FFFFE000; // @[Parameters.scala:137:{41,46}] wire [34:0] pma_checker__homogeneous_T_3 = pma_checker__homogeneous_T_2; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_4 = pma_checker__homogeneous_T_3 == 35'h0; // @[Parameters.scala:137:{46,59}] wire pma_checker__homogeneous_T_40 = pma_checker__homogeneous_T_4; // @[TLBPermissions.scala:101:65] wire [33:0] _GEN = {pma_checker_mpu_physaddr[33:14], pma_checker_mpu_physaddr[13:0] ^ 14'h3000}; // @[TLB.scala:414:25] wire [33:0] pma_checker__homogeneous_T_5; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_5 = _GEN; // @[Parameters.scala:137:31] wire [33:0] pma_checker__homogeneous_T_60; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_60 = _GEN; // @[Parameters.scala:137:31] wire [34:0] pma_checker__homogeneous_T_6 = {1'h0, pma_checker__homogeneous_T_5}; // @[Parameters.scala:137:{31,41}] wire [34:0] pma_checker__homogeneous_T_7 = pma_checker__homogeneous_T_6 & 35'h7FFFFF000; // @[Parameters.scala:137:{41,46}] wire [34:0] pma_checker__homogeneous_T_8 = pma_checker__homogeneous_T_7; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_9 = pma_checker__homogeneous_T_8 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [33:0] _GEN_0 = {pma_checker_mpu_physaddr[33:17], pma_checker_mpu_physaddr[16:0] ^ 17'h10000}; // @[TLB.scala:414:25] wire [33:0] pma_checker__homogeneous_T_10; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_10 = _GEN_0; // @[Parameters.scala:137:31] wire [33:0] pma_checker__homogeneous_T_48; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_48 = _GEN_0; // @[Parameters.scala:137:31] wire [33:0] pma_checker__homogeneous_T_65; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_65 = _GEN_0; // @[Parameters.scala:137:31] wire [33:0] pma_checker__homogeneous_T_79; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_79 = _GEN_0; // @[Parameters.scala:137:31] wire [33:0] pma_checker__homogeneous_T_86; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_86 = _GEN_0; // @[Parameters.scala:137:31] wire [34:0] pma_checker__homogeneous_T_11 = {1'h0, pma_checker__homogeneous_T_10}; // @[Parameters.scala:137:{31,41}] wire [34:0] pma_checker__homogeneous_T_12 = pma_checker__homogeneous_T_11 & 35'h7FFFF0000; // @[Parameters.scala:137:{41,46}] wire [34:0] pma_checker__homogeneous_T_13 = pma_checker__homogeneous_T_12; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_14 = pma_checker__homogeneous_T_13 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [33:0] pma_checker__homogeneous_T_15 = {pma_checker_mpu_physaddr[33:21], pma_checker_mpu_physaddr[20:0] ^ 21'h100000}; // @[TLB.scala:414:25] wire [34:0] pma_checker__homogeneous_T_16 = {1'h0, pma_checker__homogeneous_T_15}; // @[Parameters.scala:137:{31,41}] wire [34:0] pma_checker__homogeneous_T_17 = pma_checker__homogeneous_T_16 & 35'h7FFFEF000; // @[Parameters.scala:137:{41,46}] wire [34:0] pma_checker__homogeneous_T_18 = pma_checker__homogeneous_T_17; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_19 = pma_checker__homogeneous_T_18 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [33:0] pma_checker__homogeneous_T_20 = {pma_checker_mpu_physaddr[33:26], pma_checker_mpu_physaddr[25:0] ^ 26'h2000000}; // @[TLB.scala:414:25] wire [34:0] pma_checker__homogeneous_T_21 = {1'h0, pma_checker__homogeneous_T_20}; // @[Parameters.scala:137:{31,41}] wire [34:0] pma_checker__homogeneous_T_22 = pma_checker__homogeneous_T_21 & 35'h7FFFF0000; // @[Parameters.scala:137:{41,46}] wire [34:0] pma_checker__homogeneous_T_23 = pma_checker__homogeneous_T_22; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_24 = pma_checker__homogeneous_T_23 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [33:0] pma_checker__homogeneous_T_25 = {pma_checker_mpu_physaddr[33:28], pma_checker_mpu_physaddr[27:0] ^ 28'hC000000}; // @[TLB.scala:414:25] wire [34:0] pma_checker__homogeneous_T_26 = {1'h0, pma_checker__homogeneous_T_25}; // @[Parameters.scala:137:{31,41}] wire [34:0] pma_checker__homogeneous_T_27 = pma_checker__homogeneous_T_26 & 35'h7FC000000; // @[Parameters.scala:137:{41,46}] wire [34:0] pma_checker__homogeneous_T_28 = pma_checker__homogeneous_T_27; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_29 = pma_checker__homogeneous_T_28 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [33:0] pma_checker__homogeneous_T_30 = {pma_checker_mpu_physaddr[33:29], pma_checker_mpu_physaddr[28:0] ^ 29'h10020000}; // @[TLB.scala:414:25] wire [34:0] pma_checker__homogeneous_T_31 = {1'h0, pma_checker__homogeneous_T_30}; // @[Parameters.scala:137:{31,41}] wire [34:0] pma_checker__homogeneous_T_32 = pma_checker__homogeneous_T_31 & 35'h7FFFFF000; // @[Parameters.scala:137:{41,46}] wire [34:0] pma_checker__homogeneous_T_33 = pma_checker__homogeneous_T_32; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_34 = pma_checker__homogeneous_T_33 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [33:0] _GEN_1 = {pma_checker_mpu_physaddr[33:32], pma_checker_mpu_physaddr[31:0] ^ 32'h80000000}; // @[TLB.scala:414:25, :417:15] wire [33:0] pma_checker__homogeneous_T_35; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_35 = _GEN_1; // @[Parameters.scala:137:31] wire [33:0] pma_checker__homogeneous_T_70; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_70 = _GEN_1; // @[Parameters.scala:137:31] wire [34:0] pma_checker__homogeneous_T_36 = {1'h0, pma_checker__homogeneous_T_35}; // @[Parameters.scala:137:{31,41}] wire [34:0] pma_checker__homogeneous_T_37 = pma_checker__homogeneous_T_36 & 35'h7FFFFC000; // @[Parameters.scala:137:{41,46}] wire [34:0] pma_checker__homogeneous_T_38 = pma_checker__homogeneous_T_37; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_39 = pma_checker__homogeneous_T_38 == 35'h0; // @[Parameters.scala:137:{46,59}] wire pma_checker__homogeneous_T_41 = pma_checker__homogeneous_T_40 | pma_checker__homogeneous_T_9; // @[TLBPermissions.scala:101:65] wire pma_checker__homogeneous_T_42 = pma_checker__homogeneous_T_41 | pma_checker__homogeneous_T_14; // @[TLBPermissions.scala:101:65] wire pma_checker__homogeneous_T_43 = pma_checker__homogeneous_T_42 | pma_checker__homogeneous_T_19; // @[TLBPermissions.scala:101:65] wire pma_checker__homogeneous_T_44 = pma_checker__homogeneous_T_43 | pma_checker__homogeneous_T_24; // @[TLBPermissions.scala:101:65] wire pma_checker__homogeneous_T_45 = pma_checker__homogeneous_T_44 | pma_checker__homogeneous_T_29; // @[TLBPermissions.scala:101:65] wire pma_checker__homogeneous_T_46 = pma_checker__homogeneous_T_45 | pma_checker__homogeneous_T_34; // @[TLBPermissions.scala:101:65] wire pma_checker_homogeneous = pma_checker__homogeneous_T_46 | pma_checker__homogeneous_T_39; // @[TLBPermissions.scala:101:65] wire [34:0] pma_checker__homogeneous_T_49 = {1'h0, pma_checker__homogeneous_T_48}; // @[Parameters.scala:137:{31,41}] wire [34:0] pma_checker__homogeneous_T_50 = pma_checker__homogeneous_T_49 & 35'h98110000; // @[Parameters.scala:137:{41,46}] wire [34:0] pma_checker__homogeneous_T_51 = pma_checker__homogeneous_T_50; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_52 = pma_checker__homogeneous_T_51 == 35'h0; // @[Parameters.scala:137:{46,59}] wire pma_checker__homogeneous_T_53 = pma_checker__homogeneous_T_52; // @[TLBPermissions.scala:87:66] wire pma_checker__homogeneous_T_54 = ~pma_checker__homogeneous_T_53; // @[TLBPermissions.scala:87:{22,66}] wire [34:0] pma_checker__homogeneous_T_56 = {1'h0, pma_checker__homogeneous_T_55}; // @[Parameters.scala:137:{31,41}] wire [34:0] pma_checker__homogeneous_T_57 = pma_checker__homogeneous_T_56 & 35'h9A113000; // @[Parameters.scala:137:{41,46}] wire [34:0] pma_checker__homogeneous_T_58 = pma_checker__homogeneous_T_57; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_59 = pma_checker__homogeneous_T_58 == 35'h0; // @[Parameters.scala:137:{46,59}] wire pma_checker__homogeneous_T_75 = pma_checker__homogeneous_T_59; // @[TLBPermissions.scala:85:66] wire [34:0] pma_checker__homogeneous_T_61 = {1'h0, pma_checker__homogeneous_T_60}; // @[Parameters.scala:137:{31,41}] wire [34:0] pma_checker__homogeneous_T_62 = pma_checker__homogeneous_T_61 & 35'h9A113000; // @[Parameters.scala:137:{41,46}] wire [34:0] pma_checker__homogeneous_T_63 = pma_checker__homogeneous_T_62; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_64 = pma_checker__homogeneous_T_63 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] pma_checker__homogeneous_T_66 = {1'h0, pma_checker__homogeneous_T_65}; // @[Parameters.scala:137:{31,41}] wire [34:0] pma_checker__homogeneous_T_67 = pma_checker__homogeneous_T_66 & 35'h9A110000; // @[Parameters.scala:137:{41,46}] wire [34:0] pma_checker__homogeneous_T_68 = pma_checker__homogeneous_T_67; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_69 = pma_checker__homogeneous_T_68 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] pma_checker__homogeneous_T_71 = {1'h0, pma_checker__homogeneous_T_70}; // @[Parameters.scala:137:{31,41}] wire [34:0] pma_checker__homogeneous_T_72 = pma_checker__homogeneous_T_71 & 35'h9A110000; // @[Parameters.scala:137:{41,46}] wire [34:0] pma_checker__homogeneous_T_73 = pma_checker__homogeneous_T_72; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_74 = pma_checker__homogeneous_T_73 == 35'h0; // @[Parameters.scala:137:{46,59}] wire pma_checker__homogeneous_T_76 = pma_checker__homogeneous_T_75 | pma_checker__homogeneous_T_64; // @[TLBPermissions.scala:85:66] wire pma_checker__homogeneous_T_77 = pma_checker__homogeneous_T_76 | pma_checker__homogeneous_T_69; // @[TLBPermissions.scala:85:66] wire pma_checker__homogeneous_T_78 = pma_checker__homogeneous_T_77 | pma_checker__homogeneous_T_74; // @[TLBPermissions.scala:85:66] wire [34:0] pma_checker__homogeneous_T_80 = {1'h0, pma_checker__homogeneous_T_79}; // @[Parameters.scala:137:{31,41}] wire [34:0] pma_checker__homogeneous_T_81 = pma_checker__homogeneous_T_80 & 35'h98110000; // @[Parameters.scala:137:{41,46}] wire [34:0] pma_checker__homogeneous_T_82 = pma_checker__homogeneous_T_81; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_83 = pma_checker__homogeneous_T_82 == 35'h0; // @[Parameters.scala:137:{46,59}] wire pma_checker__homogeneous_T_84 = pma_checker__homogeneous_T_83; // @[TLBPermissions.scala:87:66] wire pma_checker__homogeneous_T_85 = ~pma_checker__homogeneous_T_84; // @[TLBPermissions.scala:87:{22,66}] wire [34:0] pma_checker__homogeneous_T_87 = {1'h0, pma_checker__homogeneous_T_86}; // @[Parameters.scala:137:{31,41}] wire [34:0] pma_checker__homogeneous_T_88 = pma_checker__homogeneous_T_87 & 35'h98110000; // @[Parameters.scala:137:{41,46}] wire [34:0] pma_checker__homogeneous_T_89 = pma_checker__homogeneous_T_88; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_90 = pma_checker__homogeneous_T_89 == 35'h0; // @[Parameters.scala:137:{46,59}] wire pma_checker__homogeneous_T_91 = pma_checker__homogeneous_T_90; // @[TLBPermissions.scala:87:66] wire pma_checker__homogeneous_T_92 = ~pma_checker__homogeneous_T_91; // @[TLBPermissions.scala:87:{22,66}] wire pma_checker__deny_access_to_debug_T = ~(pma_checker_mpu_priv[2]); // @[TLB.scala:415:27, :428:39] wire [34:0] pma_checker__deny_access_to_debug_T_2 = {1'h0, pma_checker__deny_access_to_debug_T_1}; // @[Parameters.scala:137:{31,41}] wire [34:0] pma_checker__deny_access_to_debug_T_3 = pma_checker__deny_access_to_debug_T_2 & 35'h7FFFFF000; // @[Parameters.scala:137:{41,46}] wire [34:0] pma_checker__deny_access_to_debug_T_4 = pma_checker__deny_access_to_debug_T_3; // @[Parameters.scala:137:46] wire pma_checker__deny_access_to_debug_T_5 = pma_checker__deny_access_to_debug_T_4 == 35'h0; // @[Parameters.scala:137:{46,59}] wire pma_checker_deny_access_to_debug = pma_checker__deny_access_to_debug_T & pma_checker__deny_access_to_debug_T_5; // @[TLB.scala:428:{39,50}] wire pma_checker__prot_r_T = ~pma_checker_deny_access_to_debug; // @[TLB.scala:428:50, :429:33] wire pma_checker__prot_r_T_1 = _pma_checker_pma_io_resp_r & pma_checker__prot_r_T; // @[TLB.scala:422:19, :429:{30,33}] wire pma_checker_prot_r = pma_checker__prot_r_T_1 & _pma_checker_pmp_io_r; // @[TLB.scala:416:19, :429:{30,55}] wire pma_checker_newEntry_pr = pma_checker_prot_r; // @[TLB.scala:429:55, :449:24] wire pma_checker__prot_w_T = ~pma_checker_deny_access_to_debug; // @[TLB.scala:428:50, :429:33, :430:33] wire pma_checker__prot_w_T_1 = _pma_checker_pma_io_resp_w & pma_checker__prot_w_T; // @[TLB.scala:422:19, :430:{30,33}] wire pma_checker_prot_w = pma_checker__prot_w_T_1 & _pma_checker_pmp_io_w; // @[TLB.scala:416:19, :430:{30,55}] wire pma_checker_newEntry_pw = pma_checker_prot_w; // @[TLB.scala:430:55, :449:24] wire pma_checker__prot_x_T = ~pma_checker_deny_access_to_debug; // @[TLB.scala:428:50, :429:33, :434:33] wire pma_checker__prot_x_T_1 = _pma_checker_pma_io_resp_x & pma_checker__prot_x_T; // @[TLB.scala:422:19, :434:{30,33}] wire pma_checker_prot_x = pma_checker__prot_x_T_1 & _pma_checker_pmp_io_x; // @[TLB.scala:416:19, :434:{30,55}] wire pma_checker_newEntry_px = pma_checker_prot_x; // @[TLB.scala:434:55, :449:24] wire pma_checker__sector_hits_T_1 = pma_checker__sector_hits_T; // @[package.scala:81:59] wire pma_checker__sector_hits_T_2 = pma_checker__sector_hits_T_1; // @[package.scala:81:59] wire [18:0] pma_checker__sector_hits_T_4 = pma_checker__sector_hits_T_3[20:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__sector_hits_T_5 = pma_checker__sector_hits_T_4 == 19'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__sector_hits_T_7 = pma_checker__sector_hits_T_5 & pma_checker__sector_hits_T_6; // @[TLB.scala:174:{86,95,105}] wire pma_checker_sector_hits_0 = pma_checker__sector_hits_T_2 & pma_checker__sector_hits_T_7; // @[package.scala:81:59] wire pma_checker__sector_hits_T_9 = pma_checker__sector_hits_T_8; // @[package.scala:81:59] wire pma_checker__sector_hits_T_10 = pma_checker__sector_hits_T_9; // @[package.scala:81:59] wire [18:0] pma_checker__sector_hits_T_12 = pma_checker__sector_hits_T_11[20:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__sector_hits_T_13 = pma_checker__sector_hits_T_12 == 19'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__sector_hits_T_15 = pma_checker__sector_hits_T_13 & pma_checker__sector_hits_T_14; // @[TLB.scala:174:{86,95,105}] wire pma_checker_sector_hits_1 = pma_checker__sector_hits_T_10 & pma_checker__sector_hits_T_15; // @[package.scala:81:59] wire pma_checker__sector_hits_T_17 = pma_checker__sector_hits_T_16; // @[package.scala:81:59] wire pma_checker__sector_hits_T_18 = pma_checker__sector_hits_T_17; // @[package.scala:81:59] wire [18:0] pma_checker__sector_hits_T_20 = pma_checker__sector_hits_T_19[20:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__sector_hits_T_21 = pma_checker__sector_hits_T_20 == 19'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__sector_hits_T_23 = pma_checker__sector_hits_T_21 & pma_checker__sector_hits_T_22; // @[TLB.scala:174:{86,95,105}] wire pma_checker_sector_hits_2 = pma_checker__sector_hits_T_18 & pma_checker__sector_hits_T_23; // @[package.scala:81:59] wire pma_checker__sector_hits_T_25 = pma_checker__sector_hits_T_24; // @[package.scala:81:59] wire pma_checker__sector_hits_T_26 = pma_checker__sector_hits_T_25; // @[package.scala:81:59] wire [18:0] pma_checker__sector_hits_T_28 = pma_checker__sector_hits_T_27[20:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__sector_hits_T_29 = pma_checker__sector_hits_T_28 == 19'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__sector_hits_T_31 = pma_checker__sector_hits_T_29 & pma_checker__sector_hits_T_30; // @[TLB.scala:174:{86,95,105}] wire pma_checker_sector_hits_3 = pma_checker__sector_hits_T_26 & pma_checker__sector_hits_T_31; // @[package.scala:81:59] wire pma_checker__sector_hits_T_33 = pma_checker__sector_hits_T_32; // @[package.scala:81:59] wire pma_checker__sector_hits_T_34 = pma_checker__sector_hits_T_33; // @[package.scala:81:59] wire [18:0] pma_checker__sector_hits_T_36 = pma_checker__sector_hits_T_35[20:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__sector_hits_T_37 = pma_checker__sector_hits_T_36 == 19'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__sector_hits_T_39 = pma_checker__sector_hits_T_37 & pma_checker__sector_hits_T_38; // @[TLB.scala:174:{86,95,105}] wire pma_checker_sector_hits_4 = pma_checker__sector_hits_T_34 & pma_checker__sector_hits_T_39; // @[package.scala:81:59] wire pma_checker__sector_hits_T_41 = pma_checker__sector_hits_T_40; // @[package.scala:81:59] wire pma_checker__sector_hits_T_42 = pma_checker__sector_hits_T_41; // @[package.scala:81:59] wire [18:0] pma_checker__sector_hits_T_44 = pma_checker__sector_hits_T_43[20:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__sector_hits_T_45 = pma_checker__sector_hits_T_44 == 19'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__sector_hits_T_47 = pma_checker__sector_hits_T_45 & pma_checker__sector_hits_T_46; // @[TLB.scala:174:{86,95,105}] wire pma_checker_sector_hits_5 = pma_checker__sector_hits_T_42 & pma_checker__sector_hits_T_47; // @[package.scala:81:59] wire pma_checker__sector_hits_T_49 = pma_checker__sector_hits_T_48; // @[package.scala:81:59] wire pma_checker__sector_hits_T_50 = pma_checker__sector_hits_T_49; // @[package.scala:81:59] wire [18:0] pma_checker__sector_hits_T_52 = pma_checker__sector_hits_T_51[20:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__sector_hits_T_53 = pma_checker__sector_hits_T_52 == 19'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__sector_hits_T_55 = pma_checker__sector_hits_T_53 & pma_checker__sector_hits_T_54; // @[TLB.scala:174:{86,95,105}] wire pma_checker_sector_hits_6 = pma_checker__sector_hits_T_50 & pma_checker__sector_hits_T_55; // @[package.scala:81:59] wire pma_checker__sector_hits_T_57 = pma_checker__sector_hits_T_56; // @[package.scala:81:59] wire pma_checker__sector_hits_T_58 = pma_checker__sector_hits_T_57; // @[package.scala:81:59] wire [18:0] pma_checker__sector_hits_T_60 = pma_checker__sector_hits_T_59[20:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__sector_hits_T_61 = pma_checker__sector_hits_T_60 == 19'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__sector_hits_T_63 = pma_checker__sector_hits_T_61 & pma_checker__sector_hits_T_62; // @[TLB.scala:174:{86,95,105}] wire pma_checker_sector_hits_7 = pma_checker__sector_hits_T_58 & pma_checker__sector_hits_T_63; // @[package.scala:81:59] wire [20:0] pma_checker__superpage_hits_T_1 = pma_checker__superpage_hits_T; // @[TLB.scala:174:{61,68}] wire pma_checker__superpage_hits_T_2 = pma_checker__superpage_hits_T_1 == 21'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__superpage_hits_T_4 = pma_checker__superpage_hits_T_2 & pma_checker__superpage_hits_T_3; // @[TLB.scala:174:{86,95,105}] wire [20:0] pma_checker__superpage_hits_T_6 = pma_checker__superpage_hits_T_5; // @[TLB.scala:174:{61,68}] wire pma_checker__superpage_hits_T_7 = pma_checker__superpage_hits_T_6 == 21'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__superpage_hits_T_9 = pma_checker__superpage_hits_T_7 & pma_checker__superpage_hits_T_8; // @[TLB.scala:174:{86,95,105}] wire [20:0] pma_checker__superpage_hits_T_11 = pma_checker__superpage_hits_T_10; // @[TLB.scala:174:{61,68}] wire pma_checker__superpage_hits_T_12 = pma_checker__superpage_hits_T_11 == 21'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__superpage_hits_T_14 = pma_checker__superpage_hits_T_12 & pma_checker__superpage_hits_T_13; // @[TLB.scala:174:{86,95,105}] wire [20:0] pma_checker__superpage_hits_T_16 = pma_checker__superpage_hits_T_15; // @[TLB.scala:174:{61,68}] wire pma_checker__superpage_hits_T_17 = pma_checker__superpage_hits_T_16 == 21'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__superpage_hits_T_19 = pma_checker__superpage_hits_T_17 & pma_checker__superpage_hits_T_18; // @[TLB.scala:174:{86,95,105}] wire [1:0] pma_checker_hitsVec_idx = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker_hitsVec_idx_1 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker_hitsVec_idx_2 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker_hitsVec_idx_3 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker_hitsVec_idx_4 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker_hitsVec_idx_5 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker_hitsVec_idx_6 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker_hitsVec_idx_7 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker__entries_T = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker__entries_T_24 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker__entries_T_48 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker__entries_T_72 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker__entries_T_96 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker__entries_T_120 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker__entries_T_144 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker__entries_T_168 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [18:0] pma_checker__hitsVec_T_1 = pma_checker__hitsVec_T[20:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__hitsVec_T_2 = pma_checker__hitsVec_T_1 == 19'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__hitsVec_T_4 = pma_checker__hitsVec_T_2 & pma_checker__hitsVec_T_3; // @[TLB.scala:174:{86,95,105}] wire [18:0] pma_checker__hitsVec_T_7 = pma_checker__hitsVec_T_6[20:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__hitsVec_T_8 = pma_checker__hitsVec_T_7 == 19'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__hitsVec_T_10 = pma_checker__hitsVec_T_8 & pma_checker__hitsVec_T_9; // @[TLB.scala:174:{86,95,105}] wire [18:0] pma_checker__hitsVec_T_13 = pma_checker__hitsVec_T_12[20:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__hitsVec_T_14 = pma_checker__hitsVec_T_13 == 19'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__hitsVec_T_16 = pma_checker__hitsVec_T_14 & pma_checker__hitsVec_T_15; // @[TLB.scala:174:{86,95,105}] wire [18:0] pma_checker__hitsVec_T_19 = pma_checker__hitsVec_T_18[20:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__hitsVec_T_20 = pma_checker__hitsVec_T_19 == 19'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__hitsVec_T_22 = pma_checker__hitsVec_T_20 & pma_checker__hitsVec_T_21; // @[TLB.scala:174:{86,95,105}] wire [18:0] pma_checker__hitsVec_T_25 = pma_checker__hitsVec_T_24[20:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__hitsVec_T_26 = pma_checker__hitsVec_T_25 == 19'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__hitsVec_T_28 = pma_checker__hitsVec_T_26 & pma_checker__hitsVec_T_27; // @[TLB.scala:174:{86,95,105}] wire [18:0] pma_checker__hitsVec_T_31 = pma_checker__hitsVec_T_30[20:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__hitsVec_T_32 = pma_checker__hitsVec_T_31 == 19'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__hitsVec_T_34 = pma_checker__hitsVec_T_32 & pma_checker__hitsVec_T_33; // @[TLB.scala:174:{86,95,105}] wire [18:0] pma_checker__hitsVec_T_37 = pma_checker__hitsVec_T_36[20:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__hitsVec_T_38 = pma_checker__hitsVec_T_37 == 19'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__hitsVec_T_40 = pma_checker__hitsVec_T_38 & pma_checker__hitsVec_T_39; // @[TLB.scala:174:{86,95,105}] wire [18:0] pma_checker__hitsVec_T_43 = pma_checker__hitsVec_T_42[20:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__hitsVec_T_44 = pma_checker__hitsVec_T_43 == 19'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__hitsVec_T_46 = pma_checker__hitsVec_T_44 & pma_checker__hitsVec_T_45; // @[TLB.scala:174:{86,95,105}] wire [20:0] pma_checker__hitsVec_T_49 = pma_checker__hitsVec_T_48; // @[TLB.scala:174:{61,68}] wire pma_checker__hitsVec_T_50 = pma_checker__hitsVec_T_49 == 21'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__hitsVec_T_52 = pma_checker__hitsVec_T_50 & pma_checker__hitsVec_T_51; // @[TLB.scala:174:{86,95,105}] wire [20:0] pma_checker__hitsVec_T_55 = pma_checker__hitsVec_T_54; // @[TLB.scala:174:{61,68}] wire pma_checker__hitsVec_T_56 = pma_checker__hitsVec_T_55 == 21'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__hitsVec_T_58 = pma_checker__hitsVec_T_56 & pma_checker__hitsVec_T_57; // @[TLB.scala:174:{86,95,105}] wire [20:0] pma_checker__hitsVec_T_61 = pma_checker__hitsVec_T_60; // @[TLB.scala:174:{61,68}] wire pma_checker__hitsVec_T_62 = pma_checker__hitsVec_T_61 == 21'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__hitsVec_T_64 = pma_checker__hitsVec_T_62 & pma_checker__hitsVec_T_63; // @[TLB.scala:174:{86,95,105}] wire [20:0] pma_checker__hitsVec_T_67 = pma_checker__hitsVec_T_66; // @[TLB.scala:174:{61,68}] wire pma_checker__hitsVec_T_68 = pma_checker__hitsVec_T_67 == 21'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__hitsVec_T_70 = pma_checker__hitsVec_T_68 & pma_checker__hitsVec_T_69; // @[TLB.scala:174:{86,95,105}] wire [20:0] pma_checker__hitsVec_T_73 = pma_checker__hitsVec_T_72; // @[TLB.scala:174:{61,68}] wire pma_checker__hitsVec_T_74 = pma_checker__hitsVec_T_73 == 21'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__hitsVec_T_76 = pma_checker__hitsVec_T_74 & pma_checker__hitsVec_T_75; // @[TLB.scala:174:{86,95,105}] wire pma_checker__hitsVec_T_77 = pma_checker__hitsVec_T_76; // @[TLB.scala:174:95, :188:18] wire pma_checker_newEntry_ppp; // @[TLB.scala:449:24] wire pma_checker_newEntry_pal; // @[TLB.scala:449:24] wire pma_checker_newEntry_paa; // @[TLB.scala:449:24] wire pma_checker_newEntry_eff; // @[TLB.scala:449:24] wire [1:0] _GEN_2 = {pma_checker_newEntry_pal, pma_checker_newEntry_paa}; // @[TLB.scala:217:24, :449:24] wire [1:0] pma_checker_special_entry_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_special_entry_data_0_lo_lo_hi_hi = _GEN_2; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_0_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_0_data_0_lo_lo_hi_hi = _GEN_2; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_1_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_1_data_0_lo_lo_hi_hi = _GEN_2; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_2_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_2_data_0_lo_lo_hi_hi = _GEN_2; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_3_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_3_data_0_lo_lo_hi_hi = _GEN_2; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_0_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_0_data_lo_lo_hi_hi = _GEN_2; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_1_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_1_data_lo_lo_hi_hi = _GEN_2; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_2_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_2_data_lo_lo_hi_hi = _GEN_2; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_3_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_3_data_lo_lo_hi_hi = _GEN_2; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_4_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_4_data_lo_lo_hi_hi = _GEN_2; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_5_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_5_data_lo_lo_hi_hi = _GEN_2; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_6_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_6_data_lo_lo_hi_hi = _GEN_2; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_7_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_7_data_lo_lo_hi_hi = _GEN_2; // @[TLB.scala:217:24] wire [2:0] pma_checker_special_entry_data_0_lo_lo_hi = {pma_checker_special_entry_data_0_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_special_entry_data_0_lo_lo = {pma_checker_special_entry_data_0_lo_lo_hi, 2'h0}; // @[TLB.scala:217:24] wire [1:0] _GEN_3 = {pma_checker_newEntry_px, pma_checker_newEntry_pr}; // @[TLB.scala:217:24, :449:24] wire [1:0] pma_checker_special_entry_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign pma_checker_special_entry_data_0_lo_hi_lo_hi = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_0_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_0_data_0_lo_hi_lo_hi = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_1_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_1_data_0_lo_hi_lo_hi = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_2_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_2_data_0_lo_hi_lo_hi = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_3_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_3_data_0_lo_hi_lo_hi = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_0_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_0_data_lo_hi_lo_hi = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_1_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_1_data_lo_hi_lo_hi = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_2_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_2_data_lo_hi_lo_hi = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_3_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_3_data_lo_hi_lo_hi = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_4_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_4_data_lo_hi_lo_hi = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_5_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_5_data_lo_hi_lo_hi = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_6_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_6_data_lo_hi_lo_hi = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_7_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_7_data_lo_hi_lo_hi = _GEN_3; // @[TLB.scala:217:24] wire [2:0] pma_checker_special_entry_data_0_lo_hi_lo = {pma_checker_special_entry_data_0_lo_hi_lo_hi, pma_checker_newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] _GEN_4 = {2'h0, pma_checker_newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [2:0] pma_checker_special_entry_data_0_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_special_entry_data_0_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_0_data_0_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_0_data_0_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_1_data_0_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_1_data_0_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_2_data_0_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_2_data_0_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_3_data_0_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_3_data_0_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_0_data_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_0_data_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_1_data_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_1_data_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_2_data_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_2_data_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_3_data_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_3_data_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_4_data_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_4_data_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_5_data_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_5_data_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_6_data_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_6_data_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_7_data_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_7_data_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [5:0] pma_checker_special_entry_data_0_lo_hi = {pma_checker_special_entry_data_0_lo_hi_hi, pma_checker_special_entry_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_special_entry_data_0_lo = {pma_checker_special_entry_data_0_lo_hi, pma_checker_special_entry_data_0_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__special_entry_data_0_T = {31'h0, pma_checker_special_entry_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_0_data_0_lo_lo_hi = {pma_checker_superpage_entries_0_data_0_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_superpage_entries_0_data_0_lo_lo = {pma_checker_superpage_entries_0_data_0_lo_lo_hi, 2'h0}; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_0_data_0_lo_hi_lo = {pma_checker_superpage_entries_0_data_0_lo_hi_lo_hi, pma_checker_newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [5:0] pma_checker_superpage_entries_0_data_0_lo_hi = {pma_checker_superpage_entries_0_data_0_lo_hi_hi, pma_checker_superpage_entries_0_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_superpage_entries_0_data_0_lo = {pma_checker_superpage_entries_0_data_0_lo_hi, pma_checker_superpage_entries_0_data_0_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__superpage_entries_0_data_0_T = {31'h0, pma_checker_superpage_entries_0_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_1_data_0_lo_lo_hi = {pma_checker_superpage_entries_1_data_0_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_superpage_entries_1_data_0_lo_lo = {pma_checker_superpage_entries_1_data_0_lo_lo_hi, 2'h0}; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_1_data_0_lo_hi_lo = {pma_checker_superpage_entries_1_data_0_lo_hi_lo_hi, pma_checker_newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [5:0] pma_checker_superpage_entries_1_data_0_lo_hi = {pma_checker_superpage_entries_1_data_0_lo_hi_hi, pma_checker_superpage_entries_1_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_superpage_entries_1_data_0_lo = {pma_checker_superpage_entries_1_data_0_lo_hi, pma_checker_superpage_entries_1_data_0_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__superpage_entries_1_data_0_T = {31'h0, pma_checker_superpage_entries_1_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_2_data_0_lo_lo_hi = {pma_checker_superpage_entries_2_data_0_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_superpage_entries_2_data_0_lo_lo = {pma_checker_superpage_entries_2_data_0_lo_lo_hi, 2'h0}; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_2_data_0_lo_hi_lo = {pma_checker_superpage_entries_2_data_0_lo_hi_lo_hi, pma_checker_newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [5:0] pma_checker_superpage_entries_2_data_0_lo_hi = {pma_checker_superpage_entries_2_data_0_lo_hi_hi, pma_checker_superpage_entries_2_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_superpage_entries_2_data_0_lo = {pma_checker_superpage_entries_2_data_0_lo_hi, pma_checker_superpage_entries_2_data_0_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__superpage_entries_2_data_0_T = {31'h0, pma_checker_superpage_entries_2_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_3_data_0_lo_lo_hi = {pma_checker_superpage_entries_3_data_0_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_superpage_entries_3_data_0_lo_lo = {pma_checker_superpage_entries_3_data_0_lo_lo_hi, 2'h0}; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_3_data_0_lo_hi_lo = {pma_checker_superpage_entries_3_data_0_lo_hi_lo_hi, pma_checker_newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [5:0] pma_checker_superpage_entries_3_data_0_lo_hi = {pma_checker_superpage_entries_3_data_0_lo_hi_hi, pma_checker_superpage_entries_3_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_superpage_entries_3_data_0_lo = {pma_checker_superpage_entries_3_data_0_lo_hi, pma_checker_superpage_entries_3_data_0_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__superpage_entries_3_data_0_T = {31'h0, pma_checker_superpage_entries_3_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_0_data_lo_lo_hi = {pma_checker_sectored_entries_0_0_data_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_sectored_entries_0_0_data_lo_lo = {pma_checker_sectored_entries_0_0_data_lo_lo_hi, 2'h0}; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_0_data_lo_hi_lo = {pma_checker_sectored_entries_0_0_data_lo_hi_lo_hi, pma_checker_newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [5:0] pma_checker_sectored_entries_0_0_data_lo_hi = {pma_checker_sectored_entries_0_0_data_lo_hi_hi, pma_checker_sectored_entries_0_0_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_sectored_entries_0_0_data_lo = {pma_checker_sectored_entries_0_0_data_lo_hi, pma_checker_sectored_entries_0_0_data_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__sectored_entries_0_0_data_T = {31'h0, pma_checker_sectored_entries_0_0_data_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_1_data_lo_lo_hi = {pma_checker_sectored_entries_0_1_data_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_sectored_entries_0_1_data_lo_lo = {pma_checker_sectored_entries_0_1_data_lo_lo_hi, 2'h0}; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_1_data_lo_hi_lo = {pma_checker_sectored_entries_0_1_data_lo_hi_lo_hi, pma_checker_newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [5:0] pma_checker_sectored_entries_0_1_data_lo_hi = {pma_checker_sectored_entries_0_1_data_lo_hi_hi, pma_checker_sectored_entries_0_1_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_sectored_entries_0_1_data_lo = {pma_checker_sectored_entries_0_1_data_lo_hi, pma_checker_sectored_entries_0_1_data_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__sectored_entries_0_1_data_T = {31'h0, pma_checker_sectored_entries_0_1_data_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_2_data_lo_lo_hi = {pma_checker_sectored_entries_0_2_data_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_sectored_entries_0_2_data_lo_lo = {pma_checker_sectored_entries_0_2_data_lo_lo_hi, 2'h0}; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_2_data_lo_hi_lo = {pma_checker_sectored_entries_0_2_data_lo_hi_lo_hi, pma_checker_newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [5:0] pma_checker_sectored_entries_0_2_data_lo_hi = {pma_checker_sectored_entries_0_2_data_lo_hi_hi, pma_checker_sectored_entries_0_2_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_sectored_entries_0_2_data_lo = {pma_checker_sectored_entries_0_2_data_lo_hi, pma_checker_sectored_entries_0_2_data_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__sectored_entries_0_2_data_T = {31'h0, pma_checker_sectored_entries_0_2_data_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_3_data_lo_lo_hi = {pma_checker_sectored_entries_0_3_data_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_sectored_entries_0_3_data_lo_lo = {pma_checker_sectored_entries_0_3_data_lo_lo_hi, 2'h0}; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_3_data_lo_hi_lo = {pma_checker_sectored_entries_0_3_data_lo_hi_lo_hi, pma_checker_newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [5:0] pma_checker_sectored_entries_0_3_data_lo_hi = {pma_checker_sectored_entries_0_3_data_lo_hi_hi, pma_checker_sectored_entries_0_3_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_sectored_entries_0_3_data_lo = {pma_checker_sectored_entries_0_3_data_lo_hi, pma_checker_sectored_entries_0_3_data_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__sectored_entries_0_3_data_T = {31'h0, pma_checker_sectored_entries_0_3_data_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_4_data_lo_lo_hi = {pma_checker_sectored_entries_0_4_data_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_sectored_entries_0_4_data_lo_lo = {pma_checker_sectored_entries_0_4_data_lo_lo_hi, 2'h0}; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_4_data_lo_hi_lo = {pma_checker_sectored_entries_0_4_data_lo_hi_lo_hi, pma_checker_newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [5:0] pma_checker_sectored_entries_0_4_data_lo_hi = {pma_checker_sectored_entries_0_4_data_lo_hi_hi, pma_checker_sectored_entries_0_4_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_sectored_entries_0_4_data_lo = {pma_checker_sectored_entries_0_4_data_lo_hi, pma_checker_sectored_entries_0_4_data_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__sectored_entries_0_4_data_T = {31'h0, pma_checker_sectored_entries_0_4_data_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_5_data_lo_lo_hi = {pma_checker_sectored_entries_0_5_data_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_sectored_entries_0_5_data_lo_lo = {pma_checker_sectored_entries_0_5_data_lo_lo_hi, 2'h0}; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_5_data_lo_hi_lo = {pma_checker_sectored_entries_0_5_data_lo_hi_lo_hi, pma_checker_newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [5:0] pma_checker_sectored_entries_0_5_data_lo_hi = {pma_checker_sectored_entries_0_5_data_lo_hi_hi, pma_checker_sectored_entries_0_5_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_sectored_entries_0_5_data_lo = {pma_checker_sectored_entries_0_5_data_lo_hi, pma_checker_sectored_entries_0_5_data_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__sectored_entries_0_5_data_T = {31'h0, pma_checker_sectored_entries_0_5_data_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_6_data_lo_lo_hi = {pma_checker_sectored_entries_0_6_data_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_sectored_entries_0_6_data_lo_lo = {pma_checker_sectored_entries_0_6_data_lo_lo_hi, 2'h0}; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_6_data_lo_hi_lo = {pma_checker_sectored_entries_0_6_data_lo_hi_lo_hi, pma_checker_newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [5:0] pma_checker_sectored_entries_0_6_data_lo_hi = {pma_checker_sectored_entries_0_6_data_lo_hi_hi, pma_checker_sectored_entries_0_6_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_sectored_entries_0_6_data_lo = {pma_checker_sectored_entries_0_6_data_lo_hi, pma_checker_sectored_entries_0_6_data_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__sectored_entries_0_6_data_T = {31'h0, pma_checker_sectored_entries_0_6_data_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_7_data_lo_lo_hi = {pma_checker_sectored_entries_0_7_data_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_sectored_entries_0_7_data_lo_lo = {pma_checker_sectored_entries_0_7_data_lo_lo_hi, 2'h0}; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_7_data_lo_hi_lo = {pma_checker_sectored_entries_0_7_data_lo_hi_lo_hi, pma_checker_newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [5:0] pma_checker_sectored_entries_0_7_data_lo_hi = {pma_checker_sectored_entries_0_7_data_lo_hi_hi, pma_checker_sectored_entries_0_7_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_sectored_entries_0_7_data_lo = {pma_checker_sectored_entries_0_7_data_lo_hi, pma_checker_sectored_entries_0_7_data_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__sectored_entries_0_7_data_T = {31'h0, pma_checker_sectored_entries_0_7_data_lo}; // @[TLB.scala:217:24] wire [19:0] pma_checker__entries_T_23; // @[TLB.scala:170:77] wire pma_checker__entries_T_22; // @[TLB.scala:170:77] wire pma_checker__entries_T_21; // @[TLB.scala:170:77] wire pma_checker__entries_T_20; // @[TLB.scala:170:77] wire pma_checker__entries_T_19; // @[TLB.scala:170:77] wire pma_checker__entries_T_18; // @[TLB.scala:170:77] wire pma_checker__entries_T_17; // @[TLB.scala:170:77] wire pma_checker__entries_T_16; // @[TLB.scala:170:77] wire pma_checker__entries_T_15; // @[TLB.scala:170:77] wire pma_checker__entries_T_14; // @[TLB.scala:170:77] wire pma_checker__entries_T_13; // @[TLB.scala:170:77] wire pma_checker__entries_T_12; // @[TLB.scala:170:77] wire pma_checker__entries_T_11; // @[TLB.scala:170:77] wire pma_checker__entries_T_10; // @[TLB.scala:170:77] wire pma_checker__entries_T_9; // @[TLB.scala:170:77] wire pma_checker__entries_T_8; // @[TLB.scala:170:77] wire pma_checker__entries_T_7; // @[TLB.scala:170:77] wire pma_checker__entries_T_6; // @[TLB.scala:170:77] wire pma_checker__entries_T_5; // @[TLB.scala:170:77] wire pma_checker__entries_T_4; // @[TLB.scala:170:77] wire pma_checker__entries_T_3; // @[TLB.scala:170:77] wire pma_checker__entries_T_2; // @[TLB.scala:170:77] wire pma_checker__entries_T_1; // @[TLB.scala:170:77] assign pma_checker__entries_T_1 = pma_checker__entries_WIRE_1[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_fragmented_superpage = pma_checker__entries_T_1; // @[TLB.scala:170:77] assign pma_checker__entries_T_2 = pma_checker__entries_WIRE_1[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_c = pma_checker__entries_T_2; // @[TLB.scala:170:77] assign pma_checker__entries_T_3 = pma_checker__entries_WIRE_1[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_eff = pma_checker__entries_T_3; // @[TLB.scala:170:77] assign pma_checker__entries_T_4 = pma_checker__entries_WIRE_1[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_paa = pma_checker__entries_T_4; // @[TLB.scala:170:77] assign pma_checker__entries_T_5 = pma_checker__entries_WIRE_1[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_pal = pma_checker__entries_T_5; // @[TLB.scala:170:77] assign pma_checker__entries_T_6 = pma_checker__entries_WIRE_1[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_ppp = pma_checker__entries_T_6; // @[TLB.scala:170:77] assign pma_checker__entries_T_7 = pma_checker__entries_WIRE_1[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_pr = pma_checker__entries_T_7; // @[TLB.scala:170:77] assign pma_checker__entries_T_8 = pma_checker__entries_WIRE_1[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_px = pma_checker__entries_T_8; // @[TLB.scala:170:77] assign pma_checker__entries_T_9 = pma_checker__entries_WIRE_1[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_pw = pma_checker__entries_T_9; // @[TLB.scala:170:77] assign pma_checker__entries_T_10 = pma_checker__entries_WIRE_1[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_hr = pma_checker__entries_T_10; // @[TLB.scala:170:77] assign pma_checker__entries_T_11 = pma_checker__entries_WIRE_1[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_hx = pma_checker__entries_T_11; // @[TLB.scala:170:77] assign pma_checker__entries_T_12 = pma_checker__entries_WIRE_1[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_hw = pma_checker__entries_T_12; // @[TLB.scala:170:77] assign pma_checker__entries_T_13 = pma_checker__entries_WIRE_1[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_sr = pma_checker__entries_T_13; // @[TLB.scala:170:77] assign pma_checker__entries_T_14 = pma_checker__entries_WIRE_1[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_sx = pma_checker__entries_T_14; // @[TLB.scala:170:77] assign pma_checker__entries_T_15 = pma_checker__entries_WIRE_1[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_sw = pma_checker__entries_T_15; // @[TLB.scala:170:77] assign pma_checker__entries_T_16 = pma_checker__entries_WIRE_1[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_gf = pma_checker__entries_T_16; // @[TLB.scala:170:77] assign pma_checker__entries_T_17 = pma_checker__entries_WIRE_1[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_pf = pma_checker__entries_T_17; // @[TLB.scala:170:77] assign pma_checker__entries_T_18 = pma_checker__entries_WIRE_1[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_ae_stage2 = pma_checker__entries_T_18; // @[TLB.scala:170:77] assign pma_checker__entries_T_19 = pma_checker__entries_WIRE_1[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_ae_final = pma_checker__entries_T_19; // @[TLB.scala:170:77] assign pma_checker__entries_T_20 = pma_checker__entries_WIRE_1[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_ae_ptw = pma_checker__entries_T_20; // @[TLB.scala:170:77] assign pma_checker__entries_T_21 = pma_checker__entries_WIRE_1[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_g = pma_checker__entries_T_21; // @[TLB.scala:170:77] assign pma_checker__entries_T_22 = pma_checker__entries_WIRE_1[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_u = pma_checker__entries_T_22; // @[TLB.scala:170:77] assign pma_checker__entries_T_23 = pma_checker__entries_WIRE_1[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_ppn = pma_checker__entries_T_23; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_47; // @[TLB.scala:170:77] wire pma_checker__entries_T_46; // @[TLB.scala:170:77] wire pma_checker__entries_T_45; // @[TLB.scala:170:77] wire pma_checker__entries_T_44; // @[TLB.scala:170:77] wire pma_checker__entries_T_43; // @[TLB.scala:170:77] wire pma_checker__entries_T_42; // @[TLB.scala:170:77] wire pma_checker__entries_T_41; // @[TLB.scala:170:77] wire pma_checker__entries_T_40; // @[TLB.scala:170:77] wire pma_checker__entries_T_39; // @[TLB.scala:170:77] wire pma_checker__entries_T_38; // @[TLB.scala:170:77] wire pma_checker__entries_T_37; // @[TLB.scala:170:77] wire pma_checker__entries_T_36; // @[TLB.scala:170:77] wire pma_checker__entries_T_35; // @[TLB.scala:170:77] wire pma_checker__entries_T_34; // @[TLB.scala:170:77] wire pma_checker__entries_T_33; // @[TLB.scala:170:77] wire pma_checker__entries_T_32; // @[TLB.scala:170:77] wire pma_checker__entries_T_31; // @[TLB.scala:170:77] wire pma_checker__entries_T_30; // @[TLB.scala:170:77] wire pma_checker__entries_T_29; // @[TLB.scala:170:77] wire pma_checker__entries_T_28; // @[TLB.scala:170:77] wire pma_checker__entries_T_27; // @[TLB.scala:170:77] wire pma_checker__entries_T_26; // @[TLB.scala:170:77] wire pma_checker__entries_T_25; // @[TLB.scala:170:77] assign pma_checker__entries_T_25 = pma_checker__entries_WIRE_3[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_fragmented_superpage = pma_checker__entries_T_25; // @[TLB.scala:170:77] assign pma_checker__entries_T_26 = pma_checker__entries_WIRE_3[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_c = pma_checker__entries_T_26; // @[TLB.scala:170:77] assign pma_checker__entries_T_27 = pma_checker__entries_WIRE_3[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_eff = pma_checker__entries_T_27; // @[TLB.scala:170:77] assign pma_checker__entries_T_28 = pma_checker__entries_WIRE_3[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_paa = pma_checker__entries_T_28; // @[TLB.scala:170:77] assign pma_checker__entries_T_29 = pma_checker__entries_WIRE_3[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_pal = pma_checker__entries_T_29; // @[TLB.scala:170:77] assign pma_checker__entries_T_30 = pma_checker__entries_WIRE_3[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_ppp = pma_checker__entries_T_30; // @[TLB.scala:170:77] assign pma_checker__entries_T_31 = pma_checker__entries_WIRE_3[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_pr = pma_checker__entries_T_31; // @[TLB.scala:170:77] assign pma_checker__entries_T_32 = pma_checker__entries_WIRE_3[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_px = pma_checker__entries_T_32; // @[TLB.scala:170:77] assign pma_checker__entries_T_33 = pma_checker__entries_WIRE_3[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_pw = pma_checker__entries_T_33; // @[TLB.scala:170:77] assign pma_checker__entries_T_34 = pma_checker__entries_WIRE_3[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_hr = pma_checker__entries_T_34; // @[TLB.scala:170:77] assign pma_checker__entries_T_35 = pma_checker__entries_WIRE_3[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_hx = pma_checker__entries_T_35; // @[TLB.scala:170:77] assign pma_checker__entries_T_36 = pma_checker__entries_WIRE_3[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_hw = pma_checker__entries_T_36; // @[TLB.scala:170:77] assign pma_checker__entries_T_37 = pma_checker__entries_WIRE_3[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_sr = pma_checker__entries_T_37; // @[TLB.scala:170:77] assign pma_checker__entries_T_38 = pma_checker__entries_WIRE_3[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_sx = pma_checker__entries_T_38; // @[TLB.scala:170:77] assign pma_checker__entries_T_39 = pma_checker__entries_WIRE_3[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_sw = pma_checker__entries_T_39; // @[TLB.scala:170:77] assign pma_checker__entries_T_40 = pma_checker__entries_WIRE_3[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_gf = pma_checker__entries_T_40; // @[TLB.scala:170:77] assign pma_checker__entries_T_41 = pma_checker__entries_WIRE_3[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_pf = pma_checker__entries_T_41; // @[TLB.scala:170:77] assign pma_checker__entries_T_42 = pma_checker__entries_WIRE_3[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_ae_stage2 = pma_checker__entries_T_42; // @[TLB.scala:170:77] assign pma_checker__entries_T_43 = pma_checker__entries_WIRE_3[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_ae_final = pma_checker__entries_T_43; // @[TLB.scala:170:77] assign pma_checker__entries_T_44 = pma_checker__entries_WIRE_3[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_ae_ptw = pma_checker__entries_T_44; // @[TLB.scala:170:77] assign pma_checker__entries_T_45 = pma_checker__entries_WIRE_3[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_g = pma_checker__entries_T_45; // @[TLB.scala:170:77] assign pma_checker__entries_T_46 = pma_checker__entries_WIRE_3[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_u = pma_checker__entries_T_46; // @[TLB.scala:170:77] assign pma_checker__entries_T_47 = pma_checker__entries_WIRE_3[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_2_ppn = pma_checker__entries_T_47; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_71; // @[TLB.scala:170:77] wire pma_checker__entries_T_70; // @[TLB.scala:170:77] wire pma_checker__entries_T_69; // @[TLB.scala:170:77] wire pma_checker__entries_T_68; // @[TLB.scala:170:77] wire pma_checker__entries_T_67; // @[TLB.scala:170:77] wire pma_checker__entries_T_66; // @[TLB.scala:170:77] wire pma_checker__entries_T_65; // @[TLB.scala:170:77] wire pma_checker__entries_T_64; // @[TLB.scala:170:77] wire pma_checker__entries_T_63; // @[TLB.scala:170:77] wire pma_checker__entries_T_62; // @[TLB.scala:170:77] wire pma_checker__entries_T_61; // @[TLB.scala:170:77] wire pma_checker__entries_T_60; // @[TLB.scala:170:77] wire pma_checker__entries_T_59; // @[TLB.scala:170:77] wire pma_checker__entries_T_58; // @[TLB.scala:170:77] wire pma_checker__entries_T_57; // @[TLB.scala:170:77] wire pma_checker__entries_T_56; // @[TLB.scala:170:77] wire pma_checker__entries_T_55; // @[TLB.scala:170:77] wire pma_checker__entries_T_54; // @[TLB.scala:170:77] wire pma_checker__entries_T_53; // @[TLB.scala:170:77] wire pma_checker__entries_T_52; // @[TLB.scala:170:77] wire pma_checker__entries_T_51; // @[TLB.scala:170:77] wire pma_checker__entries_T_50; // @[TLB.scala:170:77] wire pma_checker__entries_T_49; // @[TLB.scala:170:77] assign pma_checker__entries_T_49 = pma_checker__entries_WIRE_5[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_fragmented_superpage = pma_checker__entries_T_49; // @[TLB.scala:170:77] assign pma_checker__entries_T_50 = pma_checker__entries_WIRE_5[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_c = pma_checker__entries_T_50; // @[TLB.scala:170:77] assign pma_checker__entries_T_51 = pma_checker__entries_WIRE_5[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_eff = pma_checker__entries_T_51; // @[TLB.scala:170:77] assign pma_checker__entries_T_52 = pma_checker__entries_WIRE_5[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_paa = pma_checker__entries_T_52; // @[TLB.scala:170:77] assign pma_checker__entries_T_53 = pma_checker__entries_WIRE_5[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_pal = pma_checker__entries_T_53; // @[TLB.scala:170:77] assign pma_checker__entries_T_54 = pma_checker__entries_WIRE_5[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_ppp = pma_checker__entries_T_54; // @[TLB.scala:170:77] assign pma_checker__entries_T_55 = pma_checker__entries_WIRE_5[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_pr = pma_checker__entries_T_55; // @[TLB.scala:170:77] assign pma_checker__entries_T_56 = pma_checker__entries_WIRE_5[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_px = pma_checker__entries_T_56; // @[TLB.scala:170:77] assign pma_checker__entries_T_57 = pma_checker__entries_WIRE_5[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_pw = pma_checker__entries_T_57; // @[TLB.scala:170:77] assign pma_checker__entries_T_58 = pma_checker__entries_WIRE_5[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_hr = pma_checker__entries_T_58; // @[TLB.scala:170:77] assign pma_checker__entries_T_59 = pma_checker__entries_WIRE_5[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_hx = pma_checker__entries_T_59; // @[TLB.scala:170:77] assign pma_checker__entries_T_60 = pma_checker__entries_WIRE_5[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_hw = pma_checker__entries_T_60; // @[TLB.scala:170:77] assign pma_checker__entries_T_61 = pma_checker__entries_WIRE_5[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_sr = pma_checker__entries_T_61; // @[TLB.scala:170:77] assign pma_checker__entries_T_62 = pma_checker__entries_WIRE_5[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_sx = pma_checker__entries_T_62; // @[TLB.scala:170:77] assign pma_checker__entries_T_63 = pma_checker__entries_WIRE_5[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_sw = pma_checker__entries_T_63; // @[TLB.scala:170:77] assign pma_checker__entries_T_64 = pma_checker__entries_WIRE_5[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_gf = pma_checker__entries_T_64; // @[TLB.scala:170:77] assign pma_checker__entries_T_65 = pma_checker__entries_WIRE_5[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_pf = pma_checker__entries_T_65; // @[TLB.scala:170:77] assign pma_checker__entries_T_66 = pma_checker__entries_WIRE_5[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_ae_stage2 = pma_checker__entries_T_66; // @[TLB.scala:170:77] assign pma_checker__entries_T_67 = pma_checker__entries_WIRE_5[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_ae_final = pma_checker__entries_T_67; // @[TLB.scala:170:77] assign pma_checker__entries_T_68 = pma_checker__entries_WIRE_5[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_ae_ptw = pma_checker__entries_T_68; // @[TLB.scala:170:77] assign pma_checker__entries_T_69 = pma_checker__entries_WIRE_5[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_g = pma_checker__entries_T_69; // @[TLB.scala:170:77] assign pma_checker__entries_T_70 = pma_checker__entries_WIRE_5[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_u = pma_checker__entries_T_70; // @[TLB.scala:170:77] assign pma_checker__entries_T_71 = pma_checker__entries_WIRE_5[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_4_ppn = pma_checker__entries_T_71; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_95; // @[TLB.scala:170:77] wire pma_checker__entries_T_94; // @[TLB.scala:170:77] wire pma_checker__entries_T_93; // @[TLB.scala:170:77] wire pma_checker__entries_T_92; // @[TLB.scala:170:77] wire pma_checker__entries_T_91; // @[TLB.scala:170:77] wire pma_checker__entries_T_90; // @[TLB.scala:170:77] wire pma_checker__entries_T_89; // @[TLB.scala:170:77] wire pma_checker__entries_T_88; // @[TLB.scala:170:77] wire pma_checker__entries_T_87; // @[TLB.scala:170:77] wire pma_checker__entries_T_86; // @[TLB.scala:170:77] wire pma_checker__entries_T_85; // @[TLB.scala:170:77] wire pma_checker__entries_T_84; // @[TLB.scala:170:77] wire pma_checker__entries_T_83; // @[TLB.scala:170:77] wire pma_checker__entries_T_82; // @[TLB.scala:170:77] wire pma_checker__entries_T_81; // @[TLB.scala:170:77] wire pma_checker__entries_T_80; // @[TLB.scala:170:77] wire pma_checker__entries_T_79; // @[TLB.scala:170:77] wire pma_checker__entries_T_78; // @[TLB.scala:170:77] wire pma_checker__entries_T_77; // @[TLB.scala:170:77] wire pma_checker__entries_T_76; // @[TLB.scala:170:77] wire pma_checker__entries_T_75; // @[TLB.scala:170:77] wire pma_checker__entries_T_74; // @[TLB.scala:170:77] wire pma_checker__entries_T_73; // @[TLB.scala:170:77] assign pma_checker__entries_T_73 = pma_checker__entries_WIRE_7[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_fragmented_superpage = pma_checker__entries_T_73; // @[TLB.scala:170:77] assign pma_checker__entries_T_74 = pma_checker__entries_WIRE_7[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_c = pma_checker__entries_T_74; // @[TLB.scala:170:77] assign pma_checker__entries_T_75 = pma_checker__entries_WIRE_7[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_eff = pma_checker__entries_T_75; // @[TLB.scala:170:77] assign pma_checker__entries_T_76 = pma_checker__entries_WIRE_7[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_paa = pma_checker__entries_T_76; // @[TLB.scala:170:77] assign pma_checker__entries_T_77 = pma_checker__entries_WIRE_7[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_pal = pma_checker__entries_T_77; // @[TLB.scala:170:77] assign pma_checker__entries_T_78 = pma_checker__entries_WIRE_7[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_ppp = pma_checker__entries_T_78; // @[TLB.scala:170:77] assign pma_checker__entries_T_79 = pma_checker__entries_WIRE_7[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_pr = pma_checker__entries_T_79; // @[TLB.scala:170:77] assign pma_checker__entries_T_80 = pma_checker__entries_WIRE_7[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_px = pma_checker__entries_T_80; // @[TLB.scala:170:77] assign pma_checker__entries_T_81 = pma_checker__entries_WIRE_7[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_pw = pma_checker__entries_T_81; // @[TLB.scala:170:77] assign pma_checker__entries_T_82 = pma_checker__entries_WIRE_7[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_hr = pma_checker__entries_T_82; // @[TLB.scala:170:77] assign pma_checker__entries_T_83 = pma_checker__entries_WIRE_7[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_hx = pma_checker__entries_T_83; // @[TLB.scala:170:77] assign pma_checker__entries_T_84 = pma_checker__entries_WIRE_7[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_hw = pma_checker__entries_T_84; // @[TLB.scala:170:77] assign pma_checker__entries_T_85 = pma_checker__entries_WIRE_7[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_sr = pma_checker__entries_T_85; // @[TLB.scala:170:77] assign pma_checker__entries_T_86 = pma_checker__entries_WIRE_7[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_sx = pma_checker__entries_T_86; // @[TLB.scala:170:77] assign pma_checker__entries_T_87 = pma_checker__entries_WIRE_7[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_sw = pma_checker__entries_T_87; // @[TLB.scala:170:77] assign pma_checker__entries_T_88 = pma_checker__entries_WIRE_7[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_gf = pma_checker__entries_T_88; // @[TLB.scala:170:77] assign pma_checker__entries_T_89 = pma_checker__entries_WIRE_7[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_pf = pma_checker__entries_T_89; // @[TLB.scala:170:77] assign pma_checker__entries_T_90 = pma_checker__entries_WIRE_7[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_ae_stage2 = pma_checker__entries_T_90; // @[TLB.scala:170:77] assign pma_checker__entries_T_91 = pma_checker__entries_WIRE_7[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_ae_final = pma_checker__entries_T_91; // @[TLB.scala:170:77] assign pma_checker__entries_T_92 = pma_checker__entries_WIRE_7[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_ae_ptw = pma_checker__entries_T_92; // @[TLB.scala:170:77] assign pma_checker__entries_T_93 = pma_checker__entries_WIRE_7[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_g = pma_checker__entries_T_93; // @[TLB.scala:170:77] assign pma_checker__entries_T_94 = pma_checker__entries_WIRE_7[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_u = pma_checker__entries_T_94; // @[TLB.scala:170:77] assign pma_checker__entries_T_95 = pma_checker__entries_WIRE_7[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_6_ppn = pma_checker__entries_T_95; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_119; // @[TLB.scala:170:77] wire pma_checker__entries_T_118; // @[TLB.scala:170:77] wire pma_checker__entries_T_117; // @[TLB.scala:170:77] wire pma_checker__entries_T_116; // @[TLB.scala:170:77] wire pma_checker__entries_T_115; // @[TLB.scala:170:77] wire pma_checker__entries_T_114; // @[TLB.scala:170:77] wire pma_checker__entries_T_113; // @[TLB.scala:170:77] wire pma_checker__entries_T_112; // @[TLB.scala:170:77] wire pma_checker__entries_T_111; // @[TLB.scala:170:77] wire pma_checker__entries_T_110; // @[TLB.scala:170:77] wire pma_checker__entries_T_109; // @[TLB.scala:170:77] wire pma_checker__entries_T_108; // @[TLB.scala:170:77] wire pma_checker__entries_T_107; // @[TLB.scala:170:77] wire pma_checker__entries_T_106; // @[TLB.scala:170:77] wire pma_checker__entries_T_105; // @[TLB.scala:170:77] wire pma_checker__entries_T_104; // @[TLB.scala:170:77] wire pma_checker__entries_T_103; // @[TLB.scala:170:77] wire pma_checker__entries_T_102; // @[TLB.scala:170:77] wire pma_checker__entries_T_101; // @[TLB.scala:170:77] wire pma_checker__entries_T_100; // @[TLB.scala:170:77] wire pma_checker__entries_T_99; // @[TLB.scala:170:77] wire pma_checker__entries_T_98; // @[TLB.scala:170:77] wire pma_checker__entries_T_97; // @[TLB.scala:170:77] assign pma_checker__entries_T_97 = pma_checker__entries_WIRE_9[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_fragmented_superpage = pma_checker__entries_T_97; // @[TLB.scala:170:77] assign pma_checker__entries_T_98 = pma_checker__entries_WIRE_9[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_c = pma_checker__entries_T_98; // @[TLB.scala:170:77] assign pma_checker__entries_T_99 = pma_checker__entries_WIRE_9[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_eff = pma_checker__entries_T_99; // @[TLB.scala:170:77] assign pma_checker__entries_T_100 = pma_checker__entries_WIRE_9[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_paa = pma_checker__entries_T_100; // @[TLB.scala:170:77] assign pma_checker__entries_T_101 = pma_checker__entries_WIRE_9[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_pal = pma_checker__entries_T_101; // @[TLB.scala:170:77] assign pma_checker__entries_T_102 = pma_checker__entries_WIRE_9[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_ppp = pma_checker__entries_T_102; // @[TLB.scala:170:77] assign pma_checker__entries_T_103 = pma_checker__entries_WIRE_9[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_pr = pma_checker__entries_T_103; // @[TLB.scala:170:77] assign pma_checker__entries_T_104 = pma_checker__entries_WIRE_9[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_px = pma_checker__entries_T_104; // @[TLB.scala:170:77] assign pma_checker__entries_T_105 = pma_checker__entries_WIRE_9[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_pw = pma_checker__entries_T_105; // @[TLB.scala:170:77] assign pma_checker__entries_T_106 = pma_checker__entries_WIRE_9[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_hr = pma_checker__entries_T_106; // @[TLB.scala:170:77] assign pma_checker__entries_T_107 = pma_checker__entries_WIRE_9[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_hx = pma_checker__entries_T_107; // @[TLB.scala:170:77] assign pma_checker__entries_T_108 = pma_checker__entries_WIRE_9[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_hw = pma_checker__entries_T_108; // @[TLB.scala:170:77] assign pma_checker__entries_T_109 = pma_checker__entries_WIRE_9[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_sr = pma_checker__entries_T_109; // @[TLB.scala:170:77] assign pma_checker__entries_T_110 = pma_checker__entries_WIRE_9[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_sx = pma_checker__entries_T_110; // @[TLB.scala:170:77] assign pma_checker__entries_T_111 = pma_checker__entries_WIRE_9[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_sw = pma_checker__entries_T_111; // @[TLB.scala:170:77] assign pma_checker__entries_T_112 = pma_checker__entries_WIRE_9[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_gf = pma_checker__entries_T_112; // @[TLB.scala:170:77] assign pma_checker__entries_T_113 = pma_checker__entries_WIRE_9[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_pf = pma_checker__entries_T_113; // @[TLB.scala:170:77] assign pma_checker__entries_T_114 = pma_checker__entries_WIRE_9[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_ae_stage2 = pma_checker__entries_T_114; // @[TLB.scala:170:77] assign pma_checker__entries_T_115 = pma_checker__entries_WIRE_9[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_ae_final = pma_checker__entries_T_115; // @[TLB.scala:170:77] assign pma_checker__entries_T_116 = pma_checker__entries_WIRE_9[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_ae_ptw = pma_checker__entries_T_116; // @[TLB.scala:170:77] assign pma_checker__entries_T_117 = pma_checker__entries_WIRE_9[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_g = pma_checker__entries_T_117; // @[TLB.scala:170:77] assign pma_checker__entries_T_118 = pma_checker__entries_WIRE_9[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_u = pma_checker__entries_T_118; // @[TLB.scala:170:77] assign pma_checker__entries_T_119 = pma_checker__entries_WIRE_9[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_8_ppn = pma_checker__entries_T_119; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_143; // @[TLB.scala:170:77] wire pma_checker__entries_T_142; // @[TLB.scala:170:77] wire pma_checker__entries_T_141; // @[TLB.scala:170:77] wire pma_checker__entries_T_140; // @[TLB.scala:170:77] wire pma_checker__entries_T_139; // @[TLB.scala:170:77] wire pma_checker__entries_T_138; // @[TLB.scala:170:77] wire pma_checker__entries_T_137; // @[TLB.scala:170:77] wire pma_checker__entries_T_136; // @[TLB.scala:170:77] wire pma_checker__entries_T_135; // @[TLB.scala:170:77] wire pma_checker__entries_T_134; // @[TLB.scala:170:77] wire pma_checker__entries_T_133; // @[TLB.scala:170:77] wire pma_checker__entries_T_132; // @[TLB.scala:170:77] wire pma_checker__entries_T_131; // @[TLB.scala:170:77] wire pma_checker__entries_T_130; // @[TLB.scala:170:77] wire pma_checker__entries_T_129; // @[TLB.scala:170:77] wire pma_checker__entries_T_128; // @[TLB.scala:170:77] wire pma_checker__entries_T_127; // @[TLB.scala:170:77] wire pma_checker__entries_T_126; // @[TLB.scala:170:77] wire pma_checker__entries_T_125; // @[TLB.scala:170:77] wire pma_checker__entries_T_124; // @[TLB.scala:170:77] wire pma_checker__entries_T_123; // @[TLB.scala:170:77] wire pma_checker__entries_T_122; // @[TLB.scala:170:77] wire pma_checker__entries_T_121; // @[TLB.scala:170:77] assign pma_checker__entries_T_121 = pma_checker__entries_WIRE_11[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_fragmented_superpage = pma_checker__entries_T_121; // @[TLB.scala:170:77] assign pma_checker__entries_T_122 = pma_checker__entries_WIRE_11[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_c = pma_checker__entries_T_122; // @[TLB.scala:170:77] assign pma_checker__entries_T_123 = pma_checker__entries_WIRE_11[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_eff = pma_checker__entries_T_123; // @[TLB.scala:170:77] assign pma_checker__entries_T_124 = pma_checker__entries_WIRE_11[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_paa = pma_checker__entries_T_124; // @[TLB.scala:170:77] assign pma_checker__entries_T_125 = pma_checker__entries_WIRE_11[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_pal = pma_checker__entries_T_125; // @[TLB.scala:170:77] assign pma_checker__entries_T_126 = pma_checker__entries_WIRE_11[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_ppp = pma_checker__entries_T_126; // @[TLB.scala:170:77] assign pma_checker__entries_T_127 = pma_checker__entries_WIRE_11[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_pr = pma_checker__entries_T_127; // @[TLB.scala:170:77] assign pma_checker__entries_T_128 = pma_checker__entries_WIRE_11[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_px = pma_checker__entries_T_128; // @[TLB.scala:170:77] assign pma_checker__entries_T_129 = pma_checker__entries_WIRE_11[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_pw = pma_checker__entries_T_129; // @[TLB.scala:170:77] assign pma_checker__entries_T_130 = pma_checker__entries_WIRE_11[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_hr = pma_checker__entries_T_130; // @[TLB.scala:170:77] assign pma_checker__entries_T_131 = pma_checker__entries_WIRE_11[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_hx = pma_checker__entries_T_131; // @[TLB.scala:170:77] assign pma_checker__entries_T_132 = pma_checker__entries_WIRE_11[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_hw = pma_checker__entries_T_132; // @[TLB.scala:170:77] assign pma_checker__entries_T_133 = pma_checker__entries_WIRE_11[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_sr = pma_checker__entries_T_133; // @[TLB.scala:170:77] assign pma_checker__entries_T_134 = pma_checker__entries_WIRE_11[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_sx = pma_checker__entries_T_134; // @[TLB.scala:170:77] assign pma_checker__entries_T_135 = pma_checker__entries_WIRE_11[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_sw = pma_checker__entries_T_135; // @[TLB.scala:170:77] assign pma_checker__entries_T_136 = pma_checker__entries_WIRE_11[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_gf = pma_checker__entries_T_136; // @[TLB.scala:170:77] assign pma_checker__entries_T_137 = pma_checker__entries_WIRE_11[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_pf = pma_checker__entries_T_137; // @[TLB.scala:170:77] assign pma_checker__entries_T_138 = pma_checker__entries_WIRE_11[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_ae_stage2 = pma_checker__entries_T_138; // @[TLB.scala:170:77] assign pma_checker__entries_T_139 = pma_checker__entries_WIRE_11[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_ae_final = pma_checker__entries_T_139; // @[TLB.scala:170:77] assign pma_checker__entries_T_140 = pma_checker__entries_WIRE_11[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_ae_ptw = pma_checker__entries_T_140; // @[TLB.scala:170:77] assign pma_checker__entries_T_141 = pma_checker__entries_WIRE_11[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_g = pma_checker__entries_T_141; // @[TLB.scala:170:77] assign pma_checker__entries_T_142 = pma_checker__entries_WIRE_11[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_u = pma_checker__entries_T_142; // @[TLB.scala:170:77] assign pma_checker__entries_T_143 = pma_checker__entries_WIRE_11[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_10_ppn = pma_checker__entries_T_143; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_167; // @[TLB.scala:170:77] wire pma_checker__entries_T_166; // @[TLB.scala:170:77] wire pma_checker__entries_T_165; // @[TLB.scala:170:77] wire pma_checker__entries_T_164; // @[TLB.scala:170:77] wire pma_checker__entries_T_163; // @[TLB.scala:170:77] wire pma_checker__entries_T_162; // @[TLB.scala:170:77] wire pma_checker__entries_T_161; // @[TLB.scala:170:77] wire pma_checker__entries_T_160; // @[TLB.scala:170:77] wire pma_checker__entries_T_159; // @[TLB.scala:170:77] wire pma_checker__entries_T_158; // @[TLB.scala:170:77] wire pma_checker__entries_T_157; // @[TLB.scala:170:77] wire pma_checker__entries_T_156; // @[TLB.scala:170:77] wire pma_checker__entries_T_155; // @[TLB.scala:170:77] wire pma_checker__entries_T_154; // @[TLB.scala:170:77] wire pma_checker__entries_T_153; // @[TLB.scala:170:77] wire pma_checker__entries_T_152; // @[TLB.scala:170:77] wire pma_checker__entries_T_151; // @[TLB.scala:170:77] wire pma_checker__entries_T_150; // @[TLB.scala:170:77] wire pma_checker__entries_T_149; // @[TLB.scala:170:77] wire pma_checker__entries_T_148; // @[TLB.scala:170:77] wire pma_checker__entries_T_147; // @[TLB.scala:170:77] wire pma_checker__entries_T_146; // @[TLB.scala:170:77] wire pma_checker__entries_T_145; // @[TLB.scala:170:77] assign pma_checker__entries_T_145 = pma_checker__entries_WIRE_13[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_fragmented_superpage = pma_checker__entries_T_145; // @[TLB.scala:170:77] assign pma_checker__entries_T_146 = pma_checker__entries_WIRE_13[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_c = pma_checker__entries_T_146; // @[TLB.scala:170:77] assign pma_checker__entries_T_147 = pma_checker__entries_WIRE_13[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_eff = pma_checker__entries_T_147; // @[TLB.scala:170:77] assign pma_checker__entries_T_148 = pma_checker__entries_WIRE_13[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_paa = pma_checker__entries_T_148; // @[TLB.scala:170:77] assign pma_checker__entries_T_149 = pma_checker__entries_WIRE_13[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_pal = pma_checker__entries_T_149; // @[TLB.scala:170:77] assign pma_checker__entries_T_150 = pma_checker__entries_WIRE_13[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_ppp = pma_checker__entries_T_150; // @[TLB.scala:170:77] assign pma_checker__entries_T_151 = pma_checker__entries_WIRE_13[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_pr = pma_checker__entries_T_151; // @[TLB.scala:170:77] assign pma_checker__entries_T_152 = pma_checker__entries_WIRE_13[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_px = pma_checker__entries_T_152; // @[TLB.scala:170:77] assign pma_checker__entries_T_153 = pma_checker__entries_WIRE_13[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_pw = pma_checker__entries_T_153; // @[TLB.scala:170:77] assign pma_checker__entries_T_154 = pma_checker__entries_WIRE_13[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_hr = pma_checker__entries_T_154; // @[TLB.scala:170:77] assign pma_checker__entries_T_155 = pma_checker__entries_WIRE_13[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_hx = pma_checker__entries_T_155; // @[TLB.scala:170:77] assign pma_checker__entries_T_156 = pma_checker__entries_WIRE_13[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_hw = pma_checker__entries_T_156; // @[TLB.scala:170:77] assign pma_checker__entries_T_157 = pma_checker__entries_WIRE_13[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_sr = pma_checker__entries_T_157; // @[TLB.scala:170:77] assign pma_checker__entries_T_158 = pma_checker__entries_WIRE_13[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_sx = pma_checker__entries_T_158; // @[TLB.scala:170:77] assign pma_checker__entries_T_159 = pma_checker__entries_WIRE_13[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_sw = pma_checker__entries_T_159; // @[TLB.scala:170:77] assign pma_checker__entries_T_160 = pma_checker__entries_WIRE_13[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_gf = pma_checker__entries_T_160; // @[TLB.scala:170:77] assign pma_checker__entries_T_161 = pma_checker__entries_WIRE_13[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_pf = pma_checker__entries_T_161; // @[TLB.scala:170:77] assign pma_checker__entries_T_162 = pma_checker__entries_WIRE_13[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_ae_stage2 = pma_checker__entries_T_162; // @[TLB.scala:170:77] assign pma_checker__entries_T_163 = pma_checker__entries_WIRE_13[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_ae_final = pma_checker__entries_T_163; // @[TLB.scala:170:77] assign pma_checker__entries_T_164 = pma_checker__entries_WIRE_13[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_ae_ptw = pma_checker__entries_T_164; // @[TLB.scala:170:77] assign pma_checker__entries_T_165 = pma_checker__entries_WIRE_13[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_g = pma_checker__entries_T_165; // @[TLB.scala:170:77] assign pma_checker__entries_T_166 = pma_checker__entries_WIRE_13[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_u = pma_checker__entries_T_166; // @[TLB.scala:170:77] assign pma_checker__entries_T_167 = pma_checker__entries_WIRE_13[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_12_ppn = pma_checker__entries_T_167; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_191; // @[TLB.scala:170:77] wire pma_checker__entries_T_190; // @[TLB.scala:170:77] wire pma_checker__entries_T_189; // @[TLB.scala:170:77] wire pma_checker__entries_T_188; // @[TLB.scala:170:77] wire pma_checker__entries_T_187; // @[TLB.scala:170:77] wire pma_checker__entries_T_186; // @[TLB.scala:170:77] wire pma_checker__entries_T_185; // @[TLB.scala:170:77] wire pma_checker__entries_T_184; // @[TLB.scala:170:77] wire pma_checker__entries_T_183; // @[TLB.scala:170:77] wire pma_checker__entries_T_182; // @[TLB.scala:170:77] wire pma_checker__entries_T_181; // @[TLB.scala:170:77] wire pma_checker__entries_T_180; // @[TLB.scala:170:77] wire pma_checker__entries_T_179; // @[TLB.scala:170:77] wire pma_checker__entries_T_178; // @[TLB.scala:170:77] wire pma_checker__entries_T_177; // @[TLB.scala:170:77] wire pma_checker__entries_T_176; // @[TLB.scala:170:77] wire pma_checker__entries_T_175; // @[TLB.scala:170:77] wire pma_checker__entries_T_174; // @[TLB.scala:170:77] wire pma_checker__entries_T_173; // @[TLB.scala:170:77] wire pma_checker__entries_T_172; // @[TLB.scala:170:77] wire pma_checker__entries_T_171; // @[TLB.scala:170:77] wire pma_checker__entries_T_170; // @[TLB.scala:170:77] wire pma_checker__entries_T_169; // @[TLB.scala:170:77] assign pma_checker__entries_T_169 = pma_checker__entries_WIRE_15[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_fragmented_superpage = pma_checker__entries_T_169; // @[TLB.scala:170:77] assign pma_checker__entries_T_170 = pma_checker__entries_WIRE_15[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_c = pma_checker__entries_T_170; // @[TLB.scala:170:77] assign pma_checker__entries_T_171 = pma_checker__entries_WIRE_15[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_eff = pma_checker__entries_T_171; // @[TLB.scala:170:77] assign pma_checker__entries_T_172 = pma_checker__entries_WIRE_15[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_paa = pma_checker__entries_T_172; // @[TLB.scala:170:77] assign pma_checker__entries_T_173 = pma_checker__entries_WIRE_15[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_pal = pma_checker__entries_T_173; // @[TLB.scala:170:77] assign pma_checker__entries_T_174 = pma_checker__entries_WIRE_15[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_ppp = pma_checker__entries_T_174; // @[TLB.scala:170:77] assign pma_checker__entries_T_175 = pma_checker__entries_WIRE_15[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_pr = pma_checker__entries_T_175; // @[TLB.scala:170:77] assign pma_checker__entries_T_176 = pma_checker__entries_WIRE_15[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_px = pma_checker__entries_T_176; // @[TLB.scala:170:77] assign pma_checker__entries_T_177 = pma_checker__entries_WIRE_15[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_pw = pma_checker__entries_T_177; // @[TLB.scala:170:77] assign pma_checker__entries_T_178 = pma_checker__entries_WIRE_15[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_hr = pma_checker__entries_T_178; // @[TLB.scala:170:77] assign pma_checker__entries_T_179 = pma_checker__entries_WIRE_15[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_hx = pma_checker__entries_T_179; // @[TLB.scala:170:77] assign pma_checker__entries_T_180 = pma_checker__entries_WIRE_15[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_hw = pma_checker__entries_T_180; // @[TLB.scala:170:77] assign pma_checker__entries_T_181 = pma_checker__entries_WIRE_15[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_sr = pma_checker__entries_T_181; // @[TLB.scala:170:77] assign pma_checker__entries_T_182 = pma_checker__entries_WIRE_15[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_sx = pma_checker__entries_T_182; // @[TLB.scala:170:77] assign pma_checker__entries_T_183 = pma_checker__entries_WIRE_15[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_sw = pma_checker__entries_T_183; // @[TLB.scala:170:77] assign pma_checker__entries_T_184 = pma_checker__entries_WIRE_15[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_gf = pma_checker__entries_T_184; // @[TLB.scala:170:77] assign pma_checker__entries_T_185 = pma_checker__entries_WIRE_15[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_pf = pma_checker__entries_T_185; // @[TLB.scala:170:77] assign pma_checker__entries_T_186 = pma_checker__entries_WIRE_15[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_ae_stage2 = pma_checker__entries_T_186; // @[TLB.scala:170:77] assign pma_checker__entries_T_187 = pma_checker__entries_WIRE_15[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_ae_final = pma_checker__entries_T_187; // @[TLB.scala:170:77] assign pma_checker__entries_T_188 = pma_checker__entries_WIRE_15[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_ae_ptw = pma_checker__entries_T_188; // @[TLB.scala:170:77] assign pma_checker__entries_T_189 = pma_checker__entries_WIRE_15[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_g = pma_checker__entries_T_189; // @[TLB.scala:170:77] assign pma_checker__entries_T_190 = pma_checker__entries_WIRE_15[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_u = pma_checker__entries_T_190; // @[TLB.scala:170:77] assign pma_checker__entries_T_191 = pma_checker__entries_WIRE_15[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_14_ppn = pma_checker__entries_T_191; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_214; // @[TLB.scala:170:77] wire pma_checker__entries_T_213; // @[TLB.scala:170:77] wire pma_checker__entries_T_212; // @[TLB.scala:170:77] wire pma_checker__entries_T_211; // @[TLB.scala:170:77] wire pma_checker__entries_T_210; // @[TLB.scala:170:77] wire pma_checker__entries_T_209; // @[TLB.scala:170:77] wire pma_checker__entries_T_208; // @[TLB.scala:170:77] wire pma_checker__entries_T_207; // @[TLB.scala:170:77] wire pma_checker__entries_T_206; // @[TLB.scala:170:77] wire pma_checker__entries_T_205; // @[TLB.scala:170:77] wire pma_checker__entries_T_204; // @[TLB.scala:170:77] wire pma_checker__entries_T_203; // @[TLB.scala:170:77] wire pma_checker__entries_T_202; // @[TLB.scala:170:77] wire pma_checker__entries_T_201; // @[TLB.scala:170:77] wire pma_checker__entries_T_200; // @[TLB.scala:170:77] wire pma_checker__entries_T_199; // @[TLB.scala:170:77] wire pma_checker__entries_T_198; // @[TLB.scala:170:77] wire pma_checker__entries_T_197; // @[TLB.scala:170:77] wire pma_checker__entries_T_196; // @[TLB.scala:170:77] wire pma_checker__entries_T_195; // @[TLB.scala:170:77] wire pma_checker__entries_T_194; // @[TLB.scala:170:77] wire pma_checker__entries_T_193; // @[TLB.scala:170:77] wire pma_checker__entries_T_192; // @[TLB.scala:170:77] assign pma_checker__entries_T_192 = pma_checker__entries_WIRE_17[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_fragmented_superpage = pma_checker__entries_T_192; // @[TLB.scala:170:77] assign pma_checker__entries_T_193 = pma_checker__entries_WIRE_17[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_c = pma_checker__entries_T_193; // @[TLB.scala:170:77] assign pma_checker__entries_T_194 = pma_checker__entries_WIRE_17[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_eff = pma_checker__entries_T_194; // @[TLB.scala:170:77] assign pma_checker__entries_T_195 = pma_checker__entries_WIRE_17[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_paa = pma_checker__entries_T_195; // @[TLB.scala:170:77] assign pma_checker__entries_T_196 = pma_checker__entries_WIRE_17[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_pal = pma_checker__entries_T_196; // @[TLB.scala:170:77] assign pma_checker__entries_T_197 = pma_checker__entries_WIRE_17[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_ppp = pma_checker__entries_T_197; // @[TLB.scala:170:77] assign pma_checker__entries_T_198 = pma_checker__entries_WIRE_17[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_pr = pma_checker__entries_T_198; // @[TLB.scala:170:77] assign pma_checker__entries_T_199 = pma_checker__entries_WIRE_17[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_px = pma_checker__entries_T_199; // @[TLB.scala:170:77] assign pma_checker__entries_T_200 = pma_checker__entries_WIRE_17[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_pw = pma_checker__entries_T_200; // @[TLB.scala:170:77] assign pma_checker__entries_T_201 = pma_checker__entries_WIRE_17[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_hr = pma_checker__entries_T_201; // @[TLB.scala:170:77] assign pma_checker__entries_T_202 = pma_checker__entries_WIRE_17[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_hx = pma_checker__entries_T_202; // @[TLB.scala:170:77] assign pma_checker__entries_T_203 = pma_checker__entries_WIRE_17[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_hw = pma_checker__entries_T_203; // @[TLB.scala:170:77] assign pma_checker__entries_T_204 = pma_checker__entries_WIRE_17[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_sr = pma_checker__entries_T_204; // @[TLB.scala:170:77] assign pma_checker__entries_T_205 = pma_checker__entries_WIRE_17[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_sx = pma_checker__entries_T_205; // @[TLB.scala:170:77] assign pma_checker__entries_T_206 = pma_checker__entries_WIRE_17[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_sw = pma_checker__entries_T_206; // @[TLB.scala:170:77] assign pma_checker__entries_T_207 = pma_checker__entries_WIRE_17[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_gf = pma_checker__entries_T_207; // @[TLB.scala:170:77] assign pma_checker__entries_T_208 = pma_checker__entries_WIRE_17[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_pf = pma_checker__entries_T_208; // @[TLB.scala:170:77] assign pma_checker__entries_T_209 = pma_checker__entries_WIRE_17[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_ae_stage2 = pma_checker__entries_T_209; // @[TLB.scala:170:77] assign pma_checker__entries_T_210 = pma_checker__entries_WIRE_17[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_ae_final = pma_checker__entries_T_210; // @[TLB.scala:170:77] assign pma_checker__entries_T_211 = pma_checker__entries_WIRE_17[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_ae_ptw = pma_checker__entries_T_211; // @[TLB.scala:170:77] assign pma_checker__entries_T_212 = pma_checker__entries_WIRE_17[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_g = pma_checker__entries_T_212; // @[TLB.scala:170:77] assign pma_checker__entries_T_213 = pma_checker__entries_WIRE_17[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_u = pma_checker__entries_T_213; // @[TLB.scala:170:77] assign pma_checker__entries_T_214 = pma_checker__entries_WIRE_17[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_16_ppn = pma_checker__entries_T_214; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_237; // @[TLB.scala:170:77] wire pma_checker__entries_T_236; // @[TLB.scala:170:77] wire pma_checker__entries_T_235; // @[TLB.scala:170:77] wire pma_checker__entries_T_234; // @[TLB.scala:170:77] wire pma_checker__entries_T_233; // @[TLB.scala:170:77] wire pma_checker__entries_T_232; // @[TLB.scala:170:77] wire pma_checker__entries_T_231; // @[TLB.scala:170:77] wire pma_checker__entries_T_230; // @[TLB.scala:170:77] wire pma_checker__entries_T_229; // @[TLB.scala:170:77] wire pma_checker__entries_T_228; // @[TLB.scala:170:77] wire pma_checker__entries_T_227; // @[TLB.scala:170:77] wire pma_checker__entries_T_226; // @[TLB.scala:170:77] wire pma_checker__entries_T_225; // @[TLB.scala:170:77] wire pma_checker__entries_T_224; // @[TLB.scala:170:77] wire pma_checker__entries_T_223; // @[TLB.scala:170:77] wire pma_checker__entries_T_222; // @[TLB.scala:170:77] wire pma_checker__entries_T_221; // @[TLB.scala:170:77] wire pma_checker__entries_T_220; // @[TLB.scala:170:77] wire pma_checker__entries_T_219; // @[TLB.scala:170:77] wire pma_checker__entries_T_218; // @[TLB.scala:170:77] wire pma_checker__entries_T_217; // @[TLB.scala:170:77] wire pma_checker__entries_T_216; // @[TLB.scala:170:77] wire pma_checker__entries_T_215; // @[TLB.scala:170:77] assign pma_checker__entries_T_215 = pma_checker__entries_WIRE_19[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_fragmented_superpage = pma_checker__entries_T_215; // @[TLB.scala:170:77] assign pma_checker__entries_T_216 = pma_checker__entries_WIRE_19[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_c = pma_checker__entries_T_216; // @[TLB.scala:170:77] assign pma_checker__entries_T_217 = pma_checker__entries_WIRE_19[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_eff = pma_checker__entries_T_217; // @[TLB.scala:170:77] assign pma_checker__entries_T_218 = pma_checker__entries_WIRE_19[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_paa = pma_checker__entries_T_218; // @[TLB.scala:170:77] assign pma_checker__entries_T_219 = pma_checker__entries_WIRE_19[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_pal = pma_checker__entries_T_219; // @[TLB.scala:170:77] assign pma_checker__entries_T_220 = pma_checker__entries_WIRE_19[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_ppp = pma_checker__entries_T_220; // @[TLB.scala:170:77] assign pma_checker__entries_T_221 = pma_checker__entries_WIRE_19[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_pr = pma_checker__entries_T_221; // @[TLB.scala:170:77] assign pma_checker__entries_T_222 = pma_checker__entries_WIRE_19[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_px = pma_checker__entries_T_222; // @[TLB.scala:170:77] assign pma_checker__entries_T_223 = pma_checker__entries_WIRE_19[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_pw = pma_checker__entries_T_223; // @[TLB.scala:170:77] assign pma_checker__entries_T_224 = pma_checker__entries_WIRE_19[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_hr = pma_checker__entries_T_224; // @[TLB.scala:170:77] assign pma_checker__entries_T_225 = pma_checker__entries_WIRE_19[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_hx = pma_checker__entries_T_225; // @[TLB.scala:170:77] assign pma_checker__entries_T_226 = pma_checker__entries_WIRE_19[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_hw = pma_checker__entries_T_226; // @[TLB.scala:170:77] assign pma_checker__entries_T_227 = pma_checker__entries_WIRE_19[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_sr = pma_checker__entries_T_227; // @[TLB.scala:170:77] assign pma_checker__entries_T_228 = pma_checker__entries_WIRE_19[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_sx = pma_checker__entries_T_228; // @[TLB.scala:170:77] assign pma_checker__entries_T_229 = pma_checker__entries_WIRE_19[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_sw = pma_checker__entries_T_229; // @[TLB.scala:170:77] assign pma_checker__entries_T_230 = pma_checker__entries_WIRE_19[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_gf = pma_checker__entries_T_230; // @[TLB.scala:170:77] assign pma_checker__entries_T_231 = pma_checker__entries_WIRE_19[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_pf = pma_checker__entries_T_231; // @[TLB.scala:170:77] assign pma_checker__entries_T_232 = pma_checker__entries_WIRE_19[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_ae_stage2 = pma_checker__entries_T_232; // @[TLB.scala:170:77] assign pma_checker__entries_T_233 = pma_checker__entries_WIRE_19[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_ae_final = pma_checker__entries_T_233; // @[TLB.scala:170:77] assign pma_checker__entries_T_234 = pma_checker__entries_WIRE_19[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_ae_ptw = pma_checker__entries_T_234; // @[TLB.scala:170:77] assign pma_checker__entries_T_235 = pma_checker__entries_WIRE_19[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_g = pma_checker__entries_T_235; // @[TLB.scala:170:77] assign pma_checker__entries_T_236 = pma_checker__entries_WIRE_19[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_u = pma_checker__entries_T_236; // @[TLB.scala:170:77] assign pma_checker__entries_T_237 = pma_checker__entries_WIRE_19[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_18_ppn = pma_checker__entries_T_237; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_260; // @[TLB.scala:170:77] wire pma_checker__entries_T_259; // @[TLB.scala:170:77] wire pma_checker__entries_T_258; // @[TLB.scala:170:77] wire pma_checker__entries_T_257; // @[TLB.scala:170:77] wire pma_checker__entries_T_256; // @[TLB.scala:170:77] wire pma_checker__entries_T_255; // @[TLB.scala:170:77] wire pma_checker__entries_T_254; // @[TLB.scala:170:77] wire pma_checker__entries_T_253; // @[TLB.scala:170:77] wire pma_checker__entries_T_252; // @[TLB.scala:170:77] wire pma_checker__entries_T_251; // @[TLB.scala:170:77] wire pma_checker__entries_T_250; // @[TLB.scala:170:77] wire pma_checker__entries_T_249; // @[TLB.scala:170:77] wire pma_checker__entries_T_248; // @[TLB.scala:170:77] wire pma_checker__entries_T_247; // @[TLB.scala:170:77] wire pma_checker__entries_T_246; // @[TLB.scala:170:77] wire pma_checker__entries_T_245; // @[TLB.scala:170:77] wire pma_checker__entries_T_244; // @[TLB.scala:170:77] wire pma_checker__entries_T_243; // @[TLB.scala:170:77] wire pma_checker__entries_T_242; // @[TLB.scala:170:77] wire pma_checker__entries_T_241; // @[TLB.scala:170:77] wire pma_checker__entries_T_240; // @[TLB.scala:170:77] wire pma_checker__entries_T_239; // @[TLB.scala:170:77] wire pma_checker__entries_T_238; // @[TLB.scala:170:77] assign pma_checker__entries_T_238 = pma_checker__entries_WIRE_21[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_fragmented_superpage = pma_checker__entries_T_238; // @[TLB.scala:170:77] assign pma_checker__entries_T_239 = pma_checker__entries_WIRE_21[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_c = pma_checker__entries_T_239; // @[TLB.scala:170:77] assign pma_checker__entries_T_240 = pma_checker__entries_WIRE_21[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_eff = pma_checker__entries_T_240; // @[TLB.scala:170:77] assign pma_checker__entries_T_241 = pma_checker__entries_WIRE_21[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_paa = pma_checker__entries_T_241; // @[TLB.scala:170:77] assign pma_checker__entries_T_242 = pma_checker__entries_WIRE_21[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_pal = pma_checker__entries_T_242; // @[TLB.scala:170:77] assign pma_checker__entries_T_243 = pma_checker__entries_WIRE_21[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_ppp = pma_checker__entries_T_243; // @[TLB.scala:170:77] assign pma_checker__entries_T_244 = pma_checker__entries_WIRE_21[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_pr = pma_checker__entries_T_244; // @[TLB.scala:170:77] assign pma_checker__entries_T_245 = pma_checker__entries_WIRE_21[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_px = pma_checker__entries_T_245; // @[TLB.scala:170:77] assign pma_checker__entries_T_246 = pma_checker__entries_WIRE_21[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_pw = pma_checker__entries_T_246; // @[TLB.scala:170:77] assign pma_checker__entries_T_247 = pma_checker__entries_WIRE_21[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_hr = pma_checker__entries_T_247; // @[TLB.scala:170:77] assign pma_checker__entries_T_248 = pma_checker__entries_WIRE_21[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_hx = pma_checker__entries_T_248; // @[TLB.scala:170:77] assign pma_checker__entries_T_249 = pma_checker__entries_WIRE_21[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_hw = pma_checker__entries_T_249; // @[TLB.scala:170:77] assign pma_checker__entries_T_250 = pma_checker__entries_WIRE_21[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_sr = pma_checker__entries_T_250; // @[TLB.scala:170:77] assign pma_checker__entries_T_251 = pma_checker__entries_WIRE_21[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_sx = pma_checker__entries_T_251; // @[TLB.scala:170:77] assign pma_checker__entries_T_252 = pma_checker__entries_WIRE_21[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_sw = pma_checker__entries_T_252; // @[TLB.scala:170:77] assign pma_checker__entries_T_253 = pma_checker__entries_WIRE_21[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_gf = pma_checker__entries_T_253; // @[TLB.scala:170:77] assign pma_checker__entries_T_254 = pma_checker__entries_WIRE_21[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_pf = pma_checker__entries_T_254; // @[TLB.scala:170:77] assign pma_checker__entries_T_255 = pma_checker__entries_WIRE_21[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_ae_stage2 = pma_checker__entries_T_255; // @[TLB.scala:170:77] assign pma_checker__entries_T_256 = pma_checker__entries_WIRE_21[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_ae_final = pma_checker__entries_T_256; // @[TLB.scala:170:77] assign pma_checker__entries_T_257 = pma_checker__entries_WIRE_21[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_ae_ptw = pma_checker__entries_T_257; // @[TLB.scala:170:77] assign pma_checker__entries_T_258 = pma_checker__entries_WIRE_21[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_g = pma_checker__entries_T_258; // @[TLB.scala:170:77] assign pma_checker__entries_T_259 = pma_checker__entries_WIRE_21[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_u = pma_checker__entries_T_259; // @[TLB.scala:170:77] assign pma_checker__entries_T_260 = pma_checker__entries_WIRE_21[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_20_ppn = pma_checker__entries_T_260; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_283; // @[TLB.scala:170:77] wire pma_checker__entries_T_282; // @[TLB.scala:170:77] wire pma_checker__entries_T_281; // @[TLB.scala:170:77] wire pma_checker__entries_T_280; // @[TLB.scala:170:77] wire pma_checker__entries_T_279; // @[TLB.scala:170:77] wire pma_checker__entries_T_278; // @[TLB.scala:170:77] wire pma_checker__entries_T_277; // @[TLB.scala:170:77] wire pma_checker__entries_T_276; // @[TLB.scala:170:77] wire pma_checker__entries_T_275; // @[TLB.scala:170:77] wire pma_checker__entries_T_274; // @[TLB.scala:170:77] wire pma_checker__entries_T_273; // @[TLB.scala:170:77] wire pma_checker__entries_T_272; // @[TLB.scala:170:77] wire pma_checker__entries_T_271; // @[TLB.scala:170:77] wire pma_checker__entries_T_270; // @[TLB.scala:170:77] wire pma_checker__entries_T_269; // @[TLB.scala:170:77] wire pma_checker__entries_T_268; // @[TLB.scala:170:77] wire pma_checker__entries_T_267; // @[TLB.scala:170:77] wire pma_checker__entries_T_266; // @[TLB.scala:170:77] wire pma_checker__entries_T_265; // @[TLB.scala:170:77] wire pma_checker__entries_T_264; // @[TLB.scala:170:77] wire pma_checker__entries_T_263; // @[TLB.scala:170:77] wire pma_checker__entries_T_262; // @[TLB.scala:170:77] wire pma_checker__entries_T_261; // @[TLB.scala:170:77] assign pma_checker__entries_T_261 = pma_checker__entries_WIRE_23[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_fragmented_superpage = pma_checker__entries_T_261; // @[TLB.scala:170:77] assign pma_checker__entries_T_262 = pma_checker__entries_WIRE_23[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_c = pma_checker__entries_T_262; // @[TLB.scala:170:77] assign pma_checker__entries_T_263 = pma_checker__entries_WIRE_23[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_eff = pma_checker__entries_T_263; // @[TLB.scala:170:77] assign pma_checker__entries_T_264 = pma_checker__entries_WIRE_23[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_paa = pma_checker__entries_T_264; // @[TLB.scala:170:77] assign pma_checker__entries_T_265 = pma_checker__entries_WIRE_23[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_pal = pma_checker__entries_T_265; // @[TLB.scala:170:77] assign pma_checker__entries_T_266 = pma_checker__entries_WIRE_23[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_ppp = pma_checker__entries_T_266; // @[TLB.scala:170:77] assign pma_checker__entries_T_267 = pma_checker__entries_WIRE_23[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_pr = pma_checker__entries_T_267; // @[TLB.scala:170:77] assign pma_checker__entries_T_268 = pma_checker__entries_WIRE_23[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_px = pma_checker__entries_T_268; // @[TLB.scala:170:77] assign pma_checker__entries_T_269 = pma_checker__entries_WIRE_23[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_pw = pma_checker__entries_T_269; // @[TLB.scala:170:77] assign pma_checker__entries_T_270 = pma_checker__entries_WIRE_23[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_hr = pma_checker__entries_T_270; // @[TLB.scala:170:77] assign pma_checker__entries_T_271 = pma_checker__entries_WIRE_23[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_hx = pma_checker__entries_T_271; // @[TLB.scala:170:77] assign pma_checker__entries_T_272 = pma_checker__entries_WIRE_23[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_hw = pma_checker__entries_T_272; // @[TLB.scala:170:77] assign pma_checker__entries_T_273 = pma_checker__entries_WIRE_23[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_sr = pma_checker__entries_T_273; // @[TLB.scala:170:77] assign pma_checker__entries_T_274 = pma_checker__entries_WIRE_23[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_sx = pma_checker__entries_T_274; // @[TLB.scala:170:77] assign pma_checker__entries_T_275 = pma_checker__entries_WIRE_23[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_sw = pma_checker__entries_T_275; // @[TLB.scala:170:77] assign pma_checker__entries_T_276 = pma_checker__entries_WIRE_23[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_gf = pma_checker__entries_T_276; // @[TLB.scala:170:77] assign pma_checker__entries_T_277 = pma_checker__entries_WIRE_23[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_pf = pma_checker__entries_T_277; // @[TLB.scala:170:77] assign pma_checker__entries_T_278 = pma_checker__entries_WIRE_23[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_ae_stage2 = pma_checker__entries_T_278; // @[TLB.scala:170:77] assign pma_checker__entries_T_279 = pma_checker__entries_WIRE_23[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_ae_final = pma_checker__entries_T_279; // @[TLB.scala:170:77] assign pma_checker__entries_T_280 = pma_checker__entries_WIRE_23[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_ae_ptw = pma_checker__entries_T_280; // @[TLB.scala:170:77] assign pma_checker__entries_T_281 = pma_checker__entries_WIRE_23[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_g = pma_checker__entries_T_281; // @[TLB.scala:170:77] assign pma_checker__entries_T_282 = pma_checker__entries_WIRE_23[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_u = pma_checker__entries_T_282; // @[TLB.scala:170:77] assign pma_checker__entries_T_283 = pma_checker__entries_WIRE_23[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_22_ppn = pma_checker__entries_T_283; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_306; // @[TLB.scala:170:77] wire pma_checker__entries_T_305; // @[TLB.scala:170:77] wire pma_checker__entries_T_304; // @[TLB.scala:170:77] wire pma_checker__entries_T_303; // @[TLB.scala:170:77] wire pma_checker__entries_T_302; // @[TLB.scala:170:77] wire pma_checker__entries_T_301; // @[TLB.scala:170:77] wire pma_checker__entries_T_300; // @[TLB.scala:170:77] wire pma_checker__entries_T_299; // @[TLB.scala:170:77] wire pma_checker__entries_T_298; // @[TLB.scala:170:77] wire pma_checker__entries_T_297; // @[TLB.scala:170:77] wire pma_checker__entries_T_296; // @[TLB.scala:170:77] wire pma_checker__entries_T_295; // @[TLB.scala:170:77] wire pma_checker__entries_T_294; // @[TLB.scala:170:77] wire pma_checker__entries_T_293; // @[TLB.scala:170:77] wire pma_checker__entries_T_292; // @[TLB.scala:170:77] wire pma_checker__entries_T_291; // @[TLB.scala:170:77] wire pma_checker__entries_T_290; // @[TLB.scala:170:77] wire pma_checker__entries_T_289; // @[TLB.scala:170:77] wire pma_checker__entries_T_288; // @[TLB.scala:170:77] wire pma_checker__entries_T_287; // @[TLB.scala:170:77] wire pma_checker__entries_T_286; // @[TLB.scala:170:77] wire pma_checker__entries_T_285; // @[TLB.scala:170:77] wire pma_checker__entries_T_284; // @[TLB.scala:170:77] assign pma_checker__entries_T_284 = pma_checker__entries_WIRE_25[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_fragmented_superpage = pma_checker__entries_T_284; // @[TLB.scala:170:77] assign pma_checker__entries_T_285 = pma_checker__entries_WIRE_25[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_c = pma_checker__entries_T_285; // @[TLB.scala:170:77] assign pma_checker__entries_T_286 = pma_checker__entries_WIRE_25[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_eff = pma_checker__entries_T_286; // @[TLB.scala:170:77] assign pma_checker__entries_T_287 = pma_checker__entries_WIRE_25[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_paa = pma_checker__entries_T_287; // @[TLB.scala:170:77] assign pma_checker__entries_T_288 = pma_checker__entries_WIRE_25[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_pal = pma_checker__entries_T_288; // @[TLB.scala:170:77] assign pma_checker__entries_T_289 = pma_checker__entries_WIRE_25[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_ppp = pma_checker__entries_T_289; // @[TLB.scala:170:77] assign pma_checker__entries_T_290 = pma_checker__entries_WIRE_25[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_pr = pma_checker__entries_T_290; // @[TLB.scala:170:77] assign pma_checker__entries_T_291 = pma_checker__entries_WIRE_25[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_px = pma_checker__entries_T_291; // @[TLB.scala:170:77] assign pma_checker__entries_T_292 = pma_checker__entries_WIRE_25[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_pw = pma_checker__entries_T_292; // @[TLB.scala:170:77] assign pma_checker__entries_T_293 = pma_checker__entries_WIRE_25[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_hr = pma_checker__entries_T_293; // @[TLB.scala:170:77] assign pma_checker__entries_T_294 = pma_checker__entries_WIRE_25[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_hx = pma_checker__entries_T_294; // @[TLB.scala:170:77] assign pma_checker__entries_T_295 = pma_checker__entries_WIRE_25[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_hw = pma_checker__entries_T_295; // @[TLB.scala:170:77] assign pma_checker__entries_T_296 = pma_checker__entries_WIRE_25[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_sr = pma_checker__entries_T_296; // @[TLB.scala:170:77] assign pma_checker__entries_T_297 = pma_checker__entries_WIRE_25[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_sx = pma_checker__entries_T_297; // @[TLB.scala:170:77] assign pma_checker__entries_T_298 = pma_checker__entries_WIRE_25[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_sw = pma_checker__entries_T_298; // @[TLB.scala:170:77] assign pma_checker__entries_T_299 = pma_checker__entries_WIRE_25[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_gf = pma_checker__entries_T_299; // @[TLB.scala:170:77] assign pma_checker__entries_T_300 = pma_checker__entries_WIRE_25[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_pf = pma_checker__entries_T_300; // @[TLB.scala:170:77] assign pma_checker__entries_T_301 = pma_checker__entries_WIRE_25[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_ae_stage2 = pma_checker__entries_T_301; // @[TLB.scala:170:77] assign pma_checker__entries_T_302 = pma_checker__entries_WIRE_25[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_ae_final = pma_checker__entries_T_302; // @[TLB.scala:170:77] assign pma_checker__entries_T_303 = pma_checker__entries_WIRE_25[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_ae_ptw = pma_checker__entries_T_303; // @[TLB.scala:170:77] assign pma_checker__entries_T_304 = pma_checker__entries_WIRE_25[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_g = pma_checker__entries_T_304; // @[TLB.scala:170:77] assign pma_checker__entries_T_305 = pma_checker__entries_WIRE_25[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_u = pma_checker__entries_T_305; // @[TLB.scala:170:77] assign pma_checker__entries_T_306 = pma_checker__entries_WIRE_25[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_24_ppn = pma_checker__entries_T_306; // @[TLB.scala:170:77] wire [19:0] pma_checker__ppn_T_1 = pma_checker_vpn[19:0]; // @[TLB.scala:335:30, :502:125] wire [19:0] pma_checker__ppn_T_15 = pma_checker__ppn_T_1; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_28 = pma_checker__ppn_T_15; // @[Mux.scala:30:73] wire [19:0] pma_checker_ppn = pma_checker__ppn_T_28; // @[Mux.scala:30:73] wire [1:0] pma_checker_ptw_ae_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_ae_ptw, _pma_checker_entries_barrier_1_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ptw_ae_array_lo_lo = {pma_checker_ptw_ae_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_ptw_ae_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_ae_ptw, _pma_checker_entries_barrier_4_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ptw_ae_array_lo_hi = {pma_checker_ptw_ae_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_ptw_ae_array_lo = {pma_checker_ptw_ae_array_lo_hi, pma_checker_ptw_ae_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_ptw_ae_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_ae_ptw, _pma_checker_entries_barrier_7_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ptw_ae_array_hi_lo = {pma_checker_ptw_ae_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_ptw_ae_array_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_ae_ptw, _pma_checker_entries_barrier_9_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_ptw_ae_array_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_ae_ptw, _pma_checker_entries_barrier_11_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_ptw_ae_array_hi_hi = {pma_checker_ptw_ae_array_hi_hi_hi, pma_checker_ptw_ae_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_ptw_ae_array_hi = {pma_checker_ptw_ae_array_hi_hi, pma_checker_ptw_ae_array_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__ptw_ae_array_T = {pma_checker_ptw_ae_array_hi, pma_checker_ptw_ae_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker_ptw_ae_array = {1'h0, pma_checker__ptw_ae_array_T}; // @[package.scala:45:27] wire [1:0] pma_checker_final_ae_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_ae_final, _pma_checker_entries_barrier_1_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_final_ae_array_lo_lo = {pma_checker_final_ae_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_final_ae_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_ae_final, _pma_checker_entries_barrier_4_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_final_ae_array_lo_hi = {pma_checker_final_ae_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_final_ae_array_lo = {pma_checker_final_ae_array_lo_hi, pma_checker_final_ae_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_final_ae_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_ae_final, _pma_checker_entries_barrier_7_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_final_ae_array_hi_lo = {pma_checker_final_ae_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_final_ae_array_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_ae_final, _pma_checker_entries_barrier_9_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_final_ae_array_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_ae_final, _pma_checker_entries_barrier_11_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_final_ae_array_hi_hi = {pma_checker_final_ae_array_hi_hi_hi, pma_checker_final_ae_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_final_ae_array_hi = {pma_checker_final_ae_array_hi_hi, pma_checker_final_ae_array_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__final_ae_array_T = {pma_checker_final_ae_array_hi, pma_checker_final_ae_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker_final_ae_array = {1'h0, pma_checker__final_ae_array_T}; // @[package.scala:45:27] wire [1:0] pma_checker_ptw_pf_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_pf, _pma_checker_entries_barrier_1_io_y_pf}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ptw_pf_array_lo_lo = {pma_checker_ptw_pf_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_pf}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_ptw_pf_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_pf, _pma_checker_entries_barrier_4_io_y_pf}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ptw_pf_array_lo_hi = {pma_checker_ptw_pf_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_pf}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_ptw_pf_array_lo = {pma_checker_ptw_pf_array_lo_hi, pma_checker_ptw_pf_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_ptw_pf_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_pf, _pma_checker_entries_barrier_7_io_y_pf}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ptw_pf_array_hi_lo = {pma_checker_ptw_pf_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_pf}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_ptw_pf_array_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_pf, _pma_checker_entries_barrier_9_io_y_pf}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_ptw_pf_array_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_pf, _pma_checker_entries_barrier_11_io_y_pf}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_ptw_pf_array_hi_hi = {pma_checker_ptw_pf_array_hi_hi_hi, pma_checker_ptw_pf_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_ptw_pf_array_hi = {pma_checker_ptw_pf_array_hi_hi, pma_checker_ptw_pf_array_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__ptw_pf_array_T = {pma_checker_ptw_pf_array_hi, pma_checker_ptw_pf_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker_ptw_pf_array = {1'h0, pma_checker__ptw_pf_array_T}; // @[package.scala:45:27] wire [1:0] pma_checker_ptw_gf_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_gf, _pma_checker_entries_barrier_1_io_y_gf}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ptw_gf_array_lo_lo = {pma_checker_ptw_gf_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_gf}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_ptw_gf_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_gf, _pma_checker_entries_barrier_4_io_y_gf}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ptw_gf_array_lo_hi = {pma_checker_ptw_gf_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_gf}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_ptw_gf_array_lo = {pma_checker_ptw_gf_array_lo_hi, pma_checker_ptw_gf_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_ptw_gf_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_gf, _pma_checker_entries_barrier_7_io_y_gf}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ptw_gf_array_hi_lo = {pma_checker_ptw_gf_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_gf}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_ptw_gf_array_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_gf, _pma_checker_entries_barrier_9_io_y_gf}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_ptw_gf_array_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_gf, _pma_checker_entries_barrier_11_io_y_gf}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_ptw_gf_array_hi_hi = {pma_checker_ptw_gf_array_hi_hi_hi, pma_checker_ptw_gf_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_ptw_gf_array_hi = {pma_checker_ptw_gf_array_hi_hi, pma_checker_ptw_gf_array_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__ptw_gf_array_T = {pma_checker_ptw_gf_array_hi, pma_checker_ptw_gf_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker_ptw_gf_array = {1'h0, pma_checker__ptw_gf_array_T}; // @[package.scala:45:27] wire [13:0] pma_checker__gf_ld_array_T_3 = pma_checker_ptw_gf_array; // @[TLB.scala:509:25, :600:82] wire [13:0] pma_checker__gf_st_array_T_2 = pma_checker_ptw_gf_array; // @[TLB.scala:509:25, :601:63] wire [13:0] pma_checker__gf_inst_array_T_1 = pma_checker_ptw_gf_array; // @[TLB.scala:509:25, :602:46] wire pma_checker__priv_rw_ok_T = ~pma_checker_priv_s; // @[TLB.scala:370:20, :513:24] wire pma_checker__priv_rw_ok_T_1 = pma_checker__priv_rw_ok_T; // @[TLB.scala:513:{24,32}] wire [1:0] _GEN_5 = {_pma_checker_entries_barrier_2_io_y_u, _pma_checker_entries_barrier_1_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_priv_rw_ok_lo_lo_hi; // @[package.scala:45:27] assign pma_checker_priv_rw_ok_lo_lo_hi = _GEN_5; // @[package.scala:45:27] wire [1:0] pma_checker_priv_rw_ok_lo_lo_hi_1; // @[package.scala:45:27] assign pma_checker_priv_rw_ok_lo_lo_hi_1 = _GEN_5; // @[package.scala:45:27] wire [1:0] pma_checker_priv_x_ok_lo_lo_hi; // @[package.scala:45:27] assign pma_checker_priv_x_ok_lo_lo_hi = _GEN_5; // @[package.scala:45:27] wire [1:0] pma_checker_priv_x_ok_lo_lo_hi_1; // @[package.scala:45:27] assign pma_checker_priv_x_ok_lo_lo_hi_1 = _GEN_5; // @[package.scala:45:27] wire [2:0] pma_checker_priv_rw_ok_lo_lo = {pma_checker_priv_rw_ok_lo_lo_hi, _pma_checker_entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_6 = {_pma_checker_entries_barrier_5_io_y_u, _pma_checker_entries_barrier_4_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_priv_rw_ok_lo_hi_hi; // @[package.scala:45:27] assign pma_checker_priv_rw_ok_lo_hi_hi = _GEN_6; // @[package.scala:45:27] wire [1:0] pma_checker_priv_rw_ok_lo_hi_hi_1; // @[package.scala:45:27] assign pma_checker_priv_rw_ok_lo_hi_hi_1 = _GEN_6; // @[package.scala:45:27] wire [1:0] pma_checker_priv_x_ok_lo_hi_hi; // @[package.scala:45:27] assign pma_checker_priv_x_ok_lo_hi_hi = _GEN_6; // @[package.scala:45:27] wire [1:0] pma_checker_priv_x_ok_lo_hi_hi_1; // @[package.scala:45:27] assign pma_checker_priv_x_ok_lo_hi_hi_1 = _GEN_6; // @[package.scala:45:27] wire [2:0] pma_checker_priv_rw_ok_lo_hi = {pma_checker_priv_rw_ok_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_priv_rw_ok_lo = {pma_checker_priv_rw_ok_lo_hi, pma_checker_priv_rw_ok_lo_lo}; // @[package.scala:45:27] wire [1:0] _GEN_7 = {_pma_checker_entries_barrier_8_io_y_u, _pma_checker_entries_barrier_7_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_priv_rw_ok_hi_lo_hi; // @[package.scala:45:27] assign pma_checker_priv_rw_ok_hi_lo_hi = _GEN_7; // @[package.scala:45:27] wire [1:0] pma_checker_priv_rw_ok_hi_lo_hi_1; // @[package.scala:45:27] assign pma_checker_priv_rw_ok_hi_lo_hi_1 = _GEN_7; // @[package.scala:45:27] wire [1:0] pma_checker_priv_x_ok_hi_lo_hi; // @[package.scala:45:27] assign pma_checker_priv_x_ok_hi_lo_hi = _GEN_7; // @[package.scala:45:27] wire [1:0] pma_checker_priv_x_ok_hi_lo_hi_1; // @[package.scala:45:27] assign pma_checker_priv_x_ok_hi_lo_hi_1 = _GEN_7; // @[package.scala:45:27] wire [2:0] pma_checker_priv_rw_ok_hi_lo = {pma_checker_priv_rw_ok_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_8 = {_pma_checker_entries_barrier_10_io_y_u, _pma_checker_entries_barrier_9_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_priv_rw_ok_hi_hi_lo; // @[package.scala:45:27] assign pma_checker_priv_rw_ok_hi_hi_lo = _GEN_8; // @[package.scala:45:27] wire [1:0] pma_checker_priv_rw_ok_hi_hi_lo_1; // @[package.scala:45:27] assign pma_checker_priv_rw_ok_hi_hi_lo_1 = _GEN_8; // @[package.scala:45:27] wire [1:0] pma_checker_priv_x_ok_hi_hi_lo; // @[package.scala:45:27] assign pma_checker_priv_x_ok_hi_hi_lo = _GEN_8; // @[package.scala:45:27] wire [1:0] pma_checker_priv_x_ok_hi_hi_lo_1; // @[package.scala:45:27] assign pma_checker_priv_x_ok_hi_hi_lo_1 = _GEN_8; // @[package.scala:45:27] wire [1:0] _GEN_9 = {_pma_checker_entries_barrier_12_io_y_u, _pma_checker_entries_barrier_11_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_priv_rw_ok_hi_hi_hi; // @[package.scala:45:27] assign pma_checker_priv_rw_ok_hi_hi_hi = _GEN_9; // @[package.scala:45:27] wire [1:0] pma_checker_priv_rw_ok_hi_hi_hi_1; // @[package.scala:45:27] assign pma_checker_priv_rw_ok_hi_hi_hi_1 = _GEN_9; // @[package.scala:45:27] wire [1:0] pma_checker_priv_x_ok_hi_hi_hi; // @[package.scala:45:27] assign pma_checker_priv_x_ok_hi_hi_hi = _GEN_9; // @[package.scala:45:27] wire [1:0] pma_checker_priv_x_ok_hi_hi_hi_1; // @[package.scala:45:27] assign pma_checker_priv_x_ok_hi_hi_hi_1 = _GEN_9; // @[package.scala:45:27] wire [3:0] pma_checker_priv_rw_ok_hi_hi = {pma_checker_priv_rw_ok_hi_hi_hi, pma_checker_priv_rw_ok_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_priv_rw_ok_hi = {pma_checker_priv_rw_ok_hi_hi, pma_checker_priv_rw_ok_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__priv_rw_ok_T_2 = {pma_checker_priv_rw_ok_hi, pma_checker_priv_rw_ok_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__priv_rw_ok_T_3 = pma_checker__priv_rw_ok_T_1 ? pma_checker__priv_rw_ok_T_2 : 13'h0; // @[package.scala:45:27] wire [2:0] pma_checker_priv_rw_ok_lo_lo_1 = {pma_checker_priv_rw_ok_lo_lo_hi_1, _pma_checker_entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_priv_rw_ok_lo_hi_1 = {pma_checker_priv_rw_ok_lo_hi_hi_1, _pma_checker_entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_priv_rw_ok_lo_1 = {pma_checker_priv_rw_ok_lo_hi_1, pma_checker_priv_rw_ok_lo_lo_1}; // @[package.scala:45:27] wire [2:0] pma_checker_priv_rw_ok_hi_lo_1 = {pma_checker_priv_rw_ok_hi_lo_hi_1, _pma_checker_entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_priv_rw_ok_hi_hi_1 = {pma_checker_priv_rw_ok_hi_hi_hi_1, pma_checker_priv_rw_ok_hi_hi_lo_1}; // @[package.scala:45:27] wire [6:0] pma_checker_priv_rw_ok_hi_1 = {pma_checker_priv_rw_ok_hi_hi_1, pma_checker_priv_rw_ok_hi_lo_1}; // @[package.scala:45:27] wire [12:0] pma_checker__priv_rw_ok_T_4 = {pma_checker_priv_rw_ok_hi_1, pma_checker_priv_rw_ok_lo_1}; // @[package.scala:45:27] wire [12:0] pma_checker__priv_rw_ok_T_5 = ~pma_checker__priv_rw_ok_T_4; // @[package.scala:45:27] wire [12:0] pma_checker__priv_rw_ok_T_6 = pma_checker_priv_s ? pma_checker__priv_rw_ok_T_5 : 13'h0; // @[TLB.scala:370:20, :513:{75,84}] wire [12:0] pma_checker_priv_rw_ok = pma_checker__priv_rw_ok_T_3 | pma_checker__priv_rw_ok_T_6; // @[TLB.scala:513:{23,70,75}] wire [2:0] pma_checker_priv_x_ok_lo_lo = {pma_checker_priv_x_ok_lo_lo_hi, _pma_checker_entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_priv_x_ok_lo_hi = {pma_checker_priv_x_ok_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_priv_x_ok_lo = {pma_checker_priv_x_ok_lo_hi, pma_checker_priv_x_ok_lo_lo}; // @[package.scala:45:27] wire [2:0] pma_checker_priv_x_ok_hi_lo = {pma_checker_priv_x_ok_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_priv_x_ok_hi_hi = {pma_checker_priv_x_ok_hi_hi_hi, pma_checker_priv_x_ok_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_priv_x_ok_hi = {pma_checker_priv_x_ok_hi_hi, pma_checker_priv_x_ok_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__priv_x_ok_T = {pma_checker_priv_x_ok_hi, pma_checker_priv_x_ok_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__priv_x_ok_T_1 = ~pma_checker__priv_x_ok_T; // @[package.scala:45:27] wire [2:0] pma_checker_priv_x_ok_lo_lo_1 = {pma_checker_priv_x_ok_lo_lo_hi_1, _pma_checker_entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_priv_x_ok_lo_hi_1 = {pma_checker_priv_x_ok_lo_hi_hi_1, _pma_checker_entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_priv_x_ok_lo_1 = {pma_checker_priv_x_ok_lo_hi_1, pma_checker_priv_x_ok_lo_lo_1}; // @[package.scala:45:27] wire [2:0] pma_checker_priv_x_ok_hi_lo_1 = {pma_checker_priv_x_ok_hi_lo_hi_1, _pma_checker_entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_priv_x_ok_hi_hi_1 = {pma_checker_priv_x_ok_hi_hi_hi_1, pma_checker_priv_x_ok_hi_hi_lo_1}; // @[package.scala:45:27] wire [6:0] pma_checker_priv_x_ok_hi_1 = {pma_checker_priv_x_ok_hi_hi_1, pma_checker_priv_x_ok_hi_lo_1}; // @[package.scala:45:27] wire [12:0] pma_checker__priv_x_ok_T_2 = {pma_checker_priv_x_ok_hi_1, pma_checker_priv_x_ok_lo_1}; // @[package.scala:45:27] wire [12:0] pma_checker_priv_x_ok = pma_checker_priv_s ? pma_checker__priv_x_ok_T_1 : pma_checker__priv_x_ok_T_2; // @[package.scala:45:27] wire [1:0] pma_checker_stage1_bypass_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_ae_stage2, _pma_checker_entries_barrier_1_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_stage1_bypass_lo_lo = {pma_checker_stage1_bypass_lo_lo_hi, _pma_checker_entries_barrier_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_stage1_bypass_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_ae_stage2, _pma_checker_entries_barrier_4_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_stage1_bypass_lo_hi = {pma_checker_stage1_bypass_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_stage1_bypass_lo = {pma_checker_stage1_bypass_lo_hi, pma_checker_stage1_bypass_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_stage1_bypass_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_ae_stage2, _pma_checker_entries_barrier_7_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_stage1_bypass_hi_lo = {pma_checker_stage1_bypass_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_stage1_bypass_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_ae_stage2, _pma_checker_entries_barrier_9_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_stage1_bypass_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_ae_stage2, _pma_checker_entries_barrier_11_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_stage1_bypass_hi_hi = {pma_checker_stage1_bypass_hi_hi_hi, pma_checker_stage1_bypass_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_stage1_bypass_hi = {pma_checker_stage1_bypass_hi_hi, pma_checker_stage1_bypass_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__stage1_bypass_T_3 = {pma_checker_stage1_bypass_hi, pma_checker_stage1_bypass_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_r_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_sr, _pma_checker_entries_barrier_1_io_y_sr}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_r_array_lo_lo = {pma_checker_r_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_sr}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_r_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_sr, _pma_checker_entries_barrier_4_io_y_sr}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_r_array_lo_hi = {pma_checker_r_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_sr}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_r_array_lo = {pma_checker_r_array_lo_hi, pma_checker_r_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_r_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_sr, _pma_checker_entries_barrier_7_io_y_sr}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_r_array_hi_lo = {pma_checker_r_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_sr}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_r_array_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_sr, _pma_checker_entries_barrier_9_io_y_sr}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_r_array_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_sr, _pma_checker_entries_barrier_11_io_y_sr}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_r_array_hi_hi = {pma_checker_r_array_hi_hi_hi, pma_checker_r_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_r_array_hi = {pma_checker_r_array_hi_hi, pma_checker_r_array_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__r_array_T = {pma_checker_r_array_hi, pma_checker_r_array_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__r_array_T_3 = pma_checker__r_array_T; // @[package.scala:45:27] wire [1:0] _GEN_10 = {_pma_checker_entries_barrier_2_io_y_sx, _pma_checker_entries_barrier_1_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_r_array_lo_lo_hi_1; // @[package.scala:45:27] assign pma_checker_r_array_lo_lo_hi_1 = _GEN_10; // @[package.scala:45:27] wire [1:0] pma_checker_x_array_lo_lo_hi; // @[package.scala:45:27] assign pma_checker_x_array_lo_lo_hi = _GEN_10; // @[package.scala:45:27] wire [2:0] pma_checker_r_array_lo_lo_1 = {pma_checker_r_array_lo_lo_hi_1, _pma_checker_entries_barrier_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_11 = {_pma_checker_entries_barrier_5_io_y_sx, _pma_checker_entries_barrier_4_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_r_array_lo_hi_hi_1; // @[package.scala:45:27] assign pma_checker_r_array_lo_hi_hi_1 = _GEN_11; // @[package.scala:45:27] wire [1:0] pma_checker_x_array_lo_hi_hi; // @[package.scala:45:27] assign pma_checker_x_array_lo_hi_hi = _GEN_11; // @[package.scala:45:27] wire [2:0] pma_checker_r_array_lo_hi_1 = {pma_checker_r_array_lo_hi_hi_1, _pma_checker_entries_barrier_3_io_y_sx}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_r_array_lo_1 = {pma_checker_r_array_lo_hi_1, pma_checker_r_array_lo_lo_1}; // @[package.scala:45:27] wire [1:0] _GEN_12 = {_pma_checker_entries_barrier_8_io_y_sx, _pma_checker_entries_barrier_7_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_r_array_hi_lo_hi_1; // @[package.scala:45:27] assign pma_checker_r_array_hi_lo_hi_1 = _GEN_12; // @[package.scala:45:27] wire [1:0] pma_checker_x_array_hi_lo_hi; // @[package.scala:45:27] assign pma_checker_x_array_hi_lo_hi = _GEN_12; // @[package.scala:45:27] wire [2:0] pma_checker_r_array_hi_lo_1 = {pma_checker_r_array_hi_lo_hi_1, _pma_checker_entries_barrier_6_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_13 = {_pma_checker_entries_barrier_10_io_y_sx, _pma_checker_entries_barrier_9_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_r_array_hi_hi_lo_1; // @[package.scala:45:27] assign pma_checker_r_array_hi_hi_lo_1 = _GEN_13; // @[package.scala:45:27] wire [1:0] pma_checker_x_array_hi_hi_lo; // @[package.scala:45:27] assign pma_checker_x_array_hi_hi_lo = _GEN_13; // @[package.scala:45:27] wire [1:0] _GEN_14 = {_pma_checker_entries_barrier_12_io_y_sx, _pma_checker_entries_barrier_11_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_r_array_hi_hi_hi_1; // @[package.scala:45:27] assign pma_checker_r_array_hi_hi_hi_1 = _GEN_14; // @[package.scala:45:27] wire [1:0] pma_checker_x_array_hi_hi_hi; // @[package.scala:45:27] assign pma_checker_x_array_hi_hi_hi = _GEN_14; // @[package.scala:45:27] wire [3:0] pma_checker_r_array_hi_hi_1 = {pma_checker_r_array_hi_hi_hi_1, pma_checker_r_array_hi_hi_lo_1}; // @[package.scala:45:27] wire [6:0] pma_checker_r_array_hi_1 = {pma_checker_r_array_hi_hi_1, pma_checker_r_array_hi_lo_1}; // @[package.scala:45:27] wire [12:0] pma_checker__r_array_T_1 = {pma_checker_r_array_hi_1, pma_checker_r_array_lo_1}; // @[package.scala:45:27] wire [12:0] pma_checker__r_array_T_4 = pma_checker_priv_rw_ok & pma_checker__r_array_T_3; // @[TLB.scala:513:70, :520:{41,69}] wire [12:0] pma_checker__r_array_T_5 = pma_checker__r_array_T_4; // @[TLB.scala:520:{41,113}] wire [13:0] pma_checker_r_array = {1'h1, pma_checker__r_array_T_5}; // @[TLB.scala:520:{20,113}] wire [13:0] pma_checker__pf_ld_array_T = pma_checker_r_array; // @[TLB.scala:520:20, :597:41] wire [1:0] pma_checker_w_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_sw, _pma_checker_entries_barrier_1_io_y_sw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_w_array_lo_lo = {pma_checker_w_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_sw}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_w_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_sw, _pma_checker_entries_barrier_4_io_y_sw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_w_array_lo_hi = {pma_checker_w_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_sw}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_w_array_lo = {pma_checker_w_array_lo_hi, pma_checker_w_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_w_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_sw, _pma_checker_entries_barrier_7_io_y_sw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_w_array_hi_lo = {pma_checker_w_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_sw}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_w_array_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_sw, _pma_checker_entries_barrier_9_io_y_sw}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_w_array_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_sw, _pma_checker_entries_barrier_11_io_y_sw}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_w_array_hi_hi = {pma_checker_w_array_hi_hi_hi, pma_checker_w_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_w_array_hi = {pma_checker_w_array_hi_hi, pma_checker_w_array_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__w_array_T = {pma_checker_w_array_hi, pma_checker_w_array_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__w_array_T_1 = pma_checker_priv_rw_ok & pma_checker__w_array_T; // @[package.scala:45:27] wire [12:0] pma_checker__w_array_T_2 = pma_checker__w_array_T_1; // @[TLB.scala:521:{41,69}] wire [13:0] pma_checker_w_array = {1'h1, pma_checker__w_array_T_2}; // @[TLB.scala:521:{20,69}] wire [2:0] pma_checker_x_array_lo_lo = {pma_checker_x_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_sx}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_x_array_lo_hi = {pma_checker_x_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_sx}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_x_array_lo = {pma_checker_x_array_lo_hi, pma_checker_x_array_lo_lo}; // @[package.scala:45:27] wire [2:0] pma_checker_x_array_hi_lo = {pma_checker_x_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_sx}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_x_array_hi_hi = {pma_checker_x_array_hi_hi_hi, pma_checker_x_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_x_array_hi = {pma_checker_x_array_hi_hi, pma_checker_x_array_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__x_array_T = {pma_checker_x_array_hi, pma_checker_x_array_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__x_array_T_1 = pma_checker_priv_x_ok & pma_checker__x_array_T; // @[package.scala:45:27] wire [12:0] pma_checker__x_array_T_2 = pma_checker__x_array_T_1; // @[TLB.scala:522:{40,68}] wire [13:0] pma_checker_x_array = {1'h1, pma_checker__x_array_T_2}; // @[TLB.scala:522:{20,68}] wire [1:0] pma_checker_hr_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_hr, _pma_checker_entries_barrier_1_io_y_hr}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_hr_array_lo_lo = {pma_checker_hr_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_hr}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_hr_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_hr, _pma_checker_entries_barrier_4_io_y_hr}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_hr_array_lo_hi = {pma_checker_hr_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_hr}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_hr_array_lo = {pma_checker_hr_array_lo_hi, pma_checker_hr_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_hr_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_hr, _pma_checker_entries_barrier_7_io_y_hr}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_hr_array_hi_lo = {pma_checker_hr_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_hr}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_hr_array_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_hr, _pma_checker_entries_barrier_9_io_y_hr}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_hr_array_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_hr, _pma_checker_entries_barrier_11_io_y_hr}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_hr_array_hi_hi = {pma_checker_hr_array_hi_hi_hi, pma_checker_hr_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_hr_array_hi = {pma_checker_hr_array_hi_hi, pma_checker_hr_array_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__hr_array_T = {pma_checker_hr_array_hi, pma_checker_hr_array_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__hr_array_T_3 = pma_checker__hr_array_T; // @[package.scala:45:27] wire [1:0] _GEN_15 = {_pma_checker_entries_barrier_2_io_y_hx, _pma_checker_entries_barrier_1_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_hr_array_lo_lo_hi_1; // @[package.scala:45:27] assign pma_checker_hr_array_lo_lo_hi_1 = _GEN_15; // @[package.scala:45:27] wire [1:0] pma_checker_hx_array_lo_lo_hi; // @[package.scala:45:27] assign pma_checker_hx_array_lo_lo_hi = _GEN_15; // @[package.scala:45:27] wire [2:0] pma_checker_hr_array_lo_lo_1 = {pma_checker_hr_array_lo_lo_hi_1, _pma_checker_entries_barrier_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_16 = {_pma_checker_entries_barrier_5_io_y_hx, _pma_checker_entries_barrier_4_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_hr_array_lo_hi_hi_1; // @[package.scala:45:27] assign pma_checker_hr_array_lo_hi_hi_1 = _GEN_16; // @[package.scala:45:27] wire [1:0] pma_checker_hx_array_lo_hi_hi; // @[package.scala:45:27] assign pma_checker_hx_array_lo_hi_hi = _GEN_16; // @[package.scala:45:27] wire [2:0] pma_checker_hr_array_lo_hi_1 = {pma_checker_hr_array_lo_hi_hi_1, _pma_checker_entries_barrier_3_io_y_hx}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_hr_array_lo_1 = {pma_checker_hr_array_lo_hi_1, pma_checker_hr_array_lo_lo_1}; // @[package.scala:45:27] wire [1:0] _GEN_17 = {_pma_checker_entries_barrier_8_io_y_hx, _pma_checker_entries_barrier_7_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_hr_array_hi_lo_hi_1; // @[package.scala:45:27] assign pma_checker_hr_array_hi_lo_hi_1 = _GEN_17; // @[package.scala:45:27] wire [1:0] pma_checker_hx_array_hi_lo_hi; // @[package.scala:45:27] assign pma_checker_hx_array_hi_lo_hi = _GEN_17; // @[package.scala:45:27] wire [2:0] pma_checker_hr_array_hi_lo_1 = {pma_checker_hr_array_hi_lo_hi_1, _pma_checker_entries_barrier_6_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_18 = {_pma_checker_entries_barrier_10_io_y_hx, _pma_checker_entries_barrier_9_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_hr_array_hi_hi_lo_1; // @[package.scala:45:27] assign pma_checker_hr_array_hi_hi_lo_1 = _GEN_18; // @[package.scala:45:27] wire [1:0] pma_checker_hx_array_hi_hi_lo; // @[package.scala:45:27] assign pma_checker_hx_array_hi_hi_lo = _GEN_18; // @[package.scala:45:27] wire [1:0] _GEN_19 = {_pma_checker_entries_barrier_12_io_y_hx, _pma_checker_entries_barrier_11_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_hr_array_hi_hi_hi_1; // @[package.scala:45:27] assign pma_checker_hr_array_hi_hi_hi_1 = _GEN_19; // @[package.scala:45:27] wire [1:0] pma_checker_hx_array_hi_hi_hi; // @[package.scala:45:27] assign pma_checker_hx_array_hi_hi_hi = _GEN_19; // @[package.scala:45:27] wire [3:0] pma_checker_hr_array_hi_hi_1 = {pma_checker_hr_array_hi_hi_hi_1, pma_checker_hr_array_hi_hi_lo_1}; // @[package.scala:45:27] wire [6:0] pma_checker_hr_array_hi_1 = {pma_checker_hr_array_hi_hi_1, pma_checker_hr_array_hi_lo_1}; // @[package.scala:45:27] wire [12:0] pma_checker__hr_array_T_1 = {pma_checker_hr_array_hi_1, pma_checker_hr_array_lo_1}; // @[package.scala:45:27] wire [1:0] pma_checker_hw_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_hw, _pma_checker_entries_barrier_1_io_y_hw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_hw_array_lo_lo = {pma_checker_hw_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_hw}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_hw_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_hw, _pma_checker_entries_barrier_4_io_y_hw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_hw_array_lo_hi = {pma_checker_hw_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_hw}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_hw_array_lo = {pma_checker_hw_array_lo_hi, pma_checker_hw_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_hw_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_hw, _pma_checker_entries_barrier_7_io_y_hw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_hw_array_hi_lo = {pma_checker_hw_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_hw}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_hw_array_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_hw, _pma_checker_entries_barrier_9_io_y_hw}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_hw_array_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_hw, _pma_checker_entries_barrier_11_io_y_hw}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_hw_array_hi_hi = {pma_checker_hw_array_hi_hi_hi, pma_checker_hw_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_hw_array_hi = {pma_checker_hw_array_hi_hi, pma_checker_hw_array_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__hw_array_T = {pma_checker_hw_array_hi, pma_checker_hw_array_lo}; // @[package.scala:45:27] wire [2:0] pma_checker_hx_array_lo_lo = {pma_checker_hx_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_hx}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_hx_array_lo_hi = {pma_checker_hx_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_hx}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_hx_array_lo = {pma_checker_hx_array_lo_hi, pma_checker_hx_array_lo_lo}; // @[package.scala:45:27] wire [2:0] pma_checker_hx_array_hi_lo = {pma_checker_hx_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_hx}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_hx_array_hi_hi = {pma_checker_hx_array_hi_hi_hi, pma_checker_hx_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_hx_array_hi = {pma_checker_hx_array_hi_hi, pma_checker_hx_array_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__hx_array_T = {pma_checker_hx_array_hi, pma_checker_hx_array_lo}; // @[package.scala:45:27] wire [1:0] pma_checker__pr_array_T = {2{pma_checker_prot_r}}; // @[TLB.scala:429:55, :529:26] wire [1:0] pma_checker_pr_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_pr, _pma_checker_entries_barrier_1_io_y_pr}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pr_array_lo_lo = {pma_checker_pr_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_pr}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_pr_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_pr, _pma_checker_entries_barrier_4_io_y_pr}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pr_array_lo_hi = {pma_checker_pr_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_pr}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_pr_array_lo = {pma_checker_pr_array_lo_hi, pma_checker_pr_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_pr_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_pr, _pma_checker_entries_barrier_7_io_y_pr}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pr_array_hi_lo = {pma_checker_pr_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_pr}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_pr_array_hi_hi_hi = {_pma_checker_entries_barrier_11_io_y_pr, _pma_checker_entries_barrier_10_io_y_pr}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pr_array_hi_hi = {pma_checker_pr_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_pr}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_pr_array_hi = {pma_checker_pr_array_hi_hi, pma_checker_pr_array_hi_lo}; // @[package.scala:45:27] wire [11:0] pma_checker__pr_array_T_1 = {pma_checker_pr_array_hi, pma_checker_pr_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker__pr_array_T_2 = {pma_checker__pr_array_T, pma_checker__pr_array_T_1}; // @[package.scala:45:27] wire [13:0] _GEN_20 = pma_checker_ptw_ae_array | pma_checker_final_ae_array; // @[TLB.scala:506:25, :507:27, :529:104] wire [13:0] pma_checker__pr_array_T_3; // @[TLB.scala:529:104] assign pma_checker__pr_array_T_3 = _GEN_20; // @[TLB.scala:529:104] wire [13:0] pma_checker__pw_array_T_3; // @[TLB.scala:531:104] assign pma_checker__pw_array_T_3 = _GEN_20; // @[TLB.scala:529:104, :531:104] wire [13:0] pma_checker__px_array_T_3; // @[TLB.scala:533:104] assign pma_checker__px_array_T_3 = _GEN_20; // @[TLB.scala:529:104, :533:104] wire [13:0] pma_checker__pr_array_T_4 = ~pma_checker__pr_array_T_3; // @[TLB.scala:529:{89,104}] wire [13:0] pma_checker_pr_array = pma_checker__pr_array_T_2 & pma_checker__pr_array_T_4; // @[TLB.scala:529:{21,87,89}] wire [1:0] pma_checker__pw_array_T = {2{pma_checker_prot_w}}; // @[TLB.scala:430:55, :531:26] wire [1:0] pma_checker_pw_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_pw, _pma_checker_entries_barrier_1_io_y_pw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pw_array_lo_lo = {pma_checker_pw_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_pw}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_pw_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_pw, _pma_checker_entries_barrier_4_io_y_pw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pw_array_lo_hi = {pma_checker_pw_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_pw}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_pw_array_lo = {pma_checker_pw_array_lo_hi, pma_checker_pw_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_pw_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_pw, _pma_checker_entries_barrier_7_io_y_pw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pw_array_hi_lo = {pma_checker_pw_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_pw}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_pw_array_hi_hi_hi = {_pma_checker_entries_barrier_11_io_y_pw, _pma_checker_entries_barrier_10_io_y_pw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pw_array_hi_hi = {pma_checker_pw_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_pw}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_pw_array_hi = {pma_checker_pw_array_hi_hi, pma_checker_pw_array_hi_lo}; // @[package.scala:45:27] wire [11:0] pma_checker__pw_array_T_1 = {pma_checker_pw_array_hi, pma_checker_pw_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker__pw_array_T_2 = {pma_checker__pw_array_T, pma_checker__pw_array_T_1}; // @[package.scala:45:27] wire [13:0] pma_checker__pw_array_T_4 = ~pma_checker__pw_array_T_3; // @[TLB.scala:531:{89,104}] wire [13:0] pma_checker_pw_array = pma_checker__pw_array_T_2 & pma_checker__pw_array_T_4; // @[TLB.scala:531:{21,87,89}] wire [1:0] pma_checker__px_array_T = {2{pma_checker_prot_x}}; // @[TLB.scala:434:55, :533:26] wire [1:0] pma_checker_px_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_px, _pma_checker_entries_barrier_1_io_y_px}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_px_array_lo_lo = {pma_checker_px_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_px}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_px_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_px, _pma_checker_entries_barrier_4_io_y_px}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_px_array_lo_hi = {pma_checker_px_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_px}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_px_array_lo = {pma_checker_px_array_lo_hi, pma_checker_px_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_px_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_px, _pma_checker_entries_barrier_7_io_y_px}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_px_array_hi_lo = {pma_checker_px_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_px}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_px_array_hi_hi_hi = {_pma_checker_entries_barrier_11_io_y_px, _pma_checker_entries_barrier_10_io_y_px}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_px_array_hi_hi = {pma_checker_px_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_px}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_px_array_hi = {pma_checker_px_array_hi_hi, pma_checker_px_array_hi_lo}; // @[package.scala:45:27] wire [11:0] pma_checker__px_array_T_1 = {pma_checker_px_array_hi, pma_checker_px_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker__px_array_T_2 = {pma_checker__px_array_T, pma_checker__px_array_T_1}; // @[package.scala:45:27] wire [13:0] pma_checker__px_array_T_4 = ~pma_checker__px_array_T_3; // @[TLB.scala:533:{89,104}] wire [13:0] pma_checker_px_array = pma_checker__px_array_T_2 & pma_checker__px_array_T_4; // @[TLB.scala:533:{21,87,89}] wire [1:0] pma_checker__eff_array_T = {2{_pma_checker_pma_io_resp_eff}}; // @[TLB.scala:422:19, :535:27] wire [1:0] pma_checker_eff_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_eff, _pma_checker_entries_barrier_1_io_y_eff}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_eff_array_lo_lo = {pma_checker_eff_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_eff}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_eff_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_eff, _pma_checker_entries_barrier_4_io_y_eff}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_eff_array_lo_hi = {pma_checker_eff_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_eff}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_eff_array_lo = {pma_checker_eff_array_lo_hi, pma_checker_eff_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_eff_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_eff, _pma_checker_entries_barrier_7_io_y_eff}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_eff_array_hi_lo = {pma_checker_eff_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_eff}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_eff_array_hi_hi_hi = {_pma_checker_entries_barrier_11_io_y_eff, _pma_checker_entries_barrier_10_io_y_eff}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_eff_array_hi_hi = {pma_checker_eff_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_eff}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_eff_array_hi = {pma_checker_eff_array_hi_hi, pma_checker_eff_array_hi_lo}; // @[package.scala:45:27] wire [11:0] pma_checker__eff_array_T_1 = {pma_checker_eff_array_hi, pma_checker_eff_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker_eff_array = {pma_checker__eff_array_T, pma_checker__eff_array_T_1}; // @[package.scala:45:27] wire [1:0] _GEN_21 = {_pma_checker_entries_barrier_2_io_y_c, _pma_checker_entries_barrier_1_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_c_array_lo_lo_hi; // @[package.scala:45:27] assign pma_checker_c_array_lo_lo_hi = _GEN_21; // @[package.scala:45:27] wire [1:0] pma_checker_prefetchable_array_lo_lo_hi; // @[package.scala:45:27] assign pma_checker_prefetchable_array_lo_lo_hi = _GEN_21; // @[package.scala:45:27] wire [2:0] pma_checker_c_array_lo_lo = {pma_checker_c_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_22 = {_pma_checker_entries_barrier_5_io_y_c, _pma_checker_entries_barrier_4_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_c_array_lo_hi_hi; // @[package.scala:45:27] assign pma_checker_c_array_lo_hi_hi = _GEN_22; // @[package.scala:45:27] wire [1:0] pma_checker_prefetchable_array_lo_hi_hi; // @[package.scala:45:27] assign pma_checker_prefetchable_array_lo_hi_hi = _GEN_22; // @[package.scala:45:27] wire [2:0] pma_checker_c_array_lo_hi = {pma_checker_c_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_c}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_c_array_lo = {pma_checker_c_array_lo_hi, pma_checker_c_array_lo_lo}; // @[package.scala:45:27] wire [1:0] _GEN_23 = {_pma_checker_entries_barrier_8_io_y_c, _pma_checker_entries_barrier_7_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_c_array_hi_lo_hi; // @[package.scala:45:27] assign pma_checker_c_array_hi_lo_hi = _GEN_23; // @[package.scala:45:27] wire [1:0] pma_checker_prefetchable_array_hi_lo_hi; // @[package.scala:45:27] assign pma_checker_prefetchable_array_hi_lo_hi = _GEN_23; // @[package.scala:45:27] wire [2:0] pma_checker_c_array_hi_lo = {pma_checker_c_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_24 = {_pma_checker_entries_barrier_11_io_y_c, _pma_checker_entries_barrier_10_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_c_array_hi_hi_hi; // @[package.scala:45:27] assign pma_checker_c_array_hi_hi_hi = _GEN_24; // @[package.scala:45:27] wire [1:0] pma_checker_prefetchable_array_hi_hi_hi; // @[package.scala:45:27] assign pma_checker_prefetchable_array_hi_hi_hi = _GEN_24; // @[package.scala:45:27] wire [2:0] pma_checker_c_array_hi_hi = {pma_checker_c_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_c}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_c_array_hi = {pma_checker_c_array_hi_hi, pma_checker_c_array_hi_lo}; // @[package.scala:45:27] wire [11:0] pma_checker__c_array_T_1 = {pma_checker_c_array_hi, pma_checker_c_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker_c_array = {2'h0, pma_checker__c_array_T_1}; // @[package.scala:45:27] wire [1:0] pma_checker__ppp_array_T = {2{_pma_checker_pma_io_resp_pp}}; // @[TLB.scala:422:19, :539:27] wire [1:0] pma_checker_ppp_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_ppp, _pma_checker_entries_barrier_1_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ppp_array_lo_lo = {pma_checker_ppp_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_ppp_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_ppp, _pma_checker_entries_barrier_4_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ppp_array_lo_hi = {pma_checker_ppp_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_ppp_array_lo = {pma_checker_ppp_array_lo_hi, pma_checker_ppp_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_ppp_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_ppp, _pma_checker_entries_barrier_7_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ppp_array_hi_lo = {pma_checker_ppp_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_ppp_array_hi_hi_hi = {_pma_checker_entries_barrier_11_io_y_ppp, _pma_checker_entries_barrier_10_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ppp_array_hi_hi = {pma_checker_ppp_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_ppp_array_hi = {pma_checker_ppp_array_hi_hi, pma_checker_ppp_array_hi_lo}; // @[package.scala:45:27] wire [11:0] pma_checker__ppp_array_T_1 = {pma_checker_ppp_array_hi, pma_checker_ppp_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker_ppp_array = {pma_checker__ppp_array_T, pma_checker__ppp_array_T_1}; // @[package.scala:45:27] wire [1:0] pma_checker__paa_array_T = {2{_pma_checker_pma_io_resp_aa}}; // @[TLB.scala:422:19, :541:27] wire [1:0] pma_checker_paa_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_paa, _pma_checker_entries_barrier_1_io_y_paa}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_paa_array_lo_lo = {pma_checker_paa_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_paa}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_paa_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_paa, _pma_checker_entries_barrier_4_io_y_paa}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_paa_array_lo_hi = {pma_checker_paa_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_paa}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_paa_array_lo = {pma_checker_paa_array_lo_hi, pma_checker_paa_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_paa_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_paa, _pma_checker_entries_barrier_7_io_y_paa}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_paa_array_hi_lo = {pma_checker_paa_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_paa}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_paa_array_hi_hi_hi = {_pma_checker_entries_barrier_11_io_y_paa, _pma_checker_entries_barrier_10_io_y_paa}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_paa_array_hi_hi = {pma_checker_paa_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_paa}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_paa_array_hi = {pma_checker_paa_array_hi_hi, pma_checker_paa_array_hi_lo}; // @[package.scala:45:27] wire [11:0] pma_checker__paa_array_T_1 = {pma_checker_paa_array_hi, pma_checker_paa_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker_paa_array = {pma_checker__paa_array_T, pma_checker__paa_array_T_1}; // @[package.scala:45:27] wire [1:0] pma_checker__pal_array_T = {2{_pma_checker_pma_io_resp_al}}; // @[TLB.scala:422:19, :543:27] wire [1:0] pma_checker_pal_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_pal, _pma_checker_entries_barrier_1_io_y_pal}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pal_array_lo_lo = {pma_checker_pal_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_pal}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_pal_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_pal, _pma_checker_entries_barrier_4_io_y_pal}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pal_array_lo_hi = {pma_checker_pal_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_pal}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_pal_array_lo = {pma_checker_pal_array_lo_hi, pma_checker_pal_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_pal_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_pal, _pma_checker_entries_barrier_7_io_y_pal}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pal_array_hi_lo = {pma_checker_pal_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_pal}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_pal_array_hi_hi_hi = {_pma_checker_entries_barrier_11_io_y_pal, _pma_checker_entries_barrier_10_io_y_pal}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pal_array_hi_hi = {pma_checker_pal_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_pal}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_pal_array_hi = {pma_checker_pal_array_hi_hi, pma_checker_pal_array_hi_lo}; // @[package.scala:45:27] wire [11:0] pma_checker__pal_array_T_1 = {pma_checker_pal_array_hi, pma_checker_pal_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker_pal_array = {pma_checker__pal_array_T, pma_checker__pal_array_T_1}; // @[package.scala:45:27] wire [13:0] pma_checker_ppp_array_if_cached = pma_checker_ppp_array | pma_checker_c_array; // @[TLB.scala:537:20, :539:22, :544:39] wire [13:0] pma_checker_paa_array_if_cached = pma_checker_paa_array | pma_checker_c_array; // @[TLB.scala:537:20, :541:22, :545:39] wire [13:0] pma_checker_pal_array_if_cached = pma_checker_pal_array | pma_checker_c_array; // @[TLB.scala:537:20, :543:22, :546:39] wire [2:0] pma_checker_prefetchable_array_lo_lo = {pma_checker_prefetchable_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_c}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_prefetchable_array_lo_hi = {pma_checker_prefetchable_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_c}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_prefetchable_array_lo = {pma_checker_prefetchable_array_lo_hi, pma_checker_prefetchable_array_lo_lo}; // @[package.scala:45:27] wire [2:0] pma_checker_prefetchable_array_hi_lo = {pma_checker_prefetchable_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_c}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_prefetchable_array_hi_hi = {pma_checker_prefetchable_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_c}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_prefetchable_array_hi = {pma_checker_prefetchable_array_hi_hi, pma_checker_prefetchable_array_hi_lo}; // @[package.scala:45:27] wire [11:0] pma_checker__prefetchable_array_T_2 = {pma_checker_prefetchable_array_hi, pma_checker_prefetchable_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker_prefetchable_array = {2'h0, pma_checker__prefetchable_array_T_2}; // @[package.scala:45:27] wire [3:0] pma_checker__misaligned_T = 4'h1 << pma_checker_io_req_bits_size; // @[OneHot.scala:58:35] wire [4:0] pma_checker__misaligned_T_1 = {1'h0, pma_checker__misaligned_T} - 5'h1; // @[OneHot.scala:58:35] wire [3:0] pma_checker__misaligned_T_2 = pma_checker__misaligned_T_1[3:0]; // @[TLB.scala:550:69] wire [33:0] pma_checker__misaligned_T_3 = {30'h0, pma_checker_io_req_bits_vaddr[3:0] & pma_checker__misaligned_T_2}; // @[TLB.scala:550:{39,69}] wire pma_checker_misaligned = |pma_checker__misaligned_T_3; // @[TLB.scala:550:{39,77}] wire _GEN_25 = pma_checker_io_req_bits_cmd == 5'h6; // @[package.scala:16:47] wire pma_checker__cmd_lrsc_T; // @[package.scala:16:47] assign pma_checker__cmd_lrsc_T = _GEN_25; // @[package.scala:16:47] wire pma_checker__cmd_read_T_2; // @[package.scala:16:47] assign pma_checker__cmd_read_T_2 = _GEN_25; // @[package.scala:16:47] wire _GEN_26 = pma_checker_io_req_bits_cmd == 5'h7; // @[package.scala:16:47] wire pma_checker__cmd_lrsc_T_1; // @[package.scala:16:47] assign pma_checker__cmd_lrsc_T_1 = _GEN_26; // @[package.scala:16:47] wire pma_checker__cmd_read_T_3; // @[package.scala:16:47] assign pma_checker__cmd_read_T_3 = _GEN_26; // @[package.scala:16:47] wire pma_checker__cmd_write_T_3; // @[Consts.scala:90:66] assign pma_checker__cmd_write_T_3 = _GEN_26; // @[package.scala:16:47] wire pma_checker__cmd_lrsc_T_2 = pma_checker__cmd_lrsc_T | pma_checker__cmd_lrsc_T_1; // @[package.scala:16:47, :81:59] wire pma_checker_cmd_lrsc = pma_checker__cmd_lrsc_T_2; // @[package.scala:81:59] wire _GEN_27 = pma_checker_io_req_bits_cmd == 5'h4; // @[package.scala:16:47] wire pma_checker__cmd_amo_logical_T; // @[package.scala:16:47] assign pma_checker__cmd_amo_logical_T = _GEN_27; // @[package.scala:16:47] wire pma_checker__cmd_read_T_7; // @[package.scala:16:47] assign pma_checker__cmd_read_T_7 = _GEN_27; // @[package.scala:16:47] wire pma_checker__cmd_write_T_5; // @[package.scala:16:47] assign pma_checker__cmd_write_T_5 = _GEN_27; // @[package.scala:16:47] wire _GEN_28 = pma_checker_io_req_bits_cmd == 5'h9; // @[package.scala:16:47] wire pma_checker__cmd_amo_logical_T_1; // @[package.scala:16:47] assign pma_checker__cmd_amo_logical_T_1 = _GEN_28; // @[package.scala:16:47] wire pma_checker__cmd_read_T_8; // @[package.scala:16:47] assign pma_checker__cmd_read_T_8 = _GEN_28; // @[package.scala:16:47] wire pma_checker__cmd_write_T_6; // @[package.scala:16:47] assign pma_checker__cmd_write_T_6 = _GEN_28; // @[package.scala:16:47] wire _GEN_29 = pma_checker_io_req_bits_cmd == 5'hA; // @[package.scala:16:47] wire pma_checker__cmd_amo_logical_T_2; // @[package.scala:16:47] assign pma_checker__cmd_amo_logical_T_2 = _GEN_29; // @[package.scala:16:47] wire pma_checker__cmd_read_T_9; // @[package.scala:16:47] assign pma_checker__cmd_read_T_9 = _GEN_29; // @[package.scala:16:47] wire pma_checker__cmd_write_T_7; // @[package.scala:16:47] assign pma_checker__cmd_write_T_7 = _GEN_29; // @[package.scala:16:47] wire _GEN_30 = pma_checker_io_req_bits_cmd == 5'hB; // @[package.scala:16:47] wire pma_checker__cmd_amo_logical_T_3; // @[package.scala:16:47] assign pma_checker__cmd_amo_logical_T_3 = _GEN_30; // @[package.scala:16:47] wire pma_checker__cmd_read_T_10; // @[package.scala:16:47] assign pma_checker__cmd_read_T_10 = _GEN_30; // @[package.scala:16:47] wire pma_checker__cmd_write_T_8; // @[package.scala:16:47] assign pma_checker__cmd_write_T_8 = _GEN_30; // @[package.scala:16:47] wire pma_checker__cmd_amo_logical_T_4 = pma_checker__cmd_amo_logical_T | pma_checker__cmd_amo_logical_T_1; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_amo_logical_T_5 = pma_checker__cmd_amo_logical_T_4 | pma_checker__cmd_amo_logical_T_2; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_amo_logical_T_6 = pma_checker__cmd_amo_logical_T_5 | pma_checker__cmd_amo_logical_T_3; // @[package.scala:16:47, :81:59] wire pma_checker_cmd_amo_logical = pma_checker__cmd_amo_logical_T_6; // @[package.scala:81:59] wire _GEN_31 = pma_checker_io_req_bits_cmd == 5'h8; // @[package.scala:16:47] wire pma_checker__cmd_amo_arithmetic_T; // @[package.scala:16:47] assign pma_checker__cmd_amo_arithmetic_T = _GEN_31; // @[package.scala:16:47] wire pma_checker__cmd_read_T_14; // @[package.scala:16:47] assign pma_checker__cmd_read_T_14 = _GEN_31; // @[package.scala:16:47] wire pma_checker__cmd_write_T_12; // @[package.scala:16:47] assign pma_checker__cmd_write_T_12 = _GEN_31; // @[package.scala:16:47] wire _GEN_32 = pma_checker_io_req_bits_cmd == 5'hC; // @[package.scala:16:47] wire pma_checker__cmd_amo_arithmetic_T_1; // @[package.scala:16:47] assign pma_checker__cmd_amo_arithmetic_T_1 = _GEN_32; // @[package.scala:16:47] wire pma_checker__cmd_read_T_15; // @[package.scala:16:47] assign pma_checker__cmd_read_T_15 = _GEN_32; // @[package.scala:16:47] wire pma_checker__cmd_write_T_13; // @[package.scala:16:47] assign pma_checker__cmd_write_T_13 = _GEN_32; // @[package.scala:16:47] wire _GEN_33 = pma_checker_io_req_bits_cmd == 5'hD; // @[package.scala:16:47] wire pma_checker__cmd_amo_arithmetic_T_2; // @[package.scala:16:47] assign pma_checker__cmd_amo_arithmetic_T_2 = _GEN_33; // @[package.scala:16:47] wire pma_checker__cmd_read_T_16; // @[package.scala:16:47] assign pma_checker__cmd_read_T_16 = _GEN_33; // @[package.scala:16:47] wire pma_checker__cmd_write_T_14; // @[package.scala:16:47] assign pma_checker__cmd_write_T_14 = _GEN_33; // @[package.scala:16:47] wire _GEN_34 = pma_checker_io_req_bits_cmd == 5'hE; // @[package.scala:16:47] wire pma_checker__cmd_amo_arithmetic_T_3; // @[package.scala:16:47] assign pma_checker__cmd_amo_arithmetic_T_3 = _GEN_34; // @[package.scala:16:47] wire pma_checker__cmd_read_T_17; // @[package.scala:16:47] assign pma_checker__cmd_read_T_17 = _GEN_34; // @[package.scala:16:47] wire pma_checker__cmd_write_T_15; // @[package.scala:16:47] assign pma_checker__cmd_write_T_15 = _GEN_34; // @[package.scala:16:47] wire _GEN_35 = pma_checker_io_req_bits_cmd == 5'hF; // @[package.scala:16:47] wire pma_checker__cmd_amo_arithmetic_T_4; // @[package.scala:16:47] assign pma_checker__cmd_amo_arithmetic_T_4 = _GEN_35; // @[package.scala:16:47] wire pma_checker__cmd_read_T_18; // @[package.scala:16:47] assign pma_checker__cmd_read_T_18 = _GEN_35; // @[package.scala:16:47] wire pma_checker__cmd_write_T_16; // @[package.scala:16:47] assign pma_checker__cmd_write_T_16 = _GEN_35; // @[package.scala:16:47] wire pma_checker__cmd_amo_arithmetic_T_5 = pma_checker__cmd_amo_arithmetic_T | pma_checker__cmd_amo_arithmetic_T_1; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_amo_arithmetic_T_6 = pma_checker__cmd_amo_arithmetic_T_5 | pma_checker__cmd_amo_arithmetic_T_2; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_amo_arithmetic_T_7 = pma_checker__cmd_amo_arithmetic_T_6 | pma_checker__cmd_amo_arithmetic_T_3; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_amo_arithmetic_T_8 = pma_checker__cmd_amo_arithmetic_T_7 | pma_checker__cmd_amo_arithmetic_T_4; // @[package.scala:16:47, :81:59] wire pma_checker_cmd_amo_arithmetic = pma_checker__cmd_amo_arithmetic_T_8; // @[package.scala:81:59] wire _GEN_36 = pma_checker_io_req_bits_cmd == 5'h11; // @[TLB.scala:573:41] wire pma_checker_cmd_put_partial; // @[TLB.scala:573:41] assign pma_checker_cmd_put_partial = _GEN_36; // @[TLB.scala:573:41] wire pma_checker__cmd_write_T_1; // @[Consts.scala:90:49] assign pma_checker__cmd_write_T_1 = _GEN_36; // @[TLB.scala:573:41] wire pma_checker__cmd_read_T = pma_checker_io_req_bits_cmd == 5'h0; // @[package.scala:16:47] wire _GEN_37 = pma_checker_io_req_bits_cmd == 5'h10; // @[package.scala:16:47] wire pma_checker__cmd_read_T_1; // @[package.scala:16:47] assign pma_checker__cmd_read_T_1 = _GEN_37; // @[package.scala:16:47] wire pma_checker__cmd_readx_T; // @[TLB.scala:575:56] assign pma_checker__cmd_readx_T = _GEN_37; // @[package.scala:16:47] wire pma_checker__cmd_read_T_4 = pma_checker__cmd_read_T | pma_checker__cmd_read_T_1; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_read_T_5 = pma_checker__cmd_read_T_4 | pma_checker__cmd_read_T_2; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_read_T_6 = pma_checker__cmd_read_T_5 | pma_checker__cmd_read_T_3; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_read_T_11 = pma_checker__cmd_read_T_7 | pma_checker__cmd_read_T_8; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_read_T_12 = pma_checker__cmd_read_T_11 | pma_checker__cmd_read_T_9; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_read_T_13 = pma_checker__cmd_read_T_12 | pma_checker__cmd_read_T_10; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_read_T_19 = pma_checker__cmd_read_T_14 | pma_checker__cmd_read_T_15; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_read_T_20 = pma_checker__cmd_read_T_19 | pma_checker__cmd_read_T_16; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_read_T_21 = pma_checker__cmd_read_T_20 | pma_checker__cmd_read_T_17; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_read_T_22 = pma_checker__cmd_read_T_21 | pma_checker__cmd_read_T_18; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_read_T_23 = pma_checker__cmd_read_T_13 | pma_checker__cmd_read_T_22; // @[package.scala:81:59] wire pma_checker_cmd_read = pma_checker__cmd_read_T_6 | pma_checker__cmd_read_T_23; // @[package.scala:81:59] wire pma_checker__cmd_write_T = pma_checker_io_req_bits_cmd == 5'h1; // @[DCache.scala:120:32] wire pma_checker__cmd_write_T_2 = pma_checker__cmd_write_T | pma_checker__cmd_write_T_1; // @[Consts.scala:90:{32,42,49}] wire pma_checker__cmd_write_T_4 = pma_checker__cmd_write_T_2 | pma_checker__cmd_write_T_3; // @[Consts.scala:90:{42,59,66}] wire pma_checker__cmd_write_T_9 = pma_checker__cmd_write_T_5 | pma_checker__cmd_write_T_6; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_write_T_10 = pma_checker__cmd_write_T_9 | pma_checker__cmd_write_T_7; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_write_T_11 = pma_checker__cmd_write_T_10 | pma_checker__cmd_write_T_8; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_write_T_17 = pma_checker__cmd_write_T_12 | pma_checker__cmd_write_T_13; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_write_T_18 = pma_checker__cmd_write_T_17 | pma_checker__cmd_write_T_14; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_write_T_19 = pma_checker__cmd_write_T_18 | pma_checker__cmd_write_T_15; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_write_T_20 = pma_checker__cmd_write_T_19 | pma_checker__cmd_write_T_16; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_write_T_21 = pma_checker__cmd_write_T_11 | pma_checker__cmd_write_T_20; // @[package.scala:81:59] wire pma_checker_cmd_write = pma_checker__cmd_write_T_4 | pma_checker__cmd_write_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire pma_checker__cmd_write_perms_T = pma_checker_io_req_bits_cmd == 5'h5; // @[package.scala:16:47] wire pma_checker__cmd_write_perms_T_1 = pma_checker_io_req_bits_cmd == 5'h17; // @[package.scala:16:47] wire pma_checker__cmd_write_perms_T_2 = pma_checker__cmd_write_perms_T | pma_checker__cmd_write_perms_T_1; // @[package.scala:16:47, :81:59] wire pma_checker_cmd_write_perms = pma_checker_cmd_write | pma_checker__cmd_write_perms_T_2; // @[package.scala:81:59] wire [13:0] pma_checker__ae_array_T = pma_checker_misaligned ? pma_checker_eff_array : 14'h0; // @[TLB.scala:535:22, :550:77, :582:8] wire [13:0] _GEN_38 = {14{pma_checker_cmd_lrsc}}; // @[TLB.scala:570:33, :583:8] wire [13:0] pma_checker__ae_array_T_2; // @[TLB.scala:583:8] assign pma_checker__ae_array_T_2 = _GEN_38; // @[TLB.scala:583:8] wire [13:0] pma_checker__must_alloc_array_T_9; // @[TLB.scala:596:8] assign pma_checker__must_alloc_array_T_9 = _GEN_38; // @[TLB.scala:583:8, :596:8] wire [13:0] pma_checker_ae_array = pma_checker__ae_array_T | pma_checker__ae_array_T_2; // @[TLB.scala:582:{8,37}, :583:8] wire [13:0] pma_checker__ae_ld_array_T = ~pma_checker_pr_array; // @[TLB.scala:529:87, :586:46] wire [13:0] pma_checker__ae_ld_array_T_1 = pma_checker_ae_array | pma_checker__ae_ld_array_T; // @[TLB.scala:582:37, :586:{44,46}] wire [13:0] pma_checker_ae_ld_array = pma_checker_cmd_read ? pma_checker__ae_ld_array_T_1 : 14'h0; // @[TLB.scala:586:{24,44}] wire [13:0] pma_checker__ae_st_array_T = ~pma_checker_pw_array; // @[TLB.scala:531:87, :588:37] wire [13:0] pma_checker__ae_st_array_T_1 = pma_checker_ae_array | pma_checker__ae_st_array_T; // @[TLB.scala:582:37, :588:{35,37}] wire [13:0] pma_checker__ae_st_array_T_2 = pma_checker_cmd_write_perms ? pma_checker__ae_st_array_T_1 : 14'h0; // @[TLB.scala:577:35, :588:{8,35}] wire [13:0] pma_checker__ae_st_array_T_3 = ~pma_checker_ppp_array_if_cached; // @[TLB.scala:544:39, :589:26] wire [13:0] pma_checker__ae_st_array_T_4 = pma_checker_cmd_put_partial ? pma_checker__ae_st_array_T_3 : 14'h0; // @[TLB.scala:573:41, :589:{8,26}] wire [13:0] pma_checker__ae_st_array_T_5 = pma_checker__ae_st_array_T_2 | pma_checker__ae_st_array_T_4; // @[TLB.scala:588:{8,53}, :589:8] wire [13:0] pma_checker__ae_st_array_T_6 = ~pma_checker_pal_array_if_cached; // @[TLB.scala:546:39, :590:26] wire [13:0] pma_checker__ae_st_array_T_7 = pma_checker_cmd_amo_logical ? pma_checker__ae_st_array_T_6 : 14'h0; // @[TLB.scala:571:40, :590:{8,26}] wire [13:0] pma_checker__ae_st_array_T_8 = pma_checker__ae_st_array_T_5 | pma_checker__ae_st_array_T_7; // @[TLB.scala:588:53, :589:53, :590:8] wire [13:0] pma_checker__ae_st_array_T_9 = ~pma_checker_paa_array_if_cached; // @[TLB.scala:545:39, :591:29] wire [13:0] pma_checker__ae_st_array_T_10 = pma_checker_cmd_amo_arithmetic ? pma_checker__ae_st_array_T_9 : 14'h0; // @[TLB.scala:572:43, :591:{8,29}] wire [13:0] pma_checker_ae_st_array = pma_checker__ae_st_array_T_8 | pma_checker__ae_st_array_T_10; // @[TLB.scala:589:53, :590:53, :591:8] wire [13:0] pma_checker__must_alloc_array_T = ~pma_checker_ppp_array; // @[TLB.scala:539:22, :593:26] wire [13:0] pma_checker__must_alloc_array_T_1 = pma_checker_cmd_put_partial ? pma_checker__must_alloc_array_T : 14'h0; // @[TLB.scala:573:41, :593:{8,26}] wire [13:0] pma_checker__must_alloc_array_T_2 = ~pma_checker_pal_array; // @[TLB.scala:543:22, :594:26] wire [13:0] pma_checker__must_alloc_array_T_3 = pma_checker_cmd_amo_logical ? pma_checker__must_alloc_array_T_2 : 14'h0; // @[TLB.scala:571:40, :594:{8,26}] wire [13:0] pma_checker__must_alloc_array_T_4 = pma_checker__must_alloc_array_T_1 | pma_checker__must_alloc_array_T_3; // @[TLB.scala:593:{8,43}, :594:8] wire [13:0] pma_checker__must_alloc_array_T_5 = ~pma_checker_paa_array; // @[TLB.scala:541:22, :595:29] wire [13:0] pma_checker__must_alloc_array_T_6 = pma_checker_cmd_amo_arithmetic ? pma_checker__must_alloc_array_T_5 : 14'h0; // @[TLB.scala:572:43, :595:{8,29}] wire [13:0] pma_checker__must_alloc_array_T_7 = pma_checker__must_alloc_array_T_4 | pma_checker__must_alloc_array_T_6; // @[TLB.scala:593:43, :594:43, :595:8] wire [13:0] pma_checker_must_alloc_array = pma_checker__must_alloc_array_T_7 | pma_checker__must_alloc_array_T_9; // @[TLB.scala:594:43, :595:46, :596:8] wire [13:0] pma_checker__pf_ld_array_T_1 = ~pma_checker__pf_ld_array_T; // @[TLB.scala:597:{37,41}] wire [13:0] pma_checker__pf_ld_array_T_2 = ~pma_checker_ptw_ae_array; // @[TLB.scala:506:25, :597:73] wire [13:0] pma_checker__pf_ld_array_T_3 = pma_checker__pf_ld_array_T_1 & pma_checker__pf_ld_array_T_2; // @[TLB.scala:597:{37,71,73}] wire [13:0] pma_checker__pf_ld_array_T_4 = pma_checker__pf_ld_array_T_3 | pma_checker_ptw_pf_array; // @[TLB.scala:508:25, :597:{71,88}] wire [13:0] pma_checker__pf_ld_array_T_5 = ~pma_checker_ptw_gf_array; // @[TLB.scala:509:25, :597:106] wire [13:0] pma_checker__pf_ld_array_T_6 = pma_checker__pf_ld_array_T_4 & pma_checker__pf_ld_array_T_5; // @[TLB.scala:597:{88,104,106}] wire [13:0] pma_checker_pf_ld_array = pma_checker_cmd_read ? pma_checker__pf_ld_array_T_6 : 14'h0; // @[TLB.scala:597:{24,104}] wire [13:0] pma_checker__pf_st_array_T = ~pma_checker_w_array; // @[TLB.scala:521:20, :598:44] wire [13:0] pma_checker__pf_st_array_T_1 = ~pma_checker_ptw_ae_array; // @[TLB.scala:506:25, :597:73, :598:55] wire [13:0] pma_checker__pf_st_array_T_2 = pma_checker__pf_st_array_T & pma_checker__pf_st_array_T_1; // @[TLB.scala:598:{44,53,55}] wire [13:0] pma_checker__pf_st_array_T_3 = pma_checker__pf_st_array_T_2 | pma_checker_ptw_pf_array; // @[TLB.scala:508:25, :598:{53,70}] wire [13:0] pma_checker__pf_st_array_T_4 = ~pma_checker_ptw_gf_array; // @[TLB.scala:509:25, :597:106, :598:88] wire [13:0] pma_checker__pf_st_array_T_5 = pma_checker__pf_st_array_T_3 & pma_checker__pf_st_array_T_4; // @[TLB.scala:598:{70,86,88}] wire [13:0] pma_checker_pf_st_array = pma_checker_cmd_write_perms ? pma_checker__pf_st_array_T_5 : 14'h0; // @[TLB.scala:577:35, :598:{24,86}] wire [13:0] pma_checker__pf_inst_array_T = ~pma_checker_x_array; // @[TLB.scala:522:20, :599:25] wire [13:0] pma_checker__pf_inst_array_T_1 = ~pma_checker_ptw_ae_array; // @[TLB.scala:506:25, :597:73, :599:36] wire [13:0] pma_checker__pf_inst_array_T_2 = pma_checker__pf_inst_array_T & pma_checker__pf_inst_array_T_1; // @[TLB.scala:599:{25,34,36}] wire [13:0] pma_checker__pf_inst_array_T_3 = pma_checker__pf_inst_array_T_2 | pma_checker_ptw_pf_array; // @[TLB.scala:508:25, :599:{34,51}] wire [13:0] pma_checker__pf_inst_array_T_4 = ~pma_checker_ptw_gf_array; // @[TLB.scala:509:25, :597:106, :599:69] wire [13:0] pma_checker_pf_inst_array = pma_checker__pf_inst_array_T_3 & pma_checker__pf_inst_array_T_4; // @[TLB.scala:599:{51,67,69}] wire [13:0] pma_checker__gf_ld_array_T_4 = ~pma_checker_ptw_ae_array; // @[TLB.scala:506:25, :597:73, :600:100] wire [13:0] pma_checker__gf_ld_array_T_5 = pma_checker__gf_ld_array_T_3 & pma_checker__gf_ld_array_T_4; // @[TLB.scala:600:{82,98,100}] wire [13:0] pma_checker__gf_st_array_T_3 = ~pma_checker_ptw_ae_array; // @[TLB.scala:506:25, :597:73, :601:81] wire [13:0] pma_checker__gf_st_array_T_4 = pma_checker__gf_st_array_T_2 & pma_checker__gf_st_array_T_3; // @[TLB.scala:601:{63,79,81}] wire [13:0] pma_checker__gf_inst_array_T_2 = ~pma_checker_ptw_ae_array; // @[TLB.scala:506:25, :597:73, :602:64] wire [13:0] pma_checker__gf_inst_array_T_3 = pma_checker__gf_inst_array_T_1 & pma_checker__gf_inst_array_T_2; // @[TLB.scala:602:{46,62,64}] wire pma_checker__gpa_hits_hit_mask_T = pma_checker_vpn == 21'h0; // @[TLB.scala:335:30, :606:73] wire [1:0] pma_checker_lo_lo = {pma_checker_sector_hits_1, pma_checker_sector_hits_0}; // @[OneHot.scala:21:45] wire [1:0] pma_checker_lo_hi = {pma_checker_sector_hits_3, pma_checker_sector_hits_2}; // @[OneHot.scala:21:45] wire [3:0] pma_checker_lo = {pma_checker_lo_hi, pma_checker_lo_lo}; // @[OneHot.scala:21:45] wire [3:0] pma_checker_lo_1 = pma_checker_lo; // @[OneHot.scala:21:45, :31:18] wire [1:0] pma_checker_hi_lo = {pma_checker_sector_hits_5, pma_checker_sector_hits_4}; // @[OneHot.scala:21:45] wire [1:0] pma_checker_hi_hi = {pma_checker_sector_hits_7, pma_checker_sector_hits_6}; // @[OneHot.scala:21:45] wire [3:0] pma_checker_hi = {pma_checker_hi_hi, pma_checker_hi_lo}; // @[OneHot.scala:21:45] wire [3:0] pma_checker_hi_1 = pma_checker_hi; // @[OneHot.scala:21:45, :30:18] wire [3:0] pma_checker__T_33 = pma_checker_hi_1 | pma_checker_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] pma_checker_hi_2 = pma_checker__T_33[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] pma_checker_lo_2 = pma_checker__T_33[1:0]; // @[OneHot.scala:31:18, :32:28] wire [2:0] pma_checker_state_vec_0_touch_way_sized = {|pma_checker_hi_1, |pma_checker_hi_2, pma_checker_hi_2[1] | pma_checker_lo_2[1]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}] wire pma_checker__state_vec_0_set_left_older_T = pma_checker_state_vec_0_touch_way_sized[2]; // @[package.scala:163:13] wire pma_checker_state_vec_0_set_left_older = ~pma_checker__state_vec_0_set_left_older_T; // @[Replacement.scala:196:{33,43}] wire [1:0] pma_checker__state_vec_0_T = pma_checker_state_vec_0_touch_way_sized[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker__state_vec_0_T_11 = pma_checker_state_vec_0_touch_way_sized[1:0]; // @[package.scala:163:13] wire pma_checker__state_vec_0_set_left_older_T_1 = pma_checker__state_vec_0_T[1]; // @[package.scala:163:13] wire pma_checker_state_vec_0_set_left_older_1 = ~pma_checker__state_vec_0_set_left_older_T_1; // @[Replacement.scala:196:{33,43}] wire pma_checker__state_vec_0_T_1 = pma_checker__state_vec_0_T[0]; // @[package.scala:163:13] wire pma_checker__state_vec_0_T_5 = pma_checker__state_vec_0_T[0]; // @[package.scala:163:13] wire pma_checker__state_vec_0_T_2 = pma_checker__state_vec_0_T_1; // @[package.scala:163:13] wire pma_checker__state_vec_0_T_3 = ~pma_checker__state_vec_0_T_2; // @[Replacement.scala:218:{7,17}] wire pma_checker__state_vec_0_T_4 = ~pma_checker_state_vec_0_set_left_older_1 & pma_checker__state_vec_0_T_3; // @[Replacement.scala:196:33, :203:16, :218:7] wire pma_checker__state_vec_0_T_6 = pma_checker__state_vec_0_T_5; // @[Replacement.scala:207:62, :218:17] wire pma_checker__state_vec_0_T_7 = ~pma_checker__state_vec_0_T_6; // @[Replacement.scala:218:{7,17}] wire pma_checker__state_vec_0_T_8 = pma_checker_state_vec_0_set_left_older_1 & pma_checker__state_vec_0_T_7; // @[Replacement.scala:196:33, :206:16, :218:7] wire [1:0] pma_checker_state_vec_0_hi = {pma_checker_state_vec_0_set_left_older_1, pma_checker__state_vec_0_T_4}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] pma_checker__state_vec_0_T_9 = {pma_checker_state_vec_0_hi, pma_checker__state_vec_0_T_8}; // @[Replacement.scala:202:12, :206:16] wire [2:0] pma_checker__state_vec_0_T_10 = pma_checker_state_vec_0_set_left_older ? 3'h0 : pma_checker__state_vec_0_T_9; // @[Replacement.scala:196:33, :202:12, :203:16] wire pma_checker__state_vec_0_set_left_older_T_2 = pma_checker__state_vec_0_T_11[1]; // @[Replacement.scala:196:43, :207:62] wire pma_checker_state_vec_0_set_left_older_2 = ~pma_checker__state_vec_0_set_left_older_T_2; // @[Replacement.scala:196:{33,43}] wire pma_checker__state_vec_0_T_12 = pma_checker__state_vec_0_T_11[0]; // @[package.scala:163:13] wire pma_checker__state_vec_0_T_16 = pma_checker__state_vec_0_T_11[0]; // @[package.scala:163:13] wire pma_checker__state_vec_0_T_13 = pma_checker__state_vec_0_T_12; // @[package.scala:163:13] wire pma_checker__state_vec_0_T_14 = ~pma_checker__state_vec_0_T_13; // @[Replacement.scala:218:{7,17}] wire pma_checker__state_vec_0_T_15 = ~pma_checker_state_vec_0_set_left_older_2 & pma_checker__state_vec_0_T_14; // @[Replacement.scala:196:33, :203:16, :218:7] wire pma_checker__state_vec_0_T_17 = pma_checker__state_vec_0_T_16; // @[Replacement.scala:207:62, :218:17] wire pma_checker__state_vec_0_T_18 = ~pma_checker__state_vec_0_T_17; // @[Replacement.scala:218:{7,17}] wire pma_checker__state_vec_0_T_19 = pma_checker_state_vec_0_set_left_older_2 & pma_checker__state_vec_0_T_18; // @[Replacement.scala:196:33, :206:16, :218:7] wire [1:0] pma_checker_state_vec_0_hi_1 = {pma_checker_state_vec_0_set_left_older_2, pma_checker__state_vec_0_T_15}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] pma_checker__state_vec_0_T_20 = {pma_checker_state_vec_0_hi_1, pma_checker__state_vec_0_T_19}; // @[Replacement.scala:202:12, :206:16] wire [2:0] pma_checker__state_vec_0_T_21 = pma_checker_state_vec_0_set_left_older ? pma_checker__state_vec_0_T_20 : 3'h0; // @[Replacement.scala:196:33, :202:12, :206:16] wire [3:0] pma_checker_state_vec_0_hi_2 = {pma_checker_state_vec_0_set_left_older, pma_checker__state_vec_0_T_10}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [6:0] pma_checker__state_vec_0_T_22 = {pma_checker_state_vec_0_hi_2, pma_checker__state_vec_0_T_21}; // @[Replacement.scala:202:12, :206:16] wire [1:0] pma_checker_lo_3 = {pma_checker_superpage_hits_1, pma_checker_superpage_hits_0}; // @[OneHot.scala:21:45] wire [1:0] pma_checker_lo_4 = pma_checker_lo_3; // @[OneHot.scala:21:45, :31:18] wire [1:0] pma_checker_hi_3 = {pma_checker_superpage_hits_3, pma_checker_superpage_hits_2}; // @[OneHot.scala:21:45] wire [1:0] pma_checker_hi_4 = pma_checker_hi_3; // @[OneHot.scala:21:45, :30:18] wire [1:0] pma_checker_state_reg_touch_way_sized = {|pma_checker_hi_4, pma_checker_hi_4[1] | pma_checker_lo_4[1]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}] wire pma_checker__state_reg_set_left_older_T = pma_checker_state_reg_touch_way_sized[1]; // @[package.scala:163:13] wire pma_checker_state_reg_set_left_older = ~pma_checker__state_reg_set_left_older_T; // @[Replacement.scala:196:{33,43}] wire pma_checker__state_reg_T = pma_checker_state_reg_touch_way_sized[0]; // @[package.scala:163:13] wire pma_checker__state_reg_T_4 = pma_checker_state_reg_touch_way_sized[0]; // @[package.scala:163:13] wire pma_checker__state_reg_T_1 = pma_checker__state_reg_T; // @[package.scala:163:13] wire pma_checker__state_reg_T_2 = ~pma_checker__state_reg_T_1; // @[Replacement.scala:218:{7,17}] wire pma_checker__state_reg_T_3 = ~pma_checker_state_reg_set_left_older & pma_checker__state_reg_T_2; // @[Replacement.scala:196:33, :203:16, :218:7] wire pma_checker__state_reg_T_5 = pma_checker__state_reg_T_4; // @[Replacement.scala:207:62, :218:17] wire pma_checker__state_reg_T_6 = ~pma_checker__state_reg_T_5; // @[Replacement.scala:218:{7,17}] wire pma_checker__state_reg_T_7 = pma_checker_state_reg_set_left_older & pma_checker__state_reg_T_6; // @[Replacement.scala:196:33, :206:16, :218:7] wire [1:0] pma_checker_state_reg_hi = {pma_checker_state_reg_set_left_older, pma_checker__state_reg_T_3}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] pma_checker__state_reg_T_8 = {pma_checker_state_reg_hi, pma_checker__state_reg_T_7}; // @[Replacement.scala:202:12, :206:16] wire [13:0] pma_checker__io_resp_pf_ld_T_1 = pma_checker_pf_ld_array & 14'h2000; // @[TLB.scala:597:24, :633:57] wire pma_checker__io_resp_pf_ld_T_2 = |pma_checker__io_resp_pf_ld_T_1; // @[TLB.scala:633:{57,65}] assign pma_checker__io_resp_pf_ld_T_3 = pma_checker__io_resp_pf_ld_T_2; // @[TLB.scala:633:{41,65}] assign pma_checker_io_resp_pf_ld = pma_checker__io_resp_pf_ld_T_3; // @[TLB.scala:633:41] wire [13:0] pma_checker__io_resp_pf_st_T_1 = pma_checker_pf_st_array & 14'h2000; // @[TLB.scala:598:24, :634:64] wire pma_checker__io_resp_pf_st_T_2 = |pma_checker__io_resp_pf_st_T_1; // @[TLB.scala:634:{64,72}] assign pma_checker__io_resp_pf_st_T_3 = pma_checker__io_resp_pf_st_T_2; // @[TLB.scala:634:{48,72}] assign pma_checker_io_resp_pf_st = pma_checker__io_resp_pf_st_T_3; // @[TLB.scala:634:48] wire [13:0] pma_checker__io_resp_pf_inst_T = pma_checker_pf_inst_array & 14'h2000; // @[TLB.scala:599:67, :635:47] wire pma_checker__io_resp_pf_inst_T_1 = |pma_checker__io_resp_pf_inst_T; // @[TLB.scala:635:{47,55}] assign pma_checker__io_resp_pf_inst_T_2 = pma_checker__io_resp_pf_inst_T_1; // @[TLB.scala:635:{29,55}] assign pma_checker_io_resp_pf_inst = pma_checker__io_resp_pf_inst_T_2; // @[TLB.scala:635:29] wire [13:0] pma_checker__io_resp_ae_ld_T = pma_checker_ae_ld_array & 14'h2000; // @[TLB.scala:586:24, :641:33] assign pma_checker__io_resp_ae_ld_T_1 = |pma_checker__io_resp_ae_ld_T; // @[TLB.scala:641:{33,41}] assign pma_checker_io_resp_ae_ld = pma_checker__io_resp_ae_ld_T_1; // @[TLB.scala:641:41] wire [13:0] pma_checker__io_resp_ae_st_T = pma_checker_ae_st_array & 14'h2000; // @[TLB.scala:590:53, :642:33] assign pma_checker__io_resp_ae_st_T_1 = |pma_checker__io_resp_ae_st_T; // @[TLB.scala:642:{33,41}] assign pma_checker_io_resp_ae_st = pma_checker__io_resp_ae_st_T_1; // @[TLB.scala:642:41] wire [13:0] pma_checker__io_resp_ae_inst_T = ~pma_checker_px_array; // @[TLB.scala:533:87, :643:23] wire [13:0] pma_checker__io_resp_ae_inst_T_1 = pma_checker__io_resp_ae_inst_T & 14'h2000; // @[TLB.scala:643:{23,33}] assign pma_checker__io_resp_ae_inst_T_2 = |pma_checker__io_resp_ae_inst_T_1; // @[TLB.scala:643:{33,41}] assign pma_checker_io_resp_ae_inst = pma_checker__io_resp_ae_inst_T_2; // @[TLB.scala:643:41] assign pma_checker__io_resp_ma_ld_T = pma_checker_misaligned & pma_checker_cmd_read; // @[TLB.scala:550:77, :645:31] assign pma_checker_io_resp_ma_ld = pma_checker__io_resp_ma_ld_T; // @[TLB.scala:645:31] assign pma_checker__io_resp_ma_st_T = pma_checker_misaligned & pma_checker_cmd_write; // @[TLB.scala:550:77, :646:31] assign pma_checker_io_resp_ma_st = pma_checker__io_resp_ma_st_T; // @[TLB.scala:646:31] wire [13:0] pma_checker__io_resp_cacheable_T = pma_checker_c_array & 14'h2000; // @[TLB.scala:537:20, :648:33] assign pma_checker__io_resp_cacheable_T_1 = |pma_checker__io_resp_cacheable_T; // @[TLB.scala:648:{33,41}] assign pma_checker_io_resp_cacheable = pma_checker__io_resp_cacheable_T_1; // @[TLB.scala:648:41] wire [13:0] pma_checker__io_resp_must_alloc_T = pma_checker_must_alloc_array & 14'h2000; // @[TLB.scala:595:46, :649:43] assign pma_checker__io_resp_must_alloc_T_1 = |pma_checker__io_resp_must_alloc_T; // @[TLB.scala:649:{43,51}] assign pma_checker_io_resp_must_alloc = pma_checker__io_resp_must_alloc_T_1; // @[TLB.scala:649:51] wire [13:0] pma_checker__io_resp_prefetchable_T = pma_checker_prefetchable_array & 14'h2000; // @[TLB.scala:547:31, :650:47] wire pma_checker__io_resp_prefetchable_T_1 = |pma_checker__io_resp_prefetchable_T; // @[TLB.scala:650:{47,55}] assign pma_checker__io_resp_prefetchable_T_2 = pma_checker__io_resp_prefetchable_T_1; // @[TLB.scala:650:{55,59}] assign pma_checker_io_resp_prefetchable = pma_checker__io_resp_prefetchable_T_2; // @[TLB.scala:650:59] assign pma_checker__io_resp_paddr_T_1 = {pma_checker_ppn, pma_checker__io_resp_paddr_T}; // @[Mux.scala:30:73] assign pma_checker_io_resp_paddr = pma_checker__io_resp_paddr_T_1; // @[TLB.scala:652:23] wire [21:0] pma_checker__io_resp_gpa_page_T_1 = {1'h0, pma_checker_vpn}; // @[TLB.scala:335:30, :657:36] wire [21:0] pma_checker_io_resp_gpa_page = pma_checker__io_resp_gpa_page_T_1; // @[TLB.scala:657:{19,36}] wire [11:0] pma_checker_io_resp_gpa_offset = pma_checker__io_resp_gpa_offset_T_1; // @[TLB.scala:658:{21,82}] assign pma_checker__io_resp_gpa_T = {pma_checker_io_resp_gpa_page, pma_checker_io_resp_gpa_offset}; // @[TLB.scala:657:19, :658:21, :659:8] assign pma_checker_io_resp_gpa = pma_checker__io_resp_gpa_T; // @[TLB.scala:659:8] wire replace; // @[Replacement.scala:37:29] wire [1:0] lfsr_lo_lo_lo = {_lfsr_prng_io_out_1, _lfsr_prng_io_out_0}; // @[PRNG.scala:91:22, :95:17] wire [1:0] lfsr_lo_lo_hi = {_lfsr_prng_io_out_3, _lfsr_prng_io_out_2}; // @[PRNG.scala:91:22, :95:17] wire [3:0] lfsr_lo_lo = {lfsr_lo_lo_hi, lfsr_lo_lo_lo}; // @[PRNG.scala:95:17] wire [1:0] lfsr_lo_hi_lo = {_lfsr_prng_io_out_5, _lfsr_prng_io_out_4}; // @[PRNG.scala:91:22, :95:17] wire [1:0] lfsr_lo_hi_hi = {_lfsr_prng_io_out_7, _lfsr_prng_io_out_6}; // @[PRNG.scala:91:22, :95:17] wire [3:0] lfsr_lo_hi = {lfsr_lo_hi_hi, lfsr_lo_hi_lo}; // @[PRNG.scala:95:17] wire [7:0] lfsr_lo = {lfsr_lo_hi, lfsr_lo_lo}; // @[PRNG.scala:95:17] wire [1:0] lfsr_hi_lo_lo = {_lfsr_prng_io_out_9, _lfsr_prng_io_out_8}; // @[PRNG.scala:91:22, :95:17] wire [1:0] lfsr_hi_lo_hi = {_lfsr_prng_io_out_11, _lfsr_prng_io_out_10}; // @[PRNG.scala:91:22, :95:17] wire [3:0] lfsr_hi_lo = {lfsr_hi_lo_hi, lfsr_hi_lo_lo}; // @[PRNG.scala:95:17] wire [1:0] lfsr_hi_hi_lo = {_lfsr_prng_io_out_13, _lfsr_prng_io_out_12}; // @[PRNG.scala:91:22, :95:17] wire [1:0] lfsr_hi_hi_hi = {_lfsr_prng_io_out_15, _lfsr_prng_io_out_14}; // @[PRNG.scala:91:22, :95:17] wire [3:0] lfsr_hi_hi = {lfsr_hi_hi_hi, lfsr_hi_hi_lo}; // @[PRNG.scala:95:17] wire [7:0] lfsr_hi = {lfsr_hi_hi, lfsr_hi_lo}; // @[PRNG.scala:95:17] wire [15:0] lfsr = {lfsr_hi, lfsr_lo}; // @[PRNG.scala:95:17] wire [33:0] _metaArb_io_in_5_bits_addr_T_2; // @[DCache.scala:1018:36] wire [33:0] _metaArb_io_in_1_bits_addr_T_2; // @[DCache.scala:454:36] wire [7:0] _metaArb_io_in_1_bits_idx_T_2; // @[DCache.scala:453:35] wire _metaArb_io_in_2_valid_T; // @[DCache.scala:462:63] wire metaArb__grant_T_1 = metaArb_io_in_2_valid; // @[Arbiter.scala:45:68] wire [33:0] _metaArb_io_in_2_bits_addr_T_2; // @[DCache.scala:466:36] wire [7:0] _metaArb_io_in_2_bits_idx_T; // @[DCache.scala:465:40] wire [19:0] _metaArb_io_in_2_bits_data_T_1; // @[DCache.scala:467:97] wire metaArb__io_in_3_ready_T; // @[Arbiter.scala:153:19] wire _metaArb_io_in_3_valid_T_2; // @[DCache.scala:741:53] wire [33:0] _metaArb_io_in_3_bits_addr_T_2; // @[DCache.scala:745:36] wire [7:0] _metaArb_io_in_3_bits_idx_T; // @[DCache.scala:744:40] wire [19:0] _metaArb_io_in_3_bits_data_T_18; // @[DCache.scala:746:134] wire metaArb__io_in_4_ready_T; // @[Arbiter.scala:153:19] wire [33:0] _metaArb_io_in_4_bits_addr_T_2; // @[DCache.scala:912:36] wire releaseWay; // @[DCache.scala:232:24] wire [19:0] _metaArb_io_in_4_bits_data_T_1; // @[DCache.scala:913:97] wire metaArb__io_in_5_ready_T; // @[Arbiter.scala:153:19] wire metaArb__io_in_6_ready_T; // @[Arbiter.scala:153:19] wire [33:0] _metaArb_io_in_6_bits_addr_T_1; // @[DCache.scala:773:36] wire metaArb__io_in_7_ready_T; // @[Arbiter.scala:153:19] wire [7:0] _metaArb_io_in_7_bits_idx_T; // @[DCache.scala:263:58] wire metaArb__io_out_valid_T_1; // @[Arbiter.scala:154:31] wire [33:0] metaArb_io_in_0_bits_addr; // @[DCache.scala:135:28] wire [33:0] metaArb_io_in_1_bits_addr; // @[DCache.scala:135:28] wire [7:0] metaArb_io_in_1_bits_idx; // @[DCache.scala:135:28] wire [33:0] metaArb_io_in_2_bits_addr; // @[DCache.scala:135:28] wire [7:0] metaArb_io_in_2_bits_idx; // @[DCache.scala:135:28] wire metaArb_io_in_2_bits_way_en; // @[DCache.scala:135:28] wire [19:0] metaArb_io_in_2_bits_data; // @[DCache.scala:135:28] wire [33:0] metaArb_io_in_3_bits_addr; // @[DCache.scala:135:28] wire [7:0] metaArb_io_in_3_bits_idx; // @[DCache.scala:135:28] wire metaArb_io_in_3_bits_way_en; // @[DCache.scala:135:28] wire [19:0] metaArb_io_in_3_bits_data; // @[DCache.scala:135:28] wire metaArb_io_in_3_ready; // @[DCache.scala:135:28] wire metaArb_io_in_3_valid; // @[DCache.scala:135:28] wire [33:0] metaArb_io_in_4_bits_addr; // @[DCache.scala:135:28] wire metaArb_io_in_4_bits_way_en; // @[DCache.scala:135:28] wire [19:0] metaArb_io_in_4_bits_data; // @[DCache.scala:135:28] wire metaArb_io_in_4_ready; // @[DCache.scala:135:28] wire [33:0] metaArb_io_in_5_bits_addr; // @[DCache.scala:135:28] wire metaArb_io_in_5_bits_way_en; // @[DCache.scala:135:28] wire [19:0] metaArb_io_in_5_bits_data; // @[DCache.scala:135:28] wire metaArb_io_in_5_ready; // @[DCache.scala:135:28] wire [33:0] metaArb_io_in_6_bits_addr; // @[DCache.scala:135:28] wire metaArb_io_in_6_bits_way_en; // @[DCache.scala:135:28] wire [19:0] metaArb_io_in_6_bits_data; // @[DCache.scala:135:28] wire metaArb_io_in_6_ready; // @[DCache.scala:135:28] wire [7:0] metaArb_io_in_7_bits_idx; // @[DCache.scala:135:28] wire metaArb_io_in_7_bits_way_en; // @[DCache.scala:135:28] wire [19:0] metaArb_io_in_7_bits_data; // @[DCache.scala:135:28] wire metaArb_io_in_7_ready; // @[DCache.scala:135:28] wire metaArb_io_out_bits_write; // @[DCache.scala:135:28] wire [33:0] metaArb_io_out_bits_addr; // @[DCache.scala:135:28] wire [7:0] metaArb_io_out_bits_idx; // @[DCache.scala:135:28] wire metaArb_io_out_bits_way_en; // @[DCache.scala:135:28] wire [19:0] metaArb_io_out_bits_data; // @[DCache.scala:135:28] wire metaArb_io_out_valid; // @[DCache.scala:135:28] wire [2:0] metaArb_io_chosen; // @[DCache.scala:135:28] assign metaArb_io_chosen = metaArb_io_in_2_valid ? 3'h2 : {~metaArb_io_in_3_valid, 2'h3}; // @[Arbiter.scala:145:26, :146:17] assign metaArb_io_out_bits_addr = metaArb_io_in_2_valid ? metaArb_io_in_2_bits_addr : metaArb_io_in_3_valid ? metaArb_io_in_3_bits_addr : metaArb_io_in_7_bits_addr; // @[Arbiter.scala:145:26, :147:19] assign metaArb_io_out_bits_idx = metaArb_io_in_2_valid ? metaArb_io_in_2_bits_idx : metaArb_io_in_3_valid ? metaArb_io_in_3_bits_idx : metaArb_io_in_7_bits_idx; // @[Arbiter.scala:145:26, :147:19] assign metaArb_io_out_bits_way_en = metaArb_io_in_2_valid ? metaArb_io_in_2_bits_way_en : metaArb_io_in_3_valid ? metaArb_io_in_3_bits_way_en : metaArb_io_in_7_bits_way_en; // @[Arbiter.scala:145:26, :147:19] assign metaArb_io_out_bits_data = metaArb_io_in_2_valid ? metaArb_io_in_2_bits_data : metaArb_io_in_3_valid ? metaArb_io_in_3_bits_data : metaArb_io_in_7_bits_data; // @[Arbiter.scala:145:26, :147:19] assign metaArb_io_out_bits_write = metaArb_io_in_2_valid | metaArb_io_in_3_valid; // @[Arbiter.scala:145:26, :147:19] wire metaArb__grant_T_2 = metaArb__grant_T_1 | metaArb_io_in_3_valid; // @[Arbiter.scala:45:68] wire metaArb__grant_T_3 = metaArb__grant_T_2; // @[Arbiter.scala:45:68] wire metaArb__grant_T_4 = metaArb__grant_T_3; // @[Arbiter.scala:45:68] wire metaArb__grant_T_5 = metaArb__grant_T_4; // @[Arbiter.scala:45:68] wire metaArb_grant_3 = ~metaArb__grant_T_1; // @[Arbiter.scala:45:{68,78}] assign metaArb__io_in_3_ready_T = metaArb_grant_3; // @[Arbiter.scala:45:78, :153:19] wire metaArb_grant_4 = ~metaArb__grant_T_2; // @[Arbiter.scala:45:{68,78}] assign metaArb__io_in_4_ready_T = metaArb_grant_4; // @[Arbiter.scala:45:78, :153:19] wire metaArb_grant_5 = ~metaArb__grant_T_3; // @[Arbiter.scala:45:{68,78}] assign metaArb__io_in_5_ready_T = metaArb_grant_5; // @[Arbiter.scala:45:78, :153:19] wire metaArb_grant_6 = ~metaArb__grant_T_4; // @[Arbiter.scala:45:{68,78}] assign metaArb__io_in_6_ready_T = metaArb_grant_6; // @[Arbiter.scala:45:78, :153:19] wire metaArb_grant_7 = ~metaArb__grant_T_5; // @[Arbiter.scala:45:{68,78}] assign metaArb__io_in_7_ready_T = metaArb_grant_7; // @[Arbiter.scala:45:78, :153:19] assign metaArb_io_in_3_ready = metaArb__io_in_3_ready_T; // @[Arbiter.scala:153:19] assign metaArb_io_in_4_ready = metaArb__io_in_4_ready_T; // @[Arbiter.scala:153:19] assign metaArb_io_in_5_ready = metaArb__io_in_5_ready_T; // @[Arbiter.scala:153:19] assign metaArb_io_in_6_ready = metaArb__io_in_6_ready_T; // @[Arbiter.scala:153:19] assign metaArb_io_in_7_ready = metaArb__io_in_7_ready_T; // @[Arbiter.scala:153:19] wire metaArb__io_out_valid_T = ~metaArb_grant_7; // @[Arbiter.scala:45:78, :154:19] assign metaArb__io_out_valid_T_1 = metaArb__io_out_valid_T | metaArb_io_in_7_valid; // @[Arbiter.scala:154:{19,31}] assign metaArb_io_out_valid = metaArb__io_out_valid_T_1; // @[Arbiter.scala:154:31] wire _dataArb_io_in_0_valid_T_12; // @[DCache.scala:516:27] wire pstore_drain; // @[DCache.scala:516:27] wire [63:0] _dataArb_io_in_0_bits_wdata_T_9; // @[package.scala:45:27] wire [7:0] _dataArb_io_in_0_bits_eccMask_T_17; // @[package.scala:45:27] wire _dataArb_io_in_0_bits_way_en_T; // @[DCache.scala:550:38] wire dataArb__io_in_1_ready_T; // @[Arbiter.scala:153:19] wire dataArb__io_in_2_ready_T; // @[Arbiter.scala:153:19] wire [13:0] _dataArb_io_in_2_bits_addr_T_4; // @[DCache.scala:903:72] wire dataArb__io_in_3_ready_T; // @[Arbiter.scala:153:19] wire _dataArb_io_in_3_valid_T_58; // @[DCache.scala:242:46] wire dataArb__io_out_valid_T_1; // @[Arbiter.scala:154:31] wire [13:0] dataArb_io_in_0_bits_addr; // @[DCache.scala:152:28] wire dataArb_io_in_0_bits_write; // @[DCache.scala:152:28] wire [63:0] dataArb_io_in_0_bits_wdata; // @[DCache.scala:152:28] wire dataArb_io_in_0_bits_wordMask; // @[DCache.scala:152:28] wire [7:0] dataArb_io_in_0_bits_eccMask; // @[DCache.scala:152:28] wire dataArb_io_in_0_bits_way_en; // @[DCache.scala:152:28] wire dataArb_io_in_0_valid; // @[DCache.scala:152:28] wire [13:0] dataArb_io_in_1_bits_addr; // @[DCache.scala:152:28] wire dataArb_io_in_1_bits_write; // @[DCache.scala:152:28] wire [63:0] dataArb_io_in_1_bits_wdata; // @[DCache.scala:152:28] wire dataArb_io_in_1_bits_wordMask; // @[DCache.scala:152:28] wire [7:0] dataArb_io_in_1_bits_eccMask; // @[DCache.scala:152:28] wire dataArb_io_in_1_bits_way_en; // @[DCache.scala:152:28] wire dataArb_io_in_1_ready; // @[DCache.scala:152:28] wire dataArb_io_in_1_valid; // @[DCache.scala:152:28] wire [13:0] dataArb_io_in_2_bits_addr; // @[DCache.scala:152:28] wire [63:0] dataArb_io_in_2_bits_wdata; // @[DCache.scala:152:28] wire dataArb_io_in_2_ready; // @[DCache.scala:152:28] wire [13:0] dataArb_io_in_3_bits_addr; // @[DCache.scala:152:28] wire [63:0] dataArb_io_in_3_bits_wdata; // @[DCache.scala:152:28] wire dataArb_io_in_3_ready; // @[DCache.scala:152:28] wire dataArb_io_in_3_valid; // @[DCache.scala:152:28] wire [13:0] dataArb_io_out_bits_addr; // @[DCache.scala:152:28] wire dataArb_io_out_bits_write; // @[DCache.scala:152:28] wire [63:0] dataArb_io_out_bits_wdata; // @[DCache.scala:152:28] wire dataArb_io_out_bits_wordMask; // @[DCache.scala:152:28] wire [7:0] dataArb_io_out_bits_eccMask; // @[DCache.scala:152:28] wire dataArb_io_out_bits_way_en; // @[DCache.scala:152:28] wire dataArb_io_out_valid; // @[DCache.scala:152:28] wire [1:0] dataArb_io_chosen; // @[DCache.scala:152:28] assign dataArb_io_chosen = dataArb_io_in_0_valid ? 2'h0 : {~dataArb_io_in_1_valid, 1'h1}; // @[Arbiter.scala:145:26, :146:17] assign dataArb_io_out_bits_addr = dataArb_io_in_0_valid ? dataArb_io_in_0_bits_addr : dataArb_io_in_1_valid ? dataArb_io_in_1_bits_addr : dataArb_io_in_3_bits_addr; // @[Arbiter.scala:145:26, :147:19] assign dataArb_io_out_bits_write = dataArb_io_in_0_valid ? dataArb_io_in_0_bits_write : dataArb_io_in_1_valid & dataArb_io_in_1_bits_write; // @[Arbiter.scala:145:26, :147:19] assign dataArb_io_out_bits_wdata = dataArb_io_in_0_valid ? dataArb_io_in_0_bits_wdata : dataArb_io_in_1_valid ? dataArb_io_in_1_bits_wdata : dataArb_io_in_3_bits_wdata; // @[Arbiter.scala:145:26, :147:19] assign dataArb_io_out_bits_wordMask = dataArb_io_in_0_valid ? dataArb_io_in_0_bits_wordMask : ~dataArb_io_in_1_valid | dataArb_io_in_1_bits_wordMask; // @[Arbiter.scala:145:26, :146:17, :147:19] assign dataArb_io_out_bits_eccMask = dataArb_io_in_0_valid ? dataArb_io_in_0_bits_eccMask : dataArb_io_in_1_valid ? dataArb_io_in_1_bits_eccMask : 8'hFF; // @[Arbiter.scala:145:26, :147:19] assign dataArb_io_out_bits_way_en = dataArb_io_in_0_valid ? dataArb_io_in_0_bits_way_en : ~dataArb_io_in_1_valid | dataArb_io_in_1_bits_way_en; // @[Arbiter.scala:145:26, :146:17, :147:19] wire dataArb__grant_T = dataArb_io_in_0_valid | dataArb_io_in_1_valid; // @[Arbiter.scala:45:68] wire dataArb__grant_T_1 = dataArb__grant_T; // @[Arbiter.scala:45:68] wire dataArb_grant_1 = ~dataArb_io_in_0_valid; // @[Arbiter.scala:45:78] assign dataArb__io_in_1_ready_T = dataArb_grant_1; // @[Arbiter.scala:45:78, :153:19] wire dataArb_grant_2 = ~dataArb__grant_T; // @[Arbiter.scala:45:{68,78}] assign dataArb__io_in_2_ready_T = dataArb_grant_2; // @[Arbiter.scala:45:78, :153:19] wire dataArb_grant_3 = ~dataArb__grant_T_1; // @[Arbiter.scala:45:{68,78}] assign dataArb__io_in_3_ready_T = dataArb_grant_3; // @[Arbiter.scala:45:78, :153:19] assign dataArb_io_in_1_ready = dataArb__io_in_1_ready_T; // @[Arbiter.scala:153:19] assign dataArb_io_in_2_ready = dataArb__io_in_2_ready_T; // @[Arbiter.scala:153:19] assign dataArb_io_in_3_ready = dataArb__io_in_3_ready_T; // @[Arbiter.scala:153:19] wire dataArb__io_out_valid_T = ~dataArb_grant_3; // @[Arbiter.scala:45:78, :154:19] assign dataArb__io_out_valid_T_1 = dataArb__io_out_valid_T | dataArb_io_in_3_valid; // @[Arbiter.scala:154:{19,31}] assign dataArb_io_out_valid = dataArb__io_out_valid_T_1; // @[Arbiter.scala:154:31] wire _tl_out_a_valid_T_14; // @[DCache.scala:603:37] assign nodeOut_a_deq_valid = tl_out_a_valid; // @[Decoupled.scala:356:21] wire [2:0] _tl_out_a_bits_T_7_opcode; // @[DCache.scala:608:23] assign nodeOut_a_deq_bits_opcode = tl_out_a_bits_opcode; // @[Decoupled.scala:356:21] wire [2:0] _tl_out_a_bits_T_7_param; // @[DCache.scala:608:23] assign nodeOut_a_deq_bits_param = tl_out_a_bits_param; // @[Decoupled.scala:356:21] wire [3:0] _tl_out_a_bits_T_7_size; // @[DCache.scala:608:23] assign nodeOut_a_deq_bits_size = tl_out_a_bits_size; // @[Decoupled.scala:356:21] wire [31:0] _tl_out_a_bits_T_7_address; // @[DCache.scala:608:23] assign nodeOut_a_deq_bits_address = tl_out_a_bits_address; // @[Decoupled.scala:356:21] wire [7:0] _tl_out_a_bits_T_7_mask; // @[DCache.scala:608:23] assign nodeOut_a_deq_bits_mask = tl_out_a_bits_mask; // @[Decoupled.scala:356:21] wire [63:0] _tl_out_a_bits_T_7_data; // @[DCache.scala:608:23] assign nodeOut_a_deq_bits_data = tl_out_a_bits_data; // @[Decoupled.scala:356:21] wire tl_out_a_ready; // @[DCache.scala:159:22] assign tl_out_a_ready = nodeOut_a_deq_ready; // @[Decoupled.scala:356:21] assign nodeOut_a_valid = nodeOut_a_deq_valid; // @[Decoupled.scala:356:21] assign nodeOut_a_bits_opcode = nodeOut_a_deq_bits_opcode; // @[Decoupled.scala:356:21] assign nodeOut_a_bits_param = nodeOut_a_deq_bits_param; // @[Decoupled.scala:356:21] assign nodeOut_a_bits_size = nodeOut_a_deq_bits_size; // @[Decoupled.scala:356:21] assign nodeOut_a_bits_address = nodeOut_a_deq_bits_address; // @[Decoupled.scala:356:21] assign nodeOut_a_bits_mask = nodeOut_a_deq_bits_mask; // @[Decoupled.scala:356:21] assign nodeOut_a_bits_data = nodeOut_a_deq_bits_data; // @[Decoupled.scala:356:21] wire _tl_out_c_valid_T_6; // @[DCache.scala:810:117] wire tl_out_c_valid; // @[Bundles.scala:265:61] wire _s1_valid_T = io_cpu_req_ready_0 & io_cpu_req_valid_0; // @[Decoupled.scala:51:35] reg s1_valid; // @[DCache.scala:182:25] wire _s2_data_en_T = s1_valid; // @[DCache.scala:182:25, :366:23] wire s1_nack; // @[DCache.scala:185:28] wire _s1_valid_masked_T = ~io_cpu_s1_kill_0; // @[DCache.scala:101:7, :186:37] wire s1_valid_masked = s1_valid & _s1_valid_masked_T; // @[DCache.scala:182:25, :186:{34,37}] wire _s1_valid_not_nacked_T = ~s1_nack; // @[DCache.scala:185:28, :187:41] wire s1_valid_not_nacked = s1_valid & _s1_valid_not_nacked_T; // @[DCache.scala:182:25, :187:{38,41}] wire _s0_clk_en_T = ~metaArb_io_out_bits_write; // @[DCache.scala:135:28, :190:43] wire s0_clk_en = metaArb_io_out_valid & _s0_clk_en_T; // @[DCache.scala:135:28, :190:{40,43}] wire _s1_tlb_req_T = s0_clk_en; // @[DCache.scala:190:40, :208:52] wire [33:0] _s0_req_addr_T_2; // @[DCache.scala:193:21] wire [33:0] s0_tlb_req_vaddr = s0_req_addr; // @[DCache.scala:192:24, :199:28] wire [4:0] s0_tlb_req_cmd = s0_req_cmd; // @[DCache.scala:192:24, :199:28] wire [1:0] s0_tlb_req_size = s0_req_size; // @[DCache.scala:192:24, :199:28] wire [1:0] s0_tlb_req_prv = s0_req_dprv; // @[DCache.scala:192:24, :199:28] wire s0_tlb_req_v = s0_req_dv; // @[DCache.scala:192:24, :199:28] wire s0_tlb_req_passthrough = s0_req_phys; // @[DCache.scala:192:24, :199:28] wire [27:0] _s0_req_addr_T = metaArb_io_out_bits_addr[33:6]; // @[DCache.scala:135:28, :193:47] wire [5:0] _s0_req_addr_T_1 = io_cpu_req_bits_addr_0[5:0]; // @[DCache.scala:101:7, :193:84] assign _s0_req_addr_T_2 = {_s0_req_addr_T, _s0_req_addr_T_1}; // @[DCache.scala:193:{21,47,84}] assign s0_req_addr = _s0_req_addr_T_2; // @[DCache.scala:192:24, :193:21] assign s0_req_phys = ~metaArb_io_in_7_ready | io_cpu_req_bits_phys_0; // @[DCache.scala:101:7, :135:28, :192:24, :195:{9,34,48}] reg [33:0] s1_req_addr; // @[DCache.scala:196:25] assign pma_checker_io_req_bits_vaddr = s1_req_addr; // @[DCache.scala:120:32, :196:25] reg [6:0] s1_req_tag; // @[DCache.scala:196:25] reg [4:0] s1_req_cmd; // @[DCache.scala:196:25] assign pma_checker_io_req_bits_cmd = s1_req_cmd; // @[DCache.scala:120:32, :196:25] reg [1:0] s1_req_size; // @[DCache.scala:196:25] assign pma_checker_io_req_bits_size = s1_req_size; // @[DCache.scala:120:32, :196:25] wire [1:0] s1_mask_xwr_size = s1_req_size; // @[DCache.scala:196:25] reg s1_req_signed; // @[DCache.scala:196:25] reg [1:0] s1_req_dprv; // @[DCache.scala:196:25] assign pma_checker_io_req_bits_prv = s1_req_dprv; // @[DCache.scala:120:32, :196:25] reg s1_req_dv; // @[DCache.scala:196:25] assign pma_checker_io_req_bits_v = s1_req_dv; // @[DCache.scala:120:32, :196:25] reg s1_req_phys; // @[DCache.scala:196:25] reg s1_req_no_resp; // @[DCache.scala:196:25] reg s1_req_no_xcpt; // @[DCache.scala:196:25] wire [19:0] _s1_vaddr_T = s1_req_addr[33:14]; // @[DCache.scala:196:25, :197:56] wire [13:0] _s1_vaddr_T_1 = s1_req_addr[13:0]; // @[DCache.scala:196:25, :197:78] wire [33:0] s1_vaddr = {_s1_vaddr_T, _s1_vaddr_T_1}; // @[DCache.scala:197:{21,56,78}] reg [33:0] s1_tlb_req_vaddr; // @[DCache.scala:208:29] reg s1_tlb_req_passthrough; // @[DCache.scala:208:29] reg [1:0] s1_tlb_req_size; // @[DCache.scala:208:29] reg [4:0] s1_tlb_req_cmd; // @[DCache.scala:208:29] reg [1:0] s1_tlb_req_prv; // @[DCache.scala:208:29] reg s1_tlb_req_v; // @[DCache.scala:208:29] wire _GEN_39 = s1_req_cmd == 5'h0; // @[package.scala:16:47] wire _s1_read_T; // @[package.scala:16:47] assign _s1_read_T = _GEN_39; // @[package.scala:16:47] wire _pstore1_rmw_T; // @[package.scala:16:47] assign _pstore1_rmw_T = _GEN_39; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_1; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_1 = _GEN_39; // @[package.scala:16:47] wire _GEN_40 = s1_req_cmd == 5'h10; // @[package.scala:16:47] wire _s1_read_T_1; // @[package.scala:16:47] assign _s1_read_T_1 = _GEN_40; // @[package.scala:16:47] wire _pstore1_rmw_T_1; // @[package.scala:16:47] assign _pstore1_rmw_T_1 = _GEN_40; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_2; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_2 = _GEN_40; // @[package.scala:16:47] wire _GEN_41 = s1_req_cmd == 5'h6; // @[package.scala:16:47] wire _s1_read_T_2; // @[package.scala:16:47] assign _s1_read_T_2 = _GEN_41; // @[package.scala:16:47] wire _pstore1_rmw_T_2; // @[package.scala:16:47] assign _pstore1_rmw_T_2 = _GEN_41; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_3; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_3 = _GEN_41; // @[package.scala:16:47] wire _GEN_42 = s1_req_cmd == 5'h7; // @[package.scala:16:47] wire _s1_read_T_3; // @[package.scala:16:47] assign _s1_read_T_3 = _GEN_42; // @[package.scala:16:47] wire _s1_write_T_3; // @[Consts.scala:90:66] assign _s1_write_T_3 = _GEN_42; // @[package.scala:16:47] wire _pstore1_rmw_T_3; // @[package.scala:16:47] assign _pstore1_rmw_T_3 = _GEN_42; // @[package.scala:16:47] wire _pstore1_rmw_T_28; // @[Consts.scala:90:66] assign _pstore1_rmw_T_28 = _GEN_42; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_4; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_4 = _GEN_42; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_29; // @[Consts.scala:90:66] assign _io_cpu_perf_canAcceptLoadThenLoad_T_29 = _GEN_42; // @[package.scala:16:47] wire _s1_read_T_4 = _s1_read_T | _s1_read_T_1; // @[package.scala:16:47, :81:59] wire _s1_read_T_5 = _s1_read_T_4 | _s1_read_T_2; // @[package.scala:16:47, :81:59] wire _s1_read_T_6 = _s1_read_T_5 | _s1_read_T_3; // @[package.scala:16:47, :81:59] wire _GEN_43 = s1_req_cmd == 5'h4; // @[package.scala:16:47] wire _s1_read_T_7; // @[package.scala:16:47] assign _s1_read_T_7 = _GEN_43; // @[package.scala:16:47] wire _s1_write_T_5; // @[package.scala:16:47] assign _s1_write_T_5 = _GEN_43; // @[package.scala:16:47] wire _pstore1_rmw_T_7; // @[package.scala:16:47] assign _pstore1_rmw_T_7 = _GEN_43; // @[package.scala:16:47] wire _pstore1_rmw_T_30; // @[package.scala:16:47] assign _pstore1_rmw_T_30 = _GEN_43; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_8; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_8 = _GEN_43; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_31; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_31 = _GEN_43; // @[package.scala:16:47] wire _GEN_44 = s1_req_cmd == 5'h9; // @[package.scala:16:47] wire _s1_read_T_8; // @[package.scala:16:47] assign _s1_read_T_8 = _GEN_44; // @[package.scala:16:47] wire _s1_write_T_6; // @[package.scala:16:47] assign _s1_write_T_6 = _GEN_44; // @[package.scala:16:47] wire _pstore1_rmw_T_8; // @[package.scala:16:47] assign _pstore1_rmw_T_8 = _GEN_44; // @[package.scala:16:47] wire _pstore1_rmw_T_31; // @[package.scala:16:47] assign _pstore1_rmw_T_31 = _GEN_44; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_9; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_9 = _GEN_44; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_32; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_32 = _GEN_44; // @[package.scala:16:47] wire _GEN_45 = s1_req_cmd == 5'hA; // @[package.scala:16:47] wire _s1_read_T_9; // @[package.scala:16:47] assign _s1_read_T_9 = _GEN_45; // @[package.scala:16:47] wire _s1_write_T_7; // @[package.scala:16:47] assign _s1_write_T_7 = _GEN_45; // @[package.scala:16:47] wire _pstore1_rmw_T_9; // @[package.scala:16:47] assign _pstore1_rmw_T_9 = _GEN_45; // @[package.scala:16:47] wire _pstore1_rmw_T_32; // @[package.scala:16:47] assign _pstore1_rmw_T_32 = _GEN_45; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_10; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_10 = _GEN_45; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_33; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_33 = _GEN_45; // @[package.scala:16:47] wire _GEN_46 = s1_req_cmd == 5'hB; // @[package.scala:16:47] wire _s1_read_T_10; // @[package.scala:16:47] assign _s1_read_T_10 = _GEN_46; // @[package.scala:16:47] wire _s1_write_T_8; // @[package.scala:16:47] assign _s1_write_T_8 = _GEN_46; // @[package.scala:16:47] wire _pstore1_rmw_T_10; // @[package.scala:16:47] assign _pstore1_rmw_T_10 = _GEN_46; // @[package.scala:16:47] wire _pstore1_rmw_T_33; // @[package.scala:16:47] assign _pstore1_rmw_T_33 = _GEN_46; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_11; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_11 = _GEN_46; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_34; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_34 = _GEN_46; // @[package.scala:16:47] wire _s1_read_T_11 = _s1_read_T_7 | _s1_read_T_8; // @[package.scala:16:47, :81:59] wire _s1_read_T_12 = _s1_read_T_11 | _s1_read_T_9; // @[package.scala:16:47, :81:59] wire _s1_read_T_13 = _s1_read_T_12 | _s1_read_T_10; // @[package.scala:16:47, :81:59] wire _GEN_47 = s1_req_cmd == 5'h8; // @[package.scala:16:47] wire _s1_read_T_14; // @[package.scala:16:47] assign _s1_read_T_14 = _GEN_47; // @[package.scala:16:47] wire _s1_write_T_12; // @[package.scala:16:47] assign _s1_write_T_12 = _GEN_47; // @[package.scala:16:47] wire _pstore1_rmw_T_14; // @[package.scala:16:47] assign _pstore1_rmw_T_14 = _GEN_47; // @[package.scala:16:47] wire _pstore1_rmw_T_37; // @[package.scala:16:47] assign _pstore1_rmw_T_37 = _GEN_47; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_15; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_15 = _GEN_47; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_38; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_38 = _GEN_47; // @[package.scala:16:47] wire _GEN_48 = s1_req_cmd == 5'hC; // @[package.scala:16:47] wire _s1_read_T_15; // @[package.scala:16:47] assign _s1_read_T_15 = _GEN_48; // @[package.scala:16:47] wire _s1_write_T_13; // @[package.scala:16:47] assign _s1_write_T_13 = _GEN_48; // @[package.scala:16:47] wire _pstore1_rmw_T_15; // @[package.scala:16:47] assign _pstore1_rmw_T_15 = _GEN_48; // @[package.scala:16:47] wire _pstore1_rmw_T_38; // @[package.scala:16:47] assign _pstore1_rmw_T_38 = _GEN_48; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_16; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_16 = _GEN_48; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_39; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_39 = _GEN_48; // @[package.scala:16:47] wire _GEN_49 = s1_req_cmd == 5'hD; // @[package.scala:16:47] wire _s1_read_T_16; // @[package.scala:16:47] assign _s1_read_T_16 = _GEN_49; // @[package.scala:16:47] wire _s1_write_T_14; // @[package.scala:16:47] assign _s1_write_T_14 = _GEN_49; // @[package.scala:16:47] wire _pstore1_rmw_T_16; // @[package.scala:16:47] assign _pstore1_rmw_T_16 = _GEN_49; // @[package.scala:16:47] wire _pstore1_rmw_T_39; // @[package.scala:16:47] assign _pstore1_rmw_T_39 = _GEN_49; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_17; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_17 = _GEN_49; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_40; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_40 = _GEN_49; // @[package.scala:16:47] wire _GEN_50 = s1_req_cmd == 5'hE; // @[package.scala:16:47] wire _s1_read_T_17; // @[package.scala:16:47] assign _s1_read_T_17 = _GEN_50; // @[package.scala:16:47] wire _s1_write_T_15; // @[package.scala:16:47] assign _s1_write_T_15 = _GEN_50; // @[package.scala:16:47] wire _pstore1_rmw_T_17; // @[package.scala:16:47] assign _pstore1_rmw_T_17 = _GEN_50; // @[package.scala:16:47] wire _pstore1_rmw_T_40; // @[package.scala:16:47] assign _pstore1_rmw_T_40 = _GEN_50; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_18; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_18 = _GEN_50; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_41; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_41 = _GEN_50; // @[package.scala:16:47] wire _GEN_51 = s1_req_cmd == 5'hF; // @[package.scala:16:47] wire _s1_read_T_18; // @[package.scala:16:47] assign _s1_read_T_18 = _GEN_51; // @[package.scala:16:47] wire _s1_write_T_16; // @[package.scala:16:47] assign _s1_write_T_16 = _GEN_51; // @[package.scala:16:47] wire _pstore1_rmw_T_18; // @[package.scala:16:47] assign _pstore1_rmw_T_18 = _GEN_51; // @[package.scala:16:47] wire _pstore1_rmw_T_41; // @[package.scala:16:47] assign _pstore1_rmw_T_41 = _GEN_51; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_19; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_19 = _GEN_51; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_42; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_42 = _GEN_51; // @[package.scala:16:47] wire _s1_read_T_19 = _s1_read_T_14 | _s1_read_T_15; // @[package.scala:16:47, :81:59] wire _s1_read_T_20 = _s1_read_T_19 | _s1_read_T_16; // @[package.scala:16:47, :81:59] wire _s1_read_T_21 = _s1_read_T_20 | _s1_read_T_17; // @[package.scala:16:47, :81:59] wire _s1_read_T_22 = _s1_read_T_21 | _s1_read_T_18; // @[package.scala:16:47, :81:59] wire _s1_read_T_23 = _s1_read_T_13 | _s1_read_T_22; // @[package.scala:81:59] wire s1_read = _s1_read_T_6 | _s1_read_T_23; // @[package.scala:81:59] wire _GEN_52 = s1_req_cmd == 5'h1; // @[DCache.scala:196:25] wire _s1_write_T; // @[Consts.scala:90:32] assign _s1_write_T = _GEN_52; // @[Consts.scala:90:32] wire _pstore1_rmw_T_25; // @[Consts.scala:90:32] assign _pstore1_rmw_T_25 = _GEN_52; // @[Consts.scala:90:32] wire _io_cpu_perf_canAcceptLoadThenLoad_T_26; // @[Consts.scala:90:32] assign _io_cpu_perf_canAcceptLoadThenLoad_T_26 = _GEN_52; // @[Consts.scala:90:32] wire _T_19 = s1_req_cmd == 5'h11; // @[DCache.scala:196:25] wire _s1_write_T_1; // @[Consts.scala:90:49] assign _s1_write_T_1 = _T_19; // @[Consts.scala:90:49] wire _s1_mask_T; // @[DCache.scala:327:32] assign _s1_mask_T = _T_19; // @[DCache.scala:327:32] wire _pstore1_rmw_T_26; // @[Consts.scala:90:49] assign _pstore1_rmw_T_26 = _T_19; // @[Consts.scala:90:49] wire _pstore1_rmw_T_48; // @[DCache.scala:1191:35] assign _pstore1_rmw_T_48 = _T_19; // @[DCache.scala:1191:35] wire _io_cpu_perf_canAcceptLoadThenLoad_T_27; // @[Consts.scala:90:49] assign _io_cpu_perf_canAcceptLoadThenLoad_T_27 = _T_19; // @[Consts.scala:90:49] wire _io_cpu_perf_canAcceptLoadThenLoad_T_49; // @[DCache.scala:1191:35] assign _io_cpu_perf_canAcceptLoadThenLoad_T_49 = _T_19; // @[DCache.scala:1191:35] wire _s1_write_T_2 = _s1_write_T | _s1_write_T_1; // @[Consts.scala:90:{32,42,49}] wire _s1_write_T_4 = _s1_write_T_2 | _s1_write_T_3; // @[Consts.scala:90:{42,59,66}] wire _s1_write_T_9 = _s1_write_T_5 | _s1_write_T_6; // @[package.scala:16:47, :81:59] wire _s1_write_T_10 = _s1_write_T_9 | _s1_write_T_7; // @[package.scala:16:47, :81:59] wire _s1_write_T_11 = _s1_write_T_10 | _s1_write_T_8; // @[package.scala:16:47, :81:59] wire _s1_write_T_17 = _s1_write_T_12 | _s1_write_T_13; // @[package.scala:16:47, :81:59] wire _s1_write_T_18 = _s1_write_T_17 | _s1_write_T_14; // @[package.scala:16:47, :81:59] wire _s1_write_T_19 = _s1_write_T_18 | _s1_write_T_15; // @[package.scala:16:47, :81:59] wire _s1_write_T_20 = _s1_write_T_19 | _s1_write_T_16; // @[package.scala:16:47, :81:59] wire _s1_write_T_21 = _s1_write_T_11 | _s1_write_T_20; // @[package.scala:81:59] wire s1_write = _s1_write_T_4 | _s1_write_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire s1_readwrite = s1_read | s1_write; // @[DCache.scala:212:30] wire _s1_sfence_T = s1_req_cmd == 5'h14; // @[DCache.scala:196:25, :213:30] wire _GEN_53 = s1_req_cmd == 5'h15; // @[DCache.scala:196:25, :213:57] wire _s1_sfence_T_1; // @[DCache.scala:213:57] assign _s1_sfence_T_1 = _GEN_53; // @[DCache.scala:213:57] wire _tlb_io_sfence_bits_hv_T; // @[DCache.scala:283:39] assign _tlb_io_sfence_bits_hv_T = _GEN_53; // @[DCache.scala:213:57, :283:39] wire _s1_sfence_T_2 = _s1_sfence_T | _s1_sfence_T_1; // @[DCache.scala:213:{30,43,57}] wire _GEN_54 = s1_req_cmd == 5'h16; // @[DCache.scala:196:25, :213:85] wire _s1_sfence_T_3; // @[DCache.scala:213:85] assign _s1_sfence_T_3 = _GEN_54; // @[DCache.scala:213:85] wire _tlb_io_sfence_bits_hg_T; // @[DCache.scala:284:39] assign _tlb_io_sfence_bits_hg_T = _GEN_54; // @[DCache.scala:213:85, :284:39] wire s1_sfence = _s1_sfence_T_2 | _s1_sfence_T_3; // @[DCache.scala:213:{43,71,85}] wire _s1_flush_line_T = s1_req_cmd == 5'h5; // @[DCache.scala:196:25, :214:34] wire _s1_flush_line_T_1 = s1_req_size[0]; // @[DCache.scala:196:25, :214:64] wire _tlb_io_sfence_bits_rs1_T = s1_req_size[0]; // @[DCache.scala:196:25, :214:64, :279:40] wire s1_flush_line = _s1_flush_line_T & _s1_flush_line_T_1; // @[DCache.scala:214:{34,50,64}] reg s1_flush_valid; // @[DCache.scala:215:27] reg cached_grant_wait; // @[DCache.scala:223:34] reg [1:0] refill_way; // @[DCache.scala:229:23] wire _any_pstore_valid_T; // @[DCache.scala:508:36] wire any_pstore_valid; // @[DCache.scala:230:30] assign metaArb_io_in_4_bits_way_en = releaseWay; // @[DCache.scala:135:28, :232:24] assign metaArb_io_in_5_bits_way_en = releaseWay; // @[DCache.scala:135:28, :232:24] assign metaArb_io_in_6_bits_way_en = releaseWay; // @[DCache.scala:135:28, :232:24] assign metaArb_io_in_7_bits_way_en = releaseWay; // @[DCache.scala:135:28, :232:24] wire _io_cpu_req_ready_T_1 = ~cached_grant_wait; // @[DCache.scala:223:34, :233:54] wire _io_cpu_req_ready_T_2 = _io_cpu_req_ready_T_1; // @[DCache.scala:233:{51,54}] wire _io_cpu_req_ready_T_3 = ~s1_nack; // @[DCache.scala:185:28, :187:41, :233:76] wire _io_cpu_req_ready_T_4 = _io_cpu_req_ready_T_2 & _io_cpu_req_ready_T_3; // @[DCache.scala:233:{51,73,76}] reg uncachedInFlight_0; // @[DCache.scala:236:33] wire _s2_valid_cached_miss_T_2 = uncachedInFlight_0; // @[DCache.scala:236:33, :425:88] wire _s2_valid_uncached_pending_T_1 = uncachedInFlight_0; // @[DCache.scala:236:33, :430:92] wire _io_cpu_ordered_T_6 = uncachedInFlight_0; // @[DCache.scala:236:33, :929:142] wire _io_cpu_store_pending_T_24 = uncachedInFlight_0; // @[DCache.scala:236:33, :930:97] wire _clock_en_reg_T_22 = uncachedInFlight_0; // @[DCache.scala:236:33, :1072:50] reg [33:0] uncachedReqs_0_addr; // @[DCache.scala:237:25] wire [33:0] uncachedResp_addr = uncachedReqs_0_addr; // @[DCache.scala:237:25, :238:30] reg [6:0] uncachedReqs_0_tag; // @[DCache.scala:237:25] wire [6:0] uncachedResp_tag = uncachedReqs_0_tag; // @[DCache.scala:237:25, :238:30] reg [4:0] uncachedReqs_0_cmd; // @[DCache.scala:237:25] wire [4:0] uncachedResp_cmd = uncachedReqs_0_cmd; // @[DCache.scala:237:25, :238:30] reg [1:0] uncachedReqs_0_size; // @[DCache.scala:237:25] wire [1:0] uncachedResp_size = uncachedReqs_0_size; // @[DCache.scala:237:25, :238:30] reg uncachedReqs_0_signed; // @[DCache.scala:237:25] wire uncachedResp_signed = uncachedReqs_0_signed; // @[DCache.scala:237:25, :238:30] reg [1:0] uncachedReqs_0_dprv; // @[DCache.scala:237:25] wire [1:0] uncachedResp_dprv = uncachedReqs_0_dprv; // @[DCache.scala:237:25, :238:30] reg uncachedReqs_0_dv; // @[DCache.scala:237:25] wire uncachedResp_dv = uncachedReqs_0_dv; // @[DCache.scala:237:25, :238:30] reg uncachedReqs_0_phys; // @[DCache.scala:237:25] wire uncachedResp_phys = uncachedReqs_0_phys; // @[DCache.scala:237:25, :238:30] reg uncachedReqs_0_no_resp; // @[DCache.scala:237:25] wire uncachedResp_no_resp = uncachedReqs_0_no_resp; // @[DCache.scala:237:25, :238:30] reg uncachedReqs_0_no_alloc; // @[DCache.scala:237:25] wire uncachedResp_no_alloc = uncachedReqs_0_no_alloc; // @[DCache.scala:237:25, :238:30] reg uncachedReqs_0_no_xcpt; // @[DCache.scala:237:25] wire uncachedResp_no_xcpt = uncachedReqs_0_no_xcpt; // @[DCache.scala:237:25, :238:30] reg [63:0] uncachedReqs_0_data; // @[DCache.scala:237:25] wire [63:0] uncachedResp_data = uncachedReqs_0_data; // @[DCache.scala:237:25, :238:30] reg [7:0] uncachedReqs_0_mask; // @[DCache.scala:237:25] wire [7:0] uncachedResp_mask = uncachedReqs_0_mask; // @[DCache.scala:237:25, :238:30] wire _GEN_55 = io_cpu_req_bits_cmd_0 == 5'h0; // @[package.scala:16:47] wire _s0_read_T; // @[package.scala:16:47] assign _s0_read_T = _GEN_55; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T = _GEN_55; // @[package.scala:16:47] wire _s1_did_read_T; // @[package.scala:16:47] assign _s1_did_read_T = _GEN_55; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T = _GEN_55; // @[package.scala:16:47] wire _GEN_56 = io_cpu_req_bits_cmd_0 == 5'h10; // @[package.scala:16:47] wire _s0_read_T_1; // @[package.scala:16:47] assign _s0_read_T_1 = _GEN_56; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_1; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_1 = _GEN_56; // @[package.scala:16:47] wire _s1_did_read_T_1; // @[package.scala:16:47] assign _s1_did_read_T_1 = _GEN_56; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_1; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_1 = _GEN_56; // @[package.scala:16:47] wire _GEN_57 = io_cpu_req_bits_cmd_0 == 5'h6; // @[package.scala:16:47] wire _s0_read_T_2; // @[package.scala:16:47] assign _s0_read_T_2 = _GEN_57; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_2; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_2 = _GEN_57; // @[package.scala:16:47] wire _s1_did_read_T_2; // @[package.scala:16:47] assign _s1_did_read_T_2 = _GEN_57; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_2; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_2 = _GEN_57; // @[package.scala:16:47] wire _GEN_58 = io_cpu_req_bits_cmd_0 == 5'h7; // @[package.scala:16:47] wire _s0_read_T_3; // @[package.scala:16:47] assign _s0_read_T_3 = _GEN_58; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_3; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_3 = _GEN_58; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_28; // @[Consts.scala:90:66] assign _dataArb_io_in_3_valid_T_28 = _GEN_58; // @[package.scala:16:47] wire _s1_did_read_T_3; // @[package.scala:16:47] assign _s1_did_read_T_3 = _GEN_58; // @[package.scala:16:47] wire _s1_did_read_T_28; // @[Consts.scala:90:66] assign _s1_did_read_T_28 = _GEN_58; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_3; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_3 = _GEN_58; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_28; // @[Consts.scala:90:66] assign _pstore_drain_opportunistic_T_28 = _GEN_58; // @[package.scala:16:47] wire _s0_read_T_4 = _s0_read_T | _s0_read_T_1; // @[package.scala:16:47, :81:59] wire _s0_read_T_5 = _s0_read_T_4 | _s0_read_T_2; // @[package.scala:16:47, :81:59] wire _s0_read_T_6 = _s0_read_T_5 | _s0_read_T_3; // @[package.scala:16:47, :81:59] wire _GEN_59 = io_cpu_req_bits_cmd_0 == 5'h4; // @[package.scala:16:47] wire _s0_read_T_7; // @[package.scala:16:47] assign _s0_read_T_7 = _GEN_59; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_7; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_7 = _GEN_59; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_30; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_30 = _GEN_59; // @[package.scala:16:47] wire _s1_did_read_T_7; // @[package.scala:16:47] assign _s1_did_read_T_7 = _GEN_59; // @[package.scala:16:47] wire _s1_did_read_T_30; // @[package.scala:16:47] assign _s1_did_read_T_30 = _GEN_59; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_7; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_7 = _GEN_59; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_30; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_30 = _GEN_59; // @[package.scala:16:47] wire _GEN_60 = io_cpu_req_bits_cmd_0 == 5'h9; // @[package.scala:16:47] wire _s0_read_T_8; // @[package.scala:16:47] assign _s0_read_T_8 = _GEN_60; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_8; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_8 = _GEN_60; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_31; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_31 = _GEN_60; // @[package.scala:16:47] wire _s1_did_read_T_8; // @[package.scala:16:47] assign _s1_did_read_T_8 = _GEN_60; // @[package.scala:16:47] wire _s1_did_read_T_31; // @[package.scala:16:47] assign _s1_did_read_T_31 = _GEN_60; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_8; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_8 = _GEN_60; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_31; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_31 = _GEN_60; // @[package.scala:16:47] wire _GEN_61 = io_cpu_req_bits_cmd_0 == 5'hA; // @[package.scala:16:47] wire _s0_read_T_9; // @[package.scala:16:47] assign _s0_read_T_9 = _GEN_61; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_9; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_9 = _GEN_61; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_32; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_32 = _GEN_61; // @[package.scala:16:47] wire _s1_did_read_T_9; // @[package.scala:16:47] assign _s1_did_read_T_9 = _GEN_61; // @[package.scala:16:47] wire _s1_did_read_T_32; // @[package.scala:16:47] assign _s1_did_read_T_32 = _GEN_61; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_9; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_9 = _GEN_61; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_32; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_32 = _GEN_61; // @[package.scala:16:47] wire _GEN_62 = io_cpu_req_bits_cmd_0 == 5'hB; // @[package.scala:16:47] wire _s0_read_T_10; // @[package.scala:16:47] assign _s0_read_T_10 = _GEN_62; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_10; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_10 = _GEN_62; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_33; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_33 = _GEN_62; // @[package.scala:16:47] wire _s1_did_read_T_10; // @[package.scala:16:47] assign _s1_did_read_T_10 = _GEN_62; // @[package.scala:16:47] wire _s1_did_read_T_33; // @[package.scala:16:47] assign _s1_did_read_T_33 = _GEN_62; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_10; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_10 = _GEN_62; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_33; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_33 = _GEN_62; // @[package.scala:16:47] wire _s0_read_T_11 = _s0_read_T_7 | _s0_read_T_8; // @[package.scala:16:47, :81:59] wire _s0_read_T_12 = _s0_read_T_11 | _s0_read_T_9; // @[package.scala:16:47, :81:59] wire _s0_read_T_13 = _s0_read_T_12 | _s0_read_T_10; // @[package.scala:16:47, :81:59] wire _GEN_63 = io_cpu_req_bits_cmd_0 == 5'h8; // @[package.scala:16:47] wire _s0_read_T_14; // @[package.scala:16:47] assign _s0_read_T_14 = _GEN_63; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_14; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_14 = _GEN_63; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_37; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_37 = _GEN_63; // @[package.scala:16:47] wire _s1_did_read_T_14; // @[package.scala:16:47] assign _s1_did_read_T_14 = _GEN_63; // @[package.scala:16:47] wire _s1_did_read_T_37; // @[package.scala:16:47] assign _s1_did_read_T_37 = _GEN_63; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_14; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_14 = _GEN_63; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_37; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_37 = _GEN_63; // @[package.scala:16:47] wire _GEN_64 = io_cpu_req_bits_cmd_0 == 5'hC; // @[package.scala:16:47] wire _s0_read_T_15; // @[package.scala:16:47] assign _s0_read_T_15 = _GEN_64; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_15; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_15 = _GEN_64; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_38; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_38 = _GEN_64; // @[package.scala:16:47] wire _s1_did_read_T_15; // @[package.scala:16:47] assign _s1_did_read_T_15 = _GEN_64; // @[package.scala:16:47] wire _s1_did_read_T_38; // @[package.scala:16:47] assign _s1_did_read_T_38 = _GEN_64; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_15; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_15 = _GEN_64; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_38; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_38 = _GEN_64; // @[package.scala:16:47] wire _GEN_65 = io_cpu_req_bits_cmd_0 == 5'hD; // @[package.scala:16:47] wire _s0_read_T_16; // @[package.scala:16:47] assign _s0_read_T_16 = _GEN_65; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_16; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_16 = _GEN_65; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_39; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_39 = _GEN_65; // @[package.scala:16:47] wire _s1_did_read_T_16; // @[package.scala:16:47] assign _s1_did_read_T_16 = _GEN_65; // @[package.scala:16:47] wire _s1_did_read_T_39; // @[package.scala:16:47] assign _s1_did_read_T_39 = _GEN_65; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_16; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_16 = _GEN_65; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_39; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_39 = _GEN_65; // @[package.scala:16:47] wire _GEN_66 = io_cpu_req_bits_cmd_0 == 5'hE; // @[package.scala:16:47] wire _s0_read_T_17; // @[package.scala:16:47] assign _s0_read_T_17 = _GEN_66; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_17; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_17 = _GEN_66; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_40; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_40 = _GEN_66; // @[package.scala:16:47] wire _s1_did_read_T_17; // @[package.scala:16:47] assign _s1_did_read_T_17 = _GEN_66; // @[package.scala:16:47] wire _s1_did_read_T_40; // @[package.scala:16:47] assign _s1_did_read_T_40 = _GEN_66; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_17; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_17 = _GEN_66; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_40; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_40 = _GEN_66; // @[package.scala:16:47] wire _GEN_67 = io_cpu_req_bits_cmd_0 == 5'hF; // @[package.scala:16:47] wire _s0_read_T_18; // @[package.scala:16:47] assign _s0_read_T_18 = _GEN_67; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_18; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_18 = _GEN_67; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_41; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_41 = _GEN_67; // @[package.scala:16:47] wire _s1_did_read_T_18; // @[package.scala:16:47] assign _s1_did_read_T_18 = _GEN_67; // @[package.scala:16:47] wire _s1_did_read_T_41; // @[package.scala:16:47] assign _s1_did_read_T_41 = _GEN_67; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_18; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_18 = _GEN_67; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_41; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_41 = _GEN_67; // @[package.scala:16:47] wire _s0_read_T_19 = _s0_read_T_14 | _s0_read_T_15; // @[package.scala:16:47, :81:59] wire _s0_read_T_20 = _s0_read_T_19 | _s0_read_T_16; // @[package.scala:16:47, :81:59] wire _s0_read_T_21 = _s0_read_T_20 | _s0_read_T_17; // @[package.scala:16:47, :81:59] wire _s0_read_T_22 = _s0_read_T_21 | _s0_read_T_18; // @[package.scala:16:47, :81:59] wire _s0_read_T_23 = _s0_read_T_13 | _s0_read_T_22; // @[package.scala:81:59] wire s0_read = _s0_read_T_6 | _s0_read_T_23; // @[package.scala:81:59] wire _GEN_68 = io_cpu_req_bits_cmd_0 == 5'h1; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_res_T; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_res_T = _GEN_68; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_25; // @[Consts.scala:90:32] assign _dataArb_io_in_3_valid_T_25 = _GEN_68; // @[package.scala:16:47] wire _s1_did_read_T_25; // @[Consts.scala:90:32] assign _s1_did_read_T_25 = _GEN_68; // @[package.scala:16:47] wire _pstore_drain_opportunistic_res_T; // @[package.scala:16:47] assign _pstore_drain_opportunistic_res_T = _GEN_68; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_25; // @[Consts.scala:90:32] assign _pstore_drain_opportunistic_T_25 = _GEN_68; // @[package.scala:16:47] wire _GEN_69 = io_cpu_req_bits_cmd_0 == 5'h3; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_res_T_1; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_res_T_1 = _GEN_69; // @[package.scala:16:47] wire _pstore_drain_opportunistic_res_T_1; // @[package.scala:16:47] assign _pstore_drain_opportunistic_res_T_1 = _GEN_69; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_res_T_2 = _dataArb_io_in_3_valid_res_T | _dataArb_io_in_3_valid_res_T_1; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_res_T_3 = ~_dataArb_io_in_3_valid_res_T_2; // @[package.scala:81:59] wire dataArb_io_in_3_valid_res = _dataArb_io_in_3_valid_res_T_3; // @[DCache.scala:1185:{15,46}] wire _dataArb_io_in_3_valid_T_4 = _dataArb_io_in_3_valid_T | _dataArb_io_in_3_valid_T_1; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_5 = _dataArb_io_in_3_valid_T_4 | _dataArb_io_in_3_valid_T_2; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_6 = _dataArb_io_in_3_valid_T_5 | _dataArb_io_in_3_valid_T_3; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_11 = _dataArb_io_in_3_valid_T_7 | _dataArb_io_in_3_valid_T_8; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_12 = _dataArb_io_in_3_valid_T_11 | _dataArb_io_in_3_valid_T_9; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_13 = _dataArb_io_in_3_valid_T_12 | _dataArb_io_in_3_valid_T_10; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_19 = _dataArb_io_in_3_valid_T_14 | _dataArb_io_in_3_valid_T_15; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_20 = _dataArb_io_in_3_valid_T_19 | _dataArb_io_in_3_valid_T_16; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_21 = _dataArb_io_in_3_valid_T_20 | _dataArb_io_in_3_valid_T_17; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_22 = _dataArb_io_in_3_valid_T_21 | _dataArb_io_in_3_valid_T_18; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_23 = _dataArb_io_in_3_valid_T_13 | _dataArb_io_in_3_valid_T_22; // @[package.scala:81:59] wire _dataArb_io_in_3_valid_T_24 = _dataArb_io_in_3_valid_T_6 | _dataArb_io_in_3_valid_T_23; // @[package.scala:81:59] wire _GEN_70 = io_cpu_req_bits_cmd_0 == 5'h11; // @[DCache.scala:101:7] wire _dataArb_io_in_3_valid_T_26; // @[Consts.scala:90:49] assign _dataArb_io_in_3_valid_T_26 = _GEN_70; // @[Consts.scala:90:49] wire _dataArb_io_in_3_valid_T_48; // @[DCache.scala:1191:35] assign _dataArb_io_in_3_valid_T_48 = _GEN_70; // @[DCache.scala:1191:35] wire _s1_did_read_T_26; // @[Consts.scala:90:49] assign _s1_did_read_T_26 = _GEN_70; // @[Consts.scala:90:49] wire _s1_did_read_T_48; // @[DCache.scala:1191:35] assign _s1_did_read_T_48 = _GEN_70; // @[DCache.scala:1191:35] wire _pstore_drain_opportunistic_T_26; // @[Consts.scala:90:49] assign _pstore_drain_opportunistic_T_26 = _GEN_70; // @[Consts.scala:90:49] wire _pstore_drain_opportunistic_T_48; // @[DCache.scala:1191:35] assign _pstore_drain_opportunistic_T_48 = _GEN_70; // @[DCache.scala:1191:35] wire _dataArb_io_in_3_valid_T_27 = _dataArb_io_in_3_valid_T_25 | _dataArb_io_in_3_valid_T_26; // @[Consts.scala:90:{32,42,49}] wire _dataArb_io_in_3_valid_T_29 = _dataArb_io_in_3_valid_T_27 | _dataArb_io_in_3_valid_T_28; // @[Consts.scala:90:{42,59,66}] wire _dataArb_io_in_3_valid_T_34 = _dataArb_io_in_3_valid_T_30 | _dataArb_io_in_3_valid_T_31; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_35 = _dataArb_io_in_3_valid_T_34 | _dataArb_io_in_3_valid_T_32; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_36 = _dataArb_io_in_3_valid_T_35 | _dataArb_io_in_3_valid_T_33; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_42 = _dataArb_io_in_3_valid_T_37 | _dataArb_io_in_3_valid_T_38; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_43 = _dataArb_io_in_3_valid_T_42 | _dataArb_io_in_3_valid_T_39; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_44 = _dataArb_io_in_3_valid_T_43 | _dataArb_io_in_3_valid_T_40; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_45 = _dataArb_io_in_3_valid_T_44 | _dataArb_io_in_3_valid_T_41; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_46 = _dataArb_io_in_3_valid_T_36 | _dataArb_io_in_3_valid_T_45; // @[package.scala:81:59] wire _dataArb_io_in_3_valid_T_47 = _dataArb_io_in_3_valid_T_29 | _dataArb_io_in_3_valid_T_46; // @[Consts.scala:87:44, :90:{59,76}] wire _dataArb_io_in_3_valid_T_50 = _dataArb_io_in_3_valid_T_48; // @[DCache.scala:1191:{35,45}] wire _dataArb_io_in_3_valid_T_51 = _dataArb_io_in_3_valid_T_47 & _dataArb_io_in_3_valid_T_50; // @[DCache.scala:1191:{23,45}] wire _dataArb_io_in_3_valid_T_52 = _dataArb_io_in_3_valid_T_24 | _dataArb_io_in_3_valid_T_51; // @[DCache.scala:1190:21, :1191:23] wire _dataArb_io_in_3_valid_T_53 = ~_dataArb_io_in_3_valid_T_52; // @[DCache.scala:1186:12, :1190:21] wire _dataArb_io_in_3_valid_T_54 = _dataArb_io_in_3_valid_T_53 | dataArb_io_in_3_valid_res; // @[DCache.scala:1185:46, :1186:{12,28}] wire _dataArb_io_in_3_valid_T_56 = ~_dataArb_io_in_3_valid_T_55; // @[DCache.scala:1186:11] wire _dataArb_io_in_3_valid_T_57 = ~_dataArb_io_in_3_valid_T_54; // @[DCache.scala:1186:{11,28}] assign _dataArb_io_in_3_valid_T_58 = io_cpu_req_valid_0 & dataArb_io_in_3_valid_res; // @[DCache.scala:101:7, :242:46, :1185:46] assign dataArb_io_in_3_valid = _dataArb_io_in_3_valid_T_58; // @[DCache.scala:152:28, :242:46] wire [19:0] _dataArb_io_in_3_bits_addr_T = io_cpu_req_bits_addr_0[33:14]; // @[DCache.scala:101:7, :245:89] wire [19:0] _metaArb_io_in_1_bits_addr_T = io_cpu_req_bits_addr_0[33:14]; // @[DCache.scala:101:7, :245:89, :454:58] wire [19:0] _metaArb_io_in_2_bits_addr_T = io_cpu_req_bits_addr_0[33:14]; // @[DCache.scala:101:7, :245:89, :466:58] wire [19:0] _metaArb_io_in_3_bits_addr_T = io_cpu_req_bits_addr_0[33:14]; // @[DCache.scala:101:7, :245:89, :745:58] wire [19:0] _metaArb_io_in_4_bits_addr_T = io_cpu_req_bits_addr_0[33:14]; // @[DCache.scala:101:7, :245:89, :912:58] wire [19:0] _metaArb_io_in_5_bits_addr_T = io_cpu_req_bits_addr_0[33:14]; // @[DCache.scala:101:7, :245:89, :1018:58] wire [13:0] _dataArb_io_in_3_bits_addr_T_1 = io_cpu_req_bits_addr_0[13:0]; // @[DCache.scala:101:7, :245:120] wire [33:0] _dataArb_io_in_3_bits_addr_T_2 = {_dataArb_io_in_3_bits_addr_T, _dataArb_io_in_3_bits_addr_T_1}; // @[DCache.scala:245:{36,89,120}] assign dataArb_io_in_3_bits_addr = _dataArb_io_in_3_bits_addr_T_2[13:0]; // @[DCache.scala:152:28, :245:{30,36}] wire _T_4 = ~dataArb_io_in_3_ready & s0_read; // @[DCache.scala:152:28, :258:{9,33}] wire _s1_did_read_T_4 = _s1_did_read_T | _s1_did_read_T_1; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_5 = _s1_did_read_T_4 | _s1_did_read_T_2; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_6 = _s1_did_read_T_5 | _s1_did_read_T_3; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_11 = _s1_did_read_T_7 | _s1_did_read_T_8; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_12 = _s1_did_read_T_11 | _s1_did_read_T_9; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_13 = _s1_did_read_T_12 | _s1_did_read_T_10; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_19 = _s1_did_read_T_14 | _s1_did_read_T_15; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_20 = _s1_did_read_T_19 | _s1_did_read_T_16; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_21 = _s1_did_read_T_20 | _s1_did_read_T_17; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_22 = _s1_did_read_T_21 | _s1_did_read_T_18; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_23 = _s1_did_read_T_13 | _s1_did_read_T_22; // @[package.scala:81:59] wire _s1_did_read_T_24 = _s1_did_read_T_6 | _s1_did_read_T_23; // @[package.scala:81:59] wire _s1_did_read_T_27 = _s1_did_read_T_25 | _s1_did_read_T_26; // @[Consts.scala:90:{32,42,49}] wire _s1_did_read_T_29 = _s1_did_read_T_27 | _s1_did_read_T_28; // @[Consts.scala:90:{42,59,66}] wire _s1_did_read_T_34 = _s1_did_read_T_30 | _s1_did_read_T_31; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_35 = _s1_did_read_T_34 | _s1_did_read_T_32; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_36 = _s1_did_read_T_35 | _s1_did_read_T_33; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_42 = _s1_did_read_T_37 | _s1_did_read_T_38; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_43 = _s1_did_read_T_42 | _s1_did_read_T_39; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_44 = _s1_did_read_T_43 | _s1_did_read_T_40; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_45 = _s1_did_read_T_44 | _s1_did_read_T_41; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_46 = _s1_did_read_T_36 | _s1_did_read_T_45; // @[package.scala:81:59] wire _s1_did_read_T_47 = _s1_did_read_T_29 | _s1_did_read_T_46; // @[Consts.scala:87:44, :90:{59,76}] wire _s1_did_read_T_50 = _s1_did_read_T_48; // @[DCache.scala:1191:{35,45}] wire _s1_did_read_T_51 = _s1_did_read_T_47 & _s1_did_read_T_50; // @[DCache.scala:1191:{23,45}] wire _s1_did_read_T_52 = _s1_did_read_T_24 | _s1_did_read_T_51; // @[DCache.scala:1190:21, :1191:23] wire _s1_did_read_T_53 = io_cpu_req_valid_0 & _s1_did_read_T_52; // @[DCache.scala:101:7, :259:75, :1190:21] wire _s1_did_read_T_54 = dataArb_io_in_3_ready & _s1_did_read_T_53; // @[DCache.scala:152:28, :259:{54,75}] reg s1_did_read; // @[DCache.scala:259:30] wire _s2_data_word_en_T = s1_did_read; // @[DCache.scala:259:30, :367:63] assign _metaArb_io_in_7_bits_idx_T = _dataArb_io_in_3_bits_addr_T_2[13:6]; // @[DCache.scala:245:36, :263:58] assign metaArb_io_in_7_bits_idx = _metaArb_io_in_7_bits_idx_T; // @[DCache.scala:135:28, :263:58] wire _s1_cmd_uses_tlb_T = s1_readwrite | s1_flush_line; // @[DCache.scala:212:30, :214:50, :270:38] wire _s1_cmd_uses_tlb_T_1 = s1_req_cmd == 5'h17; // @[DCache.scala:196:25, :270:69] wire s1_cmd_uses_tlb = _s1_cmd_uses_tlb_T | _s1_cmd_uses_tlb_T_1; // @[DCache.scala:270:{38,55,69}] wire _tlb_io_req_valid_T = ~io_cpu_s1_kill_0; // @[DCache.scala:101:7, :186:37, :273:55] wire _tlb_io_req_valid_T_1 = s1_valid & _tlb_io_req_valid_T; // @[DCache.scala:182:25, :273:{52,55}] wire _tlb_io_req_valid_T_2 = _tlb_io_req_valid_T_1 & s1_cmd_uses_tlb; // @[DCache.scala:270:55, :273:{52,71}] wire _tlb_io_req_valid_T_3 = _tlb_io_req_valid_T_2; // @[DCache.scala:273:{40,71}] wire _tlb_io_sfence_valid_T = ~io_cpu_s1_kill_0; // @[DCache.scala:101:7, :186:37, :278:38] wire _tlb_io_sfence_valid_T_1 = s1_valid & _tlb_io_sfence_valid_T; // @[DCache.scala:182:25, :278:{35,38}] wire _tlb_io_sfence_valid_T_2 = _tlb_io_sfence_valid_T_1 & s1_sfence; // @[DCache.scala:213:71, :278:{35,54}] wire _tlb_io_sfence_bits_rs2_T = s1_req_size[1]; // @[DCache.scala:196:25, :280:40] wire [19:0] _s1_paddr_T = s1_req_addr[31:12]; // @[DCache.scala:196:25, :298:55] wire [19:0] _s1_paddr_T_1 = _tlb_io_resp_paddr[31:12]; // @[DCache.scala:119:19, :298:99] wire [19:0] _s1_paddr_T_2 = _s1_paddr_T_1; // @[DCache.scala:298:{25,99}] wire [11:0] _s1_paddr_T_3 = s1_req_addr[11:0]; // @[DCache.scala:196:25, :298:125] wire [31:0] s1_paddr = {_s1_paddr_T_2, _s1_paddr_T_3}; // @[DCache.scala:298:{21,25,125}] wire _baseAddr_T = ~hartIdSinkNodeOptIn; // @[LookupByHartId.scala:18:71] wire _inScratchpad_T = s1_paddr[31]; // @[DCache.scala:298:21, :303:35] wire _inScratchpad_T_3 = s1_paddr < 32'h80004000; // @[DCache.scala:298:21, :303:59] wire s1_hit_way = _inScratchpad_T & _inScratchpad_T_3; // @[DCache.scala:303:{35,47,59}] wire [1:0] s1_hit_state_state = {2{s1_hit_way}}; // @[DCache.scala:303:47, :304:25] wire [1:0] s1_data_way; // @[DCache.scala:323:32] wire [7:0] _tl_d_data_encoded_T = nodeOut_d_bits_data[7:0]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_14 = nodeOut_d_bits_data[7:0]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_1 = nodeOut_d_bits_data[15:8]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_15 = nodeOut_d_bits_data[15:8]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_2 = nodeOut_d_bits_data[23:16]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_16 = nodeOut_d_bits_data[23:16]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_3 = nodeOut_d_bits_data[31:24]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_17 = nodeOut_d_bits_data[31:24]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_4 = nodeOut_d_bits_data[39:32]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_18 = nodeOut_d_bits_data[39:32]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_5 = nodeOut_d_bits_data[47:40]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_19 = nodeOut_d_bits_data[47:40]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_6 = nodeOut_d_bits_data[55:48]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_20 = nodeOut_d_bits_data[55:48]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_7 = nodeOut_d_bits_data[63:56]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_21 = nodeOut_d_bits_data[63:56]; // @[package.scala:211:50] wire [15:0] tl_d_data_encoded_lo_lo = {_tl_d_data_encoded_T_1, _tl_d_data_encoded_T}; // @[package.scala:45:27, :211:50] wire [15:0] tl_d_data_encoded_lo_hi = {_tl_d_data_encoded_T_3, _tl_d_data_encoded_T_2}; // @[package.scala:45:27, :211:50] wire [31:0] tl_d_data_encoded_lo = {tl_d_data_encoded_lo_hi, tl_d_data_encoded_lo_lo}; // @[package.scala:45:27] wire [15:0] tl_d_data_encoded_hi_lo = {_tl_d_data_encoded_T_5, _tl_d_data_encoded_T_4}; // @[package.scala:45:27, :211:50] wire [15:0] tl_d_data_encoded_hi_hi = {_tl_d_data_encoded_T_7, _tl_d_data_encoded_T_6}; // @[package.scala:45:27, :211:50] wire [31:0] tl_d_data_encoded_hi = {tl_d_data_encoded_hi_hi, tl_d_data_encoded_hi_lo}; // @[package.scala:45:27] wire [63:0] _tl_d_data_encoded_T_8 = {tl_d_data_encoded_hi, tl_d_data_encoded_lo}; // @[package.scala:45:27] wire [63:0] _tl_d_data_encoded_T_22; // @[package.scala:45:27] wire [63:0] tl_d_data_encoded; // @[DCache.scala:324:31] wire [63:0] s1_all_data_ways_1 = tl_d_data_encoded; // @[DCache.scala:324:31, :325:33] wire [63:0] s2_data_s1_way_words_0_0 = s1_all_data_ways_0; // @[package.scala:211:50] wire [63:0] s2_data_s1_way_words_1_0 = s1_all_data_ways_1; // @[package.scala:211:50] wire _s1_mask_xwr_upper_T = s1_req_addr[0]; // @[DCache.scala:196:25] wire _s1_mask_xwr_lower_T = s1_req_addr[0]; // @[DCache.scala:196:25] wire _s1_mask_xwr_upper_T_1 = _s1_mask_xwr_upper_T; // @[AMOALU.scala:20:{22,27}] wire _s1_mask_xwr_upper_T_2 = |s1_mask_xwr_size; // @[AMOALU.scala:11:18, :20:53] wire _s1_mask_xwr_upper_T_3 = _s1_mask_xwr_upper_T_2; // @[AMOALU.scala:20:{47,53}] wire s1_mask_xwr_upper = _s1_mask_xwr_upper_T_1 | _s1_mask_xwr_upper_T_3; // @[AMOALU.scala:20:{22,42,47}] wire s1_mask_xwr_lower = ~_s1_mask_xwr_lower_T; // @[AMOALU.scala:21:{22,27}] wire [1:0] _s1_mask_xwr_T = {s1_mask_xwr_upper, s1_mask_xwr_lower}; // @[AMOALU.scala:20:42, :21:22, :22:16] wire _s1_mask_xwr_upper_T_4 = s1_req_addr[1]; // @[DCache.scala:196:25] wire _s1_mask_xwr_lower_T_1 = s1_req_addr[1]; // @[DCache.scala:196:25] wire [1:0] _s1_mask_xwr_upper_T_5 = _s1_mask_xwr_upper_T_4 ? _s1_mask_xwr_T : 2'h0; // @[AMOALU.scala:20:{22,27}, :22:16] wire _s1_mask_xwr_upper_T_6 = s1_mask_xwr_size[1]; // @[AMOALU.scala:11:18, :20:53] wire [1:0] _s1_mask_xwr_upper_T_7 = {2{_s1_mask_xwr_upper_T_6}}; // @[AMOALU.scala:20:{47,53}] wire [1:0] s1_mask_xwr_upper_1 = _s1_mask_xwr_upper_T_5 | _s1_mask_xwr_upper_T_7; // @[AMOALU.scala:20:{22,42,47}] wire [1:0] s1_mask_xwr_lower_1 = _s1_mask_xwr_lower_T_1 ? 2'h0 : _s1_mask_xwr_T; // @[AMOALU.scala:21:{22,27}, :22:16] wire [3:0] _s1_mask_xwr_T_1 = {s1_mask_xwr_upper_1, s1_mask_xwr_lower_1}; // @[AMOALU.scala:20:42, :21:22, :22:16] wire _s1_mask_xwr_upper_T_8 = s1_req_addr[2]; // @[DCache.scala:196:25] wire _s1_mask_xwr_lower_T_2 = s1_req_addr[2]; // @[DCache.scala:196:25] wire [3:0] _s1_mask_xwr_upper_T_9 = _s1_mask_xwr_upper_T_8 ? _s1_mask_xwr_T_1 : 4'h0; // @[AMOALU.scala:20:{22,27}, :22:16] wire _s1_mask_xwr_upper_T_10 = &s1_mask_xwr_size; // @[AMOALU.scala:11:18, :20:53] wire [3:0] _s1_mask_xwr_upper_T_11 = {4{_s1_mask_xwr_upper_T_10}}; // @[AMOALU.scala:20:{47,53}] wire [3:0] s1_mask_xwr_upper_2 = _s1_mask_xwr_upper_T_9 | _s1_mask_xwr_upper_T_11; // @[AMOALU.scala:20:{22,42,47}] wire [3:0] s1_mask_xwr_lower_2 = _s1_mask_xwr_lower_T_2 ? 4'h0 : _s1_mask_xwr_T_1; // @[AMOALU.scala:21:{22,27}, :22:16] wire [7:0] s1_mask_xwr = {s1_mask_xwr_upper_2, s1_mask_xwr_lower_2}; // @[AMOALU.scala:20:42, :21:22, :22:16] wire [7:0] s1_mask = _s1_mask_T ? io_cpu_s1_data_mask_0 : s1_mask_xwr; // @[DCache.scala:101:7, :327:{20,32}] wire _s2_valid_T = ~s1_sfence; // @[DCache.scala:213:71, :331:45] wire _s2_valid_T_1 = s1_valid_masked & _s2_valid_T; // @[DCache.scala:186:34, :331:{42,45}] reg s2_valid; // @[DCache.scala:331:25] wire [1:0] _s2_valid_no_xcpt_T = {io_cpu_s2_xcpt_ae_ld_0, io_cpu_s2_xcpt_ae_st_0}; // @[DCache.scala:101:7, :332:54] wire [1:0] _s2_valid_no_xcpt_T_2 = {io_cpu_s2_xcpt_pf_ld_0, io_cpu_s2_xcpt_pf_st_0}; // @[DCache.scala:101:7, :332:54] wire [1:0] _s2_valid_no_xcpt_T_3 = {io_cpu_s2_xcpt_ma_ld_0, io_cpu_s2_xcpt_ma_st_0}; // @[DCache.scala:101:7, :332:54] wire [3:0] s2_valid_no_xcpt_lo = {2'h0, _s2_valid_no_xcpt_T}; // @[DCache.scala:332:54] wire [3:0] s2_valid_no_xcpt_hi = {_s2_valid_no_xcpt_T_3, _s2_valid_no_xcpt_T_2}; // @[DCache.scala:332:54] wire [7:0] _s2_valid_no_xcpt_T_4 = {s2_valid_no_xcpt_hi, s2_valid_no_xcpt_lo}; // @[DCache.scala:332:54] wire _s2_valid_no_xcpt_T_5 = |_s2_valid_no_xcpt_T_4; // @[DCache.scala:332:{54,61}] wire _s2_valid_no_xcpt_T_6 = ~_s2_valid_no_xcpt_T_5; // @[DCache.scala:332:{38,61}] wire s2_valid_no_xcpt = s2_valid & _s2_valid_no_xcpt_T_6; // @[DCache.scala:331:25, :332:{35,38}] wire _s2_not_nacked_in_s1_T = ~s1_nack; // @[DCache.scala:185:28, :187:41, :335:37] reg s2_not_nacked_in_s1; // @[DCache.scala:335:36] wire s2_valid_not_nacked_in_s1 = s2_valid & s2_not_nacked_in_s1; // @[DCache.scala:331:25, :335:36, :336:44] wire s2_valid_masked = s2_valid_no_xcpt & s2_not_nacked_in_s1; // @[DCache.scala:332:35, :335:36, :337:42] wire s2_valid_not_killed = s2_valid_masked; // @[DCache.scala:337:42, :338:45] wire _s2_valid_hit_maybe_flush_pre_data_ecc_and_waw_T_1 = s2_valid_masked; // @[DCache.scala:337:42, :397:71] wire _s2_dont_nack_misc_T_1 = s2_valid_masked; // @[DCache.scala:337:42, :441:43] reg [33:0] s2_req_addr; // @[DCache.scala:339:19] wire [33:0] _get_legal_T_14 = s2_req_addr; // @[DCache.scala:339:19] wire [33:0] _put_legal_T_14 = s2_req_addr; // @[DCache.scala:339:19] wire [33:0] _putpartial_legal_T_14 = s2_req_addr; // @[DCache.scala:339:19] wire [33:0] _atomics_legal_T_4 = s2_req_addr; // @[DCache.scala:339:19] wire [33:0] _atomics_legal_T_34 = s2_req_addr; // @[DCache.scala:339:19] wire [33:0] _atomics_legal_T_64 = s2_req_addr; // @[DCache.scala:339:19] wire [33:0] _atomics_legal_T_94 = s2_req_addr; // @[DCache.scala:339:19] wire [33:0] _atomics_legal_T_124 = s2_req_addr; // @[DCache.scala:339:19] wire [33:0] _atomics_legal_T_154 = s2_req_addr; // @[DCache.scala:339:19] wire [33:0] _atomics_legal_T_184 = s2_req_addr; // @[DCache.scala:339:19] wire [33:0] _atomics_legal_T_214 = s2_req_addr; // @[DCache.scala:339:19] wire [33:0] _atomics_legal_T_244 = s2_req_addr; // @[DCache.scala:339:19] wire [33:0] _tl_out_a_valid_T_1 = s2_req_addr; // @[DCache.scala:339:19, :606:43] reg [6:0] s2_req_tag; // @[DCache.scala:339:19] assign io_cpu_resp_bits_tag_0 = s2_req_tag; // @[DCache.scala:101:7, :339:19] reg [4:0] s2_req_cmd; // @[DCache.scala:339:19] assign io_cpu_resp_bits_cmd_0 = s2_req_cmd; // @[DCache.scala:101:7, :339:19] reg [1:0] s2_req_size; // @[DCache.scala:339:19] assign io_cpu_resp_bits_size_0 = s2_req_size; // @[DCache.scala:101:7, :339:19] wire [1:0] size = s2_req_size; // @[DCache.scala:339:19] reg s2_req_signed; // @[DCache.scala:339:19] assign io_cpu_resp_bits_signed_0 = s2_req_signed; // @[DCache.scala:101:7, :339:19] reg [1:0] s2_req_dprv; // @[DCache.scala:339:19] assign io_cpu_resp_bits_dprv_0 = s2_req_dprv; // @[DCache.scala:101:7, :339:19] reg s2_req_dv; // @[DCache.scala:339:19] assign io_cpu_resp_bits_dv_0 = s2_req_dv; // @[DCache.scala:101:7, :339:19] reg s2_req_phys; // @[DCache.scala:339:19] reg s2_req_no_resp; // @[DCache.scala:339:19] reg s2_req_no_alloc; // @[DCache.scala:339:19] reg s2_req_no_xcpt; // @[DCache.scala:339:19] reg [63:0] s2_req_data; // @[DCache.scala:339:19] reg [7:0] s2_req_mask; // @[DCache.scala:339:19] assign io_cpu_resp_bits_mask_0 = s2_req_mask; // @[DCache.scala:101:7, :339:19] wire _GEN_71 = s2_req_cmd == 5'h5; // @[DCache.scala:339:19, :340:37] wire _s2_cmd_flush_all_T; // @[DCache.scala:340:37] assign _s2_cmd_flush_all_T = _GEN_71; // @[DCache.scala:340:37] wire _s2_cmd_flush_line_T; // @[DCache.scala:341:38] assign _s2_cmd_flush_line_T = _GEN_71; // @[DCache.scala:340:37, :341:38] wire _s2_cmd_flush_all_T_1 = s2_req_size[0]; // @[DCache.scala:339:19, :340:68] wire _s2_cmd_flush_line_T_1 = s2_req_size[0]; // @[DCache.scala:339:19, :340:68, :341:68] wire _s2_cmd_flush_all_T_2 = ~_s2_cmd_flush_all_T_1; // @[DCache.scala:340:{56,68}] wire s2_cmd_flush_all = _s2_cmd_flush_all_T & _s2_cmd_flush_all_T_2; // @[DCache.scala:340:{37,53,56}] wire s2_cmd_flush_line = _s2_cmd_flush_line_T & _s2_cmd_flush_line_T_1; // @[DCache.scala:341:{38,54,68}] reg [31:0] s2_tlb_xcpt_paddr; // @[DCache.scala:342:24] reg [33:0] s2_tlb_xcpt_gpa; // @[DCache.scala:342:24] assign io_cpu_s2_gpa_0 = s2_tlb_xcpt_gpa; // @[DCache.scala:101:7, :342:24] reg s2_tlb_xcpt_pf_ld; // @[DCache.scala:342:24] reg s2_tlb_xcpt_pf_st; // @[DCache.scala:342:24] reg s2_tlb_xcpt_pf_inst; // @[DCache.scala:342:24] reg s2_tlb_xcpt_ae_ld; // @[DCache.scala:342:24] reg s2_tlb_xcpt_ae_st; // @[DCache.scala:342:24] reg s2_tlb_xcpt_ae_inst; // @[DCache.scala:342:24] reg s2_tlb_xcpt_ma_ld; // @[DCache.scala:342:24] reg s2_tlb_xcpt_ma_st; // @[DCache.scala:342:24] reg s2_tlb_xcpt_cacheable; // @[DCache.scala:342:24] reg s2_tlb_xcpt_must_alloc; // @[DCache.scala:342:24] reg s2_tlb_xcpt_prefetchable; // @[DCache.scala:342:24] reg [1:0] s2_tlb_xcpt_size; // @[DCache.scala:342:24] reg [4:0] s2_tlb_xcpt_cmd; // @[DCache.scala:342:24] reg [31:0] s2_pma_paddr; // @[DCache.scala:343:19] reg [33:0] s2_pma_gpa; // @[DCache.scala:343:19] reg s2_pma_pf_ld; // @[DCache.scala:343:19] reg s2_pma_pf_st; // @[DCache.scala:343:19] reg s2_pma_pf_inst; // @[DCache.scala:343:19] reg s2_pma_ae_ld; // @[DCache.scala:343:19] reg s2_pma_ae_st; // @[DCache.scala:343:19] reg s2_pma_ae_inst; // @[DCache.scala:343:19] reg s2_pma_ma_ld; // @[DCache.scala:343:19] reg s2_pma_ma_st; // @[DCache.scala:343:19] reg s2_pma_cacheable; // @[DCache.scala:343:19] reg s2_pma_must_alloc; // @[DCache.scala:343:19] reg s2_pma_prefetchable; // @[DCache.scala:343:19] reg [1:0] s2_pma_size; // @[DCache.scala:343:19] reg [4:0] s2_pma_cmd; // @[DCache.scala:343:19] reg [33:0] s2_uncached_resp_addr; // @[DCache.scala:344:34] wire _T_29 = s1_valid_not_nacked | s1_flush_valid; // @[DCache.scala:187:38, :215:27, :345:29] wire _s2_vaddr_T; // @[DCache.scala:351:62] assign _s2_vaddr_T = _T_29; // @[DCache.scala:345:29, :351:62] wire _s1_meta_clk_en_T; // @[DCache.scala:357:44] assign _s1_meta_clk_en_T = _T_29; // @[DCache.scala:345:29, :357:44] wire _s2_hit_state_T; // @[DCache.scala:386:66] assign _s2_hit_state_T = _T_29; // @[DCache.scala:345:29, :386:66] wire _s2_victim_way_T; // @[DCache.scala:431:77] assign _s2_victim_way_T = _T_29; // @[DCache.scala:345:29, :431:77] reg [33:0] s2_vaddr_r; // @[DCache.scala:351:31] wire [19:0] _s2_vaddr_T_1 = s2_vaddr_r[33:14]; // @[DCache.scala:351:{31,81}] wire [13:0] _s2_vaddr_T_2 = s2_req_addr[13:0]; // @[DCache.scala:339:19, :351:103] wire [33:0] s2_vaddr = {_s2_vaddr_T_1, _s2_vaddr_T_2}; // @[DCache.scala:351:{21,81,103}] wire _s2_read_T = s2_req_cmd == 5'h0; // @[package.scala:16:47] wire _s2_read_T_1 = s2_req_cmd == 5'h10; // @[package.scala:16:47] wire _T_110 = s2_req_cmd == 5'h6; // @[package.scala:16:47] wire _s2_read_T_2; // @[package.scala:16:47] assign _s2_read_T_2 = _T_110; // @[package.scala:16:47] wire _r_c_cat_T_48; // @[Consts.scala:91:71] assign _r_c_cat_T_48 = _T_110; // @[package.scala:16:47] wire _s2_lr_T; // @[DCache.scala:470:70] assign _s2_lr_T = _T_110; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_48; // @[Consts.scala:91:71] assign _metaArb_io_in_3_bits_data_c_cat_T_48 = _T_110; // @[package.scala:16:47] wire _T_111 = s2_req_cmd == 5'h7; // @[package.scala:16:47] wire _s2_read_T_3; // @[package.scala:16:47] assign _s2_read_T_3 = _T_111; // @[package.scala:16:47] wire _s2_write_T_3; // @[Consts.scala:90:66] assign _s2_write_T_3 = _T_111; // @[package.scala:16:47] wire _r_c_cat_T_3; // @[Consts.scala:90:66] assign _r_c_cat_T_3 = _T_111; // @[package.scala:16:47] wire _r_c_cat_T_26; // @[Consts.scala:90:66] assign _r_c_cat_T_26 = _T_111; // @[package.scala:16:47] wire _s2_sc_T; // @[DCache.scala:471:70] assign _s2_sc_T = _T_111; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_3; // @[Consts.scala:90:66] assign _metaArb_io_in_3_bits_data_c_cat_T_3 = _T_111; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_26; // @[Consts.scala:90:66] assign _metaArb_io_in_3_bits_data_c_cat_T_26 = _T_111; // @[package.scala:16:47] wire _io_cpu_store_pending_T_3; // @[Consts.scala:90:66] assign _io_cpu_store_pending_T_3 = _T_111; // @[package.scala:16:47] wire _s2_read_T_4 = _s2_read_T | _s2_read_T_1; // @[package.scala:16:47, :81:59] wire _s2_read_T_5 = _s2_read_T_4 | _s2_read_T_2; // @[package.scala:16:47, :81:59] wire _s2_read_T_6 = _s2_read_T_5 | _s2_read_T_3; // @[package.scala:16:47, :81:59] wire _GEN_72 = s2_req_cmd == 5'h4; // @[package.scala:16:47] wire _s2_read_T_7; // @[package.scala:16:47] assign _s2_read_T_7 = _GEN_72; // @[package.scala:16:47] wire _s2_write_T_5; // @[package.scala:16:47] assign _s2_write_T_5 = _GEN_72; // @[package.scala:16:47] wire _r_c_cat_T_5; // @[package.scala:16:47] assign _r_c_cat_T_5 = _GEN_72; // @[package.scala:16:47] wire _r_c_cat_T_28; // @[package.scala:16:47] assign _r_c_cat_T_28 = _GEN_72; // @[package.scala:16:47] wire _atomics_T; // @[DCache.scala:587:81] assign _atomics_T = _GEN_72; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_5; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_5 = _GEN_72; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_28; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_28 = _GEN_72; // @[package.scala:16:47] wire _io_cpu_store_pending_T_5; // @[package.scala:16:47] assign _io_cpu_store_pending_T_5 = _GEN_72; // @[package.scala:16:47] wire _GEN_73 = s2_req_cmd == 5'h9; // @[package.scala:16:47] wire _s2_read_T_8; // @[package.scala:16:47] assign _s2_read_T_8 = _GEN_73; // @[package.scala:16:47] wire _s2_write_T_6; // @[package.scala:16:47] assign _s2_write_T_6 = _GEN_73; // @[package.scala:16:47] wire _r_c_cat_T_6; // @[package.scala:16:47] assign _r_c_cat_T_6 = _GEN_73; // @[package.scala:16:47] wire _r_c_cat_T_29; // @[package.scala:16:47] assign _r_c_cat_T_29 = _GEN_73; // @[package.scala:16:47] wire _atomics_T_2; // @[DCache.scala:587:81] assign _atomics_T_2 = _GEN_73; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_6; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_6 = _GEN_73; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_29; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_29 = _GEN_73; // @[package.scala:16:47] wire _io_cpu_store_pending_T_6; // @[package.scala:16:47] assign _io_cpu_store_pending_T_6 = _GEN_73; // @[package.scala:16:47] wire _GEN_74 = s2_req_cmd == 5'hA; // @[package.scala:16:47] wire _s2_read_T_9; // @[package.scala:16:47] assign _s2_read_T_9 = _GEN_74; // @[package.scala:16:47] wire _s2_write_T_7; // @[package.scala:16:47] assign _s2_write_T_7 = _GEN_74; // @[package.scala:16:47] wire _r_c_cat_T_7; // @[package.scala:16:47] assign _r_c_cat_T_7 = _GEN_74; // @[package.scala:16:47] wire _r_c_cat_T_30; // @[package.scala:16:47] assign _r_c_cat_T_30 = _GEN_74; // @[package.scala:16:47] wire _atomics_T_4; // @[DCache.scala:587:81] assign _atomics_T_4 = _GEN_74; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_7; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_7 = _GEN_74; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_30; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_30 = _GEN_74; // @[package.scala:16:47] wire _io_cpu_store_pending_T_7; // @[package.scala:16:47] assign _io_cpu_store_pending_T_7 = _GEN_74; // @[package.scala:16:47] wire _GEN_75 = s2_req_cmd == 5'hB; // @[package.scala:16:47] wire _s2_read_T_10; // @[package.scala:16:47] assign _s2_read_T_10 = _GEN_75; // @[package.scala:16:47] wire _s2_write_T_8; // @[package.scala:16:47] assign _s2_write_T_8 = _GEN_75; // @[package.scala:16:47] wire _r_c_cat_T_8; // @[package.scala:16:47] assign _r_c_cat_T_8 = _GEN_75; // @[package.scala:16:47] wire _r_c_cat_T_31; // @[package.scala:16:47] assign _r_c_cat_T_31 = _GEN_75; // @[package.scala:16:47] wire _atomics_T_6; // @[DCache.scala:587:81] assign _atomics_T_6 = _GEN_75; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_8; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_8 = _GEN_75; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_31; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_31 = _GEN_75; // @[package.scala:16:47] wire _io_cpu_store_pending_T_8; // @[package.scala:16:47] assign _io_cpu_store_pending_T_8 = _GEN_75; // @[package.scala:16:47] wire _s2_read_T_11 = _s2_read_T_7 | _s2_read_T_8; // @[package.scala:16:47, :81:59] wire _s2_read_T_12 = _s2_read_T_11 | _s2_read_T_9; // @[package.scala:16:47, :81:59] wire _s2_read_T_13 = _s2_read_T_12 | _s2_read_T_10; // @[package.scala:16:47, :81:59] wire _GEN_76 = s2_req_cmd == 5'h8; // @[package.scala:16:47] wire _s2_read_T_14; // @[package.scala:16:47] assign _s2_read_T_14 = _GEN_76; // @[package.scala:16:47] wire _s2_write_T_12; // @[package.scala:16:47] assign _s2_write_T_12 = _GEN_76; // @[package.scala:16:47] wire _r_c_cat_T_12; // @[package.scala:16:47] assign _r_c_cat_T_12 = _GEN_76; // @[package.scala:16:47] wire _r_c_cat_T_35; // @[package.scala:16:47] assign _r_c_cat_T_35 = _GEN_76; // @[package.scala:16:47] wire _atomics_T_8; // @[DCache.scala:587:81] assign _atomics_T_8 = _GEN_76; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_12; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_12 = _GEN_76; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_35; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_35 = _GEN_76; // @[package.scala:16:47] wire _io_cpu_store_pending_T_12; // @[package.scala:16:47] assign _io_cpu_store_pending_T_12 = _GEN_76; // @[package.scala:16:47] wire _GEN_77 = s2_req_cmd == 5'hC; // @[package.scala:16:47] wire _s2_read_T_15; // @[package.scala:16:47] assign _s2_read_T_15 = _GEN_77; // @[package.scala:16:47] wire _s2_write_T_13; // @[package.scala:16:47] assign _s2_write_T_13 = _GEN_77; // @[package.scala:16:47] wire _r_c_cat_T_13; // @[package.scala:16:47] assign _r_c_cat_T_13 = _GEN_77; // @[package.scala:16:47] wire _r_c_cat_T_36; // @[package.scala:16:47] assign _r_c_cat_T_36 = _GEN_77; // @[package.scala:16:47] wire _atomics_T_10; // @[DCache.scala:587:81] assign _atomics_T_10 = _GEN_77; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_13; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_13 = _GEN_77; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_36; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_36 = _GEN_77; // @[package.scala:16:47] wire _io_cpu_store_pending_T_13; // @[package.scala:16:47] assign _io_cpu_store_pending_T_13 = _GEN_77; // @[package.scala:16:47] wire _GEN_78 = s2_req_cmd == 5'hD; // @[package.scala:16:47] wire _s2_read_T_16; // @[package.scala:16:47] assign _s2_read_T_16 = _GEN_78; // @[package.scala:16:47] wire _s2_write_T_14; // @[package.scala:16:47] assign _s2_write_T_14 = _GEN_78; // @[package.scala:16:47] wire _r_c_cat_T_14; // @[package.scala:16:47] assign _r_c_cat_T_14 = _GEN_78; // @[package.scala:16:47] wire _r_c_cat_T_37; // @[package.scala:16:47] assign _r_c_cat_T_37 = _GEN_78; // @[package.scala:16:47] wire _atomics_T_12; // @[DCache.scala:587:81] assign _atomics_T_12 = _GEN_78; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_14; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_14 = _GEN_78; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_37; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_37 = _GEN_78; // @[package.scala:16:47] wire _io_cpu_store_pending_T_14; // @[package.scala:16:47] assign _io_cpu_store_pending_T_14 = _GEN_78; // @[package.scala:16:47] wire _GEN_79 = s2_req_cmd == 5'hE; // @[package.scala:16:47] wire _s2_read_T_17; // @[package.scala:16:47] assign _s2_read_T_17 = _GEN_79; // @[package.scala:16:47] wire _s2_write_T_15; // @[package.scala:16:47] assign _s2_write_T_15 = _GEN_79; // @[package.scala:16:47] wire _r_c_cat_T_15; // @[package.scala:16:47] assign _r_c_cat_T_15 = _GEN_79; // @[package.scala:16:47] wire _r_c_cat_T_38; // @[package.scala:16:47] assign _r_c_cat_T_38 = _GEN_79; // @[package.scala:16:47] wire _atomics_T_14; // @[DCache.scala:587:81] assign _atomics_T_14 = _GEN_79; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_15; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_15 = _GEN_79; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_38; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_38 = _GEN_79; // @[package.scala:16:47] wire _io_cpu_store_pending_T_15; // @[package.scala:16:47] assign _io_cpu_store_pending_T_15 = _GEN_79; // @[package.scala:16:47] wire _GEN_80 = s2_req_cmd == 5'hF; // @[package.scala:16:47] wire _s2_read_T_18; // @[package.scala:16:47] assign _s2_read_T_18 = _GEN_80; // @[package.scala:16:47] wire _s2_write_T_16; // @[package.scala:16:47] assign _s2_write_T_16 = _GEN_80; // @[package.scala:16:47] wire _r_c_cat_T_16; // @[package.scala:16:47] assign _r_c_cat_T_16 = _GEN_80; // @[package.scala:16:47] wire _r_c_cat_T_39; // @[package.scala:16:47] assign _r_c_cat_T_39 = _GEN_80; // @[package.scala:16:47] wire _atomics_T_16; // @[DCache.scala:587:81] assign _atomics_T_16 = _GEN_80; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_16; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_16 = _GEN_80; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_39; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_39 = _GEN_80; // @[package.scala:16:47] wire _io_cpu_store_pending_T_16; // @[package.scala:16:47] assign _io_cpu_store_pending_T_16 = _GEN_80; // @[package.scala:16:47] wire _s2_read_T_19 = _s2_read_T_14 | _s2_read_T_15; // @[package.scala:16:47, :81:59] wire _s2_read_T_20 = _s2_read_T_19 | _s2_read_T_16; // @[package.scala:16:47, :81:59] wire _s2_read_T_21 = _s2_read_T_20 | _s2_read_T_17; // @[package.scala:16:47, :81:59] wire _s2_read_T_22 = _s2_read_T_21 | _s2_read_T_18; // @[package.scala:16:47, :81:59] wire _s2_read_T_23 = _s2_read_T_13 | _s2_read_T_22; // @[package.scala:81:59] assign s2_read = _s2_read_T_6 | _s2_read_T_23; // @[package.scala:81:59] assign io_cpu_resp_bits_has_data_0 = s2_read; // @[DCache.scala:101:7] wire _GEN_81 = s2_req_cmd == 5'h1; // @[DCache.scala:339:19] wire _s2_write_T; // @[Consts.scala:90:32] assign _s2_write_T = _GEN_81; // @[Consts.scala:90:32] wire _r_c_cat_T; // @[Consts.scala:90:32] assign _r_c_cat_T = _GEN_81; // @[Consts.scala:90:32] wire _r_c_cat_T_23; // @[Consts.scala:90:32] assign _r_c_cat_T_23 = _GEN_81; // @[Consts.scala:90:32] wire _metaArb_io_in_3_bits_data_c_cat_T; // @[Consts.scala:90:32] assign _metaArb_io_in_3_bits_data_c_cat_T = _GEN_81; // @[Consts.scala:90:32] wire _metaArb_io_in_3_bits_data_c_cat_T_23; // @[Consts.scala:90:32] assign _metaArb_io_in_3_bits_data_c_cat_T_23 = _GEN_81; // @[Consts.scala:90:32] wire _io_cpu_store_pending_T; // @[Consts.scala:90:32] assign _io_cpu_store_pending_T = _GEN_81; // @[Consts.scala:90:32] wire _GEN_82 = s2_req_cmd == 5'h11; // @[DCache.scala:339:19] wire _s2_write_T_1; // @[Consts.scala:90:49] assign _s2_write_T_1 = _GEN_82; // @[Consts.scala:90:49] wire _r_c_cat_T_1; // @[Consts.scala:90:49] assign _r_c_cat_T_1 = _GEN_82; // @[Consts.scala:90:49] wire _r_c_cat_T_24; // @[Consts.scala:90:49] assign _r_c_cat_T_24 = _GEN_82; // @[Consts.scala:90:49] wire _tl_out_a_bits_T_2; // @[DCache.scala:610:20] assign _tl_out_a_bits_T_2 = _GEN_82; // @[DCache.scala:610:20] wire _uncachedReqs_0_cmd_T; // @[DCache.scala:637:49] assign _uncachedReqs_0_cmd_T = _GEN_82; // @[DCache.scala:637:49] wire _metaArb_io_in_3_bits_data_c_cat_T_1; // @[Consts.scala:90:49] assign _metaArb_io_in_3_bits_data_c_cat_T_1 = _GEN_82; // @[Consts.scala:90:49] wire _metaArb_io_in_3_bits_data_c_cat_T_24; // @[Consts.scala:90:49] assign _metaArb_io_in_3_bits_data_c_cat_T_24 = _GEN_82; // @[Consts.scala:90:49] wire _io_cpu_store_pending_T_1; // @[Consts.scala:90:49] assign _io_cpu_store_pending_T_1 = _GEN_82; // @[Consts.scala:90:49] wire _s2_write_T_2 = _s2_write_T | _s2_write_T_1; // @[Consts.scala:90:{32,42,49}] wire _s2_write_T_4 = _s2_write_T_2 | _s2_write_T_3; // @[Consts.scala:90:{42,59,66}] wire _s2_write_T_9 = _s2_write_T_5 | _s2_write_T_6; // @[package.scala:16:47, :81:59] wire _s2_write_T_10 = _s2_write_T_9 | _s2_write_T_7; // @[package.scala:16:47, :81:59] wire _s2_write_T_11 = _s2_write_T_10 | _s2_write_T_8; // @[package.scala:16:47, :81:59] wire _s2_write_T_17 = _s2_write_T_12 | _s2_write_T_13; // @[package.scala:16:47, :81:59] wire _s2_write_T_18 = _s2_write_T_17 | _s2_write_T_14; // @[package.scala:16:47, :81:59] wire _s2_write_T_19 = _s2_write_T_18 | _s2_write_T_15; // @[package.scala:16:47, :81:59] wire _s2_write_T_20 = _s2_write_T_19 | _s2_write_T_16; // @[package.scala:16:47, :81:59] wire _s2_write_T_21 = _s2_write_T_11 | _s2_write_T_20; // @[package.scala:81:59] wire s2_write = _s2_write_T_4 | _s2_write_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire s2_readwrite = s2_read | s2_write; // @[DCache.scala:354:30] reg s2_flush_valid_pre_tag_ecc; // @[DCache.scala:355:43] wire s2_flush_valid = s2_flush_valid_pre_tag_ecc; // @[DCache.scala:355:43, :363:51] wire s1_meta_clk_en = _s1_meta_clk_en_T; // @[DCache.scala:357:{44,62}] wire s2_data_en = _s2_data_en_T | io_cpu_replay_next_0; // @[DCache.scala:101:7, :366:{23,38}] wire s2_data_word_en = _s2_data_word_en_T; // @[DCache.scala:367:{22,63}] wire _s2_data_s1_word_en_T = ~io_cpu_replay_next_0; // @[DCache.scala:101:7, :377:28] wire s2_data_s1_word_en = ~_s2_data_s1_word_en_T | s2_data_word_en; // @[DCache.scala:367:22, :377:{27,28}] wire _s2_data_T = s2_data_s1_word_en; // @[DCache.scala:377:27, :379:39] wire [1:0] _s2_data_T_1 = _s2_data_T ? s1_data_way : 2'h0; // @[DCache.scala:323:32, :379:{28,39}] wire _s2_data_T_2 = _s2_data_T_1[0]; // @[Mux.scala:32:36] wire _s2_data_T_3 = _s2_data_T_1[1]; // @[Mux.scala:32:36] wire [63:0] _s2_data_T_4 = _s2_data_T_2 ? s2_data_s1_way_words_0_0 : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _s2_data_T_5 = _s2_data_T_3 ? s2_data_s1_way_words_1_0 : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _s2_data_T_6 = _s2_data_T_4 | _s2_data_T_5; // @[Mux.scala:30:73] wire [63:0] _s2_data_WIRE = _s2_data_T_6; // @[Mux.scala:30:73] reg [63:0] s2_data; // @[DCache.scala:379:18] reg s2_probe_way; // @[DCache.scala:383:31] assign releaseWay = s2_probe_way; // @[DCache.scala:232:24, :383:31] reg [1:0] s2_probe_state_state; // @[DCache.scala:384:33] reg s2_hit_way; // @[DCache.scala:385:29] reg [1:0] s2_hit_state_state; // @[DCache.scala:386:31] wire s2_hit_valid = |s2_hit_state_state; // @[Metadata.scala:50:45] wire _r_c_cat_T_2 = _r_c_cat_T | _r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _r_c_cat_T_4 = _r_c_cat_T_2 | _r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _r_c_cat_T_9 = _r_c_cat_T_5 | _r_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_10 = _r_c_cat_T_9 | _r_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_11 = _r_c_cat_T_10 | _r_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_17 = _r_c_cat_T_12 | _r_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_18 = _r_c_cat_T_17 | _r_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_19 = _r_c_cat_T_18 | _r_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_20 = _r_c_cat_T_19 | _r_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_21 = _r_c_cat_T_11 | _r_c_cat_T_20; // @[package.scala:81:59] wire _r_c_cat_T_22 = _r_c_cat_T_4 | _r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _r_c_cat_T_25 = _r_c_cat_T_23 | _r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _r_c_cat_T_27 = _r_c_cat_T_25 | _r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _r_c_cat_T_32 = _r_c_cat_T_28 | _r_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_33 = _r_c_cat_T_32 | _r_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_34 = _r_c_cat_T_33 | _r_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_40 = _r_c_cat_T_35 | _r_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_41 = _r_c_cat_T_40 | _r_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_42 = _r_c_cat_T_41 | _r_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_43 = _r_c_cat_T_42 | _r_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_44 = _r_c_cat_T_34 | _r_c_cat_T_43; // @[package.scala:81:59] wire _r_c_cat_T_45 = _r_c_cat_T_27 | _r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _GEN_83 = s2_req_cmd == 5'h3; // @[DCache.scala:339:19] wire _r_c_cat_T_46; // @[Consts.scala:91:54] assign _r_c_cat_T_46 = _GEN_83; // @[Consts.scala:91:54] wire _metaArb_io_in_3_bits_data_c_cat_T_46; // @[Consts.scala:91:54] assign _metaArb_io_in_3_bits_data_c_cat_T_46 = _GEN_83; // @[Consts.scala:91:54] wire _r_c_cat_T_47 = _r_c_cat_T_45 | _r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _r_c_cat_T_49 = _r_c_cat_T_47 | _r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] r_c = {_r_c_cat_T_22, _r_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _r_T = {r_c, s2_hit_state_state}; // @[Metadata.scala:29:18, :58:19] wire _r_T_25 = _r_T == 4'hC; // @[Misc.scala:49:20] wire [1:0] _r_T_27 = {1'h0, _r_T_25}; // @[Misc.scala:35:36, :49:20] wire _r_T_28 = _r_T == 4'hD; // @[Misc.scala:49:20] wire [1:0] _r_T_30 = _r_T_28 ? 2'h2 : _r_T_27; // @[Misc.scala:35:36, :49:20] wire _r_T_31 = _r_T == 4'h4; // @[Misc.scala:49:20] wire [1:0] _r_T_33 = _r_T_31 ? 2'h1 : _r_T_30; // @[Misc.scala:35:36, :49:20] wire _r_T_34 = _r_T == 4'h5; // @[Misc.scala:49:20] wire [1:0] _r_T_36 = _r_T_34 ? 2'h2 : _r_T_33; // @[Misc.scala:35:36, :49:20] wire _r_T_37 = _r_T == 4'h0; // @[Misc.scala:49:20] wire [1:0] _r_T_39 = _r_T_37 ? 2'h0 : _r_T_36; // @[Misc.scala:35:36, :49:20] wire _r_T_40 = _r_T == 4'hE; // @[Misc.scala:49:20] wire _r_T_41 = _r_T_40; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_42 = _r_T_40 ? 2'h3 : _r_T_39; // @[Misc.scala:35:36, :49:20] wire _r_T_43 = &_r_T; // @[Misc.scala:49:20] wire _r_T_44 = _r_T_43 | _r_T_41; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_45 = _r_T_43 ? 2'h3 : _r_T_42; // @[Misc.scala:35:36, :49:20] wire _r_T_46 = _r_T == 4'h6; // @[Misc.scala:49:20] wire _r_T_47 = _r_T_46 | _r_T_44; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_48 = _r_T_46 ? 2'h2 : _r_T_45; // @[Misc.scala:35:36, :49:20] wire _r_T_49 = _r_T == 4'h7; // @[Misc.scala:49:20] wire _r_T_50 = _r_T_49 | _r_T_47; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_51 = _r_T_49 ? 2'h3 : _r_T_48; // @[Misc.scala:35:36, :49:20] wire _r_T_52 = _r_T == 4'h1; // @[Misc.scala:49:20] wire _r_T_53 = _r_T_52 | _r_T_50; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_54 = _r_T_52 ? 2'h1 : _r_T_51; // @[Misc.scala:35:36, :49:20] wire _r_T_55 = _r_T == 4'h2; // @[Misc.scala:49:20] wire _r_T_56 = _r_T_55 | _r_T_53; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_57 = _r_T_55 ? 2'h2 : _r_T_54; // @[Misc.scala:35:36, :49:20] wire _r_T_58 = _r_T == 4'h3; // @[Misc.scala:49:20] wire s2_hit = _r_T_58 | _r_T_56; // @[Misc.scala:35:9, :49:20] wire [1:0] s2_grow_param = _r_T_58 ? 2'h3 : _r_T_57; // @[Misc.scala:35:36, :49:20] wire [1:0] s2_new_hit_state_state = s2_grow_param; // @[Misc.scala:35:36] wire [1:0] metaArb_io_in_2_bits_data_meta_coh_state = s2_new_hit_state_state; // @[Metadata.scala:160:20] wire [15:0] s2_data_corrected_lo_lo = s2_data[15:0]; // @[package.scala:45:27] wire [15:0] s2_data_uncorrected_lo_lo = s2_data[15:0]; // @[package.scala:45:27] wire [15:0] s2_data_corrected_lo_hi = s2_data[31:16]; // @[package.scala:45:27] wire [15:0] s2_data_uncorrected_lo_hi = s2_data[31:16]; // @[package.scala:45:27] wire [31:0] s2_data_corrected_lo = {s2_data_corrected_lo_hi, s2_data_corrected_lo_lo}; // @[package.scala:45:27] wire [15:0] s2_data_corrected_hi_lo = s2_data[47:32]; // @[package.scala:45:27] wire [15:0] s2_data_uncorrected_hi_lo = s2_data[47:32]; // @[package.scala:45:27] wire [15:0] s2_data_corrected_hi_hi = s2_data[63:48]; // @[package.scala:45:27] wire [15:0] s2_data_uncorrected_hi_hi = s2_data[63:48]; // @[package.scala:45:27] wire [31:0] s2_data_corrected_hi = {s2_data_corrected_hi_hi, s2_data_corrected_hi_lo}; // @[package.scala:45:27] wire [63:0] s2_data_corrected = {s2_data_corrected_hi, s2_data_corrected_lo}; // @[package.scala:45:27] wire [63:0] s2_data_word_corrected = s2_data_corrected; // @[package.scala:45:27] wire [31:0] s2_data_uncorrected_lo = {s2_data_uncorrected_lo_hi, s2_data_uncorrected_lo_lo}; // @[package.scala:45:27] wire [31:0] s2_data_uncorrected_hi = {s2_data_uncorrected_hi_hi, s2_data_uncorrected_hi_lo}; // @[package.scala:45:27] wire [63:0] s2_data_uncorrected = {s2_data_uncorrected_hi, s2_data_uncorrected_lo}; // @[package.scala:45:27] assign s2_data_word = s2_data_uncorrected; // @[package.scala:45:27] wire s2_valid_hit_maybe_flush_pre_data_ecc_and_waw = _s2_valid_hit_maybe_flush_pre_data_ecc_and_waw_T_1 & s2_hit; // @[Misc.scala:35:9] wire _s2_valid_hit_pre_data_ecc_and_waw_T = s2_valid_hit_maybe_flush_pre_data_ecc_and_waw & s2_readwrite; // @[DCache.scala:354:30, :397:89, :418:89] wire s2_valid_hit_pre_data_ecc_and_waw = _s2_valid_hit_pre_data_ecc_and_waw_T; // @[DCache.scala:418:{89,105}] wire s2_valid_hit_pre_data_ecc = s2_valid_hit_pre_data_ecc_and_waw; // @[DCache.scala:418:105, :420:69] wire s2_valid_flush_line = s2_valid_hit_maybe_flush_pre_data_ecc_and_waw & s2_cmd_flush_line; // @[DCache.scala:341:54, :397:89, :419:75] wire _s2_victim_tag_T = s2_valid_flush_line; // @[DCache.scala:419:75, :433:47] wire s2_valid_hit = s2_valid_hit_pre_data_ecc; // @[DCache.scala:420:69, :422:48] wire _s2_valid_miss_T = s2_valid_masked & s2_readwrite; // @[DCache.scala:337:42, :354:30, :423:39] wire _s2_valid_miss_T_2 = _s2_valid_miss_T; // @[DCache.scala:423:{39,55}] wire _s2_valid_miss_T_3 = ~s2_hit; // @[Misc.scala:35:9] wire s2_valid_miss = _s2_valid_miss_T_2 & _s2_valid_miss_T_3; // @[DCache.scala:423:{55,73,76}] wire _s2_uncached_T = ~s2_pma_cacheable; // @[DCache.scala:343:19, :424:21] wire _s2_uncached_T_1 = ~s2_pma_must_alloc; // @[DCache.scala:343:19, :424:61] wire _s2_uncached_T_2 = s2_req_no_alloc & _s2_uncached_T_1; // @[DCache.scala:339:19, :424:{58,61}] wire _s2_uncached_T_3 = ~s2_hit_valid; // @[Metadata.scala:50:45] wire _s2_uncached_T_4 = _s2_uncached_T_2 & _s2_uncached_T_3; // @[DCache.scala:424:{58,80,83}] wire s2_uncached = _s2_uncached_T | _s2_uncached_T_4; // @[DCache.scala:424:{21,39,80}] wire _s2_valid_cached_miss_T = ~s2_uncached; // @[DCache.scala:424:39, :425:47] wire _s2_valid_cached_miss_T_1 = s2_valid_miss & _s2_valid_cached_miss_T; // @[DCache.scala:423:73, :425:{44,47}] wire _s2_valid_cached_miss_T_3 = ~_s2_valid_cached_miss_T_2; // @[DCache.scala:425:{63,88}] wire s2_valid_cached_miss = _s2_valid_cached_miss_T_1 & _s2_valid_cached_miss_T_3; // @[DCache.scala:425:{44,60,63}] wire _tl_out_a_valid_T_6 = s2_valid_cached_miss; // @[DCache.scala:425:60, :605:29] wire _s2_want_victimize_T = s2_valid_cached_miss | s2_valid_flush_line; // @[DCache.scala:419:75, :425:60, :427:77] wire _s2_want_victimize_T_1 = _s2_want_victimize_T; // @[DCache.scala:427:{77,100}] wire _s2_want_victimize_T_2 = _s2_want_victimize_T_1 | s2_flush_valid; // @[DCache.scala:363:51, :427:{100,123}] wire _s2_cannot_victimize_T = ~s2_flush_valid; // @[DCache.scala:363:51, :428:29] wire _s2_valid_uncached_pending_T = s2_valid_miss & s2_uncached; // @[DCache.scala:423:73, :424:39, :430:49] wire _s2_valid_uncached_pending_T_2 = ~_s2_valid_uncached_pending_T_1; // @[DCache.scala:430:{67,92}] wire s2_valid_uncached_pending = _s2_valid_uncached_pending_T & _s2_valid_uncached_pending_T_2; // @[DCache.scala:430:{49,64,67}] wire [1:0] s2_victim_or_hit_way = s2_hit_valid ? {1'h0, s2_hit_way} : 2'h1; // @[Metadata.scala:50:45] wire [17:0] _s2_victim_tag_T_1 = s2_req_addr[31:14]; // @[DCache.scala:339:19, :433:82] wire [17:0] s2_victim_tag = _s2_victim_tag_T ? _s2_victim_tag_T_1 : 18'h0; // @[DCache.scala:433:{26,47,82}] wire [1:0] s2_victim_state_state = s2_hit_valid ? s2_hit_state_state : 2'h0; // @[Metadata.scala:50:45] wire [3:0] _r_T_59 = {2'h0, s2_probe_state_state}; // @[Metadata.scala:120:19] wire _r_T_72 = _r_T_59 == 4'h8; // @[Misc.scala:56:20] wire [2:0] _r_T_74 = _r_T_72 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _r_T_76 = _r_T_59 == 4'h9; // @[Misc.scala:56:20] wire [2:0] _r_T_78 = _r_T_76 ? 3'h2 : _r_T_74; // @[Misc.scala:38:36, :56:20] wire _r_T_80 = _r_T_59 == 4'hA; // @[Misc.scala:56:20] wire [2:0] _r_T_82 = _r_T_80 ? 3'h1 : _r_T_78; // @[Misc.scala:38:36, :56:20] wire _r_T_84 = _r_T_59 == 4'hB; // @[Misc.scala:56:20] wire _r_T_85 = _r_T_84; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_86 = _r_T_84 ? 3'h1 : _r_T_82; // @[Misc.scala:38:36, :56:20] wire _r_T_88 = _r_T_59 == 4'h4; // @[Misc.scala:56:20] wire _r_T_89 = ~_r_T_88 & _r_T_85; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_90 = _r_T_88 ? 3'h5 : _r_T_86; // @[Misc.scala:38:36, :56:20] wire _r_T_92 = _r_T_59 == 4'h5; // @[Misc.scala:56:20] wire _r_T_93 = ~_r_T_92 & _r_T_89; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_94 = _r_T_92 ? 3'h4 : _r_T_90; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_95 = {1'h0, _r_T_92}; // @[Misc.scala:38:63, :56:20] wire _r_T_96 = _r_T_59 == 4'h6; // @[Misc.scala:56:20] wire _r_T_97 = ~_r_T_96 & _r_T_93; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_98 = _r_T_96 ? 3'h0 : _r_T_94; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_99 = _r_T_96 ? 2'h1 : _r_T_95; // @[Misc.scala:38:63, :56:20] wire _r_T_100 = _r_T_59 == 4'h7; // @[Misc.scala:56:20] wire _r_T_101 = _r_T_100 | _r_T_97; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_102 = _r_T_100 ? 3'h0 : _r_T_98; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_103 = _r_T_100 ? 2'h1 : _r_T_99; // @[Misc.scala:38:63, :56:20] wire _r_T_104 = _r_T_59 == 4'h0; // @[Misc.scala:56:20] wire _r_T_105 = ~_r_T_104 & _r_T_101; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_106 = _r_T_104 ? 3'h5 : _r_T_102; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_107 = _r_T_104 ? 2'h0 : _r_T_103; // @[Misc.scala:38:63, :56:20] wire _r_T_108 = _r_T_59 == 4'h1; // @[Misc.scala:56:20] wire _r_T_109 = ~_r_T_108 & _r_T_105; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_110 = _r_T_108 ? 3'h4 : _r_T_106; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_111 = _r_T_108 ? 2'h1 : _r_T_107; // @[Misc.scala:38:63, :56:20] wire _r_T_112 = _r_T_59 == 4'h2; // @[Misc.scala:56:20] wire _r_T_113 = ~_r_T_112 & _r_T_109; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_114 = _r_T_112 ? 3'h3 : _r_T_110; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_115 = _r_T_112 ? 2'h2 : _r_T_111; // @[Misc.scala:38:63, :56:20] wire _r_T_116 = _r_T_59 == 4'h3; // @[Misc.scala:56:20] wire s2_prb_ack_data = _r_T_116 | _r_T_113; // @[Misc.scala:38:9, :56:20] wire [2:0] s2_report_param = _r_T_116 ? 3'h3 : _r_T_114; // @[Misc.scala:38:36, :56:20] wire [2:0] cleanReleaseMessage_param = s2_report_param; // @[Misc.scala:38:36] wire [2:0] dirtyReleaseMessage_param = s2_report_param; // @[Misc.scala:38:36] wire [1:0] r_3 = _r_T_116 ? 2'h2 : _r_T_115; // @[Misc.scala:38:63, :56:20] wire [1:0] probeNewCoh_state = r_3; // @[Misc.scala:38:63] wire [1:0] newCoh_state = probeNewCoh_state; // @[Metadata.scala:160:20] wire [3:0] _r_T_123 = {2'h2, s2_victim_state_state}; // @[Metadata.scala:120:19] wire _r_T_136 = _r_T_123 == 4'h8; // @[Misc.scala:56:20] wire [2:0] _r_T_138 = _r_T_136 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _r_T_140 = _r_T_123 == 4'h9; // @[Misc.scala:56:20] wire [2:0] _r_T_142 = _r_T_140 ? 3'h2 : _r_T_138; // @[Misc.scala:38:36, :56:20] wire _r_T_144 = _r_T_123 == 4'hA; // @[Misc.scala:56:20] wire [2:0] _r_T_146 = _r_T_144 ? 3'h1 : _r_T_142; // @[Misc.scala:38:36, :56:20] wire _r_T_148 = _r_T_123 == 4'hB; // @[Misc.scala:56:20] wire _r_T_149 = _r_T_148; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_150 = _r_T_148 ? 3'h1 : _r_T_146; // @[Misc.scala:38:36, :56:20] wire _r_T_152 = _r_T_123 == 4'h4; // @[Misc.scala:56:20] wire _r_T_153 = ~_r_T_152 & _r_T_149; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_154 = _r_T_152 ? 3'h5 : _r_T_150; // @[Misc.scala:38:36, :56:20] wire _r_T_156 = _r_T_123 == 4'h5; // @[Misc.scala:56:20] wire _r_T_157 = ~_r_T_156 & _r_T_153; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_158 = _r_T_156 ? 3'h4 : _r_T_154; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_159 = {1'h0, _r_T_156}; // @[Misc.scala:38:63, :56:20] wire _r_T_160 = _r_T_123 == 4'h6; // @[Misc.scala:56:20] wire _r_T_161 = ~_r_T_160 & _r_T_157; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_162 = _r_T_160 ? 3'h0 : _r_T_158; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_163 = _r_T_160 ? 2'h1 : _r_T_159; // @[Misc.scala:38:63, :56:20] wire _r_T_164 = _r_T_123 == 4'h7; // @[Misc.scala:56:20] wire _r_T_165 = _r_T_164 | _r_T_161; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_166 = _r_T_164 ? 3'h0 : _r_T_162; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_167 = _r_T_164 ? 2'h1 : _r_T_163; // @[Misc.scala:38:63, :56:20] wire _r_T_168 = _r_T_123 == 4'h0; // @[Misc.scala:56:20] wire _r_T_169 = ~_r_T_168 & _r_T_165; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_170 = _r_T_168 ? 3'h5 : _r_T_166; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_171 = _r_T_168 ? 2'h0 : _r_T_167; // @[Misc.scala:38:63, :56:20] wire _r_T_172 = _r_T_123 == 4'h1; // @[Misc.scala:56:20] wire _r_T_173 = ~_r_T_172 & _r_T_169; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_174 = _r_T_172 ? 3'h4 : _r_T_170; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_175 = _r_T_172 ? 2'h1 : _r_T_171; // @[Misc.scala:38:63, :56:20] wire _r_T_176 = _r_T_123 == 4'h2; // @[Misc.scala:56:20] wire _r_T_177 = ~_r_T_176 & _r_T_173; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_178 = _r_T_176 ? 3'h3 : _r_T_174; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_179 = _r_T_176 ? 2'h2 : _r_T_175; // @[Misc.scala:38:63, :56:20] wire _r_T_180 = _r_T_123 == 4'h3; // @[Misc.scala:56:20] wire s2_victim_dirty = _r_T_180 | _r_T_177; // @[Misc.scala:38:9, :56:20] wire [2:0] s2_shrink_param = _r_T_180 ? 3'h3 : _r_T_178; // @[Misc.scala:38:36, :56:20] wire [1:0] r_3_1 = _r_T_180 ? 2'h2 : _r_T_179; // @[Misc.scala:38:63, :56:20] wire [1:0] voluntaryNewCoh_state = r_3_1; // @[Misc.scala:38:63] wire _s2_update_meta_T = s2_hit_state_state == s2_new_hit_state_state; // @[Metadata.scala:46:46, :160:20] wire s2_update_meta = ~_s2_update_meta_T; // @[Metadata.scala:46:46, :47:40] wire s2_dont_nack_uncached = s2_valid_uncached_pending & tl_out_a_ready; // @[DCache.scala:159:22, :430:64, :440:57] wire _s2_dont_nack_misc_T_7 = ~s2_hit; // @[Misc.scala:35:9] wire _s2_dont_nack_misc_T_10 = s2_req_cmd == 5'h17; // @[DCache.scala:339:19, :444:17] wire _s2_dont_nack_misc_T_11 = _s2_dont_nack_misc_T_10; // @[DCache.scala:443:55, :444:17] wire s2_dont_nack_misc = _s2_dont_nack_misc_T_1 & _s2_dont_nack_misc_T_11; // @[DCache.scala:441:{43,61}, :443:55] wire _io_cpu_s2_nack_T = ~s2_dont_nack_uncached; // @[DCache.scala:440:57, :445:41] wire _io_cpu_s2_nack_T_1 = s2_valid_no_xcpt & _io_cpu_s2_nack_T; // @[DCache.scala:332:35, :445:{38,41}] wire _io_cpu_s2_nack_T_2 = ~s2_dont_nack_misc; // @[DCache.scala:441:61, :445:67] wire _io_cpu_s2_nack_T_3 = _io_cpu_s2_nack_T_1 & _io_cpu_s2_nack_T_2; // @[DCache.scala:445:{38,64,67}] wire _io_cpu_s2_nack_T_4 = ~s2_valid_hit; // @[DCache.scala:422:48, :445:89] assign _io_cpu_s2_nack_T_5 = _io_cpu_s2_nack_T_3 & _io_cpu_s2_nack_T_4; // @[DCache.scala:445:{64,86,89}] assign io_cpu_s2_nack_0 = _io_cpu_s2_nack_T_5; // @[DCache.scala:101:7, :445:86] assign _metaArb_io_in_2_valid_T = s2_valid_hit_pre_data_ecc_and_waw & s2_update_meta; // @[Metadata.scala:47:40] wire _metaArb_io_in_1_valid_T = s2_valid_masked | s2_flush_valid_pre_tag_ecc; // @[DCache.scala:337:42, :355:43, :450:63] wire _metaArb_io_in_1_valid_T_1 = _metaArb_io_in_1_valid_T; // @[DCache.scala:450:{63,93}] wire [7:0] _metaArb_io_in_1_bits_idx_T_1 = s2_vaddr[13:6]; // @[DCache.scala:351:21, :453:76] assign _metaArb_io_in_2_bits_idx_T = s2_vaddr[13:6]; // @[DCache.scala:351:21, :453:76, :465:40] assign _metaArb_io_in_3_bits_idx_T = s2_vaddr[13:6]; // @[DCache.scala:351:21, :453:76, :744:40] assign _metaArb_io_in_1_bits_idx_T_2 = _metaArb_io_in_1_bits_idx_T_1; // @[DCache.scala:453:{35,76}] assign metaArb_io_in_1_bits_idx = _metaArb_io_in_1_bits_idx_T_2; // @[DCache.scala:135:28, :453:35] wire [13:0] _metaArb_io_in_1_bits_addr_T_1 = {_metaArb_io_in_1_bits_idx_T_2, 6'h0}; // @[DCache.scala:453:35, :454:98] assign _metaArb_io_in_1_bits_addr_T_2 = {_metaArb_io_in_1_bits_addr_T, _metaArb_io_in_1_bits_addr_T_1}; // @[DCache.scala:454:{36,58,98}] assign metaArb_io_in_1_bits_addr = _metaArb_io_in_1_bits_addr_T_2; // @[DCache.scala:135:28, :454:36] assign metaArb_io_in_2_valid = _metaArb_io_in_2_valid_T; // @[DCache.scala:135:28, :462:63] assign metaArb_io_in_2_bits_way_en = s2_victim_or_hit_way[0]; // @[DCache.scala:135:28, :432:33, :464:32] assign metaArb_io_in_2_bits_idx = _metaArb_io_in_2_bits_idx_T; // @[DCache.scala:135:28, :465:40] wire [13:0] _metaArb_io_in_2_bits_addr_T_1 = s2_vaddr[13:0]; // @[DCache.scala:351:21, :466:80] wire [13:0] _metaArb_io_in_3_bits_addr_T_1 = s2_vaddr[13:0]; // @[DCache.scala:351:21, :466:80, :745:80] assign _metaArb_io_in_2_bits_addr_T_2 = {_metaArb_io_in_2_bits_addr_T, _metaArb_io_in_2_bits_addr_T_1}; // @[DCache.scala:466:{36,58,80}] assign metaArb_io_in_2_bits_addr = _metaArb_io_in_2_bits_addr_T_2; // @[DCache.scala:135:28, :466:36] wire [19:0] _metaArb_io_in_2_bits_data_T = s2_req_addr[33:14]; // @[DCache.scala:339:19, :467:68] wire [19:0] _metaArb_io_in_3_bits_data_T = s2_req_addr[33:14]; // @[DCache.scala:339:19, :467:68, :746:68] wire [17:0] metaArb_io_in_2_bits_data_meta_tag; // @[HellaCache.scala:305:20] assign metaArb_io_in_2_bits_data_meta_tag = _metaArb_io_in_2_bits_data_T[17:0]; // @[HellaCache.scala:305:20, :306:14] assign _metaArb_io_in_2_bits_data_T_1 = {metaArb_io_in_2_bits_data_meta_coh_state, metaArb_io_in_2_bits_data_meta_tag}; // @[HellaCache.scala:305:20] assign metaArb_io_in_2_bits_data = _metaArb_io_in_2_bits_data_T_1; // @[DCache.scala:135:28, :467:97] reg [6:0] lrscCount; // @[DCache.scala:472:26] wire lrscValid = |(lrscCount[6:2]); // @[DCache.scala:472:26, :473:29] wire _lrscBackingOff_T = |lrscCount; // @[DCache.scala:472:26, :474:34] wire _lrscBackingOff_T_1 = ~lrscValid; // @[DCache.scala:473:29, :474:43] wire lrscBackingOff = _lrscBackingOff_T & _lrscBackingOff_T_1; // @[DCache.scala:474:{34,40,43}] reg [27:0] lrscAddr; // @[DCache.scala:475:21] wire [27:0] _lrscAddrMatch_T = s2_req_addr[33:6]; // @[DCache.scala:339:19, :476:49] wire [27:0] _lrscAddr_T = s2_req_addr[33:6]; // @[DCache.scala:339:19, :476:49, :480:29] wire [27:0] _acquire_address_T = s2_req_addr[33:6]; // @[DCache.scala:339:19, :476:49, :578:38] wire [27:0] _error_addr_T_2 = s2_req_addr[33:6]; // @[DCache.scala:339:19, :476:49, :1119:27] wire [27:0] _io_errors_bus_bits_T = s2_req_addr[33:6]; // @[DCache.scala:339:19, :476:49, :1130:58] wire lrscAddrMatch = lrscAddr == _lrscAddrMatch_T; // @[DCache.scala:475:21, :476:{32,49}] wire _s2_sc_fail_T = lrscValid & lrscAddrMatch; // @[DCache.scala:473:29, :476:32, :477:41] wire _s2_sc_fail_T_1 = ~_s2_sc_fail_T; // @[DCache.scala:477:{29,41}] wire [6:0] _lrscCount_T = s2_hit ? 7'h4F : 7'h0; // @[Misc.scala:35:9] wire [7:0] _lrscCount_T_1 = {1'h0, lrscCount} - 8'h1; // @[DCache.scala:472:26, :482:51] wire [6:0] _lrscCount_T_2 = _lrscCount_T_1[6:0]; // @[DCache.scala:482:51] wire _s2_correct_T = ~any_pstore_valid; // @[DCache.scala:230:30, :487:37] wire _s2_correct_T_2 = any_pstore_valid | s2_valid; // @[DCache.scala:230:30, :331:25, :487:84] reg s2_correct_REG; // @[DCache.scala:487:66] wire _s2_correct_T_3 = ~s2_correct_REG; // @[DCache.scala:487:{58,66}] wire _GEN_84 = s1_valid_not_nacked & s1_write; // @[DCache.scala:187:38, :492:63] wire _pstore1_cmd_T; // @[DCache.scala:492:63] assign _pstore1_cmd_T = _GEN_84; // @[DCache.scala:492:63] wire _pstore1_addr_T; // @[DCache.scala:493:62] assign _pstore1_addr_T = _GEN_84; // @[DCache.scala:492:63, :493:62] wire _pstore1_data_T; // @[DCache.scala:494:73] assign _pstore1_data_T = _GEN_84; // @[DCache.scala:492:63, :494:73] wire _pstore1_way_T; // @[DCache.scala:495:63] assign _pstore1_way_T = _GEN_84; // @[DCache.scala:492:63, :495:63] wire _pstore1_mask_T; // @[DCache.scala:496:61] assign _pstore1_mask_T = _GEN_84; // @[DCache.scala:492:63, :496:61] wire _pstore1_rmw_T_53; // @[DCache.scala:498:84] assign _pstore1_rmw_T_53 = _GEN_84; // @[DCache.scala:492:63, :498:84] reg [4:0] pstore1_cmd; // @[DCache.scala:492:30] reg [33:0] pstore1_addr; // @[DCache.scala:493:31] wire [33:0] _pstore2_addr_T = pstore1_addr; // @[DCache.scala:493:31, :524:35] reg [63:0] pstore1_data; // @[DCache.scala:494:31] assign io_cpu_resp_bits_store_data_0 = pstore1_data; // @[DCache.scala:101:7, :494:31] wire [63:0] put_data = pstore1_data; // @[Edges.scala:480:17] wire [63:0] putpartial_data = pstore1_data; // @[Edges.scala:500:17] wire [63:0] atomics_a_data = pstore1_data; // @[Edges.scala:534:17] wire [63:0] atomics_a_1_data = pstore1_data; // @[Edges.scala:534:17] wire [63:0] atomics_a_2_data = pstore1_data; // @[Edges.scala:534:17] wire [63:0] atomics_a_3_data = pstore1_data; // @[Edges.scala:534:17] wire [63:0] atomics_a_4_data = pstore1_data; // @[Edges.scala:517:17] wire [63:0] atomics_a_5_data = pstore1_data; // @[Edges.scala:517:17] wire [63:0] atomics_a_6_data = pstore1_data; // @[Edges.scala:517:17] wire [63:0] atomics_a_7_data = pstore1_data; // @[Edges.scala:517:17] wire [63:0] atomics_a_8_data = pstore1_data; // @[Edges.scala:517:17] wire [63:0] _amoalu_io_rhs_T = pstore1_data; // @[DCache.scala:494:31, :986:37] reg pstore1_way; // @[DCache.scala:495:30] wire _pstore2_way_T = pstore1_way; // @[DCache.scala:495:30, :525:34] reg [7:0] pstore1_mask; // @[DCache.scala:496:31] wire [7:0] pstore2_storegen_mask_mergedMask = pstore1_mask; // @[DCache.scala:496:31, :533:37] wire [7:0] _amoalu_io_mask_T = pstore1_mask; // @[DCache.scala:496:31, :983:38] wire [7:0] _pstore1_storegen_data_mask_T = pstore1_mask; // @[DCache.scala:496:31, :990:40] wire [63:0] _pstore1_storegen_data_T_3; // @[DCache.scala:991:52] wire [63:0] pstore1_storegen_data; // @[DCache.scala:497:42] wire _pstore1_rmw_T_4 = _pstore1_rmw_T | _pstore1_rmw_T_1; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_5 = _pstore1_rmw_T_4 | _pstore1_rmw_T_2; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_6 = _pstore1_rmw_T_5 | _pstore1_rmw_T_3; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_11 = _pstore1_rmw_T_7 | _pstore1_rmw_T_8; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_12 = _pstore1_rmw_T_11 | _pstore1_rmw_T_9; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_13 = _pstore1_rmw_T_12 | _pstore1_rmw_T_10; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_19 = _pstore1_rmw_T_14 | _pstore1_rmw_T_15; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_20 = _pstore1_rmw_T_19 | _pstore1_rmw_T_16; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_21 = _pstore1_rmw_T_20 | _pstore1_rmw_T_17; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_22 = _pstore1_rmw_T_21 | _pstore1_rmw_T_18; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_23 = _pstore1_rmw_T_13 | _pstore1_rmw_T_22; // @[package.scala:81:59] wire _pstore1_rmw_T_24 = _pstore1_rmw_T_6 | _pstore1_rmw_T_23; // @[package.scala:81:59] wire _pstore1_rmw_T_27 = _pstore1_rmw_T_25 | _pstore1_rmw_T_26; // @[Consts.scala:90:{32,42,49}] wire _pstore1_rmw_T_29 = _pstore1_rmw_T_27 | _pstore1_rmw_T_28; // @[Consts.scala:90:{42,59,66}] wire _pstore1_rmw_T_34 = _pstore1_rmw_T_30 | _pstore1_rmw_T_31; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_35 = _pstore1_rmw_T_34 | _pstore1_rmw_T_32; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_36 = _pstore1_rmw_T_35 | _pstore1_rmw_T_33; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_42 = _pstore1_rmw_T_37 | _pstore1_rmw_T_38; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_43 = _pstore1_rmw_T_42 | _pstore1_rmw_T_39; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_44 = _pstore1_rmw_T_43 | _pstore1_rmw_T_40; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_45 = _pstore1_rmw_T_44 | _pstore1_rmw_T_41; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_46 = _pstore1_rmw_T_36 | _pstore1_rmw_T_45; // @[package.scala:81:59] wire _pstore1_rmw_T_47 = _pstore1_rmw_T_29 | _pstore1_rmw_T_46; // @[Consts.scala:87:44, :90:{59,76}] wire _pstore1_rmw_T_50 = _pstore1_rmw_T_48; // @[DCache.scala:1191:{35,45}] wire _pstore1_rmw_T_51 = _pstore1_rmw_T_47 & _pstore1_rmw_T_50; // @[DCache.scala:1191:{23,45}] wire _pstore1_rmw_T_52 = _pstore1_rmw_T_24 | _pstore1_rmw_T_51; // @[DCache.scala:1190:21, :1191:23] reg pstore1_rmw_r; // @[DCache.scala:498:44] wire pstore1_rmw = pstore1_rmw_r; // @[DCache.scala:498:{32,44}] wire _pstore1_merge_likely_T = s2_valid_not_nacked_in_s1 & s2_write; // @[DCache.scala:336:44, :499:56] wire _GEN_85 = s2_valid_hit & s2_write; // @[DCache.scala:422:48, :490:46] wire _pstore1_merge_T; // @[DCache.scala:490:46] assign _pstore1_merge_T = _GEN_85; // @[DCache.scala:490:46] wire _pstore1_valid_T; // @[DCache.scala:490:46] assign _pstore1_valid_T = _GEN_85; // @[DCache.scala:490:46] wire _pstore1_held_T; // @[DCache.scala:490:46] assign _pstore1_held_T = _GEN_85; // @[DCache.scala:490:46] wire _pstore1_merge_T_2 = _pstore1_merge_T; // @[DCache.scala:490:{46,58}] wire _pstore1_merge_T_4 = _pstore1_merge_T_2; // @[DCache.scala:490:58, :491:48] reg pstore2_valid; // @[DCache.scala:501:30] wire _pstore_drain_opportunistic_res_T_2 = _pstore_drain_opportunistic_res_T | _pstore_drain_opportunistic_res_T_1; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_res_T_3 = ~_pstore_drain_opportunistic_res_T_2; // @[package.scala:81:59] wire pstore_drain_opportunistic_res = _pstore_drain_opportunistic_res_T_3; // @[DCache.scala:1185:{15,46}] wire _pstore_drain_opportunistic_T_4 = _pstore_drain_opportunistic_T | _pstore_drain_opportunistic_T_1; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_5 = _pstore_drain_opportunistic_T_4 | _pstore_drain_opportunistic_T_2; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_6 = _pstore_drain_opportunistic_T_5 | _pstore_drain_opportunistic_T_3; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_11 = _pstore_drain_opportunistic_T_7 | _pstore_drain_opportunistic_T_8; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_12 = _pstore_drain_opportunistic_T_11 | _pstore_drain_opportunistic_T_9; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_13 = _pstore_drain_opportunistic_T_12 | _pstore_drain_opportunistic_T_10; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_19 = _pstore_drain_opportunistic_T_14 | _pstore_drain_opportunistic_T_15; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_20 = _pstore_drain_opportunistic_T_19 | _pstore_drain_opportunistic_T_16; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_21 = _pstore_drain_opportunistic_T_20 | _pstore_drain_opportunistic_T_17; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_22 = _pstore_drain_opportunistic_T_21 | _pstore_drain_opportunistic_T_18; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_23 = _pstore_drain_opportunistic_T_13 | _pstore_drain_opportunistic_T_22; // @[package.scala:81:59] wire _pstore_drain_opportunistic_T_24 = _pstore_drain_opportunistic_T_6 | _pstore_drain_opportunistic_T_23; // @[package.scala:81:59] wire _pstore_drain_opportunistic_T_27 = _pstore_drain_opportunistic_T_25 | _pstore_drain_opportunistic_T_26; // @[Consts.scala:90:{32,42,49}] wire _pstore_drain_opportunistic_T_29 = _pstore_drain_opportunistic_T_27 | _pstore_drain_opportunistic_T_28; // @[Consts.scala:90:{42,59,66}] wire _pstore_drain_opportunistic_T_34 = _pstore_drain_opportunistic_T_30 | _pstore_drain_opportunistic_T_31; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_35 = _pstore_drain_opportunistic_T_34 | _pstore_drain_opportunistic_T_32; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_36 = _pstore_drain_opportunistic_T_35 | _pstore_drain_opportunistic_T_33; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_42 = _pstore_drain_opportunistic_T_37 | _pstore_drain_opportunistic_T_38; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_43 = _pstore_drain_opportunistic_T_42 | _pstore_drain_opportunistic_T_39; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_44 = _pstore_drain_opportunistic_T_43 | _pstore_drain_opportunistic_T_40; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_45 = _pstore_drain_opportunistic_T_44 | _pstore_drain_opportunistic_T_41; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_46 = _pstore_drain_opportunistic_T_36 | _pstore_drain_opportunistic_T_45; // @[package.scala:81:59] wire _pstore_drain_opportunistic_T_47 = _pstore_drain_opportunistic_T_29 | _pstore_drain_opportunistic_T_46; // @[Consts.scala:87:44, :90:{59,76}] wire _pstore_drain_opportunistic_T_50 = _pstore_drain_opportunistic_T_48; // @[DCache.scala:1191:{35,45}] wire _pstore_drain_opportunistic_T_51 = _pstore_drain_opportunistic_T_47 & _pstore_drain_opportunistic_T_50; // @[DCache.scala:1191:{23,45}] wire _pstore_drain_opportunistic_T_52 = _pstore_drain_opportunistic_T_24 | _pstore_drain_opportunistic_T_51; // @[DCache.scala:1190:21, :1191:23] wire _pstore_drain_opportunistic_T_53 = ~_pstore_drain_opportunistic_T_52; // @[DCache.scala:1186:12, :1190:21] wire _pstore_drain_opportunistic_T_54 = _pstore_drain_opportunistic_T_53 | pstore_drain_opportunistic_res; // @[DCache.scala:1185:46, :1186:{12,28}] wire _pstore_drain_opportunistic_T_56 = ~_pstore_drain_opportunistic_T_55; // @[DCache.scala:1186:11] wire _pstore_drain_opportunistic_T_57 = ~_pstore_drain_opportunistic_T_54; // @[DCache.scala:1186:{11,28}] wire _pstore_drain_opportunistic_T_58 = io_cpu_req_valid_0 & pstore_drain_opportunistic_res; // @[DCache.scala:101:7, :502:55, :1185:46] wire _pstore_drain_opportunistic_T_59 = ~_pstore_drain_opportunistic_T_58; // @[DCache.scala:502:{36,55}] wire pstore_drain_opportunistic = _pstore_drain_opportunistic_T_59; // @[DCache.scala:502:{36,92}] reg pstore_drain_on_miss_REG; // @[DCache.scala:503:56] wire pstore_drain_on_miss = pstore_drain_on_miss_REG; // @[DCache.scala:503:{46,56}] reg pstore1_held; // @[DCache.scala:504:29] wire _GEN_86 = s2_valid & s2_write; // @[DCache.scala:331:25, :505:39] wire _pstore1_valid_likely_T; // @[DCache.scala:505:39] assign _pstore1_valid_likely_T = _GEN_86; // @[DCache.scala:505:39] wire _io_cpu_perf_storeBufferEmptyAfterLoad_T_1; // @[DCache.scala:1082:16] assign _io_cpu_perf_storeBufferEmptyAfterLoad_T_1 = _GEN_86; // @[DCache.scala:505:39, :1082:16] wire _io_cpu_perf_storeBufferEmptyAfterStore_T_1; // @[DCache.scala:1086:15] assign _io_cpu_perf_storeBufferEmptyAfterStore_T_1 = _GEN_86; // @[DCache.scala:505:39, :1086:15] wire _io_cpu_perf_storeBufferEmptyAfterStore_T_4; // @[DCache.scala:1087:16] assign _io_cpu_perf_storeBufferEmptyAfterStore_T_4 = _GEN_86; // @[DCache.scala:505:39, :1087:16] wire _io_cpu_perf_canAcceptStoreThenLoad_T; // @[DCache.scala:1089:16] assign _io_cpu_perf_canAcceptStoreThenLoad_T = _GEN_86; // @[DCache.scala:505:39, :1089:16] wire _io_cpu_perf_canAcceptLoadThenLoad_T_55; // @[DCache.scala:1092:100] assign _io_cpu_perf_canAcceptLoadThenLoad_T_55 = _GEN_86; // @[DCache.scala:505:39, :1092:100] wire pstore1_valid_likely = _pstore1_valid_likely_T | pstore1_held; // @[DCache.scala:504:29, :505:{39,51}] wire _pstore1_valid_T_2 = _pstore1_valid_T; // @[DCache.scala:490:{46,58}] wire _pstore1_valid_T_4 = _pstore1_valid_T_2; // @[DCache.scala:490:58, :491:48] wire pstore1_valid = _pstore1_valid_T_4 | pstore1_held; // @[DCache.scala:491:48, :504:29, :507:38] wire _advance_pstore1_T = pstore1_valid; // @[DCache.scala:507:38, :522:40] assign _any_pstore_valid_T = pstore1_held | pstore2_valid; // @[DCache.scala:501:30, :504:29, :508:36] assign any_pstore_valid = _any_pstore_valid_T; // @[DCache.scala:230:30, :508:36] wire _GEN_87 = pstore1_valid_likely & pstore2_valid; // @[DCache.scala:501:30, :505:51, :509:54] wire _pstore_drain_structural_T; // @[DCache.scala:509:54] assign _pstore_drain_structural_T = _GEN_87; // @[DCache.scala:509:54] wire _io_cpu_perf_canAcceptStoreThenLoad_T_6; // @[DCache.scala:1090:20] assign _io_cpu_perf_canAcceptStoreThenLoad_T_6 = _GEN_87; // @[DCache.scala:509:54, :1090:20] wire _GEN_88 = s1_valid & s1_write; // @[DCache.scala:182:25, :509:85] wire _pstore_drain_structural_T_1; // @[DCache.scala:509:85] assign _pstore_drain_structural_T_1 = _GEN_88; // @[DCache.scala:509:85] wire _io_cpu_perf_storeBufferEmptyAfterLoad_T; // @[DCache.scala:1081:15] assign _io_cpu_perf_storeBufferEmptyAfterLoad_T = _GEN_88; // @[DCache.scala:509:85, :1081:15] wire _io_cpu_perf_storeBufferEmptyAfterStore_T; // @[DCache.scala:1085:15] assign _io_cpu_perf_storeBufferEmptyAfterStore_T = _GEN_88; // @[DCache.scala:509:85, :1085:15] wire _io_cpu_perf_canAcceptStoreThenLoad_T_2; // @[DCache.scala:1089:57] assign _io_cpu_perf_canAcceptStoreThenLoad_T_2 = _GEN_88; // @[DCache.scala:509:85, :1089:57] wire _io_cpu_perf_canAcceptStoreThenLoad_T_7; // @[DCache.scala:1090:57] assign _io_cpu_perf_canAcceptStoreThenLoad_T_7 = _GEN_88; // @[DCache.scala:509:85, :1090:57] wire _io_cpu_perf_canAcceptLoadThenLoad_T; // @[DCache.scala:1092:52] assign _io_cpu_perf_canAcceptLoadThenLoad_T = _GEN_88; // @[DCache.scala:509:85, :1092:52] wire _pstore_drain_structural_T_2 = _pstore_drain_structural_T_1 | pstore1_rmw; // @[DCache.scala:498:32, :509:{85,98}] wire pstore_drain_structural = _pstore_drain_structural_T & _pstore_drain_structural_T_2; // @[DCache.scala:509:{54,71,98}] wire _pstore_drain_T_1 = pstore_drain_structural; // @[DCache.scala:509:71, :517:17] wire _dataArb_io_in_0_valid_T_1 = pstore_drain_structural; // @[DCache.scala:509:71, :517:17] wire _T_48 = s2_valid_hit_pre_data_ecc & s2_write; // @[DCache.scala:420:69, :506:72] wire _pstore_drain_T_2; // @[DCache.scala:506:72] assign _pstore_drain_T_2 = _T_48; // @[DCache.scala:506:72] wire _dataArb_io_in_0_valid_T_2; // @[DCache.scala:506:72] assign _dataArb_io_in_0_valid_T_2 = _T_48; // @[DCache.scala:506:72] wire _pstore_drain_T_4 = _pstore_drain_T_2; // @[DCache.scala:506:{72,84}] wire _pstore_drain_T_5 = _pstore_drain_T_4 | pstore1_held; // @[DCache.scala:504:29, :506:{84,96}] wire _pstore_drain_T_6 = ~pstore1_rmw; // @[DCache.scala:498:32, :518:44] wire _pstore_drain_T_7 = _pstore_drain_T_5 & _pstore_drain_T_6; // @[DCache.scala:506:96, :518:{41,44}] wire _pstore_drain_T_8 = _pstore_drain_T_7 | pstore2_valid; // @[DCache.scala:501:30, :518:{41,58}] wire _GEN_89 = pstore_drain_opportunistic | pstore_drain_on_miss; // @[DCache.scala:502:92, :503:46, :518:107] wire _pstore_drain_T_9; // @[DCache.scala:518:107] assign _pstore_drain_T_9 = _GEN_89; // @[DCache.scala:518:107] wire _dataArb_io_in_0_valid_T_9; // @[DCache.scala:518:107] assign _dataArb_io_in_0_valid_T_9 = _GEN_89; // @[DCache.scala:518:107] wire _pstore_drain_T_10 = _pstore_drain_T_8 & _pstore_drain_T_9; // @[DCache.scala:518:{58,76,107}] wire _pstore_drain_T_11 = _pstore_drain_T_1 | _pstore_drain_T_10; // @[DCache.scala:517:{17,44}, :518:76] assign pstore_drain = _pstore_drain_T_11; // @[DCache.scala:516:27, :517:44] assign dataArb_io_in_0_bits_write = pstore_drain; // @[DCache.scala:152:28, :516:27] wire _pstore1_held_T_2 = _pstore1_held_T; // @[DCache.scala:490:{46,58}] wire _pstore1_held_T_4 = _pstore1_held_T_2; // @[DCache.scala:490:58, :491:48] wire _pstore1_held_T_6 = _pstore1_held_T_4; // @[DCache.scala:491:48, :521:35] wire _pstore1_held_T_7 = _pstore1_held_T_6 | pstore1_held; // @[DCache.scala:504:29, :521:{35,54}] wire _pstore1_held_T_8 = _pstore1_held_T_7 & pstore2_valid; // @[DCache.scala:501:30, :521:{54,71}] wire _pstore1_held_T_9 = ~pstore_drain; // @[DCache.scala:516:27, :521:91] wire _pstore1_held_T_10 = _pstore1_held_T_8 & _pstore1_held_T_9; // @[DCache.scala:521:{71,88,91}] wire _advance_pstore1_T_1 = pstore2_valid == pstore_drain; // @[DCache.scala:501:30, :516:27, :522:79] wire advance_pstore1 = _advance_pstore1_T & _advance_pstore1_T_1; // @[DCache.scala:522:{40,61,79}] wire _pstore2_storegen_data_T_3 = advance_pstore1; // @[DCache.scala:522:61, :528:78] wire _pstore2_storegen_data_T_7 = advance_pstore1; // @[DCache.scala:522:61, :528:78] wire _pstore2_storegen_data_T_11 = advance_pstore1; // @[DCache.scala:522:61, :528:78] wire _pstore2_storegen_data_T_15 = advance_pstore1; // @[DCache.scala:522:61, :528:78] wire _pstore2_storegen_data_T_19 = advance_pstore1; // @[DCache.scala:522:61, :528:78] wire _pstore2_storegen_data_T_23 = advance_pstore1; // @[DCache.scala:522:61, :528:78] wire _pstore2_storegen_data_T_27 = advance_pstore1; // @[DCache.scala:522:61, :528:78] wire _pstore2_storegen_data_T_31 = advance_pstore1; // @[DCache.scala:522:61, :528:78] wire _pstore2_storegen_mask_T = advance_pstore1; // @[DCache.scala:522:61, :532:27] wire _pstore2_valid_T = ~pstore_drain; // @[DCache.scala:516:27, :521:91, :523:37] wire _pstore2_valid_T_1 = pstore2_valid & _pstore2_valid_T; // @[DCache.scala:501:30, :523:{34,37}] wire _pstore2_valid_T_2 = _pstore2_valid_T_1 | advance_pstore1; // @[DCache.scala:522:61, :523:{34,51}] reg [33:0] pstore2_addr; // @[DCache.scala:524:31] reg pstore2_way; // @[DCache.scala:525:30] wire [7:0] _pstore2_storegen_data_T = pstore1_storegen_data[7:0]; // @[DCache.scala:497:42, :528:44] wire _pstore2_storegen_data_T_1 = pstore1_mask[0]; // @[DCache.scala:496:31, :528:110] wire _s1_hazard_T_3 = pstore1_mask[0]; // @[package.scala:211:50] reg [7:0] pstore2_storegen_data_r; // @[DCache.scala:528:22] wire [7:0] _pstore2_storegen_data_T_4 = pstore1_storegen_data[15:8]; // @[DCache.scala:497:42, :528:44] wire _pstore2_storegen_data_T_5 = pstore1_mask[1]; // @[DCache.scala:496:31, :528:110] wire _s1_hazard_T_4 = pstore1_mask[1]; // @[package.scala:211:50] reg [7:0] pstore2_storegen_data_r_1; // @[DCache.scala:528:22] wire [7:0] _pstore2_storegen_data_T_8 = pstore1_storegen_data[23:16]; // @[DCache.scala:497:42, :528:44] wire _pstore2_storegen_data_T_9 = pstore1_mask[2]; // @[DCache.scala:496:31, :528:110] wire _s1_hazard_T_5 = pstore1_mask[2]; // @[package.scala:211:50] reg [7:0] pstore2_storegen_data_r_2; // @[DCache.scala:528:22] wire [7:0] _pstore2_storegen_data_T_12 = pstore1_storegen_data[31:24]; // @[DCache.scala:497:42, :528:44] wire _pstore2_storegen_data_T_13 = pstore1_mask[3]; // @[DCache.scala:496:31, :528:110] wire _s1_hazard_T_6 = pstore1_mask[3]; // @[package.scala:211:50] reg [7:0] pstore2_storegen_data_r_3; // @[DCache.scala:528:22] wire [7:0] _pstore2_storegen_data_T_16 = pstore1_storegen_data[39:32]; // @[DCache.scala:497:42, :528:44] wire _pstore2_storegen_data_T_17 = pstore1_mask[4]; // @[DCache.scala:496:31, :528:110] wire _s1_hazard_T_7 = pstore1_mask[4]; // @[package.scala:211:50] reg [7:0] pstore2_storegen_data_r_4; // @[DCache.scala:528:22] wire [7:0] _pstore2_storegen_data_T_20 = pstore1_storegen_data[47:40]; // @[DCache.scala:497:42, :528:44] wire _pstore2_storegen_data_T_21 = pstore1_mask[5]; // @[DCache.scala:496:31, :528:110] wire _s1_hazard_T_8 = pstore1_mask[5]; // @[package.scala:211:50] reg [7:0] pstore2_storegen_data_r_5; // @[DCache.scala:528:22] wire [7:0] _pstore2_storegen_data_T_24 = pstore1_storegen_data[55:48]; // @[DCache.scala:497:42, :528:44] wire _pstore2_storegen_data_T_25 = pstore1_mask[6]; // @[DCache.scala:496:31, :528:110] wire _s1_hazard_T_9 = pstore1_mask[6]; // @[package.scala:211:50] reg [7:0] pstore2_storegen_data_r_6; // @[DCache.scala:528:22] wire [7:0] _pstore2_storegen_data_T_28 = pstore1_storegen_data[63:56]; // @[DCache.scala:497:42, :528:44] wire _pstore2_storegen_data_T_29 = pstore1_mask[7]; // @[DCache.scala:496:31, :528:110] wire _s1_hazard_T_10 = pstore1_mask[7]; // @[package.scala:211:50] reg [7:0] pstore2_storegen_data_r_7; // @[DCache.scala:528:22] wire [15:0] pstore2_storegen_data_lo_lo = {pstore2_storegen_data_r_1, pstore2_storegen_data_r}; // @[package.scala:45:27] wire [15:0] pstore2_storegen_data_lo_hi = {pstore2_storegen_data_r_3, pstore2_storegen_data_r_2}; // @[package.scala:45:27] wire [31:0] pstore2_storegen_data_lo = {pstore2_storegen_data_lo_hi, pstore2_storegen_data_lo_lo}; // @[package.scala:45:27] wire [15:0] pstore2_storegen_data_hi_lo = {pstore2_storegen_data_r_5, pstore2_storegen_data_r_4}; // @[package.scala:45:27] wire [15:0] pstore2_storegen_data_hi_hi = {pstore2_storegen_data_r_7, pstore2_storegen_data_r_6}; // @[package.scala:45:27] wire [31:0] pstore2_storegen_data_hi = {pstore2_storegen_data_hi_hi, pstore2_storegen_data_hi_lo}; // @[package.scala:45:27] wire [63:0] pstore2_storegen_data = {pstore2_storegen_data_hi, pstore2_storegen_data_lo}; // @[package.scala:45:27] reg [7:0] pstore2_storegen_mask; // @[DCache.scala:531:19] wire [7:0] _pstore2_storegen_mask_mask_T = ~pstore2_storegen_mask_mergedMask; // @[DCache.scala:533:37, :534:37] wire [7:0] _pstore2_storegen_mask_mask_T_1 = _pstore2_storegen_mask_mask_T; // @[DCache.scala:534:{19,37}] wire [7:0] _pstore2_storegen_mask_mask_T_2 = ~_pstore2_storegen_mask_mask_T_1; // @[DCache.scala:534:{15,19}] wire _dataArb_io_in_0_valid_T_4 = _dataArb_io_in_0_valid_T_2; // @[DCache.scala:506:{72,84}] wire _dataArb_io_in_0_valid_T_5 = _dataArb_io_in_0_valid_T_4 | pstore1_held; // @[DCache.scala:504:29, :506:{84,96}] wire _dataArb_io_in_0_valid_T_6 = ~pstore1_rmw; // @[DCache.scala:498:32, :518:44] wire _dataArb_io_in_0_valid_T_7 = _dataArb_io_in_0_valid_T_5 & _dataArb_io_in_0_valid_T_6; // @[DCache.scala:506:96, :518:{41,44}] wire _dataArb_io_in_0_valid_T_8 = _dataArb_io_in_0_valid_T_7 | pstore2_valid; // @[DCache.scala:501:30, :518:{41,58}] wire _dataArb_io_in_0_valid_T_10 = _dataArb_io_in_0_valid_T_8 & _dataArb_io_in_0_valid_T_9; // @[DCache.scala:518:{58,76,107}] wire _dataArb_io_in_0_valid_T_11 = _dataArb_io_in_0_valid_T_1 | _dataArb_io_in_0_valid_T_10; // @[DCache.scala:517:{17,44}, :518:76] assign _dataArb_io_in_0_valid_T_12 = _dataArb_io_in_0_valid_T_11; // @[DCache.scala:516:27, :517:44] assign dataArb_io_in_0_valid = _dataArb_io_in_0_valid_T_12; // @[DCache.scala:152:28, :516:27] wire [33:0] _GEN_90 = pstore2_valid ? pstore2_addr : pstore1_addr; // @[DCache.scala:493:31, :501:30, :524:31, :549:36] wire [33:0] _dataArb_io_in_0_bits_addr_T; // @[DCache.scala:549:36] assign _dataArb_io_in_0_bits_addr_T = _GEN_90; // @[DCache.scala:549:36] wire [33:0] _dataArb_io_in_0_bits_wordMask_wordMask_T; // @[DCache.scala:554:32] assign _dataArb_io_in_0_bits_wordMask_wordMask_T = _GEN_90; // @[DCache.scala:549:36, :554:32] assign dataArb_io_in_0_bits_addr = _dataArb_io_in_0_bits_addr_T[13:0]; // @[DCache.scala:152:28, :549:{30,36}] assign dataArb_io_in_1_bits_addr = _dataArb_io_in_0_bits_addr_T[13:0]; // @[DCache.scala:152:28, :549:{30,36}] assign _dataArb_io_in_0_bits_way_en_T = pstore2_valid ? pstore2_way : pstore1_way; // @[DCache.scala:495:30, :501:30, :525:30, :550:38] assign dataArb_io_in_0_bits_way_en = _dataArb_io_in_0_bits_way_en_T; // @[DCache.scala:152:28, :550:38] assign dataArb_io_in_1_bits_way_en = _dataArb_io_in_0_bits_way_en_T; // @[DCache.scala:152:28, :550:38] wire [63:0] _dataArb_io_in_0_bits_wdata_T = pstore2_valid ? pstore2_storegen_data : pstore1_data; // @[package.scala:45:27] wire [7:0] _dataArb_io_in_0_bits_wdata_T_1 = _dataArb_io_in_0_bits_wdata_T[7:0]; // @[package.scala:211:50] wire [7:0] _dataArb_io_in_0_bits_wdata_T_2 = _dataArb_io_in_0_bits_wdata_T[15:8]; // @[package.scala:211:50] wire [7:0] _dataArb_io_in_0_bits_wdata_T_3 = _dataArb_io_in_0_bits_wdata_T[23:16]; // @[package.scala:211:50] wire [7:0] _dataArb_io_in_0_bits_wdata_T_4 = _dataArb_io_in_0_bits_wdata_T[31:24]; // @[package.scala:211:50] wire [7:0] _dataArb_io_in_0_bits_wdata_T_5 = _dataArb_io_in_0_bits_wdata_T[39:32]; // @[package.scala:211:50] wire [7:0] _dataArb_io_in_0_bits_wdata_T_6 = _dataArb_io_in_0_bits_wdata_T[47:40]; // @[package.scala:211:50] wire [7:0] _dataArb_io_in_0_bits_wdata_T_7 = _dataArb_io_in_0_bits_wdata_T[55:48]; // @[package.scala:211:50] wire [7:0] _dataArb_io_in_0_bits_wdata_T_8 = _dataArb_io_in_0_bits_wdata_T[63:56]; // @[package.scala:211:50] wire [15:0] dataArb_io_in_0_bits_wdata_lo_lo = {_dataArb_io_in_0_bits_wdata_T_2, _dataArb_io_in_0_bits_wdata_T_1}; // @[package.scala:45:27, :211:50] wire [15:0] dataArb_io_in_0_bits_wdata_lo_hi = {_dataArb_io_in_0_bits_wdata_T_4, _dataArb_io_in_0_bits_wdata_T_3}; // @[package.scala:45:27, :211:50] wire [31:0] dataArb_io_in_0_bits_wdata_lo = {dataArb_io_in_0_bits_wdata_lo_hi, dataArb_io_in_0_bits_wdata_lo_lo}; // @[package.scala:45:27] wire [15:0] dataArb_io_in_0_bits_wdata_hi_lo = {_dataArb_io_in_0_bits_wdata_T_6, _dataArb_io_in_0_bits_wdata_T_5}; // @[package.scala:45:27, :211:50] wire [15:0] dataArb_io_in_0_bits_wdata_hi_hi = {_dataArb_io_in_0_bits_wdata_T_8, _dataArb_io_in_0_bits_wdata_T_7}; // @[package.scala:45:27, :211:50] wire [31:0] dataArb_io_in_0_bits_wdata_hi = {dataArb_io_in_0_bits_wdata_hi_hi, dataArb_io_in_0_bits_wdata_hi_lo}; // @[package.scala:45:27] assign _dataArb_io_in_0_bits_wdata_T_9 = {dataArb_io_in_0_bits_wdata_hi, dataArb_io_in_0_bits_wdata_lo}; // @[package.scala:45:27] assign dataArb_io_in_0_bits_wdata = _dataArb_io_in_0_bits_wdata_T_9; // @[package.scala:45:27] assign dataArb_io_in_1_bits_wdata = _dataArb_io_in_0_bits_wdata_T_9; // @[package.scala:45:27] assign dataArb_io_in_2_bits_wdata = _dataArb_io_in_0_bits_wdata_T_9; // @[package.scala:45:27] assign dataArb_io_in_3_bits_wdata = _dataArb_io_in_0_bits_wdata_T_9; // @[package.scala:45:27] wire _dataArb_io_in_0_bits_wordMask_eccMask_T = _dataArb_io_in_0_bits_eccMask_T_17[0]; // @[package.scala:45:27] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_1 = _dataArb_io_in_0_bits_eccMask_T_17[1]; // @[package.scala:45:27] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_2 = _dataArb_io_in_0_bits_eccMask_T_17[2]; // @[package.scala:45:27] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_3 = _dataArb_io_in_0_bits_eccMask_T_17[3]; // @[package.scala:45:27] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_4 = _dataArb_io_in_0_bits_eccMask_T_17[4]; // @[package.scala:45:27] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_5 = _dataArb_io_in_0_bits_eccMask_T_17[5]; // @[package.scala:45:27] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_6 = _dataArb_io_in_0_bits_eccMask_T_17[6]; // @[package.scala:45:27] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_7 = _dataArb_io_in_0_bits_eccMask_T_17[7]; // @[package.scala:45:27] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_8 = _dataArb_io_in_0_bits_wordMask_eccMask_T | _dataArb_io_in_0_bits_wordMask_eccMask_T_1; // @[package.scala:81:59] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_9 = _dataArb_io_in_0_bits_wordMask_eccMask_T_8 | _dataArb_io_in_0_bits_wordMask_eccMask_T_2; // @[package.scala:81:59] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_10 = _dataArb_io_in_0_bits_wordMask_eccMask_T_9 | _dataArb_io_in_0_bits_wordMask_eccMask_T_3; // @[package.scala:81:59] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_11 = _dataArb_io_in_0_bits_wordMask_eccMask_T_10 | _dataArb_io_in_0_bits_wordMask_eccMask_T_4; // @[package.scala:81:59] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_12 = _dataArb_io_in_0_bits_wordMask_eccMask_T_11 | _dataArb_io_in_0_bits_wordMask_eccMask_T_5; // @[package.scala:81:59] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_13 = _dataArb_io_in_0_bits_wordMask_eccMask_T_12 | _dataArb_io_in_0_bits_wordMask_eccMask_T_6; // @[package.scala:81:59] wire dataArb_io_in_0_bits_wordMask_eccMask = _dataArb_io_in_0_bits_wordMask_eccMask_T_13 | _dataArb_io_in_0_bits_wordMask_eccMask_T_7; // @[package.scala:81:59] wire [1:0] _dataArb_io_in_0_bits_wordMask_T_3 = {1'h0, dataArb_io_in_0_bits_wordMask_eccMask}; // @[package.scala:81:59] assign dataArb_io_in_0_bits_wordMask = _dataArb_io_in_0_bits_wordMask_T_3[0]; // @[DCache.scala:152:28, :552:34, :555:55] assign dataArb_io_in_1_bits_wordMask = _dataArb_io_in_0_bits_wordMask_T_3[0]; // @[DCache.scala:152:28, :552:34, :555:55] wire [7:0] _dataArb_io_in_0_bits_eccMask_T = pstore2_valid ? pstore2_storegen_mask : pstore1_mask; // @[DCache.scala:496:31, :501:30, :531:19, :557:47] wire _dataArb_io_in_0_bits_eccMask_T_1 = _dataArb_io_in_0_bits_eccMask_T[0]; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_9 = _dataArb_io_in_0_bits_eccMask_T_1; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_2 = _dataArb_io_in_0_bits_eccMask_T[1]; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_10 = _dataArb_io_in_0_bits_eccMask_T_2; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_3 = _dataArb_io_in_0_bits_eccMask_T[2]; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_11 = _dataArb_io_in_0_bits_eccMask_T_3; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_4 = _dataArb_io_in_0_bits_eccMask_T[3]; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_12 = _dataArb_io_in_0_bits_eccMask_T_4; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_5 = _dataArb_io_in_0_bits_eccMask_T[4]; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_13 = _dataArb_io_in_0_bits_eccMask_T_5; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_6 = _dataArb_io_in_0_bits_eccMask_T[5]; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_14 = _dataArb_io_in_0_bits_eccMask_T_6; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_7 = _dataArb_io_in_0_bits_eccMask_T[6]; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_15 = _dataArb_io_in_0_bits_eccMask_T_7; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_8 = _dataArb_io_in_0_bits_eccMask_T[7]; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_16 = _dataArb_io_in_0_bits_eccMask_T_8; // @[package.scala:211:50] wire [1:0] dataArb_io_in_0_bits_eccMask_lo_lo = {_dataArb_io_in_0_bits_eccMask_T_10, _dataArb_io_in_0_bits_eccMask_T_9}; // @[package.scala:45:27] wire [1:0] dataArb_io_in_0_bits_eccMask_lo_hi = {_dataArb_io_in_0_bits_eccMask_T_12, _dataArb_io_in_0_bits_eccMask_T_11}; // @[package.scala:45:27] wire [3:0] dataArb_io_in_0_bits_eccMask_lo = {dataArb_io_in_0_bits_eccMask_lo_hi, dataArb_io_in_0_bits_eccMask_lo_lo}; // @[package.scala:45:27] wire [1:0] dataArb_io_in_0_bits_eccMask_hi_lo = {_dataArb_io_in_0_bits_eccMask_T_14, _dataArb_io_in_0_bits_eccMask_T_13}; // @[package.scala:45:27] wire [1:0] dataArb_io_in_0_bits_eccMask_hi_hi = {_dataArb_io_in_0_bits_eccMask_T_16, _dataArb_io_in_0_bits_eccMask_T_15}; // @[package.scala:45:27] wire [3:0] dataArb_io_in_0_bits_eccMask_hi = {dataArb_io_in_0_bits_eccMask_hi_hi, dataArb_io_in_0_bits_eccMask_hi_lo}; // @[package.scala:45:27] assign _dataArb_io_in_0_bits_eccMask_T_17 = {dataArb_io_in_0_bits_eccMask_hi, dataArb_io_in_0_bits_eccMask_lo}; // @[package.scala:45:27] assign dataArb_io_in_0_bits_eccMask = _dataArb_io_in_0_bits_eccMask_T_17; // @[package.scala:45:27] assign dataArb_io_in_1_bits_eccMask = _dataArb_io_in_0_bits_eccMask_T_17; // @[package.scala:45:27] wire [10:0] _s1_hazard_T = pstore1_addr[13:3]; // @[DCache.scala:493:31, :561:9] wire [10:0] _s1_hazard_T_1 = s1_vaddr[13:3]; // @[DCache.scala:197:21, :561:43] wire [10:0] _s1_hazard_T_63 = s1_vaddr[13:3]; // @[DCache.scala:197:21, :561:43] wire _s1_hazard_T_2 = _s1_hazard_T == _s1_hazard_T_1; // @[DCache.scala:561:{9,31,43}] wire _s1_hazard_T_11 = _s1_hazard_T_3; // @[package.scala:211:50] wire _s1_hazard_T_12 = _s1_hazard_T_4; // @[package.scala:211:50] wire _s1_hazard_T_13 = _s1_hazard_T_5; // @[package.scala:211:50] wire _s1_hazard_T_14 = _s1_hazard_T_6; // @[package.scala:211:50] wire _s1_hazard_T_15 = _s1_hazard_T_7; // @[package.scala:211:50] wire _s1_hazard_T_16 = _s1_hazard_T_8; // @[package.scala:211:50] wire _s1_hazard_T_17 = _s1_hazard_T_9; // @[package.scala:211:50] wire _s1_hazard_T_18 = _s1_hazard_T_10; // @[package.scala:211:50] wire [1:0] s1_hazard_lo_lo = {_s1_hazard_T_12, _s1_hazard_T_11}; // @[package.scala:45:27] wire [1:0] s1_hazard_lo_hi = {_s1_hazard_T_14, _s1_hazard_T_13}; // @[package.scala:45:27] wire [3:0] s1_hazard_lo = {s1_hazard_lo_hi, s1_hazard_lo_lo}; // @[package.scala:45:27] wire [1:0] s1_hazard_hi_lo = {_s1_hazard_T_16, _s1_hazard_T_15}; // @[package.scala:45:27] wire [1:0] s1_hazard_hi_hi = {_s1_hazard_T_18, _s1_hazard_T_17}; // @[package.scala:45:27] wire [3:0] s1_hazard_hi = {s1_hazard_hi_hi, s1_hazard_hi_lo}; // @[package.scala:45:27] wire [7:0] _s1_hazard_T_19 = {s1_hazard_hi, s1_hazard_lo}; // @[package.scala:45:27] wire _s1_hazard_T_20 = _s1_hazard_T_19[0]; // @[package.scala:45:27] wire _s1_hazard_T_21 = _s1_hazard_T_19[1]; // @[package.scala:45:27] wire _s1_hazard_T_22 = _s1_hazard_T_19[2]; // @[package.scala:45:27] wire _s1_hazard_T_23 = _s1_hazard_T_19[3]; // @[package.scala:45:27] wire _s1_hazard_T_24 = _s1_hazard_T_19[4]; // @[package.scala:45:27] wire _s1_hazard_T_25 = _s1_hazard_T_19[5]; // @[package.scala:45:27] wire _s1_hazard_T_26 = _s1_hazard_T_19[6]; // @[package.scala:45:27] wire _s1_hazard_T_27 = _s1_hazard_T_19[7]; // @[package.scala:45:27] wire [1:0] s1_hazard_lo_lo_1 = {_s1_hazard_T_21, _s1_hazard_T_20}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_lo_hi_1 = {_s1_hazard_T_23, _s1_hazard_T_22}; // @[DCache.scala:1182:52] wire [3:0] s1_hazard_lo_1 = {s1_hazard_lo_hi_1, s1_hazard_lo_lo_1}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_hi_lo_1 = {_s1_hazard_T_25, _s1_hazard_T_24}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_hi_hi_1 = {_s1_hazard_T_27, _s1_hazard_T_26}; // @[DCache.scala:1182:52] wire [3:0] s1_hazard_hi_1 = {s1_hazard_hi_hi_1, s1_hazard_hi_lo_1}; // @[DCache.scala:1182:52] wire [7:0] _s1_hazard_T_28 = {s1_hazard_hi_1, s1_hazard_lo_1}; // @[DCache.scala:1182:52] wire _s1_hazard_T_29 = s1_mask_xwr[0]; // @[package.scala:211:50] wire _s1_hazard_T_91 = s1_mask_xwr[0]; // @[package.scala:211:50] wire _s1_hazard_T_37 = _s1_hazard_T_29; // @[package.scala:211:50] wire _s1_hazard_T_30 = s1_mask_xwr[1]; // @[package.scala:211:50] wire _s1_hazard_T_92 = s1_mask_xwr[1]; // @[package.scala:211:50] wire _s1_hazard_T_38 = _s1_hazard_T_30; // @[package.scala:211:50] wire _s1_hazard_T_31 = s1_mask_xwr[2]; // @[package.scala:211:50] wire _s1_hazard_T_93 = s1_mask_xwr[2]; // @[package.scala:211:50] wire _s1_hazard_T_39 = _s1_hazard_T_31; // @[package.scala:211:50] wire _s1_hazard_T_32 = s1_mask_xwr[3]; // @[package.scala:211:50] wire _s1_hazard_T_94 = s1_mask_xwr[3]; // @[package.scala:211:50] wire _s1_hazard_T_40 = _s1_hazard_T_32; // @[package.scala:211:50] wire _s1_hazard_T_33 = s1_mask_xwr[4]; // @[package.scala:211:50] wire _s1_hazard_T_95 = s1_mask_xwr[4]; // @[package.scala:211:50] wire _s1_hazard_T_41 = _s1_hazard_T_33; // @[package.scala:211:50] wire _s1_hazard_T_34 = s1_mask_xwr[5]; // @[package.scala:211:50] wire _s1_hazard_T_96 = s1_mask_xwr[5]; // @[package.scala:211:50] wire _s1_hazard_T_42 = _s1_hazard_T_34; // @[package.scala:211:50] wire _s1_hazard_T_35 = s1_mask_xwr[6]; // @[package.scala:211:50] wire _s1_hazard_T_97 = s1_mask_xwr[6]; // @[package.scala:211:50] wire _s1_hazard_T_43 = _s1_hazard_T_35; // @[package.scala:211:50] wire _s1_hazard_T_36 = s1_mask_xwr[7]; // @[package.scala:211:50] wire _s1_hazard_T_98 = s1_mask_xwr[7]; // @[package.scala:211:50] wire _s1_hazard_T_44 = _s1_hazard_T_36; // @[package.scala:211:50] wire [1:0] s1_hazard_lo_lo_2 = {_s1_hazard_T_38, _s1_hazard_T_37}; // @[package.scala:45:27] wire [1:0] s1_hazard_lo_hi_2 = {_s1_hazard_T_40, _s1_hazard_T_39}; // @[package.scala:45:27] wire [3:0] s1_hazard_lo_2 = {s1_hazard_lo_hi_2, s1_hazard_lo_lo_2}; // @[package.scala:45:27] wire [1:0] s1_hazard_hi_lo_2 = {_s1_hazard_T_42, _s1_hazard_T_41}; // @[package.scala:45:27] wire [1:0] s1_hazard_hi_hi_2 = {_s1_hazard_T_44, _s1_hazard_T_43}; // @[package.scala:45:27] wire [3:0] s1_hazard_hi_2 = {s1_hazard_hi_hi_2, s1_hazard_hi_lo_2}; // @[package.scala:45:27] wire [7:0] _s1_hazard_T_45 = {s1_hazard_hi_2, s1_hazard_lo_2}; // @[package.scala:45:27] wire _s1_hazard_T_46 = _s1_hazard_T_45[0]; // @[package.scala:45:27] wire _s1_hazard_T_47 = _s1_hazard_T_45[1]; // @[package.scala:45:27] wire _s1_hazard_T_48 = _s1_hazard_T_45[2]; // @[package.scala:45:27] wire _s1_hazard_T_49 = _s1_hazard_T_45[3]; // @[package.scala:45:27] wire _s1_hazard_T_50 = _s1_hazard_T_45[4]; // @[package.scala:45:27] wire _s1_hazard_T_51 = _s1_hazard_T_45[5]; // @[package.scala:45:27] wire _s1_hazard_T_52 = _s1_hazard_T_45[6]; // @[package.scala:45:27] wire _s1_hazard_T_53 = _s1_hazard_T_45[7]; // @[package.scala:45:27] wire [1:0] s1_hazard_lo_lo_3 = {_s1_hazard_T_47, _s1_hazard_T_46}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_lo_hi_3 = {_s1_hazard_T_49, _s1_hazard_T_48}; // @[DCache.scala:1182:52] wire [3:0] s1_hazard_lo_3 = {s1_hazard_lo_hi_3, s1_hazard_lo_lo_3}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_hi_lo_3 = {_s1_hazard_T_51, _s1_hazard_T_50}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_hi_hi_3 = {_s1_hazard_T_53, _s1_hazard_T_52}; // @[DCache.scala:1182:52] wire [3:0] s1_hazard_hi_3 = {s1_hazard_hi_hi_3, s1_hazard_hi_lo_3}; // @[DCache.scala:1182:52] wire [7:0] _s1_hazard_T_54 = {s1_hazard_hi_3, s1_hazard_lo_3}; // @[DCache.scala:1182:52] wire [7:0] _s1_hazard_T_55 = _s1_hazard_T_28 & _s1_hazard_T_54; // @[DCache.scala:562:38, :1182:52] wire _s1_hazard_T_56 = |_s1_hazard_T_55; // @[DCache.scala:562:{38,66}] wire [7:0] _s1_hazard_T_57 = pstore1_mask & s1_mask_xwr; // @[DCache.scala:496:31, :562:77] wire _s1_hazard_T_58 = |_s1_hazard_T_57; // @[DCache.scala:562:{77,92}] wire _s1_hazard_T_59 = s1_write ? _s1_hazard_T_56 : _s1_hazard_T_58; // @[DCache.scala:562:{8,66,92}] wire _s1_hazard_T_60 = _s1_hazard_T_2 & _s1_hazard_T_59; // @[DCache.scala:561:{31,65}, :562:8] wire _s1_hazard_T_61 = pstore1_valid_likely & _s1_hazard_T_60; // @[DCache.scala:505:51, :561:65, :564:27] wire [10:0] _s1_hazard_T_62 = pstore2_addr[13:3]; // @[DCache.scala:524:31, :561:9] wire _s1_hazard_T_64 = _s1_hazard_T_62 == _s1_hazard_T_63; // @[DCache.scala:561:{9,31,43}] wire _s1_hazard_T_65 = pstore2_storegen_mask[0]; // @[package.scala:211:50] wire _s1_hazard_T_73 = _s1_hazard_T_65; // @[package.scala:211:50] wire _s1_hazard_T_66 = pstore2_storegen_mask[1]; // @[package.scala:211:50] wire _s1_hazard_T_74 = _s1_hazard_T_66; // @[package.scala:211:50] wire _s1_hazard_T_67 = pstore2_storegen_mask[2]; // @[package.scala:211:50] wire _s1_hazard_T_75 = _s1_hazard_T_67; // @[package.scala:211:50] wire _s1_hazard_T_68 = pstore2_storegen_mask[3]; // @[package.scala:211:50] wire _s1_hazard_T_76 = _s1_hazard_T_68; // @[package.scala:211:50] wire _s1_hazard_T_69 = pstore2_storegen_mask[4]; // @[package.scala:211:50] wire _s1_hazard_T_77 = _s1_hazard_T_69; // @[package.scala:211:50] wire _s1_hazard_T_70 = pstore2_storegen_mask[5]; // @[package.scala:211:50] wire _s1_hazard_T_78 = _s1_hazard_T_70; // @[package.scala:211:50] wire _s1_hazard_T_71 = pstore2_storegen_mask[6]; // @[package.scala:211:50] wire _s1_hazard_T_79 = _s1_hazard_T_71; // @[package.scala:211:50] wire _s1_hazard_T_72 = pstore2_storegen_mask[7]; // @[package.scala:211:50] wire _s1_hazard_T_80 = _s1_hazard_T_72; // @[package.scala:211:50] wire [1:0] s1_hazard_lo_lo_4 = {_s1_hazard_T_74, _s1_hazard_T_73}; // @[package.scala:45:27] wire [1:0] s1_hazard_lo_hi_4 = {_s1_hazard_T_76, _s1_hazard_T_75}; // @[package.scala:45:27] wire [3:0] s1_hazard_lo_4 = {s1_hazard_lo_hi_4, s1_hazard_lo_lo_4}; // @[package.scala:45:27] wire [1:0] s1_hazard_hi_lo_4 = {_s1_hazard_T_78, _s1_hazard_T_77}; // @[package.scala:45:27] wire [1:0] s1_hazard_hi_hi_4 = {_s1_hazard_T_80, _s1_hazard_T_79}; // @[package.scala:45:27] wire [3:0] s1_hazard_hi_4 = {s1_hazard_hi_hi_4, s1_hazard_hi_lo_4}; // @[package.scala:45:27] wire [7:0] _s1_hazard_T_81 = {s1_hazard_hi_4, s1_hazard_lo_4}; // @[package.scala:45:27] wire _s1_hazard_T_82 = _s1_hazard_T_81[0]; // @[package.scala:45:27] wire _s1_hazard_T_83 = _s1_hazard_T_81[1]; // @[package.scala:45:27] wire _s1_hazard_T_84 = _s1_hazard_T_81[2]; // @[package.scala:45:27] wire _s1_hazard_T_85 = _s1_hazard_T_81[3]; // @[package.scala:45:27] wire _s1_hazard_T_86 = _s1_hazard_T_81[4]; // @[package.scala:45:27] wire _s1_hazard_T_87 = _s1_hazard_T_81[5]; // @[package.scala:45:27] wire _s1_hazard_T_88 = _s1_hazard_T_81[6]; // @[package.scala:45:27] wire _s1_hazard_T_89 = _s1_hazard_T_81[7]; // @[package.scala:45:27] wire [1:0] s1_hazard_lo_lo_5 = {_s1_hazard_T_83, _s1_hazard_T_82}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_lo_hi_5 = {_s1_hazard_T_85, _s1_hazard_T_84}; // @[DCache.scala:1182:52] wire [3:0] s1_hazard_lo_5 = {s1_hazard_lo_hi_5, s1_hazard_lo_lo_5}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_hi_lo_5 = {_s1_hazard_T_87, _s1_hazard_T_86}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_hi_hi_5 = {_s1_hazard_T_89, _s1_hazard_T_88}; // @[DCache.scala:1182:52] wire [3:0] s1_hazard_hi_5 = {s1_hazard_hi_hi_5, s1_hazard_hi_lo_5}; // @[DCache.scala:1182:52] wire [7:0] _s1_hazard_T_90 = {s1_hazard_hi_5, s1_hazard_lo_5}; // @[DCache.scala:1182:52] wire _s1_hazard_T_99 = _s1_hazard_T_91; // @[package.scala:211:50] wire _s1_hazard_T_100 = _s1_hazard_T_92; // @[package.scala:211:50] wire _s1_hazard_T_101 = _s1_hazard_T_93; // @[package.scala:211:50] wire _s1_hazard_T_102 = _s1_hazard_T_94; // @[package.scala:211:50] wire _s1_hazard_T_103 = _s1_hazard_T_95; // @[package.scala:211:50] wire _s1_hazard_T_104 = _s1_hazard_T_96; // @[package.scala:211:50] wire _s1_hazard_T_105 = _s1_hazard_T_97; // @[package.scala:211:50] wire _s1_hazard_T_106 = _s1_hazard_T_98; // @[package.scala:211:50] wire [1:0] s1_hazard_lo_lo_6 = {_s1_hazard_T_100, _s1_hazard_T_99}; // @[package.scala:45:27] wire [1:0] s1_hazard_lo_hi_6 = {_s1_hazard_T_102, _s1_hazard_T_101}; // @[package.scala:45:27] wire [3:0] s1_hazard_lo_6 = {s1_hazard_lo_hi_6, s1_hazard_lo_lo_6}; // @[package.scala:45:27] wire [1:0] s1_hazard_hi_lo_6 = {_s1_hazard_T_104, _s1_hazard_T_103}; // @[package.scala:45:27] wire [1:0] s1_hazard_hi_hi_6 = {_s1_hazard_T_106, _s1_hazard_T_105}; // @[package.scala:45:27] wire [3:0] s1_hazard_hi_6 = {s1_hazard_hi_hi_6, s1_hazard_hi_lo_6}; // @[package.scala:45:27] wire [7:0] _s1_hazard_T_107 = {s1_hazard_hi_6, s1_hazard_lo_6}; // @[package.scala:45:27] wire _s1_hazard_T_108 = _s1_hazard_T_107[0]; // @[package.scala:45:27] wire _s1_hazard_T_109 = _s1_hazard_T_107[1]; // @[package.scala:45:27] wire _s1_hazard_T_110 = _s1_hazard_T_107[2]; // @[package.scala:45:27] wire _s1_hazard_T_111 = _s1_hazard_T_107[3]; // @[package.scala:45:27] wire _s1_hazard_T_112 = _s1_hazard_T_107[4]; // @[package.scala:45:27] wire _s1_hazard_T_113 = _s1_hazard_T_107[5]; // @[package.scala:45:27] wire _s1_hazard_T_114 = _s1_hazard_T_107[6]; // @[package.scala:45:27] wire _s1_hazard_T_115 = _s1_hazard_T_107[7]; // @[package.scala:45:27] wire [1:0] s1_hazard_lo_lo_7 = {_s1_hazard_T_109, _s1_hazard_T_108}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_lo_hi_7 = {_s1_hazard_T_111, _s1_hazard_T_110}; // @[DCache.scala:1182:52] wire [3:0] s1_hazard_lo_7 = {s1_hazard_lo_hi_7, s1_hazard_lo_lo_7}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_hi_lo_7 = {_s1_hazard_T_113, _s1_hazard_T_112}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_hi_hi_7 = {_s1_hazard_T_115, _s1_hazard_T_114}; // @[DCache.scala:1182:52] wire [3:0] s1_hazard_hi_7 = {s1_hazard_hi_hi_7, s1_hazard_hi_lo_7}; // @[DCache.scala:1182:52] wire [7:0] _s1_hazard_T_116 = {s1_hazard_hi_7, s1_hazard_lo_7}; // @[DCache.scala:1182:52] wire [7:0] _s1_hazard_T_117 = _s1_hazard_T_90 & _s1_hazard_T_116; // @[DCache.scala:562:38, :1182:52] wire _s1_hazard_T_118 = |_s1_hazard_T_117; // @[DCache.scala:562:{38,66}] wire [7:0] _s1_hazard_T_119 = pstore2_storegen_mask & s1_mask_xwr; // @[DCache.scala:531:19, :562:77] wire _s1_hazard_T_120 = |_s1_hazard_T_119; // @[DCache.scala:562:{77,92}] wire _s1_hazard_T_121 = s1_write ? _s1_hazard_T_118 : _s1_hazard_T_120; // @[DCache.scala:562:{8,66,92}] wire _s1_hazard_T_122 = _s1_hazard_T_64 & _s1_hazard_T_121; // @[DCache.scala:561:{31,65}, :562:8] wire _s1_hazard_T_123 = pstore2_valid & _s1_hazard_T_122; // @[DCache.scala:501:30, :561:65, :565:21] wire s1_hazard = _s1_hazard_T_61 | _s1_hazard_T_123; // @[DCache.scala:564:{27,69}, :565:21] wire s1_raw_hazard = s1_read & s1_hazard; // @[DCache.scala:564:69, :566:31] assign s1_nack = s1_valid & s1_raw_hazard | io_cpu_s2_nack_0 | _metaArb_io_in_2_valid_T; // @[DCache.scala:101:7, :182:25, :185:28, :288:75, :446:{24,82,92}, :462:63, :566:31, :571:{18,36,46}] reg io_cpu_s2_nack_cause_raw_REG; // @[DCache.scala:574:38] assign _io_cpu_s2_nack_cause_raw_T_3 = io_cpu_s2_nack_cause_raw_REG; // @[DCache.scala:574:{38,54}] assign io_cpu_s2_nack_cause_raw_0 = _io_cpu_s2_nack_cause_raw_T_3; // @[DCache.scala:101:7, :574:54] wire _a_source_T = ~uncachedInFlight_0; // @[DCache.scala:236:33, :577:34] wire _a_source_T_1 = _a_source_T; // @[DCache.scala:577:{34,59}] wire _a_source_T_2 = _a_source_T_1; // @[OneHot.scala:48:45] wire [33:0] acquire_address = {_acquire_address_T, 6'h0}; // @[DCache.scala:578:{38,49}] wire [22:0] a_mask = {15'h0, pstore1_mask}; // @[DCache.scala:496:31, :582:29] wire [33:0] _GEN_91 = {s2_req_addr[33:14], _s2_vaddr_T_2 ^ 14'h3000}; // @[DCache.scala:339:19, :351:103, :467:68] wire [33:0] _get_legal_T_4; // @[Parameters.scala:137:31] assign _get_legal_T_4 = _GEN_91; // @[Parameters.scala:137:31] wire [33:0] _put_legal_T_4; // @[Parameters.scala:137:31] assign _put_legal_T_4 = _GEN_91; // @[Parameters.scala:137:31] wire [33:0] _putpartial_legal_T_4; // @[Parameters.scala:137:31] assign _putpartial_legal_T_4 = _GEN_91; // @[Parameters.scala:137:31] wire [34:0] _get_legal_T_5 = {1'h0, _get_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [34:0] _get_legal_T_6 = _get_legal_T_5 & 35'h8A113000; // @[Parameters.scala:137:{41,46}] wire [34:0] _get_legal_T_7 = _get_legal_T_6; // @[Parameters.scala:137:46] wire _get_legal_T_8 = _get_legal_T_7 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _get_legal_T_9 = _get_legal_T_8; // @[Parameters.scala:684:54] wire _get_legal_T_50 = _get_legal_T_9; // @[Parameters.scala:684:54, :686:26] wire [34:0] _get_legal_T_15 = {1'h0, _get_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [34:0] _get_legal_T_16 = _get_legal_T_15 & 35'h8A112000; // @[Parameters.scala:137:{41,46}] wire [34:0] _get_legal_T_17 = _get_legal_T_16; // @[Parameters.scala:137:46] wire _get_legal_T_18 = _get_legal_T_17 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [33:0] _GEN_92 = {s2_req_addr[33:17], s2_req_addr[16:0] ^ 17'h10000}; // @[DCache.scala:339:19] wire [33:0] _get_legal_T_19; // @[Parameters.scala:137:31] assign _get_legal_T_19 = _GEN_92; // @[Parameters.scala:137:31] wire [33:0] _put_legal_T_45; // @[Parameters.scala:137:31] assign _put_legal_T_45 = _GEN_92; // @[Parameters.scala:137:31] wire [33:0] _putpartial_legal_T_45; // @[Parameters.scala:137:31] assign _putpartial_legal_T_45 = _GEN_92; // @[Parameters.scala:137:31] wire [33:0] _atomics_legal_T_23; // @[Parameters.scala:137:31] assign _atomics_legal_T_23 = _GEN_92; // @[Parameters.scala:137:31] wire [33:0] _atomics_legal_T_53; // @[Parameters.scala:137:31] assign _atomics_legal_T_53 = _GEN_92; // @[Parameters.scala:137:31] wire [33:0] _atomics_legal_T_83; // @[Parameters.scala:137:31] assign _atomics_legal_T_83 = _GEN_92; // @[Parameters.scala:137:31] wire [33:0] _atomics_legal_T_113; // @[Parameters.scala:137:31] assign _atomics_legal_T_113 = _GEN_92; // @[Parameters.scala:137:31] wire [33:0] _atomics_legal_T_143; // @[Parameters.scala:137:31] assign _atomics_legal_T_143 = _GEN_92; // @[Parameters.scala:137:31] wire [33:0] _atomics_legal_T_173; // @[Parameters.scala:137:31] assign _atomics_legal_T_173 = _GEN_92; // @[Parameters.scala:137:31] wire [33:0] _atomics_legal_T_203; // @[Parameters.scala:137:31] assign _atomics_legal_T_203 = _GEN_92; // @[Parameters.scala:137:31] wire [33:0] _atomics_legal_T_233; // @[Parameters.scala:137:31] assign _atomics_legal_T_233 = _GEN_92; // @[Parameters.scala:137:31] wire [33:0] _atomics_legal_T_263; // @[Parameters.scala:137:31] assign _atomics_legal_T_263 = _GEN_92; // @[Parameters.scala:137:31] wire [34:0] _get_legal_T_20 = {1'h0, _get_legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [34:0] _get_legal_T_21 = _get_legal_T_20 & 35'h8A110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _get_legal_T_22 = _get_legal_T_21; // @[Parameters.scala:137:46] wire _get_legal_T_23 = _get_legal_T_22 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [33:0] _GEN_93 = {s2_req_addr[33:21], s2_req_addr[20:0] ^ 21'h100000}; // @[DCache.scala:339:19] wire [33:0] _get_legal_T_24; // @[Parameters.scala:137:31] assign _get_legal_T_24 = _GEN_93; // @[Parameters.scala:137:31] wire [33:0] _put_legal_T_19; // @[Parameters.scala:137:31] assign _put_legal_T_19 = _GEN_93; // @[Parameters.scala:137:31] wire [33:0] _putpartial_legal_T_19; // @[Parameters.scala:137:31] assign _putpartial_legal_T_19 = _GEN_93; // @[Parameters.scala:137:31] wire [33:0] _atomics_legal_T_9; // @[Parameters.scala:137:31] assign _atomics_legal_T_9 = _GEN_93; // @[Parameters.scala:137:31] wire [33:0] _atomics_legal_T_39; // @[Parameters.scala:137:31] assign _atomics_legal_T_39 = _GEN_93; // @[Parameters.scala:137:31] wire [33:0] _atomics_legal_T_69; // @[Parameters.scala:137:31] assign _atomics_legal_T_69 = _GEN_93; // @[Parameters.scala:137:31] wire [33:0] _atomics_legal_T_99; // @[Parameters.scala:137:31] assign _atomics_legal_T_99 = _GEN_93; // @[Parameters.scala:137:31] wire [33:0] _atomics_legal_T_129; // @[Parameters.scala:137:31] assign _atomics_legal_T_129 = _GEN_93; // @[Parameters.scala:137:31] wire [33:0] _atomics_legal_T_159; // @[Parameters.scala:137:31] assign _atomics_legal_T_159 = _GEN_93; // @[Parameters.scala:137:31] wire [33:0] _atomics_legal_T_189; // @[Parameters.scala:137:31] assign _atomics_legal_T_189 = _GEN_93; // @[Parameters.scala:137:31] wire [33:0] _atomics_legal_T_219; // @[Parameters.scala:137:31] assign _atomics_legal_T_219 = _GEN_93; // @[Parameters.scala:137:31] wire [33:0] _atomics_legal_T_249; // @[Parameters.scala:137:31] assign _atomics_legal_T_249 = _GEN_93; // @[Parameters.scala:137:31] wire [34:0] _get_legal_T_25 = {1'h0, _get_legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [34:0] _get_legal_T_26 = _get_legal_T_25 & 35'h8A103000; // @[Parameters.scala:137:{41,46}] wire [34:0] _get_legal_T_27 = _get_legal_T_26; // @[Parameters.scala:137:46] wire _get_legal_T_28 = _get_legal_T_27 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [33:0] _GEN_94 = {s2_req_addr[33:26], s2_req_addr[25:0] ^ 26'h2000000}; // @[DCache.scala:339:19] wire [33:0] _get_legal_T_29; // @[Parameters.scala:137:31] assign _get_legal_T_29 = _GEN_94; // @[Parameters.scala:137:31] wire [33:0] _put_legal_T_24; // @[Parameters.scala:137:31] assign _put_legal_T_24 = _GEN_94; // @[Parameters.scala:137:31] wire [33:0] _putpartial_legal_T_24; // @[Parameters.scala:137:31] assign _putpartial_legal_T_24 = _GEN_94; // @[Parameters.scala:137:31] wire [34:0] _get_legal_T_30 = {1'h0, _get_legal_T_29}; // @[Parameters.scala:137:{31,41}] wire [34:0] _get_legal_T_31 = _get_legal_T_30 & 35'h8A110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _get_legal_T_32 = _get_legal_T_31; // @[Parameters.scala:137:46] wire _get_legal_T_33 = _get_legal_T_32 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [33:0] _GEN_95 = {s2_req_addr[33:28], s2_req_addr[27:0] ^ 28'h8000000}; // @[DCache.scala:339:19] wire [33:0] _get_legal_T_34; // @[Parameters.scala:137:31] assign _get_legal_T_34 = _GEN_95; // @[Parameters.scala:137:31] wire [33:0] _put_legal_T_29; // @[Parameters.scala:137:31] assign _put_legal_T_29 = _GEN_95; // @[Parameters.scala:137:31] wire [33:0] _putpartial_legal_T_29; // @[Parameters.scala:137:31] assign _putpartial_legal_T_29 = _GEN_95; // @[Parameters.scala:137:31] wire [33:0] _atomics_legal_T_14; // @[Parameters.scala:137:31] assign _atomics_legal_T_14 = _GEN_95; // @[Parameters.scala:137:31] wire [33:0] _atomics_legal_T_44; // @[Parameters.scala:137:31] assign _atomics_legal_T_44 = _GEN_95; // @[Parameters.scala:137:31] wire [33:0] _atomics_legal_T_74; // @[Parameters.scala:137:31] assign _atomics_legal_T_74 = _GEN_95; // @[Parameters.scala:137:31] wire [33:0] _atomics_legal_T_104; // @[Parameters.scala:137:31] assign _atomics_legal_T_104 = _GEN_95; // @[Parameters.scala:137:31] wire [33:0] _atomics_legal_T_134; // @[Parameters.scala:137:31] assign _atomics_legal_T_134 = _GEN_95; // @[Parameters.scala:137:31] wire [33:0] _atomics_legal_T_164; // @[Parameters.scala:137:31] assign _atomics_legal_T_164 = _GEN_95; // @[Parameters.scala:137:31] wire [33:0] _atomics_legal_T_194; // @[Parameters.scala:137:31] assign _atomics_legal_T_194 = _GEN_95; // @[Parameters.scala:137:31] wire [33:0] _atomics_legal_T_224; // @[Parameters.scala:137:31] assign _atomics_legal_T_224 = _GEN_95; // @[Parameters.scala:137:31] wire [33:0] _atomics_legal_T_254; // @[Parameters.scala:137:31] assign _atomics_legal_T_254 = _GEN_95; // @[Parameters.scala:137:31] wire [34:0] _get_legal_T_35 = {1'h0, _get_legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [34:0] _get_legal_T_36 = _get_legal_T_35 & 35'h88000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _get_legal_T_37 = _get_legal_T_36; // @[Parameters.scala:137:46] wire _get_legal_T_38 = _get_legal_T_37 == 35'h0; // @[Parameters.scala:137:{46,59}] assign io_cpu_s2_paddr_0 = s2_req_addr[31:0]; // @[DCache.scala:101:7, :339:19] wire [31:0] get_address = s2_req_addr[31:0]; // @[Edges.scala:460:17] wire [31:0] put_address = s2_req_addr[31:0]; // @[Edges.scala:480:17] wire [31:0] putpartial_address = s2_req_addr[31:0]; // @[Edges.scala:500:17] wire [31:0] atomics_a_address = s2_req_addr[31:0]; // @[Edges.scala:534:17] wire [31:0] atomics_a_1_address = s2_req_addr[31:0]; // @[Edges.scala:534:17] wire [31:0] atomics_a_2_address = s2_req_addr[31:0]; // @[Edges.scala:534:17] wire [31:0] atomics_a_3_address = s2_req_addr[31:0]; // @[Edges.scala:534:17] wire [31:0] atomics_a_4_address = s2_req_addr[31:0]; // @[Edges.scala:517:17] wire [31:0] atomics_a_5_address = s2_req_addr[31:0]; // @[Edges.scala:517:17] wire [31:0] atomics_a_6_address = s2_req_addr[31:0]; // @[Edges.scala:517:17] wire [31:0] atomics_a_7_address = s2_req_addr[31:0]; // @[Edges.scala:517:17] wire [31:0] atomics_a_8_address = s2_req_addr[31:0]; // @[Edges.scala:517:17] wire [33:0] _GEN_96 = {s2_req_addr[33:32], s2_req_addr[31:0] ^ 32'h80000000}; // @[DCache.scala:339:19] wire [33:0] _get_legal_T_39; // @[Parameters.scala:137:31] assign _get_legal_T_39 = _GEN_96; // @[Parameters.scala:137:31] wire [33:0] _put_legal_T_34; // @[Parameters.scala:137:31] assign _put_legal_T_34 = _GEN_96; // @[Parameters.scala:137:31] wire [33:0] _putpartial_legal_T_34; // @[Parameters.scala:137:31] assign _putpartial_legal_T_34 = _GEN_96; // @[Parameters.scala:137:31] wire [34:0] _get_legal_T_40 = {1'h0, _get_legal_T_39}; // @[Parameters.scala:137:{31,41}] wire [34:0] _get_legal_T_41 = _get_legal_T_40 & 35'h8A110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _get_legal_T_42 = _get_legal_T_41; // @[Parameters.scala:137:46] wire _get_legal_T_43 = _get_legal_T_42 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _get_legal_T_44 = _get_legal_T_18 | _get_legal_T_23; // @[Parameters.scala:685:42] wire _get_legal_T_45 = _get_legal_T_44 | _get_legal_T_28; // @[Parameters.scala:685:42] wire _get_legal_T_46 = _get_legal_T_45 | _get_legal_T_33; // @[Parameters.scala:685:42] wire _get_legal_T_47 = _get_legal_T_46 | _get_legal_T_38; // @[Parameters.scala:685:42] wire _get_legal_T_48 = _get_legal_T_47 | _get_legal_T_43; // @[Parameters.scala:685:42] wire _get_legal_T_49 = _get_legal_T_48; // @[Parameters.scala:684:54, :685:42] wire get_legal = _get_legal_T_50 | _get_legal_T_49; // @[Parameters.scala:684:54, :686:26] wire [7:0] _get_a_mask_T; // @[Misc.scala:222:10] wire [3:0] get_size; // @[Edges.scala:460:17] wire [7:0] get_mask; // @[Edges.scala:460:17] wire [3:0] _GEN_97 = {2'h0, s2_req_size}; // @[Edges.scala:463:15] assign get_size = _GEN_97; // @[Edges.scala:460:17, :463:15] wire [3:0] put_size; // @[Edges.scala:480:17] assign put_size = _GEN_97; // @[Edges.scala:463:15, :480:17] wire [3:0] putpartial_size; // @[Edges.scala:500:17] assign putpartial_size = _GEN_97; // @[Edges.scala:463:15, :500:17] wire [3:0] atomics_a_size; // @[Edges.scala:534:17] assign atomics_a_size = _GEN_97; // @[Edges.scala:463:15, :534:17] wire [3:0] atomics_a_1_size; // @[Edges.scala:534:17] assign atomics_a_1_size = _GEN_97; // @[Edges.scala:463:15, :534:17] wire [3:0] atomics_a_2_size; // @[Edges.scala:534:17] assign atomics_a_2_size = _GEN_97; // @[Edges.scala:463:15, :534:17] wire [3:0] atomics_a_3_size; // @[Edges.scala:534:17] assign atomics_a_3_size = _GEN_97; // @[Edges.scala:463:15, :534:17] wire [3:0] atomics_a_4_size; // @[Edges.scala:517:17] assign atomics_a_4_size = _GEN_97; // @[Edges.scala:463:15, :517:17] wire [3:0] atomics_a_5_size; // @[Edges.scala:517:17] assign atomics_a_5_size = _GEN_97; // @[Edges.scala:463:15, :517:17] wire [3:0] atomics_a_6_size; // @[Edges.scala:517:17] assign atomics_a_6_size = _GEN_97; // @[Edges.scala:463:15, :517:17] wire [3:0] atomics_a_7_size; // @[Edges.scala:517:17] assign atomics_a_7_size = _GEN_97; // @[Edges.scala:463:15, :517:17] wire [3:0] atomics_a_8_size; // @[Edges.scala:517:17] assign atomics_a_8_size = _GEN_97; // @[Edges.scala:463:15, :517:17] wire [2:0] _GEN_98 = {1'h0, s2_req_size}; // @[Misc.scala:202:34] wire [2:0] _get_a_mask_sizeOH_T; // @[Misc.scala:202:34] assign _get_a_mask_sizeOH_T = _GEN_98; // @[Misc.scala:202:34] wire [2:0] _put_a_mask_sizeOH_T; // @[Misc.scala:202:34] assign _put_a_mask_sizeOH_T = _GEN_98; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T = _GEN_98; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T_3; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_3 = _GEN_98; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T_6; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_6 = _GEN_98; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T_9; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_9 = _GEN_98; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T_12; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_12 = _GEN_98; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T_15; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_15 = _GEN_98; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T_18; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_18 = _GEN_98; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T_21; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_21 = _GEN_98; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T_24; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_24 = _GEN_98; // @[Misc.scala:202:34] wire [1:0] get_a_mask_sizeOH_shiftAmount = _get_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _get_a_mask_sizeOH_T_1 = 4'h1 << get_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _get_a_mask_sizeOH_T_2 = _get_a_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] get_a_mask_sizeOH = {_get_a_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire get_a_mask_sub_sub_sub_0_1 = &s2_req_size; // @[Misc.scala:206:21] wire get_a_mask_sub_sub_size = get_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire get_a_mask_sub_sub_bit = s2_req_addr[2]; // @[Misc.scala:210:26] wire put_a_mask_sub_sub_bit = s2_req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit = s2_req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_1 = s2_req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_2 = s2_req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_3 = s2_req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_4 = s2_req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_5 = s2_req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_6 = s2_req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_7 = s2_req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_8 = s2_req_addr[2]; // @[Misc.scala:210:26] wire _io_cpu_resp_bits_data_shifted_T = s2_req_addr[2]; // @[Misc.scala:210:26] wire _io_cpu_resp_bits_data_word_bypass_shifted_T = s2_req_addr[2]; // @[Misc.scala:210:26] wire get_a_mask_sub_sub_1_2 = get_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire get_a_mask_sub_sub_nbit = ~get_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire get_a_mask_sub_sub_0_2 = get_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_sub_sub_acc_T = get_a_mask_sub_sub_size & get_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_sub_0_1 = get_a_mask_sub_sub_sub_0_1 | _get_a_mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _get_a_mask_sub_sub_acc_T_1 = get_a_mask_sub_sub_size & get_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_sub_1_1 = get_a_mask_sub_sub_sub_0_1 | _get_a_mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire get_a_mask_sub_size = get_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire get_a_mask_sub_bit = s2_req_addr[1]; // @[Misc.scala:210:26] wire put_a_mask_sub_bit = s2_req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit = s2_req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_1 = s2_req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_2 = s2_req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_3 = s2_req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_4 = s2_req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_5 = s2_req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_6 = s2_req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_7 = s2_req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_8 = s2_req_addr[1]; // @[Misc.scala:210:26] wire _io_cpu_resp_bits_data_shifted_T_3 = s2_req_addr[1]; // @[Misc.scala:210:26] wire get_a_mask_sub_nbit = ~get_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire get_a_mask_sub_0_2 = get_a_mask_sub_sub_0_2 & get_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_sub_acc_T = get_a_mask_sub_size & get_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_0_1 = get_a_mask_sub_sub_0_1 | _get_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_1_2 = get_a_mask_sub_sub_0_2 & get_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_sub_acc_T_1 = get_a_mask_sub_size & get_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_1_1 = get_a_mask_sub_sub_0_1 | _get_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_2_2 = get_a_mask_sub_sub_1_2 & get_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_sub_acc_T_2 = get_a_mask_sub_size & get_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_2_1 = get_a_mask_sub_sub_1_1 | _get_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_3_2 = get_a_mask_sub_sub_1_2 & get_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_sub_acc_T_3 = get_a_mask_sub_size & get_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_3_1 = get_a_mask_sub_sub_1_1 | _get_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire get_a_mask_size = get_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire get_a_mask_bit = s2_req_addr[0]; // @[Misc.scala:210:26] wire put_a_mask_bit = s2_req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit = s2_req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_1 = s2_req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_2 = s2_req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_3 = s2_req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_4 = s2_req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_5 = s2_req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_6 = s2_req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_7 = s2_req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_8 = s2_req_addr[0]; // @[Misc.scala:210:26] wire _io_cpu_resp_bits_data_shifted_T_6 = s2_req_addr[0]; // @[Misc.scala:210:26] wire get_a_mask_nbit = ~get_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire get_a_mask_eq = get_a_mask_sub_0_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T = get_a_mask_size & get_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc = get_a_mask_sub_0_1 | _get_a_mask_acc_T; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_1 = get_a_mask_sub_0_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_1 = get_a_mask_size & get_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_1 = get_a_mask_sub_0_1 | _get_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_2 = get_a_mask_sub_1_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T_2 = get_a_mask_size & get_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_2 = get_a_mask_sub_1_1 | _get_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_3 = get_a_mask_sub_1_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_3 = get_a_mask_size & get_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_3 = get_a_mask_sub_1_1 | _get_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_4 = get_a_mask_sub_2_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T_4 = get_a_mask_size & get_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_4 = get_a_mask_sub_2_1 | _get_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_5 = get_a_mask_sub_2_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_5 = get_a_mask_size & get_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_5 = get_a_mask_sub_2_1 | _get_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_6 = get_a_mask_sub_3_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T_6 = get_a_mask_size & get_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_6 = get_a_mask_sub_3_1 | _get_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_7 = get_a_mask_sub_3_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_7 = get_a_mask_size & get_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_7 = get_a_mask_sub_3_1 | _get_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] get_a_mask_lo_lo = {get_a_mask_acc_1, get_a_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] get_a_mask_lo_hi = {get_a_mask_acc_3, get_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] get_a_mask_lo = {get_a_mask_lo_hi, get_a_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] get_a_mask_hi_lo = {get_a_mask_acc_5, get_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] get_a_mask_hi_hi = {get_a_mask_acc_7, get_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] get_a_mask_hi = {get_a_mask_hi_hi, get_a_mask_hi_lo}; // @[Misc.scala:222:10] assign _get_a_mask_T = {get_a_mask_hi, get_a_mask_lo}; // @[Misc.scala:222:10] assign get_mask = _get_a_mask_T; // @[Misc.scala:222:10] wire [34:0] _put_legal_T_5 = {1'h0, _put_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [34:0] _put_legal_T_6 = _put_legal_T_5 & 35'h8A113000; // @[Parameters.scala:137:{41,46}] wire [34:0] _put_legal_T_7 = _put_legal_T_6; // @[Parameters.scala:137:46] wire _put_legal_T_8 = _put_legal_T_7 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _put_legal_T_9 = _put_legal_T_8; // @[Parameters.scala:684:54] wire _put_legal_T_51 = _put_legal_T_9; // @[Parameters.scala:684:54, :686:26] wire [34:0] _put_legal_T_15 = {1'h0, _put_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [34:0] _put_legal_T_16 = _put_legal_T_15 & 35'h8A112000; // @[Parameters.scala:137:{41,46}] wire [34:0] _put_legal_T_17 = _put_legal_T_16; // @[Parameters.scala:137:46] wire _put_legal_T_18 = _put_legal_T_17 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _put_legal_T_20 = {1'h0, _put_legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [34:0] _put_legal_T_21 = _put_legal_T_20 & 35'h8A103000; // @[Parameters.scala:137:{41,46}] wire [34:0] _put_legal_T_22 = _put_legal_T_21; // @[Parameters.scala:137:46] wire _put_legal_T_23 = _put_legal_T_22 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _put_legal_T_25 = {1'h0, _put_legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [34:0] _put_legal_T_26 = _put_legal_T_25 & 35'h8A110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _put_legal_T_27 = _put_legal_T_26; // @[Parameters.scala:137:46] wire _put_legal_T_28 = _put_legal_T_27 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _put_legal_T_30 = {1'h0, _put_legal_T_29}; // @[Parameters.scala:137:{31,41}] wire [34:0] _put_legal_T_31 = _put_legal_T_30 & 35'h88000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _put_legal_T_32 = _put_legal_T_31; // @[Parameters.scala:137:46] wire _put_legal_T_33 = _put_legal_T_32 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _put_legal_T_35 = {1'h0, _put_legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [34:0] _put_legal_T_36 = _put_legal_T_35 & 35'h8A110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _put_legal_T_37 = _put_legal_T_36; // @[Parameters.scala:137:46] wire _put_legal_T_38 = _put_legal_T_37 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _put_legal_T_39 = _put_legal_T_18 | _put_legal_T_23; // @[Parameters.scala:685:42] wire _put_legal_T_40 = _put_legal_T_39 | _put_legal_T_28; // @[Parameters.scala:685:42] wire _put_legal_T_41 = _put_legal_T_40 | _put_legal_T_33; // @[Parameters.scala:685:42] wire _put_legal_T_42 = _put_legal_T_41 | _put_legal_T_38; // @[Parameters.scala:685:42] wire _put_legal_T_43 = _put_legal_T_42; // @[Parameters.scala:684:54, :685:42] wire [34:0] _put_legal_T_46 = {1'h0, _put_legal_T_45}; // @[Parameters.scala:137:{31,41}] wire [34:0] _put_legal_T_47 = _put_legal_T_46 & 35'h8A110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _put_legal_T_48 = _put_legal_T_47; // @[Parameters.scala:137:46] wire _put_legal_T_49 = _put_legal_T_48 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _put_legal_T_52 = _put_legal_T_51 | _put_legal_T_43; // @[Parameters.scala:684:54, :686:26] wire put_legal = _put_legal_T_52; // @[Parameters.scala:686:26] wire [7:0] _put_a_mask_T; // @[Misc.scala:222:10] wire [7:0] put_mask; // @[Edges.scala:480:17] wire [1:0] put_a_mask_sizeOH_shiftAmount = _put_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _put_a_mask_sizeOH_T_1 = 4'h1 << put_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _put_a_mask_sizeOH_T_2 = _put_a_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] put_a_mask_sizeOH = {_put_a_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire put_a_mask_sub_sub_sub_0_1 = &s2_req_size; // @[Misc.scala:206:21] wire put_a_mask_sub_sub_size = put_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire put_a_mask_sub_sub_1_2 = put_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire put_a_mask_sub_sub_nbit = ~put_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire put_a_mask_sub_sub_0_2 = put_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_sub_sub_acc_T = put_a_mask_sub_sub_size & put_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_sub_0_1 = put_a_mask_sub_sub_sub_0_1 | _put_a_mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _put_a_mask_sub_sub_acc_T_1 = put_a_mask_sub_sub_size & put_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_sub_1_1 = put_a_mask_sub_sub_sub_0_1 | _put_a_mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire put_a_mask_sub_size = put_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire put_a_mask_sub_nbit = ~put_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire put_a_mask_sub_0_2 = put_a_mask_sub_sub_0_2 & put_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_sub_acc_T = put_a_mask_sub_size & put_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_0_1 = put_a_mask_sub_sub_0_1 | _put_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_1_2 = put_a_mask_sub_sub_0_2 & put_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_sub_acc_T_1 = put_a_mask_sub_size & put_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_1_1 = put_a_mask_sub_sub_0_1 | _put_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_2_2 = put_a_mask_sub_sub_1_2 & put_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_sub_acc_T_2 = put_a_mask_sub_size & put_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_2_1 = put_a_mask_sub_sub_1_1 | _put_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_3_2 = put_a_mask_sub_sub_1_2 & put_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_sub_acc_T_3 = put_a_mask_sub_size & put_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_3_1 = put_a_mask_sub_sub_1_1 | _put_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire put_a_mask_size = put_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire put_a_mask_nbit = ~put_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire put_a_mask_eq = put_a_mask_sub_0_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T = put_a_mask_size & put_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc = put_a_mask_sub_0_1 | _put_a_mask_acc_T; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_1 = put_a_mask_sub_0_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_1 = put_a_mask_size & put_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_1 = put_a_mask_sub_0_1 | _put_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_2 = put_a_mask_sub_1_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T_2 = put_a_mask_size & put_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_2 = put_a_mask_sub_1_1 | _put_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_3 = put_a_mask_sub_1_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_3 = put_a_mask_size & put_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_3 = put_a_mask_sub_1_1 | _put_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_4 = put_a_mask_sub_2_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T_4 = put_a_mask_size & put_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_4 = put_a_mask_sub_2_1 | _put_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_5 = put_a_mask_sub_2_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_5 = put_a_mask_size & put_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_5 = put_a_mask_sub_2_1 | _put_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_6 = put_a_mask_sub_3_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T_6 = put_a_mask_size & put_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_6 = put_a_mask_sub_3_1 | _put_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_7 = put_a_mask_sub_3_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_7 = put_a_mask_size & put_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_7 = put_a_mask_sub_3_1 | _put_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] put_a_mask_lo_lo = {put_a_mask_acc_1, put_a_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] put_a_mask_lo_hi = {put_a_mask_acc_3, put_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] put_a_mask_lo = {put_a_mask_lo_hi, put_a_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] put_a_mask_hi_lo = {put_a_mask_acc_5, put_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] put_a_mask_hi_hi = {put_a_mask_acc_7, put_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] put_a_mask_hi = {put_a_mask_hi_hi, put_a_mask_hi_lo}; // @[Misc.scala:222:10] assign _put_a_mask_T = {put_a_mask_hi, put_a_mask_lo}; // @[Misc.scala:222:10] assign put_mask = _put_a_mask_T; // @[Misc.scala:222:10] wire [34:0] _putpartial_legal_T_5 = {1'h0, _putpartial_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [34:0] _putpartial_legal_T_6 = _putpartial_legal_T_5 & 35'h8A113000; // @[Parameters.scala:137:{41,46}] wire [34:0] _putpartial_legal_T_7 = _putpartial_legal_T_6; // @[Parameters.scala:137:46] wire _putpartial_legal_T_8 = _putpartial_legal_T_7 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _putpartial_legal_T_9 = _putpartial_legal_T_8; // @[Parameters.scala:684:54] wire _putpartial_legal_T_51 = _putpartial_legal_T_9; // @[Parameters.scala:684:54, :686:26] wire [34:0] _putpartial_legal_T_15 = {1'h0, _putpartial_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [34:0] _putpartial_legal_T_16 = _putpartial_legal_T_15 & 35'h8A112000; // @[Parameters.scala:137:{41,46}] wire [34:0] _putpartial_legal_T_17 = _putpartial_legal_T_16; // @[Parameters.scala:137:46] wire _putpartial_legal_T_18 = _putpartial_legal_T_17 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _putpartial_legal_T_20 = {1'h0, _putpartial_legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [34:0] _putpartial_legal_T_21 = _putpartial_legal_T_20 & 35'h8A103000; // @[Parameters.scala:137:{41,46}] wire [34:0] _putpartial_legal_T_22 = _putpartial_legal_T_21; // @[Parameters.scala:137:46] wire _putpartial_legal_T_23 = _putpartial_legal_T_22 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _putpartial_legal_T_25 = {1'h0, _putpartial_legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [34:0] _putpartial_legal_T_26 = _putpartial_legal_T_25 & 35'h8A110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _putpartial_legal_T_27 = _putpartial_legal_T_26; // @[Parameters.scala:137:46] wire _putpartial_legal_T_28 = _putpartial_legal_T_27 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _putpartial_legal_T_30 = {1'h0, _putpartial_legal_T_29}; // @[Parameters.scala:137:{31,41}] wire [34:0] _putpartial_legal_T_31 = _putpartial_legal_T_30 & 35'h88000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _putpartial_legal_T_32 = _putpartial_legal_T_31; // @[Parameters.scala:137:46] wire _putpartial_legal_T_33 = _putpartial_legal_T_32 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _putpartial_legal_T_35 = {1'h0, _putpartial_legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [34:0] _putpartial_legal_T_36 = _putpartial_legal_T_35 & 35'h8A110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _putpartial_legal_T_37 = _putpartial_legal_T_36; // @[Parameters.scala:137:46] wire _putpartial_legal_T_38 = _putpartial_legal_T_37 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _putpartial_legal_T_39 = _putpartial_legal_T_18 | _putpartial_legal_T_23; // @[Parameters.scala:685:42] wire _putpartial_legal_T_40 = _putpartial_legal_T_39 | _putpartial_legal_T_28; // @[Parameters.scala:685:42] wire _putpartial_legal_T_41 = _putpartial_legal_T_40 | _putpartial_legal_T_33; // @[Parameters.scala:685:42] wire _putpartial_legal_T_42 = _putpartial_legal_T_41 | _putpartial_legal_T_38; // @[Parameters.scala:685:42] wire _putpartial_legal_T_43 = _putpartial_legal_T_42; // @[Parameters.scala:684:54, :685:42] wire [34:0] _putpartial_legal_T_46 = {1'h0, _putpartial_legal_T_45}; // @[Parameters.scala:137:{31,41}] wire [34:0] _putpartial_legal_T_47 = _putpartial_legal_T_46 & 35'h8A110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _putpartial_legal_T_48 = _putpartial_legal_T_47; // @[Parameters.scala:137:46] wire _putpartial_legal_T_49 = _putpartial_legal_T_48 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _putpartial_legal_T_52 = _putpartial_legal_T_51 | _putpartial_legal_T_43; // @[Parameters.scala:684:54, :686:26] wire putpartial_legal = _putpartial_legal_T_52; // @[Parameters.scala:686:26] wire [7:0] putpartial_mask; // @[Edges.scala:500:17] assign putpartial_mask = a_mask[7:0]; // @[Edges.scala:500:17, :508:15] wire [34:0] _atomics_legal_T_5 = {1'h0, _atomics_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [34:0] _atomics_legal_T_6 = _atomics_legal_T_5 & 35'h8110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _atomics_legal_T_7 = _atomics_legal_T_6; // @[Parameters.scala:137:46] wire _atomics_legal_T_8 = _atomics_legal_T_7 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _atomics_legal_T_10 = {1'h0, _atomics_legal_T_9}; // @[Parameters.scala:137:{31,41}] wire [34:0] _atomics_legal_T_11 = _atomics_legal_T_10 & 35'h8101000; // @[Parameters.scala:137:{41,46}] wire [34:0] _atomics_legal_T_12 = _atomics_legal_T_11; // @[Parameters.scala:137:46] wire _atomics_legal_T_13 = _atomics_legal_T_12 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _atomics_legal_T_15 = {1'h0, _atomics_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [34:0] _atomics_legal_T_16 = _atomics_legal_T_15 & 35'h8000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _atomics_legal_T_17 = _atomics_legal_T_16; // @[Parameters.scala:137:46] wire _atomics_legal_T_18 = _atomics_legal_T_17 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_19 = _atomics_legal_T_8 | _atomics_legal_T_13; // @[Parameters.scala:685:42] wire _atomics_legal_T_20 = _atomics_legal_T_19 | _atomics_legal_T_18; // @[Parameters.scala:685:42] wire _atomics_legal_T_21 = _atomics_legal_T_20; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_29 = _atomics_legal_T_21; // @[Parameters.scala:684:54, :686:26] wire [34:0] _atomics_legal_T_24 = {1'h0, _atomics_legal_T_23}; // @[Parameters.scala:137:{31,41}] wire [34:0] _atomics_legal_T_25 = _atomics_legal_T_24 & 35'h8110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _atomics_legal_T_26 = _atomics_legal_T_25; // @[Parameters.scala:137:46] wire _atomics_legal_T_27 = _atomics_legal_T_26 == 35'h0; // @[Parameters.scala:137:{46,59}] wire atomics_legal = _atomics_legal_T_29; // @[Parameters.scala:686:26] wire [7:0] _atomics_a_mask_T; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask; // @[Edges.scala:534:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount = _atomics_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_1 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_2 = _atomics_a_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH = {_atomics_a_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1 = &s2_req_size; // @[Misc.scala:206:21] wire atomics_a_mask_sub_sub_size = atomics_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2 = atomics_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit = ~atomics_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2 = atomics_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T = atomics_a_mask_sub_sub_size & atomics_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1 = atomics_a_mask_sub_sub_sub_0_1 | _atomics_a_mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_1 = atomics_a_mask_sub_sub_size & atomics_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1 = atomics_a_mask_sub_sub_sub_0_1 | _atomics_a_mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size = atomics_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit = ~atomics_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2 = atomics_a_mask_sub_sub_0_2 & atomics_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T = atomics_a_mask_sub_size & atomics_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1 = atomics_a_mask_sub_sub_0_1 | _atomics_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2 = atomics_a_mask_sub_sub_0_2 & atomics_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_1 = atomics_a_mask_sub_size & atomics_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1 = atomics_a_mask_sub_sub_0_1 | _atomics_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2 = atomics_a_mask_sub_sub_1_2 & atomics_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_2 = atomics_a_mask_sub_size & atomics_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1 = atomics_a_mask_sub_sub_1_1 | _atomics_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2 = atomics_a_mask_sub_sub_1_2 & atomics_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_3 = atomics_a_mask_sub_size & atomics_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1 = atomics_a_mask_sub_sub_1_1 | _atomics_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size = atomics_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit = ~atomics_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq = atomics_a_mask_sub_0_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T = atomics_a_mask_size & atomics_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc = atomics_a_mask_sub_0_1 | _atomics_a_mask_acc_T; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_1 = atomics_a_mask_sub_0_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_1 = atomics_a_mask_size & atomics_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_1 = atomics_a_mask_sub_0_1 | _atomics_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_2 = atomics_a_mask_sub_1_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_2 = atomics_a_mask_size & atomics_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_2 = atomics_a_mask_sub_1_1 | _atomics_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_3 = atomics_a_mask_sub_1_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_3 = atomics_a_mask_size & atomics_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_3 = atomics_a_mask_sub_1_1 | _atomics_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_4 = atomics_a_mask_sub_2_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_4 = atomics_a_mask_size & atomics_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_4 = atomics_a_mask_sub_2_1 | _atomics_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_5 = atomics_a_mask_sub_2_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_5 = atomics_a_mask_size & atomics_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_5 = atomics_a_mask_sub_2_1 | _atomics_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_6 = atomics_a_mask_sub_3_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_6 = atomics_a_mask_size & atomics_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_6 = atomics_a_mask_sub_3_1 | _atomics_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_7 = atomics_a_mask_sub_3_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_7 = atomics_a_mask_size & atomics_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_7 = atomics_a_mask_sub_3_1 | _atomics_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo = {atomics_a_mask_acc_1, atomics_a_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi = {atomics_a_mask_acc_3, atomics_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo = {atomics_a_mask_lo_hi, atomics_a_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo = {atomics_a_mask_acc_5, atomics_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi = {atomics_a_mask_acc_7, atomics_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi = {atomics_a_mask_hi_hi, atomics_a_mask_hi_lo}; // @[Misc.scala:222:10] assign _atomics_a_mask_T = {atomics_a_mask_hi, atomics_a_mask_lo}; // @[Misc.scala:222:10] assign atomics_a_mask = _atomics_a_mask_T; // @[Misc.scala:222:10] wire [34:0] _atomics_legal_T_35 = {1'h0, _atomics_legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [34:0] _atomics_legal_T_36 = _atomics_legal_T_35 & 35'h8110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _atomics_legal_T_37 = _atomics_legal_T_36; // @[Parameters.scala:137:46] wire _atomics_legal_T_38 = _atomics_legal_T_37 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _atomics_legal_T_40 = {1'h0, _atomics_legal_T_39}; // @[Parameters.scala:137:{31,41}] wire [34:0] _atomics_legal_T_41 = _atomics_legal_T_40 & 35'h8101000; // @[Parameters.scala:137:{41,46}] wire [34:0] _atomics_legal_T_42 = _atomics_legal_T_41; // @[Parameters.scala:137:46] wire _atomics_legal_T_43 = _atomics_legal_T_42 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _atomics_legal_T_45 = {1'h0, _atomics_legal_T_44}; // @[Parameters.scala:137:{31,41}] wire [34:0] _atomics_legal_T_46 = _atomics_legal_T_45 & 35'h8000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _atomics_legal_T_47 = _atomics_legal_T_46; // @[Parameters.scala:137:46] wire _atomics_legal_T_48 = _atomics_legal_T_47 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_49 = _atomics_legal_T_38 | _atomics_legal_T_43; // @[Parameters.scala:685:42] wire _atomics_legal_T_50 = _atomics_legal_T_49 | _atomics_legal_T_48; // @[Parameters.scala:685:42] wire _atomics_legal_T_51 = _atomics_legal_T_50; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_59 = _atomics_legal_T_51; // @[Parameters.scala:684:54, :686:26] wire [34:0] _atomics_legal_T_54 = {1'h0, _atomics_legal_T_53}; // @[Parameters.scala:137:{31,41}] wire [34:0] _atomics_legal_T_55 = _atomics_legal_T_54 & 35'h8110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _atomics_legal_T_56 = _atomics_legal_T_55; // @[Parameters.scala:137:46] wire _atomics_legal_T_57 = _atomics_legal_T_56 == 35'h0; // @[Parameters.scala:137:{46,59}] wire atomics_legal_1 = _atomics_legal_T_59; // @[Parameters.scala:686:26] wire [7:0] _atomics_a_mask_T_1; // @[Misc.scala:222:10] wire [7:0] atomics_a_1_mask; // @[Edges.scala:534:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_1 = _atomics_a_mask_sizeOH_T_3[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_4 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_1; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_5 = _atomics_a_mask_sizeOH_T_4[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH_1 = {_atomics_a_mask_sizeOH_T_5[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1_1 = &s2_req_size; // @[Misc.scala:206:21] wire atomics_a_mask_sub_sub_size_1 = atomics_a_mask_sizeOH_1[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2_1 = atomics_a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit_1 = ~atomics_a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_1 = atomics_a_mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_2 = atomics_a_mask_sub_sub_size_1 & atomics_a_mask_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_1 = atomics_a_mask_sub_sub_sub_0_1_1 | _atomics_a_mask_sub_sub_acc_T_2; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_3 = atomics_a_mask_sub_sub_size_1 & atomics_a_mask_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_1 = atomics_a_mask_sub_sub_sub_0_1_1 | _atomics_a_mask_sub_sub_acc_T_3; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size_1 = atomics_a_mask_sizeOH_1[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_1 = ~atomics_a_mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_1 = atomics_a_mask_sub_sub_0_2_1 & atomics_a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_4 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_1 = atomics_a_mask_sub_sub_0_1_1 | _atomics_a_mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_1 = atomics_a_mask_sub_sub_0_2_1 & atomics_a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_5 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_1 = atomics_a_mask_sub_sub_0_1_1 | _atomics_a_mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_1 = atomics_a_mask_sub_sub_1_2_1 & atomics_a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_6 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_1 = atomics_a_mask_sub_sub_1_1_1 | _atomics_a_mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_1 = atomics_a_mask_sub_sub_1_2_1 & atomics_a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_7 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_1 = atomics_a_mask_sub_sub_1_1_1 | _atomics_a_mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_1 = atomics_a_mask_sizeOH_1[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_1 = ~atomics_a_mask_bit_1; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_8 = atomics_a_mask_sub_0_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_8 = atomics_a_mask_size_1 & atomics_a_mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_8 = atomics_a_mask_sub_0_1_1 | _atomics_a_mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_9 = atomics_a_mask_sub_0_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_9 = atomics_a_mask_size_1 & atomics_a_mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_9 = atomics_a_mask_sub_0_1_1 | _atomics_a_mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_10 = atomics_a_mask_sub_1_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_10 = atomics_a_mask_size_1 & atomics_a_mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_10 = atomics_a_mask_sub_1_1_1 | _atomics_a_mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_11 = atomics_a_mask_sub_1_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_11 = atomics_a_mask_size_1 & atomics_a_mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_11 = atomics_a_mask_sub_1_1_1 | _atomics_a_mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_12 = atomics_a_mask_sub_2_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_12 = atomics_a_mask_size_1 & atomics_a_mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_12 = atomics_a_mask_sub_2_1_1 | _atomics_a_mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_13 = atomics_a_mask_sub_2_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_13 = atomics_a_mask_size_1 & atomics_a_mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_13 = atomics_a_mask_sub_2_1_1 | _atomics_a_mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_14 = atomics_a_mask_sub_3_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_14 = atomics_a_mask_size_1 & atomics_a_mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_14 = atomics_a_mask_sub_3_1_1 | _atomics_a_mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_15 = atomics_a_mask_sub_3_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_15 = atomics_a_mask_size_1 & atomics_a_mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_15 = atomics_a_mask_sub_3_1_1 | _atomics_a_mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_1 = {atomics_a_mask_acc_9, atomics_a_mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_1 = {atomics_a_mask_acc_11, atomics_a_mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_1 = {atomics_a_mask_lo_hi_1, atomics_a_mask_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_1 = {atomics_a_mask_acc_13, atomics_a_mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_1 = {atomics_a_mask_acc_15, atomics_a_mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_1 = {atomics_a_mask_hi_hi_1, atomics_a_mask_hi_lo_1}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_1 = {atomics_a_mask_hi_1, atomics_a_mask_lo_1}; // @[Misc.scala:222:10] assign atomics_a_1_mask = _atomics_a_mask_T_1; // @[Misc.scala:222:10] wire [34:0] _atomics_legal_T_65 = {1'h0, _atomics_legal_T_64}; // @[Parameters.scala:137:{31,41}] wire [34:0] _atomics_legal_T_66 = _atomics_legal_T_65 & 35'h8110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _atomics_legal_T_67 = _atomics_legal_T_66; // @[Parameters.scala:137:46] wire _atomics_legal_T_68 = _atomics_legal_T_67 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _atomics_legal_T_70 = {1'h0, _atomics_legal_T_69}; // @[Parameters.scala:137:{31,41}] wire [34:0] _atomics_legal_T_71 = _atomics_legal_T_70 & 35'h8101000; // @[Parameters.scala:137:{41,46}] wire [34:0] _atomics_legal_T_72 = _atomics_legal_T_71; // @[Parameters.scala:137:46] wire _atomics_legal_T_73 = _atomics_legal_T_72 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _atomics_legal_T_75 = {1'h0, _atomics_legal_T_74}; // @[Parameters.scala:137:{31,41}] wire [34:0] _atomics_legal_T_76 = _atomics_legal_T_75 & 35'h8000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _atomics_legal_T_77 = _atomics_legal_T_76; // @[Parameters.scala:137:46] wire _atomics_legal_T_78 = _atomics_legal_T_77 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_79 = _atomics_legal_T_68 | _atomics_legal_T_73; // @[Parameters.scala:685:42] wire _atomics_legal_T_80 = _atomics_legal_T_79 | _atomics_legal_T_78; // @[Parameters.scala:685:42] wire _atomics_legal_T_81 = _atomics_legal_T_80; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_89 = _atomics_legal_T_81; // @[Parameters.scala:684:54, :686:26] wire [34:0] _atomics_legal_T_84 = {1'h0, _atomics_legal_T_83}; // @[Parameters.scala:137:{31,41}] wire [34:0] _atomics_legal_T_85 = _atomics_legal_T_84 & 35'h8110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _atomics_legal_T_86 = _atomics_legal_T_85; // @[Parameters.scala:137:46] wire _atomics_legal_T_87 = _atomics_legal_T_86 == 35'h0; // @[Parameters.scala:137:{46,59}] wire atomics_legal_2 = _atomics_legal_T_89; // @[Parameters.scala:686:26] wire [7:0] _atomics_a_mask_T_2; // @[Misc.scala:222:10] wire [7:0] atomics_a_2_mask; // @[Edges.scala:534:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_2 = _atomics_a_mask_sizeOH_T_6[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_7 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_2; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_8 = _atomics_a_mask_sizeOH_T_7[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH_2 = {_atomics_a_mask_sizeOH_T_8[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1_2 = &s2_req_size; // @[Misc.scala:206:21] wire atomics_a_mask_sub_sub_size_2 = atomics_a_mask_sizeOH_2[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2_2 = atomics_a_mask_sub_sub_bit_2; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit_2 = ~atomics_a_mask_sub_sub_bit_2; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_2 = atomics_a_mask_sub_sub_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_4 = atomics_a_mask_sub_sub_size_2 & atomics_a_mask_sub_sub_0_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_2 = atomics_a_mask_sub_sub_sub_0_1_2 | _atomics_a_mask_sub_sub_acc_T_4; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_5 = atomics_a_mask_sub_sub_size_2 & atomics_a_mask_sub_sub_1_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_2 = atomics_a_mask_sub_sub_sub_0_1_2 | _atomics_a_mask_sub_sub_acc_T_5; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size_2 = atomics_a_mask_sizeOH_2[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_2 = ~atomics_a_mask_sub_bit_2; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_2 = atomics_a_mask_sub_sub_0_2_2 & atomics_a_mask_sub_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_8 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_0_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_2 = atomics_a_mask_sub_sub_0_1_2 | _atomics_a_mask_sub_acc_T_8; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_2 = atomics_a_mask_sub_sub_0_2_2 & atomics_a_mask_sub_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_9 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_1_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_2 = atomics_a_mask_sub_sub_0_1_2 | _atomics_a_mask_sub_acc_T_9; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_2 = atomics_a_mask_sub_sub_1_2_2 & atomics_a_mask_sub_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_10 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_2_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_2 = atomics_a_mask_sub_sub_1_1_2 | _atomics_a_mask_sub_acc_T_10; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_2 = atomics_a_mask_sub_sub_1_2_2 & atomics_a_mask_sub_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_11 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_3_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_2 = atomics_a_mask_sub_sub_1_1_2 | _atomics_a_mask_sub_acc_T_11; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_2 = atomics_a_mask_sizeOH_2[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_2 = ~atomics_a_mask_bit_2; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_16 = atomics_a_mask_sub_0_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_16 = atomics_a_mask_size_2 & atomics_a_mask_eq_16; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_16 = atomics_a_mask_sub_0_1_2 | _atomics_a_mask_acc_T_16; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_17 = atomics_a_mask_sub_0_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_17 = atomics_a_mask_size_2 & atomics_a_mask_eq_17; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_17 = atomics_a_mask_sub_0_1_2 | _atomics_a_mask_acc_T_17; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_18 = atomics_a_mask_sub_1_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_18 = atomics_a_mask_size_2 & atomics_a_mask_eq_18; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_18 = atomics_a_mask_sub_1_1_2 | _atomics_a_mask_acc_T_18; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_19 = atomics_a_mask_sub_1_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_19 = atomics_a_mask_size_2 & atomics_a_mask_eq_19; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_19 = atomics_a_mask_sub_1_1_2 | _atomics_a_mask_acc_T_19; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_20 = atomics_a_mask_sub_2_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_20 = atomics_a_mask_size_2 & atomics_a_mask_eq_20; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_20 = atomics_a_mask_sub_2_1_2 | _atomics_a_mask_acc_T_20; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_21 = atomics_a_mask_sub_2_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_21 = atomics_a_mask_size_2 & atomics_a_mask_eq_21; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_21 = atomics_a_mask_sub_2_1_2 | _atomics_a_mask_acc_T_21; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_22 = atomics_a_mask_sub_3_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_22 = atomics_a_mask_size_2 & atomics_a_mask_eq_22; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_22 = atomics_a_mask_sub_3_1_2 | _atomics_a_mask_acc_T_22; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_23 = atomics_a_mask_sub_3_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_23 = atomics_a_mask_size_2 & atomics_a_mask_eq_23; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_23 = atomics_a_mask_sub_3_1_2 | _atomics_a_mask_acc_T_23; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_2 = {atomics_a_mask_acc_17, atomics_a_mask_acc_16}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_2 = {atomics_a_mask_acc_19, atomics_a_mask_acc_18}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_2 = {atomics_a_mask_lo_hi_2, atomics_a_mask_lo_lo_2}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_2 = {atomics_a_mask_acc_21, atomics_a_mask_acc_20}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_2 = {atomics_a_mask_acc_23, atomics_a_mask_acc_22}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_2 = {atomics_a_mask_hi_hi_2, atomics_a_mask_hi_lo_2}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_2 = {atomics_a_mask_hi_2, atomics_a_mask_lo_2}; // @[Misc.scala:222:10] assign atomics_a_2_mask = _atomics_a_mask_T_2; // @[Misc.scala:222:10] wire [34:0] _atomics_legal_T_95 = {1'h0, _atomics_legal_T_94}; // @[Parameters.scala:137:{31,41}] wire [34:0] _atomics_legal_T_96 = _atomics_legal_T_95 & 35'h8110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _atomics_legal_T_97 = _atomics_legal_T_96; // @[Parameters.scala:137:46] wire _atomics_legal_T_98 = _atomics_legal_T_97 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _atomics_legal_T_100 = {1'h0, _atomics_legal_T_99}; // @[Parameters.scala:137:{31,41}] wire [34:0] _atomics_legal_T_101 = _atomics_legal_T_100 & 35'h8101000; // @[Parameters.scala:137:{41,46}] wire [34:0] _atomics_legal_T_102 = _atomics_legal_T_101; // @[Parameters.scala:137:46] wire _atomics_legal_T_103 = _atomics_legal_T_102 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _atomics_legal_T_105 = {1'h0, _atomics_legal_T_104}; // @[Parameters.scala:137:{31,41}] wire [34:0] _atomics_legal_T_106 = _atomics_legal_T_105 & 35'h8000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _atomics_legal_T_107 = _atomics_legal_T_106; // @[Parameters.scala:137:46] wire _atomics_legal_T_108 = _atomics_legal_T_107 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_109 = _atomics_legal_T_98 | _atomics_legal_T_103; // @[Parameters.scala:685:42] wire _atomics_legal_T_110 = _atomics_legal_T_109 | _atomics_legal_T_108; // @[Parameters.scala:685:42] wire _atomics_legal_T_111 = _atomics_legal_T_110; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_119 = _atomics_legal_T_111; // @[Parameters.scala:684:54, :686:26] wire [34:0] _atomics_legal_T_114 = {1'h0, _atomics_legal_T_113}; // @[Parameters.scala:137:{31,41}] wire [34:0] _atomics_legal_T_115 = _atomics_legal_T_114 & 35'h8110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _atomics_legal_T_116 = _atomics_legal_T_115; // @[Parameters.scala:137:46] wire _atomics_legal_T_117 = _atomics_legal_T_116 == 35'h0; // @[Parameters.scala:137:{46,59}] wire atomics_legal_3 = _atomics_legal_T_119; // @[Parameters.scala:686:26] wire [7:0] _atomics_a_mask_T_3; // @[Misc.scala:222:10] wire [7:0] atomics_a_3_mask; // @[Edges.scala:534:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_3 = _atomics_a_mask_sizeOH_T_9[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_10 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_3; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_11 = _atomics_a_mask_sizeOH_T_10[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH_3 = {_atomics_a_mask_sizeOH_T_11[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1_3 = &s2_req_size; // @[Misc.scala:206:21] wire atomics_a_mask_sub_sub_size_3 = atomics_a_mask_sizeOH_3[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2_3 = atomics_a_mask_sub_sub_bit_3; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit_3 = ~atomics_a_mask_sub_sub_bit_3; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_3 = atomics_a_mask_sub_sub_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_6 = atomics_a_mask_sub_sub_size_3 & atomics_a_mask_sub_sub_0_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_3 = atomics_a_mask_sub_sub_sub_0_1_3 | _atomics_a_mask_sub_sub_acc_T_6; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_7 = atomics_a_mask_sub_sub_size_3 & atomics_a_mask_sub_sub_1_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_3 = atomics_a_mask_sub_sub_sub_0_1_3 | _atomics_a_mask_sub_sub_acc_T_7; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size_3 = atomics_a_mask_sizeOH_3[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_3 = ~atomics_a_mask_sub_bit_3; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_3 = atomics_a_mask_sub_sub_0_2_3 & atomics_a_mask_sub_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_12 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_0_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_3 = atomics_a_mask_sub_sub_0_1_3 | _atomics_a_mask_sub_acc_T_12; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_3 = atomics_a_mask_sub_sub_0_2_3 & atomics_a_mask_sub_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_13 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_1_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_3 = atomics_a_mask_sub_sub_0_1_3 | _atomics_a_mask_sub_acc_T_13; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_3 = atomics_a_mask_sub_sub_1_2_3 & atomics_a_mask_sub_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_14 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_2_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_3 = atomics_a_mask_sub_sub_1_1_3 | _atomics_a_mask_sub_acc_T_14; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_3 = atomics_a_mask_sub_sub_1_2_3 & atomics_a_mask_sub_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_15 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_3_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_3 = atomics_a_mask_sub_sub_1_1_3 | _atomics_a_mask_sub_acc_T_15; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_3 = atomics_a_mask_sizeOH_3[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_3 = ~atomics_a_mask_bit_3; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_24 = atomics_a_mask_sub_0_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_24 = atomics_a_mask_size_3 & atomics_a_mask_eq_24; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_24 = atomics_a_mask_sub_0_1_3 | _atomics_a_mask_acc_T_24; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_25 = atomics_a_mask_sub_0_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_25 = atomics_a_mask_size_3 & atomics_a_mask_eq_25; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_25 = atomics_a_mask_sub_0_1_3 | _atomics_a_mask_acc_T_25; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_26 = atomics_a_mask_sub_1_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_26 = atomics_a_mask_size_3 & atomics_a_mask_eq_26; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_26 = atomics_a_mask_sub_1_1_3 | _atomics_a_mask_acc_T_26; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_27 = atomics_a_mask_sub_1_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_27 = atomics_a_mask_size_3 & atomics_a_mask_eq_27; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_27 = atomics_a_mask_sub_1_1_3 | _atomics_a_mask_acc_T_27; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_28 = atomics_a_mask_sub_2_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_28 = atomics_a_mask_size_3 & atomics_a_mask_eq_28; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_28 = atomics_a_mask_sub_2_1_3 | _atomics_a_mask_acc_T_28; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_29 = atomics_a_mask_sub_2_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_29 = atomics_a_mask_size_3 & atomics_a_mask_eq_29; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_29 = atomics_a_mask_sub_2_1_3 | _atomics_a_mask_acc_T_29; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_30 = atomics_a_mask_sub_3_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_30 = atomics_a_mask_size_3 & atomics_a_mask_eq_30; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_30 = atomics_a_mask_sub_3_1_3 | _atomics_a_mask_acc_T_30; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_31 = atomics_a_mask_sub_3_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_31 = atomics_a_mask_size_3 & atomics_a_mask_eq_31; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_31 = atomics_a_mask_sub_3_1_3 | _atomics_a_mask_acc_T_31; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_3 = {atomics_a_mask_acc_25, atomics_a_mask_acc_24}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_3 = {atomics_a_mask_acc_27, atomics_a_mask_acc_26}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_3 = {atomics_a_mask_lo_hi_3, atomics_a_mask_lo_lo_3}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_3 = {atomics_a_mask_acc_29, atomics_a_mask_acc_28}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_3 = {atomics_a_mask_acc_31, atomics_a_mask_acc_30}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_3 = {atomics_a_mask_hi_hi_3, atomics_a_mask_hi_lo_3}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_3 = {atomics_a_mask_hi_3, atomics_a_mask_lo_3}; // @[Misc.scala:222:10] assign atomics_a_3_mask = _atomics_a_mask_T_3; // @[Misc.scala:222:10] wire [34:0] _atomics_legal_T_125 = {1'h0, _atomics_legal_T_124}; // @[Parameters.scala:137:{31,41}] wire [34:0] _atomics_legal_T_126 = _atomics_legal_T_125 & 35'h8110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _atomics_legal_T_127 = _atomics_legal_T_126; // @[Parameters.scala:137:46] wire _atomics_legal_T_128 = _atomics_legal_T_127 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _atomics_legal_T_130 = {1'h0, _atomics_legal_T_129}; // @[Parameters.scala:137:{31,41}] wire [34:0] _atomics_legal_T_131 = _atomics_legal_T_130 & 35'h8101000; // @[Parameters.scala:137:{41,46}] wire [34:0] _atomics_legal_T_132 = _atomics_legal_T_131; // @[Parameters.scala:137:46] wire _atomics_legal_T_133 = _atomics_legal_T_132 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _atomics_legal_T_135 = {1'h0, _atomics_legal_T_134}; // @[Parameters.scala:137:{31,41}] wire [34:0] _atomics_legal_T_136 = _atomics_legal_T_135 & 35'h8000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _atomics_legal_T_137 = _atomics_legal_T_136; // @[Parameters.scala:137:46] wire _atomics_legal_T_138 = _atomics_legal_T_137 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_139 = _atomics_legal_T_128 | _atomics_legal_T_133; // @[Parameters.scala:685:42] wire _atomics_legal_T_140 = _atomics_legal_T_139 | _atomics_legal_T_138; // @[Parameters.scala:685:42] wire _atomics_legal_T_141 = _atomics_legal_T_140; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_149 = _atomics_legal_T_141; // @[Parameters.scala:684:54, :686:26] wire [34:0] _atomics_legal_T_144 = {1'h0, _atomics_legal_T_143}; // @[Parameters.scala:137:{31,41}] wire [34:0] _atomics_legal_T_145 = _atomics_legal_T_144 & 35'h8110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _atomics_legal_T_146 = _atomics_legal_T_145; // @[Parameters.scala:137:46] wire _atomics_legal_T_147 = _atomics_legal_T_146 == 35'h0; // @[Parameters.scala:137:{46,59}] wire atomics_legal_4 = _atomics_legal_T_149; // @[Parameters.scala:686:26] wire [7:0] _atomics_a_mask_T_4; // @[Misc.scala:222:10] wire [7:0] atomics_a_4_mask; // @[Edges.scala:517:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_4 = _atomics_a_mask_sizeOH_T_12[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_13 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_4; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_14 = _atomics_a_mask_sizeOH_T_13[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH_4 = {_atomics_a_mask_sizeOH_T_14[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1_4 = &s2_req_size; // @[Misc.scala:206:21] wire atomics_a_mask_sub_sub_size_4 = atomics_a_mask_sizeOH_4[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2_4 = atomics_a_mask_sub_sub_bit_4; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit_4 = ~atomics_a_mask_sub_sub_bit_4; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_4 = atomics_a_mask_sub_sub_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_8 = atomics_a_mask_sub_sub_size_4 & atomics_a_mask_sub_sub_0_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_4 = atomics_a_mask_sub_sub_sub_0_1_4 | _atomics_a_mask_sub_sub_acc_T_8; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_9 = atomics_a_mask_sub_sub_size_4 & atomics_a_mask_sub_sub_1_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_4 = atomics_a_mask_sub_sub_sub_0_1_4 | _atomics_a_mask_sub_sub_acc_T_9; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size_4 = atomics_a_mask_sizeOH_4[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_4 = ~atomics_a_mask_sub_bit_4; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_4 = atomics_a_mask_sub_sub_0_2_4 & atomics_a_mask_sub_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_16 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_0_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_4 = atomics_a_mask_sub_sub_0_1_4 | _atomics_a_mask_sub_acc_T_16; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_4 = atomics_a_mask_sub_sub_0_2_4 & atomics_a_mask_sub_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_17 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_1_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_4 = atomics_a_mask_sub_sub_0_1_4 | _atomics_a_mask_sub_acc_T_17; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_4 = atomics_a_mask_sub_sub_1_2_4 & atomics_a_mask_sub_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_18 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_2_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_4 = atomics_a_mask_sub_sub_1_1_4 | _atomics_a_mask_sub_acc_T_18; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_4 = atomics_a_mask_sub_sub_1_2_4 & atomics_a_mask_sub_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_19 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_3_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_4 = atomics_a_mask_sub_sub_1_1_4 | _atomics_a_mask_sub_acc_T_19; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_4 = atomics_a_mask_sizeOH_4[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_4 = ~atomics_a_mask_bit_4; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_32 = atomics_a_mask_sub_0_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_32 = atomics_a_mask_size_4 & atomics_a_mask_eq_32; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_32 = atomics_a_mask_sub_0_1_4 | _atomics_a_mask_acc_T_32; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_33 = atomics_a_mask_sub_0_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_33 = atomics_a_mask_size_4 & atomics_a_mask_eq_33; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_33 = atomics_a_mask_sub_0_1_4 | _atomics_a_mask_acc_T_33; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_34 = atomics_a_mask_sub_1_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_34 = atomics_a_mask_size_4 & atomics_a_mask_eq_34; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_34 = atomics_a_mask_sub_1_1_4 | _atomics_a_mask_acc_T_34; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_35 = atomics_a_mask_sub_1_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_35 = atomics_a_mask_size_4 & atomics_a_mask_eq_35; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_35 = atomics_a_mask_sub_1_1_4 | _atomics_a_mask_acc_T_35; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_36 = atomics_a_mask_sub_2_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_36 = atomics_a_mask_size_4 & atomics_a_mask_eq_36; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_36 = atomics_a_mask_sub_2_1_4 | _atomics_a_mask_acc_T_36; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_37 = atomics_a_mask_sub_2_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_37 = atomics_a_mask_size_4 & atomics_a_mask_eq_37; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_37 = atomics_a_mask_sub_2_1_4 | _atomics_a_mask_acc_T_37; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_38 = atomics_a_mask_sub_3_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_38 = atomics_a_mask_size_4 & atomics_a_mask_eq_38; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_38 = atomics_a_mask_sub_3_1_4 | _atomics_a_mask_acc_T_38; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_39 = atomics_a_mask_sub_3_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_39 = atomics_a_mask_size_4 & atomics_a_mask_eq_39; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_39 = atomics_a_mask_sub_3_1_4 | _atomics_a_mask_acc_T_39; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_4 = {atomics_a_mask_acc_33, atomics_a_mask_acc_32}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_4 = {atomics_a_mask_acc_35, atomics_a_mask_acc_34}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_4 = {atomics_a_mask_lo_hi_4, atomics_a_mask_lo_lo_4}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_4 = {atomics_a_mask_acc_37, atomics_a_mask_acc_36}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_4 = {atomics_a_mask_acc_39, atomics_a_mask_acc_38}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_4 = {atomics_a_mask_hi_hi_4, atomics_a_mask_hi_lo_4}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_4 = {atomics_a_mask_hi_4, atomics_a_mask_lo_4}; // @[Misc.scala:222:10] assign atomics_a_4_mask = _atomics_a_mask_T_4; // @[Misc.scala:222:10] wire [34:0] _atomics_legal_T_155 = {1'h0, _atomics_legal_T_154}; // @[Parameters.scala:137:{31,41}] wire [34:0] _atomics_legal_T_156 = _atomics_legal_T_155 & 35'h8110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _atomics_legal_T_157 = _atomics_legal_T_156; // @[Parameters.scala:137:46] wire _atomics_legal_T_158 = _atomics_legal_T_157 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _atomics_legal_T_160 = {1'h0, _atomics_legal_T_159}; // @[Parameters.scala:137:{31,41}] wire [34:0] _atomics_legal_T_161 = _atomics_legal_T_160 & 35'h8101000; // @[Parameters.scala:137:{41,46}] wire [34:0] _atomics_legal_T_162 = _atomics_legal_T_161; // @[Parameters.scala:137:46] wire _atomics_legal_T_163 = _atomics_legal_T_162 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _atomics_legal_T_165 = {1'h0, _atomics_legal_T_164}; // @[Parameters.scala:137:{31,41}] wire [34:0] _atomics_legal_T_166 = _atomics_legal_T_165 & 35'h8000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _atomics_legal_T_167 = _atomics_legal_T_166; // @[Parameters.scala:137:46] wire _atomics_legal_T_168 = _atomics_legal_T_167 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_169 = _atomics_legal_T_158 | _atomics_legal_T_163; // @[Parameters.scala:685:42] wire _atomics_legal_T_170 = _atomics_legal_T_169 | _atomics_legal_T_168; // @[Parameters.scala:685:42] wire _atomics_legal_T_171 = _atomics_legal_T_170; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_179 = _atomics_legal_T_171; // @[Parameters.scala:684:54, :686:26] wire [34:0] _atomics_legal_T_174 = {1'h0, _atomics_legal_T_173}; // @[Parameters.scala:137:{31,41}] wire [34:0] _atomics_legal_T_175 = _atomics_legal_T_174 & 35'h8110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _atomics_legal_T_176 = _atomics_legal_T_175; // @[Parameters.scala:137:46] wire _atomics_legal_T_177 = _atomics_legal_T_176 == 35'h0; // @[Parameters.scala:137:{46,59}] wire atomics_legal_5 = _atomics_legal_T_179; // @[Parameters.scala:686:26] wire [7:0] _atomics_a_mask_T_5; // @[Misc.scala:222:10] wire [7:0] atomics_a_5_mask; // @[Edges.scala:517:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_5 = _atomics_a_mask_sizeOH_T_15[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_16 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_5; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_17 = _atomics_a_mask_sizeOH_T_16[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH_5 = {_atomics_a_mask_sizeOH_T_17[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1_5 = &s2_req_size; // @[Misc.scala:206:21] wire atomics_a_mask_sub_sub_size_5 = atomics_a_mask_sizeOH_5[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2_5 = atomics_a_mask_sub_sub_bit_5; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit_5 = ~atomics_a_mask_sub_sub_bit_5; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_5 = atomics_a_mask_sub_sub_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_10 = atomics_a_mask_sub_sub_size_5 & atomics_a_mask_sub_sub_0_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_5 = atomics_a_mask_sub_sub_sub_0_1_5 | _atomics_a_mask_sub_sub_acc_T_10; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_11 = atomics_a_mask_sub_sub_size_5 & atomics_a_mask_sub_sub_1_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_5 = atomics_a_mask_sub_sub_sub_0_1_5 | _atomics_a_mask_sub_sub_acc_T_11; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size_5 = atomics_a_mask_sizeOH_5[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_5 = ~atomics_a_mask_sub_bit_5; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_5 = atomics_a_mask_sub_sub_0_2_5 & atomics_a_mask_sub_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_20 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_0_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_5 = atomics_a_mask_sub_sub_0_1_5 | _atomics_a_mask_sub_acc_T_20; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_5 = atomics_a_mask_sub_sub_0_2_5 & atomics_a_mask_sub_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_21 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_1_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_5 = atomics_a_mask_sub_sub_0_1_5 | _atomics_a_mask_sub_acc_T_21; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_5 = atomics_a_mask_sub_sub_1_2_5 & atomics_a_mask_sub_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_22 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_2_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_5 = atomics_a_mask_sub_sub_1_1_5 | _atomics_a_mask_sub_acc_T_22; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_5 = atomics_a_mask_sub_sub_1_2_5 & atomics_a_mask_sub_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_23 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_3_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_5 = atomics_a_mask_sub_sub_1_1_5 | _atomics_a_mask_sub_acc_T_23; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_5 = atomics_a_mask_sizeOH_5[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_5 = ~atomics_a_mask_bit_5; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_40 = atomics_a_mask_sub_0_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_40 = atomics_a_mask_size_5 & atomics_a_mask_eq_40; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_40 = atomics_a_mask_sub_0_1_5 | _atomics_a_mask_acc_T_40; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_41 = atomics_a_mask_sub_0_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_41 = atomics_a_mask_size_5 & atomics_a_mask_eq_41; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_41 = atomics_a_mask_sub_0_1_5 | _atomics_a_mask_acc_T_41; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_42 = atomics_a_mask_sub_1_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_42 = atomics_a_mask_size_5 & atomics_a_mask_eq_42; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_42 = atomics_a_mask_sub_1_1_5 | _atomics_a_mask_acc_T_42; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_43 = atomics_a_mask_sub_1_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_43 = atomics_a_mask_size_5 & atomics_a_mask_eq_43; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_43 = atomics_a_mask_sub_1_1_5 | _atomics_a_mask_acc_T_43; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_44 = atomics_a_mask_sub_2_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_44 = atomics_a_mask_size_5 & atomics_a_mask_eq_44; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_44 = atomics_a_mask_sub_2_1_5 | _atomics_a_mask_acc_T_44; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_45 = atomics_a_mask_sub_2_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_45 = atomics_a_mask_size_5 & atomics_a_mask_eq_45; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_45 = atomics_a_mask_sub_2_1_5 | _atomics_a_mask_acc_T_45; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_46 = atomics_a_mask_sub_3_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_46 = atomics_a_mask_size_5 & atomics_a_mask_eq_46; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_46 = atomics_a_mask_sub_3_1_5 | _atomics_a_mask_acc_T_46; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_47 = atomics_a_mask_sub_3_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_47 = atomics_a_mask_size_5 & atomics_a_mask_eq_47; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_47 = atomics_a_mask_sub_3_1_5 | _atomics_a_mask_acc_T_47; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_5 = {atomics_a_mask_acc_41, atomics_a_mask_acc_40}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_5 = {atomics_a_mask_acc_43, atomics_a_mask_acc_42}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_5 = {atomics_a_mask_lo_hi_5, atomics_a_mask_lo_lo_5}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_5 = {atomics_a_mask_acc_45, atomics_a_mask_acc_44}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_5 = {atomics_a_mask_acc_47, atomics_a_mask_acc_46}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_5 = {atomics_a_mask_hi_hi_5, atomics_a_mask_hi_lo_5}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_5 = {atomics_a_mask_hi_5, atomics_a_mask_lo_5}; // @[Misc.scala:222:10] assign atomics_a_5_mask = _atomics_a_mask_T_5; // @[Misc.scala:222:10] wire [34:0] _atomics_legal_T_185 = {1'h0, _atomics_legal_T_184}; // @[Parameters.scala:137:{31,41}] wire [34:0] _atomics_legal_T_186 = _atomics_legal_T_185 & 35'h8110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _atomics_legal_T_187 = _atomics_legal_T_186; // @[Parameters.scala:137:46] wire _atomics_legal_T_188 = _atomics_legal_T_187 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _atomics_legal_T_190 = {1'h0, _atomics_legal_T_189}; // @[Parameters.scala:137:{31,41}] wire [34:0] _atomics_legal_T_191 = _atomics_legal_T_190 & 35'h8101000; // @[Parameters.scala:137:{41,46}] wire [34:0] _atomics_legal_T_192 = _atomics_legal_T_191; // @[Parameters.scala:137:46] wire _atomics_legal_T_193 = _atomics_legal_T_192 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _atomics_legal_T_195 = {1'h0, _atomics_legal_T_194}; // @[Parameters.scala:137:{31,41}] wire [34:0] _atomics_legal_T_196 = _atomics_legal_T_195 & 35'h8000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _atomics_legal_T_197 = _atomics_legal_T_196; // @[Parameters.scala:137:46] wire _atomics_legal_T_198 = _atomics_legal_T_197 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_199 = _atomics_legal_T_188 | _atomics_legal_T_193; // @[Parameters.scala:685:42] wire _atomics_legal_T_200 = _atomics_legal_T_199 | _atomics_legal_T_198; // @[Parameters.scala:685:42] wire _atomics_legal_T_201 = _atomics_legal_T_200; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_209 = _atomics_legal_T_201; // @[Parameters.scala:684:54, :686:26] wire [34:0] _atomics_legal_T_204 = {1'h0, _atomics_legal_T_203}; // @[Parameters.scala:137:{31,41}] wire [34:0] _atomics_legal_T_205 = _atomics_legal_T_204 & 35'h8110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _atomics_legal_T_206 = _atomics_legal_T_205; // @[Parameters.scala:137:46] wire _atomics_legal_T_207 = _atomics_legal_T_206 == 35'h0; // @[Parameters.scala:137:{46,59}] wire atomics_legal_6 = _atomics_legal_T_209; // @[Parameters.scala:686:26] wire [7:0] _atomics_a_mask_T_6; // @[Misc.scala:222:10] wire [7:0] atomics_a_6_mask; // @[Edges.scala:517:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_6 = _atomics_a_mask_sizeOH_T_18[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_19 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_6; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_20 = _atomics_a_mask_sizeOH_T_19[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH_6 = {_atomics_a_mask_sizeOH_T_20[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1_6 = &s2_req_size; // @[Misc.scala:206:21] wire atomics_a_mask_sub_sub_size_6 = atomics_a_mask_sizeOH_6[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2_6 = atomics_a_mask_sub_sub_bit_6; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit_6 = ~atomics_a_mask_sub_sub_bit_6; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_6 = atomics_a_mask_sub_sub_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_12 = atomics_a_mask_sub_sub_size_6 & atomics_a_mask_sub_sub_0_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_6 = atomics_a_mask_sub_sub_sub_0_1_6 | _atomics_a_mask_sub_sub_acc_T_12; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_13 = atomics_a_mask_sub_sub_size_6 & atomics_a_mask_sub_sub_1_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_6 = atomics_a_mask_sub_sub_sub_0_1_6 | _atomics_a_mask_sub_sub_acc_T_13; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size_6 = atomics_a_mask_sizeOH_6[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_6 = ~atomics_a_mask_sub_bit_6; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_6 = atomics_a_mask_sub_sub_0_2_6 & atomics_a_mask_sub_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_24 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_0_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_6 = atomics_a_mask_sub_sub_0_1_6 | _atomics_a_mask_sub_acc_T_24; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_6 = atomics_a_mask_sub_sub_0_2_6 & atomics_a_mask_sub_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_25 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_1_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_6 = atomics_a_mask_sub_sub_0_1_6 | _atomics_a_mask_sub_acc_T_25; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_6 = atomics_a_mask_sub_sub_1_2_6 & atomics_a_mask_sub_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_26 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_2_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_6 = atomics_a_mask_sub_sub_1_1_6 | _atomics_a_mask_sub_acc_T_26; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_6 = atomics_a_mask_sub_sub_1_2_6 & atomics_a_mask_sub_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_27 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_3_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_6 = atomics_a_mask_sub_sub_1_1_6 | _atomics_a_mask_sub_acc_T_27; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_6 = atomics_a_mask_sizeOH_6[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_6 = ~atomics_a_mask_bit_6; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_48 = atomics_a_mask_sub_0_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_48 = atomics_a_mask_size_6 & atomics_a_mask_eq_48; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_48 = atomics_a_mask_sub_0_1_6 | _atomics_a_mask_acc_T_48; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_49 = atomics_a_mask_sub_0_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_49 = atomics_a_mask_size_6 & atomics_a_mask_eq_49; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_49 = atomics_a_mask_sub_0_1_6 | _atomics_a_mask_acc_T_49; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_50 = atomics_a_mask_sub_1_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_50 = atomics_a_mask_size_6 & atomics_a_mask_eq_50; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_50 = atomics_a_mask_sub_1_1_6 | _atomics_a_mask_acc_T_50; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_51 = atomics_a_mask_sub_1_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_51 = atomics_a_mask_size_6 & atomics_a_mask_eq_51; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_51 = atomics_a_mask_sub_1_1_6 | _atomics_a_mask_acc_T_51; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_52 = atomics_a_mask_sub_2_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_52 = atomics_a_mask_size_6 & atomics_a_mask_eq_52; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_52 = atomics_a_mask_sub_2_1_6 | _atomics_a_mask_acc_T_52; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_53 = atomics_a_mask_sub_2_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_53 = atomics_a_mask_size_6 & atomics_a_mask_eq_53; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_53 = atomics_a_mask_sub_2_1_6 | _atomics_a_mask_acc_T_53; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_54 = atomics_a_mask_sub_3_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_54 = atomics_a_mask_size_6 & atomics_a_mask_eq_54; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_54 = atomics_a_mask_sub_3_1_6 | _atomics_a_mask_acc_T_54; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_55 = atomics_a_mask_sub_3_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_55 = atomics_a_mask_size_6 & atomics_a_mask_eq_55; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_55 = atomics_a_mask_sub_3_1_6 | _atomics_a_mask_acc_T_55; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_6 = {atomics_a_mask_acc_49, atomics_a_mask_acc_48}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_6 = {atomics_a_mask_acc_51, atomics_a_mask_acc_50}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_6 = {atomics_a_mask_lo_hi_6, atomics_a_mask_lo_lo_6}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_6 = {atomics_a_mask_acc_53, atomics_a_mask_acc_52}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_6 = {atomics_a_mask_acc_55, atomics_a_mask_acc_54}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_6 = {atomics_a_mask_hi_hi_6, atomics_a_mask_hi_lo_6}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_6 = {atomics_a_mask_hi_6, atomics_a_mask_lo_6}; // @[Misc.scala:222:10] assign atomics_a_6_mask = _atomics_a_mask_T_6; // @[Misc.scala:222:10] wire [34:0] _atomics_legal_T_215 = {1'h0, _atomics_legal_T_214}; // @[Parameters.scala:137:{31,41}] wire [34:0] _atomics_legal_T_216 = _atomics_legal_T_215 & 35'h8110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _atomics_legal_T_217 = _atomics_legal_T_216; // @[Parameters.scala:137:46] wire _atomics_legal_T_218 = _atomics_legal_T_217 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _atomics_legal_T_220 = {1'h0, _atomics_legal_T_219}; // @[Parameters.scala:137:{31,41}] wire [34:0] _atomics_legal_T_221 = _atomics_legal_T_220 & 35'h8101000; // @[Parameters.scala:137:{41,46}] wire [34:0] _atomics_legal_T_222 = _atomics_legal_T_221; // @[Parameters.scala:137:46] wire _atomics_legal_T_223 = _atomics_legal_T_222 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _atomics_legal_T_225 = {1'h0, _atomics_legal_T_224}; // @[Parameters.scala:137:{31,41}] wire [34:0] _atomics_legal_T_226 = _atomics_legal_T_225 & 35'h8000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _atomics_legal_T_227 = _atomics_legal_T_226; // @[Parameters.scala:137:46] wire _atomics_legal_T_228 = _atomics_legal_T_227 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_229 = _atomics_legal_T_218 | _atomics_legal_T_223; // @[Parameters.scala:685:42] wire _atomics_legal_T_230 = _atomics_legal_T_229 | _atomics_legal_T_228; // @[Parameters.scala:685:42] wire _atomics_legal_T_231 = _atomics_legal_T_230; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_239 = _atomics_legal_T_231; // @[Parameters.scala:684:54, :686:26] wire [34:0] _atomics_legal_T_234 = {1'h0, _atomics_legal_T_233}; // @[Parameters.scala:137:{31,41}] wire [34:0] _atomics_legal_T_235 = _atomics_legal_T_234 & 35'h8110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _atomics_legal_T_236 = _atomics_legal_T_235; // @[Parameters.scala:137:46] wire _atomics_legal_T_237 = _atomics_legal_T_236 == 35'h0; // @[Parameters.scala:137:{46,59}] wire atomics_legal_7 = _atomics_legal_T_239; // @[Parameters.scala:686:26] wire [7:0] _atomics_a_mask_T_7; // @[Misc.scala:222:10] wire [7:0] atomics_a_7_mask; // @[Edges.scala:517:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_7 = _atomics_a_mask_sizeOH_T_21[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_22 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_7; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_23 = _atomics_a_mask_sizeOH_T_22[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH_7 = {_atomics_a_mask_sizeOH_T_23[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1_7 = &s2_req_size; // @[Misc.scala:206:21] wire atomics_a_mask_sub_sub_size_7 = atomics_a_mask_sizeOH_7[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2_7 = atomics_a_mask_sub_sub_bit_7; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit_7 = ~atomics_a_mask_sub_sub_bit_7; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_7 = atomics_a_mask_sub_sub_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_14 = atomics_a_mask_sub_sub_size_7 & atomics_a_mask_sub_sub_0_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_7 = atomics_a_mask_sub_sub_sub_0_1_7 | _atomics_a_mask_sub_sub_acc_T_14; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_15 = atomics_a_mask_sub_sub_size_7 & atomics_a_mask_sub_sub_1_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_7 = atomics_a_mask_sub_sub_sub_0_1_7 | _atomics_a_mask_sub_sub_acc_T_15; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size_7 = atomics_a_mask_sizeOH_7[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_7 = ~atomics_a_mask_sub_bit_7; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_7 = atomics_a_mask_sub_sub_0_2_7 & atomics_a_mask_sub_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_28 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_0_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_7 = atomics_a_mask_sub_sub_0_1_7 | _atomics_a_mask_sub_acc_T_28; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_7 = atomics_a_mask_sub_sub_0_2_7 & atomics_a_mask_sub_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_29 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_1_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_7 = atomics_a_mask_sub_sub_0_1_7 | _atomics_a_mask_sub_acc_T_29; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_7 = atomics_a_mask_sub_sub_1_2_7 & atomics_a_mask_sub_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_30 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_2_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_7 = atomics_a_mask_sub_sub_1_1_7 | _atomics_a_mask_sub_acc_T_30; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_7 = atomics_a_mask_sub_sub_1_2_7 & atomics_a_mask_sub_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_31 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_3_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_7 = atomics_a_mask_sub_sub_1_1_7 | _atomics_a_mask_sub_acc_T_31; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_7 = atomics_a_mask_sizeOH_7[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_7 = ~atomics_a_mask_bit_7; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_56 = atomics_a_mask_sub_0_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_56 = atomics_a_mask_size_7 & atomics_a_mask_eq_56; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_56 = atomics_a_mask_sub_0_1_7 | _atomics_a_mask_acc_T_56; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_57 = atomics_a_mask_sub_0_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_57 = atomics_a_mask_size_7 & atomics_a_mask_eq_57; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_57 = atomics_a_mask_sub_0_1_7 | _atomics_a_mask_acc_T_57; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_58 = atomics_a_mask_sub_1_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_58 = atomics_a_mask_size_7 & atomics_a_mask_eq_58; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_58 = atomics_a_mask_sub_1_1_7 | _atomics_a_mask_acc_T_58; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_59 = atomics_a_mask_sub_1_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_59 = atomics_a_mask_size_7 & atomics_a_mask_eq_59; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_59 = atomics_a_mask_sub_1_1_7 | _atomics_a_mask_acc_T_59; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_60 = atomics_a_mask_sub_2_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_60 = atomics_a_mask_size_7 & atomics_a_mask_eq_60; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_60 = atomics_a_mask_sub_2_1_7 | _atomics_a_mask_acc_T_60; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_61 = atomics_a_mask_sub_2_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_61 = atomics_a_mask_size_7 & atomics_a_mask_eq_61; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_61 = atomics_a_mask_sub_2_1_7 | _atomics_a_mask_acc_T_61; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_62 = atomics_a_mask_sub_3_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_62 = atomics_a_mask_size_7 & atomics_a_mask_eq_62; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_62 = atomics_a_mask_sub_3_1_7 | _atomics_a_mask_acc_T_62; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_63 = atomics_a_mask_sub_3_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_63 = atomics_a_mask_size_7 & atomics_a_mask_eq_63; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_63 = atomics_a_mask_sub_3_1_7 | _atomics_a_mask_acc_T_63; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_7 = {atomics_a_mask_acc_57, atomics_a_mask_acc_56}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_7 = {atomics_a_mask_acc_59, atomics_a_mask_acc_58}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_7 = {atomics_a_mask_lo_hi_7, atomics_a_mask_lo_lo_7}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_7 = {atomics_a_mask_acc_61, atomics_a_mask_acc_60}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_7 = {atomics_a_mask_acc_63, atomics_a_mask_acc_62}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_7 = {atomics_a_mask_hi_hi_7, atomics_a_mask_hi_lo_7}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_7 = {atomics_a_mask_hi_7, atomics_a_mask_lo_7}; // @[Misc.scala:222:10] assign atomics_a_7_mask = _atomics_a_mask_T_7; // @[Misc.scala:222:10] wire [34:0] _atomics_legal_T_245 = {1'h0, _atomics_legal_T_244}; // @[Parameters.scala:137:{31,41}] wire [34:0] _atomics_legal_T_246 = _atomics_legal_T_245 & 35'h8110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _atomics_legal_T_247 = _atomics_legal_T_246; // @[Parameters.scala:137:46] wire _atomics_legal_T_248 = _atomics_legal_T_247 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _atomics_legal_T_250 = {1'h0, _atomics_legal_T_249}; // @[Parameters.scala:137:{31,41}] wire [34:0] _atomics_legal_T_251 = _atomics_legal_T_250 & 35'h8101000; // @[Parameters.scala:137:{41,46}] wire [34:0] _atomics_legal_T_252 = _atomics_legal_T_251; // @[Parameters.scala:137:46] wire _atomics_legal_T_253 = _atomics_legal_T_252 == 35'h0; // @[Parameters.scala:137:{46,59}] wire [34:0] _atomics_legal_T_255 = {1'h0, _atomics_legal_T_254}; // @[Parameters.scala:137:{31,41}] wire [34:0] _atomics_legal_T_256 = _atomics_legal_T_255 & 35'h8000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _atomics_legal_T_257 = _atomics_legal_T_256; // @[Parameters.scala:137:46] wire _atomics_legal_T_258 = _atomics_legal_T_257 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_259 = _atomics_legal_T_248 | _atomics_legal_T_253; // @[Parameters.scala:685:42] wire _atomics_legal_T_260 = _atomics_legal_T_259 | _atomics_legal_T_258; // @[Parameters.scala:685:42] wire _atomics_legal_T_261 = _atomics_legal_T_260; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_269 = _atomics_legal_T_261; // @[Parameters.scala:684:54, :686:26] wire [34:0] _atomics_legal_T_264 = {1'h0, _atomics_legal_T_263}; // @[Parameters.scala:137:{31,41}] wire [34:0] _atomics_legal_T_265 = _atomics_legal_T_264 & 35'h8110000; // @[Parameters.scala:137:{41,46}] wire [34:0] _atomics_legal_T_266 = _atomics_legal_T_265; // @[Parameters.scala:137:46] wire _atomics_legal_T_267 = _atomics_legal_T_266 == 35'h0; // @[Parameters.scala:137:{46,59}] wire atomics_legal_8 = _atomics_legal_T_269; // @[Parameters.scala:686:26] wire [7:0] _atomics_a_mask_T_8; // @[Misc.scala:222:10] wire [7:0] atomics_a_8_mask; // @[Edges.scala:517:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_8 = _atomics_a_mask_sizeOH_T_24[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_25 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_8; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_26 = _atomics_a_mask_sizeOH_T_25[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH_8 = {_atomics_a_mask_sizeOH_T_26[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1_8 = &s2_req_size; // @[Misc.scala:206:21] wire atomics_a_mask_sub_sub_size_8 = atomics_a_mask_sizeOH_8[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2_8 = atomics_a_mask_sub_sub_bit_8; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit_8 = ~atomics_a_mask_sub_sub_bit_8; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_8 = atomics_a_mask_sub_sub_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_16 = atomics_a_mask_sub_sub_size_8 & atomics_a_mask_sub_sub_0_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_8 = atomics_a_mask_sub_sub_sub_0_1_8 | _atomics_a_mask_sub_sub_acc_T_16; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_17 = atomics_a_mask_sub_sub_size_8 & atomics_a_mask_sub_sub_1_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_8 = atomics_a_mask_sub_sub_sub_0_1_8 | _atomics_a_mask_sub_sub_acc_T_17; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size_8 = atomics_a_mask_sizeOH_8[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_8 = ~atomics_a_mask_sub_bit_8; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_8 = atomics_a_mask_sub_sub_0_2_8 & atomics_a_mask_sub_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_32 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_0_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_8 = atomics_a_mask_sub_sub_0_1_8 | _atomics_a_mask_sub_acc_T_32; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_8 = atomics_a_mask_sub_sub_0_2_8 & atomics_a_mask_sub_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_33 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_1_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_8 = atomics_a_mask_sub_sub_0_1_8 | _atomics_a_mask_sub_acc_T_33; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_8 = atomics_a_mask_sub_sub_1_2_8 & atomics_a_mask_sub_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_34 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_2_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_8 = atomics_a_mask_sub_sub_1_1_8 | _atomics_a_mask_sub_acc_T_34; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_8 = atomics_a_mask_sub_sub_1_2_8 & atomics_a_mask_sub_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_35 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_3_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_8 = atomics_a_mask_sub_sub_1_1_8 | _atomics_a_mask_sub_acc_T_35; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_8 = atomics_a_mask_sizeOH_8[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_8 = ~atomics_a_mask_bit_8; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_64 = atomics_a_mask_sub_0_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_64 = atomics_a_mask_size_8 & atomics_a_mask_eq_64; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_64 = atomics_a_mask_sub_0_1_8 | _atomics_a_mask_acc_T_64; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_65 = atomics_a_mask_sub_0_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_65 = atomics_a_mask_size_8 & atomics_a_mask_eq_65; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_65 = atomics_a_mask_sub_0_1_8 | _atomics_a_mask_acc_T_65; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_66 = atomics_a_mask_sub_1_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_66 = atomics_a_mask_size_8 & atomics_a_mask_eq_66; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_66 = atomics_a_mask_sub_1_1_8 | _atomics_a_mask_acc_T_66; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_67 = atomics_a_mask_sub_1_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_67 = atomics_a_mask_size_8 & atomics_a_mask_eq_67; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_67 = atomics_a_mask_sub_1_1_8 | _atomics_a_mask_acc_T_67; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_68 = atomics_a_mask_sub_2_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_68 = atomics_a_mask_size_8 & atomics_a_mask_eq_68; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_68 = atomics_a_mask_sub_2_1_8 | _atomics_a_mask_acc_T_68; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_69 = atomics_a_mask_sub_2_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_69 = atomics_a_mask_size_8 & atomics_a_mask_eq_69; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_69 = atomics_a_mask_sub_2_1_8 | _atomics_a_mask_acc_T_69; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_70 = atomics_a_mask_sub_3_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_70 = atomics_a_mask_size_8 & atomics_a_mask_eq_70; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_70 = atomics_a_mask_sub_3_1_8 | _atomics_a_mask_acc_T_70; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_71 = atomics_a_mask_sub_3_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_71 = atomics_a_mask_size_8 & atomics_a_mask_eq_71; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_71 = atomics_a_mask_sub_3_1_8 | _atomics_a_mask_acc_T_71; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_8 = {atomics_a_mask_acc_65, atomics_a_mask_acc_64}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_8 = {atomics_a_mask_acc_67, atomics_a_mask_acc_66}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_8 = {atomics_a_mask_lo_hi_8, atomics_a_mask_lo_lo_8}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_8 = {atomics_a_mask_acc_69, atomics_a_mask_acc_68}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_8 = {atomics_a_mask_acc_71, atomics_a_mask_acc_70}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_8 = {atomics_a_mask_hi_hi_8, atomics_a_mask_hi_lo_8}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_8 = {atomics_a_mask_hi_8, atomics_a_mask_lo_8}; // @[Misc.scala:222:10] assign atomics_a_8_mask = _atomics_a_mask_T_8; // @[Misc.scala:222:10] wire [2:0] _GEN_99 = _atomics_T ? 3'h3 : 3'h0; // @[DCache.scala:587:81] wire [2:0] _atomics_T_1_opcode; // @[DCache.scala:587:81] assign _atomics_T_1_opcode = _GEN_99; // @[DCache.scala:587:81] wire [2:0] _atomics_T_1_param; // @[DCache.scala:587:81] assign _atomics_T_1_param = _GEN_99; // @[DCache.scala:587:81] wire [3:0] _atomics_T_1_size = _atomics_T ? atomics_a_size : 4'h0; // @[Edges.scala:534:17] wire [31:0] _atomics_T_1_address = _atomics_T ? atomics_a_address : 32'h0; // @[Edges.scala:534:17] wire [7:0] _atomics_T_1_mask = _atomics_T ? atomics_a_mask : 8'h0; // @[Edges.scala:534:17] wire [63:0] _atomics_T_1_data = _atomics_T ? atomics_a_data : 64'h0; // @[Edges.scala:534:17] wire [2:0] _atomics_T_3_opcode = _atomics_T_2 ? 3'h3 : _atomics_T_1_opcode; // @[DCache.scala:587:81] wire [2:0] _atomics_T_3_param = _atomics_T_2 ? 3'h0 : _atomics_T_1_param; // @[DCache.scala:587:81] wire [3:0] _atomics_T_3_size = _atomics_T_2 ? atomics_a_1_size : _atomics_T_1_size; // @[Edges.scala:534:17] wire [31:0] _atomics_T_3_address = _atomics_T_2 ? atomics_a_1_address : _atomics_T_1_address; // @[Edges.scala:534:17] wire [7:0] _atomics_T_3_mask = _atomics_T_2 ? atomics_a_1_mask : _atomics_T_1_mask; // @[Edges.scala:534:17] wire [63:0] _atomics_T_3_data = _atomics_T_2 ? atomics_a_1_data : _atomics_T_1_data; // @[Edges.scala:534:17] wire [2:0] _atomics_T_5_opcode = _atomics_T_4 ? 3'h3 : _atomics_T_3_opcode; // @[DCache.scala:587:81] wire [2:0] _atomics_T_5_param = _atomics_T_4 ? 3'h1 : _atomics_T_3_param; // @[DCache.scala:587:81] wire [3:0] _atomics_T_5_size = _atomics_T_4 ? atomics_a_2_size : _atomics_T_3_size; // @[Edges.scala:534:17] wire [31:0] _atomics_T_5_address = _atomics_T_4 ? atomics_a_2_address : _atomics_T_3_address; // @[Edges.scala:534:17] wire [7:0] _atomics_T_5_mask = _atomics_T_4 ? atomics_a_2_mask : _atomics_T_3_mask; // @[Edges.scala:534:17] wire [63:0] _atomics_T_5_data = _atomics_T_4 ? atomics_a_2_data : _atomics_T_3_data; // @[Edges.scala:534:17] wire [2:0] _atomics_T_7_opcode = _atomics_T_6 ? 3'h3 : _atomics_T_5_opcode; // @[DCache.scala:587:81] wire [2:0] _atomics_T_7_param = _atomics_T_6 ? 3'h2 : _atomics_T_5_param; // @[DCache.scala:587:81] wire [3:0] _atomics_T_7_size = _atomics_T_6 ? atomics_a_3_size : _atomics_T_5_size; // @[Edges.scala:534:17] wire [31:0] _atomics_T_7_address = _atomics_T_6 ? atomics_a_3_address : _atomics_T_5_address; // @[Edges.scala:534:17] wire [7:0] _atomics_T_7_mask = _atomics_T_6 ? atomics_a_3_mask : _atomics_T_5_mask; // @[Edges.scala:534:17] wire [63:0] _atomics_T_7_data = _atomics_T_6 ? atomics_a_3_data : _atomics_T_5_data; // @[Edges.scala:534:17] wire [2:0] _atomics_T_9_opcode = _atomics_T_8 ? 3'h2 : _atomics_T_7_opcode; // @[DCache.scala:587:81] wire [2:0] _atomics_T_9_param = _atomics_T_8 ? 3'h4 : _atomics_T_7_param; // @[DCache.scala:587:81] wire [3:0] _atomics_T_9_size = _atomics_T_8 ? atomics_a_4_size : _atomics_T_7_size; // @[Edges.scala:517:17] wire [31:0] _atomics_T_9_address = _atomics_T_8 ? atomics_a_4_address : _atomics_T_7_address; // @[Edges.scala:517:17] wire [7:0] _atomics_T_9_mask = _atomics_T_8 ? atomics_a_4_mask : _atomics_T_7_mask; // @[Edges.scala:517:17] wire [63:0] _atomics_T_9_data = _atomics_T_8 ? atomics_a_4_data : _atomics_T_7_data; // @[Edges.scala:517:17] wire [2:0] _atomics_T_11_opcode = _atomics_T_10 ? 3'h2 : _atomics_T_9_opcode; // @[DCache.scala:587:81] wire [2:0] _atomics_T_11_param = _atomics_T_10 ? 3'h0 : _atomics_T_9_param; // @[DCache.scala:587:81] wire [3:0] _atomics_T_11_size = _atomics_T_10 ? atomics_a_5_size : _atomics_T_9_size; // @[Edges.scala:517:17] wire [31:0] _atomics_T_11_address = _atomics_T_10 ? atomics_a_5_address : _atomics_T_9_address; // @[Edges.scala:517:17] wire [7:0] _atomics_T_11_mask = _atomics_T_10 ? atomics_a_5_mask : _atomics_T_9_mask; // @[Edges.scala:517:17] wire [63:0] _atomics_T_11_data = _atomics_T_10 ? atomics_a_5_data : _atomics_T_9_data; // @[Edges.scala:517:17] wire [2:0] _atomics_T_13_opcode = _atomics_T_12 ? 3'h2 : _atomics_T_11_opcode; // @[DCache.scala:587:81] wire [2:0] _atomics_T_13_param = _atomics_T_12 ? 3'h1 : _atomics_T_11_param; // @[DCache.scala:587:81] wire [3:0] _atomics_T_13_size = _atomics_T_12 ? atomics_a_6_size : _atomics_T_11_size; // @[Edges.scala:517:17] wire [31:0] _atomics_T_13_address = _atomics_T_12 ? atomics_a_6_address : _atomics_T_11_address; // @[Edges.scala:517:17] wire [7:0] _atomics_T_13_mask = _atomics_T_12 ? atomics_a_6_mask : _atomics_T_11_mask; // @[Edges.scala:517:17] wire [63:0] _atomics_T_13_data = _atomics_T_12 ? atomics_a_6_data : _atomics_T_11_data; // @[Edges.scala:517:17] wire [2:0] _atomics_T_15_opcode = _atomics_T_14 ? 3'h2 : _atomics_T_13_opcode; // @[DCache.scala:587:81] wire [2:0] _atomics_T_15_param = _atomics_T_14 ? 3'h2 : _atomics_T_13_param; // @[DCache.scala:587:81] wire [3:0] _atomics_T_15_size = _atomics_T_14 ? atomics_a_7_size : _atomics_T_13_size; // @[Edges.scala:517:17] wire [31:0] _atomics_T_15_address = _atomics_T_14 ? atomics_a_7_address : _atomics_T_13_address; // @[Edges.scala:517:17] wire [7:0] _atomics_T_15_mask = _atomics_T_14 ? atomics_a_7_mask : _atomics_T_13_mask; // @[Edges.scala:517:17] wire [63:0] _atomics_T_15_data = _atomics_T_14 ? atomics_a_7_data : _atomics_T_13_data; // @[Edges.scala:517:17] wire [2:0] atomics_opcode = _atomics_T_16 ? 3'h2 : _atomics_T_15_opcode; // @[DCache.scala:587:81] wire [2:0] atomics_param = _atomics_T_16 ? 3'h3 : _atomics_T_15_param; // @[DCache.scala:587:81] wire [3:0] atomics_size = _atomics_T_16 ? atomics_a_8_size : _atomics_T_15_size; // @[Edges.scala:517:17] wire [31:0] atomics_address = _atomics_T_16 ? atomics_a_8_address : _atomics_T_15_address; // @[Edges.scala:517:17] wire [7:0] atomics_mask = _atomics_T_16 ? atomics_a_8_mask : _atomics_T_15_mask; // @[Edges.scala:517:17] wire [63:0] atomics_data = _atomics_T_16 ? atomics_a_8_data : _atomics_T_15_data; // @[Edges.scala:517:17] wire [14:0] _tl_out_a_valid_T_2 = _tl_out_a_valid_T_1[20:6]; // @[DCache.scala:606:{43,62}] wire _tl_out_a_valid_T_3 = _tl_out_a_valid_T_2 == 15'h0; // @[DCache.scala:582:29, :606:{62,118}] wire _tl_out_a_valid_T_10 = ~s2_victim_dirty; // @[Misc.scala:38:9] wire _tl_out_a_valid_T_11 = _tl_out_a_valid_T_10; // @[DCache.scala:607:{88,91}] wire _tl_out_a_valid_T_12 = _tl_out_a_valid_T_6 & _tl_out_a_valid_T_11; // @[DCache.scala:605:29, :606:127, :607:88] wire _tl_out_a_valid_T_13 = s2_valid_uncached_pending | _tl_out_a_valid_T_12; // @[DCache.scala:430:64, :604:32, :606:127] assign _tl_out_a_valid_T_14 = _tl_out_a_valid_T_13; // @[DCache.scala:603:37, :604:32] assign tl_out_a_valid = _tl_out_a_valid_T_14; // @[DCache.scala:159:22, :603:37] wire _tl_out_a_bits_T = ~s2_uncached; // @[DCache.scala:424:39, :425:47, :608:24] wire _tl_out_a_bits_T_1 = ~s2_write; // @[DCache.scala:609:9] wire _tl_out_a_bits_T_3 = ~s2_read; // @[DCache.scala:611:9] wire [2:0] _tl_out_a_bits_T_4_opcode = _tl_out_a_bits_T_3 ? 3'h0 : atomics_opcode; // @[DCache.scala:587:81, :611:{8,9}] wire [2:0] _tl_out_a_bits_T_4_param = _tl_out_a_bits_T_3 ? 3'h0 : atomics_param; // @[DCache.scala:587:81, :611:{8,9}] wire [3:0] _tl_out_a_bits_T_4_size = _tl_out_a_bits_T_3 ? put_size : atomics_size; // @[Edges.scala:480:17] wire [31:0] _tl_out_a_bits_T_4_address = _tl_out_a_bits_T_3 ? put_address : atomics_address; // @[Edges.scala:480:17] wire [7:0] _tl_out_a_bits_T_4_mask = _tl_out_a_bits_T_3 ? put_mask : atomics_mask; // @[Edges.scala:480:17] wire [63:0] _tl_out_a_bits_T_4_data = _tl_out_a_bits_T_3 ? put_data : atomics_data; // @[Edges.scala:480:17] wire [2:0] _tl_out_a_bits_T_5_opcode = _tl_out_a_bits_T_2 ? 3'h1 : _tl_out_a_bits_T_4_opcode; // @[DCache.scala:610:{8,20}, :611:8] wire [2:0] _tl_out_a_bits_T_5_param = _tl_out_a_bits_T_2 ? 3'h0 : _tl_out_a_bits_T_4_param; // @[DCache.scala:610:{8,20}, :611:8] wire [3:0] _tl_out_a_bits_T_5_size = _tl_out_a_bits_T_2 ? putpartial_size : _tl_out_a_bits_T_4_size; // @[Edges.scala:500:17] wire [31:0] _tl_out_a_bits_T_5_address = _tl_out_a_bits_T_2 ? putpartial_address : _tl_out_a_bits_T_4_address; // @[Edges.scala:500:17] wire [7:0] _tl_out_a_bits_T_5_mask = _tl_out_a_bits_T_2 ? putpartial_mask : _tl_out_a_bits_T_4_mask; // @[Edges.scala:500:17] wire [63:0] _tl_out_a_bits_T_5_data = _tl_out_a_bits_T_2 ? putpartial_data : _tl_out_a_bits_T_4_data; // @[Edges.scala:500:17] wire [2:0] _tl_out_a_bits_T_6_opcode = _tl_out_a_bits_T_1 ? 3'h4 : _tl_out_a_bits_T_5_opcode; // @[DCache.scala:609:{8,9}, :610:8] wire [2:0] _tl_out_a_bits_T_6_param = _tl_out_a_bits_T_1 ? 3'h0 : _tl_out_a_bits_T_5_param; // @[DCache.scala:609:{8,9}, :610:8] wire [3:0] _tl_out_a_bits_T_6_size = _tl_out_a_bits_T_1 ? get_size : _tl_out_a_bits_T_5_size; // @[Edges.scala:460:17] wire [31:0] _tl_out_a_bits_T_6_address = _tl_out_a_bits_T_1 ? get_address : _tl_out_a_bits_T_5_address; // @[Edges.scala:460:17] wire [7:0] _tl_out_a_bits_T_6_mask = _tl_out_a_bits_T_1 ? get_mask : _tl_out_a_bits_T_5_mask; // @[Edges.scala:460:17] wire [63:0] _tl_out_a_bits_T_6_data = _tl_out_a_bits_T_1 ? 64'h0 : _tl_out_a_bits_T_5_data; // @[DCache.scala:609:{8,9}, :610:8] assign _tl_out_a_bits_T_7_opcode = _tl_out_a_bits_T ? 3'h0 : _tl_out_a_bits_T_6_opcode; // @[DCache.scala:608:{23,24}, :609:8] assign _tl_out_a_bits_T_7_param = _tl_out_a_bits_T ? 3'h0 : _tl_out_a_bits_T_6_param; // @[DCache.scala:608:{23,24}, :609:8] assign _tl_out_a_bits_T_7_size = _tl_out_a_bits_T ? 4'h0 : _tl_out_a_bits_T_6_size; // @[DCache.scala:608:{23,24}, :609:8] assign _tl_out_a_bits_T_7_address = _tl_out_a_bits_T ? 32'h0 : _tl_out_a_bits_T_6_address; // @[DCache.scala:608:{23,24}, :609:8] assign _tl_out_a_bits_T_7_mask = _tl_out_a_bits_T ? 8'h0 : _tl_out_a_bits_T_6_mask; // @[DCache.scala:608:{23,24}, :609:8] assign _tl_out_a_bits_T_7_data = _tl_out_a_bits_T ? 64'h0 : _tl_out_a_bits_T_6_data; // @[DCache.scala:608:{23,24}, :609:8] assign tl_out_a_bits_opcode = _tl_out_a_bits_T_7_opcode; // @[DCache.scala:159:22, :608:23] assign tl_out_a_bits_param = _tl_out_a_bits_T_7_param; // @[DCache.scala:159:22, :608:23] assign tl_out_a_bits_size = _tl_out_a_bits_T_7_size; // @[DCache.scala:159:22, :608:23] assign tl_out_a_bits_address = _tl_out_a_bits_T_7_address; // @[DCache.scala:159:22, :608:23] assign tl_out_a_bits_mask = _tl_out_a_bits_T_7_mask; // @[DCache.scala:159:22, :608:23] assign tl_out_a_bits_data = _tl_out_a_bits_T_7_data; // @[DCache.scala:159:22, :608:23] wire _io_cpu_perf_acquire_T = tl_out_a_ready & tl_out_a_valid; // @[Decoupled.scala:51:35] wire [4:0] _uncachedReqs_0_cmd_T_1 = {_uncachedReqs_0_cmd_T, 4'h1}; // @[DCache.scala:637:{37,49}] wire [4:0] _uncachedReqs_0_cmd_T_2 = s2_write ? _uncachedReqs_0_cmd_T_1 : 5'h0; // @[DCache.scala:637:{23,37}] wire _T_90 = nodeOut_d_ready & nodeOut_d_valid; // @[Decoupled.scala:51:35] wire _io_cpu_replay_next_T; // @[Decoupled.scala:51:35] assign _io_cpu_replay_next_T = _T_90; // @[Decoupled.scala:51:35] wire _io_cpu_perf_blocked_near_end_of_refill_T; // @[Decoupled.scala:51:35] assign _io_cpu_perf_blocked_near_end_of_refill_T = _T_90; // @[Decoupled.scala:51:35] wire _io_errors_bus_valid_T; // @[Decoupled.scala:51:35] assign _io_errors_bus_valid_T = _T_90; // @[Decoupled.scala:51:35] wire [26:0] _r_beats1_decode_T = 27'hFFF << nodeOut_d_bits_size; // @[package.scala:243:71] wire [11:0] _r_beats1_decode_T_1 = _r_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _r_beats1_decode_T_2 = ~_r_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] r_beats1_decode = _r_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire r_beats1_opdata = nodeOut_d_bits_opcode[0]; // @[Edges.scala:106:36] wire [8:0] r_beats1 = r_beats1_opdata ? r_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] r_counter; // @[Edges.scala:229:27] wire [9:0] _r_counter1_T = {1'h0, r_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] r_counter1 = _r_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = r_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _r_last_T = r_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _r_last_T_1 = r_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_last = _r_last_T | _r_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_done = d_last & _T_90; // @[Decoupled.scala:51:35] wire [8:0] _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] r_4 = r_beats1 & _r_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _r_counter_T = d_first ? r_beats1 : r_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] d_address_inc = {r_4, 3'h0}; // @[Edges.scala:234:25, :269:29] wire [1:0] d_opc = nodeOut_d_bits_opcode[1:0]; // @[DCache.scala:656:26] wire [1:0] data_plaInput = d_opc; // @[pla.scala:77:22] wire [1:0] data_invInputs = ~data_plaInput; // @[pla.scala:77:22, :78:21] wire data_invMatrixOutputs; // @[pla.scala:124:31] wire data_plaOutput; // @[pla.scala:81:23] wire grantIsUncachedData = data_plaOutput; // @[pla.scala:81:23] wire data_andMatrixOutputs_andMatrixInput_0 = data_plaInput[0]; // @[pla.scala:77:22, :90:45] wire data_andMatrixOutputs_andMatrixInput_1 = data_invInputs[1]; // @[pla.scala:78:21, :91:29] wire [1:0] _data_andMatrixOutputs_T = {data_andMatrixOutputs_andMatrixInput_0, data_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:90:45, :91:29, :98:53] wire data_andMatrixOutputs_0_2 = &_data_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] wire data_orMatrixOutputs = data_andMatrixOutputs_0_2; // @[pla.scala:98:70, :114:36] assign data_invMatrixOutputs = data_orMatrixOutputs; // @[pla.scala:114:36, :124:31] assign data_plaOutput = data_invMatrixOutputs; // @[pla.scala:81:23, :124:31] wire _tl_d_data_encoded_T_9 = io_ptw_customCSRs_csrs_0_value_0[9]; // @[CustomCSRs.scala:47:65] wire _tl_d_data_encoded_T_10 = ~_tl_d_data_encoded_T_9; // @[CustomCSRs.scala:47:65] wire _tl_d_data_encoded_T_11 = nodeOut_d_bits_corrupt & _tl_d_data_encoded_T_10; // @[DCache.scala:663:{77,80}] wire [15:0] tl_d_data_encoded_lo_lo_1 = {_tl_d_data_encoded_T_15, _tl_d_data_encoded_T_14}; // @[package.scala:45:27, :211:50] wire [15:0] tl_d_data_encoded_lo_hi_1 = {_tl_d_data_encoded_T_17, _tl_d_data_encoded_T_16}; // @[package.scala:45:27, :211:50] wire [31:0] tl_d_data_encoded_lo_1 = {tl_d_data_encoded_lo_hi_1, tl_d_data_encoded_lo_lo_1}; // @[package.scala:45:27] wire [15:0] tl_d_data_encoded_hi_lo_1 = {_tl_d_data_encoded_T_19, _tl_d_data_encoded_T_18}; // @[package.scala:45:27, :211:50] wire [15:0] tl_d_data_encoded_hi_hi_1 = {_tl_d_data_encoded_T_21, _tl_d_data_encoded_T_20}; // @[package.scala:45:27, :211:50] wire [31:0] tl_d_data_encoded_hi_1 = {tl_d_data_encoded_hi_hi_1, tl_d_data_encoded_hi_lo_1}; // @[package.scala:45:27] assign _tl_d_data_encoded_T_22 = {tl_d_data_encoded_hi_1, tl_d_data_encoded_lo_1}; // @[package.scala:45:27] assign tl_d_data_encoded = _tl_d_data_encoded_T_22; // @[package.scala:45:27] wire grantIsCached = _grantIsCached_T | _grantIsCached_T_1; // @[package.scala:16:47, :81:59] reg grantInProgress; // @[DCache.scala:667:32] wire block_probe_for_ordering = grantInProgress; // @[DCache.scala:667:32, :768:89] reg [2:0] blockProbeAfterGrantCount; // @[DCache.scala:668:42] wire [3:0] _blockProbeAfterGrantCount_T = {1'h0, blockProbeAfterGrantCount} - 4'h1; // @[DCache.scala:668:42, :669:99] wire [2:0] _blockProbeAfterGrantCount_T_1 = _blockProbeAfterGrantCount_T[2:0]; // @[DCache.scala:669:99] wire _nodeOut_d_ready_T = ~d_first; // @[Edges.scala:231:25] wire _nodeOut_d_ready_T_1 = _nodeOut_d_ready_T; // @[DCache.scala:671:{41,50}] wire _nodeOut_d_ready_T_2 = _nodeOut_d_ready_T_1; // @[DCache.scala:671:{50,69}] wire _nodeOut_d_ready_T_3 = ~grantIsCached | _nodeOut_d_ready_T_2; // @[package.scala:81:59] wire _GEN_100 = _T_90 & grantIsCached; // @[Decoupled.scala:51:35] assign replace = _GEN_100 & d_last; // @[Replacement.scala:37:29, :38:11] wire _GEN_101 = ~_T_90 | grantIsCached | ~grantIsUncachedData; // @[Decoupled.scala:51:35] assign s1_data_way = _GEN_101 ? 2'h1 : 2'h2; // @[DCache.scala:323:32, :674:24, :675:26, :684:35] wire [28:0] _s2_req_addr_dontCareBits_T = s1_paddr[31:3]; // @[DCache.scala:298:21, :701:41] wire [31:0] s2_req_addr_dontCareBits = {_s2_req_addr_dontCareBits_T, 3'h0}; // @[DCache.scala:701:{41,55}] wire [2:0] _s2_req_addr_T = uncachedResp_addr[2:0]; // @[DCache.scala:238:30, :702:45] wire [31:0] _s2_req_addr_T_1 = {s2_req_addr_dontCareBits[31:3], s2_req_addr_dontCareBits[2:0] | _s2_req_addr_T}; // @[DCache.scala:701:55, :702:{26,45}] wire _dataArb_io_in_1_valid_T = nodeOut_d_valid & grantIsRefill; // @[DCache.scala:666:29, :721:44] wire _dataArb_io_in_1_valid_T_1 = _dataArb_io_in_1_valid_T; // @[DCache.scala:721:{44,61}] wire _metaArb_io_in_3_valid_T = grantIsCached & d_done; // @[package.scala:81:59] wire _metaArb_io_in_3_valid_T_1 = ~nodeOut_d_bits_denied; // @[DCache.scala:741:56] assign _metaArb_io_in_3_valid_T_2 = _metaArb_io_in_3_valid_T & _metaArb_io_in_3_valid_T_1; // @[DCache.scala:741:{43,53,56}] assign metaArb_io_in_3_valid = _metaArb_io_in_3_valid_T_2; // @[DCache.scala:135:28, :741:53] assign metaArb_io_in_3_bits_way_en = refill_way[0]; // @[DCache.scala:135:28, :229:23, :743:32] assign metaArb_io_in_3_bits_idx = _metaArb_io_in_3_bits_idx_T; // @[DCache.scala:135:28, :744:40] assign _metaArb_io_in_3_bits_addr_T_2 = {_metaArb_io_in_3_bits_addr_T, _metaArb_io_in_3_bits_addr_T_1}; // @[DCache.scala:745:{36,58,80}] assign metaArb_io_in_3_bits_addr = _metaArb_io_in_3_bits_addr_T_2; // @[DCache.scala:135:28, :745:36] wire _metaArb_io_in_3_bits_data_c_cat_T_2 = _metaArb_io_in_3_bits_data_c_cat_T | _metaArb_io_in_3_bits_data_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _metaArb_io_in_3_bits_data_c_cat_T_4 = _metaArb_io_in_3_bits_data_c_cat_T_2 | _metaArb_io_in_3_bits_data_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _metaArb_io_in_3_bits_data_c_cat_T_9 = _metaArb_io_in_3_bits_data_c_cat_T_5 | _metaArb_io_in_3_bits_data_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_10 = _metaArb_io_in_3_bits_data_c_cat_T_9 | _metaArb_io_in_3_bits_data_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_11 = _metaArb_io_in_3_bits_data_c_cat_T_10 | _metaArb_io_in_3_bits_data_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_17 = _metaArb_io_in_3_bits_data_c_cat_T_12 | _metaArb_io_in_3_bits_data_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_18 = _metaArb_io_in_3_bits_data_c_cat_T_17 | _metaArb_io_in_3_bits_data_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_19 = _metaArb_io_in_3_bits_data_c_cat_T_18 | _metaArb_io_in_3_bits_data_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_20 = _metaArb_io_in_3_bits_data_c_cat_T_19 | _metaArb_io_in_3_bits_data_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_21 = _metaArb_io_in_3_bits_data_c_cat_T_11 | _metaArb_io_in_3_bits_data_c_cat_T_20; // @[package.scala:81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_22 = _metaArb_io_in_3_bits_data_c_cat_T_4 | _metaArb_io_in_3_bits_data_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _metaArb_io_in_3_bits_data_c_cat_T_25 = _metaArb_io_in_3_bits_data_c_cat_T_23 | _metaArb_io_in_3_bits_data_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _metaArb_io_in_3_bits_data_c_cat_T_27 = _metaArb_io_in_3_bits_data_c_cat_T_25 | _metaArb_io_in_3_bits_data_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _metaArb_io_in_3_bits_data_c_cat_T_32 = _metaArb_io_in_3_bits_data_c_cat_T_28 | _metaArb_io_in_3_bits_data_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_33 = _metaArb_io_in_3_bits_data_c_cat_T_32 | _metaArb_io_in_3_bits_data_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_34 = _metaArb_io_in_3_bits_data_c_cat_T_33 | _metaArb_io_in_3_bits_data_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_40 = _metaArb_io_in_3_bits_data_c_cat_T_35 | _metaArb_io_in_3_bits_data_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_41 = _metaArb_io_in_3_bits_data_c_cat_T_40 | _metaArb_io_in_3_bits_data_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_42 = _metaArb_io_in_3_bits_data_c_cat_T_41 | _metaArb_io_in_3_bits_data_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_43 = _metaArb_io_in_3_bits_data_c_cat_T_42 | _metaArb_io_in_3_bits_data_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_44 = _metaArb_io_in_3_bits_data_c_cat_T_34 | _metaArb_io_in_3_bits_data_c_cat_T_43; // @[package.scala:81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_45 = _metaArb_io_in_3_bits_data_c_cat_T_27 | _metaArb_io_in_3_bits_data_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _metaArb_io_in_3_bits_data_c_cat_T_47 = _metaArb_io_in_3_bits_data_c_cat_T_45 | _metaArb_io_in_3_bits_data_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _metaArb_io_in_3_bits_data_c_cat_T_49 = _metaArb_io_in_3_bits_data_c_cat_T_47 | _metaArb_io_in_3_bits_data_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] metaArb_io_in_3_bits_data_c = {_metaArb_io_in_3_bits_data_c_cat_T_22, _metaArb_io_in_3_bits_data_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _metaArb_io_in_3_bits_data_T_1 = {metaArb_io_in_3_bits_data_c, nodeOut_d_bits_param}; // @[Metadata.scala:29:18, :84:18] wire _metaArb_io_in_3_bits_data_T_10 = _metaArb_io_in_3_bits_data_T_1 == 4'h1; // @[Metadata.scala:84:{18,38}] wire [1:0] _metaArb_io_in_3_bits_data_T_11 = {1'h0, _metaArb_io_in_3_bits_data_T_10}; // @[Metadata.scala:84:38] wire _metaArb_io_in_3_bits_data_T_12 = _metaArb_io_in_3_bits_data_T_1 == 4'h0; // @[Metadata.scala:84:{18,38}] wire [1:0] _metaArb_io_in_3_bits_data_T_13 = _metaArb_io_in_3_bits_data_T_12 ? 2'h2 : _metaArb_io_in_3_bits_data_T_11; // @[Metadata.scala:84:38] wire _metaArb_io_in_3_bits_data_T_14 = _metaArb_io_in_3_bits_data_T_1 == 4'h4; // @[Metadata.scala:84:{18,38}] wire [1:0] _metaArb_io_in_3_bits_data_T_15 = _metaArb_io_in_3_bits_data_T_14 ? 2'h2 : _metaArb_io_in_3_bits_data_T_13; // @[Metadata.scala:84:38] wire _metaArb_io_in_3_bits_data_T_16 = _metaArb_io_in_3_bits_data_T_1 == 4'hC; // @[Metadata.scala:84:{18,38}] wire [1:0] _metaArb_io_in_3_bits_data_T_17 = _metaArb_io_in_3_bits_data_T_16 ? 2'h3 : _metaArb_io_in_3_bits_data_T_15; // @[Metadata.scala:84:38] wire [1:0] metaArb_io_in_3_bits_data_meta_state = _metaArb_io_in_3_bits_data_T_17; // @[Metadata.scala:84:38, :160:20] wire [1:0] metaArb_io_in_3_bits_data_meta_1_coh_state = metaArb_io_in_3_bits_data_meta_state; // @[Metadata.scala:160:20] wire [17:0] metaArb_io_in_3_bits_data_meta_1_tag; // @[HellaCache.scala:305:20] assign metaArb_io_in_3_bits_data_meta_1_tag = _metaArb_io_in_3_bits_data_T[17:0]; // @[HellaCache.scala:305:20, :306:14] assign _metaArb_io_in_3_bits_data_T_18 = {metaArb_io_in_3_bits_data_meta_1_coh_state, metaArb_io_in_3_bits_data_meta_1_tag}; // @[HellaCache.scala:305:20] assign metaArb_io_in_3_bits_data = _metaArb_io_in_3_bits_data_T_18; // @[DCache.scala:135:28, :746:134] reg blockUncachedGrant; // @[DCache.scala:750:33] wire _T_100 = grantIsUncachedData & (blockUncachedGrant | s1_valid); // @[Decode.scala:55:116] assign nodeOut_d_ready = ~(_T_100 | grantIsRefill & ~dataArb_io_in_1_ready) & _nodeOut_d_ready_T_3; // @[DCache.scala:152:28, :666:29, :671:{18,24}, :722:{23,26,51}, :724:20, :752:{31,68}, :753:22] assign io_cpu_req_ready_0 = _T_100 ? ~(nodeOut_d_valid | ~metaArb_io_in_7_ready | _T_4) & _io_cpu_req_ready_T_4 : ~(~metaArb_io_in_7_ready | _T_4) & _io_cpu_req_ready_T_4; // @[DCache.scala:101:7, :135:28, :195:9, :233:{20,73}, :258:{33,45,64}, :267:{34,53}, :275:{79,98}, :752:{31,68}, :755:29, :756:26] wire _GEN_102 = _T_100 & nodeOut_d_valid; // @[DCache.scala:721:26, :752:{31,68}, :755:29, :757:32] assign dataArb_io_in_1_valid = _GEN_102 | _dataArb_io_in_1_valid_T_1; // @[DCache.scala:152:28, :721:{26,61}, :752:68, :755:29, :757:32] assign dataArb_io_in_1_bits_write = ~_GEN_102 & pstore_drain; // @[DCache.scala:152:28, :516:27, :721:26, :734:27, :752:68, :755:29, :757:32, :758:37] wire _blockUncachedGrant_T = ~dataArb_io_in_1_ready; // @[DCache.scala:152:28, :722:26, :759:31] wire _block_probe_for_core_progress_T = |blockProbeAfterGrantCount; // @[DCache.scala:668:42, :669:35, :766:65] wire block_probe_for_core_progress = _block_probe_for_core_progress_T | lrscValid; // @[DCache.scala:473:29, :766:{65,71}] wire [14:0] _block_probe_for_pending_release_ack_T_1 = _block_probe_for_pending_release_ack_T[20:6]; // @[DCache.scala:767:{88,107}] wire _block_probe_for_pending_release_ack_T_2 = _block_probe_for_pending_release_ack_T_1 == 15'h0; // @[DCache.scala:582:29, :767:{107,163}] wire _metaArb_io_in_6_valid_T = ~block_probe_for_core_progress; // @[DCache.scala:766:71, :769:48] wire _metaArb_io_in_6_valid_T_1 = _metaArb_io_in_6_valid_T | lrscBackingOff; // @[DCache.scala:474:40, :769:{48,79}] wire [1:0] _metaArb_io_in_6_bits_addr_T = io_cpu_req_bits_addr_0[33:32]; // @[DCache.scala:101:7, :773:58] assign _metaArb_io_in_6_bits_addr_T_1 = {_metaArb_io_in_6_bits_addr_T, 32'h0}; // @[DCache.scala:773:{36,58}] assign metaArb_io_in_6_bits_addr = _metaArb_io_in_6_bits_addr_T_1; // @[DCache.scala:135:28, :773:36] wire _releaseRejected_T_2; // @[DCache.scala:803:44] wire releaseRejected; // @[DCache.scala:800:29] wire _s2_release_data_valid_T = ~releaseRejected; // @[DCache.scala:800:29, :802:64] reg s2_release_data_valid; // @[DCache.scala:802:38] assign _releaseRejected_T_2 = s2_release_data_valid; // @[DCache.scala:802:38, :803:44] wire _tl_out_c_valid_T_3 = s2_release_data_valid; // @[DCache.scala:802:38, :810:44] assign releaseRejected = _releaseRejected_T_2; // @[DCache.scala:800:29, :803:44] wire [1:0] _releaseDataBeat_T_1 = {1'h0, s2_release_data_valid}; // @[DCache.scala:802:38, :804:98] wire [2:0] _releaseDataBeat_T_2 = {1'h0, _releaseDataBeat_T_1}; // @[DCache.scala:804:{93,98}] wire [1:0] _releaseDataBeat_T_3 = _releaseDataBeat_T_2[1:0]; // @[DCache.scala:804:93] wire [1:0] _releaseDataBeat_T_4 = releaseRejected ? 2'h0 : _releaseDataBeat_T_3; // @[DCache.scala:800:29, :804:{48,93}] wire [10:0] _releaseDataBeat_T_5 = {9'h0, _releaseDataBeat_T_4}; // @[DCache.scala:804:{43,48}] wire [9:0] releaseDataBeat = _releaseDataBeat_T_5[9:0]; // @[DCache.scala:804:43] assign _tl_out_c_valid_T_6 = _tl_out_c_valid_T_3; // @[DCache.scala:810:{44,117}] assign tl_out_c_valid = _tl_out_c_valid_T_6; // @[Bundles.scala:265:61] wire [1:0] metaArb_io_in_4_bits_data_meta_coh_state = newCoh_state; // @[HellaCache.scala:305:20] wire _dataArb_io_in_2_valid_T = releaseDataBeat < 10'h8; // @[DCache.scala:804:43, :900:60] wire [2:0] _dataArb_io_in_2_bits_addr_T_2 = releaseDataBeat[2:0]; // @[DCache.scala:804:43, :903:90] wire [5:0] _dataArb_io_in_2_bits_addr_T_3 = {_dataArb_io_in_2_bits_addr_T_2, 3'h0}; // @[DCache.scala:903:{90,117}] assign _dataArb_io_in_2_bits_addr_T_4 = {8'h0, _dataArb_io_in_2_bits_addr_T_3}; // @[DCache.scala:903:{72,117}] assign dataArb_io_in_2_bits_addr = _dataArb_io_in_2_bits_addr_T_4; // @[DCache.scala:152:28, :903:72] assign _metaArb_io_in_4_bits_addr_T_2 = {_metaArb_io_in_4_bits_addr_T, 14'h0}; // @[DCache.scala:912:{36,58}] assign metaArb_io_in_4_bits_addr = _metaArb_io_in_4_bits_addr_T_2; // @[DCache.scala:135:28, :912:36] assign _metaArb_io_in_4_bits_data_T_1 = {metaArb_io_in_4_bits_data_meta_coh_state, 18'h0}; // @[HellaCache.scala:305:20] assign metaArb_io_in_4_bits_data = _metaArb_io_in_4_bits_data_T_1; // @[DCache.scala:135:28, :913:97] assign metaArb_io_in_5_bits_data = _metaArb_io_in_4_bits_data_T_1; // @[DCache.scala:135:28, :913:97] assign metaArb_io_in_6_bits_data = _metaArb_io_in_4_bits_data_T_1; // @[DCache.scala:135:28, :913:97] assign metaArb_io_in_7_bits_data = _metaArb_io_in_4_bits_data_T_1; // @[DCache.scala:135:28, :913:97] wire _io_cpu_s2_uncached_T = ~s2_hit; // @[Misc.scala:35:9] assign _io_cpu_s2_uncached_T_1 = s2_uncached & _io_cpu_s2_uncached_T; // @[DCache.scala:424:39, :920:{37,40}] assign io_cpu_s2_uncached_0 = _io_cpu_s2_uncached_T_1; // @[DCache.scala:101:7, :920:37] wire _io_cpu_ordered_T = ~s1_req_no_xcpt; // @[DCache.scala:196:25, :929:35] wire _io_cpu_ordered_T_1 = s1_valid & _io_cpu_ordered_T; // @[DCache.scala:182:25, :929:{32,35}] wire _io_cpu_ordered_T_2 = ~s2_req_no_xcpt; // @[DCache.scala:339:19, :929:72] wire _io_cpu_ordered_T_3 = s2_valid & _io_cpu_ordered_T_2; // @[DCache.scala:331:25, :929:{69,72}] wire _io_cpu_ordered_T_4 = _io_cpu_ordered_T_1 | _io_cpu_ordered_T_3; // @[DCache.scala:929:{32,57,69}] wire _io_cpu_ordered_T_5 = _io_cpu_ordered_T_4 | cached_grant_wait; // @[DCache.scala:223:34, :929:{57,94}] wire _io_cpu_ordered_T_7 = _io_cpu_ordered_T_5 | _io_cpu_ordered_T_6; // @[DCache.scala:929:{94,115,142}] assign _io_cpu_ordered_T_8 = ~_io_cpu_ordered_T_7; // @[DCache.scala:929:{21,115}] assign io_cpu_ordered_0 = _io_cpu_ordered_T_8; // @[DCache.scala:101:7, :929:21] wire _io_cpu_store_pending_T_2 = _io_cpu_store_pending_T | _io_cpu_store_pending_T_1; // @[Consts.scala:90:{32,42,49}] wire _io_cpu_store_pending_T_4 = _io_cpu_store_pending_T_2 | _io_cpu_store_pending_T_3; // @[Consts.scala:90:{42,59,66}] wire _io_cpu_store_pending_T_9 = _io_cpu_store_pending_T_5 | _io_cpu_store_pending_T_6; // @[package.scala:16:47, :81:59] wire _io_cpu_store_pending_T_10 = _io_cpu_store_pending_T_9 | _io_cpu_store_pending_T_7; // @[package.scala:16:47, :81:59] wire _io_cpu_store_pending_T_11 = _io_cpu_store_pending_T_10 | _io_cpu_store_pending_T_8; // @[package.scala:16:47, :81:59] wire _io_cpu_store_pending_T_17 = _io_cpu_store_pending_T_12 | _io_cpu_store_pending_T_13; // @[package.scala:16:47, :81:59] wire _io_cpu_store_pending_T_18 = _io_cpu_store_pending_T_17 | _io_cpu_store_pending_T_14; // @[package.scala:16:47, :81:59] wire _io_cpu_store_pending_T_19 = _io_cpu_store_pending_T_18 | _io_cpu_store_pending_T_15; // @[package.scala:16:47, :81:59] wire _io_cpu_store_pending_T_20 = _io_cpu_store_pending_T_19 | _io_cpu_store_pending_T_16; // @[package.scala:16:47, :81:59] wire _io_cpu_store_pending_T_21 = _io_cpu_store_pending_T_11 | _io_cpu_store_pending_T_20; // @[package.scala:81:59] wire _io_cpu_store_pending_T_22 = _io_cpu_store_pending_T_4 | _io_cpu_store_pending_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _io_cpu_store_pending_T_23 = cached_grant_wait & _io_cpu_store_pending_T_22; // @[DCache.scala:223:34, :930:46] assign _io_cpu_store_pending_T_25 = _io_cpu_store_pending_T_23 | _io_cpu_store_pending_T_24; // @[DCache.scala:930:{46,70,97}] assign io_cpu_store_pending_0 = _io_cpu_store_pending_T_25; // @[DCache.scala:101:7, :930:70] wire _s1_xcpt_valid_T = ~s1_req_no_xcpt; // @[DCache.scala:196:25, :929:35, :932:43] wire _s1_xcpt_valid_T_1 = _tlb_io_req_valid_T_3 & _s1_xcpt_valid_T; // @[DCache.scala:273:40, :932:{40,43}] wire _s1_xcpt_valid_T_2 = ~s1_nack; // @[DCache.scala:185:28, :187:41, :932:68] wire s1_xcpt_valid = _s1_xcpt_valid_T_1 & _s1_xcpt_valid_T_2; // @[DCache.scala:932:{40,65,68}] reg io_cpu_s2_xcpt_REG; // @[DCache.scala:933:32] wire [31:0] _io_cpu_s2_xcpt_T_paddr = io_cpu_s2_xcpt_REG ? s2_tlb_xcpt_paddr : 32'h0; // @[DCache.scala:342:24, :933:{24,32}] wire [33:0] _io_cpu_s2_xcpt_T_gpa = io_cpu_s2_xcpt_REG ? s2_tlb_xcpt_gpa : 34'h0; // @[DCache.scala:342:24, :933:{24,32}] assign _io_cpu_s2_xcpt_T_pf_ld = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_pf_ld; // @[DCache.scala:342:24, :933:{24,32}] assign _io_cpu_s2_xcpt_T_pf_st = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_pf_st; // @[DCache.scala:342:24, :933:{24,32}] wire _io_cpu_s2_xcpt_T_pf_inst = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_pf_inst; // @[DCache.scala:342:24, :933:{24,32}] assign _io_cpu_s2_xcpt_T_ae_ld = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_ae_ld; // @[DCache.scala:342:24, :933:{24,32}] assign _io_cpu_s2_xcpt_T_ae_st = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_ae_st; // @[DCache.scala:342:24, :933:{24,32}] wire _io_cpu_s2_xcpt_T_ae_inst = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_ae_inst; // @[DCache.scala:342:24, :933:{24,32}] assign _io_cpu_s2_xcpt_T_ma_ld = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_ma_ld; // @[DCache.scala:342:24, :933:{24,32}] assign _io_cpu_s2_xcpt_T_ma_st = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_ma_st; // @[DCache.scala:342:24, :933:{24,32}] wire _io_cpu_s2_xcpt_T_cacheable = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_cacheable; // @[DCache.scala:342:24, :933:{24,32}] wire _io_cpu_s2_xcpt_T_must_alloc = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_must_alloc; // @[DCache.scala:342:24, :933:{24,32}] wire _io_cpu_s2_xcpt_T_prefetchable = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_prefetchable; // @[DCache.scala:342:24, :933:{24,32}] wire [1:0] _io_cpu_s2_xcpt_T_size = io_cpu_s2_xcpt_REG ? s2_tlb_xcpt_size : 2'h0; // @[DCache.scala:342:24, :933:{24,32}] wire [4:0] _io_cpu_s2_xcpt_T_cmd = io_cpu_s2_xcpt_REG ? s2_tlb_xcpt_cmd : 5'h0; // @[DCache.scala:342:24, :933:{24,32}] assign io_cpu_s2_xcpt_pf_ld_0 = _io_cpu_s2_xcpt_T_pf_ld; // @[DCache.scala:101:7, :933:24] assign io_cpu_s2_xcpt_pf_st_0 = _io_cpu_s2_xcpt_T_pf_st; // @[DCache.scala:101:7, :933:24] assign io_cpu_s2_xcpt_ae_ld_0 = _io_cpu_s2_xcpt_T_ae_ld; // @[DCache.scala:101:7, :933:24] assign io_cpu_s2_xcpt_ae_st_0 = _io_cpu_s2_xcpt_T_ae_st; // @[DCache.scala:101:7, :933:24] assign io_cpu_s2_xcpt_ma_ld_0 = _io_cpu_s2_xcpt_T_ma_ld; // @[DCache.scala:101:7, :933:24] assign io_cpu_s2_xcpt_ma_st_0 = _io_cpu_s2_xcpt_T_ma_st; // @[DCache.scala:101:7, :933:24] reg [63:0] s2_uncached_data_word; // @[DCache.scala:947:40] reg doUncachedResp; // @[DCache.scala:948:31] assign io_cpu_resp_bits_replay_0 = doUncachedResp; // @[DCache.scala:101:7, :948:31] wire _io_cpu_resp_valid_T = s2_valid_hit_pre_data_ecc | doUncachedResp; // @[DCache.scala:420:69, :948:31, :949:51] assign _io_cpu_resp_valid_T_2 = _io_cpu_resp_valid_T; // @[DCache.scala:949:{51,70}] assign io_cpu_resp_valid_0 = _io_cpu_resp_valid_T_2; // @[DCache.scala:101:7, :949:70] wire _io_cpu_replay_next_T_1 = _io_cpu_replay_next_T & grantIsUncachedData; // @[Decoupled.scala:51:35] assign _io_cpu_replay_next_T_3 = _io_cpu_replay_next_T_1; // @[DCache.scala:950:{39,62}] assign io_cpu_replay_next_0 = _io_cpu_replay_next_T_3; // @[DCache.scala:101:7, :950:62]

Generate the Verilog code corresponding to the following Chisel files. File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File Nodes.scala: package constellation.channel import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Parameters, Field} import freechips.rocketchip.diplomacy._ case class EmptyParams() case class ChannelEdgeParams(cp: ChannelParams, p: Parameters) object ChannelImp extends SimpleNodeImp[EmptyParams, ChannelParams, ChannelEdgeParams, Channel] { def edge(pd: EmptyParams, pu: ChannelParams, p: Parameters, sourceInfo: SourceInfo) = { ChannelEdgeParams(pu, p) } def bundle(e: ChannelEdgeParams) = new Channel(e.cp)(e.p) def render(e: ChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) { RenderedEdge(colour = "ffffff", label = "X") } else { RenderedEdge(colour = "#0000ff", label = e.cp.payloadBits.toString) } override def monitor(bundle: Channel, edge: ChannelEdgeParams): Unit = { val monitor = Module(new NoCMonitor(edge.cp)(edge.p)) monitor.io.in := bundle } // TODO: Add nodepath stuff? override def mixO, override def mixI } case class ChannelSourceNode(val destId: Int)(implicit valName: ValName) extends SourceNode(ChannelImp)(Seq(EmptyParams())) case class ChannelDestNode(val destParams: ChannelParams)(implicit valName: ValName) extends SinkNode(ChannelImp)(Seq(destParams)) case class ChannelAdapterNode( slaveFn: ChannelParams => ChannelParams = { d => d })( implicit valName: ValName) extends AdapterNode(ChannelImp)((e: EmptyParams) => e, slaveFn) case class ChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(ChannelImp)() case class ChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(ChannelImp)() case class IngressChannelEdgeParams(cp: IngressChannelParams, p: Parameters) case class EgressChannelEdgeParams(cp: EgressChannelParams, p: Parameters) object IngressChannelImp extends SimpleNodeImp[EmptyParams, IngressChannelParams, IngressChannelEdgeParams, IngressChannel] { def edge(pd: EmptyParams, pu: IngressChannelParams, p: Parameters, sourceInfo: SourceInfo) = { IngressChannelEdgeParams(pu, p) } def bundle(e: IngressChannelEdgeParams) = new IngressChannel(e.cp)(e.p) def render(e: IngressChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) { RenderedEdge(colour = "ffffff", label = "X") } else { RenderedEdge(colour = "#00ff00", label = e.cp.payloadBits.toString) } } object EgressChannelImp extends SimpleNodeImp[EmptyParams, EgressChannelParams, EgressChannelEdgeParams, EgressChannel] { def edge(pd: EmptyParams, pu: EgressChannelParams, p: Parameters, sourceInfo: SourceInfo) = { EgressChannelEdgeParams(pu, p) } def bundle(e: EgressChannelEdgeParams) = new EgressChannel(e.cp)(e.p) def render(e: EgressChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) { RenderedEdge(colour = "ffffff", label = "X") } else { RenderedEdge(colour = "#ff0000", label = e.cp.payloadBits.toString) } } case class IngressChannelSourceNode(val destId: Int)(implicit valName: ValName) extends SourceNode(IngressChannelImp)(Seq(EmptyParams())) case class IngressChannelDestNode(val destParams: IngressChannelParams)(implicit valName: ValName) extends SinkNode(IngressChannelImp)(Seq(destParams)) case class EgressChannelSourceNode(val egressId: Int)(implicit valName: ValName) extends SourceNode(EgressChannelImp)(Seq(EmptyParams())) case class EgressChannelDestNode(val destParams: EgressChannelParams)(implicit valName: ValName) extends SinkNode(EgressChannelImp)(Seq(destParams)) case class IngressChannelAdapterNode( slaveFn: IngressChannelParams => IngressChannelParams = { d => d })( implicit valName: ValName) extends AdapterNode(IngressChannelImp)(m => m, slaveFn) case class EgressChannelAdapterNode( slaveFn: EgressChannelParams => EgressChannelParams = { d => d })( implicit valName: ValName) extends AdapterNode(EgressChannelImp)(m => m, slaveFn) case class IngressChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(IngressChannelImp)() case class EgressChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(EgressChannelImp)() case class IngressChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(IngressChannelImp)() case class EgressChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(EgressChannelImp)() File Router.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{RoutingRelation} import constellation.noc.{HasNoCParams} case class UserRouterParams( // Payload width. Must match payload width on all channels attached to this routing node payloadBits: Int = 64, // Combines SA and ST stages (removes pipeline register) combineSAST: Boolean = false, // Combines RC and VA stages (removes pipeline register) combineRCVA: Boolean = false, // Adds combinational path from SA to VA coupleSAVA: Boolean = false, vcAllocator: VCAllocatorParams => Parameters => VCAllocator = (vP) => (p) => new RotatingSingleVCAllocator(vP)(p) ) case class RouterParams( nodeId: Int, nIngress: Int, nEgress: Int, user: UserRouterParams ) trait HasRouterOutputParams { def outParams: Seq[ChannelParams] def egressParams: Seq[EgressChannelParams] def allOutParams = outParams ++ egressParams def nOutputs = outParams.size def nEgress = egressParams.size def nAllOutputs = allOutParams.size } trait HasRouterInputParams { def inParams: Seq[ChannelParams] def ingressParams: Seq[IngressChannelParams] def allInParams = inParams ++ ingressParams def nInputs = inParams.size def nIngress = ingressParams.size def nAllInputs = allInParams.size } trait HasRouterParams { def routerParams: RouterParams def nodeId = routerParams.nodeId def payloadBits = routerParams.user.payloadBits } class DebugBundle(val nIn: Int) extends Bundle { val va_stall = Vec(nIn, UInt()) val sa_stall = Vec(nIn, UInt()) } class Router( val routerParams: RouterParams, preDiplomaticInParams: Seq[ChannelParams], preDiplomaticIngressParams: Seq[IngressChannelParams], outDests: Seq[Int], egressIds: Seq[Int] )(implicit p: Parameters) extends LazyModule with HasNoCParams with HasRouterParams { val allPreDiplomaticInParams = preDiplomaticInParams ++ preDiplomaticIngressParams val destNodes = preDiplomaticInParams.map(u => ChannelDestNode(u)) val sourceNodes = outDests.map(u => ChannelSourceNode(u)) val ingressNodes = preDiplomaticIngressParams.map(u => IngressChannelDestNode(u)) val egressNodes = egressIds.map(u => EgressChannelSourceNode(u)) val debugNode = BundleBridgeSource(() => new DebugBundle(allPreDiplomaticInParams.size)) val ctrlNode = if (hasCtrl) Some(BundleBridgeSource(() => new RouterCtrlBundle)) else None def inParams = module.inParams def outParams = module.outParams def ingressParams = module.ingressParams def egressParams = module.egressParams lazy val module = new LazyModuleImp(this) with HasRouterInputParams with HasRouterOutputParams { val (io_in, edgesIn) = destNodes.map(_.in(0)).unzip val (io_out, edgesOut) = sourceNodes.map(_.out(0)).unzip val (io_ingress, edgesIngress) = ingressNodes.map(_.in(0)).unzip val (io_egress, edgesEgress) = egressNodes.map(_.out(0)).unzip val io_debug = debugNode.out(0)._1 val inParams = edgesIn.map(_.cp) val outParams = edgesOut.map(_.cp) val ingressParams = edgesIngress.map(_.cp) val egressParams = edgesEgress.map(_.cp) allOutParams.foreach(u => require(u.srcId == nodeId && u.payloadBits == routerParams.user.payloadBits)) allInParams.foreach(u => require(u.destId == nodeId && u.payloadBits == routerParams.user.payloadBits)) require(nIngress == routerParams.nIngress) require(nEgress == routerParams.nEgress) require(nAllInputs >= 1) require(nAllOutputs >= 1) require(nodeId < (1 << nodeIdBits)) val input_units = inParams.zipWithIndex.map { case (u,i) => Module(new InputUnit(u, outParams, egressParams, routerParams.user.combineRCVA, routerParams.user.combineSAST)) .suggestName(s"input_unit_${i}_from_${u.srcId}") } val ingress_units = ingressParams.zipWithIndex.map { case (u,i) => Module(new IngressUnit(i, u, outParams, egressParams, routerParams.user.combineRCVA, routerParams.user.combineSAST)) .suggestName(s"ingress_unit_${i+nInputs}_from_${u.ingressId}") } val all_input_units = input_units ++ ingress_units val output_units = outParams.zipWithIndex.map { case (u,i) => Module(new OutputUnit(inParams, ingressParams, u)) .suggestName(s"output_unit_${i}_to_${u.destId}")} val egress_units = egressParams.zipWithIndex.map { case (u,i) => Module(new EgressUnit(routerParams.user.coupleSAVA && all_input_units.size == 1, routerParams.user.combineSAST, inParams, ingressParams, u)) .suggestName(s"egress_unit_${i+nOutputs}_to_${u.egressId}")} val all_output_units = output_units ++ egress_units val switch = Module(new Switch(routerParams, inParams, outParams, ingressParams, egressParams)) val switch_allocator = Module(new SwitchAllocator(routerParams, inParams, outParams, ingressParams, egressParams)) val vc_allocator = Module(routerParams.user.vcAllocator( VCAllocatorParams(routerParams, inParams, outParams, ingressParams, egressParams) )(p)) val route_computer = Module(new RouteComputer(routerParams, inParams, outParams, ingressParams, egressParams)) val fires_count = WireInit(PopCount(vc_allocator.io.req.map(_.fire))) dontTouch(fires_count) (io_in zip input_units ).foreach { case (i,u) => u.io.in <> i } (io_ingress zip ingress_units).foreach { case (i,u) => u.io.in <> i.flit } (output_units zip io_out ).foreach { case (u,o) => o <> u.io.out } (egress_units zip io_egress).foreach { case (u,o) => o.flit <> u.io.out } (route_computer.io.req zip all_input_units).foreach { case (i,u) => i <> u.io.router_req } (all_input_units zip route_computer.io.resp).foreach { case (u,o) => u.io.router_resp <> o } (vc_allocator.io.req zip all_input_units).foreach { case (i,u) => i <> u.io.vcalloc_req } (all_input_units zip vc_allocator.io.resp).foreach { case (u,o) => u.io.vcalloc_resp <> o } (all_output_units zip vc_allocator.io.out_allocs).foreach { case (u,a) => u.io.allocs <> a } (vc_allocator.io.channel_status zip all_output_units).foreach { case (a,u) => a := u.io.channel_status } all_input_units.foreach(in => all_output_units.zipWithIndex.foreach { case (out,outIdx) => in.io.out_credit_available(outIdx) := out.io.credit_available }) (all_input_units zip switch_allocator.io.req).foreach { case (u,r) => r <> u.io.salloc_req } (all_output_units zip switch_allocator.io.credit_alloc).foreach { case (u,a) => u.io.credit_alloc := a } (switch.io.in zip all_input_units).foreach { case (i,u) => i <> u.io.out } (all_output_units zip switch.io.out).foreach { case (u,o) => u.io.in <> o } switch.io.sel := (if (routerParams.user.combineSAST) { switch_allocator.io.switch_sel } else { RegNext(switch_allocator.io.switch_sel) }) if (hasCtrl) { val io_ctrl = ctrlNode.get.out(0)._1 val ctrl = Module(new RouterControlUnit(routerParams, inParams, outParams, ingressParams, egressParams)) io_ctrl <> ctrl.io.ctrl (all_input_units zip ctrl.io.in_block ).foreach { case (l,r) => l.io.block := r } (all_input_units zip ctrl.io.in_fire ).foreach { case (l,r) => r := l.io.out.map(_.valid) } } else { input_units.foreach(_.io.block := false.B) ingress_units.foreach(_.io.block := false.B) } (io_debug.va_stall zip all_input_units.map(_.io.debug.va_stall)).map { case (l,r) => l := r } (io_debug.sa_stall zip all_input_units.map(_.io.debug.sa_stall)).map { case (l,r) => l := r } val debug_tsc = RegInit(0.U(64.W)) debug_tsc := debug_tsc + 1.U val debug_sample = RegInit(0.U(64.W)) debug_sample := debug_sample + 1.U val sample_rate = PlusArg("noc_util_sample_rate", width=20) when (debug_sample === sample_rate - 1.U) { debug_sample := 0.U } def sample(fire: Bool, s: String) = { val util_ctr = RegInit(0.U(64.W)) val fired = RegInit(false.B) util_ctr := util_ctr + fire fired := fired || fire when (sample_rate =/= 0.U && debug_sample === sample_rate - 1.U && fired) { val fmtStr = s"nocsample %d $s %d\n" printf(fmtStr, debug_tsc, util_ctr); fired := fire } } destNodes.map(_.in(0)).foreach { case (in, edge) => in.flit.map { f => sample(f.fire, s"${edge.cp.srcId} $nodeId") } } ingressNodes.map(_.in(0)).foreach { case (in, edge) => sample(in.flit.fire, s"i${edge.cp.asInstanceOf[IngressChannelParams].ingressId} $nodeId") } egressNodes.map(_.out(0)).foreach { case (out, edge) => sample(out.flit.fire, s"$nodeId e${edge.cp.asInstanceOf[EgressChannelParams].egressId}") } } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } }

module Router_24( // @[Router.scala:89:25] input clock, // @[Router.scala:89:25] input reset, // @[Router.scala:89:25] output [4:0] auto_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25] output [4:0] auto_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25] output [4:0] auto_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25] output [4:0] auto_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_source_nodes_out_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [5:0] auto_source_nodes_out_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [5:0] auto_source_nodes_out_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [21:0] auto_source_nodes_out_1_credit_return, // @[LazyModuleImp.scala:107:25] input [21:0] auto_source_nodes_out_1_vc_free, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_source_nodes_out_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [5:0] auto_source_nodes_out_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [5:0] auto_source_nodes_out_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [21:0] auto_source_nodes_out_0_credit_return, // @[LazyModuleImp.scala:107:25] input [21:0] auto_source_nodes_out_0_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_dest_nodes_in_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [5:0] auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [5:0] auto_dest_nodes_in_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [21:0] auto_dest_nodes_in_1_credit_return, // @[LazyModuleImp.scala:107:25] output [21:0] auto_dest_nodes_in_1_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_dest_nodes_in_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [5:0] auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [5:0] auto_dest_nodes_in_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [21:0] auto_dest_nodes_in_0_credit_return, // @[LazyModuleImp.scala:107:25] output [21:0] auto_dest_nodes_in_0_vc_free // @[LazyModuleImp.scala:107:25] ); wire [19:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire _route_computer_io_resp_1_vc_sel_1_2; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_1_3; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_1_8; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_1_9; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_1_10; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_1_11; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_1_12; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_1_13; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_1_14; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_1_15; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_1_16; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_1_17; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_1_18; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_1_19; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_1_20; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_8; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_9; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_12; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_13; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_20; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_21; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_3; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_19; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_20; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_21; // @[Router.scala:136:32] wire _vc_allocator_io_req_1_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_0_ready; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_1_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_1_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_1_8; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_1_9; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_1_10; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_1_11; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_1_12; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_1_13; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_1_14; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_1_15; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_1_16; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_1_17; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_1_18; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_1_19; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_1_20; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_8; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_9; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_12; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_13; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_20; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_21; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_19; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_20; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_21; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_2_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_3_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_8_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_9_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_10_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_11_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_12_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_13_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_14_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_15_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_16_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_17_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_18_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_19_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_20_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_21_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_8_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_9_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_12_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_13_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_20_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_21_alloc; // @[Router.scala:133:30] wire _switch_allocator_io_req_1_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_0_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_2_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_3_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_8_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_9_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_10_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_11_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_12_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_13_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_14_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_15_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_16_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_17_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_18_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_19_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_20_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_21_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_8_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_9_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_12_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_13_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_20_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_21_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_0_0; // @[Router.scala:132:34] wire _switch_io_out_1_0_valid; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_1_0_bits_payload; // @[Router.scala:131:24] wire [3:0] _switch_io_out_1_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [5:0] _switch_io_out_1_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [2:0] _switch_io_out_1_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [5:0] _switch_io_out_1_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [2:0] _switch_io_out_1_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_1_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _switch_io_out_0_0_valid; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_0_0_bits_payload; // @[Router.scala:131:24] wire [3:0] _switch_io_out_0_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [5:0] _switch_io_out_0_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [2:0] _switch_io_out_0_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [5:0] _switch_io_out_0_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [2:0] _switch_io_out_0_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_0_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _output_unit_1_to_20_io_credit_available_2; // @[Router.scala:122:13] wire _output_unit_1_to_20_io_credit_available_3; // @[Router.scala:122:13] wire _output_unit_1_to_20_io_credit_available_8; // @[Router.scala:122:13] wire _output_unit_1_to_20_io_credit_available_9; // @[Router.scala:122:13] wire _output_unit_1_to_20_io_credit_available_10; // @[Router.scala:122:13] wire _output_unit_1_to_20_io_credit_available_11; // @[Router.scala:122:13] wire _output_unit_1_to_20_io_credit_available_12; // @[Router.scala:122:13] wire _output_unit_1_to_20_io_credit_available_13; // @[Router.scala:122:13] wire _output_unit_1_to_20_io_credit_available_14; // @[Router.scala:122:13] wire _output_unit_1_to_20_io_credit_available_15; // @[Router.scala:122:13] wire _output_unit_1_to_20_io_credit_available_16; // @[Router.scala:122:13] wire _output_unit_1_to_20_io_credit_available_17; // @[Router.scala:122:13] wire _output_unit_1_to_20_io_credit_available_18; // @[Router.scala:122:13] wire _output_unit_1_to_20_io_credit_available_19; // @[Router.scala:122:13] wire _output_unit_1_to_20_io_credit_available_20; // @[Router.scala:122:13] wire _output_unit_1_to_20_io_credit_available_21; // @[Router.scala:122:13] wire _output_unit_1_to_20_io_channel_status_2_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_20_io_channel_status_3_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_20_io_channel_status_8_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_20_io_channel_status_9_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_20_io_channel_status_10_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_20_io_channel_status_11_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_20_io_channel_status_12_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_20_io_channel_status_13_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_20_io_channel_status_14_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_20_io_channel_status_15_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_20_io_channel_status_16_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_20_io_channel_status_17_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_20_io_channel_status_18_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_20_io_channel_status_19_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_20_io_channel_status_20_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_20_io_channel_status_21_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_9_io_credit_available_8; // @[Router.scala:122:13] wire _output_unit_0_to_9_io_credit_available_9; // @[Router.scala:122:13] wire _output_unit_0_to_9_io_credit_available_12; // @[Router.scala:122:13] wire _output_unit_0_to_9_io_credit_available_13; // @[Router.scala:122:13] wire _output_unit_0_to_9_io_credit_available_20; // @[Router.scala:122:13] wire _output_unit_0_to_9_io_credit_available_21; // @[Router.scala:122:13] wire _output_unit_0_to_9_io_channel_status_8_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_9_io_channel_status_9_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_9_io_channel_status_12_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_9_io_channel_status_13_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_9_io_channel_status_20_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_9_io_channel_status_21_occupied; // @[Router.scala:122:13] wire [4:0] _input_unit_1_from_28_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire [3:0] _input_unit_1_from_28_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [5:0] _input_unit_1_from_28_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_28_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [5:0] _input_unit_1_from_28_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_28_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_vcalloc_req_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_vcalloc_req_bits_vc_sel_1_3; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_vcalloc_req_bits_vc_sel_1_8; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_vcalloc_req_bits_vc_sel_1_9; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_vcalloc_req_bits_vc_sel_1_10; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_vcalloc_req_bits_vc_sel_1_11; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_vcalloc_req_bits_vc_sel_1_12; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_vcalloc_req_bits_vc_sel_1_13; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_vcalloc_req_bits_vc_sel_1_14; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_vcalloc_req_bits_vc_sel_1_15; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_vcalloc_req_bits_vc_sel_1_16; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_vcalloc_req_bits_vc_sel_1_17; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_vcalloc_req_bits_vc_sel_1_18; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_vcalloc_req_bits_vc_sel_1_19; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_vcalloc_req_bits_vc_sel_1_20; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_vcalloc_req_bits_vc_sel_0_8; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_vcalloc_req_bits_vc_sel_0_9; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_vcalloc_req_bits_vc_sel_0_12; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_vcalloc_req_bits_vc_sel_0_13; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_vcalloc_req_bits_vc_sel_0_20; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_vcalloc_req_bits_vc_sel_0_21; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_salloc_req_0_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_salloc_req_0_bits_vc_sel_1_3; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_salloc_req_0_bits_vc_sel_1_8; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_salloc_req_0_bits_vc_sel_1_9; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_salloc_req_0_bits_vc_sel_1_10; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_salloc_req_0_bits_vc_sel_1_11; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_salloc_req_0_bits_vc_sel_1_12; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_salloc_req_0_bits_vc_sel_1_13; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_salloc_req_0_bits_vc_sel_1_14; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_salloc_req_0_bits_vc_sel_1_15; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_salloc_req_0_bits_vc_sel_1_16; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_salloc_req_0_bits_vc_sel_1_17; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_salloc_req_0_bits_vc_sel_1_18; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_salloc_req_0_bits_vc_sel_1_19; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_salloc_req_0_bits_vc_sel_1_20; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_salloc_req_0_bits_vc_sel_1_21; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_salloc_req_0_bits_vc_sel_0_8; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_salloc_req_0_bits_vc_sel_0_9; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_salloc_req_0_bits_vc_sel_0_10; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_salloc_req_0_bits_vc_sel_0_11; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_salloc_req_0_bits_vc_sel_0_12; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_salloc_req_0_bits_vc_sel_0_13; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_salloc_req_0_bits_vc_sel_0_14; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_salloc_req_0_bits_vc_sel_0_15; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_salloc_req_0_bits_vc_sel_0_16; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_salloc_req_0_bits_vc_sel_0_17; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_salloc_req_0_bits_vc_sel_0_18; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_salloc_req_0_bits_vc_sel_0_19; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_salloc_req_0_bits_vc_sel_0_20; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_salloc_req_0_bits_vc_sel_0_21; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_1_from_28_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [72:0] _input_unit_1_from_28_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [3:0] _input_unit_1_from_28_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [5:0] _input_unit_1_from_28_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_28_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [5:0] _input_unit_1_from_28_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_28_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_1_from_28_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [4:0] _input_unit_0_from_9_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_9_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [5:0] _input_unit_0_from_9_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_9_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [5:0] _input_unit_0_from_9_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_9_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_vcalloc_req_bits_vc_sel_1_3; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_vcalloc_req_bits_vc_sel_1_19; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_vcalloc_req_bits_vc_sel_1_20; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_vcalloc_req_bits_vc_sel_1_21; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_salloc_req_0_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_salloc_req_0_bits_vc_sel_1_3; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_salloc_req_0_bits_vc_sel_1_8; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_salloc_req_0_bits_vc_sel_1_9; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_salloc_req_0_bits_vc_sel_1_10; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_salloc_req_0_bits_vc_sel_1_11; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_salloc_req_0_bits_vc_sel_1_12; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_salloc_req_0_bits_vc_sel_1_13; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_salloc_req_0_bits_vc_sel_1_14; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_salloc_req_0_bits_vc_sel_1_15; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_salloc_req_0_bits_vc_sel_1_16; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_salloc_req_0_bits_vc_sel_1_17; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_salloc_req_0_bits_vc_sel_1_18; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_salloc_req_0_bits_vc_sel_1_19; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_salloc_req_0_bits_vc_sel_1_20; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_salloc_req_0_bits_vc_sel_1_21; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_salloc_req_0_bits_vc_sel_0_8; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_salloc_req_0_bits_vc_sel_0_9; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_salloc_req_0_bits_vc_sel_0_10; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_salloc_req_0_bits_vc_sel_0_11; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_salloc_req_0_bits_vc_sel_0_12; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_salloc_req_0_bits_vc_sel_0_13; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_salloc_req_0_bits_vc_sel_0_14; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_salloc_req_0_bits_vc_sel_0_15; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_salloc_req_0_bits_vc_sel_0_16; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_salloc_req_0_bits_vc_sel_0_17; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_salloc_req_0_bits_vc_sel_0_18; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_salloc_req_0_bits_vc_sel_0_19; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_salloc_req_0_bits_vc_sel_0_20; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_salloc_req_0_bits_vc_sel_0_21; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_0_from_9_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [72:0] _input_unit_0_from_9_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_9_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [5:0] _input_unit_0_from_9_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_9_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [5:0] _input_unit_0_from_9_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_9_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_0_from_9_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [1:0] fires_count = {1'h0, _vc_allocator_io_req_0_ready & _input_unit_0_from_9_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_1_ready & _input_unit_1_from_28_io_vcalloc_req_valid}; // @[Decoupled.scala:51:35] reg REG_1_0_1_0; // @[Router.scala:178:14] reg REG_1_0_0_0; // @[Router.scala:178:14] reg REG_0_0_1_0; // @[Router.scala:178:14] reg REG_0_0_0_0; // @[Router.scala:178:14] reg [63:0] debug_tsc; // @[Router.scala:195:28] reg [63:0] debug_sample; // @[Router.scala:197:31] wire _GEN = debug_sample == {44'h0, _plusarg_reader_out - 20'h1}; // @[PlusArg.scala:80:11] reg [63:0] util_ctr; // @[Router.scala:203:29] reg fired; // @[Router.scala:204:26] wire _GEN_0 = (|_plusarg_reader_out) & _GEN; // @[PlusArg.scala:80:11] wire _GEN_1 = _GEN_0 & fired; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_1; // @[Router.scala:203:29] reg fired_1; // @[Router.scala:204:26] wire _GEN_2 = _GEN_0 & fired_1; // @[Router.scala:204:26, :207:{33,71}]

Generate the Verilog code corresponding to the following Chisel files. File decode.scala: //****************************************************************************** // Copyright (c) 2015 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ package boom.v3.exu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket.Instructions32 import freechips.rocketchip.rocket.CustomInstructions._ import freechips.rocketchip.rocket.RVCExpander import freechips.rocketchip.rocket.{CSR,Causes} import freechips.rocketchip.util.{uintToBitPat,UIntIsOneOf} import FUConstants._ import boom.v3.common._ import boom.v3.util._ // scalastyle:off /** * Abstract trait giving defaults and other relevant values to different Decode constants/ */ abstract trait DecodeConstants extends freechips.rocketchip.rocket.constants.ScalarOpConstants with freechips.rocketchip.rocket.constants.MemoryOpConstants { val xpr64 = Y // TODO inform this from xLen val DC2 = BitPat.dontCare(2) // Makes the listing below more readable def decode_default: List[BitPat] = // frs3_en wakeup_delay // is val inst? | imm sel | bypassable (aka, known/fixed latency) // | is fp inst? | | uses_ldq | | is_br // | | is single-prec? rs1 regtype | | | uses_stq | | | // | | | micro-code | rs2 type| | | | is_amo | | | // | | | | iq-type func unit | | | | | | | is_fence | | | // | | | | | | | | | | | | | | is_fencei | | | is breakpoint or ecall? // | | | | | | dst | | | | | | | | | mem | | | | is unique? (clear pipeline for it) // | | | | | | regtype | | | | | | | | | cmd | | | | | flush on commit // | | | | | | | | | | | | | | | | | | | | | | | csr cmd // | | | | | | | | | | | | | | | | | | | | | | | | List(N, N, X, uopX , IQT_INT, FU_X , RT_X , DC2 ,DC2 ,X, IS_X, X, X, X, X, N, M_X, DC2, X, X, N, N, X, CSR.X) val table: Array[(BitPat, List[BitPat])] } // scalastyle:on /** * Decoded control signals */ class CtrlSigs extends Bundle { val legal = Bool() val fp_val = Bool() val fp_single = Bool() val uopc = UInt(UOPC_SZ.W) val iq_type = UInt(IQT_SZ.W) val fu_code = UInt(FUC_SZ.W) val dst_type = UInt(2.W) val rs1_type = UInt(2.W) val rs2_type = UInt(2.W) val frs3_en = Bool() val imm_sel = UInt(IS_X.getWidth.W) val uses_ldq = Bool() val uses_stq = Bool() val is_amo = Bool() val is_fence = Bool() val is_fencei = Bool() val mem_cmd = UInt(freechips.rocketchip.rocket.M_SZ.W) val wakeup_delay = UInt(2.W) val bypassable = Bool() val is_br = Bool() val is_sys_pc2epc = Bool() val inst_unique = Bool() val flush_on_commit = Bool() val csr_cmd = UInt(freechips.rocketchip.rocket.CSR.SZ.W) val rocc = Bool() def decode(inst: UInt, table: Iterable[(BitPat, List[BitPat])]) = { val decoder = freechips.rocketchip.rocket.DecodeLogic(inst, XDecode.decode_default, table) val sigs = Seq(legal, fp_val, fp_single, uopc, iq_type, fu_code, dst_type, rs1_type, rs2_type, frs3_en, imm_sel, uses_ldq, uses_stq, is_amo, is_fence, is_fencei, mem_cmd, wakeup_delay, bypassable, is_br, is_sys_pc2epc, inst_unique, flush_on_commit, csr_cmd) sigs zip decoder map {case(s,d) => s := d} rocc := false.B this } } // scalastyle:off /** * Decode constants for RV32 */ object X32Decode extends DecodeConstants { // frs3_en wakeup_delay // is val inst? | imm sel | bypassable (aka, known/fixed latency) // | is fp inst? | | uses_ldq | | is_br // | | is single-prec? rs1 regtype | | | uses_stq | | | // | | | micro-code | rs2 type| | | | is_amo | | | // | | | | iq-type func unit | | | | | | | is_fence | | | // | | | | | | | | | | | | | | is_fencei | | | is breakpoint or ecall? // | | | | | | dst | | | | | | | | | mem | | | | is unique? (clear pipeline for it) // | | | | | | regtype | | | | | | | | | cmd | | | | | flush on commit // | | | | | | | | | | | | | | | | | | | | | | | csr cmd val table: Array[(BitPat, List[BitPat])] = Array(// | | | | | | | | | | | | | | | | | | Instructions32.SLLI -> List(Y, N, X, uopSLLI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), Instructions32.SRLI -> List(Y, N, X, uopSRLI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), Instructions32.SRAI -> List(Y, N, X, uopSRAI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N) ) } /** * Decode constants for RV64 */ object X64Decode extends DecodeConstants { // frs3_en wakeup_delay // is val inst? | imm sel | bypassable (aka, known/fixed latency) // | is fp inst? | | uses_ldq | | is_br // | | is single-prec? rs1 regtype | | | uses_stq | | | // | | | micro-code | rs2 type| | | | is_amo | | | // | | | | iq-type func unit | | | | | | | is_fence | | | // | | | | | | | | | | | | | | is_fencei | | | is breakpoint or ecall? // | | | | | | dst | | | | | | | | | mem | | | | is unique? (clear pipeline for it) // | | | | | | regtype | | | | | | | | | cmd | | | | | flush on commit // | | | | | | | | | | | | | | | | | | | | | | | csr cmd val table: Array[(BitPat, List[BitPat])] = Array(// | | | | | | | | | | | | | | | | | | LD -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM , RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 3.U, N, N, N, N, N, CSR.N), LWU -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM , RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 3.U, N, N, N, N, N, CSR.N), SD -> List(Y, N, X, uopSTA , IQT_MEM, FU_MEM , RT_X , RT_FIX, RT_FIX, N, IS_S, N, Y, N, N, N, M_XWR, 0.U, N, N, N, N, N, CSR.N), SLLI -> List(Y, N, X, uopSLLI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), SRLI -> List(Y, N, X, uopSRLI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), SRAI -> List(Y, N, X, uopSRAI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), ADDIW -> List(Y, N, X, uopADDIW, IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), SLLIW -> List(Y, N, X, uopSLLIW, IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), SRAIW -> List(Y, N, X, uopSRAIW, IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), SRLIW -> List(Y, N, X, uopSRLIW, IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), ADDW -> List(Y, N, X, uopADDW , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), SUBW -> List(Y, N, X, uopSUBW , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), SLLW -> List(Y, N, X, uopSLLW , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), SRAW -> List(Y, N, X, uopSRAW , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), SRLW -> List(Y, N, X, uopSRLW , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N) ) } /** * Overall Decode constants */ object XDecode extends DecodeConstants { // frs3_en wakeup_delay // is val inst? | imm sel | bypassable (aka, known/fixed latency) // | is fp inst? | | uses_ldq | | is_br // | | is single-prec? rs1 regtype | | | uses_stq | | | // | | | micro-code | rs2 type| | | | is_amo | | | // | | | | iq-type func unit | | | | | | | is_fence | | | // | | | | | | | | | | | | | | is_fencei | | | is breakpoint or ecall? // | | | | | | dst | | | | | | | | | mem | | | | is unique? (clear pipeline for it) // | | | | | | regtype | | | | | | | | | cmd | | | | | flush on commit // | | | | | | | | | | | | | | | | | | | | | | | csr cmd val table: Array[(BitPat, List[BitPat])] = Array(// | | | | | | | | | | | | | | | | | | LW -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM , RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 3.U, N, N, N, N, N, CSR.N), LH -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM , RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 3.U, N, N, N, N, N, CSR.N), LHU -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM , RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 3.U, N, N, N, N, N, CSR.N), LB -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM , RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 3.U, N, N, N, N, N, CSR.N), LBU -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM , RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 3.U, N, N, N, N, N, CSR.N), SW -> List(Y, N, X, uopSTA , IQT_MEM, FU_MEM , RT_X , RT_FIX, RT_FIX, N, IS_S, N, Y, N, N, N, M_XWR, 0.U, N, N, N, N, N, CSR.N), SH -> List(Y, N, X, uopSTA , IQT_MEM, FU_MEM , RT_X , RT_FIX, RT_FIX, N, IS_S, N, Y, N, N, N, M_XWR, 0.U, N, N, N, N, N, CSR.N), SB -> List(Y, N, X, uopSTA , IQT_MEM, FU_MEM , RT_X , RT_FIX, RT_FIX, N, IS_S, N, Y, N, N, N, M_XWR, 0.U, N, N, N, N, N, CSR.N), LUI -> List(Y, N, X, uopLUI , IQT_INT, FU_ALU , RT_FIX, RT_X , RT_X , N, IS_U, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), ADDI -> List(Y, N, X, uopADDI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), ANDI -> List(Y, N, X, uopANDI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), ORI -> List(Y, N, X, uopORI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), XORI -> List(Y, N, X, uopXORI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), SLTI -> List(Y, N, X, uopSLTI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), SLTIU -> List(Y, N, X, uopSLTIU, IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), SLL -> List(Y, N, X, uopSLL , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), ADD -> List(Y, N, X, uopADD , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), SUB -> List(Y, N, X, uopSUB , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), SLT -> List(Y, N, X, uopSLT , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), SLTU -> List(Y, N, X, uopSLTU , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), AND -> List(Y, N, X, uopAND , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), OR -> List(Y, N, X, uopOR , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), XOR -> List(Y, N, X, uopXOR , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), SRA -> List(Y, N, X, uopSRA , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), SRL -> List(Y, N, X, uopSRL , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), MUL -> List(Y, N, X, uopMUL , IQT_INT, FU_MUL , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), MULH -> List(Y, N, X, uopMULH , IQT_INT, FU_MUL , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), MULHU -> List(Y, N, X, uopMULHU, IQT_INT, FU_MUL , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), MULHSU -> List(Y, N, X, uopMULHSU,IQT_INT, FU_MUL , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), MULW -> List(Y, N, X, uopMULW , IQT_INT, FU_MUL , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), DIV -> List(Y, N, X, uopDIV , IQT_INT, FU_DIV , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), DIVU -> List(Y, N, X, uopDIVU , IQT_INT, FU_DIV , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), REM -> List(Y, N, X, uopREM , IQT_INT, FU_DIV , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), REMU -> List(Y, N, X, uopREMU , IQT_INT, FU_DIV , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), DIVW -> List(Y, N, X, uopDIVW , IQT_INT, FU_DIV , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), DIVUW -> List(Y, N, X, uopDIVUW, IQT_INT, FU_DIV , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), REMW -> List(Y, N, X, uopREMW , IQT_INT, FU_DIV , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), REMUW -> List(Y, N, X, uopREMUW, IQT_INT, FU_DIV , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), AUIPC -> List(Y, N, X, uopAUIPC, IQT_INT, FU_JMP , RT_FIX, RT_X , RT_X , N, IS_U, N, N, N, N, N, M_X , 1.U, N, N, N, N, N, CSR.N), // use BRU for the PC read JAL -> List(Y, N, X, uopJAL , IQT_INT, FU_JMP , RT_FIX, RT_X , RT_X , N, IS_J, N, N, N, N, N, M_X , 1.U, N, N, N, N, N, CSR.N), JALR -> List(Y, N, X, uopJALR , IQT_INT, FU_JMP , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, N, N, N, N, N, CSR.N), BEQ -> List(Y, N, X, uopBEQ , IQT_INT, FU_ALU , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, N, N, M_X , 0.U, N, Y, N, N, N, CSR.N), BNE -> List(Y, N, X, uopBNE , IQT_INT, FU_ALU , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, N, N, M_X , 0.U, N, Y, N, N, N, CSR.N), BGE -> List(Y, N, X, uopBGE , IQT_INT, FU_ALU , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, N, N, M_X , 0.U, N, Y, N, N, N, CSR.N), BGEU -> List(Y, N, X, uopBGEU , IQT_INT, FU_ALU , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, N, N, M_X , 0.U, N, Y, N, N, N, CSR.N), BLT -> List(Y, N, X, uopBLT , IQT_INT, FU_ALU , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, N, N, M_X , 0.U, N, Y, N, N, N, CSR.N), BLTU -> List(Y, N, X, uopBLTU , IQT_INT, FU_ALU , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, N, N, M_X , 0.U, N, Y, N, N, N, CSR.N), // I-type, the immediate12 holds the CSR register. CSRRW -> List(Y, N, X, uopCSRRW, IQT_INT, FU_CSR , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.W), CSRRS -> List(Y, N, X, uopCSRRS, IQT_INT, FU_CSR , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.S), CSRRC -> List(Y, N, X, uopCSRRC, IQT_INT, FU_CSR , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.C), CSRRWI -> List(Y, N, X, uopCSRRWI,IQT_INT, FU_CSR , RT_FIX, RT_PAS, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.W), CSRRSI -> List(Y, N, X, uopCSRRSI,IQT_INT, FU_CSR , RT_FIX, RT_PAS, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.S), CSRRCI -> List(Y, N, X, uopCSRRCI,IQT_INT, FU_CSR , RT_FIX, RT_PAS, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.C), SFENCE_VMA->List(Y,N, X, uopSFENCE,IQT_MEM, FU_MEM , RT_X , RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N,M_SFENCE,0.U,N, N, N, Y, Y, CSR.N), ECALL -> List(Y, N, X, uopERET ,IQT_INT, FU_CSR , RT_X , RT_X , RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, Y, Y, Y, CSR.I), EBREAK -> List(Y, N, X, uopERET ,IQT_INT, FU_CSR , RT_X , RT_X , RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, Y, Y, Y, CSR.I), SRET -> List(Y, N, X, uopERET ,IQT_INT, FU_CSR , RT_X , RT_X , RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.I), MRET -> List(Y, N, X, uopERET ,IQT_INT, FU_CSR , RT_X , RT_X , RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.I), DRET -> List(Y, N, X, uopERET ,IQT_INT, FU_CSR , RT_X , RT_X , RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.I), WFI -> List(Y, N, X, uopWFI ,IQT_INT, FU_CSR , RT_X , RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.I), FENCE_I -> List(Y, N, X, uopNOP , IQT_INT, FU_X , RT_X , RT_X , RT_X , N, IS_X, N, N, N, N, Y, M_X , 0.U, N, N, N, Y, Y, CSR.N), FENCE -> List(Y, N, X, uopFENCE, IQT_INT, FU_MEM , RT_X , RT_X , RT_X , N, IS_X, N, Y, N, Y, N, M_X , 0.U, N, N, N, Y, Y, CSR.N), // TODO PERF make fence higher performance // currently serializes pipeline // frs3_en wakeup_delay // is val inst? | imm sel | bypassable (aka, known/fixed latency) // | is fp inst? | | uses_ldq | | is_br // | | is single-prec? rs1 regtype | | | uses_stq | | | // | | | micro-code | rs2 type| | | | is_amo | | | // | | | | iq-type func unit | | | | | | | is_fence | | | // | | | | | | | | | | | | | | is_fencei | | | is breakpoint or ecall? // | | | | | | dst | | | | | | | | | mem | | | | is unique? (clear pipeline for it) // | | | | | | regtype | | | | | | | | | cmd | | | | | flush on commit // | | | | | | | | | | | | | | | | | | | | | | | csr cmd // A-type | | | | | | | | | | | | | | | | | | | | | | | | AMOADD_W-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_ADD, 0.U,N, N, N, Y, Y, CSR.N), // TODO make AMOs higherperformance AMOXOR_W-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_XOR, 0.U,N, N, N, Y, Y, CSR.N), AMOSWAP_W->List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_SWAP,0.U,N, N, N, Y, Y, CSR.N), AMOAND_W-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_AND, 0.U,N, N, N, Y, Y, CSR.N), AMOOR_W -> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_OR, 0.U,N, N, N, Y, Y, CSR.N), AMOMIN_W-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_MIN, 0.U,N, N, N, Y, Y, CSR.N), AMOMINU_W->List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_MINU,0.U,N, N, N, Y, Y, CSR.N), AMOMAX_W-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_MAX, 0.U,N, N, N, Y, Y, CSR.N), AMOMAXU_W->List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_MAXU,0.U,N, N, N, Y, Y, CSR.N), AMOADD_D-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_ADD, 0.U,N, N, N, Y, Y, CSR.N), AMOXOR_D-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_XOR, 0.U,N, N, N, Y, Y, CSR.N), AMOSWAP_D->List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_SWAP,0.U,N, N, N, Y, Y, CSR.N), AMOAND_D-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_AND, 0.U,N, N, N, Y, Y, CSR.N), AMOOR_D -> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_OR, 0.U,N, N, N, Y, Y, CSR.N), AMOMIN_D-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_MIN, 0.U,N, N, N, Y, Y, CSR.N), AMOMINU_D->List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_MINU,0.U,N, N, N, Y, Y, CSR.N), AMOMAX_D-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_MAX, 0.U,N, N, N, Y, Y, CSR.N), AMOMAXU_D->List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_MAXU,0.U,N, N, N, Y, Y, CSR.N), LR_W -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_X , N, IS_X, Y, N, N, N, N, M_XLR , 0.U,N, N, N, Y, Y, CSR.N), LR_D -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_X , N, IS_X, Y, N, N, N, N, M_XLR , 0.U,N, N, N, Y, Y, CSR.N), SC_W -> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XSC , 0.U,N, N, N, Y, Y, CSR.N), SC_D -> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XSC , 0.U,N, N, N, Y, Y, CSR.N) ) } /** * FP Decode constants */ object FDecode extends DecodeConstants { val table: Array[(BitPat, List[BitPat])] = Array( // frs3_en wakeup_delay // | imm sel | bypassable (aka, known/fixed latency) // | | uses_ldq | | is_br // is val inst? rs1 regtype | | | uses_stq | | | // | is fp inst? | rs2 type| | | | is_amo | | | // | | is dst single-prec? | | | | | | | is_fence | | | // | | | micro-opcode | | | | | | | | is_fencei | | | is breakpoint or ecall // | | | | iq_type func dst | | | | | | | | | mem | | | | is unique? (clear pipeline for it) // | | | | | unit regtype | | | | | | | | | cmd | | | | | flush on commit // | | | | | | | | | | | | | | | | | | | | | | | csr cmd FLW -> List(Y, Y, Y, uopLD , IQT_MEM, FU_MEM, RT_FLT, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 0.U, N, N, N, N, N, CSR.N), FLD -> List(Y, Y, N, uopLD , IQT_MEM, FU_MEM, RT_FLT, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 0.U, N, N, N, N, N, CSR.N), FSW -> List(Y, Y, Y, uopSTA , IQT_MFP,FU_F2IMEM,RT_X , RT_FIX, RT_FLT, N, IS_S, N, Y, N, N, N, M_XWR, 0.U, N, N, N, N, N, CSR.N), // sort of a lie; broken into two micro-ops FSD -> List(Y, Y, N, uopSTA , IQT_MFP,FU_F2IMEM,RT_X , RT_FIX, RT_FLT, N, IS_S, N, Y, N, N, N, M_XWR, 0.U, N, N, N, N, N, CSR.N), FCLASS_S-> List(Y, Y, Y, uopFCLASS_S,IQT_FP , FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FCLASS_D-> List(Y, Y, N, uopFCLASS_D,IQT_FP , FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FMV_W_X -> List(Y, Y, Y, uopFMV_W_X, IQT_INT, FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FMV_D_X -> List(Y, Y, N, uopFMV_D_X, IQT_INT, FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FMV_X_W -> List(Y, Y, Y, uopFMV_X_W, IQT_FP , FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FMV_X_D -> List(Y, Y, N, uopFMV_X_D, IQT_FP , FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FSGNJ_S -> List(Y, Y, Y, uopFSGNJ_S, IQT_FP , FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FSGNJ_D -> List(Y, Y, N, uopFSGNJ_D, IQT_FP , FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FSGNJX_S-> List(Y, Y, Y, uopFSGNJ_S, IQT_FP , FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FSGNJX_D-> List(Y, Y, N, uopFSGNJ_D, IQT_FP , FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FSGNJN_S-> List(Y, Y, Y, uopFSGNJ_S, IQT_FP , FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FSGNJN_D-> List(Y, Y, N, uopFSGNJ_D, IQT_FP , FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), // FP to FP FCVT_S_D-> List(Y, Y, Y, uopFCVT_S_D,IQT_FP , FU_FPU, RT_FLT, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FCVT_D_S-> List(Y, Y, N, uopFCVT_D_S,IQT_FP , FU_FPU, RT_FLT, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), // Int to FP FCVT_S_W-> List(Y, Y, Y, uopFCVT_S_X, IQT_INT,FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FCVT_S_WU->List(Y, Y, Y, uopFCVT_S_X, IQT_INT,FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FCVT_S_L-> List(Y, Y, Y, uopFCVT_S_X, IQT_INT,FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FCVT_S_LU->List(Y, Y, Y, uopFCVT_S_X, IQT_INT,FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FCVT_D_W-> List(Y, Y, N, uopFCVT_D_X, IQT_INT,FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FCVT_D_WU->List(Y, Y, N, uopFCVT_D_X, IQT_INT,FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FCVT_D_L-> List(Y, Y, N, uopFCVT_D_X, IQT_INT,FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FCVT_D_LU->List(Y, Y, N, uopFCVT_D_X, IQT_INT,FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), // FP to Int FCVT_W_S-> List(Y, Y, Y, uopFCVT_X_S, IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FCVT_WU_S->List(Y, Y, Y, uopFCVT_X_S, IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FCVT_L_S-> List(Y, Y, Y, uopFCVT_X_S, IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FCVT_LU_S->List(Y, Y, Y, uopFCVT_X_S, IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FCVT_W_D-> List(Y, Y, N, uopFCVT_X_D, IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FCVT_WU_D->List(Y, Y, N, uopFCVT_X_D, IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FCVT_L_D-> List(Y, Y, N, uopFCVT_X_D, IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FCVT_LU_D->List(Y, Y, N, uopFCVT_X_D, IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), // "fp_single" is used for wb_data formatting (and debugging) FEQ_S ->List(Y, Y, Y, uopCMPR_S , IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FLT_S ->List(Y, Y, Y, uopCMPR_S , IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FLE_S ->List(Y, Y, Y, uopCMPR_S , IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FEQ_D ->List(Y, Y, N, uopCMPR_D , IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FLT_D ->List(Y, Y, N, uopCMPR_D , IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FLE_D ->List(Y, Y, N, uopCMPR_D , IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FMIN_S ->List(Y, Y, Y,uopFMINMAX_S,IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FMAX_S ->List(Y, Y, Y,uopFMINMAX_S,IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FMIN_D ->List(Y, Y, N,uopFMINMAX_D,IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FMAX_D ->List(Y, Y, N,uopFMINMAX_D,IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FADD_S ->List(Y, Y, Y, uopFADD_S , IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FSUB_S ->List(Y, Y, Y, uopFSUB_S , IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FMUL_S ->List(Y, Y, Y, uopFMUL_S , IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FADD_D ->List(Y, Y, N, uopFADD_D , IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FSUB_D ->List(Y, Y, N, uopFSUB_D , IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FMUL_D ->List(Y, Y, N, uopFMUL_D , IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FMADD_S ->List(Y, Y, Y, uopFMADD_S, IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, Y, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FMSUB_S ->List(Y, Y, Y, uopFMSUB_S, IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, Y, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FNMADD_S ->List(Y, Y, Y, uopFNMADD_S,IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, Y, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FNMSUB_S ->List(Y, Y, Y, uopFNMSUB_S,IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, Y, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FMADD_D ->List(Y, Y, N, uopFMADD_D, IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, Y, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FMSUB_D ->List(Y, Y, N, uopFMSUB_D, IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, Y, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FNMADD_D ->List(Y, Y, N, uopFNMADD_D,IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, Y, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FNMSUB_D ->List(Y, Y, N, uopFNMSUB_D,IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, Y, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N) ) } /** * FP Divide SquareRoot Constants */ object FDivSqrtDecode extends DecodeConstants { val table: Array[(BitPat, List[BitPat])] = Array( // frs3_en wakeup_delay // | imm sel | bypassable (aka, known/fixed latency) // | | uses_ldq | | is_br // is val inst? rs1 regtype | | | uses_stq | | | // | is fp inst? | rs2 type| | | | is_amo | | | // | | is dst single-prec? | | | | | | | is_fence | | | // | | | micro-opcode | | | | | | | | is_fencei | | | is breakpoint or ecall // | | | | iq-type func dst | | | | | | | | | mem | | | | is unique? (clear pipeline for it) // | | | | | unit regtype | | | | | | | | | cmd | | | | | flush on commit // | | | | | | | | | | | | | | | | | | | | | | | csr cmd FDIV_S ->List(Y, Y, Y, uopFDIV_S , IQT_FP, FU_FDV, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FDIV_D ->List(Y, Y, N, uopFDIV_D , IQT_FP, FU_FDV, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FSQRT_S ->List(Y, Y, Y, uopFSQRT_S, IQT_FP, FU_FDV, RT_FLT, RT_FLT, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FSQRT_D ->List(Y, Y, N, uopFSQRT_D, IQT_FP, FU_FDV, RT_FLT, RT_FLT, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N) ) } //scalastyle:on /** * RoCC initial decode */ object RoCCDecode extends DecodeConstants { // Note: We use FU_CSR since CSR instructions cannot co-execute with RoCC instructions // frs3_en wakeup_delay // is val inst? | imm sel | bypassable (aka, known/fixed latency) // | is fp inst? | | uses_ldq | | is_br // | | is single-prec rs1 regtype | | | uses_stq | | | // | | | | rs2 type| | | | is_amo | | | // | | | micro-code func unit | | | | | | | is_fence | | | // | | | | iq-type | | | | | | | | | is_fencei | | | is breakpoint or ecall? // | | | | | | dst | | | | | | | | | mem | | | | is unique? (clear pipeline for it) // | | | | | | regtype | | | | | | | | | cmd | | | | | flush on commit // | | | | | | | | | | | | | | | | | | | | | | | csr cmd // | | | | | | | | | | | | | | | | | | | | | | | | val table: Array[(BitPat, List[BitPat])] = Array(// | | | | | | | | | | | | | | | | | | | CUSTOM0 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM0_RS1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_FIX, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM0_RS1_RS2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM0_RD ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM0_RD_RS1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_FIX, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM0_RD_RS1_RS2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM1_RS1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_FIX, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM1_RS1_RS2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM1_RD ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM1_RD_RS1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_FIX, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM1_RD_RS1_RS2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM2_RS1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_FIX, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM2_RS1_RS2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM2_RD ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM2_RD_RS1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_FIX, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM2_RD_RS1_RS2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM3 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM3_RS1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_FIX, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM3_RS1_RS2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM3_RD ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM3_RD_RS1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_FIX, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM3_RD_RS1_RS2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N) ) } /** * IO bundle for the Decode unit */ class DecodeUnitIo(implicit p: Parameters) extends BoomBundle { val enq = new Bundle { val uop = Input(new MicroOp()) } val deq = new Bundle { val uop = Output(new MicroOp()) } // from CSRFile val status = Input(new freechips.rocketchip.rocket.MStatus()) val csr_decode = Flipped(new freechips.rocketchip.rocket.CSRDecodeIO) val interrupt = Input(Bool()) val interrupt_cause = Input(UInt(xLen.W)) } /** * Decode unit that takes in a single instruction and generates a MicroOp. */ class DecodeUnit(implicit p: Parameters) extends BoomModule with freechips.rocketchip.rocket.constants.MemoryOpConstants { val io = IO(new DecodeUnitIo) val uop = Wire(new MicroOp()) uop := io.enq.uop var decode_table = XDecode.table if (usingFPU) decode_table ++= FDecode.table if (usingFPU && usingFDivSqrt) decode_table ++= FDivSqrtDecode.table if (usingRoCC) decode_table ++= RoCCDecode.table decode_table ++= (if (xLen == 64) X64Decode.table else X32Decode.table) val inst = uop.inst val cs = Wire(new CtrlSigs()).decode(inst, decode_table) // Exception Handling io.csr_decode.inst := inst val csr_en = cs.csr_cmd.isOneOf(CSR.S, CSR.C, CSR.W) val csr_ren = cs.csr_cmd.isOneOf(CSR.S, CSR.C) && uop.lrs1 === 0.U val system_insn = cs.csr_cmd === CSR.I val sfence = cs.uopc === uopSFENCE val cs_legal = cs.legal // dontTouch(cs_legal) val id_illegal_insn = !cs_legal || cs.fp_val && io.csr_decode.fp_illegal || // TODO check for illegal rm mode: (io.fpu.illegal_rm) cs.rocc && io.csr_decode.rocc_illegal || cs.is_amo && !io.status.isa('a'-'a') || (cs.fp_val && !cs.fp_single) && !io.status.isa('d'-'a') || csr_en && (io.csr_decode.read_illegal || !csr_ren && io.csr_decode.write_illegal) || ((sfence || system_insn) && io.csr_decode.system_illegal) // cs.div && !csr.io.status.isa('m'-'a') || TODO check for illegal div instructions def checkExceptions(x: Seq[(Bool, UInt)]) = (x.map(_._1).reduce(_||_), PriorityMux(x)) val (xcpt_valid, xcpt_cause) = checkExceptions(List( (io.interrupt && !io.enq.uop.is_sfb, io.interrupt_cause), // Disallow interrupts while we are handling a SFB (uop.bp_debug_if, (CSR.debugTriggerCause).U), (uop.bp_xcpt_if, (Causes.breakpoint).U), (uop.xcpt_pf_if, (Causes.fetch_page_fault).U), (uop.xcpt_ae_if, (Causes.fetch_access).U), (id_illegal_insn, (Causes.illegal_instruction).U))) uop.exception := xcpt_valid uop.exc_cause := xcpt_cause //------------------------------------------------------------- uop.uopc := cs.uopc uop.iq_type := cs.iq_type uop.fu_code := cs.fu_code // x-registers placed in 0-31, f-registers placed in 32-63. // This allows us to straight-up compare register specifiers and not need to // verify the rtypes (e.g., bypassing in rename). uop.ldst := inst(RD_MSB,RD_LSB) uop.lrs1 := inst(RS1_MSB,RS1_LSB) uop.lrs2 := inst(RS2_MSB,RS2_LSB) uop.lrs3 := inst(RS3_MSB,RS3_LSB) uop.ldst_val := cs.dst_type =/= RT_X && !(uop.ldst === 0.U && uop.dst_rtype === RT_FIX) uop.dst_rtype := cs.dst_type uop.lrs1_rtype := cs.rs1_type uop.lrs2_rtype := cs.rs2_type uop.frs3_en := cs.frs3_en uop.ldst_is_rs1 := uop.is_sfb_shadow // SFB optimization when (uop.is_sfb_shadow && cs.rs2_type === RT_X) { uop.lrs2_rtype := RT_FIX uop.lrs2 := inst(RD_MSB,RD_LSB) uop.ldst_is_rs1 := false.B } .elsewhen (uop.is_sfb_shadow && cs.uopc === uopADD && inst(RS1_MSB,RS1_LSB) === 0.U) { uop.uopc := uopMOV uop.lrs1 := inst(RD_MSB, RD_LSB) uop.ldst_is_rs1 := true.B } when (uop.is_sfb_br) { uop.fu_code := FU_JMP } uop.fp_val := cs.fp_val uop.fp_single := cs.fp_single // TODO use this signal instead of the FPU decode's table signal? uop.mem_cmd := cs.mem_cmd uop.mem_size := Mux(cs.mem_cmd.isOneOf(M_SFENCE, M_FLUSH_ALL), Cat(uop.lrs2 =/= 0.U, uop.lrs1 =/= 0.U), inst(13,12)) uop.mem_signed := !inst(14) uop.uses_ldq := cs.uses_ldq uop.uses_stq := cs.uses_stq uop.is_amo := cs.is_amo uop.is_fence := cs.is_fence uop.is_fencei := cs.is_fencei uop.is_sys_pc2epc := cs.is_sys_pc2epc uop.is_unique := cs.inst_unique uop.flush_on_commit := cs.flush_on_commit || (csr_en && !csr_ren && io.csr_decode.write_flush) uop.bypassable := cs.bypassable //------------------------------------------------------------- // immediates // repackage the immediate, and then pass the fewest number of bits around val di24_20 = Mux(cs.imm_sel === IS_B || cs.imm_sel === IS_S, inst(11,7), inst(24,20)) uop.imm_packed := Cat(inst(31,25), di24_20, inst(19,12)) //------------------------------------------------------------- uop.is_br := cs.is_br uop.is_jal := (uop.uopc === uopJAL) uop.is_jalr := (uop.uopc === uopJALR) // uop.is_jump := cs.is_jal || (uop.uopc === uopJALR) // uop.is_ret := (uop.uopc === uopJALR) && // (uop.ldst === X0) && // (uop.lrs1 === RA) // uop.is_call := (uop.uopc === uopJALR || uop.uopc === uopJAL) && // (uop.ldst === RA) //------------------------------------------------------------- io.deq.uop := uop } /** * Smaller Decode unit for the Frontend to decode different * branches. * Accepts EXPANDED RVC instructions */ class BranchDecodeSignals(implicit p: Parameters) extends BoomBundle { val is_ret = Bool() val is_call = Bool() val target = UInt(vaddrBitsExtended.W) val cfi_type = UInt(CFI_SZ.W) // Is this branch a short forwards jump? val sfb_offset = Valid(UInt(log2Ceil(icBlockBytes).W)) // Is this instruction allowed to be inside a sfb? val shadowable = Bool() } class BranchDecode(implicit p: Parameters) extends BoomModule { val io = IO(new Bundle { val inst = Input(UInt(32.W)) val pc = Input(UInt(vaddrBitsExtended.W)) val out = Output(new BranchDecodeSignals) }) val bpd_csignals = freechips.rocketchip.rocket.DecodeLogic(io.inst, List[BitPat](N, N, N, N, X), //// is br? //// | is jal? //// | | is jalr? //// | | | //// | | | shadowable //// | | | | has_rs2 //// | | | | | Array[(BitPat, List[BitPat])]( JAL -> List(N, Y, N, N, X), JALR -> List(N, N, Y, N, X), BEQ -> List(Y, N, N, N, X), BNE -> List(Y, N, N, N, X), BGE -> List(Y, N, N, N, X), BGEU -> List(Y, N, N, N, X), BLT -> List(Y, N, N, N, X), BLTU -> List(Y, N, N, N, X), SLLI -> List(N, N, N, Y, N), SRLI -> List(N, N, N, Y, N), SRAI -> List(N, N, N, Y, N), ADDIW -> List(N, N, N, Y, N), SLLIW -> List(N, N, N, Y, N), SRAIW -> List(N, N, N, Y, N), SRLIW -> List(N, N, N, Y, N), ADDW -> List(N, N, N, Y, Y), SUBW -> List(N, N, N, Y, Y), SLLW -> List(N, N, N, Y, Y), SRAW -> List(N, N, N, Y, Y), SRLW -> List(N, N, N, Y, Y), LUI -> List(N, N, N, Y, N), ADDI -> List(N, N, N, Y, N), ANDI -> List(N, N, N, Y, N), ORI -> List(N, N, N, Y, N), XORI -> List(N, N, N, Y, N), SLTI -> List(N, N, N, Y, N), SLTIU -> List(N, N, N, Y, N), SLL -> List(N, N, N, Y, Y), ADD -> List(N, N, N, Y, Y), SUB -> List(N, N, N, Y, Y), SLT -> List(N, N, N, Y, Y), SLTU -> List(N, N, N, Y, Y), AND -> List(N, N, N, Y, Y), OR -> List(N, N, N, Y, Y), XOR -> List(N, N, N, Y, Y), SRA -> List(N, N, N, Y, Y), SRL -> List(N, N, N, Y, Y) )) val cs_is_br = bpd_csignals(0)(0) val cs_is_jal = bpd_csignals(1)(0) val cs_is_jalr = bpd_csignals(2)(0) val cs_is_shadowable = bpd_csignals(3)(0) val cs_has_rs2 = bpd_csignals(4)(0) io.out.is_call := (cs_is_jal || cs_is_jalr) && GetRd(io.inst) === RA io.out.is_ret := cs_is_jalr && GetRs1(io.inst) === BitPat("b00?01") && GetRd(io.inst) === X0 io.out.target := Mux(cs_is_br, ComputeBranchTarget(io.pc, io.inst, xLen), ComputeJALTarget(io.pc, io.inst, xLen)) io.out.cfi_type := Mux(cs_is_jalr, CFI_JALR, Mux(cs_is_jal, CFI_JAL, Mux(cs_is_br, CFI_BR, CFI_X))) val br_offset = Cat(io.inst(7), io.inst(30,25), io.inst(11,8), 0.U(1.W)) // Is a sfb if it points forwards (offset is positive) io.out.sfb_offset.valid := cs_is_br && !io.inst(31) && br_offset =/= 0.U && (br_offset >> log2Ceil(icBlockBytes)) === 0.U io.out.sfb_offset.bits := br_offset io.out.shadowable := cs_is_shadowable && ( !cs_has_rs2 || (GetRs1(io.inst) === GetRd(io.inst)) || (io.inst === ADD && GetRs1(io.inst) === X0) ) } /** * Track the current "branch mask", and give out the branch mask to each micro-op in Decode * (each micro-op in the machine has a branch mask which says which branches it * is being speculated under). * * @param pl_width pipeline width for the processor */ class BranchMaskGenerationLogic(val pl_width: Int)(implicit p: Parameters) extends BoomModule { val io = IO(new Bundle { // guess if the uop is a branch (we'll catch this later) val is_branch = Input(Vec(pl_width, Bool())) // lock in that it's actually a branch and will fire, so we update // the branch_masks. val will_fire = Input(Vec(pl_width, Bool())) // give out tag immediately (needed in rename) // mask can come later in the cycle val br_tag = Output(Vec(pl_width, UInt(brTagSz.W))) val br_mask = Output(Vec(pl_width, UInt(maxBrCount.W))) // tell decoders the branch mask has filled up, but on the granularity // of an individual micro-op (so some micro-ops can go through) val is_full = Output(Vec(pl_width, Bool())) val brupdate = Input(new BrUpdateInfo()) val flush_pipeline = Input(Bool()) val debug_branch_mask = Output(UInt(maxBrCount.W)) }) val branch_mask = RegInit(0.U(maxBrCount.W)) //------------------------------------------------------------- // Give out the branch tag to each branch micro-op var allocate_mask = branch_mask val tag_masks = Wire(Vec(pl_width, UInt(maxBrCount.W))) for (w <- 0 until pl_width) { // TODO this is a loss of performance as we're blocking branches based on potentially fake branches io.is_full(w) := (allocate_mask === ~(0.U(maxBrCount.W))) && io.is_branch(w) // find br_tag and compute next br_mask val new_br_tag = Wire(UInt(brTagSz.W)) new_br_tag := 0.U tag_masks(w) := 0.U for (i <- maxBrCount-1 to 0 by -1) { when (~allocate_mask(i)) { new_br_tag := i.U tag_masks(w) := (1.U << i.U) } } io.br_tag(w) := new_br_tag allocate_mask = Mux(io.is_branch(w), tag_masks(w) | allocate_mask, allocate_mask) } //------------------------------------------------------------- // Give out the branch mask to each micro-op // (kill off the bits that corresponded to branches that aren't going to fire) var curr_mask = branch_mask for (w <- 0 until pl_width) { io.br_mask(w) := GetNewBrMask(io.brupdate, curr_mask) curr_mask = Mux(io.will_fire(w), tag_masks(w) | curr_mask, curr_mask) } //------------------------------------------------------------- // Update the current branch_mask when (io.flush_pipeline) { branch_mask := 0.U } .otherwise { val mask = Mux(io.brupdate.b2.mispredict, io.brupdate.b2.uop.br_mask, ~(0.U(maxBrCount.W))) branch_mask := GetNewBrMask(io.brupdate, curr_mask) & mask } io.debug_branch_mask := branch_mask } File consts.scala: //****************************************************************************** // Copyright (c) 2011 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Constants //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.common.constants import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util.Str import freechips.rocketchip.rocket.RVCExpander /** * Mixin for issue queue types */ trait IQType { val IQT_SZ = 3 val IQT_INT = 1.U(IQT_SZ.W) val IQT_MEM = 2.U(IQT_SZ.W) val IQT_FP = 4.U(IQT_SZ.W) val IQT_MFP = 6.U(IQT_SZ.W) } /** * Mixin for scalar operation constants */ trait ScalarOpConstants { val X = BitPat("b?") val Y = BitPat("b1") val N = BitPat("b0") //************************************ // Extra Constants // Which branch predictor predicted us val BSRC_SZ = 2 val BSRC_1 = 0.U(BSRC_SZ.W) // 1-cycle branch pred val BSRC_2 = 1.U(BSRC_SZ.W) // 2-cycle branch pred val BSRC_3 = 2.U(BSRC_SZ.W) // 3-cycle branch pred val BSRC_C = 3.U(BSRC_SZ.W) // core branch resolution //************************************ // Control Signals // CFI types val CFI_SZ = 3 val CFI_X = 0.U(CFI_SZ.W) // Not a CFI instruction val CFI_BR = 1.U(CFI_SZ.W) // Branch val CFI_JAL = 2.U(CFI_SZ.W) // JAL val CFI_JALR = 3.U(CFI_SZ.W) // JALR // PC Select Signal val PC_PLUS4 = 0.U(2.W) // PC + 4 val PC_BRJMP = 1.U(2.W) // brjmp_target val PC_JALR = 2.U(2.W) // jump_reg_target // Branch Type val BR_N = 0.U(4.W) // Next val BR_NE = 1.U(4.W) // Branch on NotEqual val BR_EQ = 2.U(4.W) // Branch on Equal val BR_GE = 3.U(4.W) // Branch on Greater/Equal val BR_GEU = 4.U(4.W) // Branch on Greater/Equal Unsigned val BR_LT = 5.U(4.W) // Branch on Less Than val BR_LTU = 6.U(4.W) // Branch on Less Than Unsigned val BR_J = 7.U(4.W) // Jump val BR_JR = 8.U(4.W) // Jump Register // RS1 Operand Select Signal val OP1_RS1 = 0.U(2.W) // Register Source #1 val OP1_ZERO= 1.U(2.W) val OP1_PC = 2.U(2.W) val OP1_X = BitPat("b??") // RS2 Operand Select Signal val OP2_RS2 = 0.U(3.W) // Register Source #2 val OP2_IMM = 1.U(3.W) // immediate val OP2_ZERO= 2.U(3.W) // constant 0 val OP2_NEXT= 3.U(3.W) // constant 2/4 (for PC+2/4) val OP2_IMMC= 4.U(3.W) // for CSR imm found in RS1 val OP2_X = BitPat("b???") // Register File Write Enable Signal val REN_0 = false.B val REN_1 = true.B // Is 32b Word or 64b Doubldword? val SZ_DW = 1 val DW_X = true.B // Bool(xLen==64) val DW_32 = false.B val DW_64 = true.B val DW_XPR = true.B // Bool(xLen==64) // Memory Enable Signal val MEN_0 = false.B val MEN_1 = true.B val MEN_X = false.B // Immediate Extend Select val IS_I = 0.U(3.W) // I-Type (LD,ALU) val IS_S = 1.U(3.W) // S-Type (ST) val IS_B = 2.U(3.W) // SB-Type (BR) val IS_U = 3.U(3.W) // U-Type (LUI/AUIPC) val IS_J = 4.U(3.W) // UJ-Type (J/JAL) val IS_X = BitPat("b???") // Decode Stage Control Signals val RT_FIX = 0.U(2.W) val RT_FLT = 1.U(2.W) val RT_PAS = 3.U(2.W) // pass-through (prs1 := lrs1, etc) val RT_X = 2.U(2.W) // not-a-register (but shouldn't get a busy-bit, etc.) // TODO rename RT_NAR // Micro-op opcodes // TODO change micro-op opcodes into using enum val UOPC_SZ = 7 val uopX = BitPat.dontCare(UOPC_SZ) val uopNOP = 0.U(UOPC_SZ.W) val uopLD = 1.U(UOPC_SZ.W) val uopSTA = 2.U(UOPC_SZ.W) // store address generation val uopSTD = 3.U(UOPC_SZ.W) // store data generation val uopLUI = 4.U(UOPC_SZ.W) val uopADDI = 5.U(UOPC_SZ.W) val uopANDI = 6.U(UOPC_SZ.W) val uopORI = 7.U(UOPC_SZ.W) val uopXORI = 8.U(UOPC_SZ.W) val uopSLTI = 9.U(UOPC_SZ.W) val uopSLTIU= 10.U(UOPC_SZ.W) val uopSLLI = 11.U(UOPC_SZ.W) val uopSRAI = 12.U(UOPC_SZ.W) val uopSRLI = 13.U(UOPC_SZ.W) val uopSLL = 14.U(UOPC_SZ.W) val uopADD = 15.U(UOPC_SZ.W) val uopSUB = 16.U(UOPC_SZ.W) val uopSLT = 17.U(UOPC_SZ.W) val uopSLTU = 18.U(UOPC_SZ.W) val uopAND = 19.U(UOPC_SZ.W) val uopOR = 20.U(UOPC_SZ.W) val uopXOR = 21.U(UOPC_SZ.W) val uopSRA = 22.U(UOPC_SZ.W) val uopSRL = 23.U(UOPC_SZ.W) val uopBEQ = 24.U(UOPC_SZ.W) val uopBNE = 25.U(UOPC_SZ.W) val uopBGE = 26.U(UOPC_SZ.W) val uopBGEU = 27.U(UOPC_SZ.W) val uopBLT = 28.U(UOPC_SZ.W) val uopBLTU = 29.U(UOPC_SZ.W) val uopCSRRW= 30.U(UOPC_SZ.W) val uopCSRRS= 31.U(UOPC_SZ.W) val uopCSRRC= 32.U(UOPC_SZ.W) val uopCSRRWI=33.U(UOPC_SZ.W) val uopCSRRSI=34.U(UOPC_SZ.W) val uopCSRRCI=35.U(UOPC_SZ.W) val uopJ = 36.U(UOPC_SZ.W) val uopJAL = 37.U(UOPC_SZ.W) val uopJALR = 38.U(UOPC_SZ.W) val uopAUIPC= 39.U(UOPC_SZ.W) //val uopSRET = 40.U(UOPC_SZ.W) val uopCFLSH= 41.U(UOPC_SZ.W) val uopFENCE= 42.U(UOPC_SZ.W) val uopADDIW= 43.U(UOPC_SZ.W) val uopADDW = 44.U(UOPC_SZ.W) val uopSUBW = 45.U(UOPC_SZ.W) val uopSLLIW= 46.U(UOPC_SZ.W) val uopSLLW = 47.U(UOPC_SZ.W) val uopSRAIW= 48.U(UOPC_SZ.W) val uopSRAW = 49.U(UOPC_SZ.W) val uopSRLIW= 50.U(UOPC_SZ.W) val uopSRLW = 51.U(UOPC_SZ.W) val uopMUL = 52.U(UOPC_SZ.W) val uopMULH = 53.U(UOPC_SZ.W) val uopMULHU= 54.U(UOPC_SZ.W) val uopMULHSU=55.U(UOPC_SZ.W) val uopMULW = 56.U(UOPC_SZ.W) val uopDIV = 57.U(UOPC_SZ.W) val uopDIVU = 58.U(UOPC_SZ.W) val uopREM = 59.U(UOPC_SZ.W) val uopREMU = 60.U(UOPC_SZ.W) val uopDIVW = 61.U(UOPC_SZ.W) val uopDIVUW= 62.U(UOPC_SZ.W) val uopREMW = 63.U(UOPC_SZ.W) val uopREMUW= 64.U(UOPC_SZ.W) val uopFENCEI = 65.U(UOPC_SZ.W) // = 66.U(UOPC_SZ.W) val uopAMO_AG = 67.U(UOPC_SZ.W) // AMO-address gen (use normal STD for datagen) val uopFMV_W_X = 68.U(UOPC_SZ.W) val uopFMV_D_X = 69.U(UOPC_SZ.W) val uopFMV_X_W = 70.U(UOPC_SZ.W) val uopFMV_X_D = 71.U(UOPC_SZ.W) val uopFSGNJ_S = 72.U(UOPC_SZ.W) val uopFSGNJ_D = 73.U(UOPC_SZ.W) val uopFCVT_S_D = 74.U(UOPC_SZ.W) val uopFCVT_D_S = 75.U(UOPC_SZ.W) val uopFCVT_S_X = 76.U(UOPC_SZ.W) val uopFCVT_D_X = 77.U(UOPC_SZ.W) val uopFCVT_X_S = 78.U(UOPC_SZ.W) val uopFCVT_X_D = 79.U(UOPC_SZ.W) val uopCMPR_S = 80.U(UOPC_SZ.W) val uopCMPR_D = 81.U(UOPC_SZ.W) val uopFCLASS_S = 82.U(UOPC_SZ.W) val uopFCLASS_D = 83.U(UOPC_SZ.W) val uopFMINMAX_S = 84.U(UOPC_SZ.W) val uopFMINMAX_D = 85.U(UOPC_SZ.W) // = 86.U(UOPC_SZ.W) val uopFADD_S = 87.U(UOPC_SZ.W) val uopFSUB_S = 88.U(UOPC_SZ.W) val uopFMUL_S = 89.U(UOPC_SZ.W) val uopFADD_D = 90.U(UOPC_SZ.W) val uopFSUB_D = 91.U(UOPC_SZ.W) val uopFMUL_D = 92.U(UOPC_SZ.W) val uopFMADD_S = 93.U(UOPC_SZ.W) val uopFMSUB_S = 94.U(UOPC_SZ.W) val uopFNMADD_S = 95.U(UOPC_SZ.W) val uopFNMSUB_S = 96.U(UOPC_SZ.W) val uopFMADD_D = 97.U(UOPC_SZ.W) val uopFMSUB_D = 98.U(UOPC_SZ.W) val uopFNMADD_D = 99.U(UOPC_SZ.W) val uopFNMSUB_D = 100.U(UOPC_SZ.W) val uopFDIV_S = 101.U(UOPC_SZ.W) val uopFDIV_D = 102.U(UOPC_SZ.W) val uopFSQRT_S = 103.U(UOPC_SZ.W) val uopFSQRT_D = 104.U(UOPC_SZ.W) val uopWFI = 105.U(UOPC_SZ.W) // pass uop down the CSR pipeline val uopERET = 106.U(UOPC_SZ.W) // pass uop down the CSR pipeline, also is ERET val uopSFENCE = 107.U(UOPC_SZ.W) val uopROCC = 108.U(UOPC_SZ.W) val uopMOV = 109.U(UOPC_SZ.W) // conditional mov decoded from "add rd, x0, rs2" // The Bubble Instruction (Machine generated NOP) // Insert (XOR x0,x0,x0) which is different from software compiler // generated NOPs which are (ADDI x0, x0, 0). // Reasoning for this is to let visualizers and stat-trackers differentiate // between software NOPs and machine-generated Bubbles in the pipeline. val BUBBLE = (0x4033).U(32.W) def NullMicroOp()(implicit p: Parameters): boom.v3.common.MicroOp = { val uop = Wire(new boom.v3.common.MicroOp) uop := DontCare // Overridden in the following lines uop.uopc := uopNOP // maybe not required, but helps on asserts that try to catch spurious behavior uop.bypassable := false.B uop.fp_val := false.B uop.uses_stq := false.B uop.uses_ldq := false.B uop.pdst := 0.U uop.dst_rtype := RT_X val cs = Wire(new boom.v3.common.CtrlSignals()) cs := DontCare // Overridden in the following lines cs.br_type := BR_N cs.csr_cmd := freechips.rocketchip.rocket.CSR.N cs.is_load := false.B cs.is_sta := false.B cs.is_std := false.B uop.ctrl := cs uop } } /** * Mixin for RISCV constants */ trait RISCVConstants { // abstract out instruction decode magic numbers val RD_MSB = 11 val RD_LSB = 7 val RS1_MSB = 19 val RS1_LSB = 15 val RS2_MSB = 24 val RS2_LSB = 20 val RS3_MSB = 31 val RS3_LSB = 27 val CSR_ADDR_MSB = 31 val CSR_ADDR_LSB = 20 val CSR_ADDR_SZ = 12 // location of the fifth bit in the shamt (for checking for illegal ops for SRAIW,etc.) val SHAMT_5_BIT = 25 val LONGEST_IMM_SZ = 20 val X0 = 0.U val RA = 1.U // return address register // memory consistency model // The C/C++ atomics MCM requires that two loads to the same address maintain program order. // The Cortex A9 does NOT enforce load/load ordering (which leads to buggy behavior). val MCM_ORDER_DEPENDENT_LOADS = true val jal_opc = (0x6f).U val jalr_opc = (0x67).U def GetUop(inst: UInt): UInt = inst(6,0) def GetRd (inst: UInt): UInt = inst(RD_MSB,RD_LSB) def GetRs1(inst: UInt): UInt = inst(RS1_MSB,RS1_LSB) def ExpandRVC(inst: UInt)(implicit p: Parameters): UInt = { val rvc_exp = Module(new RVCExpander) rvc_exp.io.in := inst Mux(rvc_exp.io.rvc, rvc_exp.io.out.bits, inst) } // Note: Accepts only EXPANDED rvc instructions def ComputeBranchTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = { val b_imm32 = Cat(Fill(20,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) ((pc.asSInt + b_imm32.asSInt).asSInt & (-2).S).asUInt } // Note: Accepts only EXPANDED rvc instructions def ComputeJALTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = { val j_imm32 = Cat(Fill(12,inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) ((pc.asSInt + j_imm32.asSInt).asSInt & (-2).S).asUInt } // Note: Accepts only EXPANDED rvc instructions def GetCfiType(inst: UInt)(implicit p: Parameters): UInt = { val bdecode = Module(new boom.v3.exu.BranchDecode) bdecode.io.inst := inst bdecode.io.pc := 0.U bdecode.io.out.cfi_type } } /** * Mixin for exception cause constants */ trait ExcCauseConstants { // a memory disambigious misspeculation occurred val MINI_EXCEPTION_MEM_ORDERING = 16.U val MINI_EXCEPTION_CSR_REPLAY = 17.U require (!freechips.rocketchip.rocket.Causes.all.contains(16)) require (!freechips.rocketchip.rocket.Causes.all.contains(17)) }

module BranchDecode_9( // @[decode.scala:623:7] input clock, // @[decode.scala:623:7] input reset, // @[decode.scala:623:7] input [31:0] io_inst, // @[decode.scala:625:14] input [39:0] io_pc, // @[decode.scala:625:14] output io_out_is_ret, // @[decode.scala:625:14] output io_out_is_call, // @[decode.scala:625:14] output [39:0] io_out_target, // @[decode.scala:625:14] output [2:0] io_out_cfi_type, // @[decode.scala:625:14] output io_out_sfb_offset_valid, // @[decode.scala:625:14] output [5:0] io_out_sfb_offset_bits, // @[decode.scala:625:14] output io_out_shadowable // @[decode.scala:625:14] ); wire [31:0] io_inst_0 = io_inst; // @[decode.scala:623:7] wire [39:0] io_pc_0 = io_pc; // @[decode.scala:623:7] wire [31:0] bpd_csignals_decoded_plaInput = io_inst_0; // @[pla.scala:77:22] wire _io_out_is_ret_T_6; // @[decode.scala:695:72] wire [39:0] _io_out_target_T = io_pc_0; // @[decode.scala:623:7] wire [39:0] _io_out_target_T_8 = io_pc_0; // @[decode.scala:623:7] wire _io_out_is_call_T_3; // @[decode.scala:694:47] wire [39:0] _io_out_target_T_16; // @[decode.scala:697:23] wire [2:0] _io_out_cfi_type_T_2; // @[decode.scala:700:8] wire _io_out_sfb_offset_valid_T_7; // @[decode.scala:710:76] wire _io_out_shadowable_T_11; // @[decode.scala:712:41] wire io_out_sfb_offset_valid_0; // @[decode.scala:623:7] wire [5:0] io_out_sfb_offset_bits_0; // @[decode.scala:623:7] wire io_out_is_ret_0; // @[decode.scala:623:7] wire io_out_is_call_0; // @[decode.scala:623:7] wire [39:0] io_out_target_0; // @[decode.scala:623:7] wire [2:0] io_out_cfi_type_0; // @[decode.scala:623:7] wire io_out_shadowable_0; // @[decode.scala:623:7] wire [31:0] bpd_csignals_decoded_invInputs = ~bpd_csignals_decoded_plaInput; // @[pla.scala:77:22, :78:21] wire [4:0] bpd_csignals_decoded_invMatrixOutputs; // @[pla.scala:120:37] wire [4:0] bpd_csignals_decoded; // @[pla.scala:81:23] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_1 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_2 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_3 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_4 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_5 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_6 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_7 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_8 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_9 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_10 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_11 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_12 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_13 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_14 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_15 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_1 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_2 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_3 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_4 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_5 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_6 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_7 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_8 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_9 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_10 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_11 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_12 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_13 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_14 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_15 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_1 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_2 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_3 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_4 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_6 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_9 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_10 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_11 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_12 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_13 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_14 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_15 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_3 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_5 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_6 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_7 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_9 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_11 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_12 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_13 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_1 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_2 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_3 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_4 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_5 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_9 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_10 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_11 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_13 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_14 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_15 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5 = bpd_csignals_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_1 = bpd_csignals_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_9 = bpd_csignals_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_11 = bpd_csignals_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_13 = bpd_csignals_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_1 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_2 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_3 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_4 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_5 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_9 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_10 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_11 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_13 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_14 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_15 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7 = bpd_csignals_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_1 = bpd_csignals_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_2 = bpd_csignals_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_6 = bpd_csignals_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo = {bpd_csignals_decoded_andMatrixOutputs_lo_hi, bpd_csignals_decoded_andMatrixOutputs_lo_lo}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi = {bpd_csignals_decoded_andMatrixOutputs_hi_hi, bpd_csignals_decoded_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53] wire [7:0] _bpd_csignals_decoded_andMatrixOutputs_T = {bpd_csignals_decoded_andMatrixOutputs_hi, bpd_csignals_decoded_andMatrixOutputs_lo}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_5_2 = &_bpd_csignals_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_1 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_2 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_4 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_5 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_4 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_5 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_8 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_7 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_12 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_13 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8 = bpd_csignals_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_1 = bpd_csignals_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_4 = bpd_csignals_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_3 = bpd_csignals_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_1}; // @[pla.scala:91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_1 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_1, bpd_csignals_decoded_andMatrixOutputs_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_1}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_1}; // @[pla.scala:90:45, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_1 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_1}; // @[pla.scala:91:29, :98:53] wire [4:0] bpd_csignals_decoded_andMatrixOutputs_hi_1 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_1, bpd_csignals_decoded_andMatrixOutputs_hi_lo_1}; // @[pla.scala:98:53] wire [8:0] _bpd_csignals_decoded_andMatrixOutputs_T_1 = {bpd_csignals_decoded_andMatrixOutputs_hi_1, bpd_csignals_decoded_andMatrixOutputs_lo_1}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_9_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_1; // @[pla.scala:98:{53,70}] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_2 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_3 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_4 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_5 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_6 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_7 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_8 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_12 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_15 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9 = bpd_csignals_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_3 = bpd_csignals_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_3 = bpd_csignals_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_6 = bpd_csignals_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_7 = bpd_csignals_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_8 = bpd_csignals_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10 = bpd_csignals_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_2 = bpd_csignals_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_2 = bpd_csignals_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_4 = bpd_csignals_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_5 = bpd_csignals_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_5 = bpd_csignals_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_6 = bpd_csignals_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_7 = bpd_csignals_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11 = bpd_csignals_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_1 = bpd_csignals_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_2 = bpd_csignals_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_3 = bpd_csignals_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_4 = bpd_csignals_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_5 = bpd_csignals_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_6 = bpd_csignals_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_7 = bpd_csignals_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12 = bpd_csignals_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_1 = bpd_csignals_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_2 = bpd_csignals_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_3 = bpd_csignals_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_4 = bpd_csignals_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_5 = bpd_csignals_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_6 = bpd_csignals_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_7 = bpd_csignals_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13 = bpd_csignals_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_1 = bpd_csignals_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_2 = bpd_csignals_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_3 = bpd_csignals_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_4 = bpd_csignals_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_5 = bpd_csignals_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_6 = bpd_csignals_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_7 = bpd_csignals_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14 = bpd_csignals_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_1 = bpd_csignals_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_1 = bpd_csignals_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_2 = bpd_csignals_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_3 = bpd_csignals_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_4 = bpd_csignals_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_5 = bpd_csignals_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_6 = bpd_csignals_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13}; // @[pla.scala:91:29, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_2 = {bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9}; // @[pla.scala:91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_2 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo}; // @[pla.scala:98:53] wire [6:0] bpd_csignals_decoded_andMatrixOutputs_lo_2 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_2, bpd_csignals_decoded_andMatrixOutputs_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_2}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_2 = {bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_2}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_2 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_1, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo}; // @[pla.scala:98:53] wire [7:0] bpd_csignals_decoded_andMatrixOutputs_hi_2 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_2, bpd_csignals_decoded_andMatrixOutputs_hi_lo_2}; // @[pla.scala:98:53] wire [14:0] _bpd_csignals_decoded_andMatrixOutputs_T_2 = {bpd_csignals_decoded_andMatrixOutputs_hi_2, bpd_csignals_decoded_andMatrixOutputs_lo_2}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_14_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_2; // @[pla.scala:98:{53,70}] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_1 = bpd_csignals_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_2 = bpd_csignals_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_3 = bpd_csignals_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_4 = bpd_csignals_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_1}; // @[pla.scala:91:29, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_3 = {bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_1}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_1}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_2}; // @[pla.scala:91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_3 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_1, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_1}; // @[pla.scala:98:53] wire [6:0] bpd_csignals_decoded_andMatrixOutputs_lo_3 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_3, bpd_csignals_decoded_andMatrixOutputs_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_3}; // @[pla.scala:90:45, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_3 = {bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_3}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_3}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_2 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_3}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_3 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_2, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_1}; // @[pla.scala:98:53] wire [6:0] bpd_csignals_decoded_andMatrixOutputs_hi_3 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_3, bpd_csignals_decoded_andMatrixOutputs_hi_lo_3}; // @[pla.scala:98:53] wire [13:0] _bpd_csignals_decoded_andMatrixOutputs_T_3 = {bpd_csignals_decoded_andMatrixOutputs_hi_3, bpd_csignals_decoded_andMatrixOutputs_lo_3}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_0_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_3; // @[pla.scala:98:{53,70}] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_2 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_2}; // @[pla.scala:91:29, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_4 = {bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_1}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_2 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_2}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_2 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_2}; // @[pla.scala:91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_4 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_2, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] bpd_csignals_decoded_andMatrixOutputs_lo_4 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_4, bpd_csignals_decoded_andMatrixOutputs_lo_lo_4}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_4}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_2 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_4}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_4 = {bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_2, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_2 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_4}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_3 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_4}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_4 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_3, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_2}; // @[pla.scala:98:53] wire [7:0] bpd_csignals_decoded_andMatrixOutputs_hi_4 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_4, bpd_csignals_decoded_andMatrixOutputs_hi_lo_4}; // @[pla.scala:98:53] wire [14:0] _bpd_csignals_decoded_andMatrixOutputs_T_4 = {bpd_csignals_decoded_andMatrixOutputs_hi_4, bpd_csignals_decoded_andMatrixOutputs_lo_4}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_2_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_4; // @[pla.scala:98:{53,70}] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_5 = bpd_csignals_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_7 = bpd_csignals_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_8 = bpd_csignals_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_5}; // @[pla.scala:90:45, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_5 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_5}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_5}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_5 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_5, bpd_csignals_decoded_andMatrixOutputs_hi_lo_5}; // @[pla.scala:98:53] wire [6:0] _bpd_csignals_decoded_andMatrixOutputs_T_5 = {bpd_csignals_decoded_andMatrixOutputs_hi_5, bpd_csignals_decoded_andMatrixOutputs_lo_5}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_12_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_5; // @[pla.scala:98:{53,70}] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_6 = bpd_csignals_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_7 = bpd_csignals_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_8 = bpd_csignals_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_12 = bpd_csignals_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_6 = bpd_csignals_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_7 = bpd_csignals_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_8 = bpd_csignals_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_12 = bpd_csignals_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_6 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_6, bpd_csignals_decoded_andMatrixOutputs_lo_lo_5}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_6}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_6}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_6 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_6, bpd_csignals_decoded_andMatrixOutputs_hi_lo_6}; // @[pla.scala:98:53] wire [7:0] _bpd_csignals_decoded_andMatrixOutputs_T_6 = {bpd_csignals_decoded_andMatrixOutputs_hi_6, bpd_csignals_decoded_andMatrixOutputs_lo_6}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_6_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_6; // @[pla.scala:98:{53,70}] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_3}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_3 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_7}; // @[pla.scala:90:45, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_7 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_6}; // @[pla.scala:91:29, :98:53] wire [4:0] bpd_csignals_decoded_andMatrixOutputs_lo_7 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_7, bpd_csignals_decoded_andMatrixOutputs_lo_lo_6}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_7 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_7}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_4 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_7}; // @[pla.scala:90:45, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_7 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_7}; // @[pla.scala:90:45, :98:53] wire [4:0] bpd_csignals_decoded_andMatrixOutputs_hi_7 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_7, bpd_csignals_decoded_andMatrixOutputs_hi_lo_7}; // @[pla.scala:98:53] wire [9:0] _bpd_csignals_decoded_andMatrixOutputs_T_7 = {bpd_csignals_decoded_andMatrixOutputs_hi_7, bpd_csignals_decoded_andMatrixOutputs_lo_7}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_15_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_7; // @[pla.scala:98:{53,70}] wire _bpd_csignals_decoded_orMatrixOutputs_T_4 = bpd_csignals_decoded_andMatrixOutputs_15_2; // @[pla.scala:98:70, :114:36] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_8 = bpd_csignals_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_10 = bpd_csignals_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_14 = bpd_csignals_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_8 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_8, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_8 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_8, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_8}; // @[pla.scala:90:45, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_8 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_8, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_8}; // @[pla.scala:90:45, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_8 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_8, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_8}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_8 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_8, bpd_csignals_decoded_andMatrixOutputs_hi_lo_8}; // @[pla.scala:98:53] wire [6:0] _bpd_csignals_decoded_andMatrixOutputs_T_8 = {bpd_csignals_decoded_andMatrixOutputs_hi_8, bpd_csignals_decoded_andMatrixOutputs_lo_8}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_11_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_8; // @[pla.scala:98:{53,70}] wire _bpd_csignals_decoded_orMatrixOutputs_T_5 = bpd_csignals_decoded_andMatrixOutputs_11_2; // @[pla.scala:98:70, :114:36] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_7 = bpd_csignals_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_10 = bpd_csignals_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_11 = bpd_csignals_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_14 = bpd_csignals_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_15 = bpd_csignals_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_3 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_3}; // @[pla.scala:91:29, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_7 = {bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_2}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_3 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_3}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_4 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_4}; // @[pla.scala:91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_9 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_4, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_3}; // @[pla.scala:98:53] wire [6:0] bpd_csignals_decoded_andMatrixOutputs_lo_9 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_9, bpd_csignals_decoded_andMatrixOutputs_lo_lo_7}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_2 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_9, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_3 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_9, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_9 = {bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_3, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_3 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_9, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_9}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_9, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_9}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_9 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_5, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_3}; // @[pla.scala:98:53] wire [7:0] bpd_csignals_decoded_andMatrixOutputs_hi_9 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_9, bpd_csignals_decoded_andMatrixOutputs_hi_lo_9}; // @[pla.scala:98:53] wire [14:0] _bpd_csignals_decoded_andMatrixOutputs_T_9 = {bpd_csignals_decoded_andMatrixOutputs_hi_9, bpd_csignals_decoded_andMatrixOutputs_lo_9}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_3_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_9; // @[pla.scala:98:{53,70}] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_4 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_4}; // @[pla.scala:91:29, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_8 = {bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_3}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_4 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_4}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_5}; // @[pla.scala:91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_10 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_5, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_4}; // @[pla.scala:98:53] wire [6:0] bpd_csignals_decoded_andMatrixOutputs_lo_10 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_10, bpd_csignals_decoded_andMatrixOutputs_lo_lo_8}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_3 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_10, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_4 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_10, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_10 = {bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_4, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_4 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_10, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_10, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_10}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_10 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_6, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_4}; // @[pla.scala:98:53] wire [7:0] bpd_csignals_decoded_andMatrixOutputs_hi_10 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_10, bpd_csignals_decoded_andMatrixOutputs_hi_lo_10}; // @[pla.scala:98:53] wire [14:0] _bpd_csignals_decoded_andMatrixOutputs_T_10 = {bpd_csignals_decoded_andMatrixOutputs_hi_10, bpd_csignals_decoded_andMatrixOutputs_lo_10}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_7_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_10; // @[pla.scala:98:{53,70}] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_9 = bpd_csignals_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_9 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_11, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_11 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_11, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_11 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_11, bpd_csignals_decoded_andMatrixOutputs_lo_lo_9}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_11 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_11, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_11}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_11 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_11, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_11}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_11 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_11, bpd_csignals_decoded_andMatrixOutputs_hi_lo_11}; // @[pla.scala:98:53] wire [7:0] _bpd_csignals_decoded_andMatrixOutputs_T_11 = {bpd_csignals_decoded_andMatrixOutputs_hi_11, bpd_csignals_decoded_andMatrixOutputs_lo_11}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_1_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_11; // @[pla.scala:98:{53,70}] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_10 = bpd_csignals_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_6 = bpd_csignals_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_8 = bpd_csignals_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_9 = bpd_csignals_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_10 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_12, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_10}; // @[pla.scala:90:45, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_12 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_12, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_12 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_12, bpd_csignals_decoded_andMatrixOutputs_lo_lo_10}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_12 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_12, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_12}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_12 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_12, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_12}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_12 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_12, bpd_csignals_decoded_andMatrixOutputs_hi_lo_12}; // @[pla.scala:98:53] wire [7:0] _bpd_csignals_decoded_andMatrixOutputs_T_12 = {bpd_csignals_decoded_andMatrixOutputs_hi_12, bpd_csignals_decoded_andMatrixOutputs_lo_12}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_13_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_12; // @[pla.scala:98:{53,70}] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_5}; // @[pla.scala:91:29, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_11 = {bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_4}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_5}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_13 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_6, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_5}; // @[pla.scala:98:53] wire [6:0] bpd_csignals_decoded_andMatrixOutputs_lo_13 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_13, bpd_csignals_decoded_andMatrixOutputs_lo_lo_11}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_4 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_13, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_13, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_13 = {bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_5, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_4}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_13, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_13}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_7 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_13, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_13}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_13 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_7, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_5}; // @[pla.scala:98:53] wire [7:0] bpd_csignals_decoded_andMatrixOutputs_hi_13 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_13, bpd_csignals_decoded_andMatrixOutputs_hi_lo_13}; // @[pla.scala:98:53] wire [14:0] _bpd_csignals_decoded_andMatrixOutputs_T_13 = {bpd_csignals_decoded_andMatrixOutputs_hi_13, bpd_csignals_decoded_andMatrixOutputs_lo_13}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_4_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_13; // @[pla.scala:98:{53,70}] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_6}; // @[pla.scala:91:29, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_12 = {bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_5}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_6}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_7 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_8, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_14 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_7, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_6}; // @[pla.scala:98:53] wire [6:0] bpd_csignals_decoded_andMatrixOutputs_lo_14 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_14, bpd_csignals_decoded_andMatrixOutputs_lo_lo_12}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_14, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_14, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_14 = {bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_6, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_5}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_14, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_8 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_14, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_14}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_14 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_8, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_6}; // @[pla.scala:98:53] wire [7:0] bpd_csignals_decoded_andMatrixOutputs_hi_14 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_14, bpd_csignals_decoded_andMatrixOutputs_hi_lo_14}; // @[pla.scala:98:53] wire [14:0] _bpd_csignals_decoded_andMatrixOutputs_T_14 = {bpd_csignals_decoded_andMatrixOutputs_hi_14, bpd_csignals_decoded_andMatrixOutputs_lo_14}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_8_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_14; // @[pla.scala:98:{53,70}] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_7 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_7}; // @[pla.scala:91:29, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_13 = {bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_6}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_7 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_7}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_8 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_9, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_15 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_8, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_7}; // @[pla.scala:98:53] wire [6:0] bpd_csignals_decoded_andMatrixOutputs_lo_15 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_15, bpd_csignals_decoded_andMatrixOutputs_lo_lo_13}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_15, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_7 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_15, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_15 = {bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_7, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_6}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_7 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_15, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_9 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_15, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_15}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_15 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_9, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_7}; // @[pla.scala:98:53] wire [7:0] bpd_csignals_decoded_andMatrixOutputs_hi_15 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_15, bpd_csignals_decoded_andMatrixOutputs_hi_lo_15}; // @[pla.scala:98:53] wire [14:0] _bpd_csignals_decoded_andMatrixOutputs_T_15 = {bpd_csignals_decoded_andMatrixOutputs_hi_15, bpd_csignals_decoded_andMatrixOutputs_lo_15}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_10_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_15; // @[pla.scala:98:{53,70}] wire [1:0] bpd_csignals_decoded_orMatrixOutputs_lo = {bpd_csignals_decoded_andMatrixOutputs_2_2, bpd_csignals_decoded_andMatrixOutputs_10_2}; // @[pla.scala:98:70, :114:19] wire [1:0] bpd_csignals_decoded_orMatrixOutputs_hi = {bpd_csignals_decoded_andMatrixOutputs_14_2, bpd_csignals_decoded_andMatrixOutputs_0_2}; // @[pla.scala:98:70, :114:19] wire [3:0] _bpd_csignals_decoded_orMatrixOutputs_T = {bpd_csignals_decoded_orMatrixOutputs_hi, bpd_csignals_decoded_orMatrixOutputs_lo}; // @[pla.scala:114:19] wire _bpd_csignals_decoded_orMatrixOutputs_T_1 = |_bpd_csignals_decoded_orMatrixOutputs_T; // @[pla.scala:114:{19,36}] wire [1:0] bpd_csignals_decoded_orMatrixOutputs_lo_lo = {bpd_csignals_decoded_andMatrixOutputs_8_2, bpd_csignals_decoded_andMatrixOutputs_10_2}; // @[pla.scala:98:70, :114:19] wire [1:0] bpd_csignals_decoded_orMatrixOutputs_lo_hi_hi = {bpd_csignals_decoded_andMatrixOutputs_7_2, bpd_csignals_decoded_andMatrixOutputs_1_2}; // @[pla.scala:98:70, :114:19] wire [2:0] bpd_csignals_decoded_orMatrixOutputs_lo_hi = {bpd_csignals_decoded_orMatrixOutputs_lo_hi_hi, bpd_csignals_decoded_andMatrixOutputs_4_2}; // @[pla.scala:98:70, :114:19] wire [4:0] bpd_csignals_decoded_orMatrixOutputs_lo_1 = {bpd_csignals_decoded_orMatrixOutputs_lo_hi, bpd_csignals_decoded_orMatrixOutputs_lo_lo}; // @[pla.scala:114:19] wire [1:0] bpd_csignals_decoded_orMatrixOutputs_hi_lo_hi = {bpd_csignals_decoded_andMatrixOutputs_0_2, bpd_csignals_decoded_andMatrixOutputs_12_2}; // @[pla.scala:98:70, :114:19] wire [2:0] bpd_csignals_decoded_orMatrixOutputs_hi_lo = {bpd_csignals_decoded_orMatrixOutputs_hi_lo_hi, bpd_csignals_decoded_andMatrixOutputs_3_2}; // @[pla.scala:98:70, :114:19] wire [1:0] bpd_csignals_decoded_orMatrixOutputs_hi_hi_hi = {bpd_csignals_decoded_andMatrixOutputs_5_2, bpd_csignals_decoded_andMatrixOutputs_9_2}; // @[pla.scala:98:70, :114:19] wire [2:0] bpd_csignals_decoded_orMatrixOutputs_hi_hi = {bpd_csignals_decoded_orMatrixOutputs_hi_hi_hi, bpd_csignals_decoded_andMatrixOutputs_14_2}; // @[pla.scala:98:70, :114:19] wire [5:0] bpd_csignals_decoded_orMatrixOutputs_hi_1 = {bpd_csignals_decoded_orMatrixOutputs_hi_hi, bpd_csignals_decoded_orMatrixOutputs_hi_lo}; // @[pla.scala:114:19] wire [10:0] _bpd_csignals_decoded_orMatrixOutputs_T_2 = {bpd_csignals_decoded_orMatrixOutputs_hi_1, bpd_csignals_decoded_orMatrixOutputs_lo_1}; // @[pla.scala:114:19] wire _bpd_csignals_decoded_orMatrixOutputs_T_3 = |_bpd_csignals_decoded_orMatrixOutputs_T_2; // @[pla.scala:114:{19,36}] wire [1:0] _bpd_csignals_decoded_orMatrixOutputs_T_6 = {bpd_csignals_decoded_andMatrixOutputs_6_2, bpd_csignals_decoded_andMatrixOutputs_13_2}; // @[pla.scala:98:70, :114:19] wire _bpd_csignals_decoded_orMatrixOutputs_T_7 = |_bpd_csignals_decoded_orMatrixOutputs_T_6; // @[pla.scala:114:{19,36}] wire [1:0] bpd_csignals_decoded_orMatrixOutputs_lo_2 = {_bpd_csignals_decoded_orMatrixOutputs_T_3, _bpd_csignals_decoded_orMatrixOutputs_T_1}; // @[pla.scala:102:36, :114:36] wire [1:0] bpd_csignals_decoded_orMatrixOutputs_hi_hi_1 = {_bpd_csignals_decoded_orMatrixOutputs_T_7, _bpd_csignals_decoded_orMatrixOutputs_T_5}; // @[pla.scala:102:36, :114:36] wire [2:0] bpd_csignals_decoded_orMatrixOutputs_hi_2 = {bpd_csignals_decoded_orMatrixOutputs_hi_hi_1, _bpd_csignals_decoded_orMatrixOutputs_T_4}; // @[pla.scala:102:36, :114:36] wire [4:0] bpd_csignals_decoded_orMatrixOutputs = {bpd_csignals_decoded_orMatrixOutputs_hi_2, bpd_csignals_decoded_orMatrixOutputs_lo_2}; // @[pla.scala:102:36] wire _bpd_csignals_decoded_invMatrixOutputs_T = bpd_csignals_decoded_orMatrixOutputs[0]; // @[pla.scala:102:36, :124:31] wire _bpd_csignals_decoded_invMatrixOutputs_T_1 = bpd_csignals_decoded_orMatrixOutputs[1]; // @[pla.scala:102:36, :124:31] wire _bpd_csignals_decoded_invMatrixOutputs_T_2 = bpd_csignals_decoded_orMatrixOutputs[2]; // @[pla.scala:102:36, :124:31] wire _bpd_csignals_decoded_invMatrixOutputs_T_3 = bpd_csignals_decoded_orMatrixOutputs[3]; // @[pla.scala:102:36, :124:31] wire _bpd_csignals_decoded_invMatrixOutputs_T_4 = bpd_csignals_decoded_orMatrixOutputs[4]; // @[pla.scala:102:36, :124:31] wire [1:0] bpd_csignals_decoded_invMatrixOutputs_lo = {_bpd_csignals_decoded_invMatrixOutputs_T_1, _bpd_csignals_decoded_invMatrixOutputs_T}; // @[pla.scala:120:37, :124:31] wire [1:0] bpd_csignals_decoded_invMatrixOutputs_hi_hi = {_bpd_csignals_decoded_invMatrixOutputs_T_4, _bpd_csignals_decoded_invMatrixOutputs_T_3}; // @[pla.scala:120:37, :124:31] wire [2:0] bpd_csignals_decoded_invMatrixOutputs_hi = {bpd_csignals_decoded_invMatrixOutputs_hi_hi, _bpd_csignals_decoded_invMatrixOutputs_T_2}; // @[pla.scala:120:37, :124:31] assign bpd_csignals_decoded_invMatrixOutputs = {bpd_csignals_decoded_invMatrixOutputs_hi, bpd_csignals_decoded_invMatrixOutputs_lo}; // @[pla.scala:120:37] assign bpd_csignals_decoded = bpd_csignals_decoded_invMatrixOutputs; // @[pla.scala:81:23, :120:37] wire bpd_csignals_0 = bpd_csignals_decoded[4]; // @[pla.scala:81:23] wire cs_is_br = bpd_csignals_0; // @[Decode.scala:50:77] wire bpd_csignals_1 = bpd_csignals_decoded[3]; // @[pla.scala:81:23] wire cs_is_jal = bpd_csignals_1; // @[Decode.scala:50:77] wire bpd_csignals_2 = bpd_csignals_decoded[2]; // @[pla.scala:81:23] wire cs_is_jalr = bpd_csignals_2; // @[Decode.scala:50:77] wire bpd_csignals_3 = bpd_csignals_decoded[1]; // @[pla.scala:81:23] wire cs_is_shadowable = bpd_csignals_3; // @[Decode.scala:50:77] wire bpd_csignals_4 = bpd_csignals_decoded[0]; // @[pla.scala:81:23] wire cs_has_rs2 = bpd_csignals_4; // @[Decode.scala:50:77] wire _io_out_is_call_T = cs_is_jal | cs_is_jalr; // @[decode.scala:689:34, :690:35, :694:32] wire [4:0] _io_out_is_call_T_1 = io_inst_0[11:7]; // @[decode.scala:623:7] wire [4:0] _io_out_is_ret_T_4 = io_inst_0[11:7]; // @[decode.scala:623:7] wire [4:0] _io_out_shadowable_T_2 = io_inst_0[11:7]; // @[decode.scala:623:7] wire _io_out_is_call_T_2 = _io_out_is_call_T_1 == 5'h1; // @[decode.scala:694:65] assign _io_out_is_call_T_3 = _io_out_is_call_T & _io_out_is_call_T_2; // @[decode.scala:694:{32,47,65}] assign io_out_is_call_0 = _io_out_is_call_T_3; // @[decode.scala:623:7, :694:47] wire [4:0] _io_out_is_ret_T = io_inst_0[19:15]; // @[decode.scala:623:7] wire [4:0] _io_out_shadowable_T_1 = io_inst_0[19:15]; // @[decode.scala:623:7] wire [4:0] _io_out_shadowable_T_7 = io_inst_0[19:15]; // @[decode.scala:623:7] wire [4:0] _io_out_is_ret_T_1 = _io_out_is_ret_T & 5'h1B; // @[decode.scala:695:51] wire _io_out_is_ret_T_2 = _io_out_is_ret_T_1 == 5'h1; // @[decode.scala:695:51] wire _io_out_is_ret_T_3 = cs_is_jalr & _io_out_is_ret_T_2; // @[decode.scala:690:35, :695:{32,51}] wire _io_out_is_ret_T_5 = _io_out_is_ret_T_4 == 5'h0; // @[decode.scala:695:90] assign _io_out_is_ret_T_6 = _io_out_is_ret_T_3 & _io_out_is_ret_T_5; // @[decode.scala:695:{32,72,90}] assign io_out_is_ret_0 = _io_out_is_ret_T_6; // @[decode.scala:623:7, :695:72] wire _io_out_target_b_imm32_T = io_inst_0[31]; // @[decode.scala:623:7] wire _io_out_target_j_imm32_T = io_inst_0[31]; // @[decode.scala:623:7] wire _io_out_sfb_offset_valid_T = io_inst_0[31]; // @[decode.scala:623:7, :710:50] wire [19:0] _io_out_target_b_imm32_T_1 = {20{_io_out_target_b_imm32_T}}; // @[consts.scala:337:{27,35}] wire _io_out_target_b_imm32_T_2 = io_inst_0[7]; // @[decode.scala:623:7] wire _br_offset_T = io_inst_0[7]; // @[decode.scala:623:7, :708:30] wire [5:0] _io_out_target_b_imm32_T_3 = io_inst_0[30:25]; // @[decode.scala:623:7] wire [5:0] _io_out_target_j_imm32_T_4 = io_inst_0[30:25]; // @[decode.scala:623:7] wire [5:0] _br_offset_T_1 = io_inst_0[30:25]; // @[decode.scala:623:7, :708:42] wire [3:0] _io_out_target_b_imm32_T_4 = io_inst_0[11:8]; // @[decode.scala:623:7] wire [3:0] _br_offset_T_2 = io_inst_0[11:8]; // @[decode.scala:623:7, :708:58] wire [4:0] io_out_target_b_imm32_lo = {_io_out_target_b_imm32_T_4, 1'h0}; // @[consts.scala:337:{22,68}] wire [20:0] io_out_target_b_imm32_hi_hi = {_io_out_target_b_imm32_T_1, _io_out_target_b_imm32_T_2}; // @[consts.scala:337:{22,27,46}] wire [26:0] io_out_target_b_imm32_hi = {io_out_target_b_imm32_hi_hi, _io_out_target_b_imm32_T_3}; // @[consts.scala:337:{22,55}] wire [31:0] io_out_target_b_imm32 = {io_out_target_b_imm32_hi, io_out_target_b_imm32_lo}; // @[consts.scala:337:22] wire [31:0] _io_out_target_T_1 = io_out_target_b_imm32; // @[consts.scala:337:22, :338:27] wire [40:0] _io_out_target_T_2 = {_io_out_target_T[39], _io_out_target_T} + {{9{_io_out_target_T_1[31]}}, _io_out_target_T_1}; // @[consts.scala:338:{10,17,27}] wire [39:0] _io_out_target_T_3 = _io_out_target_T_2[39:0]; // @[consts.scala:338:17] wire [39:0] _io_out_target_T_4 = _io_out_target_T_3; // @[consts.scala:338:17] wire [39:0] _io_out_target_T_5 = _io_out_target_T_4 & 40'hFFFFFFFFFE; // @[consts.scala:338:{17,42}] wire [39:0] _io_out_target_T_6 = _io_out_target_T_5; // @[consts.scala:338:42] wire [39:0] _io_out_target_T_7 = _io_out_target_T_6; // @[consts.scala:338:{42,52}] wire [11:0] _io_out_target_j_imm32_T_1 = {12{_io_out_target_j_imm32_T}}; // @[consts.scala:343:{27,35}] wire [7:0] _io_out_target_j_imm32_T_2 = io_inst_0[19:12]; // @[decode.scala:623:7] wire _io_out_target_j_imm32_T_3 = io_inst_0[20]; // @[decode.scala:623:7] wire [3:0] _io_out_target_j_imm32_T_5 = io_inst_0[24:21]; // @[decode.scala:623:7] wire [9:0] io_out_target_j_imm32_lo_hi = {_io_out_target_j_imm32_T_4, _io_out_target_j_imm32_T_5}; // @[consts.scala:343:{22,69,82}] wire [10:0] io_out_target_j_imm32_lo = {io_out_target_j_imm32_lo_hi, 1'h0}; // @[consts.scala:343:22] wire [19:0] io_out_target_j_imm32_hi_hi = {_io_out_target_j_imm32_T_1, _io_out_target_j_imm32_T_2}; // @[consts.scala:343:{22,27,46}] wire [20:0] io_out_target_j_imm32_hi = {io_out_target_j_imm32_hi_hi, _io_out_target_j_imm32_T_3}; // @[consts.scala:343:{22,59}] wire [31:0] io_out_target_j_imm32 = {io_out_target_j_imm32_hi, io_out_target_j_imm32_lo}; // @[consts.scala:343:22] wire [31:0] _io_out_target_T_9 = io_out_target_j_imm32; // @[consts.scala:343:22, :344:27] wire [40:0] _io_out_target_T_10 = {_io_out_target_T_8[39], _io_out_target_T_8} + {{9{_io_out_target_T_9[31]}}, _io_out_target_T_9}; // @[consts.scala:344:{10,17,27}] wire [39:0] _io_out_target_T_11 = _io_out_target_T_10[39:0]; // @[consts.scala:344:17] wire [39:0] _io_out_target_T_12 = _io_out_target_T_11; // @[consts.scala:344:17] wire [39:0] _io_out_target_T_13 = _io_out_target_T_12 & 40'hFFFFFFFFFE; // @[consts.scala:344:{17,42}] wire [39:0] _io_out_target_T_14 = _io_out_target_T_13; // @[consts.scala:344:42] wire [39:0] _io_out_target_T_15 = _io_out_target_T_14; // @[consts.scala:344:{42,52}] assign _io_out_target_T_16 = cs_is_br ? _io_out_target_T_7 : _io_out_target_T_15; // @[decode.scala:688:33, :697:23] assign io_out_target_0 = _io_out_target_T_16; // @[decode.scala:623:7, :697:23] wire [2:0] _io_out_cfi_type_T = {2'h0, cs_is_br}; // @[decode.scala:688:33, :704:8] wire [2:0] _io_out_cfi_type_T_1 = cs_is_jal ? 3'h2 : _io_out_cfi_type_T; // @[decode.scala:689:34, :702:8, :704:8] assign _io_out_cfi_type_T_2 = cs_is_jalr ? 3'h3 : _io_out_cfi_type_T_1; // @[decode.scala:690:35, :700:8, :702:8] assign io_out_cfi_type_0 = _io_out_cfi_type_T_2; // @[decode.scala:623:7, :700:8] wire [4:0] br_offset_lo = {_br_offset_T_2, 1'h0}; // @[decode.scala:708:{22,58}] wire [6:0] br_offset_hi = {_br_offset_T, _br_offset_T_1}; // @[decode.scala:708:{22,30,42}] wire [11:0] br_offset = {br_offset_hi, br_offset_lo}; // @[decode.scala:708:22] wire _io_out_sfb_offset_valid_T_1 = ~_io_out_sfb_offset_valid_T; // @[decode.scala:710:{42,50}] wire _io_out_sfb_offset_valid_T_2 = cs_is_br & _io_out_sfb_offset_valid_T_1; // @[decode.scala:688:33, :710:{39,42}] wire _io_out_sfb_offset_valid_T_3 = |br_offset; // @[decode.scala:708:22, :710:68] wire _io_out_sfb_offset_valid_T_4 = _io_out_sfb_offset_valid_T_2 & _io_out_sfb_offset_valid_T_3; // @[decode.scala:710:{39,55,68}] wire [5:0] _io_out_sfb_offset_valid_T_5 = br_offset[11:6]; // @[decode.scala:708:22, :710:90] wire _io_out_sfb_offset_valid_T_6 = _io_out_sfb_offset_valid_T_5 == 6'h0; // @[decode.scala:710:{90,117}] assign _io_out_sfb_offset_valid_T_7 = _io_out_sfb_offset_valid_T_4 & _io_out_sfb_offset_valid_T_6; // @[decode.scala:710:{55,76,117}] assign io_out_sfb_offset_valid_0 = _io_out_sfb_offset_valid_T_7; // @[decode.scala:623:7, :710:76] assign io_out_sfb_offset_bits_0 = br_offset[5:0]; // @[decode.scala:623:7, :708:22, :711:27] wire _io_out_shadowable_T = ~cs_has_rs2; // @[decode.scala:692:35, :713:5] wire _io_out_shadowable_T_3 = _io_out_shadowable_T_1 == _io_out_shadowable_T_2; // @[decode.scala:714:22] wire _io_out_shadowable_T_4 = _io_out_shadowable_T | _io_out_shadowable_T_3; // @[decode.scala:713:{5,17}, :714:22] wire [31:0] _io_out_shadowable_T_5 = io_inst_0 & 32'hFE00707F; // @[decode.scala:623:7, :715:14] wire _io_out_shadowable_T_6 = _io_out_shadowable_T_5 == 32'h33; // @[decode.scala:715:14] wire _io_out_shadowable_T_8 = _io_out_shadowable_T_7 == 5'h0; // @[decode.scala:695:90, :715:41] wire _io_out_shadowable_T_9 = _io_out_shadowable_T_6 & _io_out_shadowable_T_8; // @[decode.scala:715:{14,22,41}] wire _io_out_shadowable_T_10 = _io_out_shadowable_T_4 | _io_out_shadowable_T_9; // @[decode.scala:713:17, :714:42, :715:22] assign _io_out_shadowable_T_11 = cs_is_shadowable & _io_out_shadowable_T_10; // @[decode.scala:691:41, :712:41, :714:42] assign io_out_shadowable_0 = _io_out_shadowable_T_11; // @[decode.scala:623:7, :712:41] assign io_out_is_ret = io_out_is_ret_0; // @[decode.scala:623:7] assign io_out_is_call = io_out_is_call_0; // @[decode.scala:623:7] assign io_out_target = io_out_target_0; // @[decode.scala:623:7] assign io_out_cfi_type = io_out_cfi_type_0; // @[decode.scala:623:7] assign io_out_sfb_offset_valid = io_out_sfb_offset_valid_0; // @[decode.scala:623:7] assign io_out_sfb_offset_bits = io_out_sfb_offset_bits_0; // @[decode.scala:623:7] assign io_out_shadowable = io_out_shadowable_0; // @[decode.scala:623:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Tile.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ import Util._ /** * A Tile is a purely combinational 2D array of passThrough PEs. * a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs * @param width The data width of each PE in bits * @param rows Number of PEs on each row * @param columns Number of PEs on each column */ class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module { val io = IO(new Bundle { val in_a = Input(Vec(rows, inputType)) val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it val in_d = Input(Vec(columns, outputType)) val in_control = Input(Vec(columns, new PEControl(accType))) val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val in_last = Input(Vec(columns, Bool())) val out_a = Output(Vec(rows, inputType)) val out_c = Output(Vec(columns, outputType)) val out_b = Output(Vec(columns, outputType)) val out_control = Output(Vec(columns, new PEControl(accType))) val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val out_last = Output(Vec(columns, Bool())) val in_valid = Input(Vec(columns, Bool())) val out_valid = Output(Vec(columns, Bool())) val bad_dataflow = Output(Bool()) }) import ev._ val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls))) val tileT = tile.transpose // TODO: abstract hori/vert broadcast, all these connections look the same // Broadcast 'a' horizontally across the Tile for (r <- 0 until rows) { tile(r).foldLeft(io.in_a(r)) { case (in_a, pe) => pe.io.in_a := in_a pe.io.out_a } } // Broadcast 'b' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_b(c)) { case (in_b, pe) => pe.io.in_b := (if (tree_reduction) in_b.zero else in_b) pe.io.out_b } } // Broadcast 'd' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_d(c)) { case (in_d, pe) => pe.io.in_d := in_d pe.io.out_c } } // Broadcast 'control' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_control(c)) { case (in_ctrl, pe) => pe.io.in_control := in_ctrl pe.io.out_control } } // Broadcast 'garbage' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_valid(c)) { case (v, pe) => pe.io.in_valid := v pe.io.out_valid } } // Broadcast 'id' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_id(c)) { case (id, pe) => pe.io.in_id := id pe.io.out_id } } // Broadcast 'last' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_last(c)) { case (last, pe) => pe.io.in_last := last pe.io.out_last } } // Drive the Tile's bottom IO for (c <- 0 until columns) { io.out_c(c) := tile(rows-1)(c).io.out_c io.out_control(c) := tile(rows-1)(c).io.out_control io.out_id(c) := tile(rows-1)(c).io.out_id io.out_last(c) := tile(rows-1)(c).io.out_last io.out_valid(c) := tile(rows-1)(c).io.out_valid io.out_b(c) := { if (tree_reduction) { val prods = tileT(c).map(_.io.out_b) accumulateTree(prods :+ io.in_b(c)) } else { tile(rows - 1)(c).io.out_b } } } io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_||_)).reduce(_||_) // Drive the Tile's right IO for (r <- 0 until rows) { io.out_a(r) := tile(r)(columns-1).io.out_a } }

module Tile_59( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0 // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] PE_315 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Crossing.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.interrupts import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg} @deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2") class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val intnode = IntAdapterNode() lazy val module = new Impl class Impl extends LazyModuleImp(this) { (intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) => out := SynchronizerShiftReg(in, sync) } } } object IntSyncCrossingSource { def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) = { val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered)) intsource.node } } class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule { val node = IntSyncSourceNode(alreadyRegistered) lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl) class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := AsyncResetReg(Cat(in.reverse)).asBools } } class ImplRegistered extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}_Registered" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := in } } } object IntSyncCrossingSink { @deprecated("IntSyncCrossingSink which used the `sync` parameter to determine crossing type is deprecated. Use IntSyncAsyncCrossingSink, IntSyncRationalCrossingSink, or IntSyncSyncCrossingSink instead for > 1, 1, and 0 sync values respectively", "rocket-chip 1.2") def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncAsyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(sync) lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = s"IntSyncAsyncCrossingSink_n${node.out.size}x${node.out.head._1.size}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := SynchronizerShiftReg(in.sync, sync) } } } object IntSyncAsyncCrossingSink { def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncSyncCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(0) lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncSyncCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := in.sync } } } object IntSyncSyncCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncSyncCrossingSink()) intsink.node } } class IntSyncRationalCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(1) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncRationalCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := RegNext(in.sync) } } } object IntSyncRationalCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncRationalCrossingSink()) intsink.node } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File AsyncResetReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ /** This black-boxes an Async Reset * (or Set) * Register. * * Because Chisel doesn't support * parameterized black boxes, * we unfortunately have to * instantiate a number of these. * * We also have to hard-code the set/ * reset behavior. * * Do not confuse an asynchronous * reset signal with an asynchronously * reset reg. You should still * properly synchronize your reset * deassertion. * * @param d Data input * @param q Data Output * @param clk Clock Input * @param rst Reset Input * @param en Write Enable Input * */ class AsyncResetReg(resetValue: Int = 0) extends RawModule { val io = IO(new Bundle { val d = Input(Bool()) val q = Output(Bool()) val en = Input(Bool()) val clk = Input(Clock()) val rst = Input(Reset()) }) val reg = withClockAndReset(io.clk, io.rst.asAsyncReset)(RegInit(resetValue.U(1.W))) when (io.en) { reg := io.d } io.q := reg } class SimpleRegIO(val w: Int) extends Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) } class AsyncResetRegVec(val w: Int, val init: BigInt) extends Module { override def desiredName = s"AsyncResetRegVec_w${w}_i${init}" val io = IO(new SimpleRegIO(w)) val reg = withReset(reset.asAsyncReset)(RegInit(init.U(w.W))) when (io.en) { reg := io.d } io.q := reg } object AsyncResetReg { // Create Single Registers def apply(d: Bool, clk: Clock, rst: Bool, init: Boolean, name: Option[String]): Bool = { val reg = Module(new AsyncResetReg(if (init) 1 else 0)) reg.io.d := d reg.io.clk := clk reg.io.rst := rst reg.io.en := true.B name.foreach(reg.suggestName(_)) reg.io.q } def apply(d: Bool, clk: Clock, rst: Bool): Bool = apply(d, clk, rst, false, None) def apply(d: Bool, clk: Clock, rst: Bool, name: String): Bool = apply(d, clk, rst, false, Some(name)) // Create Vectors of Registers def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: Option[String] = None): UInt = { val w = updateData.getWidth max resetData.bitLength val reg = Module(new AsyncResetRegVec(w, resetData)) name.foreach(reg.suggestName(_)) reg.io.d := updateData reg.io.en := enable reg.io.q } def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: String): UInt = apply(updateData, resetData, enable, Some(name)) def apply(updateData: UInt, resetData: BigInt): UInt = apply(updateData, resetData, enable = true.B) def apply(updateData: UInt, resetData: BigInt, name: String): UInt = apply(updateData, resetData, enable = true.B, Some(name)) def apply(updateData: UInt, enable: Bool): UInt = apply(updateData, resetData=BigInt(0), enable) def apply(updateData: UInt, enable: Bool, name: String): UInt = apply(updateData, resetData = BigInt(0), enable, Some(name)) def apply(updateData: UInt): UInt = apply(updateData, resetData = BigInt(0), enable = true.B) def apply(updateData: UInt, name:String): UInt = apply(updateData, resetData = BigInt(0), enable = true.B, Some(name)) }

module IntSyncCrossingSource_n1x1_36( // @[Crossing.scala:41:9] input clock, // @[Crossing.scala:41:9] input reset, // @[Crossing.scala:41:9] input auto_in_0, // @[LazyModuleImp.scala:107:25] output auto_out_sync_0 // @[LazyModuleImp.scala:107:25] ); wire auto_in_0_0 = auto_in_0; // @[Crossing.scala:41:9] wire nodeIn_0 = auto_in_0_0; // @[Crossing.scala:41:9] wire nodeOut_sync_0; // @[MixedNode.scala:542:17] wire auto_out_sync_0_0; // @[Crossing.scala:41:9] assign auto_out_sync_0_0 = nodeOut_sync_0; // @[Crossing.scala:41:9] AsyncResetRegVec_w1_i0_36 reg_0 ( // @[AsyncResetReg.scala:86:21] .clock (clock), .reset (reset), .io_d (nodeIn_0), // @[MixedNode.scala:551:17] .io_q (nodeOut_sync_0) ); // @[AsyncResetReg.scala:86:21] assign auto_out_sync_0 = auto_out_sync_0_0; // @[Crossing.scala:41:9] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File RegisterRouter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes} import freechips.rocketchip.resources.{Device, Resource, ResourceBindings} import freechips.rocketchip.prci.{NoCrossing} import freechips.rocketchip.regmapper.{RegField, RegMapper, RegMapperParams, RegMapperInput, RegisterRouter} import freechips.rocketchip.util.{BundleField, ControlKey, ElaborationArtefacts, GenRegDescsAnno} import scala.math.min class TLRegisterRouterExtraBundle(val sourceBits: Int, val sizeBits: Int) extends Bundle { val source = UInt((sourceBits max 1).W) val size = UInt((sizeBits max 1).W) } case object TLRegisterRouterExtra extends ControlKey[TLRegisterRouterExtraBundle]("tlrr_extra") case class TLRegisterRouterExtraField(sourceBits: Int, sizeBits: Int) extends BundleField[TLRegisterRouterExtraBundle](TLRegisterRouterExtra, Output(new TLRegisterRouterExtraBundle(sourceBits, sizeBits)), x => { x.size := 0.U x.source := 0.U }) /** TLRegisterNode is a specialized TL SinkNode that encapsulates MMIO registers. * It provides functionality for describing and outputting metdata about the registers in several formats. * It also provides a concrete implementation of a regmap function that will be used * to wire a map of internal registers associated with this node to the node's interconnect port. */ case class TLRegisterNode( address: Seq[AddressSet], device: Device, deviceKey: String = "reg/control", concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false)( implicit valName: ValName) extends SinkNode(TLImp)(Seq(TLSlavePortParameters.v1( Seq(TLSlaveParameters.v1( address = address, resources = Seq(Resource(device, deviceKey)), executable = executable, supportsGet = TransferSizes(1, beatBytes), supportsPutPartial = TransferSizes(1, beatBytes), supportsPutFull = TransferSizes(1, beatBytes), fifoId = Some(0))), // requests are handled in order beatBytes = beatBytes, minLatency = min(concurrency, 1)))) with TLFormatNode // the Queue adds at most one cycle { val size = 1 << log2Ceil(1 + address.map(_.max).max - address.map(_.base).min) require (size >= beatBytes) address.foreach { case a => require (a.widen(size-1).base == address.head.widen(size-1).base, s"TLRegisterNode addresses (${address}) must be aligned to its size ${size}") } // Calling this method causes the matching TL2 bundle to be // configured to route all requests to the listed RegFields. def regmap(mapping: RegField.Map*) = { val (bundleIn, edge) = this.in(0) val a = bundleIn.a val d = bundleIn.d val fields = TLRegisterRouterExtraField(edge.bundle.sourceBits, edge.bundle.sizeBits) +: a.bits.params.echoFields val params = RegMapperParams(log2Up(size/beatBytes), beatBytes, fields) val in = Wire(Decoupled(new RegMapperInput(params))) in.bits.read := a.bits.opcode === TLMessages.Get in.bits.index := edge.addr_hi(a.bits) in.bits.data := a.bits.data in.bits.mask := a.bits.mask Connectable.waiveUnmatched(in.bits.extra, a.bits.echo) match { case (lhs, rhs) => lhs :<= rhs } val a_extra = in.bits.extra(TLRegisterRouterExtra) a_extra.source := a.bits.source a_extra.size := a.bits.size // Invoke the register map builder val out = RegMapper(beatBytes, concurrency, undefZero, in, mapping:_*) // No flow control needed in.valid := a.valid a.ready := in.ready d.valid := out.valid out.ready := d.ready // We must restore the size to enable width adapters to work val d_extra = out.bits.extra(TLRegisterRouterExtra) d.bits := edge.AccessAck(toSource = d_extra.source, lgSize = d_extra.size) // avoid a Mux on the data bus by manually overriding two fields d.bits.data := out.bits.data Connectable.waiveUnmatched(d.bits.echo, out.bits.extra) match { case (lhs, rhs) => lhs :<= rhs } d.bits.opcode := Mux(out.bits.read, TLMessages.AccessAckData, TLMessages.AccessAck) // Tie off unused channels bundleIn.b.valid := false.B bundleIn.c.ready := true.B bundleIn.e.ready := true.B genRegDescsJson(mapping:_*) } def genRegDescsJson(mapping: RegField.Map*): Unit = { // Dump out the register map for documentation purposes. val base = address.head.base val baseHex = s"0x${base.toInt.toHexString}" val name = s"${device.describe(ResourceBindings()).name}.At${baseHex}" val json = GenRegDescsAnno.serialize(base, name, mapping:_*) var suffix = 0 while( ElaborationArtefacts.contains(s"${baseHex}.${suffix}.regmap.json")) { suffix = suffix + 1 } ElaborationArtefacts.add(s"${baseHex}.${suffix}.regmap.json", json) val module = Module.currentModule.get.asInstanceOf[RawModule] GenRegDescsAnno.anno( module, base, mapping:_*) } } /** Mix HasTLControlRegMap into any subclass of RegisterRouter to gain helper functions for attaching a device control register map to TileLink. * - The intended use case is that controlNode will diplomatically publish a SW-visible device's memory-mapped control registers. * - Use the clock crossing helper controlXing to externally connect controlNode to a TileLink interconnect. * - Use the mapping helper function regmap to internally fill out the space of device control registers. */ trait HasTLControlRegMap { this: RegisterRouter => protected val controlNode = TLRegisterNode( address = address, device = device, deviceKey = "reg/control", concurrency = concurrency, beatBytes = beatBytes, undefZero = undefZero, executable = executable) // Externally, this helper should be used to connect the register control port to a bus val controlXing: TLInwardClockCrossingHelper = this.crossIn(controlNode) // Backwards-compatibility default node accessor with no clock crossing lazy val node: TLInwardNode = controlXing(NoCrossing) // Internally, this function should be used to populate the control port with registers protected def regmap(mapping: RegField.Map*): Unit = { controlNode.regmap(mapping:_*) } } File MuxLiteral.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.log2Ceil import scala.reflect.ClassTag /* MuxLiteral creates a lookup table from a key to a list of values. * Unlike MuxLookup, the table keys must be exclusive literals. */ object MuxLiteral { def apply[T <: Data:ClassTag](index: UInt, default: T, first: (UInt, T), rest: (UInt, T)*): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[(UInt, T)]): T = MuxTable(index, default, cases.map { case (k, v) => (k.litValue, v) }) } object MuxSeq { def apply[T <: Data:ClassTag](index: UInt, default: T, first: T, rest: T*): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[T]): T = MuxTable(index, default, cases.zipWithIndex.map { case (v, i) => (BigInt(i), v) }) } object MuxTable { def apply[T <: Data:ClassTag](index: UInt, default: T, first: (BigInt, T), rest: (BigInt, T)*): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[(BigInt, T)]): T = { /* All keys must be >= 0 and distinct */ cases.foreach { case (k, _) => require (k >= 0) } require (cases.map(_._1).distinct.size == cases.size) /* Filter out any cases identical to the default */ val simple = cases.filter { case (k, v) => !default.isLit || !v.isLit || v.litValue != default.litValue } val maxKey = (BigInt(0) +: simple.map(_._1)).max val endIndex = BigInt(1) << log2Ceil(maxKey+1) if (simple.isEmpty) { default } else if (endIndex <= 2*simple.size) { /* The dense encoding case uses a Vec */ val table = Array.fill(endIndex.toInt) { default } simple.foreach { case (k, v) => table(k.toInt) = v } Mux(index >= endIndex.U, default, VecInit(table)(index)) } else { /* The sparse encoding case uses switch */ val out = WireDefault(default) simple.foldLeft(new chisel3.util.SwitchContext(index, None, Set.empty)) { case (acc, (k, v)) => acc.is (k.U) { out := v } } out } } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File Control.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.regmapper._ import freechips.rocketchip.tilelink._ class InclusiveCacheControl(outer: InclusiveCache, control: InclusiveCacheControlParameters)(implicit p: Parameters) extends LazyModule()(p) { val ctrlnode = TLRegisterNode( address = Seq(AddressSet(control.address, InclusiveCacheParameters.L2ControlSize-1)), device = outer.device, concurrency = 1, // Only one flush at a time (else need to track who answers) beatBytes = control.beatBytes) lazy val module = new Impl class Impl extends LazyModuleImp(this) { val io = IO(new Bundle { val flush_match = Input(Bool()) val flush_req = Decoupled(UInt(64.W)) val flush_resp = Input(Bool()) }) // Flush directive val flushInValid = RegInit(false.B) val flushInAddress = Reg(UInt(64.W)) val flushOutValid = RegInit(false.B) val flushOutReady = WireInit(init = false.B) when (flushOutReady) { flushOutValid := false.B } when (io.flush_resp) { flushOutValid := true.B } when (io.flush_req.ready) { flushInValid := false.B } io.flush_req.valid := flushInValid io.flush_req.bits := flushInAddress when (!io.flush_match && flushInValid) { flushInValid := false.B flushOutValid := true.B } val flush32 = RegField.w(32, RegWriteFn((ivalid, oready, data) => { when (oready) { flushOutReady := true.B } when (ivalid) { flushInValid := true.B } when (ivalid && !flushInValid) { flushInAddress := data << 4 } (!flushInValid, flushOutValid) }), RegFieldDesc("Flush32", "Flush the physical address equal to the 32-bit written data << 4 from the cache")) val flush64 = RegField.w(64, RegWriteFn((ivalid, oready, data) => { when (oready) { flushOutReady := true.B } when (ivalid) { flushInValid := true.B } when (ivalid && !flushInValid) { flushInAddress := data } (!flushInValid, flushOutValid) }), RegFieldDesc("Flush64", "Flush the phsyical address equal to the 64-bit written data from the cache")) // Information about the cache configuration val banksR = RegField.r(8, outer.node.edges.in.size.U, RegFieldDesc("Banks", "Number of banks in the cache", reset=Some(outer.node.edges.in.size))) val waysR = RegField.r(8, outer.cache.ways.U, RegFieldDesc("Ways", "Number of ways per bank", reset=Some(outer.cache.ways))) val lgSetsR = RegField.r(8, log2Ceil(outer.cache.sets).U, RegFieldDesc("lgSets", "Base-2 logarithm of the sets per bank", reset=Some(log2Ceil(outer.cache.sets)))) val lgBlockBytesR = RegField.r(8, log2Ceil(outer.cache.blockBytes).U, RegFieldDesc("lgBlockBytes", "Base-2 logarithm of the bytes per cache block", reset=Some(log2Ceil(outer.cache.blockBytes)))) val regmap = ctrlnode.regmap( 0x000 -> RegFieldGroup("Config", Some("Information about the Cache Configuration"), Seq(banksR, waysR, lgSetsR, lgBlockBytesR)), 0x200 -> (if (control.beatBytes >= 8) Seq(flush64) else Nil), 0x240 -> Seq(flush32) ) } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module InclusiveCacheControl( // @[Control.scala:38:9] input clock, // @[Control.scala:38:9] input reset, // @[Control.scala:38:9] output auto_ctrl_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_ctrl_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_ctrl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_ctrl_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_ctrl_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_ctrl_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [25:0] auto_ctrl_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_ctrl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_ctrl_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_ctrl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_ctrl_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_ctrl_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_ctrl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_ctrl_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_ctrl_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_ctrl_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input io_flush_match, // @[Control.scala:39:16] input io_flush_req_ready, // @[Control.scala:39:16] output io_flush_req_valid, // @[Control.scala:39:16] output [63:0] io_flush_req_bits, // @[Control.scala:39:16] input io_flush_resp // @[Control.scala:39:16] ); wire out_bits_read; // @[RegisterRouter.scala:87:24] wire [10:0] out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [8:0] in_bits_index; // @[RegisterRouter.scala:73:18] wire in_bits_read; // @[RegisterRouter.scala:73:18] wire _out_back_front_q_io_deq_valid; // @[RegisterRouter.scala:87:24] wire _out_back_front_q_io_deq_bits_read; // @[RegisterRouter.scala:87:24] wire [8:0] _out_back_front_q_io_deq_bits_index; // @[RegisterRouter.scala:87:24] wire [63:0] _out_back_front_q_io_deq_bits_data; // @[RegisterRouter.scala:87:24] wire [7:0] _out_back_front_q_io_deq_bits_mask; // @[RegisterRouter.scala:87:24] wire auto_ctrl_in_a_valid_0 = auto_ctrl_in_a_valid; // @[Control.scala:38:9] wire [2:0] auto_ctrl_in_a_bits_opcode_0 = auto_ctrl_in_a_bits_opcode; // @[Control.scala:38:9] wire [2:0] auto_ctrl_in_a_bits_param_0 = auto_ctrl_in_a_bits_param; // @[Control.scala:38:9] wire [1:0] auto_ctrl_in_a_bits_size_0 = auto_ctrl_in_a_bits_size; // @[Control.scala:38:9] wire [10:0] auto_ctrl_in_a_bits_source_0 = auto_ctrl_in_a_bits_source; // @[Control.scala:38:9] wire [25:0] auto_ctrl_in_a_bits_address_0 = auto_ctrl_in_a_bits_address; // @[Control.scala:38:9] wire [7:0] auto_ctrl_in_a_bits_mask_0 = auto_ctrl_in_a_bits_mask; // @[Control.scala:38:9] wire [63:0] auto_ctrl_in_a_bits_data_0 = auto_ctrl_in_a_bits_data; // @[Control.scala:38:9] wire auto_ctrl_in_a_bits_corrupt_0 = auto_ctrl_in_a_bits_corrupt; // @[Control.scala:38:9] wire auto_ctrl_in_d_ready_0 = auto_ctrl_in_d_ready; // @[Control.scala:38:9] wire io_flush_match_0 = io_flush_match; // @[Control.scala:38:9] wire io_flush_req_ready_0 = io_flush_req_ready; // @[Control.scala:38:9] wire io_flush_resp_0 = io_flush_resp; // @[Control.scala:38:9] wire [3:0][63:0] _GEN = '{64'h0, 64'h0, 64'h0, 64'h60A0801}; wire [8:0] out_maskMatch = 9'h1B7; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_13 = 8'h1; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_14 = 8'h1; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T = 8'h1; // @[RegisterRouter.scala:87:24] wire [11:0] out_prepend = 12'h801; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_22 = 16'h801; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_23 = 16'h801; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1 = 16'h801; // @[RegisterRouter.scala:87:24] wire [19:0] out_prepend_1 = 20'hA0801; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_31 = 24'hA0801; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_32 = 24'hA0801; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_2 = 24'hA0801; // @[RegisterRouter.scala:87:24] wire [26:0] out_prepend_2 = 27'h60A0801; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_40 = 32'h60A0801; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_41 = 32'h60A0801; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_66 = 32'h0; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_67 = 32'h0; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_1_0 = 64'h60A0801; // @[MuxLiteral.scala:49:48] wire [2:0] ctrlnodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17] wire [63:0] _out_T_53 = 64'h0; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_54 = 64'h0; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_1_1 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_1_2 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_1_3 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] ctrlnodeIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17] wire auto_ctrl_in_d_bits_sink = 1'h0; // @[Control.scala:38:9] wire auto_ctrl_in_d_bits_denied = 1'h0; // @[Control.scala:38:9] wire auto_ctrl_in_d_bits_corrupt = 1'h0; // @[Control.scala:38:9] wire ctrlnodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire ctrlnodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire ctrlnodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire _out_rifireMux_T_8 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_18 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wifireMux_T_9 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_19 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_rofireMux_T_8 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_18 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wofireMux_T_9 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_19 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T_2 = 1'h0; // @[MuxLiteral.scala:49:17] wire ctrlnodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17] wire ctrlnodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17] wire ctrlnodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17] wire [1:0] auto_ctrl_in_d_bits_param = 2'h0; // @[Control.scala:38:9] wire [1:0] ctrlnodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] ctrlnodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17] wire ctrlnodeIn_a_ready; // @[MixedNode.scala:551:17] wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire ctrlnodeIn_a_valid = auto_ctrl_in_a_valid_0; // @[Control.scala:38:9] wire [2:0] ctrlnodeIn_a_bits_opcode = auto_ctrl_in_a_bits_opcode_0; // @[Control.scala:38:9] wire [2:0] ctrlnodeIn_a_bits_param = auto_ctrl_in_a_bits_param_0; // @[Control.scala:38:9] wire [1:0] ctrlnodeIn_a_bits_size = auto_ctrl_in_a_bits_size_0; // @[Control.scala:38:9] wire [10:0] ctrlnodeIn_a_bits_source = auto_ctrl_in_a_bits_source_0; // @[Control.scala:38:9] wire [25:0] ctrlnodeIn_a_bits_address = auto_ctrl_in_a_bits_address_0; // @[Control.scala:38:9] wire [7:0] ctrlnodeIn_a_bits_mask = auto_ctrl_in_a_bits_mask_0; // @[Control.scala:38:9] wire [63:0] ctrlnodeIn_a_bits_data = auto_ctrl_in_a_bits_data_0; // @[Control.scala:38:9] wire ctrlnodeIn_a_bits_corrupt = auto_ctrl_in_a_bits_corrupt_0; // @[Control.scala:38:9] wire ctrlnodeIn_d_ready = auto_ctrl_in_d_ready_0; // @[Control.scala:38:9] wire ctrlnodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] ctrlnodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] ctrlnodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [10:0] ctrlnodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] ctrlnodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire auto_ctrl_in_a_ready_0; // @[Control.scala:38:9] wire [2:0] auto_ctrl_in_d_bits_opcode_0; // @[Control.scala:38:9] wire [1:0] auto_ctrl_in_d_bits_size_0; // @[Control.scala:38:9] wire [10:0] auto_ctrl_in_d_bits_source_0; // @[Control.scala:38:9] wire [63:0] auto_ctrl_in_d_bits_data_0; // @[Control.scala:38:9] wire auto_ctrl_in_d_valid_0; // @[Control.scala:38:9] wire io_flush_req_valid_0; // @[Control.scala:38:9] wire [63:0] io_flush_req_bits_0; // @[Control.scala:38:9] wire in_ready; // @[RegisterRouter.scala:73:18] assign auto_ctrl_in_a_ready_0 = ctrlnodeIn_a_ready; // @[Control.scala:38:9] wire in_valid = ctrlnodeIn_a_valid; // @[RegisterRouter.scala:73:18] wire [1:0] in_bits_extra_tlrr_extra_size = ctrlnodeIn_a_bits_size; // @[RegisterRouter.scala:73:18] wire [10:0] in_bits_extra_tlrr_extra_source = ctrlnodeIn_a_bits_source; // @[RegisterRouter.scala:73:18] wire [7:0] in_bits_mask = ctrlnodeIn_a_bits_mask; // @[RegisterRouter.scala:73:18] wire [63:0] in_bits_data = ctrlnodeIn_a_bits_data; // @[RegisterRouter.scala:73:18] wire out_ready = ctrlnodeIn_d_ready; // @[RegisterRouter.scala:87:24] wire out_valid; // @[RegisterRouter.scala:87:24] assign auto_ctrl_in_d_valid_0 = ctrlnodeIn_d_valid; // @[Control.scala:38:9] assign auto_ctrl_in_d_bits_opcode_0 = ctrlnodeIn_d_bits_opcode; // @[Control.scala:38:9] wire [1:0] ctrlnodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign auto_ctrl_in_d_bits_size_0 = ctrlnodeIn_d_bits_size; // @[Control.scala:38:9] wire [10:0] ctrlnodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign auto_ctrl_in_d_bits_source_0 = ctrlnodeIn_d_bits_source; // @[Control.scala:38:9] wire [63:0] out_bits_data; // @[RegisterRouter.scala:87:24] assign auto_ctrl_in_d_bits_data_0 = ctrlnodeIn_d_bits_data; // @[Control.scala:38:9] reg flushInValid; // @[Control.scala:45:33] assign io_flush_req_valid_0 = flushInValid; // @[Control.scala:38:9, :45:33] reg [63:0] flushInAddress; // @[Control.scala:46:29] assign io_flush_req_bits_0 = flushInAddress; // @[Control.scala:38:9, :46:29] reg flushOutValid; // @[Control.scala:47:33] wire flushOutReady; // @[Control.scala:48:34] wire _out_in_ready_T; // @[RegisterRouter.scala:87:24] assign ctrlnodeIn_a_ready = in_ready; // @[RegisterRouter.scala:73:18] wire _in_bits_read_T; // @[RegisterRouter.scala:74:36] wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24] wire [8:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24] wire [63:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24] wire [7:0] out_front_bits_mask = in_bits_mask; // @[RegisterRouter.scala:73:18, :87:24] wire [10:0] out_front_bits_extra_tlrr_extra_source = in_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24] wire [1:0] out_front_bits_extra_tlrr_extra_size = in_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24] assign _in_bits_read_T = ctrlnodeIn_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36] wire [22:0] _in_bits_index_T = ctrlnodeIn_a_bits_address[25:3]; // @[Edges.scala:192:34] assign in_bits_index = _in_bits_index_T[8:0]; // @[RegisterRouter.scala:73:18, :75:19] wire _out_out_valid_T; // @[RegisterRouter.scala:87:24] assign ctrlnodeIn_d_valid = out_valid; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24] wire _ctrlnodeIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25] assign ctrlnodeIn_d_bits_data = out_bits_data; // @[RegisterRouter.scala:87:24] assign ctrlnodeIn_d_bits_d_source = out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [1:0] out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign ctrlnodeIn_d_bits_d_size = out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] wire _out_front_valid_T; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_42 = out_front_bits_data; // @[RegisterRouter.scala:87:24] wire out_front_ready; // @[RegisterRouter.scala:87:24] wire out_front_valid; // @[RegisterRouter.scala:87:24] wire [8:0] out_findex = out_front_bits_index & 9'h1B7; // @[RegisterRouter.scala:87:24] wire [8:0] out_bindex = _out_back_front_q_io_deq_bits_index & 9'h1B7; // @[RegisterRouter.scala:87:24] wire _GEN_0 = out_findex == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_T; // @[RegisterRouter.scala:87:24] assign _out_T = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_T_2; // @[RegisterRouter.scala:87:24] assign _out_T_2 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_T_4; // @[RegisterRouter.scala:87:24] assign _out_T_4 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _GEN_1 = out_bindex == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_T_1; // @[RegisterRouter.scala:87:24] assign _out_T_1 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_T_3; // @[RegisterRouter.scala:87:24] assign _out_T_3 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_T_5; // @[RegisterRouter.scala:87:24] assign _out_T_5 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_0 = _out_T_1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2 = _out_T_3; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_3 = _out_T_5; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_15; // @[RegisterRouter.scala:87:24] wire out_rivalid_0; // @[RegisterRouter.scala:87:24] wire out_rivalid_1; // @[RegisterRouter.scala:87:24] wire out_rivalid_2; // @[RegisterRouter.scala:87:24] wire out_rivalid_3; // @[RegisterRouter.scala:87:24] wire out_rivalid_4; // @[RegisterRouter.scala:87:24] wire out_rivalid_5; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_16; // @[RegisterRouter.scala:87:24] wire out_wivalid_0; // @[RegisterRouter.scala:87:24] wire out_wivalid_1; // @[RegisterRouter.scala:87:24] wire out_wivalid_2; // @[RegisterRouter.scala:87:24] wire out_wivalid_3; // @[RegisterRouter.scala:87:24] wire out_wivalid_4; // @[RegisterRouter.scala:87:24] wire out_wivalid_5; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_15; // @[RegisterRouter.scala:87:24] wire out_roready_0; // @[RegisterRouter.scala:87:24] wire out_roready_1; // @[RegisterRouter.scala:87:24] wire out_roready_2; // @[RegisterRouter.scala:87:24] wire out_roready_3; // @[RegisterRouter.scala:87:24] wire out_roready_4; // @[RegisterRouter.scala:87:24] wire out_roready_5; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_16; // @[RegisterRouter.scala:87:24] wire out_woready_0; // @[RegisterRouter.scala:87:24] wire out_woready_1; // @[RegisterRouter.scala:87:24] wire out_woready_2; // @[RegisterRouter.scala:87:24] wire out_woready_3; // @[RegisterRouter.scala:87:24] wire out_woready_4; // @[RegisterRouter.scala:87:24] wire out_woready_5; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_8 = {8{_out_frontMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_9 = {8{_out_frontMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_10 = {8{_out_frontMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_11 = {8{_out_frontMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_12 = {8{_out_frontMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_13 = {8{_out_frontMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_14 = {8{_out_frontMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_15 = {8{_out_frontMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_lo = {_out_frontMask_T_9, _out_frontMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_hi = {_out_frontMask_T_11, _out_frontMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_lo = {out_frontMask_lo_hi, out_frontMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_lo = {_out_frontMask_T_13, _out_frontMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_hi = {_out_frontMask_T_15, _out_frontMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_hi = {out_frontMask_hi_hi, out_frontMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_frontMask = {out_frontMask_hi, out_frontMask_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_rimask_T_4 = out_frontMask; // @[RegisterRouter.scala:87:24] wire [63:0] _out_wimask_T_4 = out_frontMask; // @[RegisterRouter.scala:87:24] wire _out_backMask_T = _out_back_front_q_io_deq_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_1 = _out_back_front_q_io_deq_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_2 = _out_back_front_q_io_deq_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_3 = _out_back_front_q_io_deq_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_4 = _out_back_front_q_io_deq_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_5 = _out_back_front_q_io_deq_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_6 = _out_back_front_q_io_deq_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_7 = _out_back_front_q_io_deq_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_8 = {8{_out_backMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_9 = {8{_out_backMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_10 = {8{_out_backMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_11 = {8{_out_backMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_12 = {8{_out_backMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_13 = {8{_out_backMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_14 = {8{_out_backMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_15 = {8{_out_backMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_lo = {_out_backMask_T_9, _out_backMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_hi = {_out_backMask_T_11, _out_backMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_lo = {out_backMask_lo_hi, out_backMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_lo = {_out_backMask_T_13, _out_backMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_hi = {_out_backMask_T_15, _out_backMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_hi = {out_backMask_hi_hi, out_backMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_backMask = {out_backMask_hi, out_backMask_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_romask_T_4 = out_backMask; // @[RegisterRouter.scala:87:24] wire [63:0] _out_womask_T_4 = out_backMask; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire out_rimask = |_out_rimask_T; // @[RegisterRouter.scala:87:24] wire out_wimask = &_out_wimask_T; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire out_romask = |_out_romask_T; // @[RegisterRouter.scala:87:24] wire out_womask = &_out_womask_T; // @[RegisterRouter.scala:87:24] wire out_f_rivalid = out_rivalid_0 & out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_7 = out_f_rivalid; // @[RegisterRouter.scala:87:24] wire out_f_roready = out_roready_0 & out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_8 = out_f_roready; // @[RegisterRouter.scala:87:24] wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala:87:24] wire out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6 = _out_back_front_q_io_deq_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire _out_T_9 = ~out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_10 = ~out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_11 = ~out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_12 = ~out_womask; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire out_rimask_1 = |_out_rimask_T_1; // @[RegisterRouter.scala:87:24] wire out_wimask_1 = &_out_wimask_T_1; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire out_romask_1 = |_out_romask_T_1; // @[RegisterRouter.scala:87:24] wire out_womask_1 = &_out_womask_T_1; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1 = out_rivalid_1 & out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_16 = out_f_rivalid_1; // @[RegisterRouter.scala:87:24] wire out_f_roready_1 = out_roready_1 & out_romask_1; // @[RegisterRouter.scala:87:24] wire _out_T_17 = out_f_roready_1; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1 = out_wivalid_1 & out_wimask_1; // @[RegisterRouter.scala:87:24] wire out_f_woready_1 = out_woready_1 & out_womask_1; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_15 = _out_back_front_q_io_deq_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire _out_T_18 = ~out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_19 = ~out_wimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_20 = ~out_romask_1; // @[RegisterRouter.scala:87:24] wire _out_T_21 = ~out_womask_1; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_2 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_2 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire out_rimask_2 = |_out_rimask_T_2; // @[RegisterRouter.scala:87:24] wire out_wimask_2 = &_out_wimask_T_2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_2 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_2 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire out_romask_2 = |_out_romask_T_2; // @[RegisterRouter.scala:87:24] wire out_womask_2 = &_out_womask_T_2; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_2 = out_rivalid_2 & out_rimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_25 = out_f_rivalid_2; // @[RegisterRouter.scala:87:24] wire out_f_roready_2 = out_roready_2 & out_romask_2; // @[RegisterRouter.scala:87:24] wire _out_T_26 = out_f_roready_2; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_2 = out_wivalid_2 & out_wimask_2; // @[RegisterRouter.scala:87:24] wire out_f_woready_2 = out_woready_2 & out_womask_2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_24 = _out_back_front_q_io_deq_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire _out_T_27 = ~out_rimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_28 = ~out_wimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_29 = ~out_romask_2; // @[RegisterRouter.scala:87:24] wire _out_T_30 = ~out_womask_2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_3 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_3 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire out_rimask_3 = |_out_rimask_T_3; // @[RegisterRouter.scala:87:24] wire out_wimask_3 = &_out_wimask_T_3; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_3 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_3 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire out_romask_3 = |_out_romask_T_3; // @[RegisterRouter.scala:87:24] wire out_womask_3 = &_out_womask_T_3; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_3 = out_rivalid_3 & out_rimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_34 = out_f_rivalid_3; // @[RegisterRouter.scala:87:24] wire out_f_roready_3 = out_roready_3 & out_romask_3; // @[RegisterRouter.scala:87:24] wire _out_T_35 = out_f_roready_3; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_3 = out_wivalid_3 & out_wimask_3; // @[RegisterRouter.scala:87:24] wire out_f_woready_3 = out_woready_3 & out_womask_3; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_33 = _out_back_front_q_io_deq_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire _out_T_36 = ~out_rimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_37 = ~out_wimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_38 = ~out_romask_3; // @[RegisterRouter.scala:87:24] wire _out_T_39 = ~out_womask_3; // @[RegisterRouter.scala:87:24] wire out_rimask_4 = |_out_rimask_T_4; // @[RegisterRouter.scala:87:24] wire out_wimask_4 = &_out_wimask_T_4; // @[RegisterRouter.scala:87:24] wire out_romask_4 = |_out_romask_T_4; // @[RegisterRouter.scala:87:24] wire out_womask_4 = &_out_womask_T_4; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_4 = out_rivalid_4 & out_rimask_4; // @[RegisterRouter.scala:87:24] wire out_f_roready_4 = out_roready_4 & out_romask_4; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_4 = out_wivalid_4 & out_wimask_4; // @[RegisterRouter.scala:87:24] wire out_f_woready_4 = out_woready_4 & out_womask_4; // @[RegisterRouter.scala:87:24] wire _out_T_43 = ~flushInValid; // @[Control.scala:45:33, :71:23] wire _out_T_44 = out_f_wivalid_4 & _out_T_43; // @[RegisterRouter.scala:87:24] wire out_f_wiready = ~flushInValid; // @[Control.scala:45:33, :71:23, :72:8] wire _out_T_45 = out_f_wivalid_4 & out_f_wiready; // @[RegisterRouter.scala:87:24] wire _out_T_46 = flushOutValid & out_f_woready_4; // @[RegisterRouter.scala:87:24] wire _out_T_47 = ~out_rimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_48 = ~out_wimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_49 = out_f_wiready | _out_T_48; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_2 = _out_T_49; // @[RegisterRouter.scala:87:24] wire _out_T_50 = ~out_romask_4; // @[RegisterRouter.scala:87:24] wire _out_T_51 = ~out_womask_4; // @[RegisterRouter.scala:87:24] wire _out_T_52 = flushOutValid | _out_T_51; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_2 = _out_T_52; // @[RegisterRouter.scala:87:24] wire [31:0] _out_rimask_T_5 = out_frontMask[31:0]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_wimask_T_5 = out_frontMask[31:0]; // @[RegisterRouter.scala:87:24] wire out_rimask_5 = |_out_rimask_T_5; // @[RegisterRouter.scala:87:24] wire out_wimask_5 = &_out_wimask_T_5; // @[RegisterRouter.scala:87:24] wire [31:0] _out_romask_T_5 = out_backMask[31:0]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_womask_T_5 = out_backMask[31:0]; // @[RegisterRouter.scala:87:24] wire out_romask_5 = |_out_romask_T_5; // @[RegisterRouter.scala:87:24] wire out_womask_5 = &_out_womask_T_5; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_5 = out_rivalid_5 & out_rimask_5; // @[RegisterRouter.scala:87:24] wire out_f_roready_5 = out_roready_5 & out_romask_5; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_5 = out_wivalid_5 & out_wimask_5; // @[RegisterRouter.scala:87:24] wire out_f_woready_5 = out_woready_5 & out_womask_5; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_55 = out_front_bits_data[31:0]; // @[RegisterRouter.scala:87:24] assign flushOutReady = out_f_woready_5 | out_f_woready_4; // @[RegisterRouter.scala:87:24] wire _out_T_56 = ~flushInValid; // @[Control.scala:45:33, :64:23, :71:23] wire _out_T_57 = out_f_wivalid_5 & _out_T_56; // @[RegisterRouter.scala:87:24] wire [35:0] _out_flushInAddress_T = {_out_T_55, 4'h0}; // @[RegisterRouter.scala:87:24] wire out_f_wiready_1 = ~flushInValid; // @[Control.scala:45:33, :65:8, :71:23] wire _out_T_58 = out_f_wivalid_5 & out_f_wiready_1; // @[RegisterRouter.scala:87:24] wire _out_T_59 = flushOutValid & out_f_woready_5; // @[RegisterRouter.scala:87:24] wire _out_T_60 = ~out_rimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_61 = ~out_wimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_62 = out_f_wiready_1 | _out_T_61; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_3 = _out_T_62; // @[RegisterRouter.scala:87:24] wire _out_T_63 = ~out_romask_5; // @[RegisterRouter.scala:87:24] wire _out_T_64 = ~out_womask_5; // @[RegisterRouter.scala:87:24] wire _out_T_65 = flushOutValid | _out_T_64; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_3 = _out_T_65; // @[RegisterRouter.scala:87:24] wire _out_iindex_T = out_front_bits_index[0]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_1 = out_front_bits_index[1]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_2 = out_front_bits_index[2]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_3 = out_front_bits_index[3]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_4 = out_front_bits_index[4]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_5 = out_front_bits_index[5]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_6 = out_front_bits_index[6]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_7 = out_front_bits_index[7]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_8 = out_front_bits_index[8]; // @[RegisterRouter.scala:87:24] wire [1:0] out_iindex = {_out_iindex_T_6, _out_iindex_T_3}; // @[RegisterRouter.scala:87:24] wire _out_oindex_T = _out_back_front_q_io_deq_bits_index[0]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_1 = _out_back_front_q_io_deq_bits_index[1]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_2 = _out_back_front_q_io_deq_bits_index[2]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_3 = _out_back_front_q_io_deq_bits_index[3]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_4 = _out_back_front_q_io_deq_bits_index[4]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_5 = _out_back_front_q_io_deq_bits_index[5]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_6 = _out_back_front_q_io_deq_bits_index[6]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_7 = _out_back_front_q_io_deq_bits_index[7]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_8 = _out_back_front_q_io_deq_bits_index[8]; // @[RegisterRouter.scala:87:24] wire [1:0] out_oindex = {_out_oindex_T_6, _out_oindex_T_3}; // @[RegisterRouter.scala:87:24] wire [3:0] _out_frontSel_T = 4'h1 << out_iindex; // @[OneHot.scala:58:35] wire out_frontSel_0 = _out_frontSel_T[0]; // @[OneHot.scala:58:35] wire out_frontSel_1 = _out_frontSel_T[1]; // @[OneHot.scala:58:35] wire out_frontSel_2 = _out_frontSel_T[2]; // @[OneHot.scala:58:35] wire out_frontSel_3 = _out_frontSel_T[3]; // @[OneHot.scala:58:35] wire [3:0] _out_backSel_T = 4'h1 << out_oindex; // @[OneHot.scala:58:35] wire out_backSel_0 = _out_backSel_T[0]; // @[OneHot.scala:58:35] wire out_backSel_1 = _out_backSel_T[1]; // @[OneHot.scala:58:35] wire out_backSel_2 = _out_backSel_T[2]; // @[OneHot.scala:58:35] wire out_backSel_3 = _out_backSel_T[3]; // @[OneHot.scala:58:35] wire _GEN_2 = in_valid & out_front_ready; // @[RegisterRouter.scala:73:18, :87:24] wire _out_rifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T = _GEN_2; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T = _GEN_2; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1 = _out_rifireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_2 = _out_rifireMux_T_1 & out_frontSel_0; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_3 = _out_rifireMux_T_2 & _out_T; // @[RegisterRouter.scala:87:24] assign out_rivalid_0 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_1 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_2 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_3 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_4 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_6 = _out_rifireMux_T_1 & out_frontSel_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_7 = _out_rifireMux_T_6; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_10 = _out_rifireMux_T_1 & out_frontSel_2; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_11 = _out_rifireMux_T_10 & _out_T_2; // @[RegisterRouter.scala:87:24] assign out_rivalid_4 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_12 = ~_out_T_2; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_14 = _out_rifireMux_T_1 & out_frontSel_3; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_15 = _out_rifireMux_T_14 & _out_T_4; // @[RegisterRouter.scala:87:24] assign out_rivalid_5 = _out_rifireMux_T_15; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_16 = ~_out_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_2 = _out_wifireMux_T & _out_wifireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_3 = _out_wifireMux_T_2 & out_frontSel_0; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_4 = _out_wifireMux_T_3 & _out_T; // @[RegisterRouter.scala:87:24] assign out_wivalid_0 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_1 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_2 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_3 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_5 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_7 = _out_wifireMux_T_2 & out_frontSel_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_8 = _out_wifireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_11 = _out_wifireMux_T_2 & out_frontSel_2; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_12 = _out_wifireMux_T_11 & _out_T_2; // @[RegisterRouter.scala:87:24] assign out_wivalid_4 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] wire out_wifireMux_all = _out_wifireMux_T_12 & _out_T_49; // @[ReduceOthers.scala:47:21] wire _out_wifireMux_T_13 = ~_out_T_2; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_14 = out_wifireMux_out_2 | _out_wifireMux_T_13; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_WIRE_2 = _out_wifireMux_T_14; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_T_15 = _out_wifireMux_T_2 & out_frontSel_3; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_16 = _out_wifireMux_T_15 & _out_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_5 = _out_wifireMux_T_16; // @[RegisterRouter.scala:87:24] wire out_wifireMux_all_1 = _out_wifireMux_T_16 & _out_T_62; // @[ReduceOthers.scala:47:21] wire _out_wifireMux_T_17 = ~_out_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_18 = out_wifireMux_out_3 | _out_wifireMux_T_17; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_WIRE_3 = _out_wifireMux_T_18; // @[MuxLiteral.scala:49:48] wire [3:0] _GEN_3 = {{_out_wifireMux_WIRE_3}, {_out_wifireMux_WIRE_2}, {1'h1}, {1'h1}}; // @[MuxLiteral.scala:49:{10,48}] wire out_wifireMux = _GEN_3[out_iindex]; // @[MuxLiteral.scala:49:10] wire _GEN_4 = _out_back_front_q_io_deq_valid & out_ready; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T = _GEN_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T = _GEN_4; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1 = _out_rofireMux_T & _out_back_front_q_io_deq_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_2 = _out_rofireMux_T_1 & out_backSel_0; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_3 = _out_rofireMux_T_2 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_roready_0 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_1 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_2 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_3 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_4 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_6 = _out_rofireMux_T_1 & out_backSel_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_7 = _out_rofireMux_T_6; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_10 = _out_rofireMux_T_1 & out_backSel_2; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_11 = _out_rofireMux_T_10 & _out_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_4 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_12 = ~_out_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_14 = _out_rofireMux_T_1 & out_backSel_3; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_15 = _out_rofireMux_T_14 & _out_T_5; // @[RegisterRouter.scala:87:24] assign out_roready_5 = _out_rofireMux_T_15; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_16 = ~_out_T_5; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1 = ~_out_back_front_q_io_deq_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_2 = _out_wofireMux_T & _out_wofireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_3 = _out_wofireMux_T_2 & out_backSel_0; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_4 = _out_wofireMux_T_3 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_woready_0 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_1 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_2 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_3 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_5 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_7 = _out_wofireMux_T_2 & out_backSel_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_8 = _out_wofireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_11 = _out_wofireMux_T_2 & out_backSel_2; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_12 = _out_wofireMux_T_11 & _out_T_3; // @[RegisterRouter.scala:87:24] assign out_woready_4 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] wire out_wofireMux_all = _out_wofireMux_T_12 & _out_T_52; // @[ReduceOthers.scala:47:21] wire _out_wofireMux_T_13 = ~_out_T_3; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_14 = out_wofireMux_out_2 | _out_wofireMux_T_13; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_2 = _out_wofireMux_T_14; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_T_15 = _out_wofireMux_T_2 & out_backSel_3; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_16 = _out_wofireMux_T_15 & _out_T_5; // @[RegisterRouter.scala:87:24] assign out_woready_5 = _out_wofireMux_T_16; // @[RegisterRouter.scala:87:24] wire out_wofireMux_all_1 = _out_wofireMux_T_16 & _out_T_65; // @[ReduceOthers.scala:47:21] wire _out_wofireMux_T_17 = ~_out_T_5; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_18 = out_wofireMux_out_3 | _out_wofireMux_T_17; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_3 = _out_wofireMux_T_18; // @[MuxLiteral.scala:49:48] wire [3:0] _GEN_5 = {{_out_wofireMux_WIRE_3}, {_out_wofireMux_WIRE_2}, {1'h1}, {1'h1}}; // @[MuxLiteral.scala:49:{10,48}] wire out_wofireMux = _GEN_5[out_oindex]; // @[MuxLiteral.scala:49:10] wire out_iready = out_front_bits_read | out_wifireMux; // @[MuxLiteral.scala:49:10] wire out_oready = _out_back_front_q_io_deq_bits_read | out_wofireMux; // @[MuxLiteral.scala:49:10] assign _out_in_ready_T = out_front_ready & out_iready; // @[RegisterRouter.scala:87:24] assign in_ready = _out_in_ready_T; // @[RegisterRouter.scala:73:18, :87:24] assign _out_front_valid_T = in_valid & out_iready; // @[RegisterRouter.scala:73:18, :87:24] assign out_front_valid = _out_front_valid_T; // @[RegisterRouter.scala:87:24] wire _out_front_q_io_deq_ready_T = out_ready & out_oready; // @[RegisterRouter.scala:87:24] assign _out_out_valid_T = _out_back_front_q_io_deq_valid & out_oready; // @[RegisterRouter.scala:87:24] assign out_valid = _out_out_valid_T; // @[RegisterRouter.scala:87:24] wire [3:0] _GEN_6 = {{_out_out_bits_data_WIRE_3}, {_out_out_bits_data_WIRE_2}, {1'h1}, {_out_out_bits_data_WIRE_0}}; // @[MuxLiteral.scala:49:{10,48}] wire _out_out_bits_data_T_1 = _GEN_6[out_oindex]; // @[MuxLiteral.scala:49:10] wire [63:0] _out_out_bits_data_T_3 = _GEN[out_oindex]; // @[MuxLiteral.scala:49:10] assign _out_out_bits_data_T_4 = _out_out_bits_data_T_1 ? _out_out_bits_data_T_3 : 64'h0; // @[MuxLiteral.scala:49:10] assign out_bits_data = _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24] assign ctrlnodeIn_d_bits_size = ctrlnodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign ctrlnodeIn_d_bits_source = ctrlnodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign ctrlnodeIn_d_bits_opcode = {2'h0, _ctrlnodeIn_d_bits_opcode_T}; // @[RegisterRouter.scala:105:{19,25}] wire _T_1 = ~io_flush_match_0 & flushInValid; // @[Control.scala:38:9, :45:33, :56:{11,27}] always @(posedge clock) begin // @[Control.scala:38:9] if (reset) begin // @[Control.scala:38:9] flushInValid <= 1'h0; // @[Control.scala:45:33] flushOutValid <= 1'h0; // @[Control.scala:47:33] end else begin // @[Control.scala:38:9] flushInValid <= out_f_wivalid_5 | out_f_wivalid_4 | ~(_T_1 | io_flush_req_ready_0) & flushInValid; // @[RegisterRouter.scala:87:24] flushOutValid <= _T_1 | io_flush_resp_0 | ~flushOutReady & flushOutValid; // @[Control.scala:38:9, :47:33, :48:34, :50:{26,42}, :51:{26,42}, :56:{27,44}, :58:21] end if (_out_T_57) // @[Control.scala:64:20] flushInAddress <= {28'h0, _out_flushInAddress_T}; // @[Control.scala:46:29, :64:{55,63}] else if (_out_T_44) // @[Control.scala:71:20] flushInAddress <= _out_T_42; // @[RegisterRouter.scala:87:24] always @(posedge) TLMonitor_35 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (ctrlnodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (ctrlnodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (ctrlnodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (ctrlnodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (ctrlnodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (ctrlnodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (ctrlnodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (ctrlnodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (ctrlnodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (ctrlnodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (ctrlnodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (ctrlnodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (ctrlnodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_size (ctrlnodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (ctrlnodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_data (ctrlnodeIn_d_bits_data) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue1_RegMapperInput_i9_m8 out_back_front_q ( // @[RegisterRouter.scala:87:24] .clock (clock), .reset (reset), .io_enq_ready (out_front_ready), .io_enq_valid (out_front_valid), // @[RegisterRouter.scala:87:24] .io_enq_bits_read (out_front_bits_read), // @[RegisterRouter.scala:87:24] .io_enq_bits_index (out_front_bits_index), // @[RegisterRouter.scala:87:24] .io_enq_bits_data (out_front_bits_data), // @[RegisterRouter.scala:87:24] .io_enq_bits_mask (out_front_bits_mask), // @[RegisterRouter.scala:87:24] .io_enq_bits_extra_tlrr_extra_source (out_front_bits_extra_tlrr_extra_source), // @[RegisterRouter.scala:87:24] .io_enq_bits_extra_tlrr_extra_size (out_front_bits_extra_tlrr_extra_size), // @[RegisterRouter.scala:87:24] .io_deq_ready (_out_front_q_io_deq_ready_T), // @[RegisterRouter.scala:87:24] .io_deq_valid (_out_back_front_q_io_deq_valid), .io_deq_bits_read (_out_back_front_q_io_deq_bits_read), .io_deq_bits_index (_out_back_front_q_io_deq_bits_index), .io_deq_bits_data (_out_back_front_q_io_deq_bits_data), .io_deq_bits_mask (_out_back_front_q_io_deq_bits_mask), .io_deq_bits_extra_tlrr_extra_source (out_bits_extra_tlrr_extra_source), .io_deq_bits_extra_tlrr_extra_size (out_bits_extra_tlrr_extra_size) ); // @[RegisterRouter.scala:87:24] assign out_bits_read = _out_back_front_q_io_deq_bits_read; // @[RegisterRouter.scala:87:24] assign auto_ctrl_in_a_ready = auto_ctrl_in_a_ready_0; // @[Control.scala:38:9] assign auto_ctrl_in_d_valid = auto_ctrl_in_d_valid_0; // @[Control.scala:38:9] assign auto_ctrl_in_d_bits_opcode = auto_ctrl_in_d_bits_opcode_0; // @[Control.scala:38:9] assign auto_ctrl_in_d_bits_size = auto_ctrl_in_d_bits_size_0; // @[Control.scala:38:9] assign auto_ctrl_in_d_bits_source = auto_ctrl_in_d_bits_source_0; // @[Control.scala:38:9] assign auto_ctrl_in_d_bits_data = auto_ctrl_in_d_bits_data_0; // @[Control.scala:38:9] assign io_flush_req_valid = io_flush_req_valid_0; // @[Control.scala:38:9] assign io_flush_req_bits = io_flush_req_bits_0; // @[Control.scala:38:9] endmodule

Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }

module AsyncValidSync_96( // @[AsyncQueue.scala:58:7] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in = 1'h1; // @[ShiftReg.scala:45:23] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_109 io_out_source_valid_0 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File MulAddRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFN_interIo(expWidth: Int, sigWidth: Int) extends Bundle { //*** ENCODE SOME OF THESE CASES IN FEWER BITS?: val isSigNaNAny = Bool() val isNaNAOrB = Bool() val isInfA = Bool() val isZeroA = Bool() val isInfB = Bool() val isZeroB = Bool() val signProd = Bool() val isNaNC = Bool() val isInfC = Bool() val isZeroC = Bool() val sExpSum = SInt((expWidth + 2).W) val doSubMags = Bool() val CIsDominant = Bool() val CDom_CAlignDist = UInt(log2Ceil(sigWidth + 1).W) val highAlignedSigC = UInt((sigWidth + 2).W) val bit0AlignedSigC = UInt(1.W) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFNToRaw_preMul(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFNToRaw_preMul_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val mulAddA = Output(UInt(sigWidth.W)) val mulAddB = Output(UInt(sigWidth.W)) val mulAddC = Output(UInt((sigWidth * 2).W)) val toPostMul = Output(new MulAddRecFN_interIo(expWidth, sigWidth)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ //*** POSSIBLE TO REDUCE THIS BY 1 OR 2 BITS? (CURRENTLY 2 BITS BETWEEN //*** UNSHIFTED C AND PRODUCT): val sigSumWidth = sigWidth * 3 + 3 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val rawA = rawFloatFromRecFN(expWidth, sigWidth, io.a) val rawB = rawFloatFromRecFN(expWidth, sigWidth, io.b) val rawC = rawFloatFromRecFN(expWidth, sigWidth, io.c) val signProd = rawA.sign ^ rawB.sign ^ io.op(1) //*** REVIEW THE BIAS FOR 'sExpAlignedProd': val sExpAlignedProd = rawA.sExp +& rawB.sExp + (-(BigInt(1)<<expWidth) + sigWidth + 3).S val doSubMags = signProd ^ rawC.sign ^ io.op(0) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sNatCAlignDist = sExpAlignedProd - rawC.sExp val posNatCAlignDist = sNatCAlignDist(expWidth + 1, 0) val isMinCAlign = rawA.isZero || rawB.isZero || (sNatCAlignDist < 0.S) val CIsDominant = ! rawC.isZero && (isMinCAlign || (posNatCAlignDist <= sigWidth.U)) val CAlignDist = Mux(isMinCAlign, 0.U, Mux(posNatCAlignDist < (sigSumWidth - 1).U, posNatCAlignDist(log2Ceil(sigSumWidth) - 1, 0), (sigSumWidth - 1).U ) ) val mainAlignedSigC = (Mux(doSubMags, ~rawC.sig, rawC.sig) ## Fill(sigSumWidth - sigWidth + 2, doSubMags)).asSInt>>CAlignDist val reduced4CExtra = (orReduceBy4(rawC.sig<<((sigSumWidth - sigWidth - 1) & 3)) & lowMask( CAlignDist>>2, //*** NOT NEEDED?: // (sigSumWidth + 2)>>2, (sigSumWidth - 1)>>2, (sigSumWidth - sigWidth - 1)>>2 ) ).orR val alignedSigC = Cat(mainAlignedSigC>>3, Mux(doSubMags, mainAlignedSigC(2, 0).andR && ! reduced4CExtra, mainAlignedSigC(2, 0).orR || reduced4CExtra ) ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ io.mulAddA := rawA.sig io.mulAddB := rawB.sig io.mulAddC := alignedSigC(sigWidth * 2, 1) io.toPostMul.isSigNaNAny := isSigNaNRawFloat(rawA) || isSigNaNRawFloat(rawB) || isSigNaNRawFloat(rawC) io.toPostMul.isNaNAOrB := rawA.isNaN || rawB.isNaN io.toPostMul.isInfA := rawA.isInf io.toPostMul.isZeroA := rawA.isZero io.toPostMul.isInfB := rawB.isInf io.toPostMul.isZeroB := rawB.isZero io.toPostMul.signProd := signProd io.toPostMul.isNaNC := rawC.isNaN io.toPostMul.isInfC := rawC.isInf io.toPostMul.isZeroC := rawC.isZero io.toPostMul.sExpSum := Mux(CIsDominant, rawC.sExp, sExpAlignedProd - sigWidth.S) io.toPostMul.doSubMags := doSubMags io.toPostMul.CIsDominant := CIsDominant io.toPostMul.CDom_CAlignDist := CAlignDist(log2Ceil(sigWidth + 1) - 1, 0) io.toPostMul.highAlignedSigC := alignedSigC(sigSumWidth - 1, sigWidth * 2 + 1) io.toPostMul.bit0AlignedSigC := alignedSigC(0) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFNToRaw_postMul(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFNToRaw_postMul_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val fromPreMul = Input(new MulAddRecFN_interIo(expWidth, sigWidth)) val mulAddResult = Input(UInt((sigWidth * 2 + 1).W)) val roundingMode = Input(UInt(3.W)) val invalidExc = Output(Bool()) val rawOut = Output(new RawFloat(expWidth, sigWidth + 2)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigSumWidth = sigWidth * 3 + 3 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_min = (io.roundingMode === round_min) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val opSignC = io.fromPreMul.signProd ^ io.fromPreMul.doSubMags val sigSum = Cat(Mux(io.mulAddResult(sigWidth * 2), io.fromPreMul.highAlignedSigC + 1.U, io.fromPreMul.highAlignedSigC ), io.mulAddResult(sigWidth * 2 - 1, 0), io.fromPreMul.bit0AlignedSigC ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val CDom_sign = opSignC val CDom_sExp = io.fromPreMul.sExpSum - io.fromPreMul.doSubMags.zext val CDom_absSigSum = Mux(io.fromPreMul.doSubMags, ~sigSum(sigSumWidth - 1, sigWidth + 1), 0.U(1.W) ## //*** IF GAP IS REDUCED TO 1 BIT, MUST REDUCE THIS COMPONENT TO 1 BIT TOO: io.fromPreMul.highAlignedSigC(sigWidth + 1, sigWidth) ## sigSum(sigSumWidth - 3, sigWidth + 2) ) val CDom_absSigSumExtra = Mux(io.fromPreMul.doSubMags, (~sigSum(sigWidth, 1)).orR, sigSum(sigWidth + 1, 1).orR ) val CDom_mainSig = (CDom_absSigSum<<io.fromPreMul.CDom_CAlignDist)( sigWidth * 2 + 1, sigWidth - 3) val CDom_reduced4SigExtra = (orReduceBy4(CDom_absSigSum(sigWidth - 1, 0)<<(~sigWidth & 3)) & lowMask(io.fromPreMul.CDom_CAlignDist>>2, 0, sigWidth>>2)).orR val CDom_sig = Cat(CDom_mainSig>>3, CDom_mainSig(2, 0).orR || CDom_reduced4SigExtra || CDom_absSigSumExtra ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val notCDom_signSigSum = sigSum(sigWidth * 2 + 3) val notCDom_absSigSum = Mux(notCDom_signSigSum, ~sigSum(sigWidth * 2 + 2, 0), sigSum(sigWidth * 2 + 2, 0) + io.fromPreMul.doSubMags ) val notCDom_reduced2AbsSigSum = orReduceBy2(notCDom_absSigSum) val notCDom_normDistReduced2 = countLeadingZeros(notCDom_reduced2AbsSigSum) val notCDom_nearNormDist = notCDom_normDistReduced2<<1 val notCDom_sExp = io.fromPreMul.sExpSum - notCDom_nearNormDist.asUInt.zext val notCDom_mainSig = (notCDom_absSigSum<<notCDom_nearNormDist)( sigWidth * 2 + 3, sigWidth - 1) val notCDom_reduced4SigExtra = (orReduceBy2( notCDom_reduced2AbsSigSum(sigWidth>>1, 0)<<((sigWidth>>1) & 1)) & lowMask(notCDom_normDistReduced2>>1, 0, (sigWidth + 2)>>2) ).orR val notCDom_sig = Cat(notCDom_mainSig>>3, notCDom_mainSig(2, 0).orR || notCDom_reduced4SigExtra ) val notCDom_completeCancellation = (notCDom_sig(sigWidth + 2, sigWidth + 1) === 0.U) val notCDom_sign = Mux(notCDom_completeCancellation, roundingMode_min, io.fromPreMul.signProd ^ notCDom_signSigSum ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val notNaN_isInfProd = io.fromPreMul.isInfA || io.fromPreMul.isInfB val notNaN_isInfOut = notNaN_isInfProd || io.fromPreMul.isInfC val notNaN_addZeros = (io.fromPreMul.isZeroA || io.fromPreMul.isZeroB) && io.fromPreMul.isZeroC io.invalidExc := io.fromPreMul.isSigNaNAny || (io.fromPreMul.isInfA && io.fromPreMul.isZeroB) || (io.fromPreMul.isZeroA && io.fromPreMul.isInfB) || (! io.fromPreMul.isNaNAOrB && (io.fromPreMul.isInfA || io.fromPreMul.isInfB) && io.fromPreMul.isInfC && io.fromPreMul.doSubMags) io.rawOut.isNaN := io.fromPreMul.isNaNAOrB || io.fromPreMul.isNaNC io.rawOut.isInf := notNaN_isInfOut //*** IMPROVE?: io.rawOut.isZero := notNaN_addZeros || (! io.fromPreMul.CIsDominant && notCDom_completeCancellation) io.rawOut.sign := (notNaN_isInfProd && io.fromPreMul.signProd) || (io.fromPreMul.isInfC && opSignC) || (notNaN_addZeros && ! roundingMode_min && io.fromPreMul.signProd && opSignC) || (notNaN_addZeros && roundingMode_min && (io.fromPreMul.signProd || opSignC)) || (! notNaN_isInfOut && ! notNaN_addZeros && Mux(io.fromPreMul.CIsDominant, CDom_sign, notCDom_sign)) io.rawOut.sExp := Mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp) io.rawOut.sig := Mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFN(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val mulAddRecFNToRaw_preMul = Module(new MulAddRecFNToRaw_preMul(expWidth, sigWidth)) val mulAddRecFNToRaw_postMul = Module(new MulAddRecFNToRaw_postMul(expWidth, sigWidth)) mulAddRecFNToRaw_preMul.io.op := io.op mulAddRecFNToRaw_preMul.io.a := io.a mulAddRecFNToRaw_preMul.io.b := io.b mulAddRecFNToRaw_preMul.io.c := io.c val mulAddResult = (mulAddRecFNToRaw_preMul.io.mulAddA * mulAddRecFNToRaw_preMul.io.mulAddB) +& mulAddRecFNToRaw_preMul.io.mulAddC mulAddRecFNToRaw_postMul.io.fromPreMul := mulAddRecFNToRaw_preMul.io.toPostMul mulAddRecFNToRaw_postMul.io.mulAddResult := mulAddResult mulAddRecFNToRaw_postMul.io.roundingMode := io.roundingMode //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundRawFNToRecFN = Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0)) roundRawFNToRecFN.io.invalidExc := mulAddRecFNToRaw_postMul.io.invalidExc roundRawFNToRecFN.io.infiniteExc := false.B roundRawFNToRecFN.io.in := mulAddRecFNToRaw_postMul.io.rawOut roundRawFNToRecFN.io.roundingMode := io.roundingMode roundRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundRawFNToRecFN.io.out io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags }

module MulAddRecFN_e8_s24_11( // @[MulAddRecFN.scala:300:7] input [32:0] io_a, // @[MulAddRecFN.scala:303:16] input [32:0] io_b, // @[MulAddRecFN.scala:303:16] output [32:0] io_out // @[MulAddRecFN.scala:303:16] ); wire _mulAddRecFNToRaw_postMul_io_invalidExc; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_isInf; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_isZero; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_sign; // @[MulAddRecFN.scala:319:15] wire [9:0] _mulAddRecFNToRaw_postMul_io_rawOut_sExp; // @[MulAddRecFN.scala:319:15] wire [26:0] _mulAddRecFNToRaw_postMul_io_rawOut_sig; // @[MulAddRecFN.scala:319:15] wire [23:0] _mulAddRecFNToRaw_preMul_io_mulAddA; // @[MulAddRecFN.scala:317:15] wire [23:0] _mulAddRecFNToRaw_preMul_io_mulAddB; // @[MulAddRecFN.scala:317:15] wire [47:0] _mulAddRecFNToRaw_preMul_io_mulAddC; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfB; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_signProd; // @[MulAddRecFN.scala:317:15] wire [9:0] _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; // @[MulAddRecFN.scala:317:15] wire [4:0] _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist; // @[MulAddRecFN.scala:317:15] wire [25:0] _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; // @[MulAddRecFN.scala:317:15] wire [32:0] io_a_0 = io_a; // @[MulAddRecFN.scala:300:7] wire [32:0] io_b_0 = io_b; // @[MulAddRecFN.scala:300:7] wire io_detectTininess = 1'h1; // @[MulAddRecFN.scala:300:7, :303:16, :317:15, :319:15, :339:15] wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:300:7, :303:16, :319:15, :339:15] wire [32:0] io_c = 33'h0; // @[MulAddRecFN.scala:300:7, :303:16, :317:15] wire [1:0] io_op = 2'h0; // @[MulAddRecFN.scala:300:7, :303:16, :317:15] wire [32:0] io_out_0; // @[MulAddRecFN.scala:300:7] wire [4:0] io_exceptionFlags; // @[MulAddRecFN.scala:300:7] wire [47:0] _mulAddResult_T = {24'h0, _mulAddRecFNToRaw_preMul_io_mulAddA} * {24'h0, _mulAddRecFNToRaw_preMul_io_mulAddB}; // @[MulAddRecFN.scala:317:15, :327:45] wire [48:0] mulAddResult = {1'h0, _mulAddResult_T} + {1'h0, _mulAddRecFNToRaw_preMul_io_mulAddC}; // @[MulAddRecFN.scala:317:15, :327:45, :328:50] MulAddRecFNToRaw_preMul_e8_s24_11 mulAddRecFNToRaw_preMul ( // @[MulAddRecFN.scala:317:15] .io_a (io_a_0), // @[MulAddRecFN.scala:300:7] .io_b (io_b_0), // @[MulAddRecFN.scala:300:7] .io_mulAddA (_mulAddRecFNToRaw_preMul_io_mulAddA), .io_mulAddB (_mulAddRecFNToRaw_preMul_io_mulAddB), .io_mulAddC (_mulAddRecFNToRaw_preMul_io_mulAddC), .io_toPostMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny), .io_toPostMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB), .io_toPostMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA), .io_toPostMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA), .io_toPostMul_isInfB (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfB), .io_toPostMul_isZeroB (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB), .io_toPostMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd), .io_toPostMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum), .io_toPostMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags), .io_toPostMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist), .io_toPostMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC), .io_toPostMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC) ); // @[MulAddRecFN.scala:317:15] MulAddRecFNToRaw_postMul_e8_s24_11 mulAddRecFNToRaw_postMul ( // @[MulAddRecFN.scala:319:15] .io_fromPreMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isInfB (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfB), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isZeroB (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC), // @[MulAddRecFN.scala:317:15] .io_mulAddResult (mulAddResult), // @[MulAddRecFN.scala:328:50] .io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc), .io_rawOut_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN), .io_rawOut_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf), .io_rawOut_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero), .io_rawOut_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign), .io_rawOut_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp), .io_rawOut_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig) ); // @[MulAddRecFN.scala:319:15] RoundRawFNToRecFN_e8_s24_11 roundRawFNToRecFN ( // @[MulAddRecFN.scala:339:15] .io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc), // @[MulAddRecFN.scala:319:15] .io_in_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN), // @[MulAddRecFN.scala:319:15] .io_in_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf), // @[MulAddRecFN.scala:319:15] .io_in_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero), // @[MulAddRecFN.scala:319:15] .io_in_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign), // @[MulAddRecFN.scala:319:15] .io_in_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp), // @[MulAddRecFN.scala:319:15] .io_in_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig), // @[MulAddRecFN.scala:319:15] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags) ); // @[MulAddRecFN.scala:339:15] assign io_out = io_out_0; // @[MulAddRecFN.scala:300:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File ShiftRegisterPriorityQueue.scala: package compressacc import chisel3._ import chisel3.util._ import chisel3.util._ // TODO : support enq & deq at the same cycle class PriorityQueueStageIO(keyWidth: Int, value: ValueInfo) extends Bundle { val output_prev = KeyValue(keyWidth, value) val output_nxt = KeyValue(keyWidth, value) val input_prev = Flipped(KeyValue(keyWidth, value)) val input_nxt = Flipped(KeyValue(keyWidth, value)) val cmd = Flipped(Valid(UInt(1.W))) val insert_here = Input(Bool()) val cur_input_keyval = Flipped(KeyValue(keyWidth, value)) val cur_output_keyval = KeyValue(keyWidth, value) } class PriorityQueueStage(keyWidth: Int, value: ValueInfo) extends Module { val io = IO(new PriorityQueueStageIO(keyWidth, value)) dontTouch(io) val CMD_DEQ = 0.U val CMD_ENQ = 1.U val MAX_VALUE = (1 << keyWidth) - 1 val key_reg = RegInit(MAX_VALUE.U(keyWidth.W)) val value_reg = Reg(value) io.output_prev.key := key_reg io.output_prev.value := value_reg io.output_nxt.key := key_reg io.output_nxt.value := value_reg io.cur_output_keyval.key := key_reg io.cur_output_keyval.value := value_reg when (io.cmd.valid) { switch (io.cmd.bits) { is (CMD_DEQ) { key_reg := io.input_nxt.key value_reg := io.input_nxt.value } is (CMD_ENQ) { when (io.insert_here) { key_reg := io.cur_input_keyval.key value_reg := io.cur_input_keyval.value } .elsewhen (key_reg >= io.cur_input_keyval.key) { key_reg := io.input_prev.key value_reg := io.input_prev.value } .otherwise { // do nothing } } } } } object PriorityQueueStage { def apply(keyWidth: Int, v: ValueInfo): PriorityQueueStage = new PriorityQueueStage(keyWidth, v) } // TODO // - This design is not scalable as the enqued_keyval is broadcasted to all the stages // - Add pipeline registers later class PriorityQueueIO(queSize: Int, keyWidth: Int, value: ValueInfo) extends Bundle { val cnt_bits = log2Ceil(queSize+1) val counter = Output(UInt(cnt_bits.W)) val enq = Flipped(Decoupled(KeyValue(keyWidth, value))) val deq = Decoupled(KeyValue(keyWidth, value)) } class PriorityQueue(queSize: Int, keyWidth: Int, value: ValueInfo) extends Module { val keyWidthInternal = keyWidth + 1 val CMD_DEQ = 0.U val CMD_ENQ = 1.U val io = IO(new PriorityQueueIO(queSize, keyWidthInternal, value)) dontTouch(io) val MAX_VALUE = ((1 << keyWidthInternal) - 1).U val cnt_bits = log2Ceil(queSize+1) // do not consider cases where we are inserting more entries then the queSize val counter = RegInit(0.U(cnt_bits.W)) io.counter := counter val full = (counter === queSize.U) val empty = (counter === 0.U) io.deq.valid := !empty io.enq.ready := !full when (io.enq.fire) { counter := counter + 1.U } when (io.deq.fire) { counter := counter - 1.U } val cmd_valid = io.enq.valid || io.deq.ready val cmd = Mux(io.enq.valid, CMD_ENQ, CMD_DEQ) assert(!(io.enq.valid && io.deq.ready)) val stages = Seq.fill(queSize)(Module(new PriorityQueueStage(keyWidthInternal, value))) for (i <- 0 until (queSize - 1)) { stages(i+1).io.input_prev <> stages(i).io.output_nxt stages(i).io.input_nxt <> stages(i+1).io.output_prev } stages(queSize-1).io.input_nxt.key := MAX_VALUE // stages(queSize-1).io.input_nxt.value := stages(queSize-1).io.input_nxt.value.symbol := 0.U // stages(queSize-1).io.input_nxt.value.child(0) := 0.U // stages(queSize-1).io.input_nxt.value.child(1) := 0.U stages(0).io.input_prev.key := io.enq.bits.key stages(0).io.input_prev.value <> io.enq.bits.value for (i <- 0 until queSize) { stages(i).io.cmd.valid := cmd_valid stages(i).io.cmd.bits := cmd stages(i).io.cur_input_keyval <> io.enq.bits } val is_large_or_equal = WireInit(VecInit(Seq.fill(queSize)(false.B))) for (i <- 0 until queSize) { is_large_or_equal(i) := (stages(i).io.cur_output_keyval.key >= io.enq.bits.key) } val is_large_or_equal_cat = Wire(UInt(queSize.W)) is_large_or_equal_cat := Cat(is_large_or_equal.reverse) val insert_here_idx = PriorityEncoder(is_large_or_equal_cat) for (i <- 0 until queSize) { when (i.U === insert_here_idx) { stages(i).io.insert_here := true.B } .otherwise { stages(i).io.insert_here := false.B } } io.deq.bits <> stages(0).io.output_prev }

module PriorityQueueStage_219( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async } File AsyncCrossing.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet, NodeHandle} import freechips.rocketchip.prci.{AsynchronousCrossing} import freechips.rocketchip.subsystem.CrossingWrapper import freechips.rocketchip.util.{AsyncQueueParams, ToAsyncBundle, FromAsyncBundle, Pow2ClockDivider, property} class TLAsyncCrossingSource(sync: Option[Int])(implicit p: Parameters) extends LazyModule { def this(x: Int)(implicit p: Parameters) = this(Some(x)) def this()(implicit p: Parameters) = this(None) val node = TLAsyncSourceNode(sync) lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = (Seq("TLAsyncCrossingSource") ++ node.in.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => val bce = edgeIn.manager.anySupportAcquireB && edgeIn.client.anySupportProbe val psync = sync.getOrElse(edgeOut.manager.async.sync) val params = edgeOut.manager.async.copy(sync = psync) out.a <> ToAsyncBundle(in.a, params) in.d <> FromAsyncBundle(out.d, psync) property.cover(in.a, "TL_ASYNC_CROSSING_SOURCE_A", "MemorySystem;;TLAsyncCrossingSource Channel A") property.cover(in.d, "TL_ASYNC_CROSSING_SOURCE_D", "MemorySystem;;TLAsyncCrossingSource Channel D") if (bce) { in.b <> FromAsyncBundle(out.b, psync) out.c <> ToAsyncBundle(in.c, params) out.e <> ToAsyncBundle(in.e, params) property.cover(in.b, "TL_ASYNC_CROSSING_SOURCE_B", "MemorySystem;;TLAsyncCrossingSource Channel B") property.cover(in.c, "TL_ASYNC_CROSSING_SOURCE_C", "MemorySystem;;TLAsyncCrossingSource Channel C") property.cover(in.e, "TL_ASYNC_CROSSING_SOURCE_E", "MemorySystem;;TLAsyncCrossingSource Channel E") } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ridx := 0.U out.c.widx := 0.U out.e.widx := 0.U } } } } class TLAsyncCrossingSink(params: AsyncQueueParams = AsyncQueueParams())(implicit p: Parameters) extends LazyModule { val node = TLAsyncSinkNode(params) lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = (Seq("TLAsyncCrossingSink") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => val bce = edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe out.a <> FromAsyncBundle(in.a, params.sync) in.d <> ToAsyncBundle(out.d, params) property.cover(out.a, "TL_ASYNC_CROSSING_SINK_A", "MemorySystem;;TLAsyncCrossingSink Channel A") property.cover(out.d, "TL_ASYNC_CROSSING_SINK_D", "MemorySystem;;TLAsyncCrossingSink Channel D") if (bce) { in.b <> ToAsyncBundle(out.b, params) out.c <> FromAsyncBundle(in.c, params.sync) out.e <> FromAsyncBundle(in.e, params.sync) property.cover(out.b, "TL_ASYNC_CROSSING_SINK_B", "MemorySystem;;TLAsyncCrossingSinkChannel B") property.cover(out.c, "TL_ASYNC_CROSSING_SINK_C", "MemorySystem;;TLAsyncCrossingSink Channel C") property.cover(out.e, "TL_ASYNC_CROSSING_SINK_E", "MemorySystem;;TLAsyncCrossingSink Channel E") } else { in.b.widx := 0.U in.c.ridx := 0.U in.e.ridx := 0.U out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLAsyncCrossingSource { def apply()(implicit p: Parameters): TLAsyncSourceNode = apply(None) def apply(sync: Int)(implicit p: Parameters): TLAsyncSourceNode = apply(Some(sync)) def apply(sync: Option[Int])(implicit p: Parameters): TLAsyncSourceNode = { val asource = LazyModule(new TLAsyncCrossingSource(sync)) asource.node } } object TLAsyncCrossingSink { def apply(params: AsyncQueueParams = AsyncQueueParams())(implicit p: Parameters) = { val asink = LazyModule(new TLAsyncCrossingSink(params)) asink.node } } @deprecated("TLAsyncCrossing is fragile. Use TLAsyncCrossingSource and TLAsyncCrossingSink", "rocket-chip 1.2") class TLAsyncCrossing(params: AsyncQueueParams = AsyncQueueParams())(implicit p: Parameters) extends LazyModule { val source = LazyModule(new TLAsyncCrossingSource()) val sink = LazyModule(new TLAsyncCrossingSink(params)) val node = NodeHandle(source.node, sink.node) sink.node := source.node lazy val module = new Impl class Impl extends LazyModuleImp(this) { val io = IO(new Bundle { val in_clock = Input(Clock()) val in_reset = Input(Bool()) val out_clock = Input(Clock()) val out_reset = Input(Bool()) }) source.module.clock := io.in_clock source.module.reset := io.in_reset sink.module.clock := io.out_clock sink.module.reset := io.out_reset } } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMAsyncCrossing(txns: Int, params: AsynchronousCrossing = AsynchronousCrossing())(implicit p: Parameters) extends LazyModule { val model = LazyModule(new TLRAMModel("AsyncCrossing")) val fuzz = LazyModule(new TLFuzzer(txns)) val island = LazyModule(new CrossingWrapper(params)) val ram = island { LazyModule(new TLRAM(AddressSet(0x0, 0x3ff))) } island.crossTLIn(ram.node) := TLFragmenter(4, 256) := TLDelayer(0.1) := model.node := fuzz.node lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished // Shove the RAM into another clock domain val clocks = Module(new Pow2ClockDivider(2)) island.module.clock := clocks.io.clock_out } } class TLRAMAsyncCrossingTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut_wide = Module(LazyModule(new TLRAMAsyncCrossing(txns)).module) val dut_narrow = Module(LazyModule(new TLRAMAsyncCrossing(txns, AsynchronousCrossing(safe = false, narrow = true))).module) io.finished := dut_wide.io.finished && dut_narrow.io.finished dut_wide.io.start := io.start dut_narrow.io.start := io.start } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } }

module TLAsyncCrossingSource_a9d32s1k1z2u( // @[AsyncCrossing.scala:23:9] input clock, // @[AsyncCrossing.scala:23:9] input reset, // @[AsyncCrossing.scala:23:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [8:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [31:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_mem_0_opcode, // @[LazyModuleImp.scala:107:25] output [8:0] auto_out_a_mem_0_address, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_mem_0_data, // @[LazyModuleImp.scala:107:25] input auto_out_a_ridx, // @[LazyModuleImp.scala:107:25] output auto_out_a_widx, // @[LazyModuleImp.scala:107:25] input auto_out_a_safe_ridx_valid, // @[LazyModuleImp.scala:107:25] output auto_out_a_safe_widx_valid, // @[LazyModuleImp.scala:107:25] output auto_out_a_safe_source_reset_n, // @[LazyModuleImp.scala:107:25] input auto_out_a_safe_sink_reset_n, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_mem_0_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_mem_0_size, // @[LazyModuleImp.scala:107:25] input auto_out_d_mem_0_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_out_d_mem_0_data, // @[LazyModuleImp.scala:107:25] output auto_out_d_ridx, // @[LazyModuleImp.scala:107:25] input auto_out_d_widx, // @[LazyModuleImp.scala:107:25] output auto_out_d_safe_ridx_valid, // @[LazyModuleImp.scala:107:25] input auto_out_d_safe_widx_valid, // @[LazyModuleImp.scala:107:25] input auto_out_d_safe_source_reset_n, // @[LazyModuleImp.scala:107:25] output auto_out_d_safe_sink_reset_n // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[AsyncCrossing.scala:23:9] wire [8:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[AsyncCrossing.scala:23:9] wire [31:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[AsyncCrossing.scala:23:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[AsyncCrossing.scala:23:9] wire auto_out_a_ridx_0 = auto_out_a_ridx; // @[AsyncCrossing.scala:23:9] wire auto_out_a_safe_ridx_valid_0 = auto_out_a_safe_ridx_valid; // @[AsyncCrossing.scala:23:9] wire auto_out_a_safe_sink_reset_n_0 = auto_out_a_safe_sink_reset_n; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_out_d_mem_0_opcode_0 = auto_out_d_mem_0_opcode; // @[AsyncCrossing.scala:23:9] wire [1:0] auto_out_d_mem_0_size_0 = auto_out_d_mem_0_size; // @[AsyncCrossing.scala:23:9] wire auto_out_d_mem_0_source_0 = auto_out_d_mem_0_source; // @[AsyncCrossing.scala:23:9] wire [31:0] auto_out_d_mem_0_data_0 = auto_out_d_mem_0_data; // @[AsyncCrossing.scala:23:9] wire auto_out_d_widx_0 = auto_out_d_widx; // @[AsyncCrossing.scala:23:9] wire auto_out_d_safe_widx_valid_0 = auto_out_d_safe_widx_valid; // @[AsyncCrossing.scala:23:9] wire auto_out_d_safe_source_reset_n_0 = auto_out_d_safe_source_reset_n; // @[AsyncCrossing.scala:23:9] wire [31:0] auto_out_b_mem_0_data = 32'h0; // @[AsyncCrossing.scala:23:9] wire [31:0] auto_out_c_mem_0_data = 32'h0; // @[AsyncCrossing.scala:23:9] wire [31:0] nodeOut_b_mem_0_data = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_c_mem_0_data = 32'h0; // @[MixedNode.scala:542:17] wire [3:0] auto_out_b_mem_0_mask = 4'h0; // @[AsyncCrossing.scala:23:9] wire [3:0] nodeOut_b_mem_0_mask = 4'h0; // @[AsyncCrossing.scala:23:9] wire [8:0] auto_out_b_mem_0_address = 9'h0; // @[AsyncCrossing.scala:23:9] wire [8:0] auto_out_c_mem_0_address = 9'h0; // @[AsyncCrossing.scala:23:9] wire [8:0] nodeOut_b_mem_0_address = 9'h0; // @[MixedNode.scala:542:17] wire [8:0] nodeOut_c_mem_0_address = 9'h0; // @[MixedNode.scala:542:17] wire [1:0] auto_out_b_mem_0_param = 2'h0; // @[AsyncCrossing.scala:23:9] wire [1:0] auto_out_b_mem_0_size = 2'h0; // @[AsyncCrossing.scala:23:9] wire [1:0] auto_out_c_mem_0_size = 2'h0; // @[AsyncCrossing.scala:23:9] wire [1:0] auto_out_d_mem_0_param = 2'h0; // @[AsyncCrossing.scala:23:9] wire [1:0] nodeOut_b_mem_0_param = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_b_mem_0_size = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_c_mem_0_size = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_d_mem_0_param = 2'h0; // @[MixedNode.scala:542:17] wire [3:0] auto_in_a_bits_mask = 4'hF; // @[AsyncCrossing.scala:23:9] wire [3:0] auto_out_a_mem_0_mask = 4'hF; // @[AsyncCrossing.scala:23:9] wire [3:0] nodeIn_a_bits_mask = 4'hF; // @[MixedNode.scala:551:17] wire [3:0] nodeOut_a_mem_0_mask = 4'hF; // @[MixedNode.scala:542:17] wire auto_in_a_bits_source = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_in_a_bits_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_a_mem_0_source = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_a_mem_0_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_mem_0_source = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_mem_0_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_ridx = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_widx = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_safe_ridx_valid = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_safe_widx_valid = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_safe_source_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_safe_sink_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_mem_0_source = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_mem_0_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_ridx = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_widx = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_safe_ridx_valid = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_safe_widx_valid = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_safe_source_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_safe_sink_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_d_mem_0_sink = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_d_mem_0_denied = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_d_mem_0_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_e_mem_0_sink = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_e_ridx = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_e_widx = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_e_safe_ridx_valid = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_e_safe_widx_valid = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_e_safe_source_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_e_safe_sink_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9] wire nodeIn_a_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire nodeOut_a_mem_0_source = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_a_mem_0_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_mem_0_source = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_mem_0_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_ridx = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_widx = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_safe_ridx_valid = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_safe_widx_valid = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_safe_source_reset_n = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_safe_sink_reset_n = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_mem_0_source = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_mem_0_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_ridx = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_widx = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_safe_ridx_valid = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_safe_widx_valid = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_safe_source_reset_n = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_safe_sink_reset_n = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_d_mem_0_sink = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_d_mem_0_denied = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_d_mem_0_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_e_mem_0_sink = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_e_ridx = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_e_widx = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_e_safe_ridx_valid = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_e_safe_widx_valid = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_e_safe_source_reset_n = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_e_safe_sink_reset_n = 1'h0; // @[MixedNode.scala:542:17] wire [1:0] auto_in_a_bits_size = 2'h2; // @[AsyncCrossing.scala:23:9] wire [1:0] auto_out_a_mem_0_size = 2'h2; // @[AsyncCrossing.scala:23:9] wire [1:0] nodeIn_a_bits_size = 2'h2; // @[MixedNode.scala:551:17] wire [1:0] nodeOut_a_mem_0_size = 2'h2; // @[MixedNode.scala:542:17] wire [2:0] auto_in_a_bits_param = 3'h0; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_out_a_mem_0_param = 3'h0; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_out_b_mem_0_opcode = 3'h0; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_out_c_mem_0_opcode = 3'h0; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_out_c_mem_0_param = 3'h0; // @[AsyncCrossing.scala:23:9] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_a_bits_param = 3'h0; // @[MixedNode.scala:551:17] wire [2:0] nodeOut_a_mem_0_param = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_b_mem_0_opcode = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_mem_0_opcode = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_mem_0_param = 3'h0; // @[MixedNode.scala:542:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[AsyncCrossing.scala:23:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[AsyncCrossing.scala:23:9] wire [8:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[AsyncCrossing.scala:23:9] wire [31:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[AsyncCrossing.scala:23:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[AsyncCrossing.scala:23:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [31:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [2:0] nodeOut_a_mem_0_opcode; // @[MixedNode.scala:542:17] wire [8:0] nodeOut_a_mem_0_address; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_mem_0_data; // @[MixedNode.scala:542:17] wire nodeOut_a_ridx = auto_out_a_ridx_0; // @[AsyncCrossing.scala:23:9] wire nodeOut_a_widx; // @[MixedNode.scala:542:17] wire nodeOut_a_safe_ridx_valid = auto_out_a_safe_ridx_valid_0; // @[AsyncCrossing.scala:23:9] wire nodeOut_a_safe_widx_valid; // @[MixedNode.scala:542:17] wire nodeOut_a_safe_source_reset_n; // @[MixedNode.scala:542:17] wire nodeOut_a_safe_sink_reset_n = auto_out_a_safe_sink_reset_n_0; // @[AsyncCrossing.scala:23:9] wire [2:0] nodeOut_d_mem_0_opcode = auto_out_d_mem_0_opcode_0; // @[AsyncCrossing.scala:23:9] wire [1:0] nodeOut_d_mem_0_size = auto_out_d_mem_0_size_0; // @[AsyncCrossing.scala:23:9] wire nodeOut_d_mem_0_source = auto_out_d_mem_0_source_0; // @[AsyncCrossing.scala:23:9] wire [31:0] nodeOut_d_mem_0_data = auto_out_d_mem_0_data_0; // @[AsyncCrossing.scala:23:9] wire nodeOut_d_ridx; // @[MixedNode.scala:542:17] wire nodeOut_d_widx = auto_out_d_widx_0; // @[AsyncCrossing.scala:23:9] wire nodeOut_d_safe_ridx_valid; // @[MixedNode.scala:542:17] wire nodeOut_d_safe_widx_valid = auto_out_d_safe_widx_valid_0; // @[AsyncCrossing.scala:23:9] wire nodeOut_d_safe_source_reset_n = auto_out_d_safe_source_reset_n_0; // @[AsyncCrossing.scala:23:9] wire nodeOut_d_safe_sink_reset_n; // @[MixedNode.scala:542:17] wire auto_in_a_ready_0; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_in_d_bits_opcode_0; // @[AsyncCrossing.scala:23:9] wire [1:0] auto_in_d_bits_param_0; // @[AsyncCrossing.scala:23:9] wire [1:0] auto_in_d_bits_size_0; // @[AsyncCrossing.scala:23:9] wire auto_in_d_bits_source_0; // @[AsyncCrossing.scala:23:9] wire auto_in_d_bits_sink_0; // @[AsyncCrossing.scala:23:9] wire auto_in_d_bits_denied_0; // @[AsyncCrossing.scala:23:9] wire [31:0] auto_in_d_bits_data_0; // @[AsyncCrossing.scala:23:9] wire auto_in_d_bits_corrupt_0; // @[AsyncCrossing.scala:23:9] wire auto_in_d_valid_0; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_out_a_mem_0_opcode_0; // @[AsyncCrossing.scala:23:9] wire [8:0] auto_out_a_mem_0_address_0; // @[AsyncCrossing.scala:23:9] wire [31:0] auto_out_a_mem_0_data_0; // @[AsyncCrossing.scala:23:9] wire auto_out_a_safe_widx_valid_0; // @[AsyncCrossing.scala:23:9] wire auto_out_a_safe_source_reset_n_0; // @[AsyncCrossing.scala:23:9] wire auto_out_a_widx_0; // @[AsyncCrossing.scala:23:9] wire auto_out_d_safe_ridx_valid_0; // @[AsyncCrossing.scala:23:9] wire auto_out_d_safe_sink_reset_n_0; // @[AsyncCrossing.scala:23:9] wire auto_out_d_ridx_0; // @[AsyncCrossing.scala:23:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[AsyncCrossing.scala:23:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[AsyncCrossing.scala:23:9] assign auto_out_a_mem_0_opcode_0 = nodeOut_a_mem_0_opcode; // @[AsyncCrossing.scala:23:9] assign auto_out_a_mem_0_address_0 = nodeOut_a_mem_0_address; // @[AsyncCrossing.scala:23:9] assign auto_out_a_mem_0_data_0 = nodeOut_a_mem_0_data; // @[AsyncCrossing.scala:23:9] assign auto_out_a_widx_0 = nodeOut_a_widx; // @[AsyncCrossing.scala:23:9] assign auto_out_a_safe_widx_valid_0 = nodeOut_a_safe_widx_valid; // @[AsyncCrossing.scala:23:9] assign auto_out_a_safe_source_reset_n_0 = nodeOut_a_safe_source_reset_n; // @[AsyncCrossing.scala:23:9] assign auto_out_d_ridx_0 = nodeOut_d_ridx; // @[AsyncCrossing.scala:23:9] assign auto_out_d_safe_ridx_valid_0 = nodeOut_d_safe_ridx_valid; // @[AsyncCrossing.scala:23:9] assign auto_out_d_safe_sink_reset_n_0 = nodeOut_d_safe_sink_reset_n; // @[AsyncCrossing.scala:23:9] TLMonitor_52 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] AsyncQueueSource_TLBundleA_a9d32s1k1z2u nodeOut_a_source ( // @[AsyncQueue.scala:220:24] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_async_mem_0_opcode (nodeOut_a_mem_0_opcode), .io_async_mem_0_address (nodeOut_a_mem_0_address), .io_async_mem_0_data (nodeOut_a_mem_0_data), .io_async_ridx (nodeOut_a_ridx), // @[MixedNode.scala:542:17] .io_async_widx (nodeOut_a_widx), .io_async_safe_ridx_valid (nodeOut_a_safe_ridx_valid), // @[MixedNode.scala:542:17] .io_async_safe_widx_valid (nodeOut_a_safe_widx_valid), .io_async_safe_source_reset_n (nodeOut_a_safe_source_reset_n), .io_async_safe_sink_reset_n (nodeOut_a_safe_sink_reset_n) // @[MixedNode.scala:542:17] ); // @[AsyncQueue.scala:220:24] AsyncQueueSink_TLBundleD_a9d32s1k1z2u nodeIn_d_sink ( // @[AsyncQueue.scala:211:22] .clock (clock), .reset (reset), .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt), .io_async_mem_0_opcode (nodeOut_d_mem_0_opcode), // @[MixedNode.scala:542:17] .io_async_mem_0_size (nodeOut_d_mem_0_size), // @[MixedNode.scala:542:17] .io_async_mem_0_source (nodeOut_d_mem_0_source), // @[MixedNode.scala:542:17] .io_async_mem_0_data (nodeOut_d_mem_0_data), // @[MixedNode.scala:542:17] .io_async_ridx (nodeOut_d_ridx), .io_async_widx (nodeOut_d_widx), // @[MixedNode.scala:542:17] .io_async_safe_ridx_valid (nodeOut_d_safe_ridx_valid), .io_async_safe_widx_valid (nodeOut_d_safe_widx_valid), // @[MixedNode.scala:542:17] .io_async_safe_source_reset_n (nodeOut_d_safe_source_reset_n), // @[MixedNode.scala:542:17] .io_async_safe_sink_reset_n (nodeOut_d_safe_sink_reset_n) ); // @[AsyncQueue.scala:211:22] assign auto_in_a_ready = auto_in_a_ready_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[AsyncCrossing.scala:23:9] assign auto_out_a_mem_0_opcode = auto_out_a_mem_0_opcode_0; // @[AsyncCrossing.scala:23:9] assign auto_out_a_mem_0_address = auto_out_a_mem_0_address_0; // @[AsyncCrossing.scala:23:9] assign auto_out_a_mem_0_data = auto_out_a_mem_0_data_0; // @[AsyncCrossing.scala:23:9] assign auto_out_a_widx = auto_out_a_widx_0; // @[AsyncCrossing.scala:23:9] assign auto_out_a_safe_widx_valid = auto_out_a_safe_widx_valid_0; // @[AsyncCrossing.scala:23:9] assign auto_out_a_safe_source_reset_n = auto_out_a_safe_source_reset_n_0; // @[AsyncCrossing.scala:23:9] assign auto_out_d_ridx = auto_out_d_ridx_0; // @[AsyncCrossing.scala:23:9] assign auto_out_d_safe_ridx_valid = auto_out_d_safe_ridx_valid_0; // @[AsyncCrossing.scala:23:9] assign auto_out_d_safe_sink_reset_n = auto_out_d_safe_sink_reset_n_0; // @[AsyncCrossing.scala:23:9] endmodule

Generate the Verilog code corresponding to the following Chisel files. File primitives.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object lowMask { def apply(in: UInt, topBound: BigInt, bottomBound: BigInt): UInt = { require(topBound != bottomBound) val numInVals = BigInt(1)<<in.getWidth if (topBound < bottomBound) { lowMask(~in, numInVals - 1 - topBound, numInVals - 1 - bottomBound) } else if (numInVals > 64 /* Empirical */) { // For simulation performance, we should avoid generating // exteremely wide shifters, so we divide and conquer. // Empirically, this does not impact synthesis QoR. val mid = numInVals / 2 val msb = in(in.getWidth - 1) val lsbs = in(in.getWidth - 2, 0) if (mid < topBound) { if (mid <= bottomBound) { Mux(msb, lowMask(lsbs, topBound - mid, bottomBound - mid), 0.U ) } else { Mux(msb, lowMask(lsbs, topBound - mid, 0) ## ((BigInt(1)<<(mid - bottomBound).toInt) - 1).U, lowMask(lsbs, mid, bottomBound) ) } } else { ~Mux(msb, 0.U, ~lowMask(lsbs, topBound, bottomBound)) } } else { val shift = (BigInt(-1)<<numInVals.toInt).S>>in Reverse( shift( (numInVals - 1 - bottomBound).toInt, (numInVals - topBound).toInt ) ) } } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object countLeadingZeros { def apply(in: UInt): UInt = PriorityEncoder(in.asBools.reverse) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy2 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 1)>>1 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 2 + 1, ix * 2).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 2).orR reducedVec.asUInt } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy4 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 3)>>2 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 4 + 3, ix * 4).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 4).orR reducedVec.asUInt } } File MulAddRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFN_interIo(expWidth: Int, sigWidth: Int) extends Bundle { //*** ENCODE SOME OF THESE CASES IN FEWER BITS?: val isSigNaNAny = Bool() val isNaNAOrB = Bool() val isInfA = Bool() val isZeroA = Bool() val isInfB = Bool() val isZeroB = Bool() val signProd = Bool() val isNaNC = Bool() val isInfC = Bool() val isZeroC = Bool() val sExpSum = SInt((expWidth + 2).W) val doSubMags = Bool() val CIsDominant = Bool() val CDom_CAlignDist = UInt(log2Ceil(sigWidth + 1).W) val highAlignedSigC = UInt((sigWidth + 2).W) val bit0AlignedSigC = UInt(1.W) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFNToRaw_preMul(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFNToRaw_preMul_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val mulAddA = Output(UInt(sigWidth.W)) val mulAddB = Output(UInt(sigWidth.W)) val mulAddC = Output(UInt((sigWidth * 2).W)) val toPostMul = Output(new MulAddRecFN_interIo(expWidth, sigWidth)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ //*** POSSIBLE TO REDUCE THIS BY 1 OR 2 BITS? (CURRENTLY 2 BITS BETWEEN //*** UNSHIFTED C AND PRODUCT): val sigSumWidth = sigWidth * 3 + 3 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val rawA = rawFloatFromRecFN(expWidth, sigWidth, io.a) val rawB = rawFloatFromRecFN(expWidth, sigWidth, io.b) val rawC = rawFloatFromRecFN(expWidth, sigWidth, io.c) val signProd = rawA.sign ^ rawB.sign ^ io.op(1) //*** REVIEW THE BIAS FOR 'sExpAlignedProd': val sExpAlignedProd = rawA.sExp +& rawB.sExp + (-(BigInt(1)<<expWidth) + sigWidth + 3).S val doSubMags = signProd ^ rawC.sign ^ io.op(0) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sNatCAlignDist = sExpAlignedProd - rawC.sExp val posNatCAlignDist = sNatCAlignDist(expWidth + 1, 0) val isMinCAlign = rawA.isZero || rawB.isZero || (sNatCAlignDist < 0.S) val CIsDominant = ! rawC.isZero && (isMinCAlign || (posNatCAlignDist <= sigWidth.U)) val CAlignDist = Mux(isMinCAlign, 0.U, Mux(posNatCAlignDist < (sigSumWidth - 1).U, posNatCAlignDist(log2Ceil(sigSumWidth) - 1, 0), (sigSumWidth - 1).U ) ) val mainAlignedSigC = (Mux(doSubMags, ~rawC.sig, rawC.sig) ## Fill(sigSumWidth - sigWidth + 2, doSubMags)).asSInt>>CAlignDist val reduced4CExtra = (orReduceBy4(rawC.sig<<((sigSumWidth - sigWidth - 1) & 3)) & lowMask( CAlignDist>>2, //*** NOT NEEDED?: // (sigSumWidth + 2)>>2, (sigSumWidth - 1)>>2, (sigSumWidth - sigWidth - 1)>>2 ) ).orR val alignedSigC = Cat(mainAlignedSigC>>3, Mux(doSubMags, mainAlignedSigC(2, 0).andR && ! reduced4CExtra, mainAlignedSigC(2, 0).orR || reduced4CExtra ) ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ io.mulAddA := rawA.sig io.mulAddB := rawB.sig io.mulAddC := alignedSigC(sigWidth * 2, 1) io.toPostMul.isSigNaNAny := isSigNaNRawFloat(rawA) || isSigNaNRawFloat(rawB) || isSigNaNRawFloat(rawC) io.toPostMul.isNaNAOrB := rawA.isNaN || rawB.isNaN io.toPostMul.isInfA := rawA.isInf io.toPostMul.isZeroA := rawA.isZero io.toPostMul.isInfB := rawB.isInf io.toPostMul.isZeroB := rawB.isZero io.toPostMul.signProd := signProd io.toPostMul.isNaNC := rawC.isNaN io.toPostMul.isInfC := rawC.isInf io.toPostMul.isZeroC := rawC.isZero io.toPostMul.sExpSum := Mux(CIsDominant, rawC.sExp, sExpAlignedProd - sigWidth.S) io.toPostMul.doSubMags := doSubMags io.toPostMul.CIsDominant := CIsDominant io.toPostMul.CDom_CAlignDist := CAlignDist(log2Ceil(sigWidth + 1) - 1, 0) io.toPostMul.highAlignedSigC := alignedSigC(sigSumWidth - 1, sigWidth * 2 + 1) io.toPostMul.bit0AlignedSigC := alignedSigC(0) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFNToRaw_postMul(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFNToRaw_postMul_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val fromPreMul = Input(new MulAddRecFN_interIo(expWidth, sigWidth)) val mulAddResult = Input(UInt((sigWidth * 2 + 1).W)) val roundingMode = Input(UInt(3.W)) val invalidExc = Output(Bool()) val rawOut = Output(new RawFloat(expWidth, sigWidth + 2)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigSumWidth = sigWidth * 3 + 3 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_min = (io.roundingMode === round_min) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val opSignC = io.fromPreMul.signProd ^ io.fromPreMul.doSubMags val sigSum = Cat(Mux(io.mulAddResult(sigWidth * 2), io.fromPreMul.highAlignedSigC + 1.U, io.fromPreMul.highAlignedSigC ), io.mulAddResult(sigWidth * 2 - 1, 0), io.fromPreMul.bit0AlignedSigC ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val CDom_sign = opSignC val CDom_sExp = io.fromPreMul.sExpSum - io.fromPreMul.doSubMags.zext val CDom_absSigSum = Mux(io.fromPreMul.doSubMags, ~sigSum(sigSumWidth - 1, sigWidth + 1), 0.U(1.W) ## //*** IF GAP IS REDUCED TO 1 BIT, MUST REDUCE THIS COMPONENT TO 1 BIT TOO: io.fromPreMul.highAlignedSigC(sigWidth + 1, sigWidth) ## sigSum(sigSumWidth - 3, sigWidth + 2) ) val CDom_absSigSumExtra = Mux(io.fromPreMul.doSubMags, (~sigSum(sigWidth, 1)).orR, sigSum(sigWidth + 1, 1).orR ) val CDom_mainSig = (CDom_absSigSum<<io.fromPreMul.CDom_CAlignDist)( sigWidth * 2 + 1, sigWidth - 3) val CDom_reduced4SigExtra = (orReduceBy4(CDom_absSigSum(sigWidth - 1, 0)<<(~sigWidth & 3)) & lowMask(io.fromPreMul.CDom_CAlignDist>>2, 0, sigWidth>>2)).orR val CDom_sig = Cat(CDom_mainSig>>3, CDom_mainSig(2, 0).orR || CDom_reduced4SigExtra || CDom_absSigSumExtra ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val notCDom_signSigSum = sigSum(sigWidth * 2 + 3) val notCDom_absSigSum = Mux(notCDom_signSigSum, ~sigSum(sigWidth * 2 + 2, 0), sigSum(sigWidth * 2 + 2, 0) + io.fromPreMul.doSubMags ) val notCDom_reduced2AbsSigSum = orReduceBy2(notCDom_absSigSum) val notCDom_normDistReduced2 = countLeadingZeros(notCDom_reduced2AbsSigSum) val notCDom_nearNormDist = notCDom_normDistReduced2<<1 val notCDom_sExp = io.fromPreMul.sExpSum - notCDom_nearNormDist.asUInt.zext val notCDom_mainSig = (notCDom_absSigSum<<notCDom_nearNormDist)( sigWidth * 2 + 3, sigWidth - 1) val notCDom_reduced4SigExtra = (orReduceBy2( notCDom_reduced2AbsSigSum(sigWidth>>1, 0)<<((sigWidth>>1) & 1)) & lowMask(notCDom_normDistReduced2>>1, 0, (sigWidth + 2)>>2) ).orR val notCDom_sig = Cat(notCDom_mainSig>>3, notCDom_mainSig(2, 0).orR || notCDom_reduced4SigExtra ) val notCDom_completeCancellation = (notCDom_sig(sigWidth + 2, sigWidth + 1) === 0.U) val notCDom_sign = Mux(notCDom_completeCancellation, roundingMode_min, io.fromPreMul.signProd ^ notCDom_signSigSum ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val notNaN_isInfProd = io.fromPreMul.isInfA || io.fromPreMul.isInfB val notNaN_isInfOut = notNaN_isInfProd || io.fromPreMul.isInfC val notNaN_addZeros = (io.fromPreMul.isZeroA || io.fromPreMul.isZeroB) && io.fromPreMul.isZeroC io.invalidExc := io.fromPreMul.isSigNaNAny || (io.fromPreMul.isInfA && io.fromPreMul.isZeroB) || (io.fromPreMul.isZeroA && io.fromPreMul.isInfB) || (! io.fromPreMul.isNaNAOrB && (io.fromPreMul.isInfA || io.fromPreMul.isInfB) && io.fromPreMul.isInfC && io.fromPreMul.doSubMags) io.rawOut.isNaN := io.fromPreMul.isNaNAOrB || io.fromPreMul.isNaNC io.rawOut.isInf := notNaN_isInfOut //*** IMPROVE?: io.rawOut.isZero := notNaN_addZeros || (! io.fromPreMul.CIsDominant && notCDom_completeCancellation) io.rawOut.sign := (notNaN_isInfProd && io.fromPreMul.signProd) || (io.fromPreMul.isInfC && opSignC) || (notNaN_addZeros && ! roundingMode_min && io.fromPreMul.signProd && opSignC) || (notNaN_addZeros && roundingMode_min && (io.fromPreMul.signProd || opSignC)) || (! notNaN_isInfOut && ! notNaN_addZeros && Mux(io.fromPreMul.CIsDominant, CDom_sign, notCDom_sign)) io.rawOut.sExp := Mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp) io.rawOut.sig := Mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFN(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val mulAddRecFNToRaw_preMul = Module(new MulAddRecFNToRaw_preMul(expWidth, sigWidth)) val mulAddRecFNToRaw_postMul = Module(new MulAddRecFNToRaw_postMul(expWidth, sigWidth)) mulAddRecFNToRaw_preMul.io.op := io.op mulAddRecFNToRaw_preMul.io.a := io.a mulAddRecFNToRaw_preMul.io.b := io.b mulAddRecFNToRaw_preMul.io.c := io.c val mulAddResult = (mulAddRecFNToRaw_preMul.io.mulAddA * mulAddRecFNToRaw_preMul.io.mulAddB) +& mulAddRecFNToRaw_preMul.io.mulAddC mulAddRecFNToRaw_postMul.io.fromPreMul := mulAddRecFNToRaw_preMul.io.toPostMul mulAddRecFNToRaw_postMul.io.mulAddResult := mulAddResult mulAddRecFNToRaw_postMul.io.roundingMode := io.roundingMode //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundRawFNToRecFN = Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0)) roundRawFNToRecFN.io.invalidExc := mulAddRecFNToRaw_postMul.io.invalidExc roundRawFNToRecFN.io.infiniteExc := false.B roundRawFNToRecFN.io.in := mulAddRecFNToRaw_postMul.io.rawOut roundRawFNToRecFN.io.roundingMode := io.roundingMode roundRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundRawFNToRecFN.io.out io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags }

module MulAddRecFNToRaw_postMul_e8_s24_79( // @[MulAddRecFN.scala:169:7] input io_fromPreMul_isSigNaNAny, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isNaNAOrB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfA, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroA, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_signProd, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isNaNC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroC, // @[MulAddRecFN.scala:172:16] input [9:0] io_fromPreMul_sExpSum, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_doSubMags, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_CIsDominant, // @[MulAddRecFN.scala:172:16] input [4:0] io_fromPreMul_CDom_CAlignDist, // @[MulAddRecFN.scala:172:16] input [25:0] io_fromPreMul_highAlignedSigC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_bit0AlignedSigC, // @[MulAddRecFN.scala:172:16] input [48:0] io_mulAddResult, // @[MulAddRecFN.scala:172:16] output io_invalidExc, // @[MulAddRecFN.scala:172:16] output io_rawOut_isNaN, // @[MulAddRecFN.scala:172:16] output io_rawOut_isInf, // @[MulAddRecFN.scala:172:16] output io_rawOut_isZero, // @[MulAddRecFN.scala:172:16] output io_rawOut_sign, // @[MulAddRecFN.scala:172:16] output [9:0] io_rawOut_sExp, // @[MulAddRecFN.scala:172:16] output [26:0] io_rawOut_sig // @[MulAddRecFN.scala:172:16] ); wire io_fromPreMul_isSigNaNAny_0 = io_fromPreMul_isSigNaNAny; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isNaNAOrB_0 = io_fromPreMul_isNaNAOrB; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfA_0 = io_fromPreMul_isInfA; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroA_0 = io_fromPreMul_isZeroA; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfB_0 = io_fromPreMul_isInfB; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroB_0 = io_fromPreMul_isZeroB; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_signProd_0 = io_fromPreMul_signProd; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isNaNC_0 = io_fromPreMul_isNaNC; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfC_0 = io_fromPreMul_isInfC; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroC_0 = io_fromPreMul_isZeroC; // @[MulAddRecFN.scala:169:7] wire [9:0] io_fromPreMul_sExpSum_0 = io_fromPreMul_sExpSum; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_doSubMags_0 = io_fromPreMul_doSubMags; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_CIsDominant_0 = io_fromPreMul_CIsDominant; // @[MulAddRecFN.scala:169:7] wire [4:0] io_fromPreMul_CDom_CAlignDist_0 = io_fromPreMul_CDom_CAlignDist; // @[MulAddRecFN.scala:169:7] wire [25:0] io_fromPreMul_highAlignedSigC_0 = io_fromPreMul_highAlignedSigC; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_bit0AlignedSigC_0 = io_fromPreMul_bit0AlignedSigC; // @[MulAddRecFN.scala:169:7] wire [48:0] io_mulAddResult_0 = io_mulAddResult; // @[MulAddRecFN.scala:169:7] wire _io_rawOut_sign_T_3 = 1'h1; // @[MulAddRecFN.scala:287:29] wire roundingMode_min = 1'h0; // @[MulAddRecFN.scala:186:45] wire _io_rawOut_sign_T_8 = 1'h0; // @[MulAddRecFN.scala:289:26] wire _io_rawOut_sign_T_10 = 1'h0; // @[MulAddRecFN.scala:289:46] wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:169:7, :172:16] wire _io_invalidExc_T_9; // @[MulAddRecFN.scala:273:57] wire _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:278:48] wire notNaN_isInfOut; // @[MulAddRecFN.scala:265:44] wire _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:282:25] wire _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:290:50] wire [9:0] _io_rawOut_sExp_T; // @[MulAddRecFN.scala:293:26] wire [26:0] _io_rawOut_sig_T; // @[MulAddRecFN.scala:294:25] wire io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7] wire [9:0] io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7] wire [26:0] io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7] wire io_invalidExc_0; // @[MulAddRecFN.scala:169:7] wire opSignC = io_fromPreMul_signProd_0 ^ io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :190:42] wire _sigSum_T = io_mulAddResult_0[48]; // @[MulAddRecFN.scala:169:7, :192:32] wire [26:0] _sigSum_T_1 = {1'h0, io_fromPreMul_highAlignedSigC_0} + 27'h1; // @[MulAddRecFN.scala:169:7, :193:47] wire [25:0] _sigSum_T_2 = _sigSum_T_1[25:0]; // @[MulAddRecFN.scala:193:47] wire [25:0] _sigSum_T_3 = _sigSum_T ? _sigSum_T_2 : io_fromPreMul_highAlignedSigC_0; // @[MulAddRecFN.scala:169:7, :192:{16,32}, :193:47] wire [47:0] _sigSum_T_4 = io_mulAddResult_0[47:0]; // @[MulAddRecFN.scala:169:7, :196:28] wire [73:0] sigSum_hi = {_sigSum_T_3, _sigSum_T_4}; // @[MulAddRecFN.scala:192:{12,16}, :196:28] wire [74:0] sigSum = {sigSum_hi, io_fromPreMul_bit0AlignedSigC_0}; // @[MulAddRecFN.scala:169:7, :192:12] wire [1:0] _CDom_sExp_T = {1'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :203:69] wire [10:0] _GEN = {io_fromPreMul_sExpSum_0[9], io_fromPreMul_sExpSum_0}; // @[MulAddRecFN.scala:169:7, :203:43] wire [10:0] _CDom_sExp_T_1 = _GEN - {{9{_CDom_sExp_T[1]}}, _CDom_sExp_T}; // @[MulAddRecFN.scala:203:{43,69}] wire [9:0] _CDom_sExp_T_2 = _CDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:203:43] wire [9:0] CDom_sExp = _CDom_sExp_T_2; // @[MulAddRecFN.scala:203:43] wire [49:0] _CDom_absSigSum_T = sigSum[74:25]; // @[MulAddRecFN.scala:192:12, :206:20] wire [49:0] _CDom_absSigSum_T_1 = ~_CDom_absSigSum_T; // @[MulAddRecFN.scala:206:{13,20}] wire [1:0] _CDom_absSigSum_T_2 = io_fromPreMul_highAlignedSigC_0[25:24]; // @[MulAddRecFN.scala:169:7, :209:46] wire [2:0] _CDom_absSigSum_T_3 = {1'h0, _CDom_absSigSum_T_2}; // @[MulAddRecFN.scala:207:22, :209:46] wire [46:0] _CDom_absSigSum_T_4 = sigSum[72:26]; // @[MulAddRecFN.scala:192:12, :210:23] wire [49:0] _CDom_absSigSum_T_5 = {_CDom_absSigSum_T_3, _CDom_absSigSum_T_4}; // @[MulAddRecFN.scala:207:22, :209:71, :210:23] wire [49:0] CDom_absSigSum = io_fromPreMul_doSubMags_0 ? _CDom_absSigSum_T_1 : _CDom_absSigSum_T_5; // @[MulAddRecFN.scala:169:7, :205:12, :206:13, :209:71] wire [23:0] _CDom_absSigSumExtra_T = sigSum[24:1]; // @[MulAddRecFN.scala:192:12, :215:21] wire [23:0] _CDom_absSigSumExtra_T_1 = ~_CDom_absSigSumExtra_T; // @[MulAddRecFN.scala:215:{14,21}] wire _CDom_absSigSumExtra_T_2 = |_CDom_absSigSumExtra_T_1; // @[MulAddRecFN.scala:215:{14,36}] wire [24:0] _CDom_absSigSumExtra_T_3 = sigSum[25:1]; // @[MulAddRecFN.scala:192:12, :216:19] wire _CDom_absSigSumExtra_T_4 = |_CDom_absSigSumExtra_T_3; // @[MulAddRecFN.scala:216:{19,37}] wire CDom_absSigSumExtra = io_fromPreMul_doSubMags_0 ? _CDom_absSigSumExtra_T_2 : _CDom_absSigSumExtra_T_4; // @[MulAddRecFN.scala:169:7, :214:12, :215:36, :216:37] wire [80:0] _CDom_mainSig_T = {31'h0, CDom_absSigSum} << io_fromPreMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:169:7, :205:12, :219:24] wire [28:0] CDom_mainSig = _CDom_mainSig_T[49:21]; // @[MulAddRecFN.scala:219:{24,56}] wire [23:0] _CDom_reduced4SigExtra_T = CDom_absSigSum[23:0]; // @[MulAddRecFN.scala:205:12, :222:36] wire [26:0] _CDom_reduced4SigExtra_T_1 = {_CDom_reduced4SigExtra_T, 3'h0}; // @[MulAddRecFN.scala:169:7, :172:16, :222:{36,53}] wire _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:123:57] wire CDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:118:30] wire [3:0] _CDom_reduced4SigExtra_reducedVec_0_T = _CDom_reduced4SigExtra_T_1[3:0]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_0_T_1 = |_CDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_0 = _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_1_T = _CDom_reduced4SigExtra_T_1[7:4]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_1_T_1 = |_CDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_1 = _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_2_T = _CDom_reduced4SigExtra_T_1[11:8]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_2_T_1 = |_CDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_2 = _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_3_T = _CDom_reduced4SigExtra_T_1[15:12]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_3_T_1 = |_CDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_3 = _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_4_T = _CDom_reduced4SigExtra_T_1[19:16]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_4_T_1 = |_CDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_4 = _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_5_T = _CDom_reduced4SigExtra_T_1[23:20]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_5_T_1 = |_CDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_5 = _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54] wire [2:0] _CDom_reduced4SigExtra_reducedVec_6_T = _CDom_reduced4SigExtra_T_1[26:24]; // @[primitives.scala:123:15] assign _CDom_reduced4SigExtra_reducedVec_6_T_1 = |_CDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:123:{15,57}] assign CDom_reduced4SigExtra_reducedVec_6 = _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :123:57] wire [1:0] CDom_reduced4SigExtra_lo_hi = {CDom_reduced4SigExtra_reducedVec_2, CDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20] wire [2:0] CDom_reduced4SigExtra_lo = {CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20] wire [1:0] CDom_reduced4SigExtra_hi_lo = {CDom_reduced4SigExtra_reducedVec_4, CDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20] wire [1:0] CDom_reduced4SigExtra_hi_hi = {CDom_reduced4SigExtra_reducedVec_6, CDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20] wire [3:0] CDom_reduced4SigExtra_hi = {CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:124:20] wire [6:0] _CDom_reduced4SigExtra_T_2 = {CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo}; // @[primitives.scala:124:20] wire [2:0] _CDom_reduced4SigExtra_T_3 = io_fromPreMul_CDom_CAlignDist_0[4:2]; // @[MulAddRecFN.scala:169:7, :223:51] wire [2:0] _CDom_reduced4SigExtra_T_4 = ~_CDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21] wire [8:0] CDom_reduced4SigExtra_shift = $signed(9'sh100 >>> _CDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56] wire [5:0] _CDom_reduced4SigExtra_T_5 = CDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22] wire [3:0] _CDom_reduced4SigExtra_T_6 = _CDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22] wire [1:0] _CDom_reduced4SigExtra_T_7 = _CDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_8 = _CDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_9 = _CDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_10 = {_CDom_reduced4SigExtra_T_8, _CDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_11 = _CDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_12 = _CDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_13 = _CDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_14 = {_CDom_reduced4SigExtra_T_12, _CDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20] wire [3:0] _CDom_reduced4SigExtra_T_15 = {_CDom_reduced4SigExtra_T_10, _CDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_16 = _CDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22] wire _CDom_reduced4SigExtra_T_17 = _CDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_18 = _CDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_19 = {_CDom_reduced4SigExtra_T_17, _CDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20] wire [5:0] _CDom_reduced4SigExtra_T_20 = {_CDom_reduced4SigExtra_T_15, _CDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20] wire [6:0] _CDom_reduced4SigExtra_T_21 = {1'h0, _CDom_reduced4SigExtra_T_2[5:0] & _CDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :124:20] wire CDom_reduced4SigExtra = |_CDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:222:72, :223:73] wire [25:0] _CDom_sig_T = CDom_mainSig[28:3]; // @[MulAddRecFN.scala:219:56, :225:25] wire [2:0] _CDom_sig_T_1 = CDom_mainSig[2:0]; // @[MulAddRecFN.scala:219:56, :226:25] wire _CDom_sig_T_2 = |_CDom_sig_T_1; // @[MulAddRecFN.scala:226:{25,32}] wire _CDom_sig_T_3 = _CDom_sig_T_2 | CDom_reduced4SigExtra; // @[MulAddRecFN.scala:223:73, :226:{32,36}] wire _CDom_sig_T_4 = _CDom_sig_T_3 | CDom_absSigSumExtra; // @[MulAddRecFN.scala:214:12, :226:{36,61}] wire [26:0] CDom_sig = {_CDom_sig_T, _CDom_sig_T_4}; // @[MulAddRecFN.scala:225:{12,25}, :226:61] wire notCDom_signSigSum = sigSum[51]; // @[MulAddRecFN.scala:192:12, :232:36] wire [50:0] _notCDom_absSigSum_T = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20] wire [50:0] _notCDom_absSigSum_T_2 = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20, :236:19] wire [50:0] _notCDom_absSigSum_T_1 = ~_notCDom_absSigSum_T; // @[MulAddRecFN.scala:235:{13,20}] wire [51:0] _notCDom_absSigSum_T_3 = {1'h0, _notCDom_absSigSum_T_2} + {51'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :236:{19,41}] wire [50:0] _notCDom_absSigSum_T_4 = _notCDom_absSigSum_T_3[50:0]; // @[MulAddRecFN.scala:236:41] wire [50:0] notCDom_absSigSum = notCDom_signSigSum ? _notCDom_absSigSum_T_1 : _notCDom_absSigSum_T_4; // @[MulAddRecFN.scala:232:36, :234:12, :235:13, :236:41] wire _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:106:57] wire notCDom_reduced2AbsSigSum_reducedVec_0; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_1; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_2; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_3; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_4; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_5; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_6; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_7; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_8; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_9; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_10; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_11; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_12; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_13; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_14; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_15; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_16; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_17; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_18; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_19; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_20; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_21; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_22; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_23; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_24; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_25; // @[primitives.scala:101:30] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_0_T = notCDom_absSigSum[1:0]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_0_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_0 = _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_1_T = notCDom_absSigSum[3:2]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_1_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_1 = _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_2_T = notCDom_absSigSum[5:4]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_2_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_2 = _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_3_T = notCDom_absSigSum[7:6]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_3_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_3 = _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_4_T = notCDom_absSigSum[9:8]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_4_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_4 = _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_5_T = notCDom_absSigSum[11:10]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_5_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_5 = _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_6_T = notCDom_absSigSum[13:12]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_6_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_6 = _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_7_T = notCDom_absSigSum[15:14]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_7_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_7 = _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_8_T = notCDom_absSigSum[17:16]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_8_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_8 = _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_9_T = notCDom_absSigSum[19:18]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_9_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_9 = _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_10_T = notCDom_absSigSum[21:20]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_10_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_10 = _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_11_T = notCDom_absSigSum[23:22]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_11_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_11 = _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_12_T = notCDom_absSigSum[25:24]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_12_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_12 = _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_13_T = notCDom_absSigSum[27:26]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_13_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_13 = _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_14_T = notCDom_absSigSum[29:28]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_14_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_14 = _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_15_T = notCDom_absSigSum[31:30]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_15_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_15 = _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_16_T = notCDom_absSigSum[33:32]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_16_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_16 = _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_17_T = notCDom_absSigSum[35:34]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_17_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_17 = _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_18_T = notCDom_absSigSum[37:36]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_18_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_18 = _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_19_T = notCDom_absSigSum[39:38]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_19_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_19 = _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_20_T = notCDom_absSigSum[41:40]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_20_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_20 = _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_21_T = notCDom_absSigSum[43:42]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_21_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_21 = _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_22_T = notCDom_absSigSum[45:44]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_22_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_22 = _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_23_T = notCDom_absSigSum[47:46]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_23_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_23 = _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_24_T = notCDom_absSigSum[49:48]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_24_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_24 = _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:101:30, :103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_25_T = notCDom_absSigSum[50]; // @[primitives.scala:106:15] assign _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = _notCDom_reduced2AbsSigSum_reducedVec_25_T; // @[primitives.scala:106:{15,57}] assign notCDom_reduced2AbsSigSum_reducedVec_25 = _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:101:30, :106:57] wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_2, notCDom_reduced2AbsSigSum_reducedVec_1}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_0}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_5, notCDom_reduced2AbsSigSum_reducedVec_4}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_hi = {notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_3}; // @[primitives.scala:101:30, :107:20] wire [5:0] notCDom_reduced2AbsSigSum_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_8, notCDom_reduced2AbsSigSum_reducedVec_7}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_hi_lo = {notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_6}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_10, notCDom_reduced2AbsSigSum_reducedVec_9}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_12, notCDom_reduced2AbsSigSum_reducedVec_11}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced2AbsSigSum_lo_hi_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo}; // @[primitives.scala:107:20] wire [6:0] notCDom_reduced2AbsSigSum_lo_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo}; // @[primitives.scala:107:20] wire [12:0] notCDom_reduced2AbsSigSum_lo = {notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_15, notCDom_reduced2AbsSigSum_reducedVec_14}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_lo = {notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_13}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_18, notCDom_reduced2AbsSigSum_reducedVec_17}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_hi = {notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_16}; // @[primitives.scala:101:30, :107:20] wire [5:0] notCDom_reduced2AbsSigSum_hi_lo = {notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_21, notCDom_reduced2AbsSigSum_reducedVec_20}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_hi_lo = {notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_19}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_23, notCDom_reduced2AbsSigSum_reducedVec_22}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_25, notCDom_reduced2AbsSigSum_reducedVec_24}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced2AbsSigSum_hi_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo}; // @[primitives.scala:107:20] wire [6:0] notCDom_reduced2AbsSigSum_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo}; // @[primitives.scala:107:20] wire [12:0] notCDom_reduced2AbsSigSum_hi = {notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo}; // @[primitives.scala:107:20] wire [25:0] notCDom_reduced2AbsSigSum = {notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo}; // @[primitives.scala:107:20] wire _notCDom_normDistReduced2_T = notCDom_reduced2AbsSigSum[0]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_1 = notCDom_reduced2AbsSigSum[1]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_2 = notCDom_reduced2AbsSigSum[2]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_3 = notCDom_reduced2AbsSigSum[3]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_4 = notCDom_reduced2AbsSigSum[4]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_5 = notCDom_reduced2AbsSigSum[5]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_6 = notCDom_reduced2AbsSigSum[6]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_7 = notCDom_reduced2AbsSigSum[7]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_8 = notCDom_reduced2AbsSigSum[8]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_9 = notCDom_reduced2AbsSigSum[9]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_10 = notCDom_reduced2AbsSigSum[10]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_11 = notCDom_reduced2AbsSigSum[11]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_12 = notCDom_reduced2AbsSigSum[12]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_13 = notCDom_reduced2AbsSigSum[13]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_14 = notCDom_reduced2AbsSigSum[14]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_15 = notCDom_reduced2AbsSigSum[15]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_16 = notCDom_reduced2AbsSigSum[16]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_17 = notCDom_reduced2AbsSigSum[17]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_18 = notCDom_reduced2AbsSigSum[18]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_19 = notCDom_reduced2AbsSigSum[19]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_20 = notCDom_reduced2AbsSigSum[20]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_21 = notCDom_reduced2AbsSigSum[21]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_22 = notCDom_reduced2AbsSigSum[22]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_23 = notCDom_reduced2AbsSigSum[23]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_24 = notCDom_reduced2AbsSigSum[24]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_25 = notCDom_reduced2AbsSigSum[25]; // @[primitives.scala:91:52, :107:20] wire [4:0] _notCDom_normDistReduced2_T_26 = {4'hC, ~_notCDom_normDistReduced2_T_1}; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_27 = _notCDom_normDistReduced2_T_2 ? 5'h17 : _notCDom_normDistReduced2_T_26; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_28 = _notCDom_normDistReduced2_T_3 ? 5'h16 : _notCDom_normDistReduced2_T_27; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_29 = _notCDom_normDistReduced2_T_4 ? 5'h15 : _notCDom_normDistReduced2_T_28; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_30 = _notCDom_normDistReduced2_T_5 ? 5'h14 : _notCDom_normDistReduced2_T_29; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_31 = _notCDom_normDistReduced2_T_6 ? 5'h13 : _notCDom_normDistReduced2_T_30; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_32 = _notCDom_normDistReduced2_T_7 ? 5'h12 : _notCDom_normDistReduced2_T_31; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_33 = _notCDom_normDistReduced2_T_8 ? 5'h11 : _notCDom_normDistReduced2_T_32; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_34 = _notCDom_normDistReduced2_T_9 ? 5'h10 : _notCDom_normDistReduced2_T_33; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_35 = _notCDom_normDistReduced2_T_10 ? 5'hF : _notCDom_normDistReduced2_T_34; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_36 = _notCDom_normDistReduced2_T_11 ? 5'hE : _notCDom_normDistReduced2_T_35; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_37 = _notCDom_normDistReduced2_T_12 ? 5'hD : _notCDom_normDistReduced2_T_36; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_38 = _notCDom_normDistReduced2_T_13 ? 5'hC : _notCDom_normDistReduced2_T_37; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_39 = _notCDom_normDistReduced2_T_14 ? 5'hB : _notCDom_normDistReduced2_T_38; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_40 = _notCDom_normDistReduced2_T_15 ? 5'hA : _notCDom_normDistReduced2_T_39; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_41 = _notCDom_normDistReduced2_T_16 ? 5'h9 : _notCDom_normDistReduced2_T_40; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_42 = _notCDom_normDistReduced2_T_17 ? 5'h8 : _notCDom_normDistReduced2_T_41; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_43 = _notCDom_normDistReduced2_T_18 ? 5'h7 : _notCDom_normDistReduced2_T_42; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_44 = _notCDom_normDistReduced2_T_19 ? 5'h6 : _notCDom_normDistReduced2_T_43; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_45 = _notCDom_normDistReduced2_T_20 ? 5'h5 : _notCDom_normDistReduced2_T_44; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_46 = _notCDom_normDistReduced2_T_21 ? 5'h4 : _notCDom_normDistReduced2_T_45; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_47 = _notCDom_normDistReduced2_T_22 ? 5'h3 : _notCDom_normDistReduced2_T_46; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_48 = _notCDom_normDistReduced2_T_23 ? 5'h2 : _notCDom_normDistReduced2_T_47; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_49 = _notCDom_normDistReduced2_T_24 ? 5'h1 : _notCDom_normDistReduced2_T_48; // @[Mux.scala:50:70] wire [4:0] notCDom_normDistReduced2 = _notCDom_normDistReduced2_T_25 ? 5'h0 : _notCDom_normDistReduced2_T_49; // @[Mux.scala:50:70] wire [5:0] notCDom_nearNormDist = {notCDom_normDistReduced2, 1'h0}; // @[Mux.scala:50:70] wire [6:0] _notCDom_sExp_T = {1'h0, notCDom_nearNormDist}; // @[MulAddRecFN.scala:240:56, :241:76] wire [10:0] _notCDom_sExp_T_1 = _GEN - {{4{_notCDom_sExp_T[6]}}, _notCDom_sExp_T}; // @[MulAddRecFN.scala:203:43, :241:{46,76}] wire [9:0] _notCDom_sExp_T_2 = _notCDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:241:46] wire [9:0] notCDom_sExp = _notCDom_sExp_T_2; // @[MulAddRecFN.scala:241:46] wire [113:0] _notCDom_mainSig_T = {63'h0, notCDom_absSigSum} << notCDom_nearNormDist; // @[MulAddRecFN.scala:234:12, :240:56, :243:27] wire [28:0] notCDom_mainSig = _notCDom_mainSig_T[51:23]; // @[MulAddRecFN.scala:243:{27,50}] wire [12:0] _notCDom_reduced4SigExtra_T = notCDom_reduced2AbsSigSum[12:0]; // @[primitives.scala:107:20] wire [12:0] _notCDom_reduced4SigExtra_T_1 = _notCDom_reduced4SigExtra_T; // @[MulAddRecFN.scala:247:{39,55}] wire _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:106:57] wire notCDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:101:30] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_0_T = _notCDom_reduced4SigExtra_T_1[1:0]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_0_T_1 = |_notCDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_0 = _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_1_T = _notCDom_reduced4SigExtra_T_1[3:2]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_1_T_1 = |_notCDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_1 = _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_2_T = _notCDom_reduced4SigExtra_T_1[5:4]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_2_T_1 = |_notCDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_2 = _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_3_T = _notCDom_reduced4SigExtra_T_1[7:6]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_3_T_1 = |_notCDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_3 = _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_4_T = _notCDom_reduced4SigExtra_T_1[9:8]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_4_T_1 = |_notCDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_4 = _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_5_T = _notCDom_reduced4SigExtra_T_1[11:10]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_5_T_1 = |_notCDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_5 = _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54] wire _notCDom_reduced4SigExtra_reducedVec_6_T = _notCDom_reduced4SigExtra_T_1[12]; // @[primitives.scala:106:15] assign _notCDom_reduced4SigExtra_reducedVec_6_T_1 = _notCDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:106:{15,57}] assign notCDom_reduced4SigExtra_reducedVec_6 = _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:101:30, :106:57] wire [1:0] notCDom_reduced4SigExtra_lo_hi = {notCDom_reduced4SigExtra_reducedVec_2, notCDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced4SigExtra_lo = {notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced4SigExtra_hi_lo = {notCDom_reduced4SigExtra_reducedVec_4, notCDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced4SigExtra_hi_hi = {notCDom_reduced4SigExtra_reducedVec_6, notCDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced4SigExtra_hi = {notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:107:20] wire [6:0] _notCDom_reduced4SigExtra_T_2 = {notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo}; // @[primitives.scala:107:20] wire [3:0] _notCDom_reduced4SigExtra_T_3 = notCDom_normDistReduced2[4:1]; // @[Mux.scala:50:70] wire [3:0] _notCDom_reduced4SigExtra_T_4 = ~_notCDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21] wire [16:0] notCDom_reduced4SigExtra_shift = $signed(17'sh10000 >>> _notCDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56] wire [5:0] _notCDom_reduced4SigExtra_T_5 = notCDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22] wire [3:0] _notCDom_reduced4SigExtra_T_6 = _notCDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22] wire [1:0] _notCDom_reduced4SigExtra_T_7 = _notCDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_8 = _notCDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_9 = _notCDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_10 = {_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_11 = _notCDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_12 = _notCDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_13 = _notCDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_14 = {_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20] wire [3:0] _notCDom_reduced4SigExtra_T_15 = {_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_16 = _notCDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22] wire _notCDom_reduced4SigExtra_T_17 = _notCDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_18 = _notCDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_19 = {_notCDom_reduced4SigExtra_T_17, _notCDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20] wire [5:0] _notCDom_reduced4SigExtra_T_20 = {_notCDom_reduced4SigExtra_T_15, _notCDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20] wire [6:0] _notCDom_reduced4SigExtra_T_21 = {1'h0, _notCDom_reduced4SigExtra_T_2[5:0] & _notCDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :107:20] wire notCDom_reduced4SigExtra = |_notCDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:247:78, :249:11] wire [25:0] _notCDom_sig_T = notCDom_mainSig[28:3]; // @[MulAddRecFN.scala:243:50, :251:28] wire [2:0] _notCDom_sig_T_1 = notCDom_mainSig[2:0]; // @[MulAddRecFN.scala:243:50, :252:28] wire _notCDom_sig_T_2 = |_notCDom_sig_T_1; // @[MulAddRecFN.scala:252:{28,35}] wire _notCDom_sig_T_3 = _notCDom_sig_T_2 | notCDom_reduced4SigExtra; // @[MulAddRecFN.scala:249:11, :252:{35,39}] wire [26:0] notCDom_sig = {_notCDom_sig_T, _notCDom_sig_T_3}; // @[MulAddRecFN.scala:251:{12,28}, :252:39] wire [1:0] _notCDom_completeCancellation_T = notCDom_sig[26:25]; // @[MulAddRecFN.scala:251:12, :255:21] wire notCDom_completeCancellation = _notCDom_completeCancellation_T == 2'h0; // @[primitives.scala:103:54] wire _notCDom_sign_T = io_fromPreMul_signProd_0 ^ notCDom_signSigSum; // @[MulAddRecFN.scala:169:7, :232:36, :259:36] wire notCDom_sign = ~notCDom_completeCancellation & _notCDom_sign_T; // @[MulAddRecFN.scala:255:50, :257:12, :259:36] wire _GEN_0 = io_fromPreMul_isInfA_0 | io_fromPreMul_isInfB_0; // @[MulAddRecFN.scala:169:7, :264:49] wire notNaN_isInfProd; // @[MulAddRecFN.scala:264:49] assign notNaN_isInfProd = _GEN_0; // @[MulAddRecFN.scala:264:49] wire _io_invalidExc_T_5; // @[MulAddRecFN.scala:275:36] assign _io_invalidExc_T_5 = _GEN_0; // @[MulAddRecFN.scala:264:49, :275:36] assign notNaN_isInfOut = notNaN_isInfProd | io_fromPreMul_isInfC_0; // @[MulAddRecFN.scala:169:7, :264:49, :265:44] assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulAddRecFN.scala:169:7, :265:44] wire _notNaN_addZeros_T = io_fromPreMul_isZeroA_0 | io_fromPreMul_isZeroB_0; // @[MulAddRecFN.scala:169:7, :267:32] wire notNaN_addZeros = _notNaN_addZeros_T & io_fromPreMul_isZeroC_0; // @[MulAddRecFN.scala:169:7, :267:{32,58}] wire _io_rawOut_sign_T_4 = notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :287:26] wire _io_invalidExc_T = io_fromPreMul_isInfA_0 & io_fromPreMul_isZeroB_0; // @[MulAddRecFN.scala:169:7, :272:31] wire _io_invalidExc_T_1 = io_fromPreMul_isSigNaNAny_0 | _io_invalidExc_T; // @[MulAddRecFN.scala:169:7, :271:35, :272:31] wire _io_invalidExc_T_2 = io_fromPreMul_isZeroA_0 & io_fromPreMul_isInfB_0; // @[MulAddRecFN.scala:169:7, :273:32] wire _io_invalidExc_T_3 = _io_invalidExc_T_1 | _io_invalidExc_T_2; // @[MulAddRecFN.scala:271:35, :272:57, :273:32] wire _io_invalidExc_T_4 = ~io_fromPreMul_isNaNAOrB_0; // @[MulAddRecFN.scala:169:7, :274:10] wire _io_invalidExc_T_6 = _io_invalidExc_T_4 & _io_invalidExc_T_5; // @[MulAddRecFN.scala:274:{10,36}, :275:36] wire _io_invalidExc_T_7 = _io_invalidExc_T_6 & io_fromPreMul_isInfC_0; // @[MulAddRecFN.scala:169:7, :274:36, :275:61] wire _io_invalidExc_T_8 = _io_invalidExc_T_7 & io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :275:61, :276:35] assign _io_invalidExc_T_9 = _io_invalidExc_T_3 | _io_invalidExc_T_8; // @[MulAddRecFN.scala:272:57, :273:57, :276:35] assign io_invalidExc_0 = _io_invalidExc_T_9; // @[MulAddRecFN.scala:169:7, :273:57] assign _io_rawOut_isNaN_T = io_fromPreMul_isNaNAOrB_0 | io_fromPreMul_isNaNC_0; // @[MulAddRecFN.scala:169:7, :278:48] assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:169:7, :278:48] wire _io_rawOut_isZero_T = ~io_fromPreMul_CIsDominant_0; // @[MulAddRecFN.scala:169:7, :283:14] wire _io_rawOut_isZero_T_1 = _io_rawOut_isZero_T & notCDom_completeCancellation; // @[MulAddRecFN.scala:255:50, :283:{14,42}] assign _io_rawOut_isZero_T_2 = notNaN_addZeros | _io_rawOut_isZero_T_1; // @[MulAddRecFN.scala:267:58, :282:25, :283:42] assign io_rawOut_isZero_0 = _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:169:7, :282:25] wire _io_rawOut_sign_T = notNaN_isInfProd & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :264:49, :285:27] wire _io_rawOut_sign_T_1 = io_fromPreMul_isInfC_0 & opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :286:31] wire _io_rawOut_sign_T_2 = _io_rawOut_sign_T | _io_rawOut_sign_T_1; // @[MulAddRecFN.scala:285:{27,54}, :286:31] wire _io_rawOut_sign_T_5 = _io_rawOut_sign_T_4 & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :287:{26,48}] wire _io_rawOut_sign_T_6 = _io_rawOut_sign_T_5 & opSignC; // @[MulAddRecFN.scala:190:42, :287:48, :288:36] wire _io_rawOut_sign_T_7 = _io_rawOut_sign_T_2 | _io_rawOut_sign_T_6; // @[MulAddRecFN.scala:285:54, :286:43, :288:36] wire _io_rawOut_sign_T_11 = _io_rawOut_sign_T_7; // @[MulAddRecFN.scala:286:43, :288:48] wire _io_rawOut_sign_T_9 = io_fromPreMul_signProd_0 | opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :290:37] wire _io_rawOut_sign_T_12 = ~notNaN_isInfOut; // @[MulAddRecFN.scala:265:44, :291:10] wire _io_rawOut_sign_T_13 = ~notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :291:31] wire _io_rawOut_sign_T_14 = _io_rawOut_sign_T_12 & _io_rawOut_sign_T_13; // @[MulAddRecFN.scala:291:{10,28,31}] wire _io_rawOut_sign_T_15 = io_fromPreMul_CIsDominant_0 ? opSignC : notCDom_sign; // @[MulAddRecFN.scala:169:7, :190:42, :257:12, :292:17] wire _io_rawOut_sign_T_16 = _io_rawOut_sign_T_14 & _io_rawOut_sign_T_15; // @[MulAddRecFN.scala:291:{28,49}, :292:17] assign _io_rawOut_sign_T_17 = _io_rawOut_sign_T_11 | _io_rawOut_sign_T_16; // @[MulAddRecFN.scala:288:48, :290:50, :291:49] assign io_rawOut_sign_0 = _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:169:7, :290:50] assign _io_rawOut_sExp_T = io_fromPreMul_CIsDominant_0 ? CDom_sExp : notCDom_sExp; // @[MulAddRecFN.scala:169:7, :203:43, :241:46, :293:26] assign io_rawOut_sExp_0 = _io_rawOut_sExp_T; // @[MulAddRecFN.scala:169:7, :293:26] assign _io_rawOut_sig_T = io_fromPreMul_CIsDominant_0 ? CDom_sig : notCDom_sig; // @[MulAddRecFN.scala:169:7, :225:12, :251:12, :294:25] assign io_rawOut_sig_0 = _io_rawOut_sig_T; // @[MulAddRecFN.scala:169:7, :294:25] assign io_invalidExc = io_invalidExc_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sign = io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sig = io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File RegisterFile.scala: package saturn.backend import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import freechips.rocketchip.tile.{CoreModule} import freechips.rocketchip.util._ import saturn.common._ class OldestRRArbiter(val n: Int)(implicit p: Parameters) extends Module { val io = IO(new ArbiterIO(new VectorReadReq, n)) val arb = Module(new RRArbiter(new VectorReadReq, n)) io <> arb.io val oldest_oh = io.in.map(i => i.valid && i.bits.oldest) //assert(PopCount(oldest_oh) <= 1.U) when (oldest_oh.orR) { io.chosen := VecInit(oldest_oh).asUInt io.out.valid := true.B io.out.bits := Mux1H(oldest_oh, io.in.map(_.bits)) for (i <- 0 until n) { io.in(i).ready := oldest_oh(i) && io.out.ready } } } class RegisterReadXbar(n: Int, banks: Int)(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams { val io = IO(new Bundle { val in = Vec(n, Flipped(new VectorReadIO)) val out = Vec(banks, new VectorReadIO) }) val arbs = Seq.fill(banks) { Module(new OldestRRArbiter(n)) } for (i <- 0 until banks) { io.out(i).req <> arbs(i).io.out } val bankOffset = log2Ceil(banks) for (i <- 0 until n) { val bank_sel = if (bankOffset == 0) true.B else UIntToOH(io.in(i).req.bits.eg(bankOffset-1,0)) for (j <- 0 until banks) { arbs(j).io.in(i).valid := io.in(i).req.valid && bank_sel(j) arbs(j).io.in(i).bits.eg := io.in(i).req.bits.eg >> bankOffset arbs(j).io.in(i).bits.oldest := io.in(i).req.bits.oldest } io.in(i).req.ready := Mux1H(bank_sel, arbs.map(_.io.in(i).ready)) io.in(i).resp := Mux1H(bank_sel, io.out.map(_.resp)) } } class RegisterFileBank(reads: Int, maskReads: Int, rows: Int, maskRows: Int)(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams { val io = IO(new Bundle { val read = Vec(reads, Flipped(new VectorReadIO)) val mask_read = Vec(maskReads, Flipped(new VectorReadIO)) val write = Input(Valid(new VectorWrite(dLen))) val ll_write = Flipped(Decoupled(new VectorWrite(dLen))) }) val ll_write_valid = RegInit(false.B) val ll_write_bits = Reg(new VectorWrite(dLen)) val vrf = Mem(rows, Vec(dLen, Bool())) val v0_mask = Mem(maskRows, Vec(dLen, Bool())) for (read <- io.read) { read.req.ready := !(ll_write_valid && read.req.bits.eg === ll_write_bits.eg) read.resp := DontCare when (read.req.valid) { read.resp := vrf.read(read.req.bits.eg).asUInt } } for (mask_read <- io.mask_read) { mask_read.req.ready := !(ll_write_valid && mask_read.req.bits.eg === ll_write_bits.eg) mask_read.resp := DontCare when (mask_read.req.valid) { mask_read.resp := v0_mask.read(mask_read.req.bits.eg).asUInt } } val write = WireInit(io.write) io.ll_write.ready := false.B if (vParams.vrfHiccupBuffer) { when (!io.write.valid) { // drain hiccup buffer write.valid := ll_write_valid || io.ll_write.valid write.bits := Mux(ll_write_valid, ll_write_bits, io.ll_write.bits) ll_write_valid := false.B when (io.ll_write.valid && ll_write_valid) { ll_write_valid := true.B ll_write_bits := io.ll_write.bits } io.ll_write.ready := true.B } .elsewhen (!ll_write_valid) { // fill hiccup buffer when (io.ll_write.valid) { ll_write_valid := true.B ll_write_bits := io.ll_write.bits } io.ll_write.ready := true.B } } else { when (!io.write.valid) { io.ll_write.ready := true.B write.valid := io.ll_write.valid write.bits := io.ll_write.bits } } when (write.valid) { vrf.write( write.bits.eg, VecInit(write.bits.data.asBools), write.bits.mask.asBools) when (write.bits.eg < maskRows.U) { v0_mask.write( write.bits.eg, VecInit(write.bits.data.asBools), write.bits.mask.asBools) } } } class RegisterFile(reads: Seq[Int], maskReads: Seq[Int], pipeWrites: Int, llWrites: Int)(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams { val nBanks = vParams.vrfBanking // Support 1, 2, and 4 banks for the VRF require(nBanks == 1 || nBanks == 2 || nBanks == 4) val io = IO(new Bundle { val read = MixedVec(reads.map(rc => Vec(rc, Flipped(new VectorReadIO)))) val mask_read = MixedVec(maskReads.map(rc => Vec(rc, Flipped(new VectorReadIO)))) val pipe_writes = Vec(pipeWrites, Input(Valid(new VectorWrite(dLen)))) val ll_writes = Vec(llWrites, Flipped(Decoupled(new VectorWrite(dLen)))) }) val vrf = Seq.fill(nBanks) { Module(new RegisterFileBank(reads.size, maskReads.size, egsTotal/nBanks, if (egsPerVReg < nBanks) 1 else egsPerVReg / nBanks)) } reads.zipWithIndex.foreach { case (rc, i) => val xbar = Module(new RegisterReadXbar(rc, nBanks)) vrf.zipWithIndex.foreach { case (bank, j) => bank.io.read(i) <> xbar.io.out(j) } xbar.io.in <> io.read(i) } maskReads.zipWithIndex.foreach { case (rc, i) => val mask_xbar = Module(new RegisterReadXbar(rc, nBanks)) vrf.zipWithIndex.foreach { case (bank, j) => bank.io.mask_read(i) <> mask_xbar.io.out(j) } mask_xbar.io.in <> io.mask_read(i) } io.ll_writes.foreach(_.ready := false.B) vrf.zipWithIndex.foreach { case (rf, i) => val bank_match = io.pipe_writes.map { w => (w.bits.bankId === i.U) && w.valid } val bank_write_data = Mux1H(bank_match, io.pipe_writes.map(_.bits.data)) val bank_write_mask = Mux1H(bank_match, io.pipe_writes.map(_.bits.mask)) val bank_write_eg = Mux1H(bank_match, io.pipe_writes.map(_.bits.eg)) val bank_write_valid = bank_match.orR rf.io.write.valid := bank_write_valid rf.io.write.bits.data := bank_write_data rf.io.write.bits.mask := bank_write_mask rf.io.write.bits.eg := bank_write_eg >> vrfBankBits when (bank_write_valid) { PopCount(bank_match) === 1.U } val ll_arb = Module(new Arbiter(new VectorWrite(dLen), llWrites)) rf.io.ll_write <> ll_arb.io.out io.ll_writes.zipWithIndex.foreach { case (w, j) => ll_arb.io.in(j).valid := w.valid && w.bits.bankId === i.U ll_arb.io.in(j).bits.eg := w.bits.eg >> vrfBankBits ll_arb.io.in(j).bits.data := w.bits.data ll_arb.io.in(j).bits.mask := w.bits.mask when (ll_arb.io.in(j).ready && w.bits.bankId === i.U) { w.ready := true.B } } } }

module RegisterReadXbar( // @[RegisterFile.scala:27:7] input clock, // @[RegisterFile.scala:27:7] output io_in_0_req_ready, // @[RegisterFile.scala:28:14] input io_in_0_req_valid, // @[RegisterFile.scala:28:14] input [4:0] io_in_0_req_bits_eg, // @[RegisterFile.scala:28:14] input io_in_0_req_bits_oldest, // @[RegisterFile.scala:28:14] output [127:0] io_in_0_resp, // @[RegisterFile.scala:28:14] output io_in_1_req_ready, // @[RegisterFile.scala:28:14] input io_in_1_req_valid, // @[RegisterFile.scala:28:14] input [4:0] io_in_1_req_bits_eg, // @[RegisterFile.scala:28:14] input io_in_1_req_bits_oldest, // @[RegisterFile.scala:28:14] output [127:0] io_in_1_resp, // @[RegisterFile.scala:28:14] output io_in_2_req_ready, // @[RegisterFile.scala:28:14] input io_in_2_req_valid, // @[RegisterFile.scala:28:14] input [4:0] io_in_2_req_bits_eg, // @[RegisterFile.scala:28:14] output [127:0] io_in_2_resp, // @[RegisterFile.scala:28:14] input io_out_0_req_ready, // @[RegisterFile.scala:28:14] output io_out_0_req_valid, // @[RegisterFile.scala:28:14] output [4:0] io_out_0_req_bits_eg, // @[RegisterFile.scala:28:14] input [127:0] io_out_0_resp, // @[RegisterFile.scala:28:14] input io_out_1_req_ready, // @[RegisterFile.scala:28:14] output io_out_1_req_valid, // @[RegisterFile.scala:28:14] output [4:0] io_out_1_req_bits_eg, // @[RegisterFile.scala:28:14] input [127:0] io_out_1_resp, // @[RegisterFile.scala:28:14] input io_out_2_req_ready, // @[RegisterFile.scala:28:14] output io_out_2_req_valid, // @[RegisterFile.scala:28:14] output [4:0] io_out_2_req_bits_eg, // @[RegisterFile.scala:28:14] input [127:0] io_out_2_resp, // @[RegisterFile.scala:28:14] input io_out_3_req_ready, // @[RegisterFile.scala:28:14] output io_out_3_req_valid, // @[RegisterFile.scala:28:14] output [4:0] io_out_3_req_bits_eg, // @[RegisterFile.scala:28:14] input [127:0] io_out_3_resp // @[RegisterFile.scala:28:14] ); wire _arbs_3_io_in_0_ready; // @[RegisterFile.scala:33:38] wire _arbs_3_io_in_1_ready; // @[RegisterFile.scala:33:38] wire _arbs_3_io_in_2_ready; // @[RegisterFile.scala:33:38] wire _arbs_2_io_in_0_ready; // @[RegisterFile.scala:33:38] wire _arbs_2_io_in_1_ready; // @[RegisterFile.scala:33:38] wire _arbs_2_io_in_2_ready; // @[RegisterFile.scala:33:38] wire _arbs_1_io_in_0_ready; // @[RegisterFile.scala:33:38] wire _arbs_1_io_in_1_ready; // @[RegisterFile.scala:33:38] wire _arbs_1_io_in_2_ready; // @[RegisterFile.scala:33:38] wire _arbs_0_io_in_0_ready; // @[RegisterFile.scala:33:38] wire _arbs_0_io_in_1_ready; // @[RegisterFile.scala:33:38] wire _arbs_0_io_in_2_ready; // @[RegisterFile.scala:33:38] wire _io_in_0_resp_T = io_in_0_req_bits_eg[1:0] == 2'h0; // @[RegisterFile.scala:41:82, :43:63] wire [4:0] arbs_3_io_in_0_bits_eg = {2'h0, io_in_0_req_bits_eg[4:2]}; // @[RegisterFile.scala:44:{32,56}] wire _io_in_0_resp_T_1 = io_in_0_req_bits_eg[1:0] == 2'h1; // @[RegisterFile.scala:41:82, :43:63] wire _io_in_0_resp_T_2 = io_in_0_req_bits_eg[1:0] == 2'h2; // @[RegisterFile.scala:41:82, :43:63] wire _io_in_1_resp_T = io_in_1_req_bits_eg[1:0] == 2'h0; // @[RegisterFile.scala:41:82, :43:63] wire [4:0] arbs_3_io_in_1_bits_eg = {2'h0, io_in_1_req_bits_eg[4:2]}; // @[RegisterFile.scala:44:{32,56}] wire _io_in_1_resp_T_1 = io_in_1_req_bits_eg[1:0] == 2'h1; // @[RegisterFile.scala:41:82, :43:63] wire _io_in_1_resp_T_2 = io_in_1_req_bits_eg[1:0] == 2'h2; // @[RegisterFile.scala:41:82, :43:63] wire _io_in_2_resp_T = io_in_2_req_bits_eg[1:0] == 2'h0; // @[RegisterFile.scala:41:82, :43:63] wire [4:0] arbs_3_io_in_2_bits_eg = {2'h0, io_in_2_req_bits_eg[4:2]}; // @[RegisterFile.scala:44:{32,56}] wire _io_in_2_resp_T_1 = io_in_2_req_bits_eg[1:0] == 2'h1; // @[RegisterFile.scala:41:82, :43:63] wire _io_in_2_resp_T_2 = io_in_2_req_bits_eg[1:0] == 2'h2; // @[RegisterFile.scala:41:82, :43:63] OldestRRArbiter arbs_0 ( // @[RegisterFile.scala:33:38] .clock (clock), .io_in_0_ready (_arbs_0_io_in_0_ready), .io_in_0_valid (io_in_0_req_valid & _io_in_0_resp_T), // @[RegisterFile.scala:43:{52,63}] .io_in_0_bits_eg (arbs_3_io_in_0_bits_eg), // @[RegisterFile.scala:44:32] .io_in_0_bits_oldest (io_in_0_req_bits_oldest), .io_in_1_ready (_arbs_0_io_in_1_ready), .io_in_1_valid (io_in_1_req_valid & _io_in_1_resp_T), // @[RegisterFile.scala:43:{52,63}] .io_in_1_bits_eg (arbs_3_io_in_1_bits_eg), // @[RegisterFile.scala:44:32] .io_in_1_bits_oldest (io_in_1_req_bits_oldest), .io_in_2_ready (_arbs_0_io_in_2_ready), .io_in_2_valid (io_in_2_req_valid & _io_in_2_resp_T), // @[RegisterFile.scala:43:{52,63}] .io_in_2_bits_eg (arbs_3_io_in_2_bits_eg), // @[RegisterFile.scala:44:32] .io_out_ready (io_out_0_req_ready), .io_out_valid (io_out_0_req_valid), .io_out_bits_eg (io_out_0_req_bits_eg) ); // @[RegisterFile.scala:33:38] OldestRRArbiter arbs_1 ( // @[RegisterFile.scala:33:38] .clock (clock), .io_in_0_ready (_arbs_1_io_in_0_ready), .io_in_0_valid (io_in_0_req_valid & _io_in_0_resp_T_1), // @[RegisterFile.scala:43:{52,63}] .io_in_0_bits_eg (arbs_3_io_in_0_bits_eg), // @[RegisterFile.scala:44:32] .io_in_0_bits_oldest (io_in_0_req_bits_oldest), .io_in_1_ready (_arbs_1_io_in_1_ready), .io_in_1_valid (io_in_1_req_valid & _io_in_1_resp_T_1), // @[RegisterFile.scala:43:{52,63}] .io_in_1_bits_eg (arbs_3_io_in_1_bits_eg), // @[RegisterFile.scala:44:32] .io_in_1_bits_oldest (io_in_1_req_bits_oldest), .io_in_2_ready (_arbs_1_io_in_2_ready), .io_in_2_valid (io_in_2_req_valid & _io_in_2_resp_T_1), // @[RegisterFile.scala:43:{52,63}] .io_in_2_bits_eg (arbs_3_io_in_2_bits_eg), // @[RegisterFile.scala:44:32] .io_out_ready (io_out_1_req_ready), .io_out_valid (io_out_1_req_valid), .io_out_bits_eg (io_out_1_req_bits_eg) ); // @[RegisterFile.scala:33:38] OldestRRArbiter arbs_2 ( // @[RegisterFile.scala:33:38] .clock (clock), .io_in_0_ready (_arbs_2_io_in_0_ready), .io_in_0_valid (io_in_0_req_valid & _io_in_0_resp_T_2), // @[RegisterFile.scala:43:{52,63}] .io_in_0_bits_eg (arbs_3_io_in_0_bits_eg), // @[RegisterFile.scala:44:32] .io_in_0_bits_oldest (io_in_0_req_bits_oldest), .io_in_1_ready (_arbs_2_io_in_1_ready), .io_in_1_valid (io_in_1_req_valid & _io_in_1_resp_T_2), // @[RegisterFile.scala:43:{52,63}] .io_in_1_bits_eg (arbs_3_io_in_1_bits_eg), // @[RegisterFile.scala:44:32] .io_in_1_bits_oldest (io_in_1_req_bits_oldest), .io_in_2_ready (_arbs_2_io_in_2_ready), .io_in_2_valid (io_in_2_req_valid & _io_in_2_resp_T_2), // @[RegisterFile.scala:43:{52,63}] .io_in_2_bits_eg (arbs_3_io_in_2_bits_eg), // @[RegisterFile.scala:44:32] .io_out_ready (io_out_2_req_ready), .io_out_valid (io_out_2_req_valid), .io_out_bits_eg (io_out_2_req_bits_eg) ); // @[RegisterFile.scala:33:38] OldestRRArbiter arbs_3 ( // @[RegisterFile.scala:33:38] .clock (clock), .io_in_0_ready (_arbs_3_io_in_0_ready), .io_in_0_valid (io_in_0_req_valid & (&(io_in_0_req_bits_eg[1:0]))), // @[RegisterFile.scala:41:82, :43:{52,63}] .io_in_0_bits_eg (arbs_3_io_in_0_bits_eg), // @[RegisterFile.scala:44:32] .io_in_0_bits_oldest (io_in_0_req_bits_oldest), .io_in_1_ready (_arbs_3_io_in_1_ready), .io_in_1_valid (io_in_1_req_valid & (&(io_in_1_req_bits_eg[1:0]))), // @[RegisterFile.scala:41:82, :43:{52,63}] .io_in_1_bits_eg (arbs_3_io_in_1_bits_eg), // @[RegisterFile.scala:44:32] .io_in_1_bits_oldest (io_in_1_req_bits_oldest), .io_in_2_ready (_arbs_3_io_in_2_ready), .io_in_2_valid (io_in_2_req_valid & (&(io_in_2_req_bits_eg[1:0]))), // @[RegisterFile.scala:41:82, :43:{52,63}] .io_in_2_bits_eg (arbs_3_io_in_2_bits_eg), // @[RegisterFile.scala:44:32] .io_out_ready (io_out_3_req_ready), .io_out_valid (io_out_3_req_valid), .io_out_bits_eg (io_out_3_req_bits_eg) ); // @[RegisterFile.scala:33:38] assign io_in_0_req_ready = _io_in_0_resp_T & _arbs_0_io_in_0_ready | _io_in_0_resp_T_1 & _arbs_1_io_in_0_ready | _io_in_0_resp_T_2 & _arbs_2_io_in_0_ready | (&(io_in_0_req_bits_eg[1:0])) & _arbs_3_io_in_0_ready; // @[Mux.scala:30:73] assign io_in_0_resp = (_io_in_0_resp_T ? io_out_0_resp : 128'h0) | (_io_in_0_resp_T_1 ? io_out_1_resp : 128'h0) | (_io_in_0_resp_T_2 ? io_out_2_resp : 128'h0) | ((&(io_in_0_req_bits_eg[1:0])) ? io_out_3_resp : 128'h0); // @[Mux.scala:30:73] assign io_in_1_req_ready = _io_in_1_resp_T & _arbs_0_io_in_1_ready | _io_in_1_resp_T_1 & _arbs_1_io_in_1_ready | _io_in_1_resp_T_2 & _arbs_2_io_in_1_ready | (&(io_in_1_req_bits_eg[1:0])) & _arbs_3_io_in_1_ready; // @[Mux.scala:30:73] assign io_in_1_resp = (_io_in_1_resp_T ? io_out_0_resp : 128'h0) | (_io_in_1_resp_T_1 ? io_out_1_resp : 128'h0) | (_io_in_1_resp_T_2 ? io_out_2_resp : 128'h0) | ((&(io_in_1_req_bits_eg[1:0])) ? io_out_3_resp : 128'h0); // @[Mux.scala:30:73] assign io_in_2_req_ready = _io_in_2_resp_T & _arbs_0_io_in_2_ready | _io_in_2_resp_T_1 & _arbs_1_io_in_2_ready | _io_in_2_resp_T_2 & _arbs_2_io_in_2_ready | (&(io_in_2_req_bits_eg[1:0])) & _arbs_3_io_in_2_ready; // @[Mux.scala:30:73] assign io_in_2_resp = (_io_in_2_resp_T ? io_out_0_resp : 128'h0) | (_io_in_2_resp_T_1 ? io_out_1_resp : 128'h0) | (_io_in_2_resp_T_2 ? io_out_2_resp : 128'h0) | ((&(io_in_2_req_bits_eg[1:0])) ? io_out_3_resp : 128'h0); // @[Mux.scala:30:73] endmodule

Generate the Verilog code corresponding to the following Chisel files. File FFT.scala: //****************************************************************************** // Copyright (c) 2021-2022, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE for license details. //------------------------------------------------------------------------------ package fftgenerator import chisel3.util._ import chisel3._ import craft._ import dsptools._ import dsptools.numbers._ import dsptools.numbers.implicits._ import dspjunctions._ import dspblocks._ import scala.math._ import fixedpoint._ import fixedpoint.{fromIntToBinaryPoint} class DirectFFTIO[T<:Data:Real](genMid: DspComplex[T], genOut: DspComplex[T], lanes: Int) extends Bundle { val in = Input(ValidWithSync(Vec(lanes, genMid))) val out = Output(ValidWithSync(Vec(lanes, genOut))) } /** * fast fourier transform - cooley-tukey algorithm, decimation-in-time * direct form version * note, this is always a p-point FFT, though the twiddle factors will be different if p < n * @tparam T */ class DirectFFT[T<:Data:Real](params: FFTConfig[T], genMid: DspComplex[T], genTwiddle: DspComplex[T], genOutFull: DspComplex[T]) extends Module { val io = IO(new DirectFFTIO[T](genMid, genOutFull, params.lanes)) // synchronize val valid_delay = RegNext(io.in.valid) val sync = CounterWithReset(true.B, params.bp, io.in.sync, ~valid_delay & io.in.valid)._1 io.out.sync := ShiftRegisterWithReset(io.in.valid && sync === (params.bp-1).U, params.direct_pipe, 0.U) // should valid keep sync from propagating? io.out.valid := ShiftRegisterWithReset(io.in.valid, params.direct_pipe, 0.U) // wire up twiddles val genTwiddleReal = genTwiddle.real val genTwiddleImag = genTwiddle.imag val twiddle_rom = VecInit(params.twiddle.map( x => { val real = Wire(genTwiddleReal.cloneType) val imag = Wire(genTwiddleImag.cloneType) real := Real[T].fromDouble(x(0), genTwiddleReal) imag := Real[T].fromDouble(x(1), genTwiddleImag) val twiddle = Wire(DspComplex(genTwiddleReal, genTwiddleImag)) twiddle.real := real twiddle.imag := imag twiddle })) val indices_rom = VecInit(params.dindices.map(x => x.U)) val start = sync*(params.lanes-1).U val twiddle = Wire(Vec(params.lanes-1, genTwiddle.cloneType)) // special case when n = 4, because the pattern breaks down if (params.n == 4) { twiddle := VecInit((0 until params.lanes-1).map(x => { val true_branch = Wire(genTwiddle) true_branch := twiddle_rom(0).divj() val false_branch = Wire(genTwiddle) false_branch := twiddle_rom(0) Mux( indices_rom(start+x.U)(log2Ceil(params.n/4)), true_branch, false_branch ) })) } else { twiddle.zipWithIndex.foreach { case (t, x) => t := { val true_branch = twiddle_rom(indices_rom(start+x.U)(log2Ceil(params.n/4)-1, 0)).divj().asTypeOf(genTwiddle) val false_branch = twiddle_rom(indices_rom(start+x.U)).asTypeOf(genTwiddle) val index = indices_rom(start+x.U) Mux(index(log2Ceil(params.n/4)), true_branch, false_branch ) } } } // p-point decimation-in-time direct form FFT with inputs in normal order // (outputs bit reversed) val stage_outputs = List.fill(log2Ceil(params.lanes)+1)(List.fill(params.lanes)(Wire(genOutFull))) io.in.bits.zip(stage_outputs(0)).foreach { case(in, out) => out := in } // indices to the twiddle Vec var indices = List(List(0,1),List(0,2)) for (i <- 0 until log2Ceil(params.lanes)-2) { indices = indices.map(x => x.map(y => y+1)) val indices_max = indices.foldLeft(0)((b,a) => max(b,a.reduceLeft((d,c) => max(c,d)))) indices = indices ++ indices.map(x => x.map(y => y+indices_max)) indices = indices.map(x => 0 +: x) } // create the FFT hardware for (i <- 0 until log2Ceil(params.lanes)) { for (j <- 0 until params.lanes/2) { val skip = pow(2,log2Ceil(params.n/2)-(i+log2Ceil(params.bp))).toInt val start = ((j % skip) + floor(j/skip) * skip*2).toInt // hook it up val outputs = List(stage_outputs(i+1)(start), stage_outputs(i+1)(start+skip)) val shr_delay = params.pipe.drop(log2Ceil(params.bp)).dropRight(log2Ceil(params.lanes)-i).foldLeft(0)(_+_) val shr = ShiftRegisterMem[DspComplex[T]](twiddle(indices(j)(i)), shr_delay, name = this.name + s"_${i}_${j}_twiddle_sram") val butterfly_outputs = Butterfly[T](Seq(stage_outputs(i)(start), stage_outputs(i)(start+skip)), shr) outputs.zip(butterfly_outputs).foreach { x => x._1 := ShiftRegisterMem(x._2, params.pipe(i+log2Ceil(params.bp)), name = this.name + s"_${i}_${j}_pipeline_sram") } } } // wire up top-level outputs // note, truncation happens here! io.out.bits := stage_outputs(log2Ceil(params.lanes)) } class BiplexFFTIO[T<:Data:Real](lanes: Int, genIn: DspComplex[T], genMid: DspComplex[T]) extends Bundle { val in = Input(ValidWithSync(Vec(lanes, genIn))) val out = Output(ValidWithSync(Vec(lanes, genMid))) } /** * fast fourier transform - cooley-tukey algorithm, decimation-in-time * biplex pipelined version * note, this is always a bp-point FFT * @tparam T */ class BiplexFFT[T<:Data:Real](params: FFTConfig[T], genMid: DspComplex[T], genTwiddle: DspComplex[T]) extends Module { val io = IO(new BiplexFFTIO[T](params.lanes, params.genIn, genMid)) // synchronize val stage_delays = (0 until log2Ceil(params.bp)+1).map(x => { if (x == log2Ceil(params.bp)) params.bp/2 else (params.bp/pow(2,x+1)).toInt }) val sync = List.fill(log2Ceil(params.bp)+1)(Wire(UInt(width=log2Ceil(params.bp).W))) val valid_delay = RegNext(io.in.valid) sync(0) := CounterWithReset(true.B, params.bp, io.in.sync, ~valid_delay & io.in.valid)._1 sync.drop(1).zip(sync).zip(stage_delays).foreach { case ((next, prev), delay) => next := ShiftRegisterWithReset(prev, delay, 0.U) } io.out.sync := sync(log2Ceil(params.bp)) === ((params.bp/2-1+params.biplex_pipe)%params.bp).U io.out.valid := ShiftRegisterWithReset(io.in.valid, stage_delays.reduce(_+_) + params.biplex_pipe, 0.U) // wire up twiddles val genTwiddleReal = genTwiddle.real val genTwiddleImag = genTwiddle.imag val twiddle_rom = VecInit(params.twiddle.map(x => { val real = Wire(genTwiddleReal.cloneType) val imag = Wire(genTwiddleImag.cloneType) real := Real[T].fromDouble(x(0), genTwiddleReal) imag := Real[T].fromDouble(x(1), genTwiddleImag) val twiddle = Wire(DspComplex(genTwiddleReal, genTwiddleImag)) twiddle.real := real twiddle.imag := imag twiddle })) val indices_rom = VecInit(params.bindices.map(x => x.U)) val indices = (0 until log2Ceil(params.bp)).map(x => indices_rom((pow(2,x)-1).toInt.U +& { if (x == 0) 0.U else ShiftRegisterMem(sync(x+1), params.pipe.dropRight(log2Ceil(params.n)-x).reduceRight(_+_), name = this.name + s"_twiddle_sram")(log2Ceil(params.bp)-2,log2Ceil(params.bp)-1-x) })) val twiddle = Wire(Vec(log2Ceil(params.bp), genTwiddle)) // special cases if (params.n == 4) { twiddle := VecInit((0 until log2Ceil(params.bp)).map(x => { val true_branch = Wire(genTwiddle) val false_branch = Wire(genTwiddle) true_branch := twiddle_rom(0).divj() false_branch := twiddle_rom(0) Mux(indices(x)(log2Ceil(params.n/4)), true_branch, false_branch) })) } else if (params.bp == 2) { twiddle := VecInit((0 until log2Ceil(params.bp)).map(x => twiddle_rom(indices(x)) )) } else { twiddle := VecInit((0 until log2Ceil(params.bp)).map(x => { val true_branch = Wire(genTwiddle) val false_branch = Wire(genTwiddle) true_branch := twiddle_rom(indices(x)(log2Ceil(params.n/4)-1, 0)).divj() false_branch := twiddle_rom(indices(x)) Mux(indices(x)(log2Ceil(params.n/4)), true_branch, false_branch) })) } // bp-point decimation-in-time biplex pipelined FFT with outputs in bit-reversed order // up-scale to genMid immediately for simplicity val stage_outputs = List.fill(log2Ceil(params.bp)+2)(List.fill(params.lanes)(Wire(genMid))) io.in.bits.zip(stage_outputs(0)).foreach { case(in, out) => out := in } // create the FFT hardware for (i <- 0 until log2Ceil(params.bp)+1) { for (j <- 0 until params.lanes/2) { val skip = 1 val start = j*2 // hook it up // last stage just has one extra permutation, no butterfly val mux_out = BarrelShifter(VecInit(stage_outputs(i)(start), ShiftRegisterMem(stage_outputs(i)(start+skip), stage_delays(i), name = this.name + s"_${i}_${j}_mux1_sram")), ShiftRegisterMem(sync(i)(log2Ceil(params.bp)-1 - { if (i == log2Ceil(params.bp)) 0 else i }), {if (i == 0) 0 else params.pipe.dropRight(log2Ceil(params.n)-i).reduceRight(_+_)}, name = this.name + s"_${i}_${j}_mux1_sram")) if (i == log2Ceil(params.bp)) { Seq(stage_outputs(i+1)(start), stage_outputs(i+1)(start+skip)).zip(Seq(ShiftRegisterMem(mux_out(0), stage_delays(i), name = this.name + s"_${i}_${j}_last_sram" ), mux_out(1))).foreach { x => x._1 := x._2 } } else { Seq(stage_outputs(i+1)(start), stage_outputs(i+1)(start+skip)).zip(Butterfly(Seq(ShiftRegisterMem(mux_out(0), stage_delays(i), name = this.name + s"_${i}_${j}_pipeline0_sram"), mux_out(1)), twiddle(i))).foreach { x => x._1 := ShiftRegisterMem(x._2, params.pipe(i), name = this.name + s"_${i}_${j}_pipeline1_sram") } } } } // wire up top-level outputs io.out.bits := stage_outputs(log2Ceil(params.bp)+1) } /** * IO Bundle for FFT * @tparam T */ class FFTIO[T<:Data:Real](lanes: Int, genIn: DspComplex[T], genOut: DspComplex[T]) extends Bundle { val in = Input(ValidWithSync(Vec(lanes, genIn))) val out = Output(ValidWithSync(Vec(lanes, genOut))) } /** * fast fourier transform - cooley-tukey algorithm, decimation-in-time * mixed version * note, this is always an n-point FFT * @tparam T */ class FFT[T<:Data:Real](val params: FFTConfig[T]) extends Module { require(params.lanes >= 2, "Must have at least 2 parallel inputs") require(isPow2(params.lanes), "FFT parallelism must be a power of 2") require(params.lanes <= params.n, "An n-point FFT cannot have more than n inputs (p must be less than or equal to n)") val io = IO(new FFTIO(params.lanes, params.genIn, params.genOut)) // calculate direct FFT input bitwidth // this is just the input total width + growth of 1 bit per biplex stage val genMid: DspComplex[T] = { if (params.bp == 1) { params.genIn } else { val growth = log2Ceil(params.bp) params.genIn.underlyingType() match { case "fixed" => params.genIn.real.asInstanceOf[FixedPoint].binaryPoint match { case KnownBinaryPoint(binaryPoint) => val totalBits = params.genIn.real.getWidth + growth DspComplex(FixedPoint(totalBits.W, binaryPoint.BP), FixedPoint(totalBits.W, binaryPoint.BP)).asInstanceOf[DspComplex[T]] case _ => throw new DspException("Error: unknown binary point when calculating FFT bitwdiths") } case "sint" => { val totalBits = params.genIn.real.getWidth + growth DspComplex(SInt(totalBits.W), SInt(totalBits.W)).asInstanceOf[DspComplex[T]] } case _ => throw new DspException("Error: unknown type when calculating FFT bitwidths") } } } // calculate twiddle factor bitwidth // total input bits val genTwiddleBiplex: DspComplex[T] = { val growth = log2Ceil(params.bp) params.genIn.asInstanceOf[DspComplex[T]].underlyingType() match { case "fixed" => params.genIn.asInstanceOf[DspComplex[T]].real.asInstanceOf[FixedPoint].binaryPoint match { case KnownBinaryPoint(binaryPoint) => val totalBits = params.genIn.asInstanceOf[DspComplex[T]].real.getWidth + growth DspComplex(FixedPoint(totalBits.W, (totalBits-2).BP), FixedPoint(totalBits.W, (totalBits-2).BP)).asInstanceOf[DspComplex[T]] case _ => throw new DspException("Error: unknown binary point when calculating FFT bitwdiths") } case "sint" => { val totalBits = params.genIn.asInstanceOf[DspComplex[T]].real.getWidth + growth DspComplex(SInt(totalBits.W), SInt(totalBits.W)).asInstanceOf[DspComplex[T]] } case _ => throw new DspException("Error: unknown type when calculating FFT bitwidths") } } val genTwiddleDirect: DspComplex[T] = { val growth = log2Ceil(params.n) params.genIn.asInstanceOf[DspComplex[T]].underlyingType() match { case "fixed" => params.genIn.asInstanceOf[DspComplex[T]].real.asInstanceOf[FixedPoint].binaryPoint match { case KnownBinaryPoint(binaryPoint) => val totalBits = params.genIn.asInstanceOf[DspComplex[T]].real.getWidth + growth DspComplex(FixedPoint(totalBits.W, (totalBits-2).BP), FixedPoint(totalBits.W, (totalBits-2).BP)).asInstanceOf[DspComplex[T]] case _ => throw new DspException("Error: unknown binary point when calculating FFT bitwdiths") } case "sint" => { val totalBits = params.genIn.asInstanceOf[DspComplex[T]].real.getWidth + growth DspComplex(SInt(totalBits.W), SInt(totalBits.W)).asInstanceOf[DspComplex[T]] } case _ => throw new DspException("Error: unknown type when calculating FFT bitwidths") } } // calculate direct FFT output bitwidth // this is just the input total width + growth of 1 bit per FFT stage val genOutDirect: DspComplex[T] = { if (params.bp == 1) { params.genIn } else { val growth = log2Ceil(params.n) params.genIn.asInstanceOf[DspComplex[T]].underlyingType() match { case "fixed" => params.genIn.asInstanceOf[DspComplex[T]].real.asInstanceOf[FixedPoint].binaryPoint match { case KnownBinaryPoint(binaryPoint) => val totalBits = params.genIn.asInstanceOf[DspComplex[T]].real.getWidth + growth DspComplex(FixedPoint(totalBits.W, binaryPoint.BP), FixedPoint(totalBits.W, binaryPoint.BP)).asInstanceOf[DspComplex[T]] case _ => throw new DspException("Error: unknown binary point when calculating FFT bitwdiths") } case "sint" => { val totalBits = params.genIn.asInstanceOf[DspComplex[T]].real.getWidth + growth DspComplex(SInt(totalBits.W), SInt(totalBits.W)).asInstanceOf[DspComplex[T]] } case _ => throw new DspException("Error: unknown type when calculating FFT bitwidths") } } } // feed in zeros when invalid val in = Wire(ValidWithSync(Vec(params.lanes, params.genIn))) when (io.in.valid) { in.bits := io.in.bits } .otherwise { in.bits.foreach { case b => b.real := Real[T].zero b.imag := Real[T].zero } } in.valid := io.in.valid in.sync := io.in.sync // instantiate sub-FFTs val direct = Module(new DirectFFT[T]( params = params, genMid = genMid, genTwiddle = genTwiddleDirect, genOutFull = genOutDirect )) io.out <> direct.io.out if (params.n != params.lanes) { val biplex = Module(new BiplexFFT[T](params, genMid, genTwiddleBiplex)) direct.io.in := biplex.io.out biplex.io.in <> in } else { direct.io.in <> in } }

module FFT( // @[FFT.scala:230:7] input io_in_valid, // @[FFT.scala:236:14] input [15:0] io_in_bits_0_real, // @[FFT.scala:236:14] input [15:0] io_in_bits_0_imag, // @[FFT.scala:236:14] input [15:0] io_in_bits_1_real, // @[FFT.scala:236:14] input [15:0] io_in_bits_1_imag, // @[FFT.scala:236:14] input [15:0] io_in_bits_2_real, // @[FFT.scala:236:14] input [15:0] io_in_bits_2_imag, // @[FFT.scala:236:14] input [15:0] io_in_bits_3_real, // @[FFT.scala:236:14] input [15:0] io_in_bits_3_imag, // @[FFT.scala:236:14] input [15:0] io_in_bits_4_real, // @[FFT.scala:236:14] input [15:0] io_in_bits_4_imag, // @[FFT.scala:236:14] input [15:0] io_in_bits_5_real, // @[FFT.scala:236:14] input [15:0] io_in_bits_5_imag, // @[FFT.scala:236:14] input [15:0] io_in_bits_6_real, // @[FFT.scala:236:14] input [15:0] io_in_bits_6_imag, // @[FFT.scala:236:14] input [15:0] io_in_bits_7_real, // @[FFT.scala:236:14] input [15:0] io_in_bits_7_imag, // @[FFT.scala:236:14] output io_out_valid, // @[FFT.scala:236:14] output [15:0] io_out_bits_0_real, // @[FFT.scala:236:14] output [15:0] io_out_bits_0_imag, // @[FFT.scala:236:14] output [15:0] io_out_bits_1_real, // @[FFT.scala:236:14] output [15:0] io_out_bits_1_imag, // @[FFT.scala:236:14] output [15:0] io_out_bits_2_real, // @[FFT.scala:236:14] output [15:0] io_out_bits_2_imag, // @[FFT.scala:236:14] output [15:0] io_out_bits_3_real, // @[FFT.scala:236:14] output [15:0] io_out_bits_3_imag, // @[FFT.scala:236:14] output [15:0] io_out_bits_4_real, // @[FFT.scala:236:14] output [15:0] io_out_bits_4_imag, // @[FFT.scala:236:14] output [15:0] io_out_bits_5_real, // @[FFT.scala:236:14] output [15:0] io_out_bits_5_imag, // @[FFT.scala:236:14] output [15:0] io_out_bits_6_real, // @[FFT.scala:236:14] output [15:0] io_out_bits_6_imag, // @[FFT.scala:236:14] output [15:0] io_out_bits_7_real, // @[FFT.scala:236:14] output [15:0] io_out_bits_7_imag // @[FFT.scala:236:14] ); DirectFFT direct ( // @[FFT.scala:336:22] .io_in_valid (io_in_valid), .io_in_bits_0_real (io_in_valid ? io_in_bits_0_real : 16'h0), // @[FFT.scala:324:22, :325:13, :328:14] .io_in_bits_0_imag (io_in_valid ? io_in_bits_0_imag : 16'h0), // @[FFT.scala:324:22, :325:13, :329:14] .io_in_bits_1_real (io_in_valid ? io_in_bits_1_real : 16'h0), // @[FFT.scala:324:22, :325:13, :328:14] .io_in_bits_1_imag (io_in_valid ? io_in_bits_1_imag : 16'h0), // @[FFT.scala:324:22, :325:13, :329:14] .io_in_bits_2_real (io_in_valid ? io_in_bits_2_real : 16'h0), // @[FFT.scala:324:22, :325:13, :328:14] .io_in_bits_2_imag (io_in_valid ? io_in_bits_2_imag : 16'h0), // @[FFT.scala:324:22, :325:13, :329:14] .io_in_bits_3_real (io_in_valid ? io_in_bits_3_real : 16'h0), // @[FFT.scala:324:22, :325:13, :328:14] .io_in_bits_3_imag (io_in_valid ? io_in_bits_3_imag : 16'h0), // @[FFT.scala:324:22, :325:13, :329:14] .io_in_bits_4_real (io_in_valid ? io_in_bits_4_real : 16'h0), // @[FFT.scala:324:22, :325:13, :328:14] .io_in_bits_4_imag (io_in_valid ? io_in_bits_4_imag : 16'h0), // @[FFT.scala:324:22, :325:13, :329:14] .io_in_bits_5_real (io_in_valid ? io_in_bits_5_real : 16'h0), // @[FFT.scala:324:22, :325:13, :328:14] .io_in_bits_5_imag (io_in_valid ? io_in_bits_5_imag : 16'h0), // @[FFT.scala:324:22, :325:13, :329:14] .io_in_bits_6_real (io_in_valid ? io_in_bits_6_real : 16'h0), // @[FFT.scala:324:22, :325:13, :328:14] .io_in_bits_6_imag (io_in_valid ? io_in_bits_6_imag : 16'h0), // @[FFT.scala:324:22, :325:13, :329:14] .io_in_bits_7_real (io_in_valid ? io_in_bits_7_real : 16'h0), // @[FFT.scala:324:22, :325:13, :328:14] .io_in_bits_7_imag (io_in_valid ? io_in_bits_7_imag : 16'h0), // @[FFT.scala:324:22, :325:13, :329:14] .io_out_valid (io_out_valid), .io_out_bits_0_real (io_out_bits_0_real), .io_out_bits_0_imag (io_out_bits_0_imag), .io_out_bits_1_real (io_out_bits_1_real), .io_out_bits_1_imag (io_out_bits_1_imag), .io_out_bits_2_real (io_out_bits_2_real), .io_out_bits_2_imag (io_out_bits_2_imag), .io_out_bits_3_real (io_out_bits_3_real), .io_out_bits_3_imag (io_out_bits_3_imag), .io_out_bits_4_real (io_out_bits_4_real), .io_out_bits_4_imag (io_out_bits_4_imag), .io_out_bits_5_real (io_out_bits_5_real), .io_out_bits_5_imag (io_out_bits_5_imag), .io_out_bits_6_real (io_out_bits_6_real), .io_out_bits_6_imag (io_out_bits_6_imag), .io_out_bits_7_real (io_out_bits_7_real), .io_out_bits_7_imag (io_out_bits_7_imag) ); // @[FFT.scala:336:22] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Decode.scala: // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.BitPat import chisel3.util.experimental.decode._ object DecodeLogic { // TODO This should be a method on BitPat private def hasDontCare(bp: BitPat): Boolean = bp.mask.bitCount != bp.width // Pads BitPats that are safe to pad (no don't cares), errors otherwise private def padBP(bp: BitPat, width: Int): BitPat = { if (bp.width == width) bp else { require(!hasDontCare(bp), s"Cannot pad '$bp' to '$width' bits because it has don't cares") val diff = width - bp.width require(diff > 0, s"Cannot pad '$bp' to '$width' because it is already '${bp.width}' bits wide!") BitPat(0.U(diff.W)) ## bp } } def apply(addr: UInt, default: BitPat, mapping: Iterable[(BitPat, BitPat)]): UInt = chisel3.util.experimental.decode.decoder(QMCMinimizer, addr, TruthTable(mapping, default)) def apply(addr: UInt, default: Seq[BitPat], mappingIn: Iterable[(BitPat, Seq[BitPat])]): Seq[UInt] = { val nElts = default.size require(mappingIn.forall(_._2.size == nElts), s"All Seq[BitPat] must be of the same length, got $nElts vs. ${mappingIn.find(_._2.size != nElts).get}" ) val elementsGrouped = mappingIn.map(_._2).transpose val elementWidths = elementsGrouped.zip(default).map { case (elts, default) => (default :: elts.toList).map(_.getWidth).max } val resultWidth = elementWidths.sum val elementIndices = elementWidths.scan(resultWidth - 1) { case (l, r) => l - r } // All BitPats that correspond to a given element in the result must have the same width in the // chisel3 decoder. We will zero pad any BitPats that are too small so long as they dont have // any don't cares. If there are don't cares, it is an error and the user needs to pad the // BitPat themselves val defaultsPadded = default.zip(elementWidths).map { case (bp, w) => padBP(bp, w) } val mappingInPadded = mappingIn.map { case (in, elts) => in -> elts.zip(elementWidths).map { case (bp, w) => padBP(bp, w) } } val decoded = apply(addr, defaultsPadded.reduce(_ ## _), mappingInPadded.map { case (in, out) => (in, out.reduce(_ ## _)) }) elementIndices.zip(elementIndices.tail).map { case (msb, lsb) => decoded(msb, lsb + 1) }.toList } def apply(addr: UInt, default: Seq[BitPat], mappingIn: List[(UInt, Seq[BitPat])]): Seq[UInt] = apply(addr, default, mappingIn.map(m => (BitPat(m._1), m._2)).asInstanceOf[Iterable[(BitPat, Seq[BitPat])]]) def apply(addr: UInt, trues: Iterable[UInt], falses: Iterable[UInt]): Bool = apply(addr, BitPat.dontCare(1), trues.map(BitPat(_) -> BitPat("b1")) ++ falses.map(BitPat(_) -> BitPat("b0"))).asBool } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File util.scala: //****************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v4.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v4.common.{MicroOp} import boom.v4.exu.{BrUpdateInfo} /** * Object to XOR fold a input register of fullLength into a compressedLength. */ object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /** * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks */ object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, flush: Bool, uop: MicroOp): Bool = { return apply(brupdate, flush, uop.br_mask) } def apply(brupdate: BrUpdateInfo, flush: Bool, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) || flush } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: T): Bool = { return apply(brupdate, flush, bundle.uop) } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Bool = { return apply(brupdate, flush, bundle.bits) } } /** * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. */ object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /** * Object to return a BR mask given a MicroOp mask and old BR mask. */ object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, flush, bundle.bits.uop.br_mask) out } } /** * Object to check if at least 1 bit matches in two masks */ object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /** * Object to clear one bit in a mask given an index */ object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /** * Object to shift a register over by one bit and concat a new one */ object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /** * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. */ object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /** * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. */ object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc | (b-1).U) } } /** * Object to rotate a signal left by one */ object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /** * Object to sext a value to a particular length. */ object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /** * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. */ object ImmGen { import boom.v4.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U, IS_N} def apply(i: UInt, isel: UInt): UInt = { val ip = Mux(isel === IS_N, 0.U(LONGEST_IMM_SZ.W), i) val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0) } } /** * Object to see if an instruction is a JALR. */ object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /** * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). */ object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /** * Object to return the lowest bit position after the head. */ object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /** * Object to determine whether queue * index i0 is older than index i1. */ object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } object IsYoungerMask { def apply(i: UInt, head: UInt, n: Integer): UInt = { val hi_mask = ~MaskLower(UIntToOH(i)(n-1,0)) val lo_mask = ~MaskUpper(UIntToOH(head)(n-1,0)) Mux(i < head, hi_mask & lo_mask, hi_mask | lo_mask)(n-1,0) } } /** * Set all bits at or below the highest order '1'. */ object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_|_) } } /** * Set all bits at or above the lowest order '1'. */ object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_) } } /** * Transpose a matrix of Chisel Vecs. */ object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /** * N-wide one-hot priority encoder. */ object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /** * Connect the first k of n valid input interfaces to k output interfaces. */ class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_)) val out_valids = sels map (col => col.reduce(_||_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /** * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). */ class BranchKillableQueue[T <: boom.v4.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v4.common.MicroOp => Bool = u => true.B, fastDeq: Boolean = false) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) if (fastDeq && entries > 1) { // Pipeline dequeue selection so the mux gets an entire cycle val main = Module(new BranchKillableQueue(gen, entries-1, flush_fn, false)) val out_reg = Reg(gen) val out_valid = RegInit(false.B) val out_uop = Reg(new MicroOp) main.io.enq <> io.enq main.io.brupdate := io.brupdate main.io.flush := io.flush io.empty := main.io.empty && !out_valid io.count := main.io.count + out_valid io.deq.valid := out_valid io.deq.bits := out_reg io.deq.bits.uop := out_uop out_uop := UpdateBrMask(io.brupdate, out_uop) out_valid := out_valid && !IsKilledByBranch(io.brupdate, false.B, out_uop) && !(io.flush && flush_fn(out_uop)) main.io.deq.ready := false.B when (io.deq.fire || !out_valid) { out_valid := main.io.deq.valid && !IsKilledByBranch(io.brupdate, false.B, main.io.deq.bits.uop) && !(io.flush && flush_fn(main.io.deq.bits.uop)) out_reg := main.io.deq.bits out_uop := UpdateBrMask(io.brupdate, main.io.deq.bits.uop) main.io.deq.ready := true.B } } else { val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire && !IsKilledByBranch(io.brupdate, false.B, io.enq.bits.uop) && !(io.flush && flush_fn(io.enq.bits.uop))) val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, false.B, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) io.deq.bits := out val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /** * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" */ def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) */ def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) */ def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) */ def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /** * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line */ def apply(strs: String*)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } class BranchKillablePipeline[T <: boom.v4.common.HasBoomUOP](gen: T, stages: Int) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val req = Input(Valid(gen)) val flush = Input(Bool()) val brupdate = Input(new BrUpdateInfo) val resp = Output(Vec(stages, Valid(gen))) }) require(stages > 0) val uops = Reg(Vec(stages, Valid(gen))) uops(0).valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.flush, io.req.bits) uops(0).bits := UpdateBrMask(io.brupdate, io.req.bits) for (i <- 1 until stages) { uops(i).valid := uops(i-1).valid && !IsKilledByBranch(io.brupdate, io.flush, uops(i-1).bits) uops(i).bits := UpdateBrMask(io.brupdate, uops(i-1).bits) } for (i <- 0 until stages) { when (reset.asBool) { uops(i).valid := false.B } } io.resp := uops } File decode.scala: //****************************************************************************** // Copyright (c) 2015 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ package boom.v4.exu import chisel3._ import chisel3.util._ import freechips.rocketchip.tile.FPConstants import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket.Instructions32 import freechips.rocketchip.rocket.CustomInstructions._ import freechips.rocketchip.rocket.RVCExpander import freechips.rocketchip.rocket.ALU._ import freechips.rocketchip.rocket.{CSR, Causes, DecodeLogic} import freechips.rocketchip.util._ import boom.v4.common._ import boom.v4.util._ // scalastyle:off /** * Abstract trait giving defaults and other relevant values to different Decode constants/ */ object DecodeTables extends freechips.rocketchip.rocket.constants.ScalarOpConstants with freechips.rocketchip.rocket.constants.MemoryOpConstants with freechips.rocketchip.tile.HasFPUParameters { lazy val fLen = 64 lazy val minFLen = 32 def xLen = 64 def xpr64 = Y // TODO inform this from xLen def DC(i: Int) = BitPat.dontCare(i) def fc2oh(fc: Int): UInt = (1 << fc).U(FC_SZ.W) // FP stores generate data through FP F2I, and generate address through MemAddrCalc def FCOH_F2IMEM = ((1 << FC_AGEN) | (1 << FC_F2I )).U(FC_SZ.W) def FCOH_STORE = ((1 << FC_AGEN) | (1 << FC_DGEN)).U(FC_SZ.W) def FN_00 = BitPat("b???00") def FN_01 = BitPat("b???01") def FN_10 = BitPat("b???10") def FN_11 = BitPat("b???11") def decode_default: List[BitPat] = // frs3_en // is val inst? | imm sel // | is fp inst? | | uses_ldq // | | rs1 regtype | | | uses_stq is unique? (clear pipeline for it) // | | | rs2 type| | | | is_amo | flush on commit // | | func unit | | | | | | | | | csr cmd // | | | | | | | | | | | | | fcn_dw swap12 fma // | | | dst | | | | | | | mem | | | | fcn_op | swap32 | div // | | | regtype | | | | | | | cmd | | | | | | | typeTagIn | | sqrt // | | | | | | | | | | | | | | | | | ldst | | | typeTagOut | | wflags // | | | | | | | | | | | | | | | | | | wen | | | | from_int | | | // | | | | | | | | | | | | | | | | | | | ren1 | | | | | to_int | | | // | | | | | | | | | | | | | | | | | | | | ren2 | | | | | | fast | | | // | | | | | | | | | | | | | | | | | | | | | ren3 | | | | | | | | | | // | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | List(N, N, DC(FC_SZ) , RT_X , DC(2) , DC(2) , X, IS_N, X, X, X, M_X, N, X, CSR.X, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X) def X32_table: Seq[(BitPat, List[BitPat])] = { import Instructions32._; Seq( SLLI -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_SL , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SRLI -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_SR , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SRAI -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_SRA , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X) ) } def X64_table: Seq[(BitPat, List[BitPat])] = Seq( LD -> List(Y, N, fc2oh(FC_AGEN), RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, M_XRD , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), LWU -> List(Y, N, fc2oh(FC_AGEN), RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, M_XRD , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SD -> List(Y, N, FCOH_STORE , RT_X , RT_FIX, RT_FIX, N, IS_S, N, Y, N, M_XWR , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SLLI -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_SL , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SRLI -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_SR , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SRAI -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_SRA , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), ADDIW -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_32 , FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SLLIW -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_32 , FN_SL , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SRAIW -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_32 , FN_SRA , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SRLIW -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_32 , FN_SR , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), ADDW -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_32 , FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SUBW -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_32 , FN_SUB , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SLLW -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_32 , FN_SL , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SRAW -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_32 , FN_SRA , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SRLW -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_32 , FN_SR , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X) ) def X_table: Seq[(BitPat, List[BitPat])] = Seq( LW -> List(Y, N, fc2oh(FC_AGEN), RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, M_XRD , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), LH -> List(Y, N, fc2oh(FC_AGEN), RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, M_XRD , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), LHU -> List(Y, N, fc2oh(FC_AGEN), RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, M_XRD , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), LB -> List(Y, N, fc2oh(FC_AGEN), RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, M_XRD , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), LBU -> List(Y, N, fc2oh(FC_AGEN), RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, M_XRD , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SW -> List(Y, N, FCOH_STORE , RT_X , RT_FIX, RT_FIX, N, IS_S, N, Y, N, M_XWR , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SH -> List(Y, N, FCOH_STORE , RT_X , RT_FIX, RT_FIX, N, IS_S, N, Y, N, M_XWR , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SB -> List(Y, N, FCOH_STORE , RT_X , RT_FIX, RT_FIX, N, IS_S, N, Y, N, M_XWR , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), LUI -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_X , RT_X , N, IS_U, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), ADDI -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), ANDI -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_AND , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), ORI -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_OR , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), XORI -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_XOR , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SLTI -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_SLT , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SLTIU -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_SLTU, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SLL -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_SL , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), ADD -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SUB -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_SUB , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SLT -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_SLT , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SLTU -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_SLTU, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), AND -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_AND , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), OR -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_OR , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), XOR -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_XOR , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SRA -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_SRA , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SRL -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_SR , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), MUL -> List(Y, N, fc2oh(FC_MUL) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_MUL , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), MULH -> List(Y, N, fc2oh(FC_MUL) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_MULH, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), MULHU -> List(Y, N, fc2oh(FC_MUL) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_MULHU, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), MULHSU -> List(Y, N, fc2oh(FC_MUL) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_MULHSU, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), MULW -> List(Y, N, fc2oh(FC_MUL) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_32 , FN_MUL , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), DIV -> List(Y, N, fc2oh(FC_DIV) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_DIV , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), DIVU -> List(Y, N, fc2oh(FC_DIV) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_DIVU, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), REM -> List(Y, N, fc2oh(FC_DIV) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_REM , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), REMU -> List(Y, N, fc2oh(FC_DIV) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_REMU, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), DIVW -> List(Y, N, fc2oh(FC_DIV) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_32 , FN_DIV , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), DIVUW -> List(Y, N, fc2oh(FC_DIV) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_32 , FN_DIVU, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), REMW -> List(Y, N, fc2oh(FC_DIV) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_32 , FN_REM , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), REMUW -> List(Y, N, fc2oh(FC_DIV) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_32 , FN_REMU, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), AUIPC -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_X , RT_X , N, IS_U, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), // use BRU for the PC read JAL -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_X , RT_X , N, IS_J, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), JALR -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), BEQ -> List(Y, N, fc2oh(FC_ALU) , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_SUB , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), BNE -> List(Y, N, fc2oh(FC_ALU) , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_SUB , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), BGE -> List(Y, N, fc2oh(FC_ALU) , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_SLT , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), BGEU -> List(Y, N, fc2oh(FC_ALU) , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_SLTU, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), BLT -> List(Y, N, fc2oh(FC_ALU) , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_SLT , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), BLTU -> List(Y, N, fc2oh(FC_ALU) , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_SLTU, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), // I-type, the immedia2 holds the CSR regi ster. CSRRW -> List(Y, N, fc2oh(FC_CSR) , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , Y, Y, CSR.W, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CSRRS -> List(Y, N, fc2oh(FC_CSR) , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , Y, Y, CSR.S, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CSRRC -> List(Y, N, fc2oh(FC_CSR) , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , Y, Y, CSR.C, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CSRRWI -> List(Y, N, fc2oh(FC_CSR) , RT_FIX, RT_X , RT_X , N, IS_I, N, N, N, M_X , Y, Y, CSR.W, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CSRRSI -> List(Y, N, fc2oh(FC_CSR) , RT_FIX, RT_X , RT_X , N, IS_I, N, N, N, M_X , Y, Y, CSR.S, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CSRRCI -> List(Y, N, fc2oh(FC_CSR) , RT_FIX, RT_X , RT_X , N, IS_I, N, N, N, M_X , Y, Y, CSR.C, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SFENCE_VMA ->List(Y, N, fc2oh(FC_CSR) , RT_X , RT_FIX, RT_FIX, N, IS_N, N, N, N,M_SFENCE , Y, Y, CSR.R, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), ECALL -> List(Y, N, fc2oh(FC_CSR) , RT_X , RT_X , RT_X , N, IS_I, N, N, N, M_X , Y, Y, CSR.I, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), EBREAK -> List(Y, N, fc2oh(FC_CSR) , RT_X , RT_X , RT_X , N, IS_I, N, N, N, M_X , Y, Y, CSR.I, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SRET -> List(Y, N, fc2oh(FC_CSR) , RT_X , RT_X , RT_X , N, IS_I, N, N, N, M_X , Y, Y, CSR.I, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), MRET -> List(Y, N, fc2oh(FC_CSR) , RT_X , RT_X , RT_X , N, IS_I, N, N, N, M_X , Y, Y, CSR.I, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), DRET -> List(Y, N, fc2oh(FC_CSR) , RT_X , RT_X , RT_X , N, IS_I, N, N, N, M_X , Y, Y, CSR.I, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), WFI -> List(Y, N, fc2oh(FC_CSR) , RT_X , RT_X , RT_X , N, IS_I, N, N, N, M_X , Y, Y, CSR.I, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), FENCE_I -> List(Y, N, 0.U(FC_SZ.W) , RT_X , RT_X , RT_X , N, IS_N, N, N, N, M_X , Y, Y, CSR.N, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), FENCE -> List(Y, N, 0.U(FC_SZ.W) , RT_X , RT_X , RT_X , N, IS_N, N, Y, N, M_X , Y, Y, CSR.N, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), // TODO PERF make fence higher performance // currently serializes pipeline // A-type AMOADD_W -> List(Y, N, FCOH_STORE , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, Y, Y, M_XA_ADD, Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), // TODO make AMOs higherperformance AMOXOR_W -> List(Y, N, FCOH_STORE , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, Y, Y, M_XA_XOR, Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), AMOSWAP_W -> List(Y, N, FCOH_STORE , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, Y, Y, M_XA_SWAP,Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), AMOAND_W -> List(Y, N, FCOH_STORE , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, Y, Y, M_XA_AND, Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), AMOOR_W -> List(Y, N, FCOH_STORE , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, Y, Y, M_XA_OR, Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), AMOMIN_W -> List(Y, N, FCOH_STORE , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, Y, Y, M_XA_MIN, Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), AMOMINU_W -> List(Y, N, FCOH_STORE , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, Y, Y, M_XA_MINU,Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), AMOMAX_W -> List(Y, N, FCOH_STORE , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, Y, Y, M_XA_MAX, Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), AMOMAXU_W -> List(Y, N, FCOH_STORE , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, Y, Y, M_XA_MAXU,Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), AMOADD_D -> List(Y, N, FCOH_STORE , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, Y, Y, M_XA_ADD, Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), AMOXOR_D -> List(Y, N, FCOH_STORE , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, Y, Y, M_XA_XOR, Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), AMOSWAP_D -> List(Y, N, FCOH_STORE , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, Y, Y, M_XA_SWAP,Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), AMOAND_D -> List(Y, N, FCOH_STORE , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, Y, Y, M_XA_AND, Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), AMOOR_D -> List(Y, N, FCOH_STORE , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, Y, Y, M_XA_OR, Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), AMOMIN_D -> List(Y, N, FCOH_STORE , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, Y, Y, M_XA_MIN, Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), AMOMINU_D -> List(Y, N, FCOH_STORE , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, Y, Y, M_XA_MINU,Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), AMOMAX_D -> List(Y, N, FCOH_STORE , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, Y, Y, M_XA_MAX, Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), AMOMAXU_D -> List(Y, N, FCOH_STORE , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, Y, Y, M_XA_MAXU,Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), LR_W -> List(Y, N, fc2oh(FC_AGEN), RT_FIX, RT_FIX, RT_X , N, IS_N, Y, N, N, M_XLR , Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), LR_D -> List(Y, N, fc2oh(FC_AGEN), RT_FIX, RT_FIX, RT_X , N, IS_N, Y, N, N, M_XLR , Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SC_W -> List(Y, N, FCOH_STORE , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, Y, Y, M_XSC , Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SC_D -> List(Y, N, FCOH_STORE , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, Y, Y, M_XSC , Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X) ) def F_table: Seq[(BitPat, List[BitPat])] = Seq( FLW -> List(Y, Y, fc2oh(FC_AGEN), RT_FLT, RT_FIX, RT_X , N, IS_I, Y, N, N, M_XRD , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), FLD -> List(Y, Y, fc2oh(FC_AGEN), RT_FLT, RT_FIX, RT_X , N, IS_I, Y, N, N, M_XRD , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), FSW -> List(Y, Y, FCOH_F2IMEM , RT_X , RT_FIX, RT_FLT, N, IS_S, N, Y, N, M_XWR , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), // sort of a lie; broken into two micro-ops FSD -> List(Y, Y, FCOH_F2IMEM , RT_X , RT_FIX, RT_FLT, N, IS_S, N, Y, N, M_XWR , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), FCLASS_S -> List(Y, Y, fc2oh(FC_F2I) , RT_FIX, RT_FLT, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,N,N, N,X,S,S,N,Y,N, N,N,N,N), FCLASS_D -> List(Y, Y, fc2oh(FC_F2I) , RT_FIX, RT_FLT, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,N,N, N,X,D,D,N,Y,N, N,N,N,N), FMV_W_X -> List(Y, Y, fc2oh(FC_I2F) , RT_FLT, RT_FIX, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,N,N,N, X,X,S,D,Y,N,N, N,N,N,N), FMV_D_X -> List(Y, Y, fc2oh(FC_I2F) , RT_FLT, RT_FIX, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,N,N,N, X,X,D,D,Y,N,N, N,N,N,N), FMV_X_W -> List(Y, Y, fc2oh(FC_F2I) , RT_FIX, RT_FLT, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,N,N, N,X,D,S,N,Y,N, N,N,N,N), FMV_X_D -> List(Y, Y, fc2oh(FC_F2I) , RT_FIX, RT_FLT, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,N,N, N,X,D,D,N,Y,N, N,N,N,N), FSGNJ_S -> List(Y, Y, fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,Y,N, N,N,S,S,N,N,Y, N,N,N,N), FSGNJ_D -> List(Y, Y, fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,Y,N, N,N,D,D,N,N,Y, N,N,N,N), FSGNJX_S -> List(Y, Y, fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,Y,N, N,N,S,S,N,N,Y, N,N,N,N), FSGNJX_D -> List(Y, Y, fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,Y,N, N,N,D,D,N,N,Y, N,N,N,N), FSGNJN_S -> List(Y, Y, fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,Y,N, N,N,S,S,N,N,Y, N,N,N,N), FSGNJN_D -> List(Y, Y, fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,Y,N, N,N,D,D,N,N,Y, N,N,N,N), // FP to FP FCVT_S_D -> List(Y, Y,fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,N,N, N,X,D,S,N,N,Y, N,N,N,Y), FCVT_D_S -> List(Y, Y,fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,N,N, N,X,S,D,N,N,Y, N,N,N,Y), // Int to FP FCVT_S_W -> List(Y, Y,fc2oh(FC_I2F) , RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,N,N,N, X,X,S,S,Y,N,N, N,N,N,Y), FCVT_S_WU -> List(Y, Y,fc2oh(FC_I2F) , RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,N,N,N, X,X,S,S,Y,N,N, N,N,N,Y), FCVT_S_L -> List(Y, Y,fc2oh(FC_I2F) , RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,N,N,N, X,X,S,S,Y,N,N, N,N,N,Y), FCVT_S_LU -> List(Y, Y,fc2oh(FC_I2F) , RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,N,N,N, X,X,S,S,Y,N,N, N,N,N,Y), FCVT_D_W -> List(Y, Y,fc2oh(FC_I2F) , RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,N,N,N, X,X,D,D,Y,N,N, N,N,N,Y), FCVT_D_WU -> List(Y, Y,fc2oh(FC_I2F) , RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,N,N,N, X,X,D,D,Y,N,N, N,N,N,Y), FCVT_D_L -> List(Y, Y,fc2oh(FC_I2F) , RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,N,N,N, X,X,D,D,Y,N,N, N,N,N,Y), FCVT_D_LU -> List(Y, Y,fc2oh(FC_I2F) , RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,N,N,N, X,X,D,D,Y,N,N, N,N,N,Y), // FP to Int FCVT_W_S -> List(Y, Y,fc2oh(FC_F2I) , RT_FIX, RT_FLT, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,N,N, N,X,S,S,N,Y,N, N,N,N,Y), FCVT_WU_S -> List(Y, Y,fc2oh(FC_F2I) , RT_FIX, RT_FLT, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,N,N, N,X,S,S,N,Y,N, N,N,N,Y), FCVT_L_S -> List(Y, Y,fc2oh(FC_F2I) , RT_FIX, RT_FLT, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,N,N, N,X,S,S,N,Y,N, N,N,N,Y), FCVT_LU_S -> List(Y, Y,fc2oh(FC_F2I) , RT_FIX, RT_FLT, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,N,N, N,X,S,S,N,Y,N, N,N,N,Y), FCVT_W_D -> List(Y, Y,fc2oh(FC_F2I) , RT_FIX, RT_FLT, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,N,N, N,X,D,D,N,Y,N, N,N,N,Y), FCVT_WU_D -> List(Y, Y,fc2oh(FC_F2I) , RT_FIX, RT_FLT, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,N,N, N,X,D,D,N,Y,N, N,N,N,Y), FCVT_L_D -> List(Y, Y,fc2oh(FC_F2I) , RT_FIX, RT_FLT, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,N,N, N,X,D,D,N,Y,N, N,N,N,Y), FCVT_LU_D -> List(Y, Y,fc2oh(FC_F2I) , RT_FIX, RT_FLT, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,N,N, N,X,D,D,N,Y,N, N,N,N,Y), FEQ_S -> List(Y, Y, fc2oh(FC_F2I) , RT_FIX, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,Y,N, N,N,S,S,N,Y,N, N,N,N,Y), FLT_S -> List(Y, Y, fc2oh(FC_F2I) , RT_FIX, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,Y,N, N,N,S,S,N,Y,N, N,N,N,Y), FLE_S -> List(Y, Y, fc2oh(FC_F2I) , RT_FIX, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,Y,N, N,N,S,S,N,Y,N, N,N,N,Y), FEQ_D -> List(Y, Y, fc2oh(FC_F2I) , RT_FIX, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,Y,N, N,N,D,D,N,Y,N, N,N,N,Y), FLT_D -> List(Y, Y, fc2oh(FC_F2I) , RT_FIX, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,Y,N, N,N,D,D,N,Y,N, N,N,N,Y), FLE_D -> List(Y, Y, fc2oh(FC_F2I) , RT_FIX, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,Y,N, N,N,D,D,N,Y,N, N,N,N,Y), FMIN_S -> List(Y, Y,fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,Y,N, N,N,S,S,N,N,Y, N,N,N,Y), FMAX_S -> List(Y, Y,fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,Y,N, N,N,S,S,N,N,Y, N,N,N,Y), FMIN_D -> List(Y, Y,fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,Y,N, N,N,D,D,N,N,Y, N,N,N,Y), FMAX_D -> List(Y, Y,fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,Y,N, N,N,D,D,N,N,Y, N,N,N,Y), FADD_S -> List(Y, Y,fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_00 ,X,X,Y,Y,N, N,Y,S,S,N,N,N, Y,N,N,Y), FSUB_S -> List(Y, Y,fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_01 ,X,X,Y,Y,N, N,Y,S,S,N,N,N, Y,N,N,Y), FMUL_S -> List(Y, Y,fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_00 ,X,X,Y,Y,N, N,N,S,S,N,N,N, Y,N,N,Y), FADD_D -> List(Y, Y,fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_00 ,X,X,Y,Y,N, N,Y,D,D,N,N,N, Y,N,N,Y), FSUB_D -> List(Y, Y,fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_01 ,X,X,Y,Y,N, N,Y,D,D,N,N,N, Y,N,N,Y), FMUL_D -> List(Y, Y,fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_00 ,X,X,Y,Y,N, N,N,D,D,N,N,N, Y,N,N,Y), FMADD_S -> List(Y, Y,fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, Y, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_00 ,X,X,Y,Y,Y, N,N,S,S,N,N,N, Y,N,N,Y), FMSUB_S -> List(Y, Y,fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, Y, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_01 ,X,X,Y,Y,Y, N,N,S,S,N,N,N, Y,N,N,Y), FNMADD_S -> List(Y, Y,fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, Y, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_11 ,X,X,Y,Y,Y, N,N,S,S,N,N,N, Y,N,N,Y), FNMSUB_S -> List(Y, Y,fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, Y, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_10 ,X,X,Y,Y,Y, N,N,S,S,N,N,N, Y,N,N,Y), FMADD_D -> List(Y, Y,fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, Y, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_00 ,X,X,Y,Y,Y, N,N,D,D,N,N,N, Y,N,N,Y), FMSUB_D -> List(Y, Y,fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, Y, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_01 ,X,X,Y,Y,Y, N,N,D,D,N,N,N, Y,N,N,Y), FNMADD_D -> List(Y, Y,fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, Y, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_11 ,X,X,Y,Y,Y, N,N,D,D,N,N,N, Y,N,N,Y), FNMSUB_D -> List(Y, Y,fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, Y, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_10 ,X,X,Y,Y,Y, N,N,D,D,N,N,N, Y,N,N,Y) ) def FDivSqrt_table: Seq[(BitPat, List[BitPat])] = Seq( FDIV_S -> List(Y, Y, fc2oh(FC_FDV) , RT_FLT, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,Y,X, X,X,S,S,X,X,X, X,Y,N,Y), FDIV_D -> List(Y, Y, fc2oh(FC_FDV) , RT_FLT, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,Y,X, X,X,D,D,X,X,X, X,Y,N,Y), FSQRT_S -> List(Y, Y, fc2oh(FC_FDV) , RT_FLT, RT_FLT, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,N,X, X,X,S,S,X,X,X, X,N,Y,Y), FSQRT_D -> List(Y, Y, fc2oh(FC_FDV) , RT_FLT, RT_FLT, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,N,X, X,X,D,D,X,X,X, X,N,Y,Y), ) def B_table: Seq[(BitPat, List[BitPat])] = Seq( SH1ADD -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_F3,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SH2ADD -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_F3,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SH3ADD -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_F3,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SH1ADD_UW -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_F3,N, N, N, M_X , N, N, CSR.N, DW_32 , FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SH2ADD_UW -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_F3,N, N, N, M_X , N, N, CSR.N, DW_32 , FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SH3ADD_UW -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_F3,N, N, N, M_X , N, N, CSR.N, DW_32 , FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), ADD_UW -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_F3,N, N, N, M_X , N, N, CSR.N, DW_32 , FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SLLI_UW -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_I ,N, N, N, M_X , N, N, CSR.N, DW_32 , FN_SL , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), ANDN -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N ,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_ANDN, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), ORN -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N ,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_ORN , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), XNOR -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N ,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_XNOR, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), MAX -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N ,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_MAX , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), MAXU -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N ,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_MAXU, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), MIN -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N ,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_MIN , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), MINU -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N ,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_MINU, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), ROL -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N ,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_ROL , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), ROR -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N ,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_ROR , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), RORI -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I ,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_ROR , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CLZ -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I ,N, N, N, M_X , N, N, CSR.N, DW_XPR,FN_UNARY, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CTZ -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I ,N, N, N, M_X , N, N, CSR.N, DW_XPR,FN_UNARY, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CPOP -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I ,N, N, N, M_X , N, N, CSR.N, DW_XPR,FN_UNARY, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), ORC_B -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I ,N, N, N, M_X , N, N, CSR.N, DW_XPR,FN_UNARY, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SEXT_B -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I ,N, N, N, M_X , N, N, CSR.N, DW_XPR,FN_UNARY, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SEXT_H -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I ,N, N, N, M_X , N, N, CSR.N, DW_XPR,FN_UNARY, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), ZEXT_H -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I ,N, N, N, M_X , N, N, CSR.N, DW_XPR,FN_UNARY, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), REV8 -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I ,N, N, N, M_X , N, N, CSR.N, DW_XPR,FN_UNARY, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), ROLW -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N ,N, N, N, M_X , N, N, CSR.N, DW_32 , FN_ROL , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), RORW -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N ,N, N, N, M_X , N, N, CSR.N, DW_32 , FN_ROR , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), RORIW -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I ,N, N, N, M_X , N, N, CSR.N, DW_32 , FN_ROR , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CLZW -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I ,N, N, N, M_X , N, N, CSR.N, DW_32 ,FN_UNARY, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CTZW -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I ,N, N, N, M_X , N, N, CSR.N, DW_32 ,FN_UNARY, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CPOPW -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I ,N, N, N, M_X , N, N, CSR.N, DW_32 ,FN_UNARY, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), BCLR -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N ,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_ANDN, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), BCLRI -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I ,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_ANDN, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), BINV -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N ,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_XOR , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), BINVI -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I ,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_XOR , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), BSET -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N ,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_OR , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), BSETI -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I ,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_OR , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), BEXT -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N ,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_BEXT, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), BEXTI -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I ,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_BEXT, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), ) def RoCC_table: Seq[(BitPat, List[BitPat])] = Seq( // Note: We use fc2oh(FC_CSR) since CSR instructions cannot co-execute with RoCC instructions CUSTOM0 -> List(Y, N, fc2oh(FC_CSR) , RT_X , RT_X , RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM0_RS1 -> List(Y, N, fc2oh(FC_CSR) , RT_X , RT_FIX, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM0_RS1_RS2 -> List(Y, N, fc2oh(FC_CSR) , RT_X , RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM0_RD -> List(Y, N, fc2oh(FC_CSR) , RT_FIX, RT_X , RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM0_RD_RS1 -> List(Y, N, fc2oh(FC_CSR) , RT_FIX, RT_FIX, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM0_RD_RS1_RS2 -> List(Y, N, fc2oh(FC_CSR) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM1 -> List(Y, N, fc2oh(FC_CSR) , RT_X , RT_X , RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM1_RS1 -> List(Y, N, fc2oh(FC_CSR) , RT_X , RT_FIX, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM1_RS1_RS2 -> List(Y, N, fc2oh(FC_CSR) , RT_X , RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM1_RD -> List(Y, N, fc2oh(FC_CSR) , RT_FIX, RT_X , RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM1_RD_RS1 -> List(Y, N, fc2oh(FC_CSR) , RT_FIX, RT_FIX, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM1_RD_RS1_RS2 -> List(Y, N, fc2oh(FC_CSR) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM2 -> List(Y, N, fc2oh(FC_CSR) , RT_X , RT_X , RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM2_RS1 -> List(Y, N, fc2oh(FC_CSR) , RT_X , RT_FIX, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM2_RS1_RS2 -> List(Y, N, fc2oh(FC_CSR) , RT_X , RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM2_RD -> List(Y, N, fc2oh(FC_CSR) , RT_FIX, RT_X , RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM2_RD_RS1 -> List(Y, N, fc2oh(FC_CSR) , RT_FIX, RT_FIX, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM2_RD_RS1_RS2 -> List(Y, N, fc2oh(FC_CSR) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM3 -> List(Y, N, fc2oh(FC_CSR) , RT_X , RT_X , RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM3_RS1 -> List(Y, N, fc2oh(FC_CSR) , RT_X , RT_FIX, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM3_RS1_RS2 -> List(Y, N, fc2oh(FC_CSR) , RT_X , RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM3_RD -> List(Y, N, fc2oh(FC_CSR) , RT_FIX, RT_X , RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM3_RD_RS1 -> List(Y, N, fc2oh(FC_CSR) , RT_FIX, RT_FIX, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM3_RD_RS1_RS2 -> List(Y, N, fc2oh(FC_CSR) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X) ) } // scalastyle:on /** * Decoded control signals */ class CtrlSigs(implicit p: Parameters) extends Bundle { val legal = Bool() val fp_val = Bool() val fu_code = UInt(FC_SZ.W) val dst_type = UInt(2.W) val rs1_type = UInt(2.W) val rs2_type = UInt(2.W) val frs3_en = Bool() val imm_sel = UInt(IS_N.getWidth.W) val uses_ldq = Bool() val uses_stq = Bool() val is_amo = Bool() val mem_cmd = UInt(freechips.rocketchip.rocket.M_SZ.W) val inst_unique = Bool() val flush_on_commit = Bool() val csr_cmd = UInt(freechips.rocketchip.rocket.CSR.SZ.W) val fcn_dw = Bool() val fcn_op = UInt(SZ_ALU_FN.W) val fp = new freechips.rocketchip.tile.FPUCtrlSigs() def decode(inst: UInt, table: Iterable[(BitPat, List[BitPat])]) = { val decoder = freechips.rocketchip.rocket.DecodeLogic(inst, DecodeTables.decode_default, table) val sigs = Seq( legal, fp_val, fu_code, dst_type, rs1_type, rs2_type, frs3_en, imm_sel, uses_ldq, uses_stq, is_amo, mem_cmd, inst_unique, flush_on_commit, csr_cmd, fcn_dw, fcn_op, fp.ldst, fp.wen, fp.ren1, fp.ren2, fp.ren3, fp.swap12, fp.swap23, fp.typeTagIn, fp.typeTagOut, fp.fromint, fp.toint, fp.fastpipe, fp.fma, fp.div, fp.sqrt, fp.wflags ) sigs zip decoder map {case(s,d) => s := d} fp.vec := false.B this } } /** * IO bundle for the Decode unit */ class DecodeUnitIo(implicit p: Parameters) extends BoomBundle { val enq = new Bundle { val uop = Input(new MicroOp()) } val deq = new Bundle { val uop = Output(new MicroOp()) } // from CSRFile val status = Input(new freechips.rocketchip.rocket.MStatus()) val csr_decode = Flipped(new freechips.rocketchip.rocket.CSRDecodeIO) val fcsr_rm = Input(UInt(FPConstants.RM_SZ.W)) val interrupt = Input(Bool()) val interrupt_cause = Input(UInt(xLen.W)) } /** * Decode unit that takes in a single instruction and generates a MicroOp. */ class DecodeUnit(implicit p: Parameters) extends BoomModule with freechips.rocketchip.rocket.constants.MemoryOpConstants with freechips.rocketchip.rocket.constants.ScalarOpConstants { val io = IO(new DecodeUnitIo) val uop = Wire(new MicroOp()) uop := io.enq.uop val decode_table = ( DecodeTables.X_table ++ DecodeTables.F_table ++ DecodeTables.FDivSqrt_table ++ DecodeTables.X64_table ++ DecodeTables.B_table ++ (if (usingRoCC) DecodeTables.RoCC_table else Nil) ) val inst = uop.inst val LDST = inst(RD_MSB,RD_LSB) val LRS1 = inst(RS1_MSB,RS1_LSB) val LRS2 = inst(RS2_MSB,RS2_LSB) val LRS3 = inst(RS3_MSB,RS3_LSB) val cs = Wire(new CtrlSigs()).decode(inst, decode_table) // Exception Handling io.csr_decode.inst := inst val csr_en = cs.csr_cmd.isOneOf(CSR.S, CSR.C, CSR.W) val csr_ren = cs.csr_cmd.isOneOf(CSR.S, CSR.C) && uop.lrs1 === 0.U val system_insn = cs.csr_cmd === CSR.I val sfence = inst === SFENCE_VMA val cs_legal = cs.legal // dontTouch(cs_legal) require (fLen >= 64) val illegal_rm = inst(14,12).isOneOf(5.U,6.U) || (inst(14,12) === 7.U && io.fcsr_rm >= 5.U) val id_illegal_insn = (!cs_legal || (cs.fp_val && (io.csr_decode.fp_illegal || illegal_rm)) || (uop.is_rocc && io.csr_decode.rocc_illegal) || (cs.is_amo && !io.status.isa('a'-'a')) || (csr_en && (io.csr_decode.read_illegal || !csr_ren && io.csr_decode.write_illegal)) || ((sfence || system_insn) && io.csr_decode.system_illegal)) // cs.div && !csr.io.status.isa('m'-'a') || TODO check for illegal div instructions def checkExceptions(x: Seq[(Bool, UInt)]) = (x.map(_._1).reduce(_||_), PriorityMux(x)) val (xcpt_valid, xcpt_cause) = checkExceptions(List( (io.interrupt && !io.enq.uop.is_sfb, io.interrupt_cause), // Disallow interrupts while we are handling a SFB (uop.bp_debug_if, (CSR.debugTriggerCause).U), (uop.bp_xcpt_if, (Causes.breakpoint).U), (uop.xcpt_pf_if, (Causes.fetch_page_fault).U), (uop.xcpt_ae_if, (Causes.fetch_access).U), (id_illegal_insn, (Causes.illegal_instruction).U))) uop.exception := xcpt_valid uop.exc_cause := xcpt_cause //------------------------------------------------------------- uop.is_mov := inst === ADD && LRS1 === 0.U uop.iq_type(IQ_UNQ) := Seq(FC_MUL , FC_DIV, FC_CSR, FC_I2F).map { c => cs.fu_code(c) }.reduce(_||_) uop.iq_type(IQ_ALU) := Seq(FC_ALU ).map { c => cs.fu_code(c) }.reduce(_||_) uop.iq_type(IQ_MEM) := Seq(FC_AGEN, FC_DGEN ).map { c => cs.fu_code(c) }.reduce(_||_) uop.iq_type(IQ_FP ) := Seq(FC_FPU , FC_FDV, FC_F2I ).map { c => cs.fu_code(c) }.reduce(_||_) uop.fu_code := cs.fu_code.asBools uop.ldst := LDST uop.lrs1 := LRS1 uop.lrs2 := LRS2 uop.lrs3 := LRS3 uop.dst_rtype := cs.dst_type uop.lrs1_rtype := Mux(cs.rs1_type === RT_FIX && LRS1 === 0.U, RT_ZERO, cs.rs1_type) uop.lrs2_rtype := Mux(cs.rs2_type === RT_FIX && LRS2 === 0.U, RT_ZERO, cs.rs2_type) uop.frs3_en := cs.frs3_en uop.ldst_is_rs1 := uop.is_sfb_shadow // SFB optimization when (uop.is_sfb_shadow && cs.rs2_type === RT_X) { uop.lrs2_rtype := Mux(LDST === 0.U, RT_ZERO, RT_FIX) uop.lrs2 := LDST uop.ldst_is_rs1 := false.B } .elsewhen (uop.is_sfb_shadow && uop.is_mov) { uop.lrs1 := LDST uop.lrs1_rtype := Mux(LDST === 0.U, RT_ZERO, RT_FIX) uop.ldst_is_rs1 := true.B } uop.fp_val := cs.fp_val uop.fp_ctrl := cs.fp uop.mem_cmd := cs.mem_cmd uop.mem_size := Mux(cs.mem_cmd.isOneOf(M_SFENCE, M_FLUSH_ALL), Cat(LRS2 =/= 0.U, LRS1 =/= 0.U), inst(13,12)) uop.mem_signed := !inst(14) uop.uses_ldq := cs.uses_ldq uop.uses_stq := cs.uses_stq uop.is_amo := cs.is_amo uop.is_fence := inst === FENCE uop.is_fencei := inst === FENCE_I uop.is_sfence := inst === SFENCE_VMA uop.is_sys_pc2epc := inst === EBREAK || inst === ECALL uop.is_eret := inst === ECALL || inst === EBREAK || inst === SRET || inst === MRET || inst === DRET uop.is_unique := cs.inst_unique uop.is_rocc := inst(6,0).isOneOf("b0001011".U, "b0101011".U, "b1111011".U) && inst(14,12).isOneOf(0.U, 2.U, 3.U, 4.U, 6.U, 7.U) uop.flush_on_commit := cs.flush_on_commit || (csr_en && !csr_ren && io.csr_decode.write_flush) //------------------------------------------------------------- // immediates // repackage the immediate, and then pass the fewest number of bits around val di24_20 = Mux(cs.imm_sel === IS_B || cs.imm_sel === IS_S, inst(11,7), inst(24,20)) val imm_packed = Cat(inst(31,25), di24_20, inst(19,12)) val imm = ImmGen(imm_packed, cs.imm_sel) val imm_hi = imm >> (immPregSz-1) val imm_lo = imm(immPregSz-1, 0) val short_imm = imm_hi === 0.U || ~imm_hi === 0.U || cs.imm_sel === IS_F3 uop.imm_rename := cs.imm_sel =/= IS_N && cs.imm_sel =/= IS_F3 uop.imm_packed := imm_packed uop.imm_sel := cs.imm_sel when (short_imm) { uop.imm_rename := false.B uop.imm_sel := IS_SH uop.pimm := Mux(cs.imm_sel === IS_F3, inst(14,12), imm_lo) } uop.fp_rm := Mux(inst(14,12) === 7.U, io.fcsr_rm, inst(14,12)) uop.fp_typ := inst(21,20) //------------------------------------------------------------- uop.csr_cmd := cs.csr_cmd when ((cs.csr_cmd === CSR.S || cs.csr_cmd === CSR.C) && LRS1 === 0.U) { uop.csr_cmd := CSR.R } uop.fcn_dw := cs.fcn_dw uop.fcn_op := cs.fcn_op uop.op1_sel := OP1_RS1 when (inst === LUI || inst === CSRRWI || inst === CSRRSI || inst === CSRRCI || inst === WFI || inst === SRET || inst === MRET || inst === DRET) { uop.op1_sel := OP1_ZERO } .elsewhen (inst === JAL || inst === JALR || inst === AUIPC) { uop.op1_sel := OP1_PC } .elsewhen (Seq(SH1ADD, SH2ADD, SH3ADD, SH1ADD_UW, SH2ADD_UW, SH3ADD_UW, ADD_UW, SLLI_UW).map(_ === inst).orR) { uop.op1_sel := OP1_RS1SHL } uop.op2_sel := OP2_RS2 when (cs.is_amo || inst === CSRRW || inst === CSRRS || inst === CSRRC) { uop.op2_sel := OP2_ZERO } .elsewhen (inst === CSRRWI || inst === CSRRSI || inst === CSRRCI || inst === WFI || inst === SRET || inst === DRET || inst === MRET) { uop.op2_sel := OP2_IMMC } .elsewhen (inst === JAL || inst === JALR) { uop.op2_sel := OP2_NEXT } .elsewhen (Seq(BCLR, BCLRI, BINV, BINVI, BSET, BSETI).map(_ === inst).orR) { uop.op2_sel := Mux(uop.lrs2_rtype === RT_FIX, OP2_RS2OH, OP2_IMMOH) } .elsewhen (cs.imm_sel === IS_U || cs.imm_sel === IS_I || cs.imm_sel === IS_S) { uop.op2_sel := OP2_IMM } uop.br_type := Seq( (BEQ , B_EQ ), (BNE , B_NE ), (BGE , B_GE ), (BGEU , B_GEU), (BLT , B_LT ), (BLTU , B_LTU), (JAL , B_J ), (JALR , B_JR ) ) .map { case (c, b) => Mux(inst === c, b, 0.U) } .reduce(_|_) io.deq.uop := uop } /** * Smaller Decode unit for the Frontend to decode different * branches. * Accepts EXPANDED RVC instructions */ class BranchDecodeSignals(implicit p: Parameters) extends BoomBundle { val is_ret = Bool() val is_call = Bool() val target = UInt(vaddrBitsExtended.W) val cfi_type = UInt(CFI_SZ.W) // Is this branch a short forwards jump? val sfb_offset = Valid(UInt(log2Ceil(icBlockBytes).W)) // Is this instruction allowed to be inside a sfb? val shadowable = Bool() } class BranchDecode(implicit p: Parameters) extends BoomModule { val io = IO(new Bundle { val inst = Input(UInt(32.W)) val pc = Input(UInt(vaddrBitsExtended.W)) val out = Output(new BranchDecodeSignals) }) val bpd_csignals = freechips.rocketchip.rocket.DecodeLogic(io.inst, List[BitPat](N, N, N, N, X), //// is br? //// | is jal? //// | | is jalr? //// | | | //// | | | shadowable //// | | | | has_rs2 //// | | | | | Seq[(BitPat, List[BitPat])]( JAL -> List(N, Y, N, N, X), JALR -> List(N, N, Y, N, X), BEQ -> List(Y, N, N, N, X), BNE -> List(Y, N, N, N, X), BGE -> List(Y, N, N, N, X), BGEU -> List(Y, N, N, N, X), BLT -> List(Y, N, N, N, X), BLTU -> List(Y, N, N, N, X), SLLI -> List(N, N, N, Y, N), SRLI -> List(N, N, N, Y, N), SRAI -> List(N, N, N, Y, N), ADDIW -> List(N, N, N, Y, N), SLLIW -> List(N, N, N, Y, N), SRAIW -> List(N, N, N, Y, N), SRLIW -> List(N, N, N, Y, N), ADDW -> List(N, N, N, Y, Y), SUBW -> List(N, N, N, Y, Y), SLLW -> List(N, N, N, Y, Y), SRAW -> List(N, N, N, Y, Y), SRLW -> List(N, N, N, Y, Y), LUI -> List(N, N, N, Y, N), ADDI -> List(N, N, N, Y, N), ANDI -> List(N, N, N, Y, N), ORI -> List(N, N, N, Y, N), XORI -> List(N, N, N, Y, N), SLTI -> List(N, N, N, Y, N), SLTIU -> List(N, N, N, Y, N), SLL -> List(N, N, N, Y, Y), ADD -> List(N, N, N, Y, Y), SUB -> List(N, N, N, Y, Y), SLT -> List(N, N, N, Y, Y), SLTU -> List(N, N, N, Y, Y), AND -> List(N, N, N, Y, Y), OR -> List(N, N, N, Y, Y), XOR -> List(N, N, N, Y, Y), SRA -> List(N, N, N, Y, Y), SRL -> List(N, N, N, Y, Y) )) val cs_is_br = bpd_csignals(0)(0) val cs_is_jal = bpd_csignals(1)(0) val cs_is_jalr = bpd_csignals(2)(0) val cs_is_shadowable = bpd_csignals(3)(0) val cs_has_rs2 = bpd_csignals(4)(0) io.out.is_call := (cs_is_jal || cs_is_jalr) && GetRd(io.inst) === RA io.out.is_ret := cs_is_jalr && GetRs1(io.inst) === BitPat("b00?01") && GetRd(io.inst) === X0 io.out.target := Mux(cs_is_br, ComputeBranchTarget(io.pc, io.inst, xLen), ComputeJALTarget(io.pc, io.inst, xLen)) io.out.cfi_type := Mux(cs_is_jalr, CFI_JALR, Mux(cs_is_jal, CFI_JAL, Mux(cs_is_br, CFI_BR, CFI_X))) val br_offset = Cat(io.inst(7), io.inst(30,25), io.inst(11,8), 0.U(1.W)) // Is a sfb if it points forwards (offset is positive) io.out.sfb_offset.valid := cs_is_br && !io.inst(31) && br_offset =/= 0.U && (br_offset >> log2Ceil(icBlockBytes)) === 0.U io.out.sfb_offset.bits := br_offset io.out.shadowable := cs_is_shadowable && ( !cs_has_rs2 || (GetRs1(io.inst) === GetRd(io.inst)) || (io.inst === ADD && GetRs1(io.inst) === X0) ) } /** * Track the current "branch mask", and give out the branch mask to each micro-op in Decode * (each micro-op in the machine has a branch mask which says which branches it * is being speculated under). * * @param pl_width pipeline width for the processor */ class BranchMaskGenerationLogic(val pl_width: Int)(implicit p: Parameters) extends BoomModule { val io = IO(new Bundle { // guess if the uop is a branch (we'll catch this later) val is_branch = Input(Vec(pl_width, Bool())) // lock in that it's actually a branch and will fire, so we update // the branch_masks. val will_fire = Input(Vec(pl_width, Bool())) // give out tag immediately (needed in rename) // mask can come later in the cycle val br_tag = Output(Vec(pl_width, UInt(brTagSz.W))) val br_mask = Output(Vec(pl_width, UInt(maxBrCount.W))) // tell decoders the branch mask has filled up, but on the granularity // of an individual micro-op (so some micro-ops can go through) val is_full = Output(Vec(pl_width, Bool())) val brupdate = Input(new BrUpdateInfo()) val flush_pipeline = Input(Bool()) val debug_branch_mask = Output(UInt(maxBrCount.W)) }) val branch_mask = RegInit(0.U(maxBrCount.W)) //------------------------------------------------------------- // Give out the branch tag to each branch micro-op var allocate_mask = branch_mask val tag_masks = Wire(Vec(pl_width, UInt(maxBrCount.W))) for (w <- 0 until pl_width) { // TODO this is a loss of performance as we're blocking branches based on potentially fake branches io.is_full(w) := (allocate_mask === ~(0.U(maxBrCount.W))) && io.is_branch(w) // find br_tag and compute next br_mask val new_br_tag = Wire(UInt(brTagSz.W)) new_br_tag := 0.U tag_masks(w) := 0.U for (i <- maxBrCount-1 to 0 by -1) { when (~allocate_mask(i)) { new_br_tag := i.U tag_masks(w) := (1.U << i.U) } } io.br_tag(w) := new_br_tag allocate_mask = Mux(io.is_branch(w), tag_masks(w) | allocate_mask, allocate_mask) } //------------------------------------------------------------- // Give out the branch mask to each micro-op // (kill off the bits that corresponded to branches that aren't going to fire) var curr_mask = branch_mask for (w <- 0 until pl_width) { io.br_mask(w) := GetNewBrMask(io.brupdate, curr_mask) curr_mask = Mux(io.will_fire(w), tag_masks(w) | curr_mask, curr_mask) } //------------------------------------------------------------- // Update the current branch_mask when (io.flush_pipeline) { branch_mask := 0.U } .otherwise { val mask = Mux(io.brupdate.b2.mispredict, io.brupdate.b2.uop.br_mask, ~(0.U(maxBrCount.W))) branch_mask := GetNewBrMask(io.brupdate, curr_mask) & mask } io.debug_branch_mask := branch_mask }

module DecodeUnit_1( // @[decode.scala:422:7] input clock, // @[decode.scala:422:7] input reset, // @[decode.scala:422:7] input [31:0] io_enq_uop_inst, // @[decode.scala:426:14] input [31:0] io_enq_uop_debug_inst, // @[decode.scala:426:14] input io_enq_uop_is_rvc, // @[decode.scala:426:14] input [39:0] io_enq_uop_debug_pc, // @[decode.scala:426:14] input io_enq_uop_is_sfb, // @[decode.scala:426:14] input [4:0] io_enq_uop_ftq_idx, // @[decode.scala:426:14] input io_enq_uop_edge_inst, // @[decode.scala:426:14] input [5:0] io_enq_uop_pc_lob, // @[decode.scala:426:14] input io_enq_uop_taken, // @[decode.scala:426:14] input io_enq_uop_xcpt_pf_if, // @[decode.scala:426:14] input io_enq_uop_xcpt_ae_if, // @[decode.scala:426:14] input io_enq_uop_bp_debug_if, // @[decode.scala:426:14] input io_enq_uop_bp_xcpt_if, // @[decode.scala:426:14] input [2:0] io_enq_uop_debug_fsrc, // @[decode.scala:426:14] output [31:0] io_deq_uop_inst, // @[decode.scala:426:14] output [31:0] io_deq_uop_debug_inst, // @[decode.scala:426:14] output io_deq_uop_is_rvc, // @[decode.scala:426:14] output [39:0] io_deq_uop_debug_pc, // @[decode.scala:426:14] output io_deq_uop_iq_type_0, // @[decode.scala:426:14] output io_deq_uop_iq_type_1, // @[decode.scala:426:14] output io_deq_uop_iq_type_2, // @[decode.scala:426:14] output io_deq_uop_iq_type_3, // @[decode.scala:426:14] output io_deq_uop_fu_code_0, // @[decode.scala:426:14] output io_deq_uop_fu_code_1, // @[decode.scala:426:14] output io_deq_uop_fu_code_2, // @[decode.scala:426:14] output io_deq_uop_fu_code_3, // @[decode.scala:426:14] output io_deq_uop_fu_code_4, // @[decode.scala:426:14] output io_deq_uop_fu_code_5, // @[decode.scala:426:14] output io_deq_uop_fu_code_6, // @[decode.scala:426:14] output io_deq_uop_fu_code_7, // @[decode.scala:426:14] output io_deq_uop_fu_code_8, // @[decode.scala:426:14] output io_deq_uop_fu_code_9, // @[decode.scala:426:14] output [3:0] io_deq_uop_br_type, // @[decode.scala:426:14] output io_deq_uop_is_sfb, // @[decode.scala:426:14] output io_deq_uop_is_fence, // @[decode.scala:426:14] output io_deq_uop_is_fencei, // @[decode.scala:426:14] output io_deq_uop_is_sfence, // @[decode.scala:426:14] output io_deq_uop_is_amo, // @[decode.scala:426:14] output io_deq_uop_is_eret, // @[decode.scala:426:14] output io_deq_uop_is_sys_pc2epc, // @[decode.scala:426:14] output io_deq_uop_is_rocc, // @[decode.scala:426:14] output io_deq_uop_is_mov, // @[decode.scala:426:14] output [4:0] io_deq_uop_ftq_idx, // @[decode.scala:426:14] output io_deq_uop_edge_inst, // @[decode.scala:426:14] output [5:0] io_deq_uop_pc_lob, // @[decode.scala:426:14] output io_deq_uop_taken, // @[decode.scala:426:14] output io_deq_uop_imm_rename, // @[decode.scala:426:14] output [2:0] io_deq_uop_imm_sel, // @[decode.scala:426:14] output [4:0] io_deq_uop_pimm, // @[decode.scala:426:14] output [19:0] io_deq_uop_imm_packed, // @[decode.scala:426:14] output [1:0] io_deq_uop_op1_sel, // @[decode.scala:426:14] output [2:0] io_deq_uop_op2_sel, // @[decode.scala:426:14] output io_deq_uop_fp_ctrl_ldst, // @[decode.scala:426:14] output io_deq_uop_fp_ctrl_wen, // @[decode.scala:426:14] output io_deq_uop_fp_ctrl_ren1, // @[decode.scala:426:14] output io_deq_uop_fp_ctrl_ren2, // @[decode.scala:426:14] output io_deq_uop_fp_ctrl_ren3, // @[decode.scala:426:14] output io_deq_uop_fp_ctrl_swap12, // @[decode.scala:426:14] output io_deq_uop_fp_ctrl_swap23, // @[decode.scala:426:14] output [1:0] io_deq_uop_fp_ctrl_typeTagIn, // @[decode.scala:426:14] output [1:0] io_deq_uop_fp_ctrl_typeTagOut, // @[decode.scala:426:14] output io_deq_uop_fp_ctrl_fromint, // @[decode.scala:426:14] output io_deq_uop_fp_ctrl_toint, // @[decode.scala:426:14] output io_deq_uop_fp_ctrl_fastpipe, // @[decode.scala:426:14] output io_deq_uop_fp_ctrl_fma, // @[decode.scala:426:14] output io_deq_uop_fp_ctrl_div, // @[decode.scala:426:14] output io_deq_uop_fp_ctrl_sqrt, // @[decode.scala:426:14] output io_deq_uop_fp_ctrl_wflags, // @[decode.scala:426:14] output io_deq_uop_exception, // @[decode.scala:426:14] output [63:0] io_deq_uop_exc_cause, // @[decode.scala:426:14] output [4:0] io_deq_uop_mem_cmd, // @[decode.scala:426:14] output [1:0] io_deq_uop_mem_size, // @[decode.scala:426:14] output io_deq_uop_mem_signed, // @[decode.scala:426:14] output io_deq_uop_uses_ldq, // @[decode.scala:426:14] output io_deq_uop_uses_stq, // @[decode.scala:426:14] output io_deq_uop_is_unique, // @[decode.scala:426:14] output io_deq_uop_flush_on_commit, // @[decode.scala:426:14] output [2:0] io_deq_uop_csr_cmd, // @[decode.scala:426:14] output io_deq_uop_ldst_is_rs1, // @[decode.scala:426:14] output [5:0] io_deq_uop_ldst, // @[decode.scala:426:14] output [5:0] io_deq_uop_lrs1, // @[decode.scala:426:14] output [5:0] io_deq_uop_lrs2, // @[decode.scala:426:14] output [5:0] io_deq_uop_lrs3, // @[decode.scala:426:14] output [1:0] io_deq_uop_dst_rtype, // @[decode.scala:426:14] output [1:0] io_deq_uop_lrs1_rtype, // @[decode.scala:426:14] output [1:0] io_deq_uop_lrs2_rtype, // @[decode.scala:426:14] output io_deq_uop_frs3_en, // @[decode.scala:426:14] output io_deq_uop_fcn_dw, // @[decode.scala:426:14] output [4:0] io_deq_uop_fcn_op, // @[decode.scala:426:14] output io_deq_uop_fp_val, // @[decode.scala:426:14] output [2:0] io_deq_uop_fp_rm, // @[decode.scala:426:14] output [1:0] io_deq_uop_fp_typ, // @[decode.scala:426:14] output io_deq_uop_xcpt_pf_if, // @[decode.scala:426:14] output io_deq_uop_xcpt_ae_if, // @[decode.scala:426:14] output io_deq_uop_bp_debug_if, // @[decode.scala:426:14] output io_deq_uop_bp_xcpt_if, // @[decode.scala:426:14] output [2:0] io_deq_uop_debug_fsrc, // @[decode.scala:426:14] input io_status_debug, // @[decode.scala:426:14] input io_status_cease, // @[decode.scala:426:14] input io_status_wfi, // @[decode.scala:426:14] input [1:0] io_status_dprv, // @[decode.scala:426:14] input io_status_dv, // @[decode.scala:426:14] input [1:0] io_status_prv, // @[decode.scala:426:14] input io_status_v, // @[decode.scala:426:14] input io_status_sd, // @[decode.scala:426:14] input io_status_mpv, // @[decode.scala:426:14] input io_status_gva, // @[decode.scala:426:14] input io_status_tsr, // @[decode.scala:426:14] input io_status_tw, // @[decode.scala:426:14] input io_status_tvm, // @[decode.scala:426:14] input io_status_mxr, // @[decode.scala:426:14] input io_status_sum, // @[decode.scala:426:14] input io_status_mprv, // @[decode.scala:426:14] input [1:0] io_status_fs, // @[decode.scala:426:14] input [1:0] io_status_mpp, // @[decode.scala:426:14] input io_status_spp, // @[decode.scala:426:14] input io_status_mpie, // @[decode.scala:426:14] input io_status_spie, // @[decode.scala:426:14] input io_status_mie, // @[decode.scala:426:14] input io_status_sie, // @[decode.scala:426:14] output [31:0] io_csr_decode_inst, // @[decode.scala:426:14] input io_csr_decode_fp_illegal, // @[decode.scala:426:14] input io_csr_decode_fp_csr, // @[decode.scala:426:14] input io_csr_decode_read_illegal, // @[decode.scala:426:14] input io_csr_decode_write_illegal, // @[decode.scala:426:14] input io_csr_decode_write_flush, // @[decode.scala:426:14] input io_csr_decode_system_illegal, // @[decode.scala:426:14] input io_csr_decode_virtual_access_illegal, // @[decode.scala:426:14] input io_csr_decode_virtual_system_illegal, // @[decode.scala:426:14] input [2:0] io_fcsr_rm, // @[decode.scala:426:14] input io_interrupt, // @[decode.scala:426:14] input [63:0] io_interrupt_cause // @[decode.scala:426:14] ); wire [31:0] io_enq_uop_inst_0 = io_enq_uop_inst; // @[decode.scala:422:7] wire [31:0] io_enq_uop_debug_inst_0 = io_enq_uop_debug_inst; // @[decode.scala:422:7] wire io_enq_uop_is_rvc_0 = io_enq_uop_is_rvc; // @[decode.scala:422:7] wire [39:0] io_enq_uop_debug_pc_0 = io_enq_uop_debug_pc; // @[decode.scala:422:7] wire io_enq_uop_is_sfb_0 = io_enq_uop_is_sfb; // @[decode.scala:422:7] wire [4:0] io_enq_uop_ftq_idx_0 = io_enq_uop_ftq_idx; // @[decode.scala:422:7] wire io_enq_uop_edge_inst_0 = io_enq_uop_edge_inst; // @[decode.scala:422:7] wire [5:0] io_enq_uop_pc_lob_0 = io_enq_uop_pc_lob; // @[decode.scala:422:7] wire io_enq_uop_taken_0 = io_enq_uop_taken; // @[decode.scala:422:7] wire io_enq_uop_xcpt_pf_if_0 = io_enq_uop_xcpt_pf_if; // @[decode.scala:422:7] wire io_enq_uop_xcpt_ae_if_0 = io_enq_uop_xcpt_ae_if; // @[decode.scala:422:7] wire io_enq_uop_bp_debug_if_0 = io_enq_uop_bp_debug_if; // @[decode.scala:422:7] wire io_enq_uop_bp_xcpt_if_0 = io_enq_uop_bp_xcpt_if; // @[decode.scala:422:7] wire [2:0] io_enq_uop_debug_fsrc_0 = io_enq_uop_debug_fsrc; // @[decode.scala:422:7] wire io_status_debug_0 = io_status_debug; // @[decode.scala:422:7] wire io_status_cease_0 = io_status_cease; // @[decode.scala:422:7] wire io_status_wfi_0 = io_status_wfi; // @[decode.scala:422:7] wire [1:0] io_status_dprv_0 = io_status_dprv; // @[decode.scala:422:7] wire io_status_dv_0 = io_status_dv; // @[decode.scala:422:7] wire [1:0] io_status_prv_0 = io_status_prv; // @[decode.scala:422:7] wire io_status_v_0 = io_status_v; // @[decode.scala:422:7] wire io_status_sd_0 = io_status_sd; // @[decode.scala:422:7] wire io_status_mpv_0 = io_status_mpv; // @[decode.scala:422:7] wire io_status_gva_0 = io_status_gva; // @[decode.scala:422:7] wire io_status_tsr_0 = io_status_tsr; // @[decode.scala:422:7] wire io_status_tw_0 = io_status_tw; // @[decode.scala:422:7] wire io_status_tvm_0 = io_status_tvm; // @[decode.scala:422:7] wire io_status_mxr_0 = io_status_mxr; // @[decode.scala:422:7] wire io_status_sum_0 = io_status_sum; // @[decode.scala:422:7] wire io_status_mprv_0 = io_status_mprv; // @[decode.scala:422:7] wire [1:0] io_status_fs_0 = io_status_fs; // @[decode.scala:422:7] wire [1:0] io_status_mpp_0 = io_status_mpp; // @[decode.scala:422:7] wire io_status_spp_0 = io_status_spp; // @[decode.scala:422:7] wire io_status_mpie_0 = io_status_mpie; // @[decode.scala:422:7] wire io_status_spie_0 = io_status_spie; // @[decode.scala:422:7] wire io_status_mie_0 = io_status_mie; // @[decode.scala:422:7] wire io_status_sie_0 = io_status_sie; // @[decode.scala:422:7] wire io_csr_decode_fp_illegal_0 = io_csr_decode_fp_illegal; // @[decode.scala:422:7] wire io_csr_decode_fp_csr_0 = io_csr_decode_fp_csr; // @[decode.scala:422:7] wire io_csr_decode_read_illegal_0 = io_csr_decode_read_illegal; // @[decode.scala:422:7] wire io_csr_decode_write_illegal_0 = io_csr_decode_write_illegal; // @[decode.scala:422:7] wire io_csr_decode_write_flush_0 = io_csr_decode_write_flush; // @[decode.scala:422:7] wire io_csr_decode_system_illegal_0 = io_csr_decode_system_illegal; // @[decode.scala:422:7] wire io_csr_decode_virtual_access_illegal_0 = io_csr_decode_virtual_access_illegal; // @[decode.scala:422:7] wire io_csr_decode_virtual_system_illegal_0 = io_csr_decode_virtual_system_illegal; // @[decode.scala:422:7] wire [2:0] io_fcsr_rm_0 = io_fcsr_rm; // @[decode.scala:422:7] wire io_interrupt_0 = io_interrupt; // @[decode.scala:422:7] wire [63:0] io_interrupt_cause_0 = io_interrupt_cause; // @[decode.scala:422:7] wire [1:0] io_status_sxl = 2'h2; // @[decode.scala:422:7] wire [1:0] io_status_uxl = 2'h2; // @[decode.scala:422:7] wire io_csr_decode_vector_illegal = 1'h1; // @[decode.scala:422:7] wire io_csr_decode_rocc_illegal = 1'h1; // @[decode.scala:422:7] wire _id_illegal_insn_T_6 = 1'h1; // @[decode.scala:464:33] wire [7:0] io_status_zero1 = 8'h0; // @[decode.scala:422:7, :426:14] wire [22:0] io_status_zero2 = 23'h0; // @[decode.scala:422:7, :426:14] wire [31:0] io_status_isa = 32'h14112D; // @[decode.scala:422:7, :426:14] wire [63:0] io_enq_uop_exc_cause = 64'h0; // @[decode.scala:422:7, :426:14] wire [6:0] io_enq_uop_pdst = 7'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [6:0] io_enq_uop_prs1 = 7'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [6:0] io_enq_uop_prs2 = 7'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [6:0] io_enq_uop_prs3 = 7'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [6:0] io_enq_uop_stale_pdst = 7'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [6:0] io_deq_uop_pdst = 7'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [6:0] io_deq_uop_prs1 = 7'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [6:0] io_deq_uop_prs2 = 7'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [6:0] io_deq_uop_prs3 = 7'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [6:0] io_deq_uop_stale_pdst = 7'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [6:0] uop_pdst = 7'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [6:0] uop_prs1 = 7'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [6:0] uop_prs2 = 7'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [6:0] uop_prs3 = 7'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [6:0] uop_stale_pdst = 7'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [5:0] io_enq_uop_rob_idx = 6'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [5:0] io_enq_uop_ldst = 6'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [5:0] io_enq_uop_lrs1 = 6'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [5:0] io_enq_uop_lrs2 = 6'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [5:0] io_enq_uop_lrs3 = 6'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [5:0] io_deq_uop_rob_idx = 6'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [5:0] uop_rob_idx = 6'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [19:0] io_enq_uop_imm_packed = 20'h0; // @[decode.scala:422:7] wire [4:0] io_enq_uop_pimm = 5'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [4:0] io_enq_uop_ppred = 5'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [4:0] io_enq_uop_mem_cmd = 5'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [4:0] io_enq_uop_fcn_op = 5'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [4:0] io_deq_uop_ppred = 5'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [4:0] uop_ppred = 5'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [2:0] io_enq_uop_imm_sel = 3'h0; // @[decode.scala:422:7] wire [2:0] io_enq_uop_op2_sel = 3'h0; // @[decode.scala:422:7] wire [2:0] io_enq_uop_csr_cmd = 3'h0; // @[decode.scala:422:7] wire [2:0] io_enq_uop_fp_rm = 3'h0; // @[decode.scala:422:7] wire [2:0] io_enq_uop_debug_tsrc = 3'h0; // @[decode.scala:422:7] wire [2:0] io_deq_uop_debug_tsrc = 3'h0; // @[decode.scala:422:7] wire [2:0] uop_debug_tsrc = 3'h0; // @[decode.scala:428:17] wire [3:0] io_enq_uop_br_tag = 4'h0; // @[decode.scala:422:7] wire [3:0] io_enq_uop_br_type = 4'h0; // @[decode.scala:422:7] wire [3:0] io_enq_uop_ldq_idx = 4'h0; // @[decode.scala:422:7] wire [3:0] io_enq_uop_stq_idx = 4'h0; // @[decode.scala:422:7] wire [3:0] io_deq_uop_br_tag = 4'h0; // @[decode.scala:422:7] wire [3:0] io_deq_uop_ldq_idx = 4'h0; // @[decode.scala:422:7] wire [3:0] io_deq_uop_stq_idx = 4'h0; // @[decode.scala:422:7] wire [3:0] uop_br_tag = 4'h0; // @[decode.scala:428:17] wire [3:0] uop_ldq_idx = 4'h0; // @[decode.scala:428:17] wire [3:0] uop_stq_idx = 4'h0; // @[decode.scala:428:17] wire [11:0] io_enq_uop_br_mask = 12'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [11:0] io_deq_uop_br_mask = 12'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [11:0] uop_br_mask = 12'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [1:0] io_enq_uop_iw_p1_speculative_child = 2'h0; // @[decode.scala:422:7] wire [1:0] io_enq_uop_iw_p2_speculative_child = 2'h0; // @[decode.scala:422:7] wire [1:0] io_enq_uop_dis_col_sel = 2'h0; // @[decode.scala:422:7] wire [1:0] io_enq_uop_op1_sel = 2'h0; // @[decode.scala:422:7] wire [1:0] io_enq_uop_fp_ctrl_typeTagIn = 2'h0; // @[decode.scala:422:7] wire [1:0] io_enq_uop_fp_ctrl_typeTagOut = 2'h0; // @[decode.scala:422:7] wire [1:0] io_enq_uop_rxq_idx = 2'h0; // @[decode.scala:422:7] wire [1:0] io_enq_uop_mem_size = 2'h0; // @[decode.scala:422:7] wire [1:0] io_enq_uop_dst_rtype = 2'h0; // @[decode.scala:422:7] wire [1:0] io_enq_uop_lrs1_rtype = 2'h0; // @[decode.scala:422:7] wire [1:0] io_enq_uop_lrs2_rtype = 2'h0; // @[decode.scala:422:7] wire [1:0] io_enq_uop_fp_typ = 2'h0; // @[decode.scala:422:7] wire [1:0] io_deq_uop_iw_p1_speculative_child = 2'h0; // @[decode.scala:422:7] wire [1:0] io_deq_uop_iw_p2_speculative_child = 2'h0; // @[decode.scala:422:7] wire [1:0] io_deq_uop_dis_col_sel = 2'h0; // @[decode.scala:422:7] wire [1:0] io_deq_uop_rxq_idx = 2'h0; // @[decode.scala:422:7] wire [1:0] io_status_xs = 2'h0; // @[decode.scala:422:7] wire [1:0] io_status_vs = 2'h0; // @[decode.scala:422:7] wire [1:0] uop_iw_p1_speculative_child = 2'h0; // @[decode.scala:428:17] wire [1:0] uop_iw_p2_speculative_child = 2'h0; // @[decode.scala:428:17] wire [1:0] uop_dis_col_sel = 2'h0; // @[decode.scala:428:17] wire [1:0] uop_rxq_idx = 2'h0; // @[decode.scala:428:17] wire io_enq_uop_iq_type_0 = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_iq_type_1 = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_iq_type_2 = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_iq_type_3 = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fu_code_0 = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fu_code_1 = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fu_code_2 = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fu_code_3 = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fu_code_4 = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fu_code_5 = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fu_code_6 = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fu_code_7 = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fu_code_8 = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fu_code_9 = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_iw_issued = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_iw_issued_partial_agen = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_iw_issued_partial_dgen = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_iw_p1_bypass_hint = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_iw_p2_bypass_hint = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_iw_p3_bypass_hint = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_is_fence = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_is_fencei = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_is_sfence = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_is_amo = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_is_eret = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_is_sys_pc2epc = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_is_rocc = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_is_mov = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_imm_rename = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fp_ctrl_ldst = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fp_ctrl_wen = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fp_ctrl_ren1 = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fp_ctrl_ren2 = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fp_ctrl_ren3 = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fp_ctrl_swap12 = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fp_ctrl_swap23 = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fp_ctrl_fromint = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fp_ctrl_toint = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fp_ctrl_fastpipe = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fp_ctrl_fma = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fp_ctrl_div = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fp_ctrl_sqrt = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fp_ctrl_wflags = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fp_ctrl_vec = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_prs1_busy = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_prs2_busy = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_prs3_busy = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_ppred_busy = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_exception = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_mem_signed = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_uses_ldq = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_uses_stq = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_is_unique = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_flush_on_commit = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_ldst_is_rs1 = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_frs3_en = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fcn_dw = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fp_val = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_xcpt_ma_if = 1'h0; // @[decode.scala:422:7] wire io_deq_uop_iw_issued = 1'h0; // @[decode.scala:422:7] wire io_deq_uop_iw_issued_partial_agen = 1'h0; // @[decode.scala:422:7] wire io_deq_uop_iw_issued_partial_dgen = 1'h0; // @[decode.scala:422:7] wire io_deq_uop_iw_p1_bypass_hint = 1'h0; // @[decode.scala:422:7] wire io_deq_uop_iw_p2_bypass_hint = 1'h0; // @[decode.scala:422:7] wire io_deq_uop_iw_p3_bypass_hint = 1'h0; // @[decode.scala:422:7] wire io_deq_uop_fp_ctrl_vec = 1'h0; // @[decode.scala:422:7] wire io_deq_uop_prs1_busy = 1'h0; // @[decode.scala:422:7] wire io_deq_uop_prs2_busy = 1'h0; // @[decode.scala:422:7] wire io_deq_uop_prs3_busy = 1'h0; // @[decode.scala:422:7] wire io_deq_uop_ppred_busy = 1'h0; // @[decode.scala:422:7] wire io_deq_uop_xcpt_ma_if = 1'h0; // @[decode.scala:422:7] wire io_status_mbe = 1'h0; // @[decode.scala:422:7] wire io_status_sbe = 1'h0; // @[decode.scala:422:7] wire io_status_sd_rv32 = 1'h0; // @[decode.scala:422:7] wire io_status_ube = 1'h0; // @[decode.scala:422:7] wire io_status_upie = 1'h0; // @[decode.scala:422:7] wire io_status_hie = 1'h0; // @[decode.scala:422:7] wire io_status_uie = 1'h0; // @[decode.scala:422:7] wire io_csr_decode_vector_csr = 1'h0; // @[decode.scala:422:7] wire uop_iw_issued = 1'h0; // @[decode.scala:428:17] wire uop_iw_issued_partial_agen = 1'h0; // @[decode.scala:428:17] wire uop_iw_issued_partial_dgen = 1'h0; // @[decode.scala:428:17] wire uop_iw_p1_bypass_hint = 1'h0; // @[decode.scala:428:17] wire uop_iw_p2_bypass_hint = 1'h0; // @[decode.scala:428:17] wire uop_iw_p3_bypass_hint = 1'h0; // @[decode.scala:428:17] wire uop_fp_ctrl_vec = 1'h0; // @[decode.scala:428:17] wire uop_prs1_busy = 1'h0; // @[decode.scala:428:17] wire uop_prs2_busy = 1'h0; // @[decode.scala:428:17] wire uop_prs3_busy = 1'h0; // @[decode.scala:428:17] wire uop_ppred_busy = 1'h0; // @[decode.scala:428:17] wire uop_xcpt_ma_if = 1'h0; // @[decode.scala:428:17] wire cs_fp_vec = 1'h0; // @[decode.scala:447:16] wire _id_illegal_insn_T_7 = 1'h0; // @[decode.scala:464:19] wire _id_illegal_insn_T_8 = 1'h0; // @[decode.scala:464:16] wire [31:0] uop_inst = io_enq_uop_inst_0; // @[decode.scala:422:7, :428:17] wire [31:0] uop_debug_inst = io_enq_uop_debug_inst_0; // @[decode.scala:422:7, :428:17] wire uop_is_rvc = io_enq_uop_is_rvc_0; // @[decode.scala:422:7, :428:17] wire [39:0] uop_debug_pc = io_enq_uop_debug_pc_0; // @[decode.scala:422:7, :428:17] wire uop_is_sfb = io_enq_uop_is_sfb_0; // @[decode.scala:422:7, :428:17] wire [4:0] uop_ftq_idx = io_enq_uop_ftq_idx_0; // @[decode.scala:422:7, :428:17] wire uop_edge_inst = io_enq_uop_edge_inst_0; // @[decode.scala:422:7, :428:17] wire [5:0] uop_pc_lob = io_enq_uop_pc_lob_0; // @[decode.scala:422:7, :428:17] wire uop_taken = io_enq_uop_taken_0; // @[decode.scala:422:7, :428:17] wire uop_xcpt_pf_if = io_enq_uop_xcpt_pf_if_0; // @[decode.scala:422:7, :428:17] wire uop_xcpt_ae_if = io_enq_uop_xcpt_ae_if_0; // @[decode.scala:422:7, :428:17] wire uop_bp_debug_if = io_enq_uop_bp_debug_if_0; // @[decode.scala:422:7, :428:17] wire uop_bp_xcpt_if = io_enq_uop_bp_xcpt_if_0; // @[decode.scala:422:7, :428:17] wire [2:0] uop_debug_fsrc = io_enq_uop_debug_fsrc_0; // @[decode.scala:422:7, :428:17] wire uop_iq_type_0; // @[decode.scala:428:17] wire uop_iq_type_1; // @[decode.scala:428:17] wire uop_iq_type_2; // @[decode.scala:428:17] wire uop_iq_type_3; // @[decode.scala:428:17] wire uop_fu_code_0; // @[decode.scala:428:17] wire uop_fu_code_1; // @[decode.scala:428:17] wire uop_fu_code_2; // @[decode.scala:428:17] wire uop_fu_code_3; // @[decode.scala:428:17] wire uop_fu_code_4; // @[decode.scala:428:17] wire uop_fu_code_5; // @[decode.scala:428:17] wire uop_fu_code_6; // @[decode.scala:428:17] wire uop_fu_code_7; // @[decode.scala:428:17] wire uop_fu_code_8; // @[decode.scala:428:17] wire uop_fu_code_9; // @[decode.scala:428:17] wire [3:0] uop_br_type; // @[decode.scala:428:17] wire uop_is_fence; // @[decode.scala:428:17] wire uop_is_fencei; // @[decode.scala:428:17] wire uop_is_sfence; // @[decode.scala:428:17] wire uop_is_amo; // @[decode.scala:428:17] wire uop_is_eret; // @[decode.scala:428:17] wire uop_is_sys_pc2epc; // @[decode.scala:428:17] wire uop_is_rocc; // @[decode.scala:428:17] wire uop_is_mov; // @[decode.scala:428:17] wire uop_imm_rename; // @[decode.scala:428:17] wire [2:0] uop_imm_sel; // @[decode.scala:428:17] wire [4:0] uop_pimm; // @[decode.scala:428:17] wire [19:0] uop_imm_packed; // @[decode.scala:428:17] wire [1:0] uop_op1_sel; // @[decode.scala:428:17] wire [2:0] uop_op2_sel; // @[decode.scala:428:17] wire uop_fp_ctrl_ldst; // @[decode.scala:428:17] wire uop_fp_ctrl_wen; // @[decode.scala:428:17] wire uop_fp_ctrl_ren1; // @[decode.scala:428:17] wire uop_fp_ctrl_ren2; // @[decode.scala:428:17] wire uop_fp_ctrl_ren3; // @[decode.scala:428:17] wire uop_fp_ctrl_swap12; // @[decode.scala:428:17] wire uop_fp_ctrl_swap23; // @[decode.scala:428:17] wire [1:0] uop_fp_ctrl_typeTagIn; // @[decode.scala:428:17] wire [1:0] uop_fp_ctrl_typeTagOut; // @[decode.scala:428:17] wire uop_fp_ctrl_fromint; // @[decode.scala:428:17] wire uop_fp_ctrl_toint; // @[decode.scala:428:17] wire uop_fp_ctrl_fastpipe; // @[decode.scala:428:17] wire uop_fp_ctrl_fma; // @[decode.scala:428:17] wire uop_fp_ctrl_div; // @[decode.scala:428:17] wire uop_fp_ctrl_sqrt; // @[decode.scala:428:17] wire uop_fp_ctrl_wflags; // @[decode.scala:428:17] wire uop_exception; // @[decode.scala:428:17] wire [63:0] uop_exc_cause; // @[decode.scala:428:17] wire [4:0] uop_mem_cmd; // @[decode.scala:428:17] wire [1:0] uop_mem_size; // @[decode.scala:428:17] wire uop_mem_signed; // @[decode.scala:428:17] wire uop_uses_ldq; // @[decode.scala:428:17] wire uop_uses_stq; // @[decode.scala:428:17] wire uop_is_unique; // @[decode.scala:428:17] wire uop_flush_on_commit; // @[decode.scala:428:17] wire [2:0] uop_csr_cmd; // @[decode.scala:428:17] wire uop_ldst_is_rs1; // @[decode.scala:428:17] wire [5:0] uop_ldst; // @[decode.scala:428:17] wire [5:0] uop_lrs1; // @[decode.scala:428:17] wire [5:0] uop_lrs2; // @[decode.scala:428:17] wire [5:0] uop_lrs3; // @[decode.scala:428:17] wire [1:0] uop_dst_rtype; // @[decode.scala:428:17] wire [1:0] uop_lrs1_rtype; // @[decode.scala:428:17] wire [1:0] uop_lrs2_rtype; // @[decode.scala:428:17] wire uop_frs3_en; // @[decode.scala:428:17] wire uop_fcn_dw; // @[decode.scala:428:17] wire [4:0] uop_fcn_op; // @[decode.scala:428:17] wire uop_fp_val; // @[decode.scala:428:17] wire [2:0] uop_fp_rm; // @[decode.scala:428:17] wire [1:0] uop_fp_typ; // @[decode.scala:428:17] wire io_deq_uop_iq_type_0_0; // @[decode.scala:422:7] wire io_deq_uop_iq_type_1_0; // @[decode.scala:422:7] wire io_deq_uop_iq_type_2_0; // @[decode.scala:422:7] wire io_deq_uop_iq_type_3_0; // @[decode.scala:422:7] wire io_deq_uop_fu_code_0_0; // @[decode.scala:422:7] wire io_deq_uop_fu_code_1_0; // @[decode.scala:422:7] wire io_deq_uop_fu_code_2_0; // @[decode.scala:422:7] wire io_deq_uop_fu_code_3_0; // @[decode.scala:422:7] wire io_deq_uop_fu_code_4_0; // @[decode.scala:422:7] wire io_deq_uop_fu_code_5_0; // @[decode.scala:422:7] wire io_deq_uop_fu_code_6_0; // @[decode.scala:422:7] wire io_deq_uop_fu_code_7_0; // @[decode.scala:422:7] wire io_deq_uop_fu_code_8_0; // @[decode.scala:422:7] wire io_deq_uop_fu_code_9_0; // @[decode.scala:422:7] wire io_deq_uop_fp_ctrl_ldst_0; // @[decode.scala:422:7] wire io_deq_uop_fp_ctrl_wen_0; // @[decode.scala:422:7] wire io_deq_uop_fp_ctrl_ren1_0; // @[decode.scala:422:7] wire io_deq_uop_fp_ctrl_ren2_0; // @[decode.scala:422:7] wire io_deq_uop_fp_ctrl_ren3_0; // @[decode.scala:422:7] wire io_deq_uop_fp_ctrl_swap12_0; // @[decode.scala:422:7] wire io_deq_uop_fp_ctrl_swap23_0; // @[decode.scala:422:7] wire [1:0] io_deq_uop_fp_ctrl_typeTagIn_0; // @[decode.scala:422:7] wire [1:0] io_deq_uop_fp_ctrl_typeTagOut_0; // @[decode.scala:422:7] wire io_deq_uop_fp_ctrl_fromint_0; // @[decode.scala:422:7] wire io_deq_uop_fp_ctrl_toint_0; // @[decode.scala:422:7] wire io_deq_uop_fp_ctrl_fastpipe_0; // @[decode.scala:422:7] wire io_deq_uop_fp_ctrl_fma_0; // @[decode.scala:422:7] wire io_deq_uop_fp_ctrl_div_0; // @[decode.scala:422:7] wire io_deq_uop_fp_ctrl_sqrt_0; // @[decode.scala:422:7] wire io_deq_uop_fp_ctrl_wflags_0; // @[decode.scala:422:7] wire [31:0] io_deq_uop_inst_0; // @[decode.scala:422:7] wire [31:0] io_deq_uop_debug_inst_0; // @[decode.scala:422:7] wire io_deq_uop_is_rvc_0; // @[decode.scala:422:7] wire [39:0] io_deq_uop_debug_pc_0; // @[decode.scala:422:7] wire [3:0] io_deq_uop_br_type_0; // @[decode.scala:422:7] wire io_deq_uop_is_sfb_0; // @[decode.scala:422:7] wire io_deq_uop_is_fence_0; // @[decode.scala:422:7] wire io_deq_uop_is_fencei_0; // @[decode.scala:422:7] wire io_deq_uop_is_sfence_0; // @[decode.scala:422:7] wire io_deq_uop_is_amo_0; // @[decode.scala:422:7] wire io_deq_uop_is_eret_0; // @[decode.scala:422:7] wire io_deq_uop_is_sys_pc2epc_0; // @[decode.scala:422:7] wire io_deq_uop_is_rocc_0; // @[decode.scala:422:7] wire io_deq_uop_is_mov_0; // @[decode.scala:422:7] wire [4:0] io_deq_uop_ftq_idx_0; // @[decode.scala:422:7] wire io_deq_uop_edge_inst_0; // @[decode.scala:422:7] wire [5:0] io_deq_uop_pc_lob_0; // @[decode.scala:422:7] wire io_deq_uop_taken_0; // @[decode.scala:422:7] wire io_deq_uop_imm_rename_0; // @[decode.scala:422:7] wire [2:0] io_deq_uop_imm_sel_0; // @[decode.scala:422:7] wire [4:0] io_deq_uop_pimm_0; // @[decode.scala:422:7] wire [19:0] io_deq_uop_imm_packed_0; // @[decode.scala:422:7] wire [1:0] io_deq_uop_op1_sel_0; // @[decode.scala:422:7] wire [2:0] io_deq_uop_op2_sel_0; // @[decode.scala:422:7] wire io_deq_uop_exception_0; // @[decode.scala:422:7] wire [63:0] io_deq_uop_exc_cause_0; // @[decode.scala:422:7] wire [4:0] io_deq_uop_mem_cmd_0; // @[decode.scala:422:7] wire [1:0] io_deq_uop_mem_size_0; // @[decode.scala:422:7] wire io_deq_uop_mem_signed_0; // @[decode.scala:422:7] wire io_deq_uop_uses_ldq_0; // @[decode.scala:422:7] wire io_deq_uop_uses_stq_0; // @[decode.scala:422:7] wire io_deq_uop_is_unique_0; // @[decode.scala:422:7] wire io_deq_uop_flush_on_commit_0; // @[decode.scala:422:7] wire [2:0] io_deq_uop_csr_cmd_0; // @[decode.scala:422:7] wire io_deq_uop_ldst_is_rs1_0; // @[decode.scala:422:7] wire [5:0] io_deq_uop_ldst_0; // @[decode.scala:422:7] wire [5:0] io_deq_uop_lrs1_0; // @[decode.scala:422:7] wire [5:0] io_deq_uop_lrs2_0; // @[decode.scala:422:7] wire [5:0] io_deq_uop_lrs3_0; // @[decode.scala:422:7] wire [1:0] io_deq_uop_dst_rtype_0; // @[decode.scala:422:7] wire [1:0] io_deq_uop_lrs1_rtype_0; // @[decode.scala:422:7] wire [1:0] io_deq_uop_lrs2_rtype_0; // @[decode.scala:422:7] wire io_deq_uop_frs3_en_0; // @[decode.scala:422:7] wire io_deq_uop_fcn_dw_0; // @[decode.scala:422:7] wire [4:0] io_deq_uop_fcn_op_0; // @[decode.scala:422:7] wire io_deq_uop_fp_val_0; // @[decode.scala:422:7] wire [2:0] io_deq_uop_fp_rm_0; // @[decode.scala:422:7] wire [1:0] io_deq_uop_fp_typ_0; // @[decode.scala:422:7] wire io_deq_uop_xcpt_pf_if_0; // @[decode.scala:422:7] wire io_deq_uop_xcpt_ae_if_0; // @[decode.scala:422:7] wire io_deq_uop_bp_debug_if_0; // @[decode.scala:422:7] wire io_deq_uop_bp_xcpt_if_0; // @[decode.scala:422:7] wire [2:0] io_deq_uop_debug_fsrc_0; // @[decode.scala:422:7] wire [31:0] io_csr_decode_inst_0; // @[decode.scala:422:7] assign io_deq_uop_inst_0 = uop_inst; // @[decode.scala:422:7, :428:17] assign io_csr_decode_inst_0 = uop_inst; // @[decode.scala:422:7, :428:17] wire [31:0] cs_decoder_decoded_plaInput = uop_inst; // @[pla.scala:77:22] wire [31:0] _uop_is_sys_pc2epc_T = uop_inst; // @[decode.scala:428:17, :529:29] wire [31:0] _uop_is_sys_pc2epc_T_2 = uop_inst; // @[decode.scala:428:17, :529:48] wire [31:0] _uop_is_eret_T = uop_inst; // @[decode.scala:428:17, :530:26] wire [31:0] _uop_is_eret_T_2 = uop_inst; // @[decode.scala:428:17, :530:44] wire [31:0] _uop_is_eret_T_5 = uop_inst; // @[decode.scala:428:17, :530:63] wire [31:0] _uop_is_eret_T_8 = uop_inst; // @[decode.scala:428:17, :530:80] wire [31:0] _uop_is_eret_T_11 = uop_inst; // @[decode.scala:428:17, :530:97] assign io_deq_uop_debug_inst_0 = uop_debug_inst; // @[decode.scala:422:7, :428:17] assign io_deq_uop_is_rvc_0 = uop_is_rvc; // @[decode.scala:422:7, :428:17] assign io_deq_uop_debug_pc_0 = uop_debug_pc; // @[decode.scala:422:7, :428:17] wire _uop_iq_type_0_T_2; // @[decode.scala:489:98] assign io_deq_uop_iq_type_0_0 = uop_iq_type_0; // @[decode.scala:422:7, :428:17] wire _uop_iq_type_1_T_6; // @[decode.scala:487:98] assign io_deq_uop_iq_type_1_0 = uop_iq_type_1; // @[decode.scala:422:7, :428:17] wire _uop_iq_type_2_T; // @[decode.scala:488:84] assign io_deq_uop_iq_type_2_0 = uop_iq_type_2; // @[decode.scala:422:7, :428:17] wire _uop_iq_type_3_T_4; // @[decode.scala:490:98] assign io_deq_uop_iq_type_3_0 = uop_iq_type_3; // @[decode.scala:422:7, :428:17] assign io_deq_uop_fu_code_0_0 = uop_fu_code_0; // @[decode.scala:422:7, :428:17] assign io_deq_uop_fu_code_1_0 = uop_fu_code_1; // @[decode.scala:422:7, :428:17] assign io_deq_uop_fu_code_2_0 = uop_fu_code_2; // @[decode.scala:422:7, :428:17] assign io_deq_uop_fu_code_3_0 = uop_fu_code_3; // @[decode.scala:422:7, :428:17] assign io_deq_uop_fu_code_4_0 = uop_fu_code_4; // @[decode.scala:422:7, :428:17] assign io_deq_uop_fu_code_5_0 = uop_fu_code_5; // @[decode.scala:422:7, :428:17] assign io_deq_uop_fu_code_6_0 = uop_fu_code_6; // @[decode.scala:422:7, :428:17] assign io_deq_uop_fu_code_7_0 = uop_fu_code_7; // @[decode.scala:422:7, :428:17] assign io_deq_uop_fu_code_8_0 = uop_fu_code_8; // @[decode.scala:422:7, :428:17] assign io_deq_uop_fu_code_9_0 = uop_fu_code_9; // @[decode.scala:422:7, :428:17] wire [3:0] _uop_br_type_T_30; // @[decode.scala:604:62] assign io_deq_uop_br_type_0 = uop_br_type; // @[decode.scala:422:7, :428:17] assign io_deq_uop_is_sfb_0 = uop_is_sfb; // @[decode.scala:422:7, :428:17] wire _uop_is_fence_T_1; // @[decode.scala:526:26] assign io_deq_uop_is_fence_0 = uop_is_fence; // @[decode.scala:422:7, :428:17] wire _uop_is_fencei_T_1; // @[decode.scala:527:26] assign io_deq_uop_is_fencei_0 = uop_is_fencei; // @[decode.scala:422:7, :428:17] wire _uop_is_sfence_T_1; // @[decode.scala:528:26] assign io_deq_uop_is_sfence_0 = uop_is_sfence; // @[decode.scala:422:7, :428:17] wire cs_is_amo; // @[decode.scala:447:16] assign io_deq_uop_is_amo_0 = uop_is_amo; // @[decode.scala:422:7, :428:17] wire _uop_is_eret_T_13; // @[decode.scala:530:89] assign io_deq_uop_is_eret_0 = uop_is_eret; // @[decode.scala:422:7, :428:17] wire _uop_is_sys_pc2epc_T_4; // @[decode.scala:529:40] assign io_deq_uop_is_sys_pc2epc_0 = uop_is_sys_pc2epc; // @[decode.scala:422:7, :428:17] wire _uop_is_rocc_T_18; // @[decode.scala:532:81] assign io_deq_uop_is_rocc_0 = uop_is_rocc; // @[decode.scala:422:7, :428:17] wire _id_illegal_insn_T_4 = uop_is_rocc; // @[decode.scala:428:17, :463:18] wire _uop_is_mov_T_3; // @[decode.scala:485:34] assign io_deq_uop_is_mov_0 = uop_is_mov; // @[decode.scala:422:7, :428:17] assign io_deq_uop_ftq_idx_0 = uop_ftq_idx; // @[decode.scala:422:7, :428:17] assign io_deq_uop_edge_inst_0 = uop_edge_inst; // @[decode.scala:422:7, :428:17] assign io_deq_uop_pc_lob_0 = uop_pc_lob; // @[decode.scala:422:7, :428:17] assign io_deq_uop_taken_0 = uop_taken; // @[decode.scala:422:7, :428:17] assign io_deq_uop_imm_rename_0 = uop_imm_rename; // @[decode.scala:422:7, :428:17] assign io_deq_uop_imm_sel_0 = uop_imm_sel; // @[decode.scala:422:7, :428:17] assign io_deq_uop_pimm_0 = uop_pimm; // @[decode.scala:422:7, :428:17] wire [19:0] imm_packed; // @[decode.scala:541:23] assign io_deq_uop_imm_packed_0 = uop_imm_packed; // @[decode.scala:422:7, :428:17] assign io_deq_uop_op1_sel_0 = uop_op1_sel; // @[decode.scala:422:7, :428:17] assign io_deq_uop_op2_sel_0 = uop_op2_sel; // @[decode.scala:422:7, :428:17] wire cs_fp_ldst; // @[decode.scala:447:16] assign io_deq_uop_fp_ctrl_ldst_0 = uop_fp_ctrl_ldst; // @[decode.scala:422:7, :428:17] wire cs_fp_wen; // @[decode.scala:447:16] assign io_deq_uop_fp_ctrl_wen_0 = uop_fp_ctrl_wen; // @[decode.scala:422:7, :428:17] wire cs_fp_ren1; // @[decode.scala:447:16] assign io_deq_uop_fp_ctrl_ren1_0 = uop_fp_ctrl_ren1; // @[decode.scala:422:7, :428:17] wire cs_fp_ren2; // @[decode.scala:447:16] assign io_deq_uop_fp_ctrl_ren2_0 = uop_fp_ctrl_ren2; // @[decode.scala:422:7, :428:17] wire cs_fp_ren3; // @[decode.scala:447:16] assign io_deq_uop_fp_ctrl_ren3_0 = uop_fp_ctrl_ren3; // @[decode.scala:422:7, :428:17] wire cs_fp_swap12; // @[decode.scala:447:16] assign io_deq_uop_fp_ctrl_swap12_0 = uop_fp_ctrl_swap12; // @[decode.scala:422:7, :428:17] wire cs_fp_swap23; // @[decode.scala:447:16] assign io_deq_uop_fp_ctrl_swap23_0 = uop_fp_ctrl_swap23; // @[decode.scala:422:7, :428:17] wire [1:0] cs_fp_typeTagIn; // @[decode.scala:447:16] assign io_deq_uop_fp_ctrl_typeTagIn_0 = uop_fp_ctrl_typeTagIn; // @[decode.scala:422:7, :428:17] wire [1:0] cs_fp_typeTagOut; // @[decode.scala:447:16] assign io_deq_uop_fp_ctrl_typeTagOut_0 = uop_fp_ctrl_typeTagOut; // @[decode.scala:422:7, :428:17] wire cs_fp_fromint; // @[decode.scala:447:16] assign io_deq_uop_fp_ctrl_fromint_0 = uop_fp_ctrl_fromint; // @[decode.scala:422:7, :428:17] wire cs_fp_toint; // @[decode.scala:447:16] assign io_deq_uop_fp_ctrl_toint_0 = uop_fp_ctrl_toint; // @[decode.scala:422:7, :428:17] wire cs_fp_fastpipe; // @[decode.scala:447:16] assign io_deq_uop_fp_ctrl_fastpipe_0 = uop_fp_ctrl_fastpipe; // @[decode.scala:422:7, :428:17] wire cs_fp_fma; // @[decode.scala:447:16] assign io_deq_uop_fp_ctrl_fma_0 = uop_fp_ctrl_fma; // @[decode.scala:422:7, :428:17] wire cs_fp_div; // @[decode.scala:447:16] assign io_deq_uop_fp_ctrl_div_0 = uop_fp_ctrl_div; // @[decode.scala:422:7, :428:17] wire cs_fp_sqrt; // @[decode.scala:447:16] assign io_deq_uop_fp_ctrl_sqrt_0 = uop_fp_ctrl_sqrt; // @[decode.scala:422:7, :428:17] wire cs_fp_wflags; // @[decode.scala:447:16] assign io_deq_uop_fp_ctrl_wflags_0 = uop_fp_ctrl_wflags; // @[decode.scala:422:7, :428:17] wire xcpt_valid; // @[decode.scala:470:26] assign io_deq_uop_exception_0 = uop_exception; // @[decode.scala:422:7, :428:17] wire [63:0] xcpt_cause; // @[Mux.scala:50:70] assign io_deq_uop_exc_cause_0 = uop_exc_cause; // @[decode.scala:422:7, :428:17] wire [4:0] cs_mem_cmd; // @[decode.scala:447:16] assign io_deq_uop_mem_cmd_0 = uop_mem_cmd; // @[decode.scala:422:7, :428:17] wire [1:0] _uop_mem_size_T_7; // @[decode.scala:521:24] assign io_deq_uop_mem_size_0 = uop_mem_size; // @[decode.scala:422:7, :428:17] wire _uop_mem_signed_T_1; // @[decode.scala:522:21] assign io_deq_uop_mem_signed_0 = uop_mem_signed; // @[decode.scala:422:7, :428:17] wire cs_uses_ldq; // @[decode.scala:447:16] assign io_deq_uop_uses_ldq_0 = uop_uses_ldq; // @[decode.scala:422:7, :428:17] wire cs_uses_stq; // @[decode.scala:447:16] assign io_deq_uop_uses_stq_0 = uop_uses_stq; // @[decode.scala:422:7, :428:17] wire cs_inst_unique; // @[decode.scala:447:16] assign io_deq_uop_is_unique_0 = uop_is_unique; // @[decode.scala:422:7, :428:17] wire _uop_flush_on_commit_T_3; // @[decode.scala:533:45] assign io_deq_uop_flush_on_commit_0 = uop_flush_on_commit; // @[decode.scala:422:7, :428:17] assign io_deq_uop_csr_cmd_0 = uop_csr_cmd; // @[decode.scala:422:7, :428:17] assign io_deq_uop_ldst_is_rs1_0 = uop_ldst_is_rs1; // @[decode.scala:422:7, :428:17] assign io_deq_uop_ldst_0 = uop_ldst; // @[decode.scala:422:7, :428:17] assign io_deq_uop_lrs1_0 = uop_lrs1; // @[decode.scala:422:7, :428:17] assign io_deq_uop_lrs2_0 = uop_lrs2; // @[decode.scala:422:7, :428:17] assign io_deq_uop_lrs3_0 = uop_lrs3; // @[decode.scala:422:7, :428:17] wire [1:0] cs_dst_type; // @[decode.scala:447:16] assign io_deq_uop_dst_rtype_0 = uop_dst_rtype; // @[decode.scala:422:7, :428:17] assign io_deq_uop_lrs1_rtype_0 = uop_lrs1_rtype; // @[decode.scala:422:7, :428:17] assign io_deq_uop_lrs2_rtype_0 = uop_lrs2_rtype; // @[decode.scala:422:7, :428:17] wire cs_frs3_en; // @[decode.scala:447:16] assign io_deq_uop_frs3_en_0 = uop_frs3_en; // @[decode.scala:422:7, :428:17] wire cs_fcn_dw; // @[decode.scala:447:16] assign io_deq_uop_fcn_dw_0 = uop_fcn_dw; // @[decode.scala:422:7, :428:17] wire [4:0] cs_fcn_op; // @[decode.scala:447:16] assign io_deq_uop_fcn_op_0 = uop_fcn_op; // @[decode.scala:422:7, :428:17] wire cs_fp_val; // @[decode.scala:447:16] assign io_deq_uop_fp_val_0 = uop_fp_val; // @[decode.scala:422:7, :428:17] wire [2:0] _uop_fp_rm_T_3; // @[decode.scala:556:21] assign io_deq_uop_fp_rm_0 = uop_fp_rm; // @[decode.scala:422:7, :428:17] wire [1:0] _uop_fp_typ_T; // @[decode.scala:557:22] assign io_deq_uop_fp_typ_0 = uop_fp_typ; // @[decode.scala:422:7, :428:17] assign io_deq_uop_xcpt_pf_if_0 = uop_xcpt_pf_if; // @[decode.scala:422:7, :428:17] assign io_deq_uop_xcpt_ae_if_0 = uop_xcpt_ae_if; // @[decode.scala:422:7, :428:17] assign io_deq_uop_bp_debug_if_0 = uop_bp_debug_if; // @[decode.scala:422:7, :428:17] assign io_deq_uop_bp_xcpt_if_0 = uop_bp_xcpt_if; // @[decode.scala:422:7, :428:17] assign io_deq_uop_debug_fsrc_0 = uop_debug_fsrc; // @[decode.scala:422:7, :428:17] wire [4:0] LDST = uop_inst[11:7]; // @[decode.scala:428:17, :441:18] wire [4:0] _di24_20_T_3 = uop_inst[11:7]; // @[decode.scala:428:17, :441:18, :540:69] wire [4:0] LRS1 = uop_inst[19:15]; // @[decode.scala:428:17, :442:18] wire [4:0] LRS2 = uop_inst[24:20]; // @[decode.scala:428:17, :443:18] wire [4:0] _di24_20_T_4 = uop_inst[24:20]; // @[decode.scala:428:17, :443:18, :540:81] wire [4:0] LRS3 = uop_inst[31:27]; // @[decode.scala:428:17, :444:18] wire cs_decoder_0; // @[Decode.scala:50:77] wire cs_decoder_1; // @[Decode.scala:50:77] assign uop_fp_val = cs_fp_val; // @[decode.scala:428:17, :447:16] wire [9:0] cs_decoder_2; // @[Decode.scala:50:77] wire [1:0] cs_decoder_3; // @[Decode.scala:50:77] assign uop_dst_rtype = cs_dst_type; // @[decode.scala:428:17, :447:16] wire [1:0] cs_decoder_4; // @[Decode.scala:50:77] wire [1:0] cs_decoder_5; // @[Decode.scala:50:77] wire cs_decoder_6; // @[Decode.scala:50:77] assign uop_frs3_en = cs_frs3_en; // @[decode.scala:428:17, :447:16] wire [2:0] cs_decoder_7; // @[Decode.scala:50:77] wire cs_decoder_8; // @[Decode.scala:50:77] assign uop_uses_ldq = cs_uses_ldq; // @[decode.scala:428:17, :447:16] wire cs_decoder_9; // @[Decode.scala:50:77] assign uop_uses_stq = cs_uses_stq; // @[decode.scala:428:17, :447:16] wire cs_decoder_10; // @[Decode.scala:50:77] assign uop_is_amo = cs_is_amo; // @[decode.scala:428:17, :447:16] wire [4:0] cs_decoder_11; // @[Decode.scala:50:77] assign uop_mem_cmd = cs_mem_cmd; // @[decode.scala:428:17, :447:16] wire cs_decoder_12; // @[Decode.scala:50:77] assign uop_is_unique = cs_inst_unique; // @[decode.scala:428:17, :447:16] wire cs_decoder_13; // @[Decode.scala:50:77] wire [2:0] cs_decoder_14; // @[Decode.scala:50:77] wire cs_decoder_15; // @[Decode.scala:50:77] assign uop_fcn_dw = cs_fcn_dw; // @[decode.scala:428:17, :447:16] wire [4:0] cs_decoder_16; // @[Decode.scala:50:77] assign uop_fcn_op = cs_fcn_op; // @[decode.scala:428:17, :447:16] wire cs_decoder_17; // @[Decode.scala:50:77] assign uop_fp_ctrl_ldst = cs_fp_ldst; // @[decode.scala:428:17, :447:16] wire cs_decoder_18; // @[Decode.scala:50:77] assign uop_fp_ctrl_wen = cs_fp_wen; // @[decode.scala:428:17, :447:16] wire cs_decoder_19; // @[Decode.scala:50:77] assign uop_fp_ctrl_ren1 = cs_fp_ren1; // @[decode.scala:428:17, :447:16] wire cs_decoder_20; // @[Decode.scala:50:77] assign uop_fp_ctrl_ren2 = cs_fp_ren2; // @[decode.scala:428:17, :447:16] wire cs_decoder_21; // @[Decode.scala:50:77] assign uop_fp_ctrl_ren3 = cs_fp_ren3; // @[decode.scala:428:17, :447:16] wire cs_decoder_22; // @[Decode.scala:50:77] assign uop_fp_ctrl_swap12 = cs_fp_swap12; // @[decode.scala:428:17, :447:16] wire cs_decoder_23; // @[Decode.scala:50:77] assign uop_fp_ctrl_swap23 = cs_fp_swap23; // @[decode.scala:428:17, :447:16] assign uop_fp_ctrl_typeTagIn = cs_fp_typeTagIn; // @[decode.scala:428:17, :447:16] assign uop_fp_ctrl_typeTagOut = cs_fp_typeTagOut; // @[decode.scala:428:17, :447:16] wire cs_decoder_26; // @[Decode.scala:50:77] assign uop_fp_ctrl_fromint = cs_fp_fromint; // @[decode.scala:428:17, :447:16] wire cs_decoder_27; // @[Decode.scala:50:77] assign uop_fp_ctrl_toint = cs_fp_toint; // @[decode.scala:428:17, :447:16] wire cs_decoder_28; // @[Decode.scala:50:77] assign uop_fp_ctrl_fastpipe = cs_fp_fastpipe; // @[decode.scala:428:17, :447:16] wire cs_decoder_29; // @[Decode.scala:50:77] assign uop_fp_ctrl_fma = cs_fp_fma; // @[decode.scala:428:17, :447:16] wire cs_decoder_30; // @[Decode.scala:50:77] assign uop_fp_ctrl_div = cs_fp_div; // @[decode.scala:428:17, :447:16] wire cs_decoder_31; // @[Decode.scala:50:77] assign uop_fp_ctrl_sqrt = cs_fp_sqrt; // @[decode.scala:428:17, :447:16] wire cs_decoder_32; // @[Decode.scala:50:77] assign uop_fp_ctrl_wflags = cs_fp_wflags; // @[decode.scala:428:17, :447:16] wire cs_legal; // @[decode.scala:447:16] wire [9:0] cs_fu_code; // @[decode.scala:447:16] wire [1:0] cs_rs1_type; // @[decode.scala:447:16] wire [1:0] cs_rs2_type; // @[decode.scala:447:16] wire [2:0] cs_imm_sel; // @[decode.scala:447:16] wire cs_flush_on_commit; // @[decode.scala:447:16] wire [2:0] cs_csr_cmd; // @[decode.scala:447:16] wire [31:0] cs_decoder_decoded_invInputs = ~cs_decoder_decoded_plaInput; // @[pla.scala:77:22, :78:21] wire [56:0] cs_decoder_decoded_invMatrixOutputs; // @[pla.scala:120:37] wire [56:0] cs_decoder_decoded; // @[pla.scala:81:23] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_1 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_2 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_3 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_4 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_5 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_6 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_7 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_8 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_9 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_10 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_11 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_12 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_13 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_14 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_15 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_16 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_17 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_18 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_19 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_20 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_21 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_22 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_23 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_24 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_25 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_26 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_27 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_28 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_29 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_30 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_31 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_32 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_33 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_34 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_35 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_36 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_37 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_38 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_39 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_40 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_41 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_42 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_43 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_44 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_45 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_46 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_47 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_48 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_49 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_50 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_51 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_52 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_53 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_54 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_55 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_56 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_57 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_58 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_59 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_60 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_61 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_62 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_63 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_64 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_65 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_66 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_67 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_68 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_69 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_70 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_71 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_72 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_73 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_74 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_75 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_76 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_77 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_78 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_79 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_80 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_81 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_82 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_83 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_84 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_85 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_86 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_87 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_88 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_89 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_92 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_93 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_94 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_95 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_96 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_97 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_98 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_99 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_100 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_101 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_102 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_103 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_104 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_105 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_106 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_107 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_108 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_109 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_110 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_111 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_112 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_113 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_114 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_115 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_116 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_117 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_118 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_119 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_120 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_121 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_122 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_123 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_124 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_125 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_126 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_127 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_128 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_129 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_130 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_131 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_132 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_133 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_134 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_135 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_136 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_137 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_138 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_139 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_140 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_141 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_142 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_143 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_144 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_145 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_146 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_147 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_148 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_149 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_150 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_151 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_154 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_155 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_156 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_157 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_158 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_159 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_160 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_161 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_162 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_163 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_164 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_165 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_166 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_167 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_168 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_1 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_2 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_3 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_4 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_5 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_6 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_7 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_8 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_9 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_10 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_11 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_12 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_13 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_14 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_15 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_17 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_18 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_19 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_20 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_21 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_22 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_23 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_24 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_25 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_26 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_27 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_28 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_30 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_31 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_32 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_33 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_34 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_35 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_36 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_37 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_38 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_39 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_40 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_41 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_42 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_43 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_44 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_45 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_46 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_47 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_48 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_49 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_50 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_51 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_52 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_53 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_54 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_55 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_56 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_57 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_58 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_59 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_60 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_61 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_62 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_63 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_64 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_65 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_66 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_67 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_68 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_69 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_70 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_71 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_72 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_73 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_74 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_75 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_76 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_77 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_78 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_79 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_80 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_81 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_82 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_83 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_84 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_85 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_86 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_89 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_92 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_93 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_94 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_95 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_96 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_97 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_98 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_99 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_100 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_101 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_102 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_103 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_104 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_105 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_106 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_107 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_108 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_109 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_110 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_111 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_112 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_113 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_114 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_115 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_116 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_117 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_118 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_119 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_120 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_121 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_122 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_123 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_124 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_125 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_126 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_127 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_128 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_129 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_130 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_131 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_132 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_133 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_134 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_135 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_136 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_137 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_138 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_139 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_140 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_141 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_142 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_143 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_144 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_145 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_146 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_147 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_148 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_149 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_150 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_151 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_154 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_155 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_156 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_157 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_158 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_159 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_160 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_161 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_162 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_163 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_164 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_165 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_166 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_167 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_168 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_1 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_2 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_3 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_6 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_7 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_9 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_10 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_11 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_12 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_13 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_14 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_15 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_21 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_22 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_23 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_24 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_25 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_30 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_31 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_32 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_33 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_34 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_35 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_36 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_41 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_42 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_46 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_47 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_48 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_49 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_50 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_51 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_52 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_53 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_54 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_55 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_56 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_57 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_58 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_59 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_60 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_61 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_62 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_63 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_64 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_65 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_66 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_67 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_68 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_70 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_71 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_72 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_73 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_74 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_75 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_76 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_77 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_78 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_79 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_81 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_82 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_83 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_84 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_89 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_92 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_93 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_94 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_95 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_96 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_98 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_99 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_100 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_101 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_103 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_104 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_105 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_106 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_107 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_108 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_109 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_110 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_111 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_112 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_113 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_114 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_115 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_117 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_118 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_119 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_120 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_121 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_122 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_123 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_124 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_125 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_126 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_127 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_128 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_129 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_130 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_131 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_132 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_133 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_134 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_135 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_136 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_137 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_138 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_139 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_140 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_141 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_142 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_143 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_144 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_145 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_146 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_147 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_148 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_149 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_150 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_151 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_154 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_156 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_157 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_158 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_159 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_160 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_161 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_162 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_163 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_164 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_165 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_166 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_167 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_168 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_1 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_2 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_3 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_6 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_8 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_9 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_10 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_12 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_14 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_21 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_22 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_23 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_24 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_25 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_26 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_27 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_30 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_31 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_32 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_35 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_36 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_37 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_38 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_39 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_40 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_41 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_42 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_43 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_44 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_46 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_47 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_48 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_49 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_50 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_51 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_52 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_53 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_54 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_55 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_56 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_57 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_60 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_61 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_62 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_63 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_64 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_65 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_66 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_67 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_70 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_71 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_72 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_73 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_78 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_82 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_83 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_84 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_89 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_92 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_93 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_94 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_95 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_96 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_98 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_99 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_100 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_101 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_105 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_106 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_107 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_108 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_109 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_110 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_111 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_112 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_113 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_114 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_117 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_118 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_119 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_120 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_121 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_126 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_127 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_128 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_129 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_130 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_131 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_132 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_133 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_134 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_135 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_136 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_137 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_138 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_139 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_142 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_144 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_147 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_149 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_151 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_154 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_156 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_157 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_158 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_159 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_160 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_161 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_162 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_163 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_164 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_165 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_166 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_167 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_168 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_1 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_2 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_4 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_5 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_6 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_7 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_17 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_18 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_19 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_20 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_20 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_21 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_22 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_31 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_33 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_38 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_39 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_40 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_41 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_49 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_51 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_61 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_65 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_69 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_69 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_77 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_78 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_95 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_97 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_98 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_99 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_100 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_104 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_105 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_106 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_107 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_108 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_109 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_112 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_118 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_119 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_120 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_122 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_128 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_129 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_130 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_131 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_132 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_133 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_136 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_137 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_138 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_140 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_141 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_141 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_143 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_143 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_145 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_148 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_150 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_155 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_156 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_157 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_158 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_159 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_160 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_161 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_162 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_163 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_164 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_165 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_166 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_167 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_1 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_2 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_3 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_4 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_5 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_6 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_7 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_8 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_8 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_9 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_11 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_11 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_13 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_13 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_14 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_30 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_29 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_32 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_31 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_37 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_37 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_38 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_37 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_38 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_39 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_42 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_41 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_42 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_43 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_44 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_45 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_47 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_48 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_49 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_50 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_51 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_52 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_56 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_57 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_58 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_57 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_59 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_60 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_63 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_64 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_67 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_68 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_69 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_70 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_73 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_74 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_75 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_74 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_76 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_77 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_78 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_79 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_80 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_81 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_82 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_83 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_94 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_99 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_102 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_103 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_106 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_107 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_108 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_109 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_110 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_111 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_114 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_113 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_114 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_115 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_116 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_117 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_118 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_121 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_120 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_123 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_124 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_123 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_124 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_125 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_130 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_131 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_132 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_133 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_136 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_139 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_140 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_139 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_142 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_141 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_144 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_145 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_144 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_147 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_146 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_149 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_148 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_152 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_3 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_4 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_7 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_7 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_10 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_12 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_12 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_13 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_23 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_20 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_12 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_8 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_37 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_43 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_45 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_65 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_67 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_71 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_77 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_52 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_45 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_87 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_68 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_48 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_55 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_51 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_88 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_91 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_100 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_101 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_95 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_104 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_112 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_108 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_118 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_149 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_130 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_108 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_146 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_153 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_155 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_156 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_158 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo = {cs_decoder_decoded_andMatrixOutputs_lo_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi = {cs_decoder_decoded_andMatrixOutputs_hi_hi, cs_decoder_decoded_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53] wire [6:0] _cs_decoder_decoded_andMatrixOutputs_T = {cs_decoder_decoded_andMatrixOutputs_hi, cs_decoder_decoded_andMatrixOutputs_lo}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_81_2 = &_cs_decoder_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_1 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_2 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_3 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_4 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_5 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_9 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_17 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_18 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_19 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_20 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_24 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_25 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_26 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_27 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_28 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_37 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_38 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_39 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_40 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_43 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_44 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_45 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_56 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_64 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_69 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_80 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_85 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_86 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_97 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_102 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_116 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_155 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_1}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_1 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_lo_lo}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_1}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_1}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_1 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_hi_lo_1}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_1 = {cs_decoder_decoded_andMatrixOutputs_hi_1, cs_decoder_decoded_andMatrixOutputs_lo_1}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_85_2 = &_cs_decoder_decoded_andMatrixOutputs_T_1; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_1 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_2 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_1 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_5 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_3 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_8 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_10 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_8 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_9 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_17 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_18 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_19 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_15 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_10 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_7 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_23 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_19 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_25 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_21 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_27 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_48 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_49 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_50 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_59 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_54 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_56 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_58 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_73 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_64 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_49 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_42 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_80 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_55 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_45 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_53 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_48 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_89 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_90 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_96 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_97 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_98 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_86 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_87 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_88 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_89 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_90 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_91 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_105 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_96 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_97 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_98 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_112 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_100 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_114 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_115 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_103 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_110 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_111 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_112 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_113 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_119 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_133 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_121 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_135 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_136 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_124 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_138 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_126 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_140 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_128 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_142 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_117 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_104 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_147 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_140 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_154 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_142 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_143 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_157 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_145 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_1}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_2}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_2 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_2}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_2}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_2 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_hi_lo_2}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_2 = {cs_decoder_decoded_andMatrixOutputs_hi_2, cs_decoder_decoded_andMatrixOutputs_lo_2}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_10_2 = &_cs_decoder_decoded_andMatrixOutputs_T_2; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_3 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_2 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_6 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_4 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_6 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_6 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_7 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_13 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_14 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_11 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_9 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_6 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_34 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_29 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_30 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_22 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_23 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_34 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_24 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_25 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_28 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_58 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_46 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_41 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_43 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_57 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_63 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_51 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_47 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_36 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_67 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_52 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_39 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_50 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_42 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_74 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_75 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_76 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_77 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_78 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_79 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_82 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_83 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_84 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_85 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_73 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_74 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_75 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_76 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_92 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_93 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_98 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_100 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_106 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_120 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_108 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_122 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_125 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_129 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_114 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_94 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_132 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_133 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_134 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_127 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_141 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_129 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_130 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_144 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_132 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_3}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_3 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_3}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_3}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_3}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_3 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_hi_lo_3}; // @[pla.scala:98:53] wire [6:0] _cs_decoder_decoded_andMatrixOutputs_T_3 = {cs_decoder_decoded_andMatrixOutputs_hi_3, cs_decoder_decoded_andMatrixOutputs_lo_3}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_26_2 = &_cs_decoder_decoded_andMatrixOutputs_T_3; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_4 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_5 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_8 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_19 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_27 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_28 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_39 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_40 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_44 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_45 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_80 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_85 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_86 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_97 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_102 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_116 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_155 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_4 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_5 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_15 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_20 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_28 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_33 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_34 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_45 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_58 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_59 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_77 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_79 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_80 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_81 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_85 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_86 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_97 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_102 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_116 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_122 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_123 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_124 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_150 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_155 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_4}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_4 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_4}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_4}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_4 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_4}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_4 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_4, cs_decoder_decoded_andMatrixOutputs_hi_lo_4}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_4 = {cs_decoder_decoded_andMatrixOutputs_hi_4, cs_decoder_decoded_andMatrixOutputs_lo_4}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_100_2 = &_cs_decoder_decoded_andMatrixOutputs_T_4; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_5}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_3}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_5 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_5}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_5 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_5}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_5 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_hi_lo_5}; // @[pla.scala:98:53] wire [9:0] _cs_decoder_decoded_andMatrixOutputs_T_5 = {cs_decoder_decoded_andMatrixOutputs_hi_5, cs_decoder_decoded_andMatrixOutputs_lo_5}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_88_2 = &_cs_decoder_decoded_andMatrixOutputs_T_5; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_6 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_7 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_8 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_10 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_11 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_12 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_13 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_14 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_15 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_21 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_22 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_23 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_29 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_30 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_31 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_32 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_33 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_34 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_36 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_41 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_42 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_46 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_47 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_48 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_49 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_50 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_51 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_52 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_53 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_54 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_55 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_57 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_58 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_59 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_60 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_61 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_62 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_63 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_65 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_66 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_67 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_68 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_70 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_71 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_72 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_73 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_74 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_75 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_76 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_77 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_78 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_79 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_81 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_82 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_83 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_84 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_88 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_89 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_91 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_92 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_93 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_94 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_95 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_96 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_98 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_99 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_100 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_101 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_103 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_104 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_105 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_106 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_107 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_108 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_109 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_110 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_111 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_112 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_113 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_114 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_115 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_117 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_118 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_119 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_120 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_121 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_122 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_123 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_124 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_125 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_126 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_127 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_128 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_129 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_130 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_131 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_132 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_133 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_134 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_135 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_136 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_137 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_138 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_139 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_140 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_141 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_142 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_143 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_144 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_145 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_146 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_147 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_148 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_149 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_150 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_151 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_153 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_154 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_156 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_157 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_158 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_159 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_160 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_161 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_162 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_163 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_164 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_165 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_166 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_167 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_168 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_4}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_6 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_lo_lo_4}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_6}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_6}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_6 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_hi_lo_6}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_6 = {cs_decoder_decoded_andMatrixOutputs_hi_6, cs_decoder_decoded_andMatrixOutputs_lo_6}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_62_2 = &_cs_decoder_decoded_andMatrixOutputs_T_6; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_2}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_7}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_7 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_lo_lo_5}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_7}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_7 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_7}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_7 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_hi_lo_7}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_7 = {cs_decoder_decoded_andMatrixOutputs_hi_7, cs_decoder_decoded_andMatrixOutputs_lo_7}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_77_2 = &_cs_decoder_decoded_andMatrixOutputs_T_7; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_8 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_8}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_8}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_8 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_8}; // @[pla.scala:90:45, :98:53] wire [5:0] _cs_decoder_decoded_andMatrixOutputs_T_8 = {cs_decoder_decoded_andMatrixOutputs_hi_8, cs_decoder_decoded_andMatrixOutputs_lo_8}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_29_2 = &_cs_decoder_decoded_andMatrixOutputs_T_8; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_9 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_10 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_11 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_12 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_13 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_14 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_15 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_23 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_24 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_26 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_26 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_27 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_29 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_29 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_35 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_35 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_43 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_43 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_44 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_45 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_46 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_47 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_48 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_50 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_52 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_53 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_54 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_55 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_59 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_60 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_62 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_63 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_64 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_66 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_68 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_70 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_71 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_72 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_74 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_75 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_76 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_76 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_79 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_80 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_81 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_82 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_83 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_84 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_85 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_88 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_88 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_91 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_91 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_92 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_93 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_94 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_96 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_101 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_103 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_104 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_110 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_111 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_113 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_115 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_115 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_116 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_117 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_125 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_125 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_126 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_127 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_134 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_135 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_146 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_146 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_148 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_153 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_153 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_154 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_6}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_9 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_9, cs_decoder_decoded_andMatrixOutputs_lo_lo_6}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_9}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_9}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_9 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_hi_lo_8}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_9 = {cs_decoder_decoded_andMatrixOutputs_hi_9, cs_decoder_decoded_andMatrixOutputs_lo_9}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_110_2 = &_cs_decoder_decoded_andMatrixOutputs_T_9; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_1 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_2 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_11 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_5 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_1 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_2 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_20 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_17 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_19 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_27 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_21 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_32 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_24 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_27 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_28 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_38 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_10 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_4 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_4 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_5 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_7 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_8 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_8 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_80 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_81 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_72 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_73 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_27 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_78 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_79 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_94 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_82 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_86 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_84 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_88 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_89 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_87 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_91 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_89 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_83 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_84 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_99 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_97 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_100 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_101 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_102 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_92 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_93 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_84 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_95 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_123 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_111 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_112 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_114 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_1 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_9 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_4 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_7 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_5 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_17 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_16 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_17 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_14 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_15 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_16 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_1 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_2 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_18 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_15 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_16 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_15 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_17 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_20 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_19 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_22 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_23 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_22 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_34 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_26 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_25 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_26 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_29 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_30 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_32 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_30 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_66 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_47 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_35 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_36 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_37 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_51 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_39 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_40 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_36 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_68 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_40 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_4 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_46 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_44 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_45 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_4 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_4 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_3 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_7 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_7 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_5 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_52 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_41 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_15 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_86 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_62 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_63 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_64 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_65 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_67 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_68 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_66 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_67 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_68 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_72 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_70 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_71 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_70 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_71 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_17 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_75 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_76 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_81 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_79 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_80 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_81 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_82 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_83 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_82 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_85 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_86 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_85 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_88 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_87 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_79 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_80 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_81 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_82 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_97 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_95 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_96 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_95 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_91 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_88 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_98 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_99 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_100 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_82 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_83 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_51 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_85 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_110 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_108 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_109 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_110 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_111 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_33 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_14 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_10 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_7 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_120 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_121 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_111 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_120 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_121 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_120 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_123 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_65 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_103 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_67 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_40 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_69 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_70 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_1 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_5 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_3 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_5 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_11 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_1 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_1 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_14 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_13 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_14 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_14 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_18 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_15 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_18 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_17 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_20 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_21 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_20 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_25 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_24 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_23 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_24 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_27 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_28 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_29 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_28 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_32 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_33 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_38 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_36 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_37 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_41 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_33 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_3 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_4 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_3 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_7 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_7 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_5 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_49 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_22 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_12 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_59 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_60 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_62 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_66 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_64 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_65 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_64 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_65 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_73 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_74 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_80 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_78 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_77 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_78 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_80 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_81 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_77 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_83 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_84 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_86 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_82 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_69 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_70 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_71 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_72 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_93 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_94 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_95 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_49 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_50 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_31 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_52 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_107 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_106 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_107 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_108 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_109 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_119 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_117 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_118 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_107 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_118 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_119 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_114 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_121 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_37 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_66 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_39 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_31 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_41 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_42 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_1 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_3 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_3 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_4 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_5 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_12 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_1 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_1 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_12 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_12 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_13 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_12 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_16 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_13 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_16 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_15 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_18 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_19 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_18 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_23 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_22 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_21 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_22 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_25 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_26 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_27 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_26 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_30 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_31 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_34 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_35 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_34 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_35 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_32 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_42 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_35 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_3 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_41 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_39 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_40 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_57 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_58 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_61 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_60 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_63 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_62 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_63 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_60 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_61 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_66 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_67 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_64 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_65 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_62 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_63 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_13 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_69 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_70 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_77 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_76 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_72 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_73 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_79 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_75 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_76 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_73 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_78 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_79 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_80 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_81 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_78 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_37 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_38 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_39 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_40 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_92 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_88 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_89 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_86 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_89 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_90 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_91 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_29 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_30 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_22 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_32 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_105 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_101 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_102 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_103 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_104 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_21 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_116 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_115 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_116 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_113 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_38 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_30 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_32 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_1 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_2 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_3 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_4 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_4 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_10 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_9 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_10 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_1 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_28 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_11 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_10 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_11 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_11 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_14 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_14 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_16 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_17 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_21 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_20 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_20 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_21 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_23 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_24 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_25 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_25 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_34 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_27 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_28 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_32 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_33 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_31 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_32 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_26 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_39 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_33 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_41 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_3 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_38 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_36 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_37 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_32 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_6 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_6 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_7 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_29_2 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_40 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_11 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_11 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_57 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_56 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_65 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_66 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_71 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_68 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_74 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_71 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_74 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_76 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_77 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_68 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_19 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_20 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_21 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_22 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_87 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_84 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_85 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_76 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_44 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_25 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_112 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_109 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_110 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_111 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_1 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_2 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_2 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_3 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_7 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_7 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_8 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_30 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_8 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_7 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_8 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_4 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_10 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_11 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_5 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_13 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_16 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_14 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_18 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_15 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_16 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_6 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_18 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_19 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_20 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_7 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_29 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_22 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_23 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_28 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_29 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_24 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_25 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_3 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_34 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_9 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_36 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_3 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_29 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_11 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_12 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_5 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_4 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_3 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_2 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_30_1 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_6 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_4 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_31 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_13 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_10 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_10 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_52 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_49 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_52 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_43 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_44 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_45 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_48 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_49 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_50 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_24 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_25 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_16 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_11 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_28 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_29 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_57 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_30 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_59 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_60 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_31 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_62 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_32 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_33 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_65 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_34 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_35 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_18 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_14 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_15 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_73 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_41 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_42 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_23 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_18 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_16 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_26 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_27 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_28 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_13 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_14 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_12 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_16 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_86 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_53 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_54 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_55 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_56 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_12 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_9 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_6 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_31_1 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_7 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_1}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_10 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_10 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_10, cs_decoder_decoded_andMatrixOutputs_lo_lo_7}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_7}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_10}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_9 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_10}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_10}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_10 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_10 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_hi_lo_9}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_10 = {cs_decoder_decoded_andMatrixOutputs_hi_10, cs_decoder_decoded_andMatrixOutputs_lo_10}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_61_2 = &_cs_decoder_decoded_andMatrixOutputs_T_10; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_1}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_8 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_1}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_1}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_2}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_11 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_1}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_11 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_11, cs_decoder_decoded_andMatrixOutputs_lo_lo_8}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_8}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_10 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_11}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_11 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_4, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_1}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_11 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_11, cs_decoder_decoded_andMatrixOutputs_hi_lo_10}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_11 = {cs_decoder_decoded_andMatrixOutputs_hi_11, cs_decoder_decoded_andMatrixOutputs_lo_11}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_166_2 = &_cs_decoder_decoded_andMatrixOutputs_T_11; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_2 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_2 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_4 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_3 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_8 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_8 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_9 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_29 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_9 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_9 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_10 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_9 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_12 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_13 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_12 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_15 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_17 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_19 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_19 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_17 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_22 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_23 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_24 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_21 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_31 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_26 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_27 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_29 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_30 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_30 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_31 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_8 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_37 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_27 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_39 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_3 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_35 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_30 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_31 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_13 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_4 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_3 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_2 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_29_1 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_6 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_4 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_30_2 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_21 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_11 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_10 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_55 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_53 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_50 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_51 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_56 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_53 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_54 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_55 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_46 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_47 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_58 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_59 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_51 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_26 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_11 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_105 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_106 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_2}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_9 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_2}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_5}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_12 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_3}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_12 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_12, cs_decoder_decoded_andMatrixOutputs_lo_lo_9}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_12}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_11 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_11}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_12}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_12}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_12 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_12 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_12, cs_decoder_decoded_andMatrixOutputs_hi_lo_11}; // @[pla.scala:98:53] wire [12:0] _cs_decoder_decoded_andMatrixOutputs_T_12 = {cs_decoder_decoded_andMatrixOutputs_hi_12, cs_decoder_decoded_andMatrixOutputs_lo_12}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_8_2 = &_cs_decoder_decoded_andMatrixOutputs_T_12; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_2}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_10 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_2}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_3}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_4}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_13 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_4, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_13 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_13, cs_decoder_decoded_andMatrixOutputs_lo_lo_10}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_10}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_12 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_3, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_13}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_13 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_3}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_13 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_13, cs_decoder_decoded_andMatrixOutputs_hi_lo_12}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_13 = {cs_decoder_decoded_andMatrixOutputs_hi_13, cs_decoder_decoded_andMatrixOutputs_lo_13}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_80_2 = &_cs_decoder_decoded_andMatrixOutputs_T_13; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_4}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_11 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_3}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_4}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_7}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_14 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_3}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_14 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_14, cs_decoder_decoded_andMatrixOutputs_lo_lo_11}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_14}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_13 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_13}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_14}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_14}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_14 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_4}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_14 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_hi_lo_13}; // @[pla.scala:98:53] wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_14 = {cs_decoder_decoded_andMatrixOutputs_hi_14, cs_decoder_decoded_andMatrixOutputs_lo_14}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_14_2 = &_cs_decoder_decoded_andMatrixOutputs_T_14; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_4}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_12 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_5}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_6}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_15 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_4}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_15 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_15, cs_decoder_decoded_andMatrixOutputs_lo_lo_12}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_12}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_15}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_14 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_15}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_15 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_5}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_15 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_hi_lo_14}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_15 = {cs_decoder_decoded_andMatrixOutputs_hi_15, cs_decoder_decoded_andMatrixOutputs_lo_15}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_56_2 = &_cs_decoder_decoded_andMatrixOutputs_T_15; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_16 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_17 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_18 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_18 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_19 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_18 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_19 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_20 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_21 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_22 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_25 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_24 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_25 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_29 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_27 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_34 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_33 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_46 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_53 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_58 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_61 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_62 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_69 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_67 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_75 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_87 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_88 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_86 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_90 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_91 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_89 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_90 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_91 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_92 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_93 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_95 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_96 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_97 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_98 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_102 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_103 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_104 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_105 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_126 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_127 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_128 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_129 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_134 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_135 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_152 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_153 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_151 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_153 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_154 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_155 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_156 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_157 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_158 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_159 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_160 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_161 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_162 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_163 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_164 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_165 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_16 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_29 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_22 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_87 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_88 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_79 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_90 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_91 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_82 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_83 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_84 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_85 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_152 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_153 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_144 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_16 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_28 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_17 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_87 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_87 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_66 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_90 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_91 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_69 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_70 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_71 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_72 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_152 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_153 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_131 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_16 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_26 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_13 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_87 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_85 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_53 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_90 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_90 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_56 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_57 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_58 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_59 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_152 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_152 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_118 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_16 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_21 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_11 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_86 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_78 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_50 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_90 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_88 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_53 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_56 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_152 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_150 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_115 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_15 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_16 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_10 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_84 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_65 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_48 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_89 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_81 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_51 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_54 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_151 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_143 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_113 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_6 = cs_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_7 = cs_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_3 = cs_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_48 = cs_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_44 = cs_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_17 = cs_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_54 = cs_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_50 = cs_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_20 = cs_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_116 = cs_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_112 = cs_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_60 = cs_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_6 = cs_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_6 = cs_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_2 = cs_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_46 = cs_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_41 = cs_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_9 = cs_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_51 = cs_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_47 = cs_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_12 = cs_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_113 = cs_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_107 = cs_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_36 = cs_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_6 = cs_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_5 = cs_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_2 = cs_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_43 = cs_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_35 = cs_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_7 = cs_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_49 = cs_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_44 = cs_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_10 = cs_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_111 = cs_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_103 = cs_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_27 = cs_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_5 = cs_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_2 = cs_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_2 = cs_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_40 = cs_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_16 = cs_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_7 = cs_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_46 = cs_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_38 = cs_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_10 = cs_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_106 = cs_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_93 = cs_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_24 = cs_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_4 = cs_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_1 = cs_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_2 = cs_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_34 = cs_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_8 = cs_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_6 = cs_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_43 = cs_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_19 = cs_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_9 = cs_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_102 = cs_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_59 = cs_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_20 = cs_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_1 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_1 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_2 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_40 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_62 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_47 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_18 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_9 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_9 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_106 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_107 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_108 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_109 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_114 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_115 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_129 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_138 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_103 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_109 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_110 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_135 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_122 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_125 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_124 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_125 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_128 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_127 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_1 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_2 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_37 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_49 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_45 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_5 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_5 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_5 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_93 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_94 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_95 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_96 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_101 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_102 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_130 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_131 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_104 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_103 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_106 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_105 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_34 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_23 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_11 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_122 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_149 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_150 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_151 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_152 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_116 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_123 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_118 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_119 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_126 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_121 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_1 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_2 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_34 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_46 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_42 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_5 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_5 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_5 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_8 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_8 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_8 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_64 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_90 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_91 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_92 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_93 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_98 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_99 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_116 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_117 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_118 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_101 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_102 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_98 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_104 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_25 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_19 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_11 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_119 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_136 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_137 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_138 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_139 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_112 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_117 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_114 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_115 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_120 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_117 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_1 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_2 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_28 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_44 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_39 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_4 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_5 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_5 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_8 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_8 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_8 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_54 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_88 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_89 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_90 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_91 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_96 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_97 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_103 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_104 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_105 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_96 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_97 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_94 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_99 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_117 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_123 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_124 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_125 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_126 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_102 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_113 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_104 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_105 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_116 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_107 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_6 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_13 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_5 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_4}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_7 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_16 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_5}; // @[pla.scala:98:53] wire [12:0] cs_decoder_decoded_andMatrixOutputs_lo_16 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_16, cs_decoder_decoded_andMatrixOutputs_lo_lo_13}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_6}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_4 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_6}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_9}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_6 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_7}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_15 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_4}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_16}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_6 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_15}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_16}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_16}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_9 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_16 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_6}; // @[pla.scala:98:53] wire [12:0] cs_decoder_decoded_andMatrixOutputs_hi_16 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_16, cs_decoder_decoded_andMatrixOutputs_hi_lo_15}; // @[pla.scala:98:53] wire [25:0] _cs_decoder_decoded_andMatrixOutputs_T_16 = {cs_decoder_decoded_andMatrixOutputs_hi_16, cs_decoder_decoded_andMatrixOutputs_lo_16}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_43_2 = &_cs_decoder_decoded_andMatrixOutputs_T_16; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_17}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_17}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_17 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_17}; // @[pla.scala:91:29, :98:53] wire [4:0] _cs_decoder_decoded_andMatrixOutputs_T_17 = {cs_decoder_decoded_andMatrixOutputs_hi_17, cs_decoder_decoded_andMatrixOutputs_lo_17}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_157_2 = &_cs_decoder_decoded_andMatrixOutputs_T_17; // @[pla.scala:98:{53,70}] wire _cs_decoder_decoded_orMatrixOutputs_T_17 = cs_decoder_decoded_andMatrixOutputs_157_2; // @[pla.scala:98:70, :114:36] wire _cs_decoder_decoded_orMatrixOutputs_T_63 = cs_decoder_decoded_andMatrixOutputs_157_2; // @[pla.scala:98:70, :114:36] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_18}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_18 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_17}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_18}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_18 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_18}; // @[pla.scala:91:29, :98:53] wire [5:0] _cs_decoder_decoded_andMatrixOutputs_T_18 = {cs_decoder_decoded_andMatrixOutputs_hi_18, cs_decoder_decoded_andMatrixOutputs_lo_18}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_123_2 = &_cs_decoder_decoded_andMatrixOutputs_T_18; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_18}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_19 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_16}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_19}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_19 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_19, cs_decoder_decoded_andMatrixOutputs_hi_lo_16}; // @[pla.scala:98:53] wire [6:0] _cs_decoder_decoded_andMatrixOutputs_T_19 = {cs_decoder_decoded_andMatrixOutputs_hi_19, cs_decoder_decoded_andMatrixOutputs_lo_19}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_102_2 = &_cs_decoder_decoded_andMatrixOutputs_T_19; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_20 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_17}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_20}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_20}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_20 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_20, cs_decoder_decoded_andMatrixOutputs_hi_lo_17}; // @[pla.scala:98:53] wire [6:0] _cs_decoder_decoded_andMatrixOutputs_T_20 = {cs_decoder_decoded_andMatrixOutputs_hi_20, cs_decoder_decoded_andMatrixOutputs_lo_20}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_140_2 = &_cs_decoder_decoded_andMatrixOutputs_T_20; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_7}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_20 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_10}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_21 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_20, cs_decoder_decoded_andMatrixOutputs_lo_lo_14}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_18 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_20}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_21}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_21 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_21}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_21 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_21, cs_decoder_decoded_andMatrixOutputs_hi_lo_18}; // @[pla.scala:98:53] wire [10:0] _cs_decoder_decoded_andMatrixOutputs_T_21 = {cs_decoder_decoded_andMatrixOutputs_hi_21, cs_decoder_decoded_andMatrixOutputs_lo_21}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_21_2 = &_cs_decoder_decoded_andMatrixOutputs_T_21; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_8}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_15 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_7}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_21 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_11}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_22 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_21, cs_decoder_decoded_andMatrixOutputs_lo_lo_15}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_19 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_21}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_22}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_22 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_22}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_22 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_22, cs_decoder_decoded_andMatrixOutputs_hi_lo_19}; // @[pla.scala:98:53] wire [11:0] _cs_decoder_decoded_andMatrixOutputs_T_22 = {cs_decoder_decoded_andMatrixOutputs_hi_22, cs_decoder_decoded_andMatrixOutputs_lo_22}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_145_2 = &_cs_decoder_decoded_andMatrixOutputs_T_22; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_9}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_16 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_8}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_22 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_12}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_23 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_22, cs_decoder_decoded_andMatrixOutputs_lo_lo_16}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_20 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_22}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_23}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_23 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_23}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_23 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_23, cs_decoder_decoded_andMatrixOutputs_hi_lo_20}; // @[pla.scala:98:53] wire [11:0] _cs_decoder_decoded_andMatrixOutputs_T_23 = {cs_decoder_decoded_andMatrixOutputs_hi_23, cs_decoder_decoded_andMatrixOutputs_lo_23}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_161_2 = &_cs_decoder_decoded_andMatrixOutputs_T_23; // @[pla.scala:98:{53,70}] wire _cs_decoder_decoded_orMatrixOutputs_T_16 = cs_decoder_decoded_andMatrixOutputs_161_2; // @[pla.scala:98:70, :114:36] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_17}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_24 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_23, cs_decoder_decoded_andMatrixOutputs_lo_lo_17}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_24}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_24}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_24 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_24, cs_decoder_decoded_andMatrixOutputs_hi_lo_21}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_24 = {cs_decoder_decoded_andMatrixOutputs_hi_24, cs_decoder_decoded_andMatrixOutputs_lo_24}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_79_2 = &_cs_decoder_decoded_andMatrixOutputs_T_24; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_13}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_22}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_25 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_24, cs_decoder_decoded_andMatrixOutputs_lo_lo_18}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_25}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_25}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_25 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_25}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_25 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_25, cs_decoder_decoded_andMatrixOutputs_hi_lo_22}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_25 = {cs_decoder_decoded_andMatrixOutputs_hi_25, cs_decoder_decoded_andMatrixOutputs_lo_25}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_33_2 = &_cs_decoder_decoded_andMatrixOutputs_T_25; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_14}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_26 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_25, cs_decoder_decoded_andMatrixOutputs_lo_lo_19}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_26}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_26 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_26}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_26 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_26, cs_decoder_decoded_andMatrixOutputs_hi_lo_23}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_26 = {cs_decoder_decoded_andMatrixOutputs_hi_26, cs_decoder_decoded_andMatrixOutputs_lo_26}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_112_2 = &_cs_decoder_decoded_andMatrixOutputs_T_26; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_11}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_24}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_26 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_20}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_27 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_26, cs_decoder_decoded_andMatrixOutputs_lo_lo_20}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_27}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_27}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_27 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_27}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_27 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_27, cs_decoder_decoded_andMatrixOutputs_hi_lo_24}; // @[pla.scala:98:53] wire [9:0] _cs_decoder_decoded_andMatrixOutputs_T_27 = {cs_decoder_decoded_andMatrixOutputs_hi_27, cs_decoder_decoded_andMatrixOutputs_lo_27}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_168_2 = &_cs_decoder_decoded_andMatrixOutputs_T_27; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_27}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_28 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_25}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_28}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_28}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_28 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_28, cs_decoder_decoded_andMatrixOutputs_hi_lo_25}; // @[pla.scala:98:53] wire [6:0] _cs_decoder_decoded_andMatrixOutputs_T_28 = {cs_decoder_decoded_andMatrixOutputs_hi_28, cs_decoder_decoded_andMatrixOutputs_lo_28}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_138_2 = &_cs_decoder_decoded_andMatrixOutputs_T_28; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_2 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_1}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_1}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_9 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_21 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_9, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_1}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_6 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_1}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_1}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_2}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_12 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_1}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_28 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_12, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_6}; // @[pla.scala:98:53] wire [13:0] cs_decoder_decoded_andMatrixOutputs_lo_29 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_28, cs_decoder_decoded_andMatrixOutputs_lo_lo_21}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_7}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_5 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_6}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_10}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_16}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_10 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_26 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_10, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_5}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_28}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_7 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_26}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_29}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_29}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_16 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_1}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_29 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_16, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_7}; // @[pla.scala:98:53] wire [13:0] cs_decoder_decoded_andMatrixOutputs_hi_29 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_29, cs_decoder_decoded_andMatrixOutputs_hi_lo_26}; // @[pla.scala:98:53] wire [27:0] _cs_decoder_decoded_andMatrixOutputs_T_29 = {cs_decoder_decoded_andMatrixOutputs_hi_29, cs_decoder_decoded_andMatrixOutputs_lo_29}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_47_2 = &_cs_decoder_decoded_andMatrixOutputs_T_29; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_29}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_3 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_30}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_1}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_2}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_10 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_1}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_22 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_10, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_2}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_2}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_7 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_2}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_2}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_13 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_2}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_29 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_13, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_7}; // @[pla.scala:98:53] wire [14:0] cs_decoder_decoded_andMatrixOutputs_lo_30 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_29, cs_decoder_decoded_andMatrixOutputs_lo_lo_22}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_3}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_7}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_6 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_10}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_13}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_11 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_1}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_27 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_11, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_6}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_29}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_8 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_30}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_30}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_17 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_2}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_30 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_17, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_8}; // @[pla.scala:98:53] wire [15:0] cs_decoder_decoded_andMatrixOutputs_hi_30 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_30, cs_decoder_decoded_andMatrixOutputs_hi_lo_27}; // @[pla.scala:98:53] wire [30:0] _cs_decoder_decoded_andMatrixOutputs_T_30 = {cs_decoder_decoded_andMatrixOutputs_hi_30, cs_decoder_decoded_andMatrixOutputs_lo_30}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_71_2 = &_cs_decoder_decoded_andMatrixOutputs_T_30; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_28 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_24 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_30 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_26 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_32 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_28 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_41 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_42 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_54 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_55 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_56 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_51 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_52 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_57 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_61 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_72 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_69 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_74 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_99 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_100 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_101 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_102 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_103 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_109 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_110 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_111 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_119 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_113 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_121 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_122 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_116 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_123 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_124 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_125 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_126 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_132 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_140 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_134 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_142 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_143 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_137 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_145 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_139 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_147 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_141 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_9}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_23 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_8}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_12}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_18}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_30 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_8}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_31 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_30, cs_decoder_decoded_andMatrixOutputs_lo_lo_23}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_28 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_28}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_31}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_31}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_31 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_18, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_9}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_31 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_31, cs_decoder_decoded_andMatrixOutputs_hi_lo_28}; // @[pla.scala:98:53] wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_31 = {cs_decoder_decoded_andMatrixOutputs_hi_31, cs_decoder_decoded_andMatrixOutputs_lo_31}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_105_2 = &_cs_decoder_decoded_andMatrixOutputs_T_31; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_9}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_24 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_7}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_12}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_15}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_31 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_9}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_32 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_31, cs_decoder_decoded_andMatrixOutputs_lo_lo_24}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_24}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_29 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_13, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_7}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_32}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_32}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_32 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_19, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_10}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_32 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_32, cs_decoder_decoded_andMatrixOutputs_hi_lo_29}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_32 = {cs_decoder_decoded_andMatrixOutputs_hi_32, cs_decoder_decoded_andMatrixOutputs_lo_32}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_52_2 = &_cs_decoder_decoded_andMatrixOutputs_T_32; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_10}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_25 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_8}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_13}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_16}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_32 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_16, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_10}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_33 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_32, cs_decoder_decoded_andMatrixOutputs_lo_lo_25}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_32}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_30 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_14, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_8}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_33}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_33 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_20, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_11}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_33 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_33, cs_decoder_decoded_andMatrixOutputs_hi_lo_30}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_33 = {cs_decoder_decoded_andMatrixOutputs_hi_33, cs_decoder_decoded_andMatrixOutputs_lo_33}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_86_2 = &_cs_decoder_decoded_andMatrixOutputs_T_33; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_4}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_11}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_26 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_14, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_4}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_14}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_17}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_33 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_17, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_11}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_34 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_33, cs_decoder_decoded_andMatrixOutputs_lo_lo_26}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_34, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_31 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_15, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_9}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_34, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_34, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_34}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_34 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_21, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_12}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_34 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_34, cs_decoder_decoded_andMatrixOutputs_hi_lo_31}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_34 = {cs_decoder_decoded_andMatrixOutputs_hi_34, cs_decoder_decoded_andMatrixOutputs_lo_34}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_0_2 = &_cs_decoder_decoded_andMatrixOutputs_T_34; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_27}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_34 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_34}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_35 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_34, cs_decoder_decoded_andMatrixOutputs_lo_lo_27}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_35}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_35 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_35}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_35 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_35, cs_decoder_decoded_andMatrixOutputs_hi_lo_32}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_35 = {cs_decoder_decoded_andMatrixOutputs_hi_35, cs_decoder_decoded_andMatrixOutputs_lo_35}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_76_2 = &_cs_decoder_decoded_andMatrixOutputs_T_35; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_28}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_35 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_35}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_36 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_35, cs_decoder_decoded_andMatrixOutputs_lo_lo_28}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_36}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_36}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_36 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_36, cs_decoder_decoded_andMatrixOutputs_hi_lo_33}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_36 = {cs_decoder_decoded_andMatrixOutputs_hi_36, cs_decoder_decoded_andMatrixOutputs_lo_36}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_160_2 = &_cs_decoder_decoded_andMatrixOutputs_T_36; // @[pla.scala:98:{53,70}] wire _cs_decoder_decoded_orMatrixOutputs_T_34 = cs_decoder_decoded_andMatrixOutputs_160_2; // @[pla.scala:98:70, :114:36] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_36 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_35 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_36 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_31 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_32 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_33 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_40 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_35 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_36 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_26 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_38 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_39 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_40 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_29 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_30 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_53 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_54 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_55 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_56 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_44 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_62 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_73 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_70 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_76 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_87 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_92 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_93 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_106 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_117 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_105 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_145 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_37 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_34}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_34 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_37}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_37 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_37}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_37 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_37, cs_decoder_decoded_andMatrixOutputs_hi_lo_34}; // @[pla.scala:98:53] wire [6:0] _cs_decoder_decoded_andMatrixOutputs_T_37 = {cs_decoder_decoded_andMatrixOutputs_hi_37, cs_decoder_decoded_andMatrixOutputs_lo_37}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_120_2 = &_cs_decoder_decoded_andMatrixOutputs_T_37; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_37 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_37}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_38 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_37, cs_decoder_decoded_andMatrixOutputs_lo_lo_29}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_35 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_38}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_38 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_38}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_38 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_38, cs_decoder_decoded_andMatrixOutputs_hi_lo_35}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_38 = {cs_decoder_decoded_andMatrixOutputs_hi_38, cs_decoder_decoded_andMatrixOutputs_lo_38}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_45_2 = &_cs_decoder_decoded_andMatrixOutputs_T_38; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_38 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_38}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_39 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_38, cs_decoder_decoded_andMatrixOutputs_lo_lo_30}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_39}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_39}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_39 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_39, cs_decoder_decoded_andMatrixOutputs_hi_lo_36}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_39 = {cs_decoder_decoded_andMatrixOutputs_hi_39, cs_decoder_decoded_andMatrixOutputs_lo_39}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_162_2 = &_cs_decoder_decoded_andMatrixOutputs_T_39; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_37}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_40 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_39, cs_decoder_decoded_andMatrixOutputs_lo_lo_31}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_37 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_40}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_40}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_40 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_40}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_40 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_40, cs_decoder_decoded_andMatrixOutputs_hi_lo_37}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_40 = {cs_decoder_decoded_andMatrixOutputs_hi_40, cs_decoder_decoded_andMatrixOutputs_lo_40}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_73_2 = &_cs_decoder_decoded_andMatrixOutputs_T_40; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_32}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_40}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_41 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_40, cs_decoder_decoded_andMatrixOutputs_lo_lo_32}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_38 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_41}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_41 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_41}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_41 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_41, cs_decoder_decoded_andMatrixOutputs_hi_lo_38}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_41 = {cs_decoder_decoded_andMatrixOutputs_hi_41, cs_decoder_decoded_andMatrixOutputs_lo_41}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_18_2 = &_cs_decoder_decoded_andMatrixOutputs_T_41; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_41 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_39}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_42 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_41, cs_decoder_decoded_andMatrixOutputs_lo_lo_33}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_42, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_42, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_42}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_42 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_42}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_42 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_42, cs_decoder_decoded_andMatrixOutputs_hi_lo_39}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_42 = {cs_decoder_decoded_andMatrixOutputs_hi_42, cs_decoder_decoded_andMatrixOutputs_lo_42}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_111_2 = &_cs_decoder_decoded_andMatrixOutputs_T_42; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_34 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_42 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_43 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_42, cs_decoder_decoded_andMatrixOutputs_lo_lo_34}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_43}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_43 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_43}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_43 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_43, cs_decoder_decoded_andMatrixOutputs_hi_lo_40}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_43 = {cs_decoder_decoded_andMatrixOutputs_hi_43, cs_decoder_decoded_andMatrixOutputs_lo_43}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_153_2 = &_cs_decoder_decoded_andMatrixOutputs_T_43; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_35 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_24}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_43 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_41}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_44 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_43, cs_decoder_decoded_andMatrixOutputs_lo_lo_35}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_41 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_44, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_44}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_44, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_44}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_44 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_44}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_44 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_44, cs_decoder_decoded_andMatrixOutputs_hi_lo_41}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_44 = {cs_decoder_decoded_andMatrixOutputs_hi_44, cs_decoder_decoded_andMatrixOutputs_lo_44}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_107_2 = &_cs_decoder_decoded_andMatrixOutputs_T_44; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_16}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_42, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_44 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_25}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_45 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_44, cs_decoder_decoded_andMatrixOutputs_lo_lo_36}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_45}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_42 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_44}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_45}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_45 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_45}; // @[pla.scala:90:45, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_45 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_45, cs_decoder_decoded_andMatrixOutputs_hi_lo_42}; // @[pla.scala:98:53] wire [10:0] _cs_decoder_decoded_andMatrixOutputs_T_45 = {cs_decoder_decoded_andMatrixOutputs_hi_45, cs_decoder_decoded_andMatrixOutputs_lo_45}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_17_2 = &_cs_decoder_decoded_andMatrixOutputs_T_45; // @[pla.scala:98:{53,70}] wire _cs_decoder_decoded_orMatrixOutputs_T_49 = cs_decoder_decoded_andMatrixOutputs_17_2; // @[pla.scala:98:70, :114:36] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_12}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_37 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_10}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_15}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_45 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_19, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_12}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_46 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_45, cs_decoder_decoded_andMatrixOutputs_lo_lo_37}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_37}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_46, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_45}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_43 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_17, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_10}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_46, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_46}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_46, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_46}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_46 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_26, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_13}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_46 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_46, cs_decoder_decoded_andMatrixOutputs_hi_lo_43}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_46 = {cs_decoder_decoded_andMatrixOutputs_hi_46, cs_decoder_decoded_andMatrixOutputs_lo_46}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_167_2 = &_cs_decoder_decoded_andMatrixOutputs_T_46; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_13}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_38 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_11}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_16}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_20}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_46 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_20, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_13}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_47 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_46, cs_decoder_decoded_andMatrixOutputs_lo_lo_38}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_44, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_46}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_44 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_18, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_11}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_47}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_47}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_47 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_27, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_14}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_47 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_47, cs_decoder_decoded_andMatrixOutputs_hi_lo_44}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_47 = {cs_decoder_decoded_andMatrixOutputs_hi_47, cs_decoder_decoded_andMatrixOutputs_lo_47}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_113_2 = &_cs_decoder_decoded_andMatrixOutputs_T_47; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_5}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_14}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_39 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_17, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_5}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_17}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_21}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_47 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_21, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_14}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_48 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_47, cs_decoder_decoded_andMatrixOutputs_lo_lo_39}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_39}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_47}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_45 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_19, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_12}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_48}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_48}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_48 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_28, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_15}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_48 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_48, cs_decoder_decoded_andMatrixOutputs_hi_lo_45}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_48 = {cs_decoder_decoded_andMatrixOutputs_hi_48, cs_decoder_decoded_andMatrixOutputs_lo_48}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_42_2 = &_cs_decoder_decoded_andMatrixOutputs_T_48; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_46, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_40}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_48 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_49, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_48}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_49 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_48, cs_decoder_decoded_andMatrixOutputs_lo_lo_40}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_46 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_49, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_49}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_49 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_49, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_49}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_49 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_49, cs_decoder_decoded_andMatrixOutputs_hi_lo_46}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_49 = {cs_decoder_decoded_andMatrixOutputs_hi_49, cs_decoder_decoded_andMatrixOutputs_lo_49}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_131_2 = &_cs_decoder_decoded_andMatrixOutputs_T_49; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_41 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_29}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_49 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_49, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_47}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_50 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_49, cs_decoder_decoded_andMatrixOutputs_lo_lo_41}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_47 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_50, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_50}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_50, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_50}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_50 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_50}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_50 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_50, cs_decoder_decoded_andMatrixOutputs_hi_lo_47}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_50 = {cs_decoder_decoded_andMatrixOutputs_hi_50, cs_decoder_decoded_andMatrixOutputs_lo_50}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_1_2 = &_cs_decoder_decoded_andMatrixOutputs_T_50; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_15}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_42 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_13}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_18}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_50 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_22, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_15}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_51 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_50, cs_decoder_decoded_andMatrixOutputs_lo_lo_42}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_51, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_50}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_48 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_20, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_13}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_51, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_51}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_51, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_51}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_51 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_30, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_16}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_51 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_51, cs_decoder_decoded_andMatrixOutputs_hi_lo_48}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_51 = {cs_decoder_decoded_andMatrixOutputs_hi_51, cs_decoder_decoded_andMatrixOutputs_lo_51}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_136_2 = &_cs_decoder_decoded_andMatrixOutputs_T_51; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_31 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_44 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_33 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_46 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_47 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_35 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_36 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_37 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_38 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_39 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_40 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_41 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_42 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_43 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_31 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_63 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_71 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_65 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_66 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_45 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_72 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_60 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_61 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_94 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_77 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_107 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_95 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_83 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_84 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_85 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_99 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_87 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_101 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_102 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_90 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_104 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_92 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_113 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_127 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_115 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_43 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_51 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_51, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_49}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_52 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_51, cs_decoder_decoded_andMatrixOutputs_lo_lo_43}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_49 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_52}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_52}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_52 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_52}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_52 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_52, cs_decoder_decoded_andMatrixOutputs_hi_lo_49}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_52 = {cs_decoder_decoded_andMatrixOutputs_hi_52, cs_decoder_decoded_andMatrixOutputs_lo_52}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_39_2 = &_cs_decoder_decoded_andMatrixOutputs_T_52; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_17}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_44 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_16}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_21}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_44, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_32}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_52 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_23, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_16}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_53 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_52, cs_decoder_decoded_andMatrixOutputs_lo_lo_44}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_53, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_52}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_50 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_50}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_53, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_53}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_53, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_53}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_53 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_32, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_17}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_53 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_53, cs_decoder_decoded_andMatrixOutputs_hi_lo_50}; // @[pla.scala:98:53] wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_53 = {cs_decoder_decoded_andMatrixOutputs_hi_53, cs_decoder_decoded_andMatrixOutputs_lo_53}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_108_2 = &_cs_decoder_decoded_andMatrixOutputs_T_53; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_17}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_45 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_14}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_20}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_24}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_53 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_24, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_17}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_54 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_53, cs_decoder_decoded_andMatrixOutputs_lo_lo_45}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_51, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_45}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_54, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_53}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_51 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_22, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_14}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_54, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_54}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_54, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_54}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_54 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_33, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_18}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_54 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_54, cs_decoder_decoded_andMatrixOutputs_hi_lo_51}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_54 = {cs_decoder_decoded_andMatrixOutputs_hi_54, cs_decoder_decoded_andMatrixOutputs_lo_54}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_165_2 = &_cs_decoder_decoded_andMatrixOutputs_T_54; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_19}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_46 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_18}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_23}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_46, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_54 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_25, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_18}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_55 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_54, cs_decoder_decoded_andMatrixOutputs_lo_lo_46}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_54}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_52 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_52}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_55}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_34 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_55}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_55 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_34, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_19}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_55 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_55, cs_decoder_decoded_andMatrixOutputs_hi_lo_52}; // @[pla.scala:98:53] wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_55 = {cs_decoder_decoded_andMatrixOutputs_hi_55, cs_decoder_decoded_andMatrixOutputs_lo_55}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_127_2 = &_cs_decoder_decoded_andMatrixOutputs_T_55; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_47 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_53, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_47}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_55 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_55}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_56 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_55, cs_decoder_decoded_andMatrixOutputs_lo_lo_47}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_53 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_56}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_56 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_56}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_56 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_56, cs_decoder_decoded_andMatrixOutputs_hi_lo_53}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_56 = {cs_decoder_decoded_andMatrixOutputs_hi_56, cs_decoder_decoded_andMatrixOutputs_lo_56}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_135_2 = &_cs_decoder_decoded_andMatrixOutputs_T_56; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_19}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_48 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_15}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_22}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_56 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_26, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_19}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_57 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_56, cs_decoder_decoded_andMatrixOutputs_lo_lo_48}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_54, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_48}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_54 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_24, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_15}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_57}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_35 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_57}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_57 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_35, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_20}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_57 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_57, cs_decoder_decoded_andMatrixOutputs_hi_lo_54}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_57 = {cs_decoder_decoded_andMatrixOutputs_hi_57, cs_decoder_decoded_andMatrixOutputs_lo_57}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_114_2 = &_cs_decoder_decoded_andMatrixOutputs_T_57; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_20}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_49 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_16}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_23}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_27}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_57 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_27, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_20}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_58 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_57, cs_decoder_decoded_andMatrixOutputs_lo_lo_49}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_49}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_57}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_55 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_25, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_16}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_58}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_58 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_36, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_21}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_58 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_58, cs_decoder_decoded_andMatrixOutputs_hi_lo_55}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_58 = {cs_decoder_decoded_andMatrixOutputs_hi_58, cs_decoder_decoded_andMatrixOutputs_lo_58}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_155_2 = &_cs_decoder_decoded_andMatrixOutputs_T_58; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_6}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_21}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_50 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_24, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_6}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_24}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_58 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_28, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_21}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_59 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_58, cs_decoder_decoded_andMatrixOutputs_lo_lo_50}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_50}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_59, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_56 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_26, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_17}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_59, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_59}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_37 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_59, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_59}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_59 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_37, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_22}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_59 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_59, cs_decoder_decoded_andMatrixOutputs_hi_lo_56}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_59 = {cs_decoder_decoded_andMatrixOutputs_hi_59, cs_decoder_decoded_andMatrixOutputs_lo_59}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_6_2 = &_cs_decoder_decoded_andMatrixOutputs_T_59; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_22}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_51 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_18}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_25}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_59 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_29, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_22}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_60 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_59, cs_decoder_decoded_andMatrixOutputs_lo_lo_51}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_51}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_59}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_57 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_27, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_18}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_60}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_38 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_60}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_60 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_38, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_23}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_60 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_60, cs_decoder_decoded_andMatrixOutputs_hi_lo_57}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_60 = {cs_decoder_decoded_andMatrixOutputs_hi_60, cs_decoder_decoded_andMatrixOutputs_lo_60}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_75_2 = &_cs_decoder_decoded_andMatrixOutputs_T_60; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_52 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_39}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_60 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_58}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_61 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_60, cs_decoder_decoded_andMatrixOutputs_lo_lo_52}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_58 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_61}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_61}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_61 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_61}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_61 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_61, cs_decoder_decoded_andMatrixOutputs_hi_lo_58}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_61 = {cs_decoder_decoded_andMatrixOutputs_hi_61, cs_decoder_decoded_andMatrixOutputs_lo_61}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_72_2 = &_cs_decoder_decoded_andMatrixOutputs_T_61; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_53 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_53, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_40}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_61 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_59}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_62 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_61, cs_decoder_decoded_andMatrixOutputs_lo_lo_53}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_59 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_62, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_62}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_62, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_62}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_62 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_62}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_62 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_62, cs_decoder_decoded_andMatrixOutputs_hi_lo_59}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_62 = {cs_decoder_decoded_andMatrixOutputs_hi_62, cs_decoder_decoded_andMatrixOutputs_lo_62}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_96_2 = &_cs_decoder_decoded_andMatrixOutputs_T_62; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_23}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_54 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_19}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_26}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_62 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_30, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_23}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_63 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_62, cs_decoder_decoded_andMatrixOutputs_lo_lo_54}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_54}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_62}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_60 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_28, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_19}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_63}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_41 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_63}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_63 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_41, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_24}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_63 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_63, cs_decoder_decoded_andMatrixOutputs_hi_lo_60}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_63 = {cs_decoder_decoded_andMatrixOutputs_hi_63, cs_decoder_decoded_andMatrixOutputs_lo_63}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_149_2 = &_cs_decoder_decoded_andMatrixOutputs_T_63; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_55 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_42}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_63 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_61}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_64 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_63, cs_decoder_decoded_andMatrixOutputs_lo_lo_55}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_61 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_64}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_42 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_64}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_64 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_42, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_64}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_64 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_64, cs_decoder_decoded_andMatrixOutputs_hi_lo_61}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_64 = {cs_decoder_decoded_andMatrixOutputs_hi_64, cs_decoder_decoded_andMatrixOutputs_lo_64}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_144_2 = &_cs_decoder_decoded_andMatrixOutputs_T_64; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_56 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_43}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_64 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_62}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_65 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_64, cs_decoder_decoded_andMatrixOutputs_lo_lo_56}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_62 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_65, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_43 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_65, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_65}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_65 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_65}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_65 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_65, cs_decoder_decoded_andMatrixOutputs_hi_lo_62}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_65 = {cs_decoder_decoded_andMatrixOutputs_hi_65, cs_decoder_decoded_andMatrixOutputs_lo_65}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_3_2 = &_cs_decoder_decoded_andMatrixOutputs_T_65; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_57 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_44, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_31}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_65, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_63}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_65 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_57}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_66 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_65, cs_decoder_decoded_andMatrixOutputs_lo_lo_57}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_63 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_66}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_44 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_66}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_66 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_44, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_66}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_66 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_66, cs_decoder_decoded_andMatrixOutputs_hi_lo_63}; // @[pla.scala:98:53] wire [9:0] _cs_decoder_decoded_andMatrixOutputs_T_66 = {cs_decoder_decoded_andMatrixOutputs_hi_66, cs_decoder_decoded_andMatrixOutputs_lo_66}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_13_2 = &_cs_decoder_decoded_andMatrixOutputs_T_66; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_45 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_33 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_68 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_60 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_48 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_49 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_50 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_64 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_52 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_53 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_59 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_47 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_48 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_54 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_47 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_23 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_69 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_70 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_71 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_85 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_86 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_92 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_57 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_18 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_14 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_11 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_122 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_68 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_106 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_24}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_58 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_20}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_27}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_32}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_66 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_32, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_24}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_67 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_66, cs_decoder_decoded_andMatrixOutputs_lo_lo_58}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_58}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_67, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_66}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_64 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_29, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_20}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_67, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_67}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_45 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_67, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_67}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_67 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_45, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_25}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_67 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_67, cs_decoder_decoded_andMatrixOutputs_hi_lo_64}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_67 = {cs_decoder_decoded_andMatrixOutputs_hi_67, cs_decoder_decoded_andMatrixOutputs_lo_67}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_141_2 = &_cs_decoder_decoded_andMatrixOutputs_T_67; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_7}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_25}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_59 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_28, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_7}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_28}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_46, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_67 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_33, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_25}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_68 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_67, cs_decoder_decoded_andMatrixOutputs_lo_lo_59}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_65, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_59}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_68, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_67}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_65 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_30, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_21}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_68, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_68}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_46 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_68, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_68}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_68 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_46, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_26}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_68 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_68, cs_decoder_decoded_andMatrixOutputs_hi_lo_65}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_68 = {cs_decoder_decoded_andMatrixOutputs_hi_68, cs_decoder_decoded_andMatrixOutputs_lo_68}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_93_2 = &_cs_decoder_decoded_andMatrixOutputs_T_68; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_68 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_69, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_68}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_69 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_68, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_66}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_66 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_69, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_69}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_69 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_69, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_69}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_69 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_69, cs_decoder_decoded_andMatrixOutputs_hi_lo_66}; // @[pla.scala:98:53] wire [6:0] _cs_decoder_decoded_andMatrixOutputs_T_69 = {cs_decoder_decoded_andMatrixOutputs_hi_69, cs_decoder_decoded_andMatrixOutputs_lo_69}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_60_2 = &_cs_decoder_decoded_andMatrixOutputs_T_69; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_34, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_31}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_60 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_29}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_34 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_67, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_60}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_69 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_34, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_47}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_70 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_69, cs_decoder_decoded_andMatrixOutputs_lo_lo_60}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_70, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_70}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_67 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_69}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_47 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_70, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_70}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_70 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_70}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_70 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_70, cs_decoder_decoded_andMatrixOutputs_hi_lo_67}; // @[pla.scala:98:53] wire [11:0] _cs_decoder_decoded_andMatrixOutputs_T_70 = {cs_decoder_decoded_andMatrixOutputs_hi_70, cs_decoder_decoded_andMatrixOutputs_lo_70}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_69_2 = &_cs_decoder_decoded_andMatrixOutputs_T_70; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_26}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_61 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_22}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_30}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_35 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_70 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_35, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_26}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_71 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_70, cs_decoder_decoded_andMatrixOutputs_lo_lo_61}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_68, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_61}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_70}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_68 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_32, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_22}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_71}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_48 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_71}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_71 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_48, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_27}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_71 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_71, cs_decoder_decoded_andMatrixOutputs_hi_lo_68}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_71 = {cs_decoder_decoded_andMatrixOutputs_hi_71, cs_decoder_decoded_andMatrixOutputs_lo_71}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_124_2 = &_cs_decoder_decoded_andMatrixOutputs_T_71; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_27}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_62 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_23}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_31}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_49, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_71 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_36, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_27}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_72 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_71, cs_decoder_decoded_andMatrixOutputs_lo_lo_62}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_69, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_62}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_71}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_69 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_33, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_23}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_72}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_49 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_72}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_72 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_49, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_28}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_72 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_72, cs_decoder_decoded_andMatrixOutputs_hi_lo_69}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_72 = {cs_decoder_decoded_andMatrixOutputs_hi_72, cs_decoder_decoded_andMatrixOutputs_lo_72}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_30_2 = &_cs_decoder_decoded_andMatrixOutputs_T_72; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_29}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_63 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_28}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_34}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_37 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_50}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_72 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_37, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_28}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_73 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_72, cs_decoder_decoded_andMatrixOutputs_lo_lo_63}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_34 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_73, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_72}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_70 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_34, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_70}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_73, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_73}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_50 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_73, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_73}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_73 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_50, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_29}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_73 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_73, cs_decoder_decoded_andMatrixOutputs_hi_lo_70}; // @[pla.scala:98:53] wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_73 = {cs_decoder_decoded_andMatrixOutputs_hi_73, cs_decoder_decoded_andMatrixOutputs_lo_73}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_35_2 = &_cs_decoder_decoded_andMatrixOutputs_T_73; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_30}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_64 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_29}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_35}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_38 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_51}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_73 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_38, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_29}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_74 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_73, cs_decoder_decoded_andMatrixOutputs_lo_lo_64}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_35 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_74, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_73}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_71 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_71}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_74, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_74}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_51 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_74, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_74}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_74 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_51, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_30}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_74 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_74, cs_decoder_decoded_andMatrixOutputs_hi_lo_71}; // @[pla.scala:98:53] wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_74 = {cs_decoder_decoded_andMatrixOutputs_hi_74, cs_decoder_decoded_andMatrixOutputs_lo_74}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_9_2 = &_cs_decoder_decoded_andMatrixOutputs_T_74; // @[pla.scala:98:{53,70}] wire _cs_decoder_decoded_orMatrixOutputs_T_84 = cs_decoder_decoded_andMatrixOutputs_9_2; // @[pla.scala:98:70, :114:36] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_34 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_30}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_65 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_34, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_24}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_34}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_39}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_74 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_39, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_30}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_75 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_74, cs_decoder_decoded_andMatrixOutputs_lo_lo_65}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_65}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_74}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_72 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_36, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_24}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_75}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_52 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_75}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_75 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_52, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_31}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_75 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_75, cs_decoder_decoded_andMatrixOutputs_hi_lo_72}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_75 = {cs_decoder_decoded_andMatrixOutputs_hi_75, cs_decoder_decoded_andMatrixOutputs_lo_75}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_89_2 = &_cs_decoder_decoded_andMatrixOutputs_T_75; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_35 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_31}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_66 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_25}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_35}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_53, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_40}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_75 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_40, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_31}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_76 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_75, cs_decoder_decoded_andMatrixOutputs_lo_lo_66}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_73, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_66}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_37 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_75}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_73 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_37, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_25}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_76}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_53 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_76}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_76 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_53, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_32}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_76 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_76, cs_decoder_decoded_andMatrixOutputs_hi_lo_73}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_76 = {cs_decoder_decoded_andMatrixOutputs_hi_76, cs_decoder_decoded_andMatrixOutputs_lo_76}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_57_2 = &_cs_decoder_decoded_andMatrixOutputs_T_76; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_33 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_55 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_38 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_44 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_3 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_43 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_42 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_43 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_73 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_61 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_69 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_68 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_69 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_66 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_67 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_13 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_94 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_93 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_94 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_90 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_87 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_78 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_24 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_13 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_10 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_7 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_3}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_26}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_67 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_36, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_8}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_41 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_38}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_76 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_41, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_32}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_77 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_76, cs_decoder_decoded_andMatrixOutputs_lo_lo_67}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_67, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_54}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_38 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_74}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_74 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_38, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_26}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_77}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_77}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_54 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_77}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_77 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_54, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_33}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_77 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_77, cs_decoder_decoded_andMatrixOutputs_hi_lo_74}; // @[pla.scala:98:53] wire [16:0] _cs_decoder_decoded_andMatrixOutputs_T_77 = {cs_decoder_decoded_andMatrixOutputs_hi_77, cs_decoder_decoded_andMatrixOutputs_lo_77}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_164_2 = &_cs_decoder_decoded_andMatrixOutputs_T_77; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_37 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_37}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_68 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_34}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_42 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_68, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_55}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_77 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_42, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_42}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_78 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_77, cs_decoder_decoded_andMatrixOutputs_lo_lo_68}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_77}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_75 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_75}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_34 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_78}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_55 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_78}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_78 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_55, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_34}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_78 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_78, cs_decoder_decoded_andMatrixOutputs_hi_lo_75}; // @[pla.scala:98:53] wire [12:0] _cs_decoder_decoded_andMatrixOutputs_T_78 = {cs_decoder_decoded_andMatrixOutputs_hi_78, cs_decoder_decoded_andMatrixOutputs_lo_78}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_121_2 = &_cs_decoder_decoded_andMatrixOutputs_T_78; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_9}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_38 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_33}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_69 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_38, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_9}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_43 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_43}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_78 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_43, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_33}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_79 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_78, cs_decoder_decoded_andMatrixOutputs_lo_lo_69}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_69}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_79, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_78}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_76 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_40, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_27}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_35 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_79, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_79}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_56 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_79, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_79}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_79 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_56, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_35}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_79 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_79, cs_decoder_decoded_andMatrixOutputs_hi_lo_76}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_79 = {cs_decoder_decoded_andMatrixOutputs_hi_79, cs_decoder_decoded_andMatrixOutputs_lo_79}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_25_2 = &_cs_decoder_decoded_andMatrixOutputs_T_79; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_39}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_70 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_36}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_44 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_70, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_57}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_79 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_44, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_44}; // @[pla.scala:90:45, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_80 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_79, cs_decoder_decoded_andMatrixOutputs_lo_lo_70}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_41 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_79}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_77 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_77}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_80}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_57 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_80}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_80 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_57, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_36}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_80 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_80, cs_decoder_decoded_andMatrixOutputs_hi_lo_77}; // @[pla.scala:98:53] wire [12:0] _cs_decoder_decoded_andMatrixOutputs_T_80 = {cs_decoder_decoded_andMatrixOutputs_hi_80, cs_decoder_decoded_andMatrixOutputs_lo_80}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_99_2 = &_cs_decoder_decoded_andMatrixOutputs_T_80; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_42 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_75 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_50 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_15 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_6 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_6 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_121 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_122 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_127 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_128 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_137 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_107 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_105 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_112 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_92 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_35 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_16 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_148 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_124 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_128 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_126 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_127 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_131 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_129 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_3}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_3}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_40 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_3}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_71 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_40, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_10}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_10}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_34 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_4}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_37}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_45 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_34}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_80 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_45, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_34}; // @[pla.scala:98:53] wire [10:0] cs_decoder_decoded_andMatrixOutputs_lo_81 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_80, cs_decoder_decoded_andMatrixOutputs_lo_lo_71}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_71}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_42 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_58}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_78 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_42, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_28}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_81}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_37 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_80}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_81}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_58 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_81}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_81 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_58, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_37}; // @[pla.scala:98:53] wire [10:0] cs_decoder_decoded_andMatrixOutputs_hi_81 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_81, cs_decoder_decoded_andMatrixOutputs_hi_lo_78}; // @[pla.scala:98:53] wire [21:0] _cs_decoder_decoded_andMatrixOutputs_T_81 = {cs_decoder_decoded_andMatrixOutputs_hi_81, cs_decoder_decoded_andMatrixOutputs_lo_81}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_51_2 = &_cs_decoder_decoded_andMatrixOutputs_T_81; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_41 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_35}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_72 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_29}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_35 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_41}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_46 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_59, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_46}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_81 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_46, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_35}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_82 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_81, cs_decoder_decoded_andMatrixOutputs_lo_lo_72}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_79, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_72}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_43 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_82, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_81}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_79 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_43, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_29}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_38 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_82, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_82}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_59 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_82, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_82}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_82 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_59, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_38}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_82 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_82, cs_decoder_decoded_andMatrixOutputs_hi_lo_79}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_82 = {cs_decoder_decoded_andMatrixOutputs_hi_82, cs_decoder_decoded_andMatrixOutputs_lo_82}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_37_2 = &_cs_decoder_decoded_andMatrixOutputs_T_82; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_11}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_42 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_36}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_73 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_42, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_11}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_44, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_47 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_47}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_82 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_47, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_36}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_83 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_82, cs_decoder_decoded_andMatrixOutputs_lo_lo_73}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_73}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_44 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_82}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_80 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_44, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_30}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_83}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_60 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_83}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_83 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_60, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_39}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_83 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_83, cs_decoder_decoded_andMatrixOutputs_hi_lo_80}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_83 = {cs_decoder_decoded_andMatrixOutputs_hi_83, cs_decoder_decoded_andMatrixOutputs_lo_83}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_143_2 = &_cs_decoder_decoded_andMatrixOutputs_T_83; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_12}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_43 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_37}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_74 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_43, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_12}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_37 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_43}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_48 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_48}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_83 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_48, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_37}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_84 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_83, cs_decoder_decoded_andMatrixOutputs_lo_lo_74}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_74}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_45 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_83}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_81 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_45, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_31}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_84}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_61 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_84}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_84 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_61, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_40}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_84 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_84, cs_decoder_decoded_andMatrixOutputs_hi_lo_81}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_84 = {cs_decoder_decoded_andMatrixOutputs_hi_84, cs_decoder_decoded_andMatrixOutputs_lo_84}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_137_2 = &_cs_decoder_decoded_andMatrixOutputs_T_84; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_38 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_14 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_3 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_4 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_28_1 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_6 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_7 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_28_2 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_46 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_14 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_12 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_60 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_58 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_77 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_45 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_9 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_10 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_28_3 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_115 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_33 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_5}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_44 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_32}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_75 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_44, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_13}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_38 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_44, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_41}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_49 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_49, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_46}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_84 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_49, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_38}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_85 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_84, cs_decoder_decoded_andMatrixOutputs_lo_lo_75}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_62}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_46 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_82}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_82 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_46, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_32}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_41 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_85, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_85}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_85, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_85}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_62 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_85}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_85 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_62, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_41}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_85 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_85, cs_decoder_decoded_andMatrixOutputs_hi_lo_82}; // @[pla.scala:98:53] wire [16:0] _cs_decoder_decoded_andMatrixOutputs_T_85 = {cs_decoder_decoded_andMatrixOutputs_hi_85, cs_decoder_decoded_andMatrixOutputs_lo_85}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_118_2 = &_cs_decoder_decoded_andMatrixOutputs_T_85; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_4}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_45 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_76 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_45, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_14}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_33}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_45}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_50 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_42}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_85 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_50, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_39}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_lo_86 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_85, cs_decoder_decoded_andMatrixOutputs_lo_lo_76}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_50}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_85, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_83}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_47 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_76}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_83 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_47, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_33}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_42 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_86, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_86}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_86, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_86}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_63 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_86}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_86 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_63, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_42}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_hi_86 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_86, cs_decoder_decoded_andMatrixOutputs_hi_lo_83}; // @[pla.scala:98:53] wire [18:0] _cs_decoder_decoded_andMatrixOutputs_T_86 = {cs_decoder_decoded_andMatrixOutputs_hi_86, cs_decoder_decoded_andMatrixOutputs_lo_86}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_58_2 = &_cs_decoder_decoded_andMatrixOutputs_T_86; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_7 = cs_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_6 = cs_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_6 = cs_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_72 = cs_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_58 = cs_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_26 = cs_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_15 = cs_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_3}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_15 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_3}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_4}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_46 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_3}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_77 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_46, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_15}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_5}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_40 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_4}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_34}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_51 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_3}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_86 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_51, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_40}; // @[pla.scala:98:53] wire [12:0] cs_decoder_decoded_andMatrixOutputs_lo_87 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_86, cs_decoder_decoded_andMatrixOutputs_lo_lo_77}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_46}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_34 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_43}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_64}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_48 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_51}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_84 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_48, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_34}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_87, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_86}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_43 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_84}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_87, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_87}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_87, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_87}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_64 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_3}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_87 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_64, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_43}; // @[pla.scala:98:53] wire [12:0] cs_decoder_decoded_andMatrixOutputs_hi_87 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_87, cs_decoder_decoded_andMatrixOutputs_hi_lo_84}; // @[pla.scala:98:53] wire [25:0] _cs_decoder_decoded_andMatrixOutputs_T_87 = {cs_decoder_decoded_andMatrixOutputs_hi_87, cs_decoder_decoded_andMatrixOutputs_lo_87}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_146_2 = &_cs_decoder_decoded_andMatrixOutputs_T_87; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_16 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_2}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_4}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_4}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_47 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_78 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_47, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_16}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_41 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_5}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_6}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_16}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_52 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_4}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_87 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_52, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_41}; // @[pla.scala:98:53] wire [13:0] cs_decoder_decoded_andMatrixOutputs_lo_88 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_87, cs_decoder_decoded_andMatrixOutputs_lo_lo_78}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_44}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_35 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_41}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_49}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_65}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_49 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_85 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_49, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_35}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_88, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_87}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_44 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_85}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_88, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_88}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_88, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_88}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_65 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_4}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_88 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_65, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_44}; // @[pla.scala:98:53] wire [13:0] cs_decoder_decoded_andMatrixOutputs_hi_88 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_88, cs_decoder_decoded_andMatrixOutputs_hi_lo_85}; // @[pla.scala:98:53] wire [27:0] _cs_decoder_decoded_andMatrixOutputs_T_88 = {cs_decoder_decoded_andMatrixOutputs_hi_88, cs_decoder_decoded_andMatrixOutputs_lo_88}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_50_2 = &_cs_decoder_decoded_andMatrixOutputs_T_88; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_28_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_29_1}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_17 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_30_1}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_3}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_5}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_48 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_3}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_79 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_48, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_17}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_5}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_42 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_6}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_7}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_53 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_5}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_88 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_53, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_42}; // @[pla.scala:98:53] wire [14:0] cs_decoder_decoded_andMatrixOutputs_lo_89 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_88, cs_decoder_decoded_andMatrixOutputs_lo_lo_79}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_17}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_42}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_36 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_50, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_48}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_53}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_50 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_3}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_86 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_50, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_36}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_86, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_79}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_89, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_88}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_45 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_89, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_89}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_89, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_89}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_66 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_5}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_89 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_66, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_45}; // @[pla.scala:98:53] wire [15:0] cs_decoder_decoded_andMatrixOutputs_hi_89 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_89, cs_decoder_decoded_andMatrixOutputs_hi_lo_86}; // @[pla.scala:98:53] wire [30:0] _cs_decoder_decoded_andMatrixOutputs_T_89 = {cs_decoder_decoded_andMatrixOutputs_hi_89, cs_decoder_decoded_andMatrixOutputs_lo_89}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_129_2 = &_cs_decoder_decoded_andMatrixOutputs_T_89; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_37 = cs_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_11 = cs_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_9 = cs_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_74 = cs_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_119 = cs_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_120 = cs_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_10 = cs_decoder_decoded_plaInput[22]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_9 = cs_decoder_decoded_plaInput[22]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_8 = cs_decoder_decoded_plaInput[22]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_68 = cs_decoder_decoded_plaInput[22]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_6}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_18 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_6}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_7}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_49 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_6}; // @[pla.scala:90:45, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_80 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_49, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_18}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_8}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_43 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_7}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_54 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_6}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_89 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_54, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_43}; // @[pla.scala:98:53] wire [12:0] cs_decoder_decoded_andMatrixOutputs_lo_90 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_89, cs_decoder_decoded_andMatrixOutputs_lo_lo_80}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_51, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_49}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_37 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_46}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_67}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_51 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_54}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_87 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_51, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_37}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_90, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_89}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_46 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_87}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_90, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_90}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_90, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_90}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_67 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_6}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_90 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_67, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_46}; // @[pla.scala:98:53] wire [12:0] cs_decoder_decoded_andMatrixOutputs_hi_90 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_90, cs_decoder_decoded_andMatrixOutputs_hi_lo_87}; // @[pla.scala:98:53] wire [25:0] _cs_decoder_decoded_andMatrixOutputs_T_90 = {cs_decoder_decoded_andMatrixOutputs_hi_90, cs_decoder_decoded_andMatrixOutputs_lo_90}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_66_2 = &_cs_decoder_decoded_andMatrixOutputs_T_90; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_4}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_19 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_4}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_7}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_50 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_4}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_81 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_50, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_19}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_44 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_8}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_19}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_55 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_7}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_90 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_55, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_44}; // @[pla.scala:98:53] wire [13:0] cs_decoder_decoded_andMatrixOutputs_lo_91 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_90, cs_decoder_decoded_andMatrixOutputs_lo_lo_81}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_50, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_47}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_38 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_44}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_52}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_68}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_52 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_4}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_88 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_52, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_38}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_90}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_47 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_88}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_91}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_91}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_68 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_11, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_7}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_91 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_68, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_47}; // @[pla.scala:98:53] wire [13:0] cs_decoder_decoded_andMatrixOutputs_hi_91 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_91, cs_decoder_decoded_andMatrixOutputs_hi_lo_88}; // @[pla.scala:98:53] wire [27:0] _cs_decoder_decoded_andMatrixOutputs_T_91 = {cs_decoder_decoded_andMatrixOutputs_hi_91, cs_decoder_decoded_andMatrixOutputs_lo_91}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_134_2 = &_cs_decoder_decoded_andMatrixOutputs_T_91; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_30_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_31}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_28_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_29_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_20 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_8, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_lo}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_5}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_8}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_51 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_5}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_82 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_51, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_20}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_45 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_9, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_9}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_10}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_56 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_8}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_91 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_56, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_45}; // @[pla.scala:98:53] wire [15:0] cs_decoder_decoded_andMatrixOutputs_lo_92 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_91, cs_decoder_decoded_andMatrixOutputs_lo_lo_82}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_20}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_45}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_39 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_8, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_53, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_51}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_69, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_56}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_53 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_5}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_89 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_53, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_39}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_89, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_82}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_92, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_91}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_48 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_9, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_92, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_92}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_92, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_92}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_69 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_12, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_8}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_92 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_69, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_48}; // @[pla.scala:98:53] wire [15:0] cs_decoder_decoded_andMatrixOutputs_hi_92 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_92, cs_decoder_decoded_andMatrixOutputs_hi_lo_89}; // @[pla.scala:98:53] wire [31:0] _cs_decoder_decoded_andMatrixOutputs_T_92 = {cs_decoder_decoded_andMatrixOutputs_hi_92, cs_decoder_decoded_andMatrixOutputs_lo_92}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_97_2 = &_cs_decoder_decoded_andMatrixOutputs_T_92; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_13}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_52 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_46, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_40}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_83 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_52, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_21}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_46 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_49}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_57 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_54}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_92 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_57, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_46}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_93 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_92, cs_decoder_decoded_andMatrixOutputs_lo_lo_83}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_70}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_54 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_92, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_90}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_90 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_54, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_40}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_49 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_93, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_93}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_93, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_93}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_70 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_93}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_93 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_70, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_49}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_93 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_93, cs_decoder_decoded_andMatrixOutputs_hi_lo_90}; // @[pla.scala:98:53] wire [16:0] _cs_decoder_decoded_andMatrixOutputs_T_93 = {cs_decoder_decoded_andMatrixOutputs_hi_93, cs_decoder_decoded_andMatrixOutputs_lo_93}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_65_2 = &_cs_decoder_decoded_andMatrixOutputs_T_93; // @[pla.scala:98:{53,70}] wire _cs_decoder_decoded_orMatrixOutputs_T_50 = cs_decoder_decoded_andMatrixOutputs_65_2; // @[pla.scala:98:70, :114:36] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_10}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_53 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_11}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_84 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_53, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_22}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_47 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_41}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_53}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_58 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_50}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_93 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_58, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_47}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_lo_94 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_93, cs_decoder_decoded_andMatrixOutputs_lo_lo_84}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_41 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_58}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_93, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_91}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_55 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_84}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_91 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_55, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_41}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_50 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_94, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_94}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_94, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_94}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_71 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_94}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_94 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_71, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_50}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_hi_94 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_94, cs_decoder_decoded_andMatrixOutputs_hi_lo_91}; // @[pla.scala:98:53] wire [19:0] _cs_decoder_decoded_andMatrixOutputs_T_94 = {cs_decoder_decoded_andMatrixOutputs_hi_94, cs_decoder_decoded_andMatrixOutputs_lo_94}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_16_2 = &_cs_decoder_decoded_andMatrixOutputs_T_94; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_10}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_54 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_11}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_85 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_54, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_23}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_42, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_48 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_15}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_54, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_51}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_59 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_48}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_94 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_59, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_48}; // @[pla.scala:98:53] wire [10:0] cs_decoder_decoded_andMatrixOutputs_lo_95 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_94, cs_decoder_decoded_andMatrixOutputs_lo_lo_85}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_42 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_59, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_56}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_92, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_85}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_56 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_72}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_92 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_56, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_42}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_95, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_95}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_51 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_94}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_95, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_95}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_72 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_95}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_95 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_72, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_51}; // @[pla.scala:98:53] wire [10:0] cs_decoder_decoded_andMatrixOutputs_hi_95 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_95, cs_decoder_decoded_andMatrixOutputs_hi_lo_92}; // @[pla.scala:98:53] wire [21:0] _cs_decoder_decoded_andMatrixOutputs_T_95 = {cs_decoder_decoded_andMatrixOutputs_hi_95, cs_decoder_decoded_andMatrixOutputs_lo_95}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_95_2 = &_cs_decoder_decoded_andMatrixOutputs_T_95; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_55 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_55}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_86 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_52}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_60 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_86, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_73}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_95 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_60}; // @[pla.scala:90:45, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_96 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_95, cs_decoder_decoded_andMatrixOutputs_lo_lo_86}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_57 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_96, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_95}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_93 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_93}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_52 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_96, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_96}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_73 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_96, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_96}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_96 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_73, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_52}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_96 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_96, cs_decoder_decoded_andMatrixOutputs_hi_lo_93}; // @[pla.scala:98:53] wire [12:0] _cs_decoder_decoded_andMatrixOutputs_T_96 = {cs_decoder_decoded_andMatrixOutputs_hi_96, cs_decoder_decoded_andMatrixOutputs_lo_96}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_82_2 = &_cs_decoder_decoded_andMatrixOutputs_T_96; // @[pla.scala:98:{53,70}] wire _cs_decoder_decoded_orMatrixOutputs_T_3 = cs_decoder_decoded_andMatrixOutputs_82_2; // @[pla.scala:98:70, :114:36] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_56 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_53}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_87 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_49}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_49 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_58}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_61 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_87, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_74}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_96 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_61, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_49}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_97 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_96, cs_decoder_decoded_andMatrixOutputs_lo_lo_87}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_58 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_97, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_96}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_94 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_94}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_53 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_97, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_97}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_74 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_97, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_97}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_97 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_74, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_53}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_97 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_97, cs_decoder_decoded_andMatrixOutputs_hi_lo_94}; // @[pla.scala:98:53] wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_97 = {cs_decoder_decoded_andMatrixOutputs_hi_97, cs_decoder_decoded_andMatrixOutputs_lo_97}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_54_2 = &_cs_decoder_decoded_andMatrixOutputs_T_97; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_54 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_55 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_59 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_57 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_61 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_58 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_59 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_56 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_57 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_62 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_63 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_60 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_61 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_52 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_53 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_12 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_79 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_80 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_81 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_20 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_21 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_19 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_23 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_100 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_97 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_98 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_99 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_100 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_17 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_9 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_10 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_29_3 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_109 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_110 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_28 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_29 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_27 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_28 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_29 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_30 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_57 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_54}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_88 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_50}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_50 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_62, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_59}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_62 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_88, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_75}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_97 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_62, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_50}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_98 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_97, cs_decoder_decoded_andMatrixOutputs_lo_lo_88}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_59 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_98, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_97}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_95 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_59, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_95}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_54 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_98, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_98}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_75 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_98, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_98}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_98 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_75, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_54}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_98 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_98, cs_decoder_decoded_andMatrixOutputs_hi_lo_95}; // @[pla.scala:98:53] wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_98 = {cs_decoder_decoded_andMatrixOutputs_hi_98, cs_decoder_decoded_andMatrixOutputs_lo_98}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_7_2 = &_cs_decoder_decoded_andMatrixOutputs_T_98; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_58 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_55}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_89 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_51}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_51 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_60}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_63 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_89, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_76}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_98 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_63, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_51}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_99 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_98, cs_decoder_decoded_andMatrixOutputs_lo_lo_89}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_60 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_99, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_98}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_96 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_96}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_55 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_99, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_99}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_76 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_99, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_99}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_99 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_76, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_55}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_99 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_99, cs_decoder_decoded_andMatrixOutputs_hi_lo_96}; // @[pla.scala:98:53] wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_99 = {cs_decoder_decoded_andMatrixOutputs_hi_99, cs_decoder_decoded_andMatrixOutputs_lo_99}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_115_2 = &_cs_decoder_decoded_andMatrixOutputs_T_99; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_59 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_59, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_90 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_59, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_52}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_52 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_61}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_64 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_90, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_77}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_99 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_64, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_52}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_100 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_99, cs_decoder_decoded_andMatrixOutputs_lo_lo_90}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_61 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_100, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_99}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_97 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_97}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_56 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_100, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_100}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_77 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_100, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_100}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_100 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_77, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_56}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_100 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_100, cs_decoder_decoded_andMatrixOutputs_hi_lo_97}; // @[pla.scala:98:53] wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_100 = {cs_decoder_decoded_andMatrixOutputs_hi_100, cs_decoder_decoded_andMatrixOutputs_lo_100}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_92_2 = &_cs_decoder_decoded_andMatrixOutputs_T_100; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_60 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_53}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_91 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_43}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_53 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_62, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_60}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_65 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_65}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_100 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_65, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_53}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_101 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_100, cs_decoder_decoded_andMatrixOutputs_lo_lo_91}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_43 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_98, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_91}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_62 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_101, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_100}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_98 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_62, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_43}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_57 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_101, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_101}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_78 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_101, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_101}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_101 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_78, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_57}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_101 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_101, cs_decoder_decoded_andMatrixOutputs_hi_lo_98}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_101 = {cs_decoder_decoded_andMatrixOutputs_hi_101, cs_decoder_decoded_andMatrixOutputs_lo_101}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_40_2 = &_cs_decoder_decoded_andMatrixOutputs_T_101; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_61 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_63}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_92 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_61}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_66 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_99, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_92}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_101 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_79}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_102 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_101, cs_decoder_decoded_andMatrixOutputs_lo_lo_92}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_63 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_102, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_102}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_99 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_101}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_79 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_102, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_102}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_102 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_79, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_102}; // @[pla.scala:90:45, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_102 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_102, cs_decoder_decoded_andMatrixOutputs_hi_lo_99}; // @[pla.scala:98:53] wire [11:0] _cs_decoder_decoded_andMatrixOutputs_T_102 = {cs_decoder_decoded_andMatrixOutputs_hi_102, cs_decoder_decoded_andMatrixOutputs_lo_102}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_63_2 = &_cs_decoder_decoded_andMatrixOutputs_T_102; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_62 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_54}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_93 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_62, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_44}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_54 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_62}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_67 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_67}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_102 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_67, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_54}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_103 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_102, cs_decoder_decoded_andMatrixOutputs_lo_lo_93}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_44 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_100, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_93}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_64 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_103, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_102}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_100 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_64, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_44}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_58 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_103, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_103}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_80 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_103, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_103}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_103 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_80, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_58}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_103 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_103, cs_decoder_decoded_andMatrixOutputs_hi_lo_100}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_103 = {cs_decoder_decoded_andMatrixOutputs_hi_103, cs_decoder_decoded_andMatrixOutputs_lo_103}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_133_2 = &_cs_decoder_decoded_andMatrixOutputs_T_103; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_63 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_59, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_55}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_94 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_45}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_55 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_65, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_63}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_68 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_68}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_103 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_68, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_55}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_104 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_103, cs_decoder_decoded_andMatrixOutputs_lo_lo_94}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_45 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_101, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_94}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_65 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_104, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_103}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_101 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_65, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_45}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_59 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_104, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_104}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_81 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_104, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_104}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_104 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_81, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_59}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_104 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_104, cs_decoder_decoded_andMatrixOutputs_hi_lo_101}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_104 = {cs_decoder_decoded_andMatrixOutputs_hi_104, cs_decoder_decoded_andMatrixOutputs_lo_104}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_28_2 = &_cs_decoder_decoded_andMatrixOutputs_T_104; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_64 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_95 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_46}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_56 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_64}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_69 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_82, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_69}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_104 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_69, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_56}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_105 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_104, cs_decoder_decoded_andMatrixOutputs_lo_lo_95}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_46 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_102, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_95}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_66 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_105, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_104}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_102 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_66, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_46}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_60 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_105, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_105}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_82 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_105, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_105}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_105 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_82, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_60}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_105 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_105, cs_decoder_decoded_andMatrixOutputs_hi_lo_102}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_105 = {cs_decoder_decoded_andMatrixOutputs_hi_105, cs_decoder_decoded_andMatrixOutputs_lo_105}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_68_2 = &_cs_decoder_decoded_andMatrixOutputs_T_105; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_65 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_57}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_96 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_65, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_47}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_57 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_67, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_65}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_70 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_70}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_105 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_70, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_57}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_106 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_105, cs_decoder_decoded_andMatrixOutputs_lo_lo_96}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_47 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_103, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_96}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_67 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_106, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_105}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_103 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_67, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_47}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_61 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_106, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_106}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_83 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_106, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_106}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_106 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_83, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_61}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_106 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_106, cs_decoder_decoded_andMatrixOutputs_hi_lo_103}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_106 = {cs_decoder_decoded_andMatrixOutputs_hi_106, cs_decoder_decoded_andMatrixOutputs_lo_106}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_11_2 = &_cs_decoder_decoded_andMatrixOutputs_T_106; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_66 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_62, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_97 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_48}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_58 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_68, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_66}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_71 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_71}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_106 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_71, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_58}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_107 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_106, cs_decoder_decoded_andMatrixOutputs_lo_lo_97}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_48 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_104, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_97}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_68 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_107, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_106}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_104 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_68, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_48}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_62 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_107, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_107}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_84 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_107, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_107}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_107 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_84, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_62}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_107 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_107, cs_decoder_decoded_andMatrixOutputs_hi_lo_104}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_107 = {cs_decoder_decoded_andMatrixOutputs_hi_107, cs_decoder_decoded_andMatrixOutputs_lo_107}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_74_2 = &_cs_decoder_decoded_andMatrixOutputs_T_107; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_67 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_59}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_98 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_67, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_49}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_59 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_69, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_67}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_72 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_85, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_72}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_107 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_72, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_59}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_108 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_107, cs_decoder_decoded_andMatrixOutputs_lo_lo_98}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_49 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_105, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_98}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_69 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_108, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_107}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_105 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_69, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_49}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_63 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_108, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_108}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_85 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_108, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_108}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_108 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_85, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_63}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_108 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_108, cs_decoder_decoded_andMatrixOutputs_hi_lo_105}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_108 = {cs_decoder_decoded_andMatrixOutputs_hi_108, cs_decoder_decoded_andMatrixOutputs_lo_108}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_139_2 = &_cs_decoder_decoded_andMatrixOutputs_T_108; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_68 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_60}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_99 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_68, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_50}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_60 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_70, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_68}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_73 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_86, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_73}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_108 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_73, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_60}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_109 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_108, cs_decoder_decoded_andMatrixOutputs_lo_lo_99}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_50 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_106, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_99}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_70 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_109, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_108}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_106 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_70, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_50}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_64 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_109, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_109}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_86 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_109, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_109}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_109 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_86, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_64}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_109 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_109, cs_decoder_decoded_andMatrixOutputs_hi_lo_106}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_109 = {cs_decoder_decoded_andMatrixOutputs_hi_109, cs_decoder_decoded_andMatrixOutputs_lo_109}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_156_2 = &_cs_decoder_decoded_andMatrixOutputs_T_109; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_51, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_24}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_69 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_65, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_61}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_100 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_69, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_24}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_61 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_69}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_74 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_87, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_74}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_109 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_74, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_61}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_110 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_109, cs_decoder_decoded_andMatrixOutputs_lo_lo_100}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_51 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_107, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_100}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_71 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_110, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_109}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_107 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_71, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_51}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_65 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_110, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_110}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_87 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_110, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_110}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_110 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_87, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_65}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_110 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_110, cs_decoder_decoded_andMatrixOutputs_hi_lo_107}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_110 = {cs_decoder_decoded_andMatrixOutputs_hi_110, cs_decoder_decoded_andMatrixOutputs_lo_110}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_38_2 = &_cs_decoder_decoded_andMatrixOutputs_T_110; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_70 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_62}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_101 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_70, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_25}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_62 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_70}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_75 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_88, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_75}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_110 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_75, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_62}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_111 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_110, cs_decoder_decoded_andMatrixOutputs_lo_lo_101}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_52 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_108, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_101}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_72 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_111, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_110}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_108 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_72, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_52}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_66 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_111, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_111}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_88 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_111, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_111}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_111 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_88, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_66}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_111 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_111, cs_decoder_decoded_andMatrixOutputs_hi_lo_108}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_111 = {cs_decoder_decoded_andMatrixOutputs_hi_111, cs_decoder_decoded_andMatrixOutputs_lo_111}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_116_2 = &_cs_decoder_decoded_andMatrixOutputs_T_111; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_16}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_71 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_53}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_102 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_71, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_26}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_63 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_67}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_76 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_73}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_111 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_76, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_63}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_112 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_111, cs_decoder_decoded_andMatrixOutputs_lo_lo_102}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_53 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_102, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_89}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_73 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_111, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_109}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_109 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_73, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_53}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_67 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_112, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_112}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_112, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_112}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_89 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_112}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_112 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_89, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_67}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_112 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_112, cs_decoder_decoded_andMatrixOutputs_hi_lo_109}; // @[pla.scala:98:53] wire [16:0] _cs_decoder_decoded_andMatrixOutputs_T_112 = {cs_decoder_decoded_andMatrixOutputs_hi_112, cs_decoder_decoded_andMatrixOutputs_lo_112}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_4_2 = &_cs_decoder_decoded_andMatrixOutputs_T_112; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_11}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_72 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_12}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_103 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_72, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_27}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_54, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_27}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_64 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_17}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_68}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_77 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_64}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_112 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_77, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_64}; // @[pla.scala:98:53] wire [10:0] cs_decoder_decoded_andMatrixOutputs_lo_113 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_112, cs_decoder_decoded_andMatrixOutputs_lo_lo_103}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_54 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_74}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_110, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_103}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_74 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_90}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_110 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_74, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_54}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_113, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_113}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_68 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_112}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_113, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_113}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_90 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_113}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_113 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_90, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_68}; // @[pla.scala:98:53] wire [10:0] cs_decoder_decoded_andMatrixOutputs_hi_113 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_113, cs_decoder_decoded_andMatrixOutputs_hi_lo_110}; // @[pla.scala:98:53] wire [21:0] _cs_decoder_decoded_andMatrixOutputs_T_113 = {cs_decoder_decoded_andMatrixOutputs_hi_113, cs_decoder_decoded_andMatrixOutputs_lo_113}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_163_2 = &_cs_decoder_decoded_andMatrixOutputs_T_113; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_55 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_56 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_75 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_67 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_58 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_69 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_70 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_61 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_72 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_63 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_64 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_75 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_66 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_67 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_36 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_14 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_15 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_16 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_17 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_83 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_74 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_75 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_43 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_24 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_19 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_46 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_47 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_48 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_17 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_18 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_15 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_20 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_96 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_87 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_88 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_89 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_90 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_13 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_9 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_6 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_30_3 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_97 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_108 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_99 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_100 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_101 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_25 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_26 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_23 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_24 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_25 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_26 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_73 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_69, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_65}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_104 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_73, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_28}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_65 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_73}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_78 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_78}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_113 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_78, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_65}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_114 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_113, cs_decoder_decoded_andMatrixOutputs_lo_lo_104}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_55 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_111, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_104}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_75 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_114, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_113}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_111 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_75, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_55}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_69 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_114, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_114}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_91 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_114, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_114}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_114 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_91, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_69}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_114 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_114, cs_decoder_decoded_andMatrixOutputs_hi_lo_111}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_114 = {cs_decoder_decoded_andMatrixOutputs_hi_114, cs_decoder_decoded_andMatrixOutputs_lo_114}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_5_2 = &_cs_decoder_decoded_andMatrixOutputs_T_114; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_74 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_70, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_66}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_105 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_74, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_29}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_66 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_74}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_79 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_92, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_79}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_114 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_79, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_66}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_115 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_114, cs_decoder_decoded_andMatrixOutputs_lo_lo_105}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_56 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_112, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_105}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_76 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_115, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_114}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_112 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_76, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_56}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_70 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_115, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_115}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_92 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_115, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_115}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_115 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_92, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_70}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_115 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_115, cs_decoder_decoded_andMatrixOutputs_hi_lo_112}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_115 = {cs_decoder_decoded_andMatrixOutputs_hi_115, cs_decoder_decoded_andMatrixOutputs_lo_115}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_22_2 = &_cs_decoder_decoded_andMatrixOutputs_T_115; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_75 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_77}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_106 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_75}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_80 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_113, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_106}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_115 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_93}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_116 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_115, cs_decoder_decoded_andMatrixOutputs_lo_lo_106}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_77 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_116, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_116}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_113 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_115}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_93 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_116, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_116}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_116 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_93, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_116}; // @[pla.scala:90:45, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_116 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_116, cs_decoder_decoded_andMatrixOutputs_hi_lo_113}; // @[pla.scala:98:53] wire [11:0] _cs_decoder_decoded_andMatrixOutputs_T_116 = {cs_decoder_decoded_andMatrixOutputs_hi_116, cs_decoder_decoded_andMatrixOutputs_lo_116}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_48_2 = &_cs_decoder_decoded_andMatrixOutputs_T_116; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_76 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_67}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_107 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_57}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_67 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_76}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_81 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_94, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_81}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_116 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_81, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_67}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_117 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_116, cs_decoder_decoded_andMatrixOutputs_lo_lo_107}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_57 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_114, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_107}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_78 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_117, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_116}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_114 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_78, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_57}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_71 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_117, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_117}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_94 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_117, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_117}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_117 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_94, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_71}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_117 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_117, cs_decoder_decoded_andMatrixOutputs_hi_lo_114}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_117 = {cs_decoder_decoded_andMatrixOutputs_hi_117, cs_decoder_decoded_andMatrixOutputs_lo_117}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_125_2 = &_cs_decoder_decoded_andMatrixOutputs_T_117; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_77 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_68}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_108 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_77, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_30}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_68 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_79, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_77}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_82 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_95, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_82}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_117 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_82, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_68}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_118 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_117, cs_decoder_decoded_andMatrixOutputs_lo_lo_108}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_58 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_115, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_108}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_79 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_118, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_117}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_115 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_79, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_58}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_72 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_118, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_118}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_95 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_118, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_118}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_118 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_95, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_72}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_118 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_118, cs_decoder_decoded_andMatrixOutputs_hi_lo_115}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_118 = {cs_decoder_decoded_andMatrixOutputs_hi_118, cs_decoder_decoded_andMatrixOutputs_lo_118}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_24_2 = &_cs_decoder_decoded_andMatrixOutputs_T_118; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_78 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_73, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_69}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_109 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_59}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_69 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_78}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_83 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_96, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_83}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_118 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_83, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_69}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_119 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_118, cs_decoder_decoded_andMatrixOutputs_lo_lo_109}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_59 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_116, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_109}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_80 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_119, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_118}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_116 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_80, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_59}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_73 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_119, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_119}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_96 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_119, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_119}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_119 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_96, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_73}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_119 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_119, cs_decoder_decoded_andMatrixOutputs_hi_lo_116}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_119 = {cs_decoder_decoded_andMatrixOutputs_hi_119, cs_decoder_decoded_andMatrixOutputs_lo_119}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_44_2 = &_cs_decoder_decoded_andMatrixOutputs_T_119; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_79 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_74, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_70}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_110 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_79, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_60}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_70 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_79}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_84 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_97, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_84}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_119 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_84, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_70}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_120 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_119, cs_decoder_decoded_andMatrixOutputs_lo_lo_110}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_60 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_117, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_110}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_81 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_120, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_119}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_117 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_81, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_60}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_74 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_120, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_120}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_97 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_120, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_120}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_120 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_97, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_74}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_120 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_120, cs_decoder_decoded_andMatrixOutputs_hi_lo_117}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_120 = {cs_decoder_decoded_andMatrixOutputs_hi_120, cs_decoder_decoded_andMatrixOutputs_lo_120}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_119_2 = &_cs_decoder_decoded_andMatrixOutputs_T_120; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_80 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_71}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_111 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_80, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_31}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_71 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_82, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_80}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_85 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_98, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_85}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_120 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_85, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_71}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_121 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_120, cs_decoder_decoded_andMatrixOutputs_lo_lo_111}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_61 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_118, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_111}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_82 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_121, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_120}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_118 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_82, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_61}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_75 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_121, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_121}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_98 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_121, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_121}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_121 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_98, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_75}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_121 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_121, cs_decoder_decoded_andMatrixOutputs_hi_lo_118}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_121 = {cs_decoder_decoded_andMatrixOutputs_hi_121, cs_decoder_decoded_andMatrixOutputs_lo_121}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_154_2 = &_cs_decoder_decoded_andMatrixOutputs_T_121; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_81 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_72}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_112 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_62}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_72 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_81}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_86 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_99, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_86}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_121 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_86, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_72}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_122 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_121, cs_decoder_decoded_andMatrixOutputs_lo_lo_112}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_62 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_119, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_112}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_83 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_122, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_121}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_119 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_83, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_62}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_76 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_122, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_122}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_99 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_122, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_122}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_122 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_99, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_76}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_122 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_122, cs_decoder_decoded_andMatrixOutputs_hi_lo_119}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_122 = {cs_decoder_decoded_andMatrixOutputs_hi_122, cs_decoder_decoded_andMatrixOutputs_lo_122}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_151_2 = &_cs_decoder_decoded_andMatrixOutputs_T_122; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_32}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_82 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_73}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_113 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_82, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_32}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_73 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_82}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_87 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_100, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_87}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_122 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_87, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_73}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_123 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_122, cs_decoder_decoded_andMatrixOutputs_lo_lo_113}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_63 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_120, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_113}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_84 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_123, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_122}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_120 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_84, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_63}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_77 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_123, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_123}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_100 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_123, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_123}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_123 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_100, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_77}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_123 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_123, cs_decoder_decoded_andMatrixOutputs_hi_lo_120}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_123 = {cs_decoder_decoded_andMatrixOutputs_hi_123, cs_decoder_decoded_andMatrixOutputs_lo_123}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_104_2 = &_cs_decoder_decoded_andMatrixOutputs_T_123; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_83 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_74}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_114 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_83, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_33}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_74 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_85, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_83}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_88 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_101, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_88}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_123 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_88, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_74}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_124 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_123, cs_decoder_decoded_andMatrixOutputs_lo_lo_114}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_64 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_121, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_114}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_85 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_124, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_123}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_121 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_85, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_64}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_78 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_124, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_124}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_101 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_124, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_124}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_124 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_101, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_78}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_124 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_124, cs_decoder_decoded_andMatrixOutputs_hi_lo_121}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_124 = {cs_decoder_decoded_andMatrixOutputs_hi_124, cs_decoder_decoded_andMatrixOutputs_lo_124}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_20_2 = &_cs_decoder_decoded_andMatrixOutputs_T_124; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_84 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_79, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_75}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_115 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_65}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_75 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_86, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_84}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_89 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_102, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_89}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_124 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_89, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_75}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_125 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_124, cs_decoder_decoded_andMatrixOutputs_lo_lo_115}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_65 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_122, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_115}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_86 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_125, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_124}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_122 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_86, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_65}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_79 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_125, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_125}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_102 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_125, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_125}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_125 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_102, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_79}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_125 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_125, cs_decoder_decoded_andMatrixOutputs_hi_lo_122}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_125 = {cs_decoder_decoded_andMatrixOutputs_hi_125, cs_decoder_decoded_andMatrixOutputs_lo_125}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_49_2 = &_cs_decoder_decoded_andMatrixOutputs_T_125; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_34 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_85 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_76}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_116 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_85, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_34}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_76 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_87, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_85}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_90 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_103, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_90}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_125 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_90, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_76}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_126 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_125, cs_decoder_decoded_andMatrixOutputs_lo_lo_116}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_66 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_123, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_116}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_87 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_126, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_125}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_123 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_87, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_66}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_80 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_126, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_126}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_103 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_126, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_126}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_126 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_103, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_80}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_126 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_126, cs_decoder_decoded_andMatrixOutputs_hi_lo_123}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_126 = {cs_decoder_decoded_andMatrixOutputs_hi_126, cs_decoder_decoded_andMatrixOutputs_lo_126}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_122_2 = &_cs_decoder_decoded_andMatrixOutputs_T_126; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_35 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_67, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_86 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_77}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_117 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_86, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_35}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_77 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_88, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_86}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_91 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_104, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_91}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_126 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_91, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_77}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_127 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_126, cs_decoder_decoded_andMatrixOutputs_lo_lo_117}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_67 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_124, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_117}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_88 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_127, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_126}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_124 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_88, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_67}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_81 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_127, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_127}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_104 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_127, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_127}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_127 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_104, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_81}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_127 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_127, cs_decoder_decoded_andMatrixOutputs_hi_lo_124}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_127 = {cs_decoder_decoded_andMatrixOutputs_hi_127, cs_decoder_decoded_andMatrixOutputs_lo_127}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_12_2 = &_cs_decoder_decoded_andMatrixOutputs_T_127; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_18}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_87 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_68}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_118 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_87, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_36}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_78 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_87, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_82}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_92 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_92, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_89}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_127 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_92, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_78}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_128 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_127, cs_decoder_decoded_andMatrixOutputs_lo_lo_118}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_68 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_118, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_105}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_89 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_127, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_125}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_125 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_89, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_68}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_82 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_128, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_128}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_128, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_128}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_105 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_128}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_128 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_105, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_82}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_128 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_128, cs_decoder_decoded_andMatrixOutputs_hi_lo_125}; // @[pla.scala:98:53] wire [16:0] _cs_decoder_decoded_andMatrixOutputs_T_128 = {cs_decoder_decoded_andMatrixOutputs_hi_128, cs_decoder_decoded_andMatrixOutputs_lo_128}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_41_2 = &_cs_decoder_decoded_andMatrixOutputs_T_128; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_37 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_88 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_69, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_37}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_119 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_88, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_37}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_79 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_79}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_93, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_90}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_93 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_88}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_128 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_93, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_79}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_lo_129 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_128, cs_decoder_decoded_andMatrixOutputs_lo_lo_119}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_69 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_119, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_106}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_90 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_128, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_126}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_126 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_90, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_69}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_83 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_129, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_129}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_129, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_129}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_106 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_129}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_129 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_106, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_83}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_129 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_129, cs_decoder_decoded_andMatrixOutputs_hi_lo_126}; // @[pla.scala:98:53] wire [17:0] _cs_decoder_decoded_andMatrixOutputs_T_129 = {cs_decoder_decoded_andMatrixOutputs_hi_129, cs_decoder_decoded_andMatrixOutputs_lo_129}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_152_2 = &_cs_decoder_decoded_andMatrixOutputs_T_129; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_38 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_89 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_20}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_120 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_89, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_38}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_80 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_70}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_89}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_94 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_84}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_129 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_94, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_80}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_lo_130 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_129, cs_decoder_decoded_andMatrixOutputs_lo_lo_120}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_70 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_107, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_94}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_129, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_127}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_91 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_120}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_127 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_91, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_70}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_84 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_130, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_130}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_130, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_130}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_107 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_130}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_130 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_107, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_84}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_hi_130 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_130, cs_decoder_decoded_andMatrixOutputs_hi_lo_127}; // @[pla.scala:98:53] wire [18:0] _cs_decoder_decoded_andMatrixOutputs_T_130 = {cs_decoder_decoded_andMatrixOutputs_hi_130, cs_decoder_decoded_andMatrixOutputs_lo_130}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_23_2 = &_cs_decoder_decoded_andMatrixOutputs_T_130; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_90 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_39}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_121 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_90, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_39}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_81 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_85, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_81}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_95, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_92}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_95 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_90}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_130 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_95, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_81}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_lo_131 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_130, cs_decoder_decoded_andMatrixOutputs_lo_lo_121}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_71 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_121, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_108}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_92 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_130, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_128}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_128 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_92, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_71}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_85 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_131, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_131}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_131, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_131}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_108 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_131}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_131 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_108, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_85}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_131 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_131, cs_decoder_decoded_andMatrixOutputs_hi_lo_128}; // @[pla.scala:98:53] wire [17:0] _cs_decoder_decoded_andMatrixOutputs_T_131 = {cs_decoder_decoded_andMatrixOutputs_hi_131, cs_decoder_decoded_andMatrixOutputs_lo_131}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_98_2 = &_cs_decoder_decoded_andMatrixOutputs_T_131; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_91 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_22}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_122 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_91, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_40}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_82 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_82, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_72}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_93, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_91}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_96 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_86}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_131 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_96, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_82}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_lo_132 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_131, cs_decoder_decoded_andMatrixOutputs_lo_lo_122}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_72 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_109, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_96}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_131, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_129}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_93 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_122}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_129 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_93, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_72}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_86 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_132, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_132}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_132, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_132}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_109 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_132}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_132 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_109, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_86}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_hi_132 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_132, cs_decoder_decoded_andMatrixOutputs_hi_lo_129}; // @[pla.scala:98:53] wire [18:0] _cs_decoder_decoded_andMatrixOutputs_T_132 = {cs_decoder_decoded_andMatrixOutputs_hi_132, cs_decoder_decoded_andMatrixOutputs_lo_132}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_15_2 = &_cs_decoder_decoded_andMatrixOutputs_T_132; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_92 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_87, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_83}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_123 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_92, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_73}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_83 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_94, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_92}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_97 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_110, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_97}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_132 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_97, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_83}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_133 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_132, cs_decoder_decoded_andMatrixOutputs_lo_lo_123}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_73 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_130, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_123}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_94 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_133, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_132}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_130 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_94, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_73}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_87 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_133, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_133}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_110 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_133, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_133}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_133 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_110, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_87}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_133 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_133, cs_decoder_decoded_andMatrixOutputs_hi_lo_130}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_133 = {cs_decoder_decoded_andMatrixOutputs_hi_133, cs_decoder_decoded_andMatrixOutputs_lo_133}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_36_2 = &_cs_decoder_decoded_andMatrixOutputs_T_133; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_41 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_74, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_41}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_93 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_88, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_84}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_124 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_93, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_41}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_84 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_95, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_93}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_98 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_111, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_98}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_133 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_98, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_84}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_134 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_133, cs_decoder_decoded_andMatrixOutputs_lo_lo_124}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_74 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_131, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_124}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_95 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_134, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_133}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_131 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_95, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_74}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_88 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_134, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_134}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_111 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_134, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_134}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_134 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_111, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_88}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_134 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_134, cs_decoder_decoded_andMatrixOutputs_hi_lo_131}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_134 = {cs_decoder_decoded_andMatrixOutputs_hi_134, cs_decoder_decoded_andMatrixOutputs_lo_134}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_46_2 = &_cs_decoder_decoded_andMatrixOutputs_T_134; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_42 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_94 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_89, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_85}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_125 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_94, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_42}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_85 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_96, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_94}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_99 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_112, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_99}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_134 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_99, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_85}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_135 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_134, cs_decoder_decoded_andMatrixOutputs_lo_lo_125}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_75 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_132, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_125}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_96 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_135, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_134}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_132 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_96, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_75}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_89 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_135, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_135}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_112 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_135, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_135}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_135 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_112, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_89}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_135 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_135, cs_decoder_decoded_andMatrixOutputs_hi_lo_132}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_135 = {cs_decoder_decoded_andMatrixOutputs_hi_135, cs_decoder_decoded_andMatrixOutputs_lo_135}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_55_2 = &_cs_decoder_decoded_andMatrixOutputs_T_135; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_43 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_95 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_86, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_76}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_126 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_95, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_43}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_86 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_95, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_90}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_100 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_100, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_97}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_135 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_100, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_86}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_136 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_135, cs_decoder_decoded_andMatrixOutputs_lo_lo_126}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_76 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_126, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_113}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_97 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_135, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_133}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_133 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_97, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_76}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_90 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_136, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_136}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_136, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_136}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_113 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_136}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_136 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_113, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_90}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_136 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_136, cs_decoder_decoded_andMatrixOutputs_hi_lo_133}; // @[pla.scala:98:53] wire [16:0] _cs_decoder_decoded_andMatrixOutputs_T_136 = {cs_decoder_decoded_andMatrixOutputs_hi_136, cs_decoder_decoded_andMatrixOutputs_lo_136}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_159_2 = &_cs_decoder_decoded_andMatrixOutputs_T_136; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_44 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_18}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_96 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_44}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_127 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_96, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_44}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_87 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_87}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_101, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_98}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_101 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_96}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_136 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_101, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_87}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_lo_137 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_136, cs_decoder_decoded_andMatrixOutputs_lo_lo_127}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_77 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_127, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_114}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_98 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_136, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_134}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_134 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_98, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_77}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_91 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_137, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_137}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_137, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_137}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_114 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_137}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_137 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_114, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_91}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_137 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_137, cs_decoder_decoded_andMatrixOutputs_hi_lo_134}; // @[pla.scala:98:53] wire [17:0] _cs_decoder_decoded_andMatrixOutputs_T_137 = {cs_decoder_decoded_andMatrixOutputs_hi_137, cs_decoder_decoded_andMatrixOutputs_lo_137}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_117_2 = &_cs_decoder_decoded_andMatrixOutputs_T_137; // @[pla.scala:98:{53,70}] wire _cs_decoder_decoded_orMatrixOutputs_T_2 = cs_decoder_decoded_andMatrixOutputs_117_2; // @[pla.scala:98:70, :114:36] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_45 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_97 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_128 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_97, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_45}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_88 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_88, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_78}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_99, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_97}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_102 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_92}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_137 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_102, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_88}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_lo_138 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_137, cs_decoder_decoded_andMatrixOutputs_lo_lo_128}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_78 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_115, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_102}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_137, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_135}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_99 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_128}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_135 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_99, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_78}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_92 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_138, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_138}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_138, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_138}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_115 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_138}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_138 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_115, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_92}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_hi_138 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_138, cs_decoder_decoded_andMatrixOutputs_hi_lo_135}; // @[pla.scala:98:53] wire [18:0] _cs_decoder_decoded_andMatrixOutputs_T_138 = {cs_decoder_decoded_andMatrixOutputs_hi_138, cs_decoder_decoded_andMatrixOutputs_lo_138}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_109_2 = &_cs_decoder_decoded_andMatrixOutputs_T_138; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_46 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_46, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_98 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_89, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_79}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_129 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_98, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_46}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_89 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_98, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_93}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_103 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_103, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_100}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_138 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_103, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_89}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_139 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_138, cs_decoder_decoded_andMatrixOutputs_lo_lo_129}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_79 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_129, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_116}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_100 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_138, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_136}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_136 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_100, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_79}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_93 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_139, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_139}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_139, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_139}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_116 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_139}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_139 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_116, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_93}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_139 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_139, cs_decoder_decoded_andMatrixOutputs_hi_lo_136}; // @[pla.scala:98:53] wire [16:0] _cs_decoder_decoded_andMatrixOutputs_T_139 = {cs_decoder_decoded_andMatrixOutputs_hi_139, cs_decoder_decoded_andMatrixOutputs_lo_139}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_128_2 = &_cs_decoder_decoded_andMatrixOutputs_T_139; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_47 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_27}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_99 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_90, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_80}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_130 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_99, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_47}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_90 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_99, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_94}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_104 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_104, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_101}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_139 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_104, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_90}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_140 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_139, cs_decoder_decoded_andMatrixOutputs_lo_lo_130}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_80 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_130, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_117}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_101 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_139, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_137}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_137 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_101, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_80}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_94 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_140, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_140}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_140, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_140}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_117 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_140}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_140 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_117, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_94}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_140 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_140, cs_decoder_decoded_andMatrixOutputs_hi_lo_137}; // @[pla.scala:98:53] wire [16:0] _cs_decoder_decoded_andMatrixOutputs_T_140 = {cs_decoder_decoded_andMatrixOutputs_hi_140, cs_decoder_decoded_andMatrixOutputs_lo_140}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_2_2 = &_cs_decoder_decoded_andMatrixOutputs_T_140; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_48 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_100 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_81}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_131 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_100, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_48}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_91 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_100, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_95}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_105 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_105, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_102}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_140 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_105, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_91}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_141 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_140, cs_decoder_decoded_andMatrixOutputs_lo_lo_131}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_81 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_131, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_118}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_102 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_140, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_138}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_138 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_102, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_81}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_95 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_141, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_141}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_141, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_141}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_118 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_141}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_141 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_118, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_95}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_141 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_141, cs_decoder_decoded_andMatrixOutputs_hi_lo_138}; // @[pla.scala:98:53] wire [16:0] _cs_decoder_decoded_andMatrixOutputs_T_141 = {cs_decoder_decoded_andMatrixOutputs_hi_141, cs_decoder_decoded_andMatrixOutputs_lo_141}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_83_2 = &_cs_decoder_decoded_andMatrixOutputs_T_141; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_49 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_49, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_29}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_101 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_20}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_132 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_101, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_49}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_92 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_92, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_82}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_103, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_101}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_106 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_96}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_141 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_106, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_92}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_lo_142 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_141, cs_decoder_decoded_andMatrixOutputs_lo_lo_132}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_82 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_119, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_106}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_141, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_139}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_103 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_132}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_139 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_103, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_82}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_96 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_142, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_142}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_142, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_142}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_119 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_142}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_142 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_119, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_96}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_hi_142 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_142, cs_decoder_decoded_andMatrixOutputs_hi_lo_139}; // @[pla.scala:98:53] wire [19:0] _cs_decoder_decoded_andMatrixOutputs_T_142 = {cs_decoder_decoded_andMatrixOutputs_hi_142, cs_decoder_decoded_andMatrixOutputs_lo_142}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_87_2 = &_cs_decoder_decoded_andMatrixOutputs_T_142; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_50 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_50, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_30}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_102 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_21}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_133 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_102, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_50}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_93 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_93, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_83}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_104, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_102}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_107 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_97}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_142 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_107, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_93}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_lo_143 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_142, cs_decoder_decoded_andMatrixOutputs_lo_lo_133}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_83 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_120, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_107}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_142, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_140}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_104 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_133}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_140 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_104, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_83}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_97 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_143, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_143}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_143, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_143}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_120 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_143}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_143 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_120, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_97}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_hi_143 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_143, cs_decoder_decoded_andMatrixOutputs_hi_lo_140}; // @[pla.scala:98:53] wire [19:0] _cs_decoder_decoded_andMatrixOutputs_T_143 = {cs_decoder_decoded_andMatrixOutputs_hi_143, cs_decoder_decoded_andMatrixOutputs_lo_143}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_158_2 = &_cs_decoder_decoded_andMatrixOutputs_T_143; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_51 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_22}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_103 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_19}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_134 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_103, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_51}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_94 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_51}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_103, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_98}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_108 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_94}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_143 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_108, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_94}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_lo_144 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_143, cs_decoder_decoded_andMatrixOutputs_lo_lo_134}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_84 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_108, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_105}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_141, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_134}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_105 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_121}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_141 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_105, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_84}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_144, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_144}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_98 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_143}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_144, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_144}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_121 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_144}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_144 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_121, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_98}; // @[pla.scala:98:53] wire [10:0] cs_decoder_decoded_andMatrixOutputs_hi_144 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_144, cs_decoder_decoded_andMatrixOutputs_hi_lo_141}; // @[pla.scala:98:53] wire [20:0] _cs_decoder_decoded_andMatrixOutputs_T_144 = {cs_decoder_decoded_andMatrixOutputs_hi_144, cs_decoder_decoded_andMatrixOutputs_lo_144}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_19_2 = &_cs_decoder_decoded_andMatrixOutputs_T_144; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_52 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_32}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_104 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_23}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_135 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_104, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_52}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_95 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_95, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_85}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_106, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_104}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_109 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_99}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_144 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_109, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_95}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_lo_145 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_144, cs_decoder_decoded_andMatrixOutputs_lo_lo_135}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_85 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_122, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_109}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_144, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_142}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_106 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_135}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_142 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_106, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_85}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_99 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_145, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_145}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_145, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_145}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_122 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_145}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_145 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_122, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_99}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_hi_145 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_145, cs_decoder_decoded_andMatrixOutputs_hi_lo_142}; // @[pla.scala:98:53] wire [19:0] _cs_decoder_decoded_andMatrixOutputs_T_145 = {cs_decoder_decoded_andMatrixOutputs_hi_145, cs_decoder_decoded_andMatrixOutputs_lo_145}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_91_2 = &_cs_decoder_decoded_andMatrixOutputs_T_145; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_105 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_100, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_96}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_136 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_105, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_86}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_96 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_107, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_105}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_110 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_123, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_110}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_145 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_110, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_96}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_146 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_145, cs_decoder_decoded_andMatrixOutputs_lo_lo_136}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_86 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_143, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_136}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_107 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_146, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_145}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_143 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_107, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_86}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_100 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_146, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_146}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_123 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_146, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_146}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_146 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_123, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_100}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_146 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_146, cs_decoder_decoded_andMatrixOutputs_hi_lo_143}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_146 = {cs_decoder_decoded_andMatrixOutputs_hi_146, cs_decoder_decoded_andMatrixOutputs_lo_146}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_70_2 = &_cs_decoder_decoded_andMatrixOutputs_T_146; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_53 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_87, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_53}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_106 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_101, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_97}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_137 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_106, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_53}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_97 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_108, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_106}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_111 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_124, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_111}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_146 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_111, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_97}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_147 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_146, cs_decoder_decoded_andMatrixOutputs_lo_lo_137}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_87 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_144, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_137}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_108 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_147, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_146}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_144 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_108, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_87}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_101 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_147, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_147}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_124 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_147, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_147}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_147 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_124, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_101}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_147 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_147, cs_decoder_decoded_andMatrixOutputs_hi_lo_144}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_147 = {cs_decoder_decoded_andMatrixOutputs_hi_147, cs_decoder_decoded_andMatrixOutputs_lo_147}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_53_2 = &_cs_decoder_decoded_andMatrixOutputs_T_147; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_54 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_88, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_54}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_107 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_102, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_98}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_138 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_107, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_54}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_98 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_109, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_107}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_112 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_125, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_112}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_147 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_112, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_98}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_148 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_147, cs_decoder_decoded_andMatrixOutputs_lo_lo_138}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_88 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_145, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_138}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_109 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_148, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_147}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_145 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_109, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_88}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_102 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_148, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_148}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_125 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_148, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_148}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_148 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_125, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_102}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_148 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_148, cs_decoder_decoded_andMatrixOutputs_hi_lo_145}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_148 = {cs_decoder_decoded_andMatrixOutputs_hi_148, cs_decoder_decoded_andMatrixOutputs_lo_148}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_126_2 = &_cs_decoder_decoded_andMatrixOutputs_T_148; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_55 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_89, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_55}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_108 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_103, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_99}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_139 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_108, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_55}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_99 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_110, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_108}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_113 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_126, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_113}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_148 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_113, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_99}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_149 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_148, cs_decoder_decoded_andMatrixOutputs_lo_lo_139}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_89 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_146, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_139}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_110 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_149, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_148}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_146 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_110, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_89}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_103 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_149, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_149}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_126 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_149, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_149}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_149 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_126, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_103}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_149 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_149, cs_decoder_decoded_andMatrixOutputs_hi_lo_146}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_149 = {cs_decoder_decoded_andMatrixOutputs_hi_149, cs_decoder_decoded_andMatrixOutputs_lo_149}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_150_2 = &_cs_decoder_decoded_andMatrixOutputs_T_149; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_56 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_90, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_109 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_104, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_100}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_140 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_109, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_56}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_100 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_111, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_109}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_114 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_127, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_114}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_149 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_114, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_100}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_150 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_149, cs_decoder_decoded_andMatrixOutputs_lo_lo_140}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_90 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_147, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_140}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_111 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_150, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_149}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_147 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_111, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_90}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_104 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_150, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_150}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_127 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_150, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_150}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_150 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_127, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_104}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_150 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_150, cs_decoder_decoded_andMatrixOutputs_hi_lo_147}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_150 = {cs_decoder_decoded_andMatrixOutputs_hi_150, cs_decoder_decoded_andMatrixOutputs_lo_150}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_31_2 = &_cs_decoder_decoded_andMatrixOutputs_T_150; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_101 = cs_decoder_decoded_plaInput[23]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_91 = cs_decoder_decoded_plaInput[24]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_22 = cs_decoder_decoded_plaInput[24]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_15 = cs_decoder_decoded_plaInput[24]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_11 = cs_decoder_decoded_plaInput[24]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_57 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_110 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_17}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_141 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_110, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_57}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_57}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_101 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_33}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_110, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_105}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_115 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_101}; // @[pla.scala:90:45, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_150 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_115, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_101}; // @[pla.scala:98:53] wire [10:0] cs_decoder_decoded_andMatrixOutputs_lo_151 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_150, cs_decoder_decoded_andMatrixOutputs_lo_lo_141}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_91 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_115, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_112}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_148, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_141}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_112 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_128}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_148 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_112, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_91}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_151, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_151}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_105 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_150}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_151, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_151}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_128 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_151}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_151 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_128, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_105}; // @[pla.scala:98:53] wire [10:0] cs_decoder_decoded_andMatrixOutputs_hi_151 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_151, cs_decoder_decoded_andMatrixOutputs_hi_lo_148}; // @[pla.scala:98:53] wire [21:0] _cs_decoder_decoded_andMatrixOutputs_T_151 = {cs_decoder_decoded_andMatrixOutputs_hi_151, cs_decoder_decoded_andMatrixOutputs_lo_151}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_106_2 = &_cs_decoder_decoded_andMatrixOutputs_T_151; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_9}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_58 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_9}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_111 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_9}; // @[pla.scala:90:45, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_142 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_111, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_58}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_102 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_18}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_102, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_92}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_116 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_25, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_9}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_151 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_116, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_102}; // @[pla.scala:98:53] wire [12:0] cs_decoder_decoded_andMatrixOutputs_lo_152 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_151, cs_decoder_decoded_andMatrixOutputs_lo_lo_142}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_113, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_111}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_92 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_106}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_142, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_129}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_113 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_116}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_149 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_113, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_92}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_152, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_151}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_106 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_149}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_152, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_152}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_34 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_152, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_152}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_129 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_34, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_9}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_152 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_129, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_106}; // @[pla.scala:98:53] wire [12:0] cs_decoder_decoded_andMatrixOutputs_hi_152 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_152, cs_decoder_decoded_andMatrixOutputs_hi_lo_149}; // @[pla.scala:98:53] wire [25:0] _cs_decoder_decoded_andMatrixOutputs_T_152 = {cs_decoder_decoded_andMatrixOutputs_hi_152, cs_decoder_decoded_andMatrixOutputs_lo_152}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_78_2 = &_cs_decoder_decoded_andMatrixOutputs_T_152; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_6}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_59 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_6}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_10}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_112 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_19, cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_6}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_143 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_112, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_59}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_19}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_103 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_15}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_93, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_59}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_117 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_26, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_10}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_152 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_117, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_103}; // @[pla.scala:98:53] wire [13:0] cs_decoder_decoded_andMatrixOutputs_lo_153 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_152, cs_decoder_decoded_andMatrixOutputs_lo_lo_143}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_112, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_107}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_93 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_103}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_117, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_114}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_143, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_130}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_114 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_23, cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_6}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_150 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_114, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_93}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_153, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_152}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_107 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_150}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_153, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_153}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_35 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_153, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_153}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_130 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_35, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_10}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_153 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_130, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_107}; // @[pla.scala:98:53] wire [13:0] cs_decoder_decoded_andMatrixOutputs_hi_153 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_153, cs_decoder_decoded_andMatrixOutputs_hi_lo_150}; // @[pla.scala:98:53] wire [27:0] _cs_decoder_decoded_andMatrixOutputs_T_153 = {cs_decoder_decoded_andMatrixOutputs_hi_153, cs_decoder_decoded_andMatrixOutputs_lo_153}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_64_2 = &_cs_decoder_decoded_andMatrixOutputs_T_153; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_30_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_31_1}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_28_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_29_3}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_60 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_11, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_11}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_113 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_20, cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_7}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_144 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_113, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_60}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_11}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_104 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_15, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_20}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_27}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_118 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_27, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_11}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_153 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_118, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_104}; // @[pla.scala:98:53] wire [15:0] cs_decoder_decoded_andMatrixOutputs_lo_154 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_153, cs_decoder_decoded_andMatrixOutputs_lo_lo_144}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_94, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_60}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_108, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_104}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_94 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_11, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_115, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_113}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_131, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_118}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_115 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_24, cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_7}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_151 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_115, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_94}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_151, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_144}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_154, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_153}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_108 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_16, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_154, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_154}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_154, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_154}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_131 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_36, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_11}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_154 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_131, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_108}; // @[pla.scala:98:53] wire [15:0] cs_decoder_decoded_andMatrixOutputs_hi_154 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_154, cs_decoder_decoded_andMatrixOutputs_hi_lo_151}; // @[pla.scala:98:53] wire [31:0] _cs_decoder_decoded_andMatrixOutputs_T_154 = {cs_decoder_decoded_andMatrixOutputs_hi_154, cs_decoder_decoded_andMatrixOutputs_lo_154}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_103_2 = &_cs_decoder_decoded_andMatrixOutputs_T_154; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_114 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_95 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_96 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_61 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_98 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_62 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_63 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_64 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_21 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_22 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_17 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_18 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_19 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_20 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_114 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_119, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_116}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_145 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_114, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_114}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_119 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_152, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_145}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_154 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_119, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_132}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_155 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_154, cs_decoder_decoded_andMatrixOutputs_lo_lo_145}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_116 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_155, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_155}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_152 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_116, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_154}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_132 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_155, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_155}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_155 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_132, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_155}; // @[pla.scala:90:45, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_155 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_155, cs_decoder_decoded_andMatrixOutputs_hi_lo_152}; // @[pla.scala:98:53] wire [11:0] _cs_decoder_decoded_andMatrixOutputs_T_155 = {cs_decoder_decoded_andMatrixOutputs_hi_155, cs_decoder_decoded_andMatrixOutputs_lo_155}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_147_2 = &_cs_decoder_decoded_andMatrixOutputs_T_155; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_115 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_109, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_105}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_146 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_115, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_95}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_105 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_117, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_115}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_120 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_133, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_120}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_155 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_120, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_105}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_156 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_155, cs_decoder_decoded_andMatrixOutputs_lo_lo_146}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_95 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_153, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_146}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_117 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_156, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_155}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_153 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_117, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_95}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_109 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_156, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_156}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_133 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_156, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_156}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_156 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_133, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_109}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_156 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_156, cs_decoder_decoded_andMatrixOutputs_hi_lo_153}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_156 = {cs_decoder_decoded_andMatrixOutputs_hi_156, cs_decoder_decoded_andMatrixOutputs_lo_156}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_142_2 = &_cs_decoder_decoded_andMatrixOutputs_T_156; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_116 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_110, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_106}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_147 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_116, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_96}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_106 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_118, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_116}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_121 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_134, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_121}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_156 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_121, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_106}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_157 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_156, cs_decoder_decoded_andMatrixOutputs_lo_lo_147}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_96 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_154, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_147}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_118 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_157, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_156}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_154 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_118, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_96}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_110 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_157, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_157}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_134 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_157, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_157}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_157 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_134, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_110}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_157 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_157, cs_decoder_decoded_andMatrixOutputs_hi_lo_154}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_157 = {cs_decoder_decoded_andMatrixOutputs_hi_157, cs_decoder_decoded_andMatrixOutputs_lo_157}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_130_2 = &_cs_decoder_decoded_andMatrixOutputs_T_157; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_61 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_97, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_61}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_117 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_111, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_107}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_148 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_117, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_61}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_107 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_119, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_117}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_122 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_135, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_122}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_157 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_122, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_107}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_158 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_157, cs_decoder_decoded_andMatrixOutputs_lo_lo_148}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_97 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_155, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_148}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_119 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_158, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_157}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_155 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_119, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_97}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_111 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_158, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_158}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_135 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_158, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_158}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_158 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_135, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_111}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_158 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_158, cs_decoder_decoded_andMatrixOutputs_hi_lo_155}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_158 = {cs_decoder_decoded_andMatrixOutputs_hi_158, cs_decoder_decoded_andMatrixOutputs_lo_158}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_32_2 = &_cs_decoder_decoded_andMatrixOutputs_T_158; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_118 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_112, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_108}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_149 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_118, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_98}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_108 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_120, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_118}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_123 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_136, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_123}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_158 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_123, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_108}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_159 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_158, cs_decoder_decoded_andMatrixOutputs_lo_lo_149}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_98 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_156, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_149}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_120 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_159, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_158}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_156 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_120, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_98}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_112 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_159, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_159}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_136 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_159, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_159}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_159 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_136, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_112}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_159 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_159, cs_decoder_decoded_andMatrixOutputs_hi_lo_156}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_159 = {cs_decoder_decoded_andMatrixOutputs_hi_159, cs_decoder_decoded_andMatrixOutputs_lo_159}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_94_2 = &_cs_decoder_decoded_andMatrixOutputs_T_159; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_62 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_99, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_62}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_119 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_113, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_109}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_150 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_119, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_62}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_109 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_121, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_119}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_124 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_137, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_124}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_159 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_124, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_109}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_160 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_159, cs_decoder_decoded_andMatrixOutputs_lo_lo_150}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_99 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_157, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_150}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_121 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_160, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_159}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_157 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_121, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_99}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_113 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_160, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_160}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_137 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_160, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_160}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_160 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_137, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_113}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_160 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_160, cs_decoder_decoded_andMatrixOutputs_hi_lo_157}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_160 = {cs_decoder_decoded_andMatrixOutputs_hi_160, cs_decoder_decoded_andMatrixOutputs_lo_160}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_84_2 = &_cs_decoder_decoded_andMatrixOutputs_T_160; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_63 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_100, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_63}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_120 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_114, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_110}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_151 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_120, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_63}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_110 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_122, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_120}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_125 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_138, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_125}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_160 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_125, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_110}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_161 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_160, cs_decoder_decoded_andMatrixOutputs_lo_lo_151}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_100 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_158, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_151}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_122 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_161, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_160}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_158 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_122, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_100}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_114 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_161, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_161}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_138 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_161, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_161}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_161 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_138, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_114}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_161 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_161, cs_decoder_decoded_andMatrixOutputs_hi_lo_158}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_161 = {cs_decoder_decoded_andMatrixOutputs_hi_161, cs_decoder_decoded_andMatrixOutputs_lo_161}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_101_2 = &_cs_decoder_decoded_andMatrixOutputs_T_161; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_64 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_101, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_64}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_121 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_115, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_111}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_152 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_121, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_64}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_111 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_123, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_121}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_126 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_139, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_126}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_161 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_126, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_111}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_162 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_161, cs_decoder_decoded_andMatrixOutputs_lo_lo_152}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_101 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_159, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_152}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_123 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_162, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_161}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_159 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_123, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_101}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_115 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_162, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_162}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_139 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_162, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_162}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_162 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_139, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_115}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_162 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_162, cs_decoder_decoded_andMatrixOutputs_hi_lo_159}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_162 = {cs_decoder_decoded_andMatrixOutputs_hi_162, cs_decoder_decoded_andMatrixOutputs_lo_162}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_132_2 = &_cs_decoder_decoded_andMatrixOutputs_T_162; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_65 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_21}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_65, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_37}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_122 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_28}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_153 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_122, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_65}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_112 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_112, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_102}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_124, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_122}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_127 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_116}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_162 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_127, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_112}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_lo_163 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_162, cs_decoder_decoded_andMatrixOutputs_lo_lo_153}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_102 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_140, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_127}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_162, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_160}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_124 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_153}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_160 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_124, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_102}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_116 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_163, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_163}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_37 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_163, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_163}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_140 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_163}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_163 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_140, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_116}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_hi_163 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_163, cs_decoder_decoded_andMatrixOutputs_hi_lo_160}; // @[pla.scala:98:53] wire [19:0] _cs_decoder_decoded_andMatrixOutputs_T_163 = {cs_decoder_decoded_andMatrixOutputs_hi_163, cs_decoder_decoded_andMatrixOutputs_lo_163}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_90_2 = &_cs_decoder_decoded_andMatrixOutputs_T_163; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_66 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_22}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_38}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_123 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_29}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_154 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_123, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_66}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_113 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_113, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_103}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_125, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_123}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_128 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_117}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_163 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_128, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_113}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_lo_164 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_163, cs_decoder_decoded_andMatrixOutputs_lo_lo_154}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_103 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_141, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_128}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_163, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_161}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_125 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_154}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_161 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_125, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_103}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_117 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_164, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_164}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_38 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_164, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_164}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_141 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_164}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_164 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_141, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_117}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_hi_164 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_164, cs_decoder_decoded_andMatrixOutputs_hi_lo_161}; // @[pla.scala:98:53] wire [19:0] _cs_decoder_decoded_andMatrixOutputs_T_164 = {cs_decoder_decoded_andMatrixOutputs_hi_164, cs_decoder_decoded_andMatrixOutputs_lo_164}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_27_2 = &_cs_decoder_decoded_andMatrixOutputs_T_164; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_67 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_17}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_30}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_124 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_27}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_155 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_124, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_67}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_114 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_104, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_67}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_124, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_118}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_129 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_114}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_164 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_129, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_114}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_lo_165 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_164, cs_decoder_decoded_andMatrixOutputs_lo_lo_155}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_104 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_129, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_126}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_162, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_155}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_126 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_142}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_162 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_126, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_104}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_165, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_165}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_118 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_164}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_165, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_165}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_142 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_165}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_165 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_142, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_118}; // @[pla.scala:98:53] wire [10:0] cs_decoder_decoded_andMatrixOutputs_hi_165 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_165, cs_decoder_decoded_andMatrixOutputs_hi_lo_162}; // @[pla.scala:98:53] wire [20:0] _cs_decoder_decoded_andMatrixOutputs_T_165 = {cs_decoder_decoded_andMatrixOutputs_hi_165, cs_decoder_decoded_andMatrixOutputs_lo_165}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_148_2 = &_cs_decoder_decoded_andMatrixOutputs_T_165; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_68 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_18}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_31}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_125 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_28}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_156 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_125, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_68}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_115 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_105, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_68}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_125, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_119}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_130 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_115}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_165 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_130, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_115}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_lo_166 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_165, cs_decoder_decoded_andMatrixOutputs_lo_lo_156}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_105 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_130, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_127}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_163, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_156}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_127 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_143}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_163 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_127, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_105}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_166, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_166}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_119 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_165}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_166, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_166}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_143 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_166}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_166 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_143, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_119}; // @[pla.scala:98:53] wire [10:0] cs_decoder_decoded_andMatrixOutputs_hi_166 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_166, cs_decoder_decoded_andMatrixOutputs_hi_lo_163}; // @[pla.scala:98:53] wire [20:0] _cs_decoder_decoded_andMatrixOutputs_T_166 = {cs_decoder_decoded_andMatrixOutputs_hi_166, cs_decoder_decoded_andMatrixOutputs_lo_166}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_67_2 = &_cs_decoder_decoded_andMatrixOutputs_T_166; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_69 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_19}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_32}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_126 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_29}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_157 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_126, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_69}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_116 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_106, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_69}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_126, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_120}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_131 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_116}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_166 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_131, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_116}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_lo_167 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_166, cs_decoder_decoded_andMatrixOutputs_lo_lo_157}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_106 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_131, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_128}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_164, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_157}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_128 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_144}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_164 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_128, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_106}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_167, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_167}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_120 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_166}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_41 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_167, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_167}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_144 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_167}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_167 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_144, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_120}; // @[pla.scala:98:53] wire [10:0] cs_decoder_decoded_andMatrixOutputs_hi_167 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_167, cs_decoder_decoded_andMatrixOutputs_hi_lo_164}; // @[pla.scala:98:53] wire [20:0] _cs_decoder_decoded_andMatrixOutputs_T_167 = {cs_decoder_decoded_andMatrixOutputs_hi_167, cs_decoder_decoded_andMatrixOutputs_lo_167}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_34_2 = &_cs_decoder_decoded_andMatrixOutputs_T_167; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_70 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_20}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_42, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_127 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_30}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_158 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_127, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_70}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_117 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_107, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_70}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_127, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_121}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_132 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_117}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_167 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_132, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_117}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_lo_168 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_167, cs_decoder_decoded_andMatrixOutputs_lo_lo_158}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_107 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_132, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_129}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_165, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_158}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_129 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_145}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_165 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_129, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_107}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_168, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_168}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_121 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_167}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_42 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_168, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_168}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_145 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_42, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_168}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_168 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_145, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_121}; // @[pla.scala:98:53] wire [10:0] cs_decoder_decoded_andMatrixOutputs_hi_168 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_168, cs_decoder_decoded_andMatrixOutputs_hi_lo_165}; // @[pla.scala:98:53] wire [20:0] _cs_decoder_decoded_andMatrixOutputs_T_168 = {cs_decoder_decoded_andMatrixOutputs_hi_168, cs_decoder_decoded_andMatrixOutputs_lo_168}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_59_2 = &_cs_decoder_decoded_andMatrixOutputs_T_168; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo = {cs_decoder_decoded_andMatrixOutputs_130_2, cs_decoder_decoded_andMatrixOutputs_94_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi = {cs_decoder_decoded_andMatrixOutputs_117_2, cs_decoder_decoded_andMatrixOutputs_142_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo = {cs_decoder_decoded_orMatrixOutputs_lo_hi, cs_decoder_decoded_orMatrixOutputs_lo_lo}; // @[pla.scala:114:19] wire [1:0] _GEN = {cs_decoder_decoded_andMatrixOutputs_152_2, cs_decoder_decoded_andMatrixOutputs_98_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo = _GEN; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_2; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_2 = _GEN; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_14; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_14 = _GEN; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_18; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_18 = _GEN; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_1 = _GEN; // @[pla.scala:114:19] wire [1:0] _GEN_0 = {cs_decoder_decoded_andMatrixOutputs_157_2, cs_decoder_decoded_andMatrixOutputs_21_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi = _GEN_0; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_3; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_3 = _GEN_0; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_3; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_3 = _GEN_0; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_18; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_18 = _GEN_0; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_15; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_15 = _GEN_0; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_139_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi = {cs_decoder_decoded_orMatrixOutputs_hi_hi, cs_decoder_decoded_orMatrixOutputs_hi_lo}; // @[pla.scala:114:19] wire [8:0] _cs_decoder_decoded_orMatrixOutputs_T = {cs_decoder_decoded_orMatrixOutputs_hi, cs_decoder_decoded_orMatrixOutputs_lo}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_1 = |_cs_decoder_decoded_orMatrixOutputs_T; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_1 = {cs_decoder_decoded_andMatrixOutputs_157_2, cs_decoder_decoded_andMatrixOutputs_145_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_1 = _GEN_1; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_27; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_27 = _GEN_1; // @[pla.scala:114:19] wire [2:0] _cs_decoder_decoded_orMatrixOutputs_T_4 = {cs_decoder_decoded_orMatrixOutputs_hi_1, cs_decoder_decoded_andMatrixOutputs_161_2}; // @[pla.scala:98:70, :114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_5 = |_cs_decoder_decoded_orMatrixOutputs_T_4; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_2 = {cs_decoder_decoded_andMatrixOutputs_23_2, cs_decoder_decoded_andMatrixOutputs_15_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_1 = _GEN_2; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_15; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_15 = _GEN_2; // @[pla.scala:114:19] wire [1:0] _GEN_3 = {cs_decoder_decoded_andMatrixOutputs_92_2, cs_decoder_decoded_andMatrixOutputs_40_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_2; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_2 = _GEN_3; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_17; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_17 = _GEN_3; // @[pla.scala:114:19] wire [3:0] _cs_decoder_decoded_orMatrixOutputs_T_6 = {cs_decoder_decoded_orMatrixOutputs_hi_2, cs_decoder_decoded_orMatrixOutputs_lo_1}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_7 = |_cs_decoder_decoded_orMatrixOutputs_T_6; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_4 = {cs_decoder_decoded_andMatrixOutputs_84_2, cs_decoder_decoded_andMatrixOutputs_27_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_2; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_2 = _GEN_4; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_3; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_3 = _GEN_4; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_15; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_15 = _GEN_4; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_33; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_33 = _GEN_4; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_3 = {cs_decoder_decoded_andMatrixOutputs_142_2, cs_decoder_decoded_andMatrixOutputs_130_2}; // @[pla.scala:98:70, :114:19] wire [3:0] _cs_decoder_decoded_orMatrixOutputs_T_8 = {cs_decoder_decoded_orMatrixOutputs_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_2}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_9 = |_cs_decoder_decoded_orMatrixOutputs_T_8; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_5 = {cs_decoder_decoded_andMatrixOutputs_132_2, cs_decoder_decoded_andMatrixOutputs_59_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _cs_decoder_decoded_orMatrixOutputs_T_10; // @[pla.scala:114:19] assign _cs_decoder_decoded_orMatrixOutputs_T_10 = _GEN_5; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_17; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_17 = _GEN_5; // @[pla.scala:114:19] wire [1:0] _cs_decoder_decoded_orMatrixOutputs_T_91; // @[pla.scala:114:19] assign _cs_decoder_decoded_orMatrixOutputs_T_91 = _GEN_5; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_11 = |_cs_decoder_decoded_orMatrixOutputs_T_10; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_34_2, cs_decoder_decoded_andMatrixOutputs_59_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi = {cs_decoder_decoded_andMatrixOutputs_98_2, cs_decoder_decoded_andMatrixOutputs_109_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_1 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_101_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_3 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_1, cs_decoder_decoded_orMatrixOutputs_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] _GEN_6 = {cs_decoder_decoded_andMatrixOutputs_11_2, cs_decoder_decoded_andMatrixOutputs_74_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_1 = _GEN_6; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_hi = _GEN_6; // @[pla.scala:114:19] wire [1:0] _GEN_7 = {cs_decoder_decoded_andMatrixOutputs_60_2, cs_decoder_decoded_andMatrixOutputs_69_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_1 = _GEN_7; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_2; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_2 = _GEN_7; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_1 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_68_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_4 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_hi_lo_1}; // @[pla.scala:114:19] wire [9:0] _cs_decoder_decoded_orMatrixOutputs_T_12 = {cs_decoder_decoded_orMatrixOutputs_hi_4, cs_decoder_decoded_orMatrixOutputs_lo_3}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_13 = |_cs_decoder_decoded_orMatrixOutputs_T_12; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_2 = {cs_decoder_decoded_andMatrixOutputs_67_2, cs_decoder_decoded_andMatrixOutputs_34_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_109_2, cs_decoder_decoded_andMatrixOutputs_101_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_2 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_148_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_4 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_2, cs_decoder_decoded_orMatrixOutputs_lo_lo_2}; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_2 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi, cs_decoder_decoded_andMatrixOutputs_23_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_2 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_68_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_5 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_hi_lo_2}; // @[pla.scala:114:19] wire [10:0] _cs_decoder_decoded_orMatrixOutputs_T_14 = {cs_decoder_decoded_orMatrixOutputs_hi_5, cs_decoder_decoded_orMatrixOutputs_lo_4}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_15 = |_cs_decoder_decoded_orMatrixOutputs_T_14; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_8 = {cs_decoder_decoded_andMatrixOutputs_115_2, cs_decoder_decoded_andMatrixOutputs_92_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_5; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_5 = _GEN_8; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_3; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_3 = _GEN_8; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_15; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_15 = _GEN_8; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_6 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_7_2}; // @[pla.scala:98:70, :114:19] wire [4:0] _cs_decoder_decoded_orMatrixOutputs_T_18 = {cs_decoder_decoded_orMatrixOutputs_hi_6, cs_decoder_decoded_orMatrixOutputs_lo_5}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_19 = |_cs_decoder_decoded_orMatrixOutputs_T_18; // @[pla.scala:114:{19,36}] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_3 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_117_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_6 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_lo_3}; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_4 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_7_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_7 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_4, cs_decoder_decoded_orMatrixOutputs_hi_lo_3}; // @[pla.scala:114:19] wire [9:0] _cs_decoder_decoded_orMatrixOutputs_T_20 = {cs_decoder_decoded_orMatrixOutputs_hi_7, cs_decoder_decoded_orMatrixOutputs_lo_6}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_21 = |_cs_decoder_decoded_orMatrixOutputs_T_20; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi = {cs_decoder_decoded_andMatrixOutputs_122_2, cs_decoder_decoded_andMatrixOutputs_41_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_4 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi, cs_decoder_decoded_andMatrixOutputs_126_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo = {cs_decoder_decoded_andMatrixOutputs_143_2, cs_decoder_decoded_andMatrixOutputs_119_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_121_2, cs_decoder_decoded_andMatrixOutputs_25_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_4 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_lo_7 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_4, cs_decoder_decoded_orMatrixOutputs_lo_lo_4}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo = {cs_decoder_decoded_andMatrixOutputs_124_2, cs_decoder_decoded_andMatrixOutputs_89_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_1 = {cs_decoder_decoded_andMatrixOutputs_75_2, cs_decoder_decoded_andMatrixOutputs_13_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_4 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_1, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo = {cs_decoder_decoded_andMatrixOutputs_86_2, cs_decoder_decoded_andMatrixOutputs_155_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_4 = {cs_decoder_decoded_andMatrixOutputs_102_2, cs_decoder_decoded_andMatrixOutputs_105_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_5 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_4, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo}; // @[pla.scala:114:19] wire [7:0] cs_decoder_decoded_orMatrixOutputs_hi_8 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_5, cs_decoder_decoded_orMatrixOutputs_hi_lo_4}; // @[pla.scala:114:19] wire [14:0] _cs_decoder_decoded_orMatrixOutputs_T_22 = {cs_decoder_decoded_orMatrixOutputs_hi_8, cs_decoder_decoded_orMatrixOutputs_lo_7}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_23 = |_cs_decoder_decoded_orMatrixOutputs_T_22; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo = {cs_decoder_decoded_andMatrixOutputs_49_2, cs_decoder_decoded_andMatrixOutputs_122_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_1 = {cs_decoder_decoded_andMatrixOutputs_119_2, cs_decoder_decoded_andMatrixOutputs_151_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_5 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_1, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_22_2, cs_decoder_decoded_andMatrixOutputs_44_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi = {cs_decoder_decoded_andMatrixOutputs_38_2, cs_decoder_decoded_andMatrixOutputs_4_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_4 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_5_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_5 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_4, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_1}; // @[pla.scala:114:19] wire [8:0] cs_decoder_decoded_orMatrixOutputs_lo_8 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_5, cs_decoder_decoded_orMatrixOutputs_lo_lo_5}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_57_2, cs_decoder_decoded_andMatrixOutputs_137_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi = {cs_decoder_decoded_andMatrixOutputs_149_2, cs_decoder_decoded_andMatrixOutputs_144_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_2 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_30_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_5 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_2, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_136_2, cs_decoder_decoded_andMatrixOutputs_96_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi = {cs_decoder_decoded_andMatrixOutputs_140_2, cs_decoder_decoded_andMatrixOutputs_33_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_5 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_1_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_6 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_5, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_1}; // @[pla.scala:114:19] wire [9:0] cs_decoder_decoded_orMatrixOutputs_hi_9 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_6, cs_decoder_decoded_orMatrixOutputs_hi_lo_5}; // @[pla.scala:114:19] wire [18:0] _cs_decoder_decoded_orMatrixOutputs_T_24 = {cs_decoder_decoded_orMatrixOutputs_hi_9, cs_decoder_decoded_orMatrixOutputs_lo_8}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_25 = |_cs_decoder_decoded_orMatrixOutputs_T_24; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_9 = {cs_decoder_decoded_andMatrixOutputs_156_2, cs_decoder_decoded_andMatrixOutputs_116_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_6; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_6 = _GEN_9; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi = _GEN_9; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_lo; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_lo = _GEN_9; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_5 = {cs_decoder_decoded_andMatrixOutputs_6_2, cs_decoder_decoded_andMatrixOutputs_35_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_6 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_9_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_9 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_6, cs_decoder_decoded_orMatrixOutputs_lo_lo_6}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_127_2, cs_decoder_decoded_andMatrixOutputs_135_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_6 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_3, cs_decoder_decoded_andMatrixOutputs_114_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_18_2, cs_decoder_decoded_andMatrixOutputs_113_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_7 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_39_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_10 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_7, cs_decoder_decoded_orMatrixOutputs_hi_lo_6}; // @[pla.scala:114:19] wire [10:0] _cs_decoder_decoded_orMatrixOutputs_T_26 = {cs_decoder_decoded_orMatrixOutputs_hi_10, cs_decoder_decoded_orMatrixOutputs_lo_9}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_27 = |_cs_decoder_decoded_orMatrixOutputs_T_26; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_7 = {cs_decoder_decoded_andMatrixOutputs_46_2, cs_decoder_decoded_andMatrixOutputs_159_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_125_2, cs_decoder_decoded_andMatrixOutputs_154_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_7 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_20_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_10 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_7, cs_decoder_decoded_orMatrixOutputs_lo_lo_7}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_4 = {cs_decoder_decoded_andMatrixOutputs_135_2, cs_decoder_decoded_andMatrixOutputs_37_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_7 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_22_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_7 = {cs_decoder_decoded_andMatrixOutputs_79_2, cs_decoder_decoded_andMatrixOutputs_111_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_8 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_42_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_11 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_8, cs_decoder_decoded_orMatrixOutputs_hi_lo_7}; // @[pla.scala:114:19] wire [10:0] _cs_decoder_decoded_orMatrixOutputs_T_28 = {cs_decoder_decoded_orMatrixOutputs_hi_11, cs_decoder_decoded_orMatrixOutputs_lo_10}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_29 = |_cs_decoder_decoded_orMatrixOutputs_T_28; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_150_2, cs_decoder_decoded_andMatrixOutputs_31_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_8 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_106_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_10 = {cs_decoder_decoded_andMatrixOutputs_91_2, cs_decoder_decoded_andMatrixOutputs_70_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_2; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_2 = _GEN_10; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi = _GEN_10; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_1 = _GEN_10; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_7 = {cs_decoder_decoded_andMatrixOutputs_87_2, cs_decoder_decoded_andMatrixOutputs_158_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_8 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_7, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_2}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_lo_11 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_8, cs_decoder_decoded_orMatrixOutputs_lo_lo_8}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_12_2, cs_decoder_decoded_andMatrixOutputs_36_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_8 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_55_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_2 = {cs_decoder_decoded_andMatrixOutputs_163_2, cs_decoder_decoded_andMatrixOutputs_24_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_8 = {cs_decoder_decoded_andMatrixOutputs_51_2, cs_decoder_decoded_andMatrixOutputs_37_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_9 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_8, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_2}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_hi_12 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_9, cs_decoder_decoded_orMatrixOutputs_hi_lo_8}; // @[pla.scala:114:19] wire [13:0] _cs_decoder_decoded_orMatrixOutputs_T_30 = {cs_decoder_decoded_orMatrixOutputs_hi_12, cs_decoder_decoded_orMatrixOutputs_lo_11}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_31 = |_cs_decoder_decoded_orMatrixOutputs_T_30; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo = {cs_decoder_decoded_andMatrixOutputs_106_2, cs_decoder_decoded_andMatrixOutputs_78_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi = {cs_decoder_decoded_andMatrixOutputs_19_2, cs_decoder_decoded_andMatrixOutputs_53_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_1 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo = {cs_decoder_decoded_andMatrixOutputs_55_2, cs_decoder_decoded_andMatrixOutputs_128_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi = {cs_decoder_decoded_andMatrixOutputs_44_2, cs_decoder_decoded_andMatrixOutputs_36_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_3 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo}; // @[pla.scala:114:19] wire [7:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_9 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] _GEN_11 = {cs_decoder_decoded_andMatrixOutputs_116_2, cs_decoder_decoded_andMatrixOutputs_163_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo = _GEN_11; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_5; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_5 = _GEN_11; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi = {cs_decoder_decoded_andMatrixOutputs_65_2, cs_decoder_decoded_andMatrixOutputs_156_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_3 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo = {cs_decoder_decoded_andMatrixOutputs_146_2, cs_decoder_decoded_andMatrixOutputs_66_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_35_2, cs_decoder_decoded_andMatrixOutputs_51_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_8 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo}; // @[pla.scala:114:19] wire [7:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_9 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_8, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_3}; // @[pla.scala:114:19] wire [15:0] cs_decoder_decoded_orMatrixOutputs_lo_12 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_9, cs_decoder_decoded_orMatrixOutputs_lo_lo_9}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo = {cs_decoder_decoded_andMatrixOutputs_165_2, cs_decoder_decoded_andMatrixOutputs_135_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi = {cs_decoder_decoded_andMatrixOutputs_131_2, cs_decoder_decoded_andMatrixOutputs_108_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_2 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo = {cs_decoder_decoded_andMatrixOutputs_18_2, cs_decoder_decoded_andMatrixOutputs_167_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_105_2, cs_decoder_decoded_andMatrixOutputs_76_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_6 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo}; // @[pla.scala:114:19] wire [7:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_9 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_6, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] _GEN_12 = {cs_decoder_decoded_andMatrixOutputs_112_2, cs_decoder_decoded_andMatrixOutputs_138_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo = _GEN_12; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_1 = _GEN_12; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi = {cs_decoder_decoded_andMatrixOutputs_8_2, cs_decoder_decoded_andMatrixOutputs_43_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_3 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo = {cs_decoder_decoded_andMatrixOutputs_29_2, cs_decoder_decoded_andMatrixOutputs_61_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_100_2, cs_decoder_decoded_andMatrixOutputs_62_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_9 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:114:19] wire [7:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_10 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_9, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_3}; // @[pla.scala:114:19] wire [15:0] cs_decoder_decoded_orMatrixOutputs_hi_13 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_10, cs_decoder_decoded_orMatrixOutputs_hi_lo_9}; // @[pla.scala:114:19] wire [31:0] _cs_decoder_decoded_orMatrixOutputs_T_32 = {cs_decoder_decoded_orMatrixOutputs_hi_13, cs_decoder_decoded_orMatrixOutputs_lo_12}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_33 = |_cs_decoder_decoded_orMatrixOutputs_T_32; // @[pla.scala:114:{19,36}] wire [1:0] _cs_decoder_decoded_orMatrixOutputs_T_35 = {cs_decoder_decoded_andMatrixOutputs_131_2, cs_decoder_decoded_andMatrixOutputs_16_2}; // @[pla.scala:98:70, :114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_36 = |_cs_decoder_decoded_orMatrixOutputs_T_35; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_10 = {cs_decoder_decoded_andMatrixOutputs_50_2, cs_decoder_decoded_andMatrixOutputs_134_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_13 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_10, cs_decoder_decoded_andMatrixOutputs_64_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_13 = {cs_decoder_decoded_andMatrixOutputs_47_2, cs_decoder_decoded_andMatrixOutputs_160_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_11; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_11 = _GEN_13; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_26; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_26 = _GEN_13; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_14 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_11, cs_decoder_decoded_andMatrixOutputs_131_2}; // @[pla.scala:98:70, :114:19] wire [5:0] _cs_decoder_decoded_orMatrixOutputs_T_37 = {cs_decoder_decoded_orMatrixOutputs_hi_14, cs_decoder_decoded_orMatrixOutputs_lo_13}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_38 = |_cs_decoder_decoded_orMatrixOutputs_T_37; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_10 = {cs_decoder_decoded_andMatrixOutputs_65_2, cs_decoder_decoded_andMatrixOutputs_64_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_14 = {cs_decoder_decoded_andMatrixOutputs_118_2, cs_decoder_decoded_andMatrixOutputs_50_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_9; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_9 = _GEN_14; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_1 = _GEN_14; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_11 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_134_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_14 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_11, cs_decoder_decoded_orMatrixOutputs_lo_lo_10}; // @[pla.scala:114:19] wire [1:0] _GEN_15 = {cs_decoder_decoded_andMatrixOutputs_17_2, cs_decoder_decoded_andMatrixOutputs_131_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_7; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_7 = _GEN_15; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_8; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_8 = _GEN_15; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_10 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_99_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_10 = {cs_decoder_decoded_andMatrixOutputs_100_2, cs_decoder_decoded_andMatrixOutputs_47_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_12 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_160_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_15 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_12, cs_decoder_decoded_orMatrixOutputs_hi_lo_10}; // @[pla.scala:114:19] wire [10:0] _cs_decoder_decoded_orMatrixOutputs_T_39 = {cs_decoder_decoded_orMatrixOutputs_hi_15, cs_decoder_decoded_orMatrixOutputs_lo_14}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_40 = |_cs_decoder_decoded_orMatrixOutputs_T_39; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_11 = {cs_decoder_decoded_andMatrixOutputs_95_2, cs_decoder_decoded_andMatrixOutputs_103_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_16 = {cs_decoder_decoded_andMatrixOutputs_58_2, cs_decoder_decoded_andMatrixOutputs_129_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_10; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_10 = _GEN_16; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_1 = _GEN_16; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_12 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_97_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_15 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_12, cs_decoder_decoded_orMatrixOutputs_lo_lo_11}; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_11 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_8, cs_decoder_decoded_andMatrixOutputs_99_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_11 = {cs_decoder_decoded_andMatrixOutputs_100_2, cs_decoder_decoded_andMatrixOutputs_71_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_13 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_11, cs_decoder_decoded_andMatrixOutputs_160_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_16 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_13, cs_decoder_decoded_orMatrixOutputs_hi_lo_11}; // @[pla.scala:114:19] wire [10:0] _cs_decoder_decoded_orMatrixOutputs_T_41 = {cs_decoder_decoded_orMatrixOutputs_hi_16, cs_decoder_decoded_orMatrixOutputs_lo_15}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_42 = |_cs_decoder_decoded_orMatrixOutputs_T_41; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_16 = {cs_decoder_decoded_andMatrixOutputs_54_2, cs_decoder_decoded_andMatrixOutputs_63_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_17 = {cs_decoder_decoded_andMatrixOutputs_110_2, cs_decoder_decoded_andMatrixOutputs_153_2}; // @[pla.scala:98:70, :114:19] wire [3:0] _cs_decoder_decoded_orMatrixOutputs_T_43 = {cs_decoder_decoded_orMatrixOutputs_hi_17, cs_decoder_decoded_orMatrixOutputs_lo_16}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_44 = |_cs_decoder_decoded_orMatrixOutputs_T_43; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_18 = {cs_decoder_decoded_andMatrixOutputs_118_2, cs_decoder_decoded_andMatrixOutputs_54_2}; // @[pla.scala:98:70, :114:19] wire [2:0] _cs_decoder_decoded_orMatrixOutputs_T_45 = {cs_decoder_decoded_orMatrixOutputs_hi_18, cs_decoder_decoded_andMatrixOutputs_48_2}; // @[pla.scala:98:70, :114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_46 = |_cs_decoder_decoded_orMatrixOutputs_T_45; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_17 = {cs_decoder_decoded_andMatrixOutputs_65_2, cs_decoder_decoded_andMatrixOutputs_147_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_19 = {cs_decoder_decoded_andMatrixOutputs_99_2, cs_decoder_decoded_andMatrixOutputs_118_2}; // @[pla.scala:98:70, :114:19] wire [3:0] _cs_decoder_decoded_orMatrixOutputs_T_47 = {cs_decoder_decoded_orMatrixOutputs_hi_19, cs_decoder_decoded_orMatrixOutputs_lo_17}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_48 = |_cs_decoder_decoded_orMatrixOutputs_T_47; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_17 = {cs_decoder_decoded_andMatrixOutputs_17_2, cs_decoder_decoded_andMatrixOutputs_99_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _cs_decoder_decoded_orMatrixOutputs_T_51; // @[pla.scala:114:19] assign _cs_decoder_decoded_orMatrixOutputs_T_51 = _GEN_17; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_18; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_18 = _GEN_17; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_23; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_23 = _GEN_17; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_52 = |_cs_decoder_decoded_orMatrixOutputs_T_51; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_14 = {cs_decoder_decoded_andMatrixOutputs_88_2, cs_decoder_decoded_andMatrixOutputs_110_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_20 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_153_2}; // @[pla.scala:98:70, :114:19] wire [4:0] _cs_decoder_decoded_orMatrixOutputs_T_53 = {cs_decoder_decoded_orMatrixOutputs_hi_20, cs_decoder_decoded_orMatrixOutputs_lo_18}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_54 = |_cs_decoder_decoded_orMatrixOutputs_T_53; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_19 = {cs_decoder_decoded_andMatrixOutputs_45_2, cs_decoder_decoded_andMatrixOutputs_118_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_18 = {cs_decoder_decoded_andMatrixOutputs_85_2, cs_decoder_decoded_andMatrixOutputs_10_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_21; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_21 = _GEN_18; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_25; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_25 = _GEN_18; // @[pla.scala:114:19] wire [3:0] _cs_decoder_decoded_orMatrixOutputs_T_55 = {cs_decoder_decoded_orMatrixOutputs_hi_21, cs_decoder_decoded_orMatrixOutputs_lo_19}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_56 = |_cs_decoder_decoded_orMatrixOutputs_T_55; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_13 = {cs_decoder_decoded_andMatrixOutputs_164_2, cs_decoder_decoded_andMatrixOutputs_133_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_20 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_13, cs_decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_15 = {cs_decoder_decoded_andMatrixOutputs_29_2, cs_decoder_decoded_andMatrixOutputs_110_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_22 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_153_2}; // @[pla.scala:98:70, :114:19] wire [5:0] _cs_decoder_decoded_orMatrixOutputs_T_57 = {cs_decoder_decoded_orMatrixOutputs_hi_22, cs_decoder_decoded_orMatrixOutputs_lo_20}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_58 = |_cs_decoder_decoded_orMatrixOutputs_T_57; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_19 = {cs_decoder_decoded_andMatrixOutputs_106_2, cs_decoder_decoded_andMatrixOutputs_103_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_1 = _GEN_19; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_2; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_2 = _GEN_19; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_lo; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_lo = _GEN_19; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_2 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_132_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_20 = {cs_decoder_decoded_andMatrixOutputs_158_2, cs_decoder_decoded_andMatrixOutputs_91_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_1 = _GEN_20; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_2; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_2 = _GEN_20; // @[pla.scala:114:19] wire [1:0] _GEN_21 = {cs_decoder_decoded_andMatrixOutputs_36_2, cs_decoder_decoded_andMatrixOutputs_87_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_1 = _GEN_21; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_2; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_2 = _GEN_21; // @[pla.scala:114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_4 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_1}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_12 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_4, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] _GEN_22 = {cs_decoder_decoded_andMatrixOutputs_163_2, cs_decoder_decoded_andMatrixOutputs_44_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_1 = _GEN_22; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_2; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_2 = _GEN_22; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_3; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_3 = _GEN_22; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_1 = _GEN_22; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_4 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_104_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_23 = {cs_decoder_decoded_andMatrixOutputs_97_2, cs_decoder_decoded_andMatrixOutputs_156_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_1 = _GEN_23; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_2; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_2 = _GEN_23; // @[pla.scala:114:19] wire [1:0] _GEN_24 = {cs_decoder_decoded_andMatrixOutputs_51_2, cs_decoder_decoded_andMatrixOutputs_129_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_2; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_2 = _GEN_24; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_3; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_3 = _GEN_24; // @[pla.scala:114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_11 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_1}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_14 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_11, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_4}; // @[pla.scala:114:19] wire [13:0] cs_decoder_decoded_orMatrixOutputs_lo_21 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_14, cs_decoder_decoded_orMatrixOutputs_lo_lo_12}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_1 = {cs_decoder_decoded_andMatrixOutputs_18_2, cs_decoder_decoded_andMatrixOutputs_131_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_3 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_25_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_160_2, cs_decoder_decoded_andMatrixOutputs_120_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_2 = {cs_decoder_decoded_andMatrixOutputs_52_2, cs_decoder_decoded_andMatrixOutputs_0_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_9 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_1}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_12 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_9, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] _GEN_25 = {cs_decoder_decoded_andMatrixOutputs_168_2, cs_decoder_decoded_andMatrixOutputs_138_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_1 = _GEN_25; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_3; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_3 = _GEN_25; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi = _GEN_25; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_4 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_71_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_26 = {cs_decoder_decoded_andMatrixOutputs_26_2, cs_decoder_decoded_andMatrixOutputs_77_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_1 = _GEN_26; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_2; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_2 = _GEN_26; // @[pla.scala:114:19] wire [1:0] _GEN_27 = {cs_decoder_decoded_andMatrixOutputs_81_2, cs_decoder_decoded_andMatrixOutputs_10_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_2; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_2 = _GEN_27; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_3; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_3 = _GEN_27; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi = _GEN_27; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_1 = _GEN_27; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_2; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_2 = _GEN_27; // @[pla.scala:114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_12 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_1}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_16 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_12, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_4}; // @[pla.scala:114:19] wire [13:0] cs_decoder_decoded_orMatrixOutputs_hi_23 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_16, cs_decoder_decoded_orMatrixOutputs_hi_lo_12}; // @[pla.scala:114:19] wire [27:0] _cs_decoder_decoded_orMatrixOutputs_T_59 = {cs_decoder_decoded_orMatrixOutputs_hi_23, cs_decoder_decoded_orMatrixOutputs_lo_21}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_60 = |_cs_decoder_decoded_orMatrixOutputs_T_59; // @[pla.scala:114:{19,36}] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_3 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_132_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_5 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_2}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_13 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_5, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_3}; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_5 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_104_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_12 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_2}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_15 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_12, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_5}; // @[pla.scala:114:19] wire [13:0] cs_decoder_decoded_orMatrixOutputs_lo_22 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_15, cs_decoder_decoded_orMatrixOutputs_lo_lo_13}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_131_2, cs_decoder_decoded_andMatrixOutputs_135_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_4 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_25_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_2 = {cs_decoder_decoded_andMatrixOutputs_120_2, cs_decoder_decoded_andMatrixOutputs_18_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_0_2, cs_decoder_decoded_andMatrixOutputs_76_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_10 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_3, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_2}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_13 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_10, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_4}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_71_2, cs_decoder_decoded_andMatrixOutputs_52_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_29_2, cs_decoder_decoded_andMatrixOutputs_112_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_5 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_2, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_1}; // @[pla.scala:114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_13 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_3, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_2}; // @[pla.scala:114:19] wire [7:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_17 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_13, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_5}; // @[pla.scala:114:19] wire [14:0] cs_decoder_decoded_orMatrixOutputs_hi_24 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_17, cs_decoder_decoded_orMatrixOutputs_hi_lo_13}; // @[pla.scala:114:19] wire [28:0] _cs_decoder_decoded_orMatrixOutputs_T_61 = {cs_decoder_decoded_orMatrixOutputs_hi_24, cs_decoder_decoded_orMatrixOutputs_lo_22}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_62 = |_cs_decoder_decoded_orMatrixOutputs_T_61; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_28 = {cs_decoder_decoded_andMatrixOutputs_7_2, cs_decoder_decoded_andMatrixOutputs_115_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_16; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_16 = _GEN_28; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_14; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_14 = _GEN_28; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_1 = _GEN_28; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_23 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_16, cs_decoder_decoded_andMatrixOutputs_92_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_25 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_18, cs_decoder_decoded_andMatrixOutputs_107_2}; // @[pla.scala:98:70, :114:19] wire [5:0] _cs_decoder_decoded_orMatrixOutputs_T_64 = {cs_decoder_decoded_orMatrixOutputs_hi_25, cs_decoder_decoded_orMatrixOutputs_lo_23}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_65 = |_cs_decoder_decoded_orMatrixOutputs_T_64; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_32_2, cs_decoder_decoded_andMatrixOutputs_94_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_106_2, cs_decoder_decoded_andMatrixOutputs_64_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_4 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_2_2, cs_decoder_decoded_andMatrixOutputs_83_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_117_2, cs_decoder_decoded_andMatrixOutputs_128_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_6 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_3}; // @[pla.scala:114:19] wire [7:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_14 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_6, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_4}; // @[pla.scala:114:19] wire [1:0] _GEN_29 = {cs_decoder_decoded_andMatrixOutputs_98_2, cs_decoder_decoded_andMatrixOutputs_36_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_1 = _GEN_29; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi = _GEN_29; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_104_2, cs_decoder_decoded_andMatrixOutputs_152_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_6 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_4 = {cs_decoder_decoded_andMatrixOutputs_134_2, cs_decoder_decoded_andMatrixOutputs_156_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_13 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_4, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_3}; // @[pla.scala:114:19] wire [7:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_17 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_13, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_6}; // @[pla.scala:114:19] wire [15:0] cs_decoder_decoded_orMatrixOutputs_lo_24 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_17, cs_decoder_decoded_orMatrixOutputs_lo_lo_14}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_131_2, cs_decoder_decoded_andMatrixOutputs_51_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_5 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_3, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_45_2, cs_decoder_decoded_andMatrixOutputs_18_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_4 = {cs_decoder_decoded_andMatrixOutputs_0_2, cs_decoder_decoded_andMatrixOutputs_160_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_11 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_4, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_3}; // @[pla.scala:114:19] wire [7:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_14 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_11, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_5}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_2 = {cs_decoder_decoded_andMatrixOutputs_47_2, cs_decoder_decoded_andMatrixOutputs_52_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_6 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_3, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] _GEN_30 = {cs_decoder_decoded_andMatrixOutputs_77_2, cs_decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_3; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_3 = _GEN_30; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_lo; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_lo = _GEN_30; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_1 = _GEN_30; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_4 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_100_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_14 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_4, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_3}; // @[pla.scala:114:19] wire [8:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_19 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_14, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_6}; // @[pla.scala:114:19] wire [16:0] cs_decoder_decoded_orMatrixOutputs_hi_26 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_19, cs_decoder_decoded_orMatrixOutputs_hi_lo_14}; // @[pla.scala:114:19] wire [32:0] _cs_decoder_decoded_orMatrixOutputs_T_66 = {cs_decoder_decoded_orMatrixOutputs_hi_26, cs_decoder_decoded_orMatrixOutputs_lo_24}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_67 = |_cs_decoder_decoded_orMatrixOutputs_T_66; // @[pla.scala:114:{19,36}] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_18 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_117_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_25 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_18, cs_decoder_decoded_orMatrixOutputs_lo_lo_15}; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_20 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_7_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_27 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_20, cs_decoder_decoded_orMatrixOutputs_hi_lo_15}; // @[pla.scala:114:19] wire [9:0] _cs_decoder_decoded_orMatrixOutputs_T_68 = {cs_decoder_decoded_orMatrixOutputs_hi_27, cs_decoder_decoded_orMatrixOutputs_lo_25}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_69 = |_cs_decoder_decoded_orMatrixOutputs_T_68; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_16 = {cs_decoder_decoded_andMatrixOutputs_134_2, cs_decoder_decoded_andMatrixOutputs_64_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_19 = {cs_decoder_decoded_andMatrixOutputs_3_2, cs_decoder_decoded_andMatrixOutputs_50_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_26 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_19, cs_decoder_decoded_orMatrixOutputs_lo_lo_16}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_16 = {cs_decoder_decoded_andMatrixOutputs_47_2, cs_decoder_decoded_andMatrixOutputs_72_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_16 = {cs_decoder_decoded_andMatrixOutputs_100_2, cs_decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_21 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_16, cs_decoder_decoded_andMatrixOutputs_138_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_28 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_21, cs_decoder_decoded_orMatrixOutputs_hi_lo_16}; // @[pla.scala:114:19] wire [8:0] _cs_decoder_decoded_orMatrixOutputs_T_70 = {cs_decoder_decoded_orMatrixOutputs_hi_28, cs_decoder_decoded_orMatrixOutputs_lo_26}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_71 = |_cs_decoder_decoded_orMatrixOutputs_T_70; // @[pla.scala:114:{19,36}] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_20 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_117_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_27 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_20, cs_decoder_decoded_orMatrixOutputs_lo_lo_17}; // @[pla.scala:114:19] wire [1:0] _GEN_31 = {cs_decoder_decoded_andMatrixOutputs_123_2, cs_decoder_decoded_andMatrixOutputs_21_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_17; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_17 = _GEN_31; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_20; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_20 = _GEN_31; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_lo; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_lo = _GEN_31; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_22 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_17, cs_decoder_decoded_andMatrixOutputs_73_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_29 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_22, cs_decoder_decoded_orMatrixOutputs_hi_lo_17}; // @[pla.scala:114:19] wire [9:0] _cs_decoder_decoded_orMatrixOutputs_T_72 = {cs_decoder_decoded_orMatrixOutputs_hi_29, cs_decoder_decoded_orMatrixOutputs_lo_27}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_73 = |_cs_decoder_decoded_orMatrixOutputs_T_72; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_32 = {cs_decoder_decoded_andMatrixOutputs_94_2, cs_decoder_decoded_andMatrixOutputs_90_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi = _GEN_32; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_9; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_9 = _GEN_32; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_1 = _GEN_32; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_2 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi, cs_decoder_decoded_andMatrixOutputs_27_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_4 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_106_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_5 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_4, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] _GEN_33 = {cs_decoder_decoded_andMatrixOutputs_117_2, cs_decoder_decoded_andMatrixOutputs_87_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi = _GEN_33; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_1 = _GEN_33; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_4 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi, cs_decoder_decoded_andMatrixOutputs_158_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_4 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_55_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_7 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_4, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_4}; // @[pla.scala:114:19] wire [11:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_18 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_7, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_5}; // @[pla.scala:114:19] wire [1:0] _GEN_34 = {cs_decoder_decoded_andMatrixOutputs_44_2, cs_decoder_decoded_andMatrixOutputs_151_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi = _GEN_34; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_3; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_3 = _GEN_34; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_2 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi, cs_decoder_decoded_andMatrixOutputs_152_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_4 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_163_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_7 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_4, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi = {cs_decoder_decoded_andMatrixOutputs_92_2, cs_decoder_decoded_andMatrixOutputs_133_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_4 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi, cs_decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi = {cs_decoder_decoded_andMatrixOutputs_58_2, cs_decoder_decoded_andMatrixOutputs_7_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_5 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_115_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_16 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_5, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_4}; // @[pla.scala:114:19] wire [11:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_21 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_16, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_7}; // @[pla.scala:114:19] wire [23:0] cs_decoder_decoded_orMatrixOutputs_lo_28 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_21, cs_decoder_decoded_orMatrixOutputs_lo_lo_18}; // @[pla.scala:114:19] wire [1:0] _GEN_35 = {cs_decoder_decoded_andMatrixOutputs_25_2, cs_decoder_decoded_andMatrixOutputs_99_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi = _GEN_35; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_1 = _GEN_35; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_2 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi, cs_decoder_decoded_andMatrixOutputs_51_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi = {cs_decoder_decoded_andMatrixOutputs_108_2, cs_decoder_decoded_andMatrixOutputs_35_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_4 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_9_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_6 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_4, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] _GEN_36 = {cs_decoder_decoded_andMatrixOutputs_18_2, cs_decoder_decoded_andMatrixOutputs_17_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi = _GEN_36; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_1 = _GEN_36; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_4 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi, cs_decoder_decoded_andMatrixOutputs_131_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi = {cs_decoder_decoded_andMatrixOutputs_86_2, cs_decoder_decoded_andMatrixOutputs_160_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_5 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_45_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_12 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_5, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_4}; // @[pla.scala:114:19] wire [11:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_18 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_12, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_6}; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_3 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi, cs_decoder_decoded_andMatrixOutputs_105_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi = {cs_decoder_decoded_andMatrixOutputs_56_2, cs_decoder_decoded_andMatrixOutputs_123_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_4 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_21_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_7 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_4, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] _GEN_37 = {cs_decoder_decoded_andMatrixOutputs_166_2, cs_decoder_decoded_andMatrixOutputs_8_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi = _GEN_37; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_lo; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_lo = _GEN_37; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_4 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi, cs_decoder_decoded_andMatrixOutputs_80_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_5 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_lo}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_18 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_5, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_4}; // @[pla.scala:114:19] wire [12:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_23 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_18, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_7}; // @[pla.scala:114:19] wire [24:0] cs_decoder_decoded_orMatrixOutputs_hi_30 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_23, cs_decoder_decoded_orMatrixOutputs_hi_lo_18}; // @[pla.scala:114:19] wire [48:0] _cs_decoder_decoded_orMatrixOutputs_T_74 = {cs_decoder_decoded_orMatrixOutputs_hi_30, cs_decoder_decoded_orMatrixOutputs_lo_28}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_75 = |_cs_decoder_decoded_orMatrixOutputs_T_74; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_83_2, cs_decoder_decoded_andMatrixOutputs_70_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_6 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_106_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_5 = {cs_decoder_decoded_andMatrixOutputs_128_2, cs_decoder_decoded_andMatrixOutputs_2_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_38 = {cs_decoder_decoded_andMatrixOutputs_36_2, cs_decoder_decoded_andMatrixOutputs_55_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_5; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_5 = _GEN_38; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_lo; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_lo = _GEN_38; // @[pla.scala:114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_8 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_5, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_5}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_19 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_8, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_6}; // @[pla.scala:114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_8 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_5, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_5 = {cs_decoder_decoded_andMatrixOutputs_28_2, cs_decoder_decoded_andMatrixOutputs_156_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_37_2, cs_decoder_decoded_andMatrixOutputs_133_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_17 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_6, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_5}; // @[pla.scala:114:19] wire [7:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_22 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_17, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_8}; // @[pla.scala:114:19] wire [14:0] cs_decoder_decoded_orMatrixOutputs_lo_29 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_22, cs_decoder_decoded_orMatrixOutputs_lo_lo_19}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_3 = {cs_decoder_decoded_andMatrixOutputs_25_2, cs_decoder_decoded_andMatrixOutputs_51_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_39 = {cs_decoder_decoded_andMatrixOutputs_108_2, cs_decoder_decoded_andMatrixOutputs_135_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_5; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_5 = _GEN_39; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_1 = _GEN_39; // @[pla.scala:114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_7 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_5, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_5 = {cs_decoder_decoded_andMatrixOutputs_86_2, cs_decoder_decoded_andMatrixOutputs_18_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_138_2, cs_decoder_decoded_andMatrixOutputs_52_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_13 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_6, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_5}; // @[pla.scala:114:19] wire [7:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_19 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_13, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_7}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_4 = {cs_decoder_decoded_andMatrixOutputs_79_2, cs_decoder_decoded_andMatrixOutputs_112_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_14_2, cs_decoder_decoded_andMatrixOutputs_56_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_8 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_5, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_4}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_5 = {cs_decoder_decoded_andMatrixOutputs_29_2, cs_decoder_decoded_andMatrixOutputs_166_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_62_2, cs_decoder_decoded_andMatrixOutputs_77_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_19 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_6, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_5}; // @[pla.scala:114:19] wire [7:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_24 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_19, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_8}; // @[pla.scala:114:19] wire [15:0] cs_decoder_decoded_orMatrixOutputs_hi_31 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_24, cs_decoder_decoded_orMatrixOutputs_hi_lo_19}; // @[pla.scala:114:19] wire [30:0] _cs_decoder_decoded_orMatrixOutputs_T_76 = {cs_decoder_decoded_orMatrixOutputs_hi_31, cs_decoder_decoded_orMatrixOutputs_lo_29}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_77 = |_cs_decoder_decoded_orMatrixOutputs_T_76; // @[pla.scala:114:{19,36}] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_30 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_23, cs_decoder_decoded_andMatrixOutputs_118_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_20 = {cs_decoder_decoded_andMatrixOutputs_26_2, cs_decoder_decoded_andMatrixOutputs_120_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_32 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_25, cs_decoder_decoded_orMatrixOutputs_hi_lo_20}; // @[pla.scala:114:19] wire [6:0] _cs_decoder_decoded_orMatrixOutputs_T_78 = {cs_decoder_decoded_orMatrixOutputs_hi_32, cs_decoder_decoded_orMatrixOutputs_lo_30}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_79 = |_cs_decoder_decoded_orMatrixOutputs_T_78; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_33 = {cs_decoder_decoded_andMatrixOutputs_110_2, cs_decoder_decoded_andMatrixOutputs_17_2}; // @[pla.scala:98:70, :114:19] wire [2:0] _cs_decoder_decoded_orMatrixOutputs_T_80 = {cs_decoder_decoded_orMatrixOutputs_hi_33, cs_decoder_decoded_andMatrixOutputs_99_2}; // @[pla.scala:98:70, :114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_81 = |_cs_decoder_decoded_orMatrixOutputs_T_80; // @[pla.scala:114:{19,36}] wire [1:0] _cs_decoder_decoded_orMatrixOutputs_T_82 = {cs_decoder_decoded_andMatrixOutputs_141_2, cs_decoder_decoded_andMatrixOutputs_93_2}; // @[pla.scala:98:70, :114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_83 = |_cs_decoder_decoded_orMatrixOutputs_T_82; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_24 = {cs_decoder_decoded_andMatrixOutputs_134_2, cs_decoder_decoded_andMatrixOutputs_65_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_31 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_24, cs_decoder_decoded_andMatrixOutputs_64_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_21 = {cs_decoder_decoded_andMatrixOutputs_131_2, cs_decoder_decoded_andMatrixOutputs_50_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_34 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_26, cs_decoder_decoded_orMatrixOutputs_hi_lo_21}; // @[pla.scala:114:19] wire [6:0] _cs_decoder_decoded_orMatrixOutputs_T_85 = {cs_decoder_decoded_orMatrixOutputs_hi_34, cs_decoder_decoded_orMatrixOutputs_lo_31}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_86 = |_cs_decoder_decoded_orMatrixOutputs_T_85; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_25 = {cs_decoder_decoded_andMatrixOutputs_40_2, cs_decoder_decoded_andMatrixOutputs_23_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_32 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_25, cs_decoder_decoded_andMatrixOutputs_15_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_22 = {cs_decoder_decoded_andMatrixOutputs_161_2, cs_decoder_decoded_andMatrixOutputs_92_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_35 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_27, cs_decoder_decoded_orMatrixOutputs_hi_lo_22}; // @[pla.scala:114:19] wire [6:0] _cs_decoder_decoded_orMatrixOutputs_T_87 = {cs_decoder_decoded_orMatrixOutputs_hi_35, cs_decoder_decoded_orMatrixOutputs_lo_32}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_88 = |_cs_decoder_decoded_orMatrixOutputs_T_87; // @[pla.scala:114:{19,36}] wire [1:0] _cs_decoder_decoded_orMatrixOutputs_T_89 = {cs_decoder_decoded_andMatrixOutputs_82_2, cs_decoder_decoded_andMatrixOutputs_117_2}; // @[pla.scala:98:70, :114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_90 = |_cs_decoder_decoded_orMatrixOutputs_T_89; // @[pla.scala:114:{19,36}] wire _cs_decoder_decoded_orMatrixOutputs_T_92 = |_cs_decoder_decoded_orMatrixOutputs_T_91; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_28 = {cs_decoder_decoded_andMatrixOutputs_107_2, cs_decoder_decoded_andMatrixOutputs_142_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_36 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_28, cs_decoder_decoded_andMatrixOutputs_130_2}; // @[pla.scala:98:70, :114:19] wire [4:0] _cs_decoder_decoded_orMatrixOutputs_T_93 = {cs_decoder_decoded_orMatrixOutputs_hi_36, cs_decoder_decoded_orMatrixOutputs_lo_33}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_94 = |_cs_decoder_decoded_orMatrixOutputs_T_93; // @[pla.scala:114:{19,36}] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_20 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_9, cs_decoder_decoded_andMatrixOutputs_27_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_26 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_18, cs_decoder_decoded_andMatrixOutputs_117_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_lo_34 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_26, cs_decoder_decoded_orMatrixOutputs_lo_lo_20}; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_23 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_14, cs_decoder_decoded_andMatrixOutputs_92_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_29 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_20, cs_decoder_decoded_andMatrixOutputs_162_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_37 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_29, cs_decoder_decoded_orMatrixOutputs_hi_lo_23}; // @[pla.scala:114:19] wire [11:0] _cs_decoder_decoded_orMatrixOutputs_T_95 = {cs_decoder_decoded_orMatrixOutputs_hi_37, cs_decoder_decoded_orMatrixOutputs_lo_34}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_96 = |_cs_decoder_decoded_orMatrixOutputs_T_95; // @[pla.scala:114:{19,36}] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_3 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_27_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_6 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_lo}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_7 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_6, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_3}; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_6 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_158_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_6 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_lo}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_10 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_6, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_6}; // @[pla.scala:114:19] wire [13:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_21 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_10, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_7}; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_4 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_151_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_133_2, cs_decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_6 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_lo}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_9 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_6, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_4}; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_6 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_92_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_lo = {cs_decoder_decoded_andMatrixOutputs_97_2, cs_decoder_decoded_andMatrixOutputs_95_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_7 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_lo}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_19 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_7, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_6}; // @[pla.scala:114:19] wire [13:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_27 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_19, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_9}; // @[pla.scala:114:19] wire [27:0] cs_decoder_decoded_orMatrixOutputs_lo_35 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_27, cs_decoder_decoded_orMatrixOutputs_lo_lo_21}; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_4 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_51_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_lo = {cs_decoder_decoded_andMatrixOutputs_35_2, cs_decoder_decoded_andMatrixOutputs_9_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_6 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_lo}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_8 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_6, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_4}; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_6 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_131_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_lo = {cs_decoder_decoded_andMatrixOutputs_76_2, cs_decoder_decoded_andMatrixOutputs_120_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_105_2, cs_decoder_decoded_andMatrixOutputs_86_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_7 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_lo}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_15 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_7, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_6}; // @[pla.scala:114:19] wire [13:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_24 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_15, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_8}; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_5 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_71_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_80_2, cs_decoder_decoded_andMatrixOutputs_56_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_6 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_lo}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_9 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_6, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_5}; // @[pla.scala:114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_6 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_1, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_lo}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_26_2, cs_decoder_decoded_andMatrixOutputs_100_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_7 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_1}; // @[pla.scala:114:19] wire [7:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_21 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_7, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_6}; // @[pla.scala:114:19] wire [14:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_30 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_21, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_9}; // @[pla.scala:114:19] wire [28:0] cs_decoder_decoded_orMatrixOutputs_hi_38 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_30, cs_decoder_decoded_orMatrixOutputs_hi_lo_24}; // @[pla.scala:114:19] wire [56:0] _cs_decoder_decoded_orMatrixOutputs_T_97 = {cs_decoder_decoded_orMatrixOutputs_hi_38, cs_decoder_decoded_orMatrixOutputs_lo_35}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_98 = |_cs_decoder_decoded_orMatrixOutputs_T_97; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_2 = {_cs_decoder_decoded_orMatrixOutputs_T_3, _cs_decoder_decoded_orMatrixOutputs_T_2}; // @[pla.scala:102:36, :114:36] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_4 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_2, _cs_decoder_decoded_orMatrixOutputs_T_1}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_1 = {_cs_decoder_decoded_orMatrixOutputs_T_7, _cs_decoder_decoded_orMatrixOutputs_T_5}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_2 = {_cs_decoder_decoded_orMatrixOutputs_T_11, _cs_decoder_decoded_orMatrixOutputs_T_9}; // @[pla.scala:102:36, :114:36] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_7 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_1}; // @[pla.scala:102:36] wire [6:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_8 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_7, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_4}; // @[pla.scala:102:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_2 = {_cs_decoder_decoded_orMatrixOutputs_T_16, _cs_decoder_decoded_orMatrixOutputs_T_15}; // @[pla.scala:102:36, :114:36] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_7 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_2, _cs_decoder_decoded_orMatrixOutputs_T_13}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_1 = {_cs_decoder_decoded_orMatrixOutputs_T_17, 1'h0}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_2 = {_cs_decoder_decoded_orMatrixOutputs_T_21, _cs_decoder_decoded_orMatrixOutputs_T_19}; // @[pla.scala:102:36, :114:36] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_7 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_1}; // @[pla.scala:102:36] wire [6:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_11 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_7, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_7}; // @[pla.scala:102:36] wire [13:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_22 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_11, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_8}; // @[pla.scala:102:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_2 = {_cs_decoder_decoded_orMatrixOutputs_T_23, 1'h0}; // @[pla.scala:102:36, :114:36] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_5 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_2, 1'h0}; // @[pla.scala:102:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_1 = {_cs_decoder_decoded_orMatrixOutputs_T_27, _cs_decoder_decoded_orMatrixOutputs_T_25}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_2 = {_cs_decoder_decoded_orMatrixOutputs_T_31, _cs_decoder_decoded_orMatrixOutputs_T_29}; // @[pla.scala:102:36, :114:36] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_7 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_1}; // @[pla.scala:102:36] wire [6:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_10 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_7, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_5}; // @[pla.scala:102:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_2 = {_cs_decoder_decoded_orMatrixOutputs_T_36, _cs_decoder_decoded_orMatrixOutputs_T_34}; // @[pla.scala:102:36, :114:36] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_7 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_2, _cs_decoder_decoded_orMatrixOutputs_T_33}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_1 = {_cs_decoder_decoded_orMatrixOutputs_T_40, _cs_decoder_decoded_orMatrixOutputs_T_38}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_2 = {_cs_decoder_decoded_orMatrixOutputs_T_44, _cs_decoder_decoded_orMatrixOutputs_T_42}; // @[pla.scala:102:36, :114:36] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_8 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_1}; // @[pla.scala:102:36] wire [6:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_20 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_8, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_7}; // @[pla.scala:102:36] wire [13:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_28 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_20, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_10}; // @[pla.scala:102:36] wire [27:0] cs_decoder_decoded_orMatrixOutputs_lo_36 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_28, cs_decoder_decoded_orMatrixOutputs_lo_lo_22}; // @[pla.scala:102:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_2 = {_cs_decoder_decoded_orMatrixOutputs_T_49, _cs_decoder_decoded_orMatrixOutputs_T_48}; // @[pla.scala:102:36, :114:36] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_5 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_2, _cs_decoder_decoded_orMatrixOutputs_T_46}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_1 = {_cs_decoder_decoded_orMatrixOutputs_T_52, _cs_decoder_decoded_orMatrixOutputs_T_50}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_2 = {_cs_decoder_decoded_orMatrixOutputs_T_56, _cs_decoder_decoded_orMatrixOutputs_T_54}; // @[pla.scala:102:36, :114:36] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_7 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_1}; // @[pla.scala:102:36] wire [6:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_9 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_7, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_5}; // @[pla.scala:102:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_2 = {_cs_decoder_decoded_orMatrixOutputs_T_62, _cs_decoder_decoded_orMatrixOutputs_T_60}; // @[pla.scala:102:36, :114:36] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_7 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_2, _cs_decoder_decoded_orMatrixOutputs_T_58}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_1 = {_cs_decoder_decoded_orMatrixOutputs_T_65, _cs_decoder_decoded_orMatrixOutputs_T_63}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_2 = {_cs_decoder_decoded_orMatrixOutputs_T_69, _cs_decoder_decoded_orMatrixOutputs_T_67}; // @[pla.scala:102:36, :114:36] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_8 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_1}; // @[pla.scala:102:36] wire [6:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_16 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_8, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_7}; // @[pla.scala:102:36] wire [13:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_25 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_16, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_9}; // @[pla.scala:102:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_2 = {_cs_decoder_decoded_orMatrixOutputs_T_75, _cs_decoder_decoded_orMatrixOutputs_T_73}; // @[pla.scala:102:36, :114:36] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_6 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_2, _cs_decoder_decoded_orMatrixOutputs_T_71}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_1 = {_cs_decoder_decoded_orMatrixOutputs_T_79, _cs_decoder_decoded_orMatrixOutputs_T_77}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_2 = {_cs_decoder_decoded_orMatrixOutputs_T_83, _cs_decoder_decoded_orMatrixOutputs_T_81}; // @[pla.scala:102:36, :114:36] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_7 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_1}; // @[pla.scala:102:36] wire [6:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_10 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_7, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_6}; // @[pla.scala:102:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_1 = {_cs_decoder_decoded_orMatrixOutputs_T_86, _cs_decoder_decoded_orMatrixOutputs_T_84}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_2 = {_cs_decoder_decoded_orMatrixOutputs_T_90, _cs_decoder_decoded_orMatrixOutputs_T_88}; // @[pla.scala:102:36, :114:36] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_7 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_2, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_1}; // @[pla.scala:102:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_2 = {_cs_decoder_decoded_orMatrixOutputs_T_94, _cs_decoder_decoded_orMatrixOutputs_T_92}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_3 = {_cs_decoder_decoded_orMatrixOutputs_T_98, _cs_decoder_decoded_orMatrixOutputs_T_96}; // @[pla.scala:102:36, :114:36] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_8 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_3, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_2}; // @[pla.scala:102:36] wire [7:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_22 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_8, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_7}; // @[pla.scala:102:36] wire [14:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_31 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_22, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_10}; // @[pla.scala:102:36] wire [28:0] cs_decoder_decoded_orMatrixOutputs_hi_39 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_31, cs_decoder_decoded_orMatrixOutputs_hi_lo_25}; // @[pla.scala:102:36] wire [56:0] cs_decoder_decoded_orMatrixOutputs = {cs_decoder_decoded_orMatrixOutputs_hi_39, cs_decoder_decoded_orMatrixOutputs_lo_36}; // @[pla.scala:102:36] wire _cs_decoder_decoded_invMatrixOutputs_T = cs_decoder_decoded_orMatrixOutputs[0]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_1 = cs_decoder_decoded_orMatrixOutputs[1]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_2 = cs_decoder_decoded_orMatrixOutputs[2]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_3 = cs_decoder_decoded_orMatrixOutputs[3]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_4 = cs_decoder_decoded_orMatrixOutputs[4]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_5 = cs_decoder_decoded_orMatrixOutputs[5]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_6 = cs_decoder_decoded_orMatrixOutputs[6]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_7 = cs_decoder_decoded_orMatrixOutputs[7]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_8 = cs_decoder_decoded_orMatrixOutputs[8]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_9 = cs_decoder_decoded_orMatrixOutputs[9]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_10 = cs_decoder_decoded_orMatrixOutputs[10]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_11 = cs_decoder_decoded_orMatrixOutputs[11]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_12 = cs_decoder_decoded_orMatrixOutputs[12]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_13 = cs_decoder_decoded_orMatrixOutputs[13]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_14 = cs_decoder_decoded_orMatrixOutputs[14]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_15 = cs_decoder_decoded_orMatrixOutputs[15]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_16 = cs_decoder_decoded_orMatrixOutputs[16]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_17 = cs_decoder_decoded_orMatrixOutputs[17]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_18 = cs_decoder_decoded_orMatrixOutputs[18]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_19 = cs_decoder_decoded_orMatrixOutputs[19]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_20 = cs_decoder_decoded_orMatrixOutputs[20]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_21 = cs_decoder_decoded_orMatrixOutputs[21]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_22 = cs_decoder_decoded_orMatrixOutputs[22]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_23 = cs_decoder_decoded_orMatrixOutputs[23]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_24 = cs_decoder_decoded_orMatrixOutputs[24]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_25 = cs_decoder_decoded_orMatrixOutputs[25]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_26 = cs_decoder_decoded_orMatrixOutputs[26]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_27 = cs_decoder_decoded_orMatrixOutputs[27]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_28 = cs_decoder_decoded_orMatrixOutputs[28]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_29 = cs_decoder_decoded_orMatrixOutputs[29]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_30 = cs_decoder_decoded_orMatrixOutputs[30]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_31 = cs_decoder_decoded_orMatrixOutputs[31]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_32 = cs_decoder_decoded_orMatrixOutputs[32]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_33 = cs_decoder_decoded_orMatrixOutputs[33]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_34 = cs_decoder_decoded_orMatrixOutputs[34]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_35 = cs_decoder_decoded_orMatrixOutputs[35]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_36 = cs_decoder_decoded_orMatrixOutputs[36]; // @[pla.scala:102:36, :123:56] wire _cs_decoder_decoded_invMatrixOutputs_T_37 = ~_cs_decoder_decoded_invMatrixOutputs_T_36; // @[pla.scala:123:{40,56}] wire _cs_decoder_decoded_invMatrixOutputs_T_38 = cs_decoder_decoded_orMatrixOutputs[37]; // @[pla.scala:102:36, :123:56] wire _cs_decoder_decoded_invMatrixOutputs_T_39 = ~_cs_decoder_decoded_invMatrixOutputs_T_38; // @[pla.scala:123:{40,56}] wire _cs_decoder_decoded_invMatrixOutputs_T_40 = cs_decoder_decoded_orMatrixOutputs[38]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_41 = cs_decoder_decoded_orMatrixOutputs[39]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_42 = cs_decoder_decoded_orMatrixOutputs[40]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_43 = cs_decoder_decoded_orMatrixOutputs[41]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_44 = cs_decoder_decoded_orMatrixOutputs[42]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_45 = cs_decoder_decoded_orMatrixOutputs[43]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_46 = cs_decoder_decoded_orMatrixOutputs[44]; // @[pla.scala:102:36, :123:56] wire _cs_decoder_decoded_invMatrixOutputs_T_47 = ~_cs_decoder_decoded_invMatrixOutputs_T_46; // @[pla.scala:123:{40,56}] wire _cs_decoder_decoded_invMatrixOutputs_T_48 = cs_decoder_decoded_orMatrixOutputs[45]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_49 = cs_decoder_decoded_orMatrixOutputs[46]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_50 = cs_decoder_decoded_orMatrixOutputs[47]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_51 = cs_decoder_decoded_orMatrixOutputs[48]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_52 = cs_decoder_decoded_orMatrixOutputs[49]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_53 = cs_decoder_decoded_orMatrixOutputs[50]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_54 = cs_decoder_decoded_orMatrixOutputs[51]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_55 = cs_decoder_decoded_orMatrixOutputs[52]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_56 = cs_decoder_decoded_orMatrixOutputs[53]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_57 = cs_decoder_decoded_orMatrixOutputs[54]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_58 = cs_decoder_decoded_orMatrixOutputs[55]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_59 = cs_decoder_decoded_orMatrixOutputs[56]; // @[pla.scala:102:36, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_lo_hi = {_cs_decoder_decoded_invMatrixOutputs_T_2, _cs_decoder_decoded_invMatrixOutputs_T_1}; // @[pla.scala:120:37, :124:31] wire [2:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_lo = {cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_lo_hi, _cs_decoder_decoded_invMatrixOutputs_T}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi_lo = {_cs_decoder_decoded_invMatrixOutputs_T_4, _cs_decoder_decoded_invMatrixOutputs_T_3}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi_hi = {_cs_decoder_decoded_invMatrixOutputs_T_6, _cs_decoder_decoded_invMatrixOutputs_T_5}; // @[pla.scala:120:37, :124:31] wire [3:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi = {cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi_hi, cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [6:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_lo = {cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi, cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_lo_hi = {_cs_decoder_decoded_invMatrixOutputs_T_9, _cs_decoder_decoded_invMatrixOutputs_T_8}; // @[pla.scala:120:37, :124:31] wire [2:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_lo = {cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_lo_hi, _cs_decoder_decoded_invMatrixOutputs_T_7}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi_lo = {_cs_decoder_decoded_invMatrixOutputs_T_11, _cs_decoder_decoded_invMatrixOutputs_T_10}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi_hi = {_cs_decoder_decoded_invMatrixOutputs_T_13, _cs_decoder_decoded_invMatrixOutputs_T_12}; // @[pla.scala:120:37, :124:31] wire [3:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi = {cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi_hi, cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [6:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_hi = {cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi, cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [13:0] cs_decoder_decoded_invMatrixOutputs_lo_lo = {cs_decoder_decoded_invMatrixOutputs_lo_lo_hi, cs_decoder_decoded_invMatrixOutputs_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_lo_hi = {_cs_decoder_decoded_invMatrixOutputs_T_16, _cs_decoder_decoded_invMatrixOutputs_T_15}; // @[pla.scala:120:37, :124:31] wire [2:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_lo = {cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_lo_hi, _cs_decoder_decoded_invMatrixOutputs_T_14}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi_lo = {_cs_decoder_decoded_invMatrixOutputs_T_18, _cs_decoder_decoded_invMatrixOutputs_T_17}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi_hi = {_cs_decoder_decoded_invMatrixOutputs_T_20, _cs_decoder_decoded_invMatrixOutputs_T_19}; // @[pla.scala:120:37, :124:31] wire [3:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi = {cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi_hi, cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [6:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_lo = {cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi, cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo_hi = {_cs_decoder_decoded_invMatrixOutputs_T_23, _cs_decoder_decoded_invMatrixOutputs_T_22}; // @[pla.scala:120:37, :124:31] wire [2:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo = {cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo_hi, _cs_decoder_decoded_invMatrixOutputs_T_21}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi_lo = {_cs_decoder_decoded_invMatrixOutputs_T_25, _cs_decoder_decoded_invMatrixOutputs_T_24}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi_hi = {_cs_decoder_decoded_invMatrixOutputs_T_27, _cs_decoder_decoded_invMatrixOutputs_T_26}; // @[pla.scala:120:37, :124:31] wire [3:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi = {cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi_hi, cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [6:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_hi = {cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi, cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [13:0] cs_decoder_decoded_invMatrixOutputs_lo_hi = {cs_decoder_decoded_invMatrixOutputs_lo_hi_hi, cs_decoder_decoded_invMatrixOutputs_lo_hi_lo}; // @[pla.scala:120:37] wire [27:0] cs_decoder_decoded_invMatrixOutputs_lo = {cs_decoder_decoded_invMatrixOutputs_lo_hi, cs_decoder_decoded_invMatrixOutputs_lo_lo}; // @[pla.scala:120:37] wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_lo_hi = {_cs_decoder_decoded_invMatrixOutputs_T_30, _cs_decoder_decoded_invMatrixOutputs_T_29}; // @[pla.scala:120:37, :124:31] wire [2:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_lo = {cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_lo_hi, _cs_decoder_decoded_invMatrixOutputs_T_28}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi_lo = {_cs_decoder_decoded_invMatrixOutputs_T_32, _cs_decoder_decoded_invMatrixOutputs_T_31}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi_hi = {_cs_decoder_decoded_invMatrixOutputs_T_34, _cs_decoder_decoded_invMatrixOutputs_T_33}; // @[pla.scala:120:37, :124:31] wire [3:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi = {cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi_hi, cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [6:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_lo = {cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi, cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_lo_hi = {_cs_decoder_decoded_invMatrixOutputs_T_39, _cs_decoder_decoded_invMatrixOutputs_T_37}; // @[pla.scala:120:37, :123:40] wire [2:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_lo = {cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_lo_hi, _cs_decoder_decoded_invMatrixOutputs_T_35}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi_lo = {_cs_decoder_decoded_invMatrixOutputs_T_41, _cs_decoder_decoded_invMatrixOutputs_T_40}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi_hi = {_cs_decoder_decoded_invMatrixOutputs_T_43, _cs_decoder_decoded_invMatrixOutputs_T_42}; // @[pla.scala:120:37, :124:31] wire [3:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi = {cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi_hi, cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [6:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_hi = {cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi, cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [13:0] cs_decoder_decoded_invMatrixOutputs_hi_lo = {cs_decoder_decoded_invMatrixOutputs_hi_lo_hi, cs_decoder_decoded_invMatrixOutputs_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_lo_hi = {_cs_decoder_decoded_invMatrixOutputs_T_47, _cs_decoder_decoded_invMatrixOutputs_T_45}; // @[pla.scala:120:37, :123:40, :124:31] wire [2:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_lo = {cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_lo_hi, _cs_decoder_decoded_invMatrixOutputs_T_44}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi_lo = {_cs_decoder_decoded_invMatrixOutputs_T_49, _cs_decoder_decoded_invMatrixOutputs_T_48}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi_hi = {_cs_decoder_decoded_invMatrixOutputs_T_51, _cs_decoder_decoded_invMatrixOutputs_T_50}; // @[pla.scala:120:37, :124:31] wire [3:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi = {cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi_hi, cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [6:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_lo = {cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi, cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo_lo = {_cs_decoder_decoded_invMatrixOutputs_T_53, _cs_decoder_decoded_invMatrixOutputs_T_52}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo_hi = {_cs_decoder_decoded_invMatrixOutputs_T_55, _cs_decoder_decoded_invMatrixOutputs_T_54}; // @[pla.scala:120:37, :124:31] wire [3:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo = {cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo_hi, cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi_lo = {_cs_decoder_decoded_invMatrixOutputs_T_57, _cs_decoder_decoded_invMatrixOutputs_T_56}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi_hi = {_cs_decoder_decoded_invMatrixOutputs_T_59, _cs_decoder_decoded_invMatrixOutputs_T_58}; // @[pla.scala:120:37, :124:31] wire [3:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi = {cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi_hi, cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [7:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_hi = {cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi, cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [14:0] cs_decoder_decoded_invMatrixOutputs_hi_hi = {cs_decoder_decoded_invMatrixOutputs_hi_hi_hi, cs_decoder_decoded_invMatrixOutputs_hi_hi_lo}; // @[pla.scala:120:37] wire [28:0] cs_decoder_decoded_invMatrixOutputs_hi = {cs_decoder_decoded_invMatrixOutputs_hi_hi, cs_decoder_decoded_invMatrixOutputs_hi_lo}; // @[pla.scala:120:37] assign cs_decoder_decoded_invMatrixOutputs = {cs_decoder_decoded_invMatrixOutputs_hi, cs_decoder_decoded_invMatrixOutputs_lo}; // @[pla.scala:120:37] assign cs_decoder_decoded = cs_decoder_decoded_invMatrixOutputs; // @[pla.scala:81:23, :120:37] assign cs_decoder_0 = cs_decoder_decoded[56]; // @[pla.scala:81:23] assign cs_legal = cs_decoder_0; // @[Decode.scala:50:77] assign cs_decoder_1 = cs_decoder_decoded[55]; // @[pla.scala:81:23] assign cs_fp_val = cs_decoder_1; // @[Decode.scala:50:77] assign cs_decoder_2 = cs_decoder_decoded[54:45]; // @[pla.scala:81:23] assign cs_fu_code = cs_decoder_2; // @[Decode.scala:50:77] assign cs_decoder_3 = cs_decoder_decoded[44:43]; // @[pla.scala:81:23] assign cs_dst_type = cs_decoder_3; // @[Decode.scala:50:77] assign cs_decoder_4 = cs_decoder_decoded[42:41]; // @[pla.scala:81:23] assign cs_rs1_type = cs_decoder_4; // @[Decode.scala:50:77] assign cs_decoder_5 = cs_decoder_decoded[40:39]; // @[pla.scala:81:23] assign cs_rs2_type = cs_decoder_5; // @[Decode.scala:50:77] assign cs_decoder_6 = cs_decoder_decoded[38]; // @[pla.scala:81:23] assign cs_frs3_en = cs_decoder_6; // @[Decode.scala:50:77] assign cs_decoder_7 = cs_decoder_decoded[37:35]; // @[pla.scala:81:23] assign cs_imm_sel = cs_decoder_7; // @[Decode.scala:50:77] assign cs_decoder_8 = cs_decoder_decoded[34]; // @[pla.scala:81:23] assign cs_uses_ldq = cs_decoder_8; // @[Decode.scala:50:77] assign cs_decoder_9 = cs_decoder_decoded[33]; // @[pla.scala:81:23] assign cs_uses_stq = cs_decoder_9; // @[Decode.scala:50:77] assign cs_decoder_10 = cs_decoder_decoded[32]; // @[pla.scala:81:23] assign cs_is_amo = cs_decoder_10; // @[Decode.scala:50:77] assign cs_decoder_11 = cs_decoder_decoded[31:27]; // @[pla.scala:81:23] assign cs_mem_cmd = cs_decoder_11; // @[Decode.scala:50:77] assign cs_decoder_12 = cs_decoder_decoded[26]; // @[pla.scala:81:23] assign cs_inst_unique = cs_decoder_12; // @[Decode.scala:50:77] assign cs_decoder_13 = cs_decoder_decoded[25]; // @[pla.scala:81:23] assign cs_flush_on_commit = cs_decoder_13; // @[Decode.scala:50:77] assign cs_decoder_14 = cs_decoder_decoded[24:22]; // @[pla.scala:81:23] assign cs_csr_cmd = cs_decoder_14; // @[Decode.scala:50:77] assign cs_decoder_15 = cs_decoder_decoded[21]; // @[pla.scala:81:23] assign cs_fcn_dw = cs_decoder_15; // @[Decode.scala:50:77] assign cs_decoder_16 = cs_decoder_decoded[20:16]; // @[pla.scala:81:23] assign cs_fcn_op = cs_decoder_16; // @[Decode.scala:50:77] assign cs_decoder_17 = cs_decoder_decoded[15]; // @[pla.scala:81:23] assign cs_fp_ldst = cs_decoder_17; // @[Decode.scala:50:77] assign cs_decoder_18 = cs_decoder_decoded[14]; // @[pla.scala:81:23] assign cs_fp_wen = cs_decoder_18; // @[Decode.scala:50:77] assign cs_decoder_19 = cs_decoder_decoded[13]; // @[pla.scala:81:23] assign cs_fp_ren1 = cs_decoder_19; // @[Decode.scala:50:77] assign cs_decoder_20 = cs_decoder_decoded[12]; // @[pla.scala:81:23] assign cs_fp_ren2 = cs_decoder_20; // @[Decode.scala:50:77] assign cs_decoder_21 = cs_decoder_decoded[11]; // @[pla.scala:81:23] assign cs_fp_ren3 = cs_decoder_21; // @[Decode.scala:50:77] assign cs_decoder_22 = cs_decoder_decoded[10]; // @[pla.scala:81:23] assign cs_fp_swap12 = cs_decoder_22; // @[Decode.scala:50:77] assign cs_decoder_23 = cs_decoder_decoded[9]; // @[pla.scala:81:23] assign cs_fp_swap23 = cs_decoder_23; // @[Decode.scala:50:77] wire cs_decoder_24 = cs_decoder_decoded[8]; // @[pla.scala:81:23] wire cs_decoder_25 = cs_decoder_decoded[7]; // @[pla.scala:81:23] assign cs_decoder_26 = cs_decoder_decoded[6]; // @[pla.scala:81:23] assign cs_fp_fromint = cs_decoder_26; // @[Decode.scala:50:77] assign cs_decoder_27 = cs_decoder_decoded[5]; // @[pla.scala:81:23] assign cs_fp_toint = cs_decoder_27; // @[Decode.scala:50:77] assign cs_decoder_28 = cs_decoder_decoded[4]; // @[pla.scala:81:23] assign cs_fp_fastpipe = cs_decoder_28; // @[Decode.scala:50:77] assign cs_decoder_29 = cs_decoder_decoded[3]; // @[pla.scala:81:23] assign cs_fp_fma = cs_decoder_29; // @[Decode.scala:50:77] assign cs_decoder_30 = cs_decoder_decoded[2]; // @[pla.scala:81:23] assign cs_fp_div = cs_decoder_30; // @[Decode.scala:50:77] assign cs_decoder_31 = cs_decoder_decoded[1]; // @[pla.scala:81:23] assign cs_fp_sqrt = cs_decoder_31; // @[Decode.scala:50:77] assign cs_decoder_32 = cs_decoder_decoded[0]; // @[pla.scala:81:23] assign cs_fp_wflags = cs_decoder_32; // @[Decode.scala:50:77] assign cs_fp_typeTagIn = {1'h0, cs_decoder_24}; // @[Decode.scala:50:77] assign cs_fp_typeTagOut = {1'h0, cs_decoder_25}; // @[Decode.scala:50:77] wire _T_29 = cs_csr_cmd == 3'h6; // @[package.scala:16:47] wire _csr_en_T; // @[package.scala:16:47] assign _csr_en_T = _T_29; // @[package.scala:16:47] wire _csr_ren_T; // @[package.scala:16:47] assign _csr_ren_T = _T_29; // @[package.scala:16:47] wire _csr_en_T_1 = &cs_csr_cmd; // @[package.scala:16:47] wire _csr_en_T_2 = cs_csr_cmd == 3'h5; // @[package.scala:16:47] wire _csr_en_T_3 = _csr_en_T | _csr_en_T_1; // @[package.scala:16:47, :81:59] wire csr_en = _csr_en_T_3 | _csr_en_T_2; // @[package.scala:16:47, :81:59] wire _csr_ren_T_1 = &cs_csr_cmd; // @[package.scala:16:47] wire _csr_ren_T_2 = _csr_ren_T | _csr_ren_T_1; // @[package.scala:16:47, :81:59] wire _csr_ren_T_3 = uop_lrs1 == 6'h0; // @[decode.scala:422:7, :426:14, :428:17, :452:62] wire csr_ren = _csr_ren_T_2 & _csr_ren_T_3; // @[package.scala:81:59] wire system_insn = cs_csr_cmd == 3'h4; // @[decode.scala:447:16, :453:32] wire [31:0] _GEN_40 = uop_inst & 32'hFE007FFF; // @[decode.scala:428:17, :454:21] wire [31:0] _sfence_T; // @[decode.scala:454:21] assign _sfence_T = _GEN_40; // @[decode.scala:454:21] wire [31:0] _uop_is_sfence_T; // @[decode.scala:528:26] assign _uop_is_sfence_T = _GEN_40; // @[decode.scala:454:21, :528:26] wire sfence = _sfence_T == 32'h12000073; // @[decode.scala:454:21] wire [2:0] _illegal_rm_T = uop_inst[14:12]; // @[decode.scala:428:17, :460:24] wire [2:0] _illegal_rm_T_4 = uop_inst[14:12]; // @[decode.scala:428:17, :460:{24,57}] wire [2:0] _uop_is_rocc_T_6 = uop_inst[14:12]; // @[decode.scala:428:17, :460:24, :532:88] wire [2:0] _uop_pimm_T_1 = uop_inst[14:12]; // @[decode.scala:428:17, :460:24, :553:47] wire [2:0] _uop_fp_rm_T = uop_inst[14:12]; // @[decode.scala:428:17, :460:24, :556:26] wire [2:0] _uop_fp_rm_T_2 = uop_inst[14:12]; // @[decode.scala:428:17, :460:24, :556:59] wire _illegal_rm_T_1 = _illegal_rm_T == 3'h5; // @[package.scala:16:47] wire _illegal_rm_T_2 = _illegal_rm_T == 3'h6; // @[package.scala:16:47] wire _illegal_rm_T_3 = _illegal_rm_T_1 | _illegal_rm_T_2; // @[package.scala:16:47, :81:59] wire _illegal_rm_T_5 = &_illegal_rm_T_4; // @[decode.scala:460:{57,65}] wire _illegal_rm_T_6 = io_fcsr_rm_0 > 3'h4; // @[decode.scala:422:7, :460:87] wire _illegal_rm_T_7 = _illegal_rm_T_5 & _illegal_rm_T_6; // @[decode.scala:460:{65,73,87}] wire illegal_rm = _illegal_rm_T_3 | _illegal_rm_T_7; // @[package.scala:81:59] wire _id_illegal_insn_T = ~cs_legal; // @[decode.scala:447:16, :461:26] wire _id_illegal_insn_T_1 = io_csr_decode_fp_illegal_0 | illegal_rm; // @[decode.scala:422:7, :460:49, :462:45] wire _id_illegal_insn_T_2 = cs_fp_val & _id_illegal_insn_T_1; // @[decode.scala:447:16, :462:{16,45}] wire _id_illegal_insn_T_3 = _id_illegal_insn_T | _id_illegal_insn_T_2; // @[decode.scala:461:{26,36}, :462:16] wire _id_illegal_insn_T_5 = _id_illegal_insn_T_3 | _id_illegal_insn_T_4; // @[decode.scala:461:36, :462:61, :463:18] wire _id_illegal_insn_T_9 = _id_illegal_insn_T_5; // @[decode.scala:462:61, :463:49] wire _id_illegal_insn_T_10 = ~csr_ren; // @[decode.scala:452:50, :465:47] wire _id_illegal_insn_T_11 = _id_illegal_insn_T_10 & io_csr_decode_write_illegal_0; // @[decode.scala:422:7, :465:{47,56}] wire _id_illegal_insn_T_12 = io_csr_decode_read_illegal_0 | _id_illegal_insn_T_11; // @[decode.scala:422:7, :465:{44,56}] wire _id_illegal_insn_T_13 = csr_en & _id_illegal_insn_T_12; // @[package.scala:81:59] wire _id_illegal_insn_T_14 = _id_illegal_insn_T_9 | _id_illegal_insn_T_13; // @[decode.scala:463:49, :464:45, :465:13] wire _id_illegal_insn_T_15 = sfence | system_insn; // @[decode.scala:453:32, :454:21, :466:14] wire _id_illegal_insn_T_16 = _id_illegal_insn_T_15 & io_csr_decode_system_illegal_0; // @[decode.scala:422:7, :466:{14,30}] wire id_illegal_insn = _id_illegal_insn_T_14 | _id_illegal_insn_T_16; // @[decode.scala:464:45, :465:89, :466:30] wire _T_1 = io_interrupt_0 & ~io_enq_uop_is_sfb_0; // @[decode.scala:422:7, :473:{19,22}] assign xcpt_valid = _T_1 | uop_bp_debug_if | uop_bp_xcpt_if | uop_xcpt_pf_if | uop_xcpt_ae_if | id_illegal_insn; // @[decode.scala:428:17, :465:89, :470:26, :473:19] assign uop_exception = xcpt_valid; // @[decode.scala:428:17, :470:26] assign xcpt_cause = _T_1 ? io_interrupt_cause_0 : {60'h0, uop_bp_debug_if ? 4'hE : uop_bp_xcpt_if ? 4'h3 : uop_xcpt_pf_if ? 4'hC : {2'h0, uop_xcpt_ae_if ? 2'h1 : 2'h2}}; // @[Mux.scala:50:70] assign uop_exc_cause = xcpt_cause; // @[Mux.scala:50:70] wire [31:0] _uop_is_mov_T = uop_inst & 32'hFE00707F; // @[decode.scala:428:17, :485:26] wire _uop_is_mov_T_1 = _uop_is_mov_T == 32'h33; // @[decode.scala:485:26] wire _uop_is_mov_T_2 = ~(|LRS1); // @[decode.scala:442:18, :485:42] assign _uop_is_mov_T_3 = _uop_is_mov_T_1 & _uop_is_mov_T_2; // @[decode.scala:485:{26,34,42}] assign uop_is_mov = _uop_is_mov_T_3; // @[decode.scala:428:17, :485:34] assign uop_fu_code_3 = cs_fu_code[3]; // @[decode.scala:428:17, :447:16, :487:84] wire _uop_iq_type_1_T = cs_fu_code[3]; // @[decode.scala:447:16, :487:84] assign uop_fu_code_4 = cs_fu_code[4]; // @[decode.scala:428:17, :447:16, :487:84] wire _uop_iq_type_1_T_1 = cs_fu_code[4]; // @[decode.scala:447:16, :487:84] assign uop_fu_code_5 = cs_fu_code[5]; // @[decode.scala:428:17, :447:16, :487:84] wire _uop_iq_type_1_T_2 = cs_fu_code[5]; // @[decode.scala:447:16, :487:84] assign uop_fu_code_8 = cs_fu_code[8]; // @[decode.scala:428:17, :447:16, :487:84] wire _uop_iq_type_1_T_3 = cs_fu_code[8]; // @[decode.scala:447:16, :487:84] wire _uop_iq_type_1_T_4 = _uop_iq_type_1_T | _uop_iq_type_1_T_1; // @[decode.scala:487:{84,98}] wire _uop_iq_type_1_T_5 = _uop_iq_type_1_T_4 | _uop_iq_type_1_T_2; // @[decode.scala:487:{84,98}] assign _uop_iq_type_1_T_6 = _uop_iq_type_1_T_5 | _uop_iq_type_1_T_3; // @[decode.scala:487:{84,98}] assign uop_iq_type_1 = _uop_iq_type_1_T_6; // @[decode.scala:428:17, :487:98] assign uop_fu_code_0 = cs_fu_code[0]; // @[decode.scala:428:17, :447:16, :488:84] assign _uop_iq_type_2_T = cs_fu_code[0]; // @[decode.scala:447:16, :488:84] assign uop_iq_type_2 = _uop_iq_type_2_T; // @[decode.scala:428:17, :488:84] assign uop_fu_code_1 = cs_fu_code[1]; // @[decode.scala:428:17, :447:16, :489:84] wire _uop_iq_type_0_T = cs_fu_code[1]; // @[decode.scala:447:16, :489:84] assign uop_fu_code_2 = cs_fu_code[2]; // @[decode.scala:428:17, :447:16, :489:84] wire _uop_iq_type_0_T_1 = cs_fu_code[2]; // @[decode.scala:447:16, :489:84] assign _uop_iq_type_0_T_2 = _uop_iq_type_0_T | _uop_iq_type_0_T_1; // @[decode.scala:489:{84,98}] assign uop_iq_type_0 = _uop_iq_type_0_T_2; // @[decode.scala:428:17, :489:98] assign uop_fu_code_6 = cs_fu_code[6]; // @[decode.scala:428:17, :447:16, :490:84] wire _uop_iq_type_3_T = cs_fu_code[6]; // @[decode.scala:447:16, :490:84] assign uop_fu_code_7 = cs_fu_code[7]; // @[decode.scala:428:17, :447:16, :490:84] wire _uop_iq_type_3_T_1 = cs_fu_code[7]; // @[decode.scala:447:16, :490:84] assign uop_fu_code_9 = cs_fu_code[9]; // @[decode.scala:428:17, :447:16, :490:84] wire _uop_iq_type_3_T_2 = cs_fu_code[9]; // @[decode.scala:447:16, :490:84] wire _uop_iq_type_3_T_3 = _uop_iq_type_3_T | _uop_iq_type_3_T_1; // @[decode.scala:490:{84,98}] assign _uop_iq_type_3_T_4 = _uop_iq_type_3_T_3 | _uop_iq_type_3_T_2; // @[decode.scala:490:{84,98}] assign uop_iq_type_3 = _uop_iq_type_3_T_4; // @[decode.scala:428:17, :490:98] assign uop_ldst = {1'h0, LDST}; // @[decode.scala:428:17, :441:18, :494:18] assign uop_lrs3 = {1'h0, LRS3}; // @[decode.scala:428:17, :444:18, :497:18] wire _uop_lrs1_rtype_T = cs_rs1_type == 2'h0; // @[decode.scala:447:16, :500:37] wire _uop_lrs1_rtype_T_1 = ~(|LRS1); // @[decode.scala:442:18, :485:42, :500:56] wire _uop_lrs1_rtype_T_2 = _uop_lrs1_rtype_T & _uop_lrs1_rtype_T_1; // @[decode.scala:500:{37,48,56}] wire [1:0] _uop_lrs1_rtype_T_3 = _uop_lrs1_rtype_T_2 ? 2'h3 : cs_rs1_type; // @[decode.scala:447:16, :500:{24,48}] wire _uop_lrs2_rtype_T = cs_rs2_type == 2'h0; // @[decode.scala:447:16, :501:37] wire _uop_lrs2_rtype_T_1 = ~(|LRS2); // @[decode.scala:443:18, :501:56] wire _uop_lrs2_rtype_T_2 = _uop_lrs2_rtype_T & _uop_lrs2_rtype_T_1; // @[decode.scala:501:{37,48,56}] wire [1:0] _uop_lrs2_rtype_T_3 = _uop_lrs2_rtype_T_2 ? 2'h3 : cs_rs2_type; // @[decode.scala:447:16, :501:{24,48}] wire _uop_ldst_is_rs1_T = uop_br_type == 4'h0; // @[decode.scala:428:17] wire _uop_ldst_is_rs1_T_1 = _uop_ldst_is_rs1_T & uop_is_sfb; // @[decode.scala:428:17] wire _uop_ldst_is_rs1_T_2 = _uop_ldst_is_rs1_T_1; // @[micro-op.scala:121:{42,52}] wire _T_24 = _uop_ldst_is_rs1_T & uop_is_sfb & cs_rs2_type == 2'h2; // @[decode.scala:428:17, :447:16, :506:{27,42}] wire _GEN_41 = LDST == 5'h0; // @[decode.scala:422:7, :426:14, :428:17, :441:18, :507:33] wire _uop_lrs2_rtype_T_4; // @[decode.scala:507:33] assign _uop_lrs2_rtype_T_4 = _GEN_41; // @[decode.scala:507:33] wire _uop_lrs1_rtype_T_4; // @[decode.scala:512:33] assign _uop_lrs1_rtype_T_4 = _GEN_41; // @[decode.scala:507:33, :512:33] wire [1:0] _uop_lrs2_rtype_T_5 = {2{_uop_lrs2_rtype_T_4}}; // @[decode.scala:507:{27,33}] assign uop_lrs2_rtype = _T_24 ? _uop_lrs2_rtype_T_5 : _uop_lrs2_rtype_T_3; // @[decode.scala:428:17, :501:{18,24}, :506:{27,52}, :507:{21,27}] assign uop_lrs2 = {1'h0, _T_24 ? LDST : LRS2}; // @[decode.scala:428:17, :441:18, :443:18, :496:18, :506:{27,52}, :508:21] wire _T_28 = _uop_ldst_is_rs1_T & uop_is_sfb & uop_is_mov; // @[decode.scala:428:17, :510:34] wire _GEN_42 = _T_24 | ~_T_28; // @[decode.scala:495:18, :506:{27,52}, :510:{34,49}] assign uop_lrs1 = {1'h0, _GEN_42 ? LRS1 : LDST}; // @[decode.scala:428:17, :441:18, :442:18, :495:18, :506:52, :510:49] wire [1:0] _uop_lrs1_rtype_T_5 = {2{_uop_lrs1_rtype_T_4}}; // @[decode.scala:512:{27,33}] assign uop_lrs1_rtype = _GEN_42 ? _uop_lrs1_rtype_T_3 : _uop_lrs1_rtype_T_5; // @[decode.scala:428:17, :495:18, :500:{18,24}, :506:52, :510:49, :512:27] assign uop_ldst_is_rs1 = ~_T_24 & (_T_28 | _uop_ldst_is_rs1_T_2); // @[decode.scala:428:17, :504:19, :506:{27,52}, :509:21, :510:{34,49}, :513:21] wire _uop_mem_size_T = cs_mem_cmd == 5'h14; // @[package.scala:16:47] wire _uop_mem_size_T_1 = cs_mem_cmd == 5'h5; // @[package.scala:16:47] wire _uop_mem_size_T_2 = _uop_mem_size_T | _uop_mem_size_T_1; // @[package.scala:16:47, :81:59] wire _uop_mem_size_T_3 = |LRS2; // @[decode.scala:443:18, :501:56, :521:77] wire _uop_mem_size_T_4 = |LRS1; // @[decode.scala:442:18, :485:42, :521:91] wire [1:0] _uop_mem_size_T_5 = {_uop_mem_size_T_3, _uop_mem_size_T_4}; // @[decode.scala:521:{71,77,91}] wire [1:0] _uop_mem_size_T_6 = uop_inst[13:12]; // @[decode.scala:428:17, :521:105] assign _uop_mem_size_T_7 = _uop_mem_size_T_2 ? _uop_mem_size_T_5 : _uop_mem_size_T_6; // @[package.scala:81:59] assign uop_mem_size = _uop_mem_size_T_7; // @[decode.scala:428:17, :521:24] wire _uop_mem_signed_T = uop_inst[14]; // @[decode.scala:428:17, :522:26] assign _uop_mem_signed_T_1 = ~_uop_mem_signed_T; // @[decode.scala:522:{21,26}] assign uop_mem_signed = _uop_mem_signed_T_1; // @[decode.scala:428:17, :522:21] wire [31:0] _GEN_43 = {17'h0, uop_inst[14:0] & 15'h707F}; // @[decode.scala:428:17, :526:26] wire [31:0] _uop_is_fence_T; // @[decode.scala:526:26] assign _uop_is_fence_T = _GEN_43; // @[decode.scala:526:26] wire [31:0] _uop_is_fencei_T; // @[decode.scala:527:26] assign _uop_is_fencei_T = _GEN_43; // @[decode.scala:526:26, :527:26] wire [31:0] _uop_br_type_T; // @[decode.scala:604:36] assign _uop_br_type_T = _GEN_43; // @[decode.scala:526:26, :604:36] wire [31:0] _uop_br_type_T_3; // @[decode.scala:604:36] assign _uop_br_type_T_3 = _GEN_43; // @[decode.scala:526:26, :604:36] wire [31:0] _uop_br_type_T_6; // @[decode.scala:604:36] assign _uop_br_type_T_6 = _GEN_43; // @[decode.scala:526:26, :604:36] wire [31:0] _uop_br_type_T_9; // @[decode.scala:604:36] assign _uop_br_type_T_9 = _GEN_43; // @[decode.scala:526:26, :604:36] wire [31:0] _uop_br_type_T_12; // @[decode.scala:604:36] assign _uop_br_type_T_12 = _GEN_43; // @[decode.scala:526:26, :604:36] wire [31:0] _uop_br_type_T_15; // @[decode.scala:604:36] assign _uop_br_type_T_15 = _GEN_43; // @[decode.scala:526:26, :604:36] wire [31:0] _uop_br_type_T_21; // @[decode.scala:604:36] assign _uop_br_type_T_21 = _GEN_43; // @[decode.scala:526:26, :604:36] assign _uop_is_fence_T_1 = _uop_is_fence_T == 32'hF; // @[decode.scala:526:26] assign uop_is_fence = _uop_is_fence_T_1; // @[decode.scala:428:17, :526:26] assign _uop_is_fencei_T_1 = _uop_is_fencei_T == 32'h100F; // @[decode.scala:527:26] assign uop_is_fencei = _uop_is_fencei_T_1; // @[decode.scala:428:17, :527:26] assign _uop_is_sfence_T_1 = _uop_is_sfence_T == 32'h12000073; // @[decode.scala:528:26] assign uop_is_sfence = _uop_is_sfence_T_1; // @[decode.scala:428:17, :528:26] wire _uop_is_sys_pc2epc_T_1 = _uop_is_sys_pc2epc_T == 32'h100073; // @[decode.scala:529:29] wire _uop_is_sys_pc2epc_T_3 = _uop_is_sys_pc2epc_T_2 == 32'h73; // @[decode.scala:529:48] assign _uop_is_sys_pc2epc_T_4 = _uop_is_sys_pc2epc_T_1 | _uop_is_sys_pc2epc_T_3; // @[decode.scala:529:{29,40,48}] assign uop_is_sys_pc2epc = _uop_is_sys_pc2epc_T_4; // @[decode.scala:428:17, :529:40] wire _uop_is_eret_T_1 = _uop_is_eret_T == 32'h73; // @[decode.scala:530:26] wire _uop_is_eret_T_3 = _uop_is_eret_T_2 == 32'h100073; // @[decode.scala:530:44] wire _uop_is_eret_T_4 = _uop_is_eret_T_1 | _uop_is_eret_T_3; // @[decode.scala:530:{26,36,44}] wire _uop_is_eret_T_6 = _uop_is_eret_T_5 == 32'h10200073; // @[decode.scala:530:63] wire _uop_is_eret_T_7 = _uop_is_eret_T_4 | _uop_is_eret_T_6; // @[decode.scala:530:{36,55,63}] wire _uop_is_eret_T_9 = _uop_is_eret_T_8 == 32'h30200073; // @[decode.scala:530:80] wire _uop_is_eret_T_10 = _uop_is_eret_T_7 | _uop_is_eret_T_9; // @[decode.scala:530:{55,72,80}] wire _uop_is_eret_T_12 = _uop_is_eret_T_11 == 32'h7B200073; // @[decode.scala:530:97] assign _uop_is_eret_T_13 = _uop_is_eret_T_10 | _uop_is_eret_T_12; // @[decode.scala:530:{72,89,97}] assign uop_is_eret = _uop_is_eret_T_13; // @[decode.scala:428:17, :530:89] wire [6:0] _uop_is_rocc_T = uop_inst[6:0]; // @[decode.scala:428:17, :532:25] wire _uop_is_rocc_T_1 = _uop_is_rocc_T == 7'hB; // @[package.scala:16:47] wire _uop_is_rocc_T_2 = _uop_is_rocc_T == 7'h2B; // @[package.scala:16:47] wire _uop_is_rocc_T_3 = _uop_is_rocc_T == 7'h7B; // @[package.scala:16:47] wire _uop_is_rocc_T_4 = _uop_is_rocc_T_1 | _uop_is_rocc_T_2; // @[package.scala:16:47, :81:59] wire _uop_is_rocc_T_5 = _uop_is_rocc_T_4 | _uop_is_rocc_T_3; // @[package.scala:16:47, :81:59] wire _uop_is_rocc_T_7 = _uop_is_rocc_T_6 == 3'h0; // @[package.scala:16:47] wire _uop_is_rocc_T_8 = _uop_is_rocc_T_6 == 3'h2; // @[package.scala:16:47] wire _uop_is_rocc_T_9 = _uop_is_rocc_T_6 == 3'h3; // @[package.scala:16:47] wire _uop_is_rocc_T_10 = _uop_is_rocc_T_6 == 3'h4; // @[package.scala:16:47] wire _uop_is_rocc_T_11 = _uop_is_rocc_T_6 == 3'h6; // @[package.scala:16:47] wire _uop_is_rocc_T_12 = &_uop_is_rocc_T_6; // @[package.scala:16:47] wire _uop_is_rocc_T_13 = _uop_is_rocc_T_7 | _uop_is_rocc_T_8; // @[package.scala:16:47, :81:59] wire _uop_is_rocc_T_14 = _uop_is_rocc_T_13 | _uop_is_rocc_T_9; // @[package.scala:16:47, :81:59] wire _uop_is_rocc_T_15 = _uop_is_rocc_T_14 | _uop_is_rocc_T_10; // @[package.scala:16:47, :81:59] wire _uop_is_rocc_T_16 = _uop_is_rocc_T_15 | _uop_is_rocc_T_11; // @[package.scala:16:47, :81:59] wire _uop_is_rocc_T_17 = _uop_is_rocc_T_16 | _uop_is_rocc_T_12; // @[package.scala:16:47, :81:59] assign _uop_is_rocc_T_18 = _uop_is_rocc_T_5 & _uop_is_rocc_T_17; // @[package.scala:81:59] assign uop_is_rocc = _uop_is_rocc_T_18; // @[decode.scala:428:17, :532:81] wire _uop_flush_on_commit_T = ~csr_ren; // @[decode.scala:452:50, :465:47, :533:59] wire _uop_flush_on_commit_T_1 = csr_en & _uop_flush_on_commit_T; // @[package.scala:81:59] wire _uop_flush_on_commit_T_2 = _uop_flush_on_commit_T_1 & io_csr_decode_write_flush_0; // @[decode.scala:422:7, :533:{56,68}] assign _uop_flush_on_commit_T_3 = cs_flush_on_commit | _uop_flush_on_commit_T_2; // @[decode.scala:447:16, :533:{45,68}] assign uop_flush_on_commit = _uop_flush_on_commit_T_3; // @[decode.scala:428:17, :533:45] wire _GEN_44 = cs_imm_sel == 3'h2; // @[package.scala:16:47] wire _di24_20_T; // @[decode.scala:540:32] assign _di24_20_T = _GEN_44; // @[decode.scala:540:32] wire _imm_i11_T_2; // @[util.scala:288:44] assign _imm_i11_T_2 = _GEN_44; // @[util.scala:288:44] wire _T_142 = cs_imm_sel == 3'h1; // @[decode.scala:447:16, :540:55] wire _di24_20_T_1; // @[decode.scala:540:55] assign _di24_20_T_1 = _T_142; // @[decode.scala:540:55] wire _imm_i0_T; // @[util.scala:291:27] assign _imm_i0_T = _T_142; // @[util.scala:291:27] wire _di24_20_T_2 = _di24_20_T | _di24_20_T_1; // @[decode.scala:540:{32,41,55}] wire [4:0] di24_20 = _di24_20_T_2 ? _di24_20_T_3 : _di24_20_T_4; // @[decode.scala:540:{20,41,69,81}] wire [6:0] _imm_packed_T = uop_inst[31:25]; // @[decode.scala:428:17, :541:28] wire [7:0] _imm_packed_T_1 = uop_inst[19:12]; // @[decode.scala:428:17, :541:50] wire [11:0] imm_packed_hi = {_imm_packed_T, di24_20}; // @[decode.scala:540:20, :541:{23,28}] assign imm_packed = {imm_packed_hi, _imm_packed_T_1}; // @[decode.scala:541:{23,50}] assign uop_imm_packed = imm_packed; // @[decode.scala:428:17, :541:23] wire _imm_ip_T = cs_imm_sel == 3'h6; // @[util.scala:282:23] wire [19:0] imm_ip = _imm_ip_T ? 20'h0 : imm_packed; // @[util.scala:282:{17,23}] wire _imm_sign_T = imm_ip[19]; // @[util.scala:282:17, :284:18] wire imm_sign = _imm_sign_T; // @[util.scala:284:{18,37}] wire imm_hi_hi_hi = imm_sign; // @[util.scala:284:37, :294:15] wire _T_139 = cs_imm_sel == 3'h3; // @[package.scala:16:47] wire _imm_i30_20_T; // @[util.scala:285:27] assign _imm_i30_20_T = _T_139; // @[util.scala:285:27] wire _imm_i19_12_T; // @[util.scala:286:27] assign _imm_i19_12_T = _T_139; // @[util.scala:285:27, :286:27] wire _imm_i11_T; // @[util.scala:287:27] assign _imm_i11_T = _T_139; // @[util.scala:285:27, :287:27] wire _imm_i10_5_T; // @[util.scala:289:27] assign _imm_i10_5_T = _T_139; // @[util.scala:285:27, :289:27] wire _imm_i4_1_T; // @[util.scala:290:27] assign _imm_i4_1_T = _T_139; // @[util.scala:285:27, :290:27] wire [10:0] _imm_i30_20_T_1 = imm_ip[18:8]; // @[util.scala:282:17, :285:39] wire [10:0] _imm_i30_20_T_2 = _imm_i30_20_T_1; // @[util.scala:285:{39,46}] wire [10:0] imm_i30_20 = _imm_i30_20_T ? _imm_i30_20_T_2 : {11{imm_sign}}; // @[util.scala:284:37, :285:{21,27,46}] wire [10:0] imm_hi_hi_lo = imm_i30_20; // @[util.scala:285:21, :294:15] wire _GEN_45 = cs_imm_sel == 3'h4; // @[util.scala:286:44] wire _imm_i19_12_T_1; // @[util.scala:286:44] assign _imm_i19_12_T_1 = _GEN_45; // @[util.scala:286:44] wire _imm_i11_T_1; // @[util.scala:288:27] assign _imm_i11_T_1 = _GEN_45; // @[util.scala:286:44, :288:27] wire _imm_i19_12_T_2 = _imm_i19_12_T | _imm_i19_12_T_1; // @[util.scala:286:{27,36,44}] wire [7:0] _imm_i19_12_T_3 = imm_ip[7:0]; // @[util.scala:282:17, :286:56] wire [7:0] _imm_i19_12_T_4 = _imm_i19_12_T_3; // @[util.scala:286:{56,62}] wire [7:0] imm_i19_12 = _imm_i19_12_T_2 ? _imm_i19_12_T_4 : {8{imm_sign}}; // @[util.scala:284:37, :286:{21,36,62}] wire [7:0] imm_hi_lo_hi = imm_i19_12; // @[util.scala:286:21, :294:15] wire _imm_i11_T_3 = _imm_i11_T_1 | _imm_i11_T_2; // @[util.scala:288:{27,36,44}] wire _imm_i11_T_4 = imm_ip[8]; // @[util.scala:282:17, :288:56] wire _imm_i0_T_3 = imm_ip[8]; // @[util.scala:282:17, :288:56, :291:56] wire _imm_i11_T_5 = _imm_i11_T_4; // @[util.scala:288:{56,60}] wire _imm_i11_T_6 = _imm_i11_T_3 ? _imm_i11_T_5 : imm_sign; // @[util.scala:284:37, :288:{21,36,60}] wire imm_i11 = ~_imm_i11_T & _imm_i11_T_6; // @[util.scala:287:{21,27}, :288:21] wire imm_hi_lo_lo = imm_i11; // @[util.scala:287:21, :294:15] wire [4:0] _imm_i10_5_T_1 = imm_ip[18:14]; // @[util.scala:282:17, :289:44] wire [4:0] _imm_i10_5_T_2 = _imm_i10_5_T_1; // @[util.scala:289:{44,52}] wire [4:0] imm_i10_5 = _imm_i10_5_T ? 5'h0 : _imm_i10_5_T_2; // @[util.scala:289:{21,27,52}] wire [4:0] imm_lo_hi_hi = imm_i10_5; // @[util.scala:289:21, :294:15] wire [4:0] _imm_i4_1_T_1 = imm_ip[13:9]; // @[util.scala:282:17, :290:44] wire [4:0] _imm_i4_1_T_2 = _imm_i4_1_T_1; // @[util.scala:290:{44,51}] wire [4:0] imm_i4_1 = _imm_i4_1_T ? 5'h0 : _imm_i4_1_T_2; // @[util.scala:290:{21,27,51}] wire [4:0] imm_lo_hi_lo = imm_i4_1; // @[util.scala:290:21, :294:15] wire _imm_i0_T_1 = cs_imm_sel == 3'h0; // @[util.scala:291:44] wire _imm_i0_T_2 = _imm_i0_T | _imm_i0_T_1; // @[util.scala:291:{27,36,44}] wire _imm_i0_T_4 = _imm_i0_T_3; // @[util.scala:291:{56,60}] wire imm_i0 = _imm_i0_T_2 & _imm_i0_T_4; // @[util.scala:291:{21,36,60}] wire imm_lo_lo = imm_i0; // @[util.scala:291:21, :294:15] wire [9:0] imm_lo_hi = {imm_lo_hi_hi, imm_lo_hi_lo}; // @[util.scala:294:15] wire [10:0] imm_lo = {imm_lo_hi, imm_lo_lo}; // @[util.scala:294:15] wire [8:0] imm_hi_lo = {imm_hi_lo_hi, imm_hi_lo_lo}; // @[util.scala:294:15] wire [11:0] imm_hi_hi = {imm_hi_hi_hi, imm_hi_hi_lo}; // @[util.scala:294:15] wire [20:0] imm_hi = {imm_hi_hi, imm_hi_lo}; // @[util.scala:294:15] wire [31:0] imm = {imm_hi, imm_lo}; // @[util.scala:294:15] wire [27:0] imm_hi_1 = imm[31:4]; // @[util.scala:294:15] wire [4:0] imm_lo_1 = imm[4:0]; // @[util.scala:294:15] wire _short_imm_T = imm_hi_1 == 28'h0; // @[pla.scala:114:36] wire [27:0] _short_imm_T_1 = ~imm_hi_1; // @[decode.scala:543:20, :545:37] wire _short_imm_T_2 = _short_imm_T_1 == 28'h0; // @[pla.scala:114:36] wire _short_imm_T_3 = _short_imm_T | _short_imm_T_2; // @[decode.scala:545:{26,34,45}] wire _short_imm_T_4 = &cs_imm_sel; // @[decode.scala:447:16, :545:67] wire short_imm = _short_imm_T_3 | _short_imm_T_4; // @[decode.scala:545:{34,53,67}] wire _uop_imm_rename_T = cs_imm_sel != 3'h6; // @[decode.scala:447:16, :547:32] wire _uop_imm_rename_T_1 = ~(&cs_imm_sel); // @[decode.scala:447:16, :545:67, :547:55] wire _uop_imm_rename_T_2 = _uop_imm_rename_T & _uop_imm_rename_T_1; // @[decode.scala:547:{32,41,55}] assign uop_imm_rename = ~short_imm & _uop_imm_rename_T_2; // @[decode.scala:428:17, :545:53, :547:{18,41}, :550:20, :551:20] assign uop_imm_sel = short_imm ? 3'h5 : cs_imm_sel; // @[decode.scala:428:17, :447:16, :545:53, :549:18, :550:20, :552:17] wire _uop_pimm_T = &cs_imm_sel; // @[decode.scala:447:16, :545:67, :553:32] wire [4:0] _uop_pimm_T_2 = _uop_pimm_T ? {2'h0, _uop_pimm_T_1} : imm_lo_1; // @[decode.scala:544:19, :553:{20,32,47}] assign uop_pimm = short_imm ? _uop_pimm_T_2 : 5'h0; // @[decode.scala:422:7, :426:14, :428:17, :429:7, :545:53, :550:20, :553:{14,20}] wire _uop_fp_rm_T_1 = &_uop_fp_rm_T; // @[decode.scala:556:{26,34}] assign _uop_fp_rm_T_3 = _uop_fp_rm_T_1 ? io_fcsr_rm_0 : _uop_fp_rm_T_2; // @[decode.scala:422:7, :556:{21,34,59}] assign uop_fp_rm = _uop_fp_rm_T_3; // @[decode.scala:428:17, :556:21] assign _uop_fp_typ_T = uop_inst[21:20]; // @[decode.scala:428:17, :557:22] assign uop_fp_typ = _uop_fp_typ_T; // @[decode.scala:428:17, :557:22] assign uop_csr_cmd = (_T_29 | (&cs_csr_cmd)) & ~(|LRS1) ? 3'h2 : cs_csr_cmd; // @[package.scala:16:47] wire [31:0] _uop_br_type_T_18 = {25'h0, _uop_is_rocc_T}; // @[decode.scala:529:48, :532:25, :572:14, :604:36] wire [9:0] _GEN_46 = {uop_inst[14:12], _uop_is_rocc_T}; // @[decode.scala:428:17, :460:24, :526:26, :532:25] wire [16:0] _GEN_47 = {_imm_packed_T, uop_inst[14:12], _uop_is_rocc_T}; // @[decode.scala:428:17, :460:24, :485:26, :532:25, :541:28] assign uop_op1_sel = _uop_is_rocc_T == 7'h37 | _GEN_46 == 10'h2F3 | _GEN_46 == 10'h373 | _GEN_46 == 10'h3F3 | uop_inst == 32'h10500073 | uop_inst == 32'h10200073 | uop_inst == 32'h30200073 | uop_inst == 32'h7B200073 ? 2'h1 : _uop_is_rocc_T == 7'h6F | _GEN_46 == 10'h67 | _uop_is_rocc_T == 7'h17 ? 2'h2 : {2{_GEN_47 == 17'h4133 | _GEN_47 == 17'h4233 | _GEN_47 == 17'h4333 | _GEN_47 == 17'h413B | _GEN_47 == 17'h423B | _GEN_47 == 17'h433B | _GEN_47 == 17'h103B | {uop_inst[31:26], uop_inst[14:12], _uop_is_rocc_T} == 16'h89B}}; // @[package.scala:81:59] wire [15:0] _GEN_48 = {uop_inst[31:26], uop_inst[14:12], _uop_is_rocc_T}; // @[decode.scala:428:17, :460:24, :532:25, :589:65] wire _uop_op2_sel_T = uop_lrs2_rtype == 2'h0; // @[decode.scala:428:17, :590:39] wire [2:0] _uop_op2_sel_T_1 = _uop_op2_sel_T ? 3'h5 : 3'h6; // @[decode.scala:590:{23,39}] assign uop_op2_sel = cs_is_amo | _GEN_46 == 10'hF3 | _GEN_46 == 10'h173 | _GEN_46 == 10'h1F3 ? 3'h2 : _GEN_46 == 10'h2F3 | _GEN_46 == 10'h373 | _GEN_46 == 10'h3F3 | uop_inst == 32'h10500073 | uop_inst == 32'h10200073 | uop_inst == 32'h7B200073 | uop_inst == 32'h30200073 ? 3'h4 : _uop_is_rocc_T == 7'h6F | _GEN_46 == 10'h67 ? 3'h3 : _GEN_47 == 17'h90B3 | _GEN_48 == 16'h4893 | _GEN_47 == 17'hD0B3 | _GEN_48 == 16'h6893 | _GEN_47 == 17'h50B3 | {uop_inst[31:26], uop_inst[14:12], _uop_is_rocc_T} == 16'h2893 ? _uop_op2_sel_T_1 : {2'h0, _T_139 | _imm_i0_T_1 | _T_142}; // @[package.scala:16:47, :81:59] wire _uop_br_type_T_1 = _uop_br_type_T == 32'h63; // @[decode.scala:604:36] wire [3:0] _uop_br_type_T_2 = {2'h0, _uop_br_type_T_1, 1'h0}; // @[decode.scala:604:{30,36}] wire _uop_br_type_T_4 = _uop_br_type_T_3 == 32'h1063; // @[decode.scala:604:36] wire [3:0] _uop_br_type_T_5 = {3'h0, _uop_br_type_T_4}; // @[decode.scala:604:{30,36}] wire _uop_br_type_T_7 = _uop_br_type_T_6 == 32'h5063; // @[decode.scala:604:36] wire [3:0] _uop_br_type_T_8 = _uop_br_type_T_7 ? 4'h3 : 4'h0; // @[decode.scala:604:{30,36}] wire _uop_br_type_T_10 = _uop_br_type_T_9 == 32'h7063; // @[decode.scala:604:36] wire [3:0] _uop_br_type_T_11 = {1'h0, _uop_br_type_T_10, 2'h0}; // @[decode.scala:604:{30,36}] wire _uop_br_type_T_13 = _uop_br_type_T_12 == 32'h4063; // @[decode.scala:604:36] wire [3:0] _uop_br_type_T_14 = _uop_br_type_T_13 ? 4'h5 : 4'h0; // @[decode.scala:604:{30,36}] wire _uop_br_type_T_16 = _uop_br_type_T_15 == 32'h6063; // @[decode.scala:604:36] wire [3:0] _uop_br_type_T_17 = _uop_br_type_T_16 ? 4'h6 : 4'h0; // @[decode.scala:604:{30,36}] wire _uop_br_type_T_19 = _uop_br_type_T_18 == 32'h6F; // @[decode.scala:604:36] wire [3:0] _uop_br_type_T_20 = _uop_br_type_T_19 ? 4'h7 : 4'h0; // @[decode.scala:604:{30,36}] wire _uop_br_type_T_22 = _uop_br_type_T_21 == 32'h67; // @[decode.scala:604:36] wire [3:0] _uop_br_type_T_23 = {_uop_br_type_T_22, 3'h0}; // @[decode.scala:604:{30,36}] wire [3:0] _uop_br_type_T_24 = _uop_br_type_T_2 | _uop_br_type_T_5; // @[decode.scala:604:{30,62}] wire [3:0] _uop_br_type_T_25 = _uop_br_type_T_24 | _uop_br_type_T_8; // @[decode.scala:604:{30,62}] wire [3:0] _uop_br_type_T_26 = _uop_br_type_T_25 | _uop_br_type_T_11; // @[decode.scala:604:{30,62}] wire [3:0] _uop_br_type_T_27 = _uop_br_type_T_26 | _uop_br_type_T_14; // @[decode.scala:604:{30,62}] wire [3:0] _uop_br_type_T_28 = _uop_br_type_T_27 | _uop_br_type_T_17; // @[decode.scala:604:{30,62}] wire [3:0] _uop_br_type_T_29 = _uop_br_type_T_28 | _uop_br_type_T_20; // @[decode.scala:604:{30,62}] assign _uop_br_type_T_30 = _uop_br_type_T_29 | _uop_br_type_T_23; // @[decode.scala:604:{30,62}] assign uop_br_type = _uop_br_type_T_30; // @[decode.scala:428:17, :604:62] assign io_deq_uop_inst = io_deq_uop_inst_0; // @[decode.scala:422:7] assign io_deq_uop_debug_inst = io_deq_uop_debug_inst_0; // @[decode.scala:422:7] assign io_deq_uop_is_rvc = io_deq_uop_is_rvc_0; // @[decode.scala:422:7] assign io_deq_uop_debug_pc = io_deq_uop_debug_pc_0; // @[decode.scala:422:7] assign io_deq_uop_iq_type_0 = io_deq_uop_iq_type_0_0; // @[decode.scala:422:7] assign io_deq_uop_iq_type_1 = io_deq_uop_iq_type_1_0; // @[decode.scala:422:7] assign io_deq_uop_iq_type_2 = io_deq_uop_iq_type_2_0; // @[decode.scala:422:7] assign io_deq_uop_iq_type_3 = io_deq_uop_iq_type_3_0; // @[decode.scala:422:7] assign io_deq_uop_fu_code_0 = io_deq_uop_fu_code_0_0; // @[decode.scala:422:7] assign io_deq_uop_fu_code_1 = io_deq_uop_fu_code_1_0; // @[decode.scala:422:7] assign io_deq_uop_fu_code_2 = io_deq_uop_fu_code_2_0; // @[decode.scala:422:7] assign io_deq_uop_fu_code_3 = io_deq_uop_fu_code_3_0; // @[decode.scala:422:7] assign io_deq_uop_fu_code_4 = io_deq_uop_fu_code_4_0; // @[decode.scala:422:7] assign io_deq_uop_fu_code_5 = io_deq_uop_fu_code_5_0; // @[decode.scala:422:7] assign io_deq_uop_fu_code_6 = io_deq_uop_fu_code_6_0; // @[decode.scala:422:7] assign io_deq_uop_fu_code_7 = io_deq_uop_fu_code_7_0; // @[decode.scala:422:7] assign io_deq_uop_fu_code_8 = io_deq_uop_fu_code_8_0; // @[decode.scala:422:7] assign io_deq_uop_fu_code_9 = io_deq_uop_fu_code_9_0; // @[decode.scala:422:7] assign io_deq_uop_br_type = io_deq_uop_br_type_0; // @[decode.scala:422:7] assign io_deq_uop_is_sfb = io_deq_uop_is_sfb_0; // @[decode.scala:422:7] assign io_deq_uop_is_fence = io_deq_uop_is_fence_0; // @[decode.scala:422:7] assign io_deq_uop_is_fencei = io_deq_uop_is_fencei_0; // @[decode.scala:422:7] assign io_deq_uop_is_sfence = io_deq_uop_is_sfence_0; // @[decode.scala:422:7] assign io_deq_uop_is_amo = io_deq_uop_is_amo_0; // @[decode.scala:422:7] assign io_deq_uop_is_eret = io_deq_uop_is_eret_0; // @[decode.scala:422:7] assign io_deq_uop_is_sys_pc2epc = io_deq_uop_is_sys_pc2epc_0; // @[decode.scala:422:7] assign io_deq_uop_is_rocc = io_deq_uop_is_rocc_0; // @[decode.scala:422:7] assign io_deq_uop_is_mov = io_deq_uop_is_mov_0; // @[decode.scala:422:7] assign io_deq_uop_ftq_idx = io_deq_uop_ftq_idx_0; // @[decode.scala:422:7] assign io_deq_uop_edge_inst = io_deq_uop_edge_inst_0; // @[decode.scala:422:7] assign io_deq_uop_pc_lob = io_deq_uop_pc_lob_0; // @[decode.scala:422:7] assign io_deq_uop_taken = io_deq_uop_taken_0; // @[decode.scala:422:7] assign io_deq_uop_imm_rename = io_deq_uop_imm_rename_0; // @[decode.scala:422:7] assign io_deq_uop_imm_sel = io_deq_uop_imm_sel_0; // @[decode.scala:422:7] assign io_deq_uop_pimm = io_deq_uop_pimm_0; // @[decode.scala:422:7] assign io_deq_uop_imm_packed = io_deq_uop_imm_packed_0; // @[decode.scala:422:7] assign io_deq_uop_op1_sel = io_deq_uop_op1_sel_0; // @[decode.scala:422:7] assign io_deq_uop_op2_sel = io_deq_uop_op2_sel_0; // @[decode.scala:422:7] assign io_deq_uop_fp_ctrl_ldst = io_deq_uop_fp_ctrl_ldst_0; // @[decode.scala:422:7] assign io_deq_uop_fp_ctrl_wen = io_deq_uop_fp_ctrl_wen_0; // @[decode.scala:422:7] assign io_deq_uop_fp_ctrl_ren1 = io_deq_uop_fp_ctrl_ren1_0; // @[decode.scala:422:7] assign io_deq_uop_fp_ctrl_ren2 = io_deq_uop_fp_ctrl_ren2_0; // @[decode.scala:422:7] assign io_deq_uop_fp_ctrl_ren3 = io_deq_uop_fp_ctrl_ren3_0; // @[decode.scala:422:7] assign io_deq_uop_fp_ctrl_swap12 = io_deq_uop_fp_ctrl_swap12_0; // @[decode.scala:422:7] assign io_deq_uop_fp_ctrl_swap23 = io_deq_uop_fp_ctrl_swap23_0; // @[decode.scala:422:7] assign io_deq_uop_fp_ctrl_typeTagIn = io_deq_uop_fp_ctrl_typeTagIn_0; // @[decode.scala:422:7] assign io_deq_uop_fp_ctrl_typeTagOut = io_deq_uop_fp_ctrl_typeTagOut_0; // @[decode.scala:422:7] assign io_deq_uop_fp_ctrl_fromint = io_deq_uop_fp_ctrl_fromint_0; // @[decode.scala:422:7] assign io_deq_uop_fp_ctrl_toint = io_deq_uop_fp_ctrl_toint_0; // @[decode.scala:422:7] assign io_deq_uop_fp_ctrl_fastpipe = io_deq_uop_fp_ctrl_fastpipe_0; // @[decode.scala:422:7] assign io_deq_uop_fp_ctrl_fma = io_deq_uop_fp_ctrl_fma_0; // @[decode.scala:422:7] assign io_deq_uop_fp_ctrl_div = io_deq_uop_fp_ctrl_div_0; // @[decode.scala:422:7] assign io_deq_uop_fp_ctrl_sqrt = io_deq_uop_fp_ctrl_sqrt_0; // @[decode.scala:422:7] assign io_deq_uop_fp_ctrl_wflags = io_deq_uop_fp_ctrl_wflags_0; // @[decode.scala:422:7] assign io_deq_uop_exception = io_deq_uop_exception_0; // @[decode.scala:422:7] assign io_deq_uop_exc_cause = io_deq_uop_exc_cause_0; // @[decode.scala:422:7] assign io_deq_uop_mem_cmd = io_deq_uop_mem_cmd_0; // @[decode.scala:422:7] assign io_deq_uop_mem_size = io_deq_uop_mem_size_0; // @[decode.scala:422:7] assign io_deq_uop_mem_signed = io_deq_uop_mem_signed_0; // @[decode.scala:422:7] assign io_deq_uop_uses_ldq = io_deq_uop_uses_ldq_0; // @[decode.scala:422:7] assign io_deq_uop_uses_stq = io_deq_uop_uses_stq_0; // @[decode.scala:422:7] assign io_deq_uop_is_unique = io_deq_uop_is_unique_0; // @[decode.scala:422:7] assign io_deq_uop_flush_on_commit = io_deq_uop_flush_on_commit_0; // @[decode.scala:422:7] assign io_deq_uop_csr_cmd = io_deq_uop_csr_cmd_0; // @[decode.scala:422:7] assign io_deq_uop_ldst_is_rs1 = io_deq_uop_ldst_is_rs1_0; // @[decode.scala:422:7] assign io_deq_uop_ldst = io_deq_uop_ldst_0; // @[decode.scala:422:7] assign io_deq_uop_lrs1 = io_deq_uop_lrs1_0; // @[decode.scala:422:7] assign io_deq_uop_lrs2 = io_deq_uop_lrs2_0; // @[decode.scala:422:7] assign io_deq_uop_lrs3 = io_deq_uop_lrs3_0; // @[decode.scala:422:7] assign io_deq_uop_dst_rtype = io_deq_uop_dst_rtype_0; // @[decode.scala:422:7] assign io_deq_uop_lrs1_rtype = io_deq_uop_lrs1_rtype_0; // @[decode.scala:422:7] assign io_deq_uop_lrs2_rtype = io_deq_uop_lrs2_rtype_0; // @[decode.scala:422:7] assign io_deq_uop_frs3_en = io_deq_uop_frs3_en_0; // @[decode.scala:422:7] assign io_deq_uop_fcn_dw = io_deq_uop_fcn_dw_0; // @[decode.scala:422:7] assign io_deq_uop_fcn_op = io_deq_uop_fcn_op_0; // @[decode.scala:422:7] assign io_deq_uop_fp_val = io_deq_uop_fp_val_0; // @[decode.scala:422:7] assign io_deq_uop_fp_rm = io_deq_uop_fp_rm_0; // @[decode.scala:422:7] assign io_deq_uop_fp_typ = io_deq_uop_fp_typ_0; // @[decode.scala:422:7] assign io_deq_uop_xcpt_pf_if = io_deq_uop_xcpt_pf_if_0; // @[decode.scala:422:7] assign io_deq_uop_xcpt_ae_if = io_deq_uop_xcpt_ae_if_0; // @[decode.scala:422:7] assign io_deq_uop_bp_debug_if = io_deq_uop_bp_debug_if_0; // @[decode.scala:422:7] assign io_deq_uop_bp_xcpt_if = io_deq_uop_bp_xcpt_if_0; // @[decode.scala:422:7] assign io_deq_uop_debug_fsrc = io_deq_uop_debug_fsrc_0; // @[decode.scala:422:7] assign io_csr_decode_inst = io_csr_decode_inst_0; // @[decode.scala:422:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module TLMonitor_66( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_source, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [26:0] _GEN = {23'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] reg [8:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg source_1; // @[Monitor.scala:541:22] reg [3:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [7:0] inflight_sizes; // @[Monitor.scala:618:33] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_0 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:36:7, :673:46] wire _GEN_1 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:36:7, :673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [1:0] inflight_1; // @[Monitor.scala:726:35] reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to the following Chisel files. File Serdes.scala: package testchipip.serdes import chisel3._ import chisel3.util._ import freechips.rocketchip.diplomacy._ import org.chipsalliance.cde.config._ class GenericSerializer[T <: Data](t: T, flitWidth: Int) extends Module { override def desiredName = s"GenericSerializer_${t.typeName}w${t.getWidth}_f${flitWidth}" val io = IO(new Bundle { val in = Flipped(Decoupled(t)) val out = Decoupled(new Flit(flitWidth)) val busy = Output(Bool()) }) val dataBits = t.getWidth.max(flitWidth) val dataBeats = (dataBits - 1) / flitWidth + 1 require(dataBeats >= 1) val data = Reg(Vec(dataBeats, UInt(flitWidth.W))) val beat = RegInit(0.U(log2Ceil(dataBeats).W)) io.in.ready := io.out.ready && beat === 0.U io.out.valid := io.in.valid || beat =/= 0.U io.out.bits.flit := Mux(beat === 0.U, io.in.bits.asUInt, data(beat)) when (io.out.fire) { beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U) when (beat === 0.U) { data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(flitWidth.W))) data(0) := DontCare // unused, DCE this } } io.busy := io.out.valid } class GenericDeserializer[T <: Data](t: T, flitWidth: Int) extends Module { override def desiredName = s"GenericDeserializer_${t.typeName}w${t.getWidth}_f${flitWidth}" val io = IO(new Bundle { val in = Flipped(Decoupled(new Flit(flitWidth))) val out = Decoupled(t) val busy = Output(Bool()) }) val dataBits = t.getWidth.max(flitWidth) val dataBeats = (dataBits - 1) / flitWidth + 1 require(dataBeats >= 1) val data = Reg(Vec(dataBeats-1, UInt(flitWidth.W))) val beat = RegInit(0.U(log2Ceil(dataBeats).W)) io.in.ready := io.out.ready || beat =/= (dataBeats-1).U io.out.valid := io.in.valid && beat === (dataBeats-1).U io.out.bits := (if (dataBeats == 1) { io.in.bits.flit.asTypeOf(t) } else { Cat(io.in.bits.flit, data.asUInt).asTypeOf(t) }) when (io.in.fire) { beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U) if (dataBeats > 1) { when (beat =/= (dataBeats-1).U) { data(beat(log2Ceil(dataBeats-1)-1,0)) := io.in.bits.flit } } } io.busy := beat =/= 0.U } class FlitToPhit(flitWidth: Int, phitWidth: Int) extends Module { override def desiredName = s"FlitToPhit_f${flitWidth}_p${phitWidth}" val io = IO(new Bundle { val in = Flipped(Decoupled(new Flit(flitWidth))) val out = Decoupled(new Phit(phitWidth)) }) require(flitWidth >= phitWidth) val dataBeats = (flitWidth - 1) / phitWidth + 1 val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W))) val beat = RegInit(0.U(log2Ceil(dataBeats).W)) io.in.ready := io.out.ready && beat === 0.U io.out.valid := io.in.valid || beat =/= 0.U io.out.bits.phit := (if (dataBeats == 1) io.in.bits.flit else Mux(beat === 0.U, io.in.bits.flit, data(beat-1.U))) when (io.out.fire) { beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U) when (beat === 0.U) { data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(phitWidth.W))).tail } } } object FlitToPhit { def apply(flit: DecoupledIO[Flit], phitWidth: Int): DecoupledIO[Phit] = { val flit2phit = Module(new FlitToPhit(flit.bits.flitWidth, phitWidth)) flit2phit.io.in <> flit flit2phit.io.out } } class PhitToFlit(flitWidth: Int, phitWidth: Int) extends Module { override def desiredName = s"PhitToFlit_p${phitWidth}_f${flitWidth}" val io = IO(new Bundle { val in = Flipped(Decoupled(new Phit(phitWidth))) val out = Decoupled(new Flit(flitWidth)) }) require(flitWidth >= phitWidth) val dataBeats = (flitWidth - 1) / phitWidth + 1 val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W))) val beat = RegInit(0.U(log2Ceil(dataBeats).W)) io.in.ready := io.out.ready || beat =/= (dataBeats-1).U io.out.valid := io.in.valid && beat === (dataBeats-1).U io.out.bits.flit := (if (dataBeats == 1) io.in.bits.phit else Cat(io.in.bits.phit, data.asUInt)) when (io.in.fire) { beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U) if (dataBeats > 1) { when (beat =/= (dataBeats-1).U) { data(beat) := io.in.bits.phit } } } } object PhitToFlit { def apply(phit: DecoupledIO[Phit], flitWidth: Int): DecoupledIO[Flit] = { val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth)) phit2flit.io.in <> phit phit2flit.io.out } def apply(phit: ValidIO[Phit], flitWidth: Int): ValidIO[Flit] = { val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth)) phit2flit.io.in.valid := phit.valid phit2flit.io.in.bits := phit.bits when (phit.valid) { assert(phit2flit.io.in.ready) } val out = Wire(Valid(new Flit(flitWidth))) out.valid := phit2flit.io.out.valid out.bits := phit2flit.io.out.bits phit2flit.io.out.ready := true.B out } } class PhitArbiter(phitWidth: Int, flitWidth: Int, channels: Int) extends Module { override def desiredName = s"PhitArbiter_p${phitWidth}_f${flitWidth}_n${channels}" val io = IO(new Bundle { val in = Flipped(Vec(channels, Decoupled(new Phit(phitWidth)))) val out = Decoupled(new Phit(phitWidth)) }) if (channels == 1) { io.out <> io.in(0) } else { val headerWidth = log2Ceil(channels) val headerBeats = (headerWidth - 1) / phitWidth + 1 val flitBeats = (flitWidth - 1) / phitWidth + 1 val beats = headerBeats + flitBeats val beat = RegInit(0.U(log2Ceil(beats).W)) val chosen_reg = Reg(UInt(headerWidth.W)) val chosen_prio = PriorityEncoder(io.in.map(_.valid)) val chosen = Mux(beat === 0.U, chosen_prio, chosen_reg) val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0) io.out.valid := VecInit(io.in.map(_.valid))(chosen) io.out.bits.phit := Mux(beat < headerBeats.U, chosen.asTypeOf(Vec(headerBeats, UInt(phitWidth.W)))(header_idx), VecInit(io.in.map(_.bits.phit))(chosen)) for (i <- 0 until channels) { io.in(i).ready := io.out.ready && beat >= headerBeats.U && chosen_reg === i.U } when (io.out.fire) { beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U) when (beat === 0.U) { chosen_reg := chosen_prio } } } } class PhitDemux(phitWidth: Int, flitWidth: Int, channels: Int) extends Module { override def desiredName = s"PhitDemux_p${phitWidth}_f${flitWidth}_n${channels}" val io = IO(new Bundle { val in = Flipped(Decoupled(new Phit(phitWidth))) val out = Vec(channels, Decoupled(new Phit(phitWidth))) }) if (channels == 1) { io.out(0) <> io.in } else { val headerWidth = log2Ceil(channels) val headerBeats = (headerWidth - 1) / phitWidth + 1 val flitBeats = (flitWidth - 1) / phitWidth + 1 val beats = headerBeats + flitBeats val beat = RegInit(0.U(log2Ceil(beats).W)) val channel_vec = Reg(Vec(headerBeats, UInt(phitWidth.W))) val channel = channel_vec.asUInt(log2Ceil(channels)-1,0) val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0) io.in.ready := beat < headerBeats.U || VecInit(io.out.map(_.ready))(channel) for (c <- 0 until channels) { io.out(c).valid := io.in.valid && beat >= headerBeats.U && channel === c.U io.out(c).bits.phit := io.in.bits.phit } when (io.in.fire) { beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U) when (beat < headerBeats.U) { channel_vec(header_idx) := io.in.bits.phit } } } } class DecoupledFlitToCreditedFlit(flitWidth: Int, bufferSz: Int) extends Module { override def desiredName = s"DecoupledFlitToCreditedFlit_f${flitWidth}_b${bufferSz}" val io = IO(new Bundle { val in = Flipped(Decoupled(new Flit(flitWidth))) val out = Decoupled(new Flit(flitWidth)) val credit = Flipped(Decoupled(new Flit(flitWidth))) }) val creditWidth = log2Ceil(bufferSz) require(creditWidth <= flitWidth) val credits = RegInit(0.U((creditWidth+1).W)) val credit_incr = io.out.fire val credit_decr = io.credit.fire when (credit_incr || credit_decr) { credits := credits + credit_incr - Mux(io.credit.valid, io.credit.bits.flit +& 1.U, 0.U) } io.out.valid := io.in.valid && credits < bufferSz.U io.out.bits.flit := io.in.bits.flit io.in.ready := io.out.ready && credits < bufferSz.U io.credit.ready := true.B } class CreditedFlitToDecoupledFlit(flitWidth: Int, bufferSz: Int) extends Module { override def desiredName = s"CreditedFlitToDecoupledFlit_f${flitWidth}_b${bufferSz}" val io = IO(new Bundle { val in = Flipped(Decoupled(new Flit(flitWidth))) val out = Decoupled(new Flit(flitWidth)) val credit = Decoupled(new Flit(flitWidth)) }) val creditWidth = log2Ceil(bufferSz) require(creditWidth <= flitWidth) val buffer = Module(new Queue(new Flit(flitWidth), bufferSz)) val credits = RegInit(0.U((creditWidth+1).W)) val credit_incr = buffer.io.deq.fire val credit_decr = io.credit.fire when (credit_incr || credit_decr) { credits := credit_incr + Mux(credit_decr, 0.U, credits) } buffer.io.enq.valid := io.in.valid buffer.io.enq.bits := io.in.bits io.in.ready := true.B when (io.in.valid) { assert(buffer.io.enq.ready) } io.out <> buffer.io.deq io.credit.valid := credits =/= 0.U io.credit.bits.flit := credits - 1.U }

module GenericSerializer_TLBeatw67_f32( // @[Serdes.scala:8:7] input clock, // @[Serdes.scala:8:7] input reset, // @[Serdes.scala:8:7] output io_in_ready, // @[Serdes.scala:10:14] input io_in_valid, // @[Serdes.scala:10:14] input [64:0] io_in_bits_payload, // @[Serdes.scala:10:14] input io_in_bits_head, // @[Serdes.scala:10:14] input io_in_bits_tail, // @[Serdes.scala:10:14] input io_out_ready, // @[Serdes.scala:10:14] output io_out_valid, // @[Serdes.scala:10:14] output [31:0] io_out_bits_flit, // @[Serdes.scala:10:14] output io_busy // @[Serdes.scala:10:14] ); wire io_out_valid_0; // @[Serdes.scala:8:7] wire io_in_valid_0 = io_in_valid; // @[Serdes.scala:8:7] wire [64:0] io_in_bits_payload_0 = io_in_bits_payload; // @[Serdes.scala:8:7] wire io_in_bits_head_0 = io_in_bits_head; // @[Serdes.scala:8:7] wire io_in_bits_tail_0 = io_in_bits_tail; // @[Serdes.scala:8:7] wire io_out_ready_0 = io_out_ready; // @[Serdes.scala:8:7] wire [0:0][31:0] _GEN = '{32'h0}; wire _io_in_ready_T_1; // @[Serdes.scala:22:31] wire _io_out_valid_T_1; // @[Serdes.scala:23:31] wire io_busy_0 = io_out_valid_0; // @[Serdes.scala:8:7] wire io_in_ready_0; // @[Serdes.scala:8:7] wire [31:0] io_out_bits_flit_0; // @[Serdes.scala:8:7] reg [31:0] data_1; // @[Serdes.scala:19:17] reg [31:0] data_2; // @[Serdes.scala:19:17] reg [1:0] beat; // @[Serdes.scala:20:21] wire _io_in_ready_T = ~(|beat); // @[Serdes.scala:20:21, :22:39] assign _io_in_ready_T_1 = io_out_ready_0 & _io_in_ready_T; // @[Serdes.scala:8:7, :22:{31,39}] assign io_in_ready_0 = _io_in_ready_T_1; // @[Serdes.scala:8:7, :22:31] wire _io_out_valid_T = |beat; // @[Serdes.scala:20:21, :22:39, :23:39] assign _io_out_valid_T_1 = io_in_valid_0 | _io_out_valid_T; // @[Serdes.scala:8:7, :23:{31,39}] assign io_out_valid_0 = _io_out_valid_T_1; // @[Serdes.scala:8:7, :23:31] wire _io_out_bits_flit_T = ~(|beat); // @[Serdes.scala:20:21, :22:39, :24:32] wire [65:0] _GEN_0 = {io_in_bits_payload_0, io_in_bits_head_0}; // @[Serdes.scala:8:7, :24:52] wire [65:0] io_out_bits_flit_hi; // @[Serdes.scala:24:52] assign io_out_bits_flit_hi = _GEN_0; // @[Serdes.scala:24:52] wire [65:0] hi; // @[Serdes.scala:29:34] assign hi = _GEN_0; // @[Serdes.scala:24:52, :29:34] wire [66:0] _io_out_bits_flit_T_1 = {io_out_bits_flit_hi, io_in_bits_tail_0}; // @[Serdes.scala:8:7, :24:52] wire [3:0][31:0] _GEN_1 = {_GEN, {{data_2}, {data_1}, {32'h0}}}; // @[Serdes.scala:19:17, :24:26] wire [66:0] _io_out_bits_flit_T_2 = _io_out_bits_flit_T ? _io_out_bits_flit_T_1 : {35'h0, _GEN_1[beat]}; // @[Serdes.scala:20:21, :24:{26,32,52}] assign io_out_bits_flit_0 = _io_out_bits_flit_T_2[31:0]; // @[Serdes.scala:8:7, :24:{20,26}] wire _beat_T = beat == 2'h2; // @[Serdes.scala:20:21, :27:22] wire [2:0] _beat_T_1 = {1'h0, beat} + 3'h1; // @[Serdes.scala:20:21, :27:53] wire [1:0] _beat_T_2 = _beat_T_1[1:0]; // @[Serdes.scala:27:53] wire [1:0] _beat_T_3 = _beat_T ? 2'h0 : _beat_T_2; // @[Serdes.scala:27:{16,22,53}] wire _T = io_out_ready_0 & io_out_valid_0; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[Serdes.scala:8:7] if (_T & ~(|beat)) begin // @[Decoupled.scala:51:35] data_1 <= hi[62:31]; // @[Serdes.scala:19:17, :29:34] data_2 <= {29'h0, hi[65:63]}; // @[Serdes.scala:19:17, :29:34] end if (reset) // @[Serdes.scala:8:7] beat <= 2'h0; // @[Serdes.scala:20:21] else if (_T) // @[Decoupled.scala:51:35] beat <= _beat_T_3; // @[Serdes.scala:20:21, :27:16] always @(posedge) assign io_in_ready = io_in_ready_0; // @[Serdes.scala:8:7] assign io_out_valid = io_out_valid_0; // @[Serdes.scala:8:7] assign io_out_bits_flit = io_out_bits_flit_0; // @[Serdes.scala:8:7] assign io_busy = io_busy_0; // @[Serdes.scala:8:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File RegisterRouter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes} import freechips.rocketchip.resources.{Device, Resource, ResourceBindings} import freechips.rocketchip.prci.{NoCrossing} import freechips.rocketchip.regmapper.{RegField, RegMapper, RegMapperParams, RegMapperInput, RegisterRouter} import freechips.rocketchip.util.{BundleField, ControlKey, ElaborationArtefacts, GenRegDescsAnno} import scala.math.min class TLRegisterRouterExtraBundle(val sourceBits: Int, val sizeBits: Int) extends Bundle { val source = UInt((sourceBits max 1).W) val size = UInt((sizeBits max 1).W) } case object TLRegisterRouterExtra extends ControlKey[TLRegisterRouterExtraBundle]("tlrr_extra") case class TLRegisterRouterExtraField(sourceBits: Int, sizeBits: Int) extends BundleField[TLRegisterRouterExtraBundle](TLRegisterRouterExtra, Output(new TLRegisterRouterExtraBundle(sourceBits, sizeBits)), x => { x.size := 0.U x.source := 0.U }) /** TLRegisterNode is a specialized TL SinkNode that encapsulates MMIO registers. * It provides functionality for describing and outputting metdata about the registers in several formats. * It also provides a concrete implementation of a regmap function that will be used * to wire a map of internal registers associated with this node to the node's interconnect port. */ case class TLRegisterNode( address: Seq[AddressSet], device: Device, deviceKey: String = "reg/control", concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false)( implicit valName: ValName) extends SinkNode(TLImp)(Seq(TLSlavePortParameters.v1( Seq(TLSlaveParameters.v1( address = address, resources = Seq(Resource(device, deviceKey)), executable = executable, supportsGet = TransferSizes(1, beatBytes), supportsPutPartial = TransferSizes(1, beatBytes), supportsPutFull = TransferSizes(1, beatBytes), fifoId = Some(0))), // requests are handled in order beatBytes = beatBytes, minLatency = min(concurrency, 1)))) with TLFormatNode // the Queue adds at most one cycle { val size = 1 << log2Ceil(1 + address.map(_.max).max - address.map(_.base).min) require (size >= beatBytes) address.foreach { case a => require (a.widen(size-1).base == address.head.widen(size-1).base, s"TLRegisterNode addresses (${address}) must be aligned to its size ${size}") } // Calling this method causes the matching TL2 bundle to be // configured to route all requests to the listed RegFields. def regmap(mapping: RegField.Map*) = { val (bundleIn, edge) = this.in(0) val a = bundleIn.a val d = bundleIn.d val fields = TLRegisterRouterExtraField(edge.bundle.sourceBits, edge.bundle.sizeBits) +: a.bits.params.echoFields val params = RegMapperParams(log2Up(size/beatBytes), beatBytes, fields) val in = Wire(Decoupled(new RegMapperInput(params))) in.bits.read := a.bits.opcode === TLMessages.Get in.bits.index := edge.addr_hi(a.bits) in.bits.data := a.bits.data in.bits.mask := a.bits.mask Connectable.waiveUnmatched(in.bits.extra, a.bits.echo) match { case (lhs, rhs) => lhs :<= rhs } val a_extra = in.bits.extra(TLRegisterRouterExtra) a_extra.source := a.bits.source a_extra.size := a.bits.size // Invoke the register map builder val out = RegMapper(beatBytes, concurrency, undefZero, in, mapping:_*) // No flow control needed in.valid := a.valid a.ready := in.ready d.valid := out.valid out.ready := d.ready // We must restore the size to enable width adapters to work val d_extra = out.bits.extra(TLRegisterRouterExtra) d.bits := edge.AccessAck(toSource = d_extra.source, lgSize = d_extra.size) // avoid a Mux on the data bus by manually overriding two fields d.bits.data := out.bits.data Connectable.waiveUnmatched(d.bits.echo, out.bits.extra) match { case (lhs, rhs) => lhs :<= rhs } d.bits.opcode := Mux(out.bits.read, TLMessages.AccessAckData, TLMessages.AccessAck) // Tie off unused channels bundleIn.b.valid := false.B bundleIn.c.ready := true.B bundleIn.e.ready := true.B genRegDescsJson(mapping:_*) } def genRegDescsJson(mapping: RegField.Map*): Unit = { // Dump out the register map for documentation purposes. val base = address.head.base val baseHex = s"0x${base.toInt.toHexString}" val name = s"${device.describe(ResourceBindings()).name}.At${baseHex}" val json = GenRegDescsAnno.serialize(base, name, mapping:_*) var suffix = 0 while( ElaborationArtefacts.contains(s"${baseHex}.${suffix}.regmap.json")) { suffix = suffix + 1 } ElaborationArtefacts.add(s"${baseHex}.${suffix}.regmap.json", json) val module = Module.currentModule.get.asInstanceOf[RawModule] GenRegDescsAnno.anno( module, base, mapping:_*) } } /** Mix HasTLControlRegMap into any subclass of RegisterRouter to gain helper functions for attaching a device control register map to TileLink. * - The intended use case is that controlNode will diplomatically publish a SW-visible device's memory-mapped control registers. * - Use the clock crossing helper controlXing to externally connect controlNode to a TileLink interconnect. * - Use the mapping helper function regmap to internally fill out the space of device control registers. */ trait HasTLControlRegMap { this: RegisterRouter => protected val controlNode = TLRegisterNode( address = address, device = device, deviceKey = "reg/control", concurrency = concurrency, beatBytes = beatBytes, undefZero = undefZero, executable = executable) // Externally, this helper should be used to connect the register control port to a bus val controlXing: TLInwardClockCrossingHelper = this.crossIn(controlNode) // Backwards-compatibility default node accessor with no clock crossing lazy val node: TLInwardNode = controlXing(NoCrossing) // Internally, this function should be used to populate the control port with registers protected def regmap(mapping: RegField.Map*): Unit = { controlNode.regmap(mapping:_*) } } File MuxLiteral.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.log2Ceil import scala.reflect.ClassTag /* MuxLiteral creates a lookup table from a key to a list of values. * Unlike MuxLookup, the table keys must be exclusive literals. */ object MuxLiteral { def apply[T <: Data:ClassTag](index: UInt, default: T, first: (UInt, T), rest: (UInt, T)*): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[(UInt, T)]): T = MuxTable(index, default, cases.map { case (k, v) => (k.litValue, v) }) } object MuxSeq { def apply[T <: Data:ClassTag](index: UInt, default: T, first: T, rest: T*): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[T]): T = MuxTable(index, default, cases.zipWithIndex.map { case (v, i) => (BigInt(i), v) }) } object MuxTable { def apply[T <: Data:ClassTag](index: UInt, default: T, first: (BigInt, T), rest: (BigInt, T)*): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[(BigInt, T)]): T = { /* All keys must be >= 0 and distinct */ cases.foreach { case (k, _) => require (k >= 0) } require (cases.map(_._1).distinct.size == cases.size) /* Filter out any cases identical to the default */ val simple = cases.filter { case (k, v) => !default.isLit || !v.isLit || v.litValue != default.litValue } val maxKey = (BigInt(0) +: simple.map(_._1)).max val endIndex = BigInt(1) << log2Ceil(maxKey+1) if (simple.isEmpty) { default } else if (endIndex <= 2*simple.size) { /* The dense encoding case uses a Vec */ val table = Array.fill(endIndex.toInt) { default } simple.foreach { case (k, v) => table(k.toInt) = v } Mux(index >= endIndex.U, default, VecInit(table)(index)) } else { /* The sparse encoding case uses switch */ val out = WireDefault(default) simple.foldLeft(new chisel3.util.SwitchContext(index, None, Set.empty)) { case (acc, (k, v)) => acc.is (k.U) { out := v } } out } } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Debug.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.devices.debug import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.amba.apb.{APBFanout, APBToTL} import freechips.rocketchip.devices.debug.systembusaccess.{SBToTL, SystemBusAccessModule} import freechips.rocketchip.devices.tilelink.{DevNullParams, TLBusBypass, TLError} import freechips.rocketchip.diplomacy.{AddressSet, BufferParams} import freechips.rocketchip.resources.{Description, Device, Resource, ResourceBindings, ResourceString, SimpleDevice} import freechips.rocketchip.interrupts.{IntNexusNode, IntSinkParameters, IntSinkPortParameters, IntSourceParameters, IntSourcePortParameters, IntSyncCrossingSource, IntSyncIdentityNode} import freechips.rocketchip.regmapper.{RegField, RegFieldAccessType, RegFieldDesc, RegFieldGroup, RegFieldWrType, RegReadFn, RegWriteFn} import freechips.rocketchip.rocket.{CSRs, Instructions} import freechips.rocketchip.tile.MaxHartIdBits import freechips.rocketchip.tilelink.{TLAsyncCrossingSink, TLAsyncCrossingSource, TLBuffer, TLRegisterNode, TLXbar} import freechips.rocketchip.util.{Annotated, AsyncBundle, AsyncQueueParams, AsyncResetSynchronizerShiftReg, FromAsyncBundle, ParameterizedBundle, ResetSynchronizerShiftReg, ToAsyncBundle} import freechips.rocketchip.util.SeqBoolBitwiseOps import freechips.rocketchip.util.SeqToAugmentedSeq import freechips.rocketchip.util.BooleanToAugmentedBoolean object DsbBusConsts { def sbAddrWidth = 12 def sbIdWidth = 10 } object DsbRegAddrs{ // These are used by the ROM. def HALTED = 0x100 def GOING = 0x104 def RESUMING = 0x108 def EXCEPTION = 0x10C def WHERETO = 0x300 // This needs to be aligned for up to lq/sq // This shows up in HartInfo, and needs to be aligned // to enable up to LQ/SQ instructions. def DATA = 0x380 // We want DATA to immediately follow PROGBUF so that we can // use them interchangeably. Leave another slot if there is an // implicit ebreak. def PROGBUF(cfg:DebugModuleParams) = { val tmp = DATA - (cfg.nProgramBufferWords * 4) if (cfg.hasImplicitEbreak) (tmp - 4) else tmp } // This is unused if hasImpEbreak is false, and just points to the end of the PROGBUF. def IMPEBREAK(cfg: DebugModuleParams) = { DATA - 4 } // We want abstract to be immediately before PROGBUF // because we auto-generate 2 (or 5) instructions. def ABSTRACT(cfg:DebugModuleParams) = PROGBUF(cfg) - (cfg.nAbstractInstructions * 4) def FLAGS = 0x400 def ROMBASE = 0x800 } /** Enumerations used both in the hardware * and in the configuration specification. */ object DebugModuleAccessType extends scala.Enumeration { type DebugModuleAccessType = Value val Access8Bit, Access16Bit, Access32Bit, Access64Bit, Access128Bit = Value } object DebugAbstractCommandError extends scala.Enumeration { type DebugAbstractCommandError = Value val Success, ErrBusy, ErrNotSupported, ErrException, ErrHaltResume = Value } object DebugAbstractCommandType extends scala.Enumeration { type DebugAbstractCommandType = Value val AccessRegister, QuickAccess = Value } /** Parameters exposed to the top-level design, set based on * external requirements, etc. * * This object checks that the parameters conform to the * full specification. The implementation which receives this * object can perform more checks on what that implementation * actually supports. * @param nComponents Number of components to support debugging. * @param baseAddress Base offest for debugEntry and debugException * @param nDMIAddrSize Size of the Debug Bus Address * @param nAbstractDataWords Number of 32-bit words for Abstract Commands * @param nProgamBufferWords Number of 32-bit words for Program Buffer * @param hasBusMaster Whether or not a bus master should be included * @param clockGate Whether or not to use dmactive as the clockgate for debug module * @param maxSupportedSBAccess Maximum transaction size supported by System Bus Access logic. * @param supportQuickAccess Whether or not to support the quick access command. * @param supportHartArray Whether or not to implement the hart array register (if >1 hart). * @param nHaltGroups Number of halt groups * @param nExtTriggers Number of external triggers * @param hasHartResets Feature to reset all the currently selected harts * @param hasImplicitEbreak There is an additional RO program buffer word containing an ebreak * @param crossingHasSafeReset Include "safe" logic in Async Crossings so that only one side needs to be reset. */ case class DebugModuleParams ( baseAddress : BigInt = BigInt(0), nDMIAddrSize : Int = 7, nProgramBufferWords: Int = 16, nAbstractDataWords : Int = 4, nScratch : Int = 1, hasBusMaster : Boolean = false, clockGate : Boolean = true, maxSupportedSBAccess : Int = 32, supportQuickAccess : Boolean = false, supportHartArray : Boolean = true, nHaltGroups : Int = 1, nExtTriggers : Int = 0, hasHartResets : Boolean = false, hasImplicitEbreak : Boolean = false, hasAuthentication : Boolean = false, crossingHasSafeReset : Boolean = true ) { require ((nDMIAddrSize >= 7) && (nDMIAddrSize <= 32), s"Legal DMIAddrSize is 7-32, not ${nDMIAddrSize}") require ((nAbstractDataWords > 0) && (nAbstractDataWords <= 16), s"Legal nAbstractDataWords is 0-16, not ${nAbstractDataWords}") require ((nProgramBufferWords >= 0) && (nProgramBufferWords <= 16), s"Legal nProgramBufferWords is 0-16, not ${nProgramBufferWords}") require (nHaltGroups < 32, s"Legal nHaltGroups is 0-31, not ${nHaltGroups}") require (nExtTriggers <= 16, s"Legal nExtTriggers is 0-16, not ${nExtTriggers}") if (supportQuickAccess) { // TODO: Check that quick access requirements are met. } def address = AddressSet(baseAddress, 0xFFF) /** the base address of DM */ def atzero = (baseAddress == 0) /** The number of generated instructions * * When the base address is not zero, we need more instruction also, * more dscratch registers) to load/store memory mapped data register * because they may no longer be directly addressible with x0 + 12-bit imm */ def nAbstractInstructions = if (atzero) 2 else 5 def debugEntry: BigInt = baseAddress + 0x800 def debugException: BigInt = baseAddress + 0x808 def nDscratch: Int = if (atzero) 1 else 2 } object DefaultDebugModuleParams { def apply(xlen:Int /*TODO , val configStringAddr: Int*/): DebugModuleParams = { new DebugModuleParams().copy( nAbstractDataWords = (if (xlen == 32) 1 else if (xlen == 64) 2 else 4), maxSupportedSBAccess = xlen ) } } case object DebugModuleKey extends Field[Option[DebugModuleParams]](Some(DebugModuleParams())) /** Functional parameters exposed to the design configuration. * * hartIdToHartSel: For systems where hart ids are not 1:1 with hartsel, provide the mapping. * hartSelToHartId: Provide inverse mapping of the above */ case class DebugModuleHartSelFuncs ( hartIdToHartSel : (UInt) => UInt = (x:UInt) => x, hartSelToHartId : (UInt) => UInt = (x:UInt) => x ) case object DebugModuleHartSelKey extends Field(DebugModuleHartSelFuncs()) class DebugExtTriggerOut (val nExtTriggers: Int) extends Bundle { val req = Output(UInt(nExtTriggers.W)) val ack = Input(UInt(nExtTriggers.W)) } class DebugExtTriggerIn (val nExtTriggers: Int) extends Bundle { val req = Input(UInt(nExtTriggers.W)) val ack = Output(UInt(nExtTriggers.W)) } class DebugExtTriggerIO () (implicit val p: Parameters) extends ParameterizedBundle()(p) { val out = new DebugExtTriggerOut(p(DebugModuleKey).get.nExtTriggers) val in = new DebugExtTriggerIn (p(DebugModuleKey).get.nExtTriggers) } class DebugAuthenticationIO () (implicit val p: Parameters) extends ParameterizedBundle()(p) { val dmactive = Output(Bool()) val dmAuthWrite = Output(Bool()) val dmAuthRead = Output(Bool()) val dmAuthWdata = Output(UInt(32.W)) val dmAuthBusy = Input(Bool()) val dmAuthRdata = Input(UInt(32.W)) val dmAuthenticated = Input(Bool()) } // ***************************************** // Module Interfaces // // ***************************************** /** Control signals for Inner, generated in Outer * {{{ * run control: resumreq, ackhavereset, halt-on-reset mask * hart select: hasel, hartsel and the hart array mask * }}} */ class DebugInternalBundle (val nComponents: Int)(implicit val p: Parameters) extends ParameterizedBundle()(p) { /** resume request */ val resumereq = Bool() /** hart select */ val hartsel = UInt(10.W) /** reset acknowledge */ val ackhavereset = Bool() /** hart array enable */ val hasel = Bool() /** hart array mask */ val hamask = Vec(nComponents, Bool()) /** halt-on-reset mask */ val hrmask = Vec(nComponents, Bool()) } /** structure for top-level Debug Module signals which aren't the bus interfaces. */ class DebugCtrlBundle (nComponents: Int)(implicit val p: Parameters) extends ParameterizedBundle()(p) { /** debug availability status for all harts */ val debugUnavail = Input(Vec(nComponents, Bool())) /** reset signal * * for every part of the hardware platform, * including every hart, except for the DM and any * logic required to access the DM */ val ndreset = Output(Bool()) /** reset signal for the DM itself */ val dmactive = Output(Bool()) /** dmactive acknowlege */ val dmactiveAck = Input(Bool()) } // ***************************************** // Debug Module // // ***************************************** /** Parameterized version of the Debug Module defined in the * RISC-V Debug Specification * * DebugModule is a slave to two asynchronous masters: * The Debug Bus (DMI) -- This is driven by an external debugger * * The System Bus -- This services requests from the cores. Generally * this interface should only be active at the request * of the debugger, but the Debug Module may also * provide the default MTVEC since it is mapped * to address 0x0. * * DebugModule is responsible for control registers and RAM, and * Debug ROM. It runs partially off of the dmiClk (e.g. TCK) and * the TL clock. Therefore, it is divided into "Outer" portion (running * off dmiClock and dmiReset) and "Inner" (running off tl_clock and tl_reset). * This allows DMCONTROL.haltreq, hartsel, hasel, hawindowsel, hawindow, dmactive, * and ndreset to be modified even while the Core is in reset or not being clocked. * Not all reads from the Debugger to the Debug Module will actually complete * in these scenarios either, they will just block until tl_clock and tl_reset * allow them to complete. This is not strictly necessary for * proper debugger functionality. */ // Local reg mapper function : Notify when written, but give the value as well. object WNotifyWire { def apply(n: Int, value: UInt, set: Bool, name: String, desc: String) : RegField = { RegField(n, 0.U, RegWriteFn((valid, data) => { set := valid value := data true.B }), Some(RegFieldDesc(name = name, desc = desc, access = RegFieldAccessType.W))) } } // Local reg mapper function : Notify when accessed either as read or write. object RWNotify { def apply (n: Int, rVal: UInt, wVal: UInt, rNotify: Bool, wNotify: Bool, desc: Option[RegFieldDesc] = None): RegField = { RegField(n, RegReadFn ((ready) => {rNotify := ready ; (true.B, rVal)}), RegWriteFn((valid, data) => { wNotify := valid when (valid) {wVal := data} true.B } ), desc) } } // Local reg mapper function : Notify with value when written, take read input as presented. // This allows checking or correcting the write value before storing it in the register field. object WNotifyVal { def apply(n: Int, rVal: UInt, wVal: UInt, wNotify: Bool, desc: RegFieldDesc): RegField = { RegField(n, rVal, RegWriteFn((valid, data) => { wNotify := valid wVal := data true.B } ), desc) } } class TLDebugModuleOuter(device: Device)(implicit p: Parameters) extends LazyModule { // For Shorter Register Names import DMI_RegAddrs._ val cfg = p(DebugModuleKey).get val intnode = IntNexusNode( sourceFn = { _ => IntSourcePortParameters(Seq(IntSourceParameters(1, Seq(Resource(device, "int"))))) }, sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) }, outputRequiresInput = false) val dmiNode = TLRegisterNode ( address = AddressSet.misaligned(DMI_DMCONTROL << 2, 4) ++ AddressSet.misaligned(DMI_HARTINFO << 2, 4) ++ AddressSet.misaligned(DMI_HAWINDOWSEL << 2, 4) ++ AddressSet.misaligned(DMI_HAWINDOW << 2, 4), device = device, beatBytes = 4, executable = false ) lazy val module = new Impl class Impl extends LazyModuleImp(this) { require (intnode.edges.in.size == 0, "Debug Module does not accept interrupts") val nComponents = intnode.out.size def getNComponents = () => nComponents val supportHartArray = cfg.supportHartArray && (nComponents > 1) // no hart array if only one hart val io = IO(new Bundle { /** structure for top-level Debug Module signals which aren't the bus interfaces. */ val ctrl = (new DebugCtrlBundle(nComponents)) /** control signals for Inner, generated in Outer */ val innerCtrl = new DecoupledIO(new DebugInternalBundle(nComponents)) /** debug interruption from Inner to Outer * * contains 2 type of debug interruption causes: * - halt group * - halt-on-reset */ val hgDebugInt = Input(Vec(nComponents, Bool())) /** hart reset request to core */ val hartResetReq = cfg.hasHartResets.option(Output(Vec(nComponents, Bool()))) /** authentication support */ val dmAuthenticated = cfg.hasAuthentication.option(Input(Bool())) }) val omRegMap = withReset(reset.asAsyncReset) { // FIXME: Instead of casting reset to ensure it is Async, assert/require reset.Type == AsyncReset (when this feature is available) val dmAuthenticated = io.dmAuthenticated.map( dma => ResetSynchronizerShiftReg(in=dma, sync=3, name=Some("dmAuthenticated_sync"))).getOrElse(true.B) //----DMCONTROL (The whole point of 'Outer' is to maintain this register on dmiClock (e.g. TCK) domain, so that it // can be written even if 'Inner' is not being clocked or is in reset. This allows halting // harts while the rest of the system is in reset. It doesn't really allow any other // register accesses, which will keep returning 'busy' to the debugger interface. val DMCONTROLReset = WireInit(0.U.asTypeOf(new DMCONTROLFields())) val DMCONTROLNxt = WireInit(0.U.asTypeOf(new DMCONTROLFields())) val DMCONTROLReg = RegNext(next=DMCONTROLNxt, init=0.U.asTypeOf(DMCONTROLNxt)).suggestName("DMCONTROLReg") val hartsel_mask = if (nComponents > 1) ((1 << p(MaxHartIdBits)) - 1).U else 0.U val DMCONTROLWrData = WireInit(0.U.asTypeOf(new DMCONTROLFields())) val dmactiveWrEn = WireInit(false.B) val ndmresetWrEn = WireInit(false.B) val clrresethaltreqWrEn = WireInit(false.B) val setresethaltreqWrEn = WireInit(false.B) val hartselloWrEn = WireInit(false.B) val haselWrEn = WireInit(false.B) val ackhaveresetWrEn = WireInit(false.B) val hartresetWrEn = WireInit(false.B) val resumereqWrEn = WireInit(false.B) val haltreqWrEn = WireInit(false.B) val dmactive = DMCONTROLReg.dmactive DMCONTROLNxt := DMCONTROLReg when (~dmactive) { DMCONTROLNxt := DMCONTROLReset } .otherwise { when (dmAuthenticated && ndmresetWrEn) { DMCONTROLNxt.ndmreset := DMCONTROLWrData.ndmreset } when (dmAuthenticated && hartselloWrEn) { DMCONTROLNxt.hartsello := DMCONTROLWrData.hartsello & hartsel_mask} when (dmAuthenticated && haselWrEn) { DMCONTROLNxt.hasel := DMCONTROLWrData.hasel } when (dmAuthenticated && hartresetWrEn) { DMCONTROLNxt.hartreset := DMCONTROLWrData.hartreset } when (dmAuthenticated && haltreqWrEn) { DMCONTROLNxt.haltreq := DMCONTROLWrData.haltreq } } // Put this last to override its own effects. when (dmactiveWrEn) { DMCONTROLNxt.dmactive := DMCONTROLWrData.dmactive } //----HARTINFO // DATA registers are mapped to memory. The dataaddr field of HARTINFO has only // 12 bits and assumes the DM base is 0. If not at 0, then HARTINFO reads as 0 // (implying nonexistence according to the Debug Spec). val HARTINFORdData = WireInit(0.U.asTypeOf(new HARTINFOFields())) if (cfg.atzero) when (dmAuthenticated) { HARTINFORdData.dataaccess := true.B HARTINFORdData.datasize := cfg.nAbstractDataWords.U HARTINFORdData.dataaddr := DsbRegAddrs.DATA.U HARTINFORdData.nscratch := cfg.nScratch.U } //-------------------------------------------------------------- // Hart array mask and window // hamask is hart array mask(1 bit per component), which doesn't include the hart selected by dmcontrol.hartsello // HAWINDOWSEL selects a 32-bit slice of HAMASK to be visible for read/write in HAWINDOW //-------------------------------------------------------------- val hamask = WireInit(VecInit(Seq.fill(nComponents) {false.B} )) def haWindowSize = 32 // The following need to be declared even if supportHartArray is false due to reference // at compile time by dmiNode.regmap val HAWINDOWSELWrData = WireInit(0.U.asTypeOf(new HAWINDOWSELFields())) val HAWINDOWSELWrEn = WireInit(false.B) val HAWINDOWRdData = WireInit(0.U.asTypeOf(new HAWINDOWFields())) val HAWINDOWWrData = WireInit(0.U.asTypeOf(new HAWINDOWFields())) val HAWINDOWWrEn = WireInit(false.B) /** whether the hart is selected */ def hartSelected(hart: Int): Bool = { ((io.innerCtrl.bits.hartsel === hart.U) || (if (supportHartArray) io.innerCtrl.bits.hasel && io.innerCtrl.bits.hamask(hart) else false.B)) } val HAWINDOWSELNxt = WireInit(0.U.asTypeOf(new HAWINDOWSELFields())) val HAWINDOWSELReg = RegNext(next=HAWINDOWSELNxt, init=0.U.asTypeOf(HAWINDOWSELNxt)) if (supportHartArray) { val HAWINDOWSELReset = WireInit(0.U.asTypeOf(new HAWINDOWSELFields())) HAWINDOWSELNxt := HAWINDOWSELReg when (~dmactive || ~dmAuthenticated) { HAWINDOWSELNxt := HAWINDOWSELReset } .otherwise { when (HAWINDOWSELWrEn) { // Unneeded upper bits of HAWINDOWSEL are tied to 0. Entire register is 0 if all harts fit in one window if (nComponents > haWindowSize) { HAWINDOWSELNxt.hawindowsel := HAWINDOWSELWrData.hawindowsel & ((1 << (log2Up(nComponents) - 5)) - 1).U } else { HAWINDOWSELNxt.hawindowsel := 0.U } } } val numHAMASKSlices = ((nComponents - 1)/haWindowSize)+1 HAWINDOWRdData.maskdata := 0.U // default, overridden below // for each slice,use a hamaskReg to store the selection info for (ii <- 0 until numHAMASKSlices) { val sliceMask = if (nComponents > ((ii*haWindowSize) + haWindowSize-1)) (BigInt(1) << haWindowSize) - 1 // All harts in this slice exist else (BigInt(1)<<(nComponents - (ii*haWindowSize))) - 1 // Partial last slice val HAMASKRst = WireInit(0.U.asTypeOf(new HAWINDOWFields())) val HAMASKNxt = WireInit(0.U.asTypeOf(new HAWINDOWFields())) val HAMASKReg = RegNext(next=HAMASKNxt, init=0.U.asTypeOf(HAMASKNxt)) when (ii.U === HAWINDOWSELReg.hawindowsel) { HAWINDOWRdData.maskdata := HAMASKReg.asUInt & sliceMask.U } HAMASKNxt.maskdata := HAMASKReg.asUInt when (~dmactive || ~dmAuthenticated) { HAMASKNxt := HAMASKRst }.otherwise { when (HAWINDOWWrEn && (ii.U === HAWINDOWSELReg.hawindowsel)) { HAMASKNxt.maskdata := HAWINDOWWrData.maskdata } } // drive each slice of hamask with stored HAMASKReg or with new value being written for (jj <- 0 until haWindowSize) { if (((ii*haWindowSize) + jj) < nComponents) { val tempWrData = HAWINDOWWrData.maskdata.asBools val tempMaskReg = HAMASKReg.asUInt.asBools when (HAWINDOWWrEn && (ii.U === HAWINDOWSELReg.hawindowsel)) { hamask(ii*haWindowSize + jj) := tempWrData(jj) }.otherwise { hamask(ii*haWindowSize + jj) := tempMaskReg(jj) } } } } } //-------------------------------------------------------------- // Halt-on-reset // hrmaskReg is current set of harts that should halt-on-reset // Reset state (dmactive=0) is all zeroes // Bits are set by writing 1 to DMCONTROL.setresethaltreq // Bits are cleared by writing 1 to DMCONTROL.clrresethaltreq // Spec says if both are 1, then clrresethaltreq is executed // hrmask is the halt-on-reset mask which will be sent to inner //-------------------------------------------------------------- val hrmask = Wire(Vec(nComponents, Bool())) val hrmaskNxt = Wire(Vec(nComponents, Bool())) val hrmaskReg = RegNext(next=hrmaskNxt, init=0.U.asTypeOf(hrmaskNxt)).suggestName("hrmaskReg") hrmaskNxt := hrmaskReg for (component <- 0 until nComponents) { when (~dmactive || ~dmAuthenticated) { hrmaskNxt(component) := false.B }.elsewhen (clrresethaltreqWrEn && DMCONTROLWrData.clrresethaltreq && hartSelected(component)) { hrmaskNxt(component) := false.B }.elsewhen (setresethaltreqWrEn && DMCONTROLWrData.setresethaltreq && hartSelected(component)) { hrmaskNxt(component) := true.B } } hrmask := hrmaskNxt val dmControlRegFields = RegFieldGroup("dmcontrol", Some("debug module control register"), Seq( WNotifyVal(1, DMCONTROLReg.dmactive & io.ctrl.dmactiveAck, DMCONTROLWrData.dmactive, dmactiveWrEn, RegFieldDesc("dmactive", "debug module active", reset=Some(0))), WNotifyVal(1, DMCONTROLReg.ndmreset, DMCONTROLWrData.ndmreset, ndmresetWrEn, RegFieldDesc("ndmreset", "debug module reset output", reset=Some(0))), WNotifyVal(1, 0.U, DMCONTROLWrData.clrresethaltreq, clrresethaltreqWrEn, RegFieldDesc("clrresethaltreq", "clear reset halt request", reset=Some(0), access=RegFieldAccessType.W)), WNotifyVal(1, 0.U, DMCONTROLWrData.setresethaltreq, setresethaltreqWrEn, RegFieldDesc("setresethaltreq", "set reset halt request", reset=Some(0), access=RegFieldAccessType.W)), RegField(12), if (nComponents > 1) WNotifyVal(p(MaxHartIdBits), DMCONTROLReg.hartsello, DMCONTROLWrData.hartsello, hartselloWrEn, RegFieldDesc("hartsello", "hart select low", reset=Some(0))) else RegField(1), if (nComponents > 1) RegField(10-p(MaxHartIdBits)) else RegField(9), if (supportHartArray) WNotifyVal(1, DMCONTROLReg.hasel, DMCONTROLWrData.hasel, haselWrEn, RegFieldDesc("hasel", "hart array select", reset=Some(0))) else RegField(1), RegField(1), WNotifyVal(1, 0.U, DMCONTROLWrData.ackhavereset, ackhaveresetWrEn, RegFieldDesc("ackhavereset", "acknowledge reset", reset=Some(0), access=RegFieldAccessType.W)), if (cfg.hasHartResets) WNotifyVal(1, DMCONTROLReg.hartreset, DMCONTROLWrData.hartreset, hartresetWrEn, RegFieldDesc("hartreset", "hart reset request", reset=Some(0))) else RegField(1), WNotifyVal(1, 0.U, DMCONTROLWrData.resumereq, resumereqWrEn, RegFieldDesc("resumereq", "resume request", reset=Some(0), access=RegFieldAccessType.W)), WNotifyVal(1, DMCONTROLReg.haltreq, DMCONTROLWrData.haltreq, haltreqWrEn, // Spec says W, but maintaining previous behavior RegFieldDesc("haltreq", "halt request", reset=Some(0))) )) val hartinfoRegFields = RegFieldGroup("dmi_hartinfo", Some("hart information"), Seq( RegField.r(12, HARTINFORdData.dataaddr, RegFieldDesc("dataaddr", "data address", reset=Some(if (cfg.atzero) DsbRegAddrs.DATA else 0))), RegField.r(4, HARTINFORdData.datasize, RegFieldDesc("datasize", "number of DATA registers", reset=Some(if (cfg.atzero) cfg.nAbstractDataWords else 0))), RegField.r(1, HARTINFORdData.dataaccess, RegFieldDesc("dataaccess", "data access type", reset=Some(if (cfg.atzero) 1 else 0))), RegField(3), RegField.r(4, HARTINFORdData.nscratch, RegFieldDesc("nscratch", "number of scratch registers", reset=Some(if (cfg.atzero) cfg.nScratch else 0))) )) //-------------------------------------------------------------- // DMI register decoder for Outer //-------------------------------------------------------------- // regmap addresses are byte offsets from lowest address def DMI_DMCONTROL_OFFSET = 0 def DMI_HARTINFO_OFFSET = ((DMI_HARTINFO - DMI_DMCONTROL) << 2) def DMI_HAWINDOWSEL_OFFSET = ((DMI_HAWINDOWSEL - DMI_DMCONTROL) << 2) def DMI_HAWINDOW_OFFSET = ((DMI_HAWINDOW - DMI_DMCONTROL) << 2) val omRegMap = dmiNode.regmap( DMI_DMCONTROL_OFFSET -> dmControlRegFields, DMI_HARTINFO_OFFSET -> hartinfoRegFields, DMI_HAWINDOWSEL_OFFSET -> (if (supportHartArray && (nComponents > 32)) Seq( WNotifyVal(log2Up(nComponents)-5, HAWINDOWSELReg.hawindowsel, HAWINDOWSELWrData.hawindowsel, HAWINDOWSELWrEn, RegFieldDesc("hawindowsel", "hart array window select", reset=Some(0)))) else Nil), DMI_HAWINDOW_OFFSET -> (if (supportHartArray) Seq( WNotifyVal(if (nComponents > 31) 32 else nComponents, HAWINDOWRdData.maskdata, HAWINDOWWrData.maskdata, HAWINDOWWrEn, RegFieldDesc("hawindow", "hart array window", reset=Some(0), volatile=(nComponents > 32)))) else Nil) ) //-------------------------------------------------------------- // Interrupt Registers //-------------------------------------------------------------- val debugIntNxt = WireInit(VecInit(Seq.fill(nComponents) {false.B} )) val debugIntRegs = RegNext(next=debugIntNxt, init=0.U.asTypeOf(debugIntNxt)).suggestName("debugIntRegs") debugIntNxt := debugIntRegs val (intnode_out, _) = intnode.out.unzip for (component <- 0 until nComponents) { intnode_out(component)(0) := debugIntRegs(component) | io.hgDebugInt(component) } // sends debug interruption to Core when dmcs.haltreq is set, for (component <- 0 until nComponents) { when (~dmactive || ~dmAuthenticated) { debugIntNxt(component) := false.B }. otherwise { when (haltreqWrEn && ((DMCONTROLWrData.hartsello === component.U) || (if (supportHartArray) DMCONTROLWrData.hasel && hamask(component) else false.B))) { debugIntNxt(component) := DMCONTROLWrData.haltreq } } } // Halt request registers are set & cleared by writes to DMCONTROL.haltreq // resumereq also causes the core to execute a 'dret', // so resumereq is passed through to Inner. // hartsel/hasel/hamask must also be used by the DebugModule state machine, // so it is passed to Inner. // These registers ensure that requests to dmInner are not lost if inner clock isn't running or requests occur too close together. // If the innerCtrl async queue is not ready, the notification will be posted and held until ready is received. // Additional notifications that occur while one is already waiting update the pending data so that the last value written is sent. // Volatile events resumereq and ackhavereset are registered when they occur and remain pending until ready is received. val innerCtrlValid = Wire(Bool()) val innerCtrlValidReg = RegInit(false.B).suggestName("innerCtrlValidReg") val innerCtrlResumeReqReg = RegInit(false.B).suggestName("innerCtrlResumeReqReg") val innerCtrlAckHaveResetReg = RegInit(false.B).suggestName("innerCtrlAckHaveResetReg") innerCtrlValid := hartselloWrEn | resumereqWrEn | ackhaveresetWrEn | setresethaltreqWrEn | clrresethaltreqWrEn | haselWrEn | (HAWINDOWWrEn & supportHartArray.B) innerCtrlValidReg := io.innerCtrl.valid & ~io.innerCtrl.ready // Hold innerctrl request until the async queue accepts it innerCtrlResumeReqReg := io.innerCtrl.bits.resumereq & ~io.innerCtrl.ready // Hold resumereq until accepted innerCtrlAckHaveResetReg := io.innerCtrl.bits.ackhavereset & ~io.innerCtrl.ready // Hold ackhavereset until accepted io.innerCtrl.valid := innerCtrlValid | innerCtrlValidReg io.innerCtrl.bits.hartsel := Mux(hartselloWrEn, DMCONTROLWrData.hartsello, DMCONTROLReg.hartsello) io.innerCtrl.bits.resumereq := (resumereqWrEn & DMCONTROLWrData.resumereq) | innerCtrlResumeReqReg io.innerCtrl.bits.ackhavereset := (ackhaveresetWrEn & DMCONTROLWrData.ackhavereset) | innerCtrlAckHaveResetReg io.innerCtrl.bits.hrmask := hrmask if (supportHartArray) { io.innerCtrl.bits.hasel := Mux(haselWrEn, DMCONTROLWrData.hasel, DMCONTROLReg.hasel) io.innerCtrl.bits.hamask := hamask } else { io.innerCtrl.bits.hasel := DontCare io.innerCtrl.bits.hamask := DontCare } io.ctrl.ndreset := DMCONTROLReg.ndmreset io.ctrl.dmactive := DMCONTROLReg.dmactive // hart reset mechanism implementation if (cfg.hasHartResets) { val hartResetNxt = Wire(Vec(nComponents, Bool())) val hartResetReg = RegNext(next=hartResetNxt, init=0.U.asTypeOf(hartResetNxt)) for (component <- 0 until nComponents) { hartResetNxt(component) := DMCONTROLReg.hartreset & hartSelected(component) io.hartResetReq.get(component) := hartResetReg(component) } } omRegMap // FIXME: Remove this when withReset is removed }} } // wrap a Outer with a DMIToTL, derived by dmi clock & reset class TLDebugModuleOuterAsync(device: Device)(implicit p: Parameters) extends LazyModule { val cfg = p(DebugModuleKey).get val dmiXbar = LazyModule (new TLXbar(nameSuffix = Some("dmixbar"))) val dmi2tlOpt = (!p(ExportDebug).apb).option({ val dmi2tl = LazyModule(new DMIToTL()) dmiXbar.node := dmi2tl.node dmi2tl }) val apbNodeOpt = p(ExportDebug).apb.option({ val apb2tl = LazyModule(new APBToTL()) val apb2tlBuffer = LazyModule(new TLBuffer(BufferParams.pipe)) val dmTopAddr = (1 << cfg.nDMIAddrSize) << 2 val tlErrorParams = DevNullParams(AddressSet.misaligned(dmTopAddr, APBDebugConsts.apbDebugRegBase-dmTopAddr), maxAtomic=0, maxTransfer=4) val tlError = LazyModule(new TLError(tlErrorParams, buffer=false)) val apbXbar = LazyModule(new APBFanout()) val apbRegs = LazyModule(new APBDebugRegisters()) apbRegs.node := apbXbar.node apb2tl.node := apbXbar.node apb2tlBuffer.node := apb2tl.node dmiXbar.node := apb2tlBuffer.node tlError.node := dmiXbar.node apbXbar.node }) val dmOuter = LazyModule( new TLDebugModuleOuter(device)) val intnode = IntSyncIdentityNode() intnode :*= IntSyncCrossingSource(alreadyRegistered = true) :*= dmOuter.intnode val dmiBypass = LazyModule(new TLBusBypass(beatBytes=4, bufferError=false, maxAtomic=0, maxTransfer=4)) val dmiInnerNode = TLAsyncCrossingSource() := dmiBypass.node := dmiXbar.node dmOuter.dmiNode := dmiXbar.node lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { val nComponents = dmOuter.intnode.edges.out.size val io = IO(new Bundle { val dmi_clock = Input(Clock()) val dmi_reset = Input(Reset()) /** Debug Module Interface bewteen DM and DTM * * The DTM provides access to one or more Debug Modules (DMs) using DMI */ val dmi = (!p(ExportDebug).apb).option(Flipped(new DMIIO()(p))) // Optional APB Interface is fully diplomatic so is not listed here. val ctrl = new DebugCtrlBundle(nComponents) /** conrol signals for Inner, generated in Outer */ val innerCtrl = new AsyncBundle(new DebugInternalBundle(nComponents), AsyncQueueParams.singleton(safe=cfg.crossingHasSafeReset)) /** debug interruption generated in Inner */ val hgDebugInt = Input(Vec(nComponents, Bool())) /** hart reset request to core */ val hartResetReq = p(DebugModuleKey).get.hasHartResets.option(Output(Vec(nComponents, Bool()))) /** Authentication signal from core */ val dmAuthenticated = p(DebugModuleKey).get.hasAuthentication.option(Input(Bool())) }) val rf_reset = IO(Input(Reset())) // RF transform childClock := io.dmi_clock childReset := io.dmi_reset override def provideImplicitClockToLazyChildren = true withClockAndReset(childClock, childReset) { dmi2tlOpt.foreach { _.module.io.dmi <> io.dmi.get } val dmactiveAck = AsyncResetSynchronizerShiftReg(in=io.ctrl.dmactiveAck, sync=3, name=Some("dmactiveAckSync")) dmiBypass.module.io.bypass := ~io.ctrl.dmactive | ~dmactiveAck io.ctrl <> dmOuter.module.io.ctrl dmOuter.module.io.ctrl.dmactiveAck := dmactiveAck // send synced version down to dmOuter io.innerCtrl <> ToAsyncBundle(dmOuter.module.io.innerCtrl, AsyncQueueParams.singleton(safe=cfg.crossingHasSafeReset)) dmOuter.module.io.hgDebugInt := io.hgDebugInt io.hartResetReq.foreach { x => dmOuter.module.io.hartResetReq.foreach {y => x := y}} io.dmAuthenticated.foreach { x => dmOuter.module.io.dmAuthenticated.foreach { y => y := x}} } } } class TLDebugModuleInner(device: Device, getNComponents: () => Int, beatBytes: Int)(implicit p: Parameters) extends LazyModule { // For Shorter Register Names import DMI_RegAddrs._ val cfg = p(DebugModuleKey).get def getCfg = () => cfg val dmTopAddr = (1 << cfg.nDMIAddrSize) << 2 /** dmiNode address set */ val dmiNode = TLRegisterNode( // Address is range 0 to 0x1FF except DMCONTROL, HARTINFO, HAWINDOWSEL, HAWINDOW which are handled by Outer address = AddressSet.misaligned(0, DMI_DMCONTROL << 2) ++ AddressSet.misaligned((DMI_DMCONTROL + 1) << 2, ((DMI_HARTINFO << 2) - ((DMI_DMCONTROL + 1) << 2))) ++ AddressSet.misaligned((DMI_HARTINFO + 1) << 2, ((DMI_HAWINDOWSEL << 2) - ((DMI_HARTINFO + 1) << 2))) ++ AddressSet.misaligned((DMI_HAWINDOW + 1) << 2, (dmTopAddr - ((DMI_HAWINDOW + 1) << 2))), device = device, beatBytes = 4, executable = false ) val tlNode = TLRegisterNode( address=Seq(cfg.address), device=device, beatBytes=beatBytes, executable=true ) val sb2tlOpt = cfg.hasBusMaster.option(LazyModule(new SBToTL())) // If we want to support custom registers read through Abstract Commands, // provide a place to bring them into the debug module. What this connects // to is up to the implementation. val customNode = new DebugCustomSink() lazy val module = new Impl class Impl extends LazyModuleImp(this){ val nComponents = getNComponents() Annotated.params(this, cfg) val supportHartArray = cfg.supportHartArray & (nComponents > 1) val nExtTriggers = cfg.nExtTriggers val nHaltGroups = if ((nComponents > 1) | (nExtTriggers > 0)) cfg.nHaltGroups else 0 // no halt groups possible if single hart with no external triggers val hartSelFuncs = if (getNComponents() > 1) p(DebugModuleHartSelKey) else DebugModuleHartSelFuncs( hartIdToHartSel = (x) => 0.U, hartSelToHartId = (x) => x ) val io = IO(new Bundle { /** dm reset signal passed in from Outer */ val dmactive = Input(Bool()) /** conrol signals for Inner * * it's generated by Outer and comes in */ val innerCtrl = Flipped(new DecoupledIO(new DebugInternalBundle(nComponents))) /** debug unavail signal passed in from Outer*/ val debugUnavail = Input(Vec(nComponents, Bool())) /** debug interruption from Inner to Outer * * contain 2 type of debug interruption causes: * - halt group * - halt-on-reset */ val hgDebugInt = Output(Vec(nComponents, Bool())) /** interface for trigger */ val extTrigger = (nExtTriggers > 0).option(new DebugExtTriggerIO()) /** vector to indicate which hart is in reset * * dm receives it from core and sends it to Inner */ val hartIsInReset = Input(Vec(nComponents, Bool())) val tl_clock = Input(Clock()) val tl_reset = Input(Reset()) /** Debug Authentication signals from core */ val auth = cfg.hasAuthentication.option(new DebugAuthenticationIO()) }) sb2tlOpt.map { sb => sb.module.clock := io.tl_clock sb.module.reset := io.tl_reset sb.module.rf_reset := io.tl_reset } //-------------------------------------------------------------- // Import constants for shorter variable names //-------------------------------------------------------------- import DMI_RegAddrs._ import DsbRegAddrs._ import DsbBusConsts._ //-------------------------------------------------------------- // Sanity Check Configuration For this implementation. //-------------------------------------------------------------- require (cfg.supportQuickAccess == false, "No Quick Access support yet") require ((nHaltGroups > 0) || (nExtTriggers == 0), "External triggers require at least 1 halt group") //-------------------------------------------------------------- // Register & Wire Declarations (which need to be pre-declared) //-------------------------------------------------------------- // run control regs: tracking all the harts // implements: see implementation-specific bits part /** all harts halted status */ val haltedBitRegs = Reg(UInt(nComponents.W)) /** all harts resume request status */ val resumeReqRegs = Reg(UInt(nComponents.W)) /** all harts have reset status */ val haveResetBitRegs = Reg(UInt(nComponents.W)) // default is 1,after resume, resumeAcks get 0 /** all harts resume ack status */ val resumeAcks = Wire(UInt(nComponents.W)) // --- regmapper outputs // hart state Id and En // in Hart Bus Access ROM val hartHaltedWrEn = Wire(Bool()) val hartHaltedId = Wire(UInt(sbIdWidth.W)) val hartGoingWrEn = Wire(Bool()) val hartGoingId = Wire(UInt(sbIdWidth.W)) val hartResumingWrEn = Wire(Bool()) val hartResumingId = Wire(UInt(sbIdWidth.W)) val hartExceptionWrEn = Wire(Bool()) val hartExceptionId = Wire(UInt(sbIdWidth.W)) // progbuf and abstract data: byte-addressable control logic // AccessLegal is set only when state = waiting // RdEn and WrEnMaybe : contrl signal drived by DMI bus val dmiProgramBufferRdEn = WireInit(VecInit(Seq.fill(cfg.nProgramBufferWords * 4) {false.B} )) val dmiProgramBufferAccessLegal = WireInit(false.B) val dmiProgramBufferWrEnMaybe = WireInit(VecInit(Seq.fill(cfg.nProgramBufferWords * 4) {false.B} )) val dmiAbstractDataRdEn = WireInit(VecInit(Seq.fill(cfg.nAbstractDataWords * 4) {false.B} )) val dmiAbstractDataAccessLegal = WireInit(false.B) val dmiAbstractDataWrEnMaybe = WireInit(VecInit(Seq.fill(cfg.nAbstractDataWords * 4) {false.B} )) //-------------------------------------------------------------- // Registers coming from 'CONTROL' in Outer //-------------------------------------------------------------- val dmAuthenticated = io.auth.map(a => a.dmAuthenticated).getOrElse(true.B) val selectedHartReg = Reg(UInt(p(MaxHartIdBits).W)) // hamaskFull is a vector of all selected harts including hartsel, whether or not supportHartArray is true val hamaskFull = WireInit(VecInit(Seq.fill(nComponents) {false.B} )) if (nComponents > 1) { when (~io.dmactive) { selectedHartReg := 0.U }.elsewhen (io.innerCtrl.fire){ selectedHartReg := io.innerCtrl.bits.hartsel } } if (supportHartArray) { val hamaskZero = WireInit(VecInit(Seq.fill(nComponents) {false.B} )) val hamaskReg = Reg(Vec(nComponents, Bool())) when (~io.dmactive || ~dmAuthenticated) { hamaskReg := hamaskZero }.elsewhen (io.innerCtrl.fire){ hamaskReg := Mux(io.innerCtrl.bits.hasel, io.innerCtrl.bits.hamask, hamaskZero) } hamaskFull := hamaskReg } // Outer.hamask doesn't consider the hart selected by dmcontrol.hartsello, // so append it here when (selectedHartReg < nComponents.U) { hamaskFull(if (nComponents == 1) 0.U(0.W) else selectedHartReg) := true.B } io.innerCtrl.ready := true.B // Construct a Vec from io.innerCtrl fields indicating whether each hart is being selected in this write // A hart may be selected by hartsel field or by hart array val hamaskWrSel = WireInit(VecInit(Seq.fill(nComponents) {false.B} )) for (component <- 0 until nComponents ) { hamaskWrSel(component) := ((io.innerCtrl.bits.hartsel === component.U) || (if (supportHartArray) io.innerCtrl.bits.hasel && io.innerCtrl.bits.hamask(component) else false.B)) } //------------------------------------- // Halt-on-reset logic // hrmask is set in dmOuter and passed in // Debug interrupt is generated when a reset occurs whose corresponding hrmask bit is set // Debug interrupt is maintained until the hart enters halted state //------------------------------------- val hrReset = WireInit(VecInit(Seq.fill(nComponents) { false.B } )) val hrDebugInt = Wire(Vec(nComponents, Bool())) val hrmaskReg = RegInit(hrReset) val hartIsInResetSync = Wire(Vec(nComponents, Bool())) for (component <- 0 until nComponents) { hartIsInResetSync(component) := AsyncResetSynchronizerShiftReg(io.hartIsInReset(component), 3, Some(s"debug_hartReset_$component")) } when (~io.dmactive || ~dmAuthenticated) { hrmaskReg := hrReset }.elsewhen (io.innerCtrl.fire){ hrmaskReg := io.innerCtrl.bits.hrmask } withReset(reset.asAsyncReset) { // ensure interrupt requests are negated at first clock edge val hrDebugIntReg = RegInit(VecInit(Seq.fill(nComponents) { false.B } )) when (~io.dmactive || ~dmAuthenticated) { hrDebugIntReg := hrReset }.otherwise { hrDebugIntReg := hrmaskReg & (hartIsInResetSync | // set debugInt during reset (hrDebugIntReg & ~(haltedBitRegs.asBools))) // maintain until core halts } hrDebugInt := hrDebugIntReg } //-------------------------------------------------------------- // DMI Registers //-------------------------------------------------------------- //----DMSTATUS val DMSTATUSRdData = WireInit(0.U.asTypeOf(new DMSTATUSFields())) DMSTATUSRdData.authenticated := dmAuthenticated DMSTATUSRdData.version := 2.U // Version 0.13 io.auth.map(a => DMSTATUSRdData.authbusy := a.dmAuthBusy) val resumereq = io.innerCtrl.fire && io.innerCtrl.bits.resumereq when (dmAuthenticated) { DMSTATUSRdData.hasresethaltreq := true.B DMSTATUSRdData.anynonexistent := (selectedHartReg >= nComponents.U) // only hartsel can be nonexistent // all harts nonexistent if hartsel is out of range and there are no harts selected in the hart array DMSTATUSRdData.allnonexistent := (selectedHartReg >= nComponents.U) & (~hamaskFull.reduce(_ | _)) when (~DMSTATUSRdData.allnonexistent) { // if no existent harts selected, all other status is false DMSTATUSRdData.anyunavail := (io.debugUnavail & hamaskFull).reduce(_ | _) DMSTATUSRdData.anyhalted := ((~io.debugUnavail & (haltedBitRegs.asBools)) & hamaskFull).reduce(_ | _) DMSTATUSRdData.anyrunning := ((~io.debugUnavail & ~(haltedBitRegs.asBools)) & hamaskFull).reduce(_ | _) DMSTATUSRdData.anyhavereset := (haveResetBitRegs.asBools & hamaskFull).reduce(_ | _) DMSTATUSRdData.anyresumeack := (resumeAcks.asBools & hamaskFull).reduce(_ | _) when (~DMSTATUSRdData.anynonexistent) { // if one hart is nonexistent, no 'all' status is set DMSTATUSRdData.allunavail := (io.debugUnavail | ~hamaskFull).reduce(_ & _) DMSTATUSRdData.allhalted := ((~io.debugUnavail & (haltedBitRegs.asBools)) | ~hamaskFull).reduce(_ & _) DMSTATUSRdData.allrunning := ((~io.debugUnavail & ~(haltedBitRegs.asBools)) | ~hamaskFull).reduce(_ & _) DMSTATUSRdData.allhavereset := (haveResetBitRegs.asBools | ~hamaskFull).reduce(_ & _) DMSTATUSRdData.allresumeack := (resumeAcks.asBools | ~hamaskFull).reduce(_ & _) } } //TODO DMSTATUSRdData.confstrptrvalid := false.B DMSTATUSRdData.impebreak := (cfg.hasImplicitEbreak).B } when(~io.dmactive || ~dmAuthenticated) { haveResetBitRegs := 0.U }.otherwise { when (io.innerCtrl.fire && io.innerCtrl.bits.ackhavereset) { haveResetBitRegs := (haveResetBitRegs & (~(hamaskWrSel.asUInt))) | hartIsInResetSync.asUInt }.otherwise { haveResetBitRegs := haveResetBitRegs | hartIsInResetSync.asUInt } } //----DMCS2 (Halt Groups) val DMCS2RdData = WireInit(0.U.asTypeOf(new DMCS2Fields())) val DMCS2WrData = WireInit(0.U.asTypeOf(new DMCS2Fields())) val hgselectWrEn = WireInit(false.B) val hgwriteWrEn = WireInit(false.B) val haltgroupWrEn = WireInit(false.B) val exttriggerWrEn = WireInit(false.B) val hgDebugInt = WireInit(VecInit(Seq.fill(nComponents) {false.B} )) if (nHaltGroups > 0) withReset (reset.asAsyncReset) { // async reset ensures triggers don't falsely fire during startup val hgBits = log2Up(nHaltGroups) // hgParticipate: Each entry indicates which hg that entity belongs to (1 to nHartGroups). 0 means no hg assigned. val hgParticipateHart = RegInit(VecInit(Seq.fill(nComponents)(0.U(hgBits.W)))) val hgParticipateTrig = if (nExtTriggers > 0) RegInit(VecInit(Seq.fill(nExtTriggers)(0.U(hgBits.W)))) else Nil // assign group index to current seledcted harts for (component <- 0 until nComponents) { when (~io.dmactive || ~dmAuthenticated) { hgParticipateHart(component) := 0.U }.otherwise { when (haltgroupWrEn & DMCS2WrData.hgwrite & ~DMCS2WrData.hgselect & hamaskFull(component) & (DMCS2WrData.haltgroup <= nHaltGroups.U)) { hgParticipateHart(component) := DMCS2WrData.haltgroup } } } DMCS2RdData.haltgroup := hgParticipateHart(if (nComponents == 1) 0.U(0.W) else selectedHartReg) if (nExtTriggers > 0) { val hgSelect = Reg(Bool()) when (~io.dmactive || ~dmAuthenticated) { hgSelect := false.B }.otherwise { when (hgselectWrEn) { hgSelect := DMCS2WrData.hgselect } } // assign group index to trigger for (trigger <- 0 until nExtTriggers) { when (~io.dmactive || ~dmAuthenticated) { hgParticipateTrig(trigger) := 0.U }.otherwise { when (haltgroupWrEn & DMCS2WrData.hgwrite & DMCS2WrData.hgselect & (DMCS2WrData.exttrigger === trigger.U) & (DMCS2WrData.haltgroup <= nHaltGroups.U)) { hgParticipateTrig(trigger) := DMCS2WrData.haltgroup } } } DMCS2RdData.hgselect := hgSelect when (hgSelect) { DMCS2RdData.haltgroup := hgParticipateTrig(0) } // If there is only 1 ext trigger, then the exttrigger field is fixed at 0 // Otherwise, instantiate a register with only the number of bits required if (nExtTriggers > 1) { val trigBits = log2Up(nExtTriggers-1) val hgExtTrigger = Reg(UInt(trigBits.W)) when (~io.dmactive || ~dmAuthenticated) { hgExtTrigger := 0.U }.otherwise { when (exttriggerWrEn & (DMCS2WrData.exttrigger < nExtTriggers.U)) { hgExtTrigger := DMCS2WrData.exttrigger } } DMCS2RdData.exttrigger := hgExtTrigger when (hgSelect) { DMCS2RdData.haltgroup := hgParticipateTrig(hgExtTrigger) } } } // Halt group state machine // IDLE: Go to FIRED when any hart in this hg writes to HALTED while its HaltedBitRegs=0 // or when any trigin assigned to this hg occurs // FIRED: Back to IDLE when all harts in this hg have set their haltedBitRegs // and all trig out in this hg have been acknowledged val hgFired = RegInit (VecInit(Seq.fill(nHaltGroups+1) {false.B} )) val hgHartFiring = WireInit(VecInit(Seq.fill(nHaltGroups+1) {false.B} )) // which hg's are firing due to hart halting val hgTrigFiring = WireInit(VecInit(Seq.fill(nHaltGroups+1) {false.B} )) // which hg's are firing due to trig in val hgHartsAllHalted = WireInit(VecInit(Seq.fill(nHaltGroups+1) {false.B} )) // in which hg's have all harts halted val hgTrigsAllAcked = WireInit(VecInit(Seq.fill(nHaltGroups+1) { true.B} )) // in which hg's have all trigouts been acked io.extTrigger.foreach {extTrigger => val extTriggerInReq = Wire(Vec(nExtTriggers, Bool())) val extTriggerOutAck = Wire(Vec(nExtTriggers, Bool())) extTriggerInReq := extTrigger.in.req.asBools extTriggerOutAck := extTrigger.out.ack.asBools val trigInReq = ResetSynchronizerShiftReg(in=extTriggerInReq, sync=3, name=Some("dm_extTriggerInReqSync")) val trigOutAck = ResetSynchronizerShiftReg(in=extTriggerOutAck, sync=3, name=Some("dm_extTriggerOutAckSync")) for (hg <- 1 to nHaltGroups) { hgTrigFiring(hg) := (trigInReq & ~RegNext(trigInReq) & hgParticipateTrig.map(_ === hg.U)).reduce(_ | _) hgTrigsAllAcked(hg) := (trigOutAck | hgParticipateTrig.map(_ =/= hg.U)).reduce(_ & _) } extTrigger.in.ack := trigInReq.asUInt } for (hg <- 1 to nHaltGroups) { hgHartFiring(hg) := hartHaltedWrEn & ~haltedBitRegs(hartHaltedId) & (hgParticipateHart(hartSelFuncs.hartIdToHartSel(hartHaltedId)) === hg.U) hgHartsAllHalted(hg) := (haltedBitRegs.asBools | hgParticipateHart.map(_ =/= hg.U)).reduce(_ & _) when (~io.dmactive || ~dmAuthenticated) { hgFired(hg) := false.B }.elsewhen (~hgFired(hg) & (hgHartFiring(hg) | hgTrigFiring(hg))) { hgFired(hg) := true.B }.elsewhen ( hgFired(hg) & hgHartsAllHalted(hg) & hgTrigsAllAcked(hg)) { hgFired(hg) := false.B } } // For each hg that has fired, assert debug interrupt to each hart in that hg for (component <- 0 until nComponents) { hgDebugInt(component) := hgFired(hgParticipateHart(component)) } // For each hg that has fired, assert trigger out for all external triggers in that hg io.extTrigger.foreach {extTrigger => val extTriggerOutReq = RegInit(VecInit(Seq.fill(cfg.nExtTriggers) {false.B} )) for (trig <- 0 until nExtTriggers) { extTriggerOutReq(trig) := hgFired(hgParticipateTrig(trig)) } extTrigger.out.req := extTriggerOutReq.asUInt } } io.hgDebugInt := hgDebugInt | hrDebugInt //----HALTSUM* val numHaltedStatus = ((nComponents - 1) / 32) + 1 val haltedStatus = Wire(Vec(numHaltedStatus, Bits(32.W))) for (ii <- 0 until numHaltedStatus) { when (dmAuthenticated) { haltedStatus(ii) := haltedBitRegs >> (ii*32) }.otherwise { haltedStatus(ii) := 0.U } } val haltedSummary = Cat(haltedStatus.map(_.orR).reverse) val HALTSUM1RdData = haltedSummary.asTypeOf(new HALTSUM1Fields()) val selectedHaltedStatus = Mux((selectedHartReg >> 5) > numHaltedStatus.U, 0.U, haltedStatus(selectedHartReg >> 5)) val HALTSUM0RdData = selectedHaltedStatus.asTypeOf(new HALTSUM0Fields()) // Since we only support 1024 harts, we don't implement HALTSUM2 or HALTSUM3 //----ABSTRACTCS val ABSTRACTCSReset = WireInit(0.U.asTypeOf(new ABSTRACTCSFields())) ABSTRACTCSReset.datacount := cfg.nAbstractDataWords.U ABSTRACTCSReset.progbufsize := cfg.nProgramBufferWords.U val ABSTRACTCSReg = Reg(new ABSTRACTCSFields()) val ABSTRACTCSWrData = WireInit(0.U.asTypeOf(new ABSTRACTCSFields())) val ABSTRACTCSRdData = WireInit(ABSTRACTCSReg) val ABSTRACTCSRdEn = WireInit(false.B) val ABSTRACTCSWrEnMaybe = WireInit(false.B) val ABSTRACTCSWrEnLegal = WireInit(false.B) val ABSTRACTCSWrEn = ABSTRACTCSWrEnMaybe && ABSTRACTCSWrEnLegal // multiple error types // find implement in the state machine part val errorBusy = WireInit(false.B) val errorException = WireInit(false.B) val errorUnsupported = WireInit(false.B) val errorHaltResume = WireInit(false.B) when (~io.dmactive || ~dmAuthenticated) { ABSTRACTCSReg := ABSTRACTCSReset }.otherwise { when (errorBusy){ ABSTRACTCSReg.cmderr := DebugAbstractCommandError.ErrBusy.id.U }.elsewhen (errorException) { ABSTRACTCSReg.cmderr := DebugAbstractCommandError.ErrException.id.U }.elsewhen (errorUnsupported) { ABSTRACTCSReg.cmderr := DebugAbstractCommandError.ErrNotSupported.id.U }.elsewhen (errorHaltResume) { ABSTRACTCSReg.cmderr := DebugAbstractCommandError.ErrHaltResume.id.U }.otherwise { //W1C when (ABSTRACTCSWrEn){ ABSTRACTCSReg.cmderr := ABSTRACTCSReg.cmderr & ~(ABSTRACTCSWrData.cmderr); } } } // For busy, see below state machine. val abstractCommandBusy = WireInit(true.B) ABSTRACTCSRdData.busy := abstractCommandBusy when (~dmAuthenticated) { // read value must be 0 when not authenticated ABSTRACTCSRdData.datacount := 0.U ABSTRACTCSRdData.progbufsize := 0.U } //---- ABSTRACTAUTO // It is a mask indicating whether datai/probufi have the autoexcution permisson // this part aims to produce 3 wires : autoexecData,autoexecProg,autoexec // first two specify which reg supports autoexec // autoexec is a control signal, meaning there is at least one enabled autoexec reg // when autoexec is set, generate instructions using COMMAND register val ABSTRACTAUTOReset = WireInit(0.U.asTypeOf(new ABSTRACTAUTOFields())) val ABSTRACTAUTOReg = Reg(new ABSTRACTAUTOFields()) val ABSTRACTAUTOWrData = WireInit(0.U.asTypeOf(new ABSTRACTAUTOFields())) val ABSTRACTAUTORdData = WireInit(ABSTRACTAUTOReg) val ABSTRACTAUTORdEn = WireInit(false.B) val autoexecdataWrEnMaybe = WireInit(false.B) val autoexecprogbufWrEnMaybe = WireInit(false.B) val ABSTRACTAUTOWrEnLegal = WireInit(false.B) when (~io.dmactive || ~dmAuthenticated) { ABSTRACTAUTOReg := ABSTRACTAUTOReset }.otherwise { when (autoexecprogbufWrEnMaybe && ABSTRACTAUTOWrEnLegal) { ABSTRACTAUTOReg.autoexecprogbuf := ABSTRACTAUTOWrData.autoexecprogbuf & ( (1 << cfg.nProgramBufferWords) - 1).U } when (autoexecdataWrEnMaybe && ABSTRACTAUTOWrEnLegal) { ABSTRACTAUTOReg.autoexecdata := ABSTRACTAUTOWrData.autoexecdata & ( (1 << cfg.nAbstractDataWords) - 1).U } } // Abstract Data access vector(byte-addressable) val dmiAbstractDataAccessVec = WireInit(VecInit(Seq.fill(cfg.nAbstractDataWords * 4) {false.B} )) dmiAbstractDataAccessVec := (dmiAbstractDataWrEnMaybe zip dmiAbstractDataRdEn).map{ case (r,w) => r | w} // Program Buffer access vector(byte-addressable) val dmiProgramBufferAccessVec = WireInit(VecInit(Seq.fill(cfg.nProgramBufferWords * 4) {false.B} )) dmiProgramBufferAccessVec := (dmiProgramBufferWrEnMaybe zip dmiProgramBufferRdEn).map{ case (r,w) => r | w} // at least one word access val dmiAbstractDataAccess = dmiAbstractDataAccessVec.reduce(_ || _ ) val dmiProgramBufferAccess = dmiProgramBufferAccessVec.reduce(_ || _) // This will take the shorter of the lists, which is what we want. val autoexecData = WireInit(VecInit(Seq.fill(cfg.nAbstractDataWords) {false.B} )) val autoexecProg = WireInit(VecInit(Seq.fill(cfg.nProgramBufferWords) {false.B} )) (autoexecData zip ABSTRACTAUTOReg.autoexecdata.asBools).zipWithIndex.foreach {case (t, i) => t._1 := dmiAbstractDataAccessVec(i * 4) && t._2 } (autoexecProg zip ABSTRACTAUTOReg.autoexecprogbuf.asBools).zipWithIndex.foreach {case (t, i) => t._1 := dmiProgramBufferAccessVec(i * 4) && t._2} val autoexec = autoexecData.reduce(_ || _) || autoexecProg.reduce(_ || _) //---- COMMAND val COMMANDReset = WireInit(0.U.asTypeOf(new COMMANDFields())) val COMMANDReg = Reg(new COMMANDFields()) val COMMANDWrDataVal = WireInit(0.U(32.W)) val COMMANDWrData = WireInit(COMMANDWrDataVal.asTypeOf(new COMMANDFields())) val COMMANDWrEnMaybe = WireInit(false.B) val COMMANDWrEnLegal = WireInit(false.B) val COMMANDRdEn = WireInit(false.B) val COMMANDWrEn = COMMANDWrEnMaybe && COMMANDWrEnLegal val COMMANDRdData = COMMANDReg when (~io.dmactive || ~dmAuthenticated) { COMMANDReg := COMMANDReset }.otherwise { when (COMMANDWrEn) { COMMANDReg := COMMANDWrData } } // --- Abstract Data // These are byte addressible, s.t. the Processor can use // byte-addressible instructions to store to them. val abstractDataMem = Reg(Vec(cfg.nAbstractDataWords*4, UInt(8.W))) val abstractDataNxt = WireInit(abstractDataMem) // --- Program Buffer // byte-addressible mem val programBufferMem = Reg(Vec(cfg.nProgramBufferWords*4, UInt(8.W))) val programBufferNxt = WireInit(programBufferMem) //-------------------------------------------------------------- // These bits are implementation-specific bits set // by harts executing code. //-------------------------------------------------------------- // Run control logic when (~io.dmactive || ~dmAuthenticated) { haltedBitRegs := 0.U resumeReqRegs := 0.U }.otherwise { //remove those harts in reset resumeReqRegs := resumeReqRegs & ~(hartIsInResetSync.asUInt) val hartHaltedIdIndex = UIntToOH(hartSelFuncs.hartIdToHartSel(hartHaltedId)) val hartResumingIdIndex = UIntToOH(hartSelFuncs.hartIdToHartSel(hartResumingId)) val hartselIndex = UIntToOH(io.innerCtrl.bits.hartsel) when (hartHaltedWrEn) { // add those harts halting and remove those in reset haltedBitRegs := (haltedBitRegs | hartHaltedIdIndex) & ~(hartIsInResetSync.asUInt) }.elsewhen (hartResumingWrEn) { // remove those harts in reset and those in resume haltedBitRegs := (haltedBitRegs & ~(hartResumingIdIndex)) & ~(hartIsInResetSync.asUInt) }.otherwise { // remove those harts in reset haltedBitRegs := haltedBitRegs & ~(hartIsInResetSync.asUInt) } when (hartResumingWrEn) { // remove those harts in resume and those in reset resumeReqRegs := (resumeReqRegs & ~(hartResumingIdIndex)) & ~(hartIsInResetSync.asUInt) } when (resumereq) { // set all sleceted harts to resumeReq, remove those in reset resumeReqRegs := (resumeReqRegs | hamaskWrSel.asUInt) & ~(hartIsInResetSync.asUInt) } } when (resumereq) { // next cycle resumeAcls will be the negation of next cycle resumeReqRegs resumeAcks := (~resumeReqRegs & ~(hamaskWrSel.asUInt)) }.otherwise { resumeAcks := ~resumeReqRegs } //---- AUTHDATA val authRdEnMaybe = WireInit(false.B) val authWrEnMaybe = WireInit(false.B) io.auth.map { a => a.dmactive := io.dmactive a.dmAuthRead := authRdEnMaybe & ~a.dmAuthBusy a.dmAuthWrite := authWrEnMaybe & ~a.dmAuthBusy } val dmstatusRegFields = RegFieldGroup("dmi_dmstatus", Some("debug module status register"), Seq( RegField.r(4, DMSTATUSRdData.version, RegFieldDesc("version", "version", reset=Some(2))), RegField.r(1, DMSTATUSRdData.confstrptrvalid, RegFieldDesc("confstrptrvalid", "confstrptrvalid", reset=Some(0))), RegField.r(1, DMSTATUSRdData.hasresethaltreq, RegFieldDesc("hasresethaltreq", "hasresethaltreq", reset=Some(1))), RegField.r(1, DMSTATUSRdData.authbusy, RegFieldDesc("authbusy", "authbusy", reset=Some(0))), RegField.r(1, DMSTATUSRdData.authenticated, RegFieldDesc("authenticated", "authenticated", reset=Some(1))), RegField.r(1, DMSTATUSRdData.anyhalted, RegFieldDesc("anyhalted", "anyhalted", reset=Some(0))), RegField.r(1, DMSTATUSRdData.allhalted, RegFieldDesc("allhalted", "allhalted", reset=Some(0))), RegField.r(1, DMSTATUSRdData.anyrunning, RegFieldDesc("anyrunning", "anyrunning", reset=Some(1))), RegField.r(1, DMSTATUSRdData.allrunning, RegFieldDesc("allrunning", "allrunning", reset=Some(1))), RegField.r(1, DMSTATUSRdData.anyunavail, RegFieldDesc("anyunavail", "anyunavail", reset=Some(0))), RegField.r(1, DMSTATUSRdData.allunavail, RegFieldDesc("allunavail", "allunavail", reset=Some(0))), RegField.r(1, DMSTATUSRdData.anynonexistent, RegFieldDesc("anynonexistent", "anynonexistent", reset=Some(0))), RegField.r(1, DMSTATUSRdData.allnonexistent, RegFieldDesc("allnonexistent", "allnonexistent", reset=Some(0))), RegField.r(1, DMSTATUSRdData.anyresumeack, RegFieldDesc("anyresumeack", "anyresumeack", reset=Some(1))), RegField.r(1, DMSTATUSRdData.allresumeack, RegFieldDesc("allresumeack", "allresumeack", reset=Some(1))), RegField.r(1, DMSTATUSRdData.anyhavereset, RegFieldDesc("anyhavereset", "anyhavereset", reset=Some(0))), RegField.r(1, DMSTATUSRdData.allhavereset, RegFieldDesc("allhavereset", "allhavereset", reset=Some(0))), RegField(2), RegField.r(1, DMSTATUSRdData.impebreak, RegFieldDesc("impebreak", "impebreak", reset=Some(if (cfg.hasImplicitEbreak) 1 else 0))) )) val dmcs2RegFields = RegFieldGroup("dmi_dmcs2", Some("debug module control/status register 2"), Seq( WNotifyVal(1, DMCS2RdData.hgselect, DMCS2WrData.hgselect, hgselectWrEn, RegFieldDesc("hgselect", "select halt groups or external triggers", reset=Some(0), volatile=true)), WNotifyVal(1, 0.U, DMCS2WrData.hgwrite, hgwriteWrEn, RegFieldDesc("hgwrite", "write 1 to change halt groups", reset=None, access=RegFieldAccessType.W)), WNotifyVal(5, DMCS2RdData.haltgroup, DMCS2WrData.haltgroup, haltgroupWrEn, RegFieldDesc("haltgroup", "halt group", reset=Some(0), volatile=true)), if (nExtTriggers > 1) WNotifyVal(4, DMCS2RdData.exttrigger, DMCS2WrData.exttrigger, exttriggerWrEn, RegFieldDesc("exttrigger", "external trigger select", reset=Some(0), volatile=true)) else RegField(4) )) val abstractcsRegFields = RegFieldGroup("dmi_abstractcs", Some("abstract command control/status"), Seq( RegField.r(4, ABSTRACTCSRdData.datacount, RegFieldDesc("datacount", "number of DATA registers", reset=Some(cfg.nAbstractDataWords))), RegField(4), WNotifyVal(3, ABSTRACTCSRdData.cmderr, ABSTRACTCSWrData.cmderr, ABSTRACTCSWrEnMaybe, RegFieldDesc("cmderr", "command error", reset=Some(0), wrType=Some(RegFieldWrType.ONE_TO_CLEAR))), RegField(1), RegField.r(1, ABSTRACTCSRdData.busy, RegFieldDesc("busy", "busy", reset=Some(0))), RegField(11), RegField.r(5, ABSTRACTCSRdData.progbufsize, RegFieldDesc("progbufsize", "number of PROGBUF registers", reset=Some(cfg.nProgramBufferWords))) )) val (sbcsFields, sbAddrFields, sbDataFields): (Seq[RegField], Seq[Seq[RegField]], Seq[Seq[RegField]]) = sb2tlOpt.map{ sb2tl => SystemBusAccessModule(sb2tl, io.dmactive, dmAuthenticated)(p) }.getOrElse((Seq.empty[RegField], Seq.fill[Seq[RegField]](4)(Seq.empty[RegField]), Seq.fill[Seq[RegField]](4)(Seq.empty[RegField]))) //-------------------------------------------------------------- // Program Buffer Access (DMI ... System Bus can override) //-------------------------------------------------------------- val omRegMap = dmiNode.regmap( (DMI_DMSTATUS << 2) -> dmstatusRegFields, //TODO (DMI_CFGSTRADDR0 << 2) -> cfgStrAddrFields, (DMI_DMCS2 << 2) -> (if (nHaltGroups > 0) dmcs2RegFields else Nil), (DMI_HALTSUM0 << 2) -> RegFieldGroup("dmi_haltsum0", Some("Halt Summary 0"), Seq(RegField.r(32, HALTSUM0RdData.asUInt, RegFieldDesc("dmi_haltsum0", "halt summary 0")))), (DMI_HALTSUM1 << 2) -> RegFieldGroup("dmi_haltsum1", Some("Halt Summary 1"), Seq(RegField.r(32, HALTSUM1RdData.asUInt, RegFieldDesc("dmi_haltsum1", "halt summary 1")))), (DMI_ABSTRACTCS << 2) -> abstractcsRegFields, (DMI_ABSTRACTAUTO<< 2) -> RegFieldGroup("dmi_abstractauto", Some("abstract command autoexec"), Seq( WNotifyVal(cfg.nAbstractDataWords, ABSTRACTAUTORdData.autoexecdata, ABSTRACTAUTOWrData.autoexecdata, autoexecdataWrEnMaybe, RegFieldDesc("autoexecdata", "abstract command data autoexec", reset=Some(0))), RegField(16-cfg.nAbstractDataWords), WNotifyVal(cfg.nProgramBufferWords, ABSTRACTAUTORdData.autoexecprogbuf, ABSTRACTAUTOWrData.autoexecprogbuf, autoexecprogbufWrEnMaybe, RegFieldDesc("autoexecprogbuf", "abstract command progbuf autoexec", reset=Some(0))))), (DMI_COMMAND << 2) -> RegFieldGroup("dmi_command", Some("Abstract Command Register"), Seq(RWNotify(32, COMMANDRdData.asUInt, COMMANDWrDataVal, COMMANDRdEn, COMMANDWrEnMaybe, Some(RegFieldDesc("dmi_command", "abstract command register", reset=Some(0), volatile=true))))), (DMI_DATA0 << 2) -> RegFieldGroup("dmi_data", Some("abstract command data registers"), abstractDataMem.zipWithIndex.map{case (x, i) => RWNotify(8, Mux(dmAuthenticated, x, 0.U), abstractDataNxt(i), dmiAbstractDataRdEn(i), dmiAbstractDataWrEnMaybe(i), Some(RegFieldDesc(s"dmi_data_$i", s"abstract command data register $i", reset = Some(0), volatile=true)))}, false), (DMI_PROGBUF0 << 2) -> RegFieldGroup("dmi_progbuf", Some("abstract command progbuf registers"), programBufferMem.zipWithIndex.map{case (x, i) => RWNotify(8, Mux(dmAuthenticated, x, 0.U), programBufferNxt(i), dmiProgramBufferRdEn(i), dmiProgramBufferWrEnMaybe(i), Some(RegFieldDesc(s"dmi_progbuf_$i", s"abstract command progbuf register $i", reset = Some(0))))}, false), (DMI_AUTHDATA << 2) -> (if (cfg.hasAuthentication) RegFieldGroup("dmi_authdata", Some("authentication data exchange register"), Seq(RWNotify(32, io.auth.get.dmAuthRdata, io.auth.get.dmAuthWdata, authRdEnMaybe, authWrEnMaybe, Some(RegFieldDesc("authdata", "authentication data exchange", volatile=true))))) else Nil), (DMI_SBCS << 2) -> sbcsFields, (DMI_SBDATA0 << 2) -> sbDataFields(0), (DMI_SBDATA1 << 2) -> sbDataFields(1), (DMI_SBDATA2 << 2) -> sbDataFields(2), (DMI_SBDATA3 << 2) -> sbDataFields(3), (DMI_SBADDRESS0 << 2) -> sbAddrFields(0), (DMI_SBADDRESS1 << 2) -> sbAddrFields(1), (DMI_SBADDRESS2 << 2) -> sbAddrFields(2), (DMI_SBADDRESS3 << 2) -> sbAddrFields(3) ) // Abstract data mem is written by both the tile link interface and DMI... abstractDataMem.zipWithIndex.foreach { case (x, i) => when (dmAuthenticated && dmiAbstractDataWrEnMaybe(i) && dmiAbstractDataAccessLegal) { x := abstractDataNxt(i) } } // ... and also by custom register read (if implemented) val (customs, customParams) = customNode.in.unzip val needCustom = (customs.size > 0) && (customParams.head.addrs.size > 0) def getNeedCustom = () => needCustom if (needCustom) { val (custom, customP) = customNode.in.head require(customP.width % 8 == 0, s"Debug Custom width must be divisible by 8, not ${customP.width}") val custom_data = custom.data.asBools val custom_bytes = Seq.tabulate(customP.width/8){i => custom_data.slice(i*8, (i+1)*8).asUInt} when (custom.ready && custom.valid) { (abstractDataMem zip custom_bytes).zipWithIndex.foreach {case ((a, b), i) => a := b } } } programBufferMem.zipWithIndex.foreach { case (x, i) => when (dmAuthenticated && dmiProgramBufferWrEnMaybe(i) && dmiProgramBufferAccessLegal) { x := programBufferNxt(i) } } //-------------------------------------------------------------- // "Variable" ROM Generation //-------------------------------------------------------------- val goReg = Reg(Bool()) val goAbstract = WireInit(false.B) val goCustom = WireInit(false.B) val jalAbstract = WireInit(Instructions.JAL.value.U.asTypeOf(new GeneratedUJ())) jalAbstract.setImm(ABSTRACT(cfg) - WHERETO) when (~io.dmactive){ goReg := false.B }.otherwise { when (goAbstract) { goReg := true.B }.elsewhen (hartGoingWrEn){ assert(hartGoingId === 0.U, "Unexpected 'GOING' hart.")//Chisel3 #540 %x, expected %x", hartGoingId, 0.U) goReg := false.B } } class flagBundle extends Bundle { val reserved = UInt(6.W) val resume = Bool() val go = Bool() } val flags = WireInit(VecInit(Seq.fill(1 << selectedHartReg.getWidth) {0.U.asTypeOf(new flagBundle())} )) assert ((hartSelFuncs.hartSelToHartId(selectedHartReg) < flags.size.U), s"HartSel to HartId Mapping is illegal for this Debug Implementation, because HartID must be < ${flags.size} for it to work.") flags(hartSelFuncs.hartSelToHartId(selectedHartReg)).go := goReg for (component <- 0 until nComponents) { val componentSel = WireInit(component.U) flags(hartSelFuncs.hartSelToHartId(componentSel)).resume := resumeReqRegs(component) } //---------------------------- // Abstract Command Decoding & Generation //---------------------------- val accessRegisterCommandWr = WireInit(COMMANDWrData.asUInt.asTypeOf(new ACCESS_REGISTERFields())) /** real COMMAND*/ val accessRegisterCommandReg = WireInit(COMMANDReg.asUInt.asTypeOf(new ACCESS_REGISTERFields())) // TODO: Quick Access class GeneratedI extends Bundle { val imm = UInt(12.W) val rs1 = UInt(5.W) val funct3 = UInt(3.W) val rd = UInt(5.W) val opcode = UInt(7.W) } class GeneratedS extends Bundle { val immhi = UInt(7.W) val rs2 = UInt(5.W) val rs1 = UInt(5.W) val funct3 = UInt(3.W) val immlo = UInt(5.W) val opcode = UInt(7.W) } class GeneratedCSR extends Bundle { val imm = UInt(12.W) val rs1 = UInt(5.W) val funct3 = UInt(3.W) val rd = UInt(5.W) val opcode = UInt(7.W) } class GeneratedUJ extends Bundle { val imm3 = UInt(1.W) val imm0 = UInt(10.W) val imm1 = UInt(1.W) val imm2 = UInt(8.W) val rd = UInt(5.W) val opcode = UInt(7.W) def setImm(imm: Int) : Unit = { // TODO: Check bounds of imm. require(imm % 2 == 0, "Immediate must be even for UJ encoding.") val immWire = WireInit(imm.S(21.W)) val immBits = WireInit(VecInit(immWire.asBools)) imm0 := immBits.slice(1, 1 + 10).asUInt imm1 := immBits.slice(11, 11 + 11).asUInt imm2 := immBits.slice(12, 12 + 8).asUInt imm3 := immBits.slice(20, 20 + 1).asUInt } } require((cfg.atzero && cfg.nAbstractInstructions == 2) || (!cfg.atzero && cfg.nAbstractInstructions == 5), "Mismatch between DebugModuleParams atzero and nAbstractInstructions") val abstractGeneratedMem = Reg(Vec(cfg.nAbstractInstructions, (UInt(32.W)))) def abstractGeneratedI(cfg: DebugModuleParams): UInt = { val inst = Wire(new GeneratedI()) val offset = if (cfg.atzero) DATA else (DATA-0x800) & 0xFFF val base = if (cfg.atzero) 0.U else Mux(accessRegisterCommandReg.regno(0), 8.U, 9.U) inst.opcode := (Instructions.LW.value.U.asTypeOf(new GeneratedI())).opcode inst.rd := (accessRegisterCommandReg.regno & 0x1F.U) inst.funct3 := accessRegisterCommandReg.size inst.rs1 := base inst.imm := offset.U inst.asUInt } def abstractGeneratedS(cfg: DebugModuleParams): UInt = { val inst = Wire(new GeneratedS()) val offset = if (cfg.atzero) DATA else (DATA-0x800) & 0xFFF val base = if (cfg.atzero) 0.U else Mux(accessRegisterCommandReg.regno(0), 8.U, 9.U) inst.opcode := (Instructions.SW.value.U.asTypeOf(new GeneratedS())).opcode inst.immlo := (offset & 0x1F).U inst.funct3 := accessRegisterCommandReg.size inst.rs1 := base inst.rs2 := (accessRegisterCommandReg.regno & 0x1F.U) inst.immhi := (offset >> 5).U inst.asUInt } def abstractGeneratedCSR: UInt = { val inst = Wire(new GeneratedCSR()) val base = Mux(accessRegisterCommandReg.regno(0), 8.U, 9.U) // use s0 as base for odd regs, s1 as base for even regs inst := (Instructions.CSRRW.value.U.asTypeOf(new GeneratedCSR())) inst.imm := CSRs.dscratch1.U inst.rs1 := base inst.rd := base inst.asUInt } val nop = Wire(new GeneratedI()) nop := Instructions.ADDI.value.U.asTypeOf(new GeneratedI()) nop.rd := 0.U nop.rs1 := 0.U nop.imm := 0.U val isa = Wire(new GeneratedI()) isa := Instructions.ADDIW.value.U.asTypeOf(new GeneratedI()) isa.rd := 0.U isa.rs1 := 0.U isa.imm := 0.U when (goAbstract) { if (cfg.nAbstractInstructions == 2) { // ABSTRACT(0): Transfer: LW or SW, else NOP // ABSTRACT(1): Postexec: NOP else EBREAK abstractGeneratedMem(0) := Mux(accessRegisterCommandReg.transfer, Mux(accessRegisterCommandReg.write, abstractGeneratedI(cfg), abstractGeneratedS(cfg)), nop.asUInt ) abstractGeneratedMem(1) := Mux(accessRegisterCommandReg.postexec, nop.asUInt, Instructions.EBREAK.value.U) } else { // Entry: All regs in GPRs, dscratch1=offset 0x800 in DM // ABSTRACT(0): CheckISA: ADDW or NOP (exception here if size=3 and not RV64) // ABSTRACT(1): CSRRW s1,dscratch1,s1 or CSRRW s0,dscratch1,s0 // ABSTRACT(2): Transfer: LW, SW, LD, SD else NOP // ABSTRACT(3): CSRRW s1,dscratch1,s1 or CSRRW s0,dscratch1,s0 // ABSTRACT(4): Postexec: NOP else EBREAK abstractGeneratedMem(0) := Mux(accessRegisterCommandReg.transfer && accessRegisterCommandReg.size =/= 2.U, isa.asUInt, nop.asUInt) abstractGeneratedMem(1) := abstractGeneratedCSR abstractGeneratedMem(2) := Mux(accessRegisterCommandReg.transfer, Mux(accessRegisterCommandReg.write, abstractGeneratedI(cfg), abstractGeneratedS(cfg)), nop.asUInt ) abstractGeneratedMem(3) := abstractGeneratedCSR abstractGeneratedMem(4) := Mux(accessRegisterCommandReg.postexec, nop.asUInt, Instructions.EBREAK.value.U) } } //-------------------------------------------------------------- // Drive Custom Access //-------------------------------------------------------------- if (needCustom) { val (custom, customP) = customNode.in.head custom.addr := accessRegisterCommandReg.regno custom.valid := goCustom } //-------------------------------------------------------------- // Hart Bus Access //-------------------------------------------------------------- tlNode.regmap( // This memory is writable. HALTED -> Seq(WNotifyWire(sbIdWidth, hartHaltedId, hartHaltedWrEn, "debug_hart_halted", "Debug ROM Causes hart to write its hartID here when it is in Debug Mode.")), GOING -> Seq(WNotifyWire(sbIdWidth, hartGoingId, hartGoingWrEn, "debug_hart_going", "Debug ROM causes hart to write 0 here when it begins executing Debug Mode instructions.")), RESUMING -> Seq(WNotifyWire(sbIdWidth, hartResumingId, hartResumingWrEn, "debug_hart_resuming", "Debug ROM causes hart to write its hartID here when it leaves Debug Mode.")), EXCEPTION -> Seq(WNotifyWire(sbIdWidth, hartExceptionId, hartExceptionWrEn, "debug_hart_exception", "Debug ROM causes hart to write 0 here if it gets an exception in Debug Mode.")), DATA -> RegFieldGroup("debug_data", Some("Data used to communicate with Debug Module"), abstractDataMem.zipWithIndex.map {case (x, i) => RegField(8, x, RegFieldDesc(s"debug_data_$i", ""))}), PROGBUF(cfg)-> RegFieldGroup("debug_progbuf", Some("Program buffer used to communicate with Debug Module"), programBufferMem.zipWithIndex.map {case (x, i) => RegField(8, x, RegFieldDesc(s"debug_progbuf_$i", ""))}), // These sections are read-only. IMPEBREAK(cfg)-> {if (cfg.hasImplicitEbreak) Seq(RegField.r(32, Instructions.EBREAK.value.U, RegFieldDesc("debug_impebreak", "Debug Implicit EBREAK", reset=Some(Instructions.EBREAK.value)))) else Nil}, WHERETO -> Seq(RegField.r(32, jalAbstract.asUInt, RegFieldDesc("debug_whereto", "Instruction filled in by Debug Module to control hart in Debug Mode", volatile = true))), ABSTRACT(cfg) -> RegFieldGroup("debug_abstract", Some("Instructions generated by Debug Module"), abstractGeneratedMem.zipWithIndex.map{ case (x,i) => RegField.r(32, x, RegFieldDesc(s"debug_abstract_$i", "", volatile=true))}), FLAGS -> RegFieldGroup("debug_flags", Some("Memory region used to control hart going/resuming in Debug Mode"), if (nComponents == 1) { Seq.tabulate(1024) { i => RegField.r(8, flags(0).asUInt, RegFieldDesc(s"debug_flags_$i", "", volatile=true)) } } else { flags.zipWithIndex.map{case(x, i) => RegField.r(8, x.asUInt, RegFieldDesc(s"debug_flags_$i", "", volatile=true))} }), ROMBASE -> RegFieldGroup("debug_rom", Some("Debug ROM"), (if (cfg.atzero) DebugRomContents() else DebugRomNonzeroContents()).zipWithIndex.map{case (x, i) => RegField.r(8, (x & 0xFF).U(8.W), RegFieldDesc(s"debug_rom_$i", "", reset=Some(x)))}) ) // Override System Bus accesses with dmactive reset. when (~io.dmactive){ abstractDataMem.foreach {x => x := 0.U} programBufferMem.foreach {x => x := 0.U} } //-------------------------------------------------------------- // Abstract Command State Machine //-------------------------------------------------------------- object CtrlState extends scala.Enumeration { type CtrlState = Value val Waiting, CheckGenerate, Exec, Custom = Value def apply( t : Value) : UInt = { t.id.U(log2Up(values.size).W) } } import CtrlState._ // This is not an initialization! val ctrlStateReg = Reg(chiselTypeOf(CtrlState(Waiting))) val hartHalted = haltedBitRegs(if (nComponents == 1) 0.U(0.W) else selectedHartReg) val ctrlStateNxt = WireInit(ctrlStateReg) //------------------------ // DMI Register Control and Status abstractCommandBusy := (ctrlStateReg =/= CtrlState(Waiting)) ABSTRACTCSWrEnLegal := (ctrlStateReg === CtrlState(Waiting)) COMMANDWrEnLegal := (ctrlStateReg === CtrlState(Waiting)) ABSTRACTAUTOWrEnLegal := (ctrlStateReg === CtrlState(Waiting)) dmiAbstractDataAccessLegal := (ctrlStateReg === CtrlState(Waiting)) dmiProgramBufferAccessLegal := (ctrlStateReg === CtrlState(Waiting)) errorBusy := (ABSTRACTCSWrEnMaybe && ~ABSTRACTCSWrEnLegal) || (autoexecdataWrEnMaybe && ~ABSTRACTAUTOWrEnLegal) || (autoexecprogbufWrEnMaybe && ~ABSTRACTAUTOWrEnLegal) || (COMMANDWrEnMaybe && ~COMMANDWrEnLegal) || (dmiAbstractDataAccess && ~dmiAbstractDataAccessLegal) || (dmiProgramBufferAccess && ~dmiProgramBufferAccessLegal) // TODO: Maybe Quick Access val commandWrIsAccessRegister = (COMMANDWrData.cmdtype === DebugAbstractCommandType.AccessRegister.id.U) val commandRegIsAccessRegister = (COMMANDReg.cmdtype === DebugAbstractCommandType.AccessRegister.id.U) val commandWrIsUnsupported = COMMANDWrEn && !commandWrIsAccessRegister val commandRegIsUnsupported = WireInit(true.B) val commandRegBadHaltResume = WireInit(false.B) // We only support abstract commands for GPRs and any custom registers, if specified. val accessRegIsLegalSize = (accessRegisterCommandReg.size === 2.U) || (accessRegisterCommandReg.size === 3.U) val accessRegIsGPR = (accessRegisterCommandReg.regno >= 0x1000.U && accessRegisterCommandReg.regno <= 0x101F.U) && accessRegIsLegalSize val accessRegIsCustom = if (needCustom) { val (custom, customP) = customNode.in.head customP.addrs.foldLeft(false.B){ (result, current) => result || (current.U === accessRegisterCommandReg.regno)} } else false.B when (commandRegIsAccessRegister) { when (accessRegIsCustom && accessRegisterCommandReg.transfer && accessRegisterCommandReg.write === false.B) { commandRegIsUnsupported := false.B }.elsewhen (!accessRegisterCommandReg.transfer || accessRegIsGPR) { commandRegIsUnsupported := false.B commandRegBadHaltResume := ~hartHalted } } val wrAccessRegisterCommand = COMMANDWrEn && commandWrIsAccessRegister && (ABSTRACTCSReg.cmderr === 0.U) val regAccessRegisterCommand = autoexec && commandRegIsAccessRegister && (ABSTRACTCSReg.cmderr === 0.U) //------------------------ // Variable ROM STATE MACHINE // ----------------------- when (ctrlStateReg === CtrlState(Waiting)){ when (wrAccessRegisterCommand || regAccessRegisterCommand) { ctrlStateNxt := CtrlState(CheckGenerate) }.elsewhen (commandWrIsUnsupported) { // These checks are really on the command type. errorUnsupported := true.B }.elsewhen (autoexec && commandRegIsUnsupported) { errorUnsupported := true.B } }.elsewhen (ctrlStateReg === CtrlState(CheckGenerate)){ // We use this state to ensure that the COMMAND has been // registered by the time that we need to use it, to avoid // generating it directly from the COMMANDWrData. // This 'commandRegIsUnsupported' is really just checking the // AccessRegisterCommand parameters (regno) when (commandRegIsUnsupported) { errorUnsupported := true.B ctrlStateNxt := CtrlState(Waiting) }.elsewhen (commandRegBadHaltResume){ errorHaltResume := true.B ctrlStateNxt := CtrlState(Waiting) }.otherwise { when(accessRegIsCustom) { ctrlStateNxt := CtrlState(Custom) }.otherwise { ctrlStateNxt := CtrlState(Exec) goAbstract := true.B } } }.elsewhen (ctrlStateReg === CtrlState(Exec)) { // We can't just look at 'hartHalted' here, because // hartHaltedWrEn is overloaded to mean 'got an ebreak' // which may have happened when we were already halted. when(goReg === false.B && hartHaltedWrEn && (hartSelFuncs.hartIdToHartSel(hartHaltedId) === selectedHartReg)){ ctrlStateNxt := CtrlState(Waiting) } when(hartExceptionWrEn) { assert(hartExceptionId === 0.U, "Unexpected 'EXCEPTION' hart")//Chisel3 #540, %x, expected %x", hartExceptionId, 0.U) ctrlStateNxt := CtrlState(Waiting) errorException := true.B } }.elsewhen (ctrlStateReg === CtrlState(Custom)) { assert(needCustom.B, "Should not be in custom state unless we need it.") goCustom := true.B val (custom, customP) = customNode.in.head when (custom.ready && custom.valid) { ctrlStateNxt := CtrlState(Waiting) } } when (~io.dmactive || ~dmAuthenticated) { ctrlStateReg := CtrlState(Waiting) }.otherwise { ctrlStateReg := ctrlStateNxt } assert ((!io.dmactive || !hartExceptionWrEn || ctrlStateReg === CtrlState(Exec)), "Unexpected EXCEPTION write: should only get it in Debug Module EXEC state") } } // Wrapper around TL Debug Module Inner and an Async DMI Sink interface. // Handles the synchronization of dmactive, which is used as a synchronous reset // inside the Inner block. // Also is the Sink side of hartsel & resumereq fields of DMCONTROL. class TLDebugModuleInnerAsync(device: Device, getNComponents: () => Int, beatBytes: Int)(implicit p: Parameters) extends LazyModule{ val cfg = p(DebugModuleKey).get val dmInner = LazyModule(new TLDebugModuleInner(device, getNComponents, beatBytes)) val dmiXing = LazyModule(new TLAsyncCrossingSink(AsyncQueueParams.singleton(safe=cfg.crossingHasSafeReset))) val dmiNode = dmiXing.node val tlNode = dmInner.tlNode dmInner.dmiNode := dmiXing.node // Require that there are no registers in TL interface, so that spurious // processor accesses to the DM don't need to enable the clock. We don't // require this property of the SBA, because the debugger is responsible for // raising dmactive (hence enabling the clock) during these transactions. require(dmInner.tlNode.concurrency == 0) lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { // Clock/reset domains: // debug_clock / debug_reset = Debug inner domain // tl_clock / tl_reset = tilelink domain (External: clock / reset) // val io = IO(new Bundle { val debug_clock = Input(Clock()) val debug_reset = Input(Reset()) val tl_clock = Input(Clock()) val tl_reset = Input(Reset()) // These are all asynchronous and come from Outer /** reset signal for DM */ val dmactive = Input(Bool()) /** conrol signals for Inner * * generated in Outer */ val innerCtrl = Flipped(new AsyncBundle(new DebugInternalBundle(getNComponents()), AsyncQueueParams.singleton(safe=cfg.crossingHasSafeReset))) // This comes from tlClk domain. /** debug available status */ val debugUnavail = Input(Vec(getNComponents(), Bool())) /** debug interruption*/ val hgDebugInt = Output(Vec(getNComponents(), Bool())) val extTrigger = (p(DebugModuleKey).get.nExtTriggers > 0).option(new DebugExtTriggerIO()) /** vector to indicate which hart is in reset * * dm receives it from core and sends it to Inner */ val hartIsInReset = Input(Vec(getNComponents(), Bool())) /** Debug Authentication signals from core */ val auth = p(DebugModuleKey).get.hasAuthentication.option(new DebugAuthenticationIO()) }) val rf_reset = IO(Input(Reset())) // RF transform childClock := io.debug_clock childReset := io.debug_reset override def provideImplicitClockToLazyChildren = true val dmactive_synced = withClockAndReset(childClock, childReset) { val dmactive_synced = AsyncResetSynchronizerShiftReg(in=io.dmactive, sync=3, name=Some("dmactiveSync")) dmInner.module.clock := io.debug_clock dmInner.module.reset := io.debug_reset dmInner.module.io.tl_clock := io.tl_clock dmInner.module.io.tl_reset := io.tl_reset dmInner.module.io.dmactive := dmactive_synced dmInner.module.io.innerCtrl <> FromAsyncBundle(io.innerCtrl) dmInner.module.io.debugUnavail := io.debugUnavail io.hgDebugInt := dmInner.module.io.hgDebugInt io.extTrigger.foreach { x => dmInner.module.io.extTrigger.foreach {y => x <> y}} dmInner.module.io.hartIsInReset := io.hartIsInReset io.auth.foreach { x => dmInner.module.io.auth.foreach {y => x <> y}} dmactive_synced } } } /** Create a version of the TLDebugModule which includes a synchronization interface * internally for the DMI. This is no longer optional outside of this module * because the Clock must run when tl_clock isn't running or tl_reset is asserted. */ class TLDebugModule(beatBytes: Int)(implicit p: Parameters) extends LazyModule { val device = new SimpleDevice("debug-controller", Seq("sifive,debug-013","riscv,debug-013")){ override val alwaysExtended = true override def describe(resources: ResourceBindings): Description = { val Description(name, mapping) = super.describe(resources) val attach = Map( "debug-attach" -> ( (if (p(ExportDebug).apb) Seq(ResourceString("apb")) else Seq()) ++ (if (p(ExportDebug).jtag) Seq(ResourceString("jtag")) else Seq()) ++ (if (p(ExportDebug).cjtag) Seq(ResourceString("cjtag")) else Seq()) ++ (if (p(ExportDebug).dmi) Seq(ResourceString("dmi")) else Seq()))) Description(name, mapping ++ attach) } } val dmOuter : TLDebugModuleOuterAsync = LazyModule(new TLDebugModuleOuterAsync(device)(p)) val dmInner : TLDebugModuleInnerAsync = LazyModule(new TLDebugModuleInnerAsync(device, () => {dmOuter.dmOuter.intnode.edges.out.size}, beatBytes)(p)) val node = dmInner.tlNode val intnode = dmOuter.intnode val apbNodeOpt = dmOuter.apbNodeOpt dmInner.dmiNode := dmOuter.dmiInnerNode lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { val nComponents = dmOuter.dmOuter.intnode.edges.out.size // Clock/reset domains: // tl_clock / tl_reset = tilelink domain // debug_clock / debug_reset = Inner debug (synchronous to tl_clock) // apb_clock / apb_reset = Outer debug with APB // dmiClock / dmiReset = Outer debug without APB // val io = IO(new Bundle { val debug_clock = Input(Clock()) val debug_reset = Input(Reset()) val tl_clock = Input(Clock()) val tl_reset = Input(Reset()) /** Debug control signals generated in Outer */ val ctrl = new DebugCtrlBundle(nComponents) /** Debug Module Interface bewteen DM and DTM * * The DTM provides access to one or more Debug Modules (DMs) using DMI */ val dmi = (!p(ExportDebug).apb).option(Flipped(new ClockedDMIIO())) val apb_clock = p(ExportDebug).apb.option(Input(Clock())) val apb_reset = p(ExportDebug).apb.option(Input(Reset())) val extTrigger = (p(DebugModuleKey).get.nExtTriggers > 0).option(new DebugExtTriggerIO()) /** vector to indicate which hart is in reset * * dm receives it from core and sends it to Inner */ val hartIsInReset = Input(Vec(nComponents, Bool())) /** hart reset request generated by hartreset-logic in Outer */ val hartResetReq = p(DebugModuleKey).get.hasHartResets.option(Output(Vec(nComponents, Bool()))) /** Debug Authentication signals from core */ val auth = p(DebugModuleKey).get.hasAuthentication.option(new DebugAuthenticationIO()) }) childClock := io.tl_clock childReset := io.tl_reset override def provideImplicitClockToLazyChildren = true dmOuter.module.io.dmi.foreach { dmOuterDMI => dmOuterDMI <> io.dmi.get.dmi dmOuter.module.io.dmi_reset := io.dmi.get.dmiReset dmOuter.module.io.dmi_clock := io.dmi.get.dmiClock dmOuter.module.rf_reset := io.dmi.get.dmiReset } (io.apb_clock zip io.apb_reset) foreach { case (c, r) => dmOuter.module.io.dmi_reset := r dmOuter.module.io.dmi_clock := c dmOuter.module.rf_reset := r } dmInner.module.rf_reset := io.debug_reset dmInner.module.io.debug_clock := io.debug_clock dmInner.module.io.debug_reset := io.debug_reset dmInner.module.io.tl_clock := io.tl_clock dmInner.module.io.tl_reset := io.tl_reset dmInner.module.io.innerCtrl <> dmOuter.module.io.innerCtrl dmInner.module.io.dmactive := dmOuter.module.io.ctrl.dmactive dmInner.module.io.debugUnavail := io.ctrl.debugUnavail dmOuter.module.io.hgDebugInt := dmInner.module.io.hgDebugInt io.ctrl <> dmOuter.module.io.ctrl io.extTrigger.foreach { x => dmInner.module.io.extTrigger.foreach {y => x <> y}} dmInner.module.io.hartIsInReset := io.hartIsInReset io.hartResetReq.foreach { x => dmOuter.module.io.hartResetReq.foreach {y => x := y}} io.auth.foreach { x => dmOuter.module.io.dmAuthenticated.get := x.dmAuthenticated } io.auth.foreach { x => dmInner.module.io.auth.foreach {y => x <> y}} } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File SBA.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.devices.debug.systembusaccess import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.amba.{AMBAProt, AMBAProtField} import freechips.rocketchip.devices.debug.{DebugModuleKey, RWNotify, SBCSFields, WNotifyVal} import freechips.rocketchip.diplomacy.TransferSizes import freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldGroup, RegFieldWrType} import freechips.rocketchip.tilelink.{TLClientNode, TLMasterParameters, TLMasterPortParameters} import freechips.rocketchip.util.property object SystemBusAccessState extends scala.Enumeration { type SystemBusAccessState = Value val Idle, SBReadRequest, SBWriteRequest, SBReadResponse, SBWriteResponse = Value } object SBErrorCode extends scala.Enumeration { type SBErrorCode = Value val NoError = Value(0) val Timeout = Value(1) val BadAddr = Value(2) val AlgnError = Value(3) val BadAccess = Value(4) val OtherError = Value(7) } object SystemBusAccessModule { def apply(sb2tl: SBToTL, dmactive: Bool, dmAuthenticated: Bool)(implicit p: Parameters): (Seq[RegField], Seq[Seq[RegField]], Seq[Seq[RegField]]) = { import SBErrorCode._ val cfg = p(DebugModuleKey).get val anyAddressWrEn = WireInit(false.B).suggestName("anyAddressWrEn") val anyDataRdEn = WireInit(false.B).suggestName("anyDataRdEn") val anyDataWrEn = WireInit(false.B).suggestName("anyDataWrEn") // --- SBCS Status Register --- val SBCSFieldsReg = Reg(new SBCSFields()).suggestName("SBCSFieldsReg") val SBCSFieldsRegReset = WireInit(0.U.asTypeOf(new SBCSFields())) SBCSFieldsRegReset.sbversion := 1.U(1.W) // This code implements a version of the spec after January 1, 2018 SBCSFieldsRegReset.sbbusy := (sb2tl.module.io.sbStateOut =/= SystemBusAccessState.Idle.id.U) SBCSFieldsRegReset.sbaccess := 2.U SBCSFieldsRegReset.sbasize := sb2tl.module.edge.bundle.addressBits.U SBCSFieldsRegReset.sbaccess128 := (cfg.maxSupportedSBAccess == 128).B SBCSFieldsRegReset.sbaccess64 := (cfg.maxSupportedSBAccess >= 64).B SBCSFieldsRegReset.sbaccess32 := (cfg.maxSupportedSBAccess >= 32).B SBCSFieldsRegReset.sbaccess16 := (cfg.maxSupportedSBAccess >= 16).B SBCSFieldsRegReset.sbaccess8 := (cfg.maxSupportedSBAccess >= 8).B val SBCSRdData = WireInit(0.U.asTypeOf(new SBCSFields())).suggestName("SBCSRdData") val SBCSWrDataVal = WireInit(0.U(32.W)) val SBCSWrData = WireInit(SBCSWrDataVal.asTypeOf(new SBCSFields())) val sberrorWrEn = WireInit(false.B) val sbreadondataWrEn = WireInit(false.B) val sbautoincrementWrEn= WireInit(false.B) val sbaccessWrEn = WireInit(false.B) val sbreadonaddrWrEn = WireInit(false.B) val sbbusyerrorWrEn = WireInit(false.B) val sbcsfields = RegFieldGroup("sbcs", Some("system bus access control and status"), Seq( RegField.r(1, SBCSRdData.sbaccess8, RegFieldDesc("sbaccess8", "8-bit accesses supported", reset=Some(if (cfg.maxSupportedSBAccess >= 8) 1 else 0))), RegField.r(1, SBCSRdData.sbaccess16, RegFieldDesc("sbaccess16", "16-bit accesses supported", reset=Some(if (cfg.maxSupportedSBAccess >= 16) 1 else 0))), RegField.r(1, SBCSRdData.sbaccess32, RegFieldDesc("sbaccess32", "32-bit accesses supported", reset=Some(if (cfg.maxSupportedSBAccess >= 32) 1 else 0))), RegField.r(1, SBCSRdData.sbaccess64, RegFieldDesc("sbaccess64", "64-bit accesses supported", reset=Some(if (cfg.maxSupportedSBAccess >= 64) 1 else 0))), RegField.r(1, SBCSRdData.sbaccess128, RegFieldDesc("sbaccess128", "128-bit accesses supported", reset=Some(if (cfg.maxSupportedSBAccess == 128) 1 else 0))), RegField.r(7, SBCSRdData.sbasize, RegFieldDesc("sbasize", "bits in address", reset=Some(sb2tl.module.edge.bundle.addressBits))), WNotifyVal(3, SBCSRdData.sberror, SBCSWrData.sberror, sberrorWrEn, RegFieldDesc("sberror", "system bus error", reset=Some(0), wrType=Some(RegFieldWrType.ONE_TO_CLEAR))), WNotifyVal(1, SBCSRdData.sbreadondata, SBCSWrData.sbreadondata, sbreadondataWrEn, RegFieldDesc("sbreadondata", "system bus read on data", reset=Some(0))), WNotifyVal(1, SBCSRdData.sbautoincrement, SBCSWrData.sbautoincrement, sbautoincrementWrEn, RegFieldDesc("sbautoincrement", "system bus auto-increment address", reset=Some(0))), WNotifyVal(3, SBCSRdData.sbaccess, SBCSWrData.sbaccess, sbaccessWrEn, RegFieldDesc("sbaccess", "system bus access size", reset=Some(2))), WNotifyVal(1, SBCSRdData.sbreadonaddr, SBCSWrData.sbreadonaddr, sbreadonaddrWrEn, RegFieldDesc("sbreadonaddr", "system bus read on data", reset=Some(0))), RegField.r(1, SBCSRdData.sbbusy, RegFieldDesc("sbbusy", "system bus access is busy", reset=Some(0))), WNotifyVal(1, SBCSRdData.sbbusyerror, SBCSWrData.sbbusyerror, sbbusyerrorWrEn, RegFieldDesc("sbbusyerror", "system bus busy error", reset=Some(0), wrType=Some(RegFieldWrType.ONE_TO_CLEAR))), RegField(6), RegField.r(3, SBCSRdData.sbversion, RegFieldDesc("sbversion", "system bus access version", reset=Some(1))), )) // --- System Bus Address Registers --- // ADDR0 Register is required // Instantiate ADDR1-3 registers as needed depending on system bus address width val hasSBAddr1 = (sb2tl.module.edge.bundle.addressBits >= 33) val hasSBAddr2 = (sb2tl.module.edge.bundle.addressBits >= 65) val hasSBAddr3 = (sb2tl.module.edge.bundle.addressBits >= 97) val hasAddr = Seq(true, hasSBAddr1, hasSBAddr2, hasSBAddr3) val SBADDRESSFieldsReg = Reg(Vec(4, UInt(32.W))) SBADDRESSFieldsReg.zipWithIndex.foreach { case(a,i) => a.suggestName("SBADDRESS"+i+"FieldsReg")} val SBADDRESSWrData = WireInit(VecInit(Seq.fill(4) {0.U(32.W)} )) val SBADDRESSRdEn = WireInit(VecInit(Seq.fill(4) {false.B} )) val SBADDRESSWrEn = WireInit(VecInit(Seq.fill(4) {false.B} )) val autoIncrementedAddr = WireInit(0.U(128.W)) autoIncrementedAddr := Cat(SBADDRESSFieldsReg.reverse) + (1.U << SBCSFieldsReg.sbaccess) autoIncrementedAddr.suggestName("autoIncrementedAddr") val sbaddrfields: Seq[Seq[RegField]] = SBADDRESSFieldsReg.zipWithIndex.map { case(a,i) => if(hasAddr(i)) { when (~dmactive || ~dmAuthenticated) { a := 0.U(32.W) }.otherwise { a := Mux(SBADDRESSWrEn(i) && !SBCSRdData.sberror && !SBCSFieldsReg.sbbusy && !SBCSFieldsReg.sbbusyerror, SBADDRESSWrData(i), Mux((sb2tl.module.io.rdDone || sb2tl.module.io.wrDone) && SBCSFieldsReg.sbautoincrement, autoIncrementedAddr(32*i+31,32*i), a)) } RegFieldGroup("dmi_sbaddr"+i, Some("SBA Address Register"), Seq(RWNotify(32, a, SBADDRESSWrData(i), SBADDRESSRdEn(i), SBADDRESSWrEn(i), Some(RegFieldDesc("dmi_sbaddr"+i, "SBA address register", reset=Some(0), volatile=true))))) } else { a := DontCare Seq.empty[RegField] } } sb2tl.module.io.addrIn := Mux(SBADDRESSWrEn(0), Cat(Cat(SBADDRESSFieldsReg.drop(1).reverse), SBADDRESSWrData(0)), Cat(SBADDRESSFieldsReg.reverse)) anyAddressWrEn := SBADDRESSWrEn.reduce(_ || _) // --- System Bus Data Registers --- // DATA0 Register is required // DATA1-3 Registers may not be needed depending on implementation val hasSBData1 = (cfg.maxSupportedSBAccess > 32) val hasSBData2And3 = (cfg.maxSupportedSBAccess == 128) val hasData = Seq(true, hasSBData1, hasSBData2And3, hasSBData2And3) val SBDATAFieldsReg = Reg(Vec(4, Vec(4, UInt(8.W)))) SBDATAFieldsReg.zipWithIndex.foreach { case(d,i) => d.zipWithIndex.foreach { case(d,j) => d.suggestName("SBDATA"+i+"BYTE"+j) }} val SBDATARdData = WireInit(VecInit(Seq.fill(4) {0.U(32.W)} )) SBDATARdData.zipWithIndex.foreach { case(d,i) => d.suggestName("SBDATARdData"+i) } val SBDATAWrData = WireInit(VecInit(Seq.fill(4) {0.U(32.W)} )) SBDATAWrData.zipWithIndex.foreach { case(d,i) => d.suggestName("SBDATAWrData"+i) } val SBDATARdEn = WireInit(VecInit(Seq.fill(4) {false.B} )) val SBDATAWrEn = WireInit(VecInit(Seq.fill(4) {false.B} )) SBDATAWrEn.zipWithIndex.foreach { case(d,i) => d.suggestName("SBDATAWrEn"+i) } val sbdatafields: Seq[Seq[RegField]] = SBDATAFieldsReg.zipWithIndex.map { case(d,i) => if(hasData(i)) { // For data registers, load enable per-byte for (j <- 0 to 3) { when (~dmactive || ~dmAuthenticated) { d(j) := 0.U(8.W) }.otherwise { d(j) := Mux(SBDATAWrEn(i) && !SBCSFieldsReg.sbbusy && !SBCSFieldsReg.sbbusyerror && !SBCSRdData.sberror, SBDATAWrData(i)(8*j+7,8*j), Mux(sb2tl.module.io.rdLoad(4*i+j), sb2tl.module.io.dataOut, d(j))) } } SBDATARdData(i) := Cat(d.reverse) RegFieldGroup("dmi_sbdata"+i, Some("SBA Data Register"), Seq(RWNotify(32, SBDATARdData(i), SBDATAWrData(i), SBDATARdEn(i), SBDATAWrEn(i), Some(RegFieldDesc("dmi_sbdata"+i, "SBA data register", reset=Some(0), volatile=true))))) } else { for (j <- 0 to 3) { d(j) := DontCare } Seq.empty[RegField] } } sb2tl.module.io.dataIn := Mux(sb2tl.module.io.wrEn,Cat(SBDATAWrData.reverse),Cat(SBDATAFieldsReg.flatten.reverse)) anyDataRdEn := SBDATARdEn.reduce(_ || _) anyDataWrEn := SBDATAWrEn.reduce(_ || _) val tryWrEn = SBDATAWrEn(0) val tryRdEn = (SBADDRESSWrEn(0) && SBCSFieldsReg.sbreadonaddr) || (SBDATARdEn(0) && SBCSFieldsReg.sbreadondata) val sbAccessError = (SBCSFieldsReg.sbaccess === 0.U) && (SBCSFieldsReg.sbaccess8 =/= 1.U) || (SBCSFieldsReg.sbaccess === 1.U) && (SBCSFieldsReg.sbaccess16 =/= 1.U) || (SBCSFieldsReg.sbaccess === 2.U) && (SBCSFieldsReg.sbaccess32 =/= 1.U) || (SBCSFieldsReg.sbaccess === 3.U) && (SBCSFieldsReg.sbaccess64 =/= 1.U) || (SBCSFieldsReg.sbaccess === 4.U) && (SBCSFieldsReg.sbaccess128 =/= 1.U) || (SBCSFieldsReg.sbaccess > 4.U) val compareAddr = Wire(UInt(32.W)) // Need use written or latched address to detect error case depending on how transaction is initiated compareAddr := Mux(SBADDRESSWrEn(0),SBADDRESSWrData(0),SBADDRESSFieldsReg(0)) val sbAlignmentError = (SBCSFieldsReg.sbaccess === 1.U) && (compareAddr(0) =/= 0.U) || (SBCSFieldsReg.sbaccess === 2.U) && (compareAddr(1,0) =/= 0.U) || (SBCSFieldsReg.sbaccess === 3.U) && (compareAddr(2,0) =/= 0.U) || (SBCSFieldsReg.sbaccess === 4.U) && (compareAddr(3,0) =/= 0.U) sbAccessError.suggestName("sbAccessError") sbAlignmentError.suggestName("sbAlignmentError") sb2tl.module.io.wrEn := dmAuthenticated && tryWrEn && !SBCSFieldsReg.sbbusy && !SBCSFieldsReg.sbbusyerror && !SBCSRdData.sberror && !sbAccessError && !sbAlignmentError sb2tl.module.io.rdEn := dmAuthenticated && tryRdEn && !SBCSFieldsReg.sbbusy && !SBCSFieldsReg.sbbusyerror && !SBCSRdData.sberror && !sbAccessError && !sbAlignmentError sb2tl.module.io.sizeIn := SBCSFieldsReg.sbaccess val sbBusy = (sb2tl.module.io.sbStateOut =/= SystemBusAccessState.Idle.id.U) when (~dmactive || ~dmAuthenticated) { SBCSFieldsReg := SBCSFieldsRegReset }.otherwise { SBCSFieldsReg.sbbusyerror := Mux(sbbusyerrorWrEn && SBCSWrData.sbbusyerror, false.B, // W1C Mux(anyAddressWrEn && sbBusy, true.B, // Set if a write to SBADDRESS occurs while busy Mux((anyDataRdEn || anyDataWrEn) && sbBusy, true.B, SBCSFieldsReg.sbbusyerror))) // Set if any access to SBDATA occurs while busy SBCSFieldsReg.sbreadonaddr := Mux(sbreadonaddrWrEn, SBCSWrData.sbreadonaddr , SBCSFieldsReg.sbreadonaddr) SBCSFieldsReg.sbautoincrement := Mux(sbautoincrementWrEn, SBCSWrData.sbautoincrement, SBCSFieldsReg.sbautoincrement) SBCSFieldsReg.sbreadondata := Mux(sbreadondataWrEn, SBCSWrData.sbreadondata , SBCSFieldsReg.sbreadondata) SBCSFieldsReg.sbaccess := Mux(sbaccessWrEn, SBCSWrData.sbaccess, SBCSFieldsReg.sbaccess) SBCSFieldsReg.sbversion := 1.U(1.W) // This code implements a version of the spec after January 1, 2018 } // sbErrorReg has a per-bit load enable since each bit can be individually cleared by writing a 1 to it val sbErrorReg = Reg(Vec(4, UInt(1.W))) when(~dmactive || ~dmAuthenticated) { for (i <- 0 until 3) sbErrorReg(i) := 0.U }.otherwise { for (i <- 0 until 3) sbErrorReg(i) := Mux(sberrorWrEn && SBCSWrData.sberror(i) === 1.U, NoError.id.U.extract(i), // W1C Mux((sb2tl.module.io.wrEn && !sb2tl.module.io.wrLegal) || (sb2tl.module.io.rdEn && !sb2tl.module.io.rdLegal), BadAddr.id.U.extract(i), // Bad address accessed Mux((tryWrEn || tryRdEn) && sbAlignmentError, AlgnError.id.U.extract(i), // Address alignment error Mux((tryWrEn || tryRdEn) && sbAccessError, BadAccess.id.U.extract(i), // Access size error Mux((sb2tl.module.io.rdDone || sb2tl.module.io.wrDone) && sb2tl.module.io.respError, OtherError.id.U.extract(i), sbErrorReg(i)))))) // Response error from TL } SBCSRdData := SBCSFieldsReg SBCSRdData.sbasize := sb2tl.module.edge.bundle.addressBits.U SBCSRdData.sbaccess128 := (cfg.maxSupportedSBAccess == 128).B SBCSRdData.sbaccess64 := (cfg.maxSupportedSBAccess >= 64).B SBCSRdData.sbaccess32 := (cfg.maxSupportedSBAccess >= 32).B SBCSRdData.sbaccess16 := (cfg.maxSupportedSBAccess >= 16).B SBCSRdData.sbaccess8 := (cfg.maxSupportedSBAccess >= 8).B SBCSRdData.sbbusy := sbBusy SBCSRdData.sberror := sbErrorReg.asUInt when (~dmAuthenticated) { // Read value must be 0 if not authenticated SBCSRdData := 0.U.asTypeOf(new SBCSFields()) } property.cover(SBCSFieldsReg.sbbusyerror, "SBCS Cover", "sberror set") property.cover(SBCSFieldsReg.sbbusy === 3.U, "SBCS Cover", "sbbusyerror alignment error") property.cover((sb2tl.module.io.wrEn || sb2tl.module.io.rdEn) && SBCSFieldsReg.sbaccess === 0.U && !sbAccessError && !sbAlignmentError, "SBCS Cover", "8-bit access") property.cover((sb2tl.module.io.wrEn || sb2tl.module.io.rdEn) && SBCSFieldsReg.sbaccess === 1.U && !sbAccessError && !sbAlignmentError, "SBCS Cover", "16-bit access") property.cover((sb2tl.module.io.wrEn || sb2tl.module.io.rdEn) && SBCSFieldsReg.sbaccess === 2.U && !sbAccessError && !sbAlignmentError, "SBCS Cover", "32-bit access") property.cover((sb2tl.module.io.wrEn || sb2tl.module.io.rdEn) && SBCSFieldsReg.sbaccess === 3.U && !sbAccessError && !sbAlignmentError, "SBCS Cover", "64-bit access") property.cover((sb2tl.module.io.wrEn || sb2tl.module.io.rdEn) && SBCSFieldsReg.sbaccess === 4.U && !sbAccessError && !sbAlignmentError, "SBCS Cover", "128-bit access") property.cover(SBCSFieldsReg.sbautoincrement && SBCSFieldsReg.sbbusy, "SBCS Cover", "Access with autoincrement set") property.cover(!SBCSFieldsReg.sbautoincrement && SBCSFieldsReg.sbbusy, "SBCS Cover", "Access without autoincrement set") property.cover((sb2tl.module.io.wrEn || sb2tl.module.io.rdEn) && SBCSFieldsReg.sbaccess > 4.U, "SBCS Cover", "Invalid sbaccess value") (sbcsfields, sbaddrfields, sbdatafields) } } class SBToTL(implicit p: Parameters) extends LazyModule { val cfg = p(DebugModuleKey).get val node = TLClientNode(Seq(TLMasterPortParameters.v1( clients = Seq(TLMasterParameters.v1("debug")), requestFields = Seq(AMBAProtField())))) lazy val module = new Impl class Impl extends LazyModuleImp(this) { val io = IO(new Bundle { val rdEn = Input(Bool()) val wrEn = Input(Bool()) val addrIn = Input(UInt(128.W)) // TODO: Parameterize these widths val dataIn = Input(UInt(128.W)) val sizeIn = Input(UInt(3.W)) val rdLegal = Output(Bool()) val wrLegal = Output(Bool()) val rdDone = Output(Bool()) val wrDone = Output(Bool()) val respError = Output(Bool()) val dataOut = Output(UInt(8.W)) val rdLoad = Output(Vec(cfg.maxSupportedSBAccess/8, Bool())) val sbStateOut = Output(UInt(log2Ceil(SystemBusAccessState.maxId).W)) }) val rf_reset = IO(Input(Reset())) import SystemBusAccessState._ val (tl, edge) = node.out(0) val sbState = RegInit(0.U) // --- Drive payloads on bus to TileLink --- val d = Queue(tl.d, 2) // Add a small buffer since response could arrive on same cycle as request d.ready := (sbState === SBReadResponse.id.U) || (sbState === SBWriteResponse.id.U) val muxedData = WireInit(0.U(8.W)) val requestValid = tl.a.valid val requestReady = tl.a.ready val responseValid = d.valid val responseReady = d.ready val counter = RegInit(0.U((log2Ceil(cfg.maxSupportedSBAccess/8)+1).W)) val vecData = Wire(Vec(cfg.maxSupportedSBAccess/8, UInt(8.W))) vecData.zipWithIndex.map { case (vd, i) => vd := io.dataIn(8*i+7,8*i) } muxedData := vecData(counter(log2Ceil(vecData.size)-1,0)) // Need an additional check to determine if address is safe for Get/Put val rdLegal_addr = edge.manager.supportsGetSafe(io.addrIn, io.sizeIn, Some(TransferSizes(1,cfg.maxSupportedSBAccess/8))) val wrLegal_addr = edge.manager.supportsPutFullSafe(io.addrIn, io.sizeIn, Some(TransferSizes(1,cfg.maxSupportedSBAccess/8))) val (_, gbits) = edge.Get(0.U, io.addrIn, io.sizeIn) val (_, pfbits) = edge.Put(0.U, io.addrIn, io.sizeIn, muxedData) io.rdLegal := rdLegal_addr io.wrLegal := wrLegal_addr io.sbStateOut := sbState when(sbState === SBReadRequest.id.U) { tl.a.bits := gbits } .otherwise { tl.a.bits := pfbits } tl.a.bits.user.lift(AMBAProt).foreach { x => x.bufferable := false.B x.modifiable := false.B x.readalloc := false.B x.writealloc := false.B x.privileged := true.B x.secure := true.B x.fetch := false.B } val respError = d.bits.denied || d.bits.corrupt io.respError := respError val wrTxValid = sbState === SBWriteRequest.id.U && requestValid && requestReady val rdTxValid = sbState === SBReadResponse.id.U && responseValid && responseReady val txLast = counter === ((1.U << io.sizeIn) - 1.U) counter := Mux((wrTxValid || rdTxValid) && txLast, 0.U, Mux((wrTxValid || rdTxValid) , counter+1.U, counter)) for (i <- 0 until (cfg.maxSupportedSBAccess/8)) { io.rdLoad(i) := rdTxValid && (counter === i.U) } // --- State Machine to interface with TileLink --- when (sbState === Idle.id.U){ sbState := Mux(io.rdEn && io.rdLegal, SBReadRequest.id.U, Mux(io.wrEn && io.wrLegal, SBWriteRequest.id.U, sbState)) }.elsewhen (sbState === SBReadRequest.id.U){ sbState := Mux(requestValid && requestReady, SBReadResponse.id.U, sbState) }.elsewhen (sbState === SBWriteRequest.id.U){ sbState := Mux(wrTxValid && txLast, SBWriteResponse.id.U, sbState) }.elsewhen (sbState === SBReadResponse.id.U){ sbState := Mux(rdTxValid && txLast, Idle.id.U, sbState) }.elsewhen (sbState === SBWriteResponse.id.U){ sbState := Mux(responseValid && responseReady, Idle.id.U, sbState) } io.rdDone := rdTxValid && txLast io.wrDone := (sbState === SBWriteResponse.id.U) && responseValid && responseReady io.dataOut := d.bits.data tl.a.valid := (sbState === SBReadRequest.id.U) || (sbState === SBWriteRequest.id.U) // Tie off unused channels tl.b.ready := false.B tl.c.valid := false.B tl.e.valid := false.B assert (sbState === Idle.id.U || sbState === SBReadRequest.id.U || sbState === SBWriteRequest.id.U || sbState === SBReadResponse.id.U || sbState === SBWriteResponse.id.U, "SBA state machine in undefined state") property.cover (sbState === Idle.id.U, "SBA State Cover", "SBA Access Idle") property.cover (sbState === SBReadRequest.id.U, "SBA State Cover", "SBA Access Read Req") property.cover (sbState === SBWriteRequest.id.U, "SBA State Cover", "SBA Access Write Req") property.cover (sbState === SBReadResponse.id.U, "SBA State Cover", "SBA Access Read Resp") property.cover (sbState === SBWriteResponse.id.U, "SBA State Cover", "SBA Access Write Resp") property.cover (io.rdEn && !io.rdLegal, "SB Legality Cover", "SBA Rd Address Illegal") property.cover (io.wrEn && !io.wrLegal, "SB Legality Cover", "SBA Wr Address Illegal") } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module TLDebugModuleInner( // @[Debug.scala:790:9] input clock, // @[Debug.scala:790:9] input reset, // @[Debug.scala:790:9] input auto_sb2tlOpt_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_sb2tlOpt_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_sb2tlOpt_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [3:0] auto_sb2tlOpt_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [31:0] auto_sb2tlOpt_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_sb2tlOpt_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_sb2tlOpt_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_sb2tlOpt_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_sb2tlOpt_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_sb2tlOpt_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_sb2tlOpt_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_sb2tlOpt_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_sb2tlOpt_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [7:0] auto_sb2tlOpt_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_sb2tlOpt_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_tl_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_tl_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_tl_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [11:0] auto_tl_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_tl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_tl_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_tl_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_tl_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_tl_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_tl_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_dmi_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_dmi_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dmi_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dmi_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dmi_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input auto_dmi_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [8:0] auto_dmi_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dmi_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [31:0] auto_dmi_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_dmi_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_dmi_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_dmi_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_dmi_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_dmi_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output auto_dmi_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_dmi_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input io_dmactive, // @[Debug.scala:803:16] input io_innerCtrl_valid, // @[Debug.scala:803:16] input io_innerCtrl_bits_resumereq, // @[Debug.scala:803:16] input [9:0] io_innerCtrl_bits_hartsel, // @[Debug.scala:803:16] input io_innerCtrl_bits_ackhavereset, // @[Debug.scala:803:16] input io_innerCtrl_bits_hasel, // @[Debug.scala:803:16] input io_innerCtrl_bits_hamask_0, // @[Debug.scala:803:16] input io_innerCtrl_bits_hrmask_0, // @[Debug.scala:803:16] output io_hgDebugInt_0, // @[Debug.scala:803:16] input io_hartIsInReset_0, // @[Debug.scala:803:16] input io_tl_clock, // @[Debug.scala:803:16] input io_tl_reset // @[Debug.scala:803:16] ); wire out_front_1_valid; // @[RegisterRouter.scala:87:24] wire out_front_1_ready; // @[RegisterRouter.scala:87:24] wire out_1_bits_read; // @[RegisterRouter.scala:87:24] wire [10:0] out_1_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [8:0] in_1_bits_index; // @[RegisterRouter.scala:73:18] wire in_1_bits_read; // @[RegisterRouter.scala:73:18] wire [7:0] _accessRegisterCommandReg_WIRE_cmdtype; // @[Debug.scala:1533:71] wire _accessRegisterCommandReg_WIRE_reserved0; // @[Debug.scala:1533:71] wire [2:0] _accessRegisterCommandReg_WIRE_size; // @[Debug.scala:1533:71] wire _accessRegisterCommandReg_WIRE_reserved1; // @[Debug.scala:1533:71] wire _accessRegisterCommandReg_WIRE_postexec; // @[Debug.scala:1533:71] wire _accessRegisterCommandReg_WIRE_transfer; // @[Debug.scala:1533:71] wire _accessRegisterCommandReg_WIRE_write; // @[Debug.scala:1533:71] wire [15:0] _accessRegisterCommandReg_WIRE_regno; // @[Debug.scala:1533:71] wire [7:0] _accessRegisterCommandWr_WIRE_cmdtype; // @[Debug.scala:1531:74] wire _accessRegisterCommandWr_WIRE_reserved0; // @[Debug.scala:1531:74] wire [2:0] _accessRegisterCommandWr_WIRE_size; // @[Debug.scala:1531:74] wire _accessRegisterCommandWr_WIRE_reserved1; // @[Debug.scala:1531:74] wire _accessRegisterCommandWr_WIRE_postexec; // @[Debug.scala:1531:74] wire _accessRegisterCommandWr_WIRE_transfer; // @[Debug.scala:1531:74] wire _accessRegisterCommandWr_WIRE_write; // @[Debug.scala:1531:74] wire [15:0] _accessRegisterCommandWr_WIRE_regno; // @[Debug.scala:1531:74] wire out_front_valid; // @[RegisterRouter.scala:87:24] wire out_front_ready; // @[RegisterRouter.scala:87:24] wire out_bits_read; // @[RegisterRouter.scala:87:24] wire out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [6:0] in_bits_index; // @[RegisterRouter.scala:73:18] wire in_bits_read; // @[RegisterRouter.scala:73:18] wire SBDATAWrEn_0; // @[SBA.scala:150:35] wire [31:0] SBDATARdData_1; // @[SBA.scala:145:35] wire [31:0] SBDATARdData_0; // @[SBA.scala:145:35] wire SBADDRESSWrEn_0; // @[SBA.scala:108:38] wire [7:0] _COMMANDWrData_WIRE_cmdtype; // @[Debug.scala:1280:65] wire [23:0] _COMMANDWrData_WIRE_control; // @[Debug.scala:1280:65] wire [15:0] ABSTRACTAUTOWrData_autoexecprogbuf; // @[Debug.scala:1236:41] wire [31:0] _HALTSUM1RdData_WIRE; // @[Debug.scala:1170:48] wire _sb2tlOpt_io_rdLegal; // @[Debug.scala:782:52] wire _sb2tlOpt_io_wrLegal; // @[Debug.scala:782:52] wire _sb2tlOpt_io_rdDone; // @[Debug.scala:782:52] wire _sb2tlOpt_io_wrDone; // @[Debug.scala:782:52] wire _sb2tlOpt_io_respError; // @[Debug.scala:782:52] wire [7:0] _sb2tlOpt_io_dataOut; // @[Debug.scala:782:52] wire _sb2tlOpt_io_rdLoad_0; // @[Debug.scala:782:52] wire _sb2tlOpt_io_rdLoad_1; // @[Debug.scala:782:52] wire _sb2tlOpt_io_rdLoad_2; // @[Debug.scala:782:52] wire _sb2tlOpt_io_rdLoad_3; // @[Debug.scala:782:52] wire _sb2tlOpt_io_rdLoad_4; // @[Debug.scala:782:52] wire _sb2tlOpt_io_rdLoad_5; // @[Debug.scala:782:52] wire _sb2tlOpt_io_rdLoad_6; // @[Debug.scala:782:52] wire _sb2tlOpt_io_rdLoad_7; // @[Debug.scala:782:52] wire [2:0] _sb2tlOpt_io_sbStateOut; // @[Debug.scala:782:52] wire auto_sb2tlOpt_out_a_ready_0 = auto_sb2tlOpt_out_a_ready; // @[Debug.scala:790:9] wire auto_sb2tlOpt_out_d_valid_0 = auto_sb2tlOpt_out_d_valid; // @[Debug.scala:790:9] wire [2:0] auto_sb2tlOpt_out_d_bits_opcode_0 = auto_sb2tlOpt_out_d_bits_opcode; // @[Debug.scala:790:9] wire [1:0] auto_sb2tlOpt_out_d_bits_param_0 = auto_sb2tlOpt_out_d_bits_param; // @[Debug.scala:790:9] wire [3:0] auto_sb2tlOpt_out_d_bits_size_0 = auto_sb2tlOpt_out_d_bits_size; // @[Debug.scala:790:9] wire [2:0] auto_sb2tlOpt_out_d_bits_sink_0 = auto_sb2tlOpt_out_d_bits_sink; // @[Debug.scala:790:9] wire auto_sb2tlOpt_out_d_bits_denied_0 = auto_sb2tlOpt_out_d_bits_denied; // @[Debug.scala:790:9] wire [7:0] auto_sb2tlOpt_out_d_bits_data_0 = auto_sb2tlOpt_out_d_bits_data; // @[Debug.scala:790:9] wire auto_sb2tlOpt_out_d_bits_corrupt_0 = auto_sb2tlOpt_out_d_bits_corrupt; // @[Debug.scala:790:9] wire auto_tl_in_a_valid_0 = auto_tl_in_a_valid; // @[Debug.scala:790:9] wire [2:0] auto_tl_in_a_bits_opcode_0 = auto_tl_in_a_bits_opcode; // @[Debug.scala:790:9] wire [2:0] auto_tl_in_a_bits_param_0 = auto_tl_in_a_bits_param; // @[Debug.scala:790:9] wire [1:0] auto_tl_in_a_bits_size_0 = auto_tl_in_a_bits_size; // @[Debug.scala:790:9] wire [10:0] auto_tl_in_a_bits_source_0 = auto_tl_in_a_bits_source; // @[Debug.scala:790:9] wire [11:0] auto_tl_in_a_bits_address_0 = auto_tl_in_a_bits_address; // @[Debug.scala:790:9] wire [7:0] auto_tl_in_a_bits_mask_0 = auto_tl_in_a_bits_mask; // @[Debug.scala:790:9] wire [63:0] auto_tl_in_a_bits_data_0 = auto_tl_in_a_bits_data; // @[Debug.scala:790:9] wire auto_tl_in_a_bits_corrupt_0 = auto_tl_in_a_bits_corrupt; // @[Debug.scala:790:9] wire auto_tl_in_d_ready_0 = auto_tl_in_d_ready; // @[Debug.scala:790:9] wire auto_dmi_in_a_valid_0 = auto_dmi_in_a_valid; // @[Debug.scala:790:9] wire [2:0] auto_dmi_in_a_bits_opcode_0 = auto_dmi_in_a_bits_opcode; // @[Debug.scala:790:9] wire [2:0] auto_dmi_in_a_bits_param_0 = auto_dmi_in_a_bits_param; // @[Debug.scala:790:9] wire [1:0] auto_dmi_in_a_bits_size_0 = auto_dmi_in_a_bits_size; // @[Debug.scala:790:9] wire auto_dmi_in_a_bits_source_0 = auto_dmi_in_a_bits_source; // @[Debug.scala:790:9] wire [8:0] auto_dmi_in_a_bits_address_0 = auto_dmi_in_a_bits_address; // @[Debug.scala:790:9] wire [3:0] auto_dmi_in_a_bits_mask_0 = auto_dmi_in_a_bits_mask; // @[Debug.scala:790:9] wire [31:0] auto_dmi_in_a_bits_data_0 = auto_dmi_in_a_bits_data; // @[Debug.scala:790:9] wire auto_dmi_in_a_bits_corrupt_0 = auto_dmi_in_a_bits_corrupt; // @[Debug.scala:790:9] wire auto_dmi_in_d_ready_0 = auto_dmi_in_d_ready; // @[Debug.scala:790:9] wire io_dmactive_0 = io_dmactive; // @[Debug.scala:790:9] wire io_innerCtrl_valid_0 = io_innerCtrl_valid; // @[Debug.scala:790:9] wire io_innerCtrl_bits_resumereq_0 = io_innerCtrl_bits_resumereq; // @[Debug.scala:790:9] wire [9:0] io_innerCtrl_bits_hartsel_0 = io_innerCtrl_bits_hartsel; // @[Debug.scala:790:9] wire io_innerCtrl_bits_ackhavereset_0 = io_innerCtrl_bits_ackhavereset; // @[Debug.scala:790:9] wire io_innerCtrl_bits_hasel_0 = io_innerCtrl_bits_hasel; // @[Debug.scala:790:9] wire io_innerCtrl_bits_hamask_0_0 = io_innerCtrl_bits_hamask_0; // @[Debug.scala:790:9] wire io_innerCtrl_bits_hrmask_0_0 = io_innerCtrl_bits_hrmask_0; // @[Debug.scala:790:9] wire io_hartIsInReset_0_0 = io_hartIsInReset_0; // @[Debug.scala:790:9] wire io_tl_clock_0 = io_tl_clock; // @[Debug.scala:790:9] wire io_tl_reset_0 = io_tl_reset; // @[Debug.scala:790:9] wire auto_sb2tlOpt_out_a_bits_source = 1'h0; // @[Debug.scala:790:9] wire auto_sb2tlOpt_out_a_bits_corrupt = 1'h0; // @[Debug.scala:790:9] wire auto_sb2tlOpt_out_d_bits_source = 1'h0; // @[Debug.scala:790:9] wire auto_custom_in_addr = 1'h0; // @[Debug.scala:790:9] wire auto_custom_in_ready = 1'h0; // @[Debug.scala:790:9] wire auto_custom_in_valid = 1'h0; // @[Debug.scala:790:9] wire auto_tl_in_d_bits_sink = 1'h0; // @[Debug.scala:790:9] wire auto_tl_in_d_bits_denied = 1'h0; // @[Debug.scala:790:9] wire auto_tl_in_d_bits_corrupt = 1'h0; // @[Debug.scala:790:9] wire auto_dmi_in_d_bits_sink = 1'h0; // @[Debug.scala:790:9] wire auto_dmi_in_d_bits_denied = 1'h0; // @[Debug.scala:790:9] wire auto_dmi_in_d_bits_corrupt = 1'h0; // @[Debug.scala:790:9] wire io_debugUnavail_0 = 1'h0; // @[Debug.scala:790:9] wire dmiNodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire dmiNodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire dmiNodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire tlNodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire tlNodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire tlNodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire customNodeIn_addr = 1'h0; // @[MixedNode.scala:551:17] wire customNodeIn_ready = 1'h0; // @[MixedNode.scala:551:17] wire customNodeIn_valid = 1'h0; // @[MixedNode.scala:551:17] wire _dmiProgramBufferRdEn_WIRE_0 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_1 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_2 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_3 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_4 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_5 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_6 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_7 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_8 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_9 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_10 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_11 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_12 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_13 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_14 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_15 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_16 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_17 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_18 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_19 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_20 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_21 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_22 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_23 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_24 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_25 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_26 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_27 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_28 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_29 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_30 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_31 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_32 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_33 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_34 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_35 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_36 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_37 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_38 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_39 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_40 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_41 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_42 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_43 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_44 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_45 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_46 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_47 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_48 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_49 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_50 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_51 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_52 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_53 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_54 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_55 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_56 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_57 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_58 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_59 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_60 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_61 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_62 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_63 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferWrEnMaybe_WIRE_0 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_1 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_2 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_3 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_4 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_5 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_6 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_7 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_8 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_9 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_10 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_11 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_12 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_13 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_14 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_15 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_16 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_17 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_18 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_19 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_20 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_21 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_22 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_23 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_24 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_25 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_26 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_27 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_28 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_29 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_30 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_31 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_32 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_33 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_34 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_35 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_36 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_37 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_38 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_39 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_40 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_41 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_42 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_43 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_44 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_45 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_46 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_47 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_48 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_49 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_50 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_51 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_52 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_53 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_54 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_55 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_56 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_57 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_58 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_59 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_60 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_61 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_62 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_63 = 1'h0; // @[Debug.scala:889:53] wire _dmiAbstractDataRdEn_WIRE_0 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_1 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_2 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_3 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_4 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_5 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_6 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_7 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_8 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_9 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_10 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_11 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_12 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_13 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_14 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_15 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_16 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_17 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_18 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_19 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_20 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_21 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_22 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_23 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_24 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_25 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_26 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_27 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_28 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_29 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_30 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_31 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataWrEnMaybe_WIRE_0 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_1 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_2 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_3 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_4 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_5 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_6 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_7 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_8 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_9 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_10 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_11 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_12 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_13 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_14 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_15 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_16 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_17 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_18 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_19 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_20 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_21 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_22 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_23 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_24 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_25 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_26 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_27 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_28 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_29 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_30 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_31 = 1'h0; // @[Debug.scala:893:52] wire _hamaskFull_WIRE_0 = 1'h0; // @[Debug.scala:903:38] wire _hamaskWrSel_WIRE_0 = 1'h0; // @[Debug.scala:933:39] wire _hrReset_WIRE_0 = 1'h0; // @[Debug.scala:945:38] wire hrReset_0 = 1'h0; // @[Debug.scala:945:30] wire _hrDebugIntReg_WIRE_0 = 1'h0; // @[Debug.scala:961:42] wire _DMSTATUSRdData_WIRE_impebreak = 1'h0; // @[Debug.scala:978:47] wire _DMSTATUSRdData_WIRE_allhavereset = 1'h0; // @[Debug.scala:978:47] wire _DMSTATUSRdData_WIRE_anyhavereset = 1'h0; // @[Debug.scala:978:47] wire _DMSTATUSRdData_WIRE_allresumeack = 1'h0; // @[Debug.scala:978:47] wire _DMSTATUSRdData_WIRE_anyresumeack = 1'h0; // @[Debug.scala:978:47] wire _DMSTATUSRdData_WIRE_allnonexistent = 1'h0; // @[Debug.scala:978:47] wire _DMSTATUSRdData_WIRE_anynonexistent = 1'h0; // @[Debug.scala:978:47] wire _DMSTATUSRdData_WIRE_allunavail = 1'h0; // @[Debug.scala:978:47] wire _DMSTATUSRdData_WIRE_anyunavail = 1'h0; // @[Debug.scala:978:47] wire _DMSTATUSRdData_WIRE_allrunning = 1'h0; // @[Debug.scala:978:47] wire _DMSTATUSRdData_WIRE_anyrunning = 1'h0; // @[Debug.scala:978:47] wire _DMSTATUSRdData_WIRE_allhalted = 1'h0; // @[Debug.scala:978:47] wire _DMSTATUSRdData_WIRE_anyhalted = 1'h0; // @[Debug.scala:978:47] wire _DMSTATUSRdData_WIRE_authenticated = 1'h0; // @[Debug.scala:978:47] wire _DMSTATUSRdData_WIRE_authbusy = 1'h0; // @[Debug.scala:978:47] wire _DMSTATUSRdData_WIRE_hasresethaltreq = 1'h0; // @[Debug.scala:978:47] wire _DMSTATUSRdData_WIRE_confstrptrvalid = 1'h0; // @[Debug.scala:978:47] wire DMSTATUSRdData_impebreak = 1'h0; // @[Debug.scala:978:34] wire DMSTATUSRdData_anyunavail = 1'h0; // @[Debug.scala:978:34] wire DMSTATUSRdData_authbusy = 1'h0; // @[Debug.scala:978:34] wire DMSTATUSRdData_confstrptrvalid = 1'h0; // @[Debug.scala:978:34] wire _DMSTATUSRdData_anynonexistent_T = 1'h0; // @[Debug.scala:988:57] wire _DMSTATUSRdData_allnonexistent_T = 1'h0; // @[Debug.scala:991:57] wire _DMSTATUSRdData_anyunavail_T = 1'h0; // @[package.scala:74:72] wire _DMCS2RdData_WIRE_hgwrite = 1'h0; // @[Debug.scala:1025:47] wire _DMCS2RdData_WIRE_hgselect = 1'h0; // @[Debug.scala:1025:47] wire DMCS2RdData_hgwrite = 1'h0; // @[Debug.scala:1025:34] wire DMCS2RdData_hgselect = 1'h0; // @[Debug.scala:1025:34] wire _DMCS2WrData_WIRE_hgwrite = 1'h0; // @[Debug.scala:1026:47] wire _DMCS2WrData_WIRE_hgselect = 1'h0; // @[Debug.scala:1026:47] wire DMCS2WrData_hgwrite = 1'h0; // @[Debug.scala:1026:34] wire DMCS2WrData_hgselect = 1'h0; // @[Debug.scala:1026:34] wire hgselectWrEn = 1'h0; // @[Debug.scala:1027:34] wire hgwriteWrEn = 1'h0; // @[Debug.scala:1028:34] wire haltgroupWrEn = 1'h0; // @[Debug.scala:1029:34] wire exttriggerWrEn = 1'h0; // @[Debug.scala:1030:34] wire _hgDebugInt_WIRE_0 = 1'h0; // @[Debug.scala:1031:42] wire hgDebugInt_0 = 1'h0; // @[Debug.scala:1031:34] wire _selectedHaltedStatus_T = 1'h0; // @[Debug.scala:1172:53] wire _selectedHaltedStatus_T_1 = 1'h0; // @[Debug.scala:1172:59] wire _selectedHaltedStatus_T_2 = 1'h0; // @[Debug.scala:1172:114] wire _selectedHaltedStatus_WIRE = 1'h0; wire _ABSTRACTCSReset_WIRE_busy = 1'h0; // @[Debug.scala:1179:48] wire _ABSTRACTCSReset_WIRE_reserved2 = 1'h0; // @[Debug.scala:1179:48] wire ABSTRACTCSReset_busy = 1'h0; // @[Debug.scala:1179:35] wire ABSTRACTCSReset_reserved2 = 1'h0; // @[Debug.scala:1179:35] wire _ABSTRACTCSWrData_WIRE_busy = 1'h0; // @[Debug.scala:1184:52] wire _ABSTRACTCSWrData_WIRE_reserved2 = 1'h0; // @[Debug.scala:1184:52] wire ABSTRACTCSWrData_busy = 1'h0; // @[Debug.scala:1184:39] wire ABSTRACTCSWrData_reserved2 = 1'h0; // @[Debug.scala:1184:39] wire ABSTRACTCSRdData_reserved2 = 1'h0; // @[Debug.scala:1185:39] wire ABSTRACTCSRdEn = 1'h0; // @[Debug.scala:1187:34] wire ABSTRACTAUTORdEn = 1'h0; // @[Debug.scala:1239:36] wire _dmiAbstractDataAccessVec_WIRE_0 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_1 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_2 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_3 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_4 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_5 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_6 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_7 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_8 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_9 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_10 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_11 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_12 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_13 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_14 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_15 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_16 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_17 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_18 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_19 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_20 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_21 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_22 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_23 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_24 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_25 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_26 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_27 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_28 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_29 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_30 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_31 = 1'h0; // @[Debug.scala:1257:53] wire _dmiProgramBufferAccessVec_WIRE_0 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_1 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_2 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_3 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_4 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_5 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_6 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_7 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_8 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_9 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_10 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_11 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_12 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_13 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_14 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_15 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_16 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_17 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_18 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_19 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_20 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_21 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_22 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_23 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_24 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_25 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_26 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_27 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_28 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_29 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_30 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_31 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_32 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_33 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_34 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_35 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_36 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_37 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_38 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_39 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_40 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_41 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_42 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_43 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_44 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_45 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_46 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_47 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_48 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_49 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_50 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_51 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_52 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_53 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_54 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_55 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_56 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_57 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_58 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_59 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_60 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_61 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_62 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_63 = 1'h0; // @[Debug.scala:1260:54] wire _autoexecData_WIRE_0 = 1'h0; // @[Debug.scala:1267:41] wire _autoexecData_WIRE_1 = 1'h0; // @[Debug.scala:1267:41] wire _autoexecData_WIRE_2 = 1'h0; // @[Debug.scala:1267:41] wire _autoexecData_WIRE_3 = 1'h0; // @[Debug.scala:1267:41] wire _autoexecData_WIRE_4 = 1'h0; // @[Debug.scala:1267:41] wire _autoexecData_WIRE_5 = 1'h0; // @[Debug.scala:1267:41] wire _autoexecData_WIRE_6 = 1'h0; // @[Debug.scala:1267:41] wire _autoexecData_WIRE_7 = 1'h0; // @[Debug.scala:1267:41] wire _autoexecProg_WIRE_0 = 1'h0; // @[Debug.scala:1268:41] wire _autoexecProg_WIRE_1 = 1'h0; // @[Debug.scala:1268:41] wire _autoexecProg_WIRE_2 = 1'h0; // @[Debug.scala:1268:41] wire _autoexecProg_WIRE_3 = 1'h0; // @[Debug.scala:1268:41] wire _autoexecProg_WIRE_4 = 1'h0; // @[Debug.scala:1268:41] wire _autoexecProg_WIRE_5 = 1'h0; // @[Debug.scala:1268:41] wire _autoexecProg_WIRE_6 = 1'h0; // @[Debug.scala:1268:41] wire _autoexecProg_WIRE_7 = 1'h0; // @[Debug.scala:1268:41] wire _autoexecProg_WIRE_8 = 1'h0; // @[Debug.scala:1268:41] wire _autoexecProg_WIRE_9 = 1'h0; // @[Debug.scala:1268:41] wire _autoexecProg_WIRE_10 = 1'h0; // @[Debug.scala:1268:41] wire _autoexecProg_WIRE_11 = 1'h0; // @[Debug.scala:1268:41] wire _autoexecProg_WIRE_12 = 1'h0; // @[Debug.scala:1268:41] wire _autoexecProg_WIRE_13 = 1'h0; // @[Debug.scala:1268:41] wire _autoexecProg_WIRE_14 = 1'h0; // @[Debug.scala:1268:41] wire _autoexecProg_WIRE_15 = 1'h0; // @[Debug.scala:1268:41] wire authRdEnMaybe = 1'h0; // @[Debug.scala:1356:33] wire authWrEnMaybe = 1'h0; // @[Debug.scala:1357:33] wire _SBCSFieldsRegReset_WIRE_sbbusyerror = 1'h0; // @[SBA.scala:49:51] wire _SBCSFieldsRegReset_WIRE_sbbusy = 1'h0; // @[SBA.scala:49:51] wire _SBCSFieldsRegReset_WIRE_sbreadonaddr = 1'h0; // @[SBA.scala:49:51] wire _SBCSFieldsRegReset_WIRE_sbautoincrement = 1'h0; // @[SBA.scala:49:51] wire _SBCSFieldsRegReset_WIRE_sbreadondata = 1'h0; // @[SBA.scala:49:51] wire _SBCSFieldsRegReset_WIRE_sbaccess128 = 1'h0; // @[SBA.scala:49:51] wire _SBCSFieldsRegReset_WIRE_sbaccess64 = 1'h0; // @[SBA.scala:49:51] wire _SBCSFieldsRegReset_WIRE_sbaccess32 = 1'h0; // @[SBA.scala:49:51] wire _SBCSFieldsRegReset_WIRE_sbaccess16 = 1'h0; // @[SBA.scala:49:51] wire _SBCSFieldsRegReset_WIRE_sbaccess8 = 1'h0; // @[SBA.scala:49:51] wire SBCSFieldsRegReset_sbbusyerror = 1'h0; // @[SBA.scala:49:38] wire SBCSFieldsRegReset_sbreadonaddr = 1'h0; // @[SBA.scala:49:38] wire SBCSFieldsRegReset_sbautoincrement = 1'h0; // @[SBA.scala:49:38] wire SBCSFieldsRegReset_sbreadondata = 1'h0; // @[SBA.scala:49:38] wire SBCSFieldsRegReset_sbaccess128 = 1'h0; // @[SBA.scala:49:38] wire _SBCSRdData_WIRE_sbbusyerror = 1'h0; // @[SBA.scala:60:51] wire _SBCSRdData_WIRE_sbbusy = 1'h0; // @[SBA.scala:60:51] wire _SBCSRdData_WIRE_sbreadonaddr = 1'h0; // @[SBA.scala:60:51] wire _SBCSRdData_WIRE_sbautoincrement = 1'h0; // @[SBA.scala:60:51] wire _SBCSRdData_WIRE_sbreadondata = 1'h0; // @[SBA.scala:60:51] wire _SBCSRdData_WIRE_sbaccess128 = 1'h0; // @[SBA.scala:60:51] wire _SBCSRdData_WIRE_sbaccess64 = 1'h0; // @[SBA.scala:60:51] wire _SBCSRdData_WIRE_sbaccess32 = 1'h0; // @[SBA.scala:60:51] wire _SBCSRdData_WIRE_sbaccess16 = 1'h0; // @[SBA.scala:60:51] wire _SBCSRdData_WIRE_sbaccess8 = 1'h0; // @[SBA.scala:60:51] wire SBCSRdData_sbaccess128 = 1'h0; // @[SBA.scala:60:38] wire _SBCSWrData_WIRE_sbbusyerror = 1'h0; // @[SBA.scala:63:61] wire _SBCSWrData_WIRE_sbbusy = 1'h0; // @[SBA.scala:63:61] wire _SBCSWrData_WIRE_sbreadonaddr = 1'h0; // @[SBA.scala:63:61] wire _SBCSWrData_WIRE_sbautoincrement = 1'h0; // @[SBA.scala:63:61] wire _SBCSWrData_WIRE_sbreadondata = 1'h0; // @[SBA.scala:63:61] wire _SBCSWrData_WIRE_sbaccess128 = 1'h0; // @[SBA.scala:63:61] wire _SBCSWrData_WIRE_sbaccess64 = 1'h0; // @[SBA.scala:63:61] wire _SBCSWrData_WIRE_sbaccess32 = 1'h0; // @[SBA.scala:63:61] wire _SBCSWrData_WIRE_sbaccess16 = 1'h0; // @[SBA.scala:63:61] wire _SBCSWrData_WIRE_sbaccess8 = 1'h0; // @[SBA.scala:63:61] wire _SBCSWrData_T = 1'h0; // @[SBA.scala:63:61] wire _SBCSWrData_T_1 = 1'h0; // @[SBA.scala:63:61] wire _SBCSWrData_T_2 = 1'h0; // @[SBA.scala:63:61] wire _SBCSWrData_T_3 = 1'h0; // @[SBA.scala:63:61] wire _SBCSWrData_T_4 = 1'h0; // @[SBA.scala:63:61] wire _SBCSWrData_T_7 = 1'h0; // @[SBA.scala:63:61] wire _SBCSWrData_T_8 = 1'h0; // @[SBA.scala:63:61] wire _SBCSWrData_T_10 = 1'h0; // @[SBA.scala:63:61] wire _SBCSWrData_T_11 = 1'h0; // @[SBA.scala:63:61] wire _SBCSWrData_T_12 = 1'h0; // @[SBA.scala:63:61] wire SBCSWrData_sbbusy = 1'h0; // @[SBA.scala:63:38] wire SBCSWrData_sbaccess128 = 1'h0; // @[SBA.scala:63:38] wire SBCSWrData_sbaccess64 = 1'h0; // @[SBA.scala:63:38] wire SBCSWrData_sbaccess32 = 1'h0; // @[SBA.scala:63:38] wire SBCSWrData_sbaccess16 = 1'h0; // @[SBA.scala:63:38] wire SBCSWrData_sbaccess8 = 1'h0; // @[SBA.scala:63:38] wire _SBADDRESSRdEn_WIRE_0 = 1'h0; // @[SBA.scala:107:46] wire _SBADDRESSRdEn_WIRE_1 = 1'h0; // @[SBA.scala:107:46] wire _SBADDRESSRdEn_WIRE_2 = 1'h0; // @[SBA.scala:107:46] wire _SBADDRESSRdEn_WIRE_3 = 1'h0; // @[SBA.scala:107:46] wire SBADDRESSRdEn_1 = 1'h0; // @[SBA.scala:107:38] wire SBADDRESSRdEn_2 = 1'h0; // @[SBA.scala:107:38] wire SBADDRESSRdEn_3 = 1'h0; // @[SBA.scala:107:38] wire _SBADDRESSWrEn_WIRE_0 = 1'h0; // @[SBA.scala:108:46] wire _SBADDRESSWrEn_WIRE_1 = 1'h0; // @[SBA.scala:108:46] wire _SBADDRESSWrEn_WIRE_2 = 1'h0; // @[SBA.scala:108:46] wire _SBADDRESSWrEn_WIRE_3 = 1'h0; // @[SBA.scala:108:46] wire SBADDRESSWrEn_1 = 1'h0; // @[SBA.scala:108:38] wire SBADDRESSWrEn_2 = 1'h0; // @[SBA.scala:108:38] wire SBADDRESSWrEn_3 = 1'h0; // @[SBA.scala:108:38] wire _SBDATARdEn_WIRE_0 = 1'h0; // @[SBA.scala:149:43] wire _SBDATARdEn_WIRE_1 = 1'h0; // @[SBA.scala:149:43] wire _SBDATARdEn_WIRE_2 = 1'h0; // @[SBA.scala:149:43] wire _SBDATARdEn_WIRE_3 = 1'h0; // @[SBA.scala:149:43] wire SBDATARdEn_2 = 1'h0; // @[SBA.scala:149:35] wire SBDATARdEn_3 = 1'h0; // @[SBA.scala:149:35] wire _SBDATAWrEn_WIRE_0 = 1'h0; // @[SBA.scala:150:43] wire _SBDATAWrEn_WIRE_1 = 1'h0; // @[SBA.scala:150:43] wire _SBDATAWrEn_WIRE_2 = 1'h0; // @[SBA.scala:150:43] wire _SBDATAWrEn_WIRE_3 = 1'h0; // @[SBA.scala:150:43] wire SBDATAWrEn_2 = 1'h0; // @[SBA.scala:150:35] wire SBDATAWrEn_3 = 1'h0; // @[SBA.scala:150:35] wire _sbAccessError_T_1 = 1'h0; // @[SBA.scala:182:88] wire _sbAccessError_T_2 = 1'h0; // @[SBA.scala:182:58] wire _sbAccessError_T_4 = 1'h0; // @[SBA.scala:183:88] wire _sbAccessError_T_5 = 1'h0; // @[SBA.scala:183:58] wire _sbAccessError_T_6 = 1'h0; // @[SBA.scala:182:97] wire _sbAccessError_T_8 = 1'h0; // @[SBA.scala:184:88] wire _sbAccessError_T_9 = 1'h0; // @[SBA.scala:184:58] wire _sbAccessError_T_10 = 1'h0; // @[SBA.scala:183:97] wire _sbAccessError_T_12 = 1'h0; // @[SBA.scala:185:88] wire _sbAccessError_T_13 = 1'h0; // @[SBA.scala:185:58] wire _sbAccessError_T_14 = 1'h0; // @[SBA.scala:184:97] wire _SBCSRdData_WIRE_1_sbbusyerror = 1'h0; // @[SBA.scala:243:33] wire _SBCSRdData_WIRE_1_sbbusy = 1'h0; // @[SBA.scala:243:33] wire _SBCSRdData_WIRE_1_sbreadonaddr = 1'h0; // @[SBA.scala:243:33] wire _SBCSRdData_WIRE_1_sbautoincrement = 1'h0; // @[SBA.scala:243:33] wire _SBCSRdData_WIRE_1_sbreadondata = 1'h0; // @[SBA.scala:243:33] wire _SBCSRdData_WIRE_1_sbaccess128 = 1'h0; // @[SBA.scala:243:33] wire _SBCSRdData_WIRE_1_sbaccess64 = 1'h0; // @[SBA.scala:243:33] wire _SBCSRdData_WIRE_1_sbaccess32 = 1'h0; // @[SBA.scala:243:33] wire _SBCSRdData_WIRE_1_sbaccess16 = 1'h0; // @[SBA.scala:243:33] wire _SBCSRdData_WIRE_1_sbaccess8 = 1'h0; // @[SBA.scala:243:33] wire _out_rifireMux_T_8 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_12 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_16 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_52 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_56 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_60 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_64 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_68 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_76 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_84 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_88 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_104 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_108 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_112 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_116 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_120 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_124 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_128 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_196 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_200 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_204 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_208 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_212 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_216 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_220 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_224 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_236 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_240 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_252 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_256 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_258 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wifireMux_T_9 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_13 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_17 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_53 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_57 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_61 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_65 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_69 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_77 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_85 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_89 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_105 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_109 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_113 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_117 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_121 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_125 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_129 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_197 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_201 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_205 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_209 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_213 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_217 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_221 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_225 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_237 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_241 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_253 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_257 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_259 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_rofireMux_T_8 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_12 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_16 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_52 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_56 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_60 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_64 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_68 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_76 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_84 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_88 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_104 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_108 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_112 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_116 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_120 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_124 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_128 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_196 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_200 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_204 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_208 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_212 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_216 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_220 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_224 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_236 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_240 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_252 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_256 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_258 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wofireMux_T_9 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_13 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_17 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_53 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_57 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_61 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_65 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_69 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_77 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_85 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_89 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_105 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_109 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_113 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_117 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_121 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_125 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_129 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_197 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_201 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_205 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_209 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_213 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_217 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_221 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_225 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_237 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_241 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_253 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_257 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_259 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T_2 = 1'h0; // @[MuxLiteral.scala:49:17] wire dmiNodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17] wire dmiNodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17] wire dmiNodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17] wire _jalAbstract_WIRE_imm3 = 1'h0; // @[Debug.scala:1497:66] wire _jalAbstract_WIRE_imm1 = 1'h0; // @[Debug.scala:1497:66] wire jalAbstract_imm3 = 1'h0; // @[Debug.scala:1497:32] wire jalAbstract_imm1 = 1'h0; // @[Debug.scala:1497:32] wire _immBits_T = 1'h0; // @[Debug.scala:1575:48] wire _immBits_T_1 = 1'h0; // @[Debug.scala:1575:48] wire _immBits_T_2 = 1'h0; // @[Debug.scala:1575:48] wire _immBits_T_6 = 1'h0; // @[Debug.scala:1575:48] wire _immBits_T_7 = 1'h0; // @[Debug.scala:1575:48] wire _immBits_T_8 = 1'h0; // @[Debug.scala:1575:48] wire _immBits_T_9 = 1'h0; // @[Debug.scala:1575:48] wire _immBits_T_10 = 1'h0; // @[Debug.scala:1575:48] wire _immBits_T_11 = 1'h0; // @[Debug.scala:1575:48] wire _immBits_T_12 = 1'h0; // @[Debug.scala:1575:48] wire _immBits_T_13 = 1'h0; // @[Debug.scala:1575:48] wire _immBits_T_14 = 1'h0; // @[Debug.scala:1575:48] wire _immBits_T_15 = 1'h0; // @[Debug.scala:1575:48] wire _immBits_T_16 = 1'h0; // @[Debug.scala:1575:48] wire _immBits_T_17 = 1'h0; // @[Debug.scala:1575:48] wire _immBits_T_18 = 1'h0; // @[Debug.scala:1575:48] wire _immBits_T_19 = 1'h0; // @[Debug.scala:1575:48] wire _immBits_T_20 = 1'h0; // @[Debug.scala:1575:48] wire _immBits_WIRE_0 = 1'h0; // @[Debug.scala:1575:39] wire _immBits_WIRE_1 = 1'h0; // @[Debug.scala:1575:39] wire _immBits_WIRE_2 = 1'h0; // @[Debug.scala:1575:39] wire _immBits_WIRE_6 = 1'h0; // @[Debug.scala:1575:39] wire _immBits_WIRE_7 = 1'h0; // @[Debug.scala:1575:39] wire _immBits_WIRE_8 = 1'h0; // @[Debug.scala:1575:39] wire _immBits_WIRE_9 = 1'h0; // @[Debug.scala:1575:39] wire _immBits_WIRE_10 = 1'h0; // @[Debug.scala:1575:39] wire _immBits_WIRE_11 = 1'h0; // @[Debug.scala:1575:39] wire _immBits_WIRE_12 = 1'h0; // @[Debug.scala:1575:39] wire _immBits_WIRE_13 = 1'h0; // @[Debug.scala:1575:39] wire _immBits_WIRE_14 = 1'h0; // @[Debug.scala:1575:39] wire _immBits_WIRE_15 = 1'h0; // @[Debug.scala:1575:39] wire _immBits_WIRE_16 = 1'h0; // @[Debug.scala:1575:39] wire _immBits_WIRE_17 = 1'h0; // @[Debug.scala:1575:39] wire _immBits_WIRE_18 = 1'h0; // @[Debug.scala:1575:39] wire _immBits_WIRE_19 = 1'h0; // @[Debug.scala:1575:39] wire _immBits_WIRE_20 = 1'h0; // @[Debug.scala:1575:39] wire immBits_0 = 1'h0; // @[Debug.scala:1575:31] wire immBits_1 = 1'h0; // @[Debug.scala:1575:31] wire immBits_2 = 1'h0; // @[Debug.scala:1575:31] wire immBits_6 = 1'h0; // @[Debug.scala:1575:31] wire immBits_7 = 1'h0; // @[Debug.scala:1575:31] wire immBits_8 = 1'h0; // @[Debug.scala:1575:31] wire immBits_9 = 1'h0; // @[Debug.scala:1575:31] wire immBits_10 = 1'h0; // @[Debug.scala:1575:31] wire immBits_11 = 1'h0; // @[Debug.scala:1575:31] wire immBits_12 = 1'h0; // @[Debug.scala:1575:31] wire immBits_13 = 1'h0; // @[Debug.scala:1575:31] wire immBits_14 = 1'h0; // @[Debug.scala:1575:31] wire immBits_15 = 1'h0; // @[Debug.scala:1575:31] wire immBits_16 = 1'h0; // @[Debug.scala:1575:31] wire immBits_17 = 1'h0; // @[Debug.scala:1575:31] wire immBits_18 = 1'h0; // @[Debug.scala:1575:31] wire immBits_19 = 1'h0; // @[Debug.scala:1575:31] wire immBits_20 = 1'h0; // @[Debug.scala:1575:31] wire _flags_WIRE_resume = 1'h0; // @[Debug.scala:1517:87] wire _flags_WIRE_go = 1'h0; // @[Debug.scala:1517:87] wire _flags_WIRE_1_resume = 1'h0; // @[Debug.scala:1517:87] wire _flags_WIRE_1_go = 1'h0; // @[Debug.scala:1517:87] wire _flags_WIRE_2_0_resume = 1'h0; // @[Debug.scala:1517:33] wire _flags_WIRE_2_0_go = 1'h0; // @[Debug.scala:1517:33] wire _flags_WIRE_2_1_resume = 1'h0; // @[Debug.scala:1517:33] wire _flags_WIRE_2_1_go = 1'h0; // @[Debug.scala:1517:33] wire flags_1_resume = 1'h0; // @[Debug.scala:1517:25] wire flags_1_go = 1'h0; // @[Debug.scala:1517:25] wire componentSel = 1'h0; // @[Debug.scala:1523:34] wire _out_rifireMux_T_307 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_311 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_315 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_319 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_323 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_327 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_331 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_335 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_339 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_343 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_347 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_351 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_355 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_359 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_363 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_367 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_371 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_375 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_379 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_383 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_387 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_399 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_403 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_407 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_411 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_415 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_419 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_423 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_427 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_431 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_435 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_439 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_443 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_447 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_451 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_455 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_459 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_463 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_467 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_471 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_475 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_479 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_483 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_487 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_491 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_495 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_499 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_503 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_507 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_511 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_515 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_519 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_523 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_527 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_531 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_535 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_539 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_543 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_547 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_551 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_555 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_559 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_563 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_567 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_571 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_575 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_579 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_583 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_587 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_591 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_595 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_599 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_603 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_607 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_611 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_615 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_619 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_623 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_627 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_631 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_635 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_639 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_643 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_651 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_655 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_659 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_663 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_667 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_671 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_727 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_731 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_735 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_739 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_743 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_747 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_751 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_755 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_759 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_763 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_767 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_771 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1285 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wifireMux_T_309 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_313 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_317 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_321 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_325 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_329 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_333 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_337 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_341 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_345 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_349 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_353 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_357 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_361 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_365 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_369 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_373 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_377 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_381 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_385 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_389 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_401 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_405 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_409 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_413 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_417 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_421 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_425 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_429 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_433 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_437 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_441 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_445 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_449 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_453 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_457 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_461 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_465 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_469 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_473 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_477 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_481 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_485 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_489 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_493 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_497 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_501 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_505 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_509 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_513 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_517 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_521 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_525 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_529 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_533 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_537 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_541 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_545 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_549 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_553 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_557 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_561 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_565 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_569 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_573 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_577 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_581 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_585 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_589 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_593 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_597 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_601 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_605 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_609 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_613 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_617 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_621 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_625 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_629 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_633 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_637 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_641 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_645 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_653 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_657 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_661 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_665 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_669 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_673 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_729 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_733 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_737 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_741 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_745 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_749 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_753 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_757 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_761 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_765 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_769 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_773 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1287 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_rofireMux_T_307 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_311 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_315 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_319 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_323 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_327 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_331 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_335 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_339 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_343 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_347 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_351 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_355 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_359 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_363 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_367 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_371 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_375 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_379 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_383 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_387 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_399 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_403 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_407 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_411 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_415 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_419 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_423 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_427 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_431 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_435 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_439 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_443 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_447 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_451 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_455 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_459 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_463 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_467 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_471 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_475 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_479 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_483 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_487 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_491 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_495 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_499 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_503 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_507 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_511 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_515 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_519 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_523 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_527 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_531 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_535 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_539 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_543 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_547 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_551 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_555 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_559 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_563 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_567 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_571 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_575 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_579 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_583 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_587 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_591 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_595 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_599 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_603 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_607 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_611 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_615 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_619 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_623 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_627 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_631 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_635 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_639 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_643 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_651 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_655 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_659 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_663 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_667 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_671 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_727 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_731 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_735 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_739 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_743 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_747 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_751 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_755 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_759 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_763 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_767 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_771 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1285 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wofireMux_T_309 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_313 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_317 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_321 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_325 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_329 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_333 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_337 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_341 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_345 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_349 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_353 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_357 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_361 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_365 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_369 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_373 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_377 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_381 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_385 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_389 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_401 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_405 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_409 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_413 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_417 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_421 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_425 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_429 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_433 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_437 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_441 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_445 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_449 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_453 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_457 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_461 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_465 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_469 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_473 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_477 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_481 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_485 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_489 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_493 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_497 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_501 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_505 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_509 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_513 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_517 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_521 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_525 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_529 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_533 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_537 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_541 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_545 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_549 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_553 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_557 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_561 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_565 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_569 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_573 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_577 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_581 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_585 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_589 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_593 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_597 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_601 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_605 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_609 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_613 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_617 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_621 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_625 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_629 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_633 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_637 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_641 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_645 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_653 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_657 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_661 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_665 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_669 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_673 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_729 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_733 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_737 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_741 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_745 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_749 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_753 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_757 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_761 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_765 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_769 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_773 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1287 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T_5 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T_7 = 1'h0; // @[MuxLiteral.scala:49:17] wire tlNodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17] wire tlNodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17] wire tlNodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17] wire [63:0] autoIncrementedAddr_hi = 64'h0; // @[SBA.scala:111:31] wire [63:0] sb2tlOpt_io_addrIn_hi = 64'h0; // @[SBA.scala:132:14] wire [63:0] sb2tlOpt_io_addrIn_hi_1 = 64'h0; // @[SBA.scala:133:10] wire [63:0] sb2tlOpt_io_dataIn_hi = 64'h0; // @[SBA.scala:175:59] wire [63:0] sb2tlOpt_io_dataIn_hi_1 = 64'h0; // @[SBA.scala:175:85] wire [63:0] _out_out_bits_data_WIRE_3_11 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_12 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_13 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_14 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_15 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_16 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_17 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_18 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_19 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_20 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_21 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_22 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_23 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_24 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_25 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_26 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_27 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_28 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_29 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_30 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_31 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_32 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_33 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_34 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_35 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_36 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_37 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_38 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_39 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_40 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_41 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_42 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_43 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_44 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_45 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_46 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_47 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_48 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_49 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_50 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_51 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_52 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_53 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_54 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_55 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_56 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_57 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_58 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_59 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_60 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_61 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_62 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_63 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_64 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_65 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_66 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_67 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_68 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_69 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_70 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_71 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_72 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_73 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_74 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_75 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_76 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_77 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_78 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_79 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_80 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_81 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_82 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_83 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_84 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_85 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_86 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_87 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_88 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_89 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_90 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_91 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_92 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_93 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_94 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_95 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_97 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_98 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_99 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_100 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_101 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_102 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_116 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_117 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_118 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_119 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_120 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_121 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_122 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_123 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_124 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_125 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_126 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_127 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] tlNodeIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17] wire [2:0] auto_sb2tlOpt_out_a_bits_param = 3'h0; // @[Debug.scala:790:9] wire [2:0] _ABSTRACTCSReset_WIRE_reserved0 = 3'h0; // @[Debug.scala:1179:48] wire [2:0] _ABSTRACTCSReset_WIRE_cmderr = 3'h0; // @[Debug.scala:1179:48] wire [2:0] ABSTRACTCSReset_reserved0 = 3'h0; // @[Debug.scala:1179:35] wire [2:0] ABSTRACTCSReset_cmderr = 3'h0; // @[Debug.scala:1179:35] wire [2:0] _ABSTRACTCSWrData_WIRE_reserved0 = 3'h0; // @[Debug.scala:1184:52] wire [2:0] _ABSTRACTCSWrData_WIRE_cmderr = 3'h0; // @[Debug.scala:1184:52] wire [2:0] ABSTRACTCSWrData_reserved0 = 3'h0; // @[Debug.scala:1184:39] wire [2:0] ABSTRACTCSRdData_reserved0 = 3'h0; // @[Debug.scala:1185:39] wire [2:0] _SBCSFieldsRegReset_WIRE_sbversion = 3'h0; // @[SBA.scala:49:51] wire [2:0] _SBCSFieldsRegReset_WIRE_sbaccess = 3'h0; // @[SBA.scala:49:51] wire [2:0] _SBCSFieldsRegReset_WIRE_sberror = 3'h0; // @[SBA.scala:49:51] wire [2:0] SBCSFieldsRegReset_sberror = 3'h0; // @[SBA.scala:49:38] wire [2:0] _SBCSRdData_WIRE_sbversion = 3'h0; // @[SBA.scala:60:51] wire [2:0] _SBCSRdData_WIRE_sbaccess = 3'h0; // @[SBA.scala:60:51] wire [2:0] _SBCSRdData_WIRE_sberror = 3'h0; // @[SBA.scala:60:51] wire [2:0] _SBCSWrData_WIRE_sbversion = 3'h0; // @[SBA.scala:63:61] wire [2:0] _SBCSWrData_WIRE_sbaccess = 3'h0; // @[SBA.scala:63:61] wire [2:0] _SBCSWrData_WIRE_sberror = 3'h0; // @[SBA.scala:63:61] wire [2:0] _SBCSWrData_T_6 = 3'h0; // @[SBA.scala:63:61] wire [2:0] _SBCSWrData_T_9 = 3'h0; // @[SBA.scala:63:61] wire [2:0] _SBCSWrData_T_14 = 3'h0; // @[SBA.scala:63:61] wire [2:0] SBCSWrData_sbversion = 3'h0; // @[SBA.scala:63:38] wire [2:0] _SBCSRdData_WIRE_1_sbversion = 3'h0; // @[SBA.scala:243:33] wire [2:0] _SBCSRdData_WIRE_1_sbaccess = 3'h0; // @[SBA.scala:243:33] wire [2:0] _SBCSRdData_WIRE_1_sberror = 3'h0; // @[SBA.scala:243:33] wire [2:0] dmiNodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17] wire [2:0] jalAbstract_imm0_hi_hi = 3'h0; // @[package.scala:45:27] wire [2:0] jalAbstract_imm1_lo_hi = 3'h0; // @[package.scala:45:27] wire [2:0] jalAbstract_imm1_hi_hi = 3'h0; // @[package.scala:45:27] wire [2:0] nop_funct3 = 3'h0; // @[Debug.scala:1623:19] wire [2:0] _nop_WIRE_funct3 = 3'h0; // @[Debug.scala:1624:46] wire [2:0] isa_funct3 = 3'h0; // @[Debug.scala:1629:19] wire [2:0] _isa_WIRE_funct3 = 3'h0; // @[Debug.scala:1630:47] wire [2:0] tlNodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17] wire auto_sb2tlOpt_out_a_bits_mask = 1'h1; // @[Debug.scala:790:9] wire io_innerCtrl_ready = 1'h1; // @[Debug.scala:790:9] wire hamaskFull_0 = 1'h1; // @[Debug.scala:903:30] wire DMSTATUSRdData_authenticated = 1'h1; // @[Debug.scala:978:34] wire DMSTATUSRdData_hasresethaltreq = 1'h1; // @[Debug.scala:978:34] wire _DMSTATUSRdData_anyhalted_T = 1'h1; // @[package.scala:79:37] wire _DMSTATUSRdData_anyrunning_T = 1'h1; // @[package.scala:79:37] wire _DMSTATUSRdData_allhalted_T = 1'h1; // @[package.scala:79:37] wire _DMSTATUSRdData_allrunning_T = 1'h1; // @[package.scala:79:37] wire SBCSFieldsRegReset_sbaccess64 = 1'h1; // @[SBA.scala:49:38] wire SBCSFieldsRegReset_sbaccess32 = 1'h1; // @[SBA.scala:49:38] wire SBCSFieldsRegReset_sbaccess16 = 1'h1; // @[SBA.scala:49:38] wire SBCSFieldsRegReset_sbaccess8 = 1'h1; // @[SBA.scala:49:38] wire SBCSRdData_sbaccess64 = 1'h1; // @[SBA.scala:60:38] wire SBCSRdData_sbaccess32 = 1'h1; // @[SBA.scala:60:38] wire SBCSRdData_sbaccess16 = 1'h1; // @[SBA.scala:60:38] wire SBCSRdData_sbaccess8 = 1'h1; // @[SBA.scala:60:38] wire _sbAccessError_T_16 = 1'h1; // @[SBA.scala:186:88] wire _out_T_438 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_T_439 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_prepend_T_24 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_4 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_21 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_25 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_29 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_7 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_33 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_8 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_37 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_41 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_45 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_11 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_49 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_12 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_53 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_57 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_61 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_15 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_65 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_16 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_69 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_73 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_77 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_19 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_81 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_20 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_85 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_21 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_89 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_22 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_93 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_23 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_97 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_24 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_101 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_25 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_105 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_26 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_109 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_27 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_113 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_28 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_117 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_29 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_121 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_30 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_125 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_31 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_129 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_32 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_133 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_33 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_137 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_34 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_141 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_35 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_145 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_36 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_149 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_37 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_153 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_38 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_157 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_39 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_161 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_40 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_165 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_41 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_169 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_42 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_173 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_43 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_177 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_44 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_181 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_45 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_185 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_46 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_189 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_47 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_193 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_48 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_197 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_49 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_201 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_50 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_205 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_51 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_209 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_52 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_213 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_53 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_217 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_54 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_221 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_55 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_225 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_56 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_229 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_57 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_233 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_58 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_237 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_59 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_241 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_60 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_245 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_61 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_249 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_62 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_253 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_63 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_257 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_4 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_5 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_6 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_7 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_8 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_9 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_10 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_11 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_12 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_13 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_14 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_15 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_16 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_17 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_18 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_19 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_20 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_21 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_22 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_23 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_24 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_25 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_26 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_27 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_28 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_29 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_30 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_31 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_32 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_33 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_34 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_35 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_36 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_37 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_38 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_39 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_40 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_41 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_42 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_43 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_44 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_45 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_46 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_47 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_48 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_49 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_50 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_51 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_52 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_53 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_54 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_55 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_56 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_57 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_58 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_59 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_60 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_61 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_62 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_63 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_4 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_22 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_26 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_30 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_7 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_34 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_8 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_38 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_42 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_46 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_11 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_50 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_12 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_54 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_58 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_62 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_15 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_66 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_16 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_70 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_74 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_78 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_19 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_82 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_20 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_86 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_21 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_90 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_22 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_94 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_23 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_98 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_24 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_102 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_25 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_106 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_26 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_110 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_27 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_114 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_28 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_118 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_29 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_122 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_30 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_126 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_31 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_130 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_32 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_134 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_33 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_138 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_34 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_142 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_35 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_146 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_36 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_150 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_37 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_154 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_38 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_158 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_39 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_162 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_40 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_166 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_41 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_170 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_42 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_174 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_43 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_178 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_44 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_182 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_45 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_186 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_46 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_190 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_47 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_194 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_48 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_198 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_49 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_202 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_50 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_206 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_51 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_210 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_52 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_214 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_53 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_218 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_54 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_222 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_55 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_226 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_56 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_230 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_57 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_234 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_58 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_238 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_59 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_242 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_60 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_246 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_61 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_250 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_62 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_254 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_63 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_258 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_4 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_5 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_6 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_7 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_8 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_9 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_10 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_11 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_12 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_13 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_14 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_15 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_16 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_17 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_18 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_19 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_20 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_21 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_22 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_23 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_24 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_25 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_26 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_27 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_28 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_29 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_30 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_31 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_32 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_33 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_34 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_35 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_36 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_37 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_38 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_39 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_40 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_41 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_42 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_43 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_44 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_45 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_46 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_47 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_48 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_49 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_50 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_51 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_52 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_53 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_54 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_55 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_56 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_57 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_58 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_59 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_60 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_61 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_62 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_63 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_4 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_21 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_25 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_29 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_7 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_33 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_8 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_37 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_41 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_45 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_11 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_49 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_12 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_53 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_57 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_61 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_15 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_65 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_16 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_69 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_73 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_77 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_19 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_81 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_20 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_85 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_21 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_89 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_22 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_93 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_23 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_97 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_24 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_101 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_25 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_105 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_26 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_109 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_27 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_113 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_28 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_117 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_29 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_121 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_30 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_125 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_31 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_129 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_32 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_133 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_33 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_137 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_34 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_141 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_35 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_145 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_36 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_149 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_37 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_153 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_38 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_157 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_39 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_161 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_40 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_165 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_41 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_169 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_42 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_173 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_43 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_177 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_44 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_181 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_45 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_185 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_46 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_189 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_47 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_193 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_48 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_197 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_49 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_201 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_50 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_205 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_51 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_209 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_52 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_213 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_53 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_217 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_54 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_221 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_55 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_225 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_56 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_229 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_57 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_233 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_58 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_237 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_59 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_241 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_60 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_245 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_61 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_249 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_62 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_253 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_63 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_257 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_4 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_5 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_6 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_7 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_8 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_9 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_10 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_11 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_12 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_13 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_14 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_15 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_16 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_17 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_18 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_19 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_20 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_21 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_22 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_23 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_24 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_25 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_26 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_27 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_28 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_29 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_30 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_31 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_32 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_33 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_34 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_35 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_36 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_37 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_38 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_39 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_40 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_41 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_42 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_43 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_44 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_45 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_46 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_47 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_48 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_49 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_50 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_51 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_52 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_53 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_54 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_55 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_56 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_57 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_58 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_59 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_60 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_61 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_62 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_63 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_4 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_22 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_26 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_30 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_7 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_34 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_8 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_38 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_42 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_46 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_11 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_50 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_12 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_54 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_58 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_62 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_15 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_66 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_16 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_70 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_74 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_78 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_19 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_82 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_20 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_86 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_21 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_90 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_22 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_94 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_23 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_98 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_24 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_102 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_25 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_106 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_26 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_110 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_27 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_114 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_28 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_118 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_29 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_122 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_30 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_126 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_31 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_130 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_32 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_134 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_33 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_138 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_34 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_142 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_35 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_146 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_36 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_150 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_37 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_154 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_38 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_158 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_39 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_162 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_40 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_166 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_41 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_170 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_42 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_174 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_43 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_178 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_44 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_182 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_45 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_186 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_46 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_190 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_47 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_194 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_48 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_198 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_49 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_202 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_50 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_206 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_51 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_210 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_52 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_214 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_53 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_218 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_54 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_222 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_55 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_226 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_56 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_230 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_57 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_234 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_58 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_238 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_59 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_242 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_60 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_246 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_61 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_250 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_62 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_254 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_63 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_258 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_4 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_5 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_6 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_7 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_8 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_9 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_10 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_11 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_12 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_13 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_14 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_15 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_16 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_17 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_18 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_19 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_20 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_21 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_22 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_23 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_24 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_25 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_26 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_27 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_28 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_29 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_30 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_31 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_32 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_33 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_34 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_35 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_36 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_37 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_38 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_39 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_40 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_41 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_42 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_43 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_44 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_45 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_46 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_47 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_48 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_49 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_50 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_51 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_52 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_53 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_54 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_55 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_56 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_57 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_58 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_59 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_60 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_61 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_62 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_63 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_iready = 1'h1; // @[RegisterRouter.scala:87:24] wire out_oready = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_12 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_13 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_14 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_15 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_16 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_18 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_20 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_21 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_25 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_26 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_27 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_28 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_29 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_30 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_31 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_48 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_49 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_50 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_51 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_52 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_53 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_54 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_55 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_58 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_59 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_62 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_63 = 1'h1; // @[MuxLiteral.scala:49:48] wire _immBits_T_3 = 1'h1; // @[Debug.scala:1575:48] wire _immBits_T_4 = 1'h1; // @[Debug.scala:1575:48] wire _immBits_T_5 = 1'h1; // @[Debug.scala:1575:48] wire _immBits_WIRE_3 = 1'h1; // @[Debug.scala:1575:39] wire _immBits_WIRE_4 = 1'h1; // @[Debug.scala:1575:39] wire _immBits_WIRE_5 = 1'h1; // @[Debug.scala:1575:39] wire immBits_3 = 1'h1; // @[Debug.scala:1575:31] wire immBits_4 = 1'h1; // @[Debug.scala:1575:31] wire immBits_5 = 1'h1; // @[Debug.scala:1575:31] wire out_rifireMux_out_64 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_264 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_65 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_268 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_66 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_272 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_67 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_276 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_68 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_280 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_69 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_284 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_70 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_288 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_71 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_292 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_72 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_296 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_73 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_300 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_74 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_304 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_75 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_308 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_76 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_312 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_77 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_316 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_78 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_320 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_79 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_324 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_80 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_328 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_81 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_332 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_82 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_336 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_83 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_340 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_84 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_344 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_85 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_348 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_86 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_352 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_87 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_356 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_88 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_360 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_89 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_364 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_90 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_368 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_91 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_372 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_92 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_376 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_93 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_380 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_94 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_384 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_95 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_388 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_96 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_392 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_97 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_396 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_98 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_400 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_99 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_404 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_100 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_408 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_101 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_412 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_102 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_416 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_103 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_420 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_104 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_424 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_105 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_428 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_106 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_432 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_107 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_436 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_108 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_440 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_109 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_444 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_110 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_448 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_111 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_452 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_112 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_456 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_113 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_460 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_114 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_464 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_115 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_468 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_116 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_472 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_117 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_476 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_118 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_480 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_119 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_484 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_120 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_488 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_121 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_492 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_122 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_496 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_123 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_500 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_124 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_504 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_125 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_508 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_126 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_512 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_127 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_516 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_128 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_520 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_129 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_524 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_130 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_528 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_131 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_532 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_132 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_536 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_133 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_540 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_134 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_544 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_135 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_548 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_136 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_552 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_137 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_556 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_138 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_560 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_139 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_564 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_140 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_568 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_141 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_572 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_142 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_576 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_143 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_580 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_144 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_584 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_145 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_588 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_146 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_592 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_147 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_596 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_148 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_600 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_149 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_604 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_150 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_608 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_151 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_612 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_152 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_616 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_153 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_620 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_154 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_624 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_155 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_628 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_156 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_632 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_157 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_636 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_158 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_640 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_159 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_644 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_160 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_648 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_161 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_652 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_162 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_656 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_163 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_660 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_164 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_664 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_165 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_668 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_166 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_672 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_167 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_676 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_168 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_680 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_169 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_684 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_170 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_688 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_171 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_692 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_172 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_696 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_173 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_700 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_174 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_704 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_175 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_708 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_176 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_712 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_177 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_716 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_178 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_720 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_179 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_724 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_180 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_728 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_181 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_732 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_182 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_736 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_183 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_740 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_184 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_744 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_185 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_748 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_186 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_752 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_187 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_756 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_188 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_760 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_189 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_764 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_190 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_768 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_191 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_772 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_192 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_776 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_193 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_780 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_194 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_784 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_195 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_788 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_196 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_792 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_197 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_796 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_198 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_800 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_199 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_804 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_200 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_808 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_201 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_812 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_202 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_816 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_203 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_820 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_204 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_824 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_205 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_828 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_206 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_832 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_207 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_836 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_208 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_840 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_209 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_844 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_210 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_848 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_211 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_852 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_212 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_856 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_213 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_860 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_214 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_864 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_215 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_868 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_216 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_872 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_217 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_876 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_218 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_880 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_219 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_884 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_220 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_888 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_221 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_892 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_222 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_896 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_223 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_900 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_224 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_904 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_225 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_908 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_226 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_912 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_227 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_916 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_228 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_920 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_229 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_924 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_230 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_928 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_231 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_932 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_232 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_936 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_233 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_940 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_234 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_944 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_235 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_948 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_236 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_952 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_237 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_956 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_238 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_960 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_239 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_964 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_240 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_968 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_241 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_972 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_242 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_976 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_243 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_980 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_244 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_984 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_245 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_988 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_246 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_992 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_247 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_996 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_248 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1000 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_249 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1004 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_250 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1008 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_251 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1012 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_252 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1016 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_253 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1020 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_254 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1024 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_255 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1028 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_256 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1032 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_257 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1036 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_258 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1040 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_259 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1044 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_260 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1048 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_261 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1052 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_262 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1056 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_263 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1060 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_264 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1064 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_265 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1068 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_266 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1072 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_267 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1076 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_268 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1080 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_269 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1084 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_270 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1088 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_271 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1092 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_272 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1096 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_273 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1100 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_274 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1104 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_275 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1108 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_276 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1112 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_277 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1116 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_278 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1120 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_279 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1124 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_280 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1128 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_281 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1132 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_282 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1136 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_283 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1140 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_284 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1144 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_285 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1148 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_286 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1152 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_287 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1156 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_288 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1160 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_289 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1164 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_290 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1168 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_291 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1172 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_292 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1176 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_293 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1180 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_294 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1184 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_295 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1188 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_296 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1192 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_297 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1196 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_298 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1200 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_299 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1204 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_300 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1208 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_301 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1212 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_302 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1216 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_303 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1220 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_304 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1224 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_305 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1228 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_306 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1232 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_307 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1236 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_308 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1240 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_309 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1244 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_310 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1248 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_311 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1252 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_312 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1256 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_313 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1260 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_314 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1264 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_315 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1268 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_316 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1272 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_317 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1276 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_318 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1280 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_319 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1284 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_WIRE_1_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_4 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_5 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_6 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_7 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_8 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_9 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_10 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_11 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_12 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_13 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_14 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_15 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_16 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_17 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_18 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_19 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_20 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_21 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_22 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_23 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_24 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_25 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_26 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_27 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_28 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_29 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_30 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_31 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_32 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_33 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_34 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_35 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_36 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_37 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_38 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_39 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_40 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_41 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_42 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_43 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_44 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_45 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_46 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_47 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_48 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_49 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_50 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_51 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_52 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_53 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_54 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_55 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_56 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_57 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_58 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_59 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_60 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_61 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_62 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_63 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_64 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_65 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_66 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_67 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_68 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_69 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_70 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_71 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_72 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_73 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_74 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_75 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_76 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_77 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_78 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_79 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_80 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_81 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_82 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_83 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_84 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_85 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_86 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_87 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_88 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_89 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_90 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_91 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_92 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_93 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_94 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_95 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_96 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_97 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_98 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_99 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_100 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_101 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_102 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_103 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_104 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_105 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_106 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_107 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_108 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_109 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_110 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_111 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_112 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_113 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_114 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_115 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_116 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_117 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_118 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_119 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_120 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_121 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_122 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_123 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_124 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_125 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_126 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_127 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_128 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_129 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_130 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_131 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_132 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_133 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_134 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_135 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_136 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_137 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_138 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_139 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_140 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_141 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_142 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_143 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_144 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_145 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_146 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_147 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_148 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_149 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_150 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_151 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_152 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_153 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_154 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_155 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_156 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_157 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_158 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_159 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_160 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_161 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_162 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_163 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_164 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_165 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_166 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_167 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_168 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_169 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_170 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_171 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_172 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_173 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_174 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_175 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_176 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_177 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_178 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_179 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_180 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_181 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_182 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_183 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_184 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_185 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_186 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_187 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_188 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_189 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_190 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_191 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_192 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_193 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_194 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_195 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_196 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_197 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_198 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_199 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_200 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_201 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_202 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_203 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_204 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_205 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_206 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_207 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_208 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_209 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_210 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_211 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_212 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_213 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_214 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_215 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_216 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_217 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_218 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_219 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_220 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_221 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_222 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_223 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_224 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_225 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_226 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_227 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_228 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_229 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_230 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_231 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_232 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_233 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_234 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_235 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_236 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_237 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_238 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_239 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_240 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_241 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_242 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_243 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_244 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_245 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_246 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_247 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_248 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_249 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_250 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_251 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_252 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_253 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_254 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_255 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rifireMux_1 = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wifireMux_out_64 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_266 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_65 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_270 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_66 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_274 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_67 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_278 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_68 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_282 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_69 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_286 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_70 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_290 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_71 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_294 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_72 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_298 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_73 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_302 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_74 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_306 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_75 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_310 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_76 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_314 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_77 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_318 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_78 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_322 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_79 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_326 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_80 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_330 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_81 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_334 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_82 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_338 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_83 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_342 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_84 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_346 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_85 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_350 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_86 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_354 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_87 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_358 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_88 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_362 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_89 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_366 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_90 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_370 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_91 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_374 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_92 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_378 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_93 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_382 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_94 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_386 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_95 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_390 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_96 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_394 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_97 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_398 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_98 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_402 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_99 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_406 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_100 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_410 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_101 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_414 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_102 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_418 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_103 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_422 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_104 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_426 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_105 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_430 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_106 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_434 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_107 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_438 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_108 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_442 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_109 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_446 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_110 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_450 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_111 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_454 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_112 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_458 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_113 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_462 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_114 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_466 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_115 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_470 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_116 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_474 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_117 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_478 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_118 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_482 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_119 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_486 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_120 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_490 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_121 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_494 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_122 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_498 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_123 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_502 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_124 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_506 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_125 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_510 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_126 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_514 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_127 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_518 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_128 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_522 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_129 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_526 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_130 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_530 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_131 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_534 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_132 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_538 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_133 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_542 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_134 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_546 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_135 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_550 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_136 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_554 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_137 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_558 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_138 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_562 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_139 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_566 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_140 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_570 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_141 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_574 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_142 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_578 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_143 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_582 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_144 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_586 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_145 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_590 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_146 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_594 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_147 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_598 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_148 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_602 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_149 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_606 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_150 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_610 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_151 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_614 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_152 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_618 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_153 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_622 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_154 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_626 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_155 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_630 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_156 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_634 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_157 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_638 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_158 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_642 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_159 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_646 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_160 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_650 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_161 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_654 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_162 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_658 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_163 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_662 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_164 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_666 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_165 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_670 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_166 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_674 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_167 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_678 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_168 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_682 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_169 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_686 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_170 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_690 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_171 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_694 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_172 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_698 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_173 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_702 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_174 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_706 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_175 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_710 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_176 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_714 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_177 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_718 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_178 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_722 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_179 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_726 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_180 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_730 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_181 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_734 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_182 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_738 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_183 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_742 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_184 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_746 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_185 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_750 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_186 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_754 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_187 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_758 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_188 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_762 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_189 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_766 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_190 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_770 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_191 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_774 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_192 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_778 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_193 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_782 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_194 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_786 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_195 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_790 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_196 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_794 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_197 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_798 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_198 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_802 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_199 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_806 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_200 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_810 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_201 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_814 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_202 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_818 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_203 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_822 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_204 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_826 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_205 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_830 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_206 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_834 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_207 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_838 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_208 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_842 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_209 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_846 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_210 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_850 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_211 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_854 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_212 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_858 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_213 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_862 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_214 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_866 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_215 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_870 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_216 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_874 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_217 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_878 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_218 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_882 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_219 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_886 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_220 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_890 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_221 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_894 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_222 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_898 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_223 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_902 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_224 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_906 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_225 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_910 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_226 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_914 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_227 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_918 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_228 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_922 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_229 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_926 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_230 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_930 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_231 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_934 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_232 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_938 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_233 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_942 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_234 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_946 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_235 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_950 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_236 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_954 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_237 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_958 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_238 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_962 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_239 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_966 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_240 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_970 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_241 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_974 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_242 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_978 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_243 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_982 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_244 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_986 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_245 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_990 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_246 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_994 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_247 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_998 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_248 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1002 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_249 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1006 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_250 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1010 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_251 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1014 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_252 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1018 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_253 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1022 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_254 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1026 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_255 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1030 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_256 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1034 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_257 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1038 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_258 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1042 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_259 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1046 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_260 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1050 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_261 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1054 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_262 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1058 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_263 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1062 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_264 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1066 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_265 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1070 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_266 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1074 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_267 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1078 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_268 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1082 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_269 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1086 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_270 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1090 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_271 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1094 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_272 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1098 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_273 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1102 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_274 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1106 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_275 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1110 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_276 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1114 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_277 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1118 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_278 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1122 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_279 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1126 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_280 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1130 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_281 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1134 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_282 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1138 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_283 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1142 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_284 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1146 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_285 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1150 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_286 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1154 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_287 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1158 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_288 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1162 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_289 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1166 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_290 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1170 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_291 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1174 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_292 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1178 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_293 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1182 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_294 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1186 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_295 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1190 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_296 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1194 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_297 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1198 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_298 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1202 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_299 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1206 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_300 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1210 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_301 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1214 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_302 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1218 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_303 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1222 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_304 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1226 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_305 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1230 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_306 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1234 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_307 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1238 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_308 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1242 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_309 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1246 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_310 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1250 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_311 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1254 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_312 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1258 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_313 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1262 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_314 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1266 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_315 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1270 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_316 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1274 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_317 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1278 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_318 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1282 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_319 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1286 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_WIRE_1_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_4 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_5 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_6 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_7 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_8 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_9 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_10 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_11 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_12 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_13 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_14 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_15 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_16 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_17 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_18 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_19 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_20 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_21 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_22 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_23 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_24 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_25 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_26 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_27 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_28 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_29 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_30 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_31 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_32 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_33 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_34 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_35 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_36 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_37 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_38 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_39 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_40 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_41 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_42 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_43 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_44 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_45 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_46 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_47 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_48 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_49 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_50 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_51 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_52 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_53 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_54 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_55 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_56 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_57 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_58 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_59 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_60 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_61 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_62 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_63 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_64 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_65 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_66 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_67 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_68 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_69 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_70 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_71 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_72 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_73 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_74 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_75 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_76 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_77 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_78 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_79 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_80 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_81 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_82 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_83 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_84 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_85 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_86 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_87 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_88 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_89 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_90 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_91 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_92 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_93 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_94 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_95 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_96 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_97 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_98 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_99 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_100 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_101 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_102 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_103 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_104 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_105 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_106 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_107 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_108 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_109 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_110 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_111 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_112 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_113 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_114 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_115 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_116 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_117 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_118 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_119 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_120 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_121 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_122 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_123 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_124 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_125 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_126 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_127 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_128 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_129 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_130 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_131 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_132 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_133 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_134 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_135 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_136 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_137 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_138 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_139 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_140 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_141 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_142 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_143 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_144 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_145 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_146 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_147 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_148 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_149 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_150 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_151 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_152 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_153 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_154 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_155 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_156 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_157 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_158 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_159 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_160 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_161 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_162 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_163 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_164 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_165 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_166 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_167 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_168 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_169 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_170 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_171 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_172 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_173 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_174 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_175 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_176 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_177 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_178 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_179 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_180 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_181 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_182 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_183 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_184 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_185 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_186 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_187 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_188 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_189 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_190 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_191 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_192 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_193 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_194 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_195 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_196 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_197 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_198 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_199 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_200 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_201 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_202 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_203 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_204 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_205 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_206 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_207 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_208 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_209 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_210 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_211 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_212 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_213 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_214 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_215 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_216 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_217 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_218 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_219 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_220 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_221 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_222 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_223 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_224 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_225 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_226 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_227 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_228 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_229 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_230 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_231 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_232 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_233 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_234 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_235 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_236 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_237 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_238 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_239 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_240 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_241 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_242 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_243 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_244 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_245 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_246 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_247 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_248 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_249 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_250 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_251 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_252 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_253 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_254 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_255 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wifireMux_1 = 1'h1; // @[MuxLiteral.scala:49:10] wire out_rofireMux_out_64 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_264 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_65 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_268 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_66 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_272 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_67 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_276 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_68 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_280 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_69 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_284 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_70 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_288 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_71 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_292 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_72 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_296 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_73 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_300 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_74 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_304 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_75 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_308 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_76 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_312 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_77 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_316 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_78 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_320 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_79 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_324 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_80 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_328 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_81 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_332 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_82 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_336 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_83 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_340 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_84 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_344 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_85 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_348 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_86 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_352 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_87 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_356 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_88 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_360 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_89 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_364 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_90 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_368 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_91 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_372 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_92 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_376 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_93 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_380 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_94 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_384 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_95 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_388 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_96 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_392 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_97 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_396 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_98 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_400 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_99 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_404 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_100 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_408 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_101 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_412 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_102 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_416 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_103 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_420 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_104 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_424 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_105 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_428 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_106 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_432 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_107 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_436 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_108 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_440 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_109 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_444 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_110 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_448 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_111 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_452 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_112 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_456 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_113 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_460 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_114 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_464 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_115 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_468 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_116 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_472 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_117 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_476 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_118 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_480 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_119 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_484 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_120 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_488 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_121 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_492 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_122 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_496 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_123 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_500 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_124 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_504 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_125 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_508 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_126 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_512 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_127 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_516 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_128 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_520 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_129 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_524 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_130 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_528 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_131 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_532 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_132 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_536 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_133 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_540 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_134 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_544 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_135 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_548 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_136 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_552 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_137 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_556 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_138 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_560 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_139 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_564 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_140 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_568 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_141 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_572 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_142 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_576 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_143 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_580 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_144 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_584 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_145 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_588 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_146 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_592 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_147 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_596 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_148 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_600 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_149 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_604 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_150 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_608 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_151 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_612 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_152 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_616 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_153 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_620 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_154 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_624 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_155 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_628 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_156 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_632 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_157 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_636 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_158 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_640 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_159 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_644 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_160 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_648 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_161 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_652 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_162 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_656 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_163 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_660 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_164 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_664 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_165 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_668 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_166 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_672 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_167 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_676 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_168 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_680 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_169 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_684 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_170 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_688 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_171 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_692 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_172 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_696 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_173 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_700 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_174 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_704 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_175 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_708 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_176 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_712 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_177 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_716 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_178 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_720 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_179 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_724 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_180 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_728 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_181 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_732 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_182 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_736 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_183 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_740 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_184 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_744 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_185 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_748 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_186 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_752 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_187 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_756 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_188 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_760 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_189 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_764 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_190 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_768 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_191 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_772 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_192 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_776 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_193 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_780 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_194 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_784 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_195 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_788 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_196 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_792 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_197 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_796 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_198 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_800 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_199 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_804 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_200 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_808 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_201 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_812 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_202 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_816 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_203 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_820 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_204 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_824 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_205 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_828 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_206 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_832 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_207 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_836 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_208 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_840 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_209 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_844 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_210 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_848 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_211 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_852 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_212 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_856 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_213 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_860 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_214 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_864 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_215 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_868 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_216 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_872 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_217 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_876 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_218 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_880 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_219 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_884 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_220 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_888 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_221 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_892 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_222 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_896 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_223 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_900 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_224 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_904 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_225 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_908 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_226 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_912 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_227 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_916 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_228 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_920 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_229 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_924 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_230 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_928 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_231 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_932 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_232 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_936 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_233 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_940 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_234 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_944 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_235 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_948 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_236 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_952 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_237 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_956 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_238 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_960 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_239 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_964 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_240 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_968 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_241 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_972 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_242 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_976 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_243 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_980 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_244 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_984 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_245 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_988 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_246 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_992 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_247 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_996 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_248 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1000 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_249 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1004 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_250 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1008 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_251 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1012 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_252 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1016 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_253 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1020 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_254 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1024 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_255 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1028 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_256 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1032 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_257 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1036 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_258 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1040 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_259 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1044 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_260 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1048 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_261 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1052 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_262 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1056 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_263 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1060 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_264 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1064 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_265 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1068 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_266 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1072 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_267 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1076 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_268 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1080 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_269 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1084 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_270 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1088 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_271 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1092 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_272 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1096 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_273 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1100 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_274 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1104 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_275 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1108 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_276 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1112 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_277 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1116 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_278 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1120 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_279 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1124 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_280 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1128 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_281 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1132 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_282 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1136 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_283 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1140 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_284 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1144 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_285 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1148 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_286 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1152 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_287 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1156 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_288 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1160 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_289 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1164 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_290 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1168 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_291 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1172 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_292 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1176 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_293 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1180 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_294 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1184 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_295 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1188 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_296 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1192 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_297 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1196 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_298 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1200 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_299 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1204 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_300 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1208 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_301 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1212 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_302 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1216 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_303 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1220 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_304 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1224 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_305 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1228 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_306 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1232 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_307 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1236 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_308 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1240 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_309 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1244 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_310 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1248 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_311 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1252 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_312 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1256 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_313 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1260 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_314 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1264 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_315 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1268 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_316 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1272 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_317 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1276 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_318 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1280 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_319 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1284 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_WIRE_1_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_4 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_5 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_6 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_7 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_8 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_9 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_10 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_11 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_12 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_13 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_14 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_15 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_16 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_17 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_18 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_19 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_20 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_21 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_22 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_23 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_24 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_25 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_26 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_27 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_28 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_29 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_30 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_31 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_32 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_33 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_34 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_35 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_36 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_37 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_38 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_39 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_40 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_41 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_42 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_43 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_44 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_45 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_46 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_47 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_48 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_49 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_50 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_51 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_52 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_53 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_54 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_55 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_56 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_57 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_58 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_59 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_60 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_61 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_62 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_63 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_64 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_65 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_66 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_67 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_68 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_69 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_70 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_71 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_72 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_73 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_74 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_75 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_76 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_77 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_78 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_79 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_80 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_81 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_82 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_83 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_84 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_85 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_86 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_87 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_88 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_89 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_90 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_91 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_92 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_93 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_94 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_95 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_96 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_97 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_98 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_99 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_100 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_101 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_102 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_103 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_104 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_105 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_106 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_107 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_108 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_109 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_110 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_111 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_112 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_113 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_114 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_115 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_116 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_117 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_118 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_119 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_120 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_121 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_122 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_123 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_124 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_125 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_126 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_127 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_128 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_129 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_130 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_131 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_132 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_133 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_134 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_135 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_136 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_137 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_138 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_139 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_140 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_141 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_142 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_143 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_144 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_145 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_146 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_147 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_148 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_149 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_150 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_151 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_152 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_153 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_154 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_155 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_156 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_157 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_158 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_159 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_160 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_161 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_162 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_163 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_164 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_165 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_166 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_167 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_168 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_169 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_170 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_171 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_172 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_173 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_174 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_175 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_176 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_177 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_178 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_179 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_180 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_181 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_182 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_183 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_184 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_185 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_186 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_187 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_188 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_189 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_190 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_191 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_192 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_193 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_194 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_195 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_196 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_197 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_198 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_199 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_200 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_201 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_202 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_203 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_204 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_205 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_206 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_207 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_208 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_209 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_210 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_211 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_212 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_213 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_214 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_215 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_216 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_217 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_218 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_219 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_220 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_221 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_222 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_223 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_224 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_225 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_226 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_227 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_228 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_229 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_230 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_231 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_232 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_233 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_234 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_235 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_236 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_237 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_238 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_239 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_240 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_241 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_242 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_243 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_244 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_245 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_246 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_247 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_248 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_249 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_250 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_251 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_252 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_253 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_254 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_255 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rofireMux_1 = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wofireMux_out_64 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_266 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_65 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_270 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_66 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_274 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_67 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_278 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_68 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_282 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_69 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_286 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_70 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_290 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_71 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_294 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_72 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_298 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_73 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_302 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_74 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_306 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_75 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_310 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_76 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_314 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_77 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_318 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_78 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_322 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_79 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_326 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_80 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_330 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_81 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_334 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_82 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_338 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_83 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_342 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_84 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_346 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_85 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_350 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_86 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_354 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_87 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_358 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_88 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_362 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_89 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_366 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_90 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_370 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_91 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_374 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_92 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_378 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_93 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_382 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_94 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_386 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_95 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_390 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_96 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_394 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_97 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_398 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_98 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_402 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_99 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_406 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_100 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_410 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_101 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_414 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_102 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_418 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_103 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_422 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_104 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_426 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_105 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_430 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_106 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_434 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_107 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_438 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_108 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_442 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_109 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_446 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_110 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_450 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_111 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_454 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_112 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_458 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_113 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_462 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_114 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_466 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_115 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_470 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_116 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_474 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_117 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_478 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_118 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_482 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_119 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_486 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_120 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_490 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_121 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_494 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_122 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_498 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_123 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_502 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_124 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_506 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_125 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_510 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_126 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_514 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_127 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_518 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_128 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_522 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_129 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_526 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_130 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_530 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_131 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_534 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_132 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_538 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_133 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_542 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_134 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_546 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_135 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_550 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_136 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_554 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_137 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_558 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_138 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_562 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_139 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_566 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_140 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_570 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_141 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_574 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_142 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_578 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_143 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_582 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_144 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_586 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_145 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_590 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_146 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_594 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_147 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_598 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_148 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_602 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_149 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_606 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_150 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_610 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_151 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_614 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_152 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_618 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_153 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_622 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_154 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_626 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_155 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_630 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_156 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_634 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_157 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_638 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_158 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_642 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_159 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_646 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_160 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_650 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_161 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_654 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_162 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_658 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_163 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_662 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_164 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_666 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_165 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_670 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_166 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_674 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_167 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_678 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_168 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_682 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_169 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_686 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_170 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_690 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_171 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_694 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_172 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_698 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_173 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_702 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_174 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_706 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_175 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_710 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_176 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_714 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_177 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_718 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_178 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_722 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_179 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_726 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_180 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_730 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_181 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_734 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_182 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_738 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_183 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_742 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_184 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_746 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_185 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_750 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_186 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_754 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_187 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_758 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_188 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_762 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_189 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_766 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_190 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_770 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_191 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_774 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_192 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_778 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_193 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_782 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_194 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_786 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_195 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_790 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_196 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_794 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_197 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_798 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_198 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_802 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_199 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_806 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_200 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_810 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_201 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_814 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_202 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_818 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_203 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_822 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_204 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_826 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_205 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_830 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_206 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_834 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_207 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_838 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_208 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_842 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_209 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_846 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_210 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_850 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_211 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_854 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_212 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_858 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_213 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_862 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_214 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_866 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_215 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_870 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_216 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_874 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_217 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_878 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_218 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_882 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_219 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_886 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_220 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_890 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_221 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_894 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_222 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_898 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_223 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_902 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_224 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_906 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_225 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_910 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_226 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_914 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_227 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_918 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_228 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_922 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_229 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_926 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_230 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_930 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_231 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_934 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_232 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_938 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_233 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_942 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_234 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_946 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_235 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_950 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_236 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_954 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_237 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_958 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_238 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_962 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_239 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_966 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_240 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_970 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_241 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_974 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_242 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_978 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_243 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_982 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_244 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_986 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_245 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_990 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_246 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_994 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_247 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_998 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_248 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1002 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_249 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1006 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_250 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1010 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_251 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1014 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_252 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1018 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_253 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1022 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_254 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1026 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_255 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1030 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_256 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1034 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_257 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1038 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_258 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1042 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_259 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1046 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_260 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1050 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_261 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1054 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_262 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1058 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_263 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1062 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_264 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1066 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_265 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1070 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_266 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1074 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_267 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1078 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_268 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1082 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_269 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1086 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_270 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1090 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_271 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1094 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_272 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1098 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_273 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1102 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_274 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1106 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_275 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1110 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_276 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1114 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_277 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1118 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_278 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1122 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_279 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1126 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_280 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1130 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_281 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1134 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_282 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1138 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_283 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1142 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_284 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1146 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_285 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1150 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_286 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1154 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_287 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1158 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_288 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1162 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_289 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1166 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_290 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1170 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_291 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1174 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_292 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1178 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_293 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1182 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_294 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1186 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_295 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1190 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_296 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1194 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_297 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1198 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_298 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1202 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_299 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1206 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_300 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1210 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_301 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1214 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_302 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1218 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_303 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1222 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_304 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1226 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_305 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1230 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_306 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1234 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_307 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1238 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_308 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1242 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_309 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1246 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_310 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1250 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_311 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1254 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_312 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1258 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_313 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1262 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_314 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1266 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_315 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1270 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_316 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1274 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_317 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1278 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_318 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1282 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_319 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1286 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_1_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_4 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_5 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_6 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_7 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_8 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_9 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_10 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_11 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_12 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_13 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_14 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_15 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_16 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_17 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_18 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_19 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_20 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_21 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_22 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_23 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_24 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_25 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_26 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_27 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_28 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_29 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_30 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_31 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_32 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_33 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_34 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_35 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_36 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_37 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_38 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_39 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_40 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_41 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_42 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_43 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_44 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_45 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_46 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_47 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_48 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_49 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_50 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_51 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_52 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_53 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_54 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_55 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_56 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_57 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_58 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_59 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_60 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_61 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_62 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_63 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_64 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_65 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_66 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_67 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_68 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_69 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_70 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_71 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_72 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_73 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_74 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_75 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_76 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_77 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_78 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_79 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_80 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_81 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_82 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_83 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_84 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_85 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_86 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_87 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_88 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_89 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_90 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_91 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_92 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_93 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_94 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_95 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_96 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_97 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_98 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_99 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_100 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_101 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_102 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_103 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_104 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_105 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_106 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_107 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_108 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_109 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_110 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_111 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_112 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_113 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_114 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_115 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_116 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_117 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_118 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_119 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_120 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_121 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_122 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_123 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_124 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_125 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_126 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_127 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_128 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_129 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_130 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_131 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_132 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_133 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_134 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_135 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_136 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_137 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_138 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_139 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_140 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_141 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_142 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_143 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_144 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_145 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_146 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_147 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_148 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_149 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_150 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_151 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_152 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_153 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_154 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_155 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_156 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_157 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_158 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_159 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_160 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_161 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_162 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_163 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_164 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_165 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_166 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_167 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_168 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_169 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_170 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_171 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_172 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_173 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_174 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_175 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_176 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_177 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_178 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_179 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_180 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_181 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_182 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_183 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_184 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_185 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_186 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_187 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_188 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_189 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_190 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_191 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_192 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_193 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_194 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_195 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_196 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_197 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_198 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_199 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_200 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_201 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_202 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_203 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_204 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_205 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_206 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_207 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_208 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_209 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_210 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_211 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_212 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_213 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_214 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_215 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_216 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_217 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_218 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_219 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_220 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_221 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_222 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_223 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_224 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_225 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_226 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_227 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_228 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_229 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_230 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_231 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_232 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_233 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_234 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_235 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_236 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_237 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_238 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_239 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_240 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_241 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_242 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_243 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_244 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_245 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_246 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_247 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_248 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_249 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_250 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_251 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_252 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_253 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_254 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_255 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wofireMux_1 = 1'h1; // @[MuxLiteral.scala:49:10] wire out_iready_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_oready_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_2_11 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_12 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_13 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_14 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_15 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_16 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_17 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_18 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_19 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_20 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_21 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_22 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_23 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_24 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_25 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_26 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_27 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_28 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_29 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_30 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_31 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_34 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_35 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_36 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_37 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_38 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_39 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_40 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_41 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_42 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_43 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_44 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_45 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_46 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_47 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_48 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_49 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_50 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_51 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_52 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_53 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_54 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_55 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_56 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_57 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_58 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_59 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_60 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_61 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_62 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_63 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_64 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_65 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_66 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_67 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_68 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_69 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_70 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_71 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_72 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_73 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_74 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_75 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_76 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_77 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_78 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_79 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_80 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_81 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_82 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_83 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_84 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_85 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_86 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_87 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_88 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_89 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_90 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_91 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_92 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_93 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_94 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_95 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_97 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_98 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_99 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_100 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_101 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_102 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_116 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_117 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_118 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_119 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_120 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_121 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_122 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_123 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_124 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_125 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_126 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_127 = 1'h1; // @[MuxLiteral.scala:49:48] wire [31:0] SBCSWrDataVal = 32'h0; // @[SBA.scala:62:38] wire [31:0] _SBCSWrData_WIRE_1 = 32'h0; // @[SBA.scala:63:61] wire [31:0] _SBADDRESSWrData_WIRE_0 = 32'h0; // @[SBA.scala:106:46] wire [31:0] _SBADDRESSWrData_WIRE_1 = 32'h0; // @[SBA.scala:106:46] wire [31:0] _SBADDRESSWrData_WIRE_2 = 32'h0; // @[SBA.scala:106:46] wire [31:0] _SBADDRESSWrData_WIRE_3 = 32'h0; // @[SBA.scala:106:46] wire [31:0] SBADDRESSWrData_1 = 32'h0; // @[SBA.scala:106:38] wire [31:0] SBADDRESSWrData_2 = 32'h0; // @[SBA.scala:106:38] wire [31:0] SBADDRESSWrData_3 = 32'h0; // @[SBA.scala:106:38] wire [31:0] _SBDATARdData_WIRE_0 = 32'h0; // @[SBA.scala:145:43] wire [31:0] _SBDATARdData_WIRE_1 = 32'h0; // @[SBA.scala:145:43] wire [31:0] _SBDATARdData_WIRE_2 = 32'h0; // @[SBA.scala:145:43] wire [31:0] _SBDATARdData_WIRE_3 = 32'h0; // @[SBA.scala:145:43] wire [31:0] SBDATARdData_2 = 32'h0; // @[SBA.scala:145:35] wire [31:0] SBDATARdData_3 = 32'h0; // @[SBA.scala:145:35] wire [31:0] _SBDATAWrData_WIRE_0 = 32'h0; // @[SBA.scala:147:43] wire [31:0] _SBDATAWrData_WIRE_1 = 32'h0; // @[SBA.scala:147:43] wire [31:0] _SBDATAWrData_WIRE_2 = 32'h0; // @[SBA.scala:147:43] wire [31:0] _SBDATAWrData_WIRE_3 = 32'h0; // @[SBA.scala:147:43] wire [31:0] SBDATAWrData_2 = 32'h0; // @[SBA.scala:147:35] wire [31:0] SBDATAWrData_3 = 32'h0; // @[SBA.scala:147:35] wire [31:0] sb2tlOpt_io_dataIn_hi_lo = 32'h0; // @[SBA.scala:175:85] wire [31:0] sb2tlOpt_io_dataIn_hi_hi = 32'h0; // @[SBA.scala:175:85] wire [31:0] _out_out_bits_data_WIRE_1_1 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_2 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_3 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_12 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_13 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_14 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_15 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_16 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_18 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_20 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_21 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_25 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_26 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_27 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_28 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_29 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_30 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_31 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_48 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_49 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_50 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_51 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_52 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_53 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_54 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_55 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_58 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_59 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_62 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_63 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] dmiNodeIn_d_bits_d_data = 32'h0; // @[Edges.scala:792:17] wire [31:0] _out_prepend_T_420 = 32'h0; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_578 = 32'h0; // @[RegisterRouter.scala:87:24] wire [5:0] _SBCSFieldsRegReset_WIRE_reserved0 = 6'h0; // @[SBA.scala:49:51] wire [5:0] SBCSFieldsRegReset_reserved0 = 6'h0; // @[SBA.scala:49:38] wire [5:0] _SBCSRdData_WIRE_reserved0 = 6'h0; // @[SBA.scala:60:51] wire [5:0] SBCSRdData_reserved0 = 6'h0; // @[SBA.scala:60:38] wire [5:0] _SBCSWrData_WIRE_reserved0 = 6'h0; // @[SBA.scala:63:61] wire [5:0] _SBCSWrData_T_13 = 6'h0; // @[SBA.scala:63:61] wire [5:0] SBCSWrData_reserved0 = 6'h0; // @[SBA.scala:63:38] wire [5:0] _SBCSRdData_WIRE_1_reserved0 = 6'h0; // @[SBA.scala:243:33] wire [5:0] _flags_WIRE_reserved = 6'h0; // @[Debug.scala:1517:87] wire [5:0] _flags_WIRE_1_reserved = 6'h0; // @[Debug.scala:1517:87] wire [5:0] _flags_WIRE_2_0_reserved = 6'h0; // @[Debug.scala:1517:33] wire [5:0] _flags_WIRE_2_1_reserved = 6'h0; // @[Debug.scala:1517:33] wire [5:0] flags_0_reserved = 6'h0; // @[Debug.scala:1517:25] wire [5:0] flags_1_reserved = 6'h0; // @[Debug.scala:1517:25] wire [3:0] _DMSTATUSRdData_WIRE_version = 4'h0; // @[Debug.scala:978:47] wire [3:0] _DMCS2RdData_WIRE_exttrigger = 4'h0; // @[Debug.scala:1025:47] wire [3:0] DMCS2RdData_exttrigger = 4'h0; // @[Debug.scala:1025:34] wire [3:0] _DMCS2WrData_WIRE_exttrigger = 4'h0; // @[Debug.scala:1026:47] wire [3:0] DMCS2WrData_exttrigger = 4'h0; // @[Debug.scala:1026:34] wire [3:0] _ABSTRACTCSReset_WIRE_reserved3 = 4'h0; // @[Debug.scala:1179:48] wire [3:0] _ABSTRACTCSReset_WIRE_datacount = 4'h0; // @[Debug.scala:1179:48] wire [3:0] ABSTRACTCSReset_reserved3 = 4'h0; // @[Debug.scala:1179:35] wire [3:0] _ABSTRACTCSWrData_WIRE_reserved3 = 4'h0; // @[Debug.scala:1184:52] wire [3:0] _ABSTRACTCSWrData_WIRE_datacount = 4'h0; // @[Debug.scala:1184:52] wire [3:0] ABSTRACTCSWrData_reserved3 = 4'h0; // @[Debug.scala:1184:39] wire [3:0] ABSTRACTCSWrData_datacount = 4'h0; // @[Debug.scala:1184:39] wire [3:0] ABSTRACTCSRdData_reserved3 = 4'h0; // @[Debug.scala:1185:39] wire [3:0] _ABSTRACTAUTOReset_WIRE_reserved0 = 4'h0; // @[Debug.scala:1234:54] wire [3:0] ABSTRACTAUTOReset_reserved0 = 4'h0; // @[Debug.scala:1234:41] wire [3:0] _ABSTRACTAUTOWrData_WIRE_reserved0 = 4'h0; // @[Debug.scala:1236:54] wire [3:0] ABSTRACTAUTOWrData_reserved0 = 4'h0; // @[Debug.scala:1236:41] wire [3:0] ABSTRACTAUTORdData_reserved0 = 4'h0; // @[Debug.scala:1237:41] wire [3:0] jalAbstract_imm2_lo = 4'h0; // @[package.scala:45:27] wire [3:0] jalAbstract_imm2_hi = 4'h0; // @[package.scala:45:27] wire [7:0] _out_T_1223 = 8'h8; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1224 = 8'h8; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_86 = 8'h8; // @[RegisterRouter.scala:87:24] wire [4:0] out_prepend_85 = 5'h8; // @[RegisterRouter.scala:87:24] wire [3:0] ABSTRACTCSReset_datacount = 4'h8; // @[Debug.scala:1179:35] wire [3:0] ABSTRACTCSRdData_datacount = 4'h8; // @[Debug.scala:1185:39] wire [3:0] _out_T_1214 = 4'h8; // @[RegisterRouter.scala:87:24] wire [3:0] _out_T_1215 = 4'h8; // @[RegisterRouter.scala:87:24] wire [3:0] _out_prepend_T_85 = 4'h8; // @[RegisterRouter.scala:87:24] wire [15:0] _ABSTRACTAUTOReset_WIRE_autoexecprogbuf = 16'h0; // @[Debug.scala:1234:54] wire [15:0] ABSTRACTAUTOReset_autoexecprogbuf = 16'h0; // @[Debug.scala:1234:41] wire [15:0] _ABSTRACTAUTOWrData_WIRE_autoexecprogbuf = 16'h0; // @[Debug.scala:1236:54] wire [15:0] sb2tlOpt_io_dataIn_hi_lo_lo = 16'h0; // @[SBA.scala:175:85] wire [15:0] sb2tlOpt_io_dataIn_hi_lo_hi = 16'h0; // @[SBA.scala:175:85] wire [15:0] sb2tlOpt_io_dataIn_hi_hi_lo = 16'h0; // @[SBA.scala:175:85] wire [15:0] sb2tlOpt_io_dataIn_hi_hi_hi = 16'h0; // @[SBA.scala:175:85] wire [95:0] _sb2tlOpt_io_addrIn_T = 96'h0; // @[SBA.scala:132:14] wire [2:0] SBCSFieldsRegReset_sbversion = 3'h1; // @[SBA.scala:49:38] wire [2:0] SBCSRdData_sbversion = 3'h1; // @[SBA.scala:60:38] wire [10:0] _ABSTRACTCSReset_WIRE_reserved1 = 11'h0; // @[Debug.scala:1179:48] wire [10:0] ABSTRACTCSReset_reserved1 = 11'h0; // @[Debug.scala:1179:35] wire [10:0] _ABSTRACTCSWrData_WIRE_reserved1 = 11'h0; // @[Debug.scala:1184:52] wire [10:0] ABSTRACTCSWrData_reserved1 = 11'h0; // @[Debug.scala:1184:39] wire [10:0] ABSTRACTCSRdData_reserved1 = 11'h0; // @[Debug.scala:1185:39] wire [4:0] ABSTRACTCSReset_progbufsize = 5'h10; // @[Debug.scala:1179:35] wire [4:0] ABSTRACTCSRdData_progbufsize = 5'h10; // @[Debug.scala:1185:39] wire [7:0] _COMMANDReset_WIRE_cmdtype = 8'h0; // @[Debug.scala:1276:45] wire [7:0] COMMANDReset_cmdtype = 8'h0; // @[Debug.scala:1276:32] wire [7:0] _jalAbstract_WIRE_imm2 = 8'h0; // @[Debug.scala:1497:66] wire [7:0] jalAbstract_imm2 = 8'h0; // @[Debug.scala:1497:32] wire [7:0] _jalAbstract_imm2_T = 8'h0; // @[package.scala:45:27] wire [6:0] SBCSFieldsRegReset_sbasize = 7'h20; // @[SBA.scala:49:38] wire [6:0] SBCSRdData_sbasize = 7'h20; // @[SBA.scala:60:38] wire [1:0] auto_tl_in_d_bits_param = 2'h0; // @[Debug.scala:790:9] wire [1:0] auto_dmi_in_d_bits_param = 2'h0; // @[Debug.scala:790:9] wire [1:0] dmiNodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] tlNodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] _DMSTATUSRdData_WIRE_reserved1 = 2'h0; // @[Debug.scala:978:47] wire [1:0] DMSTATUSRdData_reserved1 = 2'h0; // @[Debug.scala:978:34] wire [1:0] _haltedBitRegs_T_4 = 2'h0; // @[Debug.scala:1330:43] wire [1:0] _haltedBitRegs_T_6 = 2'h0; // @[Debug.scala:1330:69] wire [1:0] _resumeReqRegs_T_3 = 2'h0; // @[Debug.scala:1338:43] wire [1:0] _resumeReqRegs_T_5 = 2'h0; // @[Debug.scala:1338:69] wire [1:0] dmiNodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17] wire [1:0] jalAbstract_imm0_lo_lo = 2'h0; // @[package.scala:45:27] wire [1:0] jalAbstract_imm0_hi_lo = 2'h0; // @[package.scala:45:27] wire [1:0] jalAbstract_imm0_hi_hi_hi = 2'h0; // @[package.scala:45:27] wire [1:0] jalAbstract_imm1_lo_lo = 2'h0; // @[package.scala:45:27] wire [1:0] jalAbstract_imm1_lo_hi_hi = 2'h0; // @[package.scala:45:27] wire [1:0] jalAbstract_imm1_hi_lo = 2'h0; // @[package.scala:45:27] wire [1:0] jalAbstract_imm1_hi_hi_hi = 2'h0; // @[package.scala:45:27] wire [1:0] jalAbstract_imm2_lo_lo = 2'h0; // @[package.scala:45:27] wire [1:0] jalAbstract_imm2_lo_hi = 2'h0; // @[package.scala:45:27] wire [1:0] jalAbstract_imm2_hi_lo = 2'h0; // @[package.scala:45:27] wire [1:0] jalAbstract_imm2_hi_hi = 2'h0; // @[package.scala:45:27] wire [1:0] tlNodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17] wire [63:0] _out_out_bits_data_WIRE_3_96 = 64'h380006F; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_10 = 64'h100073; // @[MuxLiteral.scala:49:48] wire [63:0] out_prepend_349 = 64'h100026237B200073; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4404 = 64'h100026237B200073; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4405 = 64'h100026237B200073; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_9 = 64'h100026237B200073; // @[MuxLiteral.scala:49:48] wire [63:0] out_prepend_592 = 64'h7B20247310802423; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6965 = 64'h7B20247310802423; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6966 = 64'h7B20247310802423; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_8 = 64'h7B20247310802423; // @[MuxLiteral.scala:49:48] wire [63:0] out_prepend_866 = 64'hF140247330000067; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9839 = 64'hF140247330000067; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9840 = 64'hF140247330000067; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_7 = 64'hF140247330000067; // @[MuxLiteral.scala:49:48] wire [63:0] out_prepend_1055 = 64'h100022237B202473; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11815 = 64'h100022237B202473; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11816 = 64'h100022237B202473; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_6 = 64'h100022237B202473; // @[MuxLiteral.scala:49:48] wire [63:0] out_prepend_258 = 64'h4086300147413; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3452 = 64'h4086300147413; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3453 = 64'h4086300147413; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_5 = 64'h4086300147413; // @[MuxLiteral.scala:49:48] wire [63:0] out_prepend_391 = 64'hFE0408E300347413; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4836 = 64'hFE0408E300347413; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4837 = 64'hFE0408E300347413; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_4 = 64'hFE0408E300347413; // @[MuxLiteral.scala:49:48] wire [63:0] out_prepend_641 = 64'h4004440310802023; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7469 = 64'h4004440310802023; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7470 = 64'h4004440310802023; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_3 = 64'h4004440310802023; // @[MuxLiteral.scala:49:48] wire [63:0] out_prepend_950 = 64'hF14024737B241073; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10719 = 64'hF14024737B241073; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10720 = 64'hF14024737B241073; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_2 = 64'hF14024737B241073; // @[MuxLiteral.scala:49:48] wire [63:0] out_prepend_202 = 64'hFF0000F0440006F; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2860 = 64'hFF0000F0440006F; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2861 = 64'hFF0000F0440006F; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_1 = 64'hFF0000F0440006F; // @[MuxLiteral.scala:49:48] wire [63:0] out_prepend_511 = 64'h380006F00C0006F; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6103 = 64'h380006F00C0006F; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6104 = 64'h380006F00C0006F; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_0 = 64'h380006F00C0006F; // @[MuxLiteral.scala:49:48] wire [55:0] out_prepend_1054 = 56'h22237B202473; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11806 = 56'h22237B202473; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11807 = 56'h22237B202473; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1055 = 56'h22237B202473; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1053 = 48'h22237B202473; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11797 = 48'h22237B202473; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11798 = 48'h22237B202473; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1054 = 48'h22237B202473; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1052 = 40'h237B202473; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11788 = 40'h237B202473; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11789 = 40'h237B202473; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1053 = 40'h237B202473; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1051 = 32'h7B202473; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11779 = 32'h7B202473; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11780 = 32'h7B202473; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1052 = 32'h7B202473; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1050 = 24'h202473; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11770 = 24'h202473; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11771 = 24'h202473; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1051 = 24'h202473; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1049 = 16'h2473; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11761 = 16'h2473; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11762 = 16'h2473; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1050 = 16'h2473; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4341 = 8'h73; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4342 = 8'h73; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_343 = 8'h73; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6328 = 8'h73; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6329 = 8'h73; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_533 = 8'h73; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10656 = 8'h73; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10657 = 8'h73; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_944 = 8'h73; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11752 = 8'h73; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11753 = 8'h73; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1049 = 8'h73; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_949 = 56'h4024737B241073; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10710 = 56'h4024737B241073; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10711 = 56'h4024737B241073; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_950 = 56'h4024737B241073; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_948 = 48'h24737B241073; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10701 = 48'h24737B241073; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10702 = 48'h24737B241073; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_949 = 48'h24737B241073; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_947 = 40'h737B241073; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10692 = 40'h737B241073; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10693 = 40'h737B241073; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_948 = 40'h737B241073; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_946 = 32'h7B241073; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10683 = 32'h7B241073; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10684 = 32'h7B241073; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_947 = 32'h7B241073; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_945 = 24'h241073; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10674 = 24'h241073; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10675 = 24'h241073; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_946 = 24'h241073; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_944 = 16'h1073; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10665 = 16'h1073; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10666 = 16'h1073; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_945 = 16'h1073; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_865 = 56'h40247330000067; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9830 = 56'h40247330000067; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9831 = 56'h40247330000067; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_866 = 56'h40247330000067; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_864 = 48'h247330000067; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9821 = 48'h247330000067; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9822 = 48'h247330000067; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_865 = 48'h247330000067; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_863 = 40'h7330000067; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9812 = 40'h7330000067; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9813 = 40'h7330000067; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_864 = 40'h7330000067; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_862 = 32'h30000067; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9803 = 32'h30000067; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9804 = 32'h30000067; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_863 = 32'h30000067; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_861 = 24'h67; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9794 = 24'h67; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9795 = 24'h67; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_862 = 24'h67; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_860 = 16'h67; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9785 = 16'h67; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9786 = 16'h67; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_861 = 16'h67; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9776 = 8'h67; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9777 = 8'h67; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_860 = 8'h67; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_640 = 56'h4440310802023; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7460 = 56'h4440310802023; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7461 = 56'h4440310802023; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_641 = 56'h4440310802023; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_639 = 48'h440310802023; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7451 = 48'h440310802023; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7452 = 48'h440310802023; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_640 = 48'h440310802023; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_638 = 40'h310802023; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7442 = 40'h310802023; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7443 = 40'h310802023; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_639 = 40'h310802023; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_637 = 32'h10802023; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7433 = 32'h10802023; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7434 = 32'h10802023; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_638 = 32'h10802023; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_636 = 24'h802023; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7424 = 24'h802023; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7425 = 24'h802023; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_637 = 24'h802023; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_635 = 16'h2023; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7415 = 16'h2023; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7416 = 16'h2023; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_636 = 16'h2023; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6902 = 8'h23; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6903 = 8'h23; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_586 = 8'h23; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7406 = 8'h23; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7407 = 8'h23; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_635 = 8'h23; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_591 = 56'h20247310802423; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6956 = 56'h20247310802423; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6957 = 56'h20247310802423; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_592 = 56'h20247310802423; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_590 = 48'h247310802423; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6947 = 48'h247310802423; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6948 = 48'h247310802423; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_591 = 48'h247310802423; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_589 = 40'h7310802423; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6938 = 40'h7310802423; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6939 = 40'h7310802423; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_590 = 40'h7310802423; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_588 = 32'h10802423; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6929 = 32'h10802423; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6930 = 32'h10802423; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_589 = 32'h10802423; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_587 = 24'h802423; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6920 = 24'h802423; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6921 = 24'h802423; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_588 = 24'h802423; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_586 = 16'h2423; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6911 = 16'h2423; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6912 = 16'h2423; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_587 = 16'h2423; // @[RegisterRouter.scala:87:24] wire [41:0] _out_T_5142 = 42'h0; // @[RegisterRouter.scala:87:24] wire [41:0] _out_T_5143 = 42'h0; // @[RegisterRouter.scala:87:24] wire [41:0] _out_T_6821 = 42'h0; // @[RegisterRouter.scala:87:24] wire [41:0] _out_T_6822 = 42'h0; // @[RegisterRouter.scala:87:24] wire [32:0] out_prepend_420 = 33'h0; // @[RegisterRouter.scala:87:24] wire [32:0] out_prepend_578 = 33'h0; // @[RegisterRouter.scala:87:24] wire [9:0] _jalAbstract_WIRE_imm0 = 10'h0; // @[Debug.scala:1497:66] wire [9:0] _jalAbstract_imm1_T = 10'h0; // @[package.scala:45:27] wire [9:0] _out_T_5133 = 10'h0; // @[RegisterRouter.scala:87:24] wire [9:0] _out_T_5134 = 10'h0; // @[RegisterRouter.scala:87:24] wire [9:0] _out_T_6812 = 10'h0; // @[RegisterRouter.scala:87:24] wire [9:0] _out_T_6813 = 10'h0; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_535 = 32'h100073; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6355 = 32'h100073; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6356 = 32'h100073; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_534 = 24'h100073; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6346 = 24'h100073; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6347 = 24'h100073; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_535 = 24'h100073; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_343 = 16'h73; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4350 = 16'h73; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4351 = 16'h73; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_344 = 16'h73; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_533 = 16'h73; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6337 = 16'h73; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6338 = 16'h73; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_534 = 16'h73; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_510 = 56'h80006F00C0006F; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6094 = 56'h80006F00C0006F; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6095 = 56'h80006F00C0006F; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_511 = 56'h80006F00C0006F; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_509 = 48'h6F00C0006F; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6085 = 48'h6F00C0006F; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6086 = 48'h6F00C0006F; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_510 = 48'h6F00C0006F; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_508 = 40'h6F00C0006F; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6076 = 40'h6F00C0006F; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6077 = 40'h6F00C0006F; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_509 = 40'h6F00C0006F; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_507 = 32'hC0006F; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6067 = 32'hC0006F; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6068 = 32'hC0006F; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_508 = 32'hC0006F; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_506 = 24'hC0006F; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6058 = 24'hC0006F; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6059 = 24'hC0006F; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_507 = 24'hC0006F; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_196 = 16'h6F; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2806 = 16'h6F; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2807 = 16'h6F; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_197 = 16'h6F; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_505 = 16'h6F; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6049 = 16'h6F; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6050 = 16'h6F; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_506 = 16'h6F; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2797 = 8'h6F; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2798 = 8'h6F; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_196 = 8'h6F; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6040 = 8'h6F; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6041 = 8'h6F; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_505 = 8'h6F; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5943 = 32'h380006F; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5944 = 32'h380006F; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_390 = 56'h408E300347413; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4827 = 56'h408E300347413; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4828 = 56'h408E300347413; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_391 = 56'h408E300347413; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_389 = 48'h8E300347413; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4818 = 48'h8E300347413; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4819 = 48'h8E300347413; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_390 = 48'h8E300347413; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_388 = 40'hE300347413; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4809 = 40'hE300347413; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4810 = 40'hE300347413; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_389 = 40'hE300347413; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_387 = 32'h347413; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4800 = 32'h347413; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4801 = 32'h347413; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_388 = 32'h347413; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_386 = 24'h347413; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4791 = 24'h347413; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4792 = 24'h347413; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_387 = 24'h347413; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_252 = 16'h7413; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3398 = 16'h7413; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3399 = 16'h7413; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_253 = 16'h7413; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_385 = 16'h7413; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4782 = 16'h7413; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4783 = 16'h7413; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_386 = 16'h7413; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3389 = 8'h13; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3390 = 8'h13; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_252 = 8'h13; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4773 = 8'h13; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4774 = 8'h13; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_385 = 8'h13; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_348 = 56'h26237B200073; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4395 = 56'h26237B200073; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4396 = 56'h26237B200073; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_349 = 56'h26237B200073; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_347 = 48'h26237B200073; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4386 = 48'h26237B200073; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4387 = 48'h26237B200073; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_348 = 48'h26237B200073; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_346 = 40'h237B200073; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4377 = 40'h237B200073; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4378 = 40'h237B200073; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_347 = 40'h237B200073; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_345 = 32'h7B200073; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4368 = 32'h7B200073; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4369 = 32'h7B200073; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_346 = 32'h7B200073; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_344 = 24'h200073; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4359 = 24'h200073; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4360 = 24'h200073; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_345 = 24'h200073; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_257 = 56'h4086300147413; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3443 = 56'h4086300147413; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3444 = 56'h4086300147413; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_258 = 56'h4086300147413; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_256 = 48'h86300147413; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3434 = 48'h86300147413; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3435 = 48'h86300147413; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_257 = 48'h86300147413; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_255 = 40'h6300147413; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3425 = 40'h6300147413; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3426 = 40'h6300147413; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_256 = 40'h6300147413; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_254 = 32'h147413; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3416 = 32'h147413; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3417 = 32'h147413; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_255 = 32'h147413; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_253 = 24'h147413; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3407 = 24'h147413; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3408 = 24'h147413; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_254 = 24'h147413; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_201 = 56'hF0000F0440006F; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2851 = 56'hF0000F0440006F; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2852 = 56'hF0000F0440006F; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_202 = 56'hF0000F0440006F; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_200 = 48'hF0440006F; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2842 = 48'hF0440006F; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2843 = 48'hF0440006F; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_201 = 48'hF0440006F; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_199 = 40'hF0440006F; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2833 = 40'hF0440006F; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2834 = 40'hF0440006F; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_200 = 40'hF0440006F; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_198 = 32'h440006F; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2824 = 32'h440006F; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2825 = 32'h440006F; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_199 = 32'h440006F; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_197 = 24'h40006F; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2815 = 24'h40006F; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2816 = 24'h40006F; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_198 = 24'h40006F; // @[RegisterRouter.scala:87:24] wire [8:0] out_maskMatch_1 = 9'h100; // @[RegisterRouter.scala:87:24] wire [11:0] hi = 12'h38; // @[Debug.scala:1697:55] wire [10:0] hi_hi = 11'h1C; // @[Debug.scala:1697:55] wire [19:0] lo = 20'h6F; // @[Debug.scala:1697:55] wire [12:0] lo_hi = 13'h0; // @[Debug.scala:1697:55] wire [31:0] _abstractGeneratedMem_0_T_3 = 32'h13; // @[Debug.scala:1642:15] wire [31:0] _abstractGeneratedMem_1_T = 32'h13; // @[Debug.scala:1645:15] wire [19:0] abstractGeneratedMem_0_hi_2 = 20'h0; // @[Debug.scala:1642:15] wire [19:0] abstractGeneratedMem_1_hi = 20'h0; // @[Debug.scala:1645:15] wire [16:0] abstractGeneratedMem_0_hi_hi_2 = 17'h0; // @[Debug.scala:1642:15] wire [16:0] abstractGeneratedMem_1_hi_hi = 17'h0; // @[Debug.scala:1645:15] wire [11:0] abstractGeneratedMem_0_lo_2 = 12'h13; // @[Debug.scala:1642:15] wire [11:0] abstractGeneratedMem_1_lo = 12'h13; // @[Debug.scala:1645:15] wire [6:0] abstractGeneratedMem_0_inst_1_opcode = 7'h23; // @[Debug.scala:1601:22] wire [6:0] _abstractGeneratedMem_0_inst_opcode_WIRE_1_opcode = 7'h23; // @[Debug.scala:1604:55] wire [4:0] _DMCS2RdData_WIRE_haltgroup = 5'h0; // @[Debug.scala:1025:47] wire [4:0] DMCS2RdData_haltgroup = 5'h0; // @[Debug.scala:1025:34] wire [4:0] _DMCS2WrData_WIRE_haltgroup = 5'h0; // @[Debug.scala:1026:47] wire [4:0] DMCS2WrData_haltgroup = 5'h0; // @[Debug.scala:1026:34] wire [4:0] _ABSTRACTCSReset_WIRE_progbufsize = 5'h0; // @[Debug.scala:1179:48] wire [4:0] _ABSTRACTCSWrData_WIRE_progbufsize = 5'h0; // @[Debug.scala:1184:52] wire [4:0] ABSTRACTCSWrData_progbufsize = 5'h0; // @[Debug.scala:1184:39] wire [4:0] _jalAbstract_WIRE_rd = 5'h0; // @[Debug.scala:1497:66] wire [4:0] jalAbstract_rd = 5'h0; // @[Debug.scala:1497:32] wire [4:0] jalAbstract_imm0_hi = 5'h0; // @[package.scala:45:27] wire [4:0] jalAbstract_imm1_lo = 5'h0; // @[package.scala:45:27] wire [4:0] jalAbstract_imm1_hi = 5'h0; // @[package.scala:45:27] wire [4:0] nop_rs1 = 5'h0; // @[Debug.scala:1623:19] wire [4:0] nop_rd = 5'h0; // @[Debug.scala:1623:19] wire [4:0] _nop_WIRE_rs1 = 5'h0; // @[Debug.scala:1624:46] wire [4:0] _nop_WIRE_rd = 5'h0; // @[Debug.scala:1624:46] wire [4:0] isa_rs1 = 5'h0; // @[Debug.scala:1629:19] wire [4:0] isa_rd = 5'h0; // @[Debug.scala:1629:19] wire [4:0] _isa_WIRE_rs1 = 5'h0; // @[Debug.scala:1630:47] wire [4:0] _isa_WIRE_rd = 5'h0; // @[Debug.scala:1630:47] wire [4:0] abstractGeneratedMem_0_inst_rs1 = 5'h0; // @[Debug.scala:1589:22] wire [4:0] _abstractGeneratedMem_0_inst_opcode_WIRE_rs1 = 5'h0; // @[Debug.scala:1592:55] wire [4:0] _abstractGeneratedMem_0_inst_opcode_WIRE_rd = 5'h0; // @[Debug.scala:1592:55] wire [4:0] abstractGeneratedMem_0_inst_1_rs1 = 5'h0; // @[Debug.scala:1601:22] wire [4:0] abstractGeneratedMem_0_inst_1_immlo = 5'h0; // @[Debug.scala:1601:22] wire [4:0] _abstractGeneratedMem_0_inst_opcode_WIRE_1_rs2 = 5'h0; // @[Debug.scala:1604:55] wire [4:0] _abstractGeneratedMem_0_inst_opcode_WIRE_1_rs1 = 5'h0; // @[Debug.scala:1604:55] wire [4:0] _abstractGeneratedMem_0_inst_opcode_WIRE_1_immlo = 5'h0; // @[Debug.scala:1604:55] wire [2:0] SBCSFieldsRegReset_sbaccess = 3'h2; // @[SBA.scala:49:38] wire [2:0] _abstractGeneratedMem_0_inst_opcode_WIRE_funct3 = 3'h2; // @[Debug.scala:1592:55] wire [2:0] _abstractGeneratedMem_0_inst_opcode_WIRE_1_funct3 = 3'h2; // @[Debug.scala:1604:55] wire [6:0] _SBCSFieldsRegReset_WIRE_sbasize = 7'h0; // @[SBA.scala:49:51] wire [6:0] _SBCSRdData_WIRE_sbasize = 7'h0; // @[SBA.scala:60:51] wire [6:0] _SBCSWrData_WIRE_sbasize = 7'h0; // @[SBA.scala:63:61] wire [6:0] _SBCSWrData_T_5 = 7'h0; // @[SBA.scala:63:61] wire [6:0] SBCSWrData_sbasize = 7'h0; // @[SBA.scala:63:38] wire [6:0] _SBCSRdData_WIRE_1_sbasize = 7'h0; // @[SBA.scala:243:33] wire [6:0] _abstractGeneratedMem_0_inst_opcode_WIRE_1_immhi = 7'h0; // @[Debug.scala:1604:55] wire [6:0] abstractGeneratedMem_0_inst_1_immhi = 7'h1C; // @[Debug.scala:1601:22] wire [16:0] abstractGeneratedMem_0_hi_hi = 17'h7000; // @[Debug.scala:1597:12] wire [6:0] abstractGeneratedMem_0_inst_opcode = 7'h3; // @[Debug.scala:1589:22] wire [6:0] _abstractGeneratedMem_0_inst_opcode_WIRE_opcode = 7'h3; // @[Debug.scala:1592:55] wire [11:0] _ABSTRACTAUTOReset_WIRE_autoexecdata = 12'h0; // @[Debug.scala:1234:54] wire [11:0] ABSTRACTAUTOReset_autoexecdata = 12'h0; // @[Debug.scala:1234:41] wire [11:0] _ABSTRACTAUTOWrData_WIRE_autoexecdata = 12'h0; // @[Debug.scala:1236:54] wire [11:0] nop_imm = 12'h0; // @[Debug.scala:1623:19] wire [11:0] _nop_WIRE_imm = 12'h0; // @[Debug.scala:1624:46] wire [11:0] isa_imm = 12'h0; // @[Debug.scala:1629:19] wire [11:0] _isa_WIRE_imm = 12'h0; // @[Debug.scala:1630:47] wire [11:0] _abstractGeneratedMem_0_inst_opcode_WIRE_imm = 12'h0; // @[Debug.scala:1592:55] wire [11:0] abstractGeneratedMem_0_inst_imm = 12'h380; // @[Debug.scala:1589:22] wire [6:0] isa_opcode = 7'h1B; // @[Debug.scala:1629:19] wire [6:0] _isa_WIRE_opcode = 7'h1B; // @[Debug.scala:1630:47] wire [6:0] nop_opcode = 7'h13; // @[Debug.scala:1623:19] wire [6:0] _nop_WIRE_opcode = 7'h13; // @[Debug.scala:1624:46] wire [9:0] jalAbstract_imm0 = 10'h1C; // @[Debug.scala:1497:32] wire [9:0] _jalAbstract_imm0_T = 10'h1C; // @[package.scala:45:27] wire [4:0] jalAbstract_imm0_lo = 5'h1C; // @[package.scala:45:27] wire [2:0] out_prepend_25 = 3'h7; // @[RegisterRouter.scala:87:24] wire [2:0] _out_T_456 = 3'h7; // @[RegisterRouter.scala:87:24] wire [2:0] _out_T_457 = 3'h7; // @[RegisterRouter.scala:87:24] wire [2:0] _out_prepend_T_26 = 3'h7; // @[RegisterRouter.scala:87:24] wire [2:0] jalAbstract_imm0_lo_hi = 3'h7; // @[package.scala:45:27] wire [1:0] out_prepend_24 = 2'h3; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_447 = 2'h3; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_448 = 2'h3; // @[RegisterRouter.scala:87:24] wire [1:0] _out_prepend_T_25 = 2'h3; // @[RegisterRouter.scala:87:24] wire [1:0] jalAbstract_imm0_lo_hi_hi = 2'h3; // @[package.scala:45:27] wire [20:0] immWire = 21'h38; // @[Debug.scala:1574:31] wire [6:0] _jalAbstract_WIRE_opcode = 7'h6F; // @[Debug.scala:1497:66] wire [6:0] jalAbstract_opcode = 7'h6F; // @[Debug.scala:1497:32] wire [7:0] out_prepend_64 = 8'hA2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_991 = 8'hA2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_992 = 8'hA2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_65 = 8'hA2; // @[RegisterRouter.scala:87:24] wire [6:0] out_prepend_63 = 7'h22; // @[RegisterRouter.scala:87:24] wire [6:0] _out_T_982 = 7'h22; // @[RegisterRouter.scala:87:24] wire [6:0] _out_T_983 = 7'h22; // @[RegisterRouter.scala:87:24] wire [6:0] _out_prepend_T_64 = 7'h22; // @[RegisterRouter.scala:87:24] wire [5:0] out_prepend_62 = 6'h22; // @[RegisterRouter.scala:87:24] wire [5:0] _out_T_973 = 6'h22; // @[RegisterRouter.scala:87:24] wire [5:0] _out_T_974 = 6'h22; // @[RegisterRouter.scala:87:24] wire [5:0] _out_prepend_T_63 = 6'h22; // @[RegisterRouter.scala:87:24] wire [4:0] out_prepend_61 = 5'h2; // @[RegisterRouter.scala:87:24] wire [4:0] _out_T_964 = 5'h2; // @[RegisterRouter.scala:87:24] wire [4:0] _out_T_965 = 5'h2; // @[RegisterRouter.scala:87:24] wire [4:0] _out_prepend_T_62 = 5'h2; // @[RegisterRouter.scala:87:24] wire [3:0] DMSTATUSRdData_version = 4'h2; // @[Debug.scala:978:34] wire [3:0] _out_T_955 = 4'h2; // @[RegisterRouter.scala:87:24] wire [3:0] _out_T_956 = 4'h2; // @[RegisterRouter.scala:87:24] wire [3:0] _out_prepend_T_61 = 4'h2; // @[RegisterRouter.scala:87:24] wire [11:0] out_prepend_28 = 12'h40F; // @[RegisterRouter.scala:87:24] wire [11:0] _out_T_483 = 12'h40F; // @[RegisterRouter.scala:87:24] wire [11:0] _out_T_484 = 12'h40F; // @[RegisterRouter.scala:87:24] wire [11:0] _out_prepend_T_29 = 12'h40F; // @[RegisterRouter.scala:87:24] wire [4:0] out_prepend_27 = 5'hF; // @[RegisterRouter.scala:87:24] wire [4:0] _out_T_474 = 5'hF; // @[RegisterRouter.scala:87:24] wire [4:0] _out_T_475 = 5'hF; // @[RegisterRouter.scala:87:24] wire [4:0] _out_prepend_T_28 = 5'hF; // @[RegisterRouter.scala:87:24] wire [3:0] out_prepend_26 = 4'hF; // @[RegisterRouter.scala:87:24] wire [3:0] _out_T_465 = 4'hF; // @[RegisterRouter.scala:87:24] wire [3:0] _out_T_466 = 4'hF; // @[RegisterRouter.scala:87:24] wire [3:0] _out_prepend_T_27 = 4'hF; // @[RegisterRouter.scala:87:24] wire [6:0] out_maskMatch = 7'h40; // @[RegisterRouter.scala:87:24] wire [1:0] _haltedBitRegs_T_3 = 2'h2; // @[Debug.scala:1330:45] wire [1:0] _resumeReqRegs_T_2 = 2'h2; // @[Debug.scala:1338:45] wire [1:0] hartHaltedIdIndex = 2'h1; // @[OneHot.scala:58:35] wire [1:0] hartResumingIdIndex = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _haltedBitRegs_T = 2'h1; // @[Debug.scala:1327:43] wire [23:0] _COMMANDReset_WIRE_control = 24'h0; // @[Debug.scala:1276:45] wire [23:0] COMMANDReset_control = 24'h0; // @[Debug.scala:1276:32] wire [20:0] _DMCS2RdData_WIRE_reserved0 = 21'h0; // @[Debug.scala:1025:47] wire [20:0] DMCS2RdData_reserved0 = 21'h0; // @[Debug.scala:1025:34] wire [20:0] _DMCS2WrData_WIRE_reserved0 = 21'h0; // @[Debug.scala:1026:47] wire [20:0] DMCS2WrData_reserved0 = 21'h0; // @[Debug.scala:1026:34] wire [8:0] _DMSTATUSRdData_WIRE_reserved0 = 9'h0; // @[Debug.scala:978:47] wire [8:0] DMSTATUSRdData_reserved0 = 9'h0; // @[Debug.scala:978:34] wire tlNodeIn_a_ready; // @[MixedNode.scala:551:17] wire tlNodeIn_a_valid = auto_tl_in_a_valid_0; // @[Debug.scala:790:9] wire [2:0] tlNodeIn_a_bits_opcode = auto_tl_in_a_bits_opcode_0; // @[Debug.scala:790:9] wire [2:0] tlNodeIn_a_bits_param = auto_tl_in_a_bits_param_0; // @[Debug.scala:790:9] wire [1:0] tlNodeIn_a_bits_size = auto_tl_in_a_bits_size_0; // @[Debug.scala:790:9] wire [10:0] tlNodeIn_a_bits_source = auto_tl_in_a_bits_source_0; // @[Debug.scala:790:9] wire [11:0] tlNodeIn_a_bits_address = auto_tl_in_a_bits_address_0; // @[Debug.scala:790:9] wire [7:0] tlNodeIn_a_bits_mask = auto_tl_in_a_bits_mask_0; // @[Debug.scala:790:9] wire [63:0] tlNodeIn_a_bits_data = auto_tl_in_a_bits_data_0; // @[Debug.scala:790:9] wire tlNodeIn_a_bits_corrupt = auto_tl_in_a_bits_corrupt_0; // @[Debug.scala:790:9] wire tlNodeIn_d_ready = auto_tl_in_d_ready_0; // @[Debug.scala:790:9] wire tlNodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] tlNodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] tlNodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [10:0] tlNodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] tlNodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire dmiNodeIn_a_ready; // @[MixedNode.scala:551:17] wire dmiNodeIn_a_valid = auto_dmi_in_a_valid_0; // @[Debug.scala:790:9] wire [2:0] dmiNodeIn_a_bits_opcode = auto_dmi_in_a_bits_opcode_0; // @[Debug.scala:790:9] wire [2:0] dmiNodeIn_a_bits_param = auto_dmi_in_a_bits_param_0; // @[Debug.scala:790:9] wire [1:0] dmiNodeIn_a_bits_size = auto_dmi_in_a_bits_size_0; // @[Debug.scala:790:9] wire dmiNodeIn_a_bits_source = auto_dmi_in_a_bits_source_0; // @[Debug.scala:790:9] wire [8:0] dmiNodeIn_a_bits_address = auto_dmi_in_a_bits_address_0; // @[Debug.scala:790:9] wire [3:0] dmiNodeIn_a_bits_mask = auto_dmi_in_a_bits_mask_0; // @[Debug.scala:790:9] wire [31:0] dmiNodeIn_a_bits_data = auto_dmi_in_a_bits_data_0; // @[Debug.scala:790:9] wire dmiNodeIn_a_bits_corrupt = auto_dmi_in_a_bits_corrupt_0; // @[Debug.scala:790:9] wire dmiNodeIn_d_ready = auto_dmi_in_d_ready_0; // @[Debug.scala:790:9] wire dmiNodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] dmiNodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] dmiNodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire dmiNodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [31:0] dmiNodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire _resumereq_T = io_innerCtrl_valid_0; // @[Decoupled.scala:51:35] wire hrDebugInt_0; // @[Debug.scala:946:26] wire [2:0] auto_sb2tlOpt_out_a_bits_opcode_0; // @[Debug.scala:790:9] wire [3:0] auto_sb2tlOpt_out_a_bits_size_0; // @[Debug.scala:790:9] wire [31:0] auto_sb2tlOpt_out_a_bits_address_0; // @[Debug.scala:790:9] wire [7:0] auto_sb2tlOpt_out_a_bits_data_0; // @[Debug.scala:790:9] wire auto_sb2tlOpt_out_a_valid_0; // @[Debug.scala:790:9] wire auto_sb2tlOpt_out_d_ready_0; // @[Debug.scala:790:9] wire auto_tl_in_a_ready_0; // @[Debug.scala:790:9] wire [2:0] auto_tl_in_d_bits_opcode_0; // @[Debug.scala:790:9] wire [1:0] auto_tl_in_d_bits_size_0; // @[Debug.scala:790:9] wire [10:0] auto_tl_in_d_bits_source_0; // @[Debug.scala:790:9] wire [63:0] auto_tl_in_d_bits_data_0; // @[Debug.scala:790:9] wire auto_tl_in_d_valid_0; // @[Debug.scala:790:9] wire auto_dmi_in_a_ready_0; // @[Debug.scala:790:9] wire [2:0] auto_dmi_in_d_bits_opcode_0; // @[Debug.scala:790:9] wire [1:0] auto_dmi_in_d_bits_size_0; // @[Debug.scala:790:9] wire auto_dmi_in_d_bits_source_0; // @[Debug.scala:790:9] wire [31:0] auto_dmi_in_d_bits_data_0; // @[Debug.scala:790:9] wire auto_dmi_in_d_valid_0; // @[Debug.scala:790:9] wire io_hgDebugInt_0_0; // @[Debug.scala:790:9] wire in_ready; // @[RegisterRouter.scala:73:18] assign auto_dmi_in_a_ready_0 = dmiNodeIn_a_ready; // @[Debug.scala:790:9] wire in_valid = dmiNodeIn_a_valid; // @[RegisterRouter.scala:73:18] wire [1:0] in_bits_extra_tlrr_extra_size = dmiNodeIn_a_bits_size; // @[RegisterRouter.scala:73:18] wire in_bits_extra_tlrr_extra_source = dmiNodeIn_a_bits_source; // @[RegisterRouter.scala:73:18] wire [3:0] in_bits_mask = dmiNodeIn_a_bits_mask; // @[RegisterRouter.scala:73:18] wire [31:0] in_bits_data = dmiNodeIn_a_bits_data; // @[RegisterRouter.scala:73:18] wire out_ready = dmiNodeIn_d_ready; // @[RegisterRouter.scala:87:24] wire out_valid; // @[RegisterRouter.scala:87:24] assign auto_dmi_in_d_valid_0 = dmiNodeIn_d_valid; // @[Debug.scala:790:9] assign auto_dmi_in_d_bits_opcode_0 = dmiNodeIn_d_bits_opcode; // @[Debug.scala:790:9] wire [1:0] dmiNodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign auto_dmi_in_d_bits_size_0 = dmiNodeIn_d_bits_size; // @[Debug.scala:790:9] wire dmiNodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign auto_dmi_in_d_bits_source_0 = dmiNodeIn_d_bits_source; // @[Debug.scala:790:9] wire [31:0] out_bits_data; // @[RegisterRouter.scala:87:24] assign auto_dmi_in_d_bits_data_0 = dmiNodeIn_d_bits_data; // @[Debug.scala:790:9] wire in_1_ready; // @[RegisterRouter.scala:73:18] assign auto_tl_in_a_ready_0 = tlNodeIn_a_ready; // @[Debug.scala:790:9] wire in_1_valid = tlNodeIn_a_valid; // @[RegisterRouter.scala:73:18] wire [1:0] in_1_bits_extra_tlrr_extra_size = tlNodeIn_a_bits_size; // @[RegisterRouter.scala:73:18] wire [10:0] in_1_bits_extra_tlrr_extra_source = tlNodeIn_a_bits_source; // @[RegisterRouter.scala:73:18] wire [7:0] in_1_bits_mask = tlNodeIn_a_bits_mask; // @[RegisterRouter.scala:73:18] wire [63:0] in_1_bits_data = tlNodeIn_a_bits_data; // @[RegisterRouter.scala:73:18] wire out_1_ready = tlNodeIn_d_ready; // @[RegisterRouter.scala:87:24] wire out_1_valid; // @[RegisterRouter.scala:87:24] assign auto_tl_in_d_valid_0 = tlNodeIn_d_valid; // @[Debug.scala:790:9] assign auto_tl_in_d_bits_opcode_0 = tlNodeIn_d_bits_opcode; // @[Debug.scala:790:9] wire [1:0] tlNodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign auto_tl_in_d_bits_size_0 = tlNodeIn_d_bits_size; // @[Debug.scala:790:9] wire [10:0] tlNodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign auto_tl_in_d_bits_source_0 = tlNodeIn_d_bits_source; // @[Debug.scala:790:9] wire [63:0] out_1_bits_data; // @[RegisterRouter.scala:87:24] assign auto_tl_in_d_bits_data_0 = tlNodeIn_d_bits_data; // @[Debug.scala:790:9] reg haltedBitRegs; // @[Debug.scala:861:31] wire _DMSTATUSRdData_anyhalted_T_1 = haltedBitRegs; // @[Debug.scala:861:31, :995:77] wire _DMSTATUSRdData_anyrunning_T_1 = haltedBitRegs; // @[Debug.scala:861:31, :996:77] wire _DMSTATUSRdData_allhalted_T_1 = haltedBitRegs; // @[Debug.scala:861:31, :1001:79] wire _DMSTATUSRdData_allrunning_T_1 = haltedBitRegs; // @[Debug.scala:861:31, :1002:79] wire _haltedStatus_0_T = haltedBitRegs; // @[Debug.scala:861:31, :1163:43] wire _hartHalted_T = haltedBitRegs; // @[Debug.scala:861:31, :1734:37] reg resumeReqRegs; // @[Debug.scala:863:31] wire _flags_resume_T = resumeReqRegs; // @[Debug.scala:863:31, :1524:80] reg haveResetBitRegs; // @[Debug.scala:865:31] wire _DMSTATUSRdData_anyhavereset_T = haveResetBitRegs; // @[Debug.scala:865:31, :997:58] wire _DMSTATUSRdData_allhavereset_T = haveResetBitRegs; // @[Debug.scala:865:31, :1003:60] wire resumeAcks; // @[Debug.scala:869:32] wire _DMSTATUSRdData_anyresumeack_T = resumeAcks; // @[Debug.scala:869:32, :998:52] wire _DMSTATUSRdData_allresumeack_T = resumeAcks; // @[Debug.scala:869:32, :1004:54] wire out_f_woready_681; // @[RegisterRouter.scala:87:24] wire hartHaltedWrEn; // @[Debug.scala:875:36] wire [9:0] _out_T_6805; // @[RegisterRouter.scala:87:24] wire [9:0] hartHaltedId; // @[Debug.scala:876:36] wire out_f_woready_682; // @[RegisterRouter.scala:87:24] wire hartGoingWrEn; // @[Debug.scala:877:36] wire [9:0] _out_T_6814; // @[RegisterRouter.scala:87:24] wire [9:0] hartGoingId; // @[Debug.scala:878:36] wire out_f_woready_498; // @[RegisterRouter.scala:87:24] wire hartResumingWrEn; // @[Debug.scala:879:36] wire [9:0] _out_T_5126; // @[RegisterRouter.scala:87:24] wire [9:0] hartResumingId; // @[Debug.scala:880:36] wire out_f_woready_499; // @[RegisterRouter.scala:87:24] wire hartExceptionWrEn; // @[Debug.scala:881:36] wire [9:0] _out_T_5135; // @[RegisterRouter.scala:87:24] wire [9:0] hartExceptionId; // @[Debug.scala:882:36] wire out_f_roready_101; // @[RegisterRouter.scala:87:24] wire out_f_roready_102; // @[RegisterRouter.scala:87:24] wire out_f_roready_103; // @[RegisterRouter.scala:87:24] wire out_f_roready_104; // @[RegisterRouter.scala:87:24] wire out_f_roready_73; // @[RegisterRouter.scala:87:24] wire out_f_roready_74; // @[RegisterRouter.scala:87:24] wire out_f_roready_75; // @[RegisterRouter.scala:87:24] wire out_f_roready_76; // @[RegisterRouter.scala:87:24] wire out_f_roready_105; // @[RegisterRouter.scala:87:24] wire out_f_roready_106; // @[RegisterRouter.scala:87:24] wire out_f_roready_107; // @[RegisterRouter.scala:87:24] wire out_f_roready_108; // @[RegisterRouter.scala:87:24] wire out_f_roready_13; // @[RegisterRouter.scala:87:24] wire out_f_roready_14; // @[RegisterRouter.scala:87:24] wire out_f_roready_15; // @[RegisterRouter.scala:87:24] wire out_f_roready_16; // @[RegisterRouter.scala:87:24] wire out_f_roready_141; // @[RegisterRouter.scala:87:24] wire out_f_roready_142; // @[RegisterRouter.scala:87:24] wire out_f_roready_143; // @[RegisterRouter.scala:87:24] wire out_f_roready_144; // @[RegisterRouter.scala:87:24] wire out_f_roready_55; // @[RegisterRouter.scala:87:24] wire out_f_roready_56; // @[RegisterRouter.scala:87:24] wire out_f_roready_57; // @[RegisterRouter.scala:87:24] wire out_f_roready_58; // @[RegisterRouter.scala:87:24] wire out_f_roready_69; // @[RegisterRouter.scala:87:24] wire out_f_roready_70; // @[RegisterRouter.scala:87:24] wire out_f_roready_71; // @[RegisterRouter.scala:87:24] wire out_f_roready_72; // @[RegisterRouter.scala:87:24] wire out_f_roready_124; // @[RegisterRouter.scala:87:24] wire out_f_roready_125; // @[RegisterRouter.scala:87:24] wire out_f_roready_126; // @[RegisterRouter.scala:87:24] wire out_f_roready_127; // @[RegisterRouter.scala:87:24] wire out_f_roready_136; // @[RegisterRouter.scala:87:24] wire out_f_roready_137; // @[RegisterRouter.scala:87:24] wire out_f_roready_138; // @[RegisterRouter.scala:87:24] wire out_f_roready_139; // @[RegisterRouter.scala:87:24] wire out_f_roready_9; // @[RegisterRouter.scala:87:24] wire out_f_roready_10; // @[RegisterRouter.scala:87:24] wire out_f_roready_11; // @[RegisterRouter.scala:87:24] wire out_f_roready_12; // @[RegisterRouter.scala:87:24] wire out_f_roready_48; // @[RegisterRouter.scala:87:24] wire out_f_roready_49; // @[RegisterRouter.scala:87:24] wire out_f_roready_50; // @[RegisterRouter.scala:87:24] wire out_f_roready_51; // @[RegisterRouter.scala:87:24] wire out_f_roready_132; // @[RegisterRouter.scala:87:24] wire out_f_roready_133; // @[RegisterRouter.scala:87:24] wire out_f_roready_134; // @[RegisterRouter.scala:87:24] wire out_f_roready_135; // @[RegisterRouter.scala:87:24] wire out_f_roready_116; // @[RegisterRouter.scala:87:24] wire out_f_roready_117; // @[RegisterRouter.scala:87:24] wire out_f_roready_118; // @[RegisterRouter.scala:87:24] wire out_f_roready_119; // @[RegisterRouter.scala:87:24] wire out_f_roready_77; // @[RegisterRouter.scala:87:24] wire out_f_roready_78; // @[RegisterRouter.scala:87:24] wire out_f_roready_79; // @[RegisterRouter.scala:87:24] wire out_f_roready_80; // @[RegisterRouter.scala:87:24] wire out_f_roready_59; // @[RegisterRouter.scala:87:24] wire out_f_roready_60; // @[RegisterRouter.scala:87:24] wire out_f_roready_61; // @[RegisterRouter.scala:87:24] wire out_f_roready_62; // @[RegisterRouter.scala:87:24] wire out_f_roready_25; // @[RegisterRouter.scala:87:24] wire out_f_roready_26; // @[RegisterRouter.scala:87:24] wire out_f_roready_27; // @[RegisterRouter.scala:87:24] wire out_f_roready_28; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_0; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_1; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_2; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_3; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_4; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_5; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_6; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_7; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_8; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_9; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_10; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_11; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_12; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_13; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_14; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_15; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_16; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_17; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_18; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_19; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_20; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_21; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_22; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_23; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_24; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_25; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_26; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_27; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_28; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_29; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_30; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_31; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_32; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_33; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_34; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_35; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_36; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_37; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_38; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_39; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_40; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_41; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_42; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_43; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_44; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_45; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_46; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_47; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_48; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_49; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_50; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_51; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_52; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_53; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_54; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_55; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_56; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_57; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_58; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_59; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_60; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_61; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_62; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_63; // @[Debug.scala:887:40] wire _dmiProgramBufferAccessLegal_T; // @[Debug.scala:1746:50] wire dmiProgramBufferAccessLegal; // @[Debug.scala:888:47] wire out_f_woready_101; // @[RegisterRouter.scala:87:24] wire out_f_woready_102; // @[RegisterRouter.scala:87:24] wire out_f_woready_103; // @[RegisterRouter.scala:87:24] wire out_f_woready_104; // @[RegisterRouter.scala:87:24] wire out_f_woready_73; // @[RegisterRouter.scala:87:24] wire out_f_woready_74; // @[RegisterRouter.scala:87:24] wire out_f_woready_75; // @[RegisterRouter.scala:87:24] wire out_f_woready_76; // @[RegisterRouter.scala:87:24] wire out_f_woready_105; // @[RegisterRouter.scala:87:24] wire out_f_woready_106; // @[RegisterRouter.scala:87:24] wire out_f_woready_107; // @[RegisterRouter.scala:87:24] wire out_f_woready_108; // @[RegisterRouter.scala:87:24] wire out_f_woready_13; // @[RegisterRouter.scala:87:24] wire out_f_woready_14; // @[RegisterRouter.scala:87:24] wire out_f_woready_15; // @[RegisterRouter.scala:87:24] wire out_f_woready_16; // @[RegisterRouter.scala:87:24] wire out_f_woready_141; // @[RegisterRouter.scala:87:24] wire out_f_woready_142; // @[RegisterRouter.scala:87:24] wire out_f_woready_143; // @[RegisterRouter.scala:87:24] wire out_f_woready_144; // @[RegisterRouter.scala:87:24] wire out_f_woready_55; // @[RegisterRouter.scala:87:24] wire out_f_woready_56; // @[RegisterRouter.scala:87:24] wire out_f_woready_57; // @[RegisterRouter.scala:87:24] wire out_f_woready_58; // @[RegisterRouter.scala:87:24] wire out_f_woready_69; // @[RegisterRouter.scala:87:24] wire out_f_woready_70; // @[RegisterRouter.scala:87:24] wire out_f_woready_71; // @[RegisterRouter.scala:87:24] wire out_f_woready_72; // @[RegisterRouter.scala:87:24] wire out_f_woready_124; // @[RegisterRouter.scala:87:24] wire out_f_woready_125; // @[RegisterRouter.scala:87:24] wire out_f_woready_126; // @[RegisterRouter.scala:87:24] wire out_f_woready_127; // @[RegisterRouter.scala:87:24] wire out_f_woready_136; // @[RegisterRouter.scala:87:24] wire out_f_woready_137; // @[RegisterRouter.scala:87:24] wire out_f_woready_138; // @[RegisterRouter.scala:87:24] wire out_f_woready_139; // @[RegisterRouter.scala:87:24] wire out_f_woready_9; // @[RegisterRouter.scala:87:24] wire out_f_woready_10; // @[RegisterRouter.scala:87:24] wire out_f_woready_11; // @[RegisterRouter.scala:87:24] wire out_f_woready_12; // @[RegisterRouter.scala:87:24] wire out_f_woready_48; // @[RegisterRouter.scala:87:24] wire out_f_woready_49; // @[RegisterRouter.scala:87:24] wire out_f_woready_50; // @[RegisterRouter.scala:87:24] wire out_f_woready_51; // @[RegisterRouter.scala:87:24] wire out_f_woready_132; // @[RegisterRouter.scala:87:24] wire out_f_woready_133; // @[RegisterRouter.scala:87:24] wire out_f_woready_134; // @[RegisterRouter.scala:87:24] wire out_f_woready_135; // @[RegisterRouter.scala:87:24] wire out_f_woready_116; // @[RegisterRouter.scala:87:24] wire out_f_woready_117; // @[RegisterRouter.scala:87:24] wire out_f_woready_118; // @[RegisterRouter.scala:87:24] wire out_f_woready_119; // @[RegisterRouter.scala:87:24] wire out_f_woready_77; // @[RegisterRouter.scala:87:24] wire out_f_woready_78; // @[RegisterRouter.scala:87:24] wire out_f_woready_79; // @[RegisterRouter.scala:87:24] wire out_f_woready_80; // @[RegisterRouter.scala:87:24] wire out_f_woready_59; // @[RegisterRouter.scala:87:24] wire out_f_woready_60; // @[RegisterRouter.scala:87:24] wire out_f_woready_61; // @[RegisterRouter.scala:87:24] wire out_f_woready_62; // @[RegisterRouter.scala:87:24] wire out_f_woready_25; // @[RegisterRouter.scala:87:24] wire out_f_woready_26; // @[RegisterRouter.scala:87:24] wire out_f_woready_27; // @[RegisterRouter.scala:87:24] wire out_f_woready_28; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_0; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_1; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_2; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_3; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_4; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_5; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_6; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_7; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_8; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_9; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_10; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_11; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_12; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_13; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_14; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_15; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_16; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_17; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_18; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_19; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_20; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_21; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_22; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_23; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_24; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_25; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_26; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_27; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_28; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_29; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_30; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_31; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_32; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_33; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_34; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_35; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_36; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_37; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_38; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_39; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_40; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_41; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_42; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_43; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_44; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_45; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_46; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_47; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_48; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_49; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_50; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_51; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_52; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_53; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_54; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_55; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_56; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_57; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_58; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_59; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_60; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_61; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_62; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_63; // @[Debug.scala:889:45] wire out_f_roready_21; // @[RegisterRouter.scala:87:24] wire out_f_roready_22; // @[RegisterRouter.scala:87:24] wire out_f_roready_23; // @[RegisterRouter.scala:87:24] wire out_f_roready_24; // @[RegisterRouter.scala:87:24] wire out_f_roready; // @[RegisterRouter.scala:87:24] wire out_f_roready_1; // @[RegisterRouter.scala:87:24] wire out_f_roready_2; // @[RegisterRouter.scala:87:24] wire out_f_roready_3; // @[RegisterRouter.scala:87:24] wire out_f_roready_64; // @[RegisterRouter.scala:87:24] wire out_f_roready_65; // @[RegisterRouter.scala:87:24] wire out_f_roready_66; // @[RegisterRouter.scala:87:24] wire out_f_roready_67; // @[RegisterRouter.scala:87:24] wire out_f_roready_120; // @[RegisterRouter.scala:87:24] wire out_f_roready_121; // @[RegisterRouter.scala:87:24] wire out_f_roready_122; // @[RegisterRouter.scala:87:24] wire out_f_roready_123; // @[RegisterRouter.scala:87:24] wire out_f_roready_17; // @[RegisterRouter.scala:87:24] wire out_f_roready_18; // @[RegisterRouter.scala:87:24] wire out_f_roready_19; // @[RegisterRouter.scala:87:24] wire out_f_roready_20; // @[RegisterRouter.scala:87:24] wire out_f_roready_5; // @[RegisterRouter.scala:87:24] wire out_f_roready_6; // @[RegisterRouter.scala:87:24] wire out_f_roready_7; // @[RegisterRouter.scala:87:24] wire out_f_roready_8; // @[RegisterRouter.scala:87:24] wire out_f_roready_29; // @[RegisterRouter.scala:87:24] wire out_f_roready_30; // @[RegisterRouter.scala:87:24] wire out_f_roready_31; // @[RegisterRouter.scala:87:24] wire out_f_roready_32; // @[RegisterRouter.scala:87:24] wire out_f_roready_128; // @[RegisterRouter.scala:87:24] wire out_f_roready_129; // @[RegisterRouter.scala:87:24] wire out_f_roready_130; // @[RegisterRouter.scala:87:24] wire out_f_roready_131; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataRdEn_0; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_1; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_2; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_3; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_4; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_5; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_6; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_7; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_8; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_9; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_10; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_11; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_12; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_13; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_14; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_15; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_16; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_17; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_18; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_19; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_20; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_21; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_22; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_23; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_24; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_25; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_26; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_27; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_28; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_29; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_30; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_31; // @[Debug.scala:891:39] wire _dmiAbstractDataAccessLegal_T; // @[Debug.scala:1745:50] wire dmiAbstractDataAccessLegal; // @[Debug.scala:892:46] wire out_f_woready_21; // @[RegisterRouter.scala:87:24] wire out_f_woready_22; // @[RegisterRouter.scala:87:24] wire out_f_woready_23; // @[RegisterRouter.scala:87:24] wire out_f_woready_24; // @[RegisterRouter.scala:87:24] wire out_f_woready; // @[RegisterRouter.scala:87:24] wire out_f_woready_1; // @[RegisterRouter.scala:87:24] wire out_f_woready_2; // @[RegisterRouter.scala:87:24] wire out_f_woready_3; // @[RegisterRouter.scala:87:24] wire out_f_woready_64; // @[RegisterRouter.scala:87:24] wire out_f_woready_65; // @[RegisterRouter.scala:87:24] wire out_f_woready_66; // @[RegisterRouter.scala:87:24] wire out_f_woready_67; // @[RegisterRouter.scala:87:24] wire out_f_woready_120; // @[RegisterRouter.scala:87:24] wire out_f_woready_121; // @[RegisterRouter.scala:87:24] wire out_f_woready_122; // @[RegisterRouter.scala:87:24] wire out_f_woready_123; // @[RegisterRouter.scala:87:24] wire out_f_woready_17; // @[RegisterRouter.scala:87:24] wire out_f_woready_18; // @[RegisterRouter.scala:87:24] wire out_f_woready_19; // @[RegisterRouter.scala:87:24] wire out_f_woready_20; // @[RegisterRouter.scala:87:24] wire out_f_woready_5; // @[RegisterRouter.scala:87:24] wire out_f_woready_6; // @[RegisterRouter.scala:87:24] wire out_f_woready_7; // @[RegisterRouter.scala:87:24] wire out_f_woready_8; // @[RegisterRouter.scala:87:24] wire out_f_woready_29; // @[RegisterRouter.scala:87:24] wire out_f_woready_30; // @[RegisterRouter.scala:87:24] wire out_f_woready_31; // @[RegisterRouter.scala:87:24] wire out_f_woready_32; // @[RegisterRouter.scala:87:24] wire out_f_woready_128; // @[RegisterRouter.scala:87:24] wire out_f_woready_129; // @[RegisterRouter.scala:87:24] wire out_f_woready_130; // @[RegisterRouter.scala:87:24] wire out_f_woready_131; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataWrEnMaybe_0; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_1; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_2; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_3; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_4; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_5; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_6; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_7; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_8; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_9; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_10; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_11; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_12; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_13; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_14; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_15; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_16; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_17; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_18; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_19; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_20; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_21; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_22; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_23; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_24; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_25; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_26; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_27; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_28; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_29; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_30; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_31; // @[Debug.scala:893:44] wire _hamaskWrSel_0_T_1; // @[Debug.scala:935:78] wire hamaskWrSel_0; // @[Debug.scala:933:31] wire _hamaskWrSel_0_T = io_innerCtrl_bits_hartsel_0 == 10'h0; // @[Debug.scala:790:9, :935:61] assign _hamaskWrSel_0_T_1 = _hamaskWrSel_0_T; // @[Debug.scala:935:{61,78}] assign hamaskWrSel_0 = _hamaskWrSel_0_T_1; // @[Debug.scala:933:31, :935:78] assign io_hgDebugInt_0_0 = hrDebugInt_0; // @[Debug.scala:790:9, :946:26] reg hrmaskReg_0; // @[Debug.scala:947:29] wire _hartIsInResetSync_0_WIRE; // @[ShiftReg.scala:48:24] wire hartIsInResetSync_0; // @[Debug.scala:948:33] assign hartIsInResetSync_0 = _hartIsInResetSync_0_WIRE; // @[ShiftReg.scala:48:24] reg hrDebugIntReg_0; // @[Debug.scala:961:34] assign hrDebugInt_0 = hrDebugIntReg_0; // @[Debug.scala:946:26, :961:34] wire _DMSTATUSRdData_allnonexistent_T_2; // @[Debug.scala:991:75] wire DMSTATUSRdData_allhavereset; // @[Debug.scala:978:34] wire DMSTATUSRdData_anyhavereset; // @[Debug.scala:978:34] wire DMSTATUSRdData_allresumeack; // @[Debug.scala:978:34] wire DMSTATUSRdData_anyresumeack; // @[Debug.scala:978:34] wire DMSTATUSRdData_allnonexistent; // @[Debug.scala:978:34] wire DMSTATUSRdData_anynonexistent; // @[Debug.scala:978:34] wire DMSTATUSRdData_allunavail; // @[Debug.scala:978:34] wire DMSTATUSRdData_allrunning; // @[Debug.scala:978:34] wire DMSTATUSRdData_anyrunning; // @[Debug.scala:978:34] wire DMSTATUSRdData_allhalted; // @[Debug.scala:978:34] wire DMSTATUSRdData_anyhalted; // @[Debug.scala:978:34] wire resumereq = _resumereq_T & io_innerCtrl_bits_resumereq_0; // @[Decoupled.scala:51:35] assign DMSTATUSRdData_anynonexistent = _DMSTATUSRdData_anynonexistent_T; // @[Debug.scala:978:34, :988:57] wire _DMSTATUSRdData_allnonexistent_T_1 = ~hamaskFull_0; // @[Debug.scala:903:30, :991:78] assign _DMSTATUSRdData_allnonexistent_T_2 = _DMSTATUSRdData_allnonexistent_T & _DMSTATUSRdData_allnonexistent_T_1; // @[Debug.scala:991:{57,75,78}] assign DMSTATUSRdData_allnonexistent = _DMSTATUSRdData_allnonexistent_T_2; // @[Debug.scala:978:34, :991:75] wire _DMSTATUSRdData_anyhalted_T_2 = _DMSTATUSRdData_anyhalted_T_1; // @[package.scala:74:72] wire _DMSTATUSRdData_anyhalted_T_3 = _DMSTATUSRdData_anyhalted_T_2 & hamaskFull_0; // @[package.scala:74:72] assign DMSTATUSRdData_anyhalted = ~DMSTATUSRdData_allnonexistent & _DMSTATUSRdData_anyhalted_T_3; // @[package.scala:74:72] wire _DMSTATUSRdData_anyrunning_T_2 = ~_DMSTATUSRdData_anyrunning_T_1; // @[package.scala:79:37] wire _DMSTATUSRdData_anyrunning_T_3 = _DMSTATUSRdData_anyrunning_T_2; // @[package.scala:74:72, :79:37] wire _DMSTATUSRdData_anyrunning_T_4 = _DMSTATUSRdData_anyrunning_T_3 & hamaskFull_0; // @[package.scala:74:72] assign DMSTATUSRdData_anyrunning = ~DMSTATUSRdData_allnonexistent & _DMSTATUSRdData_anyrunning_T_4; // @[package.scala:74:72] wire _DMSTATUSRdData_anyhavereset_T_1 = _DMSTATUSRdData_anyhavereset_T & hamaskFull_0; // @[package.scala:74:72] assign DMSTATUSRdData_anyhavereset = ~DMSTATUSRdData_allnonexistent & _DMSTATUSRdData_anyhavereset_T_1; // @[package.scala:74:72] wire _DMSTATUSRdData_anyresumeack_T_1 = _DMSTATUSRdData_anyresumeack_T & hamaskFull_0; // @[package.scala:74:72] assign DMSTATUSRdData_anyresumeack = ~DMSTATUSRdData_allnonexistent & _DMSTATUSRdData_anyresumeack_T_1; // @[package.scala:74:72] wire _DMSTATUSRdData_allunavail_T = ~hamaskFull_0; // @[package.scala:79:37] wire _DMSTATUSRdData_allunavail_T_1 = _DMSTATUSRdData_allunavail_T; // @[package.scala:75:75, :79:37] wire _GEN = ~DMSTATUSRdData_allnonexistent & ~DMSTATUSRdData_anynonexistent; // @[Debug.scala:978:34, :993:{13,45}, :999:{15,47}, :1000:39] assign DMSTATUSRdData_allunavail = _GEN & _DMSTATUSRdData_allunavail_T_1; // @[package.scala:75:75] wire _DMSTATUSRdData_allhalted_T_2 = _DMSTATUSRdData_allhalted_T_1; // @[package.scala:74:72] wire _DMSTATUSRdData_allhalted_T_3 = ~hamaskFull_0; // @[package.scala:79:37] wire _DMSTATUSRdData_allhalted_T_4 = _DMSTATUSRdData_allhalted_T_2 | _DMSTATUSRdData_allhalted_T_3; // @[package.scala:74:72, :75:75, :79:37] assign DMSTATUSRdData_allhalted = _GEN & _DMSTATUSRdData_allhalted_T_4; // @[package.scala:75:75] wire _DMSTATUSRdData_allrunning_T_2 = ~_DMSTATUSRdData_allrunning_T_1; // @[package.scala:79:37] wire _DMSTATUSRdData_allrunning_T_3 = _DMSTATUSRdData_allrunning_T_2; // @[package.scala:74:72, :79:37] wire _DMSTATUSRdData_allrunning_T_4 = ~hamaskFull_0; // @[package.scala:79:37] wire _DMSTATUSRdData_allrunning_T_5 = _DMSTATUSRdData_allrunning_T_3 | _DMSTATUSRdData_allrunning_T_4; // @[package.scala:74:72, :75:75, :79:37] assign DMSTATUSRdData_allrunning = _GEN & _DMSTATUSRdData_allrunning_T_5; // @[package.scala:75:75] wire _DMSTATUSRdData_allhavereset_T_1 = ~hamaskFull_0; // @[package.scala:79:37] wire _DMSTATUSRdData_allhavereset_T_2 = _DMSTATUSRdData_allhavereset_T | _DMSTATUSRdData_allhavereset_T_1; // @[package.scala:75:75, :79:37] assign DMSTATUSRdData_allhavereset = _GEN & _DMSTATUSRdData_allhavereset_T_2; // @[package.scala:75:75] wire _DMSTATUSRdData_allresumeack_T_1 = ~hamaskFull_0; // @[package.scala:79:37] wire _DMSTATUSRdData_allresumeack_T_2 = _DMSTATUSRdData_allresumeack_T | _DMSTATUSRdData_allresumeack_T_1; // @[package.scala:75:75, :79:37] assign DMSTATUSRdData_allresumeack = _GEN & _DMSTATUSRdData_allresumeack_T_2; // @[package.scala:75:75] wire _haveResetBitRegs_T = ~hamaskWrSel_0; // @[Debug.scala:933:31, :1017:50] wire _haveResetBitRegs_T_1 = haveResetBitRegs & _haveResetBitRegs_T; // @[Debug.scala:865:31, :1017:{47,50}] wire _haveResetBitRegs_T_2 = _haveResetBitRegs_T_1 | hartIsInResetSync_0; // @[Debug.scala:948:33, :1017:{47,74}] wire _haveResetBitRegs_T_3 = haveResetBitRegs | hartIsInResetSync_0; // @[Debug.scala:865:31, :948:33, :1019:46] wire [31:0] haltedStatus_0; // @[Debug.scala:1159:30] wire [31:0] selectedHaltedStatus = haltedStatus_0; // @[Debug.scala:1159:30, :1172:35] assign haltedStatus_0 = {31'h0, _haltedStatus_0_T}; // @[Debug.scala:1159:30, :1163:{26,43}] wire haltedSummary = |haltedStatus_0; // @[Debug.scala:1159:30, :1169:48] wire [31:0] _HALTSUM1RdData_T; // @[Debug.scala:1170:48] wire [31:0] HALTSUM1RdData_haltsum1; // @[Debug.scala:1170:48] wire [31:0] _out_T_1598 = HALTSUM1RdData_haltsum1; // @[RegisterRouter.scala:87:24] assign _HALTSUM1RdData_T = _HALTSUM1RdData_WIRE; // @[Debug.scala:1170:48] assign _HALTSUM1RdData_WIRE = {31'h0, haltedSummary}; // @[Debug.scala:1169:48, :1170:48] assign HALTSUM1RdData_haltsum1 = _HALTSUM1RdData_T; // @[Debug.scala:1170:48] wire [31:0] _HALTSUM0RdData_WIRE = selectedHaltedStatus; // @[Debug.scala:1172:35, :1173:55] wire [31:0] _HALTSUM0RdData_T; // @[Debug.scala:1173:55] wire [31:0] HALTSUM0RdData_haltsum0; // @[Debug.scala:1173:55] wire [31:0] _out_T_946 = HALTSUM0RdData_haltsum0; // @[RegisterRouter.scala:87:24] assign _HALTSUM0RdData_T = _HALTSUM0RdData_WIRE; // @[Debug.scala:1173:55] assign HALTSUM0RdData_haltsum0 = _HALTSUM0RdData_T; // @[Debug.scala:1173:55] reg [2:0] ABSTRACTCSReg_cmderr; // @[Debug.scala:1183:34] wire [2:0] ABSTRACTCSRdData_cmderr = ABSTRACTCSReg_cmderr; // @[Debug.scala:1183:34, :1185:39] wire [2:0] _out_T_1225; // @[RegisterRouter.scala:87:24] wire [2:0] ABSTRACTCSWrData_cmderr; // @[Debug.scala:1184:39] wire abstractCommandBusy; // @[Debug.scala:1220:39] wire ABSTRACTCSRdData_busy; // @[Debug.scala:1185:39] wire out_f_woready_111; // @[RegisterRouter.scala:87:24] wire ABSTRACTCSWrEnMaybe; // @[Debug.scala:1188:39] wire _ABSTRACTCSWrEnLegal_T; // @[Debug.scala:1742:44] wire ABSTRACTCSWrEnLegal; // @[Debug.scala:1190:39] wire ABSTRACTCSWrEn = ABSTRACTCSWrEnMaybe & ABSTRACTCSWrEnLegal; // @[Debug.scala:1188:39, :1190:39, :1191:51] wire _errorBusy_T_16; // @[Debug.scala:1752:74] wire errorBusy; // @[Debug.scala:1195:36] wire errorException; // @[Debug.scala:1196:36] wire errorUnsupported; // @[Debug.scala:1197:36] wire errorHaltResume; // @[Debug.scala:1198:36] wire [2:0] _ABSTRACTCSReg_cmderr_T = ~ABSTRACTCSWrData_cmderr; // @[Debug.scala:1184:39, :1214:58] wire [2:0] _ABSTRACTCSReg_cmderr_T_1 = ABSTRACTCSReg_cmderr & _ABSTRACTCSReg_cmderr_T; // @[Debug.scala:1183:34, :1214:{56,58}] wire _abstractCommandBusy_T; // @[Debug.scala:1740:42] assign ABSTRACTCSRdData_busy = abstractCommandBusy; // @[Debug.scala:1185:39, :1220:39] reg [15:0] ABSTRACTAUTOReg_autoexecprogbuf; // @[Debug.scala:1235:36] wire [15:0] ABSTRACTAUTORdData_autoexecprogbuf = ABSTRACTAUTOReg_autoexecprogbuf; // @[Debug.scala:1235:36, :1237:41] reg [11:0] ABSTRACTAUTOReg_autoexecdata; // @[Debug.scala:1235:36] wire [11:0] ABSTRACTAUTORdData_autoexecdata = ABSTRACTAUTOReg_autoexecdata; // @[Debug.scala:1235:36, :1237:41] wire [15:0] _out_T_642; // @[RegisterRouter.scala:87:24] wire [15:0] _ABSTRACTAUTOReg_autoexecprogbuf_T = ABSTRACTAUTOWrData_autoexecprogbuf; // @[Debug.scala:1236:41, :1249:79] wire [11:0] ABSTRACTAUTOWrData_autoexecdata; // @[Debug.scala:1236:41] wire [11:0] _out_T_631 = ABSTRACTAUTORdData_autoexecdata; // @[RegisterRouter.scala:87:24] wire out_f_woready_52; // @[RegisterRouter.scala:87:24] wire autoexecdataWrEnMaybe; // @[Debug.scala:1240:41] wire out_f_woready_54; // @[RegisterRouter.scala:87:24] wire autoexecprogbufWrEnMaybe; // @[Debug.scala:1241:44] wire _ABSTRACTAUTOWrEnLegal_T; // @[Debug.scala:1744:44] wire ABSTRACTAUTOWrEnLegal; // @[Debug.scala:1243:41] wire [11:0] _ABSTRACTAUTOReg_autoexecdata_T = {4'h0, ABSTRACTAUTOWrData_autoexecdata[7:0]}; // @[Debug.scala:1236:41, :1252:73] wire dmiAbstractDataAccessVec_0; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_1; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_2; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_3; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_4; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_5; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_6; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_7; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_8; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_9; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_10; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_11; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_12; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_13; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_14; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_15; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_16; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_17; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_18; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_19; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_20; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_21; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_22; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_23; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_24; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_25; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_26; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_27; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_28; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_29; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_30; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_31; // @[Debug.scala:1257:45] assign dmiAbstractDataAccessVec_0 = dmiAbstractDataWrEnMaybe_0 | dmiAbstractDataRdEn_0; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_1 = dmiAbstractDataWrEnMaybe_1 | dmiAbstractDataRdEn_1; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_2 = dmiAbstractDataWrEnMaybe_2 | dmiAbstractDataRdEn_2; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_3 = dmiAbstractDataWrEnMaybe_3 | dmiAbstractDataRdEn_3; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_4 = dmiAbstractDataWrEnMaybe_4 | dmiAbstractDataRdEn_4; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_5 = dmiAbstractDataWrEnMaybe_5 | dmiAbstractDataRdEn_5; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_6 = dmiAbstractDataWrEnMaybe_6 | dmiAbstractDataRdEn_6; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_7 = dmiAbstractDataWrEnMaybe_7 | dmiAbstractDataRdEn_7; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_8 = dmiAbstractDataWrEnMaybe_8 | dmiAbstractDataRdEn_8; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_9 = dmiAbstractDataWrEnMaybe_9 | dmiAbstractDataRdEn_9; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_10 = dmiAbstractDataWrEnMaybe_10 | dmiAbstractDataRdEn_10; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_11 = dmiAbstractDataWrEnMaybe_11 | dmiAbstractDataRdEn_11; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_12 = dmiAbstractDataWrEnMaybe_12 | dmiAbstractDataRdEn_12; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_13 = dmiAbstractDataWrEnMaybe_13 | dmiAbstractDataRdEn_13; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_14 = dmiAbstractDataWrEnMaybe_14 | dmiAbstractDataRdEn_14; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_15 = dmiAbstractDataWrEnMaybe_15 | dmiAbstractDataRdEn_15; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_16 = dmiAbstractDataWrEnMaybe_16 | dmiAbstractDataRdEn_16; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_17 = dmiAbstractDataWrEnMaybe_17 | dmiAbstractDataRdEn_17; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_18 = dmiAbstractDataWrEnMaybe_18 | dmiAbstractDataRdEn_18; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_19 = dmiAbstractDataWrEnMaybe_19 | dmiAbstractDataRdEn_19; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_20 = dmiAbstractDataWrEnMaybe_20 | dmiAbstractDataRdEn_20; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_21 = dmiAbstractDataWrEnMaybe_21 | dmiAbstractDataRdEn_21; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_22 = dmiAbstractDataWrEnMaybe_22 | dmiAbstractDataRdEn_22; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_23 = dmiAbstractDataWrEnMaybe_23 | dmiAbstractDataRdEn_23; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_24 = dmiAbstractDataWrEnMaybe_24 | dmiAbstractDataRdEn_24; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_25 = dmiAbstractDataWrEnMaybe_25 | dmiAbstractDataRdEn_25; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_26 = dmiAbstractDataWrEnMaybe_26 | dmiAbstractDataRdEn_26; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_27 = dmiAbstractDataWrEnMaybe_27 | dmiAbstractDataRdEn_27; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_28 = dmiAbstractDataWrEnMaybe_28 | dmiAbstractDataRdEn_28; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_29 = dmiAbstractDataWrEnMaybe_29 | dmiAbstractDataRdEn_29; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_30 = dmiAbstractDataWrEnMaybe_30 | dmiAbstractDataRdEn_30; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_31 = dmiAbstractDataWrEnMaybe_31 | dmiAbstractDataRdEn_31; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] wire dmiProgramBufferAccessVec_0; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_1; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_2; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_3; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_4; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_5; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_6; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_7; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_8; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_9; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_10; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_11; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_12; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_13; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_14; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_15; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_16; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_17; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_18; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_19; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_20; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_21; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_22; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_23; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_24; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_25; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_26; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_27; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_28; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_29; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_30; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_31; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_32; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_33; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_34; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_35; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_36; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_37; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_38; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_39; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_40; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_41; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_42; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_43; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_44; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_45; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_46; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_47; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_48; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_49; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_50; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_51; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_52; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_53; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_54; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_55; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_56; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_57; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_58; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_59; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_60; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_61; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_62; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_63; // @[Debug.scala:1260:46] assign dmiProgramBufferAccessVec_0 = dmiProgramBufferWrEnMaybe_0 | dmiProgramBufferRdEn_0; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_1 = dmiProgramBufferWrEnMaybe_1 | dmiProgramBufferRdEn_1; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_2 = dmiProgramBufferWrEnMaybe_2 | dmiProgramBufferRdEn_2; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_3 = dmiProgramBufferWrEnMaybe_3 | dmiProgramBufferRdEn_3; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_4 = dmiProgramBufferWrEnMaybe_4 | dmiProgramBufferRdEn_4; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_5 = dmiProgramBufferWrEnMaybe_5 | dmiProgramBufferRdEn_5; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_6 = dmiProgramBufferWrEnMaybe_6 | dmiProgramBufferRdEn_6; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_7 = dmiProgramBufferWrEnMaybe_7 | dmiProgramBufferRdEn_7; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_8 = dmiProgramBufferWrEnMaybe_8 | dmiProgramBufferRdEn_8; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_9 = dmiProgramBufferWrEnMaybe_9 | dmiProgramBufferRdEn_9; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_10 = dmiProgramBufferWrEnMaybe_10 | dmiProgramBufferRdEn_10; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_11 = dmiProgramBufferWrEnMaybe_11 | dmiProgramBufferRdEn_11; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_12 = dmiProgramBufferWrEnMaybe_12 | dmiProgramBufferRdEn_12; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_13 = dmiProgramBufferWrEnMaybe_13 | dmiProgramBufferRdEn_13; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_14 = dmiProgramBufferWrEnMaybe_14 | dmiProgramBufferRdEn_14; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_15 = dmiProgramBufferWrEnMaybe_15 | dmiProgramBufferRdEn_15; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_16 = dmiProgramBufferWrEnMaybe_16 | dmiProgramBufferRdEn_16; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_17 = dmiProgramBufferWrEnMaybe_17 | dmiProgramBufferRdEn_17; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_18 = dmiProgramBufferWrEnMaybe_18 | dmiProgramBufferRdEn_18; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_19 = dmiProgramBufferWrEnMaybe_19 | dmiProgramBufferRdEn_19; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_20 = dmiProgramBufferWrEnMaybe_20 | dmiProgramBufferRdEn_20; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_21 = dmiProgramBufferWrEnMaybe_21 | dmiProgramBufferRdEn_21; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_22 = dmiProgramBufferWrEnMaybe_22 | dmiProgramBufferRdEn_22; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_23 = dmiProgramBufferWrEnMaybe_23 | dmiProgramBufferRdEn_23; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_24 = dmiProgramBufferWrEnMaybe_24 | dmiProgramBufferRdEn_24; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_25 = dmiProgramBufferWrEnMaybe_25 | dmiProgramBufferRdEn_25; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_26 = dmiProgramBufferWrEnMaybe_26 | dmiProgramBufferRdEn_26; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_27 = dmiProgramBufferWrEnMaybe_27 | dmiProgramBufferRdEn_27; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_28 = dmiProgramBufferWrEnMaybe_28 | dmiProgramBufferRdEn_28; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_29 = dmiProgramBufferWrEnMaybe_29 | dmiProgramBufferRdEn_29; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_30 = dmiProgramBufferWrEnMaybe_30 | dmiProgramBufferRdEn_30; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_31 = dmiProgramBufferWrEnMaybe_31 | dmiProgramBufferRdEn_31; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_32 = dmiProgramBufferWrEnMaybe_32 | dmiProgramBufferRdEn_32; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_33 = dmiProgramBufferWrEnMaybe_33 | dmiProgramBufferRdEn_33; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_34 = dmiProgramBufferWrEnMaybe_34 | dmiProgramBufferRdEn_34; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_35 = dmiProgramBufferWrEnMaybe_35 | dmiProgramBufferRdEn_35; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_36 = dmiProgramBufferWrEnMaybe_36 | dmiProgramBufferRdEn_36; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_37 = dmiProgramBufferWrEnMaybe_37 | dmiProgramBufferRdEn_37; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_38 = dmiProgramBufferWrEnMaybe_38 | dmiProgramBufferRdEn_38; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_39 = dmiProgramBufferWrEnMaybe_39 | dmiProgramBufferRdEn_39; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_40 = dmiProgramBufferWrEnMaybe_40 | dmiProgramBufferRdEn_40; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_41 = dmiProgramBufferWrEnMaybe_41 | dmiProgramBufferRdEn_41; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_42 = dmiProgramBufferWrEnMaybe_42 | dmiProgramBufferRdEn_42; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_43 = dmiProgramBufferWrEnMaybe_43 | dmiProgramBufferRdEn_43; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_44 = dmiProgramBufferWrEnMaybe_44 | dmiProgramBufferRdEn_44; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_45 = dmiProgramBufferWrEnMaybe_45 | dmiProgramBufferRdEn_45; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_46 = dmiProgramBufferWrEnMaybe_46 | dmiProgramBufferRdEn_46; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_47 = dmiProgramBufferWrEnMaybe_47 | dmiProgramBufferRdEn_47; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_48 = dmiProgramBufferWrEnMaybe_48 | dmiProgramBufferRdEn_48; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_49 = dmiProgramBufferWrEnMaybe_49 | dmiProgramBufferRdEn_49; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_50 = dmiProgramBufferWrEnMaybe_50 | dmiProgramBufferRdEn_50; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_51 = dmiProgramBufferWrEnMaybe_51 | dmiProgramBufferRdEn_51; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_52 = dmiProgramBufferWrEnMaybe_52 | dmiProgramBufferRdEn_52; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_53 = dmiProgramBufferWrEnMaybe_53 | dmiProgramBufferRdEn_53; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_54 = dmiProgramBufferWrEnMaybe_54 | dmiProgramBufferRdEn_54; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_55 = dmiProgramBufferWrEnMaybe_55 | dmiProgramBufferRdEn_55; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_56 = dmiProgramBufferWrEnMaybe_56 | dmiProgramBufferRdEn_56; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_57 = dmiProgramBufferWrEnMaybe_57 | dmiProgramBufferRdEn_57; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_58 = dmiProgramBufferWrEnMaybe_58 | dmiProgramBufferRdEn_58; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_59 = dmiProgramBufferWrEnMaybe_59 | dmiProgramBufferRdEn_59; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_60 = dmiProgramBufferWrEnMaybe_60 | dmiProgramBufferRdEn_60; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_61 = dmiProgramBufferWrEnMaybe_61 | dmiProgramBufferRdEn_61; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_62 = dmiProgramBufferWrEnMaybe_62 | dmiProgramBufferRdEn_62; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_63 = dmiProgramBufferWrEnMaybe_63 | dmiProgramBufferRdEn_63; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] wire _dmiAbstractDataAccess_T = dmiAbstractDataAccessVec_0 | dmiAbstractDataAccessVec_1; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_1 = _dmiAbstractDataAccess_T | dmiAbstractDataAccessVec_2; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_2 = _dmiAbstractDataAccess_T_1 | dmiAbstractDataAccessVec_3; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_3 = _dmiAbstractDataAccess_T_2 | dmiAbstractDataAccessVec_4; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_4 = _dmiAbstractDataAccess_T_3 | dmiAbstractDataAccessVec_5; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_5 = _dmiAbstractDataAccess_T_4 | dmiAbstractDataAccessVec_6; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_6 = _dmiAbstractDataAccess_T_5 | dmiAbstractDataAccessVec_7; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_7 = _dmiAbstractDataAccess_T_6 | dmiAbstractDataAccessVec_8; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_8 = _dmiAbstractDataAccess_T_7 | dmiAbstractDataAccessVec_9; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_9 = _dmiAbstractDataAccess_T_8 | dmiAbstractDataAccessVec_10; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_10 = _dmiAbstractDataAccess_T_9 | dmiAbstractDataAccessVec_11; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_11 = _dmiAbstractDataAccess_T_10 | dmiAbstractDataAccessVec_12; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_12 = _dmiAbstractDataAccess_T_11 | dmiAbstractDataAccessVec_13; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_13 = _dmiAbstractDataAccess_T_12 | dmiAbstractDataAccessVec_14; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_14 = _dmiAbstractDataAccess_T_13 | dmiAbstractDataAccessVec_15; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_15 = _dmiAbstractDataAccess_T_14 | dmiAbstractDataAccessVec_16; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_16 = _dmiAbstractDataAccess_T_15 | dmiAbstractDataAccessVec_17; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_17 = _dmiAbstractDataAccess_T_16 | dmiAbstractDataAccessVec_18; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_18 = _dmiAbstractDataAccess_T_17 | dmiAbstractDataAccessVec_19; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_19 = _dmiAbstractDataAccess_T_18 | dmiAbstractDataAccessVec_20; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_20 = _dmiAbstractDataAccess_T_19 | dmiAbstractDataAccessVec_21; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_21 = _dmiAbstractDataAccess_T_20 | dmiAbstractDataAccessVec_22; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_22 = _dmiAbstractDataAccess_T_21 | dmiAbstractDataAccessVec_23; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_23 = _dmiAbstractDataAccess_T_22 | dmiAbstractDataAccessVec_24; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_24 = _dmiAbstractDataAccess_T_23 | dmiAbstractDataAccessVec_25; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_25 = _dmiAbstractDataAccess_T_24 | dmiAbstractDataAccessVec_26; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_26 = _dmiAbstractDataAccess_T_25 | dmiAbstractDataAccessVec_27; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_27 = _dmiAbstractDataAccess_T_26 | dmiAbstractDataAccessVec_28; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_28 = _dmiAbstractDataAccess_T_27 | dmiAbstractDataAccessVec_29; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_29 = _dmiAbstractDataAccess_T_28 | dmiAbstractDataAccessVec_30; // @[Debug.scala:1257:45, :1263:68] wire dmiAbstractDataAccess = _dmiAbstractDataAccess_T_29 | dmiAbstractDataAccessVec_31; // @[Debug.scala:1257:45, :1263:68] wire _dmiProgramBufferAccess_T = dmiProgramBufferAccessVec_0 | dmiProgramBufferAccessVec_1; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_1 = _dmiProgramBufferAccess_T | dmiProgramBufferAccessVec_2; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_2 = _dmiProgramBufferAccess_T_1 | dmiProgramBufferAccessVec_3; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_3 = _dmiProgramBufferAccess_T_2 | dmiProgramBufferAccessVec_4; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_4 = _dmiProgramBufferAccess_T_3 | dmiProgramBufferAccessVec_5; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_5 = _dmiProgramBufferAccess_T_4 | dmiProgramBufferAccessVec_6; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_6 = _dmiProgramBufferAccess_T_5 | dmiProgramBufferAccessVec_7; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_7 = _dmiProgramBufferAccess_T_6 | dmiProgramBufferAccessVec_8; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_8 = _dmiProgramBufferAccess_T_7 | dmiProgramBufferAccessVec_9; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_9 = _dmiProgramBufferAccess_T_8 | dmiProgramBufferAccessVec_10; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_10 = _dmiProgramBufferAccess_T_9 | dmiProgramBufferAccessVec_11; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_11 = _dmiProgramBufferAccess_T_10 | dmiProgramBufferAccessVec_12; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_12 = _dmiProgramBufferAccess_T_11 | dmiProgramBufferAccessVec_13; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_13 = _dmiProgramBufferAccess_T_12 | dmiProgramBufferAccessVec_14; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_14 = _dmiProgramBufferAccess_T_13 | dmiProgramBufferAccessVec_15; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_15 = _dmiProgramBufferAccess_T_14 | dmiProgramBufferAccessVec_16; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_16 = _dmiProgramBufferAccess_T_15 | dmiProgramBufferAccessVec_17; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_17 = _dmiProgramBufferAccess_T_16 | dmiProgramBufferAccessVec_18; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_18 = _dmiProgramBufferAccess_T_17 | dmiProgramBufferAccessVec_19; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_19 = _dmiProgramBufferAccess_T_18 | dmiProgramBufferAccessVec_20; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_20 = _dmiProgramBufferAccess_T_19 | dmiProgramBufferAccessVec_21; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_21 = _dmiProgramBufferAccess_T_20 | dmiProgramBufferAccessVec_22; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_22 = _dmiProgramBufferAccess_T_21 | dmiProgramBufferAccessVec_23; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_23 = _dmiProgramBufferAccess_T_22 | dmiProgramBufferAccessVec_24; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_24 = _dmiProgramBufferAccess_T_23 | dmiProgramBufferAccessVec_25; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_25 = _dmiProgramBufferAccess_T_24 | dmiProgramBufferAccessVec_26; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_26 = _dmiProgramBufferAccess_T_25 | dmiProgramBufferAccessVec_27; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_27 = _dmiProgramBufferAccess_T_26 | dmiProgramBufferAccessVec_28; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_28 = _dmiProgramBufferAccess_T_27 | dmiProgramBufferAccessVec_29; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_29 = _dmiProgramBufferAccess_T_28 | dmiProgramBufferAccessVec_30; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_30 = _dmiProgramBufferAccess_T_29 | dmiProgramBufferAccessVec_31; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_31 = _dmiProgramBufferAccess_T_30 | dmiProgramBufferAccessVec_32; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_32 = _dmiProgramBufferAccess_T_31 | dmiProgramBufferAccessVec_33; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_33 = _dmiProgramBufferAccess_T_32 | dmiProgramBufferAccessVec_34; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_34 = _dmiProgramBufferAccess_T_33 | dmiProgramBufferAccessVec_35; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_35 = _dmiProgramBufferAccess_T_34 | dmiProgramBufferAccessVec_36; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_36 = _dmiProgramBufferAccess_T_35 | dmiProgramBufferAccessVec_37; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_37 = _dmiProgramBufferAccess_T_36 | dmiProgramBufferAccessVec_38; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_38 = _dmiProgramBufferAccess_T_37 | dmiProgramBufferAccessVec_39; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_39 = _dmiProgramBufferAccess_T_38 | dmiProgramBufferAccessVec_40; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_40 = _dmiProgramBufferAccess_T_39 | dmiProgramBufferAccessVec_41; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_41 = _dmiProgramBufferAccess_T_40 | dmiProgramBufferAccessVec_42; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_42 = _dmiProgramBufferAccess_T_41 | dmiProgramBufferAccessVec_43; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_43 = _dmiProgramBufferAccess_T_42 | dmiProgramBufferAccessVec_44; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_44 = _dmiProgramBufferAccess_T_43 | dmiProgramBufferAccessVec_45; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_45 = _dmiProgramBufferAccess_T_44 | dmiProgramBufferAccessVec_46; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_46 = _dmiProgramBufferAccess_T_45 | dmiProgramBufferAccessVec_47; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_47 = _dmiProgramBufferAccess_T_46 | dmiProgramBufferAccessVec_48; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_48 = _dmiProgramBufferAccess_T_47 | dmiProgramBufferAccessVec_49; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_49 = _dmiProgramBufferAccess_T_48 | dmiProgramBufferAccessVec_50; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_50 = _dmiProgramBufferAccess_T_49 | dmiProgramBufferAccessVec_51; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_51 = _dmiProgramBufferAccess_T_50 | dmiProgramBufferAccessVec_52; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_52 = _dmiProgramBufferAccess_T_51 | dmiProgramBufferAccessVec_53; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_53 = _dmiProgramBufferAccess_T_52 | dmiProgramBufferAccessVec_54; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_54 = _dmiProgramBufferAccess_T_53 | dmiProgramBufferAccessVec_55; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_55 = _dmiProgramBufferAccess_T_54 | dmiProgramBufferAccessVec_56; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_56 = _dmiProgramBufferAccess_T_55 | dmiProgramBufferAccessVec_57; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_57 = _dmiProgramBufferAccess_T_56 | dmiProgramBufferAccessVec_58; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_58 = _dmiProgramBufferAccess_T_57 | dmiProgramBufferAccessVec_59; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_59 = _dmiProgramBufferAccess_T_58 | dmiProgramBufferAccessVec_60; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_60 = _dmiProgramBufferAccess_T_59 | dmiProgramBufferAccessVec_61; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_61 = _dmiProgramBufferAccess_T_60 | dmiProgramBufferAccessVec_62; // @[Debug.scala:1260:46, :1264:69] wire dmiProgramBufferAccess = _dmiProgramBufferAccess_T_61 | dmiProgramBufferAccessVec_63; // @[Debug.scala:1260:46, :1264:69] wire _autoexecData_0_T; // @[Debug.scala:1269:140] wire _autoexecData_1_T; // @[Debug.scala:1269:140] wire _autoexecData_2_T; // @[Debug.scala:1269:140] wire _autoexecData_3_T; // @[Debug.scala:1269:140] wire _autoexecData_4_T; // @[Debug.scala:1269:140] wire _autoexecData_5_T; // @[Debug.scala:1269:140] wire _autoexecData_6_T; // @[Debug.scala:1269:140] wire _autoexecData_7_T; // @[Debug.scala:1269:140] wire autoexecData_0; // @[Debug.scala:1267:33] wire autoexecData_1; // @[Debug.scala:1267:33] wire autoexecData_2; // @[Debug.scala:1267:33] wire autoexecData_3; // @[Debug.scala:1267:33] wire autoexecData_4; // @[Debug.scala:1267:33] wire autoexecData_5; // @[Debug.scala:1267:33] wire autoexecData_6; // @[Debug.scala:1267:33] wire autoexecData_7; // @[Debug.scala:1267:33] wire _autoexecProg_0_T; // @[Debug.scala:1270:144] wire _autoexecProg_1_T; // @[Debug.scala:1270:144] wire _autoexecProg_2_T; // @[Debug.scala:1270:144] wire _autoexecProg_3_T; // @[Debug.scala:1270:144] wire _autoexecProg_4_T; // @[Debug.scala:1270:144] wire _autoexecProg_5_T; // @[Debug.scala:1270:144] wire _autoexecProg_6_T; // @[Debug.scala:1270:144] wire _autoexecProg_7_T; // @[Debug.scala:1270:144] wire _autoexecProg_8_T; // @[Debug.scala:1270:144] wire _autoexecProg_9_T; // @[Debug.scala:1270:144] wire _autoexecProg_10_T; // @[Debug.scala:1270:144] wire _autoexecProg_11_T; // @[Debug.scala:1270:144] wire _autoexecProg_12_T; // @[Debug.scala:1270:144] wire _autoexecProg_13_T; // @[Debug.scala:1270:144] wire _autoexecProg_14_T; // @[Debug.scala:1270:144] wire _autoexecProg_15_T; // @[Debug.scala:1270:144] wire autoexecProg_0; // @[Debug.scala:1268:33] wire autoexecProg_1; // @[Debug.scala:1268:33] wire autoexecProg_2; // @[Debug.scala:1268:33] wire autoexecProg_3; // @[Debug.scala:1268:33] wire autoexecProg_4; // @[Debug.scala:1268:33] wire autoexecProg_5; // @[Debug.scala:1268:33] wire autoexecProg_6; // @[Debug.scala:1268:33] wire autoexecProg_7; // @[Debug.scala:1268:33] wire autoexecProg_8; // @[Debug.scala:1268:33] wire autoexecProg_9; // @[Debug.scala:1268:33] wire autoexecProg_10; // @[Debug.scala:1268:33] wire autoexecProg_11; // @[Debug.scala:1268:33] wire autoexecProg_12; // @[Debug.scala:1268:33] wire autoexecProg_13; // @[Debug.scala:1268:33] wire autoexecProg_14; // @[Debug.scala:1268:33] wire autoexecProg_15; // @[Debug.scala:1268:33] assign _autoexecData_0_T = dmiAbstractDataAccessVec_0 & ABSTRACTAUTOReg_autoexecdata[0]; // @[Debug.scala:1235:36, :1257:45, :1269:{54,140}] assign autoexecData_0 = _autoexecData_0_T; // @[Debug.scala:1267:33, :1269:140] assign _autoexecData_1_T = dmiAbstractDataAccessVec_4 & ABSTRACTAUTOReg_autoexecdata[1]; // @[Debug.scala:1235:36, :1257:45, :1269:{54,140}] assign autoexecData_1 = _autoexecData_1_T; // @[Debug.scala:1267:33, :1269:140] assign _autoexecData_2_T = dmiAbstractDataAccessVec_8 & ABSTRACTAUTOReg_autoexecdata[2]; // @[Debug.scala:1235:36, :1257:45, :1269:{54,140}] assign autoexecData_2 = _autoexecData_2_T; // @[Debug.scala:1267:33, :1269:140] assign _autoexecData_3_T = dmiAbstractDataAccessVec_12 & ABSTRACTAUTOReg_autoexecdata[3]; // @[Debug.scala:1235:36, :1257:45, :1269:{54,140}] assign autoexecData_3 = _autoexecData_3_T; // @[Debug.scala:1267:33, :1269:140] assign _autoexecData_4_T = dmiAbstractDataAccessVec_16 & ABSTRACTAUTOReg_autoexecdata[4]; // @[Debug.scala:1235:36, :1257:45, :1269:{54,140}] assign autoexecData_4 = _autoexecData_4_T; // @[Debug.scala:1267:33, :1269:140] assign _autoexecData_5_T = dmiAbstractDataAccessVec_20 & ABSTRACTAUTOReg_autoexecdata[5]; // @[Debug.scala:1235:36, :1257:45, :1269:{54,140}] assign autoexecData_5 = _autoexecData_5_T; // @[Debug.scala:1267:33, :1269:140] assign _autoexecData_6_T = dmiAbstractDataAccessVec_24 & ABSTRACTAUTOReg_autoexecdata[6]; // @[Debug.scala:1235:36, :1257:45, :1269:{54,140}] assign autoexecData_6 = _autoexecData_6_T; // @[Debug.scala:1267:33, :1269:140] assign _autoexecData_7_T = dmiAbstractDataAccessVec_28 & ABSTRACTAUTOReg_autoexecdata[7]; // @[Debug.scala:1235:36, :1257:45, :1269:{54,140}] assign autoexecData_7 = _autoexecData_7_T; // @[Debug.scala:1267:33, :1269:140] assign _autoexecProg_0_T = dmiProgramBufferAccessVec_0 & ABSTRACTAUTOReg_autoexecprogbuf[0]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}] assign autoexecProg_0 = _autoexecProg_0_T; // @[Debug.scala:1268:33, :1270:144] assign _autoexecProg_1_T = dmiProgramBufferAccessVec_4 & ABSTRACTAUTOReg_autoexecprogbuf[1]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}] assign autoexecProg_1 = _autoexecProg_1_T; // @[Debug.scala:1268:33, :1270:144] assign _autoexecProg_2_T = dmiProgramBufferAccessVec_8 & ABSTRACTAUTOReg_autoexecprogbuf[2]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}] assign autoexecProg_2 = _autoexecProg_2_T; // @[Debug.scala:1268:33, :1270:144] assign _autoexecProg_3_T = dmiProgramBufferAccessVec_12 & ABSTRACTAUTOReg_autoexecprogbuf[3]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}] assign autoexecProg_3 = _autoexecProg_3_T; // @[Debug.scala:1268:33, :1270:144] assign _autoexecProg_4_T = dmiProgramBufferAccessVec_16 & ABSTRACTAUTOReg_autoexecprogbuf[4]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}] assign autoexecProg_4 = _autoexecProg_4_T; // @[Debug.scala:1268:33, :1270:144] assign _autoexecProg_5_T = dmiProgramBufferAccessVec_20 & ABSTRACTAUTOReg_autoexecprogbuf[5]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}] assign autoexecProg_5 = _autoexecProg_5_T; // @[Debug.scala:1268:33, :1270:144] assign _autoexecProg_6_T = dmiProgramBufferAccessVec_24 & ABSTRACTAUTOReg_autoexecprogbuf[6]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}] assign autoexecProg_6 = _autoexecProg_6_T; // @[Debug.scala:1268:33, :1270:144] assign _autoexecProg_7_T = dmiProgramBufferAccessVec_28 & ABSTRACTAUTOReg_autoexecprogbuf[7]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}] assign autoexecProg_7 = _autoexecProg_7_T; // @[Debug.scala:1268:33, :1270:144] assign _autoexecProg_8_T = dmiProgramBufferAccessVec_32 & ABSTRACTAUTOReg_autoexecprogbuf[8]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}] assign autoexecProg_8 = _autoexecProg_8_T; // @[Debug.scala:1268:33, :1270:144] assign _autoexecProg_9_T = dmiProgramBufferAccessVec_36 & ABSTRACTAUTOReg_autoexecprogbuf[9]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}] assign autoexecProg_9 = _autoexecProg_9_T; // @[Debug.scala:1268:33, :1270:144] assign _autoexecProg_10_T = dmiProgramBufferAccessVec_40 & ABSTRACTAUTOReg_autoexecprogbuf[10]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}] assign autoexecProg_10 = _autoexecProg_10_T; // @[Debug.scala:1268:33, :1270:144] assign _autoexecProg_11_T = dmiProgramBufferAccessVec_44 & ABSTRACTAUTOReg_autoexecprogbuf[11]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}] assign autoexecProg_11 = _autoexecProg_11_T; // @[Debug.scala:1268:33, :1270:144] assign _autoexecProg_12_T = dmiProgramBufferAccessVec_48 & ABSTRACTAUTOReg_autoexecprogbuf[12]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}] assign autoexecProg_12 = _autoexecProg_12_T; // @[Debug.scala:1268:33, :1270:144] assign _autoexecProg_13_T = dmiProgramBufferAccessVec_52 & ABSTRACTAUTOReg_autoexecprogbuf[13]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}] assign autoexecProg_13 = _autoexecProg_13_T; // @[Debug.scala:1268:33, :1270:144] assign _autoexecProg_14_T = dmiProgramBufferAccessVec_56 & ABSTRACTAUTOReg_autoexecprogbuf[14]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}] assign autoexecProg_14 = _autoexecProg_14_T; // @[Debug.scala:1268:33, :1270:144] assign _autoexecProg_15_T = dmiProgramBufferAccessVec_60 & ABSTRACTAUTOReg_autoexecprogbuf[15]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}] assign autoexecProg_15 = _autoexecProg_15_T; // @[Debug.scala:1268:33, :1270:144] wire _autoexec_T = autoexecData_0 | autoexecData_1; // @[Debug.scala:1267:33, :1272:42] wire _autoexec_T_1 = _autoexec_T | autoexecData_2; // @[Debug.scala:1267:33, :1272:42] wire _autoexec_T_2 = _autoexec_T_1 | autoexecData_3; // @[Debug.scala:1267:33, :1272:42] wire _autoexec_T_3 = _autoexec_T_2 | autoexecData_4; // @[Debug.scala:1267:33, :1272:42] wire _autoexec_T_4 = _autoexec_T_3 | autoexecData_5; // @[Debug.scala:1267:33, :1272:42] wire _autoexec_T_5 = _autoexec_T_4 | autoexecData_6; // @[Debug.scala:1267:33, :1272:42] wire _autoexec_T_6 = _autoexec_T_5 | autoexecData_7; // @[Debug.scala:1267:33, :1272:42] wire _autoexec_T_7 = autoexecProg_0 | autoexecProg_1; // @[Debug.scala:1268:33, :1272:73] wire _autoexec_T_8 = _autoexec_T_7 | autoexecProg_2; // @[Debug.scala:1268:33, :1272:73] wire _autoexec_T_9 = _autoexec_T_8 | autoexecProg_3; // @[Debug.scala:1268:33, :1272:73] wire _autoexec_T_10 = _autoexec_T_9 | autoexecProg_4; // @[Debug.scala:1268:33, :1272:73] wire _autoexec_T_11 = _autoexec_T_10 | autoexecProg_5; // @[Debug.scala:1268:33, :1272:73] wire _autoexec_T_12 = _autoexec_T_11 | autoexecProg_6; // @[Debug.scala:1268:33, :1272:73] wire _autoexec_T_13 = _autoexec_T_12 | autoexecProg_7; // @[Debug.scala:1268:33, :1272:73] wire _autoexec_T_14 = _autoexec_T_13 | autoexecProg_8; // @[Debug.scala:1268:33, :1272:73] wire _autoexec_T_15 = _autoexec_T_14 | autoexecProg_9; // @[Debug.scala:1268:33, :1272:73] wire _autoexec_T_16 = _autoexec_T_15 | autoexecProg_10; // @[Debug.scala:1268:33, :1272:73] wire _autoexec_T_17 = _autoexec_T_16 | autoexecProg_11; // @[Debug.scala:1268:33, :1272:73] wire _autoexec_T_18 = _autoexec_T_17 | autoexecProg_12; // @[Debug.scala:1268:33, :1272:73] wire _autoexec_T_19 = _autoexec_T_18 | autoexecProg_13; // @[Debug.scala:1268:33, :1272:73] wire _autoexec_T_20 = _autoexec_T_19 | autoexecProg_14; // @[Debug.scala:1268:33, :1272:73] wire _autoexec_T_21 = _autoexec_T_20 | autoexecProg_15; // @[Debug.scala:1268:33, :1272:73] wire autoexec = _autoexec_T_6 | _autoexec_T_21; // @[Debug.scala:1272:{42,48,73}] reg [7:0] COMMANDReg_cmdtype; // @[Debug.scala:1277:25] reg [23:0] COMMANDReg_control; // @[Debug.scala:1277:25] wire [31:0] COMMANDWrDataVal; // @[Debug.scala:1279:39] wire [31:0] _COMMANDWrData_WIRE_1 = COMMANDWrDataVal; // @[Debug.scala:1279:39, :1280:65] wire [7:0] _COMMANDWrData_T_1; // @[Debug.scala:1280:65] wire [23:0] _COMMANDWrData_T; // @[Debug.scala:1280:65] wire [7:0] COMMANDWrData_cmdtype = _COMMANDWrData_WIRE_cmdtype; // @[Debug.scala:1280:{39,65}] wire [23:0] COMMANDWrData_control = _COMMANDWrData_WIRE_control; // @[Debug.scala:1280:{39,65}] assign _COMMANDWrData_T = _COMMANDWrData_WIRE_1[23:0]; // @[Debug.scala:1280:65] assign _COMMANDWrData_WIRE_control = _COMMANDWrData_T; // @[Debug.scala:1280:65] assign _COMMANDWrData_T_1 = _COMMANDWrData_WIRE_1[31:24]; // @[Debug.scala:1280:65] assign _COMMANDWrData_WIRE_cmdtype = _COMMANDWrData_T_1; // @[Debug.scala:1280:65] wire out_f_woready_140; // @[RegisterRouter.scala:87:24] wire COMMANDWrEnMaybe; // @[Debug.scala:1281:39] wire _COMMANDWrEnLegal_T; // @[Debug.scala:1743:44] wire COMMANDWrEnLegal; // @[Debug.scala:1282:39] wire out_f_roready_140; // @[RegisterRouter.scala:87:24] wire COMMANDRdEn; // @[Debug.scala:1283:32] wire COMMANDWrEn = COMMANDWrEnMaybe & COMMANDWrEnLegal; // @[Debug.scala:1281:39, :1282:39, :1285:40] reg [7:0] abstractDataMem_0; // @[Debug.scala:1300:36] wire [7:0] _out_T_308 = abstractDataMem_0; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9474 = abstractDataMem_0; // @[RegisterRouter.scala:87:24] reg [7:0] abstractDataMem_1; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_2; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_3; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_4; // @[Debug.scala:1300:36] wire [7:0] _out_T_77 = abstractDataMem_4; // @[RegisterRouter.scala:87:24] reg [7:0] abstractDataMem_5; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_6; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_7; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_8; // @[Debug.scala:1300:36] wire [7:0] _out_T_761 = abstractDataMem_8; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7912 = abstractDataMem_8; // @[RegisterRouter.scala:87:24] reg [7:0] abstractDataMem_9; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_10; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_11; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_12; // @[Debug.scala:1300:36] wire [7:0] _out_T_1325 = abstractDataMem_12; // @[RegisterRouter.scala:87:24] reg [7:0] abstractDataMem_13; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_14; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_15; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_16; // @[Debug.scala:1300:36] wire [7:0] _out_T_264 = abstractDataMem_16; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10874 = abstractDataMem_16; // @[RegisterRouter.scala:87:24] reg [7:0] abstractDataMem_17; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_18; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_19; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_20; // @[Debug.scala:1300:36] wire [7:0] _out_T_132 = abstractDataMem_20; // @[RegisterRouter.scala:87:24] reg [7:0] abstractDataMem_21; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_22; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_23; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_24; // @[Debug.scala:1300:36] wire [7:0] _out_T_396 = abstractDataMem_24; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2207 = abstractDataMem_24; // @[RegisterRouter.scala:87:24] reg [7:0] abstractDataMem_25; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_26; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_27; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_28; // @[Debug.scala:1300:36] wire [7:0] _out_T_1413 = abstractDataMem_28; // @[RegisterRouter.scala:87:24] reg [7:0] abstractDataMem_29; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_30; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_31; // @[Debug.scala:1300:36] wire [7:0] abstractDataNxt_0; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_1; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_2; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_3; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_4; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_5; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_6; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_7; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_8; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_9; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_10; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_11; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_12; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_13; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_14; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_15; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_16; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_17; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_18; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_19; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_20; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_21; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_22; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_23; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_24; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_25; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_26; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_27; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_28; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_29; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_30; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_31; // @[Debug.scala:1301:41] reg [7:0] programBufferMem_0; // @[Debug.scala:1306:34] wire [7:0] _out_T_1128 = programBufferMem_0; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10426 = programBufferMem_0; // @[RegisterRouter.scala:87:24] reg [7:0] programBufferMem_1; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_2; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_3; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_4; // @[Debug.scala:1306:34] wire [7:0] _out_T_860 = programBufferMem_4; // @[RegisterRouter.scala:87:24] reg [7:0] programBufferMem_5; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_6; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_7; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_8; // @[Debug.scala:1306:34] wire [7:0] _out_T_1172 = programBufferMem_8; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6582 = programBufferMem_8; // @[RegisterRouter.scala:87:24] reg [7:0] programBufferMem_9; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_10; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_11; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_12; // @[Debug.scala:1306:34] wire [7:0] _out_T_220 = programBufferMem_12; // @[RegisterRouter.scala:87:24] reg [7:0] programBufferMem_13; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_14; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_15; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_16; // @[Debug.scala:1306:34] wire [7:0] _out_T_1556 = programBufferMem_16; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3679 = programBufferMem_16; // @[RegisterRouter.scala:87:24] reg [7:0] programBufferMem_17; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_18; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_19; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_20; // @[Debug.scala:1306:34] wire [7:0] _out_T_662 = programBufferMem_20; // @[RegisterRouter.scala:87:24] reg [7:0] programBufferMem_21; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_22; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_23; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_24; // @[Debug.scala:1306:34] wire [7:0] _out_T_816 = programBufferMem_24; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11898 = programBufferMem_24; // @[RegisterRouter.scala:87:24] reg [7:0] programBufferMem_25; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_26; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_27; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_28; // @[Debug.scala:1306:34] wire [7:0] _out_T_1369 = programBufferMem_28; // @[RegisterRouter.scala:87:24] reg [7:0] programBufferMem_29; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_30; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_31; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_32; // @[Debug.scala:1306:34] wire [7:0] _out_T_1501 = programBufferMem_32; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8594 = programBufferMem_32; // @[RegisterRouter.scala:87:24] reg [7:0] programBufferMem_33; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_34; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_35; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_36; // @[Debug.scala:1306:34] wire [7:0] _out_T_176 = programBufferMem_36; // @[RegisterRouter.scala:87:24] reg [7:0] programBufferMem_37; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_38; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_39; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_40; // @[Debug.scala:1306:34] wire [7:0] _out_T_587 = programBufferMem_40; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5954 = programBufferMem_40; // @[RegisterRouter.scala:87:24] reg [7:0] programBufferMem_41; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_42; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_43; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_44; // @[Debug.scala:1306:34] wire [7:0] _out_T_1457 = programBufferMem_44; // @[RegisterRouter.scala:87:24] reg [7:0] programBufferMem_45; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_46; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_47; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_48; // @[Debug.scala:1306:34] wire [7:0] _out_T_1281 = programBufferMem_48; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2943 = programBufferMem_48; // @[RegisterRouter.scala:87:24] reg [7:0] programBufferMem_49; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_50; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_51; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_52; // @[Debug.scala:1306:34] wire [7:0] _out_T_904 = programBufferMem_52; // @[RegisterRouter.scala:87:24] reg [7:0] programBufferMem_53; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_54; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_55; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_56; // @[Debug.scala:1306:34] wire [7:0] _out_T_706 = programBufferMem_56; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12562 = programBufferMem_56; // @[RegisterRouter.scala:87:24] reg [7:0] programBufferMem_57; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_58; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_59; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_60; // @[Debug.scala:1306:34] wire [7:0] _out_T_352 = programBufferMem_60; // @[RegisterRouter.scala:87:24] reg [7:0] programBufferMem_61; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_62; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_63; // @[Debug.scala:1306:34] wire [7:0] programBufferNxt_0; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_1; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_2; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_3; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_4; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_5; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_6; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_7; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_8; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_9; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_10; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_11; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_12; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_13; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_14; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_15; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_16; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_17; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_18; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_19; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_20; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_21; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_22; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_23; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_24; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_25; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_26; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_27; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_28; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_29; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_30; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_31; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_32; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_33; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_34; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_35; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_36; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_37; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_38; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_39; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_40; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_41; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_42; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_43; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_44; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_45; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_46; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_47; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_48; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_49; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_50; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_51; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_52; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_53; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_54; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_55; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_56; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_57; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_58; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_59; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_60; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_61; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_62; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_63; // @[Debug.scala:1307:39] wire _resumeReqRegs_T = ~hartIsInResetSync_0; // @[Debug.scala:948:33, :1320:42] wire _resumeReqRegs_T_1 = resumeReqRegs & _resumeReqRegs_T; // @[Debug.scala:863:31, :1320:{40,42}] wire [1023:0] hartselIndex = 1024'h1 << io_innerCtrl_bits_hartsel_0; // @[OneHot.scala:58:35] wire _haltedBitRegs_T_1 = ~hartIsInResetSync_0; // @[Debug.scala:948:33, :1320:42, :1327:66] wire [1:0] _haltedBitRegs_T_2 = {1'h0, _haltedBitRegs_T[0] & _haltedBitRegs_T_1}; // @[Debug.scala:1327:{43,64,66}] wire _haltedBitRegs_T_5 = ~hartIsInResetSync_0; // @[Debug.scala:948:33, :1320:42, :1330:71] wire _haltedBitRegs_T_7 = ~hartIsInResetSync_0; // @[Debug.scala:948:33, :1320:42, :1333:44] wire _haltedBitRegs_T_8 = haltedBitRegs & _haltedBitRegs_T_7; // @[Debug.scala:861:31, :1333:{42,44}] wire _resumeReqRegs_T_4 = ~hartIsInResetSync_0; // @[Debug.scala:948:33, :1320:42, :1338:71] wire _resumeReqRegs_T_6 = resumeReqRegs | hamaskWrSel_0; // @[Debug.scala:863:31, :933:31, :1342:43] wire _resumeReqRegs_T_7 = ~hartIsInResetSync_0; // @[Debug.scala:948:33, :1320:42, :1342:67] wire _resumeReqRegs_T_8 = _resumeReqRegs_T_6 & _resumeReqRegs_T_7; // @[Debug.scala:1342:{43,65,67}] wire _resumeAcks_T = ~resumeReqRegs; // @[Debug.scala:863:31, :1349:24] wire _resumeAcks_T_1 = ~hamaskWrSel_0; // @[Debug.scala:933:31, :1017:50, :1349:41] wire _resumeAcks_T_2 = _resumeAcks_T & _resumeAcks_T_1; // @[Debug.scala:1349:{24,39,41}] wire _resumeAcks_T_3 = ~resumeReqRegs; // @[Debug.scala:863:31, :1349:24, :1351:23] assign resumeAcks = resumereq ? _resumeAcks_T_2 : _resumeAcks_T_3; // @[Debug.scala:869:32, :983:39, :1347:24, :1349:{20,39}, :1351:{20,23}] wire _anyAddressWrEn_T_2; // @[SBA.scala:134:54] wire anyAddressWrEn; // @[SBA.scala:42:34] wire _anyDataRdEn_T_2; // @[SBA.scala:176:51] wire anyDataRdEn; // @[SBA.scala:43:34] wire _anyDataWrEn_T_2; // @[SBA.scala:177:51] wire anyDataWrEn; // @[SBA.scala:44:34] reg SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28] wire SBCSRdData_sbbusyerror = SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28, :60:38] reg SBCSFieldsReg_sbbusy; // @[SBA.scala:47:28] reg SBCSFieldsReg_sbreadonaddr; // @[SBA.scala:47:28] wire SBCSRdData_sbreadonaddr = SBCSFieldsReg_sbreadonaddr; // @[SBA.scala:47:28, :60:38] reg [2:0] SBCSFieldsReg_sbaccess; // @[SBA.scala:47:28] wire [2:0] SBCSRdData_sbaccess = SBCSFieldsReg_sbaccess; // @[SBA.scala:47:28, :60:38] reg SBCSFieldsReg_sbautoincrement; // @[SBA.scala:47:28] wire SBCSRdData_sbautoincrement = SBCSFieldsReg_sbautoincrement; // @[SBA.scala:47:28, :60:38] reg SBCSFieldsReg_sbreadondata; // @[SBA.scala:47:28] wire SBCSRdData_sbreadondata = SBCSFieldsReg_sbreadondata; // @[SBA.scala:47:28, :60:38] wire _SBCSFieldsRegReset_sbbusy_T; // @[SBA.scala:51:67] wire SBCSFieldsRegReset_sbbusy; // @[SBA.scala:49:38] assign _SBCSFieldsRegReset_sbbusy_T = |_sb2tlOpt_io_sbStateOut; // @[SBA.scala:51:67] assign SBCSFieldsRegReset_sbbusy = _SBCSFieldsRegReset_sbbusy_T; // @[SBA.scala:49:38, :51:67] wire sbBusy; // @[SBA.scala:203:46] wire SBCSRdData_sbbusy; // @[SBA.scala:60:38] wire [2:0] SBCSRdData_sberror; // @[SBA.scala:60:38] wire _out_T_549; // @[RegisterRouter.scala:87:24] wire _out_T_529; // @[RegisterRouter.scala:87:24] wire [2:0] _out_T_518; // @[RegisterRouter.scala:87:24] wire _out_T_507; // @[RegisterRouter.scala:87:24] wire _out_T_496; // @[RegisterRouter.scala:87:24] wire [2:0] _out_T_485; // @[RegisterRouter.scala:87:24] wire SBCSWrData_sbbusyerror; // @[SBA.scala:63:38] wire SBCSWrData_sbreadonaddr; // @[SBA.scala:63:38] wire [2:0] SBCSWrData_sbaccess; // @[SBA.scala:63:38] wire SBCSWrData_sbautoincrement; // @[SBA.scala:63:38] wire SBCSWrData_sbreadondata; // @[SBA.scala:63:38] wire [2:0] SBCSWrData_sberror; // @[SBA.scala:63:38] wire out_f_woready_39; // @[RegisterRouter.scala:87:24] wire sberrorWrEn; // @[SBA.scala:65:38] wire out_f_woready_40; // @[RegisterRouter.scala:87:24] wire sbreadondataWrEn; // @[SBA.scala:66:38] wire out_f_woready_41; // @[RegisterRouter.scala:87:24] wire sbautoincrementWrEn; // @[SBA.scala:67:38] wire out_f_woready_42; // @[RegisterRouter.scala:87:24] wire sbaccessWrEn; // @[SBA.scala:68:38] wire out_f_woready_43; // @[RegisterRouter.scala:87:24] wire sbreadonaddrWrEn; // @[SBA.scala:69:38] wire out_f_woready_45; // @[RegisterRouter.scala:87:24] wire sbbusyerrorWrEn; // @[SBA.scala:70:38] reg [31:0] SBADDRESSFieldsReg_0; // @[SBA.scala:104:33] wire [31:0] _out_T_750 = SBADDRESSFieldsReg_0; // @[RegisterRouter.scala:87:24] wire [31:0] SBADDRESSWrData_0; // @[SBA.scala:106:38] wire out_f_roready_63; // @[RegisterRouter.scala:87:24] wire SBADDRESSRdEn_0; // @[SBA.scala:107:38] wire out_f_woready_63; // @[RegisterRouter.scala:87:24] wire _anyAddressWrEn_T = SBADDRESSWrEn_0; // @[SBA.scala:108:38, :134:54] wire [127:0] _autoIncrementedAddr_T_3; // @[SBA.scala:111:60] wire [127:0] autoIncrementedAddr; // @[SBA.scala:110:39] wire [63:0] _GEN_0 = {32'h0, SBADDRESSFieldsReg_0}; // @[SBA.scala:104:33, :111:31] wire [63:0] autoIncrementedAddr_lo; // @[SBA.scala:111:31] assign autoIncrementedAddr_lo = _GEN_0; // @[SBA.scala:111:31] wire [63:0] sb2tlOpt_io_addrIn_lo; // @[SBA.scala:133:10] assign sb2tlOpt_io_addrIn_lo = _GEN_0; // @[SBA.scala:111:31, :133:10] wire [127:0] _autoIncrementedAddr_T = {64'h0, autoIncrementedAddr_lo}; // @[SBA.scala:111:31] wire [7:0] _autoIncrementedAddr_T_1 = 8'h1 << SBCSFieldsReg_sbaccess; // @[SBA.scala:47:28, :111:67] wire [128:0] _autoIncrementedAddr_T_2 = {1'h0, _autoIncrementedAddr_T} + {121'h0, _autoIncrementedAddr_T_1}; // @[SBA.scala:111:{31,60,67}] assign _autoIncrementedAddr_T_3 = _autoIncrementedAddr_T_2[127:0]; // @[SBA.scala:111:60] assign autoIncrementedAddr = _autoIncrementedAddr_T_3; // @[SBA.scala:110:39, :111:60] wire _GEN_1 = SBCSRdData_sberror == 3'h0; // @[SBA.scala:60:38, :119:40] wire _SBADDRESSFieldsReg_0_T; // @[SBA.scala:119:40] assign _SBADDRESSFieldsReg_0_T = _GEN_1; // @[SBA.scala:119:40] wire _SBDATAFieldsReg_0_0_T_4; // @[SBA.scala:160:97] assign _SBDATAFieldsReg_0_0_T_4 = _GEN_1; // @[SBA.scala:119:40, :160:97] wire _SBDATAFieldsReg_0_1_T_4; // @[SBA.scala:160:97] assign _SBDATAFieldsReg_0_1_T_4 = _GEN_1; // @[SBA.scala:119:40, :160:97] wire _SBDATAFieldsReg_0_2_T_4; // @[SBA.scala:160:97] assign _SBDATAFieldsReg_0_2_T_4 = _GEN_1; // @[SBA.scala:119:40, :160:97] wire _SBDATAFieldsReg_0_3_T_4; // @[SBA.scala:160:97] assign _SBDATAFieldsReg_0_3_T_4 = _GEN_1; // @[SBA.scala:119:40, :160:97] wire _SBDATAFieldsReg_1_0_T_4; // @[SBA.scala:160:97] assign _SBDATAFieldsReg_1_0_T_4 = _GEN_1; // @[SBA.scala:119:40, :160:97] wire _SBDATAFieldsReg_1_1_T_4; // @[SBA.scala:160:97] assign _SBDATAFieldsReg_1_1_T_4 = _GEN_1; // @[SBA.scala:119:40, :160:97] wire _SBDATAFieldsReg_1_2_T_4; // @[SBA.scala:160:97] assign _SBDATAFieldsReg_1_2_T_4 = _GEN_1; // @[SBA.scala:119:40, :160:97] wire _SBDATAFieldsReg_1_3_T_4; // @[SBA.scala:160:97] assign _SBDATAFieldsReg_1_3_T_4 = _GEN_1; // @[SBA.scala:119:40, :160:97] wire _sb2tlOpt_io_wrEn_T_5; // @[SBA.scala:199:118] assign _sb2tlOpt_io_wrEn_T_5 = _GEN_1; // @[SBA.scala:119:40, :199:118] wire _sb2tlOpt_io_rdEn_T_5; // @[SBA.scala:200:118] assign _sb2tlOpt_io_rdEn_T_5 = _GEN_1; // @[SBA.scala:119:40, :200:118] wire _SBADDRESSFieldsReg_0_T_1 = SBADDRESSWrEn_0 & _SBADDRESSFieldsReg_0_T; // @[SBA.scala:108:38, :119:{37,40}] wire _SBADDRESSFieldsReg_0_T_2 = ~SBCSFieldsReg_sbbusy; // @[SBA.scala:47:28, :119:63] wire _SBADDRESSFieldsReg_0_T_3 = _SBADDRESSFieldsReg_0_T_1 & _SBADDRESSFieldsReg_0_T_2; // @[SBA.scala:119:{37,60,63}] wire _SBADDRESSFieldsReg_0_T_4 = ~SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28, :119:88] wire _SBADDRESSFieldsReg_0_T_5 = _SBADDRESSFieldsReg_0_T_3 & _SBADDRESSFieldsReg_0_T_4; // @[SBA.scala:119:{60,85,88}] wire _GEN_2 = _sb2tlOpt_io_rdDone | _sb2tlOpt_io_wrDone; // @[SBA.scala:120:44] wire _SBADDRESSFieldsReg_0_T_6; // @[SBA.scala:120:44] assign _SBADDRESSFieldsReg_0_T_6 = _GEN_2; // @[SBA.scala:120:44] wire _sbErrorReg_0_T_12; // @[SBA.scala:229:54] assign _sbErrorReg_0_T_12 = _GEN_2; // @[SBA.scala:120:44, :229:54] wire _sbErrorReg_1_T_12; // @[SBA.scala:229:54] assign _sbErrorReg_1_T_12 = _GEN_2; // @[SBA.scala:120:44, :229:54] wire _sbErrorReg_2_T_12; // @[SBA.scala:229:54] assign _sbErrorReg_2_T_12 = _GEN_2; // @[SBA.scala:120:44, :229:54] wire _SBADDRESSFieldsReg_0_T_7 = _SBADDRESSFieldsReg_0_T_6 & SBCSFieldsReg_sbautoincrement; // @[SBA.scala:47:28, :120:{44,71}] wire [31:0] _SBADDRESSFieldsReg_0_T_8 = autoIncrementedAddr[31:0]; // @[SBA.scala:110:39, :120:124] wire [31:0] _SBADDRESSFieldsReg_0_T_9 = _SBADDRESSFieldsReg_0_T_7 ? _SBADDRESSFieldsReg_0_T_8 : SBADDRESSFieldsReg_0; // @[SBA.scala:104:33, :120:{19,71,124}] wire [31:0] _SBADDRESSFieldsReg_0_T_10 = _SBADDRESSFieldsReg_0_T_5 ? SBADDRESSWrData_0 : _SBADDRESSFieldsReg_0_T_9; // @[SBA.scala:106:38, :119:{19,85}, :120:19] wire [127:0] _sb2tlOpt_io_addrIn_T_1 = {96'h0, SBADDRESSWrData_0}; // @[SBA.scala:106:38, :132:10] wire [127:0] _sb2tlOpt_io_addrIn_T_2 = {64'h0, sb2tlOpt_io_addrIn_lo}; // @[SBA.scala:133:10] wire [127:0] _sb2tlOpt_io_addrIn_T_3 = SBADDRESSWrEn_0 ? _sb2tlOpt_io_addrIn_T_1 : _sb2tlOpt_io_addrIn_T_2; // @[SBA.scala:108:38, :131:34, :132:10, :133:10] wire _anyAddressWrEn_T_1 = _anyAddressWrEn_T; // @[SBA.scala:134:54] assign _anyAddressWrEn_T_2 = _anyAddressWrEn_T_1; // @[SBA.scala:134:54] assign anyAddressWrEn = _anyAddressWrEn_T_2; // @[SBA.scala:42:34, :134:54] reg [7:0] SBDATAFieldsReg_0_0; // @[SBA.scala:143:30] reg [7:0] SBDATAFieldsReg_0_1; // @[SBA.scala:143:30] reg [7:0] SBDATAFieldsReg_0_2; // @[SBA.scala:143:30] reg [7:0] SBDATAFieldsReg_0_3; // @[SBA.scala:143:30] reg [7:0] SBDATAFieldsReg_1_0; // @[SBA.scala:143:30] reg [7:0] SBDATAFieldsReg_1_1; // @[SBA.scala:143:30] reg [7:0] SBDATAFieldsReg_1_2; // @[SBA.scala:143:30] reg [7:0] SBDATAFieldsReg_1_3; // @[SBA.scala:143:30] wire [31:0] _SBDATARdData_0_T; // @[SBA.scala:165:31] wire [31:0] _SBDATARdData_1_T; // @[SBA.scala:165:31] wire [31:0] _out_T_805 = SBDATARdData_0; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_121 = SBDATARdData_1; // @[RegisterRouter.scala:87:24] wire [31:0] SBDATAWrData_0; // @[SBA.scala:147:35] wire [31:0] SBDATAWrData_1; // @[SBA.scala:147:35] wire out_f_roready_68; // @[RegisterRouter.scala:87:24] wire out_f_roready_4; // @[RegisterRouter.scala:87:24] wire SBDATARdEn_0; // @[SBA.scala:149:35] wire SBDATARdEn_1; // @[SBA.scala:149:35] wire out_f_woready_68; // @[RegisterRouter.scala:87:24] wire _sb2tlOpt_io_wrEn_T = SBDATAWrEn_0; // @[SBA.scala:150:35, :199:49] wire out_f_woready_4; // @[RegisterRouter.scala:87:24] wire SBDATAWrEn_1; // @[SBA.scala:150:35] wire _SBDATAFieldsReg_0_0_T = ~SBCSFieldsReg_sbbusy; // @[SBA.scala:47:28, :119:63, :160:42] wire _SBDATAFieldsReg_0_0_T_1 = SBDATAWrEn_0 & _SBDATAFieldsReg_0_0_T; // @[SBA.scala:150:35, :160:{39,42}] wire _SBDATAFieldsReg_0_0_T_2 = ~SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28, :119:88, :160:67] wire _SBDATAFieldsReg_0_0_T_3 = _SBDATAFieldsReg_0_0_T_1 & _SBDATAFieldsReg_0_0_T_2; // @[SBA.scala:160:{39,64,67}] wire _SBDATAFieldsReg_0_0_T_5 = _SBDATAFieldsReg_0_0_T_3 & _SBDATAFieldsReg_0_0_T_4; // @[SBA.scala:160:{64,94,97}] wire [7:0] _SBDATAFieldsReg_0_0_T_6 = SBDATAWrData_0[7:0]; // @[SBA.scala:147:35, :160:133] wire [7:0] _SBDATAFieldsReg_0_0_T_7 = _sb2tlOpt_io_rdLoad_0 ? _sb2tlOpt_io_dataOut : SBDATAFieldsReg_0_0; // @[SBA.scala:143:30, :161:24] wire [7:0] _SBDATAFieldsReg_0_0_T_8 = _SBDATAFieldsReg_0_0_T_5 ? _SBDATAFieldsReg_0_0_T_6 : _SBDATAFieldsReg_0_0_T_7; // @[SBA.scala:160:{24,94,133}, :161:24] wire _SBDATAFieldsReg_0_1_T = ~SBCSFieldsReg_sbbusy; // @[SBA.scala:47:28, :119:63, :160:42] wire _SBDATAFieldsReg_0_1_T_1 = SBDATAWrEn_0 & _SBDATAFieldsReg_0_1_T; // @[SBA.scala:150:35, :160:{39,42}] wire _SBDATAFieldsReg_0_1_T_2 = ~SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28, :119:88, :160:67] wire _SBDATAFieldsReg_0_1_T_3 = _SBDATAFieldsReg_0_1_T_1 & _SBDATAFieldsReg_0_1_T_2; // @[SBA.scala:160:{39,64,67}] wire _SBDATAFieldsReg_0_1_T_5 = _SBDATAFieldsReg_0_1_T_3 & _SBDATAFieldsReg_0_1_T_4; // @[SBA.scala:160:{64,94,97}] wire [7:0] _SBDATAFieldsReg_0_1_T_6 = SBDATAWrData_0[15:8]; // @[SBA.scala:147:35, :160:133] wire [7:0] _SBDATAFieldsReg_0_1_T_7 = _sb2tlOpt_io_rdLoad_1 ? _sb2tlOpt_io_dataOut : SBDATAFieldsReg_0_1; // @[SBA.scala:143:30, :161:24] wire [7:0] _SBDATAFieldsReg_0_1_T_8 = _SBDATAFieldsReg_0_1_T_5 ? _SBDATAFieldsReg_0_1_T_6 : _SBDATAFieldsReg_0_1_T_7; // @[SBA.scala:160:{24,94,133}, :161:24] wire _SBDATAFieldsReg_0_2_T = ~SBCSFieldsReg_sbbusy; // @[SBA.scala:47:28, :119:63, :160:42] wire _SBDATAFieldsReg_0_2_T_1 = SBDATAWrEn_0 & _SBDATAFieldsReg_0_2_T; // @[SBA.scala:150:35, :160:{39,42}] wire _SBDATAFieldsReg_0_2_T_2 = ~SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28, :119:88, :160:67] wire _SBDATAFieldsReg_0_2_T_3 = _SBDATAFieldsReg_0_2_T_1 & _SBDATAFieldsReg_0_2_T_2; // @[SBA.scala:160:{39,64,67}] wire _SBDATAFieldsReg_0_2_T_5 = _SBDATAFieldsReg_0_2_T_3 & _SBDATAFieldsReg_0_2_T_4; // @[SBA.scala:160:{64,94,97}] wire [7:0] _SBDATAFieldsReg_0_2_T_6 = SBDATAWrData_0[23:16]; // @[SBA.scala:147:35, :160:133] wire [7:0] _SBDATAFieldsReg_0_2_T_7 = _sb2tlOpt_io_rdLoad_2 ? _sb2tlOpt_io_dataOut : SBDATAFieldsReg_0_2; // @[SBA.scala:143:30, :161:24] wire [7:0] _SBDATAFieldsReg_0_2_T_8 = _SBDATAFieldsReg_0_2_T_5 ? _SBDATAFieldsReg_0_2_T_6 : _SBDATAFieldsReg_0_2_T_7; // @[SBA.scala:160:{24,94,133}, :161:24] wire _SBDATAFieldsReg_0_3_T = ~SBCSFieldsReg_sbbusy; // @[SBA.scala:47:28, :119:63, :160:42] wire _SBDATAFieldsReg_0_3_T_1 = SBDATAWrEn_0 & _SBDATAFieldsReg_0_3_T; // @[SBA.scala:150:35, :160:{39,42}] wire _SBDATAFieldsReg_0_3_T_2 = ~SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28, :119:88, :160:67] wire _SBDATAFieldsReg_0_3_T_3 = _SBDATAFieldsReg_0_3_T_1 & _SBDATAFieldsReg_0_3_T_2; // @[SBA.scala:160:{39,64,67}] wire _SBDATAFieldsReg_0_3_T_5 = _SBDATAFieldsReg_0_3_T_3 & _SBDATAFieldsReg_0_3_T_4; // @[SBA.scala:160:{64,94,97}] wire [7:0] _SBDATAFieldsReg_0_3_T_6 = SBDATAWrData_0[31:24]; // @[SBA.scala:147:35, :160:133] wire [7:0] _SBDATAFieldsReg_0_3_T_7 = _sb2tlOpt_io_rdLoad_3 ? _sb2tlOpt_io_dataOut : SBDATAFieldsReg_0_3; // @[SBA.scala:143:30, :161:24] wire [7:0] _SBDATAFieldsReg_0_3_T_8 = _SBDATAFieldsReg_0_3_T_5 ? _SBDATAFieldsReg_0_3_T_6 : _SBDATAFieldsReg_0_3_T_7; // @[SBA.scala:160:{24,94,133}, :161:24] wire [15:0] _GEN_3 = {SBDATAFieldsReg_0_1, SBDATAFieldsReg_0_0}; // @[SBA.scala:143:30, :165:31] wire [15:0] SBDATARdData_0_lo; // @[SBA.scala:165:31] assign SBDATARdData_0_lo = _GEN_3; // @[SBA.scala:165:31] wire [15:0] sb2tlOpt_io_dataIn_lo_lo_lo; // @[SBA.scala:175:85] assign sb2tlOpt_io_dataIn_lo_lo_lo = _GEN_3; // @[SBA.scala:165:31, :175:85] wire [15:0] _GEN_4 = {SBDATAFieldsReg_0_3, SBDATAFieldsReg_0_2}; // @[SBA.scala:143:30, :165:31] wire [15:0] SBDATARdData_0_hi; // @[SBA.scala:165:31] assign SBDATARdData_0_hi = _GEN_4; // @[SBA.scala:165:31] wire [15:0] sb2tlOpt_io_dataIn_lo_lo_hi; // @[SBA.scala:175:85] assign sb2tlOpt_io_dataIn_lo_lo_hi = _GEN_4; // @[SBA.scala:165:31, :175:85] assign _SBDATARdData_0_T = {SBDATARdData_0_hi, SBDATARdData_0_lo}; // @[SBA.scala:165:31] assign SBDATARdData_0 = _SBDATARdData_0_T; // @[SBA.scala:145:35, :165:31] wire _SBDATAFieldsReg_1_0_T = ~SBCSFieldsReg_sbbusy; // @[SBA.scala:47:28, :119:63, :160:42] wire _SBDATAFieldsReg_1_0_T_1 = SBDATAWrEn_1 & _SBDATAFieldsReg_1_0_T; // @[SBA.scala:150:35, :160:{39,42}] wire _SBDATAFieldsReg_1_0_T_2 = ~SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28, :119:88, :160:67] wire _SBDATAFieldsReg_1_0_T_3 = _SBDATAFieldsReg_1_0_T_1 & _SBDATAFieldsReg_1_0_T_2; // @[SBA.scala:160:{39,64,67}] wire _SBDATAFieldsReg_1_0_T_5 = _SBDATAFieldsReg_1_0_T_3 & _SBDATAFieldsReg_1_0_T_4; // @[SBA.scala:160:{64,94,97}] wire [7:0] _SBDATAFieldsReg_1_0_T_6 = SBDATAWrData_1[7:0]; // @[SBA.scala:147:35, :160:133] wire [7:0] _SBDATAFieldsReg_1_0_T_7 = _sb2tlOpt_io_rdLoad_4 ? _sb2tlOpt_io_dataOut : SBDATAFieldsReg_1_0; // @[SBA.scala:143:30, :161:24] wire [7:0] _SBDATAFieldsReg_1_0_T_8 = _SBDATAFieldsReg_1_0_T_5 ? _SBDATAFieldsReg_1_0_T_6 : _SBDATAFieldsReg_1_0_T_7; // @[SBA.scala:160:{24,94,133}, :161:24] wire _SBDATAFieldsReg_1_1_T = ~SBCSFieldsReg_sbbusy; // @[SBA.scala:47:28, :119:63, :160:42] wire _SBDATAFieldsReg_1_1_T_1 = SBDATAWrEn_1 & _SBDATAFieldsReg_1_1_T; // @[SBA.scala:150:35, :160:{39,42}] wire _SBDATAFieldsReg_1_1_T_2 = ~SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28, :119:88, :160:67] wire _SBDATAFieldsReg_1_1_T_3 = _SBDATAFieldsReg_1_1_T_1 & _SBDATAFieldsReg_1_1_T_2; // @[SBA.scala:160:{39,64,67}] wire _SBDATAFieldsReg_1_1_T_5 = _SBDATAFieldsReg_1_1_T_3 & _SBDATAFieldsReg_1_1_T_4; // @[SBA.scala:160:{64,94,97}] wire [7:0] _SBDATAFieldsReg_1_1_T_6 = SBDATAWrData_1[15:8]; // @[SBA.scala:147:35, :160:133] wire [7:0] _SBDATAFieldsReg_1_1_T_7 = _sb2tlOpt_io_rdLoad_5 ? _sb2tlOpt_io_dataOut : SBDATAFieldsReg_1_1; // @[SBA.scala:143:30, :161:24] wire [7:0] _SBDATAFieldsReg_1_1_T_8 = _SBDATAFieldsReg_1_1_T_5 ? _SBDATAFieldsReg_1_1_T_6 : _SBDATAFieldsReg_1_1_T_7; // @[SBA.scala:160:{24,94,133}, :161:24] wire _SBDATAFieldsReg_1_2_T = ~SBCSFieldsReg_sbbusy; // @[SBA.scala:47:28, :119:63, :160:42] wire _SBDATAFieldsReg_1_2_T_1 = SBDATAWrEn_1 & _SBDATAFieldsReg_1_2_T; // @[SBA.scala:150:35, :160:{39,42}] wire _SBDATAFieldsReg_1_2_T_2 = ~SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28, :119:88, :160:67] wire _SBDATAFieldsReg_1_2_T_3 = _SBDATAFieldsReg_1_2_T_1 & _SBDATAFieldsReg_1_2_T_2; // @[SBA.scala:160:{39,64,67}] wire _SBDATAFieldsReg_1_2_T_5 = _SBDATAFieldsReg_1_2_T_3 & _SBDATAFieldsReg_1_2_T_4; // @[SBA.scala:160:{64,94,97}] wire [7:0] _SBDATAFieldsReg_1_2_T_6 = SBDATAWrData_1[23:16]; // @[SBA.scala:147:35, :160:133] wire [7:0] _SBDATAFieldsReg_1_2_T_7 = _sb2tlOpt_io_rdLoad_6 ? _sb2tlOpt_io_dataOut : SBDATAFieldsReg_1_2; // @[SBA.scala:143:30, :161:24] wire [7:0] _SBDATAFieldsReg_1_2_T_8 = _SBDATAFieldsReg_1_2_T_5 ? _SBDATAFieldsReg_1_2_T_6 : _SBDATAFieldsReg_1_2_T_7; // @[SBA.scala:160:{24,94,133}, :161:24] wire _SBDATAFieldsReg_1_3_T = ~SBCSFieldsReg_sbbusy; // @[SBA.scala:47:28, :119:63, :160:42] wire _SBDATAFieldsReg_1_3_T_1 = SBDATAWrEn_1 & _SBDATAFieldsReg_1_3_T; // @[SBA.scala:150:35, :160:{39,42}] wire _SBDATAFieldsReg_1_3_T_2 = ~SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28, :119:88, :160:67] wire _SBDATAFieldsReg_1_3_T_3 = _SBDATAFieldsReg_1_3_T_1 & _SBDATAFieldsReg_1_3_T_2; // @[SBA.scala:160:{39,64,67}] wire _SBDATAFieldsReg_1_3_T_5 = _SBDATAFieldsReg_1_3_T_3 & _SBDATAFieldsReg_1_3_T_4; // @[SBA.scala:160:{64,94,97}] wire [7:0] _SBDATAFieldsReg_1_3_T_6 = SBDATAWrData_1[31:24]; // @[SBA.scala:147:35, :160:133] wire [7:0] _SBDATAFieldsReg_1_3_T_7 = _sb2tlOpt_io_rdLoad_7 ? _sb2tlOpt_io_dataOut : SBDATAFieldsReg_1_3; // @[SBA.scala:143:30, :161:24] wire [7:0] _SBDATAFieldsReg_1_3_T_8 = _SBDATAFieldsReg_1_3_T_5 ? _SBDATAFieldsReg_1_3_T_6 : _SBDATAFieldsReg_1_3_T_7; // @[SBA.scala:160:{24,94,133}, :161:24] wire [15:0] _GEN_5 = {SBDATAFieldsReg_1_1, SBDATAFieldsReg_1_0}; // @[SBA.scala:143:30, :165:31] wire [15:0] SBDATARdData_1_lo; // @[SBA.scala:165:31] assign SBDATARdData_1_lo = _GEN_5; // @[SBA.scala:165:31] wire [15:0] sb2tlOpt_io_dataIn_lo_hi_lo; // @[SBA.scala:175:85] assign sb2tlOpt_io_dataIn_lo_hi_lo = _GEN_5; // @[SBA.scala:165:31, :175:85] wire [15:0] _GEN_6 = {SBDATAFieldsReg_1_3, SBDATAFieldsReg_1_2}; // @[SBA.scala:143:30, :165:31] wire [15:0] SBDATARdData_1_hi; // @[SBA.scala:165:31] assign SBDATARdData_1_hi = _GEN_6; // @[SBA.scala:165:31] wire [15:0] sb2tlOpt_io_dataIn_lo_hi_hi; // @[SBA.scala:175:85] assign sb2tlOpt_io_dataIn_lo_hi_hi = _GEN_6; // @[SBA.scala:165:31, :175:85] assign _SBDATARdData_1_T = {SBDATARdData_1_hi, SBDATARdData_1_lo}; // @[SBA.scala:165:31] assign SBDATARdData_1 = _SBDATARdData_1_T; // @[SBA.scala:145:35, :165:31] wire [63:0] sb2tlOpt_io_dataIn_lo = {SBDATAWrData_1, SBDATAWrData_0}; // @[SBA.scala:147:35, :175:59] wire [127:0] _sb2tlOpt_io_dataIn_T = {64'h0, sb2tlOpt_io_dataIn_lo}; // @[SBA.scala:175:59] wire [31:0] sb2tlOpt_io_dataIn_lo_lo = {sb2tlOpt_io_dataIn_lo_lo_hi, sb2tlOpt_io_dataIn_lo_lo_lo}; // @[SBA.scala:175:85] wire [31:0] sb2tlOpt_io_dataIn_lo_hi = {sb2tlOpt_io_dataIn_lo_hi_hi, sb2tlOpt_io_dataIn_lo_hi_lo}; // @[SBA.scala:175:85] wire [63:0] sb2tlOpt_io_dataIn_lo_1 = {sb2tlOpt_io_dataIn_lo_hi, sb2tlOpt_io_dataIn_lo_lo}; // @[SBA.scala:175:85] wire [127:0] _sb2tlOpt_io_dataIn_T_1 = {64'h0, sb2tlOpt_io_dataIn_lo_1}; // @[SBA.scala:175:85] wire _sb2tlOpt_io_wrEn_T_10; // @[SBA.scala:199:156] wire [127:0] _sb2tlOpt_io_dataIn_T_2 = _sb2tlOpt_io_wrEn_T_10 ? _sb2tlOpt_io_dataIn_T : _sb2tlOpt_io_dataIn_T_1; // @[SBA.scala:175:{34,59,85}, :199:156] wire _anyDataRdEn_T = SBDATARdEn_0 | SBDATARdEn_1; // @[SBA.scala:149:35, :176:51] wire _anyDataRdEn_T_1 = _anyDataRdEn_T; // @[SBA.scala:176:51] assign _anyDataRdEn_T_2 = _anyDataRdEn_T_1; // @[SBA.scala:176:51] assign anyDataRdEn = _anyDataRdEn_T_2; // @[SBA.scala:43:34, :176:51] wire _anyDataWrEn_T = SBDATAWrEn_0 | SBDATAWrEn_1; // @[SBA.scala:150:35, :177:51] wire _anyDataWrEn_T_1 = _anyDataWrEn_T; // @[SBA.scala:177:51] assign _anyDataWrEn_T_2 = _anyDataWrEn_T_1; // @[SBA.scala:177:51] assign anyDataWrEn = _anyDataWrEn_T_2; // @[SBA.scala:44:34, :177:51] wire _tryRdEn_T = SBADDRESSWrEn_0 & SBCSFieldsReg_sbreadonaddr; // @[SBA.scala:47:28, :108:38, :180:37] wire _tryRdEn_T_1 = SBDATARdEn_0 & SBCSFieldsReg_sbreadondata; // @[SBA.scala:47:28, :149:35, :180:86] wire tryRdEn = _tryRdEn_T | _tryRdEn_T_1; // @[SBA.scala:180:{37,68,86}] wire _sb2tlOpt_io_rdEn_T = tryRdEn; // @[SBA.scala:180:68, :200:49] wire _sbAccessError_T = SBCSFieldsReg_sbaccess == 3'h0; // @[SBA.scala:47:28, :182:49] wire _T_204 = SBCSFieldsReg_sbaccess == 3'h1; // @[SBA.scala:47:28, :183:49] wire _sbAccessError_T_3; // @[SBA.scala:183:49] assign _sbAccessError_T_3 = _T_204; // @[SBA.scala:183:49] wire _sbAlignmentError_T; // @[SBA.scala:191:52] assign _sbAlignmentError_T = _T_204; // @[SBA.scala:183:49, :191:52] wire _T_211 = SBCSFieldsReg_sbaccess == 3'h2; // @[SBA.scala:47:28, :184:49] wire _sbAccessError_T_7; // @[SBA.scala:184:49] assign _sbAccessError_T_7 = _T_211; // @[SBA.scala:184:49] wire _sbAlignmentError_T_4; // @[SBA.scala:192:52] assign _sbAlignmentError_T_4 = _T_211; // @[SBA.scala:184:49, :192:52] wire _T_218 = SBCSFieldsReg_sbaccess == 3'h3; // @[SBA.scala:47:28, :185:49] wire _sbAccessError_T_11; // @[SBA.scala:185:49] assign _sbAccessError_T_11 = _T_218; // @[SBA.scala:185:49] wire _sbAlignmentError_T_9; // @[SBA.scala:193:52] assign _sbAlignmentError_T_9 = _T_218; // @[SBA.scala:185:49, :193:52] wire _T_225 = SBCSFieldsReg_sbaccess == 3'h4; // @[SBA.scala:47:28, :186:49] wire _sbAccessError_T_15; // @[SBA.scala:186:49] assign _sbAccessError_T_15 = _T_225; // @[SBA.scala:186:49] wire _sbAlignmentError_T_14; // @[SBA.scala:194:52] assign _sbAlignmentError_T_14 = _T_225; // @[SBA.scala:186:49, :194:52] wire _sbAccessError_T_17 = _sbAccessError_T_15; // @[SBA.scala:186:{49,58}] wire _sbAccessError_T_18 = _sbAccessError_T_17; // @[SBA.scala:185:97, :186:58] wire _sbAccessError_T_19 = SBCSFieldsReg_sbaccess > 3'h4; // @[SBA.scala:47:28, :186:124] wire sbAccessError = _sbAccessError_T_18 | _sbAccessError_T_19; // @[SBA.scala:185:97, :186:{97,124}] wire [31:0] _compareAddr_T; // @[SBA.scala:189:23] wire [31:0] compareAddr; // @[SBA.scala:188:27] assign _compareAddr_T = SBADDRESSWrEn_0 ? SBADDRESSWrData_0 : SBADDRESSFieldsReg_0; // @[SBA.scala:104:33, :106:38, :108:38, :189:23] assign compareAddr = _compareAddr_T; // @[SBA.scala:188:27, :189:23] wire _sbAlignmentError_T_1 = compareAddr[0]; // @[SBA.scala:188:27, :191:76] wire _sbAlignmentError_T_2 = _sbAlignmentError_T_1; // @[SBA.scala:191:{76,82}] wire _sbAlignmentError_T_3 = _sbAlignmentError_T & _sbAlignmentError_T_2; // @[SBA.scala:191:{52,61,82}] wire [1:0] _sbAlignmentError_T_5 = compareAddr[1:0]; // @[SBA.scala:188:27, :192:76] wire _sbAlignmentError_T_6 = |_sbAlignmentError_T_5; // @[SBA.scala:192:{76,82}] wire _sbAlignmentError_T_7 = _sbAlignmentError_T_4 & _sbAlignmentError_T_6; // @[SBA.scala:192:{52,61,82}] wire _sbAlignmentError_T_8 = _sbAlignmentError_T_3 | _sbAlignmentError_T_7; // @[SBA.scala:191:{61,91}, :192:61] wire [2:0] _sbAlignmentError_T_10 = compareAddr[2:0]; // @[SBA.scala:188:27, :193:76] wire _sbAlignmentError_T_11 = |_sbAlignmentError_T_10; // @[SBA.scala:193:{76,82}] wire _sbAlignmentError_T_12 = _sbAlignmentError_T_9 & _sbAlignmentError_T_11; // @[SBA.scala:193:{52,61,82}] wire _sbAlignmentError_T_13 = _sbAlignmentError_T_8 | _sbAlignmentError_T_12; // @[SBA.scala:191:91, :192:91, :193:61] wire [3:0] _sbAlignmentError_T_15 = compareAddr[3:0]; // @[SBA.scala:188:27, :194:76] wire _sbAlignmentError_T_16 = |_sbAlignmentError_T_15; // @[SBA.scala:194:{76,82}] wire _sbAlignmentError_T_17 = _sbAlignmentError_T_14 & _sbAlignmentError_T_16; // @[SBA.scala:194:{52,61,82}] wire sbAlignmentError = _sbAlignmentError_T_13 | _sbAlignmentError_T_17; // @[SBA.scala:192:91, :193:91, :194:61] wire _sb2tlOpt_io_wrEn_T_1 = ~SBCSFieldsReg_sbbusy; // @[SBA.scala:47:28, :119:63, :199:63] wire _sb2tlOpt_io_wrEn_T_2 = _sb2tlOpt_io_wrEn_T & _sb2tlOpt_io_wrEn_T_1; // @[SBA.scala:199:{49,60,63}] wire _sb2tlOpt_io_wrEn_T_3 = ~SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28, :119:88, :199:88] wire _sb2tlOpt_io_wrEn_T_4 = _sb2tlOpt_io_wrEn_T_2 & _sb2tlOpt_io_wrEn_T_3; // @[SBA.scala:199:{60,85,88}] wire _sb2tlOpt_io_wrEn_T_6 = _sb2tlOpt_io_wrEn_T_4 & _sb2tlOpt_io_wrEn_T_5; // @[SBA.scala:199:{85,115,118}] wire _sb2tlOpt_io_wrEn_T_7 = ~sbAccessError; // @[SBA.scala:186:97, :199:141] wire _sb2tlOpt_io_wrEn_T_8 = _sb2tlOpt_io_wrEn_T_6 & _sb2tlOpt_io_wrEn_T_7; // @[SBA.scala:199:{115,138,141}] wire _sb2tlOpt_io_wrEn_T_9 = ~sbAlignmentError; // @[SBA.scala:193:91, :199:159] assign _sb2tlOpt_io_wrEn_T_10 = _sb2tlOpt_io_wrEn_T_8 & _sb2tlOpt_io_wrEn_T_9; // @[SBA.scala:199:{138,156,159}] wire _sb2tlOpt_io_rdEn_T_1 = ~SBCSFieldsReg_sbbusy; // @[SBA.scala:47:28, :119:63, :200:63] wire _sb2tlOpt_io_rdEn_T_2 = _sb2tlOpt_io_rdEn_T & _sb2tlOpt_io_rdEn_T_1; // @[SBA.scala:200:{49,60,63}] wire _sb2tlOpt_io_rdEn_T_3 = ~SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28, :119:88, :200:88] wire _sb2tlOpt_io_rdEn_T_4 = _sb2tlOpt_io_rdEn_T_2 & _sb2tlOpt_io_rdEn_T_3; // @[SBA.scala:200:{60,85,88}] wire _sb2tlOpt_io_rdEn_T_6 = _sb2tlOpt_io_rdEn_T_4 & _sb2tlOpt_io_rdEn_T_5; // @[SBA.scala:200:{85,115,118}] wire _sb2tlOpt_io_rdEn_T_7 = ~sbAccessError; // @[SBA.scala:186:97, :199:141, :200:141] wire _sb2tlOpt_io_rdEn_T_8 = _sb2tlOpt_io_rdEn_T_6 & _sb2tlOpt_io_rdEn_T_7; // @[SBA.scala:200:{115,138,141}] wire _sb2tlOpt_io_rdEn_T_9 = ~sbAlignmentError; // @[SBA.scala:193:91, :199:159, :200:159] wire _sb2tlOpt_io_rdEn_T_10 = _sb2tlOpt_io_rdEn_T_8 & _sb2tlOpt_io_rdEn_T_9; // @[SBA.scala:200:{138,156,159}] assign sbBusy = |_sb2tlOpt_io_sbStateOut; // @[SBA.scala:51:67, :203:46] assign SBCSRdData_sbbusy = sbBusy; // @[SBA.scala:60:38, :203:46] wire _SBCSFieldsReg_sbbusyerror_T = sbbusyerrorWrEn & SBCSWrData_sbbusyerror; // @[SBA.scala:63:38, :70:38, :208:60] wire _SBCSFieldsReg_sbbusyerror_T_1 = anyAddressWrEn & sbBusy; // @[SBA.scala:42:34, :203:46, :209:59] wire _SBCSFieldsReg_sbbusyerror_T_2 = anyDataRdEn | anyDataWrEn; // @[SBA.scala:43:34, :44:34, :210:57] wire _SBCSFieldsReg_sbbusyerror_T_3 = _SBCSFieldsReg_sbbusyerror_T_2 & sbBusy; // @[SBA.scala:203:46, :210:{57,73}] wire _SBCSFieldsReg_sbbusyerror_T_4 = _SBCSFieldsReg_sbbusyerror_T_3 | SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28, :210:{43,73}] wire _SBCSFieldsReg_sbbusyerror_T_5 = _SBCSFieldsReg_sbbusyerror_T_1 | _SBCSFieldsReg_sbbusyerror_T_4; // @[SBA.scala:209:{43,59}, :210:43] wire _SBCSFieldsReg_sbbusyerror_T_6 = ~_SBCSFieldsReg_sbbusyerror_T & _SBCSFieldsReg_sbbusyerror_T_5; // @[SBA.scala:208:{43,60}, :209:43] wire _SBCSFieldsReg_sbreadonaddr_T = sbreadonaddrWrEn ? SBCSWrData_sbreadonaddr : SBCSFieldsReg_sbreadonaddr; // @[SBA.scala:47:28, :63:38, :69:38, :211:43] wire _SBCSFieldsReg_sbautoincrement_T = sbautoincrementWrEn ? SBCSWrData_sbautoincrement : SBCSFieldsReg_sbautoincrement; // @[SBA.scala:47:28, :63:38, :67:38, :212:43] wire _SBCSFieldsReg_sbreadondata_T = sbreadondataWrEn ? SBCSWrData_sbreadondata : SBCSFieldsReg_sbreadondata; // @[SBA.scala:47:28, :63:38, :66:38, :213:43] wire [2:0] _SBCSFieldsReg_sbaccess_T = sbaccessWrEn ? SBCSWrData_sbaccess : SBCSFieldsReg_sbaccess; // @[SBA.scala:47:28, :63:38, :68:38, :214:43] reg sbErrorReg_0; // @[SBA.scala:219:25] reg sbErrorReg_1; // @[SBA.scala:219:25] reg sbErrorReg_2; // @[SBA.scala:219:25] wire _sbErrorReg_0_T = SBCSWrData_sberror[0]; // @[SBA.scala:63:38, :225:63] wire _sbErrorReg_0_T_1 = _sbErrorReg_0_T; // @[SBA.scala:225:{63,67}] wire _sbErrorReg_0_T_2 = sberrorWrEn & _sbErrorReg_0_T_1; // @[SBA.scala:65:38, :225:{42,67}] wire _sbErrorReg_0_T_3 = ~_sb2tlOpt_io_wrLegal; // @[SBA.scala:226:55] wire _sbErrorReg_0_T_4 = _sb2tlOpt_io_wrEn_T_10 & _sbErrorReg_0_T_3; // @[SBA.scala:199:156, :226:{52,55}] wire _sbErrorReg_0_T_5 = ~_sb2tlOpt_io_rdLegal; // @[SBA.scala:226:109] wire _sbErrorReg_0_T_6 = _sb2tlOpt_io_rdEn_T_10 & _sbErrorReg_0_T_5; // @[SBA.scala:200:156, :226:{106,109}] wire _sbErrorReg_0_T_7 = _sbErrorReg_0_T_4 | _sbErrorReg_0_T_6; // @[SBA.scala:226:{52,81,106}] wire _GEN_7 = SBDATAWrEn_0 | tryRdEn; // @[SBA.scala:150:35, :180:68, :227:39] wire _sbErrorReg_0_T_8; // @[SBA.scala:227:39] assign _sbErrorReg_0_T_8 = _GEN_7; // @[SBA.scala:227:39] wire _sbErrorReg_0_T_10; // @[SBA.scala:228:39] assign _sbErrorReg_0_T_10 = _GEN_7; // @[SBA.scala:227:39, :228:39] wire _sbErrorReg_1_T_8; // @[SBA.scala:227:39] assign _sbErrorReg_1_T_8 = _GEN_7; // @[SBA.scala:227:39] wire _sbErrorReg_1_T_10; // @[SBA.scala:228:39] assign _sbErrorReg_1_T_10 = _GEN_7; // @[SBA.scala:227:39, :228:39] wire _sbErrorReg_2_T_8; // @[SBA.scala:227:39] assign _sbErrorReg_2_T_8 = _GEN_7; // @[SBA.scala:227:39] wire _sbErrorReg_2_T_10; // @[SBA.scala:228:39] assign _sbErrorReg_2_T_10 = _GEN_7; // @[SBA.scala:227:39, :228:39] wire _sbErrorReg_0_T_9 = _sbErrorReg_0_T_8 & sbAlignmentError; // @[SBA.scala:193:91, :227:{39,51}] wire _sbErrorReg_0_T_11 = _sbErrorReg_0_T_10 & sbAccessError; // @[SBA.scala:186:97, :228:{39,51}] wire _sbErrorReg_0_T_13 = _sbErrorReg_0_T_12 & _sb2tlOpt_io_respError; // @[SBA.scala:229:{54,81}] wire _sbErrorReg_0_T_14 = _sbErrorReg_0_T_13 | sbErrorReg_0; // @[SBA.scala:219:25, :229:{29,81}] wire _sbErrorReg_0_T_15 = ~_sbErrorReg_0_T_11 & _sbErrorReg_0_T_14; // @[SBA.scala:228:{29,51}, :229:29] wire _sbErrorReg_0_T_16 = _sbErrorReg_0_T_9 | _sbErrorReg_0_T_15; // @[SBA.scala:227:{29,51}, :228:29] wire _sbErrorReg_0_T_17 = ~_sbErrorReg_0_T_7 & _sbErrorReg_0_T_16; // @[SBA.scala:226:{29,81}, :227:29] wire _sbErrorReg_0_T_18 = ~_sbErrorReg_0_T_2 & _sbErrorReg_0_T_17; // @[SBA.scala:225:{29,42}, :226:29] wire _sbErrorReg_1_T = SBCSWrData_sberror[1]; // @[SBA.scala:63:38, :225:63] wire _sbErrorReg_1_T_1 = _sbErrorReg_1_T; // @[SBA.scala:225:{63,67}] wire _sbErrorReg_1_T_2 = sberrorWrEn & _sbErrorReg_1_T_1; // @[SBA.scala:65:38, :225:{42,67}] wire _sbErrorReg_1_T_3 = ~_sb2tlOpt_io_wrLegal; // @[SBA.scala:226:55] wire _sbErrorReg_1_T_4 = _sb2tlOpt_io_wrEn_T_10 & _sbErrorReg_1_T_3; // @[SBA.scala:199:156, :226:{52,55}] wire _sbErrorReg_1_T_5 = ~_sb2tlOpt_io_rdLegal; // @[SBA.scala:226:109] wire _sbErrorReg_1_T_6 = _sb2tlOpt_io_rdEn_T_10 & _sbErrorReg_1_T_5; // @[SBA.scala:200:156, :226:{106,109}] wire _sbErrorReg_1_T_7 = _sbErrorReg_1_T_4 | _sbErrorReg_1_T_6; // @[SBA.scala:226:{52,81,106}] wire _sbErrorReg_1_T_9 = _sbErrorReg_1_T_8 & sbAlignmentError; // @[SBA.scala:193:91, :227:{39,51}] wire _sbErrorReg_1_T_11 = _sbErrorReg_1_T_10 & sbAccessError; // @[SBA.scala:186:97, :228:{39,51}] wire _sbErrorReg_1_T_13 = _sbErrorReg_1_T_12 & _sb2tlOpt_io_respError; // @[SBA.scala:229:{54,81}] wire _sbErrorReg_1_T_14 = _sbErrorReg_1_T_13 | sbErrorReg_1; // @[SBA.scala:219:25, :229:{29,81}] wire _sbErrorReg_1_T_15 = ~_sbErrorReg_1_T_11 & _sbErrorReg_1_T_14; // @[SBA.scala:228:{29,51}, :229:29] wire _sbErrorReg_1_T_16 = _sbErrorReg_1_T_9 | _sbErrorReg_1_T_15; // @[SBA.scala:227:{29,51}, :228:29] wire _sbErrorReg_1_T_17 = _sbErrorReg_1_T_7 | _sbErrorReg_1_T_16; // @[SBA.scala:226:{29,81}, :227:29] wire _sbErrorReg_1_T_18 = ~_sbErrorReg_1_T_2 & _sbErrorReg_1_T_17; // @[SBA.scala:225:{29,42}, :226:29] wire _sbErrorReg_2_T = SBCSWrData_sberror[2]; // @[SBA.scala:63:38, :225:63] wire _sbErrorReg_2_T_1 = _sbErrorReg_2_T; // @[SBA.scala:225:{63,67}] wire _sbErrorReg_2_T_2 = sberrorWrEn & _sbErrorReg_2_T_1; // @[SBA.scala:65:38, :225:{42,67}] wire _sbErrorReg_2_T_3 = ~_sb2tlOpt_io_wrLegal; // @[SBA.scala:226:55] wire _sbErrorReg_2_T_4 = _sb2tlOpt_io_wrEn_T_10 & _sbErrorReg_2_T_3; // @[SBA.scala:199:156, :226:{52,55}] wire _sbErrorReg_2_T_5 = ~_sb2tlOpt_io_rdLegal; // @[SBA.scala:226:109] wire _sbErrorReg_2_T_6 = _sb2tlOpt_io_rdEn_T_10 & _sbErrorReg_2_T_5; // @[SBA.scala:200:156, :226:{106,109}] wire _sbErrorReg_2_T_7 = _sbErrorReg_2_T_4 | _sbErrorReg_2_T_6; // @[SBA.scala:226:{52,81,106}] wire _sbErrorReg_2_T_9 = _sbErrorReg_2_T_8 & sbAlignmentError; // @[SBA.scala:193:91, :227:{39,51}] wire _sbErrorReg_2_T_11 = _sbErrorReg_2_T_10 & sbAccessError; // @[SBA.scala:186:97, :228:{39,51}] wire _sbErrorReg_2_T_13 = _sbErrorReg_2_T_12 & _sb2tlOpt_io_respError; // @[SBA.scala:229:{54,81}] wire _sbErrorReg_2_T_14 = _sbErrorReg_2_T_13 | sbErrorReg_2; // @[SBA.scala:219:25, :229:{29,81}] wire _sbErrorReg_2_T_15 = _sbErrorReg_2_T_11 | _sbErrorReg_2_T_14; // @[SBA.scala:228:{29,51}, :229:29] wire _sbErrorReg_2_T_16 = ~_sbErrorReg_2_T_9 & _sbErrorReg_2_T_15; // @[SBA.scala:227:{29,51}, :228:29] wire _sbErrorReg_2_T_17 = ~_sbErrorReg_2_T_7 & _sbErrorReg_2_T_16; // @[SBA.scala:226:{29,81}, :227:29] wire _sbErrorReg_2_T_18 = ~_sbErrorReg_2_T_2 & _sbErrorReg_2_T_17; // @[SBA.scala:225:{29,42}, :226:29] wire [1:0] SBCSRdData_sberror_lo = {sbErrorReg_1, sbErrorReg_0}; // @[SBA.scala:219:25, :240:42] wire [1:0] SBCSRdData_sberror_hi = {1'h0, sbErrorReg_2}; // @[SBA.scala:219:25, :240:42] wire [3:0] _SBCSRdData_sberror_T = {SBCSRdData_sberror_hi, SBCSRdData_sberror_lo}; // @[SBA.scala:240:42] assign SBCSRdData_sberror = _SBCSRdData_sberror_T[2:0]; // @[SBA.scala:60:38, :240:{28,42}] wire [31:0] _T_237 = {COMMANDReg_cmdtype, COMMANDReg_control}; // @[Debug.scala:1277:25, :1435:40] wire [31:0] _out_T_1545; // @[RegisterRouter.scala:87:24] assign _out_T_1545 = _T_237; // @[RegisterRouter.scala:87:24] wire _out_in_ready_T; // @[RegisterRouter.scala:87:24] wire [31:0] _accessRegisterCommandReg_T; // @[Debug.scala:1533:56] assign _accessRegisterCommandReg_T = _T_237; // @[Debug.scala:1435:40, :1533:56] assign dmiNodeIn_a_ready = in_ready; // @[RegisterRouter.scala:73:18] wire _in_bits_read_T; // @[RegisterRouter.scala:74:36] wire _out_front_valid_T = in_valid; // @[RegisterRouter.scala:73:18, :87:24] wire [6:0] _in_bits_index_T; // @[Edges.scala:192:34] wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24] wire [6:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24] wire [31:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24] wire [3:0] out_front_bits_mask = in_bits_mask; // @[RegisterRouter.scala:73:18, :87:24] wire out_front_bits_extra_tlrr_extra_source = in_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24] wire [1:0] out_front_bits_extra_tlrr_extra_size = in_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24] assign _in_bits_read_T = dmiNodeIn_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36] assign _in_bits_index_T = dmiNodeIn_a_bits_address[8:2]; // @[Edges.scala:192:34] assign in_bits_index = _in_bits_index_T; // @[RegisterRouter.scala:73:18] wire _out_front_ready_T = out_ready; // @[RegisterRouter.scala:87:24] wire _out_out_valid_T; // @[RegisterRouter.scala:87:24] assign dmiNodeIn_d_valid = out_valid; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24] wire _dmiNodeIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25] assign dmiNodeIn_d_bits_data = out_bits_data; // @[RegisterRouter.scala:87:24] assign dmiNodeIn_d_bits_d_source = out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [1:0] out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign dmiNodeIn_d_bits_d_size = out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign _out_in_ready_T = out_front_ready; // @[RegisterRouter.scala:87:24] assign _out_out_valid_T = out_front_valid; // @[RegisterRouter.scala:87:24] assign out_bits_read = out_front_bits_read; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_112 = out_front_bits_data; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_741 = out_front_bits_data; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_796 = out_front_bits_data; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_939 = out_front_bits_data; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1536 = out_front_bits_data; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1591 = out_front_bits_data; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_source = out_front_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_size = out_front_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] wire [6:0] _GEN_8 = out_front_bits_index & 7'h40; // @[RegisterRouter.scala:87:24] wire [6:0] out_findex; // @[RegisterRouter.scala:87:24] assign out_findex = _GEN_8; // @[RegisterRouter.scala:87:24] wire [6:0] out_bindex; // @[RegisterRouter.scala:87:24] assign out_bindex = _GEN_8; // @[RegisterRouter.scala:87:24] wire _GEN_9 = out_findex == 7'h0; // @[RegisterRouter.scala:87:24] wire _out_T; // @[RegisterRouter.scala:87:24] assign _out_T = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_2; // @[RegisterRouter.scala:87:24] assign _out_T_2 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_4; // @[RegisterRouter.scala:87:24] assign _out_T_4 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_6; // @[RegisterRouter.scala:87:24] assign _out_T_6 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_8; // @[RegisterRouter.scala:87:24] assign _out_T_8 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_10; // @[RegisterRouter.scala:87:24] assign _out_T_10 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_12; // @[RegisterRouter.scala:87:24] assign _out_T_12 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_14; // @[RegisterRouter.scala:87:24] assign _out_T_14 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_16; // @[RegisterRouter.scala:87:24] assign _out_T_16 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_18; // @[RegisterRouter.scala:87:24] assign _out_T_18 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_20; // @[RegisterRouter.scala:87:24] assign _out_T_20 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_22; // @[RegisterRouter.scala:87:24] assign _out_T_22 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_24; // @[RegisterRouter.scala:87:24] assign _out_T_24 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_26; // @[RegisterRouter.scala:87:24] assign _out_T_26 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_28; // @[RegisterRouter.scala:87:24] assign _out_T_28 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_30; // @[RegisterRouter.scala:87:24] assign _out_T_30 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_32; // @[RegisterRouter.scala:87:24] assign _out_T_32 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_34; // @[RegisterRouter.scala:87:24] assign _out_T_34 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_36; // @[RegisterRouter.scala:87:24] assign _out_T_36 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_38; // @[RegisterRouter.scala:87:24] assign _out_T_38 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_42; // @[RegisterRouter.scala:87:24] assign _out_T_42 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_44; // @[RegisterRouter.scala:87:24] assign _out_T_44 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_46; // @[RegisterRouter.scala:87:24] assign _out_T_46 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_48; // @[RegisterRouter.scala:87:24] assign _out_T_48 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_50; // @[RegisterRouter.scala:87:24] assign _out_T_50 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_52; // @[RegisterRouter.scala:87:24] assign _out_T_52 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_54; // @[RegisterRouter.scala:87:24] assign _out_T_54 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_56; // @[RegisterRouter.scala:87:24] assign _out_T_56 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_58; // @[RegisterRouter.scala:87:24] assign _out_T_58 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_60; // @[RegisterRouter.scala:87:24] assign _out_T_60 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_62; // @[RegisterRouter.scala:87:24] assign _out_T_62 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_64; // @[RegisterRouter.scala:87:24] assign _out_T_64 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_66; // @[RegisterRouter.scala:87:24] assign _out_T_66 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _GEN_10 = out_bindex == 7'h0; // @[RegisterRouter.scala:87:24] wire _out_T_1; // @[RegisterRouter.scala:87:24] assign _out_T_1 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_3; // @[RegisterRouter.scala:87:24] assign _out_T_3 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_5; // @[RegisterRouter.scala:87:24] assign _out_T_5 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_7; // @[RegisterRouter.scala:87:24] assign _out_T_7 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_9; // @[RegisterRouter.scala:87:24] assign _out_T_9 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_11; // @[RegisterRouter.scala:87:24] assign _out_T_11 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_13; // @[RegisterRouter.scala:87:24] assign _out_T_13 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_15; // @[RegisterRouter.scala:87:24] assign _out_T_15 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_17; // @[RegisterRouter.scala:87:24] assign _out_T_17 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_19; // @[RegisterRouter.scala:87:24] assign _out_T_19 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_21; // @[RegisterRouter.scala:87:24] assign _out_T_21 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_23; // @[RegisterRouter.scala:87:24] assign _out_T_23 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_25; // @[RegisterRouter.scala:87:24] assign _out_T_25 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_27; // @[RegisterRouter.scala:87:24] assign _out_T_27 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_29; // @[RegisterRouter.scala:87:24] assign _out_T_29 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_31; // @[RegisterRouter.scala:87:24] assign _out_T_31 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_33; // @[RegisterRouter.scala:87:24] assign _out_T_33 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_35; // @[RegisterRouter.scala:87:24] assign _out_T_35 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_37; // @[RegisterRouter.scala:87:24] assign _out_T_37 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_39; // @[RegisterRouter.scala:87:24] assign _out_T_39 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_43; // @[RegisterRouter.scala:87:24] assign _out_T_43 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_45; // @[RegisterRouter.scala:87:24] assign _out_T_45 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_47; // @[RegisterRouter.scala:87:24] assign _out_T_47 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_49; // @[RegisterRouter.scala:87:24] assign _out_T_49 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_51; // @[RegisterRouter.scala:87:24] assign _out_T_51 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_53; // @[RegisterRouter.scala:87:24] assign _out_T_53 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_55; // @[RegisterRouter.scala:87:24] assign _out_T_55 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_57; // @[RegisterRouter.scala:87:24] assign _out_T_57 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_59; // @[RegisterRouter.scala:87:24] assign _out_T_59 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_61; // @[RegisterRouter.scala:87:24] assign _out_T_61 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_63; // @[RegisterRouter.scala:87:24] assign _out_T_63 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_65; // @[RegisterRouter.scala:87:24] assign _out_T_65 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_67; // @[RegisterRouter.scala:87:24] assign _out_T_67 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_5 = _out_T_1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_61 = _out_T_3; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_9 = _out_T_5; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_41 = _out_T_7; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_35 = _out_T_9; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_8 = _out_T_11; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_4 = _out_T_13; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_47 = _out_T_15; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_10 = _out_T_17; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_56 = _out_T_19; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_42 = _out_T_21; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_24 = _out_T_23; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_37 = _out_T_25; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_46 = _out_T_27; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_57 = _out_T_29; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_6 = _out_T_31; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_60 = _out_T_33; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_38 = _out_T_35; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_33 = _out_T_37; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_45 = _out_T_39; // @[MuxLiteral.scala:49:48] wire _out_T_40 = out_findex == 7'h40; // @[RegisterRouter.scala:87:24] wire _out_T_41 = out_bindex == 7'h40; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_0 = _out_T_41; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_17 = _out_T_43; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_32 = _out_T_45; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_34 = _out_T_47; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_22 = _out_T_49; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_44 = _out_T_51; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_7 = _out_T_53; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_39 = _out_T_55; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_11 = _out_T_57; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_43 = _out_T_59; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_40 = _out_T_61; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_23 = _out_T_63; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_36 = _out_T_65; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_T_23; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_19 = _out_T_67; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_T_247; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_39; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_167; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_143; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_35; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_19; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_191; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_43; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_171; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_99; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_151; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_187; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_231; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_27; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_243; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_155; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_135; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_183; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_131; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_139; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_91; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_179; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_31; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_159; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_47; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_175; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_163; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_95; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_147; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_79; // @[RegisterRouter.scala:87:24] wire out_rivalid_0; // @[RegisterRouter.scala:87:24] wire out_rivalid_1; // @[RegisterRouter.scala:87:24] wire out_rivalid_2; // @[RegisterRouter.scala:87:24] wire out_rivalid_3; // @[RegisterRouter.scala:87:24] wire out_rivalid_4; // @[RegisterRouter.scala:87:24] wire out_rivalid_5; // @[RegisterRouter.scala:87:24] wire out_rivalid_6; // @[RegisterRouter.scala:87:24] wire out_rivalid_7; // @[RegisterRouter.scala:87:24] wire out_rivalid_8; // @[RegisterRouter.scala:87:24] wire out_rivalid_9; // @[RegisterRouter.scala:87:24] wire out_rivalid_10; // @[RegisterRouter.scala:87:24] wire out_rivalid_11; // @[RegisterRouter.scala:87:24] wire out_rivalid_12; // @[RegisterRouter.scala:87:24] wire out_rivalid_13; // @[RegisterRouter.scala:87:24] wire out_rivalid_14; // @[RegisterRouter.scala:87:24] wire out_rivalid_15; // @[RegisterRouter.scala:87:24] wire out_rivalid_16; // @[RegisterRouter.scala:87:24] wire out_rivalid_17; // @[RegisterRouter.scala:87:24] wire out_rivalid_18; // @[RegisterRouter.scala:87:24] wire out_rivalid_19; // @[RegisterRouter.scala:87:24] wire out_rivalid_20; // @[RegisterRouter.scala:87:24] wire out_rivalid_21; // @[RegisterRouter.scala:87:24] wire out_rivalid_22; // @[RegisterRouter.scala:87:24] wire out_rivalid_23; // @[RegisterRouter.scala:87:24] wire out_rivalid_24; // @[RegisterRouter.scala:87:24] wire out_rivalid_25; // @[RegisterRouter.scala:87:24] wire out_rivalid_26; // @[RegisterRouter.scala:87:24] wire out_rivalid_27; // @[RegisterRouter.scala:87:24] wire out_rivalid_28; // @[RegisterRouter.scala:87:24] wire out_rivalid_29; // @[RegisterRouter.scala:87:24] wire out_rivalid_30; // @[RegisterRouter.scala:87:24] wire out_rivalid_31; // @[RegisterRouter.scala:87:24] wire out_rivalid_32; // @[RegisterRouter.scala:87:24] wire out_rivalid_33; // @[RegisterRouter.scala:87:24] wire out_rivalid_34; // @[RegisterRouter.scala:87:24] wire out_rivalid_35; // @[RegisterRouter.scala:87:24] wire out_rivalid_36; // @[RegisterRouter.scala:87:24] wire out_rivalid_37; // @[RegisterRouter.scala:87:24] wire out_rivalid_38; // @[RegisterRouter.scala:87:24] wire out_rivalid_39; // @[RegisterRouter.scala:87:24] wire out_rivalid_40; // @[RegisterRouter.scala:87:24] wire out_rivalid_41; // @[RegisterRouter.scala:87:24] wire out_rivalid_42; // @[RegisterRouter.scala:87:24] wire out_rivalid_43; // @[RegisterRouter.scala:87:24] wire out_rivalid_44; // @[RegisterRouter.scala:87:24] wire out_rivalid_45; // @[RegisterRouter.scala:87:24] wire out_rivalid_46; // @[RegisterRouter.scala:87:24] wire out_rivalid_47; // @[RegisterRouter.scala:87:24] wire out_rivalid_48; // @[RegisterRouter.scala:87:24] wire out_rivalid_49; // @[RegisterRouter.scala:87:24] wire out_rivalid_50; // @[RegisterRouter.scala:87:24] wire out_rivalid_51; // @[RegisterRouter.scala:87:24] wire out_rivalid_52; // @[RegisterRouter.scala:87:24] wire out_rivalid_53; // @[RegisterRouter.scala:87:24] wire out_rivalid_54; // @[RegisterRouter.scala:87:24] wire out_rivalid_55; // @[RegisterRouter.scala:87:24] wire out_rivalid_56; // @[RegisterRouter.scala:87:24] wire out_rivalid_57; // @[RegisterRouter.scala:87:24] wire out_rivalid_58; // @[RegisterRouter.scala:87:24] wire out_rivalid_59; // @[RegisterRouter.scala:87:24] wire out_rivalid_60; // @[RegisterRouter.scala:87:24] wire out_rivalid_61; // @[RegisterRouter.scala:87:24] wire out_rivalid_62; // @[RegisterRouter.scala:87:24] wire out_rivalid_63; // @[RegisterRouter.scala:87:24] wire out_rivalid_64; // @[RegisterRouter.scala:87:24] wire out_rivalid_65; // @[RegisterRouter.scala:87:24] wire out_rivalid_66; // @[RegisterRouter.scala:87:24] wire out_rivalid_67; // @[RegisterRouter.scala:87:24] wire out_rivalid_68; // @[RegisterRouter.scala:87:24] wire out_rivalid_69; // @[RegisterRouter.scala:87:24] wire out_rivalid_70; // @[RegisterRouter.scala:87:24] wire out_rivalid_71; // @[RegisterRouter.scala:87:24] wire out_rivalid_72; // @[RegisterRouter.scala:87:24] wire out_rivalid_73; // @[RegisterRouter.scala:87:24] wire out_rivalid_74; // @[RegisterRouter.scala:87:24] wire out_rivalid_75; // @[RegisterRouter.scala:87:24] wire out_rivalid_76; // @[RegisterRouter.scala:87:24] wire out_rivalid_77; // @[RegisterRouter.scala:87:24] wire out_rivalid_78; // @[RegisterRouter.scala:87:24] wire out_rivalid_79; // @[RegisterRouter.scala:87:24] wire out_rivalid_80; // @[RegisterRouter.scala:87:24] wire out_rivalid_81; // @[RegisterRouter.scala:87:24] wire out_rivalid_82; // @[RegisterRouter.scala:87:24] wire out_rivalid_83; // @[RegisterRouter.scala:87:24] wire out_rivalid_84; // @[RegisterRouter.scala:87:24] wire out_rivalid_85; // @[RegisterRouter.scala:87:24] wire out_rivalid_86; // @[RegisterRouter.scala:87:24] wire out_rivalid_87; // @[RegisterRouter.scala:87:24] wire out_rivalid_88; // @[RegisterRouter.scala:87:24] wire out_rivalid_89; // @[RegisterRouter.scala:87:24] wire out_rivalid_90; // @[RegisterRouter.scala:87:24] wire out_rivalid_91; // @[RegisterRouter.scala:87:24] wire out_rivalid_92; // @[RegisterRouter.scala:87:24] wire out_rivalid_93; // @[RegisterRouter.scala:87:24] wire out_rivalid_94; // @[RegisterRouter.scala:87:24] wire out_rivalid_95; // @[RegisterRouter.scala:87:24] wire out_rivalid_96; // @[RegisterRouter.scala:87:24] wire out_rivalid_97; // @[RegisterRouter.scala:87:24] wire out_rivalid_98; // @[RegisterRouter.scala:87:24] wire out_rivalid_99; // @[RegisterRouter.scala:87:24] wire out_rivalid_100; // @[RegisterRouter.scala:87:24] wire out_rivalid_101; // @[RegisterRouter.scala:87:24] wire out_rivalid_102; // @[RegisterRouter.scala:87:24] wire out_rivalid_103; // @[RegisterRouter.scala:87:24] wire out_rivalid_104; // @[RegisterRouter.scala:87:24] wire out_rivalid_105; // @[RegisterRouter.scala:87:24] wire out_rivalid_106; // @[RegisterRouter.scala:87:24] wire out_rivalid_107; // @[RegisterRouter.scala:87:24] wire out_rivalid_108; // @[RegisterRouter.scala:87:24] wire out_rivalid_109; // @[RegisterRouter.scala:87:24] wire out_rivalid_110; // @[RegisterRouter.scala:87:24] wire out_rivalid_111; // @[RegisterRouter.scala:87:24] wire out_rivalid_112; // @[RegisterRouter.scala:87:24] wire out_rivalid_113; // @[RegisterRouter.scala:87:24] wire out_rivalid_114; // @[RegisterRouter.scala:87:24] wire out_rivalid_115; // @[RegisterRouter.scala:87:24] wire out_rivalid_116; // @[RegisterRouter.scala:87:24] wire out_rivalid_117; // @[RegisterRouter.scala:87:24] wire out_rivalid_118; // @[RegisterRouter.scala:87:24] wire out_rivalid_119; // @[RegisterRouter.scala:87:24] wire out_rivalid_120; // @[RegisterRouter.scala:87:24] wire out_rivalid_121; // @[RegisterRouter.scala:87:24] wire out_rivalid_122; // @[RegisterRouter.scala:87:24] wire out_rivalid_123; // @[RegisterRouter.scala:87:24] wire out_rivalid_124; // @[RegisterRouter.scala:87:24] wire out_rivalid_125; // @[RegisterRouter.scala:87:24] wire out_rivalid_126; // @[RegisterRouter.scala:87:24] wire out_rivalid_127; // @[RegisterRouter.scala:87:24] wire out_rivalid_128; // @[RegisterRouter.scala:87:24] wire out_rivalid_129; // @[RegisterRouter.scala:87:24] wire out_rivalid_130; // @[RegisterRouter.scala:87:24] wire out_rivalid_131; // @[RegisterRouter.scala:87:24] wire out_rivalid_132; // @[RegisterRouter.scala:87:24] wire out_rivalid_133; // @[RegisterRouter.scala:87:24] wire out_rivalid_134; // @[RegisterRouter.scala:87:24] wire out_rivalid_135; // @[RegisterRouter.scala:87:24] wire out_rivalid_136; // @[RegisterRouter.scala:87:24] wire out_rivalid_137; // @[RegisterRouter.scala:87:24] wire out_rivalid_138; // @[RegisterRouter.scala:87:24] wire out_rivalid_139; // @[RegisterRouter.scala:87:24] wire out_rivalid_140; // @[RegisterRouter.scala:87:24] wire out_rivalid_141; // @[RegisterRouter.scala:87:24] wire out_rivalid_142; // @[RegisterRouter.scala:87:24] wire out_rivalid_143; // @[RegisterRouter.scala:87:24] wire out_rivalid_144; // @[RegisterRouter.scala:87:24] wire out_rivalid_145; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_24; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_248; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_40; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_168; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_144; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_36; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_20; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_192; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_44; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_172; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_100; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_152; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_188; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_232; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_28; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_244; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_156; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_136; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_184; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_132; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_140; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_92; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_180; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_32; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_160; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_48; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_176; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_164; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_96; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_148; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_80; // @[RegisterRouter.scala:87:24] wire out_wivalid_0; // @[RegisterRouter.scala:87:24] wire out_wivalid_1; // @[RegisterRouter.scala:87:24] wire out_wivalid_2; // @[RegisterRouter.scala:87:24] wire out_wivalid_3; // @[RegisterRouter.scala:87:24] wire out_wivalid_4; // @[RegisterRouter.scala:87:24] wire out_wivalid_5; // @[RegisterRouter.scala:87:24] wire out_wivalid_6; // @[RegisterRouter.scala:87:24] wire out_wivalid_7; // @[RegisterRouter.scala:87:24] wire out_wivalid_8; // @[RegisterRouter.scala:87:24] wire out_wivalid_9; // @[RegisterRouter.scala:87:24] wire out_wivalid_10; // @[RegisterRouter.scala:87:24] wire out_wivalid_11; // @[RegisterRouter.scala:87:24] wire out_wivalid_12; // @[RegisterRouter.scala:87:24] wire out_wivalid_13; // @[RegisterRouter.scala:87:24] wire out_wivalid_14; // @[RegisterRouter.scala:87:24] wire out_wivalid_15; // @[RegisterRouter.scala:87:24] wire out_wivalid_16; // @[RegisterRouter.scala:87:24] wire out_wivalid_17; // @[RegisterRouter.scala:87:24] wire out_wivalid_18; // @[RegisterRouter.scala:87:24] wire out_wivalid_19; // @[RegisterRouter.scala:87:24] wire out_wivalid_20; // @[RegisterRouter.scala:87:24] wire out_wivalid_21; // @[RegisterRouter.scala:87:24] wire out_wivalid_22; // @[RegisterRouter.scala:87:24] wire out_wivalid_23; // @[RegisterRouter.scala:87:24] wire out_wivalid_24; // @[RegisterRouter.scala:87:24] wire out_wivalid_25; // @[RegisterRouter.scala:87:24] wire out_wivalid_26; // @[RegisterRouter.scala:87:24] wire out_wivalid_27; // @[RegisterRouter.scala:87:24] wire out_wivalid_28; // @[RegisterRouter.scala:87:24] wire out_wivalid_29; // @[RegisterRouter.scala:87:24] wire out_wivalid_30; // @[RegisterRouter.scala:87:24] wire out_wivalid_31; // @[RegisterRouter.scala:87:24] wire out_wivalid_32; // @[RegisterRouter.scala:87:24] wire out_wivalid_33; // @[RegisterRouter.scala:87:24] wire out_wivalid_34; // @[RegisterRouter.scala:87:24] wire out_wivalid_35; // @[RegisterRouter.scala:87:24] wire out_wivalid_36; // @[RegisterRouter.scala:87:24] wire out_wivalid_37; // @[RegisterRouter.scala:87:24] wire out_wivalid_38; // @[RegisterRouter.scala:87:24] wire out_wivalid_39; // @[RegisterRouter.scala:87:24] wire out_wivalid_40; // @[RegisterRouter.scala:87:24] wire out_wivalid_41; // @[RegisterRouter.scala:87:24] wire out_wivalid_42; // @[RegisterRouter.scala:87:24] wire out_wivalid_43; // @[RegisterRouter.scala:87:24] wire out_wivalid_44; // @[RegisterRouter.scala:87:24] wire out_wivalid_45; // @[RegisterRouter.scala:87:24] wire out_wivalid_46; // @[RegisterRouter.scala:87:24] wire out_wivalid_47; // @[RegisterRouter.scala:87:24] wire out_wivalid_48; // @[RegisterRouter.scala:87:24] wire out_wivalid_49; // @[RegisterRouter.scala:87:24] wire out_wivalid_50; // @[RegisterRouter.scala:87:24] wire out_wivalid_51; // @[RegisterRouter.scala:87:24] wire out_wivalid_52; // @[RegisterRouter.scala:87:24] wire out_wivalid_53; // @[RegisterRouter.scala:87:24] wire out_wivalid_54; // @[RegisterRouter.scala:87:24] wire out_wivalid_55; // @[RegisterRouter.scala:87:24] wire out_wivalid_56; // @[RegisterRouter.scala:87:24] wire out_wivalid_57; // @[RegisterRouter.scala:87:24] wire out_wivalid_58; // @[RegisterRouter.scala:87:24] wire out_wivalid_59; // @[RegisterRouter.scala:87:24] wire out_wivalid_60; // @[RegisterRouter.scala:87:24] wire out_wivalid_61; // @[RegisterRouter.scala:87:24] wire out_wivalid_62; // @[RegisterRouter.scala:87:24] wire out_wivalid_63; // @[RegisterRouter.scala:87:24] wire out_wivalid_64; // @[RegisterRouter.scala:87:24] wire out_wivalid_65; // @[RegisterRouter.scala:87:24] wire out_wivalid_66; // @[RegisterRouter.scala:87:24] wire out_wivalid_67; // @[RegisterRouter.scala:87:24] wire out_wivalid_68; // @[RegisterRouter.scala:87:24] wire out_wivalid_69; // @[RegisterRouter.scala:87:24] wire out_wivalid_70; // @[RegisterRouter.scala:87:24] wire out_wivalid_71; // @[RegisterRouter.scala:87:24] wire out_wivalid_72; // @[RegisterRouter.scala:87:24] wire out_wivalid_73; // @[RegisterRouter.scala:87:24] wire out_wivalid_74; // @[RegisterRouter.scala:87:24] wire out_wivalid_75; // @[RegisterRouter.scala:87:24] wire out_wivalid_76; // @[RegisterRouter.scala:87:24] wire out_wivalid_77; // @[RegisterRouter.scala:87:24] wire out_wivalid_78; // @[RegisterRouter.scala:87:24] wire out_wivalid_79; // @[RegisterRouter.scala:87:24] wire out_wivalid_80; // @[RegisterRouter.scala:87:24] wire out_wivalid_81; // @[RegisterRouter.scala:87:24] wire out_wivalid_82; // @[RegisterRouter.scala:87:24] wire out_wivalid_83; // @[RegisterRouter.scala:87:24] wire out_wivalid_84; // @[RegisterRouter.scala:87:24] wire out_wivalid_85; // @[RegisterRouter.scala:87:24] wire out_wivalid_86; // @[RegisterRouter.scala:87:24] wire out_wivalid_87; // @[RegisterRouter.scala:87:24] wire out_wivalid_88; // @[RegisterRouter.scala:87:24] wire out_wivalid_89; // @[RegisterRouter.scala:87:24] wire out_wivalid_90; // @[RegisterRouter.scala:87:24] wire out_wivalid_91; // @[RegisterRouter.scala:87:24] wire out_wivalid_92; // @[RegisterRouter.scala:87:24] wire out_wivalid_93; // @[RegisterRouter.scala:87:24] wire out_wivalid_94; // @[RegisterRouter.scala:87:24] wire out_wivalid_95; // @[RegisterRouter.scala:87:24] wire out_wivalid_96; // @[RegisterRouter.scala:87:24] wire out_wivalid_97; // @[RegisterRouter.scala:87:24] wire out_wivalid_98; // @[RegisterRouter.scala:87:24] wire out_wivalid_99; // @[RegisterRouter.scala:87:24] wire out_wivalid_100; // @[RegisterRouter.scala:87:24] wire out_wivalid_101; // @[RegisterRouter.scala:87:24] wire out_wivalid_102; // @[RegisterRouter.scala:87:24] wire out_wivalid_103; // @[RegisterRouter.scala:87:24] wire out_wivalid_104; // @[RegisterRouter.scala:87:24] wire out_wivalid_105; // @[RegisterRouter.scala:87:24] wire out_wivalid_106; // @[RegisterRouter.scala:87:24] wire out_wivalid_107; // @[RegisterRouter.scala:87:24] wire out_wivalid_108; // @[RegisterRouter.scala:87:24] wire out_wivalid_109; // @[RegisterRouter.scala:87:24] wire out_wivalid_110; // @[RegisterRouter.scala:87:24] wire out_wivalid_111; // @[RegisterRouter.scala:87:24] wire out_wivalid_112; // @[RegisterRouter.scala:87:24] wire out_wivalid_113; // @[RegisterRouter.scala:87:24] wire out_wivalid_114; // @[RegisterRouter.scala:87:24] wire out_wivalid_115; // @[RegisterRouter.scala:87:24] wire out_wivalid_116; // @[RegisterRouter.scala:87:24] wire out_wivalid_117; // @[RegisterRouter.scala:87:24] wire out_wivalid_118; // @[RegisterRouter.scala:87:24] wire out_wivalid_119; // @[RegisterRouter.scala:87:24] wire out_wivalid_120; // @[RegisterRouter.scala:87:24] wire out_wivalid_121; // @[RegisterRouter.scala:87:24] wire out_wivalid_122; // @[RegisterRouter.scala:87:24] wire out_wivalid_123; // @[RegisterRouter.scala:87:24] wire out_wivalid_124; // @[RegisterRouter.scala:87:24] wire out_wivalid_125; // @[RegisterRouter.scala:87:24] wire out_wivalid_126; // @[RegisterRouter.scala:87:24] wire out_wivalid_127; // @[RegisterRouter.scala:87:24] wire out_wivalid_128; // @[RegisterRouter.scala:87:24] wire out_wivalid_129; // @[RegisterRouter.scala:87:24] wire out_wivalid_130; // @[RegisterRouter.scala:87:24] wire out_wivalid_131; // @[RegisterRouter.scala:87:24] wire out_wivalid_132; // @[RegisterRouter.scala:87:24] wire out_wivalid_133; // @[RegisterRouter.scala:87:24] wire out_wivalid_134; // @[RegisterRouter.scala:87:24] wire out_wivalid_135; // @[RegisterRouter.scala:87:24] wire out_wivalid_136; // @[RegisterRouter.scala:87:24] wire out_wivalid_137; // @[RegisterRouter.scala:87:24] wire out_wivalid_138; // @[RegisterRouter.scala:87:24] wire out_wivalid_139; // @[RegisterRouter.scala:87:24] wire out_wivalid_140; // @[RegisterRouter.scala:87:24] wire out_wivalid_141; // @[RegisterRouter.scala:87:24] wire out_wivalid_142; // @[RegisterRouter.scala:87:24] wire out_wivalid_143; // @[RegisterRouter.scala:87:24] wire out_wivalid_144; // @[RegisterRouter.scala:87:24] wire out_wivalid_145; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_23; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_247; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_39; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_167; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_143; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_35; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_19; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_191; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_43; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_171; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_99; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_151; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_187; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_231; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_27; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_243; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_155; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_135; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_183; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_131; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_139; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_91; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_179; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_31; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_159; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_47; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_175; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_163; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_95; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_147; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_79; // @[RegisterRouter.scala:87:24] wire out_roready_0; // @[RegisterRouter.scala:87:24] wire out_roready_1; // @[RegisterRouter.scala:87:24] wire out_roready_2; // @[RegisterRouter.scala:87:24] wire out_roready_3; // @[RegisterRouter.scala:87:24] wire out_roready_4; // @[RegisterRouter.scala:87:24] wire out_roready_5; // @[RegisterRouter.scala:87:24] wire out_roready_6; // @[RegisterRouter.scala:87:24] wire out_roready_7; // @[RegisterRouter.scala:87:24] wire out_roready_8; // @[RegisterRouter.scala:87:24] wire out_roready_9; // @[RegisterRouter.scala:87:24] wire out_roready_10; // @[RegisterRouter.scala:87:24] wire out_roready_11; // @[RegisterRouter.scala:87:24] wire out_roready_12; // @[RegisterRouter.scala:87:24] wire out_roready_13; // @[RegisterRouter.scala:87:24] wire out_roready_14; // @[RegisterRouter.scala:87:24] wire out_roready_15; // @[RegisterRouter.scala:87:24] wire out_roready_16; // @[RegisterRouter.scala:87:24] wire out_roready_17; // @[RegisterRouter.scala:87:24] wire out_roready_18; // @[RegisterRouter.scala:87:24] wire out_roready_19; // @[RegisterRouter.scala:87:24] wire out_roready_20; // @[RegisterRouter.scala:87:24] wire out_roready_21; // @[RegisterRouter.scala:87:24] wire out_roready_22; // @[RegisterRouter.scala:87:24] wire out_roready_23; // @[RegisterRouter.scala:87:24] wire out_roready_24; // @[RegisterRouter.scala:87:24] wire out_roready_25; // @[RegisterRouter.scala:87:24] wire out_roready_26; // @[RegisterRouter.scala:87:24] wire out_roready_27; // @[RegisterRouter.scala:87:24] wire out_roready_28; // @[RegisterRouter.scala:87:24] wire out_roready_29; // @[RegisterRouter.scala:87:24] wire out_roready_30; // @[RegisterRouter.scala:87:24] wire out_roready_31; // @[RegisterRouter.scala:87:24] wire out_roready_32; // @[RegisterRouter.scala:87:24] wire out_roready_33; // @[RegisterRouter.scala:87:24] wire out_roready_34; // @[RegisterRouter.scala:87:24] wire out_roready_35; // @[RegisterRouter.scala:87:24] wire out_roready_36; // @[RegisterRouter.scala:87:24] wire out_roready_37; // @[RegisterRouter.scala:87:24] wire out_roready_38; // @[RegisterRouter.scala:87:24] wire out_roready_39; // @[RegisterRouter.scala:87:24] wire out_roready_40; // @[RegisterRouter.scala:87:24] wire out_roready_41; // @[RegisterRouter.scala:87:24] wire out_roready_42; // @[RegisterRouter.scala:87:24] wire out_roready_43; // @[RegisterRouter.scala:87:24] wire out_roready_44; // @[RegisterRouter.scala:87:24] wire out_roready_45; // @[RegisterRouter.scala:87:24] wire out_roready_46; // @[RegisterRouter.scala:87:24] wire out_roready_47; // @[RegisterRouter.scala:87:24] wire out_roready_48; // @[RegisterRouter.scala:87:24] wire out_roready_49; // @[RegisterRouter.scala:87:24] wire out_roready_50; // @[RegisterRouter.scala:87:24] wire out_roready_51; // @[RegisterRouter.scala:87:24] wire out_roready_52; // @[RegisterRouter.scala:87:24] wire out_roready_53; // @[RegisterRouter.scala:87:24] wire out_roready_54; // @[RegisterRouter.scala:87:24] wire out_roready_55; // @[RegisterRouter.scala:87:24] wire out_roready_56; // @[RegisterRouter.scala:87:24] wire out_roready_57; // @[RegisterRouter.scala:87:24] wire out_roready_58; // @[RegisterRouter.scala:87:24] wire out_roready_59; // @[RegisterRouter.scala:87:24] wire out_roready_60; // @[RegisterRouter.scala:87:24] wire out_roready_61; // @[RegisterRouter.scala:87:24] wire out_roready_62; // @[RegisterRouter.scala:87:24] wire out_roready_63; // @[RegisterRouter.scala:87:24] wire out_roready_64; // @[RegisterRouter.scala:87:24] wire out_roready_65; // @[RegisterRouter.scala:87:24] wire out_roready_66; // @[RegisterRouter.scala:87:24] wire out_roready_67; // @[RegisterRouter.scala:87:24] wire out_roready_68; // @[RegisterRouter.scala:87:24] wire out_roready_69; // @[RegisterRouter.scala:87:24] wire out_roready_70; // @[RegisterRouter.scala:87:24] wire out_roready_71; // @[RegisterRouter.scala:87:24] wire out_roready_72; // @[RegisterRouter.scala:87:24] wire out_roready_73; // @[RegisterRouter.scala:87:24] wire out_roready_74; // @[RegisterRouter.scala:87:24] wire out_roready_75; // @[RegisterRouter.scala:87:24] wire out_roready_76; // @[RegisterRouter.scala:87:24] wire out_roready_77; // @[RegisterRouter.scala:87:24] wire out_roready_78; // @[RegisterRouter.scala:87:24] wire out_roready_79; // @[RegisterRouter.scala:87:24] wire out_roready_80; // @[RegisterRouter.scala:87:24] wire out_roready_81; // @[RegisterRouter.scala:87:24] wire out_roready_82; // @[RegisterRouter.scala:87:24] wire out_roready_83; // @[RegisterRouter.scala:87:24] wire out_roready_84; // @[RegisterRouter.scala:87:24] wire out_roready_85; // @[RegisterRouter.scala:87:24] wire out_roready_86; // @[RegisterRouter.scala:87:24] wire out_roready_87; // @[RegisterRouter.scala:87:24] wire out_roready_88; // @[RegisterRouter.scala:87:24] wire out_roready_89; // @[RegisterRouter.scala:87:24] wire out_roready_90; // @[RegisterRouter.scala:87:24] wire out_roready_91; // @[RegisterRouter.scala:87:24] wire out_roready_92; // @[RegisterRouter.scala:87:24] wire out_roready_93; // @[RegisterRouter.scala:87:24] wire out_roready_94; // @[RegisterRouter.scala:87:24] wire out_roready_95; // @[RegisterRouter.scala:87:24] wire out_roready_96; // @[RegisterRouter.scala:87:24] wire out_roready_97; // @[RegisterRouter.scala:87:24] wire out_roready_98; // @[RegisterRouter.scala:87:24] wire out_roready_99; // @[RegisterRouter.scala:87:24] wire out_roready_100; // @[RegisterRouter.scala:87:24] wire out_roready_101; // @[RegisterRouter.scala:87:24] wire out_roready_102; // @[RegisterRouter.scala:87:24] wire out_roready_103; // @[RegisterRouter.scala:87:24] wire out_roready_104; // @[RegisterRouter.scala:87:24] wire out_roready_105; // @[RegisterRouter.scala:87:24] wire out_roready_106; // @[RegisterRouter.scala:87:24] wire out_roready_107; // @[RegisterRouter.scala:87:24] wire out_roready_108; // @[RegisterRouter.scala:87:24] wire out_roready_109; // @[RegisterRouter.scala:87:24] wire out_roready_110; // @[RegisterRouter.scala:87:24] wire out_roready_111; // @[RegisterRouter.scala:87:24] wire out_roready_112; // @[RegisterRouter.scala:87:24] wire out_roready_113; // @[RegisterRouter.scala:87:24] wire out_roready_114; // @[RegisterRouter.scala:87:24] wire out_roready_115; // @[RegisterRouter.scala:87:24] wire out_roready_116; // @[RegisterRouter.scala:87:24] wire out_roready_117; // @[RegisterRouter.scala:87:24] wire out_roready_118; // @[RegisterRouter.scala:87:24] wire out_roready_119; // @[RegisterRouter.scala:87:24] wire out_roready_120; // @[RegisterRouter.scala:87:24] wire out_roready_121; // @[RegisterRouter.scala:87:24] wire out_roready_122; // @[RegisterRouter.scala:87:24] wire out_roready_123; // @[RegisterRouter.scala:87:24] wire out_roready_124; // @[RegisterRouter.scala:87:24] wire out_roready_125; // @[RegisterRouter.scala:87:24] wire out_roready_126; // @[RegisterRouter.scala:87:24] wire out_roready_127; // @[RegisterRouter.scala:87:24] wire out_roready_128; // @[RegisterRouter.scala:87:24] wire out_roready_129; // @[RegisterRouter.scala:87:24] wire out_roready_130; // @[RegisterRouter.scala:87:24] wire out_roready_131; // @[RegisterRouter.scala:87:24] wire out_roready_132; // @[RegisterRouter.scala:87:24] wire out_roready_133; // @[RegisterRouter.scala:87:24] wire out_roready_134; // @[RegisterRouter.scala:87:24] wire out_roready_135; // @[RegisterRouter.scala:87:24] wire out_roready_136; // @[RegisterRouter.scala:87:24] wire out_roready_137; // @[RegisterRouter.scala:87:24] wire out_roready_138; // @[RegisterRouter.scala:87:24] wire out_roready_139; // @[RegisterRouter.scala:87:24] wire out_roready_140; // @[RegisterRouter.scala:87:24] wire out_roready_141; // @[RegisterRouter.scala:87:24] wire out_roready_142; // @[RegisterRouter.scala:87:24] wire out_roready_143; // @[RegisterRouter.scala:87:24] wire out_roready_144; // @[RegisterRouter.scala:87:24] wire out_roready_145; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_24; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_248; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_40; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_168; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_144; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_36; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_20; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_192; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_44; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_172; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_100; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_152; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_188; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_232; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_28; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_244; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_156; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_136; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_184; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_132; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_140; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_92; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_180; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_32; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_160; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_48; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_176; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_164; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_96; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_148; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_80; // @[RegisterRouter.scala:87:24] wire out_woready_0; // @[RegisterRouter.scala:87:24] wire out_woready_1; // @[RegisterRouter.scala:87:24] wire out_woready_2; // @[RegisterRouter.scala:87:24] wire out_woready_3; // @[RegisterRouter.scala:87:24] wire out_woready_4; // @[RegisterRouter.scala:87:24] wire out_woready_5; // @[RegisterRouter.scala:87:24] wire out_woready_6; // @[RegisterRouter.scala:87:24] wire out_woready_7; // @[RegisterRouter.scala:87:24] wire out_woready_8; // @[RegisterRouter.scala:87:24] wire out_woready_9; // @[RegisterRouter.scala:87:24] wire out_woready_10; // @[RegisterRouter.scala:87:24] wire out_woready_11; // @[RegisterRouter.scala:87:24] wire out_woready_12; // @[RegisterRouter.scala:87:24] wire out_woready_13; // @[RegisterRouter.scala:87:24] wire out_woready_14; // @[RegisterRouter.scala:87:24] wire out_woready_15; // @[RegisterRouter.scala:87:24] wire out_woready_16; // @[RegisterRouter.scala:87:24] wire out_woready_17; // @[RegisterRouter.scala:87:24] wire out_woready_18; // @[RegisterRouter.scala:87:24] wire out_woready_19; // @[RegisterRouter.scala:87:24] wire out_woready_20; // @[RegisterRouter.scala:87:24] wire out_woready_21; // @[RegisterRouter.scala:87:24] wire out_woready_22; // @[RegisterRouter.scala:87:24] wire out_woready_23; // @[RegisterRouter.scala:87:24] wire out_woready_24; // @[RegisterRouter.scala:87:24] wire out_woready_25; // @[RegisterRouter.scala:87:24] wire out_woready_26; // @[RegisterRouter.scala:87:24] wire out_woready_27; // @[RegisterRouter.scala:87:24] wire out_woready_28; // @[RegisterRouter.scala:87:24] wire out_woready_29; // @[RegisterRouter.scala:87:24] wire out_woready_30; // @[RegisterRouter.scala:87:24] wire out_woready_31; // @[RegisterRouter.scala:87:24] wire out_woready_32; // @[RegisterRouter.scala:87:24] wire out_woready_33; // @[RegisterRouter.scala:87:24] wire out_woready_34; // @[RegisterRouter.scala:87:24] wire out_woready_35; // @[RegisterRouter.scala:87:24] wire out_woready_36; // @[RegisterRouter.scala:87:24] wire out_woready_37; // @[RegisterRouter.scala:87:24] wire out_woready_38; // @[RegisterRouter.scala:87:24] wire out_woready_39; // @[RegisterRouter.scala:87:24] wire out_woready_40; // @[RegisterRouter.scala:87:24] wire out_woready_41; // @[RegisterRouter.scala:87:24] wire out_woready_42; // @[RegisterRouter.scala:87:24] wire out_woready_43; // @[RegisterRouter.scala:87:24] wire out_woready_44; // @[RegisterRouter.scala:87:24] wire out_woready_45; // @[RegisterRouter.scala:87:24] wire out_woready_46; // @[RegisterRouter.scala:87:24] wire out_woready_47; // @[RegisterRouter.scala:87:24] wire out_woready_48; // @[RegisterRouter.scala:87:24] wire out_woready_49; // @[RegisterRouter.scala:87:24] wire out_woready_50; // @[RegisterRouter.scala:87:24] wire out_woready_51; // @[RegisterRouter.scala:87:24] wire out_woready_52; // @[RegisterRouter.scala:87:24] wire out_woready_53; // @[RegisterRouter.scala:87:24] wire out_woready_54; // @[RegisterRouter.scala:87:24] wire out_woready_55; // @[RegisterRouter.scala:87:24] wire out_woready_56; // @[RegisterRouter.scala:87:24] wire out_woready_57; // @[RegisterRouter.scala:87:24] wire out_woready_58; // @[RegisterRouter.scala:87:24] wire out_woready_59; // @[RegisterRouter.scala:87:24] wire out_woready_60; // @[RegisterRouter.scala:87:24] wire out_woready_61; // @[RegisterRouter.scala:87:24] wire out_woready_62; // @[RegisterRouter.scala:87:24] wire out_woready_63; // @[RegisterRouter.scala:87:24] wire out_woready_64; // @[RegisterRouter.scala:87:24] wire out_woready_65; // @[RegisterRouter.scala:87:24] wire out_woready_66; // @[RegisterRouter.scala:87:24] wire out_woready_67; // @[RegisterRouter.scala:87:24] wire out_woready_68; // @[RegisterRouter.scala:87:24] wire out_woready_69; // @[RegisterRouter.scala:87:24] wire out_woready_70; // @[RegisterRouter.scala:87:24] wire out_woready_71; // @[RegisterRouter.scala:87:24] wire out_woready_72; // @[RegisterRouter.scala:87:24] wire out_woready_73; // @[RegisterRouter.scala:87:24] wire out_woready_74; // @[RegisterRouter.scala:87:24] wire out_woready_75; // @[RegisterRouter.scala:87:24] wire out_woready_76; // @[RegisterRouter.scala:87:24] wire out_woready_77; // @[RegisterRouter.scala:87:24] wire out_woready_78; // @[RegisterRouter.scala:87:24] wire out_woready_79; // @[RegisterRouter.scala:87:24] wire out_woready_80; // @[RegisterRouter.scala:87:24] wire out_woready_81; // @[RegisterRouter.scala:87:24] wire out_woready_82; // @[RegisterRouter.scala:87:24] wire out_woready_83; // @[RegisterRouter.scala:87:24] wire out_woready_84; // @[RegisterRouter.scala:87:24] wire out_woready_85; // @[RegisterRouter.scala:87:24] wire out_woready_86; // @[RegisterRouter.scala:87:24] wire out_woready_87; // @[RegisterRouter.scala:87:24] wire out_woready_88; // @[RegisterRouter.scala:87:24] wire out_woready_89; // @[RegisterRouter.scala:87:24] wire out_woready_90; // @[RegisterRouter.scala:87:24] wire out_woready_91; // @[RegisterRouter.scala:87:24] wire out_woready_92; // @[RegisterRouter.scala:87:24] wire out_woready_93; // @[RegisterRouter.scala:87:24] wire out_woready_94; // @[RegisterRouter.scala:87:24] wire out_woready_95; // @[RegisterRouter.scala:87:24] wire out_woready_96; // @[RegisterRouter.scala:87:24] wire out_woready_97; // @[RegisterRouter.scala:87:24] wire out_woready_98; // @[RegisterRouter.scala:87:24] wire out_woready_99; // @[RegisterRouter.scala:87:24] wire out_woready_100; // @[RegisterRouter.scala:87:24] wire out_woready_101; // @[RegisterRouter.scala:87:24] wire out_woready_102; // @[RegisterRouter.scala:87:24] wire out_woready_103; // @[RegisterRouter.scala:87:24] wire out_woready_104; // @[RegisterRouter.scala:87:24] wire out_woready_105; // @[RegisterRouter.scala:87:24] wire out_woready_106; // @[RegisterRouter.scala:87:24] wire out_woready_107; // @[RegisterRouter.scala:87:24] wire out_woready_108; // @[RegisterRouter.scala:87:24] wire out_woready_109; // @[RegisterRouter.scala:87:24] wire out_woready_110; // @[RegisterRouter.scala:87:24] wire out_woready_111; // @[RegisterRouter.scala:87:24] wire out_woready_112; // @[RegisterRouter.scala:87:24] wire out_woready_113; // @[RegisterRouter.scala:87:24] wire out_woready_114; // @[RegisterRouter.scala:87:24] wire out_woready_115; // @[RegisterRouter.scala:87:24] wire out_woready_116; // @[RegisterRouter.scala:87:24] wire out_woready_117; // @[RegisterRouter.scala:87:24] wire out_woready_118; // @[RegisterRouter.scala:87:24] wire out_woready_119; // @[RegisterRouter.scala:87:24] wire out_woready_120; // @[RegisterRouter.scala:87:24] wire out_woready_121; // @[RegisterRouter.scala:87:24] wire out_woready_122; // @[RegisterRouter.scala:87:24] wire out_woready_123; // @[RegisterRouter.scala:87:24] wire out_woready_124; // @[RegisterRouter.scala:87:24] wire out_woready_125; // @[RegisterRouter.scala:87:24] wire out_woready_126; // @[RegisterRouter.scala:87:24] wire out_woready_127; // @[RegisterRouter.scala:87:24] wire out_woready_128; // @[RegisterRouter.scala:87:24] wire out_woready_129; // @[RegisterRouter.scala:87:24] wire out_woready_130; // @[RegisterRouter.scala:87:24] wire out_woready_131; // @[RegisterRouter.scala:87:24] wire out_woready_132; // @[RegisterRouter.scala:87:24] wire out_woready_133; // @[RegisterRouter.scala:87:24] wire out_woready_134; // @[RegisterRouter.scala:87:24] wire out_woready_135; // @[RegisterRouter.scala:87:24] wire out_woready_136; // @[RegisterRouter.scala:87:24] wire out_woready_137; // @[RegisterRouter.scala:87:24] wire out_woready_138; // @[RegisterRouter.scala:87:24] wire out_woready_139; // @[RegisterRouter.scala:87:24] wire out_woready_140; // @[RegisterRouter.scala:87:24] wire out_woready_141; // @[RegisterRouter.scala:87:24] wire out_woready_142; // @[RegisterRouter.scala:87:24] wire out_woready_143; // @[RegisterRouter.scala:87:24] wire out_woready_144; // @[RegisterRouter.scala:87:24] wire out_woready_145; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_4 = {8{_out_frontMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_5 = {8{_out_frontMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_6 = {8{_out_frontMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_7 = {8{_out_frontMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo = {_out_frontMask_T_5, _out_frontMask_T_4}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi = {_out_frontMask_T_7, _out_frontMask_T_6}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask = {out_frontMask_hi, out_frontMask_lo}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_rimask_T_4 = out_frontMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_wimask_T_4 = out_frontMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_rimask_T_63 = out_frontMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_wimask_T_63 = out_frontMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_rimask_T_68 = out_frontMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_wimask_T_68 = out_frontMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_rimask_T_81 = out_frontMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_wimask_T_81 = out_frontMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_rimask_T_140 = out_frontMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_wimask_T_140 = out_frontMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_rimask_T_145 = out_frontMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_wimask_T_145 = out_frontMask; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_4 = {8{_out_backMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_5 = {8{_out_backMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_6 = {8{_out_backMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_7 = {8{_out_backMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo = {_out_backMask_T_5, _out_backMask_T_4}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi = {_out_backMask_T_7, _out_backMask_T_6}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask = {out_backMask_hi, out_backMask_lo}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_romask_T_4 = out_backMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_womask_T_4 = out_backMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_romask_T_63 = out_backMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_womask_T_63 = out_backMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_romask_T_68 = out_backMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_womask_T_68 = out_backMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_romask_T_81 = out_backMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_womask_T_81 = out_backMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_romask_T_140 = out_backMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_womask_T_140 = out_backMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_romask_T_145 = out_backMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_womask_T_145 = out_backMask; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_5 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_5 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_9 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_9 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_13 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_13 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_17 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_17 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_21 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_21 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_25 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_25 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_29 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_29 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_48 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_48 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_52 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_52 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_55 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_55 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_59 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_59 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_64 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_64 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_69 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_69 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_73 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_73 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_77 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_77 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_101 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_101 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_105 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_105 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_116 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_116 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_120 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_120 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_124 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_124 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_128 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_128 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_132 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_132 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_136 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_136 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_141 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_141 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire out_rimask = |_out_rimask_T; // @[RegisterRouter.scala:87:24] wire out_wimask = &_out_wimask_T; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_5 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_5 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_9 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_9 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_13 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_13 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_17 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_17 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_21 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_21 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_25 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_25 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_29 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_29 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_48 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_48 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_52 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_52 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_55 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_55 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_59 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_59 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_64 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_64 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_69 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_69 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_73 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_73 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_77 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_77 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_101 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_101 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_105 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_105 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_116 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_116 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_120 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_120 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_124 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_124 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_128 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_128 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_132 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_132 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_136 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_136 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_141 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_141 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire out_romask = |_out_romask_T; // @[RegisterRouter.scala:87:24] wire out_womask = &_out_womask_T; // @[RegisterRouter.scala:87:24] wire out_f_rivalid = out_rivalid_0 & out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_69 = out_f_rivalid; // @[RegisterRouter.scala:87:24] assign out_f_roready = out_roready_0 & out_romask; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_4 = out_f_roready; // @[RegisterRouter.scala:87:24] wire _out_T_70 = out_f_roready; // @[RegisterRouter.scala:87:24] wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_71 = out_f_wivalid; // @[RegisterRouter.scala:87:24] assign out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_4 = out_f_woready; // @[RegisterRouter.scala:87:24] wire _out_T_72 = out_f_woready; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_68 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_123 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_167 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_211 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_255 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_299 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_343 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_387 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_578 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_622 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_653 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_697 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_752 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_807 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_851 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_895 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1119 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1163 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1272 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1316 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1360 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1404 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1448 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1492 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1547 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_4 = out_f_woready ? _out_T_68 : abstractDataMem_4; // @[RegisterRouter.scala:87:24] wire _out_T_73 = ~out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_74 = ~out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_75 = ~out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_76 = ~out_womask; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_78 = _out_T_77; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T = _out_T_78; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_6 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_6 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_10 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_10 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_14 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_14 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_18 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_18 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_22 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_22 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_26 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_26 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_30 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_30 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_49 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_49 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_53 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_53 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_56 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_56 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_60 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_60 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_65 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_65 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_70 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_70 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_74 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_74 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_78 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_78 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_102 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_102 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_106 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_106 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_117 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_117 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_121 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_121 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_125 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_125 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_129 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_129 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_133 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_133 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_137 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_137 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_142 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_142 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire out_rimask_1 = |_out_rimask_T_1; // @[RegisterRouter.scala:87:24] wire out_wimask_1 = &_out_wimask_T_1; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_6 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_6 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_10 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_10 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_14 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_14 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_18 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_18 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_22 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_22 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_26 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_26 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_30 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_30 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_49 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_49 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_53 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_53 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_56 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_56 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_60 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_60 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_65 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_65 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_70 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_70 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_74 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_74 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_78 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_78 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_102 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_102 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_106 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_106 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_117 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_117 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_121 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_121 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_125 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_125 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_129 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_129 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_133 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_133 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_137 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_137 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_142 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_142 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire out_romask_1 = |_out_romask_T_1; // @[RegisterRouter.scala:87:24] wire out_womask_1 = &_out_womask_T_1; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1 = out_rivalid_1 & out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_80 = out_f_rivalid_1; // @[RegisterRouter.scala:87:24] assign out_f_roready_1 = out_roready_1 & out_romask_1; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_5 = out_f_roready_1; // @[RegisterRouter.scala:87:24] wire _out_T_81 = out_f_roready_1; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1 = out_wivalid_1 & out_wimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_82 = out_f_wivalid_1; // @[RegisterRouter.scala:87:24] assign out_f_woready_1 = out_woready_1 & out_womask_1; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_5 = out_f_woready_1; // @[RegisterRouter.scala:87:24] wire _out_T_83 = out_f_woready_1; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_79 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_134 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_178 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_222 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_266 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_310 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_354 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_398 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_589 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_633 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_664 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_708 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_763 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_818 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_862 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_906 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1130 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1174 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1283 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1327 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1371 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1415 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1459 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1503 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1558 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_5 = out_f_woready_1 ? _out_T_79 : abstractDataMem_5; // @[RegisterRouter.scala:87:24] wire _out_T_84 = ~out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_85 = ~out_wimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_86 = ~out_romask_1; // @[RegisterRouter.scala:87:24] wire _out_T_87 = ~out_womask_1; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend = {abstractDataMem_5, _out_prepend_T}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_88 = out_prepend; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_89 = _out_T_88; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1 = _out_T_89; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_2 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_2 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_7 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_7 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_11 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_11 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_15 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_15 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_19 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_19 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_23 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_23 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_27 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_27 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_31 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_31 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_50 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_50 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_57 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_57 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_61 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_61 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_66 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_66 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_71 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_71 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_75 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_75 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_79 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_79 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_103 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_103 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_107 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_107 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_118 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_118 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_122 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_122 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_126 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_126 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_130 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_130 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_134 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_134 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_138 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_138 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_143 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_143 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire out_rimask_2 = |_out_rimask_T_2; // @[RegisterRouter.scala:87:24] wire out_wimask_2 = &_out_wimask_T_2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_2 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_2 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_7 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_7 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_11 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_11 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_15 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_15 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_19 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_19 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_23 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_23 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_27 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_27 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_31 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_31 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_50 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_50 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_57 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_57 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_61 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_61 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_66 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_66 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_71 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_71 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_75 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_75 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_79 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_79 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_103 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_103 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_107 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_107 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_118 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_118 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_122 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_122 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_126 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_126 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_130 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_130 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_134 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_134 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_138 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_138 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_143 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_143 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire out_romask_2 = |_out_romask_T_2; // @[RegisterRouter.scala:87:24] wire out_womask_2 = &_out_womask_T_2; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_2 = out_rivalid_2 & out_rimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_91 = out_f_rivalid_2; // @[RegisterRouter.scala:87:24] assign out_f_roready_2 = out_roready_2 & out_romask_2; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_6 = out_f_roready_2; // @[RegisterRouter.scala:87:24] wire _out_T_92 = out_f_roready_2; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_2 = out_wivalid_2 & out_wimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_93 = out_f_wivalid_2; // @[RegisterRouter.scala:87:24] assign out_f_woready_2 = out_woready_2 & out_womask_2; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_6 = out_f_woready_2; // @[RegisterRouter.scala:87:24] wire _out_T_94 = out_f_woready_2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_90 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_145 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_189 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_233 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_277 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_321 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_365 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_409 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_600 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_675 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_719 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_774 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_829 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_873 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_917 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1141 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1185 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1294 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1338 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1382 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1426 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1470 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1514 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1569 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_6 = out_f_woready_2 ? _out_T_90 : abstractDataMem_6; // @[RegisterRouter.scala:87:24] wire _out_T_95 = ~out_rimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_96 = ~out_wimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_97 = ~out_romask_2; // @[RegisterRouter.scala:87:24] wire _out_T_98 = ~out_womask_2; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1 = {abstractDataMem_6, _out_prepend_T_1}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_99 = out_prepend_1; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_100 = _out_T_99; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_2 = _out_T_100; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_3 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_3 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_8 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_8 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_12 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_12 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_16 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_16 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_20 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_20 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_24 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_24 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_28 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_28 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_32 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_32 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_51 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_51 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_58 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_58 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_62 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_62 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_67 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_67 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_72 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_72 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_76 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_76 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_80 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_80 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_104 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_104 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_108 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_108 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_119 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_119 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_123 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_123 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_127 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_127 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_131 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_131 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_135 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_135 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_139 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_139 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_144 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_144 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire out_rimask_3 = |_out_rimask_T_3; // @[RegisterRouter.scala:87:24] wire out_wimask_3 = &_out_wimask_T_3; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_3 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_3 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_8 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_8 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_12 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_12 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_16 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_16 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_20 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_20 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_24 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_24 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_28 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_28 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_32 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_32 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_51 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_51 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_58 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_58 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_62 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_62 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_67 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_67 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_72 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_72 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_76 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_76 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_80 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_80 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_104 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_104 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_108 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_108 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_119 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_119 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_123 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_123 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_127 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_127 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_131 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_131 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_135 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_135 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_139 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_139 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_144 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_144 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire out_romask_3 = |_out_romask_T_3; // @[RegisterRouter.scala:87:24] wire out_womask_3 = &_out_womask_T_3; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_3 = out_rivalid_3 & out_rimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_102 = out_f_rivalid_3; // @[RegisterRouter.scala:87:24] assign out_f_roready_3 = out_roready_3 & out_romask_3; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_7 = out_f_roready_3; // @[RegisterRouter.scala:87:24] wire _out_T_103 = out_f_roready_3; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_3 = out_wivalid_3 & out_wimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_104 = out_f_wivalid_3; // @[RegisterRouter.scala:87:24] assign out_f_woready_3 = out_woready_3 & out_womask_3; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_7 = out_f_woready_3; // @[RegisterRouter.scala:87:24] wire _out_T_105 = out_f_woready_3; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_101 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_156 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_200 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_244 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_288 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_332 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_376 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_420 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_611 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_686 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_730 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_785 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_840 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_884 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_928 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1152 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1196 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1305 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1349 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1393 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1437 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1481 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1525 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1580 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_7 = out_f_woready_3 ? _out_T_101 : abstractDataMem_7; // @[RegisterRouter.scala:87:24] wire _out_T_106 = ~out_rimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_107 = ~out_wimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_108 = ~out_romask_3; // @[RegisterRouter.scala:87:24] wire _out_T_109 = ~out_womask_3; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_2 = {abstractDataMem_7, _out_prepend_T_2}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_110 = out_prepend_2; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_111 = _out_T_110; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_5 = _out_T_111; // @[MuxLiteral.scala:49:48] wire out_rimask_4 = |_out_rimask_T_4; // @[RegisterRouter.scala:87:24] wire out_wimask_4 = &_out_wimask_T_4; // @[RegisterRouter.scala:87:24] wire out_romask_4 = |_out_romask_T_4; // @[RegisterRouter.scala:87:24] wire out_womask_4 = &_out_womask_T_4; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_4 = out_rivalid_4 & out_rimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_113 = out_f_rivalid_4; // @[RegisterRouter.scala:87:24] assign out_f_roready_4 = out_roready_4 & out_romask_4; // @[RegisterRouter.scala:87:24] assign SBDATARdEn_1 = out_f_roready_4; // @[RegisterRouter.scala:87:24] wire _out_T_114 = out_f_roready_4; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_4 = out_wivalid_4 & out_wimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_115 = out_f_wivalid_4; // @[RegisterRouter.scala:87:24] assign out_f_woready_4 = out_woready_4 & out_womask_4; // @[RegisterRouter.scala:87:24] assign SBDATAWrEn_1 = out_f_woready_4; // @[RegisterRouter.scala:87:24] wire _out_T_116 = out_f_woready_4; // @[RegisterRouter.scala:87:24] assign SBDATAWrData_1 = out_f_woready_4 ? _out_T_112 : 32'h0; // @[RegisterRouter.scala:87:24] wire _out_T_117 = ~out_rimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_118 = ~out_wimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_119 = ~out_romask_4; // @[RegisterRouter.scala:87:24] wire _out_T_120 = ~out_womask_4; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_122 = _out_T_121; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_61 = _out_T_122; // @[MuxLiteral.scala:49:48] wire out_rimask_5 = |_out_rimask_T_5; // @[RegisterRouter.scala:87:24] wire out_wimask_5 = &_out_wimask_T_5; // @[RegisterRouter.scala:87:24] wire out_romask_5 = |_out_romask_T_5; // @[RegisterRouter.scala:87:24] wire out_womask_5 = &_out_womask_T_5; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_5 = out_rivalid_5 & out_rimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_124 = out_f_rivalid_5; // @[RegisterRouter.scala:87:24] assign out_f_roready_5 = out_roready_5 & out_romask_5; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_20 = out_f_roready_5; // @[RegisterRouter.scala:87:24] wire _out_T_125 = out_f_roready_5; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_5 = out_wivalid_5 & out_wimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_126 = out_f_wivalid_5; // @[RegisterRouter.scala:87:24] assign out_f_woready_5 = out_woready_5 & out_womask_5; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_20 = out_f_woready_5; // @[RegisterRouter.scala:87:24] wire _out_T_127 = out_f_woready_5; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_20 = out_f_woready_5 ? _out_T_123 : abstractDataMem_20; // @[RegisterRouter.scala:87:24] wire _out_T_128 = ~out_rimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_129 = ~out_wimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_130 = ~out_romask_5; // @[RegisterRouter.scala:87:24] wire _out_T_131 = ~out_womask_5; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_133 = _out_T_132; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_3 = _out_T_133; // @[RegisterRouter.scala:87:24] wire out_rimask_6 = |_out_rimask_T_6; // @[RegisterRouter.scala:87:24] wire out_wimask_6 = &_out_wimask_T_6; // @[RegisterRouter.scala:87:24] wire out_romask_6 = |_out_romask_T_6; // @[RegisterRouter.scala:87:24] wire out_womask_6 = &_out_womask_T_6; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_6 = out_rivalid_6 & out_rimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_135 = out_f_rivalid_6; // @[RegisterRouter.scala:87:24] assign out_f_roready_6 = out_roready_6 & out_romask_6; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_21 = out_f_roready_6; // @[RegisterRouter.scala:87:24] wire _out_T_136 = out_f_roready_6; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_6 = out_wivalid_6 & out_wimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_137 = out_f_wivalid_6; // @[RegisterRouter.scala:87:24] assign out_f_woready_6 = out_woready_6 & out_womask_6; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_21 = out_f_woready_6; // @[RegisterRouter.scala:87:24] wire _out_T_138 = out_f_woready_6; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_21 = out_f_woready_6 ? _out_T_134 : abstractDataMem_21; // @[RegisterRouter.scala:87:24] wire _out_T_139 = ~out_rimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_140 = ~out_wimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_141 = ~out_romask_6; // @[RegisterRouter.scala:87:24] wire _out_T_142 = ~out_womask_6; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_3 = {abstractDataMem_21, _out_prepend_T_3}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_143 = out_prepend_3; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_144 = _out_T_143; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_4 = _out_T_144; // @[RegisterRouter.scala:87:24] wire out_rimask_7 = |_out_rimask_T_7; // @[RegisterRouter.scala:87:24] wire out_wimask_7 = &_out_wimask_T_7; // @[RegisterRouter.scala:87:24] wire out_romask_7 = |_out_romask_T_7; // @[RegisterRouter.scala:87:24] wire out_womask_7 = &_out_womask_T_7; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_7 = out_rivalid_7 & out_rimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_146 = out_f_rivalid_7; // @[RegisterRouter.scala:87:24] assign out_f_roready_7 = out_roready_7 & out_romask_7; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_22 = out_f_roready_7; // @[RegisterRouter.scala:87:24] wire _out_T_147 = out_f_roready_7; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_7 = out_wivalid_7 & out_wimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_148 = out_f_wivalid_7; // @[RegisterRouter.scala:87:24] assign out_f_woready_7 = out_woready_7 & out_womask_7; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_22 = out_f_woready_7; // @[RegisterRouter.scala:87:24] wire _out_T_149 = out_f_woready_7; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_22 = out_f_woready_7 ? _out_T_145 : abstractDataMem_22; // @[RegisterRouter.scala:87:24] wire _out_T_150 = ~out_rimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_151 = ~out_wimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_152 = ~out_romask_7; // @[RegisterRouter.scala:87:24] wire _out_T_153 = ~out_womask_7; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_4 = {abstractDataMem_22, _out_prepend_T_4}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_154 = out_prepend_4; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_155 = _out_T_154; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_5 = _out_T_155; // @[RegisterRouter.scala:87:24] wire out_rimask_8 = |_out_rimask_T_8; // @[RegisterRouter.scala:87:24] wire out_wimask_8 = &_out_wimask_T_8; // @[RegisterRouter.scala:87:24] wire out_romask_8 = |_out_romask_T_8; // @[RegisterRouter.scala:87:24] wire out_womask_8 = &_out_womask_T_8; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_8 = out_rivalid_8 & out_rimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_157 = out_f_rivalid_8; // @[RegisterRouter.scala:87:24] assign out_f_roready_8 = out_roready_8 & out_romask_8; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_23 = out_f_roready_8; // @[RegisterRouter.scala:87:24] wire _out_T_158 = out_f_roready_8; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_8 = out_wivalid_8 & out_wimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_159 = out_f_wivalid_8; // @[RegisterRouter.scala:87:24] assign out_f_woready_8 = out_woready_8 & out_womask_8; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_23 = out_f_woready_8; // @[RegisterRouter.scala:87:24] wire _out_T_160 = out_f_woready_8; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_23 = out_f_woready_8 ? _out_T_156 : abstractDataMem_23; // @[RegisterRouter.scala:87:24] wire _out_T_161 = ~out_rimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_162 = ~out_wimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_163 = ~out_romask_8; // @[RegisterRouter.scala:87:24] wire _out_T_164 = ~out_womask_8; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_5 = {abstractDataMem_23, _out_prepend_T_5}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_165 = out_prepend_5; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_166 = _out_T_165; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_9 = _out_T_166; // @[MuxLiteral.scala:49:48] wire out_rimask_9 = |_out_rimask_T_9; // @[RegisterRouter.scala:87:24] wire out_wimask_9 = &_out_wimask_T_9; // @[RegisterRouter.scala:87:24] wire out_romask_9 = |_out_romask_T_9; // @[RegisterRouter.scala:87:24] wire out_womask_9 = &_out_womask_T_9; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_9 = out_rivalid_9 & out_rimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_168 = out_f_rivalid_9; // @[RegisterRouter.scala:87:24] assign out_f_roready_9 = out_roready_9 & out_romask_9; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_36 = out_f_roready_9; // @[RegisterRouter.scala:87:24] wire _out_T_169 = out_f_roready_9; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_9 = out_wivalid_9 & out_wimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_170 = out_f_wivalid_9; // @[RegisterRouter.scala:87:24] assign out_f_woready_9 = out_woready_9 & out_womask_9; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_36 = out_f_woready_9; // @[RegisterRouter.scala:87:24] wire _out_T_171 = out_f_woready_9; // @[RegisterRouter.scala:87:24] assign programBufferNxt_36 = out_f_woready_9 ? _out_T_167 : programBufferMem_36; // @[RegisterRouter.scala:87:24] wire _out_T_172 = ~out_rimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_173 = ~out_wimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_174 = ~out_romask_9; // @[RegisterRouter.scala:87:24] wire _out_T_175 = ~out_womask_9; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_177 = _out_T_176; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_6 = _out_T_177; // @[RegisterRouter.scala:87:24] wire out_rimask_10 = |_out_rimask_T_10; // @[RegisterRouter.scala:87:24] wire out_wimask_10 = &_out_wimask_T_10; // @[RegisterRouter.scala:87:24] wire out_romask_10 = |_out_romask_T_10; // @[RegisterRouter.scala:87:24] wire out_womask_10 = &_out_womask_T_10; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_10 = out_rivalid_10 & out_rimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_179 = out_f_rivalid_10; // @[RegisterRouter.scala:87:24] assign out_f_roready_10 = out_roready_10 & out_romask_10; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_37 = out_f_roready_10; // @[RegisterRouter.scala:87:24] wire _out_T_180 = out_f_roready_10; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_10 = out_wivalid_10 & out_wimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_181 = out_f_wivalid_10; // @[RegisterRouter.scala:87:24] assign out_f_woready_10 = out_woready_10 & out_womask_10; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_37 = out_f_woready_10; // @[RegisterRouter.scala:87:24] wire _out_T_182 = out_f_woready_10; // @[RegisterRouter.scala:87:24] assign programBufferNxt_37 = out_f_woready_10 ? _out_T_178 : programBufferMem_37; // @[RegisterRouter.scala:87:24] wire _out_T_183 = ~out_rimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_184 = ~out_wimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_185 = ~out_romask_10; // @[RegisterRouter.scala:87:24] wire _out_T_186 = ~out_womask_10; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_6 = {programBufferMem_37, _out_prepend_T_6}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_187 = out_prepend_6; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_188 = _out_T_187; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_7 = _out_T_188; // @[RegisterRouter.scala:87:24] wire out_rimask_11 = |_out_rimask_T_11; // @[RegisterRouter.scala:87:24] wire out_wimask_11 = &_out_wimask_T_11; // @[RegisterRouter.scala:87:24] wire out_romask_11 = |_out_romask_T_11; // @[RegisterRouter.scala:87:24] wire out_womask_11 = &_out_womask_T_11; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_11 = out_rivalid_11 & out_rimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_190 = out_f_rivalid_11; // @[RegisterRouter.scala:87:24] assign out_f_roready_11 = out_roready_11 & out_romask_11; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_38 = out_f_roready_11; // @[RegisterRouter.scala:87:24] wire _out_T_191 = out_f_roready_11; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_11 = out_wivalid_11 & out_wimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_192 = out_f_wivalid_11; // @[RegisterRouter.scala:87:24] assign out_f_woready_11 = out_woready_11 & out_womask_11; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_38 = out_f_woready_11; // @[RegisterRouter.scala:87:24] wire _out_T_193 = out_f_woready_11; // @[RegisterRouter.scala:87:24] assign programBufferNxt_38 = out_f_woready_11 ? _out_T_189 : programBufferMem_38; // @[RegisterRouter.scala:87:24] wire _out_T_194 = ~out_rimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_195 = ~out_wimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_196 = ~out_romask_11; // @[RegisterRouter.scala:87:24] wire _out_T_197 = ~out_womask_11; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_7 = {programBufferMem_38, _out_prepend_T_7}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_198 = out_prepend_7; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_199 = _out_T_198; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_8 = _out_T_199; // @[RegisterRouter.scala:87:24] wire out_rimask_12 = |_out_rimask_T_12; // @[RegisterRouter.scala:87:24] wire out_wimask_12 = &_out_wimask_T_12; // @[RegisterRouter.scala:87:24] wire out_romask_12 = |_out_romask_T_12; // @[RegisterRouter.scala:87:24] wire out_womask_12 = &_out_womask_T_12; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_12 = out_rivalid_12 & out_rimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_201 = out_f_rivalid_12; // @[RegisterRouter.scala:87:24] assign out_f_roready_12 = out_roready_12 & out_romask_12; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_39 = out_f_roready_12; // @[RegisterRouter.scala:87:24] wire _out_T_202 = out_f_roready_12; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_12 = out_wivalid_12 & out_wimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_203 = out_f_wivalid_12; // @[RegisterRouter.scala:87:24] assign out_f_woready_12 = out_woready_12 & out_womask_12; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_39 = out_f_woready_12; // @[RegisterRouter.scala:87:24] wire _out_T_204 = out_f_woready_12; // @[RegisterRouter.scala:87:24] assign programBufferNxt_39 = out_f_woready_12 ? _out_T_200 : programBufferMem_39; // @[RegisterRouter.scala:87:24] wire _out_T_205 = ~out_rimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_206 = ~out_wimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_207 = ~out_romask_12; // @[RegisterRouter.scala:87:24] wire _out_T_208 = ~out_womask_12; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_8 = {programBufferMem_39, _out_prepend_T_8}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_209 = out_prepend_8; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_210 = _out_T_209; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_41 = _out_T_210; // @[MuxLiteral.scala:49:48] wire out_rimask_13 = |_out_rimask_T_13; // @[RegisterRouter.scala:87:24] wire out_wimask_13 = &_out_wimask_T_13; // @[RegisterRouter.scala:87:24] wire out_romask_13 = |_out_romask_T_13; // @[RegisterRouter.scala:87:24] wire out_womask_13 = &_out_womask_T_13; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_13 = out_rivalid_13 & out_rimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_212 = out_f_rivalid_13; // @[RegisterRouter.scala:87:24] assign out_f_roready_13 = out_roready_13 & out_romask_13; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_12 = out_f_roready_13; // @[RegisterRouter.scala:87:24] wire _out_T_213 = out_f_roready_13; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_13 = out_wivalid_13 & out_wimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_214 = out_f_wivalid_13; // @[RegisterRouter.scala:87:24] assign out_f_woready_13 = out_woready_13 & out_womask_13; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_12 = out_f_woready_13; // @[RegisterRouter.scala:87:24] wire _out_T_215 = out_f_woready_13; // @[RegisterRouter.scala:87:24] assign programBufferNxt_12 = out_f_woready_13 ? _out_T_211 : programBufferMem_12; // @[RegisterRouter.scala:87:24] wire _out_T_216 = ~out_rimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_217 = ~out_wimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_218 = ~out_romask_13; // @[RegisterRouter.scala:87:24] wire _out_T_219 = ~out_womask_13; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_221 = _out_T_220; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_9 = _out_T_221; // @[RegisterRouter.scala:87:24] wire out_rimask_14 = |_out_rimask_T_14; // @[RegisterRouter.scala:87:24] wire out_wimask_14 = &_out_wimask_T_14; // @[RegisterRouter.scala:87:24] wire out_romask_14 = |_out_romask_T_14; // @[RegisterRouter.scala:87:24] wire out_womask_14 = &_out_womask_T_14; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_14 = out_rivalid_14 & out_rimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_223 = out_f_rivalid_14; // @[RegisterRouter.scala:87:24] assign out_f_roready_14 = out_roready_14 & out_romask_14; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_13 = out_f_roready_14; // @[RegisterRouter.scala:87:24] wire _out_T_224 = out_f_roready_14; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_14 = out_wivalid_14 & out_wimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_225 = out_f_wivalid_14; // @[RegisterRouter.scala:87:24] assign out_f_woready_14 = out_woready_14 & out_womask_14; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_13 = out_f_woready_14; // @[RegisterRouter.scala:87:24] wire _out_T_226 = out_f_woready_14; // @[RegisterRouter.scala:87:24] assign programBufferNxt_13 = out_f_woready_14 ? _out_T_222 : programBufferMem_13; // @[RegisterRouter.scala:87:24] wire _out_T_227 = ~out_rimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_228 = ~out_wimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_229 = ~out_romask_14; // @[RegisterRouter.scala:87:24] wire _out_T_230 = ~out_womask_14; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_9 = {programBufferMem_13, _out_prepend_T_9}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_231 = out_prepend_9; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_232 = _out_T_231; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_10 = _out_T_232; // @[RegisterRouter.scala:87:24] wire out_rimask_15 = |_out_rimask_T_15; // @[RegisterRouter.scala:87:24] wire out_wimask_15 = &_out_wimask_T_15; // @[RegisterRouter.scala:87:24] wire out_romask_15 = |_out_romask_T_15; // @[RegisterRouter.scala:87:24] wire out_womask_15 = &_out_womask_T_15; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_15 = out_rivalid_15 & out_rimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_234 = out_f_rivalid_15; // @[RegisterRouter.scala:87:24] assign out_f_roready_15 = out_roready_15 & out_romask_15; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_14 = out_f_roready_15; // @[RegisterRouter.scala:87:24] wire _out_T_235 = out_f_roready_15; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_15 = out_wivalid_15 & out_wimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_236 = out_f_wivalid_15; // @[RegisterRouter.scala:87:24] assign out_f_woready_15 = out_woready_15 & out_womask_15; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_14 = out_f_woready_15; // @[RegisterRouter.scala:87:24] wire _out_T_237 = out_f_woready_15; // @[RegisterRouter.scala:87:24] assign programBufferNxt_14 = out_f_woready_15 ? _out_T_233 : programBufferMem_14; // @[RegisterRouter.scala:87:24] wire _out_T_238 = ~out_rimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_239 = ~out_wimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_240 = ~out_romask_15; // @[RegisterRouter.scala:87:24] wire _out_T_241 = ~out_womask_15; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_10 = {programBufferMem_14, _out_prepend_T_10}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_242 = out_prepend_10; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_243 = _out_T_242; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_11 = _out_T_243; // @[RegisterRouter.scala:87:24] wire out_rimask_16 = |_out_rimask_T_16; // @[RegisterRouter.scala:87:24] wire out_wimask_16 = &_out_wimask_T_16; // @[RegisterRouter.scala:87:24] wire out_romask_16 = |_out_romask_T_16; // @[RegisterRouter.scala:87:24] wire out_womask_16 = &_out_womask_T_16; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_16 = out_rivalid_16 & out_rimask_16; // @[RegisterRouter.scala:87:24] wire _out_T_245 = out_f_rivalid_16; // @[RegisterRouter.scala:87:24] assign out_f_roready_16 = out_roready_16 & out_romask_16; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_15 = out_f_roready_16; // @[RegisterRouter.scala:87:24] wire _out_T_246 = out_f_roready_16; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_16 = out_wivalid_16 & out_wimask_16; // @[RegisterRouter.scala:87:24] wire _out_T_247 = out_f_wivalid_16; // @[RegisterRouter.scala:87:24] assign out_f_woready_16 = out_woready_16 & out_womask_16; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_15 = out_f_woready_16; // @[RegisterRouter.scala:87:24] wire _out_T_248 = out_f_woready_16; // @[RegisterRouter.scala:87:24] assign programBufferNxt_15 = out_f_woready_16 ? _out_T_244 : programBufferMem_15; // @[RegisterRouter.scala:87:24] wire _out_T_249 = ~out_rimask_16; // @[RegisterRouter.scala:87:24] wire _out_T_250 = ~out_wimask_16; // @[RegisterRouter.scala:87:24] wire _out_T_251 = ~out_romask_16; // @[RegisterRouter.scala:87:24] wire _out_T_252 = ~out_womask_16; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_11 = {programBufferMem_15, _out_prepend_T_11}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_253 = out_prepend_11; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_254 = _out_T_253; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_35 = _out_T_254; // @[MuxLiteral.scala:49:48] wire out_rimask_17 = |_out_rimask_T_17; // @[RegisterRouter.scala:87:24] wire out_wimask_17 = &_out_wimask_T_17; // @[RegisterRouter.scala:87:24] wire out_romask_17 = |_out_romask_T_17; // @[RegisterRouter.scala:87:24] wire out_womask_17 = &_out_womask_T_17; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_17 = out_rivalid_17 & out_rimask_17; // @[RegisterRouter.scala:87:24] wire _out_T_256 = out_f_rivalid_17; // @[RegisterRouter.scala:87:24] assign out_f_roready_17 = out_roready_17 & out_romask_17; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_16 = out_f_roready_17; // @[RegisterRouter.scala:87:24] wire _out_T_257 = out_f_roready_17; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_17 = out_wivalid_17 & out_wimask_17; // @[RegisterRouter.scala:87:24] wire _out_T_258 = out_f_wivalid_17; // @[RegisterRouter.scala:87:24] assign out_f_woready_17 = out_woready_17 & out_womask_17; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_16 = out_f_woready_17; // @[RegisterRouter.scala:87:24] wire _out_T_259 = out_f_woready_17; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_16 = out_f_woready_17 ? _out_T_255 : abstractDataMem_16; // @[RegisterRouter.scala:87:24] wire _out_T_260 = ~out_rimask_17; // @[RegisterRouter.scala:87:24] wire _out_T_261 = ~out_wimask_17; // @[RegisterRouter.scala:87:24] wire _out_T_262 = ~out_romask_17; // @[RegisterRouter.scala:87:24] wire _out_T_263 = ~out_womask_17; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_265 = _out_T_264; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_12 = _out_T_265; // @[RegisterRouter.scala:87:24] wire out_rimask_18 = |_out_rimask_T_18; // @[RegisterRouter.scala:87:24] wire out_wimask_18 = &_out_wimask_T_18; // @[RegisterRouter.scala:87:24] wire out_romask_18 = |_out_romask_T_18; // @[RegisterRouter.scala:87:24] wire out_womask_18 = &_out_womask_T_18; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_18 = out_rivalid_18 & out_rimask_18; // @[RegisterRouter.scala:87:24] wire _out_T_267 = out_f_rivalid_18; // @[RegisterRouter.scala:87:24] assign out_f_roready_18 = out_roready_18 & out_romask_18; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_17 = out_f_roready_18; // @[RegisterRouter.scala:87:24] wire _out_T_268 = out_f_roready_18; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_18 = out_wivalid_18 & out_wimask_18; // @[RegisterRouter.scala:87:24] wire _out_T_269 = out_f_wivalid_18; // @[RegisterRouter.scala:87:24] assign out_f_woready_18 = out_woready_18 & out_womask_18; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_17 = out_f_woready_18; // @[RegisterRouter.scala:87:24] wire _out_T_270 = out_f_woready_18; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_17 = out_f_woready_18 ? _out_T_266 : abstractDataMem_17; // @[RegisterRouter.scala:87:24] wire _out_T_271 = ~out_rimask_18; // @[RegisterRouter.scala:87:24] wire _out_T_272 = ~out_wimask_18; // @[RegisterRouter.scala:87:24] wire _out_T_273 = ~out_romask_18; // @[RegisterRouter.scala:87:24] wire _out_T_274 = ~out_womask_18; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_12 = {abstractDataMem_17, _out_prepend_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_275 = out_prepend_12; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_276 = _out_T_275; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_13 = _out_T_276; // @[RegisterRouter.scala:87:24] wire out_rimask_19 = |_out_rimask_T_19; // @[RegisterRouter.scala:87:24] wire out_wimask_19 = &_out_wimask_T_19; // @[RegisterRouter.scala:87:24] wire out_romask_19 = |_out_romask_T_19; // @[RegisterRouter.scala:87:24] wire out_womask_19 = &_out_womask_T_19; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_19 = out_rivalid_19 & out_rimask_19; // @[RegisterRouter.scala:87:24] wire _out_T_278 = out_f_rivalid_19; // @[RegisterRouter.scala:87:24] assign out_f_roready_19 = out_roready_19 & out_romask_19; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_18 = out_f_roready_19; // @[RegisterRouter.scala:87:24] wire _out_T_279 = out_f_roready_19; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_19 = out_wivalid_19 & out_wimask_19; // @[RegisterRouter.scala:87:24] wire _out_T_280 = out_f_wivalid_19; // @[RegisterRouter.scala:87:24] assign out_f_woready_19 = out_woready_19 & out_womask_19; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_18 = out_f_woready_19; // @[RegisterRouter.scala:87:24] wire _out_T_281 = out_f_woready_19; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_18 = out_f_woready_19 ? _out_T_277 : abstractDataMem_18; // @[RegisterRouter.scala:87:24] wire _out_T_282 = ~out_rimask_19; // @[RegisterRouter.scala:87:24] wire _out_T_283 = ~out_wimask_19; // @[RegisterRouter.scala:87:24] wire _out_T_284 = ~out_romask_19; // @[RegisterRouter.scala:87:24] wire _out_T_285 = ~out_womask_19; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_13 = {abstractDataMem_18, _out_prepend_T_13}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_286 = out_prepend_13; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_287 = _out_T_286; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_14 = _out_T_287; // @[RegisterRouter.scala:87:24] wire out_rimask_20 = |_out_rimask_T_20; // @[RegisterRouter.scala:87:24] wire out_wimask_20 = &_out_wimask_T_20; // @[RegisterRouter.scala:87:24] wire out_romask_20 = |_out_romask_T_20; // @[RegisterRouter.scala:87:24] wire out_womask_20 = &_out_womask_T_20; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_20 = out_rivalid_20 & out_rimask_20; // @[RegisterRouter.scala:87:24] wire _out_T_289 = out_f_rivalid_20; // @[RegisterRouter.scala:87:24] assign out_f_roready_20 = out_roready_20 & out_romask_20; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_19 = out_f_roready_20; // @[RegisterRouter.scala:87:24] wire _out_T_290 = out_f_roready_20; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_20 = out_wivalid_20 & out_wimask_20; // @[RegisterRouter.scala:87:24] wire _out_T_291 = out_f_wivalid_20; // @[RegisterRouter.scala:87:24] assign out_f_woready_20 = out_woready_20 & out_womask_20; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_19 = out_f_woready_20; // @[RegisterRouter.scala:87:24] wire _out_T_292 = out_f_woready_20; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_19 = out_f_woready_20 ? _out_T_288 : abstractDataMem_19; // @[RegisterRouter.scala:87:24] wire _out_T_293 = ~out_rimask_20; // @[RegisterRouter.scala:87:24] wire _out_T_294 = ~out_wimask_20; // @[RegisterRouter.scala:87:24] wire _out_T_295 = ~out_romask_20; // @[RegisterRouter.scala:87:24] wire _out_T_296 = ~out_womask_20; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_14 = {abstractDataMem_19, _out_prepend_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_297 = out_prepend_14; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_298 = _out_T_297; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_8 = _out_T_298; // @[MuxLiteral.scala:49:48] wire out_rimask_21 = |_out_rimask_T_21; // @[RegisterRouter.scala:87:24] wire out_wimask_21 = &_out_wimask_T_21; // @[RegisterRouter.scala:87:24] wire out_romask_21 = |_out_romask_T_21; // @[RegisterRouter.scala:87:24] wire out_womask_21 = &_out_womask_T_21; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_21 = out_rivalid_21 & out_rimask_21; // @[RegisterRouter.scala:87:24] wire _out_T_300 = out_f_rivalid_21; // @[RegisterRouter.scala:87:24] assign out_f_roready_21 = out_roready_21 & out_romask_21; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_0 = out_f_roready_21; // @[RegisterRouter.scala:87:24] wire _out_T_301 = out_f_roready_21; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_21 = out_wivalid_21 & out_wimask_21; // @[RegisterRouter.scala:87:24] wire _out_T_302 = out_f_wivalid_21; // @[RegisterRouter.scala:87:24] assign out_f_woready_21 = out_woready_21 & out_womask_21; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_0 = out_f_woready_21; // @[RegisterRouter.scala:87:24] wire _out_T_303 = out_f_woready_21; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_0 = out_f_woready_21 ? _out_T_299 : abstractDataMem_0; // @[RegisterRouter.scala:87:24] wire _out_T_304 = ~out_rimask_21; // @[RegisterRouter.scala:87:24] wire _out_T_305 = ~out_wimask_21; // @[RegisterRouter.scala:87:24] wire _out_T_306 = ~out_romask_21; // @[RegisterRouter.scala:87:24] wire _out_T_307 = ~out_womask_21; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_309 = _out_T_308; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_15 = _out_T_309; // @[RegisterRouter.scala:87:24] wire out_rimask_22 = |_out_rimask_T_22; // @[RegisterRouter.scala:87:24] wire out_wimask_22 = &_out_wimask_T_22; // @[RegisterRouter.scala:87:24] wire out_romask_22 = |_out_romask_T_22; // @[RegisterRouter.scala:87:24] wire out_womask_22 = &_out_womask_T_22; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_22 = out_rivalid_22 & out_rimask_22; // @[RegisterRouter.scala:87:24] wire _out_T_311 = out_f_rivalid_22; // @[RegisterRouter.scala:87:24] assign out_f_roready_22 = out_roready_22 & out_romask_22; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_1 = out_f_roready_22; // @[RegisterRouter.scala:87:24] wire _out_T_312 = out_f_roready_22; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_22 = out_wivalid_22 & out_wimask_22; // @[RegisterRouter.scala:87:24] wire _out_T_313 = out_f_wivalid_22; // @[RegisterRouter.scala:87:24] assign out_f_woready_22 = out_woready_22 & out_womask_22; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_1 = out_f_woready_22; // @[RegisterRouter.scala:87:24] wire _out_T_314 = out_f_woready_22; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_1 = out_f_woready_22 ? _out_T_310 : abstractDataMem_1; // @[RegisterRouter.scala:87:24] wire _out_T_315 = ~out_rimask_22; // @[RegisterRouter.scala:87:24] wire _out_T_316 = ~out_wimask_22; // @[RegisterRouter.scala:87:24] wire _out_T_317 = ~out_romask_22; // @[RegisterRouter.scala:87:24] wire _out_T_318 = ~out_womask_22; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_15 = {abstractDataMem_1, _out_prepend_T_15}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_319 = out_prepend_15; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_320 = _out_T_319; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_16 = _out_T_320; // @[RegisterRouter.scala:87:24] wire out_rimask_23 = |_out_rimask_T_23; // @[RegisterRouter.scala:87:24] wire out_wimask_23 = &_out_wimask_T_23; // @[RegisterRouter.scala:87:24] wire out_romask_23 = |_out_romask_T_23; // @[RegisterRouter.scala:87:24] wire out_womask_23 = &_out_womask_T_23; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_23 = out_rivalid_23 & out_rimask_23; // @[RegisterRouter.scala:87:24] wire _out_T_322 = out_f_rivalid_23; // @[RegisterRouter.scala:87:24] assign out_f_roready_23 = out_roready_23 & out_romask_23; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_2 = out_f_roready_23; // @[RegisterRouter.scala:87:24] wire _out_T_323 = out_f_roready_23; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_23 = out_wivalid_23 & out_wimask_23; // @[RegisterRouter.scala:87:24] wire _out_T_324 = out_f_wivalid_23; // @[RegisterRouter.scala:87:24] assign out_f_woready_23 = out_woready_23 & out_womask_23; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_2 = out_f_woready_23; // @[RegisterRouter.scala:87:24] wire _out_T_325 = out_f_woready_23; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_2 = out_f_woready_23 ? _out_T_321 : abstractDataMem_2; // @[RegisterRouter.scala:87:24] wire _out_T_326 = ~out_rimask_23; // @[RegisterRouter.scala:87:24] wire _out_T_327 = ~out_wimask_23; // @[RegisterRouter.scala:87:24] wire _out_T_328 = ~out_romask_23; // @[RegisterRouter.scala:87:24] wire _out_T_329 = ~out_womask_23; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_16 = {abstractDataMem_2, _out_prepend_T_16}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_330 = out_prepend_16; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_331 = _out_T_330; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_17 = _out_T_331; // @[RegisterRouter.scala:87:24] wire out_rimask_24 = |_out_rimask_T_24; // @[RegisterRouter.scala:87:24] wire out_wimask_24 = &_out_wimask_T_24; // @[RegisterRouter.scala:87:24] wire out_romask_24 = |_out_romask_T_24; // @[RegisterRouter.scala:87:24] wire out_womask_24 = &_out_womask_T_24; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_24 = out_rivalid_24 & out_rimask_24; // @[RegisterRouter.scala:87:24] wire _out_T_333 = out_f_rivalid_24; // @[RegisterRouter.scala:87:24] assign out_f_roready_24 = out_roready_24 & out_romask_24; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_3 = out_f_roready_24; // @[RegisterRouter.scala:87:24] wire _out_T_334 = out_f_roready_24; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_24 = out_wivalid_24 & out_wimask_24; // @[RegisterRouter.scala:87:24] wire _out_T_335 = out_f_wivalid_24; // @[RegisterRouter.scala:87:24] assign out_f_woready_24 = out_woready_24 & out_womask_24; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_3 = out_f_woready_24; // @[RegisterRouter.scala:87:24] wire _out_T_336 = out_f_woready_24; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_3 = out_f_woready_24 ? _out_T_332 : abstractDataMem_3; // @[RegisterRouter.scala:87:24] wire _out_T_337 = ~out_rimask_24; // @[RegisterRouter.scala:87:24] wire _out_T_338 = ~out_wimask_24; // @[RegisterRouter.scala:87:24] wire _out_T_339 = ~out_romask_24; // @[RegisterRouter.scala:87:24] wire _out_T_340 = ~out_womask_24; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_17 = {abstractDataMem_3, _out_prepend_T_17}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_341 = out_prepend_17; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_342 = _out_T_341; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_4 = _out_T_342; // @[MuxLiteral.scala:49:48] wire out_rimask_25 = |_out_rimask_T_25; // @[RegisterRouter.scala:87:24] wire out_wimask_25 = &_out_wimask_T_25; // @[RegisterRouter.scala:87:24] wire out_romask_25 = |_out_romask_T_25; // @[RegisterRouter.scala:87:24] wire out_womask_25 = &_out_womask_T_25; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_25 = out_rivalid_25 & out_rimask_25; // @[RegisterRouter.scala:87:24] wire _out_T_344 = out_f_rivalid_25; // @[RegisterRouter.scala:87:24] assign out_f_roready_25 = out_roready_25 & out_romask_25; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_60 = out_f_roready_25; // @[RegisterRouter.scala:87:24] wire _out_T_345 = out_f_roready_25; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_25 = out_wivalid_25 & out_wimask_25; // @[RegisterRouter.scala:87:24] wire _out_T_346 = out_f_wivalid_25; // @[RegisterRouter.scala:87:24] assign out_f_woready_25 = out_woready_25 & out_womask_25; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_60 = out_f_woready_25; // @[RegisterRouter.scala:87:24] wire _out_T_347 = out_f_woready_25; // @[RegisterRouter.scala:87:24] assign programBufferNxt_60 = out_f_woready_25 ? _out_T_343 : programBufferMem_60; // @[RegisterRouter.scala:87:24] wire _out_T_348 = ~out_rimask_25; // @[RegisterRouter.scala:87:24] wire _out_T_349 = ~out_wimask_25; // @[RegisterRouter.scala:87:24] wire _out_T_350 = ~out_romask_25; // @[RegisterRouter.scala:87:24] wire _out_T_351 = ~out_womask_25; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_353 = _out_T_352; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_18 = _out_T_353; // @[RegisterRouter.scala:87:24] wire out_rimask_26 = |_out_rimask_T_26; // @[RegisterRouter.scala:87:24] wire out_wimask_26 = &_out_wimask_T_26; // @[RegisterRouter.scala:87:24] wire out_romask_26 = |_out_romask_T_26; // @[RegisterRouter.scala:87:24] wire out_womask_26 = &_out_womask_T_26; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_26 = out_rivalid_26 & out_rimask_26; // @[RegisterRouter.scala:87:24] wire _out_T_355 = out_f_rivalid_26; // @[RegisterRouter.scala:87:24] assign out_f_roready_26 = out_roready_26 & out_romask_26; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_61 = out_f_roready_26; // @[RegisterRouter.scala:87:24] wire _out_T_356 = out_f_roready_26; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_26 = out_wivalid_26 & out_wimask_26; // @[RegisterRouter.scala:87:24] wire _out_T_357 = out_f_wivalid_26; // @[RegisterRouter.scala:87:24] assign out_f_woready_26 = out_woready_26 & out_womask_26; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_61 = out_f_woready_26; // @[RegisterRouter.scala:87:24] wire _out_T_358 = out_f_woready_26; // @[RegisterRouter.scala:87:24] assign programBufferNxt_61 = out_f_woready_26 ? _out_T_354 : programBufferMem_61; // @[RegisterRouter.scala:87:24] wire _out_T_359 = ~out_rimask_26; // @[RegisterRouter.scala:87:24] wire _out_T_360 = ~out_wimask_26; // @[RegisterRouter.scala:87:24] wire _out_T_361 = ~out_romask_26; // @[RegisterRouter.scala:87:24] wire _out_T_362 = ~out_womask_26; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_18 = {programBufferMem_61, _out_prepend_T_18}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_363 = out_prepend_18; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_364 = _out_T_363; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_19 = _out_T_364; // @[RegisterRouter.scala:87:24] wire out_rimask_27 = |_out_rimask_T_27; // @[RegisterRouter.scala:87:24] wire out_wimask_27 = &_out_wimask_T_27; // @[RegisterRouter.scala:87:24] wire out_romask_27 = |_out_romask_T_27; // @[RegisterRouter.scala:87:24] wire out_womask_27 = &_out_womask_T_27; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_27 = out_rivalid_27 & out_rimask_27; // @[RegisterRouter.scala:87:24] wire _out_T_366 = out_f_rivalid_27; // @[RegisterRouter.scala:87:24] assign out_f_roready_27 = out_roready_27 & out_romask_27; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_62 = out_f_roready_27; // @[RegisterRouter.scala:87:24] wire _out_T_367 = out_f_roready_27; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_27 = out_wivalid_27 & out_wimask_27; // @[RegisterRouter.scala:87:24] wire _out_T_368 = out_f_wivalid_27; // @[RegisterRouter.scala:87:24] assign out_f_woready_27 = out_woready_27 & out_womask_27; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_62 = out_f_woready_27; // @[RegisterRouter.scala:87:24] wire _out_T_369 = out_f_woready_27; // @[RegisterRouter.scala:87:24] assign programBufferNxt_62 = out_f_woready_27 ? _out_T_365 : programBufferMem_62; // @[RegisterRouter.scala:87:24] wire _out_T_370 = ~out_rimask_27; // @[RegisterRouter.scala:87:24] wire _out_T_371 = ~out_wimask_27; // @[RegisterRouter.scala:87:24] wire _out_T_372 = ~out_romask_27; // @[RegisterRouter.scala:87:24] wire _out_T_373 = ~out_womask_27; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_19 = {programBufferMem_62, _out_prepend_T_19}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_374 = out_prepend_19; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_375 = _out_T_374; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_20 = _out_T_375; // @[RegisterRouter.scala:87:24] wire out_rimask_28 = |_out_rimask_T_28; // @[RegisterRouter.scala:87:24] wire out_wimask_28 = &_out_wimask_T_28; // @[RegisterRouter.scala:87:24] wire out_romask_28 = |_out_romask_T_28; // @[RegisterRouter.scala:87:24] wire out_womask_28 = &_out_womask_T_28; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_28 = out_rivalid_28 & out_rimask_28; // @[RegisterRouter.scala:87:24] wire _out_T_377 = out_f_rivalid_28; // @[RegisterRouter.scala:87:24] assign out_f_roready_28 = out_roready_28 & out_romask_28; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_63 = out_f_roready_28; // @[RegisterRouter.scala:87:24] wire _out_T_378 = out_f_roready_28; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_28 = out_wivalid_28 & out_wimask_28; // @[RegisterRouter.scala:87:24] wire _out_T_379 = out_f_wivalid_28; // @[RegisterRouter.scala:87:24] assign out_f_woready_28 = out_woready_28 & out_womask_28; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_63 = out_f_woready_28; // @[RegisterRouter.scala:87:24] wire _out_T_380 = out_f_woready_28; // @[RegisterRouter.scala:87:24] assign programBufferNxt_63 = out_f_woready_28 ? _out_T_376 : programBufferMem_63; // @[RegisterRouter.scala:87:24] wire _out_T_381 = ~out_rimask_28; // @[RegisterRouter.scala:87:24] wire _out_T_382 = ~out_wimask_28; // @[RegisterRouter.scala:87:24] wire _out_T_383 = ~out_romask_28; // @[RegisterRouter.scala:87:24] wire _out_T_384 = ~out_womask_28; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_20 = {programBufferMem_63, _out_prepend_T_20}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_385 = out_prepend_20; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_386 = _out_T_385; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_47 = _out_T_386; // @[MuxLiteral.scala:49:48] wire out_rimask_29 = |_out_rimask_T_29; // @[RegisterRouter.scala:87:24] wire out_wimask_29 = &_out_wimask_T_29; // @[RegisterRouter.scala:87:24] wire out_romask_29 = |_out_romask_T_29; // @[RegisterRouter.scala:87:24] wire out_womask_29 = &_out_womask_T_29; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_29 = out_rivalid_29 & out_rimask_29; // @[RegisterRouter.scala:87:24] wire _out_T_388 = out_f_rivalid_29; // @[RegisterRouter.scala:87:24] assign out_f_roready_29 = out_roready_29 & out_romask_29; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_24 = out_f_roready_29; // @[RegisterRouter.scala:87:24] wire _out_T_389 = out_f_roready_29; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_29 = out_wivalid_29 & out_wimask_29; // @[RegisterRouter.scala:87:24] wire _out_T_390 = out_f_wivalid_29; // @[RegisterRouter.scala:87:24] assign out_f_woready_29 = out_woready_29 & out_womask_29; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_24 = out_f_woready_29; // @[RegisterRouter.scala:87:24] wire _out_T_391 = out_f_woready_29; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_24 = out_f_woready_29 ? _out_T_387 : abstractDataMem_24; // @[RegisterRouter.scala:87:24] wire _out_T_392 = ~out_rimask_29; // @[RegisterRouter.scala:87:24] wire _out_T_393 = ~out_wimask_29; // @[RegisterRouter.scala:87:24] wire _out_T_394 = ~out_romask_29; // @[RegisterRouter.scala:87:24] wire _out_T_395 = ~out_womask_29; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_397 = _out_T_396; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_21 = _out_T_397; // @[RegisterRouter.scala:87:24] wire out_rimask_30 = |_out_rimask_T_30; // @[RegisterRouter.scala:87:24] wire out_wimask_30 = &_out_wimask_T_30; // @[RegisterRouter.scala:87:24] wire out_romask_30 = |_out_romask_T_30; // @[RegisterRouter.scala:87:24] wire out_womask_30 = &_out_womask_T_30; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_30 = out_rivalid_30 & out_rimask_30; // @[RegisterRouter.scala:87:24] wire _out_T_399 = out_f_rivalid_30; // @[RegisterRouter.scala:87:24] assign out_f_roready_30 = out_roready_30 & out_romask_30; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_25 = out_f_roready_30; // @[RegisterRouter.scala:87:24] wire _out_T_400 = out_f_roready_30; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_30 = out_wivalid_30 & out_wimask_30; // @[RegisterRouter.scala:87:24] wire _out_T_401 = out_f_wivalid_30; // @[RegisterRouter.scala:87:24] assign out_f_woready_30 = out_woready_30 & out_womask_30; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_25 = out_f_woready_30; // @[RegisterRouter.scala:87:24] wire _out_T_402 = out_f_woready_30; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_25 = out_f_woready_30 ? _out_T_398 : abstractDataMem_25; // @[RegisterRouter.scala:87:24] wire _out_T_403 = ~out_rimask_30; // @[RegisterRouter.scala:87:24] wire _out_T_404 = ~out_wimask_30; // @[RegisterRouter.scala:87:24] wire _out_T_405 = ~out_romask_30; // @[RegisterRouter.scala:87:24] wire _out_T_406 = ~out_womask_30; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_21 = {abstractDataMem_25, _out_prepend_T_21}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_407 = out_prepend_21; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_408 = _out_T_407; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_22 = _out_T_408; // @[RegisterRouter.scala:87:24] wire out_rimask_31 = |_out_rimask_T_31; // @[RegisterRouter.scala:87:24] wire out_wimask_31 = &_out_wimask_T_31; // @[RegisterRouter.scala:87:24] wire out_romask_31 = |_out_romask_T_31; // @[RegisterRouter.scala:87:24] wire out_womask_31 = &_out_womask_T_31; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_31 = out_rivalid_31 & out_rimask_31; // @[RegisterRouter.scala:87:24] wire _out_T_410 = out_f_rivalid_31; // @[RegisterRouter.scala:87:24] assign out_f_roready_31 = out_roready_31 & out_romask_31; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_26 = out_f_roready_31; // @[RegisterRouter.scala:87:24] wire _out_T_411 = out_f_roready_31; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_31 = out_wivalid_31 & out_wimask_31; // @[RegisterRouter.scala:87:24] wire _out_T_412 = out_f_wivalid_31; // @[RegisterRouter.scala:87:24] assign out_f_woready_31 = out_woready_31 & out_womask_31; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_26 = out_f_woready_31; // @[RegisterRouter.scala:87:24] wire _out_T_413 = out_f_woready_31; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_26 = out_f_woready_31 ? _out_T_409 : abstractDataMem_26; // @[RegisterRouter.scala:87:24] wire _out_T_414 = ~out_rimask_31; // @[RegisterRouter.scala:87:24] wire _out_T_415 = ~out_wimask_31; // @[RegisterRouter.scala:87:24] wire _out_T_416 = ~out_romask_31; // @[RegisterRouter.scala:87:24] wire _out_T_417 = ~out_womask_31; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_22 = {abstractDataMem_26, _out_prepend_T_22}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_418 = out_prepend_22; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_419 = _out_T_418; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_23 = _out_T_419; // @[RegisterRouter.scala:87:24] wire out_rimask_32 = |_out_rimask_T_32; // @[RegisterRouter.scala:87:24] wire out_wimask_32 = &_out_wimask_T_32; // @[RegisterRouter.scala:87:24] wire out_romask_32 = |_out_romask_T_32; // @[RegisterRouter.scala:87:24] wire out_womask_32 = &_out_womask_T_32; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_32 = out_rivalid_32 & out_rimask_32; // @[RegisterRouter.scala:87:24] wire _out_T_421 = out_f_rivalid_32; // @[RegisterRouter.scala:87:24] assign out_f_roready_32 = out_roready_32 & out_romask_32; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_27 = out_f_roready_32; // @[RegisterRouter.scala:87:24] wire _out_T_422 = out_f_roready_32; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_32 = out_wivalid_32 & out_wimask_32; // @[RegisterRouter.scala:87:24] wire _out_T_423 = out_f_wivalid_32; // @[RegisterRouter.scala:87:24] assign out_f_woready_32 = out_woready_32 & out_womask_32; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_27 = out_f_woready_32; // @[RegisterRouter.scala:87:24] wire _out_T_424 = out_f_woready_32; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_27 = out_f_woready_32 ? _out_T_420 : abstractDataMem_27; // @[RegisterRouter.scala:87:24] wire _out_T_425 = ~out_rimask_32; // @[RegisterRouter.scala:87:24] wire _out_T_426 = ~out_wimask_32; // @[RegisterRouter.scala:87:24] wire _out_T_427 = ~out_romask_32; // @[RegisterRouter.scala:87:24] wire _out_T_428 = ~out_womask_32; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_23 = {abstractDataMem_27, _out_prepend_T_23}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_429 = out_prepend_23; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_430 = _out_T_429; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_10 = _out_T_430; // @[MuxLiteral.scala:49:48] wire _out_rimask_T_33 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_33 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire out_rimask_33 = _out_rimask_T_33; // @[RegisterRouter.scala:87:24] wire out_wimask_33 = _out_wimask_T_33; // @[RegisterRouter.scala:87:24] wire _out_romask_T_33 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_33 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire out_romask_33 = _out_romask_T_33; // @[RegisterRouter.scala:87:24] wire out_womask_33 = _out_womask_T_33; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_33 = out_rivalid_33 & out_rimask_33; // @[RegisterRouter.scala:87:24] wire _out_T_432 = out_f_rivalid_33; // @[RegisterRouter.scala:87:24] wire out_f_roready_33 = out_roready_33 & out_romask_33; // @[RegisterRouter.scala:87:24] wire _out_T_433 = out_f_roready_33; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_33 = out_wivalid_33 & out_wimask_33; // @[RegisterRouter.scala:87:24] wire out_f_woready_33 = out_woready_33 & out_womask_33; // @[RegisterRouter.scala:87:24] wire _out_T_431 = out_front_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_434 = ~out_rimask_33; // @[RegisterRouter.scala:87:24] wire _out_T_435 = ~out_wimask_33; // @[RegisterRouter.scala:87:24] wire _out_T_436 = ~out_romask_33; // @[RegisterRouter.scala:87:24] wire _out_T_437 = ~out_womask_33; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_34 = out_frontMask[1]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_34 = out_frontMask[1]; // @[RegisterRouter.scala:87:24] wire out_rimask_34 = _out_rimask_T_34; // @[RegisterRouter.scala:87:24] wire out_wimask_34 = _out_wimask_T_34; // @[RegisterRouter.scala:87:24] wire _out_romask_T_34 = out_backMask[1]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_34 = out_backMask[1]; // @[RegisterRouter.scala:87:24] wire out_romask_34 = _out_romask_T_34; // @[RegisterRouter.scala:87:24] wire out_womask_34 = _out_womask_T_34; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_34 = out_rivalid_34 & out_rimask_34; // @[RegisterRouter.scala:87:24] wire _out_T_441 = out_f_rivalid_34; // @[RegisterRouter.scala:87:24] wire out_f_roready_34 = out_roready_34 & out_romask_34; // @[RegisterRouter.scala:87:24] wire _out_T_442 = out_f_roready_34; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_34 = out_wivalid_34 & out_wimask_34; // @[RegisterRouter.scala:87:24] wire out_f_woready_34 = out_woready_34 & out_womask_34; // @[RegisterRouter.scala:87:24] wire _out_T_440 = out_front_bits_data[1]; // @[RegisterRouter.scala:87:24] wire _out_T_443 = ~out_rimask_34; // @[RegisterRouter.scala:87:24] wire _out_T_444 = ~out_wimask_34; // @[RegisterRouter.scala:87:24] wire _out_T_445 = ~out_romask_34; // @[RegisterRouter.scala:87:24] wire _out_T_446 = ~out_womask_34; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_35 = out_frontMask[2]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_35 = out_frontMask[2]; // @[RegisterRouter.scala:87:24] wire out_rimask_35 = _out_rimask_T_35; // @[RegisterRouter.scala:87:24] wire out_wimask_35 = _out_wimask_T_35; // @[RegisterRouter.scala:87:24] wire _out_romask_T_35 = out_backMask[2]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_35 = out_backMask[2]; // @[RegisterRouter.scala:87:24] wire out_romask_35 = _out_romask_T_35; // @[RegisterRouter.scala:87:24] wire out_womask_35 = _out_womask_T_35; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_35 = out_rivalid_35 & out_rimask_35; // @[RegisterRouter.scala:87:24] wire _out_T_450 = out_f_rivalid_35; // @[RegisterRouter.scala:87:24] wire out_f_roready_35 = out_roready_35 & out_romask_35; // @[RegisterRouter.scala:87:24] wire _out_T_451 = out_f_roready_35; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_35 = out_wivalid_35 & out_wimask_35; // @[RegisterRouter.scala:87:24] wire out_f_woready_35 = out_woready_35 & out_womask_35; // @[RegisterRouter.scala:87:24] wire _out_T_449 = out_front_bits_data[2]; // @[RegisterRouter.scala:87:24] wire _out_T_452 = ~out_rimask_35; // @[RegisterRouter.scala:87:24] wire _out_T_453 = ~out_wimask_35; // @[RegisterRouter.scala:87:24] wire _out_T_454 = ~out_romask_35; // @[RegisterRouter.scala:87:24] wire _out_T_455 = ~out_womask_35; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_36 = out_frontMask[3]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_36 = out_frontMask[3]; // @[RegisterRouter.scala:87:24] wire out_rimask_36 = _out_rimask_T_36; // @[RegisterRouter.scala:87:24] wire out_wimask_36 = _out_wimask_T_36; // @[RegisterRouter.scala:87:24] wire _out_romask_T_36 = out_backMask[3]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_36 = out_backMask[3]; // @[RegisterRouter.scala:87:24] wire out_romask_36 = _out_romask_T_36; // @[RegisterRouter.scala:87:24] wire out_womask_36 = _out_womask_T_36; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_36 = out_rivalid_36 & out_rimask_36; // @[RegisterRouter.scala:87:24] wire _out_T_459 = out_f_rivalid_36; // @[RegisterRouter.scala:87:24] wire out_f_roready_36 = out_roready_36 & out_romask_36; // @[RegisterRouter.scala:87:24] wire _out_T_460 = out_f_roready_36; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_36 = out_wivalid_36 & out_wimask_36; // @[RegisterRouter.scala:87:24] wire out_f_woready_36 = out_woready_36 & out_womask_36; // @[RegisterRouter.scala:87:24] wire _out_T_458 = out_front_bits_data[3]; // @[RegisterRouter.scala:87:24] wire _out_T_461 = ~out_rimask_36; // @[RegisterRouter.scala:87:24] wire _out_T_462 = ~out_wimask_36; // @[RegisterRouter.scala:87:24] wire _out_T_463 = ~out_romask_36; // @[RegisterRouter.scala:87:24] wire _out_T_464 = ~out_womask_36; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_37 = out_frontMask[4]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_37 = out_frontMask[4]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_83 = out_frontMask[4]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_83 = out_frontMask[4]; // @[RegisterRouter.scala:87:24] wire out_rimask_37 = _out_rimask_T_37; // @[RegisterRouter.scala:87:24] wire out_wimask_37 = _out_wimask_T_37; // @[RegisterRouter.scala:87:24] wire _out_romask_T_37 = out_backMask[4]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_37 = out_backMask[4]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_83 = out_backMask[4]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_83 = out_backMask[4]; // @[RegisterRouter.scala:87:24] wire out_romask_37 = _out_romask_T_37; // @[RegisterRouter.scala:87:24] wire out_womask_37 = _out_womask_T_37; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_37 = out_rivalid_37 & out_rimask_37; // @[RegisterRouter.scala:87:24] wire _out_T_468 = out_f_rivalid_37; // @[RegisterRouter.scala:87:24] wire out_f_roready_37 = out_roready_37 & out_romask_37; // @[RegisterRouter.scala:87:24] wire _out_T_469 = out_f_roready_37; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_37 = out_wivalid_37 & out_wimask_37; // @[RegisterRouter.scala:87:24] wire out_f_woready_37 = out_woready_37 & out_womask_37; // @[RegisterRouter.scala:87:24] wire _out_T_467 = out_front_bits_data[4]; // @[RegisterRouter.scala:87:24] wire _out_T_957 = out_front_bits_data[4]; // @[RegisterRouter.scala:87:24] wire _out_T_470 = ~out_rimask_37; // @[RegisterRouter.scala:87:24] wire _out_T_471 = ~out_wimask_37; // @[RegisterRouter.scala:87:24] wire _out_T_472 = ~out_romask_37; // @[RegisterRouter.scala:87:24] wire _out_T_473 = ~out_womask_37; // @[RegisterRouter.scala:87:24] wire [6:0] _out_rimask_T_38 = out_frontMask[11:5]; // @[RegisterRouter.scala:87:24] wire [6:0] _out_wimask_T_38 = out_frontMask[11:5]; // @[RegisterRouter.scala:87:24] wire out_rimask_38 = |_out_rimask_T_38; // @[RegisterRouter.scala:87:24] wire out_wimask_38 = &_out_wimask_T_38; // @[RegisterRouter.scala:87:24] wire [6:0] _out_romask_T_38 = out_backMask[11:5]; // @[RegisterRouter.scala:87:24] wire [6:0] _out_womask_T_38 = out_backMask[11:5]; // @[RegisterRouter.scala:87:24] wire out_romask_38 = |_out_romask_T_38; // @[RegisterRouter.scala:87:24] wire out_womask_38 = &_out_womask_T_38; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_38 = out_rivalid_38 & out_rimask_38; // @[RegisterRouter.scala:87:24] wire _out_T_477 = out_f_rivalid_38; // @[RegisterRouter.scala:87:24] wire out_f_roready_38 = out_roready_38 & out_romask_38; // @[RegisterRouter.scala:87:24] wire _out_T_478 = out_f_roready_38; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_38 = out_wivalid_38 & out_wimask_38; // @[RegisterRouter.scala:87:24] wire out_f_woready_38 = out_woready_38 & out_womask_38; // @[RegisterRouter.scala:87:24] wire [6:0] _out_T_476 = out_front_bits_data[11:5]; // @[RegisterRouter.scala:87:24] wire _out_T_479 = ~out_rimask_38; // @[RegisterRouter.scala:87:24] wire _out_T_480 = ~out_wimask_38; // @[RegisterRouter.scala:87:24] wire _out_T_481 = ~out_romask_38; // @[RegisterRouter.scala:87:24] wire _out_T_482 = ~out_womask_38; // @[RegisterRouter.scala:87:24] wire [2:0] _out_rimask_T_39 = out_frontMask[14:12]; // @[RegisterRouter.scala:87:24] wire [2:0] _out_wimask_T_39 = out_frontMask[14:12]; // @[RegisterRouter.scala:87:24] wire out_rimask_39 = |_out_rimask_T_39; // @[RegisterRouter.scala:87:24] wire out_wimask_39 = &_out_wimask_T_39; // @[RegisterRouter.scala:87:24] wire [2:0] _out_romask_T_39 = out_backMask[14:12]; // @[RegisterRouter.scala:87:24] wire [2:0] _out_womask_T_39 = out_backMask[14:12]; // @[RegisterRouter.scala:87:24] wire out_romask_39 = |_out_romask_T_39; // @[RegisterRouter.scala:87:24] wire out_womask_39 = &_out_womask_T_39; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_39 = out_rivalid_39 & out_rimask_39; // @[RegisterRouter.scala:87:24] wire _out_T_486 = out_f_rivalid_39; // @[RegisterRouter.scala:87:24] wire out_f_roready_39 = out_roready_39 & out_romask_39; // @[RegisterRouter.scala:87:24] wire _out_T_487 = out_f_roready_39; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_39 = out_wivalid_39 & out_wimask_39; // @[RegisterRouter.scala:87:24] wire _out_T_488 = out_f_wivalid_39; // @[RegisterRouter.scala:87:24] assign out_f_woready_39 = out_woready_39 & out_womask_39; // @[RegisterRouter.scala:87:24] assign sberrorWrEn = out_f_woready_39; // @[RegisterRouter.scala:87:24] wire _out_T_489 = out_f_woready_39; // @[RegisterRouter.scala:87:24] assign _out_T_485 = out_front_bits_data[14:12]; // @[RegisterRouter.scala:87:24] assign SBCSWrData_sberror = _out_T_485; // @[RegisterRouter.scala:87:24] wire _out_T_490 = ~out_rimask_39; // @[RegisterRouter.scala:87:24] wire _out_T_491 = ~out_wimask_39; // @[RegisterRouter.scala:87:24] wire _out_T_492 = ~out_romask_39; // @[RegisterRouter.scala:87:24] wire _out_T_493 = ~out_womask_39; // @[RegisterRouter.scala:87:24] wire [14:0] out_prepend_29 = {SBCSRdData_sberror, 12'h40F}; // @[RegisterRouter.scala:87:24] wire [14:0] _out_T_494 = out_prepend_29; // @[RegisterRouter.scala:87:24] wire [14:0] _out_T_495 = _out_T_494; // @[RegisterRouter.scala:87:24] wire [14:0] _out_prepend_T_30 = _out_T_495; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_40 = out_frontMask[15]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_40 = out_frontMask[15]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_94 = out_frontMask[15]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_94 = out_frontMask[15]; // @[RegisterRouter.scala:87:24] wire out_rimask_40 = _out_rimask_T_40; // @[RegisterRouter.scala:87:24] wire out_wimask_40 = _out_wimask_T_40; // @[RegisterRouter.scala:87:24] wire _out_romask_T_40 = out_backMask[15]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_40 = out_backMask[15]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_94 = out_backMask[15]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_94 = out_backMask[15]; // @[RegisterRouter.scala:87:24] wire out_romask_40 = _out_romask_T_40; // @[RegisterRouter.scala:87:24] wire out_womask_40 = _out_womask_T_40; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_40 = out_rivalid_40 & out_rimask_40; // @[RegisterRouter.scala:87:24] wire _out_T_497 = out_f_rivalid_40; // @[RegisterRouter.scala:87:24] wire out_f_roready_40 = out_roready_40 & out_romask_40; // @[RegisterRouter.scala:87:24] wire _out_T_498 = out_f_roready_40; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_40 = out_wivalid_40 & out_wimask_40; // @[RegisterRouter.scala:87:24] wire _out_T_499 = out_f_wivalid_40; // @[RegisterRouter.scala:87:24] assign out_f_woready_40 = out_woready_40 & out_womask_40; // @[RegisterRouter.scala:87:24] assign sbreadondataWrEn = out_f_woready_40; // @[RegisterRouter.scala:87:24] wire _out_T_500 = out_f_woready_40; // @[RegisterRouter.scala:87:24] assign _out_T_496 = out_front_bits_data[15]; // @[RegisterRouter.scala:87:24] wire _out_T_1056 = out_front_bits_data[15]; // @[RegisterRouter.scala:87:24] assign SBCSWrData_sbreadondata = _out_T_496; // @[RegisterRouter.scala:87:24] wire _out_T_501 = ~out_rimask_40; // @[RegisterRouter.scala:87:24] wire _out_T_502 = ~out_wimask_40; // @[RegisterRouter.scala:87:24] wire _out_T_503 = ~out_romask_40; // @[RegisterRouter.scala:87:24] wire _out_T_504 = ~out_womask_40; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_30 = {SBCSRdData_sbreadondata, _out_prepend_T_30}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_505 = out_prepend_30; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_506 = _out_T_505; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_31 = _out_T_506; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_41 = out_frontMask[16]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_41 = out_frontMask[16]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_95 = out_frontMask[16]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_95 = out_frontMask[16]; // @[RegisterRouter.scala:87:24] wire out_rimask_41 = _out_rimask_T_41; // @[RegisterRouter.scala:87:24] wire out_wimask_41 = _out_wimask_T_41; // @[RegisterRouter.scala:87:24] wire _out_romask_T_41 = out_backMask[16]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_41 = out_backMask[16]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_95 = out_backMask[16]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_95 = out_backMask[16]; // @[RegisterRouter.scala:87:24] wire out_romask_41 = _out_romask_T_41; // @[RegisterRouter.scala:87:24] wire out_womask_41 = _out_womask_T_41; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_41 = out_rivalid_41 & out_rimask_41; // @[RegisterRouter.scala:87:24] wire _out_T_508 = out_f_rivalid_41; // @[RegisterRouter.scala:87:24] wire out_f_roready_41 = out_roready_41 & out_romask_41; // @[RegisterRouter.scala:87:24] wire _out_T_509 = out_f_roready_41; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_41 = out_wivalid_41 & out_wimask_41; // @[RegisterRouter.scala:87:24] wire _out_T_510 = out_f_wivalid_41; // @[RegisterRouter.scala:87:24] assign out_f_woready_41 = out_woready_41 & out_womask_41; // @[RegisterRouter.scala:87:24] assign sbautoincrementWrEn = out_f_woready_41; // @[RegisterRouter.scala:87:24] wire _out_T_511 = out_f_woready_41; // @[RegisterRouter.scala:87:24] assign _out_T_507 = out_front_bits_data[16]; // @[RegisterRouter.scala:87:24] wire _out_T_1065 = out_front_bits_data[16]; // @[RegisterRouter.scala:87:24] assign SBCSWrData_sbautoincrement = _out_T_507; // @[RegisterRouter.scala:87:24] wire _out_T_512 = ~out_rimask_41; // @[RegisterRouter.scala:87:24] wire _out_T_513 = ~out_wimask_41; // @[RegisterRouter.scala:87:24] wire _out_T_514 = ~out_romask_41; // @[RegisterRouter.scala:87:24] wire _out_T_515 = ~out_womask_41; // @[RegisterRouter.scala:87:24] wire [16:0] out_prepend_31 = {SBCSRdData_sbautoincrement, _out_prepend_T_31}; // @[RegisterRouter.scala:87:24] wire [16:0] _out_T_516 = out_prepend_31; // @[RegisterRouter.scala:87:24] wire [16:0] _out_T_517 = _out_T_516; // @[RegisterRouter.scala:87:24] wire [16:0] _out_prepend_T_32 = _out_T_517; // @[RegisterRouter.scala:87:24] wire [2:0] _out_rimask_T_42 = out_frontMask[19:17]; // @[RegisterRouter.scala:87:24] wire [2:0] _out_wimask_T_42 = out_frontMask[19:17]; // @[RegisterRouter.scala:87:24] wire out_rimask_42 = |_out_rimask_T_42; // @[RegisterRouter.scala:87:24] wire out_wimask_42 = &_out_wimask_T_42; // @[RegisterRouter.scala:87:24] wire [2:0] _out_romask_T_42 = out_backMask[19:17]; // @[RegisterRouter.scala:87:24] wire [2:0] _out_womask_T_42 = out_backMask[19:17]; // @[RegisterRouter.scala:87:24] wire out_romask_42 = |_out_romask_T_42; // @[RegisterRouter.scala:87:24] wire out_womask_42 = &_out_womask_T_42; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_42 = out_rivalid_42 & out_rimask_42; // @[RegisterRouter.scala:87:24] wire _out_T_519 = out_f_rivalid_42; // @[RegisterRouter.scala:87:24] wire out_f_roready_42 = out_roready_42 & out_romask_42; // @[RegisterRouter.scala:87:24] wire _out_T_520 = out_f_roready_42; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_42 = out_wivalid_42 & out_wimask_42; // @[RegisterRouter.scala:87:24] wire _out_T_521 = out_f_wivalid_42; // @[RegisterRouter.scala:87:24] assign out_f_woready_42 = out_woready_42 & out_womask_42; // @[RegisterRouter.scala:87:24] assign sbaccessWrEn = out_f_woready_42; // @[RegisterRouter.scala:87:24] wire _out_T_522 = out_f_woready_42; // @[RegisterRouter.scala:87:24] assign _out_T_518 = out_front_bits_data[19:17]; // @[RegisterRouter.scala:87:24] assign SBCSWrData_sbaccess = _out_T_518; // @[RegisterRouter.scala:87:24] wire _out_T_523 = ~out_rimask_42; // @[RegisterRouter.scala:87:24] wire _out_T_524 = ~out_wimask_42; // @[RegisterRouter.scala:87:24] wire _out_T_525 = ~out_romask_42; // @[RegisterRouter.scala:87:24] wire _out_T_526 = ~out_womask_42; // @[RegisterRouter.scala:87:24] wire [19:0] out_prepend_32 = {SBCSRdData_sbaccess, _out_prepend_T_32}; // @[RegisterRouter.scala:87:24] wire [19:0] _out_T_527 = out_prepend_32; // @[RegisterRouter.scala:87:24] wire [19:0] _out_T_528 = _out_T_527; // @[RegisterRouter.scala:87:24] wire [19:0] _out_prepend_T_33 = _out_T_528; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_43 = out_frontMask[20]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_43 = out_frontMask[20]; // @[RegisterRouter.scala:87:24] wire out_rimask_43 = _out_rimask_T_43; // @[RegisterRouter.scala:87:24] wire out_wimask_43 = _out_wimask_T_43; // @[RegisterRouter.scala:87:24] wire _out_romask_T_43 = out_backMask[20]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_43 = out_backMask[20]; // @[RegisterRouter.scala:87:24] wire out_romask_43 = _out_romask_T_43; // @[RegisterRouter.scala:87:24] wire out_womask_43 = _out_womask_T_43; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_43 = out_rivalid_43 & out_rimask_43; // @[RegisterRouter.scala:87:24] wire _out_T_530 = out_f_rivalid_43; // @[RegisterRouter.scala:87:24] wire out_f_roready_43 = out_roready_43 & out_romask_43; // @[RegisterRouter.scala:87:24] wire _out_T_531 = out_f_roready_43; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_43 = out_wivalid_43 & out_wimask_43; // @[RegisterRouter.scala:87:24] wire _out_T_532 = out_f_wivalid_43; // @[RegisterRouter.scala:87:24] assign out_f_woready_43 = out_woready_43 & out_womask_43; // @[RegisterRouter.scala:87:24] assign sbreadonaddrWrEn = out_f_woready_43; // @[RegisterRouter.scala:87:24] wire _out_T_533 = out_f_woready_43; // @[RegisterRouter.scala:87:24] assign _out_T_529 = out_front_bits_data[20]; // @[RegisterRouter.scala:87:24] assign SBCSWrData_sbreadonaddr = _out_T_529; // @[RegisterRouter.scala:87:24] wire _out_T_534 = ~out_rimask_43; // @[RegisterRouter.scala:87:24] wire _out_T_535 = ~out_wimask_43; // @[RegisterRouter.scala:87:24] wire _out_T_536 = ~out_romask_43; // @[RegisterRouter.scala:87:24] wire _out_T_537 = ~out_womask_43; // @[RegisterRouter.scala:87:24] wire [20:0] out_prepend_33 = {SBCSRdData_sbreadonaddr, _out_prepend_T_33}; // @[RegisterRouter.scala:87:24] wire [20:0] _out_T_538 = out_prepend_33; // @[RegisterRouter.scala:87:24] wire [20:0] _out_T_539 = _out_T_538; // @[RegisterRouter.scala:87:24] wire [20:0] _out_prepend_T_34 = _out_T_539; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_44 = out_frontMask[21]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_44 = out_frontMask[21]; // @[RegisterRouter.scala:87:24] wire out_rimask_44 = _out_rimask_T_44; // @[RegisterRouter.scala:87:24] wire out_wimask_44 = _out_wimask_T_44; // @[RegisterRouter.scala:87:24] wire _out_romask_T_44 = out_backMask[21]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_44 = out_backMask[21]; // @[RegisterRouter.scala:87:24] wire out_romask_44 = _out_romask_T_44; // @[RegisterRouter.scala:87:24] wire out_womask_44 = _out_womask_T_44; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_44 = out_rivalid_44 & out_rimask_44; // @[RegisterRouter.scala:87:24] wire _out_T_541 = out_f_rivalid_44; // @[RegisterRouter.scala:87:24] wire out_f_roready_44 = out_roready_44 & out_romask_44; // @[RegisterRouter.scala:87:24] wire _out_T_542 = out_f_roready_44; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_44 = out_wivalid_44 & out_wimask_44; // @[RegisterRouter.scala:87:24] wire out_f_woready_44 = out_woready_44 & out_womask_44; // @[RegisterRouter.scala:87:24] wire _out_T_540 = out_front_bits_data[21]; // @[RegisterRouter.scala:87:24] wire _out_T_543 = ~out_rimask_44; // @[RegisterRouter.scala:87:24] wire _out_T_544 = ~out_wimask_44; // @[RegisterRouter.scala:87:24] wire _out_T_545 = ~out_romask_44; // @[RegisterRouter.scala:87:24] wire _out_T_546 = ~out_womask_44; // @[RegisterRouter.scala:87:24] wire [21:0] out_prepend_34 = {SBCSRdData_sbbusy, _out_prepend_T_34}; // @[RegisterRouter.scala:87:24] wire [21:0] _out_T_547 = out_prepend_34; // @[RegisterRouter.scala:87:24] wire [21:0] _out_T_548 = _out_T_547; // @[RegisterRouter.scala:87:24] wire [21:0] _out_prepend_T_35 = _out_T_548; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_45 = out_frontMask[22]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_45 = out_frontMask[22]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_100 = out_frontMask[22]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_100 = out_frontMask[22]; // @[RegisterRouter.scala:87:24] wire out_rimask_45 = _out_rimask_T_45; // @[RegisterRouter.scala:87:24] wire out_wimask_45 = _out_wimask_T_45; // @[RegisterRouter.scala:87:24] wire _out_romask_T_45 = out_backMask[22]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_45 = out_backMask[22]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_100 = out_backMask[22]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_100 = out_backMask[22]; // @[RegisterRouter.scala:87:24] wire out_romask_45 = _out_romask_T_45; // @[RegisterRouter.scala:87:24] wire out_womask_45 = _out_womask_T_45; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_45 = out_rivalid_45 & out_rimask_45; // @[RegisterRouter.scala:87:24] wire _out_T_550 = out_f_rivalid_45; // @[RegisterRouter.scala:87:24] wire out_f_roready_45 = out_roready_45 & out_romask_45; // @[RegisterRouter.scala:87:24] wire _out_T_551 = out_f_roready_45; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_45 = out_wivalid_45 & out_wimask_45; // @[RegisterRouter.scala:87:24] wire _out_T_552 = out_f_wivalid_45; // @[RegisterRouter.scala:87:24] assign out_f_woready_45 = out_woready_45 & out_womask_45; // @[RegisterRouter.scala:87:24] assign sbbusyerrorWrEn = out_f_woready_45; // @[RegisterRouter.scala:87:24] wire _out_T_553 = out_f_woready_45; // @[RegisterRouter.scala:87:24] assign _out_T_549 = out_front_bits_data[22]; // @[RegisterRouter.scala:87:24] wire _out_T_1110 = out_front_bits_data[22]; // @[RegisterRouter.scala:87:24] assign SBCSWrData_sbbusyerror = _out_T_549; // @[RegisterRouter.scala:87:24] wire _out_T_554 = ~out_rimask_45; // @[RegisterRouter.scala:87:24] wire _out_T_555 = ~out_wimask_45; // @[RegisterRouter.scala:87:24] wire _out_T_556 = ~out_romask_45; // @[RegisterRouter.scala:87:24] wire _out_T_557 = ~out_womask_45; // @[RegisterRouter.scala:87:24] wire [22:0] out_prepend_35 = {SBCSRdData_sbbusyerror, _out_prepend_T_35}; // @[RegisterRouter.scala:87:24] wire [22:0] _out_T_558 = out_prepend_35; // @[RegisterRouter.scala:87:24] wire [22:0] _out_T_559 = _out_T_558; // @[RegisterRouter.scala:87:24] wire [22:0] _out_prepend_T_36 = _out_T_559; // @[RegisterRouter.scala:87:24] wire [5:0] _out_rimask_T_46 = out_frontMask[28:23]; // @[RegisterRouter.scala:87:24] wire [5:0] _out_wimask_T_46 = out_frontMask[28:23]; // @[RegisterRouter.scala:87:24] wire out_rimask_46 = |_out_rimask_T_46; // @[RegisterRouter.scala:87:24] wire out_wimask_46 = &_out_wimask_T_46; // @[RegisterRouter.scala:87:24] wire [5:0] _out_romask_T_46 = out_backMask[28:23]; // @[RegisterRouter.scala:87:24] wire [5:0] _out_womask_T_46 = out_backMask[28:23]; // @[RegisterRouter.scala:87:24] wire out_romask_46 = |_out_romask_T_46; // @[RegisterRouter.scala:87:24] wire out_womask_46 = &_out_womask_T_46; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_46 = out_rivalid_46 & out_rimask_46; // @[RegisterRouter.scala:87:24] wire _out_T_561 = out_f_rivalid_46; // @[RegisterRouter.scala:87:24] wire out_f_roready_46 = out_roready_46 & out_romask_46; // @[RegisterRouter.scala:87:24] wire _out_T_562 = out_f_roready_46; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_46 = out_wivalid_46 & out_wimask_46; // @[RegisterRouter.scala:87:24] wire out_f_woready_46 = out_woready_46 & out_womask_46; // @[RegisterRouter.scala:87:24] wire [5:0] _out_T_560 = out_front_bits_data[28:23]; // @[RegisterRouter.scala:87:24] wire _out_T_563 = ~out_rimask_46; // @[RegisterRouter.scala:87:24] wire _out_T_564 = ~out_wimask_46; // @[RegisterRouter.scala:87:24] wire _out_T_565 = ~out_romask_46; // @[RegisterRouter.scala:87:24] wire _out_T_566 = ~out_womask_46; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_36 = {1'h0, _out_prepend_T_36}; // @[RegisterRouter.scala:87:24] wire [28:0] _out_T_567 = {5'h0, out_prepend_36}; // @[RegisterRouter.scala:87:24] wire [28:0] _out_T_568 = _out_T_567; // @[RegisterRouter.scala:87:24] wire [28:0] _out_prepend_T_37 = _out_T_568; // @[RegisterRouter.scala:87:24] wire [2:0] _out_rimask_T_47 = out_frontMask[31:29]; // @[RegisterRouter.scala:87:24] wire [2:0] _out_wimask_T_47 = out_frontMask[31:29]; // @[RegisterRouter.scala:87:24] wire out_rimask_47 = |_out_rimask_T_47; // @[RegisterRouter.scala:87:24] wire out_wimask_47 = &_out_wimask_T_47; // @[RegisterRouter.scala:87:24] wire [2:0] _out_romask_T_47 = out_backMask[31:29]; // @[RegisterRouter.scala:87:24] wire [2:0] _out_womask_T_47 = out_backMask[31:29]; // @[RegisterRouter.scala:87:24] wire out_romask_47 = |_out_romask_T_47; // @[RegisterRouter.scala:87:24] wire out_womask_47 = &_out_womask_T_47; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_47 = out_rivalid_47 & out_rimask_47; // @[RegisterRouter.scala:87:24] wire _out_T_570 = out_f_rivalid_47; // @[RegisterRouter.scala:87:24] wire out_f_roready_47 = out_roready_47 & out_romask_47; // @[RegisterRouter.scala:87:24] wire _out_T_571 = out_f_roready_47; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_47 = out_wivalid_47 & out_wimask_47; // @[RegisterRouter.scala:87:24] wire out_f_woready_47 = out_woready_47 & out_womask_47; // @[RegisterRouter.scala:87:24] wire [2:0] _out_T_569 = out_front_bits_data[31:29]; // @[RegisterRouter.scala:87:24] wire _out_T_572 = ~out_rimask_47; // @[RegisterRouter.scala:87:24] wire _out_T_573 = ~out_wimask_47; // @[RegisterRouter.scala:87:24] wire _out_T_574 = ~out_romask_47; // @[RegisterRouter.scala:87:24] wire _out_T_575 = ~out_womask_47; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_37 = {3'h1, _out_prepend_T_37}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_576 = out_prepend_37; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_577 = _out_T_576; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_56 = _out_T_577; // @[MuxLiteral.scala:49:48] wire out_rimask_48 = |_out_rimask_T_48; // @[RegisterRouter.scala:87:24] wire out_wimask_48 = &_out_wimask_T_48; // @[RegisterRouter.scala:87:24] wire out_romask_48 = |_out_romask_T_48; // @[RegisterRouter.scala:87:24] wire out_womask_48 = &_out_womask_T_48; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_48 = out_rivalid_48 & out_rimask_48; // @[RegisterRouter.scala:87:24] wire _out_T_579 = out_f_rivalid_48; // @[RegisterRouter.scala:87:24] assign out_f_roready_48 = out_roready_48 & out_romask_48; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_40 = out_f_roready_48; // @[RegisterRouter.scala:87:24] wire _out_T_580 = out_f_roready_48; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_48 = out_wivalid_48 & out_wimask_48; // @[RegisterRouter.scala:87:24] wire _out_T_581 = out_f_wivalid_48; // @[RegisterRouter.scala:87:24] assign out_f_woready_48 = out_woready_48 & out_womask_48; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_40 = out_f_woready_48; // @[RegisterRouter.scala:87:24] wire _out_T_582 = out_f_woready_48; // @[RegisterRouter.scala:87:24] assign programBufferNxt_40 = out_f_woready_48 ? _out_T_578 : programBufferMem_40; // @[RegisterRouter.scala:87:24] wire _out_T_583 = ~out_rimask_48; // @[RegisterRouter.scala:87:24] wire _out_T_584 = ~out_wimask_48; // @[RegisterRouter.scala:87:24] wire _out_T_585 = ~out_romask_48; // @[RegisterRouter.scala:87:24] wire _out_T_586 = ~out_womask_48; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_588 = _out_T_587; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_38 = _out_T_588; // @[RegisterRouter.scala:87:24] wire out_rimask_49 = |_out_rimask_T_49; // @[RegisterRouter.scala:87:24] wire out_wimask_49 = &_out_wimask_T_49; // @[RegisterRouter.scala:87:24] wire out_romask_49 = |_out_romask_T_49; // @[RegisterRouter.scala:87:24] wire out_womask_49 = &_out_womask_T_49; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_49 = out_rivalid_49 & out_rimask_49; // @[RegisterRouter.scala:87:24] wire _out_T_590 = out_f_rivalid_49; // @[RegisterRouter.scala:87:24] assign out_f_roready_49 = out_roready_49 & out_romask_49; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_41 = out_f_roready_49; // @[RegisterRouter.scala:87:24] wire _out_T_591 = out_f_roready_49; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_49 = out_wivalid_49 & out_wimask_49; // @[RegisterRouter.scala:87:24] wire _out_T_592 = out_f_wivalid_49; // @[RegisterRouter.scala:87:24] assign out_f_woready_49 = out_woready_49 & out_womask_49; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_41 = out_f_woready_49; // @[RegisterRouter.scala:87:24] wire _out_T_593 = out_f_woready_49; // @[RegisterRouter.scala:87:24] assign programBufferNxt_41 = out_f_woready_49 ? _out_T_589 : programBufferMem_41; // @[RegisterRouter.scala:87:24] wire _out_T_594 = ~out_rimask_49; // @[RegisterRouter.scala:87:24] wire _out_T_595 = ~out_wimask_49; // @[RegisterRouter.scala:87:24] wire _out_T_596 = ~out_romask_49; // @[RegisterRouter.scala:87:24] wire _out_T_597 = ~out_womask_49; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_38 = {programBufferMem_41, _out_prepend_T_38}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_598 = out_prepend_38; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_599 = _out_T_598; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_39 = _out_T_599; // @[RegisterRouter.scala:87:24] wire out_rimask_50 = |_out_rimask_T_50; // @[RegisterRouter.scala:87:24] wire out_wimask_50 = &_out_wimask_T_50; // @[RegisterRouter.scala:87:24] wire out_romask_50 = |_out_romask_T_50; // @[RegisterRouter.scala:87:24] wire out_womask_50 = &_out_womask_T_50; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_50 = out_rivalid_50 & out_rimask_50; // @[RegisterRouter.scala:87:24] wire _out_T_601 = out_f_rivalid_50; // @[RegisterRouter.scala:87:24] assign out_f_roready_50 = out_roready_50 & out_romask_50; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_42 = out_f_roready_50; // @[RegisterRouter.scala:87:24] wire _out_T_602 = out_f_roready_50; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_50 = out_wivalid_50 & out_wimask_50; // @[RegisterRouter.scala:87:24] wire _out_T_603 = out_f_wivalid_50; // @[RegisterRouter.scala:87:24] assign out_f_woready_50 = out_woready_50 & out_womask_50; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_42 = out_f_woready_50; // @[RegisterRouter.scala:87:24] wire _out_T_604 = out_f_woready_50; // @[RegisterRouter.scala:87:24] assign programBufferNxt_42 = out_f_woready_50 ? _out_T_600 : programBufferMem_42; // @[RegisterRouter.scala:87:24] wire _out_T_605 = ~out_rimask_50; // @[RegisterRouter.scala:87:24] wire _out_T_606 = ~out_wimask_50; // @[RegisterRouter.scala:87:24] wire _out_T_607 = ~out_romask_50; // @[RegisterRouter.scala:87:24] wire _out_T_608 = ~out_womask_50; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_39 = {programBufferMem_42, _out_prepend_T_39}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_609 = out_prepend_39; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_610 = _out_T_609; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_40 = _out_T_610; // @[RegisterRouter.scala:87:24] wire out_rimask_51 = |_out_rimask_T_51; // @[RegisterRouter.scala:87:24] wire out_wimask_51 = &_out_wimask_T_51; // @[RegisterRouter.scala:87:24] wire out_romask_51 = |_out_romask_T_51; // @[RegisterRouter.scala:87:24] wire out_womask_51 = &_out_womask_T_51; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_51 = out_rivalid_51 & out_rimask_51; // @[RegisterRouter.scala:87:24] wire _out_T_612 = out_f_rivalid_51; // @[RegisterRouter.scala:87:24] assign out_f_roready_51 = out_roready_51 & out_romask_51; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_43 = out_f_roready_51; // @[RegisterRouter.scala:87:24] wire _out_T_613 = out_f_roready_51; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_51 = out_wivalid_51 & out_wimask_51; // @[RegisterRouter.scala:87:24] wire _out_T_614 = out_f_wivalid_51; // @[RegisterRouter.scala:87:24] assign out_f_woready_51 = out_woready_51 & out_womask_51; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_43 = out_f_woready_51; // @[RegisterRouter.scala:87:24] wire _out_T_615 = out_f_woready_51; // @[RegisterRouter.scala:87:24] assign programBufferNxt_43 = out_f_woready_51 ? _out_T_611 : programBufferMem_43; // @[RegisterRouter.scala:87:24] wire _out_T_616 = ~out_rimask_51; // @[RegisterRouter.scala:87:24] wire _out_T_617 = ~out_wimask_51; // @[RegisterRouter.scala:87:24] wire _out_T_618 = ~out_romask_51; // @[RegisterRouter.scala:87:24] wire _out_T_619 = ~out_womask_51; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_40 = {programBufferMem_43, _out_prepend_T_40}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_620 = out_prepend_40; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_621 = _out_T_620; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_42 = _out_T_621; // @[MuxLiteral.scala:49:48] wire out_rimask_52 = |_out_rimask_T_52; // @[RegisterRouter.scala:87:24] wire out_wimask_52 = &_out_wimask_T_52; // @[RegisterRouter.scala:87:24] wire out_romask_52 = |_out_romask_T_52; // @[RegisterRouter.scala:87:24] wire out_womask_52 = &_out_womask_T_52; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_52 = out_rivalid_52 & out_rimask_52; // @[RegisterRouter.scala:87:24] wire _out_T_623 = out_f_rivalid_52; // @[RegisterRouter.scala:87:24] wire out_f_roready_52 = out_roready_52 & out_romask_52; // @[RegisterRouter.scala:87:24] wire _out_T_624 = out_f_roready_52; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_52 = out_wivalid_52 & out_wimask_52; // @[RegisterRouter.scala:87:24] wire _out_T_625 = out_f_wivalid_52; // @[RegisterRouter.scala:87:24] assign out_f_woready_52 = out_woready_52 & out_womask_52; // @[RegisterRouter.scala:87:24] assign autoexecdataWrEnMaybe = out_f_woready_52; // @[RegisterRouter.scala:87:24] wire _out_T_626 = out_f_woready_52; // @[RegisterRouter.scala:87:24] assign ABSTRACTAUTOWrData_autoexecdata = {4'h0, _out_T_622}; // @[RegisterRouter.scala:87:24] wire _out_T_627 = ~out_rimask_52; // @[RegisterRouter.scala:87:24] wire _out_T_628 = ~out_wimask_52; // @[RegisterRouter.scala:87:24] wire _out_T_629 = ~out_romask_52; // @[RegisterRouter.scala:87:24] wire _out_T_630 = ~out_womask_52; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_632 = _out_T_631[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_41 = _out_T_632; // @[RegisterRouter.scala:87:24] wire out_rimask_53 = |_out_rimask_T_53; // @[RegisterRouter.scala:87:24] wire out_wimask_53 = &_out_wimask_T_53; // @[RegisterRouter.scala:87:24] wire out_romask_53 = |_out_romask_T_53; // @[RegisterRouter.scala:87:24] wire out_womask_53 = &_out_womask_T_53; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_53 = out_rivalid_53 & out_rimask_53; // @[RegisterRouter.scala:87:24] wire _out_T_634 = out_f_rivalid_53; // @[RegisterRouter.scala:87:24] wire out_f_roready_53 = out_roready_53 & out_romask_53; // @[RegisterRouter.scala:87:24] wire _out_T_635 = out_f_roready_53; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_53 = out_wivalid_53 & out_wimask_53; // @[RegisterRouter.scala:87:24] wire out_f_woready_53 = out_woready_53 & out_womask_53; // @[RegisterRouter.scala:87:24] wire _out_T_636 = ~out_rimask_53; // @[RegisterRouter.scala:87:24] wire _out_T_637 = ~out_wimask_53; // @[RegisterRouter.scala:87:24] wire _out_T_638 = ~out_romask_53; // @[RegisterRouter.scala:87:24] wire _out_T_639 = ~out_womask_53; // @[RegisterRouter.scala:87:24] wire [8:0] out_prepend_41 = {1'h0, _out_prepend_T_41}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_640 = {7'h0, out_prepend_41}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_641 = _out_T_640; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_42 = _out_T_641; // @[RegisterRouter.scala:87:24] wire [15:0] _out_rimask_T_54 = out_frontMask[31:16]; // @[RegisterRouter.scala:87:24] wire [15:0] _out_wimask_T_54 = out_frontMask[31:16]; // @[RegisterRouter.scala:87:24] wire out_rimask_54 = |_out_rimask_T_54; // @[RegisterRouter.scala:87:24] wire out_wimask_54 = &_out_wimask_T_54; // @[RegisterRouter.scala:87:24] wire [15:0] _out_romask_T_54 = out_backMask[31:16]; // @[RegisterRouter.scala:87:24] wire [15:0] _out_womask_T_54 = out_backMask[31:16]; // @[RegisterRouter.scala:87:24] wire out_romask_54 = |_out_romask_T_54; // @[RegisterRouter.scala:87:24] wire out_womask_54 = &_out_womask_T_54; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_54 = out_rivalid_54 & out_rimask_54; // @[RegisterRouter.scala:87:24] wire _out_T_643 = out_f_rivalid_54; // @[RegisterRouter.scala:87:24] wire out_f_roready_54 = out_roready_54 & out_romask_54; // @[RegisterRouter.scala:87:24] wire _out_T_644 = out_f_roready_54; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_54 = out_wivalid_54 & out_wimask_54; // @[RegisterRouter.scala:87:24] wire _out_T_645 = out_f_wivalid_54; // @[RegisterRouter.scala:87:24] assign out_f_woready_54 = out_woready_54 & out_womask_54; // @[RegisterRouter.scala:87:24] assign autoexecprogbufWrEnMaybe = out_f_woready_54; // @[RegisterRouter.scala:87:24] wire _out_T_646 = out_f_woready_54; // @[RegisterRouter.scala:87:24] assign _out_T_642 = out_front_bits_data[31:16]; // @[RegisterRouter.scala:87:24] assign ABSTRACTAUTOWrData_autoexecprogbuf = _out_T_642; // @[RegisterRouter.scala:87:24] wire _out_T_647 = ~out_rimask_54; // @[RegisterRouter.scala:87:24] wire _out_T_648 = ~out_wimask_54; // @[RegisterRouter.scala:87:24] wire _out_T_649 = ~out_romask_54; // @[RegisterRouter.scala:87:24] wire _out_T_650 = ~out_womask_54; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_42 = {ABSTRACTAUTORdData_autoexecprogbuf, _out_prepend_T_42}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_651 = out_prepend_42; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_652 = _out_T_651; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_24 = _out_T_652; // @[MuxLiteral.scala:49:48] wire out_rimask_55 = |_out_rimask_T_55; // @[RegisterRouter.scala:87:24] wire out_wimask_55 = &_out_wimask_T_55; // @[RegisterRouter.scala:87:24] wire out_romask_55 = |_out_romask_T_55; // @[RegisterRouter.scala:87:24] wire out_womask_55 = &_out_womask_T_55; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_55 = out_rivalid_55 & out_rimask_55; // @[RegisterRouter.scala:87:24] wire _out_T_654 = out_f_rivalid_55; // @[RegisterRouter.scala:87:24] assign out_f_roready_55 = out_roready_55 & out_romask_55; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_20 = out_f_roready_55; // @[RegisterRouter.scala:87:24] wire _out_T_655 = out_f_roready_55; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_55 = out_wivalid_55 & out_wimask_55; // @[RegisterRouter.scala:87:24] wire _out_T_656 = out_f_wivalid_55; // @[RegisterRouter.scala:87:24] assign out_f_woready_55 = out_woready_55 & out_womask_55; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_20 = out_f_woready_55; // @[RegisterRouter.scala:87:24] wire _out_T_657 = out_f_woready_55; // @[RegisterRouter.scala:87:24] assign programBufferNxt_20 = out_f_woready_55 ? _out_T_653 : programBufferMem_20; // @[RegisterRouter.scala:87:24] wire _out_T_658 = ~out_rimask_55; // @[RegisterRouter.scala:87:24] wire _out_T_659 = ~out_wimask_55; // @[RegisterRouter.scala:87:24] wire _out_T_660 = ~out_romask_55; // @[RegisterRouter.scala:87:24] wire _out_T_661 = ~out_womask_55; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_663 = _out_T_662; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_43 = _out_T_663; // @[RegisterRouter.scala:87:24] wire out_rimask_56 = |_out_rimask_T_56; // @[RegisterRouter.scala:87:24] wire out_wimask_56 = &_out_wimask_T_56; // @[RegisterRouter.scala:87:24] wire out_romask_56 = |_out_romask_T_56; // @[RegisterRouter.scala:87:24] wire out_womask_56 = &_out_womask_T_56; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_56 = out_rivalid_56 & out_rimask_56; // @[RegisterRouter.scala:87:24] wire _out_T_665 = out_f_rivalid_56; // @[RegisterRouter.scala:87:24] assign out_f_roready_56 = out_roready_56 & out_romask_56; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_21 = out_f_roready_56; // @[RegisterRouter.scala:87:24] wire _out_T_666 = out_f_roready_56; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_56 = out_wivalid_56 & out_wimask_56; // @[RegisterRouter.scala:87:24] wire _out_T_667 = out_f_wivalid_56; // @[RegisterRouter.scala:87:24] assign out_f_woready_56 = out_woready_56 & out_womask_56; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_21 = out_f_woready_56; // @[RegisterRouter.scala:87:24] wire _out_T_668 = out_f_woready_56; // @[RegisterRouter.scala:87:24] assign programBufferNxt_21 = out_f_woready_56 ? _out_T_664 : programBufferMem_21; // @[RegisterRouter.scala:87:24] wire _out_T_669 = ~out_rimask_56; // @[RegisterRouter.scala:87:24] wire _out_T_670 = ~out_wimask_56; // @[RegisterRouter.scala:87:24] wire _out_T_671 = ~out_romask_56; // @[RegisterRouter.scala:87:24] wire _out_T_672 = ~out_womask_56; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_43 = {programBufferMem_21, _out_prepend_T_43}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_673 = out_prepend_43; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_674 = _out_T_673; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_44 = _out_T_674; // @[RegisterRouter.scala:87:24] wire out_rimask_57 = |_out_rimask_T_57; // @[RegisterRouter.scala:87:24] wire out_wimask_57 = &_out_wimask_T_57; // @[RegisterRouter.scala:87:24] wire out_romask_57 = |_out_romask_T_57; // @[RegisterRouter.scala:87:24] wire out_womask_57 = &_out_womask_T_57; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_57 = out_rivalid_57 & out_rimask_57; // @[RegisterRouter.scala:87:24] wire _out_T_676 = out_f_rivalid_57; // @[RegisterRouter.scala:87:24] assign out_f_roready_57 = out_roready_57 & out_romask_57; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_22 = out_f_roready_57; // @[RegisterRouter.scala:87:24] wire _out_T_677 = out_f_roready_57; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_57 = out_wivalid_57 & out_wimask_57; // @[RegisterRouter.scala:87:24] wire _out_T_678 = out_f_wivalid_57; // @[RegisterRouter.scala:87:24] assign out_f_woready_57 = out_woready_57 & out_womask_57; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_22 = out_f_woready_57; // @[RegisterRouter.scala:87:24] wire _out_T_679 = out_f_woready_57; // @[RegisterRouter.scala:87:24] assign programBufferNxt_22 = out_f_woready_57 ? _out_T_675 : programBufferMem_22; // @[RegisterRouter.scala:87:24] wire _out_T_680 = ~out_rimask_57; // @[RegisterRouter.scala:87:24] wire _out_T_681 = ~out_wimask_57; // @[RegisterRouter.scala:87:24] wire _out_T_682 = ~out_romask_57; // @[RegisterRouter.scala:87:24] wire _out_T_683 = ~out_womask_57; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_44 = {programBufferMem_22, _out_prepend_T_44}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_684 = out_prepend_44; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_685 = _out_T_684; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_45 = _out_T_685; // @[RegisterRouter.scala:87:24] wire out_rimask_58 = |_out_rimask_T_58; // @[RegisterRouter.scala:87:24] wire out_wimask_58 = &_out_wimask_T_58; // @[RegisterRouter.scala:87:24] wire out_romask_58 = |_out_romask_T_58; // @[RegisterRouter.scala:87:24] wire out_womask_58 = &_out_womask_T_58; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_58 = out_rivalid_58 & out_rimask_58; // @[RegisterRouter.scala:87:24] wire _out_T_687 = out_f_rivalid_58; // @[RegisterRouter.scala:87:24] assign out_f_roready_58 = out_roready_58 & out_romask_58; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_23 = out_f_roready_58; // @[RegisterRouter.scala:87:24] wire _out_T_688 = out_f_roready_58; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_58 = out_wivalid_58 & out_wimask_58; // @[RegisterRouter.scala:87:24] wire _out_T_689 = out_f_wivalid_58; // @[RegisterRouter.scala:87:24] assign out_f_woready_58 = out_woready_58 & out_womask_58; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_23 = out_f_woready_58; // @[RegisterRouter.scala:87:24] wire _out_T_690 = out_f_woready_58; // @[RegisterRouter.scala:87:24] assign programBufferNxt_23 = out_f_woready_58 ? _out_T_686 : programBufferMem_23; // @[RegisterRouter.scala:87:24] wire _out_T_691 = ~out_rimask_58; // @[RegisterRouter.scala:87:24] wire _out_T_692 = ~out_wimask_58; // @[RegisterRouter.scala:87:24] wire _out_T_693 = ~out_romask_58; // @[RegisterRouter.scala:87:24] wire _out_T_694 = ~out_womask_58; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_45 = {programBufferMem_23, _out_prepend_T_45}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_695 = out_prepend_45; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_696 = _out_T_695; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_37 = _out_T_696; // @[MuxLiteral.scala:49:48] wire out_rimask_59 = |_out_rimask_T_59; // @[RegisterRouter.scala:87:24] wire out_wimask_59 = &_out_wimask_T_59; // @[RegisterRouter.scala:87:24] wire out_romask_59 = |_out_romask_T_59; // @[RegisterRouter.scala:87:24] wire out_womask_59 = &_out_womask_T_59; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_59 = out_rivalid_59 & out_rimask_59; // @[RegisterRouter.scala:87:24] wire _out_T_698 = out_f_rivalid_59; // @[RegisterRouter.scala:87:24] assign out_f_roready_59 = out_roready_59 & out_romask_59; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_56 = out_f_roready_59; // @[RegisterRouter.scala:87:24] wire _out_T_699 = out_f_roready_59; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_59 = out_wivalid_59 & out_wimask_59; // @[RegisterRouter.scala:87:24] wire _out_T_700 = out_f_wivalid_59; // @[RegisterRouter.scala:87:24] assign out_f_woready_59 = out_woready_59 & out_womask_59; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_56 = out_f_woready_59; // @[RegisterRouter.scala:87:24] wire _out_T_701 = out_f_woready_59; // @[RegisterRouter.scala:87:24] assign programBufferNxt_56 = out_f_woready_59 ? _out_T_697 : programBufferMem_56; // @[RegisterRouter.scala:87:24] wire _out_T_702 = ~out_rimask_59; // @[RegisterRouter.scala:87:24] wire _out_T_703 = ~out_wimask_59; // @[RegisterRouter.scala:87:24] wire _out_T_704 = ~out_romask_59; // @[RegisterRouter.scala:87:24] wire _out_T_705 = ~out_womask_59; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_707 = _out_T_706; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_46 = _out_T_707; // @[RegisterRouter.scala:87:24] wire out_rimask_60 = |_out_rimask_T_60; // @[RegisterRouter.scala:87:24] wire out_wimask_60 = &_out_wimask_T_60; // @[RegisterRouter.scala:87:24] wire out_romask_60 = |_out_romask_T_60; // @[RegisterRouter.scala:87:24] wire out_womask_60 = &_out_womask_T_60; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_60 = out_rivalid_60 & out_rimask_60; // @[RegisterRouter.scala:87:24] wire _out_T_709 = out_f_rivalid_60; // @[RegisterRouter.scala:87:24] assign out_f_roready_60 = out_roready_60 & out_romask_60; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_57 = out_f_roready_60; // @[RegisterRouter.scala:87:24] wire _out_T_710 = out_f_roready_60; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_60 = out_wivalid_60 & out_wimask_60; // @[RegisterRouter.scala:87:24] wire _out_T_711 = out_f_wivalid_60; // @[RegisterRouter.scala:87:24] assign out_f_woready_60 = out_woready_60 & out_womask_60; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_57 = out_f_woready_60; // @[RegisterRouter.scala:87:24] wire _out_T_712 = out_f_woready_60; // @[RegisterRouter.scala:87:24] assign programBufferNxt_57 = out_f_woready_60 ? _out_T_708 : programBufferMem_57; // @[RegisterRouter.scala:87:24] wire _out_T_713 = ~out_rimask_60; // @[RegisterRouter.scala:87:24] wire _out_T_714 = ~out_wimask_60; // @[RegisterRouter.scala:87:24] wire _out_T_715 = ~out_romask_60; // @[RegisterRouter.scala:87:24] wire _out_T_716 = ~out_womask_60; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_46 = {programBufferMem_57, _out_prepend_T_46}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_717 = out_prepend_46; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_718 = _out_T_717; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_47 = _out_T_718; // @[RegisterRouter.scala:87:24] wire out_rimask_61 = |_out_rimask_T_61; // @[RegisterRouter.scala:87:24] wire out_wimask_61 = &_out_wimask_T_61; // @[RegisterRouter.scala:87:24] wire out_romask_61 = |_out_romask_T_61; // @[RegisterRouter.scala:87:24] wire out_womask_61 = &_out_womask_T_61; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_61 = out_rivalid_61 & out_rimask_61; // @[RegisterRouter.scala:87:24] wire _out_T_720 = out_f_rivalid_61; // @[RegisterRouter.scala:87:24] assign out_f_roready_61 = out_roready_61 & out_romask_61; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_58 = out_f_roready_61; // @[RegisterRouter.scala:87:24] wire _out_T_721 = out_f_roready_61; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_61 = out_wivalid_61 & out_wimask_61; // @[RegisterRouter.scala:87:24] wire _out_T_722 = out_f_wivalid_61; // @[RegisterRouter.scala:87:24] assign out_f_woready_61 = out_woready_61 & out_womask_61; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_58 = out_f_woready_61; // @[RegisterRouter.scala:87:24] wire _out_T_723 = out_f_woready_61; // @[RegisterRouter.scala:87:24] assign programBufferNxt_58 = out_f_woready_61 ? _out_T_719 : programBufferMem_58; // @[RegisterRouter.scala:87:24] wire _out_T_724 = ~out_rimask_61; // @[RegisterRouter.scala:87:24] wire _out_T_725 = ~out_wimask_61; // @[RegisterRouter.scala:87:24] wire _out_T_726 = ~out_romask_61; // @[RegisterRouter.scala:87:24] wire _out_T_727 = ~out_womask_61; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_47 = {programBufferMem_58, _out_prepend_T_47}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_728 = out_prepend_47; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_729 = _out_T_728; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_48 = _out_T_729; // @[RegisterRouter.scala:87:24] wire out_rimask_62 = |_out_rimask_T_62; // @[RegisterRouter.scala:87:24] wire out_wimask_62 = &_out_wimask_T_62; // @[RegisterRouter.scala:87:24] wire out_romask_62 = |_out_romask_T_62; // @[RegisterRouter.scala:87:24] wire out_womask_62 = &_out_womask_T_62; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_62 = out_rivalid_62 & out_rimask_62; // @[RegisterRouter.scala:87:24] wire _out_T_731 = out_f_rivalid_62; // @[RegisterRouter.scala:87:24] assign out_f_roready_62 = out_roready_62 & out_romask_62; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_59 = out_f_roready_62; // @[RegisterRouter.scala:87:24] wire _out_T_732 = out_f_roready_62; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_62 = out_wivalid_62 & out_wimask_62; // @[RegisterRouter.scala:87:24] wire _out_T_733 = out_f_wivalid_62; // @[RegisterRouter.scala:87:24] assign out_f_woready_62 = out_woready_62 & out_womask_62; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_59 = out_f_woready_62; // @[RegisterRouter.scala:87:24] wire _out_T_734 = out_f_woready_62; // @[RegisterRouter.scala:87:24] assign programBufferNxt_59 = out_f_woready_62 ? _out_T_730 : programBufferMem_59; // @[RegisterRouter.scala:87:24] wire _out_T_735 = ~out_rimask_62; // @[RegisterRouter.scala:87:24] wire _out_T_736 = ~out_wimask_62; // @[RegisterRouter.scala:87:24] wire _out_T_737 = ~out_romask_62; // @[RegisterRouter.scala:87:24] wire _out_T_738 = ~out_womask_62; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_48 = {programBufferMem_59, _out_prepend_T_48}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_739 = out_prepend_48; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_740 = _out_T_739; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_46 = _out_T_740; // @[MuxLiteral.scala:49:48] wire out_rimask_63 = |_out_rimask_T_63; // @[RegisterRouter.scala:87:24] wire out_wimask_63 = &_out_wimask_T_63; // @[RegisterRouter.scala:87:24] wire out_romask_63 = |_out_romask_T_63; // @[RegisterRouter.scala:87:24] wire out_womask_63 = &_out_womask_T_63; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_63 = out_rivalid_63 & out_rimask_63; // @[RegisterRouter.scala:87:24] wire _out_T_742 = out_f_rivalid_63; // @[RegisterRouter.scala:87:24] assign out_f_roready_63 = out_roready_63 & out_romask_63; // @[RegisterRouter.scala:87:24] assign SBADDRESSRdEn_0 = out_f_roready_63; // @[RegisterRouter.scala:87:24] wire _out_T_743 = out_f_roready_63; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_63 = out_wivalid_63 & out_wimask_63; // @[RegisterRouter.scala:87:24] wire _out_T_744 = out_f_wivalid_63; // @[RegisterRouter.scala:87:24] assign out_f_woready_63 = out_woready_63 & out_womask_63; // @[RegisterRouter.scala:87:24] assign SBADDRESSWrEn_0 = out_f_woready_63; // @[RegisterRouter.scala:87:24] wire _out_T_745 = out_f_woready_63; // @[RegisterRouter.scala:87:24] assign SBADDRESSWrData_0 = out_f_woready_63 ? _out_T_741 : 32'h0; // @[RegisterRouter.scala:87:24] wire _out_T_746 = ~out_rimask_63; // @[RegisterRouter.scala:87:24] wire _out_T_747 = ~out_wimask_63; // @[RegisterRouter.scala:87:24] wire _out_T_748 = ~out_romask_63; // @[RegisterRouter.scala:87:24] wire _out_T_749 = ~out_womask_63; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_751 = _out_T_750; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_57 = _out_T_751; // @[MuxLiteral.scala:49:48] wire out_rimask_64 = |_out_rimask_T_64; // @[RegisterRouter.scala:87:24] wire out_wimask_64 = &_out_wimask_T_64; // @[RegisterRouter.scala:87:24] wire out_romask_64 = |_out_romask_T_64; // @[RegisterRouter.scala:87:24] wire out_womask_64 = &_out_womask_T_64; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_64 = out_rivalid_64 & out_rimask_64; // @[RegisterRouter.scala:87:24] wire _out_T_753 = out_f_rivalid_64; // @[RegisterRouter.scala:87:24] assign out_f_roready_64 = out_roready_64 & out_romask_64; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_8 = out_f_roready_64; // @[RegisterRouter.scala:87:24] wire _out_T_754 = out_f_roready_64; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_64 = out_wivalid_64 & out_wimask_64; // @[RegisterRouter.scala:87:24] wire _out_T_755 = out_f_wivalid_64; // @[RegisterRouter.scala:87:24] assign out_f_woready_64 = out_woready_64 & out_womask_64; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_8 = out_f_woready_64; // @[RegisterRouter.scala:87:24] wire _out_T_756 = out_f_woready_64; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_8 = out_f_woready_64 ? _out_T_752 : abstractDataMem_8; // @[RegisterRouter.scala:87:24] wire _out_T_757 = ~out_rimask_64; // @[RegisterRouter.scala:87:24] wire _out_T_758 = ~out_wimask_64; // @[RegisterRouter.scala:87:24] wire _out_T_759 = ~out_romask_64; // @[RegisterRouter.scala:87:24] wire _out_T_760 = ~out_womask_64; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_762 = _out_T_761; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_49 = _out_T_762; // @[RegisterRouter.scala:87:24] wire out_rimask_65 = |_out_rimask_T_65; // @[RegisterRouter.scala:87:24] wire out_wimask_65 = &_out_wimask_T_65; // @[RegisterRouter.scala:87:24] wire out_romask_65 = |_out_romask_T_65; // @[RegisterRouter.scala:87:24] wire out_womask_65 = &_out_womask_T_65; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_65 = out_rivalid_65 & out_rimask_65; // @[RegisterRouter.scala:87:24] wire _out_T_764 = out_f_rivalid_65; // @[RegisterRouter.scala:87:24] assign out_f_roready_65 = out_roready_65 & out_romask_65; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_9 = out_f_roready_65; // @[RegisterRouter.scala:87:24] wire _out_T_765 = out_f_roready_65; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_65 = out_wivalid_65 & out_wimask_65; // @[RegisterRouter.scala:87:24] wire _out_T_766 = out_f_wivalid_65; // @[RegisterRouter.scala:87:24] assign out_f_woready_65 = out_woready_65 & out_womask_65; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_9 = out_f_woready_65; // @[RegisterRouter.scala:87:24] wire _out_T_767 = out_f_woready_65; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_9 = out_f_woready_65 ? _out_T_763 : abstractDataMem_9; // @[RegisterRouter.scala:87:24] wire _out_T_768 = ~out_rimask_65; // @[RegisterRouter.scala:87:24] wire _out_T_769 = ~out_wimask_65; // @[RegisterRouter.scala:87:24] wire _out_T_770 = ~out_romask_65; // @[RegisterRouter.scala:87:24] wire _out_T_771 = ~out_womask_65; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_49 = {abstractDataMem_9, _out_prepend_T_49}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_772 = out_prepend_49; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_773 = _out_T_772; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_50 = _out_T_773; // @[RegisterRouter.scala:87:24] wire out_rimask_66 = |_out_rimask_T_66; // @[RegisterRouter.scala:87:24] wire out_wimask_66 = &_out_wimask_T_66; // @[RegisterRouter.scala:87:24] wire out_romask_66 = |_out_romask_T_66; // @[RegisterRouter.scala:87:24] wire out_womask_66 = &_out_womask_T_66; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_66 = out_rivalid_66 & out_rimask_66; // @[RegisterRouter.scala:87:24] wire _out_T_775 = out_f_rivalid_66; // @[RegisterRouter.scala:87:24] assign out_f_roready_66 = out_roready_66 & out_romask_66; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_10 = out_f_roready_66; // @[RegisterRouter.scala:87:24] wire _out_T_776 = out_f_roready_66; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_66 = out_wivalid_66 & out_wimask_66; // @[RegisterRouter.scala:87:24] wire _out_T_777 = out_f_wivalid_66; // @[RegisterRouter.scala:87:24] assign out_f_woready_66 = out_woready_66 & out_womask_66; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_10 = out_f_woready_66; // @[RegisterRouter.scala:87:24] wire _out_T_778 = out_f_woready_66; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_10 = out_f_woready_66 ? _out_T_774 : abstractDataMem_10; // @[RegisterRouter.scala:87:24] wire _out_T_779 = ~out_rimask_66; // @[RegisterRouter.scala:87:24] wire _out_T_780 = ~out_wimask_66; // @[RegisterRouter.scala:87:24] wire _out_T_781 = ~out_romask_66; // @[RegisterRouter.scala:87:24] wire _out_T_782 = ~out_womask_66; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_50 = {abstractDataMem_10, _out_prepend_T_50}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_783 = out_prepend_50; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_784 = _out_T_783; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_51 = _out_T_784; // @[RegisterRouter.scala:87:24] wire out_rimask_67 = |_out_rimask_T_67; // @[RegisterRouter.scala:87:24] wire out_wimask_67 = &_out_wimask_T_67; // @[RegisterRouter.scala:87:24] wire out_romask_67 = |_out_romask_T_67; // @[RegisterRouter.scala:87:24] wire out_womask_67 = &_out_womask_T_67; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_67 = out_rivalid_67 & out_rimask_67; // @[RegisterRouter.scala:87:24] wire _out_T_786 = out_f_rivalid_67; // @[RegisterRouter.scala:87:24] assign out_f_roready_67 = out_roready_67 & out_romask_67; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_11 = out_f_roready_67; // @[RegisterRouter.scala:87:24] wire _out_T_787 = out_f_roready_67; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_67 = out_wivalid_67 & out_wimask_67; // @[RegisterRouter.scala:87:24] wire _out_T_788 = out_f_wivalid_67; // @[RegisterRouter.scala:87:24] assign out_f_woready_67 = out_woready_67 & out_womask_67; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_11 = out_f_woready_67; // @[RegisterRouter.scala:87:24] wire _out_T_789 = out_f_woready_67; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_11 = out_f_woready_67 ? _out_T_785 : abstractDataMem_11; // @[RegisterRouter.scala:87:24] wire _out_T_790 = ~out_rimask_67; // @[RegisterRouter.scala:87:24] wire _out_T_791 = ~out_wimask_67; // @[RegisterRouter.scala:87:24] wire _out_T_792 = ~out_romask_67; // @[RegisterRouter.scala:87:24] wire _out_T_793 = ~out_womask_67; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_51 = {abstractDataMem_11, _out_prepend_T_51}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_794 = out_prepend_51; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_795 = _out_T_794; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_6 = _out_T_795; // @[MuxLiteral.scala:49:48] wire out_rimask_68 = |_out_rimask_T_68; // @[RegisterRouter.scala:87:24] wire out_wimask_68 = &_out_wimask_T_68; // @[RegisterRouter.scala:87:24] wire out_romask_68 = |_out_romask_T_68; // @[RegisterRouter.scala:87:24] wire out_womask_68 = &_out_womask_T_68; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_68 = out_rivalid_68 & out_rimask_68; // @[RegisterRouter.scala:87:24] wire _out_T_797 = out_f_rivalid_68; // @[RegisterRouter.scala:87:24] assign out_f_roready_68 = out_roready_68 & out_romask_68; // @[RegisterRouter.scala:87:24] assign SBDATARdEn_0 = out_f_roready_68; // @[RegisterRouter.scala:87:24] wire _out_T_798 = out_f_roready_68; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_68 = out_wivalid_68 & out_wimask_68; // @[RegisterRouter.scala:87:24] wire _out_T_799 = out_f_wivalid_68; // @[RegisterRouter.scala:87:24] assign out_f_woready_68 = out_woready_68 & out_womask_68; // @[RegisterRouter.scala:87:24] assign SBDATAWrEn_0 = out_f_woready_68; // @[RegisterRouter.scala:87:24] wire _out_T_800 = out_f_woready_68; // @[RegisterRouter.scala:87:24] assign SBDATAWrData_0 = out_f_woready_68 ? _out_T_796 : 32'h0; // @[RegisterRouter.scala:87:24] wire _out_T_801 = ~out_rimask_68; // @[RegisterRouter.scala:87:24] wire _out_T_802 = ~out_wimask_68; // @[RegisterRouter.scala:87:24] wire _out_T_803 = ~out_romask_68; // @[RegisterRouter.scala:87:24] wire _out_T_804 = ~out_womask_68; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_806 = _out_T_805; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_60 = _out_T_806; // @[MuxLiteral.scala:49:48] wire out_rimask_69 = |_out_rimask_T_69; // @[RegisterRouter.scala:87:24] wire out_wimask_69 = &_out_wimask_T_69; // @[RegisterRouter.scala:87:24] wire out_romask_69 = |_out_romask_T_69; // @[RegisterRouter.scala:87:24] wire out_womask_69 = &_out_womask_T_69; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_69 = out_rivalid_69 & out_rimask_69; // @[RegisterRouter.scala:87:24] wire _out_T_808 = out_f_rivalid_69; // @[RegisterRouter.scala:87:24] assign out_f_roready_69 = out_roready_69 & out_romask_69; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_24 = out_f_roready_69; // @[RegisterRouter.scala:87:24] wire _out_T_809 = out_f_roready_69; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_69 = out_wivalid_69 & out_wimask_69; // @[RegisterRouter.scala:87:24] wire _out_T_810 = out_f_wivalid_69; // @[RegisterRouter.scala:87:24] assign out_f_woready_69 = out_woready_69 & out_womask_69; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_24 = out_f_woready_69; // @[RegisterRouter.scala:87:24] wire _out_T_811 = out_f_woready_69; // @[RegisterRouter.scala:87:24] assign programBufferNxt_24 = out_f_woready_69 ? _out_T_807 : programBufferMem_24; // @[RegisterRouter.scala:87:24] wire _out_T_812 = ~out_rimask_69; // @[RegisterRouter.scala:87:24] wire _out_T_813 = ~out_wimask_69; // @[RegisterRouter.scala:87:24] wire _out_T_814 = ~out_romask_69; // @[RegisterRouter.scala:87:24] wire _out_T_815 = ~out_womask_69; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_817 = _out_T_816; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_52 = _out_T_817; // @[RegisterRouter.scala:87:24] wire out_rimask_70 = |_out_rimask_T_70; // @[RegisterRouter.scala:87:24] wire out_wimask_70 = &_out_wimask_T_70; // @[RegisterRouter.scala:87:24] wire out_romask_70 = |_out_romask_T_70; // @[RegisterRouter.scala:87:24] wire out_womask_70 = &_out_womask_T_70; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_70 = out_rivalid_70 & out_rimask_70; // @[RegisterRouter.scala:87:24] wire _out_T_819 = out_f_rivalid_70; // @[RegisterRouter.scala:87:24] assign out_f_roready_70 = out_roready_70 & out_romask_70; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_25 = out_f_roready_70; // @[RegisterRouter.scala:87:24] wire _out_T_820 = out_f_roready_70; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_70 = out_wivalid_70 & out_wimask_70; // @[RegisterRouter.scala:87:24] wire _out_T_821 = out_f_wivalid_70; // @[RegisterRouter.scala:87:24] assign out_f_woready_70 = out_woready_70 & out_womask_70; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_25 = out_f_woready_70; // @[RegisterRouter.scala:87:24] wire _out_T_822 = out_f_woready_70; // @[RegisterRouter.scala:87:24] assign programBufferNxt_25 = out_f_woready_70 ? _out_T_818 : programBufferMem_25; // @[RegisterRouter.scala:87:24] wire _out_T_823 = ~out_rimask_70; // @[RegisterRouter.scala:87:24] wire _out_T_824 = ~out_wimask_70; // @[RegisterRouter.scala:87:24] wire _out_T_825 = ~out_romask_70; // @[RegisterRouter.scala:87:24] wire _out_T_826 = ~out_womask_70; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_52 = {programBufferMem_25, _out_prepend_T_52}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_827 = out_prepend_52; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_828 = _out_T_827; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_53 = _out_T_828; // @[RegisterRouter.scala:87:24] wire out_rimask_71 = |_out_rimask_T_71; // @[RegisterRouter.scala:87:24] wire out_wimask_71 = &_out_wimask_T_71; // @[RegisterRouter.scala:87:24] wire out_romask_71 = |_out_romask_T_71; // @[RegisterRouter.scala:87:24] wire out_womask_71 = &_out_womask_T_71; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_71 = out_rivalid_71 & out_rimask_71; // @[RegisterRouter.scala:87:24] wire _out_T_830 = out_f_rivalid_71; // @[RegisterRouter.scala:87:24] assign out_f_roready_71 = out_roready_71 & out_romask_71; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_26 = out_f_roready_71; // @[RegisterRouter.scala:87:24] wire _out_T_831 = out_f_roready_71; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_71 = out_wivalid_71 & out_wimask_71; // @[RegisterRouter.scala:87:24] wire _out_T_832 = out_f_wivalid_71; // @[RegisterRouter.scala:87:24] assign out_f_woready_71 = out_woready_71 & out_womask_71; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_26 = out_f_woready_71; // @[RegisterRouter.scala:87:24] wire _out_T_833 = out_f_woready_71; // @[RegisterRouter.scala:87:24] assign programBufferNxt_26 = out_f_woready_71 ? _out_T_829 : programBufferMem_26; // @[RegisterRouter.scala:87:24] wire _out_T_834 = ~out_rimask_71; // @[RegisterRouter.scala:87:24] wire _out_T_835 = ~out_wimask_71; // @[RegisterRouter.scala:87:24] wire _out_T_836 = ~out_romask_71; // @[RegisterRouter.scala:87:24] wire _out_T_837 = ~out_womask_71; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_53 = {programBufferMem_26, _out_prepend_T_53}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_838 = out_prepend_53; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_839 = _out_T_838; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_54 = _out_T_839; // @[RegisterRouter.scala:87:24] wire out_rimask_72 = |_out_rimask_T_72; // @[RegisterRouter.scala:87:24] wire out_wimask_72 = &_out_wimask_T_72; // @[RegisterRouter.scala:87:24] wire out_romask_72 = |_out_romask_T_72; // @[RegisterRouter.scala:87:24] wire out_womask_72 = &_out_womask_T_72; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_72 = out_rivalid_72 & out_rimask_72; // @[RegisterRouter.scala:87:24] wire _out_T_841 = out_f_rivalid_72; // @[RegisterRouter.scala:87:24] assign out_f_roready_72 = out_roready_72 & out_romask_72; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_27 = out_f_roready_72; // @[RegisterRouter.scala:87:24] wire _out_T_842 = out_f_roready_72; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_72 = out_wivalid_72 & out_wimask_72; // @[RegisterRouter.scala:87:24] wire _out_T_843 = out_f_wivalid_72; // @[RegisterRouter.scala:87:24] assign out_f_woready_72 = out_woready_72 & out_womask_72; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_27 = out_f_woready_72; // @[RegisterRouter.scala:87:24] wire _out_T_844 = out_f_woready_72; // @[RegisterRouter.scala:87:24] assign programBufferNxt_27 = out_f_woready_72 ? _out_T_840 : programBufferMem_27; // @[RegisterRouter.scala:87:24] wire _out_T_845 = ~out_rimask_72; // @[RegisterRouter.scala:87:24] wire _out_T_846 = ~out_wimask_72; // @[RegisterRouter.scala:87:24] wire _out_T_847 = ~out_romask_72; // @[RegisterRouter.scala:87:24] wire _out_T_848 = ~out_womask_72; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_54 = {programBufferMem_27, _out_prepend_T_54}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_849 = out_prepend_54; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_850 = _out_T_849; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_38 = _out_T_850; // @[MuxLiteral.scala:49:48] wire out_rimask_73 = |_out_rimask_T_73; // @[RegisterRouter.scala:87:24] wire out_wimask_73 = &_out_wimask_T_73; // @[RegisterRouter.scala:87:24] wire out_romask_73 = |_out_romask_T_73; // @[RegisterRouter.scala:87:24] wire out_womask_73 = &_out_womask_T_73; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_73 = out_rivalid_73 & out_rimask_73; // @[RegisterRouter.scala:87:24] wire _out_T_852 = out_f_rivalid_73; // @[RegisterRouter.scala:87:24] assign out_f_roready_73 = out_roready_73 & out_romask_73; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_4 = out_f_roready_73; // @[RegisterRouter.scala:87:24] wire _out_T_853 = out_f_roready_73; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_73 = out_wivalid_73 & out_wimask_73; // @[RegisterRouter.scala:87:24] wire _out_T_854 = out_f_wivalid_73; // @[RegisterRouter.scala:87:24] assign out_f_woready_73 = out_woready_73 & out_womask_73; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_4 = out_f_woready_73; // @[RegisterRouter.scala:87:24] wire _out_T_855 = out_f_woready_73; // @[RegisterRouter.scala:87:24] assign programBufferNxt_4 = out_f_woready_73 ? _out_T_851 : programBufferMem_4; // @[RegisterRouter.scala:87:24] wire _out_T_856 = ~out_rimask_73; // @[RegisterRouter.scala:87:24] wire _out_T_857 = ~out_wimask_73; // @[RegisterRouter.scala:87:24] wire _out_T_858 = ~out_romask_73; // @[RegisterRouter.scala:87:24] wire _out_T_859 = ~out_womask_73; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_861 = _out_T_860; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_55 = _out_T_861; // @[RegisterRouter.scala:87:24] wire out_rimask_74 = |_out_rimask_T_74; // @[RegisterRouter.scala:87:24] wire out_wimask_74 = &_out_wimask_T_74; // @[RegisterRouter.scala:87:24] wire out_romask_74 = |_out_romask_T_74; // @[RegisterRouter.scala:87:24] wire out_womask_74 = &_out_womask_T_74; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_74 = out_rivalid_74 & out_rimask_74; // @[RegisterRouter.scala:87:24] wire _out_T_863 = out_f_rivalid_74; // @[RegisterRouter.scala:87:24] assign out_f_roready_74 = out_roready_74 & out_romask_74; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_5 = out_f_roready_74; // @[RegisterRouter.scala:87:24] wire _out_T_864 = out_f_roready_74; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_74 = out_wivalid_74 & out_wimask_74; // @[RegisterRouter.scala:87:24] wire _out_T_865 = out_f_wivalid_74; // @[RegisterRouter.scala:87:24] assign out_f_woready_74 = out_woready_74 & out_womask_74; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_5 = out_f_woready_74; // @[RegisterRouter.scala:87:24] wire _out_T_866 = out_f_woready_74; // @[RegisterRouter.scala:87:24] assign programBufferNxt_5 = out_f_woready_74 ? _out_T_862 : programBufferMem_5; // @[RegisterRouter.scala:87:24] wire _out_T_867 = ~out_rimask_74; // @[RegisterRouter.scala:87:24] wire _out_T_868 = ~out_wimask_74; // @[RegisterRouter.scala:87:24] wire _out_T_869 = ~out_romask_74; // @[RegisterRouter.scala:87:24] wire _out_T_870 = ~out_womask_74; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_55 = {programBufferMem_5, _out_prepend_T_55}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_871 = out_prepend_55; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_872 = _out_T_871; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_56 = _out_T_872; // @[RegisterRouter.scala:87:24] wire out_rimask_75 = |_out_rimask_T_75; // @[RegisterRouter.scala:87:24] wire out_wimask_75 = &_out_wimask_T_75; // @[RegisterRouter.scala:87:24] wire out_romask_75 = |_out_romask_T_75; // @[RegisterRouter.scala:87:24] wire out_womask_75 = &_out_womask_T_75; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_75 = out_rivalid_75 & out_rimask_75; // @[RegisterRouter.scala:87:24] wire _out_T_874 = out_f_rivalid_75; // @[RegisterRouter.scala:87:24] assign out_f_roready_75 = out_roready_75 & out_romask_75; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_6 = out_f_roready_75; // @[RegisterRouter.scala:87:24] wire _out_T_875 = out_f_roready_75; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_75 = out_wivalid_75 & out_wimask_75; // @[RegisterRouter.scala:87:24] wire _out_T_876 = out_f_wivalid_75; // @[RegisterRouter.scala:87:24] assign out_f_woready_75 = out_woready_75 & out_womask_75; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_6 = out_f_woready_75; // @[RegisterRouter.scala:87:24] wire _out_T_877 = out_f_woready_75; // @[RegisterRouter.scala:87:24] assign programBufferNxt_6 = out_f_woready_75 ? _out_T_873 : programBufferMem_6; // @[RegisterRouter.scala:87:24] wire _out_T_878 = ~out_rimask_75; // @[RegisterRouter.scala:87:24] wire _out_T_879 = ~out_wimask_75; // @[RegisterRouter.scala:87:24] wire _out_T_880 = ~out_romask_75; // @[RegisterRouter.scala:87:24] wire _out_T_881 = ~out_womask_75; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_56 = {programBufferMem_6, _out_prepend_T_56}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_882 = out_prepend_56; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_883 = _out_T_882; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_57 = _out_T_883; // @[RegisterRouter.scala:87:24] wire out_rimask_76 = |_out_rimask_T_76; // @[RegisterRouter.scala:87:24] wire out_wimask_76 = &_out_wimask_T_76; // @[RegisterRouter.scala:87:24] wire out_romask_76 = |_out_romask_T_76; // @[RegisterRouter.scala:87:24] wire out_womask_76 = &_out_womask_T_76; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_76 = out_rivalid_76 & out_rimask_76; // @[RegisterRouter.scala:87:24] wire _out_T_885 = out_f_rivalid_76; // @[RegisterRouter.scala:87:24] assign out_f_roready_76 = out_roready_76 & out_romask_76; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_7 = out_f_roready_76; // @[RegisterRouter.scala:87:24] wire _out_T_886 = out_f_roready_76; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_76 = out_wivalid_76 & out_wimask_76; // @[RegisterRouter.scala:87:24] wire _out_T_887 = out_f_wivalid_76; // @[RegisterRouter.scala:87:24] assign out_f_woready_76 = out_woready_76 & out_womask_76; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_7 = out_f_woready_76; // @[RegisterRouter.scala:87:24] wire _out_T_888 = out_f_woready_76; // @[RegisterRouter.scala:87:24] assign programBufferNxt_7 = out_f_woready_76 ? _out_T_884 : programBufferMem_7; // @[RegisterRouter.scala:87:24] wire _out_T_889 = ~out_rimask_76; // @[RegisterRouter.scala:87:24] wire _out_T_890 = ~out_wimask_76; // @[RegisterRouter.scala:87:24] wire _out_T_891 = ~out_romask_76; // @[RegisterRouter.scala:87:24] wire _out_T_892 = ~out_womask_76; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_57 = {programBufferMem_7, _out_prepend_T_57}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_893 = out_prepend_57; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_894 = _out_T_893; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_33 = _out_T_894; // @[MuxLiteral.scala:49:48] wire out_rimask_77 = |_out_rimask_T_77; // @[RegisterRouter.scala:87:24] wire out_wimask_77 = &_out_wimask_T_77; // @[RegisterRouter.scala:87:24] wire out_romask_77 = |_out_romask_T_77; // @[RegisterRouter.scala:87:24] wire out_womask_77 = &_out_womask_T_77; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_77 = out_rivalid_77 & out_rimask_77; // @[RegisterRouter.scala:87:24] wire _out_T_896 = out_f_rivalid_77; // @[RegisterRouter.scala:87:24] assign out_f_roready_77 = out_roready_77 & out_romask_77; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_52 = out_f_roready_77; // @[RegisterRouter.scala:87:24] wire _out_T_897 = out_f_roready_77; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_77 = out_wivalid_77 & out_wimask_77; // @[RegisterRouter.scala:87:24] wire _out_T_898 = out_f_wivalid_77; // @[RegisterRouter.scala:87:24] assign out_f_woready_77 = out_woready_77 & out_womask_77; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_52 = out_f_woready_77; // @[RegisterRouter.scala:87:24] wire _out_T_899 = out_f_woready_77; // @[RegisterRouter.scala:87:24] assign programBufferNxt_52 = out_f_woready_77 ? _out_T_895 : programBufferMem_52; // @[RegisterRouter.scala:87:24] wire _out_T_900 = ~out_rimask_77; // @[RegisterRouter.scala:87:24] wire _out_T_901 = ~out_wimask_77; // @[RegisterRouter.scala:87:24] wire _out_T_902 = ~out_romask_77; // @[RegisterRouter.scala:87:24] wire _out_T_903 = ~out_womask_77; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_905 = _out_T_904; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_58 = _out_T_905; // @[RegisterRouter.scala:87:24] wire out_rimask_78 = |_out_rimask_T_78; // @[RegisterRouter.scala:87:24] wire out_wimask_78 = &_out_wimask_T_78; // @[RegisterRouter.scala:87:24] wire out_romask_78 = |_out_romask_T_78; // @[RegisterRouter.scala:87:24] wire out_womask_78 = &_out_womask_T_78; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_78 = out_rivalid_78 & out_rimask_78; // @[RegisterRouter.scala:87:24] wire _out_T_907 = out_f_rivalid_78; // @[RegisterRouter.scala:87:24] assign out_f_roready_78 = out_roready_78 & out_romask_78; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_53 = out_f_roready_78; // @[RegisterRouter.scala:87:24] wire _out_T_908 = out_f_roready_78; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_78 = out_wivalid_78 & out_wimask_78; // @[RegisterRouter.scala:87:24] wire _out_T_909 = out_f_wivalid_78; // @[RegisterRouter.scala:87:24] assign out_f_woready_78 = out_woready_78 & out_womask_78; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_53 = out_f_woready_78; // @[RegisterRouter.scala:87:24] wire _out_T_910 = out_f_woready_78; // @[RegisterRouter.scala:87:24] assign programBufferNxt_53 = out_f_woready_78 ? _out_T_906 : programBufferMem_53; // @[RegisterRouter.scala:87:24] wire _out_T_911 = ~out_rimask_78; // @[RegisterRouter.scala:87:24] wire _out_T_912 = ~out_wimask_78; // @[RegisterRouter.scala:87:24] wire _out_T_913 = ~out_romask_78; // @[RegisterRouter.scala:87:24] wire _out_T_914 = ~out_womask_78; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_58 = {programBufferMem_53, _out_prepend_T_58}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_915 = out_prepend_58; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_916 = _out_T_915; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_59 = _out_T_916; // @[RegisterRouter.scala:87:24] wire out_rimask_79 = |_out_rimask_T_79; // @[RegisterRouter.scala:87:24] wire out_wimask_79 = &_out_wimask_T_79; // @[RegisterRouter.scala:87:24] wire out_romask_79 = |_out_romask_T_79; // @[RegisterRouter.scala:87:24] wire out_womask_79 = &_out_womask_T_79; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_79 = out_rivalid_79 & out_rimask_79; // @[RegisterRouter.scala:87:24] wire _out_T_918 = out_f_rivalid_79; // @[RegisterRouter.scala:87:24] assign out_f_roready_79 = out_roready_79 & out_romask_79; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_54 = out_f_roready_79; // @[RegisterRouter.scala:87:24] wire _out_T_919 = out_f_roready_79; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_79 = out_wivalid_79 & out_wimask_79; // @[RegisterRouter.scala:87:24] wire _out_T_920 = out_f_wivalid_79; // @[RegisterRouter.scala:87:24] assign out_f_woready_79 = out_woready_79 & out_womask_79; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_54 = out_f_woready_79; // @[RegisterRouter.scala:87:24] wire _out_T_921 = out_f_woready_79; // @[RegisterRouter.scala:87:24] assign programBufferNxt_54 = out_f_woready_79 ? _out_T_917 : programBufferMem_54; // @[RegisterRouter.scala:87:24] wire _out_T_922 = ~out_rimask_79; // @[RegisterRouter.scala:87:24] wire _out_T_923 = ~out_wimask_79; // @[RegisterRouter.scala:87:24] wire _out_T_924 = ~out_romask_79; // @[RegisterRouter.scala:87:24] wire _out_T_925 = ~out_womask_79; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_59 = {programBufferMem_54, _out_prepend_T_59}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_926 = out_prepend_59; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_927 = _out_T_926; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_60 = _out_T_927; // @[RegisterRouter.scala:87:24] wire out_rimask_80 = |_out_rimask_T_80; // @[RegisterRouter.scala:87:24] wire out_wimask_80 = &_out_wimask_T_80; // @[RegisterRouter.scala:87:24] wire out_romask_80 = |_out_romask_T_80; // @[RegisterRouter.scala:87:24] wire out_womask_80 = &_out_womask_T_80; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_80 = out_rivalid_80 & out_rimask_80; // @[RegisterRouter.scala:87:24] wire _out_T_929 = out_f_rivalid_80; // @[RegisterRouter.scala:87:24] assign out_f_roready_80 = out_roready_80 & out_romask_80; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_55 = out_f_roready_80; // @[RegisterRouter.scala:87:24] wire _out_T_930 = out_f_roready_80; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_80 = out_wivalid_80 & out_wimask_80; // @[RegisterRouter.scala:87:24] wire _out_T_931 = out_f_wivalid_80; // @[RegisterRouter.scala:87:24] assign out_f_woready_80 = out_woready_80 & out_womask_80; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_55 = out_f_woready_80; // @[RegisterRouter.scala:87:24] wire _out_T_932 = out_f_woready_80; // @[RegisterRouter.scala:87:24] assign programBufferNxt_55 = out_f_woready_80 ? _out_T_928 : programBufferMem_55; // @[RegisterRouter.scala:87:24] wire _out_T_933 = ~out_rimask_80; // @[RegisterRouter.scala:87:24] wire _out_T_934 = ~out_wimask_80; // @[RegisterRouter.scala:87:24] wire _out_T_935 = ~out_romask_80; // @[RegisterRouter.scala:87:24] wire _out_T_936 = ~out_womask_80; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_60 = {programBufferMem_55, _out_prepend_T_60}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_937 = out_prepend_60; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_938 = _out_T_937; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_45 = _out_T_938; // @[MuxLiteral.scala:49:48] wire out_rimask_81 = |_out_rimask_T_81; // @[RegisterRouter.scala:87:24] wire out_wimask_81 = &_out_wimask_T_81; // @[RegisterRouter.scala:87:24] wire out_romask_81 = |_out_romask_T_81; // @[RegisterRouter.scala:87:24] wire out_womask_81 = &_out_womask_T_81; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_81 = out_rivalid_81 & out_rimask_81; // @[RegisterRouter.scala:87:24] wire _out_T_940 = out_f_rivalid_81; // @[RegisterRouter.scala:87:24] wire out_f_roready_81 = out_roready_81 & out_romask_81; // @[RegisterRouter.scala:87:24] wire _out_T_941 = out_f_roready_81; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_81 = out_wivalid_81 & out_wimask_81; // @[RegisterRouter.scala:87:24] wire out_f_woready_81 = out_woready_81 & out_womask_81; // @[RegisterRouter.scala:87:24] wire _out_T_942 = ~out_rimask_81; // @[RegisterRouter.scala:87:24] wire _out_T_943 = ~out_wimask_81; // @[RegisterRouter.scala:87:24] wire _out_T_944 = ~out_romask_81; // @[RegisterRouter.scala:87:24] wire _out_T_945 = ~out_womask_81; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_947 = _out_T_946; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_0 = _out_T_947; // @[MuxLiteral.scala:49:48] wire [3:0] _out_rimask_T_82 = out_frontMask[3:0]; // @[RegisterRouter.scala:87:24] wire [3:0] _out_wimask_T_82 = out_frontMask[3:0]; // @[RegisterRouter.scala:87:24] wire [3:0] _out_rimask_T_109 = out_frontMask[3:0]; // @[RegisterRouter.scala:87:24] wire [3:0] _out_wimask_T_109 = out_frontMask[3:0]; // @[RegisterRouter.scala:87:24] wire out_rimask_82 = |_out_rimask_T_82; // @[RegisterRouter.scala:87:24] wire out_wimask_82 = &_out_wimask_T_82; // @[RegisterRouter.scala:87:24] wire [3:0] _out_romask_T_82 = out_backMask[3:0]; // @[RegisterRouter.scala:87:24] wire [3:0] _out_womask_T_82 = out_backMask[3:0]; // @[RegisterRouter.scala:87:24] wire [3:0] _out_romask_T_109 = out_backMask[3:0]; // @[RegisterRouter.scala:87:24] wire [3:0] _out_womask_T_109 = out_backMask[3:0]; // @[RegisterRouter.scala:87:24] wire out_romask_82 = |_out_romask_T_82; // @[RegisterRouter.scala:87:24] wire out_womask_82 = &_out_womask_T_82; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_82 = out_rivalid_82 & out_rimask_82; // @[RegisterRouter.scala:87:24] wire _out_T_949 = out_f_rivalid_82; // @[RegisterRouter.scala:87:24] wire out_f_roready_82 = out_roready_82 & out_romask_82; // @[RegisterRouter.scala:87:24] wire _out_T_950 = out_f_roready_82; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_82 = out_wivalid_82 & out_wimask_82; // @[RegisterRouter.scala:87:24] wire out_f_woready_82 = out_woready_82 & out_womask_82; // @[RegisterRouter.scala:87:24] wire [3:0] _out_T_948 = out_front_bits_data[3:0]; // @[RegisterRouter.scala:87:24] wire [3:0] _out_T_1207 = out_front_bits_data[3:0]; // @[RegisterRouter.scala:87:24] wire _out_T_951 = ~out_rimask_82; // @[RegisterRouter.scala:87:24] wire _out_T_952 = ~out_wimask_82; // @[RegisterRouter.scala:87:24] wire _out_T_953 = ~out_romask_82; // @[RegisterRouter.scala:87:24] wire _out_T_954 = ~out_womask_82; // @[RegisterRouter.scala:87:24] wire out_rimask_83 = _out_rimask_T_83; // @[RegisterRouter.scala:87:24] wire out_wimask_83 = _out_wimask_T_83; // @[RegisterRouter.scala:87:24] wire out_romask_83 = _out_romask_T_83; // @[RegisterRouter.scala:87:24] wire out_womask_83 = _out_womask_T_83; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_83 = out_rivalid_83 & out_rimask_83; // @[RegisterRouter.scala:87:24] wire _out_T_958 = out_f_rivalid_83; // @[RegisterRouter.scala:87:24] wire out_f_roready_83 = out_roready_83 & out_romask_83; // @[RegisterRouter.scala:87:24] wire _out_T_959 = out_f_roready_83; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_83 = out_wivalid_83 & out_wimask_83; // @[RegisterRouter.scala:87:24] wire out_f_woready_83 = out_woready_83 & out_womask_83; // @[RegisterRouter.scala:87:24] wire _out_T_960 = ~out_rimask_83; // @[RegisterRouter.scala:87:24] wire _out_T_961 = ~out_wimask_83; // @[RegisterRouter.scala:87:24] wire _out_T_962 = ~out_romask_83; // @[RegisterRouter.scala:87:24] wire _out_T_963 = ~out_womask_83; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_84 = out_frontMask[5]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_84 = out_frontMask[5]; // @[RegisterRouter.scala:87:24] wire out_rimask_84 = _out_rimask_T_84; // @[RegisterRouter.scala:87:24] wire out_wimask_84 = _out_wimask_T_84; // @[RegisterRouter.scala:87:24] wire _out_romask_T_84 = out_backMask[5]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_84 = out_backMask[5]; // @[RegisterRouter.scala:87:24] wire out_romask_84 = _out_romask_T_84; // @[RegisterRouter.scala:87:24] wire out_womask_84 = _out_womask_T_84; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_84 = out_rivalid_84 & out_rimask_84; // @[RegisterRouter.scala:87:24] wire _out_T_967 = out_f_rivalid_84; // @[RegisterRouter.scala:87:24] wire out_f_roready_84 = out_roready_84 & out_romask_84; // @[RegisterRouter.scala:87:24] wire _out_T_968 = out_f_roready_84; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_84 = out_wivalid_84 & out_wimask_84; // @[RegisterRouter.scala:87:24] wire out_f_woready_84 = out_woready_84 & out_womask_84; // @[RegisterRouter.scala:87:24] wire _out_T_966 = out_front_bits_data[5]; // @[RegisterRouter.scala:87:24] wire _out_T_969 = ~out_rimask_84; // @[RegisterRouter.scala:87:24] wire _out_T_970 = ~out_wimask_84; // @[RegisterRouter.scala:87:24] wire _out_T_971 = ~out_romask_84; // @[RegisterRouter.scala:87:24] wire _out_T_972 = ~out_womask_84; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_85 = out_frontMask[6]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_85 = out_frontMask[6]; // @[RegisterRouter.scala:87:24] wire out_rimask_85 = _out_rimask_T_85; // @[RegisterRouter.scala:87:24] wire out_wimask_85 = _out_wimask_T_85; // @[RegisterRouter.scala:87:24] wire _out_romask_T_85 = out_backMask[6]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_85 = out_backMask[6]; // @[RegisterRouter.scala:87:24] wire out_romask_85 = _out_romask_T_85; // @[RegisterRouter.scala:87:24] wire out_womask_85 = _out_womask_T_85; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_85 = out_rivalid_85 & out_rimask_85; // @[RegisterRouter.scala:87:24] wire _out_T_976 = out_f_rivalid_85; // @[RegisterRouter.scala:87:24] wire out_f_roready_85 = out_roready_85 & out_romask_85; // @[RegisterRouter.scala:87:24] wire _out_T_977 = out_f_roready_85; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_85 = out_wivalid_85 & out_wimask_85; // @[RegisterRouter.scala:87:24] wire out_f_woready_85 = out_woready_85 & out_womask_85; // @[RegisterRouter.scala:87:24] wire _out_T_975 = out_front_bits_data[6]; // @[RegisterRouter.scala:87:24] wire _out_T_978 = ~out_rimask_85; // @[RegisterRouter.scala:87:24] wire _out_T_979 = ~out_wimask_85; // @[RegisterRouter.scala:87:24] wire _out_T_980 = ~out_romask_85; // @[RegisterRouter.scala:87:24] wire _out_T_981 = ~out_womask_85; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_86 = out_frontMask[7]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_86 = out_frontMask[7]; // @[RegisterRouter.scala:87:24] wire out_rimask_86 = _out_rimask_T_86; // @[RegisterRouter.scala:87:24] wire out_wimask_86 = _out_wimask_T_86; // @[RegisterRouter.scala:87:24] wire _out_romask_T_86 = out_backMask[7]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_86 = out_backMask[7]; // @[RegisterRouter.scala:87:24] wire out_romask_86 = _out_romask_T_86; // @[RegisterRouter.scala:87:24] wire out_womask_86 = _out_womask_T_86; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_86 = out_rivalid_86 & out_rimask_86; // @[RegisterRouter.scala:87:24] wire _out_T_985 = out_f_rivalid_86; // @[RegisterRouter.scala:87:24] wire out_f_roready_86 = out_roready_86 & out_romask_86; // @[RegisterRouter.scala:87:24] wire _out_T_986 = out_f_roready_86; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_86 = out_wivalid_86 & out_wimask_86; // @[RegisterRouter.scala:87:24] wire out_f_woready_86 = out_woready_86 & out_womask_86; // @[RegisterRouter.scala:87:24] wire _out_T_984 = out_front_bits_data[7]; // @[RegisterRouter.scala:87:24] wire _out_T_987 = ~out_rimask_86; // @[RegisterRouter.scala:87:24] wire _out_T_988 = ~out_wimask_86; // @[RegisterRouter.scala:87:24] wire _out_T_989 = ~out_romask_86; // @[RegisterRouter.scala:87:24] wire _out_T_990 = ~out_womask_86; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_87 = out_frontMask[8]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_87 = out_frontMask[8]; // @[RegisterRouter.scala:87:24] wire out_rimask_87 = _out_rimask_T_87; // @[RegisterRouter.scala:87:24] wire out_wimask_87 = _out_wimask_T_87; // @[RegisterRouter.scala:87:24] wire _out_romask_T_87 = out_backMask[8]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_87 = out_backMask[8]; // @[RegisterRouter.scala:87:24] wire out_romask_87 = _out_romask_T_87; // @[RegisterRouter.scala:87:24] wire out_womask_87 = _out_womask_T_87; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_87 = out_rivalid_87 & out_rimask_87; // @[RegisterRouter.scala:87:24] wire _out_T_994 = out_f_rivalid_87; // @[RegisterRouter.scala:87:24] wire out_f_roready_87 = out_roready_87 & out_romask_87; // @[RegisterRouter.scala:87:24] wire _out_T_995 = out_f_roready_87; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_87 = out_wivalid_87 & out_wimask_87; // @[RegisterRouter.scala:87:24] wire out_f_woready_87 = out_woready_87 & out_womask_87; // @[RegisterRouter.scala:87:24] wire _out_T_993 = out_front_bits_data[8]; // @[RegisterRouter.scala:87:24] wire _out_T_996 = ~out_rimask_87; // @[RegisterRouter.scala:87:24] wire _out_T_997 = ~out_wimask_87; // @[RegisterRouter.scala:87:24] wire _out_T_998 = ~out_romask_87; // @[RegisterRouter.scala:87:24] wire _out_T_999 = ~out_womask_87; // @[RegisterRouter.scala:87:24] wire [8:0] out_prepend_65 = {DMSTATUSRdData_anyhalted, 8'hA2}; // @[RegisterRouter.scala:87:24] wire [8:0] _out_T_1000 = out_prepend_65; // @[RegisterRouter.scala:87:24] wire [8:0] _out_T_1001 = _out_T_1000; // @[RegisterRouter.scala:87:24] wire [8:0] _out_prepend_T_66 = _out_T_1001; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_88 = out_frontMask[9]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_88 = out_frontMask[9]; // @[RegisterRouter.scala:87:24] wire out_rimask_88 = _out_rimask_T_88; // @[RegisterRouter.scala:87:24] wire out_wimask_88 = _out_wimask_T_88; // @[RegisterRouter.scala:87:24] wire _out_romask_T_88 = out_backMask[9]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_88 = out_backMask[9]; // @[RegisterRouter.scala:87:24] wire out_romask_88 = _out_romask_T_88; // @[RegisterRouter.scala:87:24] wire out_womask_88 = _out_womask_T_88; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_88 = out_rivalid_88 & out_rimask_88; // @[RegisterRouter.scala:87:24] wire _out_T_1003 = out_f_rivalid_88; // @[RegisterRouter.scala:87:24] wire out_f_roready_88 = out_roready_88 & out_romask_88; // @[RegisterRouter.scala:87:24] wire _out_T_1004 = out_f_roready_88; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_88 = out_wivalid_88 & out_wimask_88; // @[RegisterRouter.scala:87:24] wire out_f_woready_88 = out_woready_88 & out_womask_88; // @[RegisterRouter.scala:87:24] wire _out_T_1002 = out_front_bits_data[9]; // @[RegisterRouter.scala:87:24] wire _out_T_1005 = ~out_rimask_88; // @[RegisterRouter.scala:87:24] wire _out_T_1006 = ~out_wimask_88; // @[RegisterRouter.scala:87:24] wire _out_T_1007 = ~out_romask_88; // @[RegisterRouter.scala:87:24] wire _out_T_1008 = ~out_womask_88; // @[RegisterRouter.scala:87:24] wire [9:0] out_prepend_66 = {DMSTATUSRdData_allhalted, _out_prepend_T_66}; // @[RegisterRouter.scala:87:24] wire [9:0] _out_T_1009 = out_prepend_66; // @[RegisterRouter.scala:87:24] wire [9:0] _out_T_1010 = _out_T_1009; // @[RegisterRouter.scala:87:24] wire [9:0] _out_prepend_T_67 = _out_T_1010; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_89 = out_frontMask[10]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_89 = out_frontMask[10]; // @[RegisterRouter.scala:87:24] wire out_rimask_89 = _out_rimask_T_89; // @[RegisterRouter.scala:87:24] wire out_wimask_89 = _out_wimask_T_89; // @[RegisterRouter.scala:87:24] wire _out_romask_T_89 = out_backMask[10]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_89 = out_backMask[10]; // @[RegisterRouter.scala:87:24] wire out_romask_89 = _out_romask_T_89; // @[RegisterRouter.scala:87:24] wire out_womask_89 = _out_womask_T_89; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_89 = out_rivalid_89 & out_rimask_89; // @[RegisterRouter.scala:87:24] wire _out_T_1012 = out_f_rivalid_89; // @[RegisterRouter.scala:87:24] wire out_f_roready_89 = out_roready_89 & out_romask_89; // @[RegisterRouter.scala:87:24] wire _out_T_1013 = out_f_roready_89; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_89 = out_wivalid_89 & out_wimask_89; // @[RegisterRouter.scala:87:24] wire out_f_woready_89 = out_woready_89 & out_womask_89; // @[RegisterRouter.scala:87:24] wire _out_T_1011 = out_front_bits_data[10]; // @[RegisterRouter.scala:87:24] wire _out_T_1014 = ~out_rimask_89; // @[RegisterRouter.scala:87:24] wire _out_T_1015 = ~out_wimask_89; // @[RegisterRouter.scala:87:24] wire _out_T_1016 = ~out_romask_89; // @[RegisterRouter.scala:87:24] wire _out_T_1017 = ~out_womask_89; // @[RegisterRouter.scala:87:24] wire [10:0] out_prepend_67 = {DMSTATUSRdData_anyrunning, _out_prepend_T_67}; // @[RegisterRouter.scala:87:24] wire [10:0] _out_T_1018 = out_prepend_67; // @[RegisterRouter.scala:87:24] wire [10:0] _out_T_1019 = _out_T_1018; // @[RegisterRouter.scala:87:24] wire [10:0] _out_prepend_T_68 = _out_T_1019; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_90 = out_frontMask[11]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_90 = out_frontMask[11]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_112 = out_frontMask[11]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_112 = out_frontMask[11]; // @[RegisterRouter.scala:87:24] wire out_rimask_90 = _out_rimask_T_90; // @[RegisterRouter.scala:87:24] wire out_wimask_90 = _out_wimask_T_90; // @[RegisterRouter.scala:87:24] wire _out_romask_T_90 = out_backMask[11]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_90 = out_backMask[11]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_112 = out_backMask[11]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_112 = out_backMask[11]; // @[RegisterRouter.scala:87:24] wire out_romask_90 = _out_romask_T_90; // @[RegisterRouter.scala:87:24] wire out_womask_90 = _out_womask_T_90; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_90 = out_rivalid_90 & out_rimask_90; // @[RegisterRouter.scala:87:24] wire _out_T_1021 = out_f_rivalid_90; // @[RegisterRouter.scala:87:24] wire out_f_roready_90 = out_roready_90 & out_romask_90; // @[RegisterRouter.scala:87:24] wire _out_T_1022 = out_f_roready_90; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_90 = out_wivalid_90 & out_wimask_90; // @[RegisterRouter.scala:87:24] wire out_f_woready_90 = out_woready_90 & out_womask_90; // @[RegisterRouter.scala:87:24] wire _out_T_1020 = out_front_bits_data[11]; // @[RegisterRouter.scala:87:24] wire _out_T_1236 = out_front_bits_data[11]; // @[RegisterRouter.scala:87:24] wire _out_T_1023 = ~out_rimask_90; // @[RegisterRouter.scala:87:24] wire _out_T_1024 = ~out_wimask_90; // @[RegisterRouter.scala:87:24] wire _out_T_1025 = ~out_romask_90; // @[RegisterRouter.scala:87:24] wire _out_T_1026 = ~out_womask_90; // @[RegisterRouter.scala:87:24] wire [11:0] out_prepend_68 = {DMSTATUSRdData_allrunning, _out_prepend_T_68}; // @[RegisterRouter.scala:87:24] wire [11:0] _out_T_1027 = out_prepend_68; // @[RegisterRouter.scala:87:24] wire [11:0] _out_T_1028 = _out_T_1027; // @[RegisterRouter.scala:87:24] wire [11:0] _out_prepend_T_69 = _out_T_1028; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_91 = out_frontMask[12]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_91 = out_frontMask[12]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_113 = out_frontMask[12]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_113 = out_frontMask[12]; // @[RegisterRouter.scala:87:24] wire out_rimask_91 = _out_rimask_T_91; // @[RegisterRouter.scala:87:24] wire out_wimask_91 = _out_wimask_T_91; // @[RegisterRouter.scala:87:24] wire _out_romask_T_91 = out_backMask[12]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_91 = out_backMask[12]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_113 = out_backMask[12]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_113 = out_backMask[12]; // @[RegisterRouter.scala:87:24] wire out_romask_91 = _out_romask_T_91; // @[RegisterRouter.scala:87:24] wire out_womask_91 = _out_womask_T_91; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_91 = out_rivalid_91 & out_rimask_91; // @[RegisterRouter.scala:87:24] wire _out_T_1030 = out_f_rivalid_91; // @[RegisterRouter.scala:87:24] wire out_f_roready_91 = out_roready_91 & out_romask_91; // @[RegisterRouter.scala:87:24] wire _out_T_1031 = out_f_roready_91; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_91 = out_wivalid_91 & out_wimask_91; // @[RegisterRouter.scala:87:24] wire out_f_woready_91 = out_woready_91 & out_womask_91; // @[RegisterRouter.scala:87:24] wire _out_T_1029 = out_front_bits_data[12]; // @[RegisterRouter.scala:87:24] wire _out_T_1245 = out_front_bits_data[12]; // @[RegisterRouter.scala:87:24] wire _out_T_1032 = ~out_rimask_91; // @[RegisterRouter.scala:87:24] wire _out_T_1033 = ~out_wimask_91; // @[RegisterRouter.scala:87:24] wire _out_T_1034 = ~out_romask_91; // @[RegisterRouter.scala:87:24] wire _out_T_1035 = ~out_womask_91; // @[RegisterRouter.scala:87:24] wire [12:0] out_prepend_69 = {1'h0, _out_prepend_T_69}; // @[RegisterRouter.scala:87:24] wire [12:0] _out_T_1036 = out_prepend_69; // @[RegisterRouter.scala:87:24] wire [12:0] _out_T_1037 = _out_T_1036; // @[RegisterRouter.scala:87:24] wire [12:0] _out_prepend_T_70 = _out_T_1037; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_92 = out_frontMask[13]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_92 = out_frontMask[13]; // @[RegisterRouter.scala:87:24] wire out_rimask_92 = _out_rimask_T_92; // @[RegisterRouter.scala:87:24] wire out_wimask_92 = _out_wimask_T_92; // @[RegisterRouter.scala:87:24] wire _out_romask_T_92 = out_backMask[13]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_92 = out_backMask[13]; // @[RegisterRouter.scala:87:24] wire out_romask_92 = _out_romask_T_92; // @[RegisterRouter.scala:87:24] wire out_womask_92 = _out_womask_T_92; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_92 = out_rivalid_92 & out_rimask_92; // @[RegisterRouter.scala:87:24] wire _out_T_1039 = out_f_rivalid_92; // @[RegisterRouter.scala:87:24] wire out_f_roready_92 = out_roready_92 & out_romask_92; // @[RegisterRouter.scala:87:24] wire _out_T_1040 = out_f_roready_92; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_92 = out_wivalid_92 & out_wimask_92; // @[RegisterRouter.scala:87:24] wire out_f_woready_92 = out_woready_92 & out_womask_92; // @[RegisterRouter.scala:87:24] wire _out_T_1038 = out_front_bits_data[13]; // @[RegisterRouter.scala:87:24] wire _out_T_1041 = ~out_rimask_92; // @[RegisterRouter.scala:87:24] wire _out_T_1042 = ~out_wimask_92; // @[RegisterRouter.scala:87:24] wire _out_T_1043 = ~out_romask_92; // @[RegisterRouter.scala:87:24] wire _out_T_1044 = ~out_womask_92; // @[RegisterRouter.scala:87:24] wire [13:0] out_prepend_70 = {DMSTATUSRdData_allunavail, _out_prepend_T_70}; // @[RegisterRouter.scala:87:24] wire [13:0] _out_T_1045 = out_prepend_70; // @[RegisterRouter.scala:87:24] wire [13:0] _out_T_1046 = _out_T_1045; // @[RegisterRouter.scala:87:24] wire [13:0] _out_prepend_T_71 = _out_T_1046; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_93 = out_frontMask[14]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_93 = out_frontMask[14]; // @[RegisterRouter.scala:87:24] wire out_rimask_93 = _out_rimask_T_93; // @[RegisterRouter.scala:87:24] wire out_wimask_93 = _out_wimask_T_93; // @[RegisterRouter.scala:87:24] wire _out_romask_T_93 = out_backMask[14]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_93 = out_backMask[14]; // @[RegisterRouter.scala:87:24] wire out_romask_93 = _out_romask_T_93; // @[RegisterRouter.scala:87:24] wire out_womask_93 = _out_womask_T_93; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_93 = out_rivalid_93 & out_rimask_93; // @[RegisterRouter.scala:87:24] wire _out_T_1048 = out_f_rivalid_93; // @[RegisterRouter.scala:87:24] wire out_f_roready_93 = out_roready_93 & out_romask_93; // @[RegisterRouter.scala:87:24] wire _out_T_1049 = out_f_roready_93; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_93 = out_wivalid_93 & out_wimask_93; // @[RegisterRouter.scala:87:24] wire out_f_woready_93 = out_woready_93 & out_womask_93; // @[RegisterRouter.scala:87:24] wire _out_T_1047 = out_front_bits_data[14]; // @[RegisterRouter.scala:87:24] wire _out_T_1050 = ~out_rimask_93; // @[RegisterRouter.scala:87:24] wire _out_T_1051 = ~out_wimask_93; // @[RegisterRouter.scala:87:24] wire _out_T_1052 = ~out_romask_93; // @[RegisterRouter.scala:87:24] wire _out_T_1053 = ~out_womask_93; // @[RegisterRouter.scala:87:24] wire [14:0] out_prepend_71 = {DMSTATUSRdData_anynonexistent, _out_prepend_T_71}; // @[RegisterRouter.scala:87:24] wire [14:0] _out_T_1054 = out_prepend_71; // @[RegisterRouter.scala:87:24] wire [14:0] _out_T_1055 = _out_T_1054; // @[RegisterRouter.scala:87:24] wire [14:0] _out_prepend_T_72 = _out_T_1055; // @[RegisterRouter.scala:87:24] wire out_rimask_94 = _out_rimask_T_94; // @[RegisterRouter.scala:87:24] wire out_wimask_94 = _out_wimask_T_94; // @[RegisterRouter.scala:87:24] wire out_romask_94 = _out_romask_T_94; // @[RegisterRouter.scala:87:24] wire out_womask_94 = _out_womask_T_94; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_94 = out_rivalid_94 & out_rimask_94; // @[RegisterRouter.scala:87:24] wire _out_T_1057 = out_f_rivalid_94; // @[RegisterRouter.scala:87:24] wire out_f_roready_94 = out_roready_94 & out_romask_94; // @[RegisterRouter.scala:87:24] wire _out_T_1058 = out_f_roready_94; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_94 = out_wivalid_94 & out_wimask_94; // @[RegisterRouter.scala:87:24] wire out_f_woready_94 = out_woready_94 & out_womask_94; // @[RegisterRouter.scala:87:24] wire _out_T_1059 = ~out_rimask_94; // @[RegisterRouter.scala:87:24] wire _out_T_1060 = ~out_wimask_94; // @[RegisterRouter.scala:87:24] wire _out_T_1061 = ~out_romask_94; // @[RegisterRouter.scala:87:24] wire _out_T_1062 = ~out_womask_94; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_72 = {DMSTATUSRdData_allnonexistent, _out_prepend_T_72}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1063 = out_prepend_72; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1064 = _out_T_1063; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_73 = _out_T_1064; // @[RegisterRouter.scala:87:24] wire out_rimask_95 = _out_rimask_T_95; // @[RegisterRouter.scala:87:24] wire out_wimask_95 = _out_wimask_T_95; // @[RegisterRouter.scala:87:24] wire out_romask_95 = _out_romask_T_95; // @[RegisterRouter.scala:87:24] wire out_womask_95 = _out_womask_T_95; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_95 = out_rivalid_95 & out_rimask_95; // @[RegisterRouter.scala:87:24] wire _out_T_1066 = out_f_rivalid_95; // @[RegisterRouter.scala:87:24] wire out_f_roready_95 = out_roready_95 & out_romask_95; // @[RegisterRouter.scala:87:24] wire _out_T_1067 = out_f_roready_95; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_95 = out_wivalid_95 & out_wimask_95; // @[RegisterRouter.scala:87:24] wire out_f_woready_95 = out_woready_95 & out_womask_95; // @[RegisterRouter.scala:87:24] wire _out_T_1068 = ~out_rimask_95; // @[RegisterRouter.scala:87:24] wire _out_T_1069 = ~out_wimask_95; // @[RegisterRouter.scala:87:24] wire _out_T_1070 = ~out_romask_95; // @[RegisterRouter.scala:87:24] wire _out_T_1071 = ~out_womask_95; // @[RegisterRouter.scala:87:24] wire [16:0] out_prepend_73 = {DMSTATUSRdData_anyresumeack, _out_prepend_T_73}; // @[RegisterRouter.scala:87:24] wire [16:0] _out_T_1072 = out_prepend_73; // @[RegisterRouter.scala:87:24] wire [16:0] _out_T_1073 = _out_T_1072; // @[RegisterRouter.scala:87:24] wire [16:0] _out_prepend_T_74 = _out_T_1073; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_96 = out_frontMask[17]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_96 = out_frontMask[17]; // @[RegisterRouter.scala:87:24] wire out_rimask_96 = _out_rimask_T_96; // @[RegisterRouter.scala:87:24] wire out_wimask_96 = _out_wimask_T_96; // @[RegisterRouter.scala:87:24] wire _out_romask_T_96 = out_backMask[17]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_96 = out_backMask[17]; // @[RegisterRouter.scala:87:24] wire out_romask_96 = _out_romask_T_96; // @[RegisterRouter.scala:87:24] wire out_womask_96 = _out_womask_T_96; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_96 = out_rivalid_96 & out_rimask_96; // @[RegisterRouter.scala:87:24] wire _out_T_1075 = out_f_rivalid_96; // @[RegisterRouter.scala:87:24] wire out_f_roready_96 = out_roready_96 & out_romask_96; // @[RegisterRouter.scala:87:24] wire _out_T_1076 = out_f_roready_96; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_96 = out_wivalid_96 & out_wimask_96; // @[RegisterRouter.scala:87:24] wire out_f_woready_96 = out_woready_96 & out_womask_96; // @[RegisterRouter.scala:87:24] wire _out_T_1074 = out_front_bits_data[17]; // @[RegisterRouter.scala:87:24] wire _out_T_1077 = ~out_rimask_96; // @[RegisterRouter.scala:87:24] wire _out_T_1078 = ~out_wimask_96; // @[RegisterRouter.scala:87:24] wire _out_T_1079 = ~out_romask_96; // @[RegisterRouter.scala:87:24] wire _out_T_1080 = ~out_womask_96; // @[RegisterRouter.scala:87:24] wire [17:0] out_prepend_74 = {DMSTATUSRdData_allresumeack, _out_prepend_T_74}; // @[RegisterRouter.scala:87:24] wire [17:0] _out_T_1081 = out_prepend_74; // @[RegisterRouter.scala:87:24] wire [17:0] _out_T_1082 = _out_T_1081; // @[RegisterRouter.scala:87:24] wire [17:0] _out_prepend_T_75 = _out_T_1082; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_97 = out_frontMask[18]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_97 = out_frontMask[18]; // @[RegisterRouter.scala:87:24] wire out_rimask_97 = _out_rimask_T_97; // @[RegisterRouter.scala:87:24] wire out_wimask_97 = _out_wimask_T_97; // @[RegisterRouter.scala:87:24] wire _out_romask_T_97 = out_backMask[18]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_97 = out_backMask[18]; // @[RegisterRouter.scala:87:24] wire out_romask_97 = _out_romask_T_97; // @[RegisterRouter.scala:87:24] wire out_womask_97 = _out_womask_T_97; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_97 = out_rivalid_97 & out_rimask_97; // @[RegisterRouter.scala:87:24] wire _out_T_1084 = out_f_rivalid_97; // @[RegisterRouter.scala:87:24] wire out_f_roready_97 = out_roready_97 & out_romask_97; // @[RegisterRouter.scala:87:24] wire _out_T_1085 = out_f_roready_97; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_97 = out_wivalid_97 & out_wimask_97; // @[RegisterRouter.scala:87:24] wire out_f_woready_97 = out_woready_97 & out_womask_97; // @[RegisterRouter.scala:87:24] wire _out_T_1083 = out_front_bits_data[18]; // @[RegisterRouter.scala:87:24] wire _out_T_1086 = ~out_rimask_97; // @[RegisterRouter.scala:87:24] wire _out_T_1087 = ~out_wimask_97; // @[RegisterRouter.scala:87:24] wire _out_T_1088 = ~out_romask_97; // @[RegisterRouter.scala:87:24] wire _out_T_1089 = ~out_womask_97; // @[RegisterRouter.scala:87:24] wire [18:0] out_prepend_75 = {DMSTATUSRdData_anyhavereset, _out_prepend_T_75}; // @[RegisterRouter.scala:87:24] wire [18:0] _out_T_1090 = out_prepend_75; // @[RegisterRouter.scala:87:24] wire [18:0] _out_T_1091 = _out_T_1090; // @[RegisterRouter.scala:87:24] wire [18:0] _out_prepend_T_76 = _out_T_1091; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_98 = out_frontMask[19]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_98 = out_frontMask[19]; // @[RegisterRouter.scala:87:24] wire out_rimask_98 = _out_rimask_T_98; // @[RegisterRouter.scala:87:24] wire out_wimask_98 = _out_wimask_T_98; // @[RegisterRouter.scala:87:24] wire _out_romask_T_98 = out_backMask[19]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_98 = out_backMask[19]; // @[RegisterRouter.scala:87:24] wire out_romask_98 = _out_romask_T_98; // @[RegisterRouter.scala:87:24] wire out_womask_98 = _out_womask_T_98; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_98 = out_rivalid_98 & out_rimask_98; // @[RegisterRouter.scala:87:24] wire _out_T_1093 = out_f_rivalid_98; // @[RegisterRouter.scala:87:24] wire out_f_roready_98 = out_roready_98 & out_romask_98; // @[RegisterRouter.scala:87:24] wire _out_T_1094 = out_f_roready_98; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_98 = out_wivalid_98 & out_wimask_98; // @[RegisterRouter.scala:87:24] wire out_f_woready_98 = out_woready_98 & out_womask_98; // @[RegisterRouter.scala:87:24] wire _out_T_1092 = out_front_bits_data[19]; // @[RegisterRouter.scala:87:24] wire _out_T_1095 = ~out_rimask_98; // @[RegisterRouter.scala:87:24] wire _out_T_1096 = ~out_wimask_98; // @[RegisterRouter.scala:87:24] wire _out_T_1097 = ~out_romask_98; // @[RegisterRouter.scala:87:24] wire _out_T_1098 = ~out_womask_98; // @[RegisterRouter.scala:87:24] wire [19:0] out_prepend_76 = {DMSTATUSRdData_allhavereset, _out_prepend_T_76}; // @[RegisterRouter.scala:87:24] wire [19:0] _out_T_1099 = out_prepend_76; // @[RegisterRouter.scala:87:24] wire [19:0] _out_T_1100 = _out_T_1099; // @[RegisterRouter.scala:87:24] wire [19:0] _out_prepend_T_77 = _out_T_1100; // @[RegisterRouter.scala:87:24] wire [1:0] _out_rimask_T_99 = out_frontMask[21:20]; // @[RegisterRouter.scala:87:24] wire [1:0] _out_wimask_T_99 = out_frontMask[21:20]; // @[RegisterRouter.scala:87:24] wire out_rimask_99 = |_out_rimask_T_99; // @[RegisterRouter.scala:87:24] wire out_wimask_99 = &_out_wimask_T_99; // @[RegisterRouter.scala:87:24] wire [1:0] _out_romask_T_99 = out_backMask[21:20]; // @[RegisterRouter.scala:87:24] wire [1:0] _out_womask_T_99 = out_backMask[21:20]; // @[RegisterRouter.scala:87:24] wire out_romask_99 = |_out_romask_T_99; // @[RegisterRouter.scala:87:24] wire out_womask_99 = &_out_womask_T_99; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_99 = out_rivalid_99 & out_rimask_99; // @[RegisterRouter.scala:87:24] wire _out_T_1102 = out_f_rivalid_99; // @[RegisterRouter.scala:87:24] wire out_f_roready_99 = out_roready_99 & out_romask_99; // @[RegisterRouter.scala:87:24] wire _out_T_1103 = out_f_roready_99; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_99 = out_wivalid_99 & out_wimask_99; // @[RegisterRouter.scala:87:24] wire out_f_woready_99 = out_woready_99 & out_womask_99; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_1101 = out_front_bits_data[21:20]; // @[RegisterRouter.scala:87:24] wire _out_T_1104 = ~out_rimask_99; // @[RegisterRouter.scala:87:24] wire _out_T_1105 = ~out_wimask_99; // @[RegisterRouter.scala:87:24] wire _out_T_1106 = ~out_romask_99; // @[RegisterRouter.scala:87:24] wire _out_T_1107 = ~out_womask_99; // @[RegisterRouter.scala:87:24] wire [20:0] out_prepend_77 = {1'h0, _out_prepend_T_77}; // @[RegisterRouter.scala:87:24] wire [21:0] _out_T_1108 = {1'h0, out_prepend_77}; // @[RegisterRouter.scala:87:24] wire [21:0] _out_T_1109 = _out_T_1108; // @[RegisterRouter.scala:87:24] wire [21:0] _out_prepend_T_78 = _out_T_1109; // @[RegisterRouter.scala:87:24] wire out_rimask_100 = _out_rimask_T_100; // @[RegisterRouter.scala:87:24] wire out_wimask_100 = _out_wimask_T_100; // @[RegisterRouter.scala:87:24] wire out_romask_100 = _out_romask_T_100; // @[RegisterRouter.scala:87:24] wire out_womask_100 = _out_womask_T_100; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_100 = out_rivalid_100 & out_rimask_100; // @[RegisterRouter.scala:87:24] wire _out_T_1111 = out_f_rivalid_100; // @[RegisterRouter.scala:87:24] wire out_f_roready_100 = out_roready_100 & out_romask_100; // @[RegisterRouter.scala:87:24] wire _out_T_1112 = out_f_roready_100; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_100 = out_wivalid_100 & out_wimask_100; // @[RegisterRouter.scala:87:24] wire out_f_woready_100 = out_woready_100 & out_womask_100; // @[RegisterRouter.scala:87:24] wire _out_T_1113 = ~out_rimask_100; // @[RegisterRouter.scala:87:24] wire _out_T_1114 = ~out_wimask_100; // @[RegisterRouter.scala:87:24] wire _out_T_1115 = ~out_romask_100; // @[RegisterRouter.scala:87:24] wire _out_T_1116 = ~out_womask_100; // @[RegisterRouter.scala:87:24] wire [22:0] out_prepend_78 = {1'h0, _out_prepend_T_78}; // @[RegisterRouter.scala:87:24] wire [22:0] _out_T_1117 = out_prepend_78; // @[RegisterRouter.scala:87:24] wire [22:0] _out_T_1118 = _out_T_1117; // @[RegisterRouter.scala:87:24] wire out_rimask_101 = |_out_rimask_T_101; // @[RegisterRouter.scala:87:24] wire out_wimask_101 = &_out_wimask_T_101; // @[RegisterRouter.scala:87:24] wire out_romask_101 = |_out_romask_T_101; // @[RegisterRouter.scala:87:24] wire out_womask_101 = &_out_womask_T_101; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_101 = out_rivalid_101 & out_rimask_101; // @[RegisterRouter.scala:87:24] wire _out_T_1120 = out_f_rivalid_101; // @[RegisterRouter.scala:87:24] assign out_f_roready_101 = out_roready_101 & out_romask_101; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_0 = out_f_roready_101; // @[RegisterRouter.scala:87:24] wire _out_T_1121 = out_f_roready_101; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_101 = out_wivalid_101 & out_wimask_101; // @[RegisterRouter.scala:87:24] wire _out_T_1122 = out_f_wivalid_101; // @[RegisterRouter.scala:87:24] assign out_f_woready_101 = out_woready_101 & out_womask_101; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_0 = out_f_woready_101; // @[RegisterRouter.scala:87:24] wire _out_T_1123 = out_f_woready_101; // @[RegisterRouter.scala:87:24] assign programBufferNxt_0 = out_f_woready_101 ? _out_T_1119 : programBufferMem_0; // @[RegisterRouter.scala:87:24] wire _out_T_1124 = ~out_rimask_101; // @[RegisterRouter.scala:87:24] wire _out_T_1125 = ~out_wimask_101; // @[RegisterRouter.scala:87:24] wire _out_T_1126 = ~out_romask_101; // @[RegisterRouter.scala:87:24] wire _out_T_1127 = ~out_womask_101; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1129 = _out_T_1128; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_79 = _out_T_1129; // @[RegisterRouter.scala:87:24] wire out_rimask_102 = |_out_rimask_T_102; // @[RegisterRouter.scala:87:24] wire out_wimask_102 = &_out_wimask_T_102; // @[RegisterRouter.scala:87:24] wire out_romask_102 = |_out_romask_T_102; // @[RegisterRouter.scala:87:24] wire out_womask_102 = &_out_womask_T_102; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_102 = out_rivalid_102 & out_rimask_102; // @[RegisterRouter.scala:87:24] wire _out_T_1131 = out_f_rivalid_102; // @[RegisterRouter.scala:87:24] assign out_f_roready_102 = out_roready_102 & out_romask_102; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_1 = out_f_roready_102; // @[RegisterRouter.scala:87:24] wire _out_T_1132 = out_f_roready_102; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_102 = out_wivalid_102 & out_wimask_102; // @[RegisterRouter.scala:87:24] wire _out_T_1133 = out_f_wivalid_102; // @[RegisterRouter.scala:87:24] assign out_f_woready_102 = out_woready_102 & out_womask_102; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_1 = out_f_woready_102; // @[RegisterRouter.scala:87:24] wire _out_T_1134 = out_f_woready_102; // @[RegisterRouter.scala:87:24] assign programBufferNxt_1 = out_f_woready_102 ? _out_T_1130 : programBufferMem_1; // @[RegisterRouter.scala:87:24] wire _out_T_1135 = ~out_rimask_102; // @[RegisterRouter.scala:87:24] wire _out_T_1136 = ~out_wimask_102; // @[RegisterRouter.scala:87:24] wire _out_T_1137 = ~out_romask_102; // @[RegisterRouter.scala:87:24] wire _out_T_1138 = ~out_womask_102; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_79 = {programBufferMem_1, _out_prepend_T_79}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1139 = out_prepend_79; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1140 = _out_T_1139; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_80 = _out_T_1140; // @[RegisterRouter.scala:87:24] wire out_rimask_103 = |_out_rimask_T_103; // @[RegisterRouter.scala:87:24] wire out_wimask_103 = &_out_wimask_T_103; // @[RegisterRouter.scala:87:24] wire out_romask_103 = |_out_romask_T_103; // @[RegisterRouter.scala:87:24] wire out_womask_103 = &_out_womask_T_103; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_103 = out_rivalid_103 & out_rimask_103; // @[RegisterRouter.scala:87:24] wire _out_T_1142 = out_f_rivalid_103; // @[RegisterRouter.scala:87:24] assign out_f_roready_103 = out_roready_103 & out_romask_103; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_2 = out_f_roready_103; // @[RegisterRouter.scala:87:24] wire _out_T_1143 = out_f_roready_103; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_103 = out_wivalid_103 & out_wimask_103; // @[RegisterRouter.scala:87:24] wire _out_T_1144 = out_f_wivalid_103; // @[RegisterRouter.scala:87:24] assign out_f_woready_103 = out_woready_103 & out_womask_103; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_2 = out_f_woready_103; // @[RegisterRouter.scala:87:24] wire _out_T_1145 = out_f_woready_103; // @[RegisterRouter.scala:87:24] assign programBufferNxt_2 = out_f_woready_103 ? _out_T_1141 : programBufferMem_2; // @[RegisterRouter.scala:87:24] wire _out_T_1146 = ~out_rimask_103; // @[RegisterRouter.scala:87:24] wire _out_T_1147 = ~out_wimask_103; // @[RegisterRouter.scala:87:24] wire _out_T_1148 = ~out_romask_103; // @[RegisterRouter.scala:87:24] wire _out_T_1149 = ~out_womask_103; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_80 = {programBufferMem_2, _out_prepend_T_80}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1150 = out_prepend_80; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1151 = _out_T_1150; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_81 = _out_T_1151; // @[RegisterRouter.scala:87:24] wire out_rimask_104 = |_out_rimask_T_104; // @[RegisterRouter.scala:87:24] wire out_wimask_104 = &_out_wimask_T_104; // @[RegisterRouter.scala:87:24] wire out_romask_104 = |_out_romask_T_104; // @[RegisterRouter.scala:87:24] wire out_womask_104 = &_out_womask_T_104; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_104 = out_rivalid_104 & out_rimask_104; // @[RegisterRouter.scala:87:24] wire _out_T_1153 = out_f_rivalid_104; // @[RegisterRouter.scala:87:24] assign out_f_roready_104 = out_roready_104 & out_romask_104; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_3 = out_f_roready_104; // @[RegisterRouter.scala:87:24] wire _out_T_1154 = out_f_roready_104; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_104 = out_wivalid_104 & out_wimask_104; // @[RegisterRouter.scala:87:24] wire _out_T_1155 = out_f_wivalid_104; // @[RegisterRouter.scala:87:24] assign out_f_woready_104 = out_woready_104 & out_womask_104; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_3 = out_f_woready_104; // @[RegisterRouter.scala:87:24] wire _out_T_1156 = out_f_woready_104; // @[RegisterRouter.scala:87:24] assign programBufferNxt_3 = out_f_woready_104 ? _out_T_1152 : programBufferMem_3; // @[RegisterRouter.scala:87:24] wire _out_T_1157 = ~out_rimask_104; // @[RegisterRouter.scala:87:24] wire _out_T_1158 = ~out_wimask_104; // @[RegisterRouter.scala:87:24] wire _out_T_1159 = ~out_romask_104; // @[RegisterRouter.scala:87:24] wire _out_T_1160 = ~out_womask_104; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_81 = {programBufferMem_3, _out_prepend_T_81}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1161 = out_prepend_81; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1162 = _out_T_1161; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_32 = _out_T_1162; // @[MuxLiteral.scala:49:48] wire out_rimask_105 = |_out_rimask_T_105; // @[RegisterRouter.scala:87:24] wire out_wimask_105 = &_out_wimask_T_105; // @[RegisterRouter.scala:87:24] wire out_romask_105 = |_out_romask_T_105; // @[RegisterRouter.scala:87:24] wire out_womask_105 = &_out_womask_T_105; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_105 = out_rivalid_105 & out_rimask_105; // @[RegisterRouter.scala:87:24] wire _out_T_1164 = out_f_rivalid_105; // @[RegisterRouter.scala:87:24] assign out_f_roready_105 = out_roready_105 & out_romask_105; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_8 = out_f_roready_105; // @[RegisterRouter.scala:87:24] wire _out_T_1165 = out_f_roready_105; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_105 = out_wivalid_105 & out_wimask_105; // @[RegisterRouter.scala:87:24] wire _out_T_1166 = out_f_wivalid_105; // @[RegisterRouter.scala:87:24] assign out_f_woready_105 = out_woready_105 & out_womask_105; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_8 = out_f_woready_105; // @[RegisterRouter.scala:87:24] wire _out_T_1167 = out_f_woready_105; // @[RegisterRouter.scala:87:24] assign programBufferNxt_8 = out_f_woready_105 ? _out_T_1163 : programBufferMem_8; // @[RegisterRouter.scala:87:24] wire _out_T_1168 = ~out_rimask_105; // @[RegisterRouter.scala:87:24] wire _out_T_1169 = ~out_wimask_105; // @[RegisterRouter.scala:87:24] wire _out_T_1170 = ~out_romask_105; // @[RegisterRouter.scala:87:24] wire _out_T_1171 = ~out_womask_105; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1173 = _out_T_1172; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_82 = _out_T_1173; // @[RegisterRouter.scala:87:24] wire out_rimask_106 = |_out_rimask_T_106; // @[RegisterRouter.scala:87:24] wire out_wimask_106 = &_out_wimask_T_106; // @[RegisterRouter.scala:87:24] wire out_romask_106 = |_out_romask_T_106; // @[RegisterRouter.scala:87:24] wire out_womask_106 = &_out_womask_T_106; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_106 = out_rivalid_106 & out_rimask_106; // @[RegisterRouter.scala:87:24] wire _out_T_1175 = out_f_rivalid_106; // @[RegisterRouter.scala:87:24] assign out_f_roready_106 = out_roready_106 & out_romask_106; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_9 = out_f_roready_106; // @[RegisterRouter.scala:87:24] wire _out_T_1176 = out_f_roready_106; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_106 = out_wivalid_106 & out_wimask_106; // @[RegisterRouter.scala:87:24] wire _out_T_1177 = out_f_wivalid_106; // @[RegisterRouter.scala:87:24] assign out_f_woready_106 = out_woready_106 & out_womask_106; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_9 = out_f_woready_106; // @[RegisterRouter.scala:87:24] wire _out_T_1178 = out_f_woready_106; // @[RegisterRouter.scala:87:24] assign programBufferNxt_9 = out_f_woready_106 ? _out_T_1174 : programBufferMem_9; // @[RegisterRouter.scala:87:24] wire _out_T_1179 = ~out_rimask_106; // @[RegisterRouter.scala:87:24] wire _out_T_1180 = ~out_wimask_106; // @[RegisterRouter.scala:87:24] wire _out_T_1181 = ~out_romask_106; // @[RegisterRouter.scala:87:24] wire _out_T_1182 = ~out_womask_106; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_82 = {programBufferMem_9, _out_prepend_T_82}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1183 = out_prepend_82; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1184 = _out_T_1183; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_83 = _out_T_1184; // @[RegisterRouter.scala:87:24] wire out_rimask_107 = |_out_rimask_T_107; // @[RegisterRouter.scala:87:24] wire out_wimask_107 = &_out_wimask_T_107; // @[RegisterRouter.scala:87:24] wire out_romask_107 = |_out_romask_T_107; // @[RegisterRouter.scala:87:24] wire out_womask_107 = &_out_womask_T_107; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_107 = out_rivalid_107 & out_rimask_107; // @[RegisterRouter.scala:87:24] wire _out_T_1186 = out_f_rivalid_107; // @[RegisterRouter.scala:87:24] assign out_f_roready_107 = out_roready_107 & out_romask_107; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_10 = out_f_roready_107; // @[RegisterRouter.scala:87:24] wire _out_T_1187 = out_f_roready_107; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_107 = out_wivalid_107 & out_wimask_107; // @[RegisterRouter.scala:87:24] wire _out_T_1188 = out_f_wivalid_107; // @[RegisterRouter.scala:87:24] assign out_f_woready_107 = out_woready_107 & out_womask_107; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_10 = out_f_woready_107; // @[RegisterRouter.scala:87:24] wire _out_T_1189 = out_f_woready_107; // @[RegisterRouter.scala:87:24] assign programBufferNxt_10 = out_f_woready_107 ? _out_T_1185 : programBufferMem_10; // @[RegisterRouter.scala:87:24] wire _out_T_1190 = ~out_rimask_107; // @[RegisterRouter.scala:87:24] wire _out_T_1191 = ~out_wimask_107; // @[RegisterRouter.scala:87:24] wire _out_T_1192 = ~out_romask_107; // @[RegisterRouter.scala:87:24] wire _out_T_1193 = ~out_womask_107; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_83 = {programBufferMem_10, _out_prepend_T_83}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1194 = out_prepend_83; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1195 = _out_T_1194; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_84 = _out_T_1195; // @[RegisterRouter.scala:87:24] wire out_rimask_108 = |_out_rimask_T_108; // @[RegisterRouter.scala:87:24] wire out_wimask_108 = &_out_wimask_T_108; // @[RegisterRouter.scala:87:24] wire out_romask_108 = |_out_romask_T_108; // @[RegisterRouter.scala:87:24] wire out_womask_108 = &_out_womask_T_108; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_108 = out_rivalid_108 & out_rimask_108; // @[RegisterRouter.scala:87:24] wire _out_T_1197 = out_f_rivalid_108; // @[RegisterRouter.scala:87:24] assign out_f_roready_108 = out_roready_108 & out_romask_108; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_11 = out_f_roready_108; // @[RegisterRouter.scala:87:24] wire _out_T_1198 = out_f_roready_108; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_108 = out_wivalid_108 & out_wimask_108; // @[RegisterRouter.scala:87:24] wire _out_T_1199 = out_f_wivalid_108; // @[RegisterRouter.scala:87:24] assign out_f_woready_108 = out_woready_108 & out_womask_108; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_11 = out_f_woready_108; // @[RegisterRouter.scala:87:24] wire _out_T_1200 = out_f_woready_108; // @[RegisterRouter.scala:87:24] assign programBufferNxt_11 = out_f_woready_108 ? _out_T_1196 : programBufferMem_11; // @[RegisterRouter.scala:87:24] wire _out_T_1201 = ~out_rimask_108; // @[RegisterRouter.scala:87:24] wire _out_T_1202 = ~out_wimask_108; // @[RegisterRouter.scala:87:24] wire _out_T_1203 = ~out_romask_108; // @[RegisterRouter.scala:87:24] wire _out_T_1204 = ~out_womask_108; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_84 = {programBufferMem_11, _out_prepend_T_84}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1205 = out_prepend_84; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1206 = _out_T_1205; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_34 = _out_T_1206; // @[MuxLiteral.scala:49:48] wire out_rimask_109 = |_out_rimask_T_109; // @[RegisterRouter.scala:87:24] wire out_wimask_109 = &_out_wimask_T_109; // @[RegisterRouter.scala:87:24] wire out_romask_109 = |_out_romask_T_109; // @[RegisterRouter.scala:87:24] wire out_womask_109 = &_out_womask_T_109; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_109 = out_rivalid_109 & out_rimask_109; // @[RegisterRouter.scala:87:24] wire _out_T_1208 = out_f_rivalid_109; // @[RegisterRouter.scala:87:24] wire out_f_roready_109 = out_roready_109 & out_romask_109; // @[RegisterRouter.scala:87:24] wire _out_T_1209 = out_f_roready_109; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_109 = out_wivalid_109 & out_wimask_109; // @[RegisterRouter.scala:87:24] wire out_f_woready_109 = out_woready_109 & out_womask_109; // @[RegisterRouter.scala:87:24] wire _out_T_1210 = ~out_rimask_109; // @[RegisterRouter.scala:87:24] wire _out_T_1211 = ~out_wimask_109; // @[RegisterRouter.scala:87:24] wire _out_T_1212 = ~out_romask_109; // @[RegisterRouter.scala:87:24] wire _out_T_1213 = ~out_womask_109; // @[RegisterRouter.scala:87:24] wire [3:0] _out_rimask_T_110 = out_frontMask[7:4]; // @[RegisterRouter.scala:87:24] wire [3:0] _out_wimask_T_110 = out_frontMask[7:4]; // @[RegisterRouter.scala:87:24] wire out_rimask_110 = |_out_rimask_T_110; // @[RegisterRouter.scala:87:24] wire out_wimask_110 = &_out_wimask_T_110; // @[RegisterRouter.scala:87:24] wire [3:0] _out_romask_T_110 = out_backMask[7:4]; // @[RegisterRouter.scala:87:24] wire [3:0] _out_womask_T_110 = out_backMask[7:4]; // @[RegisterRouter.scala:87:24] wire out_romask_110 = |_out_romask_T_110; // @[RegisterRouter.scala:87:24] wire out_womask_110 = &_out_womask_T_110; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_110 = out_rivalid_110 & out_rimask_110; // @[RegisterRouter.scala:87:24] wire _out_T_1217 = out_f_rivalid_110; // @[RegisterRouter.scala:87:24] wire out_f_roready_110 = out_roready_110 & out_romask_110; // @[RegisterRouter.scala:87:24] wire _out_T_1218 = out_f_roready_110; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_110 = out_wivalid_110 & out_wimask_110; // @[RegisterRouter.scala:87:24] wire out_f_woready_110 = out_woready_110 & out_womask_110; // @[RegisterRouter.scala:87:24] wire [3:0] _out_T_1216 = out_front_bits_data[7:4]; // @[RegisterRouter.scala:87:24] wire _out_T_1219 = ~out_rimask_110; // @[RegisterRouter.scala:87:24] wire _out_T_1220 = ~out_wimask_110; // @[RegisterRouter.scala:87:24] wire _out_T_1221 = ~out_romask_110; // @[RegisterRouter.scala:87:24] wire _out_T_1222 = ~out_womask_110; // @[RegisterRouter.scala:87:24] wire [2:0] _out_rimask_T_111 = out_frontMask[10:8]; // @[RegisterRouter.scala:87:24] wire [2:0] _out_wimask_T_111 = out_frontMask[10:8]; // @[RegisterRouter.scala:87:24] wire out_rimask_111 = |_out_rimask_T_111; // @[RegisterRouter.scala:87:24] wire out_wimask_111 = &_out_wimask_T_111; // @[RegisterRouter.scala:87:24] wire [2:0] _out_romask_T_111 = out_backMask[10:8]; // @[RegisterRouter.scala:87:24] wire [2:0] _out_womask_T_111 = out_backMask[10:8]; // @[RegisterRouter.scala:87:24] wire out_romask_111 = |_out_romask_T_111; // @[RegisterRouter.scala:87:24] wire out_womask_111 = &_out_womask_T_111; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_111 = out_rivalid_111 & out_rimask_111; // @[RegisterRouter.scala:87:24] wire _out_T_1226 = out_f_rivalid_111; // @[RegisterRouter.scala:87:24] wire out_f_roready_111 = out_roready_111 & out_romask_111; // @[RegisterRouter.scala:87:24] wire _out_T_1227 = out_f_roready_111; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_111 = out_wivalid_111 & out_wimask_111; // @[RegisterRouter.scala:87:24] wire _out_T_1228 = out_f_wivalid_111; // @[RegisterRouter.scala:87:24] assign out_f_woready_111 = out_woready_111 & out_womask_111; // @[RegisterRouter.scala:87:24] assign ABSTRACTCSWrEnMaybe = out_f_woready_111; // @[RegisterRouter.scala:87:24] wire _out_T_1229 = out_f_woready_111; // @[RegisterRouter.scala:87:24] assign _out_T_1225 = out_front_bits_data[10:8]; // @[RegisterRouter.scala:87:24] assign ABSTRACTCSWrData_cmderr = _out_T_1225; // @[RegisterRouter.scala:87:24] wire _out_T_1230 = ~out_rimask_111; // @[RegisterRouter.scala:87:24] wire _out_T_1231 = ~out_wimask_111; // @[RegisterRouter.scala:87:24] wire _out_T_1232 = ~out_romask_111; // @[RegisterRouter.scala:87:24] wire _out_T_1233 = ~out_womask_111; // @[RegisterRouter.scala:87:24] wire [10:0] out_prepend_86 = {ABSTRACTCSRdData_cmderr, 8'h8}; // @[RegisterRouter.scala:87:24] wire [10:0] _out_T_1234 = out_prepend_86; // @[RegisterRouter.scala:87:24] wire [10:0] _out_T_1235 = _out_T_1234; // @[RegisterRouter.scala:87:24] wire [10:0] _out_prepend_T_87 = _out_T_1235; // @[RegisterRouter.scala:87:24] wire out_rimask_112 = _out_rimask_T_112; // @[RegisterRouter.scala:87:24] wire out_wimask_112 = _out_wimask_T_112; // @[RegisterRouter.scala:87:24] wire out_romask_112 = _out_romask_T_112; // @[RegisterRouter.scala:87:24] wire out_womask_112 = _out_womask_T_112; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_112 = out_rivalid_112 & out_rimask_112; // @[RegisterRouter.scala:87:24] wire _out_T_1237 = out_f_rivalid_112; // @[RegisterRouter.scala:87:24] wire out_f_roready_112 = out_roready_112 & out_romask_112; // @[RegisterRouter.scala:87:24] wire _out_T_1238 = out_f_roready_112; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_112 = out_wivalid_112 & out_wimask_112; // @[RegisterRouter.scala:87:24] wire out_f_woready_112 = out_woready_112 & out_womask_112; // @[RegisterRouter.scala:87:24] wire _out_T_1239 = ~out_rimask_112; // @[RegisterRouter.scala:87:24] wire _out_T_1240 = ~out_wimask_112; // @[RegisterRouter.scala:87:24] wire _out_T_1241 = ~out_romask_112; // @[RegisterRouter.scala:87:24] wire _out_T_1242 = ~out_womask_112; // @[RegisterRouter.scala:87:24] wire [11:0] out_prepend_87 = {1'h0, _out_prepend_T_87}; // @[RegisterRouter.scala:87:24] wire [11:0] _out_T_1243 = out_prepend_87; // @[RegisterRouter.scala:87:24] wire [11:0] _out_T_1244 = _out_T_1243; // @[RegisterRouter.scala:87:24] wire [11:0] _out_prepend_T_88 = _out_T_1244; // @[RegisterRouter.scala:87:24] wire out_rimask_113 = _out_rimask_T_113; // @[RegisterRouter.scala:87:24] wire out_wimask_113 = _out_wimask_T_113; // @[RegisterRouter.scala:87:24] wire out_romask_113 = _out_romask_T_113; // @[RegisterRouter.scala:87:24] wire out_womask_113 = _out_womask_T_113; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_113 = out_rivalid_113 & out_rimask_113; // @[RegisterRouter.scala:87:24] wire _out_T_1246 = out_f_rivalid_113; // @[RegisterRouter.scala:87:24] wire out_f_roready_113 = out_roready_113 & out_romask_113; // @[RegisterRouter.scala:87:24] wire _out_T_1247 = out_f_roready_113; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_113 = out_wivalid_113 & out_wimask_113; // @[RegisterRouter.scala:87:24] wire out_f_woready_113 = out_woready_113 & out_womask_113; // @[RegisterRouter.scala:87:24] wire _out_T_1248 = ~out_rimask_113; // @[RegisterRouter.scala:87:24] wire _out_T_1249 = ~out_wimask_113; // @[RegisterRouter.scala:87:24] wire _out_T_1250 = ~out_romask_113; // @[RegisterRouter.scala:87:24] wire _out_T_1251 = ~out_womask_113; // @[RegisterRouter.scala:87:24] wire [12:0] out_prepend_88 = {ABSTRACTCSRdData_busy, _out_prepend_T_88}; // @[RegisterRouter.scala:87:24] wire [12:0] _out_T_1252 = out_prepend_88; // @[RegisterRouter.scala:87:24] wire [12:0] _out_T_1253 = _out_T_1252; // @[RegisterRouter.scala:87:24] wire [12:0] _out_prepend_T_89 = _out_T_1253; // @[RegisterRouter.scala:87:24] wire [10:0] _out_rimask_T_114 = out_frontMask[23:13]; // @[RegisterRouter.scala:87:24] wire [10:0] _out_wimask_T_114 = out_frontMask[23:13]; // @[RegisterRouter.scala:87:24] wire out_rimask_114 = |_out_rimask_T_114; // @[RegisterRouter.scala:87:24] wire out_wimask_114 = &_out_wimask_T_114; // @[RegisterRouter.scala:87:24] wire [10:0] _out_romask_T_114 = out_backMask[23:13]; // @[RegisterRouter.scala:87:24] wire [10:0] _out_womask_T_114 = out_backMask[23:13]; // @[RegisterRouter.scala:87:24] wire out_romask_114 = |_out_romask_T_114; // @[RegisterRouter.scala:87:24] wire out_womask_114 = &_out_womask_T_114; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_114 = out_rivalid_114 & out_rimask_114; // @[RegisterRouter.scala:87:24] wire _out_T_1255 = out_f_rivalid_114; // @[RegisterRouter.scala:87:24] wire out_f_roready_114 = out_roready_114 & out_romask_114; // @[RegisterRouter.scala:87:24] wire _out_T_1256 = out_f_roready_114; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_114 = out_wivalid_114 & out_wimask_114; // @[RegisterRouter.scala:87:24] wire out_f_woready_114 = out_woready_114 & out_womask_114; // @[RegisterRouter.scala:87:24] wire [10:0] _out_T_1254 = out_front_bits_data[23:13]; // @[RegisterRouter.scala:87:24] wire _out_T_1257 = ~out_rimask_114; // @[RegisterRouter.scala:87:24] wire _out_T_1258 = ~out_wimask_114; // @[RegisterRouter.scala:87:24] wire _out_T_1259 = ~out_romask_114; // @[RegisterRouter.scala:87:24] wire _out_T_1260 = ~out_womask_114; // @[RegisterRouter.scala:87:24] wire [13:0] out_prepend_89 = {1'h0, _out_prepend_T_89}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1261 = {10'h0, out_prepend_89}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1262 = _out_T_1261; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_90 = _out_T_1262; // @[RegisterRouter.scala:87:24] wire [4:0] _out_rimask_T_115 = out_frontMask[28:24]; // @[RegisterRouter.scala:87:24] wire [4:0] _out_wimask_T_115 = out_frontMask[28:24]; // @[RegisterRouter.scala:87:24] wire out_rimask_115 = |_out_rimask_T_115; // @[RegisterRouter.scala:87:24] wire out_wimask_115 = &_out_wimask_T_115; // @[RegisterRouter.scala:87:24] wire [4:0] _out_romask_T_115 = out_backMask[28:24]; // @[RegisterRouter.scala:87:24] wire [4:0] _out_womask_T_115 = out_backMask[28:24]; // @[RegisterRouter.scala:87:24] wire out_romask_115 = |_out_romask_T_115; // @[RegisterRouter.scala:87:24] wire out_womask_115 = &_out_womask_T_115; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_115 = out_rivalid_115 & out_rimask_115; // @[RegisterRouter.scala:87:24] wire _out_T_1264 = out_f_rivalid_115; // @[RegisterRouter.scala:87:24] wire out_f_roready_115 = out_roready_115 & out_romask_115; // @[RegisterRouter.scala:87:24] wire _out_T_1265 = out_f_roready_115; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_115 = out_wivalid_115 & out_wimask_115; // @[RegisterRouter.scala:87:24] wire out_f_woready_115 = out_woready_115 & out_womask_115; // @[RegisterRouter.scala:87:24] wire [4:0] _out_T_1263 = out_front_bits_data[28:24]; // @[RegisterRouter.scala:87:24] wire _out_T_1266 = ~out_rimask_115; // @[RegisterRouter.scala:87:24] wire _out_T_1267 = ~out_wimask_115; // @[RegisterRouter.scala:87:24] wire _out_T_1268 = ~out_romask_115; // @[RegisterRouter.scala:87:24] wire _out_T_1269 = ~out_womask_115; // @[RegisterRouter.scala:87:24] wire [28:0] out_prepend_90 = {5'h10, _out_prepend_T_90}; // @[RegisterRouter.scala:87:24] wire [28:0] _out_T_1270 = out_prepend_90; // @[RegisterRouter.scala:87:24] wire [28:0] _out_T_1271 = _out_T_1270; // @[RegisterRouter.scala:87:24] wire out_rimask_116 = |_out_rimask_T_116; // @[RegisterRouter.scala:87:24] wire out_wimask_116 = &_out_wimask_T_116; // @[RegisterRouter.scala:87:24] wire out_romask_116 = |_out_romask_T_116; // @[RegisterRouter.scala:87:24] wire out_womask_116 = &_out_womask_T_116; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_116 = out_rivalid_116 & out_rimask_116; // @[RegisterRouter.scala:87:24] wire _out_T_1273 = out_f_rivalid_116; // @[RegisterRouter.scala:87:24] assign out_f_roready_116 = out_roready_116 & out_romask_116; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_48 = out_f_roready_116; // @[RegisterRouter.scala:87:24] wire _out_T_1274 = out_f_roready_116; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_116 = out_wivalid_116 & out_wimask_116; // @[RegisterRouter.scala:87:24] wire _out_T_1275 = out_f_wivalid_116; // @[RegisterRouter.scala:87:24] assign out_f_woready_116 = out_woready_116 & out_womask_116; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_48 = out_f_woready_116; // @[RegisterRouter.scala:87:24] wire _out_T_1276 = out_f_woready_116; // @[RegisterRouter.scala:87:24] assign programBufferNxt_48 = out_f_woready_116 ? _out_T_1272 : programBufferMem_48; // @[RegisterRouter.scala:87:24] wire _out_T_1277 = ~out_rimask_116; // @[RegisterRouter.scala:87:24] wire _out_T_1278 = ~out_wimask_116; // @[RegisterRouter.scala:87:24] wire _out_T_1279 = ~out_romask_116; // @[RegisterRouter.scala:87:24] wire _out_T_1280 = ~out_womask_116; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1282 = _out_T_1281; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_91 = _out_T_1282; // @[RegisterRouter.scala:87:24] wire out_rimask_117 = |_out_rimask_T_117; // @[RegisterRouter.scala:87:24] wire out_wimask_117 = &_out_wimask_T_117; // @[RegisterRouter.scala:87:24] wire out_romask_117 = |_out_romask_T_117; // @[RegisterRouter.scala:87:24] wire out_womask_117 = &_out_womask_T_117; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_117 = out_rivalid_117 & out_rimask_117; // @[RegisterRouter.scala:87:24] wire _out_T_1284 = out_f_rivalid_117; // @[RegisterRouter.scala:87:24] assign out_f_roready_117 = out_roready_117 & out_romask_117; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_49 = out_f_roready_117; // @[RegisterRouter.scala:87:24] wire _out_T_1285 = out_f_roready_117; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_117 = out_wivalid_117 & out_wimask_117; // @[RegisterRouter.scala:87:24] wire _out_T_1286 = out_f_wivalid_117; // @[RegisterRouter.scala:87:24] assign out_f_woready_117 = out_woready_117 & out_womask_117; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_49 = out_f_woready_117; // @[RegisterRouter.scala:87:24] wire _out_T_1287 = out_f_woready_117; // @[RegisterRouter.scala:87:24] assign programBufferNxt_49 = out_f_woready_117 ? _out_T_1283 : programBufferMem_49; // @[RegisterRouter.scala:87:24] wire _out_T_1288 = ~out_rimask_117; // @[RegisterRouter.scala:87:24] wire _out_T_1289 = ~out_wimask_117; // @[RegisterRouter.scala:87:24] wire _out_T_1290 = ~out_romask_117; // @[RegisterRouter.scala:87:24] wire _out_T_1291 = ~out_womask_117; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_91 = {programBufferMem_49, _out_prepend_T_91}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1292 = out_prepend_91; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1293 = _out_T_1292; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_92 = _out_T_1293; // @[RegisterRouter.scala:87:24] wire out_rimask_118 = |_out_rimask_T_118; // @[RegisterRouter.scala:87:24] wire out_wimask_118 = &_out_wimask_T_118; // @[RegisterRouter.scala:87:24] wire out_romask_118 = |_out_romask_T_118; // @[RegisterRouter.scala:87:24] wire out_womask_118 = &_out_womask_T_118; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_118 = out_rivalid_118 & out_rimask_118; // @[RegisterRouter.scala:87:24] wire _out_T_1295 = out_f_rivalid_118; // @[RegisterRouter.scala:87:24] assign out_f_roready_118 = out_roready_118 & out_romask_118; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_50 = out_f_roready_118; // @[RegisterRouter.scala:87:24] wire _out_T_1296 = out_f_roready_118; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_118 = out_wivalid_118 & out_wimask_118; // @[RegisterRouter.scala:87:24] wire _out_T_1297 = out_f_wivalid_118; // @[RegisterRouter.scala:87:24] assign out_f_woready_118 = out_woready_118 & out_womask_118; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_50 = out_f_woready_118; // @[RegisterRouter.scala:87:24] wire _out_T_1298 = out_f_woready_118; // @[RegisterRouter.scala:87:24] assign programBufferNxt_50 = out_f_woready_118 ? _out_T_1294 : programBufferMem_50; // @[RegisterRouter.scala:87:24] wire _out_T_1299 = ~out_rimask_118; // @[RegisterRouter.scala:87:24] wire _out_T_1300 = ~out_wimask_118; // @[RegisterRouter.scala:87:24] wire _out_T_1301 = ~out_romask_118; // @[RegisterRouter.scala:87:24] wire _out_T_1302 = ~out_womask_118; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_92 = {programBufferMem_50, _out_prepend_T_92}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1303 = out_prepend_92; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1304 = _out_T_1303; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_93 = _out_T_1304; // @[RegisterRouter.scala:87:24] wire out_rimask_119 = |_out_rimask_T_119; // @[RegisterRouter.scala:87:24] wire out_wimask_119 = &_out_wimask_T_119; // @[RegisterRouter.scala:87:24] wire out_romask_119 = |_out_romask_T_119; // @[RegisterRouter.scala:87:24] wire out_womask_119 = &_out_womask_T_119; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_119 = out_rivalid_119 & out_rimask_119; // @[RegisterRouter.scala:87:24] wire _out_T_1306 = out_f_rivalid_119; // @[RegisterRouter.scala:87:24] assign out_f_roready_119 = out_roready_119 & out_romask_119; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_51 = out_f_roready_119; // @[RegisterRouter.scala:87:24] wire _out_T_1307 = out_f_roready_119; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_119 = out_wivalid_119 & out_wimask_119; // @[RegisterRouter.scala:87:24] wire _out_T_1308 = out_f_wivalid_119; // @[RegisterRouter.scala:87:24] assign out_f_woready_119 = out_woready_119 & out_womask_119; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_51 = out_f_woready_119; // @[RegisterRouter.scala:87:24] wire _out_T_1309 = out_f_woready_119; // @[RegisterRouter.scala:87:24] assign programBufferNxt_51 = out_f_woready_119 ? _out_T_1305 : programBufferMem_51; // @[RegisterRouter.scala:87:24] wire _out_T_1310 = ~out_rimask_119; // @[RegisterRouter.scala:87:24] wire _out_T_1311 = ~out_wimask_119; // @[RegisterRouter.scala:87:24] wire _out_T_1312 = ~out_romask_119; // @[RegisterRouter.scala:87:24] wire _out_T_1313 = ~out_womask_119; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_93 = {programBufferMem_51, _out_prepend_T_93}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1314 = out_prepend_93; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1315 = _out_T_1314; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_44 = _out_T_1315; // @[MuxLiteral.scala:49:48] wire out_rimask_120 = |_out_rimask_T_120; // @[RegisterRouter.scala:87:24] wire out_wimask_120 = &_out_wimask_T_120; // @[RegisterRouter.scala:87:24] wire out_romask_120 = |_out_romask_T_120; // @[RegisterRouter.scala:87:24] wire out_womask_120 = &_out_womask_T_120; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_120 = out_rivalid_120 & out_rimask_120; // @[RegisterRouter.scala:87:24] wire _out_T_1317 = out_f_rivalid_120; // @[RegisterRouter.scala:87:24] assign out_f_roready_120 = out_roready_120 & out_romask_120; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_12 = out_f_roready_120; // @[RegisterRouter.scala:87:24] wire _out_T_1318 = out_f_roready_120; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_120 = out_wivalid_120 & out_wimask_120; // @[RegisterRouter.scala:87:24] wire _out_T_1319 = out_f_wivalid_120; // @[RegisterRouter.scala:87:24] assign out_f_woready_120 = out_woready_120 & out_womask_120; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_12 = out_f_woready_120; // @[RegisterRouter.scala:87:24] wire _out_T_1320 = out_f_woready_120; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_12 = out_f_woready_120 ? _out_T_1316 : abstractDataMem_12; // @[RegisterRouter.scala:87:24] wire _out_T_1321 = ~out_rimask_120; // @[RegisterRouter.scala:87:24] wire _out_T_1322 = ~out_wimask_120; // @[RegisterRouter.scala:87:24] wire _out_T_1323 = ~out_romask_120; // @[RegisterRouter.scala:87:24] wire _out_T_1324 = ~out_womask_120; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1326 = _out_T_1325; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_94 = _out_T_1326; // @[RegisterRouter.scala:87:24] wire out_rimask_121 = |_out_rimask_T_121; // @[RegisterRouter.scala:87:24] wire out_wimask_121 = &_out_wimask_T_121; // @[RegisterRouter.scala:87:24] wire out_romask_121 = |_out_romask_T_121; // @[RegisterRouter.scala:87:24] wire out_womask_121 = &_out_womask_T_121; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_121 = out_rivalid_121 & out_rimask_121; // @[RegisterRouter.scala:87:24] wire _out_T_1328 = out_f_rivalid_121; // @[RegisterRouter.scala:87:24] assign out_f_roready_121 = out_roready_121 & out_romask_121; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_13 = out_f_roready_121; // @[RegisterRouter.scala:87:24] wire _out_T_1329 = out_f_roready_121; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_121 = out_wivalid_121 & out_wimask_121; // @[RegisterRouter.scala:87:24] wire _out_T_1330 = out_f_wivalid_121; // @[RegisterRouter.scala:87:24] assign out_f_woready_121 = out_woready_121 & out_womask_121; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_13 = out_f_woready_121; // @[RegisterRouter.scala:87:24] wire _out_T_1331 = out_f_woready_121; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_13 = out_f_woready_121 ? _out_T_1327 : abstractDataMem_13; // @[RegisterRouter.scala:87:24] wire _out_T_1332 = ~out_rimask_121; // @[RegisterRouter.scala:87:24] wire _out_T_1333 = ~out_wimask_121; // @[RegisterRouter.scala:87:24] wire _out_T_1334 = ~out_romask_121; // @[RegisterRouter.scala:87:24] wire _out_T_1335 = ~out_womask_121; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_94 = {abstractDataMem_13, _out_prepend_T_94}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1336 = out_prepend_94; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1337 = _out_T_1336; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_95 = _out_T_1337; // @[RegisterRouter.scala:87:24] wire out_rimask_122 = |_out_rimask_T_122; // @[RegisterRouter.scala:87:24] wire out_wimask_122 = &_out_wimask_T_122; // @[RegisterRouter.scala:87:24] wire out_romask_122 = |_out_romask_T_122; // @[RegisterRouter.scala:87:24] wire out_womask_122 = &_out_womask_T_122; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_122 = out_rivalid_122 & out_rimask_122; // @[RegisterRouter.scala:87:24] wire _out_T_1339 = out_f_rivalid_122; // @[RegisterRouter.scala:87:24] assign out_f_roready_122 = out_roready_122 & out_romask_122; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_14 = out_f_roready_122; // @[RegisterRouter.scala:87:24] wire _out_T_1340 = out_f_roready_122; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_122 = out_wivalid_122 & out_wimask_122; // @[RegisterRouter.scala:87:24] wire _out_T_1341 = out_f_wivalid_122; // @[RegisterRouter.scala:87:24] assign out_f_woready_122 = out_woready_122 & out_womask_122; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_14 = out_f_woready_122; // @[RegisterRouter.scala:87:24] wire _out_T_1342 = out_f_woready_122; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_14 = out_f_woready_122 ? _out_T_1338 : abstractDataMem_14; // @[RegisterRouter.scala:87:24] wire _out_T_1343 = ~out_rimask_122; // @[RegisterRouter.scala:87:24] wire _out_T_1344 = ~out_wimask_122; // @[RegisterRouter.scala:87:24] wire _out_T_1345 = ~out_romask_122; // @[RegisterRouter.scala:87:24] wire _out_T_1346 = ~out_womask_122; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_95 = {abstractDataMem_14, _out_prepend_T_95}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1347 = out_prepend_95; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1348 = _out_T_1347; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_96 = _out_T_1348; // @[RegisterRouter.scala:87:24] wire out_rimask_123 = |_out_rimask_T_123; // @[RegisterRouter.scala:87:24] wire out_wimask_123 = &_out_wimask_T_123; // @[RegisterRouter.scala:87:24] wire out_romask_123 = |_out_romask_T_123; // @[RegisterRouter.scala:87:24] wire out_womask_123 = &_out_womask_T_123; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_123 = out_rivalid_123 & out_rimask_123; // @[RegisterRouter.scala:87:24] wire _out_T_1350 = out_f_rivalid_123; // @[RegisterRouter.scala:87:24] assign out_f_roready_123 = out_roready_123 & out_romask_123; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_15 = out_f_roready_123; // @[RegisterRouter.scala:87:24] wire _out_T_1351 = out_f_roready_123; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_123 = out_wivalid_123 & out_wimask_123; // @[RegisterRouter.scala:87:24] wire _out_T_1352 = out_f_wivalid_123; // @[RegisterRouter.scala:87:24] assign out_f_woready_123 = out_woready_123 & out_womask_123; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_15 = out_f_woready_123; // @[RegisterRouter.scala:87:24] wire _out_T_1353 = out_f_woready_123; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_15 = out_f_woready_123 ? _out_T_1349 : abstractDataMem_15; // @[RegisterRouter.scala:87:24] wire _out_T_1354 = ~out_rimask_123; // @[RegisterRouter.scala:87:24] wire _out_T_1355 = ~out_wimask_123; // @[RegisterRouter.scala:87:24] wire _out_T_1356 = ~out_romask_123; // @[RegisterRouter.scala:87:24] wire _out_T_1357 = ~out_womask_123; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_96 = {abstractDataMem_15, _out_prepend_T_96}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1358 = out_prepend_96; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1359 = _out_T_1358; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_7 = _out_T_1359; // @[MuxLiteral.scala:49:48] wire out_rimask_124 = |_out_rimask_T_124; // @[RegisterRouter.scala:87:24] wire out_wimask_124 = &_out_wimask_T_124; // @[RegisterRouter.scala:87:24] wire out_romask_124 = |_out_romask_T_124; // @[RegisterRouter.scala:87:24] wire out_womask_124 = &_out_womask_T_124; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_124 = out_rivalid_124 & out_rimask_124; // @[RegisterRouter.scala:87:24] wire _out_T_1361 = out_f_rivalid_124; // @[RegisterRouter.scala:87:24] assign out_f_roready_124 = out_roready_124 & out_romask_124; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_28 = out_f_roready_124; // @[RegisterRouter.scala:87:24] wire _out_T_1362 = out_f_roready_124; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_124 = out_wivalid_124 & out_wimask_124; // @[RegisterRouter.scala:87:24] wire _out_T_1363 = out_f_wivalid_124; // @[RegisterRouter.scala:87:24] assign out_f_woready_124 = out_woready_124 & out_womask_124; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_28 = out_f_woready_124; // @[RegisterRouter.scala:87:24] wire _out_T_1364 = out_f_woready_124; // @[RegisterRouter.scala:87:24] assign programBufferNxt_28 = out_f_woready_124 ? _out_T_1360 : programBufferMem_28; // @[RegisterRouter.scala:87:24] wire _out_T_1365 = ~out_rimask_124; // @[RegisterRouter.scala:87:24] wire _out_T_1366 = ~out_wimask_124; // @[RegisterRouter.scala:87:24] wire _out_T_1367 = ~out_romask_124; // @[RegisterRouter.scala:87:24] wire _out_T_1368 = ~out_womask_124; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1370 = _out_T_1369; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_97 = _out_T_1370; // @[RegisterRouter.scala:87:24] wire out_rimask_125 = |_out_rimask_T_125; // @[RegisterRouter.scala:87:24] wire out_wimask_125 = &_out_wimask_T_125; // @[RegisterRouter.scala:87:24] wire out_romask_125 = |_out_romask_T_125; // @[RegisterRouter.scala:87:24] wire out_womask_125 = &_out_womask_T_125; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_125 = out_rivalid_125 & out_rimask_125; // @[RegisterRouter.scala:87:24] wire _out_T_1372 = out_f_rivalid_125; // @[RegisterRouter.scala:87:24] assign out_f_roready_125 = out_roready_125 & out_romask_125; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_29 = out_f_roready_125; // @[RegisterRouter.scala:87:24] wire _out_T_1373 = out_f_roready_125; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_125 = out_wivalid_125 & out_wimask_125; // @[RegisterRouter.scala:87:24] wire _out_T_1374 = out_f_wivalid_125; // @[RegisterRouter.scala:87:24] assign out_f_woready_125 = out_woready_125 & out_womask_125; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_29 = out_f_woready_125; // @[RegisterRouter.scala:87:24] wire _out_T_1375 = out_f_woready_125; // @[RegisterRouter.scala:87:24] assign programBufferNxt_29 = out_f_woready_125 ? _out_T_1371 : programBufferMem_29; // @[RegisterRouter.scala:87:24] wire _out_T_1376 = ~out_rimask_125; // @[RegisterRouter.scala:87:24] wire _out_T_1377 = ~out_wimask_125; // @[RegisterRouter.scala:87:24] wire _out_T_1378 = ~out_romask_125; // @[RegisterRouter.scala:87:24] wire _out_T_1379 = ~out_womask_125; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_97 = {programBufferMem_29, _out_prepend_T_97}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1380 = out_prepend_97; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1381 = _out_T_1380; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_98 = _out_T_1381; // @[RegisterRouter.scala:87:24] wire out_rimask_126 = |_out_rimask_T_126; // @[RegisterRouter.scala:87:24] wire out_wimask_126 = &_out_wimask_T_126; // @[RegisterRouter.scala:87:24] wire out_romask_126 = |_out_romask_T_126; // @[RegisterRouter.scala:87:24] wire out_womask_126 = &_out_womask_T_126; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_126 = out_rivalid_126 & out_rimask_126; // @[RegisterRouter.scala:87:24] wire _out_T_1383 = out_f_rivalid_126; // @[RegisterRouter.scala:87:24] assign out_f_roready_126 = out_roready_126 & out_romask_126; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_30 = out_f_roready_126; // @[RegisterRouter.scala:87:24] wire _out_T_1384 = out_f_roready_126; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_126 = out_wivalid_126 & out_wimask_126; // @[RegisterRouter.scala:87:24] wire _out_T_1385 = out_f_wivalid_126; // @[RegisterRouter.scala:87:24] assign out_f_woready_126 = out_woready_126 & out_womask_126; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_30 = out_f_woready_126; // @[RegisterRouter.scala:87:24] wire _out_T_1386 = out_f_woready_126; // @[RegisterRouter.scala:87:24] assign programBufferNxt_30 = out_f_woready_126 ? _out_T_1382 : programBufferMem_30; // @[RegisterRouter.scala:87:24] wire _out_T_1387 = ~out_rimask_126; // @[RegisterRouter.scala:87:24] wire _out_T_1388 = ~out_wimask_126; // @[RegisterRouter.scala:87:24] wire _out_T_1389 = ~out_romask_126; // @[RegisterRouter.scala:87:24] wire _out_T_1390 = ~out_womask_126; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_98 = {programBufferMem_30, _out_prepend_T_98}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1391 = out_prepend_98; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1392 = _out_T_1391; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_99 = _out_T_1392; // @[RegisterRouter.scala:87:24] wire out_rimask_127 = |_out_rimask_T_127; // @[RegisterRouter.scala:87:24] wire out_wimask_127 = &_out_wimask_T_127; // @[RegisterRouter.scala:87:24] wire out_romask_127 = |_out_romask_T_127; // @[RegisterRouter.scala:87:24] wire out_womask_127 = &_out_womask_T_127; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_127 = out_rivalid_127 & out_rimask_127; // @[RegisterRouter.scala:87:24] wire _out_T_1394 = out_f_rivalid_127; // @[RegisterRouter.scala:87:24] assign out_f_roready_127 = out_roready_127 & out_romask_127; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_31 = out_f_roready_127; // @[RegisterRouter.scala:87:24] wire _out_T_1395 = out_f_roready_127; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_127 = out_wivalid_127 & out_wimask_127; // @[RegisterRouter.scala:87:24] wire _out_T_1396 = out_f_wivalid_127; // @[RegisterRouter.scala:87:24] assign out_f_woready_127 = out_woready_127 & out_womask_127; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_31 = out_f_woready_127; // @[RegisterRouter.scala:87:24] wire _out_T_1397 = out_f_woready_127; // @[RegisterRouter.scala:87:24] assign programBufferNxt_31 = out_f_woready_127 ? _out_T_1393 : programBufferMem_31; // @[RegisterRouter.scala:87:24] wire _out_T_1398 = ~out_rimask_127; // @[RegisterRouter.scala:87:24] wire _out_T_1399 = ~out_wimask_127; // @[RegisterRouter.scala:87:24] wire _out_T_1400 = ~out_romask_127; // @[RegisterRouter.scala:87:24] wire _out_T_1401 = ~out_womask_127; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_99 = {programBufferMem_31, _out_prepend_T_99}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1402 = out_prepend_99; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1403 = _out_T_1402; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_39 = _out_T_1403; // @[MuxLiteral.scala:49:48] wire out_rimask_128 = |_out_rimask_T_128; // @[RegisterRouter.scala:87:24] wire out_wimask_128 = &_out_wimask_T_128; // @[RegisterRouter.scala:87:24] wire out_romask_128 = |_out_romask_T_128; // @[RegisterRouter.scala:87:24] wire out_womask_128 = &_out_womask_T_128; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_128 = out_rivalid_128 & out_rimask_128; // @[RegisterRouter.scala:87:24] wire _out_T_1405 = out_f_rivalid_128; // @[RegisterRouter.scala:87:24] assign out_f_roready_128 = out_roready_128 & out_romask_128; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_28 = out_f_roready_128; // @[RegisterRouter.scala:87:24] wire _out_T_1406 = out_f_roready_128; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_128 = out_wivalid_128 & out_wimask_128; // @[RegisterRouter.scala:87:24] wire _out_T_1407 = out_f_wivalid_128; // @[RegisterRouter.scala:87:24] assign out_f_woready_128 = out_woready_128 & out_womask_128; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_28 = out_f_woready_128; // @[RegisterRouter.scala:87:24] wire _out_T_1408 = out_f_woready_128; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_28 = out_f_woready_128 ? _out_T_1404 : abstractDataMem_28; // @[RegisterRouter.scala:87:24] wire _out_T_1409 = ~out_rimask_128; // @[RegisterRouter.scala:87:24] wire _out_T_1410 = ~out_wimask_128; // @[RegisterRouter.scala:87:24] wire _out_T_1411 = ~out_romask_128; // @[RegisterRouter.scala:87:24] wire _out_T_1412 = ~out_womask_128; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1414 = _out_T_1413; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_100 = _out_T_1414; // @[RegisterRouter.scala:87:24] wire out_rimask_129 = |_out_rimask_T_129; // @[RegisterRouter.scala:87:24] wire out_wimask_129 = &_out_wimask_T_129; // @[RegisterRouter.scala:87:24] wire out_romask_129 = |_out_romask_T_129; // @[RegisterRouter.scala:87:24] wire out_womask_129 = &_out_womask_T_129; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_129 = out_rivalid_129 & out_rimask_129; // @[RegisterRouter.scala:87:24] wire _out_T_1416 = out_f_rivalid_129; // @[RegisterRouter.scala:87:24] assign out_f_roready_129 = out_roready_129 & out_romask_129; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_29 = out_f_roready_129; // @[RegisterRouter.scala:87:24] wire _out_T_1417 = out_f_roready_129; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_129 = out_wivalid_129 & out_wimask_129; // @[RegisterRouter.scala:87:24] wire _out_T_1418 = out_f_wivalid_129; // @[RegisterRouter.scala:87:24] assign out_f_woready_129 = out_woready_129 & out_womask_129; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_29 = out_f_woready_129; // @[RegisterRouter.scala:87:24] wire _out_T_1419 = out_f_woready_129; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_29 = out_f_woready_129 ? _out_T_1415 : abstractDataMem_29; // @[RegisterRouter.scala:87:24] wire _out_T_1420 = ~out_rimask_129; // @[RegisterRouter.scala:87:24] wire _out_T_1421 = ~out_wimask_129; // @[RegisterRouter.scala:87:24] wire _out_T_1422 = ~out_romask_129; // @[RegisterRouter.scala:87:24] wire _out_T_1423 = ~out_womask_129; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_100 = {abstractDataMem_29, _out_prepend_T_100}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1424 = out_prepend_100; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1425 = _out_T_1424; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_101 = _out_T_1425; // @[RegisterRouter.scala:87:24] wire out_rimask_130 = |_out_rimask_T_130; // @[RegisterRouter.scala:87:24] wire out_wimask_130 = &_out_wimask_T_130; // @[RegisterRouter.scala:87:24] wire out_romask_130 = |_out_romask_T_130; // @[RegisterRouter.scala:87:24] wire out_womask_130 = &_out_womask_T_130; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_130 = out_rivalid_130 & out_rimask_130; // @[RegisterRouter.scala:87:24] wire _out_T_1427 = out_f_rivalid_130; // @[RegisterRouter.scala:87:24] assign out_f_roready_130 = out_roready_130 & out_romask_130; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_30 = out_f_roready_130; // @[RegisterRouter.scala:87:24] wire _out_T_1428 = out_f_roready_130; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_130 = out_wivalid_130 & out_wimask_130; // @[RegisterRouter.scala:87:24] wire _out_T_1429 = out_f_wivalid_130; // @[RegisterRouter.scala:87:24] assign out_f_woready_130 = out_woready_130 & out_womask_130; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_30 = out_f_woready_130; // @[RegisterRouter.scala:87:24] wire _out_T_1430 = out_f_woready_130; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_30 = out_f_woready_130 ? _out_T_1426 : abstractDataMem_30; // @[RegisterRouter.scala:87:24] wire _out_T_1431 = ~out_rimask_130; // @[RegisterRouter.scala:87:24] wire _out_T_1432 = ~out_wimask_130; // @[RegisterRouter.scala:87:24] wire _out_T_1433 = ~out_romask_130; // @[RegisterRouter.scala:87:24] wire _out_T_1434 = ~out_womask_130; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_101 = {abstractDataMem_30, _out_prepend_T_101}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1435 = out_prepend_101; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1436 = _out_T_1435; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_102 = _out_T_1436; // @[RegisterRouter.scala:87:24] wire out_rimask_131 = |_out_rimask_T_131; // @[RegisterRouter.scala:87:24] wire out_wimask_131 = &_out_wimask_T_131; // @[RegisterRouter.scala:87:24] wire out_romask_131 = |_out_romask_T_131; // @[RegisterRouter.scala:87:24] wire out_womask_131 = &_out_womask_T_131; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_131 = out_rivalid_131 & out_rimask_131; // @[RegisterRouter.scala:87:24] wire _out_T_1438 = out_f_rivalid_131; // @[RegisterRouter.scala:87:24] assign out_f_roready_131 = out_roready_131 & out_romask_131; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_31 = out_f_roready_131; // @[RegisterRouter.scala:87:24] wire _out_T_1439 = out_f_roready_131; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_131 = out_wivalid_131 & out_wimask_131; // @[RegisterRouter.scala:87:24] wire _out_T_1440 = out_f_wivalid_131; // @[RegisterRouter.scala:87:24] assign out_f_woready_131 = out_woready_131 & out_womask_131; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_31 = out_f_woready_131; // @[RegisterRouter.scala:87:24] wire _out_T_1441 = out_f_woready_131; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_31 = out_f_woready_131 ? _out_T_1437 : abstractDataMem_31; // @[RegisterRouter.scala:87:24] wire _out_T_1442 = ~out_rimask_131; // @[RegisterRouter.scala:87:24] wire _out_T_1443 = ~out_wimask_131; // @[RegisterRouter.scala:87:24] wire _out_T_1444 = ~out_romask_131; // @[RegisterRouter.scala:87:24] wire _out_T_1445 = ~out_womask_131; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_102 = {abstractDataMem_31, _out_prepend_T_102}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1446 = out_prepend_102; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1447 = _out_T_1446; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_11 = _out_T_1447; // @[MuxLiteral.scala:49:48] wire out_rimask_132 = |_out_rimask_T_132; // @[RegisterRouter.scala:87:24] wire out_wimask_132 = &_out_wimask_T_132; // @[RegisterRouter.scala:87:24] wire out_romask_132 = |_out_romask_T_132; // @[RegisterRouter.scala:87:24] wire out_womask_132 = &_out_womask_T_132; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_132 = out_rivalid_132 & out_rimask_132; // @[RegisterRouter.scala:87:24] wire _out_T_1449 = out_f_rivalid_132; // @[RegisterRouter.scala:87:24] assign out_f_roready_132 = out_roready_132 & out_romask_132; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_44 = out_f_roready_132; // @[RegisterRouter.scala:87:24] wire _out_T_1450 = out_f_roready_132; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_132 = out_wivalid_132 & out_wimask_132; // @[RegisterRouter.scala:87:24] wire _out_T_1451 = out_f_wivalid_132; // @[RegisterRouter.scala:87:24] assign out_f_woready_132 = out_woready_132 & out_womask_132; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_44 = out_f_woready_132; // @[RegisterRouter.scala:87:24] wire _out_T_1452 = out_f_woready_132; // @[RegisterRouter.scala:87:24] assign programBufferNxt_44 = out_f_woready_132 ? _out_T_1448 : programBufferMem_44; // @[RegisterRouter.scala:87:24] wire _out_T_1453 = ~out_rimask_132; // @[RegisterRouter.scala:87:24] wire _out_T_1454 = ~out_wimask_132; // @[RegisterRouter.scala:87:24] wire _out_T_1455 = ~out_romask_132; // @[RegisterRouter.scala:87:24] wire _out_T_1456 = ~out_womask_132; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1458 = _out_T_1457; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_103 = _out_T_1458; // @[RegisterRouter.scala:87:24] wire out_rimask_133 = |_out_rimask_T_133; // @[RegisterRouter.scala:87:24] wire out_wimask_133 = &_out_wimask_T_133; // @[RegisterRouter.scala:87:24] wire out_romask_133 = |_out_romask_T_133; // @[RegisterRouter.scala:87:24] wire out_womask_133 = &_out_womask_T_133; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_133 = out_rivalid_133 & out_rimask_133; // @[RegisterRouter.scala:87:24] wire _out_T_1460 = out_f_rivalid_133; // @[RegisterRouter.scala:87:24] assign out_f_roready_133 = out_roready_133 & out_romask_133; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_45 = out_f_roready_133; // @[RegisterRouter.scala:87:24] wire _out_T_1461 = out_f_roready_133; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_133 = out_wivalid_133 & out_wimask_133; // @[RegisterRouter.scala:87:24] wire _out_T_1462 = out_f_wivalid_133; // @[RegisterRouter.scala:87:24] assign out_f_woready_133 = out_woready_133 & out_womask_133; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_45 = out_f_woready_133; // @[RegisterRouter.scala:87:24] wire _out_T_1463 = out_f_woready_133; // @[RegisterRouter.scala:87:24] assign programBufferNxt_45 = out_f_woready_133 ? _out_T_1459 : programBufferMem_45; // @[RegisterRouter.scala:87:24] wire _out_T_1464 = ~out_rimask_133; // @[RegisterRouter.scala:87:24] wire _out_T_1465 = ~out_wimask_133; // @[RegisterRouter.scala:87:24] wire _out_T_1466 = ~out_romask_133; // @[RegisterRouter.scala:87:24] wire _out_T_1467 = ~out_womask_133; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_103 = {programBufferMem_45, _out_prepend_T_103}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1468 = out_prepend_103; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1469 = _out_T_1468; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_104 = _out_T_1469; // @[RegisterRouter.scala:87:24] wire out_rimask_134 = |_out_rimask_T_134; // @[RegisterRouter.scala:87:24] wire out_wimask_134 = &_out_wimask_T_134; // @[RegisterRouter.scala:87:24] wire out_romask_134 = |_out_romask_T_134; // @[RegisterRouter.scala:87:24] wire out_womask_134 = &_out_womask_T_134; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_134 = out_rivalid_134 & out_rimask_134; // @[RegisterRouter.scala:87:24] wire _out_T_1471 = out_f_rivalid_134; // @[RegisterRouter.scala:87:24] assign out_f_roready_134 = out_roready_134 & out_romask_134; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_46 = out_f_roready_134; // @[RegisterRouter.scala:87:24] wire _out_T_1472 = out_f_roready_134; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_134 = out_wivalid_134 & out_wimask_134; // @[RegisterRouter.scala:87:24] wire _out_T_1473 = out_f_wivalid_134; // @[RegisterRouter.scala:87:24] assign out_f_woready_134 = out_woready_134 & out_womask_134; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_46 = out_f_woready_134; // @[RegisterRouter.scala:87:24] wire _out_T_1474 = out_f_woready_134; // @[RegisterRouter.scala:87:24] assign programBufferNxt_46 = out_f_woready_134 ? _out_T_1470 : programBufferMem_46; // @[RegisterRouter.scala:87:24] wire _out_T_1475 = ~out_rimask_134; // @[RegisterRouter.scala:87:24] wire _out_T_1476 = ~out_wimask_134; // @[RegisterRouter.scala:87:24] wire _out_T_1477 = ~out_romask_134; // @[RegisterRouter.scala:87:24] wire _out_T_1478 = ~out_womask_134; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_104 = {programBufferMem_46, _out_prepend_T_104}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1479 = out_prepend_104; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1480 = _out_T_1479; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_105 = _out_T_1480; // @[RegisterRouter.scala:87:24] wire out_rimask_135 = |_out_rimask_T_135; // @[RegisterRouter.scala:87:24] wire out_wimask_135 = &_out_wimask_T_135; // @[RegisterRouter.scala:87:24] wire out_romask_135 = |_out_romask_T_135; // @[RegisterRouter.scala:87:24] wire out_womask_135 = &_out_womask_T_135; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_135 = out_rivalid_135 & out_rimask_135; // @[RegisterRouter.scala:87:24] wire _out_T_1482 = out_f_rivalid_135; // @[RegisterRouter.scala:87:24] assign out_f_roready_135 = out_roready_135 & out_romask_135; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_47 = out_f_roready_135; // @[RegisterRouter.scala:87:24] wire _out_T_1483 = out_f_roready_135; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_135 = out_wivalid_135 & out_wimask_135; // @[RegisterRouter.scala:87:24] wire _out_T_1484 = out_f_wivalid_135; // @[RegisterRouter.scala:87:24] assign out_f_woready_135 = out_woready_135 & out_womask_135; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_47 = out_f_woready_135; // @[RegisterRouter.scala:87:24] wire _out_T_1485 = out_f_woready_135; // @[RegisterRouter.scala:87:24] assign programBufferNxt_47 = out_f_woready_135 ? _out_T_1481 : programBufferMem_47; // @[RegisterRouter.scala:87:24] wire _out_T_1486 = ~out_rimask_135; // @[RegisterRouter.scala:87:24] wire _out_T_1487 = ~out_wimask_135; // @[RegisterRouter.scala:87:24] wire _out_T_1488 = ~out_romask_135; // @[RegisterRouter.scala:87:24] wire _out_T_1489 = ~out_womask_135; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_105 = {programBufferMem_47, _out_prepend_T_105}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1490 = out_prepend_105; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1491 = _out_T_1490; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_43 = _out_T_1491; // @[MuxLiteral.scala:49:48] wire out_rimask_136 = |_out_rimask_T_136; // @[RegisterRouter.scala:87:24] wire out_wimask_136 = &_out_wimask_T_136; // @[RegisterRouter.scala:87:24] wire out_romask_136 = |_out_romask_T_136; // @[RegisterRouter.scala:87:24] wire out_womask_136 = &_out_womask_T_136; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_136 = out_rivalid_136 & out_rimask_136; // @[RegisterRouter.scala:87:24] wire _out_T_1493 = out_f_rivalid_136; // @[RegisterRouter.scala:87:24] assign out_f_roready_136 = out_roready_136 & out_romask_136; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_32 = out_f_roready_136; // @[RegisterRouter.scala:87:24] wire _out_T_1494 = out_f_roready_136; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_136 = out_wivalid_136 & out_wimask_136; // @[RegisterRouter.scala:87:24] wire _out_T_1495 = out_f_wivalid_136; // @[RegisterRouter.scala:87:24] assign out_f_woready_136 = out_woready_136 & out_womask_136; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_32 = out_f_woready_136; // @[RegisterRouter.scala:87:24] wire _out_T_1496 = out_f_woready_136; // @[RegisterRouter.scala:87:24] assign programBufferNxt_32 = out_f_woready_136 ? _out_T_1492 : programBufferMem_32; // @[RegisterRouter.scala:87:24] wire _out_T_1497 = ~out_rimask_136; // @[RegisterRouter.scala:87:24] wire _out_T_1498 = ~out_wimask_136; // @[RegisterRouter.scala:87:24] wire _out_T_1499 = ~out_romask_136; // @[RegisterRouter.scala:87:24] wire _out_T_1500 = ~out_womask_136; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1502 = _out_T_1501; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_106 = _out_T_1502; // @[RegisterRouter.scala:87:24] wire out_rimask_137 = |_out_rimask_T_137; // @[RegisterRouter.scala:87:24] wire out_wimask_137 = &_out_wimask_T_137; // @[RegisterRouter.scala:87:24] wire out_romask_137 = |_out_romask_T_137; // @[RegisterRouter.scala:87:24] wire out_womask_137 = &_out_womask_T_137; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_137 = out_rivalid_137 & out_rimask_137; // @[RegisterRouter.scala:87:24] wire _out_T_1504 = out_f_rivalid_137; // @[RegisterRouter.scala:87:24] assign out_f_roready_137 = out_roready_137 & out_romask_137; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_33 = out_f_roready_137; // @[RegisterRouter.scala:87:24] wire _out_T_1505 = out_f_roready_137; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_137 = out_wivalid_137 & out_wimask_137; // @[RegisterRouter.scala:87:24] wire _out_T_1506 = out_f_wivalid_137; // @[RegisterRouter.scala:87:24] assign out_f_woready_137 = out_woready_137 & out_womask_137; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_33 = out_f_woready_137; // @[RegisterRouter.scala:87:24] wire _out_T_1507 = out_f_woready_137; // @[RegisterRouter.scala:87:24] assign programBufferNxt_33 = out_f_woready_137 ? _out_T_1503 : programBufferMem_33; // @[RegisterRouter.scala:87:24] wire _out_T_1508 = ~out_rimask_137; // @[RegisterRouter.scala:87:24] wire _out_T_1509 = ~out_wimask_137; // @[RegisterRouter.scala:87:24] wire _out_T_1510 = ~out_romask_137; // @[RegisterRouter.scala:87:24] wire _out_T_1511 = ~out_womask_137; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_106 = {programBufferMem_33, _out_prepend_T_106}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1512 = out_prepend_106; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1513 = _out_T_1512; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_107 = _out_T_1513; // @[RegisterRouter.scala:87:24] wire out_rimask_138 = |_out_rimask_T_138; // @[RegisterRouter.scala:87:24] wire out_wimask_138 = &_out_wimask_T_138; // @[RegisterRouter.scala:87:24] wire out_romask_138 = |_out_romask_T_138; // @[RegisterRouter.scala:87:24] wire out_womask_138 = &_out_womask_T_138; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_138 = out_rivalid_138 & out_rimask_138; // @[RegisterRouter.scala:87:24] wire _out_T_1515 = out_f_rivalid_138; // @[RegisterRouter.scala:87:24] assign out_f_roready_138 = out_roready_138 & out_romask_138; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_34 = out_f_roready_138; // @[RegisterRouter.scala:87:24] wire _out_T_1516 = out_f_roready_138; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_138 = out_wivalid_138 & out_wimask_138; // @[RegisterRouter.scala:87:24] wire _out_T_1517 = out_f_wivalid_138; // @[RegisterRouter.scala:87:24] assign out_f_woready_138 = out_woready_138 & out_womask_138; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_34 = out_f_woready_138; // @[RegisterRouter.scala:87:24] wire _out_T_1518 = out_f_woready_138; // @[RegisterRouter.scala:87:24] assign programBufferNxt_34 = out_f_woready_138 ? _out_T_1514 : programBufferMem_34; // @[RegisterRouter.scala:87:24] wire _out_T_1519 = ~out_rimask_138; // @[RegisterRouter.scala:87:24] wire _out_T_1520 = ~out_wimask_138; // @[RegisterRouter.scala:87:24] wire _out_T_1521 = ~out_romask_138; // @[RegisterRouter.scala:87:24] wire _out_T_1522 = ~out_womask_138; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_107 = {programBufferMem_34, _out_prepend_T_107}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1523 = out_prepend_107; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1524 = _out_T_1523; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_108 = _out_T_1524; // @[RegisterRouter.scala:87:24] wire out_rimask_139 = |_out_rimask_T_139; // @[RegisterRouter.scala:87:24] wire out_wimask_139 = &_out_wimask_T_139; // @[RegisterRouter.scala:87:24] wire out_romask_139 = |_out_romask_T_139; // @[RegisterRouter.scala:87:24] wire out_womask_139 = &_out_womask_T_139; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_139 = out_rivalid_139 & out_rimask_139; // @[RegisterRouter.scala:87:24] wire _out_T_1526 = out_f_rivalid_139; // @[RegisterRouter.scala:87:24] assign out_f_roready_139 = out_roready_139 & out_romask_139; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_35 = out_f_roready_139; // @[RegisterRouter.scala:87:24] wire _out_T_1527 = out_f_roready_139; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_139 = out_wivalid_139 & out_wimask_139; // @[RegisterRouter.scala:87:24] wire _out_T_1528 = out_f_wivalid_139; // @[RegisterRouter.scala:87:24] assign out_f_woready_139 = out_woready_139 & out_womask_139; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_35 = out_f_woready_139; // @[RegisterRouter.scala:87:24] wire _out_T_1529 = out_f_woready_139; // @[RegisterRouter.scala:87:24] assign programBufferNxt_35 = out_f_woready_139 ? _out_T_1525 : programBufferMem_35; // @[RegisterRouter.scala:87:24] wire _out_T_1530 = ~out_rimask_139; // @[RegisterRouter.scala:87:24] wire _out_T_1531 = ~out_wimask_139; // @[RegisterRouter.scala:87:24] wire _out_T_1532 = ~out_romask_139; // @[RegisterRouter.scala:87:24] wire _out_T_1533 = ~out_womask_139; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_108 = {programBufferMem_35, _out_prepend_T_108}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1534 = out_prepend_108; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1535 = _out_T_1534; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_40 = _out_T_1535; // @[MuxLiteral.scala:49:48] wire out_rimask_140 = |_out_rimask_T_140; // @[RegisterRouter.scala:87:24] wire out_wimask_140 = &_out_wimask_T_140; // @[RegisterRouter.scala:87:24] wire out_romask_140 = |_out_romask_T_140; // @[RegisterRouter.scala:87:24] wire out_womask_140 = &_out_womask_T_140; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_140 = out_rivalid_140 & out_rimask_140; // @[RegisterRouter.scala:87:24] wire _out_T_1537 = out_f_rivalid_140; // @[RegisterRouter.scala:87:24] assign out_f_roready_140 = out_roready_140 & out_romask_140; // @[RegisterRouter.scala:87:24] assign COMMANDRdEn = out_f_roready_140; // @[RegisterRouter.scala:87:24] wire _out_T_1538 = out_f_roready_140; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_140 = out_wivalid_140 & out_wimask_140; // @[RegisterRouter.scala:87:24] wire _out_T_1539 = out_f_wivalid_140; // @[RegisterRouter.scala:87:24] assign out_f_woready_140 = out_woready_140 & out_womask_140; // @[RegisterRouter.scala:87:24] assign COMMANDWrEnMaybe = out_f_woready_140; // @[RegisterRouter.scala:87:24] wire _out_T_1540 = out_f_woready_140; // @[RegisterRouter.scala:87:24] assign COMMANDWrDataVal = out_f_woready_140 ? _out_T_1536 : 32'h0; // @[RegisterRouter.scala:87:24] wire _out_T_1541 = ~out_rimask_140; // @[RegisterRouter.scala:87:24] wire _out_T_1542 = ~out_wimask_140; // @[RegisterRouter.scala:87:24] wire _out_T_1543 = ~out_romask_140; // @[RegisterRouter.scala:87:24] wire _out_T_1544 = ~out_womask_140; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1546 = _out_T_1545; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_23 = _out_T_1546; // @[MuxLiteral.scala:49:48] wire out_rimask_141 = |_out_rimask_T_141; // @[RegisterRouter.scala:87:24] wire out_wimask_141 = &_out_wimask_T_141; // @[RegisterRouter.scala:87:24] wire out_romask_141 = |_out_romask_T_141; // @[RegisterRouter.scala:87:24] wire out_womask_141 = &_out_womask_T_141; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_141 = out_rivalid_141 & out_rimask_141; // @[RegisterRouter.scala:87:24] wire _out_T_1548 = out_f_rivalid_141; // @[RegisterRouter.scala:87:24] assign out_f_roready_141 = out_roready_141 & out_romask_141; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_16 = out_f_roready_141; // @[RegisterRouter.scala:87:24] wire _out_T_1549 = out_f_roready_141; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_141 = out_wivalid_141 & out_wimask_141; // @[RegisterRouter.scala:87:24] wire _out_T_1550 = out_f_wivalid_141; // @[RegisterRouter.scala:87:24] assign out_f_woready_141 = out_woready_141 & out_womask_141; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_16 = out_f_woready_141; // @[RegisterRouter.scala:87:24] wire _out_T_1551 = out_f_woready_141; // @[RegisterRouter.scala:87:24] assign programBufferNxt_16 = out_f_woready_141 ? _out_T_1547 : programBufferMem_16; // @[RegisterRouter.scala:87:24] wire _out_T_1552 = ~out_rimask_141; // @[RegisterRouter.scala:87:24] wire _out_T_1553 = ~out_wimask_141; // @[RegisterRouter.scala:87:24] wire _out_T_1554 = ~out_romask_141; // @[RegisterRouter.scala:87:24] wire _out_T_1555 = ~out_womask_141; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1557 = _out_T_1556; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_109 = _out_T_1557; // @[RegisterRouter.scala:87:24] wire out_rimask_142 = |_out_rimask_T_142; // @[RegisterRouter.scala:87:24] wire out_wimask_142 = &_out_wimask_T_142; // @[RegisterRouter.scala:87:24] wire out_romask_142 = |_out_romask_T_142; // @[RegisterRouter.scala:87:24] wire out_womask_142 = &_out_womask_T_142; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_142 = out_rivalid_142 & out_rimask_142; // @[RegisterRouter.scala:87:24] wire _out_T_1559 = out_f_rivalid_142; // @[RegisterRouter.scala:87:24] assign out_f_roready_142 = out_roready_142 & out_romask_142; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_17 = out_f_roready_142; // @[RegisterRouter.scala:87:24] wire _out_T_1560 = out_f_roready_142; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_142 = out_wivalid_142 & out_wimask_142; // @[RegisterRouter.scala:87:24] wire _out_T_1561 = out_f_wivalid_142; // @[RegisterRouter.scala:87:24] assign out_f_woready_142 = out_woready_142 & out_womask_142; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_17 = out_f_woready_142; // @[RegisterRouter.scala:87:24] wire _out_T_1562 = out_f_woready_142; // @[RegisterRouter.scala:87:24] assign programBufferNxt_17 = out_f_woready_142 ? _out_T_1558 : programBufferMem_17; // @[RegisterRouter.scala:87:24] wire _out_T_1563 = ~out_rimask_142; // @[RegisterRouter.scala:87:24] wire _out_T_1564 = ~out_wimask_142; // @[RegisterRouter.scala:87:24] wire _out_T_1565 = ~out_romask_142; // @[RegisterRouter.scala:87:24] wire _out_T_1566 = ~out_womask_142; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_109 = {programBufferMem_17, _out_prepend_T_109}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1567 = out_prepend_109; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1568 = _out_T_1567; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_110 = _out_T_1568; // @[RegisterRouter.scala:87:24] wire out_rimask_143 = |_out_rimask_T_143; // @[RegisterRouter.scala:87:24] wire out_wimask_143 = &_out_wimask_T_143; // @[RegisterRouter.scala:87:24] wire out_romask_143 = |_out_romask_T_143; // @[RegisterRouter.scala:87:24] wire out_womask_143 = &_out_womask_T_143; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_143 = out_rivalid_143 & out_rimask_143; // @[RegisterRouter.scala:87:24] wire _out_T_1570 = out_f_rivalid_143; // @[RegisterRouter.scala:87:24] assign out_f_roready_143 = out_roready_143 & out_romask_143; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_18 = out_f_roready_143; // @[RegisterRouter.scala:87:24] wire _out_T_1571 = out_f_roready_143; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_143 = out_wivalid_143 & out_wimask_143; // @[RegisterRouter.scala:87:24] wire _out_T_1572 = out_f_wivalid_143; // @[RegisterRouter.scala:87:24] assign out_f_woready_143 = out_woready_143 & out_womask_143; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_18 = out_f_woready_143; // @[RegisterRouter.scala:87:24] wire _out_T_1573 = out_f_woready_143; // @[RegisterRouter.scala:87:24] assign programBufferNxt_18 = out_f_woready_143 ? _out_T_1569 : programBufferMem_18; // @[RegisterRouter.scala:87:24] wire _out_T_1574 = ~out_rimask_143; // @[RegisterRouter.scala:87:24] wire _out_T_1575 = ~out_wimask_143; // @[RegisterRouter.scala:87:24] wire _out_T_1576 = ~out_romask_143; // @[RegisterRouter.scala:87:24] wire _out_T_1577 = ~out_womask_143; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_110 = {programBufferMem_18, _out_prepend_T_110}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1578 = out_prepend_110; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1579 = _out_T_1578; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_111 = _out_T_1579; // @[RegisterRouter.scala:87:24] wire out_rimask_144 = |_out_rimask_T_144; // @[RegisterRouter.scala:87:24] wire out_wimask_144 = &_out_wimask_T_144; // @[RegisterRouter.scala:87:24] wire out_romask_144 = |_out_romask_T_144; // @[RegisterRouter.scala:87:24] wire out_womask_144 = &_out_womask_T_144; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_144 = out_rivalid_144 & out_rimask_144; // @[RegisterRouter.scala:87:24] wire _out_T_1581 = out_f_rivalid_144; // @[RegisterRouter.scala:87:24] assign out_f_roready_144 = out_roready_144 & out_romask_144; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_19 = out_f_roready_144; // @[RegisterRouter.scala:87:24] wire _out_T_1582 = out_f_roready_144; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_144 = out_wivalid_144 & out_wimask_144; // @[RegisterRouter.scala:87:24] wire _out_T_1583 = out_f_wivalid_144; // @[RegisterRouter.scala:87:24] assign out_f_woready_144 = out_woready_144 & out_womask_144; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_19 = out_f_woready_144; // @[RegisterRouter.scala:87:24] wire _out_T_1584 = out_f_woready_144; // @[RegisterRouter.scala:87:24] assign programBufferNxt_19 = out_f_woready_144 ? _out_T_1580 : programBufferMem_19; // @[RegisterRouter.scala:87:24] wire _out_T_1585 = ~out_rimask_144; // @[RegisterRouter.scala:87:24] wire _out_T_1586 = ~out_wimask_144; // @[RegisterRouter.scala:87:24] wire _out_T_1587 = ~out_romask_144; // @[RegisterRouter.scala:87:24] wire _out_T_1588 = ~out_womask_144; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_111 = {programBufferMem_19, _out_prepend_T_111}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1589 = out_prepend_111; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1590 = _out_T_1589; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_36 = _out_T_1590; // @[MuxLiteral.scala:49:48] wire out_rimask_145 = |_out_rimask_T_145; // @[RegisterRouter.scala:87:24] wire out_wimask_145 = &_out_wimask_T_145; // @[RegisterRouter.scala:87:24] wire out_romask_145 = |_out_romask_T_145; // @[RegisterRouter.scala:87:24] wire out_womask_145 = &_out_womask_T_145; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_145 = out_rivalid_145 & out_rimask_145; // @[RegisterRouter.scala:87:24] wire _out_T_1592 = out_f_rivalid_145; // @[RegisterRouter.scala:87:24] wire out_f_roready_145 = out_roready_145 & out_romask_145; // @[RegisterRouter.scala:87:24] wire _out_T_1593 = out_f_roready_145; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_145 = out_wivalid_145 & out_wimask_145; // @[RegisterRouter.scala:87:24] wire out_f_woready_145 = out_woready_145 & out_womask_145; // @[RegisterRouter.scala:87:24] wire _out_T_1594 = ~out_rimask_145; // @[RegisterRouter.scala:87:24] wire _out_T_1595 = ~out_wimask_145; // @[RegisterRouter.scala:87:24] wire _out_T_1596 = ~out_romask_145; // @[RegisterRouter.scala:87:24] wire _out_T_1597 = ~out_womask_145; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1599 = _out_T_1598; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_19 = _out_T_1599; // @[MuxLiteral.scala:49:48] wire _out_iindex_T = out_front_bits_index[0]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T = out_front_bits_index[0]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_1 = out_front_bits_index[1]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_1 = out_front_bits_index[1]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_2 = out_front_bits_index[2]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_2 = out_front_bits_index[2]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_3 = out_front_bits_index[3]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_3 = out_front_bits_index[3]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_4 = out_front_bits_index[4]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_4 = out_front_bits_index[4]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_5 = out_front_bits_index[5]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_5 = out_front_bits_index[5]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_6 = out_front_bits_index[6]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_6 = out_front_bits_index[6]; // @[RegisterRouter.scala:87:24] wire [1:0] out_iindex_lo_hi = {_out_iindex_T_2, _out_iindex_T_1}; // @[RegisterRouter.scala:87:24] wire [2:0] out_iindex_lo = {out_iindex_lo_hi, _out_iindex_T}; // @[RegisterRouter.scala:87:24] wire [1:0] out_iindex_hi_hi = {_out_iindex_T_5, _out_iindex_T_4}; // @[RegisterRouter.scala:87:24] wire [2:0] out_iindex_hi = {out_iindex_hi_hi, _out_iindex_T_3}; // @[RegisterRouter.scala:87:24] wire [5:0] out_iindex = {out_iindex_hi, out_iindex_lo}; // @[RegisterRouter.scala:87:24] wire [1:0] out_oindex_lo_hi = {_out_oindex_T_2, _out_oindex_T_1}; // @[RegisterRouter.scala:87:24] wire [2:0] out_oindex_lo = {out_oindex_lo_hi, _out_oindex_T}; // @[RegisterRouter.scala:87:24] wire [1:0] out_oindex_hi_hi = {_out_oindex_T_5, _out_oindex_T_4}; // @[RegisterRouter.scala:87:24] wire [2:0] out_oindex_hi = {out_oindex_hi_hi, _out_oindex_T_3}; // @[RegisterRouter.scala:87:24] wire [5:0] out_oindex = {out_oindex_hi, out_oindex_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_frontSel_T = 64'h1 << out_iindex; // @[OneHot.scala:58:35] wire out_frontSel_0 = _out_frontSel_T[0]; // @[OneHot.scala:58:35] wire out_frontSel_1 = _out_frontSel_T[1]; // @[OneHot.scala:58:35] wire out_frontSel_2 = _out_frontSel_T[2]; // @[OneHot.scala:58:35] wire out_frontSel_3 = _out_frontSel_T[3]; // @[OneHot.scala:58:35] wire out_frontSel_4 = _out_frontSel_T[4]; // @[OneHot.scala:58:35] wire out_frontSel_5 = _out_frontSel_T[5]; // @[OneHot.scala:58:35] wire out_frontSel_6 = _out_frontSel_T[6]; // @[OneHot.scala:58:35] wire out_frontSel_7 = _out_frontSel_T[7]; // @[OneHot.scala:58:35] wire out_frontSel_8 = _out_frontSel_T[8]; // @[OneHot.scala:58:35] wire out_frontSel_9 = _out_frontSel_T[9]; // @[OneHot.scala:58:35] wire out_frontSel_10 = _out_frontSel_T[10]; // @[OneHot.scala:58:35] wire out_frontSel_11 = _out_frontSel_T[11]; // @[OneHot.scala:58:35] wire out_frontSel_12 = _out_frontSel_T[12]; // @[OneHot.scala:58:35] wire out_frontSel_13 = _out_frontSel_T[13]; // @[OneHot.scala:58:35] wire out_frontSel_14 = _out_frontSel_T[14]; // @[OneHot.scala:58:35] wire out_frontSel_15 = _out_frontSel_T[15]; // @[OneHot.scala:58:35] wire out_frontSel_16 = _out_frontSel_T[16]; // @[OneHot.scala:58:35] wire out_frontSel_17 = _out_frontSel_T[17]; // @[OneHot.scala:58:35] wire out_frontSel_18 = _out_frontSel_T[18]; // @[OneHot.scala:58:35] wire out_frontSel_19 = _out_frontSel_T[19]; // @[OneHot.scala:58:35] wire out_frontSel_20 = _out_frontSel_T[20]; // @[OneHot.scala:58:35] wire out_frontSel_21 = _out_frontSel_T[21]; // @[OneHot.scala:58:35] wire out_frontSel_22 = _out_frontSel_T[22]; // @[OneHot.scala:58:35] wire out_frontSel_23 = _out_frontSel_T[23]; // @[OneHot.scala:58:35] wire out_frontSel_24 = _out_frontSel_T[24]; // @[OneHot.scala:58:35] wire out_frontSel_25 = _out_frontSel_T[25]; // @[OneHot.scala:58:35] wire out_frontSel_26 = _out_frontSel_T[26]; // @[OneHot.scala:58:35] wire out_frontSel_27 = _out_frontSel_T[27]; // @[OneHot.scala:58:35] wire out_frontSel_28 = _out_frontSel_T[28]; // @[OneHot.scala:58:35] wire out_frontSel_29 = _out_frontSel_T[29]; // @[OneHot.scala:58:35] wire out_frontSel_30 = _out_frontSel_T[30]; // @[OneHot.scala:58:35] wire out_frontSel_31 = _out_frontSel_T[31]; // @[OneHot.scala:58:35] wire out_frontSel_32 = _out_frontSel_T[32]; // @[OneHot.scala:58:35] wire out_frontSel_33 = _out_frontSel_T[33]; // @[OneHot.scala:58:35] wire out_frontSel_34 = _out_frontSel_T[34]; // @[OneHot.scala:58:35] wire out_frontSel_35 = _out_frontSel_T[35]; // @[OneHot.scala:58:35] wire out_frontSel_36 = _out_frontSel_T[36]; // @[OneHot.scala:58:35] wire out_frontSel_37 = _out_frontSel_T[37]; // @[OneHot.scala:58:35] wire out_frontSel_38 = _out_frontSel_T[38]; // @[OneHot.scala:58:35] wire out_frontSel_39 = _out_frontSel_T[39]; // @[OneHot.scala:58:35] wire out_frontSel_40 = _out_frontSel_T[40]; // @[OneHot.scala:58:35] wire out_frontSel_41 = _out_frontSel_T[41]; // @[OneHot.scala:58:35] wire out_frontSel_42 = _out_frontSel_T[42]; // @[OneHot.scala:58:35] wire out_frontSel_43 = _out_frontSel_T[43]; // @[OneHot.scala:58:35] wire out_frontSel_44 = _out_frontSel_T[44]; // @[OneHot.scala:58:35] wire out_frontSel_45 = _out_frontSel_T[45]; // @[OneHot.scala:58:35] wire out_frontSel_46 = _out_frontSel_T[46]; // @[OneHot.scala:58:35] wire out_frontSel_47 = _out_frontSel_T[47]; // @[OneHot.scala:58:35] wire out_frontSel_48 = _out_frontSel_T[48]; // @[OneHot.scala:58:35] wire out_frontSel_49 = _out_frontSel_T[49]; // @[OneHot.scala:58:35] wire out_frontSel_50 = _out_frontSel_T[50]; // @[OneHot.scala:58:35] wire out_frontSel_51 = _out_frontSel_T[51]; // @[OneHot.scala:58:35] wire out_frontSel_52 = _out_frontSel_T[52]; // @[OneHot.scala:58:35] wire out_frontSel_53 = _out_frontSel_T[53]; // @[OneHot.scala:58:35] wire out_frontSel_54 = _out_frontSel_T[54]; // @[OneHot.scala:58:35] wire out_frontSel_55 = _out_frontSel_T[55]; // @[OneHot.scala:58:35] wire out_frontSel_56 = _out_frontSel_T[56]; // @[OneHot.scala:58:35] wire out_frontSel_57 = _out_frontSel_T[57]; // @[OneHot.scala:58:35] wire out_frontSel_58 = _out_frontSel_T[58]; // @[OneHot.scala:58:35] wire out_frontSel_59 = _out_frontSel_T[59]; // @[OneHot.scala:58:35] wire out_frontSel_60 = _out_frontSel_T[60]; // @[OneHot.scala:58:35] wire out_frontSel_61 = _out_frontSel_T[61]; // @[OneHot.scala:58:35] wire out_frontSel_62 = _out_frontSel_T[62]; // @[OneHot.scala:58:35] wire out_frontSel_63 = _out_frontSel_T[63]; // @[OneHot.scala:58:35] wire [63:0] _out_backSel_T = 64'h1 << out_oindex; // @[OneHot.scala:58:35] wire out_backSel_0 = _out_backSel_T[0]; // @[OneHot.scala:58:35] wire out_backSel_1 = _out_backSel_T[1]; // @[OneHot.scala:58:35] wire out_backSel_2 = _out_backSel_T[2]; // @[OneHot.scala:58:35] wire out_backSel_3 = _out_backSel_T[3]; // @[OneHot.scala:58:35] wire out_backSel_4 = _out_backSel_T[4]; // @[OneHot.scala:58:35] wire out_backSel_5 = _out_backSel_T[5]; // @[OneHot.scala:58:35] wire out_backSel_6 = _out_backSel_T[6]; // @[OneHot.scala:58:35] wire out_backSel_7 = _out_backSel_T[7]; // @[OneHot.scala:58:35] wire out_backSel_8 = _out_backSel_T[8]; // @[OneHot.scala:58:35] wire out_backSel_9 = _out_backSel_T[9]; // @[OneHot.scala:58:35] wire out_backSel_10 = _out_backSel_T[10]; // @[OneHot.scala:58:35] wire out_backSel_11 = _out_backSel_T[11]; // @[OneHot.scala:58:35] wire out_backSel_12 = _out_backSel_T[12]; // @[OneHot.scala:58:35] wire out_backSel_13 = _out_backSel_T[13]; // @[OneHot.scala:58:35] wire out_backSel_14 = _out_backSel_T[14]; // @[OneHot.scala:58:35] wire out_backSel_15 = _out_backSel_T[15]; // @[OneHot.scala:58:35] wire out_backSel_16 = _out_backSel_T[16]; // @[OneHot.scala:58:35] wire out_backSel_17 = _out_backSel_T[17]; // @[OneHot.scala:58:35] wire out_backSel_18 = _out_backSel_T[18]; // @[OneHot.scala:58:35] wire out_backSel_19 = _out_backSel_T[19]; // @[OneHot.scala:58:35] wire out_backSel_20 = _out_backSel_T[20]; // @[OneHot.scala:58:35] wire out_backSel_21 = _out_backSel_T[21]; // @[OneHot.scala:58:35] wire out_backSel_22 = _out_backSel_T[22]; // @[OneHot.scala:58:35] wire out_backSel_23 = _out_backSel_T[23]; // @[OneHot.scala:58:35] wire out_backSel_24 = _out_backSel_T[24]; // @[OneHot.scala:58:35] wire out_backSel_25 = _out_backSel_T[25]; // @[OneHot.scala:58:35] wire out_backSel_26 = _out_backSel_T[26]; // @[OneHot.scala:58:35] wire out_backSel_27 = _out_backSel_T[27]; // @[OneHot.scala:58:35] wire out_backSel_28 = _out_backSel_T[28]; // @[OneHot.scala:58:35] wire out_backSel_29 = _out_backSel_T[29]; // @[OneHot.scala:58:35] wire out_backSel_30 = _out_backSel_T[30]; // @[OneHot.scala:58:35] wire out_backSel_31 = _out_backSel_T[31]; // @[OneHot.scala:58:35] wire out_backSel_32 = _out_backSel_T[32]; // @[OneHot.scala:58:35] wire out_backSel_33 = _out_backSel_T[33]; // @[OneHot.scala:58:35] wire out_backSel_34 = _out_backSel_T[34]; // @[OneHot.scala:58:35] wire out_backSel_35 = _out_backSel_T[35]; // @[OneHot.scala:58:35] wire out_backSel_36 = _out_backSel_T[36]; // @[OneHot.scala:58:35] wire out_backSel_37 = _out_backSel_T[37]; // @[OneHot.scala:58:35] wire out_backSel_38 = _out_backSel_T[38]; // @[OneHot.scala:58:35] wire out_backSel_39 = _out_backSel_T[39]; // @[OneHot.scala:58:35] wire out_backSel_40 = _out_backSel_T[40]; // @[OneHot.scala:58:35] wire out_backSel_41 = _out_backSel_T[41]; // @[OneHot.scala:58:35] wire out_backSel_42 = _out_backSel_T[42]; // @[OneHot.scala:58:35] wire out_backSel_43 = _out_backSel_T[43]; // @[OneHot.scala:58:35] wire out_backSel_44 = _out_backSel_T[44]; // @[OneHot.scala:58:35] wire out_backSel_45 = _out_backSel_T[45]; // @[OneHot.scala:58:35] wire out_backSel_46 = _out_backSel_T[46]; // @[OneHot.scala:58:35] wire out_backSel_47 = _out_backSel_T[47]; // @[OneHot.scala:58:35] wire out_backSel_48 = _out_backSel_T[48]; // @[OneHot.scala:58:35] wire out_backSel_49 = _out_backSel_T[49]; // @[OneHot.scala:58:35] wire out_backSel_50 = _out_backSel_T[50]; // @[OneHot.scala:58:35] wire out_backSel_51 = _out_backSel_T[51]; // @[OneHot.scala:58:35] wire out_backSel_52 = _out_backSel_T[52]; // @[OneHot.scala:58:35] wire out_backSel_53 = _out_backSel_T[53]; // @[OneHot.scala:58:35] wire out_backSel_54 = _out_backSel_T[54]; // @[OneHot.scala:58:35] wire out_backSel_55 = _out_backSel_T[55]; // @[OneHot.scala:58:35] wire out_backSel_56 = _out_backSel_T[56]; // @[OneHot.scala:58:35] wire out_backSel_57 = _out_backSel_T[57]; // @[OneHot.scala:58:35] wire out_backSel_58 = _out_backSel_T[58]; // @[OneHot.scala:58:35] wire out_backSel_59 = _out_backSel_T[59]; // @[OneHot.scala:58:35] wire out_backSel_60 = _out_backSel_T[60]; // @[OneHot.scala:58:35] wire out_backSel_61 = _out_backSel_T[61]; // @[OneHot.scala:58:35] wire out_backSel_62 = _out_backSel_T[62]; // @[OneHot.scala:58:35] wire out_backSel_63 = _out_backSel_T[63]; // @[OneHot.scala:58:35] wire _GEN_11 = in_valid & out_front_ready; // @[RegisterRouter.scala:73:18, :87:24] wire _out_rifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T = _GEN_11; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T = _GEN_11; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1 = _out_rifireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_2 = _out_rifireMux_T_1 & out_frontSel_0; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_3 = _out_rifireMux_T_2 & _out_T_40; // @[RegisterRouter.scala:87:24] assign out_rivalid_81 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_4 = ~_out_T_40; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_6 = _out_rifireMux_T_1 & out_frontSel_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_7 = _out_rifireMux_T_6; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_10 = _out_rifireMux_T_1 & out_frontSel_2; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_11 = _out_rifireMux_T_10; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_14 = _out_rifireMux_T_1 & out_frontSel_3; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_15 = _out_rifireMux_T_14; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_18 = _out_rifireMux_T_1 & out_frontSel_4; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_19 = _out_rifireMux_T_18 & _out_T_12; // @[RegisterRouter.scala:87:24] assign out_rivalid_21 = _out_rifireMux_T_19; // @[RegisterRouter.scala:87:24] assign out_rivalid_22 = _out_rifireMux_T_19; // @[RegisterRouter.scala:87:24] assign out_rivalid_23 = _out_rifireMux_T_19; // @[RegisterRouter.scala:87:24] assign out_rivalid_24 = _out_rifireMux_T_19; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_20 = ~_out_T_12; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_22 = _out_rifireMux_T_1 & out_frontSel_5; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_23 = _out_rifireMux_T_22 & _out_T; // @[RegisterRouter.scala:87:24] assign out_rivalid_0 = _out_rifireMux_T_23; // @[RegisterRouter.scala:87:24] assign out_rivalid_1 = _out_rifireMux_T_23; // @[RegisterRouter.scala:87:24] assign out_rivalid_2 = _out_rifireMux_T_23; // @[RegisterRouter.scala:87:24] assign out_rivalid_3 = _out_rifireMux_T_23; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_24 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_26 = _out_rifireMux_T_1 & out_frontSel_6; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_27 = _out_rifireMux_T_26 & _out_T_30; // @[RegisterRouter.scala:87:24] assign out_rivalid_64 = _out_rifireMux_T_27; // @[RegisterRouter.scala:87:24] assign out_rivalid_65 = _out_rifireMux_T_27; // @[RegisterRouter.scala:87:24] assign out_rivalid_66 = _out_rifireMux_T_27; // @[RegisterRouter.scala:87:24] assign out_rivalid_67 = _out_rifireMux_T_27; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_28 = ~_out_T_30; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_30 = _out_rifireMux_T_1 & out_frontSel_7; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_31 = _out_rifireMux_T_30 & _out_T_52; // @[RegisterRouter.scala:87:24] assign out_rivalid_120 = _out_rifireMux_T_31; // @[RegisterRouter.scala:87:24] assign out_rivalid_121 = _out_rifireMux_T_31; // @[RegisterRouter.scala:87:24] assign out_rivalid_122 = _out_rifireMux_T_31; // @[RegisterRouter.scala:87:24] assign out_rivalid_123 = _out_rifireMux_T_31; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_32 = ~_out_T_52; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_34 = _out_rifireMux_T_1 & out_frontSel_8; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_35 = _out_rifireMux_T_34 & _out_T_10; // @[RegisterRouter.scala:87:24] assign out_rivalid_17 = _out_rifireMux_T_35; // @[RegisterRouter.scala:87:24] assign out_rivalid_18 = _out_rifireMux_T_35; // @[RegisterRouter.scala:87:24] assign out_rivalid_19 = _out_rifireMux_T_35; // @[RegisterRouter.scala:87:24] assign out_rivalid_20 = _out_rifireMux_T_35; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_36 = ~_out_T_10; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_38 = _out_rifireMux_T_1 & out_frontSel_9; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_39 = _out_rifireMux_T_38 & _out_T_4; // @[RegisterRouter.scala:87:24] assign out_rivalid_5 = _out_rifireMux_T_39; // @[RegisterRouter.scala:87:24] assign out_rivalid_6 = _out_rifireMux_T_39; // @[RegisterRouter.scala:87:24] assign out_rivalid_7 = _out_rifireMux_T_39; // @[RegisterRouter.scala:87:24] assign out_rivalid_8 = _out_rifireMux_T_39; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_40 = ~_out_T_4; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_42 = _out_rifireMux_T_1 & out_frontSel_10; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_43 = _out_rifireMux_T_42 & _out_T_16; // @[RegisterRouter.scala:87:24] assign out_rivalid_29 = _out_rifireMux_T_43; // @[RegisterRouter.scala:87:24] assign out_rivalid_30 = _out_rifireMux_T_43; // @[RegisterRouter.scala:87:24] assign out_rivalid_31 = _out_rifireMux_T_43; // @[RegisterRouter.scala:87:24] assign out_rivalid_32 = _out_rifireMux_T_43; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_44 = ~_out_T_16; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_46 = _out_rifireMux_T_1 & out_frontSel_11; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_47 = _out_rifireMux_T_46 & _out_T_56; // @[RegisterRouter.scala:87:24] assign out_rivalid_128 = _out_rifireMux_T_47; // @[RegisterRouter.scala:87:24] assign out_rivalid_129 = _out_rifireMux_T_47; // @[RegisterRouter.scala:87:24] assign out_rivalid_130 = _out_rifireMux_T_47; // @[RegisterRouter.scala:87:24] assign out_rivalid_131 = _out_rifireMux_T_47; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_48 = ~_out_T_56; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_50 = _out_rifireMux_T_1 & out_frontSel_12; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_51 = _out_rifireMux_T_50; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_54 = _out_rifireMux_T_1 & out_frontSel_13; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_55 = _out_rifireMux_T_54; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_58 = _out_rifireMux_T_1 & out_frontSel_14; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_59 = _out_rifireMux_T_58; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_62 = _out_rifireMux_T_1 & out_frontSel_15; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_63 = _out_rifireMux_T_62; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_66 = _out_rifireMux_T_1 & out_frontSel_16; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_67 = _out_rifireMux_T_66; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_70 = _out_rifireMux_T_1 & out_frontSel_17; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_71 = _out_rifireMux_T_70 & _out_T_42; // @[RegisterRouter.scala:87:24] assign out_rivalid_82 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_rivalid_83 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_rivalid_84 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_rivalid_85 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_rivalid_86 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_rivalid_87 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_rivalid_88 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_rivalid_89 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_rivalid_90 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_rivalid_91 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_rivalid_92 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_rivalid_93 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_rivalid_94 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_rivalid_95 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_rivalid_96 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_rivalid_97 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_rivalid_98 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_rivalid_99 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_rivalid_100 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_72 = ~_out_T_42; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_74 = _out_rifireMux_T_1 & out_frontSel_18; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_75 = _out_rifireMux_T_74; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_78 = _out_rifireMux_T_1 & out_frontSel_19; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_79 = _out_rifireMux_T_78 & _out_T_66; // @[RegisterRouter.scala:87:24] assign out_rivalid_145 = _out_rifireMux_T_79; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_80 = ~_out_T_66; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_82 = _out_rifireMux_T_1 & out_frontSel_20; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_83 = _out_rifireMux_T_82; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_86 = _out_rifireMux_T_1 & out_frontSel_21; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_87 = _out_rifireMux_T_86; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_90 = _out_rifireMux_T_1 & out_frontSel_22; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_91 = _out_rifireMux_T_90 & _out_T_48; // @[RegisterRouter.scala:87:24] assign out_rivalid_109 = _out_rifireMux_T_91; // @[RegisterRouter.scala:87:24] assign out_rivalid_110 = _out_rifireMux_T_91; // @[RegisterRouter.scala:87:24] assign out_rivalid_111 = _out_rifireMux_T_91; // @[RegisterRouter.scala:87:24] assign out_rivalid_112 = _out_rifireMux_T_91; // @[RegisterRouter.scala:87:24] assign out_rivalid_113 = _out_rifireMux_T_91; // @[RegisterRouter.scala:87:24] assign out_rivalid_114 = _out_rifireMux_T_91; // @[RegisterRouter.scala:87:24] assign out_rivalid_115 = _out_rifireMux_T_91; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_92 = ~_out_T_48; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_94 = _out_rifireMux_T_1 & out_frontSel_23; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_95 = _out_rifireMux_T_94 & _out_T_62; // @[RegisterRouter.scala:87:24] assign out_rivalid_140 = _out_rifireMux_T_95; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_96 = ~_out_T_62; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_98 = _out_rifireMux_T_1 & out_frontSel_24; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_99 = _out_rifireMux_T_98 & _out_T_22; // @[RegisterRouter.scala:87:24] assign out_rivalid_52 = _out_rifireMux_T_99; // @[RegisterRouter.scala:87:24] assign out_rivalid_53 = _out_rifireMux_T_99; // @[RegisterRouter.scala:87:24] assign out_rivalid_54 = _out_rifireMux_T_99; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_100 = ~_out_T_22; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_102 = _out_rifireMux_T_1 & out_frontSel_25; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_103 = _out_rifireMux_T_102; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_106 = _out_rifireMux_T_1 & out_frontSel_26; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_107 = _out_rifireMux_T_106; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_110 = _out_rifireMux_T_1 & out_frontSel_27; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_111 = _out_rifireMux_T_110; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_114 = _out_rifireMux_T_1 & out_frontSel_28; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_115 = _out_rifireMux_T_114; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_118 = _out_rifireMux_T_1 & out_frontSel_29; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_119 = _out_rifireMux_T_118; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_122 = _out_rifireMux_T_1 & out_frontSel_30; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_123 = _out_rifireMux_T_122; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_126 = _out_rifireMux_T_1 & out_frontSel_31; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_127 = _out_rifireMux_T_126; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_130 = _out_rifireMux_T_1 & out_frontSel_32; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_131 = _out_rifireMux_T_130 & _out_T_44; // @[RegisterRouter.scala:87:24] assign out_rivalid_101 = _out_rifireMux_T_131; // @[RegisterRouter.scala:87:24] assign out_rivalid_102 = _out_rifireMux_T_131; // @[RegisterRouter.scala:87:24] assign out_rivalid_103 = _out_rifireMux_T_131; // @[RegisterRouter.scala:87:24] assign out_rivalid_104 = _out_rifireMux_T_131; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_132 = ~_out_T_44; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_134 = _out_rifireMux_T_1 & out_frontSel_33; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_135 = _out_rifireMux_T_134 & _out_T_36; // @[RegisterRouter.scala:87:24] assign out_rivalid_73 = _out_rifireMux_T_135; // @[RegisterRouter.scala:87:24] assign out_rivalid_74 = _out_rifireMux_T_135; // @[RegisterRouter.scala:87:24] assign out_rivalid_75 = _out_rifireMux_T_135; // @[RegisterRouter.scala:87:24] assign out_rivalid_76 = _out_rifireMux_T_135; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_136 = ~_out_T_36; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_138 = _out_rifireMux_T_1 & out_frontSel_34; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_139 = _out_rifireMux_T_138 & _out_T_46; // @[RegisterRouter.scala:87:24] assign out_rivalid_105 = _out_rifireMux_T_139; // @[RegisterRouter.scala:87:24] assign out_rivalid_106 = _out_rifireMux_T_139; // @[RegisterRouter.scala:87:24] assign out_rivalid_107 = _out_rifireMux_T_139; // @[RegisterRouter.scala:87:24] assign out_rivalid_108 = _out_rifireMux_T_139; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_140 = ~_out_T_46; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_142 = _out_rifireMux_T_1 & out_frontSel_35; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_143 = _out_rifireMux_T_142 & _out_T_8; // @[RegisterRouter.scala:87:24] assign out_rivalid_13 = _out_rifireMux_T_143; // @[RegisterRouter.scala:87:24] assign out_rivalid_14 = _out_rifireMux_T_143; // @[RegisterRouter.scala:87:24] assign out_rivalid_15 = _out_rifireMux_T_143; // @[RegisterRouter.scala:87:24] assign out_rivalid_16 = _out_rifireMux_T_143; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_144 = ~_out_T_8; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_146 = _out_rifireMux_T_1 & out_frontSel_36; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_147 = _out_rifireMux_T_146 & _out_T_64; // @[RegisterRouter.scala:87:24] assign out_rivalid_141 = _out_rifireMux_T_147; // @[RegisterRouter.scala:87:24] assign out_rivalid_142 = _out_rifireMux_T_147; // @[RegisterRouter.scala:87:24] assign out_rivalid_143 = _out_rifireMux_T_147; // @[RegisterRouter.scala:87:24] assign out_rivalid_144 = _out_rifireMux_T_147; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_148 = ~_out_T_64; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_150 = _out_rifireMux_T_1 & out_frontSel_37; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_151 = _out_rifireMux_T_150 & _out_T_24; // @[RegisterRouter.scala:87:24] assign out_rivalid_55 = _out_rifireMux_T_151; // @[RegisterRouter.scala:87:24] assign out_rivalid_56 = _out_rifireMux_T_151; // @[RegisterRouter.scala:87:24] assign out_rivalid_57 = _out_rifireMux_T_151; // @[RegisterRouter.scala:87:24] assign out_rivalid_58 = _out_rifireMux_T_151; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_152 = ~_out_T_24; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_154 = _out_rifireMux_T_1 & out_frontSel_38; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_155 = _out_rifireMux_T_154 & _out_T_34; // @[RegisterRouter.scala:87:24] assign out_rivalid_69 = _out_rifireMux_T_155; // @[RegisterRouter.scala:87:24] assign out_rivalid_70 = _out_rifireMux_T_155; // @[RegisterRouter.scala:87:24] assign out_rivalid_71 = _out_rifireMux_T_155; // @[RegisterRouter.scala:87:24] assign out_rivalid_72 = _out_rifireMux_T_155; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_156 = ~_out_T_34; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_158 = _out_rifireMux_T_1 & out_frontSel_39; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_159 = _out_rifireMux_T_158 & _out_T_54; // @[RegisterRouter.scala:87:24] assign out_rivalid_124 = _out_rifireMux_T_159; // @[RegisterRouter.scala:87:24] assign out_rivalid_125 = _out_rifireMux_T_159; // @[RegisterRouter.scala:87:24] assign out_rivalid_126 = _out_rifireMux_T_159; // @[RegisterRouter.scala:87:24] assign out_rivalid_127 = _out_rifireMux_T_159; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_160 = ~_out_T_54; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_162 = _out_rifireMux_T_1 & out_frontSel_40; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_163 = _out_rifireMux_T_162 & _out_T_60; // @[RegisterRouter.scala:87:24] assign out_rivalid_136 = _out_rifireMux_T_163; // @[RegisterRouter.scala:87:24] assign out_rivalid_137 = _out_rifireMux_T_163; // @[RegisterRouter.scala:87:24] assign out_rivalid_138 = _out_rifireMux_T_163; // @[RegisterRouter.scala:87:24] assign out_rivalid_139 = _out_rifireMux_T_163; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_164 = ~_out_T_60; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_166 = _out_rifireMux_T_1 & out_frontSel_41; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_167 = _out_rifireMux_T_166 & _out_T_6; // @[RegisterRouter.scala:87:24] assign out_rivalid_9 = _out_rifireMux_T_167; // @[RegisterRouter.scala:87:24] assign out_rivalid_10 = _out_rifireMux_T_167; // @[RegisterRouter.scala:87:24] assign out_rivalid_11 = _out_rifireMux_T_167; // @[RegisterRouter.scala:87:24] assign out_rivalid_12 = _out_rifireMux_T_167; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_168 = ~_out_T_6; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_170 = _out_rifireMux_T_1 & out_frontSel_42; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_171 = _out_rifireMux_T_170 & _out_T_20; // @[RegisterRouter.scala:87:24] assign out_rivalid_48 = _out_rifireMux_T_171; // @[RegisterRouter.scala:87:24] assign out_rivalid_49 = _out_rifireMux_T_171; // @[RegisterRouter.scala:87:24] assign out_rivalid_50 = _out_rifireMux_T_171; // @[RegisterRouter.scala:87:24] assign out_rivalid_51 = _out_rifireMux_T_171; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_172 = ~_out_T_20; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_174 = _out_rifireMux_T_1 & out_frontSel_43; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_175 = _out_rifireMux_T_174 & _out_T_58; // @[RegisterRouter.scala:87:24] assign out_rivalid_132 = _out_rifireMux_T_175; // @[RegisterRouter.scala:87:24] assign out_rivalid_133 = _out_rifireMux_T_175; // @[RegisterRouter.scala:87:24] assign out_rivalid_134 = _out_rifireMux_T_175; // @[RegisterRouter.scala:87:24] assign out_rivalid_135 = _out_rifireMux_T_175; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_176 = ~_out_T_58; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_178 = _out_rifireMux_T_1 & out_frontSel_44; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_179 = _out_rifireMux_T_178 & _out_T_50; // @[RegisterRouter.scala:87:24] assign out_rivalid_116 = _out_rifireMux_T_179; // @[RegisterRouter.scala:87:24] assign out_rivalid_117 = _out_rifireMux_T_179; // @[RegisterRouter.scala:87:24] assign out_rivalid_118 = _out_rifireMux_T_179; // @[RegisterRouter.scala:87:24] assign out_rivalid_119 = _out_rifireMux_T_179; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_180 = ~_out_T_50; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_182 = _out_rifireMux_T_1 & out_frontSel_45; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_183 = _out_rifireMux_T_182 & _out_T_38; // @[RegisterRouter.scala:87:24] assign out_rivalid_77 = _out_rifireMux_T_183; // @[RegisterRouter.scala:87:24] assign out_rivalid_78 = _out_rifireMux_T_183; // @[RegisterRouter.scala:87:24] assign out_rivalid_79 = _out_rifireMux_T_183; // @[RegisterRouter.scala:87:24] assign out_rivalid_80 = _out_rifireMux_T_183; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_184 = ~_out_T_38; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_186 = _out_rifireMux_T_1 & out_frontSel_46; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_187 = _out_rifireMux_T_186 & _out_T_26; // @[RegisterRouter.scala:87:24] assign out_rivalid_59 = _out_rifireMux_T_187; // @[RegisterRouter.scala:87:24] assign out_rivalid_60 = _out_rifireMux_T_187; // @[RegisterRouter.scala:87:24] assign out_rivalid_61 = _out_rifireMux_T_187; // @[RegisterRouter.scala:87:24] assign out_rivalid_62 = _out_rifireMux_T_187; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_188 = ~_out_T_26; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_190 = _out_rifireMux_T_1 & out_frontSel_47; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_191 = _out_rifireMux_T_190 & _out_T_14; // @[RegisterRouter.scala:87:24] assign out_rivalid_25 = _out_rifireMux_T_191; // @[RegisterRouter.scala:87:24] assign out_rivalid_26 = _out_rifireMux_T_191; // @[RegisterRouter.scala:87:24] assign out_rivalid_27 = _out_rifireMux_T_191; // @[RegisterRouter.scala:87:24] assign out_rivalid_28 = _out_rifireMux_T_191; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_192 = ~_out_T_14; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_194 = _out_rifireMux_T_1 & out_frontSel_48; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_195 = _out_rifireMux_T_194; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_198 = _out_rifireMux_T_1 & out_frontSel_49; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_199 = _out_rifireMux_T_198; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_202 = _out_rifireMux_T_1 & out_frontSel_50; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_203 = _out_rifireMux_T_202; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_206 = _out_rifireMux_T_1 & out_frontSel_51; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_207 = _out_rifireMux_T_206; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_210 = _out_rifireMux_T_1 & out_frontSel_52; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_211 = _out_rifireMux_T_210; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_214 = _out_rifireMux_T_1 & out_frontSel_53; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_215 = _out_rifireMux_T_214; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_218 = _out_rifireMux_T_1 & out_frontSel_54; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_219 = _out_rifireMux_T_218; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_222 = _out_rifireMux_T_1 & out_frontSel_55; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_223 = _out_rifireMux_T_222; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_226 = _out_rifireMux_T_1 & out_frontSel_56; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_227 = _out_rifireMux_T_226 & _out_T_18; // @[RegisterRouter.scala:87:24] assign out_rivalid_33 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_rivalid_34 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_rivalid_35 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_rivalid_36 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_rivalid_37 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_rivalid_38 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_rivalid_39 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_rivalid_40 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_rivalid_41 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_rivalid_42 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_rivalid_43 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_rivalid_44 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_rivalid_45 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_rivalid_46 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_rivalid_47 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_228 = ~_out_T_18; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_230 = _out_rifireMux_T_1 & out_frontSel_57; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_231 = _out_rifireMux_T_230 & _out_T_28; // @[RegisterRouter.scala:87:24] assign out_rivalid_63 = _out_rifireMux_T_231; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_232 = ~_out_T_28; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_234 = _out_rifireMux_T_1 & out_frontSel_58; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_235 = _out_rifireMux_T_234; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_238 = _out_rifireMux_T_1 & out_frontSel_59; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_239 = _out_rifireMux_T_238; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_242 = _out_rifireMux_T_1 & out_frontSel_60; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_243 = _out_rifireMux_T_242 & _out_T_32; // @[RegisterRouter.scala:87:24] assign out_rivalid_68 = _out_rifireMux_T_243; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_244 = ~_out_T_32; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_246 = _out_rifireMux_T_1 & out_frontSel_61; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_247 = _out_rifireMux_T_246 & _out_T_2; // @[RegisterRouter.scala:87:24] assign out_rivalid_4 = _out_rifireMux_T_247; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_248 = ~_out_T_2; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_250 = _out_rifireMux_T_1 & out_frontSel_62; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_251 = _out_rifireMux_T_250; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_254 = _out_rifireMux_T_1 & out_frontSel_63; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_255 = _out_rifireMux_T_254; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_2 = _out_wifireMux_T & _out_wifireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_3 = _out_wifireMux_T_2 & out_frontSel_0; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_4 = _out_wifireMux_T_3 & _out_T_40; // @[RegisterRouter.scala:87:24] assign out_wivalid_81 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_5 = ~_out_T_40; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_7 = _out_wifireMux_T_2 & out_frontSel_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_8 = _out_wifireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_11 = _out_wifireMux_T_2 & out_frontSel_2; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_12 = _out_wifireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_15 = _out_wifireMux_T_2 & out_frontSel_3; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_16 = _out_wifireMux_T_15; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_19 = _out_wifireMux_T_2 & out_frontSel_4; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_20 = _out_wifireMux_T_19 & _out_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_21 = _out_wifireMux_T_20; // @[RegisterRouter.scala:87:24] assign out_wivalid_22 = _out_wifireMux_T_20; // @[RegisterRouter.scala:87:24] assign out_wivalid_23 = _out_wifireMux_T_20; // @[RegisterRouter.scala:87:24] assign out_wivalid_24 = _out_wifireMux_T_20; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_21 = ~_out_T_12; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_23 = _out_wifireMux_T_2 & out_frontSel_5; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_24 = _out_wifireMux_T_23 & _out_T; // @[RegisterRouter.scala:87:24] assign out_wivalid_0 = _out_wifireMux_T_24; // @[RegisterRouter.scala:87:24] assign out_wivalid_1 = _out_wifireMux_T_24; // @[RegisterRouter.scala:87:24] assign out_wivalid_2 = _out_wifireMux_T_24; // @[RegisterRouter.scala:87:24] assign out_wivalid_3 = _out_wifireMux_T_24; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_25 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_27 = _out_wifireMux_T_2 & out_frontSel_6; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_28 = _out_wifireMux_T_27 & _out_T_30; // @[RegisterRouter.scala:87:24] assign out_wivalid_64 = _out_wifireMux_T_28; // @[RegisterRouter.scala:87:24] assign out_wivalid_65 = _out_wifireMux_T_28; // @[RegisterRouter.scala:87:24] assign out_wivalid_66 = _out_wifireMux_T_28; // @[RegisterRouter.scala:87:24] assign out_wivalid_67 = _out_wifireMux_T_28; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_29 = ~_out_T_30; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_31 = _out_wifireMux_T_2 & out_frontSel_7; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_32 = _out_wifireMux_T_31 & _out_T_52; // @[RegisterRouter.scala:87:24] assign out_wivalid_120 = _out_wifireMux_T_32; // @[RegisterRouter.scala:87:24] assign out_wivalid_121 = _out_wifireMux_T_32; // @[RegisterRouter.scala:87:24] assign out_wivalid_122 = _out_wifireMux_T_32; // @[RegisterRouter.scala:87:24] assign out_wivalid_123 = _out_wifireMux_T_32; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_33 = ~_out_T_52; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_35 = _out_wifireMux_T_2 & out_frontSel_8; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_36 = _out_wifireMux_T_35 & _out_T_10; // @[RegisterRouter.scala:87:24] assign out_wivalid_17 = _out_wifireMux_T_36; // @[RegisterRouter.scala:87:24] assign out_wivalid_18 = _out_wifireMux_T_36; // @[RegisterRouter.scala:87:24] assign out_wivalid_19 = _out_wifireMux_T_36; // @[RegisterRouter.scala:87:24] assign out_wivalid_20 = _out_wifireMux_T_36; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_37 = ~_out_T_10; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_39 = _out_wifireMux_T_2 & out_frontSel_9; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_40 = _out_wifireMux_T_39 & _out_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_5 = _out_wifireMux_T_40; // @[RegisterRouter.scala:87:24] assign out_wivalid_6 = _out_wifireMux_T_40; // @[RegisterRouter.scala:87:24] assign out_wivalid_7 = _out_wifireMux_T_40; // @[RegisterRouter.scala:87:24] assign out_wivalid_8 = _out_wifireMux_T_40; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_41 = ~_out_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_43 = _out_wifireMux_T_2 & out_frontSel_10; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_44 = _out_wifireMux_T_43 & _out_T_16; // @[RegisterRouter.scala:87:24] assign out_wivalid_29 = _out_wifireMux_T_44; // @[RegisterRouter.scala:87:24] assign out_wivalid_30 = _out_wifireMux_T_44; // @[RegisterRouter.scala:87:24] assign out_wivalid_31 = _out_wifireMux_T_44; // @[RegisterRouter.scala:87:24] assign out_wivalid_32 = _out_wifireMux_T_44; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_45 = ~_out_T_16; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_47 = _out_wifireMux_T_2 & out_frontSel_11; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_48 = _out_wifireMux_T_47 & _out_T_56; // @[RegisterRouter.scala:87:24] assign out_wivalid_128 = _out_wifireMux_T_48; // @[RegisterRouter.scala:87:24] assign out_wivalid_129 = _out_wifireMux_T_48; // @[RegisterRouter.scala:87:24] assign out_wivalid_130 = _out_wifireMux_T_48; // @[RegisterRouter.scala:87:24] assign out_wivalid_131 = _out_wifireMux_T_48; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_49 = ~_out_T_56; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_51 = _out_wifireMux_T_2 & out_frontSel_12; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_52 = _out_wifireMux_T_51; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_55 = _out_wifireMux_T_2 & out_frontSel_13; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_56 = _out_wifireMux_T_55; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_59 = _out_wifireMux_T_2 & out_frontSel_14; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_60 = _out_wifireMux_T_59; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_63 = _out_wifireMux_T_2 & out_frontSel_15; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_64 = _out_wifireMux_T_63; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_67 = _out_wifireMux_T_2 & out_frontSel_16; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_68 = _out_wifireMux_T_67; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_71 = _out_wifireMux_T_2 & out_frontSel_17; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_72 = _out_wifireMux_T_71 & _out_T_42; // @[RegisterRouter.scala:87:24] assign out_wivalid_82 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_wivalid_83 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_wivalid_84 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_wivalid_85 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_wivalid_86 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_wivalid_87 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_wivalid_88 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_wivalid_89 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_wivalid_90 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_wivalid_91 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_wivalid_92 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_wivalid_93 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_wivalid_94 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_wivalid_95 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_wivalid_96 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_wivalid_97 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_wivalid_98 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_wivalid_99 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_wivalid_100 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_73 = ~_out_T_42; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_75 = _out_wifireMux_T_2 & out_frontSel_18; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_76 = _out_wifireMux_T_75; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_79 = _out_wifireMux_T_2 & out_frontSel_19; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_80 = _out_wifireMux_T_79 & _out_T_66; // @[RegisterRouter.scala:87:24] assign out_wivalid_145 = _out_wifireMux_T_80; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_81 = ~_out_T_66; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_83 = _out_wifireMux_T_2 & out_frontSel_20; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_84 = _out_wifireMux_T_83; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_87 = _out_wifireMux_T_2 & out_frontSel_21; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_88 = _out_wifireMux_T_87; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_91 = _out_wifireMux_T_2 & out_frontSel_22; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_92 = _out_wifireMux_T_91 & _out_T_48; // @[RegisterRouter.scala:87:24] assign out_wivalid_109 = _out_wifireMux_T_92; // @[RegisterRouter.scala:87:24] assign out_wivalid_110 = _out_wifireMux_T_92; // @[RegisterRouter.scala:87:24] assign out_wivalid_111 = _out_wifireMux_T_92; // @[RegisterRouter.scala:87:24] assign out_wivalid_112 = _out_wifireMux_T_92; // @[RegisterRouter.scala:87:24] assign out_wivalid_113 = _out_wifireMux_T_92; // @[RegisterRouter.scala:87:24] assign out_wivalid_114 = _out_wifireMux_T_92; // @[RegisterRouter.scala:87:24] assign out_wivalid_115 = _out_wifireMux_T_92; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_93 = ~_out_T_48; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_95 = _out_wifireMux_T_2 & out_frontSel_23; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_96 = _out_wifireMux_T_95 & _out_T_62; // @[RegisterRouter.scala:87:24] assign out_wivalid_140 = _out_wifireMux_T_96; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_97 = ~_out_T_62; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_99 = _out_wifireMux_T_2 & out_frontSel_24; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_100 = _out_wifireMux_T_99 & _out_T_22; // @[RegisterRouter.scala:87:24] assign out_wivalid_52 = _out_wifireMux_T_100; // @[RegisterRouter.scala:87:24] assign out_wivalid_53 = _out_wifireMux_T_100; // @[RegisterRouter.scala:87:24] assign out_wivalid_54 = _out_wifireMux_T_100; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_101 = ~_out_T_22; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_103 = _out_wifireMux_T_2 & out_frontSel_25; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_104 = _out_wifireMux_T_103; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_107 = _out_wifireMux_T_2 & out_frontSel_26; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_108 = _out_wifireMux_T_107; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_111 = _out_wifireMux_T_2 & out_frontSel_27; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_112 = _out_wifireMux_T_111; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_115 = _out_wifireMux_T_2 & out_frontSel_28; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_116 = _out_wifireMux_T_115; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_119 = _out_wifireMux_T_2 & out_frontSel_29; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_120 = _out_wifireMux_T_119; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_123 = _out_wifireMux_T_2 & out_frontSel_30; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_124 = _out_wifireMux_T_123; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_127 = _out_wifireMux_T_2 & out_frontSel_31; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_128 = _out_wifireMux_T_127; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_131 = _out_wifireMux_T_2 & out_frontSel_32; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_132 = _out_wifireMux_T_131 & _out_T_44; // @[RegisterRouter.scala:87:24] assign out_wivalid_101 = _out_wifireMux_T_132; // @[RegisterRouter.scala:87:24] assign out_wivalid_102 = _out_wifireMux_T_132; // @[RegisterRouter.scala:87:24] assign out_wivalid_103 = _out_wifireMux_T_132; // @[RegisterRouter.scala:87:24] assign out_wivalid_104 = _out_wifireMux_T_132; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_133 = ~_out_T_44; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_135 = _out_wifireMux_T_2 & out_frontSel_33; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_136 = _out_wifireMux_T_135 & _out_T_36; // @[RegisterRouter.scala:87:24] assign out_wivalid_73 = _out_wifireMux_T_136; // @[RegisterRouter.scala:87:24] assign out_wivalid_74 = _out_wifireMux_T_136; // @[RegisterRouter.scala:87:24] assign out_wivalid_75 = _out_wifireMux_T_136; // @[RegisterRouter.scala:87:24] assign out_wivalid_76 = _out_wifireMux_T_136; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_137 = ~_out_T_36; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_139 = _out_wifireMux_T_2 & out_frontSel_34; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_140 = _out_wifireMux_T_139 & _out_T_46; // @[RegisterRouter.scala:87:24] assign out_wivalid_105 = _out_wifireMux_T_140; // @[RegisterRouter.scala:87:24] assign out_wivalid_106 = _out_wifireMux_T_140; // @[RegisterRouter.scala:87:24] assign out_wivalid_107 = _out_wifireMux_T_140; // @[RegisterRouter.scala:87:24] assign out_wivalid_108 = _out_wifireMux_T_140; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_141 = ~_out_T_46; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_143 = _out_wifireMux_T_2 & out_frontSel_35; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_144 = _out_wifireMux_T_143 & _out_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_13 = _out_wifireMux_T_144; // @[RegisterRouter.scala:87:24] assign out_wivalid_14 = _out_wifireMux_T_144; // @[RegisterRouter.scala:87:24] assign out_wivalid_15 = _out_wifireMux_T_144; // @[RegisterRouter.scala:87:24] assign out_wivalid_16 = _out_wifireMux_T_144; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_145 = ~_out_T_8; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_147 = _out_wifireMux_T_2 & out_frontSel_36; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_148 = _out_wifireMux_T_147 & _out_T_64; // @[RegisterRouter.scala:87:24] assign out_wivalid_141 = _out_wifireMux_T_148; // @[RegisterRouter.scala:87:24] assign out_wivalid_142 = _out_wifireMux_T_148; // @[RegisterRouter.scala:87:24] assign out_wivalid_143 = _out_wifireMux_T_148; // @[RegisterRouter.scala:87:24] assign out_wivalid_144 = _out_wifireMux_T_148; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_149 = ~_out_T_64; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_151 = _out_wifireMux_T_2 & out_frontSel_37; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_152 = _out_wifireMux_T_151 & _out_T_24; // @[RegisterRouter.scala:87:24] assign out_wivalid_55 = _out_wifireMux_T_152; // @[RegisterRouter.scala:87:24] assign out_wivalid_56 = _out_wifireMux_T_152; // @[RegisterRouter.scala:87:24] assign out_wivalid_57 = _out_wifireMux_T_152; // @[RegisterRouter.scala:87:24] assign out_wivalid_58 = _out_wifireMux_T_152; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_153 = ~_out_T_24; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_155 = _out_wifireMux_T_2 & out_frontSel_38; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_156 = _out_wifireMux_T_155 & _out_T_34; // @[RegisterRouter.scala:87:24] assign out_wivalid_69 = _out_wifireMux_T_156; // @[RegisterRouter.scala:87:24] assign out_wivalid_70 = _out_wifireMux_T_156; // @[RegisterRouter.scala:87:24] assign out_wivalid_71 = _out_wifireMux_T_156; // @[RegisterRouter.scala:87:24] assign out_wivalid_72 = _out_wifireMux_T_156; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_157 = ~_out_T_34; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_159 = _out_wifireMux_T_2 & out_frontSel_39; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_160 = _out_wifireMux_T_159 & _out_T_54; // @[RegisterRouter.scala:87:24] assign out_wivalid_124 = _out_wifireMux_T_160; // @[RegisterRouter.scala:87:24] assign out_wivalid_125 = _out_wifireMux_T_160; // @[RegisterRouter.scala:87:24] assign out_wivalid_126 = _out_wifireMux_T_160; // @[RegisterRouter.scala:87:24] assign out_wivalid_127 = _out_wifireMux_T_160; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_161 = ~_out_T_54; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_163 = _out_wifireMux_T_2 & out_frontSel_40; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_164 = _out_wifireMux_T_163 & _out_T_60; // @[RegisterRouter.scala:87:24] assign out_wivalid_136 = _out_wifireMux_T_164; // @[RegisterRouter.scala:87:24] assign out_wivalid_137 = _out_wifireMux_T_164; // @[RegisterRouter.scala:87:24] assign out_wivalid_138 = _out_wifireMux_T_164; // @[RegisterRouter.scala:87:24] assign out_wivalid_139 = _out_wifireMux_T_164; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_165 = ~_out_T_60; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_167 = _out_wifireMux_T_2 & out_frontSel_41; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_168 = _out_wifireMux_T_167 & _out_T_6; // @[RegisterRouter.scala:87:24] assign out_wivalid_9 = _out_wifireMux_T_168; // @[RegisterRouter.scala:87:24] assign out_wivalid_10 = _out_wifireMux_T_168; // @[RegisterRouter.scala:87:24] assign out_wivalid_11 = _out_wifireMux_T_168; // @[RegisterRouter.scala:87:24] assign out_wivalid_12 = _out_wifireMux_T_168; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_169 = ~_out_T_6; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_171 = _out_wifireMux_T_2 & out_frontSel_42; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_172 = _out_wifireMux_T_171 & _out_T_20; // @[RegisterRouter.scala:87:24] assign out_wivalid_48 = _out_wifireMux_T_172; // @[RegisterRouter.scala:87:24] assign out_wivalid_49 = _out_wifireMux_T_172; // @[RegisterRouter.scala:87:24] assign out_wivalid_50 = _out_wifireMux_T_172; // @[RegisterRouter.scala:87:24] assign out_wivalid_51 = _out_wifireMux_T_172; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_173 = ~_out_T_20; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_175 = _out_wifireMux_T_2 & out_frontSel_43; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_176 = _out_wifireMux_T_175 & _out_T_58; // @[RegisterRouter.scala:87:24] assign out_wivalid_132 = _out_wifireMux_T_176; // @[RegisterRouter.scala:87:24] assign out_wivalid_133 = _out_wifireMux_T_176; // @[RegisterRouter.scala:87:24] assign out_wivalid_134 = _out_wifireMux_T_176; // @[RegisterRouter.scala:87:24] assign out_wivalid_135 = _out_wifireMux_T_176; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_177 = ~_out_T_58; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_179 = _out_wifireMux_T_2 & out_frontSel_44; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_180 = _out_wifireMux_T_179 & _out_T_50; // @[RegisterRouter.scala:87:24] assign out_wivalid_116 = _out_wifireMux_T_180; // @[RegisterRouter.scala:87:24] assign out_wivalid_117 = _out_wifireMux_T_180; // @[RegisterRouter.scala:87:24] assign out_wivalid_118 = _out_wifireMux_T_180; // @[RegisterRouter.scala:87:24] assign out_wivalid_119 = _out_wifireMux_T_180; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_181 = ~_out_T_50; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_183 = _out_wifireMux_T_2 & out_frontSel_45; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_184 = _out_wifireMux_T_183 & _out_T_38; // @[RegisterRouter.scala:87:24] assign out_wivalid_77 = _out_wifireMux_T_184; // @[RegisterRouter.scala:87:24] assign out_wivalid_78 = _out_wifireMux_T_184; // @[RegisterRouter.scala:87:24] assign out_wivalid_79 = _out_wifireMux_T_184; // @[RegisterRouter.scala:87:24] assign out_wivalid_80 = _out_wifireMux_T_184; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_185 = ~_out_T_38; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_187 = _out_wifireMux_T_2 & out_frontSel_46; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_188 = _out_wifireMux_T_187 & _out_T_26; // @[RegisterRouter.scala:87:24] assign out_wivalid_59 = _out_wifireMux_T_188; // @[RegisterRouter.scala:87:24] assign out_wivalid_60 = _out_wifireMux_T_188; // @[RegisterRouter.scala:87:24] assign out_wivalid_61 = _out_wifireMux_T_188; // @[RegisterRouter.scala:87:24] assign out_wivalid_62 = _out_wifireMux_T_188; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_189 = ~_out_T_26; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_191 = _out_wifireMux_T_2 & out_frontSel_47; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_192 = _out_wifireMux_T_191 & _out_T_14; // @[RegisterRouter.scala:87:24] assign out_wivalid_25 = _out_wifireMux_T_192; // @[RegisterRouter.scala:87:24] assign out_wivalid_26 = _out_wifireMux_T_192; // @[RegisterRouter.scala:87:24] assign out_wivalid_27 = _out_wifireMux_T_192; // @[RegisterRouter.scala:87:24] assign out_wivalid_28 = _out_wifireMux_T_192; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_193 = ~_out_T_14; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_195 = _out_wifireMux_T_2 & out_frontSel_48; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_196 = _out_wifireMux_T_195; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_199 = _out_wifireMux_T_2 & out_frontSel_49; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_200 = _out_wifireMux_T_199; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_203 = _out_wifireMux_T_2 & out_frontSel_50; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_204 = _out_wifireMux_T_203; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_207 = _out_wifireMux_T_2 & out_frontSel_51; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_208 = _out_wifireMux_T_207; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_211 = _out_wifireMux_T_2 & out_frontSel_52; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_212 = _out_wifireMux_T_211; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_215 = _out_wifireMux_T_2 & out_frontSel_53; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_216 = _out_wifireMux_T_215; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_219 = _out_wifireMux_T_2 & out_frontSel_54; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_220 = _out_wifireMux_T_219; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_223 = _out_wifireMux_T_2 & out_frontSel_55; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_224 = _out_wifireMux_T_223; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_227 = _out_wifireMux_T_2 & out_frontSel_56; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_228 = _out_wifireMux_T_227 & _out_T_18; // @[RegisterRouter.scala:87:24] assign out_wivalid_33 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_wivalid_34 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_wivalid_35 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_wivalid_36 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_wivalid_37 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_wivalid_38 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_wivalid_39 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_wivalid_40 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_wivalid_41 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_wivalid_42 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_wivalid_43 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_wivalid_44 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_wivalid_45 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_wivalid_46 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_wivalid_47 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_229 = ~_out_T_18; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_231 = _out_wifireMux_T_2 & out_frontSel_57; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_232 = _out_wifireMux_T_231 & _out_T_28; // @[RegisterRouter.scala:87:24] assign out_wivalid_63 = _out_wifireMux_T_232; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_233 = ~_out_T_28; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_235 = _out_wifireMux_T_2 & out_frontSel_58; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_236 = _out_wifireMux_T_235; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_239 = _out_wifireMux_T_2 & out_frontSel_59; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_240 = _out_wifireMux_T_239; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_243 = _out_wifireMux_T_2 & out_frontSel_60; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_244 = _out_wifireMux_T_243 & _out_T_32; // @[RegisterRouter.scala:87:24] assign out_wivalid_68 = _out_wifireMux_T_244; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_245 = ~_out_T_32; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_247 = _out_wifireMux_T_2 & out_frontSel_61; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_248 = _out_wifireMux_T_247 & _out_T_2; // @[RegisterRouter.scala:87:24] assign out_wivalid_4 = _out_wifireMux_T_248; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_249 = ~_out_T_2; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_251 = _out_wifireMux_T_2 & out_frontSel_62; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_252 = _out_wifireMux_T_251; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_255 = _out_wifireMux_T_2 & out_frontSel_63; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_256 = _out_wifireMux_T_255; // @[RegisterRouter.scala:87:24] wire _GEN_12 = out_front_valid & out_ready; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T = _GEN_12; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T = _GEN_12; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1 = _out_rofireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_2 = _out_rofireMux_T_1 & out_backSel_0; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_3 = _out_rofireMux_T_2 & _out_T_41; // @[RegisterRouter.scala:87:24] assign out_roready_81 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_4 = ~_out_T_41; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_6 = _out_rofireMux_T_1 & out_backSel_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_7 = _out_rofireMux_T_6; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_10 = _out_rofireMux_T_1 & out_backSel_2; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_11 = _out_rofireMux_T_10; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_14 = _out_rofireMux_T_1 & out_backSel_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_15 = _out_rofireMux_T_14; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_18 = _out_rofireMux_T_1 & out_backSel_4; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_19 = _out_rofireMux_T_18 & _out_T_13; // @[RegisterRouter.scala:87:24] assign out_roready_21 = _out_rofireMux_T_19; // @[RegisterRouter.scala:87:24] assign out_roready_22 = _out_rofireMux_T_19; // @[RegisterRouter.scala:87:24] assign out_roready_23 = _out_rofireMux_T_19; // @[RegisterRouter.scala:87:24] assign out_roready_24 = _out_rofireMux_T_19; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_20 = ~_out_T_13; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_22 = _out_rofireMux_T_1 & out_backSel_5; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_23 = _out_rofireMux_T_22 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_roready_0 = _out_rofireMux_T_23; // @[RegisterRouter.scala:87:24] assign out_roready_1 = _out_rofireMux_T_23; // @[RegisterRouter.scala:87:24] assign out_roready_2 = _out_rofireMux_T_23; // @[RegisterRouter.scala:87:24] assign out_roready_3 = _out_rofireMux_T_23; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_24 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_26 = _out_rofireMux_T_1 & out_backSel_6; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_27 = _out_rofireMux_T_26 & _out_T_31; // @[RegisterRouter.scala:87:24] assign out_roready_64 = _out_rofireMux_T_27; // @[RegisterRouter.scala:87:24] assign out_roready_65 = _out_rofireMux_T_27; // @[RegisterRouter.scala:87:24] assign out_roready_66 = _out_rofireMux_T_27; // @[RegisterRouter.scala:87:24] assign out_roready_67 = _out_rofireMux_T_27; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_28 = ~_out_T_31; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_30 = _out_rofireMux_T_1 & out_backSel_7; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_31 = _out_rofireMux_T_30 & _out_T_53; // @[RegisterRouter.scala:87:24] assign out_roready_120 = _out_rofireMux_T_31; // @[RegisterRouter.scala:87:24] assign out_roready_121 = _out_rofireMux_T_31; // @[RegisterRouter.scala:87:24] assign out_roready_122 = _out_rofireMux_T_31; // @[RegisterRouter.scala:87:24] assign out_roready_123 = _out_rofireMux_T_31; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_32 = ~_out_T_53; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_34 = _out_rofireMux_T_1 & out_backSel_8; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_35 = _out_rofireMux_T_34 & _out_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_17 = _out_rofireMux_T_35; // @[RegisterRouter.scala:87:24] assign out_roready_18 = _out_rofireMux_T_35; // @[RegisterRouter.scala:87:24] assign out_roready_19 = _out_rofireMux_T_35; // @[RegisterRouter.scala:87:24] assign out_roready_20 = _out_rofireMux_T_35; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_36 = ~_out_T_11; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_38 = _out_rofireMux_T_1 & out_backSel_9; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_39 = _out_rofireMux_T_38 & _out_T_5; // @[RegisterRouter.scala:87:24] assign out_roready_5 = _out_rofireMux_T_39; // @[RegisterRouter.scala:87:24] assign out_roready_6 = _out_rofireMux_T_39; // @[RegisterRouter.scala:87:24] assign out_roready_7 = _out_rofireMux_T_39; // @[RegisterRouter.scala:87:24] assign out_roready_8 = _out_rofireMux_T_39; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_40 = ~_out_T_5; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_42 = _out_rofireMux_T_1 & out_backSel_10; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_43 = _out_rofireMux_T_42 & _out_T_17; // @[RegisterRouter.scala:87:24] assign out_roready_29 = _out_rofireMux_T_43; // @[RegisterRouter.scala:87:24] assign out_roready_30 = _out_rofireMux_T_43; // @[RegisterRouter.scala:87:24] assign out_roready_31 = _out_rofireMux_T_43; // @[RegisterRouter.scala:87:24] assign out_roready_32 = _out_rofireMux_T_43; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_44 = ~_out_T_17; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_46 = _out_rofireMux_T_1 & out_backSel_11; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_47 = _out_rofireMux_T_46 & _out_T_57; // @[RegisterRouter.scala:87:24] assign out_roready_128 = _out_rofireMux_T_47; // @[RegisterRouter.scala:87:24] assign out_roready_129 = _out_rofireMux_T_47; // @[RegisterRouter.scala:87:24] assign out_roready_130 = _out_rofireMux_T_47; // @[RegisterRouter.scala:87:24] assign out_roready_131 = _out_rofireMux_T_47; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_48 = ~_out_T_57; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_50 = _out_rofireMux_T_1 & out_backSel_12; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_51 = _out_rofireMux_T_50; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_54 = _out_rofireMux_T_1 & out_backSel_13; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_55 = _out_rofireMux_T_54; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_58 = _out_rofireMux_T_1 & out_backSel_14; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_59 = _out_rofireMux_T_58; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_62 = _out_rofireMux_T_1 & out_backSel_15; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_63 = _out_rofireMux_T_62; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_66 = _out_rofireMux_T_1 & out_backSel_16; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_67 = _out_rofireMux_T_66; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_70 = _out_rofireMux_T_1 & out_backSel_17; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_71 = _out_rofireMux_T_70 & _out_T_43; // @[RegisterRouter.scala:87:24] assign out_roready_82 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_roready_83 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_roready_84 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_roready_85 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_roready_86 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_roready_87 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_roready_88 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_roready_89 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_roready_90 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_roready_91 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_roready_92 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_roready_93 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_roready_94 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_roready_95 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_roready_96 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_roready_97 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_roready_98 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_roready_99 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_roready_100 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_72 = ~_out_T_43; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_74 = _out_rofireMux_T_1 & out_backSel_18; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_75 = _out_rofireMux_T_74; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_78 = _out_rofireMux_T_1 & out_backSel_19; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_79 = _out_rofireMux_T_78 & _out_T_67; // @[RegisterRouter.scala:87:24] assign out_roready_145 = _out_rofireMux_T_79; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_80 = ~_out_T_67; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_82 = _out_rofireMux_T_1 & out_backSel_20; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_83 = _out_rofireMux_T_82; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_86 = _out_rofireMux_T_1 & out_backSel_21; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_87 = _out_rofireMux_T_86; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_90 = _out_rofireMux_T_1 & out_backSel_22; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_91 = _out_rofireMux_T_90 & _out_T_49; // @[RegisterRouter.scala:87:24] assign out_roready_109 = _out_rofireMux_T_91; // @[RegisterRouter.scala:87:24] assign out_roready_110 = _out_rofireMux_T_91; // @[RegisterRouter.scala:87:24] assign out_roready_111 = _out_rofireMux_T_91; // @[RegisterRouter.scala:87:24] assign out_roready_112 = _out_rofireMux_T_91; // @[RegisterRouter.scala:87:24] assign out_roready_113 = _out_rofireMux_T_91; // @[RegisterRouter.scala:87:24] assign out_roready_114 = _out_rofireMux_T_91; // @[RegisterRouter.scala:87:24] assign out_roready_115 = _out_rofireMux_T_91; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_92 = ~_out_T_49; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_94 = _out_rofireMux_T_1 & out_backSel_23; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_95 = _out_rofireMux_T_94 & _out_T_63; // @[RegisterRouter.scala:87:24] assign out_roready_140 = _out_rofireMux_T_95; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_96 = ~_out_T_63; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_98 = _out_rofireMux_T_1 & out_backSel_24; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_99 = _out_rofireMux_T_98 & _out_T_23; // @[RegisterRouter.scala:87:24] assign out_roready_52 = _out_rofireMux_T_99; // @[RegisterRouter.scala:87:24] assign out_roready_53 = _out_rofireMux_T_99; // @[RegisterRouter.scala:87:24] assign out_roready_54 = _out_rofireMux_T_99; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_100 = ~_out_T_23; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_102 = _out_rofireMux_T_1 & out_backSel_25; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_103 = _out_rofireMux_T_102; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_106 = _out_rofireMux_T_1 & out_backSel_26; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_107 = _out_rofireMux_T_106; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_110 = _out_rofireMux_T_1 & out_backSel_27; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_111 = _out_rofireMux_T_110; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_114 = _out_rofireMux_T_1 & out_backSel_28; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_115 = _out_rofireMux_T_114; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_118 = _out_rofireMux_T_1 & out_backSel_29; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_119 = _out_rofireMux_T_118; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_122 = _out_rofireMux_T_1 & out_backSel_30; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_123 = _out_rofireMux_T_122; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_126 = _out_rofireMux_T_1 & out_backSel_31; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_127 = _out_rofireMux_T_126; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_130 = _out_rofireMux_T_1 & out_backSel_32; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_131 = _out_rofireMux_T_130 & _out_T_45; // @[RegisterRouter.scala:87:24] assign out_roready_101 = _out_rofireMux_T_131; // @[RegisterRouter.scala:87:24] assign out_roready_102 = _out_rofireMux_T_131; // @[RegisterRouter.scala:87:24] assign out_roready_103 = _out_rofireMux_T_131; // @[RegisterRouter.scala:87:24] assign out_roready_104 = _out_rofireMux_T_131; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_132 = ~_out_T_45; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_134 = _out_rofireMux_T_1 & out_backSel_33; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_135 = _out_rofireMux_T_134 & _out_T_37; // @[RegisterRouter.scala:87:24] assign out_roready_73 = _out_rofireMux_T_135; // @[RegisterRouter.scala:87:24] assign out_roready_74 = _out_rofireMux_T_135; // @[RegisterRouter.scala:87:24] assign out_roready_75 = _out_rofireMux_T_135; // @[RegisterRouter.scala:87:24] assign out_roready_76 = _out_rofireMux_T_135; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_136 = ~_out_T_37; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_138 = _out_rofireMux_T_1 & out_backSel_34; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_139 = _out_rofireMux_T_138 & _out_T_47; // @[RegisterRouter.scala:87:24] assign out_roready_105 = _out_rofireMux_T_139; // @[RegisterRouter.scala:87:24] assign out_roready_106 = _out_rofireMux_T_139; // @[RegisterRouter.scala:87:24] assign out_roready_107 = _out_rofireMux_T_139; // @[RegisterRouter.scala:87:24] assign out_roready_108 = _out_rofireMux_T_139; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_140 = ~_out_T_47; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_142 = _out_rofireMux_T_1 & out_backSel_35; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_143 = _out_rofireMux_T_142 & _out_T_9; // @[RegisterRouter.scala:87:24] assign out_roready_13 = _out_rofireMux_T_143; // @[RegisterRouter.scala:87:24] assign out_roready_14 = _out_rofireMux_T_143; // @[RegisterRouter.scala:87:24] assign out_roready_15 = _out_rofireMux_T_143; // @[RegisterRouter.scala:87:24] assign out_roready_16 = _out_rofireMux_T_143; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_144 = ~_out_T_9; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_146 = _out_rofireMux_T_1 & out_backSel_36; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_147 = _out_rofireMux_T_146 & _out_T_65; // @[RegisterRouter.scala:87:24] assign out_roready_141 = _out_rofireMux_T_147; // @[RegisterRouter.scala:87:24] assign out_roready_142 = _out_rofireMux_T_147; // @[RegisterRouter.scala:87:24] assign out_roready_143 = _out_rofireMux_T_147; // @[RegisterRouter.scala:87:24] assign out_roready_144 = _out_rofireMux_T_147; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_148 = ~_out_T_65; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_150 = _out_rofireMux_T_1 & out_backSel_37; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_151 = _out_rofireMux_T_150 & _out_T_25; // @[RegisterRouter.scala:87:24] assign out_roready_55 = _out_rofireMux_T_151; // @[RegisterRouter.scala:87:24] assign out_roready_56 = _out_rofireMux_T_151; // @[RegisterRouter.scala:87:24] assign out_roready_57 = _out_rofireMux_T_151; // @[RegisterRouter.scala:87:24] assign out_roready_58 = _out_rofireMux_T_151; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_152 = ~_out_T_25; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_154 = _out_rofireMux_T_1 & out_backSel_38; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_155 = _out_rofireMux_T_154 & _out_T_35; // @[RegisterRouter.scala:87:24] assign out_roready_69 = _out_rofireMux_T_155; // @[RegisterRouter.scala:87:24] assign out_roready_70 = _out_rofireMux_T_155; // @[RegisterRouter.scala:87:24] assign out_roready_71 = _out_rofireMux_T_155; // @[RegisterRouter.scala:87:24] assign out_roready_72 = _out_rofireMux_T_155; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_156 = ~_out_T_35; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_158 = _out_rofireMux_T_1 & out_backSel_39; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_159 = _out_rofireMux_T_158 & _out_T_55; // @[RegisterRouter.scala:87:24] assign out_roready_124 = _out_rofireMux_T_159; // @[RegisterRouter.scala:87:24] assign out_roready_125 = _out_rofireMux_T_159; // @[RegisterRouter.scala:87:24] assign out_roready_126 = _out_rofireMux_T_159; // @[RegisterRouter.scala:87:24] assign out_roready_127 = _out_rofireMux_T_159; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_160 = ~_out_T_55; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_162 = _out_rofireMux_T_1 & out_backSel_40; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_163 = _out_rofireMux_T_162 & _out_T_61; // @[RegisterRouter.scala:87:24] assign out_roready_136 = _out_rofireMux_T_163; // @[RegisterRouter.scala:87:24] assign out_roready_137 = _out_rofireMux_T_163; // @[RegisterRouter.scala:87:24] assign out_roready_138 = _out_rofireMux_T_163; // @[RegisterRouter.scala:87:24] assign out_roready_139 = _out_rofireMux_T_163; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_164 = ~_out_T_61; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_166 = _out_rofireMux_T_1 & out_backSel_41; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_167 = _out_rofireMux_T_166 & _out_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_9 = _out_rofireMux_T_167; // @[RegisterRouter.scala:87:24] assign out_roready_10 = _out_rofireMux_T_167; // @[RegisterRouter.scala:87:24] assign out_roready_11 = _out_rofireMux_T_167; // @[RegisterRouter.scala:87:24] assign out_roready_12 = _out_rofireMux_T_167; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_168 = ~_out_T_7; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_170 = _out_rofireMux_T_1 & out_backSel_42; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_171 = _out_rofireMux_T_170 & _out_T_21; // @[RegisterRouter.scala:87:24] assign out_roready_48 = _out_rofireMux_T_171; // @[RegisterRouter.scala:87:24] assign out_roready_49 = _out_rofireMux_T_171; // @[RegisterRouter.scala:87:24] assign out_roready_50 = _out_rofireMux_T_171; // @[RegisterRouter.scala:87:24] assign out_roready_51 = _out_rofireMux_T_171; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_172 = ~_out_T_21; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_174 = _out_rofireMux_T_1 & out_backSel_43; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_175 = _out_rofireMux_T_174 & _out_T_59; // @[RegisterRouter.scala:87:24] assign out_roready_132 = _out_rofireMux_T_175; // @[RegisterRouter.scala:87:24] assign out_roready_133 = _out_rofireMux_T_175; // @[RegisterRouter.scala:87:24] assign out_roready_134 = _out_rofireMux_T_175; // @[RegisterRouter.scala:87:24] assign out_roready_135 = _out_rofireMux_T_175; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_176 = ~_out_T_59; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_178 = _out_rofireMux_T_1 & out_backSel_44; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_179 = _out_rofireMux_T_178 & _out_T_51; // @[RegisterRouter.scala:87:24] assign out_roready_116 = _out_rofireMux_T_179; // @[RegisterRouter.scala:87:24] assign out_roready_117 = _out_rofireMux_T_179; // @[RegisterRouter.scala:87:24] assign out_roready_118 = _out_rofireMux_T_179; // @[RegisterRouter.scala:87:24] assign out_roready_119 = _out_rofireMux_T_179; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_180 = ~_out_T_51; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_182 = _out_rofireMux_T_1 & out_backSel_45; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_183 = _out_rofireMux_T_182 & _out_T_39; // @[RegisterRouter.scala:87:24] assign out_roready_77 = _out_rofireMux_T_183; // @[RegisterRouter.scala:87:24] assign out_roready_78 = _out_rofireMux_T_183; // @[RegisterRouter.scala:87:24] assign out_roready_79 = _out_rofireMux_T_183; // @[RegisterRouter.scala:87:24] assign out_roready_80 = _out_rofireMux_T_183; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_184 = ~_out_T_39; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_186 = _out_rofireMux_T_1 & out_backSel_46; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_187 = _out_rofireMux_T_186 & _out_T_27; // @[RegisterRouter.scala:87:24] assign out_roready_59 = _out_rofireMux_T_187; // @[RegisterRouter.scala:87:24] assign out_roready_60 = _out_rofireMux_T_187; // @[RegisterRouter.scala:87:24] assign out_roready_61 = _out_rofireMux_T_187; // @[RegisterRouter.scala:87:24] assign out_roready_62 = _out_rofireMux_T_187; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_188 = ~_out_T_27; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_190 = _out_rofireMux_T_1 & out_backSel_47; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_191 = _out_rofireMux_T_190 & _out_T_15; // @[RegisterRouter.scala:87:24] assign out_roready_25 = _out_rofireMux_T_191; // @[RegisterRouter.scala:87:24] assign out_roready_26 = _out_rofireMux_T_191; // @[RegisterRouter.scala:87:24] assign out_roready_27 = _out_rofireMux_T_191; // @[RegisterRouter.scala:87:24] assign out_roready_28 = _out_rofireMux_T_191; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_192 = ~_out_T_15; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_194 = _out_rofireMux_T_1 & out_backSel_48; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_195 = _out_rofireMux_T_194; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_198 = _out_rofireMux_T_1 & out_backSel_49; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_199 = _out_rofireMux_T_198; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_202 = _out_rofireMux_T_1 & out_backSel_50; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_203 = _out_rofireMux_T_202; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_206 = _out_rofireMux_T_1 & out_backSel_51; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_207 = _out_rofireMux_T_206; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_210 = _out_rofireMux_T_1 & out_backSel_52; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_211 = _out_rofireMux_T_210; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_214 = _out_rofireMux_T_1 & out_backSel_53; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_215 = _out_rofireMux_T_214; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_218 = _out_rofireMux_T_1 & out_backSel_54; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_219 = _out_rofireMux_T_218; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_222 = _out_rofireMux_T_1 & out_backSel_55; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_223 = _out_rofireMux_T_222; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_226 = _out_rofireMux_T_1 & out_backSel_56; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_227 = _out_rofireMux_T_226 & _out_T_19; // @[RegisterRouter.scala:87:24] assign out_roready_33 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_roready_34 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_roready_35 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_roready_36 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_roready_37 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_roready_38 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_roready_39 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_roready_40 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_roready_41 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_roready_42 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_roready_43 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_roready_44 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_roready_45 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_roready_46 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_roready_47 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_228 = ~_out_T_19; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_230 = _out_rofireMux_T_1 & out_backSel_57; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_231 = _out_rofireMux_T_230 & _out_T_29; // @[RegisterRouter.scala:87:24] assign out_roready_63 = _out_rofireMux_T_231; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_232 = ~_out_T_29; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_234 = _out_rofireMux_T_1 & out_backSel_58; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_235 = _out_rofireMux_T_234; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_238 = _out_rofireMux_T_1 & out_backSel_59; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_239 = _out_rofireMux_T_238; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_242 = _out_rofireMux_T_1 & out_backSel_60; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_243 = _out_rofireMux_T_242 & _out_T_33; // @[RegisterRouter.scala:87:24] assign out_roready_68 = _out_rofireMux_T_243; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_244 = ~_out_T_33; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_246 = _out_rofireMux_T_1 & out_backSel_61; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_247 = _out_rofireMux_T_246 & _out_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_4 = _out_rofireMux_T_247; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_248 = ~_out_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_250 = _out_rofireMux_T_1 & out_backSel_62; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_251 = _out_rofireMux_T_250; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_254 = _out_rofireMux_T_1 & out_backSel_63; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_255 = _out_rofireMux_T_254; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_2 = _out_wofireMux_T & _out_wofireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_3 = _out_wofireMux_T_2 & out_backSel_0; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_4 = _out_wofireMux_T_3 & _out_T_41; // @[RegisterRouter.scala:87:24] assign out_woready_81 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_5 = ~_out_T_41; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_7 = _out_wofireMux_T_2 & out_backSel_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_8 = _out_wofireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_11 = _out_wofireMux_T_2 & out_backSel_2; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_12 = _out_wofireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_15 = _out_wofireMux_T_2 & out_backSel_3; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_16 = _out_wofireMux_T_15; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_19 = _out_wofireMux_T_2 & out_backSel_4; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_20 = _out_wofireMux_T_19 & _out_T_13; // @[RegisterRouter.scala:87:24] assign out_woready_21 = _out_wofireMux_T_20; // @[RegisterRouter.scala:87:24] assign out_woready_22 = _out_wofireMux_T_20; // @[RegisterRouter.scala:87:24] assign out_woready_23 = _out_wofireMux_T_20; // @[RegisterRouter.scala:87:24] assign out_woready_24 = _out_wofireMux_T_20; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_21 = ~_out_T_13; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_23 = _out_wofireMux_T_2 & out_backSel_5; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_24 = _out_wofireMux_T_23 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_woready_0 = _out_wofireMux_T_24; // @[RegisterRouter.scala:87:24] assign out_woready_1 = _out_wofireMux_T_24; // @[RegisterRouter.scala:87:24] assign out_woready_2 = _out_wofireMux_T_24; // @[RegisterRouter.scala:87:24] assign out_woready_3 = _out_wofireMux_T_24; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_25 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_27 = _out_wofireMux_T_2 & out_backSel_6; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_28 = _out_wofireMux_T_27 & _out_T_31; // @[RegisterRouter.scala:87:24] assign out_woready_64 = _out_wofireMux_T_28; // @[RegisterRouter.scala:87:24] assign out_woready_65 = _out_wofireMux_T_28; // @[RegisterRouter.scala:87:24] assign out_woready_66 = _out_wofireMux_T_28; // @[RegisterRouter.scala:87:24] assign out_woready_67 = _out_wofireMux_T_28; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_29 = ~_out_T_31; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_31 = _out_wofireMux_T_2 & out_backSel_7; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_32 = _out_wofireMux_T_31 & _out_T_53; // @[RegisterRouter.scala:87:24] assign out_woready_120 = _out_wofireMux_T_32; // @[RegisterRouter.scala:87:24] assign out_woready_121 = _out_wofireMux_T_32; // @[RegisterRouter.scala:87:24] assign out_woready_122 = _out_wofireMux_T_32; // @[RegisterRouter.scala:87:24] assign out_woready_123 = _out_wofireMux_T_32; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_33 = ~_out_T_53; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_35 = _out_wofireMux_T_2 & out_backSel_8; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_36 = _out_wofireMux_T_35 & _out_T_11; // @[RegisterRouter.scala:87:24] assign out_woready_17 = _out_wofireMux_T_36; // @[RegisterRouter.scala:87:24] assign out_woready_18 = _out_wofireMux_T_36; // @[RegisterRouter.scala:87:24] assign out_woready_19 = _out_wofireMux_T_36; // @[RegisterRouter.scala:87:24] assign out_woready_20 = _out_wofireMux_T_36; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_37 = ~_out_T_11; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_39 = _out_wofireMux_T_2 & out_backSel_9; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_40 = _out_wofireMux_T_39 & _out_T_5; // @[RegisterRouter.scala:87:24] assign out_woready_5 = _out_wofireMux_T_40; // @[RegisterRouter.scala:87:24] assign out_woready_6 = _out_wofireMux_T_40; // @[RegisterRouter.scala:87:24] assign out_woready_7 = _out_wofireMux_T_40; // @[RegisterRouter.scala:87:24] assign out_woready_8 = _out_wofireMux_T_40; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_41 = ~_out_T_5; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_43 = _out_wofireMux_T_2 & out_backSel_10; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_44 = _out_wofireMux_T_43 & _out_T_17; // @[RegisterRouter.scala:87:24] assign out_woready_29 = _out_wofireMux_T_44; // @[RegisterRouter.scala:87:24] assign out_woready_30 = _out_wofireMux_T_44; // @[RegisterRouter.scala:87:24] assign out_woready_31 = _out_wofireMux_T_44; // @[RegisterRouter.scala:87:24] assign out_woready_32 = _out_wofireMux_T_44; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_45 = ~_out_T_17; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_47 = _out_wofireMux_T_2 & out_backSel_11; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_48 = _out_wofireMux_T_47 & _out_T_57; // @[RegisterRouter.scala:87:24] assign out_woready_128 = _out_wofireMux_T_48; // @[RegisterRouter.scala:87:24] assign out_woready_129 = _out_wofireMux_T_48; // @[RegisterRouter.scala:87:24] assign out_woready_130 = _out_wofireMux_T_48; // @[RegisterRouter.scala:87:24] assign out_woready_131 = _out_wofireMux_T_48; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_49 = ~_out_T_57; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_51 = _out_wofireMux_T_2 & out_backSel_12; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_52 = _out_wofireMux_T_51; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_55 = _out_wofireMux_T_2 & out_backSel_13; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_56 = _out_wofireMux_T_55; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_59 = _out_wofireMux_T_2 & out_backSel_14; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_60 = _out_wofireMux_T_59; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_63 = _out_wofireMux_T_2 & out_backSel_15; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_64 = _out_wofireMux_T_63; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_67 = _out_wofireMux_T_2 & out_backSel_16; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_68 = _out_wofireMux_T_67; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_71 = _out_wofireMux_T_2 & out_backSel_17; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_72 = _out_wofireMux_T_71 & _out_T_43; // @[RegisterRouter.scala:87:24] assign out_woready_82 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_woready_83 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_woready_84 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_woready_85 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_woready_86 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_woready_87 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_woready_88 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_woready_89 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_woready_90 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_woready_91 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_woready_92 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_woready_93 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_woready_94 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_woready_95 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_woready_96 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_woready_97 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_woready_98 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_woready_99 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_woready_100 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_73 = ~_out_T_43; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_75 = _out_wofireMux_T_2 & out_backSel_18; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_76 = _out_wofireMux_T_75; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_79 = _out_wofireMux_T_2 & out_backSel_19; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_80 = _out_wofireMux_T_79 & _out_T_67; // @[RegisterRouter.scala:87:24] assign out_woready_145 = _out_wofireMux_T_80; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_81 = ~_out_T_67; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_83 = _out_wofireMux_T_2 & out_backSel_20; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_84 = _out_wofireMux_T_83; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_87 = _out_wofireMux_T_2 & out_backSel_21; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_88 = _out_wofireMux_T_87; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_91 = _out_wofireMux_T_2 & out_backSel_22; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_92 = _out_wofireMux_T_91 & _out_T_49; // @[RegisterRouter.scala:87:24] assign out_woready_109 = _out_wofireMux_T_92; // @[RegisterRouter.scala:87:24] assign out_woready_110 = _out_wofireMux_T_92; // @[RegisterRouter.scala:87:24] assign out_woready_111 = _out_wofireMux_T_92; // @[RegisterRouter.scala:87:24] assign out_woready_112 = _out_wofireMux_T_92; // @[RegisterRouter.scala:87:24] assign out_woready_113 = _out_wofireMux_T_92; // @[RegisterRouter.scala:87:24] assign out_woready_114 = _out_wofireMux_T_92; // @[RegisterRouter.scala:87:24] assign out_woready_115 = _out_wofireMux_T_92; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_93 = ~_out_T_49; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_95 = _out_wofireMux_T_2 & out_backSel_23; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_96 = _out_wofireMux_T_95 & _out_T_63; // @[RegisterRouter.scala:87:24] assign out_woready_140 = _out_wofireMux_T_96; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_97 = ~_out_T_63; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_99 = _out_wofireMux_T_2 & out_backSel_24; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_100 = _out_wofireMux_T_99 & _out_T_23; // @[RegisterRouter.scala:87:24] assign out_woready_52 = _out_wofireMux_T_100; // @[RegisterRouter.scala:87:24] assign out_woready_53 = _out_wofireMux_T_100; // @[RegisterRouter.scala:87:24] assign out_woready_54 = _out_wofireMux_T_100; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_101 = ~_out_T_23; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_103 = _out_wofireMux_T_2 & out_backSel_25; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_104 = _out_wofireMux_T_103; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_107 = _out_wofireMux_T_2 & out_backSel_26; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_108 = _out_wofireMux_T_107; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_111 = _out_wofireMux_T_2 & out_backSel_27; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_112 = _out_wofireMux_T_111; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_115 = _out_wofireMux_T_2 & out_backSel_28; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_116 = _out_wofireMux_T_115; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_119 = _out_wofireMux_T_2 & out_backSel_29; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_120 = _out_wofireMux_T_119; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_123 = _out_wofireMux_T_2 & out_backSel_30; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_124 = _out_wofireMux_T_123; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_127 = _out_wofireMux_T_2 & out_backSel_31; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_128 = _out_wofireMux_T_127; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_131 = _out_wofireMux_T_2 & out_backSel_32; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_132 = _out_wofireMux_T_131 & _out_T_45; // @[RegisterRouter.scala:87:24] assign out_woready_101 = _out_wofireMux_T_132; // @[RegisterRouter.scala:87:24] assign out_woready_102 = _out_wofireMux_T_132; // @[RegisterRouter.scala:87:24] assign out_woready_103 = _out_wofireMux_T_132; // @[RegisterRouter.scala:87:24] assign out_woready_104 = _out_wofireMux_T_132; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_133 = ~_out_T_45; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_135 = _out_wofireMux_T_2 & out_backSel_33; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_136 = _out_wofireMux_T_135 & _out_T_37; // @[RegisterRouter.scala:87:24] assign out_woready_73 = _out_wofireMux_T_136; // @[RegisterRouter.scala:87:24] assign out_woready_74 = _out_wofireMux_T_136; // @[RegisterRouter.scala:87:24] assign out_woready_75 = _out_wofireMux_T_136; // @[RegisterRouter.scala:87:24] assign out_woready_76 = _out_wofireMux_T_136; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_137 = ~_out_T_37; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_139 = _out_wofireMux_T_2 & out_backSel_34; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_140 = _out_wofireMux_T_139 & _out_T_47; // @[RegisterRouter.scala:87:24] assign out_woready_105 = _out_wofireMux_T_140; // @[RegisterRouter.scala:87:24] assign out_woready_106 = _out_wofireMux_T_140; // @[RegisterRouter.scala:87:24] assign out_woready_107 = _out_wofireMux_T_140; // @[RegisterRouter.scala:87:24] assign out_woready_108 = _out_wofireMux_T_140; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_141 = ~_out_T_47; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_143 = _out_wofireMux_T_2 & out_backSel_35; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_144 = _out_wofireMux_T_143 & _out_T_9; // @[RegisterRouter.scala:87:24] assign out_woready_13 = _out_wofireMux_T_144; // @[RegisterRouter.scala:87:24] assign out_woready_14 = _out_wofireMux_T_144; // @[RegisterRouter.scala:87:24] assign out_woready_15 = _out_wofireMux_T_144; // @[RegisterRouter.scala:87:24] assign out_woready_16 = _out_wofireMux_T_144; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_145 = ~_out_T_9; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_147 = _out_wofireMux_T_2 & out_backSel_36; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_148 = _out_wofireMux_T_147 & _out_T_65; // @[RegisterRouter.scala:87:24] assign out_woready_141 = _out_wofireMux_T_148; // @[RegisterRouter.scala:87:24] assign out_woready_142 = _out_wofireMux_T_148; // @[RegisterRouter.scala:87:24] assign out_woready_143 = _out_wofireMux_T_148; // @[RegisterRouter.scala:87:24] assign out_woready_144 = _out_wofireMux_T_148; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_149 = ~_out_T_65; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_151 = _out_wofireMux_T_2 & out_backSel_37; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_152 = _out_wofireMux_T_151 & _out_T_25; // @[RegisterRouter.scala:87:24] assign out_woready_55 = _out_wofireMux_T_152; // @[RegisterRouter.scala:87:24] assign out_woready_56 = _out_wofireMux_T_152; // @[RegisterRouter.scala:87:24] assign out_woready_57 = _out_wofireMux_T_152; // @[RegisterRouter.scala:87:24] assign out_woready_58 = _out_wofireMux_T_152; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_153 = ~_out_T_25; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_155 = _out_wofireMux_T_2 & out_backSel_38; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_156 = _out_wofireMux_T_155 & _out_T_35; // @[RegisterRouter.scala:87:24] assign out_woready_69 = _out_wofireMux_T_156; // @[RegisterRouter.scala:87:24] assign out_woready_70 = _out_wofireMux_T_156; // @[RegisterRouter.scala:87:24] assign out_woready_71 = _out_wofireMux_T_156; // @[RegisterRouter.scala:87:24] assign out_woready_72 = _out_wofireMux_T_156; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_157 = ~_out_T_35; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_159 = _out_wofireMux_T_2 & out_backSel_39; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_160 = _out_wofireMux_T_159 & _out_T_55; // @[RegisterRouter.scala:87:24] assign out_woready_124 = _out_wofireMux_T_160; // @[RegisterRouter.scala:87:24] assign out_woready_125 = _out_wofireMux_T_160; // @[RegisterRouter.scala:87:24] assign out_woready_126 = _out_wofireMux_T_160; // @[RegisterRouter.scala:87:24] assign out_woready_127 = _out_wofireMux_T_160; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_161 = ~_out_T_55; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_163 = _out_wofireMux_T_2 & out_backSel_40; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_164 = _out_wofireMux_T_163 & _out_T_61; // @[RegisterRouter.scala:87:24] assign out_woready_136 = _out_wofireMux_T_164; // @[RegisterRouter.scala:87:24] assign out_woready_137 = _out_wofireMux_T_164; // @[RegisterRouter.scala:87:24] assign out_woready_138 = _out_wofireMux_T_164; // @[RegisterRouter.scala:87:24] assign out_woready_139 = _out_wofireMux_T_164; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_165 = ~_out_T_61; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_167 = _out_wofireMux_T_2 & out_backSel_41; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_168 = _out_wofireMux_T_167 & _out_T_7; // @[RegisterRouter.scala:87:24] assign out_woready_9 = _out_wofireMux_T_168; // @[RegisterRouter.scala:87:24] assign out_woready_10 = _out_wofireMux_T_168; // @[RegisterRouter.scala:87:24] assign out_woready_11 = _out_wofireMux_T_168; // @[RegisterRouter.scala:87:24] assign out_woready_12 = _out_wofireMux_T_168; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_169 = ~_out_T_7; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_171 = _out_wofireMux_T_2 & out_backSel_42; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_172 = _out_wofireMux_T_171 & _out_T_21; // @[RegisterRouter.scala:87:24] assign out_woready_48 = _out_wofireMux_T_172; // @[RegisterRouter.scala:87:24] assign out_woready_49 = _out_wofireMux_T_172; // @[RegisterRouter.scala:87:24] assign out_woready_50 = _out_wofireMux_T_172; // @[RegisterRouter.scala:87:24] assign out_woready_51 = _out_wofireMux_T_172; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_173 = ~_out_T_21; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_175 = _out_wofireMux_T_2 & out_backSel_43; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_176 = _out_wofireMux_T_175 & _out_T_59; // @[RegisterRouter.scala:87:24] assign out_woready_132 = _out_wofireMux_T_176; // @[RegisterRouter.scala:87:24] assign out_woready_133 = _out_wofireMux_T_176; // @[RegisterRouter.scala:87:24] assign out_woready_134 = _out_wofireMux_T_176; // @[RegisterRouter.scala:87:24] assign out_woready_135 = _out_wofireMux_T_176; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_177 = ~_out_T_59; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_179 = _out_wofireMux_T_2 & out_backSel_44; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_180 = _out_wofireMux_T_179 & _out_T_51; // @[RegisterRouter.scala:87:24] assign out_woready_116 = _out_wofireMux_T_180; // @[RegisterRouter.scala:87:24] assign out_woready_117 = _out_wofireMux_T_180; // @[RegisterRouter.scala:87:24] assign out_woready_118 = _out_wofireMux_T_180; // @[RegisterRouter.scala:87:24] assign out_woready_119 = _out_wofireMux_T_180; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_181 = ~_out_T_51; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_183 = _out_wofireMux_T_2 & out_backSel_45; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_184 = _out_wofireMux_T_183 & _out_T_39; // @[RegisterRouter.scala:87:24] assign out_woready_77 = _out_wofireMux_T_184; // @[RegisterRouter.scala:87:24] assign out_woready_78 = _out_wofireMux_T_184; // @[RegisterRouter.scala:87:24] assign out_woready_79 = _out_wofireMux_T_184; // @[RegisterRouter.scala:87:24] assign out_woready_80 = _out_wofireMux_T_184; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_185 = ~_out_T_39; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_187 = _out_wofireMux_T_2 & out_backSel_46; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_188 = _out_wofireMux_T_187 & _out_T_27; // @[RegisterRouter.scala:87:24] assign out_woready_59 = _out_wofireMux_T_188; // @[RegisterRouter.scala:87:24] assign out_woready_60 = _out_wofireMux_T_188; // @[RegisterRouter.scala:87:24] assign out_woready_61 = _out_wofireMux_T_188; // @[RegisterRouter.scala:87:24] assign out_woready_62 = _out_wofireMux_T_188; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_189 = ~_out_T_27; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_191 = _out_wofireMux_T_2 & out_backSel_47; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_192 = _out_wofireMux_T_191 & _out_T_15; // @[RegisterRouter.scala:87:24] assign out_woready_25 = _out_wofireMux_T_192; // @[RegisterRouter.scala:87:24] assign out_woready_26 = _out_wofireMux_T_192; // @[RegisterRouter.scala:87:24] assign out_woready_27 = _out_wofireMux_T_192; // @[RegisterRouter.scala:87:24] assign out_woready_28 = _out_wofireMux_T_192; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_193 = ~_out_T_15; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_195 = _out_wofireMux_T_2 & out_backSel_48; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_196 = _out_wofireMux_T_195; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_199 = _out_wofireMux_T_2 & out_backSel_49; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_200 = _out_wofireMux_T_199; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_203 = _out_wofireMux_T_2 & out_backSel_50; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_204 = _out_wofireMux_T_203; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_207 = _out_wofireMux_T_2 & out_backSel_51; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_208 = _out_wofireMux_T_207; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_211 = _out_wofireMux_T_2 & out_backSel_52; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_212 = _out_wofireMux_T_211; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_215 = _out_wofireMux_T_2 & out_backSel_53; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_216 = _out_wofireMux_T_215; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_219 = _out_wofireMux_T_2 & out_backSel_54; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_220 = _out_wofireMux_T_219; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_223 = _out_wofireMux_T_2 & out_backSel_55; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_224 = _out_wofireMux_T_223; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_227 = _out_wofireMux_T_2 & out_backSel_56; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_228 = _out_wofireMux_T_227 & _out_T_19; // @[RegisterRouter.scala:87:24] assign out_woready_33 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_woready_34 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_woready_35 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_woready_36 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_woready_37 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_woready_38 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_woready_39 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_woready_40 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_woready_41 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_woready_42 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_woready_43 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_woready_44 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_woready_45 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_woready_46 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_woready_47 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_229 = ~_out_T_19; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_231 = _out_wofireMux_T_2 & out_backSel_57; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_232 = _out_wofireMux_T_231 & _out_T_29; // @[RegisterRouter.scala:87:24] assign out_woready_63 = _out_wofireMux_T_232; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_233 = ~_out_T_29; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_235 = _out_wofireMux_T_2 & out_backSel_58; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_236 = _out_wofireMux_T_235; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_239 = _out_wofireMux_T_2 & out_backSel_59; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_240 = _out_wofireMux_T_239; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_243 = _out_wofireMux_T_2 & out_backSel_60; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_244 = _out_wofireMux_T_243 & _out_T_33; // @[RegisterRouter.scala:87:24] assign out_woready_68 = _out_wofireMux_T_244; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_245 = ~_out_T_33; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_247 = _out_wofireMux_T_2 & out_backSel_61; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_248 = _out_wofireMux_T_247 & _out_T_3; // @[RegisterRouter.scala:87:24] assign out_woready_4 = _out_wofireMux_T_248; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_249 = ~_out_T_3; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_251 = _out_wofireMux_T_2 & out_backSel_62; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_252 = _out_wofireMux_T_251; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_255 = _out_wofireMux_T_2 & out_backSel_63; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_256 = _out_wofireMux_T_255; // @[RegisterRouter.scala:87:24] assign in_ready = _out_in_ready_T; // @[RegisterRouter.scala:73:18, :87:24] assign out_front_valid = _out_front_valid_T; // @[RegisterRouter.scala:87:24] assign out_front_ready = _out_front_ready_T; // @[RegisterRouter.scala:87:24] assign out_valid = _out_out_valid_T; // @[RegisterRouter.scala:87:24] wire [63:0] _GEN_13 = {{1'h1}, {1'h1}, {_out_out_bits_data_WIRE_61}, {_out_out_bits_data_WIRE_60}, {1'h1}, {1'h1}, {_out_out_bits_data_WIRE_57}, {_out_out_bits_data_WIRE_56}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {_out_out_bits_data_WIRE_47}, {_out_out_bits_data_WIRE_46}, {_out_out_bits_data_WIRE_45}, {_out_out_bits_data_WIRE_44}, {_out_out_bits_data_WIRE_43}, {_out_out_bits_data_WIRE_42}, {_out_out_bits_data_WIRE_41}, {_out_out_bits_data_WIRE_40}, {_out_out_bits_data_WIRE_39}, {_out_out_bits_data_WIRE_38}, {_out_out_bits_data_WIRE_37}, {_out_out_bits_data_WIRE_36}, {_out_out_bits_data_WIRE_35}, {_out_out_bits_data_WIRE_34}, {_out_out_bits_data_WIRE_33}, {_out_out_bits_data_WIRE_32}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {_out_out_bits_data_WIRE_24}, {_out_out_bits_data_WIRE_23}, {_out_out_bits_data_WIRE_22}, {1'h1}, {1'h1}, {_out_out_bits_data_WIRE_19}, {1'h1}, {_out_out_bits_data_WIRE_17}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {_out_out_bits_data_WIRE_11}, {_out_out_bits_data_WIRE_10}, {_out_out_bits_data_WIRE_9}, {_out_out_bits_data_WIRE_8}, {_out_out_bits_data_WIRE_7}, {_out_out_bits_data_WIRE_6}, {_out_out_bits_data_WIRE_5}, {_out_out_bits_data_WIRE_4}, {1'h1}, {1'h1}, {1'h1}, {_out_out_bits_data_WIRE_0}}; // @[MuxLiteral.scala:49:{10,48}] wire _out_out_bits_data_T_1 = _GEN_13[out_oindex]; // @[MuxLiteral.scala:49:10] wire [31:0] _out_out_bits_data_WIRE_1_17 = {9'h0, _out_T_1118}; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_22 = {3'h0, _out_T_1271}; // @[MuxLiteral.scala:49:48] wire [63:0][31:0] _GEN_14 = {{32'h0}, {32'h0}, {_out_out_bits_data_WIRE_1_61}, {_out_out_bits_data_WIRE_1_60}, {32'h0}, {32'h0}, {_out_out_bits_data_WIRE_1_57}, {_out_out_bits_data_WIRE_1_56}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {_out_out_bits_data_WIRE_1_47}, {_out_out_bits_data_WIRE_1_46}, {_out_out_bits_data_WIRE_1_45}, {_out_out_bits_data_WIRE_1_44}, {_out_out_bits_data_WIRE_1_43}, {_out_out_bits_data_WIRE_1_42}, {_out_out_bits_data_WIRE_1_41}, {_out_out_bits_data_WIRE_1_40}, {_out_out_bits_data_WIRE_1_39}, {_out_out_bits_data_WIRE_1_38}, {_out_out_bits_data_WIRE_1_37}, {_out_out_bits_data_WIRE_1_36}, {_out_out_bits_data_WIRE_1_35}, {_out_out_bits_data_WIRE_1_34}, {_out_out_bits_data_WIRE_1_33}, {_out_out_bits_data_WIRE_1_32}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {_out_out_bits_data_WIRE_1_24}, {_out_out_bits_data_WIRE_1_23}, {_out_out_bits_data_WIRE_1_22}, {32'h0}, {32'h0}, {_out_out_bits_data_WIRE_1_19}, {32'h0}, {_out_out_bits_data_WIRE_1_17}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {_out_out_bits_data_WIRE_1_11}, {_out_out_bits_data_WIRE_1_10}, {_out_out_bits_data_WIRE_1_9}, {_out_out_bits_data_WIRE_1_8}, {_out_out_bits_data_WIRE_1_7}, {_out_out_bits_data_WIRE_1_6}, {_out_out_bits_data_WIRE_1_5}, {_out_out_bits_data_WIRE_1_4}, {32'h0}, {32'h0}, {32'h0}, {_out_out_bits_data_WIRE_1_0}}; // @[MuxLiteral.scala:49:{10,48}] wire [31:0] _out_out_bits_data_T_3 = _GEN_14[out_oindex]; // @[MuxLiteral.scala:49:10] assign _out_out_bits_data_T_4 = _out_out_bits_data_T_1 ? _out_out_bits_data_T_3 : 32'h0; // @[MuxLiteral.scala:49:10] assign out_bits_data = _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24] assign dmiNodeIn_d_bits_size = dmiNodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign dmiNodeIn_d_bits_source = dmiNodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign dmiNodeIn_d_bits_opcode = {2'h0, _dmiNodeIn_d_bits_opcode_T}; // @[RegisterRouter.scala:105:{19,25}] reg goReg; // @[Debug.scala:1494:27] wire flags_0_go = goReg; // @[Debug.scala:1494:27, :1517:25] wire goAbstract; // @[Debug.scala:1495:32] wire goCustom; // @[Debug.scala:1496:32] wire flags_0_resume; // @[Debug.scala:1517:25] assign flags_0_resume = _flags_resume_T; // @[Debug.scala:1517:25, :1524:80] wire [31:0] _accessRegisterCommandWr_T = {COMMANDWrData_cmdtype, COMMANDWrData_control}; // @[Debug.scala:1280:39, :1531:59] wire [31:0] _accessRegisterCommandWr_WIRE_1 = _accessRegisterCommandWr_T; // @[Debug.scala:1531:{59,74}] wire [7:0] _accessRegisterCommandWr_T_8; // @[Debug.scala:1531:74] wire _accessRegisterCommandWr_T_7; // @[Debug.scala:1531:74] wire [7:0] accessRegisterCommandWr_cmdtype = _accessRegisterCommandWr_WIRE_cmdtype; // @[Debug.scala:1531:{44,74}] wire [2:0] _accessRegisterCommandWr_T_6; // @[Debug.scala:1531:74] wire accessRegisterCommandWr_reserved0 = _accessRegisterCommandWr_WIRE_reserved0; // @[Debug.scala:1531:{44,74}] wire _accessRegisterCommandWr_T_5; // @[Debug.scala:1531:74] wire [2:0] accessRegisterCommandWr_size = _accessRegisterCommandWr_WIRE_size; // @[Debug.scala:1531:{44,74}] wire _accessRegisterCommandWr_T_4; // @[Debug.scala:1531:74] wire accessRegisterCommandWr_reserved1 = _accessRegisterCommandWr_WIRE_reserved1; // @[Debug.scala:1531:{44,74}] wire _accessRegisterCommandWr_T_3; // @[Debug.scala:1531:74] wire accessRegisterCommandWr_postexec = _accessRegisterCommandWr_WIRE_postexec; // @[Debug.scala:1531:{44,74}] wire _accessRegisterCommandWr_T_2; // @[Debug.scala:1531:74] wire accessRegisterCommandWr_transfer = _accessRegisterCommandWr_WIRE_transfer; // @[Debug.scala:1531:{44,74}] wire [15:0] _accessRegisterCommandWr_T_1; // @[Debug.scala:1531:74] wire accessRegisterCommandWr_write = _accessRegisterCommandWr_WIRE_write; // @[Debug.scala:1531:{44,74}] wire [15:0] accessRegisterCommandWr_regno = _accessRegisterCommandWr_WIRE_regno; // @[Debug.scala:1531:{44,74}] assign _accessRegisterCommandWr_T_1 = _accessRegisterCommandWr_WIRE_1[15:0]; // @[Debug.scala:1531:74] assign _accessRegisterCommandWr_WIRE_regno = _accessRegisterCommandWr_T_1; // @[Debug.scala:1531:74] assign _accessRegisterCommandWr_T_2 = _accessRegisterCommandWr_WIRE_1[16]; // @[Debug.scala:1531:74] assign _accessRegisterCommandWr_WIRE_write = _accessRegisterCommandWr_T_2; // @[Debug.scala:1531:74] assign _accessRegisterCommandWr_T_3 = _accessRegisterCommandWr_WIRE_1[17]; // @[Debug.scala:1531:74] assign _accessRegisterCommandWr_WIRE_transfer = _accessRegisterCommandWr_T_3; // @[Debug.scala:1531:74] assign _accessRegisterCommandWr_T_4 = _accessRegisterCommandWr_WIRE_1[18]; // @[Debug.scala:1531:74] assign _accessRegisterCommandWr_WIRE_postexec = _accessRegisterCommandWr_T_4; // @[Debug.scala:1531:74] assign _accessRegisterCommandWr_T_5 = _accessRegisterCommandWr_WIRE_1[19]; // @[Debug.scala:1531:74] assign _accessRegisterCommandWr_WIRE_reserved1 = _accessRegisterCommandWr_T_5; // @[Debug.scala:1531:74] assign _accessRegisterCommandWr_T_6 = _accessRegisterCommandWr_WIRE_1[22:20]; // @[Debug.scala:1531:74] assign _accessRegisterCommandWr_WIRE_size = _accessRegisterCommandWr_T_6; // @[Debug.scala:1531:74] assign _accessRegisterCommandWr_T_7 = _accessRegisterCommandWr_WIRE_1[23]; // @[Debug.scala:1531:74] assign _accessRegisterCommandWr_WIRE_reserved0 = _accessRegisterCommandWr_T_7; // @[Debug.scala:1531:74] assign _accessRegisterCommandWr_T_8 = _accessRegisterCommandWr_WIRE_1[31:24]; // @[Debug.scala:1531:74] assign _accessRegisterCommandWr_WIRE_cmdtype = _accessRegisterCommandWr_T_8; // @[Debug.scala:1531:74] wire [31:0] _accessRegisterCommandReg_WIRE_1 = _accessRegisterCommandReg_T; // @[Debug.scala:1533:{56,71}] wire [7:0] _accessRegisterCommandReg_T_8; // @[Debug.scala:1533:71] wire _accessRegisterCommandReg_T_7; // @[Debug.scala:1533:71] wire [7:0] accessRegisterCommandReg_cmdtype = _accessRegisterCommandReg_WIRE_cmdtype; // @[Debug.scala:1533:{44,71}] wire [2:0] _accessRegisterCommandReg_T_6; // @[Debug.scala:1533:71] wire accessRegisterCommandReg_reserved0 = _accessRegisterCommandReg_WIRE_reserved0; // @[Debug.scala:1533:{44,71}] wire _accessRegisterCommandReg_T_5; // @[Debug.scala:1533:71] wire [2:0] accessRegisterCommandReg_size = _accessRegisterCommandReg_WIRE_size; // @[Debug.scala:1533:{44,71}] wire _accessRegisterCommandReg_T_4; // @[Debug.scala:1533:71] wire accessRegisterCommandReg_reserved1 = _accessRegisterCommandReg_WIRE_reserved1; // @[Debug.scala:1533:{44,71}] wire _accessRegisterCommandReg_T_3; // @[Debug.scala:1533:71] wire accessRegisterCommandReg_postexec = _accessRegisterCommandReg_WIRE_postexec; // @[Debug.scala:1533:{44,71}] wire _accessRegisterCommandReg_T_2; // @[Debug.scala:1533:71] wire accessRegisterCommandReg_transfer = _accessRegisterCommandReg_WIRE_transfer; // @[Debug.scala:1533:{44,71}] wire [15:0] _accessRegisterCommandReg_T_1; // @[Debug.scala:1533:71] wire accessRegisterCommandReg_write = _accessRegisterCommandReg_WIRE_write; // @[Debug.scala:1533:{44,71}] wire [15:0] accessRegisterCommandReg_regno = _accessRegisterCommandReg_WIRE_regno; // @[Debug.scala:1533:{44,71}] assign _accessRegisterCommandReg_T_1 = _accessRegisterCommandReg_WIRE_1[15:0]; // @[Debug.scala:1533:71] assign _accessRegisterCommandReg_WIRE_regno = _accessRegisterCommandReg_T_1; // @[Debug.scala:1533:71] assign _accessRegisterCommandReg_T_2 = _accessRegisterCommandReg_WIRE_1[16]; // @[Debug.scala:1533:71] assign _accessRegisterCommandReg_WIRE_write = _accessRegisterCommandReg_T_2; // @[Debug.scala:1533:71] assign _accessRegisterCommandReg_T_3 = _accessRegisterCommandReg_WIRE_1[17]; // @[Debug.scala:1533:71] assign _accessRegisterCommandReg_WIRE_transfer = _accessRegisterCommandReg_T_3; // @[Debug.scala:1533:71] assign _accessRegisterCommandReg_T_4 = _accessRegisterCommandReg_WIRE_1[18]; // @[Debug.scala:1533:71] assign _accessRegisterCommandReg_WIRE_postexec = _accessRegisterCommandReg_T_4; // @[Debug.scala:1533:71] assign _accessRegisterCommandReg_T_5 = _accessRegisterCommandReg_WIRE_1[19]; // @[Debug.scala:1533:71] assign _accessRegisterCommandReg_WIRE_reserved1 = _accessRegisterCommandReg_T_5; // @[Debug.scala:1533:71] assign _accessRegisterCommandReg_T_6 = _accessRegisterCommandReg_WIRE_1[22:20]; // @[Debug.scala:1533:71] assign _accessRegisterCommandReg_WIRE_size = _accessRegisterCommandReg_T_6; // @[Debug.scala:1533:71] assign _accessRegisterCommandReg_T_7 = _accessRegisterCommandReg_WIRE_1[23]; // @[Debug.scala:1533:71] assign _accessRegisterCommandReg_WIRE_reserved0 = _accessRegisterCommandReg_T_7; // @[Debug.scala:1533:71] assign _accessRegisterCommandReg_T_8 = _accessRegisterCommandReg_WIRE_1[31:24]; // @[Debug.scala:1533:71] assign _accessRegisterCommandReg_WIRE_cmdtype = _accessRegisterCommandReg_T_8; // @[Debug.scala:1533:71] wire [2:0] abstractGeneratedMem_0_inst_funct3 = accessRegisterCommandReg_size; // @[Debug.scala:1533:44, :1589:22] wire [2:0] abstractGeneratedMem_0_inst_1_funct3 = accessRegisterCommandReg_size; // @[Debug.scala:1533:44, :1601:22] reg [31:0] abstractGeneratedMem_0; // @[Debug.scala:1586:35] wire [31:0] _out_T_8286 = abstractGeneratedMem_0; // @[RegisterRouter.scala:87:24] reg [31:0] abstractGeneratedMem_1; // @[Debug.scala:1586:35] wire [4:0] abstractGeneratedMem_0_inst_rd; // @[Debug.scala:1589:22] wire [15:0] _GEN_15 = {11'h0, accessRegisterCommandReg_regno[4:0]}; // @[Debug.scala:1533:44, :1593:54] wire [15:0] _abstractGeneratedMem_0_inst_rd_T; // @[Debug.scala:1593:54] assign _abstractGeneratedMem_0_inst_rd_T = _GEN_15; // @[Debug.scala:1593:54] wire [15:0] _abstractGeneratedMem_0_inst_rs2_T; // @[Debug.scala:1608:54] assign _abstractGeneratedMem_0_inst_rs2_T = _GEN_15; // @[Debug.scala:1593:54, :1608:54] assign abstractGeneratedMem_0_inst_rd = _abstractGeneratedMem_0_inst_rd_T[4:0]; // @[Debug.scala:1589:22, :1593:{19,54}] wire [11:0] abstractGeneratedMem_0_lo = {abstractGeneratedMem_0_inst_rd, 7'h3}; // @[Debug.scala:1589:22, :1597:12] wire [19:0] abstractGeneratedMem_0_hi = {17'h7000, abstractGeneratedMem_0_inst_funct3}; // @[Debug.scala:1589:22, :1597:12] wire [31:0] _abstractGeneratedMem_0_T = {abstractGeneratedMem_0_hi, abstractGeneratedMem_0_lo}; // @[Debug.scala:1597:12] wire [4:0] abstractGeneratedMem_0_inst_1_rs2; // @[Debug.scala:1601:22] assign abstractGeneratedMem_0_inst_1_rs2 = _abstractGeneratedMem_0_inst_rs2_T[4:0]; // @[Debug.scala:1601:22, :1608:{19,54}] wire [7:0] abstractGeneratedMem_0_lo_hi = {abstractGeneratedMem_0_inst_1_funct3, 5'h0}; // @[Debug.scala:1601:22, :1610:12] wire [14:0] abstractGeneratedMem_0_lo_1 = {abstractGeneratedMem_0_lo_hi, 7'h23}; // @[Debug.scala:1610:12] wire [11:0] abstractGeneratedMem_0_hi_hi_1 = {7'h1C, abstractGeneratedMem_0_inst_1_rs2}; // @[Debug.scala:1601:22, :1610:12] wire [16:0] abstractGeneratedMem_0_hi_1 = {abstractGeneratedMem_0_hi_hi_1, 5'h0}; // @[Debug.scala:1610:12] wire [31:0] _abstractGeneratedMem_0_T_1 = {abstractGeneratedMem_0_hi_1, abstractGeneratedMem_0_lo_1}; // @[Debug.scala:1610:12] wire [31:0] _abstractGeneratedMem_0_T_2 = accessRegisterCommandReg_write ? _abstractGeneratedMem_0_T : _abstractGeneratedMem_0_T_1; // @[Debug.scala:1533:44, :1597:12, :1610:12, :1641:14] wire [31:0] _abstractGeneratedMem_0_T_4 = accessRegisterCommandReg_transfer ? _abstractGeneratedMem_0_T_2 : 32'h13; // @[Debug.scala:1533:44, :1640:39, :1641:14] wire [31:0] _abstractGeneratedMem_1_T_1 = accessRegisterCommandReg_postexec ? 32'h13 : 32'h100073; // @[Debug.scala:1533:44, :1644:39] wire [6:0] _GEN_16 = {6'h0, flags_0_resume}; // @[Debug.scala:1517:25, :1702:60] wire [6:0] hi_1; // @[Debug.scala:1702:60] assign hi_1 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_2; // @[Debug.scala:1702:60] assign hi_2 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_3; // @[Debug.scala:1702:60] assign hi_3 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_4; // @[Debug.scala:1702:60] assign hi_4 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_5; // @[Debug.scala:1702:60] assign hi_5 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_6; // @[Debug.scala:1702:60] assign hi_6 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_7; // @[Debug.scala:1702:60] assign hi_7 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_8; // @[Debug.scala:1702:60] assign hi_8 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_9; // @[Debug.scala:1702:60] assign hi_9 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_10; // @[Debug.scala:1702:60] assign hi_10 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_11; // @[Debug.scala:1702:60] assign hi_11 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_12; // @[Debug.scala:1702:60] assign hi_12 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_13; // @[Debug.scala:1702:60] assign hi_13 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_14; // @[Debug.scala:1702:60] assign hi_14 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_15; // @[Debug.scala:1702:60] assign hi_15 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_16; // @[Debug.scala:1702:60] assign hi_16 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_17; // @[Debug.scala:1702:60] assign hi_17 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_18; // @[Debug.scala:1702:60] assign hi_18 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_19; // @[Debug.scala:1702:60] assign hi_19 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_20; // @[Debug.scala:1702:60] assign hi_20 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_21; // @[Debug.scala:1702:60] assign hi_21 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_22; // @[Debug.scala:1702:60] assign hi_22 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_23; // @[Debug.scala:1702:60] assign hi_23 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_24; // @[Debug.scala:1702:60] assign hi_24 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_25; // @[Debug.scala:1702:60] assign hi_25 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_26; // @[Debug.scala:1702:60] assign hi_26 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_27; // @[Debug.scala:1702:60] assign hi_27 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_28; // @[Debug.scala:1702:60] assign hi_28 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_29; // @[Debug.scala:1702:60] assign hi_29 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_30; // @[Debug.scala:1702:60] assign hi_30 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_31; // @[Debug.scala:1702:60] assign hi_31 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_32; // @[Debug.scala:1702:60] assign hi_32 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_33; // @[Debug.scala:1702:60] assign hi_33 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_34; // @[Debug.scala:1702:60] assign hi_34 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_35; // @[Debug.scala:1702:60] assign hi_35 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_36; // @[Debug.scala:1702:60] assign hi_36 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_37; // @[Debug.scala:1702:60] assign hi_37 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_38; // @[Debug.scala:1702:60] assign hi_38 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_39; // @[Debug.scala:1702:60] assign hi_39 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_40; // @[Debug.scala:1702:60] assign hi_40 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_41; // @[Debug.scala:1702:60] assign hi_41 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_42; // @[Debug.scala:1702:60] assign hi_42 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_43; // @[Debug.scala:1702:60] assign hi_43 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_44; // @[Debug.scala:1702:60] assign hi_44 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_45; // @[Debug.scala:1702:60] assign hi_45 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_46; // @[Debug.scala:1702:60] assign hi_46 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_47; // @[Debug.scala:1702:60] assign hi_47 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_48; // @[Debug.scala:1702:60] assign hi_48 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_49; // @[Debug.scala:1702:60] assign hi_49 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_50; // @[Debug.scala:1702:60] assign hi_50 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_51; // @[Debug.scala:1702:60] assign hi_51 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_52; // @[Debug.scala:1702:60] assign hi_52 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_53; // @[Debug.scala:1702:60] assign hi_53 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_54; // @[Debug.scala:1702:60] assign hi_54 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_55; // @[Debug.scala:1702:60] assign hi_55 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_56; // @[Debug.scala:1702:60] assign hi_56 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_57; // @[Debug.scala:1702:60] assign hi_57 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_58; // @[Debug.scala:1702:60] assign hi_58 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_59; // @[Debug.scala:1702:60] assign hi_59 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_60; // @[Debug.scala:1702:60] assign hi_60 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_61; // @[Debug.scala:1702:60] assign hi_61 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_62; // @[Debug.scala:1702:60] assign hi_62 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_63; // @[Debug.scala:1702:60] assign hi_63 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_64; // @[Debug.scala:1702:60] assign hi_64 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_65; // @[Debug.scala:1702:60] assign hi_65 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_66; // @[Debug.scala:1702:60] assign hi_66 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_67; // @[Debug.scala:1702:60] assign hi_67 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_68; // @[Debug.scala:1702:60] assign hi_68 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_69; // @[Debug.scala:1702:60] assign hi_69 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_70; // @[Debug.scala:1702:60] assign hi_70 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_71; // @[Debug.scala:1702:60] assign hi_71 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_72; // @[Debug.scala:1702:60] assign hi_72 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_73; // @[Debug.scala:1702:60] assign hi_73 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_74; // @[Debug.scala:1702:60] assign hi_74 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_75; // @[Debug.scala:1702:60] assign hi_75 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_76; // @[Debug.scala:1702:60] assign hi_76 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_77; // @[Debug.scala:1702:60] assign hi_77 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_78; // @[Debug.scala:1702:60] assign hi_78 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_79; // @[Debug.scala:1702:60] assign hi_79 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_80; // @[Debug.scala:1702:60] assign hi_80 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_81; // @[Debug.scala:1702:60] assign hi_81 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_82; // @[Debug.scala:1702:60] assign hi_82 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_83; // @[Debug.scala:1702:60] assign hi_83 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_84; // @[Debug.scala:1702:60] assign hi_84 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_85; // @[Debug.scala:1702:60] assign hi_85 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_86; // @[Debug.scala:1702:60] assign hi_86 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_87; // @[Debug.scala:1702:60] assign hi_87 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_88; // @[Debug.scala:1702:60] assign hi_88 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_89; // @[Debug.scala:1702:60] assign hi_89 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_90; // @[Debug.scala:1702:60] assign hi_90 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_91; // @[Debug.scala:1702:60] assign hi_91 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_92; // @[Debug.scala:1702:60] assign hi_92 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_93; // @[Debug.scala:1702:60] assign hi_93 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_94; // @[Debug.scala:1702:60] assign hi_94 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_95; // @[Debug.scala:1702:60] assign hi_95 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_96; // @[Debug.scala:1702:60] assign hi_96 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_97; // @[Debug.scala:1702:60] assign hi_97 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_98; // @[Debug.scala:1702:60] assign hi_98 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_99; // @[Debug.scala:1702:60] assign hi_99 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_100; // @[Debug.scala:1702:60] assign hi_100 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_101; // @[Debug.scala:1702:60] assign hi_101 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_102; // @[Debug.scala:1702:60] assign hi_102 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_103; // @[Debug.scala:1702:60] assign hi_103 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_104; // @[Debug.scala:1702:60] assign hi_104 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_105; // @[Debug.scala:1702:60] assign hi_105 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_106; // @[Debug.scala:1702:60] assign hi_106 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_107; // @[Debug.scala:1702:60] assign hi_107 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_108; // @[Debug.scala:1702:60] assign hi_108 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_109; // @[Debug.scala:1702:60] assign hi_109 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_110; // @[Debug.scala:1702:60] assign hi_110 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_111; // @[Debug.scala:1702:60] assign hi_111 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_112; // @[Debug.scala:1702:60] assign hi_112 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_113; // @[Debug.scala:1702:60] assign hi_113 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_114; // @[Debug.scala:1702:60] assign hi_114 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_115; // @[Debug.scala:1702:60] assign hi_115 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_116; // @[Debug.scala:1702:60] assign hi_116 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_117; // @[Debug.scala:1702:60] assign hi_117 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_118; // @[Debug.scala:1702:60] assign hi_118 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_119; // @[Debug.scala:1702:60] assign hi_119 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_120; // @[Debug.scala:1702:60] assign hi_120 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_121; // @[Debug.scala:1702:60] assign hi_121 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_122; // @[Debug.scala:1702:60] assign hi_122 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_123; // @[Debug.scala:1702:60] assign hi_123 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_124; // @[Debug.scala:1702:60] assign hi_124 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_125; // @[Debug.scala:1702:60] assign hi_125 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_126; // @[Debug.scala:1702:60] assign hi_126 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_127; // @[Debug.scala:1702:60] assign hi_127 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_128; // @[Debug.scala:1702:60] assign hi_128 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_129; // @[Debug.scala:1702:60] assign hi_129 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_130; // @[Debug.scala:1702:60] assign hi_130 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_131; // @[Debug.scala:1702:60] assign hi_131 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_132; // @[Debug.scala:1702:60] assign hi_132 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_133; // @[Debug.scala:1702:60] assign hi_133 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_134; // @[Debug.scala:1702:60] assign hi_134 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_135; // @[Debug.scala:1702:60] assign hi_135 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_136; // @[Debug.scala:1702:60] assign hi_136 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_137; // @[Debug.scala:1702:60] assign hi_137 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_138; // @[Debug.scala:1702:60] assign hi_138 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_139; // @[Debug.scala:1702:60] assign hi_139 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_140; // @[Debug.scala:1702:60] assign hi_140 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_141; // @[Debug.scala:1702:60] assign hi_141 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_142; // @[Debug.scala:1702:60] assign hi_142 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_143; // @[Debug.scala:1702:60] assign hi_143 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_144; // @[Debug.scala:1702:60] assign hi_144 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_145; // @[Debug.scala:1702:60] assign hi_145 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_146; // @[Debug.scala:1702:60] assign hi_146 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_147; // @[Debug.scala:1702:60] assign hi_147 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_148; // @[Debug.scala:1702:60] assign hi_148 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_149; // @[Debug.scala:1702:60] assign hi_149 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_150; // @[Debug.scala:1702:60] assign hi_150 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_151; // @[Debug.scala:1702:60] assign hi_151 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_152; // @[Debug.scala:1702:60] assign hi_152 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_153; // @[Debug.scala:1702:60] assign hi_153 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_154; // @[Debug.scala:1702:60] assign hi_154 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_155; // @[Debug.scala:1702:60] assign hi_155 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_156; // @[Debug.scala:1702:60] assign hi_156 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_157; // @[Debug.scala:1702:60] assign hi_157 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_158; // @[Debug.scala:1702:60] assign hi_158 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_159; // @[Debug.scala:1702:60] assign hi_159 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_160; // @[Debug.scala:1702:60] assign hi_160 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_161; // @[Debug.scala:1702:60] assign hi_161 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_162; // @[Debug.scala:1702:60] assign hi_162 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_163; // @[Debug.scala:1702:60] assign hi_163 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_164; // @[Debug.scala:1702:60] assign hi_164 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_165; // @[Debug.scala:1702:60] assign hi_165 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_166; // @[Debug.scala:1702:60] assign hi_166 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_167; // @[Debug.scala:1702:60] assign hi_167 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_168; // @[Debug.scala:1702:60] assign hi_168 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_169; // @[Debug.scala:1702:60] assign hi_169 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_170; // @[Debug.scala:1702:60] assign hi_170 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_171; // @[Debug.scala:1702:60] assign hi_171 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_172; // @[Debug.scala:1702:60] assign hi_172 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_173; // @[Debug.scala:1702:60] assign hi_173 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_174; // @[Debug.scala:1702:60] assign hi_174 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_175; // @[Debug.scala:1702:60] assign hi_175 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_176; // @[Debug.scala:1702:60] assign hi_176 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_177; // @[Debug.scala:1702:60] assign hi_177 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_178; // @[Debug.scala:1702:60] assign hi_178 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_179; // @[Debug.scala:1702:60] assign hi_179 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_180; // @[Debug.scala:1702:60] assign hi_180 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_181; // @[Debug.scala:1702:60] assign hi_181 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_182; // @[Debug.scala:1702:60] assign hi_182 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_183; // @[Debug.scala:1702:60] assign hi_183 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_184; // @[Debug.scala:1702:60] assign hi_184 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_185; // @[Debug.scala:1702:60] assign hi_185 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_186; // @[Debug.scala:1702:60] assign hi_186 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_187; // @[Debug.scala:1702:60] assign hi_187 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_188; // @[Debug.scala:1702:60] assign hi_188 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_189; // @[Debug.scala:1702:60] assign hi_189 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_190; // @[Debug.scala:1702:60] assign hi_190 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_191; // @[Debug.scala:1702:60] assign hi_191 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_192; // @[Debug.scala:1702:60] assign hi_192 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_193; // @[Debug.scala:1702:60] assign hi_193 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_194; // @[Debug.scala:1702:60] assign hi_194 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_195; // @[Debug.scala:1702:60] assign hi_195 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_196; // @[Debug.scala:1702:60] assign hi_196 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_197; // @[Debug.scala:1702:60] assign hi_197 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_198; // @[Debug.scala:1702:60] assign hi_198 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_199; // @[Debug.scala:1702:60] assign hi_199 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_200; // @[Debug.scala:1702:60] assign hi_200 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_201; // @[Debug.scala:1702:60] assign hi_201 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_202; // @[Debug.scala:1702:60] assign hi_202 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_203; // @[Debug.scala:1702:60] assign hi_203 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_204; // @[Debug.scala:1702:60] assign hi_204 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_205; // @[Debug.scala:1702:60] assign hi_205 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_206; // @[Debug.scala:1702:60] assign hi_206 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_207; // @[Debug.scala:1702:60] assign hi_207 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_208; // @[Debug.scala:1702:60] assign hi_208 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_209; // @[Debug.scala:1702:60] assign hi_209 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_210; // @[Debug.scala:1702:60] assign hi_210 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_211; // @[Debug.scala:1702:60] assign hi_211 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_212; // @[Debug.scala:1702:60] assign hi_212 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_213; // @[Debug.scala:1702:60] assign hi_213 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_214; // @[Debug.scala:1702:60] assign hi_214 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_215; // @[Debug.scala:1702:60] assign hi_215 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_216; // @[Debug.scala:1702:60] assign hi_216 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_217; // @[Debug.scala:1702:60] assign hi_217 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_218; // @[Debug.scala:1702:60] assign hi_218 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_219; // @[Debug.scala:1702:60] assign hi_219 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_220; // @[Debug.scala:1702:60] assign hi_220 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_221; // @[Debug.scala:1702:60] assign hi_221 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_222; // @[Debug.scala:1702:60] assign hi_222 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_223; // @[Debug.scala:1702:60] assign hi_223 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_224; // @[Debug.scala:1702:60] assign hi_224 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_225; // @[Debug.scala:1702:60] assign hi_225 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_226; // @[Debug.scala:1702:60] assign hi_226 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_227; // @[Debug.scala:1702:60] assign hi_227 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_228; // @[Debug.scala:1702:60] assign hi_228 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_229; // @[Debug.scala:1702:60] assign hi_229 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_230; // @[Debug.scala:1702:60] assign hi_230 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_231; // @[Debug.scala:1702:60] assign hi_231 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_232; // @[Debug.scala:1702:60] assign hi_232 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_233; // @[Debug.scala:1702:60] assign hi_233 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_234; // @[Debug.scala:1702:60] assign hi_234 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_235; // @[Debug.scala:1702:60] assign hi_235 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_236; // @[Debug.scala:1702:60] assign hi_236 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_237; // @[Debug.scala:1702:60] assign hi_237 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_238; // @[Debug.scala:1702:60] assign hi_238 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_239; // @[Debug.scala:1702:60] assign hi_239 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_240; // @[Debug.scala:1702:60] assign hi_240 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_241; // @[Debug.scala:1702:60] assign hi_241 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_242; // @[Debug.scala:1702:60] assign hi_242 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_243; // @[Debug.scala:1702:60] assign hi_243 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_244; // @[Debug.scala:1702:60] assign hi_244 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_245; // @[Debug.scala:1702:60] assign hi_245 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_246; // @[Debug.scala:1702:60] assign hi_246 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_247; // @[Debug.scala:1702:60] assign hi_247 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_248; // @[Debug.scala:1702:60] assign hi_248 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_249; // @[Debug.scala:1702:60] assign hi_249 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_250; // @[Debug.scala:1702:60] assign hi_250 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_251; // @[Debug.scala:1702:60] assign hi_251 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_252; // @[Debug.scala:1702:60] assign hi_252 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_253; // @[Debug.scala:1702:60] assign hi_253 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_254; // @[Debug.scala:1702:60] assign hi_254 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_255; // @[Debug.scala:1702:60] assign hi_255 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_256; // @[Debug.scala:1702:60] assign hi_256 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_257; // @[Debug.scala:1702:60] assign hi_257 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_258; // @[Debug.scala:1702:60] assign hi_258 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_259; // @[Debug.scala:1702:60] assign hi_259 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_260; // @[Debug.scala:1702:60] assign hi_260 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_261; // @[Debug.scala:1702:60] assign hi_261 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_262; // @[Debug.scala:1702:60] assign hi_262 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_263; // @[Debug.scala:1702:60] assign hi_263 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_264; // @[Debug.scala:1702:60] assign hi_264 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_265; // @[Debug.scala:1702:60] assign hi_265 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_266; // @[Debug.scala:1702:60] assign hi_266 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_267; // @[Debug.scala:1702:60] assign hi_267 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_268; // @[Debug.scala:1702:60] assign hi_268 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_269; // @[Debug.scala:1702:60] assign hi_269 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_270; // @[Debug.scala:1702:60] assign hi_270 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_271; // @[Debug.scala:1702:60] assign hi_271 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_272; // @[Debug.scala:1702:60] assign hi_272 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_273; // @[Debug.scala:1702:60] assign hi_273 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_274; // @[Debug.scala:1702:60] assign hi_274 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_275; // @[Debug.scala:1702:60] assign hi_275 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_276; // @[Debug.scala:1702:60] assign hi_276 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_277; // @[Debug.scala:1702:60] assign hi_277 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_278; // @[Debug.scala:1702:60] assign hi_278 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_279; // @[Debug.scala:1702:60] assign hi_279 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_280; // @[Debug.scala:1702:60] assign hi_280 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_281; // @[Debug.scala:1702:60] assign hi_281 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_282; // @[Debug.scala:1702:60] assign hi_282 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_283; // @[Debug.scala:1702:60] assign hi_283 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_284; // @[Debug.scala:1702:60] assign hi_284 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_285; // @[Debug.scala:1702:60] assign hi_285 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_286; // @[Debug.scala:1702:60] assign hi_286 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_287; // @[Debug.scala:1702:60] assign hi_287 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_288; // @[Debug.scala:1702:60] assign hi_288 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_289; // @[Debug.scala:1702:60] assign hi_289 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_290; // @[Debug.scala:1702:60] assign hi_290 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_291; // @[Debug.scala:1702:60] assign hi_291 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_292; // @[Debug.scala:1702:60] assign hi_292 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_293; // @[Debug.scala:1702:60] assign hi_293 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_294; // @[Debug.scala:1702:60] assign hi_294 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_295; // @[Debug.scala:1702:60] assign hi_295 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_296; // @[Debug.scala:1702:60] assign hi_296 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_297; // @[Debug.scala:1702:60] assign hi_297 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_298; // @[Debug.scala:1702:60] assign hi_298 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_299; // @[Debug.scala:1702:60] assign hi_299 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_300; // @[Debug.scala:1702:60] assign hi_300 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_301; // @[Debug.scala:1702:60] assign hi_301 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_302; // @[Debug.scala:1702:60] assign hi_302 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_303; // @[Debug.scala:1702:60] assign hi_303 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_304; // @[Debug.scala:1702:60] assign hi_304 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_305; // @[Debug.scala:1702:60] assign hi_305 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_306; // @[Debug.scala:1702:60] assign hi_306 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_307; // @[Debug.scala:1702:60] assign hi_307 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_308; // @[Debug.scala:1702:60] assign hi_308 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_309; // @[Debug.scala:1702:60] assign hi_309 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_310; // @[Debug.scala:1702:60] assign hi_310 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_311; // @[Debug.scala:1702:60] assign hi_311 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_312; // @[Debug.scala:1702:60] assign hi_312 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_313; // @[Debug.scala:1702:60] assign hi_313 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_314; // @[Debug.scala:1702:60] assign hi_314 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_315; // @[Debug.scala:1702:60] assign hi_315 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_316; // @[Debug.scala:1702:60] assign hi_316 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_317; // @[Debug.scala:1702:60] assign hi_317 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_318; // @[Debug.scala:1702:60] assign hi_318 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_319; // @[Debug.scala:1702:60] assign hi_319 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_320; // @[Debug.scala:1702:60] assign hi_320 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_321; // @[Debug.scala:1702:60] assign hi_321 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_322; // @[Debug.scala:1702:60] assign hi_322 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_323; // @[Debug.scala:1702:60] assign hi_323 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_324; // @[Debug.scala:1702:60] assign hi_324 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_325; // @[Debug.scala:1702:60] assign hi_325 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_326; // @[Debug.scala:1702:60] assign hi_326 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_327; // @[Debug.scala:1702:60] assign hi_327 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_328; // @[Debug.scala:1702:60] assign hi_328 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_329; // @[Debug.scala:1702:60] assign hi_329 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_330; // @[Debug.scala:1702:60] assign hi_330 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_331; // @[Debug.scala:1702:60] assign hi_331 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_332; // @[Debug.scala:1702:60] assign hi_332 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_333; // @[Debug.scala:1702:60] assign hi_333 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_334; // @[Debug.scala:1702:60] assign hi_334 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_335; // @[Debug.scala:1702:60] assign hi_335 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_336; // @[Debug.scala:1702:60] assign hi_336 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_337; // @[Debug.scala:1702:60] assign hi_337 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_338; // @[Debug.scala:1702:60] assign hi_338 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_339; // @[Debug.scala:1702:60] assign hi_339 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_340; // @[Debug.scala:1702:60] assign hi_340 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_341; // @[Debug.scala:1702:60] assign hi_341 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_342; // @[Debug.scala:1702:60] assign hi_342 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_343; // @[Debug.scala:1702:60] assign hi_343 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_344; // @[Debug.scala:1702:60] assign hi_344 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_345; // @[Debug.scala:1702:60] assign hi_345 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_346; // @[Debug.scala:1702:60] assign hi_346 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_347; // @[Debug.scala:1702:60] assign hi_347 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_348; // @[Debug.scala:1702:60] assign hi_348 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_349; // @[Debug.scala:1702:60] assign hi_349 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_350; // @[Debug.scala:1702:60] assign hi_350 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_351; // @[Debug.scala:1702:60] assign hi_351 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_352; // @[Debug.scala:1702:60] assign hi_352 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_353; // @[Debug.scala:1702:60] assign hi_353 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_354; // @[Debug.scala:1702:60] assign hi_354 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_355; // @[Debug.scala:1702:60] assign hi_355 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_356; // @[Debug.scala:1702:60] assign hi_356 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_357; // @[Debug.scala:1702:60] assign hi_357 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_358; // @[Debug.scala:1702:60] assign hi_358 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_359; // @[Debug.scala:1702:60] assign hi_359 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_360; // @[Debug.scala:1702:60] assign hi_360 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_361; // @[Debug.scala:1702:60] assign hi_361 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_362; // @[Debug.scala:1702:60] assign hi_362 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_363; // @[Debug.scala:1702:60] assign hi_363 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_364; // @[Debug.scala:1702:60] assign hi_364 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_365; // @[Debug.scala:1702:60] assign hi_365 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_366; // @[Debug.scala:1702:60] assign hi_366 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_367; // @[Debug.scala:1702:60] assign hi_367 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_368; // @[Debug.scala:1702:60] assign hi_368 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_369; // @[Debug.scala:1702:60] assign hi_369 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_370; // @[Debug.scala:1702:60] assign hi_370 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_371; // @[Debug.scala:1702:60] assign hi_371 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_372; // @[Debug.scala:1702:60] assign hi_372 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_373; // @[Debug.scala:1702:60] assign hi_373 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_374; // @[Debug.scala:1702:60] assign hi_374 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_375; // @[Debug.scala:1702:60] assign hi_375 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_376; // @[Debug.scala:1702:60] assign hi_376 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_377; // @[Debug.scala:1702:60] assign hi_377 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_378; // @[Debug.scala:1702:60] assign hi_378 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_379; // @[Debug.scala:1702:60] assign hi_379 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_380; // @[Debug.scala:1702:60] assign hi_380 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_381; // @[Debug.scala:1702:60] assign hi_381 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_382; // @[Debug.scala:1702:60] assign hi_382 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_383; // @[Debug.scala:1702:60] assign hi_383 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_384; // @[Debug.scala:1702:60] assign hi_384 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_385; // @[Debug.scala:1702:60] assign hi_385 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_386; // @[Debug.scala:1702:60] assign hi_386 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_387; // @[Debug.scala:1702:60] assign hi_387 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_388; // @[Debug.scala:1702:60] assign hi_388 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_389; // @[Debug.scala:1702:60] assign hi_389 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_390; // @[Debug.scala:1702:60] assign hi_390 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_391; // @[Debug.scala:1702:60] assign hi_391 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_392; // @[Debug.scala:1702:60] assign hi_392 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_393; // @[Debug.scala:1702:60] assign hi_393 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_394; // @[Debug.scala:1702:60] assign hi_394 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_395; // @[Debug.scala:1702:60] assign hi_395 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_396; // @[Debug.scala:1702:60] assign hi_396 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_397; // @[Debug.scala:1702:60] assign hi_397 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_398; // @[Debug.scala:1702:60] assign hi_398 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_399; // @[Debug.scala:1702:60] assign hi_399 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_400; // @[Debug.scala:1702:60] assign hi_400 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_401; // @[Debug.scala:1702:60] assign hi_401 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_402; // @[Debug.scala:1702:60] assign hi_402 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_403; // @[Debug.scala:1702:60] assign hi_403 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_404; // @[Debug.scala:1702:60] assign hi_404 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_405; // @[Debug.scala:1702:60] assign hi_405 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_406; // @[Debug.scala:1702:60] assign hi_406 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_407; // @[Debug.scala:1702:60] assign hi_407 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_408; // @[Debug.scala:1702:60] assign hi_408 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_409; // @[Debug.scala:1702:60] assign hi_409 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_410; // @[Debug.scala:1702:60] assign hi_410 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_411; // @[Debug.scala:1702:60] assign hi_411 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_412; // @[Debug.scala:1702:60] assign hi_412 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_413; // @[Debug.scala:1702:60] assign hi_413 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_414; // @[Debug.scala:1702:60] assign hi_414 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_415; // @[Debug.scala:1702:60] assign hi_415 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_416; // @[Debug.scala:1702:60] assign hi_416 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_417; // @[Debug.scala:1702:60] assign hi_417 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_418; // @[Debug.scala:1702:60] assign hi_418 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_419; // @[Debug.scala:1702:60] assign hi_419 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_420; // @[Debug.scala:1702:60] assign hi_420 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_421; // @[Debug.scala:1702:60] assign hi_421 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_422; // @[Debug.scala:1702:60] assign hi_422 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_423; // @[Debug.scala:1702:60] assign hi_423 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_424; // @[Debug.scala:1702:60] assign hi_424 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_425; // @[Debug.scala:1702:60] assign hi_425 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_426; // @[Debug.scala:1702:60] assign hi_426 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_427; // @[Debug.scala:1702:60] assign hi_427 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_428; // @[Debug.scala:1702:60] assign hi_428 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_429; // @[Debug.scala:1702:60] assign hi_429 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_430; // @[Debug.scala:1702:60] assign hi_430 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_431; // @[Debug.scala:1702:60] assign hi_431 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_432; // @[Debug.scala:1702:60] assign hi_432 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_433; // @[Debug.scala:1702:60] assign hi_433 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_434; // @[Debug.scala:1702:60] assign hi_434 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_435; // @[Debug.scala:1702:60] assign hi_435 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_436; // @[Debug.scala:1702:60] assign hi_436 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_437; // @[Debug.scala:1702:60] assign hi_437 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_438; // @[Debug.scala:1702:60] assign hi_438 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_439; // @[Debug.scala:1702:60] assign hi_439 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_440; // @[Debug.scala:1702:60] assign hi_440 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_441; // @[Debug.scala:1702:60] assign hi_441 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_442; // @[Debug.scala:1702:60] assign hi_442 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_443; // @[Debug.scala:1702:60] assign hi_443 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_444; // @[Debug.scala:1702:60] assign hi_444 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_445; // @[Debug.scala:1702:60] assign hi_445 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_446; // @[Debug.scala:1702:60] assign hi_446 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_447; // @[Debug.scala:1702:60] assign hi_447 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_448; // @[Debug.scala:1702:60] assign hi_448 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_449; // @[Debug.scala:1702:60] assign hi_449 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_450; // @[Debug.scala:1702:60] assign hi_450 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_451; // @[Debug.scala:1702:60] assign hi_451 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_452; // @[Debug.scala:1702:60] assign hi_452 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_453; // @[Debug.scala:1702:60] assign hi_453 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_454; // @[Debug.scala:1702:60] assign hi_454 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_455; // @[Debug.scala:1702:60] assign hi_455 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_456; // @[Debug.scala:1702:60] assign hi_456 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_457; // @[Debug.scala:1702:60] assign hi_457 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_458; // @[Debug.scala:1702:60] assign hi_458 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_459; // @[Debug.scala:1702:60] assign hi_459 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_460; // @[Debug.scala:1702:60] assign hi_460 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_461; // @[Debug.scala:1702:60] assign hi_461 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_462; // @[Debug.scala:1702:60] assign hi_462 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_463; // @[Debug.scala:1702:60] assign hi_463 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_464; // @[Debug.scala:1702:60] assign hi_464 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_465; // @[Debug.scala:1702:60] assign hi_465 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_466; // @[Debug.scala:1702:60] assign hi_466 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_467; // @[Debug.scala:1702:60] assign hi_467 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_468; // @[Debug.scala:1702:60] assign hi_468 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_469; // @[Debug.scala:1702:60] assign hi_469 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_470; // @[Debug.scala:1702:60] assign hi_470 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_471; // @[Debug.scala:1702:60] assign hi_471 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_472; // @[Debug.scala:1702:60] assign hi_472 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_473; // @[Debug.scala:1702:60] assign hi_473 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_474; // @[Debug.scala:1702:60] assign hi_474 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_475; // @[Debug.scala:1702:60] assign hi_475 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_476; // @[Debug.scala:1702:60] assign hi_476 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_477; // @[Debug.scala:1702:60] assign hi_477 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_478; // @[Debug.scala:1702:60] assign hi_478 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_479; // @[Debug.scala:1702:60] assign hi_479 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_480; // @[Debug.scala:1702:60] assign hi_480 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_481; // @[Debug.scala:1702:60] assign hi_481 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_482; // @[Debug.scala:1702:60] assign hi_482 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_483; // @[Debug.scala:1702:60] assign hi_483 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_484; // @[Debug.scala:1702:60] assign hi_484 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_485; // @[Debug.scala:1702:60] assign hi_485 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_486; // @[Debug.scala:1702:60] assign hi_486 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_487; // @[Debug.scala:1702:60] assign hi_487 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_488; // @[Debug.scala:1702:60] assign hi_488 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_489; // @[Debug.scala:1702:60] assign hi_489 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_490; // @[Debug.scala:1702:60] assign hi_490 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_491; // @[Debug.scala:1702:60] assign hi_491 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_492; // @[Debug.scala:1702:60] assign hi_492 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_493; // @[Debug.scala:1702:60] assign hi_493 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_494; // @[Debug.scala:1702:60] assign hi_494 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_495; // @[Debug.scala:1702:60] assign hi_495 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_496; // @[Debug.scala:1702:60] assign hi_496 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_497; // @[Debug.scala:1702:60] assign hi_497 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_498; // @[Debug.scala:1702:60] assign hi_498 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_499; // @[Debug.scala:1702:60] assign hi_499 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_500; // @[Debug.scala:1702:60] assign hi_500 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_501; // @[Debug.scala:1702:60] assign hi_501 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_502; // @[Debug.scala:1702:60] assign hi_502 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_503; // @[Debug.scala:1702:60] assign hi_503 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_504; // @[Debug.scala:1702:60] assign hi_504 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_505; // @[Debug.scala:1702:60] assign hi_505 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_506; // @[Debug.scala:1702:60] assign hi_506 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_507; // @[Debug.scala:1702:60] assign hi_507 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_508; // @[Debug.scala:1702:60] assign hi_508 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_509; // @[Debug.scala:1702:60] assign hi_509 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_510; // @[Debug.scala:1702:60] assign hi_510 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_511; // @[Debug.scala:1702:60] assign hi_511 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_512; // @[Debug.scala:1702:60] assign hi_512 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_513; // @[Debug.scala:1702:60] assign hi_513 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_514; // @[Debug.scala:1702:60] assign hi_514 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_515; // @[Debug.scala:1702:60] assign hi_515 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_516; // @[Debug.scala:1702:60] assign hi_516 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_517; // @[Debug.scala:1702:60] assign hi_517 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_518; // @[Debug.scala:1702:60] assign hi_518 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_519; // @[Debug.scala:1702:60] assign hi_519 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_520; // @[Debug.scala:1702:60] assign hi_520 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_521; // @[Debug.scala:1702:60] assign hi_521 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_522; // @[Debug.scala:1702:60] assign hi_522 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_523; // @[Debug.scala:1702:60] assign hi_523 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_524; // @[Debug.scala:1702:60] assign hi_524 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_525; // @[Debug.scala:1702:60] assign hi_525 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_526; // @[Debug.scala:1702:60] assign hi_526 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_527; // @[Debug.scala:1702:60] assign hi_527 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_528; // @[Debug.scala:1702:60] assign hi_528 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_529; // @[Debug.scala:1702:60] assign hi_529 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_530; // @[Debug.scala:1702:60] assign hi_530 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_531; // @[Debug.scala:1702:60] assign hi_531 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_532; // @[Debug.scala:1702:60] assign hi_532 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_533; // @[Debug.scala:1702:60] assign hi_533 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_534; // @[Debug.scala:1702:60] assign hi_534 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_535; // @[Debug.scala:1702:60] assign hi_535 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_536; // @[Debug.scala:1702:60] assign hi_536 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_537; // @[Debug.scala:1702:60] assign hi_537 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_538; // @[Debug.scala:1702:60] assign hi_538 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_539; // @[Debug.scala:1702:60] assign hi_539 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_540; // @[Debug.scala:1702:60] assign hi_540 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_541; // @[Debug.scala:1702:60] assign hi_541 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_542; // @[Debug.scala:1702:60] assign hi_542 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_543; // @[Debug.scala:1702:60] assign hi_543 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_544; // @[Debug.scala:1702:60] assign hi_544 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_545; // @[Debug.scala:1702:60] assign hi_545 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_546; // @[Debug.scala:1702:60] assign hi_546 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_547; // @[Debug.scala:1702:60] assign hi_547 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_548; // @[Debug.scala:1702:60] assign hi_548 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_549; // @[Debug.scala:1702:60] assign hi_549 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_550; // @[Debug.scala:1702:60] assign hi_550 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_551; // @[Debug.scala:1702:60] assign hi_551 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_552; // @[Debug.scala:1702:60] assign hi_552 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_553; // @[Debug.scala:1702:60] assign hi_553 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_554; // @[Debug.scala:1702:60] assign hi_554 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_555; // @[Debug.scala:1702:60] assign hi_555 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_556; // @[Debug.scala:1702:60] assign hi_556 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_557; // @[Debug.scala:1702:60] assign hi_557 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_558; // @[Debug.scala:1702:60] assign hi_558 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_559; // @[Debug.scala:1702:60] assign hi_559 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_560; // @[Debug.scala:1702:60] assign hi_560 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_561; // @[Debug.scala:1702:60] assign hi_561 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_562; // @[Debug.scala:1702:60] assign hi_562 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_563; // @[Debug.scala:1702:60] assign hi_563 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_564; // @[Debug.scala:1702:60] assign hi_564 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_565; // @[Debug.scala:1702:60] assign hi_565 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_566; // @[Debug.scala:1702:60] assign hi_566 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_567; // @[Debug.scala:1702:60] assign hi_567 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_568; // @[Debug.scala:1702:60] assign hi_568 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_569; // @[Debug.scala:1702:60] assign hi_569 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_570; // @[Debug.scala:1702:60] assign hi_570 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_571; // @[Debug.scala:1702:60] assign hi_571 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_572; // @[Debug.scala:1702:60] assign hi_572 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_573; // @[Debug.scala:1702:60] assign hi_573 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_574; // @[Debug.scala:1702:60] assign hi_574 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_575; // @[Debug.scala:1702:60] assign hi_575 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_576; // @[Debug.scala:1702:60] assign hi_576 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_577; // @[Debug.scala:1702:60] assign hi_577 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_578; // @[Debug.scala:1702:60] assign hi_578 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_579; // @[Debug.scala:1702:60] assign hi_579 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_580; // @[Debug.scala:1702:60] assign hi_580 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_581; // @[Debug.scala:1702:60] assign hi_581 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_582; // @[Debug.scala:1702:60] assign hi_582 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_583; // @[Debug.scala:1702:60] assign hi_583 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_584; // @[Debug.scala:1702:60] assign hi_584 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_585; // @[Debug.scala:1702:60] assign hi_585 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_586; // @[Debug.scala:1702:60] assign hi_586 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_587; // @[Debug.scala:1702:60] assign hi_587 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_588; // @[Debug.scala:1702:60] assign hi_588 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_589; // @[Debug.scala:1702:60] assign hi_589 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_590; // @[Debug.scala:1702:60] assign hi_590 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_591; // @[Debug.scala:1702:60] assign hi_591 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_592; // @[Debug.scala:1702:60] assign hi_592 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_593; // @[Debug.scala:1702:60] assign hi_593 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_594; // @[Debug.scala:1702:60] assign hi_594 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_595; // @[Debug.scala:1702:60] assign hi_595 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_596; // @[Debug.scala:1702:60] assign hi_596 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_597; // @[Debug.scala:1702:60] assign hi_597 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_598; // @[Debug.scala:1702:60] assign hi_598 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_599; // @[Debug.scala:1702:60] assign hi_599 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_600; // @[Debug.scala:1702:60] assign hi_600 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_601; // @[Debug.scala:1702:60] assign hi_601 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_602; // @[Debug.scala:1702:60] assign hi_602 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_603; // @[Debug.scala:1702:60] assign hi_603 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_604; // @[Debug.scala:1702:60] assign hi_604 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_605; // @[Debug.scala:1702:60] assign hi_605 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_606; // @[Debug.scala:1702:60] assign hi_606 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_607; // @[Debug.scala:1702:60] assign hi_607 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_608; // @[Debug.scala:1702:60] assign hi_608 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_609; // @[Debug.scala:1702:60] assign hi_609 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_610; // @[Debug.scala:1702:60] assign hi_610 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_611; // @[Debug.scala:1702:60] assign hi_611 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_612; // @[Debug.scala:1702:60] assign hi_612 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_613; // @[Debug.scala:1702:60] assign hi_613 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_614; // @[Debug.scala:1702:60] assign hi_614 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_615; // @[Debug.scala:1702:60] assign hi_615 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_616; // @[Debug.scala:1702:60] assign hi_616 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_617; // @[Debug.scala:1702:60] assign hi_617 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_618; // @[Debug.scala:1702:60] assign hi_618 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_619; // @[Debug.scala:1702:60] assign hi_619 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_620; // @[Debug.scala:1702:60] assign hi_620 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_621; // @[Debug.scala:1702:60] assign hi_621 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_622; // @[Debug.scala:1702:60] assign hi_622 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_623; // @[Debug.scala:1702:60] assign hi_623 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_624; // @[Debug.scala:1702:60] assign hi_624 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_625; // @[Debug.scala:1702:60] assign hi_625 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_626; // @[Debug.scala:1702:60] assign hi_626 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_627; // @[Debug.scala:1702:60] assign hi_627 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_628; // @[Debug.scala:1702:60] assign hi_628 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_629; // @[Debug.scala:1702:60] assign hi_629 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_630; // @[Debug.scala:1702:60] assign hi_630 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_631; // @[Debug.scala:1702:60] assign hi_631 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_632; // @[Debug.scala:1702:60] assign hi_632 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_633; // @[Debug.scala:1702:60] assign hi_633 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_634; // @[Debug.scala:1702:60] assign hi_634 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_635; // @[Debug.scala:1702:60] assign hi_635 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_636; // @[Debug.scala:1702:60] assign hi_636 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_637; // @[Debug.scala:1702:60] assign hi_637 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_638; // @[Debug.scala:1702:60] assign hi_638 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_639; // @[Debug.scala:1702:60] assign hi_639 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_640; // @[Debug.scala:1702:60] assign hi_640 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_641; // @[Debug.scala:1702:60] assign hi_641 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_642; // @[Debug.scala:1702:60] assign hi_642 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_643; // @[Debug.scala:1702:60] assign hi_643 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_644; // @[Debug.scala:1702:60] assign hi_644 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_645; // @[Debug.scala:1702:60] assign hi_645 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_646; // @[Debug.scala:1702:60] assign hi_646 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_647; // @[Debug.scala:1702:60] assign hi_647 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_648; // @[Debug.scala:1702:60] assign hi_648 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_649; // @[Debug.scala:1702:60] assign hi_649 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_650; // @[Debug.scala:1702:60] assign hi_650 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_651; // @[Debug.scala:1702:60] assign hi_651 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_652; // @[Debug.scala:1702:60] assign hi_652 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_653; // @[Debug.scala:1702:60] assign hi_653 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_654; // @[Debug.scala:1702:60] assign hi_654 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_655; // @[Debug.scala:1702:60] assign hi_655 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_656; // @[Debug.scala:1702:60] assign hi_656 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_657; // @[Debug.scala:1702:60] assign hi_657 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_658; // @[Debug.scala:1702:60] assign hi_658 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_659; // @[Debug.scala:1702:60] assign hi_659 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_660; // @[Debug.scala:1702:60] assign hi_660 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_661; // @[Debug.scala:1702:60] assign hi_661 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_662; // @[Debug.scala:1702:60] assign hi_662 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_663; // @[Debug.scala:1702:60] assign hi_663 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_664; // @[Debug.scala:1702:60] assign hi_664 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_665; // @[Debug.scala:1702:60] assign hi_665 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_666; // @[Debug.scala:1702:60] assign hi_666 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_667; // @[Debug.scala:1702:60] assign hi_667 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_668; // @[Debug.scala:1702:60] assign hi_668 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_669; // @[Debug.scala:1702:60] assign hi_669 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_670; // @[Debug.scala:1702:60] assign hi_670 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_671; // @[Debug.scala:1702:60] assign hi_671 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_672; // @[Debug.scala:1702:60] assign hi_672 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_673; // @[Debug.scala:1702:60] assign hi_673 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_674; // @[Debug.scala:1702:60] assign hi_674 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_675; // @[Debug.scala:1702:60] assign hi_675 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_676; // @[Debug.scala:1702:60] assign hi_676 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_677; // @[Debug.scala:1702:60] assign hi_677 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_678; // @[Debug.scala:1702:60] assign hi_678 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_679; // @[Debug.scala:1702:60] assign hi_679 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_680; // @[Debug.scala:1702:60] assign hi_680 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_681; // @[Debug.scala:1702:60] assign hi_681 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_682; // @[Debug.scala:1702:60] assign hi_682 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_683; // @[Debug.scala:1702:60] assign hi_683 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_684; // @[Debug.scala:1702:60] assign hi_684 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_685; // @[Debug.scala:1702:60] assign hi_685 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_686; // @[Debug.scala:1702:60] assign hi_686 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_687; // @[Debug.scala:1702:60] assign hi_687 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_688; // @[Debug.scala:1702:60] assign hi_688 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_689; // @[Debug.scala:1702:60] assign hi_689 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_690; // @[Debug.scala:1702:60] assign hi_690 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_691; // @[Debug.scala:1702:60] assign hi_691 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_692; // @[Debug.scala:1702:60] assign hi_692 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_693; // @[Debug.scala:1702:60] assign hi_693 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_694; // @[Debug.scala:1702:60] assign hi_694 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_695; // @[Debug.scala:1702:60] assign hi_695 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_696; // @[Debug.scala:1702:60] assign hi_696 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_697; // @[Debug.scala:1702:60] assign hi_697 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_698; // @[Debug.scala:1702:60] assign hi_698 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_699; // @[Debug.scala:1702:60] assign hi_699 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_700; // @[Debug.scala:1702:60] assign hi_700 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_701; // @[Debug.scala:1702:60] assign hi_701 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_702; // @[Debug.scala:1702:60] assign hi_702 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_703; // @[Debug.scala:1702:60] assign hi_703 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_704; // @[Debug.scala:1702:60] assign hi_704 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_705; // @[Debug.scala:1702:60] assign hi_705 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_706; // @[Debug.scala:1702:60] assign hi_706 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_707; // @[Debug.scala:1702:60] assign hi_707 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_708; // @[Debug.scala:1702:60] assign hi_708 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_709; // @[Debug.scala:1702:60] assign hi_709 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_710; // @[Debug.scala:1702:60] assign hi_710 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_711; // @[Debug.scala:1702:60] assign hi_711 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_712; // @[Debug.scala:1702:60] assign hi_712 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_713; // @[Debug.scala:1702:60] assign hi_713 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_714; // @[Debug.scala:1702:60] assign hi_714 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_715; // @[Debug.scala:1702:60] assign hi_715 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_716; // @[Debug.scala:1702:60] assign hi_716 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_717; // @[Debug.scala:1702:60] assign hi_717 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_718; // @[Debug.scala:1702:60] assign hi_718 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_719; // @[Debug.scala:1702:60] assign hi_719 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_720; // @[Debug.scala:1702:60] assign hi_720 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_721; // @[Debug.scala:1702:60] assign hi_721 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_722; // @[Debug.scala:1702:60] assign hi_722 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_723; // @[Debug.scala:1702:60] assign hi_723 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_724; // @[Debug.scala:1702:60] assign hi_724 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_725; // @[Debug.scala:1702:60] assign hi_725 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_726; // @[Debug.scala:1702:60] assign hi_726 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_727; // @[Debug.scala:1702:60] assign hi_727 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_728; // @[Debug.scala:1702:60] assign hi_728 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_729; // @[Debug.scala:1702:60] assign hi_729 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_730; // @[Debug.scala:1702:60] assign hi_730 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_731; // @[Debug.scala:1702:60] assign hi_731 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_732; // @[Debug.scala:1702:60] assign hi_732 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_733; // @[Debug.scala:1702:60] assign hi_733 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_734; // @[Debug.scala:1702:60] assign hi_734 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_735; // @[Debug.scala:1702:60] assign hi_735 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_736; // @[Debug.scala:1702:60] assign hi_736 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_737; // @[Debug.scala:1702:60] assign hi_737 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_738; // @[Debug.scala:1702:60] assign hi_738 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_739; // @[Debug.scala:1702:60] assign hi_739 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_740; // @[Debug.scala:1702:60] assign hi_740 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_741; // @[Debug.scala:1702:60] assign hi_741 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_742; // @[Debug.scala:1702:60] assign hi_742 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_743; // @[Debug.scala:1702:60] assign hi_743 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_744; // @[Debug.scala:1702:60] assign hi_744 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_745; // @[Debug.scala:1702:60] assign hi_745 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_746; // @[Debug.scala:1702:60] assign hi_746 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_747; // @[Debug.scala:1702:60] assign hi_747 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_748; // @[Debug.scala:1702:60] assign hi_748 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_749; // @[Debug.scala:1702:60] assign hi_749 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_750; // @[Debug.scala:1702:60] assign hi_750 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_751; // @[Debug.scala:1702:60] assign hi_751 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_752; // @[Debug.scala:1702:60] assign hi_752 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_753; // @[Debug.scala:1702:60] assign hi_753 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_754; // @[Debug.scala:1702:60] assign hi_754 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_755; // @[Debug.scala:1702:60] assign hi_755 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_756; // @[Debug.scala:1702:60] assign hi_756 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_757; // @[Debug.scala:1702:60] assign hi_757 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_758; // @[Debug.scala:1702:60] assign hi_758 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_759; // @[Debug.scala:1702:60] assign hi_759 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_760; // @[Debug.scala:1702:60] assign hi_760 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_761; // @[Debug.scala:1702:60] assign hi_761 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_762; // @[Debug.scala:1702:60] assign hi_762 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_763; // @[Debug.scala:1702:60] assign hi_763 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_764; // @[Debug.scala:1702:60] assign hi_764 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_765; // @[Debug.scala:1702:60] assign hi_765 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_766; // @[Debug.scala:1702:60] assign hi_766 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_767; // @[Debug.scala:1702:60] assign hi_767 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_768; // @[Debug.scala:1702:60] assign hi_768 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_769; // @[Debug.scala:1702:60] assign hi_769 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_770; // @[Debug.scala:1702:60] assign hi_770 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_771; // @[Debug.scala:1702:60] assign hi_771 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_772; // @[Debug.scala:1702:60] assign hi_772 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_773; // @[Debug.scala:1702:60] assign hi_773 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_774; // @[Debug.scala:1702:60] assign hi_774 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_775; // @[Debug.scala:1702:60] assign hi_775 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_776; // @[Debug.scala:1702:60] assign hi_776 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_777; // @[Debug.scala:1702:60] assign hi_777 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_778; // @[Debug.scala:1702:60] assign hi_778 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_779; // @[Debug.scala:1702:60] assign hi_779 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_780; // @[Debug.scala:1702:60] assign hi_780 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_781; // @[Debug.scala:1702:60] assign hi_781 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_782; // @[Debug.scala:1702:60] assign hi_782 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_783; // @[Debug.scala:1702:60] assign hi_783 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_784; // @[Debug.scala:1702:60] assign hi_784 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_785; // @[Debug.scala:1702:60] assign hi_785 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_786; // @[Debug.scala:1702:60] assign hi_786 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_787; // @[Debug.scala:1702:60] assign hi_787 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_788; // @[Debug.scala:1702:60] assign hi_788 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_789; // @[Debug.scala:1702:60] assign hi_789 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_790; // @[Debug.scala:1702:60] assign hi_790 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_791; // @[Debug.scala:1702:60] assign hi_791 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_792; // @[Debug.scala:1702:60] assign hi_792 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_793; // @[Debug.scala:1702:60] assign hi_793 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_794; // @[Debug.scala:1702:60] assign hi_794 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_795; // @[Debug.scala:1702:60] assign hi_795 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_796; // @[Debug.scala:1702:60] assign hi_796 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_797; // @[Debug.scala:1702:60] assign hi_797 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_798; // @[Debug.scala:1702:60] assign hi_798 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_799; // @[Debug.scala:1702:60] assign hi_799 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_800; // @[Debug.scala:1702:60] assign hi_800 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_801; // @[Debug.scala:1702:60] assign hi_801 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_802; // @[Debug.scala:1702:60] assign hi_802 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_803; // @[Debug.scala:1702:60] assign hi_803 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_804; // @[Debug.scala:1702:60] assign hi_804 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_805; // @[Debug.scala:1702:60] assign hi_805 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_806; // @[Debug.scala:1702:60] assign hi_806 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_807; // @[Debug.scala:1702:60] assign hi_807 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_808; // @[Debug.scala:1702:60] assign hi_808 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_809; // @[Debug.scala:1702:60] assign hi_809 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_810; // @[Debug.scala:1702:60] assign hi_810 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_811; // @[Debug.scala:1702:60] assign hi_811 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_812; // @[Debug.scala:1702:60] assign hi_812 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_813; // @[Debug.scala:1702:60] assign hi_813 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_814; // @[Debug.scala:1702:60] assign hi_814 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_815; // @[Debug.scala:1702:60] assign hi_815 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_816; // @[Debug.scala:1702:60] assign hi_816 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_817; // @[Debug.scala:1702:60] assign hi_817 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_818; // @[Debug.scala:1702:60] assign hi_818 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_819; // @[Debug.scala:1702:60] assign hi_819 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_820; // @[Debug.scala:1702:60] assign hi_820 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_821; // @[Debug.scala:1702:60] assign hi_821 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_822; // @[Debug.scala:1702:60] assign hi_822 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_823; // @[Debug.scala:1702:60] assign hi_823 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_824; // @[Debug.scala:1702:60] assign hi_824 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_825; // @[Debug.scala:1702:60] assign hi_825 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_826; // @[Debug.scala:1702:60] assign hi_826 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_827; // @[Debug.scala:1702:60] assign hi_827 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_828; // @[Debug.scala:1702:60] assign hi_828 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_829; // @[Debug.scala:1702:60] assign hi_829 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_830; // @[Debug.scala:1702:60] assign hi_830 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_831; // @[Debug.scala:1702:60] assign hi_831 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_832; // @[Debug.scala:1702:60] assign hi_832 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_833; // @[Debug.scala:1702:60] assign hi_833 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_834; // @[Debug.scala:1702:60] assign hi_834 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_835; // @[Debug.scala:1702:60] assign hi_835 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_836; // @[Debug.scala:1702:60] assign hi_836 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_837; // @[Debug.scala:1702:60] assign hi_837 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_838; // @[Debug.scala:1702:60] assign hi_838 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_839; // @[Debug.scala:1702:60] assign hi_839 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_840; // @[Debug.scala:1702:60] assign hi_840 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_841; // @[Debug.scala:1702:60] assign hi_841 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_842; // @[Debug.scala:1702:60] assign hi_842 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_843; // @[Debug.scala:1702:60] assign hi_843 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_844; // @[Debug.scala:1702:60] assign hi_844 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_845; // @[Debug.scala:1702:60] assign hi_845 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_846; // @[Debug.scala:1702:60] assign hi_846 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_847; // @[Debug.scala:1702:60] assign hi_847 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_848; // @[Debug.scala:1702:60] assign hi_848 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_849; // @[Debug.scala:1702:60] assign hi_849 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_850; // @[Debug.scala:1702:60] assign hi_850 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_851; // @[Debug.scala:1702:60] assign hi_851 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_852; // @[Debug.scala:1702:60] assign hi_852 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_853; // @[Debug.scala:1702:60] assign hi_853 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_854; // @[Debug.scala:1702:60] assign hi_854 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_855; // @[Debug.scala:1702:60] assign hi_855 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_856; // @[Debug.scala:1702:60] assign hi_856 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_857; // @[Debug.scala:1702:60] assign hi_857 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_858; // @[Debug.scala:1702:60] assign hi_858 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_859; // @[Debug.scala:1702:60] assign hi_859 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_860; // @[Debug.scala:1702:60] assign hi_860 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_861; // @[Debug.scala:1702:60] assign hi_861 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_862; // @[Debug.scala:1702:60] assign hi_862 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_863; // @[Debug.scala:1702:60] assign hi_863 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_864; // @[Debug.scala:1702:60] assign hi_864 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_865; // @[Debug.scala:1702:60] assign hi_865 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_866; // @[Debug.scala:1702:60] assign hi_866 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_867; // @[Debug.scala:1702:60] assign hi_867 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_868; // @[Debug.scala:1702:60] assign hi_868 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_869; // @[Debug.scala:1702:60] assign hi_869 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_870; // @[Debug.scala:1702:60] assign hi_870 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_871; // @[Debug.scala:1702:60] assign hi_871 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_872; // @[Debug.scala:1702:60] assign hi_872 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_873; // @[Debug.scala:1702:60] assign hi_873 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_874; // @[Debug.scala:1702:60] assign hi_874 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_875; // @[Debug.scala:1702:60] assign hi_875 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_876; // @[Debug.scala:1702:60] assign hi_876 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_877; // @[Debug.scala:1702:60] assign hi_877 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_878; // @[Debug.scala:1702:60] assign hi_878 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_879; // @[Debug.scala:1702:60] assign hi_879 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_880; // @[Debug.scala:1702:60] assign hi_880 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_881; // @[Debug.scala:1702:60] assign hi_881 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_882; // @[Debug.scala:1702:60] assign hi_882 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_883; // @[Debug.scala:1702:60] assign hi_883 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_884; // @[Debug.scala:1702:60] assign hi_884 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_885; // @[Debug.scala:1702:60] assign hi_885 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_886; // @[Debug.scala:1702:60] assign hi_886 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_887; // @[Debug.scala:1702:60] assign hi_887 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_888; // @[Debug.scala:1702:60] assign hi_888 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_889; // @[Debug.scala:1702:60] assign hi_889 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_890; // @[Debug.scala:1702:60] assign hi_890 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_891; // @[Debug.scala:1702:60] assign hi_891 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_892; // @[Debug.scala:1702:60] assign hi_892 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_893; // @[Debug.scala:1702:60] assign hi_893 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_894; // @[Debug.scala:1702:60] assign hi_894 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_895; // @[Debug.scala:1702:60] assign hi_895 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_896; // @[Debug.scala:1702:60] assign hi_896 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_897; // @[Debug.scala:1702:60] assign hi_897 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_898; // @[Debug.scala:1702:60] assign hi_898 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_899; // @[Debug.scala:1702:60] assign hi_899 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_900; // @[Debug.scala:1702:60] assign hi_900 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_901; // @[Debug.scala:1702:60] assign hi_901 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_902; // @[Debug.scala:1702:60] assign hi_902 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_903; // @[Debug.scala:1702:60] assign hi_903 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_904; // @[Debug.scala:1702:60] assign hi_904 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_905; // @[Debug.scala:1702:60] assign hi_905 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_906; // @[Debug.scala:1702:60] assign hi_906 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_907; // @[Debug.scala:1702:60] assign hi_907 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_908; // @[Debug.scala:1702:60] assign hi_908 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_909; // @[Debug.scala:1702:60] assign hi_909 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_910; // @[Debug.scala:1702:60] assign hi_910 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_911; // @[Debug.scala:1702:60] assign hi_911 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_912; // @[Debug.scala:1702:60] assign hi_912 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_913; // @[Debug.scala:1702:60] assign hi_913 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_914; // @[Debug.scala:1702:60] assign hi_914 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_915; // @[Debug.scala:1702:60] assign hi_915 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_916; // @[Debug.scala:1702:60] assign hi_916 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_917; // @[Debug.scala:1702:60] assign hi_917 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_918; // @[Debug.scala:1702:60] assign hi_918 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_919; // @[Debug.scala:1702:60] assign hi_919 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_920; // @[Debug.scala:1702:60] assign hi_920 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_921; // @[Debug.scala:1702:60] assign hi_921 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_922; // @[Debug.scala:1702:60] assign hi_922 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_923; // @[Debug.scala:1702:60] assign hi_923 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_924; // @[Debug.scala:1702:60] assign hi_924 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_925; // @[Debug.scala:1702:60] assign hi_925 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_926; // @[Debug.scala:1702:60] assign hi_926 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_927; // @[Debug.scala:1702:60] assign hi_927 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_928; // @[Debug.scala:1702:60] assign hi_928 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_929; // @[Debug.scala:1702:60] assign hi_929 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_930; // @[Debug.scala:1702:60] assign hi_930 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_931; // @[Debug.scala:1702:60] assign hi_931 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_932; // @[Debug.scala:1702:60] assign hi_932 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_933; // @[Debug.scala:1702:60] assign hi_933 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_934; // @[Debug.scala:1702:60] assign hi_934 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_935; // @[Debug.scala:1702:60] assign hi_935 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_936; // @[Debug.scala:1702:60] assign hi_936 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_937; // @[Debug.scala:1702:60] assign hi_937 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_938; // @[Debug.scala:1702:60] assign hi_938 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_939; // @[Debug.scala:1702:60] assign hi_939 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_940; // @[Debug.scala:1702:60] assign hi_940 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_941; // @[Debug.scala:1702:60] assign hi_941 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_942; // @[Debug.scala:1702:60] assign hi_942 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_943; // @[Debug.scala:1702:60] assign hi_943 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_944; // @[Debug.scala:1702:60] assign hi_944 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_945; // @[Debug.scala:1702:60] assign hi_945 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_946; // @[Debug.scala:1702:60] assign hi_946 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_947; // @[Debug.scala:1702:60] assign hi_947 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_948; // @[Debug.scala:1702:60] assign hi_948 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_949; // @[Debug.scala:1702:60] assign hi_949 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_950; // @[Debug.scala:1702:60] assign hi_950 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_951; // @[Debug.scala:1702:60] assign hi_951 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_952; // @[Debug.scala:1702:60] assign hi_952 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_953; // @[Debug.scala:1702:60] assign hi_953 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_954; // @[Debug.scala:1702:60] assign hi_954 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_955; // @[Debug.scala:1702:60] assign hi_955 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_956; // @[Debug.scala:1702:60] assign hi_956 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_957; // @[Debug.scala:1702:60] assign hi_957 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_958; // @[Debug.scala:1702:60] assign hi_958 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_959; // @[Debug.scala:1702:60] assign hi_959 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_960; // @[Debug.scala:1702:60] assign hi_960 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_961; // @[Debug.scala:1702:60] assign hi_961 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_962; // @[Debug.scala:1702:60] assign hi_962 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_963; // @[Debug.scala:1702:60] assign hi_963 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_964; // @[Debug.scala:1702:60] assign hi_964 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_965; // @[Debug.scala:1702:60] assign hi_965 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_966; // @[Debug.scala:1702:60] assign hi_966 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_967; // @[Debug.scala:1702:60] assign hi_967 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_968; // @[Debug.scala:1702:60] assign hi_968 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_969; // @[Debug.scala:1702:60] assign hi_969 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_970; // @[Debug.scala:1702:60] assign hi_970 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_971; // @[Debug.scala:1702:60] assign hi_971 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_972; // @[Debug.scala:1702:60] assign hi_972 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_973; // @[Debug.scala:1702:60] assign hi_973 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_974; // @[Debug.scala:1702:60] assign hi_974 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_975; // @[Debug.scala:1702:60] assign hi_975 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_976; // @[Debug.scala:1702:60] assign hi_976 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_977; // @[Debug.scala:1702:60] assign hi_977 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_978; // @[Debug.scala:1702:60] assign hi_978 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_979; // @[Debug.scala:1702:60] assign hi_979 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_980; // @[Debug.scala:1702:60] assign hi_980 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_981; // @[Debug.scala:1702:60] assign hi_981 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_982; // @[Debug.scala:1702:60] assign hi_982 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_983; // @[Debug.scala:1702:60] assign hi_983 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_984; // @[Debug.scala:1702:60] assign hi_984 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_985; // @[Debug.scala:1702:60] assign hi_985 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_986; // @[Debug.scala:1702:60] assign hi_986 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_987; // @[Debug.scala:1702:60] assign hi_987 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_988; // @[Debug.scala:1702:60] assign hi_988 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_989; // @[Debug.scala:1702:60] assign hi_989 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_990; // @[Debug.scala:1702:60] assign hi_990 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_991; // @[Debug.scala:1702:60] assign hi_991 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_992; // @[Debug.scala:1702:60] assign hi_992 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_993; // @[Debug.scala:1702:60] assign hi_993 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_994; // @[Debug.scala:1702:60] assign hi_994 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_995; // @[Debug.scala:1702:60] assign hi_995 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_996; // @[Debug.scala:1702:60] assign hi_996 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_997; // @[Debug.scala:1702:60] assign hi_997 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_998; // @[Debug.scala:1702:60] assign hi_998 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_999; // @[Debug.scala:1702:60] assign hi_999 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1000; // @[Debug.scala:1702:60] assign hi_1000 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1001; // @[Debug.scala:1702:60] assign hi_1001 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1002; // @[Debug.scala:1702:60] assign hi_1002 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1003; // @[Debug.scala:1702:60] assign hi_1003 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1004; // @[Debug.scala:1702:60] assign hi_1004 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1005; // @[Debug.scala:1702:60] assign hi_1005 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1006; // @[Debug.scala:1702:60] assign hi_1006 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1007; // @[Debug.scala:1702:60] assign hi_1007 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1008; // @[Debug.scala:1702:60] assign hi_1008 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1009; // @[Debug.scala:1702:60] assign hi_1009 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1010; // @[Debug.scala:1702:60] assign hi_1010 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1011; // @[Debug.scala:1702:60] assign hi_1011 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1012; // @[Debug.scala:1702:60] assign hi_1012 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1013; // @[Debug.scala:1702:60] assign hi_1013 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1014; // @[Debug.scala:1702:60] assign hi_1014 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1015; // @[Debug.scala:1702:60] assign hi_1015 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1016; // @[Debug.scala:1702:60] assign hi_1016 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1017; // @[Debug.scala:1702:60] assign hi_1017 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1018; // @[Debug.scala:1702:60] assign hi_1018 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1019; // @[Debug.scala:1702:60] assign hi_1019 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1020; // @[Debug.scala:1702:60] assign hi_1020 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1021; // @[Debug.scala:1702:60] assign hi_1021 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1022; // @[Debug.scala:1702:60] assign hi_1022 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1023; // @[Debug.scala:1702:60] assign hi_1023 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1024; // @[Debug.scala:1702:60] assign hi_1024 = _GEN_16; // @[Debug.scala:1702:60] wire [7:0] _out_T_6436 = {hi_1, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6184 = {hi_9, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8824 = {hi_17, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12272 = {hi_25, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4125 = {hi_33, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4197 = {hi_41, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6256 = {hi_49, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8968 = {hi_57, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11984 = {hi_65, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4989 = {hi_73, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1917 = {hi_81, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11032 = {hi_89, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8304 = {hi_97, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5655 = {hi_105, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2509 = {hi_113, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10208 = {hi_121, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7478 = {hi_129, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9632 = {hi_137, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11464 = {hi_145, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3981 = {hi_153, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6830 = {hi_161, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7118 = {hi_169, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9704 = {hi_177, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11392 = {hi_185, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3245 = {hi_193, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2581 = {hi_201, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10064 = {hi_209, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8448 = {hi_217, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5439 = {hi_225, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3101 = {hi_233, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10728 = {hi_241, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7694 = {hi_249, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4845 = {hi_257, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6974 = {hi_265, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9256 = {hi_273, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12416 = {hi_281, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3533 = {hi_289, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5061 = {hi_297, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6740 = {hi_305, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9184 = {hi_313, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11680 = {hi_321, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5583 = {hi_329, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2133 = {hi_337, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10960 = {hi_345, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7838 = {hi_353, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6112 = {hi_361, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2653 = {hi_369, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10136 = {hi_377, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7190 = {hi_385, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9920 = {hi_393, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12344 = {hi_401, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3605 = {hi_409, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7046 = {hi_417, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7622 = {hi_425, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9992 = {hi_433, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11608 = {hi_441, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2869 = {hi_449, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2725 = {hi_457, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10800 = {hi_465, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7766 = {hi_473, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5511 = {hi_481, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3173 = {hi_489, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11536 = {hi_497, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7262 = {hi_505, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4917 = {hi_513, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5799 = {hi_521, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9560 = {hi_529, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12056 = {hi_537, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3029 = {hi_545, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5295 = {hi_553, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8520 = {hi_561, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9848 = {hi_569, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12488 = {hi_577, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4629 = {hi_585, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2437 = {hi_593, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10280 = {hi_601, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7334 = {hi_609, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6364 = {hi_617, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4413 = {hi_625, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11104 = {hi_633, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8214 = {hi_641, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9400 = {hi_649, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11824 = {hi_657, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3837 = {hi_665, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5871 = {hi_673, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8376 = {hi_681, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11176 = {hi_689, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12648 = {hi_697, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3461 = {hi_705, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2293 = {hi_713, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10352 = {hi_721, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7998 = {hi_729, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4701 = {hi_737, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4053 = {hi_745, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12720 = {hi_753, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8896 = {hi_761, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5367 = {hi_769, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5727 = {hi_777, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9040 = {hi_785, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12936 = {hi_793, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3317 = {hi_801, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5151 = {hi_809, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8070 = {hi_817, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10584 = {hi_825, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12792 = {hi_833, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4485 = {hi_841, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2061 = {hi_849, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11248 = {hi_857, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7550 = {hi_865, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6508 = {hi_873, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3765 = {hi_881, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12128 = {hi_889, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8680 = {hi_897, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9112 = {hi_905, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12200 = {hi_913, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4269 = {hi_921, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6668 = {hi_929, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8142 = {hi_937, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11320 = {hi_945, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2365 = {hi_953, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4557 = {hi_961, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1989 = {hi_969, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10512 = {hi_977, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8752 = {hi_985, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5223 = {hi_993, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3909 = {hi_1001, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12864 = {hi_1009, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9328 = {hi_1017, flags_0_go}; // @[RegisterRouter.scala:87:24] wire _out_in_ready_T_1; // @[RegisterRouter.scala:87:24] assign tlNodeIn_a_ready = in_1_ready; // @[RegisterRouter.scala:73:18] wire _in_bits_read_T_1; // @[RegisterRouter.scala:74:36] wire _out_front_valid_T_1 = in_1_valid; // @[RegisterRouter.scala:73:18, :87:24] wire [8:0] _in_bits_index_T_1; // @[Edges.scala:192:34] wire out_front_1_bits_read = in_1_bits_read; // @[RegisterRouter.scala:73:18, :87:24] wire [8:0] out_front_1_bits_index = in_1_bits_index; // @[RegisterRouter.scala:73:18, :87:24] wire [63:0] out_front_1_bits_data = in_1_bits_data; // @[RegisterRouter.scala:73:18, :87:24] wire [7:0] out_front_1_bits_mask = in_1_bits_mask; // @[RegisterRouter.scala:73:18, :87:24] wire [10:0] out_front_1_bits_extra_tlrr_extra_source = in_1_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24] wire [1:0] out_front_1_bits_extra_tlrr_extra_size = in_1_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24] assign _in_bits_read_T_1 = tlNodeIn_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] assign in_1_bits_read = _in_bits_read_T_1; // @[RegisterRouter.scala:73:18, :74:36] assign _in_bits_index_T_1 = tlNodeIn_a_bits_address[11:3]; // @[Edges.scala:192:34] assign in_1_bits_index = _in_bits_index_T_1; // @[RegisterRouter.scala:73:18] wire _out_front_ready_T_1 = out_1_ready; // @[RegisterRouter.scala:87:24] wire _out_out_valid_T_1; // @[RegisterRouter.scala:87:24] assign tlNodeIn_d_valid = out_1_valid; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_T_9; // @[RegisterRouter.scala:87:24] wire _tlNodeIn_d_bits_opcode_T = out_1_bits_read; // @[RegisterRouter.scala:87:24, :105:25] assign tlNodeIn_d_bits_data = out_1_bits_data; // @[RegisterRouter.scala:87:24] assign tlNodeIn_d_bits_d_source = out_1_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [1:0] out_1_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign tlNodeIn_d_bits_d_size = out_1_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign _out_in_ready_T_1 = out_front_1_ready; // @[RegisterRouter.scala:87:24] assign _out_out_valid_T_1 = out_front_1_valid; // @[RegisterRouter.scala:87:24] assign out_1_bits_read = out_front_1_bits_read; // @[RegisterRouter.scala:87:24] assign out_1_bits_extra_tlrr_extra_source = out_front_1_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] assign out_1_bits_extra_tlrr_extra_size = out_front_1_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] wire [8:0] _GEN_17 = out_front_1_bits_index & 9'h100; // @[RegisterRouter.scala:87:24] wire [8:0] out_findex_1; // @[RegisterRouter.scala:87:24] assign out_findex_1 = _GEN_17; // @[RegisterRouter.scala:87:24] wire [8:0] out_bindex_1; // @[RegisterRouter.scala:87:24] assign out_bindex_1 = _GEN_17; // @[RegisterRouter.scala:87:24] wire _GEN_18 = out_findex_1 == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_T_1600; // @[RegisterRouter.scala:87:24] assign _out_T_1600 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1602; // @[RegisterRouter.scala:87:24] assign _out_T_1602 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1604; // @[RegisterRouter.scala:87:24] assign _out_T_1604 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1606; // @[RegisterRouter.scala:87:24] assign _out_T_1606 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1608; // @[RegisterRouter.scala:87:24] assign _out_T_1608 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1610; // @[RegisterRouter.scala:87:24] assign _out_T_1610 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1612; // @[RegisterRouter.scala:87:24] assign _out_T_1612 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1614; // @[RegisterRouter.scala:87:24] assign _out_T_1614 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1616; // @[RegisterRouter.scala:87:24] assign _out_T_1616 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1618; // @[RegisterRouter.scala:87:24] assign _out_T_1618 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1620; // @[RegisterRouter.scala:87:24] assign _out_T_1620 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1622; // @[RegisterRouter.scala:87:24] assign _out_T_1622 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1626; // @[RegisterRouter.scala:87:24] assign _out_T_1626 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1628; // @[RegisterRouter.scala:87:24] assign _out_T_1628 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1630; // @[RegisterRouter.scala:87:24] assign _out_T_1630 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1632; // @[RegisterRouter.scala:87:24] assign _out_T_1632 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1634; // @[RegisterRouter.scala:87:24] assign _out_T_1634 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1636; // @[RegisterRouter.scala:87:24] assign _out_T_1636 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1638; // @[RegisterRouter.scala:87:24] assign _out_T_1638 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1642; // @[RegisterRouter.scala:87:24] assign _out_T_1642 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1644; // @[RegisterRouter.scala:87:24] assign _out_T_1644 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1646; // @[RegisterRouter.scala:87:24] assign _out_T_1646 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1648; // @[RegisterRouter.scala:87:24] assign _out_T_1648 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1650; // @[RegisterRouter.scala:87:24] assign _out_T_1650 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1652; // @[RegisterRouter.scala:87:24] assign _out_T_1652 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1654; // @[RegisterRouter.scala:87:24] assign _out_T_1654 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1656; // @[RegisterRouter.scala:87:24] assign _out_T_1656 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1658; // @[RegisterRouter.scala:87:24] assign _out_T_1658 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1660; // @[RegisterRouter.scala:87:24] assign _out_T_1660 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1662; // @[RegisterRouter.scala:87:24] assign _out_T_1662 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1664; // @[RegisterRouter.scala:87:24] assign _out_T_1664 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1668; // @[RegisterRouter.scala:87:24] assign _out_T_1668 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1670; // @[RegisterRouter.scala:87:24] assign _out_T_1670 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1672; // @[RegisterRouter.scala:87:24] assign _out_T_1672 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1674; // @[RegisterRouter.scala:87:24] assign _out_T_1674 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1676; // @[RegisterRouter.scala:87:24] assign _out_T_1676 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1680; // @[RegisterRouter.scala:87:24] assign _out_T_1680 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1682; // @[RegisterRouter.scala:87:24] assign _out_T_1682 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1684; // @[RegisterRouter.scala:87:24] assign _out_T_1684 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1686; // @[RegisterRouter.scala:87:24] assign _out_T_1686 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1688; // @[RegisterRouter.scala:87:24] assign _out_T_1688 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1690; // @[RegisterRouter.scala:87:24] assign _out_T_1690 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1692; // @[RegisterRouter.scala:87:24] assign _out_T_1692 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1694; // @[RegisterRouter.scala:87:24] assign _out_T_1694 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1696; // @[RegisterRouter.scala:87:24] assign _out_T_1696 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1698; // @[RegisterRouter.scala:87:24] assign _out_T_1698 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1700; // @[RegisterRouter.scala:87:24] assign _out_T_1700 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1702; // @[RegisterRouter.scala:87:24] assign _out_T_1702 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1704; // @[RegisterRouter.scala:87:24] assign _out_T_1704 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1706; // @[RegisterRouter.scala:87:24] assign _out_T_1706 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1708; // @[RegisterRouter.scala:87:24] assign _out_T_1708 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1710; // @[RegisterRouter.scala:87:24] assign _out_T_1710 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1712; // @[RegisterRouter.scala:87:24] assign _out_T_1712 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1714; // @[RegisterRouter.scala:87:24] assign _out_T_1714 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1718; // @[RegisterRouter.scala:87:24] assign _out_T_1718 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1720; // @[RegisterRouter.scala:87:24] assign _out_T_1720 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1722; // @[RegisterRouter.scala:87:24] assign _out_T_1722 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1726; // @[RegisterRouter.scala:87:24] assign _out_T_1726 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1728; // @[RegisterRouter.scala:87:24] assign _out_T_1728 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1730; // @[RegisterRouter.scala:87:24] assign _out_T_1730 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1732; // @[RegisterRouter.scala:87:24] assign _out_T_1732 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1734; // @[RegisterRouter.scala:87:24] assign _out_T_1734 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1736; // @[RegisterRouter.scala:87:24] assign _out_T_1736 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1738; // @[RegisterRouter.scala:87:24] assign _out_T_1738 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1740; // @[RegisterRouter.scala:87:24] assign _out_T_1740 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1744; // @[RegisterRouter.scala:87:24] assign _out_T_1744 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1746; // @[RegisterRouter.scala:87:24] assign _out_T_1746 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1748; // @[RegisterRouter.scala:87:24] assign _out_T_1748 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1750; // @[RegisterRouter.scala:87:24] assign _out_T_1750 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1752; // @[RegisterRouter.scala:87:24] assign _out_T_1752 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1754; // @[RegisterRouter.scala:87:24] assign _out_T_1754 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1758; // @[RegisterRouter.scala:87:24] assign _out_T_1758 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1760; // @[RegisterRouter.scala:87:24] assign _out_T_1760 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1762; // @[RegisterRouter.scala:87:24] assign _out_T_1762 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1764; // @[RegisterRouter.scala:87:24] assign _out_T_1764 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1766; // @[RegisterRouter.scala:87:24] assign _out_T_1766 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1768; // @[RegisterRouter.scala:87:24] assign _out_T_1768 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1770; // @[RegisterRouter.scala:87:24] assign _out_T_1770 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1772; // @[RegisterRouter.scala:87:24] assign _out_T_1772 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1774; // @[RegisterRouter.scala:87:24] assign _out_T_1774 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1776; // @[RegisterRouter.scala:87:24] assign _out_T_1776 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1778; // @[RegisterRouter.scala:87:24] assign _out_T_1778 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1780; // @[RegisterRouter.scala:87:24] assign _out_T_1780 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1782; // @[RegisterRouter.scala:87:24] assign _out_T_1782 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1784; // @[RegisterRouter.scala:87:24] assign _out_T_1784 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1786; // @[RegisterRouter.scala:87:24] assign _out_T_1786 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1788; // @[RegisterRouter.scala:87:24] assign _out_T_1788 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1790; // @[RegisterRouter.scala:87:24] assign _out_T_1790 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1792; // @[RegisterRouter.scala:87:24] assign _out_T_1792 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1794; // @[RegisterRouter.scala:87:24] assign _out_T_1794 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1796; // @[RegisterRouter.scala:87:24] assign _out_T_1796 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1798; // @[RegisterRouter.scala:87:24] assign _out_T_1798 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1800; // @[RegisterRouter.scala:87:24] assign _out_T_1800 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1802; // @[RegisterRouter.scala:87:24] assign _out_T_1802 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1804; // @[RegisterRouter.scala:87:24] assign _out_T_1804 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1806; // @[RegisterRouter.scala:87:24] assign _out_T_1806 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1808; // @[RegisterRouter.scala:87:24] assign _out_T_1808 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1810; // @[RegisterRouter.scala:87:24] assign _out_T_1810 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1812; // @[RegisterRouter.scala:87:24] assign _out_T_1812 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1814; // @[RegisterRouter.scala:87:24] assign _out_T_1814 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1816; // @[RegisterRouter.scala:87:24] assign _out_T_1816 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1818; // @[RegisterRouter.scala:87:24] assign _out_T_1818 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1820; // @[RegisterRouter.scala:87:24] assign _out_T_1820 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1824; // @[RegisterRouter.scala:87:24] assign _out_T_1824 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1826; // @[RegisterRouter.scala:87:24] assign _out_T_1826 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1828; // @[RegisterRouter.scala:87:24] assign _out_T_1828 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1830; // @[RegisterRouter.scala:87:24] assign _out_T_1830 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1832; // @[RegisterRouter.scala:87:24] assign _out_T_1832 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1834; // @[RegisterRouter.scala:87:24] assign _out_T_1834 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1836; // @[RegisterRouter.scala:87:24] assign _out_T_1836 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1838; // @[RegisterRouter.scala:87:24] assign _out_T_1838 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1840; // @[RegisterRouter.scala:87:24] assign _out_T_1840 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1842; // @[RegisterRouter.scala:87:24] assign _out_T_1842 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1844; // @[RegisterRouter.scala:87:24] assign _out_T_1844 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1848; // @[RegisterRouter.scala:87:24] assign _out_T_1848 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1850; // @[RegisterRouter.scala:87:24] assign _out_T_1850 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1852; // @[RegisterRouter.scala:87:24] assign _out_T_1852 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1854; // @[RegisterRouter.scala:87:24] assign _out_T_1854 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1856; // @[RegisterRouter.scala:87:24] assign _out_T_1856 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1858; // @[RegisterRouter.scala:87:24] assign _out_T_1858 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1860; // @[RegisterRouter.scala:87:24] assign _out_T_1860 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1862; // @[RegisterRouter.scala:87:24] assign _out_T_1862 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1864; // @[RegisterRouter.scala:87:24] assign _out_T_1864 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1866; // @[RegisterRouter.scala:87:24] assign _out_T_1866 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1868; // @[RegisterRouter.scala:87:24] assign _out_T_1868 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1870; // @[RegisterRouter.scala:87:24] assign _out_T_1870 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1872; // @[RegisterRouter.scala:87:24] assign _out_T_1872 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1874; // @[RegisterRouter.scala:87:24] assign _out_T_1874 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1878; // @[RegisterRouter.scala:87:24] assign _out_T_1878 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1880; // @[RegisterRouter.scala:87:24] assign _out_T_1880 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1882; // @[RegisterRouter.scala:87:24] assign _out_T_1882 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1884; // @[RegisterRouter.scala:87:24] assign _out_T_1884 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1886; // @[RegisterRouter.scala:87:24] assign _out_T_1886 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1888; // @[RegisterRouter.scala:87:24] assign _out_T_1888 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1890; // @[RegisterRouter.scala:87:24] assign _out_T_1890 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1892; // @[RegisterRouter.scala:87:24] assign _out_T_1892 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1894; // @[RegisterRouter.scala:87:24] assign _out_T_1894 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1896; // @[RegisterRouter.scala:87:24] assign _out_T_1896 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1898; // @[RegisterRouter.scala:87:24] assign _out_T_1898 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1900; // @[RegisterRouter.scala:87:24] assign _out_T_1900 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1902; // @[RegisterRouter.scala:87:24] assign _out_T_1902 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1904; // @[RegisterRouter.scala:87:24] assign _out_T_1904 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1906; // @[RegisterRouter.scala:87:24] assign _out_T_1906 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1908; // @[RegisterRouter.scala:87:24] assign _out_T_1908 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _GEN_19 = out_bindex_1 == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_T_1601; // @[RegisterRouter.scala:87:24] assign _out_T_1601 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1603; // @[RegisterRouter.scala:87:24] assign _out_T_1603 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1605; // @[RegisterRouter.scala:87:24] assign _out_T_1605 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1607; // @[RegisterRouter.scala:87:24] assign _out_T_1607 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1609; // @[RegisterRouter.scala:87:24] assign _out_T_1609 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1611; // @[RegisterRouter.scala:87:24] assign _out_T_1611 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1613; // @[RegisterRouter.scala:87:24] assign _out_T_1613 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1615; // @[RegisterRouter.scala:87:24] assign _out_T_1615 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1617; // @[RegisterRouter.scala:87:24] assign _out_T_1617 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1619; // @[RegisterRouter.scala:87:24] assign _out_T_1619 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1621; // @[RegisterRouter.scala:87:24] assign _out_T_1621 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1623; // @[RegisterRouter.scala:87:24] assign _out_T_1623 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1627; // @[RegisterRouter.scala:87:24] assign _out_T_1627 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1629; // @[RegisterRouter.scala:87:24] assign _out_T_1629 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1631; // @[RegisterRouter.scala:87:24] assign _out_T_1631 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1633; // @[RegisterRouter.scala:87:24] assign _out_T_1633 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1635; // @[RegisterRouter.scala:87:24] assign _out_T_1635 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1637; // @[RegisterRouter.scala:87:24] assign _out_T_1637 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1639; // @[RegisterRouter.scala:87:24] assign _out_T_1639 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1643; // @[RegisterRouter.scala:87:24] assign _out_T_1643 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1645; // @[RegisterRouter.scala:87:24] assign _out_T_1645 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1647; // @[RegisterRouter.scala:87:24] assign _out_T_1647 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1649; // @[RegisterRouter.scala:87:24] assign _out_T_1649 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1651; // @[RegisterRouter.scala:87:24] assign _out_T_1651 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1653; // @[RegisterRouter.scala:87:24] assign _out_T_1653 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1655; // @[RegisterRouter.scala:87:24] assign _out_T_1655 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1657; // @[RegisterRouter.scala:87:24] assign _out_T_1657 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1659; // @[RegisterRouter.scala:87:24] assign _out_T_1659 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1661; // @[RegisterRouter.scala:87:24] assign _out_T_1661 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1663; // @[RegisterRouter.scala:87:24] assign _out_T_1663 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1665; // @[RegisterRouter.scala:87:24] assign _out_T_1665 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1669; // @[RegisterRouter.scala:87:24] assign _out_T_1669 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1671; // @[RegisterRouter.scala:87:24] assign _out_T_1671 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1673; // @[RegisterRouter.scala:87:24] assign _out_T_1673 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1675; // @[RegisterRouter.scala:87:24] assign _out_T_1675 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1677; // @[RegisterRouter.scala:87:24] assign _out_T_1677 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1681; // @[RegisterRouter.scala:87:24] assign _out_T_1681 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1683; // @[RegisterRouter.scala:87:24] assign _out_T_1683 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1685; // @[RegisterRouter.scala:87:24] assign _out_T_1685 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1687; // @[RegisterRouter.scala:87:24] assign _out_T_1687 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1689; // @[RegisterRouter.scala:87:24] assign _out_T_1689 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1691; // @[RegisterRouter.scala:87:24] assign _out_T_1691 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1693; // @[RegisterRouter.scala:87:24] assign _out_T_1693 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1695; // @[RegisterRouter.scala:87:24] assign _out_T_1695 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1697; // @[RegisterRouter.scala:87:24] assign _out_T_1697 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1699; // @[RegisterRouter.scala:87:24] assign _out_T_1699 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1701; // @[RegisterRouter.scala:87:24] assign _out_T_1701 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1703; // @[RegisterRouter.scala:87:24] assign _out_T_1703 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1705; // @[RegisterRouter.scala:87:24] assign _out_T_1705 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1707; // @[RegisterRouter.scala:87:24] assign _out_T_1707 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1709; // @[RegisterRouter.scala:87:24] assign _out_T_1709 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1711; // @[RegisterRouter.scala:87:24] assign _out_T_1711 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1713; // @[RegisterRouter.scala:87:24] assign _out_T_1713 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1715; // @[RegisterRouter.scala:87:24] assign _out_T_1715 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1719; // @[RegisterRouter.scala:87:24] assign _out_T_1719 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1721; // @[RegisterRouter.scala:87:24] assign _out_T_1721 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1723; // @[RegisterRouter.scala:87:24] assign _out_T_1723 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1727; // @[RegisterRouter.scala:87:24] assign _out_T_1727 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1729; // @[RegisterRouter.scala:87:24] assign _out_T_1729 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1731; // @[RegisterRouter.scala:87:24] assign _out_T_1731 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1733; // @[RegisterRouter.scala:87:24] assign _out_T_1733 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1735; // @[RegisterRouter.scala:87:24] assign _out_T_1735 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1737; // @[RegisterRouter.scala:87:24] assign _out_T_1737 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1739; // @[RegisterRouter.scala:87:24] assign _out_T_1739 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1741; // @[RegisterRouter.scala:87:24] assign _out_T_1741 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1745; // @[RegisterRouter.scala:87:24] assign _out_T_1745 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1747; // @[RegisterRouter.scala:87:24] assign _out_T_1747 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1749; // @[RegisterRouter.scala:87:24] assign _out_T_1749 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1751; // @[RegisterRouter.scala:87:24] assign _out_T_1751 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1753; // @[RegisterRouter.scala:87:24] assign _out_T_1753 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1755; // @[RegisterRouter.scala:87:24] assign _out_T_1755 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1759; // @[RegisterRouter.scala:87:24] assign _out_T_1759 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1761; // @[RegisterRouter.scala:87:24] assign _out_T_1761 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1763; // @[RegisterRouter.scala:87:24] assign _out_T_1763 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1765; // @[RegisterRouter.scala:87:24] assign _out_T_1765 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1767; // @[RegisterRouter.scala:87:24] assign _out_T_1767 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1769; // @[RegisterRouter.scala:87:24] assign _out_T_1769 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1771; // @[RegisterRouter.scala:87:24] assign _out_T_1771 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1773; // @[RegisterRouter.scala:87:24] assign _out_T_1773 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1775; // @[RegisterRouter.scala:87:24] assign _out_T_1775 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1777; // @[RegisterRouter.scala:87:24] assign _out_T_1777 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1779; // @[RegisterRouter.scala:87:24] assign _out_T_1779 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1781; // @[RegisterRouter.scala:87:24] assign _out_T_1781 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1783; // @[RegisterRouter.scala:87:24] assign _out_T_1783 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1785; // @[RegisterRouter.scala:87:24] assign _out_T_1785 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1787; // @[RegisterRouter.scala:87:24] assign _out_T_1787 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1789; // @[RegisterRouter.scala:87:24] assign _out_T_1789 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1791; // @[RegisterRouter.scala:87:24] assign _out_T_1791 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1793; // @[RegisterRouter.scala:87:24] assign _out_T_1793 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1795; // @[RegisterRouter.scala:87:24] assign _out_T_1795 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1797; // @[RegisterRouter.scala:87:24] assign _out_T_1797 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1799; // @[RegisterRouter.scala:87:24] assign _out_T_1799 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1801; // @[RegisterRouter.scala:87:24] assign _out_T_1801 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1803; // @[RegisterRouter.scala:87:24] assign _out_T_1803 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1805; // @[RegisterRouter.scala:87:24] assign _out_T_1805 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1807; // @[RegisterRouter.scala:87:24] assign _out_T_1807 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1809; // @[RegisterRouter.scala:87:24] assign _out_T_1809 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1811; // @[RegisterRouter.scala:87:24] assign _out_T_1811 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1813; // @[RegisterRouter.scala:87:24] assign _out_T_1813 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1815; // @[RegisterRouter.scala:87:24] assign _out_T_1815 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1817; // @[RegisterRouter.scala:87:24] assign _out_T_1817 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1819; // @[RegisterRouter.scala:87:24] assign _out_T_1819 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1821; // @[RegisterRouter.scala:87:24] assign _out_T_1821 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1825; // @[RegisterRouter.scala:87:24] assign _out_T_1825 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1827; // @[RegisterRouter.scala:87:24] assign _out_T_1827 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1829; // @[RegisterRouter.scala:87:24] assign _out_T_1829 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1831; // @[RegisterRouter.scala:87:24] assign _out_T_1831 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1833; // @[RegisterRouter.scala:87:24] assign _out_T_1833 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1835; // @[RegisterRouter.scala:87:24] assign _out_T_1835 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1837; // @[RegisterRouter.scala:87:24] assign _out_T_1837 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1839; // @[RegisterRouter.scala:87:24] assign _out_T_1839 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1841; // @[RegisterRouter.scala:87:24] assign _out_T_1841 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1843; // @[RegisterRouter.scala:87:24] assign _out_T_1843 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1845; // @[RegisterRouter.scala:87:24] assign _out_T_1845 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1849; // @[RegisterRouter.scala:87:24] assign _out_T_1849 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1851; // @[RegisterRouter.scala:87:24] assign _out_T_1851 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1853; // @[RegisterRouter.scala:87:24] assign _out_T_1853 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1855; // @[RegisterRouter.scala:87:24] assign _out_T_1855 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1857; // @[RegisterRouter.scala:87:24] assign _out_T_1857 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1859; // @[RegisterRouter.scala:87:24] assign _out_T_1859 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1861; // @[RegisterRouter.scala:87:24] assign _out_T_1861 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1863; // @[RegisterRouter.scala:87:24] assign _out_T_1863 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1865; // @[RegisterRouter.scala:87:24] assign _out_T_1865 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1867; // @[RegisterRouter.scala:87:24] assign _out_T_1867 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1869; // @[RegisterRouter.scala:87:24] assign _out_T_1869 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1871; // @[RegisterRouter.scala:87:24] assign _out_T_1871 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1873; // @[RegisterRouter.scala:87:24] assign _out_T_1873 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1875; // @[RegisterRouter.scala:87:24] assign _out_T_1875 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1879; // @[RegisterRouter.scala:87:24] assign _out_T_1879 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1881; // @[RegisterRouter.scala:87:24] assign _out_T_1881 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1883; // @[RegisterRouter.scala:87:24] assign _out_T_1883 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1885; // @[RegisterRouter.scala:87:24] assign _out_T_1885 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1887; // @[RegisterRouter.scala:87:24] assign _out_T_1887 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1889; // @[RegisterRouter.scala:87:24] assign _out_T_1889 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1891; // @[RegisterRouter.scala:87:24] assign _out_T_1891 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1893; // @[RegisterRouter.scala:87:24] assign _out_T_1893 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1895; // @[RegisterRouter.scala:87:24] assign _out_T_1895 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1897; // @[RegisterRouter.scala:87:24] assign _out_T_1897 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1899; // @[RegisterRouter.scala:87:24] assign _out_T_1899 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1901; // @[RegisterRouter.scala:87:24] assign _out_T_1901 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1903; // @[RegisterRouter.scala:87:24] assign _out_T_1903 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1905; // @[RegisterRouter.scala:87:24] assign _out_T_1905 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1907; // @[RegisterRouter.scala:87:24] assign _out_T_1907 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1909; // @[RegisterRouter.scala:87:24] assign _out_T_1909 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_2_138 = _out_T_1601; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_249 = _out_T_1603; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_234 = _out_T_1605; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_170 = _out_T_1607; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_115 = _out_T_1609; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_217 = _out_T_1611; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_247 = _out_T_1613; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_202 = _out_T_1615; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_142 = _out_T_1617; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_153 = _out_T_1619; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_174 = _out_T_1621; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_185 = _out_T_1623; // @[MuxLiteral.scala:49:48] wire _GEN_20 = out_findex_1 == 9'h100; // @[RegisterRouter.scala:87:24] wire _out_T_1624; // @[RegisterRouter.scala:87:24] assign _out_T_1624 = _GEN_20; // @[RegisterRouter.scala:87:24] wire _out_T_1640; // @[RegisterRouter.scala:87:24] assign _out_T_1640 = _GEN_20; // @[RegisterRouter.scala:87:24] wire _out_T_1666; // @[RegisterRouter.scala:87:24] assign _out_T_1666 = _GEN_20; // @[RegisterRouter.scala:87:24] wire _out_T_1678; // @[RegisterRouter.scala:87:24] assign _out_T_1678 = _GEN_20; // @[RegisterRouter.scala:87:24] wire _out_T_1716; // @[RegisterRouter.scala:87:24] assign _out_T_1716 = _GEN_20; // @[RegisterRouter.scala:87:24] wire _out_T_1724; // @[RegisterRouter.scala:87:24] assign _out_T_1724 = _GEN_20; // @[RegisterRouter.scala:87:24] wire _out_T_1742; // @[RegisterRouter.scala:87:24] assign _out_T_1742 = _GEN_20; // @[RegisterRouter.scala:87:24] wire _out_T_1756; // @[RegisterRouter.scala:87:24] assign _out_T_1756 = _GEN_20; // @[RegisterRouter.scala:87:24] wire _out_T_1822; // @[RegisterRouter.scala:87:24] assign _out_T_1822 = _GEN_20; // @[RegisterRouter.scala:87:24] wire _out_T_1846; // @[RegisterRouter.scala:87:24] assign _out_T_1846 = _GEN_20; // @[RegisterRouter.scala:87:24] wire _out_T_1876; // @[RegisterRouter.scala:87:24] assign _out_T_1876 = _GEN_20; // @[RegisterRouter.scala:87:24] wire _GEN_21 = out_bindex_1 == 9'h100; // @[RegisterRouter.scala:87:24] wire _out_T_1625; // @[RegisterRouter.scala:87:24] assign _out_T_1625 = _GEN_21; // @[RegisterRouter.scala:87:24] wire _out_T_1641; // @[RegisterRouter.scala:87:24] assign _out_T_1641 = _GEN_21; // @[RegisterRouter.scala:87:24] wire _out_T_1667; // @[RegisterRouter.scala:87:24] assign _out_T_1667 = _GEN_21; // @[RegisterRouter.scala:87:24] wire _out_T_1679; // @[RegisterRouter.scala:87:24] assign _out_T_1679 = _GEN_21; // @[RegisterRouter.scala:87:24] wire _out_T_1717; // @[RegisterRouter.scala:87:24] assign _out_T_1717 = _GEN_21; // @[RegisterRouter.scala:87:24] wire _out_T_1725; // @[RegisterRouter.scala:87:24] assign _out_T_1725 = _GEN_21; // @[RegisterRouter.scala:87:24] wire _out_T_1743; // @[RegisterRouter.scala:87:24] assign _out_T_1743 = _GEN_21; // @[RegisterRouter.scala:87:24] wire _out_T_1757; // @[RegisterRouter.scala:87:24] assign _out_T_1757 = _GEN_21; // @[RegisterRouter.scala:87:24] wire _out_T_1823; // @[RegisterRouter.scala:87:24] assign _out_T_1823 = _GEN_21; // @[RegisterRouter.scala:87:24] wire _out_T_1847; // @[RegisterRouter.scala:87:24] assign _out_T_1847 = _GEN_21; // @[RegisterRouter.scala:87:24] wire _out_T_1877; // @[RegisterRouter.scala:87:24] assign _out_T_1877 = _GEN_21; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_2_1 = _out_T_1625; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_184 = _out_T_1627; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_110 = _out_T_1629; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_196 = _out_T_1631; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_157 = _out_T_1633; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_189 = _out_T_1635; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_152 = _out_T_1637; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_228 = _out_T_1639; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_5 = _out_T_1641; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_216 = _out_T_1643; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_164 = _out_T_1645; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_179 = _out_T_1647; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_106 = _out_T_1649; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_238 = _out_T_1651; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_211 = _out_T_1653; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_253 = _out_T_1655; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_147 = _out_T_1657; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_221 = _out_T_1659; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_132 = _out_T_1661; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_133 = _out_T_1663; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_243 = _out_T_1665; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_9 = _out_T_1667; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_206 = _out_T_1669; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_233 = _out_T_1671; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_248 = _out_T_1673; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_201 = _out_T_1675; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_220 = _out_T_1677; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_4 = _out_T_1679; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_160 = _out_T_1681; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_192 = _out_T_1683; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_137 = _out_T_1685; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_165 = _out_T_1687; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_33 = _out_T_1689; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_229 = _out_T_1691; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_252 = _out_T_1693; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_197 = _out_T_1695; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_224 = _out_T_1697; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_156 = _out_T_1699; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_188 = _out_T_1701; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_169 = _out_T_1703; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_141 = _out_T_1705; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_225 = _out_T_1707; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_193 = _out_T_1709; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_212 = _out_T_1711; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_96 = _out_T_1713; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_109 = _out_T_1715; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_0 = _out_T_1717; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_173 = _out_T_1719; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_129 = _out_T_1721; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_134 = _out_T_1723; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_10 = _out_T_1725; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_205 = _out_T_1727; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_128 = _out_T_1729; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_237 = _out_T_1731; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_105 = _out_T_1733; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_244 = _out_T_1735; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_166 = _out_T_1737; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_32 = _out_T_1739; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_148 = _out_T_1741; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_8 = _out_T_1743; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_161 = _out_T_1745; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_180 = _out_T_1747; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_149 = _out_T_1749; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_176 = _out_T_1751; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_191 = _out_T_1753; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_204 = _out_T_1755; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_3 = _out_T_1757; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_144 = _out_T_1759; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_236 = _out_T_1761; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_181 = _out_T_1763; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_159 = _out_T_1765; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_187 = _out_T_1767; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_172 = _out_T_1769; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_113 = _out_T_1771; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_219 = _out_T_1773; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_230 = _out_T_1775; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_245 = _out_T_1777; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_208 = _out_T_1779; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_103 = _out_T_1781; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_140 = _out_T_1783; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_213 = _out_T_1785; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_155 = _out_T_1787; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_198 = _out_T_1789; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_108 = _out_T_1791; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_240 = _out_T_1793; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_251 = _out_T_1795; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_130 = _out_T_1797; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_223 = _out_T_1799; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_135 = _out_T_1801; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_226 = _out_T_1803; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_241 = _out_T_1805; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_167 = _out_T_1807; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_162 = _out_T_1809; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_255 = _out_T_1811; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_209 = _out_T_1813; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_112 = _out_T_1815; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_194 = _out_T_1817; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_145 = _out_T_1819; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_150 = _out_T_1821; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_7 = _out_T_1823; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_199 = _out_T_1825; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_177 = _out_T_1827; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_182 = _out_T_1829; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_154 = _out_T_1831; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_175 = _out_T_1833; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_143 = _out_T_1835; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_203 = _out_T_1837; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_218 = _out_T_1839; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_104 = _out_T_1841; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_250 = _out_T_1843; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_231 = _out_T_1845; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_2 = _out_T_1847; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_158 = _out_T_1849; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_186 = _out_T_1851; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_114 = _out_T_1853; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_171 = _out_T_1855; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_139 = _out_T_1857; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_207 = _out_T_1859; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_214 = _out_T_1861; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_235 = _out_T_1863; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_246 = _out_T_1865; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_151 = _out_T_1867; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_146 = _out_T_1869; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_190 = _out_T_1871; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_183 = _out_T_1873; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_168 = _out_T_1875; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_6 = _out_T_1877; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_210 = _out_T_1879; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_107 = _out_T_1881; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_136 = _out_T_1883; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_195 = _out_T_1885; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_239 = _out_T_1887; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_242 = _out_T_1889; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_131 = _out_T_1891; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_178 = _out_T_1893; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_163 = _out_T_1895; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_200 = _out_T_1897; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_111 = _out_T_1899; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_215 = _out_T_1901; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_222 = _out_T_1903; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_232 = _out_T_1905; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_254 = _out_T_1907; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_T_814; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_2_227 = _out_T_1909; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_T_1258; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1198; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_942; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_722; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1130; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1250; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1070; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_830; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_874; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_958; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1002; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_266; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_998; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_702; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1046; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_890; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1018; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_870; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1174; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_282; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1126; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_918; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_978; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_686; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1214; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1106; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1274; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_850; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1146; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_790; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_794; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1234; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_298; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1086; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1194; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1254; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1066; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1142; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_278; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_902; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1030; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_810; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_922; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_394; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1178; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1270; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1050; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1158; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_886; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1014; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_938; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_826; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1162; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1034; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1110; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_646; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_698; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_262; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_954; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_778; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_798; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_302; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1082; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_774; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1210; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_682; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1238; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_926; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_390; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_854; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_294; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_906; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_982; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_858; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_966; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1026; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1078; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_274; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_838; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1206; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_986; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_898; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1010; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_950; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_714; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1138; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1182; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1242; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1094; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_674; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_822; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1114; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_882; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1054; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_694; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1222; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1266; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_782; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1154; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_802; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1166; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1226; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_930; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_910; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1282; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1098; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_710; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1038; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_842; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_862; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_290; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1058; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_970; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_990; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_878; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_962; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_834; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1074; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1134; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_678; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1262; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1186; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_270; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_894; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1006; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_718; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_946; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_818; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1090; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1118; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1202; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1246; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_866; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_846; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1022; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_994; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_934; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_286; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1102; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_690; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_806; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1042; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1218; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1230; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_786; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_974; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_914; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1062; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_706; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1122; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1150; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1190; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1278; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1170; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_0; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_2; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_3; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_4; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_5; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_6; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_7; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_8; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_9; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_10; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_11; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_12; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_13; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_14; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_15; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_16; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_17; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_18; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_19; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_20; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_21; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_22; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_23; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_24; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_25; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_26; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_27; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_28; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_29; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_30; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_31; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_32; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_33; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_34; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_35; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_36; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_37; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_38; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_39; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_40; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_41; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_42; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_43; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_44; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_45; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_46; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_47; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_48; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_49; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_50; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_51; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_52; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_53; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_54; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_55; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_56; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_57; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_58; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_59; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_60; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_61; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_62; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_63; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_64; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_65; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_66; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_67; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_68; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_69; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_70; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_71; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_72; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_73; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_74; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_75; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_76; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_77; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_78; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_79; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_80; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_81; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_82; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_83; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_84; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_85; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_86; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_87; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_88; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_89; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_90; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_91; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_92; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_93; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_94; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_95; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_96; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_97; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_98; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_99; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_100; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_101; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_102; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_103; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_104; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_105; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_106; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_107; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_108; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_109; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_110; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_111; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_112; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_113; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_114; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_115; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_116; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_117; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_118; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_119; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_120; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_121; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_122; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_123; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_124; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_125; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_126; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_127; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_128; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_129; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_130; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_131; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_132; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_133; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_134; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_135; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_136; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_137; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_138; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_139; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_140; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_141; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_142; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_143; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_144; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_145; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_146; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_147; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_148; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_149; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_150; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_151; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_152; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_153; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_154; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_155; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_156; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_157; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_158; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_159; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_160; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_161; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_162; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_163; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_164; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_165; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_166; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_167; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_168; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_169; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_170; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_171; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_172; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_173; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_174; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_175; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_176; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_177; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_178; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_179; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_180; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_181; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_182; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_183; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_184; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_185; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_186; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_187; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_188; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_189; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_190; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_191; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_192; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_193; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_194; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_195; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_196; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_197; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_198; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_199; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_200; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_201; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_202; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_203; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_204; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_205; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_206; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_207; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_208; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_209; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_210; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_211; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_212; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_213; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_214; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_215; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_216; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_217; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_218; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_219; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_220; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_221; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_222; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_223; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_224; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_225; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_226; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_227; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_228; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_229; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_230; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_231; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_232; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_233; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_234; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_235; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_236; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_237; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_238; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_239; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_240; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_241; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_242; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_243; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_244; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_245; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_246; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_247; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_248; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_249; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_250; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_251; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_252; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_253; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_254; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_255; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_256; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_257; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_258; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_259; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_260; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_261; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_262; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_263; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_264; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_265; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_266; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_267; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_268; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_269; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_270; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_271; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_272; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_273; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_274; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_275; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_276; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_277; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_278; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_279; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_280; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_281; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_282; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_283; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_284; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_285; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_286; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_287; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_288; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_289; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_290; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_291; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_292; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_293; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_294; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_295; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_296; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_297; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_298; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_299; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_300; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_301; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_302; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_303; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_304; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_305; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_306; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_307; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_308; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_309; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_310; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_311; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_312; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_313; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_314; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_315; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_316; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_317; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_318; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_319; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_320; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_321; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_322; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_323; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_324; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_325; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_326; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_327; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_328; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_329; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_330; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_331; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_332; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_333; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_334; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_335; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_336; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_337; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_338; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_339; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_340; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_341; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_342; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_343; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_344; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_345; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_346; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_347; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_348; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_349; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_350; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_351; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_352; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_353; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_354; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_355; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_356; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_357; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_358; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_359; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_360; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_361; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_362; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_363; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_364; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_365; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_366; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_367; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_368; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_369; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_370; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_371; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_372; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_373; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_374; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_375; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_376; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_377; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_378; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_379; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_380; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_381; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_382; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_383; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_384; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_385; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_386; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_387; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_388; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_389; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_390; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_391; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_392; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_393; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_394; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_395; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_396; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_397; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_398; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_399; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_400; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_401; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_402; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_403; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_404; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_405; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_406; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_407; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_408; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_409; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_410; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_411; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_412; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_413; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_414; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_415; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_416; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_417; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_418; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_419; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_420; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_421; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_422; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_423; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_424; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_425; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_426; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_427; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_428; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_429; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_430; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_431; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_432; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_433; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_434; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_435; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_436; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_437; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_438; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_439; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_440; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_441; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_442; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_443; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_444; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_445; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_446; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_447; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_448; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_449; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_450; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_451; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_452; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_453; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_454; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_455; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_456; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_457; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_458; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_459; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_460; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_461; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_462; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_463; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_464; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_465; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_466; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_467; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_468; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_469; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_470; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_471; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_472; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_473; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_474; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_475; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_476; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_477; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_478; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_479; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_480; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_481; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_482; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_483; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_484; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_485; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_486; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_487; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_488; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_489; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_490; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_491; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_492; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_493; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_494; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_495; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_496; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_497; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_498; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_499; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_500; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_501; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_502; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_503; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_504; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_505; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_506; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_507; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_508; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_509; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_510; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_511; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_512; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_513; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_514; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_515; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_516; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_517; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_518; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_519; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_520; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_521; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_522; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_523; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_524; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_525; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_526; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_527; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_528; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_529; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_530; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_531; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_532; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_533; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_534; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_535; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_536; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_537; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_538; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_539; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_540; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_541; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_542; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_543; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_544; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_545; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_546; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_547; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_548; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_549; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_550; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_551; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_552; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_553; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_554; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_555; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_556; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_557; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_558; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_559; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_560; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_561; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_562; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_563; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_564; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_565; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_566; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_567; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_568; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_569; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_570; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_571; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_572; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_573; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_574; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_575; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_576; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_577; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_578; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_579; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_580; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_581; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_582; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_583; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_584; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_585; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_586; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_587; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_588; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_589; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_590; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_591; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_592; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_593; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_594; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_595; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_596; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_597; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_598; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_599; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_600; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_601; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_602; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_603; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_604; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_605; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_606; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_607; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_608; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_609; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_610; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_611; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_612; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_613; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_614; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_615; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_616; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_617; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_618; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_619; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_620; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_621; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_622; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_623; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_624; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_625; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_626; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_627; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_628; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_629; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_630; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_631; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_632; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_633; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_634; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_635; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_636; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_637; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_638; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_639; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_640; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_641; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_642; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_643; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_644; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_645; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_646; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_647; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_648; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_649; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_650; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_651; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_652; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_653; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_654; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_655; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_656; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_657; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_658; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_659; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_660; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_661; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_662; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_663; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_664; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_665; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_666; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_667; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_668; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_669; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_670; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_671; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_672; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_673; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_674; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_675; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_676; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_677; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_678; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_679; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_680; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_681; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_682; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_683; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_684; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_685; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_686; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_687; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_688; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_689; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_690; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_691; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_692; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_693; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_694; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_695; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_696; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_697; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_698; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_699; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_700; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_701; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_702; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_703; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_704; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_705; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_706; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_707; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_708; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_709; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_710; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_711; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_712; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_713; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_714; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_715; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_716; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_717; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_718; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_719; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_720; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_721; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_722; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_723; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_724; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_725; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_726; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_727; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_728; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_729; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_730; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_731; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_732; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_733; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_734; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_735; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_736; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_737; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_738; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_739; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_740; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_741; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_742; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_743; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_744; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_745; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_746; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_747; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_748; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_749; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_750; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_751; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_752; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_753; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_754; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_755; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_756; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_757; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_758; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_759; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_760; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_761; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_762; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_763; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_764; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_765; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_766; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_767; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_768; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_769; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_770; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_771; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_772; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_773; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_774; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_775; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_776; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_777; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_778; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_779; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_780; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_781; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_782; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_783; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_784; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_785; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_786; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_787; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_788; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_789; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_790; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_791; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_792; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_793; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_794; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_795; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_796; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_797; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_798; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_799; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_800; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_801; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_802; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_803; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_804; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_805; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_806; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_807; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_808; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_809; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_810; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_811; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_812; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_813; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_814; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_815; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_816; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_817; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_818; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_819; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_820; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_821; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_822; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_823; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_824; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_825; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_826; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_827; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_828; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_829; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_830; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_831; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_832; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_833; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_834; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_835; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_836; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_837; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_838; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_839; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_840; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_841; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_842; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_843; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_844; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_845; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_846; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_847; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_848; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_849; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_850; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_851; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_852; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_853; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_854; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_855; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_856; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_857; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_858; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_859; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_860; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_861; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_862; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_863; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_864; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_865; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_866; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_867; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_868; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_869; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_870; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_871; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_872; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_873; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_874; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_875; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_876; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_877; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_878; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_879; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_880; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_881; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_882; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_883; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_884; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_885; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_886; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_887; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_888; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_889; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_890; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_891; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_892; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_893; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_894; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_895; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_896; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_897; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_898; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_899; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_900; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_901; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_902; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_903; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_904; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_905; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_906; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_907; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_908; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_909; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_910; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_911; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_912; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_913; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_914; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_915; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_916; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_917; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_918; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_919; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_920; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_921; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_922; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_923; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_924; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_925; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_926; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_927; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_928; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_929; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_930; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_931; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_932; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_933; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_934; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_935; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_936; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_937; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_938; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_939; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_940; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_941; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_942; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_943; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_944; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_945; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_946; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_947; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_948; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_949; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_950; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_951; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_952; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_953; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_954; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_955; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_956; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_957; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_958; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_959; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_960; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_961; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_962; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_963; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_964; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_965; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_966; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_967; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_968; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_969; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_970; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_971; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_972; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_973; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_974; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_975; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_976; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_977; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_978; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_979; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_980; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_981; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_982; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_983; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_984; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_985; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_986; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_987; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_988; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_989; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_990; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_991; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_992; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_993; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_994; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_995; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_996; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_997; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_998; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_999; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1000; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1001; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1002; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1003; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1004; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1005; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1006; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1007; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1008; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1009; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1010; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1011; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1012; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1013; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1014; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1015; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1016; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1017; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1018; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1019; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1020; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1021; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1022; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1023; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1024; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1025; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1026; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1027; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1028; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1029; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1030; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1031; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1032; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1033; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1034; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1035; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1036; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1037; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1038; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1039; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1040; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1041; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1042; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1043; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1044; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1045; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1046; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1047; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1048; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1049; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1050; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1051; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1052; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1053; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1054; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1055; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1056; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1057; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1058; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1059; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1060; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1061; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1062; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1063; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1064; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1065; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1066; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1067; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1068; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1069; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1070; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1071; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1072; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1073; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1074; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1075; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1076; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1077; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1078; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1079; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1080; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1081; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1082; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1083; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1084; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1085; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1086; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1087; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1088; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1089; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1090; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1091; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1092; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1093; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1094; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1095; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1096; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1097; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1098; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1099; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1100; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1101; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1102; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1103; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1104; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1105; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1106; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1107; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1108; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1109; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1110; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1111; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1112; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1113; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1114; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1115; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1116; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1117; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1118; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1119; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1120; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1121; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1122; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1123; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1124; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1125; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1126; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1127; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1128; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1129; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1130; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1131; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1132; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1133; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1134; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1135; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1136; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1137; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1138; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1139; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1140; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1141; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1142; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1143; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1144; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1145; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1146; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1147; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1148; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1149; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1150; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1151; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1152; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1153; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1154; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1155; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1156; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1157; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1158; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1159; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1160; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1161; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1162; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1163; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1164; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1165; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1166; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1167; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1168; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1169; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1170; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1171; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1172; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1173; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1174; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1175; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1176; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1177; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1178; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1179; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1180; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1181; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1182; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1183; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1184; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1185; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1186; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1187; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1188; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1189; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1190; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1191; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1192; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1193; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1194; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1195; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1196; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1197; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1198; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1199; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1200; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1201; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1202; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1203; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1204; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1205; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1206; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1207; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1208; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1209; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1210; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_816; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1260; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1200; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_944; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_724; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1132; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1252; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1072; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_832; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_876; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_960; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1004; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_268; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1000; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_704; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1048; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_892; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1020; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_872; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1176; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_284; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1128; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_920; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_980; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_688; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1216; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1108; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1276; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_852; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1148; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_792; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_796; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1236; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_300; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1088; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1196; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1256; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1068; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1144; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_280; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_904; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1032; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_812; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_924; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_396; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1180; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1272; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1052; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1160; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_888; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1016; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_940; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_828; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1164; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1036; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1112; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_648; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_700; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_264; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_956; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_780; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_800; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_304; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1084; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_776; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1212; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_684; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1240; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_928; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_392; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_856; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_296; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_908; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_984; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_860; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_968; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1028; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1080; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_276; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_840; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1208; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_988; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_900; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1012; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_952; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_716; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1140; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1184; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1244; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1096; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_676; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_824; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1116; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_884; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1056; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_696; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1224; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1268; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_784; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1156; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_804; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1168; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1228; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_932; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_912; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1284; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1100; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_712; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1040; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_844; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_864; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_292; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1060; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_972; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_992; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_880; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_964; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_836; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1076; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1136; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_680; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1264; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1188; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_272; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_896; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1008; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_720; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_948; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_820; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1092; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1120; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1204; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1248; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_868; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_848; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1024; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_996; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_936; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_288; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1104; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_692; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_808; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1044; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1220; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1232; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_788; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_976; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_916; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1064; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_708; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1124; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1152; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1192; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1280; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1172; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_0; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_2; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_3; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_4; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_5; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_6; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_7; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_8; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_9; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_10; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_11; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_12; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_13; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_14; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_15; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_16; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_17; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_18; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_19; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_20; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_21; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_22; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_23; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_24; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_25; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_26; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_27; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_28; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_29; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_30; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_31; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_32; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_33; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_34; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_35; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_36; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_37; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_38; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_39; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_40; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_41; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_42; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_43; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_44; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_45; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_46; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_47; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_48; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_49; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_50; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_51; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_52; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_53; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_54; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_55; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_56; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_57; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_58; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_59; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_60; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_61; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_62; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_63; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_64; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_65; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_66; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_67; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_68; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_69; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_70; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_71; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_72; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_73; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_74; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_75; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_76; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_77; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_78; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_79; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_80; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_81; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_82; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_83; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_84; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_85; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_86; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_87; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_88; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_89; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_90; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_91; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_92; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_93; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_94; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_95; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_96; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_97; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_98; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_99; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_100; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_101; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_102; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_103; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_104; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_105; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_106; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_107; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_108; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_109; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_110; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_111; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_112; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_113; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_114; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_115; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_116; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_117; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_118; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_119; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_120; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_121; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_122; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_123; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_124; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_125; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_126; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_127; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_128; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_129; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_130; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_131; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_132; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_133; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_134; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_135; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_136; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_137; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_138; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_139; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_140; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_141; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_142; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_143; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_144; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_145; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_146; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_147; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_148; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_149; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_150; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_151; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_152; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_153; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_154; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_155; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_156; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_157; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_158; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_159; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_160; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_161; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_162; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_163; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_164; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_165; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_166; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_167; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_168; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_169; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_170; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_171; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_172; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_173; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_174; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_175; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_176; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_177; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_178; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_179; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_180; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_181; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_182; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_183; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_184; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_185; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_186; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_187; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_188; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_189; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_190; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_191; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_192; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_193; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_194; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_195; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_196; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_197; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_198; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_199; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_200; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_201; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_202; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_203; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_204; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_205; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_206; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_207; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_208; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_209; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_210; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_211; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_212; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_213; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_214; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_215; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_216; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_217; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_218; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_219; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_220; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_221; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_222; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_223; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_224; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_225; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_226; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_227; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_228; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_229; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_230; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_231; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_232; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_233; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_234; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_235; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_236; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_237; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_238; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_239; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_240; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_241; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_242; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_243; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_244; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_245; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_246; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_247; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_248; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_249; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_250; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_251; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_252; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_253; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_254; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_255; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_256; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_257; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_258; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_259; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_260; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_261; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_262; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_263; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_264; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_265; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_266; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_267; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_268; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_269; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_270; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_271; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_272; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_273; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_274; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_275; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_276; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_277; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_278; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_279; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_280; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_281; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_282; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_283; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_284; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_285; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_286; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_287; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_288; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_289; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_290; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_291; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_292; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_293; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_294; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_295; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_296; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_297; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_298; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_299; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_300; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_301; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_302; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_303; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_304; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_305; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_306; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_307; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_308; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_309; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_310; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_311; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_312; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_313; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_314; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_315; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_316; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_317; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_318; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_319; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_320; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_321; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_322; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_323; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_324; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_325; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_326; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_327; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_328; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_329; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_330; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_331; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_332; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_333; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_334; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_335; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_336; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_337; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_338; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_339; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_340; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_341; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_342; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_343; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_344; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_345; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_346; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_347; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_348; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_349; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_350; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_351; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_352; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_353; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_354; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_355; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_356; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_357; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_358; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_359; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_360; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_361; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_362; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_363; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_364; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_365; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_366; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_367; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_368; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_369; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_370; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_371; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_372; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_373; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_374; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_375; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_376; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_377; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_378; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_379; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_380; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_381; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_382; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_383; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_384; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_385; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_386; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_387; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_388; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_389; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_390; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_391; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_392; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_393; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_394; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_395; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_396; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_397; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_398; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_399; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_400; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_401; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_402; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_403; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_404; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_405; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_406; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_407; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_408; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_409; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_410; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_411; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_412; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_413; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_414; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_415; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_416; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_417; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_418; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_419; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_420; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_421; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_422; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_423; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_424; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_425; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_426; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_427; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_428; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_429; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_430; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_431; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_432; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_433; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_434; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_435; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_436; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_437; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_438; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_439; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_440; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_441; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_442; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_443; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_444; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_445; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_446; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_447; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_448; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_449; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_450; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_451; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_452; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_453; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_454; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_455; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_456; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_457; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_458; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_459; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_460; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_461; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_462; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_463; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_464; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_465; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_466; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_467; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_468; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_469; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_470; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_471; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_472; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_473; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_474; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_475; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_476; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_477; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_478; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_479; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_480; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_481; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_482; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_483; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_484; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_485; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_486; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_487; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_488; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_489; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_490; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_491; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_492; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_493; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_494; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_495; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_496; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_497; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_498; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_499; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_500; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_501; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_502; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_503; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_504; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_505; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_506; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_507; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_508; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_509; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_510; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_511; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_512; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_513; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_514; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_515; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_516; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_517; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_518; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_519; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_520; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_521; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_522; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_523; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_524; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_525; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_526; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_527; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_528; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_529; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_530; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_531; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_532; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_533; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_534; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_535; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_536; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_537; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_538; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_539; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_540; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_541; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_542; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_543; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_544; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_545; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_546; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_547; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_548; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_549; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_550; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_551; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_552; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_553; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_554; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_555; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_556; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_557; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_558; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_559; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_560; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_561; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_562; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_563; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_564; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_565; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_566; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_567; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_568; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_569; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_570; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_571; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_572; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_573; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_574; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_575; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_576; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_577; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_578; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_579; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_580; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_581; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_582; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_583; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_584; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_585; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_586; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_587; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_588; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_589; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_590; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_591; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_592; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_593; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_594; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_595; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_596; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_597; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_598; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_599; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_600; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_601; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_602; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_603; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_604; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_605; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_606; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_607; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_608; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_609; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_610; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_611; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_612; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_613; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_614; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_615; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_616; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_617; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_618; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_619; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_620; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_621; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_622; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_623; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_624; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_625; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_626; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_627; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_628; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_629; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_630; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_631; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_632; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_633; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_634; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_635; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_636; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_637; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_638; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_639; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_640; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_641; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_642; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_643; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_644; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_645; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_646; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_647; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_648; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_649; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_650; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_651; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_652; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_653; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_654; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_655; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_656; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_657; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_658; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_659; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_660; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_661; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_662; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_663; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_664; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_665; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_666; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_667; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_668; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_669; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_670; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_671; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_672; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_673; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_674; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_675; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_676; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_677; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_678; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_679; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_680; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_681; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_682; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_683; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_684; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_685; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_686; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_687; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_688; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_689; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_690; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_691; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_692; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_693; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_694; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_695; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_696; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_697; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_698; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_699; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_700; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_701; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_702; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_703; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_704; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_705; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_706; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_707; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_708; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_709; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_710; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_711; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_712; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_713; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_714; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_715; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_716; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_717; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_718; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_719; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_720; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_721; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_722; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_723; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_724; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_725; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_726; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_727; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_728; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_729; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_730; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_731; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_732; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_733; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_734; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_735; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_736; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_737; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_738; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_739; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_740; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_741; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_742; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_743; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_744; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_745; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_746; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_747; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_748; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_749; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_750; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_751; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_752; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_753; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_754; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_755; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_756; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_757; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_758; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_759; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_760; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_761; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_762; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_763; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_764; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_765; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_766; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_767; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_768; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_769; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_770; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_771; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_772; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_773; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_774; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_775; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_776; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_777; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_778; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_779; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_780; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_781; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_782; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_783; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_784; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_785; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_786; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_787; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_788; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_789; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_790; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_791; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_792; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_793; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_794; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_795; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_796; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_797; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_798; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_799; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_800; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_801; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_802; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_803; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_804; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_805; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_806; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_807; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_808; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_809; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_810; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_811; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_812; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_813; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_814; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_815; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_816; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_817; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_818; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_819; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_820; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_821; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_822; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_823; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_824; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_825; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_826; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_827; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_828; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_829; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_830; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_831; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_832; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_833; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_834; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_835; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_836; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_837; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_838; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_839; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_840; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_841; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_842; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_843; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_844; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_845; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_846; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_847; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_848; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_849; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_850; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_851; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_852; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_853; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_854; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_855; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_856; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_857; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_858; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_859; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_860; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_861; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_862; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_863; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_864; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_865; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_866; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_867; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_868; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_869; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_870; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_871; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_872; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_873; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_874; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_875; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_876; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_877; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_878; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_879; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_880; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_881; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_882; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_883; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_884; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_885; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_886; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_887; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_888; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_889; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_890; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_891; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_892; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_893; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_894; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_895; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_896; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_897; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_898; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_899; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_900; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_901; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_902; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_903; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_904; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_905; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_906; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_907; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_908; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_909; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_910; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_911; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_912; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_913; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_914; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_915; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_916; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_917; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_918; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_919; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_920; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_921; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_922; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_923; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_924; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_925; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_926; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_927; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_928; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_929; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_930; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_931; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_932; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_933; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_934; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_935; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_936; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_937; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_938; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_939; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_940; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_941; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_942; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_943; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_944; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_945; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_946; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_947; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_948; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_949; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_950; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_951; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_952; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_953; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_954; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_955; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_956; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_957; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_958; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_959; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_960; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_961; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_962; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_963; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_964; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_965; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_966; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_967; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_968; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_969; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_970; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_971; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_972; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_973; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_974; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_975; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_976; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_977; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_978; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_979; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_980; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_981; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_982; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_983; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_984; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_985; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_986; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_987; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_988; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_989; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_990; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_991; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_992; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_993; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_994; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_995; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_996; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_997; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_998; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_999; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1000; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1001; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1002; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1003; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1004; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1005; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1006; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1007; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1008; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1009; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1010; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1011; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1012; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1013; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1014; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1015; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1016; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1017; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1018; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1019; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1020; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1021; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1022; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1023; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1024; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1025; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1026; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1027; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1028; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1029; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1030; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1031; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1032; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1033; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1034; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1035; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1036; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1037; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1038; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1039; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1040; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1041; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1042; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1043; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1044; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1045; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1046; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1047; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1048; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1049; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1050; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1051; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1052; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1053; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1054; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1055; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1056; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1057; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1058; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1059; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1060; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1061; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1062; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1063; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1064; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1065; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1066; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1067; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1068; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1069; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1070; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1071; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1072; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1073; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1074; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1075; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1076; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1077; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1078; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1079; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1080; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1081; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1082; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1083; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1084; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1085; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1086; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1087; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1088; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1089; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1090; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1091; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1092; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1093; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1094; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1095; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1096; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1097; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1098; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1099; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1100; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1101; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1102; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1103; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1104; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1105; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1106; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1107; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1108; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1109; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1110; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1111; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1112; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1113; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1114; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1115; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1116; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1117; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1118; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1119; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1120; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1121; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1122; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1123; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1124; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1125; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1126; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1127; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1128; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1129; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1130; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1131; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1132; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1133; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1134; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1135; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1136; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1137; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1138; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1139; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1140; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1141; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1142; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1143; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1144; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1145; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1146; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1147; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1148; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1149; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1150; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1151; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1152; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1153; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1154; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1155; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1156; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1157; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1158; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1159; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1160; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1161; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1162; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1163; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1164; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1165; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1166; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1167; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1168; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1169; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1170; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1171; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1172; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1173; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1174; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1175; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1176; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1177; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1178; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1179; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1180; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1181; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1182; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1183; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1184; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1185; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1186; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1187; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1188; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1189; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1190; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1191; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1192; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1193; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1194; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1195; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1196; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1197; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1198; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1199; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1200; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1201; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1202; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1203; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1204; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1205; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1206; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1207; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1208; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1209; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1210; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_814; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1258; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1198; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_942; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_722; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1130; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1250; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1070; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_830; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_874; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_958; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1002; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_266; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_998; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_702; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1046; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_890; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1018; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_870; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1174; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_282; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1126; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_918; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_978; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_686; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1214; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1106; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1274; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_850; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1146; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_790; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_794; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1234; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_298; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1086; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1194; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1254; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1066; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1142; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_278; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_902; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1030; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_810; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_922; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_394; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1178; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1270; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1050; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1158; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_886; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1014; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_938; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_826; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1162; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1034; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1110; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_646; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_698; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_262; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_954; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_778; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_798; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_302; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1082; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_774; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1210; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_682; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1238; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_926; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_390; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_854; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_294; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_906; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_982; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_858; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_966; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1026; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1078; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_274; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_838; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1206; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_986; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_898; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1010; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_950; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_714; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1138; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1182; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1242; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1094; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_674; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_822; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1114; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_882; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1054; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_694; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1222; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1266; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_782; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1154; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_802; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1166; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1226; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_930; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_910; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1282; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1098; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_710; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1038; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_842; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_862; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_290; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1058; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_970; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_990; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_878; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_962; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_834; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1074; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1134; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_678; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1262; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1186; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_270; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_894; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1006; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_718; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_946; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_818; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1090; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1118; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1202; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1246; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_866; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_846; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1022; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_994; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_934; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_286; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1102; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_690; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_806; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1042; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1218; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1230; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_786; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_974; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_914; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1062; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_706; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1122; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1150; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1190; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1278; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1170; // @[RegisterRouter.scala:87:24] wire out_roready_1_0; // @[RegisterRouter.scala:87:24] wire out_roready_1_1; // @[RegisterRouter.scala:87:24] wire out_roready_1_2; // @[RegisterRouter.scala:87:24] wire out_roready_1_3; // @[RegisterRouter.scala:87:24] wire out_roready_1_4; // @[RegisterRouter.scala:87:24] wire out_roready_1_5; // @[RegisterRouter.scala:87:24] wire out_roready_1_6; // @[RegisterRouter.scala:87:24] wire out_roready_1_7; // @[RegisterRouter.scala:87:24] wire out_roready_1_8; // @[RegisterRouter.scala:87:24] wire out_roready_1_9; // @[RegisterRouter.scala:87:24] wire out_roready_1_10; // @[RegisterRouter.scala:87:24] wire out_roready_1_11; // @[RegisterRouter.scala:87:24] wire out_roready_1_12; // @[RegisterRouter.scala:87:24] wire out_roready_1_13; // @[RegisterRouter.scala:87:24] wire out_roready_1_14; // @[RegisterRouter.scala:87:24] wire out_roready_1_15; // @[RegisterRouter.scala:87:24] wire out_roready_1_16; // @[RegisterRouter.scala:87:24] wire out_roready_1_17; // @[RegisterRouter.scala:87:24] wire out_roready_1_18; // @[RegisterRouter.scala:87:24] wire out_roready_1_19; // @[RegisterRouter.scala:87:24] wire out_roready_1_20; // @[RegisterRouter.scala:87:24] wire out_roready_1_21; // @[RegisterRouter.scala:87:24] wire out_roready_1_22; // @[RegisterRouter.scala:87:24] wire out_roready_1_23; // @[RegisterRouter.scala:87:24] wire out_roready_1_24; // @[RegisterRouter.scala:87:24] wire out_roready_1_25; // @[RegisterRouter.scala:87:24] wire out_roready_1_26; // @[RegisterRouter.scala:87:24] wire out_roready_1_27; // @[RegisterRouter.scala:87:24] wire out_roready_1_28; // @[RegisterRouter.scala:87:24] wire out_roready_1_29; // @[RegisterRouter.scala:87:24] wire out_roready_1_30; // @[RegisterRouter.scala:87:24] wire out_roready_1_31; // @[RegisterRouter.scala:87:24] wire out_roready_1_32; // @[RegisterRouter.scala:87:24] wire out_roready_1_33; // @[RegisterRouter.scala:87:24] wire out_roready_1_34; // @[RegisterRouter.scala:87:24] wire out_roready_1_35; // @[RegisterRouter.scala:87:24] wire out_roready_1_36; // @[RegisterRouter.scala:87:24] wire out_roready_1_37; // @[RegisterRouter.scala:87:24] wire out_roready_1_38; // @[RegisterRouter.scala:87:24] wire out_roready_1_39; // @[RegisterRouter.scala:87:24] wire out_roready_1_40; // @[RegisterRouter.scala:87:24] wire out_roready_1_41; // @[RegisterRouter.scala:87:24] wire out_roready_1_42; // @[RegisterRouter.scala:87:24] wire out_roready_1_43; // @[RegisterRouter.scala:87:24] wire out_roready_1_44; // @[RegisterRouter.scala:87:24] wire out_roready_1_45; // @[RegisterRouter.scala:87:24] wire out_roready_1_46; // @[RegisterRouter.scala:87:24] wire out_roready_1_47; // @[RegisterRouter.scala:87:24] wire out_roready_1_48; // @[RegisterRouter.scala:87:24] wire out_roready_1_49; // @[RegisterRouter.scala:87:24] wire out_roready_1_50; // @[RegisterRouter.scala:87:24] wire out_roready_1_51; // @[RegisterRouter.scala:87:24] wire out_roready_1_52; // @[RegisterRouter.scala:87:24] wire out_roready_1_53; // @[RegisterRouter.scala:87:24] wire out_roready_1_54; // @[RegisterRouter.scala:87:24] wire out_roready_1_55; // @[RegisterRouter.scala:87:24] wire out_roready_1_56; // @[RegisterRouter.scala:87:24] wire out_roready_1_57; // @[RegisterRouter.scala:87:24] wire out_roready_1_58; // @[RegisterRouter.scala:87:24] wire out_roready_1_59; // @[RegisterRouter.scala:87:24] wire out_roready_1_60; // @[RegisterRouter.scala:87:24] wire out_roready_1_61; // @[RegisterRouter.scala:87:24] wire out_roready_1_62; // @[RegisterRouter.scala:87:24] wire out_roready_1_63; // @[RegisterRouter.scala:87:24] wire out_roready_1_64; // @[RegisterRouter.scala:87:24] wire out_roready_1_65; // @[RegisterRouter.scala:87:24] wire out_roready_1_66; // @[RegisterRouter.scala:87:24] wire out_roready_1_67; // @[RegisterRouter.scala:87:24] wire out_roready_1_68; // @[RegisterRouter.scala:87:24] wire out_roready_1_69; // @[RegisterRouter.scala:87:24] wire out_roready_1_70; // @[RegisterRouter.scala:87:24] wire out_roready_1_71; // @[RegisterRouter.scala:87:24] wire out_roready_1_72; // @[RegisterRouter.scala:87:24] wire out_roready_1_73; // @[RegisterRouter.scala:87:24] wire out_roready_1_74; // @[RegisterRouter.scala:87:24] wire out_roready_1_75; // @[RegisterRouter.scala:87:24] wire out_roready_1_76; // @[RegisterRouter.scala:87:24] wire out_roready_1_77; // @[RegisterRouter.scala:87:24] wire out_roready_1_78; // @[RegisterRouter.scala:87:24] wire out_roready_1_79; // @[RegisterRouter.scala:87:24] wire out_roready_1_80; // @[RegisterRouter.scala:87:24] wire out_roready_1_81; // @[RegisterRouter.scala:87:24] wire out_roready_1_82; // @[RegisterRouter.scala:87:24] wire out_roready_1_83; // @[RegisterRouter.scala:87:24] wire out_roready_1_84; // @[RegisterRouter.scala:87:24] wire out_roready_1_85; // @[RegisterRouter.scala:87:24] wire out_roready_1_86; // @[RegisterRouter.scala:87:24] wire out_roready_1_87; // @[RegisterRouter.scala:87:24] wire out_roready_1_88; // @[RegisterRouter.scala:87:24] wire out_roready_1_89; // @[RegisterRouter.scala:87:24] wire out_roready_1_90; // @[RegisterRouter.scala:87:24] wire out_roready_1_91; // @[RegisterRouter.scala:87:24] wire out_roready_1_92; // @[RegisterRouter.scala:87:24] wire out_roready_1_93; // @[RegisterRouter.scala:87:24] wire out_roready_1_94; // @[RegisterRouter.scala:87:24] wire out_roready_1_95; // @[RegisterRouter.scala:87:24] wire out_roready_1_96; // @[RegisterRouter.scala:87:24] wire out_roready_1_97; // @[RegisterRouter.scala:87:24] wire out_roready_1_98; // @[RegisterRouter.scala:87:24] wire out_roready_1_99; // @[RegisterRouter.scala:87:24] wire out_roready_1_100; // @[RegisterRouter.scala:87:24] wire out_roready_1_101; // @[RegisterRouter.scala:87:24] wire out_roready_1_102; // @[RegisterRouter.scala:87:24] wire out_roready_1_103; // @[RegisterRouter.scala:87:24] wire out_roready_1_104; // @[RegisterRouter.scala:87:24] wire out_roready_1_105; // @[RegisterRouter.scala:87:24] wire out_roready_1_106; // @[RegisterRouter.scala:87:24] wire out_roready_1_107; // @[RegisterRouter.scala:87:24] wire out_roready_1_108; // @[RegisterRouter.scala:87:24] wire out_roready_1_109; // @[RegisterRouter.scala:87:24] wire out_roready_1_110; // @[RegisterRouter.scala:87:24] wire out_roready_1_111; // @[RegisterRouter.scala:87:24] wire out_roready_1_112; // @[RegisterRouter.scala:87:24] wire out_roready_1_113; // @[RegisterRouter.scala:87:24] wire out_roready_1_114; // @[RegisterRouter.scala:87:24] wire out_roready_1_115; // @[RegisterRouter.scala:87:24] wire out_roready_1_116; // @[RegisterRouter.scala:87:24] wire out_roready_1_117; // @[RegisterRouter.scala:87:24] wire out_roready_1_118; // @[RegisterRouter.scala:87:24] wire out_roready_1_119; // @[RegisterRouter.scala:87:24] wire out_roready_1_120; // @[RegisterRouter.scala:87:24] wire out_roready_1_121; // @[RegisterRouter.scala:87:24] wire out_roready_1_122; // @[RegisterRouter.scala:87:24] wire out_roready_1_123; // @[RegisterRouter.scala:87:24] wire out_roready_1_124; // @[RegisterRouter.scala:87:24] wire out_roready_1_125; // @[RegisterRouter.scala:87:24] wire out_roready_1_126; // @[RegisterRouter.scala:87:24] wire out_roready_1_127; // @[RegisterRouter.scala:87:24] wire out_roready_1_128; // @[RegisterRouter.scala:87:24] wire out_roready_1_129; // @[RegisterRouter.scala:87:24] wire out_roready_1_130; // @[RegisterRouter.scala:87:24] wire out_roready_1_131; // @[RegisterRouter.scala:87:24] wire out_roready_1_132; // @[RegisterRouter.scala:87:24] wire out_roready_1_133; // @[RegisterRouter.scala:87:24] wire out_roready_1_134; // @[RegisterRouter.scala:87:24] wire out_roready_1_135; // @[RegisterRouter.scala:87:24] wire out_roready_1_136; // @[RegisterRouter.scala:87:24] wire out_roready_1_137; // @[RegisterRouter.scala:87:24] wire out_roready_1_138; // @[RegisterRouter.scala:87:24] wire out_roready_1_139; // @[RegisterRouter.scala:87:24] wire out_roready_1_140; // @[RegisterRouter.scala:87:24] wire out_roready_1_141; // @[RegisterRouter.scala:87:24] wire out_roready_1_142; // @[RegisterRouter.scala:87:24] wire out_roready_1_143; // @[RegisterRouter.scala:87:24] wire out_roready_1_144; // @[RegisterRouter.scala:87:24] wire out_roready_1_145; // @[RegisterRouter.scala:87:24] wire out_roready_1_146; // @[RegisterRouter.scala:87:24] wire out_roready_1_147; // @[RegisterRouter.scala:87:24] wire out_roready_1_148; // @[RegisterRouter.scala:87:24] wire out_roready_1_149; // @[RegisterRouter.scala:87:24] wire out_roready_1_150; // @[RegisterRouter.scala:87:24] wire out_roready_1_151; // @[RegisterRouter.scala:87:24] wire out_roready_1_152; // @[RegisterRouter.scala:87:24] wire out_roready_1_153; // @[RegisterRouter.scala:87:24] wire out_roready_1_154; // @[RegisterRouter.scala:87:24] wire out_roready_1_155; // @[RegisterRouter.scala:87:24] wire out_roready_1_156; // @[RegisterRouter.scala:87:24] wire out_roready_1_157; // @[RegisterRouter.scala:87:24] wire out_roready_1_158; // @[RegisterRouter.scala:87:24] wire out_roready_1_159; // @[RegisterRouter.scala:87:24] wire out_roready_1_160; // @[RegisterRouter.scala:87:24] wire out_roready_1_161; // @[RegisterRouter.scala:87:24] wire out_roready_1_162; // @[RegisterRouter.scala:87:24] wire out_roready_1_163; // @[RegisterRouter.scala:87:24] wire out_roready_1_164; // @[RegisterRouter.scala:87:24] wire out_roready_1_165; // @[RegisterRouter.scala:87:24] wire out_roready_1_166; // @[RegisterRouter.scala:87:24] wire out_roready_1_167; // @[RegisterRouter.scala:87:24] wire out_roready_1_168; // @[RegisterRouter.scala:87:24] wire out_roready_1_169; // @[RegisterRouter.scala:87:24] wire out_roready_1_170; // @[RegisterRouter.scala:87:24] wire out_roready_1_171; // @[RegisterRouter.scala:87:24] wire out_roready_1_172; // @[RegisterRouter.scala:87:24] wire out_roready_1_173; // @[RegisterRouter.scala:87:24] wire out_roready_1_174; // @[RegisterRouter.scala:87:24] wire out_roready_1_175; // @[RegisterRouter.scala:87:24] wire out_roready_1_176; // @[RegisterRouter.scala:87:24] wire out_roready_1_177; // @[RegisterRouter.scala:87:24] wire out_roready_1_178; // @[RegisterRouter.scala:87:24] wire out_roready_1_179; // @[RegisterRouter.scala:87:24] wire out_roready_1_180; // @[RegisterRouter.scala:87:24] wire out_roready_1_181; // @[RegisterRouter.scala:87:24] wire out_roready_1_182; // @[RegisterRouter.scala:87:24] wire out_roready_1_183; // @[RegisterRouter.scala:87:24] wire out_roready_1_184; // @[RegisterRouter.scala:87:24] wire out_roready_1_185; // @[RegisterRouter.scala:87:24] wire out_roready_1_186; // @[RegisterRouter.scala:87:24] wire out_roready_1_187; // @[RegisterRouter.scala:87:24] wire out_roready_1_188; // @[RegisterRouter.scala:87:24] wire out_roready_1_189; // @[RegisterRouter.scala:87:24] wire out_roready_1_190; // @[RegisterRouter.scala:87:24] wire out_roready_1_191; // @[RegisterRouter.scala:87:24] wire out_roready_1_192; // @[RegisterRouter.scala:87:24] wire out_roready_1_193; // @[RegisterRouter.scala:87:24] wire out_roready_1_194; // @[RegisterRouter.scala:87:24] wire out_roready_1_195; // @[RegisterRouter.scala:87:24] wire out_roready_1_196; // @[RegisterRouter.scala:87:24] wire out_roready_1_197; // @[RegisterRouter.scala:87:24] wire out_roready_1_198; // @[RegisterRouter.scala:87:24] wire out_roready_1_199; // @[RegisterRouter.scala:87:24] wire out_roready_1_200; // @[RegisterRouter.scala:87:24] wire out_roready_1_201; // @[RegisterRouter.scala:87:24] wire out_roready_1_202; // @[RegisterRouter.scala:87:24] wire out_roready_1_203; // @[RegisterRouter.scala:87:24] wire out_roready_1_204; // @[RegisterRouter.scala:87:24] wire out_roready_1_205; // @[RegisterRouter.scala:87:24] wire out_roready_1_206; // @[RegisterRouter.scala:87:24] wire out_roready_1_207; // @[RegisterRouter.scala:87:24] wire out_roready_1_208; // @[RegisterRouter.scala:87:24] wire out_roready_1_209; // @[RegisterRouter.scala:87:24] wire out_roready_1_210; // @[RegisterRouter.scala:87:24] wire out_roready_1_211; // @[RegisterRouter.scala:87:24] wire out_roready_1_212; // @[RegisterRouter.scala:87:24] wire out_roready_1_213; // @[RegisterRouter.scala:87:24] wire out_roready_1_214; // @[RegisterRouter.scala:87:24] wire out_roready_1_215; // @[RegisterRouter.scala:87:24] wire out_roready_1_216; // @[RegisterRouter.scala:87:24] wire out_roready_1_217; // @[RegisterRouter.scala:87:24] wire out_roready_1_218; // @[RegisterRouter.scala:87:24] wire out_roready_1_219; // @[RegisterRouter.scala:87:24] wire out_roready_1_220; // @[RegisterRouter.scala:87:24] wire out_roready_1_221; // @[RegisterRouter.scala:87:24] wire out_roready_1_222; // @[RegisterRouter.scala:87:24] wire out_roready_1_223; // @[RegisterRouter.scala:87:24] wire out_roready_1_224; // @[RegisterRouter.scala:87:24] wire out_roready_1_225; // @[RegisterRouter.scala:87:24] wire out_roready_1_226; // @[RegisterRouter.scala:87:24] wire out_roready_1_227; // @[RegisterRouter.scala:87:24] wire out_roready_1_228; // @[RegisterRouter.scala:87:24] wire out_roready_1_229; // @[RegisterRouter.scala:87:24] wire out_roready_1_230; // @[RegisterRouter.scala:87:24] wire out_roready_1_231; // @[RegisterRouter.scala:87:24] wire out_roready_1_232; // @[RegisterRouter.scala:87:24] wire out_roready_1_233; // @[RegisterRouter.scala:87:24] wire out_roready_1_234; // @[RegisterRouter.scala:87:24] wire out_roready_1_235; // @[RegisterRouter.scala:87:24] wire out_roready_1_236; // @[RegisterRouter.scala:87:24] wire out_roready_1_237; // @[RegisterRouter.scala:87:24] wire out_roready_1_238; // @[RegisterRouter.scala:87:24] wire out_roready_1_239; // @[RegisterRouter.scala:87:24] wire out_roready_1_240; // @[RegisterRouter.scala:87:24] wire out_roready_1_241; // @[RegisterRouter.scala:87:24] wire out_roready_1_242; // @[RegisterRouter.scala:87:24] wire out_roready_1_243; // @[RegisterRouter.scala:87:24] wire out_roready_1_244; // @[RegisterRouter.scala:87:24] wire out_roready_1_245; // @[RegisterRouter.scala:87:24] wire out_roready_1_246; // @[RegisterRouter.scala:87:24] wire out_roready_1_247; // @[RegisterRouter.scala:87:24] wire out_roready_1_248; // @[RegisterRouter.scala:87:24] wire out_roready_1_249; // @[RegisterRouter.scala:87:24] wire out_roready_1_250; // @[RegisterRouter.scala:87:24] wire out_roready_1_251; // @[RegisterRouter.scala:87:24] wire out_roready_1_252; // @[RegisterRouter.scala:87:24] wire out_roready_1_253; // @[RegisterRouter.scala:87:24] wire out_roready_1_254; // @[RegisterRouter.scala:87:24] wire out_roready_1_255; // @[RegisterRouter.scala:87:24] wire out_roready_1_256; // @[RegisterRouter.scala:87:24] wire out_roready_1_257; // @[RegisterRouter.scala:87:24] wire out_roready_1_258; // @[RegisterRouter.scala:87:24] wire out_roready_1_259; // @[RegisterRouter.scala:87:24] wire out_roready_1_260; // @[RegisterRouter.scala:87:24] wire out_roready_1_261; // @[RegisterRouter.scala:87:24] wire out_roready_1_262; // @[RegisterRouter.scala:87:24] wire out_roready_1_263; // @[RegisterRouter.scala:87:24] wire out_roready_1_264; // @[RegisterRouter.scala:87:24] wire out_roready_1_265; // @[RegisterRouter.scala:87:24] wire out_roready_1_266; // @[RegisterRouter.scala:87:24] wire out_roready_1_267; // @[RegisterRouter.scala:87:24] wire out_roready_1_268; // @[RegisterRouter.scala:87:24] wire out_roready_1_269; // @[RegisterRouter.scala:87:24] wire out_roready_1_270; // @[RegisterRouter.scala:87:24] wire out_roready_1_271; // @[RegisterRouter.scala:87:24] wire out_roready_1_272; // @[RegisterRouter.scala:87:24] wire out_roready_1_273; // @[RegisterRouter.scala:87:24] wire out_roready_1_274; // @[RegisterRouter.scala:87:24] wire out_roready_1_275; // @[RegisterRouter.scala:87:24] wire out_roready_1_276; // @[RegisterRouter.scala:87:24] wire out_roready_1_277; // @[RegisterRouter.scala:87:24] wire out_roready_1_278; // @[RegisterRouter.scala:87:24] wire out_roready_1_279; // @[RegisterRouter.scala:87:24] wire out_roready_1_280; // @[RegisterRouter.scala:87:24] wire out_roready_1_281; // @[RegisterRouter.scala:87:24] wire out_roready_1_282; // @[RegisterRouter.scala:87:24] wire out_roready_1_283; // @[RegisterRouter.scala:87:24] wire out_roready_1_284; // @[RegisterRouter.scala:87:24] wire out_roready_1_285; // @[RegisterRouter.scala:87:24] wire out_roready_1_286; // @[RegisterRouter.scala:87:24] wire out_roready_1_287; // @[RegisterRouter.scala:87:24] wire out_roready_1_288; // @[RegisterRouter.scala:87:24] wire out_roready_1_289; // @[RegisterRouter.scala:87:24] wire out_roready_1_290; // @[RegisterRouter.scala:87:24] wire out_roready_1_291; // @[RegisterRouter.scala:87:24] wire out_roready_1_292; // @[RegisterRouter.scala:87:24] wire out_roready_1_293; // @[RegisterRouter.scala:87:24] wire out_roready_1_294; // @[RegisterRouter.scala:87:24] wire out_roready_1_295; // @[RegisterRouter.scala:87:24] wire out_roready_1_296; // @[RegisterRouter.scala:87:24] wire out_roready_1_297; // @[RegisterRouter.scala:87:24] wire out_roready_1_298; // @[RegisterRouter.scala:87:24] wire out_roready_1_299; // @[RegisterRouter.scala:87:24] wire out_roready_1_300; // @[RegisterRouter.scala:87:24] wire out_roready_1_301; // @[RegisterRouter.scala:87:24] wire out_roready_1_302; // @[RegisterRouter.scala:87:24] wire out_roready_1_303; // @[RegisterRouter.scala:87:24] wire out_roready_1_304; // @[RegisterRouter.scala:87:24] wire out_roready_1_305; // @[RegisterRouter.scala:87:24] wire out_roready_1_306; // @[RegisterRouter.scala:87:24] wire out_roready_1_307; // @[RegisterRouter.scala:87:24] wire out_roready_1_308; // @[RegisterRouter.scala:87:24] wire out_roready_1_309; // @[RegisterRouter.scala:87:24] wire out_roready_1_310; // @[RegisterRouter.scala:87:24] wire out_roready_1_311; // @[RegisterRouter.scala:87:24] wire out_roready_1_312; // @[RegisterRouter.scala:87:24] wire out_roready_1_313; // @[RegisterRouter.scala:87:24] wire out_roready_1_314; // @[RegisterRouter.scala:87:24] wire out_roready_1_315; // @[RegisterRouter.scala:87:24] wire out_roready_1_316; // @[RegisterRouter.scala:87:24] wire out_roready_1_317; // @[RegisterRouter.scala:87:24] wire out_roready_1_318; // @[RegisterRouter.scala:87:24] wire out_roready_1_319; // @[RegisterRouter.scala:87:24] wire out_roready_1_320; // @[RegisterRouter.scala:87:24] wire out_roready_1_321; // @[RegisterRouter.scala:87:24] wire out_roready_1_322; // @[RegisterRouter.scala:87:24] wire out_roready_1_323; // @[RegisterRouter.scala:87:24] wire out_roready_1_324; // @[RegisterRouter.scala:87:24] wire out_roready_1_325; // @[RegisterRouter.scala:87:24] wire out_roready_1_326; // @[RegisterRouter.scala:87:24] wire out_roready_1_327; // @[RegisterRouter.scala:87:24] wire out_roready_1_328; // @[RegisterRouter.scala:87:24] wire out_roready_1_329; // @[RegisterRouter.scala:87:24] wire out_roready_1_330; // @[RegisterRouter.scala:87:24] wire out_roready_1_331; // @[RegisterRouter.scala:87:24] wire out_roready_1_332; // @[RegisterRouter.scala:87:24] wire out_roready_1_333; // @[RegisterRouter.scala:87:24] wire out_roready_1_334; // @[RegisterRouter.scala:87:24] wire out_roready_1_335; // @[RegisterRouter.scala:87:24] wire out_roready_1_336; // @[RegisterRouter.scala:87:24] wire out_roready_1_337; // @[RegisterRouter.scala:87:24] wire out_roready_1_338; // @[RegisterRouter.scala:87:24] wire out_roready_1_339; // @[RegisterRouter.scala:87:24] wire out_roready_1_340; // @[RegisterRouter.scala:87:24] wire out_roready_1_341; // @[RegisterRouter.scala:87:24] wire out_roready_1_342; // @[RegisterRouter.scala:87:24] wire out_roready_1_343; // @[RegisterRouter.scala:87:24] wire out_roready_1_344; // @[RegisterRouter.scala:87:24] wire out_roready_1_345; // @[RegisterRouter.scala:87:24] wire out_roready_1_346; // @[RegisterRouter.scala:87:24] wire out_roready_1_347; // @[RegisterRouter.scala:87:24] wire out_roready_1_348; // @[RegisterRouter.scala:87:24] wire out_roready_1_349; // @[RegisterRouter.scala:87:24] wire out_roready_1_350; // @[RegisterRouter.scala:87:24] wire out_roready_1_351; // @[RegisterRouter.scala:87:24] wire out_roready_1_352; // @[RegisterRouter.scala:87:24] wire out_roready_1_353; // @[RegisterRouter.scala:87:24] wire out_roready_1_354; // @[RegisterRouter.scala:87:24] wire out_roready_1_355; // @[RegisterRouter.scala:87:24] wire out_roready_1_356; // @[RegisterRouter.scala:87:24] wire out_roready_1_357; // @[RegisterRouter.scala:87:24] wire out_roready_1_358; // @[RegisterRouter.scala:87:24] wire out_roready_1_359; // @[RegisterRouter.scala:87:24] wire out_roready_1_360; // @[RegisterRouter.scala:87:24] wire out_roready_1_361; // @[RegisterRouter.scala:87:24] wire out_roready_1_362; // @[RegisterRouter.scala:87:24] wire out_roready_1_363; // @[RegisterRouter.scala:87:24] wire out_roready_1_364; // @[RegisterRouter.scala:87:24] wire out_roready_1_365; // @[RegisterRouter.scala:87:24] wire out_roready_1_366; // @[RegisterRouter.scala:87:24] wire out_roready_1_367; // @[RegisterRouter.scala:87:24] wire out_roready_1_368; // @[RegisterRouter.scala:87:24] wire out_roready_1_369; // @[RegisterRouter.scala:87:24] wire out_roready_1_370; // @[RegisterRouter.scala:87:24] wire out_roready_1_371; // @[RegisterRouter.scala:87:24] wire out_roready_1_372; // @[RegisterRouter.scala:87:24] wire out_roready_1_373; // @[RegisterRouter.scala:87:24] wire out_roready_1_374; // @[RegisterRouter.scala:87:24] wire out_roready_1_375; // @[RegisterRouter.scala:87:24] wire out_roready_1_376; // @[RegisterRouter.scala:87:24] wire out_roready_1_377; // @[RegisterRouter.scala:87:24] wire out_roready_1_378; // @[RegisterRouter.scala:87:24] wire out_roready_1_379; // @[RegisterRouter.scala:87:24] wire out_roready_1_380; // @[RegisterRouter.scala:87:24] wire out_roready_1_381; // @[RegisterRouter.scala:87:24] wire out_roready_1_382; // @[RegisterRouter.scala:87:24] wire out_roready_1_383; // @[RegisterRouter.scala:87:24] wire out_roready_1_384; // @[RegisterRouter.scala:87:24] wire out_roready_1_385; // @[RegisterRouter.scala:87:24] wire out_roready_1_386; // @[RegisterRouter.scala:87:24] wire out_roready_1_387; // @[RegisterRouter.scala:87:24] wire out_roready_1_388; // @[RegisterRouter.scala:87:24] wire out_roready_1_389; // @[RegisterRouter.scala:87:24] wire out_roready_1_390; // @[RegisterRouter.scala:87:24] wire out_roready_1_391; // @[RegisterRouter.scala:87:24] wire out_roready_1_392; // @[RegisterRouter.scala:87:24] wire out_roready_1_393; // @[RegisterRouter.scala:87:24] wire out_roready_1_394; // @[RegisterRouter.scala:87:24] wire out_roready_1_395; // @[RegisterRouter.scala:87:24] wire out_roready_1_396; // @[RegisterRouter.scala:87:24] wire out_roready_1_397; // @[RegisterRouter.scala:87:24] wire out_roready_1_398; // @[RegisterRouter.scala:87:24] wire out_roready_1_399; // @[RegisterRouter.scala:87:24] wire out_roready_1_400; // @[RegisterRouter.scala:87:24] wire out_roready_1_401; // @[RegisterRouter.scala:87:24] wire out_roready_1_402; // @[RegisterRouter.scala:87:24] wire out_roready_1_403; // @[RegisterRouter.scala:87:24] wire out_roready_1_404; // @[RegisterRouter.scala:87:24] wire out_roready_1_405; // @[RegisterRouter.scala:87:24] wire out_roready_1_406; // @[RegisterRouter.scala:87:24] wire out_roready_1_407; // @[RegisterRouter.scala:87:24] wire out_roready_1_408; // @[RegisterRouter.scala:87:24] wire out_roready_1_409; // @[RegisterRouter.scala:87:24] wire out_roready_1_410; // @[RegisterRouter.scala:87:24] wire out_roready_1_411; // @[RegisterRouter.scala:87:24] wire out_roready_1_412; // @[RegisterRouter.scala:87:24] wire out_roready_1_413; // @[RegisterRouter.scala:87:24] wire out_roready_1_414; // @[RegisterRouter.scala:87:24] wire out_roready_1_415; // @[RegisterRouter.scala:87:24] wire out_roready_1_416; // @[RegisterRouter.scala:87:24] wire out_roready_1_417; // @[RegisterRouter.scala:87:24] wire out_roready_1_418; // @[RegisterRouter.scala:87:24] wire out_roready_1_419; // @[RegisterRouter.scala:87:24] wire out_roready_1_420; // @[RegisterRouter.scala:87:24] wire out_roready_1_421; // @[RegisterRouter.scala:87:24] wire out_roready_1_422; // @[RegisterRouter.scala:87:24] wire out_roready_1_423; // @[RegisterRouter.scala:87:24] wire out_roready_1_424; // @[RegisterRouter.scala:87:24] wire out_roready_1_425; // @[RegisterRouter.scala:87:24] wire out_roready_1_426; // @[RegisterRouter.scala:87:24] wire out_roready_1_427; // @[RegisterRouter.scala:87:24] wire out_roready_1_428; // @[RegisterRouter.scala:87:24] wire out_roready_1_429; // @[RegisterRouter.scala:87:24] wire out_roready_1_430; // @[RegisterRouter.scala:87:24] wire out_roready_1_431; // @[RegisterRouter.scala:87:24] wire out_roready_1_432; // @[RegisterRouter.scala:87:24] wire out_roready_1_433; // @[RegisterRouter.scala:87:24] wire out_roready_1_434; // @[RegisterRouter.scala:87:24] wire out_roready_1_435; // @[RegisterRouter.scala:87:24] wire out_roready_1_436; // @[RegisterRouter.scala:87:24] wire out_roready_1_437; // @[RegisterRouter.scala:87:24] wire out_roready_1_438; // @[RegisterRouter.scala:87:24] wire out_roready_1_439; // @[RegisterRouter.scala:87:24] wire out_roready_1_440; // @[RegisterRouter.scala:87:24] wire out_roready_1_441; // @[RegisterRouter.scala:87:24] wire out_roready_1_442; // @[RegisterRouter.scala:87:24] wire out_roready_1_443; // @[RegisterRouter.scala:87:24] wire out_roready_1_444; // @[RegisterRouter.scala:87:24] wire out_roready_1_445; // @[RegisterRouter.scala:87:24] wire out_roready_1_446; // @[RegisterRouter.scala:87:24] wire out_roready_1_447; // @[RegisterRouter.scala:87:24] wire out_roready_1_448; // @[RegisterRouter.scala:87:24] wire out_roready_1_449; // @[RegisterRouter.scala:87:24] wire out_roready_1_450; // @[RegisterRouter.scala:87:24] wire out_roready_1_451; // @[RegisterRouter.scala:87:24] wire out_roready_1_452; // @[RegisterRouter.scala:87:24] wire out_roready_1_453; // @[RegisterRouter.scala:87:24] wire out_roready_1_454; // @[RegisterRouter.scala:87:24] wire out_roready_1_455; // @[RegisterRouter.scala:87:24] wire out_roready_1_456; // @[RegisterRouter.scala:87:24] wire out_roready_1_457; // @[RegisterRouter.scala:87:24] wire out_roready_1_458; // @[RegisterRouter.scala:87:24] wire out_roready_1_459; // @[RegisterRouter.scala:87:24] wire out_roready_1_460; // @[RegisterRouter.scala:87:24] wire out_roready_1_461; // @[RegisterRouter.scala:87:24] wire out_roready_1_462; // @[RegisterRouter.scala:87:24] wire out_roready_1_463; // @[RegisterRouter.scala:87:24] wire out_roready_1_464; // @[RegisterRouter.scala:87:24] wire out_roready_1_465; // @[RegisterRouter.scala:87:24] wire out_roready_1_466; // @[RegisterRouter.scala:87:24] wire out_roready_1_467; // @[RegisterRouter.scala:87:24] wire out_roready_1_468; // @[RegisterRouter.scala:87:24] wire out_roready_1_469; // @[RegisterRouter.scala:87:24] wire out_roready_1_470; // @[RegisterRouter.scala:87:24] wire out_roready_1_471; // @[RegisterRouter.scala:87:24] wire out_roready_1_472; // @[RegisterRouter.scala:87:24] wire out_roready_1_473; // @[RegisterRouter.scala:87:24] wire out_roready_1_474; // @[RegisterRouter.scala:87:24] wire out_roready_1_475; // @[RegisterRouter.scala:87:24] wire out_roready_1_476; // @[RegisterRouter.scala:87:24] wire out_roready_1_477; // @[RegisterRouter.scala:87:24] wire out_roready_1_478; // @[RegisterRouter.scala:87:24] wire out_roready_1_479; // @[RegisterRouter.scala:87:24] wire out_roready_1_480; // @[RegisterRouter.scala:87:24] wire out_roready_1_481; // @[RegisterRouter.scala:87:24] wire out_roready_1_482; // @[RegisterRouter.scala:87:24] wire out_roready_1_483; // @[RegisterRouter.scala:87:24] wire out_roready_1_484; // @[RegisterRouter.scala:87:24] wire out_roready_1_485; // @[RegisterRouter.scala:87:24] wire out_roready_1_486; // @[RegisterRouter.scala:87:24] wire out_roready_1_487; // @[RegisterRouter.scala:87:24] wire out_roready_1_488; // @[RegisterRouter.scala:87:24] wire out_roready_1_489; // @[RegisterRouter.scala:87:24] wire out_roready_1_490; // @[RegisterRouter.scala:87:24] wire out_roready_1_491; // @[RegisterRouter.scala:87:24] wire out_roready_1_492; // @[RegisterRouter.scala:87:24] wire out_roready_1_493; // @[RegisterRouter.scala:87:24] wire out_roready_1_494; // @[RegisterRouter.scala:87:24] wire out_roready_1_495; // @[RegisterRouter.scala:87:24] wire out_roready_1_496; // @[RegisterRouter.scala:87:24] wire out_roready_1_497; // @[RegisterRouter.scala:87:24] wire out_roready_1_498; // @[RegisterRouter.scala:87:24] wire out_roready_1_499; // @[RegisterRouter.scala:87:24] wire out_roready_1_500; // @[RegisterRouter.scala:87:24] wire out_roready_1_501; // @[RegisterRouter.scala:87:24] wire out_roready_1_502; // @[RegisterRouter.scala:87:24] wire out_roready_1_503; // @[RegisterRouter.scala:87:24] wire out_roready_1_504; // @[RegisterRouter.scala:87:24] wire out_roready_1_505; // @[RegisterRouter.scala:87:24] wire out_roready_1_506; // @[RegisterRouter.scala:87:24] wire out_roready_1_507; // @[RegisterRouter.scala:87:24] wire out_roready_1_508; // @[RegisterRouter.scala:87:24] wire out_roready_1_509; // @[RegisterRouter.scala:87:24] wire out_roready_1_510; // @[RegisterRouter.scala:87:24] wire out_roready_1_511; // @[RegisterRouter.scala:87:24] wire out_roready_1_512; // @[RegisterRouter.scala:87:24] wire out_roready_1_513; // @[RegisterRouter.scala:87:24] wire out_roready_1_514; // @[RegisterRouter.scala:87:24] wire out_roready_1_515; // @[RegisterRouter.scala:87:24] wire out_roready_1_516; // @[RegisterRouter.scala:87:24] wire out_roready_1_517; // @[RegisterRouter.scala:87:24] wire out_roready_1_518; // @[RegisterRouter.scala:87:24] wire out_roready_1_519; // @[RegisterRouter.scala:87:24] wire out_roready_1_520; // @[RegisterRouter.scala:87:24] wire out_roready_1_521; // @[RegisterRouter.scala:87:24] wire out_roready_1_522; // @[RegisterRouter.scala:87:24] wire out_roready_1_523; // @[RegisterRouter.scala:87:24] wire out_roready_1_524; // @[RegisterRouter.scala:87:24] wire out_roready_1_525; // @[RegisterRouter.scala:87:24] wire out_roready_1_526; // @[RegisterRouter.scala:87:24] wire out_roready_1_527; // @[RegisterRouter.scala:87:24] wire out_roready_1_528; // @[RegisterRouter.scala:87:24] wire out_roready_1_529; // @[RegisterRouter.scala:87:24] wire out_roready_1_530; // @[RegisterRouter.scala:87:24] wire out_roready_1_531; // @[RegisterRouter.scala:87:24] wire out_roready_1_532; // @[RegisterRouter.scala:87:24] wire out_roready_1_533; // @[RegisterRouter.scala:87:24] wire out_roready_1_534; // @[RegisterRouter.scala:87:24] wire out_roready_1_535; // @[RegisterRouter.scala:87:24] wire out_roready_1_536; // @[RegisterRouter.scala:87:24] wire out_roready_1_537; // @[RegisterRouter.scala:87:24] wire out_roready_1_538; // @[RegisterRouter.scala:87:24] wire out_roready_1_539; // @[RegisterRouter.scala:87:24] wire out_roready_1_540; // @[RegisterRouter.scala:87:24] wire out_roready_1_541; // @[RegisterRouter.scala:87:24] wire out_roready_1_542; // @[RegisterRouter.scala:87:24] wire out_roready_1_543; // @[RegisterRouter.scala:87:24] wire out_roready_1_544; // @[RegisterRouter.scala:87:24] wire out_roready_1_545; // @[RegisterRouter.scala:87:24] wire out_roready_1_546; // @[RegisterRouter.scala:87:24] wire out_roready_1_547; // @[RegisterRouter.scala:87:24] wire out_roready_1_548; // @[RegisterRouter.scala:87:24] wire out_roready_1_549; // @[RegisterRouter.scala:87:24] wire out_roready_1_550; // @[RegisterRouter.scala:87:24] wire out_roready_1_551; // @[RegisterRouter.scala:87:24] wire out_roready_1_552; // @[RegisterRouter.scala:87:24] wire out_roready_1_553; // @[RegisterRouter.scala:87:24] wire out_roready_1_554; // @[RegisterRouter.scala:87:24] wire out_roready_1_555; // @[RegisterRouter.scala:87:24] wire out_roready_1_556; // @[RegisterRouter.scala:87:24] wire out_roready_1_557; // @[RegisterRouter.scala:87:24] wire out_roready_1_558; // @[RegisterRouter.scala:87:24] wire out_roready_1_559; // @[RegisterRouter.scala:87:24] wire out_roready_1_560; // @[RegisterRouter.scala:87:24] wire out_roready_1_561; // @[RegisterRouter.scala:87:24] wire out_roready_1_562; // @[RegisterRouter.scala:87:24] wire out_roready_1_563; // @[RegisterRouter.scala:87:24] wire out_roready_1_564; // @[RegisterRouter.scala:87:24] wire out_roready_1_565; // @[RegisterRouter.scala:87:24] wire out_roready_1_566; // @[RegisterRouter.scala:87:24] wire out_roready_1_567; // @[RegisterRouter.scala:87:24] wire out_roready_1_568; // @[RegisterRouter.scala:87:24] wire out_roready_1_569; // @[RegisterRouter.scala:87:24] wire out_roready_1_570; // @[RegisterRouter.scala:87:24] wire out_roready_1_571; // @[RegisterRouter.scala:87:24] wire out_roready_1_572; // @[RegisterRouter.scala:87:24] wire out_roready_1_573; // @[RegisterRouter.scala:87:24] wire out_roready_1_574; // @[RegisterRouter.scala:87:24] wire out_roready_1_575; // @[RegisterRouter.scala:87:24] wire out_roready_1_576; // @[RegisterRouter.scala:87:24] wire out_roready_1_577; // @[RegisterRouter.scala:87:24] wire out_roready_1_578; // @[RegisterRouter.scala:87:24] wire out_roready_1_579; // @[RegisterRouter.scala:87:24] wire out_roready_1_580; // @[RegisterRouter.scala:87:24] wire out_roready_1_581; // @[RegisterRouter.scala:87:24] wire out_roready_1_582; // @[RegisterRouter.scala:87:24] wire out_roready_1_583; // @[RegisterRouter.scala:87:24] wire out_roready_1_584; // @[RegisterRouter.scala:87:24] wire out_roready_1_585; // @[RegisterRouter.scala:87:24] wire out_roready_1_586; // @[RegisterRouter.scala:87:24] wire out_roready_1_587; // @[RegisterRouter.scala:87:24] wire out_roready_1_588; // @[RegisterRouter.scala:87:24] wire out_roready_1_589; // @[RegisterRouter.scala:87:24] wire out_roready_1_590; // @[RegisterRouter.scala:87:24] wire out_roready_1_591; // @[RegisterRouter.scala:87:24] wire out_roready_1_592; // @[RegisterRouter.scala:87:24] wire out_roready_1_593; // @[RegisterRouter.scala:87:24] wire out_roready_1_594; // @[RegisterRouter.scala:87:24] wire out_roready_1_595; // @[RegisterRouter.scala:87:24] wire out_roready_1_596; // @[RegisterRouter.scala:87:24] wire out_roready_1_597; // @[RegisterRouter.scala:87:24] wire out_roready_1_598; // @[RegisterRouter.scala:87:24] wire out_roready_1_599; // @[RegisterRouter.scala:87:24] wire out_roready_1_600; // @[RegisterRouter.scala:87:24] wire out_roready_1_601; // @[RegisterRouter.scala:87:24] wire out_roready_1_602; // @[RegisterRouter.scala:87:24] wire out_roready_1_603; // @[RegisterRouter.scala:87:24] wire out_roready_1_604; // @[RegisterRouter.scala:87:24] wire out_roready_1_605; // @[RegisterRouter.scala:87:24] wire out_roready_1_606; // @[RegisterRouter.scala:87:24] wire out_roready_1_607; // @[RegisterRouter.scala:87:24] wire out_roready_1_608; // @[RegisterRouter.scala:87:24] wire out_roready_1_609; // @[RegisterRouter.scala:87:24] wire out_roready_1_610; // @[RegisterRouter.scala:87:24] wire out_roready_1_611; // @[RegisterRouter.scala:87:24] wire out_roready_1_612; // @[RegisterRouter.scala:87:24] wire out_roready_1_613; // @[RegisterRouter.scala:87:24] wire out_roready_1_614; // @[RegisterRouter.scala:87:24] wire out_roready_1_615; // @[RegisterRouter.scala:87:24] wire out_roready_1_616; // @[RegisterRouter.scala:87:24] wire out_roready_1_617; // @[RegisterRouter.scala:87:24] wire out_roready_1_618; // @[RegisterRouter.scala:87:24] wire out_roready_1_619; // @[RegisterRouter.scala:87:24] wire out_roready_1_620; // @[RegisterRouter.scala:87:24] wire out_roready_1_621; // @[RegisterRouter.scala:87:24] wire out_roready_1_622; // @[RegisterRouter.scala:87:24] wire out_roready_1_623; // @[RegisterRouter.scala:87:24] wire out_roready_1_624; // @[RegisterRouter.scala:87:24] wire out_roready_1_625; // @[RegisterRouter.scala:87:24] wire out_roready_1_626; // @[RegisterRouter.scala:87:24] wire out_roready_1_627; // @[RegisterRouter.scala:87:24] wire out_roready_1_628; // @[RegisterRouter.scala:87:24] wire out_roready_1_629; // @[RegisterRouter.scala:87:24] wire out_roready_1_630; // @[RegisterRouter.scala:87:24] wire out_roready_1_631; // @[RegisterRouter.scala:87:24] wire out_roready_1_632; // @[RegisterRouter.scala:87:24] wire out_roready_1_633; // @[RegisterRouter.scala:87:24] wire out_roready_1_634; // @[RegisterRouter.scala:87:24] wire out_roready_1_635; // @[RegisterRouter.scala:87:24] wire out_roready_1_636; // @[RegisterRouter.scala:87:24] wire out_roready_1_637; // @[RegisterRouter.scala:87:24] wire out_roready_1_638; // @[RegisterRouter.scala:87:24] wire out_roready_1_639; // @[RegisterRouter.scala:87:24] wire out_roready_1_640; // @[RegisterRouter.scala:87:24] wire out_roready_1_641; // @[RegisterRouter.scala:87:24] wire out_roready_1_642; // @[RegisterRouter.scala:87:24] wire out_roready_1_643; // @[RegisterRouter.scala:87:24] wire out_roready_1_644; // @[RegisterRouter.scala:87:24] wire out_roready_1_645; // @[RegisterRouter.scala:87:24] wire out_roready_1_646; // @[RegisterRouter.scala:87:24] wire out_roready_1_647; // @[RegisterRouter.scala:87:24] wire out_roready_1_648; // @[RegisterRouter.scala:87:24] wire out_roready_1_649; // @[RegisterRouter.scala:87:24] wire out_roready_1_650; // @[RegisterRouter.scala:87:24] wire out_roready_1_651; // @[RegisterRouter.scala:87:24] wire out_roready_1_652; // @[RegisterRouter.scala:87:24] wire out_roready_1_653; // @[RegisterRouter.scala:87:24] wire out_roready_1_654; // @[RegisterRouter.scala:87:24] wire out_roready_1_655; // @[RegisterRouter.scala:87:24] wire out_roready_1_656; // @[RegisterRouter.scala:87:24] wire out_roready_1_657; // @[RegisterRouter.scala:87:24] wire out_roready_1_658; // @[RegisterRouter.scala:87:24] wire out_roready_1_659; // @[RegisterRouter.scala:87:24] wire out_roready_1_660; // @[RegisterRouter.scala:87:24] wire out_roready_1_661; // @[RegisterRouter.scala:87:24] wire out_roready_1_662; // @[RegisterRouter.scala:87:24] wire out_roready_1_663; // @[RegisterRouter.scala:87:24] wire out_roready_1_664; // @[RegisterRouter.scala:87:24] wire out_roready_1_665; // @[RegisterRouter.scala:87:24] wire out_roready_1_666; // @[RegisterRouter.scala:87:24] wire out_roready_1_667; // @[RegisterRouter.scala:87:24] wire out_roready_1_668; // @[RegisterRouter.scala:87:24] wire out_roready_1_669; // @[RegisterRouter.scala:87:24] wire out_roready_1_670; // @[RegisterRouter.scala:87:24] wire out_roready_1_671; // @[RegisterRouter.scala:87:24] wire out_roready_1_672; // @[RegisterRouter.scala:87:24] wire out_roready_1_673; // @[RegisterRouter.scala:87:24] wire out_roready_1_674; // @[RegisterRouter.scala:87:24] wire out_roready_1_675; // @[RegisterRouter.scala:87:24] wire out_roready_1_676; // @[RegisterRouter.scala:87:24] wire out_roready_1_677; // @[RegisterRouter.scala:87:24] wire out_roready_1_678; // @[RegisterRouter.scala:87:24] wire out_roready_1_679; // @[RegisterRouter.scala:87:24] wire out_roready_1_680; // @[RegisterRouter.scala:87:24] wire out_roready_1_681; // @[RegisterRouter.scala:87:24] wire out_roready_1_682; // @[RegisterRouter.scala:87:24] wire out_roready_1_683; // @[RegisterRouter.scala:87:24] wire out_roready_1_684; // @[RegisterRouter.scala:87:24] wire out_roready_1_685; // @[RegisterRouter.scala:87:24] wire out_roready_1_686; // @[RegisterRouter.scala:87:24] wire out_roready_1_687; // @[RegisterRouter.scala:87:24] wire out_roready_1_688; // @[RegisterRouter.scala:87:24] wire out_roready_1_689; // @[RegisterRouter.scala:87:24] wire out_roready_1_690; // @[RegisterRouter.scala:87:24] wire out_roready_1_691; // @[RegisterRouter.scala:87:24] wire out_roready_1_692; // @[RegisterRouter.scala:87:24] wire out_roready_1_693; // @[RegisterRouter.scala:87:24] wire out_roready_1_694; // @[RegisterRouter.scala:87:24] wire out_roready_1_695; // @[RegisterRouter.scala:87:24] wire out_roready_1_696; // @[RegisterRouter.scala:87:24] wire out_roready_1_697; // @[RegisterRouter.scala:87:24] wire out_roready_1_698; // @[RegisterRouter.scala:87:24] wire out_roready_1_699; // @[RegisterRouter.scala:87:24] wire out_roready_1_700; // @[RegisterRouter.scala:87:24] wire out_roready_1_701; // @[RegisterRouter.scala:87:24] wire out_roready_1_702; // @[RegisterRouter.scala:87:24] wire out_roready_1_703; // @[RegisterRouter.scala:87:24] wire out_roready_1_704; // @[RegisterRouter.scala:87:24] wire out_roready_1_705; // @[RegisterRouter.scala:87:24] wire out_roready_1_706; // @[RegisterRouter.scala:87:24] wire out_roready_1_707; // @[RegisterRouter.scala:87:24] wire out_roready_1_708; // @[RegisterRouter.scala:87:24] wire out_roready_1_709; // @[RegisterRouter.scala:87:24] wire out_roready_1_710; // @[RegisterRouter.scala:87:24] wire out_roready_1_711; // @[RegisterRouter.scala:87:24] wire out_roready_1_712; // @[RegisterRouter.scala:87:24] wire out_roready_1_713; // @[RegisterRouter.scala:87:24] wire out_roready_1_714; // @[RegisterRouter.scala:87:24] wire out_roready_1_715; // @[RegisterRouter.scala:87:24] wire out_roready_1_716; // @[RegisterRouter.scala:87:24] wire out_roready_1_717; // @[RegisterRouter.scala:87:24] wire out_roready_1_718; // @[RegisterRouter.scala:87:24] wire out_roready_1_719; // @[RegisterRouter.scala:87:24] wire out_roready_1_720; // @[RegisterRouter.scala:87:24] wire out_roready_1_721; // @[RegisterRouter.scala:87:24] wire out_roready_1_722; // @[RegisterRouter.scala:87:24] wire out_roready_1_723; // @[RegisterRouter.scala:87:24] wire out_roready_1_724; // @[RegisterRouter.scala:87:24] wire out_roready_1_725; // @[RegisterRouter.scala:87:24] wire out_roready_1_726; // @[RegisterRouter.scala:87:24] wire out_roready_1_727; // @[RegisterRouter.scala:87:24] wire out_roready_1_728; // @[RegisterRouter.scala:87:24] wire out_roready_1_729; // @[RegisterRouter.scala:87:24] wire out_roready_1_730; // @[RegisterRouter.scala:87:24] wire out_roready_1_731; // @[RegisterRouter.scala:87:24] wire out_roready_1_732; // @[RegisterRouter.scala:87:24] wire out_roready_1_733; // @[RegisterRouter.scala:87:24] wire out_roready_1_734; // @[RegisterRouter.scala:87:24] wire out_roready_1_735; // @[RegisterRouter.scala:87:24] wire out_roready_1_736; // @[RegisterRouter.scala:87:24] wire out_roready_1_737; // @[RegisterRouter.scala:87:24] wire out_roready_1_738; // @[RegisterRouter.scala:87:24] wire out_roready_1_739; // @[RegisterRouter.scala:87:24] wire out_roready_1_740; // @[RegisterRouter.scala:87:24] wire out_roready_1_741; // @[RegisterRouter.scala:87:24] wire out_roready_1_742; // @[RegisterRouter.scala:87:24] wire out_roready_1_743; // @[RegisterRouter.scala:87:24] wire out_roready_1_744; // @[RegisterRouter.scala:87:24] wire out_roready_1_745; // @[RegisterRouter.scala:87:24] wire out_roready_1_746; // @[RegisterRouter.scala:87:24] wire out_roready_1_747; // @[RegisterRouter.scala:87:24] wire out_roready_1_748; // @[RegisterRouter.scala:87:24] wire out_roready_1_749; // @[RegisterRouter.scala:87:24] wire out_roready_1_750; // @[RegisterRouter.scala:87:24] wire out_roready_1_751; // @[RegisterRouter.scala:87:24] wire out_roready_1_752; // @[RegisterRouter.scala:87:24] wire out_roready_1_753; // @[RegisterRouter.scala:87:24] wire out_roready_1_754; // @[RegisterRouter.scala:87:24] wire out_roready_1_755; // @[RegisterRouter.scala:87:24] wire out_roready_1_756; // @[RegisterRouter.scala:87:24] wire out_roready_1_757; // @[RegisterRouter.scala:87:24] wire out_roready_1_758; // @[RegisterRouter.scala:87:24] wire out_roready_1_759; // @[RegisterRouter.scala:87:24] wire out_roready_1_760; // @[RegisterRouter.scala:87:24] wire out_roready_1_761; // @[RegisterRouter.scala:87:24] wire out_roready_1_762; // @[RegisterRouter.scala:87:24] wire out_roready_1_763; // @[RegisterRouter.scala:87:24] wire out_roready_1_764; // @[RegisterRouter.scala:87:24] wire out_roready_1_765; // @[RegisterRouter.scala:87:24] wire out_roready_1_766; // @[RegisterRouter.scala:87:24] wire out_roready_1_767; // @[RegisterRouter.scala:87:24] wire out_roready_1_768; // @[RegisterRouter.scala:87:24] wire out_roready_1_769; // @[RegisterRouter.scala:87:24] wire out_roready_1_770; // @[RegisterRouter.scala:87:24] wire out_roready_1_771; // @[RegisterRouter.scala:87:24] wire out_roready_1_772; // @[RegisterRouter.scala:87:24] wire out_roready_1_773; // @[RegisterRouter.scala:87:24] wire out_roready_1_774; // @[RegisterRouter.scala:87:24] wire out_roready_1_775; // @[RegisterRouter.scala:87:24] wire out_roready_1_776; // @[RegisterRouter.scala:87:24] wire out_roready_1_777; // @[RegisterRouter.scala:87:24] wire out_roready_1_778; // @[RegisterRouter.scala:87:24] wire out_roready_1_779; // @[RegisterRouter.scala:87:24] wire out_roready_1_780; // @[RegisterRouter.scala:87:24] wire out_roready_1_781; // @[RegisterRouter.scala:87:24] wire out_roready_1_782; // @[RegisterRouter.scala:87:24] wire out_roready_1_783; // @[RegisterRouter.scala:87:24] wire out_roready_1_784; // @[RegisterRouter.scala:87:24] wire out_roready_1_785; // @[RegisterRouter.scala:87:24] wire out_roready_1_786; // @[RegisterRouter.scala:87:24] wire out_roready_1_787; // @[RegisterRouter.scala:87:24] wire out_roready_1_788; // @[RegisterRouter.scala:87:24] wire out_roready_1_789; // @[RegisterRouter.scala:87:24] wire out_roready_1_790; // @[RegisterRouter.scala:87:24] wire out_roready_1_791; // @[RegisterRouter.scala:87:24] wire out_roready_1_792; // @[RegisterRouter.scala:87:24] wire out_roready_1_793; // @[RegisterRouter.scala:87:24] wire out_roready_1_794; // @[RegisterRouter.scala:87:24] wire out_roready_1_795; // @[RegisterRouter.scala:87:24] wire out_roready_1_796; // @[RegisterRouter.scala:87:24] wire out_roready_1_797; // @[RegisterRouter.scala:87:24] wire out_roready_1_798; // @[RegisterRouter.scala:87:24] wire out_roready_1_799; // @[RegisterRouter.scala:87:24] wire out_roready_1_800; // @[RegisterRouter.scala:87:24] wire out_roready_1_801; // @[RegisterRouter.scala:87:24] wire out_roready_1_802; // @[RegisterRouter.scala:87:24] wire out_roready_1_803; // @[RegisterRouter.scala:87:24] wire out_roready_1_804; // @[RegisterRouter.scala:87:24] wire out_roready_1_805; // @[RegisterRouter.scala:87:24] wire out_roready_1_806; // @[RegisterRouter.scala:87:24] wire out_roready_1_807; // @[RegisterRouter.scala:87:24] wire out_roready_1_808; // @[RegisterRouter.scala:87:24] wire out_roready_1_809; // @[RegisterRouter.scala:87:24] wire out_roready_1_810; // @[RegisterRouter.scala:87:24] wire out_roready_1_811; // @[RegisterRouter.scala:87:24] wire out_roready_1_812; // @[RegisterRouter.scala:87:24] wire out_roready_1_813; // @[RegisterRouter.scala:87:24] wire out_roready_1_814; // @[RegisterRouter.scala:87:24] wire out_roready_1_815; // @[RegisterRouter.scala:87:24] wire out_roready_1_816; // @[RegisterRouter.scala:87:24] wire out_roready_1_817; // @[RegisterRouter.scala:87:24] wire out_roready_1_818; // @[RegisterRouter.scala:87:24] wire out_roready_1_819; // @[RegisterRouter.scala:87:24] wire out_roready_1_820; // @[RegisterRouter.scala:87:24] wire out_roready_1_821; // @[RegisterRouter.scala:87:24] wire out_roready_1_822; // @[RegisterRouter.scala:87:24] wire out_roready_1_823; // @[RegisterRouter.scala:87:24] wire out_roready_1_824; // @[RegisterRouter.scala:87:24] wire out_roready_1_825; // @[RegisterRouter.scala:87:24] wire out_roready_1_826; // @[RegisterRouter.scala:87:24] wire out_roready_1_827; // @[RegisterRouter.scala:87:24] wire out_roready_1_828; // @[RegisterRouter.scala:87:24] wire out_roready_1_829; // @[RegisterRouter.scala:87:24] wire out_roready_1_830; // @[RegisterRouter.scala:87:24] wire out_roready_1_831; // @[RegisterRouter.scala:87:24] wire out_roready_1_832; // @[RegisterRouter.scala:87:24] wire out_roready_1_833; // @[RegisterRouter.scala:87:24] wire out_roready_1_834; // @[RegisterRouter.scala:87:24] wire out_roready_1_835; // @[RegisterRouter.scala:87:24] wire out_roready_1_836; // @[RegisterRouter.scala:87:24] wire out_roready_1_837; // @[RegisterRouter.scala:87:24] wire out_roready_1_838; // @[RegisterRouter.scala:87:24] wire out_roready_1_839; // @[RegisterRouter.scala:87:24] wire out_roready_1_840; // @[RegisterRouter.scala:87:24] wire out_roready_1_841; // @[RegisterRouter.scala:87:24] wire out_roready_1_842; // @[RegisterRouter.scala:87:24] wire out_roready_1_843; // @[RegisterRouter.scala:87:24] wire out_roready_1_844; // @[RegisterRouter.scala:87:24] wire out_roready_1_845; // @[RegisterRouter.scala:87:24] wire out_roready_1_846; // @[RegisterRouter.scala:87:24] wire out_roready_1_847; // @[RegisterRouter.scala:87:24] wire out_roready_1_848; // @[RegisterRouter.scala:87:24] wire out_roready_1_849; // @[RegisterRouter.scala:87:24] wire out_roready_1_850; // @[RegisterRouter.scala:87:24] wire out_roready_1_851; // @[RegisterRouter.scala:87:24] wire out_roready_1_852; // @[RegisterRouter.scala:87:24] wire out_roready_1_853; // @[RegisterRouter.scala:87:24] wire out_roready_1_854; // @[RegisterRouter.scala:87:24] wire out_roready_1_855; // @[RegisterRouter.scala:87:24] wire out_roready_1_856; // @[RegisterRouter.scala:87:24] wire out_roready_1_857; // @[RegisterRouter.scala:87:24] wire out_roready_1_858; // @[RegisterRouter.scala:87:24] wire out_roready_1_859; // @[RegisterRouter.scala:87:24] wire out_roready_1_860; // @[RegisterRouter.scala:87:24] wire out_roready_1_861; // @[RegisterRouter.scala:87:24] wire out_roready_1_862; // @[RegisterRouter.scala:87:24] wire out_roready_1_863; // @[RegisterRouter.scala:87:24] wire out_roready_1_864; // @[RegisterRouter.scala:87:24] wire out_roready_1_865; // @[RegisterRouter.scala:87:24] wire out_roready_1_866; // @[RegisterRouter.scala:87:24] wire out_roready_1_867; // @[RegisterRouter.scala:87:24] wire out_roready_1_868; // @[RegisterRouter.scala:87:24] wire out_roready_1_869; // @[RegisterRouter.scala:87:24] wire out_roready_1_870; // @[RegisterRouter.scala:87:24] wire out_roready_1_871; // @[RegisterRouter.scala:87:24] wire out_roready_1_872; // @[RegisterRouter.scala:87:24] wire out_roready_1_873; // @[RegisterRouter.scala:87:24] wire out_roready_1_874; // @[RegisterRouter.scala:87:24] wire out_roready_1_875; // @[RegisterRouter.scala:87:24] wire out_roready_1_876; // @[RegisterRouter.scala:87:24] wire out_roready_1_877; // @[RegisterRouter.scala:87:24] wire out_roready_1_878; // @[RegisterRouter.scala:87:24] wire out_roready_1_879; // @[RegisterRouter.scala:87:24] wire out_roready_1_880; // @[RegisterRouter.scala:87:24] wire out_roready_1_881; // @[RegisterRouter.scala:87:24] wire out_roready_1_882; // @[RegisterRouter.scala:87:24] wire out_roready_1_883; // @[RegisterRouter.scala:87:24] wire out_roready_1_884; // @[RegisterRouter.scala:87:24] wire out_roready_1_885; // @[RegisterRouter.scala:87:24] wire out_roready_1_886; // @[RegisterRouter.scala:87:24] wire out_roready_1_887; // @[RegisterRouter.scala:87:24] wire out_roready_1_888; // @[RegisterRouter.scala:87:24] wire out_roready_1_889; // @[RegisterRouter.scala:87:24] wire out_roready_1_890; // @[RegisterRouter.scala:87:24] wire out_roready_1_891; // @[RegisterRouter.scala:87:24] wire out_roready_1_892; // @[RegisterRouter.scala:87:24] wire out_roready_1_893; // @[RegisterRouter.scala:87:24] wire out_roready_1_894; // @[RegisterRouter.scala:87:24] wire out_roready_1_895; // @[RegisterRouter.scala:87:24] wire out_roready_1_896; // @[RegisterRouter.scala:87:24] wire out_roready_1_897; // @[RegisterRouter.scala:87:24] wire out_roready_1_898; // @[RegisterRouter.scala:87:24] wire out_roready_1_899; // @[RegisterRouter.scala:87:24] wire out_roready_1_900; // @[RegisterRouter.scala:87:24] wire out_roready_1_901; // @[RegisterRouter.scala:87:24] wire out_roready_1_902; // @[RegisterRouter.scala:87:24] wire out_roready_1_903; // @[RegisterRouter.scala:87:24] wire out_roready_1_904; // @[RegisterRouter.scala:87:24] wire out_roready_1_905; // @[RegisterRouter.scala:87:24] wire out_roready_1_906; // @[RegisterRouter.scala:87:24] wire out_roready_1_907; // @[RegisterRouter.scala:87:24] wire out_roready_1_908; // @[RegisterRouter.scala:87:24] wire out_roready_1_909; // @[RegisterRouter.scala:87:24] wire out_roready_1_910; // @[RegisterRouter.scala:87:24] wire out_roready_1_911; // @[RegisterRouter.scala:87:24] wire out_roready_1_912; // @[RegisterRouter.scala:87:24] wire out_roready_1_913; // @[RegisterRouter.scala:87:24] wire out_roready_1_914; // @[RegisterRouter.scala:87:24] wire out_roready_1_915; // @[RegisterRouter.scala:87:24] wire out_roready_1_916; // @[RegisterRouter.scala:87:24] wire out_roready_1_917; // @[RegisterRouter.scala:87:24] wire out_roready_1_918; // @[RegisterRouter.scala:87:24] wire out_roready_1_919; // @[RegisterRouter.scala:87:24] wire out_roready_1_920; // @[RegisterRouter.scala:87:24] wire out_roready_1_921; // @[RegisterRouter.scala:87:24] wire out_roready_1_922; // @[RegisterRouter.scala:87:24] wire out_roready_1_923; // @[RegisterRouter.scala:87:24] wire out_roready_1_924; // @[RegisterRouter.scala:87:24] wire out_roready_1_925; // @[RegisterRouter.scala:87:24] wire out_roready_1_926; // @[RegisterRouter.scala:87:24] wire out_roready_1_927; // @[RegisterRouter.scala:87:24] wire out_roready_1_928; // @[RegisterRouter.scala:87:24] wire out_roready_1_929; // @[RegisterRouter.scala:87:24] wire out_roready_1_930; // @[RegisterRouter.scala:87:24] wire out_roready_1_931; // @[RegisterRouter.scala:87:24] wire out_roready_1_932; // @[RegisterRouter.scala:87:24] wire out_roready_1_933; // @[RegisterRouter.scala:87:24] wire out_roready_1_934; // @[RegisterRouter.scala:87:24] wire out_roready_1_935; // @[RegisterRouter.scala:87:24] wire out_roready_1_936; // @[RegisterRouter.scala:87:24] wire out_roready_1_937; // @[RegisterRouter.scala:87:24] wire out_roready_1_938; // @[RegisterRouter.scala:87:24] wire out_roready_1_939; // @[RegisterRouter.scala:87:24] wire out_roready_1_940; // @[RegisterRouter.scala:87:24] wire out_roready_1_941; // @[RegisterRouter.scala:87:24] wire out_roready_1_942; // @[RegisterRouter.scala:87:24] wire out_roready_1_943; // @[RegisterRouter.scala:87:24] wire out_roready_1_944; // @[RegisterRouter.scala:87:24] wire out_roready_1_945; // @[RegisterRouter.scala:87:24] wire out_roready_1_946; // @[RegisterRouter.scala:87:24] wire out_roready_1_947; // @[RegisterRouter.scala:87:24] wire out_roready_1_948; // @[RegisterRouter.scala:87:24] wire out_roready_1_949; // @[RegisterRouter.scala:87:24] wire out_roready_1_950; // @[RegisterRouter.scala:87:24] wire out_roready_1_951; // @[RegisterRouter.scala:87:24] wire out_roready_1_952; // @[RegisterRouter.scala:87:24] wire out_roready_1_953; // @[RegisterRouter.scala:87:24] wire out_roready_1_954; // @[RegisterRouter.scala:87:24] wire out_roready_1_955; // @[RegisterRouter.scala:87:24] wire out_roready_1_956; // @[RegisterRouter.scala:87:24] wire out_roready_1_957; // @[RegisterRouter.scala:87:24] wire out_roready_1_958; // @[RegisterRouter.scala:87:24] wire out_roready_1_959; // @[RegisterRouter.scala:87:24] wire out_roready_1_960; // @[RegisterRouter.scala:87:24] wire out_roready_1_961; // @[RegisterRouter.scala:87:24] wire out_roready_1_962; // @[RegisterRouter.scala:87:24] wire out_roready_1_963; // @[RegisterRouter.scala:87:24] wire out_roready_1_964; // @[RegisterRouter.scala:87:24] wire out_roready_1_965; // @[RegisterRouter.scala:87:24] wire out_roready_1_966; // @[RegisterRouter.scala:87:24] wire out_roready_1_967; // @[RegisterRouter.scala:87:24] wire out_roready_1_968; // @[RegisterRouter.scala:87:24] wire out_roready_1_969; // @[RegisterRouter.scala:87:24] wire out_roready_1_970; // @[RegisterRouter.scala:87:24] wire out_roready_1_971; // @[RegisterRouter.scala:87:24] wire out_roready_1_972; // @[RegisterRouter.scala:87:24] wire out_roready_1_973; // @[RegisterRouter.scala:87:24] wire out_roready_1_974; // @[RegisterRouter.scala:87:24] wire out_roready_1_975; // @[RegisterRouter.scala:87:24] wire out_roready_1_976; // @[RegisterRouter.scala:87:24] wire out_roready_1_977; // @[RegisterRouter.scala:87:24] wire out_roready_1_978; // @[RegisterRouter.scala:87:24] wire out_roready_1_979; // @[RegisterRouter.scala:87:24] wire out_roready_1_980; // @[RegisterRouter.scala:87:24] wire out_roready_1_981; // @[RegisterRouter.scala:87:24] wire out_roready_1_982; // @[RegisterRouter.scala:87:24] wire out_roready_1_983; // @[RegisterRouter.scala:87:24] wire out_roready_1_984; // @[RegisterRouter.scala:87:24] wire out_roready_1_985; // @[RegisterRouter.scala:87:24] wire out_roready_1_986; // @[RegisterRouter.scala:87:24] wire out_roready_1_987; // @[RegisterRouter.scala:87:24] wire out_roready_1_988; // @[RegisterRouter.scala:87:24] wire out_roready_1_989; // @[RegisterRouter.scala:87:24] wire out_roready_1_990; // @[RegisterRouter.scala:87:24] wire out_roready_1_991; // @[RegisterRouter.scala:87:24] wire out_roready_1_992; // @[RegisterRouter.scala:87:24] wire out_roready_1_993; // @[RegisterRouter.scala:87:24] wire out_roready_1_994; // @[RegisterRouter.scala:87:24] wire out_roready_1_995; // @[RegisterRouter.scala:87:24] wire out_roready_1_996; // @[RegisterRouter.scala:87:24] wire out_roready_1_997; // @[RegisterRouter.scala:87:24] wire out_roready_1_998; // @[RegisterRouter.scala:87:24] wire out_roready_1_999; // @[RegisterRouter.scala:87:24] wire out_roready_1_1000; // @[RegisterRouter.scala:87:24] wire out_roready_1_1001; // @[RegisterRouter.scala:87:24] wire out_roready_1_1002; // @[RegisterRouter.scala:87:24] wire out_roready_1_1003; // @[RegisterRouter.scala:87:24] wire out_roready_1_1004; // @[RegisterRouter.scala:87:24] wire out_roready_1_1005; // @[RegisterRouter.scala:87:24] wire out_roready_1_1006; // @[RegisterRouter.scala:87:24] wire out_roready_1_1007; // @[RegisterRouter.scala:87:24] wire out_roready_1_1008; // @[RegisterRouter.scala:87:24] wire out_roready_1_1009; // @[RegisterRouter.scala:87:24] wire out_roready_1_1010; // @[RegisterRouter.scala:87:24] wire out_roready_1_1011; // @[RegisterRouter.scala:87:24] wire out_roready_1_1012; // @[RegisterRouter.scala:87:24] wire out_roready_1_1013; // @[RegisterRouter.scala:87:24] wire out_roready_1_1014; // @[RegisterRouter.scala:87:24] wire out_roready_1_1015; // @[RegisterRouter.scala:87:24] wire out_roready_1_1016; // @[RegisterRouter.scala:87:24] wire out_roready_1_1017; // @[RegisterRouter.scala:87:24] wire out_roready_1_1018; // @[RegisterRouter.scala:87:24] wire out_roready_1_1019; // @[RegisterRouter.scala:87:24] wire out_roready_1_1020; // @[RegisterRouter.scala:87:24] wire out_roready_1_1021; // @[RegisterRouter.scala:87:24] wire out_roready_1_1022; // @[RegisterRouter.scala:87:24] wire out_roready_1_1023; // @[RegisterRouter.scala:87:24] wire out_roready_1_1024; // @[RegisterRouter.scala:87:24] wire out_roready_1_1025; // @[RegisterRouter.scala:87:24] wire out_roready_1_1026; // @[RegisterRouter.scala:87:24] wire out_roready_1_1027; // @[RegisterRouter.scala:87:24] wire out_roready_1_1028; // @[RegisterRouter.scala:87:24] wire out_roready_1_1029; // @[RegisterRouter.scala:87:24] wire out_roready_1_1030; // @[RegisterRouter.scala:87:24] wire out_roready_1_1031; // @[RegisterRouter.scala:87:24] wire out_roready_1_1032; // @[RegisterRouter.scala:87:24] wire out_roready_1_1033; // @[RegisterRouter.scala:87:24] wire out_roready_1_1034; // @[RegisterRouter.scala:87:24] wire out_roready_1_1035; // @[RegisterRouter.scala:87:24] wire out_roready_1_1036; // @[RegisterRouter.scala:87:24] wire out_roready_1_1037; // @[RegisterRouter.scala:87:24] wire out_roready_1_1038; // @[RegisterRouter.scala:87:24] wire out_roready_1_1039; // @[RegisterRouter.scala:87:24] wire out_roready_1_1040; // @[RegisterRouter.scala:87:24] wire out_roready_1_1041; // @[RegisterRouter.scala:87:24] wire out_roready_1_1042; // @[RegisterRouter.scala:87:24] wire out_roready_1_1043; // @[RegisterRouter.scala:87:24] wire out_roready_1_1044; // @[RegisterRouter.scala:87:24] wire out_roready_1_1045; // @[RegisterRouter.scala:87:24] wire out_roready_1_1046; // @[RegisterRouter.scala:87:24] wire out_roready_1_1047; // @[RegisterRouter.scala:87:24] wire out_roready_1_1048; // @[RegisterRouter.scala:87:24] wire out_roready_1_1049; // @[RegisterRouter.scala:87:24] wire out_roready_1_1050; // @[RegisterRouter.scala:87:24] wire out_roready_1_1051; // @[RegisterRouter.scala:87:24] wire out_roready_1_1052; // @[RegisterRouter.scala:87:24] wire out_roready_1_1053; // @[RegisterRouter.scala:87:24] wire out_roready_1_1054; // @[RegisterRouter.scala:87:24] wire out_roready_1_1055; // @[RegisterRouter.scala:87:24] wire out_roready_1_1056; // @[RegisterRouter.scala:87:24] wire out_roready_1_1057; // @[RegisterRouter.scala:87:24] wire out_roready_1_1058; // @[RegisterRouter.scala:87:24] wire out_roready_1_1059; // @[RegisterRouter.scala:87:24] wire out_roready_1_1060; // @[RegisterRouter.scala:87:24] wire out_roready_1_1061; // @[RegisterRouter.scala:87:24] wire out_roready_1_1062; // @[RegisterRouter.scala:87:24] wire out_roready_1_1063; // @[RegisterRouter.scala:87:24] wire out_roready_1_1064; // @[RegisterRouter.scala:87:24] wire out_roready_1_1065; // @[RegisterRouter.scala:87:24] wire out_roready_1_1066; // @[RegisterRouter.scala:87:24] wire out_roready_1_1067; // @[RegisterRouter.scala:87:24] wire out_roready_1_1068; // @[RegisterRouter.scala:87:24] wire out_roready_1_1069; // @[RegisterRouter.scala:87:24] wire out_roready_1_1070; // @[RegisterRouter.scala:87:24] wire out_roready_1_1071; // @[RegisterRouter.scala:87:24] wire out_roready_1_1072; // @[RegisterRouter.scala:87:24] wire out_roready_1_1073; // @[RegisterRouter.scala:87:24] wire out_roready_1_1074; // @[RegisterRouter.scala:87:24] wire out_roready_1_1075; // @[RegisterRouter.scala:87:24] wire out_roready_1_1076; // @[RegisterRouter.scala:87:24] wire out_roready_1_1077; // @[RegisterRouter.scala:87:24] wire out_roready_1_1078; // @[RegisterRouter.scala:87:24] wire out_roready_1_1079; // @[RegisterRouter.scala:87:24] wire out_roready_1_1080; // @[RegisterRouter.scala:87:24] wire out_roready_1_1081; // @[RegisterRouter.scala:87:24] wire out_roready_1_1082; // @[RegisterRouter.scala:87:24] wire out_roready_1_1083; // @[RegisterRouter.scala:87:24] wire out_roready_1_1084; // @[RegisterRouter.scala:87:24] wire out_roready_1_1085; // @[RegisterRouter.scala:87:24] wire out_roready_1_1086; // @[RegisterRouter.scala:87:24] wire out_roready_1_1087; // @[RegisterRouter.scala:87:24] wire out_roready_1_1088; // @[RegisterRouter.scala:87:24] wire out_roready_1_1089; // @[RegisterRouter.scala:87:24] wire out_roready_1_1090; // @[RegisterRouter.scala:87:24] wire out_roready_1_1091; // @[RegisterRouter.scala:87:24] wire out_roready_1_1092; // @[RegisterRouter.scala:87:24] wire out_roready_1_1093; // @[RegisterRouter.scala:87:24] wire out_roready_1_1094; // @[RegisterRouter.scala:87:24] wire out_roready_1_1095; // @[RegisterRouter.scala:87:24] wire out_roready_1_1096; // @[RegisterRouter.scala:87:24] wire out_roready_1_1097; // @[RegisterRouter.scala:87:24] wire out_roready_1_1098; // @[RegisterRouter.scala:87:24] wire out_roready_1_1099; // @[RegisterRouter.scala:87:24] wire out_roready_1_1100; // @[RegisterRouter.scala:87:24] wire out_roready_1_1101; // @[RegisterRouter.scala:87:24] wire out_roready_1_1102; // @[RegisterRouter.scala:87:24] wire out_roready_1_1103; // @[RegisterRouter.scala:87:24] wire out_roready_1_1104; // @[RegisterRouter.scala:87:24] wire out_roready_1_1105; // @[RegisterRouter.scala:87:24] wire out_roready_1_1106; // @[RegisterRouter.scala:87:24] wire out_roready_1_1107; // @[RegisterRouter.scala:87:24] wire out_roready_1_1108; // @[RegisterRouter.scala:87:24] wire out_roready_1_1109; // @[RegisterRouter.scala:87:24] wire out_roready_1_1110; // @[RegisterRouter.scala:87:24] wire out_roready_1_1111; // @[RegisterRouter.scala:87:24] wire out_roready_1_1112; // @[RegisterRouter.scala:87:24] wire out_roready_1_1113; // @[RegisterRouter.scala:87:24] wire out_roready_1_1114; // @[RegisterRouter.scala:87:24] wire out_roready_1_1115; // @[RegisterRouter.scala:87:24] wire out_roready_1_1116; // @[RegisterRouter.scala:87:24] wire out_roready_1_1117; // @[RegisterRouter.scala:87:24] wire out_roready_1_1118; // @[RegisterRouter.scala:87:24] wire out_roready_1_1119; // @[RegisterRouter.scala:87:24] wire out_roready_1_1120; // @[RegisterRouter.scala:87:24] wire out_roready_1_1121; // @[RegisterRouter.scala:87:24] wire out_roready_1_1122; // @[RegisterRouter.scala:87:24] wire out_roready_1_1123; // @[RegisterRouter.scala:87:24] wire out_roready_1_1124; // @[RegisterRouter.scala:87:24] wire out_roready_1_1125; // @[RegisterRouter.scala:87:24] wire out_roready_1_1126; // @[RegisterRouter.scala:87:24] wire out_roready_1_1127; // @[RegisterRouter.scala:87:24] wire out_roready_1_1128; // @[RegisterRouter.scala:87:24] wire out_roready_1_1129; // @[RegisterRouter.scala:87:24] wire out_roready_1_1130; // @[RegisterRouter.scala:87:24] wire out_roready_1_1131; // @[RegisterRouter.scala:87:24] wire out_roready_1_1132; // @[RegisterRouter.scala:87:24] wire out_roready_1_1133; // @[RegisterRouter.scala:87:24] wire out_roready_1_1134; // @[RegisterRouter.scala:87:24] wire out_roready_1_1135; // @[RegisterRouter.scala:87:24] wire out_roready_1_1136; // @[RegisterRouter.scala:87:24] wire out_roready_1_1137; // @[RegisterRouter.scala:87:24] wire out_roready_1_1138; // @[RegisterRouter.scala:87:24] wire out_roready_1_1139; // @[RegisterRouter.scala:87:24] wire out_roready_1_1140; // @[RegisterRouter.scala:87:24] wire out_roready_1_1141; // @[RegisterRouter.scala:87:24] wire out_roready_1_1142; // @[RegisterRouter.scala:87:24] wire out_roready_1_1143; // @[RegisterRouter.scala:87:24] wire out_roready_1_1144; // @[RegisterRouter.scala:87:24] wire out_roready_1_1145; // @[RegisterRouter.scala:87:24] wire out_roready_1_1146; // @[RegisterRouter.scala:87:24] wire out_roready_1_1147; // @[RegisterRouter.scala:87:24] wire out_roready_1_1148; // @[RegisterRouter.scala:87:24] wire out_roready_1_1149; // @[RegisterRouter.scala:87:24] wire out_roready_1_1150; // @[RegisterRouter.scala:87:24] wire out_roready_1_1151; // @[RegisterRouter.scala:87:24] wire out_roready_1_1152; // @[RegisterRouter.scala:87:24] wire out_roready_1_1153; // @[RegisterRouter.scala:87:24] wire out_roready_1_1154; // @[RegisterRouter.scala:87:24] wire out_roready_1_1155; // @[RegisterRouter.scala:87:24] wire out_roready_1_1156; // @[RegisterRouter.scala:87:24] wire out_roready_1_1157; // @[RegisterRouter.scala:87:24] wire out_roready_1_1158; // @[RegisterRouter.scala:87:24] wire out_roready_1_1159; // @[RegisterRouter.scala:87:24] wire out_roready_1_1160; // @[RegisterRouter.scala:87:24] wire out_roready_1_1161; // @[RegisterRouter.scala:87:24] wire out_roready_1_1162; // @[RegisterRouter.scala:87:24] wire out_roready_1_1163; // @[RegisterRouter.scala:87:24] wire out_roready_1_1164; // @[RegisterRouter.scala:87:24] wire out_roready_1_1165; // @[RegisterRouter.scala:87:24] wire out_roready_1_1166; // @[RegisterRouter.scala:87:24] wire out_roready_1_1167; // @[RegisterRouter.scala:87:24] wire out_roready_1_1168; // @[RegisterRouter.scala:87:24] wire out_roready_1_1169; // @[RegisterRouter.scala:87:24] wire out_roready_1_1170; // @[RegisterRouter.scala:87:24] wire out_roready_1_1171; // @[RegisterRouter.scala:87:24] wire out_roready_1_1172; // @[RegisterRouter.scala:87:24] wire out_roready_1_1173; // @[RegisterRouter.scala:87:24] wire out_roready_1_1174; // @[RegisterRouter.scala:87:24] wire out_roready_1_1175; // @[RegisterRouter.scala:87:24] wire out_roready_1_1176; // @[RegisterRouter.scala:87:24] wire out_roready_1_1177; // @[RegisterRouter.scala:87:24] wire out_roready_1_1178; // @[RegisterRouter.scala:87:24] wire out_roready_1_1179; // @[RegisterRouter.scala:87:24] wire out_roready_1_1180; // @[RegisterRouter.scala:87:24] wire out_roready_1_1181; // @[RegisterRouter.scala:87:24] wire out_roready_1_1182; // @[RegisterRouter.scala:87:24] wire out_roready_1_1183; // @[RegisterRouter.scala:87:24] wire out_roready_1_1184; // @[RegisterRouter.scala:87:24] wire out_roready_1_1185; // @[RegisterRouter.scala:87:24] wire out_roready_1_1186; // @[RegisterRouter.scala:87:24] wire out_roready_1_1187; // @[RegisterRouter.scala:87:24] wire out_roready_1_1188; // @[RegisterRouter.scala:87:24] wire out_roready_1_1189; // @[RegisterRouter.scala:87:24] wire out_roready_1_1190; // @[RegisterRouter.scala:87:24] wire out_roready_1_1191; // @[RegisterRouter.scala:87:24] wire out_roready_1_1192; // @[RegisterRouter.scala:87:24] wire out_roready_1_1193; // @[RegisterRouter.scala:87:24] wire out_roready_1_1194; // @[RegisterRouter.scala:87:24] wire out_roready_1_1195; // @[RegisterRouter.scala:87:24] wire out_roready_1_1196; // @[RegisterRouter.scala:87:24] wire out_roready_1_1197; // @[RegisterRouter.scala:87:24] wire out_roready_1_1198; // @[RegisterRouter.scala:87:24] wire out_roready_1_1199; // @[RegisterRouter.scala:87:24] wire out_roready_1_1200; // @[RegisterRouter.scala:87:24] wire out_roready_1_1201; // @[RegisterRouter.scala:87:24] wire out_roready_1_1202; // @[RegisterRouter.scala:87:24] wire out_roready_1_1203; // @[RegisterRouter.scala:87:24] wire out_roready_1_1204; // @[RegisterRouter.scala:87:24] wire out_roready_1_1205; // @[RegisterRouter.scala:87:24] wire out_roready_1_1206; // @[RegisterRouter.scala:87:24] wire out_roready_1_1207; // @[RegisterRouter.scala:87:24] wire out_roready_1_1208; // @[RegisterRouter.scala:87:24] wire out_roready_1_1209; // @[RegisterRouter.scala:87:24] wire out_roready_1_1210; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_816; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1260; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1200; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_944; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_724; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1132; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1252; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1072; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_832; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_876; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_960; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1004; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_268; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1000; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_704; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1048; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_892; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1020; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_872; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1176; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_284; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1128; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_920; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_980; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_688; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1216; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1108; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1276; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_852; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1148; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_792; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_796; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1236; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_300; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1088; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1196; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1256; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1068; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1144; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_280; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_904; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1032; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_812; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_924; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_396; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1180; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1272; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1052; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1160; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_888; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1016; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_940; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_828; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1164; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1036; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1112; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_648; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_700; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_264; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_956; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_780; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_800; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_304; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1084; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_776; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1212; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_684; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1240; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_928; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_392; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_856; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_296; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_908; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_984; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_860; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_968; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1028; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1080; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_276; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_840; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1208; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_988; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_900; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1012; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_952; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_716; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1140; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1184; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1244; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1096; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_676; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_824; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1116; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_884; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1056; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_696; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1224; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1268; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_784; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1156; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_804; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1168; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1228; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_932; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_912; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1284; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1100; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_712; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1040; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_844; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_864; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_292; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1060; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_972; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_992; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_880; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_964; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_836; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1076; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1136; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_680; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1264; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1188; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_272; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_896; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1008; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_720; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_948; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_820; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1092; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1120; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1204; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1248; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_868; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_848; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1024; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_996; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_936; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_288; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1104; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_692; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_808; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1044; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1220; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1232; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_788; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_976; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_916; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1064; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_708; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1124; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1152; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1192; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1280; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1172; // @[RegisterRouter.scala:87:24] wire out_woready_1_0; // @[RegisterRouter.scala:87:24] wire out_woready_1_1; // @[RegisterRouter.scala:87:24] wire out_woready_1_2; // @[RegisterRouter.scala:87:24] wire out_woready_1_3; // @[RegisterRouter.scala:87:24] wire out_woready_1_4; // @[RegisterRouter.scala:87:24] wire out_woready_1_5; // @[RegisterRouter.scala:87:24] wire out_woready_1_6; // @[RegisterRouter.scala:87:24] wire out_woready_1_7; // @[RegisterRouter.scala:87:24] wire out_woready_1_8; // @[RegisterRouter.scala:87:24] wire out_woready_1_9; // @[RegisterRouter.scala:87:24] wire out_woready_1_10; // @[RegisterRouter.scala:87:24] wire out_woready_1_11; // @[RegisterRouter.scala:87:24] wire out_woready_1_12; // @[RegisterRouter.scala:87:24] wire out_woready_1_13; // @[RegisterRouter.scala:87:24] wire out_woready_1_14; // @[RegisterRouter.scala:87:24] wire out_woready_1_15; // @[RegisterRouter.scala:87:24] wire out_woready_1_16; // @[RegisterRouter.scala:87:24] wire out_woready_1_17; // @[RegisterRouter.scala:87:24] wire out_woready_1_18; // @[RegisterRouter.scala:87:24] wire out_woready_1_19; // @[RegisterRouter.scala:87:24] wire out_woready_1_20; // @[RegisterRouter.scala:87:24] wire out_woready_1_21; // @[RegisterRouter.scala:87:24] wire out_woready_1_22; // @[RegisterRouter.scala:87:24] wire out_woready_1_23; // @[RegisterRouter.scala:87:24] wire out_woready_1_24; // @[RegisterRouter.scala:87:24] wire out_woready_1_25; // @[RegisterRouter.scala:87:24] wire out_woready_1_26; // @[RegisterRouter.scala:87:24] wire out_woready_1_27; // @[RegisterRouter.scala:87:24] wire out_woready_1_28; // @[RegisterRouter.scala:87:24] wire out_woready_1_29; // @[RegisterRouter.scala:87:24] wire out_woready_1_30; // @[RegisterRouter.scala:87:24] wire out_woready_1_31; // @[RegisterRouter.scala:87:24] wire out_woready_1_32; // @[RegisterRouter.scala:87:24] wire out_woready_1_33; // @[RegisterRouter.scala:87:24] wire out_woready_1_34; // @[RegisterRouter.scala:87:24] wire out_woready_1_35; // @[RegisterRouter.scala:87:24] wire out_woready_1_36; // @[RegisterRouter.scala:87:24] wire out_woready_1_37; // @[RegisterRouter.scala:87:24] wire out_woready_1_38; // @[RegisterRouter.scala:87:24] wire out_woready_1_39; // @[RegisterRouter.scala:87:24] wire out_woready_1_40; // @[RegisterRouter.scala:87:24] wire out_woready_1_41; // @[RegisterRouter.scala:87:24] wire out_woready_1_42; // @[RegisterRouter.scala:87:24] wire out_woready_1_43; // @[RegisterRouter.scala:87:24] wire out_woready_1_44; // @[RegisterRouter.scala:87:24] wire out_woready_1_45; // @[RegisterRouter.scala:87:24] wire out_woready_1_46; // @[RegisterRouter.scala:87:24] wire out_woready_1_47; // @[RegisterRouter.scala:87:24] wire out_woready_1_48; // @[RegisterRouter.scala:87:24] wire out_woready_1_49; // @[RegisterRouter.scala:87:24] wire out_woready_1_50; // @[RegisterRouter.scala:87:24] wire out_woready_1_51; // @[RegisterRouter.scala:87:24] wire out_woready_1_52; // @[RegisterRouter.scala:87:24] wire out_woready_1_53; // @[RegisterRouter.scala:87:24] wire out_woready_1_54; // @[RegisterRouter.scala:87:24] wire out_woready_1_55; // @[RegisterRouter.scala:87:24] wire out_woready_1_56; // @[RegisterRouter.scala:87:24] wire out_woready_1_57; // @[RegisterRouter.scala:87:24] wire out_woready_1_58; // @[RegisterRouter.scala:87:24] wire out_woready_1_59; // @[RegisterRouter.scala:87:24] wire out_woready_1_60; // @[RegisterRouter.scala:87:24] wire out_woready_1_61; // @[RegisterRouter.scala:87:24] wire out_woready_1_62; // @[RegisterRouter.scala:87:24] wire out_woready_1_63; // @[RegisterRouter.scala:87:24] wire out_woready_1_64; // @[RegisterRouter.scala:87:24] wire out_woready_1_65; // @[RegisterRouter.scala:87:24] wire out_woready_1_66; // @[RegisterRouter.scala:87:24] wire out_woready_1_67; // @[RegisterRouter.scala:87:24] wire out_woready_1_68; // @[RegisterRouter.scala:87:24] wire out_woready_1_69; // @[RegisterRouter.scala:87:24] wire out_woready_1_70; // @[RegisterRouter.scala:87:24] wire out_woready_1_71; // @[RegisterRouter.scala:87:24] wire out_woready_1_72; // @[RegisterRouter.scala:87:24] wire out_woready_1_73; // @[RegisterRouter.scala:87:24] wire out_woready_1_74; // @[RegisterRouter.scala:87:24] wire out_woready_1_75; // @[RegisterRouter.scala:87:24] wire out_woready_1_76; // @[RegisterRouter.scala:87:24] wire out_woready_1_77; // @[RegisterRouter.scala:87:24] wire out_woready_1_78; // @[RegisterRouter.scala:87:24] wire out_woready_1_79; // @[RegisterRouter.scala:87:24] wire out_woready_1_80; // @[RegisterRouter.scala:87:24] wire out_woready_1_81; // @[RegisterRouter.scala:87:24] wire out_woready_1_82; // @[RegisterRouter.scala:87:24] wire out_woready_1_83; // @[RegisterRouter.scala:87:24] wire out_woready_1_84; // @[RegisterRouter.scala:87:24] wire out_woready_1_85; // @[RegisterRouter.scala:87:24] wire out_woready_1_86; // @[RegisterRouter.scala:87:24] wire out_woready_1_87; // @[RegisterRouter.scala:87:24] wire out_woready_1_88; // @[RegisterRouter.scala:87:24] wire out_woready_1_89; // @[RegisterRouter.scala:87:24] wire out_woready_1_90; // @[RegisterRouter.scala:87:24] wire out_woready_1_91; // @[RegisterRouter.scala:87:24] wire out_woready_1_92; // @[RegisterRouter.scala:87:24] wire out_woready_1_93; // @[RegisterRouter.scala:87:24] wire out_woready_1_94; // @[RegisterRouter.scala:87:24] wire out_woready_1_95; // @[RegisterRouter.scala:87:24] wire out_woready_1_96; // @[RegisterRouter.scala:87:24] wire out_woready_1_97; // @[RegisterRouter.scala:87:24] wire out_woready_1_98; // @[RegisterRouter.scala:87:24] wire out_woready_1_99; // @[RegisterRouter.scala:87:24] wire out_woready_1_100; // @[RegisterRouter.scala:87:24] wire out_woready_1_101; // @[RegisterRouter.scala:87:24] wire out_woready_1_102; // @[RegisterRouter.scala:87:24] wire out_woready_1_103; // @[RegisterRouter.scala:87:24] wire out_woready_1_104; // @[RegisterRouter.scala:87:24] wire out_woready_1_105; // @[RegisterRouter.scala:87:24] wire out_woready_1_106; // @[RegisterRouter.scala:87:24] wire out_woready_1_107; // @[RegisterRouter.scala:87:24] wire out_woready_1_108; // @[RegisterRouter.scala:87:24] wire out_woready_1_109; // @[RegisterRouter.scala:87:24] wire out_woready_1_110; // @[RegisterRouter.scala:87:24] wire out_woready_1_111; // @[RegisterRouter.scala:87:24] wire out_woready_1_112; // @[RegisterRouter.scala:87:24] wire out_woready_1_113; // @[RegisterRouter.scala:87:24] wire out_woready_1_114; // @[RegisterRouter.scala:87:24] wire out_woready_1_115; // @[RegisterRouter.scala:87:24] wire out_woready_1_116; // @[RegisterRouter.scala:87:24] wire out_woready_1_117; // @[RegisterRouter.scala:87:24] wire out_woready_1_118; // @[RegisterRouter.scala:87:24] wire out_woready_1_119; // @[RegisterRouter.scala:87:24] wire out_woready_1_120; // @[RegisterRouter.scala:87:24] wire out_woready_1_121; // @[RegisterRouter.scala:87:24] wire out_woready_1_122; // @[RegisterRouter.scala:87:24] wire out_woready_1_123; // @[RegisterRouter.scala:87:24] wire out_woready_1_124; // @[RegisterRouter.scala:87:24] wire out_woready_1_125; // @[RegisterRouter.scala:87:24] wire out_woready_1_126; // @[RegisterRouter.scala:87:24] wire out_woready_1_127; // @[RegisterRouter.scala:87:24] wire out_woready_1_128; // @[RegisterRouter.scala:87:24] wire out_woready_1_129; // @[RegisterRouter.scala:87:24] wire out_woready_1_130; // @[RegisterRouter.scala:87:24] wire out_woready_1_131; // @[RegisterRouter.scala:87:24] wire out_woready_1_132; // @[RegisterRouter.scala:87:24] wire out_woready_1_133; // @[RegisterRouter.scala:87:24] wire out_woready_1_134; // @[RegisterRouter.scala:87:24] wire out_woready_1_135; // @[RegisterRouter.scala:87:24] wire out_woready_1_136; // @[RegisterRouter.scala:87:24] wire out_woready_1_137; // @[RegisterRouter.scala:87:24] wire out_woready_1_138; // @[RegisterRouter.scala:87:24] wire out_woready_1_139; // @[RegisterRouter.scala:87:24] wire out_woready_1_140; // @[RegisterRouter.scala:87:24] wire out_woready_1_141; // @[RegisterRouter.scala:87:24] wire out_woready_1_142; // @[RegisterRouter.scala:87:24] wire out_woready_1_143; // @[RegisterRouter.scala:87:24] wire out_woready_1_144; // @[RegisterRouter.scala:87:24] wire out_woready_1_145; // @[RegisterRouter.scala:87:24] wire out_woready_1_146; // @[RegisterRouter.scala:87:24] wire out_woready_1_147; // @[RegisterRouter.scala:87:24] wire out_woready_1_148; // @[RegisterRouter.scala:87:24] wire out_woready_1_149; // @[RegisterRouter.scala:87:24] wire out_woready_1_150; // @[RegisterRouter.scala:87:24] wire out_woready_1_151; // @[RegisterRouter.scala:87:24] wire out_woready_1_152; // @[RegisterRouter.scala:87:24] wire out_woready_1_153; // @[RegisterRouter.scala:87:24] wire out_woready_1_154; // @[RegisterRouter.scala:87:24] wire out_woready_1_155; // @[RegisterRouter.scala:87:24] wire out_woready_1_156; // @[RegisterRouter.scala:87:24] wire out_woready_1_157; // @[RegisterRouter.scala:87:24] wire out_woready_1_158; // @[RegisterRouter.scala:87:24] wire out_woready_1_159; // @[RegisterRouter.scala:87:24] wire out_woready_1_160; // @[RegisterRouter.scala:87:24] wire out_woready_1_161; // @[RegisterRouter.scala:87:24] wire out_woready_1_162; // @[RegisterRouter.scala:87:24] wire out_woready_1_163; // @[RegisterRouter.scala:87:24] wire out_woready_1_164; // @[RegisterRouter.scala:87:24] wire out_woready_1_165; // @[RegisterRouter.scala:87:24] wire out_woready_1_166; // @[RegisterRouter.scala:87:24] wire out_woready_1_167; // @[RegisterRouter.scala:87:24] wire out_woready_1_168; // @[RegisterRouter.scala:87:24] wire out_woready_1_169; // @[RegisterRouter.scala:87:24] wire out_woready_1_170; // @[RegisterRouter.scala:87:24] wire out_woready_1_171; // @[RegisterRouter.scala:87:24] wire out_woready_1_172; // @[RegisterRouter.scala:87:24] wire out_woready_1_173; // @[RegisterRouter.scala:87:24] wire out_woready_1_174; // @[RegisterRouter.scala:87:24] wire out_woready_1_175; // @[RegisterRouter.scala:87:24] wire out_woready_1_176; // @[RegisterRouter.scala:87:24] wire out_woready_1_177; // @[RegisterRouter.scala:87:24] wire out_woready_1_178; // @[RegisterRouter.scala:87:24] wire out_woready_1_179; // @[RegisterRouter.scala:87:24] wire out_woready_1_180; // @[RegisterRouter.scala:87:24] wire out_woready_1_181; // @[RegisterRouter.scala:87:24] wire out_woready_1_182; // @[RegisterRouter.scala:87:24] wire out_woready_1_183; // @[RegisterRouter.scala:87:24] wire out_woready_1_184; // @[RegisterRouter.scala:87:24] wire out_woready_1_185; // @[RegisterRouter.scala:87:24] wire out_woready_1_186; // @[RegisterRouter.scala:87:24] wire out_woready_1_187; // @[RegisterRouter.scala:87:24] wire out_woready_1_188; // @[RegisterRouter.scala:87:24] wire out_woready_1_189; // @[RegisterRouter.scala:87:24] wire out_woready_1_190; // @[RegisterRouter.scala:87:24] wire out_woready_1_191; // @[RegisterRouter.scala:87:24] wire out_woready_1_192; // @[RegisterRouter.scala:87:24] wire out_woready_1_193; // @[RegisterRouter.scala:87:24] wire out_woready_1_194; // @[RegisterRouter.scala:87:24] wire out_woready_1_195; // @[RegisterRouter.scala:87:24] wire out_woready_1_196; // @[RegisterRouter.scala:87:24] wire out_woready_1_197; // @[RegisterRouter.scala:87:24] wire out_woready_1_198; // @[RegisterRouter.scala:87:24] wire out_woready_1_199; // @[RegisterRouter.scala:87:24] wire out_woready_1_200; // @[RegisterRouter.scala:87:24] wire out_woready_1_201; // @[RegisterRouter.scala:87:24] wire out_woready_1_202; // @[RegisterRouter.scala:87:24] wire out_woready_1_203; // @[RegisterRouter.scala:87:24] wire out_woready_1_204; // @[RegisterRouter.scala:87:24] wire out_woready_1_205; // @[RegisterRouter.scala:87:24] wire out_woready_1_206; // @[RegisterRouter.scala:87:24] wire out_woready_1_207; // @[RegisterRouter.scala:87:24] wire out_woready_1_208; // @[RegisterRouter.scala:87:24] wire out_woready_1_209; // @[RegisterRouter.scala:87:24] wire out_woready_1_210; // @[RegisterRouter.scala:87:24] wire out_woready_1_211; // @[RegisterRouter.scala:87:24] wire out_woready_1_212; // @[RegisterRouter.scala:87:24] wire out_woready_1_213; // @[RegisterRouter.scala:87:24] wire out_woready_1_214; // @[RegisterRouter.scala:87:24] wire out_woready_1_215; // @[RegisterRouter.scala:87:24] wire out_woready_1_216; // @[RegisterRouter.scala:87:24] wire out_woready_1_217; // @[RegisterRouter.scala:87:24] wire out_woready_1_218; // @[RegisterRouter.scala:87:24] wire out_woready_1_219; // @[RegisterRouter.scala:87:24] wire out_woready_1_220; // @[RegisterRouter.scala:87:24] wire out_woready_1_221; // @[RegisterRouter.scala:87:24] wire out_woready_1_222; // @[RegisterRouter.scala:87:24] wire out_woready_1_223; // @[RegisterRouter.scala:87:24] wire out_woready_1_224; // @[RegisterRouter.scala:87:24] wire out_woready_1_225; // @[RegisterRouter.scala:87:24] wire out_woready_1_226; // @[RegisterRouter.scala:87:24] wire out_woready_1_227; // @[RegisterRouter.scala:87:24] wire out_woready_1_228; // @[RegisterRouter.scala:87:24] wire out_woready_1_229; // @[RegisterRouter.scala:87:24] wire out_woready_1_230; // @[RegisterRouter.scala:87:24] wire out_woready_1_231; // @[RegisterRouter.scala:87:24] wire out_woready_1_232; // @[RegisterRouter.scala:87:24] wire out_woready_1_233; // @[RegisterRouter.scala:87:24] wire out_woready_1_234; // @[RegisterRouter.scala:87:24] wire out_woready_1_235; // @[RegisterRouter.scala:87:24] wire out_woready_1_236; // @[RegisterRouter.scala:87:24] wire out_woready_1_237; // @[RegisterRouter.scala:87:24] wire out_woready_1_238; // @[RegisterRouter.scala:87:24] wire out_woready_1_239; // @[RegisterRouter.scala:87:24] wire out_woready_1_240; // @[RegisterRouter.scala:87:24] wire out_woready_1_241; // @[RegisterRouter.scala:87:24] wire out_woready_1_242; // @[RegisterRouter.scala:87:24] wire out_woready_1_243; // @[RegisterRouter.scala:87:24] wire out_woready_1_244; // @[RegisterRouter.scala:87:24] wire out_woready_1_245; // @[RegisterRouter.scala:87:24] wire out_woready_1_246; // @[RegisterRouter.scala:87:24] wire out_woready_1_247; // @[RegisterRouter.scala:87:24] wire out_woready_1_248; // @[RegisterRouter.scala:87:24] wire out_woready_1_249; // @[RegisterRouter.scala:87:24] wire out_woready_1_250; // @[RegisterRouter.scala:87:24] wire out_woready_1_251; // @[RegisterRouter.scala:87:24] wire out_woready_1_252; // @[RegisterRouter.scala:87:24] wire out_woready_1_253; // @[RegisterRouter.scala:87:24] wire out_woready_1_254; // @[RegisterRouter.scala:87:24] wire out_woready_1_255; // @[RegisterRouter.scala:87:24] wire out_woready_1_256; // @[RegisterRouter.scala:87:24] wire out_woready_1_257; // @[RegisterRouter.scala:87:24] wire out_woready_1_258; // @[RegisterRouter.scala:87:24] wire out_woready_1_259; // @[RegisterRouter.scala:87:24] wire out_woready_1_260; // @[RegisterRouter.scala:87:24] wire out_woready_1_261; // @[RegisterRouter.scala:87:24] wire out_woready_1_262; // @[RegisterRouter.scala:87:24] wire out_woready_1_263; // @[RegisterRouter.scala:87:24] wire out_woready_1_264; // @[RegisterRouter.scala:87:24] wire out_woready_1_265; // @[RegisterRouter.scala:87:24] wire out_woready_1_266; // @[RegisterRouter.scala:87:24] wire out_woready_1_267; // @[RegisterRouter.scala:87:24] wire out_woready_1_268; // @[RegisterRouter.scala:87:24] wire out_woready_1_269; // @[RegisterRouter.scala:87:24] wire out_woready_1_270; // @[RegisterRouter.scala:87:24] wire out_woready_1_271; // @[RegisterRouter.scala:87:24] wire out_woready_1_272; // @[RegisterRouter.scala:87:24] wire out_woready_1_273; // @[RegisterRouter.scala:87:24] wire out_woready_1_274; // @[RegisterRouter.scala:87:24] wire out_woready_1_275; // @[RegisterRouter.scala:87:24] wire out_woready_1_276; // @[RegisterRouter.scala:87:24] wire out_woready_1_277; // @[RegisterRouter.scala:87:24] wire out_woready_1_278; // @[RegisterRouter.scala:87:24] wire out_woready_1_279; // @[RegisterRouter.scala:87:24] wire out_woready_1_280; // @[RegisterRouter.scala:87:24] wire out_woready_1_281; // @[RegisterRouter.scala:87:24] wire out_woready_1_282; // @[RegisterRouter.scala:87:24] wire out_woready_1_283; // @[RegisterRouter.scala:87:24] wire out_woready_1_284; // @[RegisterRouter.scala:87:24] wire out_woready_1_285; // @[RegisterRouter.scala:87:24] wire out_woready_1_286; // @[RegisterRouter.scala:87:24] wire out_woready_1_287; // @[RegisterRouter.scala:87:24] wire out_woready_1_288; // @[RegisterRouter.scala:87:24] wire out_woready_1_289; // @[RegisterRouter.scala:87:24] wire out_woready_1_290; // @[RegisterRouter.scala:87:24] wire out_woready_1_291; // @[RegisterRouter.scala:87:24] wire out_woready_1_292; // @[RegisterRouter.scala:87:24] wire out_woready_1_293; // @[RegisterRouter.scala:87:24] wire out_woready_1_294; // @[RegisterRouter.scala:87:24] wire out_woready_1_295; // @[RegisterRouter.scala:87:24] wire out_woready_1_296; // @[RegisterRouter.scala:87:24] wire out_woready_1_297; // @[RegisterRouter.scala:87:24] wire out_woready_1_298; // @[RegisterRouter.scala:87:24] wire out_woready_1_299; // @[RegisterRouter.scala:87:24] wire out_woready_1_300; // @[RegisterRouter.scala:87:24] wire out_woready_1_301; // @[RegisterRouter.scala:87:24] wire out_woready_1_302; // @[RegisterRouter.scala:87:24] wire out_woready_1_303; // @[RegisterRouter.scala:87:24] wire out_woready_1_304; // @[RegisterRouter.scala:87:24] wire out_woready_1_305; // @[RegisterRouter.scala:87:24] wire out_woready_1_306; // @[RegisterRouter.scala:87:24] wire out_woready_1_307; // @[RegisterRouter.scala:87:24] wire out_woready_1_308; // @[RegisterRouter.scala:87:24] wire out_woready_1_309; // @[RegisterRouter.scala:87:24] wire out_woready_1_310; // @[RegisterRouter.scala:87:24] wire out_woready_1_311; // @[RegisterRouter.scala:87:24] wire out_woready_1_312; // @[RegisterRouter.scala:87:24] wire out_woready_1_313; // @[RegisterRouter.scala:87:24] wire out_woready_1_314; // @[RegisterRouter.scala:87:24] wire out_woready_1_315; // @[RegisterRouter.scala:87:24] wire out_woready_1_316; // @[RegisterRouter.scala:87:24] wire out_woready_1_317; // @[RegisterRouter.scala:87:24] wire out_woready_1_318; // @[RegisterRouter.scala:87:24] wire out_woready_1_319; // @[RegisterRouter.scala:87:24] wire out_woready_1_320; // @[RegisterRouter.scala:87:24] wire out_woready_1_321; // @[RegisterRouter.scala:87:24] wire out_woready_1_322; // @[RegisterRouter.scala:87:24] wire out_woready_1_323; // @[RegisterRouter.scala:87:24] wire out_woready_1_324; // @[RegisterRouter.scala:87:24] wire out_woready_1_325; // @[RegisterRouter.scala:87:24] wire out_woready_1_326; // @[RegisterRouter.scala:87:24] wire out_woready_1_327; // @[RegisterRouter.scala:87:24] wire out_woready_1_328; // @[RegisterRouter.scala:87:24] wire out_woready_1_329; // @[RegisterRouter.scala:87:24] wire out_woready_1_330; // @[RegisterRouter.scala:87:24] wire out_woready_1_331; // @[RegisterRouter.scala:87:24] wire out_woready_1_332; // @[RegisterRouter.scala:87:24] wire out_woready_1_333; // @[RegisterRouter.scala:87:24] wire out_woready_1_334; // @[RegisterRouter.scala:87:24] wire out_woready_1_335; // @[RegisterRouter.scala:87:24] wire out_woready_1_336; // @[RegisterRouter.scala:87:24] wire out_woready_1_337; // @[RegisterRouter.scala:87:24] wire out_woready_1_338; // @[RegisterRouter.scala:87:24] wire out_woready_1_339; // @[RegisterRouter.scala:87:24] wire out_woready_1_340; // @[RegisterRouter.scala:87:24] wire out_woready_1_341; // @[RegisterRouter.scala:87:24] wire out_woready_1_342; // @[RegisterRouter.scala:87:24] wire out_woready_1_343; // @[RegisterRouter.scala:87:24] wire out_woready_1_344; // @[RegisterRouter.scala:87:24] wire out_woready_1_345; // @[RegisterRouter.scala:87:24] wire out_woready_1_346; // @[RegisterRouter.scala:87:24] wire out_woready_1_347; // @[RegisterRouter.scala:87:24] wire out_woready_1_348; // @[RegisterRouter.scala:87:24] wire out_woready_1_349; // @[RegisterRouter.scala:87:24] wire out_woready_1_350; // @[RegisterRouter.scala:87:24] wire out_woready_1_351; // @[RegisterRouter.scala:87:24] wire out_woready_1_352; // @[RegisterRouter.scala:87:24] wire out_woready_1_353; // @[RegisterRouter.scala:87:24] wire out_woready_1_354; // @[RegisterRouter.scala:87:24] wire out_woready_1_355; // @[RegisterRouter.scala:87:24] wire out_woready_1_356; // @[RegisterRouter.scala:87:24] wire out_woready_1_357; // @[RegisterRouter.scala:87:24] wire out_woready_1_358; // @[RegisterRouter.scala:87:24] wire out_woready_1_359; // @[RegisterRouter.scala:87:24] wire out_woready_1_360; // @[RegisterRouter.scala:87:24] wire out_woready_1_361; // @[RegisterRouter.scala:87:24] wire out_woready_1_362; // @[RegisterRouter.scala:87:24] wire out_woready_1_363; // @[RegisterRouter.scala:87:24] wire out_woready_1_364; // @[RegisterRouter.scala:87:24] wire out_woready_1_365; // @[RegisterRouter.scala:87:24] wire out_woready_1_366; // @[RegisterRouter.scala:87:24] wire out_woready_1_367; // @[RegisterRouter.scala:87:24] wire out_woready_1_368; // @[RegisterRouter.scala:87:24] wire out_woready_1_369; // @[RegisterRouter.scala:87:24] wire out_woready_1_370; // @[RegisterRouter.scala:87:24] wire out_woready_1_371; // @[RegisterRouter.scala:87:24] wire out_woready_1_372; // @[RegisterRouter.scala:87:24] wire out_woready_1_373; // @[RegisterRouter.scala:87:24] wire out_woready_1_374; // @[RegisterRouter.scala:87:24] wire out_woready_1_375; // @[RegisterRouter.scala:87:24] wire out_woready_1_376; // @[RegisterRouter.scala:87:24] wire out_woready_1_377; // @[RegisterRouter.scala:87:24] wire out_woready_1_378; // @[RegisterRouter.scala:87:24] wire out_woready_1_379; // @[RegisterRouter.scala:87:24] wire out_woready_1_380; // @[RegisterRouter.scala:87:24] wire out_woready_1_381; // @[RegisterRouter.scala:87:24] wire out_woready_1_382; // @[RegisterRouter.scala:87:24] wire out_woready_1_383; // @[RegisterRouter.scala:87:24] wire out_woready_1_384; // @[RegisterRouter.scala:87:24] wire out_woready_1_385; // @[RegisterRouter.scala:87:24] wire out_woready_1_386; // @[RegisterRouter.scala:87:24] wire out_woready_1_387; // @[RegisterRouter.scala:87:24] wire out_woready_1_388; // @[RegisterRouter.scala:87:24] wire out_woready_1_389; // @[RegisterRouter.scala:87:24] wire out_woready_1_390; // @[RegisterRouter.scala:87:24] wire out_woready_1_391; // @[RegisterRouter.scala:87:24] wire out_woready_1_392; // @[RegisterRouter.scala:87:24] wire out_woready_1_393; // @[RegisterRouter.scala:87:24] wire out_woready_1_394; // @[RegisterRouter.scala:87:24] wire out_woready_1_395; // @[RegisterRouter.scala:87:24] wire out_woready_1_396; // @[RegisterRouter.scala:87:24] wire out_woready_1_397; // @[RegisterRouter.scala:87:24] wire out_woready_1_398; // @[RegisterRouter.scala:87:24] wire out_woready_1_399; // @[RegisterRouter.scala:87:24] wire out_woready_1_400; // @[RegisterRouter.scala:87:24] wire out_woready_1_401; // @[RegisterRouter.scala:87:24] wire out_woready_1_402; // @[RegisterRouter.scala:87:24] wire out_woready_1_403; // @[RegisterRouter.scala:87:24] wire out_woready_1_404; // @[RegisterRouter.scala:87:24] wire out_woready_1_405; // @[RegisterRouter.scala:87:24] wire out_woready_1_406; // @[RegisterRouter.scala:87:24] wire out_woready_1_407; // @[RegisterRouter.scala:87:24] wire out_woready_1_408; // @[RegisterRouter.scala:87:24] wire out_woready_1_409; // @[RegisterRouter.scala:87:24] wire out_woready_1_410; // @[RegisterRouter.scala:87:24] wire out_woready_1_411; // @[RegisterRouter.scala:87:24] wire out_woready_1_412; // @[RegisterRouter.scala:87:24] wire out_woready_1_413; // @[RegisterRouter.scala:87:24] wire out_woready_1_414; // @[RegisterRouter.scala:87:24] wire out_woready_1_415; // @[RegisterRouter.scala:87:24] wire out_woready_1_416; // @[RegisterRouter.scala:87:24] wire out_woready_1_417; // @[RegisterRouter.scala:87:24] wire out_woready_1_418; // @[RegisterRouter.scala:87:24] wire out_woready_1_419; // @[RegisterRouter.scala:87:24] wire out_woready_1_420; // @[RegisterRouter.scala:87:24] wire out_woready_1_421; // @[RegisterRouter.scala:87:24] wire out_woready_1_422; // @[RegisterRouter.scala:87:24] wire out_woready_1_423; // @[RegisterRouter.scala:87:24] wire out_woready_1_424; // @[RegisterRouter.scala:87:24] wire out_woready_1_425; // @[RegisterRouter.scala:87:24] wire out_woready_1_426; // @[RegisterRouter.scala:87:24] wire out_woready_1_427; // @[RegisterRouter.scala:87:24] wire out_woready_1_428; // @[RegisterRouter.scala:87:24] wire out_woready_1_429; // @[RegisterRouter.scala:87:24] wire out_woready_1_430; // @[RegisterRouter.scala:87:24] wire out_woready_1_431; // @[RegisterRouter.scala:87:24] wire out_woready_1_432; // @[RegisterRouter.scala:87:24] wire out_woready_1_433; // @[RegisterRouter.scala:87:24] wire out_woready_1_434; // @[RegisterRouter.scala:87:24] wire out_woready_1_435; // @[RegisterRouter.scala:87:24] wire out_woready_1_436; // @[RegisterRouter.scala:87:24] wire out_woready_1_437; // @[RegisterRouter.scala:87:24] wire out_woready_1_438; // @[RegisterRouter.scala:87:24] wire out_woready_1_439; // @[RegisterRouter.scala:87:24] wire out_woready_1_440; // @[RegisterRouter.scala:87:24] wire out_woready_1_441; // @[RegisterRouter.scala:87:24] wire out_woready_1_442; // @[RegisterRouter.scala:87:24] wire out_woready_1_443; // @[RegisterRouter.scala:87:24] wire out_woready_1_444; // @[RegisterRouter.scala:87:24] wire out_woready_1_445; // @[RegisterRouter.scala:87:24] wire out_woready_1_446; // @[RegisterRouter.scala:87:24] wire out_woready_1_447; // @[RegisterRouter.scala:87:24] wire out_woready_1_448; // @[RegisterRouter.scala:87:24] wire out_woready_1_449; // @[RegisterRouter.scala:87:24] wire out_woready_1_450; // @[RegisterRouter.scala:87:24] wire out_woready_1_451; // @[RegisterRouter.scala:87:24] wire out_woready_1_452; // @[RegisterRouter.scala:87:24] wire out_woready_1_453; // @[RegisterRouter.scala:87:24] wire out_woready_1_454; // @[RegisterRouter.scala:87:24] wire out_woready_1_455; // @[RegisterRouter.scala:87:24] wire out_woready_1_456; // @[RegisterRouter.scala:87:24] wire out_woready_1_457; // @[RegisterRouter.scala:87:24] wire out_woready_1_458; // @[RegisterRouter.scala:87:24] wire out_woready_1_459; // @[RegisterRouter.scala:87:24] wire out_woready_1_460; // @[RegisterRouter.scala:87:24] wire out_woready_1_461; // @[RegisterRouter.scala:87:24] wire out_woready_1_462; // @[RegisterRouter.scala:87:24] wire out_woready_1_463; // @[RegisterRouter.scala:87:24] wire out_woready_1_464; // @[RegisterRouter.scala:87:24] wire out_woready_1_465; // @[RegisterRouter.scala:87:24] wire out_woready_1_466; // @[RegisterRouter.scala:87:24] wire out_woready_1_467; // @[RegisterRouter.scala:87:24] wire out_woready_1_468; // @[RegisterRouter.scala:87:24] wire out_woready_1_469; // @[RegisterRouter.scala:87:24] wire out_woready_1_470; // @[RegisterRouter.scala:87:24] wire out_woready_1_471; // @[RegisterRouter.scala:87:24] wire out_woready_1_472; // @[RegisterRouter.scala:87:24] wire out_woready_1_473; // @[RegisterRouter.scala:87:24] wire out_woready_1_474; // @[RegisterRouter.scala:87:24] wire out_woready_1_475; // @[RegisterRouter.scala:87:24] wire out_woready_1_476; // @[RegisterRouter.scala:87:24] wire out_woready_1_477; // @[RegisterRouter.scala:87:24] wire out_woready_1_478; // @[RegisterRouter.scala:87:24] wire out_woready_1_479; // @[RegisterRouter.scala:87:24] wire out_woready_1_480; // @[RegisterRouter.scala:87:24] wire out_woready_1_481; // @[RegisterRouter.scala:87:24] wire out_woready_1_482; // @[RegisterRouter.scala:87:24] wire out_woready_1_483; // @[RegisterRouter.scala:87:24] wire out_woready_1_484; // @[RegisterRouter.scala:87:24] wire out_woready_1_485; // @[RegisterRouter.scala:87:24] wire out_woready_1_486; // @[RegisterRouter.scala:87:24] wire out_woready_1_487; // @[RegisterRouter.scala:87:24] wire out_woready_1_488; // @[RegisterRouter.scala:87:24] wire out_woready_1_489; // @[RegisterRouter.scala:87:24] wire out_woready_1_490; // @[RegisterRouter.scala:87:24] wire out_woready_1_491; // @[RegisterRouter.scala:87:24] wire out_woready_1_492; // @[RegisterRouter.scala:87:24] wire out_woready_1_493; // @[RegisterRouter.scala:87:24] wire out_woready_1_494; // @[RegisterRouter.scala:87:24] wire out_woready_1_495; // @[RegisterRouter.scala:87:24] wire out_woready_1_496; // @[RegisterRouter.scala:87:24] wire out_woready_1_497; // @[RegisterRouter.scala:87:24] wire out_woready_1_498; // @[RegisterRouter.scala:87:24] wire out_woready_1_499; // @[RegisterRouter.scala:87:24] wire out_woready_1_500; // @[RegisterRouter.scala:87:24] wire out_woready_1_501; // @[RegisterRouter.scala:87:24] wire out_woready_1_502; // @[RegisterRouter.scala:87:24] wire out_woready_1_503; // @[RegisterRouter.scala:87:24] wire out_woready_1_504; // @[RegisterRouter.scala:87:24] wire out_woready_1_505; // @[RegisterRouter.scala:87:24] wire out_woready_1_506; // @[RegisterRouter.scala:87:24] wire out_woready_1_507; // @[RegisterRouter.scala:87:24] wire out_woready_1_508; // @[RegisterRouter.scala:87:24] wire out_woready_1_509; // @[RegisterRouter.scala:87:24] wire out_woready_1_510; // @[RegisterRouter.scala:87:24] wire out_woready_1_511; // @[RegisterRouter.scala:87:24] wire out_woready_1_512; // @[RegisterRouter.scala:87:24] wire out_woready_1_513; // @[RegisterRouter.scala:87:24] wire out_woready_1_514; // @[RegisterRouter.scala:87:24] wire out_woready_1_515; // @[RegisterRouter.scala:87:24] wire out_woready_1_516; // @[RegisterRouter.scala:87:24] wire out_woready_1_517; // @[RegisterRouter.scala:87:24] wire out_woready_1_518; // @[RegisterRouter.scala:87:24] wire out_woready_1_519; // @[RegisterRouter.scala:87:24] wire out_woready_1_520; // @[RegisterRouter.scala:87:24] wire out_woready_1_521; // @[RegisterRouter.scala:87:24] wire out_woready_1_522; // @[RegisterRouter.scala:87:24] wire out_woready_1_523; // @[RegisterRouter.scala:87:24] wire out_woready_1_524; // @[RegisterRouter.scala:87:24] wire out_woready_1_525; // @[RegisterRouter.scala:87:24] wire out_woready_1_526; // @[RegisterRouter.scala:87:24] wire out_woready_1_527; // @[RegisterRouter.scala:87:24] wire out_woready_1_528; // @[RegisterRouter.scala:87:24] wire out_woready_1_529; // @[RegisterRouter.scala:87:24] wire out_woready_1_530; // @[RegisterRouter.scala:87:24] wire out_woready_1_531; // @[RegisterRouter.scala:87:24] wire out_woready_1_532; // @[RegisterRouter.scala:87:24] wire out_woready_1_533; // @[RegisterRouter.scala:87:24] wire out_woready_1_534; // @[RegisterRouter.scala:87:24] wire out_woready_1_535; // @[RegisterRouter.scala:87:24] wire out_woready_1_536; // @[RegisterRouter.scala:87:24] wire out_woready_1_537; // @[RegisterRouter.scala:87:24] wire out_woready_1_538; // @[RegisterRouter.scala:87:24] wire out_woready_1_539; // @[RegisterRouter.scala:87:24] wire out_woready_1_540; // @[RegisterRouter.scala:87:24] wire out_woready_1_541; // @[RegisterRouter.scala:87:24] wire out_woready_1_542; // @[RegisterRouter.scala:87:24] wire out_woready_1_543; // @[RegisterRouter.scala:87:24] wire out_woready_1_544; // @[RegisterRouter.scala:87:24] wire out_woready_1_545; // @[RegisterRouter.scala:87:24] wire out_woready_1_546; // @[RegisterRouter.scala:87:24] wire out_woready_1_547; // @[RegisterRouter.scala:87:24] wire out_woready_1_548; // @[RegisterRouter.scala:87:24] wire out_woready_1_549; // @[RegisterRouter.scala:87:24] wire out_woready_1_550; // @[RegisterRouter.scala:87:24] wire out_woready_1_551; // @[RegisterRouter.scala:87:24] wire out_woready_1_552; // @[RegisterRouter.scala:87:24] wire out_woready_1_553; // @[RegisterRouter.scala:87:24] wire out_woready_1_554; // @[RegisterRouter.scala:87:24] wire out_woready_1_555; // @[RegisterRouter.scala:87:24] wire out_woready_1_556; // @[RegisterRouter.scala:87:24] wire out_woready_1_557; // @[RegisterRouter.scala:87:24] wire out_woready_1_558; // @[RegisterRouter.scala:87:24] wire out_woready_1_559; // @[RegisterRouter.scala:87:24] wire out_woready_1_560; // @[RegisterRouter.scala:87:24] wire out_woready_1_561; // @[RegisterRouter.scala:87:24] wire out_woready_1_562; // @[RegisterRouter.scala:87:24] wire out_woready_1_563; // @[RegisterRouter.scala:87:24] wire out_woready_1_564; // @[RegisterRouter.scala:87:24] wire out_woready_1_565; // @[RegisterRouter.scala:87:24] wire out_woready_1_566; // @[RegisterRouter.scala:87:24] wire out_woready_1_567; // @[RegisterRouter.scala:87:24] wire out_woready_1_568; // @[RegisterRouter.scala:87:24] wire out_woready_1_569; // @[RegisterRouter.scala:87:24] wire out_woready_1_570; // @[RegisterRouter.scala:87:24] wire out_woready_1_571; // @[RegisterRouter.scala:87:24] wire out_woready_1_572; // @[RegisterRouter.scala:87:24] wire out_woready_1_573; // @[RegisterRouter.scala:87:24] wire out_woready_1_574; // @[RegisterRouter.scala:87:24] wire out_woready_1_575; // @[RegisterRouter.scala:87:24] wire out_woready_1_576; // @[RegisterRouter.scala:87:24] wire out_woready_1_577; // @[RegisterRouter.scala:87:24] wire out_woready_1_578; // @[RegisterRouter.scala:87:24] wire out_woready_1_579; // @[RegisterRouter.scala:87:24] wire out_woready_1_580; // @[RegisterRouter.scala:87:24] wire out_woready_1_581; // @[RegisterRouter.scala:87:24] wire out_woready_1_582; // @[RegisterRouter.scala:87:24] wire out_woready_1_583; // @[RegisterRouter.scala:87:24] wire out_woready_1_584; // @[RegisterRouter.scala:87:24] wire out_woready_1_585; // @[RegisterRouter.scala:87:24] wire out_woready_1_586; // @[RegisterRouter.scala:87:24] wire out_woready_1_587; // @[RegisterRouter.scala:87:24] wire out_woready_1_588; // @[RegisterRouter.scala:87:24] wire out_woready_1_589; // @[RegisterRouter.scala:87:24] wire out_woready_1_590; // @[RegisterRouter.scala:87:24] wire out_woready_1_591; // @[RegisterRouter.scala:87:24] wire out_woready_1_592; // @[RegisterRouter.scala:87:24] wire out_woready_1_593; // @[RegisterRouter.scala:87:24] wire out_woready_1_594; // @[RegisterRouter.scala:87:24] wire out_woready_1_595; // @[RegisterRouter.scala:87:24] wire out_woready_1_596; // @[RegisterRouter.scala:87:24] wire out_woready_1_597; // @[RegisterRouter.scala:87:24] wire out_woready_1_598; // @[RegisterRouter.scala:87:24] wire out_woready_1_599; // @[RegisterRouter.scala:87:24] wire out_woready_1_600; // @[RegisterRouter.scala:87:24] wire out_woready_1_601; // @[RegisterRouter.scala:87:24] wire out_woready_1_602; // @[RegisterRouter.scala:87:24] wire out_woready_1_603; // @[RegisterRouter.scala:87:24] wire out_woready_1_604; // @[RegisterRouter.scala:87:24] wire out_woready_1_605; // @[RegisterRouter.scala:87:24] wire out_woready_1_606; // @[RegisterRouter.scala:87:24] wire out_woready_1_607; // @[RegisterRouter.scala:87:24] wire out_woready_1_608; // @[RegisterRouter.scala:87:24] wire out_woready_1_609; // @[RegisterRouter.scala:87:24] wire out_woready_1_610; // @[RegisterRouter.scala:87:24] wire out_woready_1_611; // @[RegisterRouter.scala:87:24] wire out_woready_1_612; // @[RegisterRouter.scala:87:24] wire out_woready_1_613; // @[RegisterRouter.scala:87:24] wire out_woready_1_614; // @[RegisterRouter.scala:87:24] wire out_woready_1_615; // @[RegisterRouter.scala:87:24] wire out_woready_1_616; // @[RegisterRouter.scala:87:24] wire out_woready_1_617; // @[RegisterRouter.scala:87:24] wire out_woready_1_618; // @[RegisterRouter.scala:87:24] wire out_woready_1_619; // @[RegisterRouter.scala:87:24] wire out_woready_1_620; // @[RegisterRouter.scala:87:24] wire out_woready_1_621; // @[RegisterRouter.scala:87:24] wire out_woready_1_622; // @[RegisterRouter.scala:87:24] wire out_woready_1_623; // @[RegisterRouter.scala:87:24] wire out_woready_1_624; // @[RegisterRouter.scala:87:24] wire out_woready_1_625; // @[RegisterRouter.scala:87:24] wire out_woready_1_626; // @[RegisterRouter.scala:87:24] wire out_woready_1_627; // @[RegisterRouter.scala:87:24] wire out_woready_1_628; // @[RegisterRouter.scala:87:24] wire out_woready_1_629; // @[RegisterRouter.scala:87:24] wire out_woready_1_630; // @[RegisterRouter.scala:87:24] wire out_woready_1_631; // @[RegisterRouter.scala:87:24] wire out_woready_1_632; // @[RegisterRouter.scala:87:24] wire out_woready_1_633; // @[RegisterRouter.scala:87:24] wire out_woready_1_634; // @[RegisterRouter.scala:87:24] wire out_woready_1_635; // @[RegisterRouter.scala:87:24] wire out_woready_1_636; // @[RegisterRouter.scala:87:24] wire out_woready_1_637; // @[RegisterRouter.scala:87:24] wire out_woready_1_638; // @[RegisterRouter.scala:87:24] wire out_woready_1_639; // @[RegisterRouter.scala:87:24] wire out_woready_1_640; // @[RegisterRouter.scala:87:24] wire out_woready_1_641; // @[RegisterRouter.scala:87:24] wire out_woready_1_642; // @[RegisterRouter.scala:87:24] wire out_woready_1_643; // @[RegisterRouter.scala:87:24] wire out_woready_1_644; // @[RegisterRouter.scala:87:24] wire out_woready_1_645; // @[RegisterRouter.scala:87:24] wire out_woready_1_646; // @[RegisterRouter.scala:87:24] wire out_woready_1_647; // @[RegisterRouter.scala:87:24] wire out_woready_1_648; // @[RegisterRouter.scala:87:24] wire out_woready_1_649; // @[RegisterRouter.scala:87:24] wire out_woready_1_650; // @[RegisterRouter.scala:87:24] wire out_woready_1_651; // @[RegisterRouter.scala:87:24] wire out_woready_1_652; // @[RegisterRouter.scala:87:24] wire out_woready_1_653; // @[RegisterRouter.scala:87:24] wire out_woready_1_654; // @[RegisterRouter.scala:87:24] wire out_woready_1_655; // @[RegisterRouter.scala:87:24] wire out_woready_1_656; // @[RegisterRouter.scala:87:24] wire out_woready_1_657; // @[RegisterRouter.scala:87:24] wire out_woready_1_658; // @[RegisterRouter.scala:87:24] wire out_woready_1_659; // @[RegisterRouter.scala:87:24] wire out_woready_1_660; // @[RegisterRouter.scala:87:24] wire out_woready_1_661; // @[RegisterRouter.scala:87:24] wire out_woready_1_662; // @[RegisterRouter.scala:87:24] wire out_woready_1_663; // @[RegisterRouter.scala:87:24] wire out_woready_1_664; // @[RegisterRouter.scala:87:24] wire out_woready_1_665; // @[RegisterRouter.scala:87:24] wire out_woready_1_666; // @[RegisterRouter.scala:87:24] wire out_woready_1_667; // @[RegisterRouter.scala:87:24] wire out_woready_1_668; // @[RegisterRouter.scala:87:24] wire out_woready_1_669; // @[RegisterRouter.scala:87:24] wire out_woready_1_670; // @[RegisterRouter.scala:87:24] wire out_woready_1_671; // @[RegisterRouter.scala:87:24] wire out_woready_1_672; // @[RegisterRouter.scala:87:24] wire out_woready_1_673; // @[RegisterRouter.scala:87:24] wire out_woready_1_674; // @[RegisterRouter.scala:87:24] wire out_woready_1_675; // @[RegisterRouter.scala:87:24] wire out_woready_1_676; // @[RegisterRouter.scala:87:24] wire out_woready_1_677; // @[RegisterRouter.scala:87:24] wire out_woready_1_678; // @[RegisterRouter.scala:87:24] wire out_woready_1_679; // @[RegisterRouter.scala:87:24] wire out_woready_1_680; // @[RegisterRouter.scala:87:24] wire out_woready_1_681; // @[RegisterRouter.scala:87:24] wire out_woready_1_682; // @[RegisterRouter.scala:87:24] wire out_woready_1_683; // @[RegisterRouter.scala:87:24] wire out_woready_1_684; // @[RegisterRouter.scala:87:24] wire out_woready_1_685; // @[RegisterRouter.scala:87:24] wire out_woready_1_686; // @[RegisterRouter.scala:87:24] wire out_woready_1_687; // @[RegisterRouter.scala:87:24] wire out_woready_1_688; // @[RegisterRouter.scala:87:24] wire out_woready_1_689; // @[RegisterRouter.scala:87:24] wire out_woready_1_690; // @[RegisterRouter.scala:87:24] wire out_woready_1_691; // @[RegisterRouter.scala:87:24] wire out_woready_1_692; // @[RegisterRouter.scala:87:24] wire out_woready_1_693; // @[RegisterRouter.scala:87:24] wire out_woready_1_694; // @[RegisterRouter.scala:87:24] wire out_woready_1_695; // @[RegisterRouter.scala:87:24] wire out_woready_1_696; // @[RegisterRouter.scala:87:24] wire out_woready_1_697; // @[RegisterRouter.scala:87:24] wire out_woready_1_698; // @[RegisterRouter.scala:87:24] wire out_woready_1_699; // @[RegisterRouter.scala:87:24] wire out_woready_1_700; // @[RegisterRouter.scala:87:24] wire out_woready_1_701; // @[RegisterRouter.scala:87:24] wire out_woready_1_702; // @[RegisterRouter.scala:87:24] wire out_woready_1_703; // @[RegisterRouter.scala:87:24] wire out_woready_1_704; // @[RegisterRouter.scala:87:24] wire out_woready_1_705; // @[RegisterRouter.scala:87:24] wire out_woready_1_706; // @[RegisterRouter.scala:87:24] wire out_woready_1_707; // @[RegisterRouter.scala:87:24] wire out_woready_1_708; // @[RegisterRouter.scala:87:24] wire out_woready_1_709; // @[RegisterRouter.scala:87:24] wire out_woready_1_710; // @[RegisterRouter.scala:87:24] wire out_woready_1_711; // @[RegisterRouter.scala:87:24] wire out_woready_1_712; // @[RegisterRouter.scala:87:24] wire out_woready_1_713; // @[RegisterRouter.scala:87:24] wire out_woready_1_714; // @[RegisterRouter.scala:87:24] wire out_woready_1_715; // @[RegisterRouter.scala:87:24] wire out_woready_1_716; // @[RegisterRouter.scala:87:24] wire out_woready_1_717; // @[RegisterRouter.scala:87:24] wire out_woready_1_718; // @[RegisterRouter.scala:87:24] wire out_woready_1_719; // @[RegisterRouter.scala:87:24] wire out_woready_1_720; // @[RegisterRouter.scala:87:24] wire out_woready_1_721; // @[RegisterRouter.scala:87:24] wire out_woready_1_722; // @[RegisterRouter.scala:87:24] wire out_woready_1_723; // @[RegisterRouter.scala:87:24] wire out_woready_1_724; // @[RegisterRouter.scala:87:24] wire out_woready_1_725; // @[RegisterRouter.scala:87:24] wire out_woready_1_726; // @[RegisterRouter.scala:87:24] wire out_woready_1_727; // @[RegisterRouter.scala:87:24] wire out_woready_1_728; // @[RegisterRouter.scala:87:24] wire out_woready_1_729; // @[RegisterRouter.scala:87:24] wire out_woready_1_730; // @[RegisterRouter.scala:87:24] wire out_woready_1_731; // @[RegisterRouter.scala:87:24] wire out_woready_1_732; // @[RegisterRouter.scala:87:24] wire out_woready_1_733; // @[RegisterRouter.scala:87:24] wire out_woready_1_734; // @[RegisterRouter.scala:87:24] wire out_woready_1_735; // @[RegisterRouter.scala:87:24] wire out_woready_1_736; // @[RegisterRouter.scala:87:24] wire out_woready_1_737; // @[RegisterRouter.scala:87:24] wire out_woready_1_738; // @[RegisterRouter.scala:87:24] wire out_woready_1_739; // @[RegisterRouter.scala:87:24] wire out_woready_1_740; // @[RegisterRouter.scala:87:24] wire out_woready_1_741; // @[RegisterRouter.scala:87:24] wire out_woready_1_742; // @[RegisterRouter.scala:87:24] wire out_woready_1_743; // @[RegisterRouter.scala:87:24] wire out_woready_1_744; // @[RegisterRouter.scala:87:24] wire out_woready_1_745; // @[RegisterRouter.scala:87:24] wire out_woready_1_746; // @[RegisterRouter.scala:87:24] wire out_woready_1_747; // @[RegisterRouter.scala:87:24] wire out_woready_1_748; // @[RegisterRouter.scala:87:24] wire out_woready_1_749; // @[RegisterRouter.scala:87:24] wire out_woready_1_750; // @[RegisterRouter.scala:87:24] wire out_woready_1_751; // @[RegisterRouter.scala:87:24] wire out_woready_1_752; // @[RegisterRouter.scala:87:24] wire out_woready_1_753; // @[RegisterRouter.scala:87:24] wire out_woready_1_754; // @[RegisterRouter.scala:87:24] wire out_woready_1_755; // @[RegisterRouter.scala:87:24] wire out_woready_1_756; // @[RegisterRouter.scala:87:24] wire out_woready_1_757; // @[RegisterRouter.scala:87:24] wire out_woready_1_758; // @[RegisterRouter.scala:87:24] wire out_woready_1_759; // @[RegisterRouter.scala:87:24] wire out_woready_1_760; // @[RegisterRouter.scala:87:24] wire out_woready_1_761; // @[RegisterRouter.scala:87:24] wire out_woready_1_762; // @[RegisterRouter.scala:87:24] wire out_woready_1_763; // @[RegisterRouter.scala:87:24] wire out_woready_1_764; // @[RegisterRouter.scala:87:24] wire out_woready_1_765; // @[RegisterRouter.scala:87:24] wire out_woready_1_766; // @[RegisterRouter.scala:87:24] wire out_woready_1_767; // @[RegisterRouter.scala:87:24] wire out_woready_1_768; // @[RegisterRouter.scala:87:24] wire out_woready_1_769; // @[RegisterRouter.scala:87:24] wire out_woready_1_770; // @[RegisterRouter.scala:87:24] wire out_woready_1_771; // @[RegisterRouter.scala:87:24] wire out_woready_1_772; // @[RegisterRouter.scala:87:24] wire out_woready_1_773; // @[RegisterRouter.scala:87:24] wire out_woready_1_774; // @[RegisterRouter.scala:87:24] wire out_woready_1_775; // @[RegisterRouter.scala:87:24] wire out_woready_1_776; // @[RegisterRouter.scala:87:24] wire out_woready_1_777; // @[RegisterRouter.scala:87:24] wire out_woready_1_778; // @[RegisterRouter.scala:87:24] wire out_woready_1_779; // @[RegisterRouter.scala:87:24] wire out_woready_1_780; // @[RegisterRouter.scala:87:24] wire out_woready_1_781; // @[RegisterRouter.scala:87:24] wire out_woready_1_782; // @[RegisterRouter.scala:87:24] wire out_woready_1_783; // @[RegisterRouter.scala:87:24] wire out_woready_1_784; // @[RegisterRouter.scala:87:24] wire out_woready_1_785; // @[RegisterRouter.scala:87:24] wire out_woready_1_786; // @[RegisterRouter.scala:87:24] wire out_woready_1_787; // @[RegisterRouter.scala:87:24] wire out_woready_1_788; // @[RegisterRouter.scala:87:24] wire out_woready_1_789; // @[RegisterRouter.scala:87:24] wire out_woready_1_790; // @[RegisterRouter.scala:87:24] wire out_woready_1_791; // @[RegisterRouter.scala:87:24] wire out_woready_1_792; // @[RegisterRouter.scala:87:24] wire out_woready_1_793; // @[RegisterRouter.scala:87:24] wire out_woready_1_794; // @[RegisterRouter.scala:87:24] wire out_woready_1_795; // @[RegisterRouter.scala:87:24] wire out_woready_1_796; // @[RegisterRouter.scala:87:24] wire out_woready_1_797; // @[RegisterRouter.scala:87:24] wire out_woready_1_798; // @[RegisterRouter.scala:87:24] wire out_woready_1_799; // @[RegisterRouter.scala:87:24] wire out_woready_1_800; // @[RegisterRouter.scala:87:24] wire out_woready_1_801; // @[RegisterRouter.scala:87:24] wire out_woready_1_802; // @[RegisterRouter.scala:87:24] wire out_woready_1_803; // @[RegisterRouter.scala:87:24] wire out_woready_1_804; // @[RegisterRouter.scala:87:24] wire out_woready_1_805; // @[RegisterRouter.scala:87:24] wire out_woready_1_806; // @[RegisterRouter.scala:87:24] wire out_woready_1_807; // @[RegisterRouter.scala:87:24] wire out_woready_1_808; // @[RegisterRouter.scala:87:24] wire out_woready_1_809; // @[RegisterRouter.scala:87:24] wire out_woready_1_810; // @[RegisterRouter.scala:87:24] wire out_woready_1_811; // @[RegisterRouter.scala:87:24] wire out_woready_1_812; // @[RegisterRouter.scala:87:24] wire out_woready_1_813; // @[RegisterRouter.scala:87:24] wire out_woready_1_814; // @[RegisterRouter.scala:87:24] wire out_woready_1_815; // @[RegisterRouter.scala:87:24] wire out_woready_1_816; // @[RegisterRouter.scala:87:24] wire out_woready_1_817; // @[RegisterRouter.scala:87:24] wire out_woready_1_818; // @[RegisterRouter.scala:87:24] wire out_woready_1_819; // @[RegisterRouter.scala:87:24] wire out_woready_1_820; // @[RegisterRouter.scala:87:24] wire out_woready_1_821; // @[RegisterRouter.scala:87:24] wire out_woready_1_822; // @[RegisterRouter.scala:87:24] wire out_woready_1_823; // @[RegisterRouter.scala:87:24] wire out_woready_1_824; // @[RegisterRouter.scala:87:24] wire out_woready_1_825; // @[RegisterRouter.scala:87:24] wire out_woready_1_826; // @[RegisterRouter.scala:87:24] wire out_woready_1_827; // @[RegisterRouter.scala:87:24] wire out_woready_1_828; // @[RegisterRouter.scala:87:24] wire out_woready_1_829; // @[RegisterRouter.scala:87:24] wire out_woready_1_830; // @[RegisterRouter.scala:87:24] wire out_woready_1_831; // @[RegisterRouter.scala:87:24] wire out_woready_1_832; // @[RegisterRouter.scala:87:24] wire out_woready_1_833; // @[RegisterRouter.scala:87:24] wire out_woready_1_834; // @[RegisterRouter.scala:87:24] wire out_woready_1_835; // @[RegisterRouter.scala:87:24] wire out_woready_1_836; // @[RegisterRouter.scala:87:24] wire out_woready_1_837; // @[RegisterRouter.scala:87:24] wire out_woready_1_838; // @[RegisterRouter.scala:87:24] wire out_woready_1_839; // @[RegisterRouter.scala:87:24] wire out_woready_1_840; // @[RegisterRouter.scala:87:24] wire out_woready_1_841; // @[RegisterRouter.scala:87:24] wire out_woready_1_842; // @[RegisterRouter.scala:87:24] wire out_woready_1_843; // @[RegisterRouter.scala:87:24] wire out_woready_1_844; // @[RegisterRouter.scala:87:24] wire out_woready_1_845; // @[RegisterRouter.scala:87:24] wire out_woready_1_846; // @[RegisterRouter.scala:87:24] wire out_woready_1_847; // @[RegisterRouter.scala:87:24] wire out_woready_1_848; // @[RegisterRouter.scala:87:24] wire out_woready_1_849; // @[RegisterRouter.scala:87:24] wire out_woready_1_850; // @[RegisterRouter.scala:87:24] wire out_woready_1_851; // @[RegisterRouter.scala:87:24] wire out_woready_1_852; // @[RegisterRouter.scala:87:24] wire out_woready_1_853; // @[RegisterRouter.scala:87:24] wire out_woready_1_854; // @[RegisterRouter.scala:87:24] wire out_woready_1_855; // @[RegisterRouter.scala:87:24] wire out_woready_1_856; // @[RegisterRouter.scala:87:24] wire out_woready_1_857; // @[RegisterRouter.scala:87:24] wire out_woready_1_858; // @[RegisterRouter.scala:87:24] wire out_woready_1_859; // @[RegisterRouter.scala:87:24] wire out_woready_1_860; // @[RegisterRouter.scala:87:24] wire out_woready_1_861; // @[RegisterRouter.scala:87:24] wire out_woready_1_862; // @[RegisterRouter.scala:87:24] wire out_woready_1_863; // @[RegisterRouter.scala:87:24] wire out_woready_1_864; // @[RegisterRouter.scala:87:24] wire out_woready_1_865; // @[RegisterRouter.scala:87:24] wire out_woready_1_866; // @[RegisterRouter.scala:87:24] wire out_woready_1_867; // @[RegisterRouter.scala:87:24] wire out_woready_1_868; // @[RegisterRouter.scala:87:24] wire out_woready_1_869; // @[RegisterRouter.scala:87:24] wire out_woready_1_870; // @[RegisterRouter.scala:87:24] wire out_woready_1_871; // @[RegisterRouter.scala:87:24] wire out_woready_1_872; // @[RegisterRouter.scala:87:24] wire out_woready_1_873; // @[RegisterRouter.scala:87:24] wire out_woready_1_874; // @[RegisterRouter.scala:87:24] wire out_woready_1_875; // @[RegisterRouter.scala:87:24] wire out_woready_1_876; // @[RegisterRouter.scala:87:24] wire out_woready_1_877; // @[RegisterRouter.scala:87:24] wire out_woready_1_878; // @[RegisterRouter.scala:87:24] wire out_woready_1_879; // @[RegisterRouter.scala:87:24] wire out_woready_1_880; // @[RegisterRouter.scala:87:24] wire out_woready_1_881; // @[RegisterRouter.scala:87:24] wire out_woready_1_882; // @[RegisterRouter.scala:87:24] wire out_woready_1_883; // @[RegisterRouter.scala:87:24] wire out_woready_1_884; // @[RegisterRouter.scala:87:24] wire out_woready_1_885; // @[RegisterRouter.scala:87:24] wire out_woready_1_886; // @[RegisterRouter.scala:87:24] wire out_woready_1_887; // @[RegisterRouter.scala:87:24] wire out_woready_1_888; // @[RegisterRouter.scala:87:24] wire out_woready_1_889; // @[RegisterRouter.scala:87:24] wire out_woready_1_890; // @[RegisterRouter.scala:87:24] wire out_woready_1_891; // @[RegisterRouter.scala:87:24] wire out_woready_1_892; // @[RegisterRouter.scala:87:24] wire out_woready_1_893; // @[RegisterRouter.scala:87:24] wire out_woready_1_894; // @[RegisterRouter.scala:87:24] wire out_woready_1_895; // @[RegisterRouter.scala:87:24] wire out_woready_1_896; // @[RegisterRouter.scala:87:24] wire out_woready_1_897; // @[RegisterRouter.scala:87:24] wire out_woready_1_898; // @[RegisterRouter.scala:87:24] wire out_woready_1_899; // @[RegisterRouter.scala:87:24] wire out_woready_1_900; // @[RegisterRouter.scala:87:24] wire out_woready_1_901; // @[RegisterRouter.scala:87:24] wire out_woready_1_902; // @[RegisterRouter.scala:87:24] wire out_woready_1_903; // @[RegisterRouter.scala:87:24] wire out_woready_1_904; // @[RegisterRouter.scala:87:24] wire out_woready_1_905; // @[RegisterRouter.scala:87:24] wire out_woready_1_906; // @[RegisterRouter.scala:87:24] wire out_woready_1_907; // @[RegisterRouter.scala:87:24] wire out_woready_1_908; // @[RegisterRouter.scala:87:24] wire out_woready_1_909; // @[RegisterRouter.scala:87:24] wire out_woready_1_910; // @[RegisterRouter.scala:87:24] wire out_woready_1_911; // @[RegisterRouter.scala:87:24] wire out_woready_1_912; // @[RegisterRouter.scala:87:24] wire out_woready_1_913; // @[RegisterRouter.scala:87:24] wire out_woready_1_914; // @[RegisterRouter.scala:87:24] wire out_woready_1_915; // @[RegisterRouter.scala:87:24] wire out_woready_1_916; // @[RegisterRouter.scala:87:24] wire out_woready_1_917; // @[RegisterRouter.scala:87:24] wire out_woready_1_918; // @[RegisterRouter.scala:87:24] wire out_woready_1_919; // @[RegisterRouter.scala:87:24] wire out_woready_1_920; // @[RegisterRouter.scala:87:24] wire out_woready_1_921; // @[RegisterRouter.scala:87:24] wire out_woready_1_922; // @[RegisterRouter.scala:87:24] wire out_woready_1_923; // @[RegisterRouter.scala:87:24] wire out_woready_1_924; // @[RegisterRouter.scala:87:24] wire out_woready_1_925; // @[RegisterRouter.scala:87:24] wire out_woready_1_926; // @[RegisterRouter.scala:87:24] wire out_woready_1_927; // @[RegisterRouter.scala:87:24] wire out_woready_1_928; // @[RegisterRouter.scala:87:24] wire out_woready_1_929; // @[RegisterRouter.scala:87:24] wire out_woready_1_930; // @[RegisterRouter.scala:87:24] wire out_woready_1_931; // @[RegisterRouter.scala:87:24] wire out_woready_1_932; // @[RegisterRouter.scala:87:24] wire out_woready_1_933; // @[RegisterRouter.scala:87:24] wire out_woready_1_934; // @[RegisterRouter.scala:87:24] wire out_woready_1_935; // @[RegisterRouter.scala:87:24] wire out_woready_1_936; // @[RegisterRouter.scala:87:24] wire out_woready_1_937; // @[RegisterRouter.scala:87:24] wire out_woready_1_938; // @[RegisterRouter.scala:87:24] wire out_woready_1_939; // @[RegisterRouter.scala:87:24] wire out_woready_1_940; // @[RegisterRouter.scala:87:24] wire out_woready_1_941; // @[RegisterRouter.scala:87:24] wire out_woready_1_942; // @[RegisterRouter.scala:87:24] wire out_woready_1_943; // @[RegisterRouter.scala:87:24] wire out_woready_1_944; // @[RegisterRouter.scala:87:24] wire out_woready_1_945; // @[RegisterRouter.scala:87:24] wire out_woready_1_946; // @[RegisterRouter.scala:87:24] wire out_woready_1_947; // @[RegisterRouter.scala:87:24] wire out_woready_1_948; // @[RegisterRouter.scala:87:24] wire out_woready_1_949; // @[RegisterRouter.scala:87:24] wire out_woready_1_950; // @[RegisterRouter.scala:87:24] wire out_woready_1_951; // @[RegisterRouter.scala:87:24] wire out_woready_1_952; // @[RegisterRouter.scala:87:24] wire out_woready_1_953; // @[RegisterRouter.scala:87:24] wire out_woready_1_954; // @[RegisterRouter.scala:87:24] wire out_woready_1_955; // @[RegisterRouter.scala:87:24] wire out_woready_1_956; // @[RegisterRouter.scala:87:24] wire out_woready_1_957; // @[RegisterRouter.scala:87:24] wire out_woready_1_958; // @[RegisterRouter.scala:87:24] wire out_woready_1_959; // @[RegisterRouter.scala:87:24] wire out_woready_1_960; // @[RegisterRouter.scala:87:24] wire out_woready_1_961; // @[RegisterRouter.scala:87:24] wire out_woready_1_962; // @[RegisterRouter.scala:87:24] wire out_woready_1_963; // @[RegisterRouter.scala:87:24] wire out_woready_1_964; // @[RegisterRouter.scala:87:24] wire out_woready_1_965; // @[RegisterRouter.scala:87:24] wire out_woready_1_966; // @[RegisterRouter.scala:87:24] wire out_woready_1_967; // @[RegisterRouter.scala:87:24] wire out_woready_1_968; // @[RegisterRouter.scala:87:24] wire out_woready_1_969; // @[RegisterRouter.scala:87:24] wire out_woready_1_970; // @[RegisterRouter.scala:87:24] wire out_woready_1_971; // @[RegisterRouter.scala:87:24] wire out_woready_1_972; // @[RegisterRouter.scala:87:24] wire out_woready_1_973; // @[RegisterRouter.scala:87:24] wire out_woready_1_974; // @[RegisterRouter.scala:87:24] wire out_woready_1_975; // @[RegisterRouter.scala:87:24] wire out_woready_1_976; // @[RegisterRouter.scala:87:24] wire out_woready_1_977; // @[RegisterRouter.scala:87:24] wire out_woready_1_978; // @[RegisterRouter.scala:87:24] wire out_woready_1_979; // @[RegisterRouter.scala:87:24] wire out_woready_1_980; // @[RegisterRouter.scala:87:24] wire out_woready_1_981; // @[RegisterRouter.scala:87:24] wire out_woready_1_982; // @[RegisterRouter.scala:87:24] wire out_woready_1_983; // @[RegisterRouter.scala:87:24] wire out_woready_1_984; // @[RegisterRouter.scala:87:24] wire out_woready_1_985; // @[RegisterRouter.scala:87:24] wire out_woready_1_986; // @[RegisterRouter.scala:87:24] wire out_woready_1_987; // @[RegisterRouter.scala:87:24] wire out_woready_1_988; // @[RegisterRouter.scala:87:24] wire out_woready_1_989; // @[RegisterRouter.scala:87:24] wire out_woready_1_990; // @[RegisterRouter.scala:87:24] wire out_woready_1_991; // @[RegisterRouter.scala:87:24] wire out_woready_1_992; // @[RegisterRouter.scala:87:24] wire out_woready_1_993; // @[RegisterRouter.scala:87:24] wire out_woready_1_994; // @[RegisterRouter.scala:87:24] wire out_woready_1_995; // @[RegisterRouter.scala:87:24] wire out_woready_1_996; // @[RegisterRouter.scala:87:24] wire out_woready_1_997; // @[RegisterRouter.scala:87:24] wire out_woready_1_998; // @[RegisterRouter.scala:87:24] wire out_woready_1_999; // @[RegisterRouter.scala:87:24] wire out_woready_1_1000; // @[RegisterRouter.scala:87:24] wire out_woready_1_1001; // @[RegisterRouter.scala:87:24] wire out_woready_1_1002; // @[RegisterRouter.scala:87:24] wire out_woready_1_1003; // @[RegisterRouter.scala:87:24] wire out_woready_1_1004; // @[RegisterRouter.scala:87:24] wire out_woready_1_1005; // @[RegisterRouter.scala:87:24] wire out_woready_1_1006; // @[RegisterRouter.scala:87:24] wire out_woready_1_1007; // @[RegisterRouter.scala:87:24] wire out_woready_1_1008; // @[RegisterRouter.scala:87:24] wire out_woready_1_1009; // @[RegisterRouter.scala:87:24] wire out_woready_1_1010; // @[RegisterRouter.scala:87:24] wire out_woready_1_1011; // @[RegisterRouter.scala:87:24] wire out_woready_1_1012; // @[RegisterRouter.scala:87:24] wire out_woready_1_1013; // @[RegisterRouter.scala:87:24] wire out_woready_1_1014; // @[RegisterRouter.scala:87:24] wire out_woready_1_1015; // @[RegisterRouter.scala:87:24] wire out_woready_1_1016; // @[RegisterRouter.scala:87:24] wire out_woready_1_1017; // @[RegisterRouter.scala:87:24] wire out_woready_1_1018; // @[RegisterRouter.scala:87:24] wire out_woready_1_1019; // @[RegisterRouter.scala:87:24] wire out_woready_1_1020; // @[RegisterRouter.scala:87:24] wire out_woready_1_1021; // @[RegisterRouter.scala:87:24] wire out_woready_1_1022; // @[RegisterRouter.scala:87:24] wire out_woready_1_1023; // @[RegisterRouter.scala:87:24] wire out_woready_1_1024; // @[RegisterRouter.scala:87:24] wire out_woready_1_1025; // @[RegisterRouter.scala:87:24] wire out_woready_1_1026; // @[RegisterRouter.scala:87:24] wire out_woready_1_1027; // @[RegisterRouter.scala:87:24] wire out_woready_1_1028; // @[RegisterRouter.scala:87:24] wire out_woready_1_1029; // @[RegisterRouter.scala:87:24] wire out_woready_1_1030; // @[RegisterRouter.scala:87:24] wire out_woready_1_1031; // @[RegisterRouter.scala:87:24] wire out_woready_1_1032; // @[RegisterRouter.scala:87:24] wire out_woready_1_1033; // @[RegisterRouter.scala:87:24] wire out_woready_1_1034; // @[RegisterRouter.scala:87:24] wire out_woready_1_1035; // @[RegisterRouter.scala:87:24] wire out_woready_1_1036; // @[RegisterRouter.scala:87:24] wire out_woready_1_1037; // @[RegisterRouter.scala:87:24] wire out_woready_1_1038; // @[RegisterRouter.scala:87:24] wire out_woready_1_1039; // @[RegisterRouter.scala:87:24] wire out_woready_1_1040; // @[RegisterRouter.scala:87:24] wire out_woready_1_1041; // @[RegisterRouter.scala:87:24] wire out_woready_1_1042; // @[RegisterRouter.scala:87:24] wire out_woready_1_1043; // @[RegisterRouter.scala:87:24] wire out_woready_1_1044; // @[RegisterRouter.scala:87:24] wire out_woready_1_1045; // @[RegisterRouter.scala:87:24] wire out_woready_1_1046; // @[RegisterRouter.scala:87:24] wire out_woready_1_1047; // @[RegisterRouter.scala:87:24] wire out_woready_1_1048; // @[RegisterRouter.scala:87:24] wire out_woready_1_1049; // @[RegisterRouter.scala:87:24] wire out_woready_1_1050; // @[RegisterRouter.scala:87:24] wire out_woready_1_1051; // @[RegisterRouter.scala:87:24] wire out_woready_1_1052; // @[RegisterRouter.scala:87:24] wire out_woready_1_1053; // @[RegisterRouter.scala:87:24] wire out_woready_1_1054; // @[RegisterRouter.scala:87:24] wire out_woready_1_1055; // @[RegisterRouter.scala:87:24] wire out_woready_1_1056; // @[RegisterRouter.scala:87:24] wire out_woready_1_1057; // @[RegisterRouter.scala:87:24] wire out_woready_1_1058; // @[RegisterRouter.scala:87:24] wire out_woready_1_1059; // @[RegisterRouter.scala:87:24] wire out_woready_1_1060; // @[RegisterRouter.scala:87:24] wire out_woready_1_1061; // @[RegisterRouter.scala:87:24] wire out_woready_1_1062; // @[RegisterRouter.scala:87:24] wire out_woready_1_1063; // @[RegisterRouter.scala:87:24] wire out_woready_1_1064; // @[RegisterRouter.scala:87:24] wire out_woready_1_1065; // @[RegisterRouter.scala:87:24] wire out_woready_1_1066; // @[RegisterRouter.scala:87:24] wire out_woready_1_1067; // @[RegisterRouter.scala:87:24] wire out_woready_1_1068; // @[RegisterRouter.scala:87:24] wire out_woready_1_1069; // @[RegisterRouter.scala:87:24] wire out_woready_1_1070; // @[RegisterRouter.scala:87:24] wire out_woready_1_1071; // @[RegisterRouter.scala:87:24] wire out_woready_1_1072; // @[RegisterRouter.scala:87:24] wire out_woready_1_1073; // @[RegisterRouter.scala:87:24] wire out_woready_1_1074; // @[RegisterRouter.scala:87:24] wire out_woready_1_1075; // @[RegisterRouter.scala:87:24] wire out_woready_1_1076; // @[RegisterRouter.scala:87:24] wire out_woready_1_1077; // @[RegisterRouter.scala:87:24] wire out_woready_1_1078; // @[RegisterRouter.scala:87:24] wire out_woready_1_1079; // @[RegisterRouter.scala:87:24] wire out_woready_1_1080; // @[RegisterRouter.scala:87:24] wire out_woready_1_1081; // @[RegisterRouter.scala:87:24] wire out_woready_1_1082; // @[RegisterRouter.scala:87:24] wire out_woready_1_1083; // @[RegisterRouter.scala:87:24] wire out_woready_1_1084; // @[RegisterRouter.scala:87:24] wire out_woready_1_1085; // @[RegisterRouter.scala:87:24] wire out_woready_1_1086; // @[RegisterRouter.scala:87:24] wire out_woready_1_1087; // @[RegisterRouter.scala:87:24] wire out_woready_1_1088; // @[RegisterRouter.scala:87:24] wire out_woready_1_1089; // @[RegisterRouter.scala:87:24] wire out_woready_1_1090; // @[RegisterRouter.scala:87:24] wire out_woready_1_1091; // @[RegisterRouter.scala:87:24] wire out_woready_1_1092; // @[RegisterRouter.scala:87:24] wire out_woready_1_1093; // @[RegisterRouter.scala:87:24] wire out_woready_1_1094; // @[RegisterRouter.scala:87:24] wire out_woready_1_1095; // @[RegisterRouter.scala:87:24] wire out_woready_1_1096; // @[RegisterRouter.scala:87:24] wire out_woready_1_1097; // @[RegisterRouter.scala:87:24] wire out_woready_1_1098; // @[RegisterRouter.scala:87:24] wire out_woready_1_1099; // @[RegisterRouter.scala:87:24] wire out_woready_1_1100; // @[RegisterRouter.scala:87:24] wire out_woready_1_1101; // @[RegisterRouter.scala:87:24] wire out_woready_1_1102; // @[RegisterRouter.scala:87:24] wire out_woready_1_1103; // @[RegisterRouter.scala:87:24] wire out_woready_1_1104; // @[RegisterRouter.scala:87:24] wire out_woready_1_1105; // @[RegisterRouter.scala:87:24] wire out_woready_1_1106; // @[RegisterRouter.scala:87:24] wire out_woready_1_1107; // @[RegisterRouter.scala:87:24] wire out_woready_1_1108; // @[RegisterRouter.scala:87:24] wire out_woready_1_1109; // @[RegisterRouter.scala:87:24] wire out_woready_1_1110; // @[RegisterRouter.scala:87:24] wire out_woready_1_1111; // @[RegisterRouter.scala:87:24] wire out_woready_1_1112; // @[RegisterRouter.scala:87:24] wire out_woready_1_1113; // @[RegisterRouter.scala:87:24] wire out_woready_1_1114; // @[RegisterRouter.scala:87:24] wire out_woready_1_1115; // @[RegisterRouter.scala:87:24] wire out_woready_1_1116; // @[RegisterRouter.scala:87:24] wire out_woready_1_1117; // @[RegisterRouter.scala:87:24] wire out_woready_1_1118; // @[RegisterRouter.scala:87:24] wire out_woready_1_1119; // @[RegisterRouter.scala:87:24] wire out_woready_1_1120; // @[RegisterRouter.scala:87:24] wire out_woready_1_1121; // @[RegisterRouter.scala:87:24] wire out_woready_1_1122; // @[RegisterRouter.scala:87:24] wire out_woready_1_1123; // @[RegisterRouter.scala:87:24] wire out_woready_1_1124; // @[RegisterRouter.scala:87:24] wire out_woready_1_1125; // @[RegisterRouter.scala:87:24] wire out_woready_1_1126; // @[RegisterRouter.scala:87:24] wire out_woready_1_1127; // @[RegisterRouter.scala:87:24] wire out_woready_1_1128; // @[RegisterRouter.scala:87:24] wire out_woready_1_1129; // @[RegisterRouter.scala:87:24] wire out_woready_1_1130; // @[RegisterRouter.scala:87:24] wire out_woready_1_1131; // @[RegisterRouter.scala:87:24] wire out_woready_1_1132; // @[RegisterRouter.scala:87:24] wire out_woready_1_1133; // @[RegisterRouter.scala:87:24] wire out_woready_1_1134; // @[RegisterRouter.scala:87:24] wire out_woready_1_1135; // @[RegisterRouter.scala:87:24] wire out_woready_1_1136; // @[RegisterRouter.scala:87:24] wire out_woready_1_1137; // @[RegisterRouter.scala:87:24] wire out_woready_1_1138; // @[RegisterRouter.scala:87:24] wire out_woready_1_1139; // @[RegisterRouter.scala:87:24] wire out_woready_1_1140; // @[RegisterRouter.scala:87:24] wire out_woready_1_1141; // @[RegisterRouter.scala:87:24] wire out_woready_1_1142; // @[RegisterRouter.scala:87:24] wire out_woready_1_1143; // @[RegisterRouter.scala:87:24] wire out_woready_1_1144; // @[RegisterRouter.scala:87:24] wire out_woready_1_1145; // @[RegisterRouter.scala:87:24] wire out_woready_1_1146; // @[RegisterRouter.scala:87:24] wire out_woready_1_1147; // @[RegisterRouter.scala:87:24] wire out_woready_1_1148; // @[RegisterRouter.scala:87:24] wire out_woready_1_1149; // @[RegisterRouter.scala:87:24] wire out_woready_1_1150; // @[RegisterRouter.scala:87:24] wire out_woready_1_1151; // @[RegisterRouter.scala:87:24] wire out_woready_1_1152; // @[RegisterRouter.scala:87:24] wire out_woready_1_1153; // @[RegisterRouter.scala:87:24] wire out_woready_1_1154; // @[RegisterRouter.scala:87:24] wire out_woready_1_1155; // @[RegisterRouter.scala:87:24] wire out_woready_1_1156; // @[RegisterRouter.scala:87:24] wire out_woready_1_1157; // @[RegisterRouter.scala:87:24] wire out_woready_1_1158; // @[RegisterRouter.scala:87:24] wire out_woready_1_1159; // @[RegisterRouter.scala:87:24] wire out_woready_1_1160; // @[RegisterRouter.scala:87:24] wire out_woready_1_1161; // @[RegisterRouter.scala:87:24] wire out_woready_1_1162; // @[RegisterRouter.scala:87:24] wire out_woready_1_1163; // @[RegisterRouter.scala:87:24] wire out_woready_1_1164; // @[RegisterRouter.scala:87:24] wire out_woready_1_1165; // @[RegisterRouter.scala:87:24] wire out_woready_1_1166; // @[RegisterRouter.scala:87:24] wire out_woready_1_1167; // @[RegisterRouter.scala:87:24] wire out_woready_1_1168; // @[RegisterRouter.scala:87:24] wire out_woready_1_1169; // @[RegisterRouter.scala:87:24] wire out_woready_1_1170; // @[RegisterRouter.scala:87:24] wire out_woready_1_1171; // @[RegisterRouter.scala:87:24] wire out_woready_1_1172; // @[RegisterRouter.scala:87:24] wire out_woready_1_1173; // @[RegisterRouter.scala:87:24] wire out_woready_1_1174; // @[RegisterRouter.scala:87:24] wire out_woready_1_1175; // @[RegisterRouter.scala:87:24] wire out_woready_1_1176; // @[RegisterRouter.scala:87:24] wire out_woready_1_1177; // @[RegisterRouter.scala:87:24] wire out_woready_1_1178; // @[RegisterRouter.scala:87:24] wire out_woready_1_1179; // @[RegisterRouter.scala:87:24] wire out_woready_1_1180; // @[RegisterRouter.scala:87:24] wire out_woready_1_1181; // @[RegisterRouter.scala:87:24] wire out_woready_1_1182; // @[RegisterRouter.scala:87:24] wire out_woready_1_1183; // @[RegisterRouter.scala:87:24] wire out_woready_1_1184; // @[RegisterRouter.scala:87:24] wire out_woready_1_1185; // @[RegisterRouter.scala:87:24] wire out_woready_1_1186; // @[RegisterRouter.scala:87:24] wire out_woready_1_1187; // @[RegisterRouter.scala:87:24] wire out_woready_1_1188; // @[RegisterRouter.scala:87:24] wire out_woready_1_1189; // @[RegisterRouter.scala:87:24] wire out_woready_1_1190; // @[RegisterRouter.scala:87:24] wire out_woready_1_1191; // @[RegisterRouter.scala:87:24] wire out_woready_1_1192; // @[RegisterRouter.scala:87:24] wire out_woready_1_1193; // @[RegisterRouter.scala:87:24] wire out_woready_1_1194; // @[RegisterRouter.scala:87:24] wire out_woready_1_1195; // @[RegisterRouter.scala:87:24] wire out_woready_1_1196; // @[RegisterRouter.scala:87:24] wire out_woready_1_1197; // @[RegisterRouter.scala:87:24] wire out_woready_1_1198; // @[RegisterRouter.scala:87:24] wire out_woready_1_1199; // @[RegisterRouter.scala:87:24] wire out_woready_1_1200; // @[RegisterRouter.scala:87:24] wire out_woready_1_1201; // @[RegisterRouter.scala:87:24] wire out_woready_1_1202; // @[RegisterRouter.scala:87:24] wire out_woready_1_1203; // @[RegisterRouter.scala:87:24] wire out_woready_1_1204; // @[RegisterRouter.scala:87:24] wire out_woready_1_1205; // @[RegisterRouter.scala:87:24] wire out_woready_1_1206; // @[RegisterRouter.scala:87:24] wire out_woready_1_1207; // @[RegisterRouter.scala:87:24] wire out_woready_1_1208; // @[RegisterRouter.scala:87:24] wire out_woready_1_1209; // @[RegisterRouter.scala:87:24] wire out_woready_1_1210; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_8 = out_front_1_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_8 = out_front_1_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_9 = out_front_1_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_9 = out_front_1_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_10 = out_front_1_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_10 = out_front_1_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_11 = out_front_1_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_11 = out_front_1_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_12 = out_front_1_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_12 = out_front_1_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_13 = out_front_1_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_13 = out_front_1_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_14 = out_front_1_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_14 = out_front_1_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_15 = out_front_1_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_15 = out_front_1_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_16 = {8{_out_frontMask_T_8}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_17 = {8{_out_frontMask_T_9}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_18 = {8{_out_frontMask_T_10}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_19 = {8{_out_frontMask_T_11}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_20 = {8{_out_frontMask_T_12}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_21 = {8{_out_frontMask_T_13}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_22 = {8{_out_frontMask_T_14}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_23 = {8{_out_frontMask_T_15}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_lo = {_out_frontMask_T_17, _out_frontMask_T_16}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_hi = {_out_frontMask_T_19, _out_frontMask_T_18}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_lo_1 = {out_frontMask_lo_hi, out_frontMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_lo = {_out_frontMask_T_21, _out_frontMask_T_20}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_hi = {_out_frontMask_T_23, _out_frontMask_T_22}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_hi_1 = {out_frontMask_hi_hi, out_frontMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_frontMask_1 = {out_frontMask_hi_1, out_frontMask_lo_1}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_16 = {8{_out_backMask_T_8}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_17 = {8{_out_backMask_T_9}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_18 = {8{_out_backMask_T_10}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_19 = {8{_out_backMask_T_11}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_20 = {8{_out_backMask_T_12}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_21 = {8{_out_backMask_T_13}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_22 = {8{_out_backMask_T_14}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_23 = {8{_out_backMask_T_15}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_lo = {_out_backMask_T_17, _out_backMask_T_16}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_hi = {_out_backMask_T_19, _out_backMask_T_18}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_lo_1 = {out_backMask_lo_hi, out_backMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_lo = {_out_backMask_T_21, _out_backMask_T_20}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_hi = {_out_backMask_T_23, _out_backMask_T_22}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_hi_1 = {out_backMask_hi_hi, out_backMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_backMask_1 = {out_backMask_hi_1, out_backMask_lo_1}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_146 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_146 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_154 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_154 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_162 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_162 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_170 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_170 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_178 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_178 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_186 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_186 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_194 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_194 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_202 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_202 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_210 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_210 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_218 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_218 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_226 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_226 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_234 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_234 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_242 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_242 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_250 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_250 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_258 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_258 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_266 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_266 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_274 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_274 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_282 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_282 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_290 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_290 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_298 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_298 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_306 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_306 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_314 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_314 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_322 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_322 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_330 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_330 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_338 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_338 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_346 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_346 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_354 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_354 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_362 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_362 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_370 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_370 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_378 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_378 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_386 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_386 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_394 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_394 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_402 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_402 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_410 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_410 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_418 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_418 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_426 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_426 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_434 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_434 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_442 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_442 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_450 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_450 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_458 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_458 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_466 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_466 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_474 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_474 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_482 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_482 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_490 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_490 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_500 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_500 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_508 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_508 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_516 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_516 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_524 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_524 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_532 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_532 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_540 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_540 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_548 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_548 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_556 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_556 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_564 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_564 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_572 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_572 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_580 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_580 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_589 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_589 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_597 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_597 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_605 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_605 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_613 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_613 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_621 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_621 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_629 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_629 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_633 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_633 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_641 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_641 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_649 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_649 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_657 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_657 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_665 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_665 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_673 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_673 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_683 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_683 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_691 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_691 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_699 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_699 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_707 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_707 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_715 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_715 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_723 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_723 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_731 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_731 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_739 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_739 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_747 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_747 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_755 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_755 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_763 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_763 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_771 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_771 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_779 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_779 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_787 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_787 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_795 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_795 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_803 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_803 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_811 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_811 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_819 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_819 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_827 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_827 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_835 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_835 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_845 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_845 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_853 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_853 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_861 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_861 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_869 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_869 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_877 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_877 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_885 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_885 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_893 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_893 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_901 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_901 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_909 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_909 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_917 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_917 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_925 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_925 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_933 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_933 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_941 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_941 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_949 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_949 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_957 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_957 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_965 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_965 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_973 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_973 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_981 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_981 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_989 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_989 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_997 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_997 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1005 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1005 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1013 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1013 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1021 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1021 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1029 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1029 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1037 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1037 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1045 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1045 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1053 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1053 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1061 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1061 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1069 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1069 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1077 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1077 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1085 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1085 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1093 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1093 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1101 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1101 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1109 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1109 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1117 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1117 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1125 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1125 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1133 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1133 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1141 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1141 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1149 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1149 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1157 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1157 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1165 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1165 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1173 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1173 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1181 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1181 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1189 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1189 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1197 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1197 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1205 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1205 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1213 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1213 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1221 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1221 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1229 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1229 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1237 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1237 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1245 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1245 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1253 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1253 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1261 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1261 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1269 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1269 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1277 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1277 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1285 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1285 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1293 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1293 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1301 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1301 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1309 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1309 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1317 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1317 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1325 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1325 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1333 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1333 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1341 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1341 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1349 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1349 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire out_rimask_146 = |_out_rimask_T_146; // @[RegisterRouter.scala:87:24] wire out_wimask_146 = &_out_wimask_T_146; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_146 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_146 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_154 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_154 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_162 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_162 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_170 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_170 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_178 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_178 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_186 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_186 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_194 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_194 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_202 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_202 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_210 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_210 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_218 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_218 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_226 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_226 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_234 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_234 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_242 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_242 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_250 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_250 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_258 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_258 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_266 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_266 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_274 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_274 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_282 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_282 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_290 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_290 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_298 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_298 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_306 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_306 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_314 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_314 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_322 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_322 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_330 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_330 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_338 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_338 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_346 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_346 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_354 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_354 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_362 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_362 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_370 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_370 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_378 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_378 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_386 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_386 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_394 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_394 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_402 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_402 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_410 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_410 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_418 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_418 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_426 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_426 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_434 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_434 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_442 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_442 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_450 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_450 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_458 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_458 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_466 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_466 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_474 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_474 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_482 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_482 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_490 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_490 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_500 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_500 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_508 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_508 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_516 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_516 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_524 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_524 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_532 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_532 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_540 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_540 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_548 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_548 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_556 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_556 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_564 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_564 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_572 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_572 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_580 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_580 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_589 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_589 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_597 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_597 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_605 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_605 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_613 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_613 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_621 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_621 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_629 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_629 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_633 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_633 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_641 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_641 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_649 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_649 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_657 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_657 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_665 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_665 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_673 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_673 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_683 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_683 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_691 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_691 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_699 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_699 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_707 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_707 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_715 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_715 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_723 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_723 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_731 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_731 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_739 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_739 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_747 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_747 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_755 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_755 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_763 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_763 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_771 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_771 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_779 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_779 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_787 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_787 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_795 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_795 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_803 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_803 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_811 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_811 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_819 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_819 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_827 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_827 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_835 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_835 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_845 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_845 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_853 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_853 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_861 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_861 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_869 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_869 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_877 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_877 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_885 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_885 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_893 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_893 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_901 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_901 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_909 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_909 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_917 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_917 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_925 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_925 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_933 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_933 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_941 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_941 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_949 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_949 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_957 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_957 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_965 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_965 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_973 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_973 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_981 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_981 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_989 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_989 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_997 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_997 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1005 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1005 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1013 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1013 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1021 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1021 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1029 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1029 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1037 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1037 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1045 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1045 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1053 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1053 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1061 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1061 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1069 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1069 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1077 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1077 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1085 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1085 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1093 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1093 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1101 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1101 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1109 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1109 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1117 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1117 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1125 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1125 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1133 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1133 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1141 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1141 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1149 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1149 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1157 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1157 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1165 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1165 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1173 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1173 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1181 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1181 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1189 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1189 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1197 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1197 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1205 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1205 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1213 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1213 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1221 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1221 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1229 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1229 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1237 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1237 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1245 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1245 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1253 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1253 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1261 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1261 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1269 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1269 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1277 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1277 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1285 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1285 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1293 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1293 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1301 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1301 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1309 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1309 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1317 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1317 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1325 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1325 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1333 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1333 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1341 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1341 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1349 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1349 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire out_romask_146 = |_out_romask_T_146; // @[RegisterRouter.scala:87:24] wire out_womask_146 = &_out_womask_T_146; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_146 = out_rivalid_1_0 & out_rimask_146; // @[RegisterRouter.scala:87:24] wire _out_T_1911 = out_f_rivalid_146; // @[RegisterRouter.scala:87:24] wire out_f_roready_146 = out_roready_1_0 & out_romask_146; // @[RegisterRouter.scala:87:24] wire _out_T_1912 = out_f_roready_146; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_146 = out_wivalid_1_0 & out_wimask_146; // @[RegisterRouter.scala:87:24] wire out_f_woready_146 = out_woready_1_0 & out_womask_146; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1910 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1982 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2054 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2126 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2198 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2286 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2358 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2430 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2502 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2574 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2646 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2718 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2790 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2862 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2934 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3022 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3094 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3166 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3238 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3310 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3382 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3454 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3526 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3598 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3670 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3758 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3830 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3902 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3974 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4046 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4118 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4190 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4262 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4334 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4406 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4478 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4550 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4622 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4694 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4766 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4838 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4910 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4982 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5054 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5144 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5216 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5288 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5360 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5432 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5504 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5576 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5648 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5720 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5792 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5864 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5945 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6033 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6105 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6177 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6249 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6321 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6357 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6429 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6501 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6573 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6661 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6733 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6823 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6895 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6967 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7039 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7111 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7183 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7255 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7327 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7399 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7471 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7543 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7615 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7687 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7759 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7831 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7903 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7991 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8063 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8135 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8207 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8297 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8369 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8441 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8513 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8585 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8673 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8745 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8817 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8889 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8961 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9033 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9105 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9177 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9249 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9321 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9393 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9465 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9553 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9625 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9697 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9769 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9841 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9913 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9985 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10057 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10129 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10201 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10273 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10345 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10417 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10505 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10577 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10649 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10721 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10793 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10865 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10953 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11025 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11097 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11169 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11241 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11313 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11385 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11457 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11529 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11601 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11673 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11745 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11817 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11889 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11977 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12049 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12121 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12193 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12265 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12337 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12409 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12481 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12553 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12641 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12713 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12785 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12857 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12929 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire _out_T_1913 = ~out_rimask_146; // @[RegisterRouter.scala:87:24] wire _out_T_1914 = ~out_wimask_146; // @[RegisterRouter.scala:87:24] wire _out_T_1915 = ~out_romask_146; // @[RegisterRouter.scala:87:24] wire _out_T_1916 = ~out_womask_146; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1918 = _out_T_1917; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_112 = _out_T_1918; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_147 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_147 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_155 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_155 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_163 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_163 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_171 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_171 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_179 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_179 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_187 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_187 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_195 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_195 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_203 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_203 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_211 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_211 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_219 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_219 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_227 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_227 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_235 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_235 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_243 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_243 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_251 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_251 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_259 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_259 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_267 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_267 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_275 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_275 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_283 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_283 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_291 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_291 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_299 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_299 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_307 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_307 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_315 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_315 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_323 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_323 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_331 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_331 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_339 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_339 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_347 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_347 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_355 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_355 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_363 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_363 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_371 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_371 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_379 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_379 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_387 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_387 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_395 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_395 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_403 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_403 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_411 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_411 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_419 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_419 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_427 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_427 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_435 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_435 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_443 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_443 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_451 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_451 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_459 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_459 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_467 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_467 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_475 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_475 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_483 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_483 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_491 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_491 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_501 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_501 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_509 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_509 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_517 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_517 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_525 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_525 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_533 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_533 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_541 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_541 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_549 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_549 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_557 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_557 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_565 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_565 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_573 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_573 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_581 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_581 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_590 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_590 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_598 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_598 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_606 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_606 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_614 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_614 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_622 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_622 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_630 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_630 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_634 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_634 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_642 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_642 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_650 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_650 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_658 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_658 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_666 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_666 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_674 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_674 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_684 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_684 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_692 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_692 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_700 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_700 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_708 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_708 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_716 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_716 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_724 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_724 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_732 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_732 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_740 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_740 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_748 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_748 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_756 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_756 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_764 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_764 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_772 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_772 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_780 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_780 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_788 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_788 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_796 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_796 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_804 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_804 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_812 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_812 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_820 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_820 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_828 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_828 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_836 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_836 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_846 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_846 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_854 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_854 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_862 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_862 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_870 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_870 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_878 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_878 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_886 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_886 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_894 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_894 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_902 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_902 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_910 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_910 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_918 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_918 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_926 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_926 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_934 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_934 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_942 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_942 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_950 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_950 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_958 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_958 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_966 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_966 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_974 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_974 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_982 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_982 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_990 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_990 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_998 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_998 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1006 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1006 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1014 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1014 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1022 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1022 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1030 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1030 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1038 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1038 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1046 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1046 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1054 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1054 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1062 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1062 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1070 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1070 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1078 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1078 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1086 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1086 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1094 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1094 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1102 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1102 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1110 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1110 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1118 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1118 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1126 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1126 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1134 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1134 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1142 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1142 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1150 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1150 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1158 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1158 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1166 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1166 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1174 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1174 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1182 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1182 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1190 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1190 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1198 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1198 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1206 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1206 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1214 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1214 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1222 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1222 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1230 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1230 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1238 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1238 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1246 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1246 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1254 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1254 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1262 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1262 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1270 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1270 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1278 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1278 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1286 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1286 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1294 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1294 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1302 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1302 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1310 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1310 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1318 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1318 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1326 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1326 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1334 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1334 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1342 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1342 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1350 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1350 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire out_rimask_147 = |_out_rimask_T_147; // @[RegisterRouter.scala:87:24] wire out_wimask_147 = &_out_wimask_T_147; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_147 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_147 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_155 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_155 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_163 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_163 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_171 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_171 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_179 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_179 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_187 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_187 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_195 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_195 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_203 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_203 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_211 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_211 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_219 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_219 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_227 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_227 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_235 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_235 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_243 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_243 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_251 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_251 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_259 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_259 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_267 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_267 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_275 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_275 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_283 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_283 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_291 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_291 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_299 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_299 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_307 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_307 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_315 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_315 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_323 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_323 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_331 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_331 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_339 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_339 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_347 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_347 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_355 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_355 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_363 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_363 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_371 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_371 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_379 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_379 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_387 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_387 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_395 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_395 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_403 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_403 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_411 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_411 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_419 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_419 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_427 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_427 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_435 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_435 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_443 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_443 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_451 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_451 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_459 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_459 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_467 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_467 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_475 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_475 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_483 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_483 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_491 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_491 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_501 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_501 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_509 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_509 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_517 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_517 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_525 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_525 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_533 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_533 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_541 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_541 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_549 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_549 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_557 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_557 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_565 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_565 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_573 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_573 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_581 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_581 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_590 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_590 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_598 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_598 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_606 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_606 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_614 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_614 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_622 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_622 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_630 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_630 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_634 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_634 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_642 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_642 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_650 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_650 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_658 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_658 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_666 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_666 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_674 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_674 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_684 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_684 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_692 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_692 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_700 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_700 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_708 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_708 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_716 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_716 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_724 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_724 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_732 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_732 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_740 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_740 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_748 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_748 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_756 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_756 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_764 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_764 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_772 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_772 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_780 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_780 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_788 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_788 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_796 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_796 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_804 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_804 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_812 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_812 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_820 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_820 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_828 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_828 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_836 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_836 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_846 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_846 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_854 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_854 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_862 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_862 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_870 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_870 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_878 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_878 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_886 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_886 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_894 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_894 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_902 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_902 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_910 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_910 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_918 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_918 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_926 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_926 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_934 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_934 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_942 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_942 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_950 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_950 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_958 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_958 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_966 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_966 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_974 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_974 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_982 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_982 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_990 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_990 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_998 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_998 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1006 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1006 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1014 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1014 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1022 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1022 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1030 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1030 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1038 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1038 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1046 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1046 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1054 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1054 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1062 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1062 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1070 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1070 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1078 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1078 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1086 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1086 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1094 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1094 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1102 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1102 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1110 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1110 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1118 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1118 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1126 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1126 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1134 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1134 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1142 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1142 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1150 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1150 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1158 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1158 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1166 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1166 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1174 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1174 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1182 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1182 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1190 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1190 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1198 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1198 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1206 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1206 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1214 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1214 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1222 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1222 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1230 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1230 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1238 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1238 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1246 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1246 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1254 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1254 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1262 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1262 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1270 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1270 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1278 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1278 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1286 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1286 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1294 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1294 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1302 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1302 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1310 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1310 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1318 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1318 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1326 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1326 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1334 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1334 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1342 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1342 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1350 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1350 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire out_romask_147 = |_out_romask_T_147; // @[RegisterRouter.scala:87:24] wire out_womask_147 = &_out_womask_T_147; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_147 = out_rivalid_1_1 & out_rimask_147; // @[RegisterRouter.scala:87:24] wire _out_T_1920 = out_f_rivalid_147; // @[RegisterRouter.scala:87:24] wire out_f_roready_147 = out_roready_1_1 & out_romask_147; // @[RegisterRouter.scala:87:24] wire _out_T_1921 = out_f_roready_147; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_147 = out_wivalid_1_1 & out_wimask_147; // @[RegisterRouter.scala:87:24] wire out_f_woready_147 = out_woready_1_1 & out_womask_147; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1919 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1991 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2063 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2135 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2209 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2295 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2367 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2439 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2511 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2583 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2655 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2727 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2799 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2871 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2945 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3031 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3103 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3175 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3247 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3319 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3391 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3463 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3535 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3607 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3681 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3767 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3839 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3911 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3983 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4055 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4127 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4199 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4271 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4343 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4415 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4487 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4559 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4631 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4703 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4775 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4847 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4919 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4991 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5063 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5153 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5225 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5297 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5369 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5441 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5513 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5585 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5657 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5729 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5801 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5873 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5956 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6042 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6114 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6186 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6258 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6330 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6366 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6438 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6510 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6584 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6670 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6742 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6832 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6904 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6976 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7048 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7120 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7192 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7264 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7336 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7408 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7480 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7552 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7624 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7696 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7768 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7840 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7914 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8000 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8072 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8144 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8216 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8306 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8378 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8450 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8522 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8596 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8682 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8754 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8826 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8898 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8970 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9042 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9114 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9186 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9258 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9330 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9402 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9476 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9562 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9634 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9706 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9778 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9850 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9922 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9994 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10066 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10138 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10210 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10282 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10354 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10428 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10514 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10586 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10658 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10730 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10802 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10876 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10962 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11034 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11106 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11178 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11250 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11322 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11394 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11466 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11538 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11610 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11682 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11754 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11826 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11900 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11986 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12058 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12130 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12202 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12274 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12346 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12418 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12490 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12564 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12650 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12722 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12794 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12866 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12938 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire _out_T_1922 = ~out_rimask_147; // @[RegisterRouter.scala:87:24] wire _out_T_1923 = ~out_wimask_147; // @[RegisterRouter.scala:87:24] wire _out_T_1924 = ~out_romask_147; // @[RegisterRouter.scala:87:24] wire _out_T_1925 = ~out_womask_147; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_112 = {hi_82, flags_0_go, _out_prepend_T_112}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1926 = out_prepend_112; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1927 = _out_T_1926; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_113 = _out_T_1927; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_148 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_148 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_156 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_156 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_164 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_164 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_172 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_172 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_180 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_180 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_188 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_188 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_196 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_196 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_204 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_204 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_212 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_212 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_220 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_220 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_228 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_228 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_236 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_236 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_244 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_244 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_252 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_252 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_260 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_260 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_268 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_268 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_276 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_276 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_284 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_284 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_292 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_292 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_300 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_300 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_308 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_308 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_316 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_316 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_324 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_324 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_332 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_332 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_340 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_340 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_348 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_348 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_356 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_356 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_364 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_364 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_372 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_372 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_380 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_380 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_388 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_388 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_396 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_396 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_404 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_404 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_412 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_412 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_420 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_420 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_428 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_428 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_436 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_436 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_444 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_444 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_452 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_452 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_460 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_460 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_468 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_468 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_476 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_476 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_484 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_484 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_492 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_492 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_502 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_502 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_510 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_510 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_518 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_518 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_526 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_526 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_534 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_534 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_542 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_542 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_550 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_550 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_558 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_558 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_566 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_566 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_574 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_574 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_582 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_582 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_591 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_591 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_599 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_599 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_607 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_607 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_615 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_615 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_623 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_623 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_631 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_631 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_635 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_635 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_643 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_643 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_651 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_651 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_659 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_659 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_667 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_667 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_675 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_675 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_685 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_685 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_693 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_693 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_701 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_701 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_709 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_709 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_717 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_717 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_725 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_725 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_733 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_733 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_741 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_741 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_749 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_749 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_757 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_757 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_765 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_765 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_773 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_773 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_781 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_781 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_789 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_789 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_797 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_797 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_805 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_805 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_813 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_813 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_821 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_821 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_829 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_829 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_837 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_837 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_847 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_847 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_855 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_855 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_863 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_863 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_871 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_871 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_879 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_879 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_887 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_887 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_895 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_895 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_903 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_903 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_911 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_911 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_919 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_919 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_927 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_927 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_935 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_935 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_943 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_943 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_951 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_951 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_959 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_959 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_967 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_967 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_975 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_975 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_983 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_983 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_991 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_991 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_999 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_999 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1007 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1007 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1015 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1015 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1023 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1023 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1031 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1031 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1039 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1039 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1047 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1047 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1055 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1055 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1063 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1063 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1071 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1071 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1079 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1079 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1087 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1087 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1095 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1095 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1103 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1103 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1111 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1111 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1119 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1119 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1127 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1127 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1135 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1135 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1143 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1143 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1151 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1151 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1159 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1159 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1167 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1167 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1175 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1175 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1183 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1183 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1191 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1191 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1199 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1199 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1207 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1207 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1215 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1215 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1223 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1223 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1231 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1231 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1239 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1239 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1247 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1247 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1255 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1255 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1263 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1263 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1271 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1271 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1279 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1279 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1287 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1287 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1295 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1295 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1303 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1303 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1311 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1311 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1319 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1319 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1327 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1327 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1335 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1335 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1343 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1343 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1351 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1351 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire out_rimask_148 = |_out_rimask_T_148; // @[RegisterRouter.scala:87:24] wire out_wimask_148 = &_out_wimask_T_148; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_148 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_148 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_156 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_156 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_164 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_164 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_172 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_172 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_180 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_180 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_188 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_188 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_196 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_196 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_204 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_204 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_212 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_212 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_220 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_220 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_228 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_228 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_236 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_236 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_244 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_244 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_252 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_252 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_260 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_260 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_268 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_268 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_276 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_276 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_284 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_284 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_292 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_292 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_300 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_300 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_308 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_308 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_316 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_316 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_324 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_324 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_332 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_332 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_340 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_340 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_348 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_348 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_356 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_356 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_364 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_364 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_372 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_372 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_380 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_380 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_388 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_388 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_396 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_396 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_404 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_404 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_412 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_412 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_420 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_420 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_428 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_428 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_436 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_436 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_444 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_444 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_452 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_452 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_460 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_460 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_468 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_468 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_476 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_476 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_484 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_484 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_492 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_492 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_502 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_502 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_510 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_510 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_518 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_518 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_526 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_526 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_534 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_534 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_542 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_542 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_550 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_550 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_558 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_558 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_566 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_566 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_574 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_574 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_582 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_582 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_591 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_591 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_599 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_599 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_607 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_607 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_615 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_615 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_623 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_623 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_631 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_631 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_635 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_635 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_643 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_643 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_651 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_651 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_659 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_659 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_667 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_667 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_675 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_675 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_685 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_685 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_693 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_693 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_701 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_701 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_709 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_709 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_717 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_717 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_725 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_725 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_733 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_733 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_741 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_741 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_749 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_749 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_757 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_757 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_765 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_765 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_773 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_773 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_781 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_781 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_789 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_789 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_797 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_797 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_805 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_805 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_813 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_813 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_821 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_821 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_829 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_829 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_837 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_837 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_847 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_847 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_855 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_855 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_863 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_863 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_871 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_871 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_879 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_879 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_887 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_887 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_895 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_895 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_903 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_903 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_911 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_911 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_919 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_919 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_927 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_927 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_935 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_935 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_943 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_943 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_951 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_951 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_959 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_959 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_967 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_967 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_975 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_975 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_983 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_983 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_991 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_991 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_999 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_999 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1007 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1007 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1015 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1015 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1023 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1023 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1031 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1031 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1039 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1039 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1047 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1047 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1055 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1055 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1063 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1063 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1071 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1071 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1079 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1079 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1087 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1087 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1095 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1095 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1103 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1103 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1111 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1111 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1119 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1119 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1127 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1127 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1135 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1135 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1143 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1143 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1151 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1151 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1159 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1159 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1167 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1167 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1175 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1175 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1183 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1183 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1191 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1191 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1199 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1199 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1207 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1207 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1215 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1215 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1223 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1223 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1231 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1231 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1239 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1239 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1247 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1247 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1255 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1255 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1263 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1263 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1271 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1271 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1279 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1279 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1287 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1287 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1295 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1295 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1303 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1303 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1311 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1311 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1319 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1319 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1327 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1327 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1335 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1335 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1343 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1343 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1351 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1351 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire out_romask_148 = |_out_romask_T_148; // @[RegisterRouter.scala:87:24] wire out_womask_148 = &_out_womask_T_148; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_148 = out_rivalid_1_2 & out_rimask_148; // @[RegisterRouter.scala:87:24] wire _out_T_1929 = out_f_rivalid_148; // @[RegisterRouter.scala:87:24] wire out_f_roready_148 = out_roready_1_2 & out_romask_148; // @[RegisterRouter.scala:87:24] wire _out_T_1930 = out_f_roready_148; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_148 = out_wivalid_1_2 & out_wimask_148; // @[RegisterRouter.scala:87:24] wire out_f_woready_148 = out_woready_1_2 & out_womask_148; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1928 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2000 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2072 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2144 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2220 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2304 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2376 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2448 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2520 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2592 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2664 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2736 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2808 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2880 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2956 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3040 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3112 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3184 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3256 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3328 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3400 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3472 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3544 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3616 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3692 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3776 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3848 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3920 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3992 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4064 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4136 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4208 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4280 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4352 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4424 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4496 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4568 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4640 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4712 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4784 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4856 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4928 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5000 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5072 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5162 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5234 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5306 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5378 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5450 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5522 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5594 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5666 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5738 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5810 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5882 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5967 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6051 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6123 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6195 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6267 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6339 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6375 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6447 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6519 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6595 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6679 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6751 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6841 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6913 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6985 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7057 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7129 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7201 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7273 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7345 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7417 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7489 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7561 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7633 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7705 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7777 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7849 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7925 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8009 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8081 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8153 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8225 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8315 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8387 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8459 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8531 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8607 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8691 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8763 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8835 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8907 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8979 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9051 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9123 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9195 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9267 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9339 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9411 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9487 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9571 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9643 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9715 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9787 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9859 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9931 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10003 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10075 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10147 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10219 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10291 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10363 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10439 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10523 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10595 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10667 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10739 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10811 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10887 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10971 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11043 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11115 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11187 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11259 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11331 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11403 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11475 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11547 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11619 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11691 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11763 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11835 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11911 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11995 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12067 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12139 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12211 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12283 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12355 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12427 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12499 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12575 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12659 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12731 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12803 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12875 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12947 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire _out_T_1931 = ~out_rimask_148; // @[RegisterRouter.scala:87:24] wire _out_T_1932 = ~out_wimask_148; // @[RegisterRouter.scala:87:24] wire _out_T_1933 = ~out_romask_148; // @[RegisterRouter.scala:87:24] wire _out_T_1934 = ~out_womask_148; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_113 = {hi_83, flags_0_go, _out_prepend_T_113}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1935 = out_prepend_113; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1936 = _out_T_1935; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_114 = _out_T_1936; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_149 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_149 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_157 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_157 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_165 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_165 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_173 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_173 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_181 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_181 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_189 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_189 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_197 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_197 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_205 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_205 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_213 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_213 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_221 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_221 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_229 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_229 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_237 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_237 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_245 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_245 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_253 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_253 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_261 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_261 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_269 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_269 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_277 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_277 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_285 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_285 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_293 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_293 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_301 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_301 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_309 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_309 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_317 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_317 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_325 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_325 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_333 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_333 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_341 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_341 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_349 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_349 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_357 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_357 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_365 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_365 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_373 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_373 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_381 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_381 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_389 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_389 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_397 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_397 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_405 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_405 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_413 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_413 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_421 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_421 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_429 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_429 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_437 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_437 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_445 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_445 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_453 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_453 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_461 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_461 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_469 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_469 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_477 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_477 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_485 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_485 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_493 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_493 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_503 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_503 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_511 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_511 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_519 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_519 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_527 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_527 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_535 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_535 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_543 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_543 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_551 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_551 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_559 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_559 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_567 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_567 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_575 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_575 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_583 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_583 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_592 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_592 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_600 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_600 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_608 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_608 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_616 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_616 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_624 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_624 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_632 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_632 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_636 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_636 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_644 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_644 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_652 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_652 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_660 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_660 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_668 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_668 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_676 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_676 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_686 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_686 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_694 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_694 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_702 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_702 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_710 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_710 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_718 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_718 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_726 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_726 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_734 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_734 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_742 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_742 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_750 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_750 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_758 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_758 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_766 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_766 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_774 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_774 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_782 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_782 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_790 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_790 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_798 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_798 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_806 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_806 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_814 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_814 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_822 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_822 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_830 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_830 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_838 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_838 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_848 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_848 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_856 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_856 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_864 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_864 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_872 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_872 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_880 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_880 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_888 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_888 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_896 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_896 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_904 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_904 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_912 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_912 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_920 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_920 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_928 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_928 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_936 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_936 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_944 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_944 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_952 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_952 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_960 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_960 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_968 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_968 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_976 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_976 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_984 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_984 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_992 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_992 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1000 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1000 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1008 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1008 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1016 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1016 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1024 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1024 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1032 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1032 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1040 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1040 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1048 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1048 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1056 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1056 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1064 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1064 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1072 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1072 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1080 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1080 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1088 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1088 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1096 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1096 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1104 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1104 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1112 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1112 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1120 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1120 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1128 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1128 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1136 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1136 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1144 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1144 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1152 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1152 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1160 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1160 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1168 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1168 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1176 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1176 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1184 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1184 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1192 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1192 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1200 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1200 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1208 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1208 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1216 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1216 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1224 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1224 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1232 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1232 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1240 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1240 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1248 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1248 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1256 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1256 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1264 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1264 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1272 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1272 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1280 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1280 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1288 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1288 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1296 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1296 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1304 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1304 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1312 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1312 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1320 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1320 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1328 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1328 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1336 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1336 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1344 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1344 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1352 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1352 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire out_rimask_149 = |_out_rimask_T_149; // @[RegisterRouter.scala:87:24] wire out_wimask_149 = &_out_wimask_T_149; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_149 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_149 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_157 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_157 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_165 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_165 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_173 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_173 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_181 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_181 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_189 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_189 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_197 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_197 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_205 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_205 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_213 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_213 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_221 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_221 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_229 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_229 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_237 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_237 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_245 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_245 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_253 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_253 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_261 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_261 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_269 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_269 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_277 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_277 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_285 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_285 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_293 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_293 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_301 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_301 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_309 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_309 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_317 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_317 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_325 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_325 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_333 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_333 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_341 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_341 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_349 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_349 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_357 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_357 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_365 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_365 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_373 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_373 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_381 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_381 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_389 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_389 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_397 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_397 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_405 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_405 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_413 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_413 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_421 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_421 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_429 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_429 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_437 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_437 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_445 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_445 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_453 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_453 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_461 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_461 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_469 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_469 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_477 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_477 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_485 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_485 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_493 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_493 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_503 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_503 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_511 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_511 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_519 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_519 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_527 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_527 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_535 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_535 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_543 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_543 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_551 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_551 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_559 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_559 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_567 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_567 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_575 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_575 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_583 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_583 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_592 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_592 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_600 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_600 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_608 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_608 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_616 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_616 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_624 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_624 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_632 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_632 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_636 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_636 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_644 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_644 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_652 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_652 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_660 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_660 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_668 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_668 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_676 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_676 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_686 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_686 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_694 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_694 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_702 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_702 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_710 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_710 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_718 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_718 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_726 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_726 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_734 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_734 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_742 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_742 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_750 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_750 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_758 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_758 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_766 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_766 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_774 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_774 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_782 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_782 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_790 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_790 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_798 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_798 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_806 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_806 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_814 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_814 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_822 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_822 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_830 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_830 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_838 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_838 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_848 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_848 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_856 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_856 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_864 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_864 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_872 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_872 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_880 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_880 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_888 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_888 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_896 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_896 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_904 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_904 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_912 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_912 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_920 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_920 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_928 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_928 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_936 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_936 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_944 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_944 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_952 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_952 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_960 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_960 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_968 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_968 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_976 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_976 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_984 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_984 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_992 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_992 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1000 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1000 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1008 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1008 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1016 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1016 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1024 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1024 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1032 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1032 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1040 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1040 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1048 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1048 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1056 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1056 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1064 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1064 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1072 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1072 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1080 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1080 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1088 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1088 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1096 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1096 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1104 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1104 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1112 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1112 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1120 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1120 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1128 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1128 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1136 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1136 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1144 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1144 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1152 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1152 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1160 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1160 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1168 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1168 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1176 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1176 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1184 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1184 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1192 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1192 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1200 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1200 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1208 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1208 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1216 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1216 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1224 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1224 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1232 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1232 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1240 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1240 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1248 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1248 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1256 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1256 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1264 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1264 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1272 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1272 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1280 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1280 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1288 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1288 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1296 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1296 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1304 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1304 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1312 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1312 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1320 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1320 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1328 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1328 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1336 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1336 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1344 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1344 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1352 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1352 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire out_romask_149 = |_out_romask_T_149; // @[RegisterRouter.scala:87:24] wire out_womask_149 = &_out_womask_T_149; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_149 = out_rivalid_1_3 & out_rimask_149; // @[RegisterRouter.scala:87:24] wire _out_T_1938 = out_f_rivalid_149; // @[RegisterRouter.scala:87:24] wire out_f_roready_149 = out_roready_1_3 & out_romask_149; // @[RegisterRouter.scala:87:24] wire _out_T_1939 = out_f_roready_149; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_149 = out_wivalid_1_3 & out_wimask_149; // @[RegisterRouter.scala:87:24] wire out_f_woready_149 = out_woready_1_3 & out_womask_149; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1937 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2009 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2081 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2153 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2231 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2313 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2385 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2457 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2529 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2601 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2673 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2745 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2817 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2889 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2967 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3049 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3121 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3193 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3265 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3337 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3409 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3481 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3553 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3625 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3703 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3785 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3857 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3929 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4001 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4073 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4145 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4217 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4289 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4361 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4433 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4505 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4577 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4649 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4721 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4793 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4865 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4937 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5009 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5081 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5171 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5243 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5315 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5387 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5459 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5531 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5603 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5675 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5747 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5819 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5891 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5978 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6060 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6132 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6204 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6276 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6348 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6384 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6456 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6528 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6606 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6688 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6760 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6850 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6922 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6994 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7066 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7138 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7210 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7282 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7354 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7426 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7498 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7570 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7642 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7714 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7786 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7858 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7936 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8018 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8090 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8162 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8234 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8324 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8396 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8468 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8540 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8618 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8700 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8772 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8844 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8916 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8988 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9060 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9132 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9204 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9276 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9348 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9420 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9498 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9580 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9652 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9724 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9796 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9868 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9940 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10012 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10084 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10156 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10228 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10300 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10372 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10450 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10532 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10604 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10676 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10748 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10820 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10898 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10980 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11052 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11124 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11196 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11268 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11340 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11412 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11484 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11556 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11628 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11700 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11772 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11844 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11922 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12004 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12076 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12148 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12220 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12292 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12364 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12436 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12508 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12586 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12668 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12740 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12812 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12884 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12956 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire _out_T_1940 = ~out_rimask_149; // @[RegisterRouter.scala:87:24] wire _out_T_1941 = ~out_wimask_149; // @[RegisterRouter.scala:87:24] wire _out_T_1942 = ~out_romask_149; // @[RegisterRouter.scala:87:24] wire _out_T_1943 = ~out_womask_149; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_114 = {hi_84, flags_0_go, _out_prepend_T_114}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1944 = out_prepend_114; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1945 = _out_T_1944; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_115 = _out_T_1945; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_150 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_150 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_158 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_158 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_166 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_166 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_174 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_174 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_182 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_182 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_190 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_190 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_198 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_198 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_206 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_206 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_214 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_214 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_222 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_222 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_230 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_230 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_238 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_238 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_246 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_246 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_254 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_254 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_262 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_262 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_270 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_270 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_278 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_278 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_286 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_286 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_294 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_294 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_302 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_302 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_310 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_310 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_318 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_318 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_326 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_326 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_334 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_334 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_342 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_342 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_350 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_350 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_358 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_358 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_366 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_366 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_374 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_374 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_382 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_382 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_390 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_390 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_398 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_398 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_406 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_406 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_414 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_414 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_422 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_422 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_430 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_430 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_438 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_438 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_446 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_446 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_454 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_454 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_462 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_462 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_470 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_470 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_478 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_478 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_486 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_486 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_494 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_494 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_504 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_504 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_512 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_512 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_520 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_520 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_528 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_528 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_536 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_536 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_544 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_544 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_552 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_552 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_560 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_560 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_568 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_568 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_576 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_576 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_584 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_584 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_593 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_593 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_601 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_601 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_609 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_609 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_617 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_617 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_625 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_625 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_637 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_637 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_645 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_645 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_653 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_653 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_661 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_661 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_669 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_669 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_677 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_677 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_687 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_687 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_695 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_695 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_703 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_703 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_711 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_711 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_719 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_719 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_727 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_727 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_735 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_735 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_743 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_743 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_751 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_751 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_759 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_759 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_767 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_767 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_775 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_775 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_783 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_783 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_791 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_791 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_799 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_799 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_807 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_807 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_815 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_815 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_823 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_823 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_831 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_831 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_839 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_839 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_849 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_849 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_857 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_857 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_865 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_865 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_873 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_873 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_881 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_881 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_889 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_889 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_897 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_897 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_905 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_905 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_913 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_913 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_921 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_921 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_929 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_929 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_937 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_937 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_945 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_945 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_953 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_953 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_961 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_961 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_969 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_969 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_977 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_977 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_985 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_985 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_993 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_993 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1001 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1001 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1009 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1009 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1017 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1017 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1025 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1025 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1033 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1033 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1041 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1041 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1049 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1049 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1057 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1057 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1065 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1065 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1073 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1073 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1081 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1081 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1089 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1089 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1097 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1097 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1105 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1105 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1113 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1113 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1121 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1121 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1129 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1129 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1137 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1137 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1145 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1145 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1153 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1153 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1161 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1161 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1169 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1169 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1177 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1177 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1185 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1185 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1193 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1193 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1201 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1201 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1209 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1209 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1217 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1217 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1225 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1225 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1233 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1233 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1241 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1241 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1249 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1249 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1257 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1257 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1265 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1265 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1273 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1273 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1281 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1281 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1289 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1289 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1297 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1297 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1305 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1305 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1313 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1313 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1321 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1321 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1329 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1329 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1337 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1337 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1345 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1345 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1353 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1353 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire out_rimask_150 = |_out_rimask_T_150; // @[RegisterRouter.scala:87:24] wire out_wimask_150 = &_out_wimask_T_150; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_150 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_150 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_158 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_158 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_166 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_166 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_174 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_174 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_182 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_182 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_190 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_190 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_198 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_198 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_206 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_206 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_214 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_214 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_222 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_222 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_230 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_230 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_238 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_238 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_246 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_246 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_254 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_254 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_262 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_262 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_270 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_270 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_278 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_278 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_286 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_286 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_294 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_294 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_302 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_302 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_310 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_310 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_318 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_318 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_326 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_326 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_334 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_334 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_342 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_342 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_350 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_350 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_358 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_358 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_366 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_366 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_374 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_374 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_382 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_382 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_390 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_390 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_398 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_398 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_406 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_406 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_414 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_414 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_422 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_422 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_430 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_430 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_438 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_438 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_446 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_446 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_454 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_454 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_462 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_462 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_470 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_470 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_478 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_478 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_486 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_486 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_494 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_494 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_504 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_504 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_512 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_512 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_520 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_520 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_528 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_528 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_536 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_536 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_544 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_544 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_552 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_552 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_560 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_560 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_568 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_568 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_576 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_576 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_584 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_584 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_593 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_593 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_601 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_601 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_609 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_609 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_617 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_617 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_625 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_625 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_637 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_637 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_645 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_645 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_653 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_653 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_661 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_661 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_669 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_669 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_677 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_677 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_687 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_687 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_695 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_695 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_703 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_703 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_711 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_711 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_719 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_719 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_727 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_727 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_735 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_735 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_743 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_743 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_751 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_751 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_759 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_759 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_767 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_767 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_775 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_775 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_783 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_783 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_791 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_791 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_799 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_799 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_807 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_807 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_815 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_815 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_823 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_823 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_831 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_831 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_839 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_839 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_849 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_849 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_857 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_857 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_865 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_865 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_873 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_873 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_881 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_881 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_889 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_889 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_897 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_897 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_905 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_905 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_913 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_913 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_921 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_921 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_929 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_929 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_937 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_937 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_945 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_945 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_953 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_953 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_961 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_961 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_969 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_969 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_977 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_977 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_985 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_985 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_993 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_993 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1001 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1001 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1009 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1009 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1017 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1017 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1025 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1025 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1033 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1033 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1041 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1041 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1049 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1049 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1057 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1057 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1065 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1065 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1073 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1073 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1081 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1081 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1089 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1089 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1097 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1097 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1105 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1105 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1113 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1113 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1121 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1121 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1129 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1129 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1137 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1137 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1145 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1145 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1153 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1153 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1161 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1161 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1169 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1169 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1177 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1177 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1185 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1185 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1193 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1193 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1201 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1201 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1209 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1209 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1217 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1217 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1225 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1225 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1233 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1233 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1241 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1241 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1249 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1249 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1257 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1257 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1265 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1265 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1273 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1273 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1281 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1281 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1289 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1289 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1297 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1297 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1305 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1305 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1313 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1313 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1321 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1321 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1329 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1329 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1337 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1337 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1345 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1345 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1353 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1353 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire out_romask_150 = |_out_romask_T_150; // @[RegisterRouter.scala:87:24] wire out_womask_150 = &_out_womask_T_150; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_150 = out_rivalid_1_4 & out_rimask_150; // @[RegisterRouter.scala:87:24] wire _out_T_1947 = out_f_rivalid_150; // @[RegisterRouter.scala:87:24] wire out_f_roready_150 = out_roready_1_4 & out_romask_150; // @[RegisterRouter.scala:87:24] wire _out_T_1948 = out_f_roready_150; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_150 = out_wivalid_1_4 & out_wimask_150; // @[RegisterRouter.scala:87:24] wire out_f_woready_150 = out_woready_1_4 & out_womask_150; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1946 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2018 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2090 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2162 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2242 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2322 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2394 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2466 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2538 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2610 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2682 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2754 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2826 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2898 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2978 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3058 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3130 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3202 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3274 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3346 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3418 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3490 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3562 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3634 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3714 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3794 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3866 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3938 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4010 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4082 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4154 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4226 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4298 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4370 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4442 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4514 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4586 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4658 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4730 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4802 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4874 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4946 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5018 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5090 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5180 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5252 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5324 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5396 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5468 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5540 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5612 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5684 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5756 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5828 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5900 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5989 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6069 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6141 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6213 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6285 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6393 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6465 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6537 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6617 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6697 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6769 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6859 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6931 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7003 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7075 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7147 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7219 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7291 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7363 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7435 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7507 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7579 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7651 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7723 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7795 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7867 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7947 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8027 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8099 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8171 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8243 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8333 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8405 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8477 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8549 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8629 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8709 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8781 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8853 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8925 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8997 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9069 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9141 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9213 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9285 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9357 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9429 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9509 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9589 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9661 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9733 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9805 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9877 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9949 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10021 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10093 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10165 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10237 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10309 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10381 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10461 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10541 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10613 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10685 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10757 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10829 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10909 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10989 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11061 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11133 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11205 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11277 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11349 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11421 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11493 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11565 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11637 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11709 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11781 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11853 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11933 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12013 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12085 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12157 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12229 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12301 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12373 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12445 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12517 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12597 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12677 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12749 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12821 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12893 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12965 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire _out_T_1949 = ~out_rimask_150; // @[RegisterRouter.scala:87:24] wire _out_T_1950 = ~out_wimask_150; // @[RegisterRouter.scala:87:24] wire _out_T_1951 = ~out_romask_150; // @[RegisterRouter.scala:87:24] wire _out_T_1952 = ~out_womask_150; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_115 = {hi_85, flags_0_go, _out_prepend_T_115}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_1953 = out_prepend_115; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_1954 = _out_T_1953; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_116 = _out_T_1954; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_151 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_151 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_159 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_159 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_167 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_167 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_175 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_175 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_183 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_183 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_191 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_191 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_199 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_199 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_207 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_207 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_215 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_215 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_223 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_223 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_231 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_231 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_239 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_239 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_247 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_247 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_255 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_255 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_263 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_263 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_271 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_271 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_279 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_279 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_287 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_287 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_295 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_295 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_303 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_303 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_311 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_311 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_319 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_319 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_327 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_327 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_335 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_335 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_343 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_343 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_351 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_351 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_359 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_359 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_367 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_367 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_375 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_375 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_383 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_383 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_391 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_391 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_399 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_399 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_407 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_407 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_415 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_415 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_423 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_423 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_431 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_431 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_439 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_439 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_447 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_447 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_455 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_455 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_463 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_463 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_471 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_471 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_479 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_479 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_487 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_487 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_495 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_495 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_505 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_505 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_513 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_513 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_521 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_521 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_529 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_529 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_537 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_537 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_545 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_545 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_553 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_553 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_561 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_561 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_569 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_569 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_577 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_577 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_585 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_585 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_594 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_594 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_602 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_602 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_610 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_610 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_618 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_618 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_626 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_626 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_638 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_638 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_646 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_646 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_654 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_654 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_662 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_662 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_670 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_670 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_678 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_678 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_688 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_688 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_696 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_696 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_704 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_704 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_712 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_712 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_720 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_720 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_728 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_728 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_736 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_736 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_744 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_744 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_752 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_752 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_760 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_760 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_768 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_768 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_776 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_776 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_784 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_784 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_792 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_792 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_800 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_800 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_808 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_808 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_816 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_816 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_824 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_824 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_832 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_832 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_840 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_840 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_850 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_850 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_858 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_858 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_866 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_866 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_874 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_874 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_882 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_882 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_890 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_890 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_898 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_898 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_906 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_906 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_914 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_914 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_922 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_922 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_930 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_930 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_938 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_938 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_946 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_946 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_954 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_954 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_962 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_962 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_970 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_970 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_978 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_978 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_986 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_986 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_994 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_994 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1002 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1002 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1010 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1010 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1018 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1018 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1026 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1026 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1034 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1034 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1042 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1042 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1050 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1050 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1058 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1058 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1066 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1066 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1074 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1074 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1082 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1082 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1090 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1090 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1098 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1098 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1106 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1106 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1114 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1114 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1122 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1122 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1130 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1130 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1138 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1138 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1146 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1146 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1154 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1154 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1162 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1162 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1170 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1170 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1178 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1178 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1186 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1186 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1194 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1194 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1202 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1202 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1210 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1210 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1218 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1218 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1226 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1226 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1234 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1234 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1242 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1242 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1250 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1250 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1258 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1258 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1266 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1266 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1274 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1274 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1282 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1282 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1290 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1290 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1298 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1298 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1306 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1306 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1314 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1314 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1322 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1322 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1330 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1330 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1338 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1338 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1346 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1346 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1354 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1354 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire out_rimask_151 = |_out_rimask_T_151; // @[RegisterRouter.scala:87:24] wire out_wimask_151 = &_out_wimask_T_151; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_151 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_151 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_159 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_159 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_167 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_167 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_175 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_175 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_183 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_183 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_191 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_191 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_199 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_199 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_207 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_207 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_215 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_215 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_223 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_223 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_231 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_231 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_239 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_239 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_247 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_247 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_255 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_255 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_263 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_263 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_271 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_271 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_279 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_279 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_287 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_287 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_295 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_295 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_303 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_303 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_311 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_311 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_319 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_319 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_327 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_327 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_335 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_335 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_343 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_343 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_351 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_351 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_359 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_359 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_367 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_367 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_375 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_375 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_383 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_383 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_391 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_391 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_399 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_399 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_407 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_407 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_415 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_415 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_423 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_423 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_431 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_431 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_439 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_439 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_447 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_447 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_455 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_455 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_463 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_463 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_471 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_471 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_479 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_479 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_487 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_487 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_495 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_495 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_505 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_505 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_513 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_513 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_521 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_521 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_529 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_529 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_537 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_537 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_545 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_545 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_553 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_553 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_561 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_561 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_569 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_569 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_577 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_577 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_585 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_585 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_594 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_594 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_602 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_602 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_610 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_610 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_618 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_618 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_626 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_626 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_638 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_638 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_646 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_646 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_654 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_654 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_662 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_662 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_670 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_670 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_678 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_678 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_688 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_688 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_696 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_696 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_704 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_704 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_712 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_712 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_720 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_720 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_728 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_728 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_736 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_736 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_744 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_744 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_752 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_752 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_760 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_760 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_768 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_768 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_776 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_776 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_784 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_784 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_792 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_792 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_800 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_800 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_808 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_808 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_816 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_816 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_824 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_824 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_832 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_832 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_840 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_840 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_850 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_850 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_858 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_858 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_866 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_866 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_874 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_874 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_882 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_882 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_890 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_890 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_898 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_898 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_906 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_906 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_914 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_914 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_922 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_922 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_930 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_930 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_938 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_938 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_946 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_946 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_954 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_954 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_962 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_962 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_970 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_970 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_978 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_978 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_986 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_986 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_994 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_994 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1002 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1002 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1010 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1010 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1018 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1018 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1026 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1026 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1034 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1034 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1042 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1042 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1050 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1050 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1058 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1058 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1066 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1066 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1074 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1074 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1082 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1082 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1090 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1090 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1098 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1098 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1106 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1106 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1114 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1114 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1122 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1122 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1130 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1130 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1138 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1138 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1146 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1146 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1154 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1154 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1162 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1162 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1170 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1170 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1178 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1178 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1186 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1186 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1194 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1194 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1202 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1202 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1210 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1210 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1218 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1218 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1226 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1226 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1234 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1234 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1242 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1242 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1250 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1250 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1258 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1258 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1266 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1266 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1274 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1274 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1282 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1282 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1290 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1290 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1298 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1298 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1306 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1306 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1314 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1314 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1322 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1322 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1330 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1330 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1338 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1338 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1346 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1346 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1354 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1354 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire out_romask_151 = |_out_romask_T_151; // @[RegisterRouter.scala:87:24] wire out_womask_151 = &_out_womask_T_151; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_151 = out_rivalid_1_5 & out_rimask_151; // @[RegisterRouter.scala:87:24] wire _out_T_1956 = out_f_rivalid_151; // @[RegisterRouter.scala:87:24] wire out_f_roready_151 = out_roready_1_5 & out_romask_151; // @[RegisterRouter.scala:87:24] wire _out_T_1957 = out_f_roready_151; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_151 = out_wivalid_1_5 & out_wimask_151; // @[RegisterRouter.scala:87:24] wire out_f_woready_151 = out_woready_1_5 & out_womask_151; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1955 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2027 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2099 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2171 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2253 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2331 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2403 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2475 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2547 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2619 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2691 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2763 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2835 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2907 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2989 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3067 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3139 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3211 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3283 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3355 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3427 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3499 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3571 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3643 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3725 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3803 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3875 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3947 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4019 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4091 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4163 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4235 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4307 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4379 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4451 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4523 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4595 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4667 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4739 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4811 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4883 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4955 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5027 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5099 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5189 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5261 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5333 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5405 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5477 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5549 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5621 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5693 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5765 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5837 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5909 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6000 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6078 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6150 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6222 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6294 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6402 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6474 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6546 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6628 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6706 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6778 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6868 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6940 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7012 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7084 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7156 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7228 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7300 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7372 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7444 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7516 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7588 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7660 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7732 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7804 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7876 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7958 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8036 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8108 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8180 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8252 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8342 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8414 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8486 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8558 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8640 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8718 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8790 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8862 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8934 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9006 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9078 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9150 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9222 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9294 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9366 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9438 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9520 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9598 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9670 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9742 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9814 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9886 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9958 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10030 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10102 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10174 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10246 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10318 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10390 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10472 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10550 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10622 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10694 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10766 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10838 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10920 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10998 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11070 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11142 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11214 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11286 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11358 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11430 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11502 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11574 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11646 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11718 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11790 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11862 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11944 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12022 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12094 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12166 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12238 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12310 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12382 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12454 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12526 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12608 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12686 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12758 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12830 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12902 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12974 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire _out_T_1958 = ~out_rimask_151; // @[RegisterRouter.scala:87:24] wire _out_T_1959 = ~out_wimask_151; // @[RegisterRouter.scala:87:24] wire _out_T_1960 = ~out_romask_151; // @[RegisterRouter.scala:87:24] wire _out_T_1961 = ~out_womask_151; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_116 = {hi_86, flags_0_go, _out_prepend_T_116}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_1962 = out_prepend_116; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_1963 = _out_T_1962; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_117 = _out_T_1963; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_152 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_152 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_160 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_160 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_168 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_168 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_176 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_176 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_184 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_184 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_192 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_192 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_200 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_200 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_208 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_208 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_216 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_216 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_224 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_224 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_232 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_232 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_240 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_240 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_248 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_248 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_256 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_256 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_264 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_264 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_272 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_272 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_280 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_280 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_288 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_288 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_296 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_296 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_304 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_304 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_312 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_312 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_320 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_320 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_328 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_328 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_336 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_336 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_344 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_344 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_352 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_352 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_360 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_360 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_368 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_368 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_376 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_376 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_384 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_384 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_392 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_392 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_400 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_400 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_408 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_408 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_416 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_416 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_424 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_424 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_432 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_432 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_440 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_440 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_448 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_448 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_456 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_456 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_464 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_464 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_472 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_472 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_480 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_480 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_488 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_488 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_496 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_496 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_506 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_506 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_514 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_514 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_522 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_522 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_530 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_530 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_538 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_538 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_546 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_546 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_554 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_554 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_562 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_562 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_570 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_570 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_578 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_578 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_586 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_586 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_595 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_595 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_603 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_603 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_611 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_611 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_619 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_619 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_627 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_627 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_639 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_639 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_647 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_647 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_655 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_655 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_663 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_663 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_671 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_671 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_679 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_679 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_689 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_689 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_697 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_697 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_705 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_705 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_713 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_713 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_721 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_721 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_729 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_729 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_737 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_737 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_745 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_745 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_753 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_753 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_761 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_761 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_769 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_769 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_777 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_777 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_785 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_785 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_793 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_793 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_801 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_801 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_809 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_809 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_817 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_817 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_825 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_825 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_833 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_833 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_841 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_841 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_851 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_851 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_859 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_859 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_867 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_867 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_875 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_875 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_883 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_883 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_891 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_891 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_899 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_899 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_907 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_907 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_915 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_915 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_923 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_923 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_931 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_931 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_939 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_939 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_947 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_947 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_955 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_955 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_963 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_963 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_971 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_971 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_979 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_979 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_987 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_987 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_995 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_995 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1003 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1003 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1011 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1011 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1019 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1019 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1027 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1027 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1035 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1035 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1043 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1043 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1051 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1051 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1059 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1059 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1067 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1067 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1075 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1075 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1083 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1083 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1091 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1091 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1099 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1099 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1107 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1107 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1115 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1115 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1123 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1123 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1131 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1131 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1139 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1139 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1147 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1147 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1155 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1155 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1163 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1163 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1171 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1171 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1179 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1179 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1187 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1187 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1195 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1195 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1203 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1203 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1211 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1211 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1219 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1219 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1227 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1227 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1235 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1235 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1243 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1243 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1251 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1251 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1259 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1259 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1267 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1267 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1275 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1275 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1283 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1283 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1291 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1291 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1299 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1299 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1307 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1307 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1315 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1315 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1323 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1323 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1331 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1331 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1339 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1339 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1347 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1347 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1355 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1355 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire out_rimask_152 = |_out_rimask_T_152; // @[RegisterRouter.scala:87:24] wire out_wimask_152 = &_out_wimask_T_152; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_152 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_152 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_160 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_160 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_168 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_168 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_176 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_176 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_184 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_184 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_192 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_192 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_200 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_200 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_208 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_208 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_216 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_216 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_224 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_224 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_232 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_232 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_240 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_240 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_248 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_248 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_256 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_256 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_264 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_264 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_272 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_272 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_280 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_280 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_288 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_288 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_296 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_296 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_304 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_304 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_312 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_312 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_320 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_320 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_328 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_328 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_336 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_336 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_344 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_344 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_352 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_352 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_360 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_360 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_368 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_368 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_376 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_376 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_384 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_384 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_392 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_392 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_400 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_400 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_408 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_408 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_416 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_416 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_424 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_424 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_432 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_432 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_440 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_440 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_448 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_448 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_456 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_456 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_464 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_464 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_472 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_472 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_480 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_480 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_488 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_488 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_496 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_496 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_506 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_506 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_514 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_514 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_522 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_522 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_530 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_530 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_538 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_538 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_546 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_546 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_554 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_554 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_562 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_562 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_570 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_570 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_578 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_578 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_586 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_586 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_595 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_595 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_603 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_603 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_611 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_611 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_619 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_619 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_627 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_627 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_639 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_639 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_647 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_647 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_655 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_655 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_663 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_663 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_671 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_671 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_679 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_679 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_689 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_689 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_697 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_697 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_705 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_705 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_713 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_713 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_721 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_721 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_729 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_729 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_737 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_737 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_745 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_745 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_753 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_753 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_761 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_761 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_769 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_769 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_777 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_777 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_785 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_785 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_793 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_793 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_801 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_801 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_809 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_809 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_817 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_817 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_825 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_825 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_833 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_833 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_841 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_841 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_851 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_851 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_859 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_859 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_867 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_867 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_875 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_875 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_883 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_883 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_891 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_891 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_899 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_899 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_907 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_907 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_915 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_915 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_923 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_923 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_931 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_931 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_939 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_939 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_947 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_947 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_955 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_955 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_963 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_963 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_971 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_971 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_979 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_979 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_987 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_987 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_995 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_995 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1003 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1003 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1011 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1011 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1019 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1019 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1027 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1027 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1035 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1035 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1043 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1043 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1051 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1051 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1059 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1059 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1067 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1067 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1075 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1075 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1083 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1083 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1091 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1091 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1099 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1099 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1107 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1107 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1115 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1115 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1123 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1123 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1131 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1131 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1139 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1139 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1147 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1147 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1155 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1155 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1163 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1163 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1171 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1171 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1179 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1179 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1187 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1187 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1195 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1195 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1203 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1203 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1211 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1211 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1219 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1219 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1227 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1227 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1235 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1235 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1243 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1243 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1251 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1251 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1259 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1259 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1267 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1267 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1275 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1275 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1283 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1283 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1291 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1291 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1299 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1299 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1307 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1307 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1315 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1315 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1323 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1323 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1331 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1331 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1339 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1339 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1347 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1347 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1355 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1355 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire out_romask_152 = |_out_romask_T_152; // @[RegisterRouter.scala:87:24] wire out_womask_152 = &_out_womask_T_152; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_152 = out_rivalid_1_6 & out_rimask_152; // @[RegisterRouter.scala:87:24] wire _out_T_1965 = out_f_rivalid_152; // @[RegisterRouter.scala:87:24] wire out_f_roready_152 = out_roready_1_6 & out_romask_152; // @[RegisterRouter.scala:87:24] wire _out_T_1966 = out_f_roready_152; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_152 = out_wivalid_1_6 & out_wimask_152; // @[RegisterRouter.scala:87:24] wire out_f_woready_152 = out_woready_1_6 & out_womask_152; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1964 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2036 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2108 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2180 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2264 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2340 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2412 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2484 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2556 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2628 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2700 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2772 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2844 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2916 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3000 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3076 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3148 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3220 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3292 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3364 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3436 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3508 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3580 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3652 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3736 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3812 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3884 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3956 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4028 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4100 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4172 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4244 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4316 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4388 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4460 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4532 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4604 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4676 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4748 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4820 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4892 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4964 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5036 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5108 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5198 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5270 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5342 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5414 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5486 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5558 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5630 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5702 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5774 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5846 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5918 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6011 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6087 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6159 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6231 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6303 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6411 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6483 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6555 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6639 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6715 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6787 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6877 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6949 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7021 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7093 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7165 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7237 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7309 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7381 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7453 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7525 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7597 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7669 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7741 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7813 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7885 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7969 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8045 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8117 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8189 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8261 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8351 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8423 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8495 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8567 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8651 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8727 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8799 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8871 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8943 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9015 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9087 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9159 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9231 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9303 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9375 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9447 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9531 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9607 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9679 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9751 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9823 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9895 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9967 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10039 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10111 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10183 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10255 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10327 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10399 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10483 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10559 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10631 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10703 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10775 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10847 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10931 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11007 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11079 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11151 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11223 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11295 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11367 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11439 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11511 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11583 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11655 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11727 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11799 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11871 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11955 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12031 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12103 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12175 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12247 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12319 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12391 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12463 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12535 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12619 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12695 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12767 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12839 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12911 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12983 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire _out_T_1967 = ~out_rimask_152; // @[RegisterRouter.scala:87:24] wire _out_T_1968 = ~out_wimask_152; // @[RegisterRouter.scala:87:24] wire _out_T_1969 = ~out_romask_152; // @[RegisterRouter.scala:87:24] wire _out_T_1970 = ~out_womask_152; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_117 = {hi_87, flags_0_go, _out_prepend_T_117}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_1971 = out_prepend_117; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_1972 = _out_T_1971; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_118 = _out_T_1972; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_153 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_153 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_161 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_161 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_169 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_169 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_177 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_177 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_185 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_185 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_193 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_193 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_201 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_201 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_209 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_209 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_217 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_217 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_225 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_225 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_233 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_233 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_241 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_241 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_249 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_249 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_257 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_257 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_265 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_265 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_273 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_273 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_281 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_281 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_289 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_289 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_297 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_297 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_305 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_305 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_313 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_313 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_321 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_321 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_329 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_329 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_337 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_337 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_345 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_345 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_353 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_353 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_361 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_361 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_369 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_369 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_377 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_377 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_385 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_385 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_393 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_393 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_401 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_401 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_409 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_409 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_417 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_417 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_425 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_425 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_433 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_433 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_441 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_441 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_449 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_449 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_457 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_457 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_465 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_465 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_473 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_473 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_481 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_481 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_489 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_489 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_497 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_497 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_507 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_507 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_515 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_515 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_523 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_523 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_531 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_531 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_539 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_539 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_547 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_547 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_555 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_555 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_563 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_563 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_571 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_571 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_579 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_579 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_587 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_587 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_596 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_596 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_604 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_604 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_612 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_612 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_620 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_620 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_628 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_628 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_640 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_640 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_648 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_648 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_656 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_656 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_664 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_664 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_672 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_672 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_680 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_680 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_690 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_690 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_698 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_698 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_706 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_706 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_714 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_714 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_722 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_722 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_730 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_730 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_738 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_738 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_746 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_746 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_754 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_754 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_762 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_762 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_770 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_770 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_778 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_778 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_786 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_786 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_794 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_794 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_802 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_802 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_810 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_810 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_818 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_818 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_826 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_826 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_834 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_834 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_842 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_842 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_852 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_852 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_860 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_860 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_868 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_868 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_876 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_876 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_884 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_884 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_892 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_892 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_900 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_900 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_908 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_908 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_916 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_916 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_924 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_924 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_932 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_932 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_940 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_940 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_948 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_948 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_956 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_956 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_964 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_964 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_972 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_972 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_980 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_980 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_988 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_988 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_996 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_996 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1004 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1004 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1012 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1012 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1020 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1020 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1028 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1028 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1036 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1036 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1044 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1044 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1052 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1052 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1060 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1060 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1068 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1068 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1076 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1076 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1084 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1084 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1092 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1092 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1100 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1100 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1108 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1108 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1116 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1116 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1124 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1124 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1132 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1132 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1140 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1140 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1148 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1148 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1156 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1156 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1164 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1164 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1172 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1172 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1180 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1180 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1188 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1188 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1196 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1196 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1204 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1204 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1212 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1212 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1220 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1220 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1228 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1228 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1236 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1236 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1244 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1244 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1252 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1252 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1260 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1260 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1268 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1268 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1276 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1276 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1284 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1284 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1292 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1292 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1300 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1300 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1308 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1308 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1316 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1316 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1324 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1324 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1332 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1332 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1340 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1340 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1348 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1348 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1356 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1356 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire out_rimask_153 = |_out_rimask_T_153; // @[RegisterRouter.scala:87:24] wire out_wimask_153 = &_out_wimask_T_153; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_153 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_153 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_161 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_161 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_169 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_169 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_177 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_177 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_185 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_185 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_193 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_193 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_201 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_201 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_209 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_209 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_217 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_217 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_225 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_225 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_233 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_233 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_241 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_241 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_249 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_249 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_257 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_257 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_265 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_265 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_273 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_273 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_281 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_281 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_289 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_289 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_297 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_297 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_305 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_305 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_313 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_313 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_321 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_321 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_329 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_329 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_337 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_337 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_345 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_345 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_353 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_353 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_361 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_361 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_369 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_369 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_377 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_377 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_385 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_385 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_393 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_393 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_401 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_401 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_409 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_409 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_417 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_417 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_425 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_425 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_433 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_433 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_441 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_441 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_449 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_449 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_457 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_457 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_465 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_465 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_473 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_473 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_481 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_481 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_489 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_489 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_497 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_497 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_507 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_507 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_515 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_515 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_523 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_523 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_531 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_531 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_539 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_539 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_547 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_547 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_555 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_555 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_563 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_563 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_571 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_571 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_579 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_579 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_587 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_587 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_596 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_596 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_604 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_604 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_612 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_612 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_620 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_620 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_628 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_628 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_640 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_640 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_648 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_648 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_656 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_656 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_664 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_664 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_672 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_672 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_680 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_680 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_690 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_690 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_698 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_698 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_706 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_706 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_714 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_714 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_722 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_722 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_730 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_730 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_738 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_738 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_746 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_746 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_754 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_754 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_762 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_762 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_770 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_770 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_778 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_778 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_786 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_786 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_794 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_794 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_802 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_802 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_810 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_810 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_818 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_818 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_826 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_826 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_834 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_834 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_842 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_842 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_852 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_852 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_860 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_860 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_868 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_868 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_876 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_876 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_884 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_884 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_892 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_892 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_900 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_900 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_908 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_908 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_916 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_916 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_924 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_924 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_932 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_932 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_940 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_940 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_948 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_948 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_956 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_956 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_964 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_964 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_972 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_972 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_980 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_980 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_988 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_988 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_996 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_996 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1004 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1004 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1012 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1012 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1020 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1020 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1028 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1028 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1036 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1036 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1044 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1044 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1052 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1052 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1060 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1060 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1068 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1068 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1076 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1076 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1084 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1084 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1092 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1092 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1100 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1100 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1108 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1108 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1116 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1116 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1124 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1124 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1132 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1132 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1140 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1140 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1148 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1148 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1156 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1156 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1164 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1164 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1172 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1172 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1180 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1180 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1188 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1188 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1196 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1196 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1204 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1204 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1212 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1212 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1220 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1220 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1228 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1228 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1236 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1236 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1244 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1244 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1252 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1252 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1260 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1260 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1268 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1268 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1276 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1276 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1284 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1284 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1292 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1292 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1300 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1300 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1308 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1308 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1316 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1316 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1324 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1324 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1332 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1332 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1340 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1340 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1348 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1348 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1356 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1356 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire out_romask_153 = |_out_romask_T_153; // @[RegisterRouter.scala:87:24] wire out_womask_153 = &_out_womask_T_153; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_153 = out_rivalid_1_7 & out_rimask_153; // @[RegisterRouter.scala:87:24] wire _out_T_1974 = out_f_rivalid_153; // @[RegisterRouter.scala:87:24] wire out_f_roready_153 = out_roready_1_7 & out_romask_153; // @[RegisterRouter.scala:87:24] wire _out_T_1975 = out_f_roready_153; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_153 = out_wivalid_1_7 & out_wimask_153; // @[RegisterRouter.scala:87:24] wire out_f_woready_153 = out_woready_1_7 & out_womask_153; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1973 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2045 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2117 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2189 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2275 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2349 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2421 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2493 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2565 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2637 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2709 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2781 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2853 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2925 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3011 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3085 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3157 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3229 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3301 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3373 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3445 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3517 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3589 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3661 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3747 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3821 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3893 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3965 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4037 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4109 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4181 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4253 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4325 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4397 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4469 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4541 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4613 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4685 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4757 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4829 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4901 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4973 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5045 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5117 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5207 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5279 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5351 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5423 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5495 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5567 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5639 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5711 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5783 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5855 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5927 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6022 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6096 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6168 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6240 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6312 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6420 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6492 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6564 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6650 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6724 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6796 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6886 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6958 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7030 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7102 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7174 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7246 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7318 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7390 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7462 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7534 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7606 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7678 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7750 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7822 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7894 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7980 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8054 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8126 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8198 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8270 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8360 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8432 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8504 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8576 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8662 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8736 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8808 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8880 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8952 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9024 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9096 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9168 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9240 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9312 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9384 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9456 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9542 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9616 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9688 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9760 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9832 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9904 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9976 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10048 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10120 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10192 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10264 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10336 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10408 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10494 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10568 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10640 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10712 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10784 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10856 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10942 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11016 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11088 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11160 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11232 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11304 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11376 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11448 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11520 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11592 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11664 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11736 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11808 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11880 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11966 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12040 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12112 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12184 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12256 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12328 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12400 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12472 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12544 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12630 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12704 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12776 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12848 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12920 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12992 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire _out_T_1976 = ~out_rimask_153; // @[RegisterRouter.scala:87:24] wire _out_T_1977 = ~out_wimask_153; // @[RegisterRouter.scala:87:24] wire _out_T_1978 = ~out_romask_153; // @[RegisterRouter.scala:87:24] wire _out_T_1979 = ~out_womask_153; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_118 = {hi_88, flags_0_go, _out_prepend_T_118}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_1980 = out_prepend_118; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_1981 = _out_T_1980; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_138 = _out_T_1981; // @[MuxLiteral.scala:49:48] wire out_rimask_154 = |_out_rimask_T_154; // @[RegisterRouter.scala:87:24] wire out_wimask_154 = &_out_wimask_T_154; // @[RegisterRouter.scala:87:24] wire out_romask_154 = |_out_romask_T_154; // @[RegisterRouter.scala:87:24] wire out_womask_154 = &_out_womask_T_154; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_154 = out_rivalid_1_8 & out_rimask_154; // @[RegisterRouter.scala:87:24] wire _out_T_1983 = out_f_rivalid_154; // @[RegisterRouter.scala:87:24] wire out_f_roready_154 = out_roready_1_8 & out_romask_154; // @[RegisterRouter.scala:87:24] wire _out_T_1984 = out_f_roready_154; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_154 = out_wivalid_1_8 & out_wimask_154; // @[RegisterRouter.scala:87:24] wire out_f_woready_154 = out_woready_1_8 & out_womask_154; // @[RegisterRouter.scala:87:24] wire _out_T_1985 = ~out_rimask_154; // @[RegisterRouter.scala:87:24] wire _out_T_1986 = ~out_wimask_154; // @[RegisterRouter.scala:87:24] wire _out_T_1987 = ~out_romask_154; // @[RegisterRouter.scala:87:24] wire _out_T_1988 = ~out_womask_154; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1990 = _out_T_1989; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_119 = _out_T_1990; // @[RegisterRouter.scala:87:24] wire out_rimask_155 = |_out_rimask_T_155; // @[RegisterRouter.scala:87:24] wire out_wimask_155 = &_out_wimask_T_155; // @[RegisterRouter.scala:87:24] wire out_romask_155 = |_out_romask_T_155; // @[RegisterRouter.scala:87:24] wire out_womask_155 = &_out_womask_T_155; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_155 = out_rivalid_1_9 & out_rimask_155; // @[RegisterRouter.scala:87:24] wire _out_T_1992 = out_f_rivalid_155; // @[RegisterRouter.scala:87:24] wire out_f_roready_155 = out_roready_1_9 & out_romask_155; // @[RegisterRouter.scala:87:24] wire _out_T_1993 = out_f_roready_155; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_155 = out_wivalid_1_9 & out_wimask_155; // @[RegisterRouter.scala:87:24] wire out_f_woready_155 = out_woready_1_9 & out_womask_155; // @[RegisterRouter.scala:87:24] wire _out_T_1994 = ~out_rimask_155; // @[RegisterRouter.scala:87:24] wire _out_T_1995 = ~out_wimask_155; // @[RegisterRouter.scala:87:24] wire _out_T_1996 = ~out_romask_155; // @[RegisterRouter.scala:87:24] wire _out_T_1997 = ~out_womask_155; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_119 = {hi_970, flags_0_go, _out_prepend_T_119}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1998 = out_prepend_119; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1999 = _out_T_1998; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_120 = _out_T_1999; // @[RegisterRouter.scala:87:24] wire out_rimask_156 = |_out_rimask_T_156; // @[RegisterRouter.scala:87:24] wire out_wimask_156 = &_out_wimask_T_156; // @[RegisterRouter.scala:87:24] wire out_romask_156 = |_out_romask_T_156; // @[RegisterRouter.scala:87:24] wire out_womask_156 = &_out_womask_T_156; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_156 = out_rivalid_1_10 & out_rimask_156; // @[RegisterRouter.scala:87:24] wire _out_T_2001 = out_f_rivalid_156; // @[RegisterRouter.scala:87:24] wire out_f_roready_156 = out_roready_1_10 & out_romask_156; // @[RegisterRouter.scala:87:24] wire _out_T_2002 = out_f_roready_156; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_156 = out_wivalid_1_10 & out_wimask_156; // @[RegisterRouter.scala:87:24] wire out_f_woready_156 = out_woready_1_10 & out_womask_156; // @[RegisterRouter.scala:87:24] wire _out_T_2003 = ~out_rimask_156; // @[RegisterRouter.scala:87:24] wire _out_T_2004 = ~out_wimask_156; // @[RegisterRouter.scala:87:24] wire _out_T_2005 = ~out_romask_156; // @[RegisterRouter.scala:87:24] wire _out_T_2006 = ~out_womask_156; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_120 = {hi_971, flags_0_go, _out_prepend_T_120}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2007 = out_prepend_120; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2008 = _out_T_2007; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_121 = _out_T_2008; // @[RegisterRouter.scala:87:24] wire out_rimask_157 = |_out_rimask_T_157; // @[RegisterRouter.scala:87:24] wire out_wimask_157 = &_out_wimask_T_157; // @[RegisterRouter.scala:87:24] wire out_romask_157 = |_out_romask_T_157; // @[RegisterRouter.scala:87:24] wire out_womask_157 = &_out_womask_T_157; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_157 = out_rivalid_1_11 & out_rimask_157; // @[RegisterRouter.scala:87:24] wire _out_T_2010 = out_f_rivalid_157; // @[RegisterRouter.scala:87:24] wire out_f_roready_157 = out_roready_1_11 & out_romask_157; // @[RegisterRouter.scala:87:24] wire _out_T_2011 = out_f_roready_157; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_157 = out_wivalid_1_11 & out_wimask_157; // @[RegisterRouter.scala:87:24] wire out_f_woready_157 = out_woready_1_11 & out_womask_157; // @[RegisterRouter.scala:87:24] wire _out_T_2012 = ~out_rimask_157; // @[RegisterRouter.scala:87:24] wire _out_T_2013 = ~out_wimask_157; // @[RegisterRouter.scala:87:24] wire _out_T_2014 = ~out_romask_157; // @[RegisterRouter.scala:87:24] wire _out_T_2015 = ~out_womask_157; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_121 = {hi_972, flags_0_go, _out_prepend_T_121}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2016 = out_prepend_121; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2017 = _out_T_2016; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_122 = _out_T_2017; // @[RegisterRouter.scala:87:24] wire out_rimask_158 = |_out_rimask_T_158; // @[RegisterRouter.scala:87:24] wire out_wimask_158 = &_out_wimask_T_158; // @[RegisterRouter.scala:87:24] wire out_romask_158 = |_out_romask_T_158; // @[RegisterRouter.scala:87:24] wire out_womask_158 = &_out_womask_T_158; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_158 = out_rivalid_1_12 & out_rimask_158; // @[RegisterRouter.scala:87:24] wire _out_T_2019 = out_f_rivalid_158; // @[RegisterRouter.scala:87:24] wire out_f_roready_158 = out_roready_1_12 & out_romask_158; // @[RegisterRouter.scala:87:24] wire _out_T_2020 = out_f_roready_158; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_158 = out_wivalid_1_12 & out_wimask_158; // @[RegisterRouter.scala:87:24] wire out_f_woready_158 = out_woready_1_12 & out_womask_158; // @[RegisterRouter.scala:87:24] wire _out_T_2021 = ~out_rimask_158; // @[RegisterRouter.scala:87:24] wire _out_T_2022 = ~out_wimask_158; // @[RegisterRouter.scala:87:24] wire _out_T_2023 = ~out_romask_158; // @[RegisterRouter.scala:87:24] wire _out_T_2024 = ~out_womask_158; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_122 = {hi_973, flags_0_go, _out_prepend_T_122}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2025 = out_prepend_122; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2026 = _out_T_2025; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_123 = _out_T_2026; // @[RegisterRouter.scala:87:24] wire out_rimask_159 = |_out_rimask_T_159; // @[RegisterRouter.scala:87:24] wire out_wimask_159 = &_out_wimask_T_159; // @[RegisterRouter.scala:87:24] wire out_romask_159 = |_out_romask_T_159; // @[RegisterRouter.scala:87:24] wire out_womask_159 = &_out_womask_T_159; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_159 = out_rivalid_1_13 & out_rimask_159; // @[RegisterRouter.scala:87:24] wire _out_T_2028 = out_f_rivalid_159; // @[RegisterRouter.scala:87:24] wire out_f_roready_159 = out_roready_1_13 & out_romask_159; // @[RegisterRouter.scala:87:24] wire _out_T_2029 = out_f_roready_159; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_159 = out_wivalid_1_13 & out_wimask_159; // @[RegisterRouter.scala:87:24] wire out_f_woready_159 = out_woready_1_13 & out_womask_159; // @[RegisterRouter.scala:87:24] wire _out_T_2030 = ~out_rimask_159; // @[RegisterRouter.scala:87:24] wire _out_T_2031 = ~out_wimask_159; // @[RegisterRouter.scala:87:24] wire _out_T_2032 = ~out_romask_159; // @[RegisterRouter.scala:87:24] wire _out_T_2033 = ~out_womask_159; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_123 = {hi_974, flags_0_go, _out_prepend_T_123}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2034 = out_prepend_123; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2035 = _out_T_2034; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_124 = _out_T_2035; // @[RegisterRouter.scala:87:24] wire out_rimask_160 = |_out_rimask_T_160; // @[RegisterRouter.scala:87:24] wire out_wimask_160 = &_out_wimask_T_160; // @[RegisterRouter.scala:87:24] wire out_romask_160 = |_out_romask_T_160; // @[RegisterRouter.scala:87:24] wire out_womask_160 = &_out_womask_T_160; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_160 = out_rivalid_1_14 & out_rimask_160; // @[RegisterRouter.scala:87:24] wire _out_T_2037 = out_f_rivalid_160; // @[RegisterRouter.scala:87:24] wire out_f_roready_160 = out_roready_1_14 & out_romask_160; // @[RegisterRouter.scala:87:24] wire _out_T_2038 = out_f_roready_160; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_160 = out_wivalid_1_14 & out_wimask_160; // @[RegisterRouter.scala:87:24] wire out_f_woready_160 = out_woready_1_14 & out_womask_160; // @[RegisterRouter.scala:87:24] wire _out_T_2039 = ~out_rimask_160; // @[RegisterRouter.scala:87:24] wire _out_T_2040 = ~out_wimask_160; // @[RegisterRouter.scala:87:24] wire _out_T_2041 = ~out_romask_160; // @[RegisterRouter.scala:87:24] wire _out_T_2042 = ~out_womask_160; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_124 = {hi_975, flags_0_go, _out_prepend_T_124}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2043 = out_prepend_124; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2044 = _out_T_2043; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_125 = _out_T_2044; // @[RegisterRouter.scala:87:24] wire out_rimask_161 = |_out_rimask_T_161; // @[RegisterRouter.scala:87:24] wire out_wimask_161 = &_out_wimask_T_161; // @[RegisterRouter.scala:87:24] wire out_romask_161 = |_out_romask_T_161; // @[RegisterRouter.scala:87:24] wire out_womask_161 = &_out_womask_T_161; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_161 = out_rivalid_1_15 & out_rimask_161; // @[RegisterRouter.scala:87:24] wire _out_T_2046 = out_f_rivalid_161; // @[RegisterRouter.scala:87:24] wire out_f_roready_161 = out_roready_1_15 & out_romask_161; // @[RegisterRouter.scala:87:24] wire _out_T_2047 = out_f_roready_161; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_161 = out_wivalid_1_15 & out_wimask_161; // @[RegisterRouter.scala:87:24] wire out_f_woready_161 = out_woready_1_15 & out_womask_161; // @[RegisterRouter.scala:87:24] wire _out_T_2048 = ~out_rimask_161; // @[RegisterRouter.scala:87:24] wire _out_T_2049 = ~out_wimask_161; // @[RegisterRouter.scala:87:24] wire _out_T_2050 = ~out_romask_161; // @[RegisterRouter.scala:87:24] wire _out_T_2051 = ~out_womask_161; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_125 = {hi_976, flags_0_go, _out_prepend_T_125}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2052 = out_prepend_125; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2053 = _out_T_2052; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_249 = _out_T_2053; // @[MuxLiteral.scala:49:48] wire out_rimask_162 = |_out_rimask_T_162; // @[RegisterRouter.scala:87:24] wire out_wimask_162 = &_out_wimask_T_162; // @[RegisterRouter.scala:87:24] wire out_romask_162 = |_out_romask_T_162; // @[RegisterRouter.scala:87:24] wire out_womask_162 = &_out_womask_T_162; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_162 = out_rivalid_1_16 & out_rimask_162; // @[RegisterRouter.scala:87:24] wire _out_T_2055 = out_f_rivalid_162; // @[RegisterRouter.scala:87:24] wire out_f_roready_162 = out_roready_1_16 & out_romask_162; // @[RegisterRouter.scala:87:24] wire _out_T_2056 = out_f_roready_162; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_162 = out_wivalid_1_16 & out_wimask_162; // @[RegisterRouter.scala:87:24] wire out_f_woready_162 = out_woready_1_16 & out_womask_162; // @[RegisterRouter.scala:87:24] wire _out_T_2057 = ~out_rimask_162; // @[RegisterRouter.scala:87:24] wire _out_T_2058 = ~out_wimask_162; // @[RegisterRouter.scala:87:24] wire _out_T_2059 = ~out_romask_162; // @[RegisterRouter.scala:87:24] wire _out_T_2060 = ~out_womask_162; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2062 = _out_T_2061; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_126 = _out_T_2062; // @[RegisterRouter.scala:87:24] wire out_rimask_163 = |_out_rimask_T_163; // @[RegisterRouter.scala:87:24] wire out_wimask_163 = &_out_wimask_T_163; // @[RegisterRouter.scala:87:24] wire out_romask_163 = |_out_romask_T_163; // @[RegisterRouter.scala:87:24] wire out_womask_163 = &_out_womask_T_163; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_163 = out_rivalid_1_17 & out_rimask_163; // @[RegisterRouter.scala:87:24] wire _out_T_2064 = out_f_rivalid_163; // @[RegisterRouter.scala:87:24] wire out_f_roready_163 = out_roready_1_17 & out_romask_163; // @[RegisterRouter.scala:87:24] wire _out_T_2065 = out_f_roready_163; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_163 = out_wivalid_1_17 & out_wimask_163; // @[RegisterRouter.scala:87:24] wire out_f_woready_163 = out_woready_1_17 & out_womask_163; // @[RegisterRouter.scala:87:24] wire _out_T_2066 = ~out_rimask_163; // @[RegisterRouter.scala:87:24] wire _out_T_2067 = ~out_wimask_163; // @[RegisterRouter.scala:87:24] wire _out_T_2068 = ~out_romask_163; // @[RegisterRouter.scala:87:24] wire _out_T_2069 = ~out_womask_163; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_126 = {hi_850, flags_0_go, _out_prepend_T_126}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2070 = out_prepend_126; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2071 = _out_T_2070; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_127 = _out_T_2071; // @[RegisterRouter.scala:87:24] wire out_rimask_164 = |_out_rimask_T_164; // @[RegisterRouter.scala:87:24] wire out_wimask_164 = &_out_wimask_T_164; // @[RegisterRouter.scala:87:24] wire out_romask_164 = |_out_romask_T_164; // @[RegisterRouter.scala:87:24] wire out_womask_164 = &_out_womask_T_164; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_164 = out_rivalid_1_18 & out_rimask_164; // @[RegisterRouter.scala:87:24] wire _out_T_2073 = out_f_rivalid_164; // @[RegisterRouter.scala:87:24] wire out_f_roready_164 = out_roready_1_18 & out_romask_164; // @[RegisterRouter.scala:87:24] wire _out_T_2074 = out_f_roready_164; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_164 = out_wivalid_1_18 & out_wimask_164; // @[RegisterRouter.scala:87:24] wire out_f_woready_164 = out_woready_1_18 & out_womask_164; // @[RegisterRouter.scala:87:24] wire _out_T_2075 = ~out_rimask_164; // @[RegisterRouter.scala:87:24] wire _out_T_2076 = ~out_wimask_164; // @[RegisterRouter.scala:87:24] wire _out_T_2077 = ~out_romask_164; // @[RegisterRouter.scala:87:24] wire _out_T_2078 = ~out_womask_164; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_127 = {hi_851, flags_0_go, _out_prepend_T_127}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2079 = out_prepend_127; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2080 = _out_T_2079; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_128 = _out_T_2080; // @[RegisterRouter.scala:87:24] wire out_rimask_165 = |_out_rimask_T_165; // @[RegisterRouter.scala:87:24] wire out_wimask_165 = &_out_wimask_T_165; // @[RegisterRouter.scala:87:24] wire out_romask_165 = |_out_romask_T_165; // @[RegisterRouter.scala:87:24] wire out_womask_165 = &_out_womask_T_165; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_165 = out_rivalid_1_19 & out_rimask_165; // @[RegisterRouter.scala:87:24] wire _out_T_2082 = out_f_rivalid_165; // @[RegisterRouter.scala:87:24] wire out_f_roready_165 = out_roready_1_19 & out_romask_165; // @[RegisterRouter.scala:87:24] wire _out_T_2083 = out_f_roready_165; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_165 = out_wivalid_1_19 & out_wimask_165; // @[RegisterRouter.scala:87:24] wire out_f_woready_165 = out_woready_1_19 & out_womask_165; // @[RegisterRouter.scala:87:24] wire _out_T_2084 = ~out_rimask_165; // @[RegisterRouter.scala:87:24] wire _out_T_2085 = ~out_wimask_165; // @[RegisterRouter.scala:87:24] wire _out_T_2086 = ~out_romask_165; // @[RegisterRouter.scala:87:24] wire _out_T_2087 = ~out_womask_165; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_128 = {hi_852, flags_0_go, _out_prepend_T_128}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2088 = out_prepend_128; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2089 = _out_T_2088; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_129 = _out_T_2089; // @[RegisterRouter.scala:87:24] wire out_rimask_166 = |_out_rimask_T_166; // @[RegisterRouter.scala:87:24] wire out_wimask_166 = &_out_wimask_T_166; // @[RegisterRouter.scala:87:24] wire out_romask_166 = |_out_romask_T_166; // @[RegisterRouter.scala:87:24] wire out_womask_166 = &_out_womask_T_166; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_166 = out_rivalid_1_20 & out_rimask_166; // @[RegisterRouter.scala:87:24] wire _out_T_2091 = out_f_rivalid_166; // @[RegisterRouter.scala:87:24] wire out_f_roready_166 = out_roready_1_20 & out_romask_166; // @[RegisterRouter.scala:87:24] wire _out_T_2092 = out_f_roready_166; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_166 = out_wivalid_1_20 & out_wimask_166; // @[RegisterRouter.scala:87:24] wire out_f_woready_166 = out_woready_1_20 & out_womask_166; // @[RegisterRouter.scala:87:24] wire _out_T_2093 = ~out_rimask_166; // @[RegisterRouter.scala:87:24] wire _out_T_2094 = ~out_wimask_166; // @[RegisterRouter.scala:87:24] wire _out_T_2095 = ~out_romask_166; // @[RegisterRouter.scala:87:24] wire _out_T_2096 = ~out_womask_166; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_129 = {hi_853, flags_0_go, _out_prepend_T_129}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2097 = out_prepend_129; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2098 = _out_T_2097; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_130 = _out_T_2098; // @[RegisterRouter.scala:87:24] wire out_rimask_167 = |_out_rimask_T_167; // @[RegisterRouter.scala:87:24] wire out_wimask_167 = &_out_wimask_T_167; // @[RegisterRouter.scala:87:24] wire out_romask_167 = |_out_romask_T_167; // @[RegisterRouter.scala:87:24] wire out_womask_167 = &_out_womask_T_167; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_167 = out_rivalid_1_21 & out_rimask_167; // @[RegisterRouter.scala:87:24] wire _out_T_2100 = out_f_rivalid_167; // @[RegisterRouter.scala:87:24] wire out_f_roready_167 = out_roready_1_21 & out_romask_167; // @[RegisterRouter.scala:87:24] wire _out_T_2101 = out_f_roready_167; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_167 = out_wivalid_1_21 & out_wimask_167; // @[RegisterRouter.scala:87:24] wire out_f_woready_167 = out_woready_1_21 & out_womask_167; // @[RegisterRouter.scala:87:24] wire _out_T_2102 = ~out_rimask_167; // @[RegisterRouter.scala:87:24] wire _out_T_2103 = ~out_wimask_167; // @[RegisterRouter.scala:87:24] wire _out_T_2104 = ~out_romask_167; // @[RegisterRouter.scala:87:24] wire _out_T_2105 = ~out_womask_167; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_130 = {hi_854, flags_0_go, _out_prepend_T_130}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2106 = out_prepend_130; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2107 = _out_T_2106; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_131 = _out_T_2107; // @[RegisterRouter.scala:87:24] wire out_rimask_168 = |_out_rimask_T_168; // @[RegisterRouter.scala:87:24] wire out_wimask_168 = &_out_wimask_T_168; // @[RegisterRouter.scala:87:24] wire out_romask_168 = |_out_romask_T_168; // @[RegisterRouter.scala:87:24] wire out_womask_168 = &_out_womask_T_168; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_168 = out_rivalid_1_22 & out_rimask_168; // @[RegisterRouter.scala:87:24] wire _out_T_2109 = out_f_rivalid_168; // @[RegisterRouter.scala:87:24] wire out_f_roready_168 = out_roready_1_22 & out_romask_168; // @[RegisterRouter.scala:87:24] wire _out_T_2110 = out_f_roready_168; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_168 = out_wivalid_1_22 & out_wimask_168; // @[RegisterRouter.scala:87:24] wire out_f_woready_168 = out_woready_1_22 & out_womask_168; // @[RegisterRouter.scala:87:24] wire _out_T_2111 = ~out_rimask_168; // @[RegisterRouter.scala:87:24] wire _out_T_2112 = ~out_wimask_168; // @[RegisterRouter.scala:87:24] wire _out_T_2113 = ~out_romask_168; // @[RegisterRouter.scala:87:24] wire _out_T_2114 = ~out_womask_168; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_131 = {hi_855, flags_0_go, _out_prepend_T_131}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2115 = out_prepend_131; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2116 = _out_T_2115; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_132 = _out_T_2116; // @[RegisterRouter.scala:87:24] wire out_rimask_169 = |_out_rimask_T_169; // @[RegisterRouter.scala:87:24] wire out_wimask_169 = &_out_wimask_T_169; // @[RegisterRouter.scala:87:24] wire out_romask_169 = |_out_romask_T_169; // @[RegisterRouter.scala:87:24] wire out_womask_169 = &_out_womask_T_169; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_169 = out_rivalid_1_23 & out_rimask_169; // @[RegisterRouter.scala:87:24] wire _out_T_2118 = out_f_rivalid_169; // @[RegisterRouter.scala:87:24] wire out_f_roready_169 = out_roready_1_23 & out_romask_169; // @[RegisterRouter.scala:87:24] wire _out_T_2119 = out_f_roready_169; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_169 = out_wivalid_1_23 & out_wimask_169; // @[RegisterRouter.scala:87:24] wire out_f_woready_169 = out_woready_1_23 & out_womask_169; // @[RegisterRouter.scala:87:24] wire _out_T_2120 = ~out_rimask_169; // @[RegisterRouter.scala:87:24] wire _out_T_2121 = ~out_wimask_169; // @[RegisterRouter.scala:87:24] wire _out_T_2122 = ~out_romask_169; // @[RegisterRouter.scala:87:24] wire _out_T_2123 = ~out_womask_169; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_132 = {hi_856, flags_0_go, _out_prepend_T_132}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2124 = out_prepend_132; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2125 = _out_T_2124; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_234 = _out_T_2125; // @[MuxLiteral.scala:49:48] wire out_rimask_170 = |_out_rimask_T_170; // @[RegisterRouter.scala:87:24] wire out_wimask_170 = &_out_wimask_T_170; // @[RegisterRouter.scala:87:24] wire out_romask_170 = |_out_romask_T_170; // @[RegisterRouter.scala:87:24] wire out_womask_170 = &_out_womask_T_170; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_170 = out_rivalid_1_24 & out_rimask_170; // @[RegisterRouter.scala:87:24] wire _out_T_2127 = out_f_rivalid_170; // @[RegisterRouter.scala:87:24] wire out_f_roready_170 = out_roready_1_24 & out_romask_170; // @[RegisterRouter.scala:87:24] wire _out_T_2128 = out_f_roready_170; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_170 = out_wivalid_1_24 & out_wimask_170; // @[RegisterRouter.scala:87:24] wire out_f_woready_170 = out_woready_1_24 & out_womask_170; // @[RegisterRouter.scala:87:24] wire _out_T_2129 = ~out_rimask_170; // @[RegisterRouter.scala:87:24] wire _out_T_2130 = ~out_wimask_170; // @[RegisterRouter.scala:87:24] wire _out_T_2131 = ~out_romask_170; // @[RegisterRouter.scala:87:24] wire _out_T_2132 = ~out_womask_170; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2134 = _out_T_2133; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_133 = _out_T_2134; // @[RegisterRouter.scala:87:24] wire out_rimask_171 = |_out_rimask_T_171; // @[RegisterRouter.scala:87:24] wire out_wimask_171 = &_out_wimask_T_171; // @[RegisterRouter.scala:87:24] wire out_romask_171 = |_out_romask_T_171; // @[RegisterRouter.scala:87:24] wire out_womask_171 = &_out_womask_T_171; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_171 = out_rivalid_1_25 & out_rimask_171; // @[RegisterRouter.scala:87:24] wire _out_T_2136 = out_f_rivalid_171; // @[RegisterRouter.scala:87:24] wire out_f_roready_171 = out_roready_1_25 & out_romask_171; // @[RegisterRouter.scala:87:24] wire _out_T_2137 = out_f_roready_171; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_171 = out_wivalid_1_25 & out_wimask_171; // @[RegisterRouter.scala:87:24] wire out_f_woready_171 = out_woready_1_25 & out_womask_171; // @[RegisterRouter.scala:87:24] wire _out_T_2138 = ~out_rimask_171; // @[RegisterRouter.scala:87:24] wire _out_T_2139 = ~out_wimask_171; // @[RegisterRouter.scala:87:24] wire _out_T_2140 = ~out_romask_171; // @[RegisterRouter.scala:87:24] wire _out_T_2141 = ~out_womask_171; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_133 = {hi_338, flags_0_go, _out_prepend_T_133}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2142 = out_prepend_133; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2143 = _out_T_2142; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_134 = _out_T_2143; // @[RegisterRouter.scala:87:24] wire out_rimask_172 = |_out_rimask_T_172; // @[RegisterRouter.scala:87:24] wire out_wimask_172 = &_out_wimask_T_172; // @[RegisterRouter.scala:87:24] wire out_romask_172 = |_out_romask_T_172; // @[RegisterRouter.scala:87:24] wire out_womask_172 = &_out_womask_T_172; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_172 = out_rivalid_1_26 & out_rimask_172; // @[RegisterRouter.scala:87:24] wire _out_T_2145 = out_f_rivalid_172; // @[RegisterRouter.scala:87:24] wire out_f_roready_172 = out_roready_1_26 & out_romask_172; // @[RegisterRouter.scala:87:24] wire _out_T_2146 = out_f_roready_172; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_172 = out_wivalid_1_26 & out_wimask_172; // @[RegisterRouter.scala:87:24] wire out_f_woready_172 = out_woready_1_26 & out_womask_172; // @[RegisterRouter.scala:87:24] wire _out_T_2147 = ~out_rimask_172; // @[RegisterRouter.scala:87:24] wire _out_T_2148 = ~out_wimask_172; // @[RegisterRouter.scala:87:24] wire _out_T_2149 = ~out_romask_172; // @[RegisterRouter.scala:87:24] wire _out_T_2150 = ~out_womask_172; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_134 = {hi_339, flags_0_go, _out_prepend_T_134}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2151 = out_prepend_134; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2152 = _out_T_2151; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_135 = _out_T_2152; // @[RegisterRouter.scala:87:24] wire out_rimask_173 = |_out_rimask_T_173; // @[RegisterRouter.scala:87:24] wire out_wimask_173 = &_out_wimask_T_173; // @[RegisterRouter.scala:87:24] wire out_romask_173 = |_out_romask_T_173; // @[RegisterRouter.scala:87:24] wire out_womask_173 = &_out_womask_T_173; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_173 = out_rivalid_1_27 & out_rimask_173; // @[RegisterRouter.scala:87:24] wire _out_T_2154 = out_f_rivalid_173; // @[RegisterRouter.scala:87:24] wire out_f_roready_173 = out_roready_1_27 & out_romask_173; // @[RegisterRouter.scala:87:24] wire _out_T_2155 = out_f_roready_173; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_173 = out_wivalid_1_27 & out_wimask_173; // @[RegisterRouter.scala:87:24] wire out_f_woready_173 = out_woready_1_27 & out_womask_173; // @[RegisterRouter.scala:87:24] wire _out_T_2156 = ~out_rimask_173; // @[RegisterRouter.scala:87:24] wire _out_T_2157 = ~out_wimask_173; // @[RegisterRouter.scala:87:24] wire _out_T_2158 = ~out_romask_173; // @[RegisterRouter.scala:87:24] wire _out_T_2159 = ~out_womask_173; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_135 = {hi_340, flags_0_go, _out_prepend_T_135}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2160 = out_prepend_135; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2161 = _out_T_2160; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_136 = _out_T_2161; // @[RegisterRouter.scala:87:24] wire out_rimask_174 = |_out_rimask_T_174; // @[RegisterRouter.scala:87:24] wire out_wimask_174 = &_out_wimask_T_174; // @[RegisterRouter.scala:87:24] wire out_romask_174 = |_out_romask_T_174; // @[RegisterRouter.scala:87:24] wire out_womask_174 = &_out_womask_T_174; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_174 = out_rivalid_1_28 & out_rimask_174; // @[RegisterRouter.scala:87:24] wire _out_T_2163 = out_f_rivalid_174; // @[RegisterRouter.scala:87:24] wire out_f_roready_174 = out_roready_1_28 & out_romask_174; // @[RegisterRouter.scala:87:24] wire _out_T_2164 = out_f_roready_174; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_174 = out_wivalid_1_28 & out_wimask_174; // @[RegisterRouter.scala:87:24] wire out_f_woready_174 = out_woready_1_28 & out_womask_174; // @[RegisterRouter.scala:87:24] wire _out_T_2165 = ~out_rimask_174; // @[RegisterRouter.scala:87:24] wire _out_T_2166 = ~out_wimask_174; // @[RegisterRouter.scala:87:24] wire _out_T_2167 = ~out_romask_174; // @[RegisterRouter.scala:87:24] wire _out_T_2168 = ~out_womask_174; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_136 = {hi_341, flags_0_go, _out_prepend_T_136}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2169 = out_prepend_136; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2170 = _out_T_2169; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_137 = _out_T_2170; // @[RegisterRouter.scala:87:24] wire out_rimask_175 = |_out_rimask_T_175; // @[RegisterRouter.scala:87:24] wire out_wimask_175 = &_out_wimask_T_175; // @[RegisterRouter.scala:87:24] wire out_romask_175 = |_out_romask_T_175; // @[RegisterRouter.scala:87:24] wire out_womask_175 = &_out_womask_T_175; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_175 = out_rivalid_1_29 & out_rimask_175; // @[RegisterRouter.scala:87:24] wire _out_T_2172 = out_f_rivalid_175; // @[RegisterRouter.scala:87:24] wire out_f_roready_175 = out_roready_1_29 & out_romask_175; // @[RegisterRouter.scala:87:24] wire _out_T_2173 = out_f_roready_175; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_175 = out_wivalid_1_29 & out_wimask_175; // @[RegisterRouter.scala:87:24] wire out_f_woready_175 = out_woready_1_29 & out_womask_175; // @[RegisterRouter.scala:87:24] wire _out_T_2174 = ~out_rimask_175; // @[RegisterRouter.scala:87:24] wire _out_T_2175 = ~out_wimask_175; // @[RegisterRouter.scala:87:24] wire _out_T_2176 = ~out_romask_175; // @[RegisterRouter.scala:87:24] wire _out_T_2177 = ~out_womask_175; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_137 = {hi_342, flags_0_go, _out_prepend_T_137}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2178 = out_prepend_137; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2179 = _out_T_2178; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_138 = _out_T_2179; // @[RegisterRouter.scala:87:24] wire out_rimask_176 = |_out_rimask_T_176; // @[RegisterRouter.scala:87:24] wire out_wimask_176 = &_out_wimask_T_176; // @[RegisterRouter.scala:87:24] wire out_romask_176 = |_out_romask_T_176; // @[RegisterRouter.scala:87:24] wire out_womask_176 = &_out_womask_T_176; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_176 = out_rivalid_1_30 & out_rimask_176; // @[RegisterRouter.scala:87:24] wire _out_T_2181 = out_f_rivalid_176; // @[RegisterRouter.scala:87:24] wire out_f_roready_176 = out_roready_1_30 & out_romask_176; // @[RegisterRouter.scala:87:24] wire _out_T_2182 = out_f_roready_176; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_176 = out_wivalid_1_30 & out_wimask_176; // @[RegisterRouter.scala:87:24] wire out_f_woready_176 = out_woready_1_30 & out_womask_176; // @[RegisterRouter.scala:87:24] wire _out_T_2183 = ~out_rimask_176; // @[RegisterRouter.scala:87:24] wire _out_T_2184 = ~out_wimask_176; // @[RegisterRouter.scala:87:24] wire _out_T_2185 = ~out_romask_176; // @[RegisterRouter.scala:87:24] wire _out_T_2186 = ~out_womask_176; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_138 = {hi_343, flags_0_go, _out_prepend_T_138}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2187 = out_prepend_138; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2188 = _out_T_2187; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_139 = _out_T_2188; // @[RegisterRouter.scala:87:24] wire out_rimask_177 = |_out_rimask_T_177; // @[RegisterRouter.scala:87:24] wire out_wimask_177 = &_out_wimask_T_177; // @[RegisterRouter.scala:87:24] wire out_romask_177 = |_out_romask_T_177; // @[RegisterRouter.scala:87:24] wire out_womask_177 = &_out_womask_T_177; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_177 = out_rivalid_1_31 & out_rimask_177; // @[RegisterRouter.scala:87:24] wire _out_T_2190 = out_f_rivalid_177; // @[RegisterRouter.scala:87:24] wire out_f_roready_177 = out_roready_1_31 & out_romask_177; // @[RegisterRouter.scala:87:24] wire _out_T_2191 = out_f_roready_177; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_177 = out_wivalid_1_31 & out_wimask_177; // @[RegisterRouter.scala:87:24] wire out_f_woready_177 = out_woready_1_31 & out_womask_177; // @[RegisterRouter.scala:87:24] wire _out_T_2192 = ~out_rimask_177; // @[RegisterRouter.scala:87:24] wire _out_T_2193 = ~out_wimask_177; // @[RegisterRouter.scala:87:24] wire _out_T_2194 = ~out_romask_177; // @[RegisterRouter.scala:87:24] wire _out_T_2195 = ~out_womask_177; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_139 = {hi_344, flags_0_go, _out_prepend_T_139}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2196 = out_prepend_139; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2197 = _out_T_2196; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_170 = _out_T_2197; // @[MuxLiteral.scala:49:48] wire out_rimask_178 = |_out_rimask_T_178; // @[RegisterRouter.scala:87:24] wire out_wimask_178 = &_out_wimask_T_178; // @[RegisterRouter.scala:87:24] wire out_romask_178 = |_out_romask_T_178; // @[RegisterRouter.scala:87:24] wire out_womask_178 = &_out_womask_T_178; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_178 = out_rivalid_1_32 & out_rimask_178; // @[RegisterRouter.scala:87:24] wire _out_T_2199 = out_f_rivalid_178; // @[RegisterRouter.scala:87:24] wire out_f_roready_178 = out_roready_1_32 & out_romask_178; // @[RegisterRouter.scala:87:24] wire _out_T_2200 = out_f_roready_178; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_178 = out_wivalid_1_32 & out_wimask_178; // @[RegisterRouter.scala:87:24] wire _out_T_2201 = out_f_wivalid_178; // @[RegisterRouter.scala:87:24] wire out_f_woready_178 = out_woready_1_32 & out_womask_178; // @[RegisterRouter.scala:87:24] wire _out_T_2202 = out_f_woready_178; // @[RegisterRouter.scala:87:24] wire _out_T_2203 = ~out_rimask_178; // @[RegisterRouter.scala:87:24] wire _out_T_2204 = ~out_wimask_178; // @[RegisterRouter.scala:87:24] wire _out_T_2205 = ~out_romask_178; // @[RegisterRouter.scala:87:24] wire _out_T_2206 = ~out_womask_178; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2208 = _out_T_2207; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_140 = _out_T_2208; // @[RegisterRouter.scala:87:24] wire out_rimask_179 = |_out_rimask_T_179; // @[RegisterRouter.scala:87:24] wire out_wimask_179 = &_out_wimask_T_179; // @[RegisterRouter.scala:87:24] wire out_romask_179 = |_out_romask_T_179; // @[RegisterRouter.scala:87:24] wire out_womask_179 = &_out_womask_T_179; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_179 = out_rivalid_1_33 & out_rimask_179; // @[RegisterRouter.scala:87:24] wire _out_T_2210 = out_f_rivalid_179; // @[RegisterRouter.scala:87:24] wire out_f_roready_179 = out_roready_1_33 & out_romask_179; // @[RegisterRouter.scala:87:24] wire _out_T_2211 = out_f_roready_179; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_179 = out_wivalid_1_33 & out_wimask_179; // @[RegisterRouter.scala:87:24] wire _out_T_2212 = out_f_wivalid_179; // @[RegisterRouter.scala:87:24] wire out_f_woready_179 = out_woready_1_33 & out_womask_179; // @[RegisterRouter.scala:87:24] wire _out_T_2213 = out_f_woready_179; // @[RegisterRouter.scala:87:24] wire _out_T_2214 = ~out_rimask_179; // @[RegisterRouter.scala:87:24] wire _out_T_2215 = ~out_wimask_179; // @[RegisterRouter.scala:87:24] wire _out_T_2216 = ~out_romask_179; // @[RegisterRouter.scala:87:24] wire _out_T_2217 = ~out_womask_179; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_140 = {abstractDataMem_25, _out_prepend_T_140}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2218 = out_prepend_140; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2219 = _out_T_2218; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_141 = _out_T_2219; // @[RegisterRouter.scala:87:24] wire out_rimask_180 = |_out_rimask_T_180; // @[RegisterRouter.scala:87:24] wire out_wimask_180 = &_out_wimask_T_180; // @[RegisterRouter.scala:87:24] wire out_romask_180 = |_out_romask_T_180; // @[RegisterRouter.scala:87:24] wire out_womask_180 = &_out_womask_T_180; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_180 = out_rivalid_1_34 & out_rimask_180; // @[RegisterRouter.scala:87:24] wire _out_T_2221 = out_f_rivalid_180; // @[RegisterRouter.scala:87:24] wire out_f_roready_180 = out_roready_1_34 & out_romask_180; // @[RegisterRouter.scala:87:24] wire _out_T_2222 = out_f_roready_180; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_180 = out_wivalid_1_34 & out_wimask_180; // @[RegisterRouter.scala:87:24] wire _out_T_2223 = out_f_wivalid_180; // @[RegisterRouter.scala:87:24] wire out_f_woready_180 = out_woready_1_34 & out_womask_180; // @[RegisterRouter.scala:87:24] wire _out_T_2224 = out_f_woready_180; // @[RegisterRouter.scala:87:24] wire _out_T_2225 = ~out_rimask_180; // @[RegisterRouter.scala:87:24] wire _out_T_2226 = ~out_wimask_180; // @[RegisterRouter.scala:87:24] wire _out_T_2227 = ~out_romask_180; // @[RegisterRouter.scala:87:24] wire _out_T_2228 = ~out_womask_180; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_141 = {abstractDataMem_26, _out_prepend_T_141}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2229 = out_prepend_141; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2230 = _out_T_2229; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_142 = _out_T_2230; // @[RegisterRouter.scala:87:24] wire out_rimask_181 = |_out_rimask_T_181; // @[RegisterRouter.scala:87:24] wire out_wimask_181 = &_out_wimask_T_181; // @[RegisterRouter.scala:87:24] wire out_romask_181 = |_out_romask_T_181; // @[RegisterRouter.scala:87:24] wire out_womask_181 = &_out_womask_T_181; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_181 = out_rivalid_1_35 & out_rimask_181; // @[RegisterRouter.scala:87:24] wire _out_T_2232 = out_f_rivalid_181; // @[RegisterRouter.scala:87:24] wire out_f_roready_181 = out_roready_1_35 & out_romask_181; // @[RegisterRouter.scala:87:24] wire _out_T_2233 = out_f_roready_181; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_181 = out_wivalid_1_35 & out_wimask_181; // @[RegisterRouter.scala:87:24] wire _out_T_2234 = out_f_wivalid_181; // @[RegisterRouter.scala:87:24] wire out_f_woready_181 = out_woready_1_35 & out_womask_181; // @[RegisterRouter.scala:87:24] wire _out_T_2235 = out_f_woready_181; // @[RegisterRouter.scala:87:24] wire _out_T_2236 = ~out_rimask_181; // @[RegisterRouter.scala:87:24] wire _out_T_2237 = ~out_wimask_181; // @[RegisterRouter.scala:87:24] wire _out_T_2238 = ~out_romask_181; // @[RegisterRouter.scala:87:24] wire _out_T_2239 = ~out_womask_181; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_142 = {abstractDataMem_27, _out_prepend_T_142}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2240 = out_prepend_142; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2241 = _out_T_2240; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_143 = _out_T_2241; // @[RegisterRouter.scala:87:24] wire out_rimask_182 = |_out_rimask_T_182; // @[RegisterRouter.scala:87:24] wire out_wimask_182 = &_out_wimask_T_182; // @[RegisterRouter.scala:87:24] wire out_romask_182 = |_out_romask_T_182; // @[RegisterRouter.scala:87:24] wire out_womask_182 = &_out_womask_T_182; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_182 = out_rivalid_1_36 & out_rimask_182; // @[RegisterRouter.scala:87:24] wire _out_T_2243 = out_f_rivalid_182; // @[RegisterRouter.scala:87:24] wire out_f_roready_182 = out_roready_1_36 & out_romask_182; // @[RegisterRouter.scala:87:24] wire _out_T_2244 = out_f_roready_182; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_182 = out_wivalid_1_36 & out_wimask_182; // @[RegisterRouter.scala:87:24] wire _out_T_2245 = out_f_wivalid_182; // @[RegisterRouter.scala:87:24] wire out_f_woready_182 = out_woready_1_36 & out_womask_182; // @[RegisterRouter.scala:87:24] wire _out_T_2246 = out_f_woready_182; // @[RegisterRouter.scala:87:24] wire _out_T_2247 = ~out_rimask_182; // @[RegisterRouter.scala:87:24] wire _out_T_2248 = ~out_wimask_182; // @[RegisterRouter.scala:87:24] wire _out_T_2249 = ~out_romask_182; // @[RegisterRouter.scala:87:24] wire _out_T_2250 = ~out_womask_182; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_143 = {abstractDataMem_28, _out_prepend_T_143}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2251 = out_prepend_143; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2252 = _out_T_2251; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_144 = _out_T_2252; // @[RegisterRouter.scala:87:24] wire out_rimask_183 = |_out_rimask_T_183; // @[RegisterRouter.scala:87:24] wire out_wimask_183 = &_out_wimask_T_183; // @[RegisterRouter.scala:87:24] wire out_romask_183 = |_out_romask_T_183; // @[RegisterRouter.scala:87:24] wire out_womask_183 = &_out_womask_T_183; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_183 = out_rivalid_1_37 & out_rimask_183; // @[RegisterRouter.scala:87:24] wire _out_T_2254 = out_f_rivalid_183; // @[RegisterRouter.scala:87:24] wire out_f_roready_183 = out_roready_1_37 & out_romask_183; // @[RegisterRouter.scala:87:24] wire _out_T_2255 = out_f_roready_183; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_183 = out_wivalid_1_37 & out_wimask_183; // @[RegisterRouter.scala:87:24] wire _out_T_2256 = out_f_wivalid_183; // @[RegisterRouter.scala:87:24] wire out_f_woready_183 = out_woready_1_37 & out_womask_183; // @[RegisterRouter.scala:87:24] wire _out_T_2257 = out_f_woready_183; // @[RegisterRouter.scala:87:24] wire _out_T_2258 = ~out_rimask_183; // @[RegisterRouter.scala:87:24] wire _out_T_2259 = ~out_wimask_183; // @[RegisterRouter.scala:87:24] wire _out_T_2260 = ~out_romask_183; // @[RegisterRouter.scala:87:24] wire _out_T_2261 = ~out_womask_183; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_144 = {abstractDataMem_29, _out_prepend_T_144}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2262 = out_prepend_144; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2263 = _out_T_2262; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_145 = _out_T_2263; // @[RegisterRouter.scala:87:24] wire out_rimask_184 = |_out_rimask_T_184; // @[RegisterRouter.scala:87:24] wire out_wimask_184 = &_out_wimask_T_184; // @[RegisterRouter.scala:87:24] wire out_romask_184 = |_out_romask_T_184; // @[RegisterRouter.scala:87:24] wire out_womask_184 = &_out_womask_T_184; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_184 = out_rivalid_1_38 & out_rimask_184; // @[RegisterRouter.scala:87:24] wire _out_T_2265 = out_f_rivalid_184; // @[RegisterRouter.scala:87:24] wire out_f_roready_184 = out_roready_1_38 & out_romask_184; // @[RegisterRouter.scala:87:24] wire _out_T_2266 = out_f_roready_184; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_184 = out_wivalid_1_38 & out_wimask_184; // @[RegisterRouter.scala:87:24] wire _out_T_2267 = out_f_wivalid_184; // @[RegisterRouter.scala:87:24] wire out_f_woready_184 = out_woready_1_38 & out_womask_184; // @[RegisterRouter.scala:87:24] wire _out_T_2268 = out_f_woready_184; // @[RegisterRouter.scala:87:24] wire _out_T_2269 = ~out_rimask_184; // @[RegisterRouter.scala:87:24] wire _out_T_2270 = ~out_wimask_184; // @[RegisterRouter.scala:87:24] wire _out_T_2271 = ~out_romask_184; // @[RegisterRouter.scala:87:24] wire _out_T_2272 = ~out_womask_184; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_145 = {abstractDataMem_30, _out_prepend_T_145}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2273 = out_prepend_145; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2274 = _out_T_2273; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_146 = _out_T_2274; // @[RegisterRouter.scala:87:24] wire out_rimask_185 = |_out_rimask_T_185; // @[RegisterRouter.scala:87:24] wire out_wimask_185 = &_out_wimask_T_185; // @[RegisterRouter.scala:87:24] wire out_romask_185 = |_out_romask_T_185; // @[RegisterRouter.scala:87:24] wire out_womask_185 = &_out_womask_T_185; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_185 = out_rivalid_1_39 & out_rimask_185; // @[RegisterRouter.scala:87:24] wire _out_T_2276 = out_f_rivalid_185; // @[RegisterRouter.scala:87:24] wire out_f_roready_185 = out_roready_1_39 & out_romask_185; // @[RegisterRouter.scala:87:24] wire _out_T_2277 = out_f_roready_185; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_185 = out_wivalid_1_39 & out_wimask_185; // @[RegisterRouter.scala:87:24] wire _out_T_2278 = out_f_wivalid_185; // @[RegisterRouter.scala:87:24] wire out_f_woready_185 = out_woready_1_39 & out_womask_185; // @[RegisterRouter.scala:87:24] wire _out_T_2279 = out_f_woready_185; // @[RegisterRouter.scala:87:24] wire _out_T_2280 = ~out_rimask_185; // @[RegisterRouter.scala:87:24] wire _out_T_2281 = ~out_wimask_185; // @[RegisterRouter.scala:87:24] wire _out_T_2282 = ~out_romask_185; // @[RegisterRouter.scala:87:24] wire _out_T_2283 = ~out_womask_185; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_146 = {abstractDataMem_31, _out_prepend_T_146}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2284 = out_prepend_146; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2285 = _out_T_2284; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_115 = _out_T_2285; // @[MuxLiteral.scala:49:48] wire out_rimask_186 = |_out_rimask_T_186; // @[RegisterRouter.scala:87:24] wire out_wimask_186 = &_out_wimask_T_186; // @[RegisterRouter.scala:87:24] wire out_romask_186 = |_out_romask_T_186; // @[RegisterRouter.scala:87:24] wire out_womask_186 = &_out_womask_T_186; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_186 = out_rivalid_1_40 & out_rimask_186; // @[RegisterRouter.scala:87:24] wire _out_T_2287 = out_f_rivalid_186; // @[RegisterRouter.scala:87:24] wire out_f_roready_186 = out_roready_1_40 & out_romask_186; // @[RegisterRouter.scala:87:24] wire _out_T_2288 = out_f_roready_186; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_186 = out_wivalid_1_40 & out_wimask_186; // @[RegisterRouter.scala:87:24] wire out_f_woready_186 = out_woready_1_40 & out_womask_186; // @[RegisterRouter.scala:87:24] wire _out_T_2289 = ~out_rimask_186; // @[RegisterRouter.scala:87:24] wire _out_T_2290 = ~out_wimask_186; // @[RegisterRouter.scala:87:24] wire _out_T_2291 = ~out_romask_186; // @[RegisterRouter.scala:87:24] wire _out_T_2292 = ~out_womask_186; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2294 = _out_T_2293; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_147 = _out_T_2294; // @[RegisterRouter.scala:87:24] wire out_rimask_187 = |_out_rimask_T_187; // @[RegisterRouter.scala:87:24] wire out_wimask_187 = &_out_wimask_T_187; // @[RegisterRouter.scala:87:24] wire out_romask_187 = |_out_romask_T_187; // @[RegisterRouter.scala:87:24] wire out_womask_187 = &_out_womask_T_187; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_187 = out_rivalid_1_41 & out_rimask_187; // @[RegisterRouter.scala:87:24] wire _out_T_2296 = out_f_rivalid_187; // @[RegisterRouter.scala:87:24] wire out_f_roready_187 = out_roready_1_41 & out_romask_187; // @[RegisterRouter.scala:87:24] wire _out_T_2297 = out_f_roready_187; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_187 = out_wivalid_1_41 & out_wimask_187; // @[RegisterRouter.scala:87:24] wire out_f_woready_187 = out_woready_1_41 & out_womask_187; // @[RegisterRouter.scala:87:24] wire _out_T_2298 = ~out_rimask_187; // @[RegisterRouter.scala:87:24] wire _out_T_2299 = ~out_wimask_187; // @[RegisterRouter.scala:87:24] wire _out_T_2300 = ~out_romask_187; // @[RegisterRouter.scala:87:24] wire _out_T_2301 = ~out_womask_187; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_147 = {hi_714, flags_0_go, _out_prepend_T_147}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2302 = out_prepend_147; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2303 = _out_T_2302; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_148 = _out_T_2303; // @[RegisterRouter.scala:87:24] wire out_rimask_188 = |_out_rimask_T_188; // @[RegisterRouter.scala:87:24] wire out_wimask_188 = &_out_wimask_T_188; // @[RegisterRouter.scala:87:24] wire out_romask_188 = |_out_romask_T_188; // @[RegisterRouter.scala:87:24] wire out_womask_188 = &_out_womask_T_188; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_188 = out_rivalid_1_42 & out_rimask_188; // @[RegisterRouter.scala:87:24] wire _out_T_2305 = out_f_rivalid_188; // @[RegisterRouter.scala:87:24] wire out_f_roready_188 = out_roready_1_42 & out_romask_188; // @[RegisterRouter.scala:87:24] wire _out_T_2306 = out_f_roready_188; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_188 = out_wivalid_1_42 & out_wimask_188; // @[RegisterRouter.scala:87:24] wire out_f_woready_188 = out_woready_1_42 & out_womask_188; // @[RegisterRouter.scala:87:24] wire _out_T_2307 = ~out_rimask_188; // @[RegisterRouter.scala:87:24] wire _out_T_2308 = ~out_wimask_188; // @[RegisterRouter.scala:87:24] wire _out_T_2309 = ~out_romask_188; // @[RegisterRouter.scala:87:24] wire _out_T_2310 = ~out_womask_188; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_148 = {hi_715, flags_0_go, _out_prepend_T_148}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2311 = out_prepend_148; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2312 = _out_T_2311; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_149 = _out_T_2312; // @[RegisterRouter.scala:87:24] wire out_rimask_189 = |_out_rimask_T_189; // @[RegisterRouter.scala:87:24] wire out_wimask_189 = &_out_wimask_T_189; // @[RegisterRouter.scala:87:24] wire out_romask_189 = |_out_romask_T_189; // @[RegisterRouter.scala:87:24] wire out_womask_189 = &_out_womask_T_189; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_189 = out_rivalid_1_43 & out_rimask_189; // @[RegisterRouter.scala:87:24] wire _out_T_2314 = out_f_rivalid_189; // @[RegisterRouter.scala:87:24] wire out_f_roready_189 = out_roready_1_43 & out_romask_189; // @[RegisterRouter.scala:87:24] wire _out_T_2315 = out_f_roready_189; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_189 = out_wivalid_1_43 & out_wimask_189; // @[RegisterRouter.scala:87:24] wire out_f_woready_189 = out_woready_1_43 & out_womask_189; // @[RegisterRouter.scala:87:24] wire _out_T_2316 = ~out_rimask_189; // @[RegisterRouter.scala:87:24] wire _out_T_2317 = ~out_wimask_189; // @[RegisterRouter.scala:87:24] wire _out_T_2318 = ~out_romask_189; // @[RegisterRouter.scala:87:24] wire _out_T_2319 = ~out_womask_189; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_149 = {hi_716, flags_0_go, _out_prepend_T_149}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2320 = out_prepend_149; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2321 = _out_T_2320; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_150 = _out_T_2321; // @[RegisterRouter.scala:87:24] wire out_rimask_190 = |_out_rimask_T_190; // @[RegisterRouter.scala:87:24] wire out_wimask_190 = &_out_wimask_T_190; // @[RegisterRouter.scala:87:24] wire out_romask_190 = |_out_romask_T_190; // @[RegisterRouter.scala:87:24] wire out_womask_190 = &_out_womask_T_190; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_190 = out_rivalid_1_44 & out_rimask_190; // @[RegisterRouter.scala:87:24] wire _out_T_2323 = out_f_rivalid_190; // @[RegisterRouter.scala:87:24] wire out_f_roready_190 = out_roready_1_44 & out_romask_190; // @[RegisterRouter.scala:87:24] wire _out_T_2324 = out_f_roready_190; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_190 = out_wivalid_1_44 & out_wimask_190; // @[RegisterRouter.scala:87:24] wire out_f_woready_190 = out_woready_1_44 & out_womask_190; // @[RegisterRouter.scala:87:24] wire _out_T_2325 = ~out_rimask_190; // @[RegisterRouter.scala:87:24] wire _out_T_2326 = ~out_wimask_190; // @[RegisterRouter.scala:87:24] wire _out_T_2327 = ~out_romask_190; // @[RegisterRouter.scala:87:24] wire _out_T_2328 = ~out_womask_190; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_150 = {hi_717, flags_0_go, _out_prepend_T_150}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2329 = out_prepend_150; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2330 = _out_T_2329; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_151 = _out_T_2330; // @[RegisterRouter.scala:87:24] wire out_rimask_191 = |_out_rimask_T_191; // @[RegisterRouter.scala:87:24] wire out_wimask_191 = &_out_wimask_T_191; // @[RegisterRouter.scala:87:24] wire out_romask_191 = |_out_romask_T_191; // @[RegisterRouter.scala:87:24] wire out_womask_191 = &_out_womask_T_191; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_191 = out_rivalid_1_45 & out_rimask_191; // @[RegisterRouter.scala:87:24] wire _out_T_2332 = out_f_rivalid_191; // @[RegisterRouter.scala:87:24] wire out_f_roready_191 = out_roready_1_45 & out_romask_191; // @[RegisterRouter.scala:87:24] wire _out_T_2333 = out_f_roready_191; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_191 = out_wivalid_1_45 & out_wimask_191; // @[RegisterRouter.scala:87:24] wire out_f_woready_191 = out_woready_1_45 & out_womask_191; // @[RegisterRouter.scala:87:24] wire _out_T_2334 = ~out_rimask_191; // @[RegisterRouter.scala:87:24] wire _out_T_2335 = ~out_wimask_191; // @[RegisterRouter.scala:87:24] wire _out_T_2336 = ~out_romask_191; // @[RegisterRouter.scala:87:24] wire _out_T_2337 = ~out_womask_191; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_151 = {hi_718, flags_0_go, _out_prepend_T_151}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2338 = out_prepend_151; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2339 = _out_T_2338; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_152 = _out_T_2339; // @[RegisterRouter.scala:87:24] wire out_rimask_192 = |_out_rimask_T_192; // @[RegisterRouter.scala:87:24] wire out_wimask_192 = &_out_wimask_T_192; // @[RegisterRouter.scala:87:24] wire out_romask_192 = |_out_romask_T_192; // @[RegisterRouter.scala:87:24] wire out_womask_192 = &_out_womask_T_192; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_192 = out_rivalid_1_46 & out_rimask_192; // @[RegisterRouter.scala:87:24] wire _out_T_2341 = out_f_rivalid_192; // @[RegisterRouter.scala:87:24] wire out_f_roready_192 = out_roready_1_46 & out_romask_192; // @[RegisterRouter.scala:87:24] wire _out_T_2342 = out_f_roready_192; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_192 = out_wivalid_1_46 & out_wimask_192; // @[RegisterRouter.scala:87:24] wire out_f_woready_192 = out_woready_1_46 & out_womask_192; // @[RegisterRouter.scala:87:24] wire _out_T_2343 = ~out_rimask_192; // @[RegisterRouter.scala:87:24] wire _out_T_2344 = ~out_wimask_192; // @[RegisterRouter.scala:87:24] wire _out_T_2345 = ~out_romask_192; // @[RegisterRouter.scala:87:24] wire _out_T_2346 = ~out_womask_192; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_152 = {hi_719, flags_0_go, _out_prepend_T_152}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2347 = out_prepend_152; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2348 = _out_T_2347; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_153 = _out_T_2348; // @[RegisterRouter.scala:87:24] wire out_rimask_193 = |_out_rimask_T_193; // @[RegisterRouter.scala:87:24] wire out_wimask_193 = &_out_wimask_T_193; // @[RegisterRouter.scala:87:24] wire out_romask_193 = |_out_romask_T_193; // @[RegisterRouter.scala:87:24] wire out_womask_193 = &_out_womask_T_193; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_193 = out_rivalid_1_47 & out_rimask_193; // @[RegisterRouter.scala:87:24] wire _out_T_2350 = out_f_rivalid_193; // @[RegisterRouter.scala:87:24] wire out_f_roready_193 = out_roready_1_47 & out_romask_193; // @[RegisterRouter.scala:87:24] wire _out_T_2351 = out_f_roready_193; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_193 = out_wivalid_1_47 & out_wimask_193; // @[RegisterRouter.scala:87:24] wire out_f_woready_193 = out_woready_1_47 & out_womask_193; // @[RegisterRouter.scala:87:24] wire _out_T_2352 = ~out_rimask_193; // @[RegisterRouter.scala:87:24] wire _out_T_2353 = ~out_wimask_193; // @[RegisterRouter.scala:87:24] wire _out_T_2354 = ~out_romask_193; // @[RegisterRouter.scala:87:24] wire _out_T_2355 = ~out_womask_193; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_153 = {hi_720, flags_0_go, _out_prepend_T_153}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2356 = out_prepend_153; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2357 = _out_T_2356; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_217 = _out_T_2357; // @[MuxLiteral.scala:49:48] wire out_rimask_194 = |_out_rimask_T_194; // @[RegisterRouter.scala:87:24] wire out_wimask_194 = &_out_wimask_T_194; // @[RegisterRouter.scala:87:24] wire out_romask_194 = |_out_romask_T_194; // @[RegisterRouter.scala:87:24] wire out_womask_194 = &_out_womask_T_194; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_194 = out_rivalid_1_48 & out_rimask_194; // @[RegisterRouter.scala:87:24] wire _out_T_2359 = out_f_rivalid_194; // @[RegisterRouter.scala:87:24] wire out_f_roready_194 = out_roready_1_48 & out_romask_194; // @[RegisterRouter.scala:87:24] wire _out_T_2360 = out_f_roready_194; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_194 = out_wivalid_1_48 & out_wimask_194; // @[RegisterRouter.scala:87:24] wire out_f_woready_194 = out_woready_1_48 & out_womask_194; // @[RegisterRouter.scala:87:24] wire _out_T_2361 = ~out_rimask_194; // @[RegisterRouter.scala:87:24] wire _out_T_2362 = ~out_wimask_194; // @[RegisterRouter.scala:87:24] wire _out_T_2363 = ~out_romask_194; // @[RegisterRouter.scala:87:24] wire _out_T_2364 = ~out_womask_194; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2366 = _out_T_2365; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_154 = _out_T_2366; // @[RegisterRouter.scala:87:24] wire out_rimask_195 = |_out_rimask_T_195; // @[RegisterRouter.scala:87:24] wire out_wimask_195 = &_out_wimask_T_195; // @[RegisterRouter.scala:87:24] wire out_romask_195 = |_out_romask_T_195; // @[RegisterRouter.scala:87:24] wire out_womask_195 = &_out_womask_T_195; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_195 = out_rivalid_1_49 & out_rimask_195; // @[RegisterRouter.scala:87:24] wire _out_T_2368 = out_f_rivalid_195; // @[RegisterRouter.scala:87:24] wire out_f_roready_195 = out_roready_1_49 & out_romask_195; // @[RegisterRouter.scala:87:24] wire _out_T_2369 = out_f_roready_195; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_195 = out_wivalid_1_49 & out_wimask_195; // @[RegisterRouter.scala:87:24] wire out_f_woready_195 = out_woready_1_49 & out_womask_195; // @[RegisterRouter.scala:87:24] wire _out_T_2370 = ~out_rimask_195; // @[RegisterRouter.scala:87:24] wire _out_T_2371 = ~out_wimask_195; // @[RegisterRouter.scala:87:24] wire _out_T_2372 = ~out_romask_195; // @[RegisterRouter.scala:87:24] wire _out_T_2373 = ~out_womask_195; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_154 = {hi_954, flags_0_go, _out_prepend_T_154}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2374 = out_prepend_154; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2375 = _out_T_2374; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_155 = _out_T_2375; // @[RegisterRouter.scala:87:24] wire out_rimask_196 = |_out_rimask_T_196; // @[RegisterRouter.scala:87:24] wire out_wimask_196 = &_out_wimask_T_196; // @[RegisterRouter.scala:87:24] wire out_romask_196 = |_out_romask_T_196; // @[RegisterRouter.scala:87:24] wire out_womask_196 = &_out_womask_T_196; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_196 = out_rivalid_1_50 & out_rimask_196; // @[RegisterRouter.scala:87:24] wire _out_T_2377 = out_f_rivalid_196; // @[RegisterRouter.scala:87:24] wire out_f_roready_196 = out_roready_1_50 & out_romask_196; // @[RegisterRouter.scala:87:24] wire _out_T_2378 = out_f_roready_196; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_196 = out_wivalid_1_50 & out_wimask_196; // @[RegisterRouter.scala:87:24] wire out_f_woready_196 = out_woready_1_50 & out_womask_196; // @[RegisterRouter.scala:87:24] wire _out_T_2379 = ~out_rimask_196; // @[RegisterRouter.scala:87:24] wire _out_T_2380 = ~out_wimask_196; // @[RegisterRouter.scala:87:24] wire _out_T_2381 = ~out_romask_196; // @[RegisterRouter.scala:87:24] wire _out_T_2382 = ~out_womask_196; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_155 = {hi_955, flags_0_go, _out_prepend_T_155}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2383 = out_prepend_155; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2384 = _out_T_2383; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_156 = _out_T_2384; // @[RegisterRouter.scala:87:24] wire out_rimask_197 = |_out_rimask_T_197; // @[RegisterRouter.scala:87:24] wire out_wimask_197 = &_out_wimask_T_197; // @[RegisterRouter.scala:87:24] wire out_romask_197 = |_out_romask_T_197; // @[RegisterRouter.scala:87:24] wire out_womask_197 = &_out_womask_T_197; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_197 = out_rivalid_1_51 & out_rimask_197; // @[RegisterRouter.scala:87:24] wire _out_T_2386 = out_f_rivalid_197; // @[RegisterRouter.scala:87:24] wire out_f_roready_197 = out_roready_1_51 & out_romask_197; // @[RegisterRouter.scala:87:24] wire _out_T_2387 = out_f_roready_197; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_197 = out_wivalid_1_51 & out_wimask_197; // @[RegisterRouter.scala:87:24] wire out_f_woready_197 = out_woready_1_51 & out_womask_197; // @[RegisterRouter.scala:87:24] wire _out_T_2388 = ~out_rimask_197; // @[RegisterRouter.scala:87:24] wire _out_T_2389 = ~out_wimask_197; // @[RegisterRouter.scala:87:24] wire _out_T_2390 = ~out_romask_197; // @[RegisterRouter.scala:87:24] wire _out_T_2391 = ~out_womask_197; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_156 = {hi_956, flags_0_go, _out_prepend_T_156}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2392 = out_prepend_156; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2393 = _out_T_2392; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_157 = _out_T_2393; // @[RegisterRouter.scala:87:24] wire out_rimask_198 = |_out_rimask_T_198; // @[RegisterRouter.scala:87:24] wire out_wimask_198 = &_out_wimask_T_198; // @[RegisterRouter.scala:87:24] wire out_romask_198 = |_out_romask_T_198; // @[RegisterRouter.scala:87:24] wire out_womask_198 = &_out_womask_T_198; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_198 = out_rivalid_1_52 & out_rimask_198; // @[RegisterRouter.scala:87:24] wire _out_T_2395 = out_f_rivalid_198; // @[RegisterRouter.scala:87:24] wire out_f_roready_198 = out_roready_1_52 & out_romask_198; // @[RegisterRouter.scala:87:24] wire _out_T_2396 = out_f_roready_198; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_198 = out_wivalid_1_52 & out_wimask_198; // @[RegisterRouter.scala:87:24] wire out_f_woready_198 = out_woready_1_52 & out_womask_198; // @[RegisterRouter.scala:87:24] wire _out_T_2397 = ~out_rimask_198; // @[RegisterRouter.scala:87:24] wire _out_T_2398 = ~out_wimask_198; // @[RegisterRouter.scala:87:24] wire _out_T_2399 = ~out_romask_198; // @[RegisterRouter.scala:87:24] wire _out_T_2400 = ~out_womask_198; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_157 = {hi_957, flags_0_go, _out_prepend_T_157}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2401 = out_prepend_157; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2402 = _out_T_2401; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_158 = _out_T_2402; // @[RegisterRouter.scala:87:24] wire out_rimask_199 = |_out_rimask_T_199; // @[RegisterRouter.scala:87:24] wire out_wimask_199 = &_out_wimask_T_199; // @[RegisterRouter.scala:87:24] wire out_romask_199 = |_out_romask_T_199; // @[RegisterRouter.scala:87:24] wire out_womask_199 = &_out_womask_T_199; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_199 = out_rivalid_1_53 & out_rimask_199; // @[RegisterRouter.scala:87:24] wire _out_T_2404 = out_f_rivalid_199; // @[RegisterRouter.scala:87:24] wire out_f_roready_199 = out_roready_1_53 & out_romask_199; // @[RegisterRouter.scala:87:24] wire _out_T_2405 = out_f_roready_199; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_199 = out_wivalid_1_53 & out_wimask_199; // @[RegisterRouter.scala:87:24] wire out_f_woready_199 = out_woready_1_53 & out_womask_199; // @[RegisterRouter.scala:87:24] wire _out_T_2406 = ~out_rimask_199; // @[RegisterRouter.scala:87:24] wire _out_T_2407 = ~out_wimask_199; // @[RegisterRouter.scala:87:24] wire _out_T_2408 = ~out_romask_199; // @[RegisterRouter.scala:87:24] wire _out_T_2409 = ~out_womask_199; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_158 = {hi_958, flags_0_go, _out_prepend_T_158}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2410 = out_prepend_158; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2411 = _out_T_2410; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_159 = _out_T_2411; // @[RegisterRouter.scala:87:24] wire out_rimask_200 = |_out_rimask_T_200; // @[RegisterRouter.scala:87:24] wire out_wimask_200 = &_out_wimask_T_200; // @[RegisterRouter.scala:87:24] wire out_romask_200 = |_out_romask_T_200; // @[RegisterRouter.scala:87:24] wire out_womask_200 = &_out_womask_T_200; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_200 = out_rivalid_1_54 & out_rimask_200; // @[RegisterRouter.scala:87:24] wire _out_T_2413 = out_f_rivalid_200; // @[RegisterRouter.scala:87:24] wire out_f_roready_200 = out_roready_1_54 & out_romask_200; // @[RegisterRouter.scala:87:24] wire _out_T_2414 = out_f_roready_200; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_200 = out_wivalid_1_54 & out_wimask_200; // @[RegisterRouter.scala:87:24] wire out_f_woready_200 = out_woready_1_54 & out_womask_200; // @[RegisterRouter.scala:87:24] wire _out_T_2415 = ~out_rimask_200; // @[RegisterRouter.scala:87:24] wire _out_T_2416 = ~out_wimask_200; // @[RegisterRouter.scala:87:24] wire _out_T_2417 = ~out_romask_200; // @[RegisterRouter.scala:87:24] wire _out_T_2418 = ~out_womask_200; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_159 = {hi_959, flags_0_go, _out_prepend_T_159}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2419 = out_prepend_159; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2420 = _out_T_2419; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_160 = _out_T_2420; // @[RegisterRouter.scala:87:24] wire out_rimask_201 = |_out_rimask_T_201; // @[RegisterRouter.scala:87:24] wire out_wimask_201 = &_out_wimask_T_201; // @[RegisterRouter.scala:87:24] wire out_romask_201 = |_out_romask_T_201; // @[RegisterRouter.scala:87:24] wire out_womask_201 = &_out_womask_T_201; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_201 = out_rivalid_1_55 & out_rimask_201; // @[RegisterRouter.scala:87:24] wire _out_T_2422 = out_f_rivalid_201; // @[RegisterRouter.scala:87:24] wire out_f_roready_201 = out_roready_1_55 & out_romask_201; // @[RegisterRouter.scala:87:24] wire _out_T_2423 = out_f_roready_201; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_201 = out_wivalid_1_55 & out_wimask_201; // @[RegisterRouter.scala:87:24] wire out_f_woready_201 = out_woready_1_55 & out_womask_201; // @[RegisterRouter.scala:87:24] wire _out_T_2424 = ~out_rimask_201; // @[RegisterRouter.scala:87:24] wire _out_T_2425 = ~out_wimask_201; // @[RegisterRouter.scala:87:24] wire _out_T_2426 = ~out_romask_201; // @[RegisterRouter.scala:87:24] wire _out_T_2427 = ~out_womask_201; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_160 = {hi_960, flags_0_go, _out_prepend_T_160}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2428 = out_prepend_160; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2429 = _out_T_2428; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_247 = _out_T_2429; // @[MuxLiteral.scala:49:48] wire out_rimask_202 = |_out_rimask_T_202; // @[RegisterRouter.scala:87:24] wire out_wimask_202 = &_out_wimask_T_202; // @[RegisterRouter.scala:87:24] wire out_romask_202 = |_out_romask_T_202; // @[RegisterRouter.scala:87:24] wire out_womask_202 = &_out_womask_T_202; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_202 = out_rivalid_1_56 & out_rimask_202; // @[RegisterRouter.scala:87:24] wire _out_T_2431 = out_f_rivalid_202; // @[RegisterRouter.scala:87:24] wire out_f_roready_202 = out_roready_1_56 & out_romask_202; // @[RegisterRouter.scala:87:24] wire _out_T_2432 = out_f_roready_202; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_202 = out_wivalid_1_56 & out_wimask_202; // @[RegisterRouter.scala:87:24] wire out_f_woready_202 = out_woready_1_56 & out_womask_202; // @[RegisterRouter.scala:87:24] wire _out_T_2433 = ~out_rimask_202; // @[RegisterRouter.scala:87:24] wire _out_T_2434 = ~out_wimask_202; // @[RegisterRouter.scala:87:24] wire _out_T_2435 = ~out_romask_202; // @[RegisterRouter.scala:87:24] wire _out_T_2436 = ~out_womask_202; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2438 = _out_T_2437; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_161 = _out_T_2438; // @[RegisterRouter.scala:87:24] wire out_rimask_203 = |_out_rimask_T_203; // @[RegisterRouter.scala:87:24] wire out_wimask_203 = &_out_wimask_T_203; // @[RegisterRouter.scala:87:24] wire out_romask_203 = |_out_romask_T_203; // @[RegisterRouter.scala:87:24] wire out_womask_203 = &_out_womask_T_203; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_203 = out_rivalid_1_57 & out_rimask_203; // @[RegisterRouter.scala:87:24] wire _out_T_2440 = out_f_rivalid_203; // @[RegisterRouter.scala:87:24] wire out_f_roready_203 = out_roready_1_57 & out_romask_203; // @[RegisterRouter.scala:87:24] wire _out_T_2441 = out_f_roready_203; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_203 = out_wivalid_1_57 & out_wimask_203; // @[RegisterRouter.scala:87:24] wire out_f_woready_203 = out_woready_1_57 & out_womask_203; // @[RegisterRouter.scala:87:24] wire _out_T_2442 = ~out_rimask_203; // @[RegisterRouter.scala:87:24] wire _out_T_2443 = ~out_wimask_203; // @[RegisterRouter.scala:87:24] wire _out_T_2444 = ~out_romask_203; // @[RegisterRouter.scala:87:24] wire _out_T_2445 = ~out_womask_203; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_161 = {hi_594, flags_0_go, _out_prepend_T_161}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2446 = out_prepend_161; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2447 = _out_T_2446; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_162 = _out_T_2447; // @[RegisterRouter.scala:87:24] wire out_rimask_204 = |_out_rimask_T_204; // @[RegisterRouter.scala:87:24] wire out_wimask_204 = &_out_wimask_T_204; // @[RegisterRouter.scala:87:24] wire out_romask_204 = |_out_romask_T_204; // @[RegisterRouter.scala:87:24] wire out_womask_204 = &_out_womask_T_204; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_204 = out_rivalid_1_58 & out_rimask_204; // @[RegisterRouter.scala:87:24] wire _out_T_2449 = out_f_rivalid_204; // @[RegisterRouter.scala:87:24] wire out_f_roready_204 = out_roready_1_58 & out_romask_204; // @[RegisterRouter.scala:87:24] wire _out_T_2450 = out_f_roready_204; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_204 = out_wivalid_1_58 & out_wimask_204; // @[RegisterRouter.scala:87:24] wire out_f_woready_204 = out_woready_1_58 & out_womask_204; // @[RegisterRouter.scala:87:24] wire _out_T_2451 = ~out_rimask_204; // @[RegisterRouter.scala:87:24] wire _out_T_2452 = ~out_wimask_204; // @[RegisterRouter.scala:87:24] wire _out_T_2453 = ~out_romask_204; // @[RegisterRouter.scala:87:24] wire _out_T_2454 = ~out_womask_204; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_162 = {hi_595, flags_0_go, _out_prepend_T_162}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2455 = out_prepend_162; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2456 = _out_T_2455; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_163 = _out_T_2456; // @[RegisterRouter.scala:87:24] wire out_rimask_205 = |_out_rimask_T_205; // @[RegisterRouter.scala:87:24] wire out_wimask_205 = &_out_wimask_T_205; // @[RegisterRouter.scala:87:24] wire out_romask_205 = |_out_romask_T_205; // @[RegisterRouter.scala:87:24] wire out_womask_205 = &_out_womask_T_205; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_205 = out_rivalid_1_59 & out_rimask_205; // @[RegisterRouter.scala:87:24] wire _out_T_2458 = out_f_rivalid_205; // @[RegisterRouter.scala:87:24] wire out_f_roready_205 = out_roready_1_59 & out_romask_205; // @[RegisterRouter.scala:87:24] wire _out_T_2459 = out_f_roready_205; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_205 = out_wivalid_1_59 & out_wimask_205; // @[RegisterRouter.scala:87:24] wire out_f_woready_205 = out_woready_1_59 & out_womask_205; // @[RegisterRouter.scala:87:24] wire _out_T_2460 = ~out_rimask_205; // @[RegisterRouter.scala:87:24] wire _out_T_2461 = ~out_wimask_205; // @[RegisterRouter.scala:87:24] wire _out_T_2462 = ~out_romask_205; // @[RegisterRouter.scala:87:24] wire _out_T_2463 = ~out_womask_205; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_163 = {hi_596, flags_0_go, _out_prepend_T_163}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2464 = out_prepend_163; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2465 = _out_T_2464; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_164 = _out_T_2465; // @[RegisterRouter.scala:87:24] wire out_rimask_206 = |_out_rimask_T_206; // @[RegisterRouter.scala:87:24] wire out_wimask_206 = &_out_wimask_T_206; // @[RegisterRouter.scala:87:24] wire out_romask_206 = |_out_romask_T_206; // @[RegisterRouter.scala:87:24] wire out_womask_206 = &_out_womask_T_206; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_206 = out_rivalid_1_60 & out_rimask_206; // @[RegisterRouter.scala:87:24] wire _out_T_2467 = out_f_rivalid_206; // @[RegisterRouter.scala:87:24] wire out_f_roready_206 = out_roready_1_60 & out_romask_206; // @[RegisterRouter.scala:87:24] wire _out_T_2468 = out_f_roready_206; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_206 = out_wivalid_1_60 & out_wimask_206; // @[RegisterRouter.scala:87:24] wire out_f_woready_206 = out_woready_1_60 & out_womask_206; // @[RegisterRouter.scala:87:24] wire _out_T_2469 = ~out_rimask_206; // @[RegisterRouter.scala:87:24] wire _out_T_2470 = ~out_wimask_206; // @[RegisterRouter.scala:87:24] wire _out_T_2471 = ~out_romask_206; // @[RegisterRouter.scala:87:24] wire _out_T_2472 = ~out_womask_206; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_164 = {hi_597, flags_0_go, _out_prepend_T_164}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2473 = out_prepend_164; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2474 = _out_T_2473; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_165 = _out_T_2474; // @[RegisterRouter.scala:87:24] wire out_rimask_207 = |_out_rimask_T_207; // @[RegisterRouter.scala:87:24] wire out_wimask_207 = &_out_wimask_T_207; // @[RegisterRouter.scala:87:24] wire out_romask_207 = |_out_romask_T_207; // @[RegisterRouter.scala:87:24] wire out_womask_207 = &_out_womask_T_207; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_207 = out_rivalid_1_61 & out_rimask_207; // @[RegisterRouter.scala:87:24] wire _out_T_2476 = out_f_rivalid_207; // @[RegisterRouter.scala:87:24] wire out_f_roready_207 = out_roready_1_61 & out_romask_207; // @[RegisterRouter.scala:87:24] wire _out_T_2477 = out_f_roready_207; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_207 = out_wivalid_1_61 & out_wimask_207; // @[RegisterRouter.scala:87:24] wire out_f_woready_207 = out_woready_1_61 & out_womask_207; // @[RegisterRouter.scala:87:24] wire _out_T_2478 = ~out_rimask_207; // @[RegisterRouter.scala:87:24] wire _out_T_2479 = ~out_wimask_207; // @[RegisterRouter.scala:87:24] wire _out_T_2480 = ~out_romask_207; // @[RegisterRouter.scala:87:24] wire _out_T_2481 = ~out_womask_207; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_165 = {hi_598, flags_0_go, _out_prepend_T_165}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2482 = out_prepend_165; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2483 = _out_T_2482; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_166 = _out_T_2483; // @[RegisterRouter.scala:87:24] wire out_rimask_208 = |_out_rimask_T_208; // @[RegisterRouter.scala:87:24] wire out_wimask_208 = &_out_wimask_T_208; // @[RegisterRouter.scala:87:24] wire out_romask_208 = |_out_romask_T_208; // @[RegisterRouter.scala:87:24] wire out_womask_208 = &_out_womask_T_208; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_208 = out_rivalid_1_62 & out_rimask_208; // @[RegisterRouter.scala:87:24] wire _out_T_2485 = out_f_rivalid_208; // @[RegisterRouter.scala:87:24] wire out_f_roready_208 = out_roready_1_62 & out_romask_208; // @[RegisterRouter.scala:87:24] wire _out_T_2486 = out_f_roready_208; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_208 = out_wivalid_1_62 & out_wimask_208; // @[RegisterRouter.scala:87:24] wire out_f_woready_208 = out_woready_1_62 & out_womask_208; // @[RegisterRouter.scala:87:24] wire _out_T_2487 = ~out_rimask_208; // @[RegisterRouter.scala:87:24] wire _out_T_2488 = ~out_wimask_208; // @[RegisterRouter.scala:87:24] wire _out_T_2489 = ~out_romask_208; // @[RegisterRouter.scala:87:24] wire _out_T_2490 = ~out_womask_208; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_166 = {hi_599, flags_0_go, _out_prepend_T_166}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2491 = out_prepend_166; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2492 = _out_T_2491; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_167 = _out_T_2492; // @[RegisterRouter.scala:87:24] wire out_rimask_209 = |_out_rimask_T_209; // @[RegisterRouter.scala:87:24] wire out_wimask_209 = &_out_wimask_T_209; // @[RegisterRouter.scala:87:24] wire out_romask_209 = |_out_romask_T_209; // @[RegisterRouter.scala:87:24] wire out_womask_209 = &_out_womask_T_209; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_209 = out_rivalid_1_63 & out_rimask_209; // @[RegisterRouter.scala:87:24] wire _out_T_2494 = out_f_rivalid_209; // @[RegisterRouter.scala:87:24] wire out_f_roready_209 = out_roready_1_63 & out_romask_209; // @[RegisterRouter.scala:87:24] wire _out_T_2495 = out_f_roready_209; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_209 = out_wivalid_1_63 & out_wimask_209; // @[RegisterRouter.scala:87:24] wire out_f_woready_209 = out_woready_1_63 & out_womask_209; // @[RegisterRouter.scala:87:24] wire _out_T_2496 = ~out_rimask_209; // @[RegisterRouter.scala:87:24] wire _out_T_2497 = ~out_wimask_209; // @[RegisterRouter.scala:87:24] wire _out_T_2498 = ~out_romask_209; // @[RegisterRouter.scala:87:24] wire _out_T_2499 = ~out_womask_209; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_167 = {hi_600, flags_0_go, _out_prepend_T_167}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2500 = out_prepend_167; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2501 = _out_T_2500; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_202 = _out_T_2501; // @[MuxLiteral.scala:49:48] wire out_rimask_210 = |_out_rimask_T_210; // @[RegisterRouter.scala:87:24] wire out_wimask_210 = &_out_wimask_T_210; // @[RegisterRouter.scala:87:24] wire out_romask_210 = |_out_romask_T_210; // @[RegisterRouter.scala:87:24] wire out_womask_210 = &_out_womask_T_210; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_210 = out_rivalid_1_64 & out_rimask_210; // @[RegisterRouter.scala:87:24] wire _out_T_2503 = out_f_rivalid_210; // @[RegisterRouter.scala:87:24] wire out_f_roready_210 = out_roready_1_64 & out_romask_210; // @[RegisterRouter.scala:87:24] wire _out_T_2504 = out_f_roready_210; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_210 = out_wivalid_1_64 & out_wimask_210; // @[RegisterRouter.scala:87:24] wire out_f_woready_210 = out_woready_1_64 & out_womask_210; // @[RegisterRouter.scala:87:24] wire _out_T_2505 = ~out_rimask_210; // @[RegisterRouter.scala:87:24] wire _out_T_2506 = ~out_wimask_210; // @[RegisterRouter.scala:87:24] wire _out_T_2507 = ~out_romask_210; // @[RegisterRouter.scala:87:24] wire _out_T_2508 = ~out_womask_210; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2510 = _out_T_2509; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_168 = _out_T_2510; // @[RegisterRouter.scala:87:24] wire out_rimask_211 = |_out_rimask_T_211; // @[RegisterRouter.scala:87:24] wire out_wimask_211 = &_out_wimask_T_211; // @[RegisterRouter.scala:87:24] wire out_romask_211 = |_out_romask_T_211; // @[RegisterRouter.scala:87:24] wire out_womask_211 = &_out_womask_T_211; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_211 = out_rivalid_1_65 & out_rimask_211; // @[RegisterRouter.scala:87:24] wire _out_T_2512 = out_f_rivalid_211; // @[RegisterRouter.scala:87:24] wire out_f_roready_211 = out_roready_1_65 & out_romask_211; // @[RegisterRouter.scala:87:24] wire _out_T_2513 = out_f_roready_211; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_211 = out_wivalid_1_65 & out_wimask_211; // @[RegisterRouter.scala:87:24] wire out_f_woready_211 = out_woready_1_65 & out_womask_211; // @[RegisterRouter.scala:87:24] wire _out_T_2514 = ~out_rimask_211; // @[RegisterRouter.scala:87:24] wire _out_T_2515 = ~out_wimask_211; // @[RegisterRouter.scala:87:24] wire _out_T_2516 = ~out_romask_211; // @[RegisterRouter.scala:87:24] wire _out_T_2517 = ~out_womask_211; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_168 = {hi_114, flags_0_go, _out_prepend_T_168}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2518 = out_prepend_168; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2519 = _out_T_2518; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_169 = _out_T_2519; // @[RegisterRouter.scala:87:24] wire out_rimask_212 = |_out_rimask_T_212; // @[RegisterRouter.scala:87:24] wire out_wimask_212 = &_out_wimask_T_212; // @[RegisterRouter.scala:87:24] wire out_romask_212 = |_out_romask_T_212; // @[RegisterRouter.scala:87:24] wire out_womask_212 = &_out_womask_T_212; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_212 = out_rivalid_1_66 & out_rimask_212; // @[RegisterRouter.scala:87:24] wire _out_T_2521 = out_f_rivalid_212; // @[RegisterRouter.scala:87:24] wire out_f_roready_212 = out_roready_1_66 & out_romask_212; // @[RegisterRouter.scala:87:24] wire _out_T_2522 = out_f_roready_212; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_212 = out_wivalid_1_66 & out_wimask_212; // @[RegisterRouter.scala:87:24] wire out_f_woready_212 = out_woready_1_66 & out_womask_212; // @[RegisterRouter.scala:87:24] wire _out_T_2523 = ~out_rimask_212; // @[RegisterRouter.scala:87:24] wire _out_T_2524 = ~out_wimask_212; // @[RegisterRouter.scala:87:24] wire _out_T_2525 = ~out_romask_212; // @[RegisterRouter.scala:87:24] wire _out_T_2526 = ~out_womask_212; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_169 = {hi_115, flags_0_go, _out_prepend_T_169}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2527 = out_prepend_169; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2528 = _out_T_2527; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_170 = _out_T_2528; // @[RegisterRouter.scala:87:24] wire out_rimask_213 = |_out_rimask_T_213; // @[RegisterRouter.scala:87:24] wire out_wimask_213 = &_out_wimask_T_213; // @[RegisterRouter.scala:87:24] wire out_romask_213 = |_out_romask_T_213; // @[RegisterRouter.scala:87:24] wire out_womask_213 = &_out_womask_T_213; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_213 = out_rivalid_1_67 & out_rimask_213; // @[RegisterRouter.scala:87:24] wire _out_T_2530 = out_f_rivalid_213; // @[RegisterRouter.scala:87:24] wire out_f_roready_213 = out_roready_1_67 & out_romask_213; // @[RegisterRouter.scala:87:24] wire _out_T_2531 = out_f_roready_213; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_213 = out_wivalid_1_67 & out_wimask_213; // @[RegisterRouter.scala:87:24] wire out_f_woready_213 = out_woready_1_67 & out_womask_213; // @[RegisterRouter.scala:87:24] wire _out_T_2532 = ~out_rimask_213; // @[RegisterRouter.scala:87:24] wire _out_T_2533 = ~out_wimask_213; // @[RegisterRouter.scala:87:24] wire _out_T_2534 = ~out_romask_213; // @[RegisterRouter.scala:87:24] wire _out_T_2535 = ~out_womask_213; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_170 = {hi_116, flags_0_go, _out_prepend_T_170}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2536 = out_prepend_170; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2537 = _out_T_2536; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_171 = _out_T_2537; // @[RegisterRouter.scala:87:24] wire out_rimask_214 = |_out_rimask_T_214; // @[RegisterRouter.scala:87:24] wire out_wimask_214 = &_out_wimask_T_214; // @[RegisterRouter.scala:87:24] wire out_romask_214 = |_out_romask_T_214; // @[RegisterRouter.scala:87:24] wire out_womask_214 = &_out_womask_T_214; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_214 = out_rivalid_1_68 & out_rimask_214; // @[RegisterRouter.scala:87:24] wire _out_T_2539 = out_f_rivalid_214; // @[RegisterRouter.scala:87:24] wire out_f_roready_214 = out_roready_1_68 & out_romask_214; // @[RegisterRouter.scala:87:24] wire _out_T_2540 = out_f_roready_214; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_214 = out_wivalid_1_68 & out_wimask_214; // @[RegisterRouter.scala:87:24] wire out_f_woready_214 = out_woready_1_68 & out_womask_214; // @[RegisterRouter.scala:87:24] wire _out_T_2541 = ~out_rimask_214; // @[RegisterRouter.scala:87:24] wire _out_T_2542 = ~out_wimask_214; // @[RegisterRouter.scala:87:24] wire _out_T_2543 = ~out_romask_214; // @[RegisterRouter.scala:87:24] wire _out_T_2544 = ~out_womask_214; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_171 = {hi_117, flags_0_go, _out_prepend_T_171}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2545 = out_prepend_171; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2546 = _out_T_2545; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_172 = _out_T_2546; // @[RegisterRouter.scala:87:24] wire out_rimask_215 = |_out_rimask_T_215; // @[RegisterRouter.scala:87:24] wire out_wimask_215 = &_out_wimask_T_215; // @[RegisterRouter.scala:87:24] wire out_romask_215 = |_out_romask_T_215; // @[RegisterRouter.scala:87:24] wire out_womask_215 = &_out_womask_T_215; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_215 = out_rivalid_1_69 & out_rimask_215; // @[RegisterRouter.scala:87:24] wire _out_T_2548 = out_f_rivalid_215; // @[RegisterRouter.scala:87:24] wire out_f_roready_215 = out_roready_1_69 & out_romask_215; // @[RegisterRouter.scala:87:24] wire _out_T_2549 = out_f_roready_215; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_215 = out_wivalid_1_69 & out_wimask_215; // @[RegisterRouter.scala:87:24] wire out_f_woready_215 = out_woready_1_69 & out_womask_215; // @[RegisterRouter.scala:87:24] wire _out_T_2550 = ~out_rimask_215; // @[RegisterRouter.scala:87:24] wire _out_T_2551 = ~out_wimask_215; // @[RegisterRouter.scala:87:24] wire _out_T_2552 = ~out_romask_215; // @[RegisterRouter.scala:87:24] wire _out_T_2553 = ~out_womask_215; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_172 = {hi_118, flags_0_go, _out_prepend_T_172}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2554 = out_prepend_172; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2555 = _out_T_2554; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_173 = _out_T_2555; // @[RegisterRouter.scala:87:24] wire out_rimask_216 = |_out_rimask_T_216; // @[RegisterRouter.scala:87:24] wire out_wimask_216 = &_out_wimask_T_216; // @[RegisterRouter.scala:87:24] wire out_romask_216 = |_out_romask_T_216; // @[RegisterRouter.scala:87:24] wire out_womask_216 = &_out_womask_T_216; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_216 = out_rivalid_1_70 & out_rimask_216; // @[RegisterRouter.scala:87:24] wire _out_T_2557 = out_f_rivalid_216; // @[RegisterRouter.scala:87:24] wire out_f_roready_216 = out_roready_1_70 & out_romask_216; // @[RegisterRouter.scala:87:24] wire _out_T_2558 = out_f_roready_216; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_216 = out_wivalid_1_70 & out_wimask_216; // @[RegisterRouter.scala:87:24] wire out_f_woready_216 = out_woready_1_70 & out_womask_216; // @[RegisterRouter.scala:87:24] wire _out_T_2559 = ~out_rimask_216; // @[RegisterRouter.scala:87:24] wire _out_T_2560 = ~out_wimask_216; // @[RegisterRouter.scala:87:24] wire _out_T_2561 = ~out_romask_216; // @[RegisterRouter.scala:87:24] wire _out_T_2562 = ~out_womask_216; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_173 = {hi_119, flags_0_go, _out_prepend_T_173}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2563 = out_prepend_173; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2564 = _out_T_2563; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_174 = _out_T_2564; // @[RegisterRouter.scala:87:24] wire out_rimask_217 = |_out_rimask_T_217; // @[RegisterRouter.scala:87:24] wire out_wimask_217 = &_out_wimask_T_217; // @[RegisterRouter.scala:87:24] wire out_romask_217 = |_out_romask_T_217; // @[RegisterRouter.scala:87:24] wire out_womask_217 = &_out_womask_T_217; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_217 = out_rivalid_1_71 & out_rimask_217; // @[RegisterRouter.scala:87:24] wire _out_T_2566 = out_f_rivalid_217; // @[RegisterRouter.scala:87:24] wire out_f_roready_217 = out_roready_1_71 & out_romask_217; // @[RegisterRouter.scala:87:24] wire _out_T_2567 = out_f_roready_217; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_217 = out_wivalid_1_71 & out_wimask_217; // @[RegisterRouter.scala:87:24] wire out_f_woready_217 = out_woready_1_71 & out_womask_217; // @[RegisterRouter.scala:87:24] wire _out_T_2568 = ~out_rimask_217; // @[RegisterRouter.scala:87:24] wire _out_T_2569 = ~out_wimask_217; // @[RegisterRouter.scala:87:24] wire _out_T_2570 = ~out_romask_217; // @[RegisterRouter.scala:87:24] wire _out_T_2571 = ~out_womask_217; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_174 = {hi_120, flags_0_go, _out_prepend_T_174}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2572 = out_prepend_174; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2573 = _out_T_2572; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_142 = _out_T_2573; // @[MuxLiteral.scala:49:48] wire out_rimask_218 = |_out_rimask_T_218; // @[RegisterRouter.scala:87:24] wire out_wimask_218 = &_out_wimask_T_218; // @[RegisterRouter.scala:87:24] wire out_romask_218 = |_out_romask_T_218; // @[RegisterRouter.scala:87:24] wire out_womask_218 = &_out_womask_T_218; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_218 = out_rivalid_1_72 & out_rimask_218; // @[RegisterRouter.scala:87:24] wire _out_T_2575 = out_f_rivalid_218; // @[RegisterRouter.scala:87:24] wire out_f_roready_218 = out_roready_1_72 & out_romask_218; // @[RegisterRouter.scala:87:24] wire _out_T_2576 = out_f_roready_218; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_218 = out_wivalid_1_72 & out_wimask_218; // @[RegisterRouter.scala:87:24] wire out_f_woready_218 = out_woready_1_72 & out_womask_218; // @[RegisterRouter.scala:87:24] wire _out_T_2577 = ~out_rimask_218; // @[RegisterRouter.scala:87:24] wire _out_T_2578 = ~out_wimask_218; // @[RegisterRouter.scala:87:24] wire _out_T_2579 = ~out_romask_218; // @[RegisterRouter.scala:87:24] wire _out_T_2580 = ~out_womask_218; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2582 = _out_T_2581; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_175 = _out_T_2582; // @[RegisterRouter.scala:87:24] wire out_rimask_219 = |_out_rimask_T_219; // @[RegisterRouter.scala:87:24] wire out_wimask_219 = &_out_wimask_T_219; // @[RegisterRouter.scala:87:24] wire out_romask_219 = |_out_romask_T_219; // @[RegisterRouter.scala:87:24] wire out_womask_219 = &_out_womask_T_219; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_219 = out_rivalid_1_73 & out_rimask_219; // @[RegisterRouter.scala:87:24] wire _out_T_2584 = out_f_rivalid_219; // @[RegisterRouter.scala:87:24] wire out_f_roready_219 = out_roready_1_73 & out_romask_219; // @[RegisterRouter.scala:87:24] wire _out_T_2585 = out_f_roready_219; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_219 = out_wivalid_1_73 & out_wimask_219; // @[RegisterRouter.scala:87:24] wire out_f_woready_219 = out_woready_1_73 & out_womask_219; // @[RegisterRouter.scala:87:24] wire _out_T_2586 = ~out_rimask_219; // @[RegisterRouter.scala:87:24] wire _out_T_2587 = ~out_wimask_219; // @[RegisterRouter.scala:87:24] wire _out_T_2588 = ~out_romask_219; // @[RegisterRouter.scala:87:24] wire _out_T_2589 = ~out_womask_219; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_175 = {hi_202, flags_0_go, _out_prepend_T_175}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2590 = out_prepend_175; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2591 = _out_T_2590; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_176 = _out_T_2591; // @[RegisterRouter.scala:87:24] wire out_rimask_220 = |_out_rimask_T_220; // @[RegisterRouter.scala:87:24] wire out_wimask_220 = &_out_wimask_T_220; // @[RegisterRouter.scala:87:24] wire out_romask_220 = |_out_romask_T_220; // @[RegisterRouter.scala:87:24] wire out_womask_220 = &_out_womask_T_220; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_220 = out_rivalid_1_74 & out_rimask_220; // @[RegisterRouter.scala:87:24] wire _out_T_2593 = out_f_rivalid_220; // @[RegisterRouter.scala:87:24] wire out_f_roready_220 = out_roready_1_74 & out_romask_220; // @[RegisterRouter.scala:87:24] wire _out_T_2594 = out_f_roready_220; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_220 = out_wivalid_1_74 & out_wimask_220; // @[RegisterRouter.scala:87:24] wire out_f_woready_220 = out_woready_1_74 & out_womask_220; // @[RegisterRouter.scala:87:24] wire _out_T_2595 = ~out_rimask_220; // @[RegisterRouter.scala:87:24] wire _out_T_2596 = ~out_wimask_220; // @[RegisterRouter.scala:87:24] wire _out_T_2597 = ~out_romask_220; // @[RegisterRouter.scala:87:24] wire _out_T_2598 = ~out_womask_220; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_176 = {hi_203, flags_0_go, _out_prepend_T_176}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2599 = out_prepend_176; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2600 = _out_T_2599; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_177 = _out_T_2600; // @[RegisterRouter.scala:87:24] wire out_rimask_221 = |_out_rimask_T_221; // @[RegisterRouter.scala:87:24] wire out_wimask_221 = &_out_wimask_T_221; // @[RegisterRouter.scala:87:24] wire out_romask_221 = |_out_romask_T_221; // @[RegisterRouter.scala:87:24] wire out_womask_221 = &_out_womask_T_221; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_221 = out_rivalid_1_75 & out_rimask_221; // @[RegisterRouter.scala:87:24] wire _out_T_2602 = out_f_rivalid_221; // @[RegisterRouter.scala:87:24] wire out_f_roready_221 = out_roready_1_75 & out_romask_221; // @[RegisterRouter.scala:87:24] wire _out_T_2603 = out_f_roready_221; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_221 = out_wivalid_1_75 & out_wimask_221; // @[RegisterRouter.scala:87:24] wire out_f_woready_221 = out_woready_1_75 & out_womask_221; // @[RegisterRouter.scala:87:24] wire _out_T_2604 = ~out_rimask_221; // @[RegisterRouter.scala:87:24] wire _out_T_2605 = ~out_wimask_221; // @[RegisterRouter.scala:87:24] wire _out_T_2606 = ~out_romask_221; // @[RegisterRouter.scala:87:24] wire _out_T_2607 = ~out_womask_221; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_177 = {hi_204, flags_0_go, _out_prepend_T_177}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2608 = out_prepend_177; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2609 = _out_T_2608; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_178 = _out_T_2609; // @[RegisterRouter.scala:87:24] wire out_rimask_222 = |_out_rimask_T_222; // @[RegisterRouter.scala:87:24] wire out_wimask_222 = &_out_wimask_T_222; // @[RegisterRouter.scala:87:24] wire out_romask_222 = |_out_romask_T_222; // @[RegisterRouter.scala:87:24] wire out_womask_222 = &_out_womask_T_222; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_222 = out_rivalid_1_76 & out_rimask_222; // @[RegisterRouter.scala:87:24] wire _out_T_2611 = out_f_rivalid_222; // @[RegisterRouter.scala:87:24] wire out_f_roready_222 = out_roready_1_76 & out_romask_222; // @[RegisterRouter.scala:87:24] wire _out_T_2612 = out_f_roready_222; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_222 = out_wivalid_1_76 & out_wimask_222; // @[RegisterRouter.scala:87:24] wire out_f_woready_222 = out_woready_1_76 & out_womask_222; // @[RegisterRouter.scala:87:24] wire _out_T_2613 = ~out_rimask_222; // @[RegisterRouter.scala:87:24] wire _out_T_2614 = ~out_wimask_222; // @[RegisterRouter.scala:87:24] wire _out_T_2615 = ~out_romask_222; // @[RegisterRouter.scala:87:24] wire _out_T_2616 = ~out_womask_222; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_178 = {hi_205, flags_0_go, _out_prepend_T_178}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2617 = out_prepend_178; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2618 = _out_T_2617; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_179 = _out_T_2618; // @[RegisterRouter.scala:87:24] wire out_rimask_223 = |_out_rimask_T_223; // @[RegisterRouter.scala:87:24] wire out_wimask_223 = &_out_wimask_T_223; // @[RegisterRouter.scala:87:24] wire out_romask_223 = |_out_romask_T_223; // @[RegisterRouter.scala:87:24] wire out_womask_223 = &_out_womask_T_223; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_223 = out_rivalid_1_77 & out_rimask_223; // @[RegisterRouter.scala:87:24] wire _out_T_2620 = out_f_rivalid_223; // @[RegisterRouter.scala:87:24] wire out_f_roready_223 = out_roready_1_77 & out_romask_223; // @[RegisterRouter.scala:87:24] wire _out_T_2621 = out_f_roready_223; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_223 = out_wivalid_1_77 & out_wimask_223; // @[RegisterRouter.scala:87:24] wire out_f_woready_223 = out_woready_1_77 & out_womask_223; // @[RegisterRouter.scala:87:24] wire _out_T_2622 = ~out_rimask_223; // @[RegisterRouter.scala:87:24] wire _out_T_2623 = ~out_wimask_223; // @[RegisterRouter.scala:87:24] wire _out_T_2624 = ~out_romask_223; // @[RegisterRouter.scala:87:24] wire _out_T_2625 = ~out_womask_223; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_179 = {hi_206, flags_0_go, _out_prepend_T_179}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2626 = out_prepend_179; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2627 = _out_T_2626; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_180 = _out_T_2627; // @[RegisterRouter.scala:87:24] wire out_rimask_224 = |_out_rimask_T_224; // @[RegisterRouter.scala:87:24] wire out_wimask_224 = &_out_wimask_T_224; // @[RegisterRouter.scala:87:24] wire out_romask_224 = |_out_romask_T_224; // @[RegisterRouter.scala:87:24] wire out_womask_224 = &_out_womask_T_224; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_224 = out_rivalid_1_78 & out_rimask_224; // @[RegisterRouter.scala:87:24] wire _out_T_2629 = out_f_rivalid_224; // @[RegisterRouter.scala:87:24] wire out_f_roready_224 = out_roready_1_78 & out_romask_224; // @[RegisterRouter.scala:87:24] wire _out_T_2630 = out_f_roready_224; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_224 = out_wivalid_1_78 & out_wimask_224; // @[RegisterRouter.scala:87:24] wire out_f_woready_224 = out_woready_1_78 & out_womask_224; // @[RegisterRouter.scala:87:24] wire _out_T_2631 = ~out_rimask_224; // @[RegisterRouter.scala:87:24] wire _out_T_2632 = ~out_wimask_224; // @[RegisterRouter.scala:87:24] wire _out_T_2633 = ~out_romask_224; // @[RegisterRouter.scala:87:24] wire _out_T_2634 = ~out_womask_224; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_180 = {hi_207, flags_0_go, _out_prepend_T_180}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2635 = out_prepend_180; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2636 = _out_T_2635; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_181 = _out_T_2636; // @[RegisterRouter.scala:87:24] wire out_rimask_225 = |_out_rimask_T_225; // @[RegisterRouter.scala:87:24] wire out_wimask_225 = &_out_wimask_T_225; // @[RegisterRouter.scala:87:24] wire out_romask_225 = |_out_romask_T_225; // @[RegisterRouter.scala:87:24] wire out_womask_225 = &_out_womask_T_225; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_225 = out_rivalid_1_79 & out_rimask_225; // @[RegisterRouter.scala:87:24] wire _out_T_2638 = out_f_rivalid_225; // @[RegisterRouter.scala:87:24] wire out_f_roready_225 = out_roready_1_79 & out_romask_225; // @[RegisterRouter.scala:87:24] wire _out_T_2639 = out_f_roready_225; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_225 = out_wivalid_1_79 & out_wimask_225; // @[RegisterRouter.scala:87:24] wire out_f_woready_225 = out_woready_1_79 & out_womask_225; // @[RegisterRouter.scala:87:24] wire _out_T_2640 = ~out_rimask_225; // @[RegisterRouter.scala:87:24] wire _out_T_2641 = ~out_wimask_225; // @[RegisterRouter.scala:87:24] wire _out_T_2642 = ~out_romask_225; // @[RegisterRouter.scala:87:24] wire _out_T_2643 = ~out_womask_225; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_181 = {hi_208, flags_0_go, _out_prepend_T_181}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2644 = out_prepend_181; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2645 = _out_T_2644; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_153 = _out_T_2645; // @[MuxLiteral.scala:49:48] wire out_rimask_226 = |_out_rimask_T_226; // @[RegisterRouter.scala:87:24] wire out_wimask_226 = &_out_wimask_T_226; // @[RegisterRouter.scala:87:24] wire out_romask_226 = |_out_romask_T_226; // @[RegisterRouter.scala:87:24] wire out_womask_226 = &_out_womask_T_226; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_226 = out_rivalid_1_80 & out_rimask_226; // @[RegisterRouter.scala:87:24] wire _out_T_2647 = out_f_rivalid_226; // @[RegisterRouter.scala:87:24] wire out_f_roready_226 = out_roready_1_80 & out_romask_226; // @[RegisterRouter.scala:87:24] wire _out_T_2648 = out_f_roready_226; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_226 = out_wivalid_1_80 & out_wimask_226; // @[RegisterRouter.scala:87:24] wire out_f_woready_226 = out_woready_1_80 & out_womask_226; // @[RegisterRouter.scala:87:24] wire _out_T_2649 = ~out_rimask_226; // @[RegisterRouter.scala:87:24] wire _out_T_2650 = ~out_wimask_226; // @[RegisterRouter.scala:87:24] wire _out_T_2651 = ~out_romask_226; // @[RegisterRouter.scala:87:24] wire _out_T_2652 = ~out_womask_226; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2654 = _out_T_2653; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_182 = _out_T_2654; // @[RegisterRouter.scala:87:24] wire out_rimask_227 = |_out_rimask_T_227; // @[RegisterRouter.scala:87:24] wire out_wimask_227 = &_out_wimask_T_227; // @[RegisterRouter.scala:87:24] wire out_romask_227 = |_out_romask_T_227; // @[RegisterRouter.scala:87:24] wire out_womask_227 = &_out_womask_T_227; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_227 = out_rivalid_1_81 & out_rimask_227; // @[RegisterRouter.scala:87:24] wire _out_T_2656 = out_f_rivalid_227; // @[RegisterRouter.scala:87:24] wire out_f_roready_227 = out_roready_1_81 & out_romask_227; // @[RegisterRouter.scala:87:24] wire _out_T_2657 = out_f_roready_227; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_227 = out_wivalid_1_81 & out_wimask_227; // @[RegisterRouter.scala:87:24] wire out_f_woready_227 = out_woready_1_81 & out_womask_227; // @[RegisterRouter.scala:87:24] wire _out_T_2658 = ~out_rimask_227; // @[RegisterRouter.scala:87:24] wire _out_T_2659 = ~out_wimask_227; // @[RegisterRouter.scala:87:24] wire _out_T_2660 = ~out_romask_227; // @[RegisterRouter.scala:87:24] wire _out_T_2661 = ~out_womask_227; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_182 = {hi_370, flags_0_go, _out_prepend_T_182}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2662 = out_prepend_182; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2663 = _out_T_2662; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_183 = _out_T_2663; // @[RegisterRouter.scala:87:24] wire out_rimask_228 = |_out_rimask_T_228; // @[RegisterRouter.scala:87:24] wire out_wimask_228 = &_out_wimask_T_228; // @[RegisterRouter.scala:87:24] wire out_romask_228 = |_out_romask_T_228; // @[RegisterRouter.scala:87:24] wire out_womask_228 = &_out_womask_T_228; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_228 = out_rivalid_1_82 & out_rimask_228; // @[RegisterRouter.scala:87:24] wire _out_T_2665 = out_f_rivalid_228; // @[RegisterRouter.scala:87:24] wire out_f_roready_228 = out_roready_1_82 & out_romask_228; // @[RegisterRouter.scala:87:24] wire _out_T_2666 = out_f_roready_228; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_228 = out_wivalid_1_82 & out_wimask_228; // @[RegisterRouter.scala:87:24] wire out_f_woready_228 = out_woready_1_82 & out_womask_228; // @[RegisterRouter.scala:87:24] wire _out_T_2667 = ~out_rimask_228; // @[RegisterRouter.scala:87:24] wire _out_T_2668 = ~out_wimask_228; // @[RegisterRouter.scala:87:24] wire _out_T_2669 = ~out_romask_228; // @[RegisterRouter.scala:87:24] wire _out_T_2670 = ~out_womask_228; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_183 = {hi_371, flags_0_go, _out_prepend_T_183}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2671 = out_prepend_183; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2672 = _out_T_2671; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_184 = _out_T_2672; // @[RegisterRouter.scala:87:24] wire out_rimask_229 = |_out_rimask_T_229; // @[RegisterRouter.scala:87:24] wire out_wimask_229 = &_out_wimask_T_229; // @[RegisterRouter.scala:87:24] wire out_romask_229 = |_out_romask_T_229; // @[RegisterRouter.scala:87:24] wire out_womask_229 = &_out_womask_T_229; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_229 = out_rivalid_1_83 & out_rimask_229; // @[RegisterRouter.scala:87:24] wire _out_T_2674 = out_f_rivalid_229; // @[RegisterRouter.scala:87:24] wire out_f_roready_229 = out_roready_1_83 & out_romask_229; // @[RegisterRouter.scala:87:24] wire _out_T_2675 = out_f_roready_229; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_229 = out_wivalid_1_83 & out_wimask_229; // @[RegisterRouter.scala:87:24] wire out_f_woready_229 = out_woready_1_83 & out_womask_229; // @[RegisterRouter.scala:87:24] wire _out_T_2676 = ~out_rimask_229; // @[RegisterRouter.scala:87:24] wire _out_T_2677 = ~out_wimask_229; // @[RegisterRouter.scala:87:24] wire _out_T_2678 = ~out_romask_229; // @[RegisterRouter.scala:87:24] wire _out_T_2679 = ~out_womask_229; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_184 = {hi_372, flags_0_go, _out_prepend_T_184}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2680 = out_prepend_184; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2681 = _out_T_2680; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_185 = _out_T_2681; // @[RegisterRouter.scala:87:24] wire out_rimask_230 = |_out_rimask_T_230; // @[RegisterRouter.scala:87:24] wire out_wimask_230 = &_out_wimask_T_230; // @[RegisterRouter.scala:87:24] wire out_romask_230 = |_out_romask_T_230; // @[RegisterRouter.scala:87:24] wire out_womask_230 = &_out_womask_T_230; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_230 = out_rivalid_1_84 & out_rimask_230; // @[RegisterRouter.scala:87:24] wire _out_T_2683 = out_f_rivalid_230; // @[RegisterRouter.scala:87:24] wire out_f_roready_230 = out_roready_1_84 & out_romask_230; // @[RegisterRouter.scala:87:24] wire _out_T_2684 = out_f_roready_230; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_230 = out_wivalid_1_84 & out_wimask_230; // @[RegisterRouter.scala:87:24] wire out_f_woready_230 = out_woready_1_84 & out_womask_230; // @[RegisterRouter.scala:87:24] wire _out_T_2685 = ~out_rimask_230; // @[RegisterRouter.scala:87:24] wire _out_T_2686 = ~out_wimask_230; // @[RegisterRouter.scala:87:24] wire _out_T_2687 = ~out_romask_230; // @[RegisterRouter.scala:87:24] wire _out_T_2688 = ~out_womask_230; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_185 = {hi_373, flags_0_go, _out_prepend_T_185}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2689 = out_prepend_185; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2690 = _out_T_2689; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_186 = _out_T_2690; // @[RegisterRouter.scala:87:24] wire out_rimask_231 = |_out_rimask_T_231; // @[RegisterRouter.scala:87:24] wire out_wimask_231 = &_out_wimask_T_231; // @[RegisterRouter.scala:87:24] wire out_romask_231 = |_out_romask_T_231; // @[RegisterRouter.scala:87:24] wire out_womask_231 = &_out_womask_T_231; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_231 = out_rivalid_1_85 & out_rimask_231; // @[RegisterRouter.scala:87:24] wire _out_T_2692 = out_f_rivalid_231; // @[RegisterRouter.scala:87:24] wire out_f_roready_231 = out_roready_1_85 & out_romask_231; // @[RegisterRouter.scala:87:24] wire _out_T_2693 = out_f_roready_231; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_231 = out_wivalid_1_85 & out_wimask_231; // @[RegisterRouter.scala:87:24] wire out_f_woready_231 = out_woready_1_85 & out_womask_231; // @[RegisterRouter.scala:87:24] wire _out_T_2694 = ~out_rimask_231; // @[RegisterRouter.scala:87:24] wire _out_T_2695 = ~out_wimask_231; // @[RegisterRouter.scala:87:24] wire _out_T_2696 = ~out_romask_231; // @[RegisterRouter.scala:87:24] wire _out_T_2697 = ~out_womask_231; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_186 = {hi_374, flags_0_go, _out_prepend_T_186}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2698 = out_prepend_186; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2699 = _out_T_2698; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_187 = _out_T_2699; // @[RegisterRouter.scala:87:24] wire out_rimask_232 = |_out_rimask_T_232; // @[RegisterRouter.scala:87:24] wire out_wimask_232 = &_out_wimask_T_232; // @[RegisterRouter.scala:87:24] wire out_romask_232 = |_out_romask_T_232; // @[RegisterRouter.scala:87:24] wire out_womask_232 = &_out_womask_T_232; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_232 = out_rivalid_1_86 & out_rimask_232; // @[RegisterRouter.scala:87:24] wire _out_T_2701 = out_f_rivalid_232; // @[RegisterRouter.scala:87:24] wire out_f_roready_232 = out_roready_1_86 & out_romask_232; // @[RegisterRouter.scala:87:24] wire _out_T_2702 = out_f_roready_232; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_232 = out_wivalid_1_86 & out_wimask_232; // @[RegisterRouter.scala:87:24] wire out_f_woready_232 = out_woready_1_86 & out_womask_232; // @[RegisterRouter.scala:87:24] wire _out_T_2703 = ~out_rimask_232; // @[RegisterRouter.scala:87:24] wire _out_T_2704 = ~out_wimask_232; // @[RegisterRouter.scala:87:24] wire _out_T_2705 = ~out_romask_232; // @[RegisterRouter.scala:87:24] wire _out_T_2706 = ~out_womask_232; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_187 = {hi_375, flags_0_go, _out_prepend_T_187}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2707 = out_prepend_187; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2708 = _out_T_2707; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_188 = _out_T_2708; // @[RegisterRouter.scala:87:24] wire out_rimask_233 = |_out_rimask_T_233; // @[RegisterRouter.scala:87:24] wire out_wimask_233 = &_out_wimask_T_233; // @[RegisterRouter.scala:87:24] wire out_romask_233 = |_out_romask_T_233; // @[RegisterRouter.scala:87:24] wire out_womask_233 = &_out_womask_T_233; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_233 = out_rivalid_1_87 & out_rimask_233; // @[RegisterRouter.scala:87:24] wire _out_T_2710 = out_f_rivalid_233; // @[RegisterRouter.scala:87:24] wire out_f_roready_233 = out_roready_1_87 & out_romask_233; // @[RegisterRouter.scala:87:24] wire _out_T_2711 = out_f_roready_233; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_233 = out_wivalid_1_87 & out_wimask_233; // @[RegisterRouter.scala:87:24] wire out_f_woready_233 = out_woready_1_87 & out_womask_233; // @[RegisterRouter.scala:87:24] wire _out_T_2712 = ~out_rimask_233; // @[RegisterRouter.scala:87:24] wire _out_T_2713 = ~out_wimask_233; // @[RegisterRouter.scala:87:24] wire _out_T_2714 = ~out_romask_233; // @[RegisterRouter.scala:87:24] wire _out_T_2715 = ~out_womask_233; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_188 = {hi_376, flags_0_go, _out_prepend_T_188}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2716 = out_prepend_188; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2717 = _out_T_2716; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_174 = _out_T_2717; // @[MuxLiteral.scala:49:48] wire out_rimask_234 = |_out_rimask_T_234; // @[RegisterRouter.scala:87:24] wire out_wimask_234 = &_out_wimask_T_234; // @[RegisterRouter.scala:87:24] wire out_romask_234 = |_out_romask_T_234; // @[RegisterRouter.scala:87:24] wire out_womask_234 = &_out_womask_T_234; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_234 = out_rivalid_1_88 & out_rimask_234; // @[RegisterRouter.scala:87:24] wire _out_T_2719 = out_f_rivalid_234; // @[RegisterRouter.scala:87:24] wire out_f_roready_234 = out_roready_1_88 & out_romask_234; // @[RegisterRouter.scala:87:24] wire _out_T_2720 = out_f_roready_234; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_234 = out_wivalid_1_88 & out_wimask_234; // @[RegisterRouter.scala:87:24] wire out_f_woready_234 = out_woready_1_88 & out_womask_234; // @[RegisterRouter.scala:87:24] wire _out_T_2721 = ~out_rimask_234; // @[RegisterRouter.scala:87:24] wire _out_T_2722 = ~out_wimask_234; // @[RegisterRouter.scala:87:24] wire _out_T_2723 = ~out_romask_234; // @[RegisterRouter.scala:87:24] wire _out_T_2724 = ~out_womask_234; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2726 = _out_T_2725; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_189 = _out_T_2726; // @[RegisterRouter.scala:87:24] wire out_rimask_235 = |_out_rimask_T_235; // @[RegisterRouter.scala:87:24] wire out_wimask_235 = &_out_wimask_T_235; // @[RegisterRouter.scala:87:24] wire out_romask_235 = |_out_romask_T_235; // @[RegisterRouter.scala:87:24] wire out_womask_235 = &_out_womask_T_235; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_235 = out_rivalid_1_89 & out_rimask_235; // @[RegisterRouter.scala:87:24] wire _out_T_2728 = out_f_rivalid_235; // @[RegisterRouter.scala:87:24] wire out_f_roready_235 = out_roready_1_89 & out_romask_235; // @[RegisterRouter.scala:87:24] wire _out_T_2729 = out_f_roready_235; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_235 = out_wivalid_1_89 & out_wimask_235; // @[RegisterRouter.scala:87:24] wire out_f_woready_235 = out_woready_1_89 & out_womask_235; // @[RegisterRouter.scala:87:24] wire _out_T_2730 = ~out_rimask_235; // @[RegisterRouter.scala:87:24] wire _out_T_2731 = ~out_wimask_235; // @[RegisterRouter.scala:87:24] wire _out_T_2732 = ~out_romask_235; // @[RegisterRouter.scala:87:24] wire _out_T_2733 = ~out_womask_235; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_189 = {hi_458, flags_0_go, _out_prepend_T_189}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2734 = out_prepend_189; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2735 = _out_T_2734; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_190 = _out_T_2735; // @[RegisterRouter.scala:87:24] wire out_rimask_236 = |_out_rimask_T_236; // @[RegisterRouter.scala:87:24] wire out_wimask_236 = &_out_wimask_T_236; // @[RegisterRouter.scala:87:24] wire out_romask_236 = |_out_romask_T_236; // @[RegisterRouter.scala:87:24] wire out_womask_236 = &_out_womask_T_236; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_236 = out_rivalid_1_90 & out_rimask_236; // @[RegisterRouter.scala:87:24] wire _out_T_2737 = out_f_rivalid_236; // @[RegisterRouter.scala:87:24] wire out_f_roready_236 = out_roready_1_90 & out_romask_236; // @[RegisterRouter.scala:87:24] wire _out_T_2738 = out_f_roready_236; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_236 = out_wivalid_1_90 & out_wimask_236; // @[RegisterRouter.scala:87:24] wire out_f_woready_236 = out_woready_1_90 & out_womask_236; // @[RegisterRouter.scala:87:24] wire _out_T_2739 = ~out_rimask_236; // @[RegisterRouter.scala:87:24] wire _out_T_2740 = ~out_wimask_236; // @[RegisterRouter.scala:87:24] wire _out_T_2741 = ~out_romask_236; // @[RegisterRouter.scala:87:24] wire _out_T_2742 = ~out_womask_236; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_190 = {hi_459, flags_0_go, _out_prepend_T_190}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2743 = out_prepend_190; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2744 = _out_T_2743; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_191 = _out_T_2744; // @[RegisterRouter.scala:87:24] wire out_rimask_237 = |_out_rimask_T_237; // @[RegisterRouter.scala:87:24] wire out_wimask_237 = &_out_wimask_T_237; // @[RegisterRouter.scala:87:24] wire out_romask_237 = |_out_romask_T_237; // @[RegisterRouter.scala:87:24] wire out_womask_237 = &_out_womask_T_237; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_237 = out_rivalid_1_91 & out_rimask_237; // @[RegisterRouter.scala:87:24] wire _out_T_2746 = out_f_rivalid_237; // @[RegisterRouter.scala:87:24] wire out_f_roready_237 = out_roready_1_91 & out_romask_237; // @[RegisterRouter.scala:87:24] wire _out_T_2747 = out_f_roready_237; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_237 = out_wivalid_1_91 & out_wimask_237; // @[RegisterRouter.scala:87:24] wire out_f_woready_237 = out_woready_1_91 & out_womask_237; // @[RegisterRouter.scala:87:24] wire _out_T_2748 = ~out_rimask_237; // @[RegisterRouter.scala:87:24] wire _out_T_2749 = ~out_wimask_237; // @[RegisterRouter.scala:87:24] wire _out_T_2750 = ~out_romask_237; // @[RegisterRouter.scala:87:24] wire _out_T_2751 = ~out_womask_237; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_191 = {hi_460, flags_0_go, _out_prepend_T_191}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2752 = out_prepend_191; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2753 = _out_T_2752; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_192 = _out_T_2753; // @[RegisterRouter.scala:87:24] wire out_rimask_238 = |_out_rimask_T_238; // @[RegisterRouter.scala:87:24] wire out_wimask_238 = &_out_wimask_T_238; // @[RegisterRouter.scala:87:24] wire out_romask_238 = |_out_romask_T_238; // @[RegisterRouter.scala:87:24] wire out_womask_238 = &_out_womask_T_238; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_238 = out_rivalid_1_92 & out_rimask_238; // @[RegisterRouter.scala:87:24] wire _out_T_2755 = out_f_rivalid_238; // @[RegisterRouter.scala:87:24] wire out_f_roready_238 = out_roready_1_92 & out_romask_238; // @[RegisterRouter.scala:87:24] wire _out_T_2756 = out_f_roready_238; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_238 = out_wivalid_1_92 & out_wimask_238; // @[RegisterRouter.scala:87:24] wire out_f_woready_238 = out_woready_1_92 & out_womask_238; // @[RegisterRouter.scala:87:24] wire _out_T_2757 = ~out_rimask_238; // @[RegisterRouter.scala:87:24] wire _out_T_2758 = ~out_wimask_238; // @[RegisterRouter.scala:87:24] wire _out_T_2759 = ~out_romask_238; // @[RegisterRouter.scala:87:24] wire _out_T_2760 = ~out_womask_238; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_192 = {hi_461, flags_0_go, _out_prepend_T_192}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2761 = out_prepend_192; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2762 = _out_T_2761; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_193 = _out_T_2762; // @[RegisterRouter.scala:87:24] wire out_rimask_239 = |_out_rimask_T_239; // @[RegisterRouter.scala:87:24] wire out_wimask_239 = &_out_wimask_T_239; // @[RegisterRouter.scala:87:24] wire out_romask_239 = |_out_romask_T_239; // @[RegisterRouter.scala:87:24] wire out_womask_239 = &_out_womask_T_239; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_239 = out_rivalid_1_93 & out_rimask_239; // @[RegisterRouter.scala:87:24] wire _out_T_2764 = out_f_rivalid_239; // @[RegisterRouter.scala:87:24] wire out_f_roready_239 = out_roready_1_93 & out_romask_239; // @[RegisterRouter.scala:87:24] wire _out_T_2765 = out_f_roready_239; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_239 = out_wivalid_1_93 & out_wimask_239; // @[RegisterRouter.scala:87:24] wire out_f_woready_239 = out_woready_1_93 & out_womask_239; // @[RegisterRouter.scala:87:24] wire _out_T_2766 = ~out_rimask_239; // @[RegisterRouter.scala:87:24] wire _out_T_2767 = ~out_wimask_239; // @[RegisterRouter.scala:87:24] wire _out_T_2768 = ~out_romask_239; // @[RegisterRouter.scala:87:24] wire _out_T_2769 = ~out_womask_239; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_193 = {hi_462, flags_0_go, _out_prepend_T_193}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2770 = out_prepend_193; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2771 = _out_T_2770; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_194 = _out_T_2771; // @[RegisterRouter.scala:87:24] wire out_rimask_240 = |_out_rimask_T_240; // @[RegisterRouter.scala:87:24] wire out_wimask_240 = &_out_wimask_T_240; // @[RegisterRouter.scala:87:24] wire out_romask_240 = |_out_romask_T_240; // @[RegisterRouter.scala:87:24] wire out_womask_240 = &_out_womask_T_240; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_240 = out_rivalid_1_94 & out_rimask_240; // @[RegisterRouter.scala:87:24] wire _out_T_2773 = out_f_rivalid_240; // @[RegisterRouter.scala:87:24] wire out_f_roready_240 = out_roready_1_94 & out_romask_240; // @[RegisterRouter.scala:87:24] wire _out_T_2774 = out_f_roready_240; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_240 = out_wivalid_1_94 & out_wimask_240; // @[RegisterRouter.scala:87:24] wire out_f_woready_240 = out_woready_1_94 & out_womask_240; // @[RegisterRouter.scala:87:24] wire _out_T_2775 = ~out_rimask_240; // @[RegisterRouter.scala:87:24] wire _out_T_2776 = ~out_wimask_240; // @[RegisterRouter.scala:87:24] wire _out_T_2777 = ~out_romask_240; // @[RegisterRouter.scala:87:24] wire _out_T_2778 = ~out_womask_240; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_194 = {hi_463, flags_0_go, _out_prepend_T_194}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2779 = out_prepend_194; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2780 = _out_T_2779; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_195 = _out_T_2780; // @[RegisterRouter.scala:87:24] wire out_rimask_241 = |_out_rimask_T_241; // @[RegisterRouter.scala:87:24] wire out_wimask_241 = &_out_wimask_T_241; // @[RegisterRouter.scala:87:24] wire out_romask_241 = |_out_romask_T_241; // @[RegisterRouter.scala:87:24] wire out_womask_241 = &_out_womask_T_241; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_241 = out_rivalid_1_95 & out_rimask_241; // @[RegisterRouter.scala:87:24] wire _out_T_2782 = out_f_rivalid_241; // @[RegisterRouter.scala:87:24] wire out_f_roready_241 = out_roready_1_95 & out_romask_241; // @[RegisterRouter.scala:87:24] wire _out_T_2783 = out_f_roready_241; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_241 = out_wivalid_1_95 & out_wimask_241; // @[RegisterRouter.scala:87:24] wire out_f_woready_241 = out_woready_1_95 & out_womask_241; // @[RegisterRouter.scala:87:24] wire _out_T_2784 = ~out_rimask_241; // @[RegisterRouter.scala:87:24] wire _out_T_2785 = ~out_wimask_241; // @[RegisterRouter.scala:87:24] wire _out_T_2786 = ~out_romask_241; // @[RegisterRouter.scala:87:24] wire _out_T_2787 = ~out_womask_241; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_195 = {hi_464, flags_0_go, _out_prepend_T_195}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2788 = out_prepend_195; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2789 = _out_T_2788; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_185 = _out_T_2789; // @[MuxLiteral.scala:49:48] wire out_rimask_242 = |_out_rimask_T_242; // @[RegisterRouter.scala:87:24] wire out_wimask_242 = &_out_wimask_T_242; // @[RegisterRouter.scala:87:24] wire out_romask_242 = |_out_romask_T_242; // @[RegisterRouter.scala:87:24] wire out_womask_242 = &_out_womask_T_242; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_242 = out_rivalid_1_96 & out_rimask_242; // @[RegisterRouter.scala:87:24] wire _out_T_2791 = out_f_rivalid_242; // @[RegisterRouter.scala:87:24] wire out_f_roready_242 = out_roready_1_96 & out_romask_242; // @[RegisterRouter.scala:87:24] wire _out_T_2792 = out_f_roready_242; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_242 = out_wivalid_1_96 & out_wimask_242; // @[RegisterRouter.scala:87:24] wire out_f_woready_242 = out_woready_1_96 & out_womask_242; // @[RegisterRouter.scala:87:24] wire _out_T_2793 = ~out_rimask_242; // @[RegisterRouter.scala:87:24] wire _out_T_2794 = ~out_wimask_242; // @[RegisterRouter.scala:87:24] wire _out_T_2795 = ~out_romask_242; // @[RegisterRouter.scala:87:24] wire _out_T_2796 = ~out_womask_242; // @[RegisterRouter.scala:87:24] wire out_rimask_243 = |_out_rimask_T_243; // @[RegisterRouter.scala:87:24] wire out_wimask_243 = &_out_wimask_T_243; // @[RegisterRouter.scala:87:24] wire out_romask_243 = |_out_romask_T_243; // @[RegisterRouter.scala:87:24] wire out_womask_243 = &_out_womask_T_243; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_243 = out_rivalid_1_97 & out_rimask_243; // @[RegisterRouter.scala:87:24] wire _out_T_2800 = out_f_rivalid_243; // @[RegisterRouter.scala:87:24] wire out_f_roready_243 = out_roready_1_97 & out_romask_243; // @[RegisterRouter.scala:87:24] wire _out_T_2801 = out_f_roready_243; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_243 = out_wivalid_1_97 & out_wimask_243; // @[RegisterRouter.scala:87:24] wire out_f_woready_243 = out_woready_1_97 & out_womask_243; // @[RegisterRouter.scala:87:24] wire _out_T_2802 = ~out_rimask_243; // @[RegisterRouter.scala:87:24] wire _out_T_2803 = ~out_wimask_243; // @[RegisterRouter.scala:87:24] wire _out_T_2804 = ~out_romask_243; // @[RegisterRouter.scala:87:24] wire _out_T_2805 = ~out_womask_243; // @[RegisterRouter.scala:87:24] wire out_rimask_244 = |_out_rimask_T_244; // @[RegisterRouter.scala:87:24] wire out_wimask_244 = &_out_wimask_T_244; // @[RegisterRouter.scala:87:24] wire out_romask_244 = |_out_romask_T_244; // @[RegisterRouter.scala:87:24] wire out_womask_244 = &_out_womask_T_244; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_244 = out_rivalid_1_98 & out_rimask_244; // @[RegisterRouter.scala:87:24] wire _out_T_2809 = out_f_rivalid_244; // @[RegisterRouter.scala:87:24] wire out_f_roready_244 = out_roready_1_98 & out_romask_244; // @[RegisterRouter.scala:87:24] wire _out_T_2810 = out_f_roready_244; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_244 = out_wivalid_1_98 & out_wimask_244; // @[RegisterRouter.scala:87:24] wire out_f_woready_244 = out_woready_1_98 & out_womask_244; // @[RegisterRouter.scala:87:24] wire _out_T_2811 = ~out_rimask_244; // @[RegisterRouter.scala:87:24] wire _out_T_2812 = ~out_wimask_244; // @[RegisterRouter.scala:87:24] wire _out_T_2813 = ~out_romask_244; // @[RegisterRouter.scala:87:24] wire _out_T_2814 = ~out_womask_244; // @[RegisterRouter.scala:87:24] wire out_rimask_245 = |_out_rimask_T_245; // @[RegisterRouter.scala:87:24] wire out_wimask_245 = &_out_wimask_T_245; // @[RegisterRouter.scala:87:24] wire out_romask_245 = |_out_romask_T_245; // @[RegisterRouter.scala:87:24] wire out_womask_245 = &_out_womask_T_245; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_245 = out_rivalid_1_99 & out_rimask_245; // @[RegisterRouter.scala:87:24] wire _out_T_2818 = out_f_rivalid_245; // @[RegisterRouter.scala:87:24] wire out_f_roready_245 = out_roready_1_99 & out_romask_245; // @[RegisterRouter.scala:87:24] wire _out_T_2819 = out_f_roready_245; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_245 = out_wivalid_1_99 & out_wimask_245; // @[RegisterRouter.scala:87:24] wire out_f_woready_245 = out_woready_1_99 & out_womask_245; // @[RegisterRouter.scala:87:24] wire _out_T_2820 = ~out_rimask_245; // @[RegisterRouter.scala:87:24] wire _out_T_2821 = ~out_wimask_245; // @[RegisterRouter.scala:87:24] wire _out_T_2822 = ~out_romask_245; // @[RegisterRouter.scala:87:24] wire _out_T_2823 = ~out_womask_245; // @[RegisterRouter.scala:87:24] wire out_rimask_246 = |_out_rimask_T_246; // @[RegisterRouter.scala:87:24] wire out_wimask_246 = &_out_wimask_T_246; // @[RegisterRouter.scala:87:24] wire out_romask_246 = |_out_romask_T_246; // @[RegisterRouter.scala:87:24] wire out_womask_246 = &_out_womask_T_246; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_246 = out_rivalid_1_100 & out_rimask_246; // @[RegisterRouter.scala:87:24] wire _out_T_2827 = out_f_rivalid_246; // @[RegisterRouter.scala:87:24] wire out_f_roready_246 = out_roready_1_100 & out_romask_246; // @[RegisterRouter.scala:87:24] wire _out_T_2828 = out_f_roready_246; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_246 = out_wivalid_1_100 & out_wimask_246; // @[RegisterRouter.scala:87:24] wire out_f_woready_246 = out_woready_1_100 & out_womask_246; // @[RegisterRouter.scala:87:24] wire _out_T_2829 = ~out_rimask_246; // @[RegisterRouter.scala:87:24] wire _out_T_2830 = ~out_wimask_246; // @[RegisterRouter.scala:87:24] wire _out_T_2831 = ~out_romask_246; // @[RegisterRouter.scala:87:24] wire _out_T_2832 = ~out_womask_246; // @[RegisterRouter.scala:87:24] wire out_rimask_247 = |_out_rimask_T_247; // @[RegisterRouter.scala:87:24] wire out_wimask_247 = &_out_wimask_T_247; // @[RegisterRouter.scala:87:24] wire out_romask_247 = |_out_romask_T_247; // @[RegisterRouter.scala:87:24] wire out_womask_247 = &_out_womask_T_247; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_247 = out_rivalid_1_101 & out_rimask_247; // @[RegisterRouter.scala:87:24] wire _out_T_2836 = out_f_rivalid_247; // @[RegisterRouter.scala:87:24] wire out_f_roready_247 = out_roready_1_101 & out_romask_247; // @[RegisterRouter.scala:87:24] wire _out_T_2837 = out_f_roready_247; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_247 = out_wivalid_1_101 & out_wimask_247; // @[RegisterRouter.scala:87:24] wire out_f_woready_247 = out_woready_1_101 & out_womask_247; // @[RegisterRouter.scala:87:24] wire _out_T_2838 = ~out_rimask_247; // @[RegisterRouter.scala:87:24] wire _out_T_2839 = ~out_wimask_247; // @[RegisterRouter.scala:87:24] wire _out_T_2840 = ~out_romask_247; // @[RegisterRouter.scala:87:24] wire _out_T_2841 = ~out_womask_247; // @[RegisterRouter.scala:87:24] wire out_rimask_248 = |_out_rimask_T_248; // @[RegisterRouter.scala:87:24] wire out_wimask_248 = &_out_wimask_T_248; // @[RegisterRouter.scala:87:24] wire out_romask_248 = |_out_romask_T_248; // @[RegisterRouter.scala:87:24] wire out_womask_248 = &_out_womask_T_248; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_248 = out_rivalid_1_102 & out_rimask_248; // @[RegisterRouter.scala:87:24] wire _out_T_2845 = out_f_rivalid_248; // @[RegisterRouter.scala:87:24] wire out_f_roready_248 = out_roready_1_102 & out_romask_248; // @[RegisterRouter.scala:87:24] wire _out_T_2846 = out_f_roready_248; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_248 = out_wivalid_1_102 & out_wimask_248; // @[RegisterRouter.scala:87:24] wire out_f_woready_248 = out_woready_1_102 & out_womask_248; // @[RegisterRouter.scala:87:24] wire _out_T_2847 = ~out_rimask_248; // @[RegisterRouter.scala:87:24] wire _out_T_2848 = ~out_wimask_248; // @[RegisterRouter.scala:87:24] wire _out_T_2849 = ~out_romask_248; // @[RegisterRouter.scala:87:24] wire _out_T_2850 = ~out_womask_248; // @[RegisterRouter.scala:87:24] wire out_rimask_249 = |_out_rimask_T_249; // @[RegisterRouter.scala:87:24] wire out_wimask_249 = &_out_wimask_T_249; // @[RegisterRouter.scala:87:24] wire out_romask_249 = |_out_romask_T_249; // @[RegisterRouter.scala:87:24] wire out_womask_249 = &_out_womask_T_249; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_249 = out_rivalid_1_103 & out_rimask_249; // @[RegisterRouter.scala:87:24] wire _out_T_2854 = out_f_rivalid_249; // @[RegisterRouter.scala:87:24] wire out_f_roready_249 = out_roready_1_103 & out_romask_249; // @[RegisterRouter.scala:87:24] wire _out_T_2855 = out_f_roready_249; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_249 = out_wivalid_1_103 & out_wimask_249; // @[RegisterRouter.scala:87:24] wire out_f_woready_249 = out_woready_1_103 & out_womask_249; // @[RegisterRouter.scala:87:24] wire _out_T_2856 = ~out_rimask_249; // @[RegisterRouter.scala:87:24] wire _out_T_2857 = ~out_wimask_249; // @[RegisterRouter.scala:87:24] wire _out_T_2858 = ~out_romask_249; // @[RegisterRouter.scala:87:24] wire _out_T_2859 = ~out_womask_249; // @[RegisterRouter.scala:87:24] wire out_rimask_250 = |_out_rimask_T_250; // @[RegisterRouter.scala:87:24] wire out_wimask_250 = &_out_wimask_T_250; // @[RegisterRouter.scala:87:24] wire out_romask_250 = |_out_romask_T_250; // @[RegisterRouter.scala:87:24] wire out_womask_250 = &_out_womask_T_250; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_250 = out_rivalid_1_104 & out_rimask_250; // @[RegisterRouter.scala:87:24] wire _out_T_2863 = out_f_rivalid_250; // @[RegisterRouter.scala:87:24] wire out_f_roready_250 = out_roready_1_104 & out_romask_250; // @[RegisterRouter.scala:87:24] wire _out_T_2864 = out_f_roready_250; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_250 = out_wivalid_1_104 & out_wimask_250; // @[RegisterRouter.scala:87:24] wire out_f_woready_250 = out_woready_1_104 & out_womask_250; // @[RegisterRouter.scala:87:24] wire _out_T_2865 = ~out_rimask_250; // @[RegisterRouter.scala:87:24] wire _out_T_2866 = ~out_wimask_250; // @[RegisterRouter.scala:87:24] wire _out_T_2867 = ~out_romask_250; // @[RegisterRouter.scala:87:24] wire _out_T_2868 = ~out_womask_250; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2870 = _out_T_2869; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_203 = _out_T_2870; // @[RegisterRouter.scala:87:24] wire out_rimask_251 = |_out_rimask_T_251; // @[RegisterRouter.scala:87:24] wire out_wimask_251 = &_out_wimask_T_251; // @[RegisterRouter.scala:87:24] wire out_romask_251 = |_out_romask_T_251; // @[RegisterRouter.scala:87:24] wire out_womask_251 = &_out_womask_T_251; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_251 = out_rivalid_1_105 & out_rimask_251; // @[RegisterRouter.scala:87:24] wire _out_T_2872 = out_f_rivalid_251; // @[RegisterRouter.scala:87:24] wire out_f_roready_251 = out_roready_1_105 & out_romask_251; // @[RegisterRouter.scala:87:24] wire _out_T_2873 = out_f_roready_251; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_251 = out_wivalid_1_105 & out_wimask_251; // @[RegisterRouter.scala:87:24] wire out_f_woready_251 = out_woready_1_105 & out_womask_251; // @[RegisterRouter.scala:87:24] wire _out_T_2874 = ~out_rimask_251; // @[RegisterRouter.scala:87:24] wire _out_T_2875 = ~out_wimask_251; // @[RegisterRouter.scala:87:24] wire _out_T_2876 = ~out_romask_251; // @[RegisterRouter.scala:87:24] wire _out_T_2877 = ~out_womask_251; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_203 = {hi_450, flags_0_go, _out_prepend_T_203}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2878 = out_prepend_203; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2879 = _out_T_2878; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_204 = _out_T_2879; // @[RegisterRouter.scala:87:24] wire out_rimask_252 = |_out_rimask_T_252; // @[RegisterRouter.scala:87:24] wire out_wimask_252 = &_out_wimask_T_252; // @[RegisterRouter.scala:87:24] wire out_romask_252 = |_out_romask_T_252; // @[RegisterRouter.scala:87:24] wire out_womask_252 = &_out_womask_T_252; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_252 = out_rivalid_1_106 & out_rimask_252; // @[RegisterRouter.scala:87:24] wire _out_T_2881 = out_f_rivalid_252; // @[RegisterRouter.scala:87:24] wire out_f_roready_252 = out_roready_1_106 & out_romask_252; // @[RegisterRouter.scala:87:24] wire _out_T_2882 = out_f_roready_252; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_252 = out_wivalid_1_106 & out_wimask_252; // @[RegisterRouter.scala:87:24] wire out_f_woready_252 = out_woready_1_106 & out_womask_252; // @[RegisterRouter.scala:87:24] wire _out_T_2883 = ~out_rimask_252; // @[RegisterRouter.scala:87:24] wire _out_T_2884 = ~out_wimask_252; // @[RegisterRouter.scala:87:24] wire _out_T_2885 = ~out_romask_252; // @[RegisterRouter.scala:87:24] wire _out_T_2886 = ~out_womask_252; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_204 = {hi_451, flags_0_go, _out_prepend_T_204}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2887 = out_prepend_204; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2888 = _out_T_2887; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_205 = _out_T_2888; // @[RegisterRouter.scala:87:24] wire out_rimask_253 = |_out_rimask_T_253; // @[RegisterRouter.scala:87:24] wire out_wimask_253 = &_out_wimask_T_253; // @[RegisterRouter.scala:87:24] wire out_romask_253 = |_out_romask_T_253; // @[RegisterRouter.scala:87:24] wire out_womask_253 = &_out_womask_T_253; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_253 = out_rivalid_1_107 & out_rimask_253; // @[RegisterRouter.scala:87:24] wire _out_T_2890 = out_f_rivalid_253; // @[RegisterRouter.scala:87:24] wire out_f_roready_253 = out_roready_1_107 & out_romask_253; // @[RegisterRouter.scala:87:24] wire _out_T_2891 = out_f_roready_253; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_253 = out_wivalid_1_107 & out_wimask_253; // @[RegisterRouter.scala:87:24] wire out_f_woready_253 = out_woready_1_107 & out_womask_253; // @[RegisterRouter.scala:87:24] wire _out_T_2892 = ~out_rimask_253; // @[RegisterRouter.scala:87:24] wire _out_T_2893 = ~out_wimask_253; // @[RegisterRouter.scala:87:24] wire _out_T_2894 = ~out_romask_253; // @[RegisterRouter.scala:87:24] wire _out_T_2895 = ~out_womask_253; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_205 = {hi_452, flags_0_go, _out_prepend_T_205}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2896 = out_prepend_205; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2897 = _out_T_2896; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_206 = _out_T_2897; // @[RegisterRouter.scala:87:24] wire out_rimask_254 = |_out_rimask_T_254; // @[RegisterRouter.scala:87:24] wire out_wimask_254 = &_out_wimask_T_254; // @[RegisterRouter.scala:87:24] wire out_romask_254 = |_out_romask_T_254; // @[RegisterRouter.scala:87:24] wire out_womask_254 = &_out_womask_T_254; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_254 = out_rivalid_1_108 & out_rimask_254; // @[RegisterRouter.scala:87:24] wire _out_T_2899 = out_f_rivalid_254; // @[RegisterRouter.scala:87:24] wire out_f_roready_254 = out_roready_1_108 & out_romask_254; // @[RegisterRouter.scala:87:24] wire _out_T_2900 = out_f_roready_254; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_254 = out_wivalid_1_108 & out_wimask_254; // @[RegisterRouter.scala:87:24] wire out_f_woready_254 = out_woready_1_108 & out_womask_254; // @[RegisterRouter.scala:87:24] wire _out_T_2901 = ~out_rimask_254; // @[RegisterRouter.scala:87:24] wire _out_T_2902 = ~out_wimask_254; // @[RegisterRouter.scala:87:24] wire _out_T_2903 = ~out_romask_254; // @[RegisterRouter.scala:87:24] wire _out_T_2904 = ~out_womask_254; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_206 = {hi_453, flags_0_go, _out_prepend_T_206}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2905 = out_prepend_206; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2906 = _out_T_2905; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_207 = _out_T_2906; // @[RegisterRouter.scala:87:24] wire out_rimask_255 = |_out_rimask_T_255; // @[RegisterRouter.scala:87:24] wire out_wimask_255 = &_out_wimask_T_255; // @[RegisterRouter.scala:87:24] wire out_romask_255 = |_out_romask_T_255; // @[RegisterRouter.scala:87:24] wire out_womask_255 = &_out_womask_T_255; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_255 = out_rivalid_1_109 & out_rimask_255; // @[RegisterRouter.scala:87:24] wire _out_T_2908 = out_f_rivalid_255; // @[RegisterRouter.scala:87:24] wire out_f_roready_255 = out_roready_1_109 & out_romask_255; // @[RegisterRouter.scala:87:24] wire _out_T_2909 = out_f_roready_255; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_255 = out_wivalid_1_109 & out_wimask_255; // @[RegisterRouter.scala:87:24] wire out_f_woready_255 = out_woready_1_109 & out_womask_255; // @[RegisterRouter.scala:87:24] wire _out_T_2910 = ~out_rimask_255; // @[RegisterRouter.scala:87:24] wire _out_T_2911 = ~out_wimask_255; // @[RegisterRouter.scala:87:24] wire _out_T_2912 = ~out_romask_255; // @[RegisterRouter.scala:87:24] wire _out_T_2913 = ~out_womask_255; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_207 = {hi_454, flags_0_go, _out_prepend_T_207}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2914 = out_prepend_207; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2915 = _out_T_2914; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_208 = _out_T_2915; // @[RegisterRouter.scala:87:24] wire out_rimask_256 = |_out_rimask_T_256; // @[RegisterRouter.scala:87:24] wire out_wimask_256 = &_out_wimask_T_256; // @[RegisterRouter.scala:87:24] wire out_romask_256 = |_out_romask_T_256; // @[RegisterRouter.scala:87:24] wire out_womask_256 = &_out_womask_T_256; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_256 = out_rivalid_1_110 & out_rimask_256; // @[RegisterRouter.scala:87:24] wire _out_T_2917 = out_f_rivalid_256; // @[RegisterRouter.scala:87:24] wire out_f_roready_256 = out_roready_1_110 & out_romask_256; // @[RegisterRouter.scala:87:24] wire _out_T_2918 = out_f_roready_256; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_256 = out_wivalid_1_110 & out_wimask_256; // @[RegisterRouter.scala:87:24] wire out_f_woready_256 = out_woready_1_110 & out_womask_256; // @[RegisterRouter.scala:87:24] wire _out_T_2919 = ~out_rimask_256; // @[RegisterRouter.scala:87:24] wire _out_T_2920 = ~out_wimask_256; // @[RegisterRouter.scala:87:24] wire _out_T_2921 = ~out_romask_256; // @[RegisterRouter.scala:87:24] wire _out_T_2922 = ~out_womask_256; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_208 = {hi_455, flags_0_go, _out_prepend_T_208}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2923 = out_prepend_208; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2924 = _out_T_2923; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_209 = _out_T_2924; // @[RegisterRouter.scala:87:24] wire out_rimask_257 = |_out_rimask_T_257; // @[RegisterRouter.scala:87:24] wire out_wimask_257 = &_out_wimask_T_257; // @[RegisterRouter.scala:87:24] wire out_romask_257 = |_out_romask_T_257; // @[RegisterRouter.scala:87:24] wire out_womask_257 = &_out_womask_T_257; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_257 = out_rivalid_1_111 & out_rimask_257; // @[RegisterRouter.scala:87:24] wire _out_T_2926 = out_f_rivalid_257; // @[RegisterRouter.scala:87:24] wire out_f_roready_257 = out_roready_1_111 & out_romask_257; // @[RegisterRouter.scala:87:24] wire _out_T_2927 = out_f_roready_257; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_257 = out_wivalid_1_111 & out_wimask_257; // @[RegisterRouter.scala:87:24] wire out_f_woready_257 = out_woready_1_111 & out_womask_257; // @[RegisterRouter.scala:87:24] wire _out_T_2928 = ~out_rimask_257; // @[RegisterRouter.scala:87:24] wire _out_T_2929 = ~out_wimask_257; // @[RegisterRouter.scala:87:24] wire _out_T_2930 = ~out_romask_257; // @[RegisterRouter.scala:87:24] wire _out_T_2931 = ~out_womask_257; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_209 = {hi_456, flags_0_go, _out_prepend_T_209}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2932 = out_prepend_209; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2933 = _out_T_2932; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_184 = _out_T_2933; // @[MuxLiteral.scala:49:48] wire out_rimask_258 = |_out_rimask_T_258; // @[RegisterRouter.scala:87:24] wire out_wimask_258 = &_out_wimask_T_258; // @[RegisterRouter.scala:87:24] wire out_romask_258 = |_out_romask_T_258; // @[RegisterRouter.scala:87:24] wire out_womask_258 = &_out_womask_T_258; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_258 = out_rivalid_1_112 & out_rimask_258; // @[RegisterRouter.scala:87:24] wire _out_T_2935 = out_f_rivalid_258; // @[RegisterRouter.scala:87:24] wire out_f_roready_258 = out_roready_1_112 & out_romask_258; // @[RegisterRouter.scala:87:24] wire _out_T_2936 = out_f_roready_258; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_258 = out_wivalid_1_112 & out_wimask_258; // @[RegisterRouter.scala:87:24] wire _out_T_2937 = out_f_wivalid_258; // @[RegisterRouter.scala:87:24] wire out_f_woready_258 = out_woready_1_112 & out_womask_258; // @[RegisterRouter.scala:87:24] wire _out_T_2938 = out_f_woready_258; // @[RegisterRouter.scala:87:24] wire _out_T_2939 = ~out_rimask_258; // @[RegisterRouter.scala:87:24] wire _out_T_2940 = ~out_wimask_258; // @[RegisterRouter.scala:87:24] wire _out_T_2941 = ~out_romask_258; // @[RegisterRouter.scala:87:24] wire _out_T_2942 = ~out_womask_258; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2944 = _out_T_2943; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_210 = _out_T_2944; // @[RegisterRouter.scala:87:24] wire out_rimask_259 = |_out_rimask_T_259; // @[RegisterRouter.scala:87:24] wire out_wimask_259 = &_out_wimask_T_259; // @[RegisterRouter.scala:87:24] wire out_romask_259 = |_out_romask_T_259; // @[RegisterRouter.scala:87:24] wire out_womask_259 = &_out_womask_T_259; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_259 = out_rivalid_1_113 & out_rimask_259; // @[RegisterRouter.scala:87:24] wire _out_T_2946 = out_f_rivalid_259; // @[RegisterRouter.scala:87:24] wire out_f_roready_259 = out_roready_1_113 & out_romask_259; // @[RegisterRouter.scala:87:24] wire _out_T_2947 = out_f_roready_259; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_259 = out_wivalid_1_113 & out_wimask_259; // @[RegisterRouter.scala:87:24] wire _out_T_2948 = out_f_wivalid_259; // @[RegisterRouter.scala:87:24] wire out_f_woready_259 = out_woready_1_113 & out_womask_259; // @[RegisterRouter.scala:87:24] wire _out_T_2949 = out_f_woready_259; // @[RegisterRouter.scala:87:24] wire _out_T_2950 = ~out_rimask_259; // @[RegisterRouter.scala:87:24] wire _out_T_2951 = ~out_wimask_259; // @[RegisterRouter.scala:87:24] wire _out_T_2952 = ~out_romask_259; // @[RegisterRouter.scala:87:24] wire _out_T_2953 = ~out_womask_259; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_210 = {programBufferMem_49, _out_prepend_T_210}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2954 = out_prepend_210; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2955 = _out_T_2954; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_211 = _out_T_2955; // @[RegisterRouter.scala:87:24] wire out_rimask_260 = |_out_rimask_T_260; // @[RegisterRouter.scala:87:24] wire out_wimask_260 = &_out_wimask_T_260; // @[RegisterRouter.scala:87:24] wire out_romask_260 = |_out_romask_T_260; // @[RegisterRouter.scala:87:24] wire out_womask_260 = &_out_womask_T_260; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_260 = out_rivalid_1_114 & out_rimask_260; // @[RegisterRouter.scala:87:24] wire _out_T_2957 = out_f_rivalid_260; // @[RegisterRouter.scala:87:24] wire out_f_roready_260 = out_roready_1_114 & out_romask_260; // @[RegisterRouter.scala:87:24] wire _out_T_2958 = out_f_roready_260; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_260 = out_wivalid_1_114 & out_wimask_260; // @[RegisterRouter.scala:87:24] wire _out_T_2959 = out_f_wivalid_260; // @[RegisterRouter.scala:87:24] wire out_f_woready_260 = out_woready_1_114 & out_womask_260; // @[RegisterRouter.scala:87:24] wire _out_T_2960 = out_f_woready_260; // @[RegisterRouter.scala:87:24] wire _out_T_2961 = ~out_rimask_260; // @[RegisterRouter.scala:87:24] wire _out_T_2962 = ~out_wimask_260; // @[RegisterRouter.scala:87:24] wire _out_T_2963 = ~out_romask_260; // @[RegisterRouter.scala:87:24] wire _out_T_2964 = ~out_womask_260; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_211 = {programBufferMem_50, _out_prepend_T_211}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2965 = out_prepend_211; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2966 = _out_T_2965; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_212 = _out_T_2966; // @[RegisterRouter.scala:87:24] wire out_rimask_261 = |_out_rimask_T_261; // @[RegisterRouter.scala:87:24] wire out_wimask_261 = &_out_wimask_T_261; // @[RegisterRouter.scala:87:24] wire out_romask_261 = |_out_romask_T_261; // @[RegisterRouter.scala:87:24] wire out_womask_261 = &_out_womask_T_261; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_261 = out_rivalid_1_115 & out_rimask_261; // @[RegisterRouter.scala:87:24] wire _out_T_2968 = out_f_rivalid_261; // @[RegisterRouter.scala:87:24] wire out_f_roready_261 = out_roready_1_115 & out_romask_261; // @[RegisterRouter.scala:87:24] wire _out_T_2969 = out_f_roready_261; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_261 = out_wivalid_1_115 & out_wimask_261; // @[RegisterRouter.scala:87:24] wire _out_T_2970 = out_f_wivalid_261; // @[RegisterRouter.scala:87:24] wire out_f_woready_261 = out_woready_1_115 & out_womask_261; // @[RegisterRouter.scala:87:24] wire _out_T_2971 = out_f_woready_261; // @[RegisterRouter.scala:87:24] wire _out_T_2972 = ~out_rimask_261; // @[RegisterRouter.scala:87:24] wire _out_T_2973 = ~out_wimask_261; // @[RegisterRouter.scala:87:24] wire _out_T_2974 = ~out_romask_261; // @[RegisterRouter.scala:87:24] wire _out_T_2975 = ~out_womask_261; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_212 = {programBufferMem_51, _out_prepend_T_212}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2976 = out_prepend_212; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2977 = _out_T_2976; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_213 = _out_T_2977; // @[RegisterRouter.scala:87:24] wire out_rimask_262 = |_out_rimask_T_262; // @[RegisterRouter.scala:87:24] wire out_wimask_262 = &_out_wimask_T_262; // @[RegisterRouter.scala:87:24] wire out_romask_262 = |_out_romask_T_262; // @[RegisterRouter.scala:87:24] wire out_womask_262 = &_out_womask_T_262; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_262 = out_rivalid_1_116 & out_rimask_262; // @[RegisterRouter.scala:87:24] wire _out_T_2979 = out_f_rivalid_262; // @[RegisterRouter.scala:87:24] wire out_f_roready_262 = out_roready_1_116 & out_romask_262; // @[RegisterRouter.scala:87:24] wire _out_T_2980 = out_f_roready_262; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_262 = out_wivalid_1_116 & out_wimask_262; // @[RegisterRouter.scala:87:24] wire _out_T_2981 = out_f_wivalid_262; // @[RegisterRouter.scala:87:24] wire out_f_woready_262 = out_woready_1_116 & out_womask_262; // @[RegisterRouter.scala:87:24] wire _out_T_2982 = out_f_woready_262; // @[RegisterRouter.scala:87:24] wire _out_T_2983 = ~out_rimask_262; // @[RegisterRouter.scala:87:24] wire _out_T_2984 = ~out_wimask_262; // @[RegisterRouter.scala:87:24] wire _out_T_2985 = ~out_romask_262; // @[RegisterRouter.scala:87:24] wire _out_T_2986 = ~out_womask_262; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_213 = {programBufferMem_52, _out_prepend_T_213}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2987 = out_prepend_213; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2988 = _out_T_2987; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_214 = _out_T_2988; // @[RegisterRouter.scala:87:24] wire out_rimask_263 = |_out_rimask_T_263; // @[RegisterRouter.scala:87:24] wire out_wimask_263 = &_out_wimask_T_263; // @[RegisterRouter.scala:87:24] wire out_romask_263 = |_out_romask_T_263; // @[RegisterRouter.scala:87:24] wire out_womask_263 = &_out_womask_T_263; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_263 = out_rivalid_1_117 & out_rimask_263; // @[RegisterRouter.scala:87:24] wire _out_T_2990 = out_f_rivalid_263; // @[RegisterRouter.scala:87:24] wire out_f_roready_263 = out_roready_1_117 & out_romask_263; // @[RegisterRouter.scala:87:24] wire _out_T_2991 = out_f_roready_263; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_263 = out_wivalid_1_117 & out_wimask_263; // @[RegisterRouter.scala:87:24] wire _out_T_2992 = out_f_wivalid_263; // @[RegisterRouter.scala:87:24] wire out_f_woready_263 = out_woready_1_117 & out_womask_263; // @[RegisterRouter.scala:87:24] wire _out_T_2993 = out_f_woready_263; // @[RegisterRouter.scala:87:24] wire _out_T_2994 = ~out_rimask_263; // @[RegisterRouter.scala:87:24] wire _out_T_2995 = ~out_wimask_263; // @[RegisterRouter.scala:87:24] wire _out_T_2996 = ~out_romask_263; // @[RegisterRouter.scala:87:24] wire _out_T_2997 = ~out_womask_263; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_214 = {programBufferMem_53, _out_prepend_T_214}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2998 = out_prepend_214; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2999 = _out_T_2998; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_215 = _out_T_2999; // @[RegisterRouter.scala:87:24] wire out_rimask_264 = |_out_rimask_T_264; // @[RegisterRouter.scala:87:24] wire out_wimask_264 = &_out_wimask_T_264; // @[RegisterRouter.scala:87:24] wire out_romask_264 = |_out_romask_T_264; // @[RegisterRouter.scala:87:24] wire out_womask_264 = &_out_womask_T_264; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_264 = out_rivalid_1_118 & out_rimask_264; // @[RegisterRouter.scala:87:24] wire _out_T_3001 = out_f_rivalid_264; // @[RegisterRouter.scala:87:24] wire out_f_roready_264 = out_roready_1_118 & out_romask_264; // @[RegisterRouter.scala:87:24] wire _out_T_3002 = out_f_roready_264; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_264 = out_wivalid_1_118 & out_wimask_264; // @[RegisterRouter.scala:87:24] wire _out_T_3003 = out_f_wivalid_264; // @[RegisterRouter.scala:87:24] wire out_f_woready_264 = out_woready_1_118 & out_womask_264; // @[RegisterRouter.scala:87:24] wire _out_T_3004 = out_f_woready_264; // @[RegisterRouter.scala:87:24] wire _out_T_3005 = ~out_rimask_264; // @[RegisterRouter.scala:87:24] wire _out_T_3006 = ~out_wimask_264; // @[RegisterRouter.scala:87:24] wire _out_T_3007 = ~out_romask_264; // @[RegisterRouter.scala:87:24] wire _out_T_3008 = ~out_womask_264; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_215 = {programBufferMem_54, _out_prepend_T_215}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3009 = out_prepend_215; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3010 = _out_T_3009; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_216 = _out_T_3010; // @[RegisterRouter.scala:87:24] wire out_rimask_265 = |_out_rimask_T_265; // @[RegisterRouter.scala:87:24] wire out_wimask_265 = &_out_wimask_T_265; // @[RegisterRouter.scala:87:24] wire out_romask_265 = |_out_romask_T_265; // @[RegisterRouter.scala:87:24] wire out_womask_265 = &_out_womask_T_265; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_265 = out_rivalid_1_119 & out_rimask_265; // @[RegisterRouter.scala:87:24] wire _out_T_3012 = out_f_rivalid_265; // @[RegisterRouter.scala:87:24] wire out_f_roready_265 = out_roready_1_119 & out_romask_265; // @[RegisterRouter.scala:87:24] wire _out_T_3013 = out_f_roready_265; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_265 = out_wivalid_1_119 & out_wimask_265; // @[RegisterRouter.scala:87:24] wire _out_T_3014 = out_f_wivalid_265; // @[RegisterRouter.scala:87:24] wire out_f_woready_265 = out_woready_1_119 & out_womask_265; // @[RegisterRouter.scala:87:24] wire _out_T_3015 = out_f_woready_265; // @[RegisterRouter.scala:87:24] wire _out_T_3016 = ~out_rimask_265; // @[RegisterRouter.scala:87:24] wire _out_T_3017 = ~out_wimask_265; // @[RegisterRouter.scala:87:24] wire _out_T_3018 = ~out_romask_265; // @[RegisterRouter.scala:87:24] wire _out_T_3019 = ~out_womask_265; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_216 = {programBufferMem_55, _out_prepend_T_216}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3020 = out_prepend_216; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3021 = _out_T_3020; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_110 = _out_T_3021; // @[MuxLiteral.scala:49:48] wire out_rimask_266 = |_out_rimask_T_266; // @[RegisterRouter.scala:87:24] wire out_wimask_266 = &_out_wimask_T_266; // @[RegisterRouter.scala:87:24] wire out_romask_266 = |_out_romask_T_266; // @[RegisterRouter.scala:87:24] wire out_womask_266 = &_out_womask_T_266; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_266 = out_rivalid_1_120 & out_rimask_266; // @[RegisterRouter.scala:87:24] wire _out_T_3023 = out_f_rivalid_266; // @[RegisterRouter.scala:87:24] wire out_f_roready_266 = out_roready_1_120 & out_romask_266; // @[RegisterRouter.scala:87:24] wire _out_T_3024 = out_f_roready_266; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_266 = out_wivalid_1_120 & out_wimask_266; // @[RegisterRouter.scala:87:24] wire out_f_woready_266 = out_woready_1_120 & out_womask_266; // @[RegisterRouter.scala:87:24] wire _out_T_3025 = ~out_rimask_266; // @[RegisterRouter.scala:87:24] wire _out_T_3026 = ~out_wimask_266; // @[RegisterRouter.scala:87:24] wire _out_T_3027 = ~out_romask_266; // @[RegisterRouter.scala:87:24] wire _out_T_3028 = ~out_womask_266; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3030 = _out_T_3029; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_217 = _out_T_3030; // @[RegisterRouter.scala:87:24] wire out_rimask_267 = |_out_rimask_T_267; // @[RegisterRouter.scala:87:24] wire out_wimask_267 = &_out_wimask_T_267; // @[RegisterRouter.scala:87:24] wire out_romask_267 = |_out_romask_T_267; // @[RegisterRouter.scala:87:24] wire out_womask_267 = &_out_womask_T_267; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_267 = out_rivalid_1_121 & out_rimask_267; // @[RegisterRouter.scala:87:24] wire _out_T_3032 = out_f_rivalid_267; // @[RegisterRouter.scala:87:24] wire out_f_roready_267 = out_roready_1_121 & out_romask_267; // @[RegisterRouter.scala:87:24] wire _out_T_3033 = out_f_roready_267; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_267 = out_wivalid_1_121 & out_wimask_267; // @[RegisterRouter.scala:87:24] wire out_f_woready_267 = out_woready_1_121 & out_womask_267; // @[RegisterRouter.scala:87:24] wire _out_T_3034 = ~out_rimask_267; // @[RegisterRouter.scala:87:24] wire _out_T_3035 = ~out_wimask_267; // @[RegisterRouter.scala:87:24] wire _out_T_3036 = ~out_romask_267; // @[RegisterRouter.scala:87:24] wire _out_T_3037 = ~out_womask_267; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_217 = {hi_546, flags_0_go, _out_prepend_T_217}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3038 = out_prepend_217; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3039 = _out_T_3038; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_218 = _out_T_3039; // @[RegisterRouter.scala:87:24] wire out_rimask_268 = |_out_rimask_T_268; // @[RegisterRouter.scala:87:24] wire out_wimask_268 = &_out_wimask_T_268; // @[RegisterRouter.scala:87:24] wire out_romask_268 = |_out_romask_T_268; // @[RegisterRouter.scala:87:24] wire out_womask_268 = &_out_womask_T_268; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_268 = out_rivalid_1_122 & out_rimask_268; // @[RegisterRouter.scala:87:24] wire _out_T_3041 = out_f_rivalid_268; // @[RegisterRouter.scala:87:24] wire out_f_roready_268 = out_roready_1_122 & out_romask_268; // @[RegisterRouter.scala:87:24] wire _out_T_3042 = out_f_roready_268; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_268 = out_wivalid_1_122 & out_wimask_268; // @[RegisterRouter.scala:87:24] wire out_f_woready_268 = out_woready_1_122 & out_womask_268; // @[RegisterRouter.scala:87:24] wire _out_T_3043 = ~out_rimask_268; // @[RegisterRouter.scala:87:24] wire _out_T_3044 = ~out_wimask_268; // @[RegisterRouter.scala:87:24] wire _out_T_3045 = ~out_romask_268; // @[RegisterRouter.scala:87:24] wire _out_T_3046 = ~out_womask_268; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_218 = {hi_547, flags_0_go, _out_prepend_T_218}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3047 = out_prepend_218; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3048 = _out_T_3047; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_219 = _out_T_3048; // @[RegisterRouter.scala:87:24] wire out_rimask_269 = |_out_rimask_T_269; // @[RegisterRouter.scala:87:24] wire out_wimask_269 = &_out_wimask_T_269; // @[RegisterRouter.scala:87:24] wire out_romask_269 = |_out_romask_T_269; // @[RegisterRouter.scala:87:24] wire out_womask_269 = &_out_womask_T_269; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_269 = out_rivalid_1_123 & out_rimask_269; // @[RegisterRouter.scala:87:24] wire _out_T_3050 = out_f_rivalid_269; // @[RegisterRouter.scala:87:24] wire out_f_roready_269 = out_roready_1_123 & out_romask_269; // @[RegisterRouter.scala:87:24] wire _out_T_3051 = out_f_roready_269; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_269 = out_wivalid_1_123 & out_wimask_269; // @[RegisterRouter.scala:87:24] wire out_f_woready_269 = out_woready_1_123 & out_womask_269; // @[RegisterRouter.scala:87:24] wire _out_T_3052 = ~out_rimask_269; // @[RegisterRouter.scala:87:24] wire _out_T_3053 = ~out_wimask_269; // @[RegisterRouter.scala:87:24] wire _out_T_3054 = ~out_romask_269; // @[RegisterRouter.scala:87:24] wire _out_T_3055 = ~out_womask_269; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_219 = {hi_548, flags_0_go, _out_prepend_T_219}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3056 = out_prepend_219; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3057 = _out_T_3056; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_220 = _out_T_3057; // @[RegisterRouter.scala:87:24] wire out_rimask_270 = |_out_rimask_T_270; // @[RegisterRouter.scala:87:24] wire out_wimask_270 = &_out_wimask_T_270; // @[RegisterRouter.scala:87:24] wire out_romask_270 = |_out_romask_T_270; // @[RegisterRouter.scala:87:24] wire out_womask_270 = &_out_womask_T_270; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_270 = out_rivalid_1_124 & out_rimask_270; // @[RegisterRouter.scala:87:24] wire _out_T_3059 = out_f_rivalid_270; // @[RegisterRouter.scala:87:24] wire out_f_roready_270 = out_roready_1_124 & out_romask_270; // @[RegisterRouter.scala:87:24] wire _out_T_3060 = out_f_roready_270; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_270 = out_wivalid_1_124 & out_wimask_270; // @[RegisterRouter.scala:87:24] wire out_f_woready_270 = out_woready_1_124 & out_womask_270; // @[RegisterRouter.scala:87:24] wire _out_T_3061 = ~out_rimask_270; // @[RegisterRouter.scala:87:24] wire _out_T_3062 = ~out_wimask_270; // @[RegisterRouter.scala:87:24] wire _out_T_3063 = ~out_romask_270; // @[RegisterRouter.scala:87:24] wire _out_T_3064 = ~out_womask_270; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_220 = {hi_549, flags_0_go, _out_prepend_T_220}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3065 = out_prepend_220; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3066 = _out_T_3065; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_221 = _out_T_3066; // @[RegisterRouter.scala:87:24] wire out_rimask_271 = |_out_rimask_T_271; // @[RegisterRouter.scala:87:24] wire out_wimask_271 = &_out_wimask_T_271; // @[RegisterRouter.scala:87:24] wire out_romask_271 = |_out_romask_T_271; // @[RegisterRouter.scala:87:24] wire out_womask_271 = &_out_womask_T_271; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_271 = out_rivalid_1_125 & out_rimask_271; // @[RegisterRouter.scala:87:24] wire _out_T_3068 = out_f_rivalid_271; // @[RegisterRouter.scala:87:24] wire out_f_roready_271 = out_roready_1_125 & out_romask_271; // @[RegisterRouter.scala:87:24] wire _out_T_3069 = out_f_roready_271; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_271 = out_wivalid_1_125 & out_wimask_271; // @[RegisterRouter.scala:87:24] wire out_f_woready_271 = out_woready_1_125 & out_womask_271; // @[RegisterRouter.scala:87:24] wire _out_T_3070 = ~out_rimask_271; // @[RegisterRouter.scala:87:24] wire _out_T_3071 = ~out_wimask_271; // @[RegisterRouter.scala:87:24] wire _out_T_3072 = ~out_romask_271; // @[RegisterRouter.scala:87:24] wire _out_T_3073 = ~out_womask_271; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_221 = {hi_550, flags_0_go, _out_prepend_T_221}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3074 = out_prepend_221; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3075 = _out_T_3074; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_222 = _out_T_3075; // @[RegisterRouter.scala:87:24] wire out_rimask_272 = |_out_rimask_T_272; // @[RegisterRouter.scala:87:24] wire out_wimask_272 = &_out_wimask_T_272; // @[RegisterRouter.scala:87:24] wire out_romask_272 = |_out_romask_T_272; // @[RegisterRouter.scala:87:24] wire out_womask_272 = &_out_womask_T_272; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_272 = out_rivalid_1_126 & out_rimask_272; // @[RegisterRouter.scala:87:24] wire _out_T_3077 = out_f_rivalid_272; // @[RegisterRouter.scala:87:24] wire out_f_roready_272 = out_roready_1_126 & out_romask_272; // @[RegisterRouter.scala:87:24] wire _out_T_3078 = out_f_roready_272; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_272 = out_wivalid_1_126 & out_wimask_272; // @[RegisterRouter.scala:87:24] wire out_f_woready_272 = out_woready_1_126 & out_womask_272; // @[RegisterRouter.scala:87:24] wire _out_T_3079 = ~out_rimask_272; // @[RegisterRouter.scala:87:24] wire _out_T_3080 = ~out_wimask_272; // @[RegisterRouter.scala:87:24] wire _out_T_3081 = ~out_romask_272; // @[RegisterRouter.scala:87:24] wire _out_T_3082 = ~out_womask_272; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_222 = {hi_551, flags_0_go, _out_prepend_T_222}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3083 = out_prepend_222; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3084 = _out_T_3083; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_223 = _out_T_3084; // @[RegisterRouter.scala:87:24] wire out_rimask_273 = |_out_rimask_T_273; // @[RegisterRouter.scala:87:24] wire out_wimask_273 = &_out_wimask_T_273; // @[RegisterRouter.scala:87:24] wire out_romask_273 = |_out_romask_T_273; // @[RegisterRouter.scala:87:24] wire out_womask_273 = &_out_womask_T_273; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_273 = out_rivalid_1_127 & out_rimask_273; // @[RegisterRouter.scala:87:24] wire _out_T_3086 = out_f_rivalid_273; // @[RegisterRouter.scala:87:24] wire out_f_roready_273 = out_roready_1_127 & out_romask_273; // @[RegisterRouter.scala:87:24] wire _out_T_3087 = out_f_roready_273; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_273 = out_wivalid_1_127 & out_wimask_273; // @[RegisterRouter.scala:87:24] wire out_f_woready_273 = out_woready_1_127 & out_womask_273; // @[RegisterRouter.scala:87:24] wire _out_T_3088 = ~out_rimask_273; // @[RegisterRouter.scala:87:24] wire _out_T_3089 = ~out_wimask_273; // @[RegisterRouter.scala:87:24] wire _out_T_3090 = ~out_romask_273; // @[RegisterRouter.scala:87:24] wire _out_T_3091 = ~out_womask_273; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_223 = {hi_552, flags_0_go, _out_prepend_T_223}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3092 = out_prepend_223; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3093 = _out_T_3092; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_196 = _out_T_3093; // @[MuxLiteral.scala:49:48] wire out_rimask_274 = |_out_rimask_T_274; // @[RegisterRouter.scala:87:24] wire out_wimask_274 = &_out_wimask_T_274; // @[RegisterRouter.scala:87:24] wire out_romask_274 = |_out_romask_T_274; // @[RegisterRouter.scala:87:24] wire out_womask_274 = &_out_womask_T_274; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_274 = out_rivalid_1_128 & out_rimask_274; // @[RegisterRouter.scala:87:24] wire _out_T_3095 = out_f_rivalid_274; // @[RegisterRouter.scala:87:24] wire out_f_roready_274 = out_roready_1_128 & out_romask_274; // @[RegisterRouter.scala:87:24] wire _out_T_3096 = out_f_roready_274; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_274 = out_wivalid_1_128 & out_wimask_274; // @[RegisterRouter.scala:87:24] wire out_f_woready_274 = out_woready_1_128 & out_womask_274; // @[RegisterRouter.scala:87:24] wire _out_T_3097 = ~out_rimask_274; // @[RegisterRouter.scala:87:24] wire _out_T_3098 = ~out_wimask_274; // @[RegisterRouter.scala:87:24] wire _out_T_3099 = ~out_romask_274; // @[RegisterRouter.scala:87:24] wire _out_T_3100 = ~out_womask_274; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3102 = _out_T_3101; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_224 = _out_T_3102; // @[RegisterRouter.scala:87:24] wire out_rimask_275 = |_out_rimask_T_275; // @[RegisterRouter.scala:87:24] wire out_wimask_275 = &_out_wimask_T_275; // @[RegisterRouter.scala:87:24] wire out_romask_275 = |_out_romask_T_275; // @[RegisterRouter.scala:87:24] wire out_womask_275 = &_out_womask_T_275; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_275 = out_rivalid_1_129 & out_rimask_275; // @[RegisterRouter.scala:87:24] wire _out_T_3104 = out_f_rivalid_275; // @[RegisterRouter.scala:87:24] wire out_f_roready_275 = out_roready_1_129 & out_romask_275; // @[RegisterRouter.scala:87:24] wire _out_T_3105 = out_f_roready_275; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_275 = out_wivalid_1_129 & out_wimask_275; // @[RegisterRouter.scala:87:24] wire out_f_woready_275 = out_woready_1_129 & out_womask_275; // @[RegisterRouter.scala:87:24] wire _out_T_3106 = ~out_rimask_275; // @[RegisterRouter.scala:87:24] wire _out_T_3107 = ~out_wimask_275; // @[RegisterRouter.scala:87:24] wire _out_T_3108 = ~out_romask_275; // @[RegisterRouter.scala:87:24] wire _out_T_3109 = ~out_womask_275; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_224 = {hi_234, flags_0_go, _out_prepend_T_224}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3110 = out_prepend_224; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3111 = _out_T_3110; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_225 = _out_T_3111; // @[RegisterRouter.scala:87:24] wire out_rimask_276 = |_out_rimask_T_276; // @[RegisterRouter.scala:87:24] wire out_wimask_276 = &_out_wimask_T_276; // @[RegisterRouter.scala:87:24] wire out_romask_276 = |_out_romask_T_276; // @[RegisterRouter.scala:87:24] wire out_womask_276 = &_out_womask_T_276; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_276 = out_rivalid_1_130 & out_rimask_276; // @[RegisterRouter.scala:87:24] wire _out_T_3113 = out_f_rivalid_276; // @[RegisterRouter.scala:87:24] wire out_f_roready_276 = out_roready_1_130 & out_romask_276; // @[RegisterRouter.scala:87:24] wire _out_T_3114 = out_f_roready_276; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_276 = out_wivalid_1_130 & out_wimask_276; // @[RegisterRouter.scala:87:24] wire out_f_woready_276 = out_woready_1_130 & out_womask_276; // @[RegisterRouter.scala:87:24] wire _out_T_3115 = ~out_rimask_276; // @[RegisterRouter.scala:87:24] wire _out_T_3116 = ~out_wimask_276; // @[RegisterRouter.scala:87:24] wire _out_T_3117 = ~out_romask_276; // @[RegisterRouter.scala:87:24] wire _out_T_3118 = ~out_womask_276; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_225 = {hi_235, flags_0_go, _out_prepend_T_225}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3119 = out_prepend_225; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3120 = _out_T_3119; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_226 = _out_T_3120; // @[RegisterRouter.scala:87:24] wire out_rimask_277 = |_out_rimask_T_277; // @[RegisterRouter.scala:87:24] wire out_wimask_277 = &_out_wimask_T_277; // @[RegisterRouter.scala:87:24] wire out_romask_277 = |_out_romask_T_277; // @[RegisterRouter.scala:87:24] wire out_womask_277 = &_out_womask_T_277; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_277 = out_rivalid_1_131 & out_rimask_277; // @[RegisterRouter.scala:87:24] wire _out_T_3122 = out_f_rivalid_277; // @[RegisterRouter.scala:87:24] wire out_f_roready_277 = out_roready_1_131 & out_romask_277; // @[RegisterRouter.scala:87:24] wire _out_T_3123 = out_f_roready_277; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_277 = out_wivalid_1_131 & out_wimask_277; // @[RegisterRouter.scala:87:24] wire out_f_woready_277 = out_woready_1_131 & out_womask_277; // @[RegisterRouter.scala:87:24] wire _out_T_3124 = ~out_rimask_277; // @[RegisterRouter.scala:87:24] wire _out_T_3125 = ~out_wimask_277; // @[RegisterRouter.scala:87:24] wire _out_T_3126 = ~out_romask_277; // @[RegisterRouter.scala:87:24] wire _out_T_3127 = ~out_womask_277; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_226 = {hi_236, flags_0_go, _out_prepend_T_226}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3128 = out_prepend_226; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3129 = _out_T_3128; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_227 = _out_T_3129; // @[RegisterRouter.scala:87:24] wire out_rimask_278 = |_out_rimask_T_278; // @[RegisterRouter.scala:87:24] wire out_wimask_278 = &_out_wimask_T_278; // @[RegisterRouter.scala:87:24] wire out_romask_278 = |_out_romask_T_278; // @[RegisterRouter.scala:87:24] wire out_womask_278 = &_out_womask_T_278; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_278 = out_rivalid_1_132 & out_rimask_278; // @[RegisterRouter.scala:87:24] wire _out_T_3131 = out_f_rivalid_278; // @[RegisterRouter.scala:87:24] wire out_f_roready_278 = out_roready_1_132 & out_romask_278; // @[RegisterRouter.scala:87:24] wire _out_T_3132 = out_f_roready_278; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_278 = out_wivalid_1_132 & out_wimask_278; // @[RegisterRouter.scala:87:24] wire out_f_woready_278 = out_woready_1_132 & out_womask_278; // @[RegisterRouter.scala:87:24] wire _out_T_3133 = ~out_rimask_278; // @[RegisterRouter.scala:87:24] wire _out_T_3134 = ~out_wimask_278; // @[RegisterRouter.scala:87:24] wire _out_T_3135 = ~out_romask_278; // @[RegisterRouter.scala:87:24] wire _out_T_3136 = ~out_womask_278; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_227 = {hi_237, flags_0_go, _out_prepend_T_227}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3137 = out_prepend_227; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3138 = _out_T_3137; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_228 = _out_T_3138; // @[RegisterRouter.scala:87:24] wire out_rimask_279 = |_out_rimask_T_279; // @[RegisterRouter.scala:87:24] wire out_wimask_279 = &_out_wimask_T_279; // @[RegisterRouter.scala:87:24] wire out_romask_279 = |_out_romask_T_279; // @[RegisterRouter.scala:87:24] wire out_womask_279 = &_out_womask_T_279; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_279 = out_rivalid_1_133 & out_rimask_279; // @[RegisterRouter.scala:87:24] wire _out_T_3140 = out_f_rivalid_279; // @[RegisterRouter.scala:87:24] wire out_f_roready_279 = out_roready_1_133 & out_romask_279; // @[RegisterRouter.scala:87:24] wire _out_T_3141 = out_f_roready_279; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_279 = out_wivalid_1_133 & out_wimask_279; // @[RegisterRouter.scala:87:24] wire out_f_woready_279 = out_woready_1_133 & out_womask_279; // @[RegisterRouter.scala:87:24] wire _out_T_3142 = ~out_rimask_279; // @[RegisterRouter.scala:87:24] wire _out_T_3143 = ~out_wimask_279; // @[RegisterRouter.scala:87:24] wire _out_T_3144 = ~out_romask_279; // @[RegisterRouter.scala:87:24] wire _out_T_3145 = ~out_womask_279; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_228 = {hi_238, flags_0_go, _out_prepend_T_228}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3146 = out_prepend_228; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3147 = _out_T_3146; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_229 = _out_T_3147; // @[RegisterRouter.scala:87:24] wire out_rimask_280 = |_out_rimask_T_280; // @[RegisterRouter.scala:87:24] wire out_wimask_280 = &_out_wimask_T_280; // @[RegisterRouter.scala:87:24] wire out_romask_280 = |_out_romask_T_280; // @[RegisterRouter.scala:87:24] wire out_womask_280 = &_out_womask_T_280; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_280 = out_rivalid_1_134 & out_rimask_280; // @[RegisterRouter.scala:87:24] wire _out_T_3149 = out_f_rivalid_280; // @[RegisterRouter.scala:87:24] wire out_f_roready_280 = out_roready_1_134 & out_romask_280; // @[RegisterRouter.scala:87:24] wire _out_T_3150 = out_f_roready_280; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_280 = out_wivalid_1_134 & out_wimask_280; // @[RegisterRouter.scala:87:24] wire out_f_woready_280 = out_woready_1_134 & out_womask_280; // @[RegisterRouter.scala:87:24] wire _out_T_3151 = ~out_rimask_280; // @[RegisterRouter.scala:87:24] wire _out_T_3152 = ~out_wimask_280; // @[RegisterRouter.scala:87:24] wire _out_T_3153 = ~out_romask_280; // @[RegisterRouter.scala:87:24] wire _out_T_3154 = ~out_womask_280; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_229 = {hi_239, flags_0_go, _out_prepend_T_229}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3155 = out_prepend_229; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3156 = _out_T_3155; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_230 = _out_T_3156; // @[RegisterRouter.scala:87:24] wire out_rimask_281 = |_out_rimask_T_281; // @[RegisterRouter.scala:87:24] wire out_wimask_281 = &_out_wimask_T_281; // @[RegisterRouter.scala:87:24] wire out_romask_281 = |_out_romask_T_281; // @[RegisterRouter.scala:87:24] wire out_womask_281 = &_out_womask_T_281; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_281 = out_rivalid_1_135 & out_rimask_281; // @[RegisterRouter.scala:87:24] wire _out_T_3158 = out_f_rivalid_281; // @[RegisterRouter.scala:87:24] wire out_f_roready_281 = out_roready_1_135 & out_romask_281; // @[RegisterRouter.scala:87:24] wire _out_T_3159 = out_f_roready_281; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_281 = out_wivalid_1_135 & out_wimask_281; // @[RegisterRouter.scala:87:24] wire out_f_woready_281 = out_woready_1_135 & out_womask_281; // @[RegisterRouter.scala:87:24] wire _out_T_3160 = ~out_rimask_281; // @[RegisterRouter.scala:87:24] wire _out_T_3161 = ~out_wimask_281; // @[RegisterRouter.scala:87:24] wire _out_T_3162 = ~out_romask_281; // @[RegisterRouter.scala:87:24] wire _out_T_3163 = ~out_womask_281; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_230 = {hi_240, flags_0_go, _out_prepend_T_230}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3164 = out_prepend_230; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3165 = _out_T_3164; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_157 = _out_T_3165; // @[MuxLiteral.scala:49:48] wire out_rimask_282 = |_out_rimask_T_282; // @[RegisterRouter.scala:87:24] wire out_wimask_282 = &_out_wimask_T_282; // @[RegisterRouter.scala:87:24] wire out_romask_282 = |_out_romask_T_282; // @[RegisterRouter.scala:87:24] wire out_womask_282 = &_out_womask_T_282; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_282 = out_rivalid_1_136 & out_rimask_282; // @[RegisterRouter.scala:87:24] wire _out_T_3167 = out_f_rivalid_282; // @[RegisterRouter.scala:87:24] wire out_f_roready_282 = out_roready_1_136 & out_romask_282; // @[RegisterRouter.scala:87:24] wire _out_T_3168 = out_f_roready_282; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_282 = out_wivalid_1_136 & out_wimask_282; // @[RegisterRouter.scala:87:24] wire out_f_woready_282 = out_woready_1_136 & out_womask_282; // @[RegisterRouter.scala:87:24] wire _out_T_3169 = ~out_rimask_282; // @[RegisterRouter.scala:87:24] wire _out_T_3170 = ~out_wimask_282; // @[RegisterRouter.scala:87:24] wire _out_T_3171 = ~out_romask_282; // @[RegisterRouter.scala:87:24] wire _out_T_3172 = ~out_womask_282; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3174 = _out_T_3173; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_231 = _out_T_3174; // @[RegisterRouter.scala:87:24] wire out_rimask_283 = |_out_rimask_T_283; // @[RegisterRouter.scala:87:24] wire out_wimask_283 = &_out_wimask_T_283; // @[RegisterRouter.scala:87:24] wire out_romask_283 = |_out_romask_T_283; // @[RegisterRouter.scala:87:24] wire out_womask_283 = &_out_womask_T_283; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_283 = out_rivalid_1_137 & out_rimask_283; // @[RegisterRouter.scala:87:24] wire _out_T_3176 = out_f_rivalid_283; // @[RegisterRouter.scala:87:24] wire out_f_roready_283 = out_roready_1_137 & out_romask_283; // @[RegisterRouter.scala:87:24] wire _out_T_3177 = out_f_roready_283; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_283 = out_wivalid_1_137 & out_wimask_283; // @[RegisterRouter.scala:87:24] wire out_f_woready_283 = out_woready_1_137 & out_womask_283; // @[RegisterRouter.scala:87:24] wire _out_T_3178 = ~out_rimask_283; // @[RegisterRouter.scala:87:24] wire _out_T_3179 = ~out_wimask_283; // @[RegisterRouter.scala:87:24] wire _out_T_3180 = ~out_romask_283; // @[RegisterRouter.scala:87:24] wire _out_T_3181 = ~out_womask_283; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_231 = {hi_490, flags_0_go, _out_prepend_T_231}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3182 = out_prepend_231; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3183 = _out_T_3182; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_232 = _out_T_3183; // @[RegisterRouter.scala:87:24] wire out_rimask_284 = |_out_rimask_T_284; // @[RegisterRouter.scala:87:24] wire out_wimask_284 = &_out_wimask_T_284; // @[RegisterRouter.scala:87:24] wire out_romask_284 = |_out_romask_T_284; // @[RegisterRouter.scala:87:24] wire out_womask_284 = &_out_womask_T_284; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_284 = out_rivalid_1_138 & out_rimask_284; // @[RegisterRouter.scala:87:24] wire _out_T_3185 = out_f_rivalid_284; // @[RegisterRouter.scala:87:24] wire out_f_roready_284 = out_roready_1_138 & out_romask_284; // @[RegisterRouter.scala:87:24] wire _out_T_3186 = out_f_roready_284; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_284 = out_wivalid_1_138 & out_wimask_284; // @[RegisterRouter.scala:87:24] wire out_f_woready_284 = out_woready_1_138 & out_womask_284; // @[RegisterRouter.scala:87:24] wire _out_T_3187 = ~out_rimask_284; // @[RegisterRouter.scala:87:24] wire _out_T_3188 = ~out_wimask_284; // @[RegisterRouter.scala:87:24] wire _out_T_3189 = ~out_romask_284; // @[RegisterRouter.scala:87:24] wire _out_T_3190 = ~out_womask_284; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_232 = {hi_491, flags_0_go, _out_prepend_T_232}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3191 = out_prepend_232; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3192 = _out_T_3191; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_233 = _out_T_3192; // @[RegisterRouter.scala:87:24] wire out_rimask_285 = |_out_rimask_T_285; // @[RegisterRouter.scala:87:24] wire out_wimask_285 = &_out_wimask_T_285; // @[RegisterRouter.scala:87:24] wire out_romask_285 = |_out_romask_T_285; // @[RegisterRouter.scala:87:24] wire out_womask_285 = &_out_womask_T_285; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_285 = out_rivalid_1_139 & out_rimask_285; // @[RegisterRouter.scala:87:24] wire _out_T_3194 = out_f_rivalid_285; // @[RegisterRouter.scala:87:24] wire out_f_roready_285 = out_roready_1_139 & out_romask_285; // @[RegisterRouter.scala:87:24] wire _out_T_3195 = out_f_roready_285; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_285 = out_wivalid_1_139 & out_wimask_285; // @[RegisterRouter.scala:87:24] wire out_f_woready_285 = out_woready_1_139 & out_womask_285; // @[RegisterRouter.scala:87:24] wire _out_T_3196 = ~out_rimask_285; // @[RegisterRouter.scala:87:24] wire _out_T_3197 = ~out_wimask_285; // @[RegisterRouter.scala:87:24] wire _out_T_3198 = ~out_romask_285; // @[RegisterRouter.scala:87:24] wire _out_T_3199 = ~out_womask_285; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_233 = {hi_492, flags_0_go, _out_prepend_T_233}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3200 = out_prepend_233; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3201 = _out_T_3200; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_234 = _out_T_3201; // @[RegisterRouter.scala:87:24] wire out_rimask_286 = |_out_rimask_T_286; // @[RegisterRouter.scala:87:24] wire out_wimask_286 = &_out_wimask_T_286; // @[RegisterRouter.scala:87:24] wire out_romask_286 = |_out_romask_T_286; // @[RegisterRouter.scala:87:24] wire out_womask_286 = &_out_womask_T_286; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_286 = out_rivalid_1_140 & out_rimask_286; // @[RegisterRouter.scala:87:24] wire _out_T_3203 = out_f_rivalid_286; // @[RegisterRouter.scala:87:24] wire out_f_roready_286 = out_roready_1_140 & out_romask_286; // @[RegisterRouter.scala:87:24] wire _out_T_3204 = out_f_roready_286; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_286 = out_wivalid_1_140 & out_wimask_286; // @[RegisterRouter.scala:87:24] wire out_f_woready_286 = out_woready_1_140 & out_womask_286; // @[RegisterRouter.scala:87:24] wire _out_T_3205 = ~out_rimask_286; // @[RegisterRouter.scala:87:24] wire _out_T_3206 = ~out_wimask_286; // @[RegisterRouter.scala:87:24] wire _out_T_3207 = ~out_romask_286; // @[RegisterRouter.scala:87:24] wire _out_T_3208 = ~out_womask_286; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_234 = {hi_493, flags_0_go, _out_prepend_T_234}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3209 = out_prepend_234; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3210 = _out_T_3209; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_235 = _out_T_3210; // @[RegisterRouter.scala:87:24] wire out_rimask_287 = |_out_rimask_T_287; // @[RegisterRouter.scala:87:24] wire out_wimask_287 = &_out_wimask_T_287; // @[RegisterRouter.scala:87:24] wire out_romask_287 = |_out_romask_T_287; // @[RegisterRouter.scala:87:24] wire out_womask_287 = &_out_womask_T_287; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_287 = out_rivalid_1_141 & out_rimask_287; // @[RegisterRouter.scala:87:24] wire _out_T_3212 = out_f_rivalid_287; // @[RegisterRouter.scala:87:24] wire out_f_roready_287 = out_roready_1_141 & out_romask_287; // @[RegisterRouter.scala:87:24] wire _out_T_3213 = out_f_roready_287; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_287 = out_wivalid_1_141 & out_wimask_287; // @[RegisterRouter.scala:87:24] wire out_f_woready_287 = out_woready_1_141 & out_womask_287; // @[RegisterRouter.scala:87:24] wire _out_T_3214 = ~out_rimask_287; // @[RegisterRouter.scala:87:24] wire _out_T_3215 = ~out_wimask_287; // @[RegisterRouter.scala:87:24] wire _out_T_3216 = ~out_romask_287; // @[RegisterRouter.scala:87:24] wire _out_T_3217 = ~out_womask_287; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_235 = {hi_494, flags_0_go, _out_prepend_T_235}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3218 = out_prepend_235; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3219 = _out_T_3218; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_236 = _out_T_3219; // @[RegisterRouter.scala:87:24] wire out_rimask_288 = |_out_rimask_T_288; // @[RegisterRouter.scala:87:24] wire out_wimask_288 = &_out_wimask_T_288; // @[RegisterRouter.scala:87:24] wire out_romask_288 = |_out_romask_T_288; // @[RegisterRouter.scala:87:24] wire out_womask_288 = &_out_womask_T_288; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_288 = out_rivalid_1_142 & out_rimask_288; // @[RegisterRouter.scala:87:24] wire _out_T_3221 = out_f_rivalid_288; // @[RegisterRouter.scala:87:24] wire out_f_roready_288 = out_roready_1_142 & out_romask_288; // @[RegisterRouter.scala:87:24] wire _out_T_3222 = out_f_roready_288; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_288 = out_wivalid_1_142 & out_wimask_288; // @[RegisterRouter.scala:87:24] wire out_f_woready_288 = out_woready_1_142 & out_womask_288; // @[RegisterRouter.scala:87:24] wire _out_T_3223 = ~out_rimask_288; // @[RegisterRouter.scala:87:24] wire _out_T_3224 = ~out_wimask_288; // @[RegisterRouter.scala:87:24] wire _out_T_3225 = ~out_romask_288; // @[RegisterRouter.scala:87:24] wire _out_T_3226 = ~out_womask_288; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_236 = {hi_495, flags_0_go, _out_prepend_T_236}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3227 = out_prepend_236; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3228 = _out_T_3227; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_237 = _out_T_3228; // @[RegisterRouter.scala:87:24] wire out_rimask_289 = |_out_rimask_T_289; // @[RegisterRouter.scala:87:24] wire out_wimask_289 = &_out_wimask_T_289; // @[RegisterRouter.scala:87:24] wire out_romask_289 = |_out_romask_T_289; // @[RegisterRouter.scala:87:24] wire out_womask_289 = &_out_womask_T_289; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_289 = out_rivalid_1_143 & out_rimask_289; // @[RegisterRouter.scala:87:24] wire _out_T_3230 = out_f_rivalid_289; // @[RegisterRouter.scala:87:24] wire out_f_roready_289 = out_roready_1_143 & out_romask_289; // @[RegisterRouter.scala:87:24] wire _out_T_3231 = out_f_roready_289; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_289 = out_wivalid_1_143 & out_wimask_289; // @[RegisterRouter.scala:87:24] wire out_f_woready_289 = out_woready_1_143 & out_womask_289; // @[RegisterRouter.scala:87:24] wire _out_T_3232 = ~out_rimask_289; // @[RegisterRouter.scala:87:24] wire _out_T_3233 = ~out_wimask_289; // @[RegisterRouter.scala:87:24] wire _out_T_3234 = ~out_romask_289; // @[RegisterRouter.scala:87:24] wire _out_T_3235 = ~out_womask_289; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_237 = {hi_496, flags_0_go, _out_prepend_T_237}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3236 = out_prepend_237; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3237 = _out_T_3236; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_189 = _out_T_3237; // @[MuxLiteral.scala:49:48] wire out_rimask_290 = |_out_rimask_T_290; // @[RegisterRouter.scala:87:24] wire out_wimask_290 = &_out_wimask_T_290; // @[RegisterRouter.scala:87:24] wire out_romask_290 = |_out_romask_T_290; // @[RegisterRouter.scala:87:24] wire out_womask_290 = &_out_womask_T_290; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_290 = out_rivalid_1_144 & out_rimask_290; // @[RegisterRouter.scala:87:24] wire _out_T_3239 = out_f_rivalid_290; // @[RegisterRouter.scala:87:24] wire out_f_roready_290 = out_roready_1_144 & out_romask_290; // @[RegisterRouter.scala:87:24] wire _out_T_3240 = out_f_roready_290; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_290 = out_wivalid_1_144 & out_wimask_290; // @[RegisterRouter.scala:87:24] wire out_f_woready_290 = out_woready_1_144 & out_womask_290; // @[RegisterRouter.scala:87:24] wire _out_T_3241 = ~out_rimask_290; // @[RegisterRouter.scala:87:24] wire _out_T_3242 = ~out_wimask_290; // @[RegisterRouter.scala:87:24] wire _out_T_3243 = ~out_romask_290; // @[RegisterRouter.scala:87:24] wire _out_T_3244 = ~out_womask_290; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3246 = _out_T_3245; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_238 = _out_T_3246; // @[RegisterRouter.scala:87:24] wire out_rimask_291 = |_out_rimask_T_291; // @[RegisterRouter.scala:87:24] wire out_wimask_291 = &_out_wimask_T_291; // @[RegisterRouter.scala:87:24] wire out_romask_291 = |_out_romask_T_291; // @[RegisterRouter.scala:87:24] wire out_womask_291 = &_out_womask_T_291; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_291 = out_rivalid_1_145 & out_rimask_291; // @[RegisterRouter.scala:87:24] wire _out_T_3248 = out_f_rivalid_291; // @[RegisterRouter.scala:87:24] wire out_f_roready_291 = out_roready_1_145 & out_romask_291; // @[RegisterRouter.scala:87:24] wire _out_T_3249 = out_f_roready_291; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_291 = out_wivalid_1_145 & out_wimask_291; // @[RegisterRouter.scala:87:24] wire out_f_woready_291 = out_woready_1_145 & out_womask_291; // @[RegisterRouter.scala:87:24] wire _out_T_3250 = ~out_rimask_291; // @[RegisterRouter.scala:87:24] wire _out_T_3251 = ~out_wimask_291; // @[RegisterRouter.scala:87:24] wire _out_T_3252 = ~out_romask_291; // @[RegisterRouter.scala:87:24] wire _out_T_3253 = ~out_womask_291; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_238 = {hi_194, flags_0_go, _out_prepend_T_238}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3254 = out_prepend_238; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3255 = _out_T_3254; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_239 = _out_T_3255; // @[RegisterRouter.scala:87:24] wire out_rimask_292 = |_out_rimask_T_292; // @[RegisterRouter.scala:87:24] wire out_wimask_292 = &_out_wimask_T_292; // @[RegisterRouter.scala:87:24] wire out_romask_292 = |_out_romask_T_292; // @[RegisterRouter.scala:87:24] wire out_womask_292 = &_out_womask_T_292; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_292 = out_rivalid_1_146 & out_rimask_292; // @[RegisterRouter.scala:87:24] wire _out_T_3257 = out_f_rivalid_292; // @[RegisterRouter.scala:87:24] wire out_f_roready_292 = out_roready_1_146 & out_romask_292; // @[RegisterRouter.scala:87:24] wire _out_T_3258 = out_f_roready_292; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_292 = out_wivalid_1_146 & out_wimask_292; // @[RegisterRouter.scala:87:24] wire out_f_woready_292 = out_woready_1_146 & out_womask_292; // @[RegisterRouter.scala:87:24] wire _out_T_3259 = ~out_rimask_292; // @[RegisterRouter.scala:87:24] wire _out_T_3260 = ~out_wimask_292; // @[RegisterRouter.scala:87:24] wire _out_T_3261 = ~out_romask_292; // @[RegisterRouter.scala:87:24] wire _out_T_3262 = ~out_womask_292; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_239 = {hi_195, flags_0_go, _out_prepend_T_239}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3263 = out_prepend_239; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3264 = _out_T_3263; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_240 = _out_T_3264; // @[RegisterRouter.scala:87:24] wire out_rimask_293 = |_out_rimask_T_293; // @[RegisterRouter.scala:87:24] wire out_wimask_293 = &_out_wimask_T_293; // @[RegisterRouter.scala:87:24] wire out_romask_293 = |_out_romask_T_293; // @[RegisterRouter.scala:87:24] wire out_womask_293 = &_out_womask_T_293; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_293 = out_rivalid_1_147 & out_rimask_293; // @[RegisterRouter.scala:87:24] wire _out_T_3266 = out_f_rivalid_293; // @[RegisterRouter.scala:87:24] wire out_f_roready_293 = out_roready_1_147 & out_romask_293; // @[RegisterRouter.scala:87:24] wire _out_T_3267 = out_f_roready_293; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_293 = out_wivalid_1_147 & out_wimask_293; // @[RegisterRouter.scala:87:24] wire out_f_woready_293 = out_woready_1_147 & out_womask_293; // @[RegisterRouter.scala:87:24] wire _out_T_3268 = ~out_rimask_293; // @[RegisterRouter.scala:87:24] wire _out_T_3269 = ~out_wimask_293; // @[RegisterRouter.scala:87:24] wire _out_T_3270 = ~out_romask_293; // @[RegisterRouter.scala:87:24] wire _out_T_3271 = ~out_womask_293; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_240 = {hi_196, flags_0_go, _out_prepend_T_240}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3272 = out_prepend_240; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3273 = _out_T_3272; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_241 = _out_T_3273; // @[RegisterRouter.scala:87:24] wire out_rimask_294 = |_out_rimask_T_294; // @[RegisterRouter.scala:87:24] wire out_wimask_294 = &_out_wimask_T_294; // @[RegisterRouter.scala:87:24] wire out_romask_294 = |_out_romask_T_294; // @[RegisterRouter.scala:87:24] wire out_womask_294 = &_out_womask_T_294; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_294 = out_rivalid_1_148 & out_rimask_294; // @[RegisterRouter.scala:87:24] wire _out_T_3275 = out_f_rivalid_294; // @[RegisterRouter.scala:87:24] wire out_f_roready_294 = out_roready_1_148 & out_romask_294; // @[RegisterRouter.scala:87:24] wire _out_T_3276 = out_f_roready_294; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_294 = out_wivalid_1_148 & out_wimask_294; // @[RegisterRouter.scala:87:24] wire out_f_woready_294 = out_woready_1_148 & out_womask_294; // @[RegisterRouter.scala:87:24] wire _out_T_3277 = ~out_rimask_294; // @[RegisterRouter.scala:87:24] wire _out_T_3278 = ~out_wimask_294; // @[RegisterRouter.scala:87:24] wire _out_T_3279 = ~out_romask_294; // @[RegisterRouter.scala:87:24] wire _out_T_3280 = ~out_womask_294; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_241 = {hi_197, flags_0_go, _out_prepend_T_241}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3281 = out_prepend_241; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3282 = _out_T_3281; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_242 = _out_T_3282; // @[RegisterRouter.scala:87:24] wire out_rimask_295 = |_out_rimask_T_295; // @[RegisterRouter.scala:87:24] wire out_wimask_295 = &_out_wimask_T_295; // @[RegisterRouter.scala:87:24] wire out_romask_295 = |_out_romask_T_295; // @[RegisterRouter.scala:87:24] wire out_womask_295 = &_out_womask_T_295; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_295 = out_rivalid_1_149 & out_rimask_295; // @[RegisterRouter.scala:87:24] wire _out_T_3284 = out_f_rivalid_295; // @[RegisterRouter.scala:87:24] wire out_f_roready_295 = out_roready_1_149 & out_romask_295; // @[RegisterRouter.scala:87:24] wire _out_T_3285 = out_f_roready_295; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_295 = out_wivalid_1_149 & out_wimask_295; // @[RegisterRouter.scala:87:24] wire out_f_woready_295 = out_woready_1_149 & out_womask_295; // @[RegisterRouter.scala:87:24] wire _out_T_3286 = ~out_rimask_295; // @[RegisterRouter.scala:87:24] wire _out_T_3287 = ~out_wimask_295; // @[RegisterRouter.scala:87:24] wire _out_T_3288 = ~out_romask_295; // @[RegisterRouter.scala:87:24] wire _out_T_3289 = ~out_womask_295; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_242 = {hi_198, flags_0_go, _out_prepend_T_242}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3290 = out_prepend_242; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3291 = _out_T_3290; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_243 = _out_T_3291; // @[RegisterRouter.scala:87:24] wire out_rimask_296 = |_out_rimask_T_296; // @[RegisterRouter.scala:87:24] wire out_wimask_296 = &_out_wimask_T_296; // @[RegisterRouter.scala:87:24] wire out_romask_296 = |_out_romask_T_296; // @[RegisterRouter.scala:87:24] wire out_womask_296 = &_out_womask_T_296; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_296 = out_rivalid_1_150 & out_rimask_296; // @[RegisterRouter.scala:87:24] wire _out_T_3293 = out_f_rivalid_296; // @[RegisterRouter.scala:87:24] wire out_f_roready_296 = out_roready_1_150 & out_romask_296; // @[RegisterRouter.scala:87:24] wire _out_T_3294 = out_f_roready_296; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_296 = out_wivalid_1_150 & out_wimask_296; // @[RegisterRouter.scala:87:24] wire out_f_woready_296 = out_woready_1_150 & out_womask_296; // @[RegisterRouter.scala:87:24] wire _out_T_3295 = ~out_rimask_296; // @[RegisterRouter.scala:87:24] wire _out_T_3296 = ~out_wimask_296; // @[RegisterRouter.scala:87:24] wire _out_T_3297 = ~out_romask_296; // @[RegisterRouter.scala:87:24] wire _out_T_3298 = ~out_womask_296; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_243 = {hi_199, flags_0_go, _out_prepend_T_243}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3299 = out_prepend_243; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3300 = _out_T_3299; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_244 = _out_T_3300; // @[RegisterRouter.scala:87:24] wire out_rimask_297 = |_out_rimask_T_297; // @[RegisterRouter.scala:87:24] wire out_wimask_297 = &_out_wimask_T_297; // @[RegisterRouter.scala:87:24] wire out_romask_297 = |_out_romask_T_297; // @[RegisterRouter.scala:87:24] wire out_womask_297 = &_out_womask_T_297; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_297 = out_rivalid_1_151 & out_rimask_297; // @[RegisterRouter.scala:87:24] wire _out_T_3302 = out_f_rivalid_297; // @[RegisterRouter.scala:87:24] wire out_f_roready_297 = out_roready_1_151 & out_romask_297; // @[RegisterRouter.scala:87:24] wire _out_T_3303 = out_f_roready_297; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_297 = out_wivalid_1_151 & out_wimask_297; // @[RegisterRouter.scala:87:24] wire out_f_woready_297 = out_woready_1_151 & out_womask_297; // @[RegisterRouter.scala:87:24] wire _out_T_3304 = ~out_rimask_297; // @[RegisterRouter.scala:87:24] wire _out_T_3305 = ~out_wimask_297; // @[RegisterRouter.scala:87:24] wire _out_T_3306 = ~out_romask_297; // @[RegisterRouter.scala:87:24] wire _out_T_3307 = ~out_womask_297; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_244 = {hi_200, flags_0_go, _out_prepend_T_244}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3308 = out_prepend_244; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3309 = _out_T_3308; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_152 = _out_T_3309; // @[MuxLiteral.scala:49:48] wire out_rimask_298 = |_out_rimask_T_298; // @[RegisterRouter.scala:87:24] wire out_wimask_298 = &_out_wimask_T_298; // @[RegisterRouter.scala:87:24] wire out_romask_298 = |_out_romask_T_298; // @[RegisterRouter.scala:87:24] wire out_womask_298 = &_out_womask_T_298; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_298 = out_rivalid_1_152 & out_rimask_298; // @[RegisterRouter.scala:87:24] wire _out_T_3311 = out_f_rivalid_298; // @[RegisterRouter.scala:87:24] wire out_f_roready_298 = out_roready_1_152 & out_romask_298; // @[RegisterRouter.scala:87:24] wire _out_T_3312 = out_f_roready_298; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_298 = out_wivalid_1_152 & out_wimask_298; // @[RegisterRouter.scala:87:24] wire out_f_woready_298 = out_woready_1_152 & out_womask_298; // @[RegisterRouter.scala:87:24] wire _out_T_3313 = ~out_rimask_298; // @[RegisterRouter.scala:87:24] wire _out_T_3314 = ~out_wimask_298; // @[RegisterRouter.scala:87:24] wire _out_T_3315 = ~out_romask_298; // @[RegisterRouter.scala:87:24] wire _out_T_3316 = ~out_womask_298; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3318 = _out_T_3317; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_245 = _out_T_3318; // @[RegisterRouter.scala:87:24] wire out_rimask_299 = |_out_rimask_T_299; // @[RegisterRouter.scala:87:24] wire out_wimask_299 = &_out_wimask_T_299; // @[RegisterRouter.scala:87:24] wire out_romask_299 = |_out_romask_T_299; // @[RegisterRouter.scala:87:24] wire out_womask_299 = &_out_womask_T_299; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_299 = out_rivalid_1_153 & out_rimask_299; // @[RegisterRouter.scala:87:24] wire _out_T_3320 = out_f_rivalid_299; // @[RegisterRouter.scala:87:24] wire out_f_roready_299 = out_roready_1_153 & out_romask_299; // @[RegisterRouter.scala:87:24] wire _out_T_3321 = out_f_roready_299; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_299 = out_wivalid_1_153 & out_wimask_299; // @[RegisterRouter.scala:87:24] wire out_f_woready_299 = out_woready_1_153 & out_womask_299; // @[RegisterRouter.scala:87:24] wire _out_T_3322 = ~out_rimask_299; // @[RegisterRouter.scala:87:24] wire _out_T_3323 = ~out_wimask_299; // @[RegisterRouter.scala:87:24] wire _out_T_3324 = ~out_romask_299; // @[RegisterRouter.scala:87:24] wire _out_T_3325 = ~out_womask_299; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_245 = {hi_802, flags_0_go, _out_prepend_T_245}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3326 = out_prepend_245; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3327 = _out_T_3326; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_246 = _out_T_3327; // @[RegisterRouter.scala:87:24] wire out_rimask_300 = |_out_rimask_T_300; // @[RegisterRouter.scala:87:24] wire out_wimask_300 = &_out_wimask_T_300; // @[RegisterRouter.scala:87:24] wire out_romask_300 = |_out_romask_T_300; // @[RegisterRouter.scala:87:24] wire out_womask_300 = &_out_womask_T_300; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_300 = out_rivalid_1_154 & out_rimask_300; // @[RegisterRouter.scala:87:24] wire _out_T_3329 = out_f_rivalid_300; // @[RegisterRouter.scala:87:24] wire out_f_roready_300 = out_roready_1_154 & out_romask_300; // @[RegisterRouter.scala:87:24] wire _out_T_3330 = out_f_roready_300; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_300 = out_wivalid_1_154 & out_wimask_300; // @[RegisterRouter.scala:87:24] wire out_f_woready_300 = out_woready_1_154 & out_womask_300; // @[RegisterRouter.scala:87:24] wire _out_T_3331 = ~out_rimask_300; // @[RegisterRouter.scala:87:24] wire _out_T_3332 = ~out_wimask_300; // @[RegisterRouter.scala:87:24] wire _out_T_3333 = ~out_romask_300; // @[RegisterRouter.scala:87:24] wire _out_T_3334 = ~out_womask_300; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_246 = {hi_803, flags_0_go, _out_prepend_T_246}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3335 = out_prepend_246; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3336 = _out_T_3335; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_247 = _out_T_3336; // @[RegisterRouter.scala:87:24] wire out_rimask_301 = |_out_rimask_T_301; // @[RegisterRouter.scala:87:24] wire out_wimask_301 = &_out_wimask_T_301; // @[RegisterRouter.scala:87:24] wire out_romask_301 = |_out_romask_T_301; // @[RegisterRouter.scala:87:24] wire out_womask_301 = &_out_womask_T_301; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_301 = out_rivalid_1_155 & out_rimask_301; // @[RegisterRouter.scala:87:24] wire _out_T_3338 = out_f_rivalid_301; // @[RegisterRouter.scala:87:24] wire out_f_roready_301 = out_roready_1_155 & out_romask_301; // @[RegisterRouter.scala:87:24] wire _out_T_3339 = out_f_roready_301; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_301 = out_wivalid_1_155 & out_wimask_301; // @[RegisterRouter.scala:87:24] wire out_f_woready_301 = out_woready_1_155 & out_womask_301; // @[RegisterRouter.scala:87:24] wire _out_T_3340 = ~out_rimask_301; // @[RegisterRouter.scala:87:24] wire _out_T_3341 = ~out_wimask_301; // @[RegisterRouter.scala:87:24] wire _out_T_3342 = ~out_romask_301; // @[RegisterRouter.scala:87:24] wire _out_T_3343 = ~out_womask_301; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_247 = {hi_804, flags_0_go, _out_prepend_T_247}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3344 = out_prepend_247; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3345 = _out_T_3344; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_248 = _out_T_3345; // @[RegisterRouter.scala:87:24] wire out_rimask_302 = |_out_rimask_T_302; // @[RegisterRouter.scala:87:24] wire out_wimask_302 = &_out_wimask_T_302; // @[RegisterRouter.scala:87:24] wire out_romask_302 = |_out_romask_T_302; // @[RegisterRouter.scala:87:24] wire out_womask_302 = &_out_womask_T_302; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_302 = out_rivalid_1_156 & out_rimask_302; // @[RegisterRouter.scala:87:24] wire _out_T_3347 = out_f_rivalid_302; // @[RegisterRouter.scala:87:24] wire out_f_roready_302 = out_roready_1_156 & out_romask_302; // @[RegisterRouter.scala:87:24] wire _out_T_3348 = out_f_roready_302; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_302 = out_wivalid_1_156 & out_wimask_302; // @[RegisterRouter.scala:87:24] wire out_f_woready_302 = out_woready_1_156 & out_womask_302; // @[RegisterRouter.scala:87:24] wire _out_T_3349 = ~out_rimask_302; // @[RegisterRouter.scala:87:24] wire _out_T_3350 = ~out_wimask_302; // @[RegisterRouter.scala:87:24] wire _out_T_3351 = ~out_romask_302; // @[RegisterRouter.scala:87:24] wire _out_T_3352 = ~out_womask_302; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_248 = {hi_805, flags_0_go, _out_prepend_T_248}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3353 = out_prepend_248; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3354 = _out_T_3353; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_249 = _out_T_3354; // @[RegisterRouter.scala:87:24] wire out_rimask_303 = |_out_rimask_T_303; // @[RegisterRouter.scala:87:24] wire out_wimask_303 = &_out_wimask_T_303; // @[RegisterRouter.scala:87:24] wire out_romask_303 = |_out_romask_T_303; // @[RegisterRouter.scala:87:24] wire out_womask_303 = &_out_womask_T_303; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_303 = out_rivalid_1_157 & out_rimask_303; // @[RegisterRouter.scala:87:24] wire _out_T_3356 = out_f_rivalid_303; // @[RegisterRouter.scala:87:24] wire out_f_roready_303 = out_roready_1_157 & out_romask_303; // @[RegisterRouter.scala:87:24] wire _out_T_3357 = out_f_roready_303; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_303 = out_wivalid_1_157 & out_wimask_303; // @[RegisterRouter.scala:87:24] wire out_f_woready_303 = out_woready_1_157 & out_womask_303; // @[RegisterRouter.scala:87:24] wire _out_T_3358 = ~out_rimask_303; // @[RegisterRouter.scala:87:24] wire _out_T_3359 = ~out_wimask_303; // @[RegisterRouter.scala:87:24] wire _out_T_3360 = ~out_romask_303; // @[RegisterRouter.scala:87:24] wire _out_T_3361 = ~out_womask_303; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_249 = {hi_806, flags_0_go, _out_prepend_T_249}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3362 = out_prepend_249; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3363 = _out_T_3362; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_250 = _out_T_3363; // @[RegisterRouter.scala:87:24] wire out_rimask_304 = |_out_rimask_T_304; // @[RegisterRouter.scala:87:24] wire out_wimask_304 = &_out_wimask_T_304; // @[RegisterRouter.scala:87:24] wire out_romask_304 = |_out_romask_T_304; // @[RegisterRouter.scala:87:24] wire out_womask_304 = &_out_womask_T_304; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_304 = out_rivalid_1_158 & out_rimask_304; // @[RegisterRouter.scala:87:24] wire _out_T_3365 = out_f_rivalid_304; // @[RegisterRouter.scala:87:24] wire out_f_roready_304 = out_roready_1_158 & out_romask_304; // @[RegisterRouter.scala:87:24] wire _out_T_3366 = out_f_roready_304; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_304 = out_wivalid_1_158 & out_wimask_304; // @[RegisterRouter.scala:87:24] wire out_f_woready_304 = out_woready_1_158 & out_womask_304; // @[RegisterRouter.scala:87:24] wire _out_T_3367 = ~out_rimask_304; // @[RegisterRouter.scala:87:24] wire _out_T_3368 = ~out_wimask_304; // @[RegisterRouter.scala:87:24] wire _out_T_3369 = ~out_romask_304; // @[RegisterRouter.scala:87:24] wire _out_T_3370 = ~out_womask_304; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_250 = {hi_807, flags_0_go, _out_prepend_T_250}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3371 = out_prepend_250; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3372 = _out_T_3371; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_251 = _out_T_3372; // @[RegisterRouter.scala:87:24] wire out_rimask_305 = |_out_rimask_T_305; // @[RegisterRouter.scala:87:24] wire out_wimask_305 = &_out_wimask_T_305; // @[RegisterRouter.scala:87:24] wire out_romask_305 = |_out_romask_T_305; // @[RegisterRouter.scala:87:24] wire out_womask_305 = &_out_womask_T_305; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_305 = out_rivalid_1_159 & out_rimask_305; // @[RegisterRouter.scala:87:24] wire _out_T_3374 = out_f_rivalid_305; // @[RegisterRouter.scala:87:24] wire out_f_roready_305 = out_roready_1_159 & out_romask_305; // @[RegisterRouter.scala:87:24] wire _out_T_3375 = out_f_roready_305; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_305 = out_wivalid_1_159 & out_wimask_305; // @[RegisterRouter.scala:87:24] wire out_f_woready_305 = out_woready_1_159 & out_womask_305; // @[RegisterRouter.scala:87:24] wire _out_T_3376 = ~out_rimask_305; // @[RegisterRouter.scala:87:24] wire _out_T_3377 = ~out_wimask_305; // @[RegisterRouter.scala:87:24] wire _out_T_3378 = ~out_romask_305; // @[RegisterRouter.scala:87:24] wire _out_T_3379 = ~out_womask_305; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_251 = {hi_808, flags_0_go, _out_prepend_T_251}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3380 = out_prepend_251; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3381 = _out_T_3380; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_228 = _out_T_3381; // @[MuxLiteral.scala:49:48] wire out_rimask_306 = |_out_rimask_T_306; // @[RegisterRouter.scala:87:24] wire out_wimask_306 = &_out_wimask_T_306; // @[RegisterRouter.scala:87:24] wire out_romask_306 = |_out_romask_T_306; // @[RegisterRouter.scala:87:24] wire out_womask_306 = &_out_womask_T_306; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_306 = out_rivalid_1_160 & out_rimask_306; // @[RegisterRouter.scala:87:24] wire _out_T_3383 = out_f_rivalid_306; // @[RegisterRouter.scala:87:24] wire out_f_roready_306 = out_roready_1_160 & out_romask_306; // @[RegisterRouter.scala:87:24] wire _out_T_3384 = out_f_roready_306; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_306 = out_wivalid_1_160 & out_wimask_306; // @[RegisterRouter.scala:87:24] wire out_f_woready_306 = out_woready_1_160 & out_womask_306; // @[RegisterRouter.scala:87:24] wire _out_T_3385 = ~out_rimask_306; // @[RegisterRouter.scala:87:24] wire _out_T_3386 = ~out_wimask_306; // @[RegisterRouter.scala:87:24] wire _out_T_3387 = ~out_romask_306; // @[RegisterRouter.scala:87:24] wire _out_T_3388 = ~out_womask_306; // @[RegisterRouter.scala:87:24] wire out_rimask_307 = |_out_rimask_T_307; // @[RegisterRouter.scala:87:24] wire out_wimask_307 = &_out_wimask_T_307; // @[RegisterRouter.scala:87:24] wire out_romask_307 = |_out_romask_T_307; // @[RegisterRouter.scala:87:24] wire out_womask_307 = &_out_womask_T_307; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_307 = out_rivalid_1_161 & out_rimask_307; // @[RegisterRouter.scala:87:24] wire _out_T_3392 = out_f_rivalid_307; // @[RegisterRouter.scala:87:24] wire out_f_roready_307 = out_roready_1_161 & out_romask_307; // @[RegisterRouter.scala:87:24] wire _out_T_3393 = out_f_roready_307; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_307 = out_wivalid_1_161 & out_wimask_307; // @[RegisterRouter.scala:87:24] wire out_f_woready_307 = out_woready_1_161 & out_womask_307; // @[RegisterRouter.scala:87:24] wire _out_T_3394 = ~out_rimask_307; // @[RegisterRouter.scala:87:24] wire _out_T_3395 = ~out_wimask_307; // @[RegisterRouter.scala:87:24] wire _out_T_3396 = ~out_romask_307; // @[RegisterRouter.scala:87:24] wire _out_T_3397 = ~out_womask_307; // @[RegisterRouter.scala:87:24] wire out_rimask_308 = |_out_rimask_T_308; // @[RegisterRouter.scala:87:24] wire out_wimask_308 = &_out_wimask_T_308; // @[RegisterRouter.scala:87:24] wire out_romask_308 = |_out_romask_T_308; // @[RegisterRouter.scala:87:24] wire out_womask_308 = &_out_womask_T_308; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_308 = out_rivalid_1_162 & out_rimask_308; // @[RegisterRouter.scala:87:24] wire _out_T_3401 = out_f_rivalid_308; // @[RegisterRouter.scala:87:24] wire out_f_roready_308 = out_roready_1_162 & out_romask_308; // @[RegisterRouter.scala:87:24] wire _out_T_3402 = out_f_roready_308; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_308 = out_wivalid_1_162 & out_wimask_308; // @[RegisterRouter.scala:87:24] wire out_f_woready_308 = out_woready_1_162 & out_womask_308; // @[RegisterRouter.scala:87:24] wire _out_T_3403 = ~out_rimask_308; // @[RegisterRouter.scala:87:24] wire _out_T_3404 = ~out_wimask_308; // @[RegisterRouter.scala:87:24] wire _out_T_3405 = ~out_romask_308; // @[RegisterRouter.scala:87:24] wire _out_T_3406 = ~out_womask_308; // @[RegisterRouter.scala:87:24] wire out_rimask_309 = |_out_rimask_T_309; // @[RegisterRouter.scala:87:24] wire out_wimask_309 = &_out_wimask_T_309; // @[RegisterRouter.scala:87:24] wire out_romask_309 = |_out_romask_T_309; // @[RegisterRouter.scala:87:24] wire out_womask_309 = &_out_womask_T_309; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_309 = out_rivalid_1_163 & out_rimask_309; // @[RegisterRouter.scala:87:24] wire _out_T_3410 = out_f_rivalid_309; // @[RegisterRouter.scala:87:24] wire out_f_roready_309 = out_roready_1_163 & out_romask_309; // @[RegisterRouter.scala:87:24] wire _out_T_3411 = out_f_roready_309; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_309 = out_wivalid_1_163 & out_wimask_309; // @[RegisterRouter.scala:87:24] wire out_f_woready_309 = out_woready_1_163 & out_womask_309; // @[RegisterRouter.scala:87:24] wire _out_T_3412 = ~out_rimask_309; // @[RegisterRouter.scala:87:24] wire _out_T_3413 = ~out_wimask_309; // @[RegisterRouter.scala:87:24] wire _out_T_3414 = ~out_romask_309; // @[RegisterRouter.scala:87:24] wire _out_T_3415 = ~out_womask_309; // @[RegisterRouter.scala:87:24] wire out_rimask_310 = |_out_rimask_T_310; // @[RegisterRouter.scala:87:24] wire out_wimask_310 = &_out_wimask_T_310; // @[RegisterRouter.scala:87:24] wire out_romask_310 = |_out_romask_T_310; // @[RegisterRouter.scala:87:24] wire out_womask_310 = &_out_womask_T_310; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_310 = out_rivalid_1_164 & out_rimask_310; // @[RegisterRouter.scala:87:24] wire _out_T_3419 = out_f_rivalid_310; // @[RegisterRouter.scala:87:24] wire out_f_roready_310 = out_roready_1_164 & out_romask_310; // @[RegisterRouter.scala:87:24] wire _out_T_3420 = out_f_roready_310; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_310 = out_wivalid_1_164 & out_wimask_310; // @[RegisterRouter.scala:87:24] wire out_f_woready_310 = out_woready_1_164 & out_womask_310; // @[RegisterRouter.scala:87:24] wire _out_T_3421 = ~out_rimask_310; // @[RegisterRouter.scala:87:24] wire _out_T_3422 = ~out_wimask_310; // @[RegisterRouter.scala:87:24] wire _out_T_3423 = ~out_romask_310; // @[RegisterRouter.scala:87:24] wire _out_T_3424 = ~out_womask_310; // @[RegisterRouter.scala:87:24] wire out_rimask_311 = |_out_rimask_T_311; // @[RegisterRouter.scala:87:24] wire out_wimask_311 = &_out_wimask_T_311; // @[RegisterRouter.scala:87:24] wire out_romask_311 = |_out_romask_T_311; // @[RegisterRouter.scala:87:24] wire out_womask_311 = &_out_womask_T_311; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_311 = out_rivalid_1_165 & out_rimask_311; // @[RegisterRouter.scala:87:24] wire _out_T_3428 = out_f_rivalid_311; // @[RegisterRouter.scala:87:24] wire out_f_roready_311 = out_roready_1_165 & out_romask_311; // @[RegisterRouter.scala:87:24] wire _out_T_3429 = out_f_roready_311; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_311 = out_wivalid_1_165 & out_wimask_311; // @[RegisterRouter.scala:87:24] wire out_f_woready_311 = out_woready_1_165 & out_womask_311; // @[RegisterRouter.scala:87:24] wire _out_T_3430 = ~out_rimask_311; // @[RegisterRouter.scala:87:24] wire _out_T_3431 = ~out_wimask_311; // @[RegisterRouter.scala:87:24] wire _out_T_3432 = ~out_romask_311; // @[RegisterRouter.scala:87:24] wire _out_T_3433 = ~out_womask_311; // @[RegisterRouter.scala:87:24] wire out_rimask_312 = |_out_rimask_T_312; // @[RegisterRouter.scala:87:24] wire out_wimask_312 = &_out_wimask_T_312; // @[RegisterRouter.scala:87:24] wire out_romask_312 = |_out_romask_T_312; // @[RegisterRouter.scala:87:24] wire out_womask_312 = &_out_womask_T_312; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_312 = out_rivalid_1_166 & out_rimask_312; // @[RegisterRouter.scala:87:24] wire _out_T_3437 = out_f_rivalid_312; // @[RegisterRouter.scala:87:24] wire out_f_roready_312 = out_roready_1_166 & out_romask_312; // @[RegisterRouter.scala:87:24] wire _out_T_3438 = out_f_roready_312; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_312 = out_wivalid_1_166 & out_wimask_312; // @[RegisterRouter.scala:87:24] wire out_f_woready_312 = out_woready_1_166 & out_womask_312; // @[RegisterRouter.scala:87:24] wire _out_T_3439 = ~out_rimask_312; // @[RegisterRouter.scala:87:24] wire _out_T_3440 = ~out_wimask_312; // @[RegisterRouter.scala:87:24] wire _out_T_3441 = ~out_romask_312; // @[RegisterRouter.scala:87:24] wire _out_T_3442 = ~out_womask_312; // @[RegisterRouter.scala:87:24] wire out_rimask_313 = |_out_rimask_T_313; // @[RegisterRouter.scala:87:24] wire out_wimask_313 = &_out_wimask_T_313; // @[RegisterRouter.scala:87:24] wire out_romask_313 = |_out_romask_T_313; // @[RegisterRouter.scala:87:24] wire out_womask_313 = &_out_womask_T_313; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_313 = out_rivalid_1_167 & out_rimask_313; // @[RegisterRouter.scala:87:24] wire _out_T_3446 = out_f_rivalid_313; // @[RegisterRouter.scala:87:24] wire out_f_roready_313 = out_roready_1_167 & out_romask_313; // @[RegisterRouter.scala:87:24] wire _out_T_3447 = out_f_roready_313; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_313 = out_wivalid_1_167 & out_wimask_313; // @[RegisterRouter.scala:87:24] wire out_f_woready_313 = out_woready_1_167 & out_womask_313; // @[RegisterRouter.scala:87:24] wire _out_T_3448 = ~out_rimask_313; // @[RegisterRouter.scala:87:24] wire _out_T_3449 = ~out_wimask_313; // @[RegisterRouter.scala:87:24] wire _out_T_3450 = ~out_romask_313; // @[RegisterRouter.scala:87:24] wire _out_T_3451 = ~out_womask_313; // @[RegisterRouter.scala:87:24] wire out_rimask_314 = |_out_rimask_T_314; // @[RegisterRouter.scala:87:24] wire out_wimask_314 = &_out_wimask_T_314; // @[RegisterRouter.scala:87:24] wire out_romask_314 = |_out_romask_T_314; // @[RegisterRouter.scala:87:24] wire out_womask_314 = &_out_womask_T_314; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_314 = out_rivalid_1_168 & out_rimask_314; // @[RegisterRouter.scala:87:24] wire _out_T_3455 = out_f_rivalid_314; // @[RegisterRouter.scala:87:24] wire out_f_roready_314 = out_roready_1_168 & out_romask_314; // @[RegisterRouter.scala:87:24] wire _out_T_3456 = out_f_roready_314; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_314 = out_wivalid_1_168 & out_wimask_314; // @[RegisterRouter.scala:87:24] wire out_f_woready_314 = out_woready_1_168 & out_womask_314; // @[RegisterRouter.scala:87:24] wire _out_T_3457 = ~out_rimask_314; // @[RegisterRouter.scala:87:24] wire _out_T_3458 = ~out_wimask_314; // @[RegisterRouter.scala:87:24] wire _out_T_3459 = ~out_romask_314; // @[RegisterRouter.scala:87:24] wire _out_T_3460 = ~out_womask_314; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3462 = _out_T_3461; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_259 = _out_T_3462; // @[RegisterRouter.scala:87:24] wire out_rimask_315 = |_out_rimask_T_315; // @[RegisterRouter.scala:87:24] wire out_wimask_315 = &_out_wimask_T_315; // @[RegisterRouter.scala:87:24] wire out_romask_315 = |_out_romask_T_315; // @[RegisterRouter.scala:87:24] wire out_womask_315 = &_out_womask_T_315; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_315 = out_rivalid_1_169 & out_rimask_315; // @[RegisterRouter.scala:87:24] wire _out_T_3464 = out_f_rivalid_315; // @[RegisterRouter.scala:87:24] wire out_f_roready_315 = out_roready_1_169 & out_romask_315; // @[RegisterRouter.scala:87:24] wire _out_T_3465 = out_f_roready_315; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_315 = out_wivalid_1_169 & out_wimask_315; // @[RegisterRouter.scala:87:24] wire out_f_woready_315 = out_woready_1_169 & out_womask_315; // @[RegisterRouter.scala:87:24] wire _out_T_3466 = ~out_rimask_315; // @[RegisterRouter.scala:87:24] wire _out_T_3467 = ~out_wimask_315; // @[RegisterRouter.scala:87:24] wire _out_T_3468 = ~out_romask_315; // @[RegisterRouter.scala:87:24] wire _out_T_3469 = ~out_womask_315; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_259 = {hi_706, flags_0_go, _out_prepend_T_259}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3470 = out_prepend_259; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3471 = _out_T_3470; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_260 = _out_T_3471; // @[RegisterRouter.scala:87:24] wire out_rimask_316 = |_out_rimask_T_316; // @[RegisterRouter.scala:87:24] wire out_wimask_316 = &_out_wimask_T_316; // @[RegisterRouter.scala:87:24] wire out_romask_316 = |_out_romask_T_316; // @[RegisterRouter.scala:87:24] wire out_womask_316 = &_out_womask_T_316; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_316 = out_rivalid_1_170 & out_rimask_316; // @[RegisterRouter.scala:87:24] wire _out_T_3473 = out_f_rivalid_316; // @[RegisterRouter.scala:87:24] wire out_f_roready_316 = out_roready_1_170 & out_romask_316; // @[RegisterRouter.scala:87:24] wire _out_T_3474 = out_f_roready_316; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_316 = out_wivalid_1_170 & out_wimask_316; // @[RegisterRouter.scala:87:24] wire out_f_woready_316 = out_woready_1_170 & out_womask_316; // @[RegisterRouter.scala:87:24] wire _out_T_3475 = ~out_rimask_316; // @[RegisterRouter.scala:87:24] wire _out_T_3476 = ~out_wimask_316; // @[RegisterRouter.scala:87:24] wire _out_T_3477 = ~out_romask_316; // @[RegisterRouter.scala:87:24] wire _out_T_3478 = ~out_womask_316; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_260 = {hi_707, flags_0_go, _out_prepend_T_260}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3479 = out_prepend_260; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3480 = _out_T_3479; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_261 = _out_T_3480; // @[RegisterRouter.scala:87:24] wire out_rimask_317 = |_out_rimask_T_317; // @[RegisterRouter.scala:87:24] wire out_wimask_317 = &_out_wimask_T_317; // @[RegisterRouter.scala:87:24] wire out_romask_317 = |_out_romask_T_317; // @[RegisterRouter.scala:87:24] wire out_womask_317 = &_out_womask_T_317; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_317 = out_rivalid_1_171 & out_rimask_317; // @[RegisterRouter.scala:87:24] wire _out_T_3482 = out_f_rivalid_317; // @[RegisterRouter.scala:87:24] wire out_f_roready_317 = out_roready_1_171 & out_romask_317; // @[RegisterRouter.scala:87:24] wire _out_T_3483 = out_f_roready_317; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_317 = out_wivalid_1_171 & out_wimask_317; // @[RegisterRouter.scala:87:24] wire out_f_woready_317 = out_woready_1_171 & out_womask_317; // @[RegisterRouter.scala:87:24] wire _out_T_3484 = ~out_rimask_317; // @[RegisterRouter.scala:87:24] wire _out_T_3485 = ~out_wimask_317; // @[RegisterRouter.scala:87:24] wire _out_T_3486 = ~out_romask_317; // @[RegisterRouter.scala:87:24] wire _out_T_3487 = ~out_womask_317; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_261 = {hi_708, flags_0_go, _out_prepend_T_261}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3488 = out_prepend_261; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3489 = _out_T_3488; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_262 = _out_T_3489; // @[RegisterRouter.scala:87:24] wire out_rimask_318 = |_out_rimask_T_318; // @[RegisterRouter.scala:87:24] wire out_wimask_318 = &_out_wimask_T_318; // @[RegisterRouter.scala:87:24] wire out_romask_318 = |_out_romask_T_318; // @[RegisterRouter.scala:87:24] wire out_womask_318 = &_out_womask_T_318; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_318 = out_rivalid_1_172 & out_rimask_318; // @[RegisterRouter.scala:87:24] wire _out_T_3491 = out_f_rivalid_318; // @[RegisterRouter.scala:87:24] wire out_f_roready_318 = out_roready_1_172 & out_romask_318; // @[RegisterRouter.scala:87:24] wire _out_T_3492 = out_f_roready_318; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_318 = out_wivalid_1_172 & out_wimask_318; // @[RegisterRouter.scala:87:24] wire out_f_woready_318 = out_woready_1_172 & out_womask_318; // @[RegisterRouter.scala:87:24] wire _out_T_3493 = ~out_rimask_318; // @[RegisterRouter.scala:87:24] wire _out_T_3494 = ~out_wimask_318; // @[RegisterRouter.scala:87:24] wire _out_T_3495 = ~out_romask_318; // @[RegisterRouter.scala:87:24] wire _out_T_3496 = ~out_womask_318; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_262 = {hi_709, flags_0_go, _out_prepend_T_262}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3497 = out_prepend_262; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3498 = _out_T_3497; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_263 = _out_T_3498; // @[RegisterRouter.scala:87:24] wire out_rimask_319 = |_out_rimask_T_319; // @[RegisterRouter.scala:87:24] wire out_wimask_319 = &_out_wimask_T_319; // @[RegisterRouter.scala:87:24] wire out_romask_319 = |_out_romask_T_319; // @[RegisterRouter.scala:87:24] wire out_womask_319 = &_out_womask_T_319; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_319 = out_rivalid_1_173 & out_rimask_319; // @[RegisterRouter.scala:87:24] wire _out_T_3500 = out_f_rivalid_319; // @[RegisterRouter.scala:87:24] wire out_f_roready_319 = out_roready_1_173 & out_romask_319; // @[RegisterRouter.scala:87:24] wire _out_T_3501 = out_f_roready_319; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_319 = out_wivalid_1_173 & out_wimask_319; // @[RegisterRouter.scala:87:24] wire out_f_woready_319 = out_woready_1_173 & out_womask_319; // @[RegisterRouter.scala:87:24] wire _out_T_3502 = ~out_rimask_319; // @[RegisterRouter.scala:87:24] wire _out_T_3503 = ~out_wimask_319; // @[RegisterRouter.scala:87:24] wire _out_T_3504 = ~out_romask_319; // @[RegisterRouter.scala:87:24] wire _out_T_3505 = ~out_womask_319; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_263 = {hi_710, flags_0_go, _out_prepend_T_263}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3506 = out_prepend_263; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3507 = _out_T_3506; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_264 = _out_T_3507; // @[RegisterRouter.scala:87:24] wire out_rimask_320 = |_out_rimask_T_320; // @[RegisterRouter.scala:87:24] wire out_wimask_320 = &_out_wimask_T_320; // @[RegisterRouter.scala:87:24] wire out_romask_320 = |_out_romask_T_320; // @[RegisterRouter.scala:87:24] wire out_womask_320 = &_out_womask_T_320; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_320 = out_rivalid_1_174 & out_rimask_320; // @[RegisterRouter.scala:87:24] wire _out_T_3509 = out_f_rivalid_320; // @[RegisterRouter.scala:87:24] wire out_f_roready_320 = out_roready_1_174 & out_romask_320; // @[RegisterRouter.scala:87:24] wire _out_T_3510 = out_f_roready_320; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_320 = out_wivalid_1_174 & out_wimask_320; // @[RegisterRouter.scala:87:24] wire out_f_woready_320 = out_woready_1_174 & out_womask_320; // @[RegisterRouter.scala:87:24] wire _out_T_3511 = ~out_rimask_320; // @[RegisterRouter.scala:87:24] wire _out_T_3512 = ~out_wimask_320; // @[RegisterRouter.scala:87:24] wire _out_T_3513 = ~out_romask_320; // @[RegisterRouter.scala:87:24] wire _out_T_3514 = ~out_womask_320; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_264 = {hi_711, flags_0_go, _out_prepend_T_264}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3515 = out_prepend_264; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3516 = _out_T_3515; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_265 = _out_T_3516; // @[RegisterRouter.scala:87:24] wire out_rimask_321 = |_out_rimask_T_321; // @[RegisterRouter.scala:87:24] wire out_wimask_321 = &_out_wimask_T_321; // @[RegisterRouter.scala:87:24] wire out_romask_321 = |_out_romask_T_321; // @[RegisterRouter.scala:87:24] wire out_womask_321 = &_out_womask_T_321; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_321 = out_rivalid_1_175 & out_rimask_321; // @[RegisterRouter.scala:87:24] wire _out_T_3518 = out_f_rivalid_321; // @[RegisterRouter.scala:87:24] wire out_f_roready_321 = out_roready_1_175 & out_romask_321; // @[RegisterRouter.scala:87:24] wire _out_T_3519 = out_f_roready_321; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_321 = out_wivalid_1_175 & out_wimask_321; // @[RegisterRouter.scala:87:24] wire out_f_woready_321 = out_woready_1_175 & out_womask_321; // @[RegisterRouter.scala:87:24] wire _out_T_3520 = ~out_rimask_321; // @[RegisterRouter.scala:87:24] wire _out_T_3521 = ~out_wimask_321; // @[RegisterRouter.scala:87:24] wire _out_T_3522 = ~out_romask_321; // @[RegisterRouter.scala:87:24] wire _out_T_3523 = ~out_womask_321; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_265 = {hi_712, flags_0_go, _out_prepend_T_265}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3524 = out_prepend_265; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3525 = _out_T_3524; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_216 = _out_T_3525; // @[MuxLiteral.scala:49:48] wire out_rimask_322 = |_out_rimask_T_322; // @[RegisterRouter.scala:87:24] wire out_wimask_322 = &_out_wimask_T_322; // @[RegisterRouter.scala:87:24] wire out_romask_322 = |_out_romask_T_322; // @[RegisterRouter.scala:87:24] wire out_womask_322 = &_out_womask_T_322; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_322 = out_rivalid_1_176 & out_rimask_322; // @[RegisterRouter.scala:87:24] wire _out_T_3527 = out_f_rivalid_322; // @[RegisterRouter.scala:87:24] wire out_f_roready_322 = out_roready_1_176 & out_romask_322; // @[RegisterRouter.scala:87:24] wire _out_T_3528 = out_f_roready_322; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_322 = out_wivalid_1_176 & out_wimask_322; // @[RegisterRouter.scala:87:24] wire out_f_woready_322 = out_woready_1_176 & out_womask_322; // @[RegisterRouter.scala:87:24] wire _out_T_3529 = ~out_rimask_322; // @[RegisterRouter.scala:87:24] wire _out_T_3530 = ~out_wimask_322; // @[RegisterRouter.scala:87:24] wire _out_T_3531 = ~out_romask_322; // @[RegisterRouter.scala:87:24] wire _out_T_3532 = ~out_womask_322; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3534 = _out_T_3533; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_266 = _out_T_3534; // @[RegisterRouter.scala:87:24] wire out_rimask_323 = |_out_rimask_T_323; // @[RegisterRouter.scala:87:24] wire out_wimask_323 = &_out_wimask_T_323; // @[RegisterRouter.scala:87:24] wire out_romask_323 = |_out_romask_T_323; // @[RegisterRouter.scala:87:24] wire out_womask_323 = &_out_womask_T_323; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_323 = out_rivalid_1_177 & out_rimask_323; // @[RegisterRouter.scala:87:24] wire _out_T_3536 = out_f_rivalid_323; // @[RegisterRouter.scala:87:24] wire out_f_roready_323 = out_roready_1_177 & out_romask_323; // @[RegisterRouter.scala:87:24] wire _out_T_3537 = out_f_roready_323; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_323 = out_wivalid_1_177 & out_wimask_323; // @[RegisterRouter.scala:87:24] wire out_f_woready_323 = out_woready_1_177 & out_womask_323; // @[RegisterRouter.scala:87:24] wire _out_T_3538 = ~out_rimask_323; // @[RegisterRouter.scala:87:24] wire _out_T_3539 = ~out_wimask_323; // @[RegisterRouter.scala:87:24] wire _out_T_3540 = ~out_romask_323; // @[RegisterRouter.scala:87:24] wire _out_T_3541 = ~out_womask_323; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_266 = {hi_290, flags_0_go, _out_prepend_T_266}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3542 = out_prepend_266; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3543 = _out_T_3542; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_267 = _out_T_3543; // @[RegisterRouter.scala:87:24] wire out_rimask_324 = |_out_rimask_T_324; // @[RegisterRouter.scala:87:24] wire out_wimask_324 = &_out_wimask_T_324; // @[RegisterRouter.scala:87:24] wire out_romask_324 = |_out_romask_T_324; // @[RegisterRouter.scala:87:24] wire out_womask_324 = &_out_womask_T_324; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_324 = out_rivalid_1_178 & out_rimask_324; // @[RegisterRouter.scala:87:24] wire _out_T_3545 = out_f_rivalid_324; // @[RegisterRouter.scala:87:24] wire out_f_roready_324 = out_roready_1_178 & out_romask_324; // @[RegisterRouter.scala:87:24] wire _out_T_3546 = out_f_roready_324; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_324 = out_wivalid_1_178 & out_wimask_324; // @[RegisterRouter.scala:87:24] wire out_f_woready_324 = out_woready_1_178 & out_womask_324; // @[RegisterRouter.scala:87:24] wire _out_T_3547 = ~out_rimask_324; // @[RegisterRouter.scala:87:24] wire _out_T_3548 = ~out_wimask_324; // @[RegisterRouter.scala:87:24] wire _out_T_3549 = ~out_romask_324; // @[RegisterRouter.scala:87:24] wire _out_T_3550 = ~out_womask_324; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_267 = {hi_291, flags_0_go, _out_prepend_T_267}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3551 = out_prepend_267; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3552 = _out_T_3551; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_268 = _out_T_3552; // @[RegisterRouter.scala:87:24] wire out_rimask_325 = |_out_rimask_T_325; // @[RegisterRouter.scala:87:24] wire out_wimask_325 = &_out_wimask_T_325; // @[RegisterRouter.scala:87:24] wire out_romask_325 = |_out_romask_T_325; // @[RegisterRouter.scala:87:24] wire out_womask_325 = &_out_womask_T_325; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_325 = out_rivalid_1_179 & out_rimask_325; // @[RegisterRouter.scala:87:24] wire _out_T_3554 = out_f_rivalid_325; // @[RegisterRouter.scala:87:24] wire out_f_roready_325 = out_roready_1_179 & out_romask_325; // @[RegisterRouter.scala:87:24] wire _out_T_3555 = out_f_roready_325; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_325 = out_wivalid_1_179 & out_wimask_325; // @[RegisterRouter.scala:87:24] wire out_f_woready_325 = out_woready_1_179 & out_womask_325; // @[RegisterRouter.scala:87:24] wire _out_T_3556 = ~out_rimask_325; // @[RegisterRouter.scala:87:24] wire _out_T_3557 = ~out_wimask_325; // @[RegisterRouter.scala:87:24] wire _out_T_3558 = ~out_romask_325; // @[RegisterRouter.scala:87:24] wire _out_T_3559 = ~out_womask_325; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_268 = {hi_292, flags_0_go, _out_prepend_T_268}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3560 = out_prepend_268; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3561 = _out_T_3560; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_269 = _out_T_3561; // @[RegisterRouter.scala:87:24] wire out_rimask_326 = |_out_rimask_T_326; // @[RegisterRouter.scala:87:24] wire out_wimask_326 = &_out_wimask_T_326; // @[RegisterRouter.scala:87:24] wire out_romask_326 = |_out_romask_T_326; // @[RegisterRouter.scala:87:24] wire out_womask_326 = &_out_womask_T_326; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_326 = out_rivalid_1_180 & out_rimask_326; // @[RegisterRouter.scala:87:24] wire _out_T_3563 = out_f_rivalid_326; // @[RegisterRouter.scala:87:24] wire out_f_roready_326 = out_roready_1_180 & out_romask_326; // @[RegisterRouter.scala:87:24] wire _out_T_3564 = out_f_roready_326; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_326 = out_wivalid_1_180 & out_wimask_326; // @[RegisterRouter.scala:87:24] wire out_f_woready_326 = out_woready_1_180 & out_womask_326; // @[RegisterRouter.scala:87:24] wire _out_T_3565 = ~out_rimask_326; // @[RegisterRouter.scala:87:24] wire _out_T_3566 = ~out_wimask_326; // @[RegisterRouter.scala:87:24] wire _out_T_3567 = ~out_romask_326; // @[RegisterRouter.scala:87:24] wire _out_T_3568 = ~out_womask_326; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_269 = {hi_293, flags_0_go, _out_prepend_T_269}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3569 = out_prepend_269; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3570 = _out_T_3569; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_270 = _out_T_3570; // @[RegisterRouter.scala:87:24] wire out_rimask_327 = |_out_rimask_T_327; // @[RegisterRouter.scala:87:24] wire out_wimask_327 = &_out_wimask_T_327; // @[RegisterRouter.scala:87:24] wire out_romask_327 = |_out_romask_T_327; // @[RegisterRouter.scala:87:24] wire out_womask_327 = &_out_womask_T_327; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_327 = out_rivalid_1_181 & out_rimask_327; // @[RegisterRouter.scala:87:24] wire _out_T_3572 = out_f_rivalid_327; // @[RegisterRouter.scala:87:24] wire out_f_roready_327 = out_roready_1_181 & out_romask_327; // @[RegisterRouter.scala:87:24] wire _out_T_3573 = out_f_roready_327; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_327 = out_wivalid_1_181 & out_wimask_327; // @[RegisterRouter.scala:87:24] wire out_f_woready_327 = out_woready_1_181 & out_womask_327; // @[RegisterRouter.scala:87:24] wire _out_T_3574 = ~out_rimask_327; // @[RegisterRouter.scala:87:24] wire _out_T_3575 = ~out_wimask_327; // @[RegisterRouter.scala:87:24] wire _out_T_3576 = ~out_romask_327; // @[RegisterRouter.scala:87:24] wire _out_T_3577 = ~out_womask_327; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_270 = {hi_294, flags_0_go, _out_prepend_T_270}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3578 = out_prepend_270; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3579 = _out_T_3578; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_271 = _out_T_3579; // @[RegisterRouter.scala:87:24] wire out_rimask_328 = |_out_rimask_T_328; // @[RegisterRouter.scala:87:24] wire out_wimask_328 = &_out_wimask_T_328; // @[RegisterRouter.scala:87:24] wire out_romask_328 = |_out_romask_T_328; // @[RegisterRouter.scala:87:24] wire out_womask_328 = &_out_womask_T_328; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_328 = out_rivalid_1_182 & out_rimask_328; // @[RegisterRouter.scala:87:24] wire _out_T_3581 = out_f_rivalid_328; // @[RegisterRouter.scala:87:24] wire out_f_roready_328 = out_roready_1_182 & out_romask_328; // @[RegisterRouter.scala:87:24] wire _out_T_3582 = out_f_roready_328; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_328 = out_wivalid_1_182 & out_wimask_328; // @[RegisterRouter.scala:87:24] wire out_f_woready_328 = out_woready_1_182 & out_womask_328; // @[RegisterRouter.scala:87:24] wire _out_T_3583 = ~out_rimask_328; // @[RegisterRouter.scala:87:24] wire _out_T_3584 = ~out_wimask_328; // @[RegisterRouter.scala:87:24] wire _out_T_3585 = ~out_romask_328; // @[RegisterRouter.scala:87:24] wire _out_T_3586 = ~out_womask_328; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_271 = {hi_295, flags_0_go, _out_prepend_T_271}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3587 = out_prepend_271; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3588 = _out_T_3587; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_272 = _out_T_3588; // @[RegisterRouter.scala:87:24] wire out_rimask_329 = |_out_rimask_T_329; // @[RegisterRouter.scala:87:24] wire out_wimask_329 = &_out_wimask_T_329; // @[RegisterRouter.scala:87:24] wire out_romask_329 = |_out_romask_T_329; // @[RegisterRouter.scala:87:24] wire out_womask_329 = &_out_womask_T_329; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_329 = out_rivalid_1_183 & out_rimask_329; // @[RegisterRouter.scala:87:24] wire _out_T_3590 = out_f_rivalid_329; // @[RegisterRouter.scala:87:24] wire out_f_roready_329 = out_roready_1_183 & out_romask_329; // @[RegisterRouter.scala:87:24] wire _out_T_3591 = out_f_roready_329; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_329 = out_wivalid_1_183 & out_wimask_329; // @[RegisterRouter.scala:87:24] wire out_f_woready_329 = out_woready_1_183 & out_womask_329; // @[RegisterRouter.scala:87:24] wire _out_T_3592 = ~out_rimask_329; // @[RegisterRouter.scala:87:24] wire _out_T_3593 = ~out_wimask_329; // @[RegisterRouter.scala:87:24] wire _out_T_3594 = ~out_romask_329; // @[RegisterRouter.scala:87:24] wire _out_T_3595 = ~out_womask_329; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_272 = {hi_296, flags_0_go, _out_prepend_T_272}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3596 = out_prepend_272; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3597 = _out_T_3596; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_164 = _out_T_3597; // @[MuxLiteral.scala:49:48] wire out_rimask_330 = |_out_rimask_T_330; // @[RegisterRouter.scala:87:24] wire out_wimask_330 = &_out_wimask_T_330; // @[RegisterRouter.scala:87:24] wire out_romask_330 = |_out_romask_T_330; // @[RegisterRouter.scala:87:24] wire out_womask_330 = &_out_womask_T_330; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_330 = out_rivalid_1_184 & out_rimask_330; // @[RegisterRouter.scala:87:24] wire _out_T_3599 = out_f_rivalid_330; // @[RegisterRouter.scala:87:24] wire out_f_roready_330 = out_roready_1_184 & out_romask_330; // @[RegisterRouter.scala:87:24] wire _out_T_3600 = out_f_roready_330; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_330 = out_wivalid_1_184 & out_wimask_330; // @[RegisterRouter.scala:87:24] wire out_f_woready_330 = out_woready_1_184 & out_womask_330; // @[RegisterRouter.scala:87:24] wire _out_T_3601 = ~out_rimask_330; // @[RegisterRouter.scala:87:24] wire _out_T_3602 = ~out_wimask_330; // @[RegisterRouter.scala:87:24] wire _out_T_3603 = ~out_romask_330; // @[RegisterRouter.scala:87:24] wire _out_T_3604 = ~out_womask_330; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3606 = _out_T_3605; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_273 = _out_T_3606; // @[RegisterRouter.scala:87:24] wire out_rimask_331 = |_out_rimask_T_331; // @[RegisterRouter.scala:87:24] wire out_wimask_331 = &_out_wimask_T_331; // @[RegisterRouter.scala:87:24] wire out_romask_331 = |_out_romask_T_331; // @[RegisterRouter.scala:87:24] wire out_womask_331 = &_out_womask_T_331; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_331 = out_rivalid_1_185 & out_rimask_331; // @[RegisterRouter.scala:87:24] wire _out_T_3608 = out_f_rivalid_331; // @[RegisterRouter.scala:87:24] wire out_f_roready_331 = out_roready_1_185 & out_romask_331; // @[RegisterRouter.scala:87:24] wire _out_T_3609 = out_f_roready_331; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_331 = out_wivalid_1_185 & out_wimask_331; // @[RegisterRouter.scala:87:24] wire out_f_woready_331 = out_woready_1_185 & out_womask_331; // @[RegisterRouter.scala:87:24] wire _out_T_3610 = ~out_rimask_331; // @[RegisterRouter.scala:87:24] wire _out_T_3611 = ~out_wimask_331; // @[RegisterRouter.scala:87:24] wire _out_T_3612 = ~out_romask_331; // @[RegisterRouter.scala:87:24] wire _out_T_3613 = ~out_womask_331; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_273 = {hi_410, flags_0_go, _out_prepend_T_273}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3614 = out_prepend_273; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3615 = _out_T_3614; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_274 = _out_T_3615; // @[RegisterRouter.scala:87:24] wire out_rimask_332 = |_out_rimask_T_332; // @[RegisterRouter.scala:87:24] wire out_wimask_332 = &_out_wimask_T_332; // @[RegisterRouter.scala:87:24] wire out_romask_332 = |_out_romask_T_332; // @[RegisterRouter.scala:87:24] wire out_womask_332 = &_out_womask_T_332; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_332 = out_rivalid_1_186 & out_rimask_332; // @[RegisterRouter.scala:87:24] wire _out_T_3617 = out_f_rivalid_332; // @[RegisterRouter.scala:87:24] wire out_f_roready_332 = out_roready_1_186 & out_romask_332; // @[RegisterRouter.scala:87:24] wire _out_T_3618 = out_f_roready_332; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_332 = out_wivalid_1_186 & out_wimask_332; // @[RegisterRouter.scala:87:24] wire out_f_woready_332 = out_woready_1_186 & out_womask_332; // @[RegisterRouter.scala:87:24] wire _out_T_3619 = ~out_rimask_332; // @[RegisterRouter.scala:87:24] wire _out_T_3620 = ~out_wimask_332; // @[RegisterRouter.scala:87:24] wire _out_T_3621 = ~out_romask_332; // @[RegisterRouter.scala:87:24] wire _out_T_3622 = ~out_womask_332; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_274 = {hi_411, flags_0_go, _out_prepend_T_274}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3623 = out_prepend_274; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3624 = _out_T_3623; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_275 = _out_T_3624; // @[RegisterRouter.scala:87:24] wire out_rimask_333 = |_out_rimask_T_333; // @[RegisterRouter.scala:87:24] wire out_wimask_333 = &_out_wimask_T_333; // @[RegisterRouter.scala:87:24] wire out_romask_333 = |_out_romask_T_333; // @[RegisterRouter.scala:87:24] wire out_womask_333 = &_out_womask_T_333; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_333 = out_rivalid_1_187 & out_rimask_333; // @[RegisterRouter.scala:87:24] wire _out_T_3626 = out_f_rivalid_333; // @[RegisterRouter.scala:87:24] wire out_f_roready_333 = out_roready_1_187 & out_romask_333; // @[RegisterRouter.scala:87:24] wire _out_T_3627 = out_f_roready_333; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_333 = out_wivalid_1_187 & out_wimask_333; // @[RegisterRouter.scala:87:24] wire out_f_woready_333 = out_woready_1_187 & out_womask_333; // @[RegisterRouter.scala:87:24] wire _out_T_3628 = ~out_rimask_333; // @[RegisterRouter.scala:87:24] wire _out_T_3629 = ~out_wimask_333; // @[RegisterRouter.scala:87:24] wire _out_T_3630 = ~out_romask_333; // @[RegisterRouter.scala:87:24] wire _out_T_3631 = ~out_womask_333; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_275 = {hi_412, flags_0_go, _out_prepend_T_275}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3632 = out_prepend_275; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3633 = _out_T_3632; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_276 = _out_T_3633; // @[RegisterRouter.scala:87:24] wire out_rimask_334 = |_out_rimask_T_334; // @[RegisterRouter.scala:87:24] wire out_wimask_334 = &_out_wimask_T_334; // @[RegisterRouter.scala:87:24] wire out_romask_334 = |_out_romask_T_334; // @[RegisterRouter.scala:87:24] wire out_womask_334 = &_out_womask_T_334; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_334 = out_rivalid_1_188 & out_rimask_334; // @[RegisterRouter.scala:87:24] wire _out_T_3635 = out_f_rivalid_334; // @[RegisterRouter.scala:87:24] wire out_f_roready_334 = out_roready_1_188 & out_romask_334; // @[RegisterRouter.scala:87:24] wire _out_T_3636 = out_f_roready_334; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_334 = out_wivalid_1_188 & out_wimask_334; // @[RegisterRouter.scala:87:24] wire out_f_woready_334 = out_woready_1_188 & out_womask_334; // @[RegisterRouter.scala:87:24] wire _out_T_3637 = ~out_rimask_334; // @[RegisterRouter.scala:87:24] wire _out_T_3638 = ~out_wimask_334; // @[RegisterRouter.scala:87:24] wire _out_T_3639 = ~out_romask_334; // @[RegisterRouter.scala:87:24] wire _out_T_3640 = ~out_womask_334; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_276 = {hi_413, flags_0_go, _out_prepend_T_276}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3641 = out_prepend_276; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3642 = _out_T_3641; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_277 = _out_T_3642; // @[RegisterRouter.scala:87:24] wire out_rimask_335 = |_out_rimask_T_335; // @[RegisterRouter.scala:87:24] wire out_wimask_335 = &_out_wimask_T_335; // @[RegisterRouter.scala:87:24] wire out_romask_335 = |_out_romask_T_335; // @[RegisterRouter.scala:87:24] wire out_womask_335 = &_out_womask_T_335; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_335 = out_rivalid_1_189 & out_rimask_335; // @[RegisterRouter.scala:87:24] wire _out_T_3644 = out_f_rivalid_335; // @[RegisterRouter.scala:87:24] wire out_f_roready_335 = out_roready_1_189 & out_romask_335; // @[RegisterRouter.scala:87:24] wire _out_T_3645 = out_f_roready_335; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_335 = out_wivalid_1_189 & out_wimask_335; // @[RegisterRouter.scala:87:24] wire out_f_woready_335 = out_woready_1_189 & out_womask_335; // @[RegisterRouter.scala:87:24] wire _out_T_3646 = ~out_rimask_335; // @[RegisterRouter.scala:87:24] wire _out_T_3647 = ~out_wimask_335; // @[RegisterRouter.scala:87:24] wire _out_T_3648 = ~out_romask_335; // @[RegisterRouter.scala:87:24] wire _out_T_3649 = ~out_womask_335; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_277 = {hi_414, flags_0_go, _out_prepend_T_277}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3650 = out_prepend_277; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3651 = _out_T_3650; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_278 = _out_T_3651; // @[RegisterRouter.scala:87:24] wire out_rimask_336 = |_out_rimask_T_336; // @[RegisterRouter.scala:87:24] wire out_wimask_336 = &_out_wimask_T_336; // @[RegisterRouter.scala:87:24] wire out_romask_336 = |_out_romask_T_336; // @[RegisterRouter.scala:87:24] wire out_womask_336 = &_out_womask_T_336; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_336 = out_rivalid_1_190 & out_rimask_336; // @[RegisterRouter.scala:87:24] wire _out_T_3653 = out_f_rivalid_336; // @[RegisterRouter.scala:87:24] wire out_f_roready_336 = out_roready_1_190 & out_romask_336; // @[RegisterRouter.scala:87:24] wire _out_T_3654 = out_f_roready_336; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_336 = out_wivalid_1_190 & out_wimask_336; // @[RegisterRouter.scala:87:24] wire out_f_woready_336 = out_woready_1_190 & out_womask_336; // @[RegisterRouter.scala:87:24] wire _out_T_3655 = ~out_rimask_336; // @[RegisterRouter.scala:87:24] wire _out_T_3656 = ~out_wimask_336; // @[RegisterRouter.scala:87:24] wire _out_T_3657 = ~out_romask_336; // @[RegisterRouter.scala:87:24] wire _out_T_3658 = ~out_womask_336; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_278 = {hi_415, flags_0_go, _out_prepend_T_278}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3659 = out_prepend_278; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3660 = _out_T_3659; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_279 = _out_T_3660; // @[RegisterRouter.scala:87:24] wire out_rimask_337 = |_out_rimask_T_337; // @[RegisterRouter.scala:87:24] wire out_wimask_337 = &_out_wimask_T_337; // @[RegisterRouter.scala:87:24] wire out_romask_337 = |_out_romask_T_337; // @[RegisterRouter.scala:87:24] wire out_womask_337 = &_out_womask_T_337; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_337 = out_rivalid_1_191 & out_rimask_337; // @[RegisterRouter.scala:87:24] wire _out_T_3662 = out_f_rivalid_337; // @[RegisterRouter.scala:87:24] wire out_f_roready_337 = out_roready_1_191 & out_romask_337; // @[RegisterRouter.scala:87:24] wire _out_T_3663 = out_f_roready_337; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_337 = out_wivalid_1_191 & out_wimask_337; // @[RegisterRouter.scala:87:24] wire out_f_woready_337 = out_woready_1_191 & out_womask_337; // @[RegisterRouter.scala:87:24] wire _out_T_3664 = ~out_rimask_337; // @[RegisterRouter.scala:87:24] wire _out_T_3665 = ~out_wimask_337; // @[RegisterRouter.scala:87:24] wire _out_T_3666 = ~out_romask_337; // @[RegisterRouter.scala:87:24] wire _out_T_3667 = ~out_womask_337; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_279 = {hi_416, flags_0_go, _out_prepend_T_279}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3668 = out_prepend_279; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3669 = _out_T_3668; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_179 = _out_T_3669; // @[MuxLiteral.scala:49:48] wire out_rimask_338 = |_out_rimask_T_338; // @[RegisterRouter.scala:87:24] wire out_wimask_338 = &_out_wimask_T_338; // @[RegisterRouter.scala:87:24] wire out_romask_338 = |_out_romask_T_338; // @[RegisterRouter.scala:87:24] wire out_womask_338 = &_out_womask_T_338; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_338 = out_rivalid_1_192 & out_rimask_338; // @[RegisterRouter.scala:87:24] wire _out_T_3671 = out_f_rivalid_338; // @[RegisterRouter.scala:87:24] wire out_f_roready_338 = out_roready_1_192 & out_romask_338; // @[RegisterRouter.scala:87:24] wire _out_T_3672 = out_f_roready_338; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_338 = out_wivalid_1_192 & out_wimask_338; // @[RegisterRouter.scala:87:24] wire _out_T_3673 = out_f_wivalid_338; // @[RegisterRouter.scala:87:24] wire out_f_woready_338 = out_woready_1_192 & out_womask_338; // @[RegisterRouter.scala:87:24] wire _out_T_3674 = out_f_woready_338; // @[RegisterRouter.scala:87:24] wire _out_T_3675 = ~out_rimask_338; // @[RegisterRouter.scala:87:24] wire _out_T_3676 = ~out_wimask_338; // @[RegisterRouter.scala:87:24] wire _out_T_3677 = ~out_romask_338; // @[RegisterRouter.scala:87:24] wire _out_T_3678 = ~out_womask_338; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3680 = _out_T_3679; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_280 = _out_T_3680; // @[RegisterRouter.scala:87:24] wire out_rimask_339 = |_out_rimask_T_339; // @[RegisterRouter.scala:87:24] wire out_wimask_339 = &_out_wimask_T_339; // @[RegisterRouter.scala:87:24] wire out_romask_339 = |_out_romask_T_339; // @[RegisterRouter.scala:87:24] wire out_womask_339 = &_out_womask_T_339; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_339 = out_rivalid_1_193 & out_rimask_339; // @[RegisterRouter.scala:87:24] wire _out_T_3682 = out_f_rivalid_339; // @[RegisterRouter.scala:87:24] wire out_f_roready_339 = out_roready_1_193 & out_romask_339; // @[RegisterRouter.scala:87:24] wire _out_T_3683 = out_f_roready_339; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_339 = out_wivalid_1_193 & out_wimask_339; // @[RegisterRouter.scala:87:24] wire _out_T_3684 = out_f_wivalid_339; // @[RegisterRouter.scala:87:24] wire out_f_woready_339 = out_woready_1_193 & out_womask_339; // @[RegisterRouter.scala:87:24] wire _out_T_3685 = out_f_woready_339; // @[RegisterRouter.scala:87:24] wire _out_T_3686 = ~out_rimask_339; // @[RegisterRouter.scala:87:24] wire _out_T_3687 = ~out_wimask_339; // @[RegisterRouter.scala:87:24] wire _out_T_3688 = ~out_romask_339; // @[RegisterRouter.scala:87:24] wire _out_T_3689 = ~out_womask_339; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_280 = {programBufferMem_17, _out_prepend_T_280}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3690 = out_prepend_280; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3691 = _out_T_3690; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_281 = _out_T_3691; // @[RegisterRouter.scala:87:24] wire out_rimask_340 = |_out_rimask_T_340; // @[RegisterRouter.scala:87:24] wire out_wimask_340 = &_out_wimask_T_340; // @[RegisterRouter.scala:87:24] wire out_romask_340 = |_out_romask_T_340; // @[RegisterRouter.scala:87:24] wire out_womask_340 = &_out_womask_T_340; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_340 = out_rivalid_1_194 & out_rimask_340; // @[RegisterRouter.scala:87:24] wire _out_T_3693 = out_f_rivalid_340; // @[RegisterRouter.scala:87:24] wire out_f_roready_340 = out_roready_1_194 & out_romask_340; // @[RegisterRouter.scala:87:24] wire _out_T_3694 = out_f_roready_340; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_340 = out_wivalid_1_194 & out_wimask_340; // @[RegisterRouter.scala:87:24] wire _out_T_3695 = out_f_wivalid_340; // @[RegisterRouter.scala:87:24] wire out_f_woready_340 = out_woready_1_194 & out_womask_340; // @[RegisterRouter.scala:87:24] wire _out_T_3696 = out_f_woready_340; // @[RegisterRouter.scala:87:24] wire _out_T_3697 = ~out_rimask_340; // @[RegisterRouter.scala:87:24] wire _out_T_3698 = ~out_wimask_340; // @[RegisterRouter.scala:87:24] wire _out_T_3699 = ~out_romask_340; // @[RegisterRouter.scala:87:24] wire _out_T_3700 = ~out_womask_340; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_281 = {programBufferMem_18, _out_prepend_T_281}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3701 = out_prepend_281; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3702 = _out_T_3701; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_282 = _out_T_3702; // @[RegisterRouter.scala:87:24] wire out_rimask_341 = |_out_rimask_T_341; // @[RegisterRouter.scala:87:24] wire out_wimask_341 = &_out_wimask_T_341; // @[RegisterRouter.scala:87:24] wire out_romask_341 = |_out_romask_T_341; // @[RegisterRouter.scala:87:24] wire out_womask_341 = &_out_womask_T_341; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_341 = out_rivalid_1_195 & out_rimask_341; // @[RegisterRouter.scala:87:24] wire _out_T_3704 = out_f_rivalid_341; // @[RegisterRouter.scala:87:24] wire out_f_roready_341 = out_roready_1_195 & out_romask_341; // @[RegisterRouter.scala:87:24] wire _out_T_3705 = out_f_roready_341; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_341 = out_wivalid_1_195 & out_wimask_341; // @[RegisterRouter.scala:87:24] wire _out_T_3706 = out_f_wivalid_341; // @[RegisterRouter.scala:87:24] wire out_f_woready_341 = out_woready_1_195 & out_womask_341; // @[RegisterRouter.scala:87:24] wire _out_T_3707 = out_f_woready_341; // @[RegisterRouter.scala:87:24] wire _out_T_3708 = ~out_rimask_341; // @[RegisterRouter.scala:87:24] wire _out_T_3709 = ~out_wimask_341; // @[RegisterRouter.scala:87:24] wire _out_T_3710 = ~out_romask_341; // @[RegisterRouter.scala:87:24] wire _out_T_3711 = ~out_womask_341; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_282 = {programBufferMem_19, _out_prepend_T_282}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3712 = out_prepend_282; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3713 = _out_T_3712; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_283 = _out_T_3713; // @[RegisterRouter.scala:87:24] wire out_rimask_342 = |_out_rimask_T_342; // @[RegisterRouter.scala:87:24] wire out_wimask_342 = &_out_wimask_T_342; // @[RegisterRouter.scala:87:24] wire out_romask_342 = |_out_romask_T_342; // @[RegisterRouter.scala:87:24] wire out_womask_342 = &_out_womask_T_342; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_342 = out_rivalid_1_196 & out_rimask_342; // @[RegisterRouter.scala:87:24] wire _out_T_3715 = out_f_rivalid_342; // @[RegisterRouter.scala:87:24] wire out_f_roready_342 = out_roready_1_196 & out_romask_342; // @[RegisterRouter.scala:87:24] wire _out_T_3716 = out_f_roready_342; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_342 = out_wivalid_1_196 & out_wimask_342; // @[RegisterRouter.scala:87:24] wire _out_T_3717 = out_f_wivalid_342; // @[RegisterRouter.scala:87:24] wire out_f_woready_342 = out_woready_1_196 & out_womask_342; // @[RegisterRouter.scala:87:24] wire _out_T_3718 = out_f_woready_342; // @[RegisterRouter.scala:87:24] wire _out_T_3719 = ~out_rimask_342; // @[RegisterRouter.scala:87:24] wire _out_T_3720 = ~out_wimask_342; // @[RegisterRouter.scala:87:24] wire _out_T_3721 = ~out_romask_342; // @[RegisterRouter.scala:87:24] wire _out_T_3722 = ~out_womask_342; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_283 = {programBufferMem_20, _out_prepend_T_283}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3723 = out_prepend_283; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3724 = _out_T_3723; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_284 = _out_T_3724; // @[RegisterRouter.scala:87:24] wire out_rimask_343 = |_out_rimask_T_343; // @[RegisterRouter.scala:87:24] wire out_wimask_343 = &_out_wimask_T_343; // @[RegisterRouter.scala:87:24] wire out_romask_343 = |_out_romask_T_343; // @[RegisterRouter.scala:87:24] wire out_womask_343 = &_out_womask_T_343; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_343 = out_rivalid_1_197 & out_rimask_343; // @[RegisterRouter.scala:87:24] wire _out_T_3726 = out_f_rivalid_343; // @[RegisterRouter.scala:87:24] wire out_f_roready_343 = out_roready_1_197 & out_romask_343; // @[RegisterRouter.scala:87:24] wire _out_T_3727 = out_f_roready_343; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_343 = out_wivalid_1_197 & out_wimask_343; // @[RegisterRouter.scala:87:24] wire _out_T_3728 = out_f_wivalid_343; // @[RegisterRouter.scala:87:24] wire out_f_woready_343 = out_woready_1_197 & out_womask_343; // @[RegisterRouter.scala:87:24] wire _out_T_3729 = out_f_woready_343; // @[RegisterRouter.scala:87:24] wire _out_T_3730 = ~out_rimask_343; // @[RegisterRouter.scala:87:24] wire _out_T_3731 = ~out_wimask_343; // @[RegisterRouter.scala:87:24] wire _out_T_3732 = ~out_romask_343; // @[RegisterRouter.scala:87:24] wire _out_T_3733 = ~out_womask_343; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_284 = {programBufferMem_21, _out_prepend_T_284}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3734 = out_prepend_284; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3735 = _out_T_3734; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_285 = _out_T_3735; // @[RegisterRouter.scala:87:24] wire out_rimask_344 = |_out_rimask_T_344; // @[RegisterRouter.scala:87:24] wire out_wimask_344 = &_out_wimask_T_344; // @[RegisterRouter.scala:87:24] wire out_romask_344 = |_out_romask_T_344; // @[RegisterRouter.scala:87:24] wire out_womask_344 = &_out_womask_T_344; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_344 = out_rivalid_1_198 & out_rimask_344; // @[RegisterRouter.scala:87:24] wire _out_T_3737 = out_f_rivalid_344; // @[RegisterRouter.scala:87:24] wire out_f_roready_344 = out_roready_1_198 & out_romask_344; // @[RegisterRouter.scala:87:24] wire _out_T_3738 = out_f_roready_344; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_344 = out_wivalid_1_198 & out_wimask_344; // @[RegisterRouter.scala:87:24] wire _out_T_3739 = out_f_wivalid_344; // @[RegisterRouter.scala:87:24] wire out_f_woready_344 = out_woready_1_198 & out_womask_344; // @[RegisterRouter.scala:87:24] wire _out_T_3740 = out_f_woready_344; // @[RegisterRouter.scala:87:24] wire _out_T_3741 = ~out_rimask_344; // @[RegisterRouter.scala:87:24] wire _out_T_3742 = ~out_wimask_344; // @[RegisterRouter.scala:87:24] wire _out_T_3743 = ~out_romask_344; // @[RegisterRouter.scala:87:24] wire _out_T_3744 = ~out_womask_344; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_285 = {programBufferMem_22, _out_prepend_T_285}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3745 = out_prepend_285; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3746 = _out_T_3745; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_286 = _out_T_3746; // @[RegisterRouter.scala:87:24] wire out_rimask_345 = |_out_rimask_T_345; // @[RegisterRouter.scala:87:24] wire out_wimask_345 = &_out_wimask_T_345; // @[RegisterRouter.scala:87:24] wire out_romask_345 = |_out_romask_T_345; // @[RegisterRouter.scala:87:24] wire out_womask_345 = &_out_womask_T_345; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_345 = out_rivalid_1_199 & out_rimask_345; // @[RegisterRouter.scala:87:24] wire _out_T_3748 = out_f_rivalid_345; // @[RegisterRouter.scala:87:24] wire out_f_roready_345 = out_roready_1_199 & out_romask_345; // @[RegisterRouter.scala:87:24] wire _out_T_3749 = out_f_roready_345; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_345 = out_wivalid_1_199 & out_wimask_345; // @[RegisterRouter.scala:87:24] wire _out_T_3750 = out_f_wivalid_345; // @[RegisterRouter.scala:87:24] wire out_f_woready_345 = out_woready_1_199 & out_womask_345; // @[RegisterRouter.scala:87:24] wire _out_T_3751 = out_f_woready_345; // @[RegisterRouter.scala:87:24] wire _out_T_3752 = ~out_rimask_345; // @[RegisterRouter.scala:87:24] wire _out_T_3753 = ~out_wimask_345; // @[RegisterRouter.scala:87:24] wire _out_T_3754 = ~out_romask_345; // @[RegisterRouter.scala:87:24] wire _out_T_3755 = ~out_womask_345; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_286 = {programBufferMem_23, _out_prepend_T_286}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3756 = out_prepend_286; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3757 = _out_T_3756; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_106 = _out_T_3757; // @[MuxLiteral.scala:49:48] wire out_rimask_346 = |_out_rimask_T_346; // @[RegisterRouter.scala:87:24] wire out_wimask_346 = &_out_wimask_T_346; // @[RegisterRouter.scala:87:24] wire out_romask_346 = |_out_romask_T_346; // @[RegisterRouter.scala:87:24] wire out_womask_346 = &_out_womask_T_346; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_346 = out_rivalid_1_200 & out_rimask_346; // @[RegisterRouter.scala:87:24] wire _out_T_3759 = out_f_rivalid_346; // @[RegisterRouter.scala:87:24] wire out_f_roready_346 = out_roready_1_200 & out_romask_346; // @[RegisterRouter.scala:87:24] wire _out_T_3760 = out_f_roready_346; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_346 = out_wivalid_1_200 & out_wimask_346; // @[RegisterRouter.scala:87:24] wire out_f_woready_346 = out_woready_1_200 & out_womask_346; // @[RegisterRouter.scala:87:24] wire _out_T_3761 = ~out_rimask_346; // @[RegisterRouter.scala:87:24] wire _out_T_3762 = ~out_wimask_346; // @[RegisterRouter.scala:87:24] wire _out_T_3763 = ~out_romask_346; // @[RegisterRouter.scala:87:24] wire _out_T_3764 = ~out_womask_346; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3766 = _out_T_3765; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_287 = _out_T_3766; // @[RegisterRouter.scala:87:24] wire out_rimask_347 = |_out_rimask_T_347; // @[RegisterRouter.scala:87:24] wire out_wimask_347 = &_out_wimask_T_347; // @[RegisterRouter.scala:87:24] wire out_romask_347 = |_out_romask_T_347; // @[RegisterRouter.scala:87:24] wire out_womask_347 = &_out_womask_T_347; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_347 = out_rivalid_1_201 & out_rimask_347; // @[RegisterRouter.scala:87:24] wire _out_T_3768 = out_f_rivalid_347; // @[RegisterRouter.scala:87:24] wire out_f_roready_347 = out_roready_1_201 & out_romask_347; // @[RegisterRouter.scala:87:24] wire _out_T_3769 = out_f_roready_347; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_347 = out_wivalid_1_201 & out_wimask_347; // @[RegisterRouter.scala:87:24] wire out_f_woready_347 = out_woready_1_201 & out_womask_347; // @[RegisterRouter.scala:87:24] wire _out_T_3770 = ~out_rimask_347; // @[RegisterRouter.scala:87:24] wire _out_T_3771 = ~out_wimask_347; // @[RegisterRouter.scala:87:24] wire _out_T_3772 = ~out_romask_347; // @[RegisterRouter.scala:87:24] wire _out_T_3773 = ~out_womask_347; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_287 = {hi_882, flags_0_go, _out_prepend_T_287}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3774 = out_prepend_287; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3775 = _out_T_3774; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_288 = _out_T_3775; // @[RegisterRouter.scala:87:24] wire out_rimask_348 = |_out_rimask_T_348; // @[RegisterRouter.scala:87:24] wire out_wimask_348 = &_out_wimask_T_348; // @[RegisterRouter.scala:87:24] wire out_romask_348 = |_out_romask_T_348; // @[RegisterRouter.scala:87:24] wire out_womask_348 = &_out_womask_T_348; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_348 = out_rivalid_1_202 & out_rimask_348; // @[RegisterRouter.scala:87:24] wire _out_T_3777 = out_f_rivalid_348; // @[RegisterRouter.scala:87:24] wire out_f_roready_348 = out_roready_1_202 & out_romask_348; // @[RegisterRouter.scala:87:24] wire _out_T_3778 = out_f_roready_348; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_348 = out_wivalid_1_202 & out_wimask_348; // @[RegisterRouter.scala:87:24] wire out_f_woready_348 = out_woready_1_202 & out_womask_348; // @[RegisterRouter.scala:87:24] wire _out_T_3779 = ~out_rimask_348; // @[RegisterRouter.scala:87:24] wire _out_T_3780 = ~out_wimask_348; // @[RegisterRouter.scala:87:24] wire _out_T_3781 = ~out_romask_348; // @[RegisterRouter.scala:87:24] wire _out_T_3782 = ~out_womask_348; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_288 = {hi_883, flags_0_go, _out_prepend_T_288}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3783 = out_prepend_288; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3784 = _out_T_3783; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_289 = _out_T_3784; // @[RegisterRouter.scala:87:24] wire out_rimask_349 = |_out_rimask_T_349; // @[RegisterRouter.scala:87:24] wire out_wimask_349 = &_out_wimask_T_349; // @[RegisterRouter.scala:87:24] wire out_romask_349 = |_out_romask_T_349; // @[RegisterRouter.scala:87:24] wire out_womask_349 = &_out_womask_T_349; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_349 = out_rivalid_1_203 & out_rimask_349; // @[RegisterRouter.scala:87:24] wire _out_T_3786 = out_f_rivalid_349; // @[RegisterRouter.scala:87:24] wire out_f_roready_349 = out_roready_1_203 & out_romask_349; // @[RegisterRouter.scala:87:24] wire _out_T_3787 = out_f_roready_349; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_349 = out_wivalid_1_203 & out_wimask_349; // @[RegisterRouter.scala:87:24] wire out_f_woready_349 = out_woready_1_203 & out_womask_349; // @[RegisterRouter.scala:87:24] wire _out_T_3788 = ~out_rimask_349; // @[RegisterRouter.scala:87:24] wire _out_T_3789 = ~out_wimask_349; // @[RegisterRouter.scala:87:24] wire _out_T_3790 = ~out_romask_349; // @[RegisterRouter.scala:87:24] wire _out_T_3791 = ~out_womask_349; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_289 = {hi_884, flags_0_go, _out_prepend_T_289}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3792 = out_prepend_289; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3793 = _out_T_3792; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_290 = _out_T_3793; // @[RegisterRouter.scala:87:24] wire out_rimask_350 = |_out_rimask_T_350; // @[RegisterRouter.scala:87:24] wire out_wimask_350 = &_out_wimask_T_350; // @[RegisterRouter.scala:87:24] wire out_romask_350 = |_out_romask_T_350; // @[RegisterRouter.scala:87:24] wire out_womask_350 = &_out_womask_T_350; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_350 = out_rivalid_1_204 & out_rimask_350; // @[RegisterRouter.scala:87:24] wire _out_T_3795 = out_f_rivalid_350; // @[RegisterRouter.scala:87:24] wire out_f_roready_350 = out_roready_1_204 & out_romask_350; // @[RegisterRouter.scala:87:24] wire _out_T_3796 = out_f_roready_350; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_350 = out_wivalid_1_204 & out_wimask_350; // @[RegisterRouter.scala:87:24] wire out_f_woready_350 = out_woready_1_204 & out_womask_350; // @[RegisterRouter.scala:87:24] wire _out_T_3797 = ~out_rimask_350; // @[RegisterRouter.scala:87:24] wire _out_T_3798 = ~out_wimask_350; // @[RegisterRouter.scala:87:24] wire _out_T_3799 = ~out_romask_350; // @[RegisterRouter.scala:87:24] wire _out_T_3800 = ~out_womask_350; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_290 = {hi_885, flags_0_go, _out_prepend_T_290}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3801 = out_prepend_290; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3802 = _out_T_3801; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_291 = _out_T_3802; // @[RegisterRouter.scala:87:24] wire out_rimask_351 = |_out_rimask_T_351; // @[RegisterRouter.scala:87:24] wire out_wimask_351 = &_out_wimask_T_351; // @[RegisterRouter.scala:87:24] wire out_romask_351 = |_out_romask_T_351; // @[RegisterRouter.scala:87:24] wire out_womask_351 = &_out_womask_T_351; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_351 = out_rivalid_1_205 & out_rimask_351; // @[RegisterRouter.scala:87:24] wire _out_T_3804 = out_f_rivalid_351; // @[RegisterRouter.scala:87:24] wire out_f_roready_351 = out_roready_1_205 & out_romask_351; // @[RegisterRouter.scala:87:24] wire _out_T_3805 = out_f_roready_351; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_351 = out_wivalid_1_205 & out_wimask_351; // @[RegisterRouter.scala:87:24] wire out_f_woready_351 = out_woready_1_205 & out_womask_351; // @[RegisterRouter.scala:87:24] wire _out_T_3806 = ~out_rimask_351; // @[RegisterRouter.scala:87:24] wire _out_T_3807 = ~out_wimask_351; // @[RegisterRouter.scala:87:24] wire _out_T_3808 = ~out_romask_351; // @[RegisterRouter.scala:87:24] wire _out_T_3809 = ~out_womask_351; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_291 = {hi_886, flags_0_go, _out_prepend_T_291}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3810 = out_prepend_291; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3811 = _out_T_3810; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_292 = _out_T_3811; // @[RegisterRouter.scala:87:24] wire out_rimask_352 = |_out_rimask_T_352; // @[RegisterRouter.scala:87:24] wire out_wimask_352 = &_out_wimask_T_352; // @[RegisterRouter.scala:87:24] wire out_romask_352 = |_out_romask_T_352; // @[RegisterRouter.scala:87:24] wire out_womask_352 = &_out_womask_T_352; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_352 = out_rivalid_1_206 & out_rimask_352; // @[RegisterRouter.scala:87:24] wire _out_T_3813 = out_f_rivalid_352; // @[RegisterRouter.scala:87:24] wire out_f_roready_352 = out_roready_1_206 & out_romask_352; // @[RegisterRouter.scala:87:24] wire _out_T_3814 = out_f_roready_352; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_352 = out_wivalid_1_206 & out_wimask_352; // @[RegisterRouter.scala:87:24] wire out_f_woready_352 = out_woready_1_206 & out_womask_352; // @[RegisterRouter.scala:87:24] wire _out_T_3815 = ~out_rimask_352; // @[RegisterRouter.scala:87:24] wire _out_T_3816 = ~out_wimask_352; // @[RegisterRouter.scala:87:24] wire _out_T_3817 = ~out_romask_352; // @[RegisterRouter.scala:87:24] wire _out_T_3818 = ~out_womask_352; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_292 = {hi_887, flags_0_go, _out_prepend_T_292}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3819 = out_prepend_292; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3820 = _out_T_3819; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_293 = _out_T_3820; // @[RegisterRouter.scala:87:24] wire out_rimask_353 = |_out_rimask_T_353; // @[RegisterRouter.scala:87:24] wire out_wimask_353 = &_out_wimask_T_353; // @[RegisterRouter.scala:87:24] wire out_romask_353 = |_out_romask_T_353; // @[RegisterRouter.scala:87:24] wire out_womask_353 = &_out_womask_T_353; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_353 = out_rivalid_1_207 & out_rimask_353; // @[RegisterRouter.scala:87:24] wire _out_T_3822 = out_f_rivalid_353; // @[RegisterRouter.scala:87:24] wire out_f_roready_353 = out_roready_1_207 & out_romask_353; // @[RegisterRouter.scala:87:24] wire _out_T_3823 = out_f_roready_353; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_353 = out_wivalid_1_207 & out_wimask_353; // @[RegisterRouter.scala:87:24] wire out_f_woready_353 = out_woready_1_207 & out_womask_353; // @[RegisterRouter.scala:87:24] wire _out_T_3824 = ~out_rimask_353; // @[RegisterRouter.scala:87:24] wire _out_T_3825 = ~out_wimask_353; // @[RegisterRouter.scala:87:24] wire _out_T_3826 = ~out_romask_353; // @[RegisterRouter.scala:87:24] wire _out_T_3827 = ~out_womask_353; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_293 = {hi_888, flags_0_go, _out_prepend_T_293}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3828 = out_prepend_293; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3829 = _out_T_3828; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_238 = _out_T_3829; // @[MuxLiteral.scala:49:48] wire out_rimask_354 = |_out_rimask_T_354; // @[RegisterRouter.scala:87:24] wire out_wimask_354 = &_out_wimask_T_354; // @[RegisterRouter.scala:87:24] wire out_romask_354 = |_out_romask_T_354; // @[RegisterRouter.scala:87:24] wire out_womask_354 = &_out_womask_T_354; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_354 = out_rivalid_1_208 & out_rimask_354; // @[RegisterRouter.scala:87:24] wire _out_T_3831 = out_f_rivalid_354; // @[RegisterRouter.scala:87:24] wire out_f_roready_354 = out_roready_1_208 & out_romask_354; // @[RegisterRouter.scala:87:24] wire _out_T_3832 = out_f_roready_354; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_354 = out_wivalid_1_208 & out_wimask_354; // @[RegisterRouter.scala:87:24] wire out_f_woready_354 = out_woready_1_208 & out_womask_354; // @[RegisterRouter.scala:87:24] wire _out_T_3833 = ~out_rimask_354; // @[RegisterRouter.scala:87:24] wire _out_T_3834 = ~out_wimask_354; // @[RegisterRouter.scala:87:24] wire _out_T_3835 = ~out_romask_354; // @[RegisterRouter.scala:87:24] wire _out_T_3836 = ~out_womask_354; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3838 = _out_T_3837; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_294 = _out_T_3838; // @[RegisterRouter.scala:87:24] wire out_rimask_355 = |_out_rimask_T_355; // @[RegisterRouter.scala:87:24] wire out_wimask_355 = &_out_wimask_T_355; // @[RegisterRouter.scala:87:24] wire out_romask_355 = |_out_romask_T_355; // @[RegisterRouter.scala:87:24] wire out_womask_355 = &_out_womask_T_355; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_355 = out_rivalid_1_209 & out_rimask_355; // @[RegisterRouter.scala:87:24] wire _out_T_3840 = out_f_rivalid_355; // @[RegisterRouter.scala:87:24] wire out_f_roready_355 = out_roready_1_209 & out_romask_355; // @[RegisterRouter.scala:87:24] wire _out_T_3841 = out_f_roready_355; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_355 = out_wivalid_1_209 & out_wimask_355; // @[RegisterRouter.scala:87:24] wire out_f_woready_355 = out_woready_1_209 & out_womask_355; // @[RegisterRouter.scala:87:24] wire _out_T_3842 = ~out_rimask_355; // @[RegisterRouter.scala:87:24] wire _out_T_3843 = ~out_wimask_355; // @[RegisterRouter.scala:87:24] wire _out_T_3844 = ~out_romask_355; // @[RegisterRouter.scala:87:24] wire _out_T_3845 = ~out_womask_355; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_294 = {hi_666, flags_0_go, _out_prepend_T_294}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3846 = out_prepend_294; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3847 = _out_T_3846; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_295 = _out_T_3847; // @[RegisterRouter.scala:87:24] wire out_rimask_356 = |_out_rimask_T_356; // @[RegisterRouter.scala:87:24] wire out_wimask_356 = &_out_wimask_T_356; // @[RegisterRouter.scala:87:24] wire out_romask_356 = |_out_romask_T_356; // @[RegisterRouter.scala:87:24] wire out_womask_356 = &_out_womask_T_356; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_356 = out_rivalid_1_210 & out_rimask_356; // @[RegisterRouter.scala:87:24] wire _out_T_3849 = out_f_rivalid_356; // @[RegisterRouter.scala:87:24] wire out_f_roready_356 = out_roready_1_210 & out_romask_356; // @[RegisterRouter.scala:87:24] wire _out_T_3850 = out_f_roready_356; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_356 = out_wivalid_1_210 & out_wimask_356; // @[RegisterRouter.scala:87:24] wire out_f_woready_356 = out_woready_1_210 & out_womask_356; // @[RegisterRouter.scala:87:24] wire _out_T_3851 = ~out_rimask_356; // @[RegisterRouter.scala:87:24] wire _out_T_3852 = ~out_wimask_356; // @[RegisterRouter.scala:87:24] wire _out_T_3853 = ~out_romask_356; // @[RegisterRouter.scala:87:24] wire _out_T_3854 = ~out_womask_356; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_295 = {hi_667, flags_0_go, _out_prepend_T_295}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3855 = out_prepend_295; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3856 = _out_T_3855; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_296 = _out_T_3856; // @[RegisterRouter.scala:87:24] wire out_rimask_357 = |_out_rimask_T_357; // @[RegisterRouter.scala:87:24] wire out_wimask_357 = &_out_wimask_T_357; // @[RegisterRouter.scala:87:24] wire out_romask_357 = |_out_romask_T_357; // @[RegisterRouter.scala:87:24] wire out_womask_357 = &_out_womask_T_357; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_357 = out_rivalid_1_211 & out_rimask_357; // @[RegisterRouter.scala:87:24] wire _out_T_3858 = out_f_rivalid_357; // @[RegisterRouter.scala:87:24] wire out_f_roready_357 = out_roready_1_211 & out_romask_357; // @[RegisterRouter.scala:87:24] wire _out_T_3859 = out_f_roready_357; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_357 = out_wivalid_1_211 & out_wimask_357; // @[RegisterRouter.scala:87:24] wire out_f_woready_357 = out_woready_1_211 & out_womask_357; // @[RegisterRouter.scala:87:24] wire _out_T_3860 = ~out_rimask_357; // @[RegisterRouter.scala:87:24] wire _out_T_3861 = ~out_wimask_357; // @[RegisterRouter.scala:87:24] wire _out_T_3862 = ~out_romask_357; // @[RegisterRouter.scala:87:24] wire _out_T_3863 = ~out_womask_357; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_296 = {hi_668, flags_0_go, _out_prepend_T_296}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3864 = out_prepend_296; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3865 = _out_T_3864; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_297 = _out_T_3865; // @[RegisterRouter.scala:87:24] wire out_rimask_358 = |_out_rimask_T_358; // @[RegisterRouter.scala:87:24] wire out_wimask_358 = &_out_wimask_T_358; // @[RegisterRouter.scala:87:24] wire out_romask_358 = |_out_romask_T_358; // @[RegisterRouter.scala:87:24] wire out_womask_358 = &_out_womask_T_358; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_358 = out_rivalid_1_212 & out_rimask_358; // @[RegisterRouter.scala:87:24] wire _out_T_3867 = out_f_rivalid_358; // @[RegisterRouter.scala:87:24] wire out_f_roready_358 = out_roready_1_212 & out_romask_358; // @[RegisterRouter.scala:87:24] wire _out_T_3868 = out_f_roready_358; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_358 = out_wivalid_1_212 & out_wimask_358; // @[RegisterRouter.scala:87:24] wire out_f_woready_358 = out_woready_1_212 & out_womask_358; // @[RegisterRouter.scala:87:24] wire _out_T_3869 = ~out_rimask_358; // @[RegisterRouter.scala:87:24] wire _out_T_3870 = ~out_wimask_358; // @[RegisterRouter.scala:87:24] wire _out_T_3871 = ~out_romask_358; // @[RegisterRouter.scala:87:24] wire _out_T_3872 = ~out_womask_358; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_297 = {hi_669, flags_0_go, _out_prepend_T_297}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3873 = out_prepend_297; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3874 = _out_T_3873; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_298 = _out_T_3874; // @[RegisterRouter.scala:87:24] wire out_rimask_359 = |_out_rimask_T_359; // @[RegisterRouter.scala:87:24] wire out_wimask_359 = &_out_wimask_T_359; // @[RegisterRouter.scala:87:24] wire out_romask_359 = |_out_romask_T_359; // @[RegisterRouter.scala:87:24] wire out_womask_359 = &_out_womask_T_359; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_359 = out_rivalid_1_213 & out_rimask_359; // @[RegisterRouter.scala:87:24] wire _out_T_3876 = out_f_rivalid_359; // @[RegisterRouter.scala:87:24] wire out_f_roready_359 = out_roready_1_213 & out_romask_359; // @[RegisterRouter.scala:87:24] wire _out_T_3877 = out_f_roready_359; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_359 = out_wivalid_1_213 & out_wimask_359; // @[RegisterRouter.scala:87:24] wire out_f_woready_359 = out_woready_1_213 & out_womask_359; // @[RegisterRouter.scala:87:24] wire _out_T_3878 = ~out_rimask_359; // @[RegisterRouter.scala:87:24] wire _out_T_3879 = ~out_wimask_359; // @[RegisterRouter.scala:87:24] wire _out_T_3880 = ~out_romask_359; // @[RegisterRouter.scala:87:24] wire _out_T_3881 = ~out_womask_359; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_298 = {hi_670, flags_0_go, _out_prepend_T_298}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3882 = out_prepend_298; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3883 = _out_T_3882; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_299 = _out_T_3883; // @[RegisterRouter.scala:87:24] wire out_rimask_360 = |_out_rimask_T_360; // @[RegisterRouter.scala:87:24] wire out_wimask_360 = &_out_wimask_T_360; // @[RegisterRouter.scala:87:24] wire out_romask_360 = |_out_romask_T_360; // @[RegisterRouter.scala:87:24] wire out_womask_360 = &_out_womask_T_360; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_360 = out_rivalid_1_214 & out_rimask_360; // @[RegisterRouter.scala:87:24] wire _out_T_3885 = out_f_rivalid_360; // @[RegisterRouter.scala:87:24] wire out_f_roready_360 = out_roready_1_214 & out_romask_360; // @[RegisterRouter.scala:87:24] wire _out_T_3886 = out_f_roready_360; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_360 = out_wivalid_1_214 & out_wimask_360; // @[RegisterRouter.scala:87:24] wire out_f_woready_360 = out_woready_1_214 & out_womask_360; // @[RegisterRouter.scala:87:24] wire _out_T_3887 = ~out_rimask_360; // @[RegisterRouter.scala:87:24] wire _out_T_3888 = ~out_wimask_360; // @[RegisterRouter.scala:87:24] wire _out_T_3889 = ~out_romask_360; // @[RegisterRouter.scala:87:24] wire _out_T_3890 = ~out_womask_360; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_299 = {hi_671, flags_0_go, _out_prepend_T_299}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3891 = out_prepend_299; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3892 = _out_T_3891; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_300 = _out_T_3892; // @[RegisterRouter.scala:87:24] wire out_rimask_361 = |_out_rimask_T_361; // @[RegisterRouter.scala:87:24] wire out_wimask_361 = &_out_wimask_T_361; // @[RegisterRouter.scala:87:24] wire out_romask_361 = |_out_romask_T_361; // @[RegisterRouter.scala:87:24] wire out_womask_361 = &_out_womask_T_361; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_361 = out_rivalid_1_215 & out_rimask_361; // @[RegisterRouter.scala:87:24] wire _out_T_3894 = out_f_rivalid_361; // @[RegisterRouter.scala:87:24] wire out_f_roready_361 = out_roready_1_215 & out_romask_361; // @[RegisterRouter.scala:87:24] wire _out_T_3895 = out_f_roready_361; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_361 = out_wivalid_1_215 & out_wimask_361; // @[RegisterRouter.scala:87:24] wire out_f_woready_361 = out_woready_1_215 & out_womask_361; // @[RegisterRouter.scala:87:24] wire _out_T_3896 = ~out_rimask_361; // @[RegisterRouter.scala:87:24] wire _out_T_3897 = ~out_wimask_361; // @[RegisterRouter.scala:87:24] wire _out_T_3898 = ~out_romask_361; // @[RegisterRouter.scala:87:24] wire _out_T_3899 = ~out_womask_361; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_300 = {hi_672, flags_0_go, _out_prepend_T_300}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3900 = out_prepend_300; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3901 = _out_T_3900; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_211 = _out_T_3901; // @[MuxLiteral.scala:49:48] wire out_rimask_362 = |_out_rimask_T_362; // @[RegisterRouter.scala:87:24] wire out_wimask_362 = &_out_wimask_T_362; // @[RegisterRouter.scala:87:24] wire out_romask_362 = |_out_romask_T_362; // @[RegisterRouter.scala:87:24] wire out_womask_362 = &_out_womask_T_362; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_362 = out_rivalid_1_216 & out_rimask_362; // @[RegisterRouter.scala:87:24] wire _out_T_3903 = out_f_rivalid_362; // @[RegisterRouter.scala:87:24] wire out_f_roready_362 = out_roready_1_216 & out_romask_362; // @[RegisterRouter.scala:87:24] wire _out_T_3904 = out_f_roready_362; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_362 = out_wivalid_1_216 & out_wimask_362; // @[RegisterRouter.scala:87:24] wire out_f_woready_362 = out_woready_1_216 & out_womask_362; // @[RegisterRouter.scala:87:24] wire _out_T_3905 = ~out_rimask_362; // @[RegisterRouter.scala:87:24] wire _out_T_3906 = ~out_wimask_362; // @[RegisterRouter.scala:87:24] wire _out_T_3907 = ~out_romask_362; // @[RegisterRouter.scala:87:24] wire _out_T_3908 = ~out_womask_362; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3910 = _out_T_3909; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_301 = _out_T_3910; // @[RegisterRouter.scala:87:24] wire out_rimask_363 = |_out_rimask_T_363; // @[RegisterRouter.scala:87:24] wire out_wimask_363 = &_out_wimask_T_363; // @[RegisterRouter.scala:87:24] wire out_romask_363 = |_out_romask_T_363; // @[RegisterRouter.scala:87:24] wire out_womask_363 = &_out_womask_T_363; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_363 = out_rivalid_1_217 & out_rimask_363; // @[RegisterRouter.scala:87:24] wire _out_T_3912 = out_f_rivalid_363; // @[RegisterRouter.scala:87:24] wire out_f_roready_363 = out_roready_1_217 & out_romask_363; // @[RegisterRouter.scala:87:24] wire _out_T_3913 = out_f_roready_363; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_363 = out_wivalid_1_217 & out_wimask_363; // @[RegisterRouter.scala:87:24] wire out_f_woready_363 = out_woready_1_217 & out_womask_363; // @[RegisterRouter.scala:87:24] wire _out_T_3914 = ~out_rimask_363; // @[RegisterRouter.scala:87:24] wire _out_T_3915 = ~out_wimask_363; // @[RegisterRouter.scala:87:24] wire _out_T_3916 = ~out_romask_363; // @[RegisterRouter.scala:87:24] wire _out_T_3917 = ~out_womask_363; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_301 = {hi_1002, flags_0_go, _out_prepend_T_301}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3918 = out_prepend_301; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3919 = _out_T_3918; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_302 = _out_T_3919; // @[RegisterRouter.scala:87:24] wire out_rimask_364 = |_out_rimask_T_364; // @[RegisterRouter.scala:87:24] wire out_wimask_364 = &_out_wimask_T_364; // @[RegisterRouter.scala:87:24] wire out_romask_364 = |_out_romask_T_364; // @[RegisterRouter.scala:87:24] wire out_womask_364 = &_out_womask_T_364; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_364 = out_rivalid_1_218 & out_rimask_364; // @[RegisterRouter.scala:87:24] wire _out_T_3921 = out_f_rivalid_364; // @[RegisterRouter.scala:87:24] wire out_f_roready_364 = out_roready_1_218 & out_romask_364; // @[RegisterRouter.scala:87:24] wire _out_T_3922 = out_f_roready_364; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_364 = out_wivalid_1_218 & out_wimask_364; // @[RegisterRouter.scala:87:24] wire out_f_woready_364 = out_woready_1_218 & out_womask_364; // @[RegisterRouter.scala:87:24] wire _out_T_3923 = ~out_rimask_364; // @[RegisterRouter.scala:87:24] wire _out_T_3924 = ~out_wimask_364; // @[RegisterRouter.scala:87:24] wire _out_T_3925 = ~out_romask_364; // @[RegisterRouter.scala:87:24] wire _out_T_3926 = ~out_womask_364; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_302 = {hi_1003, flags_0_go, _out_prepend_T_302}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3927 = out_prepend_302; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3928 = _out_T_3927; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_303 = _out_T_3928; // @[RegisterRouter.scala:87:24] wire out_rimask_365 = |_out_rimask_T_365; // @[RegisterRouter.scala:87:24] wire out_wimask_365 = &_out_wimask_T_365; // @[RegisterRouter.scala:87:24] wire out_romask_365 = |_out_romask_T_365; // @[RegisterRouter.scala:87:24] wire out_womask_365 = &_out_womask_T_365; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_365 = out_rivalid_1_219 & out_rimask_365; // @[RegisterRouter.scala:87:24] wire _out_T_3930 = out_f_rivalid_365; // @[RegisterRouter.scala:87:24] wire out_f_roready_365 = out_roready_1_219 & out_romask_365; // @[RegisterRouter.scala:87:24] wire _out_T_3931 = out_f_roready_365; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_365 = out_wivalid_1_219 & out_wimask_365; // @[RegisterRouter.scala:87:24] wire out_f_woready_365 = out_woready_1_219 & out_womask_365; // @[RegisterRouter.scala:87:24] wire _out_T_3932 = ~out_rimask_365; // @[RegisterRouter.scala:87:24] wire _out_T_3933 = ~out_wimask_365; // @[RegisterRouter.scala:87:24] wire _out_T_3934 = ~out_romask_365; // @[RegisterRouter.scala:87:24] wire _out_T_3935 = ~out_womask_365; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_303 = {hi_1004, flags_0_go, _out_prepend_T_303}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3936 = out_prepend_303; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3937 = _out_T_3936; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_304 = _out_T_3937; // @[RegisterRouter.scala:87:24] wire out_rimask_366 = |_out_rimask_T_366; // @[RegisterRouter.scala:87:24] wire out_wimask_366 = &_out_wimask_T_366; // @[RegisterRouter.scala:87:24] wire out_romask_366 = |_out_romask_T_366; // @[RegisterRouter.scala:87:24] wire out_womask_366 = &_out_womask_T_366; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_366 = out_rivalid_1_220 & out_rimask_366; // @[RegisterRouter.scala:87:24] wire _out_T_3939 = out_f_rivalid_366; // @[RegisterRouter.scala:87:24] wire out_f_roready_366 = out_roready_1_220 & out_romask_366; // @[RegisterRouter.scala:87:24] wire _out_T_3940 = out_f_roready_366; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_366 = out_wivalid_1_220 & out_wimask_366; // @[RegisterRouter.scala:87:24] wire out_f_woready_366 = out_woready_1_220 & out_womask_366; // @[RegisterRouter.scala:87:24] wire _out_T_3941 = ~out_rimask_366; // @[RegisterRouter.scala:87:24] wire _out_T_3942 = ~out_wimask_366; // @[RegisterRouter.scala:87:24] wire _out_T_3943 = ~out_romask_366; // @[RegisterRouter.scala:87:24] wire _out_T_3944 = ~out_womask_366; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_304 = {hi_1005, flags_0_go, _out_prepend_T_304}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3945 = out_prepend_304; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3946 = _out_T_3945; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_305 = _out_T_3946; // @[RegisterRouter.scala:87:24] wire out_rimask_367 = |_out_rimask_T_367; // @[RegisterRouter.scala:87:24] wire out_wimask_367 = &_out_wimask_T_367; // @[RegisterRouter.scala:87:24] wire out_romask_367 = |_out_romask_T_367; // @[RegisterRouter.scala:87:24] wire out_womask_367 = &_out_womask_T_367; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_367 = out_rivalid_1_221 & out_rimask_367; // @[RegisterRouter.scala:87:24] wire _out_T_3948 = out_f_rivalid_367; // @[RegisterRouter.scala:87:24] wire out_f_roready_367 = out_roready_1_221 & out_romask_367; // @[RegisterRouter.scala:87:24] wire _out_T_3949 = out_f_roready_367; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_367 = out_wivalid_1_221 & out_wimask_367; // @[RegisterRouter.scala:87:24] wire out_f_woready_367 = out_woready_1_221 & out_womask_367; // @[RegisterRouter.scala:87:24] wire _out_T_3950 = ~out_rimask_367; // @[RegisterRouter.scala:87:24] wire _out_T_3951 = ~out_wimask_367; // @[RegisterRouter.scala:87:24] wire _out_T_3952 = ~out_romask_367; // @[RegisterRouter.scala:87:24] wire _out_T_3953 = ~out_womask_367; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_305 = {hi_1006, flags_0_go, _out_prepend_T_305}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3954 = out_prepend_305; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3955 = _out_T_3954; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_306 = _out_T_3955; // @[RegisterRouter.scala:87:24] wire out_rimask_368 = |_out_rimask_T_368; // @[RegisterRouter.scala:87:24] wire out_wimask_368 = &_out_wimask_T_368; // @[RegisterRouter.scala:87:24] wire out_romask_368 = |_out_romask_T_368; // @[RegisterRouter.scala:87:24] wire out_womask_368 = &_out_womask_T_368; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_368 = out_rivalid_1_222 & out_rimask_368; // @[RegisterRouter.scala:87:24] wire _out_T_3957 = out_f_rivalid_368; // @[RegisterRouter.scala:87:24] wire out_f_roready_368 = out_roready_1_222 & out_romask_368; // @[RegisterRouter.scala:87:24] wire _out_T_3958 = out_f_roready_368; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_368 = out_wivalid_1_222 & out_wimask_368; // @[RegisterRouter.scala:87:24] wire out_f_woready_368 = out_woready_1_222 & out_womask_368; // @[RegisterRouter.scala:87:24] wire _out_T_3959 = ~out_rimask_368; // @[RegisterRouter.scala:87:24] wire _out_T_3960 = ~out_wimask_368; // @[RegisterRouter.scala:87:24] wire _out_T_3961 = ~out_romask_368; // @[RegisterRouter.scala:87:24] wire _out_T_3962 = ~out_womask_368; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_306 = {hi_1007, flags_0_go, _out_prepend_T_306}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3963 = out_prepend_306; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3964 = _out_T_3963; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_307 = _out_T_3964; // @[RegisterRouter.scala:87:24] wire out_rimask_369 = |_out_rimask_T_369; // @[RegisterRouter.scala:87:24] wire out_wimask_369 = &_out_wimask_T_369; // @[RegisterRouter.scala:87:24] wire out_romask_369 = |_out_romask_T_369; // @[RegisterRouter.scala:87:24] wire out_womask_369 = &_out_womask_T_369; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_369 = out_rivalid_1_223 & out_rimask_369; // @[RegisterRouter.scala:87:24] wire _out_T_3966 = out_f_rivalid_369; // @[RegisterRouter.scala:87:24] wire out_f_roready_369 = out_roready_1_223 & out_romask_369; // @[RegisterRouter.scala:87:24] wire _out_T_3967 = out_f_roready_369; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_369 = out_wivalid_1_223 & out_wimask_369; // @[RegisterRouter.scala:87:24] wire out_f_woready_369 = out_woready_1_223 & out_womask_369; // @[RegisterRouter.scala:87:24] wire _out_T_3968 = ~out_rimask_369; // @[RegisterRouter.scala:87:24] wire _out_T_3969 = ~out_wimask_369; // @[RegisterRouter.scala:87:24] wire _out_T_3970 = ~out_romask_369; // @[RegisterRouter.scala:87:24] wire _out_T_3971 = ~out_womask_369; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_307 = {hi_1008, flags_0_go, _out_prepend_T_307}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3972 = out_prepend_307; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3973 = _out_T_3972; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_253 = _out_T_3973; // @[MuxLiteral.scala:49:48] wire out_rimask_370 = |_out_rimask_T_370; // @[RegisterRouter.scala:87:24] wire out_wimask_370 = &_out_wimask_T_370; // @[RegisterRouter.scala:87:24] wire out_romask_370 = |_out_romask_T_370; // @[RegisterRouter.scala:87:24] wire out_womask_370 = &_out_womask_T_370; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_370 = out_rivalid_1_224 & out_rimask_370; // @[RegisterRouter.scala:87:24] wire _out_T_3975 = out_f_rivalid_370; // @[RegisterRouter.scala:87:24] wire out_f_roready_370 = out_roready_1_224 & out_romask_370; // @[RegisterRouter.scala:87:24] wire _out_T_3976 = out_f_roready_370; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_370 = out_wivalid_1_224 & out_wimask_370; // @[RegisterRouter.scala:87:24] wire out_f_woready_370 = out_woready_1_224 & out_womask_370; // @[RegisterRouter.scala:87:24] wire _out_T_3977 = ~out_rimask_370; // @[RegisterRouter.scala:87:24] wire _out_T_3978 = ~out_wimask_370; // @[RegisterRouter.scala:87:24] wire _out_T_3979 = ~out_romask_370; // @[RegisterRouter.scala:87:24] wire _out_T_3980 = ~out_womask_370; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3982 = _out_T_3981; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_308 = _out_T_3982; // @[RegisterRouter.scala:87:24] wire out_rimask_371 = |_out_rimask_T_371; // @[RegisterRouter.scala:87:24] wire out_wimask_371 = &_out_wimask_T_371; // @[RegisterRouter.scala:87:24] wire out_romask_371 = |_out_romask_T_371; // @[RegisterRouter.scala:87:24] wire out_womask_371 = &_out_womask_T_371; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_371 = out_rivalid_1_225 & out_rimask_371; // @[RegisterRouter.scala:87:24] wire _out_T_3984 = out_f_rivalid_371; // @[RegisterRouter.scala:87:24] wire out_f_roready_371 = out_roready_1_225 & out_romask_371; // @[RegisterRouter.scala:87:24] wire _out_T_3985 = out_f_roready_371; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_371 = out_wivalid_1_225 & out_wimask_371; // @[RegisterRouter.scala:87:24] wire out_f_woready_371 = out_woready_1_225 & out_womask_371; // @[RegisterRouter.scala:87:24] wire _out_T_3986 = ~out_rimask_371; // @[RegisterRouter.scala:87:24] wire _out_T_3987 = ~out_wimask_371; // @[RegisterRouter.scala:87:24] wire _out_T_3988 = ~out_romask_371; // @[RegisterRouter.scala:87:24] wire _out_T_3989 = ~out_womask_371; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_308 = {hi_154, flags_0_go, _out_prepend_T_308}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3990 = out_prepend_308; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3991 = _out_T_3990; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_309 = _out_T_3991; // @[RegisterRouter.scala:87:24] wire out_rimask_372 = |_out_rimask_T_372; // @[RegisterRouter.scala:87:24] wire out_wimask_372 = &_out_wimask_T_372; // @[RegisterRouter.scala:87:24] wire out_romask_372 = |_out_romask_T_372; // @[RegisterRouter.scala:87:24] wire out_womask_372 = &_out_womask_T_372; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_372 = out_rivalid_1_226 & out_rimask_372; // @[RegisterRouter.scala:87:24] wire _out_T_3993 = out_f_rivalid_372; // @[RegisterRouter.scala:87:24] wire out_f_roready_372 = out_roready_1_226 & out_romask_372; // @[RegisterRouter.scala:87:24] wire _out_T_3994 = out_f_roready_372; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_372 = out_wivalid_1_226 & out_wimask_372; // @[RegisterRouter.scala:87:24] wire out_f_woready_372 = out_woready_1_226 & out_womask_372; // @[RegisterRouter.scala:87:24] wire _out_T_3995 = ~out_rimask_372; // @[RegisterRouter.scala:87:24] wire _out_T_3996 = ~out_wimask_372; // @[RegisterRouter.scala:87:24] wire _out_T_3997 = ~out_romask_372; // @[RegisterRouter.scala:87:24] wire _out_T_3998 = ~out_womask_372; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_309 = {hi_155, flags_0_go, _out_prepend_T_309}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3999 = out_prepend_309; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4000 = _out_T_3999; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_310 = _out_T_4000; // @[RegisterRouter.scala:87:24] wire out_rimask_373 = |_out_rimask_T_373; // @[RegisterRouter.scala:87:24] wire out_wimask_373 = &_out_wimask_T_373; // @[RegisterRouter.scala:87:24] wire out_romask_373 = |_out_romask_T_373; // @[RegisterRouter.scala:87:24] wire out_womask_373 = &_out_womask_T_373; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_373 = out_rivalid_1_227 & out_rimask_373; // @[RegisterRouter.scala:87:24] wire _out_T_4002 = out_f_rivalid_373; // @[RegisterRouter.scala:87:24] wire out_f_roready_373 = out_roready_1_227 & out_romask_373; // @[RegisterRouter.scala:87:24] wire _out_T_4003 = out_f_roready_373; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_373 = out_wivalid_1_227 & out_wimask_373; // @[RegisterRouter.scala:87:24] wire out_f_woready_373 = out_woready_1_227 & out_womask_373; // @[RegisterRouter.scala:87:24] wire _out_T_4004 = ~out_rimask_373; // @[RegisterRouter.scala:87:24] wire _out_T_4005 = ~out_wimask_373; // @[RegisterRouter.scala:87:24] wire _out_T_4006 = ~out_romask_373; // @[RegisterRouter.scala:87:24] wire _out_T_4007 = ~out_womask_373; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_310 = {hi_156, flags_0_go, _out_prepend_T_310}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4008 = out_prepend_310; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4009 = _out_T_4008; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_311 = _out_T_4009; // @[RegisterRouter.scala:87:24] wire out_rimask_374 = |_out_rimask_T_374; // @[RegisterRouter.scala:87:24] wire out_wimask_374 = &_out_wimask_T_374; // @[RegisterRouter.scala:87:24] wire out_romask_374 = |_out_romask_T_374; // @[RegisterRouter.scala:87:24] wire out_womask_374 = &_out_womask_T_374; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_374 = out_rivalid_1_228 & out_rimask_374; // @[RegisterRouter.scala:87:24] wire _out_T_4011 = out_f_rivalid_374; // @[RegisterRouter.scala:87:24] wire out_f_roready_374 = out_roready_1_228 & out_romask_374; // @[RegisterRouter.scala:87:24] wire _out_T_4012 = out_f_roready_374; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_374 = out_wivalid_1_228 & out_wimask_374; // @[RegisterRouter.scala:87:24] wire out_f_woready_374 = out_woready_1_228 & out_womask_374; // @[RegisterRouter.scala:87:24] wire _out_T_4013 = ~out_rimask_374; // @[RegisterRouter.scala:87:24] wire _out_T_4014 = ~out_wimask_374; // @[RegisterRouter.scala:87:24] wire _out_T_4015 = ~out_romask_374; // @[RegisterRouter.scala:87:24] wire _out_T_4016 = ~out_womask_374; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_311 = {hi_157, flags_0_go, _out_prepend_T_311}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4017 = out_prepend_311; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4018 = _out_T_4017; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_312 = _out_T_4018; // @[RegisterRouter.scala:87:24] wire out_rimask_375 = |_out_rimask_T_375; // @[RegisterRouter.scala:87:24] wire out_wimask_375 = &_out_wimask_T_375; // @[RegisterRouter.scala:87:24] wire out_romask_375 = |_out_romask_T_375; // @[RegisterRouter.scala:87:24] wire out_womask_375 = &_out_womask_T_375; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_375 = out_rivalid_1_229 & out_rimask_375; // @[RegisterRouter.scala:87:24] wire _out_T_4020 = out_f_rivalid_375; // @[RegisterRouter.scala:87:24] wire out_f_roready_375 = out_roready_1_229 & out_romask_375; // @[RegisterRouter.scala:87:24] wire _out_T_4021 = out_f_roready_375; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_375 = out_wivalid_1_229 & out_wimask_375; // @[RegisterRouter.scala:87:24] wire out_f_woready_375 = out_woready_1_229 & out_womask_375; // @[RegisterRouter.scala:87:24] wire _out_T_4022 = ~out_rimask_375; // @[RegisterRouter.scala:87:24] wire _out_T_4023 = ~out_wimask_375; // @[RegisterRouter.scala:87:24] wire _out_T_4024 = ~out_romask_375; // @[RegisterRouter.scala:87:24] wire _out_T_4025 = ~out_womask_375; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_312 = {hi_158, flags_0_go, _out_prepend_T_312}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4026 = out_prepend_312; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4027 = _out_T_4026; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_313 = _out_T_4027; // @[RegisterRouter.scala:87:24] wire out_rimask_376 = |_out_rimask_T_376; // @[RegisterRouter.scala:87:24] wire out_wimask_376 = &_out_wimask_T_376; // @[RegisterRouter.scala:87:24] wire out_romask_376 = |_out_romask_T_376; // @[RegisterRouter.scala:87:24] wire out_womask_376 = &_out_womask_T_376; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_376 = out_rivalid_1_230 & out_rimask_376; // @[RegisterRouter.scala:87:24] wire _out_T_4029 = out_f_rivalid_376; // @[RegisterRouter.scala:87:24] wire out_f_roready_376 = out_roready_1_230 & out_romask_376; // @[RegisterRouter.scala:87:24] wire _out_T_4030 = out_f_roready_376; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_376 = out_wivalid_1_230 & out_wimask_376; // @[RegisterRouter.scala:87:24] wire out_f_woready_376 = out_woready_1_230 & out_womask_376; // @[RegisterRouter.scala:87:24] wire _out_T_4031 = ~out_rimask_376; // @[RegisterRouter.scala:87:24] wire _out_T_4032 = ~out_wimask_376; // @[RegisterRouter.scala:87:24] wire _out_T_4033 = ~out_romask_376; // @[RegisterRouter.scala:87:24] wire _out_T_4034 = ~out_womask_376; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_313 = {hi_159, flags_0_go, _out_prepend_T_313}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4035 = out_prepend_313; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4036 = _out_T_4035; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_314 = _out_T_4036; // @[RegisterRouter.scala:87:24] wire out_rimask_377 = |_out_rimask_T_377; // @[RegisterRouter.scala:87:24] wire out_wimask_377 = &_out_wimask_T_377; // @[RegisterRouter.scala:87:24] wire out_romask_377 = |_out_romask_T_377; // @[RegisterRouter.scala:87:24] wire out_womask_377 = &_out_womask_T_377; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_377 = out_rivalid_1_231 & out_rimask_377; // @[RegisterRouter.scala:87:24] wire _out_T_4038 = out_f_rivalid_377; // @[RegisterRouter.scala:87:24] wire out_f_roready_377 = out_roready_1_231 & out_romask_377; // @[RegisterRouter.scala:87:24] wire _out_T_4039 = out_f_roready_377; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_377 = out_wivalid_1_231 & out_wimask_377; // @[RegisterRouter.scala:87:24] wire out_f_woready_377 = out_woready_1_231 & out_womask_377; // @[RegisterRouter.scala:87:24] wire _out_T_4040 = ~out_rimask_377; // @[RegisterRouter.scala:87:24] wire _out_T_4041 = ~out_wimask_377; // @[RegisterRouter.scala:87:24] wire _out_T_4042 = ~out_romask_377; // @[RegisterRouter.scala:87:24] wire _out_T_4043 = ~out_womask_377; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_314 = {hi_160, flags_0_go, _out_prepend_T_314}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4044 = out_prepend_314; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4045 = _out_T_4044; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_147 = _out_T_4045; // @[MuxLiteral.scala:49:48] wire out_rimask_378 = |_out_rimask_T_378; // @[RegisterRouter.scala:87:24] wire out_wimask_378 = &_out_wimask_T_378; // @[RegisterRouter.scala:87:24] wire out_romask_378 = |_out_romask_T_378; // @[RegisterRouter.scala:87:24] wire out_womask_378 = &_out_womask_T_378; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_378 = out_rivalid_1_232 & out_rimask_378; // @[RegisterRouter.scala:87:24] wire _out_T_4047 = out_f_rivalid_378; // @[RegisterRouter.scala:87:24] wire out_f_roready_378 = out_roready_1_232 & out_romask_378; // @[RegisterRouter.scala:87:24] wire _out_T_4048 = out_f_roready_378; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_378 = out_wivalid_1_232 & out_wimask_378; // @[RegisterRouter.scala:87:24] wire out_f_woready_378 = out_woready_1_232 & out_womask_378; // @[RegisterRouter.scala:87:24] wire _out_T_4049 = ~out_rimask_378; // @[RegisterRouter.scala:87:24] wire _out_T_4050 = ~out_wimask_378; // @[RegisterRouter.scala:87:24] wire _out_T_4051 = ~out_romask_378; // @[RegisterRouter.scala:87:24] wire _out_T_4052 = ~out_womask_378; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4054 = _out_T_4053; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_315 = _out_T_4054; // @[RegisterRouter.scala:87:24] wire out_rimask_379 = |_out_rimask_T_379; // @[RegisterRouter.scala:87:24] wire out_wimask_379 = &_out_wimask_T_379; // @[RegisterRouter.scala:87:24] wire out_romask_379 = |_out_romask_T_379; // @[RegisterRouter.scala:87:24] wire out_womask_379 = &_out_womask_T_379; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_379 = out_rivalid_1_233 & out_rimask_379; // @[RegisterRouter.scala:87:24] wire _out_T_4056 = out_f_rivalid_379; // @[RegisterRouter.scala:87:24] wire out_f_roready_379 = out_roready_1_233 & out_romask_379; // @[RegisterRouter.scala:87:24] wire _out_T_4057 = out_f_roready_379; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_379 = out_wivalid_1_233 & out_wimask_379; // @[RegisterRouter.scala:87:24] wire out_f_woready_379 = out_woready_1_233 & out_womask_379; // @[RegisterRouter.scala:87:24] wire _out_T_4058 = ~out_rimask_379; // @[RegisterRouter.scala:87:24] wire _out_T_4059 = ~out_wimask_379; // @[RegisterRouter.scala:87:24] wire _out_T_4060 = ~out_romask_379; // @[RegisterRouter.scala:87:24] wire _out_T_4061 = ~out_womask_379; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_315 = {hi_746, flags_0_go, _out_prepend_T_315}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4062 = out_prepend_315; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4063 = _out_T_4062; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_316 = _out_T_4063; // @[RegisterRouter.scala:87:24] wire out_rimask_380 = |_out_rimask_T_380; // @[RegisterRouter.scala:87:24] wire out_wimask_380 = &_out_wimask_T_380; // @[RegisterRouter.scala:87:24] wire out_romask_380 = |_out_romask_T_380; // @[RegisterRouter.scala:87:24] wire out_womask_380 = &_out_womask_T_380; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_380 = out_rivalid_1_234 & out_rimask_380; // @[RegisterRouter.scala:87:24] wire _out_T_4065 = out_f_rivalid_380; // @[RegisterRouter.scala:87:24] wire out_f_roready_380 = out_roready_1_234 & out_romask_380; // @[RegisterRouter.scala:87:24] wire _out_T_4066 = out_f_roready_380; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_380 = out_wivalid_1_234 & out_wimask_380; // @[RegisterRouter.scala:87:24] wire out_f_woready_380 = out_woready_1_234 & out_womask_380; // @[RegisterRouter.scala:87:24] wire _out_T_4067 = ~out_rimask_380; // @[RegisterRouter.scala:87:24] wire _out_T_4068 = ~out_wimask_380; // @[RegisterRouter.scala:87:24] wire _out_T_4069 = ~out_romask_380; // @[RegisterRouter.scala:87:24] wire _out_T_4070 = ~out_womask_380; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_316 = {hi_747, flags_0_go, _out_prepend_T_316}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4071 = out_prepend_316; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4072 = _out_T_4071; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_317 = _out_T_4072; // @[RegisterRouter.scala:87:24] wire out_rimask_381 = |_out_rimask_T_381; // @[RegisterRouter.scala:87:24] wire out_wimask_381 = &_out_wimask_T_381; // @[RegisterRouter.scala:87:24] wire out_romask_381 = |_out_romask_T_381; // @[RegisterRouter.scala:87:24] wire out_womask_381 = &_out_womask_T_381; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_381 = out_rivalid_1_235 & out_rimask_381; // @[RegisterRouter.scala:87:24] wire _out_T_4074 = out_f_rivalid_381; // @[RegisterRouter.scala:87:24] wire out_f_roready_381 = out_roready_1_235 & out_romask_381; // @[RegisterRouter.scala:87:24] wire _out_T_4075 = out_f_roready_381; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_381 = out_wivalid_1_235 & out_wimask_381; // @[RegisterRouter.scala:87:24] wire out_f_woready_381 = out_woready_1_235 & out_womask_381; // @[RegisterRouter.scala:87:24] wire _out_T_4076 = ~out_rimask_381; // @[RegisterRouter.scala:87:24] wire _out_T_4077 = ~out_wimask_381; // @[RegisterRouter.scala:87:24] wire _out_T_4078 = ~out_romask_381; // @[RegisterRouter.scala:87:24] wire _out_T_4079 = ~out_womask_381; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_317 = {hi_748, flags_0_go, _out_prepend_T_317}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4080 = out_prepend_317; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4081 = _out_T_4080; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_318 = _out_T_4081; // @[RegisterRouter.scala:87:24] wire out_rimask_382 = |_out_rimask_T_382; // @[RegisterRouter.scala:87:24] wire out_wimask_382 = &_out_wimask_T_382; // @[RegisterRouter.scala:87:24] wire out_romask_382 = |_out_romask_T_382; // @[RegisterRouter.scala:87:24] wire out_womask_382 = &_out_womask_T_382; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_382 = out_rivalid_1_236 & out_rimask_382; // @[RegisterRouter.scala:87:24] wire _out_T_4083 = out_f_rivalid_382; // @[RegisterRouter.scala:87:24] wire out_f_roready_382 = out_roready_1_236 & out_romask_382; // @[RegisterRouter.scala:87:24] wire _out_T_4084 = out_f_roready_382; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_382 = out_wivalid_1_236 & out_wimask_382; // @[RegisterRouter.scala:87:24] wire out_f_woready_382 = out_woready_1_236 & out_womask_382; // @[RegisterRouter.scala:87:24] wire _out_T_4085 = ~out_rimask_382; // @[RegisterRouter.scala:87:24] wire _out_T_4086 = ~out_wimask_382; // @[RegisterRouter.scala:87:24] wire _out_T_4087 = ~out_romask_382; // @[RegisterRouter.scala:87:24] wire _out_T_4088 = ~out_womask_382; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_318 = {hi_749, flags_0_go, _out_prepend_T_318}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4089 = out_prepend_318; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4090 = _out_T_4089; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_319 = _out_T_4090; // @[RegisterRouter.scala:87:24] wire out_rimask_383 = |_out_rimask_T_383; // @[RegisterRouter.scala:87:24] wire out_wimask_383 = &_out_wimask_T_383; // @[RegisterRouter.scala:87:24] wire out_romask_383 = |_out_romask_T_383; // @[RegisterRouter.scala:87:24] wire out_womask_383 = &_out_womask_T_383; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_383 = out_rivalid_1_237 & out_rimask_383; // @[RegisterRouter.scala:87:24] wire _out_T_4092 = out_f_rivalid_383; // @[RegisterRouter.scala:87:24] wire out_f_roready_383 = out_roready_1_237 & out_romask_383; // @[RegisterRouter.scala:87:24] wire _out_T_4093 = out_f_roready_383; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_383 = out_wivalid_1_237 & out_wimask_383; // @[RegisterRouter.scala:87:24] wire out_f_woready_383 = out_woready_1_237 & out_womask_383; // @[RegisterRouter.scala:87:24] wire _out_T_4094 = ~out_rimask_383; // @[RegisterRouter.scala:87:24] wire _out_T_4095 = ~out_wimask_383; // @[RegisterRouter.scala:87:24] wire _out_T_4096 = ~out_romask_383; // @[RegisterRouter.scala:87:24] wire _out_T_4097 = ~out_womask_383; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_319 = {hi_750, flags_0_go, _out_prepend_T_319}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4098 = out_prepend_319; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4099 = _out_T_4098; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_320 = _out_T_4099; // @[RegisterRouter.scala:87:24] wire out_rimask_384 = |_out_rimask_T_384; // @[RegisterRouter.scala:87:24] wire out_wimask_384 = &_out_wimask_T_384; // @[RegisterRouter.scala:87:24] wire out_romask_384 = |_out_romask_T_384; // @[RegisterRouter.scala:87:24] wire out_womask_384 = &_out_womask_T_384; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_384 = out_rivalid_1_238 & out_rimask_384; // @[RegisterRouter.scala:87:24] wire _out_T_4101 = out_f_rivalid_384; // @[RegisterRouter.scala:87:24] wire out_f_roready_384 = out_roready_1_238 & out_romask_384; // @[RegisterRouter.scala:87:24] wire _out_T_4102 = out_f_roready_384; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_384 = out_wivalid_1_238 & out_wimask_384; // @[RegisterRouter.scala:87:24] wire out_f_woready_384 = out_woready_1_238 & out_womask_384; // @[RegisterRouter.scala:87:24] wire _out_T_4103 = ~out_rimask_384; // @[RegisterRouter.scala:87:24] wire _out_T_4104 = ~out_wimask_384; // @[RegisterRouter.scala:87:24] wire _out_T_4105 = ~out_romask_384; // @[RegisterRouter.scala:87:24] wire _out_T_4106 = ~out_womask_384; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_320 = {hi_751, flags_0_go, _out_prepend_T_320}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4107 = out_prepend_320; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4108 = _out_T_4107; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_321 = _out_T_4108; // @[RegisterRouter.scala:87:24] wire out_rimask_385 = |_out_rimask_T_385; // @[RegisterRouter.scala:87:24] wire out_wimask_385 = &_out_wimask_T_385; // @[RegisterRouter.scala:87:24] wire out_romask_385 = |_out_romask_T_385; // @[RegisterRouter.scala:87:24] wire out_womask_385 = &_out_womask_T_385; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_385 = out_rivalid_1_239 & out_rimask_385; // @[RegisterRouter.scala:87:24] wire _out_T_4110 = out_f_rivalid_385; // @[RegisterRouter.scala:87:24] wire out_f_roready_385 = out_roready_1_239 & out_romask_385; // @[RegisterRouter.scala:87:24] wire _out_T_4111 = out_f_roready_385; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_385 = out_wivalid_1_239 & out_wimask_385; // @[RegisterRouter.scala:87:24] wire out_f_woready_385 = out_woready_1_239 & out_womask_385; // @[RegisterRouter.scala:87:24] wire _out_T_4112 = ~out_rimask_385; // @[RegisterRouter.scala:87:24] wire _out_T_4113 = ~out_wimask_385; // @[RegisterRouter.scala:87:24] wire _out_T_4114 = ~out_romask_385; // @[RegisterRouter.scala:87:24] wire _out_T_4115 = ~out_womask_385; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_321 = {hi_752, flags_0_go, _out_prepend_T_321}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4116 = out_prepend_321; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4117 = _out_T_4116; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_221 = _out_T_4117; // @[MuxLiteral.scala:49:48] wire out_rimask_386 = |_out_rimask_T_386; // @[RegisterRouter.scala:87:24] wire out_wimask_386 = &_out_wimask_T_386; // @[RegisterRouter.scala:87:24] wire out_romask_386 = |_out_romask_T_386; // @[RegisterRouter.scala:87:24] wire out_womask_386 = &_out_womask_T_386; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_386 = out_rivalid_1_240 & out_rimask_386; // @[RegisterRouter.scala:87:24] wire _out_T_4119 = out_f_rivalid_386; // @[RegisterRouter.scala:87:24] wire out_f_roready_386 = out_roready_1_240 & out_romask_386; // @[RegisterRouter.scala:87:24] wire _out_T_4120 = out_f_roready_386; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_386 = out_wivalid_1_240 & out_wimask_386; // @[RegisterRouter.scala:87:24] wire out_f_woready_386 = out_woready_1_240 & out_womask_386; // @[RegisterRouter.scala:87:24] wire _out_T_4121 = ~out_rimask_386; // @[RegisterRouter.scala:87:24] wire _out_T_4122 = ~out_wimask_386; // @[RegisterRouter.scala:87:24] wire _out_T_4123 = ~out_romask_386; // @[RegisterRouter.scala:87:24] wire _out_T_4124 = ~out_womask_386; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4126 = _out_T_4125; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_322 = _out_T_4126; // @[RegisterRouter.scala:87:24] wire out_rimask_387 = |_out_rimask_T_387; // @[RegisterRouter.scala:87:24] wire out_wimask_387 = &_out_wimask_T_387; // @[RegisterRouter.scala:87:24] wire out_romask_387 = |_out_romask_T_387; // @[RegisterRouter.scala:87:24] wire out_womask_387 = &_out_womask_T_387; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_387 = out_rivalid_1_241 & out_rimask_387; // @[RegisterRouter.scala:87:24] wire _out_T_4128 = out_f_rivalid_387; // @[RegisterRouter.scala:87:24] wire out_f_roready_387 = out_roready_1_241 & out_romask_387; // @[RegisterRouter.scala:87:24] wire _out_T_4129 = out_f_roready_387; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_387 = out_wivalid_1_241 & out_wimask_387; // @[RegisterRouter.scala:87:24] wire out_f_woready_387 = out_woready_1_241 & out_womask_387; // @[RegisterRouter.scala:87:24] wire _out_T_4130 = ~out_rimask_387; // @[RegisterRouter.scala:87:24] wire _out_T_4131 = ~out_wimask_387; // @[RegisterRouter.scala:87:24] wire _out_T_4132 = ~out_romask_387; // @[RegisterRouter.scala:87:24] wire _out_T_4133 = ~out_womask_387; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_322 = {hi_34, flags_0_go, _out_prepend_T_322}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4134 = out_prepend_322; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4135 = _out_T_4134; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_323 = _out_T_4135; // @[RegisterRouter.scala:87:24] wire out_rimask_388 = |_out_rimask_T_388; // @[RegisterRouter.scala:87:24] wire out_wimask_388 = &_out_wimask_T_388; // @[RegisterRouter.scala:87:24] wire out_romask_388 = |_out_romask_T_388; // @[RegisterRouter.scala:87:24] wire out_womask_388 = &_out_womask_T_388; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_388 = out_rivalid_1_242 & out_rimask_388; // @[RegisterRouter.scala:87:24] wire _out_T_4137 = out_f_rivalid_388; // @[RegisterRouter.scala:87:24] wire out_f_roready_388 = out_roready_1_242 & out_romask_388; // @[RegisterRouter.scala:87:24] wire _out_T_4138 = out_f_roready_388; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_388 = out_wivalid_1_242 & out_wimask_388; // @[RegisterRouter.scala:87:24] wire out_f_woready_388 = out_woready_1_242 & out_womask_388; // @[RegisterRouter.scala:87:24] wire _out_T_4139 = ~out_rimask_388; // @[RegisterRouter.scala:87:24] wire _out_T_4140 = ~out_wimask_388; // @[RegisterRouter.scala:87:24] wire _out_T_4141 = ~out_romask_388; // @[RegisterRouter.scala:87:24] wire _out_T_4142 = ~out_womask_388; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_323 = {hi_35, flags_0_go, _out_prepend_T_323}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4143 = out_prepend_323; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4144 = _out_T_4143; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_324 = _out_T_4144; // @[RegisterRouter.scala:87:24] wire out_rimask_389 = |_out_rimask_T_389; // @[RegisterRouter.scala:87:24] wire out_wimask_389 = &_out_wimask_T_389; // @[RegisterRouter.scala:87:24] wire out_romask_389 = |_out_romask_T_389; // @[RegisterRouter.scala:87:24] wire out_womask_389 = &_out_womask_T_389; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_389 = out_rivalid_1_243 & out_rimask_389; // @[RegisterRouter.scala:87:24] wire _out_T_4146 = out_f_rivalid_389; // @[RegisterRouter.scala:87:24] wire out_f_roready_389 = out_roready_1_243 & out_romask_389; // @[RegisterRouter.scala:87:24] wire _out_T_4147 = out_f_roready_389; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_389 = out_wivalid_1_243 & out_wimask_389; // @[RegisterRouter.scala:87:24] wire out_f_woready_389 = out_woready_1_243 & out_womask_389; // @[RegisterRouter.scala:87:24] wire _out_T_4148 = ~out_rimask_389; // @[RegisterRouter.scala:87:24] wire _out_T_4149 = ~out_wimask_389; // @[RegisterRouter.scala:87:24] wire _out_T_4150 = ~out_romask_389; // @[RegisterRouter.scala:87:24] wire _out_T_4151 = ~out_womask_389; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_324 = {hi_36, flags_0_go, _out_prepend_T_324}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4152 = out_prepend_324; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4153 = _out_T_4152; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_325 = _out_T_4153; // @[RegisterRouter.scala:87:24] wire out_rimask_390 = |_out_rimask_T_390; // @[RegisterRouter.scala:87:24] wire out_wimask_390 = &_out_wimask_T_390; // @[RegisterRouter.scala:87:24] wire out_romask_390 = |_out_romask_T_390; // @[RegisterRouter.scala:87:24] wire out_womask_390 = &_out_womask_T_390; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_390 = out_rivalid_1_244 & out_rimask_390; // @[RegisterRouter.scala:87:24] wire _out_T_4155 = out_f_rivalid_390; // @[RegisterRouter.scala:87:24] wire out_f_roready_390 = out_roready_1_244 & out_romask_390; // @[RegisterRouter.scala:87:24] wire _out_T_4156 = out_f_roready_390; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_390 = out_wivalid_1_244 & out_wimask_390; // @[RegisterRouter.scala:87:24] wire out_f_woready_390 = out_woready_1_244 & out_womask_390; // @[RegisterRouter.scala:87:24] wire _out_T_4157 = ~out_rimask_390; // @[RegisterRouter.scala:87:24] wire _out_T_4158 = ~out_wimask_390; // @[RegisterRouter.scala:87:24] wire _out_T_4159 = ~out_romask_390; // @[RegisterRouter.scala:87:24] wire _out_T_4160 = ~out_womask_390; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_325 = {hi_37, flags_0_go, _out_prepend_T_325}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4161 = out_prepend_325; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4162 = _out_T_4161; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_326 = _out_T_4162; // @[RegisterRouter.scala:87:24] wire out_rimask_391 = |_out_rimask_T_391; // @[RegisterRouter.scala:87:24] wire out_wimask_391 = &_out_wimask_T_391; // @[RegisterRouter.scala:87:24] wire out_romask_391 = |_out_romask_T_391; // @[RegisterRouter.scala:87:24] wire out_womask_391 = &_out_womask_T_391; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_391 = out_rivalid_1_245 & out_rimask_391; // @[RegisterRouter.scala:87:24] wire _out_T_4164 = out_f_rivalid_391; // @[RegisterRouter.scala:87:24] wire out_f_roready_391 = out_roready_1_245 & out_romask_391; // @[RegisterRouter.scala:87:24] wire _out_T_4165 = out_f_roready_391; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_391 = out_wivalid_1_245 & out_wimask_391; // @[RegisterRouter.scala:87:24] wire out_f_woready_391 = out_woready_1_245 & out_womask_391; // @[RegisterRouter.scala:87:24] wire _out_T_4166 = ~out_rimask_391; // @[RegisterRouter.scala:87:24] wire _out_T_4167 = ~out_wimask_391; // @[RegisterRouter.scala:87:24] wire _out_T_4168 = ~out_romask_391; // @[RegisterRouter.scala:87:24] wire _out_T_4169 = ~out_womask_391; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_326 = {hi_38, flags_0_go, _out_prepend_T_326}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4170 = out_prepend_326; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4171 = _out_T_4170; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_327 = _out_T_4171; // @[RegisterRouter.scala:87:24] wire out_rimask_392 = |_out_rimask_T_392; // @[RegisterRouter.scala:87:24] wire out_wimask_392 = &_out_wimask_T_392; // @[RegisterRouter.scala:87:24] wire out_romask_392 = |_out_romask_T_392; // @[RegisterRouter.scala:87:24] wire out_womask_392 = &_out_womask_T_392; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_392 = out_rivalid_1_246 & out_rimask_392; // @[RegisterRouter.scala:87:24] wire _out_T_4173 = out_f_rivalid_392; // @[RegisterRouter.scala:87:24] wire out_f_roready_392 = out_roready_1_246 & out_romask_392; // @[RegisterRouter.scala:87:24] wire _out_T_4174 = out_f_roready_392; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_392 = out_wivalid_1_246 & out_wimask_392; // @[RegisterRouter.scala:87:24] wire out_f_woready_392 = out_woready_1_246 & out_womask_392; // @[RegisterRouter.scala:87:24] wire _out_T_4175 = ~out_rimask_392; // @[RegisterRouter.scala:87:24] wire _out_T_4176 = ~out_wimask_392; // @[RegisterRouter.scala:87:24] wire _out_T_4177 = ~out_romask_392; // @[RegisterRouter.scala:87:24] wire _out_T_4178 = ~out_womask_392; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_327 = {hi_39, flags_0_go, _out_prepend_T_327}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4179 = out_prepend_327; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4180 = _out_T_4179; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_328 = _out_T_4180; // @[RegisterRouter.scala:87:24] wire out_rimask_393 = |_out_rimask_T_393; // @[RegisterRouter.scala:87:24] wire out_wimask_393 = &_out_wimask_T_393; // @[RegisterRouter.scala:87:24] wire out_romask_393 = |_out_romask_T_393; // @[RegisterRouter.scala:87:24] wire out_womask_393 = &_out_womask_T_393; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_393 = out_rivalid_1_247 & out_rimask_393; // @[RegisterRouter.scala:87:24] wire _out_T_4182 = out_f_rivalid_393; // @[RegisterRouter.scala:87:24] wire out_f_roready_393 = out_roready_1_247 & out_romask_393; // @[RegisterRouter.scala:87:24] wire _out_T_4183 = out_f_roready_393; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_393 = out_wivalid_1_247 & out_wimask_393; // @[RegisterRouter.scala:87:24] wire out_f_woready_393 = out_woready_1_247 & out_womask_393; // @[RegisterRouter.scala:87:24] wire _out_T_4184 = ~out_rimask_393; // @[RegisterRouter.scala:87:24] wire _out_T_4185 = ~out_wimask_393; // @[RegisterRouter.scala:87:24] wire _out_T_4186 = ~out_romask_393; // @[RegisterRouter.scala:87:24] wire _out_T_4187 = ~out_womask_393; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_328 = {hi_40, flags_0_go, _out_prepend_T_328}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4188 = out_prepend_328; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4189 = _out_T_4188; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_132 = _out_T_4189; // @[MuxLiteral.scala:49:48] wire out_rimask_394 = |_out_rimask_T_394; // @[RegisterRouter.scala:87:24] wire out_wimask_394 = &_out_wimask_T_394; // @[RegisterRouter.scala:87:24] wire out_romask_394 = |_out_romask_T_394; // @[RegisterRouter.scala:87:24] wire out_womask_394 = &_out_womask_T_394; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_394 = out_rivalid_1_248 & out_rimask_394; // @[RegisterRouter.scala:87:24] wire _out_T_4191 = out_f_rivalid_394; // @[RegisterRouter.scala:87:24] wire out_f_roready_394 = out_roready_1_248 & out_romask_394; // @[RegisterRouter.scala:87:24] wire _out_T_4192 = out_f_roready_394; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_394 = out_wivalid_1_248 & out_wimask_394; // @[RegisterRouter.scala:87:24] wire out_f_woready_394 = out_woready_1_248 & out_womask_394; // @[RegisterRouter.scala:87:24] wire _out_T_4193 = ~out_rimask_394; // @[RegisterRouter.scala:87:24] wire _out_T_4194 = ~out_wimask_394; // @[RegisterRouter.scala:87:24] wire _out_T_4195 = ~out_romask_394; // @[RegisterRouter.scala:87:24] wire _out_T_4196 = ~out_womask_394; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4198 = _out_T_4197; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_329 = _out_T_4198; // @[RegisterRouter.scala:87:24] wire out_rimask_395 = |_out_rimask_T_395; // @[RegisterRouter.scala:87:24] wire out_wimask_395 = &_out_wimask_T_395; // @[RegisterRouter.scala:87:24] wire out_romask_395 = |_out_romask_T_395; // @[RegisterRouter.scala:87:24] wire out_womask_395 = &_out_womask_T_395; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_395 = out_rivalid_1_249 & out_rimask_395; // @[RegisterRouter.scala:87:24] wire _out_T_4200 = out_f_rivalid_395; // @[RegisterRouter.scala:87:24] wire out_f_roready_395 = out_roready_1_249 & out_romask_395; // @[RegisterRouter.scala:87:24] wire _out_T_4201 = out_f_roready_395; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_395 = out_wivalid_1_249 & out_wimask_395; // @[RegisterRouter.scala:87:24] wire out_f_woready_395 = out_woready_1_249 & out_womask_395; // @[RegisterRouter.scala:87:24] wire _out_T_4202 = ~out_rimask_395; // @[RegisterRouter.scala:87:24] wire _out_T_4203 = ~out_wimask_395; // @[RegisterRouter.scala:87:24] wire _out_T_4204 = ~out_romask_395; // @[RegisterRouter.scala:87:24] wire _out_T_4205 = ~out_womask_395; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_329 = {hi_42, flags_0_go, _out_prepend_T_329}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4206 = out_prepend_329; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4207 = _out_T_4206; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_330 = _out_T_4207; // @[RegisterRouter.scala:87:24] wire out_rimask_396 = |_out_rimask_T_396; // @[RegisterRouter.scala:87:24] wire out_wimask_396 = &_out_wimask_T_396; // @[RegisterRouter.scala:87:24] wire out_romask_396 = |_out_romask_T_396; // @[RegisterRouter.scala:87:24] wire out_womask_396 = &_out_womask_T_396; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_396 = out_rivalid_1_250 & out_rimask_396; // @[RegisterRouter.scala:87:24] wire _out_T_4209 = out_f_rivalid_396; // @[RegisterRouter.scala:87:24] wire out_f_roready_396 = out_roready_1_250 & out_romask_396; // @[RegisterRouter.scala:87:24] wire _out_T_4210 = out_f_roready_396; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_396 = out_wivalid_1_250 & out_wimask_396; // @[RegisterRouter.scala:87:24] wire out_f_woready_396 = out_woready_1_250 & out_womask_396; // @[RegisterRouter.scala:87:24] wire _out_T_4211 = ~out_rimask_396; // @[RegisterRouter.scala:87:24] wire _out_T_4212 = ~out_wimask_396; // @[RegisterRouter.scala:87:24] wire _out_T_4213 = ~out_romask_396; // @[RegisterRouter.scala:87:24] wire _out_T_4214 = ~out_womask_396; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_330 = {hi_43, flags_0_go, _out_prepend_T_330}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4215 = out_prepend_330; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4216 = _out_T_4215; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_331 = _out_T_4216; // @[RegisterRouter.scala:87:24] wire out_rimask_397 = |_out_rimask_T_397; // @[RegisterRouter.scala:87:24] wire out_wimask_397 = &_out_wimask_T_397; // @[RegisterRouter.scala:87:24] wire out_romask_397 = |_out_romask_T_397; // @[RegisterRouter.scala:87:24] wire out_womask_397 = &_out_womask_T_397; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_397 = out_rivalid_1_251 & out_rimask_397; // @[RegisterRouter.scala:87:24] wire _out_T_4218 = out_f_rivalid_397; // @[RegisterRouter.scala:87:24] wire out_f_roready_397 = out_roready_1_251 & out_romask_397; // @[RegisterRouter.scala:87:24] wire _out_T_4219 = out_f_roready_397; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_397 = out_wivalid_1_251 & out_wimask_397; // @[RegisterRouter.scala:87:24] wire out_f_woready_397 = out_woready_1_251 & out_womask_397; // @[RegisterRouter.scala:87:24] wire _out_T_4220 = ~out_rimask_397; // @[RegisterRouter.scala:87:24] wire _out_T_4221 = ~out_wimask_397; // @[RegisterRouter.scala:87:24] wire _out_T_4222 = ~out_romask_397; // @[RegisterRouter.scala:87:24] wire _out_T_4223 = ~out_womask_397; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_331 = {hi_44, flags_0_go, _out_prepend_T_331}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4224 = out_prepend_331; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4225 = _out_T_4224; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_332 = _out_T_4225; // @[RegisterRouter.scala:87:24] wire out_rimask_398 = |_out_rimask_T_398; // @[RegisterRouter.scala:87:24] wire out_wimask_398 = &_out_wimask_T_398; // @[RegisterRouter.scala:87:24] wire out_romask_398 = |_out_romask_T_398; // @[RegisterRouter.scala:87:24] wire out_womask_398 = &_out_womask_T_398; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_398 = out_rivalid_1_252 & out_rimask_398; // @[RegisterRouter.scala:87:24] wire _out_T_4227 = out_f_rivalid_398; // @[RegisterRouter.scala:87:24] wire out_f_roready_398 = out_roready_1_252 & out_romask_398; // @[RegisterRouter.scala:87:24] wire _out_T_4228 = out_f_roready_398; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_398 = out_wivalid_1_252 & out_wimask_398; // @[RegisterRouter.scala:87:24] wire out_f_woready_398 = out_woready_1_252 & out_womask_398; // @[RegisterRouter.scala:87:24] wire _out_T_4229 = ~out_rimask_398; // @[RegisterRouter.scala:87:24] wire _out_T_4230 = ~out_wimask_398; // @[RegisterRouter.scala:87:24] wire _out_T_4231 = ~out_romask_398; // @[RegisterRouter.scala:87:24] wire _out_T_4232 = ~out_womask_398; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_332 = {hi_45, flags_0_go, _out_prepend_T_332}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4233 = out_prepend_332; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4234 = _out_T_4233; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_333 = _out_T_4234; // @[RegisterRouter.scala:87:24] wire out_rimask_399 = |_out_rimask_T_399; // @[RegisterRouter.scala:87:24] wire out_wimask_399 = &_out_wimask_T_399; // @[RegisterRouter.scala:87:24] wire out_romask_399 = |_out_romask_T_399; // @[RegisterRouter.scala:87:24] wire out_womask_399 = &_out_womask_T_399; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_399 = out_rivalid_1_253 & out_rimask_399; // @[RegisterRouter.scala:87:24] wire _out_T_4236 = out_f_rivalid_399; // @[RegisterRouter.scala:87:24] wire out_f_roready_399 = out_roready_1_253 & out_romask_399; // @[RegisterRouter.scala:87:24] wire _out_T_4237 = out_f_roready_399; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_399 = out_wivalid_1_253 & out_wimask_399; // @[RegisterRouter.scala:87:24] wire out_f_woready_399 = out_woready_1_253 & out_womask_399; // @[RegisterRouter.scala:87:24] wire _out_T_4238 = ~out_rimask_399; // @[RegisterRouter.scala:87:24] wire _out_T_4239 = ~out_wimask_399; // @[RegisterRouter.scala:87:24] wire _out_T_4240 = ~out_romask_399; // @[RegisterRouter.scala:87:24] wire _out_T_4241 = ~out_womask_399; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_333 = {hi_46, flags_0_go, _out_prepend_T_333}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4242 = out_prepend_333; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4243 = _out_T_4242; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_334 = _out_T_4243; // @[RegisterRouter.scala:87:24] wire out_rimask_400 = |_out_rimask_T_400; // @[RegisterRouter.scala:87:24] wire out_wimask_400 = &_out_wimask_T_400; // @[RegisterRouter.scala:87:24] wire out_romask_400 = |_out_romask_T_400; // @[RegisterRouter.scala:87:24] wire out_womask_400 = &_out_womask_T_400; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_400 = out_rivalid_1_254 & out_rimask_400; // @[RegisterRouter.scala:87:24] wire _out_T_4245 = out_f_rivalid_400; // @[RegisterRouter.scala:87:24] wire out_f_roready_400 = out_roready_1_254 & out_romask_400; // @[RegisterRouter.scala:87:24] wire _out_T_4246 = out_f_roready_400; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_400 = out_wivalid_1_254 & out_wimask_400; // @[RegisterRouter.scala:87:24] wire out_f_woready_400 = out_woready_1_254 & out_womask_400; // @[RegisterRouter.scala:87:24] wire _out_T_4247 = ~out_rimask_400; // @[RegisterRouter.scala:87:24] wire _out_T_4248 = ~out_wimask_400; // @[RegisterRouter.scala:87:24] wire _out_T_4249 = ~out_romask_400; // @[RegisterRouter.scala:87:24] wire _out_T_4250 = ~out_womask_400; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_334 = {hi_47, flags_0_go, _out_prepend_T_334}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4251 = out_prepend_334; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4252 = _out_T_4251; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_335 = _out_T_4252; // @[RegisterRouter.scala:87:24] wire out_rimask_401 = |_out_rimask_T_401; // @[RegisterRouter.scala:87:24] wire out_wimask_401 = &_out_wimask_T_401; // @[RegisterRouter.scala:87:24] wire out_romask_401 = |_out_romask_T_401; // @[RegisterRouter.scala:87:24] wire out_womask_401 = &_out_womask_T_401; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_401 = out_rivalid_1_255 & out_rimask_401; // @[RegisterRouter.scala:87:24] wire _out_T_4254 = out_f_rivalid_401; // @[RegisterRouter.scala:87:24] wire out_f_roready_401 = out_roready_1_255 & out_romask_401; // @[RegisterRouter.scala:87:24] wire _out_T_4255 = out_f_roready_401; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_401 = out_wivalid_1_255 & out_wimask_401; // @[RegisterRouter.scala:87:24] wire out_f_woready_401 = out_woready_1_255 & out_womask_401; // @[RegisterRouter.scala:87:24] wire _out_T_4256 = ~out_rimask_401; // @[RegisterRouter.scala:87:24] wire _out_T_4257 = ~out_wimask_401; // @[RegisterRouter.scala:87:24] wire _out_T_4258 = ~out_romask_401; // @[RegisterRouter.scala:87:24] wire _out_T_4259 = ~out_womask_401; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_335 = {hi_48, flags_0_go, _out_prepend_T_335}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4260 = out_prepend_335; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4261 = _out_T_4260; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_133 = _out_T_4261; // @[MuxLiteral.scala:49:48] wire out_rimask_402 = |_out_rimask_T_402; // @[RegisterRouter.scala:87:24] wire out_wimask_402 = &_out_wimask_T_402; // @[RegisterRouter.scala:87:24] wire out_romask_402 = |_out_romask_T_402; // @[RegisterRouter.scala:87:24] wire out_womask_402 = &_out_womask_T_402; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_402 = out_rivalid_1_256 & out_rimask_402; // @[RegisterRouter.scala:87:24] wire _out_T_4263 = out_f_rivalid_402; // @[RegisterRouter.scala:87:24] wire out_f_roready_402 = out_roready_1_256 & out_romask_402; // @[RegisterRouter.scala:87:24] wire _out_T_4264 = out_f_roready_402; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_402 = out_wivalid_1_256 & out_wimask_402; // @[RegisterRouter.scala:87:24] wire out_f_woready_402 = out_woready_1_256 & out_womask_402; // @[RegisterRouter.scala:87:24] wire _out_T_4265 = ~out_rimask_402; // @[RegisterRouter.scala:87:24] wire _out_T_4266 = ~out_wimask_402; // @[RegisterRouter.scala:87:24] wire _out_T_4267 = ~out_romask_402; // @[RegisterRouter.scala:87:24] wire _out_T_4268 = ~out_womask_402; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4270 = _out_T_4269; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_336 = _out_T_4270; // @[RegisterRouter.scala:87:24] wire out_rimask_403 = |_out_rimask_T_403; // @[RegisterRouter.scala:87:24] wire out_wimask_403 = &_out_wimask_T_403; // @[RegisterRouter.scala:87:24] wire out_romask_403 = |_out_romask_T_403; // @[RegisterRouter.scala:87:24] wire out_womask_403 = &_out_womask_T_403; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_403 = out_rivalid_1_257 & out_rimask_403; // @[RegisterRouter.scala:87:24] wire _out_T_4272 = out_f_rivalid_403; // @[RegisterRouter.scala:87:24] wire out_f_roready_403 = out_roready_1_257 & out_romask_403; // @[RegisterRouter.scala:87:24] wire _out_T_4273 = out_f_roready_403; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_403 = out_wivalid_1_257 & out_wimask_403; // @[RegisterRouter.scala:87:24] wire out_f_woready_403 = out_woready_1_257 & out_womask_403; // @[RegisterRouter.scala:87:24] wire _out_T_4274 = ~out_rimask_403; // @[RegisterRouter.scala:87:24] wire _out_T_4275 = ~out_wimask_403; // @[RegisterRouter.scala:87:24] wire _out_T_4276 = ~out_romask_403; // @[RegisterRouter.scala:87:24] wire _out_T_4277 = ~out_womask_403; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_336 = {hi_922, flags_0_go, _out_prepend_T_336}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4278 = out_prepend_336; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4279 = _out_T_4278; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_337 = _out_T_4279; // @[RegisterRouter.scala:87:24] wire out_rimask_404 = |_out_rimask_T_404; // @[RegisterRouter.scala:87:24] wire out_wimask_404 = &_out_wimask_T_404; // @[RegisterRouter.scala:87:24] wire out_romask_404 = |_out_romask_T_404; // @[RegisterRouter.scala:87:24] wire out_womask_404 = &_out_womask_T_404; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_404 = out_rivalid_1_258 & out_rimask_404; // @[RegisterRouter.scala:87:24] wire _out_T_4281 = out_f_rivalid_404; // @[RegisterRouter.scala:87:24] wire out_f_roready_404 = out_roready_1_258 & out_romask_404; // @[RegisterRouter.scala:87:24] wire _out_T_4282 = out_f_roready_404; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_404 = out_wivalid_1_258 & out_wimask_404; // @[RegisterRouter.scala:87:24] wire out_f_woready_404 = out_woready_1_258 & out_womask_404; // @[RegisterRouter.scala:87:24] wire _out_T_4283 = ~out_rimask_404; // @[RegisterRouter.scala:87:24] wire _out_T_4284 = ~out_wimask_404; // @[RegisterRouter.scala:87:24] wire _out_T_4285 = ~out_romask_404; // @[RegisterRouter.scala:87:24] wire _out_T_4286 = ~out_womask_404; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_337 = {hi_923, flags_0_go, _out_prepend_T_337}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4287 = out_prepend_337; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4288 = _out_T_4287; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_338 = _out_T_4288; // @[RegisterRouter.scala:87:24] wire out_rimask_405 = |_out_rimask_T_405; // @[RegisterRouter.scala:87:24] wire out_wimask_405 = &_out_wimask_T_405; // @[RegisterRouter.scala:87:24] wire out_romask_405 = |_out_romask_T_405; // @[RegisterRouter.scala:87:24] wire out_womask_405 = &_out_womask_T_405; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_405 = out_rivalid_1_259 & out_rimask_405; // @[RegisterRouter.scala:87:24] wire _out_T_4290 = out_f_rivalid_405; // @[RegisterRouter.scala:87:24] wire out_f_roready_405 = out_roready_1_259 & out_romask_405; // @[RegisterRouter.scala:87:24] wire _out_T_4291 = out_f_roready_405; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_405 = out_wivalid_1_259 & out_wimask_405; // @[RegisterRouter.scala:87:24] wire out_f_woready_405 = out_woready_1_259 & out_womask_405; // @[RegisterRouter.scala:87:24] wire _out_T_4292 = ~out_rimask_405; // @[RegisterRouter.scala:87:24] wire _out_T_4293 = ~out_wimask_405; // @[RegisterRouter.scala:87:24] wire _out_T_4294 = ~out_romask_405; // @[RegisterRouter.scala:87:24] wire _out_T_4295 = ~out_womask_405; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_338 = {hi_924, flags_0_go, _out_prepend_T_338}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4296 = out_prepend_338; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4297 = _out_T_4296; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_339 = _out_T_4297; // @[RegisterRouter.scala:87:24] wire out_rimask_406 = |_out_rimask_T_406; // @[RegisterRouter.scala:87:24] wire out_wimask_406 = &_out_wimask_T_406; // @[RegisterRouter.scala:87:24] wire out_romask_406 = |_out_romask_T_406; // @[RegisterRouter.scala:87:24] wire out_womask_406 = &_out_womask_T_406; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_406 = out_rivalid_1_260 & out_rimask_406; // @[RegisterRouter.scala:87:24] wire _out_T_4299 = out_f_rivalid_406; // @[RegisterRouter.scala:87:24] wire out_f_roready_406 = out_roready_1_260 & out_romask_406; // @[RegisterRouter.scala:87:24] wire _out_T_4300 = out_f_roready_406; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_406 = out_wivalid_1_260 & out_wimask_406; // @[RegisterRouter.scala:87:24] wire out_f_woready_406 = out_woready_1_260 & out_womask_406; // @[RegisterRouter.scala:87:24] wire _out_T_4301 = ~out_rimask_406; // @[RegisterRouter.scala:87:24] wire _out_T_4302 = ~out_wimask_406; // @[RegisterRouter.scala:87:24] wire _out_T_4303 = ~out_romask_406; // @[RegisterRouter.scala:87:24] wire _out_T_4304 = ~out_womask_406; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_339 = {hi_925, flags_0_go, _out_prepend_T_339}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4305 = out_prepend_339; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4306 = _out_T_4305; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_340 = _out_T_4306; // @[RegisterRouter.scala:87:24] wire out_rimask_407 = |_out_rimask_T_407; // @[RegisterRouter.scala:87:24] wire out_wimask_407 = &_out_wimask_T_407; // @[RegisterRouter.scala:87:24] wire out_romask_407 = |_out_romask_T_407; // @[RegisterRouter.scala:87:24] wire out_womask_407 = &_out_womask_T_407; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_407 = out_rivalid_1_261 & out_rimask_407; // @[RegisterRouter.scala:87:24] wire _out_T_4308 = out_f_rivalid_407; // @[RegisterRouter.scala:87:24] wire out_f_roready_407 = out_roready_1_261 & out_romask_407; // @[RegisterRouter.scala:87:24] wire _out_T_4309 = out_f_roready_407; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_407 = out_wivalid_1_261 & out_wimask_407; // @[RegisterRouter.scala:87:24] wire out_f_woready_407 = out_woready_1_261 & out_womask_407; // @[RegisterRouter.scala:87:24] wire _out_T_4310 = ~out_rimask_407; // @[RegisterRouter.scala:87:24] wire _out_T_4311 = ~out_wimask_407; // @[RegisterRouter.scala:87:24] wire _out_T_4312 = ~out_romask_407; // @[RegisterRouter.scala:87:24] wire _out_T_4313 = ~out_womask_407; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_340 = {hi_926, flags_0_go, _out_prepend_T_340}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4314 = out_prepend_340; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4315 = _out_T_4314; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_341 = _out_T_4315; // @[RegisterRouter.scala:87:24] wire out_rimask_408 = |_out_rimask_T_408; // @[RegisterRouter.scala:87:24] wire out_wimask_408 = &_out_wimask_T_408; // @[RegisterRouter.scala:87:24] wire out_romask_408 = |_out_romask_T_408; // @[RegisterRouter.scala:87:24] wire out_womask_408 = &_out_womask_T_408; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_408 = out_rivalid_1_262 & out_rimask_408; // @[RegisterRouter.scala:87:24] wire _out_T_4317 = out_f_rivalid_408; // @[RegisterRouter.scala:87:24] wire out_f_roready_408 = out_roready_1_262 & out_romask_408; // @[RegisterRouter.scala:87:24] wire _out_T_4318 = out_f_roready_408; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_408 = out_wivalid_1_262 & out_wimask_408; // @[RegisterRouter.scala:87:24] wire out_f_woready_408 = out_woready_1_262 & out_womask_408; // @[RegisterRouter.scala:87:24] wire _out_T_4319 = ~out_rimask_408; // @[RegisterRouter.scala:87:24] wire _out_T_4320 = ~out_wimask_408; // @[RegisterRouter.scala:87:24] wire _out_T_4321 = ~out_romask_408; // @[RegisterRouter.scala:87:24] wire _out_T_4322 = ~out_womask_408; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_341 = {hi_927, flags_0_go, _out_prepend_T_341}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4323 = out_prepend_341; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4324 = _out_T_4323; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_342 = _out_T_4324; // @[RegisterRouter.scala:87:24] wire out_rimask_409 = |_out_rimask_T_409; // @[RegisterRouter.scala:87:24] wire out_wimask_409 = &_out_wimask_T_409; // @[RegisterRouter.scala:87:24] wire out_romask_409 = |_out_romask_T_409; // @[RegisterRouter.scala:87:24] wire out_womask_409 = &_out_womask_T_409; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_409 = out_rivalid_1_263 & out_rimask_409; // @[RegisterRouter.scala:87:24] wire _out_T_4326 = out_f_rivalid_409; // @[RegisterRouter.scala:87:24] wire out_f_roready_409 = out_roready_1_263 & out_romask_409; // @[RegisterRouter.scala:87:24] wire _out_T_4327 = out_f_roready_409; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_409 = out_wivalid_1_263 & out_wimask_409; // @[RegisterRouter.scala:87:24] wire out_f_woready_409 = out_woready_1_263 & out_womask_409; // @[RegisterRouter.scala:87:24] wire _out_T_4328 = ~out_rimask_409; // @[RegisterRouter.scala:87:24] wire _out_T_4329 = ~out_wimask_409; // @[RegisterRouter.scala:87:24] wire _out_T_4330 = ~out_romask_409; // @[RegisterRouter.scala:87:24] wire _out_T_4331 = ~out_womask_409; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_342 = {hi_928, flags_0_go, _out_prepend_T_342}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4332 = out_prepend_342; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4333 = _out_T_4332; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_243 = _out_T_4333; // @[MuxLiteral.scala:49:48] wire out_rimask_410 = |_out_rimask_T_410; // @[RegisterRouter.scala:87:24] wire out_wimask_410 = &_out_wimask_T_410; // @[RegisterRouter.scala:87:24] wire out_romask_410 = |_out_romask_T_410; // @[RegisterRouter.scala:87:24] wire out_womask_410 = &_out_womask_T_410; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_410 = out_rivalid_1_264 & out_rimask_410; // @[RegisterRouter.scala:87:24] wire _out_T_4335 = out_f_rivalid_410; // @[RegisterRouter.scala:87:24] wire out_f_roready_410 = out_roready_1_264 & out_romask_410; // @[RegisterRouter.scala:87:24] wire _out_T_4336 = out_f_roready_410; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_410 = out_wivalid_1_264 & out_wimask_410; // @[RegisterRouter.scala:87:24] wire out_f_woready_410 = out_woready_1_264 & out_womask_410; // @[RegisterRouter.scala:87:24] wire _out_T_4337 = ~out_rimask_410; // @[RegisterRouter.scala:87:24] wire _out_T_4338 = ~out_wimask_410; // @[RegisterRouter.scala:87:24] wire _out_T_4339 = ~out_romask_410; // @[RegisterRouter.scala:87:24] wire _out_T_4340 = ~out_womask_410; // @[RegisterRouter.scala:87:24] wire out_rimask_411 = |_out_rimask_T_411; // @[RegisterRouter.scala:87:24] wire out_wimask_411 = &_out_wimask_T_411; // @[RegisterRouter.scala:87:24] wire out_romask_411 = |_out_romask_T_411; // @[RegisterRouter.scala:87:24] wire out_womask_411 = &_out_womask_T_411; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_411 = out_rivalid_1_265 & out_rimask_411; // @[RegisterRouter.scala:87:24] wire _out_T_4344 = out_f_rivalid_411; // @[RegisterRouter.scala:87:24] wire out_f_roready_411 = out_roready_1_265 & out_romask_411; // @[RegisterRouter.scala:87:24] wire _out_T_4345 = out_f_roready_411; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_411 = out_wivalid_1_265 & out_wimask_411; // @[RegisterRouter.scala:87:24] wire out_f_woready_411 = out_woready_1_265 & out_womask_411; // @[RegisterRouter.scala:87:24] wire _out_T_4346 = ~out_rimask_411; // @[RegisterRouter.scala:87:24] wire _out_T_4347 = ~out_wimask_411; // @[RegisterRouter.scala:87:24] wire _out_T_4348 = ~out_romask_411; // @[RegisterRouter.scala:87:24] wire _out_T_4349 = ~out_womask_411; // @[RegisterRouter.scala:87:24] wire out_rimask_412 = |_out_rimask_T_412; // @[RegisterRouter.scala:87:24] wire out_wimask_412 = &_out_wimask_T_412; // @[RegisterRouter.scala:87:24] wire out_romask_412 = |_out_romask_T_412; // @[RegisterRouter.scala:87:24] wire out_womask_412 = &_out_womask_T_412; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_412 = out_rivalid_1_266 & out_rimask_412; // @[RegisterRouter.scala:87:24] wire _out_T_4353 = out_f_rivalid_412; // @[RegisterRouter.scala:87:24] wire out_f_roready_412 = out_roready_1_266 & out_romask_412; // @[RegisterRouter.scala:87:24] wire _out_T_4354 = out_f_roready_412; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_412 = out_wivalid_1_266 & out_wimask_412; // @[RegisterRouter.scala:87:24] wire out_f_woready_412 = out_woready_1_266 & out_womask_412; // @[RegisterRouter.scala:87:24] wire _out_T_4355 = ~out_rimask_412; // @[RegisterRouter.scala:87:24] wire _out_T_4356 = ~out_wimask_412; // @[RegisterRouter.scala:87:24] wire _out_T_4357 = ~out_romask_412; // @[RegisterRouter.scala:87:24] wire _out_T_4358 = ~out_womask_412; // @[RegisterRouter.scala:87:24] wire out_rimask_413 = |_out_rimask_T_413; // @[RegisterRouter.scala:87:24] wire out_wimask_413 = &_out_wimask_T_413; // @[RegisterRouter.scala:87:24] wire out_romask_413 = |_out_romask_T_413; // @[RegisterRouter.scala:87:24] wire out_womask_413 = &_out_womask_T_413; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_413 = out_rivalid_1_267 & out_rimask_413; // @[RegisterRouter.scala:87:24] wire _out_T_4362 = out_f_rivalid_413; // @[RegisterRouter.scala:87:24] wire out_f_roready_413 = out_roready_1_267 & out_romask_413; // @[RegisterRouter.scala:87:24] wire _out_T_4363 = out_f_roready_413; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_413 = out_wivalid_1_267 & out_wimask_413; // @[RegisterRouter.scala:87:24] wire out_f_woready_413 = out_woready_1_267 & out_womask_413; // @[RegisterRouter.scala:87:24] wire _out_T_4364 = ~out_rimask_413; // @[RegisterRouter.scala:87:24] wire _out_T_4365 = ~out_wimask_413; // @[RegisterRouter.scala:87:24] wire _out_T_4366 = ~out_romask_413; // @[RegisterRouter.scala:87:24] wire _out_T_4367 = ~out_womask_413; // @[RegisterRouter.scala:87:24] wire out_rimask_414 = |_out_rimask_T_414; // @[RegisterRouter.scala:87:24] wire out_wimask_414 = &_out_wimask_T_414; // @[RegisterRouter.scala:87:24] wire out_romask_414 = |_out_romask_T_414; // @[RegisterRouter.scala:87:24] wire out_womask_414 = &_out_womask_T_414; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_414 = out_rivalid_1_268 & out_rimask_414; // @[RegisterRouter.scala:87:24] wire _out_T_4371 = out_f_rivalid_414; // @[RegisterRouter.scala:87:24] wire out_f_roready_414 = out_roready_1_268 & out_romask_414; // @[RegisterRouter.scala:87:24] wire _out_T_4372 = out_f_roready_414; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_414 = out_wivalid_1_268 & out_wimask_414; // @[RegisterRouter.scala:87:24] wire out_f_woready_414 = out_woready_1_268 & out_womask_414; // @[RegisterRouter.scala:87:24] wire _out_T_4373 = ~out_rimask_414; // @[RegisterRouter.scala:87:24] wire _out_T_4374 = ~out_wimask_414; // @[RegisterRouter.scala:87:24] wire _out_T_4375 = ~out_romask_414; // @[RegisterRouter.scala:87:24] wire _out_T_4376 = ~out_womask_414; // @[RegisterRouter.scala:87:24] wire out_rimask_415 = |_out_rimask_T_415; // @[RegisterRouter.scala:87:24] wire out_wimask_415 = &_out_wimask_T_415; // @[RegisterRouter.scala:87:24] wire out_romask_415 = |_out_romask_T_415; // @[RegisterRouter.scala:87:24] wire out_womask_415 = &_out_womask_T_415; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_415 = out_rivalid_1_269 & out_rimask_415; // @[RegisterRouter.scala:87:24] wire _out_T_4380 = out_f_rivalid_415; // @[RegisterRouter.scala:87:24] wire out_f_roready_415 = out_roready_1_269 & out_romask_415; // @[RegisterRouter.scala:87:24] wire _out_T_4381 = out_f_roready_415; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_415 = out_wivalid_1_269 & out_wimask_415; // @[RegisterRouter.scala:87:24] wire out_f_woready_415 = out_woready_1_269 & out_womask_415; // @[RegisterRouter.scala:87:24] wire _out_T_4382 = ~out_rimask_415; // @[RegisterRouter.scala:87:24] wire _out_T_4383 = ~out_wimask_415; // @[RegisterRouter.scala:87:24] wire _out_T_4384 = ~out_romask_415; // @[RegisterRouter.scala:87:24] wire _out_T_4385 = ~out_womask_415; // @[RegisterRouter.scala:87:24] wire out_rimask_416 = |_out_rimask_T_416; // @[RegisterRouter.scala:87:24] wire out_wimask_416 = &_out_wimask_T_416; // @[RegisterRouter.scala:87:24] wire out_romask_416 = |_out_romask_T_416; // @[RegisterRouter.scala:87:24] wire out_womask_416 = &_out_womask_T_416; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_416 = out_rivalid_1_270 & out_rimask_416; // @[RegisterRouter.scala:87:24] wire _out_T_4389 = out_f_rivalid_416; // @[RegisterRouter.scala:87:24] wire out_f_roready_416 = out_roready_1_270 & out_romask_416; // @[RegisterRouter.scala:87:24] wire _out_T_4390 = out_f_roready_416; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_416 = out_wivalid_1_270 & out_wimask_416; // @[RegisterRouter.scala:87:24] wire out_f_woready_416 = out_woready_1_270 & out_womask_416; // @[RegisterRouter.scala:87:24] wire _out_T_4391 = ~out_rimask_416; // @[RegisterRouter.scala:87:24] wire _out_T_4392 = ~out_wimask_416; // @[RegisterRouter.scala:87:24] wire _out_T_4393 = ~out_romask_416; // @[RegisterRouter.scala:87:24] wire _out_T_4394 = ~out_womask_416; // @[RegisterRouter.scala:87:24] wire out_rimask_417 = |_out_rimask_T_417; // @[RegisterRouter.scala:87:24] wire out_wimask_417 = &_out_wimask_T_417; // @[RegisterRouter.scala:87:24] wire out_romask_417 = |_out_romask_T_417; // @[RegisterRouter.scala:87:24] wire out_womask_417 = &_out_womask_T_417; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_417 = out_rivalid_1_271 & out_rimask_417; // @[RegisterRouter.scala:87:24] wire _out_T_4398 = out_f_rivalid_417; // @[RegisterRouter.scala:87:24] wire out_f_roready_417 = out_roready_1_271 & out_romask_417; // @[RegisterRouter.scala:87:24] wire _out_T_4399 = out_f_roready_417; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_417 = out_wivalid_1_271 & out_wimask_417; // @[RegisterRouter.scala:87:24] wire out_f_woready_417 = out_woready_1_271 & out_womask_417; // @[RegisterRouter.scala:87:24] wire _out_T_4400 = ~out_rimask_417; // @[RegisterRouter.scala:87:24] wire _out_T_4401 = ~out_wimask_417; // @[RegisterRouter.scala:87:24] wire _out_T_4402 = ~out_romask_417; // @[RegisterRouter.scala:87:24] wire _out_T_4403 = ~out_womask_417; // @[RegisterRouter.scala:87:24] wire out_rimask_418 = |_out_rimask_T_418; // @[RegisterRouter.scala:87:24] wire out_wimask_418 = &_out_wimask_T_418; // @[RegisterRouter.scala:87:24] wire out_romask_418 = |_out_romask_T_418; // @[RegisterRouter.scala:87:24] wire out_womask_418 = &_out_womask_T_418; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_418 = out_rivalid_1_272 & out_rimask_418; // @[RegisterRouter.scala:87:24] wire _out_T_4407 = out_f_rivalid_418; // @[RegisterRouter.scala:87:24] wire out_f_roready_418 = out_roready_1_272 & out_romask_418; // @[RegisterRouter.scala:87:24] wire _out_T_4408 = out_f_roready_418; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_418 = out_wivalid_1_272 & out_wimask_418; // @[RegisterRouter.scala:87:24] wire out_f_woready_418 = out_woready_1_272 & out_womask_418; // @[RegisterRouter.scala:87:24] wire _out_T_4409 = ~out_rimask_418; // @[RegisterRouter.scala:87:24] wire _out_T_4410 = ~out_wimask_418; // @[RegisterRouter.scala:87:24] wire _out_T_4411 = ~out_romask_418; // @[RegisterRouter.scala:87:24] wire _out_T_4412 = ~out_womask_418; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4414 = _out_T_4413; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_350 = _out_T_4414; // @[RegisterRouter.scala:87:24] wire out_rimask_419 = |_out_rimask_T_419; // @[RegisterRouter.scala:87:24] wire out_wimask_419 = &_out_wimask_T_419; // @[RegisterRouter.scala:87:24] wire out_romask_419 = |_out_romask_T_419; // @[RegisterRouter.scala:87:24] wire out_womask_419 = &_out_womask_T_419; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_419 = out_rivalid_1_273 & out_rimask_419; // @[RegisterRouter.scala:87:24] wire _out_T_4416 = out_f_rivalid_419; // @[RegisterRouter.scala:87:24] wire out_f_roready_419 = out_roready_1_273 & out_romask_419; // @[RegisterRouter.scala:87:24] wire _out_T_4417 = out_f_roready_419; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_419 = out_wivalid_1_273 & out_wimask_419; // @[RegisterRouter.scala:87:24] wire out_f_woready_419 = out_woready_1_273 & out_womask_419; // @[RegisterRouter.scala:87:24] wire _out_T_4418 = ~out_rimask_419; // @[RegisterRouter.scala:87:24] wire _out_T_4419 = ~out_wimask_419; // @[RegisterRouter.scala:87:24] wire _out_T_4420 = ~out_romask_419; // @[RegisterRouter.scala:87:24] wire _out_T_4421 = ~out_womask_419; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_350 = {hi_626, flags_0_go, _out_prepend_T_350}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4422 = out_prepend_350; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4423 = _out_T_4422; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_351 = _out_T_4423; // @[RegisterRouter.scala:87:24] wire out_rimask_420 = |_out_rimask_T_420; // @[RegisterRouter.scala:87:24] wire out_wimask_420 = &_out_wimask_T_420; // @[RegisterRouter.scala:87:24] wire out_romask_420 = |_out_romask_T_420; // @[RegisterRouter.scala:87:24] wire out_womask_420 = &_out_womask_T_420; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_420 = out_rivalid_1_274 & out_rimask_420; // @[RegisterRouter.scala:87:24] wire _out_T_4425 = out_f_rivalid_420; // @[RegisterRouter.scala:87:24] wire out_f_roready_420 = out_roready_1_274 & out_romask_420; // @[RegisterRouter.scala:87:24] wire _out_T_4426 = out_f_roready_420; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_420 = out_wivalid_1_274 & out_wimask_420; // @[RegisterRouter.scala:87:24] wire out_f_woready_420 = out_woready_1_274 & out_womask_420; // @[RegisterRouter.scala:87:24] wire _out_T_4427 = ~out_rimask_420; // @[RegisterRouter.scala:87:24] wire _out_T_4428 = ~out_wimask_420; // @[RegisterRouter.scala:87:24] wire _out_T_4429 = ~out_romask_420; // @[RegisterRouter.scala:87:24] wire _out_T_4430 = ~out_womask_420; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_351 = {hi_627, flags_0_go, _out_prepend_T_351}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4431 = out_prepend_351; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4432 = _out_T_4431; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_352 = _out_T_4432; // @[RegisterRouter.scala:87:24] wire out_rimask_421 = |_out_rimask_T_421; // @[RegisterRouter.scala:87:24] wire out_wimask_421 = &_out_wimask_T_421; // @[RegisterRouter.scala:87:24] wire out_romask_421 = |_out_romask_T_421; // @[RegisterRouter.scala:87:24] wire out_womask_421 = &_out_womask_T_421; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_421 = out_rivalid_1_275 & out_rimask_421; // @[RegisterRouter.scala:87:24] wire _out_T_4434 = out_f_rivalid_421; // @[RegisterRouter.scala:87:24] wire out_f_roready_421 = out_roready_1_275 & out_romask_421; // @[RegisterRouter.scala:87:24] wire _out_T_4435 = out_f_roready_421; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_421 = out_wivalid_1_275 & out_wimask_421; // @[RegisterRouter.scala:87:24] wire out_f_woready_421 = out_woready_1_275 & out_womask_421; // @[RegisterRouter.scala:87:24] wire _out_T_4436 = ~out_rimask_421; // @[RegisterRouter.scala:87:24] wire _out_T_4437 = ~out_wimask_421; // @[RegisterRouter.scala:87:24] wire _out_T_4438 = ~out_romask_421; // @[RegisterRouter.scala:87:24] wire _out_T_4439 = ~out_womask_421; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_352 = {hi_628, flags_0_go, _out_prepend_T_352}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4440 = out_prepend_352; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4441 = _out_T_4440; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_353 = _out_T_4441; // @[RegisterRouter.scala:87:24] wire out_rimask_422 = |_out_rimask_T_422; // @[RegisterRouter.scala:87:24] wire out_wimask_422 = &_out_wimask_T_422; // @[RegisterRouter.scala:87:24] wire out_romask_422 = |_out_romask_T_422; // @[RegisterRouter.scala:87:24] wire out_womask_422 = &_out_womask_T_422; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_422 = out_rivalid_1_276 & out_rimask_422; // @[RegisterRouter.scala:87:24] wire _out_T_4443 = out_f_rivalid_422; // @[RegisterRouter.scala:87:24] wire out_f_roready_422 = out_roready_1_276 & out_romask_422; // @[RegisterRouter.scala:87:24] wire _out_T_4444 = out_f_roready_422; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_422 = out_wivalid_1_276 & out_wimask_422; // @[RegisterRouter.scala:87:24] wire out_f_woready_422 = out_woready_1_276 & out_womask_422; // @[RegisterRouter.scala:87:24] wire _out_T_4445 = ~out_rimask_422; // @[RegisterRouter.scala:87:24] wire _out_T_4446 = ~out_wimask_422; // @[RegisterRouter.scala:87:24] wire _out_T_4447 = ~out_romask_422; // @[RegisterRouter.scala:87:24] wire _out_T_4448 = ~out_womask_422; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_353 = {hi_629, flags_0_go, _out_prepend_T_353}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4449 = out_prepend_353; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4450 = _out_T_4449; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_354 = _out_T_4450; // @[RegisterRouter.scala:87:24] wire out_rimask_423 = |_out_rimask_T_423; // @[RegisterRouter.scala:87:24] wire out_wimask_423 = &_out_wimask_T_423; // @[RegisterRouter.scala:87:24] wire out_romask_423 = |_out_romask_T_423; // @[RegisterRouter.scala:87:24] wire out_womask_423 = &_out_womask_T_423; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_423 = out_rivalid_1_277 & out_rimask_423; // @[RegisterRouter.scala:87:24] wire _out_T_4452 = out_f_rivalid_423; // @[RegisterRouter.scala:87:24] wire out_f_roready_423 = out_roready_1_277 & out_romask_423; // @[RegisterRouter.scala:87:24] wire _out_T_4453 = out_f_roready_423; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_423 = out_wivalid_1_277 & out_wimask_423; // @[RegisterRouter.scala:87:24] wire out_f_woready_423 = out_woready_1_277 & out_womask_423; // @[RegisterRouter.scala:87:24] wire _out_T_4454 = ~out_rimask_423; // @[RegisterRouter.scala:87:24] wire _out_T_4455 = ~out_wimask_423; // @[RegisterRouter.scala:87:24] wire _out_T_4456 = ~out_romask_423; // @[RegisterRouter.scala:87:24] wire _out_T_4457 = ~out_womask_423; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_354 = {hi_630, flags_0_go, _out_prepend_T_354}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4458 = out_prepend_354; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4459 = _out_T_4458; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_355 = _out_T_4459; // @[RegisterRouter.scala:87:24] wire out_rimask_424 = |_out_rimask_T_424; // @[RegisterRouter.scala:87:24] wire out_wimask_424 = &_out_wimask_T_424; // @[RegisterRouter.scala:87:24] wire out_romask_424 = |_out_romask_T_424; // @[RegisterRouter.scala:87:24] wire out_womask_424 = &_out_womask_T_424; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_424 = out_rivalid_1_278 & out_rimask_424; // @[RegisterRouter.scala:87:24] wire _out_T_4461 = out_f_rivalid_424; // @[RegisterRouter.scala:87:24] wire out_f_roready_424 = out_roready_1_278 & out_romask_424; // @[RegisterRouter.scala:87:24] wire _out_T_4462 = out_f_roready_424; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_424 = out_wivalid_1_278 & out_wimask_424; // @[RegisterRouter.scala:87:24] wire out_f_woready_424 = out_woready_1_278 & out_womask_424; // @[RegisterRouter.scala:87:24] wire _out_T_4463 = ~out_rimask_424; // @[RegisterRouter.scala:87:24] wire _out_T_4464 = ~out_wimask_424; // @[RegisterRouter.scala:87:24] wire _out_T_4465 = ~out_romask_424; // @[RegisterRouter.scala:87:24] wire _out_T_4466 = ~out_womask_424; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_355 = {hi_631, flags_0_go, _out_prepend_T_355}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4467 = out_prepend_355; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4468 = _out_T_4467; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_356 = _out_T_4468; // @[RegisterRouter.scala:87:24] wire out_rimask_425 = |_out_rimask_T_425; // @[RegisterRouter.scala:87:24] wire out_wimask_425 = &_out_wimask_T_425; // @[RegisterRouter.scala:87:24] wire out_romask_425 = |_out_romask_T_425; // @[RegisterRouter.scala:87:24] wire out_womask_425 = &_out_womask_T_425; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_425 = out_rivalid_1_279 & out_rimask_425; // @[RegisterRouter.scala:87:24] wire _out_T_4470 = out_f_rivalid_425; // @[RegisterRouter.scala:87:24] wire out_f_roready_425 = out_roready_1_279 & out_romask_425; // @[RegisterRouter.scala:87:24] wire _out_T_4471 = out_f_roready_425; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_425 = out_wivalid_1_279 & out_wimask_425; // @[RegisterRouter.scala:87:24] wire out_f_woready_425 = out_woready_1_279 & out_womask_425; // @[RegisterRouter.scala:87:24] wire _out_T_4472 = ~out_rimask_425; // @[RegisterRouter.scala:87:24] wire _out_T_4473 = ~out_wimask_425; // @[RegisterRouter.scala:87:24] wire _out_T_4474 = ~out_romask_425; // @[RegisterRouter.scala:87:24] wire _out_T_4475 = ~out_womask_425; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_356 = {hi_632, flags_0_go, _out_prepend_T_356}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4476 = out_prepend_356; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4477 = _out_T_4476; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_206 = _out_T_4477; // @[MuxLiteral.scala:49:48] wire out_rimask_426 = |_out_rimask_T_426; // @[RegisterRouter.scala:87:24] wire out_wimask_426 = &_out_wimask_T_426; // @[RegisterRouter.scala:87:24] wire out_romask_426 = |_out_romask_T_426; // @[RegisterRouter.scala:87:24] wire out_womask_426 = &_out_womask_T_426; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_426 = out_rivalid_1_280 & out_rimask_426; // @[RegisterRouter.scala:87:24] wire _out_T_4479 = out_f_rivalid_426; // @[RegisterRouter.scala:87:24] wire out_f_roready_426 = out_roready_1_280 & out_romask_426; // @[RegisterRouter.scala:87:24] wire _out_T_4480 = out_f_roready_426; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_426 = out_wivalid_1_280 & out_wimask_426; // @[RegisterRouter.scala:87:24] wire out_f_woready_426 = out_woready_1_280 & out_womask_426; // @[RegisterRouter.scala:87:24] wire _out_T_4481 = ~out_rimask_426; // @[RegisterRouter.scala:87:24] wire _out_T_4482 = ~out_wimask_426; // @[RegisterRouter.scala:87:24] wire _out_T_4483 = ~out_romask_426; // @[RegisterRouter.scala:87:24] wire _out_T_4484 = ~out_womask_426; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4486 = _out_T_4485; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_357 = _out_T_4486; // @[RegisterRouter.scala:87:24] wire out_rimask_427 = |_out_rimask_T_427; // @[RegisterRouter.scala:87:24] wire out_wimask_427 = &_out_wimask_T_427; // @[RegisterRouter.scala:87:24] wire out_romask_427 = |_out_romask_T_427; // @[RegisterRouter.scala:87:24] wire out_womask_427 = &_out_womask_T_427; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_427 = out_rivalid_1_281 & out_rimask_427; // @[RegisterRouter.scala:87:24] wire _out_T_4488 = out_f_rivalid_427; // @[RegisterRouter.scala:87:24] wire out_f_roready_427 = out_roready_1_281 & out_romask_427; // @[RegisterRouter.scala:87:24] wire _out_T_4489 = out_f_roready_427; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_427 = out_wivalid_1_281 & out_wimask_427; // @[RegisterRouter.scala:87:24] wire out_f_woready_427 = out_woready_1_281 & out_womask_427; // @[RegisterRouter.scala:87:24] wire _out_T_4490 = ~out_rimask_427; // @[RegisterRouter.scala:87:24] wire _out_T_4491 = ~out_wimask_427; // @[RegisterRouter.scala:87:24] wire _out_T_4492 = ~out_romask_427; // @[RegisterRouter.scala:87:24] wire _out_T_4493 = ~out_womask_427; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_357 = {hi_842, flags_0_go, _out_prepend_T_357}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4494 = out_prepend_357; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4495 = _out_T_4494; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_358 = _out_T_4495; // @[RegisterRouter.scala:87:24] wire out_rimask_428 = |_out_rimask_T_428; // @[RegisterRouter.scala:87:24] wire out_wimask_428 = &_out_wimask_T_428; // @[RegisterRouter.scala:87:24] wire out_romask_428 = |_out_romask_T_428; // @[RegisterRouter.scala:87:24] wire out_womask_428 = &_out_womask_T_428; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_428 = out_rivalid_1_282 & out_rimask_428; // @[RegisterRouter.scala:87:24] wire _out_T_4497 = out_f_rivalid_428; // @[RegisterRouter.scala:87:24] wire out_f_roready_428 = out_roready_1_282 & out_romask_428; // @[RegisterRouter.scala:87:24] wire _out_T_4498 = out_f_roready_428; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_428 = out_wivalid_1_282 & out_wimask_428; // @[RegisterRouter.scala:87:24] wire out_f_woready_428 = out_woready_1_282 & out_womask_428; // @[RegisterRouter.scala:87:24] wire _out_T_4499 = ~out_rimask_428; // @[RegisterRouter.scala:87:24] wire _out_T_4500 = ~out_wimask_428; // @[RegisterRouter.scala:87:24] wire _out_T_4501 = ~out_romask_428; // @[RegisterRouter.scala:87:24] wire _out_T_4502 = ~out_womask_428; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_358 = {hi_843, flags_0_go, _out_prepend_T_358}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4503 = out_prepend_358; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4504 = _out_T_4503; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_359 = _out_T_4504; // @[RegisterRouter.scala:87:24] wire out_rimask_429 = |_out_rimask_T_429; // @[RegisterRouter.scala:87:24] wire out_wimask_429 = &_out_wimask_T_429; // @[RegisterRouter.scala:87:24] wire out_romask_429 = |_out_romask_T_429; // @[RegisterRouter.scala:87:24] wire out_womask_429 = &_out_womask_T_429; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_429 = out_rivalid_1_283 & out_rimask_429; // @[RegisterRouter.scala:87:24] wire _out_T_4506 = out_f_rivalid_429; // @[RegisterRouter.scala:87:24] wire out_f_roready_429 = out_roready_1_283 & out_romask_429; // @[RegisterRouter.scala:87:24] wire _out_T_4507 = out_f_roready_429; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_429 = out_wivalid_1_283 & out_wimask_429; // @[RegisterRouter.scala:87:24] wire out_f_woready_429 = out_woready_1_283 & out_womask_429; // @[RegisterRouter.scala:87:24] wire _out_T_4508 = ~out_rimask_429; // @[RegisterRouter.scala:87:24] wire _out_T_4509 = ~out_wimask_429; // @[RegisterRouter.scala:87:24] wire _out_T_4510 = ~out_romask_429; // @[RegisterRouter.scala:87:24] wire _out_T_4511 = ~out_womask_429; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_359 = {hi_844, flags_0_go, _out_prepend_T_359}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4512 = out_prepend_359; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4513 = _out_T_4512; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_360 = _out_T_4513; // @[RegisterRouter.scala:87:24] wire out_rimask_430 = |_out_rimask_T_430; // @[RegisterRouter.scala:87:24] wire out_wimask_430 = &_out_wimask_T_430; // @[RegisterRouter.scala:87:24] wire out_romask_430 = |_out_romask_T_430; // @[RegisterRouter.scala:87:24] wire out_womask_430 = &_out_womask_T_430; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_430 = out_rivalid_1_284 & out_rimask_430; // @[RegisterRouter.scala:87:24] wire _out_T_4515 = out_f_rivalid_430; // @[RegisterRouter.scala:87:24] wire out_f_roready_430 = out_roready_1_284 & out_romask_430; // @[RegisterRouter.scala:87:24] wire _out_T_4516 = out_f_roready_430; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_430 = out_wivalid_1_284 & out_wimask_430; // @[RegisterRouter.scala:87:24] wire out_f_woready_430 = out_woready_1_284 & out_womask_430; // @[RegisterRouter.scala:87:24] wire _out_T_4517 = ~out_rimask_430; // @[RegisterRouter.scala:87:24] wire _out_T_4518 = ~out_wimask_430; // @[RegisterRouter.scala:87:24] wire _out_T_4519 = ~out_romask_430; // @[RegisterRouter.scala:87:24] wire _out_T_4520 = ~out_womask_430; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_360 = {hi_845, flags_0_go, _out_prepend_T_360}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4521 = out_prepend_360; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4522 = _out_T_4521; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_361 = _out_T_4522; // @[RegisterRouter.scala:87:24] wire out_rimask_431 = |_out_rimask_T_431; // @[RegisterRouter.scala:87:24] wire out_wimask_431 = &_out_wimask_T_431; // @[RegisterRouter.scala:87:24] wire out_romask_431 = |_out_romask_T_431; // @[RegisterRouter.scala:87:24] wire out_womask_431 = &_out_womask_T_431; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_431 = out_rivalid_1_285 & out_rimask_431; // @[RegisterRouter.scala:87:24] wire _out_T_4524 = out_f_rivalid_431; // @[RegisterRouter.scala:87:24] wire out_f_roready_431 = out_roready_1_285 & out_romask_431; // @[RegisterRouter.scala:87:24] wire _out_T_4525 = out_f_roready_431; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_431 = out_wivalid_1_285 & out_wimask_431; // @[RegisterRouter.scala:87:24] wire out_f_woready_431 = out_woready_1_285 & out_womask_431; // @[RegisterRouter.scala:87:24] wire _out_T_4526 = ~out_rimask_431; // @[RegisterRouter.scala:87:24] wire _out_T_4527 = ~out_wimask_431; // @[RegisterRouter.scala:87:24] wire _out_T_4528 = ~out_romask_431; // @[RegisterRouter.scala:87:24] wire _out_T_4529 = ~out_womask_431; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_361 = {hi_846, flags_0_go, _out_prepend_T_361}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4530 = out_prepend_361; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4531 = _out_T_4530; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_362 = _out_T_4531; // @[RegisterRouter.scala:87:24] wire out_rimask_432 = |_out_rimask_T_432; // @[RegisterRouter.scala:87:24] wire out_wimask_432 = &_out_wimask_T_432; // @[RegisterRouter.scala:87:24] wire out_romask_432 = |_out_romask_T_432; // @[RegisterRouter.scala:87:24] wire out_womask_432 = &_out_womask_T_432; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_432 = out_rivalid_1_286 & out_rimask_432; // @[RegisterRouter.scala:87:24] wire _out_T_4533 = out_f_rivalid_432; // @[RegisterRouter.scala:87:24] wire out_f_roready_432 = out_roready_1_286 & out_romask_432; // @[RegisterRouter.scala:87:24] wire _out_T_4534 = out_f_roready_432; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_432 = out_wivalid_1_286 & out_wimask_432; // @[RegisterRouter.scala:87:24] wire out_f_woready_432 = out_woready_1_286 & out_womask_432; // @[RegisterRouter.scala:87:24] wire _out_T_4535 = ~out_rimask_432; // @[RegisterRouter.scala:87:24] wire _out_T_4536 = ~out_wimask_432; // @[RegisterRouter.scala:87:24] wire _out_T_4537 = ~out_romask_432; // @[RegisterRouter.scala:87:24] wire _out_T_4538 = ~out_womask_432; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_362 = {hi_847, flags_0_go, _out_prepend_T_362}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4539 = out_prepend_362; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4540 = _out_T_4539; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_363 = _out_T_4540; // @[RegisterRouter.scala:87:24] wire out_rimask_433 = |_out_rimask_T_433; // @[RegisterRouter.scala:87:24] wire out_wimask_433 = &_out_wimask_T_433; // @[RegisterRouter.scala:87:24] wire out_romask_433 = |_out_romask_T_433; // @[RegisterRouter.scala:87:24] wire out_womask_433 = &_out_womask_T_433; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_433 = out_rivalid_1_287 & out_rimask_433; // @[RegisterRouter.scala:87:24] wire _out_T_4542 = out_f_rivalid_433; // @[RegisterRouter.scala:87:24] wire out_f_roready_433 = out_roready_1_287 & out_romask_433; // @[RegisterRouter.scala:87:24] wire _out_T_4543 = out_f_roready_433; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_433 = out_wivalid_1_287 & out_wimask_433; // @[RegisterRouter.scala:87:24] wire out_f_woready_433 = out_woready_1_287 & out_womask_433; // @[RegisterRouter.scala:87:24] wire _out_T_4544 = ~out_rimask_433; // @[RegisterRouter.scala:87:24] wire _out_T_4545 = ~out_wimask_433; // @[RegisterRouter.scala:87:24] wire _out_T_4546 = ~out_romask_433; // @[RegisterRouter.scala:87:24] wire _out_T_4547 = ~out_womask_433; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_363 = {hi_848, flags_0_go, _out_prepend_T_363}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4548 = out_prepend_363; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4549 = _out_T_4548; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_233 = _out_T_4549; // @[MuxLiteral.scala:49:48] wire out_rimask_434 = |_out_rimask_T_434; // @[RegisterRouter.scala:87:24] wire out_wimask_434 = &_out_wimask_T_434; // @[RegisterRouter.scala:87:24] wire out_romask_434 = |_out_romask_T_434; // @[RegisterRouter.scala:87:24] wire out_womask_434 = &_out_womask_T_434; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_434 = out_rivalid_1_288 & out_rimask_434; // @[RegisterRouter.scala:87:24] wire _out_T_4551 = out_f_rivalid_434; // @[RegisterRouter.scala:87:24] wire out_f_roready_434 = out_roready_1_288 & out_romask_434; // @[RegisterRouter.scala:87:24] wire _out_T_4552 = out_f_roready_434; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_434 = out_wivalid_1_288 & out_wimask_434; // @[RegisterRouter.scala:87:24] wire out_f_woready_434 = out_woready_1_288 & out_womask_434; // @[RegisterRouter.scala:87:24] wire _out_T_4553 = ~out_rimask_434; // @[RegisterRouter.scala:87:24] wire _out_T_4554 = ~out_wimask_434; // @[RegisterRouter.scala:87:24] wire _out_T_4555 = ~out_romask_434; // @[RegisterRouter.scala:87:24] wire _out_T_4556 = ~out_womask_434; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4558 = _out_T_4557; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_364 = _out_T_4558; // @[RegisterRouter.scala:87:24] wire out_rimask_435 = |_out_rimask_T_435; // @[RegisterRouter.scala:87:24] wire out_wimask_435 = &_out_wimask_T_435; // @[RegisterRouter.scala:87:24] wire out_romask_435 = |_out_romask_T_435; // @[RegisterRouter.scala:87:24] wire out_womask_435 = &_out_womask_T_435; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_435 = out_rivalid_1_289 & out_rimask_435; // @[RegisterRouter.scala:87:24] wire _out_T_4560 = out_f_rivalid_435; // @[RegisterRouter.scala:87:24] wire out_f_roready_435 = out_roready_1_289 & out_romask_435; // @[RegisterRouter.scala:87:24] wire _out_T_4561 = out_f_roready_435; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_435 = out_wivalid_1_289 & out_wimask_435; // @[RegisterRouter.scala:87:24] wire out_f_woready_435 = out_woready_1_289 & out_womask_435; // @[RegisterRouter.scala:87:24] wire _out_T_4562 = ~out_rimask_435; // @[RegisterRouter.scala:87:24] wire _out_T_4563 = ~out_wimask_435; // @[RegisterRouter.scala:87:24] wire _out_T_4564 = ~out_romask_435; // @[RegisterRouter.scala:87:24] wire _out_T_4565 = ~out_womask_435; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_364 = {hi_962, flags_0_go, _out_prepend_T_364}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4566 = out_prepend_364; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4567 = _out_T_4566; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_365 = _out_T_4567; // @[RegisterRouter.scala:87:24] wire out_rimask_436 = |_out_rimask_T_436; // @[RegisterRouter.scala:87:24] wire out_wimask_436 = &_out_wimask_T_436; // @[RegisterRouter.scala:87:24] wire out_romask_436 = |_out_romask_T_436; // @[RegisterRouter.scala:87:24] wire out_womask_436 = &_out_womask_T_436; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_436 = out_rivalid_1_290 & out_rimask_436; // @[RegisterRouter.scala:87:24] wire _out_T_4569 = out_f_rivalid_436; // @[RegisterRouter.scala:87:24] wire out_f_roready_436 = out_roready_1_290 & out_romask_436; // @[RegisterRouter.scala:87:24] wire _out_T_4570 = out_f_roready_436; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_436 = out_wivalid_1_290 & out_wimask_436; // @[RegisterRouter.scala:87:24] wire out_f_woready_436 = out_woready_1_290 & out_womask_436; // @[RegisterRouter.scala:87:24] wire _out_T_4571 = ~out_rimask_436; // @[RegisterRouter.scala:87:24] wire _out_T_4572 = ~out_wimask_436; // @[RegisterRouter.scala:87:24] wire _out_T_4573 = ~out_romask_436; // @[RegisterRouter.scala:87:24] wire _out_T_4574 = ~out_womask_436; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_365 = {hi_963, flags_0_go, _out_prepend_T_365}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4575 = out_prepend_365; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4576 = _out_T_4575; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_366 = _out_T_4576; // @[RegisterRouter.scala:87:24] wire out_rimask_437 = |_out_rimask_T_437; // @[RegisterRouter.scala:87:24] wire out_wimask_437 = &_out_wimask_T_437; // @[RegisterRouter.scala:87:24] wire out_romask_437 = |_out_romask_T_437; // @[RegisterRouter.scala:87:24] wire out_womask_437 = &_out_womask_T_437; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_437 = out_rivalid_1_291 & out_rimask_437; // @[RegisterRouter.scala:87:24] wire _out_T_4578 = out_f_rivalid_437; // @[RegisterRouter.scala:87:24] wire out_f_roready_437 = out_roready_1_291 & out_romask_437; // @[RegisterRouter.scala:87:24] wire _out_T_4579 = out_f_roready_437; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_437 = out_wivalid_1_291 & out_wimask_437; // @[RegisterRouter.scala:87:24] wire out_f_woready_437 = out_woready_1_291 & out_womask_437; // @[RegisterRouter.scala:87:24] wire _out_T_4580 = ~out_rimask_437; // @[RegisterRouter.scala:87:24] wire _out_T_4581 = ~out_wimask_437; // @[RegisterRouter.scala:87:24] wire _out_T_4582 = ~out_romask_437; // @[RegisterRouter.scala:87:24] wire _out_T_4583 = ~out_womask_437; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_366 = {hi_964, flags_0_go, _out_prepend_T_366}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4584 = out_prepend_366; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4585 = _out_T_4584; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_367 = _out_T_4585; // @[RegisterRouter.scala:87:24] wire out_rimask_438 = |_out_rimask_T_438; // @[RegisterRouter.scala:87:24] wire out_wimask_438 = &_out_wimask_T_438; // @[RegisterRouter.scala:87:24] wire out_romask_438 = |_out_romask_T_438; // @[RegisterRouter.scala:87:24] wire out_womask_438 = &_out_womask_T_438; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_438 = out_rivalid_1_292 & out_rimask_438; // @[RegisterRouter.scala:87:24] wire _out_T_4587 = out_f_rivalid_438; // @[RegisterRouter.scala:87:24] wire out_f_roready_438 = out_roready_1_292 & out_romask_438; // @[RegisterRouter.scala:87:24] wire _out_T_4588 = out_f_roready_438; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_438 = out_wivalid_1_292 & out_wimask_438; // @[RegisterRouter.scala:87:24] wire out_f_woready_438 = out_woready_1_292 & out_womask_438; // @[RegisterRouter.scala:87:24] wire _out_T_4589 = ~out_rimask_438; // @[RegisterRouter.scala:87:24] wire _out_T_4590 = ~out_wimask_438; // @[RegisterRouter.scala:87:24] wire _out_T_4591 = ~out_romask_438; // @[RegisterRouter.scala:87:24] wire _out_T_4592 = ~out_womask_438; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_367 = {hi_965, flags_0_go, _out_prepend_T_367}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4593 = out_prepend_367; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4594 = _out_T_4593; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_368 = _out_T_4594; // @[RegisterRouter.scala:87:24] wire out_rimask_439 = |_out_rimask_T_439; // @[RegisterRouter.scala:87:24] wire out_wimask_439 = &_out_wimask_T_439; // @[RegisterRouter.scala:87:24] wire out_romask_439 = |_out_romask_T_439; // @[RegisterRouter.scala:87:24] wire out_womask_439 = &_out_womask_T_439; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_439 = out_rivalid_1_293 & out_rimask_439; // @[RegisterRouter.scala:87:24] wire _out_T_4596 = out_f_rivalid_439; // @[RegisterRouter.scala:87:24] wire out_f_roready_439 = out_roready_1_293 & out_romask_439; // @[RegisterRouter.scala:87:24] wire _out_T_4597 = out_f_roready_439; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_439 = out_wivalid_1_293 & out_wimask_439; // @[RegisterRouter.scala:87:24] wire out_f_woready_439 = out_woready_1_293 & out_womask_439; // @[RegisterRouter.scala:87:24] wire _out_T_4598 = ~out_rimask_439; // @[RegisterRouter.scala:87:24] wire _out_T_4599 = ~out_wimask_439; // @[RegisterRouter.scala:87:24] wire _out_T_4600 = ~out_romask_439; // @[RegisterRouter.scala:87:24] wire _out_T_4601 = ~out_womask_439; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_368 = {hi_966, flags_0_go, _out_prepend_T_368}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4602 = out_prepend_368; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4603 = _out_T_4602; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_369 = _out_T_4603; // @[RegisterRouter.scala:87:24] wire out_rimask_440 = |_out_rimask_T_440; // @[RegisterRouter.scala:87:24] wire out_wimask_440 = &_out_wimask_T_440; // @[RegisterRouter.scala:87:24] wire out_romask_440 = |_out_romask_T_440; // @[RegisterRouter.scala:87:24] wire out_womask_440 = &_out_womask_T_440; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_440 = out_rivalid_1_294 & out_rimask_440; // @[RegisterRouter.scala:87:24] wire _out_T_4605 = out_f_rivalid_440; // @[RegisterRouter.scala:87:24] wire out_f_roready_440 = out_roready_1_294 & out_romask_440; // @[RegisterRouter.scala:87:24] wire _out_T_4606 = out_f_roready_440; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_440 = out_wivalid_1_294 & out_wimask_440; // @[RegisterRouter.scala:87:24] wire out_f_woready_440 = out_woready_1_294 & out_womask_440; // @[RegisterRouter.scala:87:24] wire _out_T_4607 = ~out_rimask_440; // @[RegisterRouter.scala:87:24] wire _out_T_4608 = ~out_wimask_440; // @[RegisterRouter.scala:87:24] wire _out_T_4609 = ~out_romask_440; // @[RegisterRouter.scala:87:24] wire _out_T_4610 = ~out_womask_440; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_369 = {hi_967, flags_0_go, _out_prepend_T_369}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4611 = out_prepend_369; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4612 = _out_T_4611; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_370 = _out_T_4612; // @[RegisterRouter.scala:87:24] wire out_rimask_441 = |_out_rimask_T_441; // @[RegisterRouter.scala:87:24] wire out_wimask_441 = &_out_wimask_T_441; // @[RegisterRouter.scala:87:24] wire out_romask_441 = |_out_romask_T_441; // @[RegisterRouter.scala:87:24] wire out_womask_441 = &_out_womask_T_441; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_441 = out_rivalid_1_295 & out_rimask_441; // @[RegisterRouter.scala:87:24] wire _out_T_4614 = out_f_rivalid_441; // @[RegisterRouter.scala:87:24] wire out_f_roready_441 = out_roready_1_295 & out_romask_441; // @[RegisterRouter.scala:87:24] wire _out_T_4615 = out_f_roready_441; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_441 = out_wivalid_1_295 & out_wimask_441; // @[RegisterRouter.scala:87:24] wire out_f_woready_441 = out_woready_1_295 & out_womask_441; // @[RegisterRouter.scala:87:24] wire _out_T_4616 = ~out_rimask_441; // @[RegisterRouter.scala:87:24] wire _out_T_4617 = ~out_wimask_441; // @[RegisterRouter.scala:87:24] wire _out_T_4618 = ~out_romask_441; // @[RegisterRouter.scala:87:24] wire _out_T_4619 = ~out_womask_441; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_370 = {hi_968, flags_0_go, _out_prepend_T_370}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4620 = out_prepend_370; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4621 = _out_T_4620; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_248 = _out_T_4621; // @[MuxLiteral.scala:49:48] wire out_rimask_442 = |_out_rimask_T_442; // @[RegisterRouter.scala:87:24] wire out_wimask_442 = &_out_wimask_T_442; // @[RegisterRouter.scala:87:24] wire out_romask_442 = |_out_romask_T_442; // @[RegisterRouter.scala:87:24] wire out_womask_442 = &_out_womask_T_442; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_442 = out_rivalid_1_296 & out_rimask_442; // @[RegisterRouter.scala:87:24] wire _out_T_4623 = out_f_rivalid_442; // @[RegisterRouter.scala:87:24] wire out_f_roready_442 = out_roready_1_296 & out_romask_442; // @[RegisterRouter.scala:87:24] wire _out_T_4624 = out_f_roready_442; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_442 = out_wivalid_1_296 & out_wimask_442; // @[RegisterRouter.scala:87:24] wire out_f_woready_442 = out_woready_1_296 & out_womask_442; // @[RegisterRouter.scala:87:24] wire _out_T_4625 = ~out_rimask_442; // @[RegisterRouter.scala:87:24] wire _out_T_4626 = ~out_wimask_442; // @[RegisterRouter.scala:87:24] wire _out_T_4627 = ~out_romask_442; // @[RegisterRouter.scala:87:24] wire _out_T_4628 = ~out_womask_442; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4630 = _out_T_4629; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_371 = _out_T_4630; // @[RegisterRouter.scala:87:24] wire out_rimask_443 = |_out_rimask_T_443; // @[RegisterRouter.scala:87:24] wire out_wimask_443 = &_out_wimask_T_443; // @[RegisterRouter.scala:87:24] wire out_romask_443 = |_out_romask_T_443; // @[RegisterRouter.scala:87:24] wire out_womask_443 = &_out_womask_T_443; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_443 = out_rivalid_1_297 & out_rimask_443; // @[RegisterRouter.scala:87:24] wire _out_T_4632 = out_f_rivalid_443; // @[RegisterRouter.scala:87:24] wire out_f_roready_443 = out_roready_1_297 & out_romask_443; // @[RegisterRouter.scala:87:24] wire _out_T_4633 = out_f_roready_443; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_443 = out_wivalid_1_297 & out_wimask_443; // @[RegisterRouter.scala:87:24] wire out_f_woready_443 = out_woready_1_297 & out_womask_443; // @[RegisterRouter.scala:87:24] wire _out_T_4634 = ~out_rimask_443; // @[RegisterRouter.scala:87:24] wire _out_T_4635 = ~out_wimask_443; // @[RegisterRouter.scala:87:24] wire _out_T_4636 = ~out_romask_443; // @[RegisterRouter.scala:87:24] wire _out_T_4637 = ~out_womask_443; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_371 = {hi_586, flags_0_go, _out_prepend_T_371}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4638 = out_prepend_371; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4639 = _out_T_4638; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_372 = _out_T_4639; // @[RegisterRouter.scala:87:24] wire out_rimask_444 = |_out_rimask_T_444; // @[RegisterRouter.scala:87:24] wire out_wimask_444 = &_out_wimask_T_444; // @[RegisterRouter.scala:87:24] wire out_romask_444 = |_out_romask_T_444; // @[RegisterRouter.scala:87:24] wire out_womask_444 = &_out_womask_T_444; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_444 = out_rivalid_1_298 & out_rimask_444; // @[RegisterRouter.scala:87:24] wire _out_T_4641 = out_f_rivalid_444; // @[RegisterRouter.scala:87:24] wire out_f_roready_444 = out_roready_1_298 & out_romask_444; // @[RegisterRouter.scala:87:24] wire _out_T_4642 = out_f_roready_444; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_444 = out_wivalid_1_298 & out_wimask_444; // @[RegisterRouter.scala:87:24] wire out_f_woready_444 = out_woready_1_298 & out_womask_444; // @[RegisterRouter.scala:87:24] wire _out_T_4643 = ~out_rimask_444; // @[RegisterRouter.scala:87:24] wire _out_T_4644 = ~out_wimask_444; // @[RegisterRouter.scala:87:24] wire _out_T_4645 = ~out_romask_444; // @[RegisterRouter.scala:87:24] wire _out_T_4646 = ~out_womask_444; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_372 = {hi_587, flags_0_go, _out_prepend_T_372}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4647 = out_prepend_372; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4648 = _out_T_4647; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_373 = _out_T_4648; // @[RegisterRouter.scala:87:24] wire out_rimask_445 = |_out_rimask_T_445; // @[RegisterRouter.scala:87:24] wire out_wimask_445 = &_out_wimask_T_445; // @[RegisterRouter.scala:87:24] wire out_romask_445 = |_out_romask_T_445; // @[RegisterRouter.scala:87:24] wire out_womask_445 = &_out_womask_T_445; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_445 = out_rivalid_1_299 & out_rimask_445; // @[RegisterRouter.scala:87:24] wire _out_T_4650 = out_f_rivalid_445; // @[RegisterRouter.scala:87:24] wire out_f_roready_445 = out_roready_1_299 & out_romask_445; // @[RegisterRouter.scala:87:24] wire _out_T_4651 = out_f_roready_445; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_445 = out_wivalid_1_299 & out_wimask_445; // @[RegisterRouter.scala:87:24] wire out_f_woready_445 = out_woready_1_299 & out_womask_445; // @[RegisterRouter.scala:87:24] wire _out_T_4652 = ~out_rimask_445; // @[RegisterRouter.scala:87:24] wire _out_T_4653 = ~out_wimask_445; // @[RegisterRouter.scala:87:24] wire _out_T_4654 = ~out_romask_445; // @[RegisterRouter.scala:87:24] wire _out_T_4655 = ~out_womask_445; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_373 = {hi_588, flags_0_go, _out_prepend_T_373}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4656 = out_prepend_373; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4657 = _out_T_4656; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_374 = _out_T_4657; // @[RegisterRouter.scala:87:24] wire out_rimask_446 = |_out_rimask_T_446; // @[RegisterRouter.scala:87:24] wire out_wimask_446 = &_out_wimask_T_446; // @[RegisterRouter.scala:87:24] wire out_romask_446 = |_out_romask_T_446; // @[RegisterRouter.scala:87:24] wire out_womask_446 = &_out_womask_T_446; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_446 = out_rivalid_1_300 & out_rimask_446; // @[RegisterRouter.scala:87:24] wire _out_T_4659 = out_f_rivalid_446; // @[RegisterRouter.scala:87:24] wire out_f_roready_446 = out_roready_1_300 & out_romask_446; // @[RegisterRouter.scala:87:24] wire _out_T_4660 = out_f_roready_446; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_446 = out_wivalid_1_300 & out_wimask_446; // @[RegisterRouter.scala:87:24] wire out_f_woready_446 = out_woready_1_300 & out_womask_446; // @[RegisterRouter.scala:87:24] wire _out_T_4661 = ~out_rimask_446; // @[RegisterRouter.scala:87:24] wire _out_T_4662 = ~out_wimask_446; // @[RegisterRouter.scala:87:24] wire _out_T_4663 = ~out_romask_446; // @[RegisterRouter.scala:87:24] wire _out_T_4664 = ~out_womask_446; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_374 = {hi_589, flags_0_go, _out_prepend_T_374}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4665 = out_prepend_374; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4666 = _out_T_4665; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_375 = _out_T_4666; // @[RegisterRouter.scala:87:24] wire out_rimask_447 = |_out_rimask_T_447; // @[RegisterRouter.scala:87:24] wire out_wimask_447 = &_out_wimask_T_447; // @[RegisterRouter.scala:87:24] wire out_romask_447 = |_out_romask_T_447; // @[RegisterRouter.scala:87:24] wire out_womask_447 = &_out_womask_T_447; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_447 = out_rivalid_1_301 & out_rimask_447; // @[RegisterRouter.scala:87:24] wire _out_T_4668 = out_f_rivalid_447; // @[RegisterRouter.scala:87:24] wire out_f_roready_447 = out_roready_1_301 & out_romask_447; // @[RegisterRouter.scala:87:24] wire _out_T_4669 = out_f_roready_447; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_447 = out_wivalid_1_301 & out_wimask_447; // @[RegisterRouter.scala:87:24] wire out_f_woready_447 = out_woready_1_301 & out_womask_447; // @[RegisterRouter.scala:87:24] wire _out_T_4670 = ~out_rimask_447; // @[RegisterRouter.scala:87:24] wire _out_T_4671 = ~out_wimask_447; // @[RegisterRouter.scala:87:24] wire _out_T_4672 = ~out_romask_447; // @[RegisterRouter.scala:87:24] wire _out_T_4673 = ~out_womask_447; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_375 = {hi_590, flags_0_go, _out_prepend_T_375}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4674 = out_prepend_375; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4675 = _out_T_4674; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_376 = _out_T_4675; // @[RegisterRouter.scala:87:24] wire out_rimask_448 = |_out_rimask_T_448; // @[RegisterRouter.scala:87:24] wire out_wimask_448 = &_out_wimask_T_448; // @[RegisterRouter.scala:87:24] wire out_romask_448 = |_out_romask_T_448; // @[RegisterRouter.scala:87:24] wire out_womask_448 = &_out_womask_T_448; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_448 = out_rivalid_1_302 & out_rimask_448; // @[RegisterRouter.scala:87:24] wire _out_T_4677 = out_f_rivalid_448; // @[RegisterRouter.scala:87:24] wire out_f_roready_448 = out_roready_1_302 & out_romask_448; // @[RegisterRouter.scala:87:24] wire _out_T_4678 = out_f_roready_448; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_448 = out_wivalid_1_302 & out_wimask_448; // @[RegisterRouter.scala:87:24] wire out_f_woready_448 = out_woready_1_302 & out_womask_448; // @[RegisterRouter.scala:87:24] wire _out_T_4679 = ~out_rimask_448; // @[RegisterRouter.scala:87:24] wire _out_T_4680 = ~out_wimask_448; // @[RegisterRouter.scala:87:24] wire _out_T_4681 = ~out_romask_448; // @[RegisterRouter.scala:87:24] wire _out_T_4682 = ~out_womask_448; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_376 = {hi_591, flags_0_go, _out_prepend_T_376}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4683 = out_prepend_376; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4684 = _out_T_4683; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_377 = _out_T_4684; // @[RegisterRouter.scala:87:24] wire out_rimask_449 = |_out_rimask_T_449; // @[RegisterRouter.scala:87:24] wire out_wimask_449 = &_out_wimask_T_449; // @[RegisterRouter.scala:87:24] wire out_romask_449 = |_out_romask_T_449; // @[RegisterRouter.scala:87:24] wire out_womask_449 = &_out_womask_T_449; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_449 = out_rivalid_1_303 & out_rimask_449; // @[RegisterRouter.scala:87:24] wire _out_T_4686 = out_f_rivalid_449; // @[RegisterRouter.scala:87:24] wire out_f_roready_449 = out_roready_1_303 & out_romask_449; // @[RegisterRouter.scala:87:24] wire _out_T_4687 = out_f_roready_449; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_449 = out_wivalid_1_303 & out_wimask_449; // @[RegisterRouter.scala:87:24] wire out_f_woready_449 = out_woready_1_303 & out_womask_449; // @[RegisterRouter.scala:87:24] wire _out_T_4688 = ~out_rimask_449; // @[RegisterRouter.scala:87:24] wire _out_T_4689 = ~out_wimask_449; // @[RegisterRouter.scala:87:24] wire _out_T_4690 = ~out_romask_449; // @[RegisterRouter.scala:87:24] wire _out_T_4691 = ~out_womask_449; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_377 = {hi_592, flags_0_go, _out_prepend_T_377}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4692 = out_prepend_377; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4693 = _out_T_4692; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_201 = _out_T_4693; // @[MuxLiteral.scala:49:48] wire out_rimask_450 = |_out_rimask_T_450; // @[RegisterRouter.scala:87:24] wire out_wimask_450 = &_out_wimask_T_450; // @[RegisterRouter.scala:87:24] wire out_romask_450 = |_out_romask_T_450; // @[RegisterRouter.scala:87:24] wire out_womask_450 = &_out_womask_T_450; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_450 = out_rivalid_1_304 & out_rimask_450; // @[RegisterRouter.scala:87:24] wire _out_T_4695 = out_f_rivalid_450; // @[RegisterRouter.scala:87:24] wire out_f_roready_450 = out_roready_1_304 & out_romask_450; // @[RegisterRouter.scala:87:24] wire _out_T_4696 = out_f_roready_450; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_450 = out_wivalid_1_304 & out_wimask_450; // @[RegisterRouter.scala:87:24] wire out_f_woready_450 = out_woready_1_304 & out_womask_450; // @[RegisterRouter.scala:87:24] wire _out_T_4697 = ~out_rimask_450; // @[RegisterRouter.scala:87:24] wire _out_T_4698 = ~out_wimask_450; // @[RegisterRouter.scala:87:24] wire _out_T_4699 = ~out_romask_450; // @[RegisterRouter.scala:87:24] wire _out_T_4700 = ~out_womask_450; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4702 = _out_T_4701; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_378 = _out_T_4702; // @[RegisterRouter.scala:87:24] wire out_rimask_451 = |_out_rimask_T_451; // @[RegisterRouter.scala:87:24] wire out_wimask_451 = &_out_wimask_T_451; // @[RegisterRouter.scala:87:24] wire out_romask_451 = |_out_romask_T_451; // @[RegisterRouter.scala:87:24] wire out_womask_451 = &_out_womask_T_451; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_451 = out_rivalid_1_305 & out_rimask_451; // @[RegisterRouter.scala:87:24] wire _out_T_4704 = out_f_rivalid_451; // @[RegisterRouter.scala:87:24] wire out_f_roready_451 = out_roready_1_305 & out_romask_451; // @[RegisterRouter.scala:87:24] wire _out_T_4705 = out_f_roready_451; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_451 = out_wivalid_1_305 & out_wimask_451; // @[RegisterRouter.scala:87:24] wire out_f_woready_451 = out_woready_1_305 & out_womask_451; // @[RegisterRouter.scala:87:24] wire _out_T_4706 = ~out_rimask_451; // @[RegisterRouter.scala:87:24] wire _out_T_4707 = ~out_wimask_451; // @[RegisterRouter.scala:87:24] wire _out_T_4708 = ~out_romask_451; // @[RegisterRouter.scala:87:24] wire _out_T_4709 = ~out_womask_451; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_378 = {hi_738, flags_0_go, _out_prepend_T_378}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4710 = out_prepend_378; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4711 = _out_T_4710; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_379 = _out_T_4711; // @[RegisterRouter.scala:87:24] wire out_rimask_452 = |_out_rimask_T_452; // @[RegisterRouter.scala:87:24] wire out_wimask_452 = &_out_wimask_T_452; // @[RegisterRouter.scala:87:24] wire out_romask_452 = |_out_romask_T_452; // @[RegisterRouter.scala:87:24] wire out_womask_452 = &_out_womask_T_452; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_452 = out_rivalid_1_306 & out_rimask_452; // @[RegisterRouter.scala:87:24] wire _out_T_4713 = out_f_rivalid_452; // @[RegisterRouter.scala:87:24] wire out_f_roready_452 = out_roready_1_306 & out_romask_452; // @[RegisterRouter.scala:87:24] wire _out_T_4714 = out_f_roready_452; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_452 = out_wivalid_1_306 & out_wimask_452; // @[RegisterRouter.scala:87:24] wire out_f_woready_452 = out_woready_1_306 & out_womask_452; // @[RegisterRouter.scala:87:24] wire _out_T_4715 = ~out_rimask_452; // @[RegisterRouter.scala:87:24] wire _out_T_4716 = ~out_wimask_452; // @[RegisterRouter.scala:87:24] wire _out_T_4717 = ~out_romask_452; // @[RegisterRouter.scala:87:24] wire _out_T_4718 = ~out_womask_452; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_379 = {hi_739, flags_0_go, _out_prepend_T_379}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4719 = out_prepend_379; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4720 = _out_T_4719; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_380 = _out_T_4720; // @[RegisterRouter.scala:87:24] wire out_rimask_453 = |_out_rimask_T_453; // @[RegisterRouter.scala:87:24] wire out_wimask_453 = &_out_wimask_T_453; // @[RegisterRouter.scala:87:24] wire out_romask_453 = |_out_romask_T_453; // @[RegisterRouter.scala:87:24] wire out_womask_453 = &_out_womask_T_453; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_453 = out_rivalid_1_307 & out_rimask_453; // @[RegisterRouter.scala:87:24] wire _out_T_4722 = out_f_rivalid_453; // @[RegisterRouter.scala:87:24] wire out_f_roready_453 = out_roready_1_307 & out_romask_453; // @[RegisterRouter.scala:87:24] wire _out_T_4723 = out_f_roready_453; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_453 = out_wivalid_1_307 & out_wimask_453; // @[RegisterRouter.scala:87:24] wire out_f_woready_453 = out_woready_1_307 & out_womask_453; // @[RegisterRouter.scala:87:24] wire _out_T_4724 = ~out_rimask_453; // @[RegisterRouter.scala:87:24] wire _out_T_4725 = ~out_wimask_453; // @[RegisterRouter.scala:87:24] wire _out_T_4726 = ~out_romask_453; // @[RegisterRouter.scala:87:24] wire _out_T_4727 = ~out_womask_453; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_380 = {hi_740, flags_0_go, _out_prepend_T_380}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4728 = out_prepend_380; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4729 = _out_T_4728; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_381 = _out_T_4729; // @[RegisterRouter.scala:87:24] wire out_rimask_454 = |_out_rimask_T_454; // @[RegisterRouter.scala:87:24] wire out_wimask_454 = &_out_wimask_T_454; // @[RegisterRouter.scala:87:24] wire out_romask_454 = |_out_romask_T_454; // @[RegisterRouter.scala:87:24] wire out_womask_454 = &_out_womask_T_454; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_454 = out_rivalid_1_308 & out_rimask_454; // @[RegisterRouter.scala:87:24] wire _out_T_4731 = out_f_rivalid_454; // @[RegisterRouter.scala:87:24] wire out_f_roready_454 = out_roready_1_308 & out_romask_454; // @[RegisterRouter.scala:87:24] wire _out_T_4732 = out_f_roready_454; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_454 = out_wivalid_1_308 & out_wimask_454; // @[RegisterRouter.scala:87:24] wire out_f_woready_454 = out_woready_1_308 & out_womask_454; // @[RegisterRouter.scala:87:24] wire _out_T_4733 = ~out_rimask_454; // @[RegisterRouter.scala:87:24] wire _out_T_4734 = ~out_wimask_454; // @[RegisterRouter.scala:87:24] wire _out_T_4735 = ~out_romask_454; // @[RegisterRouter.scala:87:24] wire _out_T_4736 = ~out_womask_454; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_381 = {hi_741, flags_0_go, _out_prepend_T_381}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4737 = out_prepend_381; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4738 = _out_T_4737; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_382 = _out_T_4738; // @[RegisterRouter.scala:87:24] wire out_rimask_455 = |_out_rimask_T_455; // @[RegisterRouter.scala:87:24] wire out_wimask_455 = &_out_wimask_T_455; // @[RegisterRouter.scala:87:24] wire out_romask_455 = |_out_romask_T_455; // @[RegisterRouter.scala:87:24] wire out_womask_455 = &_out_womask_T_455; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_455 = out_rivalid_1_309 & out_rimask_455; // @[RegisterRouter.scala:87:24] wire _out_T_4740 = out_f_rivalid_455; // @[RegisterRouter.scala:87:24] wire out_f_roready_455 = out_roready_1_309 & out_romask_455; // @[RegisterRouter.scala:87:24] wire _out_T_4741 = out_f_roready_455; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_455 = out_wivalid_1_309 & out_wimask_455; // @[RegisterRouter.scala:87:24] wire out_f_woready_455 = out_woready_1_309 & out_womask_455; // @[RegisterRouter.scala:87:24] wire _out_T_4742 = ~out_rimask_455; // @[RegisterRouter.scala:87:24] wire _out_T_4743 = ~out_wimask_455; // @[RegisterRouter.scala:87:24] wire _out_T_4744 = ~out_romask_455; // @[RegisterRouter.scala:87:24] wire _out_T_4745 = ~out_womask_455; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_382 = {hi_742, flags_0_go, _out_prepend_T_382}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4746 = out_prepend_382; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4747 = _out_T_4746; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_383 = _out_T_4747; // @[RegisterRouter.scala:87:24] wire out_rimask_456 = |_out_rimask_T_456; // @[RegisterRouter.scala:87:24] wire out_wimask_456 = &_out_wimask_T_456; // @[RegisterRouter.scala:87:24] wire out_romask_456 = |_out_romask_T_456; // @[RegisterRouter.scala:87:24] wire out_womask_456 = &_out_womask_T_456; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_456 = out_rivalid_1_310 & out_rimask_456; // @[RegisterRouter.scala:87:24] wire _out_T_4749 = out_f_rivalid_456; // @[RegisterRouter.scala:87:24] wire out_f_roready_456 = out_roready_1_310 & out_romask_456; // @[RegisterRouter.scala:87:24] wire _out_T_4750 = out_f_roready_456; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_456 = out_wivalid_1_310 & out_wimask_456; // @[RegisterRouter.scala:87:24] wire out_f_woready_456 = out_woready_1_310 & out_womask_456; // @[RegisterRouter.scala:87:24] wire _out_T_4751 = ~out_rimask_456; // @[RegisterRouter.scala:87:24] wire _out_T_4752 = ~out_wimask_456; // @[RegisterRouter.scala:87:24] wire _out_T_4753 = ~out_romask_456; // @[RegisterRouter.scala:87:24] wire _out_T_4754 = ~out_womask_456; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_383 = {hi_743, flags_0_go, _out_prepend_T_383}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4755 = out_prepend_383; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4756 = _out_T_4755; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_384 = _out_T_4756; // @[RegisterRouter.scala:87:24] wire out_rimask_457 = |_out_rimask_T_457; // @[RegisterRouter.scala:87:24] wire out_wimask_457 = &_out_wimask_T_457; // @[RegisterRouter.scala:87:24] wire out_romask_457 = |_out_romask_T_457; // @[RegisterRouter.scala:87:24] wire out_womask_457 = &_out_womask_T_457; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_457 = out_rivalid_1_311 & out_rimask_457; // @[RegisterRouter.scala:87:24] wire _out_T_4758 = out_f_rivalid_457; // @[RegisterRouter.scala:87:24] wire out_f_roready_457 = out_roready_1_311 & out_romask_457; // @[RegisterRouter.scala:87:24] wire _out_T_4759 = out_f_roready_457; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_457 = out_wivalid_1_311 & out_wimask_457; // @[RegisterRouter.scala:87:24] wire out_f_woready_457 = out_woready_1_311 & out_womask_457; // @[RegisterRouter.scala:87:24] wire _out_T_4760 = ~out_rimask_457; // @[RegisterRouter.scala:87:24] wire _out_T_4761 = ~out_wimask_457; // @[RegisterRouter.scala:87:24] wire _out_T_4762 = ~out_romask_457; // @[RegisterRouter.scala:87:24] wire _out_T_4763 = ~out_womask_457; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_384 = {hi_744, flags_0_go, _out_prepend_T_384}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4764 = out_prepend_384; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4765 = _out_T_4764; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_220 = _out_T_4765; // @[MuxLiteral.scala:49:48] wire out_rimask_458 = |_out_rimask_T_458; // @[RegisterRouter.scala:87:24] wire out_wimask_458 = &_out_wimask_T_458; // @[RegisterRouter.scala:87:24] wire out_romask_458 = |_out_romask_T_458; // @[RegisterRouter.scala:87:24] wire out_womask_458 = &_out_womask_T_458; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_458 = out_rivalid_1_312 & out_rimask_458; // @[RegisterRouter.scala:87:24] wire _out_T_4767 = out_f_rivalid_458; // @[RegisterRouter.scala:87:24] wire out_f_roready_458 = out_roready_1_312 & out_romask_458; // @[RegisterRouter.scala:87:24] wire _out_T_4768 = out_f_roready_458; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_458 = out_wivalid_1_312 & out_wimask_458; // @[RegisterRouter.scala:87:24] wire out_f_woready_458 = out_woready_1_312 & out_womask_458; // @[RegisterRouter.scala:87:24] wire _out_T_4769 = ~out_rimask_458; // @[RegisterRouter.scala:87:24] wire _out_T_4770 = ~out_wimask_458; // @[RegisterRouter.scala:87:24] wire _out_T_4771 = ~out_romask_458; // @[RegisterRouter.scala:87:24] wire _out_T_4772 = ~out_womask_458; // @[RegisterRouter.scala:87:24] wire out_rimask_459 = |_out_rimask_T_459; // @[RegisterRouter.scala:87:24] wire out_wimask_459 = &_out_wimask_T_459; // @[RegisterRouter.scala:87:24] wire out_romask_459 = |_out_romask_T_459; // @[RegisterRouter.scala:87:24] wire out_womask_459 = &_out_womask_T_459; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_459 = out_rivalid_1_313 & out_rimask_459; // @[RegisterRouter.scala:87:24] wire _out_T_4776 = out_f_rivalid_459; // @[RegisterRouter.scala:87:24] wire out_f_roready_459 = out_roready_1_313 & out_romask_459; // @[RegisterRouter.scala:87:24] wire _out_T_4777 = out_f_roready_459; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_459 = out_wivalid_1_313 & out_wimask_459; // @[RegisterRouter.scala:87:24] wire out_f_woready_459 = out_woready_1_313 & out_womask_459; // @[RegisterRouter.scala:87:24] wire _out_T_4778 = ~out_rimask_459; // @[RegisterRouter.scala:87:24] wire _out_T_4779 = ~out_wimask_459; // @[RegisterRouter.scala:87:24] wire _out_T_4780 = ~out_romask_459; // @[RegisterRouter.scala:87:24] wire _out_T_4781 = ~out_womask_459; // @[RegisterRouter.scala:87:24] wire out_rimask_460 = |_out_rimask_T_460; // @[RegisterRouter.scala:87:24] wire out_wimask_460 = &_out_wimask_T_460; // @[RegisterRouter.scala:87:24] wire out_romask_460 = |_out_romask_T_460; // @[RegisterRouter.scala:87:24] wire out_womask_460 = &_out_womask_T_460; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_460 = out_rivalid_1_314 & out_rimask_460; // @[RegisterRouter.scala:87:24] wire _out_T_4785 = out_f_rivalid_460; // @[RegisterRouter.scala:87:24] wire out_f_roready_460 = out_roready_1_314 & out_romask_460; // @[RegisterRouter.scala:87:24] wire _out_T_4786 = out_f_roready_460; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_460 = out_wivalid_1_314 & out_wimask_460; // @[RegisterRouter.scala:87:24] wire out_f_woready_460 = out_woready_1_314 & out_womask_460; // @[RegisterRouter.scala:87:24] wire _out_T_4787 = ~out_rimask_460; // @[RegisterRouter.scala:87:24] wire _out_T_4788 = ~out_wimask_460; // @[RegisterRouter.scala:87:24] wire _out_T_4789 = ~out_romask_460; // @[RegisterRouter.scala:87:24] wire _out_T_4790 = ~out_womask_460; // @[RegisterRouter.scala:87:24] wire out_rimask_461 = |_out_rimask_T_461; // @[RegisterRouter.scala:87:24] wire out_wimask_461 = &_out_wimask_T_461; // @[RegisterRouter.scala:87:24] wire out_romask_461 = |_out_romask_T_461; // @[RegisterRouter.scala:87:24] wire out_womask_461 = &_out_womask_T_461; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_461 = out_rivalid_1_315 & out_rimask_461; // @[RegisterRouter.scala:87:24] wire _out_T_4794 = out_f_rivalid_461; // @[RegisterRouter.scala:87:24] wire out_f_roready_461 = out_roready_1_315 & out_romask_461; // @[RegisterRouter.scala:87:24] wire _out_T_4795 = out_f_roready_461; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_461 = out_wivalid_1_315 & out_wimask_461; // @[RegisterRouter.scala:87:24] wire out_f_woready_461 = out_woready_1_315 & out_womask_461; // @[RegisterRouter.scala:87:24] wire _out_T_4796 = ~out_rimask_461; // @[RegisterRouter.scala:87:24] wire _out_T_4797 = ~out_wimask_461; // @[RegisterRouter.scala:87:24] wire _out_T_4798 = ~out_romask_461; // @[RegisterRouter.scala:87:24] wire _out_T_4799 = ~out_womask_461; // @[RegisterRouter.scala:87:24] wire out_rimask_462 = |_out_rimask_T_462; // @[RegisterRouter.scala:87:24] wire out_wimask_462 = &_out_wimask_T_462; // @[RegisterRouter.scala:87:24] wire out_romask_462 = |_out_romask_T_462; // @[RegisterRouter.scala:87:24] wire out_womask_462 = &_out_womask_T_462; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_462 = out_rivalid_1_316 & out_rimask_462; // @[RegisterRouter.scala:87:24] wire _out_T_4803 = out_f_rivalid_462; // @[RegisterRouter.scala:87:24] wire out_f_roready_462 = out_roready_1_316 & out_romask_462; // @[RegisterRouter.scala:87:24] wire _out_T_4804 = out_f_roready_462; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_462 = out_wivalid_1_316 & out_wimask_462; // @[RegisterRouter.scala:87:24] wire out_f_woready_462 = out_woready_1_316 & out_womask_462; // @[RegisterRouter.scala:87:24] wire _out_T_4805 = ~out_rimask_462; // @[RegisterRouter.scala:87:24] wire _out_T_4806 = ~out_wimask_462; // @[RegisterRouter.scala:87:24] wire _out_T_4807 = ~out_romask_462; // @[RegisterRouter.scala:87:24] wire _out_T_4808 = ~out_womask_462; // @[RegisterRouter.scala:87:24] wire out_rimask_463 = |_out_rimask_T_463; // @[RegisterRouter.scala:87:24] wire out_wimask_463 = &_out_wimask_T_463; // @[RegisterRouter.scala:87:24] wire out_romask_463 = |_out_romask_T_463; // @[RegisterRouter.scala:87:24] wire out_womask_463 = &_out_womask_T_463; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_463 = out_rivalid_1_317 & out_rimask_463; // @[RegisterRouter.scala:87:24] wire _out_T_4812 = out_f_rivalid_463; // @[RegisterRouter.scala:87:24] wire out_f_roready_463 = out_roready_1_317 & out_romask_463; // @[RegisterRouter.scala:87:24] wire _out_T_4813 = out_f_roready_463; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_463 = out_wivalid_1_317 & out_wimask_463; // @[RegisterRouter.scala:87:24] wire out_f_woready_463 = out_woready_1_317 & out_womask_463; // @[RegisterRouter.scala:87:24] wire _out_T_4814 = ~out_rimask_463; // @[RegisterRouter.scala:87:24] wire _out_T_4815 = ~out_wimask_463; // @[RegisterRouter.scala:87:24] wire _out_T_4816 = ~out_romask_463; // @[RegisterRouter.scala:87:24] wire _out_T_4817 = ~out_womask_463; // @[RegisterRouter.scala:87:24] wire out_rimask_464 = |_out_rimask_T_464; // @[RegisterRouter.scala:87:24] wire out_wimask_464 = &_out_wimask_T_464; // @[RegisterRouter.scala:87:24] wire out_romask_464 = |_out_romask_T_464; // @[RegisterRouter.scala:87:24] wire out_womask_464 = &_out_womask_T_464; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_464 = out_rivalid_1_318 & out_rimask_464; // @[RegisterRouter.scala:87:24] wire _out_T_4821 = out_f_rivalid_464; // @[RegisterRouter.scala:87:24] wire out_f_roready_464 = out_roready_1_318 & out_romask_464; // @[RegisterRouter.scala:87:24] wire _out_T_4822 = out_f_roready_464; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_464 = out_wivalid_1_318 & out_wimask_464; // @[RegisterRouter.scala:87:24] wire out_f_woready_464 = out_woready_1_318 & out_womask_464; // @[RegisterRouter.scala:87:24] wire _out_T_4823 = ~out_rimask_464; // @[RegisterRouter.scala:87:24] wire _out_T_4824 = ~out_wimask_464; // @[RegisterRouter.scala:87:24] wire _out_T_4825 = ~out_romask_464; // @[RegisterRouter.scala:87:24] wire _out_T_4826 = ~out_womask_464; // @[RegisterRouter.scala:87:24] wire out_rimask_465 = |_out_rimask_T_465; // @[RegisterRouter.scala:87:24] wire out_wimask_465 = &_out_wimask_T_465; // @[RegisterRouter.scala:87:24] wire out_romask_465 = |_out_romask_T_465; // @[RegisterRouter.scala:87:24] wire out_womask_465 = &_out_womask_T_465; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_465 = out_rivalid_1_319 & out_rimask_465; // @[RegisterRouter.scala:87:24] wire _out_T_4830 = out_f_rivalid_465; // @[RegisterRouter.scala:87:24] wire out_f_roready_465 = out_roready_1_319 & out_romask_465; // @[RegisterRouter.scala:87:24] wire _out_T_4831 = out_f_roready_465; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_465 = out_wivalid_1_319 & out_wimask_465; // @[RegisterRouter.scala:87:24] wire out_f_woready_465 = out_woready_1_319 & out_womask_465; // @[RegisterRouter.scala:87:24] wire _out_T_4832 = ~out_rimask_465; // @[RegisterRouter.scala:87:24] wire _out_T_4833 = ~out_wimask_465; // @[RegisterRouter.scala:87:24] wire _out_T_4834 = ~out_romask_465; // @[RegisterRouter.scala:87:24] wire _out_T_4835 = ~out_womask_465; // @[RegisterRouter.scala:87:24] wire out_rimask_466 = |_out_rimask_T_466; // @[RegisterRouter.scala:87:24] wire out_wimask_466 = &_out_wimask_T_466; // @[RegisterRouter.scala:87:24] wire out_romask_466 = |_out_romask_T_466; // @[RegisterRouter.scala:87:24] wire out_womask_466 = &_out_womask_T_466; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_466 = out_rivalid_1_320 & out_rimask_466; // @[RegisterRouter.scala:87:24] wire _out_T_4839 = out_f_rivalid_466; // @[RegisterRouter.scala:87:24] wire out_f_roready_466 = out_roready_1_320 & out_romask_466; // @[RegisterRouter.scala:87:24] wire _out_T_4840 = out_f_roready_466; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_466 = out_wivalid_1_320 & out_wimask_466; // @[RegisterRouter.scala:87:24] wire out_f_woready_466 = out_woready_1_320 & out_womask_466; // @[RegisterRouter.scala:87:24] wire _out_T_4841 = ~out_rimask_466; // @[RegisterRouter.scala:87:24] wire _out_T_4842 = ~out_wimask_466; // @[RegisterRouter.scala:87:24] wire _out_T_4843 = ~out_romask_466; // @[RegisterRouter.scala:87:24] wire _out_T_4844 = ~out_womask_466; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4846 = _out_T_4845; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_392 = _out_T_4846; // @[RegisterRouter.scala:87:24] wire out_rimask_467 = |_out_rimask_T_467; // @[RegisterRouter.scala:87:24] wire out_wimask_467 = &_out_wimask_T_467; // @[RegisterRouter.scala:87:24] wire out_romask_467 = |_out_romask_T_467; // @[RegisterRouter.scala:87:24] wire out_womask_467 = &_out_womask_T_467; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_467 = out_rivalid_1_321 & out_rimask_467; // @[RegisterRouter.scala:87:24] wire _out_T_4848 = out_f_rivalid_467; // @[RegisterRouter.scala:87:24] wire out_f_roready_467 = out_roready_1_321 & out_romask_467; // @[RegisterRouter.scala:87:24] wire _out_T_4849 = out_f_roready_467; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_467 = out_wivalid_1_321 & out_wimask_467; // @[RegisterRouter.scala:87:24] wire out_f_woready_467 = out_woready_1_321 & out_womask_467; // @[RegisterRouter.scala:87:24] wire _out_T_4850 = ~out_rimask_467; // @[RegisterRouter.scala:87:24] wire _out_T_4851 = ~out_wimask_467; // @[RegisterRouter.scala:87:24] wire _out_T_4852 = ~out_romask_467; // @[RegisterRouter.scala:87:24] wire _out_T_4853 = ~out_womask_467; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_392 = {hi_258, flags_0_go, _out_prepend_T_392}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4854 = out_prepend_392; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4855 = _out_T_4854; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_393 = _out_T_4855; // @[RegisterRouter.scala:87:24] wire out_rimask_468 = |_out_rimask_T_468; // @[RegisterRouter.scala:87:24] wire out_wimask_468 = &_out_wimask_T_468; // @[RegisterRouter.scala:87:24] wire out_romask_468 = |_out_romask_T_468; // @[RegisterRouter.scala:87:24] wire out_womask_468 = &_out_womask_T_468; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_468 = out_rivalid_1_322 & out_rimask_468; // @[RegisterRouter.scala:87:24] wire _out_T_4857 = out_f_rivalid_468; // @[RegisterRouter.scala:87:24] wire out_f_roready_468 = out_roready_1_322 & out_romask_468; // @[RegisterRouter.scala:87:24] wire _out_T_4858 = out_f_roready_468; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_468 = out_wivalid_1_322 & out_wimask_468; // @[RegisterRouter.scala:87:24] wire out_f_woready_468 = out_woready_1_322 & out_womask_468; // @[RegisterRouter.scala:87:24] wire _out_T_4859 = ~out_rimask_468; // @[RegisterRouter.scala:87:24] wire _out_T_4860 = ~out_wimask_468; // @[RegisterRouter.scala:87:24] wire _out_T_4861 = ~out_romask_468; // @[RegisterRouter.scala:87:24] wire _out_T_4862 = ~out_womask_468; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_393 = {hi_259, flags_0_go, _out_prepend_T_393}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4863 = out_prepend_393; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4864 = _out_T_4863; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_394 = _out_T_4864; // @[RegisterRouter.scala:87:24] wire out_rimask_469 = |_out_rimask_T_469; // @[RegisterRouter.scala:87:24] wire out_wimask_469 = &_out_wimask_T_469; // @[RegisterRouter.scala:87:24] wire out_romask_469 = |_out_romask_T_469; // @[RegisterRouter.scala:87:24] wire out_womask_469 = &_out_womask_T_469; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_469 = out_rivalid_1_323 & out_rimask_469; // @[RegisterRouter.scala:87:24] wire _out_T_4866 = out_f_rivalid_469; // @[RegisterRouter.scala:87:24] wire out_f_roready_469 = out_roready_1_323 & out_romask_469; // @[RegisterRouter.scala:87:24] wire _out_T_4867 = out_f_roready_469; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_469 = out_wivalid_1_323 & out_wimask_469; // @[RegisterRouter.scala:87:24] wire out_f_woready_469 = out_woready_1_323 & out_womask_469; // @[RegisterRouter.scala:87:24] wire _out_T_4868 = ~out_rimask_469; // @[RegisterRouter.scala:87:24] wire _out_T_4869 = ~out_wimask_469; // @[RegisterRouter.scala:87:24] wire _out_T_4870 = ~out_romask_469; // @[RegisterRouter.scala:87:24] wire _out_T_4871 = ~out_womask_469; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_394 = {hi_260, flags_0_go, _out_prepend_T_394}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4872 = out_prepend_394; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4873 = _out_T_4872; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_395 = _out_T_4873; // @[RegisterRouter.scala:87:24] wire out_rimask_470 = |_out_rimask_T_470; // @[RegisterRouter.scala:87:24] wire out_wimask_470 = &_out_wimask_T_470; // @[RegisterRouter.scala:87:24] wire out_romask_470 = |_out_romask_T_470; // @[RegisterRouter.scala:87:24] wire out_womask_470 = &_out_womask_T_470; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_470 = out_rivalid_1_324 & out_rimask_470; // @[RegisterRouter.scala:87:24] wire _out_T_4875 = out_f_rivalid_470; // @[RegisterRouter.scala:87:24] wire out_f_roready_470 = out_roready_1_324 & out_romask_470; // @[RegisterRouter.scala:87:24] wire _out_T_4876 = out_f_roready_470; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_470 = out_wivalid_1_324 & out_wimask_470; // @[RegisterRouter.scala:87:24] wire out_f_woready_470 = out_woready_1_324 & out_womask_470; // @[RegisterRouter.scala:87:24] wire _out_T_4877 = ~out_rimask_470; // @[RegisterRouter.scala:87:24] wire _out_T_4878 = ~out_wimask_470; // @[RegisterRouter.scala:87:24] wire _out_T_4879 = ~out_romask_470; // @[RegisterRouter.scala:87:24] wire _out_T_4880 = ~out_womask_470; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_395 = {hi_261, flags_0_go, _out_prepend_T_395}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4881 = out_prepend_395; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4882 = _out_T_4881; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_396 = _out_T_4882; // @[RegisterRouter.scala:87:24] wire out_rimask_471 = |_out_rimask_T_471; // @[RegisterRouter.scala:87:24] wire out_wimask_471 = &_out_wimask_T_471; // @[RegisterRouter.scala:87:24] wire out_romask_471 = |_out_romask_T_471; // @[RegisterRouter.scala:87:24] wire out_womask_471 = &_out_womask_T_471; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_471 = out_rivalid_1_325 & out_rimask_471; // @[RegisterRouter.scala:87:24] wire _out_T_4884 = out_f_rivalid_471; // @[RegisterRouter.scala:87:24] wire out_f_roready_471 = out_roready_1_325 & out_romask_471; // @[RegisterRouter.scala:87:24] wire _out_T_4885 = out_f_roready_471; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_471 = out_wivalid_1_325 & out_wimask_471; // @[RegisterRouter.scala:87:24] wire out_f_woready_471 = out_woready_1_325 & out_womask_471; // @[RegisterRouter.scala:87:24] wire _out_T_4886 = ~out_rimask_471; // @[RegisterRouter.scala:87:24] wire _out_T_4887 = ~out_wimask_471; // @[RegisterRouter.scala:87:24] wire _out_T_4888 = ~out_romask_471; // @[RegisterRouter.scala:87:24] wire _out_T_4889 = ~out_womask_471; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_396 = {hi_262, flags_0_go, _out_prepend_T_396}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4890 = out_prepend_396; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4891 = _out_T_4890; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_397 = _out_T_4891; // @[RegisterRouter.scala:87:24] wire out_rimask_472 = |_out_rimask_T_472; // @[RegisterRouter.scala:87:24] wire out_wimask_472 = &_out_wimask_T_472; // @[RegisterRouter.scala:87:24] wire out_romask_472 = |_out_romask_T_472; // @[RegisterRouter.scala:87:24] wire out_womask_472 = &_out_womask_T_472; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_472 = out_rivalid_1_326 & out_rimask_472; // @[RegisterRouter.scala:87:24] wire _out_T_4893 = out_f_rivalid_472; // @[RegisterRouter.scala:87:24] wire out_f_roready_472 = out_roready_1_326 & out_romask_472; // @[RegisterRouter.scala:87:24] wire _out_T_4894 = out_f_roready_472; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_472 = out_wivalid_1_326 & out_wimask_472; // @[RegisterRouter.scala:87:24] wire out_f_woready_472 = out_woready_1_326 & out_womask_472; // @[RegisterRouter.scala:87:24] wire _out_T_4895 = ~out_rimask_472; // @[RegisterRouter.scala:87:24] wire _out_T_4896 = ~out_wimask_472; // @[RegisterRouter.scala:87:24] wire _out_T_4897 = ~out_romask_472; // @[RegisterRouter.scala:87:24] wire _out_T_4898 = ~out_womask_472; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_397 = {hi_263, flags_0_go, _out_prepend_T_397}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4899 = out_prepend_397; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4900 = _out_T_4899; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_398 = _out_T_4900; // @[RegisterRouter.scala:87:24] wire out_rimask_473 = |_out_rimask_T_473; // @[RegisterRouter.scala:87:24] wire out_wimask_473 = &_out_wimask_T_473; // @[RegisterRouter.scala:87:24] wire out_romask_473 = |_out_romask_T_473; // @[RegisterRouter.scala:87:24] wire out_womask_473 = &_out_womask_T_473; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_473 = out_rivalid_1_327 & out_rimask_473; // @[RegisterRouter.scala:87:24] wire _out_T_4902 = out_f_rivalid_473; // @[RegisterRouter.scala:87:24] wire out_f_roready_473 = out_roready_1_327 & out_romask_473; // @[RegisterRouter.scala:87:24] wire _out_T_4903 = out_f_roready_473; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_473 = out_wivalid_1_327 & out_wimask_473; // @[RegisterRouter.scala:87:24] wire out_f_woready_473 = out_woready_1_327 & out_womask_473; // @[RegisterRouter.scala:87:24] wire _out_T_4904 = ~out_rimask_473; // @[RegisterRouter.scala:87:24] wire _out_T_4905 = ~out_wimask_473; // @[RegisterRouter.scala:87:24] wire _out_T_4906 = ~out_romask_473; // @[RegisterRouter.scala:87:24] wire _out_T_4907 = ~out_womask_473; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_398 = {hi_264, flags_0_go, _out_prepend_T_398}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4908 = out_prepend_398; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4909 = _out_T_4908; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_160 = _out_T_4909; // @[MuxLiteral.scala:49:48] wire out_rimask_474 = |_out_rimask_T_474; // @[RegisterRouter.scala:87:24] wire out_wimask_474 = &_out_wimask_T_474; // @[RegisterRouter.scala:87:24] wire out_romask_474 = |_out_romask_T_474; // @[RegisterRouter.scala:87:24] wire out_womask_474 = &_out_womask_T_474; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_474 = out_rivalid_1_328 & out_rimask_474; // @[RegisterRouter.scala:87:24] wire _out_T_4911 = out_f_rivalid_474; // @[RegisterRouter.scala:87:24] wire out_f_roready_474 = out_roready_1_328 & out_romask_474; // @[RegisterRouter.scala:87:24] wire _out_T_4912 = out_f_roready_474; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_474 = out_wivalid_1_328 & out_wimask_474; // @[RegisterRouter.scala:87:24] wire out_f_woready_474 = out_woready_1_328 & out_womask_474; // @[RegisterRouter.scala:87:24] wire _out_T_4913 = ~out_rimask_474; // @[RegisterRouter.scala:87:24] wire _out_T_4914 = ~out_wimask_474; // @[RegisterRouter.scala:87:24] wire _out_T_4915 = ~out_romask_474; // @[RegisterRouter.scala:87:24] wire _out_T_4916 = ~out_womask_474; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4918 = _out_T_4917; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_399 = _out_T_4918; // @[RegisterRouter.scala:87:24] wire out_rimask_475 = |_out_rimask_T_475; // @[RegisterRouter.scala:87:24] wire out_wimask_475 = &_out_wimask_T_475; // @[RegisterRouter.scala:87:24] wire out_romask_475 = |_out_romask_T_475; // @[RegisterRouter.scala:87:24] wire out_womask_475 = &_out_womask_T_475; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_475 = out_rivalid_1_329 & out_rimask_475; // @[RegisterRouter.scala:87:24] wire _out_T_4920 = out_f_rivalid_475; // @[RegisterRouter.scala:87:24] wire out_f_roready_475 = out_roready_1_329 & out_romask_475; // @[RegisterRouter.scala:87:24] wire _out_T_4921 = out_f_roready_475; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_475 = out_wivalid_1_329 & out_wimask_475; // @[RegisterRouter.scala:87:24] wire out_f_woready_475 = out_woready_1_329 & out_womask_475; // @[RegisterRouter.scala:87:24] wire _out_T_4922 = ~out_rimask_475; // @[RegisterRouter.scala:87:24] wire _out_T_4923 = ~out_wimask_475; // @[RegisterRouter.scala:87:24] wire _out_T_4924 = ~out_romask_475; // @[RegisterRouter.scala:87:24] wire _out_T_4925 = ~out_womask_475; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_399 = {hi_514, flags_0_go, _out_prepend_T_399}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4926 = out_prepend_399; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4927 = _out_T_4926; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_400 = _out_T_4927; // @[RegisterRouter.scala:87:24] wire out_rimask_476 = |_out_rimask_T_476; // @[RegisterRouter.scala:87:24] wire out_wimask_476 = &_out_wimask_T_476; // @[RegisterRouter.scala:87:24] wire out_romask_476 = |_out_romask_T_476; // @[RegisterRouter.scala:87:24] wire out_womask_476 = &_out_womask_T_476; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_476 = out_rivalid_1_330 & out_rimask_476; // @[RegisterRouter.scala:87:24] wire _out_T_4929 = out_f_rivalid_476; // @[RegisterRouter.scala:87:24] wire out_f_roready_476 = out_roready_1_330 & out_romask_476; // @[RegisterRouter.scala:87:24] wire _out_T_4930 = out_f_roready_476; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_476 = out_wivalid_1_330 & out_wimask_476; // @[RegisterRouter.scala:87:24] wire out_f_woready_476 = out_woready_1_330 & out_womask_476; // @[RegisterRouter.scala:87:24] wire _out_T_4931 = ~out_rimask_476; // @[RegisterRouter.scala:87:24] wire _out_T_4932 = ~out_wimask_476; // @[RegisterRouter.scala:87:24] wire _out_T_4933 = ~out_romask_476; // @[RegisterRouter.scala:87:24] wire _out_T_4934 = ~out_womask_476; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_400 = {hi_515, flags_0_go, _out_prepend_T_400}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4935 = out_prepend_400; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4936 = _out_T_4935; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_401 = _out_T_4936; // @[RegisterRouter.scala:87:24] wire out_rimask_477 = |_out_rimask_T_477; // @[RegisterRouter.scala:87:24] wire out_wimask_477 = &_out_wimask_T_477; // @[RegisterRouter.scala:87:24] wire out_romask_477 = |_out_romask_T_477; // @[RegisterRouter.scala:87:24] wire out_womask_477 = &_out_womask_T_477; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_477 = out_rivalid_1_331 & out_rimask_477; // @[RegisterRouter.scala:87:24] wire _out_T_4938 = out_f_rivalid_477; // @[RegisterRouter.scala:87:24] wire out_f_roready_477 = out_roready_1_331 & out_romask_477; // @[RegisterRouter.scala:87:24] wire _out_T_4939 = out_f_roready_477; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_477 = out_wivalid_1_331 & out_wimask_477; // @[RegisterRouter.scala:87:24] wire out_f_woready_477 = out_woready_1_331 & out_womask_477; // @[RegisterRouter.scala:87:24] wire _out_T_4940 = ~out_rimask_477; // @[RegisterRouter.scala:87:24] wire _out_T_4941 = ~out_wimask_477; // @[RegisterRouter.scala:87:24] wire _out_T_4942 = ~out_romask_477; // @[RegisterRouter.scala:87:24] wire _out_T_4943 = ~out_womask_477; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_401 = {hi_516, flags_0_go, _out_prepend_T_401}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4944 = out_prepend_401; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4945 = _out_T_4944; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_402 = _out_T_4945; // @[RegisterRouter.scala:87:24] wire out_rimask_478 = |_out_rimask_T_478; // @[RegisterRouter.scala:87:24] wire out_wimask_478 = &_out_wimask_T_478; // @[RegisterRouter.scala:87:24] wire out_romask_478 = |_out_romask_T_478; // @[RegisterRouter.scala:87:24] wire out_womask_478 = &_out_womask_T_478; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_478 = out_rivalid_1_332 & out_rimask_478; // @[RegisterRouter.scala:87:24] wire _out_T_4947 = out_f_rivalid_478; // @[RegisterRouter.scala:87:24] wire out_f_roready_478 = out_roready_1_332 & out_romask_478; // @[RegisterRouter.scala:87:24] wire _out_T_4948 = out_f_roready_478; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_478 = out_wivalid_1_332 & out_wimask_478; // @[RegisterRouter.scala:87:24] wire out_f_woready_478 = out_woready_1_332 & out_womask_478; // @[RegisterRouter.scala:87:24] wire _out_T_4949 = ~out_rimask_478; // @[RegisterRouter.scala:87:24] wire _out_T_4950 = ~out_wimask_478; // @[RegisterRouter.scala:87:24] wire _out_T_4951 = ~out_romask_478; // @[RegisterRouter.scala:87:24] wire _out_T_4952 = ~out_womask_478; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_402 = {hi_517, flags_0_go, _out_prepend_T_402}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4953 = out_prepend_402; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4954 = _out_T_4953; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_403 = _out_T_4954; // @[RegisterRouter.scala:87:24] wire out_rimask_479 = |_out_rimask_T_479; // @[RegisterRouter.scala:87:24] wire out_wimask_479 = &_out_wimask_T_479; // @[RegisterRouter.scala:87:24] wire out_romask_479 = |_out_romask_T_479; // @[RegisterRouter.scala:87:24] wire out_womask_479 = &_out_womask_T_479; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_479 = out_rivalid_1_333 & out_rimask_479; // @[RegisterRouter.scala:87:24] wire _out_T_4956 = out_f_rivalid_479; // @[RegisterRouter.scala:87:24] wire out_f_roready_479 = out_roready_1_333 & out_romask_479; // @[RegisterRouter.scala:87:24] wire _out_T_4957 = out_f_roready_479; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_479 = out_wivalid_1_333 & out_wimask_479; // @[RegisterRouter.scala:87:24] wire out_f_woready_479 = out_woready_1_333 & out_womask_479; // @[RegisterRouter.scala:87:24] wire _out_T_4958 = ~out_rimask_479; // @[RegisterRouter.scala:87:24] wire _out_T_4959 = ~out_wimask_479; // @[RegisterRouter.scala:87:24] wire _out_T_4960 = ~out_romask_479; // @[RegisterRouter.scala:87:24] wire _out_T_4961 = ~out_womask_479; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_403 = {hi_518, flags_0_go, _out_prepend_T_403}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4962 = out_prepend_403; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4963 = _out_T_4962; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_404 = _out_T_4963; // @[RegisterRouter.scala:87:24] wire out_rimask_480 = |_out_rimask_T_480; // @[RegisterRouter.scala:87:24] wire out_wimask_480 = &_out_wimask_T_480; // @[RegisterRouter.scala:87:24] wire out_romask_480 = |_out_romask_T_480; // @[RegisterRouter.scala:87:24] wire out_womask_480 = &_out_womask_T_480; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_480 = out_rivalid_1_334 & out_rimask_480; // @[RegisterRouter.scala:87:24] wire _out_T_4965 = out_f_rivalid_480; // @[RegisterRouter.scala:87:24] wire out_f_roready_480 = out_roready_1_334 & out_romask_480; // @[RegisterRouter.scala:87:24] wire _out_T_4966 = out_f_roready_480; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_480 = out_wivalid_1_334 & out_wimask_480; // @[RegisterRouter.scala:87:24] wire out_f_woready_480 = out_woready_1_334 & out_womask_480; // @[RegisterRouter.scala:87:24] wire _out_T_4967 = ~out_rimask_480; // @[RegisterRouter.scala:87:24] wire _out_T_4968 = ~out_wimask_480; // @[RegisterRouter.scala:87:24] wire _out_T_4969 = ~out_romask_480; // @[RegisterRouter.scala:87:24] wire _out_T_4970 = ~out_womask_480; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_404 = {hi_519, flags_0_go, _out_prepend_T_404}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4971 = out_prepend_404; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4972 = _out_T_4971; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_405 = _out_T_4972; // @[RegisterRouter.scala:87:24] wire out_rimask_481 = |_out_rimask_T_481; // @[RegisterRouter.scala:87:24] wire out_wimask_481 = &_out_wimask_T_481; // @[RegisterRouter.scala:87:24] wire out_romask_481 = |_out_romask_T_481; // @[RegisterRouter.scala:87:24] wire out_womask_481 = &_out_womask_T_481; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_481 = out_rivalid_1_335 & out_rimask_481; // @[RegisterRouter.scala:87:24] wire _out_T_4974 = out_f_rivalid_481; // @[RegisterRouter.scala:87:24] wire out_f_roready_481 = out_roready_1_335 & out_romask_481; // @[RegisterRouter.scala:87:24] wire _out_T_4975 = out_f_roready_481; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_481 = out_wivalid_1_335 & out_wimask_481; // @[RegisterRouter.scala:87:24] wire out_f_woready_481 = out_woready_1_335 & out_womask_481; // @[RegisterRouter.scala:87:24] wire _out_T_4976 = ~out_rimask_481; // @[RegisterRouter.scala:87:24] wire _out_T_4977 = ~out_wimask_481; // @[RegisterRouter.scala:87:24] wire _out_T_4978 = ~out_romask_481; // @[RegisterRouter.scala:87:24] wire _out_T_4979 = ~out_womask_481; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_405 = {hi_520, flags_0_go, _out_prepend_T_405}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4980 = out_prepend_405; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4981 = _out_T_4980; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_192 = _out_T_4981; // @[MuxLiteral.scala:49:48] wire out_rimask_482 = |_out_rimask_T_482; // @[RegisterRouter.scala:87:24] wire out_wimask_482 = &_out_wimask_T_482; // @[RegisterRouter.scala:87:24] wire out_romask_482 = |_out_romask_T_482; // @[RegisterRouter.scala:87:24] wire out_womask_482 = &_out_womask_T_482; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_482 = out_rivalid_1_336 & out_rimask_482; // @[RegisterRouter.scala:87:24] wire _out_T_4983 = out_f_rivalid_482; // @[RegisterRouter.scala:87:24] wire out_f_roready_482 = out_roready_1_336 & out_romask_482; // @[RegisterRouter.scala:87:24] wire _out_T_4984 = out_f_roready_482; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_482 = out_wivalid_1_336 & out_wimask_482; // @[RegisterRouter.scala:87:24] wire out_f_woready_482 = out_woready_1_336 & out_womask_482; // @[RegisterRouter.scala:87:24] wire _out_T_4985 = ~out_rimask_482; // @[RegisterRouter.scala:87:24] wire _out_T_4986 = ~out_wimask_482; // @[RegisterRouter.scala:87:24] wire _out_T_4987 = ~out_romask_482; // @[RegisterRouter.scala:87:24] wire _out_T_4988 = ~out_womask_482; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4990 = _out_T_4989; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_406 = _out_T_4990; // @[RegisterRouter.scala:87:24] wire out_rimask_483 = |_out_rimask_T_483; // @[RegisterRouter.scala:87:24] wire out_wimask_483 = &_out_wimask_T_483; // @[RegisterRouter.scala:87:24] wire out_romask_483 = |_out_romask_T_483; // @[RegisterRouter.scala:87:24] wire out_womask_483 = &_out_womask_T_483; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_483 = out_rivalid_1_337 & out_rimask_483; // @[RegisterRouter.scala:87:24] wire _out_T_4992 = out_f_rivalid_483; // @[RegisterRouter.scala:87:24] wire out_f_roready_483 = out_roready_1_337 & out_romask_483; // @[RegisterRouter.scala:87:24] wire _out_T_4993 = out_f_roready_483; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_483 = out_wivalid_1_337 & out_wimask_483; // @[RegisterRouter.scala:87:24] wire out_f_woready_483 = out_woready_1_337 & out_womask_483; // @[RegisterRouter.scala:87:24] wire _out_T_4994 = ~out_rimask_483; // @[RegisterRouter.scala:87:24] wire _out_T_4995 = ~out_wimask_483; // @[RegisterRouter.scala:87:24] wire _out_T_4996 = ~out_romask_483; // @[RegisterRouter.scala:87:24] wire _out_T_4997 = ~out_womask_483; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_406 = {hi_74, flags_0_go, _out_prepend_T_406}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4998 = out_prepend_406; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4999 = _out_T_4998; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_407 = _out_T_4999; // @[RegisterRouter.scala:87:24] wire out_rimask_484 = |_out_rimask_T_484; // @[RegisterRouter.scala:87:24] wire out_wimask_484 = &_out_wimask_T_484; // @[RegisterRouter.scala:87:24] wire out_romask_484 = |_out_romask_T_484; // @[RegisterRouter.scala:87:24] wire out_womask_484 = &_out_womask_T_484; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_484 = out_rivalid_1_338 & out_rimask_484; // @[RegisterRouter.scala:87:24] wire _out_T_5001 = out_f_rivalid_484; // @[RegisterRouter.scala:87:24] wire out_f_roready_484 = out_roready_1_338 & out_romask_484; // @[RegisterRouter.scala:87:24] wire _out_T_5002 = out_f_roready_484; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_484 = out_wivalid_1_338 & out_wimask_484; // @[RegisterRouter.scala:87:24] wire out_f_woready_484 = out_woready_1_338 & out_womask_484; // @[RegisterRouter.scala:87:24] wire _out_T_5003 = ~out_rimask_484; // @[RegisterRouter.scala:87:24] wire _out_T_5004 = ~out_wimask_484; // @[RegisterRouter.scala:87:24] wire _out_T_5005 = ~out_romask_484; // @[RegisterRouter.scala:87:24] wire _out_T_5006 = ~out_womask_484; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_407 = {hi_75, flags_0_go, _out_prepend_T_407}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5007 = out_prepend_407; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5008 = _out_T_5007; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_408 = _out_T_5008; // @[RegisterRouter.scala:87:24] wire out_rimask_485 = |_out_rimask_T_485; // @[RegisterRouter.scala:87:24] wire out_wimask_485 = &_out_wimask_T_485; // @[RegisterRouter.scala:87:24] wire out_romask_485 = |_out_romask_T_485; // @[RegisterRouter.scala:87:24] wire out_womask_485 = &_out_womask_T_485; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_485 = out_rivalid_1_339 & out_rimask_485; // @[RegisterRouter.scala:87:24] wire _out_T_5010 = out_f_rivalid_485; // @[RegisterRouter.scala:87:24] wire out_f_roready_485 = out_roready_1_339 & out_romask_485; // @[RegisterRouter.scala:87:24] wire _out_T_5011 = out_f_roready_485; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_485 = out_wivalid_1_339 & out_wimask_485; // @[RegisterRouter.scala:87:24] wire out_f_woready_485 = out_woready_1_339 & out_womask_485; // @[RegisterRouter.scala:87:24] wire _out_T_5012 = ~out_rimask_485; // @[RegisterRouter.scala:87:24] wire _out_T_5013 = ~out_wimask_485; // @[RegisterRouter.scala:87:24] wire _out_T_5014 = ~out_romask_485; // @[RegisterRouter.scala:87:24] wire _out_T_5015 = ~out_womask_485; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_408 = {hi_76, flags_0_go, _out_prepend_T_408}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5016 = out_prepend_408; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5017 = _out_T_5016; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_409 = _out_T_5017; // @[RegisterRouter.scala:87:24] wire out_rimask_486 = |_out_rimask_T_486; // @[RegisterRouter.scala:87:24] wire out_wimask_486 = &_out_wimask_T_486; // @[RegisterRouter.scala:87:24] wire out_romask_486 = |_out_romask_T_486; // @[RegisterRouter.scala:87:24] wire out_womask_486 = &_out_womask_T_486; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_486 = out_rivalid_1_340 & out_rimask_486; // @[RegisterRouter.scala:87:24] wire _out_T_5019 = out_f_rivalid_486; // @[RegisterRouter.scala:87:24] wire out_f_roready_486 = out_roready_1_340 & out_romask_486; // @[RegisterRouter.scala:87:24] wire _out_T_5020 = out_f_roready_486; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_486 = out_wivalid_1_340 & out_wimask_486; // @[RegisterRouter.scala:87:24] wire out_f_woready_486 = out_woready_1_340 & out_womask_486; // @[RegisterRouter.scala:87:24] wire _out_T_5021 = ~out_rimask_486; // @[RegisterRouter.scala:87:24] wire _out_T_5022 = ~out_wimask_486; // @[RegisterRouter.scala:87:24] wire _out_T_5023 = ~out_romask_486; // @[RegisterRouter.scala:87:24] wire _out_T_5024 = ~out_womask_486; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_409 = {hi_77, flags_0_go, _out_prepend_T_409}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5025 = out_prepend_409; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5026 = _out_T_5025; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_410 = _out_T_5026; // @[RegisterRouter.scala:87:24] wire out_rimask_487 = |_out_rimask_T_487; // @[RegisterRouter.scala:87:24] wire out_wimask_487 = &_out_wimask_T_487; // @[RegisterRouter.scala:87:24] wire out_romask_487 = |_out_romask_T_487; // @[RegisterRouter.scala:87:24] wire out_womask_487 = &_out_womask_T_487; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_487 = out_rivalid_1_341 & out_rimask_487; // @[RegisterRouter.scala:87:24] wire _out_T_5028 = out_f_rivalid_487; // @[RegisterRouter.scala:87:24] wire out_f_roready_487 = out_roready_1_341 & out_romask_487; // @[RegisterRouter.scala:87:24] wire _out_T_5029 = out_f_roready_487; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_487 = out_wivalid_1_341 & out_wimask_487; // @[RegisterRouter.scala:87:24] wire out_f_woready_487 = out_woready_1_341 & out_womask_487; // @[RegisterRouter.scala:87:24] wire _out_T_5030 = ~out_rimask_487; // @[RegisterRouter.scala:87:24] wire _out_T_5031 = ~out_wimask_487; // @[RegisterRouter.scala:87:24] wire _out_T_5032 = ~out_romask_487; // @[RegisterRouter.scala:87:24] wire _out_T_5033 = ~out_womask_487; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_410 = {hi_78, flags_0_go, _out_prepend_T_410}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5034 = out_prepend_410; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5035 = _out_T_5034; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_411 = _out_T_5035; // @[RegisterRouter.scala:87:24] wire out_rimask_488 = |_out_rimask_T_488; // @[RegisterRouter.scala:87:24] wire out_wimask_488 = &_out_wimask_T_488; // @[RegisterRouter.scala:87:24] wire out_romask_488 = |_out_romask_T_488; // @[RegisterRouter.scala:87:24] wire out_womask_488 = &_out_womask_T_488; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_488 = out_rivalid_1_342 & out_rimask_488; // @[RegisterRouter.scala:87:24] wire _out_T_5037 = out_f_rivalid_488; // @[RegisterRouter.scala:87:24] wire out_f_roready_488 = out_roready_1_342 & out_romask_488; // @[RegisterRouter.scala:87:24] wire _out_T_5038 = out_f_roready_488; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_488 = out_wivalid_1_342 & out_wimask_488; // @[RegisterRouter.scala:87:24] wire out_f_woready_488 = out_woready_1_342 & out_womask_488; // @[RegisterRouter.scala:87:24] wire _out_T_5039 = ~out_rimask_488; // @[RegisterRouter.scala:87:24] wire _out_T_5040 = ~out_wimask_488; // @[RegisterRouter.scala:87:24] wire _out_T_5041 = ~out_romask_488; // @[RegisterRouter.scala:87:24] wire _out_T_5042 = ~out_womask_488; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_411 = {hi_79, flags_0_go, _out_prepend_T_411}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5043 = out_prepend_411; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5044 = _out_T_5043; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_412 = _out_T_5044; // @[RegisterRouter.scala:87:24] wire out_rimask_489 = |_out_rimask_T_489; // @[RegisterRouter.scala:87:24] wire out_wimask_489 = &_out_wimask_T_489; // @[RegisterRouter.scala:87:24] wire out_romask_489 = |_out_romask_T_489; // @[RegisterRouter.scala:87:24] wire out_womask_489 = &_out_womask_T_489; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_489 = out_rivalid_1_343 & out_rimask_489; // @[RegisterRouter.scala:87:24] wire _out_T_5046 = out_f_rivalid_489; // @[RegisterRouter.scala:87:24] wire out_f_roready_489 = out_roready_1_343 & out_romask_489; // @[RegisterRouter.scala:87:24] wire _out_T_5047 = out_f_roready_489; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_489 = out_wivalid_1_343 & out_wimask_489; // @[RegisterRouter.scala:87:24] wire out_f_woready_489 = out_woready_1_343 & out_womask_489; // @[RegisterRouter.scala:87:24] wire _out_T_5048 = ~out_rimask_489; // @[RegisterRouter.scala:87:24] wire _out_T_5049 = ~out_wimask_489; // @[RegisterRouter.scala:87:24] wire _out_T_5050 = ~out_romask_489; // @[RegisterRouter.scala:87:24] wire _out_T_5051 = ~out_womask_489; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_412 = {hi_80, flags_0_go, _out_prepend_T_412}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5052 = out_prepend_412; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5053 = _out_T_5052; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_137 = _out_T_5053; // @[MuxLiteral.scala:49:48] wire out_rimask_490 = |_out_rimask_T_490; // @[RegisterRouter.scala:87:24] wire out_wimask_490 = &_out_wimask_T_490; // @[RegisterRouter.scala:87:24] wire out_romask_490 = |_out_romask_T_490; // @[RegisterRouter.scala:87:24] wire out_womask_490 = &_out_womask_T_490; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_490 = out_rivalid_1_344 & out_rimask_490; // @[RegisterRouter.scala:87:24] wire _out_T_5055 = out_f_rivalid_490; // @[RegisterRouter.scala:87:24] wire out_f_roready_490 = out_roready_1_344 & out_romask_490; // @[RegisterRouter.scala:87:24] wire _out_T_5056 = out_f_roready_490; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_490 = out_wivalid_1_344 & out_wimask_490; // @[RegisterRouter.scala:87:24] wire out_f_woready_490 = out_woready_1_344 & out_womask_490; // @[RegisterRouter.scala:87:24] wire _out_T_5057 = ~out_rimask_490; // @[RegisterRouter.scala:87:24] wire _out_T_5058 = ~out_wimask_490; // @[RegisterRouter.scala:87:24] wire _out_T_5059 = ~out_romask_490; // @[RegisterRouter.scala:87:24] wire _out_T_5060 = ~out_womask_490; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5062 = _out_T_5061; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_413 = _out_T_5062; // @[RegisterRouter.scala:87:24] wire out_rimask_491 = |_out_rimask_T_491; // @[RegisterRouter.scala:87:24] wire out_wimask_491 = &_out_wimask_T_491; // @[RegisterRouter.scala:87:24] wire out_romask_491 = |_out_romask_T_491; // @[RegisterRouter.scala:87:24] wire out_womask_491 = &_out_womask_T_491; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_491 = out_rivalid_1_345 & out_rimask_491; // @[RegisterRouter.scala:87:24] wire _out_T_5064 = out_f_rivalid_491; // @[RegisterRouter.scala:87:24] wire out_f_roready_491 = out_roready_1_345 & out_romask_491; // @[RegisterRouter.scala:87:24] wire _out_T_5065 = out_f_roready_491; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_491 = out_wivalid_1_345 & out_wimask_491; // @[RegisterRouter.scala:87:24] wire out_f_woready_491 = out_woready_1_345 & out_womask_491; // @[RegisterRouter.scala:87:24] wire _out_T_5066 = ~out_rimask_491; // @[RegisterRouter.scala:87:24] wire _out_T_5067 = ~out_wimask_491; // @[RegisterRouter.scala:87:24] wire _out_T_5068 = ~out_romask_491; // @[RegisterRouter.scala:87:24] wire _out_T_5069 = ~out_womask_491; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_413 = {hi_298, flags_0_go, _out_prepend_T_413}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5070 = out_prepend_413; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5071 = _out_T_5070; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_414 = _out_T_5071; // @[RegisterRouter.scala:87:24] wire out_rimask_492 = |_out_rimask_T_492; // @[RegisterRouter.scala:87:24] wire out_wimask_492 = &_out_wimask_T_492; // @[RegisterRouter.scala:87:24] wire out_romask_492 = |_out_romask_T_492; // @[RegisterRouter.scala:87:24] wire out_womask_492 = &_out_womask_T_492; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_492 = out_rivalid_1_346 & out_rimask_492; // @[RegisterRouter.scala:87:24] wire _out_T_5073 = out_f_rivalid_492; // @[RegisterRouter.scala:87:24] wire out_f_roready_492 = out_roready_1_346 & out_romask_492; // @[RegisterRouter.scala:87:24] wire _out_T_5074 = out_f_roready_492; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_492 = out_wivalid_1_346 & out_wimask_492; // @[RegisterRouter.scala:87:24] wire out_f_woready_492 = out_woready_1_346 & out_womask_492; // @[RegisterRouter.scala:87:24] wire _out_T_5075 = ~out_rimask_492; // @[RegisterRouter.scala:87:24] wire _out_T_5076 = ~out_wimask_492; // @[RegisterRouter.scala:87:24] wire _out_T_5077 = ~out_romask_492; // @[RegisterRouter.scala:87:24] wire _out_T_5078 = ~out_womask_492; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_414 = {hi_299, flags_0_go, _out_prepend_T_414}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5079 = out_prepend_414; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5080 = _out_T_5079; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_415 = _out_T_5080; // @[RegisterRouter.scala:87:24] wire out_rimask_493 = |_out_rimask_T_493; // @[RegisterRouter.scala:87:24] wire out_wimask_493 = &_out_wimask_T_493; // @[RegisterRouter.scala:87:24] wire out_romask_493 = |_out_romask_T_493; // @[RegisterRouter.scala:87:24] wire out_womask_493 = &_out_womask_T_493; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_493 = out_rivalid_1_347 & out_rimask_493; // @[RegisterRouter.scala:87:24] wire _out_T_5082 = out_f_rivalid_493; // @[RegisterRouter.scala:87:24] wire out_f_roready_493 = out_roready_1_347 & out_romask_493; // @[RegisterRouter.scala:87:24] wire _out_T_5083 = out_f_roready_493; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_493 = out_wivalid_1_347 & out_wimask_493; // @[RegisterRouter.scala:87:24] wire out_f_woready_493 = out_woready_1_347 & out_womask_493; // @[RegisterRouter.scala:87:24] wire _out_T_5084 = ~out_rimask_493; // @[RegisterRouter.scala:87:24] wire _out_T_5085 = ~out_wimask_493; // @[RegisterRouter.scala:87:24] wire _out_T_5086 = ~out_romask_493; // @[RegisterRouter.scala:87:24] wire _out_T_5087 = ~out_womask_493; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_415 = {hi_300, flags_0_go, _out_prepend_T_415}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5088 = out_prepend_415; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5089 = _out_T_5088; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_416 = _out_T_5089; // @[RegisterRouter.scala:87:24] wire out_rimask_494 = |_out_rimask_T_494; // @[RegisterRouter.scala:87:24] wire out_wimask_494 = &_out_wimask_T_494; // @[RegisterRouter.scala:87:24] wire out_romask_494 = |_out_romask_T_494; // @[RegisterRouter.scala:87:24] wire out_womask_494 = &_out_womask_T_494; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_494 = out_rivalid_1_348 & out_rimask_494; // @[RegisterRouter.scala:87:24] wire _out_T_5091 = out_f_rivalid_494; // @[RegisterRouter.scala:87:24] wire out_f_roready_494 = out_roready_1_348 & out_romask_494; // @[RegisterRouter.scala:87:24] wire _out_T_5092 = out_f_roready_494; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_494 = out_wivalid_1_348 & out_wimask_494; // @[RegisterRouter.scala:87:24] wire out_f_woready_494 = out_woready_1_348 & out_womask_494; // @[RegisterRouter.scala:87:24] wire _out_T_5093 = ~out_rimask_494; // @[RegisterRouter.scala:87:24] wire _out_T_5094 = ~out_wimask_494; // @[RegisterRouter.scala:87:24] wire _out_T_5095 = ~out_romask_494; // @[RegisterRouter.scala:87:24] wire _out_T_5096 = ~out_womask_494; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_416 = {hi_301, flags_0_go, _out_prepend_T_416}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5097 = out_prepend_416; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5098 = _out_T_5097; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_417 = _out_T_5098; // @[RegisterRouter.scala:87:24] wire out_rimask_495 = |_out_rimask_T_495; // @[RegisterRouter.scala:87:24] wire out_wimask_495 = &_out_wimask_T_495; // @[RegisterRouter.scala:87:24] wire out_romask_495 = |_out_romask_T_495; // @[RegisterRouter.scala:87:24] wire out_womask_495 = &_out_womask_T_495; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_495 = out_rivalid_1_349 & out_rimask_495; // @[RegisterRouter.scala:87:24] wire _out_T_5100 = out_f_rivalid_495; // @[RegisterRouter.scala:87:24] wire out_f_roready_495 = out_roready_1_349 & out_romask_495; // @[RegisterRouter.scala:87:24] wire _out_T_5101 = out_f_roready_495; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_495 = out_wivalid_1_349 & out_wimask_495; // @[RegisterRouter.scala:87:24] wire out_f_woready_495 = out_woready_1_349 & out_womask_495; // @[RegisterRouter.scala:87:24] wire _out_T_5102 = ~out_rimask_495; // @[RegisterRouter.scala:87:24] wire _out_T_5103 = ~out_wimask_495; // @[RegisterRouter.scala:87:24] wire _out_T_5104 = ~out_romask_495; // @[RegisterRouter.scala:87:24] wire _out_T_5105 = ~out_womask_495; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_417 = {hi_302, flags_0_go, _out_prepend_T_417}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5106 = out_prepend_417; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5107 = _out_T_5106; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_418 = _out_T_5107; // @[RegisterRouter.scala:87:24] wire out_rimask_496 = |_out_rimask_T_496; // @[RegisterRouter.scala:87:24] wire out_wimask_496 = &_out_wimask_T_496; // @[RegisterRouter.scala:87:24] wire out_romask_496 = |_out_romask_T_496; // @[RegisterRouter.scala:87:24] wire out_womask_496 = &_out_womask_T_496; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_496 = out_rivalid_1_350 & out_rimask_496; // @[RegisterRouter.scala:87:24] wire _out_T_5109 = out_f_rivalid_496; // @[RegisterRouter.scala:87:24] wire out_f_roready_496 = out_roready_1_350 & out_romask_496; // @[RegisterRouter.scala:87:24] wire _out_T_5110 = out_f_roready_496; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_496 = out_wivalid_1_350 & out_wimask_496; // @[RegisterRouter.scala:87:24] wire out_f_woready_496 = out_woready_1_350 & out_womask_496; // @[RegisterRouter.scala:87:24] wire _out_T_5111 = ~out_rimask_496; // @[RegisterRouter.scala:87:24] wire _out_T_5112 = ~out_wimask_496; // @[RegisterRouter.scala:87:24] wire _out_T_5113 = ~out_romask_496; // @[RegisterRouter.scala:87:24] wire _out_T_5114 = ~out_womask_496; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_418 = {hi_303, flags_0_go, _out_prepend_T_418}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5115 = out_prepend_418; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5116 = _out_T_5115; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_419 = _out_T_5116; // @[RegisterRouter.scala:87:24] wire out_rimask_497 = |_out_rimask_T_497; // @[RegisterRouter.scala:87:24] wire out_wimask_497 = &_out_wimask_T_497; // @[RegisterRouter.scala:87:24] wire out_romask_497 = |_out_romask_T_497; // @[RegisterRouter.scala:87:24] wire out_womask_497 = &_out_womask_T_497; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_497 = out_rivalid_1_351 & out_rimask_497; // @[RegisterRouter.scala:87:24] wire _out_T_5118 = out_f_rivalid_497; // @[RegisterRouter.scala:87:24] wire out_f_roready_497 = out_roready_1_351 & out_romask_497; // @[RegisterRouter.scala:87:24] wire _out_T_5119 = out_f_roready_497; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_497 = out_wivalid_1_351 & out_wimask_497; // @[RegisterRouter.scala:87:24] wire out_f_woready_497 = out_woready_1_351 & out_womask_497; // @[RegisterRouter.scala:87:24] wire _out_T_5120 = ~out_rimask_497; // @[RegisterRouter.scala:87:24] wire _out_T_5121 = ~out_wimask_497; // @[RegisterRouter.scala:87:24] wire _out_T_5122 = ~out_romask_497; // @[RegisterRouter.scala:87:24] wire _out_T_5123 = ~out_womask_497; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_419 = {hi_304, flags_0_go, _out_prepend_T_419}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5124 = out_prepend_419; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5125 = _out_T_5124; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_165 = _out_T_5125; // @[MuxLiteral.scala:49:48] wire [9:0] _out_rimask_T_498 = out_frontMask_1[9:0]; // @[RegisterRouter.scala:87:24] wire [9:0] _out_wimask_T_498 = out_frontMask_1[9:0]; // @[RegisterRouter.scala:87:24] wire [9:0] _out_rimask_T_681 = out_frontMask_1[9:0]; // @[RegisterRouter.scala:87:24] wire [9:0] _out_wimask_T_681 = out_frontMask_1[9:0]; // @[RegisterRouter.scala:87:24] wire out_rimask_498 = |_out_rimask_T_498; // @[RegisterRouter.scala:87:24] wire out_wimask_498 = &_out_wimask_T_498; // @[RegisterRouter.scala:87:24] wire [9:0] _out_romask_T_498 = out_backMask_1[9:0]; // @[RegisterRouter.scala:87:24] wire [9:0] _out_womask_T_498 = out_backMask_1[9:0]; // @[RegisterRouter.scala:87:24] wire [9:0] _out_romask_T_681 = out_backMask_1[9:0]; // @[RegisterRouter.scala:87:24] wire [9:0] _out_womask_T_681 = out_backMask_1[9:0]; // @[RegisterRouter.scala:87:24] wire out_romask_498 = |_out_romask_T_498; // @[RegisterRouter.scala:87:24] wire out_womask_498 = &_out_womask_T_498; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_498 = out_rivalid_1_352 & out_rimask_498; // @[RegisterRouter.scala:87:24] wire out_f_roready_498 = out_roready_1_352 & out_romask_498; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_498 = out_wivalid_1_352 & out_wimask_498; // @[RegisterRouter.scala:87:24] wire _out_T_5127 = out_f_wivalid_498; // @[RegisterRouter.scala:87:24] assign out_f_woready_498 = out_woready_1_352 & out_womask_498; // @[RegisterRouter.scala:87:24] assign hartResumingWrEn = out_f_woready_498; // @[RegisterRouter.scala:87:24] wire _out_T_5128 = out_f_woready_498; // @[RegisterRouter.scala:87:24] assign _out_T_5126 = out_front_1_bits_data[9:0]; // @[RegisterRouter.scala:87:24] assign _out_T_6805 = out_front_1_bits_data[9:0]; // @[RegisterRouter.scala:87:24] assign hartResumingId = _out_T_5126; // @[RegisterRouter.scala:87:24] wire _out_T_5129 = ~out_rimask_498; // @[RegisterRouter.scala:87:24] wire _out_T_5130 = ~out_wimask_498; // @[RegisterRouter.scala:87:24] wire _out_T_5131 = ~out_romask_498; // @[RegisterRouter.scala:87:24] wire _out_T_5132 = ~out_womask_498; // @[RegisterRouter.scala:87:24] wire [9:0] _out_rimask_T_499 = out_frontMask_1[41:32]; // @[RegisterRouter.scala:87:24] wire [9:0] _out_wimask_T_499 = out_frontMask_1[41:32]; // @[RegisterRouter.scala:87:24] wire [9:0] _out_rimask_T_682 = out_frontMask_1[41:32]; // @[RegisterRouter.scala:87:24] wire [9:0] _out_wimask_T_682 = out_frontMask_1[41:32]; // @[RegisterRouter.scala:87:24] wire out_rimask_499 = |_out_rimask_T_499; // @[RegisterRouter.scala:87:24] wire out_wimask_499 = &_out_wimask_T_499; // @[RegisterRouter.scala:87:24] wire [9:0] _out_romask_T_499 = out_backMask_1[41:32]; // @[RegisterRouter.scala:87:24] wire [9:0] _out_womask_T_499 = out_backMask_1[41:32]; // @[RegisterRouter.scala:87:24] wire [9:0] _out_romask_T_682 = out_backMask_1[41:32]; // @[RegisterRouter.scala:87:24] wire [9:0] _out_womask_T_682 = out_backMask_1[41:32]; // @[RegisterRouter.scala:87:24] wire out_romask_499 = |_out_romask_T_499; // @[RegisterRouter.scala:87:24] wire out_womask_499 = &_out_womask_T_499; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_499 = out_rivalid_1_353 & out_rimask_499; // @[RegisterRouter.scala:87:24] wire out_f_roready_499 = out_roready_1_353 & out_romask_499; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_499 = out_wivalid_1_353 & out_wimask_499; // @[RegisterRouter.scala:87:24] wire _out_T_5136 = out_f_wivalid_499; // @[RegisterRouter.scala:87:24] assign out_f_woready_499 = out_woready_1_353 & out_womask_499; // @[RegisterRouter.scala:87:24] assign hartExceptionWrEn = out_f_woready_499; // @[RegisterRouter.scala:87:24] wire _out_T_5137 = out_f_woready_499; // @[RegisterRouter.scala:87:24] assign _out_T_5135 = out_front_1_bits_data[41:32]; // @[RegisterRouter.scala:87:24] assign _out_T_6814 = out_front_1_bits_data[41:32]; // @[RegisterRouter.scala:87:24] assign hartExceptionId = _out_T_5135; // @[RegisterRouter.scala:87:24] wire _out_T_5138 = ~out_rimask_499; // @[RegisterRouter.scala:87:24] wire _out_T_5139 = ~out_wimask_499; // @[RegisterRouter.scala:87:24] wire _out_T_5140 = ~out_romask_499; // @[RegisterRouter.scala:87:24] wire _out_T_5141 = ~out_womask_499; // @[RegisterRouter.scala:87:24] wire out_rimask_500 = |_out_rimask_T_500; // @[RegisterRouter.scala:87:24] wire out_wimask_500 = &_out_wimask_T_500; // @[RegisterRouter.scala:87:24] wire out_romask_500 = |_out_romask_T_500; // @[RegisterRouter.scala:87:24] wire out_womask_500 = &_out_womask_T_500; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_500 = out_rivalid_1_354 & out_rimask_500; // @[RegisterRouter.scala:87:24] wire _out_T_5145 = out_f_rivalid_500; // @[RegisterRouter.scala:87:24] wire out_f_roready_500 = out_roready_1_354 & out_romask_500; // @[RegisterRouter.scala:87:24] wire _out_T_5146 = out_f_roready_500; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_500 = out_wivalid_1_354 & out_wimask_500; // @[RegisterRouter.scala:87:24] wire out_f_woready_500 = out_woready_1_354 & out_womask_500; // @[RegisterRouter.scala:87:24] wire _out_T_5147 = ~out_rimask_500; // @[RegisterRouter.scala:87:24] wire _out_T_5148 = ~out_wimask_500; // @[RegisterRouter.scala:87:24] wire _out_T_5149 = ~out_romask_500; // @[RegisterRouter.scala:87:24] wire _out_T_5150 = ~out_womask_500; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5152 = _out_T_5151; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_421 = _out_T_5152; // @[RegisterRouter.scala:87:24] wire out_rimask_501 = |_out_rimask_T_501; // @[RegisterRouter.scala:87:24] wire out_wimask_501 = &_out_wimask_T_501; // @[RegisterRouter.scala:87:24] wire out_romask_501 = |_out_romask_T_501; // @[RegisterRouter.scala:87:24] wire out_womask_501 = &_out_womask_T_501; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_501 = out_rivalid_1_355 & out_rimask_501; // @[RegisterRouter.scala:87:24] wire _out_T_5154 = out_f_rivalid_501; // @[RegisterRouter.scala:87:24] wire out_f_roready_501 = out_roready_1_355 & out_romask_501; // @[RegisterRouter.scala:87:24] wire _out_T_5155 = out_f_roready_501; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_501 = out_wivalid_1_355 & out_wimask_501; // @[RegisterRouter.scala:87:24] wire out_f_woready_501 = out_woready_1_355 & out_womask_501; // @[RegisterRouter.scala:87:24] wire _out_T_5156 = ~out_rimask_501; // @[RegisterRouter.scala:87:24] wire _out_T_5157 = ~out_wimask_501; // @[RegisterRouter.scala:87:24] wire _out_T_5158 = ~out_romask_501; // @[RegisterRouter.scala:87:24] wire _out_T_5159 = ~out_womask_501; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_421 = {hi_810, flags_0_go, _out_prepend_T_421}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5160 = out_prepend_421; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5161 = _out_T_5160; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_422 = _out_T_5161; // @[RegisterRouter.scala:87:24] wire out_rimask_502 = |_out_rimask_T_502; // @[RegisterRouter.scala:87:24] wire out_wimask_502 = &_out_wimask_T_502; // @[RegisterRouter.scala:87:24] wire out_romask_502 = |_out_romask_T_502; // @[RegisterRouter.scala:87:24] wire out_womask_502 = &_out_womask_T_502; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_502 = out_rivalid_1_356 & out_rimask_502; // @[RegisterRouter.scala:87:24] wire _out_T_5163 = out_f_rivalid_502; // @[RegisterRouter.scala:87:24] wire out_f_roready_502 = out_roready_1_356 & out_romask_502; // @[RegisterRouter.scala:87:24] wire _out_T_5164 = out_f_roready_502; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_502 = out_wivalid_1_356 & out_wimask_502; // @[RegisterRouter.scala:87:24] wire out_f_woready_502 = out_woready_1_356 & out_womask_502; // @[RegisterRouter.scala:87:24] wire _out_T_5165 = ~out_rimask_502; // @[RegisterRouter.scala:87:24] wire _out_T_5166 = ~out_wimask_502; // @[RegisterRouter.scala:87:24] wire _out_T_5167 = ~out_romask_502; // @[RegisterRouter.scala:87:24] wire _out_T_5168 = ~out_womask_502; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_422 = {hi_811, flags_0_go, _out_prepend_T_422}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5169 = out_prepend_422; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5170 = _out_T_5169; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_423 = _out_T_5170; // @[RegisterRouter.scala:87:24] wire out_rimask_503 = |_out_rimask_T_503; // @[RegisterRouter.scala:87:24] wire out_wimask_503 = &_out_wimask_T_503; // @[RegisterRouter.scala:87:24] wire out_romask_503 = |_out_romask_T_503; // @[RegisterRouter.scala:87:24] wire out_womask_503 = &_out_womask_T_503; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_503 = out_rivalid_1_357 & out_rimask_503; // @[RegisterRouter.scala:87:24] wire _out_T_5172 = out_f_rivalid_503; // @[RegisterRouter.scala:87:24] wire out_f_roready_503 = out_roready_1_357 & out_romask_503; // @[RegisterRouter.scala:87:24] wire _out_T_5173 = out_f_roready_503; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_503 = out_wivalid_1_357 & out_wimask_503; // @[RegisterRouter.scala:87:24] wire out_f_woready_503 = out_woready_1_357 & out_womask_503; // @[RegisterRouter.scala:87:24] wire _out_T_5174 = ~out_rimask_503; // @[RegisterRouter.scala:87:24] wire _out_T_5175 = ~out_wimask_503; // @[RegisterRouter.scala:87:24] wire _out_T_5176 = ~out_romask_503; // @[RegisterRouter.scala:87:24] wire _out_T_5177 = ~out_womask_503; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_423 = {hi_812, flags_0_go, _out_prepend_T_423}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5178 = out_prepend_423; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5179 = _out_T_5178; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_424 = _out_T_5179; // @[RegisterRouter.scala:87:24] wire out_rimask_504 = |_out_rimask_T_504; // @[RegisterRouter.scala:87:24] wire out_wimask_504 = &_out_wimask_T_504; // @[RegisterRouter.scala:87:24] wire out_romask_504 = |_out_romask_T_504; // @[RegisterRouter.scala:87:24] wire out_womask_504 = &_out_womask_T_504; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_504 = out_rivalid_1_358 & out_rimask_504; // @[RegisterRouter.scala:87:24] wire _out_T_5181 = out_f_rivalid_504; // @[RegisterRouter.scala:87:24] wire out_f_roready_504 = out_roready_1_358 & out_romask_504; // @[RegisterRouter.scala:87:24] wire _out_T_5182 = out_f_roready_504; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_504 = out_wivalid_1_358 & out_wimask_504; // @[RegisterRouter.scala:87:24] wire out_f_woready_504 = out_woready_1_358 & out_womask_504; // @[RegisterRouter.scala:87:24] wire _out_T_5183 = ~out_rimask_504; // @[RegisterRouter.scala:87:24] wire _out_T_5184 = ~out_wimask_504; // @[RegisterRouter.scala:87:24] wire _out_T_5185 = ~out_romask_504; // @[RegisterRouter.scala:87:24] wire _out_T_5186 = ~out_womask_504; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_424 = {hi_813, flags_0_go, _out_prepend_T_424}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5187 = out_prepend_424; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5188 = _out_T_5187; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_425 = _out_T_5188; // @[RegisterRouter.scala:87:24] wire out_rimask_505 = |_out_rimask_T_505; // @[RegisterRouter.scala:87:24] wire out_wimask_505 = &_out_wimask_T_505; // @[RegisterRouter.scala:87:24] wire out_romask_505 = |_out_romask_T_505; // @[RegisterRouter.scala:87:24] wire out_womask_505 = &_out_womask_T_505; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_505 = out_rivalid_1_359 & out_rimask_505; // @[RegisterRouter.scala:87:24] wire _out_T_5190 = out_f_rivalid_505; // @[RegisterRouter.scala:87:24] wire out_f_roready_505 = out_roready_1_359 & out_romask_505; // @[RegisterRouter.scala:87:24] wire _out_T_5191 = out_f_roready_505; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_505 = out_wivalid_1_359 & out_wimask_505; // @[RegisterRouter.scala:87:24] wire out_f_woready_505 = out_woready_1_359 & out_womask_505; // @[RegisterRouter.scala:87:24] wire _out_T_5192 = ~out_rimask_505; // @[RegisterRouter.scala:87:24] wire _out_T_5193 = ~out_wimask_505; // @[RegisterRouter.scala:87:24] wire _out_T_5194 = ~out_romask_505; // @[RegisterRouter.scala:87:24] wire _out_T_5195 = ~out_womask_505; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_425 = {hi_814, flags_0_go, _out_prepend_T_425}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5196 = out_prepend_425; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5197 = _out_T_5196; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_426 = _out_T_5197; // @[RegisterRouter.scala:87:24] wire out_rimask_506 = |_out_rimask_T_506; // @[RegisterRouter.scala:87:24] wire out_wimask_506 = &_out_wimask_T_506; // @[RegisterRouter.scala:87:24] wire out_romask_506 = |_out_romask_T_506; // @[RegisterRouter.scala:87:24] wire out_womask_506 = &_out_womask_T_506; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_506 = out_rivalid_1_360 & out_rimask_506; // @[RegisterRouter.scala:87:24] wire _out_T_5199 = out_f_rivalid_506; // @[RegisterRouter.scala:87:24] wire out_f_roready_506 = out_roready_1_360 & out_romask_506; // @[RegisterRouter.scala:87:24] wire _out_T_5200 = out_f_roready_506; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_506 = out_wivalid_1_360 & out_wimask_506; // @[RegisterRouter.scala:87:24] wire out_f_woready_506 = out_woready_1_360 & out_womask_506; // @[RegisterRouter.scala:87:24] wire _out_T_5201 = ~out_rimask_506; // @[RegisterRouter.scala:87:24] wire _out_T_5202 = ~out_wimask_506; // @[RegisterRouter.scala:87:24] wire _out_T_5203 = ~out_romask_506; // @[RegisterRouter.scala:87:24] wire _out_T_5204 = ~out_womask_506; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_426 = {hi_815, flags_0_go, _out_prepend_T_426}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5205 = out_prepend_426; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5206 = _out_T_5205; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_427 = _out_T_5206; // @[RegisterRouter.scala:87:24] wire out_rimask_507 = |_out_rimask_T_507; // @[RegisterRouter.scala:87:24] wire out_wimask_507 = &_out_wimask_T_507; // @[RegisterRouter.scala:87:24] wire out_romask_507 = |_out_romask_T_507; // @[RegisterRouter.scala:87:24] wire out_womask_507 = &_out_womask_T_507; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_507 = out_rivalid_1_361 & out_rimask_507; // @[RegisterRouter.scala:87:24] wire _out_T_5208 = out_f_rivalid_507; // @[RegisterRouter.scala:87:24] wire out_f_roready_507 = out_roready_1_361 & out_romask_507; // @[RegisterRouter.scala:87:24] wire _out_T_5209 = out_f_roready_507; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_507 = out_wivalid_1_361 & out_wimask_507; // @[RegisterRouter.scala:87:24] wire out_f_woready_507 = out_woready_1_361 & out_womask_507; // @[RegisterRouter.scala:87:24] wire _out_T_5210 = ~out_rimask_507; // @[RegisterRouter.scala:87:24] wire _out_T_5211 = ~out_wimask_507; // @[RegisterRouter.scala:87:24] wire _out_T_5212 = ~out_romask_507; // @[RegisterRouter.scala:87:24] wire _out_T_5213 = ~out_womask_507; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_427 = {hi_816, flags_0_go, _out_prepend_T_427}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5214 = out_prepend_427; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5215 = _out_T_5214; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_229 = _out_T_5215; // @[MuxLiteral.scala:49:48] wire out_rimask_508 = |_out_rimask_T_508; // @[RegisterRouter.scala:87:24] wire out_wimask_508 = &_out_wimask_T_508; // @[RegisterRouter.scala:87:24] wire out_romask_508 = |_out_romask_T_508; // @[RegisterRouter.scala:87:24] wire out_womask_508 = &_out_womask_T_508; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_508 = out_rivalid_1_362 & out_rimask_508; // @[RegisterRouter.scala:87:24] wire _out_T_5217 = out_f_rivalid_508; // @[RegisterRouter.scala:87:24] wire out_f_roready_508 = out_roready_1_362 & out_romask_508; // @[RegisterRouter.scala:87:24] wire _out_T_5218 = out_f_roready_508; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_508 = out_wivalid_1_362 & out_wimask_508; // @[RegisterRouter.scala:87:24] wire out_f_woready_508 = out_woready_1_362 & out_womask_508; // @[RegisterRouter.scala:87:24] wire _out_T_5219 = ~out_rimask_508; // @[RegisterRouter.scala:87:24] wire _out_T_5220 = ~out_wimask_508; // @[RegisterRouter.scala:87:24] wire _out_T_5221 = ~out_romask_508; // @[RegisterRouter.scala:87:24] wire _out_T_5222 = ~out_womask_508; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5224 = _out_T_5223; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_428 = _out_T_5224; // @[RegisterRouter.scala:87:24] wire out_rimask_509 = |_out_rimask_T_509; // @[RegisterRouter.scala:87:24] wire out_wimask_509 = &_out_wimask_T_509; // @[RegisterRouter.scala:87:24] wire out_romask_509 = |_out_romask_T_509; // @[RegisterRouter.scala:87:24] wire out_womask_509 = &_out_womask_T_509; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_509 = out_rivalid_1_363 & out_rimask_509; // @[RegisterRouter.scala:87:24] wire _out_T_5226 = out_f_rivalid_509; // @[RegisterRouter.scala:87:24] wire out_f_roready_509 = out_roready_1_363 & out_romask_509; // @[RegisterRouter.scala:87:24] wire _out_T_5227 = out_f_roready_509; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_509 = out_wivalid_1_363 & out_wimask_509; // @[RegisterRouter.scala:87:24] wire out_f_woready_509 = out_woready_1_363 & out_womask_509; // @[RegisterRouter.scala:87:24] wire _out_T_5228 = ~out_rimask_509; // @[RegisterRouter.scala:87:24] wire _out_T_5229 = ~out_wimask_509; // @[RegisterRouter.scala:87:24] wire _out_T_5230 = ~out_romask_509; // @[RegisterRouter.scala:87:24] wire _out_T_5231 = ~out_womask_509; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_428 = {hi_994, flags_0_go, _out_prepend_T_428}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5232 = out_prepend_428; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5233 = _out_T_5232; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_429 = _out_T_5233; // @[RegisterRouter.scala:87:24] wire out_rimask_510 = |_out_rimask_T_510; // @[RegisterRouter.scala:87:24] wire out_wimask_510 = &_out_wimask_T_510; // @[RegisterRouter.scala:87:24] wire out_romask_510 = |_out_romask_T_510; // @[RegisterRouter.scala:87:24] wire out_womask_510 = &_out_womask_T_510; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_510 = out_rivalid_1_364 & out_rimask_510; // @[RegisterRouter.scala:87:24] wire _out_T_5235 = out_f_rivalid_510; // @[RegisterRouter.scala:87:24] wire out_f_roready_510 = out_roready_1_364 & out_romask_510; // @[RegisterRouter.scala:87:24] wire _out_T_5236 = out_f_roready_510; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_510 = out_wivalid_1_364 & out_wimask_510; // @[RegisterRouter.scala:87:24] wire out_f_woready_510 = out_woready_1_364 & out_womask_510; // @[RegisterRouter.scala:87:24] wire _out_T_5237 = ~out_rimask_510; // @[RegisterRouter.scala:87:24] wire _out_T_5238 = ~out_wimask_510; // @[RegisterRouter.scala:87:24] wire _out_T_5239 = ~out_romask_510; // @[RegisterRouter.scala:87:24] wire _out_T_5240 = ~out_womask_510; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_429 = {hi_995, flags_0_go, _out_prepend_T_429}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5241 = out_prepend_429; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5242 = _out_T_5241; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_430 = _out_T_5242; // @[RegisterRouter.scala:87:24] wire out_rimask_511 = |_out_rimask_T_511; // @[RegisterRouter.scala:87:24] wire out_wimask_511 = &_out_wimask_T_511; // @[RegisterRouter.scala:87:24] wire out_romask_511 = |_out_romask_T_511; // @[RegisterRouter.scala:87:24] wire out_womask_511 = &_out_womask_T_511; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_511 = out_rivalid_1_365 & out_rimask_511; // @[RegisterRouter.scala:87:24] wire _out_T_5244 = out_f_rivalid_511; // @[RegisterRouter.scala:87:24] wire out_f_roready_511 = out_roready_1_365 & out_romask_511; // @[RegisterRouter.scala:87:24] wire _out_T_5245 = out_f_roready_511; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_511 = out_wivalid_1_365 & out_wimask_511; // @[RegisterRouter.scala:87:24] wire out_f_woready_511 = out_woready_1_365 & out_womask_511; // @[RegisterRouter.scala:87:24] wire _out_T_5246 = ~out_rimask_511; // @[RegisterRouter.scala:87:24] wire _out_T_5247 = ~out_wimask_511; // @[RegisterRouter.scala:87:24] wire _out_T_5248 = ~out_romask_511; // @[RegisterRouter.scala:87:24] wire _out_T_5249 = ~out_womask_511; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_430 = {hi_996, flags_0_go, _out_prepend_T_430}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5250 = out_prepend_430; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5251 = _out_T_5250; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_431 = _out_T_5251; // @[RegisterRouter.scala:87:24] wire out_rimask_512 = |_out_rimask_T_512; // @[RegisterRouter.scala:87:24] wire out_wimask_512 = &_out_wimask_T_512; // @[RegisterRouter.scala:87:24] wire out_romask_512 = |_out_romask_T_512; // @[RegisterRouter.scala:87:24] wire out_womask_512 = &_out_womask_T_512; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_512 = out_rivalid_1_366 & out_rimask_512; // @[RegisterRouter.scala:87:24] wire _out_T_5253 = out_f_rivalid_512; // @[RegisterRouter.scala:87:24] wire out_f_roready_512 = out_roready_1_366 & out_romask_512; // @[RegisterRouter.scala:87:24] wire _out_T_5254 = out_f_roready_512; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_512 = out_wivalid_1_366 & out_wimask_512; // @[RegisterRouter.scala:87:24] wire out_f_woready_512 = out_woready_1_366 & out_womask_512; // @[RegisterRouter.scala:87:24] wire _out_T_5255 = ~out_rimask_512; // @[RegisterRouter.scala:87:24] wire _out_T_5256 = ~out_wimask_512; // @[RegisterRouter.scala:87:24] wire _out_T_5257 = ~out_romask_512; // @[RegisterRouter.scala:87:24] wire _out_T_5258 = ~out_womask_512; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_431 = {hi_997, flags_0_go, _out_prepend_T_431}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5259 = out_prepend_431; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5260 = _out_T_5259; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_432 = _out_T_5260; // @[RegisterRouter.scala:87:24] wire out_rimask_513 = |_out_rimask_T_513; // @[RegisterRouter.scala:87:24] wire out_wimask_513 = &_out_wimask_T_513; // @[RegisterRouter.scala:87:24] wire out_romask_513 = |_out_romask_T_513; // @[RegisterRouter.scala:87:24] wire out_womask_513 = &_out_womask_T_513; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_513 = out_rivalid_1_367 & out_rimask_513; // @[RegisterRouter.scala:87:24] wire _out_T_5262 = out_f_rivalid_513; // @[RegisterRouter.scala:87:24] wire out_f_roready_513 = out_roready_1_367 & out_romask_513; // @[RegisterRouter.scala:87:24] wire _out_T_5263 = out_f_roready_513; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_513 = out_wivalid_1_367 & out_wimask_513; // @[RegisterRouter.scala:87:24] wire out_f_woready_513 = out_woready_1_367 & out_womask_513; // @[RegisterRouter.scala:87:24] wire _out_T_5264 = ~out_rimask_513; // @[RegisterRouter.scala:87:24] wire _out_T_5265 = ~out_wimask_513; // @[RegisterRouter.scala:87:24] wire _out_T_5266 = ~out_romask_513; // @[RegisterRouter.scala:87:24] wire _out_T_5267 = ~out_womask_513; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_432 = {hi_998, flags_0_go, _out_prepend_T_432}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5268 = out_prepend_432; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5269 = _out_T_5268; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_433 = _out_T_5269; // @[RegisterRouter.scala:87:24] wire out_rimask_514 = |_out_rimask_T_514; // @[RegisterRouter.scala:87:24] wire out_wimask_514 = &_out_wimask_T_514; // @[RegisterRouter.scala:87:24] wire out_romask_514 = |_out_romask_T_514; // @[RegisterRouter.scala:87:24] wire out_womask_514 = &_out_womask_T_514; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_514 = out_rivalid_1_368 & out_rimask_514; // @[RegisterRouter.scala:87:24] wire _out_T_5271 = out_f_rivalid_514; // @[RegisterRouter.scala:87:24] wire out_f_roready_514 = out_roready_1_368 & out_romask_514; // @[RegisterRouter.scala:87:24] wire _out_T_5272 = out_f_roready_514; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_514 = out_wivalid_1_368 & out_wimask_514; // @[RegisterRouter.scala:87:24] wire out_f_woready_514 = out_woready_1_368 & out_womask_514; // @[RegisterRouter.scala:87:24] wire _out_T_5273 = ~out_rimask_514; // @[RegisterRouter.scala:87:24] wire _out_T_5274 = ~out_wimask_514; // @[RegisterRouter.scala:87:24] wire _out_T_5275 = ~out_romask_514; // @[RegisterRouter.scala:87:24] wire _out_T_5276 = ~out_womask_514; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_433 = {hi_999, flags_0_go, _out_prepend_T_433}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5277 = out_prepend_433; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5278 = _out_T_5277; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_434 = _out_T_5278; // @[RegisterRouter.scala:87:24] wire out_rimask_515 = |_out_rimask_T_515; // @[RegisterRouter.scala:87:24] wire out_wimask_515 = &_out_wimask_T_515; // @[RegisterRouter.scala:87:24] wire out_romask_515 = |_out_romask_T_515; // @[RegisterRouter.scala:87:24] wire out_womask_515 = &_out_womask_T_515; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_515 = out_rivalid_1_369 & out_rimask_515; // @[RegisterRouter.scala:87:24] wire _out_T_5280 = out_f_rivalid_515; // @[RegisterRouter.scala:87:24] wire out_f_roready_515 = out_roready_1_369 & out_romask_515; // @[RegisterRouter.scala:87:24] wire _out_T_5281 = out_f_roready_515; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_515 = out_wivalid_1_369 & out_wimask_515; // @[RegisterRouter.scala:87:24] wire out_f_woready_515 = out_woready_1_369 & out_womask_515; // @[RegisterRouter.scala:87:24] wire _out_T_5282 = ~out_rimask_515; // @[RegisterRouter.scala:87:24] wire _out_T_5283 = ~out_wimask_515; // @[RegisterRouter.scala:87:24] wire _out_T_5284 = ~out_romask_515; // @[RegisterRouter.scala:87:24] wire _out_T_5285 = ~out_womask_515; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_434 = {hi_1000, flags_0_go, _out_prepend_T_434}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5286 = out_prepend_434; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5287 = _out_T_5286; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_252 = _out_T_5287; // @[MuxLiteral.scala:49:48] wire out_rimask_516 = |_out_rimask_T_516; // @[RegisterRouter.scala:87:24] wire out_wimask_516 = &_out_wimask_T_516; // @[RegisterRouter.scala:87:24] wire out_romask_516 = |_out_romask_T_516; // @[RegisterRouter.scala:87:24] wire out_womask_516 = &_out_womask_T_516; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_516 = out_rivalid_1_370 & out_rimask_516; // @[RegisterRouter.scala:87:24] wire _out_T_5289 = out_f_rivalid_516; // @[RegisterRouter.scala:87:24] wire out_f_roready_516 = out_roready_1_370 & out_romask_516; // @[RegisterRouter.scala:87:24] wire _out_T_5290 = out_f_roready_516; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_516 = out_wivalid_1_370 & out_wimask_516; // @[RegisterRouter.scala:87:24] wire out_f_woready_516 = out_woready_1_370 & out_womask_516; // @[RegisterRouter.scala:87:24] wire _out_T_5291 = ~out_rimask_516; // @[RegisterRouter.scala:87:24] wire _out_T_5292 = ~out_wimask_516; // @[RegisterRouter.scala:87:24] wire _out_T_5293 = ~out_romask_516; // @[RegisterRouter.scala:87:24] wire _out_T_5294 = ~out_womask_516; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5296 = _out_T_5295; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_435 = _out_T_5296; // @[RegisterRouter.scala:87:24] wire out_rimask_517 = |_out_rimask_T_517; // @[RegisterRouter.scala:87:24] wire out_wimask_517 = &_out_wimask_T_517; // @[RegisterRouter.scala:87:24] wire out_romask_517 = |_out_romask_T_517; // @[RegisterRouter.scala:87:24] wire out_womask_517 = &_out_womask_T_517; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_517 = out_rivalid_1_371 & out_rimask_517; // @[RegisterRouter.scala:87:24] wire _out_T_5298 = out_f_rivalid_517; // @[RegisterRouter.scala:87:24] wire out_f_roready_517 = out_roready_1_371 & out_romask_517; // @[RegisterRouter.scala:87:24] wire _out_T_5299 = out_f_roready_517; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_517 = out_wivalid_1_371 & out_wimask_517; // @[RegisterRouter.scala:87:24] wire out_f_woready_517 = out_woready_1_371 & out_womask_517; // @[RegisterRouter.scala:87:24] wire _out_T_5300 = ~out_rimask_517; // @[RegisterRouter.scala:87:24] wire _out_T_5301 = ~out_wimask_517; // @[RegisterRouter.scala:87:24] wire _out_T_5302 = ~out_romask_517; // @[RegisterRouter.scala:87:24] wire _out_T_5303 = ~out_womask_517; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_435 = {hi_554, flags_0_go, _out_prepend_T_435}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5304 = out_prepend_435; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5305 = _out_T_5304; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_436 = _out_T_5305; // @[RegisterRouter.scala:87:24] wire out_rimask_518 = |_out_rimask_T_518; // @[RegisterRouter.scala:87:24] wire out_wimask_518 = &_out_wimask_T_518; // @[RegisterRouter.scala:87:24] wire out_romask_518 = |_out_romask_T_518; // @[RegisterRouter.scala:87:24] wire out_womask_518 = &_out_womask_T_518; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_518 = out_rivalid_1_372 & out_rimask_518; // @[RegisterRouter.scala:87:24] wire _out_T_5307 = out_f_rivalid_518; // @[RegisterRouter.scala:87:24] wire out_f_roready_518 = out_roready_1_372 & out_romask_518; // @[RegisterRouter.scala:87:24] wire _out_T_5308 = out_f_roready_518; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_518 = out_wivalid_1_372 & out_wimask_518; // @[RegisterRouter.scala:87:24] wire out_f_woready_518 = out_woready_1_372 & out_womask_518; // @[RegisterRouter.scala:87:24] wire _out_T_5309 = ~out_rimask_518; // @[RegisterRouter.scala:87:24] wire _out_T_5310 = ~out_wimask_518; // @[RegisterRouter.scala:87:24] wire _out_T_5311 = ~out_romask_518; // @[RegisterRouter.scala:87:24] wire _out_T_5312 = ~out_womask_518; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_436 = {hi_555, flags_0_go, _out_prepend_T_436}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5313 = out_prepend_436; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5314 = _out_T_5313; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_437 = _out_T_5314; // @[RegisterRouter.scala:87:24] wire out_rimask_519 = |_out_rimask_T_519; // @[RegisterRouter.scala:87:24] wire out_wimask_519 = &_out_wimask_T_519; // @[RegisterRouter.scala:87:24] wire out_romask_519 = |_out_romask_T_519; // @[RegisterRouter.scala:87:24] wire out_womask_519 = &_out_womask_T_519; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_519 = out_rivalid_1_373 & out_rimask_519; // @[RegisterRouter.scala:87:24] wire _out_T_5316 = out_f_rivalid_519; // @[RegisterRouter.scala:87:24] wire out_f_roready_519 = out_roready_1_373 & out_romask_519; // @[RegisterRouter.scala:87:24] wire _out_T_5317 = out_f_roready_519; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_519 = out_wivalid_1_373 & out_wimask_519; // @[RegisterRouter.scala:87:24] wire out_f_woready_519 = out_woready_1_373 & out_womask_519; // @[RegisterRouter.scala:87:24] wire _out_T_5318 = ~out_rimask_519; // @[RegisterRouter.scala:87:24] wire _out_T_5319 = ~out_wimask_519; // @[RegisterRouter.scala:87:24] wire _out_T_5320 = ~out_romask_519; // @[RegisterRouter.scala:87:24] wire _out_T_5321 = ~out_womask_519; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_437 = {hi_556, flags_0_go, _out_prepend_T_437}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5322 = out_prepend_437; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5323 = _out_T_5322; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_438 = _out_T_5323; // @[RegisterRouter.scala:87:24] wire out_rimask_520 = |_out_rimask_T_520; // @[RegisterRouter.scala:87:24] wire out_wimask_520 = &_out_wimask_T_520; // @[RegisterRouter.scala:87:24] wire out_romask_520 = |_out_romask_T_520; // @[RegisterRouter.scala:87:24] wire out_womask_520 = &_out_womask_T_520; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_520 = out_rivalid_1_374 & out_rimask_520; // @[RegisterRouter.scala:87:24] wire _out_T_5325 = out_f_rivalid_520; // @[RegisterRouter.scala:87:24] wire out_f_roready_520 = out_roready_1_374 & out_romask_520; // @[RegisterRouter.scala:87:24] wire _out_T_5326 = out_f_roready_520; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_520 = out_wivalid_1_374 & out_wimask_520; // @[RegisterRouter.scala:87:24] wire out_f_woready_520 = out_woready_1_374 & out_womask_520; // @[RegisterRouter.scala:87:24] wire _out_T_5327 = ~out_rimask_520; // @[RegisterRouter.scala:87:24] wire _out_T_5328 = ~out_wimask_520; // @[RegisterRouter.scala:87:24] wire _out_T_5329 = ~out_romask_520; // @[RegisterRouter.scala:87:24] wire _out_T_5330 = ~out_womask_520; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_438 = {hi_557, flags_0_go, _out_prepend_T_438}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5331 = out_prepend_438; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5332 = _out_T_5331; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_439 = _out_T_5332; // @[RegisterRouter.scala:87:24] wire out_rimask_521 = |_out_rimask_T_521; // @[RegisterRouter.scala:87:24] wire out_wimask_521 = &_out_wimask_T_521; // @[RegisterRouter.scala:87:24] wire out_romask_521 = |_out_romask_T_521; // @[RegisterRouter.scala:87:24] wire out_womask_521 = &_out_womask_T_521; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_521 = out_rivalid_1_375 & out_rimask_521; // @[RegisterRouter.scala:87:24] wire _out_T_5334 = out_f_rivalid_521; // @[RegisterRouter.scala:87:24] wire out_f_roready_521 = out_roready_1_375 & out_romask_521; // @[RegisterRouter.scala:87:24] wire _out_T_5335 = out_f_roready_521; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_521 = out_wivalid_1_375 & out_wimask_521; // @[RegisterRouter.scala:87:24] wire out_f_woready_521 = out_woready_1_375 & out_womask_521; // @[RegisterRouter.scala:87:24] wire _out_T_5336 = ~out_rimask_521; // @[RegisterRouter.scala:87:24] wire _out_T_5337 = ~out_wimask_521; // @[RegisterRouter.scala:87:24] wire _out_T_5338 = ~out_romask_521; // @[RegisterRouter.scala:87:24] wire _out_T_5339 = ~out_womask_521; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_439 = {hi_558, flags_0_go, _out_prepend_T_439}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5340 = out_prepend_439; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5341 = _out_T_5340; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_440 = _out_T_5341; // @[RegisterRouter.scala:87:24] wire out_rimask_522 = |_out_rimask_T_522; // @[RegisterRouter.scala:87:24] wire out_wimask_522 = &_out_wimask_T_522; // @[RegisterRouter.scala:87:24] wire out_romask_522 = |_out_romask_T_522; // @[RegisterRouter.scala:87:24] wire out_womask_522 = &_out_womask_T_522; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_522 = out_rivalid_1_376 & out_rimask_522; // @[RegisterRouter.scala:87:24] wire _out_T_5343 = out_f_rivalid_522; // @[RegisterRouter.scala:87:24] wire out_f_roready_522 = out_roready_1_376 & out_romask_522; // @[RegisterRouter.scala:87:24] wire _out_T_5344 = out_f_roready_522; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_522 = out_wivalid_1_376 & out_wimask_522; // @[RegisterRouter.scala:87:24] wire out_f_woready_522 = out_woready_1_376 & out_womask_522; // @[RegisterRouter.scala:87:24] wire _out_T_5345 = ~out_rimask_522; // @[RegisterRouter.scala:87:24] wire _out_T_5346 = ~out_wimask_522; // @[RegisterRouter.scala:87:24] wire _out_T_5347 = ~out_romask_522; // @[RegisterRouter.scala:87:24] wire _out_T_5348 = ~out_womask_522; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_440 = {hi_559, flags_0_go, _out_prepend_T_440}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5349 = out_prepend_440; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5350 = _out_T_5349; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_441 = _out_T_5350; // @[RegisterRouter.scala:87:24] wire out_rimask_523 = |_out_rimask_T_523; // @[RegisterRouter.scala:87:24] wire out_wimask_523 = &_out_wimask_T_523; // @[RegisterRouter.scala:87:24] wire out_romask_523 = |_out_romask_T_523; // @[RegisterRouter.scala:87:24] wire out_womask_523 = &_out_womask_T_523; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_523 = out_rivalid_1_377 & out_rimask_523; // @[RegisterRouter.scala:87:24] wire _out_T_5352 = out_f_rivalid_523; // @[RegisterRouter.scala:87:24] wire out_f_roready_523 = out_roready_1_377 & out_romask_523; // @[RegisterRouter.scala:87:24] wire _out_T_5353 = out_f_roready_523; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_523 = out_wivalid_1_377 & out_wimask_523; // @[RegisterRouter.scala:87:24] wire out_f_woready_523 = out_woready_1_377 & out_womask_523; // @[RegisterRouter.scala:87:24] wire _out_T_5354 = ~out_rimask_523; // @[RegisterRouter.scala:87:24] wire _out_T_5355 = ~out_wimask_523; // @[RegisterRouter.scala:87:24] wire _out_T_5356 = ~out_romask_523; // @[RegisterRouter.scala:87:24] wire _out_T_5357 = ~out_womask_523; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_441 = {hi_560, flags_0_go, _out_prepend_T_441}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5358 = out_prepend_441; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5359 = _out_T_5358; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_197 = _out_T_5359; // @[MuxLiteral.scala:49:48] wire out_rimask_524 = |_out_rimask_T_524; // @[RegisterRouter.scala:87:24] wire out_wimask_524 = &_out_wimask_T_524; // @[RegisterRouter.scala:87:24] wire out_romask_524 = |_out_romask_T_524; // @[RegisterRouter.scala:87:24] wire out_womask_524 = &_out_womask_T_524; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_524 = out_rivalid_1_378 & out_rimask_524; // @[RegisterRouter.scala:87:24] wire _out_T_5361 = out_f_rivalid_524; // @[RegisterRouter.scala:87:24] wire out_f_roready_524 = out_roready_1_378 & out_romask_524; // @[RegisterRouter.scala:87:24] wire _out_T_5362 = out_f_roready_524; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_524 = out_wivalid_1_378 & out_wimask_524; // @[RegisterRouter.scala:87:24] wire out_f_woready_524 = out_woready_1_378 & out_womask_524; // @[RegisterRouter.scala:87:24] wire _out_T_5363 = ~out_rimask_524; // @[RegisterRouter.scala:87:24] wire _out_T_5364 = ~out_wimask_524; // @[RegisterRouter.scala:87:24] wire _out_T_5365 = ~out_romask_524; // @[RegisterRouter.scala:87:24] wire _out_T_5366 = ~out_womask_524; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5368 = _out_T_5367; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_442 = _out_T_5368; // @[RegisterRouter.scala:87:24] wire out_rimask_525 = |_out_rimask_T_525; // @[RegisterRouter.scala:87:24] wire out_wimask_525 = &_out_wimask_T_525; // @[RegisterRouter.scala:87:24] wire out_romask_525 = |_out_romask_T_525; // @[RegisterRouter.scala:87:24] wire out_womask_525 = &_out_womask_T_525; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_525 = out_rivalid_1_379 & out_rimask_525; // @[RegisterRouter.scala:87:24] wire _out_T_5370 = out_f_rivalid_525; // @[RegisterRouter.scala:87:24] wire out_f_roready_525 = out_roready_1_379 & out_romask_525; // @[RegisterRouter.scala:87:24] wire _out_T_5371 = out_f_roready_525; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_525 = out_wivalid_1_379 & out_wimask_525; // @[RegisterRouter.scala:87:24] wire out_f_woready_525 = out_woready_1_379 & out_womask_525; // @[RegisterRouter.scala:87:24] wire _out_T_5372 = ~out_rimask_525; // @[RegisterRouter.scala:87:24] wire _out_T_5373 = ~out_wimask_525; // @[RegisterRouter.scala:87:24] wire _out_T_5374 = ~out_romask_525; // @[RegisterRouter.scala:87:24] wire _out_T_5375 = ~out_womask_525; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_442 = {hi_770, flags_0_go, _out_prepend_T_442}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5376 = out_prepend_442; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5377 = _out_T_5376; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_443 = _out_T_5377; // @[RegisterRouter.scala:87:24] wire out_rimask_526 = |_out_rimask_T_526; // @[RegisterRouter.scala:87:24] wire out_wimask_526 = &_out_wimask_T_526; // @[RegisterRouter.scala:87:24] wire out_romask_526 = |_out_romask_T_526; // @[RegisterRouter.scala:87:24] wire out_womask_526 = &_out_womask_T_526; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_526 = out_rivalid_1_380 & out_rimask_526; // @[RegisterRouter.scala:87:24] wire _out_T_5379 = out_f_rivalid_526; // @[RegisterRouter.scala:87:24] wire out_f_roready_526 = out_roready_1_380 & out_romask_526; // @[RegisterRouter.scala:87:24] wire _out_T_5380 = out_f_roready_526; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_526 = out_wivalid_1_380 & out_wimask_526; // @[RegisterRouter.scala:87:24] wire out_f_woready_526 = out_woready_1_380 & out_womask_526; // @[RegisterRouter.scala:87:24] wire _out_T_5381 = ~out_rimask_526; // @[RegisterRouter.scala:87:24] wire _out_T_5382 = ~out_wimask_526; // @[RegisterRouter.scala:87:24] wire _out_T_5383 = ~out_romask_526; // @[RegisterRouter.scala:87:24] wire _out_T_5384 = ~out_womask_526; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_443 = {hi_771, flags_0_go, _out_prepend_T_443}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5385 = out_prepend_443; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5386 = _out_T_5385; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_444 = _out_T_5386; // @[RegisterRouter.scala:87:24] wire out_rimask_527 = |_out_rimask_T_527; // @[RegisterRouter.scala:87:24] wire out_wimask_527 = &_out_wimask_T_527; // @[RegisterRouter.scala:87:24] wire out_romask_527 = |_out_romask_T_527; // @[RegisterRouter.scala:87:24] wire out_womask_527 = &_out_womask_T_527; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_527 = out_rivalid_1_381 & out_rimask_527; // @[RegisterRouter.scala:87:24] wire _out_T_5388 = out_f_rivalid_527; // @[RegisterRouter.scala:87:24] wire out_f_roready_527 = out_roready_1_381 & out_romask_527; // @[RegisterRouter.scala:87:24] wire _out_T_5389 = out_f_roready_527; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_527 = out_wivalid_1_381 & out_wimask_527; // @[RegisterRouter.scala:87:24] wire out_f_woready_527 = out_woready_1_381 & out_womask_527; // @[RegisterRouter.scala:87:24] wire _out_T_5390 = ~out_rimask_527; // @[RegisterRouter.scala:87:24] wire _out_T_5391 = ~out_wimask_527; // @[RegisterRouter.scala:87:24] wire _out_T_5392 = ~out_romask_527; // @[RegisterRouter.scala:87:24] wire _out_T_5393 = ~out_womask_527; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_444 = {hi_772, flags_0_go, _out_prepend_T_444}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5394 = out_prepend_444; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5395 = _out_T_5394; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_445 = _out_T_5395; // @[RegisterRouter.scala:87:24] wire out_rimask_528 = |_out_rimask_T_528; // @[RegisterRouter.scala:87:24] wire out_wimask_528 = &_out_wimask_T_528; // @[RegisterRouter.scala:87:24] wire out_romask_528 = |_out_romask_T_528; // @[RegisterRouter.scala:87:24] wire out_womask_528 = &_out_womask_T_528; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_528 = out_rivalid_1_382 & out_rimask_528; // @[RegisterRouter.scala:87:24] wire _out_T_5397 = out_f_rivalid_528; // @[RegisterRouter.scala:87:24] wire out_f_roready_528 = out_roready_1_382 & out_romask_528; // @[RegisterRouter.scala:87:24] wire _out_T_5398 = out_f_roready_528; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_528 = out_wivalid_1_382 & out_wimask_528; // @[RegisterRouter.scala:87:24] wire out_f_woready_528 = out_woready_1_382 & out_womask_528; // @[RegisterRouter.scala:87:24] wire _out_T_5399 = ~out_rimask_528; // @[RegisterRouter.scala:87:24] wire _out_T_5400 = ~out_wimask_528; // @[RegisterRouter.scala:87:24] wire _out_T_5401 = ~out_romask_528; // @[RegisterRouter.scala:87:24] wire _out_T_5402 = ~out_womask_528; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_445 = {hi_773, flags_0_go, _out_prepend_T_445}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5403 = out_prepend_445; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5404 = _out_T_5403; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_446 = _out_T_5404; // @[RegisterRouter.scala:87:24] wire out_rimask_529 = |_out_rimask_T_529; // @[RegisterRouter.scala:87:24] wire out_wimask_529 = &_out_wimask_T_529; // @[RegisterRouter.scala:87:24] wire out_romask_529 = |_out_romask_T_529; // @[RegisterRouter.scala:87:24] wire out_womask_529 = &_out_womask_T_529; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_529 = out_rivalid_1_383 & out_rimask_529; // @[RegisterRouter.scala:87:24] wire _out_T_5406 = out_f_rivalid_529; // @[RegisterRouter.scala:87:24] wire out_f_roready_529 = out_roready_1_383 & out_romask_529; // @[RegisterRouter.scala:87:24] wire _out_T_5407 = out_f_roready_529; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_529 = out_wivalid_1_383 & out_wimask_529; // @[RegisterRouter.scala:87:24] wire out_f_woready_529 = out_woready_1_383 & out_womask_529; // @[RegisterRouter.scala:87:24] wire _out_T_5408 = ~out_rimask_529; // @[RegisterRouter.scala:87:24] wire _out_T_5409 = ~out_wimask_529; // @[RegisterRouter.scala:87:24] wire _out_T_5410 = ~out_romask_529; // @[RegisterRouter.scala:87:24] wire _out_T_5411 = ~out_womask_529; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_446 = {hi_774, flags_0_go, _out_prepend_T_446}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5412 = out_prepend_446; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5413 = _out_T_5412; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_447 = _out_T_5413; // @[RegisterRouter.scala:87:24] wire out_rimask_530 = |_out_rimask_T_530; // @[RegisterRouter.scala:87:24] wire out_wimask_530 = &_out_wimask_T_530; // @[RegisterRouter.scala:87:24] wire out_romask_530 = |_out_romask_T_530; // @[RegisterRouter.scala:87:24] wire out_womask_530 = &_out_womask_T_530; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_530 = out_rivalid_1_384 & out_rimask_530; // @[RegisterRouter.scala:87:24] wire _out_T_5415 = out_f_rivalid_530; // @[RegisterRouter.scala:87:24] wire out_f_roready_530 = out_roready_1_384 & out_romask_530; // @[RegisterRouter.scala:87:24] wire _out_T_5416 = out_f_roready_530; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_530 = out_wivalid_1_384 & out_wimask_530; // @[RegisterRouter.scala:87:24] wire out_f_woready_530 = out_woready_1_384 & out_womask_530; // @[RegisterRouter.scala:87:24] wire _out_T_5417 = ~out_rimask_530; // @[RegisterRouter.scala:87:24] wire _out_T_5418 = ~out_wimask_530; // @[RegisterRouter.scala:87:24] wire _out_T_5419 = ~out_romask_530; // @[RegisterRouter.scala:87:24] wire _out_T_5420 = ~out_womask_530; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_447 = {hi_775, flags_0_go, _out_prepend_T_447}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5421 = out_prepend_447; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5422 = _out_T_5421; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_448 = _out_T_5422; // @[RegisterRouter.scala:87:24] wire out_rimask_531 = |_out_rimask_T_531; // @[RegisterRouter.scala:87:24] wire out_wimask_531 = &_out_wimask_T_531; // @[RegisterRouter.scala:87:24] wire out_romask_531 = |_out_romask_T_531; // @[RegisterRouter.scala:87:24] wire out_womask_531 = &_out_womask_T_531; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_531 = out_rivalid_1_385 & out_rimask_531; // @[RegisterRouter.scala:87:24] wire _out_T_5424 = out_f_rivalid_531; // @[RegisterRouter.scala:87:24] wire out_f_roready_531 = out_roready_1_385 & out_romask_531; // @[RegisterRouter.scala:87:24] wire _out_T_5425 = out_f_roready_531; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_531 = out_wivalid_1_385 & out_wimask_531; // @[RegisterRouter.scala:87:24] wire out_f_woready_531 = out_woready_1_385 & out_womask_531; // @[RegisterRouter.scala:87:24] wire _out_T_5426 = ~out_rimask_531; // @[RegisterRouter.scala:87:24] wire _out_T_5427 = ~out_wimask_531; // @[RegisterRouter.scala:87:24] wire _out_T_5428 = ~out_romask_531; // @[RegisterRouter.scala:87:24] wire _out_T_5429 = ~out_womask_531; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_448 = {hi_776, flags_0_go, _out_prepend_T_448}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5430 = out_prepend_448; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5431 = _out_T_5430; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_224 = _out_T_5431; // @[MuxLiteral.scala:49:48] wire out_rimask_532 = |_out_rimask_T_532; // @[RegisterRouter.scala:87:24] wire out_wimask_532 = &_out_wimask_T_532; // @[RegisterRouter.scala:87:24] wire out_romask_532 = |_out_romask_T_532; // @[RegisterRouter.scala:87:24] wire out_womask_532 = &_out_womask_T_532; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_532 = out_rivalid_1_386 & out_rimask_532; // @[RegisterRouter.scala:87:24] wire _out_T_5433 = out_f_rivalid_532; // @[RegisterRouter.scala:87:24] wire out_f_roready_532 = out_roready_1_386 & out_romask_532; // @[RegisterRouter.scala:87:24] wire _out_T_5434 = out_f_roready_532; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_532 = out_wivalid_1_386 & out_wimask_532; // @[RegisterRouter.scala:87:24] wire out_f_woready_532 = out_woready_1_386 & out_womask_532; // @[RegisterRouter.scala:87:24] wire _out_T_5435 = ~out_rimask_532; // @[RegisterRouter.scala:87:24] wire _out_T_5436 = ~out_wimask_532; // @[RegisterRouter.scala:87:24] wire _out_T_5437 = ~out_romask_532; // @[RegisterRouter.scala:87:24] wire _out_T_5438 = ~out_womask_532; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5440 = _out_T_5439; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_449 = _out_T_5440; // @[RegisterRouter.scala:87:24] wire out_rimask_533 = |_out_rimask_T_533; // @[RegisterRouter.scala:87:24] wire out_wimask_533 = &_out_wimask_T_533; // @[RegisterRouter.scala:87:24] wire out_romask_533 = |_out_romask_T_533; // @[RegisterRouter.scala:87:24] wire out_womask_533 = &_out_womask_T_533; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_533 = out_rivalid_1_387 & out_rimask_533; // @[RegisterRouter.scala:87:24] wire _out_T_5442 = out_f_rivalid_533; // @[RegisterRouter.scala:87:24] wire out_f_roready_533 = out_roready_1_387 & out_romask_533; // @[RegisterRouter.scala:87:24] wire _out_T_5443 = out_f_roready_533; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_533 = out_wivalid_1_387 & out_wimask_533; // @[RegisterRouter.scala:87:24] wire out_f_woready_533 = out_woready_1_387 & out_womask_533; // @[RegisterRouter.scala:87:24] wire _out_T_5444 = ~out_rimask_533; // @[RegisterRouter.scala:87:24] wire _out_T_5445 = ~out_wimask_533; // @[RegisterRouter.scala:87:24] wire _out_T_5446 = ~out_romask_533; // @[RegisterRouter.scala:87:24] wire _out_T_5447 = ~out_womask_533; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_449 = {hi_226, flags_0_go, _out_prepend_T_449}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5448 = out_prepend_449; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5449 = _out_T_5448; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_450 = _out_T_5449; // @[RegisterRouter.scala:87:24] wire out_rimask_534 = |_out_rimask_T_534; // @[RegisterRouter.scala:87:24] wire out_wimask_534 = &_out_wimask_T_534; // @[RegisterRouter.scala:87:24] wire out_romask_534 = |_out_romask_T_534; // @[RegisterRouter.scala:87:24] wire out_womask_534 = &_out_womask_T_534; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_534 = out_rivalid_1_388 & out_rimask_534; // @[RegisterRouter.scala:87:24] wire _out_T_5451 = out_f_rivalid_534; // @[RegisterRouter.scala:87:24] wire out_f_roready_534 = out_roready_1_388 & out_romask_534; // @[RegisterRouter.scala:87:24] wire _out_T_5452 = out_f_roready_534; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_534 = out_wivalid_1_388 & out_wimask_534; // @[RegisterRouter.scala:87:24] wire out_f_woready_534 = out_woready_1_388 & out_womask_534; // @[RegisterRouter.scala:87:24] wire _out_T_5453 = ~out_rimask_534; // @[RegisterRouter.scala:87:24] wire _out_T_5454 = ~out_wimask_534; // @[RegisterRouter.scala:87:24] wire _out_T_5455 = ~out_romask_534; // @[RegisterRouter.scala:87:24] wire _out_T_5456 = ~out_womask_534; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_450 = {hi_227, flags_0_go, _out_prepend_T_450}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5457 = out_prepend_450; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5458 = _out_T_5457; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_451 = _out_T_5458; // @[RegisterRouter.scala:87:24] wire out_rimask_535 = |_out_rimask_T_535; // @[RegisterRouter.scala:87:24] wire out_wimask_535 = &_out_wimask_T_535; // @[RegisterRouter.scala:87:24] wire out_romask_535 = |_out_romask_T_535; // @[RegisterRouter.scala:87:24] wire out_womask_535 = &_out_womask_T_535; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_535 = out_rivalid_1_389 & out_rimask_535; // @[RegisterRouter.scala:87:24] wire _out_T_5460 = out_f_rivalid_535; // @[RegisterRouter.scala:87:24] wire out_f_roready_535 = out_roready_1_389 & out_romask_535; // @[RegisterRouter.scala:87:24] wire _out_T_5461 = out_f_roready_535; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_535 = out_wivalid_1_389 & out_wimask_535; // @[RegisterRouter.scala:87:24] wire out_f_woready_535 = out_woready_1_389 & out_womask_535; // @[RegisterRouter.scala:87:24] wire _out_T_5462 = ~out_rimask_535; // @[RegisterRouter.scala:87:24] wire _out_T_5463 = ~out_wimask_535; // @[RegisterRouter.scala:87:24] wire _out_T_5464 = ~out_romask_535; // @[RegisterRouter.scala:87:24] wire _out_T_5465 = ~out_womask_535; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_451 = {hi_228, flags_0_go, _out_prepend_T_451}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5466 = out_prepend_451; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5467 = _out_T_5466; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_452 = _out_T_5467; // @[RegisterRouter.scala:87:24] wire out_rimask_536 = |_out_rimask_T_536; // @[RegisterRouter.scala:87:24] wire out_wimask_536 = &_out_wimask_T_536; // @[RegisterRouter.scala:87:24] wire out_romask_536 = |_out_romask_T_536; // @[RegisterRouter.scala:87:24] wire out_womask_536 = &_out_womask_T_536; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_536 = out_rivalid_1_390 & out_rimask_536; // @[RegisterRouter.scala:87:24] wire _out_T_5469 = out_f_rivalid_536; // @[RegisterRouter.scala:87:24] wire out_f_roready_536 = out_roready_1_390 & out_romask_536; // @[RegisterRouter.scala:87:24] wire _out_T_5470 = out_f_roready_536; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_536 = out_wivalid_1_390 & out_wimask_536; // @[RegisterRouter.scala:87:24] wire out_f_woready_536 = out_woready_1_390 & out_womask_536; // @[RegisterRouter.scala:87:24] wire _out_T_5471 = ~out_rimask_536; // @[RegisterRouter.scala:87:24] wire _out_T_5472 = ~out_wimask_536; // @[RegisterRouter.scala:87:24] wire _out_T_5473 = ~out_romask_536; // @[RegisterRouter.scala:87:24] wire _out_T_5474 = ~out_womask_536; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_452 = {hi_229, flags_0_go, _out_prepend_T_452}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5475 = out_prepend_452; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5476 = _out_T_5475; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_453 = _out_T_5476; // @[RegisterRouter.scala:87:24] wire out_rimask_537 = |_out_rimask_T_537; // @[RegisterRouter.scala:87:24] wire out_wimask_537 = &_out_wimask_T_537; // @[RegisterRouter.scala:87:24] wire out_romask_537 = |_out_romask_T_537; // @[RegisterRouter.scala:87:24] wire out_womask_537 = &_out_womask_T_537; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_537 = out_rivalid_1_391 & out_rimask_537; // @[RegisterRouter.scala:87:24] wire _out_T_5478 = out_f_rivalid_537; // @[RegisterRouter.scala:87:24] wire out_f_roready_537 = out_roready_1_391 & out_romask_537; // @[RegisterRouter.scala:87:24] wire _out_T_5479 = out_f_roready_537; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_537 = out_wivalid_1_391 & out_wimask_537; // @[RegisterRouter.scala:87:24] wire out_f_woready_537 = out_woready_1_391 & out_womask_537; // @[RegisterRouter.scala:87:24] wire _out_T_5480 = ~out_rimask_537; // @[RegisterRouter.scala:87:24] wire _out_T_5481 = ~out_wimask_537; // @[RegisterRouter.scala:87:24] wire _out_T_5482 = ~out_romask_537; // @[RegisterRouter.scala:87:24] wire _out_T_5483 = ~out_womask_537; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_453 = {hi_230, flags_0_go, _out_prepend_T_453}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5484 = out_prepend_453; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5485 = _out_T_5484; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_454 = _out_T_5485; // @[RegisterRouter.scala:87:24] wire out_rimask_538 = |_out_rimask_T_538; // @[RegisterRouter.scala:87:24] wire out_wimask_538 = &_out_wimask_T_538; // @[RegisterRouter.scala:87:24] wire out_romask_538 = |_out_romask_T_538; // @[RegisterRouter.scala:87:24] wire out_womask_538 = &_out_womask_T_538; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_538 = out_rivalid_1_392 & out_rimask_538; // @[RegisterRouter.scala:87:24] wire _out_T_5487 = out_f_rivalid_538; // @[RegisterRouter.scala:87:24] wire out_f_roready_538 = out_roready_1_392 & out_romask_538; // @[RegisterRouter.scala:87:24] wire _out_T_5488 = out_f_roready_538; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_538 = out_wivalid_1_392 & out_wimask_538; // @[RegisterRouter.scala:87:24] wire out_f_woready_538 = out_woready_1_392 & out_womask_538; // @[RegisterRouter.scala:87:24] wire _out_T_5489 = ~out_rimask_538; // @[RegisterRouter.scala:87:24] wire _out_T_5490 = ~out_wimask_538; // @[RegisterRouter.scala:87:24] wire _out_T_5491 = ~out_romask_538; // @[RegisterRouter.scala:87:24] wire _out_T_5492 = ~out_womask_538; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_454 = {hi_231, flags_0_go, _out_prepend_T_454}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5493 = out_prepend_454; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5494 = _out_T_5493; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_455 = _out_T_5494; // @[RegisterRouter.scala:87:24] wire out_rimask_539 = |_out_rimask_T_539; // @[RegisterRouter.scala:87:24] wire out_wimask_539 = &_out_wimask_T_539; // @[RegisterRouter.scala:87:24] wire out_romask_539 = |_out_romask_T_539; // @[RegisterRouter.scala:87:24] wire out_womask_539 = &_out_womask_T_539; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_539 = out_rivalid_1_393 & out_rimask_539; // @[RegisterRouter.scala:87:24] wire _out_T_5496 = out_f_rivalid_539; // @[RegisterRouter.scala:87:24] wire out_f_roready_539 = out_roready_1_393 & out_romask_539; // @[RegisterRouter.scala:87:24] wire _out_T_5497 = out_f_roready_539; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_539 = out_wivalid_1_393 & out_wimask_539; // @[RegisterRouter.scala:87:24] wire out_f_woready_539 = out_woready_1_393 & out_womask_539; // @[RegisterRouter.scala:87:24] wire _out_T_5498 = ~out_rimask_539; // @[RegisterRouter.scala:87:24] wire _out_T_5499 = ~out_wimask_539; // @[RegisterRouter.scala:87:24] wire _out_T_5500 = ~out_romask_539; // @[RegisterRouter.scala:87:24] wire _out_T_5501 = ~out_womask_539; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_455 = {hi_232, flags_0_go, _out_prepend_T_455}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5502 = out_prepend_455; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5503 = _out_T_5502; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_156 = _out_T_5503; // @[MuxLiteral.scala:49:48] wire out_rimask_540 = |_out_rimask_T_540; // @[RegisterRouter.scala:87:24] wire out_wimask_540 = &_out_wimask_T_540; // @[RegisterRouter.scala:87:24] wire out_romask_540 = |_out_romask_T_540; // @[RegisterRouter.scala:87:24] wire out_womask_540 = &_out_womask_T_540; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_540 = out_rivalid_1_394 & out_rimask_540; // @[RegisterRouter.scala:87:24] wire _out_T_5505 = out_f_rivalid_540; // @[RegisterRouter.scala:87:24] wire out_f_roready_540 = out_roready_1_394 & out_romask_540; // @[RegisterRouter.scala:87:24] wire _out_T_5506 = out_f_roready_540; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_540 = out_wivalid_1_394 & out_wimask_540; // @[RegisterRouter.scala:87:24] wire out_f_woready_540 = out_woready_1_394 & out_womask_540; // @[RegisterRouter.scala:87:24] wire _out_T_5507 = ~out_rimask_540; // @[RegisterRouter.scala:87:24] wire _out_T_5508 = ~out_wimask_540; // @[RegisterRouter.scala:87:24] wire _out_T_5509 = ~out_romask_540; // @[RegisterRouter.scala:87:24] wire _out_T_5510 = ~out_womask_540; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5512 = _out_T_5511; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_456 = _out_T_5512; // @[RegisterRouter.scala:87:24] wire out_rimask_541 = |_out_rimask_T_541; // @[RegisterRouter.scala:87:24] wire out_wimask_541 = &_out_wimask_T_541; // @[RegisterRouter.scala:87:24] wire out_romask_541 = |_out_romask_T_541; // @[RegisterRouter.scala:87:24] wire out_womask_541 = &_out_womask_T_541; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_541 = out_rivalid_1_395 & out_rimask_541; // @[RegisterRouter.scala:87:24] wire _out_T_5514 = out_f_rivalid_541; // @[RegisterRouter.scala:87:24] wire out_f_roready_541 = out_roready_1_395 & out_romask_541; // @[RegisterRouter.scala:87:24] wire _out_T_5515 = out_f_roready_541; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_541 = out_wivalid_1_395 & out_wimask_541; // @[RegisterRouter.scala:87:24] wire out_f_woready_541 = out_woready_1_395 & out_womask_541; // @[RegisterRouter.scala:87:24] wire _out_T_5516 = ~out_rimask_541; // @[RegisterRouter.scala:87:24] wire _out_T_5517 = ~out_wimask_541; // @[RegisterRouter.scala:87:24] wire _out_T_5518 = ~out_romask_541; // @[RegisterRouter.scala:87:24] wire _out_T_5519 = ~out_womask_541; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_456 = {hi_482, flags_0_go, _out_prepend_T_456}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5520 = out_prepend_456; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5521 = _out_T_5520; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_457 = _out_T_5521; // @[RegisterRouter.scala:87:24] wire out_rimask_542 = |_out_rimask_T_542; // @[RegisterRouter.scala:87:24] wire out_wimask_542 = &_out_wimask_T_542; // @[RegisterRouter.scala:87:24] wire out_romask_542 = |_out_romask_T_542; // @[RegisterRouter.scala:87:24] wire out_womask_542 = &_out_womask_T_542; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_542 = out_rivalid_1_396 & out_rimask_542; // @[RegisterRouter.scala:87:24] wire _out_T_5523 = out_f_rivalid_542; // @[RegisterRouter.scala:87:24] wire out_f_roready_542 = out_roready_1_396 & out_romask_542; // @[RegisterRouter.scala:87:24] wire _out_T_5524 = out_f_roready_542; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_542 = out_wivalid_1_396 & out_wimask_542; // @[RegisterRouter.scala:87:24] wire out_f_woready_542 = out_woready_1_396 & out_womask_542; // @[RegisterRouter.scala:87:24] wire _out_T_5525 = ~out_rimask_542; // @[RegisterRouter.scala:87:24] wire _out_T_5526 = ~out_wimask_542; // @[RegisterRouter.scala:87:24] wire _out_T_5527 = ~out_romask_542; // @[RegisterRouter.scala:87:24] wire _out_T_5528 = ~out_womask_542; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_457 = {hi_483, flags_0_go, _out_prepend_T_457}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5529 = out_prepend_457; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5530 = _out_T_5529; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_458 = _out_T_5530; // @[RegisterRouter.scala:87:24] wire out_rimask_543 = |_out_rimask_T_543; // @[RegisterRouter.scala:87:24] wire out_wimask_543 = &_out_wimask_T_543; // @[RegisterRouter.scala:87:24] wire out_romask_543 = |_out_romask_T_543; // @[RegisterRouter.scala:87:24] wire out_womask_543 = &_out_womask_T_543; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_543 = out_rivalid_1_397 & out_rimask_543; // @[RegisterRouter.scala:87:24] wire _out_T_5532 = out_f_rivalid_543; // @[RegisterRouter.scala:87:24] wire out_f_roready_543 = out_roready_1_397 & out_romask_543; // @[RegisterRouter.scala:87:24] wire _out_T_5533 = out_f_roready_543; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_543 = out_wivalid_1_397 & out_wimask_543; // @[RegisterRouter.scala:87:24] wire out_f_woready_543 = out_woready_1_397 & out_womask_543; // @[RegisterRouter.scala:87:24] wire _out_T_5534 = ~out_rimask_543; // @[RegisterRouter.scala:87:24] wire _out_T_5535 = ~out_wimask_543; // @[RegisterRouter.scala:87:24] wire _out_T_5536 = ~out_romask_543; // @[RegisterRouter.scala:87:24] wire _out_T_5537 = ~out_womask_543; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_458 = {hi_484, flags_0_go, _out_prepend_T_458}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5538 = out_prepend_458; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5539 = _out_T_5538; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_459 = _out_T_5539; // @[RegisterRouter.scala:87:24] wire out_rimask_544 = |_out_rimask_T_544; // @[RegisterRouter.scala:87:24] wire out_wimask_544 = &_out_wimask_T_544; // @[RegisterRouter.scala:87:24] wire out_romask_544 = |_out_romask_T_544; // @[RegisterRouter.scala:87:24] wire out_womask_544 = &_out_womask_T_544; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_544 = out_rivalid_1_398 & out_rimask_544; // @[RegisterRouter.scala:87:24] wire _out_T_5541 = out_f_rivalid_544; // @[RegisterRouter.scala:87:24] wire out_f_roready_544 = out_roready_1_398 & out_romask_544; // @[RegisterRouter.scala:87:24] wire _out_T_5542 = out_f_roready_544; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_544 = out_wivalid_1_398 & out_wimask_544; // @[RegisterRouter.scala:87:24] wire out_f_woready_544 = out_woready_1_398 & out_womask_544; // @[RegisterRouter.scala:87:24] wire _out_T_5543 = ~out_rimask_544; // @[RegisterRouter.scala:87:24] wire _out_T_5544 = ~out_wimask_544; // @[RegisterRouter.scala:87:24] wire _out_T_5545 = ~out_romask_544; // @[RegisterRouter.scala:87:24] wire _out_T_5546 = ~out_womask_544; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_459 = {hi_485, flags_0_go, _out_prepend_T_459}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5547 = out_prepend_459; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5548 = _out_T_5547; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_460 = _out_T_5548; // @[RegisterRouter.scala:87:24] wire out_rimask_545 = |_out_rimask_T_545; // @[RegisterRouter.scala:87:24] wire out_wimask_545 = &_out_wimask_T_545; // @[RegisterRouter.scala:87:24] wire out_romask_545 = |_out_romask_T_545; // @[RegisterRouter.scala:87:24] wire out_womask_545 = &_out_womask_T_545; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_545 = out_rivalid_1_399 & out_rimask_545; // @[RegisterRouter.scala:87:24] wire _out_T_5550 = out_f_rivalid_545; // @[RegisterRouter.scala:87:24] wire out_f_roready_545 = out_roready_1_399 & out_romask_545; // @[RegisterRouter.scala:87:24] wire _out_T_5551 = out_f_roready_545; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_545 = out_wivalid_1_399 & out_wimask_545; // @[RegisterRouter.scala:87:24] wire out_f_woready_545 = out_woready_1_399 & out_womask_545; // @[RegisterRouter.scala:87:24] wire _out_T_5552 = ~out_rimask_545; // @[RegisterRouter.scala:87:24] wire _out_T_5553 = ~out_wimask_545; // @[RegisterRouter.scala:87:24] wire _out_T_5554 = ~out_romask_545; // @[RegisterRouter.scala:87:24] wire _out_T_5555 = ~out_womask_545; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_460 = {hi_486, flags_0_go, _out_prepend_T_460}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5556 = out_prepend_460; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5557 = _out_T_5556; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_461 = _out_T_5557; // @[RegisterRouter.scala:87:24] wire out_rimask_546 = |_out_rimask_T_546; // @[RegisterRouter.scala:87:24] wire out_wimask_546 = &_out_wimask_T_546; // @[RegisterRouter.scala:87:24] wire out_romask_546 = |_out_romask_T_546; // @[RegisterRouter.scala:87:24] wire out_womask_546 = &_out_womask_T_546; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_546 = out_rivalid_1_400 & out_rimask_546; // @[RegisterRouter.scala:87:24] wire _out_T_5559 = out_f_rivalid_546; // @[RegisterRouter.scala:87:24] wire out_f_roready_546 = out_roready_1_400 & out_romask_546; // @[RegisterRouter.scala:87:24] wire _out_T_5560 = out_f_roready_546; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_546 = out_wivalid_1_400 & out_wimask_546; // @[RegisterRouter.scala:87:24] wire out_f_woready_546 = out_woready_1_400 & out_womask_546; // @[RegisterRouter.scala:87:24] wire _out_T_5561 = ~out_rimask_546; // @[RegisterRouter.scala:87:24] wire _out_T_5562 = ~out_wimask_546; // @[RegisterRouter.scala:87:24] wire _out_T_5563 = ~out_romask_546; // @[RegisterRouter.scala:87:24] wire _out_T_5564 = ~out_womask_546; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_461 = {hi_487, flags_0_go, _out_prepend_T_461}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5565 = out_prepend_461; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5566 = _out_T_5565; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_462 = _out_T_5566; // @[RegisterRouter.scala:87:24] wire out_rimask_547 = |_out_rimask_T_547; // @[RegisterRouter.scala:87:24] wire out_wimask_547 = &_out_wimask_T_547; // @[RegisterRouter.scala:87:24] wire out_romask_547 = |_out_romask_T_547; // @[RegisterRouter.scala:87:24] wire out_womask_547 = &_out_womask_T_547; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_547 = out_rivalid_1_401 & out_rimask_547; // @[RegisterRouter.scala:87:24] wire _out_T_5568 = out_f_rivalid_547; // @[RegisterRouter.scala:87:24] wire out_f_roready_547 = out_roready_1_401 & out_romask_547; // @[RegisterRouter.scala:87:24] wire _out_T_5569 = out_f_roready_547; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_547 = out_wivalid_1_401 & out_wimask_547; // @[RegisterRouter.scala:87:24] wire out_f_woready_547 = out_woready_1_401 & out_womask_547; // @[RegisterRouter.scala:87:24] wire _out_T_5570 = ~out_rimask_547; // @[RegisterRouter.scala:87:24] wire _out_T_5571 = ~out_wimask_547; // @[RegisterRouter.scala:87:24] wire _out_T_5572 = ~out_romask_547; // @[RegisterRouter.scala:87:24] wire _out_T_5573 = ~out_womask_547; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_462 = {hi_488, flags_0_go, _out_prepend_T_462}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5574 = out_prepend_462; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5575 = _out_T_5574; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_188 = _out_T_5575; // @[MuxLiteral.scala:49:48] wire out_rimask_548 = |_out_rimask_T_548; // @[RegisterRouter.scala:87:24] wire out_wimask_548 = &_out_wimask_T_548; // @[RegisterRouter.scala:87:24] wire out_romask_548 = |_out_romask_T_548; // @[RegisterRouter.scala:87:24] wire out_womask_548 = &_out_womask_T_548; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_548 = out_rivalid_1_402 & out_rimask_548; // @[RegisterRouter.scala:87:24] wire _out_T_5577 = out_f_rivalid_548; // @[RegisterRouter.scala:87:24] wire out_f_roready_548 = out_roready_1_402 & out_romask_548; // @[RegisterRouter.scala:87:24] wire _out_T_5578 = out_f_roready_548; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_548 = out_wivalid_1_402 & out_wimask_548; // @[RegisterRouter.scala:87:24] wire out_f_woready_548 = out_woready_1_402 & out_womask_548; // @[RegisterRouter.scala:87:24] wire _out_T_5579 = ~out_rimask_548; // @[RegisterRouter.scala:87:24] wire _out_T_5580 = ~out_wimask_548; // @[RegisterRouter.scala:87:24] wire _out_T_5581 = ~out_romask_548; // @[RegisterRouter.scala:87:24] wire _out_T_5582 = ~out_womask_548; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5584 = _out_T_5583; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_463 = _out_T_5584; // @[RegisterRouter.scala:87:24] wire out_rimask_549 = |_out_rimask_T_549; // @[RegisterRouter.scala:87:24] wire out_wimask_549 = &_out_wimask_T_549; // @[RegisterRouter.scala:87:24] wire out_romask_549 = |_out_romask_T_549; // @[RegisterRouter.scala:87:24] wire out_womask_549 = &_out_womask_T_549; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_549 = out_rivalid_1_403 & out_rimask_549; // @[RegisterRouter.scala:87:24] wire _out_T_5586 = out_f_rivalid_549; // @[RegisterRouter.scala:87:24] wire out_f_roready_549 = out_roready_1_403 & out_romask_549; // @[RegisterRouter.scala:87:24] wire _out_T_5587 = out_f_roready_549; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_549 = out_wivalid_1_403 & out_wimask_549; // @[RegisterRouter.scala:87:24] wire out_f_woready_549 = out_woready_1_403 & out_womask_549; // @[RegisterRouter.scala:87:24] wire _out_T_5588 = ~out_rimask_549; // @[RegisterRouter.scala:87:24] wire _out_T_5589 = ~out_wimask_549; // @[RegisterRouter.scala:87:24] wire _out_T_5590 = ~out_romask_549; // @[RegisterRouter.scala:87:24] wire _out_T_5591 = ~out_womask_549; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_463 = {hi_330, flags_0_go, _out_prepend_T_463}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5592 = out_prepend_463; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5593 = _out_T_5592; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_464 = _out_T_5593; // @[RegisterRouter.scala:87:24] wire out_rimask_550 = |_out_rimask_T_550; // @[RegisterRouter.scala:87:24] wire out_wimask_550 = &_out_wimask_T_550; // @[RegisterRouter.scala:87:24] wire out_romask_550 = |_out_romask_T_550; // @[RegisterRouter.scala:87:24] wire out_womask_550 = &_out_womask_T_550; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_550 = out_rivalid_1_404 & out_rimask_550; // @[RegisterRouter.scala:87:24] wire _out_T_5595 = out_f_rivalid_550; // @[RegisterRouter.scala:87:24] wire out_f_roready_550 = out_roready_1_404 & out_romask_550; // @[RegisterRouter.scala:87:24] wire _out_T_5596 = out_f_roready_550; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_550 = out_wivalid_1_404 & out_wimask_550; // @[RegisterRouter.scala:87:24] wire out_f_woready_550 = out_woready_1_404 & out_womask_550; // @[RegisterRouter.scala:87:24] wire _out_T_5597 = ~out_rimask_550; // @[RegisterRouter.scala:87:24] wire _out_T_5598 = ~out_wimask_550; // @[RegisterRouter.scala:87:24] wire _out_T_5599 = ~out_romask_550; // @[RegisterRouter.scala:87:24] wire _out_T_5600 = ~out_womask_550; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_464 = {hi_331, flags_0_go, _out_prepend_T_464}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5601 = out_prepend_464; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5602 = _out_T_5601; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_465 = _out_T_5602; // @[RegisterRouter.scala:87:24] wire out_rimask_551 = |_out_rimask_T_551; // @[RegisterRouter.scala:87:24] wire out_wimask_551 = &_out_wimask_T_551; // @[RegisterRouter.scala:87:24] wire out_romask_551 = |_out_romask_T_551; // @[RegisterRouter.scala:87:24] wire out_womask_551 = &_out_womask_T_551; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_551 = out_rivalid_1_405 & out_rimask_551; // @[RegisterRouter.scala:87:24] wire _out_T_5604 = out_f_rivalid_551; // @[RegisterRouter.scala:87:24] wire out_f_roready_551 = out_roready_1_405 & out_romask_551; // @[RegisterRouter.scala:87:24] wire _out_T_5605 = out_f_roready_551; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_551 = out_wivalid_1_405 & out_wimask_551; // @[RegisterRouter.scala:87:24] wire out_f_woready_551 = out_woready_1_405 & out_womask_551; // @[RegisterRouter.scala:87:24] wire _out_T_5606 = ~out_rimask_551; // @[RegisterRouter.scala:87:24] wire _out_T_5607 = ~out_wimask_551; // @[RegisterRouter.scala:87:24] wire _out_T_5608 = ~out_romask_551; // @[RegisterRouter.scala:87:24] wire _out_T_5609 = ~out_womask_551; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_465 = {hi_332, flags_0_go, _out_prepend_T_465}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5610 = out_prepend_465; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5611 = _out_T_5610; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_466 = _out_T_5611; // @[RegisterRouter.scala:87:24] wire out_rimask_552 = |_out_rimask_T_552; // @[RegisterRouter.scala:87:24] wire out_wimask_552 = &_out_wimask_T_552; // @[RegisterRouter.scala:87:24] wire out_romask_552 = |_out_romask_T_552; // @[RegisterRouter.scala:87:24] wire out_womask_552 = &_out_womask_T_552; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_552 = out_rivalid_1_406 & out_rimask_552; // @[RegisterRouter.scala:87:24] wire _out_T_5613 = out_f_rivalid_552; // @[RegisterRouter.scala:87:24] wire out_f_roready_552 = out_roready_1_406 & out_romask_552; // @[RegisterRouter.scala:87:24] wire _out_T_5614 = out_f_roready_552; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_552 = out_wivalid_1_406 & out_wimask_552; // @[RegisterRouter.scala:87:24] wire out_f_woready_552 = out_woready_1_406 & out_womask_552; // @[RegisterRouter.scala:87:24] wire _out_T_5615 = ~out_rimask_552; // @[RegisterRouter.scala:87:24] wire _out_T_5616 = ~out_wimask_552; // @[RegisterRouter.scala:87:24] wire _out_T_5617 = ~out_romask_552; // @[RegisterRouter.scala:87:24] wire _out_T_5618 = ~out_womask_552; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_466 = {hi_333, flags_0_go, _out_prepend_T_466}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5619 = out_prepend_466; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5620 = _out_T_5619; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_467 = _out_T_5620; // @[RegisterRouter.scala:87:24] wire out_rimask_553 = |_out_rimask_T_553; // @[RegisterRouter.scala:87:24] wire out_wimask_553 = &_out_wimask_T_553; // @[RegisterRouter.scala:87:24] wire out_romask_553 = |_out_romask_T_553; // @[RegisterRouter.scala:87:24] wire out_womask_553 = &_out_womask_T_553; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_553 = out_rivalid_1_407 & out_rimask_553; // @[RegisterRouter.scala:87:24] wire _out_T_5622 = out_f_rivalid_553; // @[RegisterRouter.scala:87:24] wire out_f_roready_553 = out_roready_1_407 & out_romask_553; // @[RegisterRouter.scala:87:24] wire _out_T_5623 = out_f_roready_553; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_553 = out_wivalid_1_407 & out_wimask_553; // @[RegisterRouter.scala:87:24] wire out_f_woready_553 = out_woready_1_407 & out_womask_553; // @[RegisterRouter.scala:87:24] wire _out_T_5624 = ~out_rimask_553; // @[RegisterRouter.scala:87:24] wire _out_T_5625 = ~out_wimask_553; // @[RegisterRouter.scala:87:24] wire _out_T_5626 = ~out_romask_553; // @[RegisterRouter.scala:87:24] wire _out_T_5627 = ~out_womask_553; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_467 = {hi_334, flags_0_go, _out_prepend_T_467}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5628 = out_prepend_467; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5629 = _out_T_5628; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_468 = _out_T_5629; // @[RegisterRouter.scala:87:24] wire out_rimask_554 = |_out_rimask_T_554; // @[RegisterRouter.scala:87:24] wire out_wimask_554 = &_out_wimask_T_554; // @[RegisterRouter.scala:87:24] wire out_romask_554 = |_out_romask_T_554; // @[RegisterRouter.scala:87:24] wire out_womask_554 = &_out_womask_T_554; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_554 = out_rivalid_1_408 & out_rimask_554; // @[RegisterRouter.scala:87:24] wire _out_T_5631 = out_f_rivalid_554; // @[RegisterRouter.scala:87:24] wire out_f_roready_554 = out_roready_1_408 & out_romask_554; // @[RegisterRouter.scala:87:24] wire _out_T_5632 = out_f_roready_554; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_554 = out_wivalid_1_408 & out_wimask_554; // @[RegisterRouter.scala:87:24] wire out_f_woready_554 = out_woready_1_408 & out_womask_554; // @[RegisterRouter.scala:87:24] wire _out_T_5633 = ~out_rimask_554; // @[RegisterRouter.scala:87:24] wire _out_T_5634 = ~out_wimask_554; // @[RegisterRouter.scala:87:24] wire _out_T_5635 = ~out_romask_554; // @[RegisterRouter.scala:87:24] wire _out_T_5636 = ~out_womask_554; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_468 = {hi_335, flags_0_go, _out_prepend_T_468}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5637 = out_prepend_468; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5638 = _out_T_5637; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_469 = _out_T_5638; // @[RegisterRouter.scala:87:24] wire out_rimask_555 = |_out_rimask_T_555; // @[RegisterRouter.scala:87:24] wire out_wimask_555 = &_out_wimask_T_555; // @[RegisterRouter.scala:87:24] wire out_romask_555 = |_out_romask_T_555; // @[RegisterRouter.scala:87:24] wire out_womask_555 = &_out_womask_T_555; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_555 = out_rivalid_1_409 & out_rimask_555; // @[RegisterRouter.scala:87:24] wire _out_T_5640 = out_f_rivalid_555; // @[RegisterRouter.scala:87:24] wire out_f_roready_555 = out_roready_1_409 & out_romask_555; // @[RegisterRouter.scala:87:24] wire _out_T_5641 = out_f_roready_555; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_555 = out_wivalid_1_409 & out_wimask_555; // @[RegisterRouter.scala:87:24] wire out_f_woready_555 = out_woready_1_409 & out_womask_555; // @[RegisterRouter.scala:87:24] wire _out_T_5642 = ~out_rimask_555; // @[RegisterRouter.scala:87:24] wire _out_T_5643 = ~out_wimask_555; // @[RegisterRouter.scala:87:24] wire _out_T_5644 = ~out_romask_555; // @[RegisterRouter.scala:87:24] wire _out_T_5645 = ~out_womask_555; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_469 = {hi_336, flags_0_go, _out_prepend_T_469}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5646 = out_prepend_469; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5647 = _out_T_5646; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_169 = _out_T_5647; // @[MuxLiteral.scala:49:48] wire out_rimask_556 = |_out_rimask_T_556; // @[RegisterRouter.scala:87:24] wire out_wimask_556 = &_out_wimask_T_556; // @[RegisterRouter.scala:87:24] wire out_romask_556 = |_out_romask_T_556; // @[RegisterRouter.scala:87:24] wire out_womask_556 = &_out_womask_T_556; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_556 = out_rivalid_1_410 & out_rimask_556; // @[RegisterRouter.scala:87:24] wire _out_T_5649 = out_f_rivalid_556; // @[RegisterRouter.scala:87:24] wire out_f_roready_556 = out_roready_1_410 & out_romask_556; // @[RegisterRouter.scala:87:24] wire _out_T_5650 = out_f_roready_556; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_556 = out_wivalid_1_410 & out_wimask_556; // @[RegisterRouter.scala:87:24] wire out_f_woready_556 = out_woready_1_410 & out_womask_556; // @[RegisterRouter.scala:87:24] wire _out_T_5651 = ~out_rimask_556; // @[RegisterRouter.scala:87:24] wire _out_T_5652 = ~out_wimask_556; // @[RegisterRouter.scala:87:24] wire _out_T_5653 = ~out_romask_556; // @[RegisterRouter.scala:87:24] wire _out_T_5654 = ~out_womask_556; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5656 = _out_T_5655; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_470 = _out_T_5656; // @[RegisterRouter.scala:87:24] wire out_rimask_557 = |_out_rimask_T_557; // @[RegisterRouter.scala:87:24] wire out_wimask_557 = &_out_wimask_T_557; // @[RegisterRouter.scala:87:24] wire out_romask_557 = |_out_romask_T_557; // @[RegisterRouter.scala:87:24] wire out_womask_557 = &_out_womask_T_557; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_557 = out_rivalid_1_411 & out_rimask_557; // @[RegisterRouter.scala:87:24] wire _out_T_5658 = out_f_rivalid_557; // @[RegisterRouter.scala:87:24] wire out_f_roready_557 = out_roready_1_411 & out_romask_557; // @[RegisterRouter.scala:87:24] wire _out_T_5659 = out_f_roready_557; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_557 = out_wivalid_1_411 & out_wimask_557; // @[RegisterRouter.scala:87:24] wire out_f_woready_557 = out_woready_1_411 & out_womask_557; // @[RegisterRouter.scala:87:24] wire _out_T_5660 = ~out_rimask_557; // @[RegisterRouter.scala:87:24] wire _out_T_5661 = ~out_wimask_557; // @[RegisterRouter.scala:87:24] wire _out_T_5662 = ~out_romask_557; // @[RegisterRouter.scala:87:24] wire _out_T_5663 = ~out_womask_557; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_470 = {hi_106, flags_0_go, _out_prepend_T_470}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5664 = out_prepend_470; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5665 = _out_T_5664; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_471 = _out_T_5665; // @[RegisterRouter.scala:87:24] wire out_rimask_558 = |_out_rimask_T_558; // @[RegisterRouter.scala:87:24] wire out_wimask_558 = &_out_wimask_T_558; // @[RegisterRouter.scala:87:24] wire out_romask_558 = |_out_romask_T_558; // @[RegisterRouter.scala:87:24] wire out_womask_558 = &_out_womask_T_558; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_558 = out_rivalid_1_412 & out_rimask_558; // @[RegisterRouter.scala:87:24] wire _out_T_5667 = out_f_rivalid_558; // @[RegisterRouter.scala:87:24] wire out_f_roready_558 = out_roready_1_412 & out_romask_558; // @[RegisterRouter.scala:87:24] wire _out_T_5668 = out_f_roready_558; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_558 = out_wivalid_1_412 & out_wimask_558; // @[RegisterRouter.scala:87:24] wire out_f_woready_558 = out_woready_1_412 & out_womask_558; // @[RegisterRouter.scala:87:24] wire _out_T_5669 = ~out_rimask_558; // @[RegisterRouter.scala:87:24] wire _out_T_5670 = ~out_wimask_558; // @[RegisterRouter.scala:87:24] wire _out_T_5671 = ~out_romask_558; // @[RegisterRouter.scala:87:24] wire _out_T_5672 = ~out_womask_558; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_471 = {hi_107, flags_0_go, _out_prepend_T_471}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5673 = out_prepend_471; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5674 = _out_T_5673; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_472 = _out_T_5674; // @[RegisterRouter.scala:87:24] wire out_rimask_559 = |_out_rimask_T_559; // @[RegisterRouter.scala:87:24] wire out_wimask_559 = &_out_wimask_T_559; // @[RegisterRouter.scala:87:24] wire out_romask_559 = |_out_romask_T_559; // @[RegisterRouter.scala:87:24] wire out_womask_559 = &_out_womask_T_559; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_559 = out_rivalid_1_413 & out_rimask_559; // @[RegisterRouter.scala:87:24] wire _out_T_5676 = out_f_rivalid_559; // @[RegisterRouter.scala:87:24] wire out_f_roready_559 = out_roready_1_413 & out_romask_559; // @[RegisterRouter.scala:87:24] wire _out_T_5677 = out_f_roready_559; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_559 = out_wivalid_1_413 & out_wimask_559; // @[RegisterRouter.scala:87:24] wire out_f_woready_559 = out_woready_1_413 & out_womask_559; // @[RegisterRouter.scala:87:24] wire _out_T_5678 = ~out_rimask_559; // @[RegisterRouter.scala:87:24] wire _out_T_5679 = ~out_wimask_559; // @[RegisterRouter.scala:87:24] wire _out_T_5680 = ~out_romask_559; // @[RegisterRouter.scala:87:24] wire _out_T_5681 = ~out_womask_559; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_472 = {hi_108, flags_0_go, _out_prepend_T_472}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5682 = out_prepend_472; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5683 = _out_T_5682; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_473 = _out_T_5683; // @[RegisterRouter.scala:87:24] wire out_rimask_560 = |_out_rimask_T_560; // @[RegisterRouter.scala:87:24] wire out_wimask_560 = &_out_wimask_T_560; // @[RegisterRouter.scala:87:24] wire out_romask_560 = |_out_romask_T_560; // @[RegisterRouter.scala:87:24] wire out_womask_560 = &_out_womask_T_560; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_560 = out_rivalid_1_414 & out_rimask_560; // @[RegisterRouter.scala:87:24] wire _out_T_5685 = out_f_rivalid_560; // @[RegisterRouter.scala:87:24] wire out_f_roready_560 = out_roready_1_414 & out_romask_560; // @[RegisterRouter.scala:87:24] wire _out_T_5686 = out_f_roready_560; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_560 = out_wivalid_1_414 & out_wimask_560; // @[RegisterRouter.scala:87:24] wire out_f_woready_560 = out_woready_1_414 & out_womask_560; // @[RegisterRouter.scala:87:24] wire _out_T_5687 = ~out_rimask_560; // @[RegisterRouter.scala:87:24] wire _out_T_5688 = ~out_wimask_560; // @[RegisterRouter.scala:87:24] wire _out_T_5689 = ~out_romask_560; // @[RegisterRouter.scala:87:24] wire _out_T_5690 = ~out_womask_560; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_473 = {hi_109, flags_0_go, _out_prepend_T_473}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5691 = out_prepend_473; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5692 = _out_T_5691; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_474 = _out_T_5692; // @[RegisterRouter.scala:87:24] wire out_rimask_561 = |_out_rimask_T_561; // @[RegisterRouter.scala:87:24] wire out_wimask_561 = &_out_wimask_T_561; // @[RegisterRouter.scala:87:24] wire out_romask_561 = |_out_romask_T_561; // @[RegisterRouter.scala:87:24] wire out_womask_561 = &_out_womask_T_561; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_561 = out_rivalid_1_415 & out_rimask_561; // @[RegisterRouter.scala:87:24] wire _out_T_5694 = out_f_rivalid_561; // @[RegisterRouter.scala:87:24] wire out_f_roready_561 = out_roready_1_415 & out_romask_561; // @[RegisterRouter.scala:87:24] wire _out_T_5695 = out_f_roready_561; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_561 = out_wivalid_1_415 & out_wimask_561; // @[RegisterRouter.scala:87:24] wire out_f_woready_561 = out_woready_1_415 & out_womask_561; // @[RegisterRouter.scala:87:24] wire _out_T_5696 = ~out_rimask_561; // @[RegisterRouter.scala:87:24] wire _out_T_5697 = ~out_wimask_561; // @[RegisterRouter.scala:87:24] wire _out_T_5698 = ~out_romask_561; // @[RegisterRouter.scala:87:24] wire _out_T_5699 = ~out_womask_561; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_474 = {hi_110, flags_0_go, _out_prepend_T_474}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5700 = out_prepend_474; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5701 = _out_T_5700; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_475 = _out_T_5701; // @[RegisterRouter.scala:87:24] wire out_rimask_562 = |_out_rimask_T_562; // @[RegisterRouter.scala:87:24] wire out_wimask_562 = &_out_wimask_T_562; // @[RegisterRouter.scala:87:24] wire out_romask_562 = |_out_romask_T_562; // @[RegisterRouter.scala:87:24] wire out_womask_562 = &_out_womask_T_562; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_562 = out_rivalid_1_416 & out_rimask_562; // @[RegisterRouter.scala:87:24] wire _out_T_5703 = out_f_rivalid_562; // @[RegisterRouter.scala:87:24] wire out_f_roready_562 = out_roready_1_416 & out_romask_562; // @[RegisterRouter.scala:87:24] wire _out_T_5704 = out_f_roready_562; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_562 = out_wivalid_1_416 & out_wimask_562; // @[RegisterRouter.scala:87:24] wire out_f_woready_562 = out_woready_1_416 & out_womask_562; // @[RegisterRouter.scala:87:24] wire _out_T_5705 = ~out_rimask_562; // @[RegisterRouter.scala:87:24] wire _out_T_5706 = ~out_wimask_562; // @[RegisterRouter.scala:87:24] wire _out_T_5707 = ~out_romask_562; // @[RegisterRouter.scala:87:24] wire _out_T_5708 = ~out_womask_562; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_475 = {hi_111, flags_0_go, _out_prepend_T_475}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5709 = out_prepend_475; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5710 = _out_T_5709; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_476 = _out_T_5710; // @[RegisterRouter.scala:87:24] wire out_rimask_563 = |_out_rimask_T_563; // @[RegisterRouter.scala:87:24] wire out_wimask_563 = &_out_wimask_T_563; // @[RegisterRouter.scala:87:24] wire out_romask_563 = |_out_romask_T_563; // @[RegisterRouter.scala:87:24] wire out_womask_563 = &_out_womask_T_563; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_563 = out_rivalid_1_417 & out_rimask_563; // @[RegisterRouter.scala:87:24] wire _out_T_5712 = out_f_rivalid_563; // @[RegisterRouter.scala:87:24] wire out_f_roready_563 = out_roready_1_417 & out_romask_563; // @[RegisterRouter.scala:87:24] wire _out_T_5713 = out_f_roready_563; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_563 = out_wivalid_1_417 & out_wimask_563; // @[RegisterRouter.scala:87:24] wire out_f_woready_563 = out_woready_1_417 & out_womask_563; // @[RegisterRouter.scala:87:24] wire _out_T_5714 = ~out_rimask_563; // @[RegisterRouter.scala:87:24] wire _out_T_5715 = ~out_wimask_563; // @[RegisterRouter.scala:87:24] wire _out_T_5716 = ~out_romask_563; // @[RegisterRouter.scala:87:24] wire _out_T_5717 = ~out_womask_563; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_476 = {hi_112, flags_0_go, _out_prepend_T_476}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5718 = out_prepend_476; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5719 = _out_T_5718; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_141 = _out_T_5719; // @[MuxLiteral.scala:49:48] wire out_rimask_564 = |_out_rimask_T_564; // @[RegisterRouter.scala:87:24] wire out_wimask_564 = &_out_wimask_T_564; // @[RegisterRouter.scala:87:24] wire out_romask_564 = |_out_romask_T_564; // @[RegisterRouter.scala:87:24] wire out_womask_564 = &_out_womask_T_564; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_564 = out_rivalid_1_418 & out_rimask_564; // @[RegisterRouter.scala:87:24] wire _out_T_5721 = out_f_rivalid_564; // @[RegisterRouter.scala:87:24] wire out_f_roready_564 = out_roready_1_418 & out_romask_564; // @[RegisterRouter.scala:87:24] wire _out_T_5722 = out_f_roready_564; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_564 = out_wivalid_1_418 & out_wimask_564; // @[RegisterRouter.scala:87:24] wire out_f_woready_564 = out_woready_1_418 & out_womask_564; // @[RegisterRouter.scala:87:24] wire _out_T_5723 = ~out_rimask_564; // @[RegisterRouter.scala:87:24] wire _out_T_5724 = ~out_wimask_564; // @[RegisterRouter.scala:87:24] wire _out_T_5725 = ~out_romask_564; // @[RegisterRouter.scala:87:24] wire _out_T_5726 = ~out_womask_564; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5728 = _out_T_5727; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_477 = _out_T_5728; // @[RegisterRouter.scala:87:24] wire out_rimask_565 = |_out_rimask_T_565; // @[RegisterRouter.scala:87:24] wire out_wimask_565 = &_out_wimask_T_565; // @[RegisterRouter.scala:87:24] wire out_romask_565 = |_out_romask_T_565; // @[RegisterRouter.scala:87:24] wire out_womask_565 = &_out_womask_T_565; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_565 = out_rivalid_1_419 & out_rimask_565; // @[RegisterRouter.scala:87:24] wire _out_T_5730 = out_f_rivalid_565; // @[RegisterRouter.scala:87:24] wire out_f_roready_565 = out_roready_1_419 & out_romask_565; // @[RegisterRouter.scala:87:24] wire _out_T_5731 = out_f_roready_565; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_565 = out_wivalid_1_419 & out_wimask_565; // @[RegisterRouter.scala:87:24] wire out_f_woready_565 = out_woready_1_419 & out_womask_565; // @[RegisterRouter.scala:87:24] wire _out_T_5732 = ~out_rimask_565; // @[RegisterRouter.scala:87:24] wire _out_T_5733 = ~out_wimask_565; // @[RegisterRouter.scala:87:24] wire _out_T_5734 = ~out_romask_565; // @[RegisterRouter.scala:87:24] wire _out_T_5735 = ~out_womask_565; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_477 = {hi_778, flags_0_go, _out_prepend_T_477}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5736 = out_prepend_477; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5737 = _out_T_5736; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_478 = _out_T_5737; // @[RegisterRouter.scala:87:24] wire out_rimask_566 = |_out_rimask_T_566; // @[RegisterRouter.scala:87:24] wire out_wimask_566 = &_out_wimask_T_566; // @[RegisterRouter.scala:87:24] wire out_romask_566 = |_out_romask_T_566; // @[RegisterRouter.scala:87:24] wire out_womask_566 = &_out_womask_T_566; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_566 = out_rivalid_1_420 & out_rimask_566; // @[RegisterRouter.scala:87:24] wire _out_T_5739 = out_f_rivalid_566; // @[RegisterRouter.scala:87:24] wire out_f_roready_566 = out_roready_1_420 & out_romask_566; // @[RegisterRouter.scala:87:24] wire _out_T_5740 = out_f_roready_566; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_566 = out_wivalid_1_420 & out_wimask_566; // @[RegisterRouter.scala:87:24] wire out_f_woready_566 = out_woready_1_420 & out_womask_566; // @[RegisterRouter.scala:87:24] wire _out_T_5741 = ~out_rimask_566; // @[RegisterRouter.scala:87:24] wire _out_T_5742 = ~out_wimask_566; // @[RegisterRouter.scala:87:24] wire _out_T_5743 = ~out_romask_566; // @[RegisterRouter.scala:87:24] wire _out_T_5744 = ~out_womask_566; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_478 = {hi_779, flags_0_go, _out_prepend_T_478}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5745 = out_prepend_478; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5746 = _out_T_5745; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_479 = _out_T_5746; // @[RegisterRouter.scala:87:24] wire out_rimask_567 = |_out_rimask_T_567; // @[RegisterRouter.scala:87:24] wire out_wimask_567 = &_out_wimask_T_567; // @[RegisterRouter.scala:87:24] wire out_romask_567 = |_out_romask_T_567; // @[RegisterRouter.scala:87:24] wire out_womask_567 = &_out_womask_T_567; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_567 = out_rivalid_1_421 & out_rimask_567; // @[RegisterRouter.scala:87:24] wire _out_T_5748 = out_f_rivalid_567; // @[RegisterRouter.scala:87:24] wire out_f_roready_567 = out_roready_1_421 & out_romask_567; // @[RegisterRouter.scala:87:24] wire _out_T_5749 = out_f_roready_567; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_567 = out_wivalid_1_421 & out_wimask_567; // @[RegisterRouter.scala:87:24] wire out_f_woready_567 = out_woready_1_421 & out_womask_567; // @[RegisterRouter.scala:87:24] wire _out_T_5750 = ~out_rimask_567; // @[RegisterRouter.scala:87:24] wire _out_T_5751 = ~out_wimask_567; // @[RegisterRouter.scala:87:24] wire _out_T_5752 = ~out_romask_567; // @[RegisterRouter.scala:87:24] wire _out_T_5753 = ~out_womask_567; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_479 = {hi_780, flags_0_go, _out_prepend_T_479}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5754 = out_prepend_479; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5755 = _out_T_5754; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_480 = _out_T_5755; // @[RegisterRouter.scala:87:24] wire out_rimask_568 = |_out_rimask_T_568; // @[RegisterRouter.scala:87:24] wire out_wimask_568 = &_out_wimask_T_568; // @[RegisterRouter.scala:87:24] wire out_romask_568 = |_out_romask_T_568; // @[RegisterRouter.scala:87:24] wire out_womask_568 = &_out_womask_T_568; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_568 = out_rivalid_1_422 & out_rimask_568; // @[RegisterRouter.scala:87:24] wire _out_T_5757 = out_f_rivalid_568; // @[RegisterRouter.scala:87:24] wire out_f_roready_568 = out_roready_1_422 & out_romask_568; // @[RegisterRouter.scala:87:24] wire _out_T_5758 = out_f_roready_568; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_568 = out_wivalid_1_422 & out_wimask_568; // @[RegisterRouter.scala:87:24] wire out_f_woready_568 = out_woready_1_422 & out_womask_568; // @[RegisterRouter.scala:87:24] wire _out_T_5759 = ~out_rimask_568; // @[RegisterRouter.scala:87:24] wire _out_T_5760 = ~out_wimask_568; // @[RegisterRouter.scala:87:24] wire _out_T_5761 = ~out_romask_568; // @[RegisterRouter.scala:87:24] wire _out_T_5762 = ~out_womask_568; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_480 = {hi_781, flags_0_go, _out_prepend_T_480}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5763 = out_prepend_480; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5764 = _out_T_5763; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_481 = _out_T_5764; // @[RegisterRouter.scala:87:24] wire out_rimask_569 = |_out_rimask_T_569; // @[RegisterRouter.scala:87:24] wire out_wimask_569 = &_out_wimask_T_569; // @[RegisterRouter.scala:87:24] wire out_romask_569 = |_out_romask_T_569; // @[RegisterRouter.scala:87:24] wire out_womask_569 = &_out_womask_T_569; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_569 = out_rivalid_1_423 & out_rimask_569; // @[RegisterRouter.scala:87:24] wire _out_T_5766 = out_f_rivalid_569; // @[RegisterRouter.scala:87:24] wire out_f_roready_569 = out_roready_1_423 & out_romask_569; // @[RegisterRouter.scala:87:24] wire _out_T_5767 = out_f_roready_569; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_569 = out_wivalid_1_423 & out_wimask_569; // @[RegisterRouter.scala:87:24] wire out_f_woready_569 = out_woready_1_423 & out_womask_569; // @[RegisterRouter.scala:87:24] wire _out_T_5768 = ~out_rimask_569; // @[RegisterRouter.scala:87:24] wire _out_T_5769 = ~out_wimask_569; // @[RegisterRouter.scala:87:24] wire _out_T_5770 = ~out_romask_569; // @[RegisterRouter.scala:87:24] wire _out_T_5771 = ~out_womask_569; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_481 = {hi_782, flags_0_go, _out_prepend_T_481}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5772 = out_prepend_481; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5773 = _out_T_5772; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_482 = _out_T_5773; // @[RegisterRouter.scala:87:24] wire out_rimask_570 = |_out_rimask_T_570; // @[RegisterRouter.scala:87:24] wire out_wimask_570 = &_out_wimask_T_570; // @[RegisterRouter.scala:87:24] wire out_romask_570 = |_out_romask_T_570; // @[RegisterRouter.scala:87:24] wire out_womask_570 = &_out_womask_T_570; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_570 = out_rivalid_1_424 & out_rimask_570; // @[RegisterRouter.scala:87:24] wire _out_T_5775 = out_f_rivalid_570; // @[RegisterRouter.scala:87:24] wire out_f_roready_570 = out_roready_1_424 & out_romask_570; // @[RegisterRouter.scala:87:24] wire _out_T_5776 = out_f_roready_570; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_570 = out_wivalid_1_424 & out_wimask_570; // @[RegisterRouter.scala:87:24] wire out_f_woready_570 = out_woready_1_424 & out_womask_570; // @[RegisterRouter.scala:87:24] wire _out_T_5777 = ~out_rimask_570; // @[RegisterRouter.scala:87:24] wire _out_T_5778 = ~out_wimask_570; // @[RegisterRouter.scala:87:24] wire _out_T_5779 = ~out_romask_570; // @[RegisterRouter.scala:87:24] wire _out_T_5780 = ~out_womask_570; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_482 = {hi_783, flags_0_go, _out_prepend_T_482}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5781 = out_prepend_482; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5782 = _out_T_5781; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_483 = _out_T_5782; // @[RegisterRouter.scala:87:24] wire out_rimask_571 = |_out_rimask_T_571; // @[RegisterRouter.scala:87:24] wire out_wimask_571 = &_out_wimask_T_571; // @[RegisterRouter.scala:87:24] wire out_romask_571 = |_out_romask_T_571; // @[RegisterRouter.scala:87:24] wire out_womask_571 = &_out_womask_T_571; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_571 = out_rivalid_1_425 & out_rimask_571; // @[RegisterRouter.scala:87:24] wire _out_T_5784 = out_f_rivalid_571; // @[RegisterRouter.scala:87:24] wire out_f_roready_571 = out_roready_1_425 & out_romask_571; // @[RegisterRouter.scala:87:24] wire _out_T_5785 = out_f_roready_571; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_571 = out_wivalid_1_425 & out_wimask_571; // @[RegisterRouter.scala:87:24] wire out_f_woready_571 = out_woready_1_425 & out_womask_571; // @[RegisterRouter.scala:87:24] wire _out_T_5786 = ~out_rimask_571; // @[RegisterRouter.scala:87:24] wire _out_T_5787 = ~out_wimask_571; // @[RegisterRouter.scala:87:24] wire _out_T_5788 = ~out_romask_571; // @[RegisterRouter.scala:87:24] wire _out_T_5789 = ~out_womask_571; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_483 = {hi_784, flags_0_go, _out_prepend_T_483}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5790 = out_prepend_483; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5791 = _out_T_5790; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_225 = _out_T_5791; // @[MuxLiteral.scala:49:48] wire out_rimask_572 = |_out_rimask_T_572; // @[RegisterRouter.scala:87:24] wire out_wimask_572 = &_out_wimask_T_572; // @[RegisterRouter.scala:87:24] wire out_romask_572 = |_out_romask_T_572; // @[RegisterRouter.scala:87:24] wire out_womask_572 = &_out_womask_T_572; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_572 = out_rivalid_1_426 & out_rimask_572; // @[RegisterRouter.scala:87:24] wire _out_T_5793 = out_f_rivalid_572; // @[RegisterRouter.scala:87:24] wire out_f_roready_572 = out_roready_1_426 & out_romask_572; // @[RegisterRouter.scala:87:24] wire _out_T_5794 = out_f_roready_572; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_572 = out_wivalid_1_426 & out_wimask_572; // @[RegisterRouter.scala:87:24] wire out_f_woready_572 = out_woready_1_426 & out_womask_572; // @[RegisterRouter.scala:87:24] wire _out_T_5795 = ~out_rimask_572; // @[RegisterRouter.scala:87:24] wire _out_T_5796 = ~out_wimask_572; // @[RegisterRouter.scala:87:24] wire _out_T_5797 = ~out_romask_572; // @[RegisterRouter.scala:87:24] wire _out_T_5798 = ~out_womask_572; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5800 = _out_T_5799; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_484 = _out_T_5800; // @[RegisterRouter.scala:87:24] wire out_rimask_573 = |_out_rimask_T_573; // @[RegisterRouter.scala:87:24] wire out_wimask_573 = &_out_wimask_T_573; // @[RegisterRouter.scala:87:24] wire out_romask_573 = |_out_romask_T_573; // @[RegisterRouter.scala:87:24] wire out_womask_573 = &_out_womask_T_573; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_573 = out_rivalid_1_427 & out_rimask_573; // @[RegisterRouter.scala:87:24] wire _out_T_5802 = out_f_rivalid_573; // @[RegisterRouter.scala:87:24] wire out_f_roready_573 = out_roready_1_427 & out_romask_573; // @[RegisterRouter.scala:87:24] wire _out_T_5803 = out_f_roready_573; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_573 = out_wivalid_1_427 & out_wimask_573; // @[RegisterRouter.scala:87:24] wire out_f_woready_573 = out_woready_1_427 & out_womask_573; // @[RegisterRouter.scala:87:24] wire _out_T_5804 = ~out_rimask_573; // @[RegisterRouter.scala:87:24] wire _out_T_5805 = ~out_wimask_573; // @[RegisterRouter.scala:87:24] wire _out_T_5806 = ~out_romask_573; // @[RegisterRouter.scala:87:24] wire _out_T_5807 = ~out_womask_573; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_484 = {hi_522, flags_0_go, _out_prepend_T_484}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5808 = out_prepend_484; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5809 = _out_T_5808; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_485 = _out_T_5809; // @[RegisterRouter.scala:87:24] wire out_rimask_574 = |_out_rimask_T_574; // @[RegisterRouter.scala:87:24] wire out_wimask_574 = &_out_wimask_T_574; // @[RegisterRouter.scala:87:24] wire out_romask_574 = |_out_romask_T_574; // @[RegisterRouter.scala:87:24] wire out_womask_574 = &_out_womask_T_574; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_574 = out_rivalid_1_428 & out_rimask_574; // @[RegisterRouter.scala:87:24] wire _out_T_5811 = out_f_rivalid_574; // @[RegisterRouter.scala:87:24] wire out_f_roready_574 = out_roready_1_428 & out_romask_574; // @[RegisterRouter.scala:87:24] wire _out_T_5812 = out_f_roready_574; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_574 = out_wivalid_1_428 & out_wimask_574; // @[RegisterRouter.scala:87:24] wire out_f_woready_574 = out_woready_1_428 & out_womask_574; // @[RegisterRouter.scala:87:24] wire _out_T_5813 = ~out_rimask_574; // @[RegisterRouter.scala:87:24] wire _out_T_5814 = ~out_wimask_574; // @[RegisterRouter.scala:87:24] wire _out_T_5815 = ~out_romask_574; // @[RegisterRouter.scala:87:24] wire _out_T_5816 = ~out_womask_574; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_485 = {hi_523, flags_0_go, _out_prepend_T_485}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5817 = out_prepend_485; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5818 = _out_T_5817; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_486 = _out_T_5818; // @[RegisterRouter.scala:87:24] wire out_rimask_575 = |_out_rimask_T_575; // @[RegisterRouter.scala:87:24] wire out_wimask_575 = &_out_wimask_T_575; // @[RegisterRouter.scala:87:24] wire out_romask_575 = |_out_romask_T_575; // @[RegisterRouter.scala:87:24] wire out_womask_575 = &_out_womask_T_575; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_575 = out_rivalid_1_429 & out_rimask_575; // @[RegisterRouter.scala:87:24] wire _out_T_5820 = out_f_rivalid_575; // @[RegisterRouter.scala:87:24] wire out_f_roready_575 = out_roready_1_429 & out_romask_575; // @[RegisterRouter.scala:87:24] wire _out_T_5821 = out_f_roready_575; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_575 = out_wivalid_1_429 & out_wimask_575; // @[RegisterRouter.scala:87:24] wire out_f_woready_575 = out_woready_1_429 & out_womask_575; // @[RegisterRouter.scala:87:24] wire _out_T_5822 = ~out_rimask_575; // @[RegisterRouter.scala:87:24] wire _out_T_5823 = ~out_wimask_575; // @[RegisterRouter.scala:87:24] wire _out_T_5824 = ~out_romask_575; // @[RegisterRouter.scala:87:24] wire _out_T_5825 = ~out_womask_575; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_486 = {hi_524, flags_0_go, _out_prepend_T_486}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5826 = out_prepend_486; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5827 = _out_T_5826; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_487 = _out_T_5827; // @[RegisterRouter.scala:87:24] wire out_rimask_576 = |_out_rimask_T_576; // @[RegisterRouter.scala:87:24] wire out_wimask_576 = &_out_wimask_T_576; // @[RegisterRouter.scala:87:24] wire out_romask_576 = |_out_romask_T_576; // @[RegisterRouter.scala:87:24] wire out_womask_576 = &_out_womask_T_576; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_576 = out_rivalid_1_430 & out_rimask_576; // @[RegisterRouter.scala:87:24] wire _out_T_5829 = out_f_rivalid_576; // @[RegisterRouter.scala:87:24] wire out_f_roready_576 = out_roready_1_430 & out_romask_576; // @[RegisterRouter.scala:87:24] wire _out_T_5830 = out_f_roready_576; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_576 = out_wivalid_1_430 & out_wimask_576; // @[RegisterRouter.scala:87:24] wire out_f_woready_576 = out_woready_1_430 & out_womask_576; // @[RegisterRouter.scala:87:24] wire _out_T_5831 = ~out_rimask_576; // @[RegisterRouter.scala:87:24] wire _out_T_5832 = ~out_wimask_576; // @[RegisterRouter.scala:87:24] wire _out_T_5833 = ~out_romask_576; // @[RegisterRouter.scala:87:24] wire _out_T_5834 = ~out_womask_576; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_487 = {hi_525, flags_0_go, _out_prepend_T_487}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5835 = out_prepend_487; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5836 = _out_T_5835; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_488 = _out_T_5836; // @[RegisterRouter.scala:87:24] wire out_rimask_577 = |_out_rimask_T_577; // @[RegisterRouter.scala:87:24] wire out_wimask_577 = &_out_wimask_T_577; // @[RegisterRouter.scala:87:24] wire out_romask_577 = |_out_romask_T_577; // @[RegisterRouter.scala:87:24] wire out_womask_577 = &_out_womask_T_577; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_577 = out_rivalid_1_431 & out_rimask_577; // @[RegisterRouter.scala:87:24] wire _out_T_5838 = out_f_rivalid_577; // @[RegisterRouter.scala:87:24] wire out_f_roready_577 = out_roready_1_431 & out_romask_577; // @[RegisterRouter.scala:87:24] wire _out_T_5839 = out_f_roready_577; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_577 = out_wivalid_1_431 & out_wimask_577; // @[RegisterRouter.scala:87:24] wire out_f_woready_577 = out_woready_1_431 & out_womask_577; // @[RegisterRouter.scala:87:24] wire _out_T_5840 = ~out_rimask_577; // @[RegisterRouter.scala:87:24] wire _out_T_5841 = ~out_wimask_577; // @[RegisterRouter.scala:87:24] wire _out_T_5842 = ~out_romask_577; // @[RegisterRouter.scala:87:24] wire _out_T_5843 = ~out_womask_577; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_488 = {hi_526, flags_0_go, _out_prepend_T_488}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5844 = out_prepend_488; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5845 = _out_T_5844; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_489 = _out_T_5845; // @[RegisterRouter.scala:87:24] wire out_rimask_578 = |_out_rimask_T_578; // @[RegisterRouter.scala:87:24] wire out_wimask_578 = &_out_wimask_T_578; // @[RegisterRouter.scala:87:24] wire out_romask_578 = |_out_romask_T_578; // @[RegisterRouter.scala:87:24] wire out_womask_578 = &_out_womask_T_578; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_578 = out_rivalid_1_432 & out_rimask_578; // @[RegisterRouter.scala:87:24] wire _out_T_5847 = out_f_rivalid_578; // @[RegisterRouter.scala:87:24] wire out_f_roready_578 = out_roready_1_432 & out_romask_578; // @[RegisterRouter.scala:87:24] wire _out_T_5848 = out_f_roready_578; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_578 = out_wivalid_1_432 & out_wimask_578; // @[RegisterRouter.scala:87:24] wire out_f_woready_578 = out_woready_1_432 & out_womask_578; // @[RegisterRouter.scala:87:24] wire _out_T_5849 = ~out_rimask_578; // @[RegisterRouter.scala:87:24] wire _out_T_5850 = ~out_wimask_578; // @[RegisterRouter.scala:87:24] wire _out_T_5851 = ~out_romask_578; // @[RegisterRouter.scala:87:24] wire _out_T_5852 = ~out_womask_578; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_489 = {hi_527, flags_0_go, _out_prepend_T_489}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5853 = out_prepend_489; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5854 = _out_T_5853; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_490 = _out_T_5854; // @[RegisterRouter.scala:87:24] wire out_rimask_579 = |_out_rimask_T_579; // @[RegisterRouter.scala:87:24] wire out_wimask_579 = &_out_wimask_T_579; // @[RegisterRouter.scala:87:24] wire out_romask_579 = |_out_romask_T_579; // @[RegisterRouter.scala:87:24] wire out_womask_579 = &_out_womask_T_579; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_579 = out_rivalid_1_433 & out_rimask_579; // @[RegisterRouter.scala:87:24] wire _out_T_5856 = out_f_rivalid_579; // @[RegisterRouter.scala:87:24] wire out_f_roready_579 = out_roready_1_433 & out_romask_579; // @[RegisterRouter.scala:87:24] wire _out_T_5857 = out_f_roready_579; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_579 = out_wivalid_1_433 & out_wimask_579; // @[RegisterRouter.scala:87:24] wire out_f_woready_579 = out_woready_1_433 & out_womask_579; // @[RegisterRouter.scala:87:24] wire _out_T_5858 = ~out_rimask_579; // @[RegisterRouter.scala:87:24] wire _out_T_5859 = ~out_wimask_579; // @[RegisterRouter.scala:87:24] wire _out_T_5860 = ~out_romask_579; // @[RegisterRouter.scala:87:24] wire _out_T_5861 = ~out_womask_579; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_490 = {hi_528, flags_0_go, _out_prepend_T_490}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5862 = out_prepend_490; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5863 = _out_T_5862; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_193 = _out_T_5863; // @[MuxLiteral.scala:49:48] wire out_rimask_580 = |_out_rimask_T_580; // @[RegisterRouter.scala:87:24] wire out_wimask_580 = &_out_wimask_T_580; // @[RegisterRouter.scala:87:24] wire out_romask_580 = |_out_romask_T_580; // @[RegisterRouter.scala:87:24] wire out_womask_580 = &_out_womask_T_580; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_580 = out_rivalid_1_434 & out_rimask_580; // @[RegisterRouter.scala:87:24] wire _out_T_5865 = out_f_rivalid_580; // @[RegisterRouter.scala:87:24] wire out_f_roready_580 = out_roready_1_434 & out_romask_580; // @[RegisterRouter.scala:87:24] wire _out_T_5866 = out_f_roready_580; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_580 = out_wivalid_1_434 & out_wimask_580; // @[RegisterRouter.scala:87:24] wire out_f_woready_580 = out_woready_1_434 & out_womask_580; // @[RegisterRouter.scala:87:24] wire _out_T_5867 = ~out_rimask_580; // @[RegisterRouter.scala:87:24] wire _out_T_5868 = ~out_wimask_580; // @[RegisterRouter.scala:87:24] wire _out_T_5869 = ~out_romask_580; // @[RegisterRouter.scala:87:24] wire _out_T_5870 = ~out_womask_580; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5872 = _out_T_5871; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_491 = _out_T_5872; // @[RegisterRouter.scala:87:24] wire out_rimask_581 = |_out_rimask_T_581; // @[RegisterRouter.scala:87:24] wire out_wimask_581 = &_out_wimask_T_581; // @[RegisterRouter.scala:87:24] wire out_romask_581 = |_out_romask_T_581; // @[RegisterRouter.scala:87:24] wire out_womask_581 = &_out_womask_T_581; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_581 = out_rivalid_1_435 & out_rimask_581; // @[RegisterRouter.scala:87:24] wire _out_T_5874 = out_f_rivalid_581; // @[RegisterRouter.scala:87:24] wire out_f_roready_581 = out_roready_1_435 & out_romask_581; // @[RegisterRouter.scala:87:24] wire _out_T_5875 = out_f_roready_581; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_581 = out_wivalid_1_435 & out_wimask_581; // @[RegisterRouter.scala:87:24] wire out_f_woready_581 = out_woready_1_435 & out_womask_581; // @[RegisterRouter.scala:87:24] wire _out_T_5876 = ~out_rimask_581; // @[RegisterRouter.scala:87:24] wire _out_T_5877 = ~out_wimask_581; // @[RegisterRouter.scala:87:24] wire _out_T_5878 = ~out_romask_581; // @[RegisterRouter.scala:87:24] wire _out_T_5879 = ~out_womask_581; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_491 = {hi_674, flags_0_go, _out_prepend_T_491}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5880 = out_prepend_491; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5881 = _out_T_5880; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_492 = _out_T_5881; // @[RegisterRouter.scala:87:24] wire out_rimask_582 = |_out_rimask_T_582; // @[RegisterRouter.scala:87:24] wire out_wimask_582 = &_out_wimask_T_582; // @[RegisterRouter.scala:87:24] wire out_romask_582 = |_out_romask_T_582; // @[RegisterRouter.scala:87:24] wire out_womask_582 = &_out_womask_T_582; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_582 = out_rivalid_1_436 & out_rimask_582; // @[RegisterRouter.scala:87:24] wire _out_T_5883 = out_f_rivalid_582; // @[RegisterRouter.scala:87:24] wire out_f_roready_582 = out_roready_1_436 & out_romask_582; // @[RegisterRouter.scala:87:24] wire _out_T_5884 = out_f_roready_582; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_582 = out_wivalid_1_436 & out_wimask_582; // @[RegisterRouter.scala:87:24] wire out_f_woready_582 = out_woready_1_436 & out_womask_582; // @[RegisterRouter.scala:87:24] wire _out_T_5885 = ~out_rimask_582; // @[RegisterRouter.scala:87:24] wire _out_T_5886 = ~out_wimask_582; // @[RegisterRouter.scala:87:24] wire _out_T_5887 = ~out_romask_582; // @[RegisterRouter.scala:87:24] wire _out_T_5888 = ~out_womask_582; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_492 = {hi_675, flags_0_go, _out_prepend_T_492}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5889 = out_prepend_492; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5890 = _out_T_5889; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_493 = _out_T_5890; // @[RegisterRouter.scala:87:24] wire out_rimask_583 = |_out_rimask_T_583; // @[RegisterRouter.scala:87:24] wire out_wimask_583 = &_out_wimask_T_583; // @[RegisterRouter.scala:87:24] wire out_romask_583 = |_out_romask_T_583; // @[RegisterRouter.scala:87:24] wire out_womask_583 = &_out_womask_T_583; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_583 = out_rivalid_1_437 & out_rimask_583; // @[RegisterRouter.scala:87:24] wire _out_T_5892 = out_f_rivalid_583; // @[RegisterRouter.scala:87:24] wire out_f_roready_583 = out_roready_1_437 & out_romask_583; // @[RegisterRouter.scala:87:24] wire _out_T_5893 = out_f_roready_583; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_583 = out_wivalid_1_437 & out_wimask_583; // @[RegisterRouter.scala:87:24] wire out_f_woready_583 = out_woready_1_437 & out_womask_583; // @[RegisterRouter.scala:87:24] wire _out_T_5894 = ~out_rimask_583; // @[RegisterRouter.scala:87:24] wire _out_T_5895 = ~out_wimask_583; // @[RegisterRouter.scala:87:24] wire _out_T_5896 = ~out_romask_583; // @[RegisterRouter.scala:87:24] wire _out_T_5897 = ~out_womask_583; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_493 = {hi_676, flags_0_go, _out_prepend_T_493}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5898 = out_prepend_493; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5899 = _out_T_5898; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_494 = _out_T_5899; // @[RegisterRouter.scala:87:24] wire out_rimask_584 = |_out_rimask_T_584; // @[RegisterRouter.scala:87:24] wire out_wimask_584 = &_out_wimask_T_584; // @[RegisterRouter.scala:87:24] wire out_romask_584 = |_out_romask_T_584; // @[RegisterRouter.scala:87:24] wire out_womask_584 = &_out_womask_T_584; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_584 = out_rivalid_1_438 & out_rimask_584; // @[RegisterRouter.scala:87:24] wire _out_T_5901 = out_f_rivalid_584; // @[RegisterRouter.scala:87:24] wire out_f_roready_584 = out_roready_1_438 & out_romask_584; // @[RegisterRouter.scala:87:24] wire _out_T_5902 = out_f_roready_584; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_584 = out_wivalid_1_438 & out_wimask_584; // @[RegisterRouter.scala:87:24] wire out_f_woready_584 = out_woready_1_438 & out_womask_584; // @[RegisterRouter.scala:87:24] wire _out_T_5903 = ~out_rimask_584; // @[RegisterRouter.scala:87:24] wire _out_T_5904 = ~out_wimask_584; // @[RegisterRouter.scala:87:24] wire _out_T_5905 = ~out_romask_584; // @[RegisterRouter.scala:87:24] wire _out_T_5906 = ~out_womask_584; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_494 = {hi_677, flags_0_go, _out_prepend_T_494}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5907 = out_prepend_494; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5908 = _out_T_5907; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_495 = _out_T_5908; // @[RegisterRouter.scala:87:24] wire out_rimask_585 = |_out_rimask_T_585; // @[RegisterRouter.scala:87:24] wire out_wimask_585 = &_out_wimask_T_585; // @[RegisterRouter.scala:87:24] wire out_romask_585 = |_out_romask_T_585; // @[RegisterRouter.scala:87:24] wire out_womask_585 = &_out_womask_T_585; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_585 = out_rivalid_1_439 & out_rimask_585; // @[RegisterRouter.scala:87:24] wire _out_T_5910 = out_f_rivalid_585; // @[RegisterRouter.scala:87:24] wire out_f_roready_585 = out_roready_1_439 & out_romask_585; // @[RegisterRouter.scala:87:24] wire _out_T_5911 = out_f_roready_585; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_585 = out_wivalid_1_439 & out_wimask_585; // @[RegisterRouter.scala:87:24] wire out_f_woready_585 = out_woready_1_439 & out_womask_585; // @[RegisterRouter.scala:87:24] wire _out_T_5912 = ~out_rimask_585; // @[RegisterRouter.scala:87:24] wire _out_T_5913 = ~out_wimask_585; // @[RegisterRouter.scala:87:24] wire _out_T_5914 = ~out_romask_585; // @[RegisterRouter.scala:87:24] wire _out_T_5915 = ~out_womask_585; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_495 = {hi_678, flags_0_go, _out_prepend_T_495}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5916 = out_prepend_495; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5917 = _out_T_5916; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_496 = _out_T_5917; // @[RegisterRouter.scala:87:24] wire out_rimask_586 = |_out_rimask_T_586; // @[RegisterRouter.scala:87:24] wire out_wimask_586 = &_out_wimask_T_586; // @[RegisterRouter.scala:87:24] wire out_romask_586 = |_out_romask_T_586; // @[RegisterRouter.scala:87:24] wire out_womask_586 = &_out_womask_T_586; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_586 = out_rivalid_1_440 & out_rimask_586; // @[RegisterRouter.scala:87:24] wire _out_T_5919 = out_f_rivalid_586; // @[RegisterRouter.scala:87:24] wire out_f_roready_586 = out_roready_1_440 & out_romask_586; // @[RegisterRouter.scala:87:24] wire _out_T_5920 = out_f_roready_586; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_586 = out_wivalid_1_440 & out_wimask_586; // @[RegisterRouter.scala:87:24] wire out_f_woready_586 = out_woready_1_440 & out_womask_586; // @[RegisterRouter.scala:87:24] wire _out_T_5921 = ~out_rimask_586; // @[RegisterRouter.scala:87:24] wire _out_T_5922 = ~out_wimask_586; // @[RegisterRouter.scala:87:24] wire _out_T_5923 = ~out_romask_586; // @[RegisterRouter.scala:87:24] wire _out_T_5924 = ~out_womask_586; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_496 = {hi_679, flags_0_go, _out_prepend_T_496}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5925 = out_prepend_496; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5926 = _out_T_5925; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_497 = _out_T_5926; // @[RegisterRouter.scala:87:24] wire out_rimask_587 = |_out_rimask_T_587; // @[RegisterRouter.scala:87:24] wire out_wimask_587 = &_out_wimask_T_587; // @[RegisterRouter.scala:87:24] wire out_romask_587 = |_out_romask_T_587; // @[RegisterRouter.scala:87:24] wire out_womask_587 = &_out_womask_T_587; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_587 = out_rivalid_1_441 & out_rimask_587; // @[RegisterRouter.scala:87:24] wire _out_T_5928 = out_f_rivalid_587; // @[RegisterRouter.scala:87:24] wire out_f_roready_587 = out_roready_1_441 & out_romask_587; // @[RegisterRouter.scala:87:24] wire _out_T_5929 = out_f_roready_587; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_587 = out_wivalid_1_441 & out_wimask_587; // @[RegisterRouter.scala:87:24] wire out_f_woready_587 = out_woready_1_441 & out_womask_587; // @[RegisterRouter.scala:87:24] wire _out_T_5930 = ~out_rimask_587; // @[RegisterRouter.scala:87:24] wire _out_T_5931 = ~out_wimask_587; // @[RegisterRouter.scala:87:24] wire _out_T_5932 = ~out_romask_587; // @[RegisterRouter.scala:87:24] wire _out_T_5933 = ~out_womask_587; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_497 = {hi_680, flags_0_go, _out_prepend_T_497}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5934 = out_prepend_497; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5935 = _out_T_5934; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_212 = _out_T_5935; // @[MuxLiteral.scala:49:48] wire [31:0] _out_rimask_T_588 = out_frontMask_1[31:0]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_wimask_T_588 = out_frontMask_1[31:0]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_rimask_T_843 = out_frontMask_1[31:0]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_wimask_T_843 = out_frontMask_1[31:0]; // @[RegisterRouter.scala:87:24] wire out_rimask_588 = |_out_rimask_T_588; // @[RegisterRouter.scala:87:24] wire out_wimask_588 = &_out_wimask_T_588; // @[RegisterRouter.scala:87:24] wire [31:0] _out_romask_T_588 = out_backMask_1[31:0]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_womask_T_588 = out_backMask_1[31:0]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_romask_T_843 = out_backMask_1[31:0]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_womask_T_843 = out_backMask_1[31:0]; // @[RegisterRouter.scala:87:24] wire out_romask_588 = |_out_romask_T_588; // @[RegisterRouter.scala:87:24] wire out_womask_588 = &_out_womask_T_588; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_588 = out_rivalid_1_442 & out_rimask_588; // @[RegisterRouter.scala:87:24] wire _out_T_5937 = out_f_rivalid_588; // @[RegisterRouter.scala:87:24] wire out_f_roready_588 = out_roready_1_442 & out_romask_588; // @[RegisterRouter.scala:87:24] wire _out_T_5938 = out_f_roready_588; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_588 = out_wivalid_1_442 & out_wimask_588; // @[RegisterRouter.scala:87:24] wire out_f_woready_588 = out_woready_1_442 & out_womask_588; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5936 = out_front_1_bits_data[31:0]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8279 = out_front_1_bits_data[31:0]; // @[RegisterRouter.scala:87:24] wire _out_T_5939 = ~out_rimask_588; // @[RegisterRouter.scala:87:24] wire _out_T_5940 = ~out_wimask_588; // @[RegisterRouter.scala:87:24] wire _out_T_5941 = ~out_romask_588; // @[RegisterRouter.scala:87:24] wire _out_T_5942 = ~out_womask_588; // @[RegisterRouter.scala:87:24] wire out_rimask_589 = |_out_rimask_T_589; // @[RegisterRouter.scala:87:24] wire out_wimask_589 = &_out_wimask_T_589; // @[RegisterRouter.scala:87:24] wire out_romask_589 = |_out_romask_T_589; // @[RegisterRouter.scala:87:24] wire out_womask_589 = &_out_womask_T_589; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_589 = out_rivalid_1_443 & out_rimask_589; // @[RegisterRouter.scala:87:24] wire _out_T_5946 = out_f_rivalid_589; // @[RegisterRouter.scala:87:24] wire out_f_roready_589 = out_roready_1_443 & out_romask_589; // @[RegisterRouter.scala:87:24] wire _out_T_5947 = out_f_roready_589; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_589 = out_wivalid_1_443 & out_wimask_589; // @[RegisterRouter.scala:87:24] wire _out_T_5948 = out_f_wivalid_589; // @[RegisterRouter.scala:87:24] wire out_f_woready_589 = out_woready_1_443 & out_womask_589; // @[RegisterRouter.scala:87:24] wire _out_T_5949 = out_f_woready_589; // @[RegisterRouter.scala:87:24] wire _out_T_5950 = ~out_rimask_589; // @[RegisterRouter.scala:87:24] wire _out_T_5951 = ~out_wimask_589; // @[RegisterRouter.scala:87:24] wire _out_T_5952 = ~out_romask_589; // @[RegisterRouter.scala:87:24] wire _out_T_5953 = ~out_womask_589; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5955 = _out_T_5954; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_498 = _out_T_5955; // @[RegisterRouter.scala:87:24] wire out_rimask_590 = |_out_rimask_T_590; // @[RegisterRouter.scala:87:24] wire out_wimask_590 = &_out_wimask_T_590; // @[RegisterRouter.scala:87:24] wire out_romask_590 = |_out_romask_T_590; // @[RegisterRouter.scala:87:24] wire out_womask_590 = &_out_womask_T_590; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_590 = out_rivalid_1_444 & out_rimask_590; // @[RegisterRouter.scala:87:24] wire _out_T_5957 = out_f_rivalid_590; // @[RegisterRouter.scala:87:24] wire out_f_roready_590 = out_roready_1_444 & out_romask_590; // @[RegisterRouter.scala:87:24] wire _out_T_5958 = out_f_roready_590; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_590 = out_wivalid_1_444 & out_wimask_590; // @[RegisterRouter.scala:87:24] wire _out_T_5959 = out_f_wivalid_590; // @[RegisterRouter.scala:87:24] wire out_f_woready_590 = out_woready_1_444 & out_womask_590; // @[RegisterRouter.scala:87:24] wire _out_T_5960 = out_f_woready_590; // @[RegisterRouter.scala:87:24] wire _out_T_5961 = ~out_rimask_590; // @[RegisterRouter.scala:87:24] wire _out_T_5962 = ~out_wimask_590; // @[RegisterRouter.scala:87:24] wire _out_T_5963 = ~out_romask_590; // @[RegisterRouter.scala:87:24] wire _out_T_5964 = ~out_womask_590; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_498 = {programBufferMem_41, _out_prepend_T_498}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5965 = out_prepend_498; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5966 = _out_T_5965; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_499 = _out_T_5966; // @[RegisterRouter.scala:87:24] wire out_rimask_591 = |_out_rimask_T_591; // @[RegisterRouter.scala:87:24] wire out_wimask_591 = &_out_wimask_T_591; // @[RegisterRouter.scala:87:24] wire out_romask_591 = |_out_romask_T_591; // @[RegisterRouter.scala:87:24] wire out_womask_591 = &_out_womask_T_591; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_591 = out_rivalid_1_445 & out_rimask_591; // @[RegisterRouter.scala:87:24] wire _out_T_5968 = out_f_rivalid_591; // @[RegisterRouter.scala:87:24] wire out_f_roready_591 = out_roready_1_445 & out_romask_591; // @[RegisterRouter.scala:87:24] wire _out_T_5969 = out_f_roready_591; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_591 = out_wivalid_1_445 & out_wimask_591; // @[RegisterRouter.scala:87:24] wire _out_T_5970 = out_f_wivalid_591; // @[RegisterRouter.scala:87:24] wire out_f_woready_591 = out_woready_1_445 & out_womask_591; // @[RegisterRouter.scala:87:24] wire _out_T_5971 = out_f_woready_591; // @[RegisterRouter.scala:87:24] wire _out_T_5972 = ~out_rimask_591; // @[RegisterRouter.scala:87:24] wire _out_T_5973 = ~out_wimask_591; // @[RegisterRouter.scala:87:24] wire _out_T_5974 = ~out_romask_591; // @[RegisterRouter.scala:87:24] wire _out_T_5975 = ~out_womask_591; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_499 = {programBufferMem_42, _out_prepend_T_499}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5976 = out_prepend_499; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5977 = _out_T_5976; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_500 = _out_T_5977; // @[RegisterRouter.scala:87:24] wire out_rimask_592 = |_out_rimask_T_592; // @[RegisterRouter.scala:87:24] wire out_wimask_592 = &_out_wimask_T_592; // @[RegisterRouter.scala:87:24] wire out_romask_592 = |_out_romask_T_592; // @[RegisterRouter.scala:87:24] wire out_womask_592 = &_out_womask_T_592; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_592 = out_rivalid_1_446 & out_rimask_592; // @[RegisterRouter.scala:87:24] wire _out_T_5979 = out_f_rivalid_592; // @[RegisterRouter.scala:87:24] wire out_f_roready_592 = out_roready_1_446 & out_romask_592; // @[RegisterRouter.scala:87:24] wire _out_T_5980 = out_f_roready_592; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_592 = out_wivalid_1_446 & out_wimask_592; // @[RegisterRouter.scala:87:24] wire _out_T_5981 = out_f_wivalid_592; // @[RegisterRouter.scala:87:24] wire out_f_woready_592 = out_woready_1_446 & out_womask_592; // @[RegisterRouter.scala:87:24] wire _out_T_5982 = out_f_woready_592; // @[RegisterRouter.scala:87:24] wire _out_T_5983 = ~out_rimask_592; // @[RegisterRouter.scala:87:24] wire _out_T_5984 = ~out_wimask_592; // @[RegisterRouter.scala:87:24] wire _out_T_5985 = ~out_romask_592; // @[RegisterRouter.scala:87:24] wire _out_T_5986 = ~out_womask_592; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_500 = {programBufferMem_43, _out_prepend_T_500}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5987 = out_prepend_500; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5988 = _out_T_5987; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_501 = _out_T_5988; // @[RegisterRouter.scala:87:24] wire out_rimask_593 = |_out_rimask_T_593; // @[RegisterRouter.scala:87:24] wire out_wimask_593 = &_out_wimask_T_593; // @[RegisterRouter.scala:87:24] wire out_romask_593 = |_out_romask_T_593; // @[RegisterRouter.scala:87:24] wire out_womask_593 = &_out_womask_T_593; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_593 = out_rivalid_1_447 & out_rimask_593; // @[RegisterRouter.scala:87:24] wire _out_T_5990 = out_f_rivalid_593; // @[RegisterRouter.scala:87:24] wire out_f_roready_593 = out_roready_1_447 & out_romask_593; // @[RegisterRouter.scala:87:24] wire _out_T_5991 = out_f_roready_593; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_593 = out_wivalid_1_447 & out_wimask_593; // @[RegisterRouter.scala:87:24] wire _out_T_5992 = out_f_wivalid_593; // @[RegisterRouter.scala:87:24] wire out_f_woready_593 = out_woready_1_447 & out_womask_593; // @[RegisterRouter.scala:87:24] wire _out_T_5993 = out_f_woready_593; // @[RegisterRouter.scala:87:24] wire _out_T_5994 = ~out_rimask_593; // @[RegisterRouter.scala:87:24] wire _out_T_5995 = ~out_wimask_593; // @[RegisterRouter.scala:87:24] wire _out_T_5996 = ~out_romask_593; // @[RegisterRouter.scala:87:24] wire _out_T_5997 = ~out_womask_593; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_501 = {programBufferMem_44, _out_prepend_T_501}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5998 = out_prepend_501; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5999 = _out_T_5998; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_502 = _out_T_5999; // @[RegisterRouter.scala:87:24] wire out_rimask_594 = |_out_rimask_T_594; // @[RegisterRouter.scala:87:24] wire out_wimask_594 = &_out_wimask_T_594; // @[RegisterRouter.scala:87:24] wire out_romask_594 = |_out_romask_T_594; // @[RegisterRouter.scala:87:24] wire out_womask_594 = &_out_womask_T_594; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_594 = out_rivalid_1_448 & out_rimask_594; // @[RegisterRouter.scala:87:24] wire _out_T_6001 = out_f_rivalid_594; // @[RegisterRouter.scala:87:24] wire out_f_roready_594 = out_roready_1_448 & out_romask_594; // @[RegisterRouter.scala:87:24] wire _out_T_6002 = out_f_roready_594; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_594 = out_wivalid_1_448 & out_wimask_594; // @[RegisterRouter.scala:87:24] wire _out_T_6003 = out_f_wivalid_594; // @[RegisterRouter.scala:87:24] wire out_f_woready_594 = out_woready_1_448 & out_womask_594; // @[RegisterRouter.scala:87:24] wire _out_T_6004 = out_f_woready_594; // @[RegisterRouter.scala:87:24] wire _out_T_6005 = ~out_rimask_594; // @[RegisterRouter.scala:87:24] wire _out_T_6006 = ~out_wimask_594; // @[RegisterRouter.scala:87:24] wire _out_T_6007 = ~out_romask_594; // @[RegisterRouter.scala:87:24] wire _out_T_6008 = ~out_womask_594; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_502 = {programBufferMem_45, _out_prepend_T_502}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6009 = out_prepend_502; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6010 = _out_T_6009; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_503 = _out_T_6010; // @[RegisterRouter.scala:87:24] wire out_rimask_595 = |_out_rimask_T_595; // @[RegisterRouter.scala:87:24] wire out_wimask_595 = &_out_wimask_T_595; // @[RegisterRouter.scala:87:24] wire out_romask_595 = |_out_romask_T_595; // @[RegisterRouter.scala:87:24] wire out_womask_595 = &_out_womask_T_595; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_595 = out_rivalid_1_449 & out_rimask_595; // @[RegisterRouter.scala:87:24] wire _out_T_6012 = out_f_rivalid_595; // @[RegisterRouter.scala:87:24] wire out_f_roready_595 = out_roready_1_449 & out_romask_595; // @[RegisterRouter.scala:87:24] wire _out_T_6013 = out_f_roready_595; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_595 = out_wivalid_1_449 & out_wimask_595; // @[RegisterRouter.scala:87:24] wire _out_T_6014 = out_f_wivalid_595; // @[RegisterRouter.scala:87:24] wire out_f_woready_595 = out_woready_1_449 & out_womask_595; // @[RegisterRouter.scala:87:24] wire _out_T_6015 = out_f_woready_595; // @[RegisterRouter.scala:87:24] wire _out_T_6016 = ~out_rimask_595; // @[RegisterRouter.scala:87:24] wire _out_T_6017 = ~out_wimask_595; // @[RegisterRouter.scala:87:24] wire _out_T_6018 = ~out_romask_595; // @[RegisterRouter.scala:87:24] wire _out_T_6019 = ~out_womask_595; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_503 = {programBufferMem_46, _out_prepend_T_503}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6020 = out_prepend_503; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6021 = _out_T_6020; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_504 = _out_T_6021; // @[RegisterRouter.scala:87:24] wire out_rimask_596 = |_out_rimask_T_596; // @[RegisterRouter.scala:87:24] wire out_wimask_596 = &_out_wimask_T_596; // @[RegisterRouter.scala:87:24] wire out_romask_596 = |_out_romask_T_596; // @[RegisterRouter.scala:87:24] wire out_womask_596 = &_out_womask_T_596; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_596 = out_rivalid_1_450 & out_rimask_596; // @[RegisterRouter.scala:87:24] wire _out_T_6023 = out_f_rivalid_596; // @[RegisterRouter.scala:87:24] wire out_f_roready_596 = out_roready_1_450 & out_romask_596; // @[RegisterRouter.scala:87:24] wire _out_T_6024 = out_f_roready_596; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_596 = out_wivalid_1_450 & out_wimask_596; // @[RegisterRouter.scala:87:24] wire _out_T_6025 = out_f_wivalid_596; // @[RegisterRouter.scala:87:24] wire out_f_woready_596 = out_woready_1_450 & out_womask_596; // @[RegisterRouter.scala:87:24] wire _out_T_6026 = out_f_woready_596; // @[RegisterRouter.scala:87:24] wire _out_T_6027 = ~out_rimask_596; // @[RegisterRouter.scala:87:24] wire _out_T_6028 = ~out_wimask_596; // @[RegisterRouter.scala:87:24] wire _out_T_6029 = ~out_romask_596; // @[RegisterRouter.scala:87:24] wire _out_T_6030 = ~out_womask_596; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_504 = {programBufferMem_47, _out_prepend_T_504}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6031 = out_prepend_504; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6032 = _out_T_6031; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_109 = _out_T_6032; // @[MuxLiteral.scala:49:48] wire out_rimask_597 = |_out_rimask_T_597; // @[RegisterRouter.scala:87:24] wire out_wimask_597 = &_out_wimask_T_597; // @[RegisterRouter.scala:87:24] wire out_romask_597 = |_out_romask_T_597; // @[RegisterRouter.scala:87:24] wire out_womask_597 = &_out_womask_T_597; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_597 = out_rivalid_1_451 & out_rimask_597; // @[RegisterRouter.scala:87:24] wire _out_T_6034 = out_f_rivalid_597; // @[RegisterRouter.scala:87:24] wire out_f_roready_597 = out_roready_1_451 & out_romask_597; // @[RegisterRouter.scala:87:24] wire _out_T_6035 = out_f_roready_597; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_597 = out_wivalid_1_451 & out_wimask_597; // @[RegisterRouter.scala:87:24] wire out_f_woready_597 = out_woready_1_451 & out_womask_597; // @[RegisterRouter.scala:87:24] wire _out_T_6036 = ~out_rimask_597; // @[RegisterRouter.scala:87:24] wire _out_T_6037 = ~out_wimask_597; // @[RegisterRouter.scala:87:24] wire _out_T_6038 = ~out_romask_597; // @[RegisterRouter.scala:87:24] wire _out_T_6039 = ~out_womask_597; // @[RegisterRouter.scala:87:24] wire out_rimask_598 = |_out_rimask_T_598; // @[RegisterRouter.scala:87:24] wire out_wimask_598 = &_out_wimask_T_598; // @[RegisterRouter.scala:87:24] wire out_romask_598 = |_out_romask_T_598; // @[RegisterRouter.scala:87:24] wire out_womask_598 = &_out_womask_T_598; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_598 = out_rivalid_1_452 & out_rimask_598; // @[RegisterRouter.scala:87:24] wire _out_T_6043 = out_f_rivalid_598; // @[RegisterRouter.scala:87:24] wire out_f_roready_598 = out_roready_1_452 & out_romask_598; // @[RegisterRouter.scala:87:24] wire _out_T_6044 = out_f_roready_598; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_598 = out_wivalid_1_452 & out_wimask_598; // @[RegisterRouter.scala:87:24] wire out_f_woready_598 = out_woready_1_452 & out_womask_598; // @[RegisterRouter.scala:87:24] wire _out_T_6045 = ~out_rimask_598; // @[RegisterRouter.scala:87:24] wire _out_T_6046 = ~out_wimask_598; // @[RegisterRouter.scala:87:24] wire _out_T_6047 = ~out_romask_598; // @[RegisterRouter.scala:87:24] wire _out_T_6048 = ~out_womask_598; // @[RegisterRouter.scala:87:24] wire out_rimask_599 = |_out_rimask_T_599; // @[RegisterRouter.scala:87:24] wire out_wimask_599 = &_out_wimask_T_599; // @[RegisterRouter.scala:87:24] wire out_romask_599 = |_out_romask_T_599; // @[RegisterRouter.scala:87:24] wire out_womask_599 = &_out_womask_T_599; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_599 = out_rivalid_1_453 & out_rimask_599; // @[RegisterRouter.scala:87:24] wire _out_T_6052 = out_f_rivalid_599; // @[RegisterRouter.scala:87:24] wire out_f_roready_599 = out_roready_1_453 & out_romask_599; // @[RegisterRouter.scala:87:24] wire _out_T_6053 = out_f_roready_599; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_599 = out_wivalid_1_453 & out_wimask_599; // @[RegisterRouter.scala:87:24] wire out_f_woready_599 = out_woready_1_453 & out_womask_599; // @[RegisterRouter.scala:87:24] wire _out_T_6054 = ~out_rimask_599; // @[RegisterRouter.scala:87:24] wire _out_T_6055 = ~out_wimask_599; // @[RegisterRouter.scala:87:24] wire _out_T_6056 = ~out_romask_599; // @[RegisterRouter.scala:87:24] wire _out_T_6057 = ~out_womask_599; // @[RegisterRouter.scala:87:24] wire out_rimask_600 = |_out_rimask_T_600; // @[RegisterRouter.scala:87:24] wire out_wimask_600 = &_out_wimask_T_600; // @[RegisterRouter.scala:87:24] wire out_romask_600 = |_out_romask_T_600; // @[RegisterRouter.scala:87:24] wire out_womask_600 = &_out_womask_T_600; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_600 = out_rivalid_1_454 & out_rimask_600; // @[RegisterRouter.scala:87:24] wire _out_T_6061 = out_f_rivalid_600; // @[RegisterRouter.scala:87:24] wire out_f_roready_600 = out_roready_1_454 & out_romask_600; // @[RegisterRouter.scala:87:24] wire _out_T_6062 = out_f_roready_600; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_600 = out_wivalid_1_454 & out_wimask_600; // @[RegisterRouter.scala:87:24] wire out_f_woready_600 = out_woready_1_454 & out_womask_600; // @[RegisterRouter.scala:87:24] wire _out_T_6063 = ~out_rimask_600; // @[RegisterRouter.scala:87:24] wire _out_T_6064 = ~out_wimask_600; // @[RegisterRouter.scala:87:24] wire _out_T_6065 = ~out_romask_600; // @[RegisterRouter.scala:87:24] wire _out_T_6066 = ~out_womask_600; // @[RegisterRouter.scala:87:24] wire out_rimask_601 = |_out_rimask_T_601; // @[RegisterRouter.scala:87:24] wire out_wimask_601 = &_out_wimask_T_601; // @[RegisterRouter.scala:87:24] wire out_romask_601 = |_out_romask_T_601; // @[RegisterRouter.scala:87:24] wire out_womask_601 = &_out_womask_T_601; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_601 = out_rivalid_1_455 & out_rimask_601; // @[RegisterRouter.scala:87:24] wire _out_T_6070 = out_f_rivalid_601; // @[RegisterRouter.scala:87:24] wire out_f_roready_601 = out_roready_1_455 & out_romask_601; // @[RegisterRouter.scala:87:24] wire _out_T_6071 = out_f_roready_601; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_601 = out_wivalid_1_455 & out_wimask_601; // @[RegisterRouter.scala:87:24] wire out_f_woready_601 = out_woready_1_455 & out_womask_601; // @[RegisterRouter.scala:87:24] wire _out_T_6072 = ~out_rimask_601; // @[RegisterRouter.scala:87:24] wire _out_T_6073 = ~out_wimask_601; // @[RegisterRouter.scala:87:24] wire _out_T_6074 = ~out_romask_601; // @[RegisterRouter.scala:87:24] wire _out_T_6075 = ~out_womask_601; // @[RegisterRouter.scala:87:24] wire out_rimask_602 = |_out_rimask_T_602; // @[RegisterRouter.scala:87:24] wire out_wimask_602 = &_out_wimask_T_602; // @[RegisterRouter.scala:87:24] wire out_romask_602 = |_out_romask_T_602; // @[RegisterRouter.scala:87:24] wire out_womask_602 = &_out_womask_T_602; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_602 = out_rivalid_1_456 & out_rimask_602; // @[RegisterRouter.scala:87:24] wire _out_T_6079 = out_f_rivalid_602; // @[RegisterRouter.scala:87:24] wire out_f_roready_602 = out_roready_1_456 & out_romask_602; // @[RegisterRouter.scala:87:24] wire _out_T_6080 = out_f_roready_602; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_602 = out_wivalid_1_456 & out_wimask_602; // @[RegisterRouter.scala:87:24] wire out_f_woready_602 = out_woready_1_456 & out_womask_602; // @[RegisterRouter.scala:87:24] wire _out_T_6081 = ~out_rimask_602; // @[RegisterRouter.scala:87:24] wire _out_T_6082 = ~out_wimask_602; // @[RegisterRouter.scala:87:24] wire _out_T_6083 = ~out_romask_602; // @[RegisterRouter.scala:87:24] wire _out_T_6084 = ~out_womask_602; // @[RegisterRouter.scala:87:24] wire out_rimask_603 = |_out_rimask_T_603; // @[RegisterRouter.scala:87:24] wire out_wimask_603 = &_out_wimask_T_603; // @[RegisterRouter.scala:87:24] wire out_romask_603 = |_out_romask_T_603; // @[RegisterRouter.scala:87:24] wire out_womask_603 = &_out_womask_T_603; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_603 = out_rivalid_1_457 & out_rimask_603; // @[RegisterRouter.scala:87:24] wire _out_T_6088 = out_f_rivalid_603; // @[RegisterRouter.scala:87:24] wire out_f_roready_603 = out_roready_1_457 & out_romask_603; // @[RegisterRouter.scala:87:24] wire _out_T_6089 = out_f_roready_603; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_603 = out_wivalid_1_457 & out_wimask_603; // @[RegisterRouter.scala:87:24] wire out_f_woready_603 = out_woready_1_457 & out_womask_603; // @[RegisterRouter.scala:87:24] wire _out_T_6090 = ~out_rimask_603; // @[RegisterRouter.scala:87:24] wire _out_T_6091 = ~out_wimask_603; // @[RegisterRouter.scala:87:24] wire _out_T_6092 = ~out_romask_603; // @[RegisterRouter.scala:87:24] wire _out_T_6093 = ~out_womask_603; // @[RegisterRouter.scala:87:24] wire out_rimask_604 = |_out_rimask_T_604; // @[RegisterRouter.scala:87:24] wire out_wimask_604 = &_out_wimask_T_604; // @[RegisterRouter.scala:87:24] wire out_romask_604 = |_out_romask_T_604; // @[RegisterRouter.scala:87:24] wire out_womask_604 = &_out_womask_T_604; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_604 = out_rivalid_1_458 & out_rimask_604; // @[RegisterRouter.scala:87:24] wire _out_T_6097 = out_f_rivalid_604; // @[RegisterRouter.scala:87:24] wire out_f_roready_604 = out_roready_1_458 & out_romask_604; // @[RegisterRouter.scala:87:24] wire _out_T_6098 = out_f_roready_604; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_604 = out_wivalid_1_458 & out_wimask_604; // @[RegisterRouter.scala:87:24] wire out_f_woready_604 = out_woready_1_458 & out_womask_604; // @[RegisterRouter.scala:87:24] wire _out_T_6099 = ~out_rimask_604; // @[RegisterRouter.scala:87:24] wire _out_T_6100 = ~out_wimask_604; // @[RegisterRouter.scala:87:24] wire _out_T_6101 = ~out_romask_604; // @[RegisterRouter.scala:87:24] wire _out_T_6102 = ~out_womask_604; // @[RegisterRouter.scala:87:24] wire out_rimask_605 = |_out_rimask_T_605; // @[RegisterRouter.scala:87:24] wire out_wimask_605 = &_out_wimask_T_605; // @[RegisterRouter.scala:87:24] wire out_romask_605 = |_out_romask_T_605; // @[RegisterRouter.scala:87:24] wire out_womask_605 = &_out_womask_T_605; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_605 = out_rivalid_1_459 & out_rimask_605; // @[RegisterRouter.scala:87:24] wire _out_T_6106 = out_f_rivalid_605; // @[RegisterRouter.scala:87:24] wire out_f_roready_605 = out_roready_1_459 & out_romask_605; // @[RegisterRouter.scala:87:24] wire _out_T_6107 = out_f_roready_605; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_605 = out_wivalid_1_459 & out_wimask_605; // @[RegisterRouter.scala:87:24] wire out_f_woready_605 = out_woready_1_459 & out_womask_605; // @[RegisterRouter.scala:87:24] wire _out_T_6108 = ~out_rimask_605; // @[RegisterRouter.scala:87:24] wire _out_T_6109 = ~out_wimask_605; // @[RegisterRouter.scala:87:24] wire _out_T_6110 = ~out_romask_605; // @[RegisterRouter.scala:87:24] wire _out_T_6111 = ~out_womask_605; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6113 = _out_T_6112; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_512 = _out_T_6113; // @[RegisterRouter.scala:87:24] wire out_rimask_606 = |_out_rimask_T_606; // @[RegisterRouter.scala:87:24] wire out_wimask_606 = &_out_wimask_T_606; // @[RegisterRouter.scala:87:24] wire out_romask_606 = |_out_romask_T_606; // @[RegisterRouter.scala:87:24] wire out_womask_606 = &_out_womask_T_606; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_606 = out_rivalid_1_460 & out_rimask_606; // @[RegisterRouter.scala:87:24] wire _out_T_6115 = out_f_rivalid_606; // @[RegisterRouter.scala:87:24] wire out_f_roready_606 = out_roready_1_460 & out_romask_606; // @[RegisterRouter.scala:87:24] wire _out_T_6116 = out_f_roready_606; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_606 = out_wivalid_1_460 & out_wimask_606; // @[RegisterRouter.scala:87:24] wire out_f_woready_606 = out_woready_1_460 & out_womask_606; // @[RegisterRouter.scala:87:24] wire _out_T_6117 = ~out_rimask_606; // @[RegisterRouter.scala:87:24] wire _out_T_6118 = ~out_wimask_606; // @[RegisterRouter.scala:87:24] wire _out_T_6119 = ~out_romask_606; // @[RegisterRouter.scala:87:24] wire _out_T_6120 = ~out_womask_606; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_512 = {hi_362, flags_0_go, _out_prepend_T_512}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6121 = out_prepend_512; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6122 = _out_T_6121; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_513 = _out_T_6122; // @[RegisterRouter.scala:87:24] wire out_rimask_607 = |_out_rimask_T_607; // @[RegisterRouter.scala:87:24] wire out_wimask_607 = &_out_wimask_T_607; // @[RegisterRouter.scala:87:24] wire out_romask_607 = |_out_romask_T_607; // @[RegisterRouter.scala:87:24] wire out_womask_607 = &_out_womask_T_607; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_607 = out_rivalid_1_461 & out_rimask_607; // @[RegisterRouter.scala:87:24] wire _out_T_6124 = out_f_rivalid_607; // @[RegisterRouter.scala:87:24] wire out_f_roready_607 = out_roready_1_461 & out_romask_607; // @[RegisterRouter.scala:87:24] wire _out_T_6125 = out_f_roready_607; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_607 = out_wivalid_1_461 & out_wimask_607; // @[RegisterRouter.scala:87:24] wire out_f_woready_607 = out_woready_1_461 & out_womask_607; // @[RegisterRouter.scala:87:24] wire _out_T_6126 = ~out_rimask_607; // @[RegisterRouter.scala:87:24] wire _out_T_6127 = ~out_wimask_607; // @[RegisterRouter.scala:87:24] wire _out_T_6128 = ~out_romask_607; // @[RegisterRouter.scala:87:24] wire _out_T_6129 = ~out_womask_607; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_513 = {hi_363, flags_0_go, _out_prepend_T_513}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6130 = out_prepend_513; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6131 = _out_T_6130; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_514 = _out_T_6131; // @[RegisterRouter.scala:87:24] wire out_rimask_608 = |_out_rimask_T_608; // @[RegisterRouter.scala:87:24] wire out_wimask_608 = &_out_wimask_T_608; // @[RegisterRouter.scala:87:24] wire out_romask_608 = |_out_romask_T_608; // @[RegisterRouter.scala:87:24] wire out_womask_608 = &_out_womask_T_608; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_608 = out_rivalid_1_462 & out_rimask_608; // @[RegisterRouter.scala:87:24] wire _out_T_6133 = out_f_rivalid_608; // @[RegisterRouter.scala:87:24] wire out_f_roready_608 = out_roready_1_462 & out_romask_608; // @[RegisterRouter.scala:87:24] wire _out_T_6134 = out_f_roready_608; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_608 = out_wivalid_1_462 & out_wimask_608; // @[RegisterRouter.scala:87:24] wire out_f_woready_608 = out_woready_1_462 & out_womask_608; // @[RegisterRouter.scala:87:24] wire _out_T_6135 = ~out_rimask_608; // @[RegisterRouter.scala:87:24] wire _out_T_6136 = ~out_wimask_608; // @[RegisterRouter.scala:87:24] wire _out_T_6137 = ~out_romask_608; // @[RegisterRouter.scala:87:24] wire _out_T_6138 = ~out_womask_608; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_514 = {hi_364, flags_0_go, _out_prepend_T_514}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6139 = out_prepend_514; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6140 = _out_T_6139; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_515 = _out_T_6140; // @[RegisterRouter.scala:87:24] wire out_rimask_609 = |_out_rimask_T_609; // @[RegisterRouter.scala:87:24] wire out_wimask_609 = &_out_wimask_T_609; // @[RegisterRouter.scala:87:24] wire out_romask_609 = |_out_romask_T_609; // @[RegisterRouter.scala:87:24] wire out_womask_609 = &_out_womask_T_609; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_609 = out_rivalid_1_463 & out_rimask_609; // @[RegisterRouter.scala:87:24] wire _out_T_6142 = out_f_rivalid_609; // @[RegisterRouter.scala:87:24] wire out_f_roready_609 = out_roready_1_463 & out_romask_609; // @[RegisterRouter.scala:87:24] wire _out_T_6143 = out_f_roready_609; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_609 = out_wivalid_1_463 & out_wimask_609; // @[RegisterRouter.scala:87:24] wire out_f_woready_609 = out_woready_1_463 & out_womask_609; // @[RegisterRouter.scala:87:24] wire _out_T_6144 = ~out_rimask_609; // @[RegisterRouter.scala:87:24] wire _out_T_6145 = ~out_wimask_609; // @[RegisterRouter.scala:87:24] wire _out_T_6146 = ~out_romask_609; // @[RegisterRouter.scala:87:24] wire _out_T_6147 = ~out_womask_609; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_515 = {hi_365, flags_0_go, _out_prepend_T_515}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6148 = out_prepend_515; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6149 = _out_T_6148; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_516 = _out_T_6149; // @[RegisterRouter.scala:87:24] wire out_rimask_610 = |_out_rimask_T_610; // @[RegisterRouter.scala:87:24] wire out_wimask_610 = &_out_wimask_T_610; // @[RegisterRouter.scala:87:24] wire out_romask_610 = |_out_romask_T_610; // @[RegisterRouter.scala:87:24] wire out_womask_610 = &_out_womask_T_610; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_610 = out_rivalid_1_464 & out_rimask_610; // @[RegisterRouter.scala:87:24] wire _out_T_6151 = out_f_rivalid_610; // @[RegisterRouter.scala:87:24] wire out_f_roready_610 = out_roready_1_464 & out_romask_610; // @[RegisterRouter.scala:87:24] wire _out_T_6152 = out_f_roready_610; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_610 = out_wivalid_1_464 & out_wimask_610; // @[RegisterRouter.scala:87:24] wire out_f_woready_610 = out_woready_1_464 & out_womask_610; // @[RegisterRouter.scala:87:24] wire _out_T_6153 = ~out_rimask_610; // @[RegisterRouter.scala:87:24] wire _out_T_6154 = ~out_wimask_610; // @[RegisterRouter.scala:87:24] wire _out_T_6155 = ~out_romask_610; // @[RegisterRouter.scala:87:24] wire _out_T_6156 = ~out_womask_610; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_516 = {hi_366, flags_0_go, _out_prepend_T_516}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6157 = out_prepend_516; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6158 = _out_T_6157; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_517 = _out_T_6158; // @[RegisterRouter.scala:87:24] wire out_rimask_611 = |_out_rimask_T_611; // @[RegisterRouter.scala:87:24] wire out_wimask_611 = &_out_wimask_T_611; // @[RegisterRouter.scala:87:24] wire out_romask_611 = |_out_romask_T_611; // @[RegisterRouter.scala:87:24] wire out_womask_611 = &_out_womask_T_611; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_611 = out_rivalid_1_465 & out_rimask_611; // @[RegisterRouter.scala:87:24] wire _out_T_6160 = out_f_rivalid_611; // @[RegisterRouter.scala:87:24] wire out_f_roready_611 = out_roready_1_465 & out_romask_611; // @[RegisterRouter.scala:87:24] wire _out_T_6161 = out_f_roready_611; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_611 = out_wivalid_1_465 & out_wimask_611; // @[RegisterRouter.scala:87:24] wire out_f_woready_611 = out_woready_1_465 & out_womask_611; // @[RegisterRouter.scala:87:24] wire _out_T_6162 = ~out_rimask_611; // @[RegisterRouter.scala:87:24] wire _out_T_6163 = ~out_wimask_611; // @[RegisterRouter.scala:87:24] wire _out_T_6164 = ~out_romask_611; // @[RegisterRouter.scala:87:24] wire _out_T_6165 = ~out_womask_611; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_517 = {hi_367, flags_0_go, _out_prepend_T_517}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6166 = out_prepend_517; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6167 = _out_T_6166; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_518 = _out_T_6167; // @[RegisterRouter.scala:87:24] wire out_rimask_612 = |_out_rimask_T_612; // @[RegisterRouter.scala:87:24] wire out_wimask_612 = &_out_wimask_T_612; // @[RegisterRouter.scala:87:24] wire out_romask_612 = |_out_romask_T_612; // @[RegisterRouter.scala:87:24] wire out_womask_612 = &_out_womask_T_612; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_612 = out_rivalid_1_466 & out_rimask_612; // @[RegisterRouter.scala:87:24] wire _out_T_6169 = out_f_rivalid_612; // @[RegisterRouter.scala:87:24] wire out_f_roready_612 = out_roready_1_466 & out_romask_612; // @[RegisterRouter.scala:87:24] wire _out_T_6170 = out_f_roready_612; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_612 = out_wivalid_1_466 & out_wimask_612; // @[RegisterRouter.scala:87:24] wire out_f_woready_612 = out_woready_1_466 & out_womask_612; // @[RegisterRouter.scala:87:24] wire _out_T_6171 = ~out_rimask_612; // @[RegisterRouter.scala:87:24] wire _out_T_6172 = ~out_wimask_612; // @[RegisterRouter.scala:87:24] wire _out_T_6173 = ~out_romask_612; // @[RegisterRouter.scala:87:24] wire _out_T_6174 = ~out_womask_612; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_518 = {hi_368, flags_0_go, _out_prepend_T_518}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6175 = out_prepend_518; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6176 = _out_T_6175; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_173 = _out_T_6176; // @[MuxLiteral.scala:49:48] wire out_rimask_613 = |_out_rimask_T_613; // @[RegisterRouter.scala:87:24] wire out_wimask_613 = &_out_wimask_T_613; // @[RegisterRouter.scala:87:24] wire out_romask_613 = |_out_romask_T_613; // @[RegisterRouter.scala:87:24] wire out_womask_613 = &_out_womask_T_613; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_613 = out_rivalid_1_467 & out_rimask_613; // @[RegisterRouter.scala:87:24] wire _out_T_6178 = out_f_rivalid_613; // @[RegisterRouter.scala:87:24] wire out_f_roready_613 = out_roready_1_467 & out_romask_613; // @[RegisterRouter.scala:87:24] wire _out_T_6179 = out_f_roready_613; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_613 = out_wivalid_1_467 & out_wimask_613; // @[RegisterRouter.scala:87:24] wire out_f_woready_613 = out_woready_1_467 & out_womask_613; // @[RegisterRouter.scala:87:24] wire _out_T_6180 = ~out_rimask_613; // @[RegisterRouter.scala:87:24] wire _out_T_6181 = ~out_wimask_613; // @[RegisterRouter.scala:87:24] wire _out_T_6182 = ~out_romask_613; // @[RegisterRouter.scala:87:24] wire _out_T_6183 = ~out_womask_613; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6185 = _out_T_6184; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_519 = _out_T_6185; // @[RegisterRouter.scala:87:24] wire out_rimask_614 = |_out_rimask_T_614; // @[RegisterRouter.scala:87:24] wire out_wimask_614 = &_out_wimask_T_614; // @[RegisterRouter.scala:87:24] wire out_romask_614 = |_out_romask_T_614; // @[RegisterRouter.scala:87:24] wire out_womask_614 = &_out_womask_T_614; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_614 = out_rivalid_1_468 & out_rimask_614; // @[RegisterRouter.scala:87:24] wire _out_T_6187 = out_f_rivalid_614; // @[RegisterRouter.scala:87:24] wire out_f_roready_614 = out_roready_1_468 & out_romask_614; // @[RegisterRouter.scala:87:24] wire _out_T_6188 = out_f_roready_614; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_614 = out_wivalid_1_468 & out_wimask_614; // @[RegisterRouter.scala:87:24] wire out_f_woready_614 = out_woready_1_468 & out_womask_614; // @[RegisterRouter.scala:87:24] wire _out_T_6189 = ~out_rimask_614; // @[RegisterRouter.scala:87:24] wire _out_T_6190 = ~out_wimask_614; // @[RegisterRouter.scala:87:24] wire _out_T_6191 = ~out_romask_614; // @[RegisterRouter.scala:87:24] wire _out_T_6192 = ~out_womask_614; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_519 = {hi_10, flags_0_go, _out_prepend_T_519}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6193 = out_prepend_519; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6194 = _out_T_6193; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_520 = _out_T_6194; // @[RegisterRouter.scala:87:24] wire out_rimask_615 = |_out_rimask_T_615; // @[RegisterRouter.scala:87:24] wire out_wimask_615 = &_out_wimask_T_615; // @[RegisterRouter.scala:87:24] wire out_romask_615 = |_out_romask_T_615; // @[RegisterRouter.scala:87:24] wire out_womask_615 = &_out_womask_T_615; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_615 = out_rivalid_1_469 & out_rimask_615; // @[RegisterRouter.scala:87:24] wire _out_T_6196 = out_f_rivalid_615; // @[RegisterRouter.scala:87:24] wire out_f_roready_615 = out_roready_1_469 & out_romask_615; // @[RegisterRouter.scala:87:24] wire _out_T_6197 = out_f_roready_615; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_615 = out_wivalid_1_469 & out_wimask_615; // @[RegisterRouter.scala:87:24] wire out_f_woready_615 = out_woready_1_469 & out_womask_615; // @[RegisterRouter.scala:87:24] wire _out_T_6198 = ~out_rimask_615; // @[RegisterRouter.scala:87:24] wire _out_T_6199 = ~out_wimask_615; // @[RegisterRouter.scala:87:24] wire _out_T_6200 = ~out_romask_615; // @[RegisterRouter.scala:87:24] wire _out_T_6201 = ~out_womask_615; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_520 = {hi_11, flags_0_go, _out_prepend_T_520}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6202 = out_prepend_520; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6203 = _out_T_6202; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_521 = _out_T_6203; // @[RegisterRouter.scala:87:24] wire out_rimask_616 = |_out_rimask_T_616; // @[RegisterRouter.scala:87:24] wire out_wimask_616 = &_out_wimask_T_616; // @[RegisterRouter.scala:87:24] wire out_romask_616 = |_out_romask_T_616; // @[RegisterRouter.scala:87:24] wire out_womask_616 = &_out_womask_T_616; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_616 = out_rivalid_1_470 & out_rimask_616; // @[RegisterRouter.scala:87:24] wire _out_T_6205 = out_f_rivalid_616; // @[RegisterRouter.scala:87:24] wire out_f_roready_616 = out_roready_1_470 & out_romask_616; // @[RegisterRouter.scala:87:24] wire _out_T_6206 = out_f_roready_616; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_616 = out_wivalid_1_470 & out_wimask_616; // @[RegisterRouter.scala:87:24] wire out_f_woready_616 = out_woready_1_470 & out_womask_616; // @[RegisterRouter.scala:87:24] wire _out_T_6207 = ~out_rimask_616; // @[RegisterRouter.scala:87:24] wire _out_T_6208 = ~out_wimask_616; // @[RegisterRouter.scala:87:24] wire _out_T_6209 = ~out_romask_616; // @[RegisterRouter.scala:87:24] wire _out_T_6210 = ~out_womask_616; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_521 = {hi_12, flags_0_go, _out_prepend_T_521}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6211 = out_prepend_521; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6212 = _out_T_6211; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_522 = _out_T_6212; // @[RegisterRouter.scala:87:24] wire out_rimask_617 = |_out_rimask_T_617; // @[RegisterRouter.scala:87:24] wire out_wimask_617 = &_out_wimask_T_617; // @[RegisterRouter.scala:87:24] wire out_romask_617 = |_out_romask_T_617; // @[RegisterRouter.scala:87:24] wire out_womask_617 = &_out_womask_T_617; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_617 = out_rivalid_1_471 & out_rimask_617; // @[RegisterRouter.scala:87:24] wire _out_T_6214 = out_f_rivalid_617; // @[RegisterRouter.scala:87:24] wire out_f_roready_617 = out_roready_1_471 & out_romask_617; // @[RegisterRouter.scala:87:24] wire _out_T_6215 = out_f_roready_617; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_617 = out_wivalid_1_471 & out_wimask_617; // @[RegisterRouter.scala:87:24] wire out_f_woready_617 = out_woready_1_471 & out_womask_617; // @[RegisterRouter.scala:87:24] wire _out_T_6216 = ~out_rimask_617; // @[RegisterRouter.scala:87:24] wire _out_T_6217 = ~out_wimask_617; // @[RegisterRouter.scala:87:24] wire _out_T_6218 = ~out_romask_617; // @[RegisterRouter.scala:87:24] wire _out_T_6219 = ~out_womask_617; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_522 = {hi_13, flags_0_go, _out_prepend_T_522}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6220 = out_prepend_522; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6221 = _out_T_6220; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_523 = _out_T_6221; // @[RegisterRouter.scala:87:24] wire out_rimask_618 = |_out_rimask_T_618; // @[RegisterRouter.scala:87:24] wire out_wimask_618 = &_out_wimask_T_618; // @[RegisterRouter.scala:87:24] wire out_romask_618 = |_out_romask_T_618; // @[RegisterRouter.scala:87:24] wire out_womask_618 = &_out_womask_T_618; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_618 = out_rivalid_1_472 & out_rimask_618; // @[RegisterRouter.scala:87:24] wire _out_T_6223 = out_f_rivalid_618; // @[RegisterRouter.scala:87:24] wire out_f_roready_618 = out_roready_1_472 & out_romask_618; // @[RegisterRouter.scala:87:24] wire _out_T_6224 = out_f_roready_618; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_618 = out_wivalid_1_472 & out_wimask_618; // @[RegisterRouter.scala:87:24] wire out_f_woready_618 = out_woready_1_472 & out_womask_618; // @[RegisterRouter.scala:87:24] wire _out_T_6225 = ~out_rimask_618; // @[RegisterRouter.scala:87:24] wire _out_T_6226 = ~out_wimask_618; // @[RegisterRouter.scala:87:24] wire _out_T_6227 = ~out_romask_618; // @[RegisterRouter.scala:87:24] wire _out_T_6228 = ~out_womask_618; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_523 = {hi_14, flags_0_go, _out_prepend_T_523}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6229 = out_prepend_523; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6230 = _out_T_6229; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_524 = _out_T_6230; // @[RegisterRouter.scala:87:24] wire out_rimask_619 = |_out_rimask_T_619; // @[RegisterRouter.scala:87:24] wire out_wimask_619 = &_out_wimask_T_619; // @[RegisterRouter.scala:87:24] wire out_romask_619 = |_out_romask_T_619; // @[RegisterRouter.scala:87:24] wire out_womask_619 = &_out_womask_T_619; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_619 = out_rivalid_1_473 & out_rimask_619; // @[RegisterRouter.scala:87:24] wire _out_T_6232 = out_f_rivalid_619; // @[RegisterRouter.scala:87:24] wire out_f_roready_619 = out_roready_1_473 & out_romask_619; // @[RegisterRouter.scala:87:24] wire _out_T_6233 = out_f_roready_619; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_619 = out_wivalid_1_473 & out_wimask_619; // @[RegisterRouter.scala:87:24] wire out_f_woready_619 = out_woready_1_473 & out_womask_619; // @[RegisterRouter.scala:87:24] wire _out_T_6234 = ~out_rimask_619; // @[RegisterRouter.scala:87:24] wire _out_T_6235 = ~out_wimask_619; // @[RegisterRouter.scala:87:24] wire _out_T_6236 = ~out_romask_619; // @[RegisterRouter.scala:87:24] wire _out_T_6237 = ~out_womask_619; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_524 = {hi_15, flags_0_go, _out_prepend_T_524}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6238 = out_prepend_524; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6239 = _out_T_6238; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_525 = _out_T_6239; // @[RegisterRouter.scala:87:24] wire out_rimask_620 = |_out_rimask_T_620; // @[RegisterRouter.scala:87:24] wire out_wimask_620 = &_out_wimask_T_620; // @[RegisterRouter.scala:87:24] wire out_romask_620 = |_out_romask_T_620; // @[RegisterRouter.scala:87:24] wire out_womask_620 = &_out_womask_T_620; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_620 = out_rivalid_1_474 & out_rimask_620; // @[RegisterRouter.scala:87:24] wire _out_T_6241 = out_f_rivalid_620; // @[RegisterRouter.scala:87:24] wire out_f_roready_620 = out_roready_1_474 & out_romask_620; // @[RegisterRouter.scala:87:24] wire _out_T_6242 = out_f_roready_620; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_620 = out_wivalid_1_474 & out_wimask_620; // @[RegisterRouter.scala:87:24] wire out_f_woready_620 = out_woready_1_474 & out_womask_620; // @[RegisterRouter.scala:87:24] wire _out_T_6243 = ~out_rimask_620; // @[RegisterRouter.scala:87:24] wire _out_T_6244 = ~out_wimask_620; // @[RegisterRouter.scala:87:24] wire _out_T_6245 = ~out_romask_620; // @[RegisterRouter.scala:87:24] wire _out_T_6246 = ~out_womask_620; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_525 = {hi_16, flags_0_go, _out_prepend_T_525}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6247 = out_prepend_525; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6248 = _out_T_6247; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_129 = _out_T_6248; // @[MuxLiteral.scala:49:48] wire out_rimask_621 = |_out_rimask_T_621; // @[RegisterRouter.scala:87:24] wire out_wimask_621 = &_out_wimask_T_621; // @[RegisterRouter.scala:87:24] wire out_romask_621 = |_out_romask_T_621; // @[RegisterRouter.scala:87:24] wire out_womask_621 = &_out_womask_T_621; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_621 = out_rivalid_1_475 & out_rimask_621; // @[RegisterRouter.scala:87:24] wire _out_T_6250 = out_f_rivalid_621; // @[RegisterRouter.scala:87:24] wire out_f_roready_621 = out_roready_1_475 & out_romask_621; // @[RegisterRouter.scala:87:24] wire _out_T_6251 = out_f_roready_621; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_621 = out_wivalid_1_475 & out_wimask_621; // @[RegisterRouter.scala:87:24] wire out_f_woready_621 = out_woready_1_475 & out_womask_621; // @[RegisterRouter.scala:87:24] wire _out_T_6252 = ~out_rimask_621; // @[RegisterRouter.scala:87:24] wire _out_T_6253 = ~out_wimask_621; // @[RegisterRouter.scala:87:24] wire _out_T_6254 = ~out_romask_621; // @[RegisterRouter.scala:87:24] wire _out_T_6255 = ~out_womask_621; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6257 = _out_T_6256; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_526 = _out_T_6257; // @[RegisterRouter.scala:87:24] wire out_rimask_622 = |_out_rimask_T_622; // @[RegisterRouter.scala:87:24] wire out_wimask_622 = &_out_wimask_T_622; // @[RegisterRouter.scala:87:24] wire out_romask_622 = |_out_romask_T_622; // @[RegisterRouter.scala:87:24] wire out_womask_622 = &_out_womask_T_622; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_622 = out_rivalid_1_476 & out_rimask_622; // @[RegisterRouter.scala:87:24] wire _out_T_6259 = out_f_rivalid_622; // @[RegisterRouter.scala:87:24] wire out_f_roready_622 = out_roready_1_476 & out_romask_622; // @[RegisterRouter.scala:87:24] wire _out_T_6260 = out_f_roready_622; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_622 = out_wivalid_1_476 & out_wimask_622; // @[RegisterRouter.scala:87:24] wire out_f_woready_622 = out_woready_1_476 & out_womask_622; // @[RegisterRouter.scala:87:24] wire _out_T_6261 = ~out_rimask_622; // @[RegisterRouter.scala:87:24] wire _out_T_6262 = ~out_wimask_622; // @[RegisterRouter.scala:87:24] wire _out_T_6263 = ~out_romask_622; // @[RegisterRouter.scala:87:24] wire _out_T_6264 = ~out_womask_622; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_526 = {hi_50, flags_0_go, _out_prepend_T_526}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6265 = out_prepend_526; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6266 = _out_T_6265; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_527 = _out_T_6266; // @[RegisterRouter.scala:87:24] wire out_rimask_623 = |_out_rimask_T_623; // @[RegisterRouter.scala:87:24] wire out_wimask_623 = &_out_wimask_T_623; // @[RegisterRouter.scala:87:24] wire out_romask_623 = |_out_romask_T_623; // @[RegisterRouter.scala:87:24] wire out_womask_623 = &_out_womask_T_623; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_623 = out_rivalid_1_477 & out_rimask_623; // @[RegisterRouter.scala:87:24] wire _out_T_6268 = out_f_rivalid_623; // @[RegisterRouter.scala:87:24] wire out_f_roready_623 = out_roready_1_477 & out_romask_623; // @[RegisterRouter.scala:87:24] wire _out_T_6269 = out_f_roready_623; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_623 = out_wivalid_1_477 & out_wimask_623; // @[RegisterRouter.scala:87:24] wire out_f_woready_623 = out_woready_1_477 & out_womask_623; // @[RegisterRouter.scala:87:24] wire _out_T_6270 = ~out_rimask_623; // @[RegisterRouter.scala:87:24] wire _out_T_6271 = ~out_wimask_623; // @[RegisterRouter.scala:87:24] wire _out_T_6272 = ~out_romask_623; // @[RegisterRouter.scala:87:24] wire _out_T_6273 = ~out_womask_623; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_527 = {hi_51, flags_0_go, _out_prepend_T_527}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6274 = out_prepend_527; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6275 = _out_T_6274; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_528 = _out_T_6275; // @[RegisterRouter.scala:87:24] wire out_rimask_624 = |_out_rimask_T_624; // @[RegisterRouter.scala:87:24] wire out_wimask_624 = &_out_wimask_T_624; // @[RegisterRouter.scala:87:24] wire out_romask_624 = |_out_romask_T_624; // @[RegisterRouter.scala:87:24] wire out_womask_624 = &_out_womask_T_624; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_624 = out_rivalid_1_478 & out_rimask_624; // @[RegisterRouter.scala:87:24] wire _out_T_6277 = out_f_rivalid_624; // @[RegisterRouter.scala:87:24] wire out_f_roready_624 = out_roready_1_478 & out_romask_624; // @[RegisterRouter.scala:87:24] wire _out_T_6278 = out_f_roready_624; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_624 = out_wivalid_1_478 & out_wimask_624; // @[RegisterRouter.scala:87:24] wire out_f_woready_624 = out_woready_1_478 & out_womask_624; // @[RegisterRouter.scala:87:24] wire _out_T_6279 = ~out_rimask_624; // @[RegisterRouter.scala:87:24] wire _out_T_6280 = ~out_wimask_624; // @[RegisterRouter.scala:87:24] wire _out_T_6281 = ~out_romask_624; // @[RegisterRouter.scala:87:24] wire _out_T_6282 = ~out_womask_624; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_528 = {hi_52, flags_0_go, _out_prepend_T_528}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6283 = out_prepend_528; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6284 = _out_T_6283; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_529 = _out_T_6284; // @[RegisterRouter.scala:87:24] wire out_rimask_625 = |_out_rimask_T_625; // @[RegisterRouter.scala:87:24] wire out_wimask_625 = &_out_wimask_T_625; // @[RegisterRouter.scala:87:24] wire out_romask_625 = |_out_romask_T_625; // @[RegisterRouter.scala:87:24] wire out_womask_625 = &_out_womask_T_625; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_625 = out_rivalid_1_479 & out_rimask_625; // @[RegisterRouter.scala:87:24] wire _out_T_6286 = out_f_rivalid_625; // @[RegisterRouter.scala:87:24] wire out_f_roready_625 = out_roready_1_479 & out_romask_625; // @[RegisterRouter.scala:87:24] wire _out_T_6287 = out_f_roready_625; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_625 = out_wivalid_1_479 & out_wimask_625; // @[RegisterRouter.scala:87:24] wire out_f_woready_625 = out_woready_1_479 & out_womask_625; // @[RegisterRouter.scala:87:24] wire _out_T_6288 = ~out_rimask_625; // @[RegisterRouter.scala:87:24] wire _out_T_6289 = ~out_wimask_625; // @[RegisterRouter.scala:87:24] wire _out_T_6290 = ~out_romask_625; // @[RegisterRouter.scala:87:24] wire _out_T_6291 = ~out_womask_625; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_529 = {hi_53, flags_0_go, _out_prepend_T_529}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6292 = out_prepend_529; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6293 = _out_T_6292; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_530 = _out_T_6293; // @[RegisterRouter.scala:87:24] wire out_rimask_626 = |_out_rimask_T_626; // @[RegisterRouter.scala:87:24] wire out_wimask_626 = &_out_wimask_T_626; // @[RegisterRouter.scala:87:24] wire out_romask_626 = |_out_romask_T_626; // @[RegisterRouter.scala:87:24] wire out_womask_626 = &_out_womask_T_626; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_626 = out_rivalid_1_480 & out_rimask_626; // @[RegisterRouter.scala:87:24] wire _out_T_6295 = out_f_rivalid_626; // @[RegisterRouter.scala:87:24] wire out_f_roready_626 = out_roready_1_480 & out_romask_626; // @[RegisterRouter.scala:87:24] wire _out_T_6296 = out_f_roready_626; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_626 = out_wivalid_1_480 & out_wimask_626; // @[RegisterRouter.scala:87:24] wire out_f_woready_626 = out_woready_1_480 & out_womask_626; // @[RegisterRouter.scala:87:24] wire _out_T_6297 = ~out_rimask_626; // @[RegisterRouter.scala:87:24] wire _out_T_6298 = ~out_wimask_626; // @[RegisterRouter.scala:87:24] wire _out_T_6299 = ~out_romask_626; // @[RegisterRouter.scala:87:24] wire _out_T_6300 = ~out_womask_626; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_530 = {hi_54, flags_0_go, _out_prepend_T_530}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6301 = out_prepend_530; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6302 = _out_T_6301; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_531 = _out_T_6302; // @[RegisterRouter.scala:87:24] wire out_rimask_627 = |_out_rimask_T_627; // @[RegisterRouter.scala:87:24] wire out_wimask_627 = &_out_wimask_T_627; // @[RegisterRouter.scala:87:24] wire out_romask_627 = |_out_romask_T_627; // @[RegisterRouter.scala:87:24] wire out_womask_627 = &_out_womask_T_627; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_627 = out_rivalid_1_481 & out_rimask_627; // @[RegisterRouter.scala:87:24] wire _out_T_6304 = out_f_rivalid_627; // @[RegisterRouter.scala:87:24] wire out_f_roready_627 = out_roready_1_481 & out_romask_627; // @[RegisterRouter.scala:87:24] wire _out_T_6305 = out_f_roready_627; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_627 = out_wivalid_1_481 & out_wimask_627; // @[RegisterRouter.scala:87:24] wire out_f_woready_627 = out_woready_1_481 & out_womask_627; // @[RegisterRouter.scala:87:24] wire _out_T_6306 = ~out_rimask_627; // @[RegisterRouter.scala:87:24] wire _out_T_6307 = ~out_wimask_627; // @[RegisterRouter.scala:87:24] wire _out_T_6308 = ~out_romask_627; // @[RegisterRouter.scala:87:24] wire _out_T_6309 = ~out_womask_627; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_531 = {hi_55, flags_0_go, _out_prepend_T_531}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6310 = out_prepend_531; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6311 = _out_T_6310; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_532 = _out_T_6311; // @[RegisterRouter.scala:87:24] wire out_rimask_628 = |_out_rimask_T_628; // @[RegisterRouter.scala:87:24] wire out_wimask_628 = &_out_wimask_T_628; // @[RegisterRouter.scala:87:24] wire out_romask_628 = |_out_romask_T_628; // @[RegisterRouter.scala:87:24] wire out_womask_628 = &_out_womask_T_628; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_628 = out_rivalid_1_482 & out_rimask_628; // @[RegisterRouter.scala:87:24] wire _out_T_6313 = out_f_rivalid_628; // @[RegisterRouter.scala:87:24] wire out_f_roready_628 = out_roready_1_482 & out_romask_628; // @[RegisterRouter.scala:87:24] wire _out_T_6314 = out_f_roready_628; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_628 = out_wivalid_1_482 & out_wimask_628; // @[RegisterRouter.scala:87:24] wire out_f_woready_628 = out_woready_1_482 & out_womask_628; // @[RegisterRouter.scala:87:24] wire _out_T_6315 = ~out_rimask_628; // @[RegisterRouter.scala:87:24] wire _out_T_6316 = ~out_wimask_628; // @[RegisterRouter.scala:87:24] wire _out_T_6317 = ~out_romask_628; // @[RegisterRouter.scala:87:24] wire _out_T_6318 = ~out_womask_628; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_532 = {hi_56, flags_0_go, _out_prepend_T_532}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6319 = out_prepend_532; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6320 = _out_T_6319; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_134 = _out_T_6320; // @[MuxLiteral.scala:49:48] wire out_rimask_629 = |_out_rimask_T_629; // @[RegisterRouter.scala:87:24] wire out_wimask_629 = &_out_wimask_T_629; // @[RegisterRouter.scala:87:24] wire out_romask_629 = |_out_romask_T_629; // @[RegisterRouter.scala:87:24] wire out_womask_629 = &_out_womask_T_629; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_629 = out_rivalid_1_483 & out_rimask_629; // @[RegisterRouter.scala:87:24] wire _out_T_6322 = out_f_rivalid_629; // @[RegisterRouter.scala:87:24] wire out_f_roready_629 = out_roready_1_483 & out_romask_629; // @[RegisterRouter.scala:87:24] wire _out_T_6323 = out_f_roready_629; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_629 = out_wivalid_1_483 & out_wimask_629; // @[RegisterRouter.scala:87:24] wire out_f_woready_629 = out_woready_1_483 & out_womask_629; // @[RegisterRouter.scala:87:24] wire _out_T_6324 = ~out_rimask_629; // @[RegisterRouter.scala:87:24] wire _out_T_6325 = ~out_wimask_629; // @[RegisterRouter.scala:87:24] wire _out_T_6326 = ~out_romask_629; // @[RegisterRouter.scala:87:24] wire _out_T_6327 = ~out_womask_629; // @[RegisterRouter.scala:87:24] wire out_rimask_630 = |_out_rimask_T_630; // @[RegisterRouter.scala:87:24] wire out_wimask_630 = &_out_wimask_T_630; // @[RegisterRouter.scala:87:24] wire out_romask_630 = |_out_romask_T_630; // @[RegisterRouter.scala:87:24] wire out_womask_630 = &_out_womask_T_630; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_630 = out_rivalid_1_484 & out_rimask_630; // @[RegisterRouter.scala:87:24] wire _out_T_6331 = out_f_rivalid_630; // @[RegisterRouter.scala:87:24] wire out_f_roready_630 = out_roready_1_484 & out_romask_630; // @[RegisterRouter.scala:87:24] wire _out_T_6332 = out_f_roready_630; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_630 = out_wivalid_1_484 & out_wimask_630; // @[RegisterRouter.scala:87:24] wire out_f_woready_630 = out_woready_1_484 & out_womask_630; // @[RegisterRouter.scala:87:24] wire _out_T_6333 = ~out_rimask_630; // @[RegisterRouter.scala:87:24] wire _out_T_6334 = ~out_wimask_630; // @[RegisterRouter.scala:87:24] wire _out_T_6335 = ~out_romask_630; // @[RegisterRouter.scala:87:24] wire _out_T_6336 = ~out_womask_630; // @[RegisterRouter.scala:87:24] wire out_rimask_631 = |_out_rimask_T_631; // @[RegisterRouter.scala:87:24] wire out_wimask_631 = &_out_wimask_T_631; // @[RegisterRouter.scala:87:24] wire out_romask_631 = |_out_romask_T_631; // @[RegisterRouter.scala:87:24] wire out_womask_631 = &_out_womask_T_631; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_631 = out_rivalid_1_485 & out_rimask_631; // @[RegisterRouter.scala:87:24] wire _out_T_6340 = out_f_rivalid_631; // @[RegisterRouter.scala:87:24] wire out_f_roready_631 = out_roready_1_485 & out_romask_631; // @[RegisterRouter.scala:87:24] wire _out_T_6341 = out_f_roready_631; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_631 = out_wivalid_1_485 & out_wimask_631; // @[RegisterRouter.scala:87:24] wire out_f_woready_631 = out_woready_1_485 & out_womask_631; // @[RegisterRouter.scala:87:24] wire _out_T_6342 = ~out_rimask_631; // @[RegisterRouter.scala:87:24] wire _out_T_6343 = ~out_wimask_631; // @[RegisterRouter.scala:87:24] wire _out_T_6344 = ~out_romask_631; // @[RegisterRouter.scala:87:24] wire _out_T_6345 = ~out_womask_631; // @[RegisterRouter.scala:87:24] wire out_rimask_632 = |_out_rimask_T_632; // @[RegisterRouter.scala:87:24] wire out_wimask_632 = &_out_wimask_T_632; // @[RegisterRouter.scala:87:24] wire out_romask_632 = |_out_romask_T_632; // @[RegisterRouter.scala:87:24] wire out_womask_632 = &_out_womask_T_632; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_632 = out_rivalid_1_486 & out_rimask_632; // @[RegisterRouter.scala:87:24] wire _out_T_6349 = out_f_rivalid_632; // @[RegisterRouter.scala:87:24] wire out_f_roready_632 = out_roready_1_486 & out_romask_632; // @[RegisterRouter.scala:87:24] wire _out_T_6350 = out_f_roready_632; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_632 = out_wivalid_1_486 & out_wimask_632; // @[RegisterRouter.scala:87:24] wire out_f_woready_632 = out_woready_1_486 & out_womask_632; // @[RegisterRouter.scala:87:24] wire _out_T_6351 = ~out_rimask_632; // @[RegisterRouter.scala:87:24] wire _out_T_6352 = ~out_wimask_632; // @[RegisterRouter.scala:87:24] wire _out_T_6353 = ~out_romask_632; // @[RegisterRouter.scala:87:24] wire _out_T_6354 = ~out_womask_632; // @[RegisterRouter.scala:87:24] wire out_rimask_633 = |_out_rimask_T_633; // @[RegisterRouter.scala:87:24] wire out_wimask_633 = &_out_wimask_T_633; // @[RegisterRouter.scala:87:24] wire out_romask_633 = |_out_romask_T_633; // @[RegisterRouter.scala:87:24] wire out_womask_633 = &_out_womask_T_633; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_633 = out_rivalid_1_487 & out_rimask_633; // @[RegisterRouter.scala:87:24] wire _out_T_6358 = out_f_rivalid_633; // @[RegisterRouter.scala:87:24] wire out_f_roready_633 = out_roready_1_487 & out_romask_633; // @[RegisterRouter.scala:87:24] wire _out_T_6359 = out_f_roready_633; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_633 = out_wivalid_1_487 & out_wimask_633; // @[RegisterRouter.scala:87:24] wire out_f_woready_633 = out_woready_1_487 & out_womask_633; // @[RegisterRouter.scala:87:24] wire _out_T_6360 = ~out_rimask_633; // @[RegisterRouter.scala:87:24] wire _out_T_6361 = ~out_wimask_633; // @[RegisterRouter.scala:87:24] wire _out_T_6362 = ~out_romask_633; // @[RegisterRouter.scala:87:24] wire _out_T_6363 = ~out_womask_633; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6365 = _out_T_6364; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_536 = _out_T_6365; // @[RegisterRouter.scala:87:24] wire out_rimask_634 = |_out_rimask_T_634; // @[RegisterRouter.scala:87:24] wire out_wimask_634 = &_out_wimask_T_634; // @[RegisterRouter.scala:87:24] wire out_romask_634 = |_out_romask_T_634; // @[RegisterRouter.scala:87:24] wire out_womask_634 = &_out_womask_T_634; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_634 = out_rivalid_1_488 & out_rimask_634; // @[RegisterRouter.scala:87:24] wire _out_T_6367 = out_f_rivalid_634; // @[RegisterRouter.scala:87:24] wire out_f_roready_634 = out_roready_1_488 & out_romask_634; // @[RegisterRouter.scala:87:24] wire _out_T_6368 = out_f_roready_634; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_634 = out_wivalid_1_488 & out_wimask_634; // @[RegisterRouter.scala:87:24] wire out_f_woready_634 = out_woready_1_488 & out_womask_634; // @[RegisterRouter.scala:87:24] wire _out_T_6369 = ~out_rimask_634; // @[RegisterRouter.scala:87:24] wire _out_T_6370 = ~out_wimask_634; // @[RegisterRouter.scala:87:24] wire _out_T_6371 = ~out_romask_634; // @[RegisterRouter.scala:87:24] wire _out_T_6372 = ~out_womask_634; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_536 = {hi_618, flags_0_go, _out_prepend_T_536}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6373 = out_prepend_536; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6374 = _out_T_6373; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_537 = _out_T_6374; // @[RegisterRouter.scala:87:24] wire out_rimask_635 = |_out_rimask_T_635; // @[RegisterRouter.scala:87:24] wire out_wimask_635 = &_out_wimask_T_635; // @[RegisterRouter.scala:87:24] wire out_romask_635 = |_out_romask_T_635; // @[RegisterRouter.scala:87:24] wire out_womask_635 = &_out_womask_T_635; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_635 = out_rivalid_1_489 & out_rimask_635; // @[RegisterRouter.scala:87:24] wire _out_T_6376 = out_f_rivalid_635; // @[RegisterRouter.scala:87:24] wire out_f_roready_635 = out_roready_1_489 & out_romask_635; // @[RegisterRouter.scala:87:24] wire _out_T_6377 = out_f_roready_635; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_635 = out_wivalid_1_489 & out_wimask_635; // @[RegisterRouter.scala:87:24] wire out_f_woready_635 = out_woready_1_489 & out_womask_635; // @[RegisterRouter.scala:87:24] wire _out_T_6378 = ~out_rimask_635; // @[RegisterRouter.scala:87:24] wire _out_T_6379 = ~out_wimask_635; // @[RegisterRouter.scala:87:24] wire _out_T_6380 = ~out_romask_635; // @[RegisterRouter.scala:87:24] wire _out_T_6381 = ~out_womask_635; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_537 = {hi_619, flags_0_go, _out_prepend_T_537}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6382 = out_prepend_537; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6383 = _out_T_6382; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_538 = _out_T_6383; // @[RegisterRouter.scala:87:24] wire out_rimask_636 = |_out_rimask_T_636; // @[RegisterRouter.scala:87:24] wire out_wimask_636 = &_out_wimask_T_636; // @[RegisterRouter.scala:87:24] wire out_romask_636 = |_out_romask_T_636; // @[RegisterRouter.scala:87:24] wire out_womask_636 = &_out_womask_T_636; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_636 = out_rivalid_1_490 & out_rimask_636; // @[RegisterRouter.scala:87:24] wire _out_T_6385 = out_f_rivalid_636; // @[RegisterRouter.scala:87:24] wire out_f_roready_636 = out_roready_1_490 & out_romask_636; // @[RegisterRouter.scala:87:24] wire _out_T_6386 = out_f_roready_636; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_636 = out_wivalid_1_490 & out_wimask_636; // @[RegisterRouter.scala:87:24] wire out_f_woready_636 = out_woready_1_490 & out_womask_636; // @[RegisterRouter.scala:87:24] wire _out_T_6387 = ~out_rimask_636; // @[RegisterRouter.scala:87:24] wire _out_T_6388 = ~out_wimask_636; // @[RegisterRouter.scala:87:24] wire _out_T_6389 = ~out_romask_636; // @[RegisterRouter.scala:87:24] wire _out_T_6390 = ~out_womask_636; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_538 = {hi_620, flags_0_go, _out_prepend_T_538}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6391 = out_prepend_538; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6392 = _out_T_6391; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_539 = _out_T_6392; // @[RegisterRouter.scala:87:24] wire out_rimask_637 = |_out_rimask_T_637; // @[RegisterRouter.scala:87:24] wire out_wimask_637 = &_out_wimask_T_637; // @[RegisterRouter.scala:87:24] wire out_romask_637 = |_out_romask_T_637; // @[RegisterRouter.scala:87:24] wire out_womask_637 = &_out_womask_T_637; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_637 = out_rivalid_1_491 & out_rimask_637; // @[RegisterRouter.scala:87:24] wire _out_T_6394 = out_f_rivalid_637; // @[RegisterRouter.scala:87:24] wire out_f_roready_637 = out_roready_1_491 & out_romask_637; // @[RegisterRouter.scala:87:24] wire _out_T_6395 = out_f_roready_637; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_637 = out_wivalid_1_491 & out_wimask_637; // @[RegisterRouter.scala:87:24] wire out_f_woready_637 = out_woready_1_491 & out_womask_637; // @[RegisterRouter.scala:87:24] wire _out_T_6396 = ~out_rimask_637; // @[RegisterRouter.scala:87:24] wire _out_T_6397 = ~out_wimask_637; // @[RegisterRouter.scala:87:24] wire _out_T_6398 = ~out_romask_637; // @[RegisterRouter.scala:87:24] wire _out_T_6399 = ~out_womask_637; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_539 = {hi_621, flags_0_go, _out_prepend_T_539}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6400 = out_prepend_539; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6401 = _out_T_6400; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_540 = _out_T_6401; // @[RegisterRouter.scala:87:24] wire out_rimask_638 = |_out_rimask_T_638; // @[RegisterRouter.scala:87:24] wire out_wimask_638 = &_out_wimask_T_638; // @[RegisterRouter.scala:87:24] wire out_romask_638 = |_out_romask_T_638; // @[RegisterRouter.scala:87:24] wire out_womask_638 = &_out_womask_T_638; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_638 = out_rivalid_1_492 & out_rimask_638; // @[RegisterRouter.scala:87:24] wire _out_T_6403 = out_f_rivalid_638; // @[RegisterRouter.scala:87:24] wire out_f_roready_638 = out_roready_1_492 & out_romask_638; // @[RegisterRouter.scala:87:24] wire _out_T_6404 = out_f_roready_638; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_638 = out_wivalid_1_492 & out_wimask_638; // @[RegisterRouter.scala:87:24] wire out_f_woready_638 = out_woready_1_492 & out_womask_638; // @[RegisterRouter.scala:87:24] wire _out_T_6405 = ~out_rimask_638; // @[RegisterRouter.scala:87:24] wire _out_T_6406 = ~out_wimask_638; // @[RegisterRouter.scala:87:24] wire _out_T_6407 = ~out_romask_638; // @[RegisterRouter.scala:87:24] wire _out_T_6408 = ~out_womask_638; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_540 = {hi_622, flags_0_go, _out_prepend_T_540}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6409 = out_prepend_540; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6410 = _out_T_6409; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_541 = _out_T_6410; // @[RegisterRouter.scala:87:24] wire out_rimask_639 = |_out_rimask_T_639; // @[RegisterRouter.scala:87:24] wire out_wimask_639 = &_out_wimask_T_639; // @[RegisterRouter.scala:87:24] wire out_romask_639 = |_out_romask_T_639; // @[RegisterRouter.scala:87:24] wire out_womask_639 = &_out_womask_T_639; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_639 = out_rivalid_1_493 & out_rimask_639; // @[RegisterRouter.scala:87:24] wire _out_T_6412 = out_f_rivalid_639; // @[RegisterRouter.scala:87:24] wire out_f_roready_639 = out_roready_1_493 & out_romask_639; // @[RegisterRouter.scala:87:24] wire _out_T_6413 = out_f_roready_639; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_639 = out_wivalid_1_493 & out_wimask_639; // @[RegisterRouter.scala:87:24] wire out_f_woready_639 = out_woready_1_493 & out_womask_639; // @[RegisterRouter.scala:87:24] wire _out_T_6414 = ~out_rimask_639; // @[RegisterRouter.scala:87:24] wire _out_T_6415 = ~out_wimask_639; // @[RegisterRouter.scala:87:24] wire _out_T_6416 = ~out_romask_639; // @[RegisterRouter.scala:87:24] wire _out_T_6417 = ~out_womask_639; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_541 = {hi_623, flags_0_go, _out_prepend_T_541}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6418 = out_prepend_541; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6419 = _out_T_6418; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_542 = _out_T_6419; // @[RegisterRouter.scala:87:24] wire out_rimask_640 = |_out_rimask_T_640; // @[RegisterRouter.scala:87:24] wire out_wimask_640 = &_out_wimask_T_640; // @[RegisterRouter.scala:87:24] wire out_romask_640 = |_out_romask_T_640; // @[RegisterRouter.scala:87:24] wire out_womask_640 = &_out_womask_T_640; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_640 = out_rivalid_1_494 & out_rimask_640; // @[RegisterRouter.scala:87:24] wire _out_T_6421 = out_f_rivalid_640; // @[RegisterRouter.scala:87:24] wire out_f_roready_640 = out_roready_1_494 & out_romask_640; // @[RegisterRouter.scala:87:24] wire _out_T_6422 = out_f_roready_640; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_640 = out_wivalid_1_494 & out_wimask_640; // @[RegisterRouter.scala:87:24] wire out_f_woready_640 = out_woready_1_494 & out_womask_640; // @[RegisterRouter.scala:87:24] wire _out_T_6423 = ~out_rimask_640; // @[RegisterRouter.scala:87:24] wire _out_T_6424 = ~out_wimask_640; // @[RegisterRouter.scala:87:24] wire _out_T_6425 = ~out_romask_640; // @[RegisterRouter.scala:87:24] wire _out_T_6426 = ~out_womask_640; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_542 = {hi_624, flags_0_go, _out_prepend_T_542}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6427 = out_prepend_542; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6428 = _out_T_6427; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_205 = _out_T_6428; // @[MuxLiteral.scala:49:48] wire out_rimask_641 = |_out_rimask_T_641; // @[RegisterRouter.scala:87:24] wire out_wimask_641 = &_out_wimask_T_641; // @[RegisterRouter.scala:87:24] wire out_romask_641 = |_out_romask_T_641; // @[RegisterRouter.scala:87:24] wire out_womask_641 = &_out_womask_T_641; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_641 = out_rivalid_1_495 & out_rimask_641; // @[RegisterRouter.scala:87:24] wire _out_T_6430 = out_f_rivalid_641; // @[RegisterRouter.scala:87:24] wire out_f_roready_641 = out_roready_1_495 & out_romask_641; // @[RegisterRouter.scala:87:24] wire _out_T_6431 = out_f_roready_641; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_641 = out_wivalid_1_495 & out_wimask_641; // @[RegisterRouter.scala:87:24] wire out_f_woready_641 = out_woready_1_495 & out_womask_641; // @[RegisterRouter.scala:87:24] wire _out_T_6432 = ~out_rimask_641; // @[RegisterRouter.scala:87:24] wire _out_T_6433 = ~out_wimask_641; // @[RegisterRouter.scala:87:24] wire _out_T_6434 = ~out_romask_641; // @[RegisterRouter.scala:87:24] wire _out_T_6435 = ~out_womask_641; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6437 = _out_T_6436; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_543 = _out_T_6437; // @[RegisterRouter.scala:87:24] wire out_rimask_642 = |_out_rimask_T_642; // @[RegisterRouter.scala:87:24] wire out_wimask_642 = &_out_wimask_T_642; // @[RegisterRouter.scala:87:24] wire out_romask_642 = |_out_romask_T_642; // @[RegisterRouter.scala:87:24] wire out_womask_642 = &_out_womask_T_642; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_642 = out_rivalid_1_496 & out_rimask_642; // @[RegisterRouter.scala:87:24] wire _out_T_6439 = out_f_rivalid_642; // @[RegisterRouter.scala:87:24] wire out_f_roready_642 = out_roready_1_496 & out_romask_642; // @[RegisterRouter.scala:87:24] wire _out_T_6440 = out_f_roready_642; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_642 = out_wivalid_1_496 & out_wimask_642; // @[RegisterRouter.scala:87:24] wire out_f_woready_642 = out_woready_1_496 & out_womask_642; // @[RegisterRouter.scala:87:24] wire _out_T_6441 = ~out_rimask_642; // @[RegisterRouter.scala:87:24] wire _out_T_6442 = ~out_wimask_642; // @[RegisterRouter.scala:87:24] wire _out_T_6443 = ~out_romask_642; // @[RegisterRouter.scala:87:24] wire _out_T_6444 = ~out_womask_642; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_543 = {hi_2, flags_0_go, _out_prepend_T_543}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6445 = out_prepend_543; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6446 = _out_T_6445; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_544 = _out_T_6446; // @[RegisterRouter.scala:87:24] wire out_rimask_643 = |_out_rimask_T_643; // @[RegisterRouter.scala:87:24] wire out_wimask_643 = &_out_wimask_T_643; // @[RegisterRouter.scala:87:24] wire out_romask_643 = |_out_romask_T_643; // @[RegisterRouter.scala:87:24] wire out_womask_643 = &_out_womask_T_643; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_643 = out_rivalid_1_497 & out_rimask_643; // @[RegisterRouter.scala:87:24] wire _out_T_6448 = out_f_rivalid_643; // @[RegisterRouter.scala:87:24] wire out_f_roready_643 = out_roready_1_497 & out_romask_643; // @[RegisterRouter.scala:87:24] wire _out_T_6449 = out_f_roready_643; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_643 = out_wivalid_1_497 & out_wimask_643; // @[RegisterRouter.scala:87:24] wire out_f_woready_643 = out_woready_1_497 & out_womask_643; // @[RegisterRouter.scala:87:24] wire _out_T_6450 = ~out_rimask_643; // @[RegisterRouter.scala:87:24] wire _out_T_6451 = ~out_wimask_643; // @[RegisterRouter.scala:87:24] wire _out_T_6452 = ~out_romask_643; // @[RegisterRouter.scala:87:24] wire _out_T_6453 = ~out_womask_643; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_544 = {hi_3, flags_0_go, _out_prepend_T_544}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6454 = out_prepend_544; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6455 = _out_T_6454; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_545 = _out_T_6455; // @[RegisterRouter.scala:87:24] wire out_rimask_644 = |_out_rimask_T_644; // @[RegisterRouter.scala:87:24] wire out_wimask_644 = &_out_wimask_T_644; // @[RegisterRouter.scala:87:24] wire out_romask_644 = |_out_romask_T_644; // @[RegisterRouter.scala:87:24] wire out_womask_644 = &_out_womask_T_644; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_644 = out_rivalid_1_498 & out_rimask_644; // @[RegisterRouter.scala:87:24] wire _out_T_6457 = out_f_rivalid_644; // @[RegisterRouter.scala:87:24] wire out_f_roready_644 = out_roready_1_498 & out_romask_644; // @[RegisterRouter.scala:87:24] wire _out_T_6458 = out_f_roready_644; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_644 = out_wivalid_1_498 & out_wimask_644; // @[RegisterRouter.scala:87:24] wire out_f_woready_644 = out_woready_1_498 & out_womask_644; // @[RegisterRouter.scala:87:24] wire _out_T_6459 = ~out_rimask_644; // @[RegisterRouter.scala:87:24] wire _out_T_6460 = ~out_wimask_644; // @[RegisterRouter.scala:87:24] wire _out_T_6461 = ~out_romask_644; // @[RegisterRouter.scala:87:24] wire _out_T_6462 = ~out_womask_644; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_545 = {hi_4, flags_0_go, _out_prepend_T_545}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6463 = out_prepend_545; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6464 = _out_T_6463; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_546 = _out_T_6464; // @[RegisterRouter.scala:87:24] wire out_rimask_645 = |_out_rimask_T_645; // @[RegisterRouter.scala:87:24] wire out_wimask_645 = &_out_wimask_T_645; // @[RegisterRouter.scala:87:24] wire out_romask_645 = |_out_romask_T_645; // @[RegisterRouter.scala:87:24] wire out_womask_645 = &_out_womask_T_645; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_645 = out_rivalid_1_499 & out_rimask_645; // @[RegisterRouter.scala:87:24] wire _out_T_6466 = out_f_rivalid_645; // @[RegisterRouter.scala:87:24] wire out_f_roready_645 = out_roready_1_499 & out_romask_645; // @[RegisterRouter.scala:87:24] wire _out_T_6467 = out_f_roready_645; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_645 = out_wivalid_1_499 & out_wimask_645; // @[RegisterRouter.scala:87:24] wire out_f_woready_645 = out_woready_1_499 & out_womask_645; // @[RegisterRouter.scala:87:24] wire _out_T_6468 = ~out_rimask_645; // @[RegisterRouter.scala:87:24] wire _out_T_6469 = ~out_wimask_645; // @[RegisterRouter.scala:87:24] wire _out_T_6470 = ~out_romask_645; // @[RegisterRouter.scala:87:24] wire _out_T_6471 = ~out_womask_645; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_546 = {hi_5, flags_0_go, _out_prepend_T_546}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6472 = out_prepend_546; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6473 = _out_T_6472; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_547 = _out_T_6473; // @[RegisterRouter.scala:87:24] wire out_rimask_646 = |_out_rimask_T_646; // @[RegisterRouter.scala:87:24] wire out_wimask_646 = &_out_wimask_T_646; // @[RegisterRouter.scala:87:24] wire out_romask_646 = |_out_romask_T_646; // @[RegisterRouter.scala:87:24] wire out_womask_646 = &_out_womask_T_646; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_646 = out_rivalid_1_500 & out_rimask_646; // @[RegisterRouter.scala:87:24] wire _out_T_6475 = out_f_rivalid_646; // @[RegisterRouter.scala:87:24] wire out_f_roready_646 = out_roready_1_500 & out_romask_646; // @[RegisterRouter.scala:87:24] wire _out_T_6476 = out_f_roready_646; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_646 = out_wivalid_1_500 & out_wimask_646; // @[RegisterRouter.scala:87:24] wire out_f_woready_646 = out_woready_1_500 & out_womask_646; // @[RegisterRouter.scala:87:24] wire _out_T_6477 = ~out_rimask_646; // @[RegisterRouter.scala:87:24] wire _out_T_6478 = ~out_wimask_646; // @[RegisterRouter.scala:87:24] wire _out_T_6479 = ~out_romask_646; // @[RegisterRouter.scala:87:24] wire _out_T_6480 = ~out_womask_646; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_547 = {hi_6, flags_0_go, _out_prepend_T_547}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6481 = out_prepend_547; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6482 = _out_T_6481; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_548 = _out_T_6482; // @[RegisterRouter.scala:87:24] wire out_rimask_647 = |_out_rimask_T_647; // @[RegisterRouter.scala:87:24] wire out_wimask_647 = &_out_wimask_T_647; // @[RegisterRouter.scala:87:24] wire out_romask_647 = |_out_romask_T_647; // @[RegisterRouter.scala:87:24] wire out_womask_647 = &_out_womask_T_647; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_647 = out_rivalid_1_501 & out_rimask_647; // @[RegisterRouter.scala:87:24] wire _out_T_6484 = out_f_rivalid_647; // @[RegisterRouter.scala:87:24] wire out_f_roready_647 = out_roready_1_501 & out_romask_647; // @[RegisterRouter.scala:87:24] wire _out_T_6485 = out_f_roready_647; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_647 = out_wivalid_1_501 & out_wimask_647; // @[RegisterRouter.scala:87:24] wire out_f_woready_647 = out_woready_1_501 & out_womask_647; // @[RegisterRouter.scala:87:24] wire _out_T_6486 = ~out_rimask_647; // @[RegisterRouter.scala:87:24] wire _out_T_6487 = ~out_wimask_647; // @[RegisterRouter.scala:87:24] wire _out_T_6488 = ~out_romask_647; // @[RegisterRouter.scala:87:24] wire _out_T_6489 = ~out_womask_647; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_548 = {hi_7, flags_0_go, _out_prepend_T_548}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6490 = out_prepend_548; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6491 = _out_T_6490; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_549 = _out_T_6491; // @[RegisterRouter.scala:87:24] wire out_rimask_648 = |_out_rimask_T_648; // @[RegisterRouter.scala:87:24] wire out_wimask_648 = &_out_wimask_T_648; // @[RegisterRouter.scala:87:24] wire out_romask_648 = |_out_romask_T_648; // @[RegisterRouter.scala:87:24] wire out_womask_648 = &_out_womask_T_648; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_648 = out_rivalid_1_502 & out_rimask_648; // @[RegisterRouter.scala:87:24] wire _out_T_6493 = out_f_rivalid_648; // @[RegisterRouter.scala:87:24] wire out_f_roready_648 = out_roready_1_502 & out_romask_648; // @[RegisterRouter.scala:87:24] wire _out_T_6494 = out_f_roready_648; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_648 = out_wivalid_1_502 & out_wimask_648; // @[RegisterRouter.scala:87:24] wire out_f_woready_648 = out_woready_1_502 & out_womask_648; // @[RegisterRouter.scala:87:24] wire _out_T_6495 = ~out_rimask_648; // @[RegisterRouter.scala:87:24] wire _out_T_6496 = ~out_wimask_648; // @[RegisterRouter.scala:87:24] wire _out_T_6497 = ~out_romask_648; // @[RegisterRouter.scala:87:24] wire _out_T_6498 = ~out_womask_648; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_549 = {hi_8, flags_0_go, _out_prepend_T_549}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6499 = out_prepend_549; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6500 = _out_T_6499; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_128 = _out_T_6500; // @[MuxLiteral.scala:49:48] wire out_rimask_649 = |_out_rimask_T_649; // @[RegisterRouter.scala:87:24] wire out_wimask_649 = &_out_wimask_T_649; // @[RegisterRouter.scala:87:24] wire out_romask_649 = |_out_romask_T_649; // @[RegisterRouter.scala:87:24] wire out_womask_649 = &_out_womask_T_649; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_649 = out_rivalid_1_503 & out_rimask_649; // @[RegisterRouter.scala:87:24] wire _out_T_6502 = out_f_rivalid_649; // @[RegisterRouter.scala:87:24] wire out_f_roready_649 = out_roready_1_503 & out_romask_649; // @[RegisterRouter.scala:87:24] wire _out_T_6503 = out_f_roready_649; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_649 = out_wivalid_1_503 & out_wimask_649; // @[RegisterRouter.scala:87:24] wire out_f_woready_649 = out_woready_1_503 & out_womask_649; // @[RegisterRouter.scala:87:24] wire _out_T_6504 = ~out_rimask_649; // @[RegisterRouter.scala:87:24] wire _out_T_6505 = ~out_wimask_649; // @[RegisterRouter.scala:87:24] wire _out_T_6506 = ~out_romask_649; // @[RegisterRouter.scala:87:24] wire _out_T_6507 = ~out_womask_649; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6509 = _out_T_6508; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_550 = _out_T_6509; // @[RegisterRouter.scala:87:24] wire out_rimask_650 = |_out_rimask_T_650; // @[RegisterRouter.scala:87:24] wire out_wimask_650 = &_out_wimask_T_650; // @[RegisterRouter.scala:87:24] wire out_romask_650 = |_out_romask_T_650; // @[RegisterRouter.scala:87:24] wire out_womask_650 = &_out_womask_T_650; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_650 = out_rivalid_1_504 & out_rimask_650; // @[RegisterRouter.scala:87:24] wire _out_T_6511 = out_f_rivalid_650; // @[RegisterRouter.scala:87:24] wire out_f_roready_650 = out_roready_1_504 & out_romask_650; // @[RegisterRouter.scala:87:24] wire _out_T_6512 = out_f_roready_650; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_650 = out_wivalid_1_504 & out_wimask_650; // @[RegisterRouter.scala:87:24] wire out_f_woready_650 = out_woready_1_504 & out_womask_650; // @[RegisterRouter.scala:87:24] wire _out_T_6513 = ~out_rimask_650; // @[RegisterRouter.scala:87:24] wire _out_T_6514 = ~out_wimask_650; // @[RegisterRouter.scala:87:24] wire _out_T_6515 = ~out_romask_650; // @[RegisterRouter.scala:87:24] wire _out_T_6516 = ~out_womask_650; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_550 = {hi_874, flags_0_go, _out_prepend_T_550}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6517 = out_prepend_550; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6518 = _out_T_6517; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_551 = _out_T_6518; // @[RegisterRouter.scala:87:24] wire out_rimask_651 = |_out_rimask_T_651; // @[RegisterRouter.scala:87:24] wire out_wimask_651 = &_out_wimask_T_651; // @[RegisterRouter.scala:87:24] wire out_romask_651 = |_out_romask_T_651; // @[RegisterRouter.scala:87:24] wire out_womask_651 = &_out_womask_T_651; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_651 = out_rivalid_1_505 & out_rimask_651; // @[RegisterRouter.scala:87:24] wire _out_T_6520 = out_f_rivalid_651; // @[RegisterRouter.scala:87:24] wire out_f_roready_651 = out_roready_1_505 & out_romask_651; // @[RegisterRouter.scala:87:24] wire _out_T_6521 = out_f_roready_651; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_651 = out_wivalid_1_505 & out_wimask_651; // @[RegisterRouter.scala:87:24] wire out_f_woready_651 = out_woready_1_505 & out_womask_651; // @[RegisterRouter.scala:87:24] wire _out_T_6522 = ~out_rimask_651; // @[RegisterRouter.scala:87:24] wire _out_T_6523 = ~out_wimask_651; // @[RegisterRouter.scala:87:24] wire _out_T_6524 = ~out_romask_651; // @[RegisterRouter.scala:87:24] wire _out_T_6525 = ~out_womask_651; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_551 = {hi_875, flags_0_go, _out_prepend_T_551}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6526 = out_prepend_551; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6527 = _out_T_6526; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_552 = _out_T_6527; // @[RegisterRouter.scala:87:24] wire out_rimask_652 = |_out_rimask_T_652; // @[RegisterRouter.scala:87:24] wire out_wimask_652 = &_out_wimask_T_652; // @[RegisterRouter.scala:87:24] wire out_romask_652 = |_out_romask_T_652; // @[RegisterRouter.scala:87:24] wire out_womask_652 = &_out_womask_T_652; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_652 = out_rivalid_1_506 & out_rimask_652; // @[RegisterRouter.scala:87:24] wire _out_T_6529 = out_f_rivalid_652; // @[RegisterRouter.scala:87:24] wire out_f_roready_652 = out_roready_1_506 & out_romask_652; // @[RegisterRouter.scala:87:24] wire _out_T_6530 = out_f_roready_652; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_652 = out_wivalid_1_506 & out_wimask_652; // @[RegisterRouter.scala:87:24] wire out_f_woready_652 = out_woready_1_506 & out_womask_652; // @[RegisterRouter.scala:87:24] wire _out_T_6531 = ~out_rimask_652; // @[RegisterRouter.scala:87:24] wire _out_T_6532 = ~out_wimask_652; // @[RegisterRouter.scala:87:24] wire _out_T_6533 = ~out_romask_652; // @[RegisterRouter.scala:87:24] wire _out_T_6534 = ~out_womask_652; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_552 = {hi_876, flags_0_go, _out_prepend_T_552}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6535 = out_prepend_552; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6536 = _out_T_6535; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_553 = _out_T_6536; // @[RegisterRouter.scala:87:24] wire out_rimask_653 = |_out_rimask_T_653; // @[RegisterRouter.scala:87:24] wire out_wimask_653 = &_out_wimask_T_653; // @[RegisterRouter.scala:87:24] wire out_romask_653 = |_out_romask_T_653; // @[RegisterRouter.scala:87:24] wire out_womask_653 = &_out_womask_T_653; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_653 = out_rivalid_1_507 & out_rimask_653; // @[RegisterRouter.scala:87:24] wire _out_T_6538 = out_f_rivalid_653; // @[RegisterRouter.scala:87:24] wire out_f_roready_653 = out_roready_1_507 & out_romask_653; // @[RegisterRouter.scala:87:24] wire _out_T_6539 = out_f_roready_653; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_653 = out_wivalid_1_507 & out_wimask_653; // @[RegisterRouter.scala:87:24] wire out_f_woready_653 = out_woready_1_507 & out_womask_653; // @[RegisterRouter.scala:87:24] wire _out_T_6540 = ~out_rimask_653; // @[RegisterRouter.scala:87:24] wire _out_T_6541 = ~out_wimask_653; // @[RegisterRouter.scala:87:24] wire _out_T_6542 = ~out_romask_653; // @[RegisterRouter.scala:87:24] wire _out_T_6543 = ~out_womask_653; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_553 = {hi_877, flags_0_go, _out_prepend_T_553}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6544 = out_prepend_553; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6545 = _out_T_6544; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_554 = _out_T_6545; // @[RegisterRouter.scala:87:24] wire out_rimask_654 = |_out_rimask_T_654; // @[RegisterRouter.scala:87:24] wire out_wimask_654 = &_out_wimask_T_654; // @[RegisterRouter.scala:87:24] wire out_romask_654 = |_out_romask_T_654; // @[RegisterRouter.scala:87:24] wire out_womask_654 = &_out_womask_T_654; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_654 = out_rivalid_1_508 & out_rimask_654; // @[RegisterRouter.scala:87:24] wire _out_T_6547 = out_f_rivalid_654; // @[RegisterRouter.scala:87:24] wire out_f_roready_654 = out_roready_1_508 & out_romask_654; // @[RegisterRouter.scala:87:24] wire _out_T_6548 = out_f_roready_654; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_654 = out_wivalid_1_508 & out_wimask_654; // @[RegisterRouter.scala:87:24] wire out_f_woready_654 = out_woready_1_508 & out_womask_654; // @[RegisterRouter.scala:87:24] wire _out_T_6549 = ~out_rimask_654; // @[RegisterRouter.scala:87:24] wire _out_T_6550 = ~out_wimask_654; // @[RegisterRouter.scala:87:24] wire _out_T_6551 = ~out_romask_654; // @[RegisterRouter.scala:87:24] wire _out_T_6552 = ~out_womask_654; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_554 = {hi_878, flags_0_go, _out_prepend_T_554}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6553 = out_prepend_554; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6554 = _out_T_6553; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_555 = _out_T_6554; // @[RegisterRouter.scala:87:24] wire out_rimask_655 = |_out_rimask_T_655; // @[RegisterRouter.scala:87:24] wire out_wimask_655 = &_out_wimask_T_655; // @[RegisterRouter.scala:87:24] wire out_romask_655 = |_out_romask_T_655; // @[RegisterRouter.scala:87:24] wire out_womask_655 = &_out_womask_T_655; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_655 = out_rivalid_1_509 & out_rimask_655; // @[RegisterRouter.scala:87:24] wire _out_T_6556 = out_f_rivalid_655; // @[RegisterRouter.scala:87:24] wire out_f_roready_655 = out_roready_1_509 & out_romask_655; // @[RegisterRouter.scala:87:24] wire _out_T_6557 = out_f_roready_655; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_655 = out_wivalid_1_509 & out_wimask_655; // @[RegisterRouter.scala:87:24] wire out_f_woready_655 = out_woready_1_509 & out_womask_655; // @[RegisterRouter.scala:87:24] wire _out_T_6558 = ~out_rimask_655; // @[RegisterRouter.scala:87:24] wire _out_T_6559 = ~out_wimask_655; // @[RegisterRouter.scala:87:24] wire _out_T_6560 = ~out_romask_655; // @[RegisterRouter.scala:87:24] wire _out_T_6561 = ~out_womask_655; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_555 = {hi_879, flags_0_go, _out_prepend_T_555}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6562 = out_prepend_555; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6563 = _out_T_6562; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_556 = _out_T_6563; // @[RegisterRouter.scala:87:24] wire out_rimask_656 = |_out_rimask_T_656; // @[RegisterRouter.scala:87:24] wire out_wimask_656 = &_out_wimask_T_656; // @[RegisterRouter.scala:87:24] wire out_romask_656 = |_out_romask_T_656; // @[RegisterRouter.scala:87:24] wire out_womask_656 = &_out_womask_T_656; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_656 = out_rivalid_1_510 & out_rimask_656; // @[RegisterRouter.scala:87:24] wire _out_T_6565 = out_f_rivalid_656; // @[RegisterRouter.scala:87:24] wire out_f_roready_656 = out_roready_1_510 & out_romask_656; // @[RegisterRouter.scala:87:24] wire _out_T_6566 = out_f_roready_656; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_656 = out_wivalid_1_510 & out_wimask_656; // @[RegisterRouter.scala:87:24] wire out_f_woready_656 = out_woready_1_510 & out_womask_656; // @[RegisterRouter.scala:87:24] wire _out_T_6567 = ~out_rimask_656; // @[RegisterRouter.scala:87:24] wire _out_T_6568 = ~out_wimask_656; // @[RegisterRouter.scala:87:24] wire _out_T_6569 = ~out_romask_656; // @[RegisterRouter.scala:87:24] wire _out_T_6570 = ~out_womask_656; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_556 = {hi_880, flags_0_go, _out_prepend_T_556}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6571 = out_prepend_556; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6572 = _out_T_6571; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_237 = _out_T_6572; // @[MuxLiteral.scala:49:48] wire out_rimask_657 = |_out_rimask_T_657; // @[RegisterRouter.scala:87:24] wire out_wimask_657 = &_out_wimask_T_657; // @[RegisterRouter.scala:87:24] wire out_romask_657 = |_out_romask_T_657; // @[RegisterRouter.scala:87:24] wire out_womask_657 = &_out_womask_T_657; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_657 = out_rivalid_1_511 & out_rimask_657; // @[RegisterRouter.scala:87:24] wire _out_T_6574 = out_f_rivalid_657; // @[RegisterRouter.scala:87:24] wire out_f_roready_657 = out_roready_1_511 & out_romask_657; // @[RegisterRouter.scala:87:24] wire _out_T_6575 = out_f_roready_657; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_657 = out_wivalid_1_511 & out_wimask_657; // @[RegisterRouter.scala:87:24] wire _out_T_6576 = out_f_wivalid_657; // @[RegisterRouter.scala:87:24] wire out_f_woready_657 = out_woready_1_511 & out_womask_657; // @[RegisterRouter.scala:87:24] wire _out_T_6577 = out_f_woready_657; // @[RegisterRouter.scala:87:24] wire _out_T_6578 = ~out_rimask_657; // @[RegisterRouter.scala:87:24] wire _out_T_6579 = ~out_wimask_657; // @[RegisterRouter.scala:87:24] wire _out_T_6580 = ~out_romask_657; // @[RegisterRouter.scala:87:24] wire _out_T_6581 = ~out_womask_657; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6583 = _out_T_6582; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_557 = _out_T_6583; // @[RegisterRouter.scala:87:24] wire out_rimask_658 = |_out_rimask_T_658; // @[RegisterRouter.scala:87:24] wire out_wimask_658 = &_out_wimask_T_658; // @[RegisterRouter.scala:87:24] wire out_romask_658 = |_out_romask_T_658; // @[RegisterRouter.scala:87:24] wire out_womask_658 = &_out_womask_T_658; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_658 = out_rivalid_1_512 & out_rimask_658; // @[RegisterRouter.scala:87:24] wire _out_T_6585 = out_f_rivalid_658; // @[RegisterRouter.scala:87:24] wire out_f_roready_658 = out_roready_1_512 & out_romask_658; // @[RegisterRouter.scala:87:24] wire _out_T_6586 = out_f_roready_658; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_658 = out_wivalid_1_512 & out_wimask_658; // @[RegisterRouter.scala:87:24] wire _out_T_6587 = out_f_wivalid_658; // @[RegisterRouter.scala:87:24] wire out_f_woready_658 = out_woready_1_512 & out_womask_658; // @[RegisterRouter.scala:87:24] wire _out_T_6588 = out_f_woready_658; // @[RegisterRouter.scala:87:24] wire _out_T_6589 = ~out_rimask_658; // @[RegisterRouter.scala:87:24] wire _out_T_6590 = ~out_wimask_658; // @[RegisterRouter.scala:87:24] wire _out_T_6591 = ~out_romask_658; // @[RegisterRouter.scala:87:24] wire _out_T_6592 = ~out_womask_658; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_557 = {programBufferMem_9, _out_prepend_T_557}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6593 = out_prepend_557; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6594 = _out_T_6593; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_558 = _out_T_6594; // @[RegisterRouter.scala:87:24] wire out_rimask_659 = |_out_rimask_T_659; // @[RegisterRouter.scala:87:24] wire out_wimask_659 = &_out_wimask_T_659; // @[RegisterRouter.scala:87:24] wire out_romask_659 = |_out_romask_T_659; // @[RegisterRouter.scala:87:24] wire out_womask_659 = &_out_womask_T_659; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_659 = out_rivalid_1_513 & out_rimask_659; // @[RegisterRouter.scala:87:24] wire _out_T_6596 = out_f_rivalid_659; // @[RegisterRouter.scala:87:24] wire out_f_roready_659 = out_roready_1_513 & out_romask_659; // @[RegisterRouter.scala:87:24] wire _out_T_6597 = out_f_roready_659; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_659 = out_wivalid_1_513 & out_wimask_659; // @[RegisterRouter.scala:87:24] wire _out_T_6598 = out_f_wivalid_659; // @[RegisterRouter.scala:87:24] wire out_f_woready_659 = out_woready_1_513 & out_womask_659; // @[RegisterRouter.scala:87:24] wire _out_T_6599 = out_f_woready_659; // @[RegisterRouter.scala:87:24] wire _out_T_6600 = ~out_rimask_659; // @[RegisterRouter.scala:87:24] wire _out_T_6601 = ~out_wimask_659; // @[RegisterRouter.scala:87:24] wire _out_T_6602 = ~out_romask_659; // @[RegisterRouter.scala:87:24] wire _out_T_6603 = ~out_womask_659; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_558 = {programBufferMem_10, _out_prepend_T_558}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6604 = out_prepend_558; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6605 = _out_T_6604; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_559 = _out_T_6605; // @[RegisterRouter.scala:87:24] wire out_rimask_660 = |_out_rimask_T_660; // @[RegisterRouter.scala:87:24] wire out_wimask_660 = &_out_wimask_T_660; // @[RegisterRouter.scala:87:24] wire out_romask_660 = |_out_romask_T_660; // @[RegisterRouter.scala:87:24] wire out_womask_660 = &_out_womask_T_660; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_660 = out_rivalid_1_514 & out_rimask_660; // @[RegisterRouter.scala:87:24] wire _out_T_6607 = out_f_rivalid_660; // @[RegisterRouter.scala:87:24] wire out_f_roready_660 = out_roready_1_514 & out_romask_660; // @[RegisterRouter.scala:87:24] wire _out_T_6608 = out_f_roready_660; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_660 = out_wivalid_1_514 & out_wimask_660; // @[RegisterRouter.scala:87:24] wire _out_T_6609 = out_f_wivalid_660; // @[RegisterRouter.scala:87:24] wire out_f_woready_660 = out_woready_1_514 & out_womask_660; // @[RegisterRouter.scala:87:24] wire _out_T_6610 = out_f_woready_660; // @[RegisterRouter.scala:87:24] wire _out_T_6611 = ~out_rimask_660; // @[RegisterRouter.scala:87:24] wire _out_T_6612 = ~out_wimask_660; // @[RegisterRouter.scala:87:24] wire _out_T_6613 = ~out_romask_660; // @[RegisterRouter.scala:87:24] wire _out_T_6614 = ~out_womask_660; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_559 = {programBufferMem_11, _out_prepend_T_559}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6615 = out_prepend_559; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6616 = _out_T_6615; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_560 = _out_T_6616; // @[RegisterRouter.scala:87:24] wire out_rimask_661 = |_out_rimask_T_661; // @[RegisterRouter.scala:87:24] wire out_wimask_661 = &_out_wimask_T_661; // @[RegisterRouter.scala:87:24] wire out_romask_661 = |_out_romask_T_661; // @[RegisterRouter.scala:87:24] wire out_womask_661 = &_out_womask_T_661; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_661 = out_rivalid_1_515 & out_rimask_661; // @[RegisterRouter.scala:87:24] wire _out_T_6618 = out_f_rivalid_661; // @[RegisterRouter.scala:87:24] wire out_f_roready_661 = out_roready_1_515 & out_romask_661; // @[RegisterRouter.scala:87:24] wire _out_T_6619 = out_f_roready_661; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_661 = out_wivalid_1_515 & out_wimask_661; // @[RegisterRouter.scala:87:24] wire _out_T_6620 = out_f_wivalid_661; // @[RegisterRouter.scala:87:24] wire out_f_woready_661 = out_woready_1_515 & out_womask_661; // @[RegisterRouter.scala:87:24] wire _out_T_6621 = out_f_woready_661; // @[RegisterRouter.scala:87:24] wire _out_T_6622 = ~out_rimask_661; // @[RegisterRouter.scala:87:24] wire _out_T_6623 = ~out_wimask_661; // @[RegisterRouter.scala:87:24] wire _out_T_6624 = ~out_romask_661; // @[RegisterRouter.scala:87:24] wire _out_T_6625 = ~out_womask_661; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_560 = {programBufferMem_12, _out_prepend_T_560}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6626 = out_prepend_560; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6627 = _out_T_6626; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_561 = _out_T_6627; // @[RegisterRouter.scala:87:24] wire out_rimask_662 = |_out_rimask_T_662; // @[RegisterRouter.scala:87:24] wire out_wimask_662 = &_out_wimask_T_662; // @[RegisterRouter.scala:87:24] wire out_romask_662 = |_out_romask_T_662; // @[RegisterRouter.scala:87:24] wire out_womask_662 = &_out_womask_T_662; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_662 = out_rivalid_1_516 & out_rimask_662; // @[RegisterRouter.scala:87:24] wire _out_T_6629 = out_f_rivalid_662; // @[RegisterRouter.scala:87:24] wire out_f_roready_662 = out_roready_1_516 & out_romask_662; // @[RegisterRouter.scala:87:24] wire _out_T_6630 = out_f_roready_662; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_662 = out_wivalid_1_516 & out_wimask_662; // @[RegisterRouter.scala:87:24] wire _out_T_6631 = out_f_wivalid_662; // @[RegisterRouter.scala:87:24] wire out_f_woready_662 = out_woready_1_516 & out_womask_662; // @[RegisterRouter.scala:87:24] wire _out_T_6632 = out_f_woready_662; // @[RegisterRouter.scala:87:24] wire _out_T_6633 = ~out_rimask_662; // @[RegisterRouter.scala:87:24] wire _out_T_6634 = ~out_wimask_662; // @[RegisterRouter.scala:87:24] wire _out_T_6635 = ~out_romask_662; // @[RegisterRouter.scala:87:24] wire _out_T_6636 = ~out_womask_662; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_561 = {programBufferMem_13, _out_prepend_T_561}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6637 = out_prepend_561; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6638 = _out_T_6637; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_562 = _out_T_6638; // @[RegisterRouter.scala:87:24] wire out_rimask_663 = |_out_rimask_T_663; // @[RegisterRouter.scala:87:24] wire out_wimask_663 = &_out_wimask_T_663; // @[RegisterRouter.scala:87:24] wire out_romask_663 = |_out_romask_T_663; // @[RegisterRouter.scala:87:24] wire out_womask_663 = &_out_womask_T_663; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_663 = out_rivalid_1_517 & out_rimask_663; // @[RegisterRouter.scala:87:24] wire _out_T_6640 = out_f_rivalid_663; // @[RegisterRouter.scala:87:24] wire out_f_roready_663 = out_roready_1_517 & out_romask_663; // @[RegisterRouter.scala:87:24] wire _out_T_6641 = out_f_roready_663; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_663 = out_wivalid_1_517 & out_wimask_663; // @[RegisterRouter.scala:87:24] wire _out_T_6642 = out_f_wivalid_663; // @[RegisterRouter.scala:87:24] wire out_f_woready_663 = out_woready_1_517 & out_womask_663; // @[RegisterRouter.scala:87:24] wire _out_T_6643 = out_f_woready_663; // @[RegisterRouter.scala:87:24] wire _out_T_6644 = ~out_rimask_663; // @[RegisterRouter.scala:87:24] wire _out_T_6645 = ~out_wimask_663; // @[RegisterRouter.scala:87:24] wire _out_T_6646 = ~out_romask_663; // @[RegisterRouter.scala:87:24] wire _out_T_6647 = ~out_womask_663; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_562 = {programBufferMem_14, _out_prepend_T_562}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6648 = out_prepend_562; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6649 = _out_T_6648; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_563 = _out_T_6649; // @[RegisterRouter.scala:87:24] wire out_rimask_664 = |_out_rimask_T_664; // @[RegisterRouter.scala:87:24] wire out_wimask_664 = &_out_wimask_T_664; // @[RegisterRouter.scala:87:24] wire out_romask_664 = |_out_romask_T_664; // @[RegisterRouter.scala:87:24] wire out_womask_664 = &_out_womask_T_664; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_664 = out_rivalid_1_518 & out_rimask_664; // @[RegisterRouter.scala:87:24] wire _out_T_6651 = out_f_rivalid_664; // @[RegisterRouter.scala:87:24] wire out_f_roready_664 = out_roready_1_518 & out_romask_664; // @[RegisterRouter.scala:87:24] wire _out_T_6652 = out_f_roready_664; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_664 = out_wivalid_1_518 & out_wimask_664; // @[RegisterRouter.scala:87:24] wire _out_T_6653 = out_f_wivalid_664; // @[RegisterRouter.scala:87:24] wire out_f_woready_664 = out_woready_1_518 & out_womask_664; // @[RegisterRouter.scala:87:24] wire _out_T_6654 = out_f_woready_664; // @[RegisterRouter.scala:87:24] wire _out_T_6655 = ~out_rimask_664; // @[RegisterRouter.scala:87:24] wire _out_T_6656 = ~out_wimask_664; // @[RegisterRouter.scala:87:24] wire _out_T_6657 = ~out_romask_664; // @[RegisterRouter.scala:87:24] wire _out_T_6658 = ~out_womask_664; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_563 = {programBufferMem_15, _out_prepend_T_563}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6659 = out_prepend_563; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6660 = _out_T_6659; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_105 = _out_T_6660; // @[MuxLiteral.scala:49:48] wire out_rimask_665 = |_out_rimask_T_665; // @[RegisterRouter.scala:87:24] wire out_wimask_665 = &_out_wimask_T_665; // @[RegisterRouter.scala:87:24] wire out_romask_665 = |_out_romask_T_665; // @[RegisterRouter.scala:87:24] wire out_womask_665 = &_out_womask_T_665; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_665 = out_rivalid_1_519 & out_rimask_665; // @[RegisterRouter.scala:87:24] wire _out_T_6662 = out_f_rivalid_665; // @[RegisterRouter.scala:87:24] wire out_f_roready_665 = out_roready_1_519 & out_romask_665; // @[RegisterRouter.scala:87:24] wire _out_T_6663 = out_f_roready_665; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_665 = out_wivalid_1_519 & out_wimask_665; // @[RegisterRouter.scala:87:24] wire out_f_woready_665 = out_woready_1_519 & out_womask_665; // @[RegisterRouter.scala:87:24] wire _out_T_6664 = ~out_rimask_665; // @[RegisterRouter.scala:87:24] wire _out_T_6665 = ~out_wimask_665; // @[RegisterRouter.scala:87:24] wire _out_T_6666 = ~out_romask_665; // @[RegisterRouter.scala:87:24] wire _out_T_6667 = ~out_womask_665; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6669 = _out_T_6668; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_564 = _out_T_6669; // @[RegisterRouter.scala:87:24] wire out_rimask_666 = |_out_rimask_T_666; // @[RegisterRouter.scala:87:24] wire out_wimask_666 = &_out_wimask_T_666; // @[RegisterRouter.scala:87:24] wire out_romask_666 = |_out_romask_T_666; // @[RegisterRouter.scala:87:24] wire out_womask_666 = &_out_womask_T_666; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_666 = out_rivalid_1_520 & out_rimask_666; // @[RegisterRouter.scala:87:24] wire _out_T_6671 = out_f_rivalid_666; // @[RegisterRouter.scala:87:24] wire out_f_roready_666 = out_roready_1_520 & out_romask_666; // @[RegisterRouter.scala:87:24] wire _out_T_6672 = out_f_roready_666; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_666 = out_wivalid_1_520 & out_wimask_666; // @[RegisterRouter.scala:87:24] wire out_f_woready_666 = out_woready_1_520 & out_womask_666; // @[RegisterRouter.scala:87:24] wire _out_T_6673 = ~out_rimask_666; // @[RegisterRouter.scala:87:24] wire _out_T_6674 = ~out_wimask_666; // @[RegisterRouter.scala:87:24] wire _out_T_6675 = ~out_romask_666; // @[RegisterRouter.scala:87:24] wire _out_T_6676 = ~out_womask_666; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_564 = {hi_930, flags_0_go, _out_prepend_T_564}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6677 = out_prepend_564; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6678 = _out_T_6677; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_565 = _out_T_6678; // @[RegisterRouter.scala:87:24] wire out_rimask_667 = |_out_rimask_T_667; // @[RegisterRouter.scala:87:24] wire out_wimask_667 = &_out_wimask_T_667; // @[RegisterRouter.scala:87:24] wire out_romask_667 = |_out_romask_T_667; // @[RegisterRouter.scala:87:24] wire out_womask_667 = &_out_womask_T_667; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_667 = out_rivalid_1_521 & out_rimask_667; // @[RegisterRouter.scala:87:24] wire _out_T_6680 = out_f_rivalid_667; // @[RegisterRouter.scala:87:24] wire out_f_roready_667 = out_roready_1_521 & out_romask_667; // @[RegisterRouter.scala:87:24] wire _out_T_6681 = out_f_roready_667; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_667 = out_wivalid_1_521 & out_wimask_667; // @[RegisterRouter.scala:87:24] wire out_f_woready_667 = out_woready_1_521 & out_womask_667; // @[RegisterRouter.scala:87:24] wire _out_T_6682 = ~out_rimask_667; // @[RegisterRouter.scala:87:24] wire _out_T_6683 = ~out_wimask_667; // @[RegisterRouter.scala:87:24] wire _out_T_6684 = ~out_romask_667; // @[RegisterRouter.scala:87:24] wire _out_T_6685 = ~out_womask_667; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_565 = {hi_931, flags_0_go, _out_prepend_T_565}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6686 = out_prepend_565; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6687 = _out_T_6686; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_566 = _out_T_6687; // @[RegisterRouter.scala:87:24] wire out_rimask_668 = |_out_rimask_T_668; // @[RegisterRouter.scala:87:24] wire out_wimask_668 = &_out_wimask_T_668; // @[RegisterRouter.scala:87:24] wire out_romask_668 = |_out_romask_T_668; // @[RegisterRouter.scala:87:24] wire out_womask_668 = &_out_womask_T_668; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_668 = out_rivalid_1_522 & out_rimask_668; // @[RegisterRouter.scala:87:24] wire _out_T_6689 = out_f_rivalid_668; // @[RegisterRouter.scala:87:24] wire out_f_roready_668 = out_roready_1_522 & out_romask_668; // @[RegisterRouter.scala:87:24] wire _out_T_6690 = out_f_roready_668; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_668 = out_wivalid_1_522 & out_wimask_668; // @[RegisterRouter.scala:87:24] wire out_f_woready_668 = out_woready_1_522 & out_womask_668; // @[RegisterRouter.scala:87:24] wire _out_T_6691 = ~out_rimask_668; // @[RegisterRouter.scala:87:24] wire _out_T_6692 = ~out_wimask_668; // @[RegisterRouter.scala:87:24] wire _out_T_6693 = ~out_romask_668; // @[RegisterRouter.scala:87:24] wire _out_T_6694 = ~out_womask_668; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_566 = {hi_932, flags_0_go, _out_prepend_T_566}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6695 = out_prepend_566; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6696 = _out_T_6695; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_567 = _out_T_6696; // @[RegisterRouter.scala:87:24] wire out_rimask_669 = |_out_rimask_T_669; // @[RegisterRouter.scala:87:24] wire out_wimask_669 = &_out_wimask_T_669; // @[RegisterRouter.scala:87:24] wire out_romask_669 = |_out_romask_T_669; // @[RegisterRouter.scala:87:24] wire out_womask_669 = &_out_womask_T_669; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_669 = out_rivalid_1_523 & out_rimask_669; // @[RegisterRouter.scala:87:24] wire _out_T_6698 = out_f_rivalid_669; // @[RegisterRouter.scala:87:24] wire out_f_roready_669 = out_roready_1_523 & out_romask_669; // @[RegisterRouter.scala:87:24] wire _out_T_6699 = out_f_roready_669; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_669 = out_wivalid_1_523 & out_wimask_669; // @[RegisterRouter.scala:87:24] wire out_f_woready_669 = out_woready_1_523 & out_womask_669; // @[RegisterRouter.scala:87:24] wire _out_T_6700 = ~out_rimask_669; // @[RegisterRouter.scala:87:24] wire _out_T_6701 = ~out_wimask_669; // @[RegisterRouter.scala:87:24] wire _out_T_6702 = ~out_romask_669; // @[RegisterRouter.scala:87:24] wire _out_T_6703 = ~out_womask_669; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_567 = {hi_933, flags_0_go, _out_prepend_T_567}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6704 = out_prepend_567; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6705 = _out_T_6704; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_568 = _out_T_6705; // @[RegisterRouter.scala:87:24] wire out_rimask_670 = |_out_rimask_T_670; // @[RegisterRouter.scala:87:24] wire out_wimask_670 = &_out_wimask_T_670; // @[RegisterRouter.scala:87:24] wire out_romask_670 = |_out_romask_T_670; // @[RegisterRouter.scala:87:24] wire out_womask_670 = &_out_womask_T_670; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_670 = out_rivalid_1_524 & out_rimask_670; // @[RegisterRouter.scala:87:24] wire _out_T_6707 = out_f_rivalid_670; // @[RegisterRouter.scala:87:24] wire out_f_roready_670 = out_roready_1_524 & out_romask_670; // @[RegisterRouter.scala:87:24] wire _out_T_6708 = out_f_roready_670; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_670 = out_wivalid_1_524 & out_wimask_670; // @[RegisterRouter.scala:87:24] wire out_f_woready_670 = out_woready_1_524 & out_womask_670; // @[RegisterRouter.scala:87:24] wire _out_T_6709 = ~out_rimask_670; // @[RegisterRouter.scala:87:24] wire _out_T_6710 = ~out_wimask_670; // @[RegisterRouter.scala:87:24] wire _out_T_6711 = ~out_romask_670; // @[RegisterRouter.scala:87:24] wire _out_T_6712 = ~out_womask_670; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_568 = {hi_934, flags_0_go, _out_prepend_T_568}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6713 = out_prepend_568; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6714 = _out_T_6713; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_569 = _out_T_6714; // @[RegisterRouter.scala:87:24] wire out_rimask_671 = |_out_rimask_T_671; // @[RegisterRouter.scala:87:24] wire out_wimask_671 = &_out_wimask_T_671; // @[RegisterRouter.scala:87:24] wire out_romask_671 = |_out_romask_T_671; // @[RegisterRouter.scala:87:24] wire out_womask_671 = &_out_womask_T_671; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_671 = out_rivalid_1_525 & out_rimask_671; // @[RegisterRouter.scala:87:24] wire _out_T_6716 = out_f_rivalid_671; // @[RegisterRouter.scala:87:24] wire out_f_roready_671 = out_roready_1_525 & out_romask_671; // @[RegisterRouter.scala:87:24] wire _out_T_6717 = out_f_roready_671; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_671 = out_wivalid_1_525 & out_wimask_671; // @[RegisterRouter.scala:87:24] wire out_f_woready_671 = out_woready_1_525 & out_womask_671; // @[RegisterRouter.scala:87:24] wire _out_T_6718 = ~out_rimask_671; // @[RegisterRouter.scala:87:24] wire _out_T_6719 = ~out_wimask_671; // @[RegisterRouter.scala:87:24] wire _out_T_6720 = ~out_romask_671; // @[RegisterRouter.scala:87:24] wire _out_T_6721 = ~out_womask_671; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_569 = {hi_935, flags_0_go, _out_prepend_T_569}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6722 = out_prepend_569; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6723 = _out_T_6722; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_570 = _out_T_6723; // @[RegisterRouter.scala:87:24] wire out_rimask_672 = |_out_rimask_T_672; // @[RegisterRouter.scala:87:24] wire out_wimask_672 = &_out_wimask_T_672; // @[RegisterRouter.scala:87:24] wire out_romask_672 = |_out_romask_T_672; // @[RegisterRouter.scala:87:24] wire out_womask_672 = &_out_womask_T_672; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_672 = out_rivalid_1_526 & out_rimask_672; // @[RegisterRouter.scala:87:24] wire _out_T_6725 = out_f_rivalid_672; // @[RegisterRouter.scala:87:24] wire out_f_roready_672 = out_roready_1_526 & out_romask_672; // @[RegisterRouter.scala:87:24] wire _out_T_6726 = out_f_roready_672; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_672 = out_wivalid_1_526 & out_wimask_672; // @[RegisterRouter.scala:87:24] wire out_f_woready_672 = out_woready_1_526 & out_womask_672; // @[RegisterRouter.scala:87:24] wire _out_T_6727 = ~out_rimask_672; // @[RegisterRouter.scala:87:24] wire _out_T_6728 = ~out_wimask_672; // @[RegisterRouter.scala:87:24] wire _out_T_6729 = ~out_romask_672; // @[RegisterRouter.scala:87:24] wire _out_T_6730 = ~out_womask_672; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_570 = {hi_936, flags_0_go, _out_prepend_T_570}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6731 = out_prepend_570; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6732 = _out_T_6731; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_244 = _out_T_6732; // @[MuxLiteral.scala:49:48] wire out_rimask_673 = |_out_rimask_T_673; // @[RegisterRouter.scala:87:24] wire out_wimask_673 = &_out_wimask_T_673; // @[RegisterRouter.scala:87:24] wire out_romask_673 = |_out_romask_T_673; // @[RegisterRouter.scala:87:24] wire out_womask_673 = &_out_womask_T_673; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_673 = out_rivalid_1_527 & out_rimask_673; // @[RegisterRouter.scala:87:24] wire _out_T_6734 = out_f_rivalid_673; // @[RegisterRouter.scala:87:24] wire out_f_roready_673 = out_roready_1_527 & out_romask_673; // @[RegisterRouter.scala:87:24] wire _out_T_6735 = out_f_roready_673; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_673 = out_wivalid_1_527 & out_wimask_673; // @[RegisterRouter.scala:87:24] wire out_f_woready_673 = out_woready_1_527 & out_womask_673; // @[RegisterRouter.scala:87:24] wire _out_T_6736 = ~out_rimask_673; // @[RegisterRouter.scala:87:24] wire _out_T_6737 = ~out_wimask_673; // @[RegisterRouter.scala:87:24] wire _out_T_6738 = ~out_romask_673; // @[RegisterRouter.scala:87:24] wire _out_T_6739 = ~out_womask_673; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6741 = _out_T_6740; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_571 = _out_T_6741; // @[RegisterRouter.scala:87:24] wire out_rimask_674 = |_out_rimask_T_674; // @[RegisterRouter.scala:87:24] wire out_wimask_674 = &_out_wimask_T_674; // @[RegisterRouter.scala:87:24] wire out_romask_674 = |_out_romask_T_674; // @[RegisterRouter.scala:87:24] wire out_womask_674 = &_out_womask_T_674; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_674 = out_rivalid_1_528 & out_rimask_674; // @[RegisterRouter.scala:87:24] wire _out_T_6743 = out_f_rivalid_674; // @[RegisterRouter.scala:87:24] wire out_f_roready_674 = out_roready_1_528 & out_romask_674; // @[RegisterRouter.scala:87:24] wire _out_T_6744 = out_f_roready_674; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_674 = out_wivalid_1_528 & out_wimask_674; // @[RegisterRouter.scala:87:24] wire out_f_woready_674 = out_woready_1_528 & out_womask_674; // @[RegisterRouter.scala:87:24] wire _out_T_6745 = ~out_rimask_674; // @[RegisterRouter.scala:87:24] wire _out_T_6746 = ~out_wimask_674; // @[RegisterRouter.scala:87:24] wire _out_T_6747 = ~out_romask_674; // @[RegisterRouter.scala:87:24] wire _out_T_6748 = ~out_womask_674; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_571 = {hi_306, flags_0_go, _out_prepend_T_571}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6749 = out_prepend_571; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6750 = _out_T_6749; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_572 = _out_T_6750; // @[RegisterRouter.scala:87:24] wire out_rimask_675 = |_out_rimask_T_675; // @[RegisterRouter.scala:87:24] wire out_wimask_675 = &_out_wimask_T_675; // @[RegisterRouter.scala:87:24] wire out_romask_675 = |_out_romask_T_675; // @[RegisterRouter.scala:87:24] wire out_womask_675 = &_out_womask_T_675; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_675 = out_rivalid_1_529 & out_rimask_675; // @[RegisterRouter.scala:87:24] wire _out_T_6752 = out_f_rivalid_675; // @[RegisterRouter.scala:87:24] wire out_f_roready_675 = out_roready_1_529 & out_romask_675; // @[RegisterRouter.scala:87:24] wire _out_T_6753 = out_f_roready_675; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_675 = out_wivalid_1_529 & out_wimask_675; // @[RegisterRouter.scala:87:24] wire out_f_woready_675 = out_woready_1_529 & out_womask_675; // @[RegisterRouter.scala:87:24] wire _out_T_6754 = ~out_rimask_675; // @[RegisterRouter.scala:87:24] wire _out_T_6755 = ~out_wimask_675; // @[RegisterRouter.scala:87:24] wire _out_T_6756 = ~out_romask_675; // @[RegisterRouter.scala:87:24] wire _out_T_6757 = ~out_womask_675; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_572 = {hi_307, flags_0_go, _out_prepend_T_572}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6758 = out_prepend_572; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6759 = _out_T_6758; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_573 = _out_T_6759; // @[RegisterRouter.scala:87:24] wire out_rimask_676 = |_out_rimask_T_676; // @[RegisterRouter.scala:87:24] wire out_wimask_676 = &_out_wimask_T_676; // @[RegisterRouter.scala:87:24] wire out_romask_676 = |_out_romask_T_676; // @[RegisterRouter.scala:87:24] wire out_womask_676 = &_out_womask_T_676; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_676 = out_rivalid_1_530 & out_rimask_676; // @[RegisterRouter.scala:87:24] wire _out_T_6761 = out_f_rivalid_676; // @[RegisterRouter.scala:87:24] wire out_f_roready_676 = out_roready_1_530 & out_romask_676; // @[RegisterRouter.scala:87:24] wire _out_T_6762 = out_f_roready_676; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_676 = out_wivalid_1_530 & out_wimask_676; // @[RegisterRouter.scala:87:24] wire out_f_woready_676 = out_woready_1_530 & out_womask_676; // @[RegisterRouter.scala:87:24] wire _out_T_6763 = ~out_rimask_676; // @[RegisterRouter.scala:87:24] wire _out_T_6764 = ~out_wimask_676; // @[RegisterRouter.scala:87:24] wire _out_T_6765 = ~out_romask_676; // @[RegisterRouter.scala:87:24] wire _out_T_6766 = ~out_womask_676; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_573 = {hi_308, flags_0_go, _out_prepend_T_573}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6767 = out_prepend_573; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6768 = _out_T_6767; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_574 = _out_T_6768; // @[RegisterRouter.scala:87:24] wire out_rimask_677 = |_out_rimask_T_677; // @[RegisterRouter.scala:87:24] wire out_wimask_677 = &_out_wimask_T_677; // @[RegisterRouter.scala:87:24] wire out_romask_677 = |_out_romask_T_677; // @[RegisterRouter.scala:87:24] wire out_womask_677 = &_out_womask_T_677; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_677 = out_rivalid_1_531 & out_rimask_677; // @[RegisterRouter.scala:87:24] wire _out_T_6770 = out_f_rivalid_677; // @[RegisterRouter.scala:87:24] wire out_f_roready_677 = out_roready_1_531 & out_romask_677; // @[RegisterRouter.scala:87:24] wire _out_T_6771 = out_f_roready_677; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_677 = out_wivalid_1_531 & out_wimask_677; // @[RegisterRouter.scala:87:24] wire out_f_woready_677 = out_woready_1_531 & out_womask_677; // @[RegisterRouter.scala:87:24] wire _out_T_6772 = ~out_rimask_677; // @[RegisterRouter.scala:87:24] wire _out_T_6773 = ~out_wimask_677; // @[RegisterRouter.scala:87:24] wire _out_T_6774 = ~out_romask_677; // @[RegisterRouter.scala:87:24] wire _out_T_6775 = ~out_womask_677; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_574 = {hi_309, flags_0_go, _out_prepend_T_574}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6776 = out_prepend_574; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6777 = _out_T_6776; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_575 = _out_T_6777; // @[RegisterRouter.scala:87:24] wire out_rimask_678 = |_out_rimask_T_678; // @[RegisterRouter.scala:87:24] wire out_wimask_678 = &_out_wimask_T_678; // @[RegisterRouter.scala:87:24] wire out_romask_678 = |_out_romask_T_678; // @[RegisterRouter.scala:87:24] wire out_womask_678 = &_out_womask_T_678; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_678 = out_rivalid_1_532 & out_rimask_678; // @[RegisterRouter.scala:87:24] wire _out_T_6779 = out_f_rivalid_678; // @[RegisterRouter.scala:87:24] wire out_f_roready_678 = out_roready_1_532 & out_romask_678; // @[RegisterRouter.scala:87:24] wire _out_T_6780 = out_f_roready_678; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_678 = out_wivalid_1_532 & out_wimask_678; // @[RegisterRouter.scala:87:24] wire out_f_woready_678 = out_woready_1_532 & out_womask_678; // @[RegisterRouter.scala:87:24] wire _out_T_6781 = ~out_rimask_678; // @[RegisterRouter.scala:87:24] wire _out_T_6782 = ~out_wimask_678; // @[RegisterRouter.scala:87:24] wire _out_T_6783 = ~out_romask_678; // @[RegisterRouter.scala:87:24] wire _out_T_6784 = ~out_womask_678; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_575 = {hi_310, flags_0_go, _out_prepend_T_575}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6785 = out_prepend_575; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6786 = _out_T_6785; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_576 = _out_T_6786; // @[RegisterRouter.scala:87:24] wire out_rimask_679 = |_out_rimask_T_679; // @[RegisterRouter.scala:87:24] wire out_wimask_679 = &_out_wimask_T_679; // @[RegisterRouter.scala:87:24] wire out_romask_679 = |_out_romask_T_679; // @[RegisterRouter.scala:87:24] wire out_womask_679 = &_out_womask_T_679; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_679 = out_rivalid_1_533 & out_rimask_679; // @[RegisterRouter.scala:87:24] wire _out_T_6788 = out_f_rivalid_679; // @[RegisterRouter.scala:87:24] wire out_f_roready_679 = out_roready_1_533 & out_romask_679; // @[RegisterRouter.scala:87:24] wire _out_T_6789 = out_f_roready_679; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_679 = out_wivalid_1_533 & out_wimask_679; // @[RegisterRouter.scala:87:24] wire out_f_woready_679 = out_woready_1_533 & out_womask_679; // @[RegisterRouter.scala:87:24] wire _out_T_6790 = ~out_rimask_679; // @[RegisterRouter.scala:87:24] wire _out_T_6791 = ~out_wimask_679; // @[RegisterRouter.scala:87:24] wire _out_T_6792 = ~out_romask_679; // @[RegisterRouter.scala:87:24] wire _out_T_6793 = ~out_womask_679; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_576 = {hi_311, flags_0_go, _out_prepend_T_576}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6794 = out_prepend_576; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6795 = _out_T_6794; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_577 = _out_T_6795; // @[RegisterRouter.scala:87:24] wire out_rimask_680 = |_out_rimask_T_680; // @[RegisterRouter.scala:87:24] wire out_wimask_680 = &_out_wimask_T_680; // @[RegisterRouter.scala:87:24] wire out_romask_680 = |_out_romask_T_680; // @[RegisterRouter.scala:87:24] wire out_womask_680 = &_out_womask_T_680; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_680 = out_rivalid_1_534 & out_rimask_680; // @[RegisterRouter.scala:87:24] wire _out_T_6797 = out_f_rivalid_680; // @[RegisterRouter.scala:87:24] wire out_f_roready_680 = out_roready_1_534 & out_romask_680; // @[RegisterRouter.scala:87:24] wire _out_T_6798 = out_f_roready_680; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_680 = out_wivalid_1_534 & out_wimask_680; // @[RegisterRouter.scala:87:24] wire out_f_woready_680 = out_woready_1_534 & out_womask_680; // @[RegisterRouter.scala:87:24] wire _out_T_6799 = ~out_rimask_680; // @[RegisterRouter.scala:87:24] wire _out_T_6800 = ~out_wimask_680; // @[RegisterRouter.scala:87:24] wire _out_T_6801 = ~out_romask_680; // @[RegisterRouter.scala:87:24] wire _out_T_6802 = ~out_womask_680; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_577 = {hi_312, flags_0_go, _out_prepend_T_577}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6803 = out_prepend_577; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6804 = _out_T_6803; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_166 = _out_T_6804; // @[MuxLiteral.scala:49:48] wire out_rimask_681 = |_out_rimask_T_681; // @[RegisterRouter.scala:87:24] wire out_wimask_681 = &_out_wimask_T_681; // @[RegisterRouter.scala:87:24] wire out_romask_681 = |_out_romask_T_681; // @[RegisterRouter.scala:87:24] wire out_womask_681 = &_out_womask_T_681; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_681 = out_rivalid_1_535 & out_rimask_681; // @[RegisterRouter.scala:87:24] wire out_f_roready_681 = out_roready_1_535 & out_romask_681; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_681 = out_wivalid_1_535 & out_wimask_681; // @[RegisterRouter.scala:87:24] wire _out_T_6806 = out_f_wivalid_681; // @[RegisterRouter.scala:87:24] assign out_f_woready_681 = out_woready_1_535 & out_womask_681; // @[RegisterRouter.scala:87:24] assign hartHaltedWrEn = out_f_woready_681; // @[RegisterRouter.scala:87:24] wire _out_T_6807 = out_f_woready_681; // @[RegisterRouter.scala:87:24] assign hartHaltedId = _out_T_6805; // @[RegisterRouter.scala:87:24] wire _out_T_6808 = ~out_rimask_681; // @[RegisterRouter.scala:87:24] wire _out_T_6809 = ~out_wimask_681; // @[RegisterRouter.scala:87:24] wire _out_T_6810 = ~out_romask_681; // @[RegisterRouter.scala:87:24] wire _out_T_6811 = ~out_womask_681; // @[RegisterRouter.scala:87:24] wire out_rimask_682 = |_out_rimask_T_682; // @[RegisterRouter.scala:87:24] wire out_wimask_682 = &_out_wimask_T_682; // @[RegisterRouter.scala:87:24] wire out_romask_682 = |_out_romask_T_682; // @[RegisterRouter.scala:87:24] wire out_womask_682 = &_out_womask_T_682; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_682 = out_rivalid_1_536 & out_rimask_682; // @[RegisterRouter.scala:87:24] wire out_f_roready_682 = out_roready_1_536 & out_romask_682; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_682 = out_wivalid_1_536 & out_wimask_682; // @[RegisterRouter.scala:87:24] wire _out_T_6815 = out_f_wivalid_682; // @[RegisterRouter.scala:87:24] assign out_f_woready_682 = out_woready_1_536 & out_womask_682; // @[RegisterRouter.scala:87:24] assign hartGoingWrEn = out_f_woready_682; // @[RegisterRouter.scala:87:24] wire _out_T_6816 = out_f_woready_682; // @[RegisterRouter.scala:87:24] assign hartGoingId = _out_T_6814; // @[RegisterRouter.scala:87:24] wire _out_T_6817 = ~out_rimask_682; // @[RegisterRouter.scala:87:24] wire _out_T_6818 = ~out_wimask_682; // @[RegisterRouter.scala:87:24] wire _out_T_6819 = ~out_romask_682; // @[RegisterRouter.scala:87:24] wire _out_T_6820 = ~out_womask_682; // @[RegisterRouter.scala:87:24] wire out_rimask_683 = |_out_rimask_T_683; // @[RegisterRouter.scala:87:24] wire out_wimask_683 = &_out_wimask_T_683; // @[RegisterRouter.scala:87:24] wire out_romask_683 = |_out_romask_T_683; // @[RegisterRouter.scala:87:24] wire out_womask_683 = &_out_womask_T_683; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_683 = out_rivalid_1_537 & out_rimask_683; // @[RegisterRouter.scala:87:24] wire _out_T_6824 = out_f_rivalid_683; // @[RegisterRouter.scala:87:24] wire out_f_roready_683 = out_roready_1_537 & out_romask_683; // @[RegisterRouter.scala:87:24] wire _out_T_6825 = out_f_roready_683; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_683 = out_wivalid_1_537 & out_wimask_683; // @[RegisterRouter.scala:87:24] wire out_f_woready_683 = out_woready_1_537 & out_womask_683; // @[RegisterRouter.scala:87:24] wire _out_T_6826 = ~out_rimask_683; // @[RegisterRouter.scala:87:24] wire _out_T_6827 = ~out_wimask_683; // @[RegisterRouter.scala:87:24] wire _out_T_6828 = ~out_romask_683; // @[RegisterRouter.scala:87:24] wire _out_T_6829 = ~out_womask_683; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6831 = _out_T_6830; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_579 = _out_T_6831; // @[RegisterRouter.scala:87:24] wire out_rimask_684 = |_out_rimask_T_684; // @[RegisterRouter.scala:87:24] wire out_wimask_684 = &_out_wimask_T_684; // @[RegisterRouter.scala:87:24] wire out_romask_684 = |_out_romask_T_684; // @[RegisterRouter.scala:87:24] wire out_womask_684 = &_out_womask_T_684; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_684 = out_rivalid_1_538 & out_rimask_684; // @[RegisterRouter.scala:87:24] wire _out_T_6833 = out_f_rivalid_684; // @[RegisterRouter.scala:87:24] wire out_f_roready_684 = out_roready_1_538 & out_romask_684; // @[RegisterRouter.scala:87:24] wire _out_T_6834 = out_f_roready_684; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_684 = out_wivalid_1_538 & out_wimask_684; // @[RegisterRouter.scala:87:24] wire out_f_woready_684 = out_woready_1_538 & out_womask_684; // @[RegisterRouter.scala:87:24] wire _out_T_6835 = ~out_rimask_684; // @[RegisterRouter.scala:87:24] wire _out_T_6836 = ~out_wimask_684; // @[RegisterRouter.scala:87:24] wire _out_T_6837 = ~out_romask_684; // @[RegisterRouter.scala:87:24] wire _out_T_6838 = ~out_womask_684; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_579 = {hi_162, flags_0_go, _out_prepend_T_579}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6839 = out_prepend_579; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6840 = _out_T_6839; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_580 = _out_T_6840; // @[RegisterRouter.scala:87:24] wire out_rimask_685 = |_out_rimask_T_685; // @[RegisterRouter.scala:87:24] wire out_wimask_685 = &_out_wimask_T_685; // @[RegisterRouter.scala:87:24] wire out_romask_685 = |_out_romask_T_685; // @[RegisterRouter.scala:87:24] wire out_womask_685 = &_out_womask_T_685; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_685 = out_rivalid_1_539 & out_rimask_685; // @[RegisterRouter.scala:87:24] wire _out_T_6842 = out_f_rivalid_685; // @[RegisterRouter.scala:87:24] wire out_f_roready_685 = out_roready_1_539 & out_romask_685; // @[RegisterRouter.scala:87:24] wire _out_T_6843 = out_f_roready_685; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_685 = out_wivalid_1_539 & out_wimask_685; // @[RegisterRouter.scala:87:24] wire out_f_woready_685 = out_woready_1_539 & out_womask_685; // @[RegisterRouter.scala:87:24] wire _out_T_6844 = ~out_rimask_685; // @[RegisterRouter.scala:87:24] wire _out_T_6845 = ~out_wimask_685; // @[RegisterRouter.scala:87:24] wire _out_T_6846 = ~out_romask_685; // @[RegisterRouter.scala:87:24] wire _out_T_6847 = ~out_womask_685; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_580 = {hi_163, flags_0_go, _out_prepend_T_580}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6848 = out_prepend_580; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6849 = _out_T_6848; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_581 = _out_T_6849; // @[RegisterRouter.scala:87:24] wire out_rimask_686 = |_out_rimask_T_686; // @[RegisterRouter.scala:87:24] wire out_wimask_686 = &_out_wimask_T_686; // @[RegisterRouter.scala:87:24] wire out_romask_686 = |_out_romask_T_686; // @[RegisterRouter.scala:87:24] wire out_womask_686 = &_out_womask_T_686; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_686 = out_rivalid_1_540 & out_rimask_686; // @[RegisterRouter.scala:87:24] wire _out_T_6851 = out_f_rivalid_686; // @[RegisterRouter.scala:87:24] wire out_f_roready_686 = out_roready_1_540 & out_romask_686; // @[RegisterRouter.scala:87:24] wire _out_T_6852 = out_f_roready_686; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_686 = out_wivalid_1_540 & out_wimask_686; // @[RegisterRouter.scala:87:24] wire out_f_woready_686 = out_woready_1_540 & out_womask_686; // @[RegisterRouter.scala:87:24] wire _out_T_6853 = ~out_rimask_686; // @[RegisterRouter.scala:87:24] wire _out_T_6854 = ~out_wimask_686; // @[RegisterRouter.scala:87:24] wire _out_T_6855 = ~out_romask_686; // @[RegisterRouter.scala:87:24] wire _out_T_6856 = ~out_womask_686; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_581 = {hi_164, flags_0_go, _out_prepend_T_581}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6857 = out_prepend_581; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6858 = _out_T_6857; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_582 = _out_T_6858; // @[RegisterRouter.scala:87:24] wire out_rimask_687 = |_out_rimask_T_687; // @[RegisterRouter.scala:87:24] wire out_wimask_687 = &_out_wimask_T_687; // @[RegisterRouter.scala:87:24] wire out_romask_687 = |_out_romask_T_687; // @[RegisterRouter.scala:87:24] wire out_womask_687 = &_out_womask_T_687; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_687 = out_rivalid_1_541 & out_rimask_687; // @[RegisterRouter.scala:87:24] wire _out_T_6860 = out_f_rivalid_687; // @[RegisterRouter.scala:87:24] wire out_f_roready_687 = out_roready_1_541 & out_romask_687; // @[RegisterRouter.scala:87:24] wire _out_T_6861 = out_f_roready_687; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_687 = out_wivalid_1_541 & out_wimask_687; // @[RegisterRouter.scala:87:24] wire out_f_woready_687 = out_woready_1_541 & out_womask_687; // @[RegisterRouter.scala:87:24] wire _out_T_6862 = ~out_rimask_687; // @[RegisterRouter.scala:87:24] wire _out_T_6863 = ~out_wimask_687; // @[RegisterRouter.scala:87:24] wire _out_T_6864 = ~out_romask_687; // @[RegisterRouter.scala:87:24] wire _out_T_6865 = ~out_womask_687; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_582 = {hi_165, flags_0_go, _out_prepend_T_582}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6866 = out_prepend_582; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6867 = _out_T_6866; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_583 = _out_T_6867; // @[RegisterRouter.scala:87:24] wire out_rimask_688 = |_out_rimask_T_688; // @[RegisterRouter.scala:87:24] wire out_wimask_688 = &_out_wimask_T_688; // @[RegisterRouter.scala:87:24] wire out_romask_688 = |_out_romask_T_688; // @[RegisterRouter.scala:87:24] wire out_womask_688 = &_out_womask_T_688; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_688 = out_rivalid_1_542 & out_rimask_688; // @[RegisterRouter.scala:87:24] wire _out_T_6869 = out_f_rivalid_688; // @[RegisterRouter.scala:87:24] wire out_f_roready_688 = out_roready_1_542 & out_romask_688; // @[RegisterRouter.scala:87:24] wire _out_T_6870 = out_f_roready_688; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_688 = out_wivalid_1_542 & out_wimask_688; // @[RegisterRouter.scala:87:24] wire out_f_woready_688 = out_woready_1_542 & out_womask_688; // @[RegisterRouter.scala:87:24] wire _out_T_6871 = ~out_rimask_688; // @[RegisterRouter.scala:87:24] wire _out_T_6872 = ~out_wimask_688; // @[RegisterRouter.scala:87:24] wire _out_T_6873 = ~out_romask_688; // @[RegisterRouter.scala:87:24] wire _out_T_6874 = ~out_womask_688; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_583 = {hi_166, flags_0_go, _out_prepend_T_583}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6875 = out_prepend_583; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6876 = _out_T_6875; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_584 = _out_T_6876; // @[RegisterRouter.scala:87:24] wire out_rimask_689 = |_out_rimask_T_689; // @[RegisterRouter.scala:87:24] wire out_wimask_689 = &_out_wimask_T_689; // @[RegisterRouter.scala:87:24] wire out_romask_689 = |_out_romask_T_689; // @[RegisterRouter.scala:87:24] wire out_womask_689 = &_out_womask_T_689; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_689 = out_rivalid_1_543 & out_rimask_689; // @[RegisterRouter.scala:87:24] wire _out_T_6878 = out_f_rivalid_689; // @[RegisterRouter.scala:87:24] wire out_f_roready_689 = out_roready_1_543 & out_romask_689; // @[RegisterRouter.scala:87:24] wire _out_T_6879 = out_f_roready_689; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_689 = out_wivalid_1_543 & out_wimask_689; // @[RegisterRouter.scala:87:24] wire out_f_woready_689 = out_woready_1_543 & out_womask_689; // @[RegisterRouter.scala:87:24] wire _out_T_6880 = ~out_rimask_689; // @[RegisterRouter.scala:87:24] wire _out_T_6881 = ~out_wimask_689; // @[RegisterRouter.scala:87:24] wire _out_T_6882 = ~out_romask_689; // @[RegisterRouter.scala:87:24] wire _out_T_6883 = ~out_womask_689; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_584 = {hi_167, flags_0_go, _out_prepend_T_584}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6884 = out_prepend_584; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6885 = _out_T_6884; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_585 = _out_T_6885; // @[RegisterRouter.scala:87:24] wire out_rimask_690 = |_out_rimask_T_690; // @[RegisterRouter.scala:87:24] wire out_wimask_690 = &_out_wimask_T_690; // @[RegisterRouter.scala:87:24] wire out_romask_690 = |_out_romask_T_690; // @[RegisterRouter.scala:87:24] wire out_womask_690 = &_out_womask_T_690; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_690 = out_rivalid_1_544 & out_rimask_690; // @[RegisterRouter.scala:87:24] wire _out_T_6887 = out_f_rivalid_690; // @[RegisterRouter.scala:87:24] wire out_f_roready_690 = out_roready_1_544 & out_romask_690; // @[RegisterRouter.scala:87:24] wire _out_T_6888 = out_f_roready_690; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_690 = out_wivalid_1_544 & out_wimask_690; // @[RegisterRouter.scala:87:24] wire out_f_woready_690 = out_woready_1_544 & out_womask_690; // @[RegisterRouter.scala:87:24] wire _out_T_6889 = ~out_rimask_690; // @[RegisterRouter.scala:87:24] wire _out_T_6890 = ~out_wimask_690; // @[RegisterRouter.scala:87:24] wire _out_T_6891 = ~out_romask_690; // @[RegisterRouter.scala:87:24] wire _out_T_6892 = ~out_womask_690; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_585 = {hi_168, flags_0_go, _out_prepend_T_585}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6893 = out_prepend_585; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6894 = _out_T_6893; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_148 = _out_T_6894; // @[MuxLiteral.scala:49:48] wire out_rimask_691 = |_out_rimask_T_691; // @[RegisterRouter.scala:87:24] wire out_wimask_691 = &_out_wimask_T_691; // @[RegisterRouter.scala:87:24] wire out_romask_691 = |_out_romask_T_691; // @[RegisterRouter.scala:87:24] wire out_womask_691 = &_out_womask_T_691; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_691 = out_rivalid_1_545 & out_rimask_691; // @[RegisterRouter.scala:87:24] wire _out_T_6896 = out_f_rivalid_691; // @[RegisterRouter.scala:87:24] wire out_f_roready_691 = out_roready_1_545 & out_romask_691; // @[RegisterRouter.scala:87:24] wire _out_T_6897 = out_f_roready_691; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_691 = out_wivalid_1_545 & out_wimask_691; // @[RegisterRouter.scala:87:24] wire out_f_woready_691 = out_woready_1_545 & out_womask_691; // @[RegisterRouter.scala:87:24] wire _out_T_6898 = ~out_rimask_691; // @[RegisterRouter.scala:87:24] wire _out_T_6899 = ~out_wimask_691; // @[RegisterRouter.scala:87:24] wire _out_T_6900 = ~out_romask_691; // @[RegisterRouter.scala:87:24] wire _out_T_6901 = ~out_womask_691; // @[RegisterRouter.scala:87:24] wire out_rimask_692 = |_out_rimask_T_692; // @[RegisterRouter.scala:87:24] wire out_wimask_692 = &_out_wimask_T_692; // @[RegisterRouter.scala:87:24] wire out_romask_692 = |_out_romask_T_692; // @[RegisterRouter.scala:87:24] wire out_womask_692 = &_out_womask_T_692; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_692 = out_rivalid_1_546 & out_rimask_692; // @[RegisterRouter.scala:87:24] wire _out_T_6905 = out_f_rivalid_692; // @[RegisterRouter.scala:87:24] wire out_f_roready_692 = out_roready_1_546 & out_romask_692; // @[RegisterRouter.scala:87:24] wire _out_T_6906 = out_f_roready_692; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_692 = out_wivalid_1_546 & out_wimask_692; // @[RegisterRouter.scala:87:24] wire out_f_woready_692 = out_woready_1_546 & out_womask_692; // @[RegisterRouter.scala:87:24] wire _out_T_6907 = ~out_rimask_692; // @[RegisterRouter.scala:87:24] wire _out_T_6908 = ~out_wimask_692; // @[RegisterRouter.scala:87:24] wire _out_T_6909 = ~out_romask_692; // @[RegisterRouter.scala:87:24] wire _out_T_6910 = ~out_womask_692; // @[RegisterRouter.scala:87:24] wire out_rimask_693 = |_out_rimask_T_693; // @[RegisterRouter.scala:87:24] wire out_wimask_693 = &_out_wimask_T_693; // @[RegisterRouter.scala:87:24] wire out_romask_693 = |_out_romask_T_693; // @[RegisterRouter.scala:87:24] wire out_womask_693 = &_out_womask_T_693; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_693 = out_rivalid_1_547 & out_rimask_693; // @[RegisterRouter.scala:87:24] wire _out_T_6914 = out_f_rivalid_693; // @[RegisterRouter.scala:87:24] wire out_f_roready_693 = out_roready_1_547 & out_romask_693; // @[RegisterRouter.scala:87:24] wire _out_T_6915 = out_f_roready_693; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_693 = out_wivalid_1_547 & out_wimask_693; // @[RegisterRouter.scala:87:24] wire out_f_woready_693 = out_woready_1_547 & out_womask_693; // @[RegisterRouter.scala:87:24] wire _out_T_6916 = ~out_rimask_693; // @[RegisterRouter.scala:87:24] wire _out_T_6917 = ~out_wimask_693; // @[RegisterRouter.scala:87:24] wire _out_T_6918 = ~out_romask_693; // @[RegisterRouter.scala:87:24] wire _out_T_6919 = ~out_womask_693; // @[RegisterRouter.scala:87:24] wire out_rimask_694 = |_out_rimask_T_694; // @[RegisterRouter.scala:87:24] wire out_wimask_694 = &_out_wimask_T_694; // @[RegisterRouter.scala:87:24] wire out_romask_694 = |_out_romask_T_694; // @[RegisterRouter.scala:87:24] wire out_womask_694 = &_out_womask_T_694; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_694 = out_rivalid_1_548 & out_rimask_694; // @[RegisterRouter.scala:87:24] wire _out_T_6923 = out_f_rivalid_694; // @[RegisterRouter.scala:87:24] wire out_f_roready_694 = out_roready_1_548 & out_romask_694; // @[RegisterRouter.scala:87:24] wire _out_T_6924 = out_f_roready_694; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_694 = out_wivalid_1_548 & out_wimask_694; // @[RegisterRouter.scala:87:24] wire out_f_woready_694 = out_woready_1_548 & out_womask_694; // @[RegisterRouter.scala:87:24] wire _out_T_6925 = ~out_rimask_694; // @[RegisterRouter.scala:87:24] wire _out_T_6926 = ~out_wimask_694; // @[RegisterRouter.scala:87:24] wire _out_T_6927 = ~out_romask_694; // @[RegisterRouter.scala:87:24] wire _out_T_6928 = ~out_womask_694; // @[RegisterRouter.scala:87:24] wire out_rimask_695 = |_out_rimask_T_695; // @[RegisterRouter.scala:87:24] wire out_wimask_695 = &_out_wimask_T_695; // @[RegisterRouter.scala:87:24] wire out_romask_695 = |_out_romask_T_695; // @[RegisterRouter.scala:87:24] wire out_womask_695 = &_out_womask_T_695; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_695 = out_rivalid_1_549 & out_rimask_695; // @[RegisterRouter.scala:87:24] wire _out_T_6932 = out_f_rivalid_695; // @[RegisterRouter.scala:87:24] wire out_f_roready_695 = out_roready_1_549 & out_romask_695; // @[RegisterRouter.scala:87:24] wire _out_T_6933 = out_f_roready_695; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_695 = out_wivalid_1_549 & out_wimask_695; // @[RegisterRouter.scala:87:24] wire out_f_woready_695 = out_woready_1_549 & out_womask_695; // @[RegisterRouter.scala:87:24] wire _out_T_6934 = ~out_rimask_695; // @[RegisterRouter.scala:87:24] wire _out_T_6935 = ~out_wimask_695; // @[RegisterRouter.scala:87:24] wire _out_T_6936 = ~out_romask_695; // @[RegisterRouter.scala:87:24] wire _out_T_6937 = ~out_womask_695; // @[RegisterRouter.scala:87:24] wire out_rimask_696 = |_out_rimask_T_696; // @[RegisterRouter.scala:87:24] wire out_wimask_696 = &_out_wimask_T_696; // @[RegisterRouter.scala:87:24] wire out_romask_696 = |_out_romask_T_696; // @[RegisterRouter.scala:87:24] wire out_womask_696 = &_out_womask_T_696; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_696 = out_rivalid_1_550 & out_rimask_696; // @[RegisterRouter.scala:87:24] wire _out_T_6941 = out_f_rivalid_696; // @[RegisterRouter.scala:87:24] wire out_f_roready_696 = out_roready_1_550 & out_romask_696; // @[RegisterRouter.scala:87:24] wire _out_T_6942 = out_f_roready_696; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_696 = out_wivalid_1_550 & out_wimask_696; // @[RegisterRouter.scala:87:24] wire out_f_woready_696 = out_woready_1_550 & out_womask_696; // @[RegisterRouter.scala:87:24] wire _out_T_6943 = ~out_rimask_696; // @[RegisterRouter.scala:87:24] wire _out_T_6944 = ~out_wimask_696; // @[RegisterRouter.scala:87:24] wire _out_T_6945 = ~out_romask_696; // @[RegisterRouter.scala:87:24] wire _out_T_6946 = ~out_womask_696; // @[RegisterRouter.scala:87:24] wire out_rimask_697 = |_out_rimask_T_697; // @[RegisterRouter.scala:87:24] wire out_wimask_697 = &_out_wimask_T_697; // @[RegisterRouter.scala:87:24] wire out_romask_697 = |_out_romask_T_697; // @[RegisterRouter.scala:87:24] wire out_womask_697 = &_out_womask_T_697; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_697 = out_rivalid_1_551 & out_rimask_697; // @[RegisterRouter.scala:87:24] wire _out_T_6950 = out_f_rivalid_697; // @[RegisterRouter.scala:87:24] wire out_f_roready_697 = out_roready_1_551 & out_romask_697; // @[RegisterRouter.scala:87:24] wire _out_T_6951 = out_f_roready_697; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_697 = out_wivalid_1_551 & out_wimask_697; // @[RegisterRouter.scala:87:24] wire out_f_woready_697 = out_woready_1_551 & out_womask_697; // @[RegisterRouter.scala:87:24] wire _out_T_6952 = ~out_rimask_697; // @[RegisterRouter.scala:87:24] wire _out_T_6953 = ~out_wimask_697; // @[RegisterRouter.scala:87:24] wire _out_T_6954 = ~out_romask_697; // @[RegisterRouter.scala:87:24] wire _out_T_6955 = ~out_womask_697; // @[RegisterRouter.scala:87:24] wire out_rimask_698 = |_out_rimask_T_698; // @[RegisterRouter.scala:87:24] wire out_wimask_698 = &_out_wimask_T_698; // @[RegisterRouter.scala:87:24] wire out_romask_698 = |_out_romask_T_698; // @[RegisterRouter.scala:87:24] wire out_womask_698 = &_out_womask_T_698; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_698 = out_rivalid_1_552 & out_rimask_698; // @[RegisterRouter.scala:87:24] wire _out_T_6959 = out_f_rivalid_698; // @[RegisterRouter.scala:87:24] wire out_f_roready_698 = out_roready_1_552 & out_romask_698; // @[RegisterRouter.scala:87:24] wire _out_T_6960 = out_f_roready_698; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_698 = out_wivalid_1_552 & out_wimask_698; // @[RegisterRouter.scala:87:24] wire out_f_woready_698 = out_woready_1_552 & out_womask_698; // @[RegisterRouter.scala:87:24] wire _out_T_6961 = ~out_rimask_698; // @[RegisterRouter.scala:87:24] wire _out_T_6962 = ~out_wimask_698; // @[RegisterRouter.scala:87:24] wire _out_T_6963 = ~out_romask_698; // @[RegisterRouter.scala:87:24] wire _out_T_6964 = ~out_womask_698; // @[RegisterRouter.scala:87:24] wire out_rimask_699 = |_out_rimask_T_699; // @[RegisterRouter.scala:87:24] wire out_wimask_699 = &_out_wimask_T_699; // @[RegisterRouter.scala:87:24] wire out_romask_699 = |_out_romask_T_699; // @[RegisterRouter.scala:87:24] wire out_womask_699 = &_out_womask_T_699; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_699 = out_rivalid_1_553 & out_rimask_699; // @[RegisterRouter.scala:87:24] wire _out_T_6968 = out_f_rivalid_699; // @[RegisterRouter.scala:87:24] wire out_f_roready_699 = out_roready_1_553 & out_romask_699; // @[RegisterRouter.scala:87:24] wire _out_T_6969 = out_f_roready_699; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_699 = out_wivalid_1_553 & out_wimask_699; // @[RegisterRouter.scala:87:24] wire out_f_woready_699 = out_woready_1_553 & out_womask_699; // @[RegisterRouter.scala:87:24] wire _out_T_6970 = ~out_rimask_699; // @[RegisterRouter.scala:87:24] wire _out_T_6971 = ~out_wimask_699; // @[RegisterRouter.scala:87:24] wire _out_T_6972 = ~out_romask_699; // @[RegisterRouter.scala:87:24] wire _out_T_6973 = ~out_womask_699; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6975 = _out_T_6974; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_593 = _out_T_6975; // @[RegisterRouter.scala:87:24] wire out_rimask_700 = |_out_rimask_T_700; // @[RegisterRouter.scala:87:24] wire out_wimask_700 = &_out_wimask_T_700; // @[RegisterRouter.scala:87:24] wire out_romask_700 = |_out_romask_T_700; // @[RegisterRouter.scala:87:24] wire out_womask_700 = &_out_womask_T_700; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_700 = out_rivalid_1_554 & out_rimask_700; // @[RegisterRouter.scala:87:24] wire _out_T_6977 = out_f_rivalid_700; // @[RegisterRouter.scala:87:24] wire out_f_roready_700 = out_roready_1_554 & out_romask_700; // @[RegisterRouter.scala:87:24] wire _out_T_6978 = out_f_roready_700; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_700 = out_wivalid_1_554 & out_wimask_700; // @[RegisterRouter.scala:87:24] wire out_f_woready_700 = out_woready_1_554 & out_womask_700; // @[RegisterRouter.scala:87:24] wire _out_T_6979 = ~out_rimask_700; // @[RegisterRouter.scala:87:24] wire _out_T_6980 = ~out_wimask_700; // @[RegisterRouter.scala:87:24] wire _out_T_6981 = ~out_romask_700; // @[RegisterRouter.scala:87:24] wire _out_T_6982 = ~out_womask_700; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_593 = {hi_266, flags_0_go, _out_prepend_T_593}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6983 = out_prepend_593; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6984 = _out_T_6983; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_594 = _out_T_6984; // @[RegisterRouter.scala:87:24] wire out_rimask_701 = |_out_rimask_T_701; // @[RegisterRouter.scala:87:24] wire out_wimask_701 = &_out_wimask_T_701; // @[RegisterRouter.scala:87:24] wire out_romask_701 = |_out_romask_T_701; // @[RegisterRouter.scala:87:24] wire out_womask_701 = &_out_womask_T_701; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_701 = out_rivalid_1_555 & out_rimask_701; // @[RegisterRouter.scala:87:24] wire _out_T_6986 = out_f_rivalid_701; // @[RegisterRouter.scala:87:24] wire out_f_roready_701 = out_roready_1_555 & out_romask_701; // @[RegisterRouter.scala:87:24] wire _out_T_6987 = out_f_roready_701; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_701 = out_wivalid_1_555 & out_wimask_701; // @[RegisterRouter.scala:87:24] wire out_f_woready_701 = out_woready_1_555 & out_womask_701; // @[RegisterRouter.scala:87:24] wire _out_T_6988 = ~out_rimask_701; // @[RegisterRouter.scala:87:24] wire _out_T_6989 = ~out_wimask_701; // @[RegisterRouter.scala:87:24] wire _out_T_6990 = ~out_romask_701; // @[RegisterRouter.scala:87:24] wire _out_T_6991 = ~out_womask_701; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_594 = {hi_267, flags_0_go, _out_prepend_T_594}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6992 = out_prepend_594; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6993 = _out_T_6992; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_595 = _out_T_6993; // @[RegisterRouter.scala:87:24] wire out_rimask_702 = |_out_rimask_T_702; // @[RegisterRouter.scala:87:24] wire out_wimask_702 = &_out_wimask_T_702; // @[RegisterRouter.scala:87:24] wire out_romask_702 = |_out_romask_T_702; // @[RegisterRouter.scala:87:24] wire out_womask_702 = &_out_womask_T_702; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_702 = out_rivalid_1_556 & out_rimask_702; // @[RegisterRouter.scala:87:24] wire _out_T_6995 = out_f_rivalid_702; // @[RegisterRouter.scala:87:24] wire out_f_roready_702 = out_roready_1_556 & out_romask_702; // @[RegisterRouter.scala:87:24] wire _out_T_6996 = out_f_roready_702; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_702 = out_wivalid_1_556 & out_wimask_702; // @[RegisterRouter.scala:87:24] wire out_f_woready_702 = out_woready_1_556 & out_womask_702; // @[RegisterRouter.scala:87:24] wire _out_T_6997 = ~out_rimask_702; // @[RegisterRouter.scala:87:24] wire _out_T_6998 = ~out_wimask_702; // @[RegisterRouter.scala:87:24] wire _out_T_6999 = ~out_romask_702; // @[RegisterRouter.scala:87:24] wire _out_T_7000 = ~out_womask_702; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_595 = {hi_268, flags_0_go, _out_prepend_T_595}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7001 = out_prepend_595; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7002 = _out_T_7001; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_596 = _out_T_7002; // @[RegisterRouter.scala:87:24] wire out_rimask_703 = |_out_rimask_T_703; // @[RegisterRouter.scala:87:24] wire out_wimask_703 = &_out_wimask_T_703; // @[RegisterRouter.scala:87:24] wire out_romask_703 = |_out_romask_T_703; // @[RegisterRouter.scala:87:24] wire out_womask_703 = &_out_womask_T_703; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_703 = out_rivalid_1_557 & out_rimask_703; // @[RegisterRouter.scala:87:24] wire _out_T_7004 = out_f_rivalid_703; // @[RegisterRouter.scala:87:24] wire out_f_roready_703 = out_roready_1_557 & out_romask_703; // @[RegisterRouter.scala:87:24] wire _out_T_7005 = out_f_roready_703; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_703 = out_wivalid_1_557 & out_wimask_703; // @[RegisterRouter.scala:87:24] wire out_f_woready_703 = out_woready_1_557 & out_womask_703; // @[RegisterRouter.scala:87:24] wire _out_T_7006 = ~out_rimask_703; // @[RegisterRouter.scala:87:24] wire _out_T_7007 = ~out_wimask_703; // @[RegisterRouter.scala:87:24] wire _out_T_7008 = ~out_romask_703; // @[RegisterRouter.scala:87:24] wire _out_T_7009 = ~out_womask_703; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_596 = {hi_269, flags_0_go, _out_prepend_T_596}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7010 = out_prepend_596; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7011 = _out_T_7010; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_597 = _out_T_7011; // @[RegisterRouter.scala:87:24] wire out_rimask_704 = |_out_rimask_T_704; // @[RegisterRouter.scala:87:24] wire out_wimask_704 = &_out_wimask_T_704; // @[RegisterRouter.scala:87:24] wire out_romask_704 = |_out_romask_T_704; // @[RegisterRouter.scala:87:24] wire out_womask_704 = &_out_womask_T_704; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_704 = out_rivalid_1_558 & out_rimask_704; // @[RegisterRouter.scala:87:24] wire _out_T_7013 = out_f_rivalid_704; // @[RegisterRouter.scala:87:24] wire out_f_roready_704 = out_roready_1_558 & out_romask_704; // @[RegisterRouter.scala:87:24] wire _out_T_7014 = out_f_roready_704; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_704 = out_wivalid_1_558 & out_wimask_704; // @[RegisterRouter.scala:87:24] wire out_f_woready_704 = out_woready_1_558 & out_womask_704; // @[RegisterRouter.scala:87:24] wire _out_T_7015 = ~out_rimask_704; // @[RegisterRouter.scala:87:24] wire _out_T_7016 = ~out_wimask_704; // @[RegisterRouter.scala:87:24] wire _out_T_7017 = ~out_romask_704; // @[RegisterRouter.scala:87:24] wire _out_T_7018 = ~out_womask_704; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_597 = {hi_270, flags_0_go, _out_prepend_T_597}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7019 = out_prepend_597; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7020 = _out_T_7019; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_598 = _out_T_7020; // @[RegisterRouter.scala:87:24] wire out_rimask_705 = |_out_rimask_T_705; // @[RegisterRouter.scala:87:24] wire out_wimask_705 = &_out_wimask_T_705; // @[RegisterRouter.scala:87:24] wire out_romask_705 = |_out_romask_T_705; // @[RegisterRouter.scala:87:24] wire out_womask_705 = &_out_womask_T_705; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_705 = out_rivalid_1_559 & out_rimask_705; // @[RegisterRouter.scala:87:24] wire _out_T_7022 = out_f_rivalid_705; // @[RegisterRouter.scala:87:24] wire out_f_roready_705 = out_roready_1_559 & out_romask_705; // @[RegisterRouter.scala:87:24] wire _out_T_7023 = out_f_roready_705; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_705 = out_wivalid_1_559 & out_wimask_705; // @[RegisterRouter.scala:87:24] wire out_f_woready_705 = out_woready_1_559 & out_womask_705; // @[RegisterRouter.scala:87:24] wire _out_T_7024 = ~out_rimask_705; // @[RegisterRouter.scala:87:24] wire _out_T_7025 = ~out_wimask_705; // @[RegisterRouter.scala:87:24] wire _out_T_7026 = ~out_romask_705; // @[RegisterRouter.scala:87:24] wire _out_T_7027 = ~out_womask_705; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_598 = {hi_271, flags_0_go, _out_prepend_T_598}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7028 = out_prepend_598; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7029 = _out_T_7028; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_599 = _out_T_7029; // @[RegisterRouter.scala:87:24] wire out_rimask_706 = |_out_rimask_T_706; // @[RegisterRouter.scala:87:24] wire out_wimask_706 = &_out_wimask_T_706; // @[RegisterRouter.scala:87:24] wire out_romask_706 = |_out_romask_T_706; // @[RegisterRouter.scala:87:24] wire out_womask_706 = &_out_womask_T_706; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_706 = out_rivalid_1_560 & out_rimask_706; // @[RegisterRouter.scala:87:24] wire _out_T_7031 = out_f_rivalid_706; // @[RegisterRouter.scala:87:24] wire out_f_roready_706 = out_roready_1_560 & out_romask_706; // @[RegisterRouter.scala:87:24] wire _out_T_7032 = out_f_roready_706; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_706 = out_wivalid_1_560 & out_wimask_706; // @[RegisterRouter.scala:87:24] wire out_f_woready_706 = out_woready_1_560 & out_womask_706; // @[RegisterRouter.scala:87:24] wire _out_T_7033 = ~out_rimask_706; // @[RegisterRouter.scala:87:24] wire _out_T_7034 = ~out_wimask_706; // @[RegisterRouter.scala:87:24] wire _out_T_7035 = ~out_romask_706; // @[RegisterRouter.scala:87:24] wire _out_T_7036 = ~out_womask_706; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_599 = {hi_272, flags_0_go, _out_prepend_T_599}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7037 = out_prepend_599; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7038 = _out_T_7037; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_161 = _out_T_7038; // @[MuxLiteral.scala:49:48] wire out_rimask_707 = |_out_rimask_T_707; // @[RegisterRouter.scala:87:24] wire out_wimask_707 = &_out_wimask_T_707; // @[RegisterRouter.scala:87:24] wire out_romask_707 = |_out_romask_T_707; // @[RegisterRouter.scala:87:24] wire out_womask_707 = &_out_womask_T_707; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_707 = out_rivalid_1_561 & out_rimask_707; // @[RegisterRouter.scala:87:24] wire _out_T_7040 = out_f_rivalid_707; // @[RegisterRouter.scala:87:24] wire out_f_roready_707 = out_roready_1_561 & out_romask_707; // @[RegisterRouter.scala:87:24] wire _out_T_7041 = out_f_roready_707; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_707 = out_wivalid_1_561 & out_wimask_707; // @[RegisterRouter.scala:87:24] wire out_f_woready_707 = out_woready_1_561 & out_womask_707; // @[RegisterRouter.scala:87:24] wire _out_T_7042 = ~out_rimask_707; // @[RegisterRouter.scala:87:24] wire _out_T_7043 = ~out_wimask_707; // @[RegisterRouter.scala:87:24] wire _out_T_7044 = ~out_romask_707; // @[RegisterRouter.scala:87:24] wire _out_T_7045 = ~out_womask_707; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7047 = _out_T_7046; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_600 = _out_T_7047; // @[RegisterRouter.scala:87:24] wire out_rimask_708 = |_out_rimask_T_708; // @[RegisterRouter.scala:87:24] wire out_wimask_708 = &_out_wimask_T_708; // @[RegisterRouter.scala:87:24] wire out_romask_708 = |_out_romask_T_708; // @[RegisterRouter.scala:87:24] wire out_womask_708 = &_out_womask_T_708; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_708 = out_rivalid_1_562 & out_rimask_708; // @[RegisterRouter.scala:87:24] wire _out_T_7049 = out_f_rivalid_708; // @[RegisterRouter.scala:87:24] wire out_f_roready_708 = out_roready_1_562 & out_romask_708; // @[RegisterRouter.scala:87:24] wire _out_T_7050 = out_f_roready_708; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_708 = out_wivalid_1_562 & out_wimask_708; // @[RegisterRouter.scala:87:24] wire out_f_woready_708 = out_woready_1_562 & out_womask_708; // @[RegisterRouter.scala:87:24] wire _out_T_7051 = ~out_rimask_708; // @[RegisterRouter.scala:87:24] wire _out_T_7052 = ~out_wimask_708; // @[RegisterRouter.scala:87:24] wire _out_T_7053 = ~out_romask_708; // @[RegisterRouter.scala:87:24] wire _out_T_7054 = ~out_womask_708; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_600 = {hi_418, flags_0_go, _out_prepend_T_600}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7055 = out_prepend_600; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7056 = _out_T_7055; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_601 = _out_T_7056; // @[RegisterRouter.scala:87:24] wire out_rimask_709 = |_out_rimask_T_709; // @[RegisterRouter.scala:87:24] wire out_wimask_709 = &_out_wimask_T_709; // @[RegisterRouter.scala:87:24] wire out_romask_709 = |_out_romask_T_709; // @[RegisterRouter.scala:87:24] wire out_womask_709 = &_out_womask_T_709; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_709 = out_rivalid_1_563 & out_rimask_709; // @[RegisterRouter.scala:87:24] wire _out_T_7058 = out_f_rivalid_709; // @[RegisterRouter.scala:87:24] wire out_f_roready_709 = out_roready_1_563 & out_romask_709; // @[RegisterRouter.scala:87:24] wire _out_T_7059 = out_f_roready_709; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_709 = out_wivalid_1_563 & out_wimask_709; // @[RegisterRouter.scala:87:24] wire out_f_woready_709 = out_woready_1_563 & out_womask_709; // @[RegisterRouter.scala:87:24] wire _out_T_7060 = ~out_rimask_709; // @[RegisterRouter.scala:87:24] wire _out_T_7061 = ~out_wimask_709; // @[RegisterRouter.scala:87:24] wire _out_T_7062 = ~out_romask_709; // @[RegisterRouter.scala:87:24] wire _out_T_7063 = ~out_womask_709; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_601 = {hi_419, flags_0_go, _out_prepend_T_601}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7064 = out_prepend_601; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7065 = _out_T_7064; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_602 = _out_T_7065; // @[RegisterRouter.scala:87:24] wire out_rimask_710 = |_out_rimask_T_710; // @[RegisterRouter.scala:87:24] wire out_wimask_710 = &_out_wimask_T_710; // @[RegisterRouter.scala:87:24] wire out_romask_710 = |_out_romask_T_710; // @[RegisterRouter.scala:87:24] wire out_womask_710 = &_out_womask_T_710; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_710 = out_rivalid_1_564 & out_rimask_710; // @[RegisterRouter.scala:87:24] wire _out_T_7067 = out_f_rivalid_710; // @[RegisterRouter.scala:87:24] wire out_f_roready_710 = out_roready_1_564 & out_romask_710; // @[RegisterRouter.scala:87:24] wire _out_T_7068 = out_f_roready_710; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_710 = out_wivalid_1_564 & out_wimask_710; // @[RegisterRouter.scala:87:24] wire out_f_woready_710 = out_woready_1_564 & out_womask_710; // @[RegisterRouter.scala:87:24] wire _out_T_7069 = ~out_rimask_710; // @[RegisterRouter.scala:87:24] wire _out_T_7070 = ~out_wimask_710; // @[RegisterRouter.scala:87:24] wire _out_T_7071 = ~out_romask_710; // @[RegisterRouter.scala:87:24] wire _out_T_7072 = ~out_womask_710; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_602 = {hi_420, flags_0_go, _out_prepend_T_602}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7073 = out_prepend_602; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7074 = _out_T_7073; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_603 = _out_T_7074; // @[RegisterRouter.scala:87:24] wire out_rimask_711 = |_out_rimask_T_711; // @[RegisterRouter.scala:87:24] wire out_wimask_711 = &_out_wimask_T_711; // @[RegisterRouter.scala:87:24] wire out_romask_711 = |_out_romask_T_711; // @[RegisterRouter.scala:87:24] wire out_womask_711 = &_out_womask_T_711; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_711 = out_rivalid_1_565 & out_rimask_711; // @[RegisterRouter.scala:87:24] wire _out_T_7076 = out_f_rivalid_711; // @[RegisterRouter.scala:87:24] wire out_f_roready_711 = out_roready_1_565 & out_romask_711; // @[RegisterRouter.scala:87:24] wire _out_T_7077 = out_f_roready_711; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_711 = out_wivalid_1_565 & out_wimask_711; // @[RegisterRouter.scala:87:24] wire out_f_woready_711 = out_woready_1_565 & out_womask_711; // @[RegisterRouter.scala:87:24] wire _out_T_7078 = ~out_rimask_711; // @[RegisterRouter.scala:87:24] wire _out_T_7079 = ~out_wimask_711; // @[RegisterRouter.scala:87:24] wire _out_T_7080 = ~out_romask_711; // @[RegisterRouter.scala:87:24] wire _out_T_7081 = ~out_womask_711; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_603 = {hi_421, flags_0_go, _out_prepend_T_603}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7082 = out_prepend_603; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7083 = _out_T_7082; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_604 = _out_T_7083; // @[RegisterRouter.scala:87:24] wire out_rimask_712 = |_out_rimask_T_712; // @[RegisterRouter.scala:87:24] wire out_wimask_712 = &_out_wimask_T_712; // @[RegisterRouter.scala:87:24] wire out_romask_712 = |_out_romask_T_712; // @[RegisterRouter.scala:87:24] wire out_womask_712 = &_out_womask_T_712; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_712 = out_rivalid_1_566 & out_rimask_712; // @[RegisterRouter.scala:87:24] wire _out_T_7085 = out_f_rivalid_712; // @[RegisterRouter.scala:87:24] wire out_f_roready_712 = out_roready_1_566 & out_romask_712; // @[RegisterRouter.scala:87:24] wire _out_T_7086 = out_f_roready_712; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_712 = out_wivalid_1_566 & out_wimask_712; // @[RegisterRouter.scala:87:24] wire out_f_woready_712 = out_woready_1_566 & out_womask_712; // @[RegisterRouter.scala:87:24] wire _out_T_7087 = ~out_rimask_712; // @[RegisterRouter.scala:87:24] wire _out_T_7088 = ~out_wimask_712; // @[RegisterRouter.scala:87:24] wire _out_T_7089 = ~out_romask_712; // @[RegisterRouter.scala:87:24] wire _out_T_7090 = ~out_womask_712; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_604 = {hi_422, flags_0_go, _out_prepend_T_604}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7091 = out_prepend_604; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7092 = _out_T_7091; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_605 = _out_T_7092; // @[RegisterRouter.scala:87:24] wire out_rimask_713 = |_out_rimask_T_713; // @[RegisterRouter.scala:87:24] wire out_wimask_713 = &_out_wimask_T_713; // @[RegisterRouter.scala:87:24] wire out_romask_713 = |_out_romask_T_713; // @[RegisterRouter.scala:87:24] wire out_womask_713 = &_out_womask_T_713; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_713 = out_rivalid_1_567 & out_rimask_713; // @[RegisterRouter.scala:87:24] wire _out_T_7094 = out_f_rivalid_713; // @[RegisterRouter.scala:87:24] wire out_f_roready_713 = out_roready_1_567 & out_romask_713; // @[RegisterRouter.scala:87:24] wire _out_T_7095 = out_f_roready_713; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_713 = out_wivalid_1_567 & out_wimask_713; // @[RegisterRouter.scala:87:24] wire out_f_woready_713 = out_woready_1_567 & out_womask_713; // @[RegisterRouter.scala:87:24] wire _out_T_7096 = ~out_rimask_713; // @[RegisterRouter.scala:87:24] wire _out_T_7097 = ~out_wimask_713; // @[RegisterRouter.scala:87:24] wire _out_T_7098 = ~out_romask_713; // @[RegisterRouter.scala:87:24] wire _out_T_7099 = ~out_womask_713; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_605 = {hi_423, flags_0_go, _out_prepend_T_605}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7100 = out_prepend_605; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7101 = _out_T_7100; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_606 = _out_T_7101; // @[RegisterRouter.scala:87:24] wire out_rimask_714 = |_out_rimask_T_714; // @[RegisterRouter.scala:87:24] wire out_wimask_714 = &_out_wimask_T_714; // @[RegisterRouter.scala:87:24] wire out_romask_714 = |_out_romask_T_714; // @[RegisterRouter.scala:87:24] wire out_womask_714 = &_out_womask_T_714; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_714 = out_rivalid_1_568 & out_rimask_714; // @[RegisterRouter.scala:87:24] wire _out_T_7103 = out_f_rivalid_714; // @[RegisterRouter.scala:87:24] wire out_f_roready_714 = out_roready_1_568 & out_romask_714; // @[RegisterRouter.scala:87:24] wire _out_T_7104 = out_f_roready_714; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_714 = out_wivalid_1_568 & out_wimask_714; // @[RegisterRouter.scala:87:24] wire out_f_woready_714 = out_woready_1_568 & out_womask_714; // @[RegisterRouter.scala:87:24] wire _out_T_7105 = ~out_rimask_714; // @[RegisterRouter.scala:87:24] wire _out_T_7106 = ~out_wimask_714; // @[RegisterRouter.scala:87:24] wire _out_T_7107 = ~out_romask_714; // @[RegisterRouter.scala:87:24] wire _out_T_7108 = ~out_womask_714; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_606 = {hi_424, flags_0_go, _out_prepend_T_606}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7109 = out_prepend_606; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7110 = _out_T_7109; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_180 = _out_T_7110; // @[MuxLiteral.scala:49:48] wire out_rimask_715 = |_out_rimask_T_715; // @[RegisterRouter.scala:87:24] wire out_wimask_715 = &_out_wimask_T_715; // @[RegisterRouter.scala:87:24] wire out_romask_715 = |_out_romask_T_715; // @[RegisterRouter.scala:87:24] wire out_womask_715 = &_out_womask_T_715; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_715 = out_rivalid_1_569 & out_rimask_715; // @[RegisterRouter.scala:87:24] wire _out_T_7112 = out_f_rivalid_715; // @[RegisterRouter.scala:87:24] wire out_f_roready_715 = out_roready_1_569 & out_romask_715; // @[RegisterRouter.scala:87:24] wire _out_T_7113 = out_f_roready_715; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_715 = out_wivalid_1_569 & out_wimask_715; // @[RegisterRouter.scala:87:24] wire out_f_woready_715 = out_woready_1_569 & out_womask_715; // @[RegisterRouter.scala:87:24] wire _out_T_7114 = ~out_rimask_715; // @[RegisterRouter.scala:87:24] wire _out_T_7115 = ~out_wimask_715; // @[RegisterRouter.scala:87:24] wire _out_T_7116 = ~out_romask_715; // @[RegisterRouter.scala:87:24] wire _out_T_7117 = ~out_womask_715; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7119 = _out_T_7118; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_607 = _out_T_7119; // @[RegisterRouter.scala:87:24] wire out_rimask_716 = |_out_rimask_T_716; // @[RegisterRouter.scala:87:24] wire out_wimask_716 = &_out_wimask_T_716; // @[RegisterRouter.scala:87:24] wire out_romask_716 = |_out_romask_T_716; // @[RegisterRouter.scala:87:24] wire out_womask_716 = &_out_womask_T_716; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_716 = out_rivalid_1_570 & out_rimask_716; // @[RegisterRouter.scala:87:24] wire _out_T_7121 = out_f_rivalid_716; // @[RegisterRouter.scala:87:24] wire out_f_roready_716 = out_roready_1_570 & out_romask_716; // @[RegisterRouter.scala:87:24] wire _out_T_7122 = out_f_roready_716; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_716 = out_wivalid_1_570 & out_wimask_716; // @[RegisterRouter.scala:87:24] wire out_f_woready_716 = out_woready_1_570 & out_womask_716; // @[RegisterRouter.scala:87:24] wire _out_T_7123 = ~out_rimask_716; // @[RegisterRouter.scala:87:24] wire _out_T_7124 = ~out_wimask_716; // @[RegisterRouter.scala:87:24] wire _out_T_7125 = ~out_romask_716; // @[RegisterRouter.scala:87:24] wire _out_T_7126 = ~out_womask_716; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_607 = {hi_170, flags_0_go, _out_prepend_T_607}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7127 = out_prepend_607; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7128 = _out_T_7127; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_608 = _out_T_7128; // @[RegisterRouter.scala:87:24] wire out_rimask_717 = |_out_rimask_T_717; // @[RegisterRouter.scala:87:24] wire out_wimask_717 = &_out_wimask_T_717; // @[RegisterRouter.scala:87:24] wire out_romask_717 = |_out_romask_T_717; // @[RegisterRouter.scala:87:24] wire out_womask_717 = &_out_womask_T_717; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_717 = out_rivalid_1_571 & out_rimask_717; // @[RegisterRouter.scala:87:24] wire _out_T_7130 = out_f_rivalid_717; // @[RegisterRouter.scala:87:24] wire out_f_roready_717 = out_roready_1_571 & out_romask_717; // @[RegisterRouter.scala:87:24] wire _out_T_7131 = out_f_roready_717; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_717 = out_wivalid_1_571 & out_wimask_717; // @[RegisterRouter.scala:87:24] wire out_f_woready_717 = out_woready_1_571 & out_womask_717; // @[RegisterRouter.scala:87:24] wire _out_T_7132 = ~out_rimask_717; // @[RegisterRouter.scala:87:24] wire _out_T_7133 = ~out_wimask_717; // @[RegisterRouter.scala:87:24] wire _out_T_7134 = ~out_romask_717; // @[RegisterRouter.scala:87:24] wire _out_T_7135 = ~out_womask_717; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_608 = {hi_171, flags_0_go, _out_prepend_T_608}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7136 = out_prepend_608; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7137 = _out_T_7136; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_609 = _out_T_7137; // @[RegisterRouter.scala:87:24] wire out_rimask_718 = |_out_rimask_T_718; // @[RegisterRouter.scala:87:24] wire out_wimask_718 = &_out_wimask_T_718; // @[RegisterRouter.scala:87:24] wire out_romask_718 = |_out_romask_T_718; // @[RegisterRouter.scala:87:24] wire out_womask_718 = &_out_womask_T_718; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_718 = out_rivalid_1_572 & out_rimask_718; // @[RegisterRouter.scala:87:24] wire _out_T_7139 = out_f_rivalid_718; // @[RegisterRouter.scala:87:24] wire out_f_roready_718 = out_roready_1_572 & out_romask_718; // @[RegisterRouter.scala:87:24] wire _out_T_7140 = out_f_roready_718; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_718 = out_wivalid_1_572 & out_wimask_718; // @[RegisterRouter.scala:87:24] wire out_f_woready_718 = out_woready_1_572 & out_womask_718; // @[RegisterRouter.scala:87:24] wire _out_T_7141 = ~out_rimask_718; // @[RegisterRouter.scala:87:24] wire _out_T_7142 = ~out_wimask_718; // @[RegisterRouter.scala:87:24] wire _out_T_7143 = ~out_romask_718; // @[RegisterRouter.scala:87:24] wire _out_T_7144 = ~out_womask_718; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_609 = {hi_172, flags_0_go, _out_prepend_T_609}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7145 = out_prepend_609; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7146 = _out_T_7145; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_610 = _out_T_7146; // @[RegisterRouter.scala:87:24] wire out_rimask_719 = |_out_rimask_T_719; // @[RegisterRouter.scala:87:24] wire out_wimask_719 = &_out_wimask_T_719; // @[RegisterRouter.scala:87:24] wire out_romask_719 = |_out_romask_T_719; // @[RegisterRouter.scala:87:24] wire out_womask_719 = &_out_womask_T_719; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_719 = out_rivalid_1_573 & out_rimask_719; // @[RegisterRouter.scala:87:24] wire _out_T_7148 = out_f_rivalid_719; // @[RegisterRouter.scala:87:24] wire out_f_roready_719 = out_roready_1_573 & out_romask_719; // @[RegisterRouter.scala:87:24] wire _out_T_7149 = out_f_roready_719; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_719 = out_wivalid_1_573 & out_wimask_719; // @[RegisterRouter.scala:87:24] wire out_f_woready_719 = out_woready_1_573 & out_womask_719; // @[RegisterRouter.scala:87:24] wire _out_T_7150 = ~out_rimask_719; // @[RegisterRouter.scala:87:24] wire _out_T_7151 = ~out_wimask_719; // @[RegisterRouter.scala:87:24] wire _out_T_7152 = ~out_romask_719; // @[RegisterRouter.scala:87:24] wire _out_T_7153 = ~out_womask_719; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_610 = {hi_173, flags_0_go, _out_prepend_T_610}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7154 = out_prepend_610; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7155 = _out_T_7154; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_611 = _out_T_7155; // @[RegisterRouter.scala:87:24] wire out_rimask_720 = |_out_rimask_T_720; // @[RegisterRouter.scala:87:24] wire out_wimask_720 = &_out_wimask_T_720; // @[RegisterRouter.scala:87:24] wire out_romask_720 = |_out_romask_T_720; // @[RegisterRouter.scala:87:24] wire out_womask_720 = &_out_womask_T_720; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_720 = out_rivalid_1_574 & out_rimask_720; // @[RegisterRouter.scala:87:24] wire _out_T_7157 = out_f_rivalid_720; // @[RegisterRouter.scala:87:24] wire out_f_roready_720 = out_roready_1_574 & out_romask_720; // @[RegisterRouter.scala:87:24] wire _out_T_7158 = out_f_roready_720; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_720 = out_wivalid_1_574 & out_wimask_720; // @[RegisterRouter.scala:87:24] wire out_f_woready_720 = out_woready_1_574 & out_womask_720; // @[RegisterRouter.scala:87:24] wire _out_T_7159 = ~out_rimask_720; // @[RegisterRouter.scala:87:24] wire _out_T_7160 = ~out_wimask_720; // @[RegisterRouter.scala:87:24] wire _out_T_7161 = ~out_romask_720; // @[RegisterRouter.scala:87:24] wire _out_T_7162 = ~out_womask_720; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_611 = {hi_174, flags_0_go, _out_prepend_T_611}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7163 = out_prepend_611; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7164 = _out_T_7163; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_612 = _out_T_7164; // @[RegisterRouter.scala:87:24] wire out_rimask_721 = |_out_rimask_T_721; // @[RegisterRouter.scala:87:24] wire out_wimask_721 = &_out_wimask_T_721; // @[RegisterRouter.scala:87:24] wire out_romask_721 = |_out_romask_T_721; // @[RegisterRouter.scala:87:24] wire out_womask_721 = &_out_womask_T_721; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_721 = out_rivalid_1_575 & out_rimask_721; // @[RegisterRouter.scala:87:24] wire _out_T_7166 = out_f_rivalid_721; // @[RegisterRouter.scala:87:24] wire out_f_roready_721 = out_roready_1_575 & out_romask_721; // @[RegisterRouter.scala:87:24] wire _out_T_7167 = out_f_roready_721; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_721 = out_wivalid_1_575 & out_wimask_721; // @[RegisterRouter.scala:87:24] wire out_f_woready_721 = out_woready_1_575 & out_womask_721; // @[RegisterRouter.scala:87:24] wire _out_T_7168 = ~out_rimask_721; // @[RegisterRouter.scala:87:24] wire _out_T_7169 = ~out_wimask_721; // @[RegisterRouter.scala:87:24] wire _out_T_7170 = ~out_romask_721; // @[RegisterRouter.scala:87:24] wire _out_T_7171 = ~out_womask_721; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_612 = {hi_175, flags_0_go, _out_prepend_T_612}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7172 = out_prepend_612; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7173 = _out_T_7172; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_613 = _out_T_7173; // @[RegisterRouter.scala:87:24] wire out_rimask_722 = |_out_rimask_T_722; // @[RegisterRouter.scala:87:24] wire out_wimask_722 = &_out_wimask_T_722; // @[RegisterRouter.scala:87:24] wire out_romask_722 = |_out_romask_T_722; // @[RegisterRouter.scala:87:24] wire out_womask_722 = &_out_womask_T_722; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_722 = out_rivalid_1_576 & out_rimask_722; // @[RegisterRouter.scala:87:24] wire _out_T_7175 = out_f_rivalid_722; // @[RegisterRouter.scala:87:24] wire out_f_roready_722 = out_roready_1_576 & out_romask_722; // @[RegisterRouter.scala:87:24] wire _out_T_7176 = out_f_roready_722; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_722 = out_wivalid_1_576 & out_wimask_722; // @[RegisterRouter.scala:87:24] wire out_f_woready_722 = out_woready_1_576 & out_womask_722; // @[RegisterRouter.scala:87:24] wire _out_T_7177 = ~out_rimask_722; // @[RegisterRouter.scala:87:24] wire _out_T_7178 = ~out_wimask_722; // @[RegisterRouter.scala:87:24] wire _out_T_7179 = ~out_romask_722; // @[RegisterRouter.scala:87:24] wire _out_T_7180 = ~out_womask_722; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_613 = {hi_176, flags_0_go, _out_prepend_T_613}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7181 = out_prepend_613; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7182 = _out_T_7181; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_149 = _out_T_7182; // @[MuxLiteral.scala:49:48] wire out_rimask_723 = |_out_rimask_T_723; // @[RegisterRouter.scala:87:24] wire out_wimask_723 = &_out_wimask_T_723; // @[RegisterRouter.scala:87:24] wire out_romask_723 = |_out_romask_T_723; // @[RegisterRouter.scala:87:24] wire out_womask_723 = &_out_womask_T_723; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_723 = out_rivalid_1_577 & out_rimask_723; // @[RegisterRouter.scala:87:24] wire _out_T_7184 = out_f_rivalid_723; // @[RegisterRouter.scala:87:24] wire out_f_roready_723 = out_roready_1_577 & out_romask_723; // @[RegisterRouter.scala:87:24] wire _out_T_7185 = out_f_roready_723; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_723 = out_wivalid_1_577 & out_wimask_723; // @[RegisterRouter.scala:87:24] wire out_f_woready_723 = out_woready_1_577 & out_womask_723; // @[RegisterRouter.scala:87:24] wire _out_T_7186 = ~out_rimask_723; // @[RegisterRouter.scala:87:24] wire _out_T_7187 = ~out_wimask_723; // @[RegisterRouter.scala:87:24] wire _out_T_7188 = ~out_romask_723; // @[RegisterRouter.scala:87:24] wire _out_T_7189 = ~out_womask_723; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7191 = _out_T_7190; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_614 = _out_T_7191; // @[RegisterRouter.scala:87:24] wire out_rimask_724 = |_out_rimask_T_724; // @[RegisterRouter.scala:87:24] wire out_wimask_724 = &_out_wimask_T_724; // @[RegisterRouter.scala:87:24] wire out_romask_724 = |_out_romask_T_724; // @[RegisterRouter.scala:87:24] wire out_womask_724 = &_out_womask_T_724; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_724 = out_rivalid_1_578 & out_rimask_724; // @[RegisterRouter.scala:87:24] wire _out_T_7193 = out_f_rivalid_724; // @[RegisterRouter.scala:87:24] wire out_f_roready_724 = out_roready_1_578 & out_romask_724; // @[RegisterRouter.scala:87:24] wire _out_T_7194 = out_f_roready_724; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_724 = out_wivalid_1_578 & out_wimask_724; // @[RegisterRouter.scala:87:24] wire out_f_woready_724 = out_woready_1_578 & out_womask_724; // @[RegisterRouter.scala:87:24] wire _out_T_7195 = ~out_rimask_724; // @[RegisterRouter.scala:87:24] wire _out_T_7196 = ~out_wimask_724; // @[RegisterRouter.scala:87:24] wire _out_T_7197 = ~out_romask_724; // @[RegisterRouter.scala:87:24] wire _out_T_7198 = ~out_womask_724; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_614 = {hi_386, flags_0_go, _out_prepend_T_614}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7199 = out_prepend_614; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7200 = _out_T_7199; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_615 = _out_T_7200; // @[RegisterRouter.scala:87:24] wire out_rimask_725 = |_out_rimask_T_725; // @[RegisterRouter.scala:87:24] wire out_wimask_725 = &_out_wimask_T_725; // @[RegisterRouter.scala:87:24] wire out_romask_725 = |_out_romask_T_725; // @[RegisterRouter.scala:87:24] wire out_womask_725 = &_out_womask_T_725; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_725 = out_rivalid_1_579 & out_rimask_725; // @[RegisterRouter.scala:87:24] wire _out_T_7202 = out_f_rivalid_725; // @[RegisterRouter.scala:87:24] wire out_f_roready_725 = out_roready_1_579 & out_romask_725; // @[RegisterRouter.scala:87:24] wire _out_T_7203 = out_f_roready_725; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_725 = out_wivalid_1_579 & out_wimask_725; // @[RegisterRouter.scala:87:24] wire out_f_woready_725 = out_woready_1_579 & out_womask_725; // @[RegisterRouter.scala:87:24] wire _out_T_7204 = ~out_rimask_725; // @[RegisterRouter.scala:87:24] wire _out_T_7205 = ~out_wimask_725; // @[RegisterRouter.scala:87:24] wire _out_T_7206 = ~out_romask_725; // @[RegisterRouter.scala:87:24] wire _out_T_7207 = ~out_womask_725; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_615 = {hi_387, flags_0_go, _out_prepend_T_615}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7208 = out_prepend_615; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7209 = _out_T_7208; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_616 = _out_T_7209; // @[RegisterRouter.scala:87:24] wire out_rimask_726 = |_out_rimask_T_726; // @[RegisterRouter.scala:87:24] wire out_wimask_726 = &_out_wimask_T_726; // @[RegisterRouter.scala:87:24] wire out_romask_726 = |_out_romask_T_726; // @[RegisterRouter.scala:87:24] wire out_womask_726 = &_out_womask_T_726; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_726 = out_rivalid_1_580 & out_rimask_726; // @[RegisterRouter.scala:87:24] wire _out_T_7211 = out_f_rivalid_726; // @[RegisterRouter.scala:87:24] wire out_f_roready_726 = out_roready_1_580 & out_romask_726; // @[RegisterRouter.scala:87:24] wire _out_T_7212 = out_f_roready_726; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_726 = out_wivalid_1_580 & out_wimask_726; // @[RegisterRouter.scala:87:24] wire out_f_woready_726 = out_woready_1_580 & out_womask_726; // @[RegisterRouter.scala:87:24] wire _out_T_7213 = ~out_rimask_726; // @[RegisterRouter.scala:87:24] wire _out_T_7214 = ~out_wimask_726; // @[RegisterRouter.scala:87:24] wire _out_T_7215 = ~out_romask_726; // @[RegisterRouter.scala:87:24] wire _out_T_7216 = ~out_womask_726; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_616 = {hi_388, flags_0_go, _out_prepend_T_616}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7217 = out_prepend_616; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7218 = _out_T_7217; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_617 = _out_T_7218; // @[RegisterRouter.scala:87:24] wire out_rimask_727 = |_out_rimask_T_727; // @[RegisterRouter.scala:87:24] wire out_wimask_727 = &_out_wimask_T_727; // @[RegisterRouter.scala:87:24] wire out_romask_727 = |_out_romask_T_727; // @[RegisterRouter.scala:87:24] wire out_womask_727 = &_out_womask_T_727; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_727 = out_rivalid_1_581 & out_rimask_727; // @[RegisterRouter.scala:87:24] wire _out_T_7220 = out_f_rivalid_727; // @[RegisterRouter.scala:87:24] wire out_f_roready_727 = out_roready_1_581 & out_romask_727; // @[RegisterRouter.scala:87:24] wire _out_T_7221 = out_f_roready_727; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_727 = out_wivalid_1_581 & out_wimask_727; // @[RegisterRouter.scala:87:24] wire out_f_woready_727 = out_woready_1_581 & out_womask_727; // @[RegisterRouter.scala:87:24] wire _out_T_7222 = ~out_rimask_727; // @[RegisterRouter.scala:87:24] wire _out_T_7223 = ~out_wimask_727; // @[RegisterRouter.scala:87:24] wire _out_T_7224 = ~out_romask_727; // @[RegisterRouter.scala:87:24] wire _out_T_7225 = ~out_womask_727; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_617 = {hi_389, flags_0_go, _out_prepend_T_617}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7226 = out_prepend_617; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7227 = _out_T_7226; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_618 = _out_T_7227; // @[RegisterRouter.scala:87:24] wire out_rimask_728 = |_out_rimask_T_728; // @[RegisterRouter.scala:87:24] wire out_wimask_728 = &_out_wimask_T_728; // @[RegisterRouter.scala:87:24] wire out_romask_728 = |_out_romask_T_728; // @[RegisterRouter.scala:87:24] wire out_womask_728 = &_out_womask_T_728; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_728 = out_rivalid_1_582 & out_rimask_728; // @[RegisterRouter.scala:87:24] wire _out_T_7229 = out_f_rivalid_728; // @[RegisterRouter.scala:87:24] wire out_f_roready_728 = out_roready_1_582 & out_romask_728; // @[RegisterRouter.scala:87:24] wire _out_T_7230 = out_f_roready_728; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_728 = out_wivalid_1_582 & out_wimask_728; // @[RegisterRouter.scala:87:24] wire out_f_woready_728 = out_woready_1_582 & out_womask_728; // @[RegisterRouter.scala:87:24] wire _out_T_7231 = ~out_rimask_728; // @[RegisterRouter.scala:87:24] wire _out_T_7232 = ~out_wimask_728; // @[RegisterRouter.scala:87:24] wire _out_T_7233 = ~out_romask_728; // @[RegisterRouter.scala:87:24] wire _out_T_7234 = ~out_womask_728; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_618 = {hi_390, flags_0_go, _out_prepend_T_618}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7235 = out_prepend_618; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7236 = _out_T_7235; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_619 = _out_T_7236; // @[RegisterRouter.scala:87:24] wire out_rimask_729 = |_out_rimask_T_729; // @[RegisterRouter.scala:87:24] wire out_wimask_729 = &_out_wimask_T_729; // @[RegisterRouter.scala:87:24] wire out_romask_729 = |_out_romask_T_729; // @[RegisterRouter.scala:87:24] wire out_womask_729 = &_out_womask_T_729; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_729 = out_rivalid_1_583 & out_rimask_729; // @[RegisterRouter.scala:87:24] wire _out_T_7238 = out_f_rivalid_729; // @[RegisterRouter.scala:87:24] wire out_f_roready_729 = out_roready_1_583 & out_romask_729; // @[RegisterRouter.scala:87:24] wire _out_T_7239 = out_f_roready_729; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_729 = out_wivalid_1_583 & out_wimask_729; // @[RegisterRouter.scala:87:24] wire out_f_woready_729 = out_woready_1_583 & out_womask_729; // @[RegisterRouter.scala:87:24] wire _out_T_7240 = ~out_rimask_729; // @[RegisterRouter.scala:87:24] wire _out_T_7241 = ~out_wimask_729; // @[RegisterRouter.scala:87:24] wire _out_T_7242 = ~out_romask_729; // @[RegisterRouter.scala:87:24] wire _out_T_7243 = ~out_womask_729; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_619 = {hi_391, flags_0_go, _out_prepend_T_619}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7244 = out_prepend_619; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7245 = _out_T_7244; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_620 = _out_T_7245; // @[RegisterRouter.scala:87:24] wire out_rimask_730 = |_out_rimask_T_730; // @[RegisterRouter.scala:87:24] wire out_wimask_730 = &_out_wimask_T_730; // @[RegisterRouter.scala:87:24] wire out_romask_730 = |_out_romask_T_730; // @[RegisterRouter.scala:87:24] wire out_womask_730 = &_out_womask_T_730; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_730 = out_rivalid_1_584 & out_rimask_730; // @[RegisterRouter.scala:87:24] wire _out_T_7247 = out_f_rivalid_730; // @[RegisterRouter.scala:87:24] wire out_f_roready_730 = out_roready_1_584 & out_romask_730; // @[RegisterRouter.scala:87:24] wire _out_T_7248 = out_f_roready_730; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_730 = out_wivalid_1_584 & out_wimask_730; // @[RegisterRouter.scala:87:24] wire out_f_woready_730 = out_woready_1_584 & out_womask_730; // @[RegisterRouter.scala:87:24] wire _out_T_7249 = ~out_rimask_730; // @[RegisterRouter.scala:87:24] wire _out_T_7250 = ~out_wimask_730; // @[RegisterRouter.scala:87:24] wire _out_T_7251 = ~out_romask_730; // @[RegisterRouter.scala:87:24] wire _out_T_7252 = ~out_womask_730; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_620 = {hi_392, flags_0_go, _out_prepend_T_620}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7253 = out_prepend_620; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7254 = _out_T_7253; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_176 = _out_T_7254; // @[MuxLiteral.scala:49:48] wire out_rimask_731 = |_out_rimask_T_731; // @[RegisterRouter.scala:87:24] wire out_wimask_731 = &_out_wimask_T_731; // @[RegisterRouter.scala:87:24] wire out_romask_731 = |_out_romask_T_731; // @[RegisterRouter.scala:87:24] wire out_womask_731 = &_out_womask_T_731; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_731 = out_rivalid_1_585 & out_rimask_731; // @[RegisterRouter.scala:87:24] wire _out_T_7256 = out_f_rivalid_731; // @[RegisterRouter.scala:87:24] wire out_f_roready_731 = out_roready_1_585 & out_romask_731; // @[RegisterRouter.scala:87:24] wire _out_T_7257 = out_f_roready_731; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_731 = out_wivalid_1_585 & out_wimask_731; // @[RegisterRouter.scala:87:24] wire out_f_woready_731 = out_woready_1_585 & out_womask_731; // @[RegisterRouter.scala:87:24] wire _out_T_7258 = ~out_rimask_731; // @[RegisterRouter.scala:87:24] wire _out_T_7259 = ~out_wimask_731; // @[RegisterRouter.scala:87:24] wire _out_T_7260 = ~out_romask_731; // @[RegisterRouter.scala:87:24] wire _out_T_7261 = ~out_womask_731; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7263 = _out_T_7262; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_621 = _out_T_7263; // @[RegisterRouter.scala:87:24] wire out_rimask_732 = |_out_rimask_T_732; // @[RegisterRouter.scala:87:24] wire out_wimask_732 = &_out_wimask_T_732; // @[RegisterRouter.scala:87:24] wire out_romask_732 = |_out_romask_T_732; // @[RegisterRouter.scala:87:24] wire out_womask_732 = &_out_womask_T_732; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_732 = out_rivalid_1_586 & out_rimask_732; // @[RegisterRouter.scala:87:24] wire _out_T_7265 = out_f_rivalid_732; // @[RegisterRouter.scala:87:24] wire out_f_roready_732 = out_roready_1_586 & out_romask_732; // @[RegisterRouter.scala:87:24] wire _out_T_7266 = out_f_roready_732; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_732 = out_wivalid_1_586 & out_wimask_732; // @[RegisterRouter.scala:87:24] wire out_f_woready_732 = out_woready_1_586 & out_womask_732; // @[RegisterRouter.scala:87:24] wire _out_T_7267 = ~out_rimask_732; // @[RegisterRouter.scala:87:24] wire _out_T_7268 = ~out_wimask_732; // @[RegisterRouter.scala:87:24] wire _out_T_7269 = ~out_romask_732; // @[RegisterRouter.scala:87:24] wire _out_T_7270 = ~out_womask_732; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_621 = {hi_506, flags_0_go, _out_prepend_T_621}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7271 = out_prepend_621; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7272 = _out_T_7271; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_622 = _out_T_7272; // @[RegisterRouter.scala:87:24] wire out_rimask_733 = |_out_rimask_T_733; // @[RegisterRouter.scala:87:24] wire out_wimask_733 = &_out_wimask_T_733; // @[RegisterRouter.scala:87:24] wire out_romask_733 = |_out_romask_T_733; // @[RegisterRouter.scala:87:24] wire out_womask_733 = &_out_womask_T_733; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_733 = out_rivalid_1_587 & out_rimask_733; // @[RegisterRouter.scala:87:24] wire _out_T_7274 = out_f_rivalid_733; // @[RegisterRouter.scala:87:24] wire out_f_roready_733 = out_roready_1_587 & out_romask_733; // @[RegisterRouter.scala:87:24] wire _out_T_7275 = out_f_roready_733; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_733 = out_wivalid_1_587 & out_wimask_733; // @[RegisterRouter.scala:87:24] wire out_f_woready_733 = out_woready_1_587 & out_womask_733; // @[RegisterRouter.scala:87:24] wire _out_T_7276 = ~out_rimask_733; // @[RegisterRouter.scala:87:24] wire _out_T_7277 = ~out_wimask_733; // @[RegisterRouter.scala:87:24] wire _out_T_7278 = ~out_romask_733; // @[RegisterRouter.scala:87:24] wire _out_T_7279 = ~out_womask_733; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_622 = {hi_507, flags_0_go, _out_prepend_T_622}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7280 = out_prepend_622; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7281 = _out_T_7280; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_623 = _out_T_7281; // @[RegisterRouter.scala:87:24] wire out_rimask_734 = |_out_rimask_T_734; // @[RegisterRouter.scala:87:24] wire out_wimask_734 = &_out_wimask_T_734; // @[RegisterRouter.scala:87:24] wire out_romask_734 = |_out_romask_T_734; // @[RegisterRouter.scala:87:24] wire out_womask_734 = &_out_womask_T_734; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_734 = out_rivalid_1_588 & out_rimask_734; // @[RegisterRouter.scala:87:24] wire _out_T_7283 = out_f_rivalid_734; // @[RegisterRouter.scala:87:24] wire out_f_roready_734 = out_roready_1_588 & out_romask_734; // @[RegisterRouter.scala:87:24] wire _out_T_7284 = out_f_roready_734; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_734 = out_wivalid_1_588 & out_wimask_734; // @[RegisterRouter.scala:87:24] wire out_f_woready_734 = out_woready_1_588 & out_womask_734; // @[RegisterRouter.scala:87:24] wire _out_T_7285 = ~out_rimask_734; // @[RegisterRouter.scala:87:24] wire _out_T_7286 = ~out_wimask_734; // @[RegisterRouter.scala:87:24] wire _out_T_7287 = ~out_romask_734; // @[RegisterRouter.scala:87:24] wire _out_T_7288 = ~out_womask_734; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_623 = {hi_508, flags_0_go, _out_prepend_T_623}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7289 = out_prepend_623; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7290 = _out_T_7289; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_624 = _out_T_7290; // @[RegisterRouter.scala:87:24] wire out_rimask_735 = |_out_rimask_T_735; // @[RegisterRouter.scala:87:24] wire out_wimask_735 = &_out_wimask_T_735; // @[RegisterRouter.scala:87:24] wire out_romask_735 = |_out_romask_T_735; // @[RegisterRouter.scala:87:24] wire out_womask_735 = &_out_womask_T_735; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_735 = out_rivalid_1_589 & out_rimask_735; // @[RegisterRouter.scala:87:24] wire _out_T_7292 = out_f_rivalid_735; // @[RegisterRouter.scala:87:24] wire out_f_roready_735 = out_roready_1_589 & out_romask_735; // @[RegisterRouter.scala:87:24] wire _out_T_7293 = out_f_roready_735; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_735 = out_wivalid_1_589 & out_wimask_735; // @[RegisterRouter.scala:87:24] wire out_f_woready_735 = out_woready_1_589 & out_womask_735; // @[RegisterRouter.scala:87:24] wire _out_T_7294 = ~out_rimask_735; // @[RegisterRouter.scala:87:24] wire _out_T_7295 = ~out_wimask_735; // @[RegisterRouter.scala:87:24] wire _out_T_7296 = ~out_romask_735; // @[RegisterRouter.scala:87:24] wire _out_T_7297 = ~out_womask_735; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_624 = {hi_509, flags_0_go, _out_prepend_T_624}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7298 = out_prepend_624; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7299 = _out_T_7298; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_625 = _out_T_7299; // @[RegisterRouter.scala:87:24] wire out_rimask_736 = |_out_rimask_T_736; // @[RegisterRouter.scala:87:24] wire out_wimask_736 = &_out_wimask_T_736; // @[RegisterRouter.scala:87:24] wire out_romask_736 = |_out_romask_T_736; // @[RegisterRouter.scala:87:24] wire out_womask_736 = &_out_womask_T_736; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_736 = out_rivalid_1_590 & out_rimask_736; // @[RegisterRouter.scala:87:24] wire _out_T_7301 = out_f_rivalid_736; // @[RegisterRouter.scala:87:24] wire out_f_roready_736 = out_roready_1_590 & out_romask_736; // @[RegisterRouter.scala:87:24] wire _out_T_7302 = out_f_roready_736; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_736 = out_wivalid_1_590 & out_wimask_736; // @[RegisterRouter.scala:87:24] wire out_f_woready_736 = out_woready_1_590 & out_womask_736; // @[RegisterRouter.scala:87:24] wire _out_T_7303 = ~out_rimask_736; // @[RegisterRouter.scala:87:24] wire _out_T_7304 = ~out_wimask_736; // @[RegisterRouter.scala:87:24] wire _out_T_7305 = ~out_romask_736; // @[RegisterRouter.scala:87:24] wire _out_T_7306 = ~out_womask_736; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_625 = {hi_510, flags_0_go, _out_prepend_T_625}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7307 = out_prepend_625; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7308 = _out_T_7307; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_626 = _out_T_7308; // @[RegisterRouter.scala:87:24] wire out_rimask_737 = |_out_rimask_T_737; // @[RegisterRouter.scala:87:24] wire out_wimask_737 = &_out_wimask_T_737; // @[RegisterRouter.scala:87:24] wire out_romask_737 = |_out_romask_T_737; // @[RegisterRouter.scala:87:24] wire out_womask_737 = &_out_womask_T_737; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_737 = out_rivalid_1_591 & out_rimask_737; // @[RegisterRouter.scala:87:24] wire _out_T_7310 = out_f_rivalid_737; // @[RegisterRouter.scala:87:24] wire out_f_roready_737 = out_roready_1_591 & out_romask_737; // @[RegisterRouter.scala:87:24] wire _out_T_7311 = out_f_roready_737; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_737 = out_wivalid_1_591 & out_wimask_737; // @[RegisterRouter.scala:87:24] wire out_f_woready_737 = out_woready_1_591 & out_womask_737; // @[RegisterRouter.scala:87:24] wire _out_T_7312 = ~out_rimask_737; // @[RegisterRouter.scala:87:24] wire _out_T_7313 = ~out_wimask_737; // @[RegisterRouter.scala:87:24] wire _out_T_7314 = ~out_romask_737; // @[RegisterRouter.scala:87:24] wire _out_T_7315 = ~out_womask_737; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_626 = {hi_511, flags_0_go, _out_prepend_T_626}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7316 = out_prepend_626; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7317 = _out_T_7316; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_627 = _out_T_7317; // @[RegisterRouter.scala:87:24] wire out_rimask_738 = |_out_rimask_T_738; // @[RegisterRouter.scala:87:24] wire out_wimask_738 = &_out_wimask_T_738; // @[RegisterRouter.scala:87:24] wire out_romask_738 = |_out_romask_T_738; // @[RegisterRouter.scala:87:24] wire out_womask_738 = &_out_womask_T_738; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_738 = out_rivalid_1_592 & out_rimask_738; // @[RegisterRouter.scala:87:24] wire _out_T_7319 = out_f_rivalid_738; // @[RegisterRouter.scala:87:24] wire out_f_roready_738 = out_roready_1_592 & out_romask_738; // @[RegisterRouter.scala:87:24] wire _out_T_7320 = out_f_roready_738; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_738 = out_wivalid_1_592 & out_wimask_738; // @[RegisterRouter.scala:87:24] wire out_f_woready_738 = out_woready_1_592 & out_womask_738; // @[RegisterRouter.scala:87:24] wire _out_T_7321 = ~out_rimask_738; // @[RegisterRouter.scala:87:24] wire _out_T_7322 = ~out_wimask_738; // @[RegisterRouter.scala:87:24] wire _out_T_7323 = ~out_romask_738; // @[RegisterRouter.scala:87:24] wire _out_T_7324 = ~out_womask_738; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_627 = {hi_512, flags_0_go, _out_prepend_T_627}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7325 = out_prepend_627; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7326 = _out_T_7325; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_191 = _out_T_7326; // @[MuxLiteral.scala:49:48] wire out_rimask_739 = |_out_rimask_T_739; // @[RegisterRouter.scala:87:24] wire out_wimask_739 = &_out_wimask_T_739; // @[RegisterRouter.scala:87:24] wire out_romask_739 = |_out_romask_T_739; // @[RegisterRouter.scala:87:24] wire out_womask_739 = &_out_womask_T_739; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_739 = out_rivalid_1_593 & out_rimask_739; // @[RegisterRouter.scala:87:24] wire _out_T_7328 = out_f_rivalid_739; // @[RegisterRouter.scala:87:24] wire out_f_roready_739 = out_roready_1_593 & out_romask_739; // @[RegisterRouter.scala:87:24] wire _out_T_7329 = out_f_roready_739; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_739 = out_wivalid_1_593 & out_wimask_739; // @[RegisterRouter.scala:87:24] wire out_f_woready_739 = out_woready_1_593 & out_womask_739; // @[RegisterRouter.scala:87:24] wire _out_T_7330 = ~out_rimask_739; // @[RegisterRouter.scala:87:24] wire _out_T_7331 = ~out_wimask_739; // @[RegisterRouter.scala:87:24] wire _out_T_7332 = ~out_romask_739; // @[RegisterRouter.scala:87:24] wire _out_T_7333 = ~out_womask_739; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7335 = _out_T_7334; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_628 = _out_T_7335; // @[RegisterRouter.scala:87:24] wire out_rimask_740 = |_out_rimask_T_740; // @[RegisterRouter.scala:87:24] wire out_wimask_740 = &_out_wimask_T_740; // @[RegisterRouter.scala:87:24] wire out_romask_740 = |_out_romask_T_740; // @[RegisterRouter.scala:87:24] wire out_womask_740 = &_out_womask_T_740; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_740 = out_rivalid_1_594 & out_rimask_740; // @[RegisterRouter.scala:87:24] wire _out_T_7337 = out_f_rivalid_740; // @[RegisterRouter.scala:87:24] wire out_f_roready_740 = out_roready_1_594 & out_romask_740; // @[RegisterRouter.scala:87:24] wire _out_T_7338 = out_f_roready_740; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_740 = out_wivalid_1_594 & out_wimask_740; // @[RegisterRouter.scala:87:24] wire out_f_woready_740 = out_woready_1_594 & out_womask_740; // @[RegisterRouter.scala:87:24] wire _out_T_7339 = ~out_rimask_740; // @[RegisterRouter.scala:87:24] wire _out_T_7340 = ~out_wimask_740; // @[RegisterRouter.scala:87:24] wire _out_T_7341 = ~out_romask_740; // @[RegisterRouter.scala:87:24] wire _out_T_7342 = ~out_womask_740; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_628 = {hi_610, flags_0_go, _out_prepend_T_628}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7343 = out_prepend_628; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7344 = _out_T_7343; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_629 = _out_T_7344; // @[RegisterRouter.scala:87:24] wire out_rimask_741 = |_out_rimask_T_741; // @[RegisterRouter.scala:87:24] wire out_wimask_741 = &_out_wimask_T_741; // @[RegisterRouter.scala:87:24] wire out_romask_741 = |_out_romask_T_741; // @[RegisterRouter.scala:87:24] wire out_womask_741 = &_out_womask_T_741; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_741 = out_rivalid_1_595 & out_rimask_741; // @[RegisterRouter.scala:87:24] wire _out_T_7346 = out_f_rivalid_741; // @[RegisterRouter.scala:87:24] wire out_f_roready_741 = out_roready_1_595 & out_romask_741; // @[RegisterRouter.scala:87:24] wire _out_T_7347 = out_f_roready_741; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_741 = out_wivalid_1_595 & out_wimask_741; // @[RegisterRouter.scala:87:24] wire out_f_woready_741 = out_woready_1_595 & out_womask_741; // @[RegisterRouter.scala:87:24] wire _out_T_7348 = ~out_rimask_741; // @[RegisterRouter.scala:87:24] wire _out_T_7349 = ~out_wimask_741; // @[RegisterRouter.scala:87:24] wire _out_T_7350 = ~out_romask_741; // @[RegisterRouter.scala:87:24] wire _out_T_7351 = ~out_womask_741; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_629 = {hi_611, flags_0_go, _out_prepend_T_629}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7352 = out_prepend_629; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7353 = _out_T_7352; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_630 = _out_T_7353; // @[RegisterRouter.scala:87:24] wire out_rimask_742 = |_out_rimask_T_742; // @[RegisterRouter.scala:87:24] wire out_wimask_742 = &_out_wimask_T_742; // @[RegisterRouter.scala:87:24] wire out_romask_742 = |_out_romask_T_742; // @[RegisterRouter.scala:87:24] wire out_womask_742 = &_out_womask_T_742; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_742 = out_rivalid_1_596 & out_rimask_742; // @[RegisterRouter.scala:87:24] wire _out_T_7355 = out_f_rivalid_742; // @[RegisterRouter.scala:87:24] wire out_f_roready_742 = out_roready_1_596 & out_romask_742; // @[RegisterRouter.scala:87:24] wire _out_T_7356 = out_f_roready_742; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_742 = out_wivalid_1_596 & out_wimask_742; // @[RegisterRouter.scala:87:24] wire out_f_woready_742 = out_woready_1_596 & out_womask_742; // @[RegisterRouter.scala:87:24] wire _out_T_7357 = ~out_rimask_742; // @[RegisterRouter.scala:87:24] wire _out_T_7358 = ~out_wimask_742; // @[RegisterRouter.scala:87:24] wire _out_T_7359 = ~out_romask_742; // @[RegisterRouter.scala:87:24] wire _out_T_7360 = ~out_womask_742; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_630 = {hi_612, flags_0_go, _out_prepend_T_630}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7361 = out_prepend_630; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7362 = _out_T_7361; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_631 = _out_T_7362; // @[RegisterRouter.scala:87:24] wire out_rimask_743 = |_out_rimask_T_743; // @[RegisterRouter.scala:87:24] wire out_wimask_743 = &_out_wimask_T_743; // @[RegisterRouter.scala:87:24] wire out_romask_743 = |_out_romask_T_743; // @[RegisterRouter.scala:87:24] wire out_womask_743 = &_out_womask_T_743; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_743 = out_rivalid_1_597 & out_rimask_743; // @[RegisterRouter.scala:87:24] wire _out_T_7364 = out_f_rivalid_743; // @[RegisterRouter.scala:87:24] wire out_f_roready_743 = out_roready_1_597 & out_romask_743; // @[RegisterRouter.scala:87:24] wire _out_T_7365 = out_f_roready_743; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_743 = out_wivalid_1_597 & out_wimask_743; // @[RegisterRouter.scala:87:24] wire out_f_woready_743 = out_woready_1_597 & out_womask_743; // @[RegisterRouter.scala:87:24] wire _out_T_7366 = ~out_rimask_743; // @[RegisterRouter.scala:87:24] wire _out_T_7367 = ~out_wimask_743; // @[RegisterRouter.scala:87:24] wire _out_T_7368 = ~out_romask_743; // @[RegisterRouter.scala:87:24] wire _out_T_7369 = ~out_womask_743; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_631 = {hi_613, flags_0_go, _out_prepend_T_631}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7370 = out_prepend_631; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7371 = _out_T_7370; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_632 = _out_T_7371; // @[RegisterRouter.scala:87:24] wire out_rimask_744 = |_out_rimask_T_744; // @[RegisterRouter.scala:87:24] wire out_wimask_744 = &_out_wimask_T_744; // @[RegisterRouter.scala:87:24] wire out_romask_744 = |_out_romask_T_744; // @[RegisterRouter.scala:87:24] wire out_womask_744 = &_out_womask_T_744; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_744 = out_rivalid_1_598 & out_rimask_744; // @[RegisterRouter.scala:87:24] wire _out_T_7373 = out_f_rivalid_744; // @[RegisterRouter.scala:87:24] wire out_f_roready_744 = out_roready_1_598 & out_romask_744; // @[RegisterRouter.scala:87:24] wire _out_T_7374 = out_f_roready_744; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_744 = out_wivalid_1_598 & out_wimask_744; // @[RegisterRouter.scala:87:24] wire out_f_woready_744 = out_woready_1_598 & out_womask_744; // @[RegisterRouter.scala:87:24] wire _out_T_7375 = ~out_rimask_744; // @[RegisterRouter.scala:87:24] wire _out_T_7376 = ~out_wimask_744; // @[RegisterRouter.scala:87:24] wire _out_T_7377 = ~out_romask_744; // @[RegisterRouter.scala:87:24] wire _out_T_7378 = ~out_womask_744; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_632 = {hi_614, flags_0_go, _out_prepend_T_632}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7379 = out_prepend_632; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7380 = _out_T_7379; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_633 = _out_T_7380; // @[RegisterRouter.scala:87:24] wire out_rimask_745 = |_out_rimask_T_745; // @[RegisterRouter.scala:87:24] wire out_wimask_745 = &_out_wimask_T_745; // @[RegisterRouter.scala:87:24] wire out_romask_745 = |_out_romask_T_745; // @[RegisterRouter.scala:87:24] wire out_womask_745 = &_out_womask_T_745; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_745 = out_rivalid_1_599 & out_rimask_745; // @[RegisterRouter.scala:87:24] wire _out_T_7382 = out_f_rivalid_745; // @[RegisterRouter.scala:87:24] wire out_f_roready_745 = out_roready_1_599 & out_romask_745; // @[RegisterRouter.scala:87:24] wire _out_T_7383 = out_f_roready_745; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_745 = out_wivalid_1_599 & out_wimask_745; // @[RegisterRouter.scala:87:24] wire out_f_woready_745 = out_woready_1_599 & out_womask_745; // @[RegisterRouter.scala:87:24] wire _out_T_7384 = ~out_rimask_745; // @[RegisterRouter.scala:87:24] wire _out_T_7385 = ~out_wimask_745; // @[RegisterRouter.scala:87:24] wire _out_T_7386 = ~out_romask_745; // @[RegisterRouter.scala:87:24] wire _out_T_7387 = ~out_womask_745; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_633 = {hi_615, flags_0_go, _out_prepend_T_633}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7388 = out_prepend_633; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7389 = _out_T_7388; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_634 = _out_T_7389; // @[RegisterRouter.scala:87:24] wire out_rimask_746 = |_out_rimask_T_746; // @[RegisterRouter.scala:87:24] wire out_wimask_746 = &_out_wimask_T_746; // @[RegisterRouter.scala:87:24] wire out_romask_746 = |_out_romask_T_746; // @[RegisterRouter.scala:87:24] wire out_womask_746 = &_out_womask_T_746; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_746 = out_rivalid_1_600 & out_rimask_746; // @[RegisterRouter.scala:87:24] wire _out_T_7391 = out_f_rivalid_746; // @[RegisterRouter.scala:87:24] wire out_f_roready_746 = out_roready_1_600 & out_romask_746; // @[RegisterRouter.scala:87:24] wire _out_T_7392 = out_f_roready_746; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_746 = out_wivalid_1_600 & out_wimask_746; // @[RegisterRouter.scala:87:24] wire out_f_woready_746 = out_woready_1_600 & out_womask_746; // @[RegisterRouter.scala:87:24] wire _out_T_7393 = ~out_rimask_746; // @[RegisterRouter.scala:87:24] wire _out_T_7394 = ~out_wimask_746; // @[RegisterRouter.scala:87:24] wire _out_T_7395 = ~out_romask_746; // @[RegisterRouter.scala:87:24] wire _out_T_7396 = ~out_womask_746; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_634 = {hi_616, flags_0_go, _out_prepend_T_634}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7397 = out_prepend_634; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7398 = _out_T_7397; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_204 = _out_T_7398; // @[MuxLiteral.scala:49:48] wire out_rimask_747 = |_out_rimask_T_747; // @[RegisterRouter.scala:87:24] wire out_wimask_747 = &_out_wimask_T_747; // @[RegisterRouter.scala:87:24] wire out_romask_747 = |_out_romask_T_747; // @[RegisterRouter.scala:87:24] wire out_womask_747 = &_out_womask_T_747; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_747 = out_rivalid_1_601 & out_rimask_747; // @[RegisterRouter.scala:87:24] wire _out_T_7400 = out_f_rivalid_747; // @[RegisterRouter.scala:87:24] wire out_f_roready_747 = out_roready_1_601 & out_romask_747; // @[RegisterRouter.scala:87:24] wire _out_T_7401 = out_f_roready_747; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_747 = out_wivalid_1_601 & out_wimask_747; // @[RegisterRouter.scala:87:24] wire out_f_woready_747 = out_woready_1_601 & out_womask_747; // @[RegisterRouter.scala:87:24] wire _out_T_7402 = ~out_rimask_747; // @[RegisterRouter.scala:87:24] wire _out_T_7403 = ~out_wimask_747; // @[RegisterRouter.scala:87:24] wire _out_T_7404 = ~out_romask_747; // @[RegisterRouter.scala:87:24] wire _out_T_7405 = ~out_womask_747; // @[RegisterRouter.scala:87:24] wire out_rimask_748 = |_out_rimask_T_748; // @[RegisterRouter.scala:87:24] wire out_wimask_748 = &_out_wimask_T_748; // @[RegisterRouter.scala:87:24] wire out_romask_748 = |_out_romask_T_748; // @[RegisterRouter.scala:87:24] wire out_womask_748 = &_out_womask_T_748; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_748 = out_rivalid_1_602 & out_rimask_748; // @[RegisterRouter.scala:87:24] wire _out_T_7409 = out_f_rivalid_748; // @[RegisterRouter.scala:87:24] wire out_f_roready_748 = out_roready_1_602 & out_romask_748; // @[RegisterRouter.scala:87:24] wire _out_T_7410 = out_f_roready_748; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_748 = out_wivalid_1_602 & out_wimask_748; // @[RegisterRouter.scala:87:24] wire out_f_woready_748 = out_woready_1_602 & out_womask_748; // @[RegisterRouter.scala:87:24] wire _out_T_7411 = ~out_rimask_748; // @[RegisterRouter.scala:87:24] wire _out_T_7412 = ~out_wimask_748; // @[RegisterRouter.scala:87:24] wire _out_T_7413 = ~out_romask_748; // @[RegisterRouter.scala:87:24] wire _out_T_7414 = ~out_womask_748; // @[RegisterRouter.scala:87:24] wire out_rimask_749 = |_out_rimask_T_749; // @[RegisterRouter.scala:87:24] wire out_wimask_749 = &_out_wimask_T_749; // @[RegisterRouter.scala:87:24] wire out_romask_749 = |_out_romask_T_749; // @[RegisterRouter.scala:87:24] wire out_womask_749 = &_out_womask_T_749; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_749 = out_rivalid_1_603 & out_rimask_749; // @[RegisterRouter.scala:87:24] wire _out_T_7418 = out_f_rivalid_749; // @[RegisterRouter.scala:87:24] wire out_f_roready_749 = out_roready_1_603 & out_romask_749; // @[RegisterRouter.scala:87:24] wire _out_T_7419 = out_f_roready_749; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_749 = out_wivalid_1_603 & out_wimask_749; // @[RegisterRouter.scala:87:24] wire out_f_woready_749 = out_woready_1_603 & out_womask_749; // @[RegisterRouter.scala:87:24] wire _out_T_7420 = ~out_rimask_749; // @[RegisterRouter.scala:87:24] wire _out_T_7421 = ~out_wimask_749; // @[RegisterRouter.scala:87:24] wire _out_T_7422 = ~out_romask_749; // @[RegisterRouter.scala:87:24] wire _out_T_7423 = ~out_womask_749; // @[RegisterRouter.scala:87:24] wire out_rimask_750 = |_out_rimask_T_750; // @[RegisterRouter.scala:87:24] wire out_wimask_750 = &_out_wimask_T_750; // @[RegisterRouter.scala:87:24] wire out_romask_750 = |_out_romask_T_750; // @[RegisterRouter.scala:87:24] wire out_womask_750 = &_out_womask_T_750; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_750 = out_rivalid_1_604 & out_rimask_750; // @[RegisterRouter.scala:87:24] wire _out_T_7427 = out_f_rivalid_750; // @[RegisterRouter.scala:87:24] wire out_f_roready_750 = out_roready_1_604 & out_romask_750; // @[RegisterRouter.scala:87:24] wire _out_T_7428 = out_f_roready_750; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_750 = out_wivalid_1_604 & out_wimask_750; // @[RegisterRouter.scala:87:24] wire out_f_woready_750 = out_woready_1_604 & out_womask_750; // @[RegisterRouter.scala:87:24] wire _out_T_7429 = ~out_rimask_750; // @[RegisterRouter.scala:87:24] wire _out_T_7430 = ~out_wimask_750; // @[RegisterRouter.scala:87:24] wire _out_T_7431 = ~out_romask_750; // @[RegisterRouter.scala:87:24] wire _out_T_7432 = ~out_womask_750; // @[RegisterRouter.scala:87:24] wire out_rimask_751 = |_out_rimask_T_751; // @[RegisterRouter.scala:87:24] wire out_wimask_751 = &_out_wimask_T_751; // @[RegisterRouter.scala:87:24] wire out_romask_751 = |_out_romask_T_751; // @[RegisterRouter.scala:87:24] wire out_womask_751 = &_out_womask_T_751; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_751 = out_rivalid_1_605 & out_rimask_751; // @[RegisterRouter.scala:87:24] wire _out_T_7436 = out_f_rivalid_751; // @[RegisterRouter.scala:87:24] wire out_f_roready_751 = out_roready_1_605 & out_romask_751; // @[RegisterRouter.scala:87:24] wire _out_T_7437 = out_f_roready_751; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_751 = out_wivalid_1_605 & out_wimask_751; // @[RegisterRouter.scala:87:24] wire out_f_woready_751 = out_woready_1_605 & out_womask_751; // @[RegisterRouter.scala:87:24] wire _out_T_7438 = ~out_rimask_751; // @[RegisterRouter.scala:87:24] wire _out_T_7439 = ~out_wimask_751; // @[RegisterRouter.scala:87:24] wire _out_T_7440 = ~out_romask_751; // @[RegisterRouter.scala:87:24] wire _out_T_7441 = ~out_womask_751; // @[RegisterRouter.scala:87:24] wire out_rimask_752 = |_out_rimask_T_752; // @[RegisterRouter.scala:87:24] wire out_wimask_752 = &_out_wimask_T_752; // @[RegisterRouter.scala:87:24] wire out_romask_752 = |_out_romask_T_752; // @[RegisterRouter.scala:87:24] wire out_womask_752 = &_out_womask_T_752; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_752 = out_rivalid_1_606 & out_rimask_752; // @[RegisterRouter.scala:87:24] wire _out_T_7445 = out_f_rivalid_752; // @[RegisterRouter.scala:87:24] wire out_f_roready_752 = out_roready_1_606 & out_romask_752; // @[RegisterRouter.scala:87:24] wire _out_T_7446 = out_f_roready_752; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_752 = out_wivalid_1_606 & out_wimask_752; // @[RegisterRouter.scala:87:24] wire out_f_woready_752 = out_woready_1_606 & out_womask_752; // @[RegisterRouter.scala:87:24] wire _out_T_7447 = ~out_rimask_752; // @[RegisterRouter.scala:87:24] wire _out_T_7448 = ~out_wimask_752; // @[RegisterRouter.scala:87:24] wire _out_T_7449 = ~out_romask_752; // @[RegisterRouter.scala:87:24] wire _out_T_7450 = ~out_womask_752; // @[RegisterRouter.scala:87:24] wire out_rimask_753 = |_out_rimask_T_753; // @[RegisterRouter.scala:87:24] wire out_wimask_753 = &_out_wimask_T_753; // @[RegisterRouter.scala:87:24] wire out_romask_753 = |_out_romask_T_753; // @[RegisterRouter.scala:87:24] wire out_womask_753 = &_out_womask_T_753; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_753 = out_rivalid_1_607 & out_rimask_753; // @[RegisterRouter.scala:87:24] wire _out_T_7454 = out_f_rivalid_753; // @[RegisterRouter.scala:87:24] wire out_f_roready_753 = out_roready_1_607 & out_romask_753; // @[RegisterRouter.scala:87:24] wire _out_T_7455 = out_f_roready_753; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_753 = out_wivalid_1_607 & out_wimask_753; // @[RegisterRouter.scala:87:24] wire out_f_woready_753 = out_woready_1_607 & out_womask_753; // @[RegisterRouter.scala:87:24] wire _out_T_7456 = ~out_rimask_753; // @[RegisterRouter.scala:87:24] wire _out_T_7457 = ~out_wimask_753; // @[RegisterRouter.scala:87:24] wire _out_T_7458 = ~out_romask_753; // @[RegisterRouter.scala:87:24] wire _out_T_7459 = ~out_womask_753; // @[RegisterRouter.scala:87:24] wire out_rimask_754 = |_out_rimask_T_754; // @[RegisterRouter.scala:87:24] wire out_wimask_754 = &_out_wimask_T_754; // @[RegisterRouter.scala:87:24] wire out_romask_754 = |_out_romask_T_754; // @[RegisterRouter.scala:87:24] wire out_womask_754 = &_out_womask_T_754; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_754 = out_rivalid_1_608 & out_rimask_754; // @[RegisterRouter.scala:87:24] wire _out_T_7463 = out_f_rivalid_754; // @[RegisterRouter.scala:87:24] wire out_f_roready_754 = out_roready_1_608 & out_romask_754; // @[RegisterRouter.scala:87:24] wire _out_T_7464 = out_f_roready_754; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_754 = out_wivalid_1_608 & out_wimask_754; // @[RegisterRouter.scala:87:24] wire out_f_woready_754 = out_woready_1_608 & out_womask_754; // @[RegisterRouter.scala:87:24] wire _out_T_7465 = ~out_rimask_754; // @[RegisterRouter.scala:87:24] wire _out_T_7466 = ~out_wimask_754; // @[RegisterRouter.scala:87:24] wire _out_T_7467 = ~out_romask_754; // @[RegisterRouter.scala:87:24] wire _out_T_7468 = ~out_womask_754; // @[RegisterRouter.scala:87:24] wire out_rimask_755 = |_out_rimask_T_755; // @[RegisterRouter.scala:87:24] wire out_wimask_755 = &_out_wimask_T_755; // @[RegisterRouter.scala:87:24] wire out_romask_755 = |_out_romask_T_755; // @[RegisterRouter.scala:87:24] wire out_womask_755 = &_out_womask_T_755; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_755 = out_rivalid_1_609 & out_rimask_755; // @[RegisterRouter.scala:87:24] wire _out_T_7472 = out_f_rivalid_755; // @[RegisterRouter.scala:87:24] wire out_f_roready_755 = out_roready_1_609 & out_romask_755; // @[RegisterRouter.scala:87:24] wire _out_T_7473 = out_f_roready_755; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_755 = out_wivalid_1_609 & out_wimask_755; // @[RegisterRouter.scala:87:24] wire out_f_woready_755 = out_woready_1_609 & out_womask_755; // @[RegisterRouter.scala:87:24] wire _out_T_7474 = ~out_rimask_755; // @[RegisterRouter.scala:87:24] wire _out_T_7475 = ~out_wimask_755; // @[RegisterRouter.scala:87:24] wire _out_T_7476 = ~out_romask_755; // @[RegisterRouter.scala:87:24] wire _out_T_7477 = ~out_womask_755; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7479 = _out_T_7478; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_642 = _out_T_7479; // @[RegisterRouter.scala:87:24] wire out_rimask_756 = |_out_rimask_T_756; // @[RegisterRouter.scala:87:24] wire out_wimask_756 = &_out_wimask_T_756; // @[RegisterRouter.scala:87:24] wire out_romask_756 = |_out_romask_T_756; // @[RegisterRouter.scala:87:24] wire out_womask_756 = &_out_womask_T_756; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_756 = out_rivalid_1_610 & out_rimask_756; // @[RegisterRouter.scala:87:24] wire _out_T_7481 = out_f_rivalid_756; // @[RegisterRouter.scala:87:24] wire out_f_roready_756 = out_roready_1_610 & out_romask_756; // @[RegisterRouter.scala:87:24] wire _out_T_7482 = out_f_roready_756; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_756 = out_wivalid_1_610 & out_wimask_756; // @[RegisterRouter.scala:87:24] wire out_f_woready_756 = out_woready_1_610 & out_womask_756; // @[RegisterRouter.scala:87:24] wire _out_T_7483 = ~out_rimask_756; // @[RegisterRouter.scala:87:24] wire _out_T_7484 = ~out_wimask_756; // @[RegisterRouter.scala:87:24] wire _out_T_7485 = ~out_romask_756; // @[RegisterRouter.scala:87:24] wire _out_T_7486 = ~out_womask_756; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_642 = {hi_130, flags_0_go, _out_prepend_T_642}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7487 = out_prepend_642; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7488 = _out_T_7487; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_643 = _out_T_7488; // @[RegisterRouter.scala:87:24] wire out_rimask_757 = |_out_rimask_T_757; // @[RegisterRouter.scala:87:24] wire out_wimask_757 = &_out_wimask_T_757; // @[RegisterRouter.scala:87:24] wire out_romask_757 = |_out_romask_T_757; // @[RegisterRouter.scala:87:24] wire out_womask_757 = &_out_womask_T_757; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_757 = out_rivalid_1_611 & out_rimask_757; // @[RegisterRouter.scala:87:24] wire _out_T_7490 = out_f_rivalid_757; // @[RegisterRouter.scala:87:24] wire out_f_roready_757 = out_roready_1_611 & out_romask_757; // @[RegisterRouter.scala:87:24] wire _out_T_7491 = out_f_roready_757; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_757 = out_wivalid_1_611 & out_wimask_757; // @[RegisterRouter.scala:87:24] wire out_f_woready_757 = out_woready_1_611 & out_womask_757; // @[RegisterRouter.scala:87:24] wire _out_T_7492 = ~out_rimask_757; // @[RegisterRouter.scala:87:24] wire _out_T_7493 = ~out_wimask_757; // @[RegisterRouter.scala:87:24] wire _out_T_7494 = ~out_romask_757; // @[RegisterRouter.scala:87:24] wire _out_T_7495 = ~out_womask_757; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_643 = {hi_131, flags_0_go, _out_prepend_T_643}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7496 = out_prepend_643; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7497 = _out_T_7496; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_644 = _out_T_7497; // @[RegisterRouter.scala:87:24] wire out_rimask_758 = |_out_rimask_T_758; // @[RegisterRouter.scala:87:24] wire out_wimask_758 = &_out_wimask_T_758; // @[RegisterRouter.scala:87:24] wire out_romask_758 = |_out_romask_T_758; // @[RegisterRouter.scala:87:24] wire out_womask_758 = &_out_womask_T_758; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_758 = out_rivalid_1_612 & out_rimask_758; // @[RegisterRouter.scala:87:24] wire _out_T_7499 = out_f_rivalid_758; // @[RegisterRouter.scala:87:24] wire out_f_roready_758 = out_roready_1_612 & out_romask_758; // @[RegisterRouter.scala:87:24] wire _out_T_7500 = out_f_roready_758; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_758 = out_wivalid_1_612 & out_wimask_758; // @[RegisterRouter.scala:87:24] wire out_f_woready_758 = out_woready_1_612 & out_womask_758; // @[RegisterRouter.scala:87:24] wire _out_T_7501 = ~out_rimask_758; // @[RegisterRouter.scala:87:24] wire _out_T_7502 = ~out_wimask_758; // @[RegisterRouter.scala:87:24] wire _out_T_7503 = ~out_romask_758; // @[RegisterRouter.scala:87:24] wire _out_T_7504 = ~out_womask_758; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_644 = {hi_132, flags_0_go, _out_prepend_T_644}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7505 = out_prepend_644; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7506 = _out_T_7505; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_645 = _out_T_7506; // @[RegisterRouter.scala:87:24] wire out_rimask_759 = |_out_rimask_T_759; // @[RegisterRouter.scala:87:24] wire out_wimask_759 = &_out_wimask_T_759; // @[RegisterRouter.scala:87:24] wire out_romask_759 = |_out_romask_T_759; // @[RegisterRouter.scala:87:24] wire out_womask_759 = &_out_womask_T_759; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_759 = out_rivalid_1_613 & out_rimask_759; // @[RegisterRouter.scala:87:24] wire _out_T_7508 = out_f_rivalid_759; // @[RegisterRouter.scala:87:24] wire out_f_roready_759 = out_roready_1_613 & out_romask_759; // @[RegisterRouter.scala:87:24] wire _out_T_7509 = out_f_roready_759; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_759 = out_wivalid_1_613 & out_wimask_759; // @[RegisterRouter.scala:87:24] wire out_f_woready_759 = out_woready_1_613 & out_womask_759; // @[RegisterRouter.scala:87:24] wire _out_T_7510 = ~out_rimask_759; // @[RegisterRouter.scala:87:24] wire _out_T_7511 = ~out_wimask_759; // @[RegisterRouter.scala:87:24] wire _out_T_7512 = ~out_romask_759; // @[RegisterRouter.scala:87:24] wire _out_T_7513 = ~out_womask_759; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_645 = {hi_133, flags_0_go, _out_prepend_T_645}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7514 = out_prepend_645; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7515 = _out_T_7514; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_646 = _out_T_7515; // @[RegisterRouter.scala:87:24] wire out_rimask_760 = |_out_rimask_T_760; // @[RegisterRouter.scala:87:24] wire out_wimask_760 = &_out_wimask_T_760; // @[RegisterRouter.scala:87:24] wire out_romask_760 = |_out_romask_T_760; // @[RegisterRouter.scala:87:24] wire out_womask_760 = &_out_womask_T_760; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_760 = out_rivalid_1_614 & out_rimask_760; // @[RegisterRouter.scala:87:24] wire _out_T_7517 = out_f_rivalid_760; // @[RegisterRouter.scala:87:24] wire out_f_roready_760 = out_roready_1_614 & out_romask_760; // @[RegisterRouter.scala:87:24] wire _out_T_7518 = out_f_roready_760; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_760 = out_wivalid_1_614 & out_wimask_760; // @[RegisterRouter.scala:87:24] wire out_f_woready_760 = out_woready_1_614 & out_womask_760; // @[RegisterRouter.scala:87:24] wire _out_T_7519 = ~out_rimask_760; // @[RegisterRouter.scala:87:24] wire _out_T_7520 = ~out_wimask_760; // @[RegisterRouter.scala:87:24] wire _out_T_7521 = ~out_romask_760; // @[RegisterRouter.scala:87:24] wire _out_T_7522 = ~out_womask_760; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_646 = {hi_134, flags_0_go, _out_prepend_T_646}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7523 = out_prepend_646; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7524 = _out_T_7523; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_647 = _out_T_7524; // @[RegisterRouter.scala:87:24] wire out_rimask_761 = |_out_rimask_T_761; // @[RegisterRouter.scala:87:24] wire out_wimask_761 = &_out_wimask_T_761; // @[RegisterRouter.scala:87:24] wire out_romask_761 = |_out_romask_T_761; // @[RegisterRouter.scala:87:24] wire out_womask_761 = &_out_womask_T_761; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_761 = out_rivalid_1_615 & out_rimask_761; // @[RegisterRouter.scala:87:24] wire _out_T_7526 = out_f_rivalid_761; // @[RegisterRouter.scala:87:24] wire out_f_roready_761 = out_roready_1_615 & out_romask_761; // @[RegisterRouter.scala:87:24] wire _out_T_7527 = out_f_roready_761; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_761 = out_wivalid_1_615 & out_wimask_761; // @[RegisterRouter.scala:87:24] wire out_f_woready_761 = out_woready_1_615 & out_womask_761; // @[RegisterRouter.scala:87:24] wire _out_T_7528 = ~out_rimask_761; // @[RegisterRouter.scala:87:24] wire _out_T_7529 = ~out_wimask_761; // @[RegisterRouter.scala:87:24] wire _out_T_7530 = ~out_romask_761; // @[RegisterRouter.scala:87:24] wire _out_T_7531 = ~out_womask_761; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_647 = {hi_135, flags_0_go, _out_prepend_T_647}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7532 = out_prepend_647; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7533 = _out_T_7532; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_648 = _out_T_7533; // @[RegisterRouter.scala:87:24] wire out_rimask_762 = |_out_rimask_T_762; // @[RegisterRouter.scala:87:24] wire out_wimask_762 = &_out_wimask_T_762; // @[RegisterRouter.scala:87:24] wire out_romask_762 = |_out_romask_T_762; // @[RegisterRouter.scala:87:24] wire out_womask_762 = &_out_womask_T_762; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_762 = out_rivalid_1_616 & out_rimask_762; // @[RegisterRouter.scala:87:24] wire _out_T_7535 = out_f_rivalid_762; // @[RegisterRouter.scala:87:24] wire out_f_roready_762 = out_roready_1_616 & out_romask_762; // @[RegisterRouter.scala:87:24] wire _out_T_7536 = out_f_roready_762; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_762 = out_wivalid_1_616 & out_wimask_762; // @[RegisterRouter.scala:87:24] wire out_f_woready_762 = out_woready_1_616 & out_womask_762; // @[RegisterRouter.scala:87:24] wire _out_T_7537 = ~out_rimask_762; // @[RegisterRouter.scala:87:24] wire _out_T_7538 = ~out_wimask_762; // @[RegisterRouter.scala:87:24] wire _out_T_7539 = ~out_romask_762; // @[RegisterRouter.scala:87:24] wire _out_T_7540 = ~out_womask_762; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_648 = {hi_136, flags_0_go, _out_prepend_T_648}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7541 = out_prepend_648; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7542 = _out_T_7541; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_144 = _out_T_7542; // @[MuxLiteral.scala:49:48] wire out_rimask_763 = |_out_rimask_T_763; // @[RegisterRouter.scala:87:24] wire out_wimask_763 = &_out_wimask_T_763; // @[RegisterRouter.scala:87:24] wire out_romask_763 = |_out_romask_T_763; // @[RegisterRouter.scala:87:24] wire out_womask_763 = &_out_womask_T_763; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_763 = out_rivalid_1_617 & out_rimask_763; // @[RegisterRouter.scala:87:24] wire _out_T_7544 = out_f_rivalid_763; // @[RegisterRouter.scala:87:24] wire out_f_roready_763 = out_roready_1_617 & out_romask_763; // @[RegisterRouter.scala:87:24] wire _out_T_7545 = out_f_roready_763; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_763 = out_wivalid_1_617 & out_wimask_763; // @[RegisterRouter.scala:87:24] wire out_f_woready_763 = out_woready_1_617 & out_womask_763; // @[RegisterRouter.scala:87:24] wire _out_T_7546 = ~out_rimask_763; // @[RegisterRouter.scala:87:24] wire _out_T_7547 = ~out_wimask_763; // @[RegisterRouter.scala:87:24] wire _out_T_7548 = ~out_romask_763; // @[RegisterRouter.scala:87:24] wire _out_T_7549 = ~out_womask_763; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7551 = _out_T_7550; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_649 = _out_T_7551; // @[RegisterRouter.scala:87:24] wire out_rimask_764 = |_out_rimask_T_764; // @[RegisterRouter.scala:87:24] wire out_wimask_764 = &_out_wimask_T_764; // @[RegisterRouter.scala:87:24] wire out_romask_764 = |_out_romask_T_764; // @[RegisterRouter.scala:87:24] wire out_womask_764 = &_out_womask_T_764; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_764 = out_rivalid_1_618 & out_rimask_764; // @[RegisterRouter.scala:87:24] wire _out_T_7553 = out_f_rivalid_764; // @[RegisterRouter.scala:87:24] wire out_f_roready_764 = out_roready_1_618 & out_romask_764; // @[RegisterRouter.scala:87:24] wire _out_T_7554 = out_f_roready_764; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_764 = out_wivalid_1_618 & out_wimask_764; // @[RegisterRouter.scala:87:24] wire out_f_woready_764 = out_woready_1_618 & out_womask_764; // @[RegisterRouter.scala:87:24] wire _out_T_7555 = ~out_rimask_764; // @[RegisterRouter.scala:87:24] wire _out_T_7556 = ~out_wimask_764; // @[RegisterRouter.scala:87:24] wire _out_T_7557 = ~out_romask_764; // @[RegisterRouter.scala:87:24] wire _out_T_7558 = ~out_womask_764; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_649 = {hi_866, flags_0_go, _out_prepend_T_649}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7559 = out_prepend_649; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7560 = _out_T_7559; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_650 = _out_T_7560; // @[RegisterRouter.scala:87:24] wire out_rimask_765 = |_out_rimask_T_765; // @[RegisterRouter.scala:87:24] wire out_wimask_765 = &_out_wimask_T_765; // @[RegisterRouter.scala:87:24] wire out_romask_765 = |_out_romask_T_765; // @[RegisterRouter.scala:87:24] wire out_womask_765 = &_out_womask_T_765; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_765 = out_rivalid_1_619 & out_rimask_765; // @[RegisterRouter.scala:87:24] wire _out_T_7562 = out_f_rivalid_765; // @[RegisterRouter.scala:87:24] wire out_f_roready_765 = out_roready_1_619 & out_romask_765; // @[RegisterRouter.scala:87:24] wire _out_T_7563 = out_f_roready_765; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_765 = out_wivalid_1_619 & out_wimask_765; // @[RegisterRouter.scala:87:24] wire out_f_woready_765 = out_woready_1_619 & out_womask_765; // @[RegisterRouter.scala:87:24] wire _out_T_7564 = ~out_rimask_765; // @[RegisterRouter.scala:87:24] wire _out_T_7565 = ~out_wimask_765; // @[RegisterRouter.scala:87:24] wire _out_T_7566 = ~out_romask_765; // @[RegisterRouter.scala:87:24] wire _out_T_7567 = ~out_womask_765; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_650 = {hi_867, flags_0_go, _out_prepend_T_650}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7568 = out_prepend_650; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7569 = _out_T_7568; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_651 = _out_T_7569; // @[RegisterRouter.scala:87:24] wire out_rimask_766 = |_out_rimask_T_766; // @[RegisterRouter.scala:87:24] wire out_wimask_766 = &_out_wimask_T_766; // @[RegisterRouter.scala:87:24] wire out_romask_766 = |_out_romask_T_766; // @[RegisterRouter.scala:87:24] wire out_womask_766 = &_out_womask_T_766; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_766 = out_rivalid_1_620 & out_rimask_766; // @[RegisterRouter.scala:87:24] wire _out_T_7571 = out_f_rivalid_766; // @[RegisterRouter.scala:87:24] wire out_f_roready_766 = out_roready_1_620 & out_romask_766; // @[RegisterRouter.scala:87:24] wire _out_T_7572 = out_f_roready_766; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_766 = out_wivalid_1_620 & out_wimask_766; // @[RegisterRouter.scala:87:24] wire out_f_woready_766 = out_woready_1_620 & out_womask_766; // @[RegisterRouter.scala:87:24] wire _out_T_7573 = ~out_rimask_766; // @[RegisterRouter.scala:87:24] wire _out_T_7574 = ~out_wimask_766; // @[RegisterRouter.scala:87:24] wire _out_T_7575 = ~out_romask_766; // @[RegisterRouter.scala:87:24] wire _out_T_7576 = ~out_womask_766; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_651 = {hi_868, flags_0_go, _out_prepend_T_651}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7577 = out_prepend_651; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7578 = _out_T_7577; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_652 = _out_T_7578; // @[RegisterRouter.scala:87:24] wire out_rimask_767 = |_out_rimask_T_767; // @[RegisterRouter.scala:87:24] wire out_wimask_767 = &_out_wimask_T_767; // @[RegisterRouter.scala:87:24] wire out_romask_767 = |_out_romask_T_767; // @[RegisterRouter.scala:87:24] wire out_womask_767 = &_out_womask_T_767; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_767 = out_rivalid_1_621 & out_rimask_767; // @[RegisterRouter.scala:87:24] wire _out_T_7580 = out_f_rivalid_767; // @[RegisterRouter.scala:87:24] wire out_f_roready_767 = out_roready_1_621 & out_romask_767; // @[RegisterRouter.scala:87:24] wire _out_T_7581 = out_f_roready_767; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_767 = out_wivalid_1_621 & out_wimask_767; // @[RegisterRouter.scala:87:24] wire out_f_woready_767 = out_woready_1_621 & out_womask_767; // @[RegisterRouter.scala:87:24] wire _out_T_7582 = ~out_rimask_767; // @[RegisterRouter.scala:87:24] wire _out_T_7583 = ~out_wimask_767; // @[RegisterRouter.scala:87:24] wire _out_T_7584 = ~out_romask_767; // @[RegisterRouter.scala:87:24] wire _out_T_7585 = ~out_womask_767; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_652 = {hi_869, flags_0_go, _out_prepend_T_652}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7586 = out_prepend_652; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7587 = _out_T_7586; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_653 = _out_T_7587; // @[RegisterRouter.scala:87:24] wire out_rimask_768 = |_out_rimask_T_768; // @[RegisterRouter.scala:87:24] wire out_wimask_768 = &_out_wimask_T_768; // @[RegisterRouter.scala:87:24] wire out_romask_768 = |_out_romask_T_768; // @[RegisterRouter.scala:87:24] wire out_womask_768 = &_out_womask_T_768; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_768 = out_rivalid_1_622 & out_rimask_768; // @[RegisterRouter.scala:87:24] wire _out_T_7589 = out_f_rivalid_768; // @[RegisterRouter.scala:87:24] wire out_f_roready_768 = out_roready_1_622 & out_romask_768; // @[RegisterRouter.scala:87:24] wire _out_T_7590 = out_f_roready_768; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_768 = out_wivalid_1_622 & out_wimask_768; // @[RegisterRouter.scala:87:24] wire out_f_woready_768 = out_woready_1_622 & out_womask_768; // @[RegisterRouter.scala:87:24] wire _out_T_7591 = ~out_rimask_768; // @[RegisterRouter.scala:87:24] wire _out_T_7592 = ~out_wimask_768; // @[RegisterRouter.scala:87:24] wire _out_T_7593 = ~out_romask_768; // @[RegisterRouter.scala:87:24] wire _out_T_7594 = ~out_womask_768; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_653 = {hi_870, flags_0_go, _out_prepend_T_653}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7595 = out_prepend_653; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7596 = _out_T_7595; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_654 = _out_T_7596; // @[RegisterRouter.scala:87:24] wire out_rimask_769 = |_out_rimask_T_769; // @[RegisterRouter.scala:87:24] wire out_wimask_769 = &_out_wimask_T_769; // @[RegisterRouter.scala:87:24] wire out_romask_769 = |_out_romask_T_769; // @[RegisterRouter.scala:87:24] wire out_womask_769 = &_out_womask_T_769; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_769 = out_rivalid_1_623 & out_rimask_769; // @[RegisterRouter.scala:87:24] wire _out_T_7598 = out_f_rivalid_769; // @[RegisterRouter.scala:87:24] wire out_f_roready_769 = out_roready_1_623 & out_romask_769; // @[RegisterRouter.scala:87:24] wire _out_T_7599 = out_f_roready_769; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_769 = out_wivalid_1_623 & out_wimask_769; // @[RegisterRouter.scala:87:24] wire out_f_woready_769 = out_woready_1_623 & out_womask_769; // @[RegisterRouter.scala:87:24] wire _out_T_7600 = ~out_rimask_769; // @[RegisterRouter.scala:87:24] wire _out_T_7601 = ~out_wimask_769; // @[RegisterRouter.scala:87:24] wire _out_T_7602 = ~out_romask_769; // @[RegisterRouter.scala:87:24] wire _out_T_7603 = ~out_womask_769; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_654 = {hi_871, flags_0_go, _out_prepend_T_654}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7604 = out_prepend_654; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7605 = _out_T_7604; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_655 = _out_T_7605; // @[RegisterRouter.scala:87:24] wire out_rimask_770 = |_out_rimask_T_770; // @[RegisterRouter.scala:87:24] wire out_wimask_770 = &_out_wimask_T_770; // @[RegisterRouter.scala:87:24] wire out_romask_770 = |_out_romask_T_770; // @[RegisterRouter.scala:87:24] wire out_womask_770 = &_out_womask_T_770; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_770 = out_rivalid_1_624 & out_rimask_770; // @[RegisterRouter.scala:87:24] wire _out_T_7607 = out_f_rivalid_770; // @[RegisterRouter.scala:87:24] wire out_f_roready_770 = out_roready_1_624 & out_romask_770; // @[RegisterRouter.scala:87:24] wire _out_T_7608 = out_f_roready_770; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_770 = out_wivalid_1_624 & out_wimask_770; // @[RegisterRouter.scala:87:24] wire out_f_woready_770 = out_woready_1_624 & out_womask_770; // @[RegisterRouter.scala:87:24] wire _out_T_7609 = ~out_rimask_770; // @[RegisterRouter.scala:87:24] wire _out_T_7610 = ~out_wimask_770; // @[RegisterRouter.scala:87:24] wire _out_T_7611 = ~out_romask_770; // @[RegisterRouter.scala:87:24] wire _out_T_7612 = ~out_womask_770; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_655 = {hi_872, flags_0_go, _out_prepend_T_655}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7613 = out_prepend_655; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7614 = _out_T_7613; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_236 = _out_T_7614; // @[MuxLiteral.scala:49:48] wire out_rimask_771 = |_out_rimask_T_771; // @[RegisterRouter.scala:87:24] wire out_wimask_771 = &_out_wimask_T_771; // @[RegisterRouter.scala:87:24] wire out_romask_771 = |_out_romask_T_771; // @[RegisterRouter.scala:87:24] wire out_womask_771 = &_out_womask_T_771; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_771 = out_rivalid_1_625 & out_rimask_771; // @[RegisterRouter.scala:87:24] wire _out_T_7616 = out_f_rivalid_771; // @[RegisterRouter.scala:87:24] wire out_f_roready_771 = out_roready_1_625 & out_romask_771; // @[RegisterRouter.scala:87:24] wire _out_T_7617 = out_f_roready_771; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_771 = out_wivalid_1_625 & out_wimask_771; // @[RegisterRouter.scala:87:24] wire out_f_woready_771 = out_woready_1_625 & out_womask_771; // @[RegisterRouter.scala:87:24] wire _out_T_7618 = ~out_rimask_771; // @[RegisterRouter.scala:87:24] wire _out_T_7619 = ~out_wimask_771; // @[RegisterRouter.scala:87:24] wire _out_T_7620 = ~out_romask_771; // @[RegisterRouter.scala:87:24] wire _out_T_7621 = ~out_womask_771; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7623 = _out_T_7622; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_656 = _out_T_7623; // @[RegisterRouter.scala:87:24] wire out_rimask_772 = |_out_rimask_T_772; // @[RegisterRouter.scala:87:24] wire out_wimask_772 = &_out_wimask_T_772; // @[RegisterRouter.scala:87:24] wire out_romask_772 = |_out_romask_T_772; // @[RegisterRouter.scala:87:24] wire out_womask_772 = &_out_womask_T_772; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_772 = out_rivalid_1_626 & out_rimask_772; // @[RegisterRouter.scala:87:24] wire _out_T_7625 = out_f_rivalid_772; // @[RegisterRouter.scala:87:24] wire out_f_roready_772 = out_roready_1_626 & out_romask_772; // @[RegisterRouter.scala:87:24] wire _out_T_7626 = out_f_roready_772; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_772 = out_wivalid_1_626 & out_wimask_772; // @[RegisterRouter.scala:87:24] wire out_f_woready_772 = out_woready_1_626 & out_womask_772; // @[RegisterRouter.scala:87:24] wire _out_T_7627 = ~out_rimask_772; // @[RegisterRouter.scala:87:24] wire _out_T_7628 = ~out_wimask_772; // @[RegisterRouter.scala:87:24] wire _out_T_7629 = ~out_romask_772; // @[RegisterRouter.scala:87:24] wire _out_T_7630 = ~out_womask_772; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_656 = {hi_426, flags_0_go, _out_prepend_T_656}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7631 = out_prepend_656; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7632 = _out_T_7631; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_657 = _out_T_7632; // @[RegisterRouter.scala:87:24] wire out_rimask_773 = |_out_rimask_T_773; // @[RegisterRouter.scala:87:24] wire out_wimask_773 = &_out_wimask_T_773; // @[RegisterRouter.scala:87:24] wire out_romask_773 = |_out_romask_T_773; // @[RegisterRouter.scala:87:24] wire out_womask_773 = &_out_womask_T_773; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_773 = out_rivalid_1_627 & out_rimask_773; // @[RegisterRouter.scala:87:24] wire _out_T_7634 = out_f_rivalid_773; // @[RegisterRouter.scala:87:24] wire out_f_roready_773 = out_roready_1_627 & out_romask_773; // @[RegisterRouter.scala:87:24] wire _out_T_7635 = out_f_roready_773; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_773 = out_wivalid_1_627 & out_wimask_773; // @[RegisterRouter.scala:87:24] wire out_f_woready_773 = out_woready_1_627 & out_womask_773; // @[RegisterRouter.scala:87:24] wire _out_T_7636 = ~out_rimask_773; // @[RegisterRouter.scala:87:24] wire _out_T_7637 = ~out_wimask_773; // @[RegisterRouter.scala:87:24] wire _out_T_7638 = ~out_romask_773; // @[RegisterRouter.scala:87:24] wire _out_T_7639 = ~out_womask_773; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_657 = {hi_427, flags_0_go, _out_prepend_T_657}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7640 = out_prepend_657; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7641 = _out_T_7640; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_658 = _out_T_7641; // @[RegisterRouter.scala:87:24] wire out_rimask_774 = |_out_rimask_T_774; // @[RegisterRouter.scala:87:24] wire out_wimask_774 = &_out_wimask_T_774; // @[RegisterRouter.scala:87:24] wire out_romask_774 = |_out_romask_T_774; // @[RegisterRouter.scala:87:24] wire out_womask_774 = &_out_womask_T_774; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_774 = out_rivalid_1_628 & out_rimask_774; // @[RegisterRouter.scala:87:24] wire _out_T_7643 = out_f_rivalid_774; // @[RegisterRouter.scala:87:24] wire out_f_roready_774 = out_roready_1_628 & out_romask_774; // @[RegisterRouter.scala:87:24] wire _out_T_7644 = out_f_roready_774; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_774 = out_wivalid_1_628 & out_wimask_774; // @[RegisterRouter.scala:87:24] wire out_f_woready_774 = out_woready_1_628 & out_womask_774; // @[RegisterRouter.scala:87:24] wire _out_T_7645 = ~out_rimask_774; // @[RegisterRouter.scala:87:24] wire _out_T_7646 = ~out_wimask_774; // @[RegisterRouter.scala:87:24] wire _out_T_7647 = ~out_romask_774; // @[RegisterRouter.scala:87:24] wire _out_T_7648 = ~out_womask_774; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_658 = {hi_428, flags_0_go, _out_prepend_T_658}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7649 = out_prepend_658; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7650 = _out_T_7649; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_659 = _out_T_7650; // @[RegisterRouter.scala:87:24] wire out_rimask_775 = |_out_rimask_T_775; // @[RegisterRouter.scala:87:24] wire out_wimask_775 = &_out_wimask_T_775; // @[RegisterRouter.scala:87:24] wire out_romask_775 = |_out_romask_T_775; // @[RegisterRouter.scala:87:24] wire out_womask_775 = &_out_womask_T_775; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_775 = out_rivalid_1_629 & out_rimask_775; // @[RegisterRouter.scala:87:24] wire _out_T_7652 = out_f_rivalid_775; // @[RegisterRouter.scala:87:24] wire out_f_roready_775 = out_roready_1_629 & out_romask_775; // @[RegisterRouter.scala:87:24] wire _out_T_7653 = out_f_roready_775; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_775 = out_wivalid_1_629 & out_wimask_775; // @[RegisterRouter.scala:87:24] wire out_f_woready_775 = out_woready_1_629 & out_womask_775; // @[RegisterRouter.scala:87:24] wire _out_T_7654 = ~out_rimask_775; // @[RegisterRouter.scala:87:24] wire _out_T_7655 = ~out_wimask_775; // @[RegisterRouter.scala:87:24] wire _out_T_7656 = ~out_romask_775; // @[RegisterRouter.scala:87:24] wire _out_T_7657 = ~out_womask_775; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_659 = {hi_429, flags_0_go, _out_prepend_T_659}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7658 = out_prepend_659; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7659 = _out_T_7658; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_660 = _out_T_7659; // @[RegisterRouter.scala:87:24] wire out_rimask_776 = |_out_rimask_T_776; // @[RegisterRouter.scala:87:24] wire out_wimask_776 = &_out_wimask_T_776; // @[RegisterRouter.scala:87:24] wire out_romask_776 = |_out_romask_T_776; // @[RegisterRouter.scala:87:24] wire out_womask_776 = &_out_womask_T_776; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_776 = out_rivalid_1_630 & out_rimask_776; // @[RegisterRouter.scala:87:24] wire _out_T_7661 = out_f_rivalid_776; // @[RegisterRouter.scala:87:24] wire out_f_roready_776 = out_roready_1_630 & out_romask_776; // @[RegisterRouter.scala:87:24] wire _out_T_7662 = out_f_roready_776; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_776 = out_wivalid_1_630 & out_wimask_776; // @[RegisterRouter.scala:87:24] wire out_f_woready_776 = out_woready_1_630 & out_womask_776; // @[RegisterRouter.scala:87:24] wire _out_T_7663 = ~out_rimask_776; // @[RegisterRouter.scala:87:24] wire _out_T_7664 = ~out_wimask_776; // @[RegisterRouter.scala:87:24] wire _out_T_7665 = ~out_romask_776; // @[RegisterRouter.scala:87:24] wire _out_T_7666 = ~out_womask_776; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_660 = {hi_430, flags_0_go, _out_prepend_T_660}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7667 = out_prepend_660; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7668 = _out_T_7667; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_661 = _out_T_7668; // @[RegisterRouter.scala:87:24] wire out_rimask_777 = |_out_rimask_T_777; // @[RegisterRouter.scala:87:24] wire out_wimask_777 = &_out_wimask_T_777; // @[RegisterRouter.scala:87:24] wire out_romask_777 = |_out_romask_T_777; // @[RegisterRouter.scala:87:24] wire out_womask_777 = &_out_womask_T_777; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_777 = out_rivalid_1_631 & out_rimask_777; // @[RegisterRouter.scala:87:24] wire _out_T_7670 = out_f_rivalid_777; // @[RegisterRouter.scala:87:24] wire out_f_roready_777 = out_roready_1_631 & out_romask_777; // @[RegisterRouter.scala:87:24] wire _out_T_7671 = out_f_roready_777; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_777 = out_wivalid_1_631 & out_wimask_777; // @[RegisterRouter.scala:87:24] wire out_f_woready_777 = out_woready_1_631 & out_womask_777; // @[RegisterRouter.scala:87:24] wire _out_T_7672 = ~out_rimask_777; // @[RegisterRouter.scala:87:24] wire _out_T_7673 = ~out_wimask_777; // @[RegisterRouter.scala:87:24] wire _out_T_7674 = ~out_romask_777; // @[RegisterRouter.scala:87:24] wire _out_T_7675 = ~out_womask_777; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_661 = {hi_431, flags_0_go, _out_prepend_T_661}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7676 = out_prepend_661; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7677 = _out_T_7676; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_662 = _out_T_7677; // @[RegisterRouter.scala:87:24] wire out_rimask_778 = |_out_rimask_T_778; // @[RegisterRouter.scala:87:24] wire out_wimask_778 = &_out_wimask_T_778; // @[RegisterRouter.scala:87:24] wire out_romask_778 = |_out_romask_T_778; // @[RegisterRouter.scala:87:24] wire out_womask_778 = &_out_womask_T_778; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_778 = out_rivalid_1_632 & out_rimask_778; // @[RegisterRouter.scala:87:24] wire _out_T_7679 = out_f_rivalid_778; // @[RegisterRouter.scala:87:24] wire out_f_roready_778 = out_roready_1_632 & out_romask_778; // @[RegisterRouter.scala:87:24] wire _out_T_7680 = out_f_roready_778; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_778 = out_wivalid_1_632 & out_wimask_778; // @[RegisterRouter.scala:87:24] wire out_f_woready_778 = out_woready_1_632 & out_womask_778; // @[RegisterRouter.scala:87:24] wire _out_T_7681 = ~out_rimask_778; // @[RegisterRouter.scala:87:24] wire _out_T_7682 = ~out_wimask_778; // @[RegisterRouter.scala:87:24] wire _out_T_7683 = ~out_romask_778; // @[RegisterRouter.scala:87:24] wire _out_T_7684 = ~out_womask_778; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_662 = {hi_432, flags_0_go, _out_prepend_T_662}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7685 = out_prepend_662; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7686 = _out_T_7685; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_181 = _out_T_7686; // @[MuxLiteral.scala:49:48] wire out_rimask_779 = |_out_rimask_T_779; // @[RegisterRouter.scala:87:24] wire out_wimask_779 = &_out_wimask_T_779; // @[RegisterRouter.scala:87:24] wire out_romask_779 = |_out_romask_T_779; // @[RegisterRouter.scala:87:24] wire out_womask_779 = &_out_womask_T_779; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_779 = out_rivalid_1_633 & out_rimask_779; // @[RegisterRouter.scala:87:24] wire _out_T_7688 = out_f_rivalid_779; // @[RegisterRouter.scala:87:24] wire out_f_roready_779 = out_roready_1_633 & out_romask_779; // @[RegisterRouter.scala:87:24] wire _out_T_7689 = out_f_roready_779; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_779 = out_wivalid_1_633 & out_wimask_779; // @[RegisterRouter.scala:87:24] wire out_f_woready_779 = out_woready_1_633 & out_womask_779; // @[RegisterRouter.scala:87:24] wire _out_T_7690 = ~out_rimask_779; // @[RegisterRouter.scala:87:24] wire _out_T_7691 = ~out_wimask_779; // @[RegisterRouter.scala:87:24] wire _out_T_7692 = ~out_romask_779; // @[RegisterRouter.scala:87:24] wire _out_T_7693 = ~out_womask_779; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7695 = _out_T_7694; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_663 = _out_T_7695; // @[RegisterRouter.scala:87:24] wire out_rimask_780 = |_out_rimask_T_780; // @[RegisterRouter.scala:87:24] wire out_wimask_780 = &_out_wimask_T_780; // @[RegisterRouter.scala:87:24] wire out_romask_780 = |_out_romask_T_780; // @[RegisterRouter.scala:87:24] wire out_womask_780 = &_out_womask_T_780; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_780 = out_rivalid_1_634 & out_rimask_780; // @[RegisterRouter.scala:87:24] wire _out_T_7697 = out_f_rivalid_780; // @[RegisterRouter.scala:87:24] wire out_f_roready_780 = out_roready_1_634 & out_romask_780; // @[RegisterRouter.scala:87:24] wire _out_T_7698 = out_f_roready_780; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_780 = out_wivalid_1_634 & out_wimask_780; // @[RegisterRouter.scala:87:24] wire out_f_woready_780 = out_woready_1_634 & out_womask_780; // @[RegisterRouter.scala:87:24] wire _out_T_7699 = ~out_rimask_780; // @[RegisterRouter.scala:87:24] wire _out_T_7700 = ~out_wimask_780; // @[RegisterRouter.scala:87:24] wire _out_T_7701 = ~out_romask_780; // @[RegisterRouter.scala:87:24] wire _out_T_7702 = ~out_womask_780; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_663 = {hi_250, flags_0_go, _out_prepend_T_663}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7703 = out_prepend_663; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7704 = _out_T_7703; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_664 = _out_T_7704; // @[RegisterRouter.scala:87:24] wire out_rimask_781 = |_out_rimask_T_781; // @[RegisterRouter.scala:87:24] wire out_wimask_781 = &_out_wimask_T_781; // @[RegisterRouter.scala:87:24] wire out_romask_781 = |_out_romask_T_781; // @[RegisterRouter.scala:87:24] wire out_womask_781 = &_out_womask_T_781; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_781 = out_rivalid_1_635 & out_rimask_781; // @[RegisterRouter.scala:87:24] wire _out_T_7706 = out_f_rivalid_781; // @[RegisterRouter.scala:87:24] wire out_f_roready_781 = out_roready_1_635 & out_romask_781; // @[RegisterRouter.scala:87:24] wire _out_T_7707 = out_f_roready_781; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_781 = out_wivalid_1_635 & out_wimask_781; // @[RegisterRouter.scala:87:24] wire out_f_woready_781 = out_woready_1_635 & out_womask_781; // @[RegisterRouter.scala:87:24] wire _out_T_7708 = ~out_rimask_781; // @[RegisterRouter.scala:87:24] wire _out_T_7709 = ~out_wimask_781; // @[RegisterRouter.scala:87:24] wire _out_T_7710 = ~out_romask_781; // @[RegisterRouter.scala:87:24] wire _out_T_7711 = ~out_womask_781; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_664 = {hi_251, flags_0_go, _out_prepend_T_664}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7712 = out_prepend_664; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7713 = _out_T_7712; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_665 = _out_T_7713; // @[RegisterRouter.scala:87:24] wire out_rimask_782 = |_out_rimask_T_782; // @[RegisterRouter.scala:87:24] wire out_wimask_782 = &_out_wimask_T_782; // @[RegisterRouter.scala:87:24] wire out_romask_782 = |_out_romask_T_782; // @[RegisterRouter.scala:87:24] wire out_womask_782 = &_out_womask_T_782; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_782 = out_rivalid_1_636 & out_rimask_782; // @[RegisterRouter.scala:87:24] wire _out_T_7715 = out_f_rivalid_782; // @[RegisterRouter.scala:87:24] wire out_f_roready_782 = out_roready_1_636 & out_romask_782; // @[RegisterRouter.scala:87:24] wire _out_T_7716 = out_f_roready_782; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_782 = out_wivalid_1_636 & out_wimask_782; // @[RegisterRouter.scala:87:24] wire out_f_woready_782 = out_woready_1_636 & out_womask_782; // @[RegisterRouter.scala:87:24] wire _out_T_7717 = ~out_rimask_782; // @[RegisterRouter.scala:87:24] wire _out_T_7718 = ~out_wimask_782; // @[RegisterRouter.scala:87:24] wire _out_T_7719 = ~out_romask_782; // @[RegisterRouter.scala:87:24] wire _out_T_7720 = ~out_womask_782; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_665 = {hi_252, flags_0_go, _out_prepend_T_665}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7721 = out_prepend_665; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7722 = _out_T_7721; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_666 = _out_T_7722; // @[RegisterRouter.scala:87:24] wire out_rimask_783 = |_out_rimask_T_783; // @[RegisterRouter.scala:87:24] wire out_wimask_783 = &_out_wimask_T_783; // @[RegisterRouter.scala:87:24] wire out_romask_783 = |_out_romask_T_783; // @[RegisterRouter.scala:87:24] wire out_womask_783 = &_out_womask_T_783; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_783 = out_rivalid_1_637 & out_rimask_783; // @[RegisterRouter.scala:87:24] wire _out_T_7724 = out_f_rivalid_783; // @[RegisterRouter.scala:87:24] wire out_f_roready_783 = out_roready_1_637 & out_romask_783; // @[RegisterRouter.scala:87:24] wire _out_T_7725 = out_f_roready_783; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_783 = out_wivalid_1_637 & out_wimask_783; // @[RegisterRouter.scala:87:24] wire out_f_woready_783 = out_woready_1_637 & out_womask_783; // @[RegisterRouter.scala:87:24] wire _out_T_7726 = ~out_rimask_783; // @[RegisterRouter.scala:87:24] wire _out_T_7727 = ~out_wimask_783; // @[RegisterRouter.scala:87:24] wire _out_T_7728 = ~out_romask_783; // @[RegisterRouter.scala:87:24] wire _out_T_7729 = ~out_womask_783; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_666 = {hi_253, flags_0_go, _out_prepend_T_666}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7730 = out_prepend_666; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7731 = _out_T_7730; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_667 = _out_T_7731; // @[RegisterRouter.scala:87:24] wire out_rimask_784 = |_out_rimask_T_784; // @[RegisterRouter.scala:87:24] wire out_wimask_784 = &_out_wimask_T_784; // @[RegisterRouter.scala:87:24] wire out_romask_784 = |_out_romask_T_784; // @[RegisterRouter.scala:87:24] wire out_womask_784 = &_out_womask_T_784; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_784 = out_rivalid_1_638 & out_rimask_784; // @[RegisterRouter.scala:87:24] wire _out_T_7733 = out_f_rivalid_784; // @[RegisterRouter.scala:87:24] wire out_f_roready_784 = out_roready_1_638 & out_romask_784; // @[RegisterRouter.scala:87:24] wire _out_T_7734 = out_f_roready_784; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_784 = out_wivalid_1_638 & out_wimask_784; // @[RegisterRouter.scala:87:24] wire out_f_woready_784 = out_woready_1_638 & out_womask_784; // @[RegisterRouter.scala:87:24] wire _out_T_7735 = ~out_rimask_784; // @[RegisterRouter.scala:87:24] wire _out_T_7736 = ~out_wimask_784; // @[RegisterRouter.scala:87:24] wire _out_T_7737 = ~out_romask_784; // @[RegisterRouter.scala:87:24] wire _out_T_7738 = ~out_womask_784; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_667 = {hi_254, flags_0_go, _out_prepend_T_667}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7739 = out_prepend_667; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7740 = _out_T_7739; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_668 = _out_T_7740; // @[RegisterRouter.scala:87:24] wire out_rimask_785 = |_out_rimask_T_785; // @[RegisterRouter.scala:87:24] wire out_wimask_785 = &_out_wimask_T_785; // @[RegisterRouter.scala:87:24] wire out_romask_785 = |_out_romask_T_785; // @[RegisterRouter.scala:87:24] wire out_womask_785 = &_out_womask_T_785; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_785 = out_rivalid_1_639 & out_rimask_785; // @[RegisterRouter.scala:87:24] wire _out_T_7742 = out_f_rivalid_785; // @[RegisterRouter.scala:87:24] wire out_f_roready_785 = out_roready_1_639 & out_romask_785; // @[RegisterRouter.scala:87:24] wire _out_T_7743 = out_f_roready_785; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_785 = out_wivalid_1_639 & out_wimask_785; // @[RegisterRouter.scala:87:24] wire out_f_woready_785 = out_woready_1_639 & out_womask_785; // @[RegisterRouter.scala:87:24] wire _out_T_7744 = ~out_rimask_785; // @[RegisterRouter.scala:87:24] wire _out_T_7745 = ~out_wimask_785; // @[RegisterRouter.scala:87:24] wire _out_T_7746 = ~out_romask_785; // @[RegisterRouter.scala:87:24] wire _out_T_7747 = ~out_womask_785; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_668 = {hi_255, flags_0_go, _out_prepend_T_668}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7748 = out_prepend_668; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7749 = _out_T_7748; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_669 = _out_T_7749; // @[RegisterRouter.scala:87:24] wire out_rimask_786 = |_out_rimask_T_786; // @[RegisterRouter.scala:87:24] wire out_wimask_786 = &_out_wimask_T_786; // @[RegisterRouter.scala:87:24] wire out_romask_786 = |_out_romask_T_786; // @[RegisterRouter.scala:87:24] wire out_womask_786 = &_out_womask_T_786; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_786 = out_rivalid_1_640 & out_rimask_786; // @[RegisterRouter.scala:87:24] wire _out_T_7751 = out_f_rivalid_786; // @[RegisterRouter.scala:87:24] wire out_f_roready_786 = out_roready_1_640 & out_romask_786; // @[RegisterRouter.scala:87:24] wire _out_T_7752 = out_f_roready_786; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_786 = out_wivalid_1_640 & out_wimask_786; // @[RegisterRouter.scala:87:24] wire out_f_woready_786 = out_woready_1_640 & out_womask_786; // @[RegisterRouter.scala:87:24] wire _out_T_7753 = ~out_rimask_786; // @[RegisterRouter.scala:87:24] wire _out_T_7754 = ~out_wimask_786; // @[RegisterRouter.scala:87:24] wire _out_T_7755 = ~out_romask_786; // @[RegisterRouter.scala:87:24] wire _out_T_7756 = ~out_womask_786; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_669 = {hi_256, flags_0_go, _out_prepend_T_669}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7757 = out_prepend_669; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7758 = _out_T_7757; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_159 = _out_T_7758; // @[MuxLiteral.scala:49:48] wire out_rimask_787 = |_out_rimask_T_787; // @[RegisterRouter.scala:87:24] wire out_wimask_787 = &_out_wimask_T_787; // @[RegisterRouter.scala:87:24] wire out_romask_787 = |_out_romask_T_787; // @[RegisterRouter.scala:87:24] wire out_womask_787 = &_out_womask_T_787; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_787 = out_rivalid_1_641 & out_rimask_787; // @[RegisterRouter.scala:87:24] wire _out_T_7760 = out_f_rivalid_787; // @[RegisterRouter.scala:87:24] wire out_f_roready_787 = out_roready_1_641 & out_romask_787; // @[RegisterRouter.scala:87:24] wire _out_T_7761 = out_f_roready_787; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_787 = out_wivalid_1_641 & out_wimask_787; // @[RegisterRouter.scala:87:24] wire out_f_woready_787 = out_woready_1_641 & out_womask_787; // @[RegisterRouter.scala:87:24] wire _out_T_7762 = ~out_rimask_787; // @[RegisterRouter.scala:87:24] wire _out_T_7763 = ~out_wimask_787; // @[RegisterRouter.scala:87:24] wire _out_T_7764 = ~out_romask_787; // @[RegisterRouter.scala:87:24] wire _out_T_7765 = ~out_womask_787; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7767 = _out_T_7766; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_670 = _out_T_7767; // @[RegisterRouter.scala:87:24] wire out_rimask_788 = |_out_rimask_T_788; // @[RegisterRouter.scala:87:24] wire out_wimask_788 = &_out_wimask_T_788; // @[RegisterRouter.scala:87:24] wire out_romask_788 = |_out_romask_T_788; // @[RegisterRouter.scala:87:24] wire out_womask_788 = &_out_womask_T_788; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_788 = out_rivalid_1_642 & out_rimask_788; // @[RegisterRouter.scala:87:24] wire _out_T_7769 = out_f_rivalid_788; // @[RegisterRouter.scala:87:24] wire out_f_roready_788 = out_roready_1_642 & out_romask_788; // @[RegisterRouter.scala:87:24] wire _out_T_7770 = out_f_roready_788; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_788 = out_wivalid_1_642 & out_wimask_788; // @[RegisterRouter.scala:87:24] wire out_f_woready_788 = out_woready_1_642 & out_womask_788; // @[RegisterRouter.scala:87:24] wire _out_T_7771 = ~out_rimask_788; // @[RegisterRouter.scala:87:24] wire _out_T_7772 = ~out_wimask_788; // @[RegisterRouter.scala:87:24] wire _out_T_7773 = ~out_romask_788; // @[RegisterRouter.scala:87:24] wire _out_T_7774 = ~out_womask_788; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_670 = {hi_474, flags_0_go, _out_prepend_T_670}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7775 = out_prepend_670; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7776 = _out_T_7775; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_671 = _out_T_7776; // @[RegisterRouter.scala:87:24] wire out_rimask_789 = |_out_rimask_T_789; // @[RegisterRouter.scala:87:24] wire out_wimask_789 = &_out_wimask_T_789; // @[RegisterRouter.scala:87:24] wire out_romask_789 = |_out_romask_T_789; // @[RegisterRouter.scala:87:24] wire out_womask_789 = &_out_womask_T_789; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_789 = out_rivalid_1_643 & out_rimask_789; // @[RegisterRouter.scala:87:24] wire _out_T_7778 = out_f_rivalid_789; // @[RegisterRouter.scala:87:24] wire out_f_roready_789 = out_roready_1_643 & out_romask_789; // @[RegisterRouter.scala:87:24] wire _out_T_7779 = out_f_roready_789; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_789 = out_wivalid_1_643 & out_wimask_789; // @[RegisterRouter.scala:87:24] wire out_f_woready_789 = out_woready_1_643 & out_womask_789; // @[RegisterRouter.scala:87:24] wire _out_T_7780 = ~out_rimask_789; // @[RegisterRouter.scala:87:24] wire _out_T_7781 = ~out_wimask_789; // @[RegisterRouter.scala:87:24] wire _out_T_7782 = ~out_romask_789; // @[RegisterRouter.scala:87:24] wire _out_T_7783 = ~out_womask_789; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_671 = {hi_475, flags_0_go, _out_prepend_T_671}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7784 = out_prepend_671; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7785 = _out_T_7784; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_672 = _out_T_7785; // @[RegisterRouter.scala:87:24] wire out_rimask_790 = |_out_rimask_T_790; // @[RegisterRouter.scala:87:24] wire out_wimask_790 = &_out_wimask_T_790; // @[RegisterRouter.scala:87:24] wire out_romask_790 = |_out_romask_T_790; // @[RegisterRouter.scala:87:24] wire out_womask_790 = &_out_womask_T_790; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_790 = out_rivalid_1_644 & out_rimask_790; // @[RegisterRouter.scala:87:24] wire _out_T_7787 = out_f_rivalid_790; // @[RegisterRouter.scala:87:24] wire out_f_roready_790 = out_roready_1_644 & out_romask_790; // @[RegisterRouter.scala:87:24] wire _out_T_7788 = out_f_roready_790; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_790 = out_wivalid_1_644 & out_wimask_790; // @[RegisterRouter.scala:87:24] wire out_f_woready_790 = out_woready_1_644 & out_womask_790; // @[RegisterRouter.scala:87:24] wire _out_T_7789 = ~out_rimask_790; // @[RegisterRouter.scala:87:24] wire _out_T_7790 = ~out_wimask_790; // @[RegisterRouter.scala:87:24] wire _out_T_7791 = ~out_romask_790; // @[RegisterRouter.scala:87:24] wire _out_T_7792 = ~out_womask_790; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_672 = {hi_476, flags_0_go, _out_prepend_T_672}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7793 = out_prepend_672; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7794 = _out_T_7793; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_673 = _out_T_7794; // @[RegisterRouter.scala:87:24] wire out_rimask_791 = |_out_rimask_T_791; // @[RegisterRouter.scala:87:24] wire out_wimask_791 = &_out_wimask_T_791; // @[RegisterRouter.scala:87:24] wire out_romask_791 = |_out_romask_T_791; // @[RegisterRouter.scala:87:24] wire out_womask_791 = &_out_womask_T_791; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_791 = out_rivalid_1_645 & out_rimask_791; // @[RegisterRouter.scala:87:24] wire _out_T_7796 = out_f_rivalid_791; // @[RegisterRouter.scala:87:24] wire out_f_roready_791 = out_roready_1_645 & out_romask_791; // @[RegisterRouter.scala:87:24] wire _out_T_7797 = out_f_roready_791; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_791 = out_wivalid_1_645 & out_wimask_791; // @[RegisterRouter.scala:87:24] wire out_f_woready_791 = out_woready_1_645 & out_womask_791; // @[RegisterRouter.scala:87:24] wire _out_T_7798 = ~out_rimask_791; // @[RegisterRouter.scala:87:24] wire _out_T_7799 = ~out_wimask_791; // @[RegisterRouter.scala:87:24] wire _out_T_7800 = ~out_romask_791; // @[RegisterRouter.scala:87:24] wire _out_T_7801 = ~out_womask_791; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_673 = {hi_477, flags_0_go, _out_prepend_T_673}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7802 = out_prepend_673; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7803 = _out_T_7802; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_674 = _out_T_7803; // @[RegisterRouter.scala:87:24] wire out_rimask_792 = |_out_rimask_T_792; // @[RegisterRouter.scala:87:24] wire out_wimask_792 = &_out_wimask_T_792; // @[RegisterRouter.scala:87:24] wire out_romask_792 = |_out_romask_T_792; // @[RegisterRouter.scala:87:24] wire out_womask_792 = &_out_womask_T_792; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_792 = out_rivalid_1_646 & out_rimask_792; // @[RegisterRouter.scala:87:24] wire _out_T_7805 = out_f_rivalid_792; // @[RegisterRouter.scala:87:24] wire out_f_roready_792 = out_roready_1_646 & out_romask_792; // @[RegisterRouter.scala:87:24] wire _out_T_7806 = out_f_roready_792; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_792 = out_wivalid_1_646 & out_wimask_792; // @[RegisterRouter.scala:87:24] wire out_f_woready_792 = out_woready_1_646 & out_womask_792; // @[RegisterRouter.scala:87:24] wire _out_T_7807 = ~out_rimask_792; // @[RegisterRouter.scala:87:24] wire _out_T_7808 = ~out_wimask_792; // @[RegisterRouter.scala:87:24] wire _out_T_7809 = ~out_romask_792; // @[RegisterRouter.scala:87:24] wire _out_T_7810 = ~out_womask_792; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_674 = {hi_478, flags_0_go, _out_prepend_T_674}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7811 = out_prepend_674; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7812 = _out_T_7811; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_675 = _out_T_7812; // @[RegisterRouter.scala:87:24] wire out_rimask_793 = |_out_rimask_T_793; // @[RegisterRouter.scala:87:24] wire out_wimask_793 = &_out_wimask_T_793; // @[RegisterRouter.scala:87:24] wire out_romask_793 = |_out_romask_T_793; // @[RegisterRouter.scala:87:24] wire out_womask_793 = &_out_womask_T_793; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_793 = out_rivalid_1_647 & out_rimask_793; // @[RegisterRouter.scala:87:24] wire _out_T_7814 = out_f_rivalid_793; // @[RegisterRouter.scala:87:24] wire out_f_roready_793 = out_roready_1_647 & out_romask_793; // @[RegisterRouter.scala:87:24] wire _out_T_7815 = out_f_roready_793; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_793 = out_wivalid_1_647 & out_wimask_793; // @[RegisterRouter.scala:87:24] wire out_f_woready_793 = out_woready_1_647 & out_womask_793; // @[RegisterRouter.scala:87:24] wire _out_T_7816 = ~out_rimask_793; // @[RegisterRouter.scala:87:24] wire _out_T_7817 = ~out_wimask_793; // @[RegisterRouter.scala:87:24] wire _out_T_7818 = ~out_romask_793; // @[RegisterRouter.scala:87:24] wire _out_T_7819 = ~out_womask_793; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_675 = {hi_479, flags_0_go, _out_prepend_T_675}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7820 = out_prepend_675; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7821 = _out_T_7820; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_676 = _out_T_7821; // @[RegisterRouter.scala:87:24] wire out_rimask_794 = |_out_rimask_T_794; // @[RegisterRouter.scala:87:24] wire out_wimask_794 = &_out_wimask_T_794; // @[RegisterRouter.scala:87:24] wire out_romask_794 = |_out_romask_T_794; // @[RegisterRouter.scala:87:24] wire out_womask_794 = &_out_womask_T_794; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_794 = out_rivalid_1_648 & out_rimask_794; // @[RegisterRouter.scala:87:24] wire _out_T_7823 = out_f_rivalid_794; // @[RegisterRouter.scala:87:24] wire out_f_roready_794 = out_roready_1_648 & out_romask_794; // @[RegisterRouter.scala:87:24] wire _out_T_7824 = out_f_roready_794; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_794 = out_wivalid_1_648 & out_wimask_794; // @[RegisterRouter.scala:87:24] wire out_f_woready_794 = out_woready_1_648 & out_womask_794; // @[RegisterRouter.scala:87:24] wire _out_T_7825 = ~out_rimask_794; // @[RegisterRouter.scala:87:24] wire _out_T_7826 = ~out_wimask_794; // @[RegisterRouter.scala:87:24] wire _out_T_7827 = ~out_romask_794; // @[RegisterRouter.scala:87:24] wire _out_T_7828 = ~out_womask_794; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_676 = {hi_480, flags_0_go, _out_prepend_T_676}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7829 = out_prepend_676; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7830 = _out_T_7829; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_187 = _out_T_7830; // @[MuxLiteral.scala:49:48] wire out_rimask_795 = |_out_rimask_T_795; // @[RegisterRouter.scala:87:24] wire out_wimask_795 = &_out_wimask_T_795; // @[RegisterRouter.scala:87:24] wire out_romask_795 = |_out_romask_T_795; // @[RegisterRouter.scala:87:24] wire out_womask_795 = &_out_womask_T_795; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_795 = out_rivalid_1_649 & out_rimask_795; // @[RegisterRouter.scala:87:24] wire _out_T_7832 = out_f_rivalid_795; // @[RegisterRouter.scala:87:24] wire out_f_roready_795 = out_roready_1_649 & out_romask_795; // @[RegisterRouter.scala:87:24] wire _out_T_7833 = out_f_roready_795; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_795 = out_wivalid_1_649 & out_wimask_795; // @[RegisterRouter.scala:87:24] wire out_f_woready_795 = out_woready_1_649 & out_womask_795; // @[RegisterRouter.scala:87:24] wire _out_T_7834 = ~out_rimask_795; // @[RegisterRouter.scala:87:24] wire _out_T_7835 = ~out_wimask_795; // @[RegisterRouter.scala:87:24] wire _out_T_7836 = ~out_romask_795; // @[RegisterRouter.scala:87:24] wire _out_T_7837 = ~out_womask_795; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7839 = _out_T_7838; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_677 = _out_T_7839; // @[RegisterRouter.scala:87:24] wire out_rimask_796 = |_out_rimask_T_796; // @[RegisterRouter.scala:87:24] wire out_wimask_796 = &_out_wimask_T_796; // @[RegisterRouter.scala:87:24] wire out_romask_796 = |_out_romask_T_796; // @[RegisterRouter.scala:87:24] wire out_womask_796 = &_out_womask_T_796; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_796 = out_rivalid_1_650 & out_rimask_796; // @[RegisterRouter.scala:87:24] wire _out_T_7841 = out_f_rivalid_796; // @[RegisterRouter.scala:87:24] wire out_f_roready_796 = out_roready_1_650 & out_romask_796; // @[RegisterRouter.scala:87:24] wire _out_T_7842 = out_f_roready_796; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_796 = out_wivalid_1_650 & out_wimask_796; // @[RegisterRouter.scala:87:24] wire out_f_woready_796 = out_woready_1_650 & out_womask_796; // @[RegisterRouter.scala:87:24] wire _out_T_7843 = ~out_rimask_796; // @[RegisterRouter.scala:87:24] wire _out_T_7844 = ~out_wimask_796; // @[RegisterRouter.scala:87:24] wire _out_T_7845 = ~out_romask_796; // @[RegisterRouter.scala:87:24] wire _out_T_7846 = ~out_womask_796; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_677 = {hi_354, flags_0_go, _out_prepend_T_677}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7847 = out_prepend_677; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7848 = _out_T_7847; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_678 = _out_T_7848; // @[RegisterRouter.scala:87:24] wire out_rimask_797 = |_out_rimask_T_797; // @[RegisterRouter.scala:87:24] wire out_wimask_797 = &_out_wimask_T_797; // @[RegisterRouter.scala:87:24] wire out_romask_797 = |_out_romask_T_797; // @[RegisterRouter.scala:87:24] wire out_womask_797 = &_out_womask_T_797; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_797 = out_rivalid_1_651 & out_rimask_797; // @[RegisterRouter.scala:87:24] wire _out_T_7850 = out_f_rivalid_797; // @[RegisterRouter.scala:87:24] wire out_f_roready_797 = out_roready_1_651 & out_romask_797; // @[RegisterRouter.scala:87:24] wire _out_T_7851 = out_f_roready_797; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_797 = out_wivalid_1_651 & out_wimask_797; // @[RegisterRouter.scala:87:24] wire out_f_woready_797 = out_woready_1_651 & out_womask_797; // @[RegisterRouter.scala:87:24] wire _out_T_7852 = ~out_rimask_797; // @[RegisterRouter.scala:87:24] wire _out_T_7853 = ~out_wimask_797; // @[RegisterRouter.scala:87:24] wire _out_T_7854 = ~out_romask_797; // @[RegisterRouter.scala:87:24] wire _out_T_7855 = ~out_womask_797; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_678 = {hi_355, flags_0_go, _out_prepend_T_678}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7856 = out_prepend_678; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7857 = _out_T_7856; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_679 = _out_T_7857; // @[RegisterRouter.scala:87:24] wire out_rimask_798 = |_out_rimask_T_798; // @[RegisterRouter.scala:87:24] wire out_wimask_798 = &_out_wimask_T_798; // @[RegisterRouter.scala:87:24] wire out_romask_798 = |_out_romask_T_798; // @[RegisterRouter.scala:87:24] wire out_womask_798 = &_out_womask_T_798; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_798 = out_rivalid_1_652 & out_rimask_798; // @[RegisterRouter.scala:87:24] wire _out_T_7859 = out_f_rivalid_798; // @[RegisterRouter.scala:87:24] wire out_f_roready_798 = out_roready_1_652 & out_romask_798; // @[RegisterRouter.scala:87:24] wire _out_T_7860 = out_f_roready_798; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_798 = out_wivalid_1_652 & out_wimask_798; // @[RegisterRouter.scala:87:24] wire out_f_woready_798 = out_woready_1_652 & out_womask_798; // @[RegisterRouter.scala:87:24] wire _out_T_7861 = ~out_rimask_798; // @[RegisterRouter.scala:87:24] wire _out_T_7862 = ~out_wimask_798; // @[RegisterRouter.scala:87:24] wire _out_T_7863 = ~out_romask_798; // @[RegisterRouter.scala:87:24] wire _out_T_7864 = ~out_womask_798; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_679 = {hi_356, flags_0_go, _out_prepend_T_679}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7865 = out_prepend_679; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7866 = _out_T_7865; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_680 = _out_T_7866; // @[RegisterRouter.scala:87:24] wire out_rimask_799 = |_out_rimask_T_799; // @[RegisterRouter.scala:87:24] wire out_wimask_799 = &_out_wimask_T_799; // @[RegisterRouter.scala:87:24] wire out_romask_799 = |_out_romask_T_799; // @[RegisterRouter.scala:87:24] wire out_womask_799 = &_out_womask_T_799; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_799 = out_rivalid_1_653 & out_rimask_799; // @[RegisterRouter.scala:87:24] wire _out_T_7868 = out_f_rivalid_799; // @[RegisterRouter.scala:87:24] wire out_f_roready_799 = out_roready_1_653 & out_romask_799; // @[RegisterRouter.scala:87:24] wire _out_T_7869 = out_f_roready_799; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_799 = out_wivalid_1_653 & out_wimask_799; // @[RegisterRouter.scala:87:24] wire out_f_woready_799 = out_woready_1_653 & out_womask_799; // @[RegisterRouter.scala:87:24] wire _out_T_7870 = ~out_rimask_799; // @[RegisterRouter.scala:87:24] wire _out_T_7871 = ~out_wimask_799; // @[RegisterRouter.scala:87:24] wire _out_T_7872 = ~out_romask_799; // @[RegisterRouter.scala:87:24] wire _out_T_7873 = ~out_womask_799; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_680 = {hi_357, flags_0_go, _out_prepend_T_680}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7874 = out_prepend_680; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7875 = _out_T_7874; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_681 = _out_T_7875; // @[RegisterRouter.scala:87:24] wire out_rimask_800 = |_out_rimask_T_800; // @[RegisterRouter.scala:87:24] wire out_wimask_800 = &_out_wimask_T_800; // @[RegisterRouter.scala:87:24] wire out_romask_800 = |_out_romask_T_800; // @[RegisterRouter.scala:87:24] wire out_womask_800 = &_out_womask_T_800; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_800 = out_rivalid_1_654 & out_rimask_800; // @[RegisterRouter.scala:87:24] wire _out_T_7877 = out_f_rivalid_800; // @[RegisterRouter.scala:87:24] wire out_f_roready_800 = out_roready_1_654 & out_romask_800; // @[RegisterRouter.scala:87:24] wire _out_T_7878 = out_f_roready_800; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_800 = out_wivalid_1_654 & out_wimask_800; // @[RegisterRouter.scala:87:24] wire out_f_woready_800 = out_woready_1_654 & out_womask_800; // @[RegisterRouter.scala:87:24] wire _out_T_7879 = ~out_rimask_800; // @[RegisterRouter.scala:87:24] wire _out_T_7880 = ~out_wimask_800; // @[RegisterRouter.scala:87:24] wire _out_T_7881 = ~out_romask_800; // @[RegisterRouter.scala:87:24] wire _out_T_7882 = ~out_womask_800; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_681 = {hi_358, flags_0_go, _out_prepend_T_681}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7883 = out_prepend_681; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7884 = _out_T_7883; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_682 = _out_T_7884; // @[RegisterRouter.scala:87:24] wire out_rimask_801 = |_out_rimask_T_801; // @[RegisterRouter.scala:87:24] wire out_wimask_801 = &_out_wimask_T_801; // @[RegisterRouter.scala:87:24] wire out_romask_801 = |_out_romask_T_801; // @[RegisterRouter.scala:87:24] wire out_womask_801 = &_out_womask_T_801; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_801 = out_rivalid_1_655 & out_rimask_801; // @[RegisterRouter.scala:87:24] wire _out_T_7886 = out_f_rivalid_801; // @[RegisterRouter.scala:87:24] wire out_f_roready_801 = out_roready_1_655 & out_romask_801; // @[RegisterRouter.scala:87:24] wire _out_T_7887 = out_f_roready_801; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_801 = out_wivalid_1_655 & out_wimask_801; // @[RegisterRouter.scala:87:24] wire out_f_woready_801 = out_woready_1_655 & out_womask_801; // @[RegisterRouter.scala:87:24] wire _out_T_7888 = ~out_rimask_801; // @[RegisterRouter.scala:87:24] wire _out_T_7889 = ~out_wimask_801; // @[RegisterRouter.scala:87:24] wire _out_T_7890 = ~out_romask_801; // @[RegisterRouter.scala:87:24] wire _out_T_7891 = ~out_womask_801; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_682 = {hi_359, flags_0_go, _out_prepend_T_682}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7892 = out_prepend_682; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7893 = _out_T_7892; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_683 = _out_T_7893; // @[RegisterRouter.scala:87:24] wire out_rimask_802 = |_out_rimask_T_802; // @[RegisterRouter.scala:87:24] wire out_wimask_802 = &_out_wimask_T_802; // @[RegisterRouter.scala:87:24] wire out_romask_802 = |_out_romask_T_802; // @[RegisterRouter.scala:87:24] wire out_womask_802 = &_out_womask_T_802; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_802 = out_rivalid_1_656 & out_rimask_802; // @[RegisterRouter.scala:87:24] wire _out_T_7895 = out_f_rivalid_802; // @[RegisterRouter.scala:87:24] wire out_f_roready_802 = out_roready_1_656 & out_romask_802; // @[RegisterRouter.scala:87:24] wire _out_T_7896 = out_f_roready_802; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_802 = out_wivalid_1_656 & out_wimask_802; // @[RegisterRouter.scala:87:24] wire out_f_woready_802 = out_woready_1_656 & out_womask_802; // @[RegisterRouter.scala:87:24] wire _out_T_7897 = ~out_rimask_802; // @[RegisterRouter.scala:87:24] wire _out_T_7898 = ~out_wimask_802; // @[RegisterRouter.scala:87:24] wire _out_T_7899 = ~out_romask_802; // @[RegisterRouter.scala:87:24] wire _out_T_7900 = ~out_womask_802; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_683 = {hi_360, flags_0_go, _out_prepend_T_683}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7901 = out_prepend_683; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7902 = _out_T_7901; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_172 = _out_T_7902; // @[MuxLiteral.scala:49:48] wire out_rimask_803 = |_out_rimask_T_803; // @[RegisterRouter.scala:87:24] wire out_wimask_803 = &_out_wimask_T_803; // @[RegisterRouter.scala:87:24] wire out_romask_803 = |_out_romask_T_803; // @[RegisterRouter.scala:87:24] wire out_womask_803 = &_out_womask_T_803; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_803 = out_rivalid_1_657 & out_rimask_803; // @[RegisterRouter.scala:87:24] wire _out_T_7904 = out_f_rivalid_803; // @[RegisterRouter.scala:87:24] wire out_f_roready_803 = out_roready_1_657 & out_romask_803; // @[RegisterRouter.scala:87:24] wire _out_T_7905 = out_f_roready_803; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_803 = out_wivalid_1_657 & out_wimask_803; // @[RegisterRouter.scala:87:24] wire _out_T_7906 = out_f_wivalid_803; // @[RegisterRouter.scala:87:24] wire out_f_woready_803 = out_woready_1_657 & out_womask_803; // @[RegisterRouter.scala:87:24] wire _out_T_7907 = out_f_woready_803; // @[RegisterRouter.scala:87:24] wire _out_T_7908 = ~out_rimask_803; // @[RegisterRouter.scala:87:24] wire _out_T_7909 = ~out_wimask_803; // @[RegisterRouter.scala:87:24] wire _out_T_7910 = ~out_romask_803; // @[RegisterRouter.scala:87:24] wire _out_T_7911 = ~out_womask_803; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7913 = _out_T_7912; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_684 = _out_T_7913; // @[RegisterRouter.scala:87:24] wire out_rimask_804 = |_out_rimask_T_804; // @[RegisterRouter.scala:87:24] wire out_wimask_804 = &_out_wimask_T_804; // @[RegisterRouter.scala:87:24] wire out_romask_804 = |_out_romask_T_804; // @[RegisterRouter.scala:87:24] wire out_womask_804 = &_out_womask_T_804; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_804 = out_rivalid_1_658 & out_rimask_804; // @[RegisterRouter.scala:87:24] wire _out_T_7915 = out_f_rivalid_804; // @[RegisterRouter.scala:87:24] wire out_f_roready_804 = out_roready_1_658 & out_romask_804; // @[RegisterRouter.scala:87:24] wire _out_T_7916 = out_f_roready_804; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_804 = out_wivalid_1_658 & out_wimask_804; // @[RegisterRouter.scala:87:24] wire _out_T_7917 = out_f_wivalid_804; // @[RegisterRouter.scala:87:24] wire out_f_woready_804 = out_woready_1_658 & out_womask_804; // @[RegisterRouter.scala:87:24] wire _out_T_7918 = out_f_woready_804; // @[RegisterRouter.scala:87:24] wire _out_T_7919 = ~out_rimask_804; // @[RegisterRouter.scala:87:24] wire _out_T_7920 = ~out_wimask_804; // @[RegisterRouter.scala:87:24] wire _out_T_7921 = ~out_romask_804; // @[RegisterRouter.scala:87:24] wire _out_T_7922 = ~out_womask_804; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_684 = {abstractDataMem_9, _out_prepend_T_684}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7923 = out_prepend_684; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7924 = _out_T_7923; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_685 = _out_T_7924; // @[RegisterRouter.scala:87:24] wire out_rimask_805 = |_out_rimask_T_805; // @[RegisterRouter.scala:87:24] wire out_wimask_805 = &_out_wimask_T_805; // @[RegisterRouter.scala:87:24] wire out_romask_805 = |_out_romask_T_805; // @[RegisterRouter.scala:87:24] wire out_womask_805 = &_out_womask_T_805; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_805 = out_rivalid_1_659 & out_rimask_805; // @[RegisterRouter.scala:87:24] wire _out_T_7926 = out_f_rivalid_805; // @[RegisterRouter.scala:87:24] wire out_f_roready_805 = out_roready_1_659 & out_romask_805; // @[RegisterRouter.scala:87:24] wire _out_T_7927 = out_f_roready_805; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_805 = out_wivalid_1_659 & out_wimask_805; // @[RegisterRouter.scala:87:24] wire _out_T_7928 = out_f_wivalid_805; // @[RegisterRouter.scala:87:24] wire out_f_woready_805 = out_woready_1_659 & out_womask_805; // @[RegisterRouter.scala:87:24] wire _out_T_7929 = out_f_woready_805; // @[RegisterRouter.scala:87:24] wire _out_T_7930 = ~out_rimask_805; // @[RegisterRouter.scala:87:24] wire _out_T_7931 = ~out_wimask_805; // @[RegisterRouter.scala:87:24] wire _out_T_7932 = ~out_romask_805; // @[RegisterRouter.scala:87:24] wire _out_T_7933 = ~out_womask_805; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_685 = {abstractDataMem_10, _out_prepend_T_685}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7934 = out_prepend_685; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7935 = _out_T_7934; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_686 = _out_T_7935; // @[RegisterRouter.scala:87:24] wire out_rimask_806 = |_out_rimask_T_806; // @[RegisterRouter.scala:87:24] wire out_wimask_806 = &_out_wimask_T_806; // @[RegisterRouter.scala:87:24] wire out_romask_806 = |_out_romask_T_806; // @[RegisterRouter.scala:87:24] wire out_womask_806 = &_out_womask_T_806; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_806 = out_rivalid_1_660 & out_rimask_806; // @[RegisterRouter.scala:87:24] wire _out_T_7937 = out_f_rivalid_806; // @[RegisterRouter.scala:87:24] wire out_f_roready_806 = out_roready_1_660 & out_romask_806; // @[RegisterRouter.scala:87:24] wire _out_T_7938 = out_f_roready_806; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_806 = out_wivalid_1_660 & out_wimask_806; // @[RegisterRouter.scala:87:24] wire _out_T_7939 = out_f_wivalid_806; // @[RegisterRouter.scala:87:24] wire out_f_woready_806 = out_woready_1_660 & out_womask_806; // @[RegisterRouter.scala:87:24] wire _out_T_7940 = out_f_woready_806; // @[RegisterRouter.scala:87:24] wire _out_T_7941 = ~out_rimask_806; // @[RegisterRouter.scala:87:24] wire _out_T_7942 = ~out_wimask_806; // @[RegisterRouter.scala:87:24] wire _out_T_7943 = ~out_romask_806; // @[RegisterRouter.scala:87:24] wire _out_T_7944 = ~out_womask_806; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_686 = {abstractDataMem_11, _out_prepend_T_686}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7945 = out_prepend_686; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7946 = _out_T_7945; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_687 = _out_T_7946; // @[RegisterRouter.scala:87:24] wire out_rimask_807 = |_out_rimask_T_807; // @[RegisterRouter.scala:87:24] wire out_wimask_807 = &_out_wimask_T_807; // @[RegisterRouter.scala:87:24] wire out_romask_807 = |_out_romask_T_807; // @[RegisterRouter.scala:87:24] wire out_womask_807 = &_out_womask_T_807; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_807 = out_rivalid_1_661 & out_rimask_807; // @[RegisterRouter.scala:87:24] wire _out_T_7948 = out_f_rivalid_807; // @[RegisterRouter.scala:87:24] wire out_f_roready_807 = out_roready_1_661 & out_romask_807; // @[RegisterRouter.scala:87:24] wire _out_T_7949 = out_f_roready_807; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_807 = out_wivalid_1_661 & out_wimask_807; // @[RegisterRouter.scala:87:24] wire _out_T_7950 = out_f_wivalid_807; // @[RegisterRouter.scala:87:24] wire out_f_woready_807 = out_woready_1_661 & out_womask_807; // @[RegisterRouter.scala:87:24] wire _out_T_7951 = out_f_woready_807; // @[RegisterRouter.scala:87:24] wire _out_T_7952 = ~out_rimask_807; // @[RegisterRouter.scala:87:24] wire _out_T_7953 = ~out_wimask_807; // @[RegisterRouter.scala:87:24] wire _out_T_7954 = ~out_romask_807; // @[RegisterRouter.scala:87:24] wire _out_T_7955 = ~out_womask_807; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_687 = {abstractDataMem_12, _out_prepend_T_687}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7956 = out_prepend_687; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7957 = _out_T_7956; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_688 = _out_T_7957; // @[RegisterRouter.scala:87:24] wire out_rimask_808 = |_out_rimask_T_808; // @[RegisterRouter.scala:87:24] wire out_wimask_808 = &_out_wimask_T_808; // @[RegisterRouter.scala:87:24] wire out_romask_808 = |_out_romask_T_808; // @[RegisterRouter.scala:87:24] wire out_womask_808 = &_out_womask_T_808; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_808 = out_rivalid_1_662 & out_rimask_808; // @[RegisterRouter.scala:87:24] wire _out_T_7959 = out_f_rivalid_808; // @[RegisterRouter.scala:87:24] wire out_f_roready_808 = out_roready_1_662 & out_romask_808; // @[RegisterRouter.scala:87:24] wire _out_T_7960 = out_f_roready_808; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_808 = out_wivalid_1_662 & out_wimask_808; // @[RegisterRouter.scala:87:24] wire _out_T_7961 = out_f_wivalid_808; // @[RegisterRouter.scala:87:24] wire out_f_woready_808 = out_woready_1_662 & out_womask_808; // @[RegisterRouter.scala:87:24] wire _out_T_7962 = out_f_woready_808; // @[RegisterRouter.scala:87:24] wire _out_T_7963 = ~out_rimask_808; // @[RegisterRouter.scala:87:24] wire _out_T_7964 = ~out_wimask_808; // @[RegisterRouter.scala:87:24] wire _out_T_7965 = ~out_romask_808; // @[RegisterRouter.scala:87:24] wire _out_T_7966 = ~out_womask_808; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_688 = {abstractDataMem_13, _out_prepend_T_688}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7967 = out_prepend_688; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7968 = _out_T_7967; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_689 = _out_T_7968; // @[RegisterRouter.scala:87:24] wire out_rimask_809 = |_out_rimask_T_809; // @[RegisterRouter.scala:87:24] wire out_wimask_809 = &_out_wimask_T_809; // @[RegisterRouter.scala:87:24] wire out_romask_809 = |_out_romask_T_809; // @[RegisterRouter.scala:87:24] wire out_womask_809 = &_out_womask_T_809; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_809 = out_rivalid_1_663 & out_rimask_809; // @[RegisterRouter.scala:87:24] wire _out_T_7970 = out_f_rivalid_809; // @[RegisterRouter.scala:87:24] wire out_f_roready_809 = out_roready_1_663 & out_romask_809; // @[RegisterRouter.scala:87:24] wire _out_T_7971 = out_f_roready_809; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_809 = out_wivalid_1_663 & out_wimask_809; // @[RegisterRouter.scala:87:24] wire _out_T_7972 = out_f_wivalid_809; // @[RegisterRouter.scala:87:24] wire out_f_woready_809 = out_woready_1_663 & out_womask_809; // @[RegisterRouter.scala:87:24] wire _out_T_7973 = out_f_woready_809; // @[RegisterRouter.scala:87:24] wire _out_T_7974 = ~out_rimask_809; // @[RegisterRouter.scala:87:24] wire _out_T_7975 = ~out_wimask_809; // @[RegisterRouter.scala:87:24] wire _out_T_7976 = ~out_romask_809; // @[RegisterRouter.scala:87:24] wire _out_T_7977 = ~out_womask_809; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_689 = {abstractDataMem_14, _out_prepend_T_689}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7978 = out_prepend_689; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7979 = _out_T_7978; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_690 = _out_T_7979; // @[RegisterRouter.scala:87:24] wire out_rimask_810 = |_out_rimask_T_810; // @[RegisterRouter.scala:87:24] wire out_wimask_810 = &_out_wimask_T_810; // @[RegisterRouter.scala:87:24] wire out_romask_810 = |_out_romask_T_810; // @[RegisterRouter.scala:87:24] wire out_womask_810 = &_out_womask_T_810; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_810 = out_rivalid_1_664 & out_rimask_810; // @[RegisterRouter.scala:87:24] wire _out_T_7981 = out_f_rivalid_810; // @[RegisterRouter.scala:87:24] wire out_f_roready_810 = out_roready_1_664 & out_romask_810; // @[RegisterRouter.scala:87:24] wire _out_T_7982 = out_f_roready_810; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_810 = out_wivalid_1_664 & out_wimask_810; // @[RegisterRouter.scala:87:24] wire _out_T_7983 = out_f_wivalid_810; // @[RegisterRouter.scala:87:24] wire out_f_woready_810 = out_woready_1_664 & out_womask_810; // @[RegisterRouter.scala:87:24] wire _out_T_7984 = out_f_woready_810; // @[RegisterRouter.scala:87:24] wire _out_T_7985 = ~out_rimask_810; // @[RegisterRouter.scala:87:24] wire _out_T_7986 = ~out_wimask_810; // @[RegisterRouter.scala:87:24] wire _out_T_7987 = ~out_romask_810; // @[RegisterRouter.scala:87:24] wire _out_T_7988 = ~out_womask_810; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_690 = {abstractDataMem_15, _out_prepend_T_690}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7989 = out_prepend_690; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7990 = _out_T_7989; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_113 = _out_T_7990; // @[MuxLiteral.scala:49:48] wire out_rimask_811 = |_out_rimask_T_811; // @[RegisterRouter.scala:87:24] wire out_wimask_811 = &_out_wimask_T_811; // @[RegisterRouter.scala:87:24] wire out_romask_811 = |_out_romask_T_811; // @[RegisterRouter.scala:87:24] wire out_womask_811 = &_out_womask_T_811; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_811 = out_rivalid_1_665 & out_rimask_811; // @[RegisterRouter.scala:87:24] wire _out_T_7992 = out_f_rivalid_811; // @[RegisterRouter.scala:87:24] wire out_f_roready_811 = out_roready_1_665 & out_romask_811; // @[RegisterRouter.scala:87:24] wire _out_T_7993 = out_f_roready_811; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_811 = out_wivalid_1_665 & out_wimask_811; // @[RegisterRouter.scala:87:24] wire out_f_woready_811 = out_woready_1_665 & out_womask_811; // @[RegisterRouter.scala:87:24] wire _out_T_7994 = ~out_rimask_811; // @[RegisterRouter.scala:87:24] wire _out_T_7995 = ~out_wimask_811; // @[RegisterRouter.scala:87:24] wire _out_T_7996 = ~out_romask_811; // @[RegisterRouter.scala:87:24] wire _out_T_7997 = ~out_womask_811; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7999 = _out_T_7998; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_691 = _out_T_7999; // @[RegisterRouter.scala:87:24] wire out_rimask_812 = |_out_rimask_T_812; // @[RegisterRouter.scala:87:24] wire out_wimask_812 = &_out_wimask_T_812; // @[RegisterRouter.scala:87:24] wire out_romask_812 = |_out_romask_T_812; // @[RegisterRouter.scala:87:24] wire out_womask_812 = &_out_womask_T_812; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_812 = out_rivalid_1_666 & out_rimask_812; // @[RegisterRouter.scala:87:24] wire _out_T_8001 = out_f_rivalid_812; // @[RegisterRouter.scala:87:24] wire out_f_roready_812 = out_roready_1_666 & out_romask_812; // @[RegisterRouter.scala:87:24] wire _out_T_8002 = out_f_roready_812; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_812 = out_wivalid_1_666 & out_wimask_812; // @[RegisterRouter.scala:87:24] wire out_f_woready_812 = out_woready_1_666 & out_womask_812; // @[RegisterRouter.scala:87:24] wire _out_T_8003 = ~out_rimask_812; // @[RegisterRouter.scala:87:24] wire _out_T_8004 = ~out_wimask_812; // @[RegisterRouter.scala:87:24] wire _out_T_8005 = ~out_romask_812; // @[RegisterRouter.scala:87:24] wire _out_T_8006 = ~out_womask_812; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_691 = {hi_730, flags_0_go, _out_prepend_T_691}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8007 = out_prepend_691; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8008 = _out_T_8007; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_692 = _out_T_8008; // @[RegisterRouter.scala:87:24] wire out_rimask_813 = |_out_rimask_T_813; // @[RegisterRouter.scala:87:24] wire out_wimask_813 = &_out_wimask_T_813; // @[RegisterRouter.scala:87:24] wire out_romask_813 = |_out_romask_T_813; // @[RegisterRouter.scala:87:24] wire out_womask_813 = &_out_womask_T_813; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_813 = out_rivalid_1_667 & out_rimask_813; // @[RegisterRouter.scala:87:24] wire _out_T_8010 = out_f_rivalid_813; // @[RegisterRouter.scala:87:24] wire out_f_roready_813 = out_roready_1_667 & out_romask_813; // @[RegisterRouter.scala:87:24] wire _out_T_8011 = out_f_roready_813; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_813 = out_wivalid_1_667 & out_wimask_813; // @[RegisterRouter.scala:87:24] wire out_f_woready_813 = out_woready_1_667 & out_womask_813; // @[RegisterRouter.scala:87:24] wire _out_T_8012 = ~out_rimask_813; // @[RegisterRouter.scala:87:24] wire _out_T_8013 = ~out_wimask_813; // @[RegisterRouter.scala:87:24] wire _out_T_8014 = ~out_romask_813; // @[RegisterRouter.scala:87:24] wire _out_T_8015 = ~out_womask_813; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_692 = {hi_731, flags_0_go, _out_prepend_T_692}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8016 = out_prepend_692; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8017 = _out_T_8016; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_693 = _out_T_8017; // @[RegisterRouter.scala:87:24] wire out_rimask_814 = |_out_rimask_T_814; // @[RegisterRouter.scala:87:24] wire out_wimask_814 = &_out_wimask_T_814; // @[RegisterRouter.scala:87:24] wire out_romask_814 = |_out_romask_T_814; // @[RegisterRouter.scala:87:24] wire out_womask_814 = &_out_womask_T_814; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_814 = out_rivalid_1_668 & out_rimask_814; // @[RegisterRouter.scala:87:24] wire _out_T_8019 = out_f_rivalid_814; // @[RegisterRouter.scala:87:24] wire out_f_roready_814 = out_roready_1_668 & out_romask_814; // @[RegisterRouter.scala:87:24] wire _out_T_8020 = out_f_roready_814; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_814 = out_wivalid_1_668 & out_wimask_814; // @[RegisterRouter.scala:87:24] wire out_f_woready_814 = out_woready_1_668 & out_womask_814; // @[RegisterRouter.scala:87:24] wire _out_T_8021 = ~out_rimask_814; // @[RegisterRouter.scala:87:24] wire _out_T_8022 = ~out_wimask_814; // @[RegisterRouter.scala:87:24] wire _out_T_8023 = ~out_romask_814; // @[RegisterRouter.scala:87:24] wire _out_T_8024 = ~out_womask_814; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_693 = {hi_732, flags_0_go, _out_prepend_T_693}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8025 = out_prepend_693; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8026 = _out_T_8025; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_694 = _out_T_8026; // @[RegisterRouter.scala:87:24] wire out_rimask_815 = |_out_rimask_T_815; // @[RegisterRouter.scala:87:24] wire out_wimask_815 = &_out_wimask_T_815; // @[RegisterRouter.scala:87:24] wire out_romask_815 = |_out_romask_T_815; // @[RegisterRouter.scala:87:24] wire out_womask_815 = &_out_womask_T_815; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_815 = out_rivalid_1_669 & out_rimask_815; // @[RegisterRouter.scala:87:24] wire _out_T_8028 = out_f_rivalid_815; // @[RegisterRouter.scala:87:24] wire out_f_roready_815 = out_roready_1_669 & out_romask_815; // @[RegisterRouter.scala:87:24] wire _out_T_8029 = out_f_roready_815; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_815 = out_wivalid_1_669 & out_wimask_815; // @[RegisterRouter.scala:87:24] wire out_f_woready_815 = out_woready_1_669 & out_womask_815; // @[RegisterRouter.scala:87:24] wire _out_T_8030 = ~out_rimask_815; // @[RegisterRouter.scala:87:24] wire _out_T_8031 = ~out_wimask_815; // @[RegisterRouter.scala:87:24] wire _out_T_8032 = ~out_romask_815; // @[RegisterRouter.scala:87:24] wire _out_T_8033 = ~out_womask_815; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_694 = {hi_733, flags_0_go, _out_prepend_T_694}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8034 = out_prepend_694; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8035 = _out_T_8034; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_695 = _out_T_8035; // @[RegisterRouter.scala:87:24] wire out_rimask_816 = |_out_rimask_T_816; // @[RegisterRouter.scala:87:24] wire out_wimask_816 = &_out_wimask_T_816; // @[RegisterRouter.scala:87:24] wire out_romask_816 = |_out_romask_T_816; // @[RegisterRouter.scala:87:24] wire out_womask_816 = &_out_womask_T_816; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_816 = out_rivalid_1_670 & out_rimask_816; // @[RegisterRouter.scala:87:24] wire _out_T_8037 = out_f_rivalid_816; // @[RegisterRouter.scala:87:24] wire out_f_roready_816 = out_roready_1_670 & out_romask_816; // @[RegisterRouter.scala:87:24] wire _out_T_8038 = out_f_roready_816; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_816 = out_wivalid_1_670 & out_wimask_816; // @[RegisterRouter.scala:87:24] wire out_f_woready_816 = out_woready_1_670 & out_womask_816; // @[RegisterRouter.scala:87:24] wire _out_T_8039 = ~out_rimask_816; // @[RegisterRouter.scala:87:24] wire _out_T_8040 = ~out_wimask_816; // @[RegisterRouter.scala:87:24] wire _out_T_8041 = ~out_romask_816; // @[RegisterRouter.scala:87:24] wire _out_T_8042 = ~out_womask_816; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_695 = {hi_734, flags_0_go, _out_prepend_T_695}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8043 = out_prepend_695; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8044 = _out_T_8043; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_696 = _out_T_8044; // @[RegisterRouter.scala:87:24] wire out_rimask_817 = |_out_rimask_T_817; // @[RegisterRouter.scala:87:24] wire out_wimask_817 = &_out_wimask_T_817; // @[RegisterRouter.scala:87:24] wire out_romask_817 = |_out_romask_T_817; // @[RegisterRouter.scala:87:24] wire out_womask_817 = &_out_womask_T_817; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_817 = out_rivalid_1_671 & out_rimask_817; // @[RegisterRouter.scala:87:24] wire _out_T_8046 = out_f_rivalid_817; // @[RegisterRouter.scala:87:24] wire out_f_roready_817 = out_roready_1_671 & out_romask_817; // @[RegisterRouter.scala:87:24] wire _out_T_8047 = out_f_roready_817; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_817 = out_wivalid_1_671 & out_wimask_817; // @[RegisterRouter.scala:87:24] wire out_f_woready_817 = out_woready_1_671 & out_womask_817; // @[RegisterRouter.scala:87:24] wire _out_T_8048 = ~out_rimask_817; // @[RegisterRouter.scala:87:24] wire _out_T_8049 = ~out_wimask_817; // @[RegisterRouter.scala:87:24] wire _out_T_8050 = ~out_romask_817; // @[RegisterRouter.scala:87:24] wire _out_T_8051 = ~out_womask_817; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_696 = {hi_735, flags_0_go, _out_prepend_T_696}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8052 = out_prepend_696; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8053 = _out_T_8052; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_697 = _out_T_8053; // @[RegisterRouter.scala:87:24] wire out_rimask_818 = |_out_rimask_T_818; // @[RegisterRouter.scala:87:24] wire out_wimask_818 = &_out_wimask_T_818; // @[RegisterRouter.scala:87:24] wire out_romask_818 = |_out_romask_T_818; // @[RegisterRouter.scala:87:24] wire out_womask_818 = &_out_womask_T_818; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_818 = out_rivalid_1_672 & out_rimask_818; // @[RegisterRouter.scala:87:24] wire _out_T_8055 = out_f_rivalid_818; // @[RegisterRouter.scala:87:24] wire out_f_roready_818 = out_roready_1_672 & out_romask_818; // @[RegisterRouter.scala:87:24] wire _out_T_8056 = out_f_roready_818; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_818 = out_wivalid_1_672 & out_wimask_818; // @[RegisterRouter.scala:87:24] wire out_f_woready_818 = out_woready_1_672 & out_womask_818; // @[RegisterRouter.scala:87:24] wire _out_T_8057 = ~out_rimask_818; // @[RegisterRouter.scala:87:24] wire _out_T_8058 = ~out_wimask_818; // @[RegisterRouter.scala:87:24] wire _out_T_8059 = ~out_romask_818; // @[RegisterRouter.scala:87:24] wire _out_T_8060 = ~out_womask_818; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_697 = {hi_736, flags_0_go, _out_prepend_T_697}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8061 = out_prepend_697; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8062 = _out_T_8061; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_219 = _out_T_8062; // @[MuxLiteral.scala:49:48] wire out_rimask_819 = |_out_rimask_T_819; // @[RegisterRouter.scala:87:24] wire out_wimask_819 = &_out_wimask_T_819; // @[RegisterRouter.scala:87:24] wire out_romask_819 = |_out_romask_T_819; // @[RegisterRouter.scala:87:24] wire out_womask_819 = &_out_womask_T_819; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_819 = out_rivalid_1_673 & out_rimask_819; // @[RegisterRouter.scala:87:24] wire _out_T_8064 = out_f_rivalid_819; // @[RegisterRouter.scala:87:24] wire out_f_roready_819 = out_roready_1_673 & out_romask_819; // @[RegisterRouter.scala:87:24] wire _out_T_8065 = out_f_roready_819; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_819 = out_wivalid_1_673 & out_wimask_819; // @[RegisterRouter.scala:87:24] wire out_f_woready_819 = out_woready_1_673 & out_womask_819; // @[RegisterRouter.scala:87:24] wire _out_T_8066 = ~out_rimask_819; // @[RegisterRouter.scala:87:24] wire _out_T_8067 = ~out_wimask_819; // @[RegisterRouter.scala:87:24] wire _out_T_8068 = ~out_romask_819; // @[RegisterRouter.scala:87:24] wire _out_T_8069 = ~out_womask_819; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8071 = _out_T_8070; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_698 = _out_T_8071; // @[RegisterRouter.scala:87:24] wire out_rimask_820 = |_out_rimask_T_820; // @[RegisterRouter.scala:87:24] wire out_wimask_820 = &_out_wimask_T_820; // @[RegisterRouter.scala:87:24] wire out_romask_820 = |_out_romask_T_820; // @[RegisterRouter.scala:87:24] wire out_womask_820 = &_out_womask_T_820; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_820 = out_rivalid_1_674 & out_rimask_820; // @[RegisterRouter.scala:87:24] wire _out_T_8073 = out_f_rivalid_820; // @[RegisterRouter.scala:87:24] wire out_f_roready_820 = out_roready_1_674 & out_romask_820; // @[RegisterRouter.scala:87:24] wire _out_T_8074 = out_f_roready_820; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_820 = out_wivalid_1_674 & out_wimask_820; // @[RegisterRouter.scala:87:24] wire out_f_woready_820 = out_woready_1_674 & out_womask_820; // @[RegisterRouter.scala:87:24] wire _out_T_8075 = ~out_rimask_820; // @[RegisterRouter.scala:87:24] wire _out_T_8076 = ~out_wimask_820; // @[RegisterRouter.scala:87:24] wire _out_T_8077 = ~out_romask_820; // @[RegisterRouter.scala:87:24] wire _out_T_8078 = ~out_womask_820; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_698 = {hi_818, flags_0_go, _out_prepend_T_698}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8079 = out_prepend_698; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8080 = _out_T_8079; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_699 = _out_T_8080; // @[RegisterRouter.scala:87:24] wire out_rimask_821 = |_out_rimask_T_821; // @[RegisterRouter.scala:87:24] wire out_wimask_821 = &_out_wimask_T_821; // @[RegisterRouter.scala:87:24] wire out_romask_821 = |_out_romask_T_821; // @[RegisterRouter.scala:87:24] wire out_womask_821 = &_out_womask_T_821; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_821 = out_rivalid_1_675 & out_rimask_821; // @[RegisterRouter.scala:87:24] wire _out_T_8082 = out_f_rivalid_821; // @[RegisterRouter.scala:87:24] wire out_f_roready_821 = out_roready_1_675 & out_romask_821; // @[RegisterRouter.scala:87:24] wire _out_T_8083 = out_f_roready_821; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_821 = out_wivalid_1_675 & out_wimask_821; // @[RegisterRouter.scala:87:24] wire out_f_woready_821 = out_woready_1_675 & out_womask_821; // @[RegisterRouter.scala:87:24] wire _out_T_8084 = ~out_rimask_821; // @[RegisterRouter.scala:87:24] wire _out_T_8085 = ~out_wimask_821; // @[RegisterRouter.scala:87:24] wire _out_T_8086 = ~out_romask_821; // @[RegisterRouter.scala:87:24] wire _out_T_8087 = ~out_womask_821; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_699 = {hi_819, flags_0_go, _out_prepend_T_699}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8088 = out_prepend_699; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8089 = _out_T_8088; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_700 = _out_T_8089; // @[RegisterRouter.scala:87:24] wire out_rimask_822 = |_out_rimask_T_822; // @[RegisterRouter.scala:87:24] wire out_wimask_822 = &_out_wimask_T_822; // @[RegisterRouter.scala:87:24] wire out_romask_822 = |_out_romask_T_822; // @[RegisterRouter.scala:87:24] wire out_womask_822 = &_out_womask_T_822; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_822 = out_rivalid_1_676 & out_rimask_822; // @[RegisterRouter.scala:87:24] wire _out_T_8091 = out_f_rivalid_822; // @[RegisterRouter.scala:87:24] wire out_f_roready_822 = out_roready_1_676 & out_romask_822; // @[RegisterRouter.scala:87:24] wire _out_T_8092 = out_f_roready_822; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_822 = out_wivalid_1_676 & out_wimask_822; // @[RegisterRouter.scala:87:24] wire out_f_woready_822 = out_woready_1_676 & out_womask_822; // @[RegisterRouter.scala:87:24] wire _out_T_8093 = ~out_rimask_822; // @[RegisterRouter.scala:87:24] wire _out_T_8094 = ~out_wimask_822; // @[RegisterRouter.scala:87:24] wire _out_T_8095 = ~out_romask_822; // @[RegisterRouter.scala:87:24] wire _out_T_8096 = ~out_womask_822; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_700 = {hi_820, flags_0_go, _out_prepend_T_700}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8097 = out_prepend_700; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8098 = _out_T_8097; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_701 = _out_T_8098; // @[RegisterRouter.scala:87:24] wire out_rimask_823 = |_out_rimask_T_823; // @[RegisterRouter.scala:87:24] wire out_wimask_823 = &_out_wimask_T_823; // @[RegisterRouter.scala:87:24] wire out_romask_823 = |_out_romask_T_823; // @[RegisterRouter.scala:87:24] wire out_womask_823 = &_out_womask_T_823; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_823 = out_rivalid_1_677 & out_rimask_823; // @[RegisterRouter.scala:87:24] wire _out_T_8100 = out_f_rivalid_823; // @[RegisterRouter.scala:87:24] wire out_f_roready_823 = out_roready_1_677 & out_romask_823; // @[RegisterRouter.scala:87:24] wire _out_T_8101 = out_f_roready_823; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_823 = out_wivalid_1_677 & out_wimask_823; // @[RegisterRouter.scala:87:24] wire out_f_woready_823 = out_woready_1_677 & out_womask_823; // @[RegisterRouter.scala:87:24] wire _out_T_8102 = ~out_rimask_823; // @[RegisterRouter.scala:87:24] wire _out_T_8103 = ~out_wimask_823; // @[RegisterRouter.scala:87:24] wire _out_T_8104 = ~out_romask_823; // @[RegisterRouter.scala:87:24] wire _out_T_8105 = ~out_womask_823; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_701 = {hi_821, flags_0_go, _out_prepend_T_701}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8106 = out_prepend_701; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8107 = _out_T_8106; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_702 = _out_T_8107; // @[RegisterRouter.scala:87:24] wire out_rimask_824 = |_out_rimask_T_824; // @[RegisterRouter.scala:87:24] wire out_wimask_824 = &_out_wimask_T_824; // @[RegisterRouter.scala:87:24] wire out_romask_824 = |_out_romask_T_824; // @[RegisterRouter.scala:87:24] wire out_womask_824 = &_out_womask_T_824; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_824 = out_rivalid_1_678 & out_rimask_824; // @[RegisterRouter.scala:87:24] wire _out_T_8109 = out_f_rivalid_824; // @[RegisterRouter.scala:87:24] wire out_f_roready_824 = out_roready_1_678 & out_romask_824; // @[RegisterRouter.scala:87:24] wire _out_T_8110 = out_f_roready_824; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_824 = out_wivalid_1_678 & out_wimask_824; // @[RegisterRouter.scala:87:24] wire out_f_woready_824 = out_woready_1_678 & out_womask_824; // @[RegisterRouter.scala:87:24] wire _out_T_8111 = ~out_rimask_824; // @[RegisterRouter.scala:87:24] wire _out_T_8112 = ~out_wimask_824; // @[RegisterRouter.scala:87:24] wire _out_T_8113 = ~out_romask_824; // @[RegisterRouter.scala:87:24] wire _out_T_8114 = ~out_womask_824; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_702 = {hi_822, flags_0_go, _out_prepend_T_702}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8115 = out_prepend_702; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8116 = _out_T_8115; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_703 = _out_T_8116; // @[RegisterRouter.scala:87:24] wire out_rimask_825 = |_out_rimask_T_825; // @[RegisterRouter.scala:87:24] wire out_wimask_825 = &_out_wimask_T_825; // @[RegisterRouter.scala:87:24] wire out_romask_825 = |_out_romask_T_825; // @[RegisterRouter.scala:87:24] wire out_womask_825 = &_out_womask_T_825; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_825 = out_rivalid_1_679 & out_rimask_825; // @[RegisterRouter.scala:87:24] wire _out_T_8118 = out_f_rivalid_825; // @[RegisterRouter.scala:87:24] wire out_f_roready_825 = out_roready_1_679 & out_romask_825; // @[RegisterRouter.scala:87:24] wire _out_T_8119 = out_f_roready_825; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_825 = out_wivalid_1_679 & out_wimask_825; // @[RegisterRouter.scala:87:24] wire out_f_woready_825 = out_woready_1_679 & out_womask_825; // @[RegisterRouter.scala:87:24] wire _out_T_8120 = ~out_rimask_825; // @[RegisterRouter.scala:87:24] wire _out_T_8121 = ~out_wimask_825; // @[RegisterRouter.scala:87:24] wire _out_T_8122 = ~out_romask_825; // @[RegisterRouter.scala:87:24] wire _out_T_8123 = ~out_womask_825; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_703 = {hi_823, flags_0_go, _out_prepend_T_703}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8124 = out_prepend_703; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8125 = _out_T_8124; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_704 = _out_T_8125; // @[RegisterRouter.scala:87:24] wire out_rimask_826 = |_out_rimask_T_826; // @[RegisterRouter.scala:87:24] wire out_wimask_826 = &_out_wimask_T_826; // @[RegisterRouter.scala:87:24] wire out_romask_826 = |_out_romask_T_826; // @[RegisterRouter.scala:87:24] wire out_womask_826 = &_out_womask_T_826; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_826 = out_rivalid_1_680 & out_rimask_826; // @[RegisterRouter.scala:87:24] wire _out_T_8127 = out_f_rivalid_826; // @[RegisterRouter.scala:87:24] wire out_f_roready_826 = out_roready_1_680 & out_romask_826; // @[RegisterRouter.scala:87:24] wire _out_T_8128 = out_f_roready_826; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_826 = out_wivalid_1_680 & out_wimask_826; // @[RegisterRouter.scala:87:24] wire out_f_woready_826 = out_woready_1_680 & out_womask_826; // @[RegisterRouter.scala:87:24] wire _out_T_8129 = ~out_rimask_826; // @[RegisterRouter.scala:87:24] wire _out_T_8130 = ~out_wimask_826; // @[RegisterRouter.scala:87:24] wire _out_T_8131 = ~out_romask_826; // @[RegisterRouter.scala:87:24] wire _out_T_8132 = ~out_womask_826; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_704 = {hi_824, flags_0_go, _out_prepend_T_704}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8133 = out_prepend_704; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8134 = _out_T_8133; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_230 = _out_T_8134; // @[MuxLiteral.scala:49:48] wire out_rimask_827 = |_out_rimask_T_827; // @[RegisterRouter.scala:87:24] wire out_wimask_827 = &_out_wimask_T_827; // @[RegisterRouter.scala:87:24] wire out_romask_827 = |_out_romask_T_827; // @[RegisterRouter.scala:87:24] wire out_womask_827 = &_out_womask_T_827; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_827 = out_rivalid_1_681 & out_rimask_827; // @[RegisterRouter.scala:87:24] wire _out_T_8136 = out_f_rivalid_827; // @[RegisterRouter.scala:87:24] wire out_f_roready_827 = out_roready_1_681 & out_romask_827; // @[RegisterRouter.scala:87:24] wire _out_T_8137 = out_f_roready_827; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_827 = out_wivalid_1_681 & out_wimask_827; // @[RegisterRouter.scala:87:24] wire out_f_woready_827 = out_woready_1_681 & out_womask_827; // @[RegisterRouter.scala:87:24] wire _out_T_8138 = ~out_rimask_827; // @[RegisterRouter.scala:87:24] wire _out_T_8139 = ~out_wimask_827; // @[RegisterRouter.scala:87:24] wire _out_T_8140 = ~out_romask_827; // @[RegisterRouter.scala:87:24] wire _out_T_8141 = ~out_womask_827; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8143 = _out_T_8142; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_705 = _out_T_8143; // @[RegisterRouter.scala:87:24] wire out_rimask_828 = |_out_rimask_T_828; // @[RegisterRouter.scala:87:24] wire out_wimask_828 = &_out_wimask_T_828; // @[RegisterRouter.scala:87:24] wire out_romask_828 = |_out_romask_T_828; // @[RegisterRouter.scala:87:24] wire out_womask_828 = &_out_womask_T_828; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_828 = out_rivalid_1_682 & out_rimask_828; // @[RegisterRouter.scala:87:24] wire _out_T_8145 = out_f_rivalid_828; // @[RegisterRouter.scala:87:24] wire out_f_roready_828 = out_roready_1_682 & out_romask_828; // @[RegisterRouter.scala:87:24] wire _out_T_8146 = out_f_roready_828; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_828 = out_wivalid_1_682 & out_wimask_828; // @[RegisterRouter.scala:87:24] wire out_f_woready_828 = out_woready_1_682 & out_womask_828; // @[RegisterRouter.scala:87:24] wire _out_T_8147 = ~out_rimask_828; // @[RegisterRouter.scala:87:24] wire _out_T_8148 = ~out_wimask_828; // @[RegisterRouter.scala:87:24] wire _out_T_8149 = ~out_romask_828; // @[RegisterRouter.scala:87:24] wire _out_T_8150 = ~out_womask_828; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_705 = {hi_938, flags_0_go, _out_prepend_T_705}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8151 = out_prepend_705; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8152 = _out_T_8151; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_706 = _out_T_8152; // @[RegisterRouter.scala:87:24] wire out_rimask_829 = |_out_rimask_T_829; // @[RegisterRouter.scala:87:24] wire out_wimask_829 = &_out_wimask_T_829; // @[RegisterRouter.scala:87:24] wire out_romask_829 = |_out_romask_T_829; // @[RegisterRouter.scala:87:24] wire out_womask_829 = &_out_womask_T_829; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_829 = out_rivalid_1_683 & out_rimask_829; // @[RegisterRouter.scala:87:24] wire _out_T_8154 = out_f_rivalid_829; // @[RegisterRouter.scala:87:24] wire out_f_roready_829 = out_roready_1_683 & out_romask_829; // @[RegisterRouter.scala:87:24] wire _out_T_8155 = out_f_roready_829; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_829 = out_wivalid_1_683 & out_wimask_829; // @[RegisterRouter.scala:87:24] wire out_f_woready_829 = out_woready_1_683 & out_womask_829; // @[RegisterRouter.scala:87:24] wire _out_T_8156 = ~out_rimask_829; // @[RegisterRouter.scala:87:24] wire _out_T_8157 = ~out_wimask_829; // @[RegisterRouter.scala:87:24] wire _out_T_8158 = ~out_romask_829; // @[RegisterRouter.scala:87:24] wire _out_T_8159 = ~out_womask_829; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_706 = {hi_939, flags_0_go, _out_prepend_T_706}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8160 = out_prepend_706; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8161 = _out_T_8160; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_707 = _out_T_8161; // @[RegisterRouter.scala:87:24] wire out_rimask_830 = |_out_rimask_T_830; // @[RegisterRouter.scala:87:24] wire out_wimask_830 = &_out_wimask_T_830; // @[RegisterRouter.scala:87:24] wire out_romask_830 = |_out_romask_T_830; // @[RegisterRouter.scala:87:24] wire out_womask_830 = &_out_womask_T_830; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_830 = out_rivalid_1_684 & out_rimask_830; // @[RegisterRouter.scala:87:24] wire _out_T_8163 = out_f_rivalid_830; // @[RegisterRouter.scala:87:24] wire out_f_roready_830 = out_roready_1_684 & out_romask_830; // @[RegisterRouter.scala:87:24] wire _out_T_8164 = out_f_roready_830; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_830 = out_wivalid_1_684 & out_wimask_830; // @[RegisterRouter.scala:87:24] wire out_f_woready_830 = out_woready_1_684 & out_womask_830; // @[RegisterRouter.scala:87:24] wire _out_T_8165 = ~out_rimask_830; // @[RegisterRouter.scala:87:24] wire _out_T_8166 = ~out_wimask_830; // @[RegisterRouter.scala:87:24] wire _out_T_8167 = ~out_romask_830; // @[RegisterRouter.scala:87:24] wire _out_T_8168 = ~out_womask_830; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_707 = {hi_940, flags_0_go, _out_prepend_T_707}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8169 = out_prepend_707; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8170 = _out_T_8169; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_708 = _out_T_8170; // @[RegisterRouter.scala:87:24] wire out_rimask_831 = |_out_rimask_T_831; // @[RegisterRouter.scala:87:24] wire out_wimask_831 = &_out_wimask_T_831; // @[RegisterRouter.scala:87:24] wire out_romask_831 = |_out_romask_T_831; // @[RegisterRouter.scala:87:24] wire out_womask_831 = &_out_womask_T_831; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_831 = out_rivalid_1_685 & out_rimask_831; // @[RegisterRouter.scala:87:24] wire _out_T_8172 = out_f_rivalid_831; // @[RegisterRouter.scala:87:24] wire out_f_roready_831 = out_roready_1_685 & out_romask_831; // @[RegisterRouter.scala:87:24] wire _out_T_8173 = out_f_roready_831; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_831 = out_wivalid_1_685 & out_wimask_831; // @[RegisterRouter.scala:87:24] wire out_f_woready_831 = out_woready_1_685 & out_womask_831; // @[RegisterRouter.scala:87:24] wire _out_T_8174 = ~out_rimask_831; // @[RegisterRouter.scala:87:24] wire _out_T_8175 = ~out_wimask_831; // @[RegisterRouter.scala:87:24] wire _out_T_8176 = ~out_romask_831; // @[RegisterRouter.scala:87:24] wire _out_T_8177 = ~out_womask_831; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_708 = {hi_941, flags_0_go, _out_prepend_T_708}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8178 = out_prepend_708; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8179 = _out_T_8178; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_709 = _out_T_8179; // @[RegisterRouter.scala:87:24] wire out_rimask_832 = |_out_rimask_T_832; // @[RegisterRouter.scala:87:24] wire out_wimask_832 = &_out_wimask_T_832; // @[RegisterRouter.scala:87:24] wire out_romask_832 = |_out_romask_T_832; // @[RegisterRouter.scala:87:24] wire out_womask_832 = &_out_womask_T_832; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_832 = out_rivalid_1_686 & out_rimask_832; // @[RegisterRouter.scala:87:24] wire _out_T_8181 = out_f_rivalid_832; // @[RegisterRouter.scala:87:24] wire out_f_roready_832 = out_roready_1_686 & out_romask_832; // @[RegisterRouter.scala:87:24] wire _out_T_8182 = out_f_roready_832; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_832 = out_wivalid_1_686 & out_wimask_832; // @[RegisterRouter.scala:87:24] wire out_f_woready_832 = out_woready_1_686 & out_womask_832; // @[RegisterRouter.scala:87:24] wire _out_T_8183 = ~out_rimask_832; // @[RegisterRouter.scala:87:24] wire _out_T_8184 = ~out_wimask_832; // @[RegisterRouter.scala:87:24] wire _out_T_8185 = ~out_romask_832; // @[RegisterRouter.scala:87:24] wire _out_T_8186 = ~out_womask_832; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_709 = {hi_942, flags_0_go, _out_prepend_T_709}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8187 = out_prepend_709; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8188 = _out_T_8187; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_710 = _out_T_8188; // @[RegisterRouter.scala:87:24] wire out_rimask_833 = |_out_rimask_T_833; // @[RegisterRouter.scala:87:24] wire out_wimask_833 = &_out_wimask_T_833; // @[RegisterRouter.scala:87:24] wire out_romask_833 = |_out_romask_T_833; // @[RegisterRouter.scala:87:24] wire out_womask_833 = &_out_womask_T_833; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_833 = out_rivalid_1_687 & out_rimask_833; // @[RegisterRouter.scala:87:24] wire _out_T_8190 = out_f_rivalid_833; // @[RegisterRouter.scala:87:24] wire out_f_roready_833 = out_roready_1_687 & out_romask_833; // @[RegisterRouter.scala:87:24] wire _out_T_8191 = out_f_roready_833; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_833 = out_wivalid_1_687 & out_wimask_833; // @[RegisterRouter.scala:87:24] wire out_f_woready_833 = out_woready_1_687 & out_womask_833; // @[RegisterRouter.scala:87:24] wire _out_T_8192 = ~out_rimask_833; // @[RegisterRouter.scala:87:24] wire _out_T_8193 = ~out_wimask_833; // @[RegisterRouter.scala:87:24] wire _out_T_8194 = ~out_romask_833; // @[RegisterRouter.scala:87:24] wire _out_T_8195 = ~out_womask_833; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_710 = {hi_943, flags_0_go, _out_prepend_T_710}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8196 = out_prepend_710; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8197 = _out_T_8196; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_711 = _out_T_8197; // @[RegisterRouter.scala:87:24] wire out_rimask_834 = |_out_rimask_T_834; // @[RegisterRouter.scala:87:24] wire out_wimask_834 = &_out_wimask_T_834; // @[RegisterRouter.scala:87:24] wire out_romask_834 = |_out_romask_T_834; // @[RegisterRouter.scala:87:24] wire out_womask_834 = &_out_womask_T_834; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_834 = out_rivalid_1_688 & out_rimask_834; // @[RegisterRouter.scala:87:24] wire _out_T_8199 = out_f_rivalid_834; // @[RegisterRouter.scala:87:24] wire out_f_roready_834 = out_roready_1_688 & out_romask_834; // @[RegisterRouter.scala:87:24] wire _out_T_8200 = out_f_roready_834; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_834 = out_wivalid_1_688 & out_wimask_834; // @[RegisterRouter.scala:87:24] wire out_f_woready_834 = out_woready_1_688 & out_womask_834; // @[RegisterRouter.scala:87:24] wire _out_T_8201 = ~out_rimask_834; // @[RegisterRouter.scala:87:24] wire _out_T_8202 = ~out_wimask_834; // @[RegisterRouter.scala:87:24] wire _out_T_8203 = ~out_romask_834; // @[RegisterRouter.scala:87:24] wire _out_T_8204 = ~out_womask_834; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_711 = {hi_944, flags_0_go, _out_prepend_T_711}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8205 = out_prepend_711; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8206 = _out_T_8205; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_245 = _out_T_8206; // @[MuxLiteral.scala:49:48] wire out_rimask_835 = |_out_rimask_T_835; // @[RegisterRouter.scala:87:24] wire out_wimask_835 = &_out_wimask_T_835; // @[RegisterRouter.scala:87:24] wire out_romask_835 = |_out_romask_T_835; // @[RegisterRouter.scala:87:24] wire out_womask_835 = &_out_womask_T_835; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_835 = out_rivalid_1_689 & out_rimask_835; // @[RegisterRouter.scala:87:24] wire _out_T_8208 = out_f_rivalid_835; // @[RegisterRouter.scala:87:24] wire out_f_roready_835 = out_roready_1_689 & out_romask_835; // @[RegisterRouter.scala:87:24] wire _out_T_8209 = out_f_roready_835; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_835 = out_wivalid_1_689 & out_wimask_835; // @[RegisterRouter.scala:87:24] wire out_f_woready_835 = out_woready_1_689 & out_womask_835; // @[RegisterRouter.scala:87:24] wire _out_T_8210 = ~out_rimask_835; // @[RegisterRouter.scala:87:24] wire _out_T_8211 = ~out_wimask_835; // @[RegisterRouter.scala:87:24] wire _out_T_8212 = ~out_romask_835; // @[RegisterRouter.scala:87:24] wire _out_T_8213 = ~out_womask_835; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8215 = _out_T_8214; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_712 = _out_T_8215; // @[RegisterRouter.scala:87:24] wire out_rimask_836 = |_out_rimask_T_836; // @[RegisterRouter.scala:87:24] wire out_wimask_836 = &_out_wimask_T_836; // @[RegisterRouter.scala:87:24] wire out_romask_836 = |_out_romask_T_836; // @[RegisterRouter.scala:87:24] wire out_womask_836 = &_out_womask_T_836; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_836 = out_rivalid_1_690 & out_rimask_836; // @[RegisterRouter.scala:87:24] wire _out_T_8217 = out_f_rivalid_836; // @[RegisterRouter.scala:87:24] wire out_f_roready_836 = out_roready_1_690 & out_romask_836; // @[RegisterRouter.scala:87:24] wire _out_T_8218 = out_f_roready_836; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_836 = out_wivalid_1_690 & out_wimask_836; // @[RegisterRouter.scala:87:24] wire out_f_woready_836 = out_woready_1_690 & out_womask_836; // @[RegisterRouter.scala:87:24] wire _out_T_8219 = ~out_rimask_836; // @[RegisterRouter.scala:87:24] wire _out_T_8220 = ~out_wimask_836; // @[RegisterRouter.scala:87:24] wire _out_T_8221 = ~out_romask_836; // @[RegisterRouter.scala:87:24] wire _out_T_8222 = ~out_womask_836; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_712 = {hi_642, flags_0_go, _out_prepend_T_712}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8223 = out_prepend_712; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8224 = _out_T_8223; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_713 = _out_T_8224; // @[RegisterRouter.scala:87:24] wire out_rimask_837 = |_out_rimask_T_837; // @[RegisterRouter.scala:87:24] wire out_wimask_837 = &_out_wimask_T_837; // @[RegisterRouter.scala:87:24] wire out_romask_837 = |_out_romask_T_837; // @[RegisterRouter.scala:87:24] wire out_womask_837 = &_out_womask_T_837; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_837 = out_rivalid_1_691 & out_rimask_837; // @[RegisterRouter.scala:87:24] wire _out_T_8226 = out_f_rivalid_837; // @[RegisterRouter.scala:87:24] wire out_f_roready_837 = out_roready_1_691 & out_romask_837; // @[RegisterRouter.scala:87:24] wire _out_T_8227 = out_f_roready_837; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_837 = out_wivalid_1_691 & out_wimask_837; // @[RegisterRouter.scala:87:24] wire out_f_woready_837 = out_woready_1_691 & out_womask_837; // @[RegisterRouter.scala:87:24] wire _out_T_8228 = ~out_rimask_837; // @[RegisterRouter.scala:87:24] wire _out_T_8229 = ~out_wimask_837; // @[RegisterRouter.scala:87:24] wire _out_T_8230 = ~out_romask_837; // @[RegisterRouter.scala:87:24] wire _out_T_8231 = ~out_womask_837; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_713 = {hi_643, flags_0_go, _out_prepend_T_713}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8232 = out_prepend_713; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8233 = _out_T_8232; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_714 = _out_T_8233; // @[RegisterRouter.scala:87:24] wire out_rimask_838 = |_out_rimask_T_838; // @[RegisterRouter.scala:87:24] wire out_wimask_838 = &_out_wimask_T_838; // @[RegisterRouter.scala:87:24] wire out_romask_838 = |_out_romask_T_838; // @[RegisterRouter.scala:87:24] wire out_womask_838 = &_out_womask_T_838; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_838 = out_rivalid_1_692 & out_rimask_838; // @[RegisterRouter.scala:87:24] wire _out_T_8235 = out_f_rivalid_838; // @[RegisterRouter.scala:87:24] wire out_f_roready_838 = out_roready_1_692 & out_romask_838; // @[RegisterRouter.scala:87:24] wire _out_T_8236 = out_f_roready_838; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_838 = out_wivalid_1_692 & out_wimask_838; // @[RegisterRouter.scala:87:24] wire out_f_woready_838 = out_woready_1_692 & out_womask_838; // @[RegisterRouter.scala:87:24] wire _out_T_8237 = ~out_rimask_838; // @[RegisterRouter.scala:87:24] wire _out_T_8238 = ~out_wimask_838; // @[RegisterRouter.scala:87:24] wire _out_T_8239 = ~out_romask_838; // @[RegisterRouter.scala:87:24] wire _out_T_8240 = ~out_womask_838; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_714 = {hi_644, flags_0_go, _out_prepend_T_714}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8241 = out_prepend_714; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8242 = _out_T_8241; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_715 = _out_T_8242; // @[RegisterRouter.scala:87:24] wire out_rimask_839 = |_out_rimask_T_839; // @[RegisterRouter.scala:87:24] wire out_wimask_839 = &_out_wimask_T_839; // @[RegisterRouter.scala:87:24] wire out_romask_839 = |_out_romask_T_839; // @[RegisterRouter.scala:87:24] wire out_womask_839 = &_out_womask_T_839; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_839 = out_rivalid_1_693 & out_rimask_839; // @[RegisterRouter.scala:87:24] wire _out_T_8244 = out_f_rivalid_839; // @[RegisterRouter.scala:87:24] wire out_f_roready_839 = out_roready_1_693 & out_romask_839; // @[RegisterRouter.scala:87:24] wire _out_T_8245 = out_f_roready_839; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_839 = out_wivalid_1_693 & out_wimask_839; // @[RegisterRouter.scala:87:24] wire out_f_woready_839 = out_woready_1_693 & out_womask_839; // @[RegisterRouter.scala:87:24] wire _out_T_8246 = ~out_rimask_839; // @[RegisterRouter.scala:87:24] wire _out_T_8247 = ~out_wimask_839; // @[RegisterRouter.scala:87:24] wire _out_T_8248 = ~out_romask_839; // @[RegisterRouter.scala:87:24] wire _out_T_8249 = ~out_womask_839; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_715 = {hi_645, flags_0_go, _out_prepend_T_715}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8250 = out_prepend_715; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8251 = _out_T_8250; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_716 = _out_T_8251; // @[RegisterRouter.scala:87:24] wire out_rimask_840 = |_out_rimask_T_840; // @[RegisterRouter.scala:87:24] wire out_wimask_840 = &_out_wimask_T_840; // @[RegisterRouter.scala:87:24] wire out_romask_840 = |_out_romask_T_840; // @[RegisterRouter.scala:87:24] wire out_womask_840 = &_out_womask_T_840; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_840 = out_rivalid_1_694 & out_rimask_840; // @[RegisterRouter.scala:87:24] wire _out_T_8253 = out_f_rivalid_840; // @[RegisterRouter.scala:87:24] wire out_f_roready_840 = out_roready_1_694 & out_romask_840; // @[RegisterRouter.scala:87:24] wire _out_T_8254 = out_f_roready_840; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_840 = out_wivalid_1_694 & out_wimask_840; // @[RegisterRouter.scala:87:24] wire out_f_woready_840 = out_woready_1_694 & out_womask_840; // @[RegisterRouter.scala:87:24] wire _out_T_8255 = ~out_rimask_840; // @[RegisterRouter.scala:87:24] wire _out_T_8256 = ~out_wimask_840; // @[RegisterRouter.scala:87:24] wire _out_T_8257 = ~out_romask_840; // @[RegisterRouter.scala:87:24] wire _out_T_8258 = ~out_womask_840; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_716 = {hi_646, flags_0_go, _out_prepend_T_716}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8259 = out_prepend_716; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8260 = _out_T_8259; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_717 = _out_T_8260; // @[RegisterRouter.scala:87:24] wire out_rimask_841 = |_out_rimask_T_841; // @[RegisterRouter.scala:87:24] wire out_wimask_841 = &_out_wimask_T_841; // @[RegisterRouter.scala:87:24] wire out_romask_841 = |_out_romask_T_841; // @[RegisterRouter.scala:87:24] wire out_womask_841 = &_out_womask_T_841; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_841 = out_rivalid_1_695 & out_rimask_841; // @[RegisterRouter.scala:87:24] wire _out_T_8262 = out_f_rivalid_841; // @[RegisterRouter.scala:87:24] wire out_f_roready_841 = out_roready_1_695 & out_romask_841; // @[RegisterRouter.scala:87:24] wire _out_T_8263 = out_f_roready_841; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_841 = out_wivalid_1_695 & out_wimask_841; // @[RegisterRouter.scala:87:24] wire out_f_woready_841 = out_woready_1_695 & out_womask_841; // @[RegisterRouter.scala:87:24] wire _out_T_8264 = ~out_rimask_841; // @[RegisterRouter.scala:87:24] wire _out_T_8265 = ~out_wimask_841; // @[RegisterRouter.scala:87:24] wire _out_T_8266 = ~out_romask_841; // @[RegisterRouter.scala:87:24] wire _out_T_8267 = ~out_womask_841; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_717 = {hi_647, flags_0_go, _out_prepend_T_717}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8268 = out_prepend_717; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8269 = _out_T_8268; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_718 = _out_T_8269; // @[RegisterRouter.scala:87:24] wire out_rimask_842 = |_out_rimask_T_842; // @[RegisterRouter.scala:87:24] wire out_wimask_842 = &_out_wimask_T_842; // @[RegisterRouter.scala:87:24] wire out_romask_842 = |_out_romask_T_842; // @[RegisterRouter.scala:87:24] wire out_womask_842 = &_out_womask_T_842; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_842 = out_rivalid_1_696 & out_rimask_842; // @[RegisterRouter.scala:87:24] wire _out_T_8271 = out_f_rivalid_842; // @[RegisterRouter.scala:87:24] wire out_f_roready_842 = out_roready_1_696 & out_romask_842; // @[RegisterRouter.scala:87:24] wire _out_T_8272 = out_f_roready_842; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_842 = out_wivalid_1_696 & out_wimask_842; // @[RegisterRouter.scala:87:24] wire out_f_woready_842 = out_woready_1_696 & out_womask_842; // @[RegisterRouter.scala:87:24] wire _out_T_8273 = ~out_rimask_842; // @[RegisterRouter.scala:87:24] wire _out_T_8274 = ~out_wimask_842; // @[RegisterRouter.scala:87:24] wire _out_T_8275 = ~out_romask_842; // @[RegisterRouter.scala:87:24] wire _out_T_8276 = ~out_womask_842; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_718 = {hi_648, flags_0_go, _out_prepend_T_718}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8277 = out_prepend_718; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8278 = _out_T_8277; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_208 = _out_T_8278; // @[MuxLiteral.scala:49:48] wire out_rimask_843 = |_out_rimask_T_843; // @[RegisterRouter.scala:87:24] wire out_wimask_843 = &_out_wimask_T_843; // @[RegisterRouter.scala:87:24] wire out_romask_843 = |_out_romask_T_843; // @[RegisterRouter.scala:87:24] wire out_womask_843 = &_out_womask_T_843; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_843 = out_rivalid_1_697 & out_rimask_843; // @[RegisterRouter.scala:87:24] wire _out_T_8280 = out_f_rivalid_843; // @[RegisterRouter.scala:87:24] wire out_f_roready_843 = out_roready_1_697 & out_romask_843; // @[RegisterRouter.scala:87:24] wire _out_T_8281 = out_f_roready_843; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_843 = out_wivalid_1_697 & out_wimask_843; // @[RegisterRouter.scala:87:24] wire out_f_woready_843 = out_woready_1_697 & out_womask_843; // @[RegisterRouter.scala:87:24] wire _out_T_8282 = ~out_rimask_843; // @[RegisterRouter.scala:87:24] wire _out_T_8283 = ~out_wimask_843; // @[RegisterRouter.scala:87:24] wire _out_T_8284 = ~out_romask_843; // @[RegisterRouter.scala:87:24] wire _out_T_8285 = ~out_womask_843; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8287 = _out_T_8286; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_719 = _out_T_8287; // @[RegisterRouter.scala:87:24] wire [31:0] _out_rimask_T_844 = out_frontMask_1[63:32]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_wimask_T_844 = out_frontMask_1[63:32]; // @[RegisterRouter.scala:87:24] wire out_rimask_844 = |_out_rimask_T_844; // @[RegisterRouter.scala:87:24] wire out_wimask_844 = &_out_wimask_T_844; // @[RegisterRouter.scala:87:24] wire [31:0] _out_romask_T_844 = out_backMask_1[63:32]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_womask_T_844 = out_backMask_1[63:32]; // @[RegisterRouter.scala:87:24] wire out_romask_844 = |_out_romask_T_844; // @[RegisterRouter.scala:87:24] wire out_womask_844 = &_out_womask_T_844; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_844 = out_rivalid_1_698 & out_rimask_844; // @[RegisterRouter.scala:87:24] wire _out_T_8289 = out_f_rivalid_844; // @[RegisterRouter.scala:87:24] wire out_f_roready_844 = out_roready_1_698 & out_romask_844; // @[RegisterRouter.scala:87:24] wire _out_T_8290 = out_f_roready_844; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_844 = out_wivalid_1_698 & out_wimask_844; // @[RegisterRouter.scala:87:24] wire out_f_woready_844 = out_woready_1_698 & out_womask_844; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8288 = out_front_1_bits_data[63:32]; // @[RegisterRouter.scala:87:24] wire _out_T_8291 = ~out_rimask_844; // @[RegisterRouter.scala:87:24] wire _out_T_8292 = ~out_wimask_844; // @[RegisterRouter.scala:87:24] wire _out_T_8293 = ~out_romask_844; // @[RegisterRouter.scala:87:24] wire _out_T_8294 = ~out_womask_844; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_719 = {abstractGeneratedMem_1, _out_prepend_T_719}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8295 = out_prepend_719; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8296 = _out_T_8295; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_103 = _out_T_8296; // @[MuxLiteral.scala:49:48] wire out_rimask_845 = |_out_rimask_T_845; // @[RegisterRouter.scala:87:24] wire out_wimask_845 = &_out_wimask_T_845; // @[RegisterRouter.scala:87:24] wire out_romask_845 = |_out_romask_T_845; // @[RegisterRouter.scala:87:24] wire out_womask_845 = &_out_womask_T_845; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_845 = out_rivalid_1_699 & out_rimask_845; // @[RegisterRouter.scala:87:24] wire _out_T_8298 = out_f_rivalid_845; // @[RegisterRouter.scala:87:24] wire out_f_roready_845 = out_roready_1_699 & out_romask_845; // @[RegisterRouter.scala:87:24] wire _out_T_8299 = out_f_roready_845; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_845 = out_wivalid_1_699 & out_wimask_845; // @[RegisterRouter.scala:87:24] wire out_f_woready_845 = out_woready_1_699 & out_womask_845; // @[RegisterRouter.scala:87:24] wire _out_T_8300 = ~out_rimask_845; // @[RegisterRouter.scala:87:24] wire _out_T_8301 = ~out_wimask_845; // @[RegisterRouter.scala:87:24] wire _out_T_8302 = ~out_romask_845; // @[RegisterRouter.scala:87:24] wire _out_T_8303 = ~out_womask_845; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8305 = _out_T_8304; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_720 = _out_T_8305; // @[RegisterRouter.scala:87:24] wire out_rimask_846 = |_out_rimask_T_846; // @[RegisterRouter.scala:87:24] wire out_wimask_846 = &_out_wimask_T_846; // @[RegisterRouter.scala:87:24] wire out_romask_846 = |_out_romask_T_846; // @[RegisterRouter.scala:87:24] wire out_womask_846 = &_out_womask_T_846; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_846 = out_rivalid_1_700 & out_rimask_846; // @[RegisterRouter.scala:87:24] wire _out_T_8307 = out_f_rivalid_846; // @[RegisterRouter.scala:87:24] wire out_f_roready_846 = out_roready_1_700 & out_romask_846; // @[RegisterRouter.scala:87:24] wire _out_T_8308 = out_f_roready_846; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_846 = out_wivalid_1_700 & out_wimask_846; // @[RegisterRouter.scala:87:24] wire out_f_woready_846 = out_woready_1_700 & out_womask_846; // @[RegisterRouter.scala:87:24] wire _out_T_8309 = ~out_rimask_846; // @[RegisterRouter.scala:87:24] wire _out_T_8310 = ~out_wimask_846; // @[RegisterRouter.scala:87:24] wire _out_T_8311 = ~out_romask_846; // @[RegisterRouter.scala:87:24] wire _out_T_8312 = ~out_womask_846; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_720 = {hi_98, flags_0_go, _out_prepend_T_720}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8313 = out_prepend_720; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8314 = _out_T_8313; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_721 = _out_T_8314; // @[RegisterRouter.scala:87:24] wire out_rimask_847 = |_out_rimask_T_847; // @[RegisterRouter.scala:87:24] wire out_wimask_847 = &_out_wimask_T_847; // @[RegisterRouter.scala:87:24] wire out_romask_847 = |_out_romask_T_847; // @[RegisterRouter.scala:87:24] wire out_womask_847 = &_out_womask_T_847; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_847 = out_rivalid_1_701 & out_rimask_847; // @[RegisterRouter.scala:87:24] wire _out_T_8316 = out_f_rivalid_847; // @[RegisterRouter.scala:87:24] wire out_f_roready_847 = out_roready_1_701 & out_romask_847; // @[RegisterRouter.scala:87:24] wire _out_T_8317 = out_f_roready_847; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_847 = out_wivalid_1_701 & out_wimask_847; // @[RegisterRouter.scala:87:24] wire out_f_woready_847 = out_woready_1_701 & out_womask_847; // @[RegisterRouter.scala:87:24] wire _out_T_8318 = ~out_rimask_847; // @[RegisterRouter.scala:87:24] wire _out_T_8319 = ~out_wimask_847; // @[RegisterRouter.scala:87:24] wire _out_T_8320 = ~out_romask_847; // @[RegisterRouter.scala:87:24] wire _out_T_8321 = ~out_womask_847; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_721 = {hi_99, flags_0_go, _out_prepend_T_721}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8322 = out_prepend_721; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8323 = _out_T_8322; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_722 = _out_T_8323; // @[RegisterRouter.scala:87:24] wire out_rimask_848 = |_out_rimask_T_848; // @[RegisterRouter.scala:87:24] wire out_wimask_848 = &_out_wimask_T_848; // @[RegisterRouter.scala:87:24] wire out_romask_848 = |_out_romask_T_848; // @[RegisterRouter.scala:87:24] wire out_womask_848 = &_out_womask_T_848; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_848 = out_rivalid_1_702 & out_rimask_848; // @[RegisterRouter.scala:87:24] wire _out_T_8325 = out_f_rivalid_848; // @[RegisterRouter.scala:87:24] wire out_f_roready_848 = out_roready_1_702 & out_romask_848; // @[RegisterRouter.scala:87:24] wire _out_T_8326 = out_f_roready_848; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_848 = out_wivalid_1_702 & out_wimask_848; // @[RegisterRouter.scala:87:24] wire out_f_woready_848 = out_woready_1_702 & out_womask_848; // @[RegisterRouter.scala:87:24] wire _out_T_8327 = ~out_rimask_848; // @[RegisterRouter.scala:87:24] wire _out_T_8328 = ~out_wimask_848; // @[RegisterRouter.scala:87:24] wire _out_T_8329 = ~out_romask_848; // @[RegisterRouter.scala:87:24] wire _out_T_8330 = ~out_womask_848; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_722 = {hi_100, flags_0_go, _out_prepend_T_722}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8331 = out_prepend_722; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8332 = _out_T_8331; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_723 = _out_T_8332; // @[RegisterRouter.scala:87:24] wire out_rimask_849 = |_out_rimask_T_849; // @[RegisterRouter.scala:87:24] wire out_wimask_849 = &_out_wimask_T_849; // @[RegisterRouter.scala:87:24] wire out_romask_849 = |_out_romask_T_849; // @[RegisterRouter.scala:87:24] wire out_womask_849 = &_out_womask_T_849; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_849 = out_rivalid_1_703 & out_rimask_849; // @[RegisterRouter.scala:87:24] wire _out_T_8334 = out_f_rivalid_849; // @[RegisterRouter.scala:87:24] wire out_f_roready_849 = out_roready_1_703 & out_romask_849; // @[RegisterRouter.scala:87:24] wire _out_T_8335 = out_f_roready_849; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_849 = out_wivalid_1_703 & out_wimask_849; // @[RegisterRouter.scala:87:24] wire out_f_woready_849 = out_woready_1_703 & out_womask_849; // @[RegisterRouter.scala:87:24] wire _out_T_8336 = ~out_rimask_849; // @[RegisterRouter.scala:87:24] wire _out_T_8337 = ~out_wimask_849; // @[RegisterRouter.scala:87:24] wire _out_T_8338 = ~out_romask_849; // @[RegisterRouter.scala:87:24] wire _out_T_8339 = ~out_womask_849; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_723 = {hi_101, flags_0_go, _out_prepend_T_723}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8340 = out_prepend_723; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8341 = _out_T_8340; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_724 = _out_T_8341; // @[RegisterRouter.scala:87:24] wire out_rimask_850 = |_out_rimask_T_850; // @[RegisterRouter.scala:87:24] wire out_wimask_850 = &_out_wimask_T_850; // @[RegisterRouter.scala:87:24] wire out_romask_850 = |_out_romask_T_850; // @[RegisterRouter.scala:87:24] wire out_womask_850 = &_out_womask_T_850; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_850 = out_rivalid_1_704 & out_rimask_850; // @[RegisterRouter.scala:87:24] wire _out_T_8343 = out_f_rivalid_850; // @[RegisterRouter.scala:87:24] wire out_f_roready_850 = out_roready_1_704 & out_romask_850; // @[RegisterRouter.scala:87:24] wire _out_T_8344 = out_f_roready_850; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_850 = out_wivalid_1_704 & out_wimask_850; // @[RegisterRouter.scala:87:24] wire out_f_woready_850 = out_woready_1_704 & out_womask_850; // @[RegisterRouter.scala:87:24] wire _out_T_8345 = ~out_rimask_850; // @[RegisterRouter.scala:87:24] wire _out_T_8346 = ~out_wimask_850; // @[RegisterRouter.scala:87:24] wire _out_T_8347 = ~out_romask_850; // @[RegisterRouter.scala:87:24] wire _out_T_8348 = ~out_womask_850; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_724 = {hi_102, flags_0_go, _out_prepend_T_724}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8349 = out_prepend_724; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8350 = _out_T_8349; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_725 = _out_T_8350; // @[RegisterRouter.scala:87:24] wire out_rimask_851 = |_out_rimask_T_851; // @[RegisterRouter.scala:87:24] wire out_wimask_851 = &_out_wimask_T_851; // @[RegisterRouter.scala:87:24] wire out_romask_851 = |_out_romask_T_851; // @[RegisterRouter.scala:87:24] wire out_womask_851 = &_out_womask_T_851; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_851 = out_rivalid_1_705 & out_rimask_851; // @[RegisterRouter.scala:87:24] wire _out_T_8352 = out_f_rivalid_851; // @[RegisterRouter.scala:87:24] wire out_f_roready_851 = out_roready_1_705 & out_romask_851; // @[RegisterRouter.scala:87:24] wire _out_T_8353 = out_f_roready_851; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_851 = out_wivalid_1_705 & out_wimask_851; // @[RegisterRouter.scala:87:24] wire out_f_woready_851 = out_woready_1_705 & out_womask_851; // @[RegisterRouter.scala:87:24] wire _out_T_8354 = ~out_rimask_851; // @[RegisterRouter.scala:87:24] wire _out_T_8355 = ~out_wimask_851; // @[RegisterRouter.scala:87:24] wire _out_T_8356 = ~out_romask_851; // @[RegisterRouter.scala:87:24] wire _out_T_8357 = ~out_womask_851; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_725 = {hi_103, flags_0_go, _out_prepend_T_725}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8358 = out_prepend_725; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8359 = _out_T_8358; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_726 = _out_T_8359; // @[RegisterRouter.scala:87:24] wire out_rimask_852 = |_out_rimask_T_852; // @[RegisterRouter.scala:87:24] wire out_wimask_852 = &_out_wimask_T_852; // @[RegisterRouter.scala:87:24] wire out_romask_852 = |_out_romask_T_852; // @[RegisterRouter.scala:87:24] wire out_womask_852 = &_out_womask_T_852; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_852 = out_rivalid_1_706 & out_rimask_852; // @[RegisterRouter.scala:87:24] wire _out_T_8361 = out_f_rivalid_852; // @[RegisterRouter.scala:87:24] wire out_f_roready_852 = out_roready_1_706 & out_romask_852; // @[RegisterRouter.scala:87:24] wire _out_T_8362 = out_f_roready_852; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_852 = out_wivalid_1_706 & out_wimask_852; // @[RegisterRouter.scala:87:24] wire out_f_woready_852 = out_woready_1_706 & out_womask_852; // @[RegisterRouter.scala:87:24] wire _out_T_8363 = ~out_rimask_852; // @[RegisterRouter.scala:87:24] wire _out_T_8364 = ~out_wimask_852; // @[RegisterRouter.scala:87:24] wire _out_T_8365 = ~out_romask_852; // @[RegisterRouter.scala:87:24] wire _out_T_8366 = ~out_womask_852; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_726 = {hi_104, flags_0_go, _out_prepend_T_726}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8367 = out_prepend_726; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8368 = _out_T_8367; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_140 = _out_T_8368; // @[MuxLiteral.scala:49:48] wire out_rimask_853 = |_out_rimask_T_853; // @[RegisterRouter.scala:87:24] wire out_wimask_853 = &_out_wimask_T_853; // @[RegisterRouter.scala:87:24] wire out_romask_853 = |_out_romask_T_853; // @[RegisterRouter.scala:87:24] wire out_womask_853 = &_out_womask_T_853; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_853 = out_rivalid_1_707 & out_rimask_853; // @[RegisterRouter.scala:87:24] wire _out_T_8370 = out_f_rivalid_853; // @[RegisterRouter.scala:87:24] wire out_f_roready_853 = out_roready_1_707 & out_romask_853; // @[RegisterRouter.scala:87:24] wire _out_T_8371 = out_f_roready_853; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_853 = out_wivalid_1_707 & out_wimask_853; // @[RegisterRouter.scala:87:24] wire out_f_woready_853 = out_woready_1_707 & out_womask_853; // @[RegisterRouter.scala:87:24] wire _out_T_8372 = ~out_rimask_853; // @[RegisterRouter.scala:87:24] wire _out_T_8373 = ~out_wimask_853; // @[RegisterRouter.scala:87:24] wire _out_T_8374 = ~out_romask_853; // @[RegisterRouter.scala:87:24] wire _out_T_8375 = ~out_womask_853; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8377 = _out_T_8376; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_727 = _out_T_8377; // @[RegisterRouter.scala:87:24] wire out_rimask_854 = |_out_rimask_T_854; // @[RegisterRouter.scala:87:24] wire out_wimask_854 = &_out_wimask_T_854; // @[RegisterRouter.scala:87:24] wire out_romask_854 = |_out_romask_T_854; // @[RegisterRouter.scala:87:24] wire out_womask_854 = &_out_womask_T_854; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_854 = out_rivalid_1_708 & out_rimask_854; // @[RegisterRouter.scala:87:24] wire _out_T_8379 = out_f_rivalid_854; // @[RegisterRouter.scala:87:24] wire out_f_roready_854 = out_roready_1_708 & out_romask_854; // @[RegisterRouter.scala:87:24] wire _out_T_8380 = out_f_roready_854; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_854 = out_wivalid_1_708 & out_wimask_854; // @[RegisterRouter.scala:87:24] wire out_f_woready_854 = out_woready_1_708 & out_womask_854; // @[RegisterRouter.scala:87:24] wire _out_T_8381 = ~out_rimask_854; // @[RegisterRouter.scala:87:24] wire _out_T_8382 = ~out_wimask_854; // @[RegisterRouter.scala:87:24] wire _out_T_8383 = ~out_romask_854; // @[RegisterRouter.scala:87:24] wire _out_T_8384 = ~out_womask_854; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_727 = {hi_682, flags_0_go, _out_prepend_T_727}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8385 = out_prepend_727; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8386 = _out_T_8385; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_728 = _out_T_8386; // @[RegisterRouter.scala:87:24] wire out_rimask_855 = |_out_rimask_T_855; // @[RegisterRouter.scala:87:24] wire out_wimask_855 = &_out_wimask_T_855; // @[RegisterRouter.scala:87:24] wire out_romask_855 = |_out_romask_T_855; // @[RegisterRouter.scala:87:24] wire out_womask_855 = &_out_womask_T_855; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_855 = out_rivalid_1_709 & out_rimask_855; // @[RegisterRouter.scala:87:24] wire _out_T_8388 = out_f_rivalid_855; // @[RegisterRouter.scala:87:24] wire out_f_roready_855 = out_roready_1_709 & out_romask_855; // @[RegisterRouter.scala:87:24] wire _out_T_8389 = out_f_roready_855; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_855 = out_wivalid_1_709 & out_wimask_855; // @[RegisterRouter.scala:87:24] wire out_f_woready_855 = out_woready_1_709 & out_womask_855; // @[RegisterRouter.scala:87:24] wire _out_T_8390 = ~out_rimask_855; // @[RegisterRouter.scala:87:24] wire _out_T_8391 = ~out_wimask_855; // @[RegisterRouter.scala:87:24] wire _out_T_8392 = ~out_romask_855; // @[RegisterRouter.scala:87:24] wire _out_T_8393 = ~out_womask_855; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_728 = {hi_683, flags_0_go, _out_prepend_T_728}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8394 = out_prepend_728; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8395 = _out_T_8394; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_729 = _out_T_8395; // @[RegisterRouter.scala:87:24] wire out_rimask_856 = |_out_rimask_T_856; // @[RegisterRouter.scala:87:24] wire out_wimask_856 = &_out_wimask_T_856; // @[RegisterRouter.scala:87:24] wire out_romask_856 = |_out_romask_T_856; // @[RegisterRouter.scala:87:24] wire out_womask_856 = &_out_womask_T_856; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_856 = out_rivalid_1_710 & out_rimask_856; // @[RegisterRouter.scala:87:24] wire _out_T_8397 = out_f_rivalid_856; // @[RegisterRouter.scala:87:24] wire out_f_roready_856 = out_roready_1_710 & out_romask_856; // @[RegisterRouter.scala:87:24] wire _out_T_8398 = out_f_roready_856; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_856 = out_wivalid_1_710 & out_wimask_856; // @[RegisterRouter.scala:87:24] wire out_f_woready_856 = out_woready_1_710 & out_womask_856; // @[RegisterRouter.scala:87:24] wire _out_T_8399 = ~out_rimask_856; // @[RegisterRouter.scala:87:24] wire _out_T_8400 = ~out_wimask_856; // @[RegisterRouter.scala:87:24] wire _out_T_8401 = ~out_romask_856; // @[RegisterRouter.scala:87:24] wire _out_T_8402 = ~out_womask_856; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_729 = {hi_684, flags_0_go, _out_prepend_T_729}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8403 = out_prepend_729; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8404 = _out_T_8403; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_730 = _out_T_8404; // @[RegisterRouter.scala:87:24] wire out_rimask_857 = |_out_rimask_T_857; // @[RegisterRouter.scala:87:24] wire out_wimask_857 = &_out_wimask_T_857; // @[RegisterRouter.scala:87:24] wire out_romask_857 = |_out_romask_T_857; // @[RegisterRouter.scala:87:24] wire out_womask_857 = &_out_womask_T_857; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_857 = out_rivalid_1_711 & out_rimask_857; // @[RegisterRouter.scala:87:24] wire _out_T_8406 = out_f_rivalid_857; // @[RegisterRouter.scala:87:24] wire out_f_roready_857 = out_roready_1_711 & out_romask_857; // @[RegisterRouter.scala:87:24] wire _out_T_8407 = out_f_roready_857; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_857 = out_wivalid_1_711 & out_wimask_857; // @[RegisterRouter.scala:87:24] wire out_f_woready_857 = out_woready_1_711 & out_womask_857; // @[RegisterRouter.scala:87:24] wire _out_T_8408 = ~out_rimask_857; // @[RegisterRouter.scala:87:24] wire _out_T_8409 = ~out_wimask_857; // @[RegisterRouter.scala:87:24] wire _out_T_8410 = ~out_romask_857; // @[RegisterRouter.scala:87:24] wire _out_T_8411 = ~out_womask_857; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_730 = {hi_685, flags_0_go, _out_prepend_T_730}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8412 = out_prepend_730; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8413 = _out_T_8412; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_731 = _out_T_8413; // @[RegisterRouter.scala:87:24] wire out_rimask_858 = |_out_rimask_T_858; // @[RegisterRouter.scala:87:24] wire out_wimask_858 = &_out_wimask_T_858; // @[RegisterRouter.scala:87:24] wire out_romask_858 = |_out_romask_T_858; // @[RegisterRouter.scala:87:24] wire out_womask_858 = &_out_womask_T_858; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_858 = out_rivalid_1_712 & out_rimask_858; // @[RegisterRouter.scala:87:24] wire _out_T_8415 = out_f_rivalid_858; // @[RegisterRouter.scala:87:24] wire out_f_roready_858 = out_roready_1_712 & out_romask_858; // @[RegisterRouter.scala:87:24] wire _out_T_8416 = out_f_roready_858; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_858 = out_wivalid_1_712 & out_wimask_858; // @[RegisterRouter.scala:87:24] wire out_f_woready_858 = out_woready_1_712 & out_womask_858; // @[RegisterRouter.scala:87:24] wire _out_T_8417 = ~out_rimask_858; // @[RegisterRouter.scala:87:24] wire _out_T_8418 = ~out_wimask_858; // @[RegisterRouter.scala:87:24] wire _out_T_8419 = ~out_romask_858; // @[RegisterRouter.scala:87:24] wire _out_T_8420 = ~out_womask_858; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_731 = {hi_686, flags_0_go, _out_prepend_T_731}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8421 = out_prepend_731; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8422 = _out_T_8421; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_732 = _out_T_8422; // @[RegisterRouter.scala:87:24] wire out_rimask_859 = |_out_rimask_T_859; // @[RegisterRouter.scala:87:24] wire out_wimask_859 = &_out_wimask_T_859; // @[RegisterRouter.scala:87:24] wire out_romask_859 = |_out_romask_T_859; // @[RegisterRouter.scala:87:24] wire out_womask_859 = &_out_womask_T_859; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_859 = out_rivalid_1_713 & out_rimask_859; // @[RegisterRouter.scala:87:24] wire _out_T_8424 = out_f_rivalid_859; // @[RegisterRouter.scala:87:24] wire out_f_roready_859 = out_roready_1_713 & out_romask_859; // @[RegisterRouter.scala:87:24] wire _out_T_8425 = out_f_roready_859; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_859 = out_wivalid_1_713 & out_wimask_859; // @[RegisterRouter.scala:87:24] wire out_f_woready_859 = out_woready_1_713 & out_womask_859; // @[RegisterRouter.scala:87:24] wire _out_T_8426 = ~out_rimask_859; // @[RegisterRouter.scala:87:24] wire _out_T_8427 = ~out_wimask_859; // @[RegisterRouter.scala:87:24] wire _out_T_8428 = ~out_romask_859; // @[RegisterRouter.scala:87:24] wire _out_T_8429 = ~out_womask_859; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_732 = {hi_687, flags_0_go, _out_prepend_T_732}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8430 = out_prepend_732; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8431 = _out_T_8430; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_733 = _out_T_8431; // @[RegisterRouter.scala:87:24] wire out_rimask_860 = |_out_rimask_T_860; // @[RegisterRouter.scala:87:24] wire out_wimask_860 = &_out_wimask_T_860; // @[RegisterRouter.scala:87:24] wire out_romask_860 = |_out_romask_T_860; // @[RegisterRouter.scala:87:24] wire out_womask_860 = &_out_womask_T_860; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_860 = out_rivalid_1_714 & out_rimask_860; // @[RegisterRouter.scala:87:24] wire _out_T_8433 = out_f_rivalid_860; // @[RegisterRouter.scala:87:24] wire out_f_roready_860 = out_roready_1_714 & out_romask_860; // @[RegisterRouter.scala:87:24] wire _out_T_8434 = out_f_roready_860; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_860 = out_wivalid_1_714 & out_wimask_860; // @[RegisterRouter.scala:87:24] wire out_f_woready_860 = out_woready_1_714 & out_womask_860; // @[RegisterRouter.scala:87:24] wire _out_T_8435 = ~out_rimask_860; // @[RegisterRouter.scala:87:24] wire _out_T_8436 = ~out_wimask_860; // @[RegisterRouter.scala:87:24] wire _out_T_8437 = ~out_romask_860; // @[RegisterRouter.scala:87:24] wire _out_T_8438 = ~out_womask_860; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_733 = {hi_688, flags_0_go, _out_prepend_T_733}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8439 = out_prepend_733; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8440 = _out_T_8439; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_213 = _out_T_8440; // @[MuxLiteral.scala:49:48] wire out_rimask_861 = |_out_rimask_T_861; // @[RegisterRouter.scala:87:24] wire out_wimask_861 = &_out_wimask_T_861; // @[RegisterRouter.scala:87:24] wire out_romask_861 = |_out_romask_T_861; // @[RegisterRouter.scala:87:24] wire out_womask_861 = &_out_womask_T_861; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_861 = out_rivalid_1_715 & out_rimask_861; // @[RegisterRouter.scala:87:24] wire _out_T_8442 = out_f_rivalid_861; // @[RegisterRouter.scala:87:24] wire out_f_roready_861 = out_roready_1_715 & out_romask_861; // @[RegisterRouter.scala:87:24] wire _out_T_8443 = out_f_roready_861; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_861 = out_wivalid_1_715 & out_wimask_861; // @[RegisterRouter.scala:87:24] wire out_f_woready_861 = out_woready_1_715 & out_womask_861; // @[RegisterRouter.scala:87:24] wire _out_T_8444 = ~out_rimask_861; // @[RegisterRouter.scala:87:24] wire _out_T_8445 = ~out_wimask_861; // @[RegisterRouter.scala:87:24] wire _out_T_8446 = ~out_romask_861; // @[RegisterRouter.scala:87:24] wire _out_T_8447 = ~out_womask_861; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8449 = _out_T_8448; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_734 = _out_T_8449; // @[RegisterRouter.scala:87:24] wire out_rimask_862 = |_out_rimask_T_862; // @[RegisterRouter.scala:87:24] wire out_wimask_862 = &_out_wimask_T_862; // @[RegisterRouter.scala:87:24] wire out_romask_862 = |_out_romask_T_862; // @[RegisterRouter.scala:87:24] wire out_womask_862 = &_out_womask_T_862; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_862 = out_rivalid_1_716 & out_rimask_862; // @[RegisterRouter.scala:87:24] wire _out_T_8451 = out_f_rivalid_862; // @[RegisterRouter.scala:87:24] wire out_f_roready_862 = out_roready_1_716 & out_romask_862; // @[RegisterRouter.scala:87:24] wire _out_T_8452 = out_f_roready_862; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_862 = out_wivalid_1_716 & out_wimask_862; // @[RegisterRouter.scala:87:24] wire out_f_woready_862 = out_woready_1_716 & out_womask_862; // @[RegisterRouter.scala:87:24] wire _out_T_8453 = ~out_rimask_862; // @[RegisterRouter.scala:87:24] wire _out_T_8454 = ~out_wimask_862; // @[RegisterRouter.scala:87:24] wire _out_T_8455 = ~out_romask_862; // @[RegisterRouter.scala:87:24] wire _out_T_8456 = ~out_womask_862; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_734 = {hi_218, flags_0_go, _out_prepend_T_734}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8457 = out_prepend_734; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8458 = _out_T_8457; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_735 = _out_T_8458; // @[RegisterRouter.scala:87:24] wire out_rimask_863 = |_out_rimask_T_863; // @[RegisterRouter.scala:87:24] wire out_wimask_863 = &_out_wimask_T_863; // @[RegisterRouter.scala:87:24] wire out_romask_863 = |_out_romask_T_863; // @[RegisterRouter.scala:87:24] wire out_womask_863 = &_out_womask_T_863; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_863 = out_rivalid_1_717 & out_rimask_863; // @[RegisterRouter.scala:87:24] wire _out_T_8460 = out_f_rivalid_863; // @[RegisterRouter.scala:87:24] wire out_f_roready_863 = out_roready_1_717 & out_romask_863; // @[RegisterRouter.scala:87:24] wire _out_T_8461 = out_f_roready_863; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_863 = out_wivalid_1_717 & out_wimask_863; // @[RegisterRouter.scala:87:24] wire out_f_woready_863 = out_woready_1_717 & out_womask_863; // @[RegisterRouter.scala:87:24] wire _out_T_8462 = ~out_rimask_863; // @[RegisterRouter.scala:87:24] wire _out_T_8463 = ~out_wimask_863; // @[RegisterRouter.scala:87:24] wire _out_T_8464 = ~out_romask_863; // @[RegisterRouter.scala:87:24] wire _out_T_8465 = ~out_womask_863; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_735 = {hi_219, flags_0_go, _out_prepend_T_735}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8466 = out_prepend_735; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8467 = _out_T_8466; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_736 = _out_T_8467; // @[RegisterRouter.scala:87:24] wire out_rimask_864 = |_out_rimask_T_864; // @[RegisterRouter.scala:87:24] wire out_wimask_864 = &_out_wimask_T_864; // @[RegisterRouter.scala:87:24] wire out_romask_864 = |_out_romask_T_864; // @[RegisterRouter.scala:87:24] wire out_womask_864 = &_out_womask_T_864; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_864 = out_rivalid_1_718 & out_rimask_864; // @[RegisterRouter.scala:87:24] wire _out_T_8469 = out_f_rivalid_864; // @[RegisterRouter.scala:87:24] wire out_f_roready_864 = out_roready_1_718 & out_romask_864; // @[RegisterRouter.scala:87:24] wire _out_T_8470 = out_f_roready_864; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_864 = out_wivalid_1_718 & out_wimask_864; // @[RegisterRouter.scala:87:24] wire out_f_woready_864 = out_woready_1_718 & out_womask_864; // @[RegisterRouter.scala:87:24] wire _out_T_8471 = ~out_rimask_864; // @[RegisterRouter.scala:87:24] wire _out_T_8472 = ~out_wimask_864; // @[RegisterRouter.scala:87:24] wire _out_T_8473 = ~out_romask_864; // @[RegisterRouter.scala:87:24] wire _out_T_8474 = ~out_womask_864; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_736 = {hi_220, flags_0_go, _out_prepend_T_736}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8475 = out_prepend_736; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8476 = _out_T_8475; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_737 = _out_T_8476; // @[RegisterRouter.scala:87:24] wire out_rimask_865 = |_out_rimask_T_865; // @[RegisterRouter.scala:87:24] wire out_wimask_865 = &_out_wimask_T_865; // @[RegisterRouter.scala:87:24] wire out_romask_865 = |_out_romask_T_865; // @[RegisterRouter.scala:87:24] wire out_womask_865 = &_out_womask_T_865; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_865 = out_rivalid_1_719 & out_rimask_865; // @[RegisterRouter.scala:87:24] wire _out_T_8478 = out_f_rivalid_865; // @[RegisterRouter.scala:87:24] wire out_f_roready_865 = out_roready_1_719 & out_romask_865; // @[RegisterRouter.scala:87:24] wire _out_T_8479 = out_f_roready_865; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_865 = out_wivalid_1_719 & out_wimask_865; // @[RegisterRouter.scala:87:24] wire out_f_woready_865 = out_woready_1_719 & out_womask_865; // @[RegisterRouter.scala:87:24] wire _out_T_8480 = ~out_rimask_865; // @[RegisterRouter.scala:87:24] wire _out_T_8481 = ~out_wimask_865; // @[RegisterRouter.scala:87:24] wire _out_T_8482 = ~out_romask_865; // @[RegisterRouter.scala:87:24] wire _out_T_8483 = ~out_womask_865; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_737 = {hi_221, flags_0_go, _out_prepend_T_737}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8484 = out_prepend_737; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8485 = _out_T_8484; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_738 = _out_T_8485; // @[RegisterRouter.scala:87:24] wire out_rimask_866 = |_out_rimask_T_866; // @[RegisterRouter.scala:87:24] wire out_wimask_866 = &_out_wimask_T_866; // @[RegisterRouter.scala:87:24] wire out_romask_866 = |_out_romask_T_866; // @[RegisterRouter.scala:87:24] wire out_womask_866 = &_out_womask_T_866; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_866 = out_rivalid_1_720 & out_rimask_866; // @[RegisterRouter.scala:87:24] wire _out_T_8487 = out_f_rivalid_866; // @[RegisterRouter.scala:87:24] wire out_f_roready_866 = out_roready_1_720 & out_romask_866; // @[RegisterRouter.scala:87:24] wire _out_T_8488 = out_f_roready_866; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_866 = out_wivalid_1_720 & out_wimask_866; // @[RegisterRouter.scala:87:24] wire out_f_woready_866 = out_woready_1_720 & out_womask_866; // @[RegisterRouter.scala:87:24] wire _out_T_8489 = ~out_rimask_866; // @[RegisterRouter.scala:87:24] wire _out_T_8490 = ~out_wimask_866; // @[RegisterRouter.scala:87:24] wire _out_T_8491 = ~out_romask_866; // @[RegisterRouter.scala:87:24] wire _out_T_8492 = ~out_womask_866; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_738 = {hi_222, flags_0_go, _out_prepend_T_738}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8493 = out_prepend_738; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8494 = _out_T_8493; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_739 = _out_T_8494; // @[RegisterRouter.scala:87:24] wire out_rimask_867 = |_out_rimask_T_867; // @[RegisterRouter.scala:87:24] wire out_wimask_867 = &_out_wimask_T_867; // @[RegisterRouter.scala:87:24] wire out_romask_867 = |_out_romask_T_867; // @[RegisterRouter.scala:87:24] wire out_womask_867 = &_out_womask_T_867; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_867 = out_rivalid_1_721 & out_rimask_867; // @[RegisterRouter.scala:87:24] wire _out_T_8496 = out_f_rivalid_867; // @[RegisterRouter.scala:87:24] wire out_f_roready_867 = out_roready_1_721 & out_romask_867; // @[RegisterRouter.scala:87:24] wire _out_T_8497 = out_f_roready_867; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_867 = out_wivalid_1_721 & out_wimask_867; // @[RegisterRouter.scala:87:24] wire out_f_woready_867 = out_woready_1_721 & out_womask_867; // @[RegisterRouter.scala:87:24] wire _out_T_8498 = ~out_rimask_867; // @[RegisterRouter.scala:87:24] wire _out_T_8499 = ~out_wimask_867; // @[RegisterRouter.scala:87:24] wire _out_T_8500 = ~out_romask_867; // @[RegisterRouter.scala:87:24] wire _out_T_8501 = ~out_womask_867; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_739 = {hi_223, flags_0_go, _out_prepend_T_739}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8502 = out_prepend_739; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8503 = _out_T_8502; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_740 = _out_T_8503; // @[RegisterRouter.scala:87:24] wire out_rimask_868 = |_out_rimask_T_868; // @[RegisterRouter.scala:87:24] wire out_wimask_868 = &_out_wimask_T_868; // @[RegisterRouter.scala:87:24] wire out_romask_868 = |_out_romask_T_868; // @[RegisterRouter.scala:87:24] wire out_womask_868 = &_out_womask_T_868; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_868 = out_rivalid_1_722 & out_rimask_868; // @[RegisterRouter.scala:87:24] wire _out_T_8505 = out_f_rivalid_868; // @[RegisterRouter.scala:87:24] wire out_f_roready_868 = out_roready_1_722 & out_romask_868; // @[RegisterRouter.scala:87:24] wire _out_T_8506 = out_f_roready_868; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_868 = out_wivalid_1_722 & out_wimask_868; // @[RegisterRouter.scala:87:24] wire out_f_woready_868 = out_woready_1_722 & out_womask_868; // @[RegisterRouter.scala:87:24] wire _out_T_8507 = ~out_rimask_868; // @[RegisterRouter.scala:87:24] wire _out_T_8508 = ~out_wimask_868; // @[RegisterRouter.scala:87:24] wire _out_T_8509 = ~out_romask_868; // @[RegisterRouter.scala:87:24] wire _out_T_8510 = ~out_womask_868; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_740 = {hi_224, flags_0_go, _out_prepend_T_740}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8511 = out_prepend_740; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8512 = _out_T_8511; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_155 = _out_T_8512; // @[MuxLiteral.scala:49:48] wire out_rimask_869 = |_out_rimask_T_869; // @[RegisterRouter.scala:87:24] wire out_wimask_869 = &_out_wimask_T_869; // @[RegisterRouter.scala:87:24] wire out_romask_869 = |_out_romask_T_869; // @[RegisterRouter.scala:87:24] wire out_womask_869 = &_out_womask_T_869; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_869 = out_rivalid_1_723 & out_rimask_869; // @[RegisterRouter.scala:87:24] wire _out_T_8514 = out_f_rivalid_869; // @[RegisterRouter.scala:87:24] wire out_f_roready_869 = out_roready_1_723 & out_romask_869; // @[RegisterRouter.scala:87:24] wire _out_T_8515 = out_f_roready_869; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_869 = out_wivalid_1_723 & out_wimask_869; // @[RegisterRouter.scala:87:24] wire out_f_woready_869 = out_woready_1_723 & out_womask_869; // @[RegisterRouter.scala:87:24] wire _out_T_8516 = ~out_rimask_869; // @[RegisterRouter.scala:87:24] wire _out_T_8517 = ~out_wimask_869; // @[RegisterRouter.scala:87:24] wire _out_T_8518 = ~out_romask_869; // @[RegisterRouter.scala:87:24] wire _out_T_8519 = ~out_womask_869; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8521 = _out_T_8520; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_741 = _out_T_8521; // @[RegisterRouter.scala:87:24] wire out_rimask_870 = |_out_rimask_T_870; // @[RegisterRouter.scala:87:24] wire out_wimask_870 = &_out_wimask_T_870; // @[RegisterRouter.scala:87:24] wire out_romask_870 = |_out_romask_T_870; // @[RegisterRouter.scala:87:24] wire out_womask_870 = &_out_womask_T_870; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_870 = out_rivalid_1_724 & out_rimask_870; // @[RegisterRouter.scala:87:24] wire _out_T_8523 = out_f_rivalid_870; // @[RegisterRouter.scala:87:24] wire out_f_roready_870 = out_roready_1_724 & out_romask_870; // @[RegisterRouter.scala:87:24] wire _out_T_8524 = out_f_roready_870; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_870 = out_wivalid_1_724 & out_wimask_870; // @[RegisterRouter.scala:87:24] wire out_f_woready_870 = out_woready_1_724 & out_womask_870; // @[RegisterRouter.scala:87:24] wire _out_T_8525 = ~out_rimask_870; // @[RegisterRouter.scala:87:24] wire _out_T_8526 = ~out_wimask_870; // @[RegisterRouter.scala:87:24] wire _out_T_8527 = ~out_romask_870; // @[RegisterRouter.scala:87:24] wire _out_T_8528 = ~out_womask_870; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_741 = {hi_562, flags_0_go, _out_prepend_T_741}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8529 = out_prepend_741; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8530 = _out_T_8529; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_742 = _out_T_8530; // @[RegisterRouter.scala:87:24] wire out_rimask_871 = |_out_rimask_T_871; // @[RegisterRouter.scala:87:24] wire out_wimask_871 = &_out_wimask_T_871; // @[RegisterRouter.scala:87:24] wire out_romask_871 = |_out_romask_T_871; // @[RegisterRouter.scala:87:24] wire out_womask_871 = &_out_womask_T_871; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_871 = out_rivalid_1_725 & out_rimask_871; // @[RegisterRouter.scala:87:24] wire _out_T_8532 = out_f_rivalid_871; // @[RegisterRouter.scala:87:24] wire out_f_roready_871 = out_roready_1_725 & out_romask_871; // @[RegisterRouter.scala:87:24] wire _out_T_8533 = out_f_roready_871; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_871 = out_wivalid_1_725 & out_wimask_871; // @[RegisterRouter.scala:87:24] wire out_f_woready_871 = out_woready_1_725 & out_womask_871; // @[RegisterRouter.scala:87:24] wire _out_T_8534 = ~out_rimask_871; // @[RegisterRouter.scala:87:24] wire _out_T_8535 = ~out_wimask_871; // @[RegisterRouter.scala:87:24] wire _out_T_8536 = ~out_romask_871; // @[RegisterRouter.scala:87:24] wire _out_T_8537 = ~out_womask_871; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_742 = {hi_563, flags_0_go, _out_prepend_T_742}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8538 = out_prepend_742; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8539 = _out_T_8538; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_743 = _out_T_8539; // @[RegisterRouter.scala:87:24] wire out_rimask_872 = |_out_rimask_T_872; // @[RegisterRouter.scala:87:24] wire out_wimask_872 = &_out_wimask_T_872; // @[RegisterRouter.scala:87:24] wire out_romask_872 = |_out_romask_T_872; // @[RegisterRouter.scala:87:24] wire out_womask_872 = &_out_womask_T_872; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_872 = out_rivalid_1_726 & out_rimask_872; // @[RegisterRouter.scala:87:24] wire _out_T_8541 = out_f_rivalid_872; // @[RegisterRouter.scala:87:24] wire out_f_roready_872 = out_roready_1_726 & out_romask_872; // @[RegisterRouter.scala:87:24] wire _out_T_8542 = out_f_roready_872; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_872 = out_wivalid_1_726 & out_wimask_872; // @[RegisterRouter.scala:87:24] wire out_f_woready_872 = out_woready_1_726 & out_womask_872; // @[RegisterRouter.scala:87:24] wire _out_T_8543 = ~out_rimask_872; // @[RegisterRouter.scala:87:24] wire _out_T_8544 = ~out_wimask_872; // @[RegisterRouter.scala:87:24] wire _out_T_8545 = ~out_romask_872; // @[RegisterRouter.scala:87:24] wire _out_T_8546 = ~out_womask_872; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_743 = {hi_564, flags_0_go, _out_prepend_T_743}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8547 = out_prepend_743; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8548 = _out_T_8547; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_744 = _out_T_8548; // @[RegisterRouter.scala:87:24] wire out_rimask_873 = |_out_rimask_T_873; // @[RegisterRouter.scala:87:24] wire out_wimask_873 = &_out_wimask_T_873; // @[RegisterRouter.scala:87:24] wire out_romask_873 = |_out_romask_T_873; // @[RegisterRouter.scala:87:24] wire out_womask_873 = &_out_womask_T_873; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_873 = out_rivalid_1_727 & out_rimask_873; // @[RegisterRouter.scala:87:24] wire _out_T_8550 = out_f_rivalid_873; // @[RegisterRouter.scala:87:24] wire out_f_roready_873 = out_roready_1_727 & out_romask_873; // @[RegisterRouter.scala:87:24] wire _out_T_8551 = out_f_roready_873; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_873 = out_wivalid_1_727 & out_wimask_873; // @[RegisterRouter.scala:87:24] wire out_f_woready_873 = out_woready_1_727 & out_womask_873; // @[RegisterRouter.scala:87:24] wire _out_T_8552 = ~out_rimask_873; // @[RegisterRouter.scala:87:24] wire _out_T_8553 = ~out_wimask_873; // @[RegisterRouter.scala:87:24] wire _out_T_8554 = ~out_romask_873; // @[RegisterRouter.scala:87:24] wire _out_T_8555 = ~out_womask_873; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_744 = {hi_565, flags_0_go, _out_prepend_T_744}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8556 = out_prepend_744; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8557 = _out_T_8556; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_745 = _out_T_8557; // @[RegisterRouter.scala:87:24] wire out_rimask_874 = |_out_rimask_T_874; // @[RegisterRouter.scala:87:24] wire out_wimask_874 = &_out_wimask_T_874; // @[RegisterRouter.scala:87:24] wire out_romask_874 = |_out_romask_T_874; // @[RegisterRouter.scala:87:24] wire out_womask_874 = &_out_womask_T_874; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_874 = out_rivalid_1_728 & out_rimask_874; // @[RegisterRouter.scala:87:24] wire _out_T_8559 = out_f_rivalid_874; // @[RegisterRouter.scala:87:24] wire out_f_roready_874 = out_roready_1_728 & out_romask_874; // @[RegisterRouter.scala:87:24] wire _out_T_8560 = out_f_roready_874; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_874 = out_wivalid_1_728 & out_wimask_874; // @[RegisterRouter.scala:87:24] wire out_f_woready_874 = out_woready_1_728 & out_womask_874; // @[RegisterRouter.scala:87:24] wire _out_T_8561 = ~out_rimask_874; // @[RegisterRouter.scala:87:24] wire _out_T_8562 = ~out_wimask_874; // @[RegisterRouter.scala:87:24] wire _out_T_8563 = ~out_romask_874; // @[RegisterRouter.scala:87:24] wire _out_T_8564 = ~out_womask_874; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_745 = {hi_566, flags_0_go, _out_prepend_T_745}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8565 = out_prepend_745; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8566 = _out_T_8565; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_746 = _out_T_8566; // @[RegisterRouter.scala:87:24] wire out_rimask_875 = |_out_rimask_T_875; // @[RegisterRouter.scala:87:24] wire out_wimask_875 = &_out_wimask_T_875; // @[RegisterRouter.scala:87:24] wire out_romask_875 = |_out_romask_T_875; // @[RegisterRouter.scala:87:24] wire out_womask_875 = &_out_womask_T_875; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_875 = out_rivalid_1_729 & out_rimask_875; // @[RegisterRouter.scala:87:24] wire _out_T_8568 = out_f_rivalid_875; // @[RegisterRouter.scala:87:24] wire out_f_roready_875 = out_roready_1_729 & out_romask_875; // @[RegisterRouter.scala:87:24] wire _out_T_8569 = out_f_roready_875; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_875 = out_wivalid_1_729 & out_wimask_875; // @[RegisterRouter.scala:87:24] wire out_f_woready_875 = out_woready_1_729 & out_womask_875; // @[RegisterRouter.scala:87:24] wire _out_T_8570 = ~out_rimask_875; // @[RegisterRouter.scala:87:24] wire _out_T_8571 = ~out_wimask_875; // @[RegisterRouter.scala:87:24] wire _out_T_8572 = ~out_romask_875; // @[RegisterRouter.scala:87:24] wire _out_T_8573 = ~out_womask_875; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_746 = {hi_567, flags_0_go, _out_prepend_T_746}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8574 = out_prepend_746; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8575 = _out_T_8574; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_747 = _out_T_8575; // @[RegisterRouter.scala:87:24] wire out_rimask_876 = |_out_rimask_T_876; // @[RegisterRouter.scala:87:24] wire out_wimask_876 = &_out_wimask_T_876; // @[RegisterRouter.scala:87:24] wire out_romask_876 = |_out_romask_T_876; // @[RegisterRouter.scala:87:24] wire out_womask_876 = &_out_womask_T_876; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_876 = out_rivalid_1_730 & out_rimask_876; // @[RegisterRouter.scala:87:24] wire _out_T_8577 = out_f_rivalid_876; // @[RegisterRouter.scala:87:24] wire out_f_roready_876 = out_roready_1_730 & out_romask_876; // @[RegisterRouter.scala:87:24] wire _out_T_8578 = out_f_roready_876; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_876 = out_wivalid_1_730 & out_wimask_876; // @[RegisterRouter.scala:87:24] wire out_f_woready_876 = out_woready_1_730 & out_womask_876; // @[RegisterRouter.scala:87:24] wire _out_T_8579 = ~out_rimask_876; // @[RegisterRouter.scala:87:24] wire _out_T_8580 = ~out_wimask_876; // @[RegisterRouter.scala:87:24] wire _out_T_8581 = ~out_romask_876; // @[RegisterRouter.scala:87:24] wire _out_T_8582 = ~out_womask_876; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_747 = {hi_568, flags_0_go, _out_prepend_T_747}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8583 = out_prepend_747; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8584 = _out_T_8583; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_198 = _out_T_8584; // @[MuxLiteral.scala:49:48] wire out_rimask_877 = |_out_rimask_T_877; // @[RegisterRouter.scala:87:24] wire out_wimask_877 = &_out_wimask_T_877; // @[RegisterRouter.scala:87:24] wire out_romask_877 = |_out_romask_T_877; // @[RegisterRouter.scala:87:24] wire out_womask_877 = &_out_womask_T_877; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_877 = out_rivalid_1_731 & out_rimask_877; // @[RegisterRouter.scala:87:24] wire _out_T_8586 = out_f_rivalid_877; // @[RegisterRouter.scala:87:24] wire out_f_roready_877 = out_roready_1_731 & out_romask_877; // @[RegisterRouter.scala:87:24] wire _out_T_8587 = out_f_roready_877; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_877 = out_wivalid_1_731 & out_wimask_877; // @[RegisterRouter.scala:87:24] wire _out_T_8588 = out_f_wivalid_877; // @[RegisterRouter.scala:87:24] wire out_f_woready_877 = out_woready_1_731 & out_womask_877; // @[RegisterRouter.scala:87:24] wire _out_T_8589 = out_f_woready_877; // @[RegisterRouter.scala:87:24] wire _out_T_8590 = ~out_rimask_877; // @[RegisterRouter.scala:87:24] wire _out_T_8591 = ~out_wimask_877; // @[RegisterRouter.scala:87:24] wire _out_T_8592 = ~out_romask_877; // @[RegisterRouter.scala:87:24] wire _out_T_8593 = ~out_womask_877; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8595 = _out_T_8594; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_748 = _out_T_8595; // @[RegisterRouter.scala:87:24] wire out_rimask_878 = |_out_rimask_T_878; // @[RegisterRouter.scala:87:24] wire out_wimask_878 = &_out_wimask_T_878; // @[RegisterRouter.scala:87:24] wire out_romask_878 = |_out_romask_T_878; // @[RegisterRouter.scala:87:24] wire out_womask_878 = &_out_womask_T_878; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_878 = out_rivalid_1_732 & out_rimask_878; // @[RegisterRouter.scala:87:24] wire _out_T_8597 = out_f_rivalid_878; // @[RegisterRouter.scala:87:24] wire out_f_roready_878 = out_roready_1_732 & out_romask_878; // @[RegisterRouter.scala:87:24] wire _out_T_8598 = out_f_roready_878; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_878 = out_wivalid_1_732 & out_wimask_878; // @[RegisterRouter.scala:87:24] wire _out_T_8599 = out_f_wivalid_878; // @[RegisterRouter.scala:87:24] wire out_f_woready_878 = out_woready_1_732 & out_womask_878; // @[RegisterRouter.scala:87:24] wire _out_T_8600 = out_f_woready_878; // @[RegisterRouter.scala:87:24] wire _out_T_8601 = ~out_rimask_878; // @[RegisterRouter.scala:87:24] wire _out_T_8602 = ~out_wimask_878; // @[RegisterRouter.scala:87:24] wire _out_T_8603 = ~out_romask_878; // @[RegisterRouter.scala:87:24] wire _out_T_8604 = ~out_womask_878; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_748 = {programBufferMem_33, _out_prepend_T_748}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8605 = out_prepend_748; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8606 = _out_T_8605; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_749 = _out_T_8606; // @[RegisterRouter.scala:87:24] wire out_rimask_879 = |_out_rimask_T_879; // @[RegisterRouter.scala:87:24] wire out_wimask_879 = &_out_wimask_T_879; // @[RegisterRouter.scala:87:24] wire out_romask_879 = |_out_romask_T_879; // @[RegisterRouter.scala:87:24] wire out_womask_879 = &_out_womask_T_879; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_879 = out_rivalid_1_733 & out_rimask_879; // @[RegisterRouter.scala:87:24] wire _out_T_8608 = out_f_rivalid_879; // @[RegisterRouter.scala:87:24] wire out_f_roready_879 = out_roready_1_733 & out_romask_879; // @[RegisterRouter.scala:87:24] wire _out_T_8609 = out_f_roready_879; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_879 = out_wivalid_1_733 & out_wimask_879; // @[RegisterRouter.scala:87:24] wire _out_T_8610 = out_f_wivalid_879; // @[RegisterRouter.scala:87:24] wire out_f_woready_879 = out_woready_1_733 & out_womask_879; // @[RegisterRouter.scala:87:24] wire _out_T_8611 = out_f_woready_879; // @[RegisterRouter.scala:87:24] wire _out_T_8612 = ~out_rimask_879; // @[RegisterRouter.scala:87:24] wire _out_T_8613 = ~out_wimask_879; // @[RegisterRouter.scala:87:24] wire _out_T_8614 = ~out_romask_879; // @[RegisterRouter.scala:87:24] wire _out_T_8615 = ~out_womask_879; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_749 = {programBufferMem_34, _out_prepend_T_749}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8616 = out_prepend_749; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8617 = _out_T_8616; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_750 = _out_T_8617; // @[RegisterRouter.scala:87:24] wire out_rimask_880 = |_out_rimask_T_880; // @[RegisterRouter.scala:87:24] wire out_wimask_880 = &_out_wimask_T_880; // @[RegisterRouter.scala:87:24] wire out_romask_880 = |_out_romask_T_880; // @[RegisterRouter.scala:87:24] wire out_womask_880 = &_out_womask_T_880; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_880 = out_rivalid_1_734 & out_rimask_880; // @[RegisterRouter.scala:87:24] wire _out_T_8619 = out_f_rivalid_880; // @[RegisterRouter.scala:87:24] wire out_f_roready_880 = out_roready_1_734 & out_romask_880; // @[RegisterRouter.scala:87:24] wire _out_T_8620 = out_f_roready_880; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_880 = out_wivalid_1_734 & out_wimask_880; // @[RegisterRouter.scala:87:24] wire _out_T_8621 = out_f_wivalid_880; // @[RegisterRouter.scala:87:24] wire out_f_woready_880 = out_woready_1_734 & out_womask_880; // @[RegisterRouter.scala:87:24] wire _out_T_8622 = out_f_woready_880; // @[RegisterRouter.scala:87:24] wire _out_T_8623 = ~out_rimask_880; // @[RegisterRouter.scala:87:24] wire _out_T_8624 = ~out_wimask_880; // @[RegisterRouter.scala:87:24] wire _out_T_8625 = ~out_romask_880; // @[RegisterRouter.scala:87:24] wire _out_T_8626 = ~out_womask_880; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_750 = {programBufferMem_35, _out_prepend_T_750}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8627 = out_prepend_750; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8628 = _out_T_8627; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_751 = _out_T_8628; // @[RegisterRouter.scala:87:24] wire out_rimask_881 = |_out_rimask_T_881; // @[RegisterRouter.scala:87:24] wire out_wimask_881 = &_out_wimask_T_881; // @[RegisterRouter.scala:87:24] wire out_romask_881 = |_out_romask_T_881; // @[RegisterRouter.scala:87:24] wire out_womask_881 = &_out_womask_T_881; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_881 = out_rivalid_1_735 & out_rimask_881; // @[RegisterRouter.scala:87:24] wire _out_T_8630 = out_f_rivalid_881; // @[RegisterRouter.scala:87:24] wire out_f_roready_881 = out_roready_1_735 & out_romask_881; // @[RegisterRouter.scala:87:24] wire _out_T_8631 = out_f_roready_881; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_881 = out_wivalid_1_735 & out_wimask_881; // @[RegisterRouter.scala:87:24] wire _out_T_8632 = out_f_wivalid_881; // @[RegisterRouter.scala:87:24] wire out_f_woready_881 = out_woready_1_735 & out_womask_881; // @[RegisterRouter.scala:87:24] wire _out_T_8633 = out_f_woready_881; // @[RegisterRouter.scala:87:24] wire _out_T_8634 = ~out_rimask_881; // @[RegisterRouter.scala:87:24] wire _out_T_8635 = ~out_wimask_881; // @[RegisterRouter.scala:87:24] wire _out_T_8636 = ~out_romask_881; // @[RegisterRouter.scala:87:24] wire _out_T_8637 = ~out_womask_881; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_751 = {programBufferMem_36, _out_prepend_T_751}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8638 = out_prepend_751; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8639 = _out_T_8638; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_752 = _out_T_8639; // @[RegisterRouter.scala:87:24] wire out_rimask_882 = |_out_rimask_T_882; // @[RegisterRouter.scala:87:24] wire out_wimask_882 = &_out_wimask_T_882; // @[RegisterRouter.scala:87:24] wire out_romask_882 = |_out_romask_T_882; // @[RegisterRouter.scala:87:24] wire out_womask_882 = &_out_womask_T_882; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_882 = out_rivalid_1_736 & out_rimask_882; // @[RegisterRouter.scala:87:24] wire _out_T_8641 = out_f_rivalid_882; // @[RegisterRouter.scala:87:24] wire out_f_roready_882 = out_roready_1_736 & out_romask_882; // @[RegisterRouter.scala:87:24] wire _out_T_8642 = out_f_roready_882; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_882 = out_wivalid_1_736 & out_wimask_882; // @[RegisterRouter.scala:87:24] wire _out_T_8643 = out_f_wivalid_882; // @[RegisterRouter.scala:87:24] wire out_f_woready_882 = out_woready_1_736 & out_womask_882; // @[RegisterRouter.scala:87:24] wire _out_T_8644 = out_f_woready_882; // @[RegisterRouter.scala:87:24] wire _out_T_8645 = ~out_rimask_882; // @[RegisterRouter.scala:87:24] wire _out_T_8646 = ~out_wimask_882; // @[RegisterRouter.scala:87:24] wire _out_T_8647 = ~out_romask_882; // @[RegisterRouter.scala:87:24] wire _out_T_8648 = ~out_womask_882; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_752 = {programBufferMem_37, _out_prepend_T_752}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8649 = out_prepend_752; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8650 = _out_T_8649; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_753 = _out_T_8650; // @[RegisterRouter.scala:87:24] wire out_rimask_883 = |_out_rimask_T_883; // @[RegisterRouter.scala:87:24] wire out_wimask_883 = &_out_wimask_T_883; // @[RegisterRouter.scala:87:24] wire out_romask_883 = |_out_romask_T_883; // @[RegisterRouter.scala:87:24] wire out_womask_883 = &_out_womask_T_883; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_883 = out_rivalid_1_737 & out_rimask_883; // @[RegisterRouter.scala:87:24] wire _out_T_8652 = out_f_rivalid_883; // @[RegisterRouter.scala:87:24] wire out_f_roready_883 = out_roready_1_737 & out_romask_883; // @[RegisterRouter.scala:87:24] wire _out_T_8653 = out_f_roready_883; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_883 = out_wivalid_1_737 & out_wimask_883; // @[RegisterRouter.scala:87:24] wire _out_T_8654 = out_f_wivalid_883; // @[RegisterRouter.scala:87:24] wire out_f_woready_883 = out_woready_1_737 & out_womask_883; // @[RegisterRouter.scala:87:24] wire _out_T_8655 = out_f_woready_883; // @[RegisterRouter.scala:87:24] wire _out_T_8656 = ~out_rimask_883; // @[RegisterRouter.scala:87:24] wire _out_T_8657 = ~out_wimask_883; // @[RegisterRouter.scala:87:24] wire _out_T_8658 = ~out_romask_883; // @[RegisterRouter.scala:87:24] wire _out_T_8659 = ~out_womask_883; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_753 = {programBufferMem_38, _out_prepend_T_753}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8660 = out_prepend_753; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8661 = _out_T_8660; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_754 = _out_T_8661; // @[RegisterRouter.scala:87:24] wire out_rimask_884 = |_out_rimask_T_884; // @[RegisterRouter.scala:87:24] wire out_wimask_884 = &_out_wimask_T_884; // @[RegisterRouter.scala:87:24] wire out_romask_884 = |_out_romask_T_884; // @[RegisterRouter.scala:87:24] wire out_womask_884 = &_out_womask_T_884; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_884 = out_rivalid_1_738 & out_rimask_884; // @[RegisterRouter.scala:87:24] wire _out_T_8663 = out_f_rivalid_884; // @[RegisterRouter.scala:87:24] wire out_f_roready_884 = out_roready_1_738 & out_romask_884; // @[RegisterRouter.scala:87:24] wire _out_T_8664 = out_f_roready_884; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_884 = out_wivalid_1_738 & out_wimask_884; // @[RegisterRouter.scala:87:24] wire _out_T_8665 = out_f_wivalid_884; // @[RegisterRouter.scala:87:24] wire out_f_woready_884 = out_woready_1_738 & out_womask_884; // @[RegisterRouter.scala:87:24] wire _out_T_8666 = out_f_woready_884; // @[RegisterRouter.scala:87:24] wire _out_T_8667 = ~out_rimask_884; // @[RegisterRouter.scala:87:24] wire _out_T_8668 = ~out_wimask_884; // @[RegisterRouter.scala:87:24] wire _out_T_8669 = ~out_romask_884; // @[RegisterRouter.scala:87:24] wire _out_T_8670 = ~out_womask_884; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_754 = {programBufferMem_39, _out_prepend_T_754}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8671 = out_prepend_754; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8672 = _out_T_8671; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_108 = _out_T_8672; // @[MuxLiteral.scala:49:48] wire out_rimask_885 = |_out_rimask_T_885; // @[RegisterRouter.scala:87:24] wire out_wimask_885 = &_out_wimask_T_885; // @[RegisterRouter.scala:87:24] wire out_romask_885 = |_out_romask_T_885; // @[RegisterRouter.scala:87:24] wire out_womask_885 = &_out_womask_T_885; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_885 = out_rivalid_1_739 & out_rimask_885; // @[RegisterRouter.scala:87:24] wire _out_T_8674 = out_f_rivalid_885; // @[RegisterRouter.scala:87:24] wire out_f_roready_885 = out_roready_1_739 & out_romask_885; // @[RegisterRouter.scala:87:24] wire _out_T_8675 = out_f_roready_885; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_885 = out_wivalid_1_739 & out_wimask_885; // @[RegisterRouter.scala:87:24] wire out_f_woready_885 = out_woready_1_739 & out_womask_885; // @[RegisterRouter.scala:87:24] wire _out_T_8676 = ~out_rimask_885; // @[RegisterRouter.scala:87:24] wire _out_T_8677 = ~out_wimask_885; // @[RegisterRouter.scala:87:24] wire _out_T_8678 = ~out_romask_885; // @[RegisterRouter.scala:87:24] wire _out_T_8679 = ~out_womask_885; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8681 = _out_T_8680; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_755 = _out_T_8681; // @[RegisterRouter.scala:87:24] wire out_rimask_886 = |_out_rimask_T_886; // @[RegisterRouter.scala:87:24] wire out_wimask_886 = &_out_wimask_T_886; // @[RegisterRouter.scala:87:24] wire out_romask_886 = |_out_romask_T_886; // @[RegisterRouter.scala:87:24] wire out_womask_886 = &_out_womask_T_886; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_886 = out_rivalid_1_740 & out_rimask_886; // @[RegisterRouter.scala:87:24] wire _out_T_8683 = out_f_rivalid_886; // @[RegisterRouter.scala:87:24] wire out_f_roready_886 = out_roready_1_740 & out_romask_886; // @[RegisterRouter.scala:87:24] wire _out_T_8684 = out_f_roready_886; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_886 = out_wivalid_1_740 & out_wimask_886; // @[RegisterRouter.scala:87:24] wire out_f_woready_886 = out_woready_1_740 & out_womask_886; // @[RegisterRouter.scala:87:24] wire _out_T_8685 = ~out_rimask_886; // @[RegisterRouter.scala:87:24] wire _out_T_8686 = ~out_wimask_886; // @[RegisterRouter.scala:87:24] wire _out_T_8687 = ~out_romask_886; // @[RegisterRouter.scala:87:24] wire _out_T_8688 = ~out_womask_886; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_755 = {hi_898, flags_0_go, _out_prepend_T_755}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8689 = out_prepend_755; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8690 = _out_T_8689; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_756 = _out_T_8690; // @[RegisterRouter.scala:87:24] wire out_rimask_887 = |_out_rimask_T_887; // @[RegisterRouter.scala:87:24] wire out_wimask_887 = &_out_wimask_T_887; // @[RegisterRouter.scala:87:24] wire out_romask_887 = |_out_romask_T_887; // @[RegisterRouter.scala:87:24] wire out_womask_887 = &_out_womask_T_887; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_887 = out_rivalid_1_741 & out_rimask_887; // @[RegisterRouter.scala:87:24] wire _out_T_8692 = out_f_rivalid_887; // @[RegisterRouter.scala:87:24] wire out_f_roready_887 = out_roready_1_741 & out_romask_887; // @[RegisterRouter.scala:87:24] wire _out_T_8693 = out_f_roready_887; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_887 = out_wivalid_1_741 & out_wimask_887; // @[RegisterRouter.scala:87:24] wire out_f_woready_887 = out_woready_1_741 & out_womask_887; // @[RegisterRouter.scala:87:24] wire _out_T_8694 = ~out_rimask_887; // @[RegisterRouter.scala:87:24] wire _out_T_8695 = ~out_wimask_887; // @[RegisterRouter.scala:87:24] wire _out_T_8696 = ~out_romask_887; // @[RegisterRouter.scala:87:24] wire _out_T_8697 = ~out_womask_887; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_756 = {hi_899, flags_0_go, _out_prepend_T_756}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8698 = out_prepend_756; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8699 = _out_T_8698; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_757 = _out_T_8699; // @[RegisterRouter.scala:87:24] wire out_rimask_888 = |_out_rimask_T_888; // @[RegisterRouter.scala:87:24] wire out_wimask_888 = &_out_wimask_T_888; // @[RegisterRouter.scala:87:24] wire out_romask_888 = |_out_romask_T_888; // @[RegisterRouter.scala:87:24] wire out_womask_888 = &_out_womask_T_888; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_888 = out_rivalid_1_742 & out_rimask_888; // @[RegisterRouter.scala:87:24] wire _out_T_8701 = out_f_rivalid_888; // @[RegisterRouter.scala:87:24] wire out_f_roready_888 = out_roready_1_742 & out_romask_888; // @[RegisterRouter.scala:87:24] wire _out_T_8702 = out_f_roready_888; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_888 = out_wivalid_1_742 & out_wimask_888; // @[RegisterRouter.scala:87:24] wire out_f_woready_888 = out_woready_1_742 & out_womask_888; // @[RegisterRouter.scala:87:24] wire _out_T_8703 = ~out_rimask_888; // @[RegisterRouter.scala:87:24] wire _out_T_8704 = ~out_wimask_888; // @[RegisterRouter.scala:87:24] wire _out_T_8705 = ~out_romask_888; // @[RegisterRouter.scala:87:24] wire _out_T_8706 = ~out_womask_888; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_757 = {hi_900, flags_0_go, _out_prepend_T_757}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8707 = out_prepend_757; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8708 = _out_T_8707; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_758 = _out_T_8708; // @[RegisterRouter.scala:87:24] wire out_rimask_889 = |_out_rimask_T_889; // @[RegisterRouter.scala:87:24] wire out_wimask_889 = &_out_wimask_T_889; // @[RegisterRouter.scala:87:24] wire out_romask_889 = |_out_romask_T_889; // @[RegisterRouter.scala:87:24] wire out_womask_889 = &_out_womask_T_889; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_889 = out_rivalid_1_743 & out_rimask_889; // @[RegisterRouter.scala:87:24] wire _out_T_8710 = out_f_rivalid_889; // @[RegisterRouter.scala:87:24] wire out_f_roready_889 = out_roready_1_743 & out_romask_889; // @[RegisterRouter.scala:87:24] wire _out_T_8711 = out_f_roready_889; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_889 = out_wivalid_1_743 & out_wimask_889; // @[RegisterRouter.scala:87:24] wire out_f_woready_889 = out_woready_1_743 & out_womask_889; // @[RegisterRouter.scala:87:24] wire _out_T_8712 = ~out_rimask_889; // @[RegisterRouter.scala:87:24] wire _out_T_8713 = ~out_wimask_889; // @[RegisterRouter.scala:87:24] wire _out_T_8714 = ~out_romask_889; // @[RegisterRouter.scala:87:24] wire _out_T_8715 = ~out_womask_889; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_758 = {hi_901, flags_0_go, _out_prepend_T_758}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8716 = out_prepend_758; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8717 = _out_T_8716; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_759 = _out_T_8717; // @[RegisterRouter.scala:87:24] wire out_rimask_890 = |_out_rimask_T_890; // @[RegisterRouter.scala:87:24] wire out_wimask_890 = &_out_wimask_T_890; // @[RegisterRouter.scala:87:24] wire out_romask_890 = |_out_romask_T_890; // @[RegisterRouter.scala:87:24] wire out_womask_890 = &_out_womask_T_890; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_890 = out_rivalid_1_744 & out_rimask_890; // @[RegisterRouter.scala:87:24] wire _out_T_8719 = out_f_rivalid_890; // @[RegisterRouter.scala:87:24] wire out_f_roready_890 = out_roready_1_744 & out_romask_890; // @[RegisterRouter.scala:87:24] wire _out_T_8720 = out_f_roready_890; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_890 = out_wivalid_1_744 & out_wimask_890; // @[RegisterRouter.scala:87:24] wire out_f_woready_890 = out_woready_1_744 & out_womask_890; // @[RegisterRouter.scala:87:24] wire _out_T_8721 = ~out_rimask_890; // @[RegisterRouter.scala:87:24] wire _out_T_8722 = ~out_wimask_890; // @[RegisterRouter.scala:87:24] wire _out_T_8723 = ~out_romask_890; // @[RegisterRouter.scala:87:24] wire _out_T_8724 = ~out_womask_890; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_759 = {hi_902, flags_0_go, _out_prepend_T_759}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8725 = out_prepend_759; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8726 = _out_T_8725; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_760 = _out_T_8726; // @[RegisterRouter.scala:87:24] wire out_rimask_891 = |_out_rimask_T_891; // @[RegisterRouter.scala:87:24] wire out_wimask_891 = &_out_wimask_T_891; // @[RegisterRouter.scala:87:24] wire out_romask_891 = |_out_romask_T_891; // @[RegisterRouter.scala:87:24] wire out_womask_891 = &_out_womask_T_891; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_891 = out_rivalid_1_745 & out_rimask_891; // @[RegisterRouter.scala:87:24] wire _out_T_8728 = out_f_rivalid_891; // @[RegisterRouter.scala:87:24] wire out_f_roready_891 = out_roready_1_745 & out_romask_891; // @[RegisterRouter.scala:87:24] wire _out_T_8729 = out_f_roready_891; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_891 = out_wivalid_1_745 & out_wimask_891; // @[RegisterRouter.scala:87:24] wire out_f_woready_891 = out_woready_1_745 & out_womask_891; // @[RegisterRouter.scala:87:24] wire _out_T_8730 = ~out_rimask_891; // @[RegisterRouter.scala:87:24] wire _out_T_8731 = ~out_wimask_891; // @[RegisterRouter.scala:87:24] wire _out_T_8732 = ~out_romask_891; // @[RegisterRouter.scala:87:24] wire _out_T_8733 = ~out_womask_891; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_760 = {hi_903, flags_0_go, _out_prepend_T_760}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8734 = out_prepend_760; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8735 = _out_T_8734; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_761 = _out_T_8735; // @[RegisterRouter.scala:87:24] wire out_rimask_892 = |_out_rimask_T_892; // @[RegisterRouter.scala:87:24] wire out_wimask_892 = &_out_wimask_T_892; // @[RegisterRouter.scala:87:24] wire out_romask_892 = |_out_romask_T_892; // @[RegisterRouter.scala:87:24] wire out_womask_892 = &_out_womask_T_892; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_892 = out_rivalid_1_746 & out_rimask_892; // @[RegisterRouter.scala:87:24] wire _out_T_8737 = out_f_rivalid_892; // @[RegisterRouter.scala:87:24] wire out_f_roready_892 = out_roready_1_746 & out_romask_892; // @[RegisterRouter.scala:87:24] wire _out_T_8738 = out_f_roready_892; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_892 = out_wivalid_1_746 & out_wimask_892; // @[RegisterRouter.scala:87:24] wire out_f_woready_892 = out_woready_1_746 & out_womask_892; // @[RegisterRouter.scala:87:24] wire _out_T_8739 = ~out_rimask_892; // @[RegisterRouter.scala:87:24] wire _out_T_8740 = ~out_wimask_892; // @[RegisterRouter.scala:87:24] wire _out_T_8741 = ~out_romask_892; // @[RegisterRouter.scala:87:24] wire _out_T_8742 = ~out_womask_892; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_761 = {hi_904, flags_0_go, _out_prepend_T_761}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8743 = out_prepend_761; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8744 = _out_T_8743; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_240 = _out_T_8744; // @[MuxLiteral.scala:49:48] wire out_rimask_893 = |_out_rimask_T_893; // @[RegisterRouter.scala:87:24] wire out_wimask_893 = &_out_wimask_T_893; // @[RegisterRouter.scala:87:24] wire out_romask_893 = |_out_romask_T_893; // @[RegisterRouter.scala:87:24] wire out_womask_893 = &_out_womask_T_893; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_893 = out_rivalid_1_747 & out_rimask_893; // @[RegisterRouter.scala:87:24] wire _out_T_8746 = out_f_rivalid_893; // @[RegisterRouter.scala:87:24] wire out_f_roready_893 = out_roready_1_747 & out_romask_893; // @[RegisterRouter.scala:87:24] wire _out_T_8747 = out_f_roready_893; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_893 = out_wivalid_1_747 & out_wimask_893; // @[RegisterRouter.scala:87:24] wire out_f_woready_893 = out_woready_1_747 & out_womask_893; // @[RegisterRouter.scala:87:24] wire _out_T_8748 = ~out_rimask_893; // @[RegisterRouter.scala:87:24] wire _out_T_8749 = ~out_wimask_893; // @[RegisterRouter.scala:87:24] wire _out_T_8750 = ~out_romask_893; // @[RegisterRouter.scala:87:24] wire _out_T_8751 = ~out_womask_893; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8753 = _out_T_8752; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_762 = _out_T_8753; // @[RegisterRouter.scala:87:24] wire out_rimask_894 = |_out_rimask_T_894; // @[RegisterRouter.scala:87:24] wire out_wimask_894 = &_out_wimask_T_894; // @[RegisterRouter.scala:87:24] wire out_romask_894 = |_out_romask_T_894; // @[RegisterRouter.scala:87:24] wire out_womask_894 = &_out_womask_T_894; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_894 = out_rivalid_1_748 & out_rimask_894; // @[RegisterRouter.scala:87:24] wire _out_T_8755 = out_f_rivalid_894; // @[RegisterRouter.scala:87:24] wire out_f_roready_894 = out_roready_1_748 & out_romask_894; // @[RegisterRouter.scala:87:24] wire _out_T_8756 = out_f_roready_894; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_894 = out_wivalid_1_748 & out_wimask_894; // @[RegisterRouter.scala:87:24] wire out_f_woready_894 = out_woready_1_748 & out_womask_894; // @[RegisterRouter.scala:87:24] wire _out_T_8757 = ~out_rimask_894; // @[RegisterRouter.scala:87:24] wire _out_T_8758 = ~out_wimask_894; // @[RegisterRouter.scala:87:24] wire _out_T_8759 = ~out_romask_894; // @[RegisterRouter.scala:87:24] wire _out_T_8760 = ~out_womask_894; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_762 = {hi_986, flags_0_go, _out_prepend_T_762}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8761 = out_prepend_762; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8762 = _out_T_8761; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_763 = _out_T_8762; // @[RegisterRouter.scala:87:24] wire out_rimask_895 = |_out_rimask_T_895; // @[RegisterRouter.scala:87:24] wire out_wimask_895 = &_out_wimask_T_895; // @[RegisterRouter.scala:87:24] wire out_romask_895 = |_out_romask_T_895; // @[RegisterRouter.scala:87:24] wire out_womask_895 = &_out_womask_T_895; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_895 = out_rivalid_1_749 & out_rimask_895; // @[RegisterRouter.scala:87:24] wire _out_T_8764 = out_f_rivalid_895; // @[RegisterRouter.scala:87:24] wire out_f_roready_895 = out_roready_1_749 & out_romask_895; // @[RegisterRouter.scala:87:24] wire _out_T_8765 = out_f_roready_895; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_895 = out_wivalid_1_749 & out_wimask_895; // @[RegisterRouter.scala:87:24] wire out_f_woready_895 = out_woready_1_749 & out_womask_895; // @[RegisterRouter.scala:87:24] wire _out_T_8766 = ~out_rimask_895; // @[RegisterRouter.scala:87:24] wire _out_T_8767 = ~out_wimask_895; // @[RegisterRouter.scala:87:24] wire _out_T_8768 = ~out_romask_895; // @[RegisterRouter.scala:87:24] wire _out_T_8769 = ~out_womask_895; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_763 = {hi_987, flags_0_go, _out_prepend_T_763}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8770 = out_prepend_763; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8771 = _out_T_8770; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_764 = _out_T_8771; // @[RegisterRouter.scala:87:24] wire out_rimask_896 = |_out_rimask_T_896; // @[RegisterRouter.scala:87:24] wire out_wimask_896 = &_out_wimask_T_896; // @[RegisterRouter.scala:87:24] wire out_romask_896 = |_out_romask_T_896; // @[RegisterRouter.scala:87:24] wire out_womask_896 = &_out_womask_T_896; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_896 = out_rivalid_1_750 & out_rimask_896; // @[RegisterRouter.scala:87:24] wire _out_T_8773 = out_f_rivalid_896; // @[RegisterRouter.scala:87:24] wire out_f_roready_896 = out_roready_1_750 & out_romask_896; // @[RegisterRouter.scala:87:24] wire _out_T_8774 = out_f_roready_896; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_896 = out_wivalid_1_750 & out_wimask_896; // @[RegisterRouter.scala:87:24] wire out_f_woready_896 = out_woready_1_750 & out_womask_896; // @[RegisterRouter.scala:87:24] wire _out_T_8775 = ~out_rimask_896; // @[RegisterRouter.scala:87:24] wire _out_T_8776 = ~out_wimask_896; // @[RegisterRouter.scala:87:24] wire _out_T_8777 = ~out_romask_896; // @[RegisterRouter.scala:87:24] wire _out_T_8778 = ~out_womask_896; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_764 = {hi_988, flags_0_go, _out_prepend_T_764}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8779 = out_prepend_764; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8780 = _out_T_8779; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_765 = _out_T_8780; // @[RegisterRouter.scala:87:24] wire out_rimask_897 = |_out_rimask_T_897; // @[RegisterRouter.scala:87:24] wire out_wimask_897 = &_out_wimask_T_897; // @[RegisterRouter.scala:87:24] wire out_romask_897 = |_out_romask_T_897; // @[RegisterRouter.scala:87:24] wire out_womask_897 = &_out_womask_T_897; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_897 = out_rivalid_1_751 & out_rimask_897; // @[RegisterRouter.scala:87:24] wire _out_T_8782 = out_f_rivalid_897; // @[RegisterRouter.scala:87:24] wire out_f_roready_897 = out_roready_1_751 & out_romask_897; // @[RegisterRouter.scala:87:24] wire _out_T_8783 = out_f_roready_897; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_897 = out_wivalid_1_751 & out_wimask_897; // @[RegisterRouter.scala:87:24] wire out_f_woready_897 = out_woready_1_751 & out_womask_897; // @[RegisterRouter.scala:87:24] wire _out_T_8784 = ~out_rimask_897; // @[RegisterRouter.scala:87:24] wire _out_T_8785 = ~out_wimask_897; // @[RegisterRouter.scala:87:24] wire _out_T_8786 = ~out_romask_897; // @[RegisterRouter.scala:87:24] wire _out_T_8787 = ~out_womask_897; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_765 = {hi_989, flags_0_go, _out_prepend_T_765}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8788 = out_prepend_765; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8789 = _out_T_8788; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_766 = _out_T_8789; // @[RegisterRouter.scala:87:24] wire out_rimask_898 = |_out_rimask_T_898; // @[RegisterRouter.scala:87:24] wire out_wimask_898 = &_out_wimask_T_898; // @[RegisterRouter.scala:87:24] wire out_romask_898 = |_out_romask_T_898; // @[RegisterRouter.scala:87:24] wire out_womask_898 = &_out_womask_T_898; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_898 = out_rivalid_1_752 & out_rimask_898; // @[RegisterRouter.scala:87:24] wire _out_T_8791 = out_f_rivalid_898; // @[RegisterRouter.scala:87:24] wire out_f_roready_898 = out_roready_1_752 & out_romask_898; // @[RegisterRouter.scala:87:24] wire _out_T_8792 = out_f_roready_898; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_898 = out_wivalid_1_752 & out_wimask_898; // @[RegisterRouter.scala:87:24] wire out_f_woready_898 = out_woready_1_752 & out_womask_898; // @[RegisterRouter.scala:87:24] wire _out_T_8793 = ~out_rimask_898; // @[RegisterRouter.scala:87:24] wire _out_T_8794 = ~out_wimask_898; // @[RegisterRouter.scala:87:24] wire _out_T_8795 = ~out_romask_898; // @[RegisterRouter.scala:87:24] wire _out_T_8796 = ~out_womask_898; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_766 = {hi_990, flags_0_go, _out_prepend_T_766}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8797 = out_prepend_766; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8798 = _out_T_8797; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_767 = _out_T_8798; // @[RegisterRouter.scala:87:24] wire out_rimask_899 = |_out_rimask_T_899; // @[RegisterRouter.scala:87:24] wire out_wimask_899 = &_out_wimask_T_899; // @[RegisterRouter.scala:87:24] wire out_romask_899 = |_out_romask_T_899; // @[RegisterRouter.scala:87:24] wire out_womask_899 = &_out_womask_T_899; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_899 = out_rivalid_1_753 & out_rimask_899; // @[RegisterRouter.scala:87:24] wire _out_T_8800 = out_f_rivalid_899; // @[RegisterRouter.scala:87:24] wire out_f_roready_899 = out_roready_1_753 & out_romask_899; // @[RegisterRouter.scala:87:24] wire _out_T_8801 = out_f_roready_899; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_899 = out_wivalid_1_753 & out_wimask_899; // @[RegisterRouter.scala:87:24] wire out_f_woready_899 = out_woready_1_753 & out_womask_899; // @[RegisterRouter.scala:87:24] wire _out_T_8802 = ~out_rimask_899; // @[RegisterRouter.scala:87:24] wire _out_T_8803 = ~out_wimask_899; // @[RegisterRouter.scala:87:24] wire _out_T_8804 = ~out_romask_899; // @[RegisterRouter.scala:87:24] wire _out_T_8805 = ~out_womask_899; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_767 = {hi_991, flags_0_go, _out_prepend_T_767}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8806 = out_prepend_767; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8807 = _out_T_8806; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_768 = _out_T_8807; // @[RegisterRouter.scala:87:24] wire out_rimask_900 = |_out_rimask_T_900; // @[RegisterRouter.scala:87:24] wire out_wimask_900 = &_out_wimask_T_900; // @[RegisterRouter.scala:87:24] wire out_romask_900 = |_out_romask_T_900; // @[RegisterRouter.scala:87:24] wire out_womask_900 = &_out_womask_T_900; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_900 = out_rivalid_1_754 & out_rimask_900; // @[RegisterRouter.scala:87:24] wire _out_T_8809 = out_f_rivalid_900; // @[RegisterRouter.scala:87:24] wire out_f_roready_900 = out_roready_1_754 & out_romask_900; // @[RegisterRouter.scala:87:24] wire _out_T_8810 = out_f_roready_900; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_900 = out_wivalid_1_754 & out_wimask_900; // @[RegisterRouter.scala:87:24] wire out_f_woready_900 = out_woready_1_754 & out_womask_900; // @[RegisterRouter.scala:87:24] wire _out_T_8811 = ~out_rimask_900; // @[RegisterRouter.scala:87:24] wire _out_T_8812 = ~out_wimask_900; // @[RegisterRouter.scala:87:24] wire _out_T_8813 = ~out_romask_900; // @[RegisterRouter.scala:87:24] wire _out_T_8814 = ~out_womask_900; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_768 = {hi_992, flags_0_go, _out_prepend_T_768}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8815 = out_prepend_768; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8816 = _out_T_8815; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_251 = _out_T_8816; // @[MuxLiteral.scala:49:48] wire out_rimask_901 = |_out_rimask_T_901; // @[RegisterRouter.scala:87:24] wire out_wimask_901 = &_out_wimask_T_901; // @[RegisterRouter.scala:87:24] wire out_romask_901 = |_out_romask_T_901; // @[RegisterRouter.scala:87:24] wire out_womask_901 = &_out_womask_T_901; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_901 = out_rivalid_1_755 & out_rimask_901; // @[RegisterRouter.scala:87:24] wire _out_T_8818 = out_f_rivalid_901; // @[RegisterRouter.scala:87:24] wire out_f_roready_901 = out_roready_1_755 & out_romask_901; // @[RegisterRouter.scala:87:24] wire _out_T_8819 = out_f_roready_901; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_901 = out_wivalid_1_755 & out_wimask_901; // @[RegisterRouter.scala:87:24] wire out_f_woready_901 = out_woready_1_755 & out_womask_901; // @[RegisterRouter.scala:87:24] wire _out_T_8820 = ~out_rimask_901; // @[RegisterRouter.scala:87:24] wire _out_T_8821 = ~out_wimask_901; // @[RegisterRouter.scala:87:24] wire _out_T_8822 = ~out_romask_901; // @[RegisterRouter.scala:87:24] wire _out_T_8823 = ~out_womask_901; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8825 = _out_T_8824; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_769 = _out_T_8825; // @[RegisterRouter.scala:87:24] wire out_rimask_902 = |_out_rimask_T_902; // @[RegisterRouter.scala:87:24] wire out_wimask_902 = &_out_wimask_T_902; // @[RegisterRouter.scala:87:24] wire out_romask_902 = |_out_romask_T_902; // @[RegisterRouter.scala:87:24] wire out_womask_902 = &_out_womask_T_902; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_902 = out_rivalid_1_756 & out_rimask_902; // @[RegisterRouter.scala:87:24] wire _out_T_8827 = out_f_rivalid_902; // @[RegisterRouter.scala:87:24] wire out_f_roready_902 = out_roready_1_756 & out_romask_902; // @[RegisterRouter.scala:87:24] wire _out_T_8828 = out_f_roready_902; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_902 = out_wivalid_1_756 & out_wimask_902; // @[RegisterRouter.scala:87:24] wire out_f_woready_902 = out_woready_1_756 & out_womask_902; // @[RegisterRouter.scala:87:24] wire _out_T_8829 = ~out_rimask_902; // @[RegisterRouter.scala:87:24] wire _out_T_8830 = ~out_wimask_902; // @[RegisterRouter.scala:87:24] wire _out_T_8831 = ~out_romask_902; // @[RegisterRouter.scala:87:24] wire _out_T_8832 = ~out_womask_902; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_769 = {hi_18, flags_0_go, _out_prepend_T_769}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8833 = out_prepend_769; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8834 = _out_T_8833; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_770 = _out_T_8834; // @[RegisterRouter.scala:87:24] wire out_rimask_903 = |_out_rimask_T_903; // @[RegisterRouter.scala:87:24] wire out_wimask_903 = &_out_wimask_T_903; // @[RegisterRouter.scala:87:24] wire out_romask_903 = |_out_romask_T_903; // @[RegisterRouter.scala:87:24] wire out_womask_903 = &_out_womask_T_903; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_903 = out_rivalid_1_757 & out_rimask_903; // @[RegisterRouter.scala:87:24] wire _out_T_8836 = out_f_rivalid_903; // @[RegisterRouter.scala:87:24] wire out_f_roready_903 = out_roready_1_757 & out_romask_903; // @[RegisterRouter.scala:87:24] wire _out_T_8837 = out_f_roready_903; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_903 = out_wivalid_1_757 & out_wimask_903; // @[RegisterRouter.scala:87:24] wire out_f_woready_903 = out_woready_1_757 & out_womask_903; // @[RegisterRouter.scala:87:24] wire _out_T_8838 = ~out_rimask_903; // @[RegisterRouter.scala:87:24] wire _out_T_8839 = ~out_wimask_903; // @[RegisterRouter.scala:87:24] wire _out_T_8840 = ~out_romask_903; // @[RegisterRouter.scala:87:24] wire _out_T_8841 = ~out_womask_903; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_770 = {hi_19, flags_0_go, _out_prepend_T_770}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8842 = out_prepend_770; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8843 = _out_T_8842; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_771 = _out_T_8843; // @[RegisterRouter.scala:87:24] wire out_rimask_904 = |_out_rimask_T_904; // @[RegisterRouter.scala:87:24] wire out_wimask_904 = &_out_wimask_T_904; // @[RegisterRouter.scala:87:24] wire out_romask_904 = |_out_romask_T_904; // @[RegisterRouter.scala:87:24] wire out_womask_904 = &_out_womask_T_904; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_904 = out_rivalid_1_758 & out_rimask_904; // @[RegisterRouter.scala:87:24] wire _out_T_8845 = out_f_rivalid_904; // @[RegisterRouter.scala:87:24] wire out_f_roready_904 = out_roready_1_758 & out_romask_904; // @[RegisterRouter.scala:87:24] wire _out_T_8846 = out_f_roready_904; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_904 = out_wivalid_1_758 & out_wimask_904; // @[RegisterRouter.scala:87:24] wire out_f_woready_904 = out_woready_1_758 & out_womask_904; // @[RegisterRouter.scala:87:24] wire _out_T_8847 = ~out_rimask_904; // @[RegisterRouter.scala:87:24] wire _out_T_8848 = ~out_wimask_904; // @[RegisterRouter.scala:87:24] wire _out_T_8849 = ~out_romask_904; // @[RegisterRouter.scala:87:24] wire _out_T_8850 = ~out_womask_904; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_771 = {hi_20, flags_0_go, _out_prepend_T_771}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8851 = out_prepend_771; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8852 = _out_T_8851; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_772 = _out_T_8852; // @[RegisterRouter.scala:87:24] wire out_rimask_905 = |_out_rimask_T_905; // @[RegisterRouter.scala:87:24] wire out_wimask_905 = &_out_wimask_T_905; // @[RegisterRouter.scala:87:24] wire out_romask_905 = |_out_romask_T_905; // @[RegisterRouter.scala:87:24] wire out_womask_905 = &_out_womask_T_905; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_905 = out_rivalid_1_759 & out_rimask_905; // @[RegisterRouter.scala:87:24] wire _out_T_8854 = out_f_rivalid_905; // @[RegisterRouter.scala:87:24] wire out_f_roready_905 = out_roready_1_759 & out_romask_905; // @[RegisterRouter.scala:87:24] wire _out_T_8855 = out_f_roready_905; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_905 = out_wivalid_1_759 & out_wimask_905; // @[RegisterRouter.scala:87:24] wire out_f_woready_905 = out_woready_1_759 & out_womask_905; // @[RegisterRouter.scala:87:24] wire _out_T_8856 = ~out_rimask_905; // @[RegisterRouter.scala:87:24] wire _out_T_8857 = ~out_wimask_905; // @[RegisterRouter.scala:87:24] wire _out_T_8858 = ~out_romask_905; // @[RegisterRouter.scala:87:24] wire _out_T_8859 = ~out_womask_905; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_772 = {hi_21, flags_0_go, _out_prepend_T_772}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8860 = out_prepend_772; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8861 = _out_T_8860; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_773 = _out_T_8861; // @[RegisterRouter.scala:87:24] wire out_rimask_906 = |_out_rimask_T_906; // @[RegisterRouter.scala:87:24] wire out_wimask_906 = &_out_wimask_T_906; // @[RegisterRouter.scala:87:24] wire out_romask_906 = |_out_romask_T_906; // @[RegisterRouter.scala:87:24] wire out_womask_906 = &_out_womask_T_906; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_906 = out_rivalid_1_760 & out_rimask_906; // @[RegisterRouter.scala:87:24] wire _out_T_8863 = out_f_rivalid_906; // @[RegisterRouter.scala:87:24] wire out_f_roready_906 = out_roready_1_760 & out_romask_906; // @[RegisterRouter.scala:87:24] wire _out_T_8864 = out_f_roready_906; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_906 = out_wivalid_1_760 & out_wimask_906; // @[RegisterRouter.scala:87:24] wire out_f_woready_906 = out_woready_1_760 & out_womask_906; // @[RegisterRouter.scala:87:24] wire _out_T_8865 = ~out_rimask_906; // @[RegisterRouter.scala:87:24] wire _out_T_8866 = ~out_wimask_906; // @[RegisterRouter.scala:87:24] wire _out_T_8867 = ~out_romask_906; // @[RegisterRouter.scala:87:24] wire _out_T_8868 = ~out_womask_906; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_773 = {hi_22, flags_0_go, _out_prepend_T_773}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8869 = out_prepend_773; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8870 = _out_T_8869; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_774 = _out_T_8870; // @[RegisterRouter.scala:87:24] wire out_rimask_907 = |_out_rimask_T_907; // @[RegisterRouter.scala:87:24] wire out_wimask_907 = &_out_wimask_T_907; // @[RegisterRouter.scala:87:24] wire out_romask_907 = |_out_romask_T_907; // @[RegisterRouter.scala:87:24] wire out_womask_907 = &_out_womask_T_907; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_907 = out_rivalid_1_761 & out_rimask_907; // @[RegisterRouter.scala:87:24] wire _out_T_8872 = out_f_rivalid_907; // @[RegisterRouter.scala:87:24] wire out_f_roready_907 = out_roready_1_761 & out_romask_907; // @[RegisterRouter.scala:87:24] wire _out_T_8873 = out_f_roready_907; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_907 = out_wivalid_1_761 & out_wimask_907; // @[RegisterRouter.scala:87:24] wire out_f_woready_907 = out_woready_1_761 & out_womask_907; // @[RegisterRouter.scala:87:24] wire _out_T_8874 = ~out_rimask_907; // @[RegisterRouter.scala:87:24] wire _out_T_8875 = ~out_wimask_907; // @[RegisterRouter.scala:87:24] wire _out_T_8876 = ~out_romask_907; // @[RegisterRouter.scala:87:24] wire _out_T_8877 = ~out_womask_907; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_774 = {hi_23, flags_0_go, _out_prepend_T_774}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8878 = out_prepend_774; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8879 = _out_T_8878; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_775 = _out_T_8879; // @[RegisterRouter.scala:87:24] wire out_rimask_908 = |_out_rimask_T_908; // @[RegisterRouter.scala:87:24] wire out_wimask_908 = &_out_wimask_T_908; // @[RegisterRouter.scala:87:24] wire out_romask_908 = |_out_romask_T_908; // @[RegisterRouter.scala:87:24] wire out_womask_908 = &_out_womask_T_908; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_908 = out_rivalid_1_762 & out_rimask_908; // @[RegisterRouter.scala:87:24] wire _out_T_8881 = out_f_rivalid_908; // @[RegisterRouter.scala:87:24] wire out_f_roready_908 = out_roready_1_762 & out_romask_908; // @[RegisterRouter.scala:87:24] wire _out_T_8882 = out_f_roready_908; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_908 = out_wivalid_1_762 & out_wimask_908; // @[RegisterRouter.scala:87:24] wire out_f_woready_908 = out_woready_1_762 & out_womask_908; // @[RegisterRouter.scala:87:24] wire _out_T_8883 = ~out_rimask_908; // @[RegisterRouter.scala:87:24] wire _out_T_8884 = ~out_wimask_908; // @[RegisterRouter.scala:87:24] wire _out_T_8885 = ~out_romask_908; // @[RegisterRouter.scala:87:24] wire _out_T_8886 = ~out_womask_908; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_775 = {hi_24, flags_0_go, _out_prepend_T_775}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8887 = out_prepend_775; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8888 = _out_T_8887; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_130 = _out_T_8888; // @[MuxLiteral.scala:49:48] wire out_rimask_909 = |_out_rimask_T_909; // @[RegisterRouter.scala:87:24] wire out_wimask_909 = &_out_wimask_T_909; // @[RegisterRouter.scala:87:24] wire out_romask_909 = |_out_romask_T_909; // @[RegisterRouter.scala:87:24] wire out_womask_909 = &_out_womask_T_909; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_909 = out_rivalid_1_763 & out_rimask_909; // @[RegisterRouter.scala:87:24] wire _out_T_8890 = out_f_rivalid_909; // @[RegisterRouter.scala:87:24] wire out_f_roready_909 = out_roready_1_763 & out_romask_909; // @[RegisterRouter.scala:87:24] wire _out_T_8891 = out_f_roready_909; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_909 = out_wivalid_1_763 & out_wimask_909; // @[RegisterRouter.scala:87:24] wire out_f_woready_909 = out_woready_1_763 & out_womask_909; // @[RegisterRouter.scala:87:24] wire _out_T_8892 = ~out_rimask_909; // @[RegisterRouter.scala:87:24] wire _out_T_8893 = ~out_wimask_909; // @[RegisterRouter.scala:87:24] wire _out_T_8894 = ~out_romask_909; // @[RegisterRouter.scala:87:24] wire _out_T_8895 = ~out_womask_909; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8897 = _out_T_8896; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_776 = _out_T_8897; // @[RegisterRouter.scala:87:24] wire out_rimask_910 = |_out_rimask_T_910; // @[RegisterRouter.scala:87:24] wire out_wimask_910 = &_out_wimask_T_910; // @[RegisterRouter.scala:87:24] wire out_romask_910 = |_out_romask_T_910; // @[RegisterRouter.scala:87:24] wire out_womask_910 = &_out_womask_T_910; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_910 = out_rivalid_1_764 & out_rimask_910; // @[RegisterRouter.scala:87:24] wire _out_T_8899 = out_f_rivalid_910; // @[RegisterRouter.scala:87:24] wire out_f_roready_910 = out_roready_1_764 & out_romask_910; // @[RegisterRouter.scala:87:24] wire _out_T_8900 = out_f_roready_910; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_910 = out_wivalid_1_764 & out_wimask_910; // @[RegisterRouter.scala:87:24] wire out_f_woready_910 = out_woready_1_764 & out_womask_910; // @[RegisterRouter.scala:87:24] wire _out_T_8901 = ~out_rimask_910; // @[RegisterRouter.scala:87:24] wire _out_T_8902 = ~out_wimask_910; // @[RegisterRouter.scala:87:24] wire _out_T_8903 = ~out_romask_910; // @[RegisterRouter.scala:87:24] wire _out_T_8904 = ~out_womask_910; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_776 = {hi_762, flags_0_go, _out_prepend_T_776}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8905 = out_prepend_776; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8906 = _out_T_8905; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_777 = _out_T_8906; // @[RegisterRouter.scala:87:24] wire out_rimask_911 = |_out_rimask_T_911; // @[RegisterRouter.scala:87:24] wire out_wimask_911 = &_out_wimask_T_911; // @[RegisterRouter.scala:87:24] wire out_romask_911 = |_out_romask_T_911; // @[RegisterRouter.scala:87:24] wire out_womask_911 = &_out_womask_T_911; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_911 = out_rivalid_1_765 & out_rimask_911; // @[RegisterRouter.scala:87:24] wire _out_T_8908 = out_f_rivalid_911; // @[RegisterRouter.scala:87:24] wire out_f_roready_911 = out_roready_1_765 & out_romask_911; // @[RegisterRouter.scala:87:24] wire _out_T_8909 = out_f_roready_911; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_911 = out_wivalid_1_765 & out_wimask_911; // @[RegisterRouter.scala:87:24] wire out_f_woready_911 = out_woready_1_765 & out_womask_911; // @[RegisterRouter.scala:87:24] wire _out_T_8910 = ~out_rimask_911; // @[RegisterRouter.scala:87:24] wire _out_T_8911 = ~out_wimask_911; // @[RegisterRouter.scala:87:24] wire _out_T_8912 = ~out_romask_911; // @[RegisterRouter.scala:87:24] wire _out_T_8913 = ~out_womask_911; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_777 = {hi_763, flags_0_go, _out_prepend_T_777}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8914 = out_prepend_777; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8915 = _out_T_8914; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_778 = _out_T_8915; // @[RegisterRouter.scala:87:24] wire out_rimask_912 = |_out_rimask_T_912; // @[RegisterRouter.scala:87:24] wire out_wimask_912 = &_out_wimask_T_912; // @[RegisterRouter.scala:87:24] wire out_romask_912 = |_out_romask_T_912; // @[RegisterRouter.scala:87:24] wire out_womask_912 = &_out_womask_T_912; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_912 = out_rivalid_1_766 & out_rimask_912; // @[RegisterRouter.scala:87:24] wire _out_T_8917 = out_f_rivalid_912; // @[RegisterRouter.scala:87:24] wire out_f_roready_912 = out_roready_1_766 & out_romask_912; // @[RegisterRouter.scala:87:24] wire _out_T_8918 = out_f_roready_912; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_912 = out_wivalid_1_766 & out_wimask_912; // @[RegisterRouter.scala:87:24] wire out_f_woready_912 = out_woready_1_766 & out_womask_912; // @[RegisterRouter.scala:87:24] wire _out_T_8919 = ~out_rimask_912; // @[RegisterRouter.scala:87:24] wire _out_T_8920 = ~out_wimask_912; // @[RegisterRouter.scala:87:24] wire _out_T_8921 = ~out_romask_912; // @[RegisterRouter.scala:87:24] wire _out_T_8922 = ~out_womask_912; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_778 = {hi_764, flags_0_go, _out_prepend_T_778}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8923 = out_prepend_778; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8924 = _out_T_8923; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_779 = _out_T_8924; // @[RegisterRouter.scala:87:24] wire out_rimask_913 = |_out_rimask_T_913; // @[RegisterRouter.scala:87:24] wire out_wimask_913 = &_out_wimask_T_913; // @[RegisterRouter.scala:87:24] wire out_romask_913 = |_out_romask_T_913; // @[RegisterRouter.scala:87:24] wire out_womask_913 = &_out_womask_T_913; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_913 = out_rivalid_1_767 & out_rimask_913; // @[RegisterRouter.scala:87:24] wire _out_T_8926 = out_f_rivalid_913; // @[RegisterRouter.scala:87:24] wire out_f_roready_913 = out_roready_1_767 & out_romask_913; // @[RegisterRouter.scala:87:24] wire _out_T_8927 = out_f_roready_913; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_913 = out_wivalid_1_767 & out_wimask_913; // @[RegisterRouter.scala:87:24] wire out_f_woready_913 = out_woready_1_767 & out_womask_913; // @[RegisterRouter.scala:87:24] wire _out_T_8928 = ~out_rimask_913; // @[RegisterRouter.scala:87:24] wire _out_T_8929 = ~out_wimask_913; // @[RegisterRouter.scala:87:24] wire _out_T_8930 = ~out_romask_913; // @[RegisterRouter.scala:87:24] wire _out_T_8931 = ~out_womask_913; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_779 = {hi_765, flags_0_go, _out_prepend_T_779}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8932 = out_prepend_779; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8933 = _out_T_8932; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_780 = _out_T_8933; // @[RegisterRouter.scala:87:24] wire out_rimask_914 = |_out_rimask_T_914; // @[RegisterRouter.scala:87:24] wire out_wimask_914 = &_out_wimask_T_914; // @[RegisterRouter.scala:87:24] wire out_romask_914 = |_out_romask_T_914; // @[RegisterRouter.scala:87:24] wire out_womask_914 = &_out_womask_T_914; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_914 = out_rivalid_1_768 & out_rimask_914; // @[RegisterRouter.scala:87:24] wire _out_T_8935 = out_f_rivalid_914; // @[RegisterRouter.scala:87:24] wire out_f_roready_914 = out_roready_1_768 & out_romask_914; // @[RegisterRouter.scala:87:24] wire _out_T_8936 = out_f_roready_914; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_914 = out_wivalid_1_768 & out_wimask_914; // @[RegisterRouter.scala:87:24] wire out_f_woready_914 = out_woready_1_768 & out_womask_914; // @[RegisterRouter.scala:87:24] wire _out_T_8937 = ~out_rimask_914; // @[RegisterRouter.scala:87:24] wire _out_T_8938 = ~out_wimask_914; // @[RegisterRouter.scala:87:24] wire _out_T_8939 = ~out_romask_914; // @[RegisterRouter.scala:87:24] wire _out_T_8940 = ~out_womask_914; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_780 = {hi_766, flags_0_go, _out_prepend_T_780}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8941 = out_prepend_780; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8942 = _out_T_8941; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_781 = _out_T_8942; // @[RegisterRouter.scala:87:24] wire out_rimask_915 = |_out_rimask_T_915; // @[RegisterRouter.scala:87:24] wire out_wimask_915 = &_out_wimask_T_915; // @[RegisterRouter.scala:87:24] wire out_romask_915 = |_out_romask_T_915; // @[RegisterRouter.scala:87:24] wire out_womask_915 = &_out_womask_T_915; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_915 = out_rivalid_1_769 & out_rimask_915; // @[RegisterRouter.scala:87:24] wire _out_T_8944 = out_f_rivalid_915; // @[RegisterRouter.scala:87:24] wire out_f_roready_915 = out_roready_1_769 & out_romask_915; // @[RegisterRouter.scala:87:24] wire _out_T_8945 = out_f_roready_915; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_915 = out_wivalid_1_769 & out_wimask_915; // @[RegisterRouter.scala:87:24] wire out_f_woready_915 = out_woready_1_769 & out_womask_915; // @[RegisterRouter.scala:87:24] wire _out_T_8946 = ~out_rimask_915; // @[RegisterRouter.scala:87:24] wire _out_T_8947 = ~out_wimask_915; // @[RegisterRouter.scala:87:24] wire _out_T_8948 = ~out_romask_915; // @[RegisterRouter.scala:87:24] wire _out_T_8949 = ~out_womask_915; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_781 = {hi_767, flags_0_go, _out_prepend_T_781}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8950 = out_prepend_781; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8951 = _out_T_8950; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_782 = _out_T_8951; // @[RegisterRouter.scala:87:24] wire out_rimask_916 = |_out_rimask_T_916; // @[RegisterRouter.scala:87:24] wire out_wimask_916 = &_out_wimask_T_916; // @[RegisterRouter.scala:87:24] wire out_romask_916 = |_out_romask_T_916; // @[RegisterRouter.scala:87:24] wire out_womask_916 = &_out_womask_T_916; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_916 = out_rivalid_1_770 & out_rimask_916; // @[RegisterRouter.scala:87:24] wire _out_T_8953 = out_f_rivalid_916; // @[RegisterRouter.scala:87:24] wire out_f_roready_916 = out_roready_1_770 & out_romask_916; // @[RegisterRouter.scala:87:24] wire _out_T_8954 = out_f_roready_916; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_916 = out_wivalid_1_770 & out_wimask_916; // @[RegisterRouter.scala:87:24] wire out_f_woready_916 = out_woready_1_770 & out_womask_916; // @[RegisterRouter.scala:87:24] wire _out_T_8955 = ~out_rimask_916; // @[RegisterRouter.scala:87:24] wire _out_T_8956 = ~out_wimask_916; // @[RegisterRouter.scala:87:24] wire _out_T_8957 = ~out_romask_916; // @[RegisterRouter.scala:87:24] wire _out_T_8958 = ~out_womask_916; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_782 = {hi_768, flags_0_go, _out_prepend_T_782}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8959 = out_prepend_782; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8960 = _out_T_8959; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_223 = _out_T_8960; // @[MuxLiteral.scala:49:48] wire out_rimask_917 = |_out_rimask_T_917; // @[RegisterRouter.scala:87:24] wire out_wimask_917 = &_out_wimask_T_917; // @[RegisterRouter.scala:87:24] wire out_romask_917 = |_out_romask_T_917; // @[RegisterRouter.scala:87:24] wire out_womask_917 = &_out_womask_T_917; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_917 = out_rivalid_1_771 & out_rimask_917; // @[RegisterRouter.scala:87:24] wire _out_T_8962 = out_f_rivalid_917; // @[RegisterRouter.scala:87:24] wire out_f_roready_917 = out_roready_1_771 & out_romask_917; // @[RegisterRouter.scala:87:24] wire _out_T_8963 = out_f_roready_917; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_917 = out_wivalid_1_771 & out_wimask_917; // @[RegisterRouter.scala:87:24] wire out_f_woready_917 = out_woready_1_771 & out_womask_917; // @[RegisterRouter.scala:87:24] wire _out_T_8964 = ~out_rimask_917; // @[RegisterRouter.scala:87:24] wire _out_T_8965 = ~out_wimask_917; // @[RegisterRouter.scala:87:24] wire _out_T_8966 = ~out_romask_917; // @[RegisterRouter.scala:87:24] wire _out_T_8967 = ~out_womask_917; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8969 = _out_T_8968; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_783 = _out_T_8969; // @[RegisterRouter.scala:87:24] wire out_rimask_918 = |_out_rimask_T_918; // @[RegisterRouter.scala:87:24] wire out_wimask_918 = &_out_wimask_T_918; // @[RegisterRouter.scala:87:24] wire out_romask_918 = |_out_romask_T_918; // @[RegisterRouter.scala:87:24] wire out_womask_918 = &_out_womask_T_918; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_918 = out_rivalid_1_772 & out_rimask_918; // @[RegisterRouter.scala:87:24] wire _out_T_8971 = out_f_rivalid_918; // @[RegisterRouter.scala:87:24] wire out_f_roready_918 = out_roready_1_772 & out_romask_918; // @[RegisterRouter.scala:87:24] wire _out_T_8972 = out_f_roready_918; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_918 = out_wivalid_1_772 & out_wimask_918; // @[RegisterRouter.scala:87:24] wire out_f_woready_918 = out_woready_1_772 & out_womask_918; // @[RegisterRouter.scala:87:24] wire _out_T_8973 = ~out_rimask_918; // @[RegisterRouter.scala:87:24] wire _out_T_8974 = ~out_wimask_918; // @[RegisterRouter.scala:87:24] wire _out_T_8975 = ~out_romask_918; // @[RegisterRouter.scala:87:24] wire _out_T_8976 = ~out_womask_918; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_783 = {hi_58, flags_0_go, _out_prepend_T_783}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8977 = out_prepend_783; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8978 = _out_T_8977; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_784 = _out_T_8978; // @[RegisterRouter.scala:87:24] wire out_rimask_919 = |_out_rimask_T_919; // @[RegisterRouter.scala:87:24] wire out_wimask_919 = &_out_wimask_T_919; // @[RegisterRouter.scala:87:24] wire out_romask_919 = |_out_romask_T_919; // @[RegisterRouter.scala:87:24] wire out_womask_919 = &_out_womask_T_919; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_919 = out_rivalid_1_773 & out_rimask_919; // @[RegisterRouter.scala:87:24] wire _out_T_8980 = out_f_rivalid_919; // @[RegisterRouter.scala:87:24] wire out_f_roready_919 = out_roready_1_773 & out_romask_919; // @[RegisterRouter.scala:87:24] wire _out_T_8981 = out_f_roready_919; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_919 = out_wivalid_1_773 & out_wimask_919; // @[RegisterRouter.scala:87:24] wire out_f_woready_919 = out_woready_1_773 & out_womask_919; // @[RegisterRouter.scala:87:24] wire _out_T_8982 = ~out_rimask_919; // @[RegisterRouter.scala:87:24] wire _out_T_8983 = ~out_wimask_919; // @[RegisterRouter.scala:87:24] wire _out_T_8984 = ~out_romask_919; // @[RegisterRouter.scala:87:24] wire _out_T_8985 = ~out_womask_919; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_784 = {hi_59, flags_0_go, _out_prepend_T_784}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8986 = out_prepend_784; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8987 = _out_T_8986; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_785 = _out_T_8987; // @[RegisterRouter.scala:87:24] wire out_rimask_920 = |_out_rimask_T_920; // @[RegisterRouter.scala:87:24] wire out_wimask_920 = &_out_wimask_T_920; // @[RegisterRouter.scala:87:24] wire out_romask_920 = |_out_romask_T_920; // @[RegisterRouter.scala:87:24] wire out_womask_920 = &_out_womask_T_920; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_920 = out_rivalid_1_774 & out_rimask_920; // @[RegisterRouter.scala:87:24] wire _out_T_8989 = out_f_rivalid_920; // @[RegisterRouter.scala:87:24] wire out_f_roready_920 = out_roready_1_774 & out_romask_920; // @[RegisterRouter.scala:87:24] wire _out_T_8990 = out_f_roready_920; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_920 = out_wivalid_1_774 & out_wimask_920; // @[RegisterRouter.scala:87:24] wire out_f_woready_920 = out_woready_1_774 & out_womask_920; // @[RegisterRouter.scala:87:24] wire _out_T_8991 = ~out_rimask_920; // @[RegisterRouter.scala:87:24] wire _out_T_8992 = ~out_wimask_920; // @[RegisterRouter.scala:87:24] wire _out_T_8993 = ~out_romask_920; // @[RegisterRouter.scala:87:24] wire _out_T_8994 = ~out_womask_920; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_785 = {hi_60, flags_0_go, _out_prepend_T_785}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8995 = out_prepend_785; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8996 = _out_T_8995; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_786 = _out_T_8996; // @[RegisterRouter.scala:87:24] wire out_rimask_921 = |_out_rimask_T_921; // @[RegisterRouter.scala:87:24] wire out_wimask_921 = &_out_wimask_T_921; // @[RegisterRouter.scala:87:24] wire out_romask_921 = |_out_romask_T_921; // @[RegisterRouter.scala:87:24] wire out_womask_921 = &_out_womask_T_921; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_921 = out_rivalid_1_775 & out_rimask_921; // @[RegisterRouter.scala:87:24] wire _out_T_8998 = out_f_rivalid_921; // @[RegisterRouter.scala:87:24] wire out_f_roready_921 = out_roready_1_775 & out_romask_921; // @[RegisterRouter.scala:87:24] wire _out_T_8999 = out_f_roready_921; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_921 = out_wivalid_1_775 & out_wimask_921; // @[RegisterRouter.scala:87:24] wire out_f_woready_921 = out_woready_1_775 & out_womask_921; // @[RegisterRouter.scala:87:24] wire _out_T_9000 = ~out_rimask_921; // @[RegisterRouter.scala:87:24] wire _out_T_9001 = ~out_wimask_921; // @[RegisterRouter.scala:87:24] wire _out_T_9002 = ~out_romask_921; // @[RegisterRouter.scala:87:24] wire _out_T_9003 = ~out_womask_921; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_786 = {hi_61, flags_0_go, _out_prepend_T_786}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9004 = out_prepend_786; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9005 = _out_T_9004; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_787 = _out_T_9005; // @[RegisterRouter.scala:87:24] wire out_rimask_922 = |_out_rimask_T_922; // @[RegisterRouter.scala:87:24] wire out_wimask_922 = &_out_wimask_T_922; // @[RegisterRouter.scala:87:24] wire out_romask_922 = |_out_romask_T_922; // @[RegisterRouter.scala:87:24] wire out_womask_922 = &_out_womask_T_922; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_922 = out_rivalid_1_776 & out_rimask_922; // @[RegisterRouter.scala:87:24] wire _out_T_9007 = out_f_rivalid_922; // @[RegisterRouter.scala:87:24] wire out_f_roready_922 = out_roready_1_776 & out_romask_922; // @[RegisterRouter.scala:87:24] wire _out_T_9008 = out_f_roready_922; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_922 = out_wivalid_1_776 & out_wimask_922; // @[RegisterRouter.scala:87:24] wire out_f_woready_922 = out_woready_1_776 & out_womask_922; // @[RegisterRouter.scala:87:24] wire _out_T_9009 = ~out_rimask_922; // @[RegisterRouter.scala:87:24] wire _out_T_9010 = ~out_wimask_922; // @[RegisterRouter.scala:87:24] wire _out_T_9011 = ~out_romask_922; // @[RegisterRouter.scala:87:24] wire _out_T_9012 = ~out_womask_922; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_787 = {hi_62, flags_0_go, _out_prepend_T_787}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9013 = out_prepend_787; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9014 = _out_T_9013; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_788 = _out_T_9014; // @[RegisterRouter.scala:87:24] wire out_rimask_923 = |_out_rimask_T_923; // @[RegisterRouter.scala:87:24] wire out_wimask_923 = &_out_wimask_T_923; // @[RegisterRouter.scala:87:24] wire out_romask_923 = |_out_romask_T_923; // @[RegisterRouter.scala:87:24] wire out_womask_923 = &_out_womask_T_923; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_923 = out_rivalid_1_777 & out_rimask_923; // @[RegisterRouter.scala:87:24] wire _out_T_9016 = out_f_rivalid_923; // @[RegisterRouter.scala:87:24] wire out_f_roready_923 = out_roready_1_777 & out_romask_923; // @[RegisterRouter.scala:87:24] wire _out_T_9017 = out_f_roready_923; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_923 = out_wivalid_1_777 & out_wimask_923; // @[RegisterRouter.scala:87:24] wire out_f_woready_923 = out_woready_1_777 & out_womask_923; // @[RegisterRouter.scala:87:24] wire _out_T_9018 = ~out_rimask_923; // @[RegisterRouter.scala:87:24] wire _out_T_9019 = ~out_wimask_923; // @[RegisterRouter.scala:87:24] wire _out_T_9020 = ~out_romask_923; // @[RegisterRouter.scala:87:24] wire _out_T_9021 = ~out_womask_923; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_788 = {hi_63, flags_0_go, _out_prepend_T_788}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9022 = out_prepend_788; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9023 = _out_T_9022; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_789 = _out_T_9023; // @[RegisterRouter.scala:87:24] wire out_rimask_924 = |_out_rimask_T_924; // @[RegisterRouter.scala:87:24] wire out_wimask_924 = &_out_wimask_T_924; // @[RegisterRouter.scala:87:24] wire out_romask_924 = |_out_romask_T_924; // @[RegisterRouter.scala:87:24] wire out_womask_924 = &_out_womask_T_924; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_924 = out_rivalid_1_778 & out_rimask_924; // @[RegisterRouter.scala:87:24] wire _out_T_9025 = out_f_rivalid_924; // @[RegisterRouter.scala:87:24] wire out_f_roready_924 = out_roready_1_778 & out_romask_924; // @[RegisterRouter.scala:87:24] wire _out_T_9026 = out_f_roready_924; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_924 = out_wivalid_1_778 & out_wimask_924; // @[RegisterRouter.scala:87:24] wire out_f_woready_924 = out_woready_1_778 & out_womask_924; // @[RegisterRouter.scala:87:24] wire _out_T_9027 = ~out_rimask_924; // @[RegisterRouter.scala:87:24] wire _out_T_9028 = ~out_wimask_924; // @[RegisterRouter.scala:87:24] wire _out_T_9029 = ~out_romask_924; // @[RegisterRouter.scala:87:24] wire _out_T_9030 = ~out_womask_924; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_789 = {hi_64, flags_0_go, _out_prepend_T_789}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9031 = out_prepend_789; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9032 = _out_T_9031; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_135 = _out_T_9032; // @[MuxLiteral.scala:49:48] wire out_rimask_925 = |_out_rimask_T_925; // @[RegisterRouter.scala:87:24] wire out_wimask_925 = &_out_wimask_T_925; // @[RegisterRouter.scala:87:24] wire out_romask_925 = |_out_romask_T_925; // @[RegisterRouter.scala:87:24] wire out_womask_925 = &_out_womask_T_925; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_925 = out_rivalid_1_779 & out_rimask_925; // @[RegisterRouter.scala:87:24] wire _out_T_9034 = out_f_rivalid_925; // @[RegisterRouter.scala:87:24] wire out_f_roready_925 = out_roready_1_779 & out_romask_925; // @[RegisterRouter.scala:87:24] wire _out_T_9035 = out_f_roready_925; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_925 = out_wivalid_1_779 & out_wimask_925; // @[RegisterRouter.scala:87:24] wire out_f_woready_925 = out_woready_1_779 & out_womask_925; // @[RegisterRouter.scala:87:24] wire _out_T_9036 = ~out_rimask_925; // @[RegisterRouter.scala:87:24] wire _out_T_9037 = ~out_wimask_925; // @[RegisterRouter.scala:87:24] wire _out_T_9038 = ~out_romask_925; // @[RegisterRouter.scala:87:24] wire _out_T_9039 = ~out_womask_925; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9041 = _out_T_9040; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_790 = _out_T_9041; // @[RegisterRouter.scala:87:24] wire out_rimask_926 = |_out_rimask_T_926; // @[RegisterRouter.scala:87:24] wire out_wimask_926 = &_out_wimask_T_926; // @[RegisterRouter.scala:87:24] wire out_romask_926 = |_out_romask_T_926; // @[RegisterRouter.scala:87:24] wire out_womask_926 = &_out_womask_T_926; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_926 = out_rivalid_1_780 & out_rimask_926; // @[RegisterRouter.scala:87:24] wire _out_T_9043 = out_f_rivalid_926; // @[RegisterRouter.scala:87:24] wire out_f_roready_926 = out_roready_1_780 & out_romask_926; // @[RegisterRouter.scala:87:24] wire _out_T_9044 = out_f_roready_926; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_926 = out_wivalid_1_780 & out_wimask_926; // @[RegisterRouter.scala:87:24] wire out_f_woready_926 = out_woready_1_780 & out_womask_926; // @[RegisterRouter.scala:87:24] wire _out_T_9045 = ~out_rimask_926; // @[RegisterRouter.scala:87:24] wire _out_T_9046 = ~out_wimask_926; // @[RegisterRouter.scala:87:24] wire _out_T_9047 = ~out_romask_926; // @[RegisterRouter.scala:87:24] wire _out_T_9048 = ~out_womask_926; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_790 = {hi_786, flags_0_go, _out_prepend_T_790}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9049 = out_prepend_790; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9050 = _out_T_9049; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_791 = _out_T_9050; // @[RegisterRouter.scala:87:24] wire out_rimask_927 = |_out_rimask_T_927; // @[RegisterRouter.scala:87:24] wire out_wimask_927 = &_out_wimask_T_927; // @[RegisterRouter.scala:87:24] wire out_romask_927 = |_out_romask_T_927; // @[RegisterRouter.scala:87:24] wire out_womask_927 = &_out_womask_T_927; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_927 = out_rivalid_1_781 & out_rimask_927; // @[RegisterRouter.scala:87:24] wire _out_T_9052 = out_f_rivalid_927; // @[RegisterRouter.scala:87:24] wire out_f_roready_927 = out_roready_1_781 & out_romask_927; // @[RegisterRouter.scala:87:24] wire _out_T_9053 = out_f_roready_927; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_927 = out_wivalid_1_781 & out_wimask_927; // @[RegisterRouter.scala:87:24] wire out_f_woready_927 = out_woready_1_781 & out_womask_927; // @[RegisterRouter.scala:87:24] wire _out_T_9054 = ~out_rimask_927; // @[RegisterRouter.scala:87:24] wire _out_T_9055 = ~out_wimask_927; // @[RegisterRouter.scala:87:24] wire _out_T_9056 = ~out_romask_927; // @[RegisterRouter.scala:87:24] wire _out_T_9057 = ~out_womask_927; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_791 = {hi_787, flags_0_go, _out_prepend_T_791}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9058 = out_prepend_791; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9059 = _out_T_9058; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_792 = _out_T_9059; // @[RegisterRouter.scala:87:24] wire out_rimask_928 = |_out_rimask_T_928; // @[RegisterRouter.scala:87:24] wire out_wimask_928 = &_out_wimask_T_928; // @[RegisterRouter.scala:87:24] wire out_romask_928 = |_out_romask_T_928; // @[RegisterRouter.scala:87:24] wire out_womask_928 = &_out_womask_T_928; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_928 = out_rivalid_1_782 & out_rimask_928; // @[RegisterRouter.scala:87:24] wire _out_T_9061 = out_f_rivalid_928; // @[RegisterRouter.scala:87:24] wire out_f_roready_928 = out_roready_1_782 & out_romask_928; // @[RegisterRouter.scala:87:24] wire _out_T_9062 = out_f_roready_928; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_928 = out_wivalid_1_782 & out_wimask_928; // @[RegisterRouter.scala:87:24] wire out_f_woready_928 = out_woready_1_782 & out_womask_928; // @[RegisterRouter.scala:87:24] wire _out_T_9063 = ~out_rimask_928; // @[RegisterRouter.scala:87:24] wire _out_T_9064 = ~out_wimask_928; // @[RegisterRouter.scala:87:24] wire _out_T_9065 = ~out_romask_928; // @[RegisterRouter.scala:87:24] wire _out_T_9066 = ~out_womask_928; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_792 = {hi_788, flags_0_go, _out_prepend_T_792}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9067 = out_prepend_792; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9068 = _out_T_9067; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_793 = _out_T_9068; // @[RegisterRouter.scala:87:24] wire out_rimask_929 = |_out_rimask_T_929; // @[RegisterRouter.scala:87:24] wire out_wimask_929 = &_out_wimask_T_929; // @[RegisterRouter.scala:87:24] wire out_romask_929 = |_out_romask_T_929; // @[RegisterRouter.scala:87:24] wire out_womask_929 = &_out_womask_T_929; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_929 = out_rivalid_1_783 & out_rimask_929; // @[RegisterRouter.scala:87:24] wire _out_T_9070 = out_f_rivalid_929; // @[RegisterRouter.scala:87:24] wire out_f_roready_929 = out_roready_1_783 & out_romask_929; // @[RegisterRouter.scala:87:24] wire _out_T_9071 = out_f_roready_929; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_929 = out_wivalid_1_783 & out_wimask_929; // @[RegisterRouter.scala:87:24] wire out_f_woready_929 = out_woready_1_783 & out_womask_929; // @[RegisterRouter.scala:87:24] wire _out_T_9072 = ~out_rimask_929; // @[RegisterRouter.scala:87:24] wire _out_T_9073 = ~out_wimask_929; // @[RegisterRouter.scala:87:24] wire _out_T_9074 = ~out_romask_929; // @[RegisterRouter.scala:87:24] wire _out_T_9075 = ~out_womask_929; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_793 = {hi_789, flags_0_go, _out_prepend_T_793}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9076 = out_prepend_793; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9077 = _out_T_9076; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_794 = _out_T_9077; // @[RegisterRouter.scala:87:24] wire out_rimask_930 = |_out_rimask_T_930; // @[RegisterRouter.scala:87:24] wire out_wimask_930 = &_out_wimask_T_930; // @[RegisterRouter.scala:87:24] wire out_romask_930 = |_out_romask_T_930; // @[RegisterRouter.scala:87:24] wire out_womask_930 = &_out_womask_T_930; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_930 = out_rivalid_1_784 & out_rimask_930; // @[RegisterRouter.scala:87:24] wire _out_T_9079 = out_f_rivalid_930; // @[RegisterRouter.scala:87:24] wire out_f_roready_930 = out_roready_1_784 & out_romask_930; // @[RegisterRouter.scala:87:24] wire _out_T_9080 = out_f_roready_930; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_930 = out_wivalid_1_784 & out_wimask_930; // @[RegisterRouter.scala:87:24] wire out_f_woready_930 = out_woready_1_784 & out_womask_930; // @[RegisterRouter.scala:87:24] wire _out_T_9081 = ~out_rimask_930; // @[RegisterRouter.scala:87:24] wire _out_T_9082 = ~out_wimask_930; // @[RegisterRouter.scala:87:24] wire _out_T_9083 = ~out_romask_930; // @[RegisterRouter.scala:87:24] wire _out_T_9084 = ~out_womask_930; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_794 = {hi_790, flags_0_go, _out_prepend_T_794}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9085 = out_prepend_794; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9086 = _out_T_9085; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_795 = _out_T_9086; // @[RegisterRouter.scala:87:24] wire out_rimask_931 = |_out_rimask_T_931; // @[RegisterRouter.scala:87:24] wire out_wimask_931 = &_out_wimask_T_931; // @[RegisterRouter.scala:87:24] wire out_romask_931 = |_out_romask_T_931; // @[RegisterRouter.scala:87:24] wire out_womask_931 = &_out_womask_T_931; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_931 = out_rivalid_1_785 & out_rimask_931; // @[RegisterRouter.scala:87:24] wire _out_T_9088 = out_f_rivalid_931; // @[RegisterRouter.scala:87:24] wire out_f_roready_931 = out_roready_1_785 & out_romask_931; // @[RegisterRouter.scala:87:24] wire _out_T_9089 = out_f_roready_931; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_931 = out_wivalid_1_785 & out_wimask_931; // @[RegisterRouter.scala:87:24] wire out_f_woready_931 = out_woready_1_785 & out_womask_931; // @[RegisterRouter.scala:87:24] wire _out_T_9090 = ~out_rimask_931; // @[RegisterRouter.scala:87:24] wire _out_T_9091 = ~out_wimask_931; // @[RegisterRouter.scala:87:24] wire _out_T_9092 = ~out_romask_931; // @[RegisterRouter.scala:87:24] wire _out_T_9093 = ~out_womask_931; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_795 = {hi_791, flags_0_go, _out_prepend_T_795}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9094 = out_prepend_795; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9095 = _out_T_9094; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_796 = _out_T_9095; // @[RegisterRouter.scala:87:24] wire out_rimask_932 = |_out_rimask_T_932; // @[RegisterRouter.scala:87:24] wire out_wimask_932 = &_out_wimask_T_932; // @[RegisterRouter.scala:87:24] wire out_romask_932 = |_out_romask_T_932; // @[RegisterRouter.scala:87:24] wire out_womask_932 = &_out_womask_T_932; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_932 = out_rivalid_1_786 & out_rimask_932; // @[RegisterRouter.scala:87:24] wire _out_T_9097 = out_f_rivalid_932; // @[RegisterRouter.scala:87:24] wire out_f_roready_932 = out_roready_1_786 & out_romask_932; // @[RegisterRouter.scala:87:24] wire _out_T_9098 = out_f_roready_932; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_932 = out_wivalid_1_786 & out_wimask_932; // @[RegisterRouter.scala:87:24] wire out_f_woready_932 = out_woready_1_786 & out_womask_932; // @[RegisterRouter.scala:87:24] wire _out_T_9099 = ~out_rimask_932; // @[RegisterRouter.scala:87:24] wire _out_T_9100 = ~out_wimask_932; // @[RegisterRouter.scala:87:24] wire _out_T_9101 = ~out_romask_932; // @[RegisterRouter.scala:87:24] wire _out_T_9102 = ~out_womask_932; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_796 = {hi_792, flags_0_go, _out_prepend_T_796}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9103 = out_prepend_796; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9104 = _out_T_9103; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_226 = _out_T_9104; // @[MuxLiteral.scala:49:48] wire out_rimask_933 = |_out_rimask_T_933; // @[RegisterRouter.scala:87:24] wire out_wimask_933 = &_out_wimask_T_933; // @[RegisterRouter.scala:87:24] wire out_romask_933 = |_out_romask_T_933; // @[RegisterRouter.scala:87:24] wire out_womask_933 = &_out_womask_T_933; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_933 = out_rivalid_1_787 & out_rimask_933; // @[RegisterRouter.scala:87:24] wire _out_T_9106 = out_f_rivalid_933; // @[RegisterRouter.scala:87:24] wire out_f_roready_933 = out_roready_1_787 & out_romask_933; // @[RegisterRouter.scala:87:24] wire _out_T_9107 = out_f_roready_933; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_933 = out_wivalid_1_787 & out_wimask_933; // @[RegisterRouter.scala:87:24] wire out_f_woready_933 = out_woready_1_787 & out_womask_933; // @[RegisterRouter.scala:87:24] wire _out_T_9108 = ~out_rimask_933; // @[RegisterRouter.scala:87:24] wire _out_T_9109 = ~out_wimask_933; // @[RegisterRouter.scala:87:24] wire _out_T_9110 = ~out_romask_933; // @[RegisterRouter.scala:87:24] wire _out_T_9111 = ~out_womask_933; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9113 = _out_T_9112; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_797 = _out_T_9113; // @[RegisterRouter.scala:87:24] wire out_rimask_934 = |_out_rimask_T_934; // @[RegisterRouter.scala:87:24] wire out_wimask_934 = &_out_wimask_T_934; // @[RegisterRouter.scala:87:24] wire out_romask_934 = |_out_romask_T_934; // @[RegisterRouter.scala:87:24] wire out_womask_934 = &_out_womask_T_934; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_934 = out_rivalid_1_788 & out_rimask_934; // @[RegisterRouter.scala:87:24] wire _out_T_9115 = out_f_rivalid_934; // @[RegisterRouter.scala:87:24] wire out_f_roready_934 = out_roready_1_788 & out_romask_934; // @[RegisterRouter.scala:87:24] wire _out_T_9116 = out_f_roready_934; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_934 = out_wivalid_1_788 & out_wimask_934; // @[RegisterRouter.scala:87:24] wire out_f_woready_934 = out_woready_1_788 & out_womask_934; // @[RegisterRouter.scala:87:24] wire _out_T_9117 = ~out_rimask_934; // @[RegisterRouter.scala:87:24] wire _out_T_9118 = ~out_wimask_934; // @[RegisterRouter.scala:87:24] wire _out_T_9119 = ~out_romask_934; // @[RegisterRouter.scala:87:24] wire _out_T_9120 = ~out_womask_934; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_797 = {hi_906, flags_0_go, _out_prepend_T_797}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9121 = out_prepend_797; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9122 = _out_T_9121; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_798 = _out_T_9122; // @[RegisterRouter.scala:87:24] wire out_rimask_935 = |_out_rimask_T_935; // @[RegisterRouter.scala:87:24] wire out_wimask_935 = &_out_wimask_T_935; // @[RegisterRouter.scala:87:24] wire out_romask_935 = |_out_romask_T_935; // @[RegisterRouter.scala:87:24] wire out_womask_935 = &_out_womask_T_935; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_935 = out_rivalid_1_789 & out_rimask_935; // @[RegisterRouter.scala:87:24] wire _out_T_9124 = out_f_rivalid_935; // @[RegisterRouter.scala:87:24] wire out_f_roready_935 = out_roready_1_789 & out_romask_935; // @[RegisterRouter.scala:87:24] wire _out_T_9125 = out_f_roready_935; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_935 = out_wivalid_1_789 & out_wimask_935; // @[RegisterRouter.scala:87:24] wire out_f_woready_935 = out_woready_1_789 & out_womask_935; // @[RegisterRouter.scala:87:24] wire _out_T_9126 = ~out_rimask_935; // @[RegisterRouter.scala:87:24] wire _out_T_9127 = ~out_wimask_935; // @[RegisterRouter.scala:87:24] wire _out_T_9128 = ~out_romask_935; // @[RegisterRouter.scala:87:24] wire _out_T_9129 = ~out_womask_935; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_798 = {hi_907, flags_0_go, _out_prepend_T_798}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9130 = out_prepend_798; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9131 = _out_T_9130; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_799 = _out_T_9131; // @[RegisterRouter.scala:87:24] wire out_rimask_936 = |_out_rimask_T_936; // @[RegisterRouter.scala:87:24] wire out_wimask_936 = &_out_wimask_T_936; // @[RegisterRouter.scala:87:24] wire out_romask_936 = |_out_romask_T_936; // @[RegisterRouter.scala:87:24] wire out_womask_936 = &_out_womask_T_936; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_936 = out_rivalid_1_790 & out_rimask_936; // @[RegisterRouter.scala:87:24] wire _out_T_9133 = out_f_rivalid_936; // @[RegisterRouter.scala:87:24] wire out_f_roready_936 = out_roready_1_790 & out_romask_936; // @[RegisterRouter.scala:87:24] wire _out_T_9134 = out_f_roready_936; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_936 = out_wivalid_1_790 & out_wimask_936; // @[RegisterRouter.scala:87:24] wire out_f_woready_936 = out_woready_1_790 & out_womask_936; // @[RegisterRouter.scala:87:24] wire _out_T_9135 = ~out_rimask_936; // @[RegisterRouter.scala:87:24] wire _out_T_9136 = ~out_wimask_936; // @[RegisterRouter.scala:87:24] wire _out_T_9137 = ~out_romask_936; // @[RegisterRouter.scala:87:24] wire _out_T_9138 = ~out_womask_936; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_799 = {hi_908, flags_0_go, _out_prepend_T_799}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9139 = out_prepend_799; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9140 = _out_T_9139; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_800 = _out_T_9140; // @[RegisterRouter.scala:87:24] wire out_rimask_937 = |_out_rimask_T_937; // @[RegisterRouter.scala:87:24] wire out_wimask_937 = &_out_wimask_T_937; // @[RegisterRouter.scala:87:24] wire out_romask_937 = |_out_romask_T_937; // @[RegisterRouter.scala:87:24] wire out_womask_937 = &_out_womask_T_937; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_937 = out_rivalid_1_791 & out_rimask_937; // @[RegisterRouter.scala:87:24] wire _out_T_9142 = out_f_rivalid_937; // @[RegisterRouter.scala:87:24] wire out_f_roready_937 = out_roready_1_791 & out_romask_937; // @[RegisterRouter.scala:87:24] wire _out_T_9143 = out_f_roready_937; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_937 = out_wivalid_1_791 & out_wimask_937; // @[RegisterRouter.scala:87:24] wire out_f_woready_937 = out_woready_1_791 & out_womask_937; // @[RegisterRouter.scala:87:24] wire _out_T_9144 = ~out_rimask_937; // @[RegisterRouter.scala:87:24] wire _out_T_9145 = ~out_wimask_937; // @[RegisterRouter.scala:87:24] wire _out_T_9146 = ~out_romask_937; // @[RegisterRouter.scala:87:24] wire _out_T_9147 = ~out_womask_937; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_800 = {hi_909, flags_0_go, _out_prepend_T_800}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9148 = out_prepend_800; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9149 = _out_T_9148; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_801 = _out_T_9149; // @[RegisterRouter.scala:87:24] wire out_rimask_938 = |_out_rimask_T_938; // @[RegisterRouter.scala:87:24] wire out_wimask_938 = &_out_wimask_T_938; // @[RegisterRouter.scala:87:24] wire out_romask_938 = |_out_romask_T_938; // @[RegisterRouter.scala:87:24] wire out_womask_938 = &_out_womask_T_938; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_938 = out_rivalid_1_792 & out_rimask_938; // @[RegisterRouter.scala:87:24] wire _out_T_9151 = out_f_rivalid_938; // @[RegisterRouter.scala:87:24] wire out_f_roready_938 = out_roready_1_792 & out_romask_938; // @[RegisterRouter.scala:87:24] wire _out_T_9152 = out_f_roready_938; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_938 = out_wivalid_1_792 & out_wimask_938; // @[RegisterRouter.scala:87:24] wire out_f_woready_938 = out_woready_1_792 & out_womask_938; // @[RegisterRouter.scala:87:24] wire _out_T_9153 = ~out_rimask_938; // @[RegisterRouter.scala:87:24] wire _out_T_9154 = ~out_wimask_938; // @[RegisterRouter.scala:87:24] wire _out_T_9155 = ~out_romask_938; // @[RegisterRouter.scala:87:24] wire _out_T_9156 = ~out_womask_938; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_801 = {hi_910, flags_0_go, _out_prepend_T_801}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9157 = out_prepend_801; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9158 = _out_T_9157; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_802 = _out_T_9158; // @[RegisterRouter.scala:87:24] wire out_rimask_939 = |_out_rimask_T_939; // @[RegisterRouter.scala:87:24] wire out_wimask_939 = &_out_wimask_T_939; // @[RegisterRouter.scala:87:24] wire out_romask_939 = |_out_romask_T_939; // @[RegisterRouter.scala:87:24] wire out_womask_939 = &_out_womask_T_939; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_939 = out_rivalid_1_793 & out_rimask_939; // @[RegisterRouter.scala:87:24] wire _out_T_9160 = out_f_rivalid_939; // @[RegisterRouter.scala:87:24] wire out_f_roready_939 = out_roready_1_793 & out_romask_939; // @[RegisterRouter.scala:87:24] wire _out_T_9161 = out_f_roready_939; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_939 = out_wivalid_1_793 & out_wimask_939; // @[RegisterRouter.scala:87:24] wire out_f_woready_939 = out_woready_1_793 & out_womask_939; // @[RegisterRouter.scala:87:24] wire _out_T_9162 = ~out_rimask_939; // @[RegisterRouter.scala:87:24] wire _out_T_9163 = ~out_wimask_939; // @[RegisterRouter.scala:87:24] wire _out_T_9164 = ~out_romask_939; // @[RegisterRouter.scala:87:24] wire _out_T_9165 = ~out_womask_939; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_802 = {hi_911, flags_0_go, _out_prepend_T_802}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9166 = out_prepend_802; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9167 = _out_T_9166; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_803 = _out_T_9167; // @[RegisterRouter.scala:87:24] wire out_rimask_940 = |_out_rimask_T_940; // @[RegisterRouter.scala:87:24] wire out_wimask_940 = &_out_wimask_T_940; // @[RegisterRouter.scala:87:24] wire out_romask_940 = |_out_romask_T_940; // @[RegisterRouter.scala:87:24] wire out_womask_940 = &_out_womask_T_940; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_940 = out_rivalid_1_794 & out_rimask_940; // @[RegisterRouter.scala:87:24] wire _out_T_9169 = out_f_rivalid_940; // @[RegisterRouter.scala:87:24] wire out_f_roready_940 = out_roready_1_794 & out_romask_940; // @[RegisterRouter.scala:87:24] wire _out_T_9170 = out_f_roready_940; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_940 = out_wivalid_1_794 & out_wimask_940; // @[RegisterRouter.scala:87:24] wire out_f_woready_940 = out_woready_1_794 & out_womask_940; // @[RegisterRouter.scala:87:24] wire _out_T_9171 = ~out_rimask_940; // @[RegisterRouter.scala:87:24] wire _out_T_9172 = ~out_wimask_940; // @[RegisterRouter.scala:87:24] wire _out_T_9173 = ~out_romask_940; // @[RegisterRouter.scala:87:24] wire _out_T_9174 = ~out_womask_940; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_803 = {hi_912, flags_0_go, _out_prepend_T_803}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9175 = out_prepend_803; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9176 = _out_T_9175; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_241 = _out_T_9176; // @[MuxLiteral.scala:49:48] wire out_rimask_941 = |_out_rimask_T_941; // @[RegisterRouter.scala:87:24] wire out_wimask_941 = &_out_wimask_T_941; // @[RegisterRouter.scala:87:24] wire out_romask_941 = |_out_romask_T_941; // @[RegisterRouter.scala:87:24] wire out_womask_941 = &_out_womask_T_941; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_941 = out_rivalid_1_795 & out_rimask_941; // @[RegisterRouter.scala:87:24] wire _out_T_9178 = out_f_rivalid_941; // @[RegisterRouter.scala:87:24] wire out_f_roready_941 = out_roready_1_795 & out_romask_941; // @[RegisterRouter.scala:87:24] wire _out_T_9179 = out_f_roready_941; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_941 = out_wivalid_1_795 & out_wimask_941; // @[RegisterRouter.scala:87:24] wire out_f_woready_941 = out_woready_1_795 & out_womask_941; // @[RegisterRouter.scala:87:24] wire _out_T_9180 = ~out_rimask_941; // @[RegisterRouter.scala:87:24] wire _out_T_9181 = ~out_wimask_941; // @[RegisterRouter.scala:87:24] wire _out_T_9182 = ~out_romask_941; // @[RegisterRouter.scala:87:24] wire _out_T_9183 = ~out_womask_941; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9185 = _out_T_9184; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_804 = _out_T_9185; // @[RegisterRouter.scala:87:24] wire out_rimask_942 = |_out_rimask_T_942; // @[RegisterRouter.scala:87:24] wire out_wimask_942 = &_out_wimask_T_942; // @[RegisterRouter.scala:87:24] wire out_romask_942 = |_out_romask_T_942; // @[RegisterRouter.scala:87:24] wire out_womask_942 = &_out_womask_T_942; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_942 = out_rivalid_1_796 & out_rimask_942; // @[RegisterRouter.scala:87:24] wire _out_T_9187 = out_f_rivalid_942; // @[RegisterRouter.scala:87:24] wire out_f_roready_942 = out_roready_1_796 & out_romask_942; // @[RegisterRouter.scala:87:24] wire _out_T_9188 = out_f_roready_942; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_942 = out_wivalid_1_796 & out_wimask_942; // @[RegisterRouter.scala:87:24] wire out_f_woready_942 = out_woready_1_796 & out_womask_942; // @[RegisterRouter.scala:87:24] wire _out_T_9189 = ~out_rimask_942; // @[RegisterRouter.scala:87:24] wire _out_T_9190 = ~out_wimask_942; // @[RegisterRouter.scala:87:24] wire _out_T_9191 = ~out_romask_942; // @[RegisterRouter.scala:87:24] wire _out_T_9192 = ~out_womask_942; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_804 = {hi_314, flags_0_go, _out_prepend_T_804}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9193 = out_prepend_804; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9194 = _out_T_9193; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_805 = _out_T_9194; // @[RegisterRouter.scala:87:24] wire out_rimask_943 = |_out_rimask_T_943; // @[RegisterRouter.scala:87:24] wire out_wimask_943 = &_out_wimask_T_943; // @[RegisterRouter.scala:87:24] wire out_romask_943 = |_out_romask_T_943; // @[RegisterRouter.scala:87:24] wire out_womask_943 = &_out_womask_T_943; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_943 = out_rivalid_1_797 & out_rimask_943; // @[RegisterRouter.scala:87:24] wire _out_T_9196 = out_f_rivalid_943; // @[RegisterRouter.scala:87:24] wire out_f_roready_943 = out_roready_1_797 & out_romask_943; // @[RegisterRouter.scala:87:24] wire _out_T_9197 = out_f_roready_943; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_943 = out_wivalid_1_797 & out_wimask_943; // @[RegisterRouter.scala:87:24] wire out_f_woready_943 = out_woready_1_797 & out_womask_943; // @[RegisterRouter.scala:87:24] wire _out_T_9198 = ~out_rimask_943; // @[RegisterRouter.scala:87:24] wire _out_T_9199 = ~out_wimask_943; // @[RegisterRouter.scala:87:24] wire _out_T_9200 = ~out_romask_943; // @[RegisterRouter.scala:87:24] wire _out_T_9201 = ~out_womask_943; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_805 = {hi_315, flags_0_go, _out_prepend_T_805}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9202 = out_prepend_805; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9203 = _out_T_9202; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_806 = _out_T_9203; // @[RegisterRouter.scala:87:24] wire out_rimask_944 = |_out_rimask_T_944; // @[RegisterRouter.scala:87:24] wire out_wimask_944 = &_out_wimask_T_944; // @[RegisterRouter.scala:87:24] wire out_romask_944 = |_out_romask_T_944; // @[RegisterRouter.scala:87:24] wire out_womask_944 = &_out_womask_T_944; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_944 = out_rivalid_1_798 & out_rimask_944; // @[RegisterRouter.scala:87:24] wire _out_T_9205 = out_f_rivalid_944; // @[RegisterRouter.scala:87:24] wire out_f_roready_944 = out_roready_1_798 & out_romask_944; // @[RegisterRouter.scala:87:24] wire _out_T_9206 = out_f_roready_944; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_944 = out_wivalid_1_798 & out_wimask_944; // @[RegisterRouter.scala:87:24] wire out_f_woready_944 = out_woready_1_798 & out_womask_944; // @[RegisterRouter.scala:87:24] wire _out_T_9207 = ~out_rimask_944; // @[RegisterRouter.scala:87:24] wire _out_T_9208 = ~out_wimask_944; // @[RegisterRouter.scala:87:24] wire _out_T_9209 = ~out_romask_944; // @[RegisterRouter.scala:87:24] wire _out_T_9210 = ~out_womask_944; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_806 = {hi_316, flags_0_go, _out_prepend_T_806}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9211 = out_prepend_806; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9212 = _out_T_9211; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_807 = _out_T_9212; // @[RegisterRouter.scala:87:24] wire out_rimask_945 = |_out_rimask_T_945; // @[RegisterRouter.scala:87:24] wire out_wimask_945 = &_out_wimask_T_945; // @[RegisterRouter.scala:87:24] wire out_romask_945 = |_out_romask_T_945; // @[RegisterRouter.scala:87:24] wire out_womask_945 = &_out_womask_T_945; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_945 = out_rivalid_1_799 & out_rimask_945; // @[RegisterRouter.scala:87:24] wire _out_T_9214 = out_f_rivalid_945; // @[RegisterRouter.scala:87:24] wire out_f_roready_945 = out_roready_1_799 & out_romask_945; // @[RegisterRouter.scala:87:24] wire _out_T_9215 = out_f_roready_945; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_945 = out_wivalid_1_799 & out_wimask_945; // @[RegisterRouter.scala:87:24] wire out_f_woready_945 = out_woready_1_799 & out_womask_945; // @[RegisterRouter.scala:87:24] wire _out_T_9216 = ~out_rimask_945; // @[RegisterRouter.scala:87:24] wire _out_T_9217 = ~out_wimask_945; // @[RegisterRouter.scala:87:24] wire _out_T_9218 = ~out_romask_945; // @[RegisterRouter.scala:87:24] wire _out_T_9219 = ~out_womask_945; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_807 = {hi_317, flags_0_go, _out_prepend_T_807}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9220 = out_prepend_807; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9221 = _out_T_9220; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_808 = _out_T_9221; // @[RegisterRouter.scala:87:24] wire out_rimask_946 = |_out_rimask_T_946; // @[RegisterRouter.scala:87:24] wire out_wimask_946 = &_out_wimask_T_946; // @[RegisterRouter.scala:87:24] wire out_romask_946 = |_out_romask_T_946; // @[RegisterRouter.scala:87:24] wire out_womask_946 = &_out_womask_T_946; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_946 = out_rivalid_1_800 & out_rimask_946; // @[RegisterRouter.scala:87:24] wire _out_T_9223 = out_f_rivalid_946; // @[RegisterRouter.scala:87:24] wire out_f_roready_946 = out_roready_1_800 & out_romask_946; // @[RegisterRouter.scala:87:24] wire _out_T_9224 = out_f_roready_946; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_946 = out_wivalid_1_800 & out_wimask_946; // @[RegisterRouter.scala:87:24] wire out_f_woready_946 = out_woready_1_800 & out_womask_946; // @[RegisterRouter.scala:87:24] wire _out_T_9225 = ~out_rimask_946; // @[RegisterRouter.scala:87:24] wire _out_T_9226 = ~out_wimask_946; // @[RegisterRouter.scala:87:24] wire _out_T_9227 = ~out_romask_946; // @[RegisterRouter.scala:87:24] wire _out_T_9228 = ~out_womask_946; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_808 = {hi_318, flags_0_go, _out_prepend_T_808}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9229 = out_prepend_808; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9230 = _out_T_9229; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_809 = _out_T_9230; // @[RegisterRouter.scala:87:24] wire out_rimask_947 = |_out_rimask_T_947; // @[RegisterRouter.scala:87:24] wire out_wimask_947 = &_out_wimask_T_947; // @[RegisterRouter.scala:87:24] wire out_romask_947 = |_out_romask_T_947; // @[RegisterRouter.scala:87:24] wire out_womask_947 = &_out_womask_T_947; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_947 = out_rivalid_1_801 & out_rimask_947; // @[RegisterRouter.scala:87:24] wire _out_T_9232 = out_f_rivalid_947; // @[RegisterRouter.scala:87:24] wire out_f_roready_947 = out_roready_1_801 & out_romask_947; // @[RegisterRouter.scala:87:24] wire _out_T_9233 = out_f_roready_947; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_947 = out_wivalid_1_801 & out_wimask_947; // @[RegisterRouter.scala:87:24] wire out_f_woready_947 = out_woready_1_801 & out_womask_947; // @[RegisterRouter.scala:87:24] wire _out_T_9234 = ~out_rimask_947; // @[RegisterRouter.scala:87:24] wire _out_T_9235 = ~out_wimask_947; // @[RegisterRouter.scala:87:24] wire _out_T_9236 = ~out_romask_947; // @[RegisterRouter.scala:87:24] wire _out_T_9237 = ~out_womask_947; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_809 = {hi_319, flags_0_go, _out_prepend_T_809}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9238 = out_prepend_809; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9239 = _out_T_9238; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_810 = _out_T_9239; // @[RegisterRouter.scala:87:24] wire out_rimask_948 = |_out_rimask_T_948; // @[RegisterRouter.scala:87:24] wire out_wimask_948 = &_out_wimask_T_948; // @[RegisterRouter.scala:87:24] wire out_romask_948 = |_out_romask_T_948; // @[RegisterRouter.scala:87:24] wire out_womask_948 = &_out_womask_T_948; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_948 = out_rivalid_1_802 & out_rimask_948; // @[RegisterRouter.scala:87:24] wire _out_T_9241 = out_f_rivalid_948; // @[RegisterRouter.scala:87:24] wire out_f_roready_948 = out_roready_1_802 & out_romask_948; // @[RegisterRouter.scala:87:24] wire _out_T_9242 = out_f_roready_948; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_948 = out_wivalid_1_802 & out_wimask_948; // @[RegisterRouter.scala:87:24] wire out_f_woready_948 = out_woready_1_802 & out_womask_948; // @[RegisterRouter.scala:87:24] wire _out_T_9243 = ~out_rimask_948; // @[RegisterRouter.scala:87:24] wire _out_T_9244 = ~out_wimask_948; // @[RegisterRouter.scala:87:24] wire _out_T_9245 = ~out_romask_948; // @[RegisterRouter.scala:87:24] wire _out_T_9246 = ~out_womask_948; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_810 = {hi_320, flags_0_go, _out_prepend_T_810}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9247 = out_prepend_810; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9248 = _out_T_9247; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_167 = _out_T_9248; // @[MuxLiteral.scala:49:48] wire out_rimask_949 = |_out_rimask_T_949; // @[RegisterRouter.scala:87:24] wire out_wimask_949 = &_out_wimask_T_949; // @[RegisterRouter.scala:87:24] wire out_romask_949 = |_out_romask_T_949; // @[RegisterRouter.scala:87:24] wire out_womask_949 = &_out_womask_T_949; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_949 = out_rivalid_1_803 & out_rimask_949; // @[RegisterRouter.scala:87:24] wire _out_T_9250 = out_f_rivalid_949; // @[RegisterRouter.scala:87:24] wire out_f_roready_949 = out_roready_1_803 & out_romask_949; // @[RegisterRouter.scala:87:24] wire _out_T_9251 = out_f_roready_949; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_949 = out_wivalid_1_803 & out_wimask_949; // @[RegisterRouter.scala:87:24] wire out_f_woready_949 = out_woready_1_803 & out_womask_949; // @[RegisterRouter.scala:87:24] wire _out_T_9252 = ~out_rimask_949; // @[RegisterRouter.scala:87:24] wire _out_T_9253 = ~out_wimask_949; // @[RegisterRouter.scala:87:24] wire _out_T_9254 = ~out_romask_949; // @[RegisterRouter.scala:87:24] wire _out_T_9255 = ~out_womask_949; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9257 = _out_T_9256; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_811 = _out_T_9257; // @[RegisterRouter.scala:87:24] wire out_rimask_950 = |_out_rimask_T_950; // @[RegisterRouter.scala:87:24] wire out_wimask_950 = &_out_wimask_T_950; // @[RegisterRouter.scala:87:24] wire out_romask_950 = |_out_romask_T_950; // @[RegisterRouter.scala:87:24] wire out_womask_950 = &_out_womask_T_950; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_950 = out_rivalid_1_804 & out_rimask_950; // @[RegisterRouter.scala:87:24] wire _out_T_9259 = out_f_rivalid_950; // @[RegisterRouter.scala:87:24] wire out_f_roready_950 = out_roready_1_804 & out_romask_950; // @[RegisterRouter.scala:87:24] wire _out_T_9260 = out_f_roready_950; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_950 = out_wivalid_1_804 & out_wimask_950; // @[RegisterRouter.scala:87:24] wire out_f_woready_950 = out_woready_1_804 & out_womask_950; // @[RegisterRouter.scala:87:24] wire _out_T_9261 = ~out_rimask_950; // @[RegisterRouter.scala:87:24] wire _out_T_9262 = ~out_wimask_950; // @[RegisterRouter.scala:87:24] wire _out_T_9263 = ~out_romask_950; // @[RegisterRouter.scala:87:24] wire _out_T_9264 = ~out_womask_950; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_811 = {hi_274, flags_0_go, _out_prepend_T_811}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9265 = out_prepend_811; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9266 = _out_T_9265; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_812 = _out_T_9266; // @[RegisterRouter.scala:87:24] wire out_rimask_951 = |_out_rimask_T_951; // @[RegisterRouter.scala:87:24] wire out_wimask_951 = &_out_wimask_T_951; // @[RegisterRouter.scala:87:24] wire out_romask_951 = |_out_romask_T_951; // @[RegisterRouter.scala:87:24] wire out_womask_951 = &_out_womask_T_951; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_951 = out_rivalid_1_805 & out_rimask_951; // @[RegisterRouter.scala:87:24] wire _out_T_9268 = out_f_rivalid_951; // @[RegisterRouter.scala:87:24] wire out_f_roready_951 = out_roready_1_805 & out_romask_951; // @[RegisterRouter.scala:87:24] wire _out_T_9269 = out_f_roready_951; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_951 = out_wivalid_1_805 & out_wimask_951; // @[RegisterRouter.scala:87:24] wire out_f_woready_951 = out_woready_1_805 & out_womask_951; // @[RegisterRouter.scala:87:24] wire _out_T_9270 = ~out_rimask_951; // @[RegisterRouter.scala:87:24] wire _out_T_9271 = ~out_wimask_951; // @[RegisterRouter.scala:87:24] wire _out_T_9272 = ~out_romask_951; // @[RegisterRouter.scala:87:24] wire _out_T_9273 = ~out_womask_951; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_812 = {hi_275, flags_0_go, _out_prepend_T_812}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9274 = out_prepend_812; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9275 = _out_T_9274; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_813 = _out_T_9275; // @[RegisterRouter.scala:87:24] wire out_rimask_952 = |_out_rimask_T_952; // @[RegisterRouter.scala:87:24] wire out_wimask_952 = &_out_wimask_T_952; // @[RegisterRouter.scala:87:24] wire out_romask_952 = |_out_romask_T_952; // @[RegisterRouter.scala:87:24] wire out_womask_952 = &_out_womask_T_952; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_952 = out_rivalid_1_806 & out_rimask_952; // @[RegisterRouter.scala:87:24] wire _out_T_9277 = out_f_rivalid_952; // @[RegisterRouter.scala:87:24] wire out_f_roready_952 = out_roready_1_806 & out_romask_952; // @[RegisterRouter.scala:87:24] wire _out_T_9278 = out_f_roready_952; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_952 = out_wivalid_1_806 & out_wimask_952; // @[RegisterRouter.scala:87:24] wire out_f_woready_952 = out_woready_1_806 & out_womask_952; // @[RegisterRouter.scala:87:24] wire _out_T_9279 = ~out_rimask_952; // @[RegisterRouter.scala:87:24] wire _out_T_9280 = ~out_wimask_952; // @[RegisterRouter.scala:87:24] wire _out_T_9281 = ~out_romask_952; // @[RegisterRouter.scala:87:24] wire _out_T_9282 = ~out_womask_952; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_813 = {hi_276, flags_0_go, _out_prepend_T_813}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9283 = out_prepend_813; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9284 = _out_T_9283; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_814 = _out_T_9284; // @[RegisterRouter.scala:87:24] wire out_rimask_953 = |_out_rimask_T_953; // @[RegisterRouter.scala:87:24] wire out_wimask_953 = &_out_wimask_T_953; // @[RegisterRouter.scala:87:24] wire out_romask_953 = |_out_romask_T_953; // @[RegisterRouter.scala:87:24] wire out_womask_953 = &_out_womask_T_953; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_953 = out_rivalid_1_807 & out_rimask_953; // @[RegisterRouter.scala:87:24] wire _out_T_9286 = out_f_rivalid_953; // @[RegisterRouter.scala:87:24] wire out_f_roready_953 = out_roready_1_807 & out_romask_953; // @[RegisterRouter.scala:87:24] wire _out_T_9287 = out_f_roready_953; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_953 = out_wivalid_1_807 & out_wimask_953; // @[RegisterRouter.scala:87:24] wire out_f_woready_953 = out_woready_1_807 & out_womask_953; // @[RegisterRouter.scala:87:24] wire _out_T_9288 = ~out_rimask_953; // @[RegisterRouter.scala:87:24] wire _out_T_9289 = ~out_wimask_953; // @[RegisterRouter.scala:87:24] wire _out_T_9290 = ~out_romask_953; // @[RegisterRouter.scala:87:24] wire _out_T_9291 = ~out_womask_953; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_814 = {hi_277, flags_0_go, _out_prepend_T_814}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9292 = out_prepend_814; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9293 = _out_T_9292; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_815 = _out_T_9293; // @[RegisterRouter.scala:87:24] wire out_rimask_954 = |_out_rimask_T_954; // @[RegisterRouter.scala:87:24] wire out_wimask_954 = &_out_wimask_T_954; // @[RegisterRouter.scala:87:24] wire out_romask_954 = |_out_romask_T_954; // @[RegisterRouter.scala:87:24] wire out_womask_954 = &_out_womask_T_954; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_954 = out_rivalid_1_808 & out_rimask_954; // @[RegisterRouter.scala:87:24] wire _out_T_9295 = out_f_rivalid_954; // @[RegisterRouter.scala:87:24] wire out_f_roready_954 = out_roready_1_808 & out_romask_954; // @[RegisterRouter.scala:87:24] wire _out_T_9296 = out_f_roready_954; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_954 = out_wivalid_1_808 & out_wimask_954; // @[RegisterRouter.scala:87:24] wire out_f_woready_954 = out_woready_1_808 & out_womask_954; // @[RegisterRouter.scala:87:24] wire _out_T_9297 = ~out_rimask_954; // @[RegisterRouter.scala:87:24] wire _out_T_9298 = ~out_wimask_954; // @[RegisterRouter.scala:87:24] wire _out_T_9299 = ~out_romask_954; // @[RegisterRouter.scala:87:24] wire _out_T_9300 = ~out_womask_954; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_815 = {hi_278, flags_0_go, _out_prepend_T_815}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9301 = out_prepend_815; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9302 = _out_T_9301; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_816 = _out_T_9302; // @[RegisterRouter.scala:87:24] wire out_rimask_955 = |_out_rimask_T_955; // @[RegisterRouter.scala:87:24] wire out_wimask_955 = &_out_wimask_T_955; // @[RegisterRouter.scala:87:24] wire out_romask_955 = |_out_romask_T_955; // @[RegisterRouter.scala:87:24] wire out_womask_955 = &_out_womask_T_955; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_955 = out_rivalid_1_809 & out_rimask_955; // @[RegisterRouter.scala:87:24] wire _out_T_9304 = out_f_rivalid_955; // @[RegisterRouter.scala:87:24] wire out_f_roready_955 = out_roready_1_809 & out_romask_955; // @[RegisterRouter.scala:87:24] wire _out_T_9305 = out_f_roready_955; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_955 = out_wivalid_1_809 & out_wimask_955; // @[RegisterRouter.scala:87:24] wire out_f_woready_955 = out_woready_1_809 & out_womask_955; // @[RegisterRouter.scala:87:24] wire _out_T_9306 = ~out_rimask_955; // @[RegisterRouter.scala:87:24] wire _out_T_9307 = ~out_wimask_955; // @[RegisterRouter.scala:87:24] wire _out_T_9308 = ~out_romask_955; // @[RegisterRouter.scala:87:24] wire _out_T_9309 = ~out_womask_955; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_816 = {hi_279, flags_0_go, _out_prepend_T_816}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9310 = out_prepend_816; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9311 = _out_T_9310; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_817 = _out_T_9311; // @[RegisterRouter.scala:87:24] wire out_rimask_956 = |_out_rimask_T_956; // @[RegisterRouter.scala:87:24] wire out_wimask_956 = &_out_wimask_T_956; // @[RegisterRouter.scala:87:24] wire out_romask_956 = |_out_romask_T_956; // @[RegisterRouter.scala:87:24] wire out_womask_956 = &_out_womask_T_956; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_956 = out_rivalid_1_810 & out_rimask_956; // @[RegisterRouter.scala:87:24] wire _out_T_9313 = out_f_rivalid_956; // @[RegisterRouter.scala:87:24] wire out_f_roready_956 = out_roready_1_810 & out_romask_956; // @[RegisterRouter.scala:87:24] wire _out_T_9314 = out_f_roready_956; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_956 = out_wivalid_1_810 & out_wimask_956; // @[RegisterRouter.scala:87:24] wire out_f_woready_956 = out_woready_1_810 & out_womask_956; // @[RegisterRouter.scala:87:24] wire _out_T_9315 = ~out_rimask_956; // @[RegisterRouter.scala:87:24] wire _out_T_9316 = ~out_wimask_956; // @[RegisterRouter.scala:87:24] wire _out_T_9317 = ~out_romask_956; // @[RegisterRouter.scala:87:24] wire _out_T_9318 = ~out_womask_956; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_817 = {hi_280, flags_0_go, _out_prepend_T_817}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9319 = out_prepend_817; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9320 = _out_T_9319; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_162 = _out_T_9320; // @[MuxLiteral.scala:49:48] wire out_rimask_957 = |_out_rimask_T_957; // @[RegisterRouter.scala:87:24] wire out_wimask_957 = &_out_wimask_T_957; // @[RegisterRouter.scala:87:24] wire out_romask_957 = |_out_romask_T_957; // @[RegisterRouter.scala:87:24] wire out_womask_957 = &_out_womask_T_957; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_957 = out_rivalid_1_811 & out_rimask_957; // @[RegisterRouter.scala:87:24] wire _out_T_9322 = out_f_rivalid_957; // @[RegisterRouter.scala:87:24] wire out_f_roready_957 = out_roready_1_811 & out_romask_957; // @[RegisterRouter.scala:87:24] wire _out_T_9323 = out_f_roready_957; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_957 = out_wivalid_1_811 & out_wimask_957; // @[RegisterRouter.scala:87:24] wire out_f_woready_957 = out_woready_1_811 & out_womask_957; // @[RegisterRouter.scala:87:24] wire _out_T_9324 = ~out_rimask_957; // @[RegisterRouter.scala:87:24] wire _out_T_9325 = ~out_wimask_957; // @[RegisterRouter.scala:87:24] wire _out_T_9326 = ~out_romask_957; // @[RegisterRouter.scala:87:24] wire _out_T_9327 = ~out_womask_957; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9329 = _out_T_9328; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_818 = _out_T_9329; // @[RegisterRouter.scala:87:24] wire out_rimask_958 = |_out_rimask_T_958; // @[RegisterRouter.scala:87:24] wire out_wimask_958 = &_out_wimask_T_958; // @[RegisterRouter.scala:87:24] wire out_romask_958 = |_out_romask_T_958; // @[RegisterRouter.scala:87:24] wire out_womask_958 = &_out_womask_T_958; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_958 = out_rivalid_1_812 & out_rimask_958; // @[RegisterRouter.scala:87:24] wire _out_T_9331 = out_f_rivalid_958; // @[RegisterRouter.scala:87:24] wire out_f_roready_958 = out_roready_1_812 & out_romask_958; // @[RegisterRouter.scala:87:24] wire _out_T_9332 = out_f_roready_958; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_958 = out_wivalid_1_812 & out_wimask_958; // @[RegisterRouter.scala:87:24] wire out_f_woready_958 = out_woready_1_812 & out_womask_958; // @[RegisterRouter.scala:87:24] wire _out_T_9333 = ~out_rimask_958; // @[RegisterRouter.scala:87:24] wire _out_T_9334 = ~out_wimask_958; // @[RegisterRouter.scala:87:24] wire _out_T_9335 = ~out_romask_958; // @[RegisterRouter.scala:87:24] wire _out_T_9336 = ~out_womask_958; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_818 = {hi_1018, flags_0_go, _out_prepend_T_818}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9337 = out_prepend_818; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9338 = _out_T_9337; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_819 = _out_T_9338; // @[RegisterRouter.scala:87:24] wire out_rimask_959 = |_out_rimask_T_959; // @[RegisterRouter.scala:87:24] wire out_wimask_959 = &_out_wimask_T_959; // @[RegisterRouter.scala:87:24] wire out_romask_959 = |_out_romask_T_959; // @[RegisterRouter.scala:87:24] wire out_womask_959 = &_out_womask_T_959; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_959 = out_rivalid_1_813 & out_rimask_959; // @[RegisterRouter.scala:87:24] wire _out_T_9340 = out_f_rivalid_959; // @[RegisterRouter.scala:87:24] wire out_f_roready_959 = out_roready_1_813 & out_romask_959; // @[RegisterRouter.scala:87:24] wire _out_T_9341 = out_f_roready_959; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_959 = out_wivalid_1_813 & out_wimask_959; // @[RegisterRouter.scala:87:24] wire out_f_woready_959 = out_woready_1_813 & out_womask_959; // @[RegisterRouter.scala:87:24] wire _out_T_9342 = ~out_rimask_959; // @[RegisterRouter.scala:87:24] wire _out_T_9343 = ~out_wimask_959; // @[RegisterRouter.scala:87:24] wire _out_T_9344 = ~out_romask_959; // @[RegisterRouter.scala:87:24] wire _out_T_9345 = ~out_womask_959; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_819 = {hi_1019, flags_0_go, _out_prepend_T_819}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9346 = out_prepend_819; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9347 = _out_T_9346; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_820 = _out_T_9347; // @[RegisterRouter.scala:87:24] wire out_rimask_960 = |_out_rimask_T_960; // @[RegisterRouter.scala:87:24] wire out_wimask_960 = &_out_wimask_T_960; // @[RegisterRouter.scala:87:24] wire out_romask_960 = |_out_romask_T_960; // @[RegisterRouter.scala:87:24] wire out_womask_960 = &_out_womask_T_960; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_960 = out_rivalid_1_814 & out_rimask_960; // @[RegisterRouter.scala:87:24] wire _out_T_9349 = out_f_rivalid_960; // @[RegisterRouter.scala:87:24] wire out_f_roready_960 = out_roready_1_814 & out_romask_960; // @[RegisterRouter.scala:87:24] wire _out_T_9350 = out_f_roready_960; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_960 = out_wivalid_1_814 & out_wimask_960; // @[RegisterRouter.scala:87:24] wire out_f_woready_960 = out_woready_1_814 & out_womask_960; // @[RegisterRouter.scala:87:24] wire _out_T_9351 = ~out_rimask_960; // @[RegisterRouter.scala:87:24] wire _out_T_9352 = ~out_wimask_960; // @[RegisterRouter.scala:87:24] wire _out_T_9353 = ~out_romask_960; // @[RegisterRouter.scala:87:24] wire _out_T_9354 = ~out_womask_960; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_820 = {hi_1020, flags_0_go, _out_prepend_T_820}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9355 = out_prepend_820; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9356 = _out_T_9355; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_821 = _out_T_9356; // @[RegisterRouter.scala:87:24] wire out_rimask_961 = |_out_rimask_T_961; // @[RegisterRouter.scala:87:24] wire out_wimask_961 = &_out_wimask_T_961; // @[RegisterRouter.scala:87:24] wire out_romask_961 = |_out_romask_T_961; // @[RegisterRouter.scala:87:24] wire out_womask_961 = &_out_womask_T_961; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_961 = out_rivalid_1_815 & out_rimask_961; // @[RegisterRouter.scala:87:24] wire _out_T_9358 = out_f_rivalid_961; // @[RegisterRouter.scala:87:24] wire out_f_roready_961 = out_roready_1_815 & out_romask_961; // @[RegisterRouter.scala:87:24] wire _out_T_9359 = out_f_roready_961; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_961 = out_wivalid_1_815 & out_wimask_961; // @[RegisterRouter.scala:87:24] wire out_f_woready_961 = out_woready_1_815 & out_womask_961; // @[RegisterRouter.scala:87:24] wire _out_T_9360 = ~out_rimask_961; // @[RegisterRouter.scala:87:24] wire _out_T_9361 = ~out_wimask_961; // @[RegisterRouter.scala:87:24] wire _out_T_9362 = ~out_romask_961; // @[RegisterRouter.scala:87:24] wire _out_T_9363 = ~out_womask_961; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_821 = {hi_1021, flags_0_go, _out_prepend_T_821}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9364 = out_prepend_821; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9365 = _out_T_9364; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_822 = _out_T_9365; // @[RegisterRouter.scala:87:24] wire out_rimask_962 = |_out_rimask_T_962; // @[RegisterRouter.scala:87:24] wire out_wimask_962 = &_out_wimask_T_962; // @[RegisterRouter.scala:87:24] wire out_romask_962 = |_out_romask_T_962; // @[RegisterRouter.scala:87:24] wire out_womask_962 = &_out_womask_T_962; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_962 = out_rivalid_1_816 & out_rimask_962; // @[RegisterRouter.scala:87:24] wire _out_T_9367 = out_f_rivalid_962; // @[RegisterRouter.scala:87:24] wire out_f_roready_962 = out_roready_1_816 & out_romask_962; // @[RegisterRouter.scala:87:24] wire _out_T_9368 = out_f_roready_962; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_962 = out_wivalid_1_816 & out_wimask_962; // @[RegisterRouter.scala:87:24] wire out_f_woready_962 = out_woready_1_816 & out_womask_962; // @[RegisterRouter.scala:87:24] wire _out_T_9369 = ~out_rimask_962; // @[RegisterRouter.scala:87:24] wire _out_T_9370 = ~out_wimask_962; // @[RegisterRouter.scala:87:24] wire _out_T_9371 = ~out_romask_962; // @[RegisterRouter.scala:87:24] wire _out_T_9372 = ~out_womask_962; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_822 = {hi_1022, flags_0_go, _out_prepend_T_822}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9373 = out_prepend_822; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9374 = _out_T_9373; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_823 = _out_T_9374; // @[RegisterRouter.scala:87:24] wire out_rimask_963 = |_out_rimask_T_963; // @[RegisterRouter.scala:87:24] wire out_wimask_963 = &_out_wimask_T_963; // @[RegisterRouter.scala:87:24] wire out_romask_963 = |_out_romask_T_963; // @[RegisterRouter.scala:87:24] wire out_womask_963 = &_out_womask_T_963; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_963 = out_rivalid_1_817 & out_rimask_963; // @[RegisterRouter.scala:87:24] wire _out_T_9376 = out_f_rivalid_963; // @[RegisterRouter.scala:87:24] wire out_f_roready_963 = out_roready_1_817 & out_romask_963; // @[RegisterRouter.scala:87:24] wire _out_T_9377 = out_f_roready_963; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_963 = out_wivalid_1_817 & out_wimask_963; // @[RegisterRouter.scala:87:24] wire out_f_woready_963 = out_woready_1_817 & out_womask_963; // @[RegisterRouter.scala:87:24] wire _out_T_9378 = ~out_rimask_963; // @[RegisterRouter.scala:87:24] wire _out_T_9379 = ~out_wimask_963; // @[RegisterRouter.scala:87:24] wire _out_T_9380 = ~out_romask_963; // @[RegisterRouter.scala:87:24] wire _out_T_9381 = ~out_womask_963; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_823 = {hi_1023, flags_0_go, _out_prepend_T_823}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9382 = out_prepend_823; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9383 = _out_T_9382; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_824 = _out_T_9383; // @[RegisterRouter.scala:87:24] wire out_rimask_964 = |_out_rimask_T_964; // @[RegisterRouter.scala:87:24] wire out_wimask_964 = &_out_wimask_T_964; // @[RegisterRouter.scala:87:24] wire out_romask_964 = |_out_romask_T_964; // @[RegisterRouter.scala:87:24] wire out_womask_964 = &_out_womask_T_964; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_964 = out_rivalid_1_818 & out_rimask_964; // @[RegisterRouter.scala:87:24] wire _out_T_9385 = out_f_rivalid_964; // @[RegisterRouter.scala:87:24] wire out_f_roready_964 = out_roready_1_818 & out_romask_964; // @[RegisterRouter.scala:87:24] wire _out_T_9386 = out_f_roready_964; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_964 = out_wivalid_1_818 & out_wimask_964; // @[RegisterRouter.scala:87:24] wire out_f_woready_964 = out_woready_1_818 & out_womask_964; // @[RegisterRouter.scala:87:24] wire _out_T_9387 = ~out_rimask_964; // @[RegisterRouter.scala:87:24] wire _out_T_9388 = ~out_wimask_964; // @[RegisterRouter.scala:87:24] wire _out_T_9389 = ~out_romask_964; // @[RegisterRouter.scala:87:24] wire _out_T_9390 = ~out_womask_964; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_824 = {hi_1024, flags_0_go, _out_prepend_T_824}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9391 = out_prepend_824; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9392 = _out_T_9391; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_255 = _out_T_9392; // @[MuxLiteral.scala:49:48] wire out_rimask_965 = |_out_rimask_T_965; // @[RegisterRouter.scala:87:24] wire out_wimask_965 = &_out_wimask_T_965; // @[RegisterRouter.scala:87:24] wire out_romask_965 = |_out_romask_T_965; // @[RegisterRouter.scala:87:24] wire out_womask_965 = &_out_womask_T_965; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_965 = out_rivalid_1_819 & out_rimask_965; // @[RegisterRouter.scala:87:24] wire _out_T_9394 = out_f_rivalid_965; // @[RegisterRouter.scala:87:24] wire out_f_roready_965 = out_roready_1_819 & out_romask_965; // @[RegisterRouter.scala:87:24] wire _out_T_9395 = out_f_roready_965; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_965 = out_wivalid_1_819 & out_wimask_965; // @[RegisterRouter.scala:87:24] wire out_f_woready_965 = out_woready_1_819 & out_womask_965; // @[RegisterRouter.scala:87:24] wire _out_T_9396 = ~out_rimask_965; // @[RegisterRouter.scala:87:24] wire _out_T_9397 = ~out_wimask_965; // @[RegisterRouter.scala:87:24] wire _out_T_9398 = ~out_romask_965; // @[RegisterRouter.scala:87:24] wire _out_T_9399 = ~out_womask_965; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9401 = _out_T_9400; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_825 = _out_T_9401; // @[RegisterRouter.scala:87:24] wire out_rimask_966 = |_out_rimask_T_966; // @[RegisterRouter.scala:87:24] wire out_wimask_966 = &_out_wimask_T_966; // @[RegisterRouter.scala:87:24] wire out_romask_966 = |_out_romask_T_966; // @[RegisterRouter.scala:87:24] wire out_womask_966 = &_out_womask_T_966; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_966 = out_rivalid_1_820 & out_rimask_966; // @[RegisterRouter.scala:87:24] wire _out_T_9403 = out_f_rivalid_966; // @[RegisterRouter.scala:87:24] wire out_f_roready_966 = out_roready_1_820 & out_romask_966; // @[RegisterRouter.scala:87:24] wire _out_T_9404 = out_f_roready_966; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_966 = out_wivalid_1_820 & out_wimask_966; // @[RegisterRouter.scala:87:24] wire out_f_woready_966 = out_woready_1_820 & out_womask_966; // @[RegisterRouter.scala:87:24] wire _out_T_9405 = ~out_rimask_966; // @[RegisterRouter.scala:87:24] wire _out_T_9406 = ~out_wimask_966; // @[RegisterRouter.scala:87:24] wire _out_T_9407 = ~out_romask_966; // @[RegisterRouter.scala:87:24] wire _out_T_9408 = ~out_womask_966; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_825 = {hi_650, flags_0_go, _out_prepend_T_825}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9409 = out_prepend_825; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9410 = _out_T_9409; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_826 = _out_T_9410; // @[RegisterRouter.scala:87:24] wire out_rimask_967 = |_out_rimask_T_967; // @[RegisterRouter.scala:87:24] wire out_wimask_967 = &_out_wimask_T_967; // @[RegisterRouter.scala:87:24] wire out_romask_967 = |_out_romask_T_967; // @[RegisterRouter.scala:87:24] wire out_womask_967 = &_out_womask_T_967; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_967 = out_rivalid_1_821 & out_rimask_967; // @[RegisterRouter.scala:87:24] wire _out_T_9412 = out_f_rivalid_967; // @[RegisterRouter.scala:87:24] wire out_f_roready_967 = out_roready_1_821 & out_romask_967; // @[RegisterRouter.scala:87:24] wire _out_T_9413 = out_f_roready_967; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_967 = out_wivalid_1_821 & out_wimask_967; // @[RegisterRouter.scala:87:24] wire out_f_woready_967 = out_woready_1_821 & out_womask_967; // @[RegisterRouter.scala:87:24] wire _out_T_9414 = ~out_rimask_967; // @[RegisterRouter.scala:87:24] wire _out_T_9415 = ~out_wimask_967; // @[RegisterRouter.scala:87:24] wire _out_T_9416 = ~out_romask_967; // @[RegisterRouter.scala:87:24] wire _out_T_9417 = ~out_womask_967; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_826 = {hi_651, flags_0_go, _out_prepend_T_826}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9418 = out_prepend_826; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9419 = _out_T_9418; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_827 = _out_T_9419; // @[RegisterRouter.scala:87:24] wire out_rimask_968 = |_out_rimask_T_968; // @[RegisterRouter.scala:87:24] wire out_wimask_968 = &_out_wimask_T_968; // @[RegisterRouter.scala:87:24] wire out_romask_968 = |_out_romask_T_968; // @[RegisterRouter.scala:87:24] wire out_womask_968 = &_out_womask_T_968; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_968 = out_rivalid_1_822 & out_rimask_968; // @[RegisterRouter.scala:87:24] wire _out_T_9421 = out_f_rivalid_968; // @[RegisterRouter.scala:87:24] wire out_f_roready_968 = out_roready_1_822 & out_romask_968; // @[RegisterRouter.scala:87:24] wire _out_T_9422 = out_f_roready_968; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_968 = out_wivalid_1_822 & out_wimask_968; // @[RegisterRouter.scala:87:24] wire out_f_woready_968 = out_woready_1_822 & out_womask_968; // @[RegisterRouter.scala:87:24] wire _out_T_9423 = ~out_rimask_968; // @[RegisterRouter.scala:87:24] wire _out_T_9424 = ~out_wimask_968; // @[RegisterRouter.scala:87:24] wire _out_T_9425 = ~out_romask_968; // @[RegisterRouter.scala:87:24] wire _out_T_9426 = ~out_womask_968; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_827 = {hi_652, flags_0_go, _out_prepend_T_827}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9427 = out_prepend_827; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9428 = _out_T_9427; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_828 = _out_T_9428; // @[RegisterRouter.scala:87:24] wire out_rimask_969 = |_out_rimask_T_969; // @[RegisterRouter.scala:87:24] wire out_wimask_969 = &_out_wimask_T_969; // @[RegisterRouter.scala:87:24] wire out_romask_969 = |_out_romask_T_969; // @[RegisterRouter.scala:87:24] wire out_womask_969 = &_out_womask_T_969; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_969 = out_rivalid_1_823 & out_rimask_969; // @[RegisterRouter.scala:87:24] wire _out_T_9430 = out_f_rivalid_969; // @[RegisterRouter.scala:87:24] wire out_f_roready_969 = out_roready_1_823 & out_romask_969; // @[RegisterRouter.scala:87:24] wire _out_T_9431 = out_f_roready_969; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_969 = out_wivalid_1_823 & out_wimask_969; // @[RegisterRouter.scala:87:24] wire out_f_woready_969 = out_woready_1_823 & out_womask_969; // @[RegisterRouter.scala:87:24] wire _out_T_9432 = ~out_rimask_969; // @[RegisterRouter.scala:87:24] wire _out_T_9433 = ~out_wimask_969; // @[RegisterRouter.scala:87:24] wire _out_T_9434 = ~out_romask_969; // @[RegisterRouter.scala:87:24] wire _out_T_9435 = ~out_womask_969; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_828 = {hi_653, flags_0_go, _out_prepend_T_828}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9436 = out_prepend_828; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9437 = _out_T_9436; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_829 = _out_T_9437; // @[RegisterRouter.scala:87:24] wire out_rimask_970 = |_out_rimask_T_970; // @[RegisterRouter.scala:87:24] wire out_wimask_970 = &_out_wimask_T_970; // @[RegisterRouter.scala:87:24] wire out_romask_970 = |_out_romask_T_970; // @[RegisterRouter.scala:87:24] wire out_womask_970 = &_out_womask_T_970; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_970 = out_rivalid_1_824 & out_rimask_970; // @[RegisterRouter.scala:87:24] wire _out_T_9439 = out_f_rivalid_970; // @[RegisterRouter.scala:87:24] wire out_f_roready_970 = out_roready_1_824 & out_romask_970; // @[RegisterRouter.scala:87:24] wire _out_T_9440 = out_f_roready_970; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_970 = out_wivalid_1_824 & out_wimask_970; // @[RegisterRouter.scala:87:24] wire out_f_woready_970 = out_woready_1_824 & out_womask_970; // @[RegisterRouter.scala:87:24] wire _out_T_9441 = ~out_rimask_970; // @[RegisterRouter.scala:87:24] wire _out_T_9442 = ~out_wimask_970; // @[RegisterRouter.scala:87:24] wire _out_T_9443 = ~out_romask_970; // @[RegisterRouter.scala:87:24] wire _out_T_9444 = ~out_womask_970; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_829 = {hi_654, flags_0_go, _out_prepend_T_829}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9445 = out_prepend_829; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9446 = _out_T_9445; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_830 = _out_T_9446; // @[RegisterRouter.scala:87:24] wire out_rimask_971 = |_out_rimask_T_971; // @[RegisterRouter.scala:87:24] wire out_wimask_971 = &_out_wimask_T_971; // @[RegisterRouter.scala:87:24] wire out_romask_971 = |_out_romask_T_971; // @[RegisterRouter.scala:87:24] wire out_womask_971 = &_out_womask_T_971; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_971 = out_rivalid_1_825 & out_rimask_971; // @[RegisterRouter.scala:87:24] wire _out_T_9448 = out_f_rivalid_971; // @[RegisterRouter.scala:87:24] wire out_f_roready_971 = out_roready_1_825 & out_romask_971; // @[RegisterRouter.scala:87:24] wire _out_T_9449 = out_f_roready_971; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_971 = out_wivalid_1_825 & out_wimask_971; // @[RegisterRouter.scala:87:24] wire out_f_woready_971 = out_woready_1_825 & out_womask_971; // @[RegisterRouter.scala:87:24] wire _out_T_9450 = ~out_rimask_971; // @[RegisterRouter.scala:87:24] wire _out_T_9451 = ~out_wimask_971; // @[RegisterRouter.scala:87:24] wire _out_T_9452 = ~out_romask_971; // @[RegisterRouter.scala:87:24] wire _out_T_9453 = ~out_womask_971; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_830 = {hi_655, flags_0_go, _out_prepend_T_830}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9454 = out_prepend_830; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9455 = _out_T_9454; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_831 = _out_T_9455; // @[RegisterRouter.scala:87:24] wire out_rimask_972 = |_out_rimask_T_972; // @[RegisterRouter.scala:87:24] wire out_wimask_972 = &_out_wimask_T_972; // @[RegisterRouter.scala:87:24] wire out_romask_972 = |_out_romask_T_972; // @[RegisterRouter.scala:87:24] wire out_womask_972 = &_out_womask_T_972; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_972 = out_rivalid_1_826 & out_rimask_972; // @[RegisterRouter.scala:87:24] wire _out_T_9457 = out_f_rivalid_972; // @[RegisterRouter.scala:87:24] wire out_f_roready_972 = out_roready_1_826 & out_romask_972; // @[RegisterRouter.scala:87:24] wire _out_T_9458 = out_f_roready_972; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_972 = out_wivalid_1_826 & out_wimask_972; // @[RegisterRouter.scala:87:24] wire out_f_woready_972 = out_woready_1_826 & out_womask_972; // @[RegisterRouter.scala:87:24] wire _out_T_9459 = ~out_rimask_972; // @[RegisterRouter.scala:87:24] wire _out_T_9460 = ~out_wimask_972; // @[RegisterRouter.scala:87:24] wire _out_T_9461 = ~out_romask_972; // @[RegisterRouter.scala:87:24] wire _out_T_9462 = ~out_womask_972; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_831 = {hi_656, flags_0_go, _out_prepend_T_831}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9463 = out_prepend_831; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9464 = _out_T_9463; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_209 = _out_T_9464; // @[MuxLiteral.scala:49:48] wire out_rimask_973 = |_out_rimask_T_973; // @[RegisterRouter.scala:87:24] wire out_wimask_973 = &_out_wimask_T_973; // @[RegisterRouter.scala:87:24] wire out_romask_973 = |_out_romask_T_973; // @[RegisterRouter.scala:87:24] wire out_womask_973 = &_out_womask_T_973; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_973 = out_rivalid_1_827 & out_rimask_973; // @[RegisterRouter.scala:87:24] wire _out_T_9466 = out_f_rivalid_973; // @[RegisterRouter.scala:87:24] wire out_f_roready_973 = out_roready_1_827 & out_romask_973; // @[RegisterRouter.scala:87:24] wire _out_T_9467 = out_f_roready_973; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_973 = out_wivalid_1_827 & out_wimask_973; // @[RegisterRouter.scala:87:24] wire _out_T_9468 = out_f_wivalid_973; // @[RegisterRouter.scala:87:24] wire out_f_woready_973 = out_woready_1_827 & out_womask_973; // @[RegisterRouter.scala:87:24] wire _out_T_9469 = out_f_woready_973; // @[RegisterRouter.scala:87:24] wire _out_T_9470 = ~out_rimask_973; // @[RegisterRouter.scala:87:24] wire _out_T_9471 = ~out_wimask_973; // @[RegisterRouter.scala:87:24] wire _out_T_9472 = ~out_romask_973; // @[RegisterRouter.scala:87:24] wire _out_T_9473 = ~out_womask_973; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9475 = _out_T_9474; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_832 = _out_T_9475; // @[RegisterRouter.scala:87:24] wire out_rimask_974 = |_out_rimask_T_974; // @[RegisterRouter.scala:87:24] wire out_wimask_974 = &_out_wimask_T_974; // @[RegisterRouter.scala:87:24] wire out_romask_974 = |_out_romask_T_974; // @[RegisterRouter.scala:87:24] wire out_womask_974 = &_out_womask_T_974; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_974 = out_rivalid_1_828 & out_rimask_974; // @[RegisterRouter.scala:87:24] wire _out_T_9477 = out_f_rivalid_974; // @[RegisterRouter.scala:87:24] wire out_f_roready_974 = out_roready_1_828 & out_romask_974; // @[RegisterRouter.scala:87:24] wire _out_T_9478 = out_f_roready_974; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_974 = out_wivalid_1_828 & out_wimask_974; // @[RegisterRouter.scala:87:24] wire _out_T_9479 = out_f_wivalid_974; // @[RegisterRouter.scala:87:24] wire out_f_woready_974 = out_woready_1_828 & out_womask_974; // @[RegisterRouter.scala:87:24] wire _out_T_9480 = out_f_woready_974; // @[RegisterRouter.scala:87:24] wire _out_T_9481 = ~out_rimask_974; // @[RegisterRouter.scala:87:24] wire _out_T_9482 = ~out_wimask_974; // @[RegisterRouter.scala:87:24] wire _out_T_9483 = ~out_romask_974; // @[RegisterRouter.scala:87:24] wire _out_T_9484 = ~out_womask_974; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_832 = {abstractDataMem_1, _out_prepend_T_832}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9485 = out_prepend_832; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9486 = _out_T_9485; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_833 = _out_T_9486; // @[RegisterRouter.scala:87:24] wire out_rimask_975 = |_out_rimask_T_975; // @[RegisterRouter.scala:87:24] wire out_wimask_975 = &_out_wimask_T_975; // @[RegisterRouter.scala:87:24] wire out_romask_975 = |_out_romask_T_975; // @[RegisterRouter.scala:87:24] wire out_womask_975 = &_out_womask_T_975; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_975 = out_rivalid_1_829 & out_rimask_975; // @[RegisterRouter.scala:87:24] wire _out_T_9488 = out_f_rivalid_975; // @[RegisterRouter.scala:87:24] wire out_f_roready_975 = out_roready_1_829 & out_romask_975; // @[RegisterRouter.scala:87:24] wire _out_T_9489 = out_f_roready_975; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_975 = out_wivalid_1_829 & out_wimask_975; // @[RegisterRouter.scala:87:24] wire _out_T_9490 = out_f_wivalid_975; // @[RegisterRouter.scala:87:24] wire out_f_woready_975 = out_woready_1_829 & out_womask_975; // @[RegisterRouter.scala:87:24] wire _out_T_9491 = out_f_woready_975; // @[RegisterRouter.scala:87:24] wire _out_T_9492 = ~out_rimask_975; // @[RegisterRouter.scala:87:24] wire _out_T_9493 = ~out_wimask_975; // @[RegisterRouter.scala:87:24] wire _out_T_9494 = ~out_romask_975; // @[RegisterRouter.scala:87:24] wire _out_T_9495 = ~out_womask_975; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_833 = {abstractDataMem_2, _out_prepend_T_833}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9496 = out_prepend_833; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9497 = _out_T_9496; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_834 = _out_T_9497; // @[RegisterRouter.scala:87:24] wire out_rimask_976 = |_out_rimask_T_976; // @[RegisterRouter.scala:87:24] wire out_wimask_976 = &_out_wimask_T_976; // @[RegisterRouter.scala:87:24] wire out_romask_976 = |_out_romask_T_976; // @[RegisterRouter.scala:87:24] wire out_womask_976 = &_out_womask_T_976; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_976 = out_rivalid_1_830 & out_rimask_976; // @[RegisterRouter.scala:87:24] wire _out_T_9499 = out_f_rivalid_976; // @[RegisterRouter.scala:87:24] wire out_f_roready_976 = out_roready_1_830 & out_romask_976; // @[RegisterRouter.scala:87:24] wire _out_T_9500 = out_f_roready_976; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_976 = out_wivalid_1_830 & out_wimask_976; // @[RegisterRouter.scala:87:24] wire _out_T_9501 = out_f_wivalid_976; // @[RegisterRouter.scala:87:24] wire out_f_woready_976 = out_woready_1_830 & out_womask_976; // @[RegisterRouter.scala:87:24] wire _out_T_9502 = out_f_woready_976; // @[RegisterRouter.scala:87:24] wire _out_T_9503 = ~out_rimask_976; // @[RegisterRouter.scala:87:24] wire _out_T_9504 = ~out_wimask_976; // @[RegisterRouter.scala:87:24] wire _out_T_9505 = ~out_romask_976; // @[RegisterRouter.scala:87:24] wire _out_T_9506 = ~out_womask_976; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_834 = {abstractDataMem_3, _out_prepend_T_834}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9507 = out_prepend_834; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9508 = _out_T_9507; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_835 = _out_T_9508; // @[RegisterRouter.scala:87:24] wire out_rimask_977 = |_out_rimask_T_977; // @[RegisterRouter.scala:87:24] wire out_wimask_977 = &_out_wimask_T_977; // @[RegisterRouter.scala:87:24] wire out_romask_977 = |_out_romask_T_977; // @[RegisterRouter.scala:87:24] wire out_womask_977 = &_out_womask_T_977; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_977 = out_rivalid_1_831 & out_rimask_977; // @[RegisterRouter.scala:87:24] wire _out_T_9510 = out_f_rivalid_977; // @[RegisterRouter.scala:87:24] wire out_f_roready_977 = out_roready_1_831 & out_romask_977; // @[RegisterRouter.scala:87:24] wire _out_T_9511 = out_f_roready_977; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_977 = out_wivalid_1_831 & out_wimask_977; // @[RegisterRouter.scala:87:24] wire _out_T_9512 = out_f_wivalid_977; // @[RegisterRouter.scala:87:24] wire out_f_woready_977 = out_woready_1_831 & out_womask_977; // @[RegisterRouter.scala:87:24] wire _out_T_9513 = out_f_woready_977; // @[RegisterRouter.scala:87:24] wire _out_T_9514 = ~out_rimask_977; // @[RegisterRouter.scala:87:24] wire _out_T_9515 = ~out_wimask_977; // @[RegisterRouter.scala:87:24] wire _out_T_9516 = ~out_romask_977; // @[RegisterRouter.scala:87:24] wire _out_T_9517 = ~out_womask_977; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_835 = {abstractDataMem_4, _out_prepend_T_835}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9518 = out_prepend_835; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9519 = _out_T_9518; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_836 = _out_T_9519; // @[RegisterRouter.scala:87:24] wire out_rimask_978 = |_out_rimask_T_978; // @[RegisterRouter.scala:87:24] wire out_wimask_978 = &_out_wimask_T_978; // @[RegisterRouter.scala:87:24] wire out_romask_978 = |_out_romask_T_978; // @[RegisterRouter.scala:87:24] wire out_womask_978 = &_out_womask_T_978; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_978 = out_rivalid_1_832 & out_rimask_978; // @[RegisterRouter.scala:87:24] wire _out_T_9521 = out_f_rivalid_978; // @[RegisterRouter.scala:87:24] wire out_f_roready_978 = out_roready_1_832 & out_romask_978; // @[RegisterRouter.scala:87:24] wire _out_T_9522 = out_f_roready_978; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_978 = out_wivalid_1_832 & out_wimask_978; // @[RegisterRouter.scala:87:24] wire _out_T_9523 = out_f_wivalid_978; // @[RegisterRouter.scala:87:24] wire out_f_woready_978 = out_woready_1_832 & out_womask_978; // @[RegisterRouter.scala:87:24] wire _out_T_9524 = out_f_woready_978; // @[RegisterRouter.scala:87:24] wire _out_T_9525 = ~out_rimask_978; // @[RegisterRouter.scala:87:24] wire _out_T_9526 = ~out_wimask_978; // @[RegisterRouter.scala:87:24] wire _out_T_9527 = ~out_romask_978; // @[RegisterRouter.scala:87:24] wire _out_T_9528 = ~out_womask_978; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_836 = {abstractDataMem_5, _out_prepend_T_836}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9529 = out_prepend_836; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9530 = _out_T_9529; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_837 = _out_T_9530; // @[RegisterRouter.scala:87:24] wire out_rimask_979 = |_out_rimask_T_979; // @[RegisterRouter.scala:87:24] wire out_wimask_979 = &_out_wimask_T_979; // @[RegisterRouter.scala:87:24] wire out_romask_979 = |_out_romask_T_979; // @[RegisterRouter.scala:87:24] wire out_womask_979 = &_out_womask_T_979; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_979 = out_rivalid_1_833 & out_rimask_979; // @[RegisterRouter.scala:87:24] wire _out_T_9532 = out_f_rivalid_979; // @[RegisterRouter.scala:87:24] wire out_f_roready_979 = out_roready_1_833 & out_romask_979; // @[RegisterRouter.scala:87:24] wire _out_T_9533 = out_f_roready_979; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_979 = out_wivalid_1_833 & out_wimask_979; // @[RegisterRouter.scala:87:24] wire _out_T_9534 = out_f_wivalid_979; // @[RegisterRouter.scala:87:24] wire out_f_woready_979 = out_woready_1_833 & out_womask_979; // @[RegisterRouter.scala:87:24] wire _out_T_9535 = out_f_woready_979; // @[RegisterRouter.scala:87:24] wire _out_T_9536 = ~out_rimask_979; // @[RegisterRouter.scala:87:24] wire _out_T_9537 = ~out_wimask_979; // @[RegisterRouter.scala:87:24] wire _out_T_9538 = ~out_romask_979; // @[RegisterRouter.scala:87:24] wire _out_T_9539 = ~out_womask_979; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_837 = {abstractDataMem_6, _out_prepend_T_837}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9540 = out_prepend_837; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9541 = _out_T_9540; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_838 = _out_T_9541; // @[RegisterRouter.scala:87:24] wire out_rimask_980 = |_out_rimask_T_980; // @[RegisterRouter.scala:87:24] wire out_wimask_980 = &_out_wimask_T_980; // @[RegisterRouter.scala:87:24] wire out_romask_980 = |_out_romask_T_980; // @[RegisterRouter.scala:87:24] wire out_womask_980 = &_out_womask_T_980; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_980 = out_rivalid_1_834 & out_rimask_980; // @[RegisterRouter.scala:87:24] wire _out_T_9543 = out_f_rivalid_980; // @[RegisterRouter.scala:87:24] wire out_f_roready_980 = out_roready_1_834 & out_romask_980; // @[RegisterRouter.scala:87:24] wire _out_T_9544 = out_f_roready_980; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_980 = out_wivalid_1_834 & out_wimask_980; // @[RegisterRouter.scala:87:24] wire _out_T_9545 = out_f_wivalid_980; // @[RegisterRouter.scala:87:24] wire out_f_woready_980 = out_woready_1_834 & out_womask_980; // @[RegisterRouter.scala:87:24] wire _out_T_9546 = out_f_woready_980; // @[RegisterRouter.scala:87:24] wire _out_T_9547 = ~out_rimask_980; // @[RegisterRouter.scala:87:24] wire _out_T_9548 = ~out_wimask_980; // @[RegisterRouter.scala:87:24] wire _out_T_9549 = ~out_romask_980; // @[RegisterRouter.scala:87:24] wire _out_T_9550 = ~out_womask_980; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_838 = {abstractDataMem_7, _out_prepend_T_838}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9551 = out_prepend_838; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9552 = _out_T_9551; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_112 = _out_T_9552; // @[MuxLiteral.scala:49:48] wire out_rimask_981 = |_out_rimask_T_981; // @[RegisterRouter.scala:87:24] wire out_wimask_981 = &_out_wimask_T_981; // @[RegisterRouter.scala:87:24] wire out_romask_981 = |_out_romask_T_981; // @[RegisterRouter.scala:87:24] wire out_womask_981 = &_out_womask_T_981; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_981 = out_rivalid_1_835 & out_rimask_981; // @[RegisterRouter.scala:87:24] wire _out_T_9554 = out_f_rivalid_981; // @[RegisterRouter.scala:87:24] wire out_f_roready_981 = out_roready_1_835 & out_romask_981; // @[RegisterRouter.scala:87:24] wire _out_T_9555 = out_f_roready_981; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_981 = out_wivalid_1_835 & out_wimask_981; // @[RegisterRouter.scala:87:24] wire out_f_woready_981 = out_woready_1_835 & out_womask_981; // @[RegisterRouter.scala:87:24] wire _out_T_9556 = ~out_rimask_981; // @[RegisterRouter.scala:87:24] wire _out_T_9557 = ~out_wimask_981; // @[RegisterRouter.scala:87:24] wire _out_T_9558 = ~out_romask_981; // @[RegisterRouter.scala:87:24] wire _out_T_9559 = ~out_womask_981; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9561 = _out_T_9560; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_839 = _out_T_9561; // @[RegisterRouter.scala:87:24] wire out_rimask_982 = |_out_rimask_T_982; // @[RegisterRouter.scala:87:24] wire out_wimask_982 = &_out_wimask_T_982; // @[RegisterRouter.scala:87:24] wire out_romask_982 = |_out_romask_T_982; // @[RegisterRouter.scala:87:24] wire out_womask_982 = &_out_womask_T_982; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_982 = out_rivalid_1_836 & out_rimask_982; // @[RegisterRouter.scala:87:24] wire _out_T_9563 = out_f_rivalid_982; // @[RegisterRouter.scala:87:24] wire out_f_roready_982 = out_roready_1_836 & out_romask_982; // @[RegisterRouter.scala:87:24] wire _out_T_9564 = out_f_roready_982; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_982 = out_wivalid_1_836 & out_wimask_982; // @[RegisterRouter.scala:87:24] wire out_f_woready_982 = out_woready_1_836 & out_womask_982; // @[RegisterRouter.scala:87:24] wire _out_T_9565 = ~out_rimask_982; // @[RegisterRouter.scala:87:24] wire _out_T_9566 = ~out_wimask_982; // @[RegisterRouter.scala:87:24] wire _out_T_9567 = ~out_romask_982; // @[RegisterRouter.scala:87:24] wire _out_T_9568 = ~out_womask_982; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_839 = {hi_530, flags_0_go, _out_prepend_T_839}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9569 = out_prepend_839; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9570 = _out_T_9569; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_840 = _out_T_9570; // @[RegisterRouter.scala:87:24] wire out_rimask_983 = |_out_rimask_T_983; // @[RegisterRouter.scala:87:24] wire out_wimask_983 = &_out_wimask_T_983; // @[RegisterRouter.scala:87:24] wire out_romask_983 = |_out_romask_T_983; // @[RegisterRouter.scala:87:24] wire out_womask_983 = &_out_womask_T_983; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_983 = out_rivalid_1_837 & out_rimask_983; // @[RegisterRouter.scala:87:24] wire _out_T_9572 = out_f_rivalid_983; // @[RegisterRouter.scala:87:24] wire out_f_roready_983 = out_roready_1_837 & out_romask_983; // @[RegisterRouter.scala:87:24] wire _out_T_9573 = out_f_roready_983; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_983 = out_wivalid_1_837 & out_wimask_983; // @[RegisterRouter.scala:87:24] wire out_f_woready_983 = out_woready_1_837 & out_womask_983; // @[RegisterRouter.scala:87:24] wire _out_T_9574 = ~out_rimask_983; // @[RegisterRouter.scala:87:24] wire _out_T_9575 = ~out_wimask_983; // @[RegisterRouter.scala:87:24] wire _out_T_9576 = ~out_romask_983; // @[RegisterRouter.scala:87:24] wire _out_T_9577 = ~out_womask_983; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_840 = {hi_531, flags_0_go, _out_prepend_T_840}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9578 = out_prepend_840; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9579 = _out_T_9578; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_841 = _out_T_9579; // @[RegisterRouter.scala:87:24] wire out_rimask_984 = |_out_rimask_T_984; // @[RegisterRouter.scala:87:24] wire out_wimask_984 = &_out_wimask_T_984; // @[RegisterRouter.scala:87:24] wire out_romask_984 = |_out_romask_T_984; // @[RegisterRouter.scala:87:24] wire out_womask_984 = &_out_womask_T_984; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_984 = out_rivalid_1_838 & out_rimask_984; // @[RegisterRouter.scala:87:24] wire _out_T_9581 = out_f_rivalid_984; // @[RegisterRouter.scala:87:24] wire out_f_roready_984 = out_roready_1_838 & out_romask_984; // @[RegisterRouter.scala:87:24] wire _out_T_9582 = out_f_roready_984; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_984 = out_wivalid_1_838 & out_wimask_984; // @[RegisterRouter.scala:87:24] wire out_f_woready_984 = out_woready_1_838 & out_womask_984; // @[RegisterRouter.scala:87:24] wire _out_T_9583 = ~out_rimask_984; // @[RegisterRouter.scala:87:24] wire _out_T_9584 = ~out_wimask_984; // @[RegisterRouter.scala:87:24] wire _out_T_9585 = ~out_romask_984; // @[RegisterRouter.scala:87:24] wire _out_T_9586 = ~out_womask_984; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_841 = {hi_532, flags_0_go, _out_prepend_T_841}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9587 = out_prepend_841; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9588 = _out_T_9587; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_842 = _out_T_9588; // @[RegisterRouter.scala:87:24] wire out_rimask_985 = |_out_rimask_T_985; // @[RegisterRouter.scala:87:24] wire out_wimask_985 = &_out_wimask_T_985; // @[RegisterRouter.scala:87:24] wire out_romask_985 = |_out_romask_T_985; // @[RegisterRouter.scala:87:24] wire out_womask_985 = &_out_womask_T_985; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_985 = out_rivalid_1_839 & out_rimask_985; // @[RegisterRouter.scala:87:24] wire _out_T_9590 = out_f_rivalid_985; // @[RegisterRouter.scala:87:24] wire out_f_roready_985 = out_roready_1_839 & out_romask_985; // @[RegisterRouter.scala:87:24] wire _out_T_9591 = out_f_roready_985; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_985 = out_wivalid_1_839 & out_wimask_985; // @[RegisterRouter.scala:87:24] wire out_f_woready_985 = out_woready_1_839 & out_womask_985; // @[RegisterRouter.scala:87:24] wire _out_T_9592 = ~out_rimask_985; // @[RegisterRouter.scala:87:24] wire _out_T_9593 = ~out_wimask_985; // @[RegisterRouter.scala:87:24] wire _out_T_9594 = ~out_romask_985; // @[RegisterRouter.scala:87:24] wire _out_T_9595 = ~out_womask_985; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_842 = {hi_533, flags_0_go, _out_prepend_T_842}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9596 = out_prepend_842; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9597 = _out_T_9596; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_843 = _out_T_9597; // @[RegisterRouter.scala:87:24] wire out_rimask_986 = |_out_rimask_T_986; // @[RegisterRouter.scala:87:24] wire out_wimask_986 = &_out_wimask_T_986; // @[RegisterRouter.scala:87:24] wire out_romask_986 = |_out_romask_T_986; // @[RegisterRouter.scala:87:24] wire out_womask_986 = &_out_womask_T_986; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_986 = out_rivalid_1_840 & out_rimask_986; // @[RegisterRouter.scala:87:24] wire _out_T_9599 = out_f_rivalid_986; // @[RegisterRouter.scala:87:24] wire out_f_roready_986 = out_roready_1_840 & out_romask_986; // @[RegisterRouter.scala:87:24] wire _out_T_9600 = out_f_roready_986; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_986 = out_wivalid_1_840 & out_wimask_986; // @[RegisterRouter.scala:87:24] wire out_f_woready_986 = out_woready_1_840 & out_womask_986; // @[RegisterRouter.scala:87:24] wire _out_T_9601 = ~out_rimask_986; // @[RegisterRouter.scala:87:24] wire _out_T_9602 = ~out_wimask_986; // @[RegisterRouter.scala:87:24] wire _out_T_9603 = ~out_romask_986; // @[RegisterRouter.scala:87:24] wire _out_T_9604 = ~out_womask_986; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_843 = {hi_534, flags_0_go, _out_prepend_T_843}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9605 = out_prepend_843; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9606 = _out_T_9605; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_844 = _out_T_9606; // @[RegisterRouter.scala:87:24] wire out_rimask_987 = |_out_rimask_T_987; // @[RegisterRouter.scala:87:24] wire out_wimask_987 = &_out_wimask_T_987; // @[RegisterRouter.scala:87:24] wire out_romask_987 = |_out_romask_T_987; // @[RegisterRouter.scala:87:24] wire out_womask_987 = &_out_womask_T_987; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_987 = out_rivalid_1_841 & out_rimask_987; // @[RegisterRouter.scala:87:24] wire _out_T_9608 = out_f_rivalid_987; // @[RegisterRouter.scala:87:24] wire out_f_roready_987 = out_roready_1_841 & out_romask_987; // @[RegisterRouter.scala:87:24] wire _out_T_9609 = out_f_roready_987; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_987 = out_wivalid_1_841 & out_wimask_987; // @[RegisterRouter.scala:87:24] wire out_f_woready_987 = out_woready_1_841 & out_womask_987; // @[RegisterRouter.scala:87:24] wire _out_T_9610 = ~out_rimask_987; // @[RegisterRouter.scala:87:24] wire _out_T_9611 = ~out_wimask_987; // @[RegisterRouter.scala:87:24] wire _out_T_9612 = ~out_romask_987; // @[RegisterRouter.scala:87:24] wire _out_T_9613 = ~out_womask_987; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_844 = {hi_535, flags_0_go, _out_prepend_T_844}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9614 = out_prepend_844; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9615 = _out_T_9614; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_845 = _out_T_9615; // @[RegisterRouter.scala:87:24] wire out_rimask_988 = |_out_rimask_T_988; // @[RegisterRouter.scala:87:24] wire out_wimask_988 = &_out_wimask_T_988; // @[RegisterRouter.scala:87:24] wire out_romask_988 = |_out_romask_T_988; // @[RegisterRouter.scala:87:24] wire out_womask_988 = &_out_womask_T_988; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_988 = out_rivalid_1_842 & out_rimask_988; // @[RegisterRouter.scala:87:24] wire _out_T_9617 = out_f_rivalid_988; // @[RegisterRouter.scala:87:24] wire out_f_roready_988 = out_roready_1_842 & out_romask_988; // @[RegisterRouter.scala:87:24] wire _out_T_9618 = out_f_roready_988; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_988 = out_wivalid_1_842 & out_wimask_988; // @[RegisterRouter.scala:87:24] wire out_f_woready_988 = out_woready_1_842 & out_womask_988; // @[RegisterRouter.scala:87:24] wire _out_T_9619 = ~out_rimask_988; // @[RegisterRouter.scala:87:24] wire _out_T_9620 = ~out_wimask_988; // @[RegisterRouter.scala:87:24] wire _out_T_9621 = ~out_romask_988; // @[RegisterRouter.scala:87:24] wire _out_T_9622 = ~out_womask_988; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_845 = {hi_536, flags_0_go, _out_prepend_T_845}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9623 = out_prepend_845; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9624 = _out_T_9623; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_194 = _out_T_9624; // @[MuxLiteral.scala:49:48] wire out_rimask_989 = |_out_rimask_T_989; // @[RegisterRouter.scala:87:24] wire out_wimask_989 = &_out_wimask_T_989; // @[RegisterRouter.scala:87:24] wire out_romask_989 = |_out_romask_T_989; // @[RegisterRouter.scala:87:24] wire out_womask_989 = &_out_womask_T_989; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_989 = out_rivalid_1_843 & out_rimask_989; // @[RegisterRouter.scala:87:24] wire _out_T_9626 = out_f_rivalid_989; // @[RegisterRouter.scala:87:24] wire out_f_roready_989 = out_roready_1_843 & out_romask_989; // @[RegisterRouter.scala:87:24] wire _out_T_9627 = out_f_roready_989; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_989 = out_wivalid_1_843 & out_wimask_989; // @[RegisterRouter.scala:87:24] wire out_f_woready_989 = out_woready_1_843 & out_womask_989; // @[RegisterRouter.scala:87:24] wire _out_T_9628 = ~out_rimask_989; // @[RegisterRouter.scala:87:24] wire _out_T_9629 = ~out_wimask_989; // @[RegisterRouter.scala:87:24] wire _out_T_9630 = ~out_romask_989; // @[RegisterRouter.scala:87:24] wire _out_T_9631 = ~out_womask_989; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9633 = _out_T_9632; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_846 = _out_T_9633; // @[RegisterRouter.scala:87:24] wire out_rimask_990 = |_out_rimask_T_990; // @[RegisterRouter.scala:87:24] wire out_wimask_990 = &_out_wimask_T_990; // @[RegisterRouter.scala:87:24] wire out_romask_990 = |_out_romask_T_990; // @[RegisterRouter.scala:87:24] wire out_womask_990 = &_out_womask_T_990; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_990 = out_rivalid_1_844 & out_rimask_990; // @[RegisterRouter.scala:87:24] wire _out_T_9635 = out_f_rivalid_990; // @[RegisterRouter.scala:87:24] wire out_f_roready_990 = out_roready_1_844 & out_romask_990; // @[RegisterRouter.scala:87:24] wire _out_T_9636 = out_f_roready_990; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_990 = out_wivalid_1_844 & out_wimask_990; // @[RegisterRouter.scala:87:24] wire out_f_woready_990 = out_woready_1_844 & out_womask_990; // @[RegisterRouter.scala:87:24] wire _out_T_9637 = ~out_rimask_990; // @[RegisterRouter.scala:87:24] wire _out_T_9638 = ~out_wimask_990; // @[RegisterRouter.scala:87:24] wire _out_T_9639 = ~out_romask_990; // @[RegisterRouter.scala:87:24] wire _out_T_9640 = ~out_womask_990; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_846 = {hi_138, flags_0_go, _out_prepend_T_846}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9641 = out_prepend_846; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9642 = _out_T_9641; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_847 = _out_T_9642; // @[RegisterRouter.scala:87:24] wire out_rimask_991 = |_out_rimask_T_991; // @[RegisterRouter.scala:87:24] wire out_wimask_991 = &_out_wimask_T_991; // @[RegisterRouter.scala:87:24] wire out_romask_991 = |_out_romask_T_991; // @[RegisterRouter.scala:87:24] wire out_womask_991 = &_out_womask_T_991; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_991 = out_rivalid_1_845 & out_rimask_991; // @[RegisterRouter.scala:87:24] wire _out_T_9644 = out_f_rivalid_991; // @[RegisterRouter.scala:87:24] wire out_f_roready_991 = out_roready_1_845 & out_romask_991; // @[RegisterRouter.scala:87:24] wire _out_T_9645 = out_f_roready_991; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_991 = out_wivalid_1_845 & out_wimask_991; // @[RegisterRouter.scala:87:24] wire out_f_woready_991 = out_woready_1_845 & out_womask_991; // @[RegisterRouter.scala:87:24] wire _out_T_9646 = ~out_rimask_991; // @[RegisterRouter.scala:87:24] wire _out_T_9647 = ~out_wimask_991; // @[RegisterRouter.scala:87:24] wire _out_T_9648 = ~out_romask_991; // @[RegisterRouter.scala:87:24] wire _out_T_9649 = ~out_womask_991; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_847 = {hi_139, flags_0_go, _out_prepend_T_847}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9650 = out_prepend_847; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9651 = _out_T_9650; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_848 = _out_T_9651; // @[RegisterRouter.scala:87:24] wire out_rimask_992 = |_out_rimask_T_992; // @[RegisterRouter.scala:87:24] wire out_wimask_992 = &_out_wimask_T_992; // @[RegisterRouter.scala:87:24] wire out_romask_992 = |_out_romask_T_992; // @[RegisterRouter.scala:87:24] wire out_womask_992 = &_out_womask_T_992; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_992 = out_rivalid_1_846 & out_rimask_992; // @[RegisterRouter.scala:87:24] wire _out_T_9653 = out_f_rivalid_992; // @[RegisterRouter.scala:87:24] wire out_f_roready_992 = out_roready_1_846 & out_romask_992; // @[RegisterRouter.scala:87:24] wire _out_T_9654 = out_f_roready_992; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_992 = out_wivalid_1_846 & out_wimask_992; // @[RegisterRouter.scala:87:24] wire out_f_woready_992 = out_woready_1_846 & out_womask_992; // @[RegisterRouter.scala:87:24] wire _out_T_9655 = ~out_rimask_992; // @[RegisterRouter.scala:87:24] wire _out_T_9656 = ~out_wimask_992; // @[RegisterRouter.scala:87:24] wire _out_T_9657 = ~out_romask_992; // @[RegisterRouter.scala:87:24] wire _out_T_9658 = ~out_womask_992; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_848 = {hi_140, flags_0_go, _out_prepend_T_848}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9659 = out_prepend_848; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9660 = _out_T_9659; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_849 = _out_T_9660; // @[RegisterRouter.scala:87:24] wire out_rimask_993 = |_out_rimask_T_993; // @[RegisterRouter.scala:87:24] wire out_wimask_993 = &_out_wimask_T_993; // @[RegisterRouter.scala:87:24] wire out_romask_993 = |_out_romask_T_993; // @[RegisterRouter.scala:87:24] wire out_womask_993 = &_out_womask_T_993; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_993 = out_rivalid_1_847 & out_rimask_993; // @[RegisterRouter.scala:87:24] wire _out_T_9662 = out_f_rivalid_993; // @[RegisterRouter.scala:87:24] wire out_f_roready_993 = out_roready_1_847 & out_romask_993; // @[RegisterRouter.scala:87:24] wire _out_T_9663 = out_f_roready_993; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_993 = out_wivalid_1_847 & out_wimask_993; // @[RegisterRouter.scala:87:24] wire out_f_woready_993 = out_woready_1_847 & out_womask_993; // @[RegisterRouter.scala:87:24] wire _out_T_9664 = ~out_rimask_993; // @[RegisterRouter.scala:87:24] wire _out_T_9665 = ~out_wimask_993; // @[RegisterRouter.scala:87:24] wire _out_T_9666 = ~out_romask_993; // @[RegisterRouter.scala:87:24] wire _out_T_9667 = ~out_womask_993; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_849 = {hi_141, flags_0_go, _out_prepend_T_849}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9668 = out_prepend_849; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9669 = _out_T_9668; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_850 = _out_T_9669; // @[RegisterRouter.scala:87:24] wire out_rimask_994 = |_out_rimask_T_994; // @[RegisterRouter.scala:87:24] wire out_wimask_994 = &_out_wimask_T_994; // @[RegisterRouter.scala:87:24] wire out_romask_994 = |_out_romask_T_994; // @[RegisterRouter.scala:87:24] wire out_womask_994 = &_out_womask_T_994; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_994 = out_rivalid_1_848 & out_rimask_994; // @[RegisterRouter.scala:87:24] wire _out_T_9671 = out_f_rivalid_994; // @[RegisterRouter.scala:87:24] wire out_f_roready_994 = out_roready_1_848 & out_romask_994; // @[RegisterRouter.scala:87:24] wire _out_T_9672 = out_f_roready_994; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_994 = out_wivalid_1_848 & out_wimask_994; // @[RegisterRouter.scala:87:24] wire out_f_woready_994 = out_woready_1_848 & out_womask_994; // @[RegisterRouter.scala:87:24] wire _out_T_9673 = ~out_rimask_994; // @[RegisterRouter.scala:87:24] wire _out_T_9674 = ~out_wimask_994; // @[RegisterRouter.scala:87:24] wire _out_T_9675 = ~out_romask_994; // @[RegisterRouter.scala:87:24] wire _out_T_9676 = ~out_womask_994; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_850 = {hi_142, flags_0_go, _out_prepend_T_850}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9677 = out_prepend_850; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9678 = _out_T_9677; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_851 = _out_T_9678; // @[RegisterRouter.scala:87:24] wire out_rimask_995 = |_out_rimask_T_995; // @[RegisterRouter.scala:87:24] wire out_wimask_995 = &_out_wimask_T_995; // @[RegisterRouter.scala:87:24] wire out_romask_995 = |_out_romask_T_995; // @[RegisterRouter.scala:87:24] wire out_womask_995 = &_out_womask_T_995; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_995 = out_rivalid_1_849 & out_rimask_995; // @[RegisterRouter.scala:87:24] wire _out_T_9680 = out_f_rivalid_995; // @[RegisterRouter.scala:87:24] wire out_f_roready_995 = out_roready_1_849 & out_romask_995; // @[RegisterRouter.scala:87:24] wire _out_T_9681 = out_f_roready_995; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_995 = out_wivalid_1_849 & out_wimask_995; // @[RegisterRouter.scala:87:24] wire out_f_woready_995 = out_woready_1_849 & out_womask_995; // @[RegisterRouter.scala:87:24] wire _out_T_9682 = ~out_rimask_995; // @[RegisterRouter.scala:87:24] wire _out_T_9683 = ~out_wimask_995; // @[RegisterRouter.scala:87:24] wire _out_T_9684 = ~out_romask_995; // @[RegisterRouter.scala:87:24] wire _out_T_9685 = ~out_womask_995; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_851 = {hi_143, flags_0_go, _out_prepend_T_851}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9686 = out_prepend_851; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9687 = _out_T_9686; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_852 = _out_T_9687; // @[RegisterRouter.scala:87:24] wire out_rimask_996 = |_out_rimask_T_996; // @[RegisterRouter.scala:87:24] wire out_wimask_996 = &_out_wimask_T_996; // @[RegisterRouter.scala:87:24] wire out_romask_996 = |_out_romask_T_996; // @[RegisterRouter.scala:87:24] wire out_womask_996 = &_out_womask_T_996; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_996 = out_rivalid_1_850 & out_rimask_996; // @[RegisterRouter.scala:87:24] wire _out_T_9689 = out_f_rivalid_996; // @[RegisterRouter.scala:87:24] wire out_f_roready_996 = out_roready_1_850 & out_romask_996; // @[RegisterRouter.scala:87:24] wire _out_T_9690 = out_f_roready_996; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_996 = out_wivalid_1_850 & out_wimask_996; // @[RegisterRouter.scala:87:24] wire out_f_woready_996 = out_woready_1_850 & out_womask_996; // @[RegisterRouter.scala:87:24] wire _out_T_9691 = ~out_rimask_996; // @[RegisterRouter.scala:87:24] wire _out_T_9692 = ~out_wimask_996; // @[RegisterRouter.scala:87:24] wire _out_T_9693 = ~out_romask_996; // @[RegisterRouter.scala:87:24] wire _out_T_9694 = ~out_womask_996; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_852 = {hi_144, flags_0_go, _out_prepend_T_852}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9695 = out_prepend_852; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9696 = _out_T_9695; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_145 = _out_T_9696; // @[MuxLiteral.scala:49:48] wire out_rimask_997 = |_out_rimask_T_997; // @[RegisterRouter.scala:87:24] wire out_wimask_997 = &_out_wimask_T_997; // @[RegisterRouter.scala:87:24] wire out_romask_997 = |_out_romask_T_997; // @[RegisterRouter.scala:87:24] wire out_womask_997 = &_out_womask_T_997; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_997 = out_rivalid_1_851 & out_rimask_997; // @[RegisterRouter.scala:87:24] wire _out_T_9698 = out_f_rivalid_997; // @[RegisterRouter.scala:87:24] wire out_f_roready_997 = out_roready_1_851 & out_romask_997; // @[RegisterRouter.scala:87:24] wire _out_T_9699 = out_f_roready_997; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_997 = out_wivalid_1_851 & out_wimask_997; // @[RegisterRouter.scala:87:24] wire out_f_woready_997 = out_woready_1_851 & out_womask_997; // @[RegisterRouter.scala:87:24] wire _out_T_9700 = ~out_rimask_997; // @[RegisterRouter.scala:87:24] wire _out_T_9701 = ~out_wimask_997; // @[RegisterRouter.scala:87:24] wire _out_T_9702 = ~out_romask_997; // @[RegisterRouter.scala:87:24] wire _out_T_9703 = ~out_womask_997; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9705 = _out_T_9704; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_853 = _out_T_9705; // @[RegisterRouter.scala:87:24] wire out_rimask_998 = |_out_rimask_T_998; // @[RegisterRouter.scala:87:24] wire out_wimask_998 = &_out_wimask_T_998; // @[RegisterRouter.scala:87:24] wire out_romask_998 = |_out_romask_T_998; // @[RegisterRouter.scala:87:24] wire out_womask_998 = &_out_womask_T_998; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_998 = out_rivalid_1_852 & out_rimask_998; // @[RegisterRouter.scala:87:24] wire _out_T_9707 = out_f_rivalid_998; // @[RegisterRouter.scala:87:24] wire out_f_roready_998 = out_roready_1_852 & out_romask_998; // @[RegisterRouter.scala:87:24] wire _out_T_9708 = out_f_roready_998; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_998 = out_wivalid_1_852 & out_wimask_998; // @[RegisterRouter.scala:87:24] wire out_f_woready_998 = out_woready_1_852 & out_womask_998; // @[RegisterRouter.scala:87:24] wire _out_T_9709 = ~out_rimask_998; // @[RegisterRouter.scala:87:24] wire _out_T_9710 = ~out_wimask_998; // @[RegisterRouter.scala:87:24] wire _out_T_9711 = ~out_romask_998; // @[RegisterRouter.scala:87:24] wire _out_T_9712 = ~out_womask_998; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_853 = {hi_178, flags_0_go, _out_prepend_T_853}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9713 = out_prepend_853; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9714 = _out_T_9713; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_854 = _out_T_9714; // @[RegisterRouter.scala:87:24] wire out_rimask_999 = |_out_rimask_T_999; // @[RegisterRouter.scala:87:24] wire out_wimask_999 = &_out_wimask_T_999; // @[RegisterRouter.scala:87:24] wire out_romask_999 = |_out_romask_T_999; // @[RegisterRouter.scala:87:24] wire out_womask_999 = &_out_womask_T_999; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_999 = out_rivalid_1_853 & out_rimask_999; // @[RegisterRouter.scala:87:24] wire _out_T_9716 = out_f_rivalid_999; // @[RegisterRouter.scala:87:24] wire out_f_roready_999 = out_roready_1_853 & out_romask_999; // @[RegisterRouter.scala:87:24] wire _out_T_9717 = out_f_roready_999; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_999 = out_wivalid_1_853 & out_wimask_999; // @[RegisterRouter.scala:87:24] wire out_f_woready_999 = out_woready_1_853 & out_womask_999; // @[RegisterRouter.scala:87:24] wire _out_T_9718 = ~out_rimask_999; // @[RegisterRouter.scala:87:24] wire _out_T_9719 = ~out_wimask_999; // @[RegisterRouter.scala:87:24] wire _out_T_9720 = ~out_romask_999; // @[RegisterRouter.scala:87:24] wire _out_T_9721 = ~out_womask_999; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_854 = {hi_179, flags_0_go, _out_prepend_T_854}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9722 = out_prepend_854; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9723 = _out_T_9722; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_855 = _out_T_9723; // @[RegisterRouter.scala:87:24] wire out_rimask_1000 = |_out_rimask_T_1000; // @[RegisterRouter.scala:87:24] wire out_wimask_1000 = &_out_wimask_T_1000; // @[RegisterRouter.scala:87:24] wire out_romask_1000 = |_out_romask_T_1000; // @[RegisterRouter.scala:87:24] wire out_womask_1000 = &_out_womask_T_1000; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1000 = out_rivalid_1_854 & out_rimask_1000; // @[RegisterRouter.scala:87:24] wire _out_T_9725 = out_f_rivalid_1000; // @[RegisterRouter.scala:87:24] wire out_f_roready_1000 = out_roready_1_854 & out_romask_1000; // @[RegisterRouter.scala:87:24] wire _out_T_9726 = out_f_roready_1000; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1000 = out_wivalid_1_854 & out_wimask_1000; // @[RegisterRouter.scala:87:24] wire out_f_woready_1000 = out_woready_1_854 & out_womask_1000; // @[RegisterRouter.scala:87:24] wire _out_T_9727 = ~out_rimask_1000; // @[RegisterRouter.scala:87:24] wire _out_T_9728 = ~out_wimask_1000; // @[RegisterRouter.scala:87:24] wire _out_T_9729 = ~out_romask_1000; // @[RegisterRouter.scala:87:24] wire _out_T_9730 = ~out_womask_1000; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_855 = {hi_180, flags_0_go, _out_prepend_T_855}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9731 = out_prepend_855; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9732 = _out_T_9731; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_856 = _out_T_9732; // @[RegisterRouter.scala:87:24] wire out_rimask_1001 = |_out_rimask_T_1001; // @[RegisterRouter.scala:87:24] wire out_wimask_1001 = &_out_wimask_T_1001; // @[RegisterRouter.scala:87:24] wire out_romask_1001 = |_out_romask_T_1001; // @[RegisterRouter.scala:87:24] wire out_womask_1001 = &_out_womask_T_1001; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1001 = out_rivalid_1_855 & out_rimask_1001; // @[RegisterRouter.scala:87:24] wire _out_T_9734 = out_f_rivalid_1001; // @[RegisterRouter.scala:87:24] wire out_f_roready_1001 = out_roready_1_855 & out_romask_1001; // @[RegisterRouter.scala:87:24] wire _out_T_9735 = out_f_roready_1001; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1001 = out_wivalid_1_855 & out_wimask_1001; // @[RegisterRouter.scala:87:24] wire out_f_woready_1001 = out_woready_1_855 & out_womask_1001; // @[RegisterRouter.scala:87:24] wire _out_T_9736 = ~out_rimask_1001; // @[RegisterRouter.scala:87:24] wire _out_T_9737 = ~out_wimask_1001; // @[RegisterRouter.scala:87:24] wire _out_T_9738 = ~out_romask_1001; // @[RegisterRouter.scala:87:24] wire _out_T_9739 = ~out_womask_1001; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_856 = {hi_181, flags_0_go, _out_prepend_T_856}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9740 = out_prepend_856; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9741 = _out_T_9740; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_857 = _out_T_9741; // @[RegisterRouter.scala:87:24] wire out_rimask_1002 = |_out_rimask_T_1002; // @[RegisterRouter.scala:87:24] wire out_wimask_1002 = &_out_wimask_T_1002; // @[RegisterRouter.scala:87:24] wire out_romask_1002 = |_out_romask_T_1002; // @[RegisterRouter.scala:87:24] wire out_womask_1002 = &_out_womask_T_1002; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1002 = out_rivalid_1_856 & out_rimask_1002; // @[RegisterRouter.scala:87:24] wire _out_T_9743 = out_f_rivalid_1002; // @[RegisterRouter.scala:87:24] wire out_f_roready_1002 = out_roready_1_856 & out_romask_1002; // @[RegisterRouter.scala:87:24] wire _out_T_9744 = out_f_roready_1002; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1002 = out_wivalid_1_856 & out_wimask_1002; // @[RegisterRouter.scala:87:24] wire out_f_woready_1002 = out_woready_1_856 & out_womask_1002; // @[RegisterRouter.scala:87:24] wire _out_T_9745 = ~out_rimask_1002; // @[RegisterRouter.scala:87:24] wire _out_T_9746 = ~out_wimask_1002; // @[RegisterRouter.scala:87:24] wire _out_T_9747 = ~out_romask_1002; // @[RegisterRouter.scala:87:24] wire _out_T_9748 = ~out_womask_1002; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_857 = {hi_182, flags_0_go, _out_prepend_T_857}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9749 = out_prepend_857; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9750 = _out_T_9749; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_858 = _out_T_9750; // @[RegisterRouter.scala:87:24] wire out_rimask_1003 = |_out_rimask_T_1003; // @[RegisterRouter.scala:87:24] wire out_wimask_1003 = &_out_wimask_T_1003; // @[RegisterRouter.scala:87:24] wire out_romask_1003 = |_out_romask_T_1003; // @[RegisterRouter.scala:87:24] wire out_womask_1003 = &_out_womask_T_1003; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1003 = out_rivalid_1_857 & out_rimask_1003; // @[RegisterRouter.scala:87:24] wire _out_T_9752 = out_f_rivalid_1003; // @[RegisterRouter.scala:87:24] wire out_f_roready_1003 = out_roready_1_857 & out_romask_1003; // @[RegisterRouter.scala:87:24] wire _out_T_9753 = out_f_roready_1003; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1003 = out_wivalid_1_857 & out_wimask_1003; // @[RegisterRouter.scala:87:24] wire out_f_woready_1003 = out_woready_1_857 & out_womask_1003; // @[RegisterRouter.scala:87:24] wire _out_T_9754 = ~out_rimask_1003; // @[RegisterRouter.scala:87:24] wire _out_T_9755 = ~out_wimask_1003; // @[RegisterRouter.scala:87:24] wire _out_T_9756 = ~out_romask_1003; // @[RegisterRouter.scala:87:24] wire _out_T_9757 = ~out_womask_1003; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_858 = {hi_183, flags_0_go, _out_prepend_T_858}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9758 = out_prepend_858; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9759 = _out_T_9758; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_859 = _out_T_9759; // @[RegisterRouter.scala:87:24] wire out_rimask_1004 = |_out_rimask_T_1004; // @[RegisterRouter.scala:87:24] wire out_wimask_1004 = &_out_wimask_T_1004; // @[RegisterRouter.scala:87:24] wire out_romask_1004 = |_out_romask_T_1004; // @[RegisterRouter.scala:87:24] wire out_womask_1004 = &_out_womask_T_1004; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1004 = out_rivalid_1_858 & out_rimask_1004; // @[RegisterRouter.scala:87:24] wire _out_T_9761 = out_f_rivalid_1004; // @[RegisterRouter.scala:87:24] wire out_f_roready_1004 = out_roready_1_858 & out_romask_1004; // @[RegisterRouter.scala:87:24] wire _out_T_9762 = out_f_roready_1004; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1004 = out_wivalid_1_858 & out_wimask_1004; // @[RegisterRouter.scala:87:24] wire out_f_woready_1004 = out_woready_1_858 & out_womask_1004; // @[RegisterRouter.scala:87:24] wire _out_T_9763 = ~out_rimask_1004; // @[RegisterRouter.scala:87:24] wire _out_T_9764 = ~out_wimask_1004; // @[RegisterRouter.scala:87:24] wire _out_T_9765 = ~out_romask_1004; // @[RegisterRouter.scala:87:24] wire _out_T_9766 = ~out_womask_1004; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_859 = {hi_184, flags_0_go, _out_prepend_T_859}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9767 = out_prepend_859; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9768 = _out_T_9767; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_150 = _out_T_9768; // @[MuxLiteral.scala:49:48] wire out_rimask_1005 = |_out_rimask_T_1005; // @[RegisterRouter.scala:87:24] wire out_wimask_1005 = &_out_wimask_T_1005; // @[RegisterRouter.scala:87:24] wire out_romask_1005 = |_out_romask_T_1005; // @[RegisterRouter.scala:87:24] wire out_womask_1005 = &_out_womask_T_1005; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1005 = out_rivalid_1_859 & out_rimask_1005; // @[RegisterRouter.scala:87:24] wire _out_T_9770 = out_f_rivalid_1005; // @[RegisterRouter.scala:87:24] wire out_f_roready_1005 = out_roready_1_859 & out_romask_1005; // @[RegisterRouter.scala:87:24] wire _out_T_9771 = out_f_roready_1005; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1005 = out_wivalid_1_859 & out_wimask_1005; // @[RegisterRouter.scala:87:24] wire out_f_woready_1005 = out_woready_1_859 & out_womask_1005; // @[RegisterRouter.scala:87:24] wire _out_T_9772 = ~out_rimask_1005; // @[RegisterRouter.scala:87:24] wire _out_T_9773 = ~out_wimask_1005; // @[RegisterRouter.scala:87:24] wire _out_T_9774 = ~out_romask_1005; // @[RegisterRouter.scala:87:24] wire _out_T_9775 = ~out_womask_1005; // @[RegisterRouter.scala:87:24] wire out_rimask_1006 = |_out_rimask_T_1006; // @[RegisterRouter.scala:87:24] wire out_wimask_1006 = &_out_wimask_T_1006; // @[RegisterRouter.scala:87:24] wire out_romask_1006 = |_out_romask_T_1006; // @[RegisterRouter.scala:87:24] wire out_womask_1006 = &_out_womask_T_1006; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1006 = out_rivalid_1_860 & out_rimask_1006; // @[RegisterRouter.scala:87:24] wire _out_T_9779 = out_f_rivalid_1006; // @[RegisterRouter.scala:87:24] wire out_f_roready_1006 = out_roready_1_860 & out_romask_1006; // @[RegisterRouter.scala:87:24] wire _out_T_9780 = out_f_roready_1006; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1006 = out_wivalid_1_860 & out_wimask_1006; // @[RegisterRouter.scala:87:24] wire out_f_woready_1006 = out_woready_1_860 & out_womask_1006; // @[RegisterRouter.scala:87:24] wire _out_T_9781 = ~out_rimask_1006; // @[RegisterRouter.scala:87:24] wire _out_T_9782 = ~out_wimask_1006; // @[RegisterRouter.scala:87:24] wire _out_T_9783 = ~out_romask_1006; // @[RegisterRouter.scala:87:24] wire _out_T_9784 = ~out_womask_1006; // @[RegisterRouter.scala:87:24] wire out_rimask_1007 = |_out_rimask_T_1007; // @[RegisterRouter.scala:87:24] wire out_wimask_1007 = &_out_wimask_T_1007; // @[RegisterRouter.scala:87:24] wire out_romask_1007 = |_out_romask_T_1007; // @[RegisterRouter.scala:87:24] wire out_womask_1007 = &_out_womask_T_1007; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1007 = out_rivalid_1_861 & out_rimask_1007; // @[RegisterRouter.scala:87:24] wire _out_T_9788 = out_f_rivalid_1007; // @[RegisterRouter.scala:87:24] wire out_f_roready_1007 = out_roready_1_861 & out_romask_1007; // @[RegisterRouter.scala:87:24] wire _out_T_9789 = out_f_roready_1007; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1007 = out_wivalid_1_861 & out_wimask_1007; // @[RegisterRouter.scala:87:24] wire out_f_woready_1007 = out_woready_1_861 & out_womask_1007; // @[RegisterRouter.scala:87:24] wire _out_T_9790 = ~out_rimask_1007; // @[RegisterRouter.scala:87:24] wire _out_T_9791 = ~out_wimask_1007; // @[RegisterRouter.scala:87:24] wire _out_T_9792 = ~out_romask_1007; // @[RegisterRouter.scala:87:24] wire _out_T_9793 = ~out_womask_1007; // @[RegisterRouter.scala:87:24] wire out_rimask_1008 = |_out_rimask_T_1008; // @[RegisterRouter.scala:87:24] wire out_wimask_1008 = &_out_wimask_T_1008; // @[RegisterRouter.scala:87:24] wire out_romask_1008 = |_out_romask_T_1008; // @[RegisterRouter.scala:87:24] wire out_womask_1008 = &_out_womask_T_1008; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1008 = out_rivalid_1_862 & out_rimask_1008; // @[RegisterRouter.scala:87:24] wire _out_T_9797 = out_f_rivalid_1008; // @[RegisterRouter.scala:87:24] wire out_f_roready_1008 = out_roready_1_862 & out_romask_1008; // @[RegisterRouter.scala:87:24] wire _out_T_9798 = out_f_roready_1008; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1008 = out_wivalid_1_862 & out_wimask_1008; // @[RegisterRouter.scala:87:24] wire out_f_woready_1008 = out_woready_1_862 & out_womask_1008; // @[RegisterRouter.scala:87:24] wire _out_T_9799 = ~out_rimask_1008; // @[RegisterRouter.scala:87:24] wire _out_T_9800 = ~out_wimask_1008; // @[RegisterRouter.scala:87:24] wire _out_T_9801 = ~out_romask_1008; // @[RegisterRouter.scala:87:24] wire _out_T_9802 = ~out_womask_1008; // @[RegisterRouter.scala:87:24] wire out_rimask_1009 = |_out_rimask_T_1009; // @[RegisterRouter.scala:87:24] wire out_wimask_1009 = &_out_wimask_T_1009; // @[RegisterRouter.scala:87:24] wire out_romask_1009 = |_out_romask_T_1009; // @[RegisterRouter.scala:87:24] wire out_womask_1009 = &_out_womask_T_1009; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1009 = out_rivalid_1_863 & out_rimask_1009; // @[RegisterRouter.scala:87:24] wire _out_T_9806 = out_f_rivalid_1009; // @[RegisterRouter.scala:87:24] wire out_f_roready_1009 = out_roready_1_863 & out_romask_1009; // @[RegisterRouter.scala:87:24] wire _out_T_9807 = out_f_roready_1009; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1009 = out_wivalid_1_863 & out_wimask_1009; // @[RegisterRouter.scala:87:24] wire out_f_woready_1009 = out_woready_1_863 & out_womask_1009; // @[RegisterRouter.scala:87:24] wire _out_T_9808 = ~out_rimask_1009; // @[RegisterRouter.scala:87:24] wire _out_T_9809 = ~out_wimask_1009; // @[RegisterRouter.scala:87:24] wire _out_T_9810 = ~out_romask_1009; // @[RegisterRouter.scala:87:24] wire _out_T_9811 = ~out_womask_1009; // @[RegisterRouter.scala:87:24] wire out_rimask_1010 = |_out_rimask_T_1010; // @[RegisterRouter.scala:87:24] wire out_wimask_1010 = &_out_wimask_T_1010; // @[RegisterRouter.scala:87:24] wire out_romask_1010 = |_out_romask_T_1010; // @[RegisterRouter.scala:87:24] wire out_womask_1010 = &_out_womask_T_1010; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1010 = out_rivalid_1_864 & out_rimask_1010; // @[RegisterRouter.scala:87:24] wire _out_T_9815 = out_f_rivalid_1010; // @[RegisterRouter.scala:87:24] wire out_f_roready_1010 = out_roready_1_864 & out_romask_1010; // @[RegisterRouter.scala:87:24] wire _out_T_9816 = out_f_roready_1010; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1010 = out_wivalid_1_864 & out_wimask_1010; // @[RegisterRouter.scala:87:24] wire out_f_woready_1010 = out_woready_1_864 & out_womask_1010; // @[RegisterRouter.scala:87:24] wire _out_T_9817 = ~out_rimask_1010; // @[RegisterRouter.scala:87:24] wire _out_T_9818 = ~out_wimask_1010; // @[RegisterRouter.scala:87:24] wire _out_T_9819 = ~out_romask_1010; // @[RegisterRouter.scala:87:24] wire _out_T_9820 = ~out_womask_1010; // @[RegisterRouter.scala:87:24] wire out_rimask_1011 = |_out_rimask_T_1011; // @[RegisterRouter.scala:87:24] wire out_wimask_1011 = &_out_wimask_T_1011; // @[RegisterRouter.scala:87:24] wire out_romask_1011 = |_out_romask_T_1011; // @[RegisterRouter.scala:87:24] wire out_womask_1011 = &_out_womask_T_1011; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1011 = out_rivalid_1_865 & out_rimask_1011; // @[RegisterRouter.scala:87:24] wire _out_T_9824 = out_f_rivalid_1011; // @[RegisterRouter.scala:87:24] wire out_f_roready_1011 = out_roready_1_865 & out_romask_1011; // @[RegisterRouter.scala:87:24] wire _out_T_9825 = out_f_roready_1011; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1011 = out_wivalid_1_865 & out_wimask_1011; // @[RegisterRouter.scala:87:24] wire out_f_woready_1011 = out_woready_1_865 & out_womask_1011; // @[RegisterRouter.scala:87:24] wire _out_T_9826 = ~out_rimask_1011; // @[RegisterRouter.scala:87:24] wire _out_T_9827 = ~out_wimask_1011; // @[RegisterRouter.scala:87:24] wire _out_T_9828 = ~out_romask_1011; // @[RegisterRouter.scala:87:24] wire _out_T_9829 = ~out_womask_1011; // @[RegisterRouter.scala:87:24] wire out_rimask_1012 = |_out_rimask_T_1012; // @[RegisterRouter.scala:87:24] wire out_wimask_1012 = &_out_wimask_T_1012; // @[RegisterRouter.scala:87:24] wire out_romask_1012 = |_out_romask_T_1012; // @[RegisterRouter.scala:87:24] wire out_womask_1012 = &_out_womask_T_1012; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1012 = out_rivalid_1_866 & out_rimask_1012; // @[RegisterRouter.scala:87:24] wire _out_T_9833 = out_f_rivalid_1012; // @[RegisterRouter.scala:87:24] wire out_f_roready_1012 = out_roready_1_866 & out_romask_1012; // @[RegisterRouter.scala:87:24] wire _out_T_9834 = out_f_roready_1012; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1012 = out_wivalid_1_866 & out_wimask_1012; // @[RegisterRouter.scala:87:24] wire out_f_woready_1012 = out_woready_1_866 & out_womask_1012; // @[RegisterRouter.scala:87:24] wire _out_T_9835 = ~out_rimask_1012; // @[RegisterRouter.scala:87:24] wire _out_T_9836 = ~out_wimask_1012; // @[RegisterRouter.scala:87:24] wire _out_T_9837 = ~out_romask_1012; // @[RegisterRouter.scala:87:24] wire _out_T_9838 = ~out_womask_1012; // @[RegisterRouter.scala:87:24] wire out_rimask_1013 = |_out_rimask_T_1013; // @[RegisterRouter.scala:87:24] wire out_wimask_1013 = &_out_wimask_T_1013; // @[RegisterRouter.scala:87:24] wire out_romask_1013 = |_out_romask_T_1013; // @[RegisterRouter.scala:87:24] wire out_womask_1013 = &_out_womask_T_1013; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1013 = out_rivalid_1_867 & out_rimask_1013; // @[RegisterRouter.scala:87:24] wire _out_T_9842 = out_f_rivalid_1013; // @[RegisterRouter.scala:87:24] wire out_f_roready_1013 = out_roready_1_867 & out_romask_1013; // @[RegisterRouter.scala:87:24] wire _out_T_9843 = out_f_roready_1013; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1013 = out_wivalid_1_867 & out_wimask_1013; // @[RegisterRouter.scala:87:24] wire out_f_woready_1013 = out_woready_1_867 & out_womask_1013; // @[RegisterRouter.scala:87:24] wire _out_T_9844 = ~out_rimask_1013; // @[RegisterRouter.scala:87:24] wire _out_T_9845 = ~out_wimask_1013; // @[RegisterRouter.scala:87:24] wire _out_T_9846 = ~out_romask_1013; // @[RegisterRouter.scala:87:24] wire _out_T_9847 = ~out_womask_1013; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9849 = _out_T_9848; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_867 = _out_T_9849; // @[RegisterRouter.scala:87:24] wire out_rimask_1014 = |_out_rimask_T_1014; // @[RegisterRouter.scala:87:24] wire out_wimask_1014 = &_out_wimask_T_1014; // @[RegisterRouter.scala:87:24] wire out_romask_1014 = |_out_romask_T_1014; // @[RegisterRouter.scala:87:24] wire out_womask_1014 = &_out_womask_T_1014; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1014 = out_rivalid_1_868 & out_rimask_1014; // @[RegisterRouter.scala:87:24] wire _out_T_9851 = out_f_rivalid_1014; // @[RegisterRouter.scala:87:24] wire out_f_roready_1014 = out_roready_1_868 & out_romask_1014; // @[RegisterRouter.scala:87:24] wire _out_T_9852 = out_f_roready_1014; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1014 = out_wivalid_1_868 & out_wimask_1014; // @[RegisterRouter.scala:87:24] wire out_f_woready_1014 = out_woready_1_868 & out_womask_1014; // @[RegisterRouter.scala:87:24] wire _out_T_9853 = ~out_rimask_1014; // @[RegisterRouter.scala:87:24] wire _out_T_9854 = ~out_wimask_1014; // @[RegisterRouter.scala:87:24] wire _out_T_9855 = ~out_romask_1014; // @[RegisterRouter.scala:87:24] wire _out_T_9856 = ~out_womask_1014; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_867 = {hi_570, flags_0_go, _out_prepend_T_867}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9857 = out_prepend_867; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9858 = _out_T_9857; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_868 = _out_T_9858; // @[RegisterRouter.scala:87:24] wire out_rimask_1015 = |_out_rimask_T_1015; // @[RegisterRouter.scala:87:24] wire out_wimask_1015 = &_out_wimask_T_1015; // @[RegisterRouter.scala:87:24] wire out_romask_1015 = |_out_romask_T_1015; // @[RegisterRouter.scala:87:24] wire out_womask_1015 = &_out_womask_T_1015; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1015 = out_rivalid_1_869 & out_rimask_1015; // @[RegisterRouter.scala:87:24] wire _out_T_9860 = out_f_rivalid_1015; // @[RegisterRouter.scala:87:24] wire out_f_roready_1015 = out_roready_1_869 & out_romask_1015; // @[RegisterRouter.scala:87:24] wire _out_T_9861 = out_f_roready_1015; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1015 = out_wivalid_1_869 & out_wimask_1015; // @[RegisterRouter.scala:87:24] wire out_f_woready_1015 = out_woready_1_869 & out_womask_1015; // @[RegisterRouter.scala:87:24] wire _out_T_9862 = ~out_rimask_1015; // @[RegisterRouter.scala:87:24] wire _out_T_9863 = ~out_wimask_1015; // @[RegisterRouter.scala:87:24] wire _out_T_9864 = ~out_romask_1015; // @[RegisterRouter.scala:87:24] wire _out_T_9865 = ~out_womask_1015; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_868 = {hi_571, flags_0_go, _out_prepend_T_868}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9866 = out_prepend_868; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9867 = _out_T_9866; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_869 = _out_T_9867; // @[RegisterRouter.scala:87:24] wire out_rimask_1016 = |_out_rimask_T_1016; // @[RegisterRouter.scala:87:24] wire out_wimask_1016 = &_out_wimask_T_1016; // @[RegisterRouter.scala:87:24] wire out_romask_1016 = |_out_romask_T_1016; // @[RegisterRouter.scala:87:24] wire out_womask_1016 = &_out_womask_T_1016; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1016 = out_rivalid_1_870 & out_rimask_1016; // @[RegisterRouter.scala:87:24] wire _out_T_9869 = out_f_rivalid_1016; // @[RegisterRouter.scala:87:24] wire out_f_roready_1016 = out_roready_1_870 & out_romask_1016; // @[RegisterRouter.scala:87:24] wire _out_T_9870 = out_f_roready_1016; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1016 = out_wivalid_1_870 & out_wimask_1016; // @[RegisterRouter.scala:87:24] wire out_f_woready_1016 = out_woready_1_870 & out_womask_1016; // @[RegisterRouter.scala:87:24] wire _out_T_9871 = ~out_rimask_1016; // @[RegisterRouter.scala:87:24] wire _out_T_9872 = ~out_wimask_1016; // @[RegisterRouter.scala:87:24] wire _out_T_9873 = ~out_romask_1016; // @[RegisterRouter.scala:87:24] wire _out_T_9874 = ~out_womask_1016; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_869 = {hi_572, flags_0_go, _out_prepend_T_869}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9875 = out_prepend_869; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9876 = _out_T_9875; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_870 = _out_T_9876; // @[RegisterRouter.scala:87:24] wire out_rimask_1017 = |_out_rimask_T_1017; // @[RegisterRouter.scala:87:24] wire out_wimask_1017 = &_out_wimask_T_1017; // @[RegisterRouter.scala:87:24] wire out_romask_1017 = |_out_romask_T_1017; // @[RegisterRouter.scala:87:24] wire out_womask_1017 = &_out_womask_T_1017; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1017 = out_rivalid_1_871 & out_rimask_1017; // @[RegisterRouter.scala:87:24] wire _out_T_9878 = out_f_rivalid_1017; // @[RegisterRouter.scala:87:24] wire out_f_roready_1017 = out_roready_1_871 & out_romask_1017; // @[RegisterRouter.scala:87:24] wire _out_T_9879 = out_f_roready_1017; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1017 = out_wivalid_1_871 & out_wimask_1017; // @[RegisterRouter.scala:87:24] wire out_f_woready_1017 = out_woready_1_871 & out_womask_1017; // @[RegisterRouter.scala:87:24] wire _out_T_9880 = ~out_rimask_1017; // @[RegisterRouter.scala:87:24] wire _out_T_9881 = ~out_wimask_1017; // @[RegisterRouter.scala:87:24] wire _out_T_9882 = ~out_romask_1017; // @[RegisterRouter.scala:87:24] wire _out_T_9883 = ~out_womask_1017; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_870 = {hi_573, flags_0_go, _out_prepend_T_870}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9884 = out_prepend_870; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9885 = _out_T_9884; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_871 = _out_T_9885; // @[RegisterRouter.scala:87:24] wire out_rimask_1018 = |_out_rimask_T_1018; // @[RegisterRouter.scala:87:24] wire out_wimask_1018 = &_out_wimask_T_1018; // @[RegisterRouter.scala:87:24] wire out_romask_1018 = |_out_romask_T_1018; // @[RegisterRouter.scala:87:24] wire out_womask_1018 = &_out_womask_T_1018; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1018 = out_rivalid_1_872 & out_rimask_1018; // @[RegisterRouter.scala:87:24] wire _out_T_9887 = out_f_rivalid_1018; // @[RegisterRouter.scala:87:24] wire out_f_roready_1018 = out_roready_1_872 & out_romask_1018; // @[RegisterRouter.scala:87:24] wire _out_T_9888 = out_f_roready_1018; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1018 = out_wivalid_1_872 & out_wimask_1018; // @[RegisterRouter.scala:87:24] wire out_f_woready_1018 = out_woready_1_872 & out_womask_1018; // @[RegisterRouter.scala:87:24] wire _out_T_9889 = ~out_rimask_1018; // @[RegisterRouter.scala:87:24] wire _out_T_9890 = ~out_wimask_1018; // @[RegisterRouter.scala:87:24] wire _out_T_9891 = ~out_romask_1018; // @[RegisterRouter.scala:87:24] wire _out_T_9892 = ~out_womask_1018; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_871 = {hi_574, flags_0_go, _out_prepend_T_871}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9893 = out_prepend_871; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9894 = _out_T_9893; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_872 = _out_T_9894; // @[RegisterRouter.scala:87:24] wire out_rimask_1019 = |_out_rimask_T_1019; // @[RegisterRouter.scala:87:24] wire out_wimask_1019 = &_out_wimask_T_1019; // @[RegisterRouter.scala:87:24] wire out_romask_1019 = |_out_romask_T_1019; // @[RegisterRouter.scala:87:24] wire out_womask_1019 = &_out_womask_T_1019; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1019 = out_rivalid_1_873 & out_rimask_1019; // @[RegisterRouter.scala:87:24] wire _out_T_9896 = out_f_rivalid_1019; // @[RegisterRouter.scala:87:24] wire out_f_roready_1019 = out_roready_1_873 & out_romask_1019; // @[RegisterRouter.scala:87:24] wire _out_T_9897 = out_f_roready_1019; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1019 = out_wivalid_1_873 & out_wimask_1019; // @[RegisterRouter.scala:87:24] wire out_f_woready_1019 = out_woready_1_873 & out_womask_1019; // @[RegisterRouter.scala:87:24] wire _out_T_9898 = ~out_rimask_1019; // @[RegisterRouter.scala:87:24] wire _out_T_9899 = ~out_wimask_1019; // @[RegisterRouter.scala:87:24] wire _out_T_9900 = ~out_romask_1019; // @[RegisterRouter.scala:87:24] wire _out_T_9901 = ~out_womask_1019; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_872 = {hi_575, flags_0_go, _out_prepend_T_872}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9902 = out_prepend_872; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9903 = _out_T_9902; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_873 = _out_T_9903; // @[RegisterRouter.scala:87:24] wire out_rimask_1020 = |_out_rimask_T_1020; // @[RegisterRouter.scala:87:24] wire out_wimask_1020 = &_out_wimask_T_1020; // @[RegisterRouter.scala:87:24] wire out_romask_1020 = |_out_romask_T_1020; // @[RegisterRouter.scala:87:24] wire out_womask_1020 = &_out_womask_T_1020; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1020 = out_rivalid_1_874 & out_rimask_1020; // @[RegisterRouter.scala:87:24] wire _out_T_9905 = out_f_rivalid_1020; // @[RegisterRouter.scala:87:24] wire out_f_roready_1020 = out_roready_1_874 & out_romask_1020; // @[RegisterRouter.scala:87:24] wire _out_T_9906 = out_f_roready_1020; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1020 = out_wivalid_1_874 & out_wimask_1020; // @[RegisterRouter.scala:87:24] wire out_f_woready_1020 = out_woready_1_874 & out_womask_1020; // @[RegisterRouter.scala:87:24] wire _out_T_9907 = ~out_rimask_1020; // @[RegisterRouter.scala:87:24] wire _out_T_9908 = ~out_wimask_1020; // @[RegisterRouter.scala:87:24] wire _out_T_9909 = ~out_romask_1020; // @[RegisterRouter.scala:87:24] wire _out_T_9910 = ~out_womask_1020; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_873 = {hi_576, flags_0_go, _out_prepend_T_873}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9911 = out_prepend_873; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9912 = _out_T_9911; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_199 = _out_T_9912; // @[MuxLiteral.scala:49:48] wire out_rimask_1021 = |_out_rimask_T_1021; // @[RegisterRouter.scala:87:24] wire out_wimask_1021 = &_out_wimask_T_1021; // @[RegisterRouter.scala:87:24] wire out_romask_1021 = |_out_romask_T_1021; // @[RegisterRouter.scala:87:24] wire out_womask_1021 = &_out_womask_T_1021; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1021 = out_rivalid_1_875 & out_rimask_1021; // @[RegisterRouter.scala:87:24] wire _out_T_9914 = out_f_rivalid_1021; // @[RegisterRouter.scala:87:24] wire out_f_roready_1021 = out_roready_1_875 & out_romask_1021; // @[RegisterRouter.scala:87:24] wire _out_T_9915 = out_f_roready_1021; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1021 = out_wivalid_1_875 & out_wimask_1021; // @[RegisterRouter.scala:87:24] wire out_f_woready_1021 = out_woready_1_875 & out_womask_1021; // @[RegisterRouter.scala:87:24] wire _out_T_9916 = ~out_rimask_1021; // @[RegisterRouter.scala:87:24] wire _out_T_9917 = ~out_wimask_1021; // @[RegisterRouter.scala:87:24] wire _out_T_9918 = ~out_romask_1021; // @[RegisterRouter.scala:87:24] wire _out_T_9919 = ~out_womask_1021; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9921 = _out_T_9920; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_874 = _out_T_9921; // @[RegisterRouter.scala:87:24] wire out_rimask_1022 = |_out_rimask_T_1022; // @[RegisterRouter.scala:87:24] wire out_wimask_1022 = &_out_wimask_T_1022; // @[RegisterRouter.scala:87:24] wire out_romask_1022 = |_out_romask_T_1022; // @[RegisterRouter.scala:87:24] wire out_womask_1022 = &_out_womask_T_1022; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1022 = out_rivalid_1_876 & out_rimask_1022; // @[RegisterRouter.scala:87:24] wire _out_T_9923 = out_f_rivalid_1022; // @[RegisterRouter.scala:87:24] wire out_f_roready_1022 = out_roready_1_876 & out_romask_1022; // @[RegisterRouter.scala:87:24] wire _out_T_9924 = out_f_roready_1022; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1022 = out_wivalid_1_876 & out_wimask_1022; // @[RegisterRouter.scala:87:24] wire out_f_woready_1022 = out_woready_1_876 & out_womask_1022; // @[RegisterRouter.scala:87:24] wire _out_T_9925 = ~out_rimask_1022; // @[RegisterRouter.scala:87:24] wire _out_T_9926 = ~out_wimask_1022; // @[RegisterRouter.scala:87:24] wire _out_T_9927 = ~out_romask_1022; // @[RegisterRouter.scala:87:24] wire _out_T_9928 = ~out_womask_1022; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_874 = {hi_394, flags_0_go, _out_prepend_T_874}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9929 = out_prepend_874; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9930 = _out_T_9929; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_875 = _out_T_9930; // @[RegisterRouter.scala:87:24] wire out_rimask_1023 = |_out_rimask_T_1023; // @[RegisterRouter.scala:87:24] wire out_wimask_1023 = &_out_wimask_T_1023; // @[RegisterRouter.scala:87:24] wire out_romask_1023 = |_out_romask_T_1023; // @[RegisterRouter.scala:87:24] wire out_womask_1023 = &_out_womask_T_1023; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1023 = out_rivalid_1_877 & out_rimask_1023; // @[RegisterRouter.scala:87:24] wire _out_T_9932 = out_f_rivalid_1023; // @[RegisterRouter.scala:87:24] wire out_f_roready_1023 = out_roready_1_877 & out_romask_1023; // @[RegisterRouter.scala:87:24] wire _out_T_9933 = out_f_roready_1023; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1023 = out_wivalid_1_877 & out_wimask_1023; // @[RegisterRouter.scala:87:24] wire out_f_woready_1023 = out_woready_1_877 & out_womask_1023; // @[RegisterRouter.scala:87:24] wire _out_T_9934 = ~out_rimask_1023; // @[RegisterRouter.scala:87:24] wire _out_T_9935 = ~out_wimask_1023; // @[RegisterRouter.scala:87:24] wire _out_T_9936 = ~out_romask_1023; // @[RegisterRouter.scala:87:24] wire _out_T_9937 = ~out_womask_1023; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_875 = {hi_395, flags_0_go, _out_prepend_T_875}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9938 = out_prepend_875; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9939 = _out_T_9938; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_876 = _out_T_9939; // @[RegisterRouter.scala:87:24] wire out_rimask_1024 = |_out_rimask_T_1024; // @[RegisterRouter.scala:87:24] wire out_wimask_1024 = &_out_wimask_T_1024; // @[RegisterRouter.scala:87:24] wire out_romask_1024 = |_out_romask_T_1024; // @[RegisterRouter.scala:87:24] wire out_womask_1024 = &_out_womask_T_1024; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1024 = out_rivalid_1_878 & out_rimask_1024; // @[RegisterRouter.scala:87:24] wire _out_T_9941 = out_f_rivalid_1024; // @[RegisterRouter.scala:87:24] wire out_f_roready_1024 = out_roready_1_878 & out_romask_1024; // @[RegisterRouter.scala:87:24] wire _out_T_9942 = out_f_roready_1024; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1024 = out_wivalid_1_878 & out_wimask_1024; // @[RegisterRouter.scala:87:24] wire out_f_woready_1024 = out_woready_1_878 & out_womask_1024; // @[RegisterRouter.scala:87:24] wire _out_T_9943 = ~out_rimask_1024; // @[RegisterRouter.scala:87:24] wire _out_T_9944 = ~out_wimask_1024; // @[RegisterRouter.scala:87:24] wire _out_T_9945 = ~out_romask_1024; // @[RegisterRouter.scala:87:24] wire _out_T_9946 = ~out_womask_1024; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_876 = {hi_396, flags_0_go, _out_prepend_T_876}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9947 = out_prepend_876; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9948 = _out_T_9947; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_877 = _out_T_9948; // @[RegisterRouter.scala:87:24] wire out_rimask_1025 = |_out_rimask_T_1025; // @[RegisterRouter.scala:87:24] wire out_wimask_1025 = &_out_wimask_T_1025; // @[RegisterRouter.scala:87:24] wire out_romask_1025 = |_out_romask_T_1025; // @[RegisterRouter.scala:87:24] wire out_womask_1025 = &_out_womask_T_1025; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1025 = out_rivalid_1_879 & out_rimask_1025; // @[RegisterRouter.scala:87:24] wire _out_T_9950 = out_f_rivalid_1025; // @[RegisterRouter.scala:87:24] wire out_f_roready_1025 = out_roready_1_879 & out_romask_1025; // @[RegisterRouter.scala:87:24] wire _out_T_9951 = out_f_roready_1025; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1025 = out_wivalid_1_879 & out_wimask_1025; // @[RegisterRouter.scala:87:24] wire out_f_woready_1025 = out_woready_1_879 & out_womask_1025; // @[RegisterRouter.scala:87:24] wire _out_T_9952 = ~out_rimask_1025; // @[RegisterRouter.scala:87:24] wire _out_T_9953 = ~out_wimask_1025; // @[RegisterRouter.scala:87:24] wire _out_T_9954 = ~out_romask_1025; // @[RegisterRouter.scala:87:24] wire _out_T_9955 = ~out_womask_1025; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_877 = {hi_397, flags_0_go, _out_prepend_T_877}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9956 = out_prepend_877; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9957 = _out_T_9956; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_878 = _out_T_9957; // @[RegisterRouter.scala:87:24] wire out_rimask_1026 = |_out_rimask_T_1026; // @[RegisterRouter.scala:87:24] wire out_wimask_1026 = &_out_wimask_T_1026; // @[RegisterRouter.scala:87:24] wire out_romask_1026 = |_out_romask_T_1026; // @[RegisterRouter.scala:87:24] wire out_womask_1026 = &_out_womask_T_1026; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1026 = out_rivalid_1_880 & out_rimask_1026; // @[RegisterRouter.scala:87:24] wire _out_T_9959 = out_f_rivalid_1026; // @[RegisterRouter.scala:87:24] wire out_f_roready_1026 = out_roready_1_880 & out_romask_1026; // @[RegisterRouter.scala:87:24] wire _out_T_9960 = out_f_roready_1026; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1026 = out_wivalid_1_880 & out_wimask_1026; // @[RegisterRouter.scala:87:24] wire out_f_woready_1026 = out_woready_1_880 & out_womask_1026; // @[RegisterRouter.scala:87:24] wire _out_T_9961 = ~out_rimask_1026; // @[RegisterRouter.scala:87:24] wire _out_T_9962 = ~out_wimask_1026; // @[RegisterRouter.scala:87:24] wire _out_T_9963 = ~out_romask_1026; // @[RegisterRouter.scala:87:24] wire _out_T_9964 = ~out_womask_1026; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_878 = {hi_398, flags_0_go, _out_prepend_T_878}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9965 = out_prepend_878; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9966 = _out_T_9965; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_879 = _out_T_9966; // @[RegisterRouter.scala:87:24] wire out_rimask_1027 = |_out_rimask_T_1027; // @[RegisterRouter.scala:87:24] wire out_wimask_1027 = &_out_wimask_T_1027; // @[RegisterRouter.scala:87:24] wire out_romask_1027 = |_out_romask_T_1027; // @[RegisterRouter.scala:87:24] wire out_womask_1027 = &_out_womask_T_1027; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1027 = out_rivalid_1_881 & out_rimask_1027; // @[RegisterRouter.scala:87:24] wire _out_T_9968 = out_f_rivalid_1027; // @[RegisterRouter.scala:87:24] wire out_f_roready_1027 = out_roready_1_881 & out_romask_1027; // @[RegisterRouter.scala:87:24] wire _out_T_9969 = out_f_roready_1027; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1027 = out_wivalid_1_881 & out_wimask_1027; // @[RegisterRouter.scala:87:24] wire out_f_woready_1027 = out_woready_1_881 & out_womask_1027; // @[RegisterRouter.scala:87:24] wire _out_T_9970 = ~out_rimask_1027; // @[RegisterRouter.scala:87:24] wire _out_T_9971 = ~out_wimask_1027; // @[RegisterRouter.scala:87:24] wire _out_T_9972 = ~out_romask_1027; // @[RegisterRouter.scala:87:24] wire _out_T_9973 = ~out_womask_1027; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_879 = {hi_399, flags_0_go, _out_prepend_T_879}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9974 = out_prepend_879; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9975 = _out_T_9974; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_880 = _out_T_9975; // @[RegisterRouter.scala:87:24] wire out_rimask_1028 = |_out_rimask_T_1028; // @[RegisterRouter.scala:87:24] wire out_wimask_1028 = &_out_wimask_T_1028; // @[RegisterRouter.scala:87:24] wire out_romask_1028 = |_out_romask_T_1028; // @[RegisterRouter.scala:87:24] wire out_womask_1028 = &_out_womask_T_1028; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1028 = out_rivalid_1_882 & out_rimask_1028; // @[RegisterRouter.scala:87:24] wire _out_T_9977 = out_f_rivalid_1028; // @[RegisterRouter.scala:87:24] wire out_f_roready_1028 = out_roready_1_882 & out_romask_1028; // @[RegisterRouter.scala:87:24] wire _out_T_9978 = out_f_roready_1028; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1028 = out_wivalid_1_882 & out_wimask_1028; // @[RegisterRouter.scala:87:24] wire out_f_woready_1028 = out_woready_1_882 & out_womask_1028; // @[RegisterRouter.scala:87:24] wire _out_T_9979 = ~out_rimask_1028; // @[RegisterRouter.scala:87:24] wire _out_T_9980 = ~out_wimask_1028; // @[RegisterRouter.scala:87:24] wire _out_T_9981 = ~out_romask_1028; // @[RegisterRouter.scala:87:24] wire _out_T_9982 = ~out_womask_1028; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_880 = {hi_400, flags_0_go, _out_prepend_T_880}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9983 = out_prepend_880; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9984 = _out_T_9983; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_177 = _out_T_9984; // @[MuxLiteral.scala:49:48] wire out_rimask_1029 = |_out_rimask_T_1029; // @[RegisterRouter.scala:87:24] wire out_wimask_1029 = &_out_wimask_T_1029; // @[RegisterRouter.scala:87:24] wire out_romask_1029 = |_out_romask_T_1029; // @[RegisterRouter.scala:87:24] wire out_womask_1029 = &_out_womask_T_1029; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1029 = out_rivalid_1_883 & out_rimask_1029; // @[RegisterRouter.scala:87:24] wire _out_T_9986 = out_f_rivalid_1029; // @[RegisterRouter.scala:87:24] wire out_f_roready_1029 = out_roready_1_883 & out_romask_1029; // @[RegisterRouter.scala:87:24] wire _out_T_9987 = out_f_roready_1029; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1029 = out_wivalid_1_883 & out_wimask_1029; // @[RegisterRouter.scala:87:24] wire out_f_woready_1029 = out_woready_1_883 & out_womask_1029; // @[RegisterRouter.scala:87:24] wire _out_T_9988 = ~out_rimask_1029; // @[RegisterRouter.scala:87:24] wire _out_T_9989 = ~out_wimask_1029; // @[RegisterRouter.scala:87:24] wire _out_T_9990 = ~out_romask_1029; // @[RegisterRouter.scala:87:24] wire _out_T_9991 = ~out_womask_1029; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9993 = _out_T_9992; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_881 = _out_T_9993; // @[RegisterRouter.scala:87:24] wire out_rimask_1030 = |_out_rimask_T_1030; // @[RegisterRouter.scala:87:24] wire out_wimask_1030 = &_out_wimask_T_1030; // @[RegisterRouter.scala:87:24] wire out_romask_1030 = |_out_romask_T_1030; // @[RegisterRouter.scala:87:24] wire out_womask_1030 = &_out_womask_T_1030; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1030 = out_rivalid_1_884 & out_rimask_1030; // @[RegisterRouter.scala:87:24] wire _out_T_9995 = out_f_rivalid_1030; // @[RegisterRouter.scala:87:24] wire out_f_roready_1030 = out_roready_1_884 & out_romask_1030; // @[RegisterRouter.scala:87:24] wire _out_T_9996 = out_f_roready_1030; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1030 = out_wivalid_1_884 & out_wimask_1030; // @[RegisterRouter.scala:87:24] wire out_f_woready_1030 = out_woready_1_884 & out_womask_1030; // @[RegisterRouter.scala:87:24] wire _out_T_9997 = ~out_rimask_1030; // @[RegisterRouter.scala:87:24] wire _out_T_9998 = ~out_wimask_1030; // @[RegisterRouter.scala:87:24] wire _out_T_9999 = ~out_romask_1030; // @[RegisterRouter.scala:87:24] wire _out_T_10000 = ~out_womask_1030; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_881 = {hi_434, flags_0_go, _out_prepend_T_881}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10001 = out_prepend_881; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10002 = _out_T_10001; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_882 = _out_T_10002; // @[RegisterRouter.scala:87:24] wire out_rimask_1031 = |_out_rimask_T_1031; // @[RegisterRouter.scala:87:24] wire out_wimask_1031 = &_out_wimask_T_1031; // @[RegisterRouter.scala:87:24] wire out_romask_1031 = |_out_romask_T_1031; // @[RegisterRouter.scala:87:24] wire out_womask_1031 = &_out_womask_T_1031; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1031 = out_rivalid_1_885 & out_rimask_1031; // @[RegisterRouter.scala:87:24] wire _out_T_10004 = out_f_rivalid_1031; // @[RegisterRouter.scala:87:24] wire out_f_roready_1031 = out_roready_1_885 & out_romask_1031; // @[RegisterRouter.scala:87:24] wire _out_T_10005 = out_f_roready_1031; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1031 = out_wivalid_1_885 & out_wimask_1031; // @[RegisterRouter.scala:87:24] wire out_f_woready_1031 = out_woready_1_885 & out_womask_1031; // @[RegisterRouter.scala:87:24] wire _out_T_10006 = ~out_rimask_1031; // @[RegisterRouter.scala:87:24] wire _out_T_10007 = ~out_wimask_1031; // @[RegisterRouter.scala:87:24] wire _out_T_10008 = ~out_romask_1031; // @[RegisterRouter.scala:87:24] wire _out_T_10009 = ~out_womask_1031; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_882 = {hi_435, flags_0_go, _out_prepend_T_882}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10010 = out_prepend_882; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10011 = _out_T_10010; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_883 = _out_T_10011; // @[RegisterRouter.scala:87:24] wire out_rimask_1032 = |_out_rimask_T_1032; // @[RegisterRouter.scala:87:24] wire out_wimask_1032 = &_out_wimask_T_1032; // @[RegisterRouter.scala:87:24] wire out_romask_1032 = |_out_romask_T_1032; // @[RegisterRouter.scala:87:24] wire out_womask_1032 = &_out_womask_T_1032; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1032 = out_rivalid_1_886 & out_rimask_1032; // @[RegisterRouter.scala:87:24] wire _out_T_10013 = out_f_rivalid_1032; // @[RegisterRouter.scala:87:24] wire out_f_roready_1032 = out_roready_1_886 & out_romask_1032; // @[RegisterRouter.scala:87:24] wire _out_T_10014 = out_f_roready_1032; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1032 = out_wivalid_1_886 & out_wimask_1032; // @[RegisterRouter.scala:87:24] wire out_f_woready_1032 = out_woready_1_886 & out_womask_1032; // @[RegisterRouter.scala:87:24] wire _out_T_10015 = ~out_rimask_1032; // @[RegisterRouter.scala:87:24] wire _out_T_10016 = ~out_wimask_1032; // @[RegisterRouter.scala:87:24] wire _out_T_10017 = ~out_romask_1032; // @[RegisterRouter.scala:87:24] wire _out_T_10018 = ~out_womask_1032; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_883 = {hi_436, flags_0_go, _out_prepend_T_883}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10019 = out_prepend_883; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10020 = _out_T_10019; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_884 = _out_T_10020; // @[RegisterRouter.scala:87:24] wire out_rimask_1033 = |_out_rimask_T_1033; // @[RegisterRouter.scala:87:24] wire out_wimask_1033 = &_out_wimask_T_1033; // @[RegisterRouter.scala:87:24] wire out_romask_1033 = |_out_romask_T_1033; // @[RegisterRouter.scala:87:24] wire out_womask_1033 = &_out_womask_T_1033; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1033 = out_rivalid_1_887 & out_rimask_1033; // @[RegisterRouter.scala:87:24] wire _out_T_10022 = out_f_rivalid_1033; // @[RegisterRouter.scala:87:24] wire out_f_roready_1033 = out_roready_1_887 & out_romask_1033; // @[RegisterRouter.scala:87:24] wire _out_T_10023 = out_f_roready_1033; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1033 = out_wivalid_1_887 & out_wimask_1033; // @[RegisterRouter.scala:87:24] wire out_f_woready_1033 = out_woready_1_887 & out_womask_1033; // @[RegisterRouter.scala:87:24] wire _out_T_10024 = ~out_rimask_1033; // @[RegisterRouter.scala:87:24] wire _out_T_10025 = ~out_wimask_1033; // @[RegisterRouter.scala:87:24] wire _out_T_10026 = ~out_romask_1033; // @[RegisterRouter.scala:87:24] wire _out_T_10027 = ~out_womask_1033; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_884 = {hi_437, flags_0_go, _out_prepend_T_884}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10028 = out_prepend_884; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10029 = _out_T_10028; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_885 = _out_T_10029; // @[RegisterRouter.scala:87:24] wire out_rimask_1034 = |_out_rimask_T_1034; // @[RegisterRouter.scala:87:24] wire out_wimask_1034 = &_out_wimask_T_1034; // @[RegisterRouter.scala:87:24] wire out_romask_1034 = |_out_romask_T_1034; // @[RegisterRouter.scala:87:24] wire out_womask_1034 = &_out_womask_T_1034; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1034 = out_rivalid_1_888 & out_rimask_1034; // @[RegisterRouter.scala:87:24] wire _out_T_10031 = out_f_rivalid_1034; // @[RegisterRouter.scala:87:24] wire out_f_roready_1034 = out_roready_1_888 & out_romask_1034; // @[RegisterRouter.scala:87:24] wire _out_T_10032 = out_f_roready_1034; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1034 = out_wivalid_1_888 & out_wimask_1034; // @[RegisterRouter.scala:87:24] wire out_f_woready_1034 = out_woready_1_888 & out_womask_1034; // @[RegisterRouter.scala:87:24] wire _out_T_10033 = ~out_rimask_1034; // @[RegisterRouter.scala:87:24] wire _out_T_10034 = ~out_wimask_1034; // @[RegisterRouter.scala:87:24] wire _out_T_10035 = ~out_romask_1034; // @[RegisterRouter.scala:87:24] wire _out_T_10036 = ~out_womask_1034; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_885 = {hi_438, flags_0_go, _out_prepend_T_885}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10037 = out_prepend_885; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10038 = _out_T_10037; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_886 = _out_T_10038; // @[RegisterRouter.scala:87:24] wire out_rimask_1035 = |_out_rimask_T_1035; // @[RegisterRouter.scala:87:24] wire out_wimask_1035 = &_out_wimask_T_1035; // @[RegisterRouter.scala:87:24] wire out_romask_1035 = |_out_romask_T_1035; // @[RegisterRouter.scala:87:24] wire out_womask_1035 = &_out_womask_T_1035; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1035 = out_rivalid_1_889 & out_rimask_1035; // @[RegisterRouter.scala:87:24] wire _out_T_10040 = out_f_rivalid_1035; // @[RegisterRouter.scala:87:24] wire out_f_roready_1035 = out_roready_1_889 & out_romask_1035; // @[RegisterRouter.scala:87:24] wire _out_T_10041 = out_f_roready_1035; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1035 = out_wivalid_1_889 & out_wimask_1035; // @[RegisterRouter.scala:87:24] wire out_f_woready_1035 = out_woready_1_889 & out_womask_1035; // @[RegisterRouter.scala:87:24] wire _out_T_10042 = ~out_rimask_1035; // @[RegisterRouter.scala:87:24] wire _out_T_10043 = ~out_wimask_1035; // @[RegisterRouter.scala:87:24] wire _out_T_10044 = ~out_romask_1035; // @[RegisterRouter.scala:87:24] wire _out_T_10045 = ~out_womask_1035; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_886 = {hi_439, flags_0_go, _out_prepend_T_886}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10046 = out_prepend_886; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10047 = _out_T_10046; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_887 = _out_T_10047; // @[RegisterRouter.scala:87:24] wire out_rimask_1036 = |_out_rimask_T_1036; // @[RegisterRouter.scala:87:24] wire out_wimask_1036 = &_out_wimask_T_1036; // @[RegisterRouter.scala:87:24] wire out_romask_1036 = |_out_romask_T_1036; // @[RegisterRouter.scala:87:24] wire out_womask_1036 = &_out_womask_T_1036; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1036 = out_rivalid_1_890 & out_rimask_1036; // @[RegisterRouter.scala:87:24] wire _out_T_10049 = out_f_rivalid_1036; // @[RegisterRouter.scala:87:24] wire out_f_roready_1036 = out_roready_1_890 & out_romask_1036; // @[RegisterRouter.scala:87:24] wire _out_T_10050 = out_f_roready_1036; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1036 = out_wivalid_1_890 & out_wimask_1036; // @[RegisterRouter.scala:87:24] wire out_f_woready_1036 = out_woready_1_890 & out_womask_1036; // @[RegisterRouter.scala:87:24] wire _out_T_10051 = ~out_rimask_1036; // @[RegisterRouter.scala:87:24] wire _out_T_10052 = ~out_wimask_1036; // @[RegisterRouter.scala:87:24] wire _out_T_10053 = ~out_romask_1036; // @[RegisterRouter.scala:87:24] wire _out_T_10054 = ~out_womask_1036; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_887 = {hi_440, flags_0_go, _out_prepend_T_887}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10055 = out_prepend_887; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10056 = _out_T_10055; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_182 = _out_T_10056; // @[MuxLiteral.scala:49:48] wire out_rimask_1037 = |_out_rimask_T_1037; // @[RegisterRouter.scala:87:24] wire out_wimask_1037 = &_out_wimask_T_1037; // @[RegisterRouter.scala:87:24] wire out_romask_1037 = |_out_romask_T_1037; // @[RegisterRouter.scala:87:24] wire out_womask_1037 = &_out_womask_T_1037; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1037 = out_rivalid_1_891 & out_rimask_1037; // @[RegisterRouter.scala:87:24] wire _out_T_10058 = out_f_rivalid_1037; // @[RegisterRouter.scala:87:24] wire out_f_roready_1037 = out_roready_1_891 & out_romask_1037; // @[RegisterRouter.scala:87:24] wire _out_T_10059 = out_f_roready_1037; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1037 = out_wivalid_1_891 & out_wimask_1037; // @[RegisterRouter.scala:87:24] wire out_f_woready_1037 = out_woready_1_891 & out_womask_1037; // @[RegisterRouter.scala:87:24] wire _out_T_10060 = ~out_rimask_1037; // @[RegisterRouter.scala:87:24] wire _out_T_10061 = ~out_wimask_1037; // @[RegisterRouter.scala:87:24] wire _out_T_10062 = ~out_romask_1037; // @[RegisterRouter.scala:87:24] wire _out_T_10063 = ~out_womask_1037; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10065 = _out_T_10064; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_888 = _out_T_10065; // @[RegisterRouter.scala:87:24] wire out_rimask_1038 = |_out_rimask_T_1038; // @[RegisterRouter.scala:87:24] wire out_wimask_1038 = &_out_wimask_T_1038; // @[RegisterRouter.scala:87:24] wire out_romask_1038 = |_out_romask_T_1038; // @[RegisterRouter.scala:87:24] wire out_womask_1038 = &_out_womask_T_1038; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1038 = out_rivalid_1_892 & out_rimask_1038; // @[RegisterRouter.scala:87:24] wire _out_T_10067 = out_f_rivalid_1038; // @[RegisterRouter.scala:87:24] wire out_f_roready_1038 = out_roready_1_892 & out_romask_1038; // @[RegisterRouter.scala:87:24] wire _out_T_10068 = out_f_roready_1038; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1038 = out_wivalid_1_892 & out_wimask_1038; // @[RegisterRouter.scala:87:24] wire out_f_woready_1038 = out_woready_1_892 & out_womask_1038; // @[RegisterRouter.scala:87:24] wire _out_T_10069 = ~out_rimask_1038; // @[RegisterRouter.scala:87:24] wire _out_T_10070 = ~out_wimask_1038; // @[RegisterRouter.scala:87:24] wire _out_T_10071 = ~out_romask_1038; // @[RegisterRouter.scala:87:24] wire _out_T_10072 = ~out_womask_1038; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_888 = {hi_210, flags_0_go, _out_prepend_T_888}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10073 = out_prepend_888; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10074 = _out_T_10073; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_889 = _out_T_10074; // @[RegisterRouter.scala:87:24] wire out_rimask_1039 = |_out_rimask_T_1039; // @[RegisterRouter.scala:87:24] wire out_wimask_1039 = &_out_wimask_T_1039; // @[RegisterRouter.scala:87:24] wire out_romask_1039 = |_out_romask_T_1039; // @[RegisterRouter.scala:87:24] wire out_womask_1039 = &_out_womask_T_1039; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1039 = out_rivalid_1_893 & out_rimask_1039; // @[RegisterRouter.scala:87:24] wire _out_T_10076 = out_f_rivalid_1039; // @[RegisterRouter.scala:87:24] wire out_f_roready_1039 = out_roready_1_893 & out_romask_1039; // @[RegisterRouter.scala:87:24] wire _out_T_10077 = out_f_roready_1039; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1039 = out_wivalid_1_893 & out_wimask_1039; // @[RegisterRouter.scala:87:24] wire out_f_woready_1039 = out_woready_1_893 & out_womask_1039; // @[RegisterRouter.scala:87:24] wire _out_T_10078 = ~out_rimask_1039; // @[RegisterRouter.scala:87:24] wire _out_T_10079 = ~out_wimask_1039; // @[RegisterRouter.scala:87:24] wire _out_T_10080 = ~out_romask_1039; // @[RegisterRouter.scala:87:24] wire _out_T_10081 = ~out_womask_1039; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_889 = {hi_211, flags_0_go, _out_prepend_T_889}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10082 = out_prepend_889; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10083 = _out_T_10082; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_890 = _out_T_10083; // @[RegisterRouter.scala:87:24] wire out_rimask_1040 = |_out_rimask_T_1040; // @[RegisterRouter.scala:87:24] wire out_wimask_1040 = &_out_wimask_T_1040; // @[RegisterRouter.scala:87:24] wire out_romask_1040 = |_out_romask_T_1040; // @[RegisterRouter.scala:87:24] wire out_womask_1040 = &_out_womask_T_1040; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1040 = out_rivalid_1_894 & out_rimask_1040; // @[RegisterRouter.scala:87:24] wire _out_T_10085 = out_f_rivalid_1040; // @[RegisterRouter.scala:87:24] wire out_f_roready_1040 = out_roready_1_894 & out_romask_1040; // @[RegisterRouter.scala:87:24] wire _out_T_10086 = out_f_roready_1040; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1040 = out_wivalid_1_894 & out_wimask_1040; // @[RegisterRouter.scala:87:24] wire out_f_woready_1040 = out_woready_1_894 & out_womask_1040; // @[RegisterRouter.scala:87:24] wire _out_T_10087 = ~out_rimask_1040; // @[RegisterRouter.scala:87:24] wire _out_T_10088 = ~out_wimask_1040; // @[RegisterRouter.scala:87:24] wire _out_T_10089 = ~out_romask_1040; // @[RegisterRouter.scala:87:24] wire _out_T_10090 = ~out_womask_1040; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_890 = {hi_212, flags_0_go, _out_prepend_T_890}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10091 = out_prepend_890; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10092 = _out_T_10091; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_891 = _out_T_10092; // @[RegisterRouter.scala:87:24] wire out_rimask_1041 = |_out_rimask_T_1041; // @[RegisterRouter.scala:87:24] wire out_wimask_1041 = &_out_wimask_T_1041; // @[RegisterRouter.scala:87:24] wire out_romask_1041 = |_out_romask_T_1041; // @[RegisterRouter.scala:87:24] wire out_womask_1041 = &_out_womask_T_1041; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1041 = out_rivalid_1_895 & out_rimask_1041; // @[RegisterRouter.scala:87:24] wire _out_T_10094 = out_f_rivalid_1041; // @[RegisterRouter.scala:87:24] wire out_f_roready_1041 = out_roready_1_895 & out_romask_1041; // @[RegisterRouter.scala:87:24] wire _out_T_10095 = out_f_roready_1041; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1041 = out_wivalid_1_895 & out_wimask_1041; // @[RegisterRouter.scala:87:24] wire out_f_woready_1041 = out_woready_1_895 & out_womask_1041; // @[RegisterRouter.scala:87:24] wire _out_T_10096 = ~out_rimask_1041; // @[RegisterRouter.scala:87:24] wire _out_T_10097 = ~out_wimask_1041; // @[RegisterRouter.scala:87:24] wire _out_T_10098 = ~out_romask_1041; // @[RegisterRouter.scala:87:24] wire _out_T_10099 = ~out_womask_1041; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_891 = {hi_213, flags_0_go, _out_prepend_T_891}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10100 = out_prepend_891; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10101 = _out_T_10100; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_892 = _out_T_10101; // @[RegisterRouter.scala:87:24] wire out_rimask_1042 = |_out_rimask_T_1042; // @[RegisterRouter.scala:87:24] wire out_wimask_1042 = &_out_wimask_T_1042; // @[RegisterRouter.scala:87:24] wire out_romask_1042 = |_out_romask_T_1042; // @[RegisterRouter.scala:87:24] wire out_womask_1042 = &_out_womask_T_1042; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1042 = out_rivalid_1_896 & out_rimask_1042; // @[RegisterRouter.scala:87:24] wire _out_T_10103 = out_f_rivalid_1042; // @[RegisterRouter.scala:87:24] wire out_f_roready_1042 = out_roready_1_896 & out_romask_1042; // @[RegisterRouter.scala:87:24] wire _out_T_10104 = out_f_roready_1042; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1042 = out_wivalid_1_896 & out_wimask_1042; // @[RegisterRouter.scala:87:24] wire out_f_woready_1042 = out_woready_1_896 & out_womask_1042; // @[RegisterRouter.scala:87:24] wire _out_T_10105 = ~out_rimask_1042; // @[RegisterRouter.scala:87:24] wire _out_T_10106 = ~out_wimask_1042; // @[RegisterRouter.scala:87:24] wire _out_T_10107 = ~out_romask_1042; // @[RegisterRouter.scala:87:24] wire _out_T_10108 = ~out_womask_1042; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_892 = {hi_214, flags_0_go, _out_prepend_T_892}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10109 = out_prepend_892; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10110 = _out_T_10109; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_893 = _out_T_10110; // @[RegisterRouter.scala:87:24] wire out_rimask_1043 = |_out_rimask_T_1043; // @[RegisterRouter.scala:87:24] wire out_wimask_1043 = &_out_wimask_T_1043; // @[RegisterRouter.scala:87:24] wire out_romask_1043 = |_out_romask_T_1043; // @[RegisterRouter.scala:87:24] wire out_womask_1043 = &_out_womask_T_1043; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1043 = out_rivalid_1_897 & out_rimask_1043; // @[RegisterRouter.scala:87:24] wire _out_T_10112 = out_f_rivalid_1043; // @[RegisterRouter.scala:87:24] wire out_f_roready_1043 = out_roready_1_897 & out_romask_1043; // @[RegisterRouter.scala:87:24] wire _out_T_10113 = out_f_roready_1043; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1043 = out_wivalid_1_897 & out_wimask_1043; // @[RegisterRouter.scala:87:24] wire out_f_woready_1043 = out_woready_1_897 & out_womask_1043; // @[RegisterRouter.scala:87:24] wire _out_T_10114 = ~out_rimask_1043; // @[RegisterRouter.scala:87:24] wire _out_T_10115 = ~out_wimask_1043; // @[RegisterRouter.scala:87:24] wire _out_T_10116 = ~out_romask_1043; // @[RegisterRouter.scala:87:24] wire _out_T_10117 = ~out_womask_1043; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_893 = {hi_215, flags_0_go, _out_prepend_T_893}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10118 = out_prepend_893; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10119 = _out_T_10118; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_894 = _out_T_10119; // @[RegisterRouter.scala:87:24] wire out_rimask_1044 = |_out_rimask_T_1044; // @[RegisterRouter.scala:87:24] wire out_wimask_1044 = &_out_wimask_T_1044; // @[RegisterRouter.scala:87:24] wire out_romask_1044 = |_out_romask_T_1044; // @[RegisterRouter.scala:87:24] wire out_womask_1044 = &_out_womask_T_1044; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1044 = out_rivalid_1_898 & out_rimask_1044; // @[RegisterRouter.scala:87:24] wire _out_T_10121 = out_f_rivalid_1044; // @[RegisterRouter.scala:87:24] wire out_f_roready_1044 = out_roready_1_898 & out_romask_1044; // @[RegisterRouter.scala:87:24] wire _out_T_10122 = out_f_roready_1044; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1044 = out_wivalid_1_898 & out_wimask_1044; // @[RegisterRouter.scala:87:24] wire out_f_woready_1044 = out_woready_1_898 & out_womask_1044; // @[RegisterRouter.scala:87:24] wire _out_T_10123 = ~out_rimask_1044; // @[RegisterRouter.scala:87:24] wire _out_T_10124 = ~out_wimask_1044; // @[RegisterRouter.scala:87:24] wire _out_T_10125 = ~out_romask_1044; // @[RegisterRouter.scala:87:24] wire _out_T_10126 = ~out_womask_1044; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_894 = {hi_216, flags_0_go, _out_prepend_T_894}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10127 = out_prepend_894; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10128 = _out_T_10127; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_154 = _out_T_10128; // @[MuxLiteral.scala:49:48] wire out_rimask_1045 = |_out_rimask_T_1045; // @[RegisterRouter.scala:87:24] wire out_wimask_1045 = &_out_wimask_T_1045; // @[RegisterRouter.scala:87:24] wire out_romask_1045 = |_out_romask_T_1045; // @[RegisterRouter.scala:87:24] wire out_womask_1045 = &_out_womask_T_1045; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1045 = out_rivalid_1_899 & out_rimask_1045; // @[RegisterRouter.scala:87:24] wire _out_T_10130 = out_f_rivalid_1045; // @[RegisterRouter.scala:87:24] wire out_f_roready_1045 = out_roready_1_899 & out_romask_1045; // @[RegisterRouter.scala:87:24] wire _out_T_10131 = out_f_roready_1045; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1045 = out_wivalid_1_899 & out_wimask_1045; // @[RegisterRouter.scala:87:24] wire out_f_woready_1045 = out_woready_1_899 & out_womask_1045; // @[RegisterRouter.scala:87:24] wire _out_T_10132 = ~out_rimask_1045; // @[RegisterRouter.scala:87:24] wire _out_T_10133 = ~out_wimask_1045; // @[RegisterRouter.scala:87:24] wire _out_T_10134 = ~out_romask_1045; // @[RegisterRouter.scala:87:24] wire _out_T_10135 = ~out_womask_1045; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10137 = _out_T_10136; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_895 = _out_T_10137; // @[RegisterRouter.scala:87:24] wire out_rimask_1046 = |_out_rimask_T_1046; // @[RegisterRouter.scala:87:24] wire out_wimask_1046 = &_out_wimask_T_1046; // @[RegisterRouter.scala:87:24] wire out_romask_1046 = |_out_romask_T_1046; // @[RegisterRouter.scala:87:24] wire out_womask_1046 = &_out_womask_T_1046; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1046 = out_rivalid_1_900 & out_rimask_1046; // @[RegisterRouter.scala:87:24] wire _out_T_10139 = out_f_rivalid_1046; // @[RegisterRouter.scala:87:24] wire out_f_roready_1046 = out_roready_1_900 & out_romask_1046; // @[RegisterRouter.scala:87:24] wire _out_T_10140 = out_f_roready_1046; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1046 = out_wivalid_1_900 & out_wimask_1046; // @[RegisterRouter.scala:87:24] wire out_f_woready_1046 = out_woready_1_900 & out_womask_1046; // @[RegisterRouter.scala:87:24] wire _out_T_10141 = ~out_rimask_1046; // @[RegisterRouter.scala:87:24] wire _out_T_10142 = ~out_wimask_1046; // @[RegisterRouter.scala:87:24] wire _out_T_10143 = ~out_romask_1046; // @[RegisterRouter.scala:87:24] wire _out_T_10144 = ~out_womask_1046; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_895 = {hi_378, flags_0_go, _out_prepend_T_895}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10145 = out_prepend_895; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10146 = _out_T_10145; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_896 = _out_T_10146; // @[RegisterRouter.scala:87:24] wire out_rimask_1047 = |_out_rimask_T_1047; // @[RegisterRouter.scala:87:24] wire out_wimask_1047 = &_out_wimask_T_1047; // @[RegisterRouter.scala:87:24] wire out_romask_1047 = |_out_romask_T_1047; // @[RegisterRouter.scala:87:24] wire out_womask_1047 = &_out_womask_T_1047; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1047 = out_rivalid_1_901 & out_rimask_1047; // @[RegisterRouter.scala:87:24] wire _out_T_10148 = out_f_rivalid_1047; // @[RegisterRouter.scala:87:24] wire out_f_roready_1047 = out_roready_1_901 & out_romask_1047; // @[RegisterRouter.scala:87:24] wire _out_T_10149 = out_f_roready_1047; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1047 = out_wivalid_1_901 & out_wimask_1047; // @[RegisterRouter.scala:87:24] wire out_f_woready_1047 = out_woready_1_901 & out_womask_1047; // @[RegisterRouter.scala:87:24] wire _out_T_10150 = ~out_rimask_1047; // @[RegisterRouter.scala:87:24] wire _out_T_10151 = ~out_wimask_1047; // @[RegisterRouter.scala:87:24] wire _out_T_10152 = ~out_romask_1047; // @[RegisterRouter.scala:87:24] wire _out_T_10153 = ~out_womask_1047; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_896 = {hi_379, flags_0_go, _out_prepend_T_896}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10154 = out_prepend_896; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10155 = _out_T_10154; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_897 = _out_T_10155; // @[RegisterRouter.scala:87:24] wire out_rimask_1048 = |_out_rimask_T_1048; // @[RegisterRouter.scala:87:24] wire out_wimask_1048 = &_out_wimask_T_1048; // @[RegisterRouter.scala:87:24] wire out_romask_1048 = |_out_romask_T_1048; // @[RegisterRouter.scala:87:24] wire out_womask_1048 = &_out_womask_T_1048; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1048 = out_rivalid_1_902 & out_rimask_1048; // @[RegisterRouter.scala:87:24] wire _out_T_10157 = out_f_rivalid_1048; // @[RegisterRouter.scala:87:24] wire out_f_roready_1048 = out_roready_1_902 & out_romask_1048; // @[RegisterRouter.scala:87:24] wire _out_T_10158 = out_f_roready_1048; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1048 = out_wivalid_1_902 & out_wimask_1048; // @[RegisterRouter.scala:87:24] wire out_f_woready_1048 = out_woready_1_902 & out_womask_1048; // @[RegisterRouter.scala:87:24] wire _out_T_10159 = ~out_rimask_1048; // @[RegisterRouter.scala:87:24] wire _out_T_10160 = ~out_wimask_1048; // @[RegisterRouter.scala:87:24] wire _out_T_10161 = ~out_romask_1048; // @[RegisterRouter.scala:87:24] wire _out_T_10162 = ~out_womask_1048; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_897 = {hi_380, flags_0_go, _out_prepend_T_897}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10163 = out_prepend_897; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10164 = _out_T_10163; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_898 = _out_T_10164; // @[RegisterRouter.scala:87:24] wire out_rimask_1049 = |_out_rimask_T_1049; // @[RegisterRouter.scala:87:24] wire out_wimask_1049 = &_out_wimask_T_1049; // @[RegisterRouter.scala:87:24] wire out_romask_1049 = |_out_romask_T_1049; // @[RegisterRouter.scala:87:24] wire out_womask_1049 = &_out_womask_T_1049; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1049 = out_rivalid_1_903 & out_rimask_1049; // @[RegisterRouter.scala:87:24] wire _out_T_10166 = out_f_rivalid_1049; // @[RegisterRouter.scala:87:24] wire out_f_roready_1049 = out_roready_1_903 & out_romask_1049; // @[RegisterRouter.scala:87:24] wire _out_T_10167 = out_f_roready_1049; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1049 = out_wivalid_1_903 & out_wimask_1049; // @[RegisterRouter.scala:87:24] wire out_f_woready_1049 = out_woready_1_903 & out_womask_1049; // @[RegisterRouter.scala:87:24] wire _out_T_10168 = ~out_rimask_1049; // @[RegisterRouter.scala:87:24] wire _out_T_10169 = ~out_wimask_1049; // @[RegisterRouter.scala:87:24] wire _out_T_10170 = ~out_romask_1049; // @[RegisterRouter.scala:87:24] wire _out_T_10171 = ~out_womask_1049; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_898 = {hi_381, flags_0_go, _out_prepend_T_898}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10172 = out_prepend_898; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10173 = _out_T_10172; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_899 = _out_T_10173; // @[RegisterRouter.scala:87:24] wire out_rimask_1050 = |_out_rimask_T_1050; // @[RegisterRouter.scala:87:24] wire out_wimask_1050 = &_out_wimask_T_1050; // @[RegisterRouter.scala:87:24] wire out_romask_1050 = |_out_romask_T_1050; // @[RegisterRouter.scala:87:24] wire out_womask_1050 = &_out_womask_T_1050; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1050 = out_rivalid_1_904 & out_rimask_1050; // @[RegisterRouter.scala:87:24] wire _out_T_10175 = out_f_rivalid_1050; // @[RegisterRouter.scala:87:24] wire out_f_roready_1050 = out_roready_1_904 & out_romask_1050; // @[RegisterRouter.scala:87:24] wire _out_T_10176 = out_f_roready_1050; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1050 = out_wivalid_1_904 & out_wimask_1050; // @[RegisterRouter.scala:87:24] wire out_f_woready_1050 = out_woready_1_904 & out_womask_1050; // @[RegisterRouter.scala:87:24] wire _out_T_10177 = ~out_rimask_1050; // @[RegisterRouter.scala:87:24] wire _out_T_10178 = ~out_wimask_1050; // @[RegisterRouter.scala:87:24] wire _out_T_10179 = ~out_romask_1050; // @[RegisterRouter.scala:87:24] wire _out_T_10180 = ~out_womask_1050; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_899 = {hi_382, flags_0_go, _out_prepend_T_899}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10181 = out_prepend_899; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10182 = _out_T_10181; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_900 = _out_T_10182; // @[RegisterRouter.scala:87:24] wire out_rimask_1051 = |_out_rimask_T_1051; // @[RegisterRouter.scala:87:24] wire out_wimask_1051 = &_out_wimask_T_1051; // @[RegisterRouter.scala:87:24] wire out_romask_1051 = |_out_romask_T_1051; // @[RegisterRouter.scala:87:24] wire out_womask_1051 = &_out_womask_T_1051; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1051 = out_rivalid_1_905 & out_rimask_1051; // @[RegisterRouter.scala:87:24] wire _out_T_10184 = out_f_rivalid_1051; // @[RegisterRouter.scala:87:24] wire out_f_roready_1051 = out_roready_1_905 & out_romask_1051; // @[RegisterRouter.scala:87:24] wire _out_T_10185 = out_f_roready_1051; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1051 = out_wivalid_1_905 & out_wimask_1051; // @[RegisterRouter.scala:87:24] wire out_f_woready_1051 = out_woready_1_905 & out_womask_1051; // @[RegisterRouter.scala:87:24] wire _out_T_10186 = ~out_rimask_1051; // @[RegisterRouter.scala:87:24] wire _out_T_10187 = ~out_wimask_1051; // @[RegisterRouter.scala:87:24] wire _out_T_10188 = ~out_romask_1051; // @[RegisterRouter.scala:87:24] wire _out_T_10189 = ~out_womask_1051; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_900 = {hi_383, flags_0_go, _out_prepend_T_900}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10190 = out_prepend_900; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10191 = _out_T_10190; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_901 = _out_T_10191; // @[RegisterRouter.scala:87:24] wire out_rimask_1052 = |_out_rimask_T_1052; // @[RegisterRouter.scala:87:24] wire out_wimask_1052 = &_out_wimask_T_1052; // @[RegisterRouter.scala:87:24] wire out_romask_1052 = |_out_romask_T_1052; // @[RegisterRouter.scala:87:24] wire out_womask_1052 = &_out_womask_T_1052; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1052 = out_rivalid_1_906 & out_rimask_1052; // @[RegisterRouter.scala:87:24] wire _out_T_10193 = out_f_rivalid_1052; // @[RegisterRouter.scala:87:24] wire out_f_roready_1052 = out_roready_1_906 & out_romask_1052; // @[RegisterRouter.scala:87:24] wire _out_T_10194 = out_f_roready_1052; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1052 = out_wivalid_1_906 & out_wimask_1052; // @[RegisterRouter.scala:87:24] wire out_f_woready_1052 = out_woready_1_906 & out_womask_1052; // @[RegisterRouter.scala:87:24] wire _out_T_10195 = ~out_rimask_1052; // @[RegisterRouter.scala:87:24] wire _out_T_10196 = ~out_wimask_1052; // @[RegisterRouter.scala:87:24] wire _out_T_10197 = ~out_romask_1052; // @[RegisterRouter.scala:87:24] wire _out_T_10198 = ~out_womask_1052; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_901 = {hi_384, flags_0_go, _out_prepend_T_901}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10199 = out_prepend_901; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10200 = _out_T_10199; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_175 = _out_T_10200; // @[MuxLiteral.scala:49:48] wire out_rimask_1053 = |_out_rimask_T_1053; // @[RegisterRouter.scala:87:24] wire out_wimask_1053 = &_out_wimask_T_1053; // @[RegisterRouter.scala:87:24] wire out_romask_1053 = |_out_romask_T_1053; // @[RegisterRouter.scala:87:24] wire out_womask_1053 = &_out_womask_T_1053; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1053 = out_rivalid_1_907 & out_rimask_1053; // @[RegisterRouter.scala:87:24] wire _out_T_10202 = out_f_rivalid_1053; // @[RegisterRouter.scala:87:24] wire out_f_roready_1053 = out_roready_1_907 & out_romask_1053; // @[RegisterRouter.scala:87:24] wire _out_T_10203 = out_f_roready_1053; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1053 = out_wivalid_1_907 & out_wimask_1053; // @[RegisterRouter.scala:87:24] wire out_f_woready_1053 = out_woready_1_907 & out_womask_1053; // @[RegisterRouter.scala:87:24] wire _out_T_10204 = ~out_rimask_1053; // @[RegisterRouter.scala:87:24] wire _out_T_10205 = ~out_wimask_1053; // @[RegisterRouter.scala:87:24] wire _out_T_10206 = ~out_romask_1053; // @[RegisterRouter.scala:87:24] wire _out_T_10207 = ~out_womask_1053; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10209 = _out_T_10208; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_902 = _out_T_10209; // @[RegisterRouter.scala:87:24] wire out_rimask_1054 = |_out_rimask_T_1054; // @[RegisterRouter.scala:87:24] wire out_wimask_1054 = &_out_wimask_T_1054; // @[RegisterRouter.scala:87:24] wire out_romask_1054 = |_out_romask_T_1054; // @[RegisterRouter.scala:87:24] wire out_womask_1054 = &_out_womask_T_1054; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1054 = out_rivalid_1_908 & out_rimask_1054; // @[RegisterRouter.scala:87:24] wire _out_T_10211 = out_f_rivalid_1054; // @[RegisterRouter.scala:87:24] wire out_f_roready_1054 = out_roready_1_908 & out_romask_1054; // @[RegisterRouter.scala:87:24] wire _out_T_10212 = out_f_roready_1054; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1054 = out_wivalid_1_908 & out_wimask_1054; // @[RegisterRouter.scala:87:24] wire out_f_woready_1054 = out_woready_1_908 & out_womask_1054; // @[RegisterRouter.scala:87:24] wire _out_T_10213 = ~out_rimask_1054; // @[RegisterRouter.scala:87:24] wire _out_T_10214 = ~out_wimask_1054; // @[RegisterRouter.scala:87:24] wire _out_T_10215 = ~out_romask_1054; // @[RegisterRouter.scala:87:24] wire _out_T_10216 = ~out_womask_1054; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_902 = {hi_122, flags_0_go, _out_prepend_T_902}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10217 = out_prepend_902; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10218 = _out_T_10217; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_903 = _out_T_10218; // @[RegisterRouter.scala:87:24] wire out_rimask_1055 = |_out_rimask_T_1055; // @[RegisterRouter.scala:87:24] wire out_wimask_1055 = &_out_wimask_T_1055; // @[RegisterRouter.scala:87:24] wire out_romask_1055 = |_out_romask_T_1055; // @[RegisterRouter.scala:87:24] wire out_womask_1055 = &_out_womask_T_1055; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1055 = out_rivalid_1_909 & out_rimask_1055; // @[RegisterRouter.scala:87:24] wire _out_T_10220 = out_f_rivalid_1055; // @[RegisterRouter.scala:87:24] wire out_f_roready_1055 = out_roready_1_909 & out_romask_1055; // @[RegisterRouter.scala:87:24] wire _out_T_10221 = out_f_roready_1055; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1055 = out_wivalid_1_909 & out_wimask_1055; // @[RegisterRouter.scala:87:24] wire out_f_woready_1055 = out_woready_1_909 & out_womask_1055; // @[RegisterRouter.scala:87:24] wire _out_T_10222 = ~out_rimask_1055; // @[RegisterRouter.scala:87:24] wire _out_T_10223 = ~out_wimask_1055; // @[RegisterRouter.scala:87:24] wire _out_T_10224 = ~out_romask_1055; // @[RegisterRouter.scala:87:24] wire _out_T_10225 = ~out_womask_1055; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_903 = {hi_123, flags_0_go, _out_prepend_T_903}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10226 = out_prepend_903; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10227 = _out_T_10226; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_904 = _out_T_10227; // @[RegisterRouter.scala:87:24] wire out_rimask_1056 = |_out_rimask_T_1056; // @[RegisterRouter.scala:87:24] wire out_wimask_1056 = &_out_wimask_T_1056; // @[RegisterRouter.scala:87:24] wire out_romask_1056 = |_out_romask_T_1056; // @[RegisterRouter.scala:87:24] wire out_womask_1056 = &_out_womask_T_1056; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1056 = out_rivalid_1_910 & out_rimask_1056; // @[RegisterRouter.scala:87:24] wire _out_T_10229 = out_f_rivalid_1056; // @[RegisterRouter.scala:87:24] wire out_f_roready_1056 = out_roready_1_910 & out_romask_1056; // @[RegisterRouter.scala:87:24] wire _out_T_10230 = out_f_roready_1056; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1056 = out_wivalid_1_910 & out_wimask_1056; // @[RegisterRouter.scala:87:24] wire out_f_woready_1056 = out_woready_1_910 & out_womask_1056; // @[RegisterRouter.scala:87:24] wire _out_T_10231 = ~out_rimask_1056; // @[RegisterRouter.scala:87:24] wire _out_T_10232 = ~out_wimask_1056; // @[RegisterRouter.scala:87:24] wire _out_T_10233 = ~out_romask_1056; // @[RegisterRouter.scala:87:24] wire _out_T_10234 = ~out_womask_1056; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_904 = {hi_124, flags_0_go, _out_prepend_T_904}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10235 = out_prepend_904; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10236 = _out_T_10235; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_905 = _out_T_10236; // @[RegisterRouter.scala:87:24] wire out_rimask_1057 = |_out_rimask_T_1057; // @[RegisterRouter.scala:87:24] wire out_wimask_1057 = &_out_wimask_T_1057; // @[RegisterRouter.scala:87:24] wire out_romask_1057 = |_out_romask_T_1057; // @[RegisterRouter.scala:87:24] wire out_womask_1057 = &_out_womask_T_1057; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1057 = out_rivalid_1_911 & out_rimask_1057; // @[RegisterRouter.scala:87:24] wire _out_T_10238 = out_f_rivalid_1057; // @[RegisterRouter.scala:87:24] wire out_f_roready_1057 = out_roready_1_911 & out_romask_1057; // @[RegisterRouter.scala:87:24] wire _out_T_10239 = out_f_roready_1057; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1057 = out_wivalid_1_911 & out_wimask_1057; // @[RegisterRouter.scala:87:24] wire out_f_woready_1057 = out_woready_1_911 & out_womask_1057; // @[RegisterRouter.scala:87:24] wire _out_T_10240 = ~out_rimask_1057; // @[RegisterRouter.scala:87:24] wire _out_T_10241 = ~out_wimask_1057; // @[RegisterRouter.scala:87:24] wire _out_T_10242 = ~out_romask_1057; // @[RegisterRouter.scala:87:24] wire _out_T_10243 = ~out_womask_1057; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_905 = {hi_125, flags_0_go, _out_prepend_T_905}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10244 = out_prepend_905; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10245 = _out_T_10244; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_906 = _out_T_10245; // @[RegisterRouter.scala:87:24] wire out_rimask_1058 = |_out_rimask_T_1058; // @[RegisterRouter.scala:87:24] wire out_wimask_1058 = &_out_wimask_T_1058; // @[RegisterRouter.scala:87:24] wire out_romask_1058 = |_out_romask_T_1058; // @[RegisterRouter.scala:87:24] wire out_womask_1058 = &_out_womask_T_1058; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1058 = out_rivalid_1_912 & out_rimask_1058; // @[RegisterRouter.scala:87:24] wire _out_T_10247 = out_f_rivalid_1058; // @[RegisterRouter.scala:87:24] wire out_f_roready_1058 = out_roready_1_912 & out_romask_1058; // @[RegisterRouter.scala:87:24] wire _out_T_10248 = out_f_roready_1058; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1058 = out_wivalid_1_912 & out_wimask_1058; // @[RegisterRouter.scala:87:24] wire out_f_woready_1058 = out_woready_1_912 & out_womask_1058; // @[RegisterRouter.scala:87:24] wire _out_T_10249 = ~out_rimask_1058; // @[RegisterRouter.scala:87:24] wire _out_T_10250 = ~out_wimask_1058; // @[RegisterRouter.scala:87:24] wire _out_T_10251 = ~out_romask_1058; // @[RegisterRouter.scala:87:24] wire _out_T_10252 = ~out_womask_1058; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_906 = {hi_126, flags_0_go, _out_prepend_T_906}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10253 = out_prepend_906; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10254 = _out_T_10253; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_907 = _out_T_10254; // @[RegisterRouter.scala:87:24] wire out_rimask_1059 = |_out_rimask_T_1059; // @[RegisterRouter.scala:87:24] wire out_wimask_1059 = &_out_wimask_T_1059; // @[RegisterRouter.scala:87:24] wire out_romask_1059 = |_out_romask_T_1059; // @[RegisterRouter.scala:87:24] wire out_womask_1059 = &_out_womask_T_1059; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1059 = out_rivalid_1_913 & out_rimask_1059; // @[RegisterRouter.scala:87:24] wire _out_T_10256 = out_f_rivalid_1059; // @[RegisterRouter.scala:87:24] wire out_f_roready_1059 = out_roready_1_913 & out_romask_1059; // @[RegisterRouter.scala:87:24] wire _out_T_10257 = out_f_roready_1059; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1059 = out_wivalid_1_913 & out_wimask_1059; // @[RegisterRouter.scala:87:24] wire out_f_woready_1059 = out_woready_1_913 & out_womask_1059; // @[RegisterRouter.scala:87:24] wire _out_T_10258 = ~out_rimask_1059; // @[RegisterRouter.scala:87:24] wire _out_T_10259 = ~out_wimask_1059; // @[RegisterRouter.scala:87:24] wire _out_T_10260 = ~out_romask_1059; // @[RegisterRouter.scala:87:24] wire _out_T_10261 = ~out_womask_1059; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_907 = {hi_127, flags_0_go, _out_prepend_T_907}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10262 = out_prepend_907; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10263 = _out_T_10262; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_908 = _out_T_10263; // @[RegisterRouter.scala:87:24] wire out_rimask_1060 = |_out_rimask_T_1060; // @[RegisterRouter.scala:87:24] wire out_wimask_1060 = &_out_wimask_T_1060; // @[RegisterRouter.scala:87:24] wire out_romask_1060 = |_out_romask_T_1060; // @[RegisterRouter.scala:87:24] wire out_womask_1060 = &_out_womask_T_1060; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1060 = out_rivalid_1_914 & out_rimask_1060; // @[RegisterRouter.scala:87:24] wire _out_T_10265 = out_f_rivalid_1060; // @[RegisterRouter.scala:87:24] wire out_f_roready_1060 = out_roready_1_914 & out_romask_1060; // @[RegisterRouter.scala:87:24] wire _out_T_10266 = out_f_roready_1060; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1060 = out_wivalid_1_914 & out_wimask_1060; // @[RegisterRouter.scala:87:24] wire out_f_woready_1060 = out_woready_1_914 & out_womask_1060; // @[RegisterRouter.scala:87:24] wire _out_T_10267 = ~out_rimask_1060; // @[RegisterRouter.scala:87:24] wire _out_T_10268 = ~out_wimask_1060; // @[RegisterRouter.scala:87:24] wire _out_T_10269 = ~out_romask_1060; // @[RegisterRouter.scala:87:24] wire _out_T_10270 = ~out_womask_1060; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_908 = {hi_128, flags_0_go, _out_prepend_T_908}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10271 = out_prepend_908; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10272 = _out_T_10271; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_143 = _out_T_10272; // @[MuxLiteral.scala:49:48] wire out_rimask_1061 = |_out_rimask_T_1061; // @[RegisterRouter.scala:87:24] wire out_wimask_1061 = &_out_wimask_T_1061; // @[RegisterRouter.scala:87:24] wire out_romask_1061 = |_out_romask_T_1061; // @[RegisterRouter.scala:87:24] wire out_womask_1061 = &_out_womask_T_1061; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1061 = out_rivalid_1_915 & out_rimask_1061; // @[RegisterRouter.scala:87:24] wire _out_T_10274 = out_f_rivalid_1061; // @[RegisterRouter.scala:87:24] wire out_f_roready_1061 = out_roready_1_915 & out_romask_1061; // @[RegisterRouter.scala:87:24] wire _out_T_10275 = out_f_roready_1061; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1061 = out_wivalid_1_915 & out_wimask_1061; // @[RegisterRouter.scala:87:24] wire out_f_woready_1061 = out_woready_1_915 & out_womask_1061; // @[RegisterRouter.scala:87:24] wire _out_T_10276 = ~out_rimask_1061; // @[RegisterRouter.scala:87:24] wire _out_T_10277 = ~out_wimask_1061; // @[RegisterRouter.scala:87:24] wire _out_T_10278 = ~out_romask_1061; // @[RegisterRouter.scala:87:24] wire _out_T_10279 = ~out_womask_1061; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10281 = _out_T_10280; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_909 = _out_T_10281; // @[RegisterRouter.scala:87:24] wire out_rimask_1062 = |_out_rimask_T_1062; // @[RegisterRouter.scala:87:24] wire out_wimask_1062 = &_out_wimask_T_1062; // @[RegisterRouter.scala:87:24] wire out_romask_1062 = |_out_romask_T_1062; // @[RegisterRouter.scala:87:24] wire out_womask_1062 = &_out_womask_T_1062; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1062 = out_rivalid_1_916 & out_rimask_1062; // @[RegisterRouter.scala:87:24] wire _out_T_10283 = out_f_rivalid_1062; // @[RegisterRouter.scala:87:24] wire out_f_roready_1062 = out_roready_1_916 & out_romask_1062; // @[RegisterRouter.scala:87:24] wire _out_T_10284 = out_f_roready_1062; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1062 = out_wivalid_1_916 & out_wimask_1062; // @[RegisterRouter.scala:87:24] wire out_f_woready_1062 = out_woready_1_916 & out_womask_1062; // @[RegisterRouter.scala:87:24] wire _out_T_10285 = ~out_rimask_1062; // @[RegisterRouter.scala:87:24] wire _out_T_10286 = ~out_wimask_1062; // @[RegisterRouter.scala:87:24] wire _out_T_10287 = ~out_romask_1062; // @[RegisterRouter.scala:87:24] wire _out_T_10288 = ~out_womask_1062; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_909 = {hi_602, flags_0_go, _out_prepend_T_909}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10289 = out_prepend_909; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10290 = _out_T_10289; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_910 = _out_T_10290; // @[RegisterRouter.scala:87:24] wire out_rimask_1063 = |_out_rimask_T_1063; // @[RegisterRouter.scala:87:24] wire out_wimask_1063 = &_out_wimask_T_1063; // @[RegisterRouter.scala:87:24] wire out_romask_1063 = |_out_romask_T_1063; // @[RegisterRouter.scala:87:24] wire out_womask_1063 = &_out_womask_T_1063; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1063 = out_rivalid_1_917 & out_rimask_1063; // @[RegisterRouter.scala:87:24] wire _out_T_10292 = out_f_rivalid_1063; // @[RegisterRouter.scala:87:24] wire out_f_roready_1063 = out_roready_1_917 & out_romask_1063; // @[RegisterRouter.scala:87:24] wire _out_T_10293 = out_f_roready_1063; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1063 = out_wivalid_1_917 & out_wimask_1063; // @[RegisterRouter.scala:87:24] wire out_f_woready_1063 = out_woready_1_917 & out_womask_1063; // @[RegisterRouter.scala:87:24] wire _out_T_10294 = ~out_rimask_1063; // @[RegisterRouter.scala:87:24] wire _out_T_10295 = ~out_wimask_1063; // @[RegisterRouter.scala:87:24] wire _out_T_10296 = ~out_romask_1063; // @[RegisterRouter.scala:87:24] wire _out_T_10297 = ~out_womask_1063; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_910 = {hi_603, flags_0_go, _out_prepend_T_910}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10298 = out_prepend_910; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10299 = _out_T_10298; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_911 = _out_T_10299; // @[RegisterRouter.scala:87:24] wire out_rimask_1064 = |_out_rimask_T_1064; // @[RegisterRouter.scala:87:24] wire out_wimask_1064 = &_out_wimask_T_1064; // @[RegisterRouter.scala:87:24] wire out_romask_1064 = |_out_romask_T_1064; // @[RegisterRouter.scala:87:24] wire out_womask_1064 = &_out_womask_T_1064; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1064 = out_rivalid_1_918 & out_rimask_1064; // @[RegisterRouter.scala:87:24] wire _out_T_10301 = out_f_rivalid_1064; // @[RegisterRouter.scala:87:24] wire out_f_roready_1064 = out_roready_1_918 & out_romask_1064; // @[RegisterRouter.scala:87:24] wire _out_T_10302 = out_f_roready_1064; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1064 = out_wivalid_1_918 & out_wimask_1064; // @[RegisterRouter.scala:87:24] wire out_f_woready_1064 = out_woready_1_918 & out_womask_1064; // @[RegisterRouter.scala:87:24] wire _out_T_10303 = ~out_rimask_1064; // @[RegisterRouter.scala:87:24] wire _out_T_10304 = ~out_wimask_1064; // @[RegisterRouter.scala:87:24] wire _out_T_10305 = ~out_romask_1064; // @[RegisterRouter.scala:87:24] wire _out_T_10306 = ~out_womask_1064; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_911 = {hi_604, flags_0_go, _out_prepend_T_911}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10307 = out_prepend_911; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10308 = _out_T_10307; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_912 = _out_T_10308; // @[RegisterRouter.scala:87:24] wire out_rimask_1065 = |_out_rimask_T_1065; // @[RegisterRouter.scala:87:24] wire out_wimask_1065 = &_out_wimask_T_1065; // @[RegisterRouter.scala:87:24] wire out_romask_1065 = |_out_romask_T_1065; // @[RegisterRouter.scala:87:24] wire out_womask_1065 = &_out_womask_T_1065; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1065 = out_rivalid_1_919 & out_rimask_1065; // @[RegisterRouter.scala:87:24] wire _out_T_10310 = out_f_rivalid_1065; // @[RegisterRouter.scala:87:24] wire out_f_roready_1065 = out_roready_1_919 & out_romask_1065; // @[RegisterRouter.scala:87:24] wire _out_T_10311 = out_f_roready_1065; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1065 = out_wivalid_1_919 & out_wimask_1065; // @[RegisterRouter.scala:87:24] wire out_f_woready_1065 = out_woready_1_919 & out_womask_1065; // @[RegisterRouter.scala:87:24] wire _out_T_10312 = ~out_rimask_1065; // @[RegisterRouter.scala:87:24] wire _out_T_10313 = ~out_wimask_1065; // @[RegisterRouter.scala:87:24] wire _out_T_10314 = ~out_romask_1065; // @[RegisterRouter.scala:87:24] wire _out_T_10315 = ~out_womask_1065; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_912 = {hi_605, flags_0_go, _out_prepend_T_912}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10316 = out_prepend_912; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10317 = _out_T_10316; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_913 = _out_T_10317; // @[RegisterRouter.scala:87:24] wire out_rimask_1066 = |_out_rimask_T_1066; // @[RegisterRouter.scala:87:24] wire out_wimask_1066 = &_out_wimask_T_1066; // @[RegisterRouter.scala:87:24] wire out_romask_1066 = |_out_romask_T_1066; // @[RegisterRouter.scala:87:24] wire out_womask_1066 = &_out_womask_T_1066; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1066 = out_rivalid_1_920 & out_rimask_1066; // @[RegisterRouter.scala:87:24] wire _out_T_10319 = out_f_rivalid_1066; // @[RegisterRouter.scala:87:24] wire out_f_roready_1066 = out_roready_1_920 & out_romask_1066; // @[RegisterRouter.scala:87:24] wire _out_T_10320 = out_f_roready_1066; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1066 = out_wivalid_1_920 & out_wimask_1066; // @[RegisterRouter.scala:87:24] wire out_f_woready_1066 = out_woready_1_920 & out_womask_1066; // @[RegisterRouter.scala:87:24] wire _out_T_10321 = ~out_rimask_1066; // @[RegisterRouter.scala:87:24] wire _out_T_10322 = ~out_wimask_1066; // @[RegisterRouter.scala:87:24] wire _out_T_10323 = ~out_romask_1066; // @[RegisterRouter.scala:87:24] wire _out_T_10324 = ~out_womask_1066; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_913 = {hi_606, flags_0_go, _out_prepend_T_913}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10325 = out_prepend_913; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10326 = _out_T_10325; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_914 = _out_T_10326; // @[RegisterRouter.scala:87:24] wire out_rimask_1067 = |_out_rimask_T_1067; // @[RegisterRouter.scala:87:24] wire out_wimask_1067 = &_out_wimask_T_1067; // @[RegisterRouter.scala:87:24] wire out_romask_1067 = |_out_romask_T_1067; // @[RegisterRouter.scala:87:24] wire out_womask_1067 = &_out_womask_T_1067; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1067 = out_rivalid_1_921 & out_rimask_1067; // @[RegisterRouter.scala:87:24] wire _out_T_10328 = out_f_rivalid_1067; // @[RegisterRouter.scala:87:24] wire out_f_roready_1067 = out_roready_1_921 & out_romask_1067; // @[RegisterRouter.scala:87:24] wire _out_T_10329 = out_f_roready_1067; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1067 = out_wivalid_1_921 & out_wimask_1067; // @[RegisterRouter.scala:87:24] wire out_f_woready_1067 = out_woready_1_921 & out_womask_1067; // @[RegisterRouter.scala:87:24] wire _out_T_10330 = ~out_rimask_1067; // @[RegisterRouter.scala:87:24] wire _out_T_10331 = ~out_wimask_1067; // @[RegisterRouter.scala:87:24] wire _out_T_10332 = ~out_romask_1067; // @[RegisterRouter.scala:87:24] wire _out_T_10333 = ~out_womask_1067; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_914 = {hi_607, flags_0_go, _out_prepend_T_914}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10334 = out_prepend_914; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10335 = _out_T_10334; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_915 = _out_T_10335; // @[RegisterRouter.scala:87:24] wire out_rimask_1068 = |_out_rimask_T_1068; // @[RegisterRouter.scala:87:24] wire out_wimask_1068 = &_out_wimask_T_1068; // @[RegisterRouter.scala:87:24] wire out_romask_1068 = |_out_romask_T_1068; // @[RegisterRouter.scala:87:24] wire out_womask_1068 = &_out_womask_T_1068; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1068 = out_rivalid_1_922 & out_rimask_1068; // @[RegisterRouter.scala:87:24] wire _out_T_10337 = out_f_rivalid_1068; // @[RegisterRouter.scala:87:24] wire out_f_roready_1068 = out_roready_1_922 & out_romask_1068; // @[RegisterRouter.scala:87:24] wire _out_T_10338 = out_f_roready_1068; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1068 = out_wivalid_1_922 & out_wimask_1068; // @[RegisterRouter.scala:87:24] wire out_f_woready_1068 = out_woready_1_922 & out_womask_1068; // @[RegisterRouter.scala:87:24] wire _out_T_10339 = ~out_rimask_1068; // @[RegisterRouter.scala:87:24] wire _out_T_10340 = ~out_wimask_1068; // @[RegisterRouter.scala:87:24] wire _out_T_10341 = ~out_romask_1068; // @[RegisterRouter.scala:87:24] wire _out_T_10342 = ~out_womask_1068; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_915 = {hi_608, flags_0_go, _out_prepend_T_915}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10343 = out_prepend_915; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10344 = _out_T_10343; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_203 = _out_T_10344; // @[MuxLiteral.scala:49:48] wire out_rimask_1069 = |_out_rimask_T_1069; // @[RegisterRouter.scala:87:24] wire out_wimask_1069 = &_out_wimask_T_1069; // @[RegisterRouter.scala:87:24] wire out_romask_1069 = |_out_romask_T_1069; // @[RegisterRouter.scala:87:24] wire out_womask_1069 = &_out_womask_T_1069; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1069 = out_rivalid_1_923 & out_rimask_1069; // @[RegisterRouter.scala:87:24] wire _out_T_10346 = out_f_rivalid_1069; // @[RegisterRouter.scala:87:24] wire out_f_roready_1069 = out_roready_1_923 & out_romask_1069; // @[RegisterRouter.scala:87:24] wire _out_T_10347 = out_f_roready_1069; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1069 = out_wivalid_1_923 & out_wimask_1069; // @[RegisterRouter.scala:87:24] wire out_f_woready_1069 = out_woready_1_923 & out_womask_1069; // @[RegisterRouter.scala:87:24] wire _out_T_10348 = ~out_rimask_1069; // @[RegisterRouter.scala:87:24] wire _out_T_10349 = ~out_wimask_1069; // @[RegisterRouter.scala:87:24] wire _out_T_10350 = ~out_romask_1069; // @[RegisterRouter.scala:87:24] wire _out_T_10351 = ~out_womask_1069; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10353 = _out_T_10352; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_916 = _out_T_10353; // @[RegisterRouter.scala:87:24] wire out_rimask_1070 = |_out_rimask_T_1070; // @[RegisterRouter.scala:87:24] wire out_wimask_1070 = &_out_wimask_T_1070; // @[RegisterRouter.scala:87:24] wire out_romask_1070 = |_out_romask_T_1070; // @[RegisterRouter.scala:87:24] wire out_womask_1070 = &_out_womask_T_1070; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1070 = out_rivalid_1_924 & out_rimask_1070; // @[RegisterRouter.scala:87:24] wire _out_T_10355 = out_f_rivalid_1070; // @[RegisterRouter.scala:87:24] wire out_f_roready_1070 = out_roready_1_924 & out_romask_1070; // @[RegisterRouter.scala:87:24] wire _out_T_10356 = out_f_roready_1070; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1070 = out_wivalid_1_924 & out_wimask_1070; // @[RegisterRouter.scala:87:24] wire out_f_woready_1070 = out_woready_1_924 & out_womask_1070; // @[RegisterRouter.scala:87:24] wire _out_T_10357 = ~out_rimask_1070; // @[RegisterRouter.scala:87:24] wire _out_T_10358 = ~out_wimask_1070; // @[RegisterRouter.scala:87:24] wire _out_T_10359 = ~out_romask_1070; // @[RegisterRouter.scala:87:24] wire _out_T_10360 = ~out_womask_1070; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_916 = {hi_722, flags_0_go, _out_prepend_T_916}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10361 = out_prepend_916; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10362 = _out_T_10361; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_917 = _out_T_10362; // @[RegisterRouter.scala:87:24] wire out_rimask_1071 = |_out_rimask_T_1071; // @[RegisterRouter.scala:87:24] wire out_wimask_1071 = &_out_wimask_T_1071; // @[RegisterRouter.scala:87:24] wire out_romask_1071 = |_out_romask_T_1071; // @[RegisterRouter.scala:87:24] wire out_womask_1071 = &_out_womask_T_1071; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1071 = out_rivalid_1_925 & out_rimask_1071; // @[RegisterRouter.scala:87:24] wire _out_T_10364 = out_f_rivalid_1071; // @[RegisterRouter.scala:87:24] wire out_f_roready_1071 = out_roready_1_925 & out_romask_1071; // @[RegisterRouter.scala:87:24] wire _out_T_10365 = out_f_roready_1071; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1071 = out_wivalid_1_925 & out_wimask_1071; // @[RegisterRouter.scala:87:24] wire out_f_woready_1071 = out_woready_1_925 & out_womask_1071; // @[RegisterRouter.scala:87:24] wire _out_T_10366 = ~out_rimask_1071; // @[RegisterRouter.scala:87:24] wire _out_T_10367 = ~out_wimask_1071; // @[RegisterRouter.scala:87:24] wire _out_T_10368 = ~out_romask_1071; // @[RegisterRouter.scala:87:24] wire _out_T_10369 = ~out_womask_1071; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_917 = {hi_723, flags_0_go, _out_prepend_T_917}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10370 = out_prepend_917; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10371 = _out_T_10370; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_918 = _out_T_10371; // @[RegisterRouter.scala:87:24] wire out_rimask_1072 = |_out_rimask_T_1072; // @[RegisterRouter.scala:87:24] wire out_wimask_1072 = &_out_wimask_T_1072; // @[RegisterRouter.scala:87:24] wire out_romask_1072 = |_out_romask_T_1072; // @[RegisterRouter.scala:87:24] wire out_womask_1072 = &_out_womask_T_1072; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1072 = out_rivalid_1_926 & out_rimask_1072; // @[RegisterRouter.scala:87:24] wire _out_T_10373 = out_f_rivalid_1072; // @[RegisterRouter.scala:87:24] wire out_f_roready_1072 = out_roready_1_926 & out_romask_1072; // @[RegisterRouter.scala:87:24] wire _out_T_10374 = out_f_roready_1072; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1072 = out_wivalid_1_926 & out_wimask_1072; // @[RegisterRouter.scala:87:24] wire out_f_woready_1072 = out_woready_1_926 & out_womask_1072; // @[RegisterRouter.scala:87:24] wire _out_T_10375 = ~out_rimask_1072; // @[RegisterRouter.scala:87:24] wire _out_T_10376 = ~out_wimask_1072; // @[RegisterRouter.scala:87:24] wire _out_T_10377 = ~out_romask_1072; // @[RegisterRouter.scala:87:24] wire _out_T_10378 = ~out_womask_1072; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_918 = {hi_724, flags_0_go, _out_prepend_T_918}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10379 = out_prepend_918; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10380 = _out_T_10379; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_919 = _out_T_10380; // @[RegisterRouter.scala:87:24] wire out_rimask_1073 = |_out_rimask_T_1073; // @[RegisterRouter.scala:87:24] wire out_wimask_1073 = &_out_wimask_T_1073; // @[RegisterRouter.scala:87:24] wire out_romask_1073 = |_out_romask_T_1073; // @[RegisterRouter.scala:87:24] wire out_womask_1073 = &_out_womask_T_1073; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1073 = out_rivalid_1_927 & out_rimask_1073; // @[RegisterRouter.scala:87:24] wire _out_T_10382 = out_f_rivalid_1073; // @[RegisterRouter.scala:87:24] wire out_f_roready_1073 = out_roready_1_927 & out_romask_1073; // @[RegisterRouter.scala:87:24] wire _out_T_10383 = out_f_roready_1073; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1073 = out_wivalid_1_927 & out_wimask_1073; // @[RegisterRouter.scala:87:24] wire out_f_woready_1073 = out_woready_1_927 & out_womask_1073; // @[RegisterRouter.scala:87:24] wire _out_T_10384 = ~out_rimask_1073; // @[RegisterRouter.scala:87:24] wire _out_T_10385 = ~out_wimask_1073; // @[RegisterRouter.scala:87:24] wire _out_T_10386 = ~out_romask_1073; // @[RegisterRouter.scala:87:24] wire _out_T_10387 = ~out_womask_1073; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_919 = {hi_725, flags_0_go, _out_prepend_T_919}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10388 = out_prepend_919; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10389 = _out_T_10388; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_920 = _out_T_10389; // @[RegisterRouter.scala:87:24] wire out_rimask_1074 = |_out_rimask_T_1074; // @[RegisterRouter.scala:87:24] wire out_wimask_1074 = &_out_wimask_T_1074; // @[RegisterRouter.scala:87:24] wire out_romask_1074 = |_out_romask_T_1074; // @[RegisterRouter.scala:87:24] wire out_womask_1074 = &_out_womask_T_1074; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1074 = out_rivalid_1_928 & out_rimask_1074; // @[RegisterRouter.scala:87:24] wire _out_T_10391 = out_f_rivalid_1074; // @[RegisterRouter.scala:87:24] wire out_f_roready_1074 = out_roready_1_928 & out_romask_1074; // @[RegisterRouter.scala:87:24] wire _out_T_10392 = out_f_roready_1074; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1074 = out_wivalid_1_928 & out_wimask_1074; // @[RegisterRouter.scala:87:24] wire out_f_woready_1074 = out_woready_1_928 & out_womask_1074; // @[RegisterRouter.scala:87:24] wire _out_T_10393 = ~out_rimask_1074; // @[RegisterRouter.scala:87:24] wire _out_T_10394 = ~out_wimask_1074; // @[RegisterRouter.scala:87:24] wire _out_T_10395 = ~out_romask_1074; // @[RegisterRouter.scala:87:24] wire _out_T_10396 = ~out_womask_1074; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_920 = {hi_726, flags_0_go, _out_prepend_T_920}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10397 = out_prepend_920; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10398 = _out_T_10397; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_921 = _out_T_10398; // @[RegisterRouter.scala:87:24] wire out_rimask_1075 = |_out_rimask_T_1075; // @[RegisterRouter.scala:87:24] wire out_wimask_1075 = &_out_wimask_T_1075; // @[RegisterRouter.scala:87:24] wire out_romask_1075 = |_out_romask_T_1075; // @[RegisterRouter.scala:87:24] wire out_womask_1075 = &_out_womask_T_1075; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1075 = out_rivalid_1_929 & out_rimask_1075; // @[RegisterRouter.scala:87:24] wire _out_T_10400 = out_f_rivalid_1075; // @[RegisterRouter.scala:87:24] wire out_f_roready_1075 = out_roready_1_929 & out_romask_1075; // @[RegisterRouter.scala:87:24] wire _out_T_10401 = out_f_roready_1075; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1075 = out_wivalid_1_929 & out_wimask_1075; // @[RegisterRouter.scala:87:24] wire out_f_woready_1075 = out_woready_1_929 & out_womask_1075; // @[RegisterRouter.scala:87:24] wire _out_T_10402 = ~out_rimask_1075; // @[RegisterRouter.scala:87:24] wire _out_T_10403 = ~out_wimask_1075; // @[RegisterRouter.scala:87:24] wire _out_T_10404 = ~out_romask_1075; // @[RegisterRouter.scala:87:24] wire _out_T_10405 = ~out_womask_1075; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_921 = {hi_727, flags_0_go, _out_prepend_T_921}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10406 = out_prepend_921; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10407 = _out_T_10406; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_922 = _out_T_10407; // @[RegisterRouter.scala:87:24] wire out_rimask_1076 = |_out_rimask_T_1076; // @[RegisterRouter.scala:87:24] wire out_wimask_1076 = &_out_wimask_T_1076; // @[RegisterRouter.scala:87:24] wire out_romask_1076 = |_out_romask_T_1076; // @[RegisterRouter.scala:87:24] wire out_womask_1076 = &_out_womask_T_1076; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1076 = out_rivalid_1_930 & out_rimask_1076; // @[RegisterRouter.scala:87:24] wire _out_T_10409 = out_f_rivalid_1076; // @[RegisterRouter.scala:87:24] wire out_f_roready_1076 = out_roready_1_930 & out_romask_1076; // @[RegisterRouter.scala:87:24] wire _out_T_10410 = out_f_roready_1076; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1076 = out_wivalid_1_930 & out_wimask_1076; // @[RegisterRouter.scala:87:24] wire out_f_woready_1076 = out_woready_1_930 & out_womask_1076; // @[RegisterRouter.scala:87:24] wire _out_T_10411 = ~out_rimask_1076; // @[RegisterRouter.scala:87:24] wire _out_T_10412 = ~out_wimask_1076; // @[RegisterRouter.scala:87:24] wire _out_T_10413 = ~out_romask_1076; // @[RegisterRouter.scala:87:24] wire _out_T_10414 = ~out_womask_1076; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_922 = {hi_728, flags_0_go, _out_prepend_T_922}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10415 = out_prepend_922; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10416 = _out_T_10415; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_218 = _out_T_10416; // @[MuxLiteral.scala:49:48] wire out_rimask_1077 = |_out_rimask_T_1077; // @[RegisterRouter.scala:87:24] wire out_wimask_1077 = &_out_wimask_T_1077; // @[RegisterRouter.scala:87:24] wire out_romask_1077 = |_out_romask_T_1077; // @[RegisterRouter.scala:87:24] wire out_womask_1077 = &_out_womask_T_1077; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1077 = out_rivalid_1_931 & out_rimask_1077; // @[RegisterRouter.scala:87:24] wire _out_T_10418 = out_f_rivalid_1077; // @[RegisterRouter.scala:87:24] wire out_f_roready_1077 = out_roready_1_931 & out_romask_1077; // @[RegisterRouter.scala:87:24] wire _out_T_10419 = out_f_roready_1077; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1077 = out_wivalid_1_931 & out_wimask_1077; // @[RegisterRouter.scala:87:24] wire _out_T_10420 = out_f_wivalid_1077; // @[RegisterRouter.scala:87:24] wire out_f_woready_1077 = out_woready_1_931 & out_womask_1077; // @[RegisterRouter.scala:87:24] wire _out_T_10421 = out_f_woready_1077; // @[RegisterRouter.scala:87:24] wire _out_T_10422 = ~out_rimask_1077; // @[RegisterRouter.scala:87:24] wire _out_T_10423 = ~out_wimask_1077; // @[RegisterRouter.scala:87:24] wire _out_T_10424 = ~out_romask_1077; // @[RegisterRouter.scala:87:24] wire _out_T_10425 = ~out_womask_1077; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10427 = _out_T_10426; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_923 = _out_T_10427; // @[RegisterRouter.scala:87:24] wire out_rimask_1078 = |_out_rimask_T_1078; // @[RegisterRouter.scala:87:24] wire out_wimask_1078 = &_out_wimask_T_1078; // @[RegisterRouter.scala:87:24] wire out_romask_1078 = |_out_romask_T_1078; // @[RegisterRouter.scala:87:24] wire out_womask_1078 = &_out_womask_T_1078; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1078 = out_rivalid_1_932 & out_rimask_1078; // @[RegisterRouter.scala:87:24] wire _out_T_10429 = out_f_rivalid_1078; // @[RegisterRouter.scala:87:24] wire out_f_roready_1078 = out_roready_1_932 & out_romask_1078; // @[RegisterRouter.scala:87:24] wire _out_T_10430 = out_f_roready_1078; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1078 = out_wivalid_1_932 & out_wimask_1078; // @[RegisterRouter.scala:87:24] wire _out_T_10431 = out_f_wivalid_1078; // @[RegisterRouter.scala:87:24] wire out_f_woready_1078 = out_woready_1_932 & out_womask_1078; // @[RegisterRouter.scala:87:24] wire _out_T_10432 = out_f_woready_1078; // @[RegisterRouter.scala:87:24] wire _out_T_10433 = ~out_rimask_1078; // @[RegisterRouter.scala:87:24] wire _out_T_10434 = ~out_wimask_1078; // @[RegisterRouter.scala:87:24] wire _out_T_10435 = ~out_romask_1078; // @[RegisterRouter.scala:87:24] wire _out_T_10436 = ~out_womask_1078; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_923 = {programBufferMem_1, _out_prepend_T_923}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10437 = out_prepend_923; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10438 = _out_T_10437; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_924 = _out_T_10438; // @[RegisterRouter.scala:87:24] wire out_rimask_1079 = |_out_rimask_T_1079; // @[RegisterRouter.scala:87:24] wire out_wimask_1079 = &_out_wimask_T_1079; // @[RegisterRouter.scala:87:24] wire out_romask_1079 = |_out_romask_T_1079; // @[RegisterRouter.scala:87:24] wire out_womask_1079 = &_out_womask_T_1079; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1079 = out_rivalid_1_933 & out_rimask_1079; // @[RegisterRouter.scala:87:24] wire _out_T_10440 = out_f_rivalid_1079; // @[RegisterRouter.scala:87:24] wire out_f_roready_1079 = out_roready_1_933 & out_romask_1079; // @[RegisterRouter.scala:87:24] wire _out_T_10441 = out_f_roready_1079; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1079 = out_wivalid_1_933 & out_wimask_1079; // @[RegisterRouter.scala:87:24] wire _out_T_10442 = out_f_wivalid_1079; // @[RegisterRouter.scala:87:24] wire out_f_woready_1079 = out_woready_1_933 & out_womask_1079; // @[RegisterRouter.scala:87:24] wire _out_T_10443 = out_f_woready_1079; // @[RegisterRouter.scala:87:24] wire _out_T_10444 = ~out_rimask_1079; // @[RegisterRouter.scala:87:24] wire _out_T_10445 = ~out_wimask_1079; // @[RegisterRouter.scala:87:24] wire _out_T_10446 = ~out_romask_1079; // @[RegisterRouter.scala:87:24] wire _out_T_10447 = ~out_womask_1079; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_924 = {programBufferMem_2, _out_prepend_T_924}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10448 = out_prepend_924; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10449 = _out_T_10448; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_925 = _out_T_10449; // @[RegisterRouter.scala:87:24] wire out_rimask_1080 = |_out_rimask_T_1080; // @[RegisterRouter.scala:87:24] wire out_wimask_1080 = &_out_wimask_T_1080; // @[RegisterRouter.scala:87:24] wire out_romask_1080 = |_out_romask_T_1080; // @[RegisterRouter.scala:87:24] wire out_womask_1080 = &_out_womask_T_1080; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1080 = out_rivalid_1_934 & out_rimask_1080; // @[RegisterRouter.scala:87:24] wire _out_T_10451 = out_f_rivalid_1080; // @[RegisterRouter.scala:87:24] wire out_f_roready_1080 = out_roready_1_934 & out_romask_1080; // @[RegisterRouter.scala:87:24] wire _out_T_10452 = out_f_roready_1080; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1080 = out_wivalid_1_934 & out_wimask_1080; // @[RegisterRouter.scala:87:24] wire _out_T_10453 = out_f_wivalid_1080; // @[RegisterRouter.scala:87:24] wire out_f_woready_1080 = out_woready_1_934 & out_womask_1080; // @[RegisterRouter.scala:87:24] wire _out_T_10454 = out_f_woready_1080; // @[RegisterRouter.scala:87:24] wire _out_T_10455 = ~out_rimask_1080; // @[RegisterRouter.scala:87:24] wire _out_T_10456 = ~out_wimask_1080; // @[RegisterRouter.scala:87:24] wire _out_T_10457 = ~out_romask_1080; // @[RegisterRouter.scala:87:24] wire _out_T_10458 = ~out_womask_1080; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_925 = {programBufferMem_3, _out_prepend_T_925}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10459 = out_prepend_925; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10460 = _out_T_10459; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_926 = _out_T_10460; // @[RegisterRouter.scala:87:24] wire out_rimask_1081 = |_out_rimask_T_1081; // @[RegisterRouter.scala:87:24] wire out_wimask_1081 = &_out_wimask_T_1081; // @[RegisterRouter.scala:87:24] wire out_romask_1081 = |_out_romask_T_1081; // @[RegisterRouter.scala:87:24] wire out_womask_1081 = &_out_womask_T_1081; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1081 = out_rivalid_1_935 & out_rimask_1081; // @[RegisterRouter.scala:87:24] wire _out_T_10462 = out_f_rivalid_1081; // @[RegisterRouter.scala:87:24] wire out_f_roready_1081 = out_roready_1_935 & out_romask_1081; // @[RegisterRouter.scala:87:24] wire _out_T_10463 = out_f_roready_1081; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1081 = out_wivalid_1_935 & out_wimask_1081; // @[RegisterRouter.scala:87:24] wire _out_T_10464 = out_f_wivalid_1081; // @[RegisterRouter.scala:87:24] wire out_f_woready_1081 = out_woready_1_935 & out_womask_1081; // @[RegisterRouter.scala:87:24] wire _out_T_10465 = out_f_woready_1081; // @[RegisterRouter.scala:87:24] wire _out_T_10466 = ~out_rimask_1081; // @[RegisterRouter.scala:87:24] wire _out_T_10467 = ~out_wimask_1081; // @[RegisterRouter.scala:87:24] wire _out_T_10468 = ~out_romask_1081; // @[RegisterRouter.scala:87:24] wire _out_T_10469 = ~out_womask_1081; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_926 = {programBufferMem_4, _out_prepend_T_926}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10470 = out_prepend_926; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10471 = _out_T_10470; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_927 = _out_T_10471; // @[RegisterRouter.scala:87:24] wire out_rimask_1082 = |_out_rimask_T_1082; // @[RegisterRouter.scala:87:24] wire out_wimask_1082 = &_out_wimask_T_1082; // @[RegisterRouter.scala:87:24] wire out_romask_1082 = |_out_romask_T_1082; // @[RegisterRouter.scala:87:24] wire out_womask_1082 = &_out_womask_T_1082; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1082 = out_rivalid_1_936 & out_rimask_1082; // @[RegisterRouter.scala:87:24] wire _out_T_10473 = out_f_rivalid_1082; // @[RegisterRouter.scala:87:24] wire out_f_roready_1082 = out_roready_1_936 & out_romask_1082; // @[RegisterRouter.scala:87:24] wire _out_T_10474 = out_f_roready_1082; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1082 = out_wivalid_1_936 & out_wimask_1082; // @[RegisterRouter.scala:87:24] wire _out_T_10475 = out_f_wivalid_1082; // @[RegisterRouter.scala:87:24] wire out_f_woready_1082 = out_woready_1_936 & out_womask_1082; // @[RegisterRouter.scala:87:24] wire _out_T_10476 = out_f_woready_1082; // @[RegisterRouter.scala:87:24] wire _out_T_10477 = ~out_rimask_1082; // @[RegisterRouter.scala:87:24] wire _out_T_10478 = ~out_wimask_1082; // @[RegisterRouter.scala:87:24] wire _out_T_10479 = ~out_romask_1082; // @[RegisterRouter.scala:87:24] wire _out_T_10480 = ~out_womask_1082; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_927 = {programBufferMem_5, _out_prepend_T_927}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10481 = out_prepend_927; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10482 = _out_T_10481; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_928 = _out_T_10482; // @[RegisterRouter.scala:87:24] wire out_rimask_1083 = |_out_rimask_T_1083; // @[RegisterRouter.scala:87:24] wire out_wimask_1083 = &_out_wimask_T_1083; // @[RegisterRouter.scala:87:24] wire out_romask_1083 = |_out_romask_T_1083; // @[RegisterRouter.scala:87:24] wire out_womask_1083 = &_out_womask_T_1083; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1083 = out_rivalid_1_937 & out_rimask_1083; // @[RegisterRouter.scala:87:24] wire _out_T_10484 = out_f_rivalid_1083; // @[RegisterRouter.scala:87:24] wire out_f_roready_1083 = out_roready_1_937 & out_romask_1083; // @[RegisterRouter.scala:87:24] wire _out_T_10485 = out_f_roready_1083; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1083 = out_wivalid_1_937 & out_wimask_1083; // @[RegisterRouter.scala:87:24] wire _out_T_10486 = out_f_wivalid_1083; // @[RegisterRouter.scala:87:24] wire out_f_woready_1083 = out_woready_1_937 & out_womask_1083; // @[RegisterRouter.scala:87:24] wire _out_T_10487 = out_f_woready_1083; // @[RegisterRouter.scala:87:24] wire _out_T_10488 = ~out_rimask_1083; // @[RegisterRouter.scala:87:24] wire _out_T_10489 = ~out_wimask_1083; // @[RegisterRouter.scala:87:24] wire _out_T_10490 = ~out_romask_1083; // @[RegisterRouter.scala:87:24] wire _out_T_10491 = ~out_womask_1083; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_928 = {programBufferMem_6, _out_prepend_T_928}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10492 = out_prepend_928; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10493 = _out_T_10492; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_929 = _out_T_10493; // @[RegisterRouter.scala:87:24] wire out_rimask_1084 = |_out_rimask_T_1084; // @[RegisterRouter.scala:87:24] wire out_wimask_1084 = &_out_wimask_T_1084; // @[RegisterRouter.scala:87:24] wire out_romask_1084 = |_out_romask_T_1084; // @[RegisterRouter.scala:87:24] wire out_womask_1084 = &_out_womask_T_1084; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1084 = out_rivalid_1_938 & out_rimask_1084; // @[RegisterRouter.scala:87:24] wire _out_T_10495 = out_f_rivalid_1084; // @[RegisterRouter.scala:87:24] wire out_f_roready_1084 = out_roready_1_938 & out_romask_1084; // @[RegisterRouter.scala:87:24] wire _out_T_10496 = out_f_roready_1084; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1084 = out_wivalid_1_938 & out_wimask_1084; // @[RegisterRouter.scala:87:24] wire _out_T_10497 = out_f_wivalid_1084; // @[RegisterRouter.scala:87:24] wire out_f_woready_1084 = out_woready_1_938 & out_womask_1084; // @[RegisterRouter.scala:87:24] wire _out_T_10498 = out_f_woready_1084; // @[RegisterRouter.scala:87:24] wire _out_T_10499 = ~out_rimask_1084; // @[RegisterRouter.scala:87:24] wire _out_T_10500 = ~out_wimask_1084; // @[RegisterRouter.scala:87:24] wire _out_T_10501 = ~out_romask_1084; // @[RegisterRouter.scala:87:24] wire _out_T_10502 = ~out_womask_1084; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_929 = {programBufferMem_7, _out_prepend_T_929}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10503 = out_prepend_929; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10504 = _out_T_10503; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_104 = _out_T_10504; // @[MuxLiteral.scala:49:48] wire out_rimask_1085 = |_out_rimask_T_1085; // @[RegisterRouter.scala:87:24] wire out_wimask_1085 = &_out_wimask_T_1085; // @[RegisterRouter.scala:87:24] wire out_romask_1085 = |_out_romask_T_1085; // @[RegisterRouter.scala:87:24] wire out_womask_1085 = &_out_womask_T_1085; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1085 = out_rivalid_1_939 & out_rimask_1085; // @[RegisterRouter.scala:87:24] wire _out_T_10506 = out_f_rivalid_1085; // @[RegisterRouter.scala:87:24] wire out_f_roready_1085 = out_roready_1_939 & out_romask_1085; // @[RegisterRouter.scala:87:24] wire _out_T_10507 = out_f_roready_1085; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1085 = out_wivalid_1_939 & out_wimask_1085; // @[RegisterRouter.scala:87:24] wire out_f_woready_1085 = out_woready_1_939 & out_womask_1085; // @[RegisterRouter.scala:87:24] wire _out_T_10508 = ~out_rimask_1085; // @[RegisterRouter.scala:87:24] wire _out_T_10509 = ~out_wimask_1085; // @[RegisterRouter.scala:87:24] wire _out_T_10510 = ~out_romask_1085; // @[RegisterRouter.scala:87:24] wire _out_T_10511 = ~out_womask_1085; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10513 = _out_T_10512; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_930 = _out_T_10513; // @[RegisterRouter.scala:87:24] wire out_rimask_1086 = |_out_rimask_T_1086; // @[RegisterRouter.scala:87:24] wire out_wimask_1086 = &_out_wimask_T_1086; // @[RegisterRouter.scala:87:24] wire out_romask_1086 = |_out_romask_T_1086; // @[RegisterRouter.scala:87:24] wire out_womask_1086 = &_out_womask_T_1086; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1086 = out_rivalid_1_940 & out_rimask_1086; // @[RegisterRouter.scala:87:24] wire _out_T_10515 = out_f_rivalid_1086; // @[RegisterRouter.scala:87:24] wire out_f_roready_1086 = out_roready_1_940 & out_romask_1086; // @[RegisterRouter.scala:87:24] wire _out_T_10516 = out_f_roready_1086; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1086 = out_wivalid_1_940 & out_wimask_1086; // @[RegisterRouter.scala:87:24] wire out_f_woready_1086 = out_woready_1_940 & out_womask_1086; // @[RegisterRouter.scala:87:24] wire _out_T_10517 = ~out_rimask_1086; // @[RegisterRouter.scala:87:24] wire _out_T_10518 = ~out_wimask_1086; // @[RegisterRouter.scala:87:24] wire _out_T_10519 = ~out_romask_1086; // @[RegisterRouter.scala:87:24] wire _out_T_10520 = ~out_womask_1086; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_930 = {hi_978, flags_0_go, _out_prepend_T_930}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10521 = out_prepend_930; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10522 = _out_T_10521; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_931 = _out_T_10522; // @[RegisterRouter.scala:87:24] wire out_rimask_1087 = |_out_rimask_T_1087; // @[RegisterRouter.scala:87:24] wire out_wimask_1087 = &_out_wimask_T_1087; // @[RegisterRouter.scala:87:24] wire out_romask_1087 = |_out_romask_T_1087; // @[RegisterRouter.scala:87:24] wire out_womask_1087 = &_out_womask_T_1087; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1087 = out_rivalid_1_941 & out_rimask_1087; // @[RegisterRouter.scala:87:24] wire _out_T_10524 = out_f_rivalid_1087; // @[RegisterRouter.scala:87:24] wire out_f_roready_1087 = out_roready_1_941 & out_romask_1087; // @[RegisterRouter.scala:87:24] wire _out_T_10525 = out_f_roready_1087; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1087 = out_wivalid_1_941 & out_wimask_1087; // @[RegisterRouter.scala:87:24] wire out_f_woready_1087 = out_woready_1_941 & out_womask_1087; // @[RegisterRouter.scala:87:24] wire _out_T_10526 = ~out_rimask_1087; // @[RegisterRouter.scala:87:24] wire _out_T_10527 = ~out_wimask_1087; // @[RegisterRouter.scala:87:24] wire _out_T_10528 = ~out_romask_1087; // @[RegisterRouter.scala:87:24] wire _out_T_10529 = ~out_womask_1087; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_931 = {hi_979, flags_0_go, _out_prepend_T_931}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10530 = out_prepend_931; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10531 = _out_T_10530; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_932 = _out_T_10531; // @[RegisterRouter.scala:87:24] wire out_rimask_1088 = |_out_rimask_T_1088; // @[RegisterRouter.scala:87:24] wire out_wimask_1088 = &_out_wimask_T_1088; // @[RegisterRouter.scala:87:24] wire out_romask_1088 = |_out_romask_T_1088; // @[RegisterRouter.scala:87:24] wire out_womask_1088 = &_out_womask_T_1088; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1088 = out_rivalid_1_942 & out_rimask_1088; // @[RegisterRouter.scala:87:24] wire _out_T_10533 = out_f_rivalid_1088; // @[RegisterRouter.scala:87:24] wire out_f_roready_1088 = out_roready_1_942 & out_romask_1088; // @[RegisterRouter.scala:87:24] wire _out_T_10534 = out_f_roready_1088; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1088 = out_wivalid_1_942 & out_wimask_1088; // @[RegisterRouter.scala:87:24] wire out_f_woready_1088 = out_woready_1_942 & out_womask_1088; // @[RegisterRouter.scala:87:24] wire _out_T_10535 = ~out_rimask_1088; // @[RegisterRouter.scala:87:24] wire _out_T_10536 = ~out_wimask_1088; // @[RegisterRouter.scala:87:24] wire _out_T_10537 = ~out_romask_1088; // @[RegisterRouter.scala:87:24] wire _out_T_10538 = ~out_womask_1088; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_932 = {hi_980, flags_0_go, _out_prepend_T_932}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10539 = out_prepend_932; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10540 = _out_T_10539; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_933 = _out_T_10540; // @[RegisterRouter.scala:87:24] wire out_rimask_1089 = |_out_rimask_T_1089; // @[RegisterRouter.scala:87:24] wire out_wimask_1089 = &_out_wimask_T_1089; // @[RegisterRouter.scala:87:24] wire out_romask_1089 = |_out_romask_T_1089; // @[RegisterRouter.scala:87:24] wire out_womask_1089 = &_out_womask_T_1089; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1089 = out_rivalid_1_943 & out_rimask_1089; // @[RegisterRouter.scala:87:24] wire _out_T_10542 = out_f_rivalid_1089; // @[RegisterRouter.scala:87:24] wire out_f_roready_1089 = out_roready_1_943 & out_romask_1089; // @[RegisterRouter.scala:87:24] wire _out_T_10543 = out_f_roready_1089; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1089 = out_wivalid_1_943 & out_wimask_1089; // @[RegisterRouter.scala:87:24] wire out_f_woready_1089 = out_woready_1_943 & out_womask_1089; // @[RegisterRouter.scala:87:24] wire _out_T_10544 = ~out_rimask_1089; // @[RegisterRouter.scala:87:24] wire _out_T_10545 = ~out_wimask_1089; // @[RegisterRouter.scala:87:24] wire _out_T_10546 = ~out_romask_1089; // @[RegisterRouter.scala:87:24] wire _out_T_10547 = ~out_womask_1089; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_933 = {hi_981, flags_0_go, _out_prepend_T_933}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10548 = out_prepend_933; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10549 = _out_T_10548; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_934 = _out_T_10549; // @[RegisterRouter.scala:87:24] wire out_rimask_1090 = |_out_rimask_T_1090; // @[RegisterRouter.scala:87:24] wire out_wimask_1090 = &_out_wimask_T_1090; // @[RegisterRouter.scala:87:24] wire out_romask_1090 = |_out_romask_T_1090; // @[RegisterRouter.scala:87:24] wire out_womask_1090 = &_out_womask_T_1090; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1090 = out_rivalid_1_944 & out_rimask_1090; // @[RegisterRouter.scala:87:24] wire _out_T_10551 = out_f_rivalid_1090; // @[RegisterRouter.scala:87:24] wire out_f_roready_1090 = out_roready_1_944 & out_romask_1090; // @[RegisterRouter.scala:87:24] wire _out_T_10552 = out_f_roready_1090; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1090 = out_wivalid_1_944 & out_wimask_1090; // @[RegisterRouter.scala:87:24] wire out_f_woready_1090 = out_woready_1_944 & out_womask_1090; // @[RegisterRouter.scala:87:24] wire _out_T_10553 = ~out_rimask_1090; // @[RegisterRouter.scala:87:24] wire _out_T_10554 = ~out_wimask_1090; // @[RegisterRouter.scala:87:24] wire _out_T_10555 = ~out_romask_1090; // @[RegisterRouter.scala:87:24] wire _out_T_10556 = ~out_womask_1090; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_934 = {hi_982, flags_0_go, _out_prepend_T_934}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10557 = out_prepend_934; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10558 = _out_T_10557; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_935 = _out_T_10558; // @[RegisterRouter.scala:87:24] wire out_rimask_1091 = |_out_rimask_T_1091; // @[RegisterRouter.scala:87:24] wire out_wimask_1091 = &_out_wimask_T_1091; // @[RegisterRouter.scala:87:24] wire out_romask_1091 = |_out_romask_T_1091; // @[RegisterRouter.scala:87:24] wire out_womask_1091 = &_out_womask_T_1091; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1091 = out_rivalid_1_945 & out_rimask_1091; // @[RegisterRouter.scala:87:24] wire _out_T_10560 = out_f_rivalid_1091; // @[RegisterRouter.scala:87:24] wire out_f_roready_1091 = out_roready_1_945 & out_romask_1091; // @[RegisterRouter.scala:87:24] wire _out_T_10561 = out_f_roready_1091; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1091 = out_wivalid_1_945 & out_wimask_1091; // @[RegisterRouter.scala:87:24] wire out_f_woready_1091 = out_woready_1_945 & out_womask_1091; // @[RegisterRouter.scala:87:24] wire _out_T_10562 = ~out_rimask_1091; // @[RegisterRouter.scala:87:24] wire _out_T_10563 = ~out_wimask_1091; // @[RegisterRouter.scala:87:24] wire _out_T_10564 = ~out_romask_1091; // @[RegisterRouter.scala:87:24] wire _out_T_10565 = ~out_womask_1091; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_935 = {hi_983, flags_0_go, _out_prepend_T_935}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10566 = out_prepend_935; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10567 = _out_T_10566; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_936 = _out_T_10567; // @[RegisterRouter.scala:87:24] wire out_rimask_1092 = |_out_rimask_T_1092; // @[RegisterRouter.scala:87:24] wire out_wimask_1092 = &_out_wimask_T_1092; // @[RegisterRouter.scala:87:24] wire out_romask_1092 = |_out_romask_T_1092; // @[RegisterRouter.scala:87:24] wire out_womask_1092 = &_out_womask_T_1092; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1092 = out_rivalid_1_946 & out_rimask_1092; // @[RegisterRouter.scala:87:24] wire _out_T_10569 = out_f_rivalid_1092; // @[RegisterRouter.scala:87:24] wire out_f_roready_1092 = out_roready_1_946 & out_romask_1092; // @[RegisterRouter.scala:87:24] wire _out_T_10570 = out_f_roready_1092; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1092 = out_wivalid_1_946 & out_wimask_1092; // @[RegisterRouter.scala:87:24] wire out_f_woready_1092 = out_woready_1_946 & out_womask_1092; // @[RegisterRouter.scala:87:24] wire _out_T_10571 = ~out_rimask_1092; // @[RegisterRouter.scala:87:24] wire _out_T_10572 = ~out_wimask_1092; // @[RegisterRouter.scala:87:24] wire _out_T_10573 = ~out_romask_1092; // @[RegisterRouter.scala:87:24] wire _out_T_10574 = ~out_womask_1092; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_936 = {hi_984, flags_0_go, _out_prepend_T_936}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10575 = out_prepend_936; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10576 = _out_T_10575; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_250 = _out_T_10576; // @[MuxLiteral.scala:49:48] wire out_rimask_1093 = |_out_rimask_T_1093; // @[RegisterRouter.scala:87:24] wire out_wimask_1093 = &_out_wimask_T_1093; // @[RegisterRouter.scala:87:24] wire out_romask_1093 = |_out_romask_T_1093; // @[RegisterRouter.scala:87:24] wire out_womask_1093 = &_out_womask_T_1093; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1093 = out_rivalid_1_947 & out_rimask_1093; // @[RegisterRouter.scala:87:24] wire _out_T_10578 = out_f_rivalid_1093; // @[RegisterRouter.scala:87:24] wire out_f_roready_1093 = out_roready_1_947 & out_romask_1093; // @[RegisterRouter.scala:87:24] wire _out_T_10579 = out_f_roready_1093; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1093 = out_wivalid_1_947 & out_wimask_1093; // @[RegisterRouter.scala:87:24] wire out_f_woready_1093 = out_woready_1_947 & out_womask_1093; // @[RegisterRouter.scala:87:24] wire _out_T_10580 = ~out_rimask_1093; // @[RegisterRouter.scala:87:24] wire _out_T_10581 = ~out_wimask_1093; // @[RegisterRouter.scala:87:24] wire _out_T_10582 = ~out_romask_1093; // @[RegisterRouter.scala:87:24] wire _out_T_10583 = ~out_womask_1093; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10585 = _out_T_10584; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_937 = _out_T_10585; // @[RegisterRouter.scala:87:24] wire out_rimask_1094 = |_out_rimask_T_1094; // @[RegisterRouter.scala:87:24] wire out_wimask_1094 = &_out_wimask_T_1094; // @[RegisterRouter.scala:87:24] wire out_romask_1094 = |_out_romask_T_1094; // @[RegisterRouter.scala:87:24] wire out_womask_1094 = &_out_womask_T_1094; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1094 = out_rivalid_1_948 & out_rimask_1094; // @[RegisterRouter.scala:87:24] wire _out_T_10587 = out_f_rivalid_1094; // @[RegisterRouter.scala:87:24] wire out_f_roready_1094 = out_roready_1_948 & out_romask_1094; // @[RegisterRouter.scala:87:24] wire _out_T_10588 = out_f_roready_1094; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1094 = out_wivalid_1_948 & out_wimask_1094; // @[RegisterRouter.scala:87:24] wire out_f_woready_1094 = out_woready_1_948 & out_womask_1094; // @[RegisterRouter.scala:87:24] wire _out_T_10589 = ~out_rimask_1094; // @[RegisterRouter.scala:87:24] wire _out_T_10590 = ~out_wimask_1094; // @[RegisterRouter.scala:87:24] wire _out_T_10591 = ~out_romask_1094; // @[RegisterRouter.scala:87:24] wire _out_T_10592 = ~out_womask_1094; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_937 = {hi_826, flags_0_go, _out_prepend_T_937}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10593 = out_prepend_937; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10594 = _out_T_10593; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_938 = _out_T_10594; // @[RegisterRouter.scala:87:24] wire out_rimask_1095 = |_out_rimask_T_1095; // @[RegisterRouter.scala:87:24] wire out_wimask_1095 = &_out_wimask_T_1095; // @[RegisterRouter.scala:87:24] wire out_romask_1095 = |_out_romask_T_1095; // @[RegisterRouter.scala:87:24] wire out_womask_1095 = &_out_womask_T_1095; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1095 = out_rivalid_1_949 & out_rimask_1095; // @[RegisterRouter.scala:87:24] wire _out_T_10596 = out_f_rivalid_1095; // @[RegisterRouter.scala:87:24] wire out_f_roready_1095 = out_roready_1_949 & out_romask_1095; // @[RegisterRouter.scala:87:24] wire _out_T_10597 = out_f_roready_1095; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1095 = out_wivalid_1_949 & out_wimask_1095; // @[RegisterRouter.scala:87:24] wire out_f_woready_1095 = out_woready_1_949 & out_womask_1095; // @[RegisterRouter.scala:87:24] wire _out_T_10598 = ~out_rimask_1095; // @[RegisterRouter.scala:87:24] wire _out_T_10599 = ~out_wimask_1095; // @[RegisterRouter.scala:87:24] wire _out_T_10600 = ~out_romask_1095; // @[RegisterRouter.scala:87:24] wire _out_T_10601 = ~out_womask_1095; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_938 = {hi_827, flags_0_go, _out_prepend_T_938}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10602 = out_prepend_938; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10603 = _out_T_10602; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_939 = _out_T_10603; // @[RegisterRouter.scala:87:24] wire out_rimask_1096 = |_out_rimask_T_1096; // @[RegisterRouter.scala:87:24] wire out_wimask_1096 = &_out_wimask_T_1096; // @[RegisterRouter.scala:87:24] wire out_romask_1096 = |_out_romask_T_1096; // @[RegisterRouter.scala:87:24] wire out_womask_1096 = &_out_womask_T_1096; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1096 = out_rivalid_1_950 & out_rimask_1096; // @[RegisterRouter.scala:87:24] wire _out_T_10605 = out_f_rivalid_1096; // @[RegisterRouter.scala:87:24] wire out_f_roready_1096 = out_roready_1_950 & out_romask_1096; // @[RegisterRouter.scala:87:24] wire _out_T_10606 = out_f_roready_1096; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1096 = out_wivalid_1_950 & out_wimask_1096; // @[RegisterRouter.scala:87:24] wire out_f_woready_1096 = out_woready_1_950 & out_womask_1096; // @[RegisterRouter.scala:87:24] wire _out_T_10607 = ~out_rimask_1096; // @[RegisterRouter.scala:87:24] wire _out_T_10608 = ~out_wimask_1096; // @[RegisterRouter.scala:87:24] wire _out_T_10609 = ~out_romask_1096; // @[RegisterRouter.scala:87:24] wire _out_T_10610 = ~out_womask_1096; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_939 = {hi_828, flags_0_go, _out_prepend_T_939}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10611 = out_prepend_939; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10612 = _out_T_10611; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_940 = _out_T_10612; // @[RegisterRouter.scala:87:24] wire out_rimask_1097 = |_out_rimask_T_1097; // @[RegisterRouter.scala:87:24] wire out_wimask_1097 = &_out_wimask_T_1097; // @[RegisterRouter.scala:87:24] wire out_romask_1097 = |_out_romask_T_1097; // @[RegisterRouter.scala:87:24] wire out_womask_1097 = &_out_womask_T_1097; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1097 = out_rivalid_1_951 & out_rimask_1097; // @[RegisterRouter.scala:87:24] wire _out_T_10614 = out_f_rivalid_1097; // @[RegisterRouter.scala:87:24] wire out_f_roready_1097 = out_roready_1_951 & out_romask_1097; // @[RegisterRouter.scala:87:24] wire _out_T_10615 = out_f_roready_1097; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1097 = out_wivalid_1_951 & out_wimask_1097; // @[RegisterRouter.scala:87:24] wire out_f_woready_1097 = out_woready_1_951 & out_womask_1097; // @[RegisterRouter.scala:87:24] wire _out_T_10616 = ~out_rimask_1097; // @[RegisterRouter.scala:87:24] wire _out_T_10617 = ~out_wimask_1097; // @[RegisterRouter.scala:87:24] wire _out_T_10618 = ~out_romask_1097; // @[RegisterRouter.scala:87:24] wire _out_T_10619 = ~out_womask_1097; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_940 = {hi_829, flags_0_go, _out_prepend_T_940}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10620 = out_prepend_940; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10621 = _out_T_10620; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_941 = _out_T_10621; // @[RegisterRouter.scala:87:24] wire out_rimask_1098 = |_out_rimask_T_1098; // @[RegisterRouter.scala:87:24] wire out_wimask_1098 = &_out_wimask_T_1098; // @[RegisterRouter.scala:87:24] wire out_romask_1098 = |_out_romask_T_1098; // @[RegisterRouter.scala:87:24] wire out_womask_1098 = &_out_womask_T_1098; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1098 = out_rivalid_1_952 & out_rimask_1098; // @[RegisterRouter.scala:87:24] wire _out_T_10623 = out_f_rivalid_1098; // @[RegisterRouter.scala:87:24] wire out_f_roready_1098 = out_roready_1_952 & out_romask_1098; // @[RegisterRouter.scala:87:24] wire _out_T_10624 = out_f_roready_1098; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1098 = out_wivalid_1_952 & out_wimask_1098; // @[RegisterRouter.scala:87:24] wire out_f_woready_1098 = out_woready_1_952 & out_womask_1098; // @[RegisterRouter.scala:87:24] wire _out_T_10625 = ~out_rimask_1098; // @[RegisterRouter.scala:87:24] wire _out_T_10626 = ~out_wimask_1098; // @[RegisterRouter.scala:87:24] wire _out_T_10627 = ~out_romask_1098; // @[RegisterRouter.scala:87:24] wire _out_T_10628 = ~out_womask_1098; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_941 = {hi_830, flags_0_go, _out_prepend_T_941}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10629 = out_prepend_941; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10630 = _out_T_10629; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_942 = _out_T_10630; // @[RegisterRouter.scala:87:24] wire out_rimask_1099 = |_out_rimask_T_1099; // @[RegisterRouter.scala:87:24] wire out_wimask_1099 = &_out_wimask_T_1099; // @[RegisterRouter.scala:87:24] wire out_romask_1099 = |_out_romask_T_1099; // @[RegisterRouter.scala:87:24] wire out_womask_1099 = &_out_womask_T_1099; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1099 = out_rivalid_1_953 & out_rimask_1099; // @[RegisterRouter.scala:87:24] wire _out_T_10632 = out_f_rivalid_1099; // @[RegisterRouter.scala:87:24] wire out_f_roready_1099 = out_roready_1_953 & out_romask_1099; // @[RegisterRouter.scala:87:24] wire _out_T_10633 = out_f_roready_1099; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1099 = out_wivalid_1_953 & out_wimask_1099; // @[RegisterRouter.scala:87:24] wire out_f_woready_1099 = out_woready_1_953 & out_womask_1099; // @[RegisterRouter.scala:87:24] wire _out_T_10634 = ~out_rimask_1099; // @[RegisterRouter.scala:87:24] wire _out_T_10635 = ~out_wimask_1099; // @[RegisterRouter.scala:87:24] wire _out_T_10636 = ~out_romask_1099; // @[RegisterRouter.scala:87:24] wire _out_T_10637 = ~out_womask_1099; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_942 = {hi_831, flags_0_go, _out_prepend_T_942}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10638 = out_prepend_942; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10639 = _out_T_10638; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_943 = _out_T_10639; // @[RegisterRouter.scala:87:24] wire out_rimask_1100 = |_out_rimask_T_1100; // @[RegisterRouter.scala:87:24] wire out_wimask_1100 = &_out_wimask_T_1100; // @[RegisterRouter.scala:87:24] wire out_romask_1100 = |_out_romask_T_1100; // @[RegisterRouter.scala:87:24] wire out_womask_1100 = &_out_womask_T_1100; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1100 = out_rivalid_1_954 & out_rimask_1100; // @[RegisterRouter.scala:87:24] wire _out_T_10641 = out_f_rivalid_1100; // @[RegisterRouter.scala:87:24] wire out_f_roready_1100 = out_roready_1_954 & out_romask_1100; // @[RegisterRouter.scala:87:24] wire _out_T_10642 = out_f_roready_1100; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1100 = out_wivalid_1_954 & out_wimask_1100; // @[RegisterRouter.scala:87:24] wire out_f_woready_1100 = out_woready_1_954 & out_womask_1100; // @[RegisterRouter.scala:87:24] wire _out_T_10643 = ~out_rimask_1100; // @[RegisterRouter.scala:87:24] wire _out_T_10644 = ~out_wimask_1100; // @[RegisterRouter.scala:87:24] wire _out_T_10645 = ~out_romask_1100; // @[RegisterRouter.scala:87:24] wire _out_T_10646 = ~out_womask_1100; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_943 = {hi_832, flags_0_go, _out_prepend_T_943}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10647 = out_prepend_943; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10648 = _out_T_10647; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_231 = _out_T_10648; // @[MuxLiteral.scala:49:48] wire out_rimask_1101 = |_out_rimask_T_1101; // @[RegisterRouter.scala:87:24] wire out_wimask_1101 = &_out_wimask_T_1101; // @[RegisterRouter.scala:87:24] wire out_romask_1101 = |_out_romask_T_1101; // @[RegisterRouter.scala:87:24] wire out_womask_1101 = &_out_womask_T_1101; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1101 = out_rivalid_1_955 & out_rimask_1101; // @[RegisterRouter.scala:87:24] wire _out_T_10650 = out_f_rivalid_1101; // @[RegisterRouter.scala:87:24] wire out_f_roready_1101 = out_roready_1_955 & out_romask_1101; // @[RegisterRouter.scala:87:24] wire _out_T_10651 = out_f_roready_1101; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1101 = out_wivalid_1_955 & out_wimask_1101; // @[RegisterRouter.scala:87:24] wire out_f_woready_1101 = out_woready_1_955 & out_womask_1101; // @[RegisterRouter.scala:87:24] wire _out_T_10652 = ~out_rimask_1101; // @[RegisterRouter.scala:87:24] wire _out_T_10653 = ~out_wimask_1101; // @[RegisterRouter.scala:87:24] wire _out_T_10654 = ~out_romask_1101; // @[RegisterRouter.scala:87:24] wire _out_T_10655 = ~out_womask_1101; // @[RegisterRouter.scala:87:24] wire out_rimask_1102 = |_out_rimask_T_1102; // @[RegisterRouter.scala:87:24] wire out_wimask_1102 = &_out_wimask_T_1102; // @[RegisterRouter.scala:87:24] wire out_romask_1102 = |_out_romask_T_1102; // @[RegisterRouter.scala:87:24] wire out_womask_1102 = &_out_womask_T_1102; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1102 = out_rivalid_1_956 & out_rimask_1102; // @[RegisterRouter.scala:87:24] wire _out_T_10659 = out_f_rivalid_1102; // @[RegisterRouter.scala:87:24] wire out_f_roready_1102 = out_roready_1_956 & out_romask_1102; // @[RegisterRouter.scala:87:24] wire _out_T_10660 = out_f_roready_1102; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1102 = out_wivalid_1_956 & out_wimask_1102; // @[RegisterRouter.scala:87:24] wire out_f_woready_1102 = out_woready_1_956 & out_womask_1102; // @[RegisterRouter.scala:87:24] wire _out_T_10661 = ~out_rimask_1102; // @[RegisterRouter.scala:87:24] wire _out_T_10662 = ~out_wimask_1102; // @[RegisterRouter.scala:87:24] wire _out_T_10663 = ~out_romask_1102; // @[RegisterRouter.scala:87:24] wire _out_T_10664 = ~out_womask_1102; // @[RegisterRouter.scala:87:24] wire out_rimask_1103 = |_out_rimask_T_1103; // @[RegisterRouter.scala:87:24] wire out_wimask_1103 = &_out_wimask_T_1103; // @[RegisterRouter.scala:87:24] wire out_romask_1103 = |_out_romask_T_1103; // @[RegisterRouter.scala:87:24] wire out_womask_1103 = &_out_womask_T_1103; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1103 = out_rivalid_1_957 & out_rimask_1103; // @[RegisterRouter.scala:87:24] wire _out_T_10668 = out_f_rivalid_1103; // @[RegisterRouter.scala:87:24] wire out_f_roready_1103 = out_roready_1_957 & out_romask_1103; // @[RegisterRouter.scala:87:24] wire _out_T_10669 = out_f_roready_1103; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1103 = out_wivalid_1_957 & out_wimask_1103; // @[RegisterRouter.scala:87:24] wire out_f_woready_1103 = out_woready_1_957 & out_womask_1103; // @[RegisterRouter.scala:87:24] wire _out_T_10670 = ~out_rimask_1103; // @[RegisterRouter.scala:87:24] wire _out_T_10671 = ~out_wimask_1103; // @[RegisterRouter.scala:87:24] wire _out_T_10672 = ~out_romask_1103; // @[RegisterRouter.scala:87:24] wire _out_T_10673 = ~out_womask_1103; // @[RegisterRouter.scala:87:24] wire out_rimask_1104 = |_out_rimask_T_1104; // @[RegisterRouter.scala:87:24] wire out_wimask_1104 = &_out_wimask_T_1104; // @[RegisterRouter.scala:87:24] wire out_romask_1104 = |_out_romask_T_1104; // @[RegisterRouter.scala:87:24] wire out_womask_1104 = &_out_womask_T_1104; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1104 = out_rivalid_1_958 & out_rimask_1104; // @[RegisterRouter.scala:87:24] wire _out_T_10677 = out_f_rivalid_1104; // @[RegisterRouter.scala:87:24] wire out_f_roready_1104 = out_roready_1_958 & out_romask_1104; // @[RegisterRouter.scala:87:24] wire _out_T_10678 = out_f_roready_1104; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1104 = out_wivalid_1_958 & out_wimask_1104; // @[RegisterRouter.scala:87:24] wire out_f_woready_1104 = out_woready_1_958 & out_womask_1104; // @[RegisterRouter.scala:87:24] wire _out_T_10679 = ~out_rimask_1104; // @[RegisterRouter.scala:87:24] wire _out_T_10680 = ~out_wimask_1104; // @[RegisterRouter.scala:87:24] wire _out_T_10681 = ~out_romask_1104; // @[RegisterRouter.scala:87:24] wire _out_T_10682 = ~out_womask_1104; // @[RegisterRouter.scala:87:24] wire out_rimask_1105 = |_out_rimask_T_1105; // @[RegisterRouter.scala:87:24] wire out_wimask_1105 = &_out_wimask_T_1105; // @[RegisterRouter.scala:87:24] wire out_romask_1105 = |_out_romask_T_1105; // @[RegisterRouter.scala:87:24] wire out_womask_1105 = &_out_womask_T_1105; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1105 = out_rivalid_1_959 & out_rimask_1105; // @[RegisterRouter.scala:87:24] wire _out_T_10686 = out_f_rivalid_1105; // @[RegisterRouter.scala:87:24] wire out_f_roready_1105 = out_roready_1_959 & out_romask_1105; // @[RegisterRouter.scala:87:24] wire _out_T_10687 = out_f_roready_1105; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1105 = out_wivalid_1_959 & out_wimask_1105; // @[RegisterRouter.scala:87:24] wire out_f_woready_1105 = out_woready_1_959 & out_womask_1105; // @[RegisterRouter.scala:87:24] wire _out_T_10688 = ~out_rimask_1105; // @[RegisterRouter.scala:87:24] wire _out_T_10689 = ~out_wimask_1105; // @[RegisterRouter.scala:87:24] wire _out_T_10690 = ~out_romask_1105; // @[RegisterRouter.scala:87:24] wire _out_T_10691 = ~out_womask_1105; // @[RegisterRouter.scala:87:24] wire out_rimask_1106 = |_out_rimask_T_1106; // @[RegisterRouter.scala:87:24] wire out_wimask_1106 = &_out_wimask_T_1106; // @[RegisterRouter.scala:87:24] wire out_romask_1106 = |_out_romask_T_1106; // @[RegisterRouter.scala:87:24] wire out_womask_1106 = &_out_womask_T_1106; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1106 = out_rivalid_1_960 & out_rimask_1106; // @[RegisterRouter.scala:87:24] wire _out_T_10695 = out_f_rivalid_1106; // @[RegisterRouter.scala:87:24] wire out_f_roready_1106 = out_roready_1_960 & out_romask_1106; // @[RegisterRouter.scala:87:24] wire _out_T_10696 = out_f_roready_1106; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1106 = out_wivalid_1_960 & out_wimask_1106; // @[RegisterRouter.scala:87:24] wire out_f_woready_1106 = out_woready_1_960 & out_womask_1106; // @[RegisterRouter.scala:87:24] wire _out_T_10697 = ~out_rimask_1106; // @[RegisterRouter.scala:87:24] wire _out_T_10698 = ~out_wimask_1106; // @[RegisterRouter.scala:87:24] wire _out_T_10699 = ~out_romask_1106; // @[RegisterRouter.scala:87:24] wire _out_T_10700 = ~out_womask_1106; // @[RegisterRouter.scala:87:24] wire out_rimask_1107 = |_out_rimask_T_1107; // @[RegisterRouter.scala:87:24] wire out_wimask_1107 = &_out_wimask_T_1107; // @[RegisterRouter.scala:87:24] wire out_romask_1107 = |_out_romask_T_1107; // @[RegisterRouter.scala:87:24] wire out_womask_1107 = &_out_womask_T_1107; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1107 = out_rivalid_1_961 & out_rimask_1107; // @[RegisterRouter.scala:87:24] wire _out_T_10704 = out_f_rivalid_1107; // @[RegisterRouter.scala:87:24] wire out_f_roready_1107 = out_roready_1_961 & out_romask_1107; // @[RegisterRouter.scala:87:24] wire _out_T_10705 = out_f_roready_1107; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1107 = out_wivalid_1_961 & out_wimask_1107; // @[RegisterRouter.scala:87:24] wire out_f_woready_1107 = out_woready_1_961 & out_womask_1107; // @[RegisterRouter.scala:87:24] wire _out_T_10706 = ~out_rimask_1107; // @[RegisterRouter.scala:87:24] wire _out_T_10707 = ~out_wimask_1107; // @[RegisterRouter.scala:87:24] wire _out_T_10708 = ~out_romask_1107; // @[RegisterRouter.scala:87:24] wire _out_T_10709 = ~out_womask_1107; // @[RegisterRouter.scala:87:24] wire out_rimask_1108 = |_out_rimask_T_1108; // @[RegisterRouter.scala:87:24] wire out_wimask_1108 = &_out_wimask_T_1108; // @[RegisterRouter.scala:87:24] wire out_romask_1108 = |_out_romask_T_1108; // @[RegisterRouter.scala:87:24] wire out_womask_1108 = &_out_womask_T_1108; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1108 = out_rivalid_1_962 & out_rimask_1108; // @[RegisterRouter.scala:87:24] wire _out_T_10713 = out_f_rivalid_1108; // @[RegisterRouter.scala:87:24] wire out_f_roready_1108 = out_roready_1_962 & out_romask_1108; // @[RegisterRouter.scala:87:24] wire _out_T_10714 = out_f_roready_1108; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1108 = out_wivalid_1_962 & out_wimask_1108; // @[RegisterRouter.scala:87:24] wire out_f_woready_1108 = out_woready_1_962 & out_womask_1108; // @[RegisterRouter.scala:87:24] wire _out_T_10715 = ~out_rimask_1108; // @[RegisterRouter.scala:87:24] wire _out_T_10716 = ~out_wimask_1108; // @[RegisterRouter.scala:87:24] wire _out_T_10717 = ~out_romask_1108; // @[RegisterRouter.scala:87:24] wire _out_T_10718 = ~out_womask_1108; // @[RegisterRouter.scala:87:24] wire out_rimask_1109 = |_out_rimask_T_1109; // @[RegisterRouter.scala:87:24] wire out_wimask_1109 = &_out_wimask_T_1109; // @[RegisterRouter.scala:87:24] wire out_romask_1109 = |_out_romask_T_1109; // @[RegisterRouter.scala:87:24] wire out_womask_1109 = &_out_womask_T_1109; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1109 = out_rivalid_1_963 & out_rimask_1109; // @[RegisterRouter.scala:87:24] wire _out_T_10722 = out_f_rivalid_1109; // @[RegisterRouter.scala:87:24] wire out_f_roready_1109 = out_roready_1_963 & out_romask_1109; // @[RegisterRouter.scala:87:24] wire _out_T_10723 = out_f_roready_1109; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1109 = out_wivalid_1_963 & out_wimask_1109; // @[RegisterRouter.scala:87:24] wire out_f_woready_1109 = out_woready_1_963 & out_womask_1109; // @[RegisterRouter.scala:87:24] wire _out_T_10724 = ~out_rimask_1109; // @[RegisterRouter.scala:87:24] wire _out_T_10725 = ~out_wimask_1109; // @[RegisterRouter.scala:87:24] wire _out_T_10726 = ~out_romask_1109; // @[RegisterRouter.scala:87:24] wire _out_T_10727 = ~out_womask_1109; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10729 = _out_T_10728; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_951 = _out_T_10729; // @[RegisterRouter.scala:87:24] wire out_rimask_1110 = |_out_rimask_T_1110; // @[RegisterRouter.scala:87:24] wire out_wimask_1110 = &_out_wimask_T_1110; // @[RegisterRouter.scala:87:24] wire out_romask_1110 = |_out_romask_T_1110; // @[RegisterRouter.scala:87:24] wire out_womask_1110 = &_out_womask_T_1110; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1110 = out_rivalid_1_964 & out_rimask_1110; // @[RegisterRouter.scala:87:24] wire _out_T_10731 = out_f_rivalid_1110; // @[RegisterRouter.scala:87:24] wire out_f_roready_1110 = out_roready_1_964 & out_romask_1110; // @[RegisterRouter.scala:87:24] wire _out_T_10732 = out_f_roready_1110; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1110 = out_wivalid_1_964 & out_wimask_1110; // @[RegisterRouter.scala:87:24] wire out_f_woready_1110 = out_woready_1_964 & out_womask_1110; // @[RegisterRouter.scala:87:24] wire _out_T_10733 = ~out_rimask_1110; // @[RegisterRouter.scala:87:24] wire _out_T_10734 = ~out_wimask_1110; // @[RegisterRouter.scala:87:24] wire _out_T_10735 = ~out_romask_1110; // @[RegisterRouter.scala:87:24] wire _out_T_10736 = ~out_womask_1110; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_951 = {hi_242, flags_0_go, _out_prepend_T_951}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10737 = out_prepend_951; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10738 = _out_T_10737; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_952 = _out_T_10738; // @[RegisterRouter.scala:87:24] wire out_rimask_1111 = |_out_rimask_T_1111; // @[RegisterRouter.scala:87:24] wire out_wimask_1111 = &_out_wimask_T_1111; // @[RegisterRouter.scala:87:24] wire out_romask_1111 = |_out_romask_T_1111; // @[RegisterRouter.scala:87:24] wire out_womask_1111 = &_out_womask_T_1111; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1111 = out_rivalid_1_965 & out_rimask_1111; // @[RegisterRouter.scala:87:24] wire _out_T_10740 = out_f_rivalid_1111; // @[RegisterRouter.scala:87:24] wire out_f_roready_1111 = out_roready_1_965 & out_romask_1111; // @[RegisterRouter.scala:87:24] wire _out_T_10741 = out_f_roready_1111; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1111 = out_wivalid_1_965 & out_wimask_1111; // @[RegisterRouter.scala:87:24] wire out_f_woready_1111 = out_woready_1_965 & out_womask_1111; // @[RegisterRouter.scala:87:24] wire _out_T_10742 = ~out_rimask_1111; // @[RegisterRouter.scala:87:24] wire _out_T_10743 = ~out_wimask_1111; // @[RegisterRouter.scala:87:24] wire _out_T_10744 = ~out_romask_1111; // @[RegisterRouter.scala:87:24] wire _out_T_10745 = ~out_womask_1111; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_952 = {hi_243, flags_0_go, _out_prepend_T_952}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10746 = out_prepend_952; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10747 = _out_T_10746; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_953 = _out_T_10747; // @[RegisterRouter.scala:87:24] wire out_rimask_1112 = |_out_rimask_T_1112; // @[RegisterRouter.scala:87:24] wire out_wimask_1112 = &_out_wimask_T_1112; // @[RegisterRouter.scala:87:24] wire out_romask_1112 = |_out_romask_T_1112; // @[RegisterRouter.scala:87:24] wire out_womask_1112 = &_out_womask_T_1112; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1112 = out_rivalid_1_966 & out_rimask_1112; // @[RegisterRouter.scala:87:24] wire _out_T_10749 = out_f_rivalid_1112; // @[RegisterRouter.scala:87:24] wire out_f_roready_1112 = out_roready_1_966 & out_romask_1112; // @[RegisterRouter.scala:87:24] wire _out_T_10750 = out_f_roready_1112; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1112 = out_wivalid_1_966 & out_wimask_1112; // @[RegisterRouter.scala:87:24] wire out_f_woready_1112 = out_woready_1_966 & out_womask_1112; // @[RegisterRouter.scala:87:24] wire _out_T_10751 = ~out_rimask_1112; // @[RegisterRouter.scala:87:24] wire _out_T_10752 = ~out_wimask_1112; // @[RegisterRouter.scala:87:24] wire _out_T_10753 = ~out_romask_1112; // @[RegisterRouter.scala:87:24] wire _out_T_10754 = ~out_womask_1112; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_953 = {hi_244, flags_0_go, _out_prepend_T_953}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10755 = out_prepend_953; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10756 = _out_T_10755; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_954 = _out_T_10756; // @[RegisterRouter.scala:87:24] wire out_rimask_1113 = |_out_rimask_T_1113; // @[RegisterRouter.scala:87:24] wire out_wimask_1113 = &_out_wimask_T_1113; // @[RegisterRouter.scala:87:24] wire out_romask_1113 = |_out_romask_T_1113; // @[RegisterRouter.scala:87:24] wire out_womask_1113 = &_out_womask_T_1113; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1113 = out_rivalid_1_967 & out_rimask_1113; // @[RegisterRouter.scala:87:24] wire _out_T_10758 = out_f_rivalid_1113; // @[RegisterRouter.scala:87:24] wire out_f_roready_1113 = out_roready_1_967 & out_romask_1113; // @[RegisterRouter.scala:87:24] wire _out_T_10759 = out_f_roready_1113; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1113 = out_wivalid_1_967 & out_wimask_1113; // @[RegisterRouter.scala:87:24] wire out_f_woready_1113 = out_woready_1_967 & out_womask_1113; // @[RegisterRouter.scala:87:24] wire _out_T_10760 = ~out_rimask_1113; // @[RegisterRouter.scala:87:24] wire _out_T_10761 = ~out_wimask_1113; // @[RegisterRouter.scala:87:24] wire _out_T_10762 = ~out_romask_1113; // @[RegisterRouter.scala:87:24] wire _out_T_10763 = ~out_womask_1113; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_954 = {hi_245, flags_0_go, _out_prepend_T_954}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10764 = out_prepend_954; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10765 = _out_T_10764; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_955 = _out_T_10765; // @[RegisterRouter.scala:87:24] wire out_rimask_1114 = |_out_rimask_T_1114; // @[RegisterRouter.scala:87:24] wire out_wimask_1114 = &_out_wimask_T_1114; // @[RegisterRouter.scala:87:24] wire out_romask_1114 = |_out_romask_T_1114; // @[RegisterRouter.scala:87:24] wire out_womask_1114 = &_out_womask_T_1114; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1114 = out_rivalid_1_968 & out_rimask_1114; // @[RegisterRouter.scala:87:24] wire _out_T_10767 = out_f_rivalid_1114; // @[RegisterRouter.scala:87:24] wire out_f_roready_1114 = out_roready_1_968 & out_romask_1114; // @[RegisterRouter.scala:87:24] wire _out_T_10768 = out_f_roready_1114; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1114 = out_wivalid_1_968 & out_wimask_1114; // @[RegisterRouter.scala:87:24] wire out_f_woready_1114 = out_woready_1_968 & out_womask_1114; // @[RegisterRouter.scala:87:24] wire _out_T_10769 = ~out_rimask_1114; // @[RegisterRouter.scala:87:24] wire _out_T_10770 = ~out_wimask_1114; // @[RegisterRouter.scala:87:24] wire _out_T_10771 = ~out_romask_1114; // @[RegisterRouter.scala:87:24] wire _out_T_10772 = ~out_womask_1114; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_955 = {hi_246, flags_0_go, _out_prepend_T_955}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10773 = out_prepend_955; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10774 = _out_T_10773; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_956 = _out_T_10774; // @[RegisterRouter.scala:87:24] wire out_rimask_1115 = |_out_rimask_T_1115; // @[RegisterRouter.scala:87:24] wire out_wimask_1115 = &_out_wimask_T_1115; // @[RegisterRouter.scala:87:24] wire out_romask_1115 = |_out_romask_T_1115; // @[RegisterRouter.scala:87:24] wire out_womask_1115 = &_out_womask_T_1115; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1115 = out_rivalid_1_969 & out_rimask_1115; // @[RegisterRouter.scala:87:24] wire _out_T_10776 = out_f_rivalid_1115; // @[RegisterRouter.scala:87:24] wire out_f_roready_1115 = out_roready_1_969 & out_romask_1115; // @[RegisterRouter.scala:87:24] wire _out_T_10777 = out_f_roready_1115; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1115 = out_wivalid_1_969 & out_wimask_1115; // @[RegisterRouter.scala:87:24] wire out_f_woready_1115 = out_woready_1_969 & out_womask_1115; // @[RegisterRouter.scala:87:24] wire _out_T_10778 = ~out_rimask_1115; // @[RegisterRouter.scala:87:24] wire _out_T_10779 = ~out_wimask_1115; // @[RegisterRouter.scala:87:24] wire _out_T_10780 = ~out_romask_1115; // @[RegisterRouter.scala:87:24] wire _out_T_10781 = ~out_womask_1115; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_956 = {hi_247, flags_0_go, _out_prepend_T_956}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10782 = out_prepend_956; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10783 = _out_T_10782; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_957 = _out_T_10783; // @[RegisterRouter.scala:87:24] wire out_rimask_1116 = |_out_rimask_T_1116; // @[RegisterRouter.scala:87:24] wire out_wimask_1116 = &_out_wimask_T_1116; // @[RegisterRouter.scala:87:24] wire out_romask_1116 = |_out_romask_T_1116; // @[RegisterRouter.scala:87:24] wire out_womask_1116 = &_out_womask_T_1116; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1116 = out_rivalid_1_970 & out_rimask_1116; // @[RegisterRouter.scala:87:24] wire _out_T_10785 = out_f_rivalid_1116; // @[RegisterRouter.scala:87:24] wire out_f_roready_1116 = out_roready_1_970 & out_romask_1116; // @[RegisterRouter.scala:87:24] wire _out_T_10786 = out_f_roready_1116; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1116 = out_wivalid_1_970 & out_wimask_1116; // @[RegisterRouter.scala:87:24] wire out_f_woready_1116 = out_woready_1_970 & out_womask_1116; // @[RegisterRouter.scala:87:24] wire _out_T_10787 = ~out_rimask_1116; // @[RegisterRouter.scala:87:24] wire _out_T_10788 = ~out_wimask_1116; // @[RegisterRouter.scala:87:24] wire _out_T_10789 = ~out_romask_1116; // @[RegisterRouter.scala:87:24] wire _out_T_10790 = ~out_womask_1116; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_957 = {hi_248, flags_0_go, _out_prepend_T_957}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10791 = out_prepend_957; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10792 = _out_T_10791; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_158 = _out_T_10792; // @[MuxLiteral.scala:49:48] wire out_rimask_1117 = |_out_rimask_T_1117; // @[RegisterRouter.scala:87:24] wire out_wimask_1117 = &_out_wimask_T_1117; // @[RegisterRouter.scala:87:24] wire out_romask_1117 = |_out_romask_T_1117; // @[RegisterRouter.scala:87:24] wire out_womask_1117 = &_out_womask_T_1117; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1117 = out_rivalid_1_971 & out_rimask_1117; // @[RegisterRouter.scala:87:24] wire _out_T_10794 = out_f_rivalid_1117; // @[RegisterRouter.scala:87:24] wire out_f_roready_1117 = out_roready_1_971 & out_romask_1117; // @[RegisterRouter.scala:87:24] wire _out_T_10795 = out_f_roready_1117; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1117 = out_wivalid_1_971 & out_wimask_1117; // @[RegisterRouter.scala:87:24] wire out_f_woready_1117 = out_woready_1_971 & out_womask_1117; // @[RegisterRouter.scala:87:24] wire _out_T_10796 = ~out_rimask_1117; // @[RegisterRouter.scala:87:24] wire _out_T_10797 = ~out_wimask_1117; // @[RegisterRouter.scala:87:24] wire _out_T_10798 = ~out_romask_1117; // @[RegisterRouter.scala:87:24] wire _out_T_10799 = ~out_womask_1117; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10801 = _out_T_10800; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_958 = _out_T_10801; // @[RegisterRouter.scala:87:24] wire out_rimask_1118 = |_out_rimask_T_1118; // @[RegisterRouter.scala:87:24] wire out_wimask_1118 = &_out_wimask_T_1118; // @[RegisterRouter.scala:87:24] wire out_romask_1118 = |_out_romask_T_1118; // @[RegisterRouter.scala:87:24] wire out_womask_1118 = &_out_womask_T_1118; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1118 = out_rivalid_1_972 & out_rimask_1118; // @[RegisterRouter.scala:87:24] wire _out_T_10803 = out_f_rivalid_1118; // @[RegisterRouter.scala:87:24] wire out_f_roready_1118 = out_roready_1_972 & out_romask_1118; // @[RegisterRouter.scala:87:24] wire _out_T_10804 = out_f_roready_1118; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1118 = out_wivalid_1_972 & out_wimask_1118; // @[RegisterRouter.scala:87:24] wire out_f_woready_1118 = out_woready_1_972 & out_womask_1118; // @[RegisterRouter.scala:87:24] wire _out_T_10805 = ~out_rimask_1118; // @[RegisterRouter.scala:87:24] wire _out_T_10806 = ~out_wimask_1118; // @[RegisterRouter.scala:87:24] wire _out_T_10807 = ~out_romask_1118; // @[RegisterRouter.scala:87:24] wire _out_T_10808 = ~out_womask_1118; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_958 = {hi_466, flags_0_go, _out_prepend_T_958}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10809 = out_prepend_958; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10810 = _out_T_10809; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_959 = _out_T_10810; // @[RegisterRouter.scala:87:24] wire out_rimask_1119 = |_out_rimask_T_1119; // @[RegisterRouter.scala:87:24] wire out_wimask_1119 = &_out_wimask_T_1119; // @[RegisterRouter.scala:87:24] wire out_romask_1119 = |_out_romask_T_1119; // @[RegisterRouter.scala:87:24] wire out_womask_1119 = &_out_womask_T_1119; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1119 = out_rivalid_1_973 & out_rimask_1119; // @[RegisterRouter.scala:87:24] wire _out_T_10812 = out_f_rivalid_1119; // @[RegisterRouter.scala:87:24] wire out_f_roready_1119 = out_roready_1_973 & out_romask_1119; // @[RegisterRouter.scala:87:24] wire _out_T_10813 = out_f_roready_1119; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1119 = out_wivalid_1_973 & out_wimask_1119; // @[RegisterRouter.scala:87:24] wire out_f_woready_1119 = out_woready_1_973 & out_womask_1119; // @[RegisterRouter.scala:87:24] wire _out_T_10814 = ~out_rimask_1119; // @[RegisterRouter.scala:87:24] wire _out_T_10815 = ~out_wimask_1119; // @[RegisterRouter.scala:87:24] wire _out_T_10816 = ~out_romask_1119; // @[RegisterRouter.scala:87:24] wire _out_T_10817 = ~out_womask_1119; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_959 = {hi_467, flags_0_go, _out_prepend_T_959}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10818 = out_prepend_959; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10819 = _out_T_10818; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_960 = _out_T_10819; // @[RegisterRouter.scala:87:24] wire out_rimask_1120 = |_out_rimask_T_1120; // @[RegisterRouter.scala:87:24] wire out_wimask_1120 = &_out_wimask_T_1120; // @[RegisterRouter.scala:87:24] wire out_romask_1120 = |_out_romask_T_1120; // @[RegisterRouter.scala:87:24] wire out_womask_1120 = &_out_womask_T_1120; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1120 = out_rivalid_1_974 & out_rimask_1120; // @[RegisterRouter.scala:87:24] wire _out_T_10821 = out_f_rivalid_1120; // @[RegisterRouter.scala:87:24] wire out_f_roready_1120 = out_roready_1_974 & out_romask_1120; // @[RegisterRouter.scala:87:24] wire _out_T_10822 = out_f_roready_1120; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1120 = out_wivalid_1_974 & out_wimask_1120; // @[RegisterRouter.scala:87:24] wire out_f_woready_1120 = out_woready_1_974 & out_womask_1120; // @[RegisterRouter.scala:87:24] wire _out_T_10823 = ~out_rimask_1120; // @[RegisterRouter.scala:87:24] wire _out_T_10824 = ~out_wimask_1120; // @[RegisterRouter.scala:87:24] wire _out_T_10825 = ~out_romask_1120; // @[RegisterRouter.scala:87:24] wire _out_T_10826 = ~out_womask_1120; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_960 = {hi_468, flags_0_go, _out_prepend_T_960}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10827 = out_prepend_960; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10828 = _out_T_10827; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_961 = _out_T_10828; // @[RegisterRouter.scala:87:24] wire out_rimask_1121 = |_out_rimask_T_1121; // @[RegisterRouter.scala:87:24] wire out_wimask_1121 = &_out_wimask_T_1121; // @[RegisterRouter.scala:87:24] wire out_romask_1121 = |_out_romask_T_1121; // @[RegisterRouter.scala:87:24] wire out_womask_1121 = &_out_womask_T_1121; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1121 = out_rivalid_1_975 & out_rimask_1121; // @[RegisterRouter.scala:87:24] wire _out_T_10830 = out_f_rivalid_1121; // @[RegisterRouter.scala:87:24] wire out_f_roready_1121 = out_roready_1_975 & out_romask_1121; // @[RegisterRouter.scala:87:24] wire _out_T_10831 = out_f_roready_1121; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1121 = out_wivalid_1_975 & out_wimask_1121; // @[RegisterRouter.scala:87:24] wire out_f_woready_1121 = out_woready_1_975 & out_womask_1121; // @[RegisterRouter.scala:87:24] wire _out_T_10832 = ~out_rimask_1121; // @[RegisterRouter.scala:87:24] wire _out_T_10833 = ~out_wimask_1121; // @[RegisterRouter.scala:87:24] wire _out_T_10834 = ~out_romask_1121; // @[RegisterRouter.scala:87:24] wire _out_T_10835 = ~out_womask_1121; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_961 = {hi_469, flags_0_go, _out_prepend_T_961}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10836 = out_prepend_961; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10837 = _out_T_10836; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_962 = _out_T_10837; // @[RegisterRouter.scala:87:24] wire out_rimask_1122 = |_out_rimask_T_1122; // @[RegisterRouter.scala:87:24] wire out_wimask_1122 = &_out_wimask_T_1122; // @[RegisterRouter.scala:87:24] wire out_romask_1122 = |_out_romask_T_1122; // @[RegisterRouter.scala:87:24] wire out_womask_1122 = &_out_womask_T_1122; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1122 = out_rivalid_1_976 & out_rimask_1122; // @[RegisterRouter.scala:87:24] wire _out_T_10839 = out_f_rivalid_1122; // @[RegisterRouter.scala:87:24] wire out_f_roready_1122 = out_roready_1_976 & out_romask_1122; // @[RegisterRouter.scala:87:24] wire _out_T_10840 = out_f_roready_1122; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1122 = out_wivalid_1_976 & out_wimask_1122; // @[RegisterRouter.scala:87:24] wire out_f_woready_1122 = out_woready_1_976 & out_womask_1122; // @[RegisterRouter.scala:87:24] wire _out_T_10841 = ~out_rimask_1122; // @[RegisterRouter.scala:87:24] wire _out_T_10842 = ~out_wimask_1122; // @[RegisterRouter.scala:87:24] wire _out_T_10843 = ~out_romask_1122; // @[RegisterRouter.scala:87:24] wire _out_T_10844 = ~out_womask_1122; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_962 = {hi_470, flags_0_go, _out_prepend_T_962}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10845 = out_prepend_962; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10846 = _out_T_10845; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_963 = _out_T_10846; // @[RegisterRouter.scala:87:24] wire out_rimask_1123 = |_out_rimask_T_1123; // @[RegisterRouter.scala:87:24] wire out_wimask_1123 = &_out_wimask_T_1123; // @[RegisterRouter.scala:87:24] wire out_romask_1123 = |_out_romask_T_1123; // @[RegisterRouter.scala:87:24] wire out_womask_1123 = &_out_womask_T_1123; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1123 = out_rivalid_1_977 & out_rimask_1123; // @[RegisterRouter.scala:87:24] wire _out_T_10848 = out_f_rivalid_1123; // @[RegisterRouter.scala:87:24] wire out_f_roready_1123 = out_roready_1_977 & out_romask_1123; // @[RegisterRouter.scala:87:24] wire _out_T_10849 = out_f_roready_1123; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1123 = out_wivalid_1_977 & out_wimask_1123; // @[RegisterRouter.scala:87:24] wire out_f_woready_1123 = out_woready_1_977 & out_womask_1123; // @[RegisterRouter.scala:87:24] wire _out_T_10850 = ~out_rimask_1123; // @[RegisterRouter.scala:87:24] wire _out_T_10851 = ~out_wimask_1123; // @[RegisterRouter.scala:87:24] wire _out_T_10852 = ~out_romask_1123; // @[RegisterRouter.scala:87:24] wire _out_T_10853 = ~out_womask_1123; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_963 = {hi_471, flags_0_go, _out_prepend_T_963}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10854 = out_prepend_963; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10855 = _out_T_10854; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_964 = _out_T_10855; // @[RegisterRouter.scala:87:24] wire out_rimask_1124 = |_out_rimask_T_1124; // @[RegisterRouter.scala:87:24] wire out_wimask_1124 = &_out_wimask_T_1124; // @[RegisterRouter.scala:87:24] wire out_romask_1124 = |_out_romask_T_1124; // @[RegisterRouter.scala:87:24] wire out_womask_1124 = &_out_womask_T_1124; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1124 = out_rivalid_1_978 & out_rimask_1124; // @[RegisterRouter.scala:87:24] wire _out_T_10857 = out_f_rivalid_1124; // @[RegisterRouter.scala:87:24] wire out_f_roready_1124 = out_roready_1_978 & out_romask_1124; // @[RegisterRouter.scala:87:24] wire _out_T_10858 = out_f_roready_1124; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1124 = out_wivalid_1_978 & out_wimask_1124; // @[RegisterRouter.scala:87:24] wire out_f_woready_1124 = out_woready_1_978 & out_womask_1124; // @[RegisterRouter.scala:87:24] wire _out_T_10859 = ~out_rimask_1124; // @[RegisterRouter.scala:87:24] wire _out_T_10860 = ~out_wimask_1124; // @[RegisterRouter.scala:87:24] wire _out_T_10861 = ~out_romask_1124; // @[RegisterRouter.scala:87:24] wire _out_T_10862 = ~out_womask_1124; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_964 = {hi_472, flags_0_go, _out_prepend_T_964}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10863 = out_prepend_964; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10864 = _out_T_10863; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_186 = _out_T_10864; // @[MuxLiteral.scala:49:48] wire out_rimask_1125 = |_out_rimask_T_1125; // @[RegisterRouter.scala:87:24] wire out_wimask_1125 = &_out_wimask_T_1125; // @[RegisterRouter.scala:87:24] wire out_romask_1125 = |_out_romask_T_1125; // @[RegisterRouter.scala:87:24] wire out_womask_1125 = &_out_womask_T_1125; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1125 = out_rivalid_1_979 & out_rimask_1125; // @[RegisterRouter.scala:87:24] wire _out_T_10866 = out_f_rivalid_1125; // @[RegisterRouter.scala:87:24] wire out_f_roready_1125 = out_roready_1_979 & out_romask_1125; // @[RegisterRouter.scala:87:24] wire _out_T_10867 = out_f_roready_1125; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1125 = out_wivalid_1_979 & out_wimask_1125; // @[RegisterRouter.scala:87:24] wire _out_T_10868 = out_f_wivalid_1125; // @[RegisterRouter.scala:87:24] wire out_f_woready_1125 = out_woready_1_979 & out_womask_1125; // @[RegisterRouter.scala:87:24] wire _out_T_10869 = out_f_woready_1125; // @[RegisterRouter.scala:87:24] wire _out_T_10870 = ~out_rimask_1125; // @[RegisterRouter.scala:87:24] wire _out_T_10871 = ~out_wimask_1125; // @[RegisterRouter.scala:87:24] wire _out_T_10872 = ~out_romask_1125; // @[RegisterRouter.scala:87:24] wire _out_T_10873 = ~out_womask_1125; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10875 = _out_T_10874; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_965 = _out_T_10875; // @[RegisterRouter.scala:87:24] wire out_rimask_1126 = |_out_rimask_T_1126; // @[RegisterRouter.scala:87:24] wire out_wimask_1126 = &_out_wimask_T_1126; // @[RegisterRouter.scala:87:24] wire out_romask_1126 = |_out_romask_T_1126; // @[RegisterRouter.scala:87:24] wire out_womask_1126 = &_out_womask_T_1126; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1126 = out_rivalid_1_980 & out_rimask_1126; // @[RegisterRouter.scala:87:24] wire _out_T_10877 = out_f_rivalid_1126; // @[RegisterRouter.scala:87:24] wire out_f_roready_1126 = out_roready_1_980 & out_romask_1126; // @[RegisterRouter.scala:87:24] wire _out_T_10878 = out_f_roready_1126; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1126 = out_wivalid_1_980 & out_wimask_1126; // @[RegisterRouter.scala:87:24] wire _out_T_10879 = out_f_wivalid_1126; // @[RegisterRouter.scala:87:24] wire out_f_woready_1126 = out_woready_1_980 & out_womask_1126; // @[RegisterRouter.scala:87:24] wire _out_T_10880 = out_f_woready_1126; // @[RegisterRouter.scala:87:24] wire _out_T_10881 = ~out_rimask_1126; // @[RegisterRouter.scala:87:24] wire _out_T_10882 = ~out_wimask_1126; // @[RegisterRouter.scala:87:24] wire _out_T_10883 = ~out_romask_1126; // @[RegisterRouter.scala:87:24] wire _out_T_10884 = ~out_womask_1126; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_965 = {abstractDataMem_17, _out_prepend_T_965}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10885 = out_prepend_965; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10886 = _out_T_10885; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_966 = _out_T_10886; // @[RegisterRouter.scala:87:24] wire out_rimask_1127 = |_out_rimask_T_1127; // @[RegisterRouter.scala:87:24] wire out_wimask_1127 = &_out_wimask_T_1127; // @[RegisterRouter.scala:87:24] wire out_romask_1127 = |_out_romask_T_1127; // @[RegisterRouter.scala:87:24] wire out_womask_1127 = &_out_womask_T_1127; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1127 = out_rivalid_1_981 & out_rimask_1127; // @[RegisterRouter.scala:87:24] wire _out_T_10888 = out_f_rivalid_1127; // @[RegisterRouter.scala:87:24] wire out_f_roready_1127 = out_roready_1_981 & out_romask_1127; // @[RegisterRouter.scala:87:24] wire _out_T_10889 = out_f_roready_1127; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1127 = out_wivalid_1_981 & out_wimask_1127; // @[RegisterRouter.scala:87:24] wire _out_T_10890 = out_f_wivalid_1127; // @[RegisterRouter.scala:87:24] wire out_f_woready_1127 = out_woready_1_981 & out_womask_1127; // @[RegisterRouter.scala:87:24] wire _out_T_10891 = out_f_woready_1127; // @[RegisterRouter.scala:87:24] wire _out_T_10892 = ~out_rimask_1127; // @[RegisterRouter.scala:87:24] wire _out_T_10893 = ~out_wimask_1127; // @[RegisterRouter.scala:87:24] wire _out_T_10894 = ~out_romask_1127; // @[RegisterRouter.scala:87:24] wire _out_T_10895 = ~out_womask_1127; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_966 = {abstractDataMem_18, _out_prepend_T_966}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10896 = out_prepend_966; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10897 = _out_T_10896; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_967 = _out_T_10897; // @[RegisterRouter.scala:87:24] wire out_rimask_1128 = |_out_rimask_T_1128; // @[RegisterRouter.scala:87:24] wire out_wimask_1128 = &_out_wimask_T_1128; // @[RegisterRouter.scala:87:24] wire out_romask_1128 = |_out_romask_T_1128; // @[RegisterRouter.scala:87:24] wire out_womask_1128 = &_out_womask_T_1128; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1128 = out_rivalid_1_982 & out_rimask_1128; // @[RegisterRouter.scala:87:24] wire _out_T_10899 = out_f_rivalid_1128; // @[RegisterRouter.scala:87:24] wire out_f_roready_1128 = out_roready_1_982 & out_romask_1128; // @[RegisterRouter.scala:87:24] wire _out_T_10900 = out_f_roready_1128; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1128 = out_wivalid_1_982 & out_wimask_1128; // @[RegisterRouter.scala:87:24] wire _out_T_10901 = out_f_wivalid_1128; // @[RegisterRouter.scala:87:24] wire out_f_woready_1128 = out_woready_1_982 & out_womask_1128; // @[RegisterRouter.scala:87:24] wire _out_T_10902 = out_f_woready_1128; // @[RegisterRouter.scala:87:24] wire _out_T_10903 = ~out_rimask_1128; // @[RegisterRouter.scala:87:24] wire _out_T_10904 = ~out_wimask_1128; // @[RegisterRouter.scala:87:24] wire _out_T_10905 = ~out_romask_1128; // @[RegisterRouter.scala:87:24] wire _out_T_10906 = ~out_womask_1128; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_967 = {abstractDataMem_19, _out_prepend_T_967}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10907 = out_prepend_967; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10908 = _out_T_10907; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_968 = _out_T_10908; // @[RegisterRouter.scala:87:24] wire out_rimask_1129 = |_out_rimask_T_1129; // @[RegisterRouter.scala:87:24] wire out_wimask_1129 = &_out_wimask_T_1129; // @[RegisterRouter.scala:87:24] wire out_romask_1129 = |_out_romask_T_1129; // @[RegisterRouter.scala:87:24] wire out_womask_1129 = &_out_womask_T_1129; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1129 = out_rivalid_1_983 & out_rimask_1129; // @[RegisterRouter.scala:87:24] wire _out_T_10910 = out_f_rivalid_1129; // @[RegisterRouter.scala:87:24] wire out_f_roready_1129 = out_roready_1_983 & out_romask_1129; // @[RegisterRouter.scala:87:24] wire _out_T_10911 = out_f_roready_1129; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1129 = out_wivalid_1_983 & out_wimask_1129; // @[RegisterRouter.scala:87:24] wire _out_T_10912 = out_f_wivalid_1129; // @[RegisterRouter.scala:87:24] wire out_f_woready_1129 = out_woready_1_983 & out_womask_1129; // @[RegisterRouter.scala:87:24] wire _out_T_10913 = out_f_woready_1129; // @[RegisterRouter.scala:87:24] wire _out_T_10914 = ~out_rimask_1129; // @[RegisterRouter.scala:87:24] wire _out_T_10915 = ~out_wimask_1129; // @[RegisterRouter.scala:87:24] wire _out_T_10916 = ~out_romask_1129; // @[RegisterRouter.scala:87:24] wire _out_T_10917 = ~out_womask_1129; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_968 = {abstractDataMem_20, _out_prepend_T_968}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10918 = out_prepend_968; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10919 = _out_T_10918; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_969 = _out_T_10919; // @[RegisterRouter.scala:87:24] wire out_rimask_1130 = |_out_rimask_T_1130; // @[RegisterRouter.scala:87:24] wire out_wimask_1130 = &_out_wimask_T_1130; // @[RegisterRouter.scala:87:24] wire out_romask_1130 = |_out_romask_T_1130; // @[RegisterRouter.scala:87:24] wire out_womask_1130 = &_out_womask_T_1130; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1130 = out_rivalid_1_984 & out_rimask_1130; // @[RegisterRouter.scala:87:24] wire _out_T_10921 = out_f_rivalid_1130; // @[RegisterRouter.scala:87:24] wire out_f_roready_1130 = out_roready_1_984 & out_romask_1130; // @[RegisterRouter.scala:87:24] wire _out_T_10922 = out_f_roready_1130; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1130 = out_wivalid_1_984 & out_wimask_1130; // @[RegisterRouter.scala:87:24] wire _out_T_10923 = out_f_wivalid_1130; // @[RegisterRouter.scala:87:24] wire out_f_woready_1130 = out_woready_1_984 & out_womask_1130; // @[RegisterRouter.scala:87:24] wire _out_T_10924 = out_f_woready_1130; // @[RegisterRouter.scala:87:24] wire _out_T_10925 = ~out_rimask_1130; // @[RegisterRouter.scala:87:24] wire _out_T_10926 = ~out_wimask_1130; // @[RegisterRouter.scala:87:24] wire _out_T_10927 = ~out_romask_1130; // @[RegisterRouter.scala:87:24] wire _out_T_10928 = ~out_womask_1130; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_969 = {abstractDataMem_21, _out_prepend_T_969}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10929 = out_prepend_969; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10930 = _out_T_10929; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_970 = _out_T_10930; // @[RegisterRouter.scala:87:24] wire out_rimask_1131 = |_out_rimask_T_1131; // @[RegisterRouter.scala:87:24] wire out_wimask_1131 = &_out_wimask_T_1131; // @[RegisterRouter.scala:87:24] wire out_romask_1131 = |_out_romask_T_1131; // @[RegisterRouter.scala:87:24] wire out_womask_1131 = &_out_womask_T_1131; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1131 = out_rivalid_1_985 & out_rimask_1131; // @[RegisterRouter.scala:87:24] wire _out_T_10932 = out_f_rivalid_1131; // @[RegisterRouter.scala:87:24] wire out_f_roready_1131 = out_roready_1_985 & out_romask_1131; // @[RegisterRouter.scala:87:24] wire _out_T_10933 = out_f_roready_1131; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1131 = out_wivalid_1_985 & out_wimask_1131; // @[RegisterRouter.scala:87:24] wire _out_T_10934 = out_f_wivalid_1131; // @[RegisterRouter.scala:87:24] wire out_f_woready_1131 = out_woready_1_985 & out_womask_1131; // @[RegisterRouter.scala:87:24] wire _out_T_10935 = out_f_woready_1131; // @[RegisterRouter.scala:87:24] wire _out_T_10936 = ~out_rimask_1131; // @[RegisterRouter.scala:87:24] wire _out_T_10937 = ~out_wimask_1131; // @[RegisterRouter.scala:87:24] wire _out_T_10938 = ~out_romask_1131; // @[RegisterRouter.scala:87:24] wire _out_T_10939 = ~out_womask_1131; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_970 = {abstractDataMem_22, _out_prepend_T_970}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10940 = out_prepend_970; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10941 = _out_T_10940; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_971 = _out_T_10941; // @[RegisterRouter.scala:87:24] wire out_rimask_1132 = |_out_rimask_T_1132; // @[RegisterRouter.scala:87:24] wire out_wimask_1132 = &_out_wimask_T_1132; // @[RegisterRouter.scala:87:24] wire out_romask_1132 = |_out_romask_T_1132; // @[RegisterRouter.scala:87:24] wire out_womask_1132 = &_out_womask_T_1132; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1132 = out_rivalid_1_986 & out_rimask_1132; // @[RegisterRouter.scala:87:24] wire _out_T_10943 = out_f_rivalid_1132; // @[RegisterRouter.scala:87:24] wire out_f_roready_1132 = out_roready_1_986 & out_romask_1132; // @[RegisterRouter.scala:87:24] wire _out_T_10944 = out_f_roready_1132; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1132 = out_wivalid_1_986 & out_wimask_1132; // @[RegisterRouter.scala:87:24] wire _out_T_10945 = out_f_wivalid_1132; // @[RegisterRouter.scala:87:24] wire out_f_woready_1132 = out_woready_1_986 & out_womask_1132; // @[RegisterRouter.scala:87:24] wire _out_T_10946 = out_f_woready_1132; // @[RegisterRouter.scala:87:24] wire _out_T_10947 = ~out_rimask_1132; // @[RegisterRouter.scala:87:24] wire _out_T_10948 = ~out_wimask_1132; // @[RegisterRouter.scala:87:24] wire _out_T_10949 = ~out_romask_1132; // @[RegisterRouter.scala:87:24] wire _out_T_10950 = ~out_womask_1132; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_971 = {abstractDataMem_23, _out_prepend_T_971}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10951 = out_prepend_971; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10952 = _out_T_10951; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_114 = _out_T_10952; // @[MuxLiteral.scala:49:48] wire out_rimask_1133 = |_out_rimask_T_1133; // @[RegisterRouter.scala:87:24] wire out_wimask_1133 = &_out_wimask_T_1133; // @[RegisterRouter.scala:87:24] wire out_romask_1133 = |_out_romask_T_1133; // @[RegisterRouter.scala:87:24] wire out_womask_1133 = &_out_womask_T_1133; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1133 = out_rivalid_1_987 & out_rimask_1133; // @[RegisterRouter.scala:87:24] wire _out_T_10954 = out_f_rivalid_1133; // @[RegisterRouter.scala:87:24] wire out_f_roready_1133 = out_roready_1_987 & out_romask_1133; // @[RegisterRouter.scala:87:24] wire _out_T_10955 = out_f_roready_1133; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1133 = out_wivalid_1_987 & out_wimask_1133; // @[RegisterRouter.scala:87:24] wire out_f_woready_1133 = out_woready_1_987 & out_womask_1133; // @[RegisterRouter.scala:87:24] wire _out_T_10956 = ~out_rimask_1133; // @[RegisterRouter.scala:87:24] wire _out_T_10957 = ~out_wimask_1133; // @[RegisterRouter.scala:87:24] wire _out_T_10958 = ~out_romask_1133; // @[RegisterRouter.scala:87:24] wire _out_T_10959 = ~out_womask_1133; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10961 = _out_T_10960; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_972 = _out_T_10961; // @[RegisterRouter.scala:87:24] wire out_rimask_1134 = |_out_rimask_T_1134; // @[RegisterRouter.scala:87:24] wire out_wimask_1134 = &_out_wimask_T_1134; // @[RegisterRouter.scala:87:24] wire out_romask_1134 = |_out_romask_T_1134; // @[RegisterRouter.scala:87:24] wire out_womask_1134 = &_out_womask_T_1134; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1134 = out_rivalid_1_988 & out_rimask_1134; // @[RegisterRouter.scala:87:24] wire _out_T_10963 = out_f_rivalid_1134; // @[RegisterRouter.scala:87:24] wire out_f_roready_1134 = out_roready_1_988 & out_romask_1134; // @[RegisterRouter.scala:87:24] wire _out_T_10964 = out_f_roready_1134; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1134 = out_wivalid_1_988 & out_wimask_1134; // @[RegisterRouter.scala:87:24] wire out_f_woready_1134 = out_woready_1_988 & out_womask_1134; // @[RegisterRouter.scala:87:24] wire _out_T_10965 = ~out_rimask_1134; // @[RegisterRouter.scala:87:24] wire _out_T_10966 = ~out_wimask_1134; // @[RegisterRouter.scala:87:24] wire _out_T_10967 = ~out_romask_1134; // @[RegisterRouter.scala:87:24] wire _out_T_10968 = ~out_womask_1134; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_972 = {hi_346, flags_0_go, _out_prepend_T_972}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10969 = out_prepend_972; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10970 = _out_T_10969; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_973 = _out_T_10970; // @[RegisterRouter.scala:87:24] wire out_rimask_1135 = |_out_rimask_T_1135; // @[RegisterRouter.scala:87:24] wire out_wimask_1135 = &_out_wimask_T_1135; // @[RegisterRouter.scala:87:24] wire out_romask_1135 = |_out_romask_T_1135; // @[RegisterRouter.scala:87:24] wire out_womask_1135 = &_out_womask_T_1135; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1135 = out_rivalid_1_989 & out_rimask_1135; // @[RegisterRouter.scala:87:24] wire _out_T_10972 = out_f_rivalid_1135; // @[RegisterRouter.scala:87:24] wire out_f_roready_1135 = out_roready_1_989 & out_romask_1135; // @[RegisterRouter.scala:87:24] wire _out_T_10973 = out_f_roready_1135; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1135 = out_wivalid_1_989 & out_wimask_1135; // @[RegisterRouter.scala:87:24] wire out_f_woready_1135 = out_woready_1_989 & out_womask_1135; // @[RegisterRouter.scala:87:24] wire _out_T_10974 = ~out_rimask_1135; // @[RegisterRouter.scala:87:24] wire _out_T_10975 = ~out_wimask_1135; // @[RegisterRouter.scala:87:24] wire _out_T_10976 = ~out_romask_1135; // @[RegisterRouter.scala:87:24] wire _out_T_10977 = ~out_womask_1135; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_973 = {hi_347, flags_0_go, _out_prepend_T_973}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10978 = out_prepend_973; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10979 = _out_T_10978; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_974 = _out_T_10979; // @[RegisterRouter.scala:87:24] wire out_rimask_1136 = |_out_rimask_T_1136; // @[RegisterRouter.scala:87:24] wire out_wimask_1136 = &_out_wimask_T_1136; // @[RegisterRouter.scala:87:24] wire out_romask_1136 = |_out_romask_T_1136; // @[RegisterRouter.scala:87:24] wire out_womask_1136 = &_out_womask_T_1136; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1136 = out_rivalid_1_990 & out_rimask_1136; // @[RegisterRouter.scala:87:24] wire _out_T_10981 = out_f_rivalid_1136; // @[RegisterRouter.scala:87:24] wire out_f_roready_1136 = out_roready_1_990 & out_romask_1136; // @[RegisterRouter.scala:87:24] wire _out_T_10982 = out_f_roready_1136; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1136 = out_wivalid_1_990 & out_wimask_1136; // @[RegisterRouter.scala:87:24] wire out_f_woready_1136 = out_woready_1_990 & out_womask_1136; // @[RegisterRouter.scala:87:24] wire _out_T_10983 = ~out_rimask_1136; // @[RegisterRouter.scala:87:24] wire _out_T_10984 = ~out_wimask_1136; // @[RegisterRouter.scala:87:24] wire _out_T_10985 = ~out_romask_1136; // @[RegisterRouter.scala:87:24] wire _out_T_10986 = ~out_womask_1136; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_974 = {hi_348, flags_0_go, _out_prepend_T_974}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10987 = out_prepend_974; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10988 = _out_T_10987; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_975 = _out_T_10988; // @[RegisterRouter.scala:87:24] wire out_rimask_1137 = |_out_rimask_T_1137; // @[RegisterRouter.scala:87:24] wire out_wimask_1137 = &_out_wimask_T_1137; // @[RegisterRouter.scala:87:24] wire out_romask_1137 = |_out_romask_T_1137; // @[RegisterRouter.scala:87:24] wire out_womask_1137 = &_out_womask_T_1137; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1137 = out_rivalid_1_991 & out_rimask_1137; // @[RegisterRouter.scala:87:24] wire _out_T_10990 = out_f_rivalid_1137; // @[RegisterRouter.scala:87:24] wire out_f_roready_1137 = out_roready_1_991 & out_romask_1137; // @[RegisterRouter.scala:87:24] wire _out_T_10991 = out_f_roready_1137; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1137 = out_wivalid_1_991 & out_wimask_1137; // @[RegisterRouter.scala:87:24] wire out_f_woready_1137 = out_woready_1_991 & out_womask_1137; // @[RegisterRouter.scala:87:24] wire _out_T_10992 = ~out_rimask_1137; // @[RegisterRouter.scala:87:24] wire _out_T_10993 = ~out_wimask_1137; // @[RegisterRouter.scala:87:24] wire _out_T_10994 = ~out_romask_1137; // @[RegisterRouter.scala:87:24] wire _out_T_10995 = ~out_womask_1137; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_975 = {hi_349, flags_0_go, _out_prepend_T_975}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10996 = out_prepend_975; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10997 = _out_T_10996; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_976 = _out_T_10997; // @[RegisterRouter.scala:87:24] wire out_rimask_1138 = |_out_rimask_T_1138; // @[RegisterRouter.scala:87:24] wire out_wimask_1138 = &_out_wimask_T_1138; // @[RegisterRouter.scala:87:24] wire out_romask_1138 = |_out_romask_T_1138; // @[RegisterRouter.scala:87:24] wire out_womask_1138 = &_out_womask_T_1138; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1138 = out_rivalid_1_992 & out_rimask_1138; // @[RegisterRouter.scala:87:24] wire _out_T_10999 = out_f_rivalid_1138; // @[RegisterRouter.scala:87:24] wire out_f_roready_1138 = out_roready_1_992 & out_romask_1138; // @[RegisterRouter.scala:87:24] wire _out_T_11000 = out_f_roready_1138; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1138 = out_wivalid_1_992 & out_wimask_1138; // @[RegisterRouter.scala:87:24] wire out_f_woready_1138 = out_woready_1_992 & out_womask_1138; // @[RegisterRouter.scala:87:24] wire _out_T_11001 = ~out_rimask_1138; // @[RegisterRouter.scala:87:24] wire _out_T_11002 = ~out_wimask_1138; // @[RegisterRouter.scala:87:24] wire _out_T_11003 = ~out_romask_1138; // @[RegisterRouter.scala:87:24] wire _out_T_11004 = ~out_womask_1138; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_976 = {hi_350, flags_0_go, _out_prepend_T_976}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11005 = out_prepend_976; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11006 = _out_T_11005; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_977 = _out_T_11006; // @[RegisterRouter.scala:87:24] wire out_rimask_1139 = |_out_rimask_T_1139; // @[RegisterRouter.scala:87:24] wire out_wimask_1139 = &_out_wimask_T_1139; // @[RegisterRouter.scala:87:24] wire out_romask_1139 = |_out_romask_T_1139; // @[RegisterRouter.scala:87:24] wire out_womask_1139 = &_out_womask_T_1139; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1139 = out_rivalid_1_993 & out_rimask_1139; // @[RegisterRouter.scala:87:24] wire _out_T_11008 = out_f_rivalid_1139; // @[RegisterRouter.scala:87:24] wire out_f_roready_1139 = out_roready_1_993 & out_romask_1139; // @[RegisterRouter.scala:87:24] wire _out_T_11009 = out_f_roready_1139; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1139 = out_wivalid_1_993 & out_wimask_1139; // @[RegisterRouter.scala:87:24] wire out_f_woready_1139 = out_woready_1_993 & out_womask_1139; // @[RegisterRouter.scala:87:24] wire _out_T_11010 = ~out_rimask_1139; // @[RegisterRouter.scala:87:24] wire _out_T_11011 = ~out_wimask_1139; // @[RegisterRouter.scala:87:24] wire _out_T_11012 = ~out_romask_1139; // @[RegisterRouter.scala:87:24] wire _out_T_11013 = ~out_womask_1139; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_977 = {hi_351, flags_0_go, _out_prepend_T_977}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11014 = out_prepend_977; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11015 = _out_T_11014; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_978 = _out_T_11015; // @[RegisterRouter.scala:87:24] wire out_rimask_1140 = |_out_rimask_T_1140; // @[RegisterRouter.scala:87:24] wire out_wimask_1140 = &_out_wimask_T_1140; // @[RegisterRouter.scala:87:24] wire out_romask_1140 = |_out_romask_T_1140; // @[RegisterRouter.scala:87:24] wire out_womask_1140 = &_out_womask_T_1140; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1140 = out_rivalid_1_994 & out_rimask_1140; // @[RegisterRouter.scala:87:24] wire _out_T_11017 = out_f_rivalid_1140; // @[RegisterRouter.scala:87:24] wire out_f_roready_1140 = out_roready_1_994 & out_romask_1140; // @[RegisterRouter.scala:87:24] wire _out_T_11018 = out_f_roready_1140; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1140 = out_wivalid_1_994 & out_wimask_1140; // @[RegisterRouter.scala:87:24] wire out_f_woready_1140 = out_woready_1_994 & out_womask_1140; // @[RegisterRouter.scala:87:24] wire _out_T_11019 = ~out_rimask_1140; // @[RegisterRouter.scala:87:24] wire _out_T_11020 = ~out_wimask_1140; // @[RegisterRouter.scala:87:24] wire _out_T_11021 = ~out_romask_1140; // @[RegisterRouter.scala:87:24] wire _out_T_11022 = ~out_womask_1140; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_978 = {hi_352, flags_0_go, _out_prepend_T_978}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11023 = out_prepend_978; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11024 = _out_T_11023; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_171 = _out_T_11024; // @[MuxLiteral.scala:49:48] wire out_rimask_1141 = |_out_rimask_T_1141; // @[RegisterRouter.scala:87:24] wire out_wimask_1141 = &_out_wimask_T_1141; // @[RegisterRouter.scala:87:24] wire out_romask_1141 = |_out_romask_T_1141; // @[RegisterRouter.scala:87:24] wire out_womask_1141 = &_out_womask_T_1141; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1141 = out_rivalid_1_995 & out_rimask_1141; // @[RegisterRouter.scala:87:24] wire _out_T_11026 = out_f_rivalid_1141; // @[RegisterRouter.scala:87:24] wire out_f_roready_1141 = out_roready_1_995 & out_romask_1141; // @[RegisterRouter.scala:87:24] wire _out_T_11027 = out_f_roready_1141; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1141 = out_wivalid_1_995 & out_wimask_1141; // @[RegisterRouter.scala:87:24] wire out_f_woready_1141 = out_woready_1_995 & out_womask_1141; // @[RegisterRouter.scala:87:24] wire _out_T_11028 = ~out_rimask_1141; // @[RegisterRouter.scala:87:24] wire _out_T_11029 = ~out_wimask_1141; // @[RegisterRouter.scala:87:24] wire _out_T_11030 = ~out_romask_1141; // @[RegisterRouter.scala:87:24] wire _out_T_11031 = ~out_womask_1141; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11033 = _out_T_11032; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_979 = _out_T_11033; // @[RegisterRouter.scala:87:24] wire out_rimask_1142 = |_out_rimask_T_1142; // @[RegisterRouter.scala:87:24] wire out_wimask_1142 = &_out_wimask_T_1142; // @[RegisterRouter.scala:87:24] wire out_romask_1142 = |_out_romask_T_1142; // @[RegisterRouter.scala:87:24] wire out_womask_1142 = &_out_womask_T_1142; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1142 = out_rivalid_1_996 & out_rimask_1142; // @[RegisterRouter.scala:87:24] wire _out_T_11035 = out_f_rivalid_1142; // @[RegisterRouter.scala:87:24] wire out_f_roready_1142 = out_roready_1_996 & out_romask_1142; // @[RegisterRouter.scala:87:24] wire _out_T_11036 = out_f_roready_1142; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1142 = out_wivalid_1_996 & out_wimask_1142; // @[RegisterRouter.scala:87:24] wire out_f_woready_1142 = out_woready_1_996 & out_womask_1142; // @[RegisterRouter.scala:87:24] wire _out_T_11037 = ~out_rimask_1142; // @[RegisterRouter.scala:87:24] wire _out_T_11038 = ~out_wimask_1142; // @[RegisterRouter.scala:87:24] wire _out_T_11039 = ~out_romask_1142; // @[RegisterRouter.scala:87:24] wire _out_T_11040 = ~out_womask_1142; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_979 = {hi_90, flags_0_go, _out_prepend_T_979}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11041 = out_prepend_979; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11042 = _out_T_11041; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_980 = _out_T_11042; // @[RegisterRouter.scala:87:24] wire out_rimask_1143 = |_out_rimask_T_1143; // @[RegisterRouter.scala:87:24] wire out_wimask_1143 = &_out_wimask_T_1143; // @[RegisterRouter.scala:87:24] wire out_romask_1143 = |_out_romask_T_1143; // @[RegisterRouter.scala:87:24] wire out_womask_1143 = &_out_womask_T_1143; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1143 = out_rivalid_1_997 & out_rimask_1143; // @[RegisterRouter.scala:87:24] wire _out_T_11044 = out_f_rivalid_1143; // @[RegisterRouter.scala:87:24] wire out_f_roready_1143 = out_roready_1_997 & out_romask_1143; // @[RegisterRouter.scala:87:24] wire _out_T_11045 = out_f_roready_1143; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1143 = out_wivalid_1_997 & out_wimask_1143; // @[RegisterRouter.scala:87:24] wire out_f_woready_1143 = out_woready_1_997 & out_womask_1143; // @[RegisterRouter.scala:87:24] wire _out_T_11046 = ~out_rimask_1143; // @[RegisterRouter.scala:87:24] wire _out_T_11047 = ~out_wimask_1143; // @[RegisterRouter.scala:87:24] wire _out_T_11048 = ~out_romask_1143; // @[RegisterRouter.scala:87:24] wire _out_T_11049 = ~out_womask_1143; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_980 = {hi_91, flags_0_go, _out_prepend_T_980}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11050 = out_prepend_980; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11051 = _out_T_11050; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_981 = _out_T_11051; // @[RegisterRouter.scala:87:24] wire out_rimask_1144 = |_out_rimask_T_1144; // @[RegisterRouter.scala:87:24] wire out_wimask_1144 = &_out_wimask_T_1144; // @[RegisterRouter.scala:87:24] wire out_romask_1144 = |_out_romask_T_1144; // @[RegisterRouter.scala:87:24] wire out_womask_1144 = &_out_womask_T_1144; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1144 = out_rivalid_1_998 & out_rimask_1144; // @[RegisterRouter.scala:87:24] wire _out_T_11053 = out_f_rivalid_1144; // @[RegisterRouter.scala:87:24] wire out_f_roready_1144 = out_roready_1_998 & out_romask_1144; // @[RegisterRouter.scala:87:24] wire _out_T_11054 = out_f_roready_1144; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1144 = out_wivalid_1_998 & out_wimask_1144; // @[RegisterRouter.scala:87:24] wire out_f_woready_1144 = out_woready_1_998 & out_womask_1144; // @[RegisterRouter.scala:87:24] wire _out_T_11055 = ~out_rimask_1144; // @[RegisterRouter.scala:87:24] wire _out_T_11056 = ~out_wimask_1144; // @[RegisterRouter.scala:87:24] wire _out_T_11057 = ~out_romask_1144; // @[RegisterRouter.scala:87:24] wire _out_T_11058 = ~out_womask_1144; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_981 = {hi_92, flags_0_go, _out_prepend_T_981}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11059 = out_prepend_981; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11060 = _out_T_11059; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_982 = _out_T_11060; // @[RegisterRouter.scala:87:24] wire out_rimask_1145 = |_out_rimask_T_1145; // @[RegisterRouter.scala:87:24] wire out_wimask_1145 = &_out_wimask_T_1145; // @[RegisterRouter.scala:87:24] wire out_romask_1145 = |_out_romask_T_1145; // @[RegisterRouter.scala:87:24] wire out_womask_1145 = &_out_womask_T_1145; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1145 = out_rivalid_1_999 & out_rimask_1145; // @[RegisterRouter.scala:87:24] wire _out_T_11062 = out_f_rivalid_1145; // @[RegisterRouter.scala:87:24] wire out_f_roready_1145 = out_roready_1_999 & out_romask_1145; // @[RegisterRouter.scala:87:24] wire _out_T_11063 = out_f_roready_1145; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1145 = out_wivalid_1_999 & out_wimask_1145; // @[RegisterRouter.scala:87:24] wire out_f_woready_1145 = out_woready_1_999 & out_womask_1145; // @[RegisterRouter.scala:87:24] wire _out_T_11064 = ~out_rimask_1145; // @[RegisterRouter.scala:87:24] wire _out_T_11065 = ~out_wimask_1145; // @[RegisterRouter.scala:87:24] wire _out_T_11066 = ~out_romask_1145; // @[RegisterRouter.scala:87:24] wire _out_T_11067 = ~out_womask_1145; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_982 = {hi_93, flags_0_go, _out_prepend_T_982}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11068 = out_prepend_982; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11069 = _out_T_11068; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_983 = _out_T_11069; // @[RegisterRouter.scala:87:24] wire out_rimask_1146 = |_out_rimask_T_1146; // @[RegisterRouter.scala:87:24] wire out_wimask_1146 = &_out_wimask_T_1146; // @[RegisterRouter.scala:87:24] wire out_romask_1146 = |_out_romask_T_1146; // @[RegisterRouter.scala:87:24] wire out_womask_1146 = &_out_womask_T_1146; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1146 = out_rivalid_1_1000 & out_rimask_1146; // @[RegisterRouter.scala:87:24] wire _out_T_11071 = out_f_rivalid_1146; // @[RegisterRouter.scala:87:24] wire out_f_roready_1146 = out_roready_1_1000 & out_romask_1146; // @[RegisterRouter.scala:87:24] wire _out_T_11072 = out_f_roready_1146; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1146 = out_wivalid_1_1000 & out_wimask_1146; // @[RegisterRouter.scala:87:24] wire out_f_woready_1146 = out_woready_1_1000 & out_womask_1146; // @[RegisterRouter.scala:87:24] wire _out_T_11073 = ~out_rimask_1146; // @[RegisterRouter.scala:87:24] wire _out_T_11074 = ~out_wimask_1146; // @[RegisterRouter.scala:87:24] wire _out_T_11075 = ~out_romask_1146; // @[RegisterRouter.scala:87:24] wire _out_T_11076 = ~out_womask_1146; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_983 = {hi_94, flags_0_go, _out_prepend_T_983}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11077 = out_prepend_983; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11078 = _out_T_11077; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_984 = _out_T_11078; // @[RegisterRouter.scala:87:24] wire out_rimask_1147 = |_out_rimask_T_1147; // @[RegisterRouter.scala:87:24] wire out_wimask_1147 = &_out_wimask_T_1147; // @[RegisterRouter.scala:87:24] wire out_romask_1147 = |_out_romask_T_1147; // @[RegisterRouter.scala:87:24] wire out_womask_1147 = &_out_womask_T_1147; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1147 = out_rivalid_1_1001 & out_rimask_1147; // @[RegisterRouter.scala:87:24] wire _out_T_11080 = out_f_rivalid_1147; // @[RegisterRouter.scala:87:24] wire out_f_roready_1147 = out_roready_1_1001 & out_romask_1147; // @[RegisterRouter.scala:87:24] wire _out_T_11081 = out_f_roready_1147; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1147 = out_wivalid_1_1001 & out_wimask_1147; // @[RegisterRouter.scala:87:24] wire out_f_woready_1147 = out_woready_1_1001 & out_womask_1147; // @[RegisterRouter.scala:87:24] wire _out_T_11082 = ~out_rimask_1147; // @[RegisterRouter.scala:87:24] wire _out_T_11083 = ~out_wimask_1147; // @[RegisterRouter.scala:87:24] wire _out_T_11084 = ~out_romask_1147; // @[RegisterRouter.scala:87:24] wire _out_T_11085 = ~out_womask_1147; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_984 = {hi_95, flags_0_go, _out_prepend_T_984}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11086 = out_prepend_984; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11087 = _out_T_11086; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_985 = _out_T_11087; // @[RegisterRouter.scala:87:24] wire out_rimask_1148 = |_out_rimask_T_1148; // @[RegisterRouter.scala:87:24] wire out_wimask_1148 = &_out_wimask_T_1148; // @[RegisterRouter.scala:87:24] wire out_romask_1148 = |_out_romask_T_1148; // @[RegisterRouter.scala:87:24] wire out_womask_1148 = &_out_womask_T_1148; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1148 = out_rivalid_1_1002 & out_rimask_1148; // @[RegisterRouter.scala:87:24] wire _out_T_11089 = out_f_rivalid_1148; // @[RegisterRouter.scala:87:24] wire out_f_roready_1148 = out_roready_1_1002 & out_romask_1148; // @[RegisterRouter.scala:87:24] wire _out_T_11090 = out_f_roready_1148; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1148 = out_wivalid_1_1002 & out_wimask_1148; // @[RegisterRouter.scala:87:24] wire out_f_woready_1148 = out_woready_1_1002 & out_womask_1148; // @[RegisterRouter.scala:87:24] wire _out_T_11091 = ~out_rimask_1148; // @[RegisterRouter.scala:87:24] wire _out_T_11092 = ~out_wimask_1148; // @[RegisterRouter.scala:87:24] wire _out_T_11093 = ~out_romask_1148; // @[RegisterRouter.scala:87:24] wire _out_T_11094 = ~out_womask_1148; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_985 = {hi_96, flags_0_go, _out_prepend_T_985}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11095 = out_prepend_985; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11096 = _out_T_11095; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_139 = _out_T_11096; // @[MuxLiteral.scala:49:48] wire out_rimask_1149 = |_out_rimask_T_1149; // @[RegisterRouter.scala:87:24] wire out_wimask_1149 = &_out_wimask_T_1149; // @[RegisterRouter.scala:87:24] wire out_romask_1149 = |_out_romask_T_1149; // @[RegisterRouter.scala:87:24] wire out_womask_1149 = &_out_womask_T_1149; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1149 = out_rivalid_1_1003 & out_rimask_1149; // @[RegisterRouter.scala:87:24] wire _out_T_11098 = out_f_rivalid_1149; // @[RegisterRouter.scala:87:24] wire out_f_roready_1149 = out_roready_1_1003 & out_romask_1149; // @[RegisterRouter.scala:87:24] wire _out_T_11099 = out_f_roready_1149; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1149 = out_wivalid_1_1003 & out_wimask_1149; // @[RegisterRouter.scala:87:24] wire out_f_woready_1149 = out_woready_1_1003 & out_womask_1149; // @[RegisterRouter.scala:87:24] wire _out_T_11100 = ~out_rimask_1149; // @[RegisterRouter.scala:87:24] wire _out_T_11101 = ~out_wimask_1149; // @[RegisterRouter.scala:87:24] wire _out_T_11102 = ~out_romask_1149; // @[RegisterRouter.scala:87:24] wire _out_T_11103 = ~out_womask_1149; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11105 = _out_T_11104; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_986 = _out_T_11105; // @[RegisterRouter.scala:87:24] wire out_rimask_1150 = |_out_rimask_T_1150; // @[RegisterRouter.scala:87:24] wire out_wimask_1150 = &_out_wimask_T_1150; // @[RegisterRouter.scala:87:24] wire out_romask_1150 = |_out_romask_T_1150; // @[RegisterRouter.scala:87:24] wire out_womask_1150 = &_out_womask_T_1150; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1150 = out_rivalid_1_1004 & out_rimask_1150; // @[RegisterRouter.scala:87:24] wire _out_T_11107 = out_f_rivalid_1150; // @[RegisterRouter.scala:87:24] wire out_f_roready_1150 = out_roready_1_1004 & out_romask_1150; // @[RegisterRouter.scala:87:24] wire _out_T_11108 = out_f_roready_1150; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1150 = out_wivalid_1_1004 & out_wimask_1150; // @[RegisterRouter.scala:87:24] wire out_f_woready_1150 = out_woready_1_1004 & out_womask_1150; // @[RegisterRouter.scala:87:24] wire _out_T_11109 = ~out_rimask_1150; // @[RegisterRouter.scala:87:24] wire _out_T_11110 = ~out_wimask_1150; // @[RegisterRouter.scala:87:24] wire _out_T_11111 = ~out_romask_1150; // @[RegisterRouter.scala:87:24] wire _out_T_11112 = ~out_womask_1150; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_986 = {hi_634, flags_0_go, _out_prepend_T_986}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11113 = out_prepend_986; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11114 = _out_T_11113; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_987 = _out_T_11114; // @[RegisterRouter.scala:87:24] wire out_rimask_1151 = |_out_rimask_T_1151; // @[RegisterRouter.scala:87:24] wire out_wimask_1151 = &_out_wimask_T_1151; // @[RegisterRouter.scala:87:24] wire out_romask_1151 = |_out_romask_T_1151; // @[RegisterRouter.scala:87:24] wire out_womask_1151 = &_out_womask_T_1151; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1151 = out_rivalid_1_1005 & out_rimask_1151; // @[RegisterRouter.scala:87:24] wire _out_T_11116 = out_f_rivalid_1151; // @[RegisterRouter.scala:87:24] wire out_f_roready_1151 = out_roready_1_1005 & out_romask_1151; // @[RegisterRouter.scala:87:24] wire _out_T_11117 = out_f_roready_1151; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1151 = out_wivalid_1_1005 & out_wimask_1151; // @[RegisterRouter.scala:87:24] wire out_f_woready_1151 = out_woready_1_1005 & out_womask_1151; // @[RegisterRouter.scala:87:24] wire _out_T_11118 = ~out_rimask_1151; // @[RegisterRouter.scala:87:24] wire _out_T_11119 = ~out_wimask_1151; // @[RegisterRouter.scala:87:24] wire _out_T_11120 = ~out_romask_1151; // @[RegisterRouter.scala:87:24] wire _out_T_11121 = ~out_womask_1151; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_987 = {hi_635, flags_0_go, _out_prepend_T_987}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11122 = out_prepend_987; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11123 = _out_T_11122; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_988 = _out_T_11123; // @[RegisterRouter.scala:87:24] wire out_rimask_1152 = |_out_rimask_T_1152; // @[RegisterRouter.scala:87:24] wire out_wimask_1152 = &_out_wimask_T_1152; // @[RegisterRouter.scala:87:24] wire out_romask_1152 = |_out_romask_T_1152; // @[RegisterRouter.scala:87:24] wire out_womask_1152 = &_out_womask_T_1152; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1152 = out_rivalid_1_1006 & out_rimask_1152; // @[RegisterRouter.scala:87:24] wire _out_T_11125 = out_f_rivalid_1152; // @[RegisterRouter.scala:87:24] wire out_f_roready_1152 = out_roready_1_1006 & out_romask_1152; // @[RegisterRouter.scala:87:24] wire _out_T_11126 = out_f_roready_1152; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1152 = out_wivalid_1_1006 & out_wimask_1152; // @[RegisterRouter.scala:87:24] wire out_f_woready_1152 = out_woready_1_1006 & out_womask_1152; // @[RegisterRouter.scala:87:24] wire _out_T_11127 = ~out_rimask_1152; // @[RegisterRouter.scala:87:24] wire _out_T_11128 = ~out_wimask_1152; // @[RegisterRouter.scala:87:24] wire _out_T_11129 = ~out_romask_1152; // @[RegisterRouter.scala:87:24] wire _out_T_11130 = ~out_womask_1152; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_988 = {hi_636, flags_0_go, _out_prepend_T_988}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11131 = out_prepend_988; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11132 = _out_T_11131; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_989 = _out_T_11132; // @[RegisterRouter.scala:87:24] wire out_rimask_1153 = |_out_rimask_T_1153; // @[RegisterRouter.scala:87:24] wire out_wimask_1153 = &_out_wimask_T_1153; // @[RegisterRouter.scala:87:24] wire out_romask_1153 = |_out_romask_T_1153; // @[RegisterRouter.scala:87:24] wire out_womask_1153 = &_out_womask_T_1153; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1153 = out_rivalid_1_1007 & out_rimask_1153; // @[RegisterRouter.scala:87:24] wire _out_T_11134 = out_f_rivalid_1153; // @[RegisterRouter.scala:87:24] wire out_f_roready_1153 = out_roready_1_1007 & out_romask_1153; // @[RegisterRouter.scala:87:24] wire _out_T_11135 = out_f_roready_1153; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1153 = out_wivalid_1_1007 & out_wimask_1153; // @[RegisterRouter.scala:87:24] wire out_f_woready_1153 = out_woready_1_1007 & out_womask_1153; // @[RegisterRouter.scala:87:24] wire _out_T_11136 = ~out_rimask_1153; // @[RegisterRouter.scala:87:24] wire _out_T_11137 = ~out_wimask_1153; // @[RegisterRouter.scala:87:24] wire _out_T_11138 = ~out_romask_1153; // @[RegisterRouter.scala:87:24] wire _out_T_11139 = ~out_womask_1153; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_989 = {hi_637, flags_0_go, _out_prepend_T_989}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11140 = out_prepend_989; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11141 = _out_T_11140; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_990 = _out_T_11141; // @[RegisterRouter.scala:87:24] wire out_rimask_1154 = |_out_rimask_T_1154; // @[RegisterRouter.scala:87:24] wire out_wimask_1154 = &_out_wimask_T_1154; // @[RegisterRouter.scala:87:24] wire out_romask_1154 = |_out_romask_T_1154; // @[RegisterRouter.scala:87:24] wire out_womask_1154 = &_out_womask_T_1154; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1154 = out_rivalid_1_1008 & out_rimask_1154; // @[RegisterRouter.scala:87:24] wire _out_T_11143 = out_f_rivalid_1154; // @[RegisterRouter.scala:87:24] wire out_f_roready_1154 = out_roready_1_1008 & out_romask_1154; // @[RegisterRouter.scala:87:24] wire _out_T_11144 = out_f_roready_1154; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1154 = out_wivalid_1_1008 & out_wimask_1154; // @[RegisterRouter.scala:87:24] wire out_f_woready_1154 = out_woready_1_1008 & out_womask_1154; // @[RegisterRouter.scala:87:24] wire _out_T_11145 = ~out_rimask_1154; // @[RegisterRouter.scala:87:24] wire _out_T_11146 = ~out_wimask_1154; // @[RegisterRouter.scala:87:24] wire _out_T_11147 = ~out_romask_1154; // @[RegisterRouter.scala:87:24] wire _out_T_11148 = ~out_womask_1154; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_990 = {hi_638, flags_0_go, _out_prepend_T_990}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11149 = out_prepend_990; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11150 = _out_T_11149; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_991 = _out_T_11150; // @[RegisterRouter.scala:87:24] wire out_rimask_1155 = |_out_rimask_T_1155; // @[RegisterRouter.scala:87:24] wire out_wimask_1155 = &_out_wimask_T_1155; // @[RegisterRouter.scala:87:24] wire out_romask_1155 = |_out_romask_T_1155; // @[RegisterRouter.scala:87:24] wire out_womask_1155 = &_out_womask_T_1155; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1155 = out_rivalid_1_1009 & out_rimask_1155; // @[RegisterRouter.scala:87:24] wire _out_T_11152 = out_f_rivalid_1155; // @[RegisterRouter.scala:87:24] wire out_f_roready_1155 = out_roready_1_1009 & out_romask_1155; // @[RegisterRouter.scala:87:24] wire _out_T_11153 = out_f_roready_1155; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1155 = out_wivalid_1_1009 & out_wimask_1155; // @[RegisterRouter.scala:87:24] wire out_f_woready_1155 = out_woready_1_1009 & out_womask_1155; // @[RegisterRouter.scala:87:24] wire _out_T_11154 = ~out_rimask_1155; // @[RegisterRouter.scala:87:24] wire _out_T_11155 = ~out_wimask_1155; // @[RegisterRouter.scala:87:24] wire _out_T_11156 = ~out_romask_1155; // @[RegisterRouter.scala:87:24] wire _out_T_11157 = ~out_womask_1155; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_991 = {hi_639, flags_0_go, _out_prepend_T_991}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11158 = out_prepend_991; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11159 = _out_T_11158; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_992 = _out_T_11159; // @[RegisterRouter.scala:87:24] wire out_rimask_1156 = |_out_rimask_T_1156; // @[RegisterRouter.scala:87:24] wire out_wimask_1156 = &_out_wimask_T_1156; // @[RegisterRouter.scala:87:24] wire out_romask_1156 = |_out_romask_T_1156; // @[RegisterRouter.scala:87:24] wire out_womask_1156 = &_out_womask_T_1156; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1156 = out_rivalid_1_1010 & out_rimask_1156; // @[RegisterRouter.scala:87:24] wire _out_T_11161 = out_f_rivalid_1156; // @[RegisterRouter.scala:87:24] wire out_f_roready_1156 = out_roready_1_1010 & out_romask_1156; // @[RegisterRouter.scala:87:24] wire _out_T_11162 = out_f_roready_1156; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1156 = out_wivalid_1_1010 & out_wimask_1156; // @[RegisterRouter.scala:87:24] wire out_f_woready_1156 = out_woready_1_1010 & out_womask_1156; // @[RegisterRouter.scala:87:24] wire _out_T_11163 = ~out_rimask_1156; // @[RegisterRouter.scala:87:24] wire _out_T_11164 = ~out_wimask_1156; // @[RegisterRouter.scala:87:24] wire _out_T_11165 = ~out_romask_1156; // @[RegisterRouter.scala:87:24] wire _out_T_11166 = ~out_womask_1156; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_992 = {hi_640, flags_0_go, _out_prepend_T_992}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11167 = out_prepend_992; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11168 = _out_T_11167; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_207 = _out_T_11168; // @[MuxLiteral.scala:49:48] wire out_rimask_1157 = |_out_rimask_T_1157; // @[RegisterRouter.scala:87:24] wire out_wimask_1157 = &_out_wimask_T_1157; // @[RegisterRouter.scala:87:24] wire out_romask_1157 = |_out_romask_T_1157; // @[RegisterRouter.scala:87:24] wire out_womask_1157 = &_out_womask_T_1157; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1157 = out_rivalid_1_1011 & out_rimask_1157; // @[RegisterRouter.scala:87:24] wire _out_T_11170 = out_f_rivalid_1157; // @[RegisterRouter.scala:87:24] wire out_f_roready_1157 = out_roready_1_1011 & out_romask_1157; // @[RegisterRouter.scala:87:24] wire _out_T_11171 = out_f_roready_1157; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1157 = out_wivalid_1_1011 & out_wimask_1157; // @[RegisterRouter.scala:87:24] wire out_f_woready_1157 = out_woready_1_1011 & out_womask_1157; // @[RegisterRouter.scala:87:24] wire _out_T_11172 = ~out_rimask_1157; // @[RegisterRouter.scala:87:24] wire _out_T_11173 = ~out_wimask_1157; // @[RegisterRouter.scala:87:24] wire _out_T_11174 = ~out_romask_1157; // @[RegisterRouter.scala:87:24] wire _out_T_11175 = ~out_womask_1157; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11177 = _out_T_11176; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_993 = _out_T_11177; // @[RegisterRouter.scala:87:24] wire out_rimask_1158 = |_out_rimask_T_1158; // @[RegisterRouter.scala:87:24] wire out_wimask_1158 = &_out_wimask_T_1158; // @[RegisterRouter.scala:87:24] wire out_romask_1158 = |_out_romask_T_1158; // @[RegisterRouter.scala:87:24] wire out_womask_1158 = &_out_womask_T_1158; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1158 = out_rivalid_1_1012 & out_rimask_1158; // @[RegisterRouter.scala:87:24] wire _out_T_11179 = out_f_rivalid_1158; // @[RegisterRouter.scala:87:24] wire out_f_roready_1158 = out_roready_1_1012 & out_romask_1158; // @[RegisterRouter.scala:87:24] wire _out_T_11180 = out_f_roready_1158; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1158 = out_wivalid_1_1012 & out_wimask_1158; // @[RegisterRouter.scala:87:24] wire out_f_woready_1158 = out_woready_1_1012 & out_womask_1158; // @[RegisterRouter.scala:87:24] wire _out_T_11181 = ~out_rimask_1158; // @[RegisterRouter.scala:87:24] wire _out_T_11182 = ~out_wimask_1158; // @[RegisterRouter.scala:87:24] wire _out_T_11183 = ~out_romask_1158; // @[RegisterRouter.scala:87:24] wire _out_T_11184 = ~out_womask_1158; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_993 = {hi_690, flags_0_go, _out_prepend_T_993}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11185 = out_prepend_993; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11186 = _out_T_11185; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_994 = _out_T_11186; // @[RegisterRouter.scala:87:24] wire out_rimask_1159 = |_out_rimask_T_1159; // @[RegisterRouter.scala:87:24] wire out_wimask_1159 = &_out_wimask_T_1159; // @[RegisterRouter.scala:87:24] wire out_romask_1159 = |_out_romask_T_1159; // @[RegisterRouter.scala:87:24] wire out_womask_1159 = &_out_womask_T_1159; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1159 = out_rivalid_1_1013 & out_rimask_1159; // @[RegisterRouter.scala:87:24] wire _out_T_11188 = out_f_rivalid_1159; // @[RegisterRouter.scala:87:24] wire out_f_roready_1159 = out_roready_1_1013 & out_romask_1159; // @[RegisterRouter.scala:87:24] wire _out_T_11189 = out_f_roready_1159; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1159 = out_wivalid_1_1013 & out_wimask_1159; // @[RegisterRouter.scala:87:24] wire out_f_woready_1159 = out_woready_1_1013 & out_womask_1159; // @[RegisterRouter.scala:87:24] wire _out_T_11190 = ~out_rimask_1159; // @[RegisterRouter.scala:87:24] wire _out_T_11191 = ~out_wimask_1159; // @[RegisterRouter.scala:87:24] wire _out_T_11192 = ~out_romask_1159; // @[RegisterRouter.scala:87:24] wire _out_T_11193 = ~out_womask_1159; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_994 = {hi_691, flags_0_go, _out_prepend_T_994}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11194 = out_prepend_994; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11195 = _out_T_11194; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_995 = _out_T_11195; // @[RegisterRouter.scala:87:24] wire out_rimask_1160 = |_out_rimask_T_1160; // @[RegisterRouter.scala:87:24] wire out_wimask_1160 = &_out_wimask_T_1160; // @[RegisterRouter.scala:87:24] wire out_romask_1160 = |_out_romask_T_1160; // @[RegisterRouter.scala:87:24] wire out_womask_1160 = &_out_womask_T_1160; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1160 = out_rivalid_1_1014 & out_rimask_1160; // @[RegisterRouter.scala:87:24] wire _out_T_11197 = out_f_rivalid_1160; // @[RegisterRouter.scala:87:24] wire out_f_roready_1160 = out_roready_1_1014 & out_romask_1160; // @[RegisterRouter.scala:87:24] wire _out_T_11198 = out_f_roready_1160; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1160 = out_wivalid_1_1014 & out_wimask_1160; // @[RegisterRouter.scala:87:24] wire out_f_woready_1160 = out_woready_1_1014 & out_womask_1160; // @[RegisterRouter.scala:87:24] wire _out_T_11199 = ~out_rimask_1160; // @[RegisterRouter.scala:87:24] wire _out_T_11200 = ~out_wimask_1160; // @[RegisterRouter.scala:87:24] wire _out_T_11201 = ~out_romask_1160; // @[RegisterRouter.scala:87:24] wire _out_T_11202 = ~out_womask_1160; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_995 = {hi_692, flags_0_go, _out_prepend_T_995}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11203 = out_prepend_995; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11204 = _out_T_11203; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_996 = _out_T_11204; // @[RegisterRouter.scala:87:24] wire out_rimask_1161 = |_out_rimask_T_1161; // @[RegisterRouter.scala:87:24] wire out_wimask_1161 = &_out_wimask_T_1161; // @[RegisterRouter.scala:87:24] wire out_romask_1161 = |_out_romask_T_1161; // @[RegisterRouter.scala:87:24] wire out_womask_1161 = &_out_womask_T_1161; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1161 = out_rivalid_1_1015 & out_rimask_1161; // @[RegisterRouter.scala:87:24] wire _out_T_11206 = out_f_rivalid_1161; // @[RegisterRouter.scala:87:24] wire out_f_roready_1161 = out_roready_1_1015 & out_romask_1161; // @[RegisterRouter.scala:87:24] wire _out_T_11207 = out_f_roready_1161; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1161 = out_wivalid_1_1015 & out_wimask_1161; // @[RegisterRouter.scala:87:24] wire out_f_woready_1161 = out_woready_1_1015 & out_womask_1161; // @[RegisterRouter.scala:87:24] wire _out_T_11208 = ~out_rimask_1161; // @[RegisterRouter.scala:87:24] wire _out_T_11209 = ~out_wimask_1161; // @[RegisterRouter.scala:87:24] wire _out_T_11210 = ~out_romask_1161; // @[RegisterRouter.scala:87:24] wire _out_T_11211 = ~out_womask_1161; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_996 = {hi_693, flags_0_go, _out_prepend_T_996}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11212 = out_prepend_996; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11213 = _out_T_11212; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_997 = _out_T_11213; // @[RegisterRouter.scala:87:24] wire out_rimask_1162 = |_out_rimask_T_1162; // @[RegisterRouter.scala:87:24] wire out_wimask_1162 = &_out_wimask_T_1162; // @[RegisterRouter.scala:87:24] wire out_romask_1162 = |_out_romask_T_1162; // @[RegisterRouter.scala:87:24] wire out_womask_1162 = &_out_womask_T_1162; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1162 = out_rivalid_1_1016 & out_rimask_1162; // @[RegisterRouter.scala:87:24] wire _out_T_11215 = out_f_rivalid_1162; // @[RegisterRouter.scala:87:24] wire out_f_roready_1162 = out_roready_1_1016 & out_romask_1162; // @[RegisterRouter.scala:87:24] wire _out_T_11216 = out_f_roready_1162; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1162 = out_wivalid_1_1016 & out_wimask_1162; // @[RegisterRouter.scala:87:24] wire out_f_woready_1162 = out_woready_1_1016 & out_womask_1162; // @[RegisterRouter.scala:87:24] wire _out_T_11217 = ~out_rimask_1162; // @[RegisterRouter.scala:87:24] wire _out_T_11218 = ~out_wimask_1162; // @[RegisterRouter.scala:87:24] wire _out_T_11219 = ~out_romask_1162; // @[RegisterRouter.scala:87:24] wire _out_T_11220 = ~out_womask_1162; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_997 = {hi_694, flags_0_go, _out_prepend_T_997}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11221 = out_prepend_997; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11222 = _out_T_11221; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_998 = _out_T_11222; // @[RegisterRouter.scala:87:24] wire out_rimask_1163 = |_out_rimask_T_1163; // @[RegisterRouter.scala:87:24] wire out_wimask_1163 = &_out_wimask_T_1163; // @[RegisterRouter.scala:87:24] wire out_romask_1163 = |_out_romask_T_1163; // @[RegisterRouter.scala:87:24] wire out_womask_1163 = &_out_womask_T_1163; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1163 = out_rivalid_1_1017 & out_rimask_1163; // @[RegisterRouter.scala:87:24] wire _out_T_11224 = out_f_rivalid_1163; // @[RegisterRouter.scala:87:24] wire out_f_roready_1163 = out_roready_1_1017 & out_romask_1163; // @[RegisterRouter.scala:87:24] wire _out_T_11225 = out_f_roready_1163; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1163 = out_wivalid_1_1017 & out_wimask_1163; // @[RegisterRouter.scala:87:24] wire out_f_woready_1163 = out_woready_1_1017 & out_womask_1163; // @[RegisterRouter.scala:87:24] wire _out_T_11226 = ~out_rimask_1163; // @[RegisterRouter.scala:87:24] wire _out_T_11227 = ~out_wimask_1163; // @[RegisterRouter.scala:87:24] wire _out_T_11228 = ~out_romask_1163; // @[RegisterRouter.scala:87:24] wire _out_T_11229 = ~out_womask_1163; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_998 = {hi_695, flags_0_go, _out_prepend_T_998}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11230 = out_prepend_998; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11231 = _out_T_11230; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_999 = _out_T_11231; // @[RegisterRouter.scala:87:24] wire out_rimask_1164 = |_out_rimask_T_1164; // @[RegisterRouter.scala:87:24] wire out_wimask_1164 = &_out_wimask_T_1164; // @[RegisterRouter.scala:87:24] wire out_romask_1164 = |_out_romask_T_1164; // @[RegisterRouter.scala:87:24] wire out_womask_1164 = &_out_womask_T_1164; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1164 = out_rivalid_1_1018 & out_rimask_1164; // @[RegisterRouter.scala:87:24] wire _out_T_11233 = out_f_rivalid_1164; // @[RegisterRouter.scala:87:24] wire out_f_roready_1164 = out_roready_1_1018 & out_romask_1164; // @[RegisterRouter.scala:87:24] wire _out_T_11234 = out_f_roready_1164; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1164 = out_wivalid_1_1018 & out_wimask_1164; // @[RegisterRouter.scala:87:24] wire out_f_woready_1164 = out_woready_1_1018 & out_womask_1164; // @[RegisterRouter.scala:87:24] wire _out_T_11235 = ~out_rimask_1164; // @[RegisterRouter.scala:87:24] wire _out_T_11236 = ~out_wimask_1164; // @[RegisterRouter.scala:87:24] wire _out_T_11237 = ~out_romask_1164; // @[RegisterRouter.scala:87:24] wire _out_T_11238 = ~out_womask_1164; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_999 = {hi_696, flags_0_go, _out_prepend_T_999}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11239 = out_prepend_999; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11240 = _out_T_11239; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_214 = _out_T_11240; // @[MuxLiteral.scala:49:48] wire out_rimask_1165 = |_out_rimask_T_1165; // @[RegisterRouter.scala:87:24] wire out_wimask_1165 = &_out_wimask_T_1165; // @[RegisterRouter.scala:87:24] wire out_romask_1165 = |_out_romask_T_1165; // @[RegisterRouter.scala:87:24] wire out_womask_1165 = &_out_womask_T_1165; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1165 = out_rivalid_1_1019 & out_rimask_1165; // @[RegisterRouter.scala:87:24] wire _out_T_11242 = out_f_rivalid_1165; // @[RegisterRouter.scala:87:24] wire out_f_roready_1165 = out_roready_1_1019 & out_romask_1165; // @[RegisterRouter.scala:87:24] wire _out_T_11243 = out_f_roready_1165; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1165 = out_wivalid_1_1019 & out_wimask_1165; // @[RegisterRouter.scala:87:24] wire out_f_woready_1165 = out_woready_1_1019 & out_womask_1165; // @[RegisterRouter.scala:87:24] wire _out_T_11244 = ~out_rimask_1165; // @[RegisterRouter.scala:87:24] wire _out_T_11245 = ~out_wimask_1165; // @[RegisterRouter.scala:87:24] wire _out_T_11246 = ~out_romask_1165; // @[RegisterRouter.scala:87:24] wire _out_T_11247 = ~out_womask_1165; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11249 = _out_T_11248; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1000 = _out_T_11249; // @[RegisterRouter.scala:87:24] wire out_rimask_1166 = |_out_rimask_T_1166; // @[RegisterRouter.scala:87:24] wire out_wimask_1166 = &_out_wimask_T_1166; // @[RegisterRouter.scala:87:24] wire out_romask_1166 = |_out_romask_T_1166; // @[RegisterRouter.scala:87:24] wire out_womask_1166 = &_out_womask_T_1166; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1166 = out_rivalid_1_1020 & out_rimask_1166; // @[RegisterRouter.scala:87:24] wire _out_T_11251 = out_f_rivalid_1166; // @[RegisterRouter.scala:87:24] wire out_f_roready_1166 = out_roready_1_1020 & out_romask_1166; // @[RegisterRouter.scala:87:24] wire _out_T_11252 = out_f_roready_1166; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1166 = out_wivalid_1_1020 & out_wimask_1166; // @[RegisterRouter.scala:87:24] wire out_f_woready_1166 = out_woready_1_1020 & out_womask_1166; // @[RegisterRouter.scala:87:24] wire _out_T_11253 = ~out_rimask_1166; // @[RegisterRouter.scala:87:24] wire _out_T_11254 = ~out_wimask_1166; // @[RegisterRouter.scala:87:24] wire _out_T_11255 = ~out_romask_1166; // @[RegisterRouter.scala:87:24] wire _out_T_11256 = ~out_womask_1166; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1000 = {hi_858, flags_0_go, _out_prepend_T_1000}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11257 = out_prepend_1000; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11258 = _out_T_11257; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1001 = _out_T_11258; // @[RegisterRouter.scala:87:24] wire out_rimask_1167 = |_out_rimask_T_1167; // @[RegisterRouter.scala:87:24] wire out_wimask_1167 = &_out_wimask_T_1167; // @[RegisterRouter.scala:87:24] wire out_romask_1167 = |_out_romask_T_1167; // @[RegisterRouter.scala:87:24] wire out_womask_1167 = &_out_womask_T_1167; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1167 = out_rivalid_1_1021 & out_rimask_1167; // @[RegisterRouter.scala:87:24] wire _out_T_11260 = out_f_rivalid_1167; // @[RegisterRouter.scala:87:24] wire out_f_roready_1167 = out_roready_1_1021 & out_romask_1167; // @[RegisterRouter.scala:87:24] wire _out_T_11261 = out_f_roready_1167; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1167 = out_wivalid_1_1021 & out_wimask_1167; // @[RegisterRouter.scala:87:24] wire out_f_woready_1167 = out_woready_1_1021 & out_womask_1167; // @[RegisterRouter.scala:87:24] wire _out_T_11262 = ~out_rimask_1167; // @[RegisterRouter.scala:87:24] wire _out_T_11263 = ~out_wimask_1167; // @[RegisterRouter.scala:87:24] wire _out_T_11264 = ~out_romask_1167; // @[RegisterRouter.scala:87:24] wire _out_T_11265 = ~out_womask_1167; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1001 = {hi_859, flags_0_go, _out_prepend_T_1001}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11266 = out_prepend_1001; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11267 = _out_T_11266; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1002 = _out_T_11267; // @[RegisterRouter.scala:87:24] wire out_rimask_1168 = |_out_rimask_T_1168; // @[RegisterRouter.scala:87:24] wire out_wimask_1168 = &_out_wimask_T_1168; // @[RegisterRouter.scala:87:24] wire out_romask_1168 = |_out_romask_T_1168; // @[RegisterRouter.scala:87:24] wire out_womask_1168 = &_out_womask_T_1168; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1168 = out_rivalid_1_1022 & out_rimask_1168; // @[RegisterRouter.scala:87:24] wire _out_T_11269 = out_f_rivalid_1168; // @[RegisterRouter.scala:87:24] wire out_f_roready_1168 = out_roready_1_1022 & out_romask_1168; // @[RegisterRouter.scala:87:24] wire _out_T_11270 = out_f_roready_1168; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1168 = out_wivalid_1_1022 & out_wimask_1168; // @[RegisterRouter.scala:87:24] wire out_f_woready_1168 = out_woready_1_1022 & out_womask_1168; // @[RegisterRouter.scala:87:24] wire _out_T_11271 = ~out_rimask_1168; // @[RegisterRouter.scala:87:24] wire _out_T_11272 = ~out_wimask_1168; // @[RegisterRouter.scala:87:24] wire _out_T_11273 = ~out_romask_1168; // @[RegisterRouter.scala:87:24] wire _out_T_11274 = ~out_womask_1168; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1002 = {hi_860, flags_0_go, _out_prepend_T_1002}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11275 = out_prepend_1002; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11276 = _out_T_11275; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1003 = _out_T_11276; // @[RegisterRouter.scala:87:24] wire out_rimask_1169 = |_out_rimask_T_1169; // @[RegisterRouter.scala:87:24] wire out_wimask_1169 = &_out_wimask_T_1169; // @[RegisterRouter.scala:87:24] wire out_romask_1169 = |_out_romask_T_1169; // @[RegisterRouter.scala:87:24] wire out_womask_1169 = &_out_womask_T_1169; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1169 = out_rivalid_1_1023 & out_rimask_1169; // @[RegisterRouter.scala:87:24] wire _out_T_11278 = out_f_rivalid_1169; // @[RegisterRouter.scala:87:24] wire out_f_roready_1169 = out_roready_1_1023 & out_romask_1169; // @[RegisterRouter.scala:87:24] wire _out_T_11279 = out_f_roready_1169; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1169 = out_wivalid_1_1023 & out_wimask_1169; // @[RegisterRouter.scala:87:24] wire out_f_woready_1169 = out_woready_1_1023 & out_womask_1169; // @[RegisterRouter.scala:87:24] wire _out_T_11280 = ~out_rimask_1169; // @[RegisterRouter.scala:87:24] wire _out_T_11281 = ~out_wimask_1169; // @[RegisterRouter.scala:87:24] wire _out_T_11282 = ~out_romask_1169; // @[RegisterRouter.scala:87:24] wire _out_T_11283 = ~out_womask_1169; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1003 = {hi_861, flags_0_go, _out_prepend_T_1003}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11284 = out_prepend_1003; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11285 = _out_T_11284; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1004 = _out_T_11285; // @[RegisterRouter.scala:87:24] wire out_rimask_1170 = |_out_rimask_T_1170; // @[RegisterRouter.scala:87:24] wire out_wimask_1170 = &_out_wimask_T_1170; // @[RegisterRouter.scala:87:24] wire out_romask_1170 = |_out_romask_T_1170; // @[RegisterRouter.scala:87:24] wire out_womask_1170 = &_out_womask_T_1170; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1170 = out_rivalid_1_1024 & out_rimask_1170; // @[RegisterRouter.scala:87:24] wire _out_T_11287 = out_f_rivalid_1170; // @[RegisterRouter.scala:87:24] wire out_f_roready_1170 = out_roready_1_1024 & out_romask_1170; // @[RegisterRouter.scala:87:24] wire _out_T_11288 = out_f_roready_1170; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1170 = out_wivalid_1_1024 & out_wimask_1170; // @[RegisterRouter.scala:87:24] wire out_f_woready_1170 = out_woready_1_1024 & out_womask_1170; // @[RegisterRouter.scala:87:24] wire _out_T_11289 = ~out_rimask_1170; // @[RegisterRouter.scala:87:24] wire _out_T_11290 = ~out_wimask_1170; // @[RegisterRouter.scala:87:24] wire _out_T_11291 = ~out_romask_1170; // @[RegisterRouter.scala:87:24] wire _out_T_11292 = ~out_womask_1170; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1004 = {hi_862, flags_0_go, _out_prepend_T_1004}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11293 = out_prepend_1004; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11294 = _out_T_11293; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1005 = _out_T_11294; // @[RegisterRouter.scala:87:24] wire out_rimask_1171 = |_out_rimask_T_1171; // @[RegisterRouter.scala:87:24] wire out_wimask_1171 = &_out_wimask_T_1171; // @[RegisterRouter.scala:87:24] wire out_romask_1171 = |_out_romask_T_1171; // @[RegisterRouter.scala:87:24] wire out_womask_1171 = &_out_womask_T_1171; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1171 = out_rivalid_1_1025 & out_rimask_1171; // @[RegisterRouter.scala:87:24] wire _out_T_11296 = out_f_rivalid_1171; // @[RegisterRouter.scala:87:24] wire out_f_roready_1171 = out_roready_1_1025 & out_romask_1171; // @[RegisterRouter.scala:87:24] wire _out_T_11297 = out_f_roready_1171; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1171 = out_wivalid_1_1025 & out_wimask_1171; // @[RegisterRouter.scala:87:24] wire out_f_woready_1171 = out_woready_1_1025 & out_womask_1171; // @[RegisterRouter.scala:87:24] wire _out_T_11298 = ~out_rimask_1171; // @[RegisterRouter.scala:87:24] wire _out_T_11299 = ~out_wimask_1171; // @[RegisterRouter.scala:87:24] wire _out_T_11300 = ~out_romask_1171; // @[RegisterRouter.scala:87:24] wire _out_T_11301 = ~out_womask_1171; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1005 = {hi_863, flags_0_go, _out_prepend_T_1005}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11302 = out_prepend_1005; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11303 = _out_T_11302; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1006 = _out_T_11303; // @[RegisterRouter.scala:87:24] wire out_rimask_1172 = |_out_rimask_T_1172; // @[RegisterRouter.scala:87:24] wire out_wimask_1172 = &_out_wimask_T_1172; // @[RegisterRouter.scala:87:24] wire out_romask_1172 = |_out_romask_T_1172; // @[RegisterRouter.scala:87:24] wire out_womask_1172 = &_out_womask_T_1172; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1172 = out_rivalid_1_1026 & out_rimask_1172; // @[RegisterRouter.scala:87:24] wire _out_T_11305 = out_f_rivalid_1172; // @[RegisterRouter.scala:87:24] wire out_f_roready_1172 = out_roready_1_1026 & out_romask_1172; // @[RegisterRouter.scala:87:24] wire _out_T_11306 = out_f_roready_1172; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1172 = out_wivalid_1_1026 & out_wimask_1172; // @[RegisterRouter.scala:87:24] wire out_f_woready_1172 = out_woready_1_1026 & out_womask_1172; // @[RegisterRouter.scala:87:24] wire _out_T_11307 = ~out_rimask_1172; // @[RegisterRouter.scala:87:24] wire _out_T_11308 = ~out_wimask_1172; // @[RegisterRouter.scala:87:24] wire _out_T_11309 = ~out_romask_1172; // @[RegisterRouter.scala:87:24] wire _out_T_11310 = ~out_womask_1172; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1006 = {hi_864, flags_0_go, _out_prepend_T_1006}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11311 = out_prepend_1006; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11312 = _out_T_11311; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_235 = _out_T_11312; // @[MuxLiteral.scala:49:48] wire out_rimask_1173 = |_out_rimask_T_1173; // @[RegisterRouter.scala:87:24] wire out_wimask_1173 = &_out_wimask_T_1173; // @[RegisterRouter.scala:87:24] wire out_romask_1173 = |_out_romask_T_1173; // @[RegisterRouter.scala:87:24] wire out_womask_1173 = &_out_womask_T_1173; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1173 = out_rivalid_1_1027 & out_rimask_1173; // @[RegisterRouter.scala:87:24] wire _out_T_11314 = out_f_rivalid_1173; // @[RegisterRouter.scala:87:24] wire out_f_roready_1173 = out_roready_1_1027 & out_romask_1173; // @[RegisterRouter.scala:87:24] wire _out_T_11315 = out_f_roready_1173; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1173 = out_wivalid_1_1027 & out_wimask_1173; // @[RegisterRouter.scala:87:24] wire out_f_woready_1173 = out_woready_1_1027 & out_womask_1173; // @[RegisterRouter.scala:87:24] wire _out_T_11316 = ~out_rimask_1173; // @[RegisterRouter.scala:87:24] wire _out_T_11317 = ~out_wimask_1173; // @[RegisterRouter.scala:87:24] wire _out_T_11318 = ~out_romask_1173; // @[RegisterRouter.scala:87:24] wire _out_T_11319 = ~out_womask_1173; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11321 = _out_T_11320; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1007 = _out_T_11321; // @[RegisterRouter.scala:87:24] wire out_rimask_1174 = |_out_rimask_T_1174; // @[RegisterRouter.scala:87:24] wire out_wimask_1174 = &_out_wimask_T_1174; // @[RegisterRouter.scala:87:24] wire out_romask_1174 = |_out_romask_T_1174; // @[RegisterRouter.scala:87:24] wire out_womask_1174 = &_out_womask_T_1174; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1174 = out_rivalid_1_1028 & out_rimask_1174; // @[RegisterRouter.scala:87:24] wire _out_T_11323 = out_f_rivalid_1174; // @[RegisterRouter.scala:87:24] wire out_f_roready_1174 = out_roready_1_1028 & out_romask_1174; // @[RegisterRouter.scala:87:24] wire _out_T_11324 = out_f_roready_1174; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1174 = out_wivalid_1_1028 & out_wimask_1174; // @[RegisterRouter.scala:87:24] wire out_f_woready_1174 = out_woready_1_1028 & out_womask_1174; // @[RegisterRouter.scala:87:24] wire _out_T_11325 = ~out_rimask_1174; // @[RegisterRouter.scala:87:24] wire _out_T_11326 = ~out_wimask_1174; // @[RegisterRouter.scala:87:24] wire _out_T_11327 = ~out_romask_1174; // @[RegisterRouter.scala:87:24] wire _out_T_11328 = ~out_womask_1174; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1007 = {hi_946, flags_0_go, _out_prepend_T_1007}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11329 = out_prepend_1007; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11330 = _out_T_11329; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1008 = _out_T_11330; // @[RegisterRouter.scala:87:24] wire out_rimask_1175 = |_out_rimask_T_1175; // @[RegisterRouter.scala:87:24] wire out_wimask_1175 = &_out_wimask_T_1175; // @[RegisterRouter.scala:87:24] wire out_romask_1175 = |_out_romask_T_1175; // @[RegisterRouter.scala:87:24] wire out_womask_1175 = &_out_womask_T_1175; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1175 = out_rivalid_1_1029 & out_rimask_1175; // @[RegisterRouter.scala:87:24] wire _out_T_11332 = out_f_rivalid_1175; // @[RegisterRouter.scala:87:24] wire out_f_roready_1175 = out_roready_1_1029 & out_romask_1175; // @[RegisterRouter.scala:87:24] wire _out_T_11333 = out_f_roready_1175; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1175 = out_wivalid_1_1029 & out_wimask_1175; // @[RegisterRouter.scala:87:24] wire out_f_woready_1175 = out_woready_1_1029 & out_womask_1175; // @[RegisterRouter.scala:87:24] wire _out_T_11334 = ~out_rimask_1175; // @[RegisterRouter.scala:87:24] wire _out_T_11335 = ~out_wimask_1175; // @[RegisterRouter.scala:87:24] wire _out_T_11336 = ~out_romask_1175; // @[RegisterRouter.scala:87:24] wire _out_T_11337 = ~out_womask_1175; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1008 = {hi_947, flags_0_go, _out_prepend_T_1008}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11338 = out_prepend_1008; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11339 = _out_T_11338; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1009 = _out_T_11339; // @[RegisterRouter.scala:87:24] wire out_rimask_1176 = |_out_rimask_T_1176; // @[RegisterRouter.scala:87:24] wire out_wimask_1176 = &_out_wimask_T_1176; // @[RegisterRouter.scala:87:24] wire out_romask_1176 = |_out_romask_T_1176; // @[RegisterRouter.scala:87:24] wire out_womask_1176 = &_out_womask_T_1176; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1176 = out_rivalid_1_1030 & out_rimask_1176; // @[RegisterRouter.scala:87:24] wire _out_T_11341 = out_f_rivalid_1176; // @[RegisterRouter.scala:87:24] wire out_f_roready_1176 = out_roready_1_1030 & out_romask_1176; // @[RegisterRouter.scala:87:24] wire _out_T_11342 = out_f_roready_1176; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1176 = out_wivalid_1_1030 & out_wimask_1176; // @[RegisterRouter.scala:87:24] wire out_f_woready_1176 = out_woready_1_1030 & out_womask_1176; // @[RegisterRouter.scala:87:24] wire _out_T_11343 = ~out_rimask_1176; // @[RegisterRouter.scala:87:24] wire _out_T_11344 = ~out_wimask_1176; // @[RegisterRouter.scala:87:24] wire _out_T_11345 = ~out_romask_1176; // @[RegisterRouter.scala:87:24] wire _out_T_11346 = ~out_womask_1176; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1009 = {hi_948, flags_0_go, _out_prepend_T_1009}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11347 = out_prepend_1009; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11348 = _out_T_11347; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1010 = _out_T_11348; // @[RegisterRouter.scala:87:24] wire out_rimask_1177 = |_out_rimask_T_1177; // @[RegisterRouter.scala:87:24] wire out_wimask_1177 = &_out_wimask_T_1177; // @[RegisterRouter.scala:87:24] wire out_romask_1177 = |_out_romask_T_1177; // @[RegisterRouter.scala:87:24] wire out_womask_1177 = &_out_womask_T_1177; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1177 = out_rivalid_1_1031 & out_rimask_1177; // @[RegisterRouter.scala:87:24] wire _out_T_11350 = out_f_rivalid_1177; // @[RegisterRouter.scala:87:24] wire out_f_roready_1177 = out_roready_1_1031 & out_romask_1177; // @[RegisterRouter.scala:87:24] wire _out_T_11351 = out_f_roready_1177; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1177 = out_wivalid_1_1031 & out_wimask_1177; // @[RegisterRouter.scala:87:24] wire out_f_woready_1177 = out_woready_1_1031 & out_womask_1177; // @[RegisterRouter.scala:87:24] wire _out_T_11352 = ~out_rimask_1177; // @[RegisterRouter.scala:87:24] wire _out_T_11353 = ~out_wimask_1177; // @[RegisterRouter.scala:87:24] wire _out_T_11354 = ~out_romask_1177; // @[RegisterRouter.scala:87:24] wire _out_T_11355 = ~out_womask_1177; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1010 = {hi_949, flags_0_go, _out_prepend_T_1010}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11356 = out_prepend_1010; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11357 = _out_T_11356; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1011 = _out_T_11357; // @[RegisterRouter.scala:87:24] wire out_rimask_1178 = |_out_rimask_T_1178; // @[RegisterRouter.scala:87:24] wire out_wimask_1178 = &_out_wimask_T_1178; // @[RegisterRouter.scala:87:24] wire out_romask_1178 = |_out_romask_T_1178; // @[RegisterRouter.scala:87:24] wire out_womask_1178 = &_out_womask_T_1178; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1178 = out_rivalid_1_1032 & out_rimask_1178; // @[RegisterRouter.scala:87:24] wire _out_T_11359 = out_f_rivalid_1178; // @[RegisterRouter.scala:87:24] wire out_f_roready_1178 = out_roready_1_1032 & out_romask_1178; // @[RegisterRouter.scala:87:24] wire _out_T_11360 = out_f_roready_1178; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1178 = out_wivalid_1_1032 & out_wimask_1178; // @[RegisterRouter.scala:87:24] wire out_f_woready_1178 = out_woready_1_1032 & out_womask_1178; // @[RegisterRouter.scala:87:24] wire _out_T_11361 = ~out_rimask_1178; // @[RegisterRouter.scala:87:24] wire _out_T_11362 = ~out_wimask_1178; // @[RegisterRouter.scala:87:24] wire _out_T_11363 = ~out_romask_1178; // @[RegisterRouter.scala:87:24] wire _out_T_11364 = ~out_womask_1178; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1011 = {hi_950, flags_0_go, _out_prepend_T_1011}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11365 = out_prepend_1011; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11366 = _out_T_11365; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1012 = _out_T_11366; // @[RegisterRouter.scala:87:24] wire out_rimask_1179 = |_out_rimask_T_1179; // @[RegisterRouter.scala:87:24] wire out_wimask_1179 = &_out_wimask_T_1179; // @[RegisterRouter.scala:87:24] wire out_romask_1179 = |_out_romask_T_1179; // @[RegisterRouter.scala:87:24] wire out_womask_1179 = &_out_womask_T_1179; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1179 = out_rivalid_1_1033 & out_rimask_1179; // @[RegisterRouter.scala:87:24] wire _out_T_11368 = out_f_rivalid_1179; // @[RegisterRouter.scala:87:24] wire out_f_roready_1179 = out_roready_1_1033 & out_romask_1179; // @[RegisterRouter.scala:87:24] wire _out_T_11369 = out_f_roready_1179; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1179 = out_wivalid_1_1033 & out_wimask_1179; // @[RegisterRouter.scala:87:24] wire out_f_woready_1179 = out_woready_1_1033 & out_womask_1179; // @[RegisterRouter.scala:87:24] wire _out_T_11370 = ~out_rimask_1179; // @[RegisterRouter.scala:87:24] wire _out_T_11371 = ~out_wimask_1179; // @[RegisterRouter.scala:87:24] wire _out_T_11372 = ~out_romask_1179; // @[RegisterRouter.scala:87:24] wire _out_T_11373 = ~out_womask_1179; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1012 = {hi_951, flags_0_go, _out_prepend_T_1012}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11374 = out_prepend_1012; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11375 = _out_T_11374; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1013 = _out_T_11375; // @[RegisterRouter.scala:87:24] wire out_rimask_1180 = |_out_rimask_T_1180; // @[RegisterRouter.scala:87:24] wire out_wimask_1180 = &_out_wimask_T_1180; // @[RegisterRouter.scala:87:24] wire out_romask_1180 = |_out_romask_T_1180; // @[RegisterRouter.scala:87:24] wire out_womask_1180 = &_out_womask_T_1180; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1180 = out_rivalid_1_1034 & out_rimask_1180; // @[RegisterRouter.scala:87:24] wire _out_T_11377 = out_f_rivalid_1180; // @[RegisterRouter.scala:87:24] wire out_f_roready_1180 = out_roready_1_1034 & out_romask_1180; // @[RegisterRouter.scala:87:24] wire _out_T_11378 = out_f_roready_1180; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1180 = out_wivalid_1_1034 & out_wimask_1180; // @[RegisterRouter.scala:87:24] wire out_f_woready_1180 = out_woready_1_1034 & out_womask_1180; // @[RegisterRouter.scala:87:24] wire _out_T_11379 = ~out_rimask_1180; // @[RegisterRouter.scala:87:24] wire _out_T_11380 = ~out_wimask_1180; // @[RegisterRouter.scala:87:24] wire _out_T_11381 = ~out_romask_1180; // @[RegisterRouter.scala:87:24] wire _out_T_11382 = ~out_womask_1180; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1013 = {hi_952, flags_0_go, _out_prepend_T_1013}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11383 = out_prepend_1013; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11384 = _out_T_11383; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_246 = _out_T_11384; // @[MuxLiteral.scala:49:48] wire out_rimask_1181 = |_out_rimask_T_1181; // @[RegisterRouter.scala:87:24] wire out_wimask_1181 = &_out_wimask_T_1181; // @[RegisterRouter.scala:87:24] wire out_romask_1181 = |_out_romask_T_1181; // @[RegisterRouter.scala:87:24] wire out_womask_1181 = &_out_womask_T_1181; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1181 = out_rivalid_1_1035 & out_rimask_1181; // @[RegisterRouter.scala:87:24] wire _out_T_11386 = out_f_rivalid_1181; // @[RegisterRouter.scala:87:24] wire out_f_roready_1181 = out_roready_1_1035 & out_romask_1181; // @[RegisterRouter.scala:87:24] wire _out_T_11387 = out_f_roready_1181; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1181 = out_wivalid_1_1035 & out_wimask_1181; // @[RegisterRouter.scala:87:24] wire out_f_woready_1181 = out_woready_1_1035 & out_womask_1181; // @[RegisterRouter.scala:87:24] wire _out_T_11388 = ~out_rimask_1181; // @[RegisterRouter.scala:87:24] wire _out_T_11389 = ~out_wimask_1181; // @[RegisterRouter.scala:87:24] wire _out_T_11390 = ~out_romask_1181; // @[RegisterRouter.scala:87:24] wire _out_T_11391 = ~out_womask_1181; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11393 = _out_T_11392; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1014 = _out_T_11393; // @[RegisterRouter.scala:87:24] wire out_rimask_1182 = |_out_rimask_T_1182; // @[RegisterRouter.scala:87:24] wire out_wimask_1182 = &_out_wimask_T_1182; // @[RegisterRouter.scala:87:24] wire out_romask_1182 = |_out_romask_T_1182; // @[RegisterRouter.scala:87:24] wire out_womask_1182 = &_out_womask_T_1182; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1182 = out_rivalid_1_1036 & out_rimask_1182; // @[RegisterRouter.scala:87:24] wire _out_T_11395 = out_f_rivalid_1182; // @[RegisterRouter.scala:87:24] wire out_f_roready_1182 = out_roready_1_1036 & out_romask_1182; // @[RegisterRouter.scala:87:24] wire _out_T_11396 = out_f_roready_1182; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1182 = out_wivalid_1_1036 & out_wimask_1182; // @[RegisterRouter.scala:87:24] wire out_f_woready_1182 = out_woready_1_1036 & out_womask_1182; // @[RegisterRouter.scala:87:24] wire _out_T_11397 = ~out_rimask_1182; // @[RegisterRouter.scala:87:24] wire _out_T_11398 = ~out_wimask_1182; // @[RegisterRouter.scala:87:24] wire _out_T_11399 = ~out_romask_1182; // @[RegisterRouter.scala:87:24] wire _out_T_11400 = ~out_womask_1182; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1014 = {hi_186, flags_0_go, _out_prepend_T_1014}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11401 = out_prepend_1014; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11402 = _out_T_11401; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1015 = _out_T_11402; // @[RegisterRouter.scala:87:24] wire out_rimask_1183 = |_out_rimask_T_1183; // @[RegisterRouter.scala:87:24] wire out_wimask_1183 = &_out_wimask_T_1183; // @[RegisterRouter.scala:87:24] wire out_romask_1183 = |_out_romask_T_1183; // @[RegisterRouter.scala:87:24] wire out_womask_1183 = &_out_womask_T_1183; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1183 = out_rivalid_1_1037 & out_rimask_1183; // @[RegisterRouter.scala:87:24] wire _out_T_11404 = out_f_rivalid_1183; // @[RegisterRouter.scala:87:24] wire out_f_roready_1183 = out_roready_1_1037 & out_romask_1183; // @[RegisterRouter.scala:87:24] wire _out_T_11405 = out_f_roready_1183; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1183 = out_wivalid_1_1037 & out_wimask_1183; // @[RegisterRouter.scala:87:24] wire out_f_woready_1183 = out_woready_1_1037 & out_womask_1183; // @[RegisterRouter.scala:87:24] wire _out_T_11406 = ~out_rimask_1183; // @[RegisterRouter.scala:87:24] wire _out_T_11407 = ~out_wimask_1183; // @[RegisterRouter.scala:87:24] wire _out_T_11408 = ~out_romask_1183; // @[RegisterRouter.scala:87:24] wire _out_T_11409 = ~out_womask_1183; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1015 = {hi_187, flags_0_go, _out_prepend_T_1015}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11410 = out_prepend_1015; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11411 = _out_T_11410; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1016 = _out_T_11411; // @[RegisterRouter.scala:87:24] wire out_rimask_1184 = |_out_rimask_T_1184; // @[RegisterRouter.scala:87:24] wire out_wimask_1184 = &_out_wimask_T_1184; // @[RegisterRouter.scala:87:24] wire out_romask_1184 = |_out_romask_T_1184; // @[RegisterRouter.scala:87:24] wire out_womask_1184 = &_out_womask_T_1184; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1184 = out_rivalid_1_1038 & out_rimask_1184; // @[RegisterRouter.scala:87:24] wire _out_T_11413 = out_f_rivalid_1184; // @[RegisterRouter.scala:87:24] wire out_f_roready_1184 = out_roready_1_1038 & out_romask_1184; // @[RegisterRouter.scala:87:24] wire _out_T_11414 = out_f_roready_1184; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1184 = out_wivalid_1_1038 & out_wimask_1184; // @[RegisterRouter.scala:87:24] wire out_f_woready_1184 = out_woready_1_1038 & out_womask_1184; // @[RegisterRouter.scala:87:24] wire _out_T_11415 = ~out_rimask_1184; // @[RegisterRouter.scala:87:24] wire _out_T_11416 = ~out_wimask_1184; // @[RegisterRouter.scala:87:24] wire _out_T_11417 = ~out_romask_1184; // @[RegisterRouter.scala:87:24] wire _out_T_11418 = ~out_womask_1184; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1016 = {hi_188, flags_0_go, _out_prepend_T_1016}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11419 = out_prepend_1016; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11420 = _out_T_11419; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1017 = _out_T_11420; // @[RegisterRouter.scala:87:24] wire out_rimask_1185 = |_out_rimask_T_1185; // @[RegisterRouter.scala:87:24] wire out_wimask_1185 = &_out_wimask_T_1185; // @[RegisterRouter.scala:87:24] wire out_romask_1185 = |_out_romask_T_1185; // @[RegisterRouter.scala:87:24] wire out_womask_1185 = &_out_womask_T_1185; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1185 = out_rivalid_1_1039 & out_rimask_1185; // @[RegisterRouter.scala:87:24] wire _out_T_11422 = out_f_rivalid_1185; // @[RegisterRouter.scala:87:24] wire out_f_roready_1185 = out_roready_1_1039 & out_romask_1185; // @[RegisterRouter.scala:87:24] wire _out_T_11423 = out_f_roready_1185; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1185 = out_wivalid_1_1039 & out_wimask_1185; // @[RegisterRouter.scala:87:24] wire out_f_woready_1185 = out_woready_1_1039 & out_womask_1185; // @[RegisterRouter.scala:87:24] wire _out_T_11424 = ~out_rimask_1185; // @[RegisterRouter.scala:87:24] wire _out_T_11425 = ~out_wimask_1185; // @[RegisterRouter.scala:87:24] wire _out_T_11426 = ~out_romask_1185; // @[RegisterRouter.scala:87:24] wire _out_T_11427 = ~out_womask_1185; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1017 = {hi_189, flags_0_go, _out_prepend_T_1017}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11428 = out_prepend_1017; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11429 = _out_T_11428; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1018 = _out_T_11429; // @[RegisterRouter.scala:87:24] wire out_rimask_1186 = |_out_rimask_T_1186; // @[RegisterRouter.scala:87:24] wire out_wimask_1186 = &_out_wimask_T_1186; // @[RegisterRouter.scala:87:24] wire out_romask_1186 = |_out_romask_T_1186; // @[RegisterRouter.scala:87:24] wire out_womask_1186 = &_out_womask_T_1186; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1186 = out_rivalid_1_1040 & out_rimask_1186; // @[RegisterRouter.scala:87:24] wire _out_T_11431 = out_f_rivalid_1186; // @[RegisterRouter.scala:87:24] wire out_f_roready_1186 = out_roready_1_1040 & out_romask_1186; // @[RegisterRouter.scala:87:24] wire _out_T_11432 = out_f_roready_1186; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1186 = out_wivalid_1_1040 & out_wimask_1186; // @[RegisterRouter.scala:87:24] wire out_f_woready_1186 = out_woready_1_1040 & out_womask_1186; // @[RegisterRouter.scala:87:24] wire _out_T_11433 = ~out_rimask_1186; // @[RegisterRouter.scala:87:24] wire _out_T_11434 = ~out_wimask_1186; // @[RegisterRouter.scala:87:24] wire _out_T_11435 = ~out_romask_1186; // @[RegisterRouter.scala:87:24] wire _out_T_11436 = ~out_womask_1186; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1018 = {hi_190, flags_0_go, _out_prepend_T_1018}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11437 = out_prepend_1018; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11438 = _out_T_11437; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1019 = _out_T_11438; // @[RegisterRouter.scala:87:24] wire out_rimask_1187 = |_out_rimask_T_1187; // @[RegisterRouter.scala:87:24] wire out_wimask_1187 = &_out_wimask_T_1187; // @[RegisterRouter.scala:87:24] wire out_romask_1187 = |_out_romask_T_1187; // @[RegisterRouter.scala:87:24] wire out_womask_1187 = &_out_womask_T_1187; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1187 = out_rivalid_1_1041 & out_rimask_1187; // @[RegisterRouter.scala:87:24] wire _out_T_11440 = out_f_rivalid_1187; // @[RegisterRouter.scala:87:24] wire out_f_roready_1187 = out_roready_1_1041 & out_romask_1187; // @[RegisterRouter.scala:87:24] wire _out_T_11441 = out_f_roready_1187; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1187 = out_wivalid_1_1041 & out_wimask_1187; // @[RegisterRouter.scala:87:24] wire out_f_woready_1187 = out_woready_1_1041 & out_womask_1187; // @[RegisterRouter.scala:87:24] wire _out_T_11442 = ~out_rimask_1187; // @[RegisterRouter.scala:87:24] wire _out_T_11443 = ~out_wimask_1187; // @[RegisterRouter.scala:87:24] wire _out_T_11444 = ~out_romask_1187; // @[RegisterRouter.scala:87:24] wire _out_T_11445 = ~out_womask_1187; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1019 = {hi_191, flags_0_go, _out_prepend_T_1019}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11446 = out_prepend_1019; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11447 = _out_T_11446; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1020 = _out_T_11447; // @[RegisterRouter.scala:87:24] wire out_rimask_1188 = |_out_rimask_T_1188; // @[RegisterRouter.scala:87:24] wire out_wimask_1188 = &_out_wimask_T_1188; // @[RegisterRouter.scala:87:24] wire out_romask_1188 = |_out_romask_T_1188; // @[RegisterRouter.scala:87:24] wire out_womask_1188 = &_out_womask_T_1188; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1188 = out_rivalid_1_1042 & out_rimask_1188; // @[RegisterRouter.scala:87:24] wire _out_T_11449 = out_f_rivalid_1188; // @[RegisterRouter.scala:87:24] wire out_f_roready_1188 = out_roready_1_1042 & out_romask_1188; // @[RegisterRouter.scala:87:24] wire _out_T_11450 = out_f_roready_1188; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1188 = out_wivalid_1_1042 & out_wimask_1188; // @[RegisterRouter.scala:87:24] wire out_f_woready_1188 = out_woready_1_1042 & out_womask_1188; // @[RegisterRouter.scala:87:24] wire _out_T_11451 = ~out_rimask_1188; // @[RegisterRouter.scala:87:24] wire _out_T_11452 = ~out_wimask_1188; // @[RegisterRouter.scala:87:24] wire _out_T_11453 = ~out_romask_1188; // @[RegisterRouter.scala:87:24] wire _out_T_11454 = ~out_womask_1188; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1020 = {hi_192, flags_0_go, _out_prepend_T_1020}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11455 = out_prepend_1020; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11456 = _out_T_11455; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_151 = _out_T_11456; // @[MuxLiteral.scala:49:48] wire out_rimask_1189 = |_out_rimask_T_1189; // @[RegisterRouter.scala:87:24] wire out_wimask_1189 = &_out_wimask_T_1189; // @[RegisterRouter.scala:87:24] wire out_romask_1189 = |_out_romask_T_1189; // @[RegisterRouter.scala:87:24] wire out_womask_1189 = &_out_womask_T_1189; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1189 = out_rivalid_1_1043 & out_rimask_1189; // @[RegisterRouter.scala:87:24] wire _out_T_11458 = out_f_rivalid_1189; // @[RegisterRouter.scala:87:24] wire out_f_roready_1189 = out_roready_1_1043 & out_romask_1189; // @[RegisterRouter.scala:87:24] wire _out_T_11459 = out_f_roready_1189; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1189 = out_wivalid_1_1043 & out_wimask_1189; // @[RegisterRouter.scala:87:24] wire out_f_woready_1189 = out_woready_1_1043 & out_womask_1189; // @[RegisterRouter.scala:87:24] wire _out_T_11460 = ~out_rimask_1189; // @[RegisterRouter.scala:87:24] wire _out_T_11461 = ~out_wimask_1189; // @[RegisterRouter.scala:87:24] wire _out_T_11462 = ~out_romask_1189; // @[RegisterRouter.scala:87:24] wire _out_T_11463 = ~out_womask_1189; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11465 = _out_T_11464; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1021 = _out_T_11465; // @[RegisterRouter.scala:87:24] wire out_rimask_1190 = |_out_rimask_T_1190; // @[RegisterRouter.scala:87:24] wire out_wimask_1190 = &_out_wimask_T_1190; // @[RegisterRouter.scala:87:24] wire out_romask_1190 = |_out_romask_T_1190; // @[RegisterRouter.scala:87:24] wire out_womask_1190 = &_out_womask_T_1190; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1190 = out_rivalid_1_1044 & out_rimask_1190; // @[RegisterRouter.scala:87:24] wire _out_T_11467 = out_f_rivalid_1190; // @[RegisterRouter.scala:87:24] wire out_f_roready_1190 = out_roready_1_1044 & out_romask_1190; // @[RegisterRouter.scala:87:24] wire _out_T_11468 = out_f_roready_1190; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1190 = out_wivalid_1_1044 & out_wimask_1190; // @[RegisterRouter.scala:87:24] wire out_f_woready_1190 = out_woready_1_1044 & out_womask_1190; // @[RegisterRouter.scala:87:24] wire _out_T_11469 = ~out_rimask_1190; // @[RegisterRouter.scala:87:24] wire _out_T_11470 = ~out_wimask_1190; // @[RegisterRouter.scala:87:24] wire _out_T_11471 = ~out_romask_1190; // @[RegisterRouter.scala:87:24] wire _out_T_11472 = ~out_womask_1190; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1021 = {hi_146, flags_0_go, _out_prepend_T_1021}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11473 = out_prepend_1021; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11474 = _out_T_11473; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1022 = _out_T_11474; // @[RegisterRouter.scala:87:24] wire out_rimask_1191 = |_out_rimask_T_1191; // @[RegisterRouter.scala:87:24] wire out_wimask_1191 = &_out_wimask_T_1191; // @[RegisterRouter.scala:87:24] wire out_romask_1191 = |_out_romask_T_1191; // @[RegisterRouter.scala:87:24] wire out_womask_1191 = &_out_womask_T_1191; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1191 = out_rivalid_1_1045 & out_rimask_1191; // @[RegisterRouter.scala:87:24] wire _out_T_11476 = out_f_rivalid_1191; // @[RegisterRouter.scala:87:24] wire out_f_roready_1191 = out_roready_1_1045 & out_romask_1191; // @[RegisterRouter.scala:87:24] wire _out_T_11477 = out_f_roready_1191; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1191 = out_wivalid_1_1045 & out_wimask_1191; // @[RegisterRouter.scala:87:24] wire out_f_woready_1191 = out_woready_1_1045 & out_womask_1191; // @[RegisterRouter.scala:87:24] wire _out_T_11478 = ~out_rimask_1191; // @[RegisterRouter.scala:87:24] wire _out_T_11479 = ~out_wimask_1191; // @[RegisterRouter.scala:87:24] wire _out_T_11480 = ~out_romask_1191; // @[RegisterRouter.scala:87:24] wire _out_T_11481 = ~out_womask_1191; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1022 = {hi_147, flags_0_go, _out_prepend_T_1022}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11482 = out_prepend_1022; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11483 = _out_T_11482; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1023 = _out_T_11483; // @[RegisterRouter.scala:87:24] wire out_rimask_1192 = |_out_rimask_T_1192; // @[RegisterRouter.scala:87:24] wire out_wimask_1192 = &_out_wimask_T_1192; // @[RegisterRouter.scala:87:24] wire out_romask_1192 = |_out_romask_T_1192; // @[RegisterRouter.scala:87:24] wire out_womask_1192 = &_out_womask_T_1192; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1192 = out_rivalid_1_1046 & out_rimask_1192; // @[RegisterRouter.scala:87:24] wire _out_T_11485 = out_f_rivalid_1192; // @[RegisterRouter.scala:87:24] wire out_f_roready_1192 = out_roready_1_1046 & out_romask_1192; // @[RegisterRouter.scala:87:24] wire _out_T_11486 = out_f_roready_1192; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1192 = out_wivalid_1_1046 & out_wimask_1192; // @[RegisterRouter.scala:87:24] wire out_f_woready_1192 = out_woready_1_1046 & out_womask_1192; // @[RegisterRouter.scala:87:24] wire _out_T_11487 = ~out_rimask_1192; // @[RegisterRouter.scala:87:24] wire _out_T_11488 = ~out_wimask_1192; // @[RegisterRouter.scala:87:24] wire _out_T_11489 = ~out_romask_1192; // @[RegisterRouter.scala:87:24] wire _out_T_11490 = ~out_womask_1192; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1023 = {hi_148, flags_0_go, _out_prepend_T_1023}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11491 = out_prepend_1023; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11492 = _out_T_11491; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1024 = _out_T_11492; // @[RegisterRouter.scala:87:24] wire out_rimask_1193 = |_out_rimask_T_1193; // @[RegisterRouter.scala:87:24] wire out_wimask_1193 = &_out_wimask_T_1193; // @[RegisterRouter.scala:87:24] wire out_romask_1193 = |_out_romask_T_1193; // @[RegisterRouter.scala:87:24] wire out_womask_1193 = &_out_womask_T_1193; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1193 = out_rivalid_1_1047 & out_rimask_1193; // @[RegisterRouter.scala:87:24] wire _out_T_11494 = out_f_rivalid_1193; // @[RegisterRouter.scala:87:24] wire out_f_roready_1193 = out_roready_1_1047 & out_romask_1193; // @[RegisterRouter.scala:87:24] wire _out_T_11495 = out_f_roready_1193; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1193 = out_wivalid_1_1047 & out_wimask_1193; // @[RegisterRouter.scala:87:24] wire out_f_woready_1193 = out_woready_1_1047 & out_womask_1193; // @[RegisterRouter.scala:87:24] wire _out_T_11496 = ~out_rimask_1193; // @[RegisterRouter.scala:87:24] wire _out_T_11497 = ~out_wimask_1193; // @[RegisterRouter.scala:87:24] wire _out_T_11498 = ~out_romask_1193; // @[RegisterRouter.scala:87:24] wire _out_T_11499 = ~out_womask_1193; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1024 = {hi_149, flags_0_go, _out_prepend_T_1024}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11500 = out_prepend_1024; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11501 = _out_T_11500; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1025 = _out_T_11501; // @[RegisterRouter.scala:87:24] wire out_rimask_1194 = |_out_rimask_T_1194; // @[RegisterRouter.scala:87:24] wire out_wimask_1194 = &_out_wimask_T_1194; // @[RegisterRouter.scala:87:24] wire out_romask_1194 = |_out_romask_T_1194; // @[RegisterRouter.scala:87:24] wire out_womask_1194 = &_out_womask_T_1194; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1194 = out_rivalid_1_1048 & out_rimask_1194; // @[RegisterRouter.scala:87:24] wire _out_T_11503 = out_f_rivalid_1194; // @[RegisterRouter.scala:87:24] wire out_f_roready_1194 = out_roready_1_1048 & out_romask_1194; // @[RegisterRouter.scala:87:24] wire _out_T_11504 = out_f_roready_1194; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1194 = out_wivalid_1_1048 & out_wimask_1194; // @[RegisterRouter.scala:87:24] wire out_f_woready_1194 = out_woready_1_1048 & out_womask_1194; // @[RegisterRouter.scala:87:24] wire _out_T_11505 = ~out_rimask_1194; // @[RegisterRouter.scala:87:24] wire _out_T_11506 = ~out_wimask_1194; // @[RegisterRouter.scala:87:24] wire _out_T_11507 = ~out_romask_1194; // @[RegisterRouter.scala:87:24] wire _out_T_11508 = ~out_womask_1194; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1025 = {hi_150, flags_0_go, _out_prepend_T_1025}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11509 = out_prepend_1025; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11510 = _out_T_11509; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1026 = _out_T_11510; // @[RegisterRouter.scala:87:24] wire out_rimask_1195 = |_out_rimask_T_1195; // @[RegisterRouter.scala:87:24] wire out_wimask_1195 = &_out_wimask_T_1195; // @[RegisterRouter.scala:87:24] wire out_romask_1195 = |_out_romask_T_1195; // @[RegisterRouter.scala:87:24] wire out_womask_1195 = &_out_womask_T_1195; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1195 = out_rivalid_1_1049 & out_rimask_1195; // @[RegisterRouter.scala:87:24] wire _out_T_11512 = out_f_rivalid_1195; // @[RegisterRouter.scala:87:24] wire out_f_roready_1195 = out_roready_1_1049 & out_romask_1195; // @[RegisterRouter.scala:87:24] wire _out_T_11513 = out_f_roready_1195; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1195 = out_wivalid_1_1049 & out_wimask_1195; // @[RegisterRouter.scala:87:24] wire out_f_woready_1195 = out_woready_1_1049 & out_womask_1195; // @[RegisterRouter.scala:87:24] wire _out_T_11514 = ~out_rimask_1195; // @[RegisterRouter.scala:87:24] wire _out_T_11515 = ~out_wimask_1195; // @[RegisterRouter.scala:87:24] wire _out_T_11516 = ~out_romask_1195; // @[RegisterRouter.scala:87:24] wire _out_T_11517 = ~out_womask_1195; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1026 = {hi_151, flags_0_go, _out_prepend_T_1026}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11518 = out_prepend_1026; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11519 = _out_T_11518; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1027 = _out_T_11519; // @[RegisterRouter.scala:87:24] wire out_rimask_1196 = |_out_rimask_T_1196; // @[RegisterRouter.scala:87:24] wire out_wimask_1196 = &_out_wimask_T_1196; // @[RegisterRouter.scala:87:24] wire out_romask_1196 = |_out_romask_T_1196; // @[RegisterRouter.scala:87:24] wire out_womask_1196 = &_out_womask_T_1196; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1196 = out_rivalid_1_1050 & out_rimask_1196; // @[RegisterRouter.scala:87:24] wire _out_T_11521 = out_f_rivalid_1196; // @[RegisterRouter.scala:87:24] wire out_f_roready_1196 = out_roready_1_1050 & out_romask_1196; // @[RegisterRouter.scala:87:24] wire _out_T_11522 = out_f_roready_1196; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1196 = out_wivalid_1_1050 & out_wimask_1196; // @[RegisterRouter.scala:87:24] wire out_f_woready_1196 = out_woready_1_1050 & out_womask_1196; // @[RegisterRouter.scala:87:24] wire _out_T_11523 = ~out_rimask_1196; // @[RegisterRouter.scala:87:24] wire _out_T_11524 = ~out_wimask_1196; // @[RegisterRouter.scala:87:24] wire _out_T_11525 = ~out_romask_1196; // @[RegisterRouter.scala:87:24] wire _out_T_11526 = ~out_womask_1196; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1027 = {hi_152, flags_0_go, _out_prepend_T_1027}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11527 = out_prepend_1027; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11528 = _out_T_11527; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_146 = _out_T_11528; // @[MuxLiteral.scala:49:48] wire out_rimask_1197 = |_out_rimask_T_1197; // @[RegisterRouter.scala:87:24] wire out_wimask_1197 = &_out_wimask_T_1197; // @[RegisterRouter.scala:87:24] wire out_romask_1197 = |_out_romask_T_1197; // @[RegisterRouter.scala:87:24] wire out_womask_1197 = &_out_womask_T_1197; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1197 = out_rivalid_1_1051 & out_rimask_1197; // @[RegisterRouter.scala:87:24] wire _out_T_11530 = out_f_rivalid_1197; // @[RegisterRouter.scala:87:24] wire out_f_roready_1197 = out_roready_1_1051 & out_romask_1197; // @[RegisterRouter.scala:87:24] wire _out_T_11531 = out_f_roready_1197; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1197 = out_wivalid_1_1051 & out_wimask_1197; // @[RegisterRouter.scala:87:24] wire out_f_woready_1197 = out_woready_1_1051 & out_womask_1197; // @[RegisterRouter.scala:87:24] wire _out_T_11532 = ~out_rimask_1197; // @[RegisterRouter.scala:87:24] wire _out_T_11533 = ~out_wimask_1197; // @[RegisterRouter.scala:87:24] wire _out_T_11534 = ~out_romask_1197; // @[RegisterRouter.scala:87:24] wire _out_T_11535 = ~out_womask_1197; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11537 = _out_T_11536; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1028 = _out_T_11537; // @[RegisterRouter.scala:87:24] wire out_rimask_1198 = |_out_rimask_T_1198; // @[RegisterRouter.scala:87:24] wire out_wimask_1198 = &_out_wimask_T_1198; // @[RegisterRouter.scala:87:24] wire out_romask_1198 = |_out_romask_T_1198; // @[RegisterRouter.scala:87:24] wire out_womask_1198 = &_out_womask_T_1198; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1198 = out_rivalid_1_1052 & out_rimask_1198; // @[RegisterRouter.scala:87:24] wire _out_T_11539 = out_f_rivalid_1198; // @[RegisterRouter.scala:87:24] wire out_f_roready_1198 = out_roready_1_1052 & out_romask_1198; // @[RegisterRouter.scala:87:24] wire _out_T_11540 = out_f_roready_1198; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1198 = out_wivalid_1_1052 & out_wimask_1198; // @[RegisterRouter.scala:87:24] wire out_f_woready_1198 = out_woready_1_1052 & out_womask_1198; // @[RegisterRouter.scala:87:24] wire _out_T_11541 = ~out_rimask_1198; // @[RegisterRouter.scala:87:24] wire _out_T_11542 = ~out_wimask_1198; // @[RegisterRouter.scala:87:24] wire _out_T_11543 = ~out_romask_1198; // @[RegisterRouter.scala:87:24] wire _out_T_11544 = ~out_womask_1198; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1028 = {hi_498, flags_0_go, _out_prepend_T_1028}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11545 = out_prepend_1028; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11546 = _out_T_11545; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1029 = _out_T_11546; // @[RegisterRouter.scala:87:24] wire out_rimask_1199 = |_out_rimask_T_1199; // @[RegisterRouter.scala:87:24] wire out_wimask_1199 = &_out_wimask_T_1199; // @[RegisterRouter.scala:87:24] wire out_romask_1199 = |_out_romask_T_1199; // @[RegisterRouter.scala:87:24] wire out_womask_1199 = &_out_womask_T_1199; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1199 = out_rivalid_1_1053 & out_rimask_1199; // @[RegisterRouter.scala:87:24] wire _out_T_11548 = out_f_rivalid_1199; // @[RegisterRouter.scala:87:24] wire out_f_roready_1199 = out_roready_1_1053 & out_romask_1199; // @[RegisterRouter.scala:87:24] wire _out_T_11549 = out_f_roready_1199; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1199 = out_wivalid_1_1053 & out_wimask_1199; // @[RegisterRouter.scala:87:24] wire out_f_woready_1199 = out_woready_1_1053 & out_womask_1199; // @[RegisterRouter.scala:87:24] wire _out_T_11550 = ~out_rimask_1199; // @[RegisterRouter.scala:87:24] wire _out_T_11551 = ~out_wimask_1199; // @[RegisterRouter.scala:87:24] wire _out_T_11552 = ~out_romask_1199; // @[RegisterRouter.scala:87:24] wire _out_T_11553 = ~out_womask_1199; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1029 = {hi_499, flags_0_go, _out_prepend_T_1029}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11554 = out_prepend_1029; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11555 = _out_T_11554; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1030 = _out_T_11555; // @[RegisterRouter.scala:87:24] wire out_rimask_1200 = |_out_rimask_T_1200; // @[RegisterRouter.scala:87:24] wire out_wimask_1200 = &_out_wimask_T_1200; // @[RegisterRouter.scala:87:24] wire out_romask_1200 = |_out_romask_T_1200; // @[RegisterRouter.scala:87:24] wire out_womask_1200 = &_out_womask_T_1200; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1200 = out_rivalid_1_1054 & out_rimask_1200; // @[RegisterRouter.scala:87:24] wire _out_T_11557 = out_f_rivalid_1200; // @[RegisterRouter.scala:87:24] wire out_f_roready_1200 = out_roready_1_1054 & out_romask_1200; // @[RegisterRouter.scala:87:24] wire _out_T_11558 = out_f_roready_1200; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1200 = out_wivalid_1_1054 & out_wimask_1200; // @[RegisterRouter.scala:87:24] wire out_f_woready_1200 = out_woready_1_1054 & out_womask_1200; // @[RegisterRouter.scala:87:24] wire _out_T_11559 = ~out_rimask_1200; // @[RegisterRouter.scala:87:24] wire _out_T_11560 = ~out_wimask_1200; // @[RegisterRouter.scala:87:24] wire _out_T_11561 = ~out_romask_1200; // @[RegisterRouter.scala:87:24] wire _out_T_11562 = ~out_womask_1200; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1030 = {hi_500, flags_0_go, _out_prepend_T_1030}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11563 = out_prepend_1030; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11564 = _out_T_11563; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1031 = _out_T_11564; // @[RegisterRouter.scala:87:24] wire out_rimask_1201 = |_out_rimask_T_1201; // @[RegisterRouter.scala:87:24] wire out_wimask_1201 = &_out_wimask_T_1201; // @[RegisterRouter.scala:87:24] wire out_romask_1201 = |_out_romask_T_1201; // @[RegisterRouter.scala:87:24] wire out_womask_1201 = &_out_womask_T_1201; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1201 = out_rivalid_1_1055 & out_rimask_1201; // @[RegisterRouter.scala:87:24] wire _out_T_11566 = out_f_rivalid_1201; // @[RegisterRouter.scala:87:24] wire out_f_roready_1201 = out_roready_1_1055 & out_romask_1201; // @[RegisterRouter.scala:87:24] wire _out_T_11567 = out_f_roready_1201; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1201 = out_wivalid_1_1055 & out_wimask_1201; // @[RegisterRouter.scala:87:24] wire out_f_woready_1201 = out_woready_1_1055 & out_womask_1201; // @[RegisterRouter.scala:87:24] wire _out_T_11568 = ~out_rimask_1201; // @[RegisterRouter.scala:87:24] wire _out_T_11569 = ~out_wimask_1201; // @[RegisterRouter.scala:87:24] wire _out_T_11570 = ~out_romask_1201; // @[RegisterRouter.scala:87:24] wire _out_T_11571 = ~out_womask_1201; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1031 = {hi_501, flags_0_go, _out_prepend_T_1031}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11572 = out_prepend_1031; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11573 = _out_T_11572; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1032 = _out_T_11573; // @[RegisterRouter.scala:87:24] wire out_rimask_1202 = |_out_rimask_T_1202; // @[RegisterRouter.scala:87:24] wire out_wimask_1202 = &_out_wimask_T_1202; // @[RegisterRouter.scala:87:24] wire out_romask_1202 = |_out_romask_T_1202; // @[RegisterRouter.scala:87:24] wire out_womask_1202 = &_out_womask_T_1202; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1202 = out_rivalid_1_1056 & out_rimask_1202; // @[RegisterRouter.scala:87:24] wire _out_T_11575 = out_f_rivalid_1202; // @[RegisterRouter.scala:87:24] wire out_f_roready_1202 = out_roready_1_1056 & out_romask_1202; // @[RegisterRouter.scala:87:24] wire _out_T_11576 = out_f_roready_1202; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1202 = out_wivalid_1_1056 & out_wimask_1202; // @[RegisterRouter.scala:87:24] wire out_f_woready_1202 = out_woready_1_1056 & out_womask_1202; // @[RegisterRouter.scala:87:24] wire _out_T_11577 = ~out_rimask_1202; // @[RegisterRouter.scala:87:24] wire _out_T_11578 = ~out_wimask_1202; // @[RegisterRouter.scala:87:24] wire _out_T_11579 = ~out_romask_1202; // @[RegisterRouter.scala:87:24] wire _out_T_11580 = ~out_womask_1202; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1032 = {hi_502, flags_0_go, _out_prepend_T_1032}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11581 = out_prepend_1032; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11582 = _out_T_11581; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1033 = _out_T_11582; // @[RegisterRouter.scala:87:24] wire out_rimask_1203 = |_out_rimask_T_1203; // @[RegisterRouter.scala:87:24] wire out_wimask_1203 = &_out_wimask_T_1203; // @[RegisterRouter.scala:87:24] wire out_romask_1203 = |_out_romask_T_1203; // @[RegisterRouter.scala:87:24] wire out_womask_1203 = &_out_womask_T_1203; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1203 = out_rivalid_1_1057 & out_rimask_1203; // @[RegisterRouter.scala:87:24] wire _out_T_11584 = out_f_rivalid_1203; // @[RegisterRouter.scala:87:24] wire out_f_roready_1203 = out_roready_1_1057 & out_romask_1203; // @[RegisterRouter.scala:87:24] wire _out_T_11585 = out_f_roready_1203; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1203 = out_wivalid_1_1057 & out_wimask_1203; // @[RegisterRouter.scala:87:24] wire out_f_woready_1203 = out_woready_1_1057 & out_womask_1203; // @[RegisterRouter.scala:87:24] wire _out_T_11586 = ~out_rimask_1203; // @[RegisterRouter.scala:87:24] wire _out_T_11587 = ~out_wimask_1203; // @[RegisterRouter.scala:87:24] wire _out_T_11588 = ~out_romask_1203; // @[RegisterRouter.scala:87:24] wire _out_T_11589 = ~out_womask_1203; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1033 = {hi_503, flags_0_go, _out_prepend_T_1033}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11590 = out_prepend_1033; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11591 = _out_T_11590; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1034 = _out_T_11591; // @[RegisterRouter.scala:87:24] wire out_rimask_1204 = |_out_rimask_T_1204; // @[RegisterRouter.scala:87:24] wire out_wimask_1204 = &_out_wimask_T_1204; // @[RegisterRouter.scala:87:24] wire out_romask_1204 = |_out_romask_T_1204; // @[RegisterRouter.scala:87:24] wire out_womask_1204 = &_out_womask_T_1204; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1204 = out_rivalid_1_1058 & out_rimask_1204; // @[RegisterRouter.scala:87:24] wire _out_T_11593 = out_f_rivalid_1204; // @[RegisterRouter.scala:87:24] wire out_f_roready_1204 = out_roready_1_1058 & out_romask_1204; // @[RegisterRouter.scala:87:24] wire _out_T_11594 = out_f_roready_1204; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1204 = out_wivalid_1_1058 & out_wimask_1204; // @[RegisterRouter.scala:87:24] wire out_f_woready_1204 = out_woready_1_1058 & out_womask_1204; // @[RegisterRouter.scala:87:24] wire _out_T_11595 = ~out_rimask_1204; // @[RegisterRouter.scala:87:24] wire _out_T_11596 = ~out_wimask_1204; // @[RegisterRouter.scala:87:24] wire _out_T_11597 = ~out_romask_1204; // @[RegisterRouter.scala:87:24] wire _out_T_11598 = ~out_womask_1204; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1034 = {hi_504, flags_0_go, _out_prepend_T_1034}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11599 = out_prepend_1034; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11600 = _out_T_11599; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_190 = _out_T_11600; // @[MuxLiteral.scala:49:48] wire out_rimask_1205 = |_out_rimask_T_1205; // @[RegisterRouter.scala:87:24] wire out_wimask_1205 = &_out_wimask_T_1205; // @[RegisterRouter.scala:87:24] wire out_romask_1205 = |_out_romask_T_1205; // @[RegisterRouter.scala:87:24] wire out_womask_1205 = &_out_womask_T_1205; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1205 = out_rivalid_1_1059 & out_rimask_1205; // @[RegisterRouter.scala:87:24] wire _out_T_11602 = out_f_rivalid_1205; // @[RegisterRouter.scala:87:24] wire out_f_roready_1205 = out_roready_1_1059 & out_romask_1205; // @[RegisterRouter.scala:87:24] wire _out_T_11603 = out_f_roready_1205; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1205 = out_wivalid_1_1059 & out_wimask_1205; // @[RegisterRouter.scala:87:24] wire out_f_woready_1205 = out_woready_1_1059 & out_womask_1205; // @[RegisterRouter.scala:87:24] wire _out_T_11604 = ~out_rimask_1205; // @[RegisterRouter.scala:87:24] wire _out_T_11605 = ~out_wimask_1205; // @[RegisterRouter.scala:87:24] wire _out_T_11606 = ~out_romask_1205; // @[RegisterRouter.scala:87:24] wire _out_T_11607 = ~out_womask_1205; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11609 = _out_T_11608; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1035 = _out_T_11609; // @[RegisterRouter.scala:87:24] wire out_rimask_1206 = |_out_rimask_T_1206; // @[RegisterRouter.scala:87:24] wire out_wimask_1206 = &_out_wimask_T_1206; // @[RegisterRouter.scala:87:24] wire out_romask_1206 = |_out_romask_T_1206; // @[RegisterRouter.scala:87:24] wire out_womask_1206 = &_out_womask_T_1206; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1206 = out_rivalid_1_1060 & out_rimask_1206; // @[RegisterRouter.scala:87:24] wire _out_T_11611 = out_f_rivalid_1206; // @[RegisterRouter.scala:87:24] wire out_f_roready_1206 = out_roready_1_1060 & out_romask_1206; // @[RegisterRouter.scala:87:24] wire _out_T_11612 = out_f_roready_1206; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1206 = out_wivalid_1_1060 & out_wimask_1206; // @[RegisterRouter.scala:87:24] wire out_f_woready_1206 = out_woready_1_1060 & out_womask_1206; // @[RegisterRouter.scala:87:24] wire _out_T_11613 = ~out_rimask_1206; // @[RegisterRouter.scala:87:24] wire _out_T_11614 = ~out_wimask_1206; // @[RegisterRouter.scala:87:24] wire _out_T_11615 = ~out_romask_1206; // @[RegisterRouter.scala:87:24] wire _out_T_11616 = ~out_womask_1206; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1035 = {hi_442, flags_0_go, _out_prepend_T_1035}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11617 = out_prepend_1035; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11618 = _out_T_11617; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1036 = _out_T_11618; // @[RegisterRouter.scala:87:24] wire out_rimask_1207 = |_out_rimask_T_1207; // @[RegisterRouter.scala:87:24] wire out_wimask_1207 = &_out_wimask_T_1207; // @[RegisterRouter.scala:87:24] wire out_romask_1207 = |_out_romask_T_1207; // @[RegisterRouter.scala:87:24] wire out_womask_1207 = &_out_womask_T_1207; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1207 = out_rivalid_1_1061 & out_rimask_1207; // @[RegisterRouter.scala:87:24] wire _out_T_11620 = out_f_rivalid_1207; // @[RegisterRouter.scala:87:24] wire out_f_roready_1207 = out_roready_1_1061 & out_romask_1207; // @[RegisterRouter.scala:87:24] wire _out_T_11621 = out_f_roready_1207; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1207 = out_wivalid_1_1061 & out_wimask_1207; // @[RegisterRouter.scala:87:24] wire out_f_woready_1207 = out_woready_1_1061 & out_womask_1207; // @[RegisterRouter.scala:87:24] wire _out_T_11622 = ~out_rimask_1207; // @[RegisterRouter.scala:87:24] wire _out_T_11623 = ~out_wimask_1207; // @[RegisterRouter.scala:87:24] wire _out_T_11624 = ~out_romask_1207; // @[RegisterRouter.scala:87:24] wire _out_T_11625 = ~out_womask_1207; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1036 = {hi_443, flags_0_go, _out_prepend_T_1036}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11626 = out_prepend_1036; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11627 = _out_T_11626; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1037 = _out_T_11627; // @[RegisterRouter.scala:87:24] wire out_rimask_1208 = |_out_rimask_T_1208; // @[RegisterRouter.scala:87:24] wire out_wimask_1208 = &_out_wimask_T_1208; // @[RegisterRouter.scala:87:24] wire out_romask_1208 = |_out_romask_T_1208; // @[RegisterRouter.scala:87:24] wire out_womask_1208 = &_out_womask_T_1208; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1208 = out_rivalid_1_1062 & out_rimask_1208; // @[RegisterRouter.scala:87:24] wire _out_T_11629 = out_f_rivalid_1208; // @[RegisterRouter.scala:87:24] wire out_f_roready_1208 = out_roready_1_1062 & out_romask_1208; // @[RegisterRouter.scala:87:24] wire _out_T_11630 = out_f_roready_1208; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1208 = out_wivalid_1_1062 & out_wimask_1208; // @[RegisterRouter.scala:87:24] wire out_f_woready_1208 = out_woready_1_1062 & out_womask_1208; // @[RegisterRouter.scala:87:24] wire _out_T_11631 = ~out_rimask_1208; // @[RegisterRouter.scala:87:24] wire _out_T_11632 = ~out_wimask_1208; // @[RegisterRouter.scala:87:24] wire _out_T_11633 = ~out_romask_1208; // @[RegisterRouter.scala:87:24] wire _out_T_11634 = ~out_womask_1208; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1037 = {hi_444, flags_0_go, _out_prepend_T_1037}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11635 = out_prepend_1037; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11636 = _out_T_11635; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1038 = _out_T_11636; // @[RegisterRouter.scala:87:24] wire out_rimask_1209 = |_out_rimask_T_1209; // @[RegisterRouter.scala:87:24] wire out_wimask_1209 = &_out_wimask_T_1209; // @[RegisterRouter.scala:87:24] wire out_romask_1209 = |_out_romask_T_1209; // @[RegisterRouter.scala:87:24] wire out_womask_1209 = &_out_womask_T_1209; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1209 = out_rivalid_1_1063 & out_rimask_1209; // @[RegisterRouter.scala:87:24] wire _out_T_11638 = out_f_rivalid_1209; // @[RegisterRouter.scala:87:24] wire out_f_roready_1209 = out_roready_1_1063 & out_romask_1209; // @[RegisterRouter.scala:87:24] wire _out_T_11639 = out_f_roready_1209; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1209 = out_wivalid_1_1063 & out_wimask_1209; // @[RegisterRouter.scala:87:24] wire out_f_woready_1209 = out_woready_1_1063 & out_womask_1209; // @[RegisterRouter.scala:87:24] wire _out_T_11640 = ~out_rimask_1209; // @[RegisterRouter.scala:87:24] wire _out_T_11641 = ~out_wimask_1209; // @[RegisterRouter.scala:87:24] wire _out_T_11642 = ~out_romask_1209; // @[RegisterRouter.scala:87:24] wire _out_T_11643 = ~out_womask_1209; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1038 = {hi_445, flags_0_go, _out_prepend_T_1038}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11644 = out_prepend_1038; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11645 = _out_T_11644; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1039 = _out_T_11645; // @[RegisterRouter.scala:87:24] wire out_rimask_1210 = |_out_rimask_T_1210; // @[RegisterRouter.scala:87:24] wire out_wimask_1210 = &_out_wimask_T_1210; // @[RegisterRouter.scala:87:24] wire out_romask_1210 = |_out_romask_T_1210; // @[RegisterRouter.scala:87:24] wire out_womask_1210 = &_out_womask_T_1210; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1210 = out_rivalid_1_1064 & out_rimask_1210; // @[RegisterRouter.scala:87:24] wire _out_T_11647 = out_f_rivalid_1210; // @[RegisterRouter.scala:87:24] wire out_f_roready_1210 = out_roready_1_1064 & out_romask_1210; // @[RegisterRouter.scala:87:24] wire _out_T_11648 = out_f_roready_1210; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1210 = out_wivalid_1_1064 & out_wimask_1210; // @[RegisterRouter.scala:87:24] wire out_f_woready_1210 = out_woready_1_1064 & out_womask_1210; // @[RegisterRouter.scala:87:24] wire _out_T_11649 = ~out_rimask_1210; // @[RegisterRouter.scala:87:24] wire _out_T_11650 = ~out_wimask_1210; // @[RegisterRouter.scala:87:24] wire _out_T_11651 = ~out_romask_1210; // @[RegisterRouter.scala:87:24] wire _out_T_11652 = ~out_womask_1210; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1039 = {hi_446, flags_0_go, _out_prepend_T_1039}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11653 = out_prepend_1039; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11654 = _out_T_11653; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1040 = _out_T_11654; // @[RegisterRouter.scala:87:24] wire out_rimask_1211 = |_out_rimask_T_1211; // @[RegisterRouter.scala:87:24] wire out_wimask_1211 = &_out_wimask_T_1211; // @[RegisterRouter.scala:87:24] wire out_romask_1211 = |_out_romask_T_1211; // @[RegisterRouter.scala:87:24] wire out_womask_1211 = &_out_womask_T_1211; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1211 = out_rivalid_1_1065 & out_rimask_1211; // @[RegisterRouter.scala:87:24] wire _out_T_11656 = out_f_rivalid_1211; // @[RegisterRouter.scala:87:24] wire out_f_roready_1211 = out_roready_1_1065 & out_romask_1211; // @[RegisterRouter.scala:87:24] wire _out_T_11657 = out_f_roready_1211; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1211 = out_wivalid_1_1065 & out_wimask_1211; // @[RegisterRouter.scala:87:24] wire out_f_woready_1211 = out_woready_1_1065 & out_womask_1211; // @[RegisterRouter.scala:87:24] wire _out_T_11658 = ~out_rimask_1211; // @[RegisterRouter.scala:87:24] wire _out_T_11659 = ~out_wimask_1211; // @[RegisterRouter.scala:87:24] wire _out_T_11660 = ~out_romask_1211; // @[RegisterRouter.scala:87:24] wire _out_T_11661 = ~out_womask_1211; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1040 = {hi_447, flags_0_go, _out_prepend_T_1040}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11662 = out_prepend_1040; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11663 = _out_T_11662; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1041 = _out_T_11663; // @[RegisterRouter.scala:87:24] wire out_rimask_1212 = |_out_rimask_T_1212; // @[RegisterRouter.scala:87:24] wire out_wimask_1212 = &_out_wimask_T_1212; // @[RegisterRouter.scala:87:24] wire out_romask_1212 = |_out_romask_T_1212; // @[RegisterRouter.scala:87:24] wire out_womask_1212 = &_out_womask_T_1212; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1212 = out_rivalid_1_1066 & out_rimask_1212; // @[RegisterRouter.scala:87:24] wire _out_T_11665 = out_f_rivalid_1212; // @[RegisterRouter.scala:87:24] wire out_f_roready_1212 = out_roready_1_1066 & out_romask_1212; // @[RegisterRouter.scala:87:24] wire _out_T_11666 = out_f_roready_1212; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1212 = out_wivalid_1_1066 & out_wimask_1212; // @[RegisterRouter.scala:87:24] wire out_f_woready_1212 = out_woready_1_1066 & out_womask_1212; // @[RegisterRouter.scala:87:24] wire _out_T_11667 = ~out_rimask_1212; // @[RegisterRouter.scala:87:24] wire _out_T_11668 = ~out_wimask_1212; // @[RegisterRouter.scala:87:24] wire _out_T_11669 = ~out_romask_1212; // @[RegisterRouter.scala:87:24] wire _out_T_11670 = ~out_womask_1212; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1041 = {hi_448, flags_0_go, _out_prepend_T_1041}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11671 = out_prepend_1041; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11672 = _out_T_11671; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_183 = _out_T_11672; // @[MuxLiteral.scala:49:48] wire out_rimask_1213 = |_out_rimask_T_1213; // @[RegisterRouter.scala:87:24] wire out_wimask_1213 = &_out_wimask_T_1213; // @[RegisterRouter.scala:87:24] wire out_romask_1213 = |_out_romask_T_1213; // @[RegisterRouter.scala:87:24] wire out_womask_1213 = &_out_womask_T_1213; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1213 = out_rivalid_1_1067 & out_rimask_1213; // @[RegisterRouter.scala:87:24] wire _out_T_11674 = out_f_rivalid_1213; // @[RegisterRouter.scala:87:24] wire out_f_roready_1213 = out_roready_1_1067 & out_romask_1213; // @[RegisterRouter.scala:87:24] wire _out_T_11675 = out_f_roready_1213; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1213 = out_wivalid_1_1067 & out_wimask_1213; // @[RegisterRouter.scala:87:24] wire out_f_woready_1213 = out_woready_1_1067 & out_womask_1213; // @[RegisterRouter.scala:87:24] wire _out_T_11676 = ~out_rimask_1213; // @[RegisterRouter.scala:87:24] wire _out_T_11677 = ~out_wimask_1213; // @[RegisterRouter.scala:87:24] wire _out_T_11678 = ~out_romask_1213; // @[RegisterRouter.scala:87:24] wire _out_T_11679 = ~out_womask_1213; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11681 = _out_T_11680; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1042 = _out_T_11681; // @[RegisterRouter.scala:87:24] wire out_rimask_1214 = |_out_rimask_T_1214; // @[RegisterRouter.scala:87:24] wire out_wimask_1214 = &_out_wimask_T_1214; // @[RegisterRouter.scala:87:24] wire out_romask_1214 = |_out_romask_T_1214; // @[RegisterRouter.scala:87:24] wire out_womask_1214 = &_out_womask_T_1214; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1214 = out_rivalid_1_1068 & out_rimask_1214; // @[RegisterRouter.scala:87:24] wire _out_T_11683 = out_f_rivalid_1214; // @[RegisterRouter.scala:87:24] wire out_f_roready_1214 = out_roready_1_1068 & out_romask_1214; // @[RegisterRouter.scala:87:24] wire _out_T_11684 = out_f_roready_1214; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1214 = out_wivalid_1_1068 & out_wimask_1214; // @[RegisterRouter.scala:87:24] wire out_f_woready_1214 = out_woready_1_1068 & out_womask_1214; // @[RegisterRouter.scala:87:24] wire _out_T_11685 = ~out_rimask_1214; // @[RegisterRouter.scala:87:24] wire _out_T_11686 = ~out_wimask_1214; // @[RegisterRouter.scala:87:24] wire _out_T_11687 = ~out_romask_1214; // @[RegisterRouter.scala:87:24] wire _out_T_11688 = ~out_womask_1214; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1042 = {hi_322, flags_0_go, _out_prepend_T_1042}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11689 = out_prepend_1042; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11690 = _out_T_11689; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1043 = _out_T_11690; // @[RegisterRouter.scala:87:24] wire out_rimask_1215 = |_out_rimask_T_1215; // @[RegisterRouter.scala:87:24] wire out_wimask_1215 = &_out_wimask_T_1215; // @[RegisterRouter.scala:87:24] wire out_romask_1215 = |_out_romask_T_1215; // @[RegisterRouter.scala:87:24] wire out_womask_1215 = &_out_womask_T_1215; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1215 = out_rivalid_1_1069 & out_rimask_1215; // @[RegisterRouter.scala:87:24] wire _out_T_11692 = out_f_rivalid_1215; // @[RegisterRouter.scala:87:24] wire out_f_roready_1215 = out_roready_1_1069 & out_romask_1215; // @[RegisterRouter.scala:87:24] wire _out_T_11693 = out_f_roready_1215; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1215 = out_wivalid_1_1069 & out_wimask_1215; // @[RegisterRouter.scala:87:24] wire out_f_woready_1215 = out_woready_1_1069 & out_womask_1215; // @[RegisterRouter.scala:87:24] wire _out_T_11694 = ~out_rimask_1215; // @[RegisterRouter.scala:87:24] wire _out_T_11695 = ~out_wimask_1215; // @[RegisterRouter.scala:87:24] wire _out_T_11696 = ~out_romask_1215; // @[RegisterRouter.scala:87:24] wire _out_T_11697 = ~out_womask_1215; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1043 = {hi_323, flags_0_go, _out_prepend_T_1043}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11698 = out_prepend_1043; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11699 = _out_T_11698; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1044 = _out_T_11699; // @[RegisterRouter.scala:87:24] wire out_rimask_1216 = |_out_rimask_T_1216; // @[RegisterRouter.scala:87:24] wire out_wimask_1216 = &_out_wimask_T_1216; // @[RegisterRouter.scala:87:24] wire out_romask_1216 = |_out_romask_T_1216; // @[RegisterRouter.scala:87:24] wire out_womask_1216 = &_out_womask_T_1216; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1216 = out_rivalid_1_1070 & out_rimask_1216; // @[RegisterRouter.scala:87:24] wire _out_T_11701 = out_f_rivalid_1216; // @[RegisterRouter.scala:87:24] wire out_f_roready_1216 = out_roready_1_1070 & out_romask_1216; // @[RegisterRouter.scala:87:24] wire _out_T_11702 = out_f_roready_1216; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1216 = out_wivalid_1_1070 & out_wimask_1216; // @[RegisterRouter.scala:87:24] wire out_f_woready_1216 = out_woready_1_1070 & out_womask_1216; // @[RegisterRouter.scala:87:24] wire _out_T_11703 = ~out_rimask_1216; // @[RegisterRouter.scala:87:24] wire _out_T_11704 = ~out_wimask_1216; // @[RegisterRouter.scala:87:24] wire _out_T_11705 = ~out_romask_1216; // @[RegisterRouter.scala:87:24] wire _out_T_11706 = ~out_womask_1216; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1044 = {hi_324, flags_0_go, _out_prepend_T_1044}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11707 = out_prepend_1044; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11708 = _out_T_11707; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1045 = _out_T_11708; // @[RegisterRouter.scala:87:24] wire out_rimask_1217 = |_out_rimask_T_1217; // @[RegisterRouter.scala:87:24] wire out_wimask_1217 = &_out_wimask_T_1217; // @[RegisterRouter.scala:87:24] wire out_romask_1217 = |_out_romask_T_1217; // @[RegisterRouter.scala:87:24] wire out_womask_1217 = &_out_womask_T_1217; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1217 = out_rivalid_1_1071 & out_rimask_1217; // @[RegisterRouter.scala:87:24] wire _out_T_11710 = out_f_rivalid_1217; // @[RegisterRouter.scala:87:24] wire out_f_roready_1217 = out_roready_1_1071 & out_romask_1217; // @[RegisterRouter.scala:87:24] wire _out_T_11711 = out_f_roready_1217; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1217 = out_wivalid_1_1071 & out_wimask_1217; // @[RegisterRouter.scala:87:24] wire out_f_woready_1217 = out_woready_1_1071 & out_womask_1217; // @[RegisterRouter.scala:87:24] wire _out_T_11712 = ~out_rimask_1217; // @[RegisterRouter.scala:87:24] wire _out_T_11713 = ~out_wimask_1217; // @[RegisterRouter.scala:87:24] wire _out_T_11714 = ~out_romask_1217; // @[RegisterRouter.scala:87:24] wire _out_T_11715 = ~out_womask_1217; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1045 = {hi_325, flags_0_go, _out_prepend_T_1045}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11716 = out_prepend_1045; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11717 = _out_T_11716; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1046 = _out_T_11717; // @[RegisterRouter.scala:87:24] wire out_rimask_1218 = |_out_rimask_T_1218; // @[RegisterRouter.scala:87:24] wire out_wimask_1218 = &_out_wimask_T_1218; // @[RegisterRouter.scala:87:24] wire out_romask_1218 = |_out_romask_T_1218; // @[RegisterRouter.scala:87:24] wire out_womask_1218 = &_out_womask_T_1218; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1218 = out_rivalid_1_1072 & out_rimask_1218; // @[RegisterRouter.scala:87:24] wire _out_T_11719 = out_f_rivalid_1218; // @[RegisterRouter.scala:87:24] wire out_f_roready_1218 = out_roready_1_1072 & out_romask_1218; // @[RegisterRouter.scala:87:24] wire _out_T_11720 = out_f_roready_1218; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1218 = out_wivalid_1_1072 & out_wimask_1218; // @[RegisterRouter.scala:87:24] wire out_f_woready_1218 = out_woready_1_1072 & out_womask_1218; // @[RegisterRouter.scala:87:24] wire _out_T_11721 = ~out_rimask_1218; // @[RegisterRouter.scala:87:24] wire _out_T_11722 = ~out_wimask_1218; // @[RegisterRouter.scala:87:24] wire _out_T_11723 = ~out_romask_1218; // @[RegisterRouter.scala:87:24] wire _out_T_11724 = ~out_womask_1218; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1046 = {hi_326, flags_0_go, _out_prepend_T_1046}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11725 = out_prepend_1046; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11726 = _out_T_11725; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1047 = _out_T_11726; // @[RegisterRouter.scala:87:24] wire out_rimask_1219 = |_out_rimask_T_1219; // @[RegisterRouter.scala:87:24] wire out_wimask_1219 = &_out_wimask_T_1219; // @[RegisterRouter.scala:87:24] wire out_romask_1219 = |_out_romask_T_1219; // @[RegisterRouter.scala:87:24] wire out_womask_1219 = &_out_womask_T_1219; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1219 = out_rivalid_1_1073 & out_rimask_1219; // @[RegisterRouter.scala:87:24] wire _out_T_11728 = out_f_rivalid_1219; // @[RegisterRouter.scala:87:24] wire out_f_roready_1219 = out_roready_1_1073 & out_romask_1219; // @[RegisterRouter.scala:87:24] wire _out_T_11729 = out_f_roready_1219; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1219 = out_wivalid_1_1073 & out_wimask_1219; // @[RegisterRouter.scala:87:24] wire out_f_woready_1219 = out_woready_1_1073 & out_womask_1219; // @[RegisterRouter.scala:87:24] wire _out_T_11730 = ~out_rimask_1219; // @[RegisterRouter.scala:87:24] wire _out_T_11731 = ~out_wimask_1219; // @[RegisterRouter.scala:87:24] wire _out_T_11732 = ~out_romask_1219; // @[RegisterRouter.scala:87:24] wire _out_T_11733 = ~out_womask_1219; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1047 = {hi_327, flags_0_go, _out_prepend_T_1047}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11734 = out_prepend_1047; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11735 = _out_T_11734; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1048 = _out_T_11735; // @[RegisterRouter.scala:87:24] wire out_rimask_1220 = |_out_rimask_T_1220; // @[RegisterRouter.scala:87:24] wire out_wimask_1220 = &_out_wimask_T_1220; // @[RegisterRouter.scala:87:24] wire out_romask_1220 = |_out_romask_T_1220; // @[RegisterRouter.scala:87:24] wire out_womask_1220 = &_out_womask_T_1220; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1220 = out_rivalid_1_1074 & out_rimask_1220; // @[RegisterRouter.scala:87:24] wire _out_T_11737 = out_f_rivalid_1220; // @[RegisterRouter.scala:87:24] wire out_f_roready_1220 = out_roready_1_1074 & out_romask_1220; // @[RegisterRouter.scala:87:24] wire _out_T_11738 = out_f_roready_1220; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1220 = out_wivalid_1_1074 & out_wimask_1220; // @[RegisterRouter.scala:87:24] wire out_f_woready_1220 = out_woready_1_1074 & out_womask_1220; // @[RegisterRouter.scala:87:24] wire _out_T_11739 = ~out_rimask_1220; // @[RegisterRouter.scala:87:24] wire _out_T_11740 = ~out_wimask_1220; // @[RegisterRouter.scala:87:24] wire _out_T_11741 = ~out_romask_1220; // @[RegisterRouter.scala:87:24] wire _out_T_11742 = ~out_womask_1220; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1048 = {hi_328, flags_0_go, _out_prepend_T_1048}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11743 = out_prepend_1048; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11744 = _out_T_11743; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_168 = _out_T_11744; // @[MuxLiteral.scala:49:48] wire out_rimask_1221 = |_out_rimask_T_1221; // @[RegisterRouter.scala:87:24] wire out_wimask_1221 = &_out_wimask_T_1221; // @[RegisterRouter.scala:87:24] wire out_romask_1221 = |_out_romask_T_1221; // @[RegisterRouter.scala:87:24] wire out_womask_1221 = &_out_womask_T_1221; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1221 = out_rivalid_1_1075 & out_rimask_1221; // @[RegisterRouter.scala:87:24] wire _out_T_11746 = out_f_rivalid_1221; // @[RegisterRouter.scala:87:24] wire out_f_roready_1221 = out_roready_1_1075 & out_romask_1221; // @[RegisterRouter.scala:87:24] wire _out_T_11747 = out_f_roready_1221; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1221 = out_wivalid_1_1075 & out_wimask_1221; // @[RegisterRouter.scala:87:24] wire out_f_woready_1221 = out_woready_1_1075 & out_womask_1221; // @[RegisterRouter.scala:87:24] wire _out_T_11748 = ~out_rimask_1221; // @[RegisterRouter.scala:87:24] wire _out_T_11749 = ~out_wimask_1221; // @[RegisterRouter.scala:87:24] wire _out_T_11750 = ~out_romask_1221; // @[RegisterRouter.scala:87:24] wire _out_T_11751 = ~out_womask_1221; // @[RegisterRouter.scala:87:24] wire out_rimask_1222 = |_out_rimask_T_1222; // @[RegisterRouter.scala:87:24] wire out_wimask_1222 = &_out_wimask_T_1222; // @[RegisterRouter.scala:87:24] wire out_romask_1222 = |_out_romask_T_1222; // @[RegisterRouter.scala:87:24] wire out_womask_1222 = &_out_womask_T_1222; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1222 = out_rivalid_1_1076 & out_rimask_1222; // @[RegisterRouter.scala:87:24] wire _out_T_11755 = out_f_rivalid_1222; // @[RegisterRouter.scala:87:24] wire out_f_roready_1222 = out_roready_1_1076 & out_romask_1222; // @[RegisterRouter.scala:87:24] wire _out_T_11756 = out_f_roready_1222; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1222 = out_wivalid_1_1076 & out_wimask_1222; // @[RegisterRouter.scala:87:24] wire out_f_woready_1222 = out_woready_1_1076 & out_womask_1222; // @[RegisterRouter.scala:87:24] wire _out_T_11757 = ~out_rimask_1222; // @[RegisterRouter.scala:87:24] wire _out_T_11758 = ~out_wimask_1222; // @[RegisterRouter.scala:87:24] wire _out_T_11759 = ~out_romask_1222; // @[RegisterRouter.scala:87:24] wire _out_T_11760 = ~out_womask_1222; // @[RegisterRouter.scala:87:24] wire out_rimask_1223 = |_out_rimask_T_1223; // @[RegisterRouter.scala:87:24] wire out_wimask_1223 = &_out_wimask_T_1223; // @[RegisterRouter.scala:87:24] wire out_romask_1223 = |_out_romask_T_1223; // @[RegisterRouter.scala:87:24] wire out_womask_1223 = &_out_womask_T_1223; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1223 = out_rivalid_1_1077 & out_rimask_1223; // @[RegisterRouter.scala:87:24] wire _out_T_11764 = out_f_rivalid_1223; // @[RegisterRouter.scala:87:24] wire out_f_roready_1223 = out_roready_1_1077 & out_romask_1223; // @[RegisterRouter.scala:87:24] wire _out_T_11765 = out_f_roready_1223; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1223 = out_wivalid_1_1077 & out_wimask_1223; // @[RegisterRouter.scala:87:24] wire out_f_woready_1223 = out_woready_1_1077 & out_womask_1223; // @[RegisterRouter.scala:87:24] wire _out_T_11766 = ~out_rimask_1223; // @[RegisterRouter.scala:87:24] wire _out_T_11767 = ~out_wimask_1223; // @[RegisterRouter.scala:87:24] wire _out_T_11768 = ~out_romask_1223; // @[RegisterRouter.scala:87:24] wire _out_T_11769 = ~out_womask_1223; // @[RegisterRouter.scala:87:24] wire out_rimask_1224 = |_out_rimask_T_1224; // @[RegisterRouter.scala:87:24] wire out_wimask_1224 = &_out_wimask_T_1224; // @[RegisterRouter.scala:87:24] wire out_romask_1224 = |_out_romask_T_1224; // @[RegisterRouter.scala:87:24] wire out_womask_1224 = &_out_womask_T_1224; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1224 = out_rivalid_1_1078 & out_rimask_1224; // @[RegisterRouter.scala:87:24] wire _out_T_11773 = out_f_rivalid_1224; // @[RegisterRouter.scala:87:24] wire out_f_roready_1224 = out_roready_1_1078 & out_romask_1224; // @[RegisterRouter.scala:87:24] wire _out_T_11774 = out_f_roready_1224; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1224 = out_wivalid_1_1078 & out_wimask_1224; // @[RegisterRouter.scala:87:24] wire out_f_woready_1224 = out_woready_1_1078 & out_womask_1224; // @[RegisterRouter.scala:87:24] wire _out_T_11775 = ~out_rimask_1224; // @[RegisterRouter.scala:87:24] wire _out_T_11776 = ~out_wimask_1224; // @[RegisterRouter.scala:87:24] wire _out_T_11777 = ~out_romask_1224; // @[RegisterRouter.scala:87:24] wire _out_T_11778 = ~out_womask_1224; // @[RegisterRouter.scala:87:24] wire out_rimask_1225 = |_out_rimask_T_1225; // @[RegisterRouter.scala:87:24] wire out_wimask_1225 = &_out_wimask_T_1225; // @[RegisterRouter.scala:87:24] wire out_romask_1225 = |_out_romask_T_1225; // @[RegisterRouter.scala:87:24] wire out_womask_1225 = &_out_womask_T_1225; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1225 = out_rivalid_1_1079 & out_rimask_1225; // @[RegisterRouter.scala:87:24] wire _out_T_11782 = out_f_rivalid_1225; // @[RegisterRouter.scala:87:24] wire out_f_roready_1225 = out_roready_1_1079 & out_romask_1225; // @[RegisterRouter.scala:87:24] wire _out_T_11783 = out_f_roready_1225; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1225 = out_wivalid_1_1079 & out_wimask_1225; // @[RegisterRouter.scala:87:24] wire out_f_woready_1225 = out_woready_1_1079 & out_womask_1225; // @[RegisterRouter.scala:87:24] wire _out_T_11784 = ~out_rimask_1225; // @[RegisterRouter.scala:87:24] wire _out_T_11785 = ~out_wimask_1225; // @[RegisterRouter.scala:87:24] wire _out_T_11786 = ~out_romask_1225; // @[RegisterRouter.scala:87:24] wire _out_T_11787 = ~out_womask_1225; // @[RegisterRouter.scala:87:24] wire out_rimask_1226 = |_out_rimask_T_1226; // @[RegisterRouter.scala:87:24] wire out_wimask_1226 = &_out_wimask_T_1226; // @[RegisterRouter.scala:87:24] wire out_romask_1226 = |_out_romask_T_1226; // @[RegisterRouter.scala:87:24] wire out_womask_1226 = &_out_womask_T_1226; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1226 = out_rivalid_1_1080 & out_rimask_1226; // @[RegisterRouter.scala:87:24] wire _out_T_11791 = out_f_rivalid_1226; // @[RegisterRouter.scala:87:24] wire out_f_roready_1226 = out_roready_1_1080 & out_romask_1226; // @[RegisterRouter.scala:87:24] wire _out_T_11792 = out_f_roready_1226; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1226 = out_wivalid_1_1080 & out_wimask_1226; // @[RegisterRouter.scala:87:24] wire out_f_woready_1226 = out_woready_1_1080 & out_womask_1226; // @[RegisterRouter.scala:87:24] wire _out_T_11793 = ~out_rimask_1226; // @[RegisterRouter.scala:87:24] wire _out_T_11794 = ~out_wimask_1226; // @[RegisterRouter.scala:87:24] wire _out_T_11795 = ~out_romask_1226; // @[RegisterRouter.scala:87:24] wire _out_T_11796 = ~out_womask_1226; // @[RegisterRouter.scala:87:24] wire out_rimask_1227 = |_out_rimask_T_1227; // @[RegisterRouter.scala:87:24] wire out_wimask_1227 = &_out_wimask_T_1227; // @[RegisterRouter.scala:87:24] wire out_romask_1227 = |_out_romask_T_1227; // @[RegisterRouter.scala:87:24] wire out_womask_1227 = &_out_womask_T_1227; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1227 = out_rivalid_1_1081 & out_rimask_1227; // @[RegisterRouter.scala:87:24] wire _out_T_11800 = out_f_rivalid_1227; // @[RegisterRouter.scala:87:24] wire out_f_roready_1227 = out_roready_1_1081 & out_romask_1227; // @[RegisterRouter.scala:87:24] wire _out_T_11801 = out_f_roready_1227; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1227 = out_wivalid_1_1081 & out_wimask_1227; // @[RegisterRouter.scala:87:24] wire out_f_woready_1227 = out_woready_1_1081 & out_womask_1227; // @[RegisterRouter.scala:87:24] wire _out_T_11802 = ~out_rimask_1227; // @[RegisterRouter.scala:87:24] wire _out_T_11803 = ~out_wimask_1227; // @[RegisterRouter.scala:87:24] wire _out_T_11804 = ~out_romask_1227; // @[RegisterRouter.scala:87:24] wire _out_T_11805 = ~out_womask_1227; // @[RegisterRouter.scala:87:24] wire out_rimask_1228 = |_out_rimask_T_1228; // @[RegisterRouter.scala:87:24] wire out_wimask_1228 = &_out_wimask_T_1228; // @[RegisterRouter.scala:87:24] wire out_romask_1228 = |_out_romask_T_1228; // @[RegisterRouter.scala:87:24] wire out_womask_1228 = &_out_womask_T_1228; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1228 = out_rivalid_1_1082 & out_rimask_1228; // @[RegisterRouter.scala:87:24] wire _out_T_11809 = out_f_rivalid_1228; // @[RegisterRouter.scala:87:24] wire out_f_roready_1228 = out_roready_1_1082 & out_romask_1228; // @[RegisterRouter.scala:87:24] wire _out_T_11810 = out_f_roready_1228; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1228 = out_wivalid_1_1082 & out_wimask_1228; // @[RegisterRouter.scala:87:24] wire out_f_woready_1228 = out_woready_1_1082 & out_womask_1228; // @[RegisterRouter.scala:87:24] wire _out_T_11811 = ~out_rimask_1228; // @[RegisterRouter.scala:87:24] wire _out_T_11812 = ~out_wimask_1228; // @[RegisterRouter.scala:87:24] wire _out_T_11813 = ~out_romask_1228; // @[RegisterRouter.scala:87:24] wire _out_T_11814 = ~out_womask_1228; // @[RegisterRouter.scala:87:24] wire out_rimask_1229 = |_out_rimask_T_1229; // @[RegisterRouter.scala:87:24] wire out_wimask_1229 = &_out_wimask_T_1229; // @[RegisterRouter.scala:87:24] wire out_romask_1229 = |_out_romask_T_1229; // @[RegisterRouter.scala:87:24] wire out_womask_1229 = &_out_womask_T_1229; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1229 = out_rivalid_1_1083 & out_rimask_1229; // @[RegisterRouter.scala:87:24] wire _out_T_11818 = out_f_rivalid_1229; // @[RegisterRouter.scala:87:24] wire out_f_roready_1229 = out_roready_1_1083 & out_romask_1229; // @[RegisterRouter.scala:87:24] wire _out_T_11819 = out_f_roready_1229; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1229 = out_wivalid_1_1083 & out_wimask_1229; // @[RegisterRouter.scala:87:24] wire out_f_woready_1229 = out_woready_1_1083 & out_womask_1229; // @[RegisterRouter.scala:87:24] wire _out_T_11820 = ~out_rimask_1229; // @[RegisterRouter.scala:87:24] wire _out_T_11821 = ~out_wimask_1229; // @[RegisterRouter.scala:87:24] wire _out_T_11822 = ~out_romask_1229; // @[RegisterRouter.scala:87:24] wire _out_T_11823 = ~out_womask_1229; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11825 = _out_T_11824; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1056 = _out_T_11825; // @[RegisterRouter.scala:87:24] wire out_rimask_1230 = |_out_rimask_T_1230; // @[RegisterRouter.scala:87:24] wire out_wimask_1230 = &_out_wimask_T_1230; // @[RegisterRouter.scala:87:24] wire out_romask_1230 = |_out_romask_T_1230; // @[RegisterRouter.scala:87:24] wire out_womask_1230 = &_out_womask_T_1230; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1230 = out_rivalid_1_1084 & out_rimask_1230; // @[RegisterRouter.scala:87:24] wire _out_T_11827 = out_f_rivalid_1230; // @[RegisterRouter.scala:87:24] wire out_f_roready_1230 = out_roready_1_1084 & out_romask_1230; // @[RegisterRouter.scala:87:24] wire _out_T_11828 = out_f_roready_1230; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1230 = out_wivalid_1_1084 & out_wimask_1230; // @[RegisterRouter.scala:87:24] wire out_f_woready_1230 = out_woready_1_1084 & out_womask_1230; // @[RegisterRouter.scala:87:24] wire _out_T_11829 = ~out_rimask_1230; // @[RegisterRouter.scala:87:24] wire _out_T_11830 = ~out_wimask_1230; // @[RegisterRouter.scala:87:24] wire _out_T_11831 = ~out_romask_1230; // @[RegisterRouter.scala:87:24] wire _out_T_11832 = ~out_womask_1230; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1056 = {hi_658, flags_0_go, _out_prepend_T_1056}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11833 = out_prepend_1056; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11834 = _out_T_11833; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1057 = _out_T_11834; // @[RegisterRouter.scala:87:24] wire out_rimask_1231 = |_out_rimask_T_1231; // @[RegisterRouter.scala:87:24] wire out_wimask_1231 = &_out_wimask_T_1231; // @[RegisterRouter.scala:87:24] wire out_romask_1231 = |_out_romask_T_1231; // @[RegisterRouter.scala:87:24] wire out_womask_1231 = &_out_womask_T_1231; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1231 = out_rivalid_1_1085 & out_rimask_1231; // @[RegisterRouter.scala:87:24] wire _out_T_11836 = out_f_rivalid_1231; // @[RegisterRouter.scala:87:24] wire out_f_roready_1231 = out_roready_1_1085 & out_romask_1231; // @[RegisterRouter.scala:87:24] wire _out_T_11837 = out_f_roready_1231; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1231 = out_wivalid_1_1085 & out_wimask_1231; // @[RegisterRouter.scala:87:24] wire out_f_woready_1231 = out_woready_1_1085 & out_womask_1231; // @[RegisterRouter.scala:87:24] wire _out_T_11838 = ~out_rimask_1231; // @[RegisterRouter.scala:87:24] wire _out_T_11839 = ~out_wimask_1231; // @[RegisterRouter.scala:87:24] wire _out_T_11840 = ~out_romask_1231; // @[RegisterRouter.scala:87:24] wire _out_T_11841 = ~out_womask_1231; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1057 = {hi_659, flags_0_go, _out_prepend_T_1057}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11842 = out_prepend_1057; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11843 = _out_T_11842; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1058 = _out_T_11843; // @[RegisterRouter.scala:87:24] wire out_rimask_1232 = |_out_rimask_T_1232; // @[RegisterRouter.scala:87:24] wire out_wimask_1232 = &_out_wimask_T_1232; // @[RegisterRouter.scala:87:24] wire out_romask_1232 = |_out_romask_T_1232; // @[RegisterRouter.scala:87:24] wire out_womask_1232 = &_out_womask_T_1232; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1232 = out_rivalid_1_1086 & out_rimask_1232; // @[RegisterRouter.scala:87:24] wire _out_T_11845 = out_f_rivalid_1232; // @[RegisterRouter.scala:87:24] wire out_f_roready_1232 = out_roready_1_1086 & out_romask_1232; // @[RegisterRouter.scala:87:24] wire _out_T_11846 = out_f_roready_1232; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1232 = out_wivalid_1_1086 & out_wimask_1232; // @[RegisterRouter.scala:87:24] wire out_f_woready_1232 = out_woready_1_1086 & out_womask_1232; // @[RegisterRouter.scala:87:24] wire _out_T_11847 = ~out_rimask_1232; // @[RegisterRouter.scala:87:24] wire _out_T_11848 = ~out_wimask_1232; // @[RegisterRouter.scala:87:24] wire _out_T_11849 = ~out_romask_1232; // @[RegisterRouter.scala:87:24] wire _out_T_11850 = ~out_womask_1232; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1058 = {hi_660, flags_0_go, _out_prepend_T_1058}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11851 = out_prepend_1058; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11852 = _out_T_11851; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1059 = _out_T_11852; // @[RegisterRouter.scala:87:24] wire out_rimask_1233 = |_out_rimask_T_1233; // @[RegisterRouter.scala:87:24] wire out_wimask_1233 = &_out_wimask_T_1233; // @[RegisterRouter.scala:87:24] wire out_romask_1233 = |_out_romask_T_1233; // @[RegisterRouter.scala:87:24] wire out_womask_1233 = &_out_womask_T_1233; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1233 = out_rivalid_1_1087 & out_rimask_1233; // @[RegisterRouter.scala:87:24] wire _out_T_11854 = out_f_rivalid_1233; // @[RegisterRouter.scala:87:24] wire out_f_roready_1233 = out_roready_1_1087 & out_romask_1233; // @[RegisterRouter.scala:87:24] wire _out_T_11855 = out_f_roready_1233; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1233 = out_wivalid_1_1087 & out_wimask_1233; // @[RegisterRouter.scala:87:24] wire out_f_woready_1233 = out_woready_1_1087 & out_womask_1233; // @[RegisterRouter.scala:87:24] wire _out_T_11856 = ~out_rimask_1233; // @[RegisterRouter.scala:87:24] wire _out_T_11857 = ~out_wimask_1233; // @[RegisterRouter.scala:87:24] wire _out_T_11858 = ~out_romask_1233; // @[RegisterRouter.scala:87:24] wire _out_T_11859 = ~out_womask_1233; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1059 = {hi_661, flags_0_go, _out_prepend_T_1059}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11860 = out_prepend_1059; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11861 = _out_T_11860; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1060 = _out_T_11861; // @[RegisterRouter.scala:87:24] wire out_rimask_1234 = |_out_rimask_T_1234; // @[RegisterRouter.scala:87:24] wire out_wimask_1234 = &_out_wimask_T_1234; // @[RegisterRouter.scala:87:24] wire out_romask_1234 = |_out_romask_T_1234; // @[RegisterRouter.scala:87:24] wire out_womask_1234 = &_out_womask_T_1234; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1234 = out_rivalid_1_1088 & out_rimask_1234; // @[RegisterRouter.scala:87:24] wire _out_T_11863 = out_f_rivalid_1234; // @[RegisterRouter.scala:87:24] wire out_f_roready_1234 = out_roready_1_1088 & out_romask_1234; // @[RegisterRouter.scala:87:24] wire _out_T_11864 = out_f_roready_1234; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1234 = out_wivalid_1_1088 & out_wimask_1234; // @[RegisterRouter.scala:87:24] wire out_f_woready_1234 = out_woready_1_1088 & out_womask_1234; // @[RegisterRouter.scala:87:24] wire _out_T_11865 = ~out_rimask_1234; // @[RegisterRouter.scala:87:24] wire _out_T_11866 = ~out_wimask_1234; // @[RegisterRouter.scala:87:24] wire _out_T_11867 = ~out_romask_1234; // @[RegisterRouter.scala:87:24] wire _out_T_11868 = ~out_womask_1234; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1060 = {hi_662, flags_0_go, _out_prepend_T_1060}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11869 = out_prepend_1060; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11870 = _out_T_11869; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1061 = _out_T_11870; // @[RegisterRouter.scala:87:24] wire out_rimask_1235 = |_out_rimask_T_1235; // @[RegisterRouter.scala:87:24] wire out_wimask_1235 = &_out_wimask_T_1235; // @[RegisterRouter.scala:87:24] wire out_romask_1235 = |_out_romask_T_1235; // @[RegisterRouter.scala:87:24] wire out_womask_1235 = &_out_womask_T_1235; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1235 = out_rivalid_1_1089 & out_rimask_1235; // @[RegisterRouter.scala:87:24] wire _out_T_11872 = out_f_rivalid_1235; // @[RegisterRouter.scala:87:24] wire out_f_roready_1235 = out_roready_1_1089 & out_romask_1235; // @[RegisterRouter.scala:87:24] wire _out_T_11873 = out_f_roready_1235; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1235 = out_wivalid_1_1089 & out_wimask_1235; // @[RegisterRouter.scala:87:24] wire out_f_woready_1235 = out_woready_1_1089 & out_womask_1235; // @[RegisterRouter.scala:87:24] wire _out_T_11874 = ~out_rimask_1235; // @[RegisterRouter.scala:87:24] wire _out_T_11875 = ~out_wimask_1235; // @[RegisterRouter.scala:87:24] wire _out_T_11876 = ~out_romask_1235; // @[RegisterRouter.scala:87:24] wire _out_T_11877 = ~out_womask_1235; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1061 = {hi_663, flags_0_go, _out_prepend_T_1061}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11878 = out_prepend_1061; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11879 = _out_T_11878; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1062 = _out_T_11879; // @[RegisterRouter.scala:87:24] wire out_rimask_1236 = |_out_rimask_T_1236; // @[RegisterRouter.scala:87:24] wire out_wimask_1236 = &_out_wimask_T_1236; // @[RegisterRouter.scala:87:24] wire out_romask_1236 = |_out_romask_T_1236; // @[RegisterRouter.scala:87:24] wire out_womask_1236 = &_out_womask_T_1236; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1236 = out_rivalid_1_1090 & out_rimask_1236; // @[RegisterRouter.scala:87:24] wire _out_T_11881 = out_f_rivalid_1236; // @[RegisterRouter.scala:87:24] wire out_f_roready_1236 = out_roready_1_1090 & out_romask_1236; // @[RegisterRouter.scala:87:24] wire _out_T_11882 = out_f_roready_1236; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1236 = out_wivalid_1_1090 & out_wimask_1236; // @[RegisterRouter.scala:87:24] wire out_f_woready_1236 = out_woready_1_1090 & out_womask_1236; // @[RegisterRouter.scala:87:24] wire _out_T_11883 = ~out_rimask_1236; // @[RegisterRouter.scala:87:24] wire _out_T_11884 = ~out_wimask_1236; // @[RegisterRouter.scala:87:24] wire _out_T_11885 = ~out_romask_1236; // @[RegisterRouter.scala:87:24] wire _out_T_11886 = ~out_womask_1236; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1062 = {hi_664, flags_0_go, _out_prepend_T_1062}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11887 = out_prepend_1062; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11888 = _out_T_11887; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_210 = _out_T_11888; // @[MuxLiteral.scala:49:48] wire out_rimask_1237 = |_out_rimask_T_1237; // @[RegisterRouter.scala:87:24] wire out_wimask_1237 = &_out_wimask_T_1237; // @[RegisterRouter.scala:87:24] wire out_romask_1237 = |_out_romask_T_1237; // @[RegisterRouter.scala:87:24] wire out_womask_1237 = &_out_womask_T_1237; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1237 = out_rivalid_1_1091 & out_rimask_1237; // @[RegisterRouter.scala:87:24] wire _out_T_11890 = out_f_rivalid_1237; // @[RegisterRouter.scala:87:24] wire out_f_roready_1237 = out_roready_1_1091 & out_romask_1237; // @[RegisterRouter.scala:87:24] wire _out_T_11891 = out_f_roready_1237; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1237 = out_wivalid_1_1091 & out_wimask_1237; // @[RegisterRouter.scala:87:24] wire _out_T_11892 = out_f_wivalid_1237; // @[RegisterRouter.scala:87:24] wire out_f_woready_1237 = out_woready_1_1091 & out_womask_1237; // @[RegisterRouter.scala:87:24] wire _out_T_11893 = out_f_woready_1237; // @[RegisterRouter.scala:87:24] wire _out_T_11894 = ~out_rimask_1237; // @[RegisterRouter.scala:87:24] wire _out_T_11895 = ~out_wimask_1237; // @[RegisterRouter.scala:87:24] wire _out_T_11896 = ~out_romask_1237; // @[RegisterRouter.scala:87:24] wire _out_T_11897 = ~out_womask_1237; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11899 = _out_T_11898; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1063 = _out_T_11899; // @[RegisterRouter.scala:87:24] wire out_rimask_1238 = |_out_rimask_T_1238; // @[RegisterRouter.scala:87:24] wire out_wimask_1238 = &_out_wimask_T_1238; // @[RegisterRouter.scala:87:24] wire out_romask_1238 = |_out_romask_T_1238; // @[RegisterRouter.scala:87:24] wire out_womask_1238 = &_out_womask_T_1238; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1238 = out_rivalid_1_1092 & out_rimask_1238; // @[RegisterRouter.scala:87:24] wire _out_T_11901 = out_f_rivalid_1238; // @[RegisterRouter.scala:87:24] wire out_f_roready_1238 = out_roready_1_1092 & out_romask_1238; // @[RegisterRouter.scala:87:24] wire _out_T_11902 = out_f_roready_1238; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1238 = out_wivalid_1_1092 & out_wimask_1238; // @[RegisterRouter.scala:87:24] wire _out_T_11903 = out_f_wivalid_1238; // @[RegisterRouter.scala:87:24] wire out_f_woready_1238 = out_woready_1_1092 & out_womask_1238; // @[RegisterRouter.scala:87:24] wire _out_T_11904 = out_f_woready_1238; // @[RegisterRouter.scala:87:24] wire _out_T_11905 = ~out_rimask_1238; // @[RegisterRouter.scala:87:24] wire _out_T_11906 = ~out_wimask_1238; // @[RegisterRouter.scala:87:24] wire _out_T_11907 = ~out_romask_1238; // @[RegisterRouter.scala:87:24] wire _out_T_11908 = ~out_womask_1238; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1063 = {programBufferMem_25, _out_prepend_T_1063}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11909 = out_prepend_1063; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11910 = _out_T_11909; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1064 = _out_T_11910; // @[RegisterRouter.scala:87:24] wire out_rimask_1239 = |_out_rimask_T_1239; // @[RegisterRouter.scala:87:24] wire out_wimask_1239 = &_out_wimask_T_1239; // @[RegisterRouter.scala:87:24] wire out_romask_1239 = |_out_romask_T_1239; // @[RegisterRouter.scala:87:24] wire out_womask_1239 = &_out_womask_T_1239; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1239 = out_rivalid_1_1093 & out_rimask_1239; // @[RegisterRouter.scala:87:24] wire _out_T_11912 = out_f_rivalid_1239; // @[RegisterRouter.scala:87:24] wire out_f_roready_1239 = out_roready_1_1093 & out_romask_1239; // @[RegisterRouter.scala:87:24] wire _out_T_11913 = out_f_roready_1239; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1239 = out_wivalid_1_1093 & out_wimask_1239; // @[RegisterRouter.scala:87:24] wire _out_T_11914 = out_f_wivalid_1239; // @[RegisterRouter.scala:87:24] wire out_f_woready_1239 = out_woready_1_1093 & out_womask_1239; // @[RegisterRouter.scala:87:24] wire _out_T_11915 = out_f_woready_1239; // @[RegisterRouter.scala:87:24] wire _out_T_11916 = ~out_rimask_1239; // @[RegisterRouter.scala:87:24] wire _out_T_11917 = ~out_wimask_1239; // @[RegisterRouter.scala:87:24] wire _out_T_11918 = ~out_romask_1239; // @[RegisterRouter.scala:87:24] wire _out_T_11919 = ~out_womask_1239; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1064 = {programBufferMem_26, _out_prepend_T_1064}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11920 = out_prepend_1064; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11921 = _out_T_11920; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1065 = _out_T_11921; // @[RegisterRouter.scala:87:24] wire out_rimask_1240 = |_out_rimask_T_1240; // @[RegisterRouter.scala:87:24] wire out_wimask_1240 = &_out_wimask_T_1240; // @[RegisterRouter.scala:87:24] wire out_romask_1240 = |_out_romask_T_1240; // @[RegisterRouter.scala:87:24] wire out_womask_1240 = &_out_womask_T_1240; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1240 = out_rivalid_1_1094 & out_rimask_1240; // @[RegisterRouter.scala:87:24] wire _out_T_11923 = out_f_rivalid_1240; // @[RegisterRouter.scala:87:24] wire out_f_roready_1240 = out_roready_1_1094 & out_romask_1240; // @[RegisterRouter.scala:87:24] wire _out_T_11924 = out_f_roready_1240; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1240 = out_wivalid_1_1094 & out_wimask_1240; // @[RegisterRouter.scala:87:24] wire _out_T_11925 = out_f_wivalid_1240; // @[RegisterRouter.scala:87:24] wire out_f_woready_1240 = out_woready_1_1094 & out_womask_1240; // @[RegisterRouter.scala:87:24] wire _out_T_11926 = out_f_woready_1240; // @[RegisterRouter.scala:87:24] wire _out_T_11927 = ~out_rimask_1240; // @[RegisterRouter.scala:87:24] wire _out_T_11928 = ~out_wimask_1240; // @[RegisterRouter.scala:87:24] wire _out_T_11929 = ~out_romask_1240; // @[RegisterRouter.scala:87:24] wire _out_T_11930 = ~out_womask_1240; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1065 = {programBufferMem_27, _out_prepend_T_1065}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11931 = out_prepend_1065; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11932 = _out_T_11931; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1066 = _out_T_11932; // @[RegisterRouter.scala:87:24] wire out_rimask_1241 = |_out_rimask_T_1241; // @[RegisterRouter.scala:87:24] wire out_wimask_1241 = &_out_wimask_T_1241; // @[RegisterRouter.scala:87:24] wire out_romask_1241 = |_out_romask_T_1241; // @[RegisterRouter.scala:87:24] wire out_womask_1241 = &_out_womask_T_1241; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1241 = out_rivalid_1_1095 & out_rimask_1241; // @[RegisterRouter.scala:87:24] wire _out_T_11934 = out_f_rivalid_1241; // @[RegisterRouter.scala:87:24] wire out_f_roready_1241 = out_roready_1_1095 & out_romask_1241; // @[RegisterRouter.scala:87:24] wire _out_T_11935 = out_f_roready_1241; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1241 = out_wivalid_1_1095 & out_wimask_1241; // @[RegisterRouter.scala:87:24] wire _out_T_11936 = out_f_wivalid_1241; // @[RegisterRouter.scala:87:24] wire out_f_woready_1241 = out_woready_1_1095 & out_womask_1241; // @[RegisterRouter.scala:87:24] wire _out_T_11937 = out_f_woready_1241; // @[RegisterRouter.scala:87:24] wire _out_T_11938 = ~out_rimask_1241; // @[RegisterRouter.scala:87:24] wire _out_T_11939 = ~out_wimask_1241; // @[RegisterRouter.scala:87:24] wire _out_T_11940 = ~out_romask_1241; // @[RegisterRouter.scala:87:24] wire _out_T_11941 = ~out_womask_1241; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1066 = {programBufferMem_28, _out_prepend_T_1066}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11942 = out_prepend_1066; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11943 = _out_T_11942; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1067 = _out_T_11943; // @[RegisterRouter.scala:87:24] wire out_rimask_1242 = |_out_rimask_T_1242; // @[RegisterRouter.scala:87:24] wire out_wimask_1242 = &_out_wimask_T_1242; // @[RegisterRouter.scala:87:24] wire out_romask_1242 = |_out_romask_T_1242; // @[RegisterRouter.scala:87:24] wire out_womask_1242 = &_out_womask_T_1242; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1242 = out_rivalid_1_1096 & out_rimask_1242; // @[RegisterRouter.scala:87:24] wire _out_T_11945 = out_f_rivalid_1242; // @[RegisterRouter.scala:87:24] wire out_f_roready_1242 = out_roready_1_1096 & out_romask_1242; // @[RegisterRouter.scala:87:24] wire _out_T_11946 = out_f_roready_1242; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1242 = out_wivalid_1_1096 & out_wimask_1242; // @[RegisterRouter.scala:87:24] wire _out_T_11947 = out_f_wivalid_1242; // @[RegisterRouter.scala:87:24] wire out_f_woready_1242 = out_woready_1_1096 & out_womask_1242; // @[RegisterRouter.scala:87:24] wire _out_T_11948 = out_f_woready_1242; // @[RegisterRouter.scala:87:24] wire _out_T_11949 = ~out_rimask_1242; // @[RegisterRouter.scala:87:24] wire _out_T_11950 = ~out_wimask_1242; // @[RegisterRouter.scala:87:24] wire _out_T_11951 = ~out_romask_1242; // @[RegisterRouter.scala:87:24] wire _out_T_11952 = ~out_womask_1242; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1067 = {programBufferMem_29, _out_prepend_T_1067}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11953 = out_prepend_1067; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11954 = _out_T_11953; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1068 = _out_T_11954; // @[RegisterRouter.scala:87:24] wire out_rimask_1243 = |_out_rimask_T_1243; // @[RegisterRouter.scala:87:24] wire out_wimask_1243 = &_out_wimask_T_1243; // @[RegisterRouter.scala:87:24] wire out_romask_1243 = |_out_romask_T_1243; // @[RegisterRouter.scala:87:24] wire out_womask_1243 = &_out_womask_T_1243; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1243 = out_rivalid_1_1097 & out_rimask_1243; // @[RegisterRouter.scala:87:24] wire _out_T_11956 = out_f_rivalid_1243; // @[RegisterRouter.scala:87:24] wire out_f_roready_1243 = out_roready_1_1097 & out_romask_1243; // @[RegisterRouter.scala:87:24] wire _out_T_11957 = out_f_roready_1243; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1243 = out_wivalid_1_1097 & out_wimask_1243; // @[RegisterRouter.scala:87:24] wire _out_T_11958 = out_f_wivalid_1243; // @[RegisterRouter.scala:87:24] wire out_f_woready_1243 = out_woready_1_1097 & out_womask_1243; // @[RegisterRouter.scala:87:24] wire _out_T_11959 = out_f_woready_1243; // @[RegisterRouter.scala:87:24] wire _out_T_11960 = ~out_rimask_1243; // @[RegisterRouter.scala:87:24] wire _out_T_11961 = ~out_wimask_1243; // @[RegisterRouter.scala:87:24] wire _out_T_11962 = ~out_romask_1243; // @[RegisterRouter.scala:87:24] wire _out_T_11963 = ~out_womask_1243; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1068 = {programBufferMem_30, _out_prepend_T_1068}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11964 = out_prepend_1068; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11965 = _out_T_11964; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1069 = _out_T_11965; // @[RegisterRouter.scala:87:24] wire out_rimask_1244 = |_out_rimask_T_1244; // @[RegisterRouter.scala:87:24] wire out_wimask_1244 = &_out_wimask_T_1244; // @[RegisterRouter.scala:87:24] wire out_romask_1244 = |_out_romask_T_1244; // @[RegisterRouter.scala:87:24] wire out_womask_1244 = &_out_womask_T_1244; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1244 = out_rivalid_1_1098 & out_rimask_1244; // @[RegisterRouter.scala:87:24] wire _out_T_11967 = out_f_rivalid_1244; // @[RegisterRouter.scala:87:24] wire out_f_roready_1244 = out_roready_1_1098 & out_romask_1244; // @[RegisterRouter.scala:87:24] wire _out_T_11968 = out_f_roready_1244; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1244 = out_wivalid_1_1098 & out_wimask_1244; // @[RegisterRouter.scala:87:24] wire _out_T_11969 = out_f_wivalid_1244; // @[RegisterRouter.scala:87:24] wire out_f_woready_1244 = out_woready_1_1098 & out_womask_1244; // @[RegisterRouter.scala:87:24] wire _out_T_11970 = out_f_woready_1244; // @[RegisterRouter.scala:87:24] wire _out_T_11971 = ~out_rimask_1244; // @[RegisterRouter.scala:87:24] wire _out_T_11972 = ~out_wimask_1244; // @[RegisterRouter.scala:87:24] wire _out_T_11973 = ~out_romask_1244; // @[RegisterRouter.scala:87:24] wire _out_T_11974 = ~out_womask_1244; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1069 = {programBufferMem_31, _out_prepend_T_1069}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11975 = out_prepend_1069; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11976 = _out_T_11975; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_107 = _out_T_11976; // @[MuxLiteral.scala:49:48] wire out_rimask_1245 = |_out_rimask_T_1245; // @[RegisterRouter.scala:87:24] wire out_wimask_1245 = &_out_wimask_T_1245; // @[RegisterRouter.scala:87:24] wire out_romask_1245 = |_out_romask_T_1245; // @[RegisterRouter.scala:87:24] wire out_womask_1245 = &_out_womask_T_1245; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1245 = out_rivalid_1_1099 & out_rimask_1245; // @[RegisterRouter.scala:87:24] wire _out_T_11978 = out_f_rivalid_1245; // @[RegisterRouter.scala:87:24] wire out_f_roready_1245 = out_roready_1_1099 & out_romask_1245; // @[RegisterRouter.scala:87:24] wire _out_T_11979 = out_f_roready_1245; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1245 = out_wivalid_1_1099 & out_wimask_1245; // @[RegisterRouter.scala:87:24] wire out_f_woready_1245 = out_woready_1_1099 & out_womask_1245; // @[RegisterRouter.scala:87:24] wire _out_T_11980 = ~out_rimask_1245; // @[RegisterRouter.scala:87:24] wire _out_T_11981 = ~out_wimask_1245; // @[RegisterRouter.scala:87:24] wire _out_T_11982 = ~out_romask_1245; // @[RegisterRouter.scala:87:24] wire _out_T_11983 = ~out_womask_1245; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11985 = _out_T_11984; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1070 = _out_T_11985; // @[RegisterRouter.scala:87:24] wire out_rimask_1246 = |_out_rimask_T_1246; // @[RegisterRouter.scala:87:24] wire out_wimask_1246 = &_out_wimask_T_1246; // @[RegisterRouter.scala:87:24] wire out_romask_1246 = |_out_romask_T_1246; // @[RegisterRouter.scala:87:24] wire out_womask_1246 = &_out_womask_T_1246; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1246 = out_rivalid_1_1100 & out_rimask_1246; // @[RegisterRouter.scala:87:24] wire _out_T_11987 = out_f_rivalid_1246; // @[RegisterRouter.scala:87:24] wire out_f_roready_1246 = out_roready_1_1100 & out_romask_1246; // @[RegisterRouter.scala:87:24] wire _out_T_11988 = out_f_roready_1246; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1246 = out_wivalid_1_1100 & out_wimask_1246; // @[RegisterRouter.scala:87:24] wire out_f_woready_1246 = out_woready_1_1100 & out_womask_1246; // @[RegisterRouter.scala:87:24] wire _out_T_11989 = ~out_rimask_1246; // @[RegisterRouter.scala:87:24] wire _out_T_11990 = ~out_wimask_1246; // @[RegisterRouter.scala:87:24] wire _out_T_11991 = ~out_romask_1246; // @[RegisterRouter.scala:87:24] wire _out_T_11992 = ~out_womask_1246; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1070 = {hi_66, flags_0_go, _out_prepend_T_1070}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11993 = out_prepend_1070; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11994 = _out_T_11993; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1071 = _out_T_11994; // @[RegisterRouter.scala:87:24] wire out_rimask_1247 = |_out_rimask_T_1247; // @[RegisterRouter.scala:87:24] wire out_wimask_1247 = &_out_wimask_T_1247; // @[RegisterRouter.scala:87:24] wire out_romask_1247 = |_out_romask_T_1247; // @[RegisterRouter.scala:87:24] wire out_womask_1247 = &_out_womask_T_1247; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1247 = out_rivalid_1_1101 & out_rimask_1247; // @[RegisterRouter.scala:87:24] wire _out_T_11996 = out_f_rivalid_1247; // @[RegisterRouter.scala:87:24] wire out_f_roready_1247 = out_roready_1_1101 & out_romask_1247; // @[RegisterRouter.scala:87:24] wire _out_T_11997 = out_f_roready_1247; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1247 = out_wivalid_1_1101 & out_wimask_1247; // @[RegisterRouter.scala:87:24] wire out_f_woready_1247 = out_woready_1_1101 & out_womask_1247; // @[RegisterRouter.scala:87:24] wire _out_T_11998 = ~out_rimask_1247; // @[RegisterRouter.scala:87:24] wire _out_T_11999 = ~out_wimask_1247; // @[RegisterRouter.scala:87:24] wire _out_T_12000 = ~out_romask_1247; // @[RegisterRouter.scala:87:24] wire _out_T_12001 = ~out_womask_1247; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1071 = {hi_67, flags_0_go, _out_prepend_T_1071}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12002 = out_prepend_1071; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12003 = _out_T_12002; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1072 = _out_T_12003; // @[RegisterRouter.scala:87:24] wire out_rimask_1248 = |_out_rimask_T_1248; // @[RegisterRouter.scala:87:24] wire out_wimask_1248 = &_out_wimask_T_1248; // @[RegisterRouter.scala:87:24] wire out_romask_1248 = |_out_romask_T_1248; // @[RegisterRouter.scala:87:24] wire out_womask_1248 = &_out_womask_T_1248; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1248 = out_rivalid_1_1102 & out_rimask_1248; // @[RegisterRouter.scala:87:24] wire _out_T_12005 = out_f_rivalid_1248; // @[RegisterRouter.scala:87:24] wire out_f_roready_1248 = out_roready_1_1102 & out_romask_1248; // @[RegisterRouter.scala:87:24] wire _out_T_12006 = out_f_roready_1248; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1248 = out_wivalid_1_1102 & out_wimask_1248; // @[RegisterRouter.scala:87:24] wire out_f_woready_1248 = out_woready_1_1102 & out_womask_1248; // @[RegisterRouter.scala:87:24] wire _out_T_12007 = ~out_rimask_1248; // @[RegisterRouter.scala:87:24] wire _out_T_12008 = ~out_wimask_1248; // @[RegisterRouter.scala:87:24] wire _out_T_12009 = ~out_romask_1248; // @[RegisterRouter.scala:87:24] wire _out_T_12010 = ~out_womask_1248; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1072 = {hi_68, flags_0_go, _out_prepend_T_1072}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12011 = out_prepend_1072; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12012 = _out_T_12011; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1073 = _out_T_12012; // @[RegisterRouter.scala:87:24] wire out_rimask_1249 = |_out_rimask_T_1249; // @[RegisterRouter.scala:87:24] wire out_wimask_1249 = &_out_wimask_T_1249; // @[RegisterRouter.scala:87:24] wire out_romask_1249 = |_out_romask_T_1249; // @[RegisterRouter.scala:87:24] wire out_womask_1249 = &_out_womask_T_1249; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1249 = out_rivalid_1_1103 & out_rimask_1249; // @[RegisterRouter.scala:87:24] wire _out_T_12014 = out_f_rivalid_1249; // @[RegisterRouter.scala:87:24] wire out_f_roready_1249 = out_roready_1_1103 & out_romask_1249; // @[RegisterRouter.scala:87:24] wire _out_T_12015 = out_f_roready_1249; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1249 = out_wivalid_1_1103 & out_wimask_1249; // @[RegisterRouter.scala:87:24] wire out_f_woready_1249 = out_woready_1_1103 & out_womask_1249; // @[RegisterRouter.scala:87:24] wire _out_T_12016 = ~out_rimask_1249; // @[RegisterRouter.scala:87:24] wire _out_T_12017 = ~out_wimask_1249; // @[RegisterRouter.scala:87:24] wire _out_T_12018 = ~out_romask_1249; // @[RegisterRouter.scala:87:24] wire _out_T_12019 = ~out_womask_1249; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1073 = {hi_69, flags_0_go, _out_prepend_T_1073}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12020 = out_prepend_1073; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12021 = _out_T_12020; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1074 = _out_T_12021; // @[RegisterRouter.scala:87:24] wire out_rimask_1250 = |_out_rimask_T_1250; // @[RegisterRouter.scala:87:24] wire out_wimask_1250 = &_out_wimask_T_1250; // @[RegisterRouter.scala:87:24] wire out_romask_1250 = |_out_romask_T_1250; // @[RegisterRouter.scala:87:24] wire out_womask_1250 = &_out_womask_T_1250; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1250 = out_rivalid_1_1104 & out_rimask_1250; // @[RegisterRouter.scala:87:24] wire _out_T_12023 = out_f_rivalid_1250; // @[RegisterRouter.scala:87:24] wire out_f_roready_1250 = out_roready_1_1104 & out_romask_1250; // @[RegisterRouter.scala:87:24] wire _out_T_12024 = out_f_roready_1250; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1250 = out_wivalid_1_1104 & out_wimask_1250; // @[RegisterRouter.scala:87:24] wire out_f_woready_1250 = out_woready_1_1104 & out_womask_1250; // @[RegisterRouter.scala:87:24] wire _out_T_12025 = ~out_rimask_1250; // @[RegisterRouter.scala:87:24] wire _out_T_12026 = ~out_wimask_1250; // @[RegisterRouter.scala:87:24] wire _out_T_12027 = ~out_romask_1250; // @[RegisterRouter.scala:87:24] wire _out_T_12028 = ~out_womask_1250; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1074 = {hi_70, flags_0_go, _out_prepend_T_1074}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12029 = out_prepend_1074; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12030 = _out_T_12029; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1075 = _out_T_12030; // @[RegisterRouter.scala:87:24] wire out_rimask_1251 = |_out_rimask_T_1251; // @[RegisterRouter.scala:87:24] wire out_wimask_1251 = &_out_wimask_T_1251; // @[RegisterRouter.scala:87:24] wire out_romask_1251 = |_out_romask_T_1251; // @[RegisterRouter.scala:87:24] wire out_womask_1251 = &_out_womask_T_1251; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1251 = out_rivalid_1_1105 & out_rimask_1251; // @[RegisterRouter.scala:87:24] wire _out_T_12032 = out_f_rivalid_1251; // @[RegisterRouter.scala:87:24] wire out_f_roready_1251 = out_roready_1_1105 & out_romask_1251; // @[RegisterRouter.scala:87:24] wire _out_T_12033 = out_f_roready_1251; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1251 = out_wivalid_1_1105 & out_wimask_1251; // @[RegisterRouter.scala:87:24] wire out_f_woready_1251 = out_woready_1_1105 & out_womask_1251; // @[RegisterRouter.scala:87:24] wire _out_T_12034 = ~out_rimask_1251; // @[RegisterRouter.scala:87:24] wire _out_T_12035 = ~out_wimask_1251; // @[RegisterRouter.scala:87:24] wire _out_T_12036 = ~out_romask_1251; // @[RegisterRouter.scala:87:24] wire _out_T_12037 = ~out_womask_1251; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1075 = {hi_71, flags_0_go, _out_prepend_T_1075}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12038 = out_prepend_1075; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12039 = _out_T_12038; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1076 = _out_T_12039; // @[RegisterRouter.scala:87:24] wire out_rimask_1252 = |_out_rimask_T_1252; // @[RegisterRouter.scala:87:24] wire out_wimask_1252 = &_out_wimask_T_1252; // @[RegisterRouter.scala:87:24] wire out_romask_1252 = |_out_romask_T_1252; // @[RegisterRouter.scala:87:24] wire out_womask_1252 = &_out_womask_T_1252; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1252 = out_rivalid_1_1106 & out_rimask_1252; // @[RegisterRouter.scala:87:24] wire _out_T_12041 = out_f_rivalid_1252; // @[RegisterRouter.scala:87:24] wire out_f_roready_1252 = out_roready_1_1106 & out_romask_1252; // @[RegisterRouter.scala:87:24] wire _out_T_12042 = out_f_roready_1252; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1252 = out_wivalid_1_1106 & out_wimask_1252; // @[RegisterRouter.scala:87:24] wire out_f_woready_1252 = out_woready_1_1106 & out_womask_1252; // @[RegisterRouter.scala:87:24] wire _out_T_12043 = ~out_rimask_1252; // @[RegisterRouter.scala:87:24] wire _out_T_12044 = ~out_wimask_1252; // @[RegisterRouter.scala:87:24] wire _out_T_12045 = ~out_romask_1252; // @[RegisterRouter.scala:87:24] wire _out_T_12046 = ~out_womask_1252; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1076 = {hi_72, flags_0_go, _out_prepend_T_1076}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12047 = out_prepend_1076; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12048 = _out_T_12047; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_136 = _out_T_12048; // @[MuxLiteral.scala:49:48] wire out_rimask_1253 = |_out_rimask_T_1253; // @[RegisterRouter.scala:87:24] wire out_wimask_1253 = &_out_wimask_T_1253; // @[RegisterRouter.scala:87:24] wire out_romask_1253 = |_out_romask_T_1253; // @[RegisterRouter.scala:87:24] wire out_womask_1253 = &_out_womask_T_1253; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1253 = out_rivalid_1_1107 & out_rimask_1253; // @[RegisterRouter.scala:87:24] wire _out_T_12050 = out_f_rivalid_1253; // @[RegisterRouter.scala:87:24] wire out_f_roready_1253 = out_roready_1_1107 & out_romask_1253; // @[RegisterRouter.scala:87:24] wire _out_T_12051 = out_f_roready_1253; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1253 = out_wivalid_1_1107 & out_wimask_1253; // @[RegisterRouter.scala:87:24] wire out_f_woready_1253 = out_woready_1_1107 & out_womask_1253; // @[RegisterRouter.scala:87:24] wire _out_T_12052 = ~out_rimask_1253; // @[RegisterRouter.scala:87:24] wire _out_T_12053 = ~out_wimask_1253; // @[RegisterRouter.scala:87:24] wire _out_T_12054 = ~out_romask_1253; // @[RegisterRouter.scala:87:24] wire _out_T_12055 = ~out_womask_1253; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12057 = _out_T_12056; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1077 = _out_T_12057; // @[RegisterRouter.scala:87:24] wire out_rimask_1254 = |_out_rimask_T_1254; // @[RegisterRouter.scala:87:24] wire out_wimask_1254 = &_out_wimask_T_1254; // @[RegisterRouter.scala:87:24] wire out_romask_1254 = |_out_romask_T_1254; // @[RegisterRouter.scala:87:24] wire out_womask_1254 = &_out_womask_T_1254; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1254 = out_rivalid_1_1108 & out_rimask_1254; // @[RegisterRouter.scala:87:24] wire _out_T_12059 = out_f_rivalid_1254; // @[RegisterRouter.scala:87:24] wire out_f_roready_1254 = out_roready_1_1108 & out_romask_1254; // @[RegisterRouter.scala:87:24] wire _out_T_12060 = out_f_roready_1254; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1254 = out_wivalid_1_1108 & out_wimask_1254; // @[RegisterRouter.scala:87:24] wire out_f_woready_1254 = out_woready_1_1108 & out_womask_1254; // @[RegisterRouter.scala:87:24] wire _out_T_12061 = ~out_rimask_1254; // @[RegisterRouter.scala:87:24] wire _out_T_12062 = ~out_wimask_1254; // @[RegisterRouter.scala:87:24] wire _out_T_12063 = ~out_romask_1254; // @[RegisterRouter.scala:87:24] wire _out_T_12064 = ~out_womask_1254; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1077 = {hi_538, flags_0_go, _out_prepend_T_1077}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12065 = out_prepend_1077; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12066 = _out_T_12065; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1078 = _out_T_12066; // @[RegisterRouter.scala:87:24] wire out_rimask_1255 = |_out_rimask_T_1255; // @[RegisterRouter.scala:87:24] wire out_wimask_1255 = &_out_wimask_T_1255; // @[RegisterRouter.scala:87:24] wire out_romask_1255 = |_out_romask_T_1255; // @[RegisterRouter.scala:87:24] wire out_womask_1255 = &_out_womask_T_1255; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1255 = out_rivalid_1_1109 & out_rimask_1255; // @[RegisterRouter.scala:87:24] wire _out_T_12068 = out_f_rivalid_1255; // @[RegisterRouter.scala:87:24] wire out_f_roready_1255 = out_roready_1_1109 & out_romask_1255; // @[RegisterRouter.scala:87:24] wire _out_T_12069 = out_f_roready_1255; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1255 = out_wivalid_1_1109 & out_wimask_1255; // @[RegisterRouter.scala:87:24] wire out_f_woready_1255 = out_woready_1_1109 & out_womask_1255; // @[RegisterRouter.scala:87:24] wire _out_T_12070 = ~out_rimask_1255; // @[RegisterRouter.scala:87:24] wire _out_T_12071 = ~out_wimask_1255; // @[RegisterRouter.scala:87:24] wire _out_T_12072 = ~out_romask_1255; // @[RegisterRouter.scala:87:24] wire _out_T_12073 = ~out_womask_1255; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1078 = {hi_539, flags_0_go, _out_prepend_T_1078}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12074 = out_prepend_1078; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12075 = _out_T_12074; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1079 = _out_T_12075; // @[RegisterRouter.scala:87:24] wire out_rimask_1256 = |_out_rimask_T_1256; // @[RegisterRouter.scala:87:24] wire out_wimask_1256 = &_out_wimask_T_1256; // @[RegisterRouter.scala:87:24] wire out_romask_1256 = |_out_romask_T_1256; // @[RegisterRouter.scala:87:24] wire out_womask_1256 = &_out_womask_T_1256; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1256 = out_rivalid_1_1110 & out_rimask_1256; // @[RegisterRouter.scala:87:24] wire _out_T_12077 = out_f_rivalid_1256; // @[RegisterRouter.scala:87:24] wire out_f_roready_1256 = out_roready_1_1110 & out_romask_1256; // @[RegisterRouter.scala:87:24] wire _out_T_12078 = out_f_roready_1256; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1256 = out_wivalid_1_1110 & out_wimask_1256; // @[RegisterRouter.scala:87:24] wire out_f_woready_1256 = out_woready_1_1110 & out_womask_1256; // @[RegisterRouter.scala:87:24] wire _out_T_12079 = ~out_rimask_1256; // @[RegisterRouter.scala:87:24] wire _out_T_12080 = ~out_wimask_1256; // @[RegisterRouter.scala:87:24] wire _out_T_12081 = ~out_romask_1256; // @[RegisterRouter.scala:87:24] wire _out_T_12082 = ~out_womask_1256; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1079 = {hi_540, flags_0_go, _out_prepend_T_1079}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12083 = out_prepend_1079; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12084 = _out_T_12083; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1080 = _out_T_12084; // @[RegisterRouter.scala:87:24] wire out_rimask_1257 = |_out_rimask_T_1257; // @[RegisterRouter.scala:87:24] wire out_wimask_1257 = &_out_wimask_T_1257; // @[RegisterRouter.scala:87:24] wire out_romask_1257 = |_out_romask_T_1257; // @[RegisterRouter.scala:87:24] wire out_womask_1257 = &_out_womask_T_1257; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1257 = out_rivalid_1_1111 & out_rimask_1257; // @[RegisterRouter.scala:87:24] wire _out_T_12086 = out_f_rivalid_1257; // @[RegisterRouter.scala:87:24] wire out_f_roready_1257 = out_roready_1_1111 & out_romask_1257; // @[RegisterRouter.scala:87:24] wire _out_T_12087 = out_f_roready_1257; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1257 = out_wivalid_1_1111 & out_wimask_1257; // @[RegisterRouter.scala:87:24] wire out_f_woready_1257 = out_woready_1_1111 & out_womask_1257; // @[RegisterRouter.scala:87:24] wire _out_T_12088 = ~out_rimask_1257; // @[RegisterRouter.scala:87:24] wire _out_T_12089 = ~out_wimask_1257; // @[RegisterRouter.scala:87:24] wire _out_T_12090 = ~out_romask_1257; // @[RegisterRouter.scala:87:24] wire _out_T_12091 = ~out_womask_1257; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1080 = {hi_541, flags_0_go, _out_prepend_T_1080}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12092 = out_prepend_1080; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12093 = _out_T_12092; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1081 = _out_T_12093; // @[RegisterRouter.scala:87:24] wire out_rimask_1258 = |_out_rimask_T_1258; // @[RegisterRouter.scala:87:24] wire out_wimask_1258 = &_out_wimask_T_1258; // @[RegisterRouter.scala:87:24] wire out_romask_1258 = |_out_romask_T_1258; // @[RegisterRouter.scala:87:24] wire out_womask_1258 = &_out_womask_T_1258; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1258 = out_rivalid_1_1112 & out_rimask_1258; // @[RegisterRouter.scala:87:24] wire _out_T_12095 = out_f_rivalid_1258; // @[RegisterRouter.scala:87:24] wire out_f_roready_1258 = out_roready_1_1112 & out_romask_1258; // @[RegisterRouter.scala:87:24] wire _out_T_12096 = out_f_roready_1258; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1258 = out_wivalid_1_1112 & out_wimask_1258; // @[RegisterRouter.scala:87:24] wire out_f_woready_1258 = out_woready_1_1112 & out_womask_1258; // @[RegisterRouter.scala:87:24] wire _out_T_12097 = ~out_rimask_1258; // @[RegisterRouter.scala:87:24] wire _out_T_12098 = ~out_wimask_1258; // @[RegisterRouter.scala:87:24] wire _out_T_12099 = ~out_romask_1258; // @[RegisterRouter.scala:87:24] wire _out_T_12100 = ~out_womask_1258; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1081 = {hi_542, flags_0_go, _out_prepend_T_1081}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12101 = out_prepend_1081; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12102 = _out_T_12101; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1082 = _out_T_12102; // @[RegisterRouter.scala:87:24] wire out_rimask_1259 = |_out_rimask_T_1259; // @[RegisterRouter.scala:87:24] wire out_wimask_1259 = &_out_wimask_T_1259; // @[RegisterRouter.scala:87:24] wire out_romask_1259 = |_out_romask_T_1259; // @[RegisterRouter.scala:87:24] wire out_womask_1259 = &_out_womask_T_1259; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1259 = out_rivalid_1_1113 & out_rimask_1259; // @[RegisterRouter.scala:87:24] wire _out_T_12104 = out_f_rivalid_1259; // @[RegisterRouter.scala:87:24] wire out_f_roready_1259 = out_roready_1_1113 & out_romask_1259; // @[RegisterRouter.scala:87:24] wire _out_T_12105 = out_f_roready_1259; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1259 = out_wivalid_1_1113 & out_wimask_1259; // @[RegisterRouter.scala:87:24] wire out_f_woready_1259 = out_woready_1_1113 & out_womask_1259; // @[RegisterRouter.scala:87:24] wire _out_T_12106 = ~out_rimask_1259; // @[RegisterRouter.scala:87:24] wire _out_T_12107 = ~out_wimask_1259; // @[RegisterRouter.scala:87:24] wire _out_T_12108 = ~out_romask_1259; // @[RegisterRouter.scala:87:24] wire _out_T_12109 = ~out_womask_1259; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1082 = {hi_543, flags_0_go, _out_prepend_T_1082}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12110 = out_prepend_1082; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12111 = _out_T_12110; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1083 = _out_T_12111; // @[RegisterRouter.scala:87:24] wire out_rimask_1260 = |_out_rimask_T_1260; // @[RegisterRouter.scala:87:24] wire out_wimask_1260 = &_out_wimask_T_1260; // @[RegisterRouter.scala:87:24] wire out_romask_1260 = |_out_romask_T_1260; // @[RegisterRouter.scala:87:24] wire out_womask_1260 = &_out_womask_T_1260; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1260 = out_rivalid_1_1114 & out_rimask_1260; // @[RegisterRouter.scala:87:24] wire _out_T_12113 = out_f_rivalid_1260; // @[RegisterRouter.scala:87:24] wire out_f_roready_1260 = out_roready_1_1114 & out_romask_1260; // @[RegisterRouter.scala:87:24] wire _out_T_12114 = out_f_roready_1260; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1260 = out_wivalid_1_1114 & out_wimask_1260; // @[RegisterRouter.scala:87:24] wire out_f_woready_1260 = out_woready_1_1114 & out_womask_1260; // @[RegisterRouter.scala:87:24] wire _out_T_12115 = ~out_rimask_1260; // @[RegisterRouter.scala:87:24] wire _out_T_12116 = ~out_wimask_1260; // @[RegisterRouter.scala:87:24] wire _out_T_12117 = ~out_romask_1260; // @[RegisterRouter.scala:87:24] wire _out_T_12118 = ~out_womask_1260; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1083 = {hi_544, flags_0_go, _out_prepend_T_1083}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12119 = out_prepend_1083; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12120 = _out_T_12119; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_195 = _out_T_12120; // @[MuxLiteral.scala:49:48] wire out_rimask_1261 = |_out_rimask_T_1261; // @[RegisterRouter.scala:87:24] wire out_wimask_1261 = &_out_wimask_T_1261; // @[RegisterRouter.scala:87:24] wire out_romask_1261 = |_out_romask_T_1261; // @[RegisterRouter.scala:87:24] wire out_womask_1261 = &_out_womask_T_1261; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1261 = out_rivalid_1_1115 & out_rimask_1261; // @[RegisterRouter.scala:87:24] wire _out_T_12122 = out_f_rivalid_1261; // @[RegisterRouter.scala:87:24] wire out_f_roready_1261 = out_roready_1_1115 & out_romask_1261; // @[RegisterRouter.scala:87:24] wire _out_T_12123 = out_f_roready_1261; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1261 = out_wivalid_1_1115 & out_wimask_1261; // @[RegisterRouter.scala:87:24] wire out_f_woready_1261 = out_woready_1_1115 & out_womask_1261; // @[RegisterRouter.scala:87:24] wire _out_T_12124 = ~out_rimask_1261; // @[RegisterRouter.scala:87:24] wire _out_T_12125 = ~out_wimask_1261; // @[RegisterRouter.scala:87:24] wire _out_T_12126 = ~out_romask_1261; // @[RegisterRouter.scala:87:24] wire _out_T_12127 = ~out_womask_1261; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12129 = _out_T_12128; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1084 = _out_T_12129; // @[RegisterRouter.scala:87:24] wire out_rimask_1262 = |_out_rimask_T_1262; // @[RegisterRouter.scala:87:24] wire out_wimask_1262 = &_out_wimask_T_1262; // @[RegisterRouter.scala:87:24] wire out_romask_1262 = |_out_romask_T_1262; // @[RegisterRouter.scala:87:24] wire out_womask_1262 = &_out_womask_T_1262; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1262 = out_rivalid_1_1116 & out_rimask_1262; // @[RegisterRouter.scala:87:24] wire _out_T_12131 = out_f_rivalid_1262; // @[RegisterRouter.scala:87:24] wire out_f_roready_1262 = out_roready_1_1116 & out_romask_1262; // @[RegisterRouter.scala:87:24] wire _out_T_12132 = out_f_roready_1262; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1262 = out_wivalid_1_1116 & out_wimask_1262; // @[RegisterRouter.scala:87:24] wire out_f_woready_1262 = out_woready_1_1116 & out_womask_1262; // @[RegisterRouter.scala:87:24] wire _out_T_12133 = ~out_rimask_1262; // @[RegisterRouter.scala:87:24] wire _out_T_12134 = ~out_wimask_1262; // @[RegisterRouter.scala:87:24] wire _out_T_12135 = ~out_romask_1262; // @[RegisterRouter.scala:87:24] wire _out_T_12136 = ~out_womask_1262; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1084 = {hi_890, flags_0_go, _out_prepend_T_1084}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12137 = out_prepend_1084; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12138 = _out_T_12137; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1085 = _out_T_12138; // @[RegisterRouter.scala:87:24] wire out_rimask_1263 = |_out_rimask_T_1263; // @[RegisterRouter.scala:87:24] wire out_wimask_1263 = &_out_wimask_T_1263; // @[RegisterRouter.scala:87:24] wire out_romask_1263 = |_out_romask_T_1263; // @[RegisterRouter.scala:87:24] wire out_womask_1263 = &_out_womask_T_1263; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1263 = out_rivalid_1_1117 & out_rimask_1263; // @[RegisterRouter.scala:87:24] wire _out_T_12140 = out_f_rivalid_1263; // @[RegisterRouter.scala:87:24] wire out_f_roready_1263 = out_roready_1_1117 & out_romask_1263; // @[RegisterRouter.scala:87:24] wire _out_T_12141 = out_f_roready_1263; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1263 = out_wivalid_1_1117 & out_wimask_1263; // @[RegisterRouter.scala:87:24] wire out_f_woready_1263 = out_woready_1_1117 & out_womask_1263; // @[RegisterRouter.scala:87:24] wire _out_T_12142 = ~out_rimask_1263; // @[RegisterRouter.scala:87:24] wire _out_T_12143 = ~out_wimask_1263; // @[RegisterRouter.scala:87:24] wire _out_T_12144 = ~out_romask_1263; // @[RegisterRouter.scala:87:24] wire _out_T_12145 = ~out_womask_1263; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1085 = {hi_891, flags_0_go, _out_prepend_T_1085}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12146 = out_prepend_1085; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12147 = _out_T_12146; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1086 = _out_T_12147; // @[RegisterRouter.scala:87:24] wire out_rimask_1264 = |_out_rimask_T_1264; // @[RegisterRouter.scala:87:24] wire out_wimask_1264 = &_out_wimask_T_1264; // @[RegisterRouter.scala:87:24] wire out_romask_1264 = |_out_romask_T_1264; // @[RegisterRouter.scala:87:24] wire out_womask_1264 = &_out_womask_T_1264; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1264 = out_rivalid_1_1118 & out_rimask_1264; // @[RegisterRouter.scala:87:24] wire _out_T_12149 = out_f_rivalid_1264; // @[RegisterRouter.scala:87:24] wire out_f_roready_1264 = out_roready_1_1118 & out_romask_1264; // @[RegisterRouter.scala:87:24] wire _out_T_12150 = out_f_roready_1264; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1264 = out_wivalid_1_1118 & out_wimask_1264; // @[RegisterRouter.scala:87:24] wire out_f_woready_1264 = out_woready_1_1118 & out_womask_1264; // @[RegisterRouter.scala:87:24] wire _out_T_12151 = ~out_rimask_1264; // @[RegisterRouter.scala:87:24] wire _out_T_12152 = ~out_wimask_1264; // @[RegisterRouter.scala:87:24] wire _out_T_12153 = ~out_romask_1264; // @[RegisterRouter.scala:87:24] wire _out_T_12154 = ~out_womask_1264; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1086 = {hi_892, flags_0_go, _out_prepend_T_1086}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12155 = out_prepend_1086; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12156 = _out_T_12155; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1087 = _out_T_12156; // @[RegisterRouter.scala:87:24] wire out_rimask_1265 = |_out_rimask_T_1265; // @[RegisterRouter.scala:87:24] wire out_wimask_1265 = &_out_wimask_T_1265; // @[RegisterRouter.scala:87:24] wire out_romask_1265 = |_out_romask_T_1265; // @[RegisterRouter.scala:87:24] wire out_womask_1265 = &_out_womask_T_1265; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1265 = out_rivalid_1_1119 & out_rimask_1265; // @[RegisterRouter.scala:87:24] wire _out_T_12158 = out_f_rivalid_1265; // @[RegisterRouter.scala:87:24] wire out_f_roready_1265 = out_roready_1_1119 & out_romask_1265; // @[RegisterRouter.scala:87:24] wire _out_T_12159 = out_f_roready_1265; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1265 = out_wivalid_1_1119 & out_wimask_1265; // @[RegisterRouter.scala:87:24] wire out_f_woready_1265 = out_woready_1_1119 & out_womask_1265; // @[RegisterRouter.scala:87:24] wire _out_T_12160 = ~out_rimask_1265; // @[RegisterRouter.scala:87:24] wire _out_T_12161 = ~out_wimask_1265; // @[RegisterRouter.scala:87:24] wire _out_T_12162 = ~out_romask_1265; // @[RegisterRouter.scala:87:24] wire _out_T_12163 = ~out_womask_1265; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1087 = {hi_893, flags_0_go, _out_prepend_T_1087}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12164 = out_prepend_1087; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12165 = _out_T_12164; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1088 = _out_T_12165; // @[RegisterRouter.scala:87:24] wire out_rimask_1266 = |_out_rimask_T_1266; // @[RegisterRouter.scala:87:24] wire out_wimask_1266 = &_out_wimask_T_1266; // @[RegisterRouter.scala:87:24] wire out_romask_1266 = |_out_romask_T_1266; // @[RegisterRouter.scala:87:24] wire out_womask_1266 = &_out_womask_T_1266; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1266 = out_rivalid_1_1120 & out_rimask_1266; // @[RegisterRouter.scala:87:24] wire _out_T_12167 = out_f_rivalid_1266; // @[RegisterRouter.scala:87:24] wire out_f_roready_1266 = out_roready_1_1120 & out_romask_1266; // @[RegisterRouter.scala:87:24] wire _out_T_12168 = out_f_roready_1266; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1266 = out_wivalid_1_1120 & out_wimask_1266; // @[RegisterRouter.scala:87:24] wire out_f_woready_1266 = out_woready_1_1120 & out_womask_1266; // @[RegisterRouter.scala:87:24] wire _out_T_12169 = ~out_rimask_1266; // @[RegisterRouter.scala:87:24] wire _out_T_12170 = ~out_wimask_1266; // @[RegisterRouter.scala:87:24] wire _out_T_12171 = ~out_romask_1266; // @[RegisterRouter.scala:87:24] wire _out_T_12172 = ~out_womask_1266; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1088 = {hi_894, flags_0_go, _out_prepend_T_1088}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12173 = out_prepend_1088; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12174 = _out_T_12173; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1089 = _out_T_12174; // @[RegisterRouter.scala:87:24] wire out_rimask_1267 = |_out_rimask_T_1267; // @[RegisterRouter.scala:87:24] wire out_wimask_1267 = &_out_wimask_T_1267; // @[RegisterRouter.scala:87:24] wire out_romask_1267 = |_out_romask_T_1267; // @[RegisterRouter.scala:87:24] wire out_womask_1267 = &_out_womask_T_1267; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1267 = out_rivalid_1_1121 & out_rimask_1267; // @[RegisterRouter.scala:87:24] wire _out_T_12176 = out_f_rivalid_1267; // @[RegisterRouter.scala:87:24] wire out_f_roready_1267 = out_roready_1_1121 & out_romask_1267; // @[RegisterRouter.scala:87:24] wire _out_T_12177 = out_f_roready_1267; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1267 = out_wivalid_1_1121 & out_wimask_1267; // @[RegisterRouter.scala:87:24] wire out_f_woready_1267 = out_woready_1_1121 & out_womask_1267; // @[RegisterRouter.scala:87:24] wire _out_T_12178 = ~out_rimask_1267; // @[RegisterRouter.scala:87:24] wire _out_T_12179 = ~out_wimask_1267; // @[RegisterRouter.scala:87:24] wire _out_T_12180 = ~out_romask_1267; // @[RegisterRouter.scala:87:24] wire _out_T_12181 = ~out_womask_1267; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1089 = {hi_895, flags_0_go, _out_prepend_T_1089}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12182 = out_prepend_1089; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12183 = _out_T_12182; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1090 = _out_T_12183; // @[RegisterRouter.scala:87:24] wire out_rimask_1268 = |_out_rimask_T_1268; // @[RegisterRouter.scala:87:24] wire out_wimask_1268 = &_out_wimask_T_1268; // @[RegisterRouter.scala:87:24] wire out_romask_1268 = |_out_romask_T_1268; // @[RegisterRouter.scala:87:24] wire out_womask_1268 = &_out_womask_T_1268; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1268 = out_rivalid_1_1122 & out_rimask_1268; // @[RegisterRouter.scala:87:24] wire _out_T_12185 = out_f_rivalid_1268; // @[RegisterRouter.scala:87:24] wire out_f_roready_1268 = out_roready_1_1122 & out_romask_1268; // @[RegisterRouter.scala:87:24] wire _out_T_12186 = out_f_roready_1268; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1268 = out_wivalid_1_1122 & out_wimask_1268; // @[RegisterRouter.scala:87:24] wire out_f_woready_1268 = out_woready_1_1122 & out_womask_1268; // @[RegisterRouter.scala:87:24] wire _out_T_12187 = ~out_rimask_1268; // @[RegisterRouter.scala:87:24] wire _out_T_12188 = ~out_wimask_1268; // @[RegisterRouter.scala:87:24] wire _out_T_12189 = ~out_romask_1268; // @[RegisterRouter.scala:87:24] wire _out_T_12190 = ~out_womask_1268; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1090 = {hi_896, flags_0_go, _out_prepend_T_1090}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12191 = out_prepend_1090; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12192 = _out_T_12191; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_239 = _out_T_12192; // @[MuxLiteral.scala:49:48] wire out_rimask_1269 = |_out_rimask_T_1269; // @[RegisterRouter.scala:87:24] wire out_wimask_1269 = &_out_wimask_T_1269; // @[RegisterRouter.scala:87:24] wire out_romask_1269 = |_out_romask_T_1269; // @[RegisterRouter.scala:87:24] wire out_womask_1269 = &_out_womask_T_1269; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1269 = out_rivalid_1_1123 & out_rimask_1269; // @[RegisterRouter.scala:87:24] wire _out_T_12194 = out_f_rivalid_1269; // @[RegisterRouter.scala:87:24] wire out_f_roready_1269 = out_roready_1_1123 & out_romask_1269; // @[RegisterRouter.scala:87:24] wire _out_T_12195 = out_f_roready_1269; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1269 = out_wivalid_1_1123 & out_wimask_1269; // @[RegisterRouter.scala:87:24] wire out_f_woready_1269 = out_woready_1_1123 & out_womask_1269; // @[RegisterRouter.scala:87:24] wire _out_T_12196 = ~out_rimask_1269; // @[RegisterRouter.scala:87:24] wire _out_T_12197 = ~out_wimask_1269; // @[RegisterRouter.scala:87:24] wire _out_T_12198 = ~out_romask_1269; // @[RegisterRouter.scala:87:24] wire _out_T_12199 = ~out_womask_1269; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12201 = _out_T_12200; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1091 = _out_T_12201; // @[RegisterRouter.scala:87:24] wire out_rimask_1270 = |_out_rimask_T_1270; // @[RegisterRouter.scala:87:24] wire out_wimask_1270 = &_out_wimask_T_1270; // @[RegisterRouter.scala:87:24] wire out_romask_1270 = |_out_romask_T_1270; // @[RegisterRouter.scala:87:24] wire out_womask_1270 = &_out_womask_T_1270; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1270 = out_rivalid_1_1124 & out_rimask_1270; // @[RegisterRouter.scala:87:24] wire _out_T_12203 = out_f_rivalid_1270; // @[RegisterRouter.scala:87:24] wire out_f_roready_1270 = out_roready_1_1124 & out_romask_1270; // @[RegisterRouter.scala:87:24] wire _out_T_12204 = out_f_roready_1270; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1270 = out_wivalid_1_1124 & out_wimask_1270; // @[RegisterRouter.scala:87:24] wire out_f_woready_1270 = out_woready_1_1124 & out_womask_1270; // @[RegisterRouter.scala:87:24] wire _out_T_12205 = ~out_rimask_1270; // @[RegisterRouter.scala:87:24] wire _out_T_12206 = ~out_wimask_1270; // @[RegisterRouter.scala:87:24] wire _out_T_12207 = ~out_romask_1270; // @[RegisterRouter.scala:87:24] wire _out_T_12208 = ~out_womask_1270; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1091 = {hi_914, flags_0_go, _out_prepend_T_1091}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12209 = out_prepend_1091; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12210 = _out_T_12209; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1092 = _out_T_12210; // @[RegisterRouter.scala:87:24] wire out_rimask_1271 = |_out_rimask_T_1271; // @[RegisterRouter.scala:87:24] wire out_wimask_1271 = &_out_wimask_T_1271; // @[RegisterRouter.scala:87:24] wire out_romask_1271 = |_out_romask_T_1271; // @[RegisterRouter.scala:87:24] wire out_womask_1271 = &_out_womask_T_1271; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1271 = out_rivalid_1_1125 & out_rimask_1271; // @[RegisterRouter.scala:87:24] wire _out_T_12212 = out_f_rivalid_1271; // @[RegisterRouter.scala:87:24] wire out_f_roready_1271 = out_roready_1_1125 & out_romask_1271; // @[RegisterRouter.scala:87:24] wire _out_T_12213 = out_f_roready_1271; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1271 = out_wivalid_1_1125 & out_wimask_1271; // @[RegisterRouter.scala:87:24] wire out_f_woready_1271 = out_woready_1_1125 & out_womask_1271; // @[RegisterRouter.scala:87:24] wire _out_T_12214 = ~out_rimask_1271; // @[RegisterRouter.scala:87:24] wire _out_T_12215 = ~out_wimask_1271; // @[RegisterRouter.scala:87:24] wire _out_T_12216 = ~out_romask_1271; // @[RegisterRouter.scala:87:24] wire _out_T_12217 = ~out_womask_1271; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1092 = {hi_915, flags_0_go, _out_prepend_T_1092}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12218 = out_prepend_1092; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12219 = _out_T_12218; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1093 = _out_T_12219; // @[RegisterRouter.scala:87:24] wire out_rimask_1272 = |_out_rimask_T_1272; // @[RegisterRouter.scala:87:24] wire out_wimask_1272 = &_out_wimask_T_1272; // @[RegisterRouter.scala:87:24] wire out_romask_1272 = |_out_romask_T_1272; // @[RegisterRouter.scala:87:24] wire out_womask_1272 = &_out_womask_T_1272; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1272 = out_rivalid_1_1126 & out_rimask_1272; // @[RegisterRouter.scala:87:24] wire _out_T_12221 = out_f_rivalid_1272; // @[RegisterRouter.scala:87:24] wire out_f_roready_1272 = out_roready_1_1126 & out_romask_1272; // @[RegisterRouter.scala:87:24] wire _out_T_12222 = out_f_roready_1272; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1272 = out_wivalid_1_1126 & out_wimask_1272; // @[RegisterRouter.scala:87:24] wire out_f_woready_1272 = out_woready_1_1126 & out_womask_1272; // @[RegisterRouter.scala:87:24] wire _out_T_12223 = ~out_rimask_1272; // @[RegisterRouter.scala:87:24] wire _out_T_12224 = ~out_wimask_1272; // @[RegisterRouter.scala:87:24] wire _out_T_12225 = ~out_romask_1272; // @[RegisterRouter.scala:87:24] wire _out_T_12226 = ~out_womask_1272; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1093 = {hi_916, flags_0_go, _out_prepend_T_1093}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12227 = out_prepend_1093; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12228 = _out_T_12227; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1094 = _out_T_12228; // @[RegisterRouter.scala:87:24] wire out_rimask_1273 = |_out_rimask_T_1273; // @[RegisterRouter.scala:87:24] wire out_wimask_1273 = &_out_wimask_T_1273; // @[RegisterRouter.scala:87:24] wire out_romask_1273 = |_out_romask_T_1273; // @[RegisterRouter.scala:87:24] wire out_womask_1273 = &_out_womask_T_1273; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1273 = out_rivalid_1_1127 & out_rimask_1273; // @[RegisterRouter.scala:87:24] wire _out_T_12230 = out_f_rivalid_1273; // @[RegisterRouter.scala:87:24] wire out_f_roready_1273 = out_roready_1_1127 & out_romask_1273; // @[RegisterRouter.scala:87:24] wire _out_T_12231 = out_f_roready_1273; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1273 = out_wivalid_1_1127 & out_wimask_1273; // @[RegisterRouter.scala:87:24] wire out_f_woready_1273 = out_woready_1_1127 & out_womask_1273; // @[RegisterRouter.scala:87:24] wire _out_T_12232 = ~out_rimask_1273; // @[RegisterRouter.scala:87:24] wire _out_T_12233 = ~out_wimask_1273; // @[RegisterRouter.scala:87:24] wire _out_T_12234 = ~out_romask_1273; // @[RegisterRouter.scala:87:24] wire _out_T_12235 = ~out_womask_1273; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1094 = {hi_917, flags_0_go, _out_prepend_T_1094}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12236 = out_prepend_1094; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12237 = _out_T_12236; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1095 = _out_T_12237; // @[RegisterRouter.scala:87:24] wire out_rimask_1274 = |_out_rimask_T_1274; // @[RegisterRouter.scala:87:24] wire out_wimask_1274 = &_out_wimask_T_1274; // @[RegisterRouter.scala:87:24] wire out_romask_1274 = |_out_romask_T_1274; // @[RegisterRouter.scala:87:24] wire out_womask_1274 = &_out_womask_T_1274; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1274 = out_rivalid_1_1128 & out_rimask_1274; // @[RegisterRouter.scala:87:24] wire _out_T_12239 = out_f_rivalid_1274; // @[RegisterRouter.scala:87:24] wire out_f_roready_1274 = out_roready_1_1128 & out_romask_1274; // @[RegisterRouter.scala:87:24] wire _out_T_12240 = out_f_roready_1274; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1274 = out_wivalid_1_1128 & out_wimask_1274; // @[RegisterRouter.scala:87:24] wire out_f_woready_1274 = out_woready_1_1128 & out_womask_1274; // @[RegisterRouter.scala:87:24] wire _out_T_12241 = ~out_rimask_1274; // @[RegisterRouter.scala:87:24] wire _out_T_12242 = ~out_wimask_1274; // @[RegisterRouter.scala:87:24] wire _out_T_12243 = ~out_romask_1274; // @[RegisterRouter.scala:87:24] wire _out_T_12244 = ~out_womask_1274; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1095 = {hi_918, flags_0_go, _out_prepend_T_1095}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12245 = out_prepend_1095; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12246 = _out_T_12245; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1096 = _out_T_12246; // @[RegisterRouter.scala:87:24] wire out_rimask_1275 = |_out_rimask_T_1275; // @[RegisterRouter.scala:87:24] wire out_wimask_1275 = &_out_wimask_T_1275; // @[RegisterRouter.scala:87:24] wire out_romask_1275 = |_out_romask_T_1275; // @[RegisterRouter.scala:87:24] wire out_womask_1275 = &_out_womask_T_1275; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1275 = out_rivalid_1_1129 & out_rimask_1275; // @[RegisterRouter.scala:87:24] wire _out_T_12248 = out_f_rivalid_1275; // @[RegisterRouter.scala:87:24] wire out_f_roready_1275 = out_roready_1_1129 & out_romask_1275; // @[RegisterRouter.scala:87:24] wire _out_T_12249 = out_f_roready_1275; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1275 = out_wivalid_1_1129 & out_wimask_1275; // @[RegisterRouter.scala:87:24] wire out_f_woready_1275 = out_woready_1_1129 & out_womask_1275; // @[RegisterRouter.scala:87:24] wire _out_T_12250 = ~out_rimask_1275; // @[RegisterRouter.scala:87:24] wire _out_T_12251 = ~out_wimask_1275; // @[RegisterRouter.scala:87:24] wire _out_T_12252 = ~out_romask_1275; // @[RegisterRouter.scala:87:24] wire _out_T_12253 = ~out_womask_1275; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1096 = {hi_919, flags_0_go, _out_prepend_T_1096}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12254 = out_prepend_1096; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12255 = _out_T_12254; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1097 = _out_T_12255; // @[RegisterRouter.scala:87:24] wire out_rimask_1276 = |_out_rimask_T_1276; // @[RegisterRouter.scala:87:24] wire out_wimask_1276 = &_out_wimask_T_1276; // @[RegisterRouter.scala:87:24] wire out_romask_1276 = |_out_romask_T_1276; // @[RegisterRouter.scala:87:24] wire out_womask_1276 = &_out_womask_T_1276; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1276 = out_rivalid_1_1130 & out_rimask_1276; // @[RegisterRouter.scala:87:24] wire _out_T_12257 = out_f_rivalid_1276; // @[RegisterRouter.scala:87:24] wire out_f_roready_1276 = out_roready_1_1130 & out_romask_1276; // @[RegisterRouter.scala:87:24] wire _out_T_12258 = out_f_roready_1276; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1276 = out_wivalid_1_1130 & out_wimask_1276; // @[RegisterRouter.scala:87:24] wire out_f_woready_1276 = out_woready_1_1130 & out_womask_1276; // @[RegisterRouter.scala:87:24] wire _out_T_12259 = ~out_rimask_1276; // @[RegisterRouter.scala:87:24] wire _out_T_12260 = ~out_wimask_1276; // @[RegisterRouter.scala:87:24] wire _out_T_12261 = ~out_romask_1276; // @[RegisterRouter.scala:87:24] wire _out_T_12262 = ~out_womask_1276; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1097 = {hi_920, flags_0_go, _out_prepend_T_1097}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12263 = out_prepend_1097; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12264 = _out_T_12263; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_242 = _out_T_12264; // @[MuxLiteral.scala:49:48] wire out_rimask_1277 = |_out_rimask_T_1277; // @[RegisterRouter.scala:87:24] wire out_wimask_1277 = &_out_wimask_T_1277; // @[RegisterRouter.scala:87:24] wire out_romask_1277 = |_out_romask_T_1277; // @[RegisterRouter.scala:87:24] wire out_womask_1277 = &_out_womask_T_1277; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1277 = out_rivalid_1_1131 & out_rimask_1277; // @[RegisterRouter.scala:87:24] wire _out_T_12266 = out_f_rivalid_1277; // @[RegisterRouter.scala:87:24] wire out_f_roready_1277 = out_roready_1_1131 & out_romask_1277; // @[RegisterRouter.scala:87:24] wire _out_T_12267 = out_f_roready_1277; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1277 = out_wivalid_1_1131 & out_wimask_1277; // @[RegisterRouter.scala:87:24] wire out_f_woready_1277 = out_woready_1_1131 & out_womask_1277; // @[RegisterRouter.scala:87:24] wire _out_T_12268 = ~out_rimask_1277; // @[RegisterRouter.scala:87:24] wire _out_T_12269 = ~out_wimask_1277; // @[RegisterRouter.scala:87:24] wire _out_T_12270 = ~out_romask_1277; // @[RegisterRouter.scala:87:24] wire _out_T_12271 = ~out_womask_1277; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12273 = _out_T_12272; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1098 = _out_T_12273; // @[RegisterRouter.scala:87:24] wire out_rimask_1278 = |_out_rimask_T_1278; // @[RegisterRouter.scala:87:24] wire out_wimask_1278 = &_out_wimask_T_1278; // @[RegisterRouter.scala:87:24] wire out_romask_1278 = |_out_romask_T_1278; // @[RegisterRouter.scala:87:24] wire out_womask_1278 = &_out_womask_T_1278; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1278 = out_rivalid_1_1132 & out_rimask_1278; // @[RegisterRouter.scala:87:24] wire _out_T_12275 = out_f_rivalid_1278; // @[RegisterRouter.scala:87:24] wire out_f_roready_1278 = out_roready_1_1132 & out_romask_1278; // @[RegisterRouter.scala:87:24] wire _out_T_12276 = out_f_roready_1278; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1278 = out_wivalid_1_1132 & out_wimask_1278; // @[RegisterRouter.scala:87:24] wire out_f_woready_1278 = out_woready_1_1132 & out_womask_1278; // @[RegisterRouter.scala:87:24] wire _out_T_12277 = ~out_rimask_1278; // @[RegisterRouter.scala:87:24] wire _out_T_12278 = ~out_wimask_1278; // @[RegisterRouter.scala:87:24] wire _out_T_12279 = ~out_romask_1278; // @[RegisterRouter.scala:87:24] wire _out_T_12280 = ~out_womask_1278; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1098 = {hi_26, flags_0_go, _out_prepend_T_1098}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12281 = out_prepend_1098; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12282 = _out_T_12281; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1099 = _out_T_12282; // @[RegisterRouter.scala:87:24] wire out_rimask_1279 = |_out_rimask_T_1279; // @[RegisterRouter.scala:87:24] wire out_wimask_1279 = &_out_wimask_T_1279; // @[RegisterRouter.scala:87:24] wire out_romask_1279 = |_out_romask_T_1279; // @[RegisterRouter.scala:87:24] wire out_womask_1279 = &_out_womask_T_1279; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1279 = out_rivalid_1_1133 & out_rimask_1279; // @[RegisterRouter.scala:87:24] wire _out_T_12284 = out_f_rivalid_1279; // @[RegisterRouter.scala:87:24] wire out_f_roready_1279 = out_roready_1_1133 & out_romask_1279; // @[RegisterRouter.scala:87:24] wire _out_T_12285 = out_f_roready_1279; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1279 = out_wivalid_1_1133 & out_wimask_1279; // @[RegisterRouter.scala:87:24] wire out_f_woready_1279 = out_woready_1_1133 & out_womask_1279; // @[RegisterRouter.scala:87:24] wire _out_T_12286 = ~out_rimask_1279; // @[RegisterRouter.scala:87:24] wire _out_T_12287 = ~out_wimask_1279; // @[RegisterRouter.scala:87:24] wire _out_T_12288 = ~out_romask_1279; // @[RegisterRouter.scala:87:24] wire _out_T_12289 = ~out_womask_1279; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1099 = {hi_27, flags_0_go, _out_prepend_T_1099}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12290 = out_prepend_1099; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12291 = _out_T_12290; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1100 = _out_T_12291; // @[RegisterRouter.scala:87:24] wire out_rimask_1280 = |_out_rimask_T_1280; // @[RegisterRouter.scala:87:24] wire out_wimask_1280 = &_out_wimask_T_1280; // @[RegisterRouter.scala:87:24] wire out_romask_1280 = |_out_romask_T_1280; // @[RegisterRouter.scala:87:24] wire out_womask_1280 = &_out_womask_T_1280; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1280 = out_rivalid_1_1134 & out_rimask_1280; // @[RegisterRouter.scala:87:24] wire _out_T_12293 = out_f_rivalid_1280; // @[RegisterRouter.scala:87:24] wire out_f_roready_1280 = out_roready_1_1134 & out_romask_1280; // @[RegisterRouter.scala:87:24] wire _out_T_12294 = out_f_roready_1280; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1280 = out_wivalid_1_1134 & out_wimask_1280; // @[RegisterRouter.scala:87:24] wire out_f_woready_1280 = out_woready_1_1134 & out_womask_1280; // @[RegisterRouter.scala:87:24] wire _out_T_12295 = ~out_rimask_1280; // @[RegisterRouter.scala:87:24] wire _out_T_12296 = ~out_wimask_1280; // @[RegisterRouter.scala:87:24] wire _out_T_12297 = ~out_romask_1280; // @[RegisterRouter.scala:87:24] wire _out_T_12298 = ~out_womask_1280; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1100 = {hi_28, flags_0_go, _out_prepend_T_1100}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12299 = out_prepend_1100; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12300 = _out_T_12299; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1101 = _out_T_12300; // @[RegisterRouter.scala:87:24] wire out_rimask_1281 = |_out_rimask_T_1281; // @[RegisterRouter.scala:87:24] wire out_wimask_1281 = &_out_wimask_T_1281; // @[RegisterRouter.scala:87:24] wire out_romask_1281 = |_out_romask_T_1281; // @[RegisterRouter.scala:87:24] wire out_womask_1281 = &_out_womask_T_1281; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1281 = out_rivalid_1_1135 & out_rimask_1281; // @[RegisterRouter.scala:87:24] wire _out_T_12302 = out_f_rivalid_1281; // @[RegisterRouter.scala:87:24] wire out_f_roready_1281 = out_roready_1_1135 & out_romask_1281; // @[RegisterRouter.scala:87:24] wire _out_T_12303 = out_f_roready_1281; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1281 = out_wivalid_1_1135 & out_wimask_1281; // @[RegisterRouter.scala:87:24] wire out_f_woready_1281 = out_woready_1_1135 & out_womask_1281; // @[RegisterRouter.scala:87:24] wire _out_T_12304 = ~out_rimask_1281; // @[RegisterRouter.scala:87:24] wire _out_T_12305 = ~out_wimask_1281; // @[RegisterRouter.scala:87:24] wire _out_T_12306 = ~out_romask_1281; // @[RegisterRouter.scala:87:24] wire _out_T_12307 = ~out_womask_1281; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1101 = {hi_29, flags_0_go, _out_prepend_T_1101}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12308 = out_prepend_1101; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12309 = _out_T_12308; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1102 = _out_T_12309; // @[RegisterRouter.scala:87:24] wire out_rimask_1282 = |_out_rimask_T_1282; // @[RegisterRouter.scala:87:24] wire out_wimask_1282 = &_out_wimask_T_1282; // @[RegisterRouter.scala:87:24] wire out_romask_1282 = |_out_romask_T_1282; // @[RegisterRouter.scala:87:24] wire out_womask_1282 = &_out_womask_T_1282; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1282 = out_rivalid_1_1136 & out_rimask_1282; // @[RegisterRouter.scala:87:24] wire _out_T_12311 = out_f_rivalid_1282; // @[RegisterRouter.scala:87:24] wire out_f_roready_1282 = out_roready_1_1136 & out_romask_1282; // @[RegisterRouter.scala:87:24] wire _out_T_12312 = out_f_roready_1282; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1282 = out_wivalid_1_1136 & out_wimask_1282; // @[RegisterRouter.scala:87:24] wire out_f_woready_1282 = out_woready_1_1136 & out_womask_1282; // @[RegisterRouter.scala:87:24] wire _out_T_12313 = ~out_rimask_1282; // @[RegisterRouter.scala:87:24] wire _out_T_12314 = ~out_wimask_1282; // @[RegisterRouter.scala:87:24] wire _out_T_12315 = ~out_romask_1282; // @[RegisterRouter.scala:87:24] wire _out_T_12316 = ~out_womask_1282; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1102 = {hi_30, flags_0_go, _out_prepend_T_1102}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12317 = out_prepend_1102; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12318 = _out_T_12317; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1103 = _out_T_12318; // @[RegisterRouter.scala:87:24] wire out_rimask_1283 = |_out_rimask_T_1283; // @[RegisterRouter.scala:87:24] wire out_wimask_1283 = &_out_wimask_T_1283; // @[RegisterRouter.scala:87:24] wire out_romask_1283 = |_out_romask_T_1283; // @[RegisterRouter.scala:87:24] wire out_womask_1283 = &_out_womask_T_1283; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1283 = out_rivalid_1_1137 & out_rimask_1283; // @[RegisterRouter.scala:87:24] wire _out_T_12320 = out_f_rivalid_1283; // @[RegisterRouter.scala:87:24] wire out_f_roready_1283 = out_roready_1_1137 & out_romask_1283; // @[RegisterRouter.scala:87:24] wire _out_T_12321 = out_f_roready_1283; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1283 = out_wivalid_1_1137 & out_wimask_1283; // @[RegisterRouter.scala:87:24] wire out_f_woready_1283 = out_woready_1_1137 & out_womask_1283; // @[RegisterRouter.scala:87:24] wire _out_T_12322 = ~out_rimask_1283; // @[RegisterRouter.scala:87:24] wire _out_T_12323 = ~out_wimask_1283; // @[RegisterRouter.scala:87:24] wire _out_T_12324 = ~out_romask_1283; // @[RegisterRouter.scala:87:24] wire _out_T_12325 = ~out_womask_1283; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1103 = {hi_31, flags_0_go, _out_prepend_T_1103}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12326 = out_prepend_1103; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12327 = _out_T_12326; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1104 = _out_T_12327; // @[RegisterRouter.scala:87:24] wire out_rimask_1284 = |_out_rimask_T_1284; // @[RegisterRouter.scala:87:24] wire out_wimask_1284 = &_out_wimask_T_1284; // @[RegisterRouter.scala:87:24] wire out_romask_1284 = |_out_romask_T_1284; // @[RegisterRouter.scala:87:24] wire out_womask_1284 = &_out_womask_T_1284; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1284 = out_rivalid_1_1138 & out_rimask_1284; // @[RegisterRouter.scala:87:24] wire _out_T_12329 = out_f_rivalid_1284; // @[RegisterRouter.scala:87:24] wire out_f_roready_1284 = out_roready_1_1138 & out_romask_1284; // @[RegisterRouter.scala:87:24] wire _out_T_12330 = out_f_roready_1284; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1284 = out_wivalid_1_1138 & out_wimask_1284; // @[RegisterRouter.scala:87:24] wire out_f_woready_1284 = out_woready_1_1138 & out_womask_1284; // @[RegisterRouter.scala:87:24] wire _out_T_12331 = ~out_rimask_1284; // @[RegisterRouter.scala:87:24] wire _out_T_12332 = ~out_wimask_1284; // @[RegisterRouter.scala:87:24] wire _out_T_12333 = ~out_romask_1284; // @[RegisterRouter.scala:87:24] wire _out_T_12334 = ~out_womask_1284; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1104 = {hi_32, flags_0_go, _out_prepend_T_1104}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12335 = out_prepend_1104; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12336 = _out_T_12335; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_131 = _out_T_12336; // @[MuxLiteral.scala:49:48] wire out_rimask_1285 = |_out_rimask_T_1285; // @[RegisterRouter.scala:87:24] wire out_wimask_1285 = &_out_wimask_T_1285; // @[RegisterRouter.scala:87:24] wire out_romask_1285 = |_out_romask_T_1285; // @[RegisterRouter.scala:87:24] wire out_womask_1285 = &_out_womask_T_1285; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1285 = out_rivalid_1_1139 & out_rimask_1285; // @[RegisterRouter.scala:87:24] wire _out_T_12338 = out_f_rivalid_1285; // @[RegisterRouter.scala:87:24] wire out_f_roready_1285 = out_roready_1_1139 & out_romask_1285; // @[RegisterRouter.scala:87:24] wire _out_T_12339 = out_f_roready_1285; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1285 = out_wivalid_1_1139 & out_wimask_1285; // @[RegisterRouter.scala:87:24] wire out_f_woready_1285 = out_woready_1_1139 & out_womask_1285; // @[RegisterRouter.scala:87:24] wire _out_T_12340 = ~out_rimask_1285; // @[RegisterRouter.scala:87:24] wire _out_T_12341 = ~out_wimask_1285; // @[RegisterRouter.scala:87:24] wire _out_T_12342 = ~out_romask_1285; // @[RegisterRouter.scala:87:24] wire _out_T_12343 = ~out_womask_1285; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12345 = _out_T_12344; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1105 = _out_T_12345; // @[RegisterRouter.scala:87:24] wire out_rimask_1286 = |_out_rimask_T_1286; // @[RegisterRouter.scala:87:24] wire out_wimask_1286 = &_out_wimask_T_1286; // @[RegisterRouter.scala:87:24] wire out_romask_1286 = |_out_romask_T_1286; // @[RegisterRouter.scala:87:24] wire out_womask_1286 = &_out_womask_T_1286; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1286 = out_rivalid_1_1140 & out_rimask_1286; // @[RegisterRouter.scala:87:24] wire _out_T_12347 = out_f_rivalid_1286; // @[RegisterRouter.scala:87:24] wire out_f_roready_1286 = out_roready_1_1140 & out_romask_1286; // @[RegisterRouter.scala:87:24] wire _out_T_12348 = out_f_roready_1286; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1286 = out_wivalid_1_1140 & out_wimask_1286; // @[RegisterRouter.scala:87:24] wire out_f_woready_1286 = out_woready_1_1140 & out_womask_1286; // @[RegisterRouter.scala:87:24] wire _out_T_12349 = ~out_rimask_1286; // @[RegisterRouter.scala:87:24] wire _out_T_12350 = ~out_wimask_1286; // @[RegisterRouter.scala:87:24] wire _out_T_12351 = ~out_romask_1286; // @[RegisterRouter.scala:87:24] wire _out_T_12352 = ~out_womask_1286; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1105 = {hi_402, flags_0_go, _out_prepend_T_1105}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12353 = out_prepend_1105; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12354 = _out_T_12353; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1106 = _out_T_12354; // @[RegisterRouter.scala:87:24] wire out_rimask_1287 = |_out_rimask_T_1287; // @[RegisterRouter.scala:87:24] wire out_wimask_1287 = &_out_wimask_T_1287; // @[RegisterRouter.scala:87:24] wire out_romask_1287 = |_out_romask_T_1287; // @[RegisterRouter.scala:87:24] wire out_womask_1287 = &_out_womask_T_1287; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1287 = out_rivalid_1_1141 & out_rimask_1287; // @[RegisterRouter.scala:87:24] wire _out_T_12356 = out_f_rivalid_1287; // @[RegisterRouter.scala:87:24] wire out_f_roready_1287 = out_roready_1_1141 & out_romask_1287; // @[RegisterRouter.scala:87:24] wire _out_T_12357 = out_f_roready_1287; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1287 = out_wivalid_1_1141 & out_wimask_1287; // @[RegisterRouter.scala:87:24] wire out_f_woready_1287 = out_woready_1_1141 & out_womask_1287; // @[RegisterRouter.scala:87:24] wire _out_T_12358 = ~out_rimask_1287; // @[RegisterRouter.scala:87:24] wire _out_T_12359 = ~out_wimask_1287; // @[RegisterRouter.scala:87:24] wire _out_T_12360 = ~out_romask_1287; // @[RegisterRouter.scala:87:24] wire _out_T_12361 = ~out_womask_1287; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1106 = {hi_403, flags_0_go, _out_prepend_T_1106}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12362 = out_prepend_1106; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12363 = _out_T_12362; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1107 = _out_T_12363; // @[RegisterRouter.scala:87:24] wire out_rimask_1288 = |_out_rimask_T_1288; // @[RegisterRouter.scala:87:24] wire out_wimask_1288 = &_out_wimask_T_1288; // @[RegisterRouter.scala:87:24] wire out_romask_1288 = |_out_romask_T_1288; // @[RegisterRouter.scala:87:24] wire out_womask_1288 = &_out_womask_T_1288; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1288 = out_rivalid_1_1142 & out_rimask_1288; // @[RegisterRouter.scala:87:24] wire _out_T_12365 = out_f_rivalid_1288; // @[RegisterRouter.scala:87:24] wire out_f_roready_1288 = out_roready_1_1142 & out_romask_1288; // @[RegisterRouter.scala:87:24] wire _out_T_12366 = out_f_roready_1288; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1288 = out_wivalid_1_1142 & out_wimask_1288; // @[RegisterRouter.scala:87:24] wire out_f_woready_1288 = out_woready_1_1142 & out_womask_1288; // @[RegisterRouter.scala:87:24] wire _out_T_12367 = ~out_rimask_1288; // @[RegisterRouter.scala:87:24] wire _out_T_12368 = ~out_wimask_1288; // @[RegisterRouter.scala:87:24] wire _out_T_12369 = ~out_romask_1288; // @[RegisterRouter.scala:87:24] wire _out_T_12370 = ~out_womask_1288; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1107 = {hi_404, flags_0_go, _out_prepend_T_1107}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12371 = out_prepend_1107; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12372 = _out_T_12371; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1108 = _out_T_12372; // @[RegisterRouter.scala:87:24] wire out_rimask_1289 = |_out_rimask_T_1289; // @[RegisterRouter.scala:87:24] wire out_wimask_1289 = &_out_wimask_T_1289; // @[RegisterRouter.scala:87:24] wire out_romask_1289 = |_out_romask_T_1289; // @[RegisterRouter.scala:87:24] wire out_womask_1289 = &_out_womask_T_1289; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1289 = out_rivalid_1_1143 & out_rimask_1289; // @[RegisterRouter.scala:87:24] wire _out_T_12374 = out_f_rivalid_1289; // @[RegisterRouter.scala:87:24] wire out_f_roready_1289 = out_roready_1_1143 & out_romask_1289; // @[RegisterRouter.scala:87:24] wire _out_T_12375 = out_f_roready_1289; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1289 = out_wivalid_1_1143 & out_wimask_1289; // @[RegisterRouter.scala:87:24] wire out_f_woready_1289 = out_woready_1_1143 & out_womask_1289; // @[RegisterRouter.scala:87:24] wire _out_T_12376 = ~out_rimask_1289; // @[RegisterRouter.scala:87:24] wire _out_T_12377 = ~out_wimask_1289; // @[RegisterRouter.scala:87:24] wire _out_T_12378 = ~out_romask_1289; // @[RegisterRouter.scala:87:24] wire _out_T_12379 = ~out_womask_1289; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1108 = {hi_405, flags_0_go, _out_prepend_T_1108}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12380 = out_prepend_1108; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12381 = _out_T_12380; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1109 = _out_T_12381; // @[RegisterRouter.scala:87:24] wire out_rimask_1290 = |_out_rimask_T_1290; // @[RegisterRouter.scala:87:24] wire out_wimask_1290 = &_out_wimask_T_1290; // @[RegisterRouter.scala:87:24] wire out_romask_1290 = |_out_romask_T_1290; // @[RegisterRouter.scala:87:24] wire out_womask_1290 = &_out_womask_T_1290; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1290 = out_rivalid_1_1144 & out_rimask_1290; // @[RegisterRouter.scala:87:24] wire _out_T_12383 = out_f_rivalid_1290; // @[RegisterRouter.scala:87:24] wire out_f_roready_1290 = out_roready_1_1144 & out_romask_1290; // @[RegisterRouter.scala:87:24] wire _out_T_12384 = out_f_roready_1290; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1290 = out_wivalid_1_1144 & out_wimask_1290; // @[RegisterRouter.scala:87:24] wire out_f_woready_1290 = out_woready_1_1144 & out_womask_1290; // @[RegisterRouter.scala:87:24] wire _out_T_12385 = ~out_rimask_1290; // @[RegisterRouter.scala:87:24] wire _out_T_12386 = ~out_wimask_1290; // @[RegisterRouter.scala:87:24] wire _out_T_12387 = ~out_romask_1290; // @[RegisterRouter.scala:87:24] wire _out_T_12388 = ~out_womask_1290; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1109 = {hi_406, flags_0_go, _out_prepend_T_1109}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12389 = out_prepend_1109; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12390 = _out_T_12389; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1110 = _out_T_12390; // @[RegisterRouter.scala:87:24] wire out_rimask_1291 = |_out_rimask_T_1291; // @[RegisterRouter.scala:87:24] wire out_wimask_1291 = &_out_wimask_T_1291; // @[RegisterRouter.scala:87:24] wire out_romask_1291 = |_out_romask_T_1291; // @[RegisterRouter.scala:87:24] wire out_womask_1291 = &_out_womask_T_1291; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1291 = out_rivalid_1_1145 & out_rimask_1291; // @[RegisterRouter.scala:87:24] wire _out_T_12392 = out_f_rivalid_1291; // @[RegisterRouter.scala:87:24] wire out_f_roready_1291 = out_roready_1_1145 & out_romask_1291; // @[RegisterRouter.scala:87:24] wire _out_T_12393 = out_f_roready_1291; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1291 = out_wivalid_1_1145 & out_wimask_1291; // @[RegisterRouter.scala:87:24] wire out_f_woready_1291 = out_woready_1_1145 & out_womask_1291; // @[RegisterRouter.scala:87:24] wire _out_T_12394 = ~out_rimask_1291; // @[RegisterRouter.scala:87:24] wire _out_T_12395 = ~out_wimask_1291; // @[RegisterRouter.scala:87:24] wire _out_T_12396 = ~out_romask_1291; // @[RegisterRouter.scala:87:24] wire _out_T_12397 = ~out_womask_1291; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1110 = {hi_407, flags_0_go, _out_prepend_T_1110}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12398 = out_prepend_1110; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12399 = _out_T_12398; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1111 = _out_T_12399; // @[RegisterRouter.scala:87:24] wire out_rimask_1292 = |_out_rimask_T_1292; // @[RegisterRouter.scala:87:24] wire out_wimask_1292 = &_out_wimask_T_1292; // @[RegisterRouter.scala:87:24] wire out_romask_1292 = |_out_romask_T_1292; // @[RegisterRouter.scala:87:24] wire out_womask_1292 = &_out_womask_T_1292; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1292 = out_rivalid_1_1146 & out_rimask_1292; // @[RegisterRouter.scala:87:24] wire _out_T_12401 = out_f_rivalid_1292; // @[RegisterRouter.scala:87:24] wire out_f_roready_1292 = out_roready_1_1146 & out_romask_1292; // @[RegisterRouter.scala:87:24] wire _out_T_12402 = out_f_roready_1292; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1292 = out_wivalid_1_1146 & out_wimask_1292; // @[RegisterRouter.scala:87:24] wire out_f_woready_1292 = out_woready_1_1146 & out_womask_1292; // @[RegisterRouter.scala:87:24] wire _out_T_12403 = ~out_rimask_1292; // @[RegisterRouter.scala:87:24] wire _out_T_12404 = ~out_wimask_1292; // @[RegisterRouter.scala:87:24] wire _out_T_12405 = ~out_romask_1292; // @[RegisterRouter.scala:87:24] wire _out_T_12406 = ~out_womask_1292; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1111 = {hi_408, flags_0_go, _out_prepend_T_1111}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12407 = out_prepend_1111; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12408 = _out_T_12407; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_178 = _out_T_12408; // @[MuxLiteral.scala:49:48] wire out_rimask_1293 = |_out_rimask_T_1293; // @[RegisterRouter.scala:87:24] wire out_wimask_1293 = &_out_wimask_T_1293; // @[RegisterRouter.scala:87:24] wire out_romask_1293 = |_out_romask_T_1293; // @[RegisterRouter.scala:87:24] wire out_womask_1293 = &_out_womask_T_1293; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1293 = out_rivalid_1_1147 & out_rimask_1293; // @[RegisterRouter.scala:87:24] wire _out_T_12410 = out_f_rivalid_1293; // @[RegisterRouter.scala:87:24] wire out_f_roready_1293 = out_roready_1_1147 & out_romask_1293; // @[RegisterRouter.scala:87:24] wire _out_T_12411 = out_f_roready_1293; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1293 = out_wivalid_1_1147 & out_wimask_1293; // @[RegisterRouter.scala:87:24] wire out_f_woready_1293 = out_woready_1_1147 & out_womask_1293; // @[RegisterRouter.scala:87:24] wire _out_T_12412 = ~out_rimask_1293; // @[RegisterRouter.scala:87:24] wire _out_T_12413 = ~out_wimask_1293; // @[RegisterRouter.scala:87:24] wire _out_T_12414 = ~out_romask_1293; // @[RegisterRouter.scala:87:24] wire _out_T_12415 = ~out_womask_1293; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12417 = _out_T_12416; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1112 = _out_T_12417; // @[RegisterRouter.scala:87:24] wire out_rimask_1294 = |_out_rimask_T_1294; // @[RegisterRouter.scala:87:24] wire out_wimask_1294 = &_out_wimask_T_1294; // @[RegisterRouter.scala:87:24] wire out_romask_1294 = |_out_romask_T_1294; // @[RegisterRouter.scala:87:24] wire out_womask_1294 = &_out_womask_T_1294; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1294 = out_rivalid_1_1148 & out_rimask_1294; // @[RegisterRouter.scala:87:24] wire _out_T_12419 = out_f_rivalid_1294; // @[RegisterRouter.scala:87:24] wire out_f_roready_1294 = out_roready_1_1148 & out_romask_1294; // @[RegisterRouter.scala:87:24] wire _out_T_12420 = out_f_roready_1294; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1294 = out_wivalid_1_1148 & out_wimask_1294; // @[RegisterRouter.scala:87:24] wire out_f_woready_1294 = out_woready_1_1148 & out_womask_1294; // @[RegisterRouter.scala:87:24] wire _out_T_12421 = ~out_rimask_1294; // @[RegisterRouter.scala:87:24] wire _out_T_12422 = ~out_wimask_1294; // @[RegisterRouter.scala:87:24] wire _out_T_12423 = ~out_romask_1294; // @[RegisterRouter.scala:87:24] wire _out_T_12424 = ~out_womask_1294; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1112 = {hi_282, flags_0_go, _out_prepend_T_1112}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12425 = out_prepend_1112; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12426 = _out_T_12425; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1113 = _out_T_12426; // @[RegisterRouter.scala:87:24] wire out_rimask_1295 = |_out_rimask_T_1295; // @[RegisterRouter.scala:87:24] wire out_wimask_1295 = &_out_wimask_T_1295; // @[RegisterRouter.scala:87:24] wire out_romask_1295 = |_out_romask_T_1295; // @[RegisterRouter.scala:87:24] wire out_womask_1295 = &_out_womask_T_1295; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1295 = out_rivalid_1_1149 & out_rimask_1295; // @[RegisterRouter.scala:87:24] wire _out_T_12428 = out_f_rivalid_1295; // @[RegisterRouter.scala:87:24] wire out_f_roready_1295 = out_roready_1_1149 & out_romask_1295; // @[RegisterRouter.scala:87:24] wire _out_T_12429 = out_f_roready_1295; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1295 = out_wivalid_1_1149 & out_wimask_1295; // @[RegisterRouter.scala:87:24] wire out_f_woready_1295 = out_woready_1_1149 & out_womask_1295; // @[RegisterRouter.scala:87:24] wire _out_T_12430 = ~out_rimask_1295; // @[RegisterRouter.scala:87:24] wire _out_T_12431 = ~out_wimask_1295; // @[RegisterRouter.scala:87:24] wire _out_T_12432 = ~out_romask_1295; // @[RegisterRouter.scala:87:24] wire _out_T_12433 = ~out_womask_1295; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1113 = {hi_283, flags_0_go, _out_prepend_T_1113}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12434 = out_prepend_1113; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12435 = _out_T_12434; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1114 = _out_T_12435; // @[RegisterRouter.scala:87:24] wire out_rimask_1296 = |_out_rimask_T_1296; // @[RegisterRouter.scala:87:24] wire out_wimask_1296 = &_out_wimask_T_1296; // @[RegisterRouter.scala:87:24] wire out_romask_1296 = |_out_romask_T_1296; // @[RegisterRouter.scala:87:24] wire out_womask_1296 = &_out_womask_T_1296; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1296 = out_rivalid_1_1150 & out_rimask_1296; // @[RegisterRouter.scala:87:24] wire _out_T_12437 = out_f_rivalid_1296; // @[RegisterRouter.scala:87:24] wire out_f_roready_1296 = out_roready_1_1150 & out_romask_1296; // @[RegisterRouter.scala:87:24] wire _out_T_12438 = out_f_roready_1296; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1296 = out_wivalid_1_1150 & out_wimask_1296; // @[RegisterRouter.scala:87:24] wire out_f_woready_1296 = out_woready_1_1150 & out_womask_1296; // @[RegisterRouter.scala:87:24] wire _out_T_12439 = ~out_rimask_1296; // @[RegisterRouter.scala:87:24] wire _out_T_12440 = ~out_wimask_1296; // @[RegisterRouter.scala:87:24] wire _out_T_12441 = ~out_romask_1296; // @[RegisterRouter.scala:87:24] wire _out_T_12442 = ~out_womask_1296; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1114 = {hi_284, flags_0_go, _out_prepend_T_1114}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12443 = out_prepend_1114; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12444 = _out_T_12443; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1115 = _out_T_12444; // @[RegisterRouter.scala:87:24] wire out_rimask_1297 = |_out_rimask_T_1297; // @[RegisterRouter.scala:87:24] wire out_wimask_1297 = &_out_wimask_T_1297; // @[RegisterRouter.scala:87:24] wire out_romask_1297 = |_out_romask_T_1297; // @[RegisterRouter.scala:87:24] wire out_womask_1297 = &_out_womask_T_1297; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1297 = out_rivalid_1_1151 & out_rimask_1297; // @[RegisterRouter.scala:87:24] wire _out_T_12446 = out_f_rivalid_1297; // @[RegisterRouter.scala:87:24] wire out_f_roready_1297 = out_roready_1_1151 & out_romask_1297; // @[RegisterRouter.scala:87:24] wire _out_T_12447 = out_f_roready_1297; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1297 = out_wivalid_1_1151 & out_wimask_1297; // @[RegisterRouter.scala:87:24] wire out_f_woready_1297 = out_woready_1_1151 & out_womask_1297; // @[RegisterRouter.scala:87:24] wire _out_T_12448 = ~out_rimask_1297; // @[RegisterRouter.scala:87:24] wire _out_T_12449 = ~out_wimask_1297; // @[RegisterRouter.scala:87:24] wire _out_T_12450 = ~out_romask_1297; // @[RegisterRouter.scala:87:24] wire _out_T_12451 = ~out_womask_1297; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1115 = {hi_285, flags_0_go, _out_prepend_T_1115}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12452 = out_prepend_1115; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12453 = _out_T_12452; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1116 = _out_T_12453; // @[RegisterRouter.scala:87:24] wire out_rimask_1298 = |_out_rimask_T_1298; // @[RegisterRouter.scala:87:24] wire out_wimask_1298 = &_out_wimask_T_1298; // @[RegisterRouter.scala:87:24] wire out_romask_1298 = |_out_romask_T_1298; // @[RegisterRouter.scala:87:24] wire out_womask_1298 = &_out_womask_T_1298; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1298 = out_rivalid_1_1152 & out_rimask_1298; // @[RegisterRouter.scala:87:24] wire _out_T_12455 = out_f_rivalid_1298; // @[RegisterRouter.scala:87:24] wire out_f_roready_1298 = out_roready_1_1152 & out_romask_1298; // @[RegisterRouter.scala:87:24] wire _out_T_12456 = out_f_roready_1298; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1298 = out_wivalid_1_1152 & out_wimask_1298; // @[RegisterRouter.scala:87:24] wire out_f_woready_1298 = out_woready_1_1152 & out_womask_1298; // @[RegisterRouter.scala:87:24] wire _out_T_12457 = ~out_rimask_1298; // @[RegisterRouter.scala:87:24] wire _out_T_12458 = ~out_wimask_1298; // @[RegisterRouter.scala:87:24] wire _out_T_12459 = ~out_romask_1298; // @[RegisterRouter.scala:87:24] wire _out_T_12460 = ~out_womask_1298; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1116 = {hi_286, flags_0_go, _out_prepend_T_1116}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12461 = out_prepend_1116; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12462 = _out_T_12461; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1117 = _out_T_12462; // @[RegisterRouter.scala:87:24] wire out_rimask_1299 = |_out_rimask_T_1299; // @[RegisterRouter.scala:87:24] wire out_wimask_1299 = &_out_wimask_T_1299; // @[RegisterRouter.scala:87:24] wire out_romask_1299 = |_out_romask_T_1299; // @[RegisterRouter.scala:87:24] wire out_womask_1299 = &_out_womask_T_1299; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1299 = out_rivalid_1_1153 & out_rimask_1299; // @[RegisterRouter.scala:87:24] wire _out_T_12464 = out_f_rivalid_1299; // @[RegisterRouter.scala:87:24] wire out_f_roready_1299 = out_roready_1_1153 & out_romask_1299; // @[RegisterRouter.scala:87:24] wire _out_T_12465 = out_f_roready_1299; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1299 = out_wivalid_1_1153 & out_wimask_1299; // @[RegisterRouter.scala:87:24] wire out_f_woready_1299 = out_woready_1_1153 & out_womask_1299; // @[RegisterRouter.scala:87:24] wire _out_T_12466 = ~out_rimask_1299; // @[RegisterRouter.scala:87:24] wire _out_T_12467 = ~out_wimask_1299; // @[RegisterRouter.scala:87:24] wire _out_T_12468 = ~out_romask_1299; // @[RegisterRouter.scala:87:24] wire _out_T_12469 = ~out_womask_1299; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1117 = {hi_287, flags_0_go, _out_prepend_T_1117}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12470 = out_prepend_1117; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12471 = _out_T_12470; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1118 = _out_T_12471; // @[RegisterRouter.scala:87:24] wire out_rimask_1300 = |_out_rimask_T_1300; // @[RegisterRouter.scala:87:24] wire out_wimask_1300 = &_out_wimask_T_1300; // @[RegisterRouter.scala:87:24] wire out_romask_1300 = |_out_romask_T_1300; // @[RegisterRouter.scala:87:24] wire out_womask_1300 = &_out_womask_T_1300; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1300 = out_rivalid_1_1154 & out_rimask_1300; // @[RegisterRouter.scala:87:24] wire _out_T_12473 = out_f_rivalid_1300; // @[RegisterRouter.scala:87:24] wire out_f_roready_1300 = out_roready_1_1154 & out_romask_1300; // @[RegisterRouter.scala:87:24] wire _out_T_12474 = out_f_roready_1300; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1300 = out_wivalid_1_1154 & out_wimask_1300; // @[RegisterRouter.scala:87:24] wire out_f_woready_1300 = out_woready_1_1154 & out_womask_1300; // @[RegisterRouter.scala:87:24] wire _out_T_12475 = ~out_rimask_1300; // @[RegisterRouter.scala:87:24] wire _out_T_12476 = ~out_wimask_1300; // @[RegisterRouter.scala:87:24] wire _out_T_12477 = ~out_romask_1300; // @[RegisterRouter.scala:87:24] wire _out_T_12478 = ~out_womask_1300; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1118 = {hi_288, flags_0_go, _out_prepend_T_1118}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12479 = out_prepend_1118; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12480 = _out_T_12479; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_163 = _out_T_12480; // @[MuxLiteral.scala:49:48] wire out_rimask_1301 = |_out_rimask_T_1301; // @[RegisterRouter.scala:87:24] wire out_wimask_1301 = &_out_wimask_T_1301; // @[RegisterRouter.scala:87:24] wire out_romask_1301 = |_out_romask_T_1301; // @[RegisterRouter.scala:87:24] wire out_womask_1301 = &_out_womask_T_1301; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1301 = out_rivalid_1_1155 & out_rimask_1301; // @[RegisterRouter.scala:87:24] wire _out_T_12482 = out_f_rivalid_1301; // @[RegisterRouter.scala:87:24] wire out_f_roready_1301 = out_roready_1_1155 & out_romask_1301; // @[RegisterRouter.scala:87:24] wire _out_T_12483 = out_f_roready_1301; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1301 = out_wivalid_1_1155 & out_wimask_1301; // @[RegisterRouter.scala:87:24] wire out_f_woready_1301 = out_woready_1_1155 & out_womask_1301; // @[RegisterRouter.scala:87:24] wire _out_T_12484 = ~out_rimask_1301; // @[RegisterRouter.scala:87:24] wire _out_T_12485 = ~out_wimask_1301; // @[RegisterRouter.scala:87:24] wire _out_T_12486 = ~out_romask_1301; // @[RegisterRouter.scala:87:24] wire _out_T_12487 = ~out_womask_1301; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12489 = _out_T_12488; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1119 = _out_T_12489; // @[RegisterRouter.scala:87:24] wire out_rimask_1302 = |_out_rimask_T_1302; // @[RegisterRouter.scala:87:24] wire out_wimask_1302 = &_out_wimask_T_1302; // @[RegisterRouter.scala:87:24] wire out_romask_1302 = |_out_romask_T_1302; // @[RegisterRouter.scala:87:24] wire out_womask_1302 = &_out_womask_T_1302; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1302 = out_rivalid_1_1156 & out_rimask_1302; // @[RegisterRouter.scala:87:24] wire _out_T_12491 = out_f_rivalid_1302; // @[RegisterRouter.scala:87:24] wire out_f_roready_1302 = out_roready_1_1156 & out_romask_1302; // @[RegisterRouter.scala:87:24] wire _out_T_12492 = out_f_roready_1302; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1302 = out_wivalid_1_1156 & out_wimask_1302; // @[RegisterRouter.scala:87:24] wire out_f_woready_1302 = out_woready_1_1156 & out_womask_1302; // @[RegisterRouter.scala:87:24] wire _out_T_12493 = ~out_rimask_1302; // @[RegisterRouter.scala:87:24] wire _out_T_12494 = ~out_wimask_1302; // @[RegisterRouter.scala:87:24] wire _out_T_12495 = ~out_romask_1302; // @[RegisterRouter.scala:87:24] wire _out_T_12496 = ~out_womask_1302; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1119 = {hi_578, flags_0_go, _out_prepend_T_1119}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12497 = out_prepend_1119; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12498 = _out_T_12497; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1120 = _out_T_12498; // @[RegisterRouter.scala:87:24] wire out_rimask_1303 = |_out_rimask_T_1303; // @[RegisterRouter.scala:87:24] wire out_wimask_1303 = &_out_wimask_T_1303; // @[RegisterRouter.scala:87:24] wire out_romask_1303 = |_out_romask_T_1303; // @[RegisterRouter.scala:87:24] wire out_womask_1303 = &_out_womask_T_1303; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1303 = out_rivalid_1_1157 & out_rimask_1303; // @[RegisterRouter.scala:87:24] wire _out_T_12500 = out_f_rivalid_1303; // @[RegisterRouter.scala:87:24] wire out_f_roready_1303 = out_roready_1_1157 & out_romask_1303; // @[RegisterRouter.scala:87:24] wire _out_T_12501 = out_f_roready_1303; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1303 = out_wivalid_1_1157 & out_wimask_1303; // @[RegisterRouter.scala:87:24] wire out_f_woready_1303 = out_woready_1_1157 & out_womask_1303; // @[RegisterRouter.scala:87:24] wire _out_T_12502 = ~out_rimask_1303; // @[RegisterRouter.scala:87:24] wire _out_T_12503 = ~out_wimask_1303; // @[RegisterRouter.scala:87:24] wire _out_T_12504 = ~out_romask_1303; // @[RegisterRouter.scala:87:24] wire _out_T_12505 = ~out_womask_1303; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1120 = {hi_579, flags_0_go, _out_prepend_T_1120}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12506 = out_prepend_1120; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12507 = _out_T_12506; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1121 = _out_T_12507; // @[RegisterRouter.scala:87:24] wire out_rimask_1304 = |_out_rimask_T_1304; // @[RegisterRouter.scala:87:24] wire out_wimask_1304 = &_out_wimask_T_1304; // @[RegisterRouter.scala:87:24] wire out_romask_1304 = |_out_romask_T_1304; // @[RegisterRouter.scala:87:24] wire out_womask_1304 = &_out_womask_T_1304; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1304 = out_rivalid_1_1158 & out_rimask_1304; // @[RegisterRouter.scala:87:24] wire _out_T_12509 = out_f_rivalid_1304; // @[RegisterRouter.scala:87:24] wire out_f_roready_1304 = out_roready_1_1158 & out_romask_1304; // @[RegisterRouter.scala:87:24] wire _out_T_12510 = out_f_roready_1304; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1304 = out_wivalid_1_1158 & out_wimask_1304; // @[RegisterRouter.scala:87:24] wire out_f_woready_1304 = out_woready_1_1158 & out_womask_1304; // @[RegisterRouter.scala:87:24] wire _out_T_12511 = ~out_rimask_1304; // @[RegisterRouter.scala:87:24] wire _out_T_12512 = ~out_wimask_1304; // @[RegisterRouter.scala:87:24] wire _out_T_12513 = ~out_romask_1304; // @[RegisterRouter.scala:87:24] wire _out_T_12514 = ~out_womask_1304; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1121 = {hi_580, flags_0_go, _out_prepend_T_1121}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12515 = out_prepend_1121; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12516 = _out_T_12515; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1122 = _out_T_12516; // @[RegisterRouter.scala:87:24] wire out_rimask_1305 = |_out_rimask_T_1305; // @[RegisterRouter.scala:87:24] wire out_wimask_1305 = &_out_wimask_T_1305; // @[RegisterRouter.scala:87:24] wire out_romask_1305 = |_out_romask_T_1305; // @[RegisterRouter.scala:87:24] wire out_womask_1305 = &_out_womask_T_1305; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1305 = out_rivalid_1_1159 & out_rimask_1305; // @[RegisterRouter.scala:87:24] wire _out_T_12518 = out_f_rivalid_1305; // @[RegisterRouter.scala:87:24] wire out_f_roready_1305 = out_roready_1_1159 & out_romask_1305; // @[RegisterRouter.scala:87:24] wire _out_T_12519 = out_f_roready_1305; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1305 = out_wivalid_1_1159 & out_wimask_1305; // @[RegisterRouter.scala:87:24] wire out_f_woready_1305 = out_woready_1_1159 & out_womask_1305; // @[RegisterRouter.scala:87:24] wire _out_T_12520 = ~out_rimask_1305; // @[RegisterRouter.scala:87:24] wire _out_T_12521 = ~out_wimask_1305; // @[RegisterRouter.scala:87:24] wire _out_T_12522 = ~out_romask_1305; // @[RegisterRouter.scala:87:24] wire _out_T_12523 = ~out_womask_1305; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1122 = {hi_581, flags_0_go, _out_prepend_T_1122}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12524 = out_prepend_1122; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12525 = _out_T_12524; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1123 = _out_T_12525; // @[RegisterRouter.scala:87:24] wire out_rimask_1306 = |_out_rimask_T_1306; // @[RegisterRouter.scala:87:24] wire out_wimask_1306 = &_out_wimask_T_1306; // @[RegisterRouter.scala:87:24] wire out_romask_1306 = |_out_romask_T_1306; // @[RegisterRouter.scala:87:24] wire out_womask_1306 = &_out_womask_T_1306; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1306 = out_rivalid_1_1160 & out_rimask_1306; // @[RegisterRouter.scala:87:24] wire _out_T_12527 = out_f_rivalid_1306; // @[RegisterRouter.scala:87:24] wire out_f_roready_1306 = out_roready_1_1160 & out_romask_1306; // @[RegisterRouter.scala:87:24] wire _out_T_12528 = out_f_roready_1306; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1306 = out_wivalid_1_1160 & out_wimask_1306; // @[RegisterRouter.scala:87:24] wire out_f_woready_1306 = out_woready_1_1160 & out_womask_1306; // @[RegisterRouter.scala:87:24] wire _out_T_12529 = ~out_rimask_1306; // @[RegisterRouter.scala:87:24] wire _out_T_12530 = ~out_wimask_1306; // @[RegisterRouter.scala:87:24] wire _out_T_12531 = ~out_romask_1306; // @[RegisterRouter.scala:87:24] wire _out_T_12532 = ~out_womask_1306; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1123 = {hi_582, flags_0_go, _out_prepend_T_1123}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12533 = out_prepend_1123; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12534 = _out_T_12533; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1124 = _out_T_12534; // @[RegisterRouter.scala:87:24] wire out_rimask_1307 = |_out_rimask_T_1307; // @[RegisterRouter.scala:87:24] wire out_wimask_1307 = &_out_wimask_T_1307; // @[RegisterRouter.scala:87:24] wire out_romask_1307 = |_out_romask_T_1307; // @[RegisterRouter.scala:87:24] wire out_womask_1307 = &_out_womask_T_1307; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1307 = out_rivalid_1_1161 & out_rimask_1307; // @[RegisterRouter.scala:87:24] wire _out_T_12536 = out_f_rivalid_1307; // @[RegisterRouter.scala:87:24] wire out_f_roready_1307 = out_roready_1_1161 & out_romask_1307; // @[RegisterRouter.scala:87:24] wire _out_T_12537 = out_f_roready_1307; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1307 = out_wivalid_1_1161 & out_wimask_1307; // @[RegisterRouter.scala:87:24] wire out_f_woready_1307 = out_woready_1_1161 & out_womask_1307; // @[RegisterRouter.scala:87:24] wire _out_T_12538 = ~out_rimask_1307; // @[RegisterRouter.scala:87:24] wire _out_T_12539 = ~out_wimask_1307; // @[RegisterRouter.scala:87:24] wire _out_T_12540 = ~out_romask_1307; // @[RegisterRouter.scala:87:24] wire _out_T_12541 = ~out_womask_1307; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1124 = {hi_583, flags_0_go, _out_prepend_T_1124}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12542 = out_prepend_1124; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12543 = _out_T_12542; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1125 = _out_T_12543; // @[RegisterRouter.scala:87:24] wire out_rimask_1308 = |_out_rimask_T_1308; // @[RegisterRouter.scala:87:24] wire out_wimask_1308 = &_out_wimask_T_1308; // @[RegisterRouter.scala:87:24] wire out_romask_1308 = |_out_romask_T_1308; // @[RegisterRouter.scala:87:24] wire out_womask_1308 = &_out_womask_T_1308; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1308 = out_rivalid_1_1162 & out_rimask_1308; // @[RegisterRouter.scala:87:24] wire _out_T_12545 = out_f_rivalid_1308; // @[RegisterRouter.scala:87:24] wire out_f_roready_1308 = out_roready_1_1162 & out_romask_1308; // @[RegisterRouter.scala:87:24] wire _out_T_12546 = out_f_roready_1308; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1308 = out_wivalid_1_1162 & out_wimask_1308; // @[RegisterRouter.scala:87:24] wire out_f_woready_1308 = out_woready_1_1162 & out_womask_1308; // @[RegisterRouter.scala:87:24] wire _out_T_12547 = ~out_rimask_1308; // @[RegisterRouter.scala:87:24] wire _out_T_12548 = ~out_wimask_1308; // @[RegisterRouter.scala:87:24] wire _out_T_12549 = ~out_romask_1308; // @[RegisterRouter.scala:87:24] wire _out_T_12550 = ~out_womask_1308; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1125 = {hi_584, flags_0_go, _out_prepend_T_1125}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12551 = out_prepend_1125; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12552 = _out_T_12551; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_200 = _out_T_12552; // @[MuxLiteral.scala:49:48] wire out_rimask_1309 = |_out_rimask_T_1309; // @[RegisterRouter.scala:87:24] wire out_wimask_1309 = &_out_wimask_T_1309; // @[RegisterRouter.scala:87:24] wire out_romask_1309 = |_out_romask_T_1309; // @[RegisterRouter.scala:87:24] wire out_womask_1309 = &_out_womask_T_1309; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1309 = out_rivalid_1_1163 & out_rimask_1309; // @[RegisterRouter.scala:87:24] wire _out_T_12554 = out_f_rivalid_1309; // @[RegisterRouter.scala:87:24] wire out_f_roready_1309 = out_roready_1_1163 & out_romask_1309; // @[RegisterRouter.scala:87:24] wire _out_T_12555 = out_f_roready_1309; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1309 = out_wivalid_1_1163 & out_wimask_1309; // @[RegisterRouter.scala:87:24] wire _out_T_12556 = out_f_wivalid_1309; // @[RegisterRouter.scala:87:24] wire out_f_woready_1309 = out_woready_1_1163 & out_womask_1309; // @[RegisterRouter.scala:87:24] wire _out_T_12557 = out_f_woready_1309; // @[RegisterRouter.scala:87:24] wire _out_T_12558 = ~out_rimask_1309; // @[RegisterRouter.scala:87:24] wire _out_T_12559 = ~out_wimask_1309; // @[RegisterRouter.scala:87:24] wire _out_T_12560 = ~out_romask_1309; // @[RegisterRouter.scala:87:24] wire _out_T_12561 = ~out_womask_1309; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12563 = _out_T_12562; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1126 = _out_T_12563; // @[RegisterRouter.scala:87:24] wire out_rimask_1310 = |_out_rimask_T_1310; // @[RegisterRouter.scala:87:24] wire out_wimask_1310 = &_out_wimask_T_1310; // @[RegisterRouter.scala:87:24] wire out_romask_1310 = |_out_romask_T_1310; // @[RegisterRouter.scala:87:24] wire out_womask_1310 = &_out_womask_T_1310; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1310 = out_rivalid_1_1164 & out_rimask_1310; // @[RegisterRouter.scala:87:24] wire _out_T_12565 = out_f_rivalid_1310; // @[RegisterRouter.scala:87:24] wire out_f_roready_1310 = out_roready_1_1164 & out_romask_1310; // @[RegisterRouter.scala:87:24] wire _out_T_12566 = out_f_roready_1310; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1310 = out_wivalid_1_1164 & out_wimask_1310; // @[RegisterRouter.scala:87:24] wire _out_T_12567 = out_f_wivalid_1310; // @[RegisterRouter.scala:87:24] wire out_f_woready_1310 = out_woready_1_1164 & out_womask_1310; // @[RegisterRouter.scala:87:24] wire _out_T_12568 = out_f_woready_1310; // @[RegisterRouter.scala:87:24] wire _out_T_12569 = ~out_rimask_1310; // @[RegisterRouter.scala:87:24] wire _out_T_12570 = ~out_wimask_1310; // @[RegisterRouter.scala:87:24] wire _out_T_12571 = ~out_romask_1310; // @[RegisterRouter.scala:87:24] wire _out_T_12572 = ~out_womask_1310; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1126 = {programBufferMem_57, _out_prepend_T_1126}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12573 = out_prepend_1126; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12574 = _out_T_12573; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1127 = _out_T_12574; // @[RegisterRouter.scala:87:24] wire out_rimask_1311 = |_out_rimask_T_1311; // @[RegisterRouter.scala:87:24] wire out_wimask_1311 = &_out_wimask_T_1311; // @[RegisterRouter.scala:87:24] wire out_romask_1311 = |_out_romask_T_1311; // @[RegisterRouter.scala:87:24] wire out_womask_1311 = &_out_womask_T_1311; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1311 = out_rivalid_1_1165 & out_rimask_1311; // @[RegisterRouter.scala:87:24] wire _out_T_12576 = out_f_rivalid_1311; // @[RegisterRouter.scala:87:24] wire out_f_roready_1311 = out_roready_1_1165 & out_romask_1311; // @[RegisterRouter.scala:87:24] wire _out_T_12577 = out_f_roready_1311; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1311 = out_wivalid_1_1165 & out_wimask_1311; // @[RegisterRouter.scala:87:24] wire _out_T_12578 = out_f_wivalid_1311; // @[RegisterRouter.scala:87:24] wire out_f_woready_1311 = out_woready_1_1165 & out_womask_1311; // @[RegisterRouter.scala:87:24] wire _out_T_12579 = out_f_woready_1311; // @[RegisterRouter.scala:87:24] wire _out_T_12580 = ~out_rimask_1311; // @[RegisterRouter.scala:87:24] wire _out_T_12581 = ~out_wimask_1311; // @[RegisterRouter.scala:87:24] wire _out_T_12582 = ~out_romask_1311; // @[RegisterRouter.scala:87:24] wire _out_T_12583 = ~out_womask_1311; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1127 = {programBufferMem_58, _out_prepend_T_1127}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12584 = out_prepend_1127; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12585 = _out_T_12584; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1128 = _out_T_12585; // @[RegisterRouter.scala:87:24] wire out_rimask_1312 = |_out_rimask_T_1312; // @[RegisterRouter.scala:87:24] wire out_wimask_1312 = &_out_wimask_T_1312; // @[RegisterRouter.scala:87:24] wire out_romask_1312 = |_out_romask_T_1312; // @[RegisterRouter.scala:87:24] wire out_womask_1312 = &_out_womask_T_1312; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1312 = out_rivalid_1_1166 & out_rimask_1312; // @[RegisterRouter.scala:87:24] wire _out_T_12587 = out_f_rivalid_1312; // @[RegisterRouter.scala:87:24] wire out_f_roready_1312 = out_roready_1_1166 & out_romask_1312; // @[RegisterRouter.scala:87:24] wire _out_T_12588 = out_f_roready_1312; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1312 = out_wivalid_1_1166 & out_wimask_1312; // @[RegisterRouter.scala:87:24] wire _out_T_12589 = out_f_wivalid_1312; // @[RegisterRouter.scala:87:24] wire out_f_woready_1312 = out_woready_1_1166 & out_womask_1312; // @[RegisterRouter.scala:87:24] wire _out_T_12590 = out_f_woready_1312; // @[RegisterRouter.scala:87:24] wire _out_T_12591 = ~out_rimask_1312; // @[RegisterRouter.scala:87:24] wire _out_T_12592 = ~out_wimask_1312; // @[RegisterRouter.scala:87:24] wire _out_T_12593 = ~out_romask_1312; // @[RegisterRouter.scala:87:24] wire _out_T_12594 = ~out_womask_1312; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1128 = {programBufferMem_59, _out_prepend_T_1128}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12595 = out_prepend_1128; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12596 = _out_T_12595; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1129 = _out_T_12596; // @[RegisterRouter.scala:87:24] wire out_rimask_1313 = |_out_rimask_T_1313; // @[RegisterRouter.scala:87:24] wire out_wimask_1313 = &_out_wimask_T_1313; // @[RegisterRouter.scala:87:24] wire out_romask_1313 = |_out_romask_T_1313; // @[RegisterRouter.scala:87:24] wire out_womask_1313 = &_out_womask_T_1313; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1313 = out_rivalid_1_1167 & out_rimask_1313; // @[RegisterRouter.scala:87:24] wire _out_T_12598 = out_f_rivalid_1313; // @[RegisterRouter.scala:87:24] wire out_f_roready_1313 = out_roready_1_1167 & out_romask_1313; // @[RegisterRouter.scala:87:24] wire _out_T_12599 = out_f_roready_1313; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1313 = out_wivalid_1_1167 & out_wimask_1313; // @[RegisterRouter.scala:87:24] wire _out_T_12600 = out_f_wivalid_1313; // @[RegisterRouter.scala:87:24] wire out_f_woready_1313 = out_woready_1_1167 & out_womask_1313; // @[RegisterRouter.scala:87:24] wire _out_T_12601 = out_f_woready_1313; // @[RegisterRouter.scala:87:24] wire _out_T_12602 = ~out_rimask_1313; // @[RegisterRouter.scala:87:24] wire _out_T_12603 = ~out_wimask_1313; // @[RegisterRouter.scala:87:24] wire _out_T_12604 = ~out_romask_1313; // @[RegisterRouter.scala:87:24] wire _out_T_12605 = ~out_womask_1313; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1129 = {programBufferMem_60, _out_prepend_T_1129}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12606 = out_prepend_1129; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12607 = _out_T_12606; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1130 = _out_T_12607; // @[RegisterRouter.scala:87:24] wire out_rimask_1314 = |_out_rimask_T_1314; // @[RegisterRouter.scala:87:24] wire out_wimask_1314 = &_out_wimask_T_1314; // @[RegisterRouter.scala:87:24] wire out_romask_1314 = |_out_romask_T_1314; // @[RegisterRouter.scala:87:24] wire out_womask_1314 = &_out_womask_T_1314; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1314 = out_rivalid_1_1168 & out_rimask_1314; // @[RegisterRouter.scala:87:24] wire _out_T_12609 = out_f_rivalid_1314; // @[RegisterRouter.scala:87:24] wire out_f_roready_1314 = out_roready_1_1168 & out_romask_1314; // @[RegisterRouter.scala:87:24] wire _out_T_12610 = out_f_roready_1314; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1314 = out_wivalid_1_1168 & out_wimask_1314; // @[RegisterRouter.scala:87:24] wire _out_T_12611 = out_f_wivalid_1314; // @[RegisterRouter.scala:87:24] wire out_f_woready_1314 = out_woready_1_1168 & out_womask_1314; // @[RegisterRouter.scala:87:24] wire _out_T_12612 = out_f_woready_1314; // @[RegisterRouter.scala:87:24] wire _out_T_12613 = ~out_rimask_1314; // @[RegisterRouter.scala:87:24] wire _out_T_12614 = ~out_wimask_1314; // @[RegisterRouter.scala:87:24] wire _out_T_12615 = ~out_romask_1314; // @[RegisterRouter.scala:87:24] wire _out_T_12616 = ~out_womask_1314; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1130 = {programBufferMem_61, _out_prepend_T_1130}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12617 = out_prepend_1130; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12618 = _out_T_12617; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1131 = _out_T_12618; // @[RegisterRouter.scala:87:24] wire out_rimask_1315 = |_out_rimask_T_1315; // @[RegisterRouter.scala:87:24] wire out_wimask_1315 = &_out_wimask_T_1315; // @[RegisterRouter.scala:87:24] wire out_romask_1315 = |_out_romask_T_1315; // @[RegisterRouter.scala:87:24] wire out_womask_1315 = &_out_womask_T_1315; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1315 = out_rivalid_1_1169 & out_rimask_1315; // @[RegisterRouter.scala:87:24] wire _out_T_12620 = out_f_rivalid_1315; // @[RegisterRouter.scala:87:24] wire out_f_roready_1315 = out_roready_1_1169 & out_romask_1315; // @[RegisterRouter.scala:87:24] wire _out_T_12621 = out_f_roready_1315; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1315 = out_wivalid_1_1169 & out_wimask_1315; // @[RegisterRouter.scala:87:24] wire _out_T_12622 = out_f_wivalid_1315; // @[RegisterRouter.scala:87:24] wire out_f_woready_1315 = out_woready_1_1169 & out_womask_1315; // @[RegisterRouter.scala:87:24] wire _out_T_12623 = out_f_woready_1315; // @[RegisterRouter.scala:87:24] wire _out_T_12624 = ~out_rimask_1315; // @[RegisterRouter.scala:87:24] wire _out_T_12625 = ~out_wimask_1315; // @[RegisterRouter.scala:87:24] wire _out_T_12626 = ~out_romask_1315; // @[RegisterRouter.scala:87:24] wire _out_T_12627 = ~out_womask_1315; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1131 = {programBufferMem_62, _out_prepend_T_1131}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12628 = out_prepend_1131; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12629 = _out_T_12628; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1132 = _out_T_12629; // @[RegisterRouter.scala:87:24] wire out_rimask_1316 = |_out_rimask_T_1316; // @[RegisterRouter.scala:87:24] wire out_wimask_1316 = &_out_wimask_T_1316; // @[RegisterRouter.scala:87:24] wire out_romask_1316 = |_out_romask_T_1316; // @[RegisterRouter.scala:87:24] wire out_womask_1316 = &_out_womask_T_1316; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1316 = out_rivalid_1_1170 & out_rimask_1316; // @[RegisterRouter.scala:87:24] wire _out_T_12631 = out_f_rivalid_1316; // @[RegisterRouter.scala:87:24] wire out_f_roready_1316 = out_roready_1_1170 & out_romask_1316; // @[RegisterRouter.scala:87:24] wire _out_T_12632 = out_f_roready_1316; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1316 = out_wivalid_1_1170 & out_wimask_1316; // @[RegisterRouter.scala:87:24] wire _out_T_12633 = out_f_wivalid_1316; // @[RegisterRouter.scala:87:24] wire out_f_woready_1316 = out_woready_1_1170 & out_womask_1316; // @[RegisterRouter.scala:87:24] wire _out_T_12634 = out_f_woready_1316; // @[RegisterRouter.scala:87:24] wire _out_T_12635 = ~out_rimask_1316; // @[RegisterRouter.scala:87:24] wire _out_T_12636 = ~out_wimask_1316; // @[RegisterRouter.scala:87:24] wire _out_T_12637 = ~out_romask_1316; // @[RegisterRouter.scala:87:24] wire _out_T_12638 = ~out_womask_1316; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1132 = {programBufferMem_63, _out_prepend_T_1132}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12639 = out_prepend_1132; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12640 = _out_T_12639; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_111 = _out_T_12640; // @[MuxLiteral.scala:49:48] wire out_rimask_1317 = |_out_rimask_T_1317; // @[RegisterRouter.scala:87:24] wire out_wimask_1317 = &_out_wimask_T_1317; // @[RegisterRouter.scala:87:24] wire out_romask_1317 = |_out_romask_T_1317; // @[RegisterRouter.scala:87:24] wire out_womask_1317 = &_out_womask_T_1317; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1317 = out_rivalid_1_1171 & out_rimask_1317; // @[RegisterRouter.scala:87:24] wire _out_T_12642 = out_f_rivalid_1317; // @[RegisterRouter.scala:87:24] wire out_f_roready_1317 = out_roready_1_1171 & out_romask_1317; // @[RegisterRouter.scala:87:24] wire _out_T_12643 = out_f_roready_1317; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1317 = out_wivalid_1_1171 & out_wimask_1317; // @[RegisterRouter.scala:87:24] wire out_f_woready_1317 = out_woready_1_1171 & out_womask_1317; // @[RegisterRouter.scala:87:24] wire _out_T_12644 = ~out_rimask_1317; // @[RegisterRouter.scala:87:24] wire _out_T_12645 = ~out_wimask_1317; // @[RegisterRouter.scala:87:24] wire _out_T_12646 = ~out_romask_1317; // @[RegisterRouter.scala:87:24] wire _out_T_12647 = ~out_womask_1317; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12649 = _out_T_12648; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1133 = _out_T_12649; // @[RegisterRouter.scala:87:24] wire out_rimask_1318 = |_out_rimask_T_1318; // @[RegisterRouter.scala:87:24] wire out_wimask_1318 = &_out_wimask_T_1318; // @[RegisterRouter.scala:87:24] wire out_romask_1318 = |_out_romask_T_1318; // @[RegisterRouter.scala:87:24] wire out_womask_1318 = &_out_womask_T_1318; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1318 = out_rivalid_1_1172 & out_rimask_1318; // @[RegisterRouter.scala:87:24] wire _out_T_12651 = out_f_rivalid_1318; // @[RegisterRouter.scala:87:24] wire out_f_roready_1318 = out_roready_1_1172 & out_romask_1318; // @[RegisterRouter.scala:87:24] wire _out_T_12652 = out_f_roready_1318; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1318 = out_wivalid_1_1172 & out_wimask_1318; // @[RegisterRouter.scala:87:24] wire out_f_woready_1318 = out_woready_1_1172 & out_womask_1318; // @[RegisterRouter.scala:87:24] wire _out_T_12653 = ~out_rimask_1318; // @[RegisterRouter.scala:87:24] wire _out_T_12654 = ~out_wimask_1318; // @[RegisterRouter.scala:87:24] wire _out_T_12655 = ~out_romask_1318; // @[RegisterRouter.scala:87:24] wire _out_T_12656 = ~out_womask_1318; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1133 = {hi_698, flags_0_go, _out_prepend_T_1133}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12657 = out_prepend_1133; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12658 = _out_T_12657; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1134 = _out_T_12658; // @[RegisterRouter.scala:87:24] wire out_rimask_1319 = |_out_rimask_T_1319; // @[RegisterRouter.scala:87:24] wire out_wimask_1319 = &_out_wimask_T_1319; // @[RegisterRouter.scala:87:24] wire out_romask_1319 = |_out_romask_T_1319; // @[RegisterRouter.scala:87:24] wire out_womask_1319 = &_out_womask_T_1319; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1319 = out_rivalid_1_1173 & out_rimask_1319; // @[RegisterRouter.scala:87:24] wire _out_T_12660 = out_f_rivalid_1319; // @[RegisterRouter.scala:87:24] wire out_f_roready_1319 = out_roready_1_1173 & out_romask_1319; // @[RegisterRouter.scala:87:24] wire _out_T_12661 = out_f_roready_1319; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1319 = out_wivalid_1_1173 & out_wimask_1319; // @[RegisterRouter.scala:87:24] wire out_f_woready_1319 = out_woready_1_1173 & out_womask_1319; // @[RegisterRouter.scala:87:24] wire _out_T_12662 = ~out_rimask_1319; // @[RegisterRouter.scala:87:24] wire _out_T_12663 = ~out_wimask_1319; // @[RegisterRouter.scala:87:24] wire _out_T_12664 = ~out_romask_1319; // @[RegisterRouter.scala:87:24] wire _out_T_12665 = ~out_womask_1319; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1134 = {hi_699, flags_0_go, _out_prepend_T_1134}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12666 = out_prepend_1134; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12667 = _out_T_12666; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1135 = _out_T_12667; // @[RegisterRouter.scala:87:24] wire out_rimask_1320 = |_out_rimask_T_1320; // @[RegisterRouter.scala:87:24] wire out_wimask_1320 = &_out_wimask_T_1320; // @[RegisterRouter.scala:87:24] wire out_romask_1320 = |_out_romask_T_1320; // @[RegisterRouter.scala:87:24] wire out_womask_1320 = &_out_womask_T_1320; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1320 = out_rivalid_1_1174 & out_rimask_1320; // @[RegisterRouter.scala:87:24] wire _out_T_12669 = out_f_rivalid_1320; // @[RegisterRouter.scala:87:24] wire out_f_roready_1320 = out_roready_1_1174 & out_romask_1320; // @[RegisterRouter.scala:87:24] wire _out_T_12670 = out_f_roready_1320; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1320 = out_wivalid_1_1174 & out_wimask_1320; // @[RegisterRouter.scala:87:24] wire out_f_woready_1320 = out_woready_1_1174 & out_womask_1320; // @[RegisterRouter.scala:87:24] wire _out_T_12671 = ~out_rimask_1320; // @[RegisterRouter.scala:87:24] wire _out_T_12672 = ~out_wimask_1320; // @[RegisterRouter.scala:87:24] wire _out_T_12673 = ~out_romask_1320; // @[RegisterRouter.scala:87:24] wire _out_T_12674 = ~out_womask_1320; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1135 = {hi_700, flags_0_go, _out_prepend_T_1135}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12675 = out_prepend_1135; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12676 = _out_T_12675; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1136 = _out_T_12676; // @[RegisterRouter.scala:87:24] wire out_rimask_1321 = |_out_rimask_T_1321; // @[RegisterRouter.scala:87:24] wire out_wimask_1321 = &_out_wimask_T_1321; // @[RegisterRouter.scala:87:24] wire out_romask_1321 = |_out_romask_T_1321; // @[RegisterRouter.scala:87:24] wire out_womask_1321 = &_out_womask_T_1321; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1321 = out_rivalid_1_1175 & out_rimask_1321; // @[RegisterRouter.scala:87:24] wire _out_T_12678 = out_f_rivalid_1321; // @[RegisterRouter.scala:87:24] wire out_f_roready_1321 = out_roready_1_1175 & out_romask_1321; // @[RegisterRouter.scala:87:24] wire _out_T_12679 = out_f_roready_1321; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1321 = out_wivalid_1_1175 & out_wimask_1321; // @[RegisterRouter.scala:87:24] wire out_f_woready_1321 = out_woready_1_1175 & out_womask_1321; // @[RegisterRouter.scala:87:24] wire _out_T_12680 = ~out_rimask_1321; // @[RegisterRouter.scala:87:24] wire _out_T_12681 = ~out_wimask_1321; // @[RegisterRouter.scala:87:24] wire _out_T_12682 = ~out_romask_1321; // @[RegisterRouter.scala:87:24] wire _out_T_12683 = ~out_womask_1321; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1136 = {hi_701, flags_0_go, _out_prepend_T_1136}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12684 = out_prepend_1136; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12685 = _out_T_12684; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1137 = _out_T_12685; // @[RegisterRouter.scala:87:24] wire out_rimask_1322 = |_out_rimask_T_1322; // @[RegisterRouter.scala:87:24] wire out_wimask_1322 = &_out_wimask_T_1322; // @[RegisterRouter.scala:87:24] wire out_romask_1322 = |_out_romask_T_1322; // @[RegisterRouter.scala:87:24] wire out_womask_1322 = &_out_womask_T_1322; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1322 = out_rivalid_1_1176 & out_rimask_1322; // @[RegisterRouter.scala:87:24] wire _out_T_12687 = out_f_rivalid_1322; // @[RegisterRouter.scala:87:24] wire out_f_roready_1322 = out_roready_1_1176 & out_romask_1322; // @[RegisterRouter.scala:87:24] wire _out_T_12688 = out_f_roready_1322; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1322 = out_wivalid_1_1176 & out_wimask_1322; // @[RegisterRouter.scala:87:24] wire out_f_woready_1322 = out_woready_1_1176 & out_womask_1322; // @[RegisterRouter.scala:87:24] wire _out_T_12689 = ~out_rimask_1322; // @[RegisterRouter.scala:87:24] wire _out_T_12690 = ~out_wimask_1322; // @[RegisterRouter.scala:87:24] wire _out_T_12691 = ~out_romask_1322; // @[RegisterRouter.scala:87:24] wire _out_T_12692 = ~out_womask_1322; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1137 = {hi_702, flags_0_go, _out_prepend_T_1137}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12693 = out_prepend_1137; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12694 = _out_T_12693; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1138 = _out_T_12694; // @[RegisterRouter.scala:87:24] wire out_rimask_1323 = |_out_rimask_T_1323; // @[RegisterRouter.scala:87:24] wire out_wimask_1323 = &_out_wimask_T_1323; // @[RegisterRouter.scala:87:24] wire out_romask_1323 = |_out_romask_T_1323; // @[RegisterRouter.scala:87:24] wire out_womask_1323 = &_out_womask_T_1323; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1323 = out_rivalid_1_1177 & out_rimask_1323; // @[RegisterRouter.scala:87:24] wire _out_T_12696 = out_f_rivalid_1323; // @[RegisterRouter.scala:87:24] wire out_f_roready_1323 = out_roready_1_1177 & out_romask_1323; // @[RegisterRouter.scala:87:24] wire _out_T_12697 = out_f_roready_1323; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1323 = out_wivalid_1_1177 & out_wimask_1323; // @[RegisterRouter.scala:87:24] wire out_f_woready_1323 = out_woready_1_1177 & out_womask_1323; // @[RegisterRouter.scala:87:24] wire _out_T_12698 = ~out_rimask_1323; // @[RegisterRouter.scala:87:24] wire _out_T_12699 = ~out_wimask_1323; // @[RegisterRouter.scala:87:24] wire _out_T_12700 = ~out_romask_1323; // @[RegisterRouter.scala:87:24] wire _out_T_12701 = ~out_womask_1323; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1138 = {hi_703, flags_0_go, _out_prepend_T_1138}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12702 = out_prepend_1138; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12703 = _out_T_12702; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1139 = _out_T_12703; // @[RegisterRouter.scala:87:24] wire out_rimask_1324 = |_out_rimask_T_1324; // @[RegisterRouter.scala:87:24] wire out_wimask_1324 = &_out_wimask_T_1324; // @[RegisterRouter.scala:87:24] wire out_romask_1324 = |_out_romask_T_1324; // @[RegisterRouter.scala:87:24] wire out_womask_1324 = &_out_womask_T_1324; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1324 = out_rivalid_1_1178 & out_rimask_1324; // @[RegisterRouter.scala:87:24] wire _out_T_12705 = out_f_rivalid_1324; // @[RegisterRouter.scala:87:24] wire out_f_roready_1324 = out_roready_1_1178 & out_romask_1324; // @[RegisterRouter.scala:87:24] wire _out_T_12706 = out_f_roready_1324; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1324 = out_wivalid_1_1178 & out_wimask_1324; // @[RegisterRouter.scala:87:24] wire out_f_woready_1324 = out_woready_1_1178 & out_womask_1324; // @[RegisterRouter.scala:87:24] wire _out_T_12707 = ~out_rimask_1324; // @[RegisterRouter.scala:87:24] wire _out_T_12708 = ~out_wimask_1324; // @[RegisterRouter.scala:87:24] wire _out_T_12709 = ~out_romask_1324; // @[RegisterRouter.scala:87:24] wire _out_T_12710 = ~out_womask_1324; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1139 = {hi_704, flags_0_go, _out_prepend_T_1139}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12711 = out_prepend_1139; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12712 = _out_T_12711; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_215 = _out_T_12712; // @[MuxLiteral.scala:49:48] wire out_rimask_1325 = |_out_rimask_T_1325; // @[RegisterRouter.scala:87:24] wire out_wimask_1325 = &_out_wimask_T_1325; // @[RegisterRouter.scala:87:24] wire out_romask_1325 = |_out_romask_T_1325; // @[RegisterRouter.scala:87:24] wire out_womask_1325 = &_out_womask_T_1325; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1325 = out_rivalid_1_1179 & out_rimask_1325; // @[RegisterRouter.scala:87:24] wire _out_T_12714 = out_f_rivalid_1325; // @[RegisterRouter.scala:87:24] wire out_f_roready_1325 = out_roready_1_1179 & out_romask_1325; // @[RegisterRouter.scala:87:24] wire _out_T_12715 = out_f_roready_1325; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1325 = out_wivalid_1_1179 & out_wimask_1325; // @[RegisterRouter.scala:87:24] wire out_f_woready_1325 = out_woready_1_1179 & out_womask_1325; // @[RegisterRouter.scala:87:24] wire _out_T_12716 = ~out_rimask_1325; // @[RegisterRouter.scala:87:24] wire _out_T_12717 = ~out_wimask_1325; // @[RegisterRouter.scala:87:24] wire _out_T_12718 = ~out_romask_1325; // @[RegisterRouter.scala:87:24] wire _out_T_12719 = ~out_womask_1325; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12721 = _out_T_12720; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1140 = _out_T_12721; // @[RegisterRouter.scala:87:24] wire out_rimask_1326 = |_out_rimask_T_1326; // @[RegisterRouter.scala:87:24] wire out_wimask_1326 = &_out_wimask_T_1326; // @[RegisterRouter.scala:87:24] wire out_romask_1326 = |_out_romask_T_1326; // @[RegisterRouter.scala:87:24] wire out_womask_1326 = &_out_womask_T_1326; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1326 = out_rivalid_1_1180 & out_rimask_1326; // @[RegisterRouter.scala:87:24] wire _out_T_12723 = out_f_rivalid_1326; // @[RegisterRouter.scala:87:24] wire out_f_roready_1326 = out_roready_1_1180 & out_romask_1326; // @[RegisterRouter.scala:87:24] wire _out_T_12724 = out_f_roready_1326; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1326 = out_wivalid_1_1180 & out_wimask_1326; // @[RegisterRouter.scala:87:24] wire out_f_woready_1326 = out_woready_1_1180 & out_womask_1326; // @[RegisterRouter.scala:87:24] wire _out_T_12725 = ~out_rimask_1326; // @[RegisterRouter.scala:87:24] wire _out_T_12726 = ~out_wimask_1326; // @[RegisterRouter.scala:87:24] wire _out_T_12727 = ~out_romask_1326; // @[RegisterRouter.scala:87:24] wire _out_T_12728 = ~out_womask_1326; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1140 = {hi_754, flags_0_go, _out_prepend_T_1140}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12729 = out_prepend_1140; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12730 = _out_T_12729; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1141 = _out_T_12730; // @[RegisterRouter.scala:87:24] wire out_rimask_1327 = |_out_rimask_T_1327; // @[RegisterRouter.scala:87:24] wire out_wimask_1327 = &_out_wimask_T_1327; // @[RegisterRouter.scala:87:24] wire out_romask_1327 = |_out_romask_T_1327; // @[RegisterRouter.scala:87:24] wire out_womask_1327 = &_out_womask_T_1327; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1327 = out_rivalid_1_1181 & out_rimask_1327; // @[RegisterRouter.scala:87:24] wire _out_T_12732 = out_f_rivalid_1327; // @[RegisterRouter.scala:87:24] wire out_f_roready_1327 = out_roready_1_1181 & out_romask_1327; // @[RegisterRouter.scala:87:24] wire _out_T_12733 = out_f_roready_1327; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1327 = out_wivalid_1_1181 & out_wimask_1327; // @[RegisterRouter.scala:87:24] wire out_f_woready_1327 = out_woready_1_1181 & out_womask_1327; // @[RegisterRouter.scala:87:24] wire _out_T_12734 = ~out_rimask_1327; // @[RegisterRouter.scala:87:24] wire _out_T_12735 = ~out_wimask_1327; // @[RegisterRouter.scala:87:24] wire _out_T_12736 = ~out_romask_1327; // @[RegisterRouter.scala:87:24] wire _out_T_12737 = ~out_womask_1327; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1141 = {hi_755, flags_0_go, _out_prepend_T_1141}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12738 = out_prepend_1141; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12739 = _out_T_12738; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1142 = _out_T_12739; // @[RegisterRouter.scala:87:24] wire out_rimask_1328 = |_out_rimask_T_1328; // @[RegisterRouter.scala:87:24] wire out_wimask_1328 = &_out_wimask_T_1328; // @[RegisterRouter.scala:87:24] wire out_romask_1328 = |_out_romask_T_1328; // @[RegisterRouter.scala:87:24] wire out_womask_1328 = &_out_womask_T_1328; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1328 = out_rivalid_1_1182 & out_rimask_1328; // @[RegisterRouter.scala:87:24] wire _out_T_12741 = out_f_rivalid_1328; // @[RegisterRouter.scala:87:24] wire out_f_roready_1328 = out_roready_1_1182 & out_romask_1328; // @[RegisterRouter.scala:87:24] wire _out_T_12742 = out_f_roready_1328; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1328 = out_wivalid_1_1182 & out_wimask_1328; // @[RegisterRouter.scala:87:24] wire out_f_woready_1328 = out_woready_1_1182 & out_womask_1328; // @[RegisterRouter.scala:87:24] wire _out_T_12743 = ~out_rimask_1328; // @[RegisterRouter.scala:87:24] wire _out_T_12744 = ~out_wimask_1328; // @[RegisterRouter.scala:87:24] wire _out_T_12745 = ~out_romask_1328; // @[RegisterRouter.scala:87:24] wire _out_T_12746 = ~out_womask_1328; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1142 = {hi_756, flags_0_go, _out_prepend_T_1142}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12747 = out_prepend_1142; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12748 = _out_T_12747; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1143 = _out_T_12748; // @[RegisterRouter.scala:87:24] wire out_rimask_1329 = |_out_rimask_T_1329; // @[RegisterRouter.scala:87:24] wire out_wimask_1329 = &_out_wimask_T_1329; // @[RegisterRouter.scala:87:24] wire out_romask_1329 = |_out_romask_T_1329; // @[RegisterRouter.scala:87:24] wire out_womask_1329 = &_out_womask_T_1329; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1329 = out_rivalid_1_1183 & out_rimask_1329; // @[RegisterRouter.scala:87:24] wire _out_T_12750 = out_f_rivalid_1329; // @[RegisterRouter.scala:87:24] wire out_f_roready_1329 = out_roready_1_1183 & out_romask_1329; // @[RegisterRouter.scala:87:24] wire _out_T_12751 = out_f_roready_1329; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1329 = out_wivalid_1_1183 & out_wimask_1329; // @[RegisterRouter.scala:87:24] wire out_f_woready_1329 = out_woready_1_1183 & out_womask_1329; // @[RegisterRouter.scala:87:24] wire _out_T_12752 = ~out_rimask_1329; // @[RegisterRouter.scala:87:24] wire _out_T_12753 = ~out_wimask_1329; // @[RegisterRouter.scala:87:24] wire _out_T_12754 = ~out_romask_1329; // @[RegisterRouter.scala:87:24] wire _out_T_12755 = ~out_womask_1329; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1143 = {hi_757, flags_0_go, _out_prepend_T_1143}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12756 = out_prepend_1143; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12757 = _out_T_12756; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1144 = _out_T_12757; // @[RegisterRouter.scala:87:24] wire out_rimask_1330 = |_out_rimask_T_1330; // @[RegisterRouter.scala:87:24] wire out_wimask_1330 = &_out_wimask_T_1330; // @[RegisterRouter.scala:87:24] wire out_romask_1330 = |_out_romask_T_1330; // @[RegisterRouter.scala:87:24] wire out_womask_1330 = &_out_womask_T_1330; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1330 = out_rivalid_1_1184 & out_rimask_1330; // @[RegisterRouter.scala:87:24] wire _out_T_12759 = out_f_rivalid_1330; // @[RegisterRouter.scala:87:24] wire out_f_roready_1330 = out_roready_1_1184 & out_romask_1330; // @[RegisterRouter.scala:87:24] wire _out_T_12760 = out_f_roready_1330; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1330 = out_wivalid_1_1184 & out_wimask_1330; // @[RegisterRouter.scala:87:24] wire out_f_woready_1330 = out_woready_1_1184 & out_womask_1330; // @[RegisterRouter.scala:87:24] wire _out_T_12761 = ~out_rimask_1330; // @[RegisterRouter.scala:87:24] wire _out_T_12762 = ~out_wimask_1330; // @[RegisterRouter.scala:87:24] wire _out_T_12763 = ~out_romask_1330; // @[RegisterRouter.scala:87:24] wire _out_T_12764 = ~out_womask_1330; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1144 = {hi_758, flags_0_go, _out_prepend_T_1144}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12765 = out_prepend_1144; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12766 = _out_T_12765; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1145 = _out_T_12766; // @[RegisterRouter.scala:87:24] wire out_rimask_1331 = |_out_rimask_T_1331; // @[RegisterRouter.scala:87:24] wire out_wimask_1331 = &_out_wimask_T_1331; // @[RegisterRouter.scala:87:24] wire out_romask_1331 = |_out_romask_T_1331; // @[RegisterRouter.scala:87:24] wire out_womask_1331 = &_out_womask_T_1331; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1331 = out_rivalid_1_1185 & out_rimask_1331; // @[RegisterRouter.scala:87:24] wire _out_T_12768 = out_f_rivalid_1331; // @[RegisterRouter.scala:87:24] wire out_f_roready_1331 = out_roready_1_1185 & out_romask_1331; // @[RegisterRouter.scala:87:24] wire _out_T_12769 = out_f_roready_1331; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1331 = out_wivalid_1_1185 & out_wimask_1331; // @[RegisterRouter.scala:87:24] wire out_f_woready_1331 = out_woready_1_1185 & out_womask_1331; // @[RegisterRouter.scala:87:24] wire _out_T_12770 = ~out_rimask_1331; // @[RegisterRouter.scala:87:24] wire _out_T_12771 = ~out_wimask_1331; // @[RegisterRouter.scala:87:24] wire _out_T_12772 = ~out_romask_1331; // @[RegisterRouter.scala:87:24] wire _out_T_12773 = ~out_womask_1331; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1145 = {hi_759, flags_0_go, _out_prepend_T_1145}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12774 = out_prepend_1145; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12775 = _out_T_12774; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1146 = _out_T_12775; // @[RegisterRouter.scala:87:24] wire out_rimask_1332 = |_out_rimask_T_1332; // @[RegisterRouter.scala:87:24] wire out_wimask_1332 = &_out_wimask_T_1332; // @[RegisterRouter.scala:87:24] wire out_romask_1332 = |_out_romask_T_1332; // @[RegisterRouter.scala:87:24] wire out_womask_1332 = &_out_womask_T_1332; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1332 = out_rivalid_1_1186 & out_rimask_1332; // @[RegisterRouter.scala:87:24] wire _out_T_12777 = out_f_rivalid_1332; // @[RegisterRouter.scala:87:24] wire out_f_roready_1332 = out_roready_1_1186 & out_romask_1332; // @[RegisterRouter.scala:87:24] wire _out_T_12778 = out_f_roready_1332; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1332 = out_wivalid_1_1186 & out_wimask_1332; // @[RegisterRouter.scala:87:24] wire out_f_woready_1332 = out_woready_1_1186 & out_womask_1332; // @[RegisterRouter.scala:87:24] wire _out_T_12779 = ~out_rimask_1332; // @[RegisterRouter.scala:87:24] wire _out_T_12780 = ~out_wimask_1332; // @[RegisterRouter.scala:87:24] wire _out_T_12781 = ~out_romask_1332; // @[RegisterRouter.scala:87:24] wire _out_T_12782 = ~out_womask_1332; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1146 = {hi_760, flags_0_go, _out_prepend_T_1146}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12783 = out_prepend_1146; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12784 = _out_T_12783; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_222 = _out_T_12784; // @[MuxLiteral.scala:49:48] wire out_rimask_1333 = |_out_rimask_T_1333; // @[RegisterRouter.scala:87:24] wire out_wimask_1333 = &_out_wimask_T_1333; // @[RegisterRouter.scala:87:24] wire out_romask_1333 = |_out_romask_T_1333; // @[RegisterRouter.scala:87:24] wire out_womask_1333 = &_out_womask_T_1333; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1333 = out_rivalid_1_1187 & out_rimask_1333; // @[RegisterRouter.scala:87:24] wire _out_T_12786 = out_f_rivalid_1333; // @[RegisterRouter.scala:87:24] wire out_f_roready_1333 = out_roready_1_1187 & out_romask_1333; // @[RegisterRouter.scala:87:24] wire _out_T_12787 = out_f_roready_1333; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1333 = out_wivalid_1_1187 & out_wimask_1333; // @[RegisterRouter.scala:87:24] wire out_f_woready_1333 = out_woready_1_1187 & out_womask_1333; // @[RegisterRouter.scala:87:24] wire _out_T_12788 = ~out_rimask_1333; // @[RegisterRouter.scala:87:24] wire _out_T_12789 = ~out_wimask_1333; // @[RegisterRouter.scala:87:24] wire _out_T_12790 = ~out_romask_1333; // @[RegisterRouter.scala:87:24] wire _out_T_12791 = ~out_womask_1333; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12793 = _out_T_12792; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1147 = _out_T_12793; // @[RegisterRouter.scala:87:24] wire out_rimask_1334 = |_out_rimask_T_1334; // @[RegisterRouter.scala:87:24] wire out_wimask_1334 = &_out_wimask_T_1334; // @[RegisterRouter.scala:87:24] wire out_romask_1334 = |_out_romask_T_1334; // @[RegisterRouter.scala:87:24] wire out_womask_1334 = &_out_womask_T_1334; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1334 = out_rivalid_1_1188 & out_rimask_1334; // @[RegisterRouter.scala:87:24] wire _out_T_12795 = out_f_rivalid_1334; // @[RegisterRouter.scala:87:24] wire out_f_roready_1334 = out_roready_1_1188 & out_romask_1334; // @[RegisterRouter.scala:87:24] wire _out_T_12796 = out_f_roready_1334; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1334 = out_wivalid_1_1188 & out_wimask_1334; // @[RegisterRouter.scala:87:24] wire out_f_woready_1334 = out_woready_1_1188 & out_womask_1334; // @[RegisterRouter.scala:87:24] wire _out_T_12797 = ~out_rimask_1334; // @[RegisterRouter.scala:87:24] wire _out_T_12798 = ~out_wimask_1334; // @[RegisterRouter.scala:87:24] wire _out_T_12799 = ~out_romask_1334; // @[RegisterRouter.scala:87:24] wire _out_T_12800 = ~out_womask_1334; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1147 = {hi_834, flags_0_go, _out_prepend_T_1147}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12801 = out_prepend_1147; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12802 = _out_T_12801; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1148 = _out_T_12802; // @[RegisterRouter.scala:87:24] wire out_rimask_1335 = |_out_rimask_T_1335; // @[RegisterRouter.scala:87:24] wire out_wimask_1335 = &_out_wimask_T_1335; // @[RegisterRouter.scala:87:24] wire out_romask_1335 = |_out_romask_T_1335; // @[RegisterRouter.scala:87:24] wire out_womask_1335 = &_out_womask_T_1335; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1335 = out_rivalid_1_1189 & out_rimask_1335; // @[RegisterRouter.scala:87:24] wire _out_T_12804 = out_f_rivalid_1335; // @[RegisterRouter.scala:87:24] wire out_f_roready_1335 = out_roready_1_1189 & out_romask_1335; // @[RegisterRouter.scala:87:24] wire _out_T_12805 = out_f_roready_1335; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1335 = out_wivalid_1_1189 & out_wimask_1335; // @[RegisterRouter.scala:87:24] wire out_f_woready_1335 = out_woready_1_1189 & out_womask_1335; // @[RegisterRouter.scala:87:24] wire _out_T_12806 = ~out_rimask_1335; // @[RegisterRouter.scala:87:24] wire _out_T_12807 = ~out_wimask_1335; // @[RegisterRouter.scala:87:24] wire _out_T_12808 = ~out_romask_1335; // @[RegisterRouter.scala:87:24] wire _out_T_12809 = ~out_womask_1335; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1148 = {hi_835, flags_0_go, _out_prepend_T_1148}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12810 = out_prepend_1148; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12811 = _out_T_12810; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1149 = _out_T_12811; // @[RegisterRouter.scala:87:24] wire out_rimask_1336 = |_out_rimask_T_1336; // @[RegisterRouter.scala:87:24] wire out_wimask_1336 = &_out_wimask_T_1336; // @[RegisterRouter.scala:87:24] wire out_romask_1336 = |_out_romask_T_1336; // @[RegisterRouter.scala:87:24] wire out_womask_1336 = &_out_womask_T_1336; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1336 = out_rivalid_1_1190 & out_rimask_1336; // @[RegisterRouter.scala:87:24] wire _out_T_12813 = out_f_rivalid_1336; // @[RegisterRouter.scala:87:24] wire out_f_roready_1336 = out_roready_1_1190 & out_romask_1336; // @[RegisterRouter.scala:87:24] wire _out_T_12814 = out_f_roready_1336; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1336 = out_wivalid_1_1190 & out_wimask_1336; // @[RegisterRouter.scala:87:24] wire out_f_woready_1336 = out_woready_1_1190 & out_womask_1336; // @[RegisterRouter.scala:87:24] wire _out_T_12815 = ~out_rimask_1336; // @[RegisterRouter.scala:87:24] wire _out_T_12816 = ~out_wimask_1336; // @[RegisterRouter.scala:87:24] wire _out_T_12817 = ~out_romask_1336; // @[RegisterRouter.scala:87:24] wire _out_T_12818 = ~out_womask_1336; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1149 = {hi_836, flags_0_go, _out_prepend_T_1149}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12819 = out_prepend_1149; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12820 = _out_T_12819; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1150 = _out_T_12820; // @[RegisterRouter.scala:87:24] wire out_rimask_1337 = |_out_rimask_T_1337; // @[RegisterRouter.scala:87:24] wire out_wimask_1337 = &_out_wimask_T_1337; // @[RegisterRouter.scala:87:24] wire out_romask_1337 = |_out_romask_T_1337; // @[RegisterRouter.scala:87:24] wire out_womask_1337 = &_out_womask_T_1337; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1337 = out_rivalid_1_1191 & out_rimask_1337; // @[RegisterRouter.scala:87:24] wire _out_T_12822 = out_f_rivalid_1337; // @[RegisterRouter.scala:87:24] wire out_f_roready_1337 = out_roready_1_1191 & out_romask_1337; // @[RegisterRouter.scala:87:24] wire _out_T_12823 = out_f_roready_1337; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1337 = out_wivalid_1_1191 & out_wimask_1337; // @[RegisterRouter.scala:87:24] wire out_f_woready_1337 = out_woready_1_1191 & out_womask_1337; // @[RegisterRouter.scala:87:24] wire _out_T_12824 = ~out_rimask_1337; // @[RegisterRouter.scala:87:24] wire _out_T_12825 = ~out_wimask_1337; // @[RegisterRouter.scala:87:24] wire _out_T_12826 = ~out_romask_1337; // @[RegisterRouter.scala:87:24] wire _out_T_12827 = ~out_womask_1337; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1150 = {hi_837, flags_0_go, _out_prepend_T_1150}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12828 = out_prepend_1150; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12829 = _out_T_12828; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1151 = _out_T_12829; // @[RegisterRouter.scala:87:24] wire out_rimask_1338 = |_out_rimask_T_1338; // @[RegisterRouter.scala:87:24] wire out_wimask_1338 = &_out_wimask_T_1338; // @[RegisterRouter.scala:87:24] wire out_romask_1338 = |_out_romask_T_1338; // @[RegisterRouter.scala:87:24] wire out_womask_1338 = &_out_womask_T_1338; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1338 = out_rivalid_1_1192 & out_rimask_1338; // @[RegisterRouter.scala:87:24] wire _out_T_12831 = out_f_rivalid_1338; // @[RegisterRouter.scala:87:24] wire out_f_roready_1338 = out_roready_1_1192 & out_romask_1338; // @[RegisterRouter.scala:87:24] wire _out_T_12832 = out_f_roready_1338; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1338 = out_wivalid_1_1192 & out_wimask_1338; // @[RegisterRouter.scala:87:24] wire out_f_woready_1338 = out_woready_1_1192 & out_womask_1338; // @[RegisterRouter.scala:87:24] wire _out_T_12833 = ~out_rimask_1338; // @[RegisterRouter.scala:87:24] wire _out_T_12834 = ~out_wimask_1338; // @[RegisterRouter.scala:87:24] wire _out_T_12835 = ~out_romask_1338; // @[RegisterRouter.scala:87:24] wire _out_T_12836 = ~out_womask_1338; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1151 = {hi_838, flags_0_go, _out_prepend_T_1151}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12837 = out_prepend_1151; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12838 = _out_T_12837; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1152 = _out_T_12838; // @[RegisterRouter.scala:87:24] wire out_rimask_1339 = |_out_rimask_T_1339; // @[RegisterRouter.scala:87:24] wire out_wimask_1339 = &_out_wimask_T_1339; // @[RegisterRouter.scala:87:24] wire out_romask_1339 = |_out_romask_T_1339; // @[RegisterRouter.scala:87:24] wire out_womask_1339 = &_out_womask_T_1339; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1339 = out_rivalid_1_1193 & out_rimask_1339; // @[RegisterRouter.scala:87:24] wire _out_T_12840 = out_f_rivalid_1339; // @[RegisterRouter.scala:87:24] wire out_f_roready_1339 = out_roready_1_1193 & out_romask_1339; // @[RegisterRouter.scala:87:24] wire _out_T_12841 = out_f_roready_1339; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1339 = out_wivalid_1_1193 & out_wimask_1339; // @[RegisterRouter.scala:87:24] wire out_f_woready_1339 = out_woready_1_1193 & out_womask_1339; // @[RegisterRouter.scala:87:24] wire _out_T_12842 = ~out_rimask_1339; // @[RegisterRouter.scala:87:24] wire _out_T_12843 = ~out_wimask_1339; // @[RegisterRouter.scala:87:24] wire _out_T_12844 = ~out_romask_1339; // @[RegisterRouter.scala:87:24] wire _out_T_12845 = ~out_womask_1339; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1152 = {hi_839, flags_0_go, _out_prepend_T_1152}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12846 = out_prepend_1152; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12847 = _out_T_12846; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1153 = _out_T_12847; // @[RegisterRouter.scala:87:24] wire out_rimask_1340 = |_out_rimask_T_1340; // @[RegisterRouter.scala:87:24] wire out_wimask_1340 = &_out_wimask_T_1340; // @[RegisterRouter.scala:87:24] wire out_romask_1340 = |_out_romask_T_1340; // @[RegisterRouter.scala:87:24] wire out_womask_1340 = &_out_womask_T_1340; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1340 = out_rivalid_1_1194 & out_rimask_1340; // @[RegisterRouter.scala:87:24] wire _out_T_12849 = out_f_rivalid_1340; // @[RegisterRouter.scala:87:24] wire out_f_roready_1340 = out_roready_1_1194 & out_romask_1340; // @[RegisterRouter.scala:87:24] wire _out_T_12850 = out_f_roready_1340; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1340 = out_wivalid_1_1194 & out_wimask_1340; // @[RegisterRouter.scala:87:24] wire out_f_woready_1340 = out_woready_1_1194 & out_womask_1340; // @[RegisterRouter.scala:87:24] wire _out_T_12851 = ~out_rimask_1340; // @[RegisterRouter.scala:87:24] wire _out_T_12852 = ~out_wimask_1340; // @[RegisterRouter.scala:87:24] wire _out_T_12853 = ~out_romask_1340; // @[RegisterRouter.scala:87:24] wire _out_T_12854 = ~out_womask_1340; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1153 = {hi_840, flags_0_go, _out_prepend_T_1153}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12855 = out_prepend_1153; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12856 = _out_T_12855; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_232 = _out_T_12856; // @[MuxLiteral.scala:49:48] wire out_rimask_1341 = |_out_rimask_T_1341; // @[RegisterRouter.scala:87:24] wire out_wimask_1341 = &_out_wimask_T_1341; // @[RegisterRouter.scala:87:24] wire out_romask_1341 = |_out_romask_T_1341; // @[RegisterRouter.scala:87:24] wire out_womask_1341 = &_out_womask_T_1341; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1341 = out_rivalid_1_1195 & out_rimask_1341; // @[RegisterRouter.scala:87:24] wire _out_T_12858 = out_f_rivalid_1341; // @[RegisterRouter.scala:87:24] wire out_f_roready_1341 = out_roready_1_1195 & out_romask_1341; // @[RegisterRouter.scala:87:24] wire _out_T_12859 = out_f_roready_1341; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1341 = out_wivalid_1_1195 & out_wimask_1341; // @[RegisterRouter.scala:87:24] wire out_f_woready_1341 = out_woready_1_1195 & out_womask_1341; // @[RegisterRouter.scala:87:24] wire _out_T_12860 = ~out_rimask_1341; // @[RegisterRouter.scala:87:24] wire _out_T_12861 = ~out_wimask_1341; // @[RegisterRouter.scala:87:24] wire _out_T_12862 = ~out_romask_1341; // @[RegisterRouter.scala:87:24] wire _out_T_12863 = ~out_womask_1341; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12865 = _out_T_12864; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1154 = _out_T_12865; // @[RegisterRouter.scala:87:24] wire out_rimask_1342 = |_out_rimask_T_1342; // @[RegisterRouter.scala:87:24] wire out_wimask_1342 = &_out_wimask_T_1342; // @[RegisterRouter.scala:87:24] wire out_romask_1342 = |_out_romask_T_1342; // @[RegisterRouter.scala:87:24] wire out_womask_1342 = &_out_womask_T_1342; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1342 = out_rivalid_1_1196 & out_rimask_1342; // @[RegisterRouter.scala:87:24] wire _out_T_12867 = out_f_rivalid_1342; // @[RegisterRouter.scala:87:24] wire out_f_roready_1342 = out_roready_1_1196 & out_romask_1342; // @[RegisterRouter.scala:87:24] wire _out_T_12868 = out_f_roready_1342; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1342 = out_wivalid_1_1196 & out_wimask_1342; // @[RegisterRouter.scala:87:24] wire out_f_woready_1342 = out_woready_1_1196 & out_womask_1342; // @[RegisterRouter.scala:87:24] wire _out_T_12869 = ~out_rimask_1342; // @[RegisterRouter.scala:87:24] wire _out_T_12870 = ~out_wimask_1342; // @[RegisterRouter.scala:87:24] wire _out_T_12871 = ~out_romask_1342; // @[RegisterRouter.scala:87:24] wire _out_T_12872 = ~out_womask_1342; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1154 = {hi_1010, flags_0_go, _out_prepend_T_1154}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12873 = out_prepend_1154; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12874 = _out_T_12873; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1155 = _out_T_12874; // @[RegisterRouter.scala:87:24] wire out_rimask_1343 = |_out_rimask_T_1343; // @[RegisterRouter.scala:87:24] wire out_wimask_1343 = &_out_wimask_T_1343; // @[RegisterRouter.scala:87:24] wire out_romask_1343 = |_out_romask_T_1343; // @[RegisterRouter.scala:87:24] wire out_womask_1343 = &_out_womask_T_1343; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1343 = out_rivalid_1_1197 & out_rimask_1343; // @[RegisterRouter.scala:87:24] wire _out_T_12876 = out_f_rivalid_1343; // @[RegisterRouter.scala:87:24] wire out_f_roready_1343 = out_roready_1_1197 & out_romask_1343; // @[RegisterRouter.scala:87:24] wire _out_T_12877 = out_f_roready_1343; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1343 = out_wivalid_1_1197 & out_wimask_1343; // @[RegisterRouter.scala:87:24] wire out_f_woready_1343 = out_woready_1_1197 & out_womask_1343; // @[RegisterRouter.scala:87:24] wire _out_T_12878 = ~out_rimask_1343; // @[RegisterRouter.scala:87:24] wire _out_T_12879 = ~out_wimask_1343; // @[RegisterRouter.scala:87:24] wire _out_T_12880 = ~out_romask_1343; // @[RegisterRouter.scala:87:24] wire _out_T_12881 = ~out_womask_1343; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1155 = {hi_1011, flags_0_go, _out_prepend_T_1155}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12882 = out_prepend_1155; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12883 = _out_T_12882; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1156 = _out_T_12883; // @[RegisterRouter.scala:87:24] wire out_rimask_1344 = |_out_rimask_T_1344; // @[RegisterRouter.scala:87:24] wire out_wimask_1344 = &_out_wimask_T_1344; // @[RegisterRouter.scala:87:24] wire out_romask_1344 = |_out_romask_T_1344; // @[RegisterRouter.scala:87:24] wire out_womask_1344 = &_out_womask_T_1344; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1344 = out_rivalid_1_1198 & out_rimask_1344; // @[RegisterRouter.scala:87:24] wire _out_T_12885 = out_f_rivalid_1344; // @[RegisterRouter.scala:87:24] wire out_f_roready_1344 = out_roready_1_1198 & out_romask_1344; // @[RegisterRouter.scala:87:24] wire _out_T_12886 = out_f_roready_1344; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1344 = out_wivalid_1_1198 & out_wimask_1344; // @[RegisterRouter.scala:87:24] wire out_f_woready_1344 = out_woready_1_1198 & out_womask_1344; // @[RegisterRouter.scala:87:24] wire _out_T_12887 = ~out_rimask_1344; // @[RegisterRouter.scala:87:24] wire _out_T_12888 = ~out_wimask_1344; // @[RegisterRouter.scala:87:24] wire _out_T_12889 = ~out_romask_1344; // @[RegisterRouter.scala:87:24] wire _out_T_12890 = ~out_womask_1344; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1156 = {hi_1012, flags_0_go, _out_prepend_T_1156}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12891 = out_prepend_1156; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12892 = _out_T_12891; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1157 = _out_T_12892; // @[RegisterRouter.scala:87:24] wire out_rimask_1345 = |_out_rimask_T_1345; // @[RegisterRouter.scala:87:24] wire out_wimask_1345 = &_out_wimask_T_1345; // @[RegisterRouter.scala:87:24] wire out_romask_1345 = |_out_romask_T_1345; // @[RegisterRouter.scala:87:24] wire out_womask_1345 = &_out_womask_T_1345; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1345 = out_rivalid_1_1199 & out_rimask_1345; // @[RegisterRouter.scala:87:24] wire _out_T_12894 = out_f_rivalid_1345; // @[RegisterRouter.scala:87:24] wire out_f_roready_1345 = out_roready_1_1199 & out_romask_1345; // @[RegisterRouter.scala:87:24] wire _out_T_12895 = out_f_roready_1345; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1345 = out_wivalid_1_1199 & out_wimask_1345; // @[RegisterRouter.scala:87:24] wire out_f_woready_1345 = out_woready_1_1199 & out_womask_1345; // @[RegisterRouter.scala:87:24] wire _out_T_12896 = ~out_rimask_1345; // @[RegisterRouter.scala:87:24] wire _out_T_12897 = ~out_wimask_1345; // @[RegisterRouter.scala:87:24] wire _out_T_12898 = ~out_romask_1345; // @[RegisterRouter.scala:87:24] wire _out_T_12899 = ~out_womask_1345; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1157 = {hi_1013, flags_0_go, _out_prepend_T_1157}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12900 = out_prepend_1157; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12901 = _out_T_12900; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1158 = _out_T_12901; // @[RegisterRouter.scala:87:24] wire out_rimask_1346 = |_out_rimask_T_1346; // @[RegisterRouter.scala:87:24] wire out_wimask_1346 = &_out_wimask_T_1346; // @[RegisterRouter.scala:87:24] wire out_romask_1346 = |_out_romask_T_1346; // @[RegisterRouter.scala:87:24] wire out_womask_1346 = &_out_womask_T_1346; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1346 = out_rivalid_1_1200 & out_rimask_1346; // @[RegisterRouter.scala:87:24] wire _out_T_12903 = out_f_rivalid_1346; // @[RegisterRouter.scala:87:24] wire out_f_roready_1346 = out_roready_1_1200 & out_romask_1346; // @[RegisterRouter.scala:87:24] wire _out_T_12904 = out_f_roready_1346; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1346 = out_wivalid_1_1200 & out_wimask_1346; // @[RegisterRouter.scala:87:24] wire out_f_woready_1346 = out_woready_1_1200 & out_womask_1346; // @[RegisterRouter.scala:87:24] wire _out_T_12905 = ~out_rimask_1346; // @[RegisterRouter.scala:87:24] wire _out_T_12906 = ~out_wimask_1346; // @[RegisterRouter.scala:87:24] wire _out_T_12907 = ~out_romask_1346; // @[RegisterRouter.scala:87:24] wire _out_T_12908 = ~out_womask_1346; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1158 = {hi_1014, flags_0_go, _out_prepend_T_1158}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12909 = out_prepend_1158; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12910 = _out_T_12909; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1159 = _out_T_12910; // @[RegisterRouter.scala:87:24] wire out_rimask_1347 = |_out_rimask_T_1347; // @[RegisterRouter.scala:87:24] wire out_wimask_1347 = &_out_wimask_T_1347; // @[RegisterRouter.scala:87:24] wire out_romask_1347 = |_out_romask_T_1347; // @[RegisterRouter.scala:87:24] wire out_womask_1347 = &_out_womask_T_1347; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1347 = out_rivalid_1_1201 & out_rimask_1347; // @[RegisterRouter.scala:87:24] wire _out_T_12912 = out_f_rivalid_1347; // @[RegisterRouter.scala:87:24] wire out_f_roready_1347 = out_roready_1_1201 & out_romask_1347; // @[RegisterRouter.scala:87:24] wire _out_T_12913 = out_f_roready_1347; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1347 = out_wivalid_1_1201 & out_wimask_1347; // @[RegisterRouter.scala:87:24] wire out_f_woready_1347 = out_woready_1_1201 & out_womask_1347; // @[RegisterRouter.scala:87:24] wire _out_T_12914 = ~out_rimask_1347; // @[RegisterRouter.scala:87:24] wire _out_T_12915 = ~out_wimask_1347; // @[RegisterRouter.scala:87:24] wire _out_T_12916 = ~out_romask_1347; // @[RegisterRouter.scala:87:24] wire _out_T_12917 = ~out_womask_1347; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1159 = {hi_1015, flags_0_go, _out_prepend_T_1159}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12918 = out_prepend_1159; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12919 = _out_T_12918; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1160 = _out_T_12919; // @[RegisterRouter.scala:87:24] wire out_rimask_1348 = |_out_rimask_T_1348; // @[RegisterRouter.scala:87:24] wire out_wimask_1348 = &_out_wimask_T_1348; // @[RegisterRouter.scala:87:24] wire out_romask_1348 = |_out_romask_T_1348; // @[RegisterRouter.scala:87:24] wire out_womask_1348 = &_out_womask_T_1348; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1348 = out_rivalid_1_1202 & out_rimask_1348; // @[RegisterRouter.scala:87:24] wire _out_T_12921 = out_f_rivalid_1348; // @[RegisterRouter.scala:87:24] wire out_f_roready_1348 = out_roready_1_1202 & out_romask_1348; // @[RegisterRouter.scala:87:24] wire _out_T_12922 = out_f_roready_1348; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1348 = out_wivalid_1_1202 & out_wimask_1348; // @[RegisterRouter.scala:87:24] wire out_f_woready_1348 = out_woready_1_1202 & out_womask_1348; // @[RegisterRouter.scala:87:24] wire _out_T_12923 = ~out_rimask_1348; // @[RegisterRouter.scala:87:24] wire _out_T_12924 = ~out_wimask_1348; // @[RegisterRouter.scala:87:24] wire _out_T_12925 = ~out_romask_1348; // @[RegisterRouter.scala:87:24] wire _out_T_12926 = ~out_womask_1348; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1160 = {hi_1016, flags_0_go, _out_prepend_T_1160}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12927 = out_prepend_1160; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12928 = _out_T_12927; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_254 = _out_T_12928; // @[MuxLiteral.scala:49:48] wire out_rimask_1349 = |_out_rimask_T_1349; // @[RegisterRouter.scala:87:24] wire out_wimask_1349 = &_out_wimask_T_1349; // @[RegisterRouter.scala:87:24] wire out_romask_1349 = |_out_romask_T_1349; // @[RegisterRouter.scala:87:24] wire out_womask_1349 = &_out_womask_T_1349; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1349 = out_rivalid_1_1203 & out_rimask_1349; // @[RegisterRouter.scala:87:24] wire _out_T_12930 = out_f_rivalid_1349; // @[RegisterRouter.scala:87:24] wire out_f_roready_1349 = out_roready_1_1203 & out_romask_1349; // @[RegisterRouter.scala:87:24] wire _out_T_12931 = out_f_roready_1349; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1349 = out_wivalid_1_1203 & out_wimask_1349; // @[RegisterRouter.scala:87:24] wire out_f_woready_1349 = out_woready_1_1203 & out_womask_1349; // @[RegisterRouter.scala:87:24] wire _out_T_12932 = ~out_rimask_1349; // @[RegisterRouter.scala:87:24] wire _out_T_12933 = ~out_wimask_1349; // @[RegisterRouter.scala:87:24] wire _out_T_12934 = ~out_romask_1349; // @[RegisterRouter.scala:87:24] wire _out_T_12935 = ~out_womask_1349; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12937 = _out_T_12936; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1161 = _out_T_12937; // @[RegisterRouter.scala:87:24] wire out_rimask_1350 = |_out_rimask_T_1350; // @[RegisterRouter.scala:87:24] wire out_wimask_1350 = &_out_wimask_T_1350; // @[RegisterRouter.scala:87:24] wire out_romask_1350 = |_out_romask_T_1350; // @[RegisterRouter.scala:87:24] wire out_womask_1350 = &_out_womask_T_1350; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1350 = out_rivalid_1_1204 & out_rimask_1350; // @[RegisterRouter.scala:87:24] wire _out_T_12939 = out_f_rivalid_1350; // @[RegisterRouter.scala:87:24] wire out_f_roready_1350 = out_roready_1_1204 & out_romask_1350; // @[RegisterRouter.scala:87:24] wire _out_T_12940 = out_f_roready_1350; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1350 = out_wivalid_1_1204 & out_wimask_1350; // @[RegisterRouter.scala:87:24] wire out_f_woready_1350 = out_woready_1_1204 & out_womask_1350; // @[RegisterRouter.scala:87:24] wire _out_T_12941 = ~out_rimask_1350; // @[RegisterRouter.scala:87:24] wire _out_T_12942 = ~out_wimask_1350; // @[RegisterRouter.scala:87:24] wire _out_T_12943 = ~out_romask_1350; // @[RegisterRouter.scala:87:24] wire _out_T_12944 = ~out_womask_1350; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1161 = {hi_794, flags_0_go, _out_prepend_T_1161}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12945 = out_prepend_1161; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12946 = _out_T_12945; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1162 = _out_T_12946; // @[RegisterRouter.scala:87:24] wire out_rimask_1351 = |_out_rimask_T_1351; // @[RegisterRouter.scala:87:24] wire out_wimask_1351 = &_out_wimask_T_1351; // @[RegisterRouter.scala:87:24] wire out_romask_1351 = |_out_romask_T_1351; // @[RegisterRouter.scala:87:24] wire out_womask_1351 = &_out_womask_T_1351; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1351 = out_rivalid_1_1205 & out_rimask_1351; // @[RegisterRouter.scala:87:24] wire _out_T_12948 = out_f_rivalid_1351; // @[RegisterRouter.scala:87:24] wire out_f_roready_1351 = out_roready_1_1205 & out_romask_1351; // @[RegisterRouter.scala:87:24] wire _out_T_12949 = out_f_roready_1351; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1351 = out_wivalid_1_1205 & out_wimask_1351; // @[RegisterRouter.scala:87:24] wire out_f_woready_1351 = out_woready_1_1205 & out_womask_1351; // @[RegisterRouter.scala:87:24] wire _out_T_12950 = ~out_rimask_1351; // @[RegisterRouter.scala:87:24] wire _out_T_12951 = ~out_wimask_1351; // @[RegisterRouter.scala:87:24] wire _out_T_12952 = ~out_romask_1351; // @[RegisterRouter.scala:87:24] wire _out_T_12953 = ~out_womask_1351; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1162 = {hi_795, flags_0_go, _out_prepend_T_1162}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12954 = out_prepend_1162; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12955 = _out_T_12954; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1163 = _out_T_12955; // @[RegisterRouter.scala:87:24] wire out_rimask_1352 = |_out_rimask_T_1352; // @[RegisterRouter.scala:87:24] wire out_wimask_1352 = &_out_wimask_T_1352; // @[RegisterRouter.scala:87:24] wire out_romask_1352 = |_out_romask_T_1352; // @[RegisterRouter.scala:87:24] wire out_womask_1352 = &_out_womask_T_1352; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1352 = out_rivalid_1_1206 & out_rimask_1352; // @[RegisterRouter.scala:87:24] wire _out_T_12957 = out_f_rivalid_1352; // @[RegisterRouter.scala:87:24] wire out_f_roready_1352 = out_roready_1_1206 & out_romask_1352; // @[RegisterRouter.scala:87:24] wire _out_T_12958 = out_f_roready_1352; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1352 = out_wivalid_1_1206 & out_wimask_1352; // @[RegisterRouter.scala:87:24] wire out_f_woready_1352 = out_woready_1_1206 & out_womask_1352; // @[RegisterRouter.scala:87:24] wire _out_T_12959 = ~out_rimask_1352; // @[RegisterRouter.scala:87:24] wire _out_T_12960 = ~out_wimask_1352; // @[RegisterRouter.scala:87:24] wire _out_T_12961 = ~out_romask_1352; // @[RegisterRouter.scala:87:24] wire _out_T_12962 = ~out_womask_1352; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1163 = {hi_796, flags_0_go, _out_prepend_T_1163}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12963 = out_prepend_1163; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12964 = _out_T_12963; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1164 = _out_T_12964; // @[RegisterRouter.scala:87:24] wire out_rimask_1353 = |_out_rimask_T_1353; // @[RegisterRouter.scala:87:24] wire out_wimask_1353 = &_out_wimask_T_1353; // @[RegisterRouter.scala:87:24] wire out_romask_1353 = |_out_romask_T_1353; // @[RegisterRouter.scala:87:24] wire out_womask_1353 = &_out_womask_T_1353; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1353 = out_rivalid_1_1207 & out_rimask_1353; // @[RegisterRouter.scala:87:24] wire _out_T_12966 = out_f_rivalid_1353; // @[RegisterRouter.scala:87:24] wire out_f_roready_1353 = out_roready_1_1207 & out_romask_1353; // @[RegisterRouter.scala:87:24] wire _out_T_12967 = out_f_roready_1353; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1353 = out_wivalid_1_1207 & out_wimask_1353; // @[RegisterRouter.scala:87:24] wire out_f_woready_1353 = out_woready_1_1207 & out_womask_1353; // @[RegisterRouter.scala:87:24] wire _out_T_12968 = ~out_rimask_1353; // @[RegisterRouter.scala:87:24] wire _out_T_12969 = ~out_wimask_1353; // @[RegisterRouter.scala:87:24] wire _out_T_12970 = ~out_romask_1353; // @[RegisterRouter.scala:87:24] wire _out_T_12971 = ~out_womask_1353; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1164 = {hi_797, flags_0_go, _out_prepend_T_1164}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12972 = out_prepend_1164; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12973 = _out_T_12972; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1165 = _out_T_12973; // @[RegisterRouter.scala:87:24] wire out_rimask_1354 = |_out_rimask_T_1354; // @[RegisterRouter.scala:87:24] wire out_wimask_1354 = &_out_wimask_T_1354; // @[RegisterRouter.scala:87:24] wire out_romask_1354 = |_out_romask_T_1354; // @[RegisterRouter.scala:87:24] wire out_womask_1354 = &_out_womask_T_1354; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1354 = out_rivalid_1_1208 & out_rimask_1354; // @[RegisterRouter.scala:87:24] wire _out_T_12975 = out_f_rivalid_1354; // @[RegisterRouter.scala:87:24] wire out_f_roready_1354 = out_roready_1_1208 & out_romask_1354; // @[RegisterRouter.scala:87:24] wire _out_T_12976 = out_f_roready_1354; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1354 = out_wivalid_1_1208 & out_wimask_1354; // @[RegisterRouter.scala:87:24] wire out_f_woready_1354 = out_woready_1_1208 & out_womask_1354; // @[RegisterRouter.scala:87:24] wire _out_T_12977 = ~out_rimask_1354; // @[RegisterRouter.scala:87:24] wire _out_T_12978 = ~out_wimask_1354; // @[RegisterRouter.scala:87:24] wire _out_T_12979 = ~out_romask_1354; // @[RegisterRouter.scala:87:24] wire _out_T_12980 = ~out_womask_1354; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1165 = {hi_798, flags_0_go, _out_prepend_T_1165}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12981 = out_prepend_1165; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12982 = _out_T_12981; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1166 = _out_T_12982; // @[RegisterRouter.scala:87:24] wire out_rimask_1355 = |_out_rimask_T_1355; // @[RegisterRouter.scala:87:24] wire out_wimask_1355 = &_out_wimask_T_1355; // @[RegisterRouter.scala:87:24] wire out_romask_1355 = |_out_romask_T_1355; // @[RegisterRouter.scala:87:24] wire out_womask_1355 = &_out_womask_T_1355; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1355 = out_rivalid_1_1209 & out_rimask_1355; // @[RegisterRouter.scala:87:24] wire _out_T_12984 = out_f_rivalid_1355; // @[RegisterRouter.scala:87:24] wire out_f_roready_1355 = out_roready_1_1209 & out_romask_1355; // @[RegisterRouter.scala:87:24] wire _out_T_12985 = out_f_roready_1355; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1355 = out_wivalid_1_1209 & out_wimask_1355; // @[RegisterRouter.scala:87:24] wire out_f_woready_1355 = out_woready_1_1209 & out_womask_1355; // @[RegisterRouter.scala:87:24] wire _out_T_12986 = ~out_rimask_1355; // @[RegisterRouter.scala:87:24] wire _out_T_12987 = ~out_wimask_1355; // @[RegisterRouter.scala:87:24] wire _out_T_12988 = ~out_romask_1355; // @[RegisterRouter.scala:87:24] wire _out_T_12989 = ~out_womask_1355; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1166 = {hi_799, flags_0_go, _out_prepend_T_1166}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12990 = out_prepend_1166; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12991 = _out_T_12990; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1167 = _out_T_12991; // @[RegisterRouter.scala:87:24] wire out_rimask_1356 = |_out_rimask_T_1356; // @[RegisterRouter.scala:87:24] wire out_wimask_1356 = &_out_wimask_T_1356; // @[RegisterRouter.scala:87:24] wire out_romask_1356 = |_out_romask_T_1356; // @[RegisterRouter.scala:87:24] wire out_womask_1356 = &_out_womask_T_1356; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1356 = out_rivalid_1_1210 & out_rimask_1356; // @[RegisterRouter.scala:87:24] wire _out_T_12993 = out_f_rivalid_1356; // @[RegisterRouter.scala:87:24] wire out_f_roready_1356 = out_roready_1_1210 & out_romask_1356; // @[RegisterRouter.scala:87:24] wire _out_T_12994 = out_f_roready_1356; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1356 = out_wivalid_1_1210 & out_wimask_1356; // @[RegisterRouter.scala:87:24] wire out_f_woready_1356 = out_woready_1_1210 & out_womask_1356; // @[RegisterRouter.scala:87:24] wire _out_T_12995 = ~out_rimask_1356; // @[RegisterRouter.scala:87:24] wire _out_T_12996 = ~out_wimask_1356; // @[RegisterRouter.scala:87:24] wire _out_T_12997 = ~out_romask_1356; // @[RegisterRouter.scala:87:24] wire _out_T_12998 = ~out_womask_1356; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1167 = {hi_800, flags_0_go, _out_prepend_T_1167}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12999 = out_prepend_1167; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_13000 = _out_T_12999; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_227 = _out_T_13000; // @[MuxLiteral.scala:49:48] wire _out_iindex_T_7 = out_front_1_bits_index[0]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_7 = out_front_1_bits_index[0]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_8 = out_front_1_bits_index[1]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_8 = out_front_1_bits_index[1]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_9 = out_front_1_bits_index[2]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_9 = out_front_1_bits_index[2]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_10 = out_front_1_bits_index[3]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_10 = out_front_1_bits_index[3]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_11 = out_front_1_bits_index[4]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_11 = out_front_1_bits_index[4]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_12 = out_front_1_bits_index[5]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_12 = out_front_1_bits_index[5]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_13 = out_front_1_bits_index[6]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_13 = out_front_1_bits_index[6]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_14 = out_front_1_bits_index[7]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_14 = out_front_1_bits_index[7]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_15 = out_front_1_bits_index[8]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_15 = out_front_1_bits_index[8]; // @[RegisterRouter.scala:87:24] wire [1:0] out_iindex_lo_lo = {_out_iindex_T_8, _out_iindex_T_7}; // @[RegisterRouter.scala:87:24] wire [1:0] out_iindex_lo_hi_1 = {_out_iindex_T_10, _out_iindex_T_9}; // @[RegisterRouter.scala:87:24] wire [3:0] out_iindex_lo_1 = {out_iindex_lo_hi_1, out_iindex_lo_lo}; // @[RegisterRouter.scala:87:24] wire [1:0] out_iindex_hi_lo = {_out_iindex_T_12, _out_iindex_T_11}; // @[RegisterRouter.scala:87:24] wire [1:0] out_iindex_hi_hi_1 = {_out_iindex_T_14, _out_iindex_T_13}; // @[RegisterRouter.scala:87:24] wire [3:0] out_iindex_hi_1 = {out_iindex_hi_hi_1, out_iindex_hi_lo}; // @[RegisterRouter.scala:87:24] wire [7:0] out_iindex_1 = {out_iindex_hi_1, out_iindex_lo_1}; // @[RegisterRouter.scala:87:24] wire [1:0] out_oindex_lo_lo = {_out_oindex_T_8, _out_oindex_T_7}; // @[RegisterRouter.scala:87:24] wire [1:0] out_oindex_lo_hi_1 = {_out_oindex_T_10, _out_oindex_T_9}; // @[RegisterRouter.scala:87:24] wire [3:0] out_oindex_lo_1 = {out_oindex_lo_hi_1, out_oindex_lo_lo}; // @[RegisterRouter.scala:87:24] wire [1:0] out_oindex_hi_lo = {_out_oindex_T_12, _out_oindex_T_11}; // @[RegisterRouter.scala:87:24] wire [1:0] out_oindex_hi_hi_1 = {_out_oindex_T_14, _out_oindex_T_13}; // @[RegisterRouter.scala:87:24] wire [3:0] out_oindex_hi_1 = {out_oindex_hi_hi_1, out_oindex_hi_lo}; // @[RegisterRouter.scala:87:24] wire [7:0] out_oindex_1 = {out_oindex_hi_1, out_oindex_lo_1}; // @[RegisterRouter.scala:87:24] wire [255:0] _out_frontSel_T_1 = 256'h1 << out_iindex_1; // @[OneHot.scala:58:35] wire out_frontSel_0_1 = _out_frontSel_T_1[0]; // @[OneHot.scala:58:35] wire out_frontSel_1_1 = _out_frontSel_T_1[1]; // @[OneHot.scala:58:35] wire out_frontSel_2_1 = _out_frontSel_T_1[2]; // @[OneHot.scala:58:35] wire out_frontSel_3_1 = _out_frontSel_T_1[3]; // @[OneHot.scala:58:35] wire out_frontSel_4_1 = _out_frontSel_T_1[4]; // @[OneHot.scala:58:35] wire out_frontSel_5_1 = _out_frontSel_T_1[5]; // @[OneHot.scala:58:35] wire out_frontSel_6_1 = _out_frontSel_T_1[6]; // @[OneHot.scala:58:35] wire out_frontSel_7_1 = _out_frontSel_T_1[7]; // @[OneHot.scala:58:35] wire out_frontSel_8_1 = _out_frontSel_T_1[8]; // @[OneHot.scala:58:35] wire out_frontSel_9_1 = _out_frontSel_T_1[9]; // @[OneHot.scala:58:35] wire out_frontSel_10_1 = _out_frontSel_T_1[10]; // @[OneHot.scala:58:35] wire out_frontSel_11_1 = _out_frontSel_T_1[11]; // @[OneHot.scala:58:35] wire out_frontSel_12_1 = _out_frontSel_T_1[12]; // @[OneHot.scala:58:35] wire out_frontSel_13_1 = _out_frontSel_T_1[13]; // @[OneHot.scala:58:35] wire out_frontSel_14_1 = _out_frontSel_T_1[14]; // @[OneHot.scala:58:35] wire out_frontSel_15_1 = _out_frontSel_T_1[15]; // @[OneHot.scala:58:35] wire out_frontSel_16_1 = _out_frontSel_T_1[16]; // @[OneHot.scala:58:35] wire out_frontSel_17_1 = _out_frontSel_T_1[17]; // @[OneHot.scala:58:35] wire out_frontSel_18_1 = _out_frontSel_T_1[18]; // @[OneHot.scala:58:35] wire out_frontSel_19_1 = _out_frontSel_T_1[19]; // @[OneHot.scala:58:35] wire out_frontSel_20_1 = _out_frontSel_T_1[20]; // @[OneHot.scala:58:35] wire out_frontSel_21_1 = _out_frontSel_T_1[21]; // @[OneHot.scala:58:35] wire out_frontSel_22_1 = _out_frontSel_T_1[22]; // @[OneHot.scala:58:35] wire out_frontSel_23_1 = _out_frontSel_T_1[23]; // @[OneHot.scala:58:35] wire out_frontSel_24_1 = _out_frontSel_T_1[24]; // @[OneHot.scala:58:35] wire out_frontSel_25_1 = _out_frontSel_T_1[25]; // @[OneHot.scala:58:35] wire out_frontSel_26_1 = _out_frontSel_T_1[26]; // @[OneHot.scala:58:35] wire out_frontSel_27_1 = _out_frontSel_T_1[27]; // @[OneHot.scala:58:35] wire out_frontSel_28_1 = _out_frontSel_T_1[28]; // @[OneHot.scala:58:35] wire out_frontSel_29_1 = _out_frontSel_T_1[29]; // @[OneHot.scala:58:35] wire out_frontSel_30_1 = _out_frontSel_T_1[30]; // @[OneHot.scala:58:35] wire out_frontSel_31_1 = _out_frontSel_T_1[31]; // @[OneHot.scala:58:35] wire out_frontSel_32_1 = _out_frontSel_T_1[32]; // @[OneHot.scala:58:35] wire out_frontSel_33_1 = _out_frontSel_T_1[33]; // @[OneHot.scala:58:35] wire out_frontSel_34_1 = _out_frontSel_T_1[34]; // @[OneHot.scala:58:35] wire out_frontSel_35_1 = _out_frontSel_T_1[35]; // @[OneHot.scala:58:35] wire out_frontSel_36_1 = _out_frontSel_T_1[36]; // @[OneHot.scala:58:35] wire out_frontSel_37_1 = _out_frontSel_T_1[37]; // @[OneHot.scala:58:35] wire out_frontSel_38_1 = _out_frontSel_T_1[38]; // @[OneHot.scala:58:35] wire out_frontSel_39_1 = _out_frontSel_T_1[39]; // @[OneHot.scala:58:35] wire out_frontSel_40_1 = _out_frontSel_T_1[40]; // @[OneHot.scala:58:35] wire out_frontSel_41_1 = _out_frontSel_T_1[41]; // @[OneHot.scala:58:35] wire out_frontSel_42_1 = _out_frontSel_T_1[42]; // @[OneHot.scala:58:35] wire out_frontSel_43_1 = _out_frontSel_T_1[43]; // @[OneHot.scala:58:35] wire out_frontSel_44_1 = _out_frontSel_T_1[44]; // @[OneHot.scala:58:35] wire out_frontSel_45_1 = _out_frontSel_T_1[45]; // @[OneHot.scala:58:35] wire out_frontSel_46_1 = _out_frontSel_T_1[46]; // @[OneHot.scala:58:35] wire out_frontSel_47_1 = _out_frontSel_T_1[47]; // @[OneHot.scala:58:35] wire out_frontSel_48_1 = _out_frontSel_T_1[48]; // @[OneHot.scala:58:35] wire out_frontSel_49_1 = _out_frontSel_T_1[49]; // @[OneHot.scala:58:35] wire out_frontSel_50_1 = _out_frontSel_T_1[50]; // @[OneHot.scala:58:35] wire out_frontSel_51_1 = _out_frontSel_T_1[51]; // @[OneHot.scala:58:35] wire out_frontSel_52_1 = _out_frontSel_T_1[52]; // @[OneHot.scala:58:35] wire out_frontSel_53_1 = _out_frontSel_T_1[53]; // @[OneHot.scala:58:35] wire out_frontSel_54_1 = _out_frontSel_T_1[54]; // @[OneHot.scala:58:35] wire out_frontSel_55_1 = _out_frontSel_T_1[55]; // @[OneHot.scala:58:35] wire out_frontSel_56_1 = _out_frontSel_T_1[56]; // @[OneHot.scala:58:35] wire out_frontSel_57_1 = _out_frontSel_T_1[57]; // @[OneHot.scala:58:35] wire out_frontSel_58_1 = _out_frontSel_T_1[58]; // @[OneHot.scala:58:35] wire out_frontSel_59_1 = _out_frontSel_T_1[59]; // @[OneHot.scala:58:35] wire out_frontSel_60_1 = _out_frontSel_T_1[60]; // @[OneHot.scala:58:35] wire out_frontSel_61_1 = _out_frontSel_T_1[61]; // @[OneHot.scala:58:35] wire out_frontSel_62_1 = _out_frontSel_T_1[62]; // @[OneHot.scala:58:35] wire out_frontSel_63_1 = _out_frontSel_T_1[63]; // @[OneHot.scala:58:35] wire out_frontSel_64 = _out_frontSel_T_1[64]; // @[OneHot.scala:58:35] wire out_frontSel_65 = _out_frontSel_T_1[65]; // @[OneHot.scala:58:35] wire out_frontSel_66 = _out_frontSel_T_1[66]; // @[OneHot.scala:58:35] wire out_frontSel_67 = _out_frontSel_T_1[67]; // @[OneHot.scala:58:35] wire out_frontSel_68 = _out_frontSel_T_1[68]; // @[OneHot.scala:58:35] wire out_frontSel_69 = _out_frontSel_T_1[69]; // @[OneHot.scala:58:35] wire out_frontSel_70 = _out_frontSel_T_1[70]; // @[OneHot.scala:58:35] wire out_frontSel_71 = _out_frontSel_T_1[71]; // @[OneHot.scala:58:35] wire out_frontSel_72 = _out_frontSel_T_1[72]; // @[OneHot.scala:58:35] wire out_frontSel_73 = _out_frontSel_T_1[73]; // @[OneHot.scala:58:35] wire out_frontSel_74 = _out_frontSel_T_1[74]; // @[OneHot.scala:58:35] wire out_frontSel_75 = _out_frontSel_T_1[75]; // @[OneHot.scala:58:35] wire out_frontSel_76 = _out_frontSel_T_1[76]; // @[OneHot.scala:58:35] wire out_frontSel_77 = _out_frontSel_T_1[77]; // @[OneHot.scala:58:35] wire out_frontSel_78 = _out_frontSel_T_1[78]; // @[OneHot.scala:58:35] wire out_frontSel_79 = _out_frontSel_T_1[79]; // @[OneHot.scala:58:35] wire out_frontSel_80 = _out_frontSel_T_1[80]; // @[OneHot.scala:58:35] wire out_frontSel_81 = _out_frontSel_T_1[81]; // @[OneHot.scala:58:35] wire out_frontSel_82 = _out_frontSel_T_1[82]; // @[OneHot.scala:58:35] wire out_frontSel_83 = _out_frontSel_T_1[83]; // @[OneHot.scala:58:35] wire out_frontSel_84 = _out_frontSel_T_1[84]; // @[OneHot.scala:58:35] wire out_frontSel_85 = _out_frontSel_T_1[85]; // @[OneHot.scala:58:35] wire out_frontSel_86 = _out_frontSel_T_1[86]; // @[OneHot.scala:58:35] wire out_frontSel_87 = _out_frontSel_T_1[87]; // @[OneHot.scala:58:35] wire out_frontSel_88 = _out_frontSel_T_1[88]; // @[OneHot.scala:58:35] wire out_frontSel_89 = _out_frontSel_T_1[89]; // @[OneHot.scala:58:35] wire out_frontSel_90 = _out_frontSel_T_1[90]; // @[OneHot.scala:58:35] wire out_frontSel_91 = _out_frontSel_T_1[91]; // @[OneHot.scala:58:35] wire out_frontSel_92 = _out_frontSel_T_1[92]; // @[OneHot.scala:58:35] wire out_frontSel_93 = _out_frontSel_T_1[93]; // @[OneHot.scala:58:35] wire out_frontSel_94 = _out_frontSel_T_1[94]; // @[OneHot.scala:58:35] wire out_frontSel_95 = _out_frontSel_T_1[95]; // @[OneHot.scala:58:35] wire out_frontSel_96 = _out_frontSel_T_1[96]; // @[OneHot.scala:58:35] wire out_frontSel_97 = _out_frontSel_T_1[97]; // @[OneHot.scala:58:35] wire out_frontSel_98 = _out_frontSel_T_1[98]; // @[OneHot.scala:58:35] wire out_frontSel_99 = _out_frontSel_T_1[99]; // @[OneHot.scala:58:35] wire out_frontSel_100 = _out_frontSel_T_1[100]; // @[OneHot.scala:58:35] wire out_frontSel_101 = _out_frontSel_T_1[101]; // @[OneHot.scala:58:35] wire out_frontSel_102 = _out_frontSel_T_1[102]; // @[OneHot.scala:58:35] wire out_frontSel_103 = _out_frontSel_T_1[103]; // @[OneHot.scala:58:35] wire out_frontSel_104 = _out_frontSel_T_1[104]; // @[OneHot.scala:58:35] wire out_frontSel_105 = _out_frontSel_T_1[105]; // @[OneHot.scala:58:35] wire out_frontSel_106 = _out_frontSel_T_1[106]; // @[OneHot.scala:58:35] wire out_frontSel_107 = _out_frontSel_T_1[107]; // @[OneHot.scala:58:35] wire out_frontSel_108 = _out_frontSel_T_1[108]; // @[OneHot.scala:58:35] wire out_frontSel_109 = _out_frontSel_T_1[109]; // @[OneHot.scala:58:35] wire out_frontSel_110 = _out_frontSel_T_1[110]; // @[OneHot.scala:58:35] wire out_frontSel_111 = _out_frontSel_T_1[111]; // @[OneHot.scala:58:35] wire out_frontSel_112 = _out_frontSel_T_1[112]; // @[OneHot.scala:58:35] wire out_frontSel_113 = _out_frontSel_T_1[113]; // @[OneHot.scala:58:35] wire out_frontSel_114 = _out_frontSel_T_1[114]; // @[OneHot.scala:58:35] wire out_frontSel_115 = _out_frontSel_T_1[115]; // @[OneHot.scala:58:35] wire out_frontSel_116 = _out_frontSel_T_1[116]; // @[OneHot.scala:58:35] wire out_frontSel_117 = _out_frontSel_T_1[117]; // @[OneHot.scala:58:35] wire out_frontSel_118 = _out_frontSel_T_1[118]; // @[OneHot.scala:58:35] wire out_frontSel_119 = _out_frontSel_T_1[119]; // @[OneHot.scala:58:35] wire out_frontSel_120 = _out_frontSel_T_1[120]; // @[OneHot.scala:58:35] wire out_frontSel_121 = _out_frontSel_T_1[121]; // @[OneHot.scala:58:35] wire out_frontSel_122 = _out_frontSel_T_1[122]; // @[OneHot.scala:58:35] wire out_frontSel_123 = _out_frontSel_T_1[123]; // @[OneHot.scala:58:35] wire out_frontSel_124 = _out_frontSel_T_1[124]; // @[OneHot.scala:58:35] wire out_frontSel_125 = _out_frontSel_T_1[125]; // @[OneHot.scala:58:35] wire out_frontSel_126 = _out_frontSel_T_1[126]; // @[OneHot.scala:58:35] wire out_frontSel_127 = _out_frontSel_T_1[127]; // @[OneHot.scala:58:35] wire out_frontSel_128 = _out_frontSel_T_1[128]; // @[OneHot.scala:58:35] wire out_frontSel_129 = _out_frontSel_T_1[129]; // @[OneHot.scala:58:35] wire out_frontSel_130 = _out_frontSel_T_1[130]; // @[OneHot.scala:58:35] wire out_frontSel_131 = _out_frontSel_T_1[131]; // @[OneHot.scala:58:35] wire out_frontSel_132 = _out_frontSel_T_1[132]; // @[OneHot.scala:58:35] wire out_frontSel_133 = _out_frontSel_T_1[133]; // @[OneHot.scala:58:35] wire out_frontSel_134 = _out_frontSel_T_1[134]; // @[OneHot.scala:58:35] wire out_frontSel_135 = _out_frontSel_T_1[135]; // @[OneHot.scala:58:35] wire out_frontSel_136 = _out_frontSel_T_1[136]; // @[OneHot.scala:58:35] wire out_frontSel_137 = _out_frontSel_T_1[137]; // @[OneHot.scala:58:35] wire out_frontSel_138 = _out_frontSel_T_1[138]; // @[OneHot.scala:58:35] wire out_frontSel_139 = _out_frontSel_T_1[139]; // @[OneHot.scala:58:35] wire out_frontSel_140 = _out_frontSel_T_1[140]; // @[OneHot.scala:58:35] wire out_frontSel_141 = _out_frontSel_T_1[141]; // @[OneHot.scala:58:35] wire out_frontSel_142 = _out_frontSel_T_1[142]; // @[OneHot.scala:58:35] wire out_frontSel_143 = _out_frontSel_T_1[143]; // @[OneHot.scala:58:35] wire out_frontSel_144 = _out_frontSel_T_1[144]; // @[OneHot.scala:58:35] wire out_frontSel_145 = _out_frontSel_T_1[145]; // @[OneHot.scala:58:35] wire out_frontSel_146 = _out_frontSel_T_1[146]; // @[OneHot.scala:58:35] wire out_frontSel_147 = _out_frontSel_T_1[147]; // @[OneHot.scala:58:35] wire out_frontSel_148 = _out_frontSel_T_1[148]; // @[OneHot.scala:58:35] wire out_frontSel_149 = _out_frontSel_T_1[149]; // @[OneHot.scala:58:35] wire out_frontSel_150 = _out_frontSel_T_1[150]; // @[OneHot.scala:58:35] wire out_frontSel_151 = _out_frontSel_T_1[151]; // @[OneHot.scala:58:35] wire out_frontSel_152 = _out_frontSel_T_1[152]; // @[OneHot.scala:58:35] wire out_frontSel_153 = _out_frontSel_T_1[153]; // @[OneHot.scala:58:35] wire out_frontSel_154 = _out_frontSel_T_1[154]; // @[OneHot.scala:58:35] wire out_frontSel_155 = _out_frontSel_T_1[155]; // @[OneHot.scala:58:35] wire out_frontSel_156 = _out_frontSel_T_1[156]; // @[OneHot.scala:58:35] wire out_frontSel_157 = _out_frontSel_T_1[157]; // @[OneHot.scala:58:35] wire out_frontSel_158 = _out_frontSel_T_1[158]; // @[OneHot.scala:58:35] wire out_frontSel_159 = _out_frontSel_T_1[159]; // @[OneHot.scala:58:35] wire out_frontSel_160 = _out_frontSel_T_1[160]; // @[OneHot.scala:58:35] wire out_frontSel_161 = _out_frontSel_T_1[161]; // @[OneHot.scala:58:35] wire out_frontSel_162 = _out_frontSel_T_1[162]; // @[OneHot.scala:58:35] wire out_frontSel_163 = _out_frontSel_T_1[163]; // @[OneHot.scala:58:35] wire out_frontSel_164 = _out_frontSel_T_1[164]; // @[OneHot.scala:58:35] wire out_frontSel_165 = _out_frontSel_T_1[165]; // @[OneHot.scala:58:35] wire out_frontSel_166 = _out_frontSel_T_1[166]; // @[OneHot.scala:58:35] wire out_frontSel_167 = _out_frontSel_T_1[167]; // @[OneHot.scala:58:35] wire out_frontSel_168 = _out_frontSel_T_1[168]; // @[OneHot.scala:58:35] wire out_frontSel_169 = _out_frontSel_T_1[169]; // @[OneHot.scala:58:35] wire out_frontSel_170 = _out_frontSel_T_1[170]; // @[OneHot.scala:58:35] wire out_frontSel_171 = _out_frontSel_T_1[171]; // @[OneHot.scala:58:35] wire out_frontSel_172 = _out_frontSel_T_1[172]; // @[OneHot.scala:58:35] wire out_frontSel_173 = _out_frontSel_T_1[173]; // @[OneHot.scala:58:35] wire out_frontSel_174 = _out_frontSel_T_1[174]; // @[OneHot.scala:58:35] wire out_frontSel_175 = _out_frontSel_T_1[175]; // @[OneHot.scala:58:35] wire out_frontSel_176 = _out_frontSel_T_1[176]; // @[OneHot.scala:58:35] wire out_frontSel_177 = _out_frontSel_T_1[177]; // @[OneHot.scala:58:35] wire out_frontSel_178 = _out_frontSel_T_1[178]; // @[OneHot.scala:58:35] wire out_frontSel_179 = _out_frontSel_T_1[179]; // @[OneHot.scala:58:35] wire out_frontSel_180 = _out_frontSel_T_1[180]; // @[OneHot.scala:58:35] wire out_frontSel_181 = _out_frontSel_T_1[181]; // @[OneHot.scala:58:35] wire out_frontSel_182 = _out_frontSel_T_1[182]; // @[OneHot.scala:58:35] wire out_frontSel_183 = _out_frontSel_T_1[183]; // @[OneHot.scala:58:35] wire out_frontSel_184 = _out_frontSel_T_1[184]; // @[OneHot.scala:58:35] wire out_frontSel_185 = _out_frontSel_T_1[185]; // @[OneHot.scala:58:35] wire out_frontSel_186 = _out_frontSel_T_1[186]; // @[OneHot.scala:58:35] wire out_frontSel_187 = _out_frontSel_T_1[187]; // @[OneHot.scala:58:35] wire out_frontSel_188 = _out_frontSel_T_1[188]; // @[OneHot.scala:58:35] wire out_frontSel_189 = _out_frontSel_T_1[189]; // @[OneHot.scala:58:35] wire out_frontSel_190 = _out_frontSel_T_1[190]; // @[OneHot.scala:58:35] wire out_frontSel_191 = _out_frontSel_T_1[191]; // @[OneHot.scala:58:35] wire out_frontSel_192 = _out_frontSel_T_1[192]; // @[OneHot.scala:58:35] wire out_frontSel_193 = _out_frontSel_T_1[193]; // @[OneHot.scala:58:35] wire out_frontSel_194 = _out_frontSel_T_1[194]; // @[OneHot.scala:58:35] wire out_frontSel_195 = _out_frontSel_T_1[195]; // @[OneHot.scala:58:35] wire out_frontSel_196 = _out_frontSel_T_1[196]; // @[OneHot.scala:58:35] wire out_frontSel_197 = _out_frontSel_T_1[197]; // @[OneHot.scala:58:35] wire out_frontSel_198 = _out_frontSel_T_1[198]; // @[OneHot.scala:58:35] wire out_frontSel_199 = _out_frontSel_T_1[199]; // @[OneHot.scala:58:35] wire out_frontSel_200 = _out_frontSel_T_1[200]; // @[OneHot.scala:58:35] wire out_frontSel_201 = _out_frontSel_T_1[201]; // @[OneHot.scala:58:35] wire out_frontSel_202 = _out_frontSel_T_1[202]; // @[OneHot.scala:58:35] wire out_frontSel_203 = _out_frontSel_T_1[203]; // @[OneHot.scala:58:35] wire out_frontSel_204 = _out_frontSel_T_1[204]; // @[OneHot.scala:58:35] wire out_frontSel_205 = _out_frontSel_T_1[205]; // @[OneHot.scala:58:35] wire out_frontSel_206 = _out_frontSel_T_1[206]; // @[OneHot.scala:58:35] wire out_frontSel_207 = _out_frontSel_T_1[207]; // @[OneHot.scala:58:35] wire out_frontSel_208 = _out_frontSel_T_1[208]; // @[OneHot.scala:58:35] wire out_frontSel_209 = _out_frontSel_T_1[209]; // @[OneHot.scala:58:35] wire out_frontSel_210 = _out_frontSel_T_1[210]; // @[OneHot.scala:58:35] wire out_frontSel_211 = _out_frontSel_T_1[211]; // @[OneHot.scala:58:35] wire out_frontSel_212 = _out_frontSel_T_1[212]; // @[OneHot.scala:58:35] wire out_frontSel_213 = _out_frontSel_T_1[213]; // @[OneHot.scala:58:35] wire out_frontSel_214 = _out_frontSel_T_1[214]; // @[OneHot.scala:58:35] wire out_frontSel_215 = _out_frontSel_T_1[215]; // @[OneHot.scala:58:35] wire out_frontSel_216 = _out_frontSel_T_1[216]; // @[OneHot.scala:58:35] wire out_frontSel_217 = _out_frontSel_T_1[217]; // @[OneHot.scala:58:35] wire out_frontSel_218 = _out_frontSel_T_1[218]; // @[OneHot.scala:58:35] wire out_frontSel_219 = _out_frontSel_T_1[219]; // @[OneHot.scala:58:35] wire out_frontSel_220 = _out_frontSel_T_1[220]; // @[OneHot.scala:58:35] wire out_frontSel_221 = _out_frontSel_T_1[221]; // @[OneHot.scala:58:35] wire out_frontSel_222 = _out_frontSel_T_1[222]; // @[OneHot.scala:58:35] wire out_frontSel_223 = _out_frontSel_T_1[223]; // @[OneHot.scala:58:35] wire out_frontSel_224 = _out_frontSel_T_1[224]; // @[OneHot.scala:58:35] wire out_frontSel_225 = _out_frontSel_T_1[225]; // @[OneHot.scala:58:35] wire out_frontSel_226 = _out_frontSel_T_1[226]; // @[OneHot.scala:58:35] wire out_frontSel_227 = _out_frontSel_T_1[227]; // @[OneHot.scala:58:35] wire out_frontSel_228 = _out_frontSel_T_1[228]; // @[OneHot.scala:58:35] wire out_frontSel_229 = _out_frontSel_T_1[229]; // @[OneHot.scala:58:35] wire out_frontSel_230 = _out_frontSel_T_1[230]; // @[OneHot.scala:58:35] wire out_frontSel_231 = _out_frontSel_T_1[231]; // @[OneHot.scala:58:35] wire out_frontSel_232 = _out_frontSel_T_1[232]; // @[OneHot.scala:58:35] wire out_frontSel_233 = _out_frontSel_T_1[233]; // @[OneHot.scala:58:35] wire out_frontSel_234 = _out_frontSel_T_1[234]; // @[OneHot.scala:58:35] wire out_frontSel_235 = _out_frontSel_T_1[235]; // @[OneHot.scala:58:35] wire out_frontSel_236 = _out_frontSel_T_1[236]; // @[OneHot.scala:58:35] wire out_frontSel_237 = _out_frontSel_T_1[237]; // @[OneHot.scala:58:35] wire out_frontSel_238 = _out_frontSel_T_1[238]; // @[OneHot.scala:58:35] wire out_frontSel_239 = _out_frontSel_T_1[239]; // @[OneHot.scala:58:35] wire out_frontSel_240 = _out_frontSel_T_1[240]; // @[OneHot.scala:58:35] wire out_frontSel_241 = _out_frontSel_T_1[241]; // @[OneHot.scala:58:35] wire out_frontSel_242 = _out_frontSel_T_1[242]; // @[OneHot.scala:58:35] wire out_frontSel_243 = _out_frontSel_T_1[243]; // @[OneHot.scala:58:35] wire out_frontSel_244 = _out_frontSel_T_1[244]; // @[OneHot.scala:58:35] wire out_frontSel_245 = _out_frontSel_T_1[245]; // @[OneHot.scala:58:35] wire out_frontSel_246 = _out_frontSel_T_1[246]; // @[OneHot.scala:58:35] wire out_frontSel_247 = _out_frontSel_T_1[247]; // @[OneHot.scala:58:35] wire out_frontSel_248 = _out_frontSel_T_1[248]; // @[OneHot.scala:58:35] wire out_frontSel_249 = _out_frontSel_T_1[249]; // @[OneHot.scala:58:35] wire out_frontSel_250 = _out_frontSel_T_1[250]; // @[OneHot.scala:58:35] wire out_frontSel_251 = _out_frontSel_T_1[251]; // @[OneHot.scala:58:35] wire out_frontSel_252 = _out_frontSel_T_1[252]; // @[OneHot.scala:58:35] wire out_frontSel_253 = _out_frontSel_T_1[253]; // @[OneHot.scala:58:35] wire out_frontSel_254 = _out_frontSel_T_1[254]; // @[OneHot.scala:58:35] wire out_frontSel_255 = _out_frontSel_T_1[255]; // @[OneHot.scala:58:35] wire [255:0] _out_backSel_T_1 = 256'h1 << out_oindex_1; // @[OneHot.scala:58:35] wire out_backSel_0_1 = _out_backSel_T_1[0]; // @[OneHot.scala:58:35] wire out_backSel_1_1 = _out_backSel_T_1[1]; // @[OneHot.scala:58:35] wire out_backSel_2_1 = _out_backSel_T_1[2]; // @[OneHot.scala:58:35] wire out_backSel_3_1 = _out_backSel_T_1[3]; // @[OneHot.scala:58:35] wire out_backSel_4_1 = _out_backSel_T_1[4]; // @[OneHot.scala:58:35] wire out_backSel_5_1 = _out_backSel_T_1[5]; // @[OneHot.scala:58:35] wire out_backSel_6_1 = _out_backSel_T_1[6]; // @[OneHot.scala:58:35] wire out_backSel_7_1 = _out_backSel_T_1[7]; // @[OneHot.scala:58:35] wire out_backSel_8_1 = _out_backSel_T_1[8]; // @[OneHot.scala:58:35] wire out_backSel_9_1 = _out_backSel_T_1[9]; // @[OneHot.scala:58:35] wire out_backSel_10_1 = _out_backSel_T_1[10]; // @[OneHot.scala:58:35] wire out_backSel_11_1 = _out_backSel_T_1[11]; // @[OneHot.scala:58:35] wire out_backSel_12_1 = _out_backSel_T_1[12]; // @[OneHot.scala:58:35] wire out_backSel_13_1 = _out_backSel_T_1[13]; // @[OneHot.scala:58:35] wire out_backSel_14_1 = _out_backSel_T_1[14]; // @[OneHot.scala:58:35] wire out_backSel_15_1 = _out_backSel_T_1[15]; // @[OneHot.scala:58:35] wire out_backSel_16_1 = _out_backSel_T_1[16]; // @[OneHot.scala:58:35] wire out_backSel_17_1 = _out_backSel_T_1[17]; // @[OneHot.scala:58:35] wire out_backSel_18_1 = _out_backSel_T_1[18]; // @[OneHot.scala:58:35] wire out_backSel_19_1 = _out_backSel_T_1[19]; // @[OneHot.scala:58:35] wire out_backSel_20_1 = _out_backSel_T_1[20]; // @[OneHot.scala:58:35] wire out_backSel_21_1 = _out_backSel_T_1[21]; // @[OneHot.scala:58:35] wire out_backSel_22_1 = _out_backSel_T_1[22]; // @[OneHot.scala:58:35] wire out_backSel_23_1 = _out_backSel_T_1[23]; // @[OneHot.scala:58:35] wire out_backSel_24_1 = _out_backSel_T_1[24]; // @[OneHot.scala:58:35] wire out_backSel_25_1 = _out_backSel_T_1[25]; // @[OneHot.scala:58:35] wire out_backSel_26_1 = _out_backSel_T_1[26]; // @[OneHot.scala:58:35] wire out_backSel_27_1 = _out_backSel_T_1[27]; // @[OneHot.scala:58:35] wire out_backSel_28_1 = _out_backSel_T_1[28]; // @[OneHot.scala:58:35] wire out_backSel_29_1 = _out_backSel_T_1[29]; // @[OneHot.scala:58:35] wire out_backSel_30_1 = _out_backSel_T_1[30]; // @[OneHot.scala:58:35] wire out_backSel_31_1 = _out_backSel_T_1[31]; // @[OneHot.scala:58:35] wire out_backSel_32_1 = _out_backSel_T_1[32]; // @[OneHot.scala:58:35] wire out_backSel_33_1 = _out_backSel_T_1[33]; // @[OneHot.scala:58:35] wire out_backSel_34_1 = _out_backSel_T_1[34]; // @[OneHot.scala:58:35] wire out_backSel_35_1 = _out_backSel_T_1[35]; // @[OneHot.scala:58:35] wire out_backSel_36_1 = _out_backSel_T_1[36]; // @[OneHot.scala:58:35] wire out_backSel_37_1 = _out_backSel_T_1[37]; // @[OneHot.scala:58:35] wire out_backSel_38_1 = _out_backSel_T_1[38]; // @[OneHot.scala:58:35] wire out_backSel_39_1 = _out_backSel_T_1[39]; // @[OneHot.scala:58:35] wire out_backSel_40_1 = _out_backSel_T_1[40]; // @[OneHot.scala:58:35] wire out_backSel_41_1 = _out_backSel_T_1[41]; // @[OneHot.scala:58:35] wire out_backSel_42_1 = _out_backSel_T_1[42]; // @[OneHot.scala:58:35] wire out_backSel_43_1 = _out_backSel_T_1[43]; // @[OneHot.scala:58:35] wire out_backSel_44_1 = _out_backSel_T_1[44]; // @[OneHot.scala:58:35] wire out_backSel_45_1 = _out_backSel_T_1[45]; // @[OneHot.scala:58:35] wire out_backSel_46_1 = _out_backSel_T_1[46]; // @[OneHot.scala:58:35] wire out_backSel_47_1 = _out_backSel_T_1[47]; // @[OneHot.scala:58:35] wire out_backSel_48_1 = _out_backSel_T_1[48]; // @[OneHot.scala:58:35] wire out_backSel_49_1 = _out_backSel_T_1[49]; // @[OneHot.scala:58:35] wire out_backSel_50_1 = _out_backSel_T_1[50]; // @[OneHot.scala:58:35] wire out_backSel_51_1 = _out_backSel_T_1[51]; // @[OneHot.scala:58:35] wire out_backSel_52_1 = _out_backSel_T_1[52]; // @[OneHot.scala:58:35] wire out_backSel_53_1 = _out_backSel_T_1[53]; // @[OneHot.scala:58:35] wire out_backSel_54_1 = _out_backSel_T_1[54]; // @[OneHot.scala:58:35] wire out_backSel_55_1 = _out_backSel_T_1[55]; // @[OneHot.scala:58:35] wire out_backSel_56_1 = _out_backSel_T_1[56]; // @[OneHot.scala:58:35] wire out_backSel_57_1 = _out_backSel_T_1[57]; // @[OneHot.scala:58:35] wire out_backSel_58_1 = _out_backSel_T_1[58]; // @[OneHot.scala:58:35] wire out_backSel_59_1 = _out_backSel_T_1[59]; // @[OneHot.scala:58:35] wire out_backSel_60_1 = _out_backSel_T_1[60]; // @[OneHot.scala:58:35] wire out_backSel_61_1 = _out_backSel_T_1[61]; // @[OneHot.scala:58:35] wire out_backSel_62_1 = _out_backSel_T_1[62]; // @[OneHot.scala:58:35] wire out_backSel_63_1 = _out_backSel_T_1[63]; // @[OneHot.scala:58:35] wire out_backSel_64 = _out_backSel_T_1[64]; // @[OneHot.scala:58:35] wire out_backSel_65 = _out_backSel_T_1[65]; // @[OneHot.scala:58:35] wire out_backSel_66 = _out_backSel_T_1[66]; // @[OneHot.scala:58:35] wire out_backSel_67 = _out_backSel_T_1[67]; // @[OneHot.scala:58:35] wire out_backSel_68 = _out_backSel_T_1[68]; // @[OneHot.scala:58:35] wire out_backSel_69 = _out_backSel_T_1[69]; // @[OneHot.scala:58:35] wire out_backSel_70 = _out_backSel_T_1[70]; // @[OneHot.scala:58:35] wire out_backSel_71 = _out_backSel_T_1[71]; // @[OneHot.scala:58:35] wire out_backSel_72 = _out_backSel_T_1[72]; // @[OneHot.scala:58:35] wire out_backSel_73 = _out_backSel_T_1[73]; // @[OneHot.scala:58:35] wire out_backSel_74 = _out_backSel_T_1[74]; // @[OneHot.scala:58:35] wire out_backSel_75 = _out_backSel_T_1[75]; // @[OneHot.scala:58:35] wire out_backSel_76 = _out_backSel_T_1[76]; // @[OneHot.scala:58:35] wire out_backSel_77 = _out_backSel_T_1[77]; // @[OneHot.scala:58:35] wire out_backSel_78 = _out_backSel_T_1[78]; // @[OneHot.scala:58:35] wire out_backSel_79 = _out_backSel_T_1[79]; // @[OneHot.scala:58:35] wire out_backSel_80 = _out_backSel_T_1[80]; // @[OneHot.scala:58:35] wire out_backSel_81 = _out_backSel_T_1[81]; // @[OneHot.scala:58:35] wire out_backSel_82 = _out_backSel_T_1[82]; // @[OneHot.scala:58:35] wire out_backSel_83 = _out_backSel_T_1[83]; // @[OneHot.scala:58:35] wire out_backSel_84 = _out_backSel_T_1[84]; // @[OneHot.scala:58:35] wire out_backSel_85 = _out_backSel_T_1[85]; // @[OneHot.scala:58:35] wire out_backSel_86 = _out_backSel_T_1[86]; // @[OneHot.scala:58:35] wire out_backSel_87 = _out_backSel_T_1[87]; // @[OneHot.scala:58:35] wire out_backSel_88 = _out_backSel_T_1[88]; // @[OneHot.scala:58:35] wire out_backSel_89 = _out_backSel_T_1[89]; // @[OneHot.scala:58:35] wire out_backSel_90 = _out_backSel_T_1[90]; // @[OneHot.scala:58:35] wire out_backSel_91 = _out_backSel_T_1[91]; // @[OneHot.scala:58:35] wire out_backSel_92 = _out_backSel_T_1[92]; // @[OneHot.scala:58:35] wire out_backSel_93 = _out_backSel_T_1[93]; // @[OneHot.scala:58:35] wire out_backSel_94 = _out_backSel_T_1[94]; // @[OneHot.scala:58:35] wire out_backSel_95 = _out_backSel_T_1[95]; // @[OneHot.scala:58:35] wire out_backSel_96 = _out_backSel_T_1[96]; // @[OneHot.scala:58:35] wire out_backSel_97 = _out_backSel_T_1[97]; // @[OneHot.scala:58:35] wire out_backSel_98 = _out_backSel_T_1[98]; // @[OneHot.scala:58:35] wire out_backSel_99 = _out_backSel_T_1[99]; // @[OneHot.scala:58:35] wire out_backSel_100 = _out_backSel_T_1[100]; // @[OneHot.scala:58:35] wire out_backSel_101 = _out_backSel_T_1[101]; // @[OneHot.scala:58:35] wire out_backSel_102 = _out_backSel_T_1[102]; // @[OneHot.scala:58:35] wire out_backSel_103 = _out_backSel_T_1[103]; // @[OneHot.scala:58:35] wire out_backSel_104 = _out_backSel_T_1[104]; // @[OneHot.scala:58:35] wire out_backSel_105 = _out_backSel_T_1[105]; // @[OneHot.scala:58:35] wire out_backSel_106 = _out_backSel_T_1[106]; // @[OneHot.scala:58:35] wire out_backSel_107 = _out_backSel_T_1[107]; // @[OneHot.scala:58:35] wire out_backSel_108 = _out_backSel_T_1[108]; // @[OneHot.scala:58:35] wire out_backSel_109 = _out_backSel_T_1[109]; // @[OneHot.scala:58:35] wire out_backSel_110 = _out_backSel_T_1[110]; // @[OneHot.scala:58:35] wire out_backSel_111 = _out_backSel_T_1[111]; // @[OneHot.scala:58:35] wire out_backSel_112 = _out_backSel_T_1[112]; // @[OneHot.scala:58:35] wire out_backSel_113 = _out_backSel_T_1[113]; // @[OneHot.scala:58:35] wire out_backSel_114 = _out_backSel_T_1[114]; // @[OneHot.scala:58:35] wire out_backSel_115 = _out_backSel_T_1[115]; // @[OneHot.scala:58:35] wire out_backSel_116 = _out_backSel_T_1[116]; // @[OneHot.scala:58:35] wire out_backSel_117 = _out_backSel_T_1[117]; // @[OneHot.scala:58:35] wire out_backSel_118 = _out_backSel_T_1[118]; // @[OneHot.scala:58:35] wire out_backSel_119 = _out_backSel_T_1[119]; // @[OneHot.scala:58:35] wire out_backSel_120 = _out_backSel_T_1[120]; // @[OneHot.scala:58:35] wire out_backSel_121 = _out_backSel_T_1[121]; // @[OneHot.scala:58:35] wire out_backSel_122 = _out_backSel_T_1[122]; // @[OneHot.scala:58:35] wire out_backSel_123 = _out_backSel_T_1[123]; // @[OneHot.scala:58:35] wire out_backSel_124 = _out_backSel_T_1[124]; // @[OneHot.scala:58:35] wire out_backSel_125 = _out_backSel_T_1[125]; // @[OneHot.scala:58:35] wire out_backSel_126 = _out_backSel_T_1[126]; // @[OneHot.scala:58:35] wire out_backSel_127 = _out_backSel_T_1[127]; // @[OneHot.scala:58:35] wire out_backSel_128 = _out_backSel_T_1[128]; // @[OneHot.scala:58:35] wire out_backSel_129 = _out_backSel_T_1[129]; // @[OneHot.scala:58:35] wire out_backSel_130 = _out_backSel_T_1[130]; // @[OneHot.scala:58:35] wire out_backSel_131 = _out_backSel_T_1[131]; // @[OneHot.scala:58:35] wire out_backSel_132 = _out_backSel_T_1[132]; // @[OneHot.scala:58:35] wire out_backSel_133 = _out_backSel_T_1[133]; // @[OneHot.scala:58:35] wire out_backSel_134 = _out_backSel_T_1[134]; // @[OneHot.scala:58:35] wire out_backSel_135 = _out_backSel_T_1[135]; // @[OneHot.scala:58:35] wire out_backSel_136 = _out_backSel_T_1[136]; // @[OneHot.scala:58:35] wire out_backSel_137 = _out_backSel_T_1[137]; // @[OneHot.scala:58:35] wire out_backSel_138 = _out_backSel_T_1[138]; // @[OneHot.scala:58:35] wire out_backSel_139 = _out_backSel_T_1[139]; // @[OneHot.scala:58:35] wire out_backSel_140 = _out_backSel_T_1[140]; // @[OneHot.scala:58:35] wire out_backSel_141 = _out_backSel_T_1[141]; // @[OneHot.scala:58:35] wire out_backSel_142 = _out_backSel_T_1[142]; // @[OneHot.scala:58:35] wire out_backSel_143 = _out_backSel_T_1[143]; // @[OneHot.scala:58:35] wire out_backSel_144 = _out_backSel_T_1[144]; // @[OneHot.scala:58:35] wire out_backSel_145 = _out_backSel_T_1[145]; // @[OneHot.scala:58:35] wire out_backSel_146 = _out_backSel_T_1[146]; // @[OneHot.scala:58:35] wire out_backSel_147 = _out_backSel_T_1[147]; // @[OneHot.scala:58:35] wire out_backSel_148 = _out_backSel_T_1[148]; // @[OneHot.scala:58:35] wire out_backSel_149 = _out_backSel_T_1[149]; // @[OneHot.scala:58:35] wire out_backSel_150 = _out_backSel_T_1[150]; // @[OneHot.scala:58:35] wire out_backSel_151 = _out_backSel_T_1[151]; // @[OneHot.scala:58:35] wire out_backSel_152 = _out_backSel_T_1[152]; // @[OneHot.scala:58:35] wire out_backSel_153 = _out_backSel_T_1[153]; // @[OneHot.scala:58:35] wire out_backSel_154 = _out_backSel_T_1[154]; // @[OneHot.scala:58:35] wire out_backSel_155 = _out_backSel_T_1[155]; // @[OneHot.scala:58:35] wire out_backSel_156 = _out_backSel_T_1[156]; // @[OneHot.scala:58:35] wire out_backSel_157 = _out_backSel_T_1[157]; // @[OneHot.scala:58:35] wire out_backSel_158 = _out_backSel_T_1[158]; // @[OneHot.scala:58:35] wire out_backSel_159 = _out_backSel_T_1[159]; // @[OneHot.scala:58:35] wire out_backSel_160 = _out_backSel_T_1[160]; // @[OneHot.scala:58:35] wire out_backSel_161 = _out_backSel_T_1[161]; // @[OneHot.scala:58:35] wire out_backSel_162 = _out_backSel_T_1[162]; // @[OneHot.scala:58:35] wire out_backSel_163 = _out_backSel_T_1[163]; // @[OneHot.scala:58:35] wire out_backSel_164 = _out_backSel_T_1[164]; // @[OneHot.scala:58:35] wire out_backSel_165 = _out_backSel_T_1[165]; // @[OneHot.scala:58:35] wire out_backSel_166 = _out_backSel_T_1[166]; // @[OneHot.scala:58:35] wire out_backSel_167 = _out_backSel_T_1[167]; // @[OneHot.scala:58:35] wire out_backSel_168 = _out_backSel_T_1[168]; // @[OneHot.scala:58:35] wire out_backSel_169 = _out_backSel_T_1[169]; // @[OneHot.scala:58:35] wire out_backSel_170 = _out_backSel_T_1[170]; // @[OneHot.scala:58:35] wire out_backSel_171 = _out_backSel_T_1[171]; // @[OneHot.scala:58:35] wire out_backSel_172 = _out_backSel_T_1[172]; // @[OneHot.scala:58:35] wire out_backSel_173 = _out_backSel_T_1[173]; // @[OneHot.scala:58:35] wire out_backSel_174 = _out_backSel_T_1[174]; // @[OneHot.scala:58:35] wire out_backSel_175 = _out_backSel_T_1[175]; // @[OneHot.scala:58:35] wire out_backSel_176 = _out_backSel_T_1[176]; // @[OneHot.scala:58:35] wire out_backSel_177 = _out_backSel_T_1[177]; // @[OneHot.scala:58:35] wire out_backSel_178 = _out_backSel_T_1[178]; // @[OneHot.scala:58:35] wire out_backSel_179 = _out_backSel_T_1[179]; // @[OneHot.scala:58:35] wire out_backSel_180 = _out_backSel_T_1[180]; // @[OneHot.scala:58:35] wire out_backSel_181 = _out_backSel_T_1[181]; // @[OneHot.scala:58:35] wire out_backSel_182 = _out_backSel_T_1[182]; // @[OneHot.scala:58:35] wire out_backSel_183 = _out_backSel_T_1[183]; // @[OneHot.scala:58:35] wire out_backSel_184 = _out_backSel_T_1[184]; // @[OneHot.scala:58:35] wire out_backSel_185 = _out_backSel_T_1[185]; // @[OneHot.scala:58:35] wire out_backSel_186 = _out_backSel_T_1[186]; // @[OneHot.scala:58:35] wire out_backSel_187 = _out_backSel_T_1[187]; // @[OneHot.scala:58:35] wire out_backSel_188 = _out_backSel_T_1[188]; // @[OneHot.scala:58:35] wire out_backSel_189 = _out_backSel_T_1[189]; // @[OneHot.scala:58:35] wire out_backSel_190 = _out_backSel_T_1[190]; // @[OneHot.scala:58:35] wire out_backSel_191 = _out_backSel_T_1[191]; // @[OneHot.scala:58:35] wire out_backSel_192 = _out_backSel_T_1[192]; // @[OneHot.scala:58:35] wire out_backSel_193 = _out_backSel_T_1[193]; // @[OneHot.scala:58:35] wire out_backSel_194 = _out_backSel_T_1[194]; // @[OneHot.scala:58:35] wire out_backSel_195 = _out_backSel_T_1[195]; // @[OneHot.scala:58:35] wire out_backSel_196 = _out_backSel_T_1[196]; // @[OneHot.scala:58:35] wire out_backSel_197 = _out_backSel_T_1[197]; // @[OneHot.scala:58:35] wire out_backSel_198 = _out_backSel_T_1[198]; // @[OneHot.scala:58:35] wire out_backSel_199 = _out_backSel_T_1[199]; // @[OneHot.scala:58:35] wire out_backSel_200 = _out_backSel_T_1[200]; // @[OneHot.scala:58:35] wire out_backSel_201 = _out_backSel_T_1[201]; // @[OneHot.scala:58:35] wire out_backSel_202 = _out_backSel_T_1[202]; // @[OneHot.scala:58:35] wire out_backSel_203 = _out_backSel_T_1[203]; // @[OneHot.scala:58:35] wire out_backSel_204 = _out_backSel_T_1[204]; // @[OneHot.scala:58:35] wire out_backSel_205 = _out_backSel_T_1[205]; // @[OneHot.scala:58:35] wire out_backSel_206 = _out_backSel_T_1[206]; // @[OneHot.scala:58:35] wire out_backSel_207 = _out_backSel_T_1[207]; // @[OneHot.scala:58:35] wire out_backSel_208 = _out_backSel_T_1[208]; // @[OneHot.scala:58:35] wire out_backSel_209 = _out_backSel_T_1[209]; // @[OneHot.scala:58:35] wire out_backSel_210 = _out_backSel_T_1[210]; // @[OneHot.scala:58:35] wire out_backSel_211 = _out_backSel_T_1[211]; // @[OneHot.scala:58:35] wire out_backSel_212 = _out_backSel_T_1[212]; // @[OneHot.scala:58:35] wire out_backSel_213 = _out_backSel_T_1[213]; // @[OneHot.scala:58:35] wire out_backSel_214 = _out_backSel_T_1[214]; // @[OneHot.scala:58:35] wire out_backSel_215 = _out_backSel_T_1[215]; // @[OneHot.scala:58:35] wire out_backSel_216 = _out_backSel_T_1[216]; // @[OneHot.scala:58:35] wire out_backSel_217 = _out_backSel_T_1[217]; // @[OneHot.scala:58:35] wire out_backSel_218 = _out_backSel_T_1[218]; // @[OneHot.scala:58:35] wire out_backSel_219 = _out_backSel_T_1[219]; // @[OneHot.scala:58:35] wire out_backSel_220 = _out_backSel_T_1[220]; // @[OneHot.scala:58:35] wire out_backSel_221 = _out_backSel_T_1[221]; // @[OneHot.scala:58:35] wire out_backSel_222 = _out_backSel_T_1[222]; // @[OneHot.scala:58:35] wire out_backSel_223 = _out_backSel_T_1[223]; // @[OneHot.scala:58:35] wire out_backSel_224 = _out_backSel_T_1[224]; // @[OneHot.scala:58:35] wire out_backSel_225 = _out_backSel_T_1[225]; // @[OneHot.scala:58:35] wire out_backSel_226 = _out_backSel_T_1[226]; // @[OneHot.scala:58:35] wire out_backSel_227 = _out_backSel_T_1[227]; // @[OneHot.scala:58:35] wire out_backSel_228 = _out_backSel_T_1[228]; // @[OneHot.scala:58:35] wire out_backSel_229 = _out_backSel_T_1[229]; // @[OneHot.scala:58:35] wire out_backSel_230 = _out_backSel_T_1[230]; // @[OneHot.scala:58:35] wire out_backSel_231 = _out_backSel_T_1[231]; // @[OneHot.scala:58:35] wire out_backSel_232 = _out_backSel_T_1[232]; // @[OneHot.scala:58:35] wire out_backSel_233 = _out_backSel_T_1[233]; // @[OneHot.scala:58:35] wire out_backSel_234 = _out_backSel_T_1[234]; // @[OneHot.scala:58:35] wire out_backSel_235 = _out_backSel_T_1[235]; // @[OneHot.scala:58:35] wire out_backSel_236 = _out_backSel_T_1[236]; // @[OneHot.scala:58:35] wire out_backSel_237 = _out_backSel_T_1[237]; // @[OneHot.scala:58:35] wire out_backSel_238 = _out_backSel_T_1[238]; // @[OneHot.scala:58:35] wire out_backSel_239 = _out_backSel_T_1[239]; // @[OneHot.scala:58:35] wire out_backSel_240 = _out_backSel_T_1[240]; // @[OneHot.scala:58:35] wire out_backSel_241 = _out_backSel_T_1[241]; // @[OneHot.scala:58:35] wire out_backSel_242 = _out_backSel_T_1[242]; // @[OneHot.scala:58:35] wire out_backSel_243 = _out_backSel_T_1[243]; // @[OneHot.scala:58:35] wire out_backSel_244 = _out_backSel_T_1[244]; // @[OneHot.scala:58:35] wire out_backSel_245 = _out_backSel_T_1[245]; // @[OneHot.scala:58:35] wire out_backSel_246 = _out_backSel_T_1[246]; // @[OneHot.scala:58:35] wire out_backSel_247 = _out_backSel_T_1[247]; // @[OneHot.scala:58:35] wire out_backSel_248 = _out_backSel_T_1[248]; // @[OneHot.scala:58:35] wire out_backSel_249 = _out_backSel_T_1[249]; // @[OneHot.scala:58:35] wire out_backSel_250 = _out_backSel_T_1[250]; // @[OneHot.scala:58:35] wire out_backSel_251 = _out_backSel_T_1[251]; // @[OneHot.scala:58:35] wire out_backSel_252 = _out_backSel_T_1[252]; // @[OneHot.scala:58:35] wire out_backSel_253 = _out_backSel_T_1[253]; // @[OneHot.scala:58:35] wire out_backSel_254 = _out_backSel_T_1[254]; // @[OneHot.scala:58:35] wire out_backSel_255 = _out_backSel_T_1[255]; // @[OneHot.scala:58:35] wire _GEN_22 = in_1_valid & out_front_1_ready; // @[RegisterRouter.scala:73:18, :87:24] wire _out_rifireMux_T_259; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_259 = _GEN_22; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_260; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_260 = _GEN_22; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_260 = _out_rifireMux_T_259 & out_front_1_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_261 = _out_rifireMux_T_260 & out_frontSel_0_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_262 = _out_rifireMux_T_261 & _out_T_1716; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_451 = _out_rifireMux_T_262; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_452 = _out_rifireMux_T_262; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_453 = _out_rifireMux_T_262; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_454 = _out_rifireMux_T_262; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_455 = _out_rifireMux_T_262; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_456 = _out_rifireMux_T_262; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_457 = _out_rifireMux_T_262; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_458 = _out_rifireMux_T_262; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_263 = ~_out_T_1716; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_265 = _out_rifireMux_T_260 & out_frontSel_1_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_266 = _out_rifireMux_T_265 & _out_T_1624; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_96 = _out_rifireMux_T_266; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_97 = _out_rifireMux_T_266; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_98 = _out_rifireMux_T_266; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_99 = _out_rifireMux_T_266; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_100 = _out_rifireMux_T_266; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_101 = _out_rifireMux_T_266; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_102 = _out_rifireMux_T_266; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_103 = _out_rifireMux_T_266; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_267 = ~_out_T_1624; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_269 = _out_rifireMux_T_260 & out_frontSel_2_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_270 = _out_rifireMux_T_269 & _out_T_1846; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_955 = _out_rifireMux_T_270; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_956 = _out_rifireMux_T_270; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_957 = _out_rifireMux_T_270; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_958 = _out_rifireMux_T_270; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_959 = _out_rifireMux_T_270; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_960 = _out_rifireMux_T_270; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_961 = _out_rifireMux_T_270; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_962 = _out_rifireMux_T_270; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_271 = ~_out_T_1846; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_273 = _out_rifireMux_T_260 & out_frontSel_3_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_274 = _out_rifireMux_T_273 & _out_T_1756; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_601 = _out_rifireMux_T_274; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_602 = _out_rifireMux_T_274; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_603 = _out_rifireMux_T_274; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_604 = _out_rifireMux_T_274; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_605 = _out_rifireMux_T_274; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_606 = _out_rifireMux_T_274; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_607 = _out_rifireMux_T_274; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_608 = _out_rifireMux_T_274; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_275 = ~_out_T_1756; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_277 = _out_rifireMux_T_260 & out_frontSel_4_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_278 = _out_rifireMux_T_277 & _out_T_1678; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_312 = _out_rifireMux_T_278; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_313 = _out_rifireMux_T_278; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_314 = _out_rifireMux_T_278; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_315 = _out_rifireMux_T_278; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_316 = _out_rifireMux_T_278; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_317 = _out_rifireMux_T_278; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_318 = _out_rifireMux_T_278; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_319 = _out_rifireMux_T_278; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_279 = ~_out_T_1678; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_281 = _out_rifireMux_T_260 & out_frontSel_5_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_282 = _out_rifireMux_T_281 & _out_T_1640; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_160 = _out_rifireMux_T_282; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_161 = _out_rifireMux_T_282; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_162 = _out_rifireMux_T_282; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_163 = _out_rifireMux_T_282; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_164 = _out_rifireMux_T_282; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_165 = _out_rifireMux_T_282; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_166 = _out_rifireMux_T_282; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_167 = _out_rifireMux_T_282; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_283 = ~_out_T_1640; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_285 = _out_rifireMux_T_260 & out_frontSel_6_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_286 = _out_rifireMux_T_285 & _out_T_1876; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1075 = _out_rifireMux_T_286; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1076 = _out_rifireMux_T_286; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1077 = _out_rifireMux_T_286; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1078 = _out_rifireMux_T_286; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1079 = _out_rifireMux_T_286; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1080 = _out_rifireMux_T_286; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1081 = _out_rifireMux_T_286; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1082 = _out_rifireMux_T_286; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_287 = ~_out_T_1876; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_289 = _out_rifireMux_T_260 & out_frontSel_7_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_290 = _out_rifireMux_T_289 & _out_T_1822; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_859 = _out_rifireMux_T_290; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_860 = _out_rifireMux_T_290; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_861 = _out_rifireMux_T_290; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_862 = _out_rifireMux_T_290; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_863 = _out_rifireMux_T_290; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_864 = _out_rifireMux_T_290; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_865 = _out_rifireMux_T_290; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_866 = _out_rifireMux_T_290; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_291 = ~_out_T_1822; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_293 = _out_rifireMux_T_260 & out_frontSel_8_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_294 = _out_rifireMux_T_293 & _out_T_1742; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_545 = _out_rifireMux_T_294; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_546 = _out_rifireMux_T_294; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_547 = _out_rifireMux_T_294; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_548 = _out_rifireMux_T_294; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_549 = _out_rifireMux_T_294; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_550 = _out_rifireMux_T_294; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_551 = _out_rifireMux_T_294; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_552 = _out_rifireMux_T_294; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_295 = ~_out_T_1742; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_297 = _out_rifireMux_T_260 & out_frontSel_9_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_298 = _out_rifireMux_T_297 & _out_T_1666; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_264 = _out_rifireMux_T_298; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_265 = _out_rifireMux_T_298; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_266 = _out_rifireMux_T_298; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_267 = _out_rifireMux_T_298; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_268 = _out_rifireMux_T_298; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_269 = _out_rifireMux_T_298; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_270 = _out_rifireMux_T_298; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_271 = _out_rifireMux_T_298; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_299 = ~_out_T_1666; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_301 = _out_rifireMux_T_260 & out_frontSel_10_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_302 = _out_rifireMux_T_301 & _out_T_1724; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_483 = _out_rifireMux_T_302; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_484 = _out_rifireMux_T_302; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_485 = _out_rifireMux_T_302; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_486 = _out_rifireMux_T_302; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_303 = ~_out_T_1724; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_305 = _out_rifireMux_T_260 & out_frontSel_11_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_306 = _out_rifireMux_T_305; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_309 = _out_rifireMux_T_260 & out_frontSel_12_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_310 = _out_rifireMux_T_309; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_313 = _out_rifireMux_T_260 & out_frontSel_13_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_314 = _out_rifireMux_T_313; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_317 = _out_rifireMux_T_260 & out_frontSel_14_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_318 = _out_rifireMux_T_317; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_321 = _out_rifireMux_T_260 & out_frontSel_15_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_322 = _out_rifireMux_T_321; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_325 = _out_rifireMux_T_260 & out_frontSel_16_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_326 = _out_rifireMux_T_325; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_329 = _out_rifireMux_T_260 & out_frontSel_17_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_330 = _out_rifireMux_T_329; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_333 = _out_rifireMux_T_260 & out_frontSel_18_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_334 = _out_rifireMux_T_333; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_337 = _out_rifireMux_T_260 & out_frontSel_19_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_338 = _out_rifireMux_T_337; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_341 = _out_rifireMux_T_260 & out_frontSel_20_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_342 = _out_rifireMux_T_341; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_345 = _out_rifireMux_T_260 & out_frontSel_21_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_346 = _out_rifireMux_T_345; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_349 = _out_rifireMux_T_260 & out_frontSel_22_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_350 = _out_rifireMux_T_349; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_353 = _out_rifireMux_T_260 & out_frontSel_23_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_354 = _out_rifireMux_T_353; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_357 = _out_rifireMux_T_260 & out_frontSel_24_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_358 = _out_rifireMux_T_357; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_361 = _out_rifireMux_T_260 & out_frontSel_25_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_362 = _out_rifireMux_T_361; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_365 = _out_rifireMux_T_260 & out_frontSel_26_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_366 = _out_rifireMux_T_365; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_369 = _out_rifireMux_T_260 & out_frontSel_27_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_370 = _out_rifireMux_T_369; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_373 = _out_rifireMux_T_260 & out_frontSel_28_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_374 = _out_rifireMux_T_373; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_377 = _out_rifireMux_T_260 & out_frontSel_29_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_378 = _out_rifireMux_T_377; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_381 = _out_rifireMux_T_260 & out_frontSel_30_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_382 = _out_rifireMux_T_381; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_385 = _out_rifireMux_T_260 & out_frontSel_31_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_386 = _out_rifireMux_T_385; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_389 = _out_rifireMux_T_260 & out_frontSel_32_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_390 = _out_rifireMux_T_389 & _out_T_1738; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_535 = _out_rifireMux_T_390; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_536 = _out_rifireMux_T_390; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_391 = ~_out_T_1738; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_393 = _out_rifireMux_T_260 & out_frontSel_33_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_394 = _out_rifireMux_T_393 & _out_T_1688; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_352 = _out_rifireMux_T_394; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_353 = _out_rifireMux_T_394; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_395 = ~_out_T_1688; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_397 = _out_rifireMux_T_260 & out_frontSel_34_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_398 = _out_rifireMux_T_397; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_401 = _out_rifireMux_T_260 & out_frontSel_35_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_402 = _out_rifireMux_T_401; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_405 = _out_rifireMux_T_260 & out_frontSel_36_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_406 = _out_rifireMux_T_405; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_409 = _out_rifireMux_T_260 & out_frontSel_37_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_410 = _out_rifireMux_T_409; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_413 = _out_rifireMux_T_260 & out_frontSel_38_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_414 = _out_rifireMux_T_413; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_417 = _out_rifireMux_T_260 & out_frontSel_39_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_418 = _out_rifireMux_T_417; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_421 = _out_rifireMux_T_260 & out_frontSel_40_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_422 = _out_rifireMux_T_421; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_425 = _out_rifireMux_T_260 & out_frontSel_41_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_426 = _out_rifireMux_T_425; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_429 = _out_rifireMux_T_260 & out_frontSel_42_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_430 = _out_rifireMux_T_429; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_433 = _out_rifireMux_T_260 & out_frontSel_43_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_434 = _out_rifireMux_T_433; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_437 = _out_rifireMux_T_260 & out_frontSel_44_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_438 = _out_rifireMux_T_437; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_441 = _out_rifireMux_T_260 & out_frontSel_45_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_442 = _out_rifireMux_T_441; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_445 = _out_rifireMux_T_260 & out_frontSel_46_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_446 = _out_rifireMux_T_445; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_449 = _out_rifireMux_T_260 & out_frontSel_47_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_450 = _out_rifireMux_T_449; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_453 = _out_rifireMux_T_260 & out_frontSel_48_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_454 = _out_rifireMux_T_453; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_457 = _out_rifireMux_T_260 & out_frontSel_49_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_458 = _out_rifireMux_T_457; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_461 = _out_rifireMux_T_260 & out_frontSel_50_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_462 = _out_rifireMux_T_461; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_465 = _out_rifireMux_T_260 & out_frontSel_51_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_466 = _out_rifireMux_T_465; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_469 = _out_rifireMux_T_260 & out_frontSel_52_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_470 = _out_rifireMux_T_469; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_473 = _out_rifireMux_T_260 & out_frontSel_53_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_474 = _out_rifireMux_T_473; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_477 = _out_rifireMux_T_260 & out_frontSel_54_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_478 = _out_rifireMux_T_477; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_481 = _out_rifireMux_T_260 & out_frontSel_55_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_482 = _out_rifireMux_T_481; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_485 = _out_rifireMux_T_260 & out_frontSel_56_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_486 = _out_rifireMux_T_485; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_489 = _out_rifireMux_T_260 & out_frontSel_57_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_490 = _out_rifireMux_T_489; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_493 = _out_rifireMux_T_260 & out_frontSel_58_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_494 = _out_rifireMux_T_493; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_497 = _out_rifireMux_T_260 & out_frontSel_59_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_498 = _out_rifireMux_T_497; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_501 = _out_rifireMux_T_260 & out_frontSel_60_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_502 = _out_rifireMux_T_501; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_505 = _out_rifireMux_T_260 & out_frontSel_61_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_506 = _out_rifireMux_T_505; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_509 = _out_rifireMux_T_260 & out_frontSel_62_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_510 = _out_rifireMux_T_509; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_513 = _out_rifireMux_T_260 & out_frontSel_63_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_514 = _out_rifireMux_T_513; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_517 = _out_rifireMux_T_260 & out_frontSel_64; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_518 = _out_rifireMux_T_517; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_521 = _out_rifireMux_T_260 & out_frontSel_65; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_522 = _out_rifireMux_T_521; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_525 = _out_rifireMux_T_260 & out_frontSel_66; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_526 = _out_rifireMux_T_525; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_529 = _out_rifireMux_T_260 & out_frontSel_67; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_530 = _out_rifireMux_T_529; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_533 = _out_rifireMux_T_260 & out_frontSel_68; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_534 = _out_rifireMux_T_533; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_537 = _out_rifireMux_T_260 & out_frontSel_69; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_538 = _out_rifireMux_T_537; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_541 = _out_rifireMux_T_260 & out_frontSel_70; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_542 = _out_rifireMux_T_541; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_545 = _out_rifireMux_T_260 & out_frontSel_71; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_546 = _out_rifireMux_T_545; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_549 = _out_rifireMux_T_260 & out_frontSel_72; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_550 = _out_rifireMux_T_549; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_553 = _out_rifireMux_T_260 & out_frontSel_73; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_554 = _out_rifireMux_T_553; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_557 = _out_rifireMux_T_260 & out_frontSel_74; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_558 = _out_rifireMux_T_557; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_561 = _out_rifireMux_T_260 & out_frontSel_75; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_562 = _out_rifireMux_T_561; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_565 = _out_rifireMux_T_260 & out_frontSel_76; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_566 = _out_rifireMux_T_565; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_569 = _out_rifireMux_T_260 & out_frontSel_77; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_570 = _out_rifireMux_T_569; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_573 = _out_rifireMux_T_260 & out_frontSel_78; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_574 = _out_rifireMux_T_573; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_577 = _out_rifireMux_T_260 & out_frontSel_79; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_578 = _out_rifireMux_T_577; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_581 = _out_rifireMux_T_260 & out_frontSel_80; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_582 = _out_rifireMux_T_581; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_585 = _out_rifireMux_T_260 & out_frontSel_81; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_586 = _out_rifireMux_T_585; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_589 = _out_rifireMux_T_260 & out_frontSel_82; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_590 = _out_rifireMux_T_589; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_593 = _out_rifireMux_T_260 & out_frontSel_83; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_594 = _out_rifireMux_T_593; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_597 = _out_rifireMux_T_260 & out_frontSel_84; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_598 = _out_rifireMux_T_597; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_601 = _out_rifireMux_T_260 & out_frontSel_85; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_602 = _out_rifireMux_T_601; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_605 = _out_rifireMux_T_260 & out_frontSel_86; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_606 = _out_rifireMux_T_605; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_609 = _out_rifireMux_T_260 & out_frontSel_87; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_610 = _out_rifireMux_T_609; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_613 = _out_rifireMux_T_260 & out_frontSel_88; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_614 = _out_rifireMux_T_613; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_617 = _out_rifireMux_T_260 & out_frontSel_89; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_618 = _out_rifireMux_T_617; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_621 = _out_rifireMux_T_260 & out_frontSel_90; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_622 = _out_rifireMux_T_621; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_625 = _out_rifireMux_T_260 & out_frontSel_91; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_626 = _out_rifireMux_T_625; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_629 = _out_rifireMux_T_260 & out_frontSel_92; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_630 = _out_rifireMux_T_629; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_633 = _out_rifireMux_T_260 & out_frontSel_93; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_634 = _out_rifireMux_T_633; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_637 = _out_rifireMux_T_260 & out_frontSel_94; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_638 = _out_rifireMux_T_637; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_641 = _out_rifireMux_T_260 & out_frontSel_95; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_642 = _out_rifireMux_T_641; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_645 = _out_rifireMux_T_260 & out_frontSel_96; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_646 = _out_rifireMux_T_645 & _out_T_1712; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_442 = _out_rifireMux_T_646; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_647 = ~_out_T_1712; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_649 = _out_rifireMux_T_260 & out_frontSel_97; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_650 = _out_rifireMux_T_649; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_653 = _out_rifireMux_T_260 & out_frontSel_98; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_654 = _out_rifireMux_T_653; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_657 = _out_rifireMux_T_260 & out_frontSel_99; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_658 = _out_rifireMux_T_657; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_661 = _out_rifireMux_T_260 & out_frontSel_100; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_662 = _out_rifireMux_T_661; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_665 = _out_rifireMux_T_260 & out_frontSel_101; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_666 = _out_rifireMux_T_665; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_669 = _out_rifireMux_T_260 & out_frontSel_102; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_670 = _out_rifireMux_T_669; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_673 = _out_rifireMux_T_260 & out_frontSel_103; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_674 = _out_rifireMux_T_673 & _out_T_1780; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_697 = _out_rifireMux_T_674; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_698 = _out_rifireMux_T_674; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_675 = ~_out_T_1780; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_677 = _out_rifireMux_T_260 & out_frontSel_104; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_678 = _out_rifireMux_T_677 & _out_T_1840; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_931 = _out_rifireMux_T_678; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_932 = _out_rifireMux_T_678; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_933 = _out_rifireMux_T_678; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_934 = _out_rifireMux_T_678; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_935 = _out_rifireMux_T_678; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_936 = _out_rifireMux_T_678; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_937 = _out_rifireMux_T_678; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_938 = _out_rifireMux_T_678; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_679 = ~_out_T_1840; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_681 = _out_rifireMux_T_260 & out_frontSel_105; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_682 = _out_rifireMux_T_681 & _out_T_1732; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_511 = _out_rifireMux_T_682; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_512 = _out_rifireMux_T_682; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_513 = _out_rifireMux_T_682; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_514 = _out_rifireMux_T_682; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_515 = _out_rifireMux_T_682; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_516 = _out_rifireMux_T_682; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_517 = _out_rifireMux_T_682; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_518 = _out_rifireMux_T_682; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_683 = ~_out_T_1732; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_685 = _out_rifireMux_T_260 & out_frontSel_106; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_686 = _out_rifireMux_T_685 & _out_T_1648; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_192 = _out_rifireMux_T_686; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_193 = _out_rifireMux_T_686; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_194 = _out_rifireMux_T_686; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_195 = _out_rifireMux_T_686; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_196 = _out_rifireMux_T_686; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_197 = _out_rifireMux_T_686; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_198 = _out_rifireMux_T_686; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_199 = _out_rifireMux_T_686; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_687 = ~_out_T_1648; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_689 = _out_rifireMux_T_260 & out_frontSel_107; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_690 = _out_rifireMux_T_689 & _out_T_1880; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1091 = _out_rifireMux_T_690; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1092 = _out_rifireMux_T_690; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1093 = _out_rifireMux_T_690; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1094 = _out_rifireMux_T_690; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1095 = _out_rifireMux_T_690; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1096 = _out_rifireMux_T_690; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1097 = _out_rifireMux_T_690; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1098 = _out_rifireMux_T_690; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_691 = ~_out_T_1880; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_693 = _out_rifireMux_T_260 & out_frontSel_108; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_694 = _out_rifireMux_T_693 & _out_T_1790; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_731 = _out_rifireMux_T_694; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_732 = _out_rifireMux_T_694; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_733 = _out_rifireMux_T_694; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_734 = _out_rifireMux_T_694; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_735 = _out_rifireMux_T_694; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_736 = _out_rifireMux_T_694; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_737 = _out_rifireMux_T_694; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_738 = _out_rifireMux_T_694; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_695 = ~_out_T_1790; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_697 = _out_rifireMux_T_260 & out_frontSel_109; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_698 = _out_rifireMux_T_697 & _out_T_1714; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_443 = _out_rifireMux_T_698; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_444 = _out_rifireMux_T_698; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_445 = _out_rifireMux_T_698; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_446 = _out_rifireMux_T_698; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_447 = _out_rifireMux_T_698; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_448 = _out_rifireMux_T_698; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_449 = _out_rifireMux_T_698; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_450 = _out_rifireMux_T_698; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_699 = ~_out_T_1714; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_701 = _out_rifireMux_T_260 & out_frontSel_110; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_702 = _out_rifireMux_T_701 & _out_T_1628; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_112 = _out_rifireMux_T_702; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_113 = _out_rifireMux_T_702; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_114 = _out_rifireMux_T_702; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_115 = _out_rifireMux_T_702; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_116 = _out_rifireMux_T_702; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_117 = _out_rifireMux_T_702; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_118 = _out_rifireMux_T_702; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_119 = _out_rifireMux_T_702; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_703 = ~_out_T_1628; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_705 = _out_rifireMux_T_260 & out_frontSel_111; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_706 = _out_rifireMux_T_705 & _out_T_1898; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1163 = _out_rifireMux_T_706; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1164 = _out_rifireMux_T_706; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1165 = _out_rifireMux_T_706; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1166 = _out_rifireMux_T_706; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1167 = _out_rifireMux_T_706; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1168 = _out_rifireMux_T_706; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1169 = _out_rifireMux_T_706; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1170 = _out_rifireMux_T_706; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_707 = ~_out_T_1898; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_709 = _out_rifireMux_T_260 & out_frontSel_112; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_710 = _out_rifireMux_T_709 & _out_T_1814; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_827 = _out_rifireMux_T_710; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_828 = _out_rifireMux_T_710; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_829 = _out_rifireMux_T_710; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_830 = _out_rifireMux_T_710; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_831 = _out_rifireMux_T_710; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_832 = _out_rifireMux_T_710; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_833 = _out_rifireMux_T_710; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_834 = _out_rifireMux_T_710; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_711 = ~_out_T_1814; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_713 = _out_rifireMux_T_260 & out_frontSel_113; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_714 = _out_rifireMux_T_713 & _out_T_1770; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_657 = _out_rifireMux_T_714; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_658 = _out_rifireMux_T_714; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_659 = _out_rifireMux_T_714; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_660 = _out_rifireMux_T_714; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_661 = _out_rifireMux_T_714; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_662 = _out_rifireMux_T_714; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_663 = _out_rifireMux_T_714; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_664 = _out_rifireMux_T_714; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_715 = ~_out_T_1770; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_717 = _out_rifireMux_T_260 & out_frontSel_114; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_718 = _out_rifireMux_T_717 & _out_T_1852; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_979 = _out_rifireMux_T_718; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_980 = _out_rifireMux_T_718; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_981 = _out_rifireMux_T_718; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_982 = _out_rifireMux_T_718; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_983 = _out_rifireMux_T_718; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_984 = _out_rifireMux_T_718; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_985 = _out_rifireMux_T_718; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_986 = _out_rifireMux_T_718; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_719 = ~_out_T_1852; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_721 = _out_rifireMux_T_260 & out_frontSel_115; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_722 = _out_rifireMux_T_721 & _out_T_1608; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_32 = _out_rifireMux_T_722; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_33 = _out_rifireMux_T_722; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_34 = _out_rifireMux_T_722; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_35 = _out_rifireMux_T_722; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_36 = _out_rifireMux_T_722; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_37 = _out_rifireMux_T_722; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_38 = _out_rifireMux_T_722; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_39 = _out_rifireMux_T_722; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_723 = ~_out_T_1608; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_725 = _out_rifireMux_T_260 & out_frontSel_116; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_726 = _out_rifireMux_T_725; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_729 = _out_rifireMux_T_260 & out_frontSel_117; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_730 = _out_rifireMux_T_729; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_733 = _out_rifireMux_T_260 & out_frontSel_118; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_734 = _out_rifireMux_T_733; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_737 = _out_rifireMux_T_260 & out_frontSel_119; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_738 = _out_rifireMux_T_737; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_741 = _out_rifireMux_T_260 & out_frontSel_120; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_742 = _out_rifireMux_T_741; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_745 = _out_rifireMux_T_260 & out_frontSel_121; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_746 = _out_rifireMux_T_745; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_749 = _out_rifireMux_T_260 & out_frontSel_122; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_750 = _out_rifireMux_T_749; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_753 = _out_rifireMux_T_260 & out_frontSel_123; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_754 = _out_rifireMux_T_753; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_757 = _out_rifireMux_T_260 & out_frontSel_124; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_758 = _out_rifireMux_T_757; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_761 = _out_rifireMux_T_260 & out_frontSel_125; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_762 = _out_rifireMux_T_761; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_765 = _out_rifireMux_T_260 & out_frontSel_126; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_766 = _out_rifireMux_T_765; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_769 = _out_rifireMux_T_260 & out_frontSel_127; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_770 = _out_rifireMux_T_769; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_773 = _out_rifireMux_T_260 & out_frontSel_128; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_774 = _out_rifireMux_T_773 & _out_T_1728; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_495 = _out_rifireMux_T_774; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_496 = _out_rifireMux_T_774; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_497 = _out_rifireMux_T_774; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_498 = _out_rifireMux_T_774; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_499 = _out_rifireMux_T_774; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_500 = _out_rifireMux_T_774; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_501 = _out_rifireMux_T_774; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_502 = _out_rifireMux_T_774; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_775 = ~_out_T_1728; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_777 = _out_rifireMux_T_260 & out_frontSel_129; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_778 = _out_rifireMux_T_777 & _out_T_1720; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_467 = _out_rifireMux_T_778; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_468 = _out_rifireMux_T_778; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_469 = _out_rifireMux_T_778; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_470 = _out_rifireMux_T_778; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_471 = _out_rifireMux_T_778; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_472 = _out_rifireMux_T_778; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_473 = _out_rifireMux_T_778; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_474 = _out_rifireMux_T_778; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_779 = ~_out_T_1720; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_781 = _out_rifireMux_T_260 & out_frontSel_130; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_782 = _out_rifireMux_T_781 & _out_T_1796; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_755 = _out_rifireMux_T_782; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_756 = _out_rifireMux_T_782; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_757 = _out_rifireMux_T_782; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_758 = _out_rifireMux_T_782; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_759 = _out_rifireMux_T_782; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_760 = _out_rifireMux_T_782; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_761 = _out_rifireMux_T_782; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_762 = _out_rifireMux_T_782; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_783 = ~_out_T_1796; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_785 = _out_rifireMux_T_260 & out_frontSel_131; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_786 = _out_rifireMux_T_785 & _out_T_1890; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1131 = _out_rifireMux_T_786; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1132 = _out_rifireMux_T_786; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1133 = _out_rifireMux_T_786; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1134 = _out_rifireMux_T_786; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1135 = _out_rifireMux_T_786; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1136 = _out_rifireMux_T_786; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1137 = _out_rifireMux_T_786; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1138 = _out_rifireMux_T_786; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_787 = ~_out_T_1890; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_789 = _out_rifireMux_T_260 & out_frontSel_132; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_790 = _out_rifireMux_T_789 & _out_T_1660; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_240 = _out_rifireMux_T_790; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_241 = _out_rifireMux_T_790; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_242 = _out_rifireMux_T_790; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_243 = _out_rifireMux_T_790; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_244 = _out_rifireMux_T_790; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_245 = _out_rifireMux_T_790; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_246 = _out_rifireMux_T_790; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_247 = _out_rifireMux_T_790; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_791 = ~_out_T_1660; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_793 = _out_rifireMux_T_260 & out_frontSel_133; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_794 = _out_rifireMux_T_793 & _out_T_1662; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_248 = _out_rifireMux_T_794; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_249 = _out_rifireMux_T_794; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_250 = _out_rifireMux_T_794; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_251 = _out_rifireMux_T_794; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_252 = _out_rifireMux_T_794; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_253 = _out_rifireMux_T_794; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_254 = _out_rifireMux_T_794; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_255 = _out_rifireMux_T_794; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_795 = ~_out_T_1662; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_797 = _out_rifireMux_T_260 & out_frontSel_134; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_798 = _out_rifireMux_T_797 & _out_T_1722; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_475 = _out_rifireMux_T_798; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_476 = _out_rifireMux_T_798; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_477 = _out_rifireMux_T_798; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_478 = _out_rifireMux_T_798; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_479 = _out_rifireMux_T_798; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_480 = _out_rifireMux_T_798; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_481 = _out_rifireMux_T_798; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_482 = _out_rifireMux_T_798; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_799 = ~_out_T_1722; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_801 = _out_rifireMux_T_260 & out_frontSel_135; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_802 = _out_rifireMux_T_801 & _out_T_1800; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_771 = _out_rifireMux_T_802; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_772 = _out_rifireMux_T_802; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_773 = _out_rifireMux_T_802; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_774 = _out_rifireMux_T_802; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_775 = _out_rifireMux_T_802; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_776 = _out_rifireMux_T_802; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_777 = _out_rifireMux_T_802; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_778 = _out_rifireMux_T_802; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_803 = ~_out_T_1800; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_805 = _out_rifireMux_T_260 & out_frontSel_136; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_806 = _out_rifireMux_T_805 & _out_T_1882; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1099 = _out_rifireMux_T_806; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1100 = _out_rifireMux_T_806; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1101 = _out_rifireMux_T_806; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1102 = _out_rifireMux_T_806; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1103 = _out_rifireMux_T_806; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1104 = _out_rifireMux_T_806; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1105 = _out_rifireMux_T_806; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1106 = _out_rifireMux_T_806; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_807 = ~_out_T_1882; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_809 = _out_rifireMux_T_260 & out_frontSel_137; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_810 = _out_rifireMux_T_809 & _out_T_1684; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_336 = _out_rifireMux_T_810; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_337 = _out_rifireMux_T_810; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_338 = _out_rifireMux_T_810; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_339 = _out_rifireMux_T_810; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_340 = _out_rifireMux_T_810; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_341 = _out_rifireMux_T_810; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_342 = _out_rifireMux_T_810; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_343 = _out_rifireMux_T_810; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_811 = ~_out_T_1684; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_813 = _out_rifireMux_T_260 & out_frontSel_138; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_814 = _out_rifireMux_T_813 & _out_T_1600; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_0 = _out_rifireMux_T_814; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1 = _out_rifireMux_T_814; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_2 = _out_rifireMux_T_814; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_3 = _out_rifireMux_T_814; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_4 = _out_rifireMux_T_814; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_5 = _out_rifireMux_T_814; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_6 = _out_rifireMux_T_814; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_7 = _out_rifireMux_T_814; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_815 = ~_out_T_1600; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_817 = _out_rifireMux_T_260 & out_frontSel_139; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_818 = _out_rifireMux_T_817 & _out_T_1856; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_995 = _out_rifireMux_T_818; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_996 = _out_rifireMux_T_818; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_997 = _out_rifireMux_T_818; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_998 = _out_rifireMux_T_818; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_999 = _out_rifireMux_T_818; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1000 = _out_rifireMux_T_818; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1001 = _out_rifireMux_T_818; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1002 = _out_rifireMux_T_818; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_819 = ~_out_T_1856; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_821 = _out_rifireMux_T_260 & out_frontSel_140; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_822 = _out_rifireMux_T_821 & _out_T_1782; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_699 = _out_rifireMux_T_822; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_700 = _out_rifireMux_T_822; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_701 = _out_rifireMux_T_822; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_702 = _out_rifireMux_T_822; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_703 = _out_rifireMux_T_822; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_704 = _out_rifireMux_T_822; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_705 = _out_rifireMux_T_822; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_706 = _out_rifireMux_T_822; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_823 = ~_out_T_1782; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_825 = _out_rifireMux_T_260 & out_frontSel_141; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_826 = _out_rifireMux_T_825 & _out_T_1704; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_410 = _out_rifireMux_T_826; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_411 = _out_rifireMux_T_826; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_412 = _out_rifireMux_T_826; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_413 = _out_rifireMux_T_826; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_414 = _out_rifireMux_T_826; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_415 = _out_rifireMux_T_826; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_416 = _out_rifireMux_T_826; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_417 = _out_rifireMux_T_826; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_827 = ~_out_T_1704; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_829 = _out_rifireMux_T_260 & out_frontSel_142; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_830 = _out_rifireMux_T_829 & _out_T_1616; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_64 = _out_rifireMux_T_830; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_65 = _out_rifireMux_T_830; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_66 = _out_rifireMux_T_830; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_67 = _out_rifireMux_T_830; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_68 = _out_rifireMux_T_830; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_69 = _out_rifireMux_T_830; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_70 = _out_rifireMux_T_830; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_71 = _out_rifireMux_T_830; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_831 = ~_out_T_1616; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_833 = _out_rifireMux_T_260 & out_frontSel_143; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_834 = _out_rifireMux_T_833 & _out_T_1834; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_907 = _out_rifireMux_T_834; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_908 = _out_rifireMux_T_834; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_909 = _out_rifireMux_T_834; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_910 = _out_rifireMux_T_834; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_911 = _out_rifireMux_T_834; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_912 = _out_rifireMux_T_834; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_913 = _out_rifireMux_T_834; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_914 = _out_rifireMux_T_834; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_835 = ~_out_T_1834; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_837 = _out_rifireMux_T_260 & out_frontSel_144; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_838 = _out_rifireMux_T_837 & _out_T_1758; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_609 = _out_rifireMux_T_838; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_610 = _out_rifireMux_T_838; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_611 = _out_rifireMux_T_838; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_612 = _out_rifireMux_T_838; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_613 = _out_rifireMux_T_838; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_614 = _out_rifireMux_T_838; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_615 = _out_rifireMux_T_838; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_616 = _out_rifireMux_T_838; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_839 = ~_out_T_1758; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_841 = _out_rifireMux_T_260 & out_frontSel_145; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_842 = _out_rifireMux_T_841 & _out_T_1818; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_843 = _out_rifireMux_T_842; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_844 = _out_rifireMux_T_842; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_845 = _out_rifireMux_T_842; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_846 = _out_rifireMux_T_842; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_847 = _out_rifireMux_T_842; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_848 = _out_rifireMux_T_842; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_849 = _out_rifireMux_T_842; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_850 = _out_rifireMux_T_842; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_843 = ~_out_T_1818; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_845 = _out_rifireMux_T_260 & out_frontSel_146; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_846 = _out_rifireMux_T_845 & _out_T_1868; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1043 = _out_rifireMux_T_846; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1044 = _out_rifireMux_T_846; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1045 = _out_rifireMux_T_846; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1046 = _out_rifireMux_T_846; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1047 = _out_rifireMux_T_846; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1048 = _out_rifireMux_T_846; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1049 = _out_rifireMux_T_846; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1050 = _out_rifireMux_T_846; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_847 = ~_out_T_1868; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_849 = _out_rifireMux_T_260 & out_frontSel_147; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_850 = _out_rifireMux_T_849 & _out_T_1656; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_224 = _out_rifireMux_T_850; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_225 = _out_rifireMux_T_850; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_226 = _out_rifireMux_T_850; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_227 = _out_rifireMux_T_850; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_228 = _out_rifireMux_T_850; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_229 = _out_rifireMux_T_850; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_230 = _out_rifireMux_T_850; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_231 = _out_rifireMux_T_850; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_851 = ~_out_T_1656; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_853 = _out_rifireMux_T_260 & out_frontSel_148; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_854 = _out_rifireMux_T_853 & _out_T_1740; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_537 = _out_rifireMux_T_854; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_538 = _out_rifireMux_T_854; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_539 = _out_rifireMux_T_854; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_540 = _out_rifireMux_T_854; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_541 = _out_rifireMux_T_854; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_542 = _out_rifireMux_T_854; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_543 = _out_rifireMux_T_854; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_544 = _out_rifireMux_T_854; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_855 = ~_out_T_1740; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_857 = _out_rifireMux_T_260 & out_frontSel_149; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_858 = _out_rifireMux_T_857 & _out_T_1748; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_569 = _out_rifireMux_T_858; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_570 = _out_rifireMux_T_858; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_571 = _out_rifireMux_T_858; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_572 = _out_rifireMux_T_858; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_573 = _out_rifireMux_T_858; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_574 = _out_rifireMux_T_858; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_575 = _out_rifireMux_T_858; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_576 = _out_rifireMux_T_858; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_859 = ~_out_T_1748; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_861 = _out_rifireMux_T_260 & out_frontSel_150; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_862 = _out_rifireMux_T_861 & _out_T_1820; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_851 = _out_rifireMux_T_862; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_852 = _out_rifireMux_T_862; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_853 = _out_rifireMux_T_862; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_854 = _out_rifireMux_T_862; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_855 = _out_rifireMux_T_862; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_856 = _out_rifireMux_T_862; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_857 = _out_rifireMux_T_862; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_858 = _out_rifireMux_T_862; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_863 = ~_out_T_1820; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_865 = _out_rifireMux_T_260 & out_frontSel_151; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_866 = _out_rifireMux_T_865 & _out_T_1866; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1035 = _out_rifireMux_T_866; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1036 = _out_rifireMux_T_866; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1037 = _out_rifireMux_T_866; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1038 = _out_rifireMux_T_866; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1039 = _out_rifireMux_T_866; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1040 = _out_rifireMux_T_866; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1041 = _out_rifireMux_T_866; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1042 = _out_rifireMux_T_866; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_867 = ~_out_T_1866; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_869 = _out_rifireMux_T_260 & out_frontSel_152; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_870 = _out_rifireMux_T_869 & _out_T_1636; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_144 = _out_rifireMux_T_870; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_145 = _out_rifireMux_T_870; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_146 = _out_rifireMux_T_870; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_147 = _out_rifireMux_T_870; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_148 = _out_rifireMux_T_870; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_149 = _out_rifireMux_T_870; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_150 = _out_rifireMux_T_870; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_151 = _out_rifireMux_T_870; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_871 = ~_out_T_1636; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_873 = _out_rifireMux_T_260 & out_frontSel_153; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_874 = _out_rifireMux_T_873 & _out_T_1618; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_72 = _out_rifireMux_T_874; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_73 = _out_rifireMux_T_874; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_74 = _out_rifireMux_T_874; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_75 = _out_rifireMux_T_874; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_76 = _out_rifireMux_T_874; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_77 = _out_rifireMux_T_874; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_78 = _out_rifireMux_T_874; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_79 = _out_rifireMux_T_874; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_875 = ~_out_T_1618; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_877 = _out_rifireMux_T_260 & out_frontSel_154; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_878 = _out_rifireMux_T_877 & _out_T_1830; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_891 = _out_rifireMux_T_878; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_892 = _out_rifireMux_T_878; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_893 = _out_rifireMux_T_878; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_894 = _out_rifireMux_T_878; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_895 = _out_rifireMux_T_878; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_896 = _out_rifireMux_T_878; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_897 = _out_rifireMux_T_878; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_898 = _out_rifireMux_T_878; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_879 = ~_out_T_1830; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_881 = _out_rifireMux_T_260 & out_frontSel_155; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_882 = _out_rifireMux_T_881 & _out_T_1786; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_715 = _out_rifireMux_T_882; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_716 = _out_rifireMux_T_882; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_717 = _out_rifireMux_T_882; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_718 = _out_rifireMux_T_882; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_719 = _out_rifireMux_T_882; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_720 = _out_rifireMux_T_882; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_721 = _out_rifireMux_T_882; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_722 = _out_rifireMux_T_882; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_883 = ~_out_T_1786; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_885 = _out_rifireMux_T_260 & out_frontSel_156; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_886 = _out_rifireMux_T_885 & _out_T_1698; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_386 = _out_rifireMux_T_886; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_387 = _out_rifireMux_T_886; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_388 = _out_rifireMux_T_886; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_389 = _out_rifireMux_T_886; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_390 = _out_rifireMux_T_886; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_391 = _out_rifireMux_T_886; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_392 = _out_rifireMux_T_886; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_393 = _out_rifireMux_T_886; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_887 = ~_out_T_1698; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_889 = _out_rifireMux_T_260 & out_frontSel_157; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_890 = _out_rifireMux_T_889 & _out_T_1632; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_128 = _out_rifireMux_T_890; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_129 = _out_rifireMux_T_890; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_130 = _out_rifireMux_T_890; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_131 = _out_rifireMux_T_890; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_132 = _out_rifireMux_T_890; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_133 = _out_rifireMux_T_890; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_134 = _out_rifireMux_T_890; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_135 = _out_rifireMux_T_890; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_891 = ~_out_T_1632; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_893 = _out_rifireMux_T_260 & out_frontSel_158; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_894 = _out_rifireMux_T_893 & _out_T_1848; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_963 = _out_rifireMux_T_894; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_964 = _out_rifireMux_T_894; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_965 = _out_rifireMux_T_894; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_966 = _out_rifireMux_T_894; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_967 = _out_rifireMux_T_894; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_968 = _out_rifireMux_T_894; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_969 = _out_rifireMux_T_894; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_970 = _out_rifireMux_T_894; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_895 = ~_out_T_1848; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_897 = _out_rifireMux_T_260 & out_frontSel_159; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_898 = _out_rifireMux_T_897 & _out_T_1764; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_633 = _out_rifireMux_T_898; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_634 = _out_rifireMux_T_898; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_635 = _out_rifireMux_T_898; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_636 = _out_rifireMux_T_898; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_637 = _out_rifireMux_T_898; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_638 = _out_rifireMux_T_898; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_639 = _out_rifireMux_T_898; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_640 = _out_rifireMux_T_898; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_899 = ~_out_T_1764; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_901 = _out_rifireMux_T_260 & out_frontSel_160; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_902 = _out_rifireMux_T_901 & _out_T_1680; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_320 = _out_rifireMux_T_902; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_321 = _out_rifireMux_T_902; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_322 = _out_rifireMux_T_902; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_323 = _out_rifireMux_T_902; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_324 = _out_rifireMux_T_902; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_325 = _out_rifireMux_T_902; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_326 = _out_rifireMux_T_902; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_327 = _out_rifireMux_T_902; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_903 = ~_out_T_1680; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_905 = _out_rifireMux_T_260 & out_frontSel_161; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_906 = _out_rifireMux_T_905 & _out_T_1744; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_553 = _out_rifireMux_T_906; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_554 = _out_rifireMux_T_906; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_555 = _out_rifireMux_T_906; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_556 = _out_rifireMux_T_906; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_557 = _out_rifireMux_T_906; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_558 = _out_rifireMux_T_906; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_559 = _out_rifireMux_T_906; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_560 = _out_rifireMux_T_906; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_907 = ~_out_T_1744; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_909 = _out_rifireMux_T_260 & out_frontSel_162; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_910 = _out_rifireMux_T_909 & _out_T_1808; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_803 = _out_rifireMux_T_910; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_804 = _out_rifireMux_T_910; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_805 = _out_rifireMux_T_910; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_806 = _out_rifireMux_T_910; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_807 = _out_rifireMux_T_910; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_808 = _out_rifireMux_T_910; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_809 = _out_rifireMux_T_910; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_810 = _out_rifireMux_T_910; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_911 = ~_out_T_1808; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_913 = _out_rifireMux_T_260 & out_frontSel_163; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_914 = _out_rifireMux_T_913 & _out_T_1894; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1147 = _out_rifireMux_T_914; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1148 = _out_rifireMux_T_914; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1149 = _out_rifireMux_T_914; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1150 = _out_rifireMux_T_914; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1151 = _out_rifireMux_T_914; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1152 = _out_rifireMux_T_914; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1153 = _out_rifireMux_T_914; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1154 = _out_rifireMux_T_914; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_915 = ~_out_T_1894; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_917 = _out_rifireMux_T_260 & out_frontSel_164; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_918 = _out_rifireMux_T_917 & _out_T_1644; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_176 = _out_rifireMux_T_918; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_177 = _out_rifireMux_T_918; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_178 = _out_rifireMux_T_918; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_179 = _out_rifireMux_T_918; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_180 = _out_rifireMux_T_918; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_181 = _out_rifireMux_T_918; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_182 = _out_rifireMux_T_918; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_183 = _out_rifireMux_T_918; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_919 = ~_out_T_1644; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_921 = _out_rifireMux_T_260 & out_frontSel_165; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_922 = _out_rifireMux_T_921 & _out_T_1686; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_344 = _out_rifireMux_T_922; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_345 = _out_rifireMux_T_922; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_346 = _out_rifireMux_T_922; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_347 = _out_rifireMux_T_922; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_348 = _out_rifireMux_T_922; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_349 = _out_rifireMux_T_922; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_350 = _out_rifireMux_T_922; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_351 = _out_rifireMux_T_922; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_923 = ~_out_T_1686; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_925 = _out_rifireMux_T_260 & out_frontSel_166; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_926 = _out_rifireMux_T_925 & _out_T_1736; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_527 = _out_rifireMux_T_926; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_528 = _out_rifireMux_T_926; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_529 = _out_rifireMux_T_926; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_530 = _out_rifireMux_T_926; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_531 = _out_rifireMux_T_926; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_532 = _out_rifireMux_T_926; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_533 = _out_rifireMux_T_926; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_534 = _out_rifireMux_T_926; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_927 = ~_out_T_1736; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_929 = _out_rifireMux_T_260 & out_frontSel_167; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_930 = _out_rifireMux_T_929 & _out_T_1806; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_795 = _out_rifireMux_T_930; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_796 = _out_rifireMux_T_930; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_797 = _out_rifireMux_T_930; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_798 = _out_rifireMux_T_930; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_799 = _out_rifireMux_T_930; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_800 = _out_rifireMux_T_930; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_801 = _out_rifireMux_T_930; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_802 = _out_rifireMux_T_930; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_931 = ~_out_T_1806; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_933 = _out_rifireMux_T_260 & out_frontSel_168; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_934 = _out_rifireMux_T_933 & _out_T_1874; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1067 = _out_rifireMux_T_934; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1068 = _out_rifireMux_T_934; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1069 = _out_rifireMux_T_934; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1070 = _out_rifireMux_T_934; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1071 = _out_rifireMux_T_934; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1072 = _out_rifireMux_T_934; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1073 = _out_rifireMux_T_934; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1074 = _out_rifireMux_T_934; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_935 = ~_out_T_1874; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_937 = _out_rifireMux_T_260 & out_frontSel_169; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_938 = _out_rifireMux_T_937 & _out_T_1702; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_402 = _out_rifireMux_T_938; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_403 = _out_rifireMux_T_938; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_404 = _out_rifireMux_T_938; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_405 = _out_rifireMux_T_938; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_406 = _out_rifireMux_T_938; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_407 = _out_rifireMux_T_938; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_408 = _out_rifireMux_T_938; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_409 = _out_rifireMux_T_938; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_939 = ~_out_T_1702; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_941 = _out_rifireMux_T_260 & out_frontSel_170; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_942 = _out_rifireMux_T_941 & _out_T_1606; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_24 = _out_rifireMux_T_942; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_25 = _out_rifireMux_T_942; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_26 = _out_rifireMux_T_942; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_27 = _out_rifireMux_T_942; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_28 = _out_rifireMux_T_942; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_29 = _out_rifireMux_T_942; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_30 = _out_rifireMux_T_942; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_31 = _out_rifireMux_T_942; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_943 = ~_out_T_1606; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_945 = _out_rifireMux_T_260 & out_frontSel_171; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_946 = _out_rifireMux_T_945 & _out_T_1854; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_987 = _out_rifireMux_T_946; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_988 = _out_rifireMux_T_946; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_989 = _out_rifireMux_T_946; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_990 = _out_rifireMux_T_946; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_991 = _out_rifireMux_T_946; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_992 = _out_rifireMux_T_946; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_993 = _out_rifireMux_T_946; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_994 = _out_rifireMux_T_946; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_947 = ~_out_T_1854; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_949 = _out_rifireMux_T_260 & out_frontSel_172; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_950 = _out_rifireMux_T_949 & _out_T_1768; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_649 = _out_rifireMux_T_950; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_650 = _out_rifireMux_T_950; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_651 = _out_rifireMux_T_950; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_652 = _out_rifireMux_T_950; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_653 = _out_rifireMux_T_950; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_654 = _out_rifireMux_T_950; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_655 = _out_rifireMux_T_950; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_656 = _out_rifireMux_T_950; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_951 = ~_out_T_1768; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_953 = _out_rifireMux_T_260 & out_frontSel_173; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_954 = _out_rifireMux_T_953 & _out_T_1718; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_459 = _out_rifireMux_T_954; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_460 = _out_rifireMux_T_954; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_461 = _out_rifireMux_T_954; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_462 = _out_rifireMux_T_954; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_463 = _out_rifireMux_T_954; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_464 = _out_rifireMux_T_954; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_465 = _out_rifireMux_T_954; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_466 = _out_rifireMux_T_954; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_955 = ~_out_T_1718; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_957 = _out_rifireMux_T_260 & out_frontSel_174; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_958 = _out_rifireMux_T_957 & _out_T_1620; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_80 = _out_rifireMux_T_958; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_81 = _out_rifireMux_T_958; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_82 = _out_rifireMux_T_958; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_83 = _out_rifireMux_T_958; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_84 = _out_rifireMux_T_958; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_85 = _out_rifireMux_T_958; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_86 = _out_rifireMux_T_958; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_87 = _out_rifireMux_T_958; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_959 = ~_out_T_1620; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_961 = _out_rifireMux_T_260 & out_frontSel_175; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_962 = _out_rifireMux_T_961 & _out_T_1832; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_899 = _out_rifireMux_T_962; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_900 = _out_rifireMux_T_962; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_901 = _out_rifireMux_T_962; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_902 = _out_rifireMux_T_962; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_903 = _out_rifireMux_T_962; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_904 = _out_rifireMux_T_962; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_905 = _out_rifireMux_T_962; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_906 = _out_rifireMux_T_962; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_963 = ~_out_T_1832; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_965 = _out_rifireMux_T_260 & out_frontSel_176; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_966 = _out_rifireMux_T_965 & _out_T_1750; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_577 = _out_rifireMux_T_966; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_578 = _out_rifireMux_T_966; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_579 = _out_rifireMux_T_966; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_580 = _out_rifireMux_T_966; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_581 = _out_rifireMux_T_966; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_582 = _out_rifireMux_T_966; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_583 = _out_rifireMux_T_966; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_584 = _out_rifireMux_T_966; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_967 = ~_out_T_1750; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_969 = _out_rifireMux_T_260 & out_frontSel_177; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_970 = _out_rifireMux_T_969 & _out_T_1826; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_875 = _out_rifireMux_T_970; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_876 = _out_rifireMux_T_970; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_877 = _out_rifireMux_T_970; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_878 = _out_rifireMux_T_970; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_879 = _out_rifireMux_T_970; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_880 = _out_rifireMux_T_970; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_881 = _out_rifireMux_T_970; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_882 = _out_rifireMux_T_970; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_971 = ~_out_T_1826; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_973 = _out_rifireMux_T_260 & out_frontSel_178; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_974 = _out_rifireMux_T_973 & _out_T_1892; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1139 = _out_rifireMux_T_974; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1140 = _out_rifireMux_T_974; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1141 = _out_rifireMux_T_974; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1142 = _out_rifireMux_T_974; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1143 = _out_rifireMux_T_974; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1144 = _out_rifireMux_T_974; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1145 = _out_rifireMux_T_974; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1146 = _out_rifireMux_T_974; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_975 = ~_out_T_1892; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_977 = _out_rifireMux_T_260 & out_frontSel_179; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_978 = _out_rifireMux_T_977 & _out_T_1646; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_184 = _out_rifireMux_T_978; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_185 = _out_rifireMux_T_978; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_186 = _out_rifireMux_T_978; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_187 = _out_rifireMux_T_978; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_188 = _out_rifireMux_T_978; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_189 = _out_rifireMux_T_978; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_190 = _out_rifireMux_T_978; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_191 = _out_rifireMux_T_978; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_979 = ~_out_T_1646; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_981 = _out_rifireMux_T_260 & out_frontSel_180; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_982 = _out_rifireMux_T_981 & _out_T_1746; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_561 = _out_rifireMux_T_982; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_562 = _out_rifireMux_T_982; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_563 = _out_rifireMux_T_982; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_564 = _out_rifireMux_T_982; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_565 = _out_rifireMux_T_982; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_566 = _out_rifireMux_T_982; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_567 = _out_rifireMux_T_982; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_568 = _out_rifireMux_T_982; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_983 = ~_out_T_1746; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_985 = _out_rifireMux_T_260 & out_frontSel_181; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_986 = _out_rifireMux_T_985 & _out_T_1762; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_625 = _out_rifireMux_T_986; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_626 = _out_rifireMux_T_986; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_627 = _out_rifireMux_T_986; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_628 = _out_rifireMux_T_986; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_629 = _out_rifireMux_T_986; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_630 = _out_rifireMux_T_986; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_631 = _out_rifireMux_T_986; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_632 = _out_rifireMux_T_986; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_987 = ~_out_T_1762; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_989 = _out_rifireMux_T_260 & out_frontSel_182; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_990 = _out_rifireMux_T_989 & _out_T_1828; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_883 = _out_rifireMux_T_990; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_884 = _out_rifireMux_T_990; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_885 = _out_rifireMux_T_990; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_886 = _out_rifireMux_T_990; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_887 = _out_rifireMux_T_990; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_888 = _out_rifireMux_T_990; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_889 = _out_rifireMux_T_990; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_890 = _out_rifireMux_T_990; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_991 = ~_out_T_1828; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_993 = _out_rifireMux_T_260 & out_frontSel_183; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_994 = _out_rifireMux_T_993 & _out_T_1872; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1059 = _out_rifireMux_T_994; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1060 = _out_rifireMux_T_994; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1061 = _out_rifireMux_T_994; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1062 = _out_rifireMux_T_994; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1063 = _out_rifireMux_T_994; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1064 = _out_rifireMux_T_994; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1065 = _out_rifireMux_T_994; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1066 = _out_rifireMux_T_994; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_995 = ~_out_T_1872; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_997 = _out_rifireMux_T_260 & out_frontSel_184; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_998 = _out_rifireMux_T_997 & _out_T_1626; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_104 = _out_rifireMux_T_998; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_105 = _out_rifireMux_T_998; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_106 = _out_rifireMux_T_998; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_107 = _out_rifireMux_T_998; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_108 = _out_rifireMux_T_998; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_109 = _out_rifireMux_T_998; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_110 = _out_rifireMux_T_998; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_111 = _out_rifireMux_T_998; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_999 = ~_out_T_1626; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1001 = _out_rifireMux_T_260 & out_frontSel_185; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1002 = _out_rifireMux_T_1001 & _out_T_1622; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_88 = _out_rifireMux_T_1002; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_89 = _out_rifireMux_T_1002; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_90 = _out_rifireMux_T_1002; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_91 = _out_rifireMux_T_1002; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_92 = _out_rifireMux_T_1002; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_93 = _out_rifireMux_T_1002; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_94 = _out_rifireMux_T_1002; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_95 = _out_rifireMux_T_1002; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1003 = ~_out_T_1622; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1005 = _out_rifireMux_T_260 & out_frontSel_186; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1006 = _out_rifireMux_T_1005 & _out_T_1850; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_971 = _out_rifireMux_T_1006; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_972 = _out_rifireMux_T_1006; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_973 = _out_rifireMux_T_1006; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_974 = _out_rifireMux_T_1006; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_975 = _out_rifireMux_T_1006; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_976 = _out_rifireMux_T_1006; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_977 = _out_rifireMux_T_1006; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_978 = _out_rifireMux_T_1006; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1007 = ~_out_T_1850; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1009 = _out_rifireMux_T_260 & out_frontSel_187; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1010 = _out_rifireMux_T_1009 & _out_T_1766; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_641 = _out_rifireMux_T_1010; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_642 = _out_rifireMux_T_1010; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_643 = _out_rifireMux_T_1010; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_644 = _out_rifireMux_T_1010; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_645 = _out_rifireMux_T_1010; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_646 = _out_rifireMux_T_1010; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_647 = _out_rifireMux_T_1010; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_648 = _out_rifireMux_T_1010; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1011 = ~_out_T_1766; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1013 = _out_rifireMux_T_260 & out_frontSel_188; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1014 = _out_rifireMux_T_1013 & _out_T_1700; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_394 = _out_rifireMux_T_1014; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_395 = _out_rifireMux_T_1014; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_396 = _out_rifireMux_T_1014; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_397 = _out_rifireMux_T_1014; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_398 = _out_rifireMux_T_1014; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_399 = _out_rifireMux_T_1014; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_400 = _out_rifireMux_T_1014; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_401 = _out_rifireMux_T_1014; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1015 = ~_out_T_1700; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1017 = _out_rifireMux_T_260 & out_frontSel_189; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1018 = _out_rifireMux_T_1017 & _out_T_1634; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_136 = _out_rifireMux_T_1018; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_137 = _out_rifireMux_T_1018; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_138 = _out_rifireMux_T_1018; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_139 = _out_rifireMux_T_1018; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_140 = _out_rifireMux_T_1018; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_141 = _out_rifireMux_T_1018; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_142 = _out_rifireMux_T_1018; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_143 = _out_rifireMux_T_1018; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1019 = ~_out_T_1634; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1021 = _out_rifireMux_T_260 & out_frontSel_190; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1022 = _out_rifireMux_T_1021 & _out_T_1870; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1051 = _out_rifireMux_T_1022; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1052 = _out_rifireMux_T_1022; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1053 = _out_rifireMux_T_1022; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1054 = _out_rifireMux_T_1022; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1055 = _out_rifireMux_T_1022; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1056 = _out_rifireMux_T_1022; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1057 = _out_rifireMux_T_1022; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1058 = _out_rifireMux_T_1022; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1023 = ~_out_T_1870; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1025 = _out_rifireMux_T_260 & out_frontSel_191; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1026 = _out_rifireMux_T_1025 & _out_T_1752; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_585 = _out_rifireMux_T_1026; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_586 = _out_rifireMux_T_1026; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_587 = _out_rifireMux_T_1026; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_588 = _out_rifireMux_T_1026; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_589 = _out_rifireMux_T_1026; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_590 = _out_rifireMux_T_1026; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_591 = _out_rifireMux_T_1026; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_592 = _out_rifireMux_T_1026; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1027 = ~_out_T_1752; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1029 = _out_rifireMux_T_260 & out_frontSel_192; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1030 = _out_rifireMux_T_1029 & _out_T_1682; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_328 = _out_rifireMux_T_1030; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_329 = _out_rifireMux_T_1030; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_330 = _out_rifireMux_T_1030; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_331 = _out_rifireMux_T_1030; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_332 = _out_rifireMux_T_1030; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_333 = _out_rifireMux_T_1030; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_334 = _out_rifireMux_T_1030; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_335 = _out_rifireMux_T_1030; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1031 = ~_out_T_1682; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1033 = _out_rifireMux_T_260 & out_frontSel_193; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1034 = _out_rifireMux_T_1033 & _out_T_1708; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_426 = _out_rifireMux_T_1034; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_427 = _out_rifireMux_T_1034; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_428 = _out_rifireMux_T_1034; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_429 = _out_rifireMux_T_1034; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_430 = _out_rifireMux_T_1034; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_431 = _out_rifireMux_T_1034; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_432 = _out_rifireMux_T_1034; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_433 = _out_rifireMux_T_1034; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1035 = ~_out_T_1708; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1037 = _out_rifireMux_T_260 & out_frontSel_194; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1038 = _out_rifireMux_T_1037 & _out_T_1816; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_835 = _out_rifireMux_T_1038; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_836 = _out_rifireMux_T_1038; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_837 = _out_rifireMux_T_1038; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_838 = _out_rifireMux_T_1038; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_839 = _out_rifireMux_T_1038; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_840 = _out_rifireMux_T_1038; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_841 = _out_rifireMux_T_1038; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_842 = _out_rifireMux_T_1038; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1039 = ~_out_T_1816; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1041 = _out_rifireMux_T_260 & out_frontSel_195; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1042 = _out_rifireMux_T_1041 & _out_T_1884; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1107 = _out_rifireMux_T_1042; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1108 = _out_rifireMux_T_1042; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1109 = _out_rifireMux_T_1042; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1110 = _out_rifireMux_T_1042; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1111 = _out_rifireMux_T_1042; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1112 = _out_rifireMux_T_1042; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1113 = _out_rifireMux_T_1042; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1114 = _out_rifireMux_T_1042; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1043 = ~_out_T_1884; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1045 = _out_rifireMux_T_260 & out_frontSel_196; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1046 = _out_rifireMux_T_1045 & _out_T_1630; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_120 = _out_rifireMux_T_1046; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_121 = _out_rifireMux_T_1046; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_122 = _out_rifireMux_T_1046; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_123 = _out_rifireMux_T_1046; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_124 = _out_rifireMux_T_1046; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_125 = _out_rifireMux_T_1046; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_126 = _out_rifireMux_T_1046; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_127 = _out_rifireMux_T_1046; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1047 = ~_out_T_1630; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1049 = _out_rifireMux_T_260 & out_frontSel_197; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1050 = _out_rifireMux_T_1049 & _out_T_1694; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_370 = _out_rifireMux_T_1050; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_371 = _out_rifireMux_T_1050; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_372 = _out_rifireMux_T_1050; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_373 = _out_rifireMux_T_1050; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_374 = _out_rifireMux_T_1050; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_375 = _out_rifireMux_T_1050; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_376 = _out_rifireMux_T_1050; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_377 = _out_rifireMux_T_1050; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1051 = ~_out_T_1694; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1053 = _out_rifireMux_T_260 & out_frontSel_198; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1054 = _out_rifireMux_T_1053 & _out_T_1788; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_723 = _out_rifireMux_T_1054; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_724 = _out_rifireMux_T_1054; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_725 = _out_rifireMux_T_1054; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_726 = _out_rifireMux_T_1054; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_727 = _out_rifireMux_T_1054; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_728 = _out_rifireMux_T_1054; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_729 = _out_rifireMux_T_1054; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_730 = _out_rifireMux_T_1054; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1055 = ~_out_T_1788; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1057 = _out_rifireMux_T_260 & out_frontSel_199; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1058 = _out_rifireMux_T_1057 & _out_T_1824; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_867 = _out_rifireMux_T_1058; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_868 = _out_rifireMux_T_1058; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_869 = _out_rifireMux_T_1058; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_870 = _out_rifireMux_T_1058; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_871 = _out_rifireMux_T_1058; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_872 = _out_rifireMux_T_1058; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_873 = _out_rifireMux_T_1058; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_874 = _out_rifireMux_T_1058; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1059 = ~_out_T_1824; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1061 = _out_rifireMux_T_260 & out_frontSel_200; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1062 = _out_rifireMux_T_1061 & _out_T_1896; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1155 = _out_rifireMux_T_1062; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1156 = _out_rifireMux_T_1062; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1157 = _out_rifireMux_T_1062; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1158 = _out_rifireMux_T_1062; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1159 = _out_rifireMux_T_1062; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1160 = _out_rifireMux_T_1062; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1161 = _out_rifireMux_T_1062; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1162 = _out_rifireMux_T_1062; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1063 = ~_out_T_1896; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1065 = _out_rifireMux_T_260 & out_frontSel_201; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1066 = _out_rifireMux_T_1065 & _out_T_1674; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_296 = _out_rifireMux_T_1066; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_297 = _out_rifireMux_T_1066; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_298 = _out_rifireMux_T_1066; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_299 = _out_rifireMux_T_1066; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_300 = _out_rifireMux_T_1066; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_301 = _out_rifireMux_T_1066; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_302 = _out_rifireMux_T_1066; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_303 = _out_rifireMux_T_1066; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1067 = ~_out_T_1674; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1069 = _out_rifireMux_T_260 & out_frontSel_202; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1070 = _out_rifireMux_T_1069 & _out_T_1614; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_56 = _out_rifireMux_T_1070; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_57 = _out_rifireMux_T_1070; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_58 = _out_rifireMux_T_1070; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_59 = _out_rifireMux_T_1070; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_60 = _out_rifireMux_T_1070; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_61 = _out_rifireMux_T_1070; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_62 = _out_rifireMux_T_1070; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_63 = _out_rifireMux_T_1070; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1071 = ~_out_T_1614; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1073 = _out_rifireMux_T_260 & out_frontSel_203; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1074 = _out_rifireMux_T_1073 & _out_T_1836; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_915 = _out_rifireMux_T_1074; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_916 = _out_rifireMux_T_1074; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_917 = _out_rifireMux_T_1074; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_918 = _out_rifireMux_T_1074; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_919 = _out_rifireMux_T_1074; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_920 = _out_rifireMux_T_1074; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_921 = _out_rifireMux_T_1074; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_922 = _out_rifireMux_T_1074; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1075 = ~_out_T_1836; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1077 = _out_rifireMux_T_260 & out_frontSel_204; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1078 = _out_rifireMux_T_1077 & _out_T_1754; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_593 = _out_rifireMux_T_1078; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_594 = _out_rifireMux_T_1078; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_595 = _out_rifireMux_T_1078; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_596 = _out_rifireMux_T_1078; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_597 = _out_rifireMux_T_1078; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_598 = _out_rifireMux_T_1078; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_599 = _out_rifireMux_T_1078; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_600 = _out_rifireMux_T_1078; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1079 = ~_out_T_1754; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1081 = _out_rifireMux_T_260 & out_frontSel_205; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1082 = _out_rifireMux_T_1081 & _out_T_1726; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_487 = _out_rifireMux_T_1082; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_488 = _out_rifireMux_T_1082; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_489 = _out_rifireMux_T_1082; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_490 = _out_rifireMux_T_1082; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_491 = _out_rifireMux_T_1082; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_492 = _out_rifireMux_T_1082; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_493 = _out_rifireMux_T_1082; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_494 = _out_rifireMux_T_1082; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1083 = ~_out_T_1726; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1085 = _out_rifireMux_T_260 & out_frontSel_206; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1086 = _out_rifireMux_T_1085 & _out_T_1668; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_272 = _out_rifireMux_T_1086; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_273 = _out_rifireMux_T_1086; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_274 = _out_rifireMux_T_1086; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_275 = _out_rifireMux_T_1086; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_276 = _out_rifireMux_T_1086; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_277 = _out_rifireMux_T_1086; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_278 = _out_rifireMux_T_1086; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_279 = _out_rifireMux_T_1086; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1087 = ~_out_T_1668; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1089 = _out_rifireMux_T_260 & out_frontSel_207; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1090 = _out_rifireMux_T_1089 & _out_T_1858; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1003 = _out_rifireMux_T_1090; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1004 = _out_rifireMux_T_1090; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1005 = _out_rifireMux_T_1090; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1006 = _out_rifireMux_T_1090; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1007 = _out_rifireMux_T_1090; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1008 = _out_rifireMux_T_1090; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1009 = _out_rifireMux_T_1090; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1010 = _out_rifireMux_T_1090; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1091 = ~_out_T_1858; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1093 = _out_rifireMux_T_260 & out_frontSel_208; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1094 = _out_rifireMux_T_1093 & _out_T_1778; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_689 = _out_rifireMux_T_1094; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_690 = _out_rifireMux_T_1094; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_691 = _out_rifireMux_T_1094; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_692 = _out_rifireMux_T_1094; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_693 = _out_rifireMux_T_1094; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_694 = _out_rifireMux_T_1094; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_695 = _out_rifireMux_T_1094; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_696 = _out_rifireMux_T_1094; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1095 = ~_out_T_1778; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1097 = _out_rifireMux_T_260 & out_frontSel_209; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1098 = _out_rifireMux_T_1097 & _out_T_1812; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_819 = _out_rifireMux_T_1098; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_820 = _out_rifireMux_T_1098; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_821 = _out_rifireMux_T_1098; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_822 = _out_rifireMux_T_1098; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_823 = _out_rifireMux_T_1098; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_824 = _out_rifireMux_T_1098; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_825 = _out_rifireMux_T_1098; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_826 = _out_rifireMux_T_1098; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1099 = ~_out_T_1812; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1101 = _out_rifireMux_T_260 & out_frontSel_210; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1102 = _out_rifireMux_T_1101 & _out_T_1878; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1083 = _out_rifireMux_T_1102; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1084 = _out_rifireMux_T_1102; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1085 = _out_rifireMux_T_1102; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1086 = _out_rifireMux_T_1102; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1087 = _out_rifireMux_T_1102; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1088 = _out_rifireMux_T_1102; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1089 = _out_rifireMux_T_1102; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1090 = _out_rifireMux_T_1102; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1103 = ~_out_T_1878; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1105 = _out_rifireMux_T_260 & out_frontSel_211; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1106 = _out_rifireMux_T_1105 & _out_T_1652; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_208 = _out_rifireMux_T_1106; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_209 = _out_rifireMux_T_1106; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_210 = _out_rifireMux_T_1106; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_211 = _out_rifireMux_T_1106; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_212 = _out_rifireMux_T_1106; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_213 = _out_rifireMux_T_1106; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_214 = _out_rifireMux_T_1106; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_215 = _out_rifireMux_T_1106; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1107 = ~_out_T_1652; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1109 = _out_rifireMux_T_260 & out_frontSel_212; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1110 = _out_rifireMux_T_1109 & _out_T_1710; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_434 = _out_rifireMux_T_1110; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_435 = _out_rifireMux_T_1110; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_436 = _out_rifireMux_T_1110; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_437 = _out_rifireMux_T_1110; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_438 = _out_rifireMux_T_1110; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_439 = _out_rifireMux_T_1110; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_440 = _out_rifireMux_T_1110; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_441 = _out_rifireMux_T_1110; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1111 = ~_out_T_1710; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1113 = _out_rifireMux_T_260 & out_frontSel_213; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1114 = _out_rifireMux_T_1113 & _out_T_1784; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_707 = _out_rifireMux_T_1114; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_708 = _out_rifireMux_T_1114; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_709 = _out_rifireMux_T_1114; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_710 = _out_rifireMux_T_1114; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_711 = _out_rifireMux_T_1114; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_712 = _out_rifireMux_T_1114; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_713 = _out_rifireMux_T_1114; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_714 = _out_rifireMux_T_1114; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1115 = ~_out_T_1784; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1117 = _out_rifireMux_T_260 & out_frontSel_214; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1118 = _out_rifireMux_T_1117 & _out_T_1860; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1011 = _out_rifireMux_T_1118; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1012 = _out_rifireMux_T_1118; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1013 = _out_rifireMux_T_1118; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1014 = _out_rifireMux_T_1118; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1015 = _out_rifireMux_T_1118; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1016 = _out_rifireMux_T_1118; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1017 = _out_rifireMux_T_1118; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1018 = _out_rifireMux_T_1118; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1119 = ~_out_T_1860; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1121 = _out_rifireMux_T_260 & out_frontSel_215; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1122 = _out_rifireMux_T_1121 & _out_T_1900; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1171 = _out_rifireMux_T_1122; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1172 = _out_rifireMux_T_1122; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1173 = _out_rifireMux_T_1122; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1174 = _out_rifireMux_T_1122; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1175 = _out_rifireMux_T_1122; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1176 = _out_rifireMux_T_1122; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1177 = _out_rifireMux_T_1122; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1178 = _out_rifireMux_T_1122; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1123 = ~_out_T_1900; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1125 = _out_rifireMux_T_260 & out_frontSel_216; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1126 = _out_rifireMux_T_1125 & _out_T_1642; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_168 = _out_rifireMux_T_1126; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_169 = _out_rifireMux_T_1126; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_170 = _out_rifireMux_T_1126; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_171 = _out_rifireMux_T_1126; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_172 = _out_rifireMux_T_1126; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_173 = _out_rifireMux_T_1126; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_174 = _out_rifireMux_T_1126; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_175 = _out_rifireMux_T_1126; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1127 = ~_out_T_1642; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1129 = _out_rifireMux_T_260 & out_frontSel_217; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1130 = _out_rifireMux_T_1129 & _out_T_1610; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_40 = _out_rifireMux_T_1130; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_41 = _out_rifireMux_T_1130; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_42 = _out_rifireMux_T_1130; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_43 = _out_rifireMux_T_1130; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_44 = _out_rifireMux_T_1130; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_45 = _out_rifireMux_T_1130; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_46 = _out_rifireMux_T_1130; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_47 = _out_rifireMux_T_1130; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1131 = ~_out_T_1610; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1133 = _out_rifireMux_T_260 & out_frontSel_218; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1134 = _out_rifireMux_T_1133 & _out_T_1838; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_923 = _out_rifireMux_T_1134; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_924 = _out_rifireMux_T_1134; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_925 = _out_rifireMux_T_1134; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_926 = _out_rifireMux_T_1134; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_927 = _out_rifireMux_T_1134; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_928 = _out_rifireMux_T_1134; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_929 = _out_rifireMux_T_1134; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_930 = _out_rifireMux_T_1134; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1135 = ~_out_T_1838; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1137 = _out_rifireMux_T_260 & out_frontSel_219; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1138 = _out_rifireMux_T_1137 & _out_T_1772; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_665 = _out_rifireMux_T_1138; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_666 = _out_rifireMux_T_1138; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_667 = _out_rifireMux_T_1138; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_668 = _out_rifireMux_T_1138; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_669 = _out_rifireMux_T_1138; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_670 = _out_rifireMux_T_1138; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_671 = _out_rifireMux_T_1138; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_672 = _out_rifireMux_T_1138; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1139 = ~_out_T_1772; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1141 = _out_rifireMux_T_260 & out_frontSel_220; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1142 = _out_rifireMux_T_1141 & _out_T_1676; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_304 = _out_rifireMux_T_1142; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_305 = _out_rifireMux_T_1142; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_306 = _out_rifireMux_T_1142; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_307 = _out_rifireMux_T_1142; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_308 = _out_rifireMux_T_1142; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_309 = _out_rifireMux_T_1142; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_310 = _out_rifireMux_T_1142; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_311 = _out_rifireMux_T_1142; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1143 = ~_out_T_1676; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1145 = _out_rifireMux_T_260 & out_frontSel_221; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1146 = _out_rifireMux_T_1145 & _out_T_1658; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_232 = _out_rifireMux_T_1146; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_233 = _out_rifireMux_T_1146; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_234 = _out_rifireMux_T_1146; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_235 = _out_rifireMux_T_1146; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_236 = _out_rifireMux_T_1146; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_237 = _out_rifireMux_T_1146; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_238 = _out_rifireMux_T_1146; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_239 = _out_rifireMux_T_1146; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1147 = ~_out_T_1658; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1149 = _out_rifireMux_T_260 & out_frontSel_222; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1150 = _out_rifireMux_T_1149 & _out_T_1902; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1179 = _out_rifireMux_T_1150; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1180 = _out_rifireMux_T_1150; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1181 = _out_rifireMux_T_1150; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1182 = _out_rifireMux_T_1150; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1183 = _out_rifireMux_T_1150; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1184 = _out_rifireMux_T_1150; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1185 = _out_rifireMux_T_1150; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1186 = _out_rifireMux_T_1150; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1151 = ~_out_T_1902; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1153 = _out_rifireMux_T_260 & out_frontSel_223; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1154 = _out_rifireMux_T_1153 & _out_T_1798; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_763 = _out_rifireMux_T_1154; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_764 = _out_rifireMux_T_1154; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_765 = _out_rifireMux_T_1154; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_766 = _out_rifireMux_T_1154; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_767 = _out_rifireMux_T_1154; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_768 = _out_rifireMux_T_1154; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_769 = _out_rifireMux_T_1154; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_770 = _out_rifireMux_T_1154; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1155 = ~_out_T_1798; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1157 = _out_rifireMux_T_260 & out_frontSel_224; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1158 = _out_rifireMux_T_1157 & _out_T_1696; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_378 = _out_rifireMux_T_1158; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_379 = _out_rifireMux_T_1158; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_380 = _out_rifireMux_T_1158; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_381 = _out_rifireMux_T_1158; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_382 = _out_rifireMux_T_1158; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_383 = _out_rifireMux_T_1158; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_384 = _out_rifireMux_T_1158; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_385 = _out_rifireMux_T_1158; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1159 = ~_out_T_1696; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1161 = _out_rifireMux_T_260 & out_frontSel_225; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1162 = _out_rifireMux_T_1161 & _out_T_1706; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_418 = _out_rifireMux_T_1162; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_419 = _out_rifireMux_T_1162; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_420 = _out_rifireMux_T_1162; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_421 = _out_rifireMux_T_1162; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_422 = _out_rifireMux_T_1162; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_423 = _out_rifireMux_T_1162; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_424 = _out_rifireMux_T_1162; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_425 = _out_rifireMux_T_1162; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1163 = ~_out_T_1706; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1165 = _out_rifireMux_T_260 & out_frontSel_226; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1166 = _out_rifireMux_T_1165 & _out_T_1802; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_779 = _out_rifireMux_T_1166; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_780 = _out_rifireMux_T_1166; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_781 = _out_rifireMux_T_1166; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_782 = _out_rifireMux_T_1166; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_783 = _out_rifireMux_T_1166; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_784 = _out_rifireMux_T_1166; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_785 = _out_rifireMux_T_1166; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_786 = _out_rifireMux_T_1166; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1167 = ~_out_T_1802; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1169 = _out_rifireMux_T_260 & out_frontSel_227; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1170 = _out_rifireMux_T_1169 & _out_T_1908; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1203 = _out_rifireMux_T_1170; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1204 = _out_rifireMux_T_1170; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1205 = _out_rifireMux_T_1170; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1206 = _out_rifireMux_T_1170; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1207 = _out_rifireMux_T_1170; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1208 = _out_rifireMux_T_1170; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1209 = _out_rifireMux_T_1170; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1210 = _out_rifireMux_T_1170; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1171 = ~_out_T_1908; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1173 = _out_rifireMux_T_260 & out_frontSel_228; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1174 = _out_rifireMux_T_1173 & _out_T_1638; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_152 = _out_rifireMux_T_1174; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_153 = _out_rifireMux_T_1174; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_154 = _out_rifireMux_T_1174; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_155 = _out_rifireMux_T_1174; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_156 = _out_rifireMux_T_1174; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_157 = _out_rifireMux_T_1174; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_158 = _out_rifireMux_T_1174; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_159 = _out_rifireMux_T_1174; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1175 = ~_out_T_1638; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1177 = _out_rifireMux_T_260 & out_frontSel_229; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1178 = _out_rifireMux_T_1177 & _out_T_1690; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_354 = _out_rifireMux_T_1178; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_355 = _out_rifireMux_T_1178; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_356 = _out_rifireMux_T_1178; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_357 = _out_rifireMux_T_1178; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_358 = _out_rifireMux_T_1178; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_359 = _out_rifireMux_T_1178; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_360 = _out_rifireMux_T_1178; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_361 = _out_rifireMux_T_1178; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1179 = ~_out_T_1690; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1181 = _out_rifireMux_T_260 & out_frontSel_230; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1182 = _out_rifireMux_T_1181 & _out_T_1774; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_673 = _out_rifireMux_T_1182; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_674 = _out_rifireMux_T_1182; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_675 = _out_rifireMux_T_1182; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_676 = _out_rifireMux_T_1182; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_677 = _out_rifireMux_T_1182; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_678 = _out_rifireMux_T_1182; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_679 = _out_rifireMux_T_1182; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_680 = _out_rifireMux_T_1182; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1183 = ~_out_T_1774; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1185 = _out_rifireMux_T_260 & out_frontSel_231; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1186 = _out_rifireMux_T_1185 & _out_T_1844; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_947 = _out_rifireMux_T_1186; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_948 = _out_rifireMux_T_1186; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_949 = _out_rifireMux_T_1186; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_950 = _out_rifireMux_T_1186; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_951 = _out_rifireMux_T_1186; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_952 = _out_rifireMux_T_1186; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_953 = _out_rifireMux_T_1186; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_954 = _out_rifireMux_T_1186; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1187 = ~_out_T_1844; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1189 = _out_rifireMux_T_260 & out_frontSel_232; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1190 = _out_rifireMux_T_1189 & _out_T_1904; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1187 = _out_rifireMux_T_1190; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1188 = _out_rifireMux_T_1190; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1189 = _out_rifireMux_T_1190; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1190 = _out_rifireMux_T_1190; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1191 = _out_rifireMux_T_1190; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1192 = _out_rifireMux_T_1190; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1193 = _out_rifireMux_T_1190; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1194 = _out_rifireMux_T_1190; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1191 = ~_out_T_1904; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1193 = _out_rifireMux_T_260 & out_frontSel_233; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1194 = _out_rifireMux_T_1193 & _out_T_1670; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_280 = _out_rifireMux_T_1194; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_281 = _out_rifireMux_T_1194; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_282 = _out_rifireMux_T_1194; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_283 = _out_rifireMux_T_1194; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_284 = _out_rifireMux_T_1194; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_285 = _out_rifireMux_T_1194; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_286 = _out_rifireMux_T_1194; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_287 = _out_rifireMux_T_1194; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1195 = ~_out_T_1670; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1197 = _out_rifireMux_T_260 & out_frontSel_234; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1198 = _out_rifireMux_T_1197 & _out_T_1604; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_16 = _out_rifireMux_T_1198; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_17 = _out_rifireMux_T_1198; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_18 = _out_rifireMux_T_1198; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_19 = _out_rifireMux_T_1198; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_20 = _out_rifireMux_T_1198; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_21 = _out_rifireMux_T_1198; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_22 = _out_rifireMux_T_1198; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_23 = _out_rifireMux_T_1198; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1199 = ~_out_T_1604; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1201 = _out_rifireMux_T_260 & out_frontSel_235; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1202 = _out_rifireMux_T_1201 & _out_T_1862; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1019 = _out_rifireMux_T_1202; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1020 = _out_rifireMux_T_1202; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1021 = _out_rifireMux_T_1202; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1022 = _out_rifireMux_T_1202; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1023 = _out_rifireMux_T_1202; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1024 = _out_rifireMux_T_1202; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1025 = _out_rifireMux_T_1202; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1026 = _out_rifireMux_T_1202; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1203 = ~_out_T_1862; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1205 = _out_rifireMux_T_260 & out_frontSel_236; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1206 = _out_rifireMux_T_1205 & _out_T_1760; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_617 = _out_rifireMux_T_1206; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_618 = _out_rifireMux_T_1206; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_619 = _out_rifireMux_T_1206; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_620 = _out_rifireMux_T_1206; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_621 = _out_rifireMux_T_1206; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_622 = _out_rifireMux_T_1206; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_623 = _out_rifireMux_T_1206; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_624 = _out_rifireMux_T_1206; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1207 = ~_out_T_1760; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1209 = _out_rifireMux_T_260 & out_frontSel_237; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1210 = _out_rifireMux_T_1209 & _out_T_1730; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_503 = _out_rifireMux_T_1210; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_504 = _out_rifireMux_T_1210; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_505 = _out_rifireMux_T_1210; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_506 = _out_rifireMux_T_1210; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_507 = _out_rifireMux_T_1210; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_508 = _out_rifireMux_T_1210; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_509 = _out_rifireMux_T_1210; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_510 = _out_rifireMux_T_1210; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1211 = ~_out_T_1730; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1213 = _out_rifireMux_T_260 & out_frontSel_238; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1214 = _out_rifireMux_T_1213 & _out_T_1650; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_200 = _out_rifireMux_T_1214; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_201 = _out_rifireMux_T_1214; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_202 = _out_rifireMux_T_1214; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_203 = _out_rifireMux_T_1214; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_204 = _out_rifireMux_T_1214; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_205 = _out_rifireMux_T_1214; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_206 = _out_rifireMux_T_1214; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_207 = _out_rifireMux_T_1214; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1215 = ~_out_T_1650; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1217 = _out_rifireMux_T_260 & out_frontSel_239; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1218 = _out_rifireMux_T_1217 & _out_T_1886; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1115 = _out_rifireMux_T_1218; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1116 = _out_rifireMux_T_1218; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1117 = _out_rifireMux_T_1218; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1118 = _out_rifireMux_T_1218; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1119 = _out_rifireMux_T_1218; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1120 = _out_rifireMux_T_1218; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1121 = _out_rifireMux_T_1218; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1122 = _out_rifireMux_T_1218; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1219 = ~_out_T_1886; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1221 = _out_rifireMux_T_260 & out_frontSel_240; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1222 = _out_rifireMux_T_1221 & _out_T_1792; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_739 = _out_rifireMux_T_1222; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_740 = _out_rifireMux_T_1222; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_741 = _out_rifireMux_T_1222; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_742 = _out_rifireMux_T_1222; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_743 = _out_rifireMux_T_1222; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_744 = _out_rifireMux_T_1222; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_745 = _out_rifireMux_T_1222; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_746 = _out_rifireMux_T_1222; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1223 = ~_out_T_1792; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1225 = _out_rifireMux_T_260 & out_frontSel_241; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1226 = _out_rifireMux_T_1225 & _out_T_1804; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_787 = _out_rifireMux_T_1226; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_788 = _out_rifireMux_T_1226; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_789 = _out_rifireMux_T_1226; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_790 = _out_rifireMux_T_1226; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_791 = _out_rifireMux_T_1226; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_792 = _out_rifireMux_T_1226; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_793 = _out_rifireMux_T_1226; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_794 = _out_rifireMux_T_1226; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1227 = ~_out_T_1804; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1229 = _out_rifireMux_T_260 & out_frontSel_242; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1230 = _out_rifireMux_T_1229 & _out_T_1888; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1123 = _out_rifireMux_T_1230; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1124 = _out_rifireMux_T_1230; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1125 = _out_rifireMux_T_1230; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1126 = _out_rifireMux_T_1230; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1127 = _out_rifireMux_T_1230; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1128 = _out_rifireMux_T_1230; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1129 = _out_rifireMux_T_1230; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1130 = _out_rifireMux_T_1230; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1231 = ~_out_T_1888; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1233 = _out_rifireMux_T_260 & out_frontSel_243; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1234 = _out_rifireMux_T_1233 & _out_T_1664; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_256 = _out_rifireMux_T_1234; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_257 = _out_rifireMux_T_1234; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_258 = _out_rifireMux_T_1234; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_259 = _out_rifireMux_T_1234; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_260 = _out_rifireMux_T_1234; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_261 = _out_rifireMux_T_1234; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_262 = _out_rifireMux_T_1234; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_263 = _out_rifireMux_T_1234; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1235 = ~_out_T_1664; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1237 = _out_rifireMux_T_260 & out_frontSel_244; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1238 = _out_rifireMux_T_1237 & _out_T_1734; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_519 = _out_rifireMux_T_1238; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_520 = _out_rifireMux_T_1238; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_521 = _out_rifireMux_T_1238; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_522 = _out_rifireMux_T_1238; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_523 = _out_rifireMux_T_1238; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_524 = _out_rifireMux_T_1238; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_525 = _out_rifireMux_T_1238; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_526 = _out_rifireMux_T_1238; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1239 = ~_out_T_1734; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1241 = _out_rifireMux_T_260 & out_frontSel_245; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1242 = _out_rifireMux_T_1241 & _out_T_1776; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_681 = _out_rifireMux_T_1242; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_682 = _out_rifireMux_T_1242; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_683 = _out_rifireMux_T_1242; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_684 = _out_rifireMux_T_1242; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_685 = _out_rifireMux_T_1242; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_686 = _out_rifireMux_T_1242; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_687 = _out_rifireMux_T_1242; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_688 = _out_rifireMux_T_1242; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1243 = ~_out_T_1776; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1245 = _out_rifireMux_T_260 & out_frontSel_246; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1246 = _out_rifireMux_T_1245 & _out_T_1864; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1027 = _out_rifireMux_T_1246; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1028 = _out_rifireMux_T_1246; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1029 = _out_rifireMux_T_1246; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1030 = _out_rifireMux_T_1246; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1031 = _out_rifireMux_T_1246; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1032 = _out_rifireMux_T_1246; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1033 = _out_rifireMux_T_1246; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1034 = _out_rifireMux_T_1246; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1247 = ~_out_T_1864; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1249 = _out_rifireMux_T_260 & out_frontSel_247; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1250 = _out_rifireMux_T_1249 & _out_T_1612; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_48 = _out_rifireMux_T_1250; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_49 = _out_rifireMux_T_1250; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_50 = _out_rifireMux_T_1250; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_51 = _out_rifireMux_T_1250; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_52 = _out_rifireMux_T_1250; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_53 = _out_rifireMux_T_1250; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_54 = _out_rifireMux_T_1250; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_55 = _out_rifireMux_T_1250; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1251 = ~_out_T_1612; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1253 = _out_rifireMux_T_260 & out_frontSel_248; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1254 = _out_rifireMux_T_1253 & _out_T_1672; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_288 = _out_rifireMux_T_1254; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_289 = _out_rifireMux_T_1254; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_290 = _out_rifireMux_T_1254; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_291 = _out_rifireMux_T_1254; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_292 = _out_rifireMux_T_1254; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_293 = _out_rifireMux_T_1254; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_294 = _out_rifireMux_T_1254; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_295 = _out_rifireMux_T_1254; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1255 = ~_out_T_1672; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1257 = _out_rifireMux_T_260 & out_frontSel_249; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1258 = _out_rifireMux_T_1257 & _out_T_1602; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_8 = _out_rifireMux_T_1258; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_9 = _out_rifireMux_T_1258; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_10 = _out_rifireMux_T_1258; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_11 = _out_rifireMux_T_1258; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_12 = _out_rifireMux_T_1258; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_13 = _out_rifireMux_T_1258; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_14 = _out_rifireMux_T_1258; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_15 = _out_rifireMux_T_1258; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1259 = ~_out_T_1602; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1261 = _out_rifireMux_T_260 & out_frontSel_250; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1262 = _out_rifireMux_T_1261 & _out_T_1842; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_939 = _out_rifireMux_T_1262; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_940 = _out_rifireMux_T_1262; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_941 = _out_rifireMux_T_1262; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_942 = _out_rifireMux_T_1262; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_943 = _out_rifireMux_T_1262; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_944 = _out_rifireMux_T_1262; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_945 = _out_rifireMux_T_1262; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_946 = _out_rifireMux_T_1262; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1263 = ~_out_T_1842; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1265 = _out_rifireMux_T_260 & out_frontSel_251; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1266 = _out_rifireMux_T_1265 & _out_T_1794; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_747 = _out_rifireMux_T_1266; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_748 = _out_rifireMux_T_1266; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_749 = _out_rifireMux_T_1266; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_750 = _out_rifireMux_T_1266; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_751 = _out_rifireMux_T_1266; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_752 = _out_rifireMux_T_1266; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_753 = _out_rifireMux_T_1266; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_754 = _out_rifireMux_T_1266; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1267 = ~_out_T_1794; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1269 = _out_rifireMux_T_260 & out_frontSel_252; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1270 = _out_rifireMux_T_1269 & _out_T_1692; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_362 = _out_rifireMux_T_1270; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_363 = _out_rifireMux_T_1270; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_364 = _out_rifireMux_T_1270; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_365 = _out_rifireMux_T_1270; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_366 = _out_rifireMux_T_1270; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_367 = _out_rifireMux_T_1270; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_368 = _out_rifireMux_T_1270; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_369 = _out_rifireMux_T_1270; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1271 = ~_out_T_1692; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1273 = _out_rifireMux_T_260 & out_frontSel_253; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1274 = _out_rifireMux_T_1273 & _out_T_1654; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_216 = _out_rifireMux_T_1274; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_217 = _out_rifireMux_T_1274; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_218 = _out_rifireMux_T_1274; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_219 = _out_rifireMux_T_1274; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_220 = _out_rifireMux_T_1274; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_221 = _out_rifireMux_T_1274; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_222 = _out_rifireMux_T_1274; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_223 = _out_rifireMux_T_1274; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1275 = ~_out_T_1654; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1277 = _out_rifireMux_T_260 & out_frontSel_254; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1278 = _out_rifireMux_T_1277 & _out_T_1906; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1195 = _out_rifireMux_T_1278; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1196 = _out_rifireMux_T_1278; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1197 = _out_rifireMux_T_1278; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1198 = _out_rifireMux_T_1278; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1199 = _out_rifireMux_T_1278; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1200 = _out_rifireMux_T_1278; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1201 = _out_rifireMux_T_1278; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1202 = _out_rifireMux_T_1278; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1279 = ~_out_T_1906; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1281 = _out_rifireMux_T_260 & out_frontSel_255; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1282 = _out_rifireMux_T_1281 & _out_T_1810; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_811 = _out_rifireMux_T_1282; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_812 = _out_rifireMux_T_1282; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_813 = _out_rifireMux_T_1282; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_814 = _out_rifireMux_T_1282; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_815 = _out_rifireMux_T_1282; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_816 = _out_rifireMux_T_1282; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_817 = _out_rifireMux_T_1282; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_818 = _out_rifireMux_T_1282; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1283 = ~_out_T_1810; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_261 = ~out_front_1_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_262 = _out_wifireMux_T_260 & _out_wifireMux_T_261; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_263 = _out_wifireMux_T_262 & out_frontSel_0_1; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_264 = _out_wifireMux_T_263 & _out_T_1716; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_451 = _out_wifireMux_T_264; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_452 = _out_wifireMux_T_264; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_453 = _out_wifireMux_T_264; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_454 = _out_wifireMux_T_264; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_455 = _out_wifireMux_T_264; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_456 = _out_wifireMux_T_264; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_457 = _out_wifireMux_T_264; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_458 = _out_wifireMux_T_264; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_265 = ~_out_T_1716; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_267 = _out_wifireMux_T_262 & out_frontSel_1_1; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_268 = _out_wifireMux_T_267 & _out_T_1624; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_96 = _out_wifireMux_T_268; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_97 = _out_wifireMux_T_268; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_98 = _out_wifireMux_T_268; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_99 = _out_wifireMux_T_268; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_100 = _out_wifireMux_T_268; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_101 = _out_wifireMux_T_268; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_102 = _out_wifireMux_T_268; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_103 = _out_wifireMux_T_268; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_269 = ~_out_T_1624; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_271 = _out_wifireMux_T_262 & out_frontSel_2_1; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_272 = _out_wifireMux_T_271 & _out_T_1846; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_955 = _out_wifireMux_T_272; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_956 = _out_wifireMux_T_272; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_957 = _out_wifireMux_T_272; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_958 = _out_wifireMux_T_272; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_959 = _out_wifireMux_T_272; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_960 = _out_wifireMux_T_272; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_961 = _out_wifireMux_T_272; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_962 = _out_wifireMux_T_272; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_273 = ~_out_T_1846; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_275 = _out_wifireMux_T_262 & out_frontSel_3_1; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_276 = _out_wifireMux_T_275 & _out_T_1756; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_601 = _out_wifireMux_T_276; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_602 = _out_wifireMux_T_276; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_603 = _out_wifireMux_T_276; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_604 = _out_wifireMux_T_276; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_605 = _out_wifireMux_T_276; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_606 = _out_wifireMux_T_276; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_607 = _out_wifireMux_T_276; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_608 = _out_wifireMux_T_276; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_277 = ~_out_T_1756; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_279 = _out_wifireMux_T_262 & out_frontSel_4_1; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_280 = _out_wifireMux_T_279 & _out_T_1678; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_312 = _out_wifireMux_T_280; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_313 = _out_wifireMux_T_280; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_314 = _out_wifireMux_T_280; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_315 = _out_wifireMux_T_280; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_316 = _out_wifireMux_T_280; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_317 = _out_wifireMux_T_280; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_318 = _out_wifireMux_T_280; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_319 = _out_wifireMux_T_280; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_281 = ~_out_T_1678; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_283 = _out_wifireMux_T_262 & out_frontSel_5_1; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_284 = _out_wifireMux_T_283 & _out_T_1640; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_160 = _out_wifireMux_T_284; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_161 = _out_wifireMux_T_284; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_162 = _out_wifireMux_T_284; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_163 = _out_wifireMux_T_284; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_164 = _out_wifireMux_T_284; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_165 = _out_wifireMux_T_284; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_166 = _out_wifireMux_T_284; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_167 = _out_wifireMux_T_284; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_285 = ~_out_T_1640; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_287 = _out_wifireMux_T_262 & out_frontSel_6_1; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_288 = _out_wifireMux_T_287 & _out_T_1876; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1075 = _out_wifireMux_T_288; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1076 = _out_wifireMux_T_288; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1077 = _out_wifireMux_T_288; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1078 = _out_wifireMux_T_288; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1079 = _out_wifireMux_T_288; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1080 = _out_wifireMux_T_288; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1081 = _out_wifireMux_T_288; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1082 = _out_wifireMux_T_288; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_289 = ~_out_T_1876; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_291 = _out_wifireMux_T_262 & out_frontSel_7_1; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_292 = _out_wifireMux_T_291 & _out_T_1822; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_859 = _out_wifireMux_T_292; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_860 = _out_wifireMux_T_292; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_861 = _out_wifireMux_T_292; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_862 = _out_wifireMux_T_292; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_863 = _out_wifireMux_T_292; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_864 = _out_wifireMux_T_292; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_865 = _out_wifireMux_T_292; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_866 = _out_wifireMux_T_292; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_293 = ~_out_T_1822; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_295 = _out_wifireMux_T_262 & out_frontSel_8_1; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_296 = _out_wifireMux_T_295 & _out_T_1742; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_545 = _out_wifireMux_T_296; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_546 = _out_wifireMux_T_296; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_547 = _out_wifireMux_T_296; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_548 = _out_wifireMux_T_296; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_549 = _out_wifireMux_T_296; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_550 = _out_wifireMux_T_296; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_551 = _out_wifireMux_T_296; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_552 = _out_wifireMux_T_296; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_297 = ~_out_T_1742; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_299 = _out_wifireMux_T_262 & out_frontSel_9_1; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_300 = _out_wifireMux_T_299 & _out_T_1666; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_264 = _out_wifireMux_T_300; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_265 = _out_wifireMux_T_300; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_266 = _out_wifireMux_T_300; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_267 = _out_wifireMux_T_300; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_268 = _out_wifireMux_T_300; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_269 = _out_wifireMux_T_300; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_270 = _out_wifireMux_T_300; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_271 = _out_wifireMux_T_300; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_301 = ~_out_T_1666; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_303 = _out_wifireMux_T_262 & out_frontSel_10_1; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_304 = _out_wifireMux_T_303 & _out_T_1724; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_483 = _out_wifireMux_T_304; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_484 = _out_wifireMux_T_304; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_485 = _out_wifireMux_T_304; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_486 = _out_wifireMux_T_304; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_305 = ~_out_T_1724; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_307 = _out_wifireMux_T_262 & out_frontSel_11_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_308 = _out_wifireMux_T_307; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_311 = _out_wifireMux_T_262 & out_frontSel_12_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_312 = _out_wifireMux_T_311; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_315 = _out_wifireMux_T_262 & out_frontSel_13_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_316 = _out_wifireMux_T_315; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_319 = _out_wifireMux_T_262 & out_frontSel_14_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_320 = _out_wifireMux_T_319; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_323 = _out_wifireMux_T_262 & out_frontSel_15_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_324 = _out_wifireMux_T_323; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_327 = _out_wifireMux_T_262 & out_frontSel_16_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_328 = _out_wifireMux_T_327; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_331 = _out_wifireMux_T_262 & out_frontSel_17_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_332 = _out_wifireMux_T_331; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_335 = _out_wifireMux_T_262 & out_frontSel_18_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_336 = _out_wifireMux_T_335; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_339 = _out_wifireMux_T_262 & out_frontSel_19_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_340 = _out_wifireMux_T_339; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_343 = _out_wifireMux_T_262 & out_frontSel_20_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_344 = _out_wifireMux_T_343; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_347 = _out_wifireMux_T_262 & out_frontSel_21_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_348 = _out_wifireMux_T_347; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_351 = _out_wifireMux_T_262 & out_frontSel_22_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_352 = _out_wifireMux_T_351; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_355 = _out_wifireMux_T_262 & out_frontSel_23_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_356 = _out_wifireMux_T_355; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_359 = _out_wifireMux_T_262 & out_frontSel_24_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_360 = _out_wifireMux_T_359; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_363 = _out_wifireMux_T_262 & out_frontSel_25_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_364 = _out_wifireMux_T_363; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_367 = _out_wifireMux_T_262 & out_frontSel_26_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_368 = _out_wifireMux_T_367; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_371 = _out_wifireMux_T_262 & out_frontSel_27_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_372 = _out_wifireMux_T_371; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_375 = _out_wifireMux_T_262 & out_frontSel_28_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_376 = _out_wifireMux_T_375; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_379 = _out_wifireMux_T_262 & out_frontSel_29_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_380 = _out_wifireMux_T_379; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_383 = _out_wifireMux_T_262 & out_frontSel_30_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_384 = _out_wifireMux_T_383; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_387 = _out_wifireMux_T_262 & out_frontSel_31_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_388 = _out_wifireMux_T_387; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_391 = _out_wifireMux_T_262 & out_frontSel_32_1; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_392 = _out_wifireMux_T_391 & _out_T_1738; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_535 = _out_wifireMux_T_392; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_536 = _out_wifireMux_T_392; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_393 = ~_out_T_1738; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_395 = _out_wifireMux_T_262 & out_frontSel_33_1; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_396 = _out_wifireMux_T_395 & _out_T_1688; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_352 = _out_wifireMux_T_396; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_353 = _out_wifireMux_T_396; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_397 = ~_out_T_1688; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_399 = _out_wifireMux_T_262 & out_frontSel_34_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_400 = _out_wifireMux_T_399; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_403 = _out_wifireMux_T_262 & out_frontSel_35_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_404 = _out_wifireMux_T_403; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_407 = _out_wifireMux_T_262 & out_frontSel_36_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_408 = _out_wifireMux_T_407; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_411 = _out_wifireMux_T_262 & out_frontSel_37_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_412 = _out_wifireMux_T_411; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_415 = _out_wifireMux_T_262 & out_frontSel_38_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_416 = _out_wifireMux_T_415; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_419 = _out_wifireMux_T_262 & out_frontSel_39_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_420 = _out_wifireMux_T_419; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_423 = _out_wifireMux_T_262 & out_frontSel_40_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_424 = _out_wifireMux_T_423; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_427 = _out_wifireMux_T_262 & out_frontSel_41_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_428 = _out_wifireMux_T_427; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_431 = _out_wifireMux_T_262 & out_frontSel_42_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_432 = _out_wifireMux_T_431; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_435 = _out_wifireMux_T_262 & out_frontSel_43_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_436 = _out_wifireMux_T_435; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_439 = _out_wifireMux_T_262 & out_frontSel_44_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_440 = _out_wifireMux_T_439; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_443 = _out_wifireMux_T_262 & out_frontSel_45_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_444 = _out_wifireMux_T_443; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_447 = _out_wifireMux_T_262 & out_frontSel_46_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_448 = _out_wifireMux_T_447; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_451 = _out_wifireMux_T_262 & out_frontSel_47_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_452 = _out_wifireMux_T_451; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_455 = _out_wifireMux_T_262 & out_frontSel_48_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_456 = _out_wifireMux_T_455; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_459 = _out_wifireMux_T_262 & out_frontSel_49_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_460 = _out_wifireMux_T_459; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_463 = _out_wifireMux_T_262 & out_frontSel_50_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_464 = _out_wifireMux_T_463; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_467 = _out_wifireMux_T_262 & out_frontSel_51_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_468 = _out_wifireMux_T_467; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_471 = _out_wifireMux_T_262 & out_frontSel_52_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_472 = _out_wifireMux_T_471; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_475 = _out_wifireMux_T_262 & out_frontSel_53_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_476 = _out_wifireMux_T_475; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_479 = _out_wifireMux_T_262 & out_frontSel_54_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_480 = _out_wifireMux_T_479; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_483 = _out_wifireMux_T_262 & out_frontSel_55_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_484 = _out_wifireMux_T_483; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_487 = _out_wifireMux_T_262 & out_frontSel_56_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_488 = _out_wifireMux_T_487; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_491 = _out_wifireMux_T_262 & out_frontSel_57_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_492 = _out_wifireMux_T_491; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_495 = _out_wifireMux_T_262 & out_frontSel_58_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_496 = _out_wifireMux_T_495; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_499 = _out_wifireMux_T_262 & out_frontSel_59_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_500 = _out_wifireMux_T_499; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_503 = _out_wifireMux_T_262 & out_frontSel_60_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_504 = _out_wifireMux_T_503; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_507 = _out_wifireMux_T_262 & out_frontSel_61_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_508 = _out_wifireMux_T_507; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_511 = _out_wifireMux_T_262 & out_frontSel_62_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_512 = _out_wifireMux_T_511; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_515 = _out_wifireMux_T_262 & out_frontSel_63_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_516 = _out_wifireMux_T_515; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_519 = _out_wifireMux_T_262 & out_frontSel_64; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_520 = _out_wifireMux_T_519; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_523 = _out_wifireMux_T_262 & out_frontSel_65; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_524 = _out_wifireMux_T_523; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_527 = _out_wifireMux_T_262 & out_frontSel_66; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_528 = _out_wifireMux_T_527; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_531 = _out_wifireMux_T_262 & out_frontSel_67; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_532 = _out_wifireMux_T_531; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_535 = _out_wifireMux_T_262 & out_frontSel_68; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_536 = _out_wifireMux_T_535; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_539 = _out_wifireMux_T_262 & out_frontSel_69; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_540 = _out_wifireMux_T_539; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_543 = _out_wifireMux_T_262 & out_frontSel_70; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_544 = _out_wifireMux_T_543; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_547 = _out_wifireMux_T_262 & out_frontSel_71; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_548 = _out_wifireMux_T_547; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_551 = _out_wifireMux_T_262 & out_frontSel_72; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_552 = _out_wifireMux_T_551; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_555 = _out_wifireMux_T_262 & out_frontSel_73; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_556 = _out_wifireMux_T_555; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_559 = _out_wifireMux_T_262 & out_frontSel_74; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_560 = _out_wifireMux_T_559; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_563 = _out_wifireMux_T_262 & out_frontSel_75; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_564 = _out_wifireMux_T_563; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_567 = _out_wifireMux_T_262 & out_frontSel_76; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_568 = _out_wifireMux_T_567; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_571 = _out_wifireMux_T_262 & out_frontSel_77; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_572 = _out_wifireMux_T_571; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_575 = _out_wifireMux_T_262 & out_frontSel_78; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_576 = _out_wifireMux_T_575; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_579 = _out_wifireMux_T_262 & out_frontSel_79; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_580 = _out_wifireMux_T_579; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_583 = _out_wifireMux_T_262 & out_frontSel_80; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_584 = _out_wifireMux_T_583; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_587 = _out_wifireMux_T_262 & out_frontSel_81; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_588 = _out_wifireMux_T_587; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_591 = _out_wifireMux_T_262 & out_frontSel_82; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_592 = _out_wifireMux_T_591; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_595 = _out_wifireMux_T_262 & out_frontSel_83; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_596 = _out_wifireMux_T_595; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_599 = _out_wifireMux_T_262 & out_frontSel_84; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_600 = _out_wifireMux_T_599; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_603 = _out_wifireMux_T_262 & out_frontSel_85; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_604 = _out_wifireMux_T_603; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_607 = _out_wifireMux_T_262 & out_frontSel_86; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_608 = _out_wifireMux_T_607; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_611 = _out_wifireMux_T_262 & out_frontSel_87; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_612 = _out_wifireMux_T_611; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_615 = _out_wifireMux_T_262 & out_frontSel_88; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_616 = _out_wifireMux_T_615; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_619 = _out_wifireMux_T_262 & out_frontSel_89; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_620 = _out_wifireMux_T_619; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_623 = _out_wifireMux_T_262 & out_frontSel_90; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_624 = _out_wifireMux_T_623; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_627 = _out_wifireMux_T_262 & out_frontSel_91; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_628 = _out_wifireMux_T_627; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_631 = _out_wifireMux_T_262 & out_frontSel_92; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_632 = _out_wifireMux_T_631; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_635 = _out_wifireMux_T_262 & out_frontSel_93; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_636 = _out_wifireMux_T_635; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_639 = _out_wifireMux_T_262 & out_frontSel_94; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_640 = _out_wifireMux_T_639; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_643 = _out_wifireMux_T_262 & out_frontSel_95; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_644 = _out_wifireMux_T_643; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_647 = _out_wifireMux_T_262 & out_frontSel_96; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_648 = _out_wifireMux_T_647 & _out_T_1712; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_442 = _out_wifireMux_T_648; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_649 = ~_out_T_1712; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_651 = _out_wifireMux_T_262 & out_frontSel_97; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_652 = _out_wifireMux_T_651; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_655 = _out_wifireMux_T_262 & out_frontSel_98; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_656 = _out_wifireMux_T_655; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_659 = _out_wifireMux_T_262 & out_frontSel_99; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_660 = _out_wifireMux_T_659; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_663 = _out_wifireMux_T_262 & out_frontSel_100; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_664 = _out_wifireMux_T_663; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_667 = _out_wifireMux_T_262 & out_frontSel_101; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_668 = _out_wifireMux_T_667; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_671 = _out_wifireMux_T_262 & out_frontSel_102; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_672 = _out_wifireMux_T_671; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_675 = _out_wifireMux_T_262 & out_frontSel_103; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_676 = _out_wifireMux_T_675 & _out_T_1780; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_697 = _out_wifireMux_T_676; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_698 = _out_wifireMux_T_676; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_677 = ~_out_T_1780; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_679 = _out_wifireMux_T_262 & out_frontSel_104; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_680 = _out_wifireMux_T_679 & _out_T_1840; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_931 = _out_wifireMux_T_680; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_932 = _out_wifireMux_T_680; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_933 = _out_wifireMux_T_680; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_934 = _out_wifireMux_T_680; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_935 = _out_wifireMux_T_680; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_936 = _out_wifireMux_T_680; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_937 = _out_wifireMux_T_680; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_938 = _out_wifireMux_T_680; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_681 = ~_out_T_1840; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_683 = _out_wifireMux_T_262 & out_frontSel_105; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_684 = _out_wifireMux_T_683 & _out_T_1732; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_511 = _out_wifireMux_T_684; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_512 = _out_wifireMux_T_684; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_513 = _out_wifireMux_T_684; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_514 = _out_wifireMux_T_684; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_515 = _out_wifireMux_T_684; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_516 = _out_wifireMux_T_684; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_517 = _out_wifireMux_T_684; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_518 = _out_wifireMux_T_684; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_685 = ~_out_T_1732; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_687 = _out_wifireMux_T_262 & out_frontSel_106; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_688 = _out_wifireMux_T_687 & _out_T_1648; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_192 = _out_wifireMux_T_688; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_193 = _out_wifireMux_T_688; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_194 = _out_wifireMux_T_688; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_195 = _out_wifireMux_T_688; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_196 = _out_wifireMux_T_688; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_197 = _out_wifireMux_T_688; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_198 = _out_wifireMux_T_688; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_199 = _out_wifireMux_T_688; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_689 = ~_out_T_1648; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_691 = _out_wifireMux_T_262 & out_frontSel_107; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_692 = _out_wifireMux_T_691 & _out_T_1880; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1091 = _out_wifireMux_T_692; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1092 = _out_wifireMux_T_692; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1093 = _out_wifireMux_T_692; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1094 = _out_wifireMux_T_692; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1095 = _out_wifireMux_T_692; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1096 = _out_wifireMux_T_692; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1097 = _out_wifireMux_T_692; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1098 = _out_wifireMux_T_692; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_693 = ~_out_T_1880; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_695 = _out_wifireMux_T_262 & out_frontSel_108; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_696 = _out_wifireMux_T_695 & _out_T_1790; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_731 = _out_wifireMux_T_696; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_732 = _out_wifireMux_T_696; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_733 = _out_wifireMux_T_696; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_734 = _out_wifireMux_T_696; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_735 = _out_wifireMux_T_696; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_736 = _out_wifireMux_T_696; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_737 = _out_wifireMux_T_696; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_738 = _out_wifireMux_T_696; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_697 = ~_out_T_1790; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_699 = _out_wifireMux_T_262 & out_frontSel_109; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_700 = _out_wifireMux_T_699 & _out_T_1714; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_443 = _out_wifireMux_T_700; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_444 = _out_wifireMux_T_700; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_445 = _out_wifireMux_T_700; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_446 = _out_wifireMux_T_700; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_447 = _out_wifireMux_T_700; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_448 = _out_wifireMux_T_700; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_449 = _out_wifireMux_T_700; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_450 = _out_wifireMux_T_700; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_701 = ~_out_T_1714; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_703 = _out_wifireMux_T_262 & out_frontSel_110; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_704 = _out_wifireMux_T_703 & _out_T_1628; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_112 = _out_wifireMux_T_704; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_113 = _out_wifireMux_T_704; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_114 = _out_wifireMux_T_704; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_115 = _out_wifireMux_T_704; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_116 = _out_wifireMux_T_704; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_117 = _out_wifireMux_T_704; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_118 = _out_wifireMux_T_704; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_119 = _out_wifireMux_T_704; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_705 = ~_out_T_1628; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_707 = _out_wifireMux_T_262 & out_frontSel_111; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_708 = _out_wifireMux_T_707 & _out_T_1898; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1163 = _out_wifireMux_T_708; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1164 = _out_wifireMux_T_708; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1165 = _out_wifireMux_T_708; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1166 = _out_wifireMux_T_708; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1167 = _out_wifireMux_T_708; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1168 = _out_wifireMux_T_708; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1169 = _out_wifireMux_T_708; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1170 = _out_wifireMux_T_708; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_709 = ~_out_T_1898; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_711 = _out_wifireMux_T_262 & out_frontSel_112; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_712 = _out_wifireMux_T_711 & _out_T_1814; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_827 = _out_wifireMux_T_712; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_828 = _out_wifireMux_T_712; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_829 = _out_wifireMux_T_712; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_830 = _out_wifireMux_T_712; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_831 = _out_wifireMux_T_712; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_832 = _out_wifireMux_T_712; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_833 = _out_wifireMux_T_712; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_834 = _out_wifireMux_T_712; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_713 = ~_out_T_1814; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_715 = _out_wifireMux_T_262 & out_frontSel_113; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_716 = _out_wifireMux_T_715 & _out_T_1770; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_657 = _out_wifireMux_T_716; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_658 = _out_wifireMux_T_716; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_659 = _out_wifireMux_T_716; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_660 = _out_wifireMux_T_716; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_661 = _out_wifireMux_T_716; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_662 = _out_wifireMux_T_716; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_663 = _out_wifireMux_T_716; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_664 = _out_wifireMux_T_716; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_717 = ~_out_T_1770; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_719 = _out_wifireMux_T_262 & out_frontSel_114; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_720 = _out_wifireMux_T_719 & _out_T_1852; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_979 = _out_wifireMux_T_720; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_980 = _out_wifireMux_T_720; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_981 = _out_wifireMux_T_720; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_982 = _out_wifireMux_T_720; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_983 = _out_wifireMux_T_720; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_984 = _out_wifireMux_T_720; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_985 = _out_wifireMux_T_720; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_986 = _out_wifireMux_T_720; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_721 = ~_out_T_1852; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_723 = _out_wifireMux_T_262 & out_frontSel_115; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_724 = _out_wifireMux_T_723 & _out_T_1608; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_32 = _out_wifireMux_T_724; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_33 = _out_wifireMux_T_724; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_34 = _out_wifireMux_T_724; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_35 = _out_wifireMux_T_724; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_36 = _out_wifireMux_T_724; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_37 = _out_wifireMux_T_724; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_38 = _out_wifireMux_T_724; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_39 = _out_wifireMux_T_724; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_725 = ~_out_T_1608; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_727 = _out_wifireMux_T_262 & out_frontSel_116; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_728 = _out_wifireMux_T_727; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_731 = _out_wifireMux_T_262 & out_frontSel_117; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_732 = _out_wifireMux_T_731; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_735 = _out_wifireMux_T_262 & out_frontSel_118; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_736 = _out_wifireMux_T_735; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_739 = _out_wifireMux_T_262 & out_frontSel_119; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_740 = _out_wifireMux_T_739; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_743 = _out_wifireMux_T_262 & out_frontSel_120; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_744 = _out_wifireMux_T_743; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_747 = _out_wifireMux_T_262 & out_frontSel_121; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_748 = _out_wifireMux_T_747; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_751 = _out_wifireMux_T_262 & out_frontSel_122; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_752 = _out_wifireMux_T_751; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_755 = _out_wifireMux_T_262 & out_frontSel_123; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_756 = _out_wifireMux_T_755; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_759 = _out_wifireMux_T_262 & out_frontSel_124; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_760 = _out_wifireMux_T_759; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_763 = _out_wifireMux_T_262 & out_frontSel_125; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_764 = _out_wifireMux_T_763; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_767 = _out_wifireMux_T_262 & out_frontSel_126; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_768 = _out_wifireMux_T_767; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_771 = _out_wifireMux_T_262 & out_frontSel_127; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_772 = _out_wifireMux_T_771; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_775 = _out_wifireMux_T_262 & out_frontSel_128; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_776 = _out_wifireMux_T_775 & _out_T_1728; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_495 = _out_wifireMux_T_776; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_496 = _out_wifireMux_T_776; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_497 = _out_wifireMux_T_776; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_498 = _out_wifireMux_T_776; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_499 = _out_wifireMux_T_776; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_500 = _out_wifireMux_T_776; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_501 = _out_wifireMux_T_776; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_502 = _out_wifireMux_T_776; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_777 = ~_out_T_1728; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_779 = _out_wifireMux_T_262 & out_frontSel_129; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_780 = _out_wifireMux_T_779 & _out_T_1720; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_467 = _out_wifireMux_T_780; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_468 = _out_wifireMux_T_780; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_469 = _out_wifireMux_T_780; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_470 = _out_wifireMux_T_780; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_471 = _out_wifireMux_T_780; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_472 = _out_wifireMux_T_780; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_473 = _out_wifireMux_T_780; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_474 = _out_wifireMux_T_780; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_781 = ~_out_T_1720; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_783 = _out_wifireMux_T_262 & out_frontSel_130; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_784 = _out_wifireMux_T_783 & _out_T_1796; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_755 = _out_wifireMux_T_784; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_756 = _out_wifireMux_T_784; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_757 = _out_wifireMux_T_784; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_758 = _out_wifireMux_T_784; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_759 = _out_wifireMux_T_784; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_760 = _out_wifireMux_T_784; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_761 = _out_wifireMux_T_784; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_762 = _out_wifireMux_T_784; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_785 = ~_out_T_1796; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_787 = _out_wifireMux_T_262 & out_frontSel_131; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_788 = _out_wifireMux_T_787 & _out_T_1890; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1131 = _out_wifireMux_T_788; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1132 = _out_wifireMux_T_788; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1133 = _out_wifireMux_T_788; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1134 = _out_wifireMux_T_788; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1135 = _out_wifireMux_T_788; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1136 = _out_wifireMux_T_788; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1137 = _out_wifireMux_T_788; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1138 = _out_wifireMux_T_788; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_789 = ~_out_T_1890; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_791 = _out_wifireMux_T_262 & out_frontSel_132; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_792 = _out_wifireMux_T_791 & _out_T_1660; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_240 = _out_wifireMux_T_792; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_241 = _out_wifireMux_T_792; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_242 = _out_wifireMux_T_792; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_243 = _out_wifireMux_T_792; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_244 = _out_wifireMux_T_792; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_245 = _out_wifireMux_T_792; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_246 = _out_wifireMux_T_792; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_247 = _out_wifireMux_T_792; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_793 = ~_out_T_1660; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_795 = _out_wifireMux_T_262 & out_frontSel_133; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_796 = _out_wifireMux_T_795 & _out_T_1662; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_248 = _out_wifireMux_T_796; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_249 = _out_wifireMux_T_796; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_250 = _out_wifireMux_T_796; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_251 = _out_wifireMux_T_796; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_252 = _out_wifireMux_T_796; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_253 = _out_wifireMux_T_796; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_254 = _out_wifireMux_T_796; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_255 = _out_wifireMux_T_796; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_797 = ~_out_T_1662; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_799 = _out_wifireMux_T_262 & out_frontSel_134; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_800 = _out_wifireMux_T_799 & _out_T_1722; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_475 = _out_wifireMux_T_800; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_476 = _out_wifireMux_T_800; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_477 = _out_wifireMux_T_800; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_478 = _out_wifireMux_T_800; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_479 = _out_wifireMux_T_800; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_480 = _out_wifireMux_T_800; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_481 = _out_wifireMux_T_800; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_482 = _out_wifireMux_T_800; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_801 = ~_out_T_1722; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_803 = _out_wifireMux_T_262 & out_frontSel_135; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_804 = _out_wifireMux_T_803 & _out_T_1800; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_771 = _out_wifireMux_T_804; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_772 = _out_wifireMux_T_804; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_773 = _out_wifireMux_T_804; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_774 = _out_wifireMux_T_804; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_775 = _out_wifireMux_T_804; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_776 = _out_wifireMux_T_804; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_777 = _out_wifireMux_T_804; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_778 = _out_wifireMux_T_804; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_805 = ~_out_T_1800; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_807 = _out_wifireMux_T_262 & out_frontSel_136; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_808 = _out_wifireMux_T_807 & _out_T_1882; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1099 = _out_wifireMux_T_808; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1100 = _out_wifireMux_T_808; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1101 = _out_wifireMux_T_808; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1102 = _out_wifireMux_T_808; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1103 = _out_wifireMux_T_808; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1104 = _out_wifireMux_T_808; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1105 = _out_wifireMux_T_808; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1106 = _out_wifireMux_T_808; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_809 = ~_out_T_1882; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_811 = _out_wifireMux_T_262 & out_frontSel_137; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_812 = _out_wifireMux_T_811 & _out_T_1684; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_336 = _out_wifireMux_T_812; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_337 = _out_wifireMux_T_812; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_338 = _out_wifireMux_T_812; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_339 = _out_wifireMux_T_812; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_340 = _out_wifireMux_T_812; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_341 = _out_wifireMux_T_812; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_342 = _out_wifireMux_T_812; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_343 = _out_wifireMux_T_812; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_813 = ~_out_T_1684; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_815 = _out_wifireMux_T_262 & out_frontSel_138; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_816 = _out_wifireMux_T_815 & _out_T_1600; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_0 = _out_wifireMux_T_816; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1 = _out_wifireMux_T_816; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_2 = _out_wifireMux_T_816; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_3 = _out_wifireMux_T_816; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_4 = _out_wifireMux_T_816; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_5 = _out_wifireMux_T_816; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_6 = _out_wifireMux_T_816; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_7 = _out_wifireMux_T_816; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_817 = ~_out_T_1600; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_819 = _out_wifireMux_T_262 & out_frontSel_139; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_820 = _out_wifireMux_T_819 & _out_T_1856; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_995 = _out_wifireMux_T_820; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_996 = _out_wifireMux_T_820; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_997 = _out_wifireMux_T_820; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_998 = _out_wifireMux_T_820; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_999 = _out_wifireMux_T_820; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1000 = _out_wifireMux_T_820; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1001 = _out_wifireMux_T_820; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1002 = _out_wifireMux_T_820; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_821 = ~_out_T_1856; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_823 = _out_wifireMux_T_262 & out_frontSel_140; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_824 = _out_wifireMux_T_823 & _out_T_1782; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_699 = _out_wifireMux_T_824; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_700 = _out_wifireMux_T_824; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_701 = _out_wifireMux_T_824; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_702 = _out_wifireMux_T_824; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_703 = _out_wifireMux_T_824; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_704 = _out_wifireMux_T_824; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_705 = _out_wifireMux_T_824; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_706 = _out_wifireMux_T_824; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_825 = ~_out_T_1782; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_827 = _out_wifireMux_T_262 & out_frontSel_141; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_828 = _out_wifireMux_T_827 & _out_T_1704; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_410 = _out_wifireMux_T_828; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_411 = _out_wifireMux_T_828; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_412 = _out_wifireMux_T_828; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_413 = _out_wifireMux_T_828; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_414 = _out_wifireMux_T_828; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_415 = _out_wifireMux_T_828; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_416 = _out_wifireMux_T_828; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_417 = _out_wifireMux_T_828; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_829 = ~_out_T_1704; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_831 = _out_wifireMux_T_262 & out_frontSel_142; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_832 = _out_wifireMux_T_831 & _out_T_1616; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_64 = _out_wifireMux_T_832; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_65 = _out_wifireMux_T_832; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_66 = _out_wifireMux_T_832; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_67 = _out_wifireMux_T_832; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_68 = _out_wifireMux_T_832; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_69 = _out_wifireMux_T_832; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_70 = _out_wifireMux_T_832; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_71 = _out_wifireMux_T_832; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_833 = ~_out_T_1616; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_835 = _out_wifireMux_T_262 & out_frontSel_143; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_836 = _out_wifireMux_T_835 & _out_T_1834; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_907 = _out_wifireMux_T_836; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_908 = _out_wifireMux_T_836; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_909 = _out_wifireMux_T_836; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_910 = _out_wifireMux_T_836; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_911 = _out_wifireMux_T_836; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_912 = _out_wifireMux_T_836; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_913 = _out_wifireMux_T_836; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_914 = _out_wifireMux_T_836; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_837 = ~_out_T_1834; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_839 = _out_wifireMux_T_262 & out_frontSel_144; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_840 = _out_wifireMux_T_839 & _out_T_1758; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_609 = _out_wifireMux_T_840; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_610 = _out_wifireMux_T_840; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_611 = _out_wifireMux_T_840; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_612 = _out_wifireMux_T_840; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_613 = _out_wifireMux_T_840; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_614 = _out_wifireMux_T_840; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_615 = _out_wifireMux_T_840; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_616 = _out_wifireMux_T_840; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_841 = ~_out_T_1758; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_843 = _out_wifireMux_T_262 & out_frontSel_145; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_844 = _out_wifireMux_T_843 & _out_T_1818; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_843 = _out_wifireMux_T_844; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_844 = _out_wifireMux_T_844; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_845 = _out_wifireMux_T_844; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_846 = _out_wifireMux_T_844; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_847 = _out_wifireMux_T_844; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_848 = _out_wifireMux_T_844; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_849 = _out_wifireMux_T_844; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_850 = _out_wifireMux_T_844; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_845 = ~_out_T_1818; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_847 = _out_wifireMux_T_262 & out_frontSel_146; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_848 = _out_wifireMux_T_847 & _out_T_1868; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1043 = _out_wifireMux_T_848; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1044 = _out_wifireMux_T_848; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1045 = _out_wifireMux_T_848; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1046 = _out_wifireMux_T_848; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1047 = _out_wifireMux_T_848; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1048 = _out_wifireMux_T_848; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1049 = _out_wifireMux_T_848; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1050 = _out_wifireMux_T_848; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_849 = ~_out_T_1868; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_851 = _out_wifireMux_T_262 & out_frontSel_147; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_852 = _out_wifireMux_T_851 & _out_T_1656; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_224 = _out_wifireMux_T_852; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_225 = _out_wifireMux_T_852; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_226 = _out_wifireMux_T_852; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_227 = _out_wifireMux_T_852; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_228 = _out_wifireMux_T_852; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_229 = _out_wifireMux_T_852; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_230 = _out_wifireMux_T_852; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_231 = _out_wifireMux_T_852; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_853 = ~_out_T_1656; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_855 = _out_wifireMux_T_262 & out_frontSel_148; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_856 = _out_wifireMux_T_855 & _out_T_1740; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_537 = _out_wifireMux_T_856; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_538 = _out_wifireMux_T_856; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_539 = _out_wifireMux_T_856; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_540 = _out_wifireMux_T_856; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_541 = _out_wifireMux_T_856; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_542 = _out_wifireMux_T_856; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_543 = _out_wifireMux_T_856; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_544 = _out_wifireMux_T_856; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_857 = ~_out_T_1740; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_859 = _out_wifireMux_T_262 & out_frontSel_149; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_860 = _out_wifireMux_T_859 & _out_T_1748; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_569 = _out_wifireMux_T_860; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_570 = _out_wifireMux_T_860; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_571 = _out_wifireMux_T_860; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_572 = _out_wifireMux_T_860; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_573 = _out_wifireMux_T_860; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_574 = _out_wifireMux_T_860; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_575 = _out_wifireMux_T_860; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_576 = _out_wifireMux_T_860; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_861 = ~_out_T_1748; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_863 = _out_wifireMux_T_262 & out_frontSel_150; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_864 = _out_wifireMux_T_863 & _out_T_1820; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_851 = _out_wifireMux_T_864; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_852 = _out_wifireMux_T_864; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_853 = _out_wifireMux_T_864; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_854 = _out_wifireMux_T_864; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_855 = _out_wifireMux_T_864; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_856 = _out_wifireMux_T_864; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_857 = _out_wifireMux_T_864; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_858 = _out_wifireMux_T_864; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_865 = ~_out_T_1820; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_867 = _out_wifireMux_T_262 & out_frontSel_151; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_868 = _out_wifireMux_T_867 & _out_T_1866; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1035 = _out_wifireMux_T_868; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1036 = _out_wifireMux_T_868; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1037 = _out_wifireMux_T_868; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1038 = _out_wifireMux_T_868; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1039 = _out_wifireMux_T_868; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1040 = _out_wifireMux_T_868; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1041 = _out_wifireMux_T_868; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1042 = _out_wifireMux_T_868; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_869 = ~_out_T_1866; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_871 = _out_wifireMux_T_262 & out_frontSel_152; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_872 = _out_wifireMux_T_871 & _out_T_1636; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_144 = _out_wifireMux_T_872; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_145 = _out_wifireMux_T_872; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_146 = _out_wifireMux_T_872; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_147 = _out_wifireMux_T_872; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_148 = _out_wifireMux_T_872; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_149 = _out_wifireMux_T_872; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_150 = _out_wifireMux_T_872; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_151 = _out_wifireMux_T_872; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_873 = ~_out_T_1636; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_875 = _out_wifireMux_T_262 & out_frontSel_153; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_876 = _out_wifireMux_T_875 & _out_T_1618; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_72 = _out_wifireMux_T_876; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_73 = _out_wifireMux_T_876; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_74 = _out_wifireMux_T_876; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_75 = _out_wifireMux_T_876; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_76 = _out_wifireMux_T_876; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_77 = _out_wifireMux_T_876; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_78 = _out_wifireMux_T_876; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_79 = _out_wifireMux_T_876; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_877 = ~_out_T_1618; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_879 = _out_wifireMux_T_262 & out_frontSel_154; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_880 = _out_wifireMux_T_879 & _out_T_1830; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_891 = _out_wifireMux_T_880; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_892 = _out_wifireMux_T_880; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_893 = _out_wifireMux_T_880; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_894 = _out_wifireMux_T_880; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_895 = _out_wifireMux_T_880; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_896 = _out_wifireMux_T_880; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_897 = _out_wifireMux_T_880; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_898 = _out_wifireMux_T_880; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_881 = ~_out_T_1830; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_883 = _out_wifireMux_T_262 & out_frontSel_155; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_884 = _out_wifireMux_T_883 & _out_T_1786; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_715 = _out_wifireMux_T_884; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_716 = _out_wifireMux_T_884; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_717 = _out_wifireMux_T_884; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_718 = _out_wifireMux_T_884; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_719 = _out_wifireMux_T_884; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_720 = _out_wifireMux_T_884; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_721 = _out_wifireMux_T_884; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_722 = _out_wifireMux_T_884; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_885 = ~_out_T_1786; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_887 = _out_wifireMux_T_262 & out_frontSel_156; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_888 = _out_wifireMux_T_887 & _out_T_1698; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_386 = _out_wifireMux_T_888; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_387 = _out_wifireMux_T_888; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_388 = _out_wifireMux_T_888; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_389 = _out_wifireMux_T_888; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_390 = _out_wifireMux_T_888; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_391 = _out_wifireMux_T_888; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_392 = _out_wifireMux_T_888; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_393 = _out_wifireMux_T_888; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_889 = ~_out_T_1698; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_891 = _out_wifireMux_T_262 & out_frontSel_157; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_892 = _out_wifireMux_T_891 & _out_T_1632; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_128 = _out_wifireMux_T_892; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_129 = _out_wifireMux_T_892; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_130 = _out_wifireMux_T_892; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_131 = _out_wifireMux_T_892; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_132 = _out_wifireMux_T_892; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_133 = _out_wifireMux_T_892; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_134 = _out_wifireMux_T_892; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_135 = _out_wifireMux_T_892; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_893 = ~_out_T_1632; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_895 = _out_wifireMux_T_262 & out_frontSel_158; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_896 = _out_wifireMux_T_895 & _out_T_1848; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_963 = _out_wifireMux_T_896; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_964 = _out_wifireMux_T_896; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_965 = _out_wifireMux_T_896; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_966 = _out_wifireMux_T_896; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_967 = _out_wifireMux_T_896; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_968 = _out_wifireMux_T_896; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_969 = _out_wifireMux_T_896; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_970 = _out_wifireMux_T_896; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_897 = ~_out_T_1848; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_899 = _out_wifireMux_T_262 & out_frontSel_159; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_900 = _out_wifireMux_T_899 & _out_T_1764; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_633 = _out_wifireMux_T_900; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_634 = _out_wifireMux_T_900; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_635 = _out_wifireMux_T_900; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_636 = _out_wifireMux_T_900; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_637 = _out_wifireMux_T_900; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_638 = _out_wifireMux_T_900; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_639 = _out_wifireMux_T_900; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_640 = _out_wifireMux_T_900; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_901 = ~_out_T_1764; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_903 = _out_wifireMux_T_262 & out_frontSel_160; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_904 = _out_wifireMux_T_903 & _out_T_1680; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_320 = _out_wifireMux_T_904; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_321 = _out_wifireMux_T_904; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_322 = _out_wifireMux_T_904; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_323 = _out_wifireMux_T_904; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_324 = _out_wifireMux_T_904; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_325 = _out_wifireMux_T_904; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_326 = _out_wifireMux_T_904; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_327 = _out_wifireMux_T_904; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_905 = ~_out_T_1680; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_907 = _out_wifireMux_T_262 & out_frontSel_161; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_908 = _out_wifireMux_T_907 & _out_T_1744; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_553 = _out_wifireMux_T_908; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_554 = _out_wifireMux_T_908; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_555 = _out_wifireMux_T_908; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_556 = _out_wifireMux_T_908; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_557 = _out_wifireMux_T_908; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_558 = _out_wifireMux_T_908; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_559 = _out_wifireMux_T_908; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_560 = _out_wifireMux_T_908; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_909 = ~_out_T_1744; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_911 = _out_wifireMux_T_262 & out_frontSel_162; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_912 = _out_wifireMux_T_911 & _out_T_1808; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_803 = _out_wifireMux_T_912; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_804 = _out_wifireMux_T_912; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_805 = _out_wifireMux_T_912; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_806 = _out_wifireMux_T_912; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_807 = _out_wifireMux_T_912; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_808 = _out_wifireMux_T_912; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_809 = _out_wifireMux_T_912; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_810 = _out_wifireMux_T_912; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_913 = ~_out_T_1808; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_915 = _out_wifireMux_T_262 & out_frontSel_163; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_916 = _out_wifireMux_T_915 & _out_T_1894; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1147 = _out_wifireMux_T_916; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1148 = _out_wifireMux_T_916; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1149 = _out_wifireMux_T_916; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1150 = _out_wifireMux_T_916; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1151 = _out_wifireMux_T_916; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1152 = _out_wifireMux_T_916; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1153 = _out_wifireMux_T_916; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1154 = _out_wifireMux_T_916; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_917 = ~_out_T_1894; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_919 = _out_wifireMux_T_262 & out_frontSel_164; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_920 = _out_wifireMux_T_919 & _out_T_1644; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_176 = _out_wifireMux_T_920; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_177 = _out_wifireMux_T_920; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_178 = _out_wifireMux_T_920; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_179 = _out_wifireMux_T_920; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_180 = _out_wifireMux_T_920; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_181 = _out_wifireMux_T_920; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_182 = _out_wifireMux_T_920; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_183 = _out_wifireMux_T_920; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_921 = ~_out_T_1644; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_923 = _out_wifireMux_T_262 & out_frontSel_165; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_924 = _out_wifireMux_T_923 & _out_T_1686; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_344 = _out_wifireMux_T_924; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_345 = _out_wifireMux_T_924; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_346 = _out_wifireMux_T_924; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_347 = _out_wifireMux_T_924; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_348 = _out_wifireMux_T_924; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_349 = _out_wifireMux_T_924; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_350 = _out_wifireMux_T_924; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_351 = _out_wifireMux_T_924; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_925 = ~_out_T_1686; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_927 = _out_wifireMux_T_262 & out_frontSel_166; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_928 = _out_wifireMux_T_927 & _out_T_1736; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_527 = _out_wifireMux_T_928; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_528 = _out_wifireMux_T_928; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_529 = _out_wifireMux_T_928; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_530 = _out_wifireMux_T_928; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_531 = _out_wifireMux_T_928; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_532 = _out_wifireMux_T_928; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_533 = _out_wifireMux_T_928; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_534 = _out_wifireMux_T_928; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_929 = ~_out_T_1736; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_931 = _out_wifireMux_T_262 & out_frontSel_167; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_932 = _out_wifireMux_T_931 & _out_T_1806; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_795 = _out_wifireMux_T_932; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_796 = _out_wifireMux_T_932; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_797 = _out_wifireMux_T_932; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_798 = _out_wifireMux_T_932; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_799 = _out_wifireMux_T_932; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_800 = _out_wifireMux_T_932; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_801 = _out_wifireMux_T_932; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_802 = _out_wifireMux_T_932; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_933 = ~_out_T_1806; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_935 = _out_wifireMux_T_262 & out_frontSel_168; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_936 = _out_wifireMux_T_935 & _out_T_1874; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1067 = _out_wifireMux_T_936; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1068 = _out_wifireMux_T_936; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1069 = _out_wifireMux_T_936; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1070 = _out_wifireMux_T_936; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1071 = _out_wifireMux_T_936; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1072 = _out_wifireMux_T_936; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1073 = _out_wifireMux_T_936; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1074 = _out_wifireMux_T_936; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_937 = ~_out_T_1874; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_939 = _out_wifireMux_T_262 & out_frontSel_169; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_940 = _out_wifireMux_T_939 & _out_T_1702; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_402 = _out_wifireMux_T_940; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_403 = _out_wifireMux_T_940; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_404 = _out_wifireMux_T_940; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_405 = _out_wifireMux_T_940; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_406 = _out_wifireMux_T_940; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_407 = _out_wifireMux_T_940; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_408 = _out_wifireMux_T_940; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_409 = _out_wifireMux_T_940; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_941 = ~_out_T_1702; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_943 = _out_wifireMux_T_262 & out_frontSel_170; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_944 = _out_wifireMux_T_943 & _out_T_1606; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_24 = _out_wifireMux_T_944; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_25 = _out_wifireMux_T_944; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_26 = _out_wifireMux_T_944; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_27 = _out_wifireMux_T_944; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_28 = _out_wifireMux_T_944; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_29 = _out_wifireMux_T_944; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_30 = _out_wifireMux_T_944; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_31 = _out_wifireMux_T_944; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_945 = ~_out_T_1606; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_947 = _out_wifireMux_T_262 & out_frontSel_171; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_948 = _out_wifireMux_T_947 & _out_T_1854; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_987 = _out_wifireMux_T_948; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_988 = _out_wifireMux_T_948; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_989 = _out_wifireMux_T_948; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_990 = _out_wifireMux_T_948; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_991 = _out_wifireMux_T_948; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_992 = _out_wifireMux_T_948; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_993 = _out_wifireMux_T_948; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_994 = _out_wifireMux_T_948; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_949 = ~_out_T_1854; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_951 = _out_wifireMux_T_262 & out_frontSel_172; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_952 = _out_wifireMux_T_951 & _out_T_1768; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_649 = _out_wifireMux_T_952; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_650 = _out_wifireMux_T_952; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_651 = _out_wifireMux_T_952; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_652 = _out_wifireMux_T_952; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_653 = _out_wifireMux_T_952; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_654 = _out_wifireMux_T_952; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_655 = _out_wifireMux_T_952; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_656 = _out_wifireMux_T_952; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_953 = ~_out_T_1768; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_955 = _out_wifireMux_T_262 & out_frontSel_173; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_956 = _out_wifireMux_T_955 & _out_T_1718; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_459 = _out_wifireMux_T_956; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_460 = _out_wifireMux_T_956; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_461 = _out_wifireMux_T_956; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_462 = _out_wifireMux_T_956; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_463 = _out_wifireMux_T_956; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_464 = _out_wifireMux_T_956; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_465 = _out_wifireMux_T_956; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_466 = _out_wifireMux_T_956; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_957 = ~_out_T_1718; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_959 = _out_wifireMux_T_262 & out_frontSel_174; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_960 = _out_wifireMux_T_959 & _out_T_1620; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_80 = _out_wifireMux_T_960; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_81 = _out_wifireMux_T_960; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_82 = _out_wifireMux_T_960; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_83 = _out_wifireMux_T_960; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_84 = _out_wifireMux_T_960; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_85 = _out_wifireMux_T_960; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_86 = _out_wifireMux_T_960; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_87 = _out_wifireMux_T_960; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_961 = ~_out_T_1620; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_963 = _out_wifireMux_T_262 & out_frontSel_175; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_964 = _out_wifireMux_T_963 & _out_T_1832; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_899 = _out_wifireMux_T_964; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_900 = _out_wifireMux_T_964; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_901 = _out_wifireMux_T_964; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_902 = _out_wifireMux_T_964; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_903 = _out_wifireMux_T_964; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_904 = _out_wifireMux_T_964; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_905 = _out_wifireMux_T_964; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_906 = _out_wifireMux_T_964; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_965 = ~_out_T_1832; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_967 = _out_wifireMux_T_262 & out_frontSel_176; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_968 = _out_wifireMux_T_967 & _out_T_1750; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_577 = _out_wifireMux_T_968; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_578 = _out_wifireMux_T_968; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_579 = _out_wifireMux_T_968; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_580 = _out_wifireMux_T_968; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_581 = _out_wifireMux_T_968; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_582 = _out_wifireMux_T_968; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_583 = _out_wifireMux_T_968; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_584 = _out_wifireMux_T_968; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_969 = ~_out_T_1750; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_971 = _out_wifireMux_T_262 & out_frontSel_177; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_972 = _out_wifireMux_T_971 & _out_T_1826; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_875 = _out_wifireMux_T_972; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_876 = _out_wifireMux_T_972; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_877 = _out_wifireMux_T_972; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_878 = _out_wifireMux_T_972; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_879 = _out_wifireMux_T_972; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_880 = _out_wifireMux_T_972; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_881 = _out_wifireMux_T_972; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_882 = _out_wifireMux_T_972; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_973 = ~_out_T_1826; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_975 = _out_wifireMux_T_262 & out_frontSel_178; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_976 = _out_wifireMux_T_975 & _out_T_1892; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1139 = _out_wifireMux_T_976; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1140 = _out_wifireMux_T_976; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1141 = _out_wifireMux_T_976; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1142 = _out_wifireMux_T_976; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1143 = _out_wifireMux_T_976; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1144 = _out_wifireMux_T_976; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1145 = _out_wifireMux_T_976; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1146 = _out_wifireMux_T_976; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_977 = ~_out_T_1892; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_979 = _out_wifireMux_T_262 & out_frontSel_179; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_980 = _out_wifireMux_T_979 & _out_T_1646; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_184 = _out_wifireMux_T_980; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_185 = _out_wifireMux_T_980; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_186 = _out_wifireMux_T_980; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_187 = _out_wifireMux_T_980; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_188 = _out_wifireMux_T_980; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_189 = _out_wifireMux_T_980; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_190 = _out_wifireMux_T_980; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_191 = _out_wifireMux_T_980; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_981 = ~_out_T_1646; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_983 = _out_wifireMux_T_262 & out_frontSel_180; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_984 = _out_wifireMux_T_983 & _out_T_1746; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_561 = _out_wifireMux_T_984; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_562 = _out_wifireMux_T_984; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_563 = _out_wifireMux_T_984; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_564 = _out_wifireMux_T_984; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_565 = _out_wifireMux_T_984; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_566 = _out_wifireMux_T_984; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_567 = _out_wifireMux_T_984; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_568 = _out_wifireMux_T_984; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_985 = ~_out_T_1746; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_987 = _out_wifireMux_T_262 & out_frontSel_181; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_988 = _out_wifireMux_T_987 & _out_T_1762; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_625 = _out_wifireMux_T_988; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_626 = _out_wifireMux_T_988; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_627 = _out_wifireMux_T_988; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_628 = _out_wifireMux_T_988; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_629 = _out_wifireMux_T_988; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_630 = _out_wifireMux_T_988; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_631 = _out_wifireMux_T_988; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_632 = _out_wifireMux_T_988; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_989 = ~_out_T_1762; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_991 = _out_wifireMux_T_262 & out_frontSel_182; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_992 = _out_wifireMux_T_991 & _out_T_1828; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_883 = _out_wifireMux_T_992; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_884 = _out_wifireMux_T_992; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_885 = _out_wifireMux_T_992; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_886 = _out_wifireMux_T_992; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_887 = _out_wifireMux_T_992; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_888 = _out_wifireMux_T_992; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_889 = _out_wifireMux_T_992; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_890 = _out_wifireMux_T_992; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_993 = ~_out_T_1828; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_995 = _out_wifireMux_T_262 & out_frontSel_183; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_996 = _out_wifireMux_T_995 & _out_T_1872; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1059 = _out_wifireMux_T_996; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1060 = _out_wifireMux_T_996; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1061 = _out_wifireMux_T_996; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1062 = _out_wifireMux_T_996; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1063 = _out_wifireMux_T_996; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1064 = _out_wifireMux_T_996; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1065 = _out_wifireMux_T_996; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1066 = _out_wifireMux_T_996; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_997 = ~_out_T_1872; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_999 = _out_wifireMux_T_262 & out_frontSel_184; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1000 = _out_wifireMux_T_999 & _out_T_1626; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_104 = _out_wifireMux_T_1000; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_105 = _out_wifireMux_T_1000; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_106 = _out_wifireMux_T_1000; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_107 = _out_wifireMux_T_1000; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_108 = _out_wifireMux_T_1000; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_109 = _out_wifireMux_T_1000; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_110 = _out_wifireMux_T_1000; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_111 = _out_wifireMux_T_1000; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1001 = ~_out_T_1626; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1003 = _out_wifireMux_T_262 & out_frontSel_185; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1004 = _out_wifireMux_T_1003 & _out_T_1622; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_88 = _out_wifireMux_T_1004; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_89 = _out_wifireMux_T_1004; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_90 = _out_wifireMux_T_1004; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_91 = _out_wifireMux_T_1004; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_92 = _out_wifireMux_T_1004; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_93 = _out_wifireMux_T_1004; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_94 = _out_wifireMux_T_1004; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_95 = _out_wifireMux_T_1004; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1005 = ~_out_T_1622; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1007 = _out_wifireMux_T_262 & out_frontSel_186; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1008 = _out_wifireMux_T_1007 & _out_T_1850; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_971 = _out_wifireMux_T_1008; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_972 = _out_wifireMux_T_1008; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_973 = _out_wifireMux_T_1008; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_974 = _out_wifireMux_T_1008; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_975 = _out_wifireMux_T_1008; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_976 = _out_wifireMux_T_1008; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_977 = _out_wifireMux_T_1008; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_978 = _out_wifireMux_T_1008; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1009 = ~_out_T_1850; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1011 = _out_wifireMux_T_262 & out_frontSel_187; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1012 = _out_wifireMux_T_1011 & _out_T_1766; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_641 = _out_wifireMux_T_1012; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_642 = _out_wifireMux_T_1012; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_643 = _out_wifireMux_T_1012; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_644 = _out_wifireMux_T_1012; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_645 = _out_wifireMux_T_1012; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_646 = _out_wifireMux_T_1012; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_647 = _out_wifireMux_T_1012; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_648 = _out_wifireMux_T_1012; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1013 = ~_out_T_1766; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1015 = _out_wifireMux_T_262 & out_frontSel_188; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1016 = _out_wifireMux_T_1015 & _out_T_1700; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_394 = _out_wifireMux_T_1016; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_395 = _out_wifireMux_T_1016; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_396 = _out_wifireMux_T_1016; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_397 = _out_wifireMux_T_1016; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_398 = _out_wifireMux_T_1016; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_399 = _out_wifireMux_T_1016; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_400 = _out_wifireMux_T_1016; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_401 = _out_wifireMux_T_1016; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1017 = ~_out_T_1700; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1019 = _out_wifireMux_T_262 & out_frontSel_189; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1020 = _out_wifireMux_T_1019 & _out_T_1634; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_136 = _out_wifireMux_T_1020; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_137 = _out_wifireMux_T_1020; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_138 = _out_wifireMux_T_1020; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_139 = _out_wifireMux_T_1020; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_140 = _out_wifireMux_T_1020; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_141 = _out_wifireMux_T_1020; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_142 = _out_wifireMux_T_1020; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_143 = _out_wifireMux_T_1020; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1021 = ~_out_T_1634; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1023 = _out_wifireMux_T_262 & out_frontSel_190; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1024 = _out_wifireMux_T_1023 & _out_T_1870; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1051 = _out_wifireMux_T_1024; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1052 = _out_wifireMux_T_1024; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1053 = _out_wifireMux_T_1024; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1054 = _out_wifireMux_T_1024; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1055 = _out_wifireMux_T_1024; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1056 = _out_wifireMux_T_1024; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1057 = _out_wifireMux_T_1024; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1058 = _out_wifireMux_T_1024; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1025 = ~_out_T_1870; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1027 = _out_wifireMux_T_262 & out_frontSel_191; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1028 = _out_wifireMux_T_1027 & _out_T_1752; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_585 = _out_wifireMux_T_1028; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_586 = _out_wifireMux_T_1028; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_587 = _out_wifireMux_T_1028; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_588 = _out_wifireMux_T_1028; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_589 = _out_wifireMux_T_1028; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_590 = _out_wifireMux_T_1028; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_591 = _out_wifireMux_T_1028; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_592 = _out_wifireMux_T_1028; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1029 = ~_out_T_1752; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1031 = _out_wifireMux_T_262 & out_frontSel_192; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1032 = _out_wifireMux_T_1031 & _out_T_1682; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_328 = _out_wifireMux_T_1032; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_329 = _out_wifireMux_T_1032; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_330 = _out_wifireMux_T_1032; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_331 = _out_wifireMux_T_1032; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_332 = _out_wifireMux_T_1032; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_333 = _out_wifireMux_T_1032; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_334 = _out_wifireMux_T_1032; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_335 = _out_wifireMux_T_1032; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1033 = ~_out_T_1682; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1035 = _out_wifireMux_T_262 & out_frontSel_193; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1036 = _out_wifireMux_T_1035 & _out_T_1708; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_426 = _out_wifireMux_T_1036; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_427 = _out_wifireMux_T_1036; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_428 = _out_wifireMux_T_1036; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_429 = _out_wifireMux_T_1036; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_430 = _out_wifireMux_T_1036; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_431 = _out_wifireMux_T_1036; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_432 = _out_wifireMux_T_1036; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_433 = _out_wifireMux_T_1036; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1037 = ~_out_T_1708; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1039 = _out_wifireMux_T_262 & out_frontSel_194; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1040 = _out_wifireMux_T_1039 & _out_T_1816; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_835 = _out_wifireMux_T_1040; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_836 = _out_wifireMux_T_1040; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_837 = _out_wifireMux_T_1040; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_838 = _out_wifireMux_T_1040; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_839 = _out_wifireMux_T_1040; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_840 = _out_wifireMux_T_1040; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_841 = _out_wifireMux_T_1040; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_842 = _out_wifireMux_T_1040; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1041 = ~_out_T_1816; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1043 = _out_wifireMux_T_262 & out_frontSel_195; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1044 = _out_wifireMux_T_1043 & _out_T_1884; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1107 = _out_wifireMux_T_1044; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1108 = _out_wifireMux_T_1044; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1109 = _out_wifireMux_T_1044; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1110 = _out_wifireMux_T_1044; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1111 = _out_wifireMux_T_1044; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1112 = _out_wifireMux_T_1044; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1113 = _out_wifireMux_T_1044; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1114 = _out_wifireMux_T_1044; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1045 = ~_out_T_1884; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1047 = _out_wifireMux_T_262 & out_frontSel_196; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1048 = _out_wifireMux_T_1047 & _out_T_1630; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_120 = _out_wifireMux_T_1048; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_121 = _out_wifireMux_T_1048; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_122 = _out_wifireMux_T_1048; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_123 = _out_wifireMux_T_1048; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_124 = _out_wifireMux_T_1048; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_125 = _out_wifireMux_T_1048; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_126 = _out_wifireMux_T_1048; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_127 = _out_wifireMux_T_1048; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1049 = ~_out_T_1630; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1051 = _out_wifireMux_T_262 & out_frontSel_197; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1052 = _out_wifireMux_T_1051 & _out_T_1694; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_370 = _out_wifireMux_T_1052; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_371 = _out_wifireMux_T_1052; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_372 = _out_wifireMux_T_1052; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_373 = _out_wifireMux_T_1052; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_374 = _out_wifireMux_T_1052; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_375 = _out_wifireMux_T_1052; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_376 = _out_wifireMux_T_1052; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_377 = _out_wifireMux_T_1052; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1053 = ~_out_T_1694; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1055 = _out_wifireMux_T_262 & out_frontSel_198; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1056 = _out_wifireMux_T_1055 & _out_T_1788; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_723 = _out_wifireMux_T_1056; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_724 = _out_wifireMux_T_1056; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_725 = _out_wifireMux_T_1056; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_726 = _out_wifireMux_T_1056; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_727 = _out_wifireMux_T_1056; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_728 = _out_wifireMux_T_1056; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_729 = _out_wifireMux_T_1056; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_730 = _out_wifireMux_T_1056; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1057 = ~_out_T_1788; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1059 = _out_wifireMux_T_262 & out_frontSel_199; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1060 = _out_wifireMux_T_1059 & _out_T_1824; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_867 = _out_wifireMux_T_1060; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_868 = _out_wifireMux_T_1060; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_869 = _out_wifireMux_T_1060; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_870 = _out_wifireMux_T_1060; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_871 = _out_wifireMux_T_1060; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_872 = _out_wifireMux_T_1060; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_873 = _out_wifireMux_T_1060; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_874 = _out_wifireMux_T_1060; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1061 = ~_out_T_1824; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1063 = _out_wifireMux_T_262 & out_frontSel_200; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1064 = _out_wifireMux_T_1063 & _out_T_1896; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1155 = _out_wifireMux_T_1064; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1156 = _out_wifireMux_T_1064; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1157 = _out_wifireMux_T_1064; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1158 = _out_wifireMux_T_1064; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1159 = _out_wifireMux_T_1064; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1160 = _out_wifireMux_T_1064; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1161 = _out_wifireMux_T_1064; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1162 = _out_wifireMux_T_1064; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1065 = ~_out_T_1896; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1067 = _out_wifireMux_T_262 & out_frontSel_201; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1068 = _out_wifireMux_T_1067 & _out_T_1674; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_296 = _out_wifireMux_T_1068; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_297 = _out_wifireMux_T_1068; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_298 = _out_wifireMux_T_1068; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_299 = _out_wifireMux_T_1068; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_300 = _out_wifireMux_T_1068; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_301 = _out_wifireMux_T_1068; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_302 = _out_wifireMux_T_1068; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_303 = _out_wifireMux_T_1068; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1069 = ~_out_T_1674; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1071 = _out_wifireMux_T_262 & out_frontSel_202; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1072 = _out_wifireMux_T_1071 & _out_T_1614; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_56 = _out_wifireMux_T_1072; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_57 = _out_wifireMux_T_1072; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_58 = _out_wifireMux_T_1072; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_59 = _out_wifireMux_T_1072; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_60 = _out_wifireMux_T_1072; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_61 = _out_wifireMux_T_1072; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_62 = _out_wifireMux_T_1072; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_63 = _out_wifireMux_T_1072; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1073 = ~_out_T_1614; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1075 = _out_wifireMux_T_262 & out_frontSel_203; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1076 = _out_wifireMux_T_1075 & _out_T_1836; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_915 = _out_wifireMux_T_1076; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_916 = _out_wifireMux_T_1076; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_917 = _out_wifireMux_T_1076; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_918 = _out_wifireMux_T_1076; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_919 = _out_wifireMux_T_1076; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_920 = _out_wifireMux_T_1076; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_921 = _out_wifireMux_T_1076; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_922 = _out_wifireMux_T_1076; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1077 = ~_out_T_1836; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1079 = _out_wifireMux_T_262 & out_frontSel_204; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1080 = _out_wifireMux_T_1079 & _out_T_1754; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_593 = _out_wifireMux_T_1080; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_594 = _out_wifireMux_T_1080; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_595 = _out_wifireMux_T_1080; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_596 = _out_wifireMux_T_1080; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_597 = _out_wifireMux_T_1080; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_598 = _out_wifireMux_T_1080; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_599 = _out_wifireMux_T_1080; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_600 = _out_wifireMux_T_1080; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1081 = ~_out_T_1754; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1083 = _out_wifireMux_T_262 & out_frontSel_205; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1084 = _out_wifireMux_T_1083 & _out_T_1726; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_487 = _out_wifireMux_T_1084; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_488 = _out_wifireMux_T_1084; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_489 = _out_wifireMux_T_1084; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_490 = _out_wifireMux_T_1084; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_491 = _out_wifireMux_T_1084; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_492 = _out_wifireMux_T_1084; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_493 = _out_wifireMux_T_1084; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_494 = _out_wifireMux_T_1084; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1085 = ~_out_T_1726; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1087 = _out_wifireMux_T_262 & out_frontSel_206; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1088 = _out_wifireMux_T_1087 & _out_T_1668; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_272 = _out_wifireMux_T_1088; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_273 = _out_wifireMux_T_1088; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_274 = _out_wifireMux_T_1088; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_275 = _out_wifireMux_T_1088; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_276 = _out_wifireMux_T_1088; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_277 = _out_wifireMux_T_1088; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_278 = _out_wifireMux_T_1088; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_279 = _out_wifireMux_T_1088; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1089 = ~_out_T_1668; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1091 = _out_wifireMux_T_262 & out_frontSel_207; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1092 = _out_wifireMux_T_1091 & _out_T_1858; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1003 = _out_wifireMux_T_1092; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1004 = _out_wifireMux_T_1092; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1005 = _out_wifireMux_T_1092; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1006 = _out_wifireMux_T_1092; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1007 = _out_wifireMux_T_1092; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1008 = _out_wifireMux_T_1092; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1009 = _out_wifireMux_T_1092; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1010 = _out_wifireMux_T_1092; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1093 = ~_out_T_1858; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1095 = _out_wifireMux_T_262 & out_frontSel_208; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1096 = _out_wifireMux_T_1095 & _out_T_1778; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_689 = _out_wifireMux_T_1096; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_690 = _out_wifireMux_T_1096; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_691 = _out_wifireMux_T_1096; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_692 = _out_wifireMux_T_1096; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_693 = _out_wifireMux_T_1096; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_694 = _out_wifireMux_T_1096; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_695 = _out_wifireMux_T_1096; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_696 = _out_wifireMux_T_1096; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1097 = ~_out_T_1778; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1099 = _out_wifireMux_T_262 & out_frontSel_209; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1100 = _out_wifireMux_T_1099 & _out_T_1812; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_819 = _out_wifireMux_T_1100; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_820 = _out_wifireMux_T_1100; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_821 = _out_wifireMux_T_1100; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_822 = _out_wifireMux_T_1100; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_823 = _out_wifireMux_T_1100; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_824 = _out_wifireMux_T_1100; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_825 = _out_wifireMux_T_1100; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_826 = _out_wifireMux_T_1100; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1101 = ~_out_T_1812; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1103 = _out_wifireMux_T_262 & out_frontSel_210; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1104 = _out_wifireMux_T_1103 & _out_T_1878; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1083 = _out_wifireMux_T_1104; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1084 = _out_wifireMux_T_1104; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1085 = _out_wifireMux_T_1104; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1086 = _out_wifireMux_T_1104; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1087 = _out_wifireMux_T_1104; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1088 = _out_wifireMux_T_1104; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1089 = _out_wifireMux_T_1104; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1090 = _out_wifireMux_T_1104; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1105 = ~_out_T_1878; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1107 = _out_wifireMux_T_262 & out_frontSel_211; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1108 = _out_wifireMux_T_1107 & _out_T_1652; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_208 = _out_wifireMux_T_1108; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_209 = _out_wifireMux_T_1108; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_210 = _out_wifireMux_T_1108; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_211 = _out_wifireMux_T_1108; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_212 = _out_wifireMux_T_1108; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_213 = _out_wifireMux_T_1108; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_214 = _out_wifireMux_T_1108; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_215 = _out_wifireMux_T_1108; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1109 = ~_out_T_1652; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1111 = _out_wifireMux_T_262 & out_frontSel_212; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1112 = _out_wifireMux_T_1111 & _out_T_1710; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_434 = _out_wifireMux_T_1112; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_435 = _out_wifireMux_T_1112; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_436 = _out_wifireMux_T_1112; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_437 = _out_wifireMux_T_1112; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_438 = _out_wifireMux_T_1112; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_439 = _out_wifireMux_T_1112; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_440 = _out_wifireMux_T_1112; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_441 = _out_wifireMux_T_1112; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1113 = ~_out_T_1710; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1115 = _out_wifireMux_T_262 & out_frontSel_213; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1116 = _out_wifireMux_T_1115 & _out_T_1784; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_707 = _out_wifireMux_T_1116; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_708 = _out_wifireMux_T_1116; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_709 = _out_wifireMux_T_1116; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_710 = _out_wifireMux_T_1116; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_711 = _out_wifireMux_T_1116; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_712 = _out_wifireMux_T_1116; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_713 = _out_wifireMux_T_1116; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_714 = _out_wifireMux_T_1116; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1117 = ~_out_T_1784; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1119 = _out_wifireMux_T_262 & out_frontSel_214; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1120 = _out_wifireMux_T_1119 & _out_T_1860; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1011 = _out_wifireMux_T_1120; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1012 = _out_wifireMux_T_1120; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1013 = _out_wifireMux_T_1120; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1014 = _out_wifireMux_T_1120; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1015 = _out_wifireMux_T_1120; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1016 = _out_wifireMux_T_1120; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1017 = _out_wifireMux_T_1120; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1018 = _out_wifireMux_T_1120; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1121 = ~_out_T_1860; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1123 = _out_wifireMux_T_262 & out_frontSel_215; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1124 = _out_wifireMux_T_1123 & _out_T_1900; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1171 = _out_wifireMux_T_1124; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1172 = _out_wifireMux_T_1124; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1173 = _out_wifireMux_T_1124; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1174 = _out_wifireMux_T_1124; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1175 = _out_wifireMux_T_1124; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1176 = _out_wifireMux_T_1124; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1177 = _out_wifireMux_T_1124; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1178 = _out_wifireMux_T_1124; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1125 = ~_out_T_1900; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1127 = _out_wifireMux_T_262 & out_frontSel_216; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1128 = _out_wifireMux_T_1127 & _out_T_1642; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_168 = _out_wifireMux_T_1128; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_169 = _out_wifireMux_T_1128; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_170 = _out_wifireMux_T_1128; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_171 = _out_wifireMux_T_1128; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_172 = _out_wifireMux_T_1128; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_173 = _out_wifireMux_T_1128; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_174 = _out_wifireMux_T_1128; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_175 = _out_wifireMux_T_1128; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1129 = ~_out_T_1642; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1131 = _out_wifireMux_T_262 & out_frontSel_217; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1132 = _out_wifireMux_T_1131 & _out_T_1610; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_40 = _out_wifireMux_T_1132; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_41 = _out_wifireMux_T_1132; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_42 = _out_wifireMux_T_1132; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_43 = _out_wifireMux_T_1132; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_44 = _out_wifireMux_T_1132; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_45 = _out_wifireMux_T_1132; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_46 = _out_wifireMux_T_1132; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_47 = _out_wifireMux_T_1132; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1133 = ~_out_T_1610; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1135 = _out_wifireMux_T_262 & out_frontSel_218; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1136 = _out_wifireMux_T_1135 & _out_T_1838; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_923 = _out_wifireMux_T_1136; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_924 = _out_wifireMux_T_1136; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_925 = _out_wifireMux_T_1136; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_926 = _out_wifireMux_T_1136; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_927 = _out_wifireMux_T_1136; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_928 = _out_wifireMux_T_1136; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_929 = _out_wifireMux_T_1136; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_930 = _out_wifireMux_T_1136; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1137 = ~_out_T_1838; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1139 = _out_wifireMux_T_262 & out_frontSel_219; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1140 = _out_wifireMux_T_1139 & _out_T_1772; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_665 = _out_wifireMux_T_1140; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_666 = _out_wifireMux_T_1140; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_667 = _out_wifireMux_T_1140; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_668 = _out_wifireMux_T_1140; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_669 = _out_wifireMux_T_1140; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_670 = _out_wifireMux_T_1140; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_671 = _out_wifireMux_T_1140; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_672 = _out_wifireMux_T_1140; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1141 = ~_out_T_1772; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1143 = _out_wifireMux_T_262 & out_frontSel_220; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1144 = _out_wifireMux_T_1143 & _out_T_1676; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_304 = _out_wifireMux_T_1144; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_305 = _out_wifireMux_T_1144; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_306 = _out_wifireMux_T_1144; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_307 = _out_wifireMux_T_1144; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_308 = _out_wifireMux_T_1144; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_309 = _out_wifireMux_T_1144; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_310 = _out_wifireMux_T_1144; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_311 = _out_wifireMux_T_1144; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1145 = ~_out_T_1676; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1147 = _out_wifireMux_T_262 & out_frontSel_221; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1148 = _out_wifireMux_T_1147 & _out_T_1658; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_232 = _out_wifireMux_T_1148; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_233 = _out_wifireMux_T_1148; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_234 = _out_wifireMux_T_1148; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_235 = _out_wifireMux_T_1148; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_236 = _out_wifireMux_T_1148; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_237 = _out_wifireMux_T_1148; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_238 = _out_wifireMux_T_1148; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_239 = _out_wifireMux_T_1148; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1149 = ~_out_T_1658; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1151 = _out_wifireMux_T_262 & out_frontSel_222; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1152 = _out_wifireMux_T_1151 & _out_T_1902; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1179 = _out_wifireMux_T_1152; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1180 = _out_wifireMux_T_1152; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1181 = _out_wifireMux_T_1152; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1182 = _out_wifireMux_T_1152; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1183 = _out_wifireMux_T_1152; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1184 = _out_wifireMux_T_1152; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1185 = _out_wifireMux_T_1152; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1186 = _out_wifireMux_T_1152; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1153 = ~_out_T_1902; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1155 = _out_wifireMux_T_262 & out_frontSel_223; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1156 = _out_wifireMux_T_1155 & _out_T_1798; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_763 = _out_wifireMux_T_1156; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_764 = _out_wifireMux_T_1156; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_765 = _out_wifireMux_T_1156; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_766 = _out_wifireMux_T_1156; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_767 = _out_wifireMux_T_1156; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_768 = _out_wifireMux_T_1156; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_769 = _out_wifireMux_T_1156; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_770 = _out_wifireMux_T_1156; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1157 = ~_out_T_1798; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1159 = _out_wifireMux_T_262 & out_frontSel_224; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1160 = _out_wifireMux_T_1159 & _out_T_1696; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_378 = _out_wifireMux_T_1160; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_379 = _out_wifireMux_T_1160; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_380 = _out_wifireMux_T_1160; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_381 = _out_wifireMux_T_1160; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_382 = _out_wifireMux_T_1160; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_383 = _out_wifireMux_T_1160; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_384 = _out_wifireMux_T_1160; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_385 = _out_wifireMux_T_1160; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1161 = ~_out_T_1696; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1163 = _out_wifireMux_T_262 & out_frontSel_225; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1164 = _out_wifireMux_T_1163 & _out_T_1706; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_418 = _out_wifireMux_T_1164; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_419 = _out_wifireMux_T_1164; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_420 = _out_wifireMux_T_1164; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_421 = _out_wifireMux_T_1164; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_422 = _out_wifireMux_T_1164; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_423 = _out_wifireMux_T_1164; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_424 = _out_wifireMux_T_1164; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_425 = _out_wifireMux_T_1164; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1165 = ~_out_T_1706; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1167 = _out_wifireMux_T_262 & out_frontSel_226; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1168 = _out_wifireMux_T_1167 & _out_T_1802; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_779 = _out_wifireMux_T_1168; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_780 = _out_wifireMux_T_1168; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_781 = _out_wifireMux_T_1168; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_782 = _out_wifireMux_T_1168; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_783 = _out_wifireMux_T_1168; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_784 = _out_wifireMux_T_1168; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_785 = _out_wifireMux_T_1168; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_786 = _out_wifireMux_T_1168; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1169 = ~_out_T_1802; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1171 = _out_wifireMux_T_262 & out_frontSel_227; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1172 = _out_wifireMux_T_1171 & _out_T_1908; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1203 = _out_wifireMux_T_1172; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1204 = _out_wifireMux_T_1172; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1205 = _out_wifireMux_T_1172; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1206 = _out_wifireMux_T_1172; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1207 = _out_wifireMux_T_1172; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1208 = _out_wifireMux_T_1172; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1209 = _out_wifireMux_T_1172; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1210 = _out_wifireMux_T_1172; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1173 = ~_out_T_1908; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1175 = _out_wifireMux_T_262 & out_frontSel_228; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1176 = _out_wifireMux_T_1175 & _out_T_1638; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_152 = _out_wifireMux_T_1176; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_153 = _out_wifireMux_T_1176; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_154 = _out_wifireMux_T_1176; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_155 = _out_wifireMux_T_1176; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_156 = _out_wifireMux_T_1176; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_157 = _out_wifireMux_T_1176; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_158 = _out_wifireMux_T_1176; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_159 = _out_wifireMux_T_1176; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1177 = ~_out_T_1638; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1179 = _out_wifireMux_T_262 & out_frontSel_229; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1180 = _out_wifireMux_T_1179 & _out_T_1690; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_354 = _out_wifireMux_T_1180; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_355 = _out_wifireMux_T_1180; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_356 = _out_wifireMux_T_1180; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_357 = _out_wifireMux_T_1180; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_358 = _out_wifireMux_T_1180; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_359 = _out_wifireMux_T_1180; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_360 = _out_wifireMux_T_1180; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_361 = _out_wifireMux_T_1180; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1181 = ~_out_T_1690; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1183 = _out_wifireMux_T_262 & out_frontSel_230; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1184 = _out_wifireMux_T_1183 & _out_T_1774; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_673 = _out_wifireMux_T_1184; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_674 = _out_wifireMux_T_1184; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_675 = _out_wifireMux_T_1184; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_676 = _out_wifireMux_T_1184; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_677 = _out_wifireMux_T_1184; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_678 = _out_wifireMux_T_1184; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_679 = _out_wifireMux_T_1184; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_680 = _out_wifireMux_T_1184; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1185 = ~_out_T_1774; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1187 = _out_wifireMux_T_262 & out_frontSel_231; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1188 = _out_wifireMux_T_1187 & _out_T_1844; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_947 = _out_wifireMux_T_1188; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_948 = _out_wifireMux_T_1188; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_949 = _out_wifireMux_T_1188; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_950 = _out_wifireMux_T_1188; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_951 = _out_wifireMux_T_1188; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_952 = _out_wifireMux_T_1188; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_953 = _out_wifireMux_T_1188; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_954 = _out_wifireMux_T_1188; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1189 = ~_out_T_1844; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1191 = _out_wifireMux_T_262 & out_frontSel_232; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1192 = _out_wifireMux_T_1191 & _out_T_1904; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1187 = _out_wifireMux_T_1192; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1188 = _out_wifireMux_T_1192; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1189 = _out_wifireMux_T_1192; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1190 = _out_wifireMux_T_1192; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1191 = _out_wifireMux_T_1192; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1192 = _out_wifireMux_T_1192; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1193 = _out_wifireMux_T_1192; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1194 = _out_wifireMux_T_1192; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1193 = ~_out_T_1904; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1195 = _out_wifireMux_T_262 & out_frontSel_233; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1196 = _out_wifireMux_T_1195 & _out_T_1670; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_280 = _out_wifireMux_T_1196; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_281 = _out_wifireMux_T_1196; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_282 = _out_wifireMux_T_1196; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_283 = _out_wifireMux_T_1196; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_284 = _out_wifireMux_T_1196; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_285 = _out_wifireMux_T_1196; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_286 = _out_wifireMux_T_1196; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_287 = _out_wifireMux_T_1196; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1197 = ~_out_T_1670; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1199 = _out_wifireMux_T_262 & out_frontSel_234; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1200 = _out_wifireMux_T_1199 & _out_T_1604; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_16 = _out_wifireMux_T_1200; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_17 = _out_wifireMux_T_1200; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_18 = _out_wifireMux_T_1200; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_19 = _out_wifireMux_T_1200; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_20 = _out_wifireMux_T_1200; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_21 = _out_wifireMux_T_1200; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_22 = _out_wifireMux_T_1200; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_23 = _out_wifireMux_T_1200; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1201 = ~_out_T_1604; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1203 = _out_wifireMux_T_262 & out_frontSel_235; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1204 = _out_wifireMux_T_1203 & _out_T_1862; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1019 = _out_wifireMux_T_1204; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1020 = _out_wifireMux_T_1204; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1021 = _out_wifireMux_T_1204; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1022 = _out_wifireMux_T_1204; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1023 = _out_wifireMux_T_1204; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1024 = _out_wifireMux_T_1204; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1025 = _out_wifireMux_T_1204; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1026 = _out_wifireMux_T_1204; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1205 = ~_out_T_1862; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1207 = _out_wifireMux_T_262 & out_frontSel_236; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1208 = _out_wifireMux_T_1207 & _out_T_1760; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_617 = _out_wifireMux_T_1208; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_618 = _out_wifireMux_T_1208; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_619 = _out_wifireMux_T_1208; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_620 = _out_wifireMux_T_1208; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_621 = _out_wifireMux_T_1208; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_622 = _out_wifireMux_T_1208; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_623 = _out_wifireMux_T_1208; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_624 = _out_wifireMux_T_1208; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1209 = ~_out_T_1760; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1211 = _out_wifireMux_T_262 & out_frontSel_237; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1212 = _out_wifireMux_T_1211 & _out_T_1730; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_503 = _out_wifireMux_T_1212; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_504 = _out_wifireMux_T_1212; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_505 = _out_wifireMux_T_1212; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_506 = _out_wifireMux_T_1212; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_507 = _out_wifireMux_T_1212; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_508 = _out_wifireMux_T_1212; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_509 = _out_wifireMux_T_1212; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_510 = _out_wifireMux_T_1212; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1213 = ~_out_T_1730; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1215 = _out_wifireMux_T_262 & out_frontSel_238; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1216 = _out_wifireMux_T_1215 & _out_T_1650; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_200 = _out_wifireMux_T_1216; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_201 = _out_wifireMux_T_1216; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_202 = _out_wifireMux_T_1216; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_203 = _out_wifireMux_T_1216; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_204 = _out_wifireMux_T_1216; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_205 = _out_wifireMux_T_1216; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_206 = _out_wifireMux_T_1216; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_207 = _out_wifireMux_T_1216; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1217 = ~_out_T_1650; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1219 = _out_wifireMux_T_262 & out_frontSel_239; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1220 = _out_wifireMux_T_1219 & _out_T_1886; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1115 = _out_wifireMux_T_1220; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1116 = _out_wifireMux_T_1220; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1117 = _out_wifireMux_T_1220; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1118 = _out_wifireMux_T_1220; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1119 = _out_wifireMux_T_1220; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1120 = _out_wifireMux_T_1220; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1121 = _out_wifireMux_T_1220; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1122 = _out_wifireMux_T_1220; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1221 = ~_out_T_1886; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1223 = _out_wifireMux_T_262 & out_frontSel_240; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1224 = _out_wifireMux_T_1223 & _out_T_1792; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_739 = _out_wifireMux_T_1224; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_740 = _out_wifireMux_T_1224; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_741 = _out_wifireMux_T_1224; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_742 = _out_wifireMux_T_1224; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_743 = _out_wifireMux_T_1224; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_744 = _out_wifireMux_T_1224; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_745 = _out_wifireMux_T_1224; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_746 = _out_wifireMux_T_1224; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1225 = ~_out_T_1792; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1227 = _out_wifireMux_T_262 & out_frontSel_241; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1228 = _out_wifireMux_T_1227 & _out_T_1804; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_787 = _out_wifireMux_T_1228; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_788 = _out_wifireMux_T_1228; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_789 = _out_wifireMux_T_1228; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_790 = _out_wifireMux_T_1228; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_791 = _out_wifireMux_T_1228; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_792 = _out_wifireMux_T_1228; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_793 = _out_wifireMux_T_1228; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_794 = _out_wifireMux_T_1228; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1229 = ~_out_T_1804; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1231 = _out_wifireMux_T_262 & out_frontSel_242; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1232 = _out_wifireMux_T_1231 & _out_T_1888; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1123 = _out_wifireMux_T_1232; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1124 = _out_wifireMux_T_1232; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1125 = _out_wifireMux_T_1232; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1126 = _out_wifireMux_T_1232; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1127 = _out_wifireMux_T_1232; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1128 = _out_wifireMux_T_1232; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1129 = _out_wifireMux_T_1232; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1130 = _out_wifireMux_T_1232; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1233 = ~_out_T_1888; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1235 = _out_wifireMux_T_262 & out_frontSel_243; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1236 = _out_wifireMux_T_1235 & _out_T_1664; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_256 = _out_wifireMux_T_1236; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_257 = _out_wifireMux_T_1236; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_258 = _out_wifireMux_T_1236; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_259 = _out_wifireMux_T_1236; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_260 = _out_wifireMux_T_1236; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_261 = _out_wifireMux_T_1236; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_262 = _out_wifireMux_T_1236; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_263 = _out_wifireMux_T_1236; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1237 = ~_out_T_1664; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1239 = _out_wifireMux_T_262 & out_frontSel_244; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1240 = _out_wifireMux_T_1239 & _out_T_1734; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_519 = _out_wifireMux_T_1240; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_520 = _out_wifireMux_T_1240; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_521 = _out_wifireMux_T_1240; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_522 = _out_wifireMux_T_1240; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_523 = _out_wifireMux_T_1240; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_524 = _out_wifireMux_T_1240; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_525 = _out_wifireMux_T_1240; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_526 = _out_wifireMux_T_1240; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1241 = ~_out_T_1734; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1243 = _out_wifireMux_T_262 & out_frontSel_245; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1244 = _out_wifireMux_T_1243 & _out_T_1776; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_681 = _out_wifireMux_T_1244; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_682 = _out_wifireMux_T_1244; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_683 = _out_wifireMux_T_1244; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_684 = _out_wifireMux_T_1244; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_685 = _out_wifireMux_T_1244; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_686 = _out_wifireMux_T_1244; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_687 = _out_wifireMux_T_1244; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_688 = _out_wifireMux_T_1244; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1245 = ~_out_T_1776; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1247 = _out_wifireMux_T_262 & out_frontSel_246; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1248 = _out_wifireMux_T_1247 & _out_T_1864; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1027 = _out_wifireMux_T_1248; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1028 = _out_wifireMux_T_1248; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1029 = _out_wifireMux_T_1248; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1030 = _out_wifireMux_T_1248; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1031 = _out_wifireMux_T_1248; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1032 = _out_wifireMux_T_1248; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1033 = _out_wifireMux_T_1248; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1034 = _out_wifireMux_T_1248; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1249 = ~_out_T_1864; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1251 = _out_wifireMux_T_262 & out_frontSel_247; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1252 = _out_wifireMux_T_1251 & _out_T_1612; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_48 = _out_wifireMux_T_1252; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_49 = _out_wifireMux_T_1252; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_50 = _out_wifireMux_T_1252; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_51 = _out_wifireMux_T_1252; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_52 = _out_wifireMux_T_1252; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_53 = _out_wifireMux_T_1252; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_54 = _out_wifireMux_T_1252; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_55 = _out_wifireMux_T_1252; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1253 = ~_out_T_1612; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1255 = _out_wifireMux_T_262 & out_frontSel_248; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1256 = _out_wifireMux_T_1255 & _out_T_1672; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_288 = _out_wifireMux_T_1256; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_289 = _out_wifireMux_T_1256; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_290 = _out_wifireMux_T_1256; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_291 = _out_wifireMux_T_1256; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_292 = _out_wifireMux_T_1256; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_293 = _out_wifireMux_T_1256; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_294 = _out_wifireMux_T_1256; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_295 = _out_wifireMux_T_1256; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1257 = ~_out_T_1672; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1259 = _out_wifireMux_T_262 & out_frontSel_249; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1260 = _out_wifireMux_T_1259 & _out_T_1602; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_8 = _out_wifireMux_T_1260; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_9 = _out_wifireMux_T_1260; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_10 = _out_wifireMux_T_1260; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_11 = _out_wifireMux_T_1260; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_12 = _out_wifireMux_T_1260; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_13 = _out_wifireMux_T_1260; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_14 = _out_wifireMux_T_1260; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_15 = _out_wifireMux_T_1260; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1261 = ~_out_T_1602; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1263 = _out_wifireMux_T_262 & out_frontSel_250; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1264 = _out_wifireMux_T_1263 & _out_T_1842; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_939 = _out_wifireMux_T_1264; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_940 = _out_wifireMux_T_1264; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_941 = _out_wifireMux_T_1264; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_942 = _out_wifireMux_T_1264; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_943 = _out_wifireMux_T_1264; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_944 = _out_wifireMux_T_1264; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_945 = _out_wifireMux_T_1264; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_946 = _out_wifireMux_T_1264; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1265 = ~_out_T_1842; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1267 = _out_wifireMux_T_262 & out_frontSel_251; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1268 = _out_wifireMux_T_1267 & _out_T_1794; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_747 = _out_wifireMux_T_1268; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_748 = _out_wifireMux_T_1268; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_749 = _out_wifireMux_T_1268; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_750 = _out_wifireMux_T_1268; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_751 = _out_wifireMux_T_1268; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_752 = _out_wifireMux_T_1268; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_753 = _out_wifireMux_T_1268; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_754 = _out_wifireMux_T_1268; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1269 = ~_out_T_1794; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1271 = _out_wifireMux_T_262 & out_frontSel_252; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1272 = _out_wifireMux_T_1271 & _out_T_1692; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_362 = _out_wifireMux_T_1272; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_363 = _out_wifireMux_T_1272; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_364 = _out_wifireMux_T_1272; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_365 = _out_wifireMux_T_1272; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_366 = _out_wifireMux_T_1272; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_367 = _out_wifireMux_T_1272; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_368 = _out_wifireMux_T_1272; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_369 = _out_wifireMux_T_1272; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1273 = ~_out_T_1692; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1275 = _out_wifireMux_T_262 & out_frontSel_253; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1276 = _out_wifireMux_T_1275 & _out_T_1654; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_216 = _out_wifireMux_T_1276; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_217 = _out_wifireMux_T_1276; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_218 = _out_wifireMux_T_1276; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_219 = _out_wifireMux_T_1276; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_220 = _out_wifireMux_T_1276; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_221 = _out_wifireMux_T_1276; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_222 = _out_wifireMux_T_1276; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_223 = _out_wifireMux_T_1276; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1277 = ~_out_T_1654; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1279 = _out_wifireMux_T_262 & out_frontSel_254; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1280 = _out_wifireMux_T_1279 & _out_T_1906; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1195 = _out_wifireMux_T_1280; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1196 = _out_wifireMux_T_1280; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1197 = _out_wifireMux_T_1280; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1198 = _out_wifireMux_T_1280; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1199 = _out_wifireMux_T_1280; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1200 = _out_wifireMux_T_1280; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1201 = _out_wifireMux_T_1280; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1202 = _out_wifireMux_T_1280; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1281 = ~_out_T_1906; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1283 = _out_wifireMux_T_262 & out_frontSel_255; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1284 = _out_wifireMux_T_1283 & _out_T_1810; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_811 = _out_wifireMux_T_1284; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_812 = _out_wifireMux_T_1284; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_813 = _out_wifireMux_T_1284; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_814 = _out_wifireMux_T_1284; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_815 = _out_wifireMux_T_1284; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_816 = _out_wifireMux_T_1284; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_817 = _out_wifireMux_T_1284; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_818 = _out_wifireMux_T_1284; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1285 = ~_out_T_1810; // @[RegisterRouter.scala:87:24] wire _GEN_23 = out_front_1_valid & out_1_ready; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_259; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_259 = _GEN_23; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_260; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_260 = _GEN_23; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_260 = _out_rofireMux_T_259 & out_front_1_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_261 = _out_rofireMux_T_260 & out_backSel_0_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_262 = _out_rofireMux_T_261 & _out_T_1717; // @[RegisterRouter.scala:87:24] assign out_roready_1_451 = _out_rofireMux_T_262; // @[RegisterRouter.scala:87:24] assign out_roready_1_452 = _out_rofireMux_T_262; // @[RegisterRouter.scala:87:24] assign out_roready_1_453 = _out_rofireMux_T_262; // @[RegisterRouter.scala:87:24] assign out_roready_1_454 = _out_rofireMux_T_262; // @[RegisterRouter.scala:87:24] assign out_roready_1_455 = _out_rofireMux_T_262; // @[RegisterRouter.scala:87:24] assign out_roready_1_456 = _out_rofireMux_T_262; // @[RegisterRouter.scala:87:24] assign out_roready_1_457 = _out_rofireMux_T_262; // @[RegisterRouter.scala:87:24] assign out_roready_1_458 = _out_rofireMux_T_262; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_263 = ~_out_T_1717; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_265 = _out_rofireMux_T_260 & out_backSel_1_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_266 = _out_rofireMux_T_265 & _out_T_1625; // @[RegisterRouter.scala:87:24] assign out_roready_1_96 = _out_rofireMux_T_266; // @[RegisterRouter.scala:87:24] assign out_roready_1_97 = _out_rofireMux_T_266; // @[RegisterRouter.scala:87:24] assign out_roready_1_98 = _out_rofireMux_T_266; // @[RegisterRouter.scala:87:24] assign out_roready_1_99 = _out_rofireMux_T_266; // @[RegisterRouter.scala:87:24] assign out_roready_1_100 = _out_rofireMux_T_266; // @[RegisterRouter.scala:87:24] assign out_roready_1_101 = _out_rofireMux_T_266; // @[RegisterRouter.scala:87:24] assign out_roready_1_102 = _out_rofireMux_T_266; // @[RegisterRouter.scala:87:24] assign out_roready_1_103 = _out_rofireMux_T_266; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_267 = ~_out_T_1625; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_269 = _out_rofireMux_T_260 & out_backSel_2_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_270 = _out_rofireMux_T_269 & _out_T_1847; // @[RegisterRouter.scala:87:24] assign out_roready_1_955 = _out_rofireMux_T_270; // @[RegisterRouter.scala:87:24] assign out_roready_1_956 = _out_rofireMux_T_270; // @[RegisterRouter.scala:87:24] assign out_roready_1_957 = _out_rofireMux_T_270; // @[RegisterRouter.scala:87:24] assign out_roready_1_958 = _out_rofireMux_T_270; // @[RegisterRouter.scala:87:24] assign out_roready_1_959 = _out_rofireMux_T_270; // @[RegisterRouter.scala:87:24] assign out_roready_1_960 = _out_rofireMux_T_270; // @[RegisterRouter.scala:87:24] assign out_roready_1_961 = _out_rofireMux_T_270; // @[RegisterRouter.scala:87:24] assign out_roready_1_962 = _out_rofireMux_T_270; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_271 = ~_out_T_1847; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_273 = _out_rofireMux_T_260 & out_backSel_3_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_274 = _out_rofireMux_T_273 & _out_T_1757; // @[RegisterRouter.scala:87:24] assign out_roready_1_601 = _out_rofireMux_T_274; // @[RegisterRouter.scala:87:24] assign out_roready_1_602 = _out_rofireMux_T_274; // @[RegisterRouter.scala:87:24] assign out_roready_1_603 = _out_rofireMux_T_274; // @[RegisterRouter.scala:87:24] assign out_roready_1_604 = _out_rofireMux_T_274; // @[RegisterRouter.scala:87:24] assign out_roready_1_605 = _out_rofireMux_T_274; // @[RegisterRouter.scala:87:24] assign out_roready_1_606 = _out_rofireMux_T_274; // @[RegisterRouter.scala:87:24] assign out_roready_1_607 = _out_rofireMux_T_274; // @[RegisterRouter.scala:87:24] assign out_roready_1_608 = _out_rofireMux_T_274; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_275 = ~_out_T_1757; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_277 = _out_rofireMux_T_260 & out_backSel_4_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_278 = _out_rofireMux_T_277 & _out_T_1679; // @[RegisterRouter.scala:87:24] assign out_roready_1_312 = _out_rofireMux_T_278; // @[RegisterRouter.scala:87:24] assign out_roready_1_313 = _out_rofireMux_T_278; // @[RegisterRouter.scala:87:24] assign out_roready_1_314 = _out_rofireMux_T_278; // @[RegisterRouter.scala:87:24] assign out_roready_1_315 = _out_rofireMux_T_278; // @[RegisterRouter.scala:87:24] assign out_roready_1_316 = _out_rofireMux_T_278; // @[RegisterRouter.scala:87:24] assign out_roready_1_317 = _out_rofireMux_T_278; // @[RegisterRouter.scala:87:24] assign out_roready_1_318 = _out_rofireMux_T_278; // @[RegisterRouter.scala:87:24] assign out_roready_1_319 = _out_rofireMux_T_278; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_279 = ~_out_T_1679; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_281 = _out_rofireMux_T_260 & out_backSel_5_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_282 = _out_rofireMux_T_281 & _out_T_1641; // @[RegisterRouter.scala:87:24] assign out_roready_1_160 = _out_rofireMux_T_282; // @[RegisterRouter.scala:87:24] assign out_roready_1_161 = _out_rofireMux_T_282; // @[RegisterRouter.scala:87:24] assign out_roready_1_162 = _out_rofireMux_T_282; // @[RegisterRouter.scala:87:24] assign out_roready_1_163 = _out_rofireMux_T_282; // @[RegisterRouter.scala:87:24] assign out_roready_1_164 = _out_rofireMux_T_282; // @[RegisterRouter.scala:87:24] assign out_roready_1_165 = _out_rofireMux_T_282; // @[RegisterRouter.scala:87:24] assign out_roready_1_166 = _out_rofireMux_T_282; // @[RegisterRouter.scala:87:24] assign out_roready_1_167 = _out_rofireMux_T_282; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_283 = ~_out_T_1641; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_285 = _out_rofireMux_T_260 & out_backSel_6_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_286 = _out_rofireMux_T_285 & _out_T_1877; // @[RegisterRouter.scala:87:24] assign out_roready_1_1075 = _out_rofireMux_T_286; // @[RegisterRouter.scala:87:24] assign out_roready_1_1076 = _out_rofireMux_T_286; // @[RegisterRouter.scala:87:24] assign out_roready_1_1077 = _out_rofireMux_T_286; // @[RegisterRouter.scala:87:24] assign out_roready_1_1078 = _out_rofireMux_T_286; // @[RegisterRouter.scala:87:24] assign out_roready_1_1079 = _out_rofireMux_T_286; // @[RegisterRouter.scala:87:24] assign out_roready_1_1080 = _out_rofireMux_T_286; // @[RegisterRouter.scala:87:24] assign out_roready_1_1081 = _out_rofireMux_T_286; // @[RegisterRouter.scala:87:24] assign out_roready_1_1082 = _out_rofireMux_T_286; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_287 = ~_out_T_1877; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_289 = _out_rofireMux_T_260 & out_backSel_7_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_290 = _out_rofireMux_T_289 & _out_T_1823; // @[RegisterRouter.scala:87:24] assign out_roready_1_859 = _out_rofireMux_T_290; // @[RegisterRouter.scala:87:24] assign out_roready_1_860 = _out_rofireMux_T_290; // @[RegisterRouter.scala:87:24] assign out_roready_1_861 = _out_rofireMux_T_290; // @[RegisterRouter.scala:87:24] assign out_roready_1_862 = _out_rofireMux_T_290; // @[RegisterRouter.scala:87:24] assign out_roready_1_863 = _out_rofireMux_T_290; // @[RegisterRouter.scala:87:24] assign out_roready_1_864 = _out_rofireMux_T_290; // @[RegisterRouter.scala:87:24] assign out_roready_1_865 = _out_rofireMux_T_290; // @[RegisterRouter.scala:87:24] assign out_roready_1_866 = _out_rofireMux_T_290; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_291 = ~_out_T_1823; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_293 = _out_rofireMux_T_260 & out_backSel_8_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_294 = _out_rofireMux_T_293 & _out_T_1743; // @[RegisterRouter.scala:87:24] assign out_roready_1_545 = _out_rofireMux_T_294; // @[RegisterRouter.scala:87:24] assign out_roready_1_546 = _out_rofireMux_T_294; // @[RegisterRouter.scala:87:24] assign out_roready_1_547 = _out_rofireMux_T_294; // @[RegisterRouter.scala:87:24] assign out_roready_1_548 = _out_rofireMux_T_294; // @[RegisterRouter.scala:87:24] assign out_roready_1_549 = _out_rofireMux_T_294; // @[RegisterRouter.scala:87:24] assign out_roready_1_550 = _out_rofireMux_T_294; // @[RegisterRouter.scala:87:24] assign out_roready_1_551 = _out_rofireMux_T_294; // @[RegisterRouter.scala:87:24] assign out_roready_1_552 = _out_rofireMux_T_294; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_295 = ~_out_T_1743; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_297 = _out_rofireMux_T_260 & out_backSel_9_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_298 = _out_rofireMux_T_297 & _out_T_1667; // @[RegisterRouter.scala:87:24] assign out_roready_1_264 = _out_rofireMux_T_298; // @[RegisterRouter.scala:87:24] assign out_roready_1_265 = _out_rofireMux_T_298; // @[RegisterRouter.scala:87:24] assign out_roready_1_266 = _out_rofireMux_T_298; // @[RegisterRouter.scala:87:24] assign out_roready_1_267 = _out_rofireMux_T_298; // @[RegisterRouter.scala:87:24] assign out_roready_1_268 = _out_rofireMux_T_298; // @[RegisterRouter.scala:87:24] assign out_roready_1_269 = _out_rofireMux_T_298; // @[RegisterRouter.scala:87:24] assign out_roready_1_270 = _out_rofireMux_T_298; // @[RegisterRouter.scala:87:24] assign out_roready_1_271 = _out_rofireMux_T_298; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_299 = ~_out_T_1667; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_301 = _out_rofireMux_T_260 & out_backSel_10_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_302 = _out_rofireMux_T_301 & _out_T_1725; // @[RegisterRouter.scala:87:24] assign out_roready_1_483 = _out_rofireMux_T_302; // @[RegisterRouter.scala:87:24] assign out_roready_1_484 = _out_rofireMux_T_302; // @[RegisterRouter.scala:87:24] assign out_roready_1_485 = _out_rofireMux_T_302; // @[RegisterRouter.scala:87:24] assign out_roready_1_486 = _out_rofireMux_T_302; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_303 = ~_out_T_1725; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_305 = _out_rofireMux_T_260 & out_backSel_11_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_306 = _out_rofireMux_T_305; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_309 = _out_rofireMux_T_260 & out_backSel_12_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_310 = _out_rofireMux_T_309; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_313 = _out_rofireMux_T_260 & out_backSel_13_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_314 = _out_rofireMux_T_313; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_317 = _out_rofireMux_T_260 & out_backSel_14_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_318 = _out_rofireMux_T_317; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_321 = _out_rofireMux_T_260 & out_backSel_15_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_322 = _out_rofireMux_T_321; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_325 = _out_rofireMux_T_260 & out_backSel_16_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_326 = _out_rofireMux_T_325; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_329 = _out_rofireMux_T_260 & out_backSel_17_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_330 = _out_rofireMux_T_329; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_333 = _out_rofireMux_T_260 & out_backSel_18_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_334 = _out_rofireMux_T_333; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_337 = _out_rofireMux_T_260 & out_backSel_19_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_338 = _out_rofireMux_T_337; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_341 = _out_rofireMux_T_260 & out_backSel_20_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_342 = _out_rofireMux_T_341; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_345 = _out_rofireMux_T_260 & out_backSel_21_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_346 = _out_rofireMux_T_345; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_349 = _out_rofireMux_T_260 & out_backSel_22_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_350 = _out_rofireMux_T_349; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_353 = _out_rofireMux_T_260 & out_backSel_23_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_354 = _out_rofireMux_T_353; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_357 = _out_rofireMux_T_260 & out_backSel_24_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_358 = _out_rofireMux_T_357; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_361 = _out_rofireMux_T_260 & out_backSel_25_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_362 = _out_rofireMux_T_361; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_365 = _out_rofireMux_T_260 & out_backSel_26_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_366 = _out_rofireMux_T_365; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_369 = _out_rofireMux_T_260 & out_backSel_27_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_370 = _out_rofireMux_T_369; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_373 = _out_rofireMux_T_260 & out_backSel_28_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_374 = _out_rofireMux_T_373; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_377 = _out_rofireMux_T_260 & out_backSel_29_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_378 = _out_rofireMux_T_377; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_381 = _out_rofireMux_T_260 & out_backSel_30_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_382 = _out_rofireMux_T_381; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_385 = _out_rofireMux_T_260 & out_backSel_31_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_386 = _out_rofireMux_T_385; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_389 = _out_rofireMux_T_260 & out_backSel_32_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_390 = _out_rofireMux_T_389 & _out_T_1739; // @[RegisterRouter.scala:87:24] assign out_roready_1_535 = _out_rofireMux_T_390; // @[RegisterRouter.scala:87:24] assign out_roready_1_536 = _out_rofireMux_T_390; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_391 = ~_out_T_1739; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_393 = _out_rofireMux_T_260 & out_backSel_33_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_394 = _out_rofireMux_T_393 & _out_T_1689; // @[RegisterRouter.scala:87:24] assign out_roready_1_352 = _out_rofireMux_T_394; // @[RegisterRouter.scala:87:24] assign out_roready_1_353 = _out_rofireMux_T_394; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_395 = ~_out_T_1689; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_397 = _out_rofireMux_T_260 & out_backSel_34_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_398 = _out_rofireMux_T_397; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_401 = _out_rofireMux_T_260 & out_backSel_35_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_402 = _out_rofireMux_T_401; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_405 = _out_rofireMux_T_260 & out_backSel_36_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_406 = _out_rofireMux_T_405; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_409 = _out_rofireMux_T_260 & out_backSel_37_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_410 = _out_rofireMux_T_409; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_413 = _out_rofireMux_T_260 & out_backSel_38_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_414 = _out_rofireMux_T_413; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_417 = _out_rofireMux_T_260 & out_backSel_39_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_418 = _out_rofireMux_T_417; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_421 = _out_rofireMux_T_260 & out_backSel_40_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_422 = _out_rofireMux_T_421; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_425 = _out_rofireMux_T_260 & out_backSel_41_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_426 = _out_rofireMux_T_425; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_429 = _out_rofireMux_T_260 & out_backSel_42_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_430 = _out_rofireMux_T_429; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_433 = _out_rofireMux_T_260 & out_backSel_43_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_434 = _out_rofireMux_T_433; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_437 = _out_rofireMux_T_260 & out_backSel_44_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_438 = _out_rofireMux_T_437; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_441 = _out_rofireMux_T_260 & out_backSel_45_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_442 = _out_rofireMux_T_441; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_445 = _out_rofireMux_T_260 & out_backSel_46_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_446 = _out_rofireMux_T_445; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_449 = _out_rofireMux_T_260 & out_backSel_47_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_450 = _out_rofireMux_T_449; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_453 = _out_rofireMux_T_260 & out_backSel_48_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_454 = _out_rofireMux_T_453; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_457 = _out_rofireMux_T_260 & out_backSel_49_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_458 = _out_rofireMux_T_457; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_461 = _out_rofireMux_T_260 & out_backSel_50_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_462 = _out_rofireMux_T_461; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_465 = _out_rofireMux_T_260 & out_backSel_51_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_466 = _out_rofireMux_T_465; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_469 = _out_rofireMux_T_260 & out_backSel_52_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_470 = _out_rofireMux_T_469; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_473 = _out_rofireMux_T_260 & out_backSel_53_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_474 = _out_rofireMux_T_473; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_477 = _out_rofireMux_T_260 & out_backSel_54_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_478 = _out_rofireMux_T_477; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_481 = _out_rofireMux_T_260 & out_backSel_55_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_482 = _out_rofireMux_T_481; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_485 = _out_rofireMux_T_260 & out_backSel_56_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_486 = _out_rofireMux_T_485; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_489 = _out_rofireMux_T_260 & out_backSel_57_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_490 = _out_rofireMux_T_489; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_493 = _out_rofireMux_T_260 & out_backSel_58_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_494 = _out_rofireMux_T_493; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_497 = _out_rofireMux_T_260 & out_backSel_59_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_498 = _out_rofireMux_T_497; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_501 = _out_rofireMux_T_260 & out_backSel_60_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_502 = _out_rofireMux_T_501; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_505 = _out_rofireMux_T_260 & out_backSel_61_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_506 = _out_rofireMux_T_505; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_509 = _out_rofireMux_T_260 & out_backSel_62_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_510 = _out_rofireMux_T_509; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_513 = _out_rofireMux_T_260 & out_backSel_63_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_514 = _out_rofireMux_T_513; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_517 = _out_rofireMux_T_260 & out_backSel_64; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_518 = _out_rofireMux_T_517; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_521 = _out_rofireMux_T_260 & out_backSel_65; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_522 = _out_rofireMux_T_521; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_525 = _out_rofireMux_T_260 & out_backSel_66; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_526 = _out_rofireMux_T_525; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_529 = _out_rofireMux_T_260 & out_backSel_67; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_530 = _out_rofireMux_T_529; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_533 = _out_rofireMux_T_260 & out_backSel_68; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_534 = _out_rofireMux_T_533; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_537 = _out_rofireMux_T_260 & out_backSel_69; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_538 = _out_rofireMux_T_537; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_541 = _out_rofireMux_T_260 & out_backSel_70; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_542 = _out_rofireMux_T_541; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_545 = _out_rofireMux_T_260 & out_backSel_71; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_546 = _out_rofireMux_T_545; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_549 = _out_rofireMux_T_260 & out_backSel_72; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_550 = _out_rofireMux_T_549; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_553 = _out_rofireMux_T_260 & out_backSel_73; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_554 = _out_rofireMux_T_553; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_557 = _out_rofireMux_T_260 & out_backSel_74; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_558 = _out_rofireMux_T_557; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_561 = _out_rofireMux_T_260 & out_backSel_75; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_562 = _out_rofireMux_T_561; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_565 = _out_rofireMux_T_260 & out_backSel_76; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_566 = _out_rofireMux_T_565; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_569 = _out_rofireMux_T_260 & out_backSel_77; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_570 = _out_rofireMux_T_569; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_573 = _out_rofireMux_T_260 & out_backSel_78; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_574 = _out_rofireMux_T_573; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_577 = _out_rofireMux_T_260 & out_backSel_79; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_578 = _out_rofireMux_T_577; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_581 = _out_rofireMux_T_260 & out_backSel_80; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_582 = _out_rofireMux_T_581; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_585 = _out_rofireMux_T_260 & out_backSel_81; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_586 = _out_rofireMux_T_585; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_589 = _out_rofireMux_T_260 & out_backSel_82; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_590 = _out_rofireMux_T_589; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_593 = _out_rofireMux_T_260 & out_backSel_83; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_594 = _out_rofireMux_T_593; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_597 = _out_rofireMux_T_260 & out_backSel_84; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_598 = _out_rofireMux_T_597; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_601 = _out_rofireMux_T_260 & out_backSel_85; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_602 = _out_rofireMux_T_601; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_605 = _out_rofireMux_T_260 & out_backSel_86; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_606 = _out_rofireMux_T_605; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_609 = _out_rofireMux_T_260 & out_backSel_87; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_610 = _out_rofireMux_T_609; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_613 = _out_rofireMux_T_260 & out_backSel_88; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_614 = _out_rofireMux_T_613; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_617 = _out_rofireMux_T_260 & out_backSel_89; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_618 = _out_rofireMux_T_617; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_621 = _out_rofireMux_T_260 & out_backSel_90; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_622 = _out_rofireMux_T_621; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_625 = _out_rofireMux_T_260 & out_backSel_91; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_626 = _out_rofireMux_T_625; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_629 = _out_rofireMux_T_260 & out_backSel_92; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_630 = _out_rofireMux_T_629; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_633 = _out_rofireMux_T_260 & out_backSel_93; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_634 = _out_rofireMux_T_633; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_637 = _out_rofireMux_T_260 & out_backSel_94; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_638 = _out_rofireMux_T_637; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_641 = _out_rofireMux_T_260 & out_backSel_95; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_642 = _out_rofireMux_T_641; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_645 = _out_rofireMux_T_260 & out_backSel_96; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_646 = _out_rofireMux_T_645 & _out_T_1713; // @[RegisterRouter.scala:87:24] assign out_roready_1_442 = _out_rofireMux_T_646; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_647 = ~_out_T_1713; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_649 = _out_rofireMux_T_260 & out_backSel_97; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_650 = _out_rofireMux_T_649; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_653 = _out_rofireMux_T_260 & out_backSel_98; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_654 = _out_rofireMux_T_653; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_657 = _out_rofireMux_T_260 & out_backSel_99; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_658 = _out_rofireMux_T_657; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_661 = _out_rofireMux_T_260 & out_backSel_100; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_662 = _out_rofireMux_T_661; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_665 = _out_rofireMux_T_260 & out_backSel_101; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_666 = _out_rofireMux_T_665; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_669 = _out_rofireMux_T_260 & out_backSel_102; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_670 = _out_rofireMux_T_669; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_673 = _out_rofireMux_T_260 & out_backSel_103; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_674 = _out_rofireMux_T_673 & _out_T_1781; // @[RegisterRouter.scala:87:24] assign out_roready_1_697 = _out_rofireMux_T_674; // @[RegisterRouter.scala:87:24] assign out_roready_1_698 = _out_rofireMux_T_674; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_675 = ~_out_T_1781; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_677 = _out_rofireMux_T_260 & out_backSel_104; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_678 = _out_rofireMux_T_677 & _out_T_1841; // @[RegisterRouter.scala:87:24] assign out_roready_1_931 = _out_rofireMux_T_678; // @[RegisterRouter.scala:87:24] assign out_roready_1_932 = _out_rofireMux_T_678; // @[RegisterRouter.scala:87:24] assign out_roready_1_933 = _out_rofireMux_T_678; // @[RegisterRouter.scala:87:24] assign out_roready_1_934 = _out_rofireMux_T_678; // @[RegisterRouter.scala:87:24] assign out_roready_1_935 = _out_rofireMux_T_678; // @[RegisterRouter.scala:87:24] assign out_roready_1_936 = _out_rofireMux_T_678; // @[RegisterRouter.scala:87:24] assign out_roready_1_937 = _out_rofireMux_T_678; // @[RegisterRouter.scala:87:24] assign out_roready_1_938 = _out_rofireMux_T_678; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_679 = ~_out_T_1841; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_681 = _out_rofireMux_T_260 & out_backSel_105; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_682 = _out_rofireMux_T_681 & _out_T_1733; // @[RegisterRouter.scala:87:24] assign out_roready_1_511 = _out_rofireMux_T_682; // @[RegisterRouter.scala:87:24] assign out_roready_1_512 = _out_rofireMux_T_682; // @[RegisterRouter.scala:87:24] assign out_roready_1_513 = _out_rofireMux_T_682; // @[RegisterRouter.scala:87:24] assign out_roready_1_514 = _out_rofireMux_T_682; // @[RegisterRouter.scala:87:24] assign out_roready_1_515 = _out_rofireMux_T_682; // @[RegisterRouter.scala:87:24] assign out_roready_1_516 = _out_rofireMux_T_682; // @[RegisterRouter.scala:87:24] assign out_roready_1_517 = _out_rofireMux_T_682; // @[RegisterRouter.scala:87:24] assign out_roready_1_518 = _out_rofireMux_T_682; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_683 = ~_out_T_1733; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_685 = _out_rofireMux_T_260 & out_backSel_106; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_686 = _out_rofireMux_T_685 & _out_T_1649; // @[RegisterRouter.scala:87:24] assign out_roready_1_192 = _out_rofireMux_T_686; // @[RegisterRouter.scala:87:24] assign out_roready_1_193 = _out_rofireMux_T_686; // @[RegisterRouter.scala:87:24] assign out_roready_1_194 = _out_rofireMux_T_686; // @[RegisterRouter.scala:87:24] assign out_roready_1_195 = _out_rofireMux_T_686; // @[RegisterRouter.scala:87:24] assign out_roready_1_196 = _out_rofireMux_T_686; // @[RegisterRouter.scala:87:24] assign out_roready_1_197 = _out_rofireMux_T_686; // @[RegisterRouter.scala:87:24] assign out_roready_1_198 = _out_rofireMux_T_686; // @[RegisterRouter.scala:87:24] assign out_roready_1_199 = _out_rofireMux_T_686; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_687 = ~_out_T_1649; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_689 = _out_rofireMux_T_260 & out_backSel_107; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_690 = _out_rofireMux_T_689 & _out_T_1881; // @[RegisterRouter.scala:87:24] assign out_roready_1_1091 = _out_rofireMux_T_690; // @[RegisterRouter.scala:87:24] assign out_roready_1_1092 = _out_rofireMux_T_690; // @[RegisterRouter.scala:87:24] assign out_roready_1_1093 = _out_rofireMux_T_690; // @[RegisterRouter.scala:87:24] assign out_roready_1_1094 = _out_rofireMux_T_690; // @[RegisterRouter.scala:87:24] assign out_roready_1_1095 = _out_rofireMux_T_690; // @[RegisterRouter.scala:87:24] assign out_roready_1_1096 = _out_rofireMux_T_690; // @[RegisterRouter.scala:87:24] assign out_roready_1_1097 = _out_rofireMux_T_690; // @[RegisterRouter.scala:87:24] assign out_roready_1_1098 = _out_rofireMux_T_690; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_691 = ~_out_T_1881; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_693 = _out_rofireMux_T_260 & out_backSel_108; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_694 = _out_rofireMux_T_693 & _out_T_1791; // @[RegisterRouter.scala:87:24] assign out_roready_1_731 = _out_rofireMux_T_694; // @[RegisterRouter.scala:87:24] assign out_roready_1_732 = _out_rofireMux_T_694; // @[RegisterRouter.scala:87:24] assign out_roready_1_733 = _out_rofireMux_T_694; // @[RegisterRouter.scala:87:24] assign out_roready_1_734 = _out_rofireMux_T_694; // @[RegisterRouter.scala:87:24] assign out_roready_1_735 = _out_rofireMux_T_694; // @[RegisterRouter.scala:87:24] assign out_roready_1_736 = _out_rofireMux_T_694; // @[RegisterRouter.scala:87:24] assign out_roready_1_737 = _out_rofireMux_T_694; // @[RegisterRouter.scala:87:24] assign out_roready_1_738 = _out_rofireMux_T_694; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_695 = ~_out_T_1791; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_697 = _out_rofireMux_T_260 & out_backSel_109; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_698 = _out_rofireMux_T_697 & _out_T_1715; // @[RegisterRouter.scala:87:24] assign out_roready_1_443 = _out_rofireMux_T_698; // @[RegisterRouter.scala:87:24] assign out_roready_1_444 = _out_rofireMux_T_698; // @[RegisterRouter.scala:87:24] assign out_roready_1_445 = _out_rofireMux_T_698; // @[RegisterRouter.scala:87:24] assign out_roready_1_446 = _out_rofireMux_T_698; // @[RegisterRouter.scala:87:24] assign out_roready_1_447 = _out_rofireMux_T_698; // @[RegisterRouter.scala:87:24] assign out_roready_1_448 = _out_rofireMux_T_698; // @[RegisterRouter.scala:87:24] assign out_roready_1_449 = _out_rofireMux_T_698; // @[RegisterRouter.scala:87:24] assign out_roready_1_450 = _out_rofireMux_T_698; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_699 = ~_out_T_1715; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_701 = _out_rofireMux_T_260 & out_backSel_110; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_702 = _out_rofireMux_T_701 & _out_T_1629; // @[RegisterRouter.scala:87:24] assign out_roready_1_112 = _out_rofireMux_T_702; // @[RegisterRouter.scala:87:24] assign out_roready_1_113 = _out_rofireMux_T_702; // @[RegisterRouter.scala:87:24] assign out_roready_1_114 = _out_rofireMux_T_702; // @[RegisterRouter.scala:87:24] assign out_roready_1_115 = _out_rofireMux_T_702; // @[RegisterRouter.scala:87:24] assign out_roready_1_116 = _out_rofireMux_T_702; // @[RegisterRouter.scala:87:24] assign out_roready_1_117 = _out_rofireMux_T_702; // @[RegisterRouter.scala:87:24] assign out_roready_1_118 = _out_rofireMux_T_702; // @[RegisterRouter.scala:87:24] assign out_roready_1_119 = _out_rofireMux_T_702; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_703 = ~_out_T_1629; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_705 = _out_rofireMux_T_260 & out_backSel_111; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_706 = _out_rofireMux_T_705 & _out_T_1899; // @[RegisterRouter.scala:87:24] assign out_roready_1_1163 = _out_rofireMux_T_706; // @[RegisterRouter.scala:87:24] assign out_roready_1_1164 = _out_rofireMux_T_706; // @[RegisterRouter.scala:87:24] assign out_roready_1_1165 = _out_rofireMux_T_706; // @[RegisterRouter.scala:87:24] assign out_roready_1_1166 = _out_rofireMux_T_706; // @[RegisterRouter.scala:87:24] assign out_roready_1_1167 = _out_rofireMux_T_706; // @[RegisterRouter.scala:87:24] assign out_roready_1_1168 = _out_rofireMux_T_706; // @[RegisterRouter.scala:87:24] assign out_roready_1_1169 = _out_rofireMux_T_706; // @[RegisterRouter.scala:87:24] assign out_roready_1_1170 = _out_rofireMux_T_706; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_707 = ~_out_T_1899; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_709 = _out_rofireMux_T_260 & out_backSel_112; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_710 = _out_rofireMux_T_709 & _out_T_1815; // @[RegisterRouter.scala:87:24] assign out_roready_1_827 = _out_rofireMux_T_710; // @[RegisterRouter.scala:87:24] assign out_roready_1_828 = _out_rofireMux_T_710; // @[RegisterRouter.scala:87:24] assign out_roready_1_829 = _out_rofireMux_T_710; // @[RegisterRouter.scala:87:24] assign out_roready_1_830 = _out_rofireMux_T_710; // @[RegisterRouter.scala:87:24] assign out_roready_1_831 = _out_rofireMux_T_710; // @[RegisterRouter.scala:87:24] assign out_roready_1_832 = _out_rofireMux_T_710; // @[RegisterRouter.scala:87:24] assign out_roready_1_833 = _out_rofireMux_T_710; // @[RegisterRouter.scala:87:24] assign out_roready_1_834 = _out_rofireMux_T_710; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_711 = ~_out_T_1815; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_713 = _out_rofireMux_T_260 & out_backSel_113; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_714 = _out_rofireMux_T_713 & _out_T_1771; // @[RegisterRouter.scala:87:24] assign out_roready_1_657 = _out_rofireMux_T_714; // @[RegisterRouter.scala:87:24] assign out_roready_1_658 = _out_rofireMux_T_714; // @[RegisterRouter.scala:87:24] assign out_roready_1_659 = _out_rofireMux_T_714; // @[RegisterRouter.scala:87:24] assign out_roready_1_660 = _out_rofireMux_T_714; // @[RegisterRouter.scala:87:24] assign out_roready_1_661 = _out_rofireMux_T_714; // @[RegisterRouter.scala:87:24] assign out_roready_1_662 = _out_rofireMux_T_714; // @[RegisterRouter.scala:87:24] assign out_roready_1_663 = _out_rofireMux_T_714; // @[RegisterRouter.scala:87:24] assign out_roready_1_664 = _out_rofireMux_T_714; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_715 = ~_out_T_1771; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_717 = _out_rofireMux_T_260 & out_backSel_114; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_718 = _out_rofireMux_T_717 & _out_T_1853; // @[RegisterRouter.scala:87:24] assign out_roready_1_979 = _out_rofireMux_T_718; // @[RegisterRouter.scala:87:24] assign out_roready_1_980 = _out_rofireMux_T_718; // @[RegisterRouter.scala:87:24] assign out_roready_1_981 = _out_rofireMux_T_718; // @[RegisterRouter.scala:87:24] assign out_roready_1_982 = _out_rofireMux_T_718; // @[RegisterRouter.scala:87:24] assign out_roready_1_983 = _out_rofireMux_T_718; // @[RegisterRouter.scala:87:24] assign out_roready_1_984 = _out_rofireMux_T_718; // @[RegisterRouter.scala:87:24] assign out_roready_1_985 = _out_rofireMux_T_718; // @[RegisterRouter.scala:87:24] assign out_roready_1_986 = _out_rofireMux_T_718; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_719 = ~_out_T_1853; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_721 = _out_rofireMux_T_260 & out_backSel_115; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_722 = _out_rofireMux_T_721 & _out_T_1609; // @[RegisterRouter.scala:87:24] assign out_roready_1_32 = _out_rofireMux_T_722; // @[RegisterRouter.scala:87:24] assign out_roready_1_33 = _out_rofireMux_T_722; // @[RegisterRouter.scala:87:24] assign out_roready_1_34 = _out_rofireMux_T_722; // @[RegisterRouter.scala:87:24] assign out_roready_1_35 = _out_rofireMux_T_722; // @[RegisterRouter.scala:87:24] assign out_roready_1_36 = _out_rofireMux_T_722; // @[RegisterRouter.scala:87:24] assign out_roready_1_37 = _out_rofireMux_T_722; // @[RegisterRouter.scala:87:24] assign out_roready_1_38 = _out_rofireMux_T_722; // @[RegisterRouter.scala:87:24] assign out_roready_1_39 = _out_rofireMux_T_722; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_723 = ~_out_T_1609; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_725 = _out_rofireMux_T_260 & out_backSel_116; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_726 = _out_rofireMux_T_725; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_729 = _out_rofireMux_T_260 & out_backSel_117; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_730 = _out_rofireMux_T_729; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_733 = _out_rofireMux_T_260 & out_backSel_118; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_734 = _out_rofireMux_T_733; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_737 = _out_rofireMux_T_260 & out_backSel_119; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_738 = _out_rofireMux_T_737; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_741 = _out_rofireMux_T_260 & out_backSel_120; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_742 = _out_rofireMux_T_741; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_745 = _out_rofireMux_T_260 & out_backSel_121; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_746 = _out_rofireMux_T_745; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_749 = _out_rofireMux_T_260 & out_backSel_122; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_750 = _out_rofireMux_T_749; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_753 = _out_rofireMux_T_260 & out_backSel_123; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_754 = _out_rofireMux_T_753; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_757 = _out_rofireMux_T_260 & out_backSel_124; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_758 = _out_rofireMux_T_757; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_761 = _out_rofireMux_T_260 & out_backSel_125; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_762 = _out_rofireMux_T_761; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_765 = _out_rofireMux_T_260 & out_backSel_126; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_766 = _out_rofireMux_T_765; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_769 = _out_rofireMux_T_260 & out_backSel_127; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_770 = _out_rofireMux_T_769; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_773 = _out_rofireMux_T_260 & out_backSel_128; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_774 = _out_rofireMux_T_773 & _out_T_1729; // @[RegisterRouter.scala:87:24] assign out_roready_1_495 = _out_rofireMux_T_774; // @[RegisterRouter.scala:87:24] assign out_roready_1_496 = _out_rofireMux_T_774; // @[RegisterRouter.scala:87:24] assign out_roready_1_497 = _out_rofireMux_T_774; // @[RegisterRouter.scala:87:24] assign out_roready_1_498 = _out_rofireMux_T_774; // @[RegisterRouter.scala:87:24] assign out_roready_1_499 = _out_rofireMux_T_774; // @[RegisterRouter.scala:87:24] assign out_roready_1_500 = _out_rofireMux_T_774; // @[RegisterRouter.scala:87:24] assign out_roready_1_501 = _out_rofireMux_T_774; // @[RegisterRouter.scala:87:24] assign out_roready_1_502 = _out_rofireMux_T_774; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_775 = ~_out_T_1729; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_777 = _out_rofireMux_T_260 & out_backSel_129; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_778 = _out_rofireMux_T_777 & _out_T_1721; // @[RegisterRouter.scala:87:24] assign out_roready_1_467 = _out_rofireMux_T_778; // @[RegisterRouter.scala:87:24] assign out_roready_1_468 = _out_rofireMux_T_778; // @[RegisterRouter.scala:87:24] assign out_roready_1_469 = _out_rofireMux_T_778; // @[RegisterRouter.scala:87:24] assign out_roready_1_470 = _out_rofireMux_T_778; // @[RegisterRouter.scala:87:24] assign out_roready_1_471 = _out_rofireMux_T_778; // @[RegisterRouter.scala:87:24] assign out_roready_1_472 = _out_rofireMux_T_778; // @[RegisterRouter.scala:87:24] assign out_roready_1_473 = _out_rofireMux_T_778; // @[RegisterRouter.scala:87:24] assign out_roready_1_474 = _out_rofireMux_T_778; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_779 = ~_out_T_1721; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_781 = _out_rofireMux_T_260 & out_backSel_130; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_782 = _out_rofireMux_T_781 & _out_T_1797; // @[RegisterRouter.scala:87:24] assign out_roready_1_755 = _out_rofireMux_T_782; // @[RegisterRouter.scala:87:24] assign out_roready_1_756 = _out_rofireMux_T_782; // @[RegisterRouter.scala:87:24] assign out_roready_1_757 = _out_rofireMux_T_782; // @[RegisterRouter.scala:87:24] assign out_roready_1_758 = _out_rofireMux_T_782; // @[RegisterRouter.scala:87:24] assign out_roready_1_759 = _out_rofireMux_T_782; // @[RegisterRouter.scala:87:24] assign out_roready_1_760 = _out_rofireMux_T_782; // @[RegisterRouter.scala:87:24] assign out_roready_1_761 = _out_rofireMux_T_782; // @[RegisterRouter.scala:87:24] assign out_roready_1_762 = _out_rofireMux_T_782; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_783 = ~_out_T_1797; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_785 = _out_rofireMux_T_260 & out_backSel_131; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_786 = _out_rofireMux_T_785 & _out_T_1891; // @[RegisterRouter.scala:87:24] assign out_roready_1_1131 = _out_rofireMux_T_786; // @[RegisterRouter.scala:87:24] assign out_roready_1_1132 = _out_rofireMux_T_786; // @[RegisterRouter.scala:87:24] assign out_roready_1_1133 = _out_rofireMux_T_786; // @[RegisterRouter.scala:87:24] assign out_roready_1_1134 = _out_rofireMux_T_786; // @[RegisterRouter.scala:87:24] assign out_roready_1_1135 = _out_rofireMux_T_786; // @[RegisterRouter.scala:87:24] assign out_roready_1_1136 = _out_rofireMux_T_786; // @[RegisterRouter.scala:87:24] assign out_roready_1_1137 = _out_rofireMux_T_786; // @[RegisterRouter.scala:87:24] assign out_roready_1_1138 = _out_rofireMux_T_786; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_787 = ~_out_T_1891; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_789 = _out_rofireMux_T_260 & out_backSel_132; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_790 = _out_rofireMux_T_789 & _out_T_1661; // @[RegisterRouter.scala:87:24] assign out_roready_1_240 = _out_rofireMux_T_790; // @[RegisterRouter.scala:87:24] assign out_roready_1_241 = _out_rofireMux_T_790; // @[RegisterRouter.scala:87:24] assign out_roready_1_242 = _out_rofireMux_T_790; // @[RegisterRouter.scala:87:24] assign out_roready_1_243 = _out_rofireMux_T_790; // @[RegisterRouter.scala:87:24] assign out_roready_1_244 = _out_rofireMux_T_790; // @[RegisterRouter.scala:87:24] assign out_roready_1_245 = _out_rofireMux_T_790; // @[RegisterRouter.scala:87:24] assign out_roready_1_246 = _out_rofireMux_T_790; // @[RegisterRouter.scala:87:24] assign out_roready_1_247 = _out_rofireMux_T_790; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_791 = ~_out_T_1661; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_793 = _out_rofireMux_T_260 & out_backSel_133; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_794 = _out_rofireMux_T_793 & _out_T_1663; // @[RegisterRouter.scala:87:24] assign out_roready_1_248 = _out_rofireMux_T_794; // @[RegisterRouter.scala:87:24] assign out_roready_1_249 = _out_rofireMux_T_794; // @[RegisterRouter.scala:87:24] assign out_roready_1_250 = _out_rofireMux_T_794; // @[RegisterRouter.scala:87:24] assign out_roready_1_251 = _out_rofireMux_T_794; // @[RegisterRouter.scala:87:24] assign out_roready_1_252 = _out_rofireMux_T_794; // @[RegisterRouter.scala:87:24] assign out_roready_1_253 = _out_rofireMux_T_794; // @[RegisterRouter.scala:87:24] assign out_roready_1_254 = _out_rofireMux_T_794; // @[RegisterRouter.scala:87:24] assign out_roready_1_255 = _out_rofireMux_T_794; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_795 = ~_out_T_1663; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_797 = _out_rofireMux_T_260 & out_backSel_134; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_798 = _out_rofireMux_T_797 & _out_T_1723; // @[RegisterRouter.scala:87:24] assign out_roready_1_475 = _out_rofireMux_T_798; // @[RegisterRouter.scala:87:24] assign out_roready_1_476 = _out_rofireMux_T_798; // @[RegisterRouter.scala:87:24] assign out_roready_1_477 = _out_rofireMux_T_798; // @[RegisterRouter.scala:87:24] assign out_roready_1_478 = _out_rofireMux_T_798; // @[RegisterRouter.scala:87:24] assign out_roready_1_479 = _out_rofireMux_T_798; // @[RegisterRouter.scala:87:24] assign out_roready_1_480 = _out_rofireMux_T_798; // @[RegisterRouter.scala:87:24] assign out_roready_1_481 = _out_rofireMux_T_798; // @[RegisterRouter.scala:87:24] assign out_roready_1_482 = _out_rofireMux_T_798; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_799 = ~_out_T_1723; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_801 = _out_rofireMux_T_260 & out_backSel_135; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_802 = _out_rofireMux_T_801 & _out_T_1801; // @[RegisterRouter.scala:87:24] assign out_roready_1_771 = _out_rofireMux_T_802; // @[RegisterRouter.scala:87:24] assign out_roready_1_772 = _out_rofireMux_T_802; // @[RegisterRouter.scala:87:24] assign out_roready_1_773 = _out_rofireMux_T_802; // @[RegisterRouter.scala:87:24] assign out_roready_1_774 = _out_rofireMux_T_802; // @[RegisterRouter.scala:87:24] assign out_roready_1_775 = _out_rofireMux_T_802; // @[RegisterRouter.scala:87:24] assign out_roready_1_776 = _out_rofireMux_T_802; // @[RegisterRouter.scala:87:24] assign out_roready_1_777 = _out_rofireMux_T_802; // @[RegisterRouter.scala:87:24] assign out_roready_1_778 = _out_rofireMux_T_802; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_803 = ~_out_T_1801; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_805 = _out_rofireMux_T_260 & out_backSel_136; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_806 = _out_rofireMux_T_805 & _out_T_1883; // @[RegisterRouter.scala:87:24] assign out_roready_1_1099 = _out_rofireMux_T_806; // @[RegisterRouter.scala:87:24] assign out_roready_1_1100 = _out_rofireMux_T_806; // @[RegisterRouter.scala:87:24] assign out_roready_1_1101 = _out_rofireMux_T_806; // @[RegisterRouter.scala:87:24] assign out_roready_1_1102 = _out_rofireMux_T_806; // @[RegisterRouter.scala:87:24] assign out_roready_1_1103 = _out_rofireMux_T_806; // @[RegisterRouter.scala:87:24] assign out_roready_1_1104 = _out_rofireMux_T_806; // @[RegisterRouter.scala:87:24] assign out_roready_1_1105 = _out_rofireMux_T_806; // @[RegisterRouter.scala:87:24] assign out_roready_1_1106 = _out_rofireMux_T_806; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_807 = ~_out_T_1883; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_809 = _out_rofireMux_T_260 & out_backSel_137; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_810 = _out_rofireMux_T_809 & _out_T_1685; // @[RegisterRouter.scala:87:24] assign out_roready_1_336 = _out_rofireMux_T_810; // @[RegisterRouter.scala:87:24] assign out_roready_1_337 = _out_rofireMux_T_810; // @[RegisterRouter.scala:87:24] assign out_roready_1_338 = _out_rofireMux_T_810; // @[RegisterRouter.scala:87:24] assign out_roready_1_339 = _out_rofireMux_T_810; // @[RegisterRouter.scala:87:24] assign out_roready_1_340 = _out_rofireMux_T_810; // @[RegisterRouter.scala:87:24] assign out_roready_1_341 = _out_rofireMux_T_810; // @[RegisterRouter.scala:87:24] assign out_roready_1_342 = _out_rofireMux_T_810; // @[RegisterRouter.scala:87:24] assign out_roready_1_343 = _out_rofireMux_T_810; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_811 = ~_out_T_1685; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_813 = _out_rofireMux_T_260 & out_backSel_138; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_814 = _out_rofireMux_T_813 & _out_T_1601; // @[RegisterRouter.scala:87:24] assign out_roready_1_0 = _out_rofireMux_T_814; // @[RegisterRouter.scala:87:24] assign out_roready_1_1 = _out_rofireMux_T_814; // @[RegisterRouter.scala:87:24] assign out_roready_1_2 = _out_rofireMux_T_814; // @[RegisterRouter.scala:87:24] assign out_roready_1_3 = _out_rofireMux_T_814; // @[RegisterRouter.scala:87:24] assign out_roready_1_4 = _out_rofireMux_T_814; // @[RegisterRouter.scala:87:24] assign out_roready_1_5 = _out_rofireMux_T_814; // @[RegisterRouter.scala:87:24] assign out_roready_1_6 = _out_rofireMux_T_814; // @[RegisterRouter.scala:87:24] assign out_roready_1_7 = _out_rofireMux_T_814; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_815 = ~_out_T_1601; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_817 = _out_rofireMux_T_260 & out_backSel_139; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_818 = _out_rofireMux_T_817 & _out_T_1857; // @[RegisterRouter.scala:87:24] assign out_roready_1_995 = _out_rofireMux_T_818; // @[RegisterRouter.scala:87:24] assign out_roready_1_996 = _out_rofireMux_T_818; // @[RegisterRouter.scala:87:24] assign out_roready_1_997 = _out_rofireMux_T_818; // @[RegisterRouter.scala:87:24] assign out_roready_1_998 = _out_rofireMux_T_818; // @[RegisterRouter.scala:87:24] assign out_roready_1_999 = _out_rofireMux_T_818; // @[RegisterRouter.scala:87:24] assign out_roready_1_1000 = _out_rofireMux_T_818; // @[RegisterRouter.scala:87:24] assign out_roready_1_1001 = _out_rofireMux_T_818; // @[RegisterRouter.scala:87:24] assign out_roready_1_1002 = _out_rofireMux_T_818; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_819 = ~_out_T_1857; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_821 = _out_rofireMux_T_260 & out_backSel_140; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_822 = _out_rofireMux_T_821 & _out_T_1783; // @[RegisterRouter.scala:87:24] assign out_roready_1_699 = _out_rofireMux_T_822; // @[RegisterRouter.scala:87:24] assign out_roready_1_700 = _out_rofireMux_T_822; // @[RegisterRouter.scala:87:24] assign out_roready_1_701 = _out_rofireMux_T_822; // @[RegisterRouter.scala:87:24] assign out_roready_1_702 = _out_rofireMux_T_822; // @[RegisterRouter.scala:87:24] assign out_roready_1_703 = _out_rofireMux_T_822; // @[RegisterRouter.scala:87:24] assign out_roready_1_704 = _out_rofireMux_T_822; // @[RegisterRouter.scala:87:24] assign out_roready_1_705 = _out_rofireMux_T_822; // @[RegisterRouter.scala:87:24] assign out_roready_1_706 = _out_rofireMux_T_822; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_823 = ~_out_T_1783; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_825 = _out_rofireMux_T_260 & out_backSel_141; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_826 = _out_rofireMux_T_825 & _out_T_1705; // @[RegisterRouter.scala:87:24] assign out_roready_1_410 = _out_rofireMux_T_826; // @[RegisterRouter.scala:87:24] assign out_roready_1_411 = _out_rofireMux_T_826; // @[RegisterRouter.scala:87:24] assign out_roready_1_412 = _out_rofireMux_T_826; // @[RegisterRouter.scala:87:24] assign out_roready_1_413 = _out_rofireMux_T_826; // @[RegisterRouter.scala:87:24] assign out_roready_1_414 = _out_rofireMux_T_826; // @[RegisterRouter.scala:87:24] assign out_roready_1_415 = _out_rofireMux_T_826; // @[RegisterRouter.scala:87:24] assign out_roready_1_416 = _out_rofireMux_T_826; // @[RegisterRouter.scala:87:24] assign out_roready_1_417 = _out_rofireMux_T_826; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_827 = ~_out_T_1705; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_829 = _out_rofireMux_T_260 & out_backSel_142; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_830 = _out_rofireMux_T_829 & _out_T_1617; // @[RegisterRouter.scala:87:24] assign out_roready_1_64 = _out_rofireMux_T_830; // @[RegisterRouter.scala:87:24] assign out_roready_1_65 = _out_rofireMux_T_830; // @[RegisterRouter.scala:87:24] assign out_roready_1_66 = _out_rofireMux_T_830; // @[RegisterRouter.scala:87:24] assign out_roready_1_67 = _out_rofireMux_T_830; // @[RegisterRouter.scala:87:24] assign out_roready_1_68 = _out_rofireMux_T_830; // @[RegisterRouter.scala:87:24] assign out_roready_1_69 = _out_rofireMux_T_830; // @[RegisterRouter.scala:87:24] assign out_roready_1_70 = _out_rofireMux_T_830; // @[RegisterRouter.scala:87:24] assign out_roready_1_71 = _out_rofireMux_T_830; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_831 = ~_out_T_1617; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_833 = _out_rofireMux_T_260 & out_backSel_143; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_834 = _out_rofireMux_T_833 & _out_T_1835; // @[RegisterRouter.scala:87:24] assign out_roready_1_907 = _out_rofireMux_T_834; // @[RegisterRouter.scala:87:24] assign out_roready_1_908 = _out_rofireMux_T_834; // @[RegisterRouter.scala:87:24] assign out_roready_1_909 = _out_rofireMux_T_834; // @[RegisterRouter.scala:87:24] assign out_roready_1_910 = _out_rofireMux_T_834; // @[RegisterRouter.scala:87:24] assign out_roready_1_911 = _out_rofireMux_T_834; // @[RegisterRouter.scala:87:24] assign out_roready_1_912 = _out_rofireMux_T_834; // @[RegisterRouter.scala:87:24] assign out_roready_1_913 = _out_rofireMux_T_834; // @[RegisterRouter.scala:87:24] assign out_roready_1_914 = _out_rofireMux_T_834; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_835 = ~_out_T_1835; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_837 = _out_rofireMux_T_260 & out_backSel_144; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_838 = _out_rofireMux_T_837 & _out_T_1759; // @[RegisterRouter.scala:87:24] assign out_roready_1_609 = _out_rofireMux_T_838; // @[RegisterRouter.scala:87:24] assign out_roready_1_610 = _out_rofireMux_T_838; // @[RegisterRouter.scala:87:24] assign out_roready_1_611 = _out_rofireMux_T_838; // @[RegisterRouter.scala:87:24] assign out_roready_1_612 = _out_rofireMux_T_838; // @[RegisterRouter.scala:87:24] assign out_roready_1_613 = _out_rofireMux_T_838; // @[RegisterRouter.scala:87:24] assign out_roready_1_614 = _out_rofireMux_T_838; // @[RegisterRouter.scala:87:24] assign out_roready_1_615 = _out_rofireMux_T_838; // @[RegisterRouter.scala:87:24] assign out_roready_1_616 = _out_rofireMux_T_838; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_839 = ~_out_T_1759; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_841 = _out_rofireMux_T_260 & out_backSel_145; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_842 = _out_rofireMux_T_841 & _out_T_1819; // @[RegisterRouter.scala:87:24] assign out_roready_1_843 = _out_rofireMux_T_842; // @[RegisterRouter.scala:87:24] assign out_roready_1_844 = _out_rofireMux_T_842; // @[RegisterRouter.scala:87:24] assign out_roready_1_845 = _out_rofireMux_T_842; // @[RegisterRouter.scala:87:24] assign out_roready_1_846 = _out_rofireMux_T_842; // @[RegisterRouter.scala:87:24] assign out_roready_1_847 = _out_rofireMux_T_842; // @[RegisterRouter.scala:87:24] assign out_roready_1_848 = _out_rofireMux_T_842; // @[RegisterRouter.scala:87:24] assign out_roready_1_849 = _out_rofireMux_T_842; // @[RegisterRouter.scala:87:24] assign out_roready_1_850 = _out_rofireMux_T_842; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_843 = ~_out_T_1819; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_845 = _out_rofireMux_T_260 & out_backSel_146; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_846 = _out_rofireMux_T_845 & _out_T_1869; // @[RegisterRouter.scala:87:24] assign out_roready_1_1043 = _out_rofireMux_T_846; // @[RegisterRouter.scala:87:24] assign out_roready_1_1044 = _out_rofireMux_T_846; // @[RegisterRouter.scala:87:24] assign out_roready_1_1045 = _out_rofireMux_T_846; // @[RegisterRouter.scala:87:24] assign out_roready_1_1046 = _out_rofireMux_T_846; // @[RegisterRouter.scala:87:24] assign out_roready_1_1047 = _out_rofireMux_T_846; // @[RegisterRouter.scala:87:24] assign out_roready_1_1048 = _out_rofireMux_T_846; // @[RegisterRouter.scala:87:24] assign out_roready_1_1049 = _out_rofireMux_T_846; // @[RegisterRouter.scala:87:24] assign out_roready_1_1050 = _out_rofireMux_T_846; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_847 = ~_out_T_1869; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_849 = _out_rofireMux_T_260 & out_backSel_147; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_850 = _out_rofireMux_T_849 & _out_T_1657; // @[RegisterRouter.scala:87:24] assign out_roready_1_224 = _out_rofireMux_T_850; // @[RegisterRouter.scala:87:24] assign out_roready_1_225 = _out_rofireMux_T_850; // @[RegisterRouter.scala:87:24] assign out_roready_1_226 = _out_rofireMux_T_850; // @[RegisterRouter.scala:87:24] assign out_roready_1_227 = _out_rofireMux_T_850; // @[RegisterRouter.scala:87:24] assign out_roready_1_228 = _out_rofireMux_T_850; // @[RegisterRouter.scala:87:24] assign out_roready_1_229 = _out_rofireMux_T_850; // @[RegisterRouter.scala:87:24] assign out_roready_1_230 = _out_rofireMux_T_850; // @[RegisterRouter.scala:87:24] assign out_roready_1_231 = _out_rofireMux_T_850; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_851 = ~_out_T_1657; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_853 = _out_rofireMux_T_260 & out_backSel_148; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_854 = _out_rofireMux_T_853 & _out_T_1741; // @[RegisterRouter.scala:87:24] assign out_roready_1_537 = _out_rofireMux_T_854; // @[RegisterRouter.scala:87:24] assign out_roready_1_538 = _out_rofireMux_T_854; // @[RegisterRouter.scala:87:24] assign out_roready_1_539 = _out_rofireMux_T_854; // @[RegisterRouter.scala:87:24] assign out_roready_1_540 = _out_rofireMux_T_854; // @[RegisterRouter.scala:87:24] assign out_roready_1_541 = _out_rofireMux_T_854; // @[RegisterRouter.scala:87:24] assign out_roready_1_542 = _out_rofireMux_T_854; // @[RegisterRouter.scala:87:24] assign out_roready_1_543 = _out_rofireMux_T_854; // @[RegisterRouter.scala:87:24] assign out_roready_1_544 = _out_rofireMux_T_854; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_855 = ~_out_T_1741; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_857 = _out_rofireMux_T_260 & out_backSel_149; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_858 = _out_rofireMux_T_857 & _out_T_1749; // @[RegisterRouter.scala:87:24] assign out_roready_1_569 = _out_rofireMux_T_858; // @[RegisterRouter.scala:87:24] assign out_roready_1_570 = _out_rofireMux_T_858; // @[RegisterRouter.scala:87:24] assign out_roready_1_571 = _out_rofireMux_T_858; // @[RegisterRouter.scala:87:24] assign out_roready_1_572 = _out_rofireMux_T_858; // @[RegisterRouter.scala:87:24] assign out_roready_1_573 = _out_rofireMux_T_858; // @[RegisterRouter.scala:87:24] assign out_roready_1_574 = _out_rofireMux_T_858; // @[RegisterRouter.scala:87:24] assign out_roready_1_575 = _out_rofireMux_T_858; // @[RegisterRouter.scala:87:24] assign out_roready_1_576 = _out_rofireMux_T_858; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_859 = ~_out_T_1749; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_861 = _out_rofireMux_T_260 & out_backSel_150; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_862 = _out_rofireMux_T_861 & _out_T_1821; // @[RegisterRouter.scala:87:24] assign out_roready_1_851 = _out_rofireMux_T_862; // @[RegisterRouter.scala:87:24] assign out_roready_1_852 = _out_rofireMux_T_862; // @[RegisterRouter.scala:87:24] assign out_roready_1_853 = _out_rofireMux_T_862; // @[RegisterRouter.scala:87:24] assign out_roready_1_854 = _out_rofireMux_T_862; // @[RegisterRouter.scala:87:24] assign out_roready_1_855 = _out_rofireMux_T_862; // @[RegisterRouter.scala:87:24] assign out_roready_1_856 = _out_rofireMux_T_862; // @[RegisterRouter.scala:87:24] assign out_roready_1_857 = _out_rofireMux_T_862; // @[RegisterRouter.scala:87:24] assign out_roready_1_858 = _out_rofireMux_T_862; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_863 = ~_out_T_1821; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_865 = _out_rofireMux_T_260 & out_backSel_151; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_866 = _out_rofireMux_T_865 & _out_T_1867; // @[RegisterRouter.scala:87:24] assign out_roready_1_1035 = _out_rofireMux_T_866; // @[RegisterRouter.scala:87:24] assign out_roready_1_1036 = _out_rofireMux_T_866; // @[RegisterRouter.scala:87:24] assign out_roready_1_1037 = _out_rofireMux_T_866; // @[RegisterRouter.scala:87:24] assign out_roready_1_1038 = _out_rofireMux_T_866; // @[RegisterRouter.scala:87:24] assign out_roready_1_1039 = _out_rofireMux_T_866; // @[RegisterRouter.scala:87:24] assign out_roready_1_1040 = _out_rofireMux_T_866; // @[RegisterRouter.scala:87:24] assign out_roready_1_1041 = _out_rofireMux_T_866; // @[RegisterRouter.scala:87:24] assign out_roready_1_1042 = _out_rofireMux_T_866; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_867 = ~_out_T_1867; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_869 = _out_rofireMux_T_260 & out_backSel_152; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_870 = _out_rofireMux_T_869 & _out_T_1637; // @[RegisterRouter.scala:87:24] assign out_roready_1_144 = _out_rofireMux_T_870; // @[RegisterRouter.scala:87:24] assign out_roready_1_145 = _out_rofireMux_T_870; // @[RegisterRouter.scala:87:24] assign out_roready_1_146 = _out_rofireMux_T_870; // @[RegisterRouter.scala:87:24] assign out_roready_1_147 = _out_rofireMux_T_870; // @[RegisterRouter.scala:87:24] assign out_roready_1_148 = _out_rofireMux_T_870; // @[RegisterRouter.scala:87:24] assign out_roready_1_149 = _out_rofireMux_T_870; // @[RegisterRouter.scala:87:24] assign out_roready_1_150 = _out_rofireMux_T_870; // @[RegisterRouter.scala:87:24] assign out_roready_1_151 = _out_rofireMux_T_870; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_871 = ~_out_T_1637; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_873 = _out_rofireMux_T_260 & out_backSel_153; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_874 = _out_rofireMux_T_873 & _out_T_1619; // @[RegisterRouter.scala:87:24] assign out_roready_1_72 = _out_rofireMux_T_874; // @[RegisterRouter.scala:87:24] assign out_roready_1_73 = _out_rofireMux_T_874; // @[RegisterRouter.scala:87:24] assign out_roready_1_74 = _out_rofireMux_T_874; // @[RegisterRouter.scala:87:24] assign out_roready_1_75 = _out_rofireMux_T_874; // @[RegisterRouter.scala:87:24] assign out_roready_1_76 = _out_rofireMux_T_874; // @[RegisterRouter.scala:87:24] assign out_roready_1_77 = _out_rofireMux_T_874; // @[RegisterRouter.scala:87:24] assign out_roready_1_78 = _out_rofireMux_T_874; // @[RegisterRouter.scala:87:24] assign out_roready_1_79 = _out_rofireMux_T_874; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_875 = ~_out_T_1619; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_877 = _out_rofireMux_T_260 & out_backSel_154; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_878 = _out_rofireMux_T_877 & _out_T_1831; // @[RegisterRouter.scala:87:24] assign out_roready_1_891 = _out_rofireMux_T_878; // @[RegisterRouter.scala:87:24] assign out_roready_1_892 = _out_rofireMux_T_878; // @[RegisterRouter.scala:87:24] assign out_roready_1_893 = _out_rofireMux_T_878; // @[RegisterRouter.scala:87:24] assign out_roready_1_894 = _out_rofireMux_T_878; // @[RegisterRouter.scala:87:24] assign out_roready_1_895 = _out_rofireMux_T_878; // @[RegisterRouter.scala:87:24] assign out_roready_1_896 = _out_rofireMux_T_878; // @[RegisterRouter.scala:87:24] assign out_roready_1_897 = _out_rofireMux_T_878; // @[RegisterRouter.scala:87:24] assign out_roready_1_898 = _out_rofireMux_T_878; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_879 = ~_out_T_1831; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_881 = _out_rofireMux_T_260 & out_backSel_155; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_882 = _out_rofireMux_T_881 & _out_T_1787; // @[RegisterRouter.scala:87:24] assign out_roready_1_715 = _out_rofireMux_T_882; // @[RegisterRouter.scala:87:24] assign out_roready_1_716 = _out_rofireMux_T_882; // @[RegisterRouter.scala:87:24] assign out_roready_1_717 = _out_rofireMux_T_882; // @[RegisterRouter.scala:87:24] assign out_roready_1_718 = _out_rofireMux_T_882; // @[RegisterRouter.scala:87:24] assign out_roready_1_719 = _out_rofireMux_T_882; // @[RegisterRouter.scala:87:24] assign out_roready_1_720 = _out_rofireMux_T_882; // @[RegisterRouter.scala:87:24] assign out_roready_1_721 = _out_rofireMux_T_882; // @[RegisterRouter.scala:87:24] assign out_roready_1_722 = _out_rofireMux_T_882; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_883 = ~_out_T_1787; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_885 = _out_rofireMux_T_260 & out_backSel_156; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_886 = _out_rofireMux_T_885 & _out_T_1699; // @[RegisterRouter.scala:87:24] assign out_roready_1_386 = _out_rofireMux_T_886; // @[RegisterRouter.scala:87:24] assign out_roready_1_387 = _out_rofireMux_T_886; // @[RegisterRouter.scala:87:24] assign out_roready_1_388 = _out_rofireMux_T_886; // @[RegisterRouter.scala:87:24] assign out_roready_1_389 = _out_rofireMux_T_886; // @[RegisterRouter.scala:87:24] assign out_roready_1_390 = _out_rofireMux_T_886; // @[RegisterRouter.scala:87:24] assign out_roready_1_391 = _out_rofireMux_T_886; // @[RegisterRouter.scala:87:24] assign out_roready_1_392 = _out_rofireMux_T_886; // @[RegisterRouter.scala:87:24] assign out_roready_1_393 = _out_rofireMux_T_886; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_887 = ~_out_T_1699; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_889 = _out_rofireMux_T_260 & out_backSel_157; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_890 = _out_rofireMux_T_889 & _out_T_1633; // @[RegisterRouter.scala:87:24] assign out_roready_1_128 = _out_rofireMux_T_890; // @[RegisterRouter.scala:87:24] assign out_roready_1_129 = _out_rofireMux_T_890; // @[RegisterRouter.scala:87:24] assign out_roready_1_130 = _out_rofireMux_T_890; // @[RegisterRouter.scala:87:24] assign out_roready_1_131 = _out_rofireMux_T_890; // @[RegisterRouter.scala:87:24] assign out_roready_1_132 = _out_rofireMux_T_890; // @[RegisterRouter.scala:87:24] assign out_roready_1_133 = _out_rofireMux_T_890; // @[RegisterRouter.scala:87:24] assign out_roready_1_134 = _out_rofireMux_T_890; // @[RegisterRouter.scala:87:24] assign out_roready_1_135 = _out_rofireMux_T_890; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_891 = ~_out_T_1633; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_893 = _out_rofireMux_T_260 & out_backSel_158; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_894 = _out_rofireMux_T_893 & _out_T_1849; // @[RegisterRouter.scala:87:24] assign out_roready_1_963 = _out_rofireMux_T_894; // @[RegisterRouter.scala:87:24] assign out_roready_1_964 = _out_rofireMux_T_894; // @[RegisterRouter.scala:87:24] assign out_roready_1_965 = _out_rofireMux_T_894; // @[RegisterRouter.scala:87:24] assign out_roready_1_966 = _out_rofireMux_T_894; // @[RegisterRouter.scala:87:24] assign out_roready_1_967 = _out_rofireMux_T_894; // @[RegisterRouter.scala:87:24] assign out_roready_1_968 = _out_rofireMux_T_894; // @[RegisterRouter.scala:87:24] assign out_roready_1_969 = _out_rofireMux_T_894; // @[RegisterRouter.scala:87:24] assign out_roready_1_970 = _out_rofireMux_T_894; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_895 = ~_out_T_1849; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_897 = _out_rofireMux_T_260 & out_backSel_159; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_898 = _out_rofireMux_T_897 & _out_T_1765; // @[RegisterRouter.scala:87:24] assign out_roready_1_633 = _out_rofireMux_T_898; // @[RegisterRouter.scala:87:24] assign out_roready_1_634 = _out_rofireMux_T_898; // @[RegisterRouter.scala:87:24] assign out_roready_1_635 = _out_rofireMux_T_898; // @[RegisterRouter.scala:87:24] assign out_roready_1_636 = _out_rofireMux_T_898; // @[RegisterRouter.scala:87:24] assign out_roready_1_637 = _out_rofireMux_T_898; // @[RegisterRouter.scala:87:24] assign out_roready_1_638 = _out_rofireMux_T_898; // @[RegisterRouter.scala:87:24] assign out_roready_1_639 = _out_rofireMux_T_898; // @[RegisterRouter.scala:87:24] assign out_roready_1_640 = _out_rofireMux_T_898; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_899 = ~_out_T_1765; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_901 = _out_rofireMux_T_260 & out_backSel_160; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_902 = _out_rofireMux_T_901 & _out_T_1681; // @[RegisterRouter.scala:87:24] assign out_roready_1_320 = _out_rofireMux_T_902; // @[RegisterRouter.scala:87:24] assign out_roready_1_321 = _out_rofireMux_T_902; // @[RegisterRouter.scala:87:24] assign out_roready_1_322 = _out_rofireMux_T_902; // @[RegisterRouter.scala:87:24] assign out_roready_1_323 = _out_rofireMux_T_902; // @[RegisterRouter.scala:87:24] assign out_roready_1_324 = _out_rofireMux_T_902; // @[RegisterRouter.scala:87:24] assign out_roready_1_325 = _out_rofireMux_T_902; // @[RegisterRouter.scala:87:24] assign out_roready_1_326 = _out_rofireMux_T_902; // @[RegisterRouter.scala:87:24] assign out_roready_1_327 = _out_rofireMux_T_902; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_903 = ~_out_T_1681; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_905 = _out_rofireMux_T_260 & out_backSel_161; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_906 = _out_rofireMux_T_905 & _out_T_1745; // @[RegisterRouter.scala:87:24] assign out_roready_1_553 = _out_rofireMux_T_906; // @[RegisterRouter.scala:87:24] assign out_roready_1_554 = _out_rofireMux_T_906; // @[RegisterRouter.scala:87:24] assign out_roready_1_555 = _out_rofireMux_T_906; // @[RegisterRouter.scala:87:24] assign out_roready_1_556 = _out_rofireMux_T_906; // @[RegisterRouter.scala:87:24] assign out_roready_1_557 = _out_rofireMux_T_906; // @[RegisterRouter.scala:87:24] assign out_roready_1_558 = _out_rofireMux_T_906; // @[RegisterRouter.scala:87:24] assign out_roready_1_559 = _out_rofireMux_T_906; // @[RegisterRouter.scala:87:24] assign out_roready_1_560 = _out_rofireMux_T_906; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_907 = ~_out_T_1745; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_909 = _out_rofireMux_T_260 & out_backSel_162; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_910 = _out_rofireMux_T_909 & _out_T_1809; // @[RegisterRouter.scala:87:24] assign out_roready_1_803 = _out_rofireMux_T_910; // @[RegisterRouter.scala:87:24] assign out_roready_1_804 = _out_rofireMux_T_910; // @[RegisterRouter.scala:87:24] assign out_roready_1_805 = _out_rofireMux_T_910; // @[RegisterRouter.scala:87:24] assign out_roready_1_806 = _out_rofireMux_T_910; // @[RegisterRouter.scala:87:24] assign out_roready_1_807 = _out_rofireMux_T_910; // @[RegisterRouter.scala:87:24] assign out_roready_1_808 = _out_rofireMux_T_910; // @[RegisterRouter.scala:87:24] assign out_roready_1_809 = _out_rofireMux_T_910; // @[RegisterRouter.scala:87:24] assign out_roready_1_810 = _out_rofireMux_T_910; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_911 = ~_out_T_1809; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_913 = _out_rofireMux_T_260 & out_backSel_163; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_914 = _out_rofireMux_T_913 & _out_T_1895; // @[RegisterRouter.scala:87:24] assign out_roready_1_1147 = _out_rofireMux_T_914; // @[RegisterRouter.scala:87:24] assign out_roready_1_1148 = _out_rofireMux_T_914; // @[RegisterRouter.scala:87:24] assign out_roready_1_1149 = _out_rofireMux_T_914; // @[RegisterRouter.scala:87:24] assign out_roready_1_1150 = _out_rofireMux_T_914; // @[RegisterRouter.scala:87:24] assign out_roready_1_1151 = _out_rofireMux_T_914; // @[RegisterRouter.scala:87:24] assign out_roready_1_1152 = _out_rofireMux_T_914; // @[RegisterRouter.scala:87:24] assign out_roready_1_1153 = _out_rofireMux_T_914; // @[RegisterRouter.scala:87:24] assign out_roready_1_1154 = _out_rofireMux_T_914; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_915 = ~_out_T_1895; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_917 = _out_rofireMux_T_260 & out_backSel_164; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_918 = _out_rofireMux_T_917 & _out_T_1645; // @[RegisterRouter.scala:87:24] assign out_roready_1_176 = _out_rofireMux_T_918; // @[RegisterRouter.scala:87:24] assign out_roready_1_177 = _out_rofireMux_T_918; // @[RegisterRouter.scala:87:24] assign out_roready_1_178 = _out_rofireMux_T_918; // @[RegisterRouter.scala:87:24] assign out_roready_1_179 = _out_rofireMux_T_918; // @[RegisterRouter.scala:87:24] assign out_roready_1_180 = _out_rofireMux_T_918; // @[RegisterRouter.scala:87:24] assign out_roready_1_181 = _out_rofireMux_T_918; // @[RegisterRouter.scala:87:24] assign out_roready_1_182 = _out_rofireMux_T_918; // @[RegisterRouter.scala:87:24] assign out_roready_1_183 = _out_rofireMux_T_918; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_919 = ~_out_T_1645; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_921 = _out_rofireMux_T_260 & out_backSel_165; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_922 = _out_rofireMux_T_921 & _out_T_1687; // @[RegisterRouter.scala:87:24] assign out_roready_1_344 = _out_rofireMux_T_922; // @[RegisterRouter.scala:87:24] assign out_roready_1_345 = _out_rofireMux_T_922; // @[RegisterRouter.scala:87:24] assign out_roready_1_346 = _out_rofireMux_T_922; // @[RegisterRouter.scala:87:24] assign out_roready_1_347 = _out_rofireMux_T_922; // @[RegisterRouter.scala:87:24] assign out_roready_1_348 = _out_rofireMux_T_922; // @[RegisterRouter.scala:87:24] assign out_roready_1_349 = _out_rofireMux_T_922; // @[RegisterRouter.scala:87:24] assign out_roready_1_350 = _out_rofireMux_T_922; // @[RegisterRouter.scala:87:24] assign out_roready_1_351 = _out_rofireMux_T_922; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_923 = ~_out_T_1687; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_925 = _out_rofireMux_T_260 & out_backSel_166; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_926 = _out_rofireMux_T_925 & _out_T_1737; // @[RegisterRouter.scala:87:24] assign out_roready_1_527 = _out_rofireMux_T_926; // @[RegisterRouter.scala:87:24] assign out_roready_1_528 = _out_rofireMux_T_926; // @[RegisterRouter.scala:87:24] assign out_roready_1_529 = _out_rofireMux_T_926; // @[RegisterRouter.scala:87:24] assign out_roready_1_530 = _out_rofireMux_T_926; // @[RegisterRouter.scala:87:24] assign out_roready_1_531 = _out_rofireMux_T_926; // @[RegisterRouter.scala:87:24] assign out_roready_1_532 = _out_rofireMux_T_926; // @[RegisterRouter.scala:87:24] assign out_roready_1_533 = _out_rofireMux_T_926; // @[RegisterRouter.scala:87:24] assign out_roready_1_534 = _out_rofireMux_T_926; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_927 = ~_out_T_1737; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_929 = _out_rofireMux_T_260 & out_backSel_167; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_930 = _out_rofireMux_T_929 & _out_T_1807; // @[RegisterRouter.scala:87:24] assign out_roready_1_795 = _out_rofireMux_T_930; // @[RegisterRouter.scala:87:24] assign out_roready_1_796 = _out_rofireMux_T_930; // @[RegisterRouter.scala:87:24] assign out_roready_1_797 = _out_rofireMux_T_930; // @[RegisterRouter.scala:87:24] assign out_roready_1_798 = _out_rofireMux_T_930; // @[RegisterRouter.scala:87:24] assign out_roready_1_799 = _out_rofireMux_T_930; // @[RegisterRouter.scala:87:24] assign out_roready_1_800 = _out_rofireMux_T_930; // @[RegisterRouter.scala:87:24] assign out_roready_1_801 = _out_rofireMux_T_930; // @[RegisterRouter.scala:87:24] assign out_roready_1_802 = _out_rofireMux_T_930; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_931 = ~_out_T_1807; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_933 = _out_rofireMux_T_260 & out_backSel_168; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_934 = _out_rofireMux_T_933 & _out_T_1875; // @[RegisterRouter.scala:87:24] assign out_roready_1_1067 = _out_rofireMux_T_934; // @[RegisterRouter.scala:87:24] assign out_roready_1_1068 = _out_rofireMux_T_934; // @[RegisterRouter.scala:87:24] assign out_roready_1_1069 = _out_rofireMux_T_934; // @[RegisterRouter.scala:87:24] assign out_roready_1_1070 = _out_rofireMux_T_934; // @[RegisterRouter.scala:87:24] assign out_roready_1_1071 = _out_rofireMux_T_934; // @[RegisterRouter.scala:87:24] assign out_roready_1_1072 = _out_rofireMux_T_934; // @[RegisterRouter.scala:87:24] assign out_roready_1_1073 = _out_rofireMux_T_934; // @[RegisterRouter.scala:87:24] assign out_roready_1_1074 = _out_rofireMux_T_934; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_935 = ~_out_T_1875; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_937 = _out_rofireMux_T_260 & out_backSel_169; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_938 = _out_rofireMux_T_937 & _out_T_1703; // @[RegisterRouter.scala:87:24] assign out_roready_1_402 = _out_rofireMux_T_938; // @[RegisterRouter.scala:87:24] assign out_roready_1_403 = _out_rofireMux_T_938; // @[RegisterRouter.scala:87:24] assign out_roready_1_404 = _out_rofireMux_T_938; // @[RegisterRouter.scala:87:24] assign out_roready_1_405 = _out_rofireMux_T_938; // @[RegisterRouter.scala:87:24] assign out_roready_1_406 = _out_rofireMux_T_938; // @[RegisterRouter.scala:87:24] assign out_roready_1_407 = _out_rofireMux_T_938; // @[RegisterRouter.scala:87:24] assign out_roready_1_408 = _out_rofireMux_T_938; // @[RegisterRouter.scala:87:24] assign out_roready_1_409 = _out_rofireMux_T_938; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_939 = ~_out_T_1703; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_941 = _out_rofireMux_T_260 & out_backSel_170; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_942 = _out_rofireMux_T_941 & _out_T_1607; // @[RegisterRouter.scala:87:24] assign out_roready_1_24 = _out_rofireMux_T_942; // @[RegisterRouter.scala:87:24] assign out_roready_1_25 = _out_rofireMux_T_942; // @[RegisterRouter.scala:87:24] assign out_roready_1_26 = _out_rofireMux_T_942; // @[RegisterRouter.scala:87:24] assign out_roready_1_27 = _out_rofireMux_T_942; // @[RegisterRouter.scala:87:24] assign out_roready_1_28 = _out_rofireMux_T_942; // @[RegisterRouter.scala:87:24] assign out_roready_1_29 = _out_rofireMux_T_942; // @[RegisterRouter.scala:87:24] assign out_roready_1_30 = _out_rofireMux_T_942; // @[RegisterRouter.scala:87:24] assign out_roready_1_31 = _out_rofireMux_T_942; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_943 = ~_out_T_1607; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_945 = _out_rofireMux_T_260 & out_backSel_171; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_946 = _out_rofireMux_T_945 & _out_T_1855; // @[RegisterRouter.scala:87:24] assign out_roready_1_987 = _out_rofireMux_T_946; // @[RegisterRouter.scala:87:24] assign out_roready_1_988 = _out_rofireMux_T_946; // @[RegisterRouter.scala:87:24] assign out_roready_1_989 = _out_rofireMux_T_946; // @[RegisterRouter.scala:87:24] assign out_roready_1_990 = _out_rofireMux_T_946; // @[RegisterRouter.scala:87:24] assign out_roready_1_991 = _out_rofireMux_T_946; // @[RegisterRouter.scala:87:24] assign out_roready_1_992 = _out_rofireMux_T_946; // @[RegisterRouter.scala:87:24] assign out_roready_1_993 = _out_rofireMux_T_946; // @[RegisterRouter.scala:87:24] assign out_roready_1_994 = _out_rofireMux_T_946; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_947 = ~_out_T_1855; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_949 = _out_rofireMux_T_260 & out_backSel_172; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_950 = _out_rofireMux_T_949 & _out_T_1769; // @[RegisterRouter.scala:87:24] assign out_roready_1_649 = _out_rofireMux_T_950; // @[RegisterRouter.scala:87:24] assign out_roready_1_650 = _out_rofireMux_T_950; // @[RegisterRouter.scala:87:24] assign out_roready_1_651 = _out_rofireMux_T_950; // @[RegisterRouter.scala:87:24] assign out_roready_1_652 = _out_rofireMux_T_950; // @[RegisterRouter.scala:87:24] assign out_roready_1_653 = _out_rofireMux_T_950; // @[RegisterRouter.scala:87:24] assign out_roready_1_654 = _out_rofireMux_T_950; // @[RegisterRouter.scala:87:24] assign out_roready_1_655 = _out_rofireMux_T_950; // @[RegisterRouter.scala:87:24] assign out_roready_1_656 = _out_rofireMux_T_950; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_951 = ~_out_T_1769; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_953 = _out_rofireMux_T_260 & out_backSel_173; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_954 = _out_rofireMux_T_953 & _out_T_1719; // @[RegisterRouter.scala:87:24] assign out_roready_1_459 = _out_rofireMux_T_954; // @[RegisterRouter.scala:87:24] assign out_roready_1_460 = _out_rofireMux_T_954; // @[RegisterRouter.scala:87:24] assign out_roready_1_461 = _out_rofireMux_T_954; // @[RegisterRouter.scala:87:24] assign out_roready_1_462 = _out_rofireMux_T_954; // @[RegisterRouter.scala:87:24] assign out_roready_1_463 = _out_rofireMux_T_954; // @[RegisterRouter.scala:87:24] assign out_roready_1_464 = _out_rofireMux_T_954; // @[RegisterRouter.scala:87:24] assign out_roready_1_465 = _out_rofireMux_T_954; // @[RegisterRouter.scala:87:24] assign out_roready_1_466 = _out_rofireMux_T_954; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_955 = ~_out_T_1719; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_957 = _out_rofireMux_T_260 & out_backSel_174; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_958 = _out_rofireMux_T_957 & _out_T_1621; // @[RegisterRouter.scala:87:24] assign out_roready_1_80 = _out_rofireMux_T_958; // @[RegisterRouter.scala:87:24] assign out_roready_1_81 = _out_rofireMux_T_958; // @[RegisterRouter.scala:87:24] assign out_roready_1_82 = _out_rofireMux_T_958; // @[RegisterRouter.scala:87:24] assign out_roready_1_83 = _out_rofireMux_T_958; // @[RegisterRouter.scala:87:24] assign out_roready_1_84 = _out_rofireMux_T_958; // @[RegisterRouter.scala:87:24] assign out_roready_1_85 = _out_rofireMux_T_958; // @[RegisterRouter.scala:87:24] assign out_roready_1_86 = _out_rofireMux_T_958; // @[RegisterRouter.scala:87:24] assign out_roready_1_87 = _out_rofireMux_T_958; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_959 = ~_out_T_1621; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_961 = _out_rofireMux_T_260 & out_backSel_175; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_962 = _out_rofireMux_T_961 & _out_T_1833; // @[RegisterRouter.scala:87:24] assign out_roready_1_899 = _out_rofireMux_T_962; // @[RegisterRouter.scala:87:24] assign out_roready_1_900 = _out_rofireMux_T_962; // @[RegisterRouter.scala:87:24] assign out_roready_1_901 = _out_rofireMux_T_962; // @[RegisterRouter.scala:87:24] assign out_roready_1_902 = _out_rofireMux_T_962; // @[RegisterRouter.scala:87:24] assign out_roready_1_903 = _out_rofireMux_T_962; // @[RegisterRouter.scala:87:24] assign out_roready_1_904 = _out_rofireMux_T_962; // @[RegisterRouter.scala:87:24] assign out_roready_1_905 = _out_rofireMux_T_962; // @[RegisterRouter.scala:87:24] assign out_roready_1_906 = _out_rofireMux_T_962; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_963 = ~_out_T_1833; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_965 = _out_rofireMux_T_260 & out_backSel_176; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_966 = _out_rofireMux_T_965 & _out_T_1751; // @[RegisterRouter.scala:87:24] assign out_roready_1_577 = _out_rofireMux_T_966; // @[RegisterRouter.scala:87:24] assign out_roready_1_578 = _out_rofireMux_T_966; // @[RegisterRouter.scala:87:24] assign out_roready_1_579 = _out_rofireMux_T_966; // @[RegisterRouter.scala:87:24] assign out_roready_1_580 = _out_rofireMux_T_966; // @[RegisterRouter.scala:87:24] assign out_roready_1_581 = _out_rofireMux_T_966; // @[RegisterRouter.scala:87:24] assign out_roready_1_582 = _out_rofireMux_T_966; // @[RegisterRouter.scala:87:24] assign out_roready_1_583 = _out_rofireMux_T_966; // @[RegisterRouter.scala:87:24] assign out_roready_1_584 = _out_rofireMux_T_966; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_967 = ~_out_T_1751; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_969 = _out_rofireMux_T_260 & out_backSel_177; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_970 = _out_rofireMux_T_969 & _out_T_1827; // @[RegisterRouter.scala:87:24] assign out_roready_1_875 = _out_rofireMux_T_970; // @[RegisterRouter.scala:87:24] assign out_roready_1_876 = _out_rofireMux_T_970; // @[RegisterRouter.scala:87:24] assign out_roready_1_877 = _out_rofireMux_T_970; // @[RegisterRouter.scala:87:24] assign out_roready_1_878 = _out_rofireMux_T_970; // @[RegisterRouter.scala:87:24] assign out_roready_1_879 = _out_rofireMux_T_970; // @[RegisterRouter.scala:87:24] assign out_roready_1_880 = _out_rofireMux_T_970; // @[RegisterRouter.scala:87:24] assign out_roready_1_881 = _out_rofireMux_T_970; // @[RegisterRouter.scala:87:24] assign out_roready_1_882 = _out_rofireMux_T_970; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_971 = ~_out_T_1827; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_973 = _out_rofireMux_T_260 & out_backSel_178; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_974 = _out_rofireMux_T_973 & _out_T_1893; // @[RegisterRouter.scala:87:24] assign out_roready_1_1139 = _out_rofireMux_T_974; // @[RegisterRouter.scala:87:24] assign out_roready_1_1140 = _out_rofireMux_T_974; // @[RegisterRouter.scala:87:24] assign out_roready_1_1141 = _out_rofireMux_T_974; // @[RegisterRouter.scala:87:24] assign out_roready_1_1142 = _out_rofireMux_T_974; // @[RegisterRouter.scala:87:24] assign out_roready_1_1143 = _out_rofireMux_T_974; // @[RegisterRouter.scala:87:24] assign out_roready_1_1144 = _out_rofireMux_T_974; // @[RegisterRouter.scala:87:24] assign out_roready_1_1145 = _out_rofireMux_T_974; // @[RegisterRouter.scala:87:24] assign out_roready_1_1146 = _out_rofireMux_T_974; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_975 = ~_out_T_1893; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_977 = _out_rofireMux_T_260 & out_backSel_179; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_978 = _out_rofireMux_T_977 & _out_T_1647; // @[RegisterRouter.scala:87:24] assign out_roready_1_184 = _out_rofireMux_T_978; // @[RegisterRouter.scala:87:24] assign out_roready_1_185 = _out_rofireMux_T_978; // @[RegisterRouter.scala:87:24] assign out_roready_1_186 = _out_rofireMux_T_978; // @[RegisterRouter.scala:87:24] assign out_roready_1_187 = _out_rofireMux_T_978; // @[RegisterRouter.scala:87:24] assign out_roready_1_188 = _out_rofireMux_T_978; // @[RegisterRouter.scala:87:24] assign out_roready_1_189 = _out_rofireMux_T_978; // @[RegisterRouter.scala:87:24] assign out_roready_1_190 = _out_rofireMux_T_978; // @[RegisterRouter.scala:87:24] assign out_roready_1_191 = _out_rofireMux_T_978; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_979 = ~_out_T_1647; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_981 = _out_rofireMux_T_260 & out_backSel_180; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_982 = _out_rofireMux_T_981 & _out_T_1747; // @[RegisterRouter.scala:87:24] assign out_roready_1_561 = _out_rofireMux_T_982; // @[RegisterRouter.scala:87:24] assign out_roready_1_562 = _out_rofireMux_T_982; // @[RegisterRouter.scala:87:24] assign out_roready_1_563 = _out_rofireMux_T_982; // @[RegisterRouter.scala:87:24] assign out_roready_1_564 = _out_rofireMux_T_982; // @[RegisterRouter.scala:87:24] assign out_roready_1_565 = _out_rofireMux_T_982; // @[RegisterRouter.scala:87:24] assign out_roready_1_566 = _out_rofireMux_T_982; // @[RegisterRouter.scala:87:24] assign out_roready_1_567 = _out_rofireMux_T_982; // @[RegisterRouter.scala:87:24] assign out_roready_1_568 = _out_rofireMux_T_982; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_983 = ~_out_T_1747; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_985 = _out_rofireMux_T_260 & out_backSel_181; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_986 = _out_rofireMux_T_985 & _out_T_1763; // @[RegisterRouter.scala:87:24] assign out_roready_1_625 = _out_rofireMux_T_986; // @[RegisterRouter.scala:87:24] assign out_roready_1_626 = _out_rofireMux_T_986; // @[RegisterRouter.scala:87:24] assign out_roready_1_627 = _out_rofireMux_T_986; // @[RegisterRouter.scala:87:24] assign out_roready_1_628 = _out_rofireMux_T_986; // @[RegisterRouter.scala:87:24] assign out_roready_1_629 = _out_rofireMux_T_986; // @[RegisterRouter.scala:87:24] assign out_roready_1_630 = _out_rofireMux_T_986; // @[RegisterRouter.scala:87:24] assign out_roready_1_631 = _out_rofireMux_T_986; // @[RegisterRouter.scala:87:24] assign out_roready_1_632 = _out_rofireMux_T_986; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_987 = ~_out_T_1763; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_989 = _out_rofireMux_T_260 & out_backSel_182; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_990 = _out_rofireMux_T_989 & _out_T_1829; // @[RegisterRouter.scala:87:24] assign out_roready_1_883 = _out_rofireMux_T_990; // @[RegisterRouter.scala:87:24] assign out_roready_1_884 = _out_rofireMux_T_990; // @[RegisterRouter.scala:87:24] assign out_roready_1_885 = _out_rofireMux_T_990; // @[RegisterRouter.scala:87:24] assign out_roready_1_886 = _out_rofireMux_T_990; // @[RegisterRouter.scala:87:24] assign out_roready_1_887 = _out_rofireMux_T_990; // @[RegisterRouter.scala:87:24] assign out_roready_1_888 = _out_rofireMux_T_990; // @[RegisterRouter.scala:87:24] assign out_roready_1_889 = _out_rofireMux_T_990; // @[RegisterRouter.scala:87:24] assign out_roready_1_890 = _out_rofireMux_T_990; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_991 = ~_out_T_1829; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_993 = _out_rofireMux_T_260 & out_backSel_183; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_994 = _out_rofireMux_T_993 & _out_T_1873; // @[RegisterRouter.scala:87:24] assign out_roready_1_1059 = _out_rofireMux_T_994; // @[RegisterRouter.scala:87:24] assign out_roready_1_1060 = _out_rofireMux_T_994; // @[RegisterRouter.scala:87:24] assign out_roready_1_1061 = _out_rofireMux_T_994; // @[RegisterRouter.scala:87:24] assign out_roready_1_1062 = _out_rofireMux_T_994; // @[RegisterRouter.scala:87:24] assign out_roready_1_1063 = _out_rofireMux_T_994; // @[RegisterRouter.scala:87:24] assign out_roready_1_1064 = _out_rofireMux_T_994; // @[RegisterRouter.scala:87:24] assign out_roready_1_1065 = _out_rofireMux_T_994; // @[RegisterRouter.scala:87:24] assign out_roready_1_1066 = _out_rofireMux_T_994; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_995 = ~_out_T_1873; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_997 = _out_rofireMux_T_260 & out_backSel_184; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_998 = _out_rofireMux_T_997 & _out_T_1627; // @[RegisterRouter.scala:87:24] assign out_roready_1_104 = _out_rofireMux_T_998; // @[RegisterRouter.scala:87:24] assign out_roready_1_105 = _out_rofireMux_T_998; // @[RegisterRouter.scala:87:24] assign out_roready_1_106 = _out_rofireMux_T_998; // @[RegisterRouter.scala:87:24] assign out_roready_1_107 = _out_rofireMux_T_998; // @[RegisterRouter.scala:87:24] assign out_roready_1_108 = _out_rofireMux_T_998; // @[RegisterRouter.scala:87:24] assign out_roready_1_109 = _out_rofireMux_T_998; // @[RegisterRouter.scala:87:24] assign out_roready_1_110 = _out_rofireMux_T_998; // @[RegisterRouter.scala:87:24] assign out_roready_1_111 = _out_rofireMux_T_998; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_999 = ~_out_T_1627; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1001 = _out_rofireMux_T_260 & out_backSel_185; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1002 = _out_rofireMux_T_1001 & _out_T_1623; // @[RegisterRouter.scala:87:24] assign out_roready_1_88 = _out_rofireMux_T_1002; // @[RegisterRouter.scala:87:24] assign out_roready_1_89 = _out_rofireMux_T_1002; // @[RegisterRouter.scala:87:24] assign out_roready_1_90 = _out_rofireMux_T_1002; // @[RegisterRouter.scala:87:24] assign out_roready_1_91 = _out_rofireMux_T_1002; // @[RegisterRouter.scala:87:24] assign out_roready_1_92 = _out_rofireMux_T_1002; // @[RegisterRouter.scala:87:24] assign out_roready_1_93 = _out_rofireMux_T_1002; // @[RegisterRouter.scala:87:24] assign out_roready_1_94 = _out_rofireMux_T_1002; // @[RegisterRouter.scala:87:24] assign out_roready_1_95 = _out_rofireMux_T_1002; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1003 = ~_out_T_1623; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1005 = _out_rofireMux_T_260 & out_backSel_186; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1006 = _out_rofireMux_T_1005 & _out_T_1851; // @[RegisterRouter.scala:87:24] assign out_roready_1_971 = _out_rofireMux_T_1006; // @[RegisterRouter.scala:87:24] assign out_roready_1_972 = _out_rofireMux_T_1006; // @[RegisterRouter.scala:87:24] assign out_roready_1_973 = _out_rofireMux_T_1006; // @[RegisterRouter.scala:87:24] assign out_roready_1_974 = _out_rofireMux_T_1006; // @[RegisterRouter.scala:87:24] assign out_roready_1_975 = _out_rofireMux_T_1006; // @[RegisterRouter.scala:87:24] assign out_roready_1_976 = _out_rofireMux_T_1006; // @[RegisterRouter.scala:87:24] assign out_roready_1_977 = _out_rofireMux_T_1006; // @[RegisterRouter.scala:87:24] assign out_roready_1_978 = _out_rofireMux_T_1006; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1007 = ~_out_T_1851; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1009 = _out_rofireMux_T_260 & out_backSel_187; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1010 = _out_rofireMux_T_1009 & _out_T_1767; // @[RegisterRouter.scala:87:24] assign out_roready_1_641 = _out_rofireMux_T_1010; // @[RegisterRouter.scala:87:24] assign out_roready_1_642 = _out_rofireMux_T_1010; // @[RegisterRouter.scala:87:24] assign out_roready_1_643 = _out_rofireMux_T_1010; // @[RegisterRouter.scala:87:24] assign out_roready_1_644 = _out_rofireMux_T_1010; // @[RegisterRouter.scala:87:24] assign out_roready_1_645 = _out_rofireMux_T_1010; // @[RegisterRouter.scala:87:24] assign out_roready_1_646 = _out_rofireMux_T_1010; // @[RegisterRouter.scala:87:24] assign out_roready_1_647 = _out_rofireMux_T_1010; // @[RegisterRouter.scala:87:24] assign out_roready_1_648 = _out_rofireMux_T_1010; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1011 = ~_out_T_1767; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1013 = _out_rofireMux_T_260 & out_backSel_188; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1014 = _out_rofireMux_T_1013 & _out_T_1701; // @[RegisterRouter.scala:87:24] assign out_roready_1_394 = _out_rofireMux_T_1014; // @[RegisterRouter.scala:87:24] assign out_roready_1_395 = _out_rofireMux_T_1014; // @[RegisterRouter.scala:87:24] assign out_roready_1_396 = _out_rofireMux_T_1014; // @[RegisterRouter.scala:87:24] assign out_roready_1_397 = _out_rofireMux_T_1014; // @[RegisterRouter.scala:87:24] assign out_roready_1_398 = _out_rofireMux_T_1014; // @[RegisterRouter.scala:87:24] assign out_roready_1_399 = _out_rofireMux_T_1014; // @[RegisterRouter.scala:87:24] assign out_roready_1_400 = _out_rofireMux_T_1014; // @[RegisterRouter.scala:87:24] assign out_roready_1_401 = _out_rofireMux_T_1014; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1015 = ~_out_T_1701; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1017 = _out_rofireMux_T_260 & out_backSel_189; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1018 = _out_rofireMux_T_1017 & _out_T_1635; // @[RegisterRouter.scala:87:24] assign out_roready_1_136 = _out_rofireMux_T_1018; // @[RegisterRouter.scala:87:24] assign out_roready_1_137 = _out_rofireMux_T_1018; // @[RegisterRouter.scala:87:24] assign out_roready_1_138 = _out_rofireMux_T_1018; // @[RegisterRouter.scala:87:24] assign out_roready_1_139 = _out_rofireMux_T_1018; // @[RegisterRouter.scala:87:24] assign out_roready_1_140 = _out_rofireMux_T_1018; // @[RegisterRouter.scala:87:24] assign out_roready_1_141 = _out_rofireMux_T_1018; // @[RegisterRouter.scala:87:24] assign out_roready_1_142 = _out_rofireMux_T_1018; // @[RegisterRouter.scala:87:24] assign out_roready_1_143 = _out_rofireMux_T_1018; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1019 = ~_out_T_1635; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1021 = _out_rofireMux_T_260 & out_backSel_190; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1022 = _out_rofireMux_T_1021 & _out_T_1871; // @[RegisterRouter.scala:87:24] assign out_roready_1_1051 = _out_rofireMux_T_1022; // @[RegisterRouter.scala:87:24] assign out_roready_1_1052 = _out_rofireMux_T_1022; // @[RegisterRouter.scala:87:24] assign out_roready_1_1053 = _out_rofireMux_T_1022; // @[RegisterRouter.scala:87:24] assign out_roready_1_1054 = _out_rofireMux_T_1022; // @[RegisterRouter.scala:87:24] assign out_roready_1_1055 = _out_rofireMux_T_1022; // @[RegisterRouter.scala:87:24] assign out_roready_1_1056 = _out_rofireMux_T_1022; // @[RegisterRouter.scala:87:24] assign out_roready_1_1057 = _out_rofireMux_T_1022; // @[RegisterRouter.scala:87:24] assign out_roready_1_1058 = _out_rofireMux_T_1022; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1023 = ~_out_T_1871; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1025 = _out_rofireMux_T_260 & out_backSel_191; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1026 = _out_rofireMux_T_1025 & _out_T_1753; // @[RegisterRouter.scala:87:24] assign out_roready_1_585 = _out_rofireMux_T_1026; // @[RegisterRouter.scala:87:24] assign out_roready_1_586 = _out_rofireMux_T_1026; // @[RegisterRouter.scala:87:24] assign out_roready_1_587 = _out_rofireMux_T_1026; // @[RegisterRouter.scala:87:24] assign out_roready_1_588 = _out_rofireMux_T_1026; // @[RegisterRouter.scala:87:24] assign out_roready_1_589 = _out_rofireMux_T_1026; // @[RegisterRouter.scala:87:24] assign out_roready_1_590 = _out_rofireMux_T_1026; // @[RegisterRouter.scala:87:24] assign out_roready_1_591 = _out_rofireMux_T_1026; // @[RegisterRouter.scala:87:24] assign out_roready_1_592 = _out_rofireMux_T_1026; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1027 = ~_out_T_1753; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1029 = _out_rofireMux_T_260 & out_backSel_192; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1030 = _out_rofireMux_T_1029 & _out_T_1683; // @[RegisterRouter.scala:87:24] assign out_roready_1_328 = _out_rofireMux_T_1030; // @[RegisterRouter.scala:87:24] assign out_roready_1_329 = _out_rofireMux_T_1030; // @[RegisterRouter.scala:87:24] assign out_roready_1_330 = _out_rofireMux_T_1030; // @[RegisterRouter.scala:87:24] assign out_roready_1_331 = _out_rofireMux_T_1030; // @[RegisterRouter.scala:87:24] assign out_roready_1_332 = _out_rofireMux_T_1030; // @[RegisterRouter.scala:87:24] assign out_roready_1_333 = _out_rofireMux_T_1030; // @[RegisterRouter.scala:87:24] assign out_roready_1_334 = _out_rofireMux_T_1030; // @[RegisterRouter.scala:87:24] assign out_roready_1_335 = _out_rofireMux_T_1030; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1031 = ~_out_T_1683; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1033 = _out_rofireMux_T_260 & out_backSel_193; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1034 = _out_rofireMux_T_1033 & _out_T_1709; // @[RegisterRouter.scala:87:24] assign out_roready_1_426 = _out_rofireMux_T_1034; // @[RegisterRouter.scala:87:24] assign out_roready_1_427 = _out_rofireMux_T_1034; // @[RegisterRouter.scala:87:24] assign out_roready_1_428 = _out_rofireMux_T_1034; // @[RegisterRouter.scala:87:24] assign out_roready_1_429 = _out_rofireMux_T_1034; // @[RegisterRouter.scala:87:24] assign out_roready_1_430 = _out_rofireMux_T_1034; // @[RegisterRouter.scala:87:24] assign out_roready_1_431 = _out_rofireMux_T_1034; // @[RegisterRouter.scala:87:24] assign out_roready_1_432 = _out_rofireMux_T_1034; // @[RegisterRouter.scala:87:24] assign out_roready_1_433 = _out_rofireMux_T_1034; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1035 = ~_out_T_1709; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1037 = _out_rofireMux_T_260 & out_backSel_194; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1038 = _out_rofireMux_T_1037 & _out_T_1817; // @[RegisterRouter.scala:87:24] assign out_roready_1_835 = _out_rofireMux_T_1038; // @[RegisterRouter.scala:87:24] assign out_roready_1_836 = _out_rofireMux_T_1038; // @[RegisterRouter.scala:87:24] assign out_roready_1_837 = _out_rofireMux_T_1038; // @[RegisterRouter.scala:87:24] assign out_roready_1_838 = _out_rofireMux_T_1038; // @[RegisterRouter.scala:87:24] assign out_roready_1_839 = _out_rofireMux_T_1038; // @[RegisterRouter.scala:87:24] assign out_roready_1_840 = _out_rofireMux_T_1038; // @[RegisterRouter.scala:87:24] assign out_roready_1_841 = _out_rofireMux_T_1038; // @[RegisterRouter.scala:87:24] assign out_roready_1_842 = _out_rofireMux_T_1038; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1039 = ~_out_T_1817; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1041 = _out_rofireMux_T_260 & out_backSel_195; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1042 = _out_rofireMux_T_1041 & _out_T_1885; // @[RegisterRouter.scala:87:24] assign out_roready_1_1107 = _out_rofireMux_T_1042; // @[RegisterRouter.scala:87:24] assign out_roready_1_1108 = _out_rofireMux_T_1042; // @[RegisterRouter.scala:87:24] assign out_roready_1_1109 = _out_rofireMux_T_1042; // @[RegisterRouter.scala:87:24] assign out_roready_1_1110 = _out_rofireMux_T_1042; // @[RegisterRouter.scala:87:24] assign out_roready_1_1111 = _out_rofireMux_T_1042; // @[RegisterRouter.scala:87:24] assign out_roready_1_1112 = _out_rofireMux_T_1042; // @[RegisterRouter.scala:87:24] assign out_roready_1_1113 = _out_rofireMux_T_1042; // @[RegisterRouter.scala:87:24] assign out_roready_1_1114 = _out_rofireMux_T_1042; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1043 = ~_out_T_1885; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1045 = _out_rofireMux_T_260 & out_backSel_196; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1046 = _out_rofireMux_T_1045 & _out_T_1631; // @[RegisterRouter.scala:87:24] assign out_roready_1_120 = _out_rofireMux_T_1046; // @[RegisterRouter.scala:87:24] assign out_roready_1_121 = _out_rofireMux_T_1046; // @[RegisterRouter.scala:87:24] assign out_roready_1_122 = _out_rofireMux_T_1046; // @[RegisterRouter.scala:87:24] assign out_roready_1_123 = _out_rofireMux_T_1046; // @[RegisterRouter.scala:87:24] assign out_roready_1_124 = _out_rofireMux_T_1046; // @[RegisterRouter.scala:87:24] assign out_roready_1_125 = _out_rofireMux_T_1046; // @[RegisterRouter.scala:87:24] assign out_roready_1_126 = _out_rofireMux_T_1046; // @[RegisterRouter.scala:87:24] assign out_roready_1_127 = _out_rofireMux_T_1046; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1047 = ~_out_T_1631; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1049 = _out_rofireMux_T_260 & out_backSel_197; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1050 = _out_rofireMux_T_1049 & _out_T_1695; // @[RegisterRouter.scala:87:24] assign out_roready_1_370 = _out_rofireMux_T_1050; // @[RegisterRouter.scala:87:24] assign out_roready_1_371 = _out_rofireMux_T_1050; // @[RegisterRouter.scala:87:24] assign out_roready_1_372 = _out_rofireMux_T_1050; // @[RegisterRouter.scala:87:24] assign out_roready_1_373 = _out_rofireMux_T_1050; // @[RegisterRouter.scala:87:24] assign out_roready_1_374 = _out_rofireMux_T_1050; // @[RegisterRouter.scala:87:24] assign out_roready_1_375 = _out_rofireMux_T_1050; // @[RegisterRouter.scala:87:24] assign out_roready_1_376 = _out_rofireMux_T_1050; // @[RegisterRouter.scala:87:24] assign out_roready_1_377 = _out_rofireMux_T_1050; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1051 = ~_out_T_1695; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1053 = _out_rofireMux_T_260 & out_backSel_198; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1054 = _out_rofireMux_T_1053 & _out_T_1789; // @[RegisterRouter.scala:87:24] assign out_roready_1_723 = _out_rofireMux_T_1054; // @[RegisterRouter.scala:87:24] assign out_roready_1_724 = _out_rofireMux_T_1054; // @[RegisterRouter.scala:87:24] assign out_roready_1_725 = _out_rofireMux_T_1054; // @[RegisterRouter.scala:87:24] assign out_roready_1_726 = _out_rofireMux_T_1054; // @[RegisterRouter.scala:87:24] assign out_roready_1_727 = _out_rofireMux_T_1054; // @[RegisterRouter.scala:87:24] assign out_roready_1_728 = _out_rofireMux_T_1054; // @[RegisterRouter.scala:87:24] assign out_roready_1_729 = _out_rofireMux_T_1054; // @[RegisterRouter.scala:87:24] assign out_roready_1_730 = _out_rofireMux_T_1054; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1055 = ~_out_T_1789; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1057 = _out_rofireMux_T_260 & out_backSel_199; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1058 = _out_rofireMux_T_1057 & _out_T_1825; // @[RegisterRouter.scala:87:24] assign out_roready_1_867 = _out_rofireMux_T_1058; // @[RegisterRouter.scala:87:24] assign out_roready_1_868 = _out_rofireMux_T_1058; // @[RegisterRouter.scala:87:24] assign out_roready_1_869 = _out_rofireMux_T_1058; // @[RegisterRouter.scala:87:24] assign out_roready_1_870 = _out_rofireMux_T_1058; // @[RegisterRouter.scala:87:24] assign out_roready_1_871 = _out_rofireMux_T_1058; // @[RegisterRouter.scala:87:24] assign out_roready_1_872 = _out_rofireMux_T_1058; // @[RegisterRouter.scala:87:24] assign out_roready_1_873 = _out_rofireMux_T_1058; // @[RegisterRouter.scala:87:24] assign out_roready_1_874 = _out_rofireMux_T_1058; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1059 = ~_out_T_1825; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1061 = _out_rofireMux_T_260 & out_backSel_200; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1062 = _out_rofireMux_T_1061 & _out_T_1897; // @[RegisterRouter.scala:87:24] assign out_roready_1_1155 = _out_rofireMux_T_1062; // @[RegisterRouter.scala:87:24] assign out_roready_1_1156 = _out_rofireMux_T_1062; // @[RegisterRouter.scala:87:24] assign out_roready_1_1157 = _out_rofireMux_T_1062; // @[RegisterRouter.scala:87:24] assign out_roready_1_1158 = _out_rofireMux_T_1062; // @[RegisterRouter.scala:87:24] assign out_roready_1_1159 = _out_rofireMux_T_1062; // @[RegisterRouter.scala:87:24] assign out_roready_1_1160 = _out_rofireMux_T_1062; // @[RegisterRouter.scala:87:24] assign out_roready_1_1161 = _out_rofireMux_T_1062; // @[RegisterRouter.scala:87:24] assign out_roready_1_1162 = _out_rofireMux_T_1062; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1063 = ~_out_T_1897; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1065 = _out_rofireMux_T_260 & out_backSel_201; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1066 = _out_rofireMux_T_1065 & _out_T_1675; // @[RegisterRouter.scala:87:24] assign out_roready_1_296 = _out_rofireMux_T_1066; // @[RegisterRouter.scala:87:24] assign out_roready_1_297 = _out_rofireMux_T_1066; // @[RegisterRouter.scala:87:24] assign out_roready_1_298 = _out_rofireMux_T_1066; // @[RegisterRouter.scala:87:24] assign out_roready_1_299 = _out_rofireMux_T_1066; // @[RegisterRouter.scala:87:24] assign out_roready_1_300 = _out_rofireMux_T_1066; // @[RegisterRouter.scala:87:24] assign out_roready_1_301 = _out_rofireMux_T_1066; // @[RegisterRouter.scala:87:24] assign out_roready_1_302 = _out_rofireMux_T_1066; // @[RegisterRouter.scala:87:24] assign out_roready_1_303 = _out_rofireMux_T_1066; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1067 = ~_out_T_1675; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1069 = _out_rofireMux_T_260 & out_backSel_202; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1070 = _out_rofireMux_T_1069 & _out_T_1615; // @[RegisterRouter.scala:87:24] assign out_roready_1_56 = _out_rofireMux_T_1070; // @[RegisterRouter.scala:87:24] assign out_roready_1_57 = _out_rofireMux_T_1070; // @[RegisterRouter.scala:87:24] assign out_roready_1_58 = _out_rofireMux_T_1070; // @[RegisterRouter.scala:87:24] assign out_roready_1_59 = _out_rofireMux_T_1070; // @[RegisterRouter.scala:87:24] assign out_roready_1_60 = _out_rofireMux_T_1070; // @[RegisterRouter.scala:87:24] assign out_roready_1_61 = _out_rofireMux_T_1070; // @[RegisterRouter.scala:87:24] assign out_roready_1_62 = _out_rofireMux_T_1070; // @[RegisterRouter.scala:87:24] assign out_roready_1_63 = _out_rofireMux_T_1070; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1071 = ~_out_T_1615; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1073 = _out_rofireMux_T_260 & out_backSel_203; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1074 = _out_rofireMux_T_1073 & _out_T_1837; // @[RegisterRouter.scala:87:24] assign out_roready_1_915 = _out_rofireMux_T_1074; // @[RegisterRouter.scala:87:24] assign out_roready_1_916 = _out_rofireMux_T_1074; // @[RegisterRouter.scala:87:24] assign out_roready_1_917 = _out_rofireMux_T_1074; // @[RegisterRouter.scala:87:24] assign out_roready_1_918 = _out_rofireMux_T_1074; // @[RegisterRouter.scala:87:24] assign out_roready_1_919 = _out_rofireMux_T_1074; // @[RegisterRouter.scala:87:24] assign out_roready_1_920 = _out_rofireMux_T_1074; // @[RegisterRouter.scala:87:24] assign out_roready_1_921 = _out_rofireMux_T_1074; // @[RegisterRouter.scala:87:24] assign out_roready_1_922 = _out_rofireMux_T_1074; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1075 = ~_out_T_1837; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1077 = _out_rofireMux_T_260 & out_backSel_204; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1078 = _out_rofireMux_T_1077 & _out_T_1755; // @[RegisterRouter.scala:87:24] assign out_roready_1_593 = _out_rofireMux_T_1078; // @[RegisterRouter.scala:87:24] assign out_roready_1_594 = _out_rofireMux_T_1078; // @[RegisterRouter.scala:87:24] assign out_roready_1_595 = _out_rofireMux_T_1078; // @[RegisterRouter.scala:87:24] assign out_roready_1_596 = _out_rofireMux_T_1078; // @[RegisterRouter.scala:87:24] assign out_roready_1_597 = _out_rofireMux_T_1078; // @[RegisterRouter.scala:87:24] assign out_roready_1_598 = _out_rofireMux_T_1078; // @[RegisterRouter.scala:87:24] assign out_roready_1_599 = _out_rofireMux_T_1078; // @[RegisterRouter.scala:87:24] assign out_roready_1_600 = _out_rofireMux_T_1078; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1079 = ~_out_T_1755; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1081 = _out_rofireMux_T_260 & out_backSel_205; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1082 = _out_rofireMux_T_1081 & _out_T_1727; // @[RegisterRouter.scala:87:24] assign out_roready_1_487 = _out_rofireMux_T_1082; // @[RegisterRouter.scala:87:24] assign out_roready_1_488 = _out_rofireMux_T_1082; // @[RegisterRouter.scala:87:24] assign out_roready_1_489 = _out_rofireMux_T_1082; // @[RegisterRouter.scala:87:24] assign out_roready_1_490 = _out_rofireMux_T_1082; // @[RegisterRouter.scala:87:24] assign out_roready_1_491 = _out_rofireMux_T_1082; // @[RegisterRouter.scala:87:24] assign out_roready_1_492 = _out_rofireMux_T_1082; // @[RegisterRouter.scala:87:24] assign out_roready_1_493 = _out_rofireMux_T_1082; // @[RegisterRouter.scala:87:24] assign out_roready_1_494 = _out_rofireMux_T_1082; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1083 = ~_out_T_1727; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1085 = _out_rofireMux_T_260 & out_backSel_206; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1086 = _out_rofireMux_T_1085 & _out_T_1669; // @[RegisterRouter.scala:87:24] assign out_roready_1_272 = _out_rofireMux_T_1086; // @[RegisterRouter.scala:87:24] assign out_roready_1_273 = _out_rofireMux_T_1086; // @[RegisterRouter.scala:87:24] assign out_roready_1_274 = _out_rofireMux_T_1086; // @[RegisterRouter.scala:87:24] assign out_roready_1_275 = _out_rofireMux_T_1086; // @[RegisterRouter.scala:87:24] assign out_roready_1_276 = _out_rofireMux_T_1086; // @[RegisterRouter.scala:87:24] assign out_roready_1_277 = _out_rofireMux_T_1086; // @[RegisterRouter.scala:87:24] assign out_roready_1_278 = _out_rofireMux_T_1086; // @[RegisterRouter.scala:87:24] assign out_roready_1_279 = _out_rofireMux_T_1086; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1087 = ~_out_T_1669; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1089 = _out_rofireMux_T_260 & out_backSel_207; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1090 = _out_rofireMux_T_1089 & _out_T_1859; // @[RegisterRouter.scala:87:24] assign out_roready_1_1003 = _out_rofireMux_T_1090; // @[RegisterRouter.scala:87:24] assign out_roready_1_1004 = _out_rofireMux_T_1090; // @[RegisterRouter.scala:87:24] assign out_roready_1_1005 = _out_rofireMux_T_1090; // @[RegisterRouter.scala:87:24] assign out_roready_1_1006 = _out_rofireMux_T_1090; // @[RegisterRouter.scala:87:24] assign out_roready_1_1007 = _out_rofireMux_T_1090; // @[RegisterRouter.scala:87:24] assign out_roready_1_1008 = _out_rofireMux_T_1090; // @[RegisterRouter.scala:87:24] assign out_roready_1_1009 = _out_rofireMux_T_1090; // @[RegisterRouter.scala:87:24] assign out_roready_1_1010 = _out_rofireMux_T_1090; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1091 = ~_out_T_1859; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1093 = _out_rofireMux_T_260 & out_backSel_208; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1094 = _out_rofireMux_T_1093 & _out_T_1779; // @[RegisterRouter.scala:87:24] assign out_roready_1_689 = _out_rofireMux_T_1094; // @[RegisterRouter.scala:87:24] assign out_roready_1_690 = _out_rofireMux_T_1094; // @[RegisterRouter.scala:87:24] assign out_roready_1_691 = _out_rofireMux_T_1094; // @[RegisterRouter.scala:87:24] assign out_roready_1_692 = _out_rofireMux_T_1094; // @[RegisterRouter.scala:87:24] assign out_roready_1_693 = _out_rofireMux_T_1094; // @[RegisterRouter.scala:87:24] assign out_roready_1_694 = _out_rofireMux_T_1094; // @[RegisterRouter.scala:87:24] assign out_roready_1_695 = _out_rofireMux_T_1094; // @[RegisterRouter.scala:87:24] assign out_roready_1_696 = _out_rofireMux_T_1094; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1095 = ~_out_T_1779; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1097 = _out_rofireMux_T_260 & out_backSel_209; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1098 = _out_rofireMux_T_1097 & _out_T_1813; // @[RegisterRouter.scala:87:24] assign out_roready_1_819 = _out_rofireMux_T_1098; // @[RegisterRouter.scala:87:24] assign out_roready_1_820 = _out_rofireMux_T_1098; // @[RegisterRouter.scala:87:24] assign out_roready_1_821 = _out_rofireMux_T_1098; // @[RegisterRouter.scala:87:24] assign out_roready_1_822 = _out_rofireMux_T_1098; // @[RegisterRouter.scala:87:24] assign out_roready_1_823 = _out_rofireMux_T_1098; // @[RegisterRouter.scala:87:24] assign out_roready_1_824 = _out_rofireMux_T_1098; // @[RegisterRouter.scala:87:24] assign out_roready_1_825 = _out_rofireMux_T_1098; // @[RegisterRouter.scala:87:24] assign out_roready_1_826 = _out_rofireMux_T_1098; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1099 = ~_out_T_1813; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1101 = _out_rofireMux_T_260 & out_backSel_210; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1102 = _out_rofireMux_T_1101 & _out_T_1879; // @[RegisterRouter.scala:87:24] assign out_roready_1_1083 = _out_rofireMux_T_1102; // @[RegisterRouter.scala:87:24] assign out_roready_1_1084 = _out_rofireMux_T_1102; // @[RegisterRouter.scala:87:24] assign out_roready_1_1085 = _out_rofireMux_T_1102; // @[RegisterRouter.scala:87:24] assign out_roready_1_1086 = _out_rofireMux_T_1102; // @[RegisterRouter.scala:87:24] assign out_roready_1_1087 = _out_rofireMux_T_1102; // @[RegisterRouter.scala:87:24] assign out_roready_1_1088 = _out_rofireMux_T_1102; // @[RegisterRouter.scala:87:24] assign out_roready_1_1089 = _out_rofireMux_T_1102; // @[RegisterRouter.scala:87:24] assign out_roready_1_1090 = _out_rofireMux_T_1102; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1103 = ~_out_T_1879; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1105 = _out_rofireMux_T_260 & out_backSel_211; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1106 = _out_rofireMux_T_1105 & _out_T_1653; // @[RegisterRouter.scala:87:24] assign out_roready_1_208 = _out_rofireMux_T_1106; // @[RegisterRouter.scala:87:24] assign out_roready_1_209 = _out_rofireMux_T_1106; // @[RegisterRouter.scala:87:24] assign out_roready_1_210 = _out_rofireMux_T_1106; // @[RegisterRouter.scala:87:24] assign out_roready_1_211 = _out_rofireMux_T_1106; // @[RegisterRouter.scala:87:24] assign out_roready_1_212 = _out_rofireMux_T_1106; // @[RegisterRouter.scala:87:24] assign out_roready_1_213 = _out_rofireMux_T_1106; // @[RegisterRouter.scala:87:24] assign out_roready_1_214 = _out_rofireMux_T_1106; // @[RegisterRouter.scala:87:24] assign out_roready_1_215 = _out_rofireMux_T_1106; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1107 = ~_out_T_1653; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1109 = _out_rofireMux_T_260 & out_backSel_212; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1110 = _out_rofireMux_T_1109 & _out_T_1711; // @[RegisterRouter.scala:87:24] assign out_roready_1_434 = _out_rofireMux_T_1110; // @[RegisterRouter.scala:87:24] assign out_roready_1_435 = _out_rofireMux_T_1110; // @[RegisterRouter.scala:87:24] assign out_roready_1_436 = _out_rofireMux_T_1110; // @[RegisterRouter.scala:87:24] assign out_roready_1_437 = _out_rofireMux_T_1110; // @[RegisterRouter.scala:87:24] assign out_roready_1_438 = _out_rofireMux_T_1110; // @[RegisterRouter.scala:87:24] assign out_roready_1_439 = _out_rofireMux_T_1110; // @[RegisterRouter.scala:87:24] assign out_roready_1_440 = _out_rofireMux_T_1110; // @[RegisterRouter.scala:87:24] assign out_roready_1_441 = _out_rofireMux_T_1110; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1111 = ~_out_T_1711; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1113 = _out_rofireMux_T_260 & out_backSel_213; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1114 = _out_rofireMux_T_1113 & _out_T_1785; // @[RegisterRouter.scala:87:24] assign out_roready_1_707 = _out_rofireMux_T_1114; // @[RegisterRouter.scala:87:24] assign out_roready_1_708 = _out_rofireMux_T_1114; // @[RegisterRouter.scala:87:24] assign out_roready_1_709 = _out_rofireMux_T_1114; // @[RegisterRouter.scala:87:24] assign out_roready_1_710 = _out_rofireMux_T_1114; // @[RegisterRouter.scala:87:24] assign out_roready_1_711 = _out_rofireMux_T_1114; // @[RegisterRouter.scala:87:24] assign out_roready_1_712 = _out_rofireMux_T_1114; // @[RegisterRouter.scala:87:24] assign out_roready_1_713 = _out_rofireMux_T_1114; // @[RegisterRouter.scala:87:24] assign out_roready_1_714 = _out_rofireMux_T_1114; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1115 = ~_out_T_1785; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1117 = _out_rofireMux_T_260 & out_backSel_214; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1118 = _out_rofireMux_T_1117 & _out_T_1861; // @[RegisterRouter.scala:87:24] assign out_roready_1_1011 = _out_rofireMux_T_1118; // @[RegisterRouter.scala:87:24] assign out_roready_1_1012 = _out_rofireMux_T_1118; // @[RegisterRouter.scala:87:24] assign out_roready_1_1013 = _out_rofireMux_T_1118; // @[RegisterRouter.scala:87:24] assign out_roready_1_1014 = _out_rofireMux_T_1118; // @[RegisterRouter.scala:87:24] assign out_roready_1_1015 = _out_rofireMux_T_1118; // @[RegisterRouter.scala:87:24] assign out_roready_1_1016 = _out_rofireMux_T_1118; // @[RegisterRouter.scala:87:24] assign out_roready_1_1017 = _out_rofireMux_T_1118; // @[RegisterRouter.scala:87:24] assign out_roready_1_1018 = _out_rofireMux_T_1118; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1119 = ~_out_T_1861; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1121 = _out_rofireMux_T_260 & out_backSel_215; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1122 = _out_rofireMux_T_1121 & _out_T_1901; // @[RegisterRouter.scala:87:24] assign out_roready_1_1171 = _out_rofireMux_T_1122; // @[RegisterRouter.scala:87:24] assign out_roready_1_1172 = _out_rofireMux_T_1122; // @[RegisterRouter.scala:87:24] assign out_roready_1_1173 = _out_rofireMux_T_1122; // @[RegisterRouter.scala:87:24] assign out_roready_1_1174 = _out_rofireMux_T_1122; // @[RegisterRouter.scala:87:24] assign out_roready_1_1175 = _out_rofireMux_T_1122; // @[RegisterRouter.scala:87:24] assign out_roready_1_1176 = _out_rofireMux_T_1122; // @[RegisterRouter.scala:87:24] assign out_roready_1_1177 = _out_rofireMux_T_1122; // @[RegisterRouter.scala:87:24] assign out_roready_1_1178 = _out_rofireMux_T_1122; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1123 = ~_out_T_1901; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1125 = _out_rofireMux_T_260 & out_backSel_216; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1126 = _out_rofireMux_T_1125 & _out_T_1643; // @[RegisterRouter.scala:87:24] assign out_roready_1_168 = _out_rofireMux_T_1126; // @[RegisterRouter.scala:87:24] assign out_roready_1_169 = _out_rofireMux_T_1126; // @[RegisterRouter.scala:87:24] assign out_roready_1_170 = _out_rofireMux_T_1126; // @[RegisterRouter.scala:87:24] assign out_roready_1_171 = _out_rofireMux_T_1126; // @[RegisterRouter.scala:87:24] assign out_roready_1_172 = _out_rofireMux_T_1126; // @[RegisterRouter.scala:87:24] assign out_roready_1_173 = _out_rofireMux_T_1126; // @[RegisterRouter.scala:87:24] assign out_roready_1_174 = _out_rofireMux_T_1126; // @[RegisterRouter.scala:87:24] assign out_roready_1_175 = _out_rofireMux_T_1126; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1127 = ~_out_T_1643; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1129 = _out_rofireMux_T_260 & out_backSel_217; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1130 = _out_rofireMux_T_1129 & _out_T_1611; // @[RegisterRouter.scala:87:24] assign out_roready_1_40 = _out_rofireMux_T_1130; // @[RegisterRouter.scala:87:24] assign out_roready_1_41 = _out_rofireMux_T_1130; // @[RegisterRouter.scala:87:24] assign out_roready_1_42 = _out_rofireMux_T_1130; // @[RegisterRouter.scala:87:24] assign out_roready_1_43 = _out_rofireMux_T_1130; // @[RegisterRouter.scala:87:24] assign out_roready_1_44 = _out_rofireMux_T_1130; // @[RegisterRouter.scala:87:24] assign out_roready_1_45 = _out_rofireMux_T_1130; // @[RegisterRouter.scala:87:24] assign out_roready_1_46 = _out_rofireMux_T_1130; // @[RegisterRouter.scala:87:24] assign out_roready_1_47 = _out_rofireMux_T_1130; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1131 = ~_out_T_1611; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1133 = _out_rofireMux_T_260 & out_backSel_218; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1134 = _out_rofireMux_T_1133 & _out_T_1839; // @[RegisterRouter.scala:87:24] assign out_roready_1_923 = _out_rofireMux_T_1134; // @[RegisterRouter.scala:87:24] assign out_roready_1_924 = _out_rofireMux_T_1134; // @[RegisterRouter.scala:87:24] assign out_roready_1_925 = _out_rofireMux_T_1134; // @[RegisterRouter.scala:87:24] assign out_roready_1_926 = _out_rofireMux_T_1134; // @[RegisterRouter.scala:87:24] assign out_roready_1_927 = _out_rofireMux_T_1134; // @[RegisterRouter.scala:87:24] assign out_roready_1_928 = _out_rofireMux_T_1134; // @[RegisterRouter.scala:87:24] assign out_roready_1_929 = _out_rofireMux_T_1134; // @[RegisterRouter.scala:87:24] assign out_roready_1_930 = _out_rofireMux_T_1134; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1135 = ~_out_T_1839; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1137 = _out_rofireMux_T_260 & out_backSel_219; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1138 = _out_rofireMux_T_1137 & _out_T_1773; // @[RegisterRouter.scala:87:24] assign out_roready_1_665 = _out_rofireMux_T_1138; // @[RegisterRouter.scala:87:24] assign out_roready_1_666 = _out_rofireMux_T_1138; // @[RegisterRouter.scala:87:24] assign out_roready_1_667 = _out_rofireMux_T_1138; // @[RegisterRouter.scala:87:24] assign out_roready_1_668 = _out_rofireMux_T_1138; // @[RegisterRouter.scala:87:24] assign out_roready_1_669 = _out_rofireMux_T_1138; // @[RegisterRouter.scala:87:24] assign out_roready_1_670 = _out_rofireMux_T_1138; // @[RegisterRouter.scala:87:24] assign out_roready_1_671 = _out_rofireMux_T_1138; // @[RegisterRouter.scala:87:24] assign out_roready_1_672 = _out_rofireMux_T_1138; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1139 = ~_out_T_1773; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1141 = _out_rofireMux_T_260 & out_backSel_220; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1142 = _out_rofireMux_T_1141 & _out_T_1677; // @[RegisterRouter.scala:87:24] assign out_roready_1_304 = _out_rofireMux_T_1142; // @[RegisterRouter.scala:87:24] assign out_roready_1_305 = _out_rofireMux_T_1142; // @[RegisterRouter.scala:87:24] assign out_roready_1_306 = _out_rofireMux_T_1142; // @[RegisterRouter.scala:87:24] assign out_roready_1_307 = _out_rofireMux_T_1142; // @[RegisterRouter.scala:87:24] assign out_roready_1_308 = _out_rofireMux_T_1142; // @[RegisterRouter.scala:87:24] assign out_roready_1_309 = _out_rofireMux_T_1142; // @[RegisterRouter.scala:87:24] assign out_roready_1_310 = _out_rofireMux_T_1142; // @[RegisterRouter.scala:87:24] assign out_roready_1_311 = _out_rofireMux_T_1142; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1143 = ~_out_T_1677; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1145 = _out_rofireMux_T_260 & out_backSel_221; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1146 = _out_rofireMux_T_1145 & _out_T_1659; // @[RegisterRouter.scala:87:24] assign out_roready_1_232 = _out_rofireMux_T_1146; // @[RegisterRouter.scala:87:24] assign out_roready_1_233 = _out_rofireMux_T_1146; // @[RegisterRouter.scala:87:24] assign out_roready_1_234 = _out_rofireMux_T_1146; // @[RegisterRouter.scala:87:24] assign out_roready_1_235 = _out_rofireMux_T_1146; // @[RegisterRouter.scala:87:24] assign out_roready_1_236 = _out_rofireMux_T_1146; // @[RegisterRouter.scala:87:24] assign out_roready_1_237 = _out_rofireMux_T_1146; // @[RegisterRouter.scala:87:24] assign out_roready_1_238 = _out_rofireMux_T_1146; // @[RegisterRouter.scala:87:24] assign out_roready_1_239 = _out_rofireMux_T_1146; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1147 = ~_out_T_1659; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1149 = _out_rofireMux_T_260 & out_backSel_222; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1150 = _out_rofireMux_T_1149 & _out_T_1903; // @[RegisterRouter.scala:87:24] assign out_roready_1_1179 = _out_rofireMux_T_1150; // @[RegisterRouter.scala:87:24] assign out_roready_1_1180 = _out_rofireMux_T_1150; // @[RegisterRouter.scala:87:24] assign out_roready_1_1181 = _out_rofireMux_T_1150; // @[RegisterRouter.scala:87:24] assign out_roready_1_1182 = _out_rofireMux_T_1150; // @[RegisterRouter.scala:87:24] assign out_roready_1_1183 = _out_rofireMux_T_1150; // @[RegisterRouter.scala:87:24] assign out_roready_1_1184 = _out_rofireMux_T_1150; // @[RegisterRouter.scala:87:24] assign out_roready_1_1185 = _out_rofireMux_T_1150; // @[RegisterRouter.scala:87:24] assign out_roready_1_1186 = _out_rofireMux_T_1150; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1151 = ~_out_T_1903; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1153 = _out_rofireMux_T_260 & out_backSel_223; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1154 = _out_rofireMux_T_1153 & _out_T_1799; // @[RegisterRouter.scala:87:24] assign out_roready_1_763 = _out_rofireMux_T_1154; // @[RegisterRouter.scala:87:24] assign out_roready_1_764 = _out_rofireMux_T_1154; // @[RegisterRouter.scala:87:24] assign out_roready_1_765 = _out_rofireMux_T_1154; // @[RegisterRouter.scala:87:24] assign out_roready_1_766 = _out_rofireMux_T_1154; // @[RegisterRouter.scala:87:24] assign out_roready_1_767 = _out_rofireMux_T_1154; // @[RegisterRouter.scala:87:24] assign out_roready_1_768 = _out_rofireMux_T_1154; // @[RegisterRouter.scala:87:24] assign out_roready_1_769 = _out_rofireMux_T_1154; // @[RegisterRouter.scala:87:24] assign out_roready_1_770 = _out_rofireMux_T_1154; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1155 = ~_out_T_1799; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1157 = _out_rofireMux_T_260 & out_backSel_224; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1158 = _out_rofireMux_T_1157 & _out_T_1697; // @[RegisterRouter.scala:87:24] assign out_roready_1_378 = _out_rofireMux_T_1158; // @[RegisterRouter.scala:87:24] assign out_roready_1_379 = _out_rofireMux_T_1158; // @[RegisterRouter.scala:87:24] assign out_roready_1_380 = _out_rofireMux_T_1158; // @[RegisterRouter.scala:87:24] assign out_roready_1_381 = _out_rofireMux_T_1158; // @[RegisterRouter.scala:87:24] assign out_roready_1_382 = _out_rofireMux_T_1158; // @[RegisterRouter.scala:87:24] assign out_roready_1_383 = _out_rofireMux_T_1158; // @[RegisterRouter.scala:87:24] assign out_roready_1_384 = _out_rofireMux_T_1158; // @[RegisterRouter.scala:87:24] assign out_roready_1_385 = _out_rofireMux_T_1158; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1159 = ~_out_T_1697; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1161 = _out_rofireMux_T_260 & out_backSel_225; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1162 = _out_rofireMux_T_1161 & _out_T_1707; // @[RegisterRouter.scala:87:24] assign out_roready_1_418 = _out_rofireMux_T_1162; // @[RegisterRouter.scala:87:24] assign out_roready_1_419 = _out_rofireMux_T_1162; // @[RegisterRouter.scala:87:24] assign out_roready_1_420 = _out_rofireMux_T_1162; // @[RegisterRouter.scala:87:24] assign out_roready_1_421 = _out_rofireMux_T_1162; // @[RegisterRouter.scala:87:24] assign out_roready_1_422 = _out_rofireMux_T_1162; // @[RegisterRouter.scala:87:24] assign out_roready_1_423 = _out_rofireMux_T_1162; // @[RegisterRouter.scala:87:24] assign out_roready_1_424 = _out_rofireMux_T_1162; // @[RegisterRouter.scala:87:24] assign out_roready_1_425 = _out_rofireMux_T_1162; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1163 = ~_out_T_1707; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1165 = _out_rofireMux_T_260 & out_backSel_226; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1166 = _out_rofireMux_T_1165 & _out_T_1803; // @[RegisterRouter.scala:87:24] assign out_roready_1_779 = _out_rofireMux_T_1166; // @[RegisterRouter.scala:87:24] assign out_roready_1_780 = _out_rofireMux_T_1166; // @[RegisterRouter.scala:87:24] assign out_roready_1_781 = _out_rofireMux_T_1166; // @[RegisterRouter.scala:87:24] assign out_roready_1_782 = _out_rofireMux_T_1166; // @[RegisterRouter.scala:87:24] assign out_roready_1_783 = _out_rofireMux_T_1166; // @[RegisterRouter.scala:87:24] assign out_roready_1_784 = _out_rofireMux_T_1166; // @[RegisterRouter.scala:87:24] assign out_roready_1_785 = _out_rofireMux_T_1166; // @[RegisterRouter.scala:87:24] assign out_roready_1_786 = _out_rofireMux_T_1166; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1167 = ~_out_T_1803; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1169 = _out_rofireMux_T_260 & out_backSel_227; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1170 = _out_rofireMux_T_1169 & _out_T_1909; // @[RegisterRouter.scala:87:24] assign out_roready_1_1203 = _out_rofireMux_T_1170; // @[RegisterRouter.scala:87:24] assign out_roready_1_1204 = _out_rofireMux_T_1170; // @[RegisterRouter.scala:87:24] assign out_roready_1_1205 = _out_rofireMux_T_1170; // @[RegisterRouter.scala:87:24] assign out_roready_1_1206 = _out_rofireMux_T_1170; // @[RegisterRouter.scala:87:24] assign out_roready_1_1207 = _out_rofireMux_T_1170; // @[RegisterRouter.scala:87:24] assign out_roready_1_1208 = _out_rofireMux_T_1170; // @[RegisterRouter.scala:87:24] assign out_roready_1_1209 = _out_rofireMux_T_1170; // @[RegisterRouter.scala:87:24] assign out_roready_1_1210 = _out_rofireMux_T_1170; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1171 = ~_out_T_1909; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1173 = _out_rofireMux_T_260 & out_backSel_228; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1174 = _out_rofireMux_T_1173 & _out_T_1639; // @[RegisterRouter.scala:87:24] assign out_roready_1_152 = _out_rofireMux_T_1174; // @[RegisterRouter.scala:87:24] assign out_roready_1_153 = _out_rofireMux_T_1174; // @[RegisterRouter.scala:87:24] assign out_roready_1_154 = _out_rofireMux_T_1174; // @[RegisterRouter.scala:87:24] assign out_roready_1_155 = _out_rofireMux_T_1174; // @[RegisterRouter.scala:87:24] assign out_roready_1_156 = _out_rofireMux_T_1174; // @[RegisterRouter.scala:87:24] assign out_roready_1_157 = _out_rofireMux_T_1174; // @[RegisterRouter.scala:87:24] assign out_roready_1_158 = _out_rofireMux_T_1174; // @[RegisterRouter.scala:87:24] assign out_roready_1_159 = _out_rofireMux_T_1174; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1175 = ~_out_T_1639; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1177 = _out_rofireMux_T_260 & out_backSel_229; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1178 = _out_rofireMux_T_1177 & _out_T_1691; // @[RegisterRouter.scala:87:24] assign out_roready_1_354 = _out_rofireMux_T_1178; // @[RegisterRouter.scala:87:24] assign out_roready_1_355 = _out_rofireMux_T_1178; // @[RegisterRouter.scala:87:24] assign out_roready_1_356 = _out_rofireMux_T_1178; // @[RegisterRouter.scala:87:24] assign out_roready_1_357 = _out_rofireMux_T_1178; // @[RegisterRouter.scala:87:24] assign out_roready_1_358 = _out_rofireMux_T_1178; // @[RegisterRouter.scala:87:24] assign out_roready_1_359 = _out_rofireMux_T_1178; // @[RegisterRouter.scala:87:24] assign out_roready_1_360 = _out_rofireMux_T_1178; // @[RegisterRouter.scala:87:24] assign out_roready_1_361 = _out_rofireMux_T_1178; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1179 = ~_out_T_1691; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1181 = _out_rofireMux_T_260 & out_backSel_230; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1182 = _out_rofireMux_T_1181 & _out_T_1775; // @[RegisterRouter.scala:87:24] assign out_roready_1_673 = _out_rofireMux_T_1182; // @[RegisterRouter.scala:87:24] assign out_roready_1_674 = _out_rofireMux_T_1182; // @[RegisterRouter.scala:87:24] assign out_roready_1_675 = _out_rofireMux_T_1182; // @[RegisterRouter.scala:87:24] assign out_roready_1_676 = _out_rofireMux_T_1182; // @[RegisterRouter.scala:87:24] assign out_roready_1_677 = _out_rofireMux_T_1182; // @[RegisterRouter.scala:87:24] assign out_roready_1_678 = _out_rofireMux_T_1182; // @[RegisterRouter.scala:87:24] assign out_roready_1_679 = _out_rofireMux_T_1182; // @[RegisterRouter.scala:87:24] assign out_roready_1_680 = _out_rofireMux_T_1182; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1183 = ~_out_T_1775; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1185 = _out_rofireMux_T_260 & out_backSel_231; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1186 = _out_rofireMux_T_1185 & _out_T_1845; // @[RegisterRouter.scala:87:24] assign out_roready_1_947 = _out_rofireMux_T_1186; // @[RegisterRouter.scala:87:24] assign out_roready_1_948 = _out_rofireMux_T_1186; // @[RegisterRouter.scala:87:24] assign out_roready_1_949 = _out_rofireMux_T_1186; // @[RegisterRouter.scala:87:24] assign out_roready_1_950 = _out_rofireMux_T_1186; // @[RegisterRouter.scala:87:24] assign out_roready_1_951 = _out_rofireMux_T_1186; // @[RegisterRouter.scala:87:24] assign out_roready_1_952 = _out_rofireMux_T_1186; // @[RegisterRouter.scala:87:24] assign out_roready_1_953 = _out_rofireMux_T_1186; // @[RegisterRouter.scala:87:24] assign out_roready_1_954 = _out_rofireMux_T_1186; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1187 = ~_out_T_1845; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1189 = _out_rofireMux_T_260 & out_backSel_232; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1190 = _out_rofireMux_T_1189 & _out_T_1905; // @[RegisterRouter.scala:87:24] assign out_roready_1_1187 = _out_rofireMux_T_1190; // @[RegisterRouter.scala:87:24] assign out_roready_1_1188 = _out_rofireMux_T_1190; // @[RegisterRouter.scala:87:24] assign out_roready_1_1189 = _out_rofireMux_T_1190; // @[RegisterRouter.scala:87:24] assign out_roready_1_1190 = _out_rofireMux_T_1190; // @[RegisterRouter.scala:87:24] assign out_roready_1_1191 = _out_rofireMux_T_1190; // @[RegisterRouter.scala:87:24] assign out_roready_1_1192 = _out_rofireMux_T_1190; // @[RegisterRouter.scala:87:24] assign out_roready_1_1193 = _out_rofireMux_T_1190; // @[RegisterRouter.scala:87:24] assign out_roready_1_1194 = _out_rofireMux_T_1190; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1191 = ~_out_T_1905; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1193 = _out_rofireMux_T_260 & out_backSel_233; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1194 = _out_rofireMux_T_1193 & _out_T_1671; // @[RegisterRouter.scala:87:24] assign out_roready_1_280 = _out_rofireMux_T_1194; // @[RegisterRouter.scala:87:24] assign out_roready_1_281 = _out_rofireMux_T_1194; // @[RegisterRouter.scala:87:24] assign out_roready_1_282 = _out_rofireMux_T_1194; // @[RegisterRouter.scala:87:24] assign out_roready_1_283 = _out_rofireMux_T_1194; // @[RegisterRouter.scala:87:24] assign out_roready_1_284 = _out_rofireMux_T_1194; // @[RegisterRouter.scala:87:24] assign out_roready_1_285 = _out_rofireMux_T_1194; // @[RegisterRouter.scala:87:24] assign out_roready_1_286 = _out_rofireMux_T_1194; // @[RegisterRouter.scala:87:24] assign out_roready_1_287 = _out_rofireMux_T_1194; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1195 = ~_out_T_1671; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1197 = _out_rofireMux_T_260 & out_backSel_234; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1198 = _out_rofireMux_T_1197 & _out_T_1605; // @[RegisterRouter.scala:87:24] assign out_roready_1_16 = _out_rofireMux_T_1198; // @[RegisterRouter.scala:87:24] assign out_roready_1_17 = _out_rofireMux_T_1198; // @[RegisterRouter.scala:87:24] assign out_roready_1_18 = _out_rofireMux_T_1198; // @[RegisterRouter.scala:87:24] assign out_roready_1_19 = _out_rofireMux_T_1198; // @[RegisterRouter.scala:87:24] assign out_roready_1_20 = _out_rofireMux_T_1198; // @[RegisterRouter.scala:87:24] assign out_roready_1_21 = _out_rofireMux_T_1198; // @[RegisterRouter.scala:87:24] assign out_roready_1_22 = _out_rofireMux_T_1198; // @[RegisterRouter.scala:87:24] assign out_roready_1_23 = _out_rofireMux_T_1198; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1199 = ~_out_T_1605; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1201 = _out_rofireMux_T_260 & out_backSel_235; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1202 = _out_rofireMux_T_1201 & _out_T_1863; // @[RegisterRouter.scala:87:24] assign out_roready_1_1019 = _out_rofireMux_T_1202; // @[RegisterRouter.scala:87:24] assign out_roready_1_1020 = _out_rofireMux_T_1202; // @[RegisterRouter.scala:87:24] assign out_roready_1_1021 = _out_rofireMux_T_1202; // @[RegisterRouter.scala:87:24] assign out_roready_1_1022 = _out_rofireMux_T_1202; // @[RegisterRouter.scala:87:24] assign out_roready_1_1023 = _out_rofireMux_T_1202; // @[RegisterRouter.scala:87:24] assign out_roready_1_1024 = _out_rofireMux_T_1202; // @[RegisterRouter.scala:87:24] assign out_roready_1_1025 = _out_rofireMux_T_1202; // @[RegisterRouter.scala:87:24] assign out_roready_1_1026 = _out_rofireMux_T_1202; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1203 = ~_out_T_1863; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1205 = _out_rofireMux_T_260 & out_backSel_236; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1206 = _out_rofireMux_T_1205 & _out_T_1761; // @[RegisterRouter.scala:87:24] assign out_roready_1_617 = _out_rofireMux_T_1206; // @[RegisterRouter.scala:87:24] assign out_roready_1_618 = _out_rofireMux_T_1206; // @[RegisterRouter.scala:87:24] assign out_roready_1_619 = _out_rofireMux_T_1206; // @[RegisterRouter.scala:87:24] assign out_roready_1_620 = _out_rofireMux_T_1206; // @[RegisterRouter.scala:87:24] assign out_roready_1_621 = _out_rofireMux_T_1206; // @[RegisterRouter.scala:87:24] assign out_roready_1_622 = _out_rofireMux_T_1206; // @[RegisterRouter.scala:87:24] assign out_roready_1_623 = _out_rofireMux_T_1206; // @[RegisterRouter.scala:87:24] assign out_roready_1_624 = _out_rofireMux_T_1206; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1207 = ~_out_T_1761; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1209 = _out_rofireMux_T_260 & out_backSel_237; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1210 = _out_rofireMux_T_1209 & _out_T_1731; // @[RegisterRouter.scala:87:24] assign out_roready_1_503 = _out_rofireMux_T_1210; // @[RegisterRouter.scala:87:24] assign out_roready_1_504 = _out_rofireMux_T_1210; // @[RegisterRouter.scala:87:24] assign out_roready_1_505 = _out_rofireMux_T_1210; // @[RegisterRouter.scala:87:24] assign out_roready_1_506 = _out_rofireMux_T_1210; // @[RegisterRouter.scala:87:24] assign out_roready_1_507 = _out_rofireMux_T_1210; // @[RegisterRouter.scala:87:24] assign out_roready_1_508 = _out_rofireMux_T_1210; // @[RegisterRouter.scala:87:24] assign out_roready_1_509 = _out_rofireMux_T_1210; // @[RegisterRouter.scala:87:24] assign out_roready_1_510 = _out_rofireMux_T_1210; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1211 = ~_out_T_1731; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1213 = _out_rofireMux_T_260 & out_backSel_238; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1214 = _out_rofireMux_T_1213 & _out_T_1651; // @[RegisterRouter.scala:87:24] assign out_roready_1_200 = _out_rofireMux_T_1214; // @[RegisterRouter.scala:87:24] assign out_roready_1_201 = _out_rofireMux_T_1214; // @[RegisterRouter.scala:87:24] assign out_roready_1_202 = _out_rofireMux_T_1214; // @[RegisterRouter.scala:87:24] assign out_roready_1_203 = _out_rofireMux_T_1214; // @[RegisterRouter.scala:87:24] assign out_roready_1_204 = _out_rofireMux_T_1214; // @[RegisterRouter.scala:87:24] assign out_roready_1_205 = _out_rofireMux_T_1214; // @[RegisterRouter.scala:87:24] assign out_roready_1_206 = _out_rofireMux_T_1214; // @[RegisterRouter.scala:87:24] assign out_roready_1_207 = _out_rofireMux_T_1214; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1215 = ~_out_T_1651; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1217 = _out_rofireMux_T_260 & out_backSel_239; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1218 = _out_rofireMux_T_1217 & _out_T_1887; // @[RegisterRouter.scala:87:24] assign out_roready_1_1115 = _out_rofireMux_T_1218; // @[RegisterRouter.scala:87:24] assign out_roready_1_1116 = _out_rofireMux_T_1218; // @[RegisterRouter.scala:87:24] assign out_roready_1_1117 = _out_rofireMux_T_1218; // @[RegisterRouter.scala:87:24] assign out_roready_1_1118 = _out_rofireMux_T_1218; // @[RegisterRouter.scala:87:24] assign out_roready_1_1119 = _out_rofireMux_T_1218; // @[RegisterRouter.scala:87:24] assign out_roready_1_1120 = _out_rofireMux_T_1218; // @[RegisterRouter.scala:87:24] assign out_roready_1_1121 = _out_rofireMux_T_1218; // @[RegisterRouter.scala:87:24] assign out_roready_1_1122 = _out_rofireMux_T_1218; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1219 = ~_out_T_1887; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1221 = _out_rofireMux_T_260 & out_backSel_240; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1222 = _out_rofireMux_T_1221 & _out_T_1793; // @[RegisterRouter.scala:87:24] assign out_roready_1_739 = _out_rofireMux_T_1222; // @[RegisterRouter.scala:87:24] assign out_roready_1_740 = _out_rofireMux_T_1222; // @[RegisterRouter.scala:87:24] assign out_roready_1_741 = _out_rofireMux_T_1222; // @[RegisterRouter.scala:87:24] assign out_roready_1_742 = _out_rofireMux_T_1222; // @[RegisterRouter.scala:87:24] assign out_roready_1_743 = _out_rofireMux_T_1222; // @[RegisterRouter.scala:87:24] assign out_roready_1_744 = _out_rofireMux_T_1222; // @[RegisterRouter.scala:87:24] assign out_roready_1_745 = _out_rofireMux_T_1222; // @[RegisterRouter.scala:87:24] assign out_roready_1_746 = _out_rofireMux_T_1222; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1223 = ~_out_T_1793; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1225 = _out_rofireMux_T_260 & out_backSel_241; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1226 = _out_rofireMux_T_1225 & _out_T_1805; // @[RegisterRouter.scala:87:24] assign out_roready_1_787 = _out_rofireMux_T_1226; // @[RegisterRouter.scala:87:24] assign out_roready_1_788 = _out_rofireMux_T_1226; // @[RegisterRouter.scala:87:24] assign out_roready_1_789 = _out_rofireMux_T_1226; // @[RegisterRouter.scala:87:24] assign out_roready_1_790 = _out_rofireMux_T_1226; // @[RegisterRouter.scala:87:24] assign out_roready_1_791 = _out_rofireMux_T_1226; // @[RegisterRouter.scala:87:24] assign out_roready_1_792 = _out_rofireMux_T_1226; // @[RegisterRouter.scala:87:24] assign out_roready_1_793 = _out_rofireMux_T_1226; // @[RegisterRouter.scala:87:24] assign out_roready_1_794 = _out_rofireMux_T_1226; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1227 = ~_out_T_1805; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1229 = _out_rofireMux_T_260 & out_backSel_242; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1230 = _out_rofireMux_T_1229 & _out_T_1889; // @[RegisterRouter.scala:87:24] assign out_roready_1_1123 = _out_rofireMux_T_1230; // @[RegisterRouter.scala:87:24] assign out_roready_1_1124 = _out_rofireMux_T_1230; // @[RegisterRouter.scala:87:24] assign out_roready_1_1125 = _out_rofireMux_T_1230; // @[RegisterRouter.scala:87:24] assign out_roready_1_1126 = _out_rofireMux_T_1230; // @[RegisterRouter.scala:87:24] assign out_roready_1_1127 = _out_rofireMux_T_1230; // @[RegisterRouter.scala:87:24] assign out_roready_1_1128 = _out_rofireMux_T_1230; // @[RegisterRouter.scala:87:24] assign out_roready_1_1129 = _out_rofireMux_T_1230; // @[RegisterRouter.scala:87:24] assign out_roready_1_1130 = _out_rofireMux_T_1230; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1231 = ~_out_T_1889; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1233 = _out_rofireMux_T_260 & out_backSel_243; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1234 = _out_rofireMux_T_1233 & _out_T_1665; // @[RegisterRouter.scala:87:24] assign out_roready_1_256 = _out_rofireMux_T_1234; // @[RegisterRouter.scala:87:24] assign out_roready_1_257 = _out_rofireMux_T_1234; // @[RegisterRouter.scala:87:24] assign out_roready_1_258 = _out_rofireMux_T_1234; // @[RegisterRouter.scala:87:24] assign out_roready_1_259 = _out_rofireMux_T_1234; // @[RegisterRouter.scala:87:24] assign out_roready_1_260 = _out_rofireMux_T_1234; // @[RegisterRouter.scala:87:24] assign out_roready_1_261 = _out_rofireMux_T_1234; // @[RegisterRouter.scala:87:24] assign out_roready_1_262 = _out_rofireMux_T_1234; // @[RegisterRouter.scala:87:24] assign out_roready_1_263 = _out_rofireMux_T_1234; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1235 = ~_out_T_1665; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1237 = _out_rofireMux_T_260 & out_backSel_244; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1238 = _out_rofireMux_T_1237 & _out_T_1735; // @[RegisterRouter.scala:87:24] assign out_roready_1_519 = _out_rofireMux_T_1238; // @[RegisterRouter.scala:87:24] assign out_roready_1_520 = _out_rofireMux_T_1238; // @[RegisterRouter.scala:87:24] assign out_roready_1_521 = _out_rofireMux_T_1238; // @[RegisterRouter.scala:87:24] assign out_roready_1_522 = _out_rofireMux_T_1238; // @[RegisterRouter.scala:87:24] assign out_roready_1_523 = _out_rofireMux_T_1238; // @[RegisterRouter.scala:87:24] assign out_roready_1_524 = _out_rofireMux_T_1238; // @[RegisterRouter.scala:87:24] assign out_roready_1_525 = _out_rofireMux_T_1238; // @[RegisterRouter.scala:87:24] assign out_roready_1_526 = _out_rofireMux_T_1238; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1239 = ~_out_T_1735; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1241 = _out_rofireMux_T_260 & out_backSel_245; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1242 = _out_rofireMux_T_1241 & _out_T_1777; // @[RegisterRouter.scala:87:24] assign out_roready_1_681 = _out_rofireMux_T_1242; // @[RegisterRouter.scala:87:24] assign out_roready_1_682 = _out_rofireMux_T_1242; // @[RegisterRouter.scala:87:24] assign out_roready_1_683 = _out_rofireMux_T_1242; // @[RegisterRouter.scala:87:24] assign out_roready_1_684 = _out_rofireMux_T_1242; // @[RegisterRouter.scala:87:24] assign out_roready_1_685 = _out_rofireMux_T_1242; // @[RegisterRouter.scala:87:24] assign out_roready_1_686 = _out_rofireMux_T_1242; // @[RegisterRouter.scala:87:24] assign out_roready_1_687 = _out_rofireMux_T_1242; // @[RegisterRouter.scala:87:24] assign out_roready_1_688 = _out_rofireMux_T_1242; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1243 = ~_out_T_1777; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1245 = _out_rofireMux_T_260 & out_backSel_246; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1246 = _out_rofireMux_T_1245 & _out_T_1865; // @[RegisterRouter.scala:87:24] assign out_roready_1_1027 = _out_rofireMux_T_1246; // @[RegisterRouter.scala:87:24] assign out_roready_1_1028 = _out_rofireMux_T_1246; // @[RegisterRouter.scala:87:24] assign out_roready_1_1029 = _out_rofireMux_T_1246; // @[RegisterRouter.scala:87:24] assign out_roready_1_1030 = _out_rofireMux_T_1246; // @[RegisterRouter.scala:87:24] assign out_roready_1_1031 = _out_rofireMux_T_1246; // @[RegisterRouter.scala:87:24] assign out_roready_1_1032 = _out_rofireMux_T_1246; // @[RegisterRouter.scala:87:24] assign out_roready_1_1033 = _out_rofireMux_T_1246; // @[RegisterRouter.scala:87:24] assign out_roready_1_1034 = _out_rofireMux_T_1246; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1247 = ~_out_T_1865; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1249 = _out_rofireMux_T_260 & out_backSel_247; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1250 = _out_rofireMux_T_1249 & _out_T_1613; // @[RegisterRouter.scala:87:24] assign out_roready_1_48 = _out_rofireMux_T_1250; // @[RegisterRouter.scala:87:24] assign out_roready_1_49 = _out_rofireMux_T_1250; // @[RegisterRouter.scala:87:24] assign out_roready_1_50 = _out_rofireMux_T_1250; // @[RegisterRouter.scala:87:24] assign out_roready_1_51 = _out_rofireMux_T_1250; // @[RegisterRouter.scala:87:24] assign out_roready_1_52 = _out_rofireMux_T_1250; // @[RegisterRouter.scala:87:24] assign out_roready_1_53 = _out_rofireMux_T_1250; // @[RegisterRouter.scala:87:24] assign out_roready_1_54 = _out_rofireMux_T_1250; // @[RegisterRouter.scala:87:24] assign out_roready_1_55 = _out_rofireMux_T_1250; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1251 = ~_out_T_1613; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1253 = _out_rofireMux_T_260 & out_backSel_248; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1254 = _out_rofireMux_T_1253 & _out_T_1673; // @[RegisterRouter.scala:87:24] assign out_roready_1_288 = _out_rofireMux_T_1254; // @[RegisterRouter.scala:87:24] assign out_roready_1_289 = _out_rofireMux_T_1254; // @[RegisterRouter.scala:87:24] assign out_roready_1_290 = _out_rofireMux_T_1254; // @[RegisterRouter.scala:87:24] assign out_roready_1_291 = _out_rofireMux_T_1254; // @[RegisterRouter.scala:87:24] assign out_roready_1_292 = _out_rofireMux_T_1254; // @[RegisterRouter.scala:87:24] assign out_roready_1_293 = _out_rofireMux_T_1254; // @[RegisterRouter.scala:87:24] assign out_roready_1_294 = _out_rofireMux_T_1254; // @[RegisterRouter.scala:87:24] assign out_roready_1_295 = _out_rofireMux_T_1254; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1255 = ~_out_T_1673; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1257 = _out_rofireMux_T_260 & out_backSel_249; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1258 = _out_rofireMux_T_1257 & _out_T_1603; // @[RegisterRouter.scala:87:24] assign out_roready_1_8 = _out_rofireMux_T_1258; // @[RegisterRouter.scala:87:24] assign out_roready_1_9 = _out_rofireMux_T_1258; // @[RegisterRouter.scala:87:24] assign out_roready_1_10 = _out_rofireMux_T_1258; // @[RegisterRouter.scala:87:24] assign out_roready_1_11 = _out_rofireMux_T_1258; // @[RegisterRouter.scala:87:24] assign out_roready_1_12 = _out_rofireMux_T_1258; // @[RegisterRouter.scala:87:24] assign out_roready_1_13 = _out_rofireMux_T_1258; // @[RegisterRouter.scala:87:24] assign out_roready_1_14 = _out_rofireMux_T_1258; // @[RegisterRouter.scala:87:24] assign out_roready_1_15 = _out_rofireMux_T_1258; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1259 = ~_out_T_1603; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1261 = _out_rofireMux_T_260 & out_backSel_250; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1262 = _out_rofireMux_T_1261 & _out_T_1843; // @[RegisterRouter.scala:87:24] assign out_roready_1_939 = _out_rofireMux_T_1262; // @[RegisterRouter.scala:87:24] assign out_roready_1_940 = _out_rofireMux_T_1262; // @[RegisterRouter.scala:87:24] assign out_roready_1_941 = _out_rofireMux_T_1262; // @[RegisterRouter.scala:87:24] assign out_roready_1_942 = _out_rofireMux_T_1262; // @[RegisterRouter.scala:87:24] assign out_roready_1_943 = _out_rofireMux_T_1262; // @[RegisterRouter.scala:87:24] assign out_roready_1_944 = _out_rofireMux_T_1262; // @[RegisterRouter.scala:87:24] assign out_roready_1_945 = _out_rofireMux_T_1262; // @[RegisterRouter.scala:87:24] assign out_roready_1_946 = _out_rofireMux_T_1262; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1263 = ~_out_T_1843; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1265 = _out_rofireMux_T_260 & out_backSel_251; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1266 = _out_rofireMux_T_1265 & _out_T_1795; // @[RegisterRouter.scala:87:24] assign out_roready_1_747 = _out_rofireMux_T_1266; // @[RegisterRouter.scala:87:24] assign out_roready_1_748 = _out_rofireMux_T_1266; // @[RegisterRouter.scala:87:24] assign out_roready_1_749 = _out_rofireMux_T_1266; // @[RegisterRouter.scala:87:24] assign out_roready_1_750 = _out_rofireMux_T_1266; // @[RegisterRouter.scala:87:24] assign out_roready_1_751 = _out_rofireMux_T_1266; // @[RegisterRouter.scala:87:24] assign out_roready_1_752 = _out_rofireMux_T_1266; // @[RegisterRouter.scala:87:24] assign out_roready_1_753 = _out_rofireMux_T_1266; // @[RegisterRouter.scala:87:24] assign out_roready_1_754 = _out_rofireMux_T_1266; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1267 = ~_out_T_1795; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1269 = _out_rofireMux_T_260 & out_backSel_252; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1270 = _out_rofireMux_T_1269 & _out_T_1693; // @[RegisterRouter.scala:87:24] assign out_roready_1_362 = _out_rofireMux_T_1270; // @[RegisterRouter.scala:87:24] assign out_roready_1_363 = _out_rofireMux_T_1270; // @[RegisterRouter.scala:87:24] assign out_roready_1_364 = _out_rofireMux_T_1270; // @[RegisterRouter.scala:87:24] assign out_roready_1_365 = _out_rofireMux_T_1270; // @[RegisterRouter.scala:87:24] assign out_roready_1_366 = _out_rofireMux_T_1270; // @[RegisterRouter.scala:87:24] assign out_roready_1_367 = _out_rofireMux_T_1270; // @[RegisterRouter.scala:87:24] assign out_roready_1_368 = _out_rofireMux_T_1270; // @[RegisterRouter.scala:87:24] assign out_roready_1_369 = _out_rofireMux_T_1270; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1271 = ~_out_T_1693; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1273 = _out_rofireMux_T_260 & out_backSel_253; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1274 = _out_rofireMux_T_1273 & _out_T_1655; // @[RegisterRouter.scala:87:24] assign out_roready_1_216 = _out_rofireMux_T_1274; // @[RegisterRouter.scala:87:24] assign out_roready_1_217 = _out_rofireMux_T_1274; // @[RegisterRouter.scala:87:24] assign out_roready_1_218 = _out_rofireMux_T_1274; // @[RegisterRouter.scala:87:24] assign out_roready_1_219 = _out_rofireMux_T_1274; // @[RegisterRouter.scala:87:24] assign out_roready_1_220 = _out_rofireMux_T_1274; // @[RegisterRouter.scala:87:24] assign out_roready_1_221 = _out_rofireMux_T_1274; // @[RegisterRouter.scala:87:24] assign out_roready_1_222 = _out_rofireMux_T_1274; // @[RegisterRouter.scala:87:24] assign out_roready_1_223 = _out_rofireMux_T_1274; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1275 = ~_out_T_1655; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1277 = _out_rofireMux_T_260 & out_backSel_254; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1278 = _out_rofireMux_T_1277 & _out_T_1907; // @[RegisterRouter.scala:87:24] assign out_roready_1_1195 = _out_rofireMux_T_1278; // @[RegisterRouter.scala:87:24] assign out_roready_1_1196 = _out_rofireMux_T_1278; // @[RegisterRouter.scala:87:24] assign out_roready_1_1197 = _out_rofireMux_T_1278; // @[RegisterRouter.scala:87:24] assign out_roready_1_1198 = _out_rofireMux_T_1278; // @[RegisterRouter.scala:87:24] assign out_roready_1_1199 = _out_rofireMux_T_1278; // @[RegisterRouter.scala:87:24] assign out_roready_1_1200 = _out_rofireMux_T_1278; // @[RegisterRouter.scala:87:24] assign out_roready_1_1201 = _out_rofireMux_T_1278; // @[RegisterRouter.scala:87:24] assign out_roready_1_1202 = _out_rofireMux_T_1278; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1279 = ~_out_T_1907; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1281 = _out_rofireMux_T_260 & out_backSel_255; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1282 = _out_rofireMux_T_1281 & _out_T_1811; // @[RegisterRouter.scala:87:24] assign out_roready_1_811 = _out_rofireMux_T_1282; // @[RegisterRouter.scala:87:24] assign out_roready_1_812 = _out_rofireMux_T_1282; // @[RegisterRouter.scala:87:24] assign out_roready_1_813 = _out_rofireMux_T_1282; // @[RegisterRouter.scala:87:24] assign out_roready_1_814 = _out_rofireMux_T_1282; // @[RegisterRouter.scala:87:24] assign out_roready_1_815 = _out_rofireMux_T_1282; // @[RegisterRouter.scala:87:24] assign out_roready_1_816 = _out_rofireMux_T_1282; // @[RegisterRouter.scala:87:24] assign out_roready_1_817 = _out_rofireMux_T_1282; // @[RegisterRouter.scala:87:24] assign out_roready_1_818 = _out_rofireMux_T_1282; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1283 = ~_out_T_1811; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_261 = ~out_front_1_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_262 = _out_wofireMux_T_260 & _out_wofireMux_T_261; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_263 = _out_wofireMux_T_262 & out_backSel_0_1; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_264 = _out_wofireMux_T_263 & _out_T_1717; // @[RegisterRouter.scala:87:24] assign out_woready_1_451 = _out_wofireMux_T_264; // @[RegisterRouter.scala:87:24] assign out_woready_1_452 = _out_wofireMux_T_264; // @[RegisterRouter.scala:87:24] assign out_woready_1_453 = _out_wofireMux_T_264; // @[RegisterRouter.scala:87:24] assign out_woready_1_454 = _out_wofireMux_T_264; // @[RegisterRouter.scala:87:24] assign out_woready_1_455 = _out_wofireMux_T_264; // @[RegisterRouter.scala:87:24] assign out_woready_1_456 = _out_wofireMux_T_264; // @[RegisterRouter.scala:87:24] assign out_woready_1_457 = _out_wofireMux_T_264; // @[RegisterRouter.scala:87:24] assign out_woready_1_458 = _out_wofireMux_T_264; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_265 = ~_out_T_1717; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_267 = _out_wofireMux_T_262 & out_backSel_1_1; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_268 = _out_wofireMux_T_267 & _out_T_1625; // @[RegisterRouter.scala:87:24] assign out_woready_1_96 = _out_wofireMux_T_268; // @[RegisterRouter.scala:87:24] assign out_woready_1_97 = _out_wofireMux_T_268; // @[RegisterRouter.scala:87:24] assign out_woready_1_98 = _out_wofireMux_T_268; // @[RegisterRouter.scala:87:24] assign out_woready_1_99 = _out_wofireMux_T_268; // @[RegisterRouter.scala:87:24] assign out_woready_1_100 = _out_wofireMux_T_268; // @[RegisterRouter.scala:87:24] assign out_woready_1_101 = _out_wofireMux_T_268; // @[RegisterRouter.scala:87:24] assign out_woready_1_102 = _out_wofireMux_T_268; // @[RegisterRouter.scala:87:24] assign out_woready_1_103 = _out_wofireMux_T_268; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_269 = ~_out_T_1625; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_271 = _out_wofireMux_T_262 & out_backSel_2_1; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_272 = _out_wofireMux_T_271 & _out_T_1847; // @[RegisterRouter.scala:87:24] assign out_woready_1_955 = _out_wofireMux_T_272; // @[RegisterRouter.scala:87:24] assign out_woready_1_956 = _out_wofireMux_T_272; // @[RegisterRouter.scala:87:24] assign out_woready_1_957 = _out_wofireMux_T_272; // @[RegisterRouter.scala:87:24] assign out_woready_1_958 = _out_wofireMux_T_272; // @[RegisterRouter.scala:87:24] assign out_woready_1_959 = _out_wofireMux_T_272; // @[RegisterRouter.scala:87:24] assign out_woready_1_960 = _out_wofireMux_T_272; // @[RegisterRouter.scala:87:24] assign out_woready_1_961 = _out_wofireMux_T_272; // @[RegisterRouter.scala:87:24] assign out_woready_1_962 = _out_wofireMux_T_272; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_273 = ~_out_T_1847; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_275 = _out_wofireMux_T_262 & out_backSel_3_1; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_276 = _out_wofireMux_T_275 & _out_T_1757; // @[RegisterRouter.scala:87:24] assign out_woready_1_601 = _out_wofireMux_T_276; // @[RegisterRouter.scala:87:24] assign out_woready_1_602 = _out_wofireMux_T_276; // @[RegisterRouter.scala:87:24] assign out_woready_1_603 = _out_wofireMux_T_276; // @[RegisterRouter.scala:87:24] assign out_woready_1_604 = _out_wofireMux_T_276; // @[RegisterRouter.scala:87:24] assign out_woready_1_605 = _out_wofireMux_T_276; // @[RegisterRouter.scala:87:24] assign out_woready_1_606 = _out_wofireMux_T_276; // @[RegisterRouter.scala:87:24] assign out_woready_1_607 = _out_wofireMux_T_276; // @[RegisterRouter.scala:87:24] assign out_woready_1_608 = _out_wofireMux_T_276; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_277 = ~_out_T_1757; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_279 = _out_wofireMux_T_262 & out_backSel_4_1; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_280 = _out_wofireMux_T_279 & _out_T_1679; // @[RegisterRouter.scala:87:24] assign out_woready_1_312 = _out_wofireMux_T_280; // @[RegisterRouter.scala:87:24] assign out_woready_1_313 = _out_wofireMux_T_280; // @[RegisterRouter.scala:87:24] assign out_woready_1_314 = _out_wofireMux_T_280; // @[RegisterRouter.scala:87:24] assign out_woready_1_315 = _out_wofireMux_T_280; // @[RegisterRouter.scala:87:24] assign out_woready_1_316 = _out_wofireMux_T_280; // @[RegisterRouter.scala:87:24] assign out_woready_1_317 = _out_wofireMux_T_280; // @[RegisterRouter.scala:87:24] assign out_woready_1_318 = _out_wofireMux_T_280; // @[RegisterRouter.scala:87:24] assign out_woready_1_319 = _out_wofireMux_T_280; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_281 = ~_out_T_1679; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_283 = _out_wofireMux_T_262 & out_backSel_5_1; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_284 = _out_wofireMux_T_283 & _out_T_1641; // @[RegisterRouter.scala:87:24] assign out_woready_1_160 = _out_wofireMux_T_284; // @[RegisterRouter.scala:87:24] assign out_woready_1_161 = _out_wofireMux_T_284; // @[RegisterRouter.scala:87:24] assign out_woready_1_162 = _out_wofireMux_T_284; // @[RegisterRouter.scala:87:24] assign out_woready_1_163 = _out_wofireMux_T_284; // @[RegisterRouter.scala:87:24] assign out_woready_1_164 = _out_wofireMux_T_284; // @[RegisterRouter.scala:87:24] assign out_woready_1_165 = _out_wofireMux_T_284; // @[RegisterRouter.scala:87:24] assign out_woready_1_166 = _out_wofireMux_T_284; // @[RegisterRouter.scala:87:24] assign out_woready_1_167 = _out_wofireMux_T_284; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_285 = ~_out_T_1641; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_287 = _out_wofireMux_T_262 & out_backSel_6_1; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_288 = _out_wofireMux_T_287 & _out_T_1877; // @[RegisterRouter.scala:87:24] assign out_woready_1_1075 = _out_wofireMux_T_288; // @[RegisterRouter.scala:87:24] assign out_woready_1_1076 = _out_wofireMux_T_288; // @[RegisterRouter.scala:87:24] assign out_woready_1_1077 = _out_wofireMux_T_288; // @[RegisterRouter.scala:87:24] assign out_woready_1_1078 = _out_wofireMux_T_288; // @[RegisterRouter.scala:87:24] assign out_woready_1_1079 = _out_wofireMux_T_288; // @[RegisterRouter.scala:87:24] assign out_woready_1_1080 = _out_wofireMux_T_288; // @[RegisterRouter.scala:87:24] assign out_woready_1_1081 = _out_wofireMux_T_288; // @[RegisterRouter.scala:87:24] assign out_woready_1_1082 = _out_wofireMux_T_288; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_289 = ~_out_T_1877; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_291 = _out_wofireMux_T_262 & out_backSel_7_1; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_292 = _out_wofireMux_T_291 & _out_T_1823; // @[RegisterRouter.scala:87:24] assign out_woready_1_859 = _out_wofireMux_T_292; // @[RegisterRouter.scala:87:24] assign out_woready_1_860 = _out_wofireMux_T_292; // @[RegisterRouter.scala:87:24] assign out_woready_1_861 = _out_wofireMux_T_292; // @[RegisterRouter.scala:87:24] assign out_woready_1_862 = _out_wofireMux_T_292; // @[RegisterRouter.scala:87:24] assign out_woready_1_863 = _out_wofireMux_T_292; // @[RegisterRouter.scala:87:24] assign out_woready_1_864 = _out_wofireMux_T_292; // @[RegisterRouter.scala:87:24] assign out_woready_1_865 = _out_wofireMux_T_292; // @[RegisterRouter.scala:87:24] assign out_woready_1_866 = _out_wofireMux_T_292; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_293 = ~_out_T_1823; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_295 = _out_wofireMux_T_262 & out_backSel_8_1; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_296 = _out_wofireMux_T_295 & _out_T_1743; // @[RegisterRouter.scala:87:24] assign out_woready_1_545 = _out_wofireMux_T_296; // @[RegisterRouter.scala:87:24] assign out_woready_1_546 = _out_wofireMux_T_296; // @[RegisterRouter.scala:87:24] assign out_woready_1_547 = _out_wofireMux_T_296; // @[RegisterRouter.scala:87:24] assign out_woready_1_548 = _out_wofireMux_T_296; // @[RegisterRouter.scala:87:24] assign out_woready_1_549 = _out_wofireMux_T_296; // @[RegisterRouter.scala:87:24] assign out_woready_1_550 = _out_wofireMux_T_296; // @[RegisterRouter.scala:87:24] assign out_woready_1_551 = _out_wofireMux_T_296; // @[RegisterRouter.scala:87:24] assign out_woready_1_552 = _out_wofireMux_T_296; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_297 = ~_out_T_1743; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_299 = _out_wofireMux_T_262 & out_backSel_9_1; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_300 = _out_wofireMux_T_299 & _out_T_1667; // @[RegisterRouter.scala:87:24] assign out_woready_1_264 = _out_wofireMux_T_300; // @[RegisterRouter.scala:87:24] assign out_woready_1_265 = _out_wofireMux_T_300; // @[RegisterRouter.scala:87:24] assign out_woready_1_266 = _out_wofireMux_T_300; // @[RegisterRouter.scala:87:24] assign out_woready_1_267 = _out_wofireMux_T_300; // @[RegisterRouter.scala:87:24] assign out_woready_1_268 = _out_wofireMux_T_300; // @[RegisterRouter.scala:87:24] assign out_woready_1_269 = _out_wofireMux_T_300; // @[RegisterRouter.scala:87:24] assign out_woready_1_270 = _out_wofireMux_T_300; // @[RegisterRouter.scala:87:24] assign out_woready_1_271 = _out_wofireMux_T_300; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_301 = ~_out_T_1667; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_303 = _out_wofireMux_T_262 & out_backSel_10_1; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_304 = _out_wofireMux_T_303 & _out_T_1725; // @[RegisterRouter.scala:87:24] assign out_woready_1_483 = _out_wofireMux_T_304; // @[RegisterRouter.scala:87:24] assign out_woready_1_484 = _out_wofireMux_T_304; // @[RegisterRouter.scala:87:24] assign out_woready_1_485 = _out_wofireMux_T_304; // @[RegisterRouter.scala:87:24] assign out_woready_1_486 = _out_wofireMux_T_304; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_305 = ~_out_T_1725; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_307 = _out_wofireMux_T_262 & out_backSel_11_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_308 = _out_wofireMux_T_307; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_311 = _out_wofireMux_T_262 & out_backSel_12_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_312 = _out_wofireMux_T_311; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_315 = _out_wofireMux_T_262 & out_backSel_13_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_316 = _out_wofireMux_T_315; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_319 = _out_wofireMux_T_262 & out_backSel_14_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_320 = _out_wofireMux_T_319; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_323 = _out_wofireMux_T_262 & out_backSel_15_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_324 = _out_wofireMux_T_323; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_327 = _out_wofireMux_T_262 & out_backSel_16_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_328 = _out_wofireMux_T_327; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_331 = _out_wofireMux_T_262 & out_backSel_17_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_332 = _out_wofireMux_T_331; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_335 = _out_wofireMux_T_262 & out_backSel_18_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_336 = _out_wofireMux_T_335; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_339 = _out_wofireMux_T_262 & out_backSel_19_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_340 = _out_wofireMux_T_339; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_343 = _out_wofireMux_T_262 & out_backSel_20_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_344 = _out_wofireMux_T_343; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_347 = _out_wofireMux_T_262 & out_backSel_21_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_348 = _out_wofireMux_T_347; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_351 = _out_wofireMux_T_262 & out_backSel_22_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_352 = _out_wofireMux_T_351; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_355 = _out_wofireMux_T_262 & out_backSel_23_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_356 = _out_wofireMux_T_355; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_359 = _out_wofireMux_T_262 & out_backSel_24_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_360 = _out_wofireMux_T_359; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_363 = _out_wofireMux_T_262 & out_backSel_25_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_364 = _out_wofireMux_T_363; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_367 = _out_wofireMux_T_262 & out_backSel_26_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_368 = _out_wofireMux_T_367; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_371 = _out_wofireMux_T_262 & out_backSel_27_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_372 = _out_wofireMux_T_371; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_375 = _out_wofireMux_T_262 & out_backSel_28_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_376 = _out_wofireMux_T_375; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_379 = _out_wofireMux_T_262 & out_backSel_29_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_380 = _out_wofireMux_T_379; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_383 = _out_wofireMux_T_262 & out_backSel_30_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_384 = _out_wofireMux_T_383; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_387 = _out_wofireMux_T_262 & out_backSel_31_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_388 = _out_wofireMux_T_387; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_391 = _out_wofireMux_T_262 & out_backSel_32_1; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_392 = _out_wofireMux_T_391 & _out_T_1739; // @[RegisterRouter.scala:87:24] assign out_woready_1_535 = _out_wofireMux_T_392; // @[RegisterRouter.scala:87:24] assign out_woready_1_536 = _out_wofireMux_T_392; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_393 = ~_out_T_1739; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_395 = _out_wofireMux_T_262 & out_backSel_33_1; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_396 = _out_wofireMux_T_395 & _out_T_1689; // @[RegisterRouter.scala:87:24] assign out_woready_1_352 = _out_wofireMux_T_396; // @[RegisterRouter.scala:87:24] assign out_woready_1_353 = _out_wofireMux_T_396; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_397 = ~_out_T_1689; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_399 = _out_wofireMux_T_262 & out_backSel_34_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_400 = _out_wofireMux_T_399; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_403 = _out_wofireMux_T_262 & out_backSel_35_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_404 = _out_wofireMux_T_403; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_407 = _out_wofireMux_T_262 & out_backSel_36_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_408 = _out_wofireMux_T_407; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_411 = _out_wofireMux_T_262 & out_backSel_37_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_412 = _out_wofireMux_T_411; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_415 = _out_wofireMux_T_262 & out_backSel_38_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_416 = _out_wofireMux_T_415; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_419 = _out_wofireMux_T_262 & out_backSel_39_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_420 = _out_wofireMux_T_419; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_423 = _out_wofireMux_T_262 & out_backSel_40_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_424 = _out_wofireMux_T_423; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_427 = _out_wofireMux_T_262 & out_backSel_41_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_428 = _out_wofireMux_T_427; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_431 = _out_wofireMux_T_262 & out_backSel_42_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_432 = _out_wofireMux_T_431; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_435 = _out_wofireMux_T_262 & out_backSel_43_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_436 = _out_wofireMux_T_435; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_439 = _out_wofireMux_T_262 & out_backSel_44_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_440 = _out_wofireMux_T_439; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_443 = _out_wofireMux_T_262 & out_backSel_45_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_444 = _out_wofireMux_T_443; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_447 = _out_wofireMux_T_262 & out_backSel_46_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_448 = _out_wofireMux_T_447; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_451 = _out_wofireMux_T_262 & out_backSel_47_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_452 = _out_wofireMux_T_451; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_455 = _out_wofireMux_T_262 & out_backSel_48_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_456 = _out_wofireMux_T_455; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_459 = _out_wofireMux_T_262 & out_backSel_49_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_460 = _out_wofireMux_T_459; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_463 = _out_wofireMux_T_262 & out_backSel_50_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_464 = _out_wofireMux_T_463; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_467 = _out_wofireMux_T_262 & out_backSel_51_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_468 = _out_wofireMux_T_467; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_471 = _out_wofireMux_T_262 & out_backSel_52_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_472 = _out_wofireMux_T_471; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_475 = _out_wofireMux_T_262 & out_backSel_53_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_476 = _out_wofireMux_T_475; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_479 = _out_wofireMux_T_262 & out_backSel_54_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_480 = _out_wofireMux_T_479; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_483 = _out_wofireMux_T_262 & out_backSel_55_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_484 = _out_wofireMux_T_483; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_487 = _out_wofireMux_T_262 & out_backSel_56_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_488 = _out_wofireMux_T_487; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_491 = _out_wofireMux_T_262 & out_backSel_57_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_492 = _out_wofireMux_T_491; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_495 = _out_wofireMux_T_262 & out_backSel_58_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_496 = _out_wofireMux_T_495; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_499 = _out_wofireMux_T_262 & out_backSel_59_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_500 = _out_wofireMux_T_499; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_503 = _out_wofireMux_T_262 & out_backSel_60_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_504 = _out_wofireMux_T_503; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_507 = _out_wofireMux_T_262 & out_backSel_61_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_508 = _out_wofireMux_T_507; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_511 = _out_wofireMux_T_262 & out_backSel_62_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_512 = _out_wofireMux_T_511; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_515 = _out_wofireMux_T_262 & out_backSel_63_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_516 = _out_wofireMux_T_515; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_519 = _out_wofireMux_T_262 & out_backSel_64; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_520 = _out_wofireMux_T_519; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_523 = _out_wofireMux_T_262 & out_backSel_65; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_524 = _out_wofireMux_T_523; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_527 = _out_wofireMux_T_262 & out_backSel_66; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_528 = _out_wofireMux_T_527; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_531 = _out_wofireMux_T_262 & out_backSel_67; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_532 = _out_wofireMux_T_531; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_535 = _out_wofireMux_T_262 & out_backSel_68; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_536 = _out_wofireMux_T_535; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_539 = _out_wofireMux_T_262 & out_backSel_69; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_540 = _out_wofireMux_T_539; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_543 = _out_wofireMux_T_262 & out_backSel_70; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_544 = _out_wofireMux_T_543; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_547 = _out_wofireMux_T_262 & out_backSel_71; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_548 = _out_wofireMux_T_547; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_551 = _out_wofireMux_T_262 & out_backSel_72; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_552 = _out_wofireMux_T_551; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_555 = _out_wofireMux_T_262 & out_backSel_73; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_556 = _out_wofireMux_T_555; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_559 = _out_wofireMux_T_262 & out_backSel_74; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_560 = _out_wofireMux_T_559; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_563 = _out_wofireMux_T_262 & out_backSel_75; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_564 = _out_wofireMux_T_563; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_567 = _out_wofireMux_T_262 & out_backSel_76; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_568 = _out_wofireMux_T_567; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_571 = _out_wofireMux_T_262 & out_backSel_77; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_572 = _out_wofireMux_T_571; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_575 = _out_wofireMux_T_262 & out_backSel_78; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_576 = _out_wofireMux_T_575; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_579 = _out_wofireMux_T_262 & out_backSel_79; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_580 = _out_wofireMux_T_579; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_583 = _out_wofireMux_T_262 & out_backSel_80; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_584 = _out_wofireMux_T_583; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_587 = _out_wofireMux_T_262 & out_backSel_81; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_588 = _out_wofireMux_T_587; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_591 = _out_wofireMux_T_262 & out_backSel_82; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_592 = _out_wofireMux_T_591; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_595 = _out_wofireMux_T_262 & out_backSel_83; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_596 = _out_wofireMux_T_595; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_599 = _out_wofireMux_T_262 & out_backSel_84; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_600 = _out_wofireMux_T_599; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_603 = _out_wofireMux_T_262 & out_backSel_85; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_604 = _out_wofireMux_T_603; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_607 = _out_wofireMux_T_262 & out_backSel_86; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_608 = _out_wofireMux_T_607; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_611 = _out_wofireMux_T_262 & out_backSel_87; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_612 = _out_wofireMux_T_611; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_615 = _out_wofireMux_T_262 & out_backSel_88; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_616 = _out_wofireMux_T_615; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_619 = _out_wofireMux_T_262 & out_backSel_89; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_620 = _out_wofireMux_T_619; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_623 = _out_wofireMux_T_262 & out_backSel_90; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_624 = _out_wofireMux_T_623; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_627 = _out_wofireMux_T_262 & out_backSel_91; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_628 = _out_wofireMux_T_627; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_631 = _out_wofireMux_T_262 & out_backSel_92; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_632 = _out_wofireMux_T_631; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_635 = _out_wofireMux_T_262 & out_backSel_93; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_636 = _out_wofireMux_T_635; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_639 = _out_wofireMux_T_262 & out_backSel_94; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_640 = _out_wofireMux_T_639; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_643 = _out_wofireMux_T_262 & out_backSel_95; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_644 = _out_wofireMux_T_643; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_647 = _out_wofireMux_T_262 & out_backSel_96; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_648 = _out_wofireMux_T_647 & _out_T_1713; // @[RegisterRouter.scala:87:24] assign out_woready_1_442 = _out_wofireMux_T_648; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_649 = ~_out_T_1713; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_651 = _out_wofireMux_T_262 & out_backSel_97; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_652 = _out_wofireMux_T_651; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_655 = _out_wofireMux_T_262 & out_backSel_98; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_656 = _out_wofireMux_T_655; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_659 = _out_wofireMux_T_262 & out_backSel_99; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_660 = _out_wofireMux_T_659; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_663 = _out_wofireMux_T_262 & out_backSel_100; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_664 = _out_wofireMux_T_663; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_667 = _out_wofireMux_T_262 & out_backSel_101; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_668 = _out_wofireMux_T_667; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_671 = _out_wofireMux_T_262 & out_backSel_102; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_672 = _out_wofireMux_T_671; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_675 = _out_wofireMux_T_262 & out_backSel_103; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_676 = _out_wofireMux_T_675 & _out_T_1781; // @[RegisterRouter.scala:87:24] assign out_woready_1_697 = _out_wofireMux_T_676; // @[RegisterRouter.scala:87:24] assign out_woready_1_698 = _out_wofireMux_T_676; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_677 = ~_out_T_1781; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_679 = _out_wofireMux_T_262 & out_backSel_104; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_680 = _out_wofireMux_T_679 & _out_T_1841; // @[RegisterRouter.scala:87:24] assign out_woready_1_931 = _out_wofireMux_T_680; // @[RegisterRouter.scala:87:24] assign out_woready_1_932 = _out_wofireMux_T_680; // @[RegisterRouter.scala:87:24] assign out_woready_1_933 = _out_wofireMux_T_680; // @[RegisterRouter.scala:87:24] assign out_woready_1_934 = _out_wofireMux_T_680; // @[RegisterRouter.scala:87:24] assign out_woready_1_935 = _out_wofireMux_T_680; // @[RegisterRouter.scala:87:24] assign out_woready_1_936 = _out_wofireMux_T_680; // @[RegisterRouter.scala:87:24] assign out_woready_1_937 = _out_wofireMux_T_680; // @[RegisterRouter.scala:87:24] assign out_woready_1_938 = _out_wofireMux_T_680; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_681 = ~_out_T_1841; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_683 = _out_wofireMux_T_262 & out_backSel_105; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_684 = _out_wofireMux_T_683 & _out_T_1733; // @[RegisterRouter.scala:87:24] assign out_woready_1_511 = _out_wofireMux_T_684; // @[RegisterRouter.scala:87:24] assign out_woready_1_512 = _out_wofireMux_T_684; // @[RegisterRouter.scala:87:24] assign out_woready_1_513 = _out_wofireMux_T_684; // @[RegisterRouter.scala:87:24] assign out_woready_1_514 = _out_wofireMux_T_684; // @[RegisterRouter.scala:87:24] assign out_woready_1_515 = _out_wofireMux_T_684; // @[RegisterRouter.scala:87:24] assign out_woready_1_516 = _out_wofireMux_T_684; // @[RegisterRouter.scala:87:24] assign out_woready_1_517 = _out_wofireMux_T_684; // @[RegisterRouter.scala:87:24] assign out_woready_1_518 = _out_wofireMux_T_684; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_685 = ~_out_T_1733; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_687 = _out_wofireMux_T_262 & out_backSel_106; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_688 = _out_wofireMux_T_687 & _out_T_1649; // @[RegisterRouter.scala:87:24] assign out_woready_1_192 = _out_wofireMux_T_688; // @[RegisterRouter.scala:87:24] assign out_woready_1_193 = _out_wofireMux_T_688; // @[RegisterRouter.scala:87:24] assign out_woready_1_194 = _out_wofireMux_T_688; // @[RegisterRouter.scala:87:24] assign out_woready_1_195 = _out_wofireMux_T_688; // @[RegisterRouter.scala:87:24] assign out_woready_1_196 = _out_wofireMux_T_688; // @[RegisterRouter.scala:87:24] assign out_woready_1_197 = _out_wofireMux_T_688; // @[RegisterRouter.scala:87:24] assign out_woready_1_198 = _out_wofireMux_T_688; // @[RegisterRouter.scala:87:24] assign out_woready_1_199 = _out_wofireMux_T_688; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_689 = ~_out_T_1649; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_691 = _out_wofireMux_T_262 & out_backSel_107; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_692 = _out_wofireMux_T_691 & _out_T_1881; // @[RegisterRouter.scala:87:24] assign out_woready_1_1091 = _out_wofireMux_T_692; // @[RegisterRouter.scala:87:24] assign out_woready_1_1092 = _out_wofireMux_T_692; // @[RegisterRouter.scala:87:24] assign out_woready_1_1093 = _out_wofireMux_T_692; // @[RegisterRouter.scala:87:24] assign out_woready_1_1094 = _out_wofireMux_T_692; // @[RegisterRouter.scala:87:24] assign out_woready_1_1095 = _out_wofireMux_T_692; // @[RegisterRouter.scala:87:24] assign out_woready_1_1096 = _out_wofireMux_T_692; // @[RegisterRouter.scala:87:24] assign out_woready_1_1097 = _out_wofireMux_T_692; // @[RegisterRouter.scala:87:24] assign out_woready_1_1098 = _out_wofireMux_T_692; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_693 = ~_out_T_1881; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_695 = _out_wofireMux_T_262 & out_backSel_108; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_696 = _out_wofireMux_T_695 & _out_T_1791; // @[RegisterRouter.scala:87:24] assign out_woready_1_731 = _out_wofireMux_T_696; // @[RegisterRouter.scala:87:24] assign out_woready_1_732 = _out_wofireMux_T_696; // @[RegisterRouter.scala:87:24] assign out_woready_1_733 = _out_wofireMux_T_696; // @[RegisterRouter.scala:87:24] assign out_woready_1_734 = _out_wofireMux_T_696; // @[RegisterRouter.scala:87:24] assign out_woready_1_735 = _out_wofireMux_T_696; // @[RegisterRouter.scala:87:24] assign out_woready_1_736 = _out_wofireMux_T_696; // @[RegisterRouter.scala:87:24] assign out_woready_1_737 = _out_wofireMux_T_696; // @[RegisterRouter.scala:87:24] assign out_woready_1_738 = _out_wofireMux_T_696; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_697 = ~_out_T_1791; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_699 = _out_wofireMux_T_262 & out_backSel_109; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_700 = _out_wofireMux_T_699 & _out_T_1715; // @[RegisterRouter.scala:87:24] assign out_woready_1_443 = _out_wofireMux_T_700; // @[RegisterRouter.scala:87:24] assign out_woready_1_444 = _out_wofireMux_T_700; // @[RegisterRouter.scala:87:24] assign out_woready_1_445 = _out_wofireMux_T_700; // @[RegisterRouter.scala:87:24] assign out_woready_1_446 = _out_wofireMux_T_700; // @[RegisterRouter.scala:87:24] assign out_woready_1_447 = _out_wofireMux_T_700; // @[RegisterRouter.scala:87:24] assign out_woready_1_448 = _out_wofireMux_T_700; // @[RegisterRouter.scala:87:24] assign out_woready_1_449 = _out_wofireMux_T_700; // @[RegisterRouter.scala:87:24] assign out_woready_1_450 = _out_wofireMux_T_700; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_701 = ~_out_T_1715; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_703 = _out_wofireMux_T_262 & out_backSel_110; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_704 = _out_wofireMux_T_703 & _out_T_1629; // @[RegisterRouter.scala:87:24] assign out_woready_1_112 = _out_wofireMux_T_704; // @[RegisterRouter.scala:87:24] assign out_woready_1_113 = _out_wofireMux_T_704; // @[RegisterRouter.scala:87:24] assign out_woready_1_114 = _out_wofireMux_T_704; // @[RegisterRouter.scala:87:24] assign out_woready_1_115 = _out_wofireMux_T_704; // @[RegisterRouter.scala:87:24] assign out_woready_1_116 = _out_wofireMux_T_704; // @[RegisterRouter.scala:87:24] assign out_woready_1_117 = _out_wofireMux_T_704; // @[RegisterRouter.scala:87:24] assign out_woready_1_118 = _out_wofireMux_T_704; // @[RegisterRouter.scala:87:24] assign out_woready_1_119 = _out_wofireMux_T_704; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_705 = ~_out_T_1629; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_707 = _out_wofireMux_T_262 & out_backSel_111; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_708 = _out_wofireMux_T_707 & _out_T_1899; // @[RegisterRouter.scala:87:24] assign out_woready_1_1163 = _out_wofireMux_T_708; // @[RegisterRouter.scala:87:24] assign out_woready_1_1164 = _out_wofireMux_T_708; // @[RegisterRouter.scala:87:24] assign out_woready_1_1165 = _out_wofireMux_T_708; // @[RegisterRouter.scala:87:24] assign out_woready_1_1166 = _out_wofireMux_T_708; // @[RegisterRouter.scala:87:24] assign out_woready_1_1167 = _out_wofireMux_T_708; // @[RegisterRouter.scala:87:24] assign out_woready_1_1168 = _out_wofireMux_T_708; // @[RegisterRouter.scala:87:24] assign out_woready_1_1169 = _out_wofireMux_T_708; // @[RegisterRouter.scala:87:24] assign out_woready_1_1170 = _out_wofireMux_T_708; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_709 = ~_out_T_1899; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_711 = _out_wofireMux_T_262 & out_backSel_112; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_712 = _out_wofireMux_T_711 & _out_T_1815; // @[RegisterRouter.scala:87:24] assign out_woready_1_827 = _out_wofireMux_T_712; // @[RegisterRouter.scala:87:24] assign out_woready_1_828 = _out_wofireMux_T_712; // @[RegisterRouter.scala:87:24] assign out_woready_1_829 = _out_wofireMux_T_712; // @[RegisterRouter.scala:87:24] assign out_woready_1_830 = _out_wofireMux_T_712; // @[RegisterRouter.scala:87:24] assign out_woready_1_831 = _out_wofireMux_T_712; // @[RegisterRouter.scala:87:24] assign out_woready_1_832 = _out_wofireMux_T_712; // @[RegisterRouter.scala:87:24] assign out_woready_1_833 = _out_wofireMux_T_712; // @[RegisterRouter.scala:87:24] assign out_woready_1_834 = _out_wofireMux_T_712; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_713 = ~_out_T_1815; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_715 = _out_wofireMux_T_262 & out_backSel_113; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_716 = _out_wofireMux_T_715 & _out_T_1771; // @[RegisterRouter.scala:87:24] assign out_woready_1_657 = _out_wofireMux_T_716; // @[RegisterRouter.scala:87:24] assign out_woready_1_658 = _out_wofireMux_T_716; // @[RegisterRouter.scala:87:24] assign out_woready_1_659 = _out_wofireMux_T_716; // @[RegisterRouter.scala:87:24] assign out_woready_1_660 = _out_wofireMux_T_716; // @[RegisterRouter.scala:87:24] assign out_woready_1_661 = _out_wofireMux_T_716; // @[RegisterRouter.scala:87:24] assign out_woready_1_662 = _out_wofireMux_T_716; // @[RegisterRouter.scala:87:24] assign out_woready_1_663 = _out_wofireMux_T_716; // @[RegisterRouter.scala:87:24] assign out_woready_1_664 = _out_wofireMux_T_716; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_717 = ~_out_T_1771; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_719 = _out_wofireMux_T_262 & out_backSel_114; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_720 = _out_wofireMux_T_719 & _out_T_1853; // @[RegisterRouter.scala:87:24] assign out_woready_1_979 = _out_wofireMux_T_720; // @[RegisterRouter.scala:87:24] assign out_woready_1_980 = _out_wofireMux_T_720; // @[RegisterRouter.scala:87:24] assign out_woready_1_981 = _out_wofireMux_T_720; // @[RegisterRouter.scala:87:24] assign out_woready_1_982 = _out_wofireMux_T_720; // @[RegisterRouter.scala:87:24] assign out_woready_1_983 = _out_wofireMux_T_720; // @[RegisterRouter.scala:87:24] assign out_woready_1_984 = _out_wofireMux_T_720; // @[RegisterRouter.scala:87:24] assign out_woready_1_985 = _out_wofireMux_T_720; // @[RegisterRouter.scala:87:24] assign out_woready_1_986 = _out_wofireMux_T_720; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_721 = ~_out_T_1853; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_723 = _out_wofireMux_T_262 & out_backSel_115; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_724 = _out_wofireMux_T_723 & _out_T_1609; // @[RegisterRouter.scala:87:24] assign out_woready_1_32 = _out_wofireMux_T_724; // @[RegisterRouter.scala:87:24] assign out_woready_1_33 = _out_wofireMux_T_724; // @[RegisterRouter.scala:87:24] assign out_woready_1_34 = _out_wofireMux_T_724; // @[RegisterRouter.scala:87:24] assign out_woready_1_35 = _out_wofireMux_T_724; // @[RegisterRouter.scala:87:24] assign out_woready_1_36 = _out_wofireMux_T_724; // @[RegisterRouter.scala:87:24] assign out_woready_1_37 = _out_wofireMux_T_724; // @[RegisterRouter.scala:87:24] assign out_woready_1_38 = _out_wofireMux_T_724; // @[RegisterRouter.scala:87:24] assign out_woready_1_39 = _out_wofireMux_T_724; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_725 = ~_out_T_1609; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_727 = _out_wofireMux_T_262 & out_backSel_116; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_728 = _out_wofireMux_T_727; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_731 = _out_wofireMux_T_262 & out_backSel_117; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_732 = _out_wofireMux_T_731; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_735 = _out_wofireMux_T_262 & out_backSel_118; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_736 = _out_wofireMux_T_735; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_739 = _out_wofireMux_T_262 & out_backSel_119; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_740 = _out_wofireMux_T_739; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_743 = _out_wofireMux_T_262 & out_backSel_120; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_744 = _out_wofireMux_T_743; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_747 = _out_wofireMux_T_262 & out_backSel_121; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_748 = _out_wofireMux_T_747; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_751 = _out_wofireMux_T_262 & out_backSel_122; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_752 = _out_wofireMux_T_751; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_755 = _out_wofireMux_T_262 & out_backSel_123; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_756 = _out_wofireMux_T_755; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_759 = _out_wofireMux_T_262 & out_backSel_124; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_760 = _out_wofireMux_T_759; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_763 = _out_wofireMux_T_262 & out_backSel_125; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_764 = _out_wofireMux_T_763; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_767 = _out_wofireMux_T_262 & out_backSel_126; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_768 = _out_wofireMux_T_767; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_771 = _out_wofireMux_T_262 & out_backSel_127; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_772 = _out_wofireMux_T_771; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_775 = _out_wofireMux_T_262 & out_backSel_128; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_776 = _out_wofireMux_T_775 & _out_T_1729; // @[RegisterRouter.scala:87:24] assign out_woready_1_495 = _out_wofireMux_T_776; // @[RegisterRouter.scala:87:24] assign out_woready_1_496 = _out_wofireMux_T_776; // @[RegisterRouter.scala:87:24] assign out_woready_1_497 = _out_wofireMux_T_776; // @[RegisterRouter.scala:87:24] assign out_woready_1_498 = _out_wofireMux_T_776; // @[RegisterRouter.scala:87:24] assign out_woready_1_499 = _out_wofireMux_T_776; // @[RegisterRouter.scala:87:24] assign out_woready_1_500 = _out_wofireMux_T_776; // @[RegisterRouter.scala:87:24] assign out_woready_1_501 = _out_wofireMux_T_776; // @[RegisterRouter.scala:87:24] assign out_woready_1_502 = _out_wofireMux_T_776; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_777 = ~_out_T_1729; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_779 = _out_wofireMux_T_262 & out_backSel_129; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_780 = _out_wofireMux_T_779 & _out_T_1721; // @[RegisterRouter.scala:87:24] assign out_woready_1_467 = _out_wofireMux_T_780; // @[RegisterRouter.scala:87:24] assign out_woready_1_468 = _out_wofireMux_T_780; // @[RegisterRouter.scala:87:24] assign out_woready_1_469 = _out_wofireMux_T_780; // @[RegisterRouter.scala:87:24] assign out_woready_1_470 = _out_wofireMux_T_780; // @[RegisterRouter.scala:87:24] assign out_woready_1_471 = _out_wofireMux_T_780; // @[RegisterRouter.scala:87:24] assign out_woready_1_472 = _out_wofireMux_T_780; // @[RegisterRouter.scala:87:24] assign out_woready_1_473 = _out_wofireMux_T_780; // @[RegisterRouter.scala:87:24] assign out_woready_1_474 = _out_wofireMux_T_780; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_781 = ~_out_T_1721; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_783 = _out_wofireMux_T_262 & out_backSel_130; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_784 = _out_wofireMux_T_783 & _out_T_1797; // @[RegisterRouter.scala:87:24] assign out_woready_1_755 = _out_wofireMux_T_784; // @[RegisterRouter.scala:87:24] assign out_woready_1_756 = _out_wofireMux_T_784; // @[RegisterRouter.scala:87:24] assign out_woready_1_757 = _out_wofireMux_T_784; // @[RegisterRouter.scala:87:24] assign out_woready_1_758 = _out_wofireMux_T_784; // @[RegisterRouter.scala:87:24] assign out_woready_1_759 = _out_wofireMux_T_784; // @[RegisterRouter.scala:87:24] assign out_woready_1_760 = _out_wofireMux_T_784; // @[RegisterRouter.scala:87:24] assign out_woready_1_761 = _out_wofireMux_T_784; // @[RegisterRouter.scala:87:24] assign out_woready_1_762 = _out_wofireMux_T_784; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_785 = ~_out_T_1797; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_787 = _out_wofireMux_T_262 & out_backSel_131; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_788 = _out_wofireMux_T_787 & _out_T_1891; // @[RegisterRouter.scala:87:24] assign out_woready_1_1131 = _out_wofireMux_T_788; // @[RegisterRouter.scala:87:24] assign out_woready_1_1132 = _out_wofireMux_T_788; // @[RegisterRouter.scala:87:24] assign out_woready_1_1133 = _out_wofireMux_T_788; // @[RegisterRouter.scala:87:24] assign out_woready_1_1134 = _out_wofireMux_T_788; // @[RegisterRouter.scala:87:24] assign out_woready_1_1135 = _out_wofireMux_T_788; // @[RegisterRouter.scala:87:24] assign out_woready_1_1136 = _out_wofireMux_T_788; // @[RegisterRouter.scala:87:24] assign out_woready_1_1137 = _out_wofireMux_T_788; // @[RegisterRouter.scala:87:24] assign out_woready_1_1138 = _out_wofireMux_T_788; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_789 = ~_out_T_1891; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_791 = _out_wofireMux_T_262 & out_backSel_132; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_792 = _out_wofireMux_T_791 & _out_T_1661; // @[RegisterRouter.scala:87:24] assign out_woready_1_240 = _out_wofireMux_T_792; // @[RegisterRouter.scala:87:24] assign out_woready_1_241 = _out_wofireMux_T_792; // @[RegisterRouter.scala:87:24] assign out_woready_1_242 = _out_wofireMux_T_792; // @[RegisterRouter.scala:87:24] assign out_woready_1_243 = _out_wofireMux_T_792; // @[RegisterRouter.scala:87:24] assign out_woready_1_244 = _out_wofireMux_T_792; // @[RegisterRouter.scala:87:24] assign out_woready_1_245 = _out_wofireMux_T_792; // @[RegisterRouter.scala:87:24] assign out_woready_1_246 = _out_wofireMux_T_792; // @[RegisterRouter.scala:87:24] assign out_woready_1_247 = _out_wofireMux_T_792; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_793 = ~_out_T_1661; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_795 = _out_wofireMux_T_262 & out_backSel_133; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_796 = _out_wofireMux_T_795 & _out_T_1663; // @[RegisterRouter.scala:87:24] assign out_woready_1_248 = _out_wofireMux_T_796; // @[RegisterRouter.scala:87:24] assign out_woready_1_249 = _out_wofireMux_T_796; // @[RegisterRouter.scala:87:24] assign out_woready_1_250 = _out_wofireMux_T_796; // @[RegisterRouter.scala:87:24] assign out_woready_1_251 = _out_wofireMux_T_796; // @[RegisterRouter.scala:87:24] assign out_woready_1_252 = _out_wofireMux_T_796; // @[RegisterRouter.scala:87:24] assign out_woready_1_253 = _out_wofireMux_T_796; // @[RegisterRouter.scala:87:24] assign out_woready_1_254 = _out_wofireMux_T_796; // @[RegisterRouter.scala:87:24] assign out_woready_1_255 = _out_wofireMux_T_796; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_797 = ~_out_T_1663; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_799 = _out_wofireMux_T_262 & out_backSel_134; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_800 = _out_wofireMux_T_799 & _out_T_1723; // @[RegisterRouter.scala:87:24] assign out_woready_1_475 = _out_wofireMux_T_800; // @[RegisterRouter.scala:87:24] assign out_woready_1_476 = _out_wofireMux_T_800; // @[RegisterRouter.scala:87:24] assign out_woready_1_477 = _out_wofireMux_T_800; // @[RegisterRouter.scala:87:24] assign out_woready_1_478 = _out_wofireMux_T_800; // @[RegisterRouter.scala:87:24] assign out_woready_1_479 = _out_wofireMux_T_800; // @[RegisterRouter.scala:87:24] assign out_woready_1_480 = _out_wofireMux_T_800; // @[RegisterRouter.scala:87:24] assign out_woready_1_481 = _out_wofireMux_T_800; // @[RegisterRouter.scala:87:24] assign out_woready_1_482 = _out_wofireMux_T_800; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_801 = ~_out_T_1723; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_803 = _out_wofireMux_T_262 & out_backSel_135; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_804 = _out_wofireMux_T_803 & _out_T_1801; // @[RegisterRouter.scala:87:24] assign out_woready_1_771 = _out_wofireMux_T_804; // @[RegisterRouter.scala:87:24] assign out_woready_1_772 = _out_wofireMux_T_804; // @[RegisterRouter.scala:87:24] assign out_woready_1_773 = _out_wofireMux_T_804; // @[RegisterRouter.scala:87:24] assign out_woready_1_774 = _out_wofireMux_T_804; // @[RegisterRouter.scala:87:24] assign out_woready_1_775 = _out_wofireMux_T_804; // @[RegisterRouter.scala:87:24] assign out_woready_1_776 = _out_wofireMux_T_804; // @[RegisterRouter.scala:87:24] assign out_woready_1_777 = _out_wofireMux_T_804; // @[RegisterRouter.scala:87:24] assign out_woready_1_778 = _out_wofireMux_T_804; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_805 = ~_out_T_1801; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_807 = _out_wofireMux_T_262 & out_backSel_136; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_808 = _out_wofireMux_T_807 & _out_T_1883; // @[RegisterRouter.scala:87:24] assign out_woready_1_1099 = _out_wofireMux_T_808; // @[RegisterRouter.scala:87:24] assign out_woready_1_1100 = _out_wofireMux_T_808; // @[RegisterRouter.scala:87:24] assign out_woready_1_1101 = _out_wofireMux_T_808; // @[RegisterRouter.scala:87:24] assign out_woready_1_1102 = _out_wofireMux_T_808; // @[RegisterRouter.scala:87:24] assign out_woready_1_1103 = _out_wofireMux_T_808; // @[RegisterRouter.scala:87:24] assign out_woready_1_1104 = _out_wofireMux_T_808; // @[RegisterRouter.scala:87:24] assign out_woready_1_1105 = _out_wofireMux_T_808; // @[RegisterRouter.scala:87:24] assign out_woready_1_1106 = _out_wofireMux_T_808; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_809 = ~_out_T_1883; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_811 = _out_wofireMux_T_262 & out_backSel_137; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_812 = _out_wofireMux_T_811 & _out_T_1685; // @[RegisterRouter.scala:87:24] assign out_woready_1_336 = _out_wofireMux_T_812; // @[RegisterRouter.scala:87:24] assign out_woready_1_337 = _out_wofireMux_T_812; // @[RegisterRouter.scala:87:24] assign out_woready_1_338 = _out_wofireMux_T_812; // @[RegisterRouter.scala:87:24] assign out_woready_1_339 = _out_wofireMux_T_812; // @[RegisterRouter.scala:87:24] assign out_woready_1_340 = _out_wofireMux_T_812; // @[RegisterRouter.scala:87:24] assign out_woready_1_341 = _out_wofireMux_T_812; // @[RegisterRouter.scala:87:24] assign out_woready_1_342 = _out_wofireMux_T_812; // @[RegisterRouter.scala:87:24] assign out_woready_1_343 = _out_wofireMux_T_812; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_813 = ~_out_T_1685; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_815 = _out_wofireMux_T_262 & out_backSel_138; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_816 = _out_wofireMux_T_815 & _out_T_1601; // @[RegisterRouter.scala:87:24] assign out_woready_1_0 = _out_wofireMux_T_816; // @[RegisterRouter.scala:87:24] assign out_woready_1_1 = _out_wofireMux_T_816; // @[RegisterRouter.scala:87:24] assign out_woready_1_2 = _out_wofireMux_T_816; // @[RegisterRouter.scala:87:24] assign out_woready_1_3 = _out_wofireMux_T_816; // @[RegisterRouter.scala:87:24] assign out_woready_1_4 = _out_wofireMux_T_816; // @[RegisterRouter.scala:87:24] assign out_woready_1_5 = _out_wofireMux_T_816; // @[RegisterRouter.scala:87:24] assign out_woready_1_6 = _out_wofireMux_T_816; // @[RegisterRouter.scala:87:24] assign out_woready_1_7 = _out_wofireMux_T_816; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_817 = ~_out_T_1601; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_819 = _out_wofireMux_T_262 & out_backSel_139; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_820 = _out_wofireMux_T_819 & _out_T_1857; // @[RegisterRouter.scala:87:24] assign out_woready_1_995 = _out_wofireMux_T_820; // @[RegisterRouter.scala:87:24] assign out_woready_1_996 = _out_wofireMux_T_820; // @[RegisterRouter.scala:87:24] assign out_woready_1_997 = _out_wofireMux_T_820; // @[RegisterRouter.scala:87:24] assign out_woready_1_998 = _out_wofireMux_T_820; // @[RegisterRouter.scala:87:24] assign out_woready_1_999 = _out_wofireMux_T_820; // @[RegisterRouter.scala:87:24] assign out_woready_1_1000 = _out_wofireMux_T_820; // @[RegisterRouter.scala:87:24] assign out_woready_1_1001 = _out_wofireMux_T_820; // @[RegisterRouter.scala:87:24] assign out_woready_1_1002 = _out_wofireMux_T_820; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_821 = ~_out_T_1857; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_823 = _out_wofireMux_T_262 & out_backSel_140; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_824 = _out_wofireMux_T_823 & _out_T_1783; // @[RegisterRouter.scala:87:24] assign out_woready_1_699 = _out_wofireMux_T_824; // @[RegisterRouter.scala:87:24] assign out_woready_1_700 = _out_wofireMux_T_824; // @[RegisterRouter.scala:87:24] assign out_woready_1_701 = _out_wofireMux_T_824; // @[RegisterRouter.scala:87:24] assign out_woready_1_702 = _out_wofireMux_T_824; // @[RegisterRouter.scala:87:24] assign out_woready_1_703 = _out_wofireMux_T_824; // @[RegisterRouter.scala:87:24] assign out_woready_1_704 = _out_wofireMux_T_824; // @[RegisterRouter.scala:87:24] assign out_woready_1_705 = _out_wofireMux_T_824; // @[RegisterRouter.scala:87:24] assign out_woready_1_706 = _out_wofireMux_T_824; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_825 = ~_out_T_1783; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_827 = _out_wofireMux_T_262 & out_backSel_141; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_828 = _out_wofireMux_T_827 & _out_T_1705; // @[RegisterRouter.scala:87:24] assign out_woready_1_410 = _out_wofireMux_T_828; // @[RegisterRouter.scala:87:24] assign out_woready_1_411 = _out_wofireMux_T_828; // @[RegisterRouter.scala:87:24] assign out_woready_1_412 = _out_wofireMux_T_828; // @[RegisterRouter.scala:87:24] assign out_woready_1_413 = _out_wofireMux_T_828; // @[RegisterRouter.scala:87:24] assign out_woready_1_414 = _out_wofireMux_T_828; // @[RegisterRouter.scala:87:24] assign out_woready_1_415 = _out_wofireMux_T_828; // @[RegisterRouter.scala:87:24] assign out_woready_1_416 = _out_wofireMux_T_828; // @[RegisterRouter.scala:87:24] assign out_woready_1_417 = _out_wofireMux_T_828; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_829 = ~_out_T_1705; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_831 = _out_wofireMux_T_262 & out_backSel_142; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_832 = _out_wofireMux_T_831 & _out_T_1617; // @[RegisterRouter.scala:87:24] assign out_woready_1_64 = _out_wofireMux_T_832; // @[RegisterRouter.scala:87:24] assign out_woready_1_65 = _out_wofireMux_T_832; // @[RegisterRouter.scala:87:24] assign out_woready_1_66 = _out_wofireMux_T_832; // @[RegisterRouter.scala:87:24] assign out_woready_1_67 = _out_wofireMux_T_832; // @[RegisterRouter.scala:87:24] assign out_woready_1_68 = _out_wofireMux_T_832; // @[RegisterRouter.scala:87:24] assign out_woready_1_69 = _out_wofireMux_T_832; // @[RegisterRouter.scala:87:24] assign out_woready_1_70 = _out_wofireMux_T_832; // @[RegisterRouter.scala:87:24] assign out_woready_1_71 = _out_wofireMux_T_832; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_833 = ~_out_T_1617; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_835 = _out_wofireMux_T_262 & out_backSel_143; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_836 = _out_wofireMux_T_835 & _out_T_1835; // @[RegisterRouter.scala:87:24] assign out_woready_1_907 = _out_wofireMux_T_836; // @[RegisterRouter.scala:87:24] assign out_woready_1_908 = _out_wofireMux_T_836; // @[RegisterRouter.scala:87:24] assign out_woready_1_909 = _out_wofireMux_T_836; // @[RegisterRouter.scala:87:24] assign out_woready_1_910 = _out_wofireMux_T_836; // @[RegisterRouter.scala:87:24] assign out_woready_1_911 = _out_wofireMux_T_836; // @[RegisterRouter.scala:87:24] assign out_woready_1_912 = _out_wofireMux_T_836; // @[RegisterRouter.scala:87:24] assign out_woready_1_913 = _out_wofireMux_T_836; // @[RegisterRouter.scala:87:24] assign out_woready_1_914 = _out_wofireMux_T_836; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_837 = ~_out_T_1835; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_839 = _out_wofireMux_T_262 & out_backSel_144; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_840 = _out_wofireMux_T_839 & _out_T_1759; // @[RegisterRouter.scala:87:24] assign out_woready_1_609 = _out_wofireMux_T_840; // @[RegisterRouter.scala:87:24] assign out_woready_1_610 = _out_wofireMux_T_840; // @[RegisterRouter.scala:87:24] assign out_woready_1_611 = _out_wofireMux_T_840; // @[RegisterRouter.scala:87:24] assign out_woready_1_612 = _out_wofireMux_T_840; // @[RegisterRouter.scala:87:24] assign out_woready_1_613 = _out_wofireMux_T_840; // @[RegisterRouter.scala:87:24] assign out_woready_1_614 = _out_wofireMux_T_840; // @[RegisterRouter.scala:87:24] assign out_woready_1_615 = _out_wofireMux_T_840; // @[RegisterRouter.scala:87:24] assign out_woready_1_616 = _out_wofireMux_T_840; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_841 = ~_out_T_1759; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_843 = _out_wofireMux_T_262 & out_backSel_145; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_844 = _out_wofireMux_T_843 & _out_T_1819; // @[RegisterRouter.scala:87:24] assign out_woready_1_843 = _out_wofireMux_T_844; // @[RegisterRouter.scala:87:24] assign out_woready_1_844 = _out_wofireMux_T_844; // @[RegisterRouter.scala:87:24] assign out_woready_1_845 = _out_wofireMux_T_844; // @[RegisterRouter.scala:87:24] assign out_woready_1_846 = _out_wofireMux_T_844; // @[RegisterRouter.scala:87:24] assign out_woready_1_847 = _out_wofireMux_T_844; // @[RegisterRouter.scala:87:24] assign out_woready_1_848 = _out_wofireMux_T_844; // @[RegisterRouter.scala:87:24] assign out_woready_1_849 = _out_wofireMux_T_844; // @[RegisterRouter.scala:87:24] assign out_woready_1_850 = _out_wofireMux_T_844; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_845 = ~_out_T_1819; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_847 = _out_wofireMux_T_262 & out_backSel_146; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_848 = _out_wofireMux_T_847 & _out_T_1869; // @[RegisterRouter.scala:87:24] assign out_woready_1_1043 = _out_wofireMux_T_848; // @[RegisterRouter.scala:87:24] assign out_woready_1_1044 = _out_wofireMux_T_848; // @[RegisterRouter.scala:87:24] assign out_woready_1_1045 = _out_wofireMux_T_848; // @[RegisterRouter.scala:87:24] assign out_woready_1_1046 = _out_wofireMux_T_848; // @[RegisterRouter.scala:87:24] assign out_woready_1_1047 = _out_wofireMux_T_848; // @[RegisterRouter.scala:87:24] assign out_woready_1_1048 = _out_wofireMux_T_848; // @[RegisterRouter.scala:87:24] assign out_woready_1_1049 = _out_wofireMux_T_848; // @[RegisterRouter.scala:87:24] assign out_woready_1_1050 = _out_wofireMux_T_848; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_849 = ~_out_T_1869; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_851 = _out_wofireMux_T_262 & out_backSel_147; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_852 = _out_wofireMux_T_851 & _out_T_1657; // @[RegisterRouter.scala:87:24] assign out_woready_1_224 = _out_wofireMux_T_852; // @[RegisterRouter.scala:87:24] assign out_woready_1_225 = _out_wofireMux_T_852; // @[RegisterRouter.scala:87:24] assign out_woready_1_226 = _out_wofireMux_T_852; // @[RegisterRouter.scala:87:24] assign out_woready_1_227 = _out_wofireMux_T_852; // @[RegisterRouter.scala:87:24] assign out_woready_1_228 = _out_wofireMux_T_852; // @[RegisterRouter.scala:87:24] assign out_woready_1_229 = _out_wofireMux_T_852; // @[RegisterRouter.scala:87:24] assign out_woready_1_230 = _out_wofireMux_T_852; // @[RegisterRouter.scala:87:24] assign out_woready_1_231 = _out_wofireMux_T_852; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_853 = ~_out_T_1657; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_855 = _out_wofireMux_T_262 & out_backSel_148; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_856 = _out_wofireMux_T_855 & _out_T_1741; // @[RegisterRouter.scala:87:24] assign out_woready_1_537 = _out_wofireMux_T_856; // @[RegisterRouter.scala:87:24] assign out_woready_1_538 = _out_wofireMux_T_856; // @[RegisterRouter.scala:87:24] assign out_woready_1_539 = _out_wofireMux_T_856; // @[RegisterRouter.scala:87:24] assign out_woready_1_540 = _out_wofireMux_T_856; // @[RegisterRouter.scala:87:24] assign out_woready_1_541 = _out_wofireMux_T_856; // @[RegisterRouter.scala:87:24] assign out_woready_1_542 = _out_wofireMux_T_856; // @[RegisterRouter.scala:87:24] assign out_woready_1_543 = _out_wofireMux_T_856; // @[RegisterRouter.scala:87:24] assign out_woready_1_544 = _out_wofireMux_T_856; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_857 = ~_out_T_1741; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_859 = _out_wofireMux_T_262 & out_backSel_149; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_860 = _out_wofireMux_T_859 & _out_T_1749; // @[RegisterRouter.scala:87:24] assign out_woready_1_569 = _out_wofireMux_T_860; // @[RegisterRouter.scala:87:24] assign out_woready_1_570 = _out_wofireMux_T_860; // @[RegisterRouter.scala:87:24] assign out_woready_1_571 = _out_wofireMux_T_860; // @[RegisterRouter.scala:87:24] assign out_woready_1_572 = _out_wofireMux_T_860; // @[RegisterRouter.scala:87:24] assign out_woready_1_573 = _out_wofireMux_T_860; // @[RegisterRouter.scala:87:24] assign out_woready_1_574 = _out_wofireMux_T_860; // @[RegisterRouter.scala:87:24] assign out_woready_1_575 = _out_wofireMux_T_860; // @[RegisterRouter.scala:87:24] assign out_woready_1_576 = _out_wofireMux_T_860; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_861 = ~_out_T_1749; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_863 = _out_wofireMux_T_262 & out_backSel_150; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_864 = _out_wofireMux_T_863 & _out_T_1821; // @[RegisterRouter.scala:87:24] assign out_woready_1_851 = _out_wofireMux_T_864; // @[RegisterRouter.scala:87:24] assign out_woready_1_852 = _out_wofireMux_T_864; // @[RegisterRouter.scala:87:24] assign out_woready_1_853 = _out_wofireMux_T_864; // @[RegisterRouter.scala:87:24] assign out_woready_1_854 = _out_wofireMux_T_864; // @[RegisterRouter.scala:87:24] assign out_woready_1_855 = _out_wofireMux_T_864; // @[RegisterRouter.scala:87:24] assign out_woready_1_856 = _out_wofireMux_T_864; // @[RegisterRouter.scala:87:24] assign out_woready_1_857 = _out_wofireMux_T_864; // @[RegisterRouter.scala:87:24] assign out_woready_1_858 = _out_wofireMux_T_864; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_865 = ~_out_T_1821; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_867 = _out_wofireMux_T_262 & out_backSel_151; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_868 = _out_wofireMux_T_867 & _out_T_1867; // @[RegisterRouter.scala:87:24] assign out_woready_1_1035 = _out_wofireMux_T_868; // @[RegisterRouter.scala:87:24] assign out_woready_1_1036 = _out_wofireMux_T_868; // @[RegisterRouter.scala:87:24] assign out_woready_1_1037 = _out_wofireMux_T_868; // @[RegisterRouter.scala:87:24] assign out_woready_1_1038 = _out_wofireMux_T_868; // @[RegisterRouter.scala:87:24] assign out_woready_1_1039 = _out_wofireMux_T_868; // @[RegisterRouter.scala:87:24] assign out_woready_1_1040 = _out_wofireMux_T_868; // @[RegisterRouter.scala:87:24] assign out_woready_1_1041 = _out_wofireMux_T_868; // @[RegisterRouter.scala:87:24] assign out_woready_1_1042 = _out_wofireMux_T_868; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_869 = ~_out_T_1867; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_871 = _out_wofireMux_T_262 & out_backSel_152; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_872 = _out_wofireMux_T_871 & _out_T_1637; // @[RegisterRouter.scala:87:24] assign out_woready_1_144 = _out_wofireMux_T_872; // @[RegisterRouter.scala:87:24] assign out_woready_1_145 = _out_wofireMux_T_872; // @[RegisterRouter.scala:87:24] assign out_woready_1_146 = _out_wofireMux_T_872; // @[RegisterRouter.scala:87:24] assign out_woready_1_147 = _out_wofireMux_T_872; // @[RegisterRouter.scala:87:24] assign out_woready_1_148 = _out_wofireMux_T_872; // @[RegisterRouter.scala:87:24] assign out_woready_1_149 = _out_wofireMux_T_872; // @[RegisterRouter.scala:87:24] assign out_woready_1_150 = _out_wofireMux_T_872; // @[RegisterRouter.scala:87:24] assign out_woready_1_151 = _out_wofireMux_T_872; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_873 = ~_out_T_1637; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_875 = _out_wofireMux_T_262 & out_backSel_153; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_876 = _out_wofireMux_T_875 & _out_T_1619; // @[RegisterRouter.scala:87:24] assign out_woready_1_72 = _out_wofireMux_T_876; // @[RegisterRouter.scala:87:24] assign out_woready_1_73 = _out_wofireMux_T_876; // @[RegisterRouter.scala:87:24] assign out_woready_1_74 = _out_wofireMux_T_876; // @[RegisterRouter.scala:87:24] assign out_woready_1_75 = _out_wofireMux_T_876; // @[RegisterRouter.scala:87:24] assign out_woready_1_76 = _out_wofireMux_T_876; // @[RegisterRouter.scala:87:24] assign out_woready_1_77 = _out_wofireMux_T_876; // @[RegisterRouter.scala:87:24] assign out_woready_1_78 = _out_wofireMux_T_876; // @[RegisterRouter.scala:87:24] assign out_woready_1_79 = _out_wofireMux_T_876; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_877 = ~_out_T_1619; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_879 = _out_wofireMux_T_262 & out_backSel_154; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_880 = _out_wofireMux_T_879 & _out_T_1831; // @[RegisterRouter.scala:87:24] assign out_woready_1_891 = _out_wofireMux_T_880; // @[RegisterRouter.scala:87:24] assign out_woready_1_892 = _out_wofireMux_T_880; // @[RegisterRouter.scala:87:24] assign out_woready_1_893 = _out_wofireMux_T_880; // @[RegisterRouter.scala:87:24] assign out_woready_1_894 = _out_wofireMux_T_880; // @[RegisterRouter.scala:87:24] assign out_woready_1_895 = _out_wofireMux_T_880; // @[RegisterRouter.scala:87:24] assign out_woready_1_896 = _out_wofireMux_T_880; // @[RegisterRouter.scala:87:24] assign out_woready_1_897 = _out_wofireMux_T_880; // @[RegisterRouter.scala:87:24] assign out_woready_1_898 = _out_wofireMux_T_880; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_881 = ~_out_T_1831; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_883 = _out_wofireMux_T_262 & out_backSel_155; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_884 = _out_wofireMux_T_883 & _out_T_1787; // @[RegisterRouter.scala:87:24] assign out_woready_1_715 = _out_wofireMux_T_884; // @[RegisterRouter.scala:87:24] assign out_woready_1_716 = _out_wofireMux_T_884; // @[RegisterRouter.scala:87:24] assign out_woready_1_717 = _out_wofireMux_T_884; // @[RegisterRouter.scala:87:24] assign out_woready_1_718 = _out_wofireMux_T_884; // @[RegisterRouter.scala:87:24] assign out_woready_1_719 = _out_wofireMux_T_884; // @[RegisterRouter.scala:87:24] assign out_woready_1_720 = _out_wofireMux_T_884; // @[RegisterRouter.scala:87:24] assign out_woready_1_721 = _out_wofireMux_T_884; // @[RegisterRouter.scala:87:24] assign out_woready_1_722 = _out_wofireMux_T_884; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_885 = ~_out_T_1787; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_887 = _out_wofireMux_T_262 & out_backSel_156; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_888 = _out_wofireMux_T_887 & _out_T_1699; // @[RegisterRouter.scala:87:24] assign out_woready_1_386 = _out_wofireMux_T_888; // @[RegisterRouter.scala:87:24] assign out_woready_1_387 = _out_wofireMux_T_888; // @[RegisterRouter.scala:87:24] assign out_woready_1_388 = _out_wofireMux_T_888; // @[RegisterRouter.scala:87:24] assign out_woready_1_389 = _out_wofireMux_T_888; // @[RegisterRouter.scala:87:24] assign out_woready_1_390 = _out_wofireMux_T_888; // @[RegisterRouter.scala:87:24] assign out_woready_1_391 = _out_wofireMux_T_888; // @[RegisterRouter.scala:87:24] assign out_woready_1_392 = _out_wofireMux_T_888; // @[RegisterRouter.scala:87:24] assign out_woready_1_393 = _out_wofireMux_T_888; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_889 = ~_out_T_1699; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_891 = _out_wofireMux_T_262 & out_backSel_157; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_892 = _out_wofireMux_T_891 & _out_T_1633; // @[RegisterRouter.scala:87:24] assign out_woready_1_128 = _out_wofireMux_T_892; // @[RegisterRouter.scala:87:24] assign out_woready_1_129 = _out_wofireMux_T_892; // @[RegisterRouter.scala:87:24] assign out_woready_1_130 = _out_wofireMux_T_892; // @[RegisterRouter.scala:87:24] assign out_woready_1_131 = _out_wofireMux_T_892; // @[RegisterRouter.scala:87:24] assign out_woready_1_132 = _out_wofireMux_T_892; // @[RegisterRouter.scala:87:24] assign out_woready_1_133 = _out_wofireMux_T_892; // @[RegisterRouter.scala:87:24] assign out_woready_1_134 = _out_wofireMux_T_892; // @[RegisterRouter.scala:87:24] assign out_woready_1_135 = _out_wofireMux_T_892; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_893 = ~_out_T_1633; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_895 = _out_wofireMux_T_262 & out_backSel_158; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_896 = _out_wofireMux_T_895 & _out_T_1849; // @[RegisterRouter.scala:87:24] assign out_woready_1_963 = _out_wofireMux_T_896; // @[RegisterRouter.scala:87:24] assign out_woready_1_964 = _out_wofireMux_T_896; // @[RegisterRouter.scala:87:24] assign out_woready_1_965 = _out_wofireMux_T_896; // @[RegisterRouter.scala:87:24] assign out_woready_1_966 = _out_wofireMux_T_896; // @[RegisterRouter.scala:87:24] assign out_woready_1_967 = _out_wofireMux_T_896; // @[RegisterRouter.scala:87:24] assign out_woready_1_968 = _out_wofireMux_T_896; // @[RegisterRouter.scala:87:24] assign out_woready_1_969 = _out_wofireMux_T_896; // @[RegisterRouter.scala:87:24] assign out_woready_1_970 = _out_wofireMux_T_896; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_897 = ~_out_T_1849; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_899 = _out_wofireMux_T_262 & out_backSel_159; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_900 = _out_wofireMux_T_899 & _out_T_1765; // @[RegisterRouter.scala:87:24] assign out_woready_1_633 = _out_wofireMux_T_900; // @[RegisterRouter.scala:87:24] assign out_woready_1_634 = _out_wofireMux_T_900; // @[RegisterRouter.scala:87:24] assign out_woready_1_635 = _out_wofireMux_T_900; // @[RegisterRouter.scala:87:24] assign out_woready_1_636 = _out_wofireMux_T_900; // @[RegisterRouter.scala:87:24] assign out_woready_1_637 = _out_wofireMux_T_900; // @[RegisterRouter.scala:87:24] assign out_woready_1_638 = _out_wofireMux_T_900; // @[RegisterRouter.scala:87:24] assign out_woready_1_639 = _out_wofireMux_T_900; // @[RegisterRouter.scala:87:24] assign out_woready_1_640 = _out_wofireMux_T_900; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_901 = ~_out_T_1765; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_903 = _out_wofireMux_T_262 & out_backSel_160; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_904 = _out_wofireMux_T_903 & _out_T_1681; // @[RegisterRouter.scala:87:24] assign out_woready_1_320 = _out_wofireMux_T_904; // @[RegisterRouter.scala:87:24] assign out_woready_1_321 = _out_wofireMux_T_904; // @[RegisterRouter.scala:87:24] assign out_woready_1_322 = _out_wofireMux_T_904; // @[RegisterRouter.scala:87:24] assign out_woready_1_323 = _out_wofireMux_T_904; // @[RegisterRouter.scala:87:24] assign out_woready_1_324 = _out_wofireMux_T_904; // @[RegisterRouter.scala:87:24] assign out_woready_1_325 = _out_wofireMux_T_904; // @[RegisterRouter.scala:87:24] assign out_woready_1_326 = _out_wofireMux_T_904; // @[RegisterRouter.scala:87:24] assign out_woready_1_327 = _out_wofireMux_T_904; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_905 = ~_out_T_1681; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_907 = _out_wofireMux_T_262 & out_backSel_161; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_908 = _out_wofireMux_T_907 & _out_T_1745; // @[RegisterRouter.scala:87:24] assign out_woready_1_553 = _out_wofireMux_T_908; // @[RegisterRouter.scala:87:24] assign out_woready_1_554 = _out_wofireMux_T_908; // @[RegisterRouter.scala:87:24] assign out_woready_1_555 = _out_wofireMux_T_908; // @[RegisterRouter.scala:87:24] assign out_woready_1_556 = _out_wofireMux_T_908; // @[RegisterRouter.scala:87:24] assign out_woready_1_557 = _out_wofireMux_T_908; // @[RegisterRouter.scala:87:24] assign out_woready_1_558 = _out_wofireMux_T_908; // @[RegisterRouter.scala:87:24] assign out_woready_1_559 = _out_wofireMux_T_908; // @[RegisterRouter.scala:87:24] assign out_woready_1_560 = _out_wofireMux_T_908; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_909 = ~_out_T_1745; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_911 = _out_wofireMux_T_262 & out_backSel_162; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_912 = _out_wofireMux_T_911 & _out_T_1809; // @[RegisterRouter.scala:87:24] assign out_woready_1_803 = _out_wofireMux_T_912; // @[RegisterRouter.scala:87:24] assign out_woready_1_804 = _out_wofireMux_T_912; // @[RegisterRouter.scala:87:24] assign out_woready_1_805 = _out_wofireMux_T_912; // @[RegisterRouter.scala:87:24] assign out_woready_1_806 = _out_wofireMux_T_912; // @[RegisterRouter.scala:87:24] assign out_woready_1_807 = _out_wofireMux_T_912; // @[RegisterRouter.scala:87:24] assign out_woready_1_808 = _out_wofireMux_T_912; // @[RegisterRouter.scala:87:24] assign out_woready_1_809 = _out_wofireMux_T_912; // @[RegisterRouter.scala:87:24] assign out_woready_1_810 = _out_wofireMux_T_912; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_913 = ~_out_T_1809; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_915 = _out_wofireMux_T_262 & out_backSel_163; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_916 = _out_wofireMux_T_915 & _out_T_1895; // @[RegisterRouter.scala:87:24] assign out_woready_1_1147 = _out_wofireMux_T_916; // @[RegisterRouter.scala:87:24] assign out_woready_1_1148 = _out_wofireMux_T_916; // @[RegisterRouter.scala:87:24] assign out_woready_1_1149 = _out_wofireMux_T_916; // @[RegisterRouter.scala:87:24] assign out_woready_1_1150 = _out_wofireMux_T_916; // @[RegisterRouter.scala:87:24] assign out_woready_1_1151 = _out_wofireMux_T_916; // @[RegisterRouter.scala:87:24] assign out_woready_1_1152 = _out_wofireMux_T_916; // @[RegisterRouter.scala:87:24] assign out_woready_1_1153 = _out_wofireMux_T_916; // @[RegisterRouter.scala:87:24] assign out_woready_1_1154 = _out_wofireMux_T_916; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_917 = ~_out_T_1895; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_919 = _out_wofireMux_T_262 & out_backSel_164; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_920 = _out_wofireMux_T_919 & _out_T_1645; // @[RegisterRouter.scala:87:24] assign out_woready_1_176 = _out_wofireMux_T_920; // @[RegisterRouter.scala:87:24] assign out_woready_1_177 = _out_wofireMux_T_920; // @[RegisterRouter.scala:87:24] assign out_woready_1_178 = _out_wofireMux_T_920; // @[RegisterRouter.scala:87:24] assign out_woready_1_179 = _out_wofireMux_T_920; // @[RegisterRouter.scala:87:24] assign out_woready_1_180 = _out_wofireMux_T_920; // @[RegisterRouter.scala:87:24] assign out_woready_1_181 = _out_wofireMux_T_920; // @[RegisterRouter.scala:87:24] assign out_woready_1_182 = _out_wofireMux_T_920; // @[RegisterRouter.scala:87:24] assign out_woready_1_183 = _out_wofireMux_T_920; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_921 = ~_out_T_1645; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_923 = _out_wofireMux_T_262 & out_backSel_165; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_924 = _out_wofireMux_T_923 & _out_T_1687; // @[RegisterRouter.scala:87:24] assign out_woready_1_344 = _out_wofireMux_T_924; // @[RegisterRouter.scala:87:24] assign out_woready_1_345 = _out_wofireMux_T_924; // @[RegisterRouter.scala:87:24] assign out_woready_1_346 = _out_wofireMux_T_924; // @[RegisterRouter.scala:87:24] assign out_woready_1_347 = _out_wofireMux_T_924; // @[RegisterRouter.scala:87:24] assign out_woready_1_348 = _out_wofireMux_T_924; // @[RegisterRouter.scala:87:24] assign out_woready_1_349 = _out_wofireMux_T_924; // @[RegisterRouter.scala:87:24] assign out_woready_1_350 = _out_wofireMux_T_924; // @[RegisterRouter.scala:87:24] assign out_woready_1_351 = _out_wofireMux_T_924; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_925 = ~_out_T_1687; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_927 = _out_wofireMux_T_262 & out_backSel_166; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_928 = _out_wofireMux_T_927 & _out_T_1737; // @[RegisterRouter.scala:87:24] assign out_woready_1_527 = _out_wofireMux_T_928; // @[RegisterRouter.scala:87:24] assign out_woready_1_528 = _out_wofireMux_T_928; // @[RegisterRouter.scala:87:24] assign out_woready_1_529 = _out_wofireMux_T_928; // @[RegisterRouter.scala:87:24] assign out_woready_1_530 = _out_wofireMux_T_928; // @[RegisterRouter.scala:87:24] assign out_woready_1_531 = _out_wofireMux_T_928; // @[RegisterRouter.scala:87:24] assign out_woready_1_532 = _out_wofireMux_T_928; // @[RegisterRouter.scala:87:24] assign out_woready_1_533 = _out_wofireMux_T_928; // @[RegisterRouter.scala:87:24] assign out_woready_1_534 = _out_wofireMux_T_928; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_929 = ~_out_T_1737; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_931 = _out_wofireMux_T_262 & out_backSel_167; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_932 = _out_wofireMux_T_931 & _out_T_1807; // @[RegisterRouter.scala:87:24] assign out_woready_1_795 = _out_wofireMux_T_932; // @[RegisterRouter.scala:87:24] assign out_woready_1_796 = _out_wofireMux_T_932; // @[RegisterRouter.scala:87:24] assign out_woready_1_797 = _out_wofireMux_T_932; // @[RegisterRouter.scala:87:24] assign out_woready_1_798 = _out_wofireMux_T_932; // @[RegisterRouter.scala:87:24] assign out_woready_1_799 = _out_wofireMux_T_932; // @[RegisterRouter.scala:87:24] assign out_woready_1_800 = _out_wofireMux_T_932; // @[RegisterRouter.scala:87:24] assign out_woready_1_801 = _out_wofireMux_T_932; // @[RegisterRouter.scala:87:24] assign out_woready_1_802 = _out_wofireMux_T_932; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_933 = ~_out_T_1807; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_935 = _out_wofireMux_T_262 & out_backSel_168; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_936 = _out_wofireMux_T_935 & _out_T_1875; // @[RegisterRouter.scala:87:24] assign out_woready_1_1067 = _out_wofireMux_T_936; // @[RegisterRouter.scala:87:24] assign out_woready_1_1068 = _out_wofireMux_T_936; // @[RegisterRouter.scala:87:24] assign out_woready_1_1069 = _out_wofireMux_T_936; // @[RegisterRouter.scala:87:24] assign out_woready_1_1070 = _out_wofireMux_T_936; // @[RegisterRouter.scala:87:24] assign out_woready_1_1071 = _out_wofireMux_T_936; // @[RegisterRouter.scala:87:24] assign out_woready_1_1072 = _out_wofireMux_T_936; // @[RegisterRouter.scala:87:24] assign out_woready_1_1073 = _out_wofireMux_T_936; // @[RegisterRouter.scala:87:24] assign out_woready_1_1074 = _out_wofireMux_T_936; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_937 = ~_out_T_1875; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_939 = _out_wofireMux_T_262 & out_backSel_169; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_940 = _out_wofireMux_T_939 & _out_T_1703; // @[RegisterRouter.scala:87:24] assign out_woready_1_402 = _out_wofireMux_T_940; // @[RegisterRouter.scala:87:24] assign out_woready_1_403 = _out_wofireMux_T_940; // @[RegisterRouter.scala:87:24] assign out_woready_1_404 = _out_wofireMux_T_940; // @[RegisterRouter.scala:87:24] assign out_woready_1_405 = _out_wofireMux_T_940; // @[RegisterRouter.scala:87:24] assign out_woready_1_406 = _out_wofireMux_T_940; // @[RegisterRouter.scala:87:24] assign out_woready_1_407 = _out_wofireMux_T_940; // @[RegisterRouter.scala:87:24] assign out_woready_1_408 = _out_wofireMux_T_940; // @[RegisterRouter.scala:87:24] assign out_woready_1_409 = _out_wofireMux_T_940; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_941 = ~_out_T_1703; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_943 = _out_wofireMux_T_262 & out_backSel_170; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_944 = _out_wofireMux_T_943 & _out_T_1607; // @[RegisterRouter.scala:87:24] assign out_woready_1_24 = _out_wofireMux_T_944; // @[RegisterRouter.scala:87:24] assign out_woready_1_25 = _out_wofireMux_T_944; // @[RegisterRouter.scala:87:24] assign out_woready_1_26 = _out_wofireMux_T_944; // @[RegisterRouter.scala:87:24] assign out_woready_1_27 = _out_wofireMux_T_944; // @[RegisterRouter.scala:87:24] assign out_woready_1_28 = _out_wofireMux_T_944; // @[RegisterRouter.scala:87:24] assign out_woready_1_29 = _out_wofireMux_T_944; // @[RegisterRouter.scala:87:24] assign out_woready_1_30 = _out_wofireMux_T_944; // @[RegisterRouter.scala:87:24] assign out_woready_1_31 = _out_wofireMux_T_944; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_945 = ~_out_T_1607; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_947 = _out_wofireMux_T_262 & out_backSel_171; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_948 = _out_wofireMux_T_947 & _out_T_1855; // @[RegisterRouter.scala:87:24] assign out_woready_1_987 = _out_wofireMux_T_948; // @[RegisterRouter.scala:87:24] assign out_woready_1_988 = _out_wofireMux_T_948; // @[RegisterRouter.scala:87:24] assign out_woready_1_989 = _out_wofireMux_T_948; // @[RegisterRouter.scala:87:24] assign out_woready_1_990 = _out_wofireMux_T_948; // @[RegisterRouter.scala:87:24] assign out_woready_1_991 = _out_wofireMux_T_948; // @[RegisterRouter.scala:87:24] assign out_woready_1_992 = _out_wofireMux_T_948; // @[RegisterRouter.scala:87:24] assign out_woready_1_993 = _out_wofireMux_T_948; // @[RegisterRouter.scala:87:24] assign out_woready_1_994 = _out_wofireMux_T_948; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_949 = ~_out_T_1855; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_951 = _out_wofireMux_T_262 & out_backSel_172; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_952 = _out_wofireMux_T_951 & _out_T_1769; // @[RegisterRouter.scala:87:24] assign out_woready_1_649 = _out_wofireMux_T_952; // @[RegisterRouter.scala:87:24] assign out_woready_1_650 = _out_wofireMux_T_952; // @[RegisterRouter.scala:87:24] assign out_woready_1_651 = _out_wofireMux_T_952; // @[RegisterRouter.scala:87:24] assign out_woready_1_652 = _out_wofireMux_T_952; // @[RegisterRouter.scala:87:24] assign out_woready_1_653 = _out_wofireMux_T_952; // @[RegisterRouter.scala:87:24] assign out_woready_1_654 = _out_wofireMux_T_952; // @[RegisterRouter.scala:87:24] assign out_woready_1_655 = _out_wofireMux_T_952; // @[RegisterRouter.scala:87:24] assign out_woready_1_656 = _out_wofireMux_T_952; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_953 = ~_out_T_1769; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_955 = _out_wofireMux_T_262 & out_backSel_173; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_956 = _out_wofireMux_T_955 & _out_T_1719; // @[RegisterRouter.scala:87:24] assign out_woready_1_459 = _out_wofireMux_T_956; // @[RegisterRouter.scala:87:24] assign out_woready_1_460 = _out_wofireMux_T_956; // @[RegisterRouter.scala:87:24] assign out_woready_1_461 = _out_wofireMux_T_956; // @[RegisterRouter.scala:87:24] assign out_woready_1_462 = _out_wofireMux_T_956; // @[RegisterRouter.scala:87:24] assign out_woready_1_463 = _out_wofireMux_T_956; // @[RegisterRouter.scala:87:24] assign out_woready_1_464 = _out_wofireMux_T_956; // @[RegisterRouter.scala:87:24] assign out_woready_1_465 = _out_wofireMux_T_956; // @[RegisterRouter.scala:87:24] assign out_woready_1_466 = _out_wofireMux_T_956; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_957 = ~_out_T_1719; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_959 = _out_wofireMux_T_262 & out_backSel_174; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_960 = _out_wofireMux_T_959 & _out_T_1621; // @[RegisterRouter.scala:87:24] assign out_woready_1_80 = _out_wofireMux_T_960; // @[RegisterRouter.scala:87:24] assign out_woready_1_81 = _out_wofireMux_T_960; // @[RegisterRouter.scala:87:24] assign out_woready_1_82 = _out_wofireMux_T_960; // @[RegisterRouter.scala:87:24] assign out_woready_1_83 = _out_wofireMux_T_960; // @[RegisterRouter.scala:87:24] assign out_woready_1_84 = _out_wofireMux_T_960; // @[RegisterRouter.scala:87:24] assign out_woready_1_85 = _out_wofireMux_T_960; // @[RegisterRouter.scala:87:24] assign out_woready_1_86 = _out_wofireMux_T_960; // @[RegisterRouter.scala:87:24] assign out_woready_1_87 = _out_wofireMux_T_960; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_961 = ~_out_T_1621; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_963 = _out_wofireMux_T_262 & out_backSel_175; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_964 = _out_wofireMux_T_963 & _out_T_1833; // @[RegisterRouter.scala:87:24] assign out_woready_1_899 = _out_wofireMux_T_964; // @[RegisterRouter.scala:87:24] assign out_woready_1_900 = _out_wofireMux_T_964; // @[RegisterRouter.scala:87:24] assign out_woready_1_901 = _out_wofireMux_T_964; // @[RegisterRouter.scala:87:24] assign out_woready_1_902 = _out_wofireMux_T_964; // @[RegisterRouter.scala:87:24] assign out_woready_1_903 = _out_wofireMux_T_964; // @[RegisterRouter.scala:87:24] assign out_woready_1_904 = _out_wofireMux_T_964; // @[RegisterRouter.scala:87:24] assign out_woready_1_905 = _out_wofireMux_T_964; // @[RegisterRouter.scala:87:24] assign out_woready_1_906 = _out_wofireMux_T_964; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_965 = ~_out_T_1833; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_967 = _out_wofireMux_T_262 & out_backSel_176; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_968 = _out_wofireMux_T_967 & _out_T_1751; // @[RegisterRouter.scala:87:24] assign out_woready_1_577 = _out_wofireMux_T_968; // @[RegisterRouter.scala:87:24] assign out_woready_1_578 = _out_wofireMux_T_968; // @[RegisterRouter.scala:87:24] assign out_woready_1_579 = _out_wofireMux_T_968; // @[RegisterRouter.scala:87:24] assign out_woready_1_580 = _out_wofireMux_T_968; // @[RegisterRouter.scala:87:24] assign out_woready_1_581 = _out_wofireMux_T_968; // @[RegisterRouter.scala:87:24] assign out_woready_1_582 = _out_wofireMux_T_968; // @[RegisterRouter.scala:87:24] assign out_woready_1_583 = _out_wofireMux_T_968; // @[RegisterRouter.scala:87:24] assign out_woready_1_584 = _out_wofireMux_T_968; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_969 = ~_out_T_1751; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_971 = _out_wofireMux_T_262 & out_backSel_177; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_972 = _out_wofireMux_T_971 & _out_T_1827; // @[RegisterRouter.scala:87:24] assign out_woready_1_875 = _out_wofireMux_T_972; // @[RegisterRouter.scala:87:24] assign out_woready_1_876 = _out_wofireMux_T_972; // @[RegisterRouter.scala:87:24] assign out_woready_1_877 = _out_wofireMux_T_972; // @[RegisterRouter.scala:87:24] assign out_woready_1_878 = _out_wofireMux_T_972; // @[RegisterRouter.scala:87:24] assign out_woready_1_879 = _out_wofireMux_T_972; // @[RegisterRouter.scala:87:24] assign out_woready_1_880 = _out_wofireMux_T_972; // @[RegisterRouter.scala:87:24] assign out_woready_1_881 = _out_wofireMux_T_972; // @[RegisterRouter.scala:87:24] assign out_woready_1_882 = _out_wofireMux_T_972; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_973 = ~_out_T_1827; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_975 = _out_wofireMux_T_262 & out_backSel_178; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_976 = _out_wofireMux_T_975 & _out_T_1893; // @[RegisterRouter.scala:87:24] assign out_woready_1_1139 = _out_wofireMux_T_976; // @[RegisterRouter.scala:87:24] assign out_woready_1_1140 = _out_wofireMux_T_976; // @[RegisterRouter.scala:87:24] assign out_woready_1_1141 = _out_wofireMux_T_976; // @[RegisterRouter.scala:87:24] assign out_woready_1_1142 = _out_wofireMux_T_976; // @[RegisterRouter.scala:87:24] assign out_woready_1_1143 = _out_wofireMux_T_976; // @[RegisterRouter.scala:87:24] assign out_woready_1_1144 = _out_wofireMux_T_976; // @[RegisterRouter.scala:87:24] assign out_woready_1_1145 = _out_wofireMux_T_976; // @[RegisterRouter.scala:87:24] assign out_woready_1_1146 = _out_wofireMux_T_976; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_977 = ~_out_T_1893; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_979 = _out_wofireMux_T_262 & out_backSel_179; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_980 = _out_wofireMux_T_979 & _out_T_1647; // @[RegisterRouter.scala:87:24] assign out_woready_1_184 = _out_wofireMux_T_980; // @[RegisterRouter.scala:87:24] assign out_woready_1_185 = _out_wofireMux_T_980; // @[RegisterRouter.scala:87:24] assign out_woready_1_186 = _out_wofireMux_T_980; // @[RegisterRouter.scala:87:24] assign out_woready_1_187 = _out_wofireMux_T_980; // @[RegisterRouter.scala:87:24] assign out_woready_1_188 = _out_wofireMux_T_980; // @[RegisterRouter.scala:87:24] assign out_woready_1_189 = _out_wofireMux_T_980; // @[RegisterRouter.scala:87:24] assign out_woready_1_190 = _out_wofireMux_T_980; // @[RegisterRouter.scala:87:24] assign out_woready_1_191 = _out_wofireMux_T_980; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_981 = ~_out_T_1647; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_983 = _out_wofireMux_T_262 & out_backSel_180; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_984 = _out_wofireMux_T_983 & _out_T_1747; // @[RegisterRouter.scala:87:24] assign out_woready_1_561 = _out_wofireMux_T_984; // @[RegisterRouter.scala:87:24] assign out_woready_1_562 = _out_wofireMux_T_984; // @[RegisterRouter.scala:87:24] assign out_woready_1_563 = _out_wofireMux_T_984; // @[RegisterRouter.scala:87:24] assign out_woready_1_564 = _out_wofireMux_T_984; // @[RegisterRouter.scala:87:24] assign out_woready_1_565 = _out_wofireMux_T_984; // @[RegisterRouter.scala:87:24] assign out_woready_1_566 = _out_wofireMux_T_984; // @[RegisterRouter.scala:87:24] assign out_woready_1_567 = _out_wofireMux_T_984; // @[RegisterRouter.scala:87:24] assign out_woready_1_568 = _out_wofireMux_T_984; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_985 = ~_out_T_1747; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_987 = _out_wofireMux_T_262 & out_backSel_181; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_988 = _out_wofireMux_T_987 & _out_T_1763; // @[RegisterRouter.scala:87:24] assign out_woready_1_625 = _out_wofireMux_T_988; // @[RegisterRouter.scala:87:24] assign out_woready_1_626 = _out_wofireMux_T_988; // @[RegisterRouter.scala:87:24] assign out_woready_1_627 = _out_wofireMux_T_988; // @[RegisterRouter.scala:87:24] assign out_woready_1_628 = _out_wofireMux_T_988; // @[RegisterRouter.scala:87:24] assign out_woready_1_629 = _out_wofireMux_T_988; // @[RegisterRouter.scala:87:24] assign out_woready_1_630 = _out_wofireMux_T_988; // @[RegisterRouter.scala:87:24] assign out_woready_1_631 = _out_wofireMux_T_988; // @[RegisterRouter.scala:87:24] assign out_woready_1_632 = _out_wofireMux_T_988; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_989 = ~_out_T_1763; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_991 = _out_wofireMux_T_262 & out_backSel_182; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_992 = _out_wofireMux_T_991 & _out_T_1829; // @[RegisterRouter.scala:87:24] assign out_woready_1_883 = _out_wofireMux_T_992; // @[RegisterRouter.scala:87:24] assign out_woready_1_884 = _out_wofireMux_T_992; // @[RegisterRouter.scala:87:24] assign out_woready_1_885 = _out_wofireMux_T_992; // @[RegisterRouter.scala:87:24] assign out_woready_1_886 = _out_wofireMux_T_992; // @[RegisterRouter.scala:87:24] assign out_woready_1_887 = _out_wofireMux_T_992; // @[RegisterRouter.scala:87:24] assign out_woready_1_888 = _out_wofireMux_T_992; // @[RegisterRouter.scala:87:24] assign out_woready_1_889 = _out_wofireMux_T_992; // @[RegisterRouter.scala:87:24] assign out_woready_1_890 = _out_wofireMux_T_992; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_993 = ~_out_T_1829; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_995 = _out_wofireMux_T_262 & out_backSel_183; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_996 = _out_wofireMux_T_995 & _out_T_1873; // @[RegisterRouter.scala:87:24] assign out_woready_1_1059 = _out_wofireMux_T_996; // @[RegisterRouter.scala:87:24] assign out_woready_1_1060 = _out_wofireMux_T_996; // @[RegisterRouter.scala:87:24] assign out_woready_1_1061 = _out_wofireMux_T_996; // @[RegisterRouter.scala:87:24] assign out_woready_1_1062 = _out_wofireMux_T_996; // @[RegisterRouter.scala:87:24] assign out_woready_1_1063 = _out_wofireMux_T_996; // @[RegisterRouter.scala:87:24] assign out_woready_1_1064 = _out_wofireMux_T_996; // @[RegisterRouter.scala:87:24] assign out_woready_1_1065 = _out_wofireMux_T_996; // @[RegisterRouter.scala:87:24] assign out_woready_1_1066 = _out_wofireMux_T_996; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_997 = ~_out_T_1873; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_999 = _out_wofireMux_T_262 & out_backSel_184; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1000 = _out_wofireMux_T_999 & _out_T_1627; // @[RegisterRouter.scala:87:24] assign out_woready_1_104 = _out_wofireMux_T_1000; // @[RegisterRouter.scala:87:24] assign out_woready_1_105 = _out_wofireMux_T_1000; // @[RegisterRouter.scala:87:24] assign out_woready_1_106 = _out_wofireMux_T_1000; // @[RegisterRouter.scala:87:24] assign out_woready_1_107 = _out_wofireMux_T_1000; // @[RegisterRouter.scala:87:24] assign out_woready_1_108 = _out_wofireMux_T_1000; // @[RegisterRouter.scala:87:24] assign out_woready_1_109 = _out_wofireMux_T_1000; // @[RegisterRouter.scala:87:24] assign out_woready_1_110 = _out_wofireMux_T_1000; // @[RegisterRouter.scala:87:24] assign out_woready_1_111 = _out_wofireMux_T_1000; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1001 = ~_out_T_1627; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1003 = _out_wofireMux_T_262 & out_backSel_185; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1004 = _out_wofireMux_T_1003 & _out_T_1623; // @[RegisterRouter.scala:87:24] assign out_woready_1_88 = _out_wofireMux_T_1004; // @[RegisterRouter.scala:87:24] assign out_woready_1_89 = _out_wofireMux_T_1004; // @[RegisterRouter.scala:87:24] assign out_woready_1_90 = _out_wofireMux_T_1004; // @[RegisterRouter.scala:87:24] assign out_woready_1_91 = _out_wofireMux_T_1004; // @[RegisterRouter.scala:87:24] assign out_woready_1_92 = _out_wofireMux_T_1004; // @[RegisterRouter.scala:87:24] assign out_woready_1_93 = _out_wofireMux_T_1004; // @[RegisterRouter.scala:87:24] assign out_woready_1_94 = _out_wofireMux_T_1004; // @[RegisterRouter.scala:87:24] assign out_woready_1_95 = _out_wofireMux_T_1004; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1005 = ~_out_T_1623; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1007 = _out_wofireMux_T_262 & out_backSel_186; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1008 = _out_wofireMux_T_1007 & _out_T_1851; // @[RegisterRouter.scala:87:24] assign out_woready_1_971 = _out_wofireMux_T_1008; // @[RegisterRouter.scala:87:24] assign out_woready_1_972 = _out_wofireMux_T_1008; // @[RegisterRouter.scala:87:24] assign out_woready_1_973 = _out_wofireMux_T_1008; // @[RegisterRouter.scala:87:24] assign out_woready_1_974 = _out_wofireMux_T_1008; // @[RegisterRouter.scala:87:24] assign out_woready_1_975 = _out_wofireMux_T_1008; // @[RegisterRouter.scala:87:24] assign out_woready_1_976 = _out_wofireMux_T_1008; // @[RegisterRouter.scala:87:24] assign out_woready_1_977 = _out_wofireMux_T_1008; // @[RegisterRouter.scala:87:24] assign out_woready_1_978 = _out_wofireMux_T_1008; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1009 = ~_out_T_1851; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1011 = _out_wofireMux_T_262 & out_backSel_187; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1012 = _out_wofireMux_T_1011 & _out_T_1767; // @[RegisterRouter.scala:87:24] assign out_woready_1_641 = _out_wofireMux_T_1012; // @[RegisterRouter.scala:87:24] assign out_woready_1_642 = _out_wofireMux_T_1012; // @[RegisterRouter.scala:87:24] assign out_woready_1_643 = _out_wofireMux_T_1012; // @[RegisterRouter.scala:87:24] assign out_woready_1_644 = _out_wofireMux_T_1012; // @[RegisterRouter.scala:87:24] assign out_woready_1_645 = _out_wofireMux_T_1012; // @[RegisterRouter.scala:87:24] assign out_woready_1_646 = _out_wofireMux_T_1012; // @[RegisterRouter.scala:87:24] assign out_woready_1_647 = _out_wofireMux_T_1012; // @[RegisterRouter.scala:87:24] assign out_woready_1_648 = _out_wofireMux_T_1012; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1013 = ~_out_T_1767; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1015 = _out_wofireMux_T_262 & out_backSel_188; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1016 = _out_wofireMux_T_1015 & _out_T_1701; // @[RegisterRouter.scala:87:24] assign out_woready_1_394 = _out_wofireMux_T_1016; // @[RegisterRouter.scala:87:24] assign out_woready_1_395 = _out_wofireMux_T_1016; // @[RegisterRouter.scala:87:24] assign out_woready_1_396 = _out_wofireMux_T_1016; // @[RegisterRouter.scala:87:24] assign out_woready_1_397 = _out_wofireMux_T_1016; // @[RegisterRouter.scala:87:24] assign out_woready_1_398 = _out_wofireMux_T_1016; // @[RegisterRouter.scala:87:24] assign out_woready_1_399 = _out_wofireMux_T_1016; // @[RegisterRouter.scala:87:24] assign out_woready_1_400 = _out_wofireMux_T_1016; // @[RegisterRouter.scala:87:24] assign out_woready_1_401 = _out_wofireMux_T_1016; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1017 = ~_out_T_1701; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1019 = _out_wofireMux_T_262 & out_backSel_189; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1020 = _out_wofireMux_T_1019 & _out_T_1635; // @[RegisterRouter.scala:87:24] assign out_woready_1_136 = _out_wofireMux_T_1020; // @[RegisterRouter.scala:87:24] assign out_woready_1_137 = _out_wofireMux_T_1020; // @[RegisterRouter.scala:87:24] assign out_woready_1_138 = _out_wofireMux_T_1020; // @[RegisterRouter.scala:87:24] assign out_woready_1_139 = _out_wofireMux_T_1020; // @[RegisterRouter.scala:87:24] assign out_woready_1_140 = _out_wofireMux_T_1020; // @[RegisterRouter.scala:87:24] assign out_woready_1_141 = _out_wofireMux_T_1020; // @[RegisterRouter.scala:87:24] assign out_woready_1_142 = _out_wofireMux_T_1020; // @[RegisterRouter.scala:87:24] assign out_woready_1_143 = _out_wofireMux_T_1020; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1021 = ~_out_T_1635; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1023 = _out_wofireMux_T_262 & out_backSel_190; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1024 = _out_wofireMux_T_1023 & _out_T_1871; // @[RegisterRouter.scala:87:24] assign out_woready_1_1051 = _out_wofireMux_T_1024; // @[RegisterRouter.scala:87:24] assign out_woready_1_1052 = _out_wofireMux_T_1024; // @[RegisterRouter.scala:87:24] assign out_woready_1_1053 = _out_wofireMux_T_1024; // @[RegisterRouter.scala:87:24] assign out_woready_1_1054 = _out_wofireMux_T_1024; // @[RegisterRouter.scala:87:24] assign out_woready_1_1055 = _out_wofireMux_T_1024; // @[RegisterRouter.scala:87:24] assign out_woready_1_1056 = _out_wofireMux_T_1024; // @[RegisterRouter.scala:87:24] assign out_woready_1_1057 = _out_wofireMux_T_1024; // @[RegisterRouter.scala:87:24] assign out_woready_1_1058 = _out_wofireMux_T_1024; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1025 = ~_out_T_1871; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1027 = _out_wofireMux_T_262 & out_backSel_191; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1028 = _out_wofireMux_T_1027 & _out_T_1753; // @[RegisterRouter.scala:87:24] assign out_woready_1_585 = _out_wofireMux_T_1028; // @[RegisterRouter.scala:87:24] assign out_woready_1_586 = _out_wofireMux_T_1028; // @[RegisterRouter.scala:87:24] assign out_woready_1_587 = _out_wofireMux_T_1028; // @[RegisterRouter.scala:87:24] assign out_woready_1_588 = _out_wofireMux_T_1028; // @[RegisterRouter.scala:87:24] assign out_woready_1_589 = _out_wofireMux_T_1028; // @[RegisterRouter.scala:87:24] assign out_woready_1_590 = _out_wofireMux_T_1028; // @[RegisterRouter.scala:87:24] assign out_woready_1_591 = _out_wofireMux_T_1028; // @[RegisterRouter.scala:87:24] assign out_woready_1_592 = _out_wofireMux_T_1028; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1029 = ~_out_T_1753; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1031 = _out_wofireMux_T_262 & out_backSel_192; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1032 = _out_wofireMux_T_1031 & _out_T_1683; // @[RegisterRouter.scala:87:24] assign out_woready_1_328 = _out_wofireMux_T_1032; // @[RegisterRouter.scala:87:24] assign out_woready_1_329 = _out_wofireMux_T_1032; // @[RegisterRouter.scala:87:24] assign out_woready_1_330 = _out_wofireMux_T_1032; // @[RegisterRouter.scala:87:24] assign out_woready_1_331 = _out_wofireMux_T_1032; // @[RegisterRouter.scala:87:24] assign out_woready_1_332 = _out_wofireMux_T_1032; // @[RegisterRouter.scala:87:24] assign out_woready_1_333 = _out_wofireMux_T_1032; // @[RegisterRouter.scala:87:24] assign out_woready_1_334 = _out_wofireMux_T_1032; // @[RegisterRouter.scala:87:24] assign out_woready_1_335 = _out_wofireMux_T_1032; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1033 = ~_out_T_1683; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1035 = _out_wofireMux_T_262 & out_backSel_193; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1036 = _out_wofireMux_T_1035 & _out_T_1709; // @[RegisterRouter.scala:87:24] assign out_woready_1_426 = _out_wofireMux_T_1036; // @[RegisterRouter.scala:87:24] assign out_woready_1_427 = _out_wofireMux_T_1036; // @[RegisterRouter.scala:87:24] assign out_woready_1_428 = _out_wofireMux_T_1036; // @[RegisterRouter.scala:87:24] assign out_woready_1_429 = _out_wofireMux_T_1036; // @[RegisterRouter.scala:87:24] assign out_woready_1_430 = _out_wofireMux_T_1036; // @[RegisterRouter.scala:87:24] assign out_woready_1_431 = _out_wofireMux_T_1036; // @[RegisterRouter.scala:87:24] assign out_woready_1_432 = _out_wofireMux_T_1036; // @[RegisterRouter.scala:87:24] assign out_woready_1_433 = _out_wofireMux_T_1036; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1037 = ~_out_T_1709; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1039 = _out_wofireMux_T_262 & out_backSel_194; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1040 = _out_wofireMux_T_1039 & _out_T_1817; // @[RegisterRouter.scala:87:24] assign out_woready_1_835 = _out_wofireMux_T_1040; // @[RegisterRouter.scala:87:24] assign out_woready_1_836 = _out_wofireMux_T_1040; // @[RegisterRouter.scala:87:24] assign out_woready_1_837 = _out_wofireMux_T_1040; // @[RegisterRouter.scala:87:24] assign out_woready_1_838 = _out_wofireMux_T_1040; // @[RegisterRouter.scala:87:24] assign out_woready_1_839 = _out_wofireMux_T_1040; // @[RegisterRouter.scala:87:24] assign out_woready_1_840 = _out_wofireMux_T_1040; // @[RegisterRouter.scala:87:24] assign out_woready_1_841 = _out_wofireMux_T_1040; // @[RegisterRouter.scala:87:24] assign out_woready_1_842 = _out_wofireMux_T_1040; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1041 = ~_out_T_1817; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1043 = _out_wofireMux_T_262 & out_backSel_195; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1044 = _out_wofireMux_T_1043 & _out_T_1885; // @[RegisterRouter.scala:87:24] assign out_woready_1_1107 = _out_wofireMux_T_1044; // @[RegisterRouter.scala:87:24] assign out_woready_1_1108 = _out_wofireMux_T_1044; // @[RegisterRouter.scala:87:24] assign out_woready_1_1109 = _out_wofireMux_T_1044; // @[RegisterRouter.scala:87:24] assign out_woready_1_1110 = _out_wofireMux_T_1044; // @[RegisterRouter.scala:87:24] assign out_woready_1_1111 = _out_wofireMux_T_1044; // @[RegisterRouter.scala:87:24] assign out_woready_1_1112 = _out_wofireMux_T_1044; // @[RegisterRouter.scala:87:24] assign out_woready_1_1113 = _out_wofireMux_T_1044; // @[RegisterRouter.scala:87:24] assign out_woready_1_1114 = _out_wofireMux_T_1044; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1045 = ~_out_T_1885; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1047 = _out_wofireMux_T_262 & out_backSel_196; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1048 = _out_wofireMux_T_1047 & _out_T_1631; // @[RegisterRouter.scala:87:24] assign out_woready_1_120 = _out_wofireMux_T_1048; // @[RegisterRouter.scala:87:24] assign out_woready_1_121 = _out_wofireMux_T_1048; // @[RegisterRouter.scala:87:24] assign out_woready_1_122 = _out_wofireMux_T_1048; // @[RegisterRouter.scala:87:24] assign out_woready_1_123 = _out_wofireMux_T_1048; // @[RegisterRouter.scala:87:24] assign out_woready_1_124 = _out_wofireMux_T_1048; // @[RegisterRouter.scala:87:24] assign out_woready_1_125 = _out_wofireMux_T_1048; // @[RegisterRouter.scala:87:24] assign out_woready_1_126 = _out_wofireMux_T_1048; // @[RegisterRouter.scala:87:24] assign out_woready_1_127 = _out_wofireMux_T_1048; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1049 = ~_out_T_1631; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1051 = _out_wofireMux_T_262 & out_backSel_197; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1052 = _out_wofireMux_T_1051 & _out_T_1695; // @[RegisterRouter.scala:87:24] assign out_woready_1_370 = _out_wofireMux_T_1052; // @[RegisterRouter.scala:87:24] assign out_woready_1_371 = _out_wofireMux_T_1052; // @[RegisterRouter.scala:87:24] assign out_woready_1_372 = _out_wofireMux_T_1052; // @[RegisterRouter.scala:87:24] assign out_woready_1_373 = _out_wofireMux_T_1052; // @[RegisterRouter.scala:87:24] assign out_woready_1_374 = _out_wofireMux_T_1052; // @[RegisterRouter.scala:87:24] assign out_woready_1_375 = _out_wofireMux_T_1052; // @[RegisterRouter.scala:87:24] assign out_woready_1_376 = _out_wofireMux_T_1052; // @[RegisterRouter.scala:87:24] assign out_woready_1_377 = _out_wofireMux_T_1052; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1053 = ~_out_T_1695; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1055 = _out_wofireMux_T_262 & out_backSel_198; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1056 = _out_wofireMux_T_1055 & _out_T_1789; // @[RegisterRouter.scala:87:24] assign out_woready_1_723 = _out_wofireMux_T_1056; // @[RegisterRouter.scala:87:24] assign out_woready_1_724 = _out_wofireMux_T_1056; // @[RegisterRouter.scala:87:24] assign out_woready_1_725 = _out_wofireMux_T_1056; // @[RegisterRouter.scala:87:24] assign out_woready_1_726 = _out_wofireMux_T_1056; // @[RegisterRouter.scala:87:24] assign out_woready_1_727 = _out_wofireMux_T_1056; // @[RegisterRouter.scala:87:24] assign out_woready_1_728 = _out_wofireMux_T_1056; // @[RegisterRouter.scala:87:24] assign out_woready_1_729 = _out_wofireMux_T_1056; // @[RegisterRouter.scala:87:24] assign out_woready_1_730 = _out_wofireMux_T_1056; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1057 = ~_out_T_1789; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1059 = _out_wofireMux_T_262 & out_backSel_199; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1060 = _out_wofireMux_T_1059 & _out_T_1825; // @[RegisterRouter.scala:87:24] assign out_woready_1_867 = _out_wofireMux_T_1060; // @[RegisterRouter.scala:87:24] assign out_woready_1_868 = _out_wofireMux_T_1060; // @[RegisterRouter.scala:87:24] assign out_woready_1_869 = _out_wofireMux_T_1060; // @[RegisterRouter.scala:87:24] assign out_woready_1_870 = _out_wofireMux_T_1060; // @[RegisterRouter.scala:87:24] assign out_woready_1_871 = _out_wofireMux_T_1060; // @[RegisterRouter.scala:87:24] assign out_woready_1_872 = _out_wofireMux_T_1060; // @[RegisterRouter.scala:87:24] assign out_woready_1_873 = _out_wofireMux_T_1060; // @[RegisterRouter.scala:87:24] assign out_woready_1_874 = _out_wofireMux_T_1060; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1061 = ~_out_T_1825; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1063 = _out_wofireMux_T_262 & out_backSel_200; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1064 = _out_wofireMux_T_1063 & _out_T_1897; // @[RegisterRouter.scala:87:24] assign out_woready_1_1155 = _out_wofireMux_T_1064; // @[RegisterRouter.scala:87:24] assign out_woready_1_1156 = _out_wofireMux_T_1064; // @[RegisterRouter.scala:87:24] assign out_woready_1_1157 = _out_wofireMux_T_1064; // @[RegisterRouter.scala:87:24] assign out_woready_1_1158 = _out_wofireMux_T_1064; // @[RegisterRouter.scala:87:24] assign out_woready_1_1159 = _out_wofireMux_T_1064; // @[RegisterRouter.scala:87:24] assign out_woready_1_1160 = _out_wofireMux_T_1064; // @[RegisterRouter.scala:87:24] assign out_woready_1_1161 = _out_wofireMux_T_1064; // @[RegisterRouter.scala:87:24] assign out_woready_1_1162 = _out_wofireMux_T_1064; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1065 = ~_out_T_1897; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1067 = _out_wofireMux_T_262 & out_backSel_201; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1068 = _out_wofireMux_T_1067 & _out_T_1675; // @[RegisterRouter.scala:87:24] assign out_woready_1_296 = _out_wofireMux_T_1068; // @[RegisterRouter.scala:87:24] assign out_woready_1_297 = _out_wofireMux_T_1068; // @[RegisterRouter.scala:87:24] assign out_woready_1_298 = _out_wofireMux_T_1068; // @[RegisterRouter.scala:87:24] assign out_woready_1_299 = _out_wofireMux_T_1068; // @[RegisterRouter.scala:87:24] assign out_woready_1_300 = _out_wofireMux_T_1068; // @[RegisterRouter.scala:87:24] assign out_woready_1_301 = _out_wofireMux_T_1068; // @[RegisterRouter.scala:87:24] assign out_woready_1_302 = _out_wofireMux_T_1068; // @[RegisterRouter.scala:87:24] assign out_woready_1_303 = _out_wofireMux_T_1068; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1069 = ~_out_T_1675; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1071 = _out_wofireMux_T_262 & out_backSel_202; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1072 = _out_wofireMux_T_1071 & _out_T_1615; // @[RegisterRouter.scala:87:24] assign out_woready_1_56 = _out_wofireMux_T_1072; // @[RegisterRouter.scala:87:24] assign out_woready_1_57 = _out_wofireMux_T_1072; // @[RegisterRouter.scala:87:24] assign out_woready_1_58 = _out_wofireMux_T_1072; // @[RegisterRouter.scala:87:24] assign out_woready_1_59 = _out_wofireMux_T_1072; // @[RegisterRouter.scala:87:24] assign out_woready_1_60 = _out_wofireMux_T_1072; // @[RegisterRouter.scala:87:24] assign out_woready_1_61 = _out_wofireMux_T_1072; // @[RegisterRouter.scala:87:24] assign out_woready_1_62 = _out_wofireMux_T_1072; // @[RegisterRouter.scala:87:24] assign out_woready_1_63 = _out_wofireMux_T_1072; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1073 = ~_out_T_1615; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1075 = _out_wofireMux_T_262 & out_backSel_203; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1076 = _out_wofireMux_T_1075 & _out_T_1837; // @[RegisterRouter.scala:87:24] assign out_woready_1_915 = _out_wofireMux_T_1076; // @[RegisterRouter.scala:87:24] assign out_woready_1_916 = _out_wofireMux_T_1076; // @[RegisterRouter.scala:87:24] assign out_woready_1_917 = _out_wofireMux_T_1076; // @[RegisterRouter.scala:87:24] assign out_woready_1_918 = _out_wofireMux_T_1076; // @[RegisterRouter.scala:87:24] assign out_woready_1_919 = _out_wofireMux_T_1076; // @[RegisterRouter.scala:87:24] assign out_woready_1_920 = _out_wofireMux_T_1076; // @[RegisterRouter.scala:87:24] assign out_woready_1_921 = _out_wofireMux_T_1076; // @[RegisterRouter.scala:87:24] assign out_woready_1_922 = _out_wofireMux_T_1076; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1077 = ~_out_T_1837; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1079 = _out_wofireMux_T_262 & out_backSel_204; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1080 = _out_wofireMux_T_1079 & _out_T_1755; // @[RegisterRouter.scala:87:24] assign out_woready_1_593 = _out_wofireMux_T_1080; // @[RegisterRouter.scala:87:24] assign out_woready_1_594 = _out_wofireMux_T_1080; // @[RegisterRouter.scala:87:24] assign out_woready_1_595 = _out_wofireMux_T_1080; // @[RegisterRouter.scala:87:24] assign out_woready_1_596 = _out_wofireMux_T_1080; // @[RegisterRouter.scala:87:24] assign out_woready_1_597 = _out_wofireMux_T_1080; // @[RegisterRouter.scala:87:24] assign out_woready_1_598 = _out_wofireMux_T_1080; // @[RegisterRouter.scala:87:24] assign out_woready_1_599 = _out_wofireMux_T_1080; // @[RegisterRouter.scala:87:24] assign out_woready_1_600 = _out_wofireMux_T_1080; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1081 = ~_out_T_1755; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1083 = _out_wofireMux_T_262 & out_backSel_205; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1084 = _out_wofireMux_T_1083 & _out_T_1727; // @[RegisterRouter.scala:87:24] assign out_woready_1_487 = _out_wofireMux_T_1084; // @[RegisterRouter.scala:87:24] assign out_woready_1_488 = _out_wofireMux_T_1084; // @[RegisterRouter.scala:87:24] assign out_woready_1_489 = _out_wofireMux_T_1084; // @[RegisterRouter.scala:87:24] assign out_woready_1_490 = _out_wofireMux_T_1084; // @[RegisterRouter.scala:87:24] assign out_woready_1_491 = _out_wofireMux_T_1084; // @[RegisterRouter.scala:87:24] assign out_woready_1_492 = _out_wofireMux_T_1084; // @[RegisterRouter.scala:87:24] assign out_woready_1_493 = _out_wofireMux_T_1084; // @[RegisterRouter.scala:87:24] assign out_woready_1_494 = _out_wofireMux_T_1084; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1085 = ~_out_T_1727; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1087 = _out_wofireMux_T_262 & out_backSel_206; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1088 = _out_wofireMux_T_1087 & _out_T_1669; // @[RegisterRouter.scala:87:24] assign out_woready_1_272 = _out_wofireMux_T_1088; // @[RegisterRouter.scala:87:24] assign out_woready_1_273 = _out_wofireMux_T_1088; // @[RegisterRouter.scala:87:24] assign out_woready_1_274 = _out_wofireMux_T_1088; // @[RegisterRouter.scala:87:24] assign out_woready_1_275 = _out_wofireMux_T_1088; // @[RegisterRouter.scala:87:24] assign out_woready_1_276 = _out_wofireMux_T_1088; // @[RegisterRouter.scala:87:24] assign out_woready_1_277 = _out_wofireMux_T_1088; // @[RegisterRouter.scala:87:24] assign out_woready_1_278 = _out_wofireMux_T_1088; // @[RegisterRouter.scala:87:24] assign out_woready_1_279 = _out_wofireMux_T_1088; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1089 = ~_out_T_1669; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1091 = _out_wofireMux_T_262 & out_backSel_207; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1092 = _out_wofireMux_T_1091 & _out_T_1859; // @[RegisterRouter.scala:87:24] assign out_woready_1_1003 = _out_wofireMux_T_1092; // @[RegisterRouter.scala:87:24] assign out_woready_1_1004 = _out_wofireMux_T_1092; // @[RegisterRouter.scala:87:24] assign out_woready_1_1005 = _out_wofireMux_T_1092; // @[RegisterRouter.scala:87:24] assign out_woready_1_1006 = _out_wofireMux_T_1092; // @[RegisterRouter.scala:87:24] assign out_woready_1_1007 = _out_wofireMux_T_1092; // @[RegisterRouter.scala:87:24] assign out_woready_1_1008 = _out_wofireMux_T_1092; // @[RegisterRouter.scala:87:24] assign out_woready_1_1009 = _out_wofireMux_T_1092; // @[RegisterRouter.scala:87:24] assign out_woready_1_1010 = _out_wofireMux_T_1092; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1093 = ~_out_T_1859; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1095 = _out_wofireMux_T_262 & out_backSel_208; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1096 = _out_wofireMux_T_1095 & _out_T_1779; // @[RegisterRouter.scala:87:24] assign out_woready_1_689 = _out_wofireMux_T_1096; // @[RegisterRouter.scala:87:24] assign out_woready_1_690 = _out_wofireMux_T_1096; // @[RegisterRouter.scala:87:24] assign out_woready_1_691 = _out_wofireMux_T_1096; // @[RegisterRouter.scala:87:24] assign out_woready_1_692 = _out_wofireMux_T_1096; // @[RegisterRouter.scala:87:24] assign out_woready_1_693 = _out_wofireMux_T_1096; // @[RegisterRouter.scala:87:24] assign out_woready_1_694 = _out_wofireMux_T_1096; // @[RegisterRouter.scala:87:24] assign out_woready_1_695 = _out_wofireMux_T_1096; // @[RegisterRouter.scala:87:24] assign out_woready_1_696 = _out_wofireMux_T_1096; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1097 = ~_out_T_1779; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1099 = _out_wofireMux_T_262 & out_backSel_209; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1100 = _out_wofireMux_T_1099 & _out_T_1813; // @[RegisterRouter.scala:87:24] assign out_woready_1_819 = _out_wofireMux_T_1100; // @[RegisterRouter.scala:87:24] assign out_woready_1_820 = _out_wofireMux_T_1100; // @[RegisterRouter.scala:87:24] assign out_woready_1_821 = _out_wofireMux_T_1100; // @[RegisterRouter.scala:87:24] assign out_woready_1_822 = _out_wofireMux_T_1100; // @[RegisterRouter.scala:87:24] assign out_woready_1_823 = _out_wofireMux_T_1100; // @[RegisterRouter.scala:87:24] assign out_woready_1_824 = _out_wofireMux_T_1100; // @[RegisterRouter.scala:87:24] assign out_woready_1_825 = _out_wofireMux_T_1100; // @[RegisterRouter.scala:87:24] assign out_woready_1_826 = _out_wofireMux_T_1100; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1101 = ~_out_T_1813; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1103 = _out_wofireMux_T_262 & out_backSel_210; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1104 = _out_wofireMux_T_1103 & _out_T_1879; // @[RegisterRouter.scala:87:24] assign out_woready_1_1083 = _out_wofireMux_T_1104; // @[RegisterRouter.scala:87:24] assign out_woready_1_1084 = _out_wofireMux_T_1104; // @[RegisterRouter.scala:87:24] assign out_woready_1_1085 = _out_wofireMux_T_1104; // @[RegisterRouter.scala:87:24] assign out_woready_1_1086 = _out_wofireMux_T_1104; // @[RegisterRouter.scala:87:24] assign out_woready_1_1087 = _out_wofireMux_T_1104; // @[RegisterRouter.scala:87:24] assign out_woready_1_1088 = _out_wofireMux_T_1104; // @[RegisterRouter.scala:87:24] assign out_woready_1_1089 = _out_wofireMux_T_1104; // @[RegisterRouter.scala:87:24] assign out_woready_1_1090 = _out_wofireMux_T_1104; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1105 = ~_out_T_1879; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1107 = _out_wofireMux_T_262 & out_backSel_211; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1108 = _out_wofireMux_T_1107 & _out_T_1653; // @[RegisterRouter.scala:87:24] assign out_woready_1_208 = _out_wofireMux_T_1108; // @[RegisterRouter.scala:87:24] assign out_woready_1_209 = _out_wofireMux_T_1108; // @[RegisterRouter.scala:87:24] assign out_woready_1_210 = _out_wofireMux_T_1108; // @[RegisterRouter.scala:87:24] assign out_woready_1_211 = _out_wofireMux_T_1108; // @[RegisterRouter.scala:87:24] assign out_woready_1_212 = _out_wofireMux_T_1108; // @[RegisterRouter.scala:87:24] assign out_woready_1_213 = _out_wofireMux_T_1108; // @[RegisterRouter.scala:87:24] assign out_woready_1_214 = _out_wofireMux_T_1108; // @[RegisterRouter.scala:87:24] assign out_woready_1_215 = _out_wofireMux_T_1108; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1109 = ~_out_T_1653; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1111 = _out_wofireMux_T_262 & out_backSel_212; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1112 = _out_wofireMux_T_1111 & _out_T_1711; // @[RegisterRouter.scala:87:24] assign out_woready_1_434 = _out_wofireMux_T_1112; // @[RegisterRouter.scala:87:24] assign out_woready_1_435 = _out_wofireMux_T_1112; // @[RegisterRouter.scala:87:24] assign out_woready_1_436 = _out_wofireMux_T_1112; // @[RegisterRouter.scala:87:24] assign out_woready_1_437 = _out_wofireMux_T_1112; // @[RegisterRouter.scala:87:24] assign out_woready_1_438 = _out_wofireMux_T_1112; // @[RegisterRouter.scala:87:24] assign out_woready_1_439 = _out_wofireMux_T_1112; // @[RegisterRouter.scala:87:24] assign out_woready_1_440 = _out_wofireMux_T_1112; // @[RegisterRouter.scala:87:24] assign out_woready_1_441 = _out_wofireMux_T_1112; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1113 = ~_out_T_1711; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1115 = _out_wofireMux_T_262 & out_backSel_213; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1116 = _out_wofireMux_T_1115 & _out_T_1785; // @[RegisterRouter.scala:87:24] assign out_woready_1_707 = _out_wofireMux_T_1116; // @[RegisterRouter.scala:87:24] assign out_woready_1_708 = _out_wofireMux_T_1116; // @[RegisterRouter.scala:87:24] assign out_woready_1_709 = _out_wofireMux_T_1116; // @[RegisterRouter.scala:87:24] assign out_woready_1_710 = _out_wofireMux_T_1116; // @[RegisterRouter.scala:87:24] assign out_woready_1_711 = _out_wofireMux_T_1116; // @[RegisterRouter.scala:87:24] assign out_woready_1_712 = _out_wofireMux_T_1116; // @[RegisterRouter.scala:87:24] assign out_woready_1_713 = _out_wofireMux_T_1116; // @[RegisterRouter.scala:87:24] assign out_woready_1_714 = _out_wofireMux_T_1116; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1117 = ~_out_T_1785; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1119 = _out_wofireMux_T_262 & out_backSel_214; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1120 = _out_wofireMux_T_1119 & _out_T_1861; // @[RegisterRouter.scala:87:24] assign out_woready_1_1011 = _out_wofireMux_T_1120; // @[RegisterRouter.scala:87:24] assign out_woready_1_1012 = _out_wofireMux_T_1120; // @[RegisterRouter.scala:87:24] assign out_woready_1_1013 = _out_wofireMux_T_1120; // @[RegisterRouter.scala:87:24] assign out_woready_1_1014 = _out_wofireMux_T_1120; // @[RegisterRouter.scala:87:24] assign out_woready_1_1015 = _out_wofireMux_T_1120; // @[RegisterRouter.scala:87:24] assign out_woready_1_1016 = _out_wofireMux_T_1120; // @[RegisterRouter.scala:87:24] assign out_woready_1_1017 = _out_wofireMux_T_1120; // @[RegisterRouter.scala:87:24] assign out_woready_1_1018 = _out_wofireMux_T_1120; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1121 = ~_out_T_1861; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1123 = _out_wofireMux_T_262 & out_backSel_215; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1124 = _out_wofireMux_T_1123 & _out_T_1901; // @[RegisterRouter.scala:87:24] assign out_woready_1_1171 = _out_wofireMux_T_1124; // @[RegisterRouter.scala:87:24] assign out_woready_1_1172 = _out_wofireMux_T_1124; // @[RegisterRouter.scala:87:24] assign out_woready_1_1173 = _out_wofireMux_T_1124; // @[RegisterRouter.scala:87:24] assign out_woready_1_1174 = _out_wofireMux_T_1124; // @[RegisterRouter.scala:87:24] assign out_woready_1_1175 = _out_wofireMux_T_1124; // @[RegisterRouter.scala:87:24] assign out_woready_1_1176 = _out_wofireMux_T_1124; // @[RegisterRouter.scala:87:24] assign out_woready_1_1177 = _out_wofireMux_T_1124; // @[RegisterRouter.scala:87:24] assign out_woready_1_1178 = _out_wofireMux_T_1124; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1125 = ~_out_T_1901; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1127 = _out_wofireMux_T_262 & out_backSel_216; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1128 = _out_wofireMux_T_1127 & _out_T_1643; // @[RegisterRouter.scala:87:24] assign out_woready_1_168 = _out_wofireMux_T_1128; // @[RegisterRouter.scala:87:24] assign out_woready_1_169 = _out_wofireMux_T_1128; // @[RegisterRouter.scala:87:24] assign out_woready_1_170 = _out_wofireMux_T_1128; // @[RegisterRouter.scala:87:24] assign out_woready_1_171 = _out_wofireMux_T_1128; // @[RegisterRouter.scala:87:24] assign out_woready_1_172 = _out_wofireMux_T_1128; // @[RegisterRouter.scala:87:24] assign out_woready_1_173 = _out_wofireMux_T_1128; // @[RegisterRouter.scala:87:24] assign out_woready_1_174 = _out_wofireMux_T_1128; // @[RegisterRouter.scala:87:24] assign out_woready_1_175 = _out_wofireMux_T_1128; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1129 = ~_out_T_1643; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1131 = _out_wofireMux_T_262 & out_backSel_217; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1132 = _out_wofireMux_T_1131 & _out_T_1611; // @[RegisterRouter.scala:87:24] assign out_woready_1_40 = _out_wofireMux_T_1132; // @[RegisterRouter.scala:87:24] assign out_woready_1_41 = _out_wofireMux_T_1132; // @[RegisterRouter.scala:87:24] assign out_woready_1_42 = _out_wofireMux_T_1132; // @[RegisterRouter.scala:87:24] assign out_woready_1_43 = _out_wofireMux_T_1132; // @[RegisterRouter.scala:87:24] assign out_woready_1_44 = _out_wofireMux_T_1132; // @[RegisterRouter.scala:87:24] assign out_woready_1_45 = _out_wofireMux_T_1132; // @[RegisterRouter.scala:87:24] assign out_woready_1_46 = _out_wofireMux_T_1132; // @[RegisterRouter.scala:87:24] assign out_woready_1_47 = _out_wofireMux_T_1132; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1133 = ~_out_T_1611; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1135 = _out_wofireMux_T_262 & out_backSel_218; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1136 = _out_wofireMux_T_1135 & _out_T_1839; // @[RegisterRouter.scala:87:24] assign out_woready_1_923 = _out_wofireMux_T_1136; // @[RegisterRouter.scala:87:24] assign out_woready_1_924 = _out_wofireMux_T_1136; // @[RegisterRouter.scala:87:24] assign out_woready_1_925 = _out_wofireMux_T_1136; // @[RegisterRouter.scala:87:24] assign out_woready_1_926 = _out_wofireMux_T_1136; // @[RegisterRouter.scala:87:24] assign out_woready_1_927 = _out_wofireMux_T_1136; // @[RegisterRouter.scala:87:24] assign out_woready_1_928 = _out_wofireMux_T_1136; // @[RegisterRouter.scala:87:24] assign out_woready_1_929 = _out_wofireMux_T_1136; // @[RegisterRouter.scala:87:24] assign out_woready_1_930 = _out_wofireMux_T_1136; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1137 = ~_out_T_1839; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1139 = _out_wofireMux_T_262 & out_backSel_219; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1140 = _out_wofireMux_T_1139 & _out_T_1773; // @[RegisterRouter.scala:87:24] assign out_woready_1_665 = _out_wofireMux_T_1140; // @[RegisterRouter.scala:87:24] assign out_woready_1_666 = _out_wofireMux_T_1140; // @[RegisterRouter.scala:87:24] assign out_woready_1_667 = _out_wofireMux_T_1140; // @[RegisterRouter.scala:87:24] assign out_woready_1_668 = _out_wofireMux_T_1140; // @[RegisterRouter.scala:87:24] assign out_woready_1_669 = _out_wofireMux_T_1140; // @[RegisterRouter.scala:87:24] assign out_woready_1_670 = _out_wofireMux_T_1140; // @[RegisterRouter.scala:87:24] assign out_woready_1_671 = _out_wofireMux_T_1140; // @[RegisterRouter.scala:87:24] assign out_woready_1_672 = _out_wofireMux_T_1140; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1141 = ~_out_T_1773; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1143 = _out_wofireMux_T_262 & out_backSel_220; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1144 = _out_wofireMux_T_1143 & _out_T_1677; // @[RegisterRouter.scala:87:24] assign out_woready_1_304 = _out_wofireMux_T_1144; // @[RegisterRouter.scala:87:24] assign out_woready_1_305 = _out_wofireMux_T_1144; // @[RegisterRouter.scala:87:24] assign out_woready_1_306 = _out_wofireMux_T_1144; // @[RegisterRouter.scala:87:24] assign out_woready_1_307 = _out_wofireMux_T_1144; // @[RegisterRouter.scala:87:24] assign out_woready_1_308 = _out_wofireMux_T_1144; // @[RegisterRouter.scala:87:24] assign out_woready_1_309 = _out_wofireMux_T_1144; // @[RegisterRouter.scala:87:24] assign out_woready_1_310 = _out_wofireMux_T_1144; // @[RegisterRouter.scala:87:24] assign out_woready_1_311 = _out_wofireMux_T_1144; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1145 = ~_out_T_1677; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1147 = _out_wofireMux_T_262 & out_backSel_221; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1148 = _out_wofireMux_T_1147 & _out_T_1659; // @[RegisterRouter.scala:87:24] assign out_woready_1_232 = _out_wofireMux_T_1148; // @[RegisterRouter.scala:87:24] assign out_woready_1_233 = _out_wofireMux_T_1148; // @[RegisterRouter.scala:87:24] assign out_woready_1_234 = _out_wofireMux_T_1148; // @[RegisterRouter.scala:87:24] assign out_woready_1_235 = _out_wofireMux_T_1148; // @[RegisterRouter.scala:87:24] assign out_woready_1_236 = _out_wofireMux_T_1148; // @[RegisterRouter.scala:87:24] assign out_woready_1_237 = _out_wofireMux_T_1148; // @[RegisterRouter.scala:87:24] assign out_woready_1_238 = _out_wofireMux_T_1148; // @[RegisterRouter.scala:87:24] assign out_woready_1_239 = _out_wofireMux_T_1148; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1149 = ~_out_T_1659; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1151 = _out_wofireMux_T_262 & out_backSel_222; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1152 = _out_wofireMux_T_1151 & _out_T_1903; // @[RegisterRouter.scala:87:24] assign out_woready_1_1179 = _out_wofireMux_T_1152; // @[RegisterRouter.scala:87:24] assign out_woready_1_1180 = _out_wofireMux_T_1152; // @[RegisterRouter.scala:87:24] assign out_woready_1_1181 = _out_wofireMux_T_1152; // @[RegisterRouter.scala:87:24] assign out_woready_1_1182 = _out_wofireMux_T_1152; // @[RegisterRouter.scala:87:24] assign out_woready_1_1183 = _out_wofireMux_T_1152; // @[RegisterRouter.scala:87:24] assign out_woready_1_1184 = _out_wofireMux_T_1152; // @[RegisterRouter.scala:87:24] assign out_woready_1_1185 = _out_wofireMux_T_1152; // @[RegisterRouter.scala:87:24] assign out_woready_1_1186 = _out_wofireMux_T_1152; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1153 = ~_out_T_1903; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1155 = _out_wofireMux_T_262 & out_backSel_223; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1156 = _out_wofireMux_T_1155 & _out_T_1799; // @[RegisterRouter.scala:87:24] assign out_woready_1_763 = _out_wofireMux_T_1156; // @[RegisterRouter.scala:87:24] assign out_woready_1_764 = _out_wofireMux_T_1156; // @[RegisterRouter.scala:87:24] assign out_woready_1_765 = _out_wofireMux_T_1156; // @[RegisterRouter.scala:87:24] assign out_woready_1_766 = _out_wofireMux_T_1156; // @[RegisterRouter.scala:87:24] assign out_woready_1_767 = _out_wofireMux_T_1156; // @[RegisterRouter.scala:87:24] assign out_woready_1_768 = _out_wofireMux_T_1156; // @[RegisterRouter.scala:87:24] assign out_woready_1_769 = _out_wofireMux_T_1156; // @[RegisterRouter.scala:87:24] assign out_woready_1_770 = _out_wofireMux_T_1156; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1157 = ~_out_T_1799; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1159 = _out_wofireMux_T_262 & out_backSel_224; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1160 = _out_wofireMux_T_1159 & _out_T_1697; // @[RegisterRouter.scala:87:24] assign out_woready_1_378 = _out_wofireMux_T_1160; // @[RegisterRouter.scala:87:24] assign out_woready_1_379 = _out_wofireMux_T_1160; // @[RegisterRouter.scala:87:24] assign out_woready_1_380 = _out_wofireMux_T_1160; // @[RegisterRouter.scala:87:24] assign out_woready_1_381 = _out_wofireMux_T_1160; // @[RegisterRouter.scala:87:24] assign out_woready_1_382 = _out_wofireMux_T_1160; // @[RegisterRouter.scala:87:24] assign out_woready_1_383 = _out_wofireMux_T_1160; // @[RegisterRouter.scala:87:24] assign out_woready_1_384 = _out_wofireMux_T_1160; // @[RegisterRouter.scala:87:24] assign out_woready_1_385 = _out_wofireMux_T_1160; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1161 = ~_out_T_1697; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1163 = _out_wofireMux_T_262 & out_backSel_225; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1164 = _out_wofireMux_T_1163 & _out_T_1707; // @[RegisterRouter.scala:87:24] assign out_woready_1_418 = _out_wofireMux_T_1164; // @[RegisterRouter.scala:87:24] assign out_woready_1_419 = _out_wofireMux_T_1164; // @[RegisterRouter.scala:87:24] assign out_woready_1_420 = _out_wofireMux_T_1164; // @[RegisterRouter.scala:87:24] assign out_woready_1_421 = _out_wofireMux_T_1164; // @[RegisterRouter.scala:87:24] assign out_woready_1_422 = _out_wofireMux_T_1164; // @[RegisterRouter.scala:87:24] assign out_woready_1_423 = _out_wofireMux_T_1164; // @[RegisterRouter.scala:87:24] assign out_woready_1_424 = _out_wofireMux_T_1164; // @[RegisterRouter.scala:87:24] assign out_woready_1_425 = _out_wofireMux_T_1164; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1165 = ~_out_T_1707; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1167 = _out_wofireMux_T_262 & out_backSel_226; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1168 = _out_wofireMux_T_1167 & _out_T_1803; // @[RegisterRouter.scala:87:24] assign out_woready_1_779 = _out_wofireMux_T_1168; // @[RegisterRouter.scala:87:24] assign out_woready_1_780 = _out_wofireMux_T_1168; // @[RegisterRouter.scala:87:24] assign out_woready_1_781 = _out_wofireMux_T_1168; // @[RegisterRouter.scala:87:24] assign out_woready_1_782 = _out_wofireMux_T_1168; // @[RegisterRouter.scala:87:24] assign out_woready_1_783 = _out_wofireMux_T_1168; // @[RegisterRouter.scala:87:24] assign out_woready_1_784 = _out_wofireMux_T_1168; // @[RegisterRouter.scala:87:24] assign out_woready_1_785 = _out_wofireMux_T_1168; // @[RegisterRouter.scala:87:24] assign out_woready_1_786 = _out_wofireMux_T_1168; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1169 = ~_out_T_1803; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1171 = _out_wofireMux_T_262 & out_backSel_227; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1172 = _out_wofireMux_T_1171 & _out_T_1909; // @[RegisterRouter.scala:87:24] assign out_woready_1_1203 = _out_wofireMux_T_1172; // @[RegisterRouter.scala:87:24] assign out_woready_1_1204 = _out_wofireMux_T_1172; // @[RegisterRouter.scala:87:24] assign out_woready_1_1205 = _out_wofireMux_T_1172; // @[RegisterRouter.scala:87:24] assign out_woready_1_1206 = _out_wofireMux_T_1172; // @[RegisterRouter.scala:87:24] assign out_woready_1_1207 = _out_wofireMux_T_1172; // @[RegisterRouter.scala:87:24] assign out_woready_1_1208 = _out_wofireMux_T_1172; // @[RegisterRouter.scala:87:24] assign out_woready_1_1209 = _out_wofireMux_T_1172; // @[RegisterRouter.scala:87:24] assign out_woready_1_1210 = _out_wofireMux_T_1172; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1173 = ~_out_T_1909; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1175 = _out_wofireMux_T_262 & out_backSel_228; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1176 = _out_wofireMux_T_1175 & _out_T_1639; // @[RegisterRouter.scala:87:24] assign out_woready_1_152 = _out_wofireMux_T_1176; // @[RegisterRouter.scala:87:24] assign out_woready_1_153 = _out_wofireMux_T_1176; // @[RegisterRouter.scala:87:24] assign out_woready_1_154 = _out_wofireMux_T_1176; // @[RegisterRouter.scala:87:24] assign out_woready_1_155 = _out_wofireMux_T_1176; // @[RegisterRouter.scala:87:24] assign out_woready_1_156 = _out_wofireMux_T_1176; // @[RegisterRouter.scala:87:24] assign out_woready_1_157 = _out_wofireMux_T_1176; // @[RegisterRouter.scala:87:24] assign out_woready_1_158 = _out_wofireMux_T_1176; // @[RegisterRouter.scala:87:24] assign out_woready_1_159 = _out_wofireMux_T_1176; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1177 = ~_out_T_1639; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1179 = _out_wofireMux_T_262 & out_backSel_229; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1180 = _out_wofireMux_T_1179 & _out_T_1691; // @[RegisterRouter.scala:87:24] assign out_woready_1_354 = _out_wofireMux_T_1180; // @[RegisterRouter.scala:87:24] assign out_woready_1_355 = _out_wofireMux_T_1180; // @[RegisterRouter.scala:87:24] assign out_woready_1_356 = _out_wofireMux_T_1180; // @[RegisterRouter.scala:87:24] assign out_woready_1_357 = _out_wofireMux_T_1180; // @[RegisterRouter.scala:87:24] assign out_woready_1_358 = _out_wofireMux_T_1180; // @[RegisterRouter.scala:87:24] assign out_woready_1_359 = _out_wofireMux_T_1180; // @[RegisterRouter.scala:87:24] assign out_woready_1_360 = _out_wofireMux_T_1180; // @[RegisterRouter.scala:87:24] assign out_woready_1_361 = _out_wofireMux_T_1180; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1181 = ~_out_T_1691; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1183 = _out_wofireMux_T_262 & out_backSel_230; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1184 = _out_wofireMux_T_1183 & _out_T_1775; // @[RegisterRouter.scala:87:24] assign out_woready_1_673 = _out_wofireMux_T_1184; // @[RegisterRouter.scala:87:24] assign out_woready_1_674 = _out_wofireMux_T_1184; // @[RegisterRouter.scala:87:24] assign out_woready_1_675 = _out_wofireMux_T_1184; // @[RegisterRouter.scala:87:24] assign out_woready_1_676 = _out_wofireMux_T_1184; // @[RegisterRouter.scala:87:24] assign out_woready_1_677 = _out_wofireMux_T_1184; // @[RegisterRouter.scala:87:24] assign out_woready_1_678 = _out_wofireMux_T_1184; // @[RegisterRouter.scala:87:24] assign out_woready_1_679 = _out_wofireMux_T_1184; // @[RegisterRouter.scala:87:24] assign out_woready_1_680 = _out_wofireMux_T_1184; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1185 = ~_out_T_1775; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1187 = _out_wofireMux_T_262 & out_backSel_231; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1188 = _out_wofireMux_T_1187 & _out_T_1845; // @[RegisterRouter.scala:87:24] assign out_woready_1_947 = _out_wofireMux_T_1188; // @[RegisterRouter.scala:87:24] assign out_woready_1_948 = _out_wofireMux_T_1188; // @[RegisterRouter.scala:87:24] assign out_woready_1_949 = _out_wofireMux_T_1188; // @[RegisterRouter.scala:87:24] assign out_woready_1_950 = _out_wofireMux_T_1188; // @[RegisterRouter.scala:87:24] assign out_woready_1_951 = _out_wofireMux_T_1188; // @[RegisterRouter.scala:87:24] assign out_woready_1_952 = _out_wofireMux_T_1188; // @[RegisterRouter.scala:87:24] assign out_woready_1_953 = _out_wofireMux_T_1188; // @[RegisterRouter.scala:87:24] assign out_woready_1_954 = _out_wofireMux_T_1188; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1189 = ~_out_T_1845; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1191 = _out_wofireMux_T_262 & out_backSel_232; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1192 = _out_wofireMux_T_1191 & _out_T_1905; // @[RegisterRouter.scala:87:24] assign out_woready_1_1187 = _out_wofireMux_T_1192; // @[RegisterRouter.scala:87:24] assign out_woready_1_1188 = _out_wofireMux_T_1192; // @[RegisterRouter.scala:87:24] assign out_woready_1_1189 = _out_wofireMux_T_1192; // @[RegisterRouter.scala:87:24] assign out_woready_1_1190 = _out_wofireMux_T_1192; // @[RegisterRouter.scala:87:24] assign out_woready_1_1191 = _out_wofireMux_T_1192; // @[RegisterRouter.scala:87:24] assign out_woready_1_1192 = _out_wofireMux_T_1192; // @[RegisterRouter.scala:87:24] assign out_woready_1_1193 = _out_wofireMux_T_1192; // @[RegisterRouter.scala:87:24] assign out_woready_1_1194 = _out_wofireMux_T_1192; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1193 = ~_out_T_1905; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1195 = _out_wofireMux_T_262 & out_backSel_233; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1196 = _out_wofireMux_T_1195 & _out_T_1671; // @[RegisterRouter.scala:87:24] assign out_woready_1_280 = _out_wofireMux_T_1196; // @[RegisterRouter.scala:87:24] assign out_woready_1_281 = _out_wofireMux_T_1196; // @[RegisterRouter.scala:87:24] assign out_woready_1_282 = _out_wofireMux_T_1196; // @[RegisterRouter.scala:87:24] assign out_woready_1_283 = _out_wofireMux_T_1196; // @[RegisterRouter.scala:87:24] assign out_woready_1_284 = _out_wofireMux_T_1196; // @[RegisterRouter.scala:87:24] assign out_woready_1_285 = _out_wofireMux_T_1196; // @[RegisterRouter.scala:87:24] assign out_woready_1_286 = _out_wofireMux_T_1196; // @[RegisterRouter.scala:87:24] assign out_woready_1_287 = _out_wofireMux_T_1196; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1197 = ~_out_T_1671; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1199 = _out_wofireMux_T_262 & out_backSel_234; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1200 = _out_wofireMux_T_1199 & _out_T_1605; // @[RegisterRouter.scala:87:24] assign out_woready_1_16 = _out_wofireMux_T_1200; // @[RegisterRouter.scala:87:24] assign out_woready_1_17 = _out_wofireMux_T_1200; // @[RegisterRouter.scala:87:24] assign out_woready_1_18 = _out_wofireMux_T_1200; // @[RegisterRouter.scala:87:24] assign out_woready_1_19 = _out_wofireMux_T_1200; // @[RegisterRouter.scala:87:24] assign out_woready_1_20 = _out_wofireMux_T_1200; // @[RegisterRouter.scala:87:24] assign out_woready_1_21 = _out_wofireMux_T_1200; // @[RegisterRouter.scala:87:24] assign out_woready_1_22 = _out_wofireMux_T_1200; // @[RegisterRouter.scala:87:24] assign out_woready_1_23 = _out_wofireMux_T_1200; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1201 = ~_out_T_1605; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1203 = _out_wofireMux_T_262 & out_backSel_235; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1204 = _out_wofireMux_T_1203 & _out_T_1863; // @[RegisterRouter.scala:87:24] assign out_woready_1_1019 = _out_wofireMux_T_1204; // @[RegisterRouter.scala:87:24] assign out_woready_1_1020 = _out_wofireMux_T_1204; // @[RegisterRouter.scala:87:24] assign out_woready_1_1021 = _out_wofireMux_T_1204; // @[RegisterRouter.scala:87:24] assign out_woready_1_1022 = _out_wofireMux_T_1204; // @[RegisterRouter.scala:87:24] assign out_woready_1_1023 = _out_wofireMux_T_1204; // @[RegisterRouter.scala:87:24] assign out_woready_1_1024 = _out_wofireMux_T_1204; // @[RegisterRouter.scala:87:24] assign out_woready_1_1025 = _out_wofireMux_T_1204; // @[RegisterRouter.scala:87:24] assign out_woready_1_1026 = _out_wofireMux_T_1204; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1205 = ~_out_T_1863; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1207 = _out_wofireMux_T_262 & out_backSel_236; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1208 = _out_wofireMux_T_1207 & _out_T_1761; // @[RegisterRouter.scala:87:24] assign out_woready_1_617 = _out_wofireMux_T_1208; // @[RegisterRouter.scala:87:24] assign out_woready_1_618 = _out_wofireMux_T_1208; // @[RegisterRouter.scala:87:24] assign out_woready_1_619 = _out_wofireMux_T_1208; // @[RegisterRouter.scala:87:24] assign out_woready_1_620 = _out_wofireMux_T_1208; // @[RegisterRouter.scala:87:24] assign out_woready_1_621 = _out_wofireMux_T_1208; // @[RegisterRouter.scala:87:24] assign out_woready_1_622 = _out_wofireMux_T_1208; // @[RegisterRouter.scala:87:24] assign out_woready_1_623 = _out_wofireMux_T_1208; // @[RegisterRouter.scala:87:24] assign out_woready_1_624 = _out_wofireMux_T_1208; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1209 = ~_out_T_1761; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1211 = _out_wofireMux_T_262 & out_backSel_237; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1212 = _out_wofireMux_T_1211 & _out_T_1731; // @[RegisterRouter.scala:87:24] assign out_woready_1_503 = _out_wofireMux_T_1212; // @[RegisterRouter.scala:87:24] assign out_woready_1_504 = _out_wofireMux_T_1212; // @[RegisterRouter.scala:87:24] assign out_woready_1_505 = _out_wofireMux_T_1212; // @[RegisterRouter.scala:87:24] assign out_woready_1_506 = _out_wofireMux_T_1212; // @[RegisterRouter.scala:87:24] assign out_woready_1_507 = _out_wofireMux_T_1212; // @[RegisterRouter.scala:87:24] assign out_woready_1_508 = _out_wofireMux_T_1212; // @[RegisterRouter.scala:87:24] assign out_woready_1_509 = _out_wofireMux_T_1212; // @[RegisterRouter.scala:87:24] assign out_woready_1_510 = _out_wofireMux_T_1212; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1213 = ~_out_T_1731; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1215 = _out_wofireMux_T_262 & out_backSel_238; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1216 = _out_wofireMux_T_1215 & _out_T_1651; // @[RegisterRouter.scala:87:24] assign out_woready_1_200 = _out_wofireMux_T_1216; // @[RegisterRouter.scala:87:24] assign out_woready_1_201 = _out_wofireMux_T_1216; // @[RegisterRouter.scala:87:24] assign out_woready_1_202 = _out_wofireMux_T_1216; // @[RegisterRouter.scala:87:24] assign out_woready_1_203 = _out_wofireMux_T_1216; // @[RegisterRouter.scala:87:24] assign out_woready_1_204 = _out_wofireMux_T_1216; // @[RegisterRouter.scala:87:24] assign out_woready_1_205 = _out_wofireMux_T_1216; // @[RegisterRouter.scala:87:24] assign out_woready_1_206 = _out_wofireMux_T_1216; // @[RegisterRouter.scala:87:24] assign out_woready_1_207 = _out_wofireMux_T_1216; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1217 = ~_out_T_1651; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1219 = _out_wofireMux_T_262 & out_backSel_239; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1220 = _out_wofireMux_T_1219 & _out_T_1887; // @[RegisterRouter.scala:87:24] assign out_woready_1_1115 = _out_wofireMux_T_1220; // @[RegisterRouter.scala:87:24] assign out_woready_1_1116 = _out_wofireMux_T_1220; // @[RegisterRouter.scala:87:24] assign out_woready_1_1117 = _out_wofireMux_T_1220; // @[RegisterRouter.scala:87:24] assign out_woready_1_1118 = _out_wofireMux_T_1220; // @[RegisterRouter.scala:87:24] assign out_woready_1_1119 = _out_wofireMux_T_1220; // @[RegisterRouter.scala:87:24] assign out_woready_1_1120 = _out_wofireMux_T_1220; // @[RegisterRouter.scala:87:24] assign out_woready_1_1121 = _out_wofireMux_T_1220; // @[RegisterRouter.scala:87:24] assign out_woready_1_1122 = _out_wofireMux_T_1220; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1221 = ~_out_T_1887; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1223 = _out_wofireMux_T_262 & out_backSel_240; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1224 = _out_wofireMux_T_1223 & _out_T_1793; // @[RegisterRouter.scala:87:24] assign out_woready_1_739 = _out_wofireMux_T_1224; // @[RegisterRouter.scala:87:24] assign out_woready_1_740 = _out_wofireMux_T_1224; // @[RegisterRouter.scala:87:24] assign out_woready_1_741 = _out_wofireMux_T_1224; // @[RegisterRouter.scala:87:24] assign out_woready_1_742 = _out_wofireMux_T_1224; // @[RegisterRouter.scala:87:24] assign out_woready_1_743 = _out_wofireMux_T_1224; // @[RegisterRouter.scala:87:24] assign out_woready_1_744 = _out_wofireMux_T_1224; // @[RegisterRouter.scala:87:24] assign out_woready_1_745 = _out_wofireMux_T_1224; // @[RegisterRouter.scala:87:24] assign out_woready_1_746 = _out_wofireMux_T_1224; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1225 = ~_out_T_1793; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1227 = _out_wofireMux_T_262 & out_backSel_241; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1228 = _out_wofireMux_T_1227 & _out_T_1805; // @[RegisterRouter.scala:87:24] assign out_woready_1_787 = _out_wofireMux_T_1228; // @[RegisterRouter.scala:87:24] assign out_woready_1_788 = _out_wofireMux_T_1228; // @[RegisterRouter.scala:87:24] assign out_woready_1_789 = _out_wofireMux_T_1228; // @[RegisterRouter.scala:87:24] assign out_woready_1_790 = _out_wofireMux_T_1228; // @[RegisterRouter.scala:87:24] assign out_woready_1_791 = _out_wofireMux_T_1228; // @[RegisterRouter.scala:87:24] assign out_woready_1_792 = _out_wofireMux_T_1228; // @[RegisterRouter.scala:87:24] assign out_woready_1_793 = _out_wofireMux_T_1228; // @[RegisterRouter.scala:87:24] assign out_woready_1_794 = _out_wofireMux_T_1228; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1229 = ~_out_T_1805; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1231 = _out_wofireMux_T_262 & out_backSel_242; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1232 = _out_wofireMux_T_1231 & _out_T_1889; // @[RegisterRouter.scala:87:24] assign out_woready_1_1123 = _out_wofireMux_T_1232; // @[RegisterRouter.scala:87:24] assign out_woready_1_1124 = _out_wofireMux_T_1232; // @[RegisterRouter.scala:87:24] assign out_woready_1_1125 = _out_wofireMux_T_1232; // @[RegisterRouter.scala:87:24] assign out_woready_1_1126 = _out_wofireMux_T_1232; // @[RegisterRouter.scala:87:24] assign out_woready_1_1127 = _out_wofireMux_T_1232; // @[RegisterRouter.scala:87:24] assign out_woready_1_1128 = _out_wofireMux_T_1232; // @[RegisterRouter.scala:87:24] assign out_woready_1_1129 = _out_wofireMux_T_1232; // @[RegisterRouter.scala:87:24] assign out_woready_1_1130 = _out_wofireMux_T_1232; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1233 = ~_out_T_1889; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1235 = _out_wofireMux_T_262 & out_backSel_243; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1236 = _out_wofireMux_T_1235 & _out_T_1665; // @[RegisterRouter.scala:87:24] assign out_woready_1_256 = _out_wofireMux_T_1236; // @[RegisterRouter.scala:87:24] assign out_woready_1_257 = _out_wofireMux_T_1236; // @[RegisterRouter.scala:87:24] assign out_woready_1_258 = _out_wofireMux_T_1236; // @[RegisterRouter.scala:87:24] assign out_woready_1_259 = _out_wofireMux_T_1236; // @[RegisterRouter.scala:87:24] assign out_woready_1_260 = _out_wofireMux_T_1236; // @[RegisterRouter.scala:87:24] assign out_woready_1_261 = _out_wofireMux_T_1236; // @[RegisterRouter.scala:87:24] assign out_woready_1_262 = _out_wofireMux_T_1236; // @[RegisterRouter.scala:87:24] assign out_woready_1_263 = _out_wofireMux_T_1236; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1237 = ~_out_T_1665; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1239 = _out_wofireMux_T_262 & out_backSel_244; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1240 = _out_wofireMux_T_1239 & _out_T_1735; // @[RegisterRouter.scala:87:24] assign out_woready_1_519 = _out_wofireMux_T_1240; // @[RegisterRouter.scala:87:24] assign out_woready_1_520 = _out_wofireMux_T_1240; // @[RegisterRouter.scala:87:24] assign out_woready_1_521 = _out_wofireMux_T_1240; // @[RegisterRouter.scala:87:24] assign out_woready_1_522 = _out_wofireMux_T_1240; // @[RegisterRouter.scala:87:24] assign out_woready_1_523 = _out_wofireMux_T_1240; // @[RegisterRouter.scala:87:24] assign out_woready_1_524 = _out_wofireMux_T_1240; // @[RegisterRouter.scala:87:24] assign out_woready_1_525 = _out_wofireMux_T_1240; // @[RegisterRouter.scala:87:24] assign out_woready_1_526 = _out_wofireMux_T_1240; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1241 = ~_out_T_1735; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1243 = _out_wofireMux_T_262 & out_backSel_245; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1244 = _out_wofireMux_T_1243 & _out_T_1777; // @[RegisterRouter.scala:87:24] assign out_woready_1_681 = _out_wofireMux_T_1244; // @[RegisterRouter.scala:87:24] assign out_woready_1_682 = _out_wofireMux_T_1244; // @[RegisterRouter.scala:87:24] assign out_woready_1_683 = _out_wofireMux_T_1244; // @[RegisterRouter.scala:87:24] assign out_woready_1_684 = _out_wofireMux_T_1244; // @[RegisterRouter.scala:87:24] assign out_woready_1_685 = _out_wofireMux_T_1244; // @[RegisterRouter.scala:87:24] assign out_woready_1_686 = _out_wofireMux_T_1244; // @[RegisterRouter.scala:87:24] assign out_woready_1_687 = _out_wofireMux_T_1244; // @[RegisterRouter.scala:87:24] assign out_woready_1_688 = _out_wofireMux_T_1244; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1245 = ~_out_T_1777; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1247 = _out_wofireMux_T_262 & out_backSel_246; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1248 = _out_wofireMux_T_1247 & _out_T_1865; // @[RegisterRouter.scala:87:24] assign out_woready_1_1027 = _out_wofireMux_T_1248; // @[RegisterRouter.scala:87:24] assign out_woready_1_1028 = _out_wofireMux_T_1248; // @[RegisterRouter.scala:87:24] assign out_woready_1_1029 = _out_wofireMux_T_1248; // @[RegisterRouter.scala:87:24] assign out_woready_1_1030 = _out_wofireMux_T_1248; // @[RegisterRouter.scala:87:24] assign out_woready_1_1031 = _out_wofireMux_T_1248; // @[RegisterRouter.scala:87:24] assign out_woready_1_1032 = _out_wofireMux_T_1248; // @[RegisterRouter.scala:87:24] assign out_woready_1_1033 = _out_wofireMux_T_1248; // @[RegisterRouter.scala:87:24] assign out_woready_1_1034 = _out_wofireMux_T_1248; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1249 = ~_out_T_1865; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1251 = _out_wofireMux_T_262 & out_backSel_247; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1252 = _out_wofireMux_T_1251 & _out_T_1613; // @[RegisterRouter.scala:87:24] assign out_woready_1_48 = _out_wofireMux_T_1252; // @[RegisterRouter.scala:87:24] assign out_woready_1_49 = _out_wofireMux_T_1252; // @[RegisterRouter.scala:87:24] assign out_woready_1_50 = _out_wofireMux_T_1252; // @[RegisterRouter.scala:87:24] assign out_woready_1_51 = _out_wofireMux_T_1252; // @[RegisterRouter.scala:87:24] assign out_woready_1_52 = _out_wofireMux_T_1252; // @[RegisterRouter.scala:87:24] assign out_woready_1_53 = _out_wofireMux_T_1252; // @[RegisterRouter.scala:87:24] assign out_woready_1_54 = _out_wofireMux_T_1252; // @[RegisterRouter.scala:87:24] assign out_woready_1_55 = _out_wofireMux_T_1252; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1253 = ~_out_T_1613; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1255 = _out_wofireMux_T_262 & out_backSel_248; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1256 = _out_wofireMux_T_1255 & _out_T_1673; // @[RegisterRouter.scala:87:24] assign out_woready_1_288 = _out_wofireMux_T_1256; // @[RegisterRouter.scala:87:24] assign out_woready_1_289 = _out_wofireMux_T_1256; // @[RegisterRouter.scala:87:24] assign out_woready_1_290 = _out_wofireMux_T_1256; // @[RegisterRouter.scala:87:24] assign out_woready_1_291 = _out_wofireMux_T_1256; // @[RegisterRouter.scala:87:24] assign out_woready_1_292 = _out_wofireMux_T_1256; // @[RegisterRouter.scala:87:24] assign out_woready_1_293 = _out_wofireMux_T_1256; // @[RegisterRouter.scala:87:24] assign out_woready_1_294 = _out_wofireMux_T_1256; // @[RegisterRouter.scala:87:24] assign out_woready_1_295 = _out_wofireMux_T_1256; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1257 = ~_out_T_1673; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1259 = _out_wofireMux_T_262 & out_backSel_249; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1260 = _out_wofireMux_T_1259 & _out_T_1603; // @[RegisterRouter.scala:87:24] assign out_woready_1_8 = _out_wofireMux_T_1260; // @[RegisterRouter.scala:87:24] assign out_woready_1_9 = _out_wofireMux_T_1260; // @[RegisterRouter.scala:87:24] assign out_woready_1_10 = _out_wofireMux_T_1260; // @[RegisterRouter.scala:87:24] assign out_woready_1_11 = _out_wofireMux_T_1260; // @[RegisterRouter.scala:87:24] assign out_woready_1_12 = _out_wofireMux_T_1260; // @[RegisterRouter.scala:87:24] assign out_woready_1_13 = _out_wofireMux_T_1260; // @[RegisterRouter.scala:87:24] assign out_woready_1_14 = _out_wofireMux_T_1260; // @[RegisterRouter.scala:87:24] assign out_woready_1_15 = _out_wofireMux_T_1260; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1261 = ~_out_T_1603; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1263 = _out_wofireMux_T_262 & out_backSel_250; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1264 = _out_wofireMux_T_1263 & _out_T_1843; // @[RegisterRouter.scala:87:24] assign out_woready_1_939 = _out_wofireMux_T_1264; // @[RegisterRouter.scala:87:24] assign out_woready_1_940 = _out_wofireMux_T_1264; // @[RegisterRouter.scala:87:24] assign out_woready_1_941 = _out_wofireMux_T_1264; // @[RegisterRouter.scala:87:24] assign out_woready_1_942 = _out_wofireMux_T_1264; // @[RegisterRouter.scala:87:24] assign out_woready_1_943 = _out_wofireMux_T_1264; // @[RegisterRouter.scala:87:24] assign out_woready_1_944 = _out_wofireMux_T_1264; // @[RegisterRouter.scala:87:24] assign out_woready_1_945 = _out_wofireMux_T_1264; // @[RegisterRouter.scala:87:24] assign out_woready_1_946 = _out_wofireMux_T_1264; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1265 = ~_out_T_1843; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1267 = _out_wofireMux_T_262 & out_backSel_251; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1268 = _out_wofireMux_T_1267 & _out_T_1795; // @[RegisterRouter.scala:87:24] assign out_woready_1_747 = _out_wofireMux_T_1268; // @[RegisterRouter.scala:87:24] assign out_woready_1_748 = _out_wofireMux_T_1268; // @[RegisterRouter.scala:87:24] assign out_woready_1_749 = _out_wofireMux_T_1268; // @[RegisterRouter.scala:87:24] assign out_woready_1_750 = _out_wofireMux_T_1268; // @[RegisterRouter.scala:87:24] assign out_woready_1_751 = _out_wofireMux_T_1268; // @[RegisterRouter.scala:87:24] assign out_woready_1_752 = _out_wofireMux_T_1268; // @[RegisterRouter.scala:87:24] assign out_woready_1_753 = _out_wofireMux_T_1268; // @[RegisterRouter.scala:87:24] assign out_woready_1_754 = _out_wofireMux_T_1268; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1269 = ~_out_T_1795; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1271 = _out_wofireMux_T_262 & out_backSel_252; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1272 = _out_wofireMux_T_1271 & _out_T_1693; // @[RegisterRouter.scala:87:24] assign out_woready_1_362 = _out_wofireMux_T_1272; // @[RegisterRouter.scala:87:24] assign out_woready_1_363 = _out_wofireMux_T_1272; // @[RegisterRouter.scala:87:24] assign out_woready_1_364 = _out_wofireMux_T_1272; // @[RegisterRouter.scala:87:24] assign out_woready_1_365 = _out_wofireMux_T_1272; // @[RegisterRouter.scala:87:24] assign out_woready_1_366 = _out_wofireMux_T_1272; // @[RegisterRouter.scala:87:24] assign out_woready_1_367 = _out_wofireMux_T_1272; // @[RegisterRouter.scala:87:24] assign out_woready_1_368 = _out_wofireMux_T_1272; // @[RegisterRouter.scala:87:24] assign out_woready_1_369 = _out_wofireMux_T_1272; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1273 = ~_out_T_1693; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1275 = _out_wofireMux_T_262 & out_backSel_253; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1276 = _out_wofireMux_T_1275 & _out_T_1655; // @[RegisterRouter.scala:87:24] assign out_woready_1_216 = _out_wofireMux_T_1276; // @[RegisterRouter.scala:87:24] assign out_woready_1_217 = _out_wofireMux_T_1276; // @[RegisterRouter.scala:87:24] assign out_woready_1_218 = _out_wofireMux_T_1276; // @[RegisterRouter.scala:87:24] assign out_woready_1_219 = _out_wofireMux_T_1276; // @[RegisterRouter.scala:87:24] assign out_woready_1_220 = _out_wofireMux_T_1276; // @[RegisterRouter.scala:87:24] assign out_woready_1_221 = _out_wofireMux_T_1276; // @[RegisterRouter.scala:87:24] assign out_woready_1_222 = _out_wofireMux_T_1276; // @[RegisterRouter.scala:87:24] assign out_woready_1_223 = _out_wofireMux_T_1276; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1277 = ~_out_T_1655; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1279 = _out_wofireMux_T_262 & out_backSel_254; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1280 = _out_wofireMux_T_1279 & _out_T_1907; // @[RegisterRouter.scala:87:24] assign out_woready_1_1195 = _out_wofireMux_T_1280; // @[RegisterRouter.scala:87:24] assign out_woready_1_1196 = _out_wofireMux_T_1280; // @[RegisterRouter.scala:87:24] assign out_woready_1_1197 = _out_wofireMux_T_1280; // @[RegisterRouter.scala:87:24] assign out_woready_1_1198 = _out_wofireMux_T_1280; // @[RegisterRouter.scala:87:24] assign out_woready_1_1199 = _out_wofireMux_T_1280; // @[RegisterRouter.scala:87:24] assign out_woready_1_1200 = _out_wofireMux_T_1280; // @[RegisterRouter.scala:87:24] assign out_woready_1_1201 = _out_wofireMux_T_1280; // @[RegisterRouter.scala:87:24] assign out_woready_1_1202 = _out_wofireMux_T_1280; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1281 = ~_out_T_1907; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1283 = _out_wofireMux_T_262 & out_backSel_255; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1284 = _out_wofireMux_T_1283 & _out_T_1811; // @[RegisterRouter.scala:87:24] assign out_woready_1_811 = _out_wofireMux_T_1284; // @[RegisterRouter.scala:87:24] assign out_woready_1_812 = _out_wofireMux_T_1284; // @[RegisterRouter.scala:87:24] assign out_woready_1_813 = _out_wofireMux_T_1284; // @[RegisterRouter.scala:87:24] assign out_woready_1_814 = _out_wofireMux_T_1284; // @[RegisterRouter.scala:87:24] assign out_woready_1_815 = _out_wofireMux_T_1284; // @[RegisterRouter.scala:87:24] assign out_woready_1_816 = _out_wofireMux_T_1284; // @[RegisterRouter.scala:87:24] assign out_woready_1_817 = _out_wofireMux_T_1284; // @[RegisterRouter.scala:87:24] assign out_woready_1_818 = _out_wofireMux_T_1284; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1285 = ~_out_T_1811; // @[RegisterRouter.scala:87:24] assign in_1_ready = _out_in_ready_T_1; // @[RegisterRouter.scala:73:18, :87:24] assign out_front_1_valid = _out_front_valid_T_1; // @[RegisterRouter.scala:87:24] assign out_front_1_ready = _out_front_ready_T_1; // @[RegisterRouter.scala:87:24] assign out_1_valid = _out_out_valid_T_1; // @[RegisterRouter.scala:87:24] wire [255:0] _GEN_24 = {{_out_out_bits_data_WIRE_2_255}, {_out_out_bits_data_WIRE_2_254}, {_out_out_bits_data_WIRE_2_253}, {_out_out_bits_data_WIRE_2_252}, {_out_out_bits_data_WIRE_2_251}, {_out_out_bits_data_WIRE_2_250}, {_out_out_bits_data_WIRE_2_249}, {_out_out_bits_data_WIRE_2_248}, {_out_out_bits_data_WIRE_2_247}, {_out_out_bits_data_WIRE_2_246}, {_out_out_bits_data_WIRE_2_245}, {_out_out_bits_data_WIRE_2_244}, {_out_out_bits_data_WIRE_2_243}, {_out_out_bits_data_WIRE_2_242}, {_out_out_bits_data_WIRE_2_241}, {_out_out_bits_data_WIRE_2_240}, {_out_out_bits_data_WIRE_2_239}, {_out_out_bits_data_WIRE_2_238}, {_out_out_bits_data_WIRE_2_237}, {_out_out_bits_data_WIRE_2_236}, {_out_out_bits_data_WIRE_2_235}, {_out_out_bits_data_WIRE_2_234}, {_out_out_bits_data_WIRE_2_233}, {_out_out_bits_data_WIRE_2_232}, {_out_out_bits_data_WIRE_2_231}, {_out_out_bits_data_WIRE_2_230}, {_out_out_bits_data_WIRE_2_229}, {_out_out_bits_data_WIRE_2_228}, {_out_out_bits_data_WIRE_2_227}, {_out_out_bits_data_WIRE_2_226}, {_out_out_bits_data_WIRE_2_225}, {_out_out_bits_data_WIRE_2_224}, {_out_out_bits_data_WIRE_2_223}, {_out_out_bits_data_WIRE_2_222}, {_out_out_bits_data_WIRE_2_221}, {_out_out_bits_data_WIRE_2_220}, {_out_out_bits_data_WIRE_2_219}, {_out_out_bits_data_WIRE_2_218}, {_out_out_bits_data_WIRE_2_217}, {_out_out_bits_data_WIRE_2_216}, {_out_out_bits_data_WIRE_2_215}, {_out_out_bits_data_WIRE_2_214}, {_out_out_bits_data_WIRE_2_213}, {_out_out_bits_data_WIRE_2_212}, {_out_out_bits_data_WIRE_2_211}, {_out_out_bits_data_WIRE_2_210}, {_out_out_bits_data_WIRE_2_209}, {_out_out_bits_data_WIRE_2_208}, {_out_out_bits_data_WIRE_2_207}, {_out_out_bits_data_WIRE_2_206}, {_out_out_bits_data_WIRE_2_205}, {_out_out_bits_data_WIRE_2_204}, {_out_out_bits_data_WIRE_2_203}, {_out_out_bits_data_WIRE_2_202}, {_out_out_bits_data_WIRE_2_201}, {_out_out_bits_data_WIRE_2_200}, {_out_out_bits_data_WIRE_2_199}, {_out_out_bits_data_WIRE_2_198}, {_out_out_bits_data_WIRE_2_197}, {_out_out_bits_data_WIRE_2_196}, {_out_out_bits_data_WIRE_2_195}, {_out_out_bits_data_WIRE_2_194}, {_out_out_bits_data_WIRE_2_193}, {_out_out_bits_data_WIRE_2_192}, {_out_out_bits_data_WIRE_2_191}, {_out_out_bits_data_WIRE_2_190}, {_out_out_bits_data_WIRE_2_189}, {_out_out_bits_data_WIRE_2_188}, {_out_out_bits_data_WIRE_2_187}, {_out_out_bits_data_WIRE_2_186}, {_out_out_bits_data_WIRE_2_185}, {_out_out_bits_data_WIRE_2_184}, {_out_out_bits_data_WIRE_2_183}, {_out_out_bits_data_WIRE_2_182}, {_out_out_bits_data_WIRE_2_181}, {_out_out_bits_data_WIRE_2_180}, {_out_out_bits_data_WIRE_2_179}, {_out_out_bits_data_WIRE_2_178}, {_out_out_bits_data_WIRE_2_177}, {_out_out_bits_data_WIRE_2_176}, {_out_out_bits_data_WIRE_2_175}, {_out_out_bits_data_WIRE_2_174}, {_out_out_bits_data_WIRE_2_173}, {_out_out_bits_data_WIRE_2_172}, {_out_out_bits_data_WIRE_2_171}, {_out_out_bits_data_WIRE_2_170}, {_out_out_bits_data_WIRE_2_169}, {_out_out_bits_data_WIRE_2_168}, {_out_out_bits_data_WIRE_2_167}, {_out_out_bits_data_WIRE_2_166}, {_out_out_bits_data_WIRE_2_165}, {_out_out_bits_data_WIRE_2_164}, {_out_out_bits_data_WIRE_2_163}, {_out_out_bits_data_WIRE_2_162}, {_out_out_bits_data_WIRE_2_161}, {_out_out_bits_data_WIRE_2_160}, {_out_out_bits_data_WIRE_2_159}, {_out_out_bits_data_WIRE_2_158}, {_out_out_bits_data_WIRE_2_157}, {_out_out_bits_data_WIRE_2_156}, {_out_out_bits_data_WIRE_2_155}, {_out_out_bits_data_WIRE_2_154}, {_out_out_bits_data_WIRE_2_153}, {_out_out_bits_data_WIRE_2_152}, {_out_out_bits_data_WIRE_2_151}, {_out_out_bits_data_WIRE_2_150}, {_out_out_bits_data_WIRE_2_149}, {_out_out_bits_data_WIRE_2_148}, {_out_out_bits_data_WIRE_2_147}, {_out_out_bits_data_WIRE_2_146}, {_out_out_bits_data_WIRE_2_145}, {_out_out_bits_data_WIRE_2_144}, {_out_out_bits_data_WIRE_2_143}, {_out_out_bits_data_WIRE_2_142}, {_out_out_bits_data_WIRE_2_141}, {_out_out_bits_data_WIRE_2_140}, {_out_out_bits_data_WIRE_2_139}, {_out_out_bits_data_WIRE_2_138}, {_out_out_bits_data_WIRE_2_137}, {_out_out_bits_data_WIRE_2_136}, {_out_out_bits_data_WIRE_2_135}, {_out_out_bits_data_WIRE_2_134}, {_out_out_bits_data_WIRE_2_133}, {_out_out_bits_data_WIRE_2_132}, {_out_out_bits_data_WIRE_2_131}, {_out_out_bits_data_WIRE_2_130}, {_out_out_bits_data_WIRE_2_129}, {_out_out_bits_data_WIRE_2_128}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {_out_out_bits_data_WIRE_2_115}, {_out_out_bits_data_WIRE_2_114}, {_out_out_bits_data_WIRE_2_113}, {_out_out_bits_data_WIRE_2_112}, {_out_out_bits_data_WIRE_2_111}, {_out_out_bits_data_WIRE_2_110}, {_out_out_bits_data_WIRE_2_109}, {_out_out_bits_data_WIRE_2_108}, {_out_out_bits_data_WIRE_2_107}, {_out_out_bits_data_WIRE_2_106}, {_out_out_bits_data_WIRE_2_105}, {_out_out_bits_data_WIRE_2_104}, {_out_out_bits_data_WIRE_2_103}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {_out_out_bits_data_WIRE_2_96}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {_out_out_bits_data_WIRE_2_33}, {_out_out_bits_data_WIRE_2_32}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {_out_out_bits_data_WIRE_2_10}, {_out_out_bits_data_WIRE_2_9}, {_out_out_bits_data_WIRE_2_8}, {_out_out_bits_data_WIRE_2_7}, {_out_out_bits_data_WIRE_2_6}, {_out_out_bits_data_WIRE_2_5}, {_out_out_bits_data_WIRE_2_4}, {_out_out_bits_data_WIRE_2_3}, {_out_out_bits_data_WIRE_2_2}, {_out_out_bits_data_WIRE_2_1}, {_out_out_bits_data_WIRE_2_0}}; // @[MuxLiteral.scala:49:{10,48}] wire _out_out_bits_data_T_6 = _GEN_24[out_oindex_1]; // @[MuxLiteral.scala:49:10] wire [255:0][63:0] _GEN_25 = {{_out_out_bits_data_WIRE_3_255}, {_out_out_bits_data_WIRE_3_254}, {_out_out_bits_data_WIRE_3_253}, {_out_out_bits_data_WIRE_3_252}, {_out_out_bits_data_WIRE_3_251}, {_out_out_bits_data_WIRE_3_250}, {_out_out_bits_data_WIRE_3_249}, {_out_out_bits_data_WIRE_3_248}, {_out_out_bits_data_WIRE_3_247}, {_out_out_bits_data_WIRE_3_246}, {_out_out_bits_data_WIRE_3_245}, {_out_out_bits_data_WIRE_3_244}, {_out_out_bits_data_WIRE_3_243}, {_out_out_bits_data_WIRE_3_242}, {_out_out_bits_data_WIRE_3_241}, {_out_out_bits_data_WIRE_3_240}, {_out_out_bits_data_WIRE_3_239}, {_out_out_bits_data_WIRE_3_238}, {_out_out_bits_data_WIRE_3_237}, {_out_out_bits_data_WIRE_3_236}, {_out_out_bits_data_WIRE_3_235}, {_out_out_bits_data_WIRE_3_234}, {_out_out_bits_data_WIRE_3_233}, {_out_out_bits_data_WIRE_3_232}, {_out_out_bits_data_WIRE_3_231}, {_out_out_bits_data_WIRE_3_230}, {_out_out_bits_data_WIRE_3_229}, {_out_out_bits_data_WIRE_3_228}, {_out_out_bits_data_WIRE_3_227}, {_out_out_bits_data_WIRE_3_226}, {_out_out_bits_data_WIRE_3_225}, {_out_out_bits_data_WIRE_3_224}, {_out_out_bits_data_WIRE_3_223}, {_out_out_bits_data_WIRE_3_222}, {_out_out_bits_data_WIRE_3_221}, {_out_out_bits_data_WIRE_3_220}, {_out_out_bits_data_WIRE_3_219}, {_out_out_bits_data_WIRE_3_218}, {_out_out_bits_data_WIRE_3_217}, {_out_out_bits_data_WIRE_3_216}, {_out_out_bits_data_WIRE_3_215}, {_out_out_bits_data_WIRE_3_214}, {_out_out_bits_data_WIRE_3_213}, {_out_out_bits_data_WIRE_3_212}, {_out_out_bits_data_WIRE_3_211}, {_out_out_bits_data_WIRE_3_210}, {_out_out_bits_data_WIRE_3_209}, {_out_out_bits_data_WIRE_3_208}, {_out_out_bits_data_WIRE_3_207}, {_out_out_bits_data_WIRE_3_206}, {_out_out_bits_data_WIRE_3_205}, {_out_out_bits_data_WIRE_3_204}, {_out_out_bits_data_WIRE_3_203}, {_out_out_bits_data_WIRE_3_202}, {_out_out_bits_data_WIRE_3_201}, {_out_out_bits_data_WIRE_3_200}, {_out_out_bits_data_WIRE_3_199}, {_out_out_bits_data_WIRE_3_198}, {_out_out_bits_data_WIRE_3_197}, {_out_out_bits_data_WIRE_3_196}, {_out_out_bits_data_WIRE_3_195}, {_out_out_bits_data_WIRE_3_194}, {_out_out_bits_data_WIRE_3_193}, {_out_out_bits_data_WIRE_3_192}, {_out_out_bits_data_WIRE_3_191}, {_out_out_bits_data_WIRE_3_190}, {_out_out_bits_data_WIRE_3_189}, {_out_out_bits_data_WIRE_3_188}, {_out_out_bits_data_WIRE_3_187}, {_out_out_bits_data_WIRE_3_186}, {_out_out_bits_data_WIRE_3_185}, {_out_out_bits_data_WIRE_3_184}, {_out_out_bits_data_WIRE_3_183}, {_out_out_bits_data_WIRE_3_182}, {_out_out_bits_data_WIRE_3_181}, {_out_out_bits_data_WIRE_3_180}, {_out_out_bits_data_WIRE_3_179}, {_out_out_bits_data_WIRE_3_178}, {_out_out_bits_data_WIRE_3_177}, {_out_out_bits_data_WIRE_3_176}, {_out_out_bits_data_WIRE_3_175}, {_out_out_bits_data_WIRE_3_174}, {_out_out_bits_data_WIRE_3_173}, {_out_out_bits_data_WIRE_3_172}, {_out_out_bits_data_WIRE_3_171}, {_out_out_bits_data_WIRE_3_170}, {_out_out_bits_data_WIRE_3_169}, {_out_out_bits_data_WIRE_3_168}, {_out_out_bits_data_WIRE_3_167}, {_out_out_bits_data_WIRE_3_166}, {_out_out_bits_data_WIRE_3_165}, {_out_out_bits_data_WIRE_3_164}, {_out_out_bits_data_WIRE_3_163}, {_out_out_bits_data_WIRE_3_162}, {_out_out_bits_data_WIRE_3_161}, {_out_out_bits_data_WIRE_3_160}, {_out_out_bits_data_WIRE_3_159}, {_out_out_bits_data_WIRE_3_158}, {_out_out_bits_data_WIRE_3_157}, {_out_out_bits_data_WIRE_3_156}, {_out_out_bits_data_WIRE_3_155}, {_out_out_bits_data_WIRE_3_154}, {_out_out_bits_data_WIRE_3_153}, {_out_out_bits_data_WIRE_3_152}, {_out_out_bits_data_WIRE_3_151}, {_out_out_bits_data_WIRE_3_150}, {_out_out_bits_data_WIRE_3_149}, {_out_out_bits_data_WIRE_3_148}, {_out_out_bits_data_WIRE_3_147}, {_out_out_bits_data_WIRE_3_146}, {_out_out_bits_data_WIRE_3_145}, {_out_out_bits_data_WIRE_3_144}, {_out_out_bits_data_WIRE_3_143}, {_out_out_bits_data_WIRE_3_142}, {_out_out_bits_data_WIRE_3_141}, {_out_out_bits_data_WIRE_3_140}, {_out_out_bits_data_WIRE_3_139}, {_out_out_bits_data_WIRE_3_138}, {_out_out_bits_data_WIRE_3_137}, {_out_out_bits_data_WIRE_3_136}, {_out_out_bits_data_WIRE_3_135}, {_out_out_bits_data_WIRE_3_134}, {_out_out_bits_data_WIRE_3_133}, {_out_out_bits_data_WIRE_3_132}, {_out_out_bits_data_WIRE_3_131}, {_out_out_bits_data_WIRE_3_130}, {_out_out_bits_data_WIRE_3_129}, {_out_out_bits_data_WIRE_3_128}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {_out_out_bits_data_WIRE_3_115}, {_out_out_bits_data_WIRE_3_114}, {_out_out_bits_data_WIRE_3_113}, {_out_out_bits_data_WIRE_3_112}, {_out_out_bits_data_WIRE_3_111}, {_out_out_bits_data_WIRE_3_110}, {_out_out_bits_data_WIRE_3_109}, {_out_out_bits_data_WIRE_3_108}, {_out_out_bits_data_WIRE_3_107}, {_out_out_bits_data_WIRE_3_106}, {_out_out_bits_data_WIRE_3_105}, {_out_out_bits_data_WIRE_3_104}, {_out_out_bits_data_WIRE_3_103}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h380006F}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h100073}, {64'h100026237B200073}, {64'h7B20247310802423}, {64'hF140247330000067}, {64'h100022237B202473}, {64'h4086300147413}, {64'hFE0408E300347413}, {64'h4004440310802023}, {64'hF14024737B241073}, {64'hFF0000F0440006F}, {64'h380006F00C0006F}}; // @[MuxLiteral.scala:49:{10,48}] wire [63:0] _out_out_bits_data_T_8 = _GEN_25[out_oindex_1]; // @[MuxLiteral.scala:49:10] assign _out_out_bits_data_T_9 = _out_out_bits_data_T_6 ? _out_out_bits_data_T_8 : 64'h0; // @[MuxLiteral.scala:49:10] assign out_1_bits_data = _out_out_bits_data_T_9; // @[RegisterRouter.scala:87:24] assign tlNodeIn_d_bits_size = tlNodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign tlNodeIn_d_bits_source = tlNodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign tlNodeIn_d_bits_opcode = {2'h0, _tlNodeIn_d_bits_opcode_T}; // @[RegisterRouter.scala:105:{19,25}] reg [1:0] ctrlStateReg; // @[Debug.scala:1732:27] wire hartHalted = _hartHalted_T; // @[Debug.scala:1734:37] wire [1:0] ctrlStateNxt; // @[Debug.scala:1735:32] assign _abstractCommandBusy_T = |ctrlStateReg; // @[Debug.scala:1732:27, :1740:42] assign abstractCommandBusy = _abstractCommandBusy_T; // @[Debug.scala:1220:39, :1740:42] assign _ABSTRACTCSWrEnLegal_T = ~(|ctrlStateReg); // @[Debug.scala:1732:27, :1740:42, :1742:44] assign ABSTRACTCSWrEnLegal = _ABSTRACTCSWrEnLegal_T; // @[Debug.scala:1190:39, :1742:44] assign _COMMANDWrEnLegal_T = ~(|ctrlStateReg); // @[Debug.scala:1732:27, :1740:42, :1742:44, :1743:44] assign COMMANDWrEnLegal = _COMMANDWrEnLegal_T; // @[Debug.scala:1282:39, :1743:44] assign _ABSTRACTAUTOWrEnLegal_T = ~(|ctrlStateReg); // @[Debug.scala:1732:27, :1740:42, :1742:44, :1744:44] assign ABSTRACTAUTOWrEnLegal = _ABSTRACTAUTOWrEnLegal_T; // @[Debug.scala:1243:41, :1744:44] assign _dmiAbstractDataAccessLegal_T = ~(|ctrlStateReg); // @[Debug.scala:1732:27, :1740:42, :1742:44, :1745:50] assign dmiAbstractDataAccessLegal = _dmiAbstractDataAccessLegal_T; // @[Debug.scala:892:46, :1745:50] assign _dmiProgramBufferAccessLegal_T = ~(|ctrlStateReg); // @[Debug.scala:1732:27, :1740:42, :1742:44, :1746:50] assign dmiProgramBufferAccessLegal = _dmiProgramBufferAccessLegal_T; // @[Debug.scala:888:47, :1746:50] wire _errorBusy_T = ~ABSTRACTCSWrEnLegal; // @[Debug.scala:1190:39, :1748:45] wire _errorBusy_T_1 = ABSTRACTCSWrEnMaybe & _errorBusy_T; // @[Debug.scala:1188:39, :1748:{42,45}] wire _errorBusy_T_2 = ~ABSTRACTAUTOWrEnLegal; // @[Debug.scala:1243:41, :1749:45] wire _errorBusy_T_3 = autoexecdataWrEnMaybe & _errorBusy_T_2; // @[Debug.scala:1240:41, :1749:{42,45}] wire _errorBusy_T_4 = _errorBusy_T_1 | _errorBusy_T_3; // @[Debug.scala:1748:{42,74}, :1749:42] wire _errorBusy_T_5 = ~ABSTRACTAUTOWrEnLegal; // @[Debug.scala:1243:41, :1749:45, :1750:47] wire _errorBusy_T_6 = autoexecprogbufWrEnMaybe & _errorBusy_T_5; // @[Debug.scala:1241:44, :1750:{44,47}] wire _errorBusy_T_7 = _errorBusy_T_4 | _errorBusy_T_6; // @[Debug.scala:1748:74, :1749:74, :1750:44] wire _errorBusy_T_8 = ~COMMANDWrEnLegal; // @[Debug.scala:1282:39, :1751:45] wire _errorBusy_T_9 = COMMANDWrEnMaybe & _errorBusy_T_8; // @[Debug.scala:1281:39, :1751:{42,45}] wire _errorBusy_T_10 = _errorBusy_T_7 | _errorBusy_T_9; // @[Debug.scala:1749:74, :1750:74, :1751:42] wire _errorBusy_T_11 = ~dmiAbstractDataAccessLegal; // @[Debug.scala:892:46, :1752:45] wire _errorBusy_T_12 = dmiAbstractDataAccess & _errorBusy_T_11; // @[Debug.scala:1263:68, :1752:{42,45}] wire _errorBusy_T_13 = _errorBusy_T_10 | _errorBusy_T_12; // @[Debug.scala:1750:74, :1751:74, :1752:42] wire _errorBusy_T_14 = ~dmiProgramBufferAccessLegal; // @[Debug.scala:888:47, :1753:45] wire _errorBusy_T_15 = dmiProgramBufferAccess & _errorBusy_T_14; // @[Debug.scala:1264:69, :1753:{42,45}] assign _errorBusy_T_16 = _errorBusy_T_13 | _errorBusy_T_15; // @[Debug.scala:1751:74, :1752:74, :1753:42] assign errorBusy = _errorBusy_T_16; // @[Debug.scala:1195:36, :1752:74] wire commandWrIsAccessRegister = COMMANDWrData_cmdtype == 8'h0; // @[Debug.scala:1280:39, :1756:60] wire commandRegIsAccessRegister = COMMANDReg_cmdtype == 8'h0; // @[Debug.scala:1277:25, :1757:58] wire _commandWrIsUnsupported_T = ~commandWrIsAccessRegister; // @[Debug.scala:1756:60, :1759:49] wire commandWrIsUnsupported = COMMANDWrEn & _commandWrIsUnsupported_T; // @[Debug.scala:1285:40, :1759:{46,49}] wire commandRegIsUnsupported; // @[Debug.scala:1761:43] wire commandRegBadHaltResume; // @[Debug.scala:1762:43] wire _accessRegIsLegalSize_T = accessRegisterCommandReg_size == 3'h2; // @[Debug.scala:1533:44, :1765:63] wire _accessRegIsLegalSize_T_1 = accessRegisterCommandReg_size == 3'h3; // @[Debug.scala:1533:44, :1765:106] wire accessRegIsLegalSize = _accessRegIsLegalSize_T | _accessRegIsLegalSize_T_1; // @[Debug.scala:1765:{63,72,106}] wire _accessRegIsGPR_T = |(accessRegisterCommandReg_regno[15:12]); // @[Debug.scala:1533:44, :1766:58] wire _accessRegIsGPR_T_1 = accessRegisterCommandReg_regno < 16'h1020; // @[Debug.scala:1533:44, :1766:104] wire _accessRegIsGPR_T_2 = _accessRegIsGPR_T & _accessRegIsGPR_T_1; // @[Debug.scala:1766:{58,70,104}] wire accessRegIsGPR = _accessRegIsGPR_T_2 & accessRegIsLegalSize; // @[Debug.scala:1765:72, :1766:{70,117}] wire _T_1567 = ~accessRegisterCommandReg_transfer | accessRegIsGPR; // @[Debug.scala:1533:44, :1766:117, :1776:{19,54}] assign commandRegIsUnsupported = ~commandRegIsAccessRegister | ~_T_1567; // @[Debug.scala:1757:58, :1761:43, :1773:39, :1774:115, :1775:33, :1776:{54,73}, :1777:33] wire _commandRegBadHaltResume_T = ~hartHalted; // @[Debug.scala:1734:37, :1778:36] assign commandRegBadHaltResume = commandRegIsAccessRegister & _T_1567 & _commandRegBadHaltResume_T; // @[Debug.scala:1757:58, :1762:43, :1773:39, :1774:115, :1776:{54,73}, :1778:{33,36}] wire _wrAccessRegisterCommand_T = COMMANDWrEn & commandWrIsAccessRegister; // @[Debug.scala:1285:40, :1756:60, :1782:48] wire _GEN_26 = ABSTRACTCSReg_cmderr == 3'h0; // @[Debug.scala:1183:34, :1782:103] wire _wrAccessRegisterCommand_T_1; // @[Debug.scala:1782:103] assign _wrAccessRegisterCommand_T_1 = _GEN_26; // @[Debug.scala:1782:103] wire _regAccessRegisterCommand_T_1; // @[Debug.scala:1783:103] assign _regAccessRegisterCommand_T_1 = _GEN_26; // @[Debug.scala:1782:103, :1783:103] wire wrAccessRegisterCommand = _wrAccessRegisterCommand_T & _wrAccessRegisterCommand_T_1; // @[Debug.scala:1782:{48,78,103}] wire _regAccessRegisterCommand_T = autoexec & commandRegIsAccessRegister; // @[Debug.scala:1272:48, :1757:58, :1783:48] wire regAccessRegisterCommand = _regAccessRegisterCommand_T & _regAccessRegisterCommand_T_1; // @[Debug.scala:1783:{48,78,103}] wire _T_1569 = wrAccessRegisterCommand | regAccessRegisterCommand; // @[Debug.scala:1782:78, :1783:78, :1790:37] wire _T_1571 = ctrlStateReg == 2'h1; // @[Debug.scala:1732:27, :1797:30] assign errorUnsupported = (|ctrlStateReg) ? _T_1571 & commandRegIsUnsupported : ~_T_1569 & (commandWrIsUnsupported | autoexec & commandRegIsUnsupported); // @[Debug.scala:1197:36, :1272:48, :1732:27, :1740:42, :1759:46, :1761:43, :1789:47, :1790:{37,66}, :1792:43, :1793:26, :1794:{28,56}, :1797:{30,59}, :1804:38] assign errorHaltResume = (|ctrlStateReg) & _T_1571 & ~commandRegIsUnsupported & commandRegBadHaltResume; // @[Debug.scala:1198:36, :1732:27, :1740:42, :1761:43, :1762:43, :1789:47, :1797:{30,59}, :1804:38, :1807:43] wire _GEN_27 = commandRegIsUnsupported | commandRegBadHaltResume; // @[Debug.scala:1761:43, :1762:43, :1804:38, :1806:22, :1807:43, :1809:22, :1811:33] assign goAbstract = (|ctrlStateReg) & _T_1571 & ~_GEN_27; // @[Debug.scala:1495:32, :1732:27, :1740:42, :1789:47, :1797:{30,59}, :1804:38, :1806:22, :1807:43, :1809:22, :1811:33] wire _T_1572 = ctrlStateReg == 2'h2; // @[Debug.scala:1732:27, :1818:30] wire _GEN_28 = ~(|ctrlStateReg) | _T_1571; // @[Debug.scala:1196:36, :1732:27, :1740:42, :1742:44, :1789:47, :1797:{30,59}, :1818:51] assign errorException = ~_GEN_28 & _T_1572 & hartExceptionWrEn; // @[Debug.scala:881:36, :1196:36, :1789:47, :1797:59, :1818:{30,51}, :1826:31] assign goCustom = ~(_GEN_28 | _T_1572) & (&ctrlStateReg); // @[Debug.scala:1196:36, :1496:32, :1732:27, :1789:47, :1797:59, :1818:{30,51}, :1831:{30,53}] assign ctrlStateNxt = (|ctrlStateReg) ? (_T_1571 ? {~_GEN_27, 1'h0} : _T_1572 & (hartExceptionWrEn | ~goReg & hartHaltedWrEn) ? 2'h0 : ctrlStateReg) : _T_1569 ? 2'h1 : ctrlStateReg; // @[Debug.scala:875:36, :881:36, :1494:27, :1732:27, :1735:32, :1740:42, :1789:47, :1790:{37,66}, :1791:22, :1797:{30,59}, :1804:38, :1806:22, :1807:43, :1809:22, :1811:33, :1818:{30,51}, :1823:{18,30,116}, :1824:22, :1826:31, :1828:24, :1831:53]

Generate the Verilog code corresponding to the following Chisel files. File primitives.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object lowMask { def apply(in: UInt, topBound: BigInt, bottomBound: BigInt): UInt = { require(topBound != bottomBound) val numInVals = BigInt(1)<<in.getWidth if (topBound < bottomBound) { lowMask(~in, numInVals - 1 - topBound, numInVals - 1 - bottomBound) } else if (numInVals > 64 /* Empirical */) { // For simulation performance, we should avoid generating // exteremely wide shifters, so we divide and conquer. // Empirically, this does not impact synthesis QoR. val mid = numInVals / 2 val msb = in(in.getWidth - 1) val lsbs = in(in.getWidth - 2, 0) if (mid < topBound) { if (mid <= bottomBound) { Mux(msb, lowMask(lsbs, topBound - mid, bottomBound - mid), 0.U ) } else { Mux(msb, lowMask(lsbs, topBound - mid, 0) ## ((BigInt(1)<<(mid - bottomBound).toInt) - 1).U, lowMask(lsbs, mid, bottomBound) ) } } else { ~Mux(msb, 0.U, ~lowMask(lsbs, topBound, bottomBound)) } } else { val shift = (BigInt(-1)<<numInVals.toInt).S>>in Reverse( shift( (numInVals - 1 - bottomBound).toInt, (numInVals - topBound).toInt ) ) } } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object countLeadingZeros { def apply(in: UInt): UInt = PriorityEncoder(in.asBools.reverse) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy2 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 1)>>1 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 2 + 1, ix * 2).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 2).orR reducedVec.asUInt } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy4 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 3)>>2 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 4 + 3, ix * 4).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 4).orR reducedVec.asUInt } } File RoundAnyRawFNToRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util.Fill import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundAnyRawFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int, options: Int ) extends RawModule { override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(inExpWidth, inSigWidth)) // (allowed exponent range has limits) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0) val effectiveInSigWidth = if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1 val neverUnderflows = ((options & (flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact) ) != 0) || (inExpWidth < outExpWidth) val neverOverflows = ((options & flRoundOpt_neverOverflows) != 0) || (inExpWidth < outExpWidth) val outNaNExp = BigInt(7)<<(outExpWidth - 2) val outInfExp = BigInt(6)<<(outExpWidth - 2) val outMaxFiniteExp = outInfExp - 1 val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2 val outMinNonzeroExp = outMinNormExp - outSigWidth + 1 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_near_even = (io.roundingMode === round_near_even) val roundingMode_minMag = (io.roundingMode === round_minMag) val roundingMode_min = (io.roundingMode === round_min) val roundingMode_max = (io.roundingMode === round_max) val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag) val roundingMode_odd = (io.roundingMode === round_odd) val roundMagUp = (roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sAdjustedExp = if (inExpWidth < outExpWidth) (io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S )(outExpWidth, 0).zext else if (inExpWidth == outExpWidth) io.in.sExp else io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S val adjustedSig = if (inSigWidth <= outSigWidth + 2) io.in.sig<<(outSigWidth - inSigWidth + 2) else (io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ## io.in.sig(inSigWidth - outSigWidth - 2, 0).orR ) val doShiftSigDown1 = if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2) val common_expOut = Wire(UInt((outExpWidth + 1).W)) val common_fractOut = Wire(UInt((outSigWidth - 1).W)) val common_overflow = Wire(Bool()) val common_totalUnderflow = Wire(Bool()) val common_underflow = Wire(Bool()) val common_inexact = Wire(Bool()) if ( neverOverflows && neverUnderflows && (effectiveInSigWidth <= outSigWidth) ) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1 common_fractOut := Mux(doShiftSigDown1, adjustedSig(outSigWidth + 1, 3), adjustedSig(outSigWidth, 2) ) common_overflow := false.B common_totalUnderflow := false.B common_underflow := false.B common_inexact := false.B } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundMask = if (neverUnderflows) 0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W) else (lowMask( sAdjustedExp(outExpWidth, 0), outMinNormExp - outSigWidth - 1, outMinNormExp ) | doShiftSigDown1) ## 3.U(2.W) val shiftedRoundMask = 0.U(1.W) ## roundMask>>1 val roundPosMask = ~shiftedRoundMask & roundMask val roundPosBit = (adjustedSig & roundPosMask).orR val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR val anyRound = roundPosBit || anyRoundExtra val roundIncr = ((roundingMode_near_even || roundingMode_near_maxMag) && roundPosBit) || (roundMagUp && anyRound) val roundedSig: Bits = Mux(roundIncr, (((adjustedSig | roundMask)>>2) +& 1.U) & ~Mux(roundingMode_near_even && roundPosBit && ! anyRoundExtra, roundMask>>1, 0.U((outSigWidth + 2).W) ), (adjustedSig & ~roundMask)>>2 | Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U) ) //*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //*** M.S. BIT OF SUBNORMAL SIG? val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext common_expOut := sRoundedExp(outExpWidth, 0) common_fractOut := Mux(doShiftSigDown1, roundedSig(outSigWidth - 1, 1), roundedSig(outSigWidth - 2, 0) ) common_overflow := (if (neverOverflows) false.B else //*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?: (sRoundedExp>>(outExpWidth - 1) >= 3.S)) common_totalUnderflow := (if (neverUnderflows) false.B else //*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?: (sRoundedExp < outMinNonzeroExp.S)) val unboundedRange_roundPosBit = Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1)) val unboundedRange_anyRound = (doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR val unboundedRange_roundIncr = ((roundingMode_near_even || roundingMode_near_maxMag) && unboundedRange_roundPosBit) || (roundMagUp && unboundedRange_anyRound) val roundCarry = Mux(doShiftSigDown1, roundedSig(outSigWidth + 1), roundedSig(outSigWidth) ) common_underflow := (if (neverUnderflows) false.B else common_totalUnderflow || //*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //*** M.S. BIT OF SUBNORMAL SIG? (anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) && Mux(doShiftSigDown1, roundMask(3), roundMask(2)) && ! ((io.detectTininess === tininess_afterRounding) && ! Mux(doShiftSigDown1, roundMask(4), roundMask(3) ) && roundCarry && roundPosBit && unboundedRange_roundIncr))) common_inexact := common_totalUnderflow || anyRound } //------------------------------------------------------------------------ //------------------------------------------------------------------------ val isNaNOut = io.invalidExc || io.in.isNaN val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero val overflow = commonCase && common_overflow val underflow = commonCase && common_underflow val inexact = overflow || (commonCase && common_inexact) val overflow_roundMagUp = roundingMode_near_even || roundingMode_near_maxMag || roundMagUp val pegMinNonzeroMagOut = commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd) val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp val notNaN_isInfOut = notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp) val signOut = Mux(isNaNOut, false.B, io.in.sign) val expOut = (common_expOut & ~Mux(io.in.isZero || common_totalUnderflow, (BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMinNonzeroMagOut, ~outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMaxFiniteMagOut, (BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W), 0.U ) & ~Mux(notNaN_isInfOut, (BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U )) | Mux(pegMinNonzeroMagOut, outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) | Mux(pegMaxFiniteMagOut, outMaxFiniteExp.U((outExpWidth + 1).W), 0.U ) | Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) | Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U) val fractOut = Mux(isNaNOut || io.in.isZero || common_totalUnderflow, Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U), common_fractOut ) | Fill(outSigWidth - 1, pegMaxFiniteMagOut) io.out := signOut ## expOut ## fractOut io.exceptionFlags := io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int) extends RawModule { override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(expWidth, sigWidth + 2)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( expWidth, sigWidth + 2, expWidth, sigWidth, options)) roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc roundAnyRawFNToRecFN.io.in := io.in roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags }

module RoundAnyRawFNToRecFN_ie11_is55_oe11_os53_3( // @[RoundAnyRawFNToRecFN.scala:48:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_infiniteExc, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16] input [12:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16] input [55:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16] input [2:0] io_roundingMode, // @[RoundAnyRawFNToRecFN.scala:58:16] output [64:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_infiniteExc_0 = io_infiniteExc; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [12:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [55:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [31:0] _roundMask_T_5 = 32'hFFFF; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_4 = 32'hFFFF0000; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_10 = 32'hFFFF0000; // @[primitives.scala:77:20] wire [23:0] _roundMask_T_13 = 24'hFFFF; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_14 = 32'hFFFF00; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_15 = 32'hFF00FF; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_20 = 32'hFF00FF00; // @[primitives.scala:77:20] wire [27:0] _roundMask_T_23 = 28'hFF00FF; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_24 = 32'hFF00FF0; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_25 = 32'hF0F0F0F; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_30 = 32'hF0F0F0F0; // @[primitives.scala:77:20] wire [29:0] _roundMask_T_33 = 30'hF0F0F0F; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_34 = 32'h3C3C3C3C; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_35 = 32'h33333333; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_40 = 32'hCCCCCCCC; // @[primitives.scala:77:20] wire [30:0] _roundMask_T_43 = 31'h33333333; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_44 = 32'h66666666; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_45 = 32'h55555555; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_50 = 32'hAAAAAAAA; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_56 = 16'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_55 = 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_61 = 16'hFF00; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_64 = 12'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_65 = 16'hFF0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_66 = 16'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_71 = 16'hF0F0; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_74 = 14'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_75 = 16'h3C3C; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_76 = 16'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_81 = 16'hCCCC; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_84 = 15'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_85 = 16'h6666; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_86 = 16'h5555; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_91 = 16'hAAAA; // @[primitives.scala:77:20] wire _common_underflow_T_16 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:222:27] wire [11:0] _expOut_T_4 = 12'hC31; // @[RoundAnyRawFNToRecFN.scala:258:19] wire io_detectTininess = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire _unboundedRange_anyRound_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:205:30] wire _common_underflow_T_7 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:222:49] wire _common_underflow_T_12 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:222:77] wire _common_underflow_T_13 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:226:38] wire _common_underflow_T_14 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:227:45] wire _common_underflow_T_15 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:227:60] wire [55:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22] wire [64:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33] wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66] wire [64:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_near_even = io_roundingMode_0 == 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :90:53] wire roundingMode_minMag = io_roundingMode_0 == 3'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :91:53] wire roundingMode_min = io_roundingMode_0 == 3'h2; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53] wire roundingMode_max = io_roundingMode_0 == 3'h3; // @[RoundAnyRawFNToRecFN.scala:48:5, :93:53] wire roundingMode_near_maxMag = io_roundingMode_0 == 3'h4; // @[RoundAnyRawFNToRecFN.scala:48:5, :94:53] wire roundingMode_odd = io_roundingMode_0 == 3'h6; // @[RoundAnyRawFNToRecFN.scala:48:5, :95:53] wire _roundMagUp_T = roundingMode_min & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53, :98:27] wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66] wire _roundMagUp_T_2 = roundingMode_max & _roundMagUp_T_1; // @[RoundAnyRawFNToRecFN.scala:93:53, :98:{63,66}] wire roundMagUp = _roundMagUp_T | _roundMagUp_T_2; // @[RoundAnyRawFNToRecFN.scala:98:{27,42,63}] wire [11:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37] wire [11:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31] wire [51:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16] wire [51:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31] wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50] wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37] wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31] wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37] wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40] wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37] wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49] wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37] wire [11:0] _roundMask_T = io_in_sExp_0[11:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37] wire [11:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21] wire roundMask_msb = _roundMask_T_1[11]; // @[primitives.scala:52:21, :58:25] wire [10:0] roundMask_lsbs = _roundMask_T_1[10:0]; // @[primitives.scala:52:21, :59:26] wire roundMask_msb_1 = roundMask_lsbs[10]; // @[primitives.scala:58:25, :59:26] wire [9:0] roundMask_lsbs_1 = roundMask_lsbs[9:0]; // @[primitives.scala:59:26] wire roundMask_msb_2 = roundMask_lsbs_1[9]; // @[primitives.scala:58:25, :59:26] wire roundMask_msb_6 = roundMask_lsbs_1[9]; // @[primitives.scala:58:25, :59:26] wire [8:0] roundMask_lsbs_2 = roundMask_lsbs_1[8:0]; // @[primitives.scala:59:26] wire [8:0] roundMask_lsbs_6 = roundMask_lsbs_1[8:0]; // @[primitives.scala:59:26] wire roundMask_msb_3 = roundMask_lsbs_2[8]; // @[primitives.scala:58:25, :59:26] wire [7:0] roundMask_lsbs_3 = roundMask_lsbs_2[7:0]; // @[primitives.scala:59:26] wire roundMask_msb_4 = roundMask_lsbs_3[7]; // @[primitives.scala:58:25, :59:26] wire [6:0] roundMask_lsbs_4 = roundMask_lsbs_3[6:0]; // @[primitives.scala:59:26] wire roundMask_msb_5 = roundMask_lsbs_4[6]; // @[primitives.scala:58:25, :59:26] wire [5:0] roundMask_lsbs_5 = roundMask_lsbs_4[5:0]; // @[primitives.scala:59:26] wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_5); // @[primitives.scala:59:26, :76:56] wire [50:0] _roundMask_T_2 = roundMask_shift[63:13]; // @[primitives.scala:76:56, :78:22] wire [31:0] _roundMask_T_3 = _roundMask_T_2[31:0]; // @[primitives.scala:77:20, :78:22] wire [15:0] _roundMask_T_6 = _roundMask_T_3[31:16]; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_7 = {16'h0, _roundMask_T_6}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_8 = _roundMask_T_3[15:0]; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_9 = {_roundMask_T_8, 16'h0}; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_11 = _roundMask_T_9 & 32'hFFFF0000; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_12 = _roundMask_T_7 | _roundMask_T_11; // @[primitives.scala:77:20] wire [23:0] _roundMask_T_16 = _roundMask_T_12[31:8]; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_17 = {8'h0, _roundMask_T_16 & 24'hFF00FF}; // @[primitives.scala:77:20] wire [23:0] _roundMask_T_18 = _roundMask_T_12[23:0]; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_19 = {_roundMask_T_18, 8'h0}; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_21 = _roundMask_T_19 & 32'hFF00FF00; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_22 = _roundMask_T_17 | _roundMask_T_21; // @[primitives.scala:77:20] wire [27:0] _roundMask_T_26 = _roundMask_T_22[31:4]; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_27 = {4'h0, _roundMask_T_26 & 28'hF0F0F0F}; // @[primitives.scala:77:20] wire [27:0] _roundMask_T_28 = _roundMask_T_22[27:0]; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_29 = {_roundMask_T_28, 4'h0}; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_31 = _roundMask_T_29 & 32'hF0F0F0F0; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_32 = _roundMask_T_27 | _roundMask_T_31; // @[primitives.scala:77:20] wire [29:0] _roundMask_T_36 = _roundMask_T_32[31:2]; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_37 = {2'h0, _roundMask_T_36 & 30'h33333333}; // @[primitives.scala:77:20] wire [29:0] _roundMask_T_38 = _roundMask_T_32[29:0]; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_39 = {_roundMask_T_38, 2'h0}; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_41 = _roundMask_T_39 & 32'hCCCCCCCC; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_42 = _roundMask_T_37 | _roundMask_T_41; // @[primitives.scala:77:20] wire [30:0] _roundMask_T_46 = _roundMask_T_42[31:1]; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_47 = {1'h0, _roundMask_T_46 & 31'h55555555}; // @[primitives.scala:77:20] wire [30:0] _roundMask_T_48 = _roundMask_T_42[30:0]; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_49 = {_roundMask_T_48, 1'h0}; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_51 = _roundMask_T_49 & 32'hAAAAAAAA; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_52 = _roundMask_T_47 | _roundMask_T_51; // @[primitives.scala:77:20] wire [18:0] _roundMask_T_53 = _roundMask_T_2[50:32]; // @[primitives.scala:77:20, :78:22] wire [15:0] _roundMask_T_54 = _roundMask_T_53[15:0]; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_57 = _roundMask_T_54[15:8]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_58 = {8'h0, _roundMask_T_57}; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_59 = _roundMask_T_54[7:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_60 = {_roundMask_T_59, 8'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_62 = _roundMask_T_60 & 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_63 = _roundMask_T_58 | _roundMask_T_62; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_67 = _roundMask_T_63[15:4]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_68 = {4'h0, _roundMask_T_67 & 12'hF0F}; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_69 = _roundMask_T_63[11:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_70 = {_roundMask_T_69, 4'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_72 = _roundMask_T_70 & 16'hF0F0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_73 = _roundMask_T_68 | _roundMask_T_72; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_77 = _roundMask_T_73[15:2]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_78 = {2'h0, _roundMask_T_77 & 14'h3333}; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_79 = _roundMask_T_73[13:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_80 = {_roundMask_T_79, 2'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_82 = _roundMask_T_80 & 16'hCCCC; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_83 = _roundMask_T_78 | _roundMask_T_82; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_87 = _roundMask_T_83[15:1]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_88 = {1'h0, _roundMask_T_87 & 15'h5555}; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_89 = _roundMask_T_83[14:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_90 = {_roundMask_T_89, 1'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_92 = _roundMask_T_90 & 16'hAAAA; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_93 = _roundMask_T_88 | _roundMask_T_92; // @[primitives.scala:77:20] wire [2:0] _roundMask_T_94 = _roundMask_T_53[18:16]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_95 = _roundMask_T_94[1:0]; // @[primitives.scala:77:20] wire _roundMask_T_96 = _roundMask_T_95[0]; // @[primitives.scala:77:20] wire _roundMask_T_97 = _roundMask_T_95[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_98 = {_roundMask_T_96, _roundMask_T_97}; // @[primitives.scala:77:20] wire _roundMask_T_99 = _roundMask_T_94[2]; // @[primitives.scala:77:20] wire [2:0] _roundMask_T_100 = {_roundMask_T_98, _roundMask_T_99}; // @[primitives.scala:77:20] wire [18:0] _roundMask_T_101 = {_roundMask_T_93, _roundMask_T_100}; // @[primitives.scala:77:20] wire [50:0] _roundMask_T_102 = {_roundMask_T_52, _roundMask_T_101}; // @[primitives.scala:77:20] wire [50:0] _roundMask_T_103 = ~_roundMask_T_102; // @[primitives.scala:73:32, :77:20] wire [50:0] _roundMask_T_104 = roundMask_msb_5 ? 51'h0 : _roundMask_T_103; // @[primitives.scala:58:25, :73:{21,32}] wire [50:0] _roundMask_T_105 = ~_roundMask_T_104; // @[primitives.scala:73:{17,21}] wire [50:0] _roundMask_T_106 = ~_roundMask_T_105; // @[primitives.scala:73:{17,32}] wire [50:0] _roundMask_T_107 = roundMask_msb_4 ? 51'h0 : _roundMask_T_106; // @[primitives.scala:58:25, :73:{21,32}] wire [50:0] _roundMask_T_108 = ~_roundMask_T_107; // @[primitives.scala:73:{17,21}] wire [50:0] _roundMask_T_109 = ~_roundMask_T_108; // @[primitives.scala:73:{17,32}] wire [50:0] _roundMask_T_110 = roundMask_msb_3 ? 51'h0 : _roundMask_T_109; // @[primitives.scala:58:25, :73:{21,32}] wire [50:0] _roundMask_T_111 = ~_roundMask_T_110; // @[primitives.scala:73:{17,21}] wire [50:0] _roundMask_T_112 = ~_roundMask_T_111; // @[primitives.scala:73:{17,32}] wire [50:0] _roundMask_T_113 = roundMask_msb_2 ? 51'h0 : _roundMask_T_112; // @[primitives.scala:58:25, :73:{21,32}] wire [50:0] _roundMask_T_114 = ~_roundMask_T_113; // @[primitives.scala:73:{17,21}] wire [53:0] _roundMask_T_115 = {_roundMask_T_114, 3'h7}; // @[primitives.scala:68:58, :73:17] wire roundMask_msb_7 = roundMask_lsbs_6[8]; // @[primitives.scala:58:25, :59:26] wire [7:0] roundMask_lsbs_7 = roundMask_lsbs_6[7:0]; // @[primitives.scala:59:26] wire roundMask_msb_8 = roundMask_lsbs_7[7]; // @[primitives.scala:58:25, :59:26] wire [6:0] roundMask_lsbs_8 = roundMask_lsbs_7[6:0]; // @[primitives.scala:59:26] wire roundMask_msb_9 = roundMask_lsbs_8[6]; // @[primitives.scala:58:25, :59:26] wire [5:0] roundMask_lsbs_9 = roundMask_lsbs_8[5:0]; // @[primitives.scala:59:26] wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_9); // @[primitives.scala:59:26, :76:56] wire [2:0] _roundMask_T_116 = roundMask_shift_1[2:0]; // @[primitives.scala:76:56, :78:22] wire [1:0] _roundMask_T_117 = _roundMask_T_116[1:0]; // @[primitives.scala:77:20, :78:22] wire _roundMask_T_118 = _roundMask_T_117[0]; // @[primitives.scala:77:20] wire _roundMask_T_119 = _roundMask_T_117[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_120 = {_roundMask_T_118, _roundMask_T_119}; // @[primitives.scala:77:20] wire _roundMask_T_121 = _roundMask_T_116[2]; // @[primitives.scala:77:20, :78:22] wire [2:0] _roundMask_T_122 = {_roundMask_T_120, _roundMask_T_121}; // @[primitives.scala:77:20] wire [2:0] _roundMask_T_123 = roundMask_msb_9 ? _roundMask_T_122 : 3'h0; // @[primitives.scala:58:25, :62:24, :77:20] wire [2:0] _roundMask_T_124 = roundMask_msb_8 ? _roundMask_T_123 : 3'h0; // @[primitives.scala:58:25, :62:24] wire [2:0] _roundMask_T_125 = roundMask_msb_7 ? _roundMask_T_124 : 3'h0; // @[primitives.scala:58:25, :62:24] wire [2:0] _roundMask_T_126 = roundMask_msb_6 ? _roundMask_T_125 : 3'h0; // @[primitives.scala:58:25, :62:24] wire [53:0] _roundMask_T_127 = roundMask_msb_1 ? _roundMask_T_115 : {51'h0, _roundMask_T_126}; // @[primitives.scala:58:25, :62:24, :67:24, :68:58] wire [53:0] _roundMask_T_128 = roundMask_msb ? _roundMask_T_127 : 54'h0; // @[primitives.scala:58:25, :62:24, :67:24] wire [53:0] _roundMask_T_129 = _roundMask_T_128; // @[primitives.scala:62:24] wire [55:0] roundMask = {_roundMask_T_129, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}] wire [56:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41] wire [55:0] shiftedRoundMask = _shiftedRoundMask_T[56:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}] wire [55:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28] wire [55:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}] wire [55:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40] wire roundPosBit = |_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}] wire [55:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42] wire anyRoundExtra = |_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}] wire anyRound = roundPosBit | anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36] wire _GEN = roundingMode_near_even | roundingMode_near_maxMag; // @[RoundAnyRawFNToRecFN.scala:90:53, :94:53, :169:38] wire _roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:169:38] assign _roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38] wire _unboundedRange_roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:207:38] assign _unboundedRange_roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :207:38] wire _overflow_roundMagUp_T; // @[RoundAnyRawFNToRecFN.scala:243:32] assign _overflow_roundMagUp_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :243:32] wire _roundIncr_T_1 = _roundIncr_T & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:{38,67}] wire _roundIncr_T_2 = roundMagUp & anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :166:36, :171:29] wire roundIncr = _roundIncr_T_1 | _roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31, :171:29] wire [55:0] _roundedSig_T = adjustedSig | roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32] wire [53:0] _roundedSig_T_1 = _roundedSig_T[55:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}] wire [54:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 55'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}] wire _roundedSig_T_3 = roundingMode_near_even & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:90:53, :164:56, :175:49] wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30] wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30] wire [54:0] _roundedSig_T_6 = roundMask[55:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35] wire [54:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 55'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35] wire [54:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}] wire [54:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21] wire [55:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32] wire [55:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}] wire [53:0] _roundedSig_T_12 = _roundedSig_T_11[55:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}] wire _roundedSig_T_13 = roundingMode_odd & anyRound; // @[RoundAnyRawFNToRecFN.scala:95:53, :166:36, :181:42] wire [54:0] _roundedSig_T_14 = roundPosMask[55:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67] wire [54:0] _roundedSig_T_15 = _roundedSig_T_13 ? _roundedSig_T_14 : 55'h0; // @[RoundAnyRawFNToRecFN.scala:181:{24,42,67}] wire [54:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12} | _roundedSig_T_15; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}, :181:24] wire [54:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47] wire [1:0] _sRoundedExp_T = roundedSig[54:53]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54] wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}] wire [13:0] sRoundedExp = {io_in_sExp_0[12], io_in_sExp_0} + {{11{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}] assign _common_expOut_T = sRoundedExp[11:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37] assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37] wire [51:0] _common_fractOut_T = roundedSig[52:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27] wire [51:0] _common_fractOut_T_1 = roundedSig[51:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27] assign _common_fractOut_T_2 = _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:189:16, :191:27] assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16] wire [3:0] _common_overflow_T = sRoundedExp[13:10]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30] assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}] assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50] assign _common_totalUnderflow_T = $signed(sRoundedExp) < 14'sh3CE; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31] assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31] wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45] wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44] wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61] wire unboundedRange_roundPosBit = _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:203:{16,61}] wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63] wire _unboundedRange_anyRound_T_3 = |_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}] wire unboundedRange_anyRound = _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{49,70}] wire _unboundedRange_roundIncr_T_1 = _unboundedRange_roundIncr_T & unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:{38,67}] wire _unboundedRange_roundIncr_T_2 = roundMagUp & unboundedRange_anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :205:49, :209:29] wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1 | _unboundedRange_roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46, :209:29] wire _roundCarry_T = roundedSig[54]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27] wire _roundCarry_T_1 = roundedSig[53]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27] wire roundCarry = _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:211:16, :213:27] wire [1:0] _common_underflow_T = io_in_sExp_0[12:11]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49] wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}] wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}] wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57] wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49] wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71] wire _common_underflow_T_5 = _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:221:{30,71}] wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30] wire _common_underflow_T_17 = _common_underflow_T_6; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76] wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49] wire _common_underflow_T_10 = _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:223:39, :225:49] wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}] assign _common_underflow_T_18 = common_totalUnderflow | _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76] assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40] assign _common_inexact_T = common_totalUnderflow | anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49] assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49] wire isNaNOut = io_invalidExc_0 | io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34] wire notNaN_isSpecialInfOut = io_infiniteExc_0 | io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49] wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22] wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36] wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}] wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64] wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}] wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32] wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32] wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43] wire inexact = overflow | _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}] wire overflow_roundMagUp = _overflow_roundMagUp_T | roundMagUp; // @[RoundAnyRawFNToRecFN.scala:98:42, :243:{32,60}] wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20] wire _pegMinNonzeroMagOut_T_1 = roundMagUp | roundingMode_odd; // @[RoundAnyRawFNToRecFN.scala:95:53, :98:42, :245:60] wire pegMinNonzeroMagOut = _pegMinNonzeroMagOut_T & _pegMinNonzeroMagOut_T_1; // @[RoundAnyRawFNToRecFN.scala:245:{20,45,60}] wire _pegMaxFiniteMagOut_T = ~overflow_roundMagUp; // @[RoundAnyRawFNToRecFN.scala:243:60, :246:42] wire pegMaxFiniteMagOut = overflow & _pegMaxFiniteMagOut_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :246:{39,42}] wire _notNaN_isInfOut_T = overflow & overflow_roundMagUp; // @[RoundAnyRawFNToRecFN.scala:238:32, :243:60, :248:45] wire notNaN_isInfOut = notNaN_isSpecialInfOut | _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}] wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22] wire _expOut_T = io_in_isZero_0 | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32] wire [11:0] _expOut_T_1 = _expOut_T ? 12'hE00 : 12'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}] wire [11:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}] wire [11:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14] wire [11:0] _expOut_T_5 = pegMinNonzeroMagOut ? 12'hC31 : 12'h0; // @[RoundAnyRawFNToRecFN.scala:245:45, :257:18] wire [11:0] _expOut_T_6 = ~_expOut_T_5; // @[RoundAnyRawFNToRecFN.scala:257:{14,18}] wire [11:0] _expOut_T_7 = _expOut_T_3 & _expOut_T_6; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17, :257:14] wire [11:0] _expOut_T_8 = {1'h0, pegMaxFiniteMagOut, 10'h0}; // @[RoundAnyRawFNToRecFN.scala:246:39, :261:18] wire [11:0] _expOut_T_9 = ~_expOut_T_8; // @[RoundAnyRawFNToRecFN.scala:261:{14,18}] wire [11:0] _expOut_T_10 = _expOut_T_7 & _expOut_T_9; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17, :261:14] wire [11:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 9'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18] wire [11:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}] wire [11:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14] wire [11:0] _expOut_T_14 = pegMinNonzeroMagOut ? 12'h3CE : 12'h0; // @[RoundAnyRawFNToRecFN.scala:245:45, :269:16] wire [11:0] _expOut_T_15 = _expOut_T_13 | _expOut_T_14; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18, :269:16] wire [11:0] _expOut_T_16 = pegMaxFiniteMagOut ? 12'hBFF : 12'h0; // @[RoundAnyRawFNToRecFN.scala:246:39, :273:16] wire [11:0] _expOut_T_17 = _expOut_T_15 | _expOut_T_16; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15, :273:16] wire [11:0] _expOut_T_18 = notNaN_isInfOut ? 12'hC00 : 12'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16] wire [11:0] _expOut_T_19 = _expOut_T_17 | _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16] wire [11:0] _expOut_T_20 = isNaNOut ? 12'hE00 : 12'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16] wire [11:0] expOut = _expOut_T_19 | _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16] wire _fractOut_T = isNaNOut | io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22] wire _fractOut_T_1 = _fractOut_T | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}] wire [51:0] _fractOut_T_2 = {isNaNOut, 51'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16] wire [51:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16] wire [51:0] _fractOut_T_4 = {52{pegMaxFiniteMagOut}}; // @[RoundAnyRawFNToRecFN.scala:246:39, :284:13] wire [51:0] fractOut = _fractOut_T_3 | _fractOut_T_4; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11, :284:13] wire [12:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23] assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}] assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33] wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, io_infiniteExc_0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23] wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}] wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}] assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] endmodule

Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag }

module OptimizationBarrier_TLBEntryData_282( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule

Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }

module AsyncValidSync_178( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_188 io_out_sink_extend ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }

module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_332( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)

Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }

module AsyncValidSync_134( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_144 io_out_source_extend ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File util.scala: //****************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v3.common.{MicroOp} import boom.v3.exu.{BrUpdateInfo} /** * Object to XOR fold a input register of fullLength into a compressedLength. */ object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /** * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks */ object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask) } def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) } } /** * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. */ object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /** * Object to return a BR mask given a MicroOp mask and old BR mask. */ object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask) out } } /** * Object to check if at least 1 bit matches in two masks */ object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /** * Object to clear one bit in a mask given an index */ object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /** * Object to shift a register over by one bit and concat a new one */ object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /** * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. */ object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /** * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. */ object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc | (b-1).U) } } /** * Object to rotate a signal left by one */ object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /** * Object to sext a value to a particular length. */ object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /** * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. */ object ImmGen { import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U} def apply(ip: UInt, isel: UInt): SInt = { val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt } } /** * Object to get the FP rounding mode out of a packed immediate. */ object ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } } /** * Object to get the FP function fype from a packed immediate. * Note: only works if !(IS_B or IS_S) */ object ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } } /** * Object to see if an instruction is a JALR. */ object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /** * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). */ object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /** * Object to return the lowest bit position after the head. */ object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /** * Object to determine whether queue * index i0 is older than index i1. */ object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } /** * Set all bits at or below the highest order '1'. */ object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_|_) } } /** * Set all bits at or above the lowest order '1'. */ object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_) } } /** * Transpose a matrix of Chisel Vecs. */ object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /** * N-wide one-hot priority encoder. */ object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /** * Connect the first k of n valid input interfaces to k output interfaces. */ class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_)) val out_valids = sels map (col => col.reduce(_||_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /** * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). */ class BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v3.common.BoomModule()(p) with boom.v3.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire) val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop) uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop)) io.deq.bits := out io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop) // For flow queue behavior. if (flow) { when (io.empty) { io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop) io.deq.bits := io.enq.bits io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) do_deq := false.B when (io.deq.ready) { do_enq := false.B } } } private val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /** * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" */ def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) */ def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) */ def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) */ def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /** * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line */ def apply(strs: String*)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } File consts.scala: //****************************************************************************** // Copyright (c) 2011 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Constants //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.common.constants import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util.Str import freechips.rocketchip.rocket.RVCExpander /** * Mixin for issue queue types */ trait IQType { val IQT_SZ = 3 val IQT_INT = 1.U(IQT_SZ.W) val IQT_MEM = 2.U(IQT_SZ.W) val IQT_FP = 4.U(IQT_SZ.W) val IQT_MFP = 6.U(IQT_SZ.W) } /** * Mixin for scalar operation constants */ trait ScalarOpConstants { val X = BitPat("b?") val Y = BitPat("b1") val N = BitPat("b0") //************************************ // Extra Constants // Which branch predictor predicted us val BSRC_SZ = 2 val BSRC_1 = 0.U(BSRC_SZ.W) // 1-cycle branch pred val BSRC_2 = 1.U(BSRC_SZ.W) // 2-cycle branch pred val BSRC_3 = 2.U(BSRC_SZ.W) // 3-cycle branch pred val BSRC_C = 3.U(BSRC_SZ.W) // core branch resolution //************************************ // Control Signals // CFI types val CFI_SZ = 3 val CFI_X = 0.U(CFI_SZ.W) // Not a CFI instruction val CFI_BR = 1.U(CFI_SZ.W) // Branch val CFI_JAL = 2.U(CFI_SZ.W) // JAL val CFI_JALR = 3.U(CFI_SZ.W) // JALR // PC Select Signal val PC_PLUS4 = 0.U(2.W) // PC + 4 val PC_BRJMP = 1.U(2.W) // brjmp_target val PC_JALR = 2.U(2.W) // jump_reg_target // Branch Type val BR_N = 0.U(4.W) // Next val BR_NE = 1.U(4.W) // Branch on NotEqual val BR_EQ = 2.U(4.W) // Branch on Equal val BR_GE = 3.U(4.W) // Branch on Greater/Equal val BR_GEU = 4.U(4.W) // Branch on Greater/Equal Unsigned val BR_LT = 5.U(4.W) // Branch on Less Than val BR_LTU = 6.U(4.W) // Branch on Less Than Unsigned val BR_J = 7.U(4.W) // Jump val BR_JR = 8.U(4.W) // Jump Register // RS1 Operand Select Signal val OP1_RS1 = 0.U(2.W) // Register Source #1 val OP1_ZERO= 1.U(2.W) val OP1_PC = 2.U(2.W) val OP1_X = BitPat("b??") // RS2 Operand Select Signal val OP2_RS2 = 0.U(3.W) // Register Source #2 val OP2_IMM = 1.U(3.W) // immediate val OP2_ZERO= 2.U(3.W) // constant 0 val OP2_NEXT= 3.U(3.W) // constant 2/4 (for PC+2/4) val OP2_IMMC= 4.U(3.W) // for CSR imm found in RS1 val OP2_X = BitPat("b???") // Register File Write Enable Signal val REN_0 = false.B val REN_1 = true.B // Is 32b Word or 64b Doubldword? val SZ_DW = 1 val DW_X = true.B // Bool(xLen==64) val DW_32 = false.B val DW_64 = true.B val DW_XPR = true.B // Bool(xLen==64) // Memory Enable Signal val MEN_0 = false.B val MEN_1 = true.B val MEN_X = false.B // Immediate Extend Select val IS_I = 0.U(3.W) // I-Type (LD,ALU) val IS_S = 1.U(3.W) // S-Type (ST) val IS_B = 2.U(3.W) // SB-Type (BR) val IS_U = 3.U(3.W) // U-Type (LUI/AUIPC) val IS_J = 4.U(3.W) // UJ-Type (J/JAL) val IS_X = BitPat("b???") // Decode Stage Control Signals val RT_FIX = 0.U(2.W) val RT_FLT = 1.U(2.W) val RT_PAS = 3.U(2.W) // pass-through (prs1 := lrs1, etc) val RT_X = 2.U(2.W) // not-a-register (but shouldn't get a busy-bit, etc.) // TODO rename RT_NAR // Micro-op opcodes // TODO change micro-op opcodes into using enum val UOPC_SZ = 7 val uopX = BitPat.dontCare(UOPC_SZ) val uopNOP = 0.U(UOPC_SZ.W) val uopLD = 1.U(UOPC_SZ.W) val uopSTA = 2.U(UOPC_SZ.W) // store address generation val uopSTD = 3.U(UOPC_SZ.W) // store data generation val uopLUI = 4.U(UOPC_SZ.W) val uopADDI = 5.U(UOPC_SZ.W) val uopANDI = 6.U(UOPC_SZ.W) val uopORI = 7.U(UOPC_SZ.W) val uopXORI = 8.U(UOPC_SZ.W) val uopSLTI = 9.U(UOPC_SZ.W) val uopSLTIU= 10.U(UOPC_SZ.W) val uopSLLI = 11.U(UOPC_SZ.W) val uopSRAI = 12.U(UOPC_SZ.W) val uopSRLI = 13.U(UOPC_SZ.W) val uopSLL = 14.U(UOPC_SZ.W) val uopADD = 15.U(UOPC_SZ.W) val uopSUB = 16.U(UOPC_SZ.W) val uopSLT = 17.U(UOPC_SZ.W) val uopSLTU = 18.U(UOPC_SZ.W) val uopAND = 19.U(UOPC_SZ.W) val uopOR = 20.U(UOPC_SZ.W) val uopXOR = 21.U(UOPC_SZ.W) val uopSRA = 22.U(UOPC_SZ.W) val uopSRL = 23.U(UOPC_SZ.W) val uopBEQ = 24.U(UOPC_SZ.W) val uopBNE = 25.U(UOPC_SZ.W) val uopBGE = 26.U(UOPC_SZ.W) val uopBGEU = 27.U(UOPC_SZ.W) val uopBLT = 28.U(UOPC_SZ.W) val uopBLTU = 29.U(UOPC_SZ.W) val uopCSRRW= 30.U(UOPC_SZ.W) val uopCSRRS= 31.U(UOPC_SZ.W) val uopCSRRC= 32.U(UOPC_SZ.W) val uopCSRRWI=33.U(UOPC_SZ.W) val uopCSRRSI=34.U(UOPC_SZ.W) val uopCSRRCI=35.U(UOPC_SZ.W) val uopJ = 36.U(UOPC_SZ.W) val uopJAL = 37.U(UOPC_SZ.W) val uopJALR = 38.U(UOPC_SZ.W) val uopAUIPC= 39.U(UOPC_SZ.W) //val uopSRET = 40.U(UOPC_SZ.W) val uopCFLSH= 41.U(UOPC_SZ.W) val uopFENCE= 42.U(UOPC_SZ.W) val uopADDIW= 43.U(UOPC_SZ.W) val uopADDW = 44.U(UOPC_SZ.W) val uopSUBW = 45.U(UOPC_SZ.W) val uopSLLIW= 46.U(UOPC_SZ.W) val uopSLLW = 47.U(UOPC_SZ.W) val uopSRAIW= 48.U(UOPC_SZ.W) val uopSRAW = 49.U(UOPC_SZ.W) val uopSRLIW= 50.U(UOPC_SZ.W) val uopSRLW = 51.U(UOPC_SZ.W) val uopMUL = 52.U(UOPC_SZ.W) val uopMULH = 53.U(UOPC_SZ.W) val uopMULHU= 54.U(UOPC_SZ.W) val uopMULHSU=55.U(UOPC_SZ.W) val uopMULW = 56.U(UOPC_SZ.W) val uopDIV = 57.U(UOPC_SZ.W) val uopDIVU = 58.U(UOPC_SZ.W) val uopREM = 59.U(UOPC_SZ.W) val uopREMU = 60.U(UOPC_SZ.W) val uopDIVW = 61.U(UOPC_SZ.W) val uopDIVUW= 62.U(UOPC_SZ.W) val uopREMW = 63.U(UOPC_SZ.W) val uopREMUW= 64.U(UOPC_SZ.W) val uopFENCEI = 65.U(UOPC_SZ.W) // = 66.U(UOPC_SZ.W) val uopAMO_AG = 67.U(UOPC_SZ.W) // AMO-address gen (use normal STD for datagen) val uopFMV_W_X = 68.U(UOPC_SZ.W) val uopFMV_D_X = 69.U(UOPC_SZ.W) val uopFMV_X_W = 70.U(UOPC_SZ.W) val uopFMV_X_D = 71.U(UOPC_SZ.W) val uopFSGNJ_S = 72.U(UOPC_SZ.W) val uopFSGNJ_D = 73.U(UOPC_SZ.W) val uopFCVT_S_D = 74.U(UOPC_SZ.W) val uopFCVT_D_S = 75.U(UOPC_SZ.W) val uopFCVT_S_X = 76.U(UOPC_SZ.W) val uopFCVT_D_X = 77.U(UOPC_SZ.W) val uopFCVT_X_S = 78.U(UOPC_SZ.W) val uopFCVT_X_D = 79.U(UOPC_SZ.W) val uopCMPR_S = 80.U(UOPC_SZ.W) val uopCMPR_D = 81.U(UOPC_SZ.W) val uopFCLASS_S = 82.U(UOPC_SZ.W) val uopFCLASS_D = 83.U(UOPC_SZ.W) val uopFMINMAX_S = 84.U(UOPC_SZ.W) val uopFMINMAX_D = 85.U(UOPC_SZ.W) // = 86.U(UOPC_SZ.W) val uopFADD_S = 87.U(UOPC_SZ.W) val uopFSUB_S = 88.U(UOPC_SZ.W) val uopFMUL_S = 89.U(UOPC_SZ.W) val uopFADD_D = 90.U(UOPC_SZ.W) val uopFSUB_D = 91.U(UOPC_SZ.W) val uopFMUL_D = 92.U(UOPC_SZ.W) val uopFMADD_S = 93.U(UOPC_SZ.W) val uopFMSUB_S = 94.U(UOPC_SZ.W) val uopFNMADD_S = 95.U(UOPC_SZ.W) val uopFNMSUB_S = 96.U(UOPC_SZ.W) val uopFMADD_D = 97.U(UOPC_SZ.W) val uopFMSUB_D = 98.U(UOPC_SZ.W) val uopFNMADD_D = 99.U(UOPC_SZ.W) val uopFNMSUB_D = 100.U(UOPC_SZ.W) val uopFDIV_S = 101.U(UOPC_SZ.W) val uopFDIV_D = 102.U(UOPC_SZ.W) val uopFSQRT_S = 103.U(UOPC_SZ.W) val uopFSQRT_D = 104.U(UOPC_SZ.W) val uopWFI = 105.U(UOPC_SZ.W) // pass uop down the CSR pipeline val uopERET = 106.U(UOPC_SZ.W) // pass uop down the CSR pipeline, also is ERET val uopSFENCE = 107.U(UOPC_SZ.W) val uopROCC = 108.U(UOPC_SZ.W) val uopMOV = 109.U(UOPC_SZ.W) // conditional mov decoded from "add rd, x0, rs2" // The Bubble Instruction (Machine generated NOP) // Insert (XOR x0,x0,x0) which is different from software compiler // generated NOPs which are (ADDI x0, x0, 0). // Reasoning for this is to let visualizers and stat-trackers differentiate // between software NOPs and machine-generated Bubbles in the pipeline. val BUBBLE = (0x4033).U(32.W) def NullMicroOp()(implicit p: Parameters): boom.v3.common.MicroOp = { val uop = Wire(new boom.v3.common.MicroOp) uop := DontCare // Overridden in the following lines uop.uopc := uopNOP // maybe not required, but helps on asserts that try to catch spurious behavior uop.bypassable := false.B uop.fp_val := false.B uop.uses_stq := false.B uop.uses_ldq := false.B uop.pdst := 0.U uop.dst_rtype := RT_X val cs = Wire(new boom.v3.common.CtrlSignals()) cs := DontCare // Overridden in the following lines cs.br_type := BR_N cs.csr_cmd := freechips.rocketchip.rocket.CSR.N cs.is_load := false.B cs.is_sta := false.B cs.is_std := false.B uop.ctrl := cs uop } } /** * Mixin for RISCV constants */ trait RISCVConstants { // abstract out instruction decode magic numbers val RD_MSB = 11 val RD_LSB = 7 val RS1_MSB = 19 val RS1_LSB = 15 val RS2_MSB = 24 val RS2_LSB = 20 val RS3_MSB = 31 val RS3_LSB = 27 val CSR_ADDR_MSB = 31 val CSR_ADDR_LSB = 20 val CSR_ADDR_SZ = 12 // location of the fifth bit in the shamt (for checking for illegal ops for SRAIW,etc.) val SHAMT_5_BIT = 25 val LONGEST_IMM_SZ = 20 val X0 = 0.U val RA = 1.U // return address register // memory consistency model // The C/C++ atomics MCM requires that two loads to the same address maintain program order. // The Cortex A9 does NOT enforce load/load ordering (which leads to buggy behavior). val MCM_ORDER_DEPENDENT_LOADS = true val jal_opc = (0x6f).U val jalr_opc = (0x67).U def GetUop(inst: UInt): UInt = inst(6,0) def GetRd (inst: UInt): UInt = inst(RD_MSB,RD_LSB) def GetRs1(inst: UInt): UInt = inst(RS1_MSB,RS1_LSB) def ExpandRVC(inst: UInt)(implicit p: Parameters): UInt = { val rvc_exp = Module(new RVCExpander) rvc_exp.io.in := inst Mux(rvc_exp.io.rvc, rvc_exp.io.out.bits, inst) } // Note: Accepts only EXPANDED rvc instructions def ComputeBranchTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = { val b_imm32 = Cat(Fill(20,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) ((pc.asSInt + b_imm32.asSInt).asSInt & (-2).S).asUInt } // Note: Accepts only EXPANDED rvc instructions def ComputeJALTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = { val j_imm32 = Cat(Fill(12,inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) ((pc.asSInt + j_imm32.asSInt).asSInt & (-2).S).asUInt } // Note: Accepts only EXPANDED rvc instructions def GetCfiType(inst: UInt)(implicit p: Parameters): UInt = { val bdecode = Module(new boom.v3.exu.BranchDecode) bdecode.io.inst := inst bdecode.io.pc := 0.U bdecode.io.out.cfi_type } } /** * Mixin for exception cause constants */ trait ExcCauseConstants { // a memory disambigious misspeculation occurred val MINI_EXCEPTION_MEM_ORDERING = 16.U val MINI_EXCEPTION_CSR_REPLAY = 17.U require (!freechips.rocketchip.rocket.Causes.all.contains(16)) require (!freechips.rocketchip.rocket.Causes.all.contains(17)) } File issue-slot.scala: //****************************************************************************** // Copyright (c) 2015 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Issue Slot Logic //-------------------------------------------------------------------------- //------------------------------------------------------------------------------ // // Note: stores (and AMOs) are "broken down" into 2 uops, but stored within a single issue-slot. // TODO XXX make a separate issueSlot for MemoryIssueSlots, and only they break apart stores. // TODO Disable ldspec for FP queue. package boom.v3.exu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import boom.v3.common._ import boom.v3.util._ import FUConstants._ /** * IO bundle to interact with Issue slot * * @param numWakeupPorts number of wakeup ports for the slot */ class IssueSlotIO(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomBundle { val valid = Output(Bool()) val will_be_valid = Output(Bool()) // TODO code review, do we need this signal so explicitely? val request = Output(Bool()) val request_hp = Output(Bool()) val grant = Input(Bool()) val brupdate = Input(new BrUpdateInfo()) val kill = Input(Bool()) // pipeline flush val clear = Input(Bool()) // entry being moved elsewhere (not mutually exclusive with grant) val ldspec_miss = Input(Bool()) // Previous cycle's speculative load wakeup was mispredicted. val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new IqWakeup(maxPregSz)))) val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W))) val spec_ld_wakeup = Flipped(Vec(memWidth, Valid(UInt(width=maxPregSz.W)))) val in_uop = Flipped(Valid(new MicroOp())) // if valid, this WILL overwrite an entry! val out_uop = Output(new MicroOp()) // the updated slot uop; will be shifted upwards in a collasping queue. val uop = Output(new MicroOp()) // the current Slot's uop. Sent down the pipeline when issued. val debug = { val result = new Bundle { val p1 = Bool() val p2 = Bool() val p3 = Bool() val ppred = Bool() val state = UInt(width=2.W) } Output(result) } } /** * Single issue slot. Holds a uop within the issue queue * * @param numWakeupPorts number of wakeup ports */ class IssueSlot(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomModule with IssueUnitConstants { val io = IO(new IssueSlotIO(numWakeupPorts)) // slot invalid? // slot is valid, holding 1 uop // slot is valid, holds 2 uops (like a store) def is_invalid = state === s_invalid def is_valid = state =/= s_invalid val next_state = Wire(UInt()) // the next state of this slot (which might then get moved to a new slot) val next_uopc = Wire(UInt()) // the next uopc of this slot (which might then get moved to a new slot) val next_lrs1_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot) val next_lrs2_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot) val state = RegInit(s_invalid) val p1 = RegInit(false.B) val p2 = RegInit(false.B) val p3 = RegInit(false.B) val ppred = RegInit(false.B) // Poison if woken up by speculative load. // Poison lasts 1 cycle (as ldMiss will come on the next cycle). // SO if poisoned is true, set it to false! val p1_poisoned = RegInit(false.B) val p2_poisoned = RegInit(false.B) p1_poisoned := false.B p2_poisoned := false.B val next_p1_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned) val next_p2_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned) val slot_uop = RegInit(NullMicroOp) val next_uop = Mux(io.in_uop.valid, io.in_uop.bits, slot_uop) //----------------------------------------------------------------------------- // next slot state computation // compute the next state for THIS entry slot (in a collasping queue, the // current uop may get moved elsewhere, and a new uop can enter when (io.kill) { state := s_invalid } .elsewhen (io.in_uop.valid) { state := io.in_uop.bits.iw_state } .elsewhen (io.clear) { state := s_invalid } .otherwise { state := next_state } //----------------------------------------------------------------------------- // "update" state // compute the next state for the micro-op in this slot. This micro-op may // be moved elsewhere, so the "next_state" travels with it. // defaults next_state := state next_uopc := slot_uop.uopc next_lrs1_rtype := slot_uop.lrs1_rtype next_lrs2_rtype := slot_uop.lrs2_rtype when (io.kill) { next_state := s_invalid } .elsewhen ((io.grant && (state === s_valid_1)) || (io.grant && (state === s_valid_2) && p1 && p2 && ppred)) { // try to issue this uop. when (!(io.ldspec_miss && (p1_poisoned || p2_poisoned))) { next_state := s_invalid } } .elsewhen (io.grant && (state === s_valid_2)) { when (!(io.ldspec_miss && (p1_poisoned || p2_poisoned))) { next_state := s_valid_1 when (p1) { slot_uop.uopc := uopSTD next_uopc := uopSTD slot_uop.lrs1_rtype := RT_X next_lrs1_rtype := RT_X } .otherwise { slot_uop.lrs2_rtype := RT_X next_lrs2_rtype := RT_X } } } when (io.in_uop.valid) { slot_uop := io.in_uop.bits assert (is_invalid || io.clear || io.kill, "trying to overwrite a valid issue slot.") } // Wakeup Compare Logic // these signals are the "next_p*" for the current slot's micro-op. // they are important for shifting the current slot_uop up to an other entry. val next_p1 = WireInit(p1) val next_p2 = WireInit(p2) val next_p3 = WireInit(p3) val next_ppred = WireInit(ppred) when (io.in_uop.valid) { p1 := !(io.in_uop.bits.prs1_busy) p2 := !(io.in_uop.bits.prs2_busy) p3 := !(io.in_uop.bits.prs3_busy) ppred := !(io.in_uop.bits.ppred_busy) } when (io.ldspec_miss && next_p1_poisoned) { assert(next_uop.prs1 =/= 0.U, "Poison bit can't be set for prs1=x0!") p1 := false.B } when (io.ldspec_miss && next_p2_poisoned) { assert(next_uop.prs2 =/= 0.U, "Poison bit can't be set for prs2=x0!") p2 := false.B } for (i <- 0 until numWakeupPorts) { when (io.wakeup_ports(i).valid && (io.wakeup_ports(i).bits.pdst === next_uop.prs1)) { p1 := true.B } when (io.wakeup_ports(i).valid && (io.wakeup_ports(i).bits.pdst === next_uop.prs2)) { p2 := true.B } when (io.wakeup_ports(i).valid && (io.wakeup_ports(i).bits.pdst === next_uop.prs3)) { p3 := true.B } } when (io.pred_wakeup_port.valid && io.pred_wakeup_port.bits === next_uop.ppred) { ppred := true.B } for (w <- 0 until memWidth) { assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U), "Loads to x0 should never speculatively wakeup other instructions") } // TODO disable if FP IQ. for (w <- 0 until memWidth) { when (io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === next_uop.prs1 && next_uop.lrs1_rtype === RT_FIX) { p1 := true.B p1_poisoned := true.B assert (!next_p1_poisoned) } when (io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === next_uop.prs2 && next_uop.lrs2_rtype === RT_FIX) { p2 := true.B p2_poisoned := true.B assert (!next_p2_poisoned) } } // Handle branch misspeculations val next_br_mask = GetNewBrMask(io.brupdate, slot_uop) // was this micro-op killed by a branch? if yes, we can't let it be valid if // we compact it into an other entry when (IsKilledByBranch(io.brupdate, slot_uop)) { next_state := s_invalid } when (!io.in_uop.valid) { slot_uop.br_mask := next_br_mask } //------------------------------------------------------------- // Request Logic io.request := is_valid && p1 && p2 && p3 && ppred && !io.kill val high_priority = slot_uop.is_br || slot_uop.is_jal || slot_uop.is_jalr io.request_hp := io.request && high_priority when (state === s_valid_1) { io.request := p1 && p2 && p3 && ppred && !io.kill } .elsewhen (state === s_valid_2) { io.request := (p1 || p2) && ppred && !io.kill } .otherwise { io.request := false.B } //assign outputs io.valid := is_valid io.uop := slot_uop io.uop.iw_p1_poisoned := p1_poisoned io.uop.iw_p2_poisoned := p2_poisoned // micro-op will vacate due to grant. val may_vacate = io.grant && ((state === s_valid_1) || (state === s_valid_2) && p1 && p2 && ppred) val squash_grant = io.ldspec_miss && (p1_poisoned || p2_poisoned) io.will_be_valid := is_valid && !(may_vacate && !squash_grant) io.out_uop := slot_uop io.out_uop.iw_state := next_state io.out_uop.uopc := next_uopc io.out_uop.lrs1_rtype := next_lrs1_rtype io.out_uop.lrs2_rtype := next_lrs2_rtype io.out_uop.br_mask := next_br_mask io.out_uop.prs1_busy := !p1 io.out_uop.prs2_busy := !p2 io.out_uop.prs3_busy := !p3 io.out_uop.ppred_busy := !ppred io.out_uop.iw_p1_poisoned := p1_poisoned io.out_uop.iw_p2_poisoned := p2_poisoned when (state === s_valid_2) { when (p1 && p2 && ppred) { ; // send out the entire instruction as one uop } .elsewhen (p1 && ppred) { io.uop.uopc := slot_uop.uopc io.uop.lrs2_rtype := RT_X } .elsewhen (p2 && ppred) { io.uop.uopc := uopSTD io.uop.lrs1_rtype := RT_X } } // debug outputs io.debug.p1 := p1 io.debug.p2 := p2 io.debug.p3 := p3 io.debug.ppred := ppred io.debug.state := state }

module IssueSlot_15( // @[issue-slot.scala:69:7] input clock, // @[issue-slot.scala:69:7] input reset, // @[issue-slot.scala:69:7] output io_valid, // @[issue-slot.scala:73:14] output io_will_be_valid, // @[issue-slot.scala:73:14] output io_request, // @[issue-slot.scala:73:14] output io_request_hp, // @[issue-slot.scala:73:14] input io_grant, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14] input io_brupdate_b2_valid, // @[issue-slot.scala:73:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14] input io_brupdate_b2_taken, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14] input io_kill, // @[issue-slot.scala:73:14] input io_clear, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14] input io_in_uop_valid, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14] input io_in_uop_bits_taken, // @[issue-slot.scala:73:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14] input io_in_uop_bits_exception, // @[issue-slot.scala:73:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14] input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14] output io_out_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14] output io_out_uop_is_br, // @[issue-slot.scala:73:14] output io_out_uop_is_jalr, // @[issue-slot.scala:73:14] output io_out_uop_is_jal, // @[issue-slot.scala:73:14] output io_out_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_out_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14] output io_out_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:73:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_out_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14] output io_out_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14] output io_out_uop_mem_signed, // @[issue-slot.scala:73:14] output io_out_uop_is_fence, // @[issue-slot.scala:73:14] output io_out_uop_is_fencei, // @[issue-slot.scala:73:14] output io_out_uop_is_amo, // @[issue-slot.scala:73:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_out_uop_uses_stq, // @[issue-slot.scala:73:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_out_uop_is_unique, // @[issue-slot.scala:73:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14] output io_out_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_out_uop_frs3_en, // @[issue-slot.scala:73:14] output io_out_uop_fp_val, // @[issue-slot.scala:73:14] output io_out_uop_fp_single, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14] output io_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14] output io_uop_is_br, // @[issue-slot.scala:73:14] output io_uop_is_jalr, // @[issue-slot.scala:73:14] output io_uop_is_jal, // @[issue-slot.scala:73:14] output io_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14] output io_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_uop_ppred, // @[issue-slot.scala:73:14] output io_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14] output io_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14] output io_uop_mem_signed, // @[issue-slot.scala:73:14] output io_uop_is_fence, // @[issue-slot.scala:73:14] output io_uop_is_fencei, // @[issue-slot.scala:73:14] output io_uop_is_amo, // @[issue-slot.scala:73:14] output io_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_uop_uses_stq, // @[issue-slot.scala:73:14] output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_uop_is_unique, // @[issue-slot.scala:73:14] output io_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14] output io_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_uop_frs3_en, // @[issue-slot.scala:73:14] output io_uop_fp_val, // @[issue-slot.scala:73:14] output io_uop_fp_single, // @[issue-slot.scala:73:14] output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14] output io_debug_p1, // @[issue-slot.scala:73:14] output io_debug_p2, // @[issue-slot.scala:73:14] output io_debug_p3, // @[issue-slot.scala:73:14] output io_debug_ppred, // @[issue-slot.scala:73:14] output [1:0] io_debug_state // @[issue-slot.scala:73:14] ); wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7] wire io_ldspec_miss = 1'h0; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_bits_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_bits_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7] wire io_spec_ld_wakeup_0_valid = 1'h0; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_uop_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_uop_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire next_p1_poisoned = 1'h0; // @[issue-slot.scala:99:29] wire next_p2_poisoned = 1'h0; // @[issue-slot.scala:100:29] wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire _squash_grant_T = 1'h0; // @[issue-slot.scala:261:53] wire squash_grant = 1'h0; // @[issue-slot.scala:261:37] wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:69:7] wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [6:0] io_spec_ld_wakeup_0_bits = 7'h0; // @[issue-slot.scala:69:7] wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19] wire _io_will_be_valid_T_1 = 1'h1; // @[issue-slot.scala:262:51] wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [15:0] slot_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19] wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire _io_valid_T; // @[issue-slot.scala:79:24] wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32] wire _io_request_hp_T; // @[issue-slot.scala:243:31] wire [6:0] next_uopc; // @[issue-slot.scala:82:29] wire [1:0] next_state; // @[issue-slot.scala:81:29] wire [15:0] next_br_mask; // @[util.scala:85:25] wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28] wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28] wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28] wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28] wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29] wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29] wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_out_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_out_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire io_debug_p1_0; // @[issue-slot.scala:69:7] wire io_debug_p2_0; // @[issue-slot.scala:69:7] wire io_debug_p3_0; // @[issue-slot.scala:69:7] wire io_debug_ppred_0; // @[issue-slot.scala:69:7] wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7] wire io_valid_0; // @[issue-slot.scala:69:7] wire io_will_be_valid_0; // @[issue-slot.scala:69:7] wire io_request_0; // @[issue-slot.scala:69:7] wire io_request_hp_0; // @[issue-slot.scala:69:7] assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29] assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29] assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29] assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29] reg [1:0] state; // @[issue-slot.scala:86:22] assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22] reg p1; // @[issue-slot.scala:87:22] assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22] wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25] reg p2; // @[issue-slot.scala:88:22] assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22] wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25] reg p3; // @[issue-slot.scala:89:22] assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22] wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25] reg ppred; // @[issue-slot.scala:90:22] assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22] wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28] reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25] reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25] assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25] assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_rvc; // @[issue-slot.scala:102:25] assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25] assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25] assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25] assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_is_br; // @[issue-slot.scala:102:25] assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jalr; // @[issue-slot.scala:102:25] assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jal; // @[issue-slot.scala:102:25] assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sfb; // @[issue-slot.scala:102:25] assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:102:25] assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:102:25] assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_edge_inst; // @[issue-slot.scala:102:25] assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25] assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_taken; // @[issue-slot.scala:102:25] assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25] assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25] assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:102:25] assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:102:25] assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:102:25] assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:102:25] assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25] assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25] assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25] assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25] assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_exception; // @[issue-slot.scala:102:25] assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25] assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bypassable; // @[issue-slot.scala:102:25] assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25] assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_mem_signed; // @[issue-slot.scala:102:25] assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fence; // @[issue-slot.scala:102:25] assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fencei; // @[issue-slot.scala:102:25] assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_amo; // @[issue-slot.scala:102:25] assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_stq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25] assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_unique; // @[issue-slot.scala:102:25] assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25] assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25] assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25] assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25] assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_val; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25] assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25] reg slot_uop_frs3_en; // @[issue-slot.scala:102:25] assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_val; // @[issue-slot.scala:102:25] assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_single; // @[issue-slot.scala:102:25] assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p1_poisoned = ~io_in_uop_valid_0 & slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p2_poisoned = ~io_in_uop_valid_0 & slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [15:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25] wire _T_7 = io_grant_0 & state == 2'h1 | io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}] wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25] wire _GEN = io_kill_0 | _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51] wire _GEN_0 = _GEN | ~(_T_12 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:62, :142:17, :143:23] assign next_uopc = _GEN_0 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51] assign next_lrs1_rtype = _GEN_0 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51] wire _GEN_1 = _GEN | ~_T_12 | p1; // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:62, :142:17] assign next_lrs2_rtype = _GEN_1 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17]

Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File BusBypass.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.devices.tilelink import chisel3._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ abstract class TLBusBypassBase(beatBytes: Int, deadlock: Boolean = false, bufferError: Boolean = true, maxAtomic: Int = 16, maxTransfer: Int = 4096) (implicit p: Parameters) extends LazyModule { protected val nodeIn = TLIdentityNode() protected val nodeOut = TLIdentityNode() val node = NodeHandle(nodeIn, nodeOut) protected val bar = LazyModule(new TLBusBypassBar(dFn = { mp => mp.v1copy(managers = mp.managers.map { m => m.v1copy( mayDenyPut = m.mayDenyPut || !deadlock, mayDenyGet = m.mayDenyGet || !deadlock) }) })) protected val everything = Seq(AddressSet(0, BigInt("ffffffffffffffffffffffffffffffff", 16))) // 128-bit protected val params = DevNullParams(everything, maxAtomic, maxTransfer, region=RegionType.TRACKED) protected val error = if (deadlock) LazyModule(new TLDeadlock(params, beatBytes)) else LazyModule(new TLError(params, bufferError, beatBytes)) // order matters because the parameters and bypass // assume that the non-bypassed connection is // the last connection to the bar, so keep nodeOut last. bar.node := nodeIn error.node := bar.node nodeOut := bar.node } class TLBusBypass(beatBytes: Int, bufferError: Boolean = false, maxAtomic: Int = 16, maxTransfer: Int = 4096)(implicit p: Parameters) extends TLBusBypassBase(beatBytes, deadlock = false, bufferError = bufferError, maxAtomic = maxAtomic, maxTransfer = maxTransfer) { lazy val module = new Impl class Impl extends LazyModuleImp(this) { val io = IO(new Bundle { val bypass = Input(Bool()) }) bar.module.io.bypass := io.bypass } } class TLBypassNode(dFn: TLSlavePortParameters => TLSlavePortParameters)(implicit valName: ValName) extends TLCustomNode { def resolveStar(iKnown: Int, oKnown: Int, iStars: Int, oStars: Int): (Int, Int) = { require (iStars == 0 && oStars == 0, "TLBypass node does not support :=* or :*=") require (iKnown == 1, "TLBypass node expects exactly one input") require (oKnown == 2, "TLBypass node expects exactly two outputs") (0, 0) } def mapParamsD(n: Int, p: Seq[TLMasterPortParameters]): Seq[TLMasterPortParameters] = { p ++ p } def mapParamsU(n: Int, p: Seq[TLSlavePortParameters]): Seq[TLSlavePortParameters] = { Seq(dFn(p.last).v1copy(minLatency = p.map(_.minLatency).min))} } class TLBusBypassBar(dFn: TLSlavePortParameters => TLSlavePortParameters)(implicit p: Parameters) extends LazyModule { val node = new TLBypassNode(dFn) lazy val module = new Impl class Impl extends LazyModuleImp(this) { val io = IO(new Bundle { val bypass = Input(Bool()) val pending = Output(Bool()) }) val (in, edgeIn) = node.in(0) val Seq((out0, edgeOut0), (out1, edgeOut1)) = node.out require (edgeOut0.manager.beatBytes == edgeOut1.manager.beatBytes, s"BusBypass slave device widths mismatch (${edgeOut0.manager.managers.map(_.name)} has ${edgeOut0.manager.beatBytes}B vs ${edgeOut1.manager.managers.map(_.name)} has ${edgeOut1.manager.beatBytes}B)") // We need to be locked to the given bypass direction until all transactions stop val in_reset = RegNext(false.B, init = true.B) val bypass_reg = Reg(Bool()) val bypass = Mux(in_reset, io.bypass, bypass_reg) val (flight, next_flight) = edgeIn.inFlight(in) io.pending := (flight > 0.U) when (in_reset || (next_flight === 0.U)) { bypass_reg := io.bypass } val stall = (bypass =/= io.bypass) && edgeIn.first(in.a) out0.a.valid := !stall && in.a.valid && bypass out1.a.valid := !stall && in.a.valid && !bypass in.a.ready := !stall && Mux(bypass, out0.a.ready, out1.a.ready) out0.a.bits := in.a.bits out1.a.bits := in.a.bits out0.d.ready := in.d.ready && bypass out1.d.ready := in.d.ready && !bypass in.d.valid := Mux(bypass, out0.d.valid, out1.d.valid) def cast(x: TLBundleD) = { val out = WireDefault(in.d.bits); out <> x; out } in.d.bits := Mux(bypass, cast(out0.d.bits), cast(out1.d.bits)) if (edgeIn.manager.anySupportAcquireB && edgeIn.client.anySupportProbe) { out0.b.ready := in.b.ready && bypass out1.b.ready := in.b.ready && !bypass in.b.valid := Mux(bypass, out0.b.valid, out1.b.valid) def cast(x: TLBundleB) = { val out = Wire(in.b.bits); out <> x; out } in.b.bits := Mux(bypass, cast(out0.b.bits), cast(out1.b.bits)) out0.c.valid := in.c.valid && bypass out1.c.valid := in.c.valid && !bypass in.c.ready := Mux(bypass, out0.c.ready, out1.c.ready) out0.c.bits := in.c.bits out1.c.bits := in.c.bits out0.e.valid := in.e.valid && bypass out1.e.valid := in.e.valid && !bypass in.e.ready := Mux(bypass, out0.e.ready, out1.e.ready) out0.e.bits := in.e.bits out1.e.bits := in.e.bits } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out0.b.ready := true.B out0.c.valid := false.B out0.e.valid := false.B out1.b.ready := true.B out1.c.valid := false.B out1.e.valid := false.B } } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module TLBusBypassBar( // @[BusBypass.scala:66:9] input clock, // @[BusBypass.scala:66:9] input reset, // @[BusBypass.scala:66:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [8:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [31:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_1_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_1_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [8:0] auto_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_1_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_1_d_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [31:0] auto_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_0_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_0_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [127:0] auto_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_0_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_0_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_0_d_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25] input auto_out_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] input auto_out_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input io_bypass // @[BusBypass.scala:67:16] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[BusBypass.scala:66:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[BusBypass.scala:66:9] wire [8:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[BusBypass.scala:66:9] wire [31:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[BusBypass.scala:66:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[BusBypass.scala:66:9] wire auto_out_1_a_ready_0 = auto_out_1_a_ready; // @[BusBypass.scala:66:9] wire auto_out_1_d_valid_0 = auto_out_1_d_valid; // @[BusBypass.scala:66:9] wire [2:0] auto_out_1_d_bits_opcode_0 = auto_out_1_d_bits_opcode; // @[BusBypass.scala:66:9] wire [1:0] auto_out_1_d_bits_param_0 = auto_out_1_d_bits_param; // @[BusBypass.scala:66:9] wire [1:0] auto_out_1_d_bits_size_0 = auto_out_1_d_bits_size; // @[BusBypass.scala:66:9] wire auto_out_1_d_bits_source_0 = auto_out_1_d_bits_source; // @[BusBypass.scala:66:9] wire auto_out_1_d_bits_sink_0 = auto_out_1_d_bits_sink; // @[BusBypass.scala:66:9] wire auto_out_1_d_bits_denied_0 = auto_out_1_d_bits_denied; // @[BusBypass.scala:66:9] wire [31:0] auto_out_1_d_bits_data_0 = auto_out_1_d_bits_data; // @[BusBypass.scala:66:9] wire auto_out_1_d_bits_corrupt_0 = auto_out_1_d_bits_corrupt; // @[BusBypass.scala:66:9] wire auto_out_0_a_ready_0 = auto_out_0_a_ready; // @[BusBypass.scala:66:9] wire auto_out_0_d_valid_0 = auto_out_0_d_valid; // @[BusBypass.scala:66:9] wire [2:0] auto_out_0_d_bits_opcode_0 = auto_out_0_d_bits_opcode; // @[BusBypass.scala:66:9] wire [1:0] auto_out_0_d_bits_param_0 = auto_out_0_d_bits_param; // @[BusBypass.scala:66:9] wire [1:0] auto_out_0_d_bits_size_0 = auto_out_0_d_bits_size; // @[BusBypass.scala:66:9] wire auto_out_0_d_bits_denied_0 = auto_out_0_d_bits_denied; // @[BusBypass.scala:66:9] wire auto_out_0_d_bits_corrupt_0 = auto_out_0_d_bits_corrupt; // @[BusBypass.scala:66:9] wire io_bypass_0 = io_bypass; // @[BusBypass.scala:66:9] wire [4:0] _r_beats1_decode_T_3 = 5'h3; // @[package.scala:243:71] wire [4:0] _r_beats1_decode_T_6 = 5'h3; // @[package.scala:243:71] wire [3:0] _b_inc_WIRE_bits_mask = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _b_inc_WIRE_1_bits_mask = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _b_dec_WIRE_bits_mask = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _b_dec_WIRE_1_bits_mask = 4'h0; // @[Bundles.scala:264:61] wire [8:0] _b_inc_WIRE_bits_address = 9'h0; // @[Bundles.scala:264:74] wire [8:0] _b_inc_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:264:61] wire [8:0] _c_inc_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_inc_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _b_dec_WIRE_bits_address = 9'h0; // @[Bundles.scala:264:74] wire [8:0] _b_dec_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:264:61] wire [8:0] _c_dec_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_dec_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [4:0] _r_beats1_decode_T = 5'hC; // @[package.scala:243:71] wire [4:0] _stall_beats1_decode_T = 5'hC; // @[package.scala:243:71] wire [1:0] _r_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _r_beats1_decode_T_5 = 2'h0; // @[package.scala:243:46] wire [1:0] _r_beats1_decode_T_8 = 2'h0; // @[package.scala:243:46] wire [1:0] _b_inc_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _b_inc_WIRE_bits_size = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _b_inc_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _b_inc_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _c_inc_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_inc_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _b_dec_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _b_dec_WIRE_bits_size = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _b_dec_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _b_dec_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _c_dec_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_dec_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _stall_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76] wire [31:0] auto_out_0_d_bits_data = 32'h0; // @[BusBypass.scala:66:9] wire [31:0] nodeOut_d_bits_data = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] _b_inc_WIRE_bits_data = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _b_inc_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _c_inc_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_inc_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _b_dec_WIRE_bits_data = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _b_dec_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _c_dec_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_dec_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] nodeIn_d_bits_out_data = 32'h0; // @[BusBypass.scala:97:53] wire [3:0] auto_in_a_bits_mask = 4'hF; // @[Nodes.scala:27:25] wire [3:0] auto_out_1_a_bits_mask = 4'hF; // @[Nodes.scala:27:25] wire [3:0] auto_out_0_a_bits_mask = 4'hF; // @[Nodes.scala:27:25] wire [3:0] nodeIn_a_bits_mask = 4'hF; // @[Nodes.scala:27:25] wire [3:0] nodeOut_a_bits_mask = 4'hF; // @[Nodes.scala:27:25] wire [3:0] x1_nodeOut_a_bits_mask = 4'hF; // @[Nodes.scala:27:25] wire [1:0] auto_in_a_bits_size = 2'h2; // @[Nodes.scala:27:25] wire [1:0] auto_out_1_a_bits_size = 2'h2; // @[Nodes.scala:27:25] wire [1:0] auto_out_0_a_bits_size = 2'h2; // @[Nodes.scala:27:25] wire [1:0] nodeIn_a_bits_size = 2'h2; // @[Nodes.scala:27:25] wire [1:0] nodeOut_a_bits_size = 2'h2; // @[Nodes.scala:27:25] wire [1:0] x1_nodeOut_a_bits_size = 2'h2; // @[Nodes.scala:27:25] wire [2:0] auto_in_a_bits_param = 3'h0; // @[BusBypass.scala:66:9] wire [2:0] auto_out_1_a_bits_param = 3'h0; // @[BusBypass.scala:66:9] wire [2:0] auto_out_0_a_bits_param = 3'h0; // @[BusBypass.scala:66:9] wire [2:0] nodeIn_a_bits_param = 3'h0; // @[MixedNode.scala:551:17] wire [2:0] nodeOut_a_bits_param = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_a_bits_param = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] _b_inc_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _b_inc_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _c_inc_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_inc_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_inc_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_inc_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _b_dec_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _b_dec_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _c_dec_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_dec_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_dec_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_dec_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [1:0] _r_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46] wire [1:0] _r_beats1_decode_T_4 = 2'h3; // @[package.scala:243:76] wire [1:0] _r_counter1_T_1 = 2'h3; // @[Edges.scala:230:28] wire [1:0] _r_beats1_decode_T_7 = 2'h3; // @[package.scala:243:76] wire [1:0] _r_counter1_T_2 = 2'h3; // @[Edges.scala:230:28] wire [1:0] _r_counter1_T_4 = 2'h3; // @[Edges.scala:230:28] wire [1:0] _stall_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46] wire _r_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_last = 1'h1; // @[Edges.scala:232:33] wire r_beats1_opdata_1 = 1'h1; // @[Edges.scala:97:28] wire r_counter1_1 = 1'h1; // @[Edges.scala:230:28] wire b_first = 1'h1; // @[Edges.scala:231:25] wire _r_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire b_last = 1'h1; // @[Edges.scala:232:33] wire r_counter1_2 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _r_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire c_last = 1'h1; // @[Edges.scala:232:33] wire _r_last_T_7 = 1'h1; // @[Edges.scala:232:43] wire d_last = 1'h1; // @[Edges.scala:232:33] wire r_counter1_4 = 1'h1; // @[Edges.scala:230:28] wire e_first = 1'h1; // @[Edges.scala:231:25] wire _r_last_T_9 = 1'h1; // @[Edges.scala:232:43] wire e_last = 1'h1; // @[Edges.scala:232:33] wire c_response = 1'h1; // @[Edges.scala:82:41] wire _stall_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire stall_last = 1'h1; // @[Edges.scala:232:33] wire auto_in_a_bits_source = 1'h0; // @[BusBypass.scala:66:9] wire auto_in_a_bits_corrupt = 1'h0; // @[BusBypass.scala:66:9] wire auto_out_1_a_bits_source = 1'h0; // @[BusBypass.scala:66:9] wire auto_out_1_a_bits_corrupt = 1'h0; // @[BusBypass.scala:66:9] wire auto_out_0_a_bits_source = 1'h0; // @[BusBypass.scala:66:9] wire auto_out_0_a_bits_corrupt = 1'h0; // @[BusBypass.scala:66:9] wire auto_out_0_d_bits_source = 1'h0; // @[BusBypass.scala:66:9] wire auto_out_0_d_bits_sink = 1'h0; // @[BusBypass.scala:66:9] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire nodeOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_d_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17] wire x1_nodeOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire x1_nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire r_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire r_beats1 = 1'h0; // @[Edges.scala:221:14] wire r_4 = 1'h0; // @[Edges.scala:234:25] wire r_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire _r_beats1_opdata_T_1 = 1'h0; // @[Edges.scala:97:37] wire r_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire _r_last_T_2 = 1'h0; // @[Edges.scala:232:25] wire r_3_1 = 1'h0; // @[Edges.scala:233:22] wire _r_count_T_1 = 1'h0; // @[Edges.scala:234:27] wire r_4_1 = 1'h0; // @[Edges.scala:234:25] wire _r_counter_T_1 = 1'h0; // @[Edges.scala:236:21] wire r_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire r_beats1_opdata_2 = 1'h0; // @[Edges.scala:102:36] wire r_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire _r_last_T_4 = 1'h0; // @[Edges.scala:232:25] wire r_3_2 = 1'h0; // @[Edges.scala:233:22] wire _r_count_T_2 = 1'h0; // @[Edges.scala:234:27] wire r_4_2 = 1'h0; // @[Edges.scala:234:25] wire _r_counter_T_2 = 1'h0; // @[Edges.scala:236:21] wire r_beats1_decode_3 = 1'h0; // @[Edges.scala:220:59] wire r_beats1_3 = 1'h0; // @[Edges.scala:221:14] wire r_4_3 = 1'h0; // @[Edges.scala:234:25] wire _r_last_T_8 = 1'h0; // @[Edges.scala:232:25] wire r_3_4 = 1'h0; // @[Edges.scala:233:22] wire _r_count_T_4 = 1'h0; // @[Edges.scala:234:27] wire r_4_4 = 1'h0; // @[Edges.scala:234:25] wire _r_counter_T_4 = 1'h0; // @[Edges.scala:236:21] wire c_request = 1'h0; // @[Edges.scala:68:40] wire _b_inc_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _b_inc_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _b_inc_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74] wire _b_inc_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _b_inc_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _b_inc_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _b_inc_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:264:61] wire _b_inc_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _b_inc_T = 1'h0; // @[Decoupled.scala:51:35] wire _b_inc_T_1 = 1'h0; // @[Edges.scala:311:26] wire b_inc = 1'h0; // @[Edges.scala:311:37] wire _c_inc_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_inc_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_inc_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_inc_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_inc_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_inc_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_inc_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_inc_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_inc_T = 1'h0; // @[Decoupled.scala:51:35] wire _c_inc_T_1 = 1'h0; // @[Edges.scala:312:26] wire c_inc = 1'h0; // @[Edges.scala:312:37] wire _e_inc_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _e_inc_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _e_inc_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _e_inc_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _e_inc_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _e_inc_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _e_inc_T = 1'h0; // @[Decoupled.scala:51:35] wire _e_inc_T_1 = 1'h0; // @[Edges.scala:314:26] wire e_inc = 1'h0; // @[Edges.scala:314:37] wire a_dec = 1'h0; // @[Edges.scala:317:36] wire _b_dec_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _b_dec_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _b_dec_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74] wire _b_dec_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _b_dec_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _b_dec_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _b_dec_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:264:61] wire _b_dec_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _b_dec_T = 1'h0; // @[Decoupled.scala:51:35] wire _b_dec_T_1 = 1'h0; // @[Edges.scala:318:26] wire b_dec = 1'h0; // @[Edges.scala:318:36] wire _c_dec_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_dec_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_dec_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_dec_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_dec_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_dec_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_dec_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_dec_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_dec_T = 1'h0; // @[Decoupled.scala:51:35] wire _c_dec_T_1 = 1'h0; // @[Edges.scala:319:26] wire c_dec = 1'h0; // @[Edges.scala:319:36] wire _e_dec_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _e_dec_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _e_dec_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _e_dec_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _e_dec_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _e_dec_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _e_dec_T = 1'h0; // @[Decoupled.scala:51:35] wire _e_dec_T_1 = 1'h0; // @[Edges.scala:321:26] wire e_dec = 1'h0; // @[Edges.scala:321:36] wire stall_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire stall_beats1 = 1'h0; // @[Edges.scala:221:14] wire stall_count = 1'h0; // @[Edges.scala:234:25] wire nodeIn_d_bits_out_source = 1'h0; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_sink = 1'h0; // @[BusBypass.scala:97:53] wire nodeIn_a_valid = auto_in_a_valid_0; // @[BusBypass.scala:66:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[BusBypass.scala:66:9] wire [8:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[BusBypass.scala:66:9] wire [31:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[BusBypass.scala:66:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[BusBypass.scala:66:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [31:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire x1_nodeOut_a_ready = auto_out_1_a_ready_0; // @[BusBypass.scala:66:9] wire x1_nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [8:0] x1_nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] x1_nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire x1_nodeOut_d_ready; // @[MixedNode.scala:542:17] wire x1_nodeOut_d_valid = auto_out_1_d_valid_0; // @[BusBypass.scala:66:9] wire [2:0] x1_nodeOut_d_bits_opcode = auto_out_1_d_bits_opcode_0; // @[BusBypass.scala:66:9] wire [1:0] x1_nodeOut_d_bits_param = auto_out_1_d_bits_param_0; // @[BusBypass.scala:66:9] wire [1:0] x1_nodeOut_d_bits_size = auto_out_1_d_bits_size_0; // @[BusBypass.scala:66:9] wire x1_nodeOut_d_bits_source = auto_out_1_d_bits_source_0; // @[BusBypass.scala:66:9] wire x1_nodeOut_d_bits_sink = auto_out_1_d_bits_sink_0; // @[BusBypass.scala:66:9] wire x1_nodeOut_d_bits_denied = auto_out_1_d_bits_denied_0; // @[BusBypass.scala:66:9] wire [31:0] x1_nodeOut_d_bits_data = auto_out_1_d_bits_data_0; // @[BusBypass.scala:66:9] wire x1_nodeOut_d_bits_corrupt = auto_out_1_d_bits_corrupt_0; // @[BusBypass.scala:66:9] wire nodeOut_a_ready = auto_out_0_a_ready_0; // @[BusBypass.scala:66:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [127:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_0_d_valid_0; // @[BusBypass.scala:66:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_0_d_bits_opcode_0; // @[BusBypass.scala:66:9] wire [1:0] nodeOut_d_bits_param = auto_out_0_d_bits_param_0; // @[BusBypass.scala:66:9] wire [1:0] nodeOut_d_bits_size = auto_out_0_d_bits_size_0; // @[BusBypass.scala:66:9] wire nodeOut_d_bits_denied = auto_out_0_d_bits_denied_0; // @[BusBypass.scala:66:9] wire nodeOut_d_bits_corrupt = auto_out_0_d_bits_corrupt_0; // @[BusBypass.scala:66:9] wire _io_pending_T; // @[BusBypass.scala:84:27] wire auto_in_a_ready_0; // @[BusBypass.scala:66:9] wire [2:0] auto_in_d_bits_opcode_0; // @[BusBypass.scala:66:9] wire [1:0] auto_in_d_bits_param_0; // @[BusBypass.scala:66:9] wire [1:0] auto_in_d_bits_size_0; // @[BusBypass.scala:66:9] wire auto_in_d_bits_source_0; // @[BusBypass.scala:66:9] wire auto_in_d_bits_sink_0; // @[BusBypass.scala:66:9] wire auto_in_d_bits_denied_0; // @[BusBypass.scala:66:9] wire [31:0] auto_in_d_bits_data_0; // @[BusBypass.scala:66:9] wire auto_in_d_bits_corrupt_0; // @[BusBypass.scala:66:9] wire auto_in_d_valid_0; // @[BusBypass.scala:66:9] wire [2:0] auto_out_1_a_bits_opcode_0; // @[BusBypass.scala:66:9] wire [8:0] auto_out_1_a_bits_address_0; // @[BusBypass.scala:66:9] wire [31:0] auto_out_1_a_bits_data_0; // @[BusBypass.scala:66:9] wire auto_out_1_a_valid_0; // @[BusBypass.scala:66:9] wire auto_out_1_d_ready_0; // @[BusBypass.scala:66:9] wire [2:0] auto_out_0_a_bits_opcode_0; // @[BusBypass.scala:66:9] wire [127:0] auto_out_0_a_bits_address_0; // @[BusBypass.scala:66:9] wire [31:0] auto_out_0_a_bits_data_0; // @[BusBypass.scala:66:9] wire auto_out_0_a_valid_0; // @[BusBypass.scala:66:9] wire auto_out_0_d_ready_0; // @[BusBypass.scala:66:9] wire io_pending; // @[BusBypass.scala:66:9] wire _nodeIn_a_ready_T_2; // @[BusBypass.scala:90:28] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[BusBypass.scala:66:9] assign nodeOut_a_bits_opcode = nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_nodeOut_a_bits_opcode = nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_nodeOut_a_bits_address = nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_data = nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign x1_nodeOut_a_bits_data = nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] wire _nodeIn_d_valid_T; // @[BusBypass.scala:96:24] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[BusBypass.scala:66:9] wire [2:0] _nodeIn_d_bits_T_opcode; // @[BusBypass.scala:98:21] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[BusBypass.scala:66:9] wire [1:0] _nodeIn_d_bits_T_param; // @[BusBypass.scala:98:21] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[BusBypass.scala:66:9] wire [1:0] _nodeIn_d_bits_T_size; // @[BusBypass.scala:98:21] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[BusBypass.scala:66:9] wire _nodeIn_d_bits_T_source; // @[BusBypass.scala:98:21] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[BusBypass.scala:66:9] wire _nodeIn_d_bits_T_sink; // @[BusBypass.scala:98:21] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[BusBypass.scala:66:9] wire _nodeIn_d_bits_T_denied; // @[BusBypass.scala:98:21] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[BusBypass.scala:66:9] wire [31:0] _nodeIn_d_bits_T_data; // @[BusBypass.scala:98:21] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[BusBypass.scala:66:9] wire _nodeIn_d_bits_T_corrupt; // @[BusBypass.scala:98:21] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[BusBypass.scala:66:9] wire _nodeOut_a_valid_T_2; // @[BusBypass.scala:88:42] assign auto_out_0_a_valid_0 = nodeOut_a_valid; // @[BusBypass.scala:66:9] assign auto_out_0_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[BusBypass.scala:66:9] assign auto_out_0_a_bits_address_0 = nodeOut_a_bits_address; // @[BusBypass.scala:66:9] assign auto_out_0_a_bits_data_0 = nodeOut_a_bits_data; // @[BusBypass.scala:66:9] wire _nodeOut_d_ready_T; // @[BusBypass.scala:94:32] assign auto_out_0_d_ready_0 = nodeOut_d_ready; // @[BusBypass.scala:66:9] wire [2:0] nodeIn_d_bits_out_opcode = nodeOut_d_bits_opcode; // @[BusBypass.scala:97:53] wire [1:0] nodeIn_d_bits_out_param = nodeOut_d_bits_param; // @[BusBypass.scala:97:53] wire [1:0] nodeIn_d_bits_out_size = nodeOut_d_bits_size; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_denied = nodeOut_d_bits_denied; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_corrupt = nodeOut_d_bits_corrupt; // @[BusBypass.scala:97:53] wire _nodeOut_a_valid_T_6; // @[BusBypass.scala:89:42] assign auto_out_1_a_valid_0 = x1_nodeOut_a_valid; // @[BusBypass.scala:66:9] assign auto_out_1_a_bits_opcode_0 = x1_nodeOut_a_bits_opcode; // @[BusBypass.scala:66:9] assign auto_out_1_a_bits_address_0 = x1_nodeOut_a_bits_address; // @[BusBypass.scala:66:9] assign auto_out_1_a_bits_data_0 = x1_nodeOut_a_bits_data; // @[BusBypass.scala:66:9] wire _nodeOut_d_ready_T_2; // @[BusBypass.scala:95:32] assign auto_out_1_d_ready_0 = x1_nodeOut_d_ready; // @[BusBypass.scala:66:9] wire [2:0] nodeIn_d_bits_out_1_opcode = x1_nodeOut_d_bits_opcode; // @[BusBypass.scala:97:53] wire [1:0] nodeIn_d_bits_out_1_param = x1_nodeOut_d_bits_param; // @[BusBypass.scala:97:53] wire [1:0] nodeIn_d_bits_out_1_size = x1_nodeOut_d_bits_size; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_1_source = x1_nodeOut_d_bits_source; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_1_sink = x1_nodeOut_d_bits_sink; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_1_denied = x1_nodeOut_d_bits_denied; // @[BusBypass.scala:97:53] wire [31:0] nodeIn_d_bits_out_1_data = x1_nodeOut_d_bits_data; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_1_corrupt = x1_nodeOut_d_bits_corrupt; // @[BusBypass.scala:97:53] reg in_reset; // @[BusBypass.scala:79:27] reg bypass_reg; // @[BusBypass.scala:80:25] wire bypass = in_reset ? io_bypass_0 : bypass_reg; // @[BusBypass.scala:66:9, :79:27, :80:25, :81:21] reg [1:0] flight; // @[Edges.scala:295:25] wire _T = nodeIn_a_ready & nodeIn_a_valid; // @[Decoupled.scala:51:35] wire r_3; // @[Edges.scala:233:22] assign r_3 = _T; // @[Decoupled.scala:51:35] wire _a_inc_T; // @[Decoupled.scala:51:35] assign _a_inc_T = _T; // @[Decoupled.scala:51:35] wire _a_dec_T; // @[Decoupled.scala:51:35] assign _a_dec_T = _T; // @[Decoupled.scala:51:35] wire _stall_T_1; // @[Decoupled.scala:51:35] assign _stall_T_1 = _T; // @[Decoupled.scala:51:35] wire _r_beats1_opdata_T = nodeIn_a_bits_opcode[2]; // @[Edges.scala:92:37] wire _stall_beats1_opdata_T = nodeIn_a_bits_opcode[2]; // @[Edges.scala:92:37] wire r_beats1_opdata = ~_r_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg r_counter; // @[Edges.scala:229:27] wire _r_last_T = r_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _r_counter1_T = {1'h0, r_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire r_counter1 = _r_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~r_counter; // @[Edges.scala:229:27, :231:25] wire _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27] wire _r_counter_T = ~a_first & r_counter1; // @[Edges.scala:230:28, :231:25, :236:21] wire _T_3 = nodeIn_d_ready & nodeIn_d_valid; // @[Decoupled.scala:51:35] wire r_3_3; // @[Edges.scala:233:22] assign r_3_3 = _T_3; // @[Decoupled.scala:51:35] wire _d_inc_T; // @[Decoupled.scala:51:35] assign _d_inc_T = _T_3; // @[Decoupled.scala:51:35] wire _d_dec_T; // @[Decoupled.scala:51:35] assign _d_dec_T = _T_3; // @[Decoupled.scala:51:35] wire [4:0] _r_beats1_decode_T_9 = 5'h3 << nodeIn_d_bits_size; // @[package.scala:243:71] wire [1:0] _r_beats1_decode_T_10 = _r_beats1_decode_T_9[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _r_beats1_decode_T_11 = ~_r_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire r_beats1_opdata_3 = nodeIn_d_bits_opcode[0]; // @[Edges.scala:106:36] reg r_counter_3; // @[Edges.scala:229:27] wire _r_last_T_6 = r_counter_3; // @[Edges.scala:229:27, :232:25] wire [1:0] _r_counter1_T_3 = {1'h0, r_counter_3} - 2'h1; // @[Edges.scala:229:27, :230:28] wire r_counter1_3 = _r_counter1_T_3[0]; // @[Edges.scala:230:28] wire d_first = ~r_counter_3; // @[Edges.scala:229:27, :231:25] wire _r_count_T_3 = ~r_counter1_3; // @[Edges.scala:230:28, :234:27] wire _r_counter_T_3 = ~d_first & r_counter1_3; // @[Edges.scala:230:28, :231:25, :236:21] wire d_request = nodeIn_d_bits_opcode[2] & ~(nodeIn_d_bits_opcode[1]); // @[Edges.scala:71:{36,40,43,52}] wire _a_inc_T_1 = _a_inc_T & a_first; // @[Decoupled.scala:51:35] wire a_inc = _a_inc_T_1; // @[Edges.scala:310:{26,37}] wire _d_inc_T_1 = _d_inc_T & d_first; // @[Decoupled.scala:51:35] wire d_inc = _d_inc_T_1 & d_request; // @[Edges.scala:71:40, :313:{26,37}] wire [1:0] inc = {a_inc, d_inc}; // @[Edges.scala:310:37, :313:37, :315:18] wire _a_dec_T_1 = _a_dec_T; // @[Decoupled.scala:51:35] wire _d_dec_T_1 = _d_dec_T; // @[Decoupled.scala:51:35] wire d_dec = _d_dec_T_1; // @[Edges.scala:320:{26,36}] wire [1:0] dec = {1'h0, d_dec}; // @[Edges.scala:320:36, :322:18] wire _next_flight_T = inc[0]; // @[Edges.scala:315:18, :324:40] wire _next_flight_T_1 = inc[1]; // @[Edges.scala:315:18, :324:40] wire [1:0] _next_flight_T_2 = {1'h0, _next_flight_T} + {1'h0, _next_flight_T_1}; // @[Edges.scala:324:40] wire [1:0] _next_flight_T_3 = _next_flight_T_2; // @[Edges.scala:324:40] wire [2:0] _next_flight_T_4 = {1'h0, flight} + {1'h0, _next_flight_T_3}; // @[Edges.scala:295:25, :324:{30,40}] wire [1:0] _next_flight_T_5 = _next_flight_T_4[1:0]; // @[Edges.scala:324:30] wire _next_flight_T_6 = dec[0]; // @[Edges.scala:322:18, :324:56] wire _next_flight_T_7 = dec[1]; // @[Edges.scala:322:18, :324:56] wire [1:0] _next_flight_T_8 = {1'h0, _next_flight_T_6} + {1'h0, _next_flight_T_7}; // @[Edges.scala:324:56] wire [1:0] _next_flight_T_9 = _next_flight_T_8; // @[Edges.scala:324:56] wire [2:0] _next_flight_T_10 = {1'h0, _next_flight_T_5} - {1'h0, _next_flight_T_9}; // @[Edges.scala:324:{30,46,56}] wire [1:0] next_flight = _next_flight_T_10[1:0]; // @[Edges.scala:324:46] assign _io_pending_T = |flight; // @[Edges.scala:295:25] assign io_pending = _io_pending_T; // @[BusBypass.scala:66:9, :84:27] wire _stall_T = bypass != io_bypass_0; // @[BusBypass.scala:66:9, :81:21, :86:25] wire stall_done = _stall_T_1; // @[Decoupled.scala:51:35] wire stall_beats1_opdata = ~_stall_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg stall_counter; // @[Edges.scala:229:27] wire _stall_last_T = stall_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _stall_counter1_T = {1'h0, stall_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire stall_counter1 = _stall_counter1_T[0]; // @[Edges.scala:230:28] wire stall_first = ~stall_counter; // @[Edges.scala:229:27, :231:25] wire _stall_count_T = ~stall_counter1; // @[Edges.scala:230:28, :234:27] wire _stall_counter_T = ~stall_first & stall_counter1; // @[Edges.scala:230:28, :231:25, :236:21] wire stall = _stall_T & stall_first; // @[Edges.scala:231:25] wire _nodeOut_a_valid_T = ~stall; // @[BusBypass.scala:86:40, :88:21] wire _nodeOut_a_valid_T_1 = _nodeOut_a_valid_T & nodeIn_a_valid; // @[BusBypass.scala:88:{21,28}] assign _nodeOut_a_valid_T_2 = _nodeOut_a_valid_T_1 & bypass; // @[BusBypass.scala:81:21, :88:{28,42}] assign nodeOut_a_valid = _nodeOut_a_valid_T_2; // @[BusBypass.scala:88:42] wire _nodeOut_a_valid_T_3 = ~stall; // @[BusBypass.scala:86:40, :88:21, :89:21] wire _nodeOut_a_valid_T_4 = _nodeOut_a_valid_T_3 & nodeIn_a_valid; // @[BusBypass.scala:89:{21,28}] wire _nodeOut_a_valid_T_5 = ~bypass; // @[BusBypass.scala:81:21, :89:45] assign _nodeOut_a_valid_T_6 = _nodeOut_a_valid_T_4 & _nodeOut_a_valid_T_5; // @[BusBypass.scala:89:{28,42,45}] assign x1_nodeOut_a_valid = _nodeOut_a_valid_T_6; // @[BusBypass.scala:89:42] wire _nodeIn_a_ready_T = ~stall; // @[BusBypass.scala:86:40, :88:21, :90:21] wire _nodeIn_a_ready_T_1 = bypass ? nodeOut_a_ready : x1_nodeOut_a_ready; // @[BusBypass.scala:81:21, :90:34] assign _nodeIn_a_ready_T_2 = _nodeIn_a_ready_T & _nodeIn_a_ready_T_1; // @[BusBypass.scala:90:{21,28,34}] assign nodeIn_a_ready = _nodeIn_a_ready_T_2; // @[BusBypass.scala:90:28] assign nodeOut_a_bits_address = {119'h0, nodeIn_a_bits_address}; // @[BusBypass.scala:91:18] assign _nodeOut_d_ready_T = nodeIn_d_ready & bypass; // @[BusBypass.scala:81:21, :94:32] assign nodeOut_d_ready = _nodeOut_d_ready_T; // @[BusBypass.scala:94:32] wire _nodeOut_d_ready_T_1 = ~bypass; // @[BusBypass.scala:81:21, :89:45, :95:35] assign _nodeOut_d_ready_T_2 = nodeIn_d_ready & _nodeOut_d_ready_T_1; // @[BusBypass.scala:95:{32,35}] assign x1_nodeOut_d_ready = _nodeOut_d_ready_T_2; // @[BusBypass.scala:95:32] assign _nodeIn_d_valid_T = bypass ? nodeOut_d_valid : x1_nodeOut_d_valid; // @[BusBypass.scala:81:21, :96:24] assign nodeIn_d_valid = _nodeIn_d_valid_T; // @[BusBypass.scala:96:24] assign _nodeIn_d_bits_T_opcode = bypass ? nodeIn_d_bits_out_opcode : nodeIn_d_bits_out_1_opcode; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_param = bypass ? nodeIn_d_bits_out_param : nodeIn_d_bits_out_1_param; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_size = bypass ? nodeIn_d_bits_out_size : nodeIn_d_bits_out_1_size; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_source = ~bypass & nodeIn_d_bits_out_1_source; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_sink = ~bypass & nodeIn_d_bits_out_1_sink; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_denied = bypass ? nodeIn_d_bits_out_denied : nodeIn_d_bits_out_1_denied; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_data = bypass ? 32'h0 : nodeIn_d_bits_out_1_data; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_corrupt = bypass ? nodeIn_d_bits_out_corrupt : nodeIn_d_bits_out_1_corrupt; // @[BusBypass.scala:81:21, :97:53, :98:21] assign nodeIn_d_bits_opcode = _nodeIn_d_bits_T_opcode; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_param = _nodeIn_d_bits_T_param; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_size = _nodeIn_d_bits_T_size; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_source = _nodeIn_d_bits_T_source; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_sink = _nodeIn_d_bits_T_sink; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_denied = _nodeIn_d_bits_T_denied; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_data = _nodeIn_d_bits_T_data; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_corrupt = _nodeIn_d_bits_T_corrupt; // @[BusBypass.scala:98:21] always @(posedge clock) begin // @[BusBypass.scala:66:9] if (reset) begin // @[BusBypass.scala:66:9] in_reset <= 1'h1; // @[BusBypass.scala:79:27] flight <= 2'h0; // @[Edges.scala:295:25] r_counter <= 1'h0; // @[Edges.scala:229:27] r_counter_3 <= 1'h0; // @[Edges.scala:229:27] stall_counter <= 1'h0; // @[Edges.scala:229:27] end else begin // @[BusBypass.scala:66:9] in_reset <= 1'h0; // @[BusBypass.scala:79:27] flight <= next_flight; // @[Edges.scala:295:25, :324:46] if (_T) // @[Decoupled.scala:51:35] r_counter <= _r_counter_T; // @[Edges.scala:229:27, :236:21] if (_T_3) // @[Decoupled.scala:51:35] r_counter_3 <= _r_counter_T_3; // @[Edges.scala:229:27, :236:21] if (_stall_T_1) // @[Decoupled.scala:51:35] stall_counter <= _stall_counter_T; // @[Edges.scala:229:27, :236:21] end if (in_reset | next_flight == 2'h0) // @[Edges.scala:324:46] bypass_reg <= io_bypass_0; // @[BusBypass.scala:66:9, :80:25] always @(posedge) TLMonitor_51 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] assign auto_in_a_ready = auto_in_a_ready_0; // @[BusBypass.scala:66:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[BusBypass.scala:66:9] assign auto_out_1_a_valid = auto_out_1_a_valid_0; // @[BusBypass.scala:66:9] assign auto_out_1_a_bits_opcode = auto_out_1_a_bits_opcode_0; // @[BusBypass.scala:66:9] assign auto_out_1_a_bits_address = auto_out_1_a_bits_address_0; // @[BusBypass.scala:66:9] assign auto_out_1_a_bits_data = auto_out_1_a_bits_data_0; // @[BusBypass.scala:66:9] assign auto_out_1_d_ready = auto_out_1_d_ready_0; // @[BusBypass.scala:66:9] assign auto_out_0_a_valid = auto_out_0_a_valid_0; // @[BusBypass.scala:66:9] assign auto_out_0_a_bits_opcode = auto_out_0_a_bits_opcode_0; // @[BusBypass.scala:66:9] assign auto_out_0_a_bits_address = auto_out_0_a_bits_address_0; // @[BusBypass.scala:66:9] assign auto_out_0_a_bits_data = auto_out_0_a_bits_data_0; // @[BusBypass.scala:66:9] assign auto_out_0_d_ready = auto_out_0_d_ready_0; // @[BusBypass.scala:66:9] endmodule

Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands */ class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def *(t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def *(t: UInt) = self * t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros | ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def *(t: SInt) = self * t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros | ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid || output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def *(t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def *(t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }

module PE_294( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid, // @[PE.scala:35:14] output io_bad_dataflow // @[PE.scala:35:14] ); wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24] wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [31:0] c1; // @[PE.scala:70:15] wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [31:0] c2; // @[PE.scala:71:15] wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25] wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61] wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38] wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38] assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16] assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10] wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10] c1 <= _GEN_7; // @[PE.scala:70:15, :124:10] if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30] end else // @[PE.scala:71:15, :118:101, :119:30] c2 <= _GEN_7; // @[PE.scala:71:15, :124:10] end else begin // @[PE.scala:31:7] c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10] c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10] end last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] end always @(posedge) MacUnit_38 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24] .io_out_d (_mac_unit_io_out_d) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File DescribedSRAM.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3.{Data, SyncReadMem, Vec} import chisel3.util.log2Ceil object DescribedSRAM { def apply[T <: Data]( name: String, desc: String, size: BigInt, // depth data: T ): SyncReadMem[T] = { val mem = SyncReadMem(size, data) mem.suggestName(name) val granWidth = data match { case v: Vec[_] => v.head.getWidth case d => d.getWidth } val uid = 0 Annotated.srams( component = mem, name = name, address_width = log2Ceil(size), data_width = data.getWidth, depth = size, description = desc, write_mask_granularity = granWidth ) mem } }

module rerocc_tile_dcache_tag_array_2( // @[DescribedSRAM.scala:17:26] input [1:0] RW0_addr, input RW0_en, input RW0_clk, input RW0_wmode, input [103:0] RW0_wdata, output [103:0] RW0_rdata, input [3:0] RW0_wmask ); rerocc_tile_dcache_tag_array_ext rerocc_tile_dcache_tag_array_ext ( // @[DescribedSRAM.scala:17:26] .RW0_addr (RW0_addr), .RW0_en (RW0_en), .RW0_clk (RW0_clk), .RW0_wmode (RW0_wmode), .RW0_wdata (RW0_wdata), .RW0_rdata (RW0_rdata), .RW0_wmask (RW0_wmask) ); // @[DescribedSRAM.scala:17:26] endmodule

Generate the Verilog code corresponding to the following Chisel files. File AsyncResetReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ /** This black-boxes an Async Reset * (or Set) * Register. * * Because Chisel doesn't support * parameterized black boxes, * we unfortunately have to * instantiate a number of these. * * We also have to hard-code the set/ * reset behavior. * * Do not confuse an asynchronous * reset signal with an asynchronously * reset reg. You should still * properly synchronize your reset * deassertion. * * @param d Data input * @param q Data Output * @param clk Clock Input * @param rst Reset Input * @param en Write Enable Input * */ class AsyncResetReg(resetValue: Int = 0) extends RawModule { val io = IO(new Bundle { val d = Input(Bool()) val q = Output(Bool()) val en = Input(Bool()) val clk = Input(Clock()) val rst = Input(Reset()) }) val reg = withClockAndReset(io.clk, io.rst.asAsyncReset)(RegInit(resetValue.U(1.W))) when (io.en) { reg := io.d } io.q := reg } class SimpleRegIO(val w: Int) extends Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) } class AsyncResetRegVec(val w: Int, val init: BigInt) extends Module { override def desiredName = s"AsyncResetRegVec_w${w}_i${init}" val io = IO(new SimpleRegIO(w)) val reg = withReset(reset.asAsyncReset)(RegInit(init.U(w.W))) when (io.en) { reg := io.d } io.q := reg } object AsyncResetReg { // Create Single Registers def apply(d: Bool, clk: Clock, rst: Bool, init: Boolean, name: Option[String]): Bool = { val reg = Module(new AsyncResetReg(if (init) 1 else 0)) reg.io.d := d reg.io.clk := clk reg.io.rst := rst reg.io.en := true.B name.foreach(reg.suggestName(_)) reg.io.q } def apply(d: Bool, clk: Clock, rst: Bool): Bool = apply(d, clk, rst, false, None) def apply(d: Bool, clk: Clock, rst: Bool, name: String): Bool = apply(d, clk, rst, false, Some(name)) // Create Vectors of Registers def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: Option[String] = None): UInt = { val w = updateData.getWidth max resetData.bitLength val reg = Module(new AsyncResetRegVec(w, resetData)) name.foreach(reg.suggestName(_)) reg.io.d := updateData reg.io.en := enable reg.io.q } def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: String): UInt = apply(updateData, resetData, enable, Some(name)) def apply(updateData: UInt, resetData: BigInt): UInt = apply(updateData, resetData, enable = true.B) def apply(updateData: UInt, resetData: BigInt, name: String): UInt = apply(updateData, resetData, enable = true.B, Some(name)) def apply(updateData: UInt, enable: Bool): UInt = apply(updateData, resetData=BigInt(0), enable) def apply(updateData: UInt, enable: Bool, name: String): UInt = apply(updateData, resetData = BigInt(0), enable, Some(name)) def apply(updateData: UInt): UInt = apply(updateData, resetData = BigInt(0), enable = true.B) def apply(updateData: UInt, name:String): UInt = apply(updateData, resetData = BigInt(0), enable = true.B, Some(name)) }

module AsyncResetRegVec_w1_i0_24( // @[AsyncResetReg.scala:56:7] input clock, // @[AsyncResetReg.scala:56:7] input reset, // @[AsyncResetReg.scala:56:7] input io_d, // @[AsyncResetReg.scala:59:14] output io_q // @[AsyncResetReg.scala:59:14] ); wire io_d_0 = io_d; // @[AsyncResetReg.scala:56:7] wire _reg_T = reset; // @[AsyncResetReg.scala:61:29] wire io_en = 1'h1; // @[AsyncResetReg.scala:56:7, :59:14] wire io_q_0; // @[AsyncResetReg.scala:56:7] reg reg_0; // @[AsyncResetReg.scala:61:50] assign io_q_0 = reg_0; // @[AsyncResetReg.scala:56:7, :61:50] always @(posedge clock or posedge _reg_T) begin // @[AsyncResetReg.scala:56:7, :61:29] if (_reg_T) // @[AsyncResetReg.scala:56:7, :61:29] reg_0 <= 1'h0; // @[AsyncResetReg.scala:61:50] else // @[AsyncResetReg.scala:56:7] reg_0 <= io_d_0; // @[AsyncResetReg.scala:56:7, :61:50] always @(posedge, posedge)

Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands */ class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def *(t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def *(t: UInt) = self * t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros | ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def *(t: SInt) = self * t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros | ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid || output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def *(t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def *(t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }

module MacUnit_211( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [19:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54] assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File ShiftRegisterPriorityQueue.scala: package compressacc import chisel3._ import chisel3.util._ import chisel3.util._ // TODO : support enq & deq at the same cycle class PriorityQueueStageIO(keyWidth: Int, value: ValueInfo) extends Bundle { val output_prev = KeyValue(keyWidth, value) val output_nxt = KeyValue(keyWidth, value) val input_prev = Flipped(KeyValue(keyWidth, value)) val input_nxt = Flipped(KeyValue(keyWidth, value)) val cmd = Flipped(Valid(UInt(1.W))) val insert_here = Input(Bool()) val cur_input_keyval = Flipped(KeyValue(keyWidth, value)) val cur_output_keyval = KeyValue(keyWidth, value) } class PriorityQueueStage(keyWidth: Int, value: ValueInfo) extends Module { val io = IO(new PriorityQueueStageIO(keyWidth, value)) dontTouch(io) val CMD_DEQ = 0.U val CMD_ENQ = 1.U val MAX_VALUE = (1 << keyWidth) - 1 val key_reg = RegInit(MAX_VALUE.U(keyWidth.W)) val value_reg = Reg(value) io.output_prev.key := key_reg io.output_prev.value := value_reg io.output_nxt.key := key_reg io.output_nxt.value := value_reg io.cur_output_keyval.key := key_reg io.cur_output_keyval.value := value_reg when (io.cmd.valid) { switch (io.cmd.bits) { is (CMD_DEQ) { key_reg := io.input_nxt.key value_reg := io.input_nxt.value } is (CMD_ENQ) { when (io.insert_here) { key_reg := io.cur_input_keyval.key value_reg := io.cur_input_keyval.value } .elsewhen (key_reg >= io.cur_input_keyval.key) { key_reg := io.input_prev.key value_reg := io.input_prev.value } .otherwise { // do nothing } } } } } object PriorityQueueStage { def apply(keyWidth: Int, v: ValueInfo): PriorityQueueStage = new PriorityQueueStage(keyWidth, v) } // TODO // - This design is not scalable as the enqued_keyval is broadcasted to all the stages // - Add pipeline registers later class PriorityQueueIO(queSize: Int, keyWidth: Int, value: ValueInfo) extends Bundle { val cnt_bits = log2Ceil(queSize+1) val counter = Output(UInt(cnt_bits.W)) val enq = Flipped(Decoupled(KeyValue(keyWidth, value))) val deq = Decoupled(KeyValue(keyWidth, value)) } class PriorityQueue(queSize: Int, keyWidth: Int, value: ValueInfo) extends Module { val keyWidthInternal = keyWidth + 1 val CMD_DEQ = 0.U val CMD_ENQ = 1.U val io = IO(new PriorityQueueIO(queSize, keyWidthInternal, value)) dontTouch(io) val MAX_VALUE = ((1 << keyWidthInternal) - 1).U val cnt_bits = log2Ceil(queSize+1) // do not consider cases where we are inserting more entries then the queSize val counter = RegInit(0.U(cnt_bits.W)) io.counter := counter val full = (counter === queSize.U) val empty = (counter === 0.U) io.deq.valid := !empty io.enq.ready := !full when (io.enq.fire) { counter := counter + 1.U } when (io.deq.fire) { counter := counter - 1.U } val cmd_valid = io.enq.valid || io.deq.ready val cmd = Mux(io.enq.valid, CMD_ENQ, CMD_DEQ) assert(!(io.enq.valid && io.deq.ready)) val stages = Seq.fill(queSize)(Module(new PriorityQueueStage(keyWidthInternal, value))) for (i <- 0 until (queSize - 1)) { stages(i+1).io.input_prev <> stages(i).io.output_nxt stages(i).io.input_nxt <> stages(i+1).io.output_prev } stages(queSize-1).io.input_nxt.key := MAX_VALUE // stages(queSize-1).io.input_nxt.value := stages(queSize-1).io.input_nxt.value.symbol := 0.U // stages(queSize-1).io.input_nxt.value.child(0) := 0.U // stages(queSize-1).io.input_nxt.value.child(1) := 0.U stages(0).io.input_prev.key := io.enq.bits.key stages(0).io.input_prev.value <> io.enq.bits.value for (i <- 0 until queSize) { stages(i).io.cmd.valid := cmd_valid stages(i).io.cmd.bits := cmd stages(i).io.cur_input_keyval <> io.enq.bits } val is_large_or_equal = WireInit(VecInit(Seq.fill(queSize)(false.B))) for (i <- 0 until queSize) { is_large_or_equal(i) := (stages(i).io.cur_output_keyval.key >= io.enq.bits.key) } val is_large_or_equal_cat = Wire(UInt(queSize.W)) is_large_or_equal_cat := Cat(is_large_or_equal.reverse) val insert_here_idx = PriorityEncoder(is_large_or_equal_cat) for (i <- 0 until queSize) { when (i.U === insert_here_idx) { stages(i).io.insert_here := true.B } .otherwise { stages(i).io.insert_here := false.B } } io.deq.bits <> stages(0).io.output_prev }

module PriorityQueueStage_83( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File NIC.scala: package icenet import chisel3._ import chisel3.util._ import chisel3.reflect.DataMirror import freechips.rocketchip.subsystem.{BaseSubsystem, TLBusWrapperLocation, PBUS, FBUS} import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.prci._ import freechips.rocketchip.regmapper._ import freechips.rocketchip.interrupts._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import IceNetConsts._ // This is copied from testchipip to avoid dependencies class ClockedIO[T <: Data](private val gen: T) extends Bundle { val clock = Output(Clock()) val bits = DataMirror.internal.chiselTypeClone[T](gen) } /** * @inBufFlits How many flits in the input buffer(s) * @outBufFlits Number of flits in the output buffer * @nMemXacts Maximum number of transactions that the send/receive path can send to memory * @maxAcquireBytes Cache block size * @ctrlQueueDepth Depth of the MMIO control queues * @usePauser Hardware support for Ethernet pause frames * @checksumOffload TCP checksum offload engine * @packetMaxBytes Maximum number of bytes in a packet (header size + MTU) */ case class NICConfig( inBufFlits: Int = 2 * ETH_STANDARD_MAX_BYTES / NET_IF_BYTES, outBufFlits: Int = 2 * ETH_STANDARD_MAX_BYTES / NET_IF_BYTES, nMemXacts: Int = 8, maxAcquireBytes: Int = 64, ctrlQueueDepth: Int = 10, usePauser: Boolean = false, checksumOffload: Boolean = false, packetMaxBytes: Int = ETH_STANDARD_MAX_BYTES) case class NICAttachParams( masterWhere: TLBusWrapperLocation = FBUS, slaveWhere: TLBusWrapperLocation = PBUS ) case object NICKey extends Field[Option[NICConfig]](None) case object NICAttachKey extends Field[NICAttachParams](NICAttachParams()) trait HasNICParameters { implicit val p: Parameters val nicExternal = p(NICKey).get val inBufFlits = nicExternal.inBufFlits val outBufFlits = nicExternal.outBufFlits val nMemXacts = nicExternal.nMemXacts val maxAcquireBytes = nicExternal.maxAcquireBytes val ctrlQueueDepth = nicExternal.ctrlQueueDepth val usePauser = nicExternal.usePauser val checksumOffload = nicExternal.checksumOffload val packetMaxBytes = nicExternal.packetMaxBytes } abstract class NICLazyModule(implicit p: Parameters) extends LazyModule with HasNICParameters abstract class NICModule(implicit val p: Parameters) extends Module with HasNICParameters abstract class NICBundle(implicit val p: Parameters) extends Bundle with HasNICParameters class PacketArbiter(arbN: Int, rr: Boolean = false) extends HellaPeekingArbiter( new StreamChannel(NET_IF_WIDTH), arbN, (ch: StreamChannel) => ch.last, rr = rr) class IceNicSendIO extends Bundle { val req = Decoupled(UInt(NET_IF_WIDTH.W)) val comp = Flipped(Decoupled(Bool())) } class IceNicRecvIO extends Bundle { val req = Decoupled(UInt(NET_IF_WIDTH.W)) val comp = Flipped(Decoupled(UInt(NET_LEN_BITS.W))) } trait IceNicControllerBundle extends Bundle { val send = new IceNicSendIO val recv = new IceNicRecvIO val macAddr = Input(UInt(ETH_MAC_BITS.W)) val txcsumReq = Decoupled(new ChecksumRewriteRequest) val rxcsumRes = Flipped(Decoupled(new TCPChecksumOffloadResult)) val csumEnable = Output(Bool()) } case class IceNicControllerParams(address: BigInt, beatBytes: Int) /* * Take commands from the CPU over TL2, expose as Queues */ class IceNicController(c: IceNicControllerParams)(implicit p: Parameters) extends RegisterRouter(RegisterRouterParams("ice-nic", Seq("ucb-bar,ice-nic"), c.address, beatBytes=c.beatBytes)) with HasTLControlRegMap with HasInterruptSources with HasNICParameters { override def nInterrupts = 2 def tlRegmap(mapping: RegField.Map*): Unit = regmap(mapping:_*) override lazy val module = new IceNiCControllerModuleImp(this) } class IceNiCControllerModuleImp(outer: IceNicController)(implicit p: Parameters) extends LazyModuleImp(outer) with HasNICParameters { val io = IO(new Bundle with IceNicControllerBundle) val sendCompDown = WireInit(false.B) val qDepth = ctrlQueueDepth require(qDepth < (1 << 8)) def queueCount[T <: Data](qio: QueueIO[T], depth: Int): UInt = TwoWayCounter(qio.enq.fire, qio.deq.fire, depth) // hold (len, addr) of packets that we need to send out val sendReqQueue = Module(new HellaQueue(qDepth)(UInt(NET_IF_WIDTH.W))) val sendReqCount = queueCount(sendReqQueue.io, qDepth) // hold addr of buffers we can write received packets into val recvReqQueue = Module(new HellaQueue(qDepth)(UInt(NET_IF_WIDTH.W))) val recvReqCount = queueCount(recvReqQueue.io, qDepth) // count number of sends completed val sendCompCount = TwoWayCounter(io.send.comp.fire, sendCompDown, qDepth) // hold length of received packets val recvCompQueue = Module(new HellaQueue(qDepth)(UInt(NET_LEN_BITS.W))) val recvCompCount = queueCount(recvCompQueue.io, qDepth) val sendCompValid = sendCompCount > 0.U val intMask = RegInit(0.U(2.W)) io.send.req <> sendReqQueue.io.deq io.recv.req <> recvReqQueue.io.deq io.send.comp.ready := sendCompCount < qDepth.U recvCompQueue.io.enq <> io.recv.comp outer.interrupts(0) := sendCompValid && intMask(0) outer.interrupts(1) := recvCompQueue.io.deq.valid && intMask(1) val sendReqSpace = (qDepth.U - sendReqCount) val recvReqSpace = (qDepth.U - recvReqCount) def sendCompRead = (ready: Bool) => { sendCompDown := sendCompValid && ready (sendCompValid, true.B) } val txcsumReqQueue = Module(new HellaQueue(qDepth)(UInt(49.W))) val rxcsumResQueue = Module(new HellaQueue(qDepth)(UInt(2.W))) val csumEnable = RegInit(false.B) io.txcsumReq.valid := txcsumReqQueue.io.deq.valid io.txcsumReq.bits := txcsumReqQueue.io.deq.bits.asTypeOf(new ChecksumRewriteRequest) txcsumReqQueue.io.deq.ready := io.txcsumReq.ready rxcsumResQueue.io.enq.valid := io.rxcsumRes.valid rxcsumResQueue.io.enq.bits := io.rxcsumRes.bits.asUInt io.rxcsumRes.ready := rxcsumResQueue.io.enq.ready io.csumEnable := csumEnable outer.tlRegmap( 0x00 -> Seq(RegField.w(NET_IF_WIDTH, sendReqQueue.io.enq)), 0x08 -> Seq(RegField.w(NET_IF_WIDTH, recvReqQueue.io.enq)), 0x10 -> Seq(RegField.r(1, sendCompRead)), 0x12 -> Seq(RegField.r(NET_LEN_BITS, recvCompQueue.io.deq)), 0x14 -> Seq( RegField.r(8, sendReqSpace), RegField.r(8, recvReqSpace), RegField.r(8, sendCompCount), RegField.r(8, recvCompCount)), 0x18 -> Seq(RegField.r(ETH_MAC_BITS, io.macAddr)), 0x20 -> Seq(RegField(2, intMask)), 0x28 -> Seq(RegField.w(49, txcsumReqQueue.io.enq)), 0x30 -> Seq(RegField.r(2, rxcsumResQueue.io.deq)), 0x31 -> Seq(RegField(1, csumEnable))) } class IceNicSendPath(nInputTaps: Int = 0)(implicit p: Parameters) extends NICLazyModule { val reader = LazyModule(new StreamReader( nMemXacts, outBufFlits, maxAcquireBytes)) val node = reader.node lazy val module = new Impl class Impl extends LazyModuleImp(this) { val io = IO(new Bundle { val send = Flipped(new IceNicSendIO) val tap = Flipped(Vec(nInputTaps, Decoupled(new StreamChannel(NET_IF_WIDTH)))) val out = Decoupled(new StreamChannel(NET_IF_WIDTH)) val rlimit = Input(new RateLimiterSettings) val csum = checksumOffload.option(new Bundle { val req = Flipped(Decoupled(new ChecksumRewriteRequest)) val enable = Input(Bool()) }) }) val readreq = reader.module.io.req io.send.req.ready := readreq.ready readreq.valid := io.send.req.valid readreq.bits.address := io.send.req.bits(47, 0) readreq.bits.length := io.send.req.bits(62, 48) readreq.bits.partial := io.send.req.bits(63) io.send.comp <> reader.module.io.resp val preArbOut = if (checksumOffload) { val readerOut = reader.module.io.out val arb = Module(new PacketArbiter(2)) val bufFlits = (packetMaxBytes - 1) / NET_IF_BYTES + 1 val rewriter = Module(new ChecksumRewrite(NET_IF_WIDTH, bufFlits)) val enable = io.csum.get.enable rewriter.io.req <> io.csum.get.req arb.io.in(0) <> rewriter.io.stream.out arb.io.in(1).valid := !enable && readerOut.valid arb.io.in(1).bits := readerOut.bits rewriter.io.stream.in.valid := enable && readerOut.valid rewriter.io.stream.in.bits := readerOut.bits readerOut.ready := Mux(enable, rewriter.io.stream.in.ready, arb.io.in(1).ready) arb.io.out } else { reader.module.io.out } val unlimitedOut = if (nInputTaps > 0) { val bufWords = (packetMaxBytes - 1) / NET_IF_BYTES + 1 val inputs = (preArbOut +: io.tap).map { in => // The packet collection buffer doesn't allow sending the first flit // of a packet until the last flit is received. // This ensures that we don't lock the arbiter while waiting for data // to arrive, which could cause deadocks. val buffer = Module(new PacketCollectionBuffer(bufWords)) buffer.io.in <> in buffer.io.out } val arb = Module(new PacketArbiter(inputs.size, rr = true)) arb.io.in <> inputs arb.io.out } else { preArbOut } val limiter = Module(new RateLimiter(new StreamChannel(NET_IF_WIDTH))) limiter.io.in <> unlimitedOut limiter.io.settings := io.rlimit io.out <> limiter.io.out } } class IceNicWriter(implicit p: Parameters) extends NICLazyModule { val writer = LazyModule(new StreamWriter(nMemXacts, maxAcquireBytes)) val node = writer.node lazy val module = new Impl class Impl extends LazyModuleImp(this) { val io = IO(new Bundle { val recv = Flipped(new IceNicRecvIO) val in = Flipped(Decoupled(new StreamChannel(NET_IF_WIDTH))) val length = Flipped(Valid(UInt(NET_LEN_BITS.W))) }) val streaming = RegInit(false.B) val byteAddrBits = log2Ceil(NET_IF_BYTES) val helper = DecoupledHelper( io.recv.req.valid, writer.module.io.req.ready, io.length.valid, !streaming) writer.module.io.req.valid := helper.fire(writer.module.io.req.ready) writer.module.io.req.bits.address := io.recv.req.bits writer.module.io.req.bits.length := io.length.bits io.recv.req.ready := helper.fire(io.recv.req.valid) writer.module.io.in.valid := io.in.valid && streaming writer.module.io.in.bits := io.in.bits io.in.ready := writer.module.io.in.ready && streaming io.recv.comp <> writer.module.io.resp when (io.recv.req.fire) { streaming := true.B } when (io.in.fire && io.in.bits.last) { streaming := false.B } } } /* * Recv frames */ class IceNicRecvPath(val tapFuncs: Seq[EthernetHeader => Bool] = Nil) (implicit p: Parameters) extends LazyModule { val writer = LazyModule(new IceNicWriter) val node = TLIdentityNode() node := writer.node lazy val module = new IceNicRecvPathModule(this) } class IceNicRecvPathModule(val outer: IceNicRecvPath) extends LazyModuleImp(outer) with HasNICParameters { val io = IO(new Bundle { val recv = Flipped(new IceNicRecvIO) val in = Flipped(Decoupled(new StreamChannel(NET_IF_WIDTH))) // input stream val tap = Vec(outer.tapFuncs.length, Decoupled(new StreamChannel(NET_IF_WIDTH))) val csum = checksumOffload.option(new Bundle { val res = Decoupled(new TCPChecksumOffloadResult) val enable = Input(Bool()) }) val buf_free = Output(Vec(1 + outer.tapFuncs.length, UInt(8.W))) }) def tapOutToDropCheck(tapOut: EthernetHeader => Bool) = { (header: EthernetHeader, ch: StreamChannel, update: Bool) => { val first = RegInit(true.B) val drop = tapOut(header) && first val dropReg = RegInit(false.B) when (update && first) { first := false.B; dropReg := drop } when (update && ch.last) { first := true.B; dropReg := false.B } drop || dropReg } } def duplicateStream(in: DecoupledIO[StreamChannel], outs: Seq[DecoupledIO[StreamChannel]]) = { outs.foreach { out => out.valid := in.valid out.bits := in.bits } in.ready := outs.head.ready val outReadys = Cat(outs.map(_.ready)) assert(outReadys.andR || !outReadys.orR, "Duplicated streams must all be ready simultaneously") outs } def invertCheck(check: (EthernetHeader, StreamChannel, Bool) => Bool) = (eth: EthernetHeader, ch: StreamChannel, up: Bool) => !check(eth, ch, up) val tapDropChecks = outer.tapFuncs.map(func => tapOutToDropCheck(func)) val pauseDropCheck = if (usePauser) Some(PauseDropCheck(_, _, _)) else None val allDropChecks = // Drop checks for the primary buffer // Drop if the packet should be tapped out or is a pause frame Seq(tapDropChecks ++ pauseDropCheck.toSeq) ++ // Drop checks for the tap buffers // For each tap, drop if the packet doesn't match the tap function or is a pause frame tapDropChecks.map(check => invertCheck(check) +: pauseDropCheck.toSeq) val buffers = allDropChecks.map(dropChecks => Module(new NetworkPacketBuffer( inBufFlits, maxBytes = packetMaxBytes, dropChecks = dropChecks, dropless = usePauser))) duplicateStream(io.in, buffers.map(_.io.stream.in)) io.buf_free := buffers.map(_.io.free) io.tap <> buffers.tail.map(_.io.stream.out) val bufout = buffers.head.io.stream.out val buflen = buffers.head.io.length val (csumout, recvreq) = (if (checksumOffload) { val offload = Module(new TCPChecksumOffload(NET_IF_WIDTH)) val offloadReady = offload.io.in.ready || !io.csum.get.enable val out = Wire(Decoupled(new StreamChannel(NET_IF_WIDTH))) val recvreq = Wire(Decoupled(UInt(NET_IF_WIDTH.W))) val reqq = Module(new Queue(UInt(NET_IF_WIDTH.W), 1)) val enqHelper = DecoupledHelper( io.recv.req.valid, reqq.io.enq.ready, recvreq.ready) val deqHelper = DecoupledHelper( bufout.valid, offloadReady, out.ready, reqq.io.deq.valid) reqq.io.enq.valid := enqHelper.fire(reqq.io.enq.ready) reqq.io.enq.bits := io.recv.req.bits io.recv.req.ready := enqHelper.fire(io.recv.req.valid) recvreq.valid := enqHelper.fire(recvreq.ready) recvreq.bits := io.recv.req.bits out.valid := deqHelper.fire(out.ready) out.bits := bufout.bits offload.io.in.valid := deqHelper.fire(offloadReady, io.csum.get.enable) offload.io.in.bits := bufout.bits bufout.ready := deqHelper.fire(bufout.valid) reqq.io.deq.ready := deqHelper.fire(reqq.io.deq.valid, bufout.bits.last) io.csum.get.res <> offload.io.result (out, recvreq) } else { (bufout, io.recv.req) }) val writer = outer.writer.module writer.io.recv.req <> Queue(recvreq, 1) io.recv.comp <> writer.io.recv.comp writer.io.in <> csumout writer.io.length.valid := buflen.valid writer.io.length.bits := buflen.bits } class NICIO extends StreamIO(NET_IF_WIDTH) { val macAddr = Input(UInt(ETH_MAC_BITS.W)) val rlimit = Input(new RateLimiterSettings) val pauser = Input(new PauserSettings) } /* * A simple NIC * * Expects ethernet frames (see below), but uses a custom transport * (see ExtBundle) * * Ethernet Frame format: * 2 bytes | 6 bytes | 6 bytes | 2 bytes | 46-1500B * Padding | Dest Addr | Source Addr | Type/Len | Data * * @address Starting address of MMIO control registers * @beatBytes Width of memory interface (in bytes) * @tapOutFuncs Sequence of functions for each output tap. * Each function takes the header of an Ethernet frame * and returns Bool that is true if matching and false if not. * @nInputTaps Number of input taps * */ class IceNIC(address: BigInt, beatBytes: Int = 8, tapOutFuncs: Seq[EthernetHeader => Bool] = Nil, nInputTaps: Int = 0) (implicit p: Parameters) extends NICLazyModule { val control = LazyModule(new IceNicController( IceNicControllerParams(address, beatBytes))) val sendPath = LazyModule(new IceNicSendPath(nInputTaps)) val recvPath = LazyModule(new IceNicRecvPath(tapOutFuncs)) val mmionode = TLIdentityNode() val dmanode = TLIdentityNode() val intnode = control.intXing(NoCrossing) control.node := TLAtomicAutomata() := mmionode dmanode := TLWidthWidget(NET_IF_BYTES) := sendPath.node dmanode := TLWidthWidget(NET_IF_BYTES) := recvPath.node lazy val module = new Impl class Impl extends LazyModuleImp(this) { val io = IO(new Bundle { val ext = new NICIO val tapOut = Vec(tapOutFuncs.length, Decoupled(new StreamChannel(NET_IF_WIDTH))) val tapIn = Flipped(Vec(nInputTaps, Decoupled(new StreamChannel(NET_IF_WIDTH)))) }) sendPath.module.io.send <> control.module.io.send recvPath.module.io.recv <> control.module.io.recv // connect externally if (usePauser) { val pauser = Module(new Pauser(inBufFlits, 1 + tapOutFuncs.length)) pauser.io.int.out <> sendPath.module.io.out recvPath.module.io.in <> pauser.io.int.in io.ext.out <> pauser.io.ext.out pauser.io.ext.in <> io.ext.in pauser.io.in_free := recvPath.module.io.buf_free pauser.io.macAddr := io.ext.macAddr pauser.io.settings := io.ext.pauser } else { recvPath.module.io.in <> io.ext.in io.ext.out <> sendPath.module.io.out } control.module.io.macAddr := io.ext.macAddr sendPath.module.io.rlimit := io.ext.rlimit io.tapOut <> recvPath.module.io.tap sendPath.module.io.tap <> io.tapIn if (checksumOffload) { sendPath.module.io.csum.get.req <> control.module.io.txcsumReq sendPath.module.io.csum.get.enable := control.module.io.csumEnable control.module.io.rxcsumRes <> recvPath.module.io.csum.get.res recvPath.module.io.csum.get.enable := control.module.io.csumEnable } else { control.module.io.txcsumReq.ready := false.B control.module.io.rxcsumRes.valid := false.B control.module.io.rxcsumRes.bits := DontCare } } } class SimNetwork extends BlackBox with HasBlackBoxResource { val io = IO(new Bundle { val clock = Input(Clock()) val reset = Input(Bool()) val net = Flipped(new NICIOvonly) }) addResource("/vsrc/SimNetwork.v") addResource("/csrc/SimNetwork.cc") addResource("/csrc/device.h") addResource("/csrc/device.cc") addResource("/csrc/switch.h") addResource("/csrc/switch.cc") addResource("/csrc/packet.h") } class NICIOvonly extends Bundle { val in = Flipped(Valid(new StreamChannel(NET_IF_WIDTH))) val out = Valid(new StreamChannel(NET_IF_WIDTH)) val macAddr = Input(UInt(ETH_MAC_BITS.W)) val rlimit = Input(new RateLimiterSettings) val pauser = Input(new PauserSettings) } object NICIOvonly { def apply(nicio: NICIO): NICIOvonly = { val vonly = Wire(new NICIOvonly) vonly.out.valid := nicio.out.valid vonly.out.bits := nicio.out.bits nicio.out.ready := true.B nicio.in.valid := vonly.in.valid nicio.in.bits := vonly.in.bits assert(!vonly.in.valid || nicio.in.ready, "NIC input not ready for valid") nicio.macAddr := vonly.macAddr nicio.rlimit := vonly.rlimit nicio.pauser := vonly.pauser vonly } } object NICIO { def apply(vonly: NICIOvonly): NICIO = { val nicio = Wire(new NICIO) assert(!vonly.out.valid || nicio.out.ready) nicio.out.valid := vonly.out.valid nicio.out.bits := vonly.out.bits vonly.in.valid := nicio.in.valid vonly.in.bits := nicio.in.bits nicio.in.ready := true.B vonly.macAddr := nicio.macAddr vonly.rlimit := nicio.rlimit vonly.pauser := nicio.pauser nicio } } trait CanHavePeripheryIceNIC { this: BaseSubsystem => private val address = BigInt(0x10016000) private val portName = "Ice-NIC" val icenicOpt = p(NICKey).map { params => val manager = locateTLBusWrapper(p(NICAttachKey).slaveWhere) val client = locateTLBusWrapper(p(NICAttachKey).masterWhere) // TODO: currently the controller is in the clock domain of the bus which masters it // we assume this is same as the clock domain of the bus the controller masters val domain = manager.generateSynchronousDomain.suggestName("icenic_domain") val icenic = domain { LazyModule(new IceNIC(address, manager.beatBytes)) } manager.coupleTo(portName) { icenic.mmionode := TLFragmenter(manager.beatBytes, manager.blockBytes) := _ } client.coupleFrom(portName) { _ :=* icenic.dmanode } ibus.fromSync := icenic.intnode val inner_io = domain { InModuleBody { val inner_io = IO(new NICIOvonly).suggestName("nic") inner_io <> NICIOvonly(icenic.module.io.ext) inner_io } } val outer_io = InModuleBody { val outer_io = IO(new ClockedIO(new NICIOvonly)).suggestName("nic") outer_io.bits <> inner_io outer_io.clock := domain.module.clock outer_io } outer_io } } object NicLoopback { def connect(net: Option[NICIOvonly], nicConf: Option[NICConfig], qDepth: Int, latency: Int = 10): Unit = { net.foreach { netio => import PauseConsts.BT_PER_QUANTA val packetWords = nicConf.get.packetMaxBytes / NET_IF_BYTES val packetQuanta = (nicConf.get.packetMaxBytes * 8) / BT_PER_QUANTA netio.macAddr := PlusArg("macaddr") netio.rlimit.inc := PlusArg("rlimit-inc", 1) netio.rlimit.period := PlusArg("rlimit-period", 1) netio.rlimit.size := PlusArg("rlimit-size", 8) netio.pauser.threshold := PlusArg("pauser-threshold", 2 * packetWords + latency) netio.pauser.quanta := PlusArg("pauser-quanta", 2 * packetQuanta) netio.pauser.refresh := PlusArg("pauser-refresh", packetWords) if (nicConf.get.usePauser) { val pauser = Module(new PauserComplex(qDepth)) pauser.io.ext.flipConnect(NetDelay(NICIO(netio), latency)) pauser.io.int.out <> pauser.io.int.in pauser.io.macAddr := netio.macAddr + (1 << 40).U pauser.io.settings := netio.pauser } else { netio.in := Pipe(netio.out, latency) } netio.in.bits.keep := NET_FULL_KEEP } } def connect(net: NICIOvonly, nicConf: NICConfig): Unit = { val packetWords = nicConf.packetMaxBytes / NET_IF_BYTES NicLoopback.connect(Some(net), Some(nicConf), 4 * packetWords) } } object SimNetwork { def connect(net: Option[NICIOvonly], clock: Clock, reset: Bool) { net.foreach { netio => val sim = Module(new SimNetwork) sim.io.clock := clock sim.io.reset := reset sim.io.net <> netio } } } File Arbiters.scala: // See LICENSE.Berkeley for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters /** A generalized locking RR arbiter that addresses the limitations of the * version in the Chisel standard library */ abstract class HellaLockingArbiter[T <: Data](typ: T, arbN: Int, rr: Boolean = false) extends Module { val io = IO(new Bundle { val in = Flipped(Vec(arbN, Decoupled(typ.cloneType))) val out = Decoupled(typ.cloneType) }) def rotateLeft[T <: Data](norm: Vec[T], rot: UInt): Vec[T] = { val n = norm.size VecInit.tabulate(n) { i => Mux(rot < (n - i).U, norm(i.U + rot), norm(rot - (n - i).U)) } } val lockIdx = RegInit(0.U(log2Up(arbN).W)) val locked = RegInit(false.B) val choice = if (rr) { PriorityMux( rotateLeft(VecInit(io.in.map(_.valid)), lockIdx + 1.U), rotateLeft(VecInit((0 until arbN).map(_.U)), lockIdx + 1.U)) } else { PriorityEncoder(io.in.map(_.valid)) } val chosen = Mux(locked, lockIdx, choice) for (i <- 0 until arbN) { io.in(i).ready := io.out.ready && chosen === i.U } io.out.valid := io.in(chosen).valid io.out.bits := io.in(chosen).bits } /** This locking arbiter determines when it is safe to unlock * by peeking at the data */ class HellaPeekingArbiter[T <: Data]( typ: T, arbN: Int, canUnlock: T => Bool, needsLock: Option[T => Bool] = None, rr: Boolean = false) extends HellaLockingArbiter(typ, arbN, rr) { def realNeedsLock(data: T): Bool = needsLock.map(_(data)).getOrElse(true.B) when (io.out.fire) { when (!locked && realNeedsLock(io.out.bits)) { lockIdx := choice locked := true.B } // the unlock statement takes precedent when (canUnlock(io.out.bits)) { locked := false.B } } } /** This arbiter determines when it is safe to unlock by counting transactions */ class HellaCountingArbiter[T <: Data]( typ: T, arbN: Int, count: Int, val needsLock: Option[T => Bool] = None, rr: Boolean = false) extends HellaLockingArbiter(typ, arbN, rr) { def realNeedsLock(data: T): Bool = needsLock.map(_(data)).getOrElse(true.B) // if count is 1, you should use a non-locking arbiter require(count > 1, "CountingArbiter cannot have count <= 1") val lock_ctr = Counter(count) when (io.out.fire) { when (!locked && realNeedsLock(io.out.bits)) { lockIdx := choice locked := true.B lock_ctr.inc() } when (locked) { when (lock_ctr.inc()) { locked := false.B } } } } /** This arbiter preserves the order of responses */ class InOrderArbiter[T <: Data, U <: Data](reqTyp: T, respTyp: U, n: Int) (implicit p: Parameters) extends Module { val io = IO(new Bundle { val in_req = Flipped(Vec(n, Decoupled(reqTyp))) val in_resp = Vec(n, Decoupled(respTyp)) val out_req = Decoupled(reqTyp) val out_resp = Flipped(Decoupled(respTyp)) }) if (n > 1) { val route_q = Module(new Queue(UInt(log2Up(n).W), 2)) val req_arb = Module(new RRArbiter(reqTyp, n)) req_arb.io.in <> io.in_req val req_helper = DecoupledHelper( req_arb.io.out.valid, route_q.io.enq.ready, io.out_req.ready) io.out_req.bits := req_arb.io.out.bits io.out_req.valid := req_helper.fire(io.out_req.ready) route_q.io.enq.bits := req_arb.io.chosen route_q.io.enq.valid := req_helper.fire(route_q.io.enq.ready) req_arb.io.out.ready := req_helper.fire(req_arb.io.out.valid) val resp_sel = route_q.io.deq.bits val resp_ready = io.in_resp(resp_sel).ready val resp_helper = DecoupledHelper( resp_ready, route_q.io.deq.valid, io.out_resp.valid) val resp_valid = resp_helper.fire(resp_ready) for (i <- 0 until n) { io.in_resp(i).bits := io.out_resp.bits io.in_resp(i).valid := resp_valid && resp_sel === i.U } route_q.io.deq.ready := resp_helper.fire(route_q.io.deq.valid) io.out_resp.ready := resp_helper.fire(io.out_resp.valid) } else { io.out_req <> io.in_req.head io.in_resp.head <> io.out_resp } }

module PacketArbiter( // @[NIC.scala:72:7] input clock, // @[NIC.scala:72:7] input reset, // @[NIC.scala:72:7] output io_in_0_ready, // @[Arbiters.scala:14:14] input io_in_0_valid, // @[Arbiters.scala:14:14] input [63:0] io_in_0_bits_data, // @[Arbiters.scala:14:14] input [7:0] io_in_0_bits_keep, // @[Arbiters.scala:14:14] input io_in_0_bits_last, // @[Arbiters.scala:14:14] output io_in_1_ready, // @[Arbiters.scala:14:14] input io_in_1_valid, // @[Arbiters.scala:14:14] input [63:0] io_in_1_bits_data, // @[Arbiters.scala:14:14] input [7:0] io_in_1_bits_keep, // @[Arbiters.scala:14:14] input io_in_1_bits_last, // @[Arbiters.scala:14:14] input io_out_ready, // @[Arbiters.scala:14:14] output io_out_valid, // @[Arbiters.scala:14:14] output [63:0] io_out_bits_data, // @[Arbiters.scala:14:14] output [7:0] io_out_bits_keep, // @[Arbiters.scala:14:14] output io_out_bits_last // @[Arbiters.scala:14:14] ); wire io_in_0_valid_0 = io_in_0_valid; // @[NIC.scala:72:7] wire [63:0] io_in_0_bits_data_0 = io_in_0_bits_data; // @[NIC.scala:72:7] wire [7:0] io_in_0_bits_keep_0 = io_in_0_bits_keep; // @[NIC.scala:72:7] wire io_in_0_bits_last_0 = io_in_0_bits_last; // @[NIC.scala:72:7] wire io_in_1_valid_0 = io_in_1_valid; // @[NIC.scala:72:7] wire [63:0] io_in_1_bits_data_0 = io_in_1_bits_data; // @[NIC.scala:72:7] wire [7:0] io_in_1_bits_keep_0 = io_in_1_bits_keep; // @[NIC.scala:72:7] wire io_in_1_bits_last_0 = io_in_1_bits_last; // @[NIC.scala:72:7] wire io_out_ready_0 = io_out_ready; // @[NIC.scala:72:7] wire _io_in_0_ready_T_1; // @[Arbiters.scala:40:36] wire _io_in_1_ready_T_1; // @[Arbiters.scala:40:36] wire io_in_0_ready_0; // @[NIC.scala:72:7] wire io_in_1_ready_0; // @[NIC.scala:72:7] wire [63:0] io_out_bits_data_0; // @[NIC.scala:72:7] wire [7:0] io_out_bits_keep_0; // @[NIC.scala:72:7] wire io_out_bits_last_0; // @[NIC.scala:72:7] wire io_out_valid_0; // @[NIC.scala:72:7] reg lockIdx; // @[Arbiters.scala:26:24] reg locked; // @[Arbiters.scala:27:23] wire choice = ~io_in_0_valid_0; // @[Mux.scala:50:70] wire chosen = locked ? lockIdx : choice; // @[Mux.scala:50:70] wire _io_in_1_ready_T = chosen; // @[Arbiters.scala:37:19, :40:46] wire _io_in_0_ready_T = ~chosen; // @[Arbiters.scala:37:19, :40:46] assign _io_in_0_ready_T_1 = io_out_ready_0 & _io_in_0_ready_T; // @[Arbiters.scala:40:{36,46}] assign io_in_0_ready_0 = _io_in_0_ready_T_1; // @[Arbiters.scala:40:36] assign _io_in_1_ready_T_1 = io_out_ready_0 & _io_in_1_ready_T; // @[Arbiters.scala:40:{36,46}] assign io_in_1_ready_0 = _io_in_1_ready_T_1; // @[Arbiters.scala:40:36] assign io_out_valid_0 = chosen ? io_in_1_valid_0 : io_in_0_valid_0; // @[Arbiters.scala:37:19, :43:16] assign io_out_bits_data_0 = chosen ? io_in_1_bits_data_0 : io_in_0_bits_data_0; // @[Arbiters.scala:37:19, :43:16] assign io_out_bits_keep_0 = chosen ? io_in_1_bits_keep_0 : io_in_0_bits_keep_0; // @[Arbiters.scala:37:19, :43:16] assign io_out_bits_last_0 = chosen ? io_in_1_bits_last_0 : io_in_0_bits_last_0; // @[Arbiters.scala:37:19, :43:16] wire _T = io_out_ready_0 & io_out_valid_0; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[NIC.scala:72:7] if (reset) begin // @[NIC.scala:72:7] lockIdx <= 1'h0; // @[Arbiters.scala:26:24] locked <= 1'h0; // @[Arbiters.scala:27:23] end else begin // @[NIC.scala:72:7] if (_T & ~locked) // @[Decoupled.scala:51:35] lockIdx <= choice; // @[Mux.scala:50:70] if (_T) // @[Decoupled.scala:51:35] locked <= ~io_out_bits_last_0; // @[Arbiters.scala:27:23, :60:50, :65:35, :66:14] end always @(posedge) assign io_in_0_ready = io_in_0_ready_0; // @[NIC.scala:72:7] assign io_in_1_ready = io_in_1_ready_0; // @[NIC.scala:72:7] assign io_out_valid = io_out_valid_0; // @[NIC.scala:72:7] assign io_out_bits_data = io_out_bits_data_0; // @[NIC.scala:72:7] assign io_out_bits_keep = io_out_bits_keep_0; // @[NIC.scala:72:7] assign io_out_bits_last = io_out_bits_last_0; // @[NIC.scala:72:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Replacement.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import freechips.rocketchip.util.property.cover abstract class ReplacementPolicy { def nBits: Int def perSet: Boolean def way: UInt def miss: Unit def hit: Unit def access(touch_way: UInt): Unit def access(touch_ways: Seq[Valid[UInt]]): Unit def state_read: UInt def get_next_state(state: UInt, touch_way: UInt): UInt def get_next_state(state: UInt, touch_ways: Seq[Valid[UInt]]): UInt = { touch_ways.foldLeft(state)((prev, touch_way) => Mux(touch_way.valid, get_next_state(prev, touch_way.bits), prev)) } def get_replace_way(state: UInt): UInt } object ReplacementPolicy { def fromString(s: String, n_ways: Int): ReplacementPolicy = s.toLowerCase match { case "random" => new RandomReplacement(n_ways) case "lru" => new TrueLRU(n_ways) case "plru" => new PseudoLRU(n_ways) case t => throw new IllegalArgumentException(s"unknown Replacement Policy type $t") } } class RandomReplacement(n_ways: Int) extends ReplacementPolicy { private val replace = Wire(Bool()) replace := false.B def nBits = 16 def perSet = false private val lfsr = LFSR(nBits, replace) def state_read = WireDefault(lfsr) def way = Random(n_ways, lfsr) def miss = replace := true.B def hit = {} def access(touch_way: UInt) = {} def access(touch_ways: Seq[Valid[UInt]]) = {} def get_next_state(state: UInt, touch_way: UInt) = 0.U //DontCare def get_replace_way(state: UInt) = way } abstract class SeqReplacementPolicy { def access(set: UInt): Unit def update(valid: Bool, hit: Bool, set: UInt, way: UInt): Unit def way: UInt } abstract class SetAssocReplacementPolicy { def access(set: UInt, touch_way: UInt): Unit def access(sets: Seq[UInt], touch_ways: Seq[Valid[UInt]]): Unit def way(set: UInt): UInt } class SeqRandom(n_ways: Int) extends SeqReplacementPolicy { val logic = new RandomReplacement(n_ways) def access(set: UInt) = { } def update(valid: Bool, hit: Bool, set: UInt, way: UInt) = { when (valid && !hit) { logic.miss } } def way = logic.way } class TrueLRU(n_ways: Int) extends ReplacementPolicy { // True LRU replacement policy, using a triangular matrix to track which sets are more recently used than others. // The matrix is packed into a single UInt (or Bits). Example 4-way (6-bits): // [5] - 3 more recent than 2 // [4] - 3 more recent than 1 // [3] - 2 more recent than 1 // [2] - 3 more recent than 0 // [1] - 2 more recent than 0 // [0] - 1 more recent than 0 def nBits = (n_ways * (n_ways-1)) / 2 def perSet = true private val state_reg = RegInit(0.U(nBits.W)) def state_read = WireDefault(state_reg) private def extractMRUVec(state: UInt): Seq[UInt] = { // Extract per-way information about which higher-indexed ways are more recently used val moreRecentVec = Wire(Vec(n_ways-1, UInt(n_ways.W))) var lsb = 0 for (i <- 0 until n_ways-1) { moreRecentVec(i) := Cat(state(lsb+n_ways-i-2,lsb), 0.U((i+1).W)) lsb = lsb + (n_ways - i - 1) } moreRecentVec } def get_next_state(state: UInt, touch_way: UInt): UInt = { val nextState = Wire(Vec(n_ways-1, UInt(n_ways.W))) val moreRecentVec = extractMRUVec(state) // reconstruct lower triangular matrix val wayDec = UIntToOH(touch_way, n_ways) // Compute next value of triangular matrix // set the touched way as more recent than every other way nextState.zipWithIndex.map { case (e, i) => e := Mux(i.U === touch_way, 0.U(n_ways.W), moreRecentVec(i) | wayDec) } nextState.zipWithIndex.tail.foldLeft((nextState.head.apply(n_ways-1,1),0)) { case ((pe,pi),(ce,ci)) => (Cat(ce.apply(n_ways-1,ci+1), pe), ci) }._1 } def access(touch_way: UInt): Unit = { state_reg := get_next_state(state_reg, touch_way) } def access(touch_ways: Seq[Valid[UInt]]): Unit = { when (touch_ways.map(_.valid).orR) { state_reg := get_next_state(state_reg, touch_ways) } for (i <- 1 until touch_ways.size) { cover(PopCount(touch_ways.map(_.valid)) === i.U, s"LRU_UpdateCount$i", s"LRU Update $i simultaneous") } } def get_replace_way(state: UInt): UInt = { val moreRecentVec = extractMRUVec(state) // reconstruct lower triangular matrix // For each way, determine if all other ways are more recent val mruWayDec = (0 until n_ways).map { i => val upperMoreRecent = (if (i == n_ways-1) true.B else moreRecentVec(i).apply(n_ways-1,i+1).andR) val lowerMoreRecent = (if (i == 0) true.B else moreRecentVec.map(e => !e(i)).reduce(_ && _)) upperMoreRecent && lowerMoreRecent } OHToUInt(mruWayDec) } def way = get_replace_way(state_reg) def miss = access(way) def hit = {} @deprecated("replace 'replace' with 'way' from abstract class ReplacementPolicy","Rocket Chip 2020.05") def replace: UInt = way } class PseudoLRU(n_ways: Int) extends ReplacementPolicy { // Pseudo-LRU tree algorithm: https://en.wikipedia.org/wiki/Pseudo-LRU#Tree-PLRU // // // - bits storage example for 4-way PLRU binary tree: // bit[2]: ways 3+2 older than ways 1+0 // / \ // bit[1]: way 3 older than way 2 bit[0]: way 1 older than way 0 // // // - bits storage example for 3-way PLRU binary tree: // bit[1]: way 2 older than ways 1+0 // \ // bit[0]: way 1 older than way 0 // // // - bits storage example for 8-way PLRU binary tree: // bit[6]: ways 7-4 older than ways 3-0 // / \ // bit[5]: ways 7+6 > 5+4 bit[2]: ways 3+2 > 1+0 // / \ / \ // bit[4]: way 7>6 bit[3]: way 5>4 bit[1]: way 3>2 bit[0]: way 1>0 def nBits = n_ways - 1 def perSet = true private val state_reg = if (nBits == 0) Reg(UInt(0.W)) else RegInit(0.U(nBits.W)) def state_read = WireDefault(state_reg) def access(touch_way: UInt): Unit = { state_reg := get_next_state(state_reg, touch_way) } def access(touch_ways: Seq[Valid[UInt]]): Unit = { when (touch_ways.map(_.valid).orR) { state_reg := get_next_state(state_reg, touch_ways) } for (i <- 1 until touch_ways.size) { cover(PopCount(touch_ways.map(_.valid)) === i.U, s"PLRU_UpdateCount$i", s"PLRU Update $i simultaneous") } } /** @param state state_reg bits for this sub-tree * @param touch_way touched way encoded value bits for this sub-tree * @param tree_nways number of ways in this sub-tree */ def get_next_state(state: UInt, touch_way: UInt, tree_nways: Int): UInt = { require(state.getWidth == (tree_nways-1), s"wrong state bits width ${state.getWidth} for $tree_nways ways") require(touch_way.getWidth == (log2Ceil(tree_nways) max 1), s"wrong encoded way width ${touch_way.getWidth} for $tree_nways ways") if (tree_nways > 2) { // we are at a branching node in the tree, so recurse val right_nways: Int = 1 << (log2Ceil(tree_nways) - 1) // number of ways in the right sub-tree val left_nways: Int = tree_nways - right_nways // number of ways in the left sub-tree val set_left_older = !touch_way(log2Ceil(tree_nways)-1) val left_subtree_state = state.extract(tree_nways-3, right_nways-1) val right_subtree_state = state(right_nways-2, 0) if (left_nways > 1) { // we are at a branching node in the tree with both left and right sub-trees, so recurse both sub-trees Cat(set_left_older, Mux(set_left_older, left_subtree_state, // if setting left sub-tree as older, do NOT recurse into left sub-tree get_next_state(left_subtree_state, touch_way.extract(log2Ceil(left_nways)-1,0), left_nways)), // recurse left if newer Mux(set_left_older, get_next_state(right_subtree_state, touch_way(log2Ceil(right_nways)-1,0), right_nways), // recurse right if newer right_subtree_state)) // if setting right sub-tree as older, do NOT recurse into right sub-tree } else { // we are at a branching node in the tree with only a right sub-tree, so recurse only right sub-tree Cat(set_left_older, Mux(set_left_older, get_next_state(right_subtree_state, touch_way(log2Ceil(right_nways)-1,0), right_nways), // recurse right if newer right_subtree_state)) // if setting right sub-tree as older, do NOT recurse into right sub-tree } } else if (tree_nways == 2) { // we are at a leaf node at the end of the tree, so set the single state bit opposite of the lsb of the touched way encoded value !touch_way(0) } else { // tree_nways <= 1 // we are at an empty node in an empty tree for 1 way, so return single zero bit for Chisel (no zero-width wires) 0.U(1.W) } } def get_next_state(state: UInt, touch_way: UInt): UInt = { val touch_way_sized = if (touch_way.getWidth < log2Ceil(n_ways)) touch_way.padTo (log2Ceil(n_ways)) else touch_way.extract(log2Ceil(n_ways)-1,0) get_next_state(state, touch_way_sized, n_ways) } /** @param state state_reg bits for this sub-tree * @param tree_nways number of ways in this sub-tree */ def get_replace_way(state: UInt, tree_nways: Int): UInt = { require(state.getWidth == (tree_nways-1), s"wrong state bits width ${state.getWidth} for $tree_nways ways") // this algorithm recursively descends the binary tree, filling in the way-to-replace encoded value from msb to lsb if (tree_nways > 2) { // we are at a branching node in the tree, so recurse val right_nways: Int = 1 << (log2Ceil(tree_nways) - 1) // number of ways in the right sub-tree val left_nways: Int = tree_nways - right_nways // number of ways in the left sub-tree val left_subtree_older = state(tree_nways-2) val left_subtree_state = state.extract(tree_nways-3, right_nways-1) val right_subtree_state = state(right_nways-2, 0) if (left_nways > 1) { // we are at a branching node in the tree with both left and right sub-trees, so recurse both sub-trees Cat(left_subtree_older, // return the top state bit (current tree node) as msb of the way-to-replace encoded value Mux(left_subtree_older, // if left sub-tree is older, recurse left, else recurse right get_replace_way(left_subtree_state, left_nways), // recurse left get_replace_way(right_subtree_state, right_nways))) // recurse right } else { // we are at a branching node in the tree with only a right sub-tree, so recurse only right sub-tree Cat(left_subtree_older, // return the top state bit (current tree node) as msb of the way-to-replace encoded value Mux(left_subtree_older, // if left sub-tree is older, return and do not recurse right 0.U(1.W), get_replace_way(right_subtree_state, right_nways))) // recurse right } } else if (tree_nways == 2) { // we are at a leaf node at the end of the tree, so just return the single state bit as lsb of the way-to-replace encoded value state(0) } else { // tree_nways <= 1 // we are at an empty node in an unbalanced tree for non-power-of-2 ways, so return single zero bit as lsb of the way-to-replace encoded value 0.U(1.W) } } def get_replace_way(state: UInt): UInt = get_replace_way(state, n_ways) def way = get_replace_way(state_reg) def miss = access(way) def hit = {} } class SeqPLRU(n_sets: Int, n_ways: Int) extends SeqReplacementPolicy { val logic = new PseudoLRU(n_ways) val state = SyncReadMem(n_sets, UInt(logic.nBits.W)) val current_state = Wire(UInt(logic.nBits.W)) val next_state = Wire(UInt(logic.nBits.W)) val plru_way = logic.get_replace_way(current_state) def access(set: UInt) = { current_state := state.read(set) } def update(valid: Bool, hit: Bool, set: UInt, way: UInt) = { val update_way = Mux(hit, way, plru_way) next_state := logic.get_next_state(current_state, update_way) when (valid) { state.write(set, next_state) } } def way = plru_way } class SetAssocLRU(n_sets: Int, n_ways: Int, policy: String) extends SetAssocReplacementPolicy { val logic = policy.toLowerCase match { case "plru" => new PseudoLRU(n_ways) case "lru" => new TrueLRU(n_ways) case t => throw new IllegalArgumentException(s"unknown Replacement Policy type $t") } val state_vec = if (logic.nBits == 0) Reg(Vec(n_sets, UInt(logic.nBits.W))) // Work around elaboration error on following line else RegInit(VecInit(Seq.fill(n_sets)(0.U(logic.nBits.W)))) def access(set: UInt, touch_way: UInt) = { state_vec(set) := logic.get_next_state(state_vec(set), touch_way) } def access(sets: Seq[UInt], touch_ways: Seq[Valid[UInt]]) = { require(sets.size == touch_ways.size, "internal consistency check: should be same number of simultaneous updates for sets and touch_ways") for (set <- 0 until n_sets) { val set_touch_ways = (sets zip touch_ways).map { case (touch_set, touch_way) => Pipe(touch_way.valid && (touch_set === set.U), touch_way.bits, 0)} when (set_touch_ways.map(_.valid).orR) { state_vec(set) := logic.get_next_state(state_vec(set), set_touch_ways) } } } def way(set: UInt) = logic.get_replace_way(state_vec(set)) } // Synthesizable unit tests import freechips.rocketchip.unittest._ class PLRUTest(n_ways: Int, timeout: Int = 500) extends UnitTest(timeout) { val plru = new PseudoLRU(n_ways) // step io.finished := RegNext(true.B, false.B) val get_replace_ways = (0 until (1 << (n_ways-1))).map(state => plru.get_replace_way(state = state.U((n_ways-1).W))) val get_next_states = (0 until (1 << (n_ways-1))).map(state => (0 until n_ways).map(way => plru.get_next_state (state = state.U((n_ways-1).W), touch_way = way.U(log2Ceil(n_ways).W)))) n_ways match { case 2 => { assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0)) assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1)) assert(get_next_states(0)(0) === 1.U(plru.nBits.W), s"get_next_state state=0 way=0: expected=1 actual=%d", get_next_states(0)(0)) assert(get_next_states(0)(1) === 0.U(plru.nBits.W), s"get_next_state state=0 way=1: expected=0 actual=%d", get_next_states(0)(1)) assert(get_next_states(1)(0) === 1.U(plru.nBits.W), s"get_next_state state=1 way=0: expected=1 actual=%d", get_next_states(1)(0)) assert(get_next_states(1)(1) === 0.U(plru.nBits.W), s"get_next_state state=1 way=1: expected=0 actual=%d", get_next_states(1)(1)) } case 3 => { assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0)) assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1)) assert(get_replace_ways(2) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=2: expected=2 actual=%d", get_replace_ways(2)) assert(get_replace_ways(3) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=3: expected=2 actual=%d", get_replace_ways(3)) assert(get_next_states(0)(0) === 3.U(plru.nBits.W), s"get_next_state state=0 way=0: expected=3 actual=%d", get_next_states(0)(0)) assert(get_next_states(0)(1) === 2.U(plru.nBits.W), s"get_next_state state=0 way=1: expected=2 actual=%d", get_next_states(0)(1)) assert(get_next_states(0)(2) === 0.U(plru.nBits.W), s"get_next_state state=0 way=2: expected=0 actual=%d", get_next_states(0)(2)) assert(get_next_states(1)(0) === 3.U(plru.nBits.W), s"get_next_state state=1 way=0: expected=3 actual=%d", get_next_states(1)(0)) assert(get_next_states(1)(1) === 2.U(plru.nBits.W), s"get_next_state state=1 way=1: expected=2 actual=%d", get_next_states(1)(1)) assert(get_next_states(1)(2) === 1.U(plru.nBits.W), s"get_next_state state=1 way=2: expected=1 actual=%d", get_next_states(1)(2)) assert(get_next_states(2)(0) === 3.U(plru.nBits.W), s"get_next_state state=2 way=0: expected=3 actual=%d", get_next_states(2)(0)) assert(get_next_states(2)(1) === 2.U(plru.nBits.W), s"get_next_state state=2 way=1: expected=2 actual=%d", get_next_states(2)(1)) assert(get_next_states(2)(2) === 0.U(plru.nBits.W), s"get_next_state state=2 way=2: expected=0 actual=%d", get_next_states(2)(2)) assert(get_next_states(3)(0) === 3.U(plru.nBits.W), s"get_next_state state=3 way=0: expected=3 actual=%d", get_next_states(3)(0)) assert(get_next_states(3)(1) === 2.U(plru.nBits.W), s"get_next_state state=3 way=1: expected=2 actual=%d", get_next_states(3)(1)) assert(get_next_states(3)(2) === 1.U(plru.nBits.W), s"get_next_state state=3 way=2: expected=1 actual=%d", get_next_states(3)(2)) } case 4 => { assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0)) assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1)) assert(get_replace_ways(2) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=2: expected=0 actual=%d", get_replace_ways(2)) assert(get_replace_ways(3) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=3: expected=1 actual=%d", get_replace_ways(3)) assert(get_replace_ways(4) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=4: expected=2 actual=%d", get_replace_ways(4)) assert(get_replace_ways(5) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=5: expected=2 actual=%d", get_replace_ways(5)) assert(get_replace_ways(6) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=6: expected=3 actual=%d", get_replace_ways(6)) assert(get_replace_ways(7) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=7: expected=3 actual=%d", get_replace_ways(7)) assert(get_next_states(0)(0) === 5.U(plru.nBits.W), s"get_next_state state=0 way=0: expected=5 actual=%d", get_next_states(0)(0)) assert(get_next_states(0)(1) === 4.U(plru.nBits.W), s"get_next_state state=0 way=1: expected=4 actual=%d", get_next_states(0)(1)) assert(get_next_states(0)(2) === 2.U(plru.nBits.W), s"get_next_state state=0 way=2: expected=2 actual=%d", get_next_states(0)(2)) assert(get_next_states(0)(3) === 0.U(plru.nBits.W), s"get_next_state state=0 way=3: expected=0 actual=%d", get_next_states(0)(3)) assert(get_next_states(1)(0) === 5.U(plru.nBits.W), s"get_next_state state=1 way=0: expected=5 actual=%d", get_next_states(1)(0)) assert(get_next_states(1)(1) === 4.U(plru.nBits.W), s"get_next_state state=1 way=1: expected=4 actual=%d", get_next_states(1)(1)) assert(get_next_states(1)(2) === 3.U(plru.nBits.W), s"get_next_state state=1 way=2: expected=3 actual=%d", get_next_states(1)(2)) assert(get_next_states(1)(3) === 1.U(plru.nBits.W), s"get_next_state state=1 way=3: expected=1 actual=%d", get_next_states(1)(3)) assert(get_next_states(2)(0) === 7.U(plru.nBits.W), s"get_next_state state=2 way=0: expected=7 actual=%d", get_next_states(2)(0)) assert(get_next_states(2)(1) === 6.U(plru.nBits.W), s"get_next_state state=2 way=1: expected=6 actual=%d", get_next_states(2)(1)) assert(get_next_states(2)(2) === 2.U(plru.nBits.W), s"get_next_state state=2 way=2: expected=2 actual=%d", get_next_states(2)(2)) assert(get_next_states(2)(3) === 0.U(plru.nBits.W), s"get_next_state state=2 way=3: expected=0 actual=%d", get_next_states(2)(3)) assert(get_next_states(3)(0) === 7.U(plru.nBits.W), s"get_next_state state=3 way=0: expected=7 actual=%d", get_next_states(3)(0)) assert(get_next_states(3)(1) === 6.U(plru.nBits.W), s"get_next_state state=3 way=1: expected=6 actual=%d", get_next_states(3)(1)) assert(get_next_states(3)(2) === 3.U(plru.nBits.W), s"get_next_state state=3 way=2: expected=3 actual=%d", get_next_states(3)(2)) assert(get_next_states(3)(3) === 1.U(plru.nBits.W), s"get_next_state state=3 way=3: expected=1 actual=%d", get_next_states(3)(3)) assert(get_next_states(4)(0) === 5.U(plru.nBits.W), s"get_next_state state=4 way=0: expected=5 actual=%d", get_next_states(4)(0)) assert(get_next_states(4)(1) === 4.U(plru.nBits.W), s"get_next_state state=4 way=1: expected=4 actual=%d", get_next_states(4)(1)) assert(get_next_states(4)(2) === 2.U(plru.nBits.W), s"get_next_state state=4 way=2: expected=2 actual=%d", get_next_states(4)(2)) assert(get_next_states(4)(3) === 0.U(plru.nBits.W), s"get_next_state state=4 way=3: expected=0 actual=%d", get_next_states(4)(3)) assert(get_next_states(5)(0) === 5.U(plru.nBits.W), s"get_next_state state=5 way=0: expected=5 actual=%d", get_next_states(5)(0)) assert(get_next_states(5)(1) === 4.U(plru.nBits.W), s"get_next_state state=5 way=1: expected=4 actual=%d", get_next_states(5)(1)) assert(get_next_states(5)(2) === 3.U(plru.nBits.W), s"get_next_state state=5 way=2: expected=3 actual=%d", get_next_states(5)(2)) assert(get_next_states(5)(3) === 1.U(plru.nBits.W), s"get_next_state state=5 way=3: expected=1 actual=%d", get_next_states(5)(3)) assert(get_next_states(6)(0) === 7.U(plru.nBits.W), s"get_next_state state=6 way=0: expected=7 actual=%d", get_next_states(6)(0)) assert(get_next_states(6)(1) === 6.U(plru.nBits.W), s"get_next_state state=6 way=1: expected=6 actual=%d", get_next_states(6)(1)) assert(get_next_states(6)(2) === 2.U(plru.nBits.W), s"get_next_state state=6 way=2: expected=2 actual=%d", get_next_states(6)(2)) assert(get_next_states(6)(3) === 0.U(plru.nBits.W), s"get_next_state state=6 way=3: expected=0 actual=%d", get_next_states(6)(3)) assert(get_next_states(7)(0) === 7.U(plru.nBits.W), s"get_next_state state=7 way=0: expected=7 actual=%d", get_next_states(7)(0)) assert(get_next_states(7)(1) === 6.U(plru.nBits.W), s"get_next_state state=7 way=5: expected=6 actual=%d", get_next_states(7)(1)) assert(get_next_states(7)(2) === 3.U(plru.nBits.W), s"get_next_state state=7 way=2: expected=3 actual=%d", get_next_states(7)(2)) assert(get_next_states(7)(3) === 1.U(plru.nBits.W), s"get_next_state state=7 way=3: expected=1 actual=%d", get_next_states(7)(3)) } case 5 => { assert(get_replace_ways( 0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=00: expected=0 actual=%d", get_replace_ways( 0)) assert(get_replace_ways( 1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=01: expected=1 actual=%d", get_replace_ways( 1)) assert(get_replace_ways( 2) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=02: expected=0 actual=%d", get_replace_ways( 2)) assert(get_replace_ways( 3) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=03: expected=1 actual=%d", get_replace_ways( 3)) assert(get_replace_ways( 4) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=04: expected=2 actual=%d", get_replace_ways( 4)) assert(get_replace_ways( 5) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=05: expected=2 actual=%d", get_replace_ways( 5)) assert(get_replace_ways( 6) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=06: expected=3 actual=%d", get_replace_ways( 6)) assert(get_replace_ways( 7) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=07: expected=3 actual=%d", get_replace_ways( 7)) assert(get_replace_ways( 8) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=08: expected=4 actual=%d", get_replace_ways( 8)) assert(get_replace_ways( 9) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=09: expected=4 actual=%d", get_replace_ways( 9)) assert(get_replace_ways(10) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=10: expected=4 actual=%d", get_replace_ways(10)) assert(get_replace_ways(11) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=11: expected=4 actual=%d", get_replace_ways(11)) assert(get_replace_ways(12) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=12: expected=4 actual=%d", get_replace_ways(12)) assert(get_replace_ways(13) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=13: expected=4 actual=%d", get_replace_ways(13)) assert(get_replace_ways(14) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=14: expected=4 actual=%d", get_replace_ways(14)) assert(get_replace_ways(15) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=15: expected=4 actual=%d", get_replace_ways(15)) assert(get_next_states( 0)(0) === 13.U(plru.nBits.W), s"get_next_state state=00 way=0: expected=13 actual=%d", get_next_states( 0)(0)) assert(get_next_states( 0)(1) === 12.U(plru.nBits.W), s"get_next_state state=00 way=1: expected=12 actual=%d", get_next_states( 0)(1)) assert(get_next_states( 0)(2) === 10.U(plru.nBits.W), s"get_next_state state=00 way=2: expected=10 actual=%d", get_next_states( 0)(2)) assert(get_next_states( 0)(3) === 8.U(plru.nBits.W), s"get_next_state state=00 way=3: expected=08 actual=%d", get_next_states( 0)(3)) assert(get_next_states( 0)(4) === 0.U(plru.nBits.W), s"get_next_state state=00 way=4: expected=00 actual=%d", get_next_states( 0)(4)) assert(get_next_states( 1)(0) === 13.U(plru.nBits.W), s"get_next_state state=01 way=0: expected=13 actual=%d", get_next_states( 1)(0)) assert(get_next_states( 1)(1) === 12.U(plru.nBits.W), s"get_next_state state=01 way=1: expected=12 actual=%d", get_next_states( 1)(1)) assert(get_next_states( 1)(2) === 11.U(plru.nBits.W), s"get_next_state state=01 way=2: expected=11 actual=%d", get_next_states( 1)(2)) assert(get_next_states( 1)(3) === 9.U(plru.nBits.W), s"get_next_state state=01 way=3: expected=09 actual=%d", get_next_states( 1)(3)) assert(get_next_states( 1)(4) === 1.U(plru.nBits.W), s"get_next_state state=01 way=4: expected=01 actual=%d", get_next_states( 1)(4)) assert(get_next_states( 2)(0) === 15.U(plru.nBits.W), s"get_next_state state=02 way=0: expected=15 actual=%d", get_next_states( 2)(0)) assert(get_next_states( 2)(1) === 14.U(plru.nBits.W), s"get_next_state state=02 way=1: expected=14 actual=%d", get_next_states( 2)(1)) assert(get_next_states( 2)(2) === 10.U(plru.nBits.W), s"get_next_state state=02 way=2: expected=10 actual=%d", get_next_states( 2)(2)) assert(get_next_states( 2)(3) === 8.U(plru.nBits.W), s"get_next_state state=02 way=3: expected=08 actual=%d", get_next_states( 2)(3)) assert(get_next_states( 2)(4) === 2.U(plru.nBits.W), s"get_next_state state=02 way=4: expected=02 actual=%d", get_next_states( 2)(4)) assert(get_next_states( 3)(0) === 15.U(plru.nBits.W), s"get_next_state state=03 way=0: expected=15 actual=%d", get_next_states( 3)(0)) assert(get_next_states( 3)(1) === 14.U(plru.nBits.W), s"get_next_state state=03 way=1: expected=14 actual=%d", get_next_states( 3)(1)) assert(get_next_states( 3)(2) === 11.U(plru.nBits.W), s"get_next_state state=03 way=2: expected=11 actual=%d", get_next_states( 3)(2)) assert(get_next_states( 3)(3) === 9.U(plru.nBits.W), s"get_next_state state=03 way=3: expected=09 actual=%d", get_next_states( 3)(3)) assert(get_next_states( 3)(4) === 3.U(plru.nBits.W), s"get_next_state state=03 way=4: expected=03 actual=%d", get_next_states( 3)(4)) assert(get_next_states( 4)(0) === 13.U(plru.nBits.W), s"get_next_state state=04 way=0: expected=13 actual=%d", get_next_states( 4)(0)) assert(get_next_states( 4)(1) === 12.U(plru.nBits.W), s"get_next_state state=04 way=1: expected=12 actual=%d", get_next_states( 4)(1)) assert(get_next_states( 4)(2) === 10.U(plru.nBits.W), s"get_next_state state=04 way=2: expected=10 actual=%d", get_next_states( 4)(2)) assert(get_next_states( 4)(3) === 8.U(plru.nBits.W), s"get_next_state state=04 way=3: expected=08 actual=%d", get_next_states( 4)(3)) assert(get_next_states( 4)(4) === 4.U(plru.nBits.W), s"get_next_state state=04 way=4: expected=04 actual=%d", get_next_states( 4)(4)) assert(get_next_states( 5)(0) === 13.U(plru.nBits.W), s"get_next_state state=05 way=0: expected=13 actual=%d", get_next_states( 5)(0)) assert(get_next_states( 5)(1) === 12.U(plru.nBits.W), s"get_next_state state=05 way=1: expected=12 actual=%d", get_next_states( 5)(1)) assert(get_next_states( 5)(2) === 11.U(plru.nBits.W), s"get_next_state state=05 way=2: expected=11 actual=%d", get_next_states( 5)(2)) assert(get_next_states( 5)(3) === 9.U(plru.nBits.W), s"get_next_state state=05 way=3: expected=09 actual=%d", get_next_states( 5)(3)) assert(get_next_states( 5)(4) === 5.U(plru.nBits.W), s"get_next_state state=05 way=4: expected=05 actual=%d", get_next_states( 5)(4)) assert(get_next_states( 6)(0) === 15.U(plru.nBits.W), s"get_next_state state=06 way=0: expected=15 actual=%d", get_next_states( 6)(0)) assert(get_next_states( 6)(1) === 14.U(plru.nBits.W), s"get_next_state state=06 way=1: expected=14 actual=%d", get_next_states( 6)(1)) assert(get_next_states( 6)(2) === 10.U(plru.nBits.W), s"get_next_state state=06 way=2: expected=10 actual=%d", get_next_states( 6)(2)) assert(get_next_states( 6)(3) === 8.U(plru.nBits.W), s"get_next_state state=06 way=3: expected=08 actual=%d", get_next_states( 6)(3)) assert(get_next_states( 6)(4) === 6.U(plru.nBits.W), s"get_next_state state=06 way=4: expected=06 actual=%d", get_next_states( 6)(4)) assert(get_next_states( 7)(0) === 15.U(plru.nBits.W), s"get_next_state state=07 way=0: expected=15 actual=%d", get_next_states( 7)(0)) assert(get_next_states( 7)(1) === 14.U(plru.nBits.W), s"get_next_state state=07 way=5: expected=14 actual=%d", get_next_states( 7)(1)) assert(get_next_states( 7)(2) === 11.U(plru.nBits.W), s"get_next_state state=07 way=2: expected=11 actual=%d", get_next_states( 7)(2)) assert(get_next_states( 7)(3) === 9.U(plru.nBits.W), s"get_next_state state=07 way=3: expected=09 actual=%d", get_next_states( 7)(3)) assert(get_next_states( 7)(4) === 7.U(plru.nBits.W), s"get_next_state state=07 way=4: expected=07 actual=%d", get_next_states( 7)(4)) assert(get_next_states( 8)(0) === 13.U(plru.nBits.W), s"get_next_state state=08 way=0: expected=13 actual=%d", get_next_states( 8)(0)) assert(get_next_states( 8)(1) === 12.U(plru.nBits.W), s"get_next_state state=08 way=1: expected=12 actual=%d", get_next_states( 8)(1)) assert(get_next_states( 8)(2) === 10.U(plru.nBits.W), s"get_next_state state=08 way=2: expected=10 actual=%d", get_next_states( 8)(2)) assert(get_next_states( 8)(3) === 8.U(plru.nBits.W), s"get_next_state state=08 way=3: expected=08 actual=%d", get_next_states( 8)(3)) assert(get_next_states( 8)(4) === 0.U(plru.nBits.W), s"get_next_state state=08 way=4: expected=00 actual=%d", get_next_states( 8)(4)) assert(get_next_states( 9)(0) === 13.U(plru.nBits.W), s"get_next_state state=09 way=0: expected=13 actual=%d", get_next_states( 9)(0)) assert(get_next_states( 9)(1) === 12.U(plru.nBits.W), s"get_next_state state=09 way=1: expected=12 actual=%d", get_next_states( 9)(1)) assert(get_next_states( 9)(2) === 11.U(plru.nBits.W), s"get_next_state state=09 way=2: expected=11 actual=%d", get_next_states( 9)(2)) assert(get_next_states( 9)(3) === 9.U(plru.nBits.W), s"get_next_state state=09 way=3: expected=09 actual=%d", get_next_states( 9)(3)) assert(get_next_states( 9)(4) === 1.U(plru.nBits.W), s"get_next_state state=09 way=4: expected=01 actual=%d", get_next_states( 9)(4)) assert(get_next_states(10)(0) === 15.U(plru.nBits.W), s"get_next_state state=10 way=0: expected=15 actual=%d", get_next_states(10)(0)) assert(get_next_states(10)(1) === 14.U(plru.nBits.W), s"get_next_state state=10 way=1: expected=14 actual=%d", get_next_states(10)(1)) assert(get_next_states(10)(2) === 10.U(plru.nBits.W), s"get_next_state state=10 way=2: expected=10 actual=%d", get_next_states(10)(2)) assert(get_next_states(10)(3) === 8.U(plru.nBits.W), s"get_next_state state=10 way=3: expected=08 actual=%d", get_next_states(10)(3)) assert(get_next_states(10)(4) === 2.U(plru.nBits.W), s"get_next_state state=10 way=4: expected=02 actual=%d", get_next_states(10)(4)) assert(get_next_states(11)(0) === 15.U(plru.nBits.W), s"get_next_state state=11 way=0: expected=15 actual=%d", get_next_states(11)(0)) assert(get_next_states(11)(1) === 14.U(plru.nBits.W), s"get_next_state state=11 way=1: expected=14 actual=%d", get_next_states(11)(1)) assert(get_next_states(11)(2) === 11.U(plru.nBits.W), s"get_next_state state=11 way=2: expected=11 actual=%d", get_next_states(11)(2)) assert(get_next_states(11)(3) === 9.U(plru.nBits.W), s"get_next_state state=11 way=3: expected=09 actual=%d", get_next_states(11)(3)) assert(get_next_states(11)(4) === 3.U(plru.nBits.W), s"get_next_state state=11 way=4: expected=03 actual=%d", get_next_states(11)(4)) assert(get_next_states(12)(0) === 13.U(plru.nBits.W), s"get_next_state state=12 way=0: expected=13 actual=%d", get_next_states(12)(0)) assert(get_next_states(12)(1) === 12.U(plru.nBits.W), s"get_next_state state=12 way=1: expected=12 actual=%d", get_next_states(12)(1)) assert(get_next_states(12)(2) === 10.U(plru.nBits.W), s"get_next_state state=12 way=2: expected=10 actual=%d", get_next_states(12)(2)) assert(get_next_states(12)(3) === 8.U(plru.nBits.W), s"get_next_state state=12 way=3: expected=08 actual=%d", get_next_states(12)(3)) assert(get_next_states(12)(4) === 4.U(plru.nBits.W), s"get_next_state state=12 way=4: expected=04 actual=%d", get_next_states(12)(4)) assert(get_next_states(13)(0) === 13.U(plru.nBits.W), s"get_next_state state=13 way=0: expected=13 actual=%d", get_next_states(13)(0)) assert(get_next_states(13)(1) === 12.U(plru.nBits.W), s"get_next_state state=13 way=1: expected=12 actual=%d", get_next_states(13)(1)) assert(get_next_states(13)(2) === 11.U(plru.nBits.W), s"get_next_state state=13 way=2: expected=11 actual=%d", get_next_states(13)(2)) assert(get_next_states(13)(3) === 9.U(plru.nBits.W), s"get_next_state state=13 way=3: expected=09 actual=%d", get_next_states(13)(3)) assert(get_next_states(13)(4) === 5.U(plru.nBits.W), s"get_next_state state=13 way=4: expected=05 actual=%d", get_next_states(13)(4)) assert(get_next_states(14)(0) === 15.U(plru.nBits.W), s"get_next_state state=14 way=0: expected=15 actual=%d", get_next_states(14)(0)) assert(get_next_states(14)(1) === 14.U(plru.nBits.W), s"get_next_state state=14 way=1: expected=14 actual=%d", get_next_states(14)(1)) assert(get_next_states(14)(2) === 10.U(plru.nBits.W), s"get_next_state state=14 way=2: expected=10 actual=%d", get_next_states(14)(2)) assert(get_next_states(14)(3) === 8.U(plru.nBits.W), s"get_next_state state=14 way=3: expected=08 actual=%d", get_next_states(14)(3)) assert(get_next_states(14)(4) === 6.U(plru.nBits.W), s"get_next_state state=14 way=4: expected=06 actual=%d", get_next_states(14)(4)) assert(get_next_states(15)(0) === 15.U(plru.nBits.W), s"get_next_state state=15 way=0: expected=15 actual=%d", get_next_states(15)(0)) assert(get_next_states(15)(1) === 14.U(plru.nBits.W), s"get_next_state state=15 way=5: expected=14 actual=%d", get_next_states(15)(1)) assert(get_next_states(15)(2) === 11.U(plru.nBits.W), s"get_next_state state=15 way=2: expected=11 actual=%d", get_next_states(15)(2)) assert(get_next_states(15)(3) === 9.U(plru.nBits.W), s"get_next_state state=15 way=3: expected=09 actual=%d", get_next_states(15)(3)) assert(get_next_states(15)(4) === 7.U(plru.nBits.W), s"get_next_state state=15 way=4: expected=07 actual=%d", get_next_states(15)(4)) } case 6 => { assert(get_replace_ways( 0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=00: expected=0 actual=%d", get_replace_ways( 0)) assert(get_replace_ways( 1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=01: expected=1 actual=%d", get_replace_ways( 1)) assert(get_replace_ways( 2) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=02: expected=0 actual=%d", get_replace_ways( 2)) assert(get_replace_ways( 3) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=03: expected=1 actual=%d", get_replace_ways( 3)) assert(get_replace_ways( 4) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=04: expected=2 actual=%d", get_replace_ways( 4)) assert(get_replace_ways( 5) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=05: expected=2 actual=%d", get_replace_ways( 5)) assert(get_replace_ways( 6) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=06: expected=3 actual=%d", get_replace_ways( 6)) assert(get_replace_ways( 7) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=07: expected=3 actual=%d", get_replace_ways( 7)) assert(get_replace_ways( 8) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=08: expected=0 actual=%d", get_replace_ways( 8)) assert(get_replace_ways( 9) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=09: expected=1 actual=%d", get_replace_ways( 9)) assert(get_replace_ways(10) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=10: expected=0 actual=%d", get_replace_ways(10)) assert(get_replace_ways(11) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=11: expected=1 actual=%d", get_replace_ways(11)) assert(get_replace_ways(12) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=12: expected=2 actual=%d", get_replace_ways(12)) assert(get_replace_ways(13) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=13: expected=2 actual=%d", get_replace_ways(13)) assert(get_replace_ways(14) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=14: expected=3 actual=%d", get_replace_ways(14)) assert(get_replace_ways(15) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=15: expected=3 actual=%d", get_replace_ways(15)) assert(get_replace_ways(16) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=16: expected=4 actual=%d", get_replace_ways(16)) assert(get_replace_ways(17) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=17: expected=4 actual=%d", get_replace_ways(17)) assert(get_replace_ways(18) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=18: expected=4 actual=%d", get_replace_ways(18)) assert(get_replace_ways(19) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=19: expected=4 actual=%d", get_replace_ways(19)) assert(get_replace_ways(20) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=20: expected=4 actual=%d", get_replace_ways(20)) assert(get_replace_ways(21) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=21: expected=4 actual=%d", get_replace_ways(21)) assert(get_replace_ways(22) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=22: expected=4 actual=%d", get_replace_ways(22)) assert(get_replace_ways(23) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=23: expected=4 actual=%d", get_replace_ways(23)) assert(get_replace_ways(24) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=24: expected=5 actual=%d", get_replace_ways(24)) assert(get_replace_ways(25) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=25: expected=5 actual=%d", get_replace_ways(25)) assert(get_replace_ways(26) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=26: expected=5 actual=%d", get_replace_ways(26)) assert(get_replace_ways(27) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=27: expected=5 actual=%d", get_replace_ways(27)) assert(get_replace_ways(28) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=28: expected=5 actual=%d", get_replace_ways(28)) assert(get_replace_ways(29) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=29: expected=5 actual=%d", get_replace_ways(29)) assert(get_replace_ways(30) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=30: expected=5 actual=%d", get_replace_ways(30)) assert(get_replace_ways(31) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=31: expected=5 actual=%d", get_replace_ways(31)) } case _ => throw new IllegalArgumentException(s"no test pattern found for n_ways=$n_ways") } } File Consts.scala: // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket.constants import chisel3._ import chisel3.util._ import freechips.rocketchip.util._ trait ScalarOpConstants { val SZ_BR = 3 def BR_X = BitPat("b???") def BR_EQ = 0.U(3.W) def BR_NE = 1.U(3.W) def BR_J = 2.U(3.W) def BR_N = 3.U(3.W) def BR_LT = 4.U(3.W) def BR_GE = 5.U(3.W) def BR_LTU = 6.U(3.W) def BR_GEU = 7.U(3.W) def A1_X = BitPat("b??") def A1_ZERO = 0.U(2.W) def A1_RS1 = 1.U(2.W) def A1_PC = 2.U(2.W) def A1_RS1SHL = 3.U(2.W) def IMM_X = BitPat("b???") def IMM_S = 0.U(3.W) def IMM_SB = 1.U(3.W) def IMM_U = 2.U(3.W) def IMM_UJ = 3.U(3.W) def IMM_I = 4.U(3.W) def IMM_Z = 5.U(3.W) def A2_X = BitPat("b???") def A2_ZERO = 0.U(3.W) def A2_SIZE = 1.U(3.W) def A2_RS2 = 2.U(3.W) def A2_IMM = 3.U(3.W) def A2_RS2OH = 4.U(3.W) def A2_IMMOH = 5.U(3.W) def X = BitPat("b?") def N = BitPat("b0") def Y = BitPat("b1") val SZ_DW = 1 def DW_X = X def DW_32 = false.B def DW_64 = true.B def DW_XPR = DW_64 } trait MemoryOpConstants { val NUM_XA_OPS = 9 val M_SZ = 5 def M_X = BitPat("b?????"); def M_XRD = "b00000".U; // int load def M_XWR = "b00001".U; // int store def M_PFR = "b00010".U; // prefetch with intent to read def M_PFW = "b00011".U; // prefetch with intent to write def M_XA_SWAP = "b00100".U def M_FLUSH_ALL = "b00101".U // flush all lines def M_XLR = "b00110".U def M_XSC = "b00111".U def M_XA_ADD = "b01000".U def M_XA_XOR = "b01001".U def M_XA_OR = "b01010".U def M_XA_AND = "b01011".U def M_XA_MIN = "b01100".U def M_XA_MAX = "b01101".U def M_XA_MINU = "b01110".U def M_XA_MAXU = "b01111".U def M_FLUSH = "b10000".U // write back dirty data and cede R/W permissions def M_PWR = "b10001".U // partial (masked) store def M_PRODUCE = "b10010".U // write back dirty data and cede W permissions def M_CLEAN = "b10011".U // write back dirty data and retain R/W permissions def M_SFENCE = "b10100".U // SFENCE.VMA def M_HFENCEV = "b10101".U // HFENCE.VVMA def M_HFENCEG = "b10110".U // HFENCE.GVMA def M_WOK = "b10111".U // check write permissions but don't perform a write def M_HLVX = "b10000".U // HLVX instruction def isAMOLogical(cmd: UInt) = cmd.isOneOf(M_XA_SWAP, M_XA_XOR, M_XA_OR, M_XA_AND) def isAMOArithmetic(cmd: UInt) = cmd.isOneOf(M_XA_ADD, M_XA_MIN, M_XA_MAX, M_XA_MINU, M_XA_MAXU) def isAMO(cmd: UInt) = isAMOLogical(cmd) || isAMOArithmetic(cmd) def isPrefetch(cmd: UInt) = cmd === M_PFR || cmd === M_PFW def isRead(cmd: UInt) = cmd.isOneOf(M_XRD, M_HLVX, M_XLR, M_XSC) || isAMO(cmd) def isWrite(cmd: UInt) = cmd === M_XWR || cmd === M_PWR || cmd === M_XSC || isAMO(cmd) def isWriteIntent(cmd: UInt) = isWrite(cmd) || cmd === M_PFW || cmd === M_XLR } File TLB.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import freechips.rocketchip.devices.debug.DebugModuleKey import freechips.rocketchip.diplomacy.RegionType import freechips.rocketchip.subsystem.CacheBlockBytes import freechips.rocketchip.tile.{CoreModule, CoreBundle} import freechips.rocketchip.tilelink._ import freechips.rocketchip.util.{OptimizationBarrier, SetAssocLRU, PseudoLRU, PopCountAtLeast, property} import freechips.rocketchip.util.BooleanToAugmentedBoolean import freechips.rocketchip.util.IntToAugmentedInt import freechips.rocketchip.util.UIntToAugmentedUInt import freechips.rocketchip.util.UIntIsOneOf import freechips.rocketchip.util.SeqToAugmentedSeq import freechips.rocketchip.util.SeqBoolBitwiseOps case object ASIdBits extends Field[Int](0) case object VMIdBits extends Field[Int](0) /** =SFENCE= * rs1 rs2 * {{{ * 0 0 -> flush All * 0 1 -> flush by ASID * 1 1 -> flush by ADDR * 1 0 -> flush by ADDR and ASID * }}} * {{{ * If rs1=x0 and rs2=x0, the fence orders all reads and writes made to any level of the page tables, for all address spaces. * If rs1=x0 and rs2!=x0, the fence orders all reads and writes made to any level of the page tables, but only for the address space identified by integer register rs2. Accesses to global mappings (see Section 4.3.1) are not ordered. * If rs1!=x0 and rs2=x0, the fence orders only reads and writes made to the leaf page table entry corresponding to the virtual address in rs1, for all address spaces. * If rs1!=x0 and rs2!=x0, the fence orders only reads and writes made to the leaf page table entry corresponding to the virtual address in rs1, for the address space identified by integer register rs2. Accesses to global mappings are not ordered. * }}} */ class SFenceReq(implicit p: Parameters) extends CoreBundle()(p) { val rs1 = Bool() val rs2 = Bool() val addr = UInt(vaddrBits.W) val asid = UInt((asIdBits max 1).W) // TODO zero-width val hv = Bool() val hg = Bool() } class TLBReq(lgMaxSize: Int)(implicit p: Parameters) extends CoreBundle()(p) { /** request address from CPU. */ val vaddr = UInt(vaddrBitsExtended.W) /** don't lookup TLB, bypass vaddr as paddr */ val passthrough = Bool() /** granularity */ val size = UInt(log2Ceil(lgMaxSize + 1).W) /** memory command. */ val cmd = Bits(M_SZ.W) val prv = UInt(PRV.SZ.W) /** virtualization mode */ val v = Bool() } class TLBExceptions extends Bundle { val ld = Bool() val st = Bool() val inst = Bool() } class TLBResp(lgMaxSize: Int = 3)(implicit p: Parameters) extends CoreBundle()(p) { // lookup responses val miss = Bool() /** physical address */ val paddr = UInt(paddrBits.W) val gpa = UInt(vaddrBitsExtended.W) val gpa_is_pte = Bool() /** page fault exception */ val pf = new TLBExceptions /** guest page fault exception */ val gf = new TLBExceptions /** access exception */ val ae = new TLBExceptions /** misaligned access exception */ val ma = new TLBExceptions /** if this address is cacheable */ val cacheable = Bool() /** if caches must allocate this address */ val must_alloc = Bool() /** if this address is prefetchable for caches*/ val prefetchable = Bool() /** size/cmd of request that generated this response*/ val size = UInt(log2Ceil(lgMaxSize + 1).W) val cmd = UInt(M_SZ.W) } class TLBEntryData(implicit p: Parameters) extends CoreBundle()(p) { val ppn = UInt(ppnBits.W) /** pte.u user */ val u = Bool() /** pte.g global */ val g = Bool() /** access exception. * D$ -> PTW -> TLB AE * Alignment failed. */ val ae_ptw = Bool() val ae_final = Bool() val ae_stage2 = Bool() /** page fault */ val pf = Bool() /** guest page fault */ val gf = Bool() /** supervisor write */ val sw = Bool() /** supervisor execute */ val sx = Bool() /** supervisor read */ val sr = Bool() /** hypervisor write */ val hw = Bool() /** hypervisor excute */ val hx = Bool() /** hypervisor read */ val hr = Bool() /** prot_w */ val pw = Bool() /** prot_x */ val px = Bool() /** prot_r */ val pr = Bool() /** PutPartial */ val ppp = Bool() /** AMO logical */ val pal = Bool() /** AMO arithmetic */ val paa = Bool() /** get/put effects */ val eff = Bool() /** cacheable */ val c = Bool() /** fragmented_superpage support */ val fragmented_superpage = Bool() } /** basic cell for TLB data */ class TLBEntry(val nSectors: Int, val superpage: Boolean, val superpageOnly: Boolean)(implicit p: Parameters) extends CoreBundle()(p) { require(nSectors == 1 || !superpage) require(!superpageOnly || superpage) val level = UInt(log2Ceil(pgLevels).W) /** use vpn as tag */ val tag_vpn = UInt(vpnBits.W) /** tag in vitualization mode */ val tag_v = Bool() /** entry data */ val data = Vec(nSectors, UInt(new TLBEntryData().getWidth.W)) /** valid bit */ val valid = Vec(nSectors, Bool()) /** returns all entry data in this entry */ def entry_data = data.map(_.asTypeOf(new TLBEntryData)) /** returns the index of sector */ private def sectorIdx(vpn: UInt) = vpn.extract(nSectors.log2-1, 0) /** returns the entry data matched with this vpn*/ def getData(vpn: UInt) = OptimizationBarrier(data(sectorIdx(vpn)).asTypeOf(new TLBEntryData)) /** returns whether a sector hits */ def sectorHit(vpn: UInt, virtual: Bool) = valid.orR && sectorTagMatch(vpn, virtual) /** returns whether tag matches vpn */ def sectorTagMatch(vpn: UInt, virtual: Bool) = (((tag_vpn ^ vpn) >> nSectors.log2) === 0.U) && (tag_v === virtual) /** returns hit signal */ def hit(vpn: UInt, virtual: Bool): Bool = { if (superpage && usingVM) { var tagMatch = valid.head && (tag_v === virtual) for (j <- 0 until pgLevels) { val base = (pgLevels - 1 - j) * pgLevelBits val n = pgLevelBits + (if (j == 0) hypervisorExtraAddrBits else 0) val ignore = level < j.U || (superpageOnly && j == pgLevels - 1).B tagMatch = tagMatch && (ignore || (tag_vpn ^ vpn)(base + n - 1, base) === 0.U) } tagMatch } else { val idx = sectorIdx(vpn) valid(idx) && sectorTagMatch(vpn, virtual) } } /** returns the ppn of the input TLBEntryData */ def ppn(vpn: UInt, data: TLBEntryData) = { val supervisorVPNBits = pgLevels * pgLevelBits if (superpage && usingVM) { var res = data.ppn >> pgLevelBits*(pgLevels - 1) for (j <- 1 until pgLevels) { val ignore = level < j.U || (superpageOnly && j == pgLevels - 1).B res = Cat(res, (Mux(ignore, vpn, 0.U) | data.ppn)(supervisorVPNBits - j*pgLevelBits - 1, supervisorVPNBits - (j + 1)*pgLevelBits)) } res } else { data.ppn } } /** does the refill * * find the target entry with vpn tag * and replace the target entry with the input entry data */ def insert(vpn: UInt, virtual: Bool, level: UInt, entry: TLBEntryData): Unit = { this.tag_vpn := vpn this.tag_v := virtual this.level := level.extract(log2Ceil(pgLevels - superpageOnly.toInt)-1, 0) val idx = sectorIdx(vpn) valid(idx) := true.B data(idx) := entry.asUInt } def invalidate(): Unit = { valid.foreach(_ := false.B) } def invalidate(virtual: Bool): Unit = { for ((v, e) <- valid zip entry_data) when (tag_v === virtual) { v := false.B } } def invalidateVPN(vpn: UInt, virtual: Bool): Unit = { if (superpage) { when (hit(vpn, virtual)) { invalidate() } } else { when (sectorTagMatch(vpn, virtual)) { for (((v, e), i) <- (valid zip entry_data).zipWithIndex) when (tag_v === virtual && i.U === sectorIdx(vpn)) { v := false.B } } } // For fragmented superpage mappings, we assume the worst (largest) // case, and zap entries whose most-significant VPNs match when (((tag_vpn ^ vpn) >> (pgLevelBits * (pgLevels - 1))) === 0.U) { for ((v, e) <- valid zip entry_data) when (tag_v === virtual && e.fragmented_superpage) { v := false.B } } } def invalidateNonGlobal(virtual: Bool): Unit = { for ((v, e) <- valid zip entry_data) when (tag_v === virtual && !e.g) { v := false.B } } } /** TLB config * * @param nSets the number of sets of PTE, follow [[ICacheParams.nSets]] * @param nWays the total number of wayss of PTE, follow [[ICacheParams.nWays]] * @param nSectors the number of ways in a single PTE TLBEntry * @param nSuperpageEntries the number of SuperpageEntries */ case class TLBConfig( nSets: Int, nWays: Int, nSectors: Int = 4, nSuperpageEntries: Int = 4) /** =Overview= * [[TLB]] is a TLB template which contains PMA logic and PMP checker. * * TLB caches PTE and accelerates the address translation process. * When tlb miss happens, ask PTW(L2TLB) for Page Table Walk. * Perform PMP and PMA check during the translation and throw exception if there were any. * * ==Cache Structure== * - Sectored Entry (PTE) * - set-associative or direct-mapped * - nsets = [[TLBConfig.nSets]] * - nways = [[TLBConfig.nWays]] / [[TLBConfig.nSectors]] * - PTEEntry( sectors = [[TLBConfig.nSectors]] ) * - LRU(if set-associative) * * - Superpage Entry(superpage PTE) * - fully associative * - nsets = [[TLBConfig.nSuperpageEntries]] * - PTEEntry(sectors = 1) * - PseudoLRU * * - Special Entry(PTE across PMP) * - nsets = 1 * - PTEEntry(sectors = 1) * * ==Address structure== * {{{ * |vaddr | * |ppn/vpn | pgIndex | * | | | * | |nSets |nSector | |}}} * * ==State Machine== * {{{ * s_ready: ready to accept request from CPU. * s_request: when L1TLB(this) miss, send request to PTW(L2TLB), . * s_wait: wait for PTW to refill L1TLB. * s_wait_invalidate: L1TLB is waiting for respond from PTW, but L1TLB will invalidate respond from PTW.}}} * * ==PMP== * pmp check * - special_entry: always check * - other entry: check on refill * * ==Note== * PMA consume diplomacy parameter generate physical memory address checking logic * * Boom use Rocket ITLB, and its own DTLB. * * Accelerators:{{{ * sha3: DTLB * gemmini: DTLB * hwacha: DTLB*2+ITLB}}} * @param instruction true for ITLB, false for DTLB * @param lgMaxSize @todo seems granularity * @param cfg [[TLBConfig]] * @param edge collect SoC metadata. */ class TLB(instruction: Boolean, lgMaxSize: Int, cfg: TLBConfig)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(p) { override def desiredName = if (instruction) "ITLB" else "DTLB" val io = IO(new Bundle { /** request from Core */ val req = Flipped(Decoupled(new TLBReq(lgMaxSize))) /** response to Core */ val resp = Output(new TLBResp(lgMaxSize)) /** SFence Input */ val sfence = Flipped(Valid(new SFenceReq)) /** IO to PTW */ val ptw = new TLBPTWIO /** suppress a TLB refill, one cycle after a miss */ val kill = Input(Bool()) }) io.ptw.customCSRs := DontCare val pageGranularityPMPs = pmpGranularity >= (1 << pgIdxBits) val vpn = io.req.bits.vaddr(vaddrBits-1, pgIdxBits) /** index for sectored_Entry */ val memIdx = vpn.extract(cfg.nSectors.log2 + cfg.nSets.log2 - 1, cfg.nSectors.log2) /** TLB Entry */ val sectored_entries = Reg(Vec(cfg.nSets, Vec(cfg.nWays / cfg.nSectors, new TLBEntry(cfg.nSectors, false, false)))) /** Superpage Entry */ val superpage_entries = Reg(Vec(cfg.nSuperpageEntries, new TLBEntry(1, true, true))) /** Special Entry * * If PMP granularity is less than page size, thus need additional "special" entry manage PMP. */ val special_entry = (!pageGranularityPMPs).option(Reg(new TLBEntry(1, true, false))) def ordinary_entries = sectored_entries(memIdx) ++ superpage_entries def all_entries = ordinary_entries ++ special_entry def all_real_entries = sectored_entries.flatten ++ superpage_entries ++ special_entry val s_ready :: s_request :: s_wait :: s_wait_invalidate :: Nil = Enum(4) val state = RegInit(s_ready) // use vpn as refill_tag val r_refill_tag = Reg(UInt(vpnBits.W)) val r_superpage_repl_addr = Reg(UInt(log2Ceil(superpage_entries.size).W)) val r_sectored_repl_addr = Reg(UInt(log2Ceil(sectored_entries.head.size).W)) val r_sectored_hit = Reg(Valid(UInt(log2Ceil(sectored_entries.head.size).W))) val r_superpage_hit = Reg(Valid(UInt(log2Ceil(superpage_entries.size).W))) val r_vstage1_en = Reg(Bool()) val r_stage2_en = Reg(Bool()) val r_need_gpa = Reg(Bool()) val r_gpa_valid = Reg(Bool()) val r_gpa = Reg(UInt(vaddrBits.W)) val r_gpa_vpn = Reg(UInt(vpnBits.W)) val r_gpa_is_pte = Reg(Bool()) /** privilege mode */ val priv = io.req.bits.prv val priv_v = usingHypervisor.B && io.req.bits.v val priv_s = priv(0) // user mode and supervisor mode val priv_uses_vm = priv <= PRV.S.U val satp = Mux(priv_v, io.ptw.vsatp, io.ptw.ptbr) val stage1_en = usingVM.B && satp.mode(satp.mode.getWidth-1) /** VS-stage translation enable */ val vstage1_en = usingHypervisor.B && priv_v && io.ptw.vsatp.mode(io.ptw.vsatp.mode.getWidth-1) /** G-stage translation enable */ val stage2_en = usingHypervisor.B && priv_v && io.ptw.hgatp.mode(io.ptw.hgatp.mode.getWidth-1) /** Enable Virtual Memory when: * 1. statically configured * 1. satp highest bits enabled * i. RV32: * - 0 -> Bare * - 1 -> SV32 * i. RV64: * - 0000 -> Bare * - 1000 -> SV39 * - 1001 -> SV48 * - 1010 -> SV57 * - 1011 -> SV64 * 1. In virtualization mode, vsatp highest bits enabled * 1. priv mode in U and S. * 1. in H & M mode, disable VM. * 1. no passthrough(micro-arch defined.) * * @see RV-priv spec 4.1.11 Supervisor Address Translation and Protection (satp) Register * @see RV-priv spec 8.2.18 Virtual Supervisor Address Translation and Protection Register (vsatp) */ val vm_enabled = (stage1_en || stage2_en) && priv_uses_vm && !io.req.bits.passthrough // flush guest entries on vsatp.MODE Bare <-> SvXX transitions val v_entries_use_stage1 = RegInit(false.B) val vsatp_mode_mismatch = priv_v && (vstage1_en =/= v_entries_use_stage1) && !io.req.bits.passthrough // share a single physical memory attribute checker (unshare if critical path) val refill_ppn = io.ptw.resp.bits.pte.ppn(ppnBits-1, 0) /** refill signal */ val do_refill = usingVM.B && io.ptw.resp.valid /** sfence invalidate refill */ val invalidate_refill = state.isOneOf(s_request /* don't care */, s_wait_invalidate) || io.sfence.valid // PMP val mpu_ppn = Mux(do_refill, refill_ppn, Mux(vm_enabled && special_entry.nonEmpty.B, special_entry.map(e => e.ppn(vpn, e.getData(vpn))).getOrElse(0.U), io.req.bits.vaddr >> pgIdxBits)) val mpu_physaddr = Cat(mpu_ppn, io.req.bits.vaddr(pgIdxBits-1, 0)) val mpu_priv = Mux[UInt](usingVM.B && (do_refill || io.req.bits.passthrough /* PTW */), PRV.S.U, Cat(io.ptw.status.debug, priv)) val pmp = Module(new PMPChecker(lgMaxSize)) pmp.io.addr := mpu_physaddr pmp.io.size := io.req.bits.size pmp.io.pmp := (io.ptw.pmp: Seq[PMP]) pmp.io.prv := mpu_priv val pma = Module(new PMAChecker(edge.manager)(p)) pma.io.paddr := mpu_physaddr // todo: using DataScratchpad doesn't support cacheable. val cacheable = pma.io.resp.cacheable && (instruction || !usingDataScratchpad).B val homogeneous = TLBPageLookup(edge.manager.managers, xLen, p(CacheBlockBytes), BigInt(1) << pgIdxBits, 1 << lgMaxSize)(mpu_physaddr).homogeneous // In M mode, if access DM address(debug module program buffer) val deny_access_to_debug = mpu_priv <= PRV.M.U && p(DebugModuleKey).map(dmp => dmp.address.contains(mpu_physaddr)).getOrElse(false.B) val prot_r = pma.io.resp.r && !deny_access_to_debug && pmp.io.r val prot_w = pma.io.resp.w && !deny_access_to_debug && pmp.io.w val prot_pp = pma.io.resp.pp val prot_al = pma.io.resp.al val prot_aa = pma.io.resp.aa val prot_x = pma.io.resp.x && !deny_access_to_debug && pmp.io.x val prot_eff = pma.io.resp.eff // hit check val sector_hits = sectored_entries(memIdx).map(_.sectorHit(vpn, priv_v)) val superpage_hits = superpage_entries.map(_.hit(vpn, priv_v)) val hitsVec = all_entries.map(vm_enabled && _.hit(vpn, priv_v)) val real_hits = hitsVec.asUInt val hits = Cat(!vm_enabled, real_hits) // use ptw response to refill // permission bit arrays when (do_refill) { val pte = io.ptw.resp.bits.pte val refill_v = r_vstage1_en || r_stage2_en val newEntry = Wire(new TLBEntryData) newEntry.ppn := pte.ppn newEntry.c := cacheable newEntry.u := pte.u newEntry.g := pte.g && pte.v newEntry.ae_ptw := io.ptw.resp.bits.ae_ptw newEntry.ae_final := io.ptw.resp.bits.ae_final newEntry.ae_stage2 := io.ptw.resp.bits.ae_final && io.ptw.resp.bits.gpa_is_pte && r_stage2_en newEntry.pf := io.ptw.resp.bits.pf newEntry.gf := io.ptw.resp.bits.gf newEntry.hr := io.ptw.resp.bits.hr newEntry.hw := io.ptw.resp.bits.hw newEntry.hx := io.ptw.resp.bits.hx newEntry.sr := pte.sr() newEntry.sw := pte.sw() newEntry.sx := pte.sx() newEntry.pr := prot_r newEntry.pw := prot_w newEntry.px := prot_x newEntry.ppp := prot_pp newEntry.pal := prot_al newEntry.paa := prot_aa newEntry.eff := prot_eff newEntry.fragmented_superpage := io.ptw.resp.bits.fragmented_superpage // refill special_entry when (special_entry.nonEmpty.B && !io.ptw.resp.bits.homogeneous) { special_entry.foreach(_.insert(r_refill_tag, refill_v, io.ptw.resp.bits.level, newEntry)) }.elsewhen (io.ptw.resp.bits.level < (pgLevels-1).U) { val waddr = Mux(r_superpage_hit.valid && usingHypervisor.B, r_superpage_hit.bits, r_superpage_repl_addr) for ((e, i) <- superpage_entries.zipWithIndex) when (r_superpage_repl_addr === i.U) { e.insert(r_refill_tag, refill_v, io.ptw.resp.bits.level, newEntry) when (invalidate_refill) { e.invalidate() } } // refill sectored_hit }.otherwise { val r_memIdx = r_refill_tag.extract(cfg.nSectors.log2 + cfg.nSets.log2 - 1, cfg.nSectors.log2) val waddr = Mux(r_sectored_hit.valid, r_sectored_hit.bits, r_sectored_repl_addr) for ((e, i) <- sectored_entries(r_memIdx).zipWithIndex) when (waddr === i.U) { when (!r_sectored_hit.valid) { e.invalidate() } e.insert(r_refill_tag, refill_v, 0.U, newEntry) when (invalidate_refill) { e.invalidate() } } } r_gpa_valid := io.ptw.resp.bits.gpa.valid r_gpa := io.ptw.resp.bits.gpa.bits r_gpa_is_pte := io.ptw.resp.bits.gpa_is_pte } // get all entries data. val entries = all_entries.map(_.getData(vpn)) val normal_entries = entries.take(ordinary_entries.size) // parallel query PPN from [[all_entries]], if VM not enabled return VPN instead val ppn = Mux1H(hitsVec :+ !vm_enabled, (all_entries zip entries).map{ case (entry, data) => entry.ppn(vpn, data) } :+ vpn(ppnBits-1, 0)) val nPhysicalEntries = 1 + special_entry.size // generally PTW misaligned load exception. val ptw_ae_array = Cat(false.B, entries.map(_.ae_ptw).asUInt) val final_ae_array = Cat(false.B, entries.map(_.ae_final).asUInt) val ptw_pf_array = Cat(false.B, entries.map(_.pf).asUInt) val ptw_gf_array = Cat(false.B, entries.map(_.gf).asUInt) val sum = Mux(priv_v, io.ptw.gstatus.sum, io.ptw.status.sum) // if in hypervisor/machine mode, cannot read/write user entries. // if in superviosr/user mode, "If the SUM bit in the sstatus register is set, supervisor mode software may also access pages with U=1.(from spec)" val priv_rw_ok = Mux(!priv_s || sum, entries.map(_.u).asUInt, 0.U) | Mux(priv_s, ~entries.map(_.u).asUInt, 0.U) // if in hypervisor/machine mode, other than user pages, all pages are executable. // if in superviosr/user mode, only user page can execute. val priv_x_ok = Mux(priv_s, ~entries.map(_.u).asUInt, entries.map(_.u).asUInt) val stage1_bypass = Fill(entries.size, usingHypervisor.B) & (Fill(entries.size, !stage1_en) | entries.map(_.ae_stage2).asUInt) val mxr = io.ptw.status.mxr | Mux(priv_v, io.ptw.gstatus.mxr, false.B) // "The vsstatus field MXR, which makes execute-only pages readable, only overrides VS-stage page protection.(from spec)" val r_array = Cat(true.B, (priv_rw_ok & (entries.map(_.sr).asUInt | Mux(mxr, entries.map(_.sx).asUInt, 0.U))) | stage1_bypass) val w_array = Cat(true.B, (priv_rw_ok & entries.map(_.sw).asUInt) | stage1_bypass) val x_array = Cat(true.B, (priv_x_ok & entries.map(_.sx).asUInt) | stage1_bypass) val stage2_bypass = Fill(entries.size, !stage2_en) val hr_array = Cat(true.B, entries.map(_.hr).asUInt | Mux(io.ptw.status.mxr, entries.map(_.hx).asUInt, 0.U) | stage2_bypass) val hw_array = Cat(true.B, entries.map(_.hw).asUInt | stage2_bypass) val hx_array = Cat(true.B, entries.map(_.hx).asUInt | stage2_bypass) // These array is for each TLB entries. // user mode can read: PMA OK, TLB OK, AE OK val pr_array = Cat(Fill(nPhysicalEntries, prot_r), normal_entries.map(_.pr).asUInt) & ~(ptw_ae_array | final_ae_array) // user mode can write: PMA OK, TLB OK, AE OK val pw_array = Cat(Fill(nPhysicalEntries, prot_w), normal_entries.map(_.pw).asUInt) & ~(ptw_ae_array | final_ae_array) // user mode can write: PMA OK, TLB OK, AE OK val px_array = Cat(Fill(nPhysicalEntries, prot_x), normal_entries.map(_.px).asUInt) & ~(ptw_ae_array | final_ae_array) // put effect val eff_array = Cat(Fill(nPhysicalEntries, prot_eff), normal_entries.map(_.eff).asUInt) // cacheable val c_array = Cat(Fill(nPhysicalEntries, cacheable), normal_entries.map(_.c).asUInt) // put partial val ppp_array = Cat(Fill(nPhysicalEntries, prot_pp), normal_entries.map(_.ppp).asUInt) // atomic arithmetic val paa_array = Cat(Fill(nPhysicalEntries, prot_aa), normal_entries.map(_.paa).asUInt) // atomic logic val pal_array = Cat(Fill(nPhysicalEntries, prot_al), normal_entries.map(_.pal).asUInt) val ppp_array_if_cached = ppp_array | c_array val paa_array_if_cached = paa_array | (if(usingAtomicsInCache) c_array else 0.U) val pal_array_if_cached = pal_array | (if(usingAtomicsInCache) c_array else 0.U) val prefetchable_array = Cat((cacheable && homogeneous) << (nPhysicalEntries-1), normal_entries.map(_.c).asUInt) // vaddr misaligned: vaddr[1:0]=b00 val misaligned = (io.req.bits.vaddr & (UIntToOH(io.req.bits.size) - 1.U)).orR def badVA(guestPA: Boolean): Bool = { val additionalPgLevels = (if (guestPA) io.ptw.hgatp else satp).additionalPgLevels val extraBits = if (guestPA) hypervisorExtraAddrBits else 0 val signed = !guestPA val nPgLevelChoices = pgLevels - minPgLevels + 1 val minVAddrBits = pgIdxBits + minPgLevels * pgLevelBits + extraBits (for (i <- 0 until nPgLevelChoices) yield { val mask = ((BigInt(1) << vaddrBitsExtended) - (BigInt(1) << (minVAddrBits + i * pgLevelBits - signed.toInt))).U val maskedVAddr = io.req.bits.vaddr & mask additionalPgLevels === i.U && !(maskedVAddr === 0.U || signed.B && maskedVAddr === mask) }).orR } val bad_gpa = if (!usingHypervisor) false.B else vm_enabled && !stage1_en && badVA(true) val bad_va = if (!usingVM || (minPgLevels == pgLevels && vaddrBits == vaddrBitsExtended)) false.B else vm_enabled && stage1_en && badVA(false) val cmd_lrsc = usingAtomics.B && io.req.bits.cmd.isOneOf(M_XLR, M_XSC) val cmd_amo_logical = usingAtomics.B && isAMOLogical(io.req.bits.cmd) val cmd_amo_arithmetic = usingAtomics.B && isAMOArithmetic(io.req.bits.cmd) val cmd_put_partial = io.req.bits.cmd === M_PWR val cmd_read = isRead(io.req.bits.cmd) val cmd_readx = usingHypervisor.B && io.req.bits.cmd === M_HLVX val cmd_write = isWrite(io.req.bits.cmd) val cmd_write_perms = cmd_write || io.req.bits.cmd.isOneOf(M_FLUSH_ALL, M_WOK) // not a write, but needs write permissions val lrscAllowed = Mux((usingDataScratchpad || usingAtomicsOnlyForIO).B, 0.U, c_array) val ae_array = Mux(misaligned, eff_array, 0.U) | Mux(cmd_lrsc, ~lrscAllowed, 0.U) // access exception needs SoC information from PMA val ae_ld_array = Mux(cmd_read, ae_array | ~pr_array, 0.U) val ae_st_array = Mux(cmd_write_perms, ae_array | ~pw_array, 0.U) | Mux(cmd_put_partial, ~ppp_array_if_cached, 0.U) | Mux(cmd_amo_logical, ~pal_array_if_cached, 0.U) | Mux(cmd_amo_arithmetic, ~paa_array_if_cached, 0.U) val must_alloc_array = Mux(cmd_put_partial, ~ppp_array, 0.U) | Mux(cmd_amo_logical, ~pal_array, 0.U) | Mux(cmd_amo_arithmetic, ~paa_array, 0.U) | Mux(cmd_lrsc, ~0.U(pal_array.getWidth.W), 0.U) val pf_ld_array = Mux(cmd_read, ((~Mux(cmd_readx, x_array, r_array) & ~ptw_ae_array) | ptw_pf_array) & ~ptw_gf_array, 0.U) val pf_st_array = Mux(cmd_write_perms, ((~w_array & ~ptw_ae_array) | ptw_pf_array) & ~ptw_gf_array, 0.U) val pf_inst_array = ((~x_array & ~ptw_ae_array) | ptw_pf_array) & ~ptw_gf_array val gf_ld_array = Mux(priv_v && cmd_read, (~Mux(cmd_readx, hx_array, hr_array) | ptw_gf_array) & ~ptw_ae_array, 0.U) val gf_st_array = Mux(priv_v && cmd_write_perms, (~hw_array | ptw_gf_array) & ~ptw_ae_array, 0.U) val gf_inst_array = Mux(priv_v, (~hx_array | ptw_gf_array) & ~ptw_ae_array, 0.U) val gpa_hits = { val need_gpa_mask = if (instruction) gf_inst_array else gf_ld_array | gf_st_array val hit_mask = Fill(ordinary_entries.size, r_gpa_valid && r_gpa_vpn === vpn) | Fill(all_entries.size, !vstage1_en) hit_mask | ~need_gpa_mask(all_entries.size-1, 0) } val tlb_hit_if_not_gpa_miss = real_hits.orR val tlb_hit = (real_hits & gpa_hits).orR // leads to s_request val tlb_miss = vm_enabled && !vsatp_mode_mismatch && !bad_va && !tlb_hit val sectored_plru = new SetAssocLRU(cfg.nSets, sectored_entries.head.size, "plru") val superpage_plru = new PseudoLRU(superpage_entries.size) when (io.req.valid && vm_enabled) { // replace when (sector_hits.orR) { sectored_plru.access(memIdx, OHToUInt(sector_hits)) } when (superpage_hits.orR) { superpage_plru.access(OHToUInt(superpage_hits)) } } // Superpages create the possibility that two entries in the TLB may match. // This corresponds to a software bug, but we can't return complete garbage; // we must return either the old translation or the new translation. This // isn't compatible with the Mux1H approach. So, flush the TLB and report // a miss on duplicate entries. val multipleHits = PopCountAtLeast(real_hits, 2) // only pull up req.ready when this is s_ready state. io.req.ready := state === s_ready // page fault io.resp.pf.ld := (bad_va && cmd_read) || (pf_ld_array & hits).orR io.resp.pf.st := (bad_va && cmd_write_perms) || (pf_st_array & hits).orR io.resp.pf.inst := bad_va || (pf_inst_array & hits).orR // guest page fault io.resp.gf.ld := (bad_gpa && cmd_read) || (gf_ld_array & hits).orR io.resp.gf.st := (bad_gpa && cmd_write_perms) || (gf_st_array & hits).orR io.resp.gf.inst := bad_gpa || (gf_inst_array & hits).orR // access exception io.resp.ae.ld := (ae_ld_array & hits).orR io.resp.ae.st := (ae_st_array & hits).orR io.resp.ae.inst := (~px_array & hits).orR // misaligned io.resp.ma.ld := misaligned && cmd_read io.resp.ma.st := misaligned && cmd_write io.resp.ma.inst := false.B // this is up to the pipeline to figure out io.resp.cacheable := (c_array & hits).orR io.resp.must_alloc := (must_alloc_array & hits).orR io.resp.prefetchable := (prefetchable_array & hits).orR && edge.manager.managers.forall(m => !m.supportsAcquireB || m.supportsHint).B io.resp.miss := do_refill || vsatp_mode_mismatch || tlb_miss || multipleHits io.resp.paddr := Cat(ppn, io.req.bits.vaddr(pgIdxBits-1, 0)) io.resp.size := io.req.bits.size io.resp.cmd := io.req.bits.cmd io.resp.gpa_is_pte := vstage1_en && r_gpa_is_pte io.resp.gpa := { val page = Mux(!vstage1_en, Cat(bad_gpa, vpn), r_gpa >> pgIdxBits) val offset = Mux(io.resp.gpa_is_pte, r_gpa(pgIdxBits-1, 0), io.req.bits.vaddr(pgIdxBits-1, 0)) Cat(page, offset) } io.ptw.req.valid := state === s_request io.ptw.req.bits.valid := !io.kill io.ptw.req.bits.bits.addr := r_refill_tag io.ptw.req.bits.bits.vstage1 := r_vstage1_en io.ptw.req.bits.bits.stage2 := r_stage2_en io.ptw.req.bits.bits.need_gpa := r_need_gpa if (usingVM) { when(io.ptw.req.fire && io.ptw.req.bits.valid) { r_gpa_valid := false.B r_gpa_vpn := r_refill_tag } val sfence = io.sfence.valid // this is [[s_ready]] // handle miss/hit at the first cycle. // if miss, request PTW(L2TLB). when (io.req.fire && tlb_miss) { state := s_request r_refill_tag := vpn r_need_gpa := tlb_hit_if_not_gpa_miss r_vstage1_en := vstage1_en r_stage2_en := stage2_en r_superpage_repl_addr := replacementEntry(superpage_entries, superpage_plru.way) r_sectored_repl_addr := replacementEntry(sectored_entries(memIdx), sectored_plru.way(memIdx)) r_sectored_hit.valid := sector_hits.orR r_sectored_hit.bits := OHToUInt(sector_hits) r_superpage_hit.valid := superpage_hits.orR r_superpage_hit.bits := OHToUInt(superpage_hits) } // Handle SFENCE.VMA when send request to PTW. // SFENCE.VMA io.ptw.req.ready kill // ? ? 1 // 0 0 0 // 0 1 0 -> s_wait // 1 0 0 -> s_wait_invalidate // 1 0 0 -> s_ready when (state === s_request) { // SFENCE.VMA will kill TLB entries based on rs1 and rs2. It will take 1 cycle. when (sfence) { state := s_ready } // here should be io.ptw.req.fire, but assert(io.ptw.req.ready === true.B) // fire -> s_wait when (io.ptw.req.ready) { state := Mux(sfence, s_wait_invalidate, s_wait) } // If CPU kills request(frontend.s2_redirect) when (io.kill) { state := s_ready } } // sfence in refill will results in invalidate when (state === s_wait && sfence) { state := s_wait_invalidate } // after CPU acquire response, go back to s_ready. when (io.ptw.resp.valid) { state := s_ready } // SFENCE processing logic. when (sfence) { assert(!io.sfence.bits.rs1 || (io.sfence.bits.addr >> pgIdxBits) === vpn) for (e <- all_real_entries) { val hv = usingHypervisor.B && io.sfence.bits.hv val hg = usingHypervisor.B && io.sfence.bits.hg when (!hg && io.sfence.bits.rs1) { e.invalidateVPN(vpn, hv) } .elsewhen (!hg && io.sfence.bits.rs2) { e.invalidateNonGlobal(hv) } .otherwise { e.invalidate(hv || hg) } } } when(io.req.fire && vsatp_mode_mismatch) { all_real_entries.foreach(_.invalidate(true.B)) v_entries_use_stage1 := vstage1_en } when (multipleHits || reset.asBool) { all_real_entries.foreach(_.invalidate()) } ccover(io.ptw.req.fire, "MISS", "TLB miss") ccover(io.ptw.req.valid && !io.ptw.req.ready, "PTW_STALL", "TLB miss, but PTW busy") ccover(state === s_wait_invalidate, "SFENCE_DURING_REFILL", "flush TLB during TLB refill") ccover(sfence && !io.sfence.bits.rs1 && !io.sfence.bits.rs2, "SFENCE_ALL", "flush TLB") ccover(sfence && !io.sfence.bits.rs1 && io.sfence.bits.rs2, "SFENCE_ASID", "flush TLB ASID") ccover(sfence && io.sfence.bits.rs1 && !io.sfence.bits.rs2, "SFENCE_LINE", "flush TLB line") ccover(sfence && io.sfence.bits.rs1 && io.sfence.bits.rs2, "SFENCE_LINE_ASID", "flush TLB line/ASID") ccover(multipleHits, "MULTIPLE_HITS", "Two matching translations in TLB") } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = property.cover(cond, s"${if (instruction) "I" else "D"}TLB_$label", "MemorySystem;;" + desc) /** Decides which entry to be replaced * * If there is a invalid entry, replace it with priorityencoder; * if not, replace the alt entry * * @return mask for TLBEntry replacement */ def replacementEntry(set: Seq[TLBEntry], alt: UInt) = { val valids = set.map(_.valid.orR).asUInt Mux(valids.andR, alt, PriorityEncoder(~valids)) } } File TLBPermissions.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes, RegionType, AddressDecoder} import freechips.rocketchip.tilelink.TLManagerParameters case class TLBPermissions( homogeneous: Bool, // if false, the below are undefined r: Bool, // readable w: Bool, // writeable x: Bool, // executable c: Bool, // cacheable a: Bool, // arithmetic ops l: Bool) // logical ops object TLBPageLookup { private case class TLBFixedPermissions( e: Boolean, // get-/put-effects r: Boolean, // readable w: Boolean, // writeable x: Boolean, // executable c: Boolean, // cacheable a: Boolean, // arithmetic ops l: Boolean) { // logical ops val useful = r || w || x || c || a || l } private def groupRegions(managers: Seq[TLManagerParameters]): Map[TLBFixedPermissions, Seq[AddressSet]] = { val permissions = managers.map { m => (m.address, TLBFixedPermissions( e = Seq(RegionType.PUT_EFFECTS, RegionType.GET_EFFECTS) contains m.regionType, r = m.supportsGet || m.supportsAcquireB, // if cached, never uses Get w = m.supportsPutFull || m.supportsAcquireT, // if cached, never uses Put x = m.executable, c = m.supportsAcquireB, a = m.supportsArithmetic, l = m.supportsLogical)) } permissions .filter(_._2.useful) // get rid of no-permission devices .groupBy(_._2) // group by permission type .mapValues(seq => AddressSet.unify(seq.flatMap(_._1))) // coalesce same-permission regions .toMap } // Unmapped memory is considered to be inhomogeneous def apply(managers: Seq[TLManagerParameters], xLen: Int, cacheBlockBytes: Int, pageSize: BigInt, maxRequestBytes: Int): UInt => TLBPermissions = { require (isPow2(xLen) && xLen >= 8) require (isPow2(cacheBlockBytes) && cacheBlockBytes >= xLen/8) require (isPow2(pageSize) && pageSize >= cacheBlockBytes) val xferSizes = TransferSizes(cacheBlockBytes, cacheBlockBytes) val allSizes = TransferSizes(1, maxRequestBytes) val amoSizes = TransferSizes(4, xLen/8) val permissions = managers.foreach { m => require (!m.supportsGet || m.supportsGet .contains(allSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsGet} Get, but must support ${allSizes}") require (!m.supportsPutFull || m.supportsPutFull .contains(allSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsPutFull} PutFull, but must support ${allSizes}") require (!m.supportsPutPartial || m.supportsPutPartial.contains(allSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsPutPartial} PutPartial, but must support ${allSizes}") require (!m.supportsAcquireB || m.supportsAcquireB .contains(xferSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsAcquireB} AcquireB, but must support ${xferSizes}") require (!m.supportsAcquireT || m.supportsAcquireT .contains(xferSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsAcquireT} AcquireT, but must support ${xferSizes}") require (!m.supportsLogical || m.supportsLogical .contains(amoSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsLogical} Logical, but must support ${amoSizes}") require (!m.supportsArithmetic || m.supportsArithmetic.contains(amoSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsArithmetic} Arithmetic, but must support ${amoSizes}") require (!(m.supportsAcquireB && m.supportsPutFull && !m.supportsAcquireT), s"Memory region '${m.name}' supports AcquireB (cached read) and PutFull (un-cached write) but not AcquireT (cached write)") } val grouped = groupRegions(managers) .mapValues(_.filter(_.alignment >= pageSize)) // discard any region that's not big enough def lowCostProperty(prop: TLBFixedPermissions => Boolean): UInt => Bool = { val (yesm, nom) = grouped.partition { case (k, eq) => prop(k) } val (yes, no) = (yesm.values.flatten.toList, nom.values.flatten.toList) // Find the minimal bits needed to distinguish between yes and no val decisionMask = AddressDecoder(Seq(yes, no)) def simplify(x: Seq[AddressSet]) = AddressSet.unify(x.map(_.widen(~decisionMask)).distinct) val (yesf, nof) = (simplify(yes), simplify(no)) if (yesf.size < no.size) { (x: UInt) => yesf.map(_.contains(x)).foldLeft(false.B)(_ || _) } else { (x: UInt) => !nof.map(_.contains(x)).foldLeft(false.B)(_ || _) } } // Derive simplified property circuits (don't care when !homo) val rfn = lowCostProperty(_.r) val wfn = lowCostProperty(_.w) val xfn = lowCostProperty(_.x) val cfn = lowCostProperty(_.c) val afn = lowCostProperty(_.a) val lfn = lowCostProperty(_.l) val homo = AddressSet.unify(grouped.values.flatten.toList) (x: UInt) => TLBPermissions( homogeneous = homo.map(_.contains(x)).foldLeft(false.B)(_ || _), r = rfn(x), w = wfn(x), x = xfn(x), c = cfn(x), a = afn(x), l = lfn(x)) } // Are all pageSize intervals of mapped regions homogeneous? def homogeneous(managers: Seq[TLManagerParameters], pageSize: BigInt): Boolean = { groupRegions(managers).values.forall(_.forall(_.alignment >= pageSize)) } } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File PTW.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.{Arbiter, Cat, Decoupled, Enum, Mux1H, OHToUInt, PopCount, PriorityEncoder, PriorityEncoderOH, RegEnable, UIntToOH, Valid, is, isPow2, log2Ceil, switch} import chisel3.withClock import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.subsystem.CacheBlockBytes import freechips.rocketchip.tile._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property import scala.collection.mutable.ListBuffer /** PTE request from TLB to PTW * * TLB send a PTE request to PTW when L1TLB miss */ class PTWReq(implicit p: Parameters) extends CoreBundle()(p) { val addr = UInt(vpnBits.W) val need_gpa = Bool() val vstage1 = Bool() val stage2 = Bool() } /** PTE info from L2TLB to TLB * * containing: target PTE, exceptions, two-satge tanslation info */ class PTWResp(implicit p: Parameters) extends CoreBundle()(p) { /** ptw access exception */ val ae_ptw = Bool() /** final access exception */ val ae_final = Bool() /** page fault */ val pf = Bool() /** guest page fault */ val gf = Bool() /** hypervisor read */ val hr = Bool() /** hypervisor write */ val hw = Bool() /** hypervisor execute */ val hx = Bool() /** PTE to refill L1TLB * * source: L2TLB */ val pte = new PTE /** pte pglevel */ val level = UInt(log2Ceil(pgLevels).W) /** fragmented_superpage support */ val fragmented_superpage = Bool() /** homogeneous for both pma and pmp */ val homogeneous = Bool() val gpa = Valid(UInt(vaddrBits.W)) val gpa_is_pte = Bool() } /** IO between TLB and PTW * * PTW receives : * - PTE request * - CSRs info * - pmp results from PMP(in TLB) */ class TLBPTWIO(implicit p: Parameters) extends CoreBundle()(p) with HasCoreParameters { val req = Decoupled(Valid(new PTWReq)) val resp = Flipped(Valid(new PTWResp)) val ptbr = Input(new PTBR()) val hgatp = Input(new PTBR()) val vsatp = Input(new PTBR()) val status = Input(new MStatus()) val hstatus = Input(new HStatus()) val gstatus = Input(new MStatus()) val pmp = Input(Vec(nPMPs, new PMP)) val customCSRs = Flipped(coreParams.customCSRs) } /** PTW performance statistics */ class PTWPerfEvents extends Bundle { val l2miss = Bool() val l2hit = Bool() val pte_miss = Bool() val pte_hit = Bool() } /** Datapath IO between PTW and Core * * PTW receives CSRs info, pmp checks, sfence instruction info * * PTW sends its performance statistics to core */ class DatapathPTWIO(implicit p: Parameters) extends CoreBundle()(p) with HasCoreParameters { val ptbr = Input(new PTBR()) val hgatp = Input(new PTBR()) val vsatp = Input(new PTBR()) val sfence = Flipped(Valid(new SFenceReq)) val status = Input(new MStatus()) val hstatus = Input(new HStatus()) val gstatus = Input(new MStatus()) val pmp = Input(Vec(nPMPs, new PMP)) val perf = Output(new PTWPerfEvents()) val customCSRs = Flipped(coreParams.customCSRs) /** enable clock generated by ptw */ val clock_enabled = Output(Bool()) } /** PTE template for transmission * * contains useful methods to check PTE attributes * @see RV-priv spec 4.3.1 for pgae table entry format */ class PTE(implicit p: Parameters) extends CoreBundle()(p) { val reserved_for_future = UInt(10.W) val ppn = UInt(44.W) val reserved_for_software = Bits(2.W) /** dirty bit */ val d = Bool() /** access bit */ val a = Bool() /** global mapping */ val g = Bool() /** user mode accessible */ val u = Bool() /** whether the page is executable */ val x = Bool() /** whether the page is writable */ val w = Bool() /** whether the page is readable */ val r = Bool() /** valid bit */ val v = Bool() /** return true if find a pointer to next level page table */ def table(dummy: Int = 0) = v && !r && !w && !x && !d && !a && !u && reserved_for_future === 0.U /** return true if find a leaf PTE */ def leaf(dummy: Int = 0) = v && (r || (x && !w)) && a /** user read */ def ur(dummy: Int = 0) = sr() && u /** user write*/ def uw(dummy: Int = 0) = sw() && u /** user execute */ def ux(dummy: Int = 0) = sx() && u /** supervisor read */ def sr(dummy: Int = 0) = leaf() && r /** supervisor write */ def sw(dummy: Int = 0) = leaf() && w && d /** supervisor execute */ def sx(dummy: Int = 0) = leaf() && x /** full permission: writable and executable in user mode */ def isFullPerm(dummy: Int = 0) = uw() && ux() } /** L2TLB PTE template * * contains tag bits * @param nSets number of sets in L2TLB * @see RV-priv spec 4.3.1 for page table entry format */ class L2TLBEntry(nSets: Int)(implicit p: Parameters) extends CoreBundle()(p) with HasCoreParameters { val idxBits = log2Ceil(nSets) val tagBits = maxSVAddrBits - pgIdxBits - idxBits + (if (usingHypervisor) 1 else 0) val tag = UInt(tagBits.W) val ppn = UInt(ppnBits.W) /** dirty bit */ val d = Bool() /** access bit */ val a = Bool() /** user mode accessible */ val u = Bool() /** whether the page is executable */ val x = Bool() /** whether the page is writable */ val w = Bool() /** whether the page is readable */ val r = Bool() } /** PTW contains L2TLB, and performs page table walk for high level TLB, and cache queries from L1 TLBs(I$, D$, RoCC) * * It performs hierarchy page table query to mem for the desired leaf PTE and cache them in l2tlb. * Besides leaf PTEs, it also caches non-leaf PTEs in pte_cache to accerlerate the process. * * ==Structure== * - l2tlb : for leaf PTEs * - set-associative (configurable with [[CoreParams.nL2TLBEntries]]and [[CoreParams.nL2TLBWays]])) * - PLRU * - pte_cache: for non-leaf PTEs * - set-associative * - LRU * - s2_pte_cache: for non-leaf PTEs in 2-stage translation * - set-associative * - PLRU * * l2tlb Pipeline: 3 stage * {{{ * stage 0 : read * stage 1 : decode * stage 2 : hit check * }}} * ==State Machine== * s_ready: ready to reveive request from TLB * s_req: request mem; pte_cache hit judge * s_wait1: deal with l2tlb error * s_wait2: final hit judge * s_wait3: receive mem response * s_fragment_superpage: for superpage PTE * * @note l2tlb hit happens in s_req or s_wait1 * @see RV-priv spec 4.3-4.6 for Virtual-Memory System * @see RV-priv spec 8.5 for Two-Stage Address Translation * @todo details in two-stage translation */ class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(p) { val io = IO(new Bundle { /** to n TLB */ val requestor = Flipped(Vec(n, new TLBPTWIO)) /** to HellaCache */ val mem = new HellaCacheIO /** to Core * * contains CSRs info and performance statistics */ val dpath = new DatapathPTWIO }) val s_ready :: s_req :: s_wait1 :: s_dummy1 :: s_wait2 :: s_wait3 :: s_dummy2 :: s_fragment_superpage :: Nil = Enum(8) val state = RegInit(s_ready) val l2_refill_wire = Wire(Bool()) /** Arbiter to arbite request from n TLB */ val arb = Module(new Arbiter(Valid(new PTWReq), n)) // use TLB req as arbitor's input arb.io.in <> io.requestor.map(_.req) // receive req only when s_ready and not in refill arb.io.out.ready := (state === s_ready) && !l2_refill_wire val resp_valid = RegNext(VecInit(Seq.fill(io.requestor.size)(false.B))) val clock_en = state =/= s_ready || l2_refill_wire || arb.io.out.valid || io.dpath.sfence.valid || io.dpath.customCSRs.disableDCacheClockGate io.dpath.clock_enabled := usingVM.B && clock_en val gated_clock = if (!usingVM || !tileParams.dcache.get.clockGate) clock else ClockGate(clock, clock_en, "ptw_clock_gate") withClock (gated_clock) { // entering gated-clock domain val invalidated = Reg(Bool()) /** current PTE level * {{{ * 0 <= count <= pgLevel-1 * count = pgLevel - 1 : leaf PTE * count < pgLevel - 1 : non-leaf PTE * }}} */ val count = Reg(UInt(log2Ceil(pgLevels).W)) val resp_ae_ptw = Reg(Bool()) val resp_ae_final = Reg(Bool()) val resp_pf = Reg(Bool()) val resp_gf = Reg(Bool()) val resp_hr = Reg(Bool()) val resp_hw = Reg(Bool()) val resp_hx = Reg(Bool()) val resp_fragmented_superpage = Reg(Bool()) /** tlb request */ val r_req = Reg(new PTWReq) /** current selected way in arbitor */ val r_req_dest = Reg(Bits()) // to respond to L1TLB : l2_hit // to construct mem.req.addr val r_pte = Reg(new PTE) val r_hgatp = Reg(new PTBR) // 2-stage pageLevel val aux_count = Reg(UInt(log2Ceil(pgLevels).W)) /** pte for 2-stage translation */ val aux_pte = Reg(new PTE) val gpa_pgoff = Reg(UInt(pgIdxBits.W)) // only valid in resp_gf case val stage2 = Reg(Bool()) val stage2_final = Reg(Bool()) val satp = Mux(arb.io.out.bits.bits.vstage1, io.dpath.vsatp, io.dpath.ptbr) val r_hgatp_initial_count = pgLevels.U - minPgLevels.U - r_hgatp.additionalPgLevels /** 2-stage translation both enable */ val do_both_stages = r_req.vstage1 && r_req.stage2 val max_count = count max aux_count val vpn = Mux(r_req.vstage1 && stage2, aux_pte.ppn, r_req.addr) val mem_resp_valid = RegNext(io.mem.resp.valid) val mem_resp_data = RegNext(io.mem.resp.bits.data) io.mem.uncached_resp.map { resp => assert(!(resp.valid && io.mem.resp.valid)) resp.ready := true.B when (resp.valid) { mem_resp_valid := true.B mem_resp_data := resp.bits.data } } // construct pte from mem.resp val (pte, invalid_paddr, invalid_gpa) = { val tmp = mem_resp_data.asTypeOf(new PTE()) val res = WireDefault(tmp) res.ppn := Mux(do_both_stages && !stage2, tmp.ppn(vpnBits.min(tmp.ppn.getWidth)-1, 0), tmp.ppn(ppnBits-1, 0)) when (tmp.r || tmp.w || tmp.x) { // for superpage mappings, make sure PPN LSBs are zero for (i <- 0 until pgLevels-1) when (count <= i.U && tmp.ppn((pgLevels-1-i)*pgLevelBits-1, (pgLevels-2-i)*pgLevelBits) =/= 0.U) { res.v := false.B } } (res, Mux(do_both_stages && !stage2, (tmp.ppn >> vpnBits) =/= 0.U, (tmp.ppn >> ppnBits) =/= 0.U), do_both_stages && !stage2 && checkInvalidHypervisorGPA(r_hgatp, tmp.ppn)) } // find non-leaf PTE, need traverse val traverse = pte.table() && !invalid_paddr && !invalid_gpa && count < (pgLevels-1).U /** address send to mem for enquerry */ val pte_addr = if (!usingVM) 0.U else { val vpn_idxs = (0 until pgLevels).map { i => val width = pgLevelBits + (if (i <= pgLevels - minPgLevels) hypervisorExtraAddrBits else 0) (vpn >> (pgLevels - i - 1) * pgLevelBits)(width - 1, 0) } val mask = Mux(stage2 && count === r_hgatp_initial_count, ((1 << (hypervisorExtraAddrBits + pgLevelBits)) - 1).U, ((1 << pgLevelBits) - 1).U) val vpn_idx = vpn_idxs(count) & mask val raw_pte_addr = ((r_pte.ppn << pgLevelBits) | vpn_idx) << log2Ceil(xLen / 8) val size = if (usingHypervisor) vaddrBits else paddrBits //use r_pte.ppn as page table base address //use vpn slice as offset raw_pte_addr.apply(size.min(raw_pte_addr.getWidth) - 1, 0) } /** stage2_pte_cache input addr */ val stage2_pte_cache_addr = if (!usingHypervisor) 0.U else { val vpn_idxs = (0 until pgLevels - 1).map { i => (r_req.addr >> (pgLevels - i - 1) * pgLevelBits)(pgLevelBits - 1, 0) } val vpn_idx = vpn_idxs(aux_count) val raw_s2_pte_cache_addr = Cat(aux_pte.ppn, vpn_idx) << log2Ceil(xLen / 8) raw_s2_pte_cache_addr(vaddrBits.min(raw_s2_pte_cache_addr.getWidth) - 1, 0) } def makeFragmentedSuperpagePPN(ppn: UInt): Seq[UInt] = { (pgLevels-1 until 0 by -1).map(i => Cat(ppn >> (pgLevelBits*i), r_req.addr(((pgLevelBits*i) min vpnBits)-1, 0).padTo(pgLevelBits*i))) } /** PTECache caches non-leaf PTE * @param s2 true: 2-stage address translation */ def makePTECache(s2: Boolean): (Bool, UInt) = if (coreParams.nPTECacheEntries == 0) { (false.B, 0.U) } else { val plru = new PseudoLRU(coreParams.nPTECacheEntries) val valid = RegInit(0.U(coreParams.nPTECacheEntries.W)) val tags = Reg(Vec(coreParams.nPTECacheEntries, UInt((if (usingHypervisor) 1 + vaddrBits else paddrBits).W))) // not include full pte, only ppn val data = Reg(Vec(coreParams.nPTECacheEntries, UInt((if (usingHypervisor && s2) vpnBits else ppnBits).W))) val can_hit = if (s2) count === r_hgatp_initial_count && aux_count < (pgLevels-1).U && r_req.vstage1 && stage2 && !stage2_final else count < (pgLevels-1).U && Mux(r_req.vstage1, stage2, !r_req.stage2) val can_refill = if (s2) do_both_stages && !stage2 && !stage2_final else can_hit val tag = if (s2) Cat(true.B, stage2_pte_cache_addr.padTo(vaddrBits)) else Cat(r_req.vstage1, pte_addr.padTo(if (usingHypervisor) vaddrBits else paddrBits)) val hits = tags.map(_ === tag).asUInt & valid val hit = hits.orR && can_hit // refill with mem response when (mem_resp_valid && traverse && can_refill && !hits.orR && !invalidated) { val r = Mux(valid.andR, plru.way, PriorityEncoder(~valid)) valid := valid | UIntToOH(r) tags(r) := tag data(r) := pte.ppn plru.access(r) } // replace when (hit && state === s_req) { plru.access(OHToUInt(hits)) } when (io.dpath.sfence.valid && (!io.dpath.sfence.bits.rs1 || usingHypervisor.B && io.dpath.sfence.bits.hg)) { valid := 0.U } val lcount = if (s2) aux_count else count for (i <- 0 until pgLevels-1) { ccover(hit && state === s_req && lcount === i.U, s"PTE_CACHE_HIT_L$i", s"PTE cache hit, level $i") } (hit, Mux1H(hits, data)) } // generate pte_cache val (pte_cache_hit, pte_cache_data) = makePTECache(false) // generate pte_cache with 2-stage translation val (stage2_pte_cache_hit, stage2_pte_cache_data) = makePTECache(true) // pte_cache hit or 2-stage pte_cache hit val pte_hit = RegNext(false.B) io.dpath.perf.pte_miss := false.B io.dpath.perf.pte_hit := pte_hit && (state === s_req) && !io.dpath.perf.l2hit assert(!(io.dpath.perf.l2hit && (io.dpath.perf.pte_miss || io.dpath.perf.pte_hit)), "PTE Cache Hit/Miss Performance Monitor Events are lower priority than L2TLB Hit event") // l2_refill happens when find the leaf pte val l2_refill = RegNext(false.B) l2_refill_wire := l2_refill io.dpath.perf.l2miss := false.B io.dpath.perf.l2hit := false.B // l2tlb val (l2_hit, l2_error, l2_pte, l2_tlb_ram) = if (coreParams.nL2TLBEntries == 0) (false.B, false.B, WireDefault(0.U.asTypeOf(new PTE)), None) else { val code = new ParityCode require(isPow2(coreParams.nL2TLBEntries)) require(isPow2(coreParams.nL2TLBWays)) require(coreParams.nL2TLBEntries >= coreParams.nL2TLBWays) val nL2TLBSets = coreParams.nL2TLBEntries / coreParams.nL2TLBWays require(isPow2(nL2TLBSets)) val idxBits = log2Ceil(nL2TLBSets) val l2_plru = new SetAssocLRU(nL2TLBSets, coreParams.nL2TLBWays, "plru") val ram = DescribedSRAM( name = "l2_tlb_ram", desc = "L2 TLB", size = nL2TLBSets, data = Vec(coreParams.nL2TLBWays, UInt(code.width(new L2TLBEntry(nL2TLBSets).getWidth).W)) ) val g = Reg(Vec(coreParams.nL2TLBWays, UInt(nL2TLBSets.W))) val valid = RegInit(VecInit(Seq.fill(coreParams.nL2TLBWays)(0.U(nL2TLBSets.W)))) // use r_req to construct tag val (r_tag, r_idx) = Split(Cat(r_req.vstage1, r_req.addr(maxSVAddrBits-pgIdxBits-1, 0)), idxBits) /** the valid vec for the selected set(including n ways) */ val r_valid_vec = valid.map(_(r_idx)).asUInt val r_valid_vec_q = Reg(UInt(coreParams.nL2TLBWays.W)) val r_l2_plru_way = Reg(UInt(log2Ceil(coreParams.nL2TLBWays max 1).W)) r_valid_vec_q := r_valid_vec // replacement way r_l2_plru_way := (if (coreParams.nL2TLBWays > 1) l2_plru.way(r_idx) else 0.U) // refill with r_pte(leaf pte) when (l2_refill && !invalidated) { val entry = Wire(new L2TLBEntry(nL2TLBSets)) entry.ppn := r_pte.ppn entry.d := r_pte.d entry.a := r_pte.a entry.u := r_pte.u entry.x := r_pte.x entry.w := r_pte.w entry.r := r_pte.r entry.tag := r_tag // if all the way are valid, use plru to select one way to be replaced, // otherwise use PriorityEncoderOH to select one val wmask = if (coreParams.nL2TLBWays > 1) Mux(r_valid_vec_q.andR, UIntToOH(r_l2_plru_way, coreParams.nL2TLBWays), PriorityEncoderOH(~r_valid_vec_q)) else 1.U(1.W) ram.write(r_idx, VecInit(Seq.fill(coreParams.nL2TLBWays)(code.encode(entry.asUInt))), wmask.asBools) val mask = UIntToOH(r_idx) for (way <- 0 until coreParams.nL2TLBWays) { when (wmask(way)) { valid(way) := valid(way) | mask g(way) := Mux(r_pte.g, g(way) | mask, g(way) & ~mask) } } } // sfence happens when (io.dpath.sfence.valid) { val hg = usingHypervisor.B && io.dpath.sfence.bits.hg for (way <- 0 until coreParams.nL2TLBWays) { valid(way) := Mux(!hg && io.dpath.sfence.bits.rs1, valid(way) & ~UIntToOH(io.dpath.sfence.bits.addr(idxBits+pgIdxBits-1, pgIdxBits)), Mux(!hg && io.dpath.sfence.bits.rs2, valid(way) & g(way), 0.U)) } } val s0_valid = !l2_refill && arb.io.out.fire val s0_suitable = arb.io.out.bits.bits.vstage1 === arb.io.out.bits.bits.stage2 && !arb.io.out.bits.bits.need_gpa val s1_valid = RegNext(s0_valid && s0_suitable && arb.io.out.bits.valid) val s2_valid = RegNext(s1_valid) // read from tlb idx val s1_rdata = ram.read(arb.io.out.bits.bits.addr(idxBits-1, 0), s0_valid) val s2_rdata = s1_rdata.map(s1_rdway => code.decode(RegEnable(s1_rdway, s1_valid))) val s2_valid_vec = RegEnable(r_valid_vec, s1_valid) val s2_g_vec = RegEnable(VecInit(g.map(_(r_idx))), s1_valid) val s2_error = (0 until coreParams.nL2TLBWays).map(way => s2_valid_vec(way) && s2_rdata(way).error).orR when (s2_valid && s2_error) { valid.foreach { _ := 0.U }} // decode val s2_entry_vec = s2_rdata.map(_.uncorrected.asTypeOf(new L2TLBEntry(nL2TLBSets))) val s2_hit_vec = (0 until coreParams.nL2TLBWays).map(way => s2_valid_vec(way) && (r_tag === s2_entry_vec(way).tag)) val s2_hit = s2_valid && s2_hit_vec.orR io.dpath.perf.l2miss := s2_valid && !(s2_hit_vec.orR) io.dpath.perf.l2hit := s2_hit when (s2_hit) { l2_plru.access(r_idx, OHToUInt(s2_hit_vec)) assert((PopCount(s2_hit_vec) === 1.U) || s2_error, "L2 TLB multi-hit") } val s2_pte = Wire(new PTE) val s2_hit_entry = Mux1H(s2_hit_vec, s2_entry_vec) s2_pte.ppn := s2_hit_entry.ppn s2_pte.d := s2_hit_entry.d s2_pte.a := s2_hit_entry.a s2_pte.g := Mux1H(s2_hit_vec, s2_g_vec) s2_pte.u := s2_hit_entry.u s2_pte.x := s2_hit_entry.x s2_pte.w := s2_hit_entry.w s2_pte.r := s2_hit_entry.r s2_pte.v := true.B s2_pte.reserved_for_future := 0.U s2_pte.reserved_for_software := 0.U for (way <- 0 until coreParams.nL2TLBWays) { ccover(s2_hit && s2_hit_vec(way), s"L2_TLB_HIT_WAY$way", s"L2 TLB hit way$way") } (s2_hit, s2_error, s2_pte, Some(ram)) } // if SFENCE occurs during walk, don't refill PTE cache or L2 TLB until next walk invalidated := io.dpath.sfence.valid || (invalidated && state =/= s_ready) // mem request io.mem.keep_clock_enabled := false.B io.mem.req.valid := state === s_req || state === s_dummy1 io.mem.req.bits.phys := true.B io.mem.req.bits.cmd := M_XRD io.mem.req.bits.size := log2Ceil(xLen/8).U io.mem.req.bits.signed := false.B io.mem.req.bits.addr := pte_addr io.mem.req.bits.idx.foreach(_ := pte_addr) io.mem.req.bits.dprv := PRV.S.U // PTW accesses are S-mode by definition io.mem.req.bits.dv := do_both_stages && !stage2 io.mem.req.bits.tag := DontCare io.mem.req.bits.no_resp := false.B io.mem.req.bits.no_alloc := DontCare io.mem.req.bits.no_xcpt := DontCare io.mem.req.bits.data := DontCare io.mem.req.bits.mask := DontCare io.mem.s1_kill := l2_hit || (state =/= s_wait1) || resp_gf io.mem.s1_data := DontCare io.mem.s2_kill := false.B val pageGranularityPMPs = pmpGranularity >= (1 << pgIdxBits) require(!usingHypervisor || pageGranularityPMPs, s"hypervisor requires pmpGranularity >= ${1<<pgIdxBits}") val pmaPgLevelHomogeneous = (0 until pgLevels) map { i => val pgSize = BigInt(1) << (pgIdxBits + ((pgLevels - 1 - i) * pgLevelBits)) if (pageGranularityPMPs && i == pgLevels - 1) { require(TLBPageLookup.homogeneous(edge.manager.managers, pgSize), s"All memory regions must be $pgSize-byte aligned") true.B } else { TLBPageLookup(edge.manager.managers, xLen, p(CacheBlockBytes), pgSize, xLen/8)(r_pte.ppn << pgIdxBits).homogeneous } } val pmaHomogeneous = pmaPgLevelHomogeneous(count) val pmpHomogeneous = new PMPHomogeneityChecker(io.dpath.pmp).apply(r_pte.ppn << pgIdxBits, count) val homogeneous = pmaHomogeneous && pmpHomogeneous // response to tlb for (i <- 0 until io.requestor.size) { io.requestor(i).resp.valid := resp_valid(i) io.requestor(i).resp.bits.ae_ptw := resp_ae_ptw io.requestor(i).resp.bits.ae_final := resp_ae_final io.requestor(i).resp.bits.pf := resp_pf io.requestor(i).resp.bits.gf := resp_gf io.requestor(i).resp.bits.hr := resp_hr io.requestor(i).resp.bits.hw := resp_hw io.requestor(i).resp.bits.hx := resp_hx io.requestor(i).resp.bits.pte := r_pte io.requestor(i).resp.bits.level := max_count io.requestor(i).resp.bits.homogeneous := homogeneous || pageGranularityPMPs.B io.requestor(i).resp.bits.fragmented_superpage := resp_fragmented_superpage && pageGranularityPMPs.B io.requestor(i).resp.bits.gpa.valid := r_req.need_gpa io.requestor(i).resp.bits.gpa.bits := Cat(Mux(!stage2_final || !r_req.vstage1 || aux_count === (pgLevels - 1).U, aux_pte.ppn, makeFragmentedSuperpagePPN(aux_pte.ppn)(aux_count)), gpa_pgoff) io.requestor(i).resp.bits.gpa_is_pte := !stage2_final io.requestor(i).ptbr := io.dpath.ptbr io.requestor(i).hgatp := io.dpath.hgatp io.requestor(i).vsatp := io.dpath.vsatp io.requestor(i).customCSRs <> io.dpath.customCSRs io.requestor(i).status := io.dpath.status io.requestor(i).hstatus := io.dpath.hstatus io.requestor(i).gstatus := io.dpath.gstatus io.requestor(i).pmp := io.dpath.pmp } // control state machine val next_state = WireDefault(state) state := OptimizationBarrier(next_state) val do_switch = WireDefault(false.B) switch (state) { is (s_ready) { when (arb.io.out.fire) { val satp_initial_count = pgLevels.U - minPgLevels.U - satp.additionalPgLevels val vsatp_initial_count = pgLevels.U - minPgLevels.U - io.dpath.vsatp.additionalPgLevels val hgatp_initial_count = pgLevels.U - minPgLevels.U - io.dpath.hgatp.additionalPgLevels val aux_ppn = Mux(arb.io.out.bits.bits.vstage1, io.dpath.vsatp.ppn, arb.io.out.bits.bits.addr) r_req := arb.io.out.bits.bits r_req_dest := arb.io.chosen next_state := Mux(arb.io.out.bits.valid, s_req, s_ready) stage2 := arb.io.out.bits.bits.stage2 stage2_final := arb.io.out.bits.bits.stage2 && !arb.io.out.bits.bits.vstage1 count := Mux(arb.io.out.bits.bits.stage2, hgatp_initial_count, satp_initial_count) aux_count := Mux(arb.io.out.bits.bits.vstage1, vsatp_initial_count, 0.U) aux_pte.ppn := aux_ppn aux_pte.reserved_for_future := 0.U resp_ae_ptw := false.B resp_ae_final := false.B resp_pf := false.B resp_gf := checkInvalidHypervisorGPA(io.dpath.hgatp, aux_ppn) && arb.io.out.bits.bits.stage2 resp_hr := true.B resp_hw := true.B resp_hx := true.B resp_fragmented_superpage := false.B r_hgatp := io.dpath.hgatp assert(!arb.io.out.bits.bits.need_gpa || arb.io.out.bits.bits.stage2) } } is (s_req) { when(stage2 && count === r_hgatp_initial_count) { gpa_pgoff := Mux(aux_count === (pgLevels-1).U, r_req.addr << (xLen/8).log2, stage2_pte_cache_addr) } // pte_cache hit when (stage2_pte_cache_hit) { aux_count := aux_count + 1.U aux_pte.ppn := stage2_pte_cache_data aux_pte.reserved_for_future := 0.U pte_hit := true.B }.elsewhen (pte_cache_hit) { count := count + 1.U pte_hit := true.B }.otherwise { next_state := Mux(io.mem.req.ready, s_wait1, s_req) } when(resp_gf) { next_state := s_ready resp_valid(r_req_dest) := true.B } } is (s_wait1) { // This Mux is for the l2_error case; the l2_hit && !l2_error case is overriden below next_state := Mux(l2_hit, s_req, s_wait2) } is (s_wait2) { next_state := s_wait3 io.dpath.perf.pte_miss := count < (pgLevels-1).U when (io.mem.s2_xcpt.ae.ld) { resp_ae_ptw := true.B next_state := s_ready resp_valid(r_req_dest) := true.B } } is (s_fragment_superpage) { next_state := s_ready resp_valid(r_req_dest) := true.B when (!homogeneous) { count := (pgLevels-1).U resp_fragmented_superpage := true.B } when (do_both_stages) { resp_fragmented_superpage := true.B } } } val merged_pte = { val superpage_masks = (0 until pgLevels).map(i => ((BigInt(1) << pte.ppn.getWidth) - (BigInt(1) << (pgLevels-1-i)*pgLevelBits)).U) val superpage_mask = superpage_masks(Mux(stage2_final, max_count, (pgLevels-1).U)) val stage1_ppns = (0 until pgLevels-1).map(i => Cat(pte.ppn(pte.ppn.getWidth-1, (pgLevels-i-1)*pgLevelBits), aux_pte.ppn((pgLevels-i-1)*pgLevelBits-1,0))) :+ pte.ppn val stage1_ppn = stage1_ppns(count) makePTE(stage1_ppn & superpage_mask, aux_pte) } r_pte := OptimizationBarrier( // l2tlb hit->find a leaf PTE(l2_pte), respond to L1TLB Mux(l2_hit && !l2_error && !resp_gf, l2_pte, // S2 PTE cache hit -> proceed to the next level of walking, update the r_pte with hgatp Mux(state === s_req && stage2_pte_cache_hit, makeHypervisorRootPTE(r_hgatp, stage2_pte_cache_data, l2_pte), // pte cache hit->find a non-leaf PTE(pte_cache),continue to request mem Mux(state === s_req && pte_cache_hit, makePTE(pte_cache_data, l2_pte), // 2-stage translation Mux(do_switch, makeHypervisorRootPTE(r_hgatp, pte.ppn, r_pte), // when mem respond, store mem.resp.pte Mux(mem_resp_valid, Mux(!traverse && r_req.vstage1 && stage2, merged_pte, pte), // fragment_superpage Mux(state === s_fragment_superpage && !homogeneous && count =/= (pgLevels - 1).U, makePTE(makeFragmentedSuperpagePPN(r_pte.ppn)(count), r_pte), // when tlb request come->request mem, use root address in satp(or vsatp,hgatp) Mux(arb.io.out.fire, Mux(arb.io.out.bits.bits.stage2, makeHypervisorRootPTE(io.dpath.hgatp, io.dpath.vsatp.ppn, r_pte), makePTE(satp.ppn, r_pte)), r_pte)))))))) when (l2_hit && !l2_error && !resp_gf) { assert(state === s_req || state === s_wait1) next_state := s_ready resp_valid(r_req_dest) := true.B count := (pgLevels-1).U } when (mem_resp_valid) { assert(state === s_wait3) next_state := s_req when (traverse) { when (do_both_stages && !stage2) { do_switch := true.B } count := count + 1.U }.otherwise { val gf = (stage2 && !stage2_final && !pte.ur()) || (pte.leaf() && pte.reserved_for_future === 0.U && invalid_gpa) val ae = pte.v && invalid_paddr val pf = pte.v && pte.reserved_for_future =/= 0.U val success = pte.v && !ae && !pf && !gf when (do_both_stages && !stage2_final && success) { when (stage2) { stage2 := false.B count := aux_count }.otherwise { stage2_final := true.B do_switch := true.B } }.otherwise { // find a leaf pte, start l2 refill l2_refill := success && count === (pgLevels-1).U && !r_req.need_gpa && (!r_req.vstage1 && !r_req.stage2 || do_both_stages && aux_count === (pgLevels-1).U && pte.isFullPerm()) count := max_count when (pageGranularityPMPs.B && !(count === (pgLevels-1).U && (!do_both_stages || aux_count === (pgLevels-1).U))) { next_state := s_fragment_superpage }.otherwise { next_state := s_ready resp_valid(r_req_dest) := true.B } resp_ae_ptw := ae && count < (pgLevels-1).U && pte.table() resp_ae_final := ae && pte.leaf() resp_pf := pf && !stage2 resp_gf := gf || (pf && stage2) resp_hr := !stage2 || (!pf && !gf && pte.ur()) resp_hw := !stage2 || (!pf && !gf && pte.uw()) resp_hx := !stage2 || (!pf && !gf && pte.ux()) } } } when (io.mem.s2_nack) { assert(state === s_wait2) next_state := s_req } when (do_switch) { aux_count := Mux(traverse, count + 1.U, count) count := r_hgatp_initial_count aux_pte := Mux(traverse, pte, { val s1_ppns = (0 until pgLevels-1).map(i => Cat(pte.ppn(pte.ppn.getWidth-1, (pgLevels-i-1)*pgLevelBits), r_req.addr(((pgLevels-i-1)*pgLevelBits min vpnBits)-1,0).padTo((pgLevels-i-1)*pgLevelBits))) :+ pte.ppn makePTE(s1_ppns(count), pte) }) stage2 := true.B } for (i <- 0 until pgLevels) { val leaf = mem_resp_valid && !traverse && count === i.U ccover(leaf && pte.v && !invalid_paddr && !invalid_gpa && pte.reserved_for_future === 0.U, s"L$i", s"successful page-table access, level $i") ccover(leaf && pte.v && invalid_paddr, s"L${i}_BAD_PPN_MSB", s"PPN too large, level $i") ccover(leaf && pte.v && invalid_gpa, s"L${i}_BAD_GPA_MSB", s"GPA too large, level $i") ccover(leaf && pte.v && pte.reserved_for_future =/= 0.U, s"L${i}_BAD_RSV_MSB", s"reserved MSBs set, level $i") ccover(leaf && !mem_resp_data(0), s"L${i}_INVALID_PTE", s"page not present, level $i") if (i != pgLevels-1) ccover(leaf && !pte.v && mem_resp_data(0), s"L${i}_BAD_PPN_LSB", s"PPN LSBs not zero, level $i") } ccover(mem_resp_valid && count === (pgLevels-1).U && pte.table(), s"TOO_DEEP", s"page table too deep") ccover(io.mem.s2_nack, "NACK", "D$ nacked page-table access") ccover(state === s_wait2 && io.mem.s2_xcpt.ae.ld, "AE", "access exception while walking page table") } // leaving gated-clock domain private def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = if (usingVM) property.cover(cond, s"PTW_$label", "MemorySystem;;" + desc) /** Relace PTE.ppn with ppn */ private def makePTE(ppn: UInt, default: PTE) = { val pte = WireDefault(default) pte.ppn := ppn pte } /** use hgatp and vpn to construct a new ppn */ private def makeHypervisorRootPTE(hgatp: PTBR, vpn: UInt, default: PTE) = { val count = pgLevels.U - minPgLevels.U - hgatp.additionalPgLevels val idxs = (0 to pgLevels-minPgLevels).map(i => (vpn >> (pgLevels-i)*pgLevelBits)) val lsbs = WireDefault(UInt(maxHypervisorExtraAddrBits.W), idxs(count)) val pte = WireDefault(default) pte.ppn := Cat(hgatp.ppn >> maxHypervisorExtraAddrBits, lsbs) pte } /** use hgatp and vpn to check for gpa out of range */ private def checkInvalidHypervisorGPA(hgatp: PTBR, vpn: UInt) = { val count = pgLevels.U - minPgLevels.U - hgatp.additionalPgLevels val idxs = (0 to pgLevels-minPgLevels).map(i => (vpn >> ((pgLevels-i)*pgLevelBits)+maxHypervisorExtraAddrBits)) idxs.extract(count) =/= 0.U } } /** Mix-ins for constructing tiles that might have a PTW */ trait CanHavePTW extends HasTileParameters with HasHellaCache { this: BaseTile => val module: CanHavePTWModule var nPTWPorts = 1 nDCachePorts += usingPTW.toInt } trait CanHavePTWModule extends HasHellaCacheModule { val outer: CanHavePTW val ptwPorts = ListBuffer(outer.dcache.module.io.ptw) val ptw = Module(new PTW(outer.nPTWPorts)(outer.dcache.node.edges.out(0), outer.p)) ptw.io.mem <> DontCare if (outer.usingPTW) { dcachePorts += ptw.io.mem } }

module DTLB_13( // @[TLB.scala:318:7] input clock, // @[TLB.scala:318:7] input reset, // @[TLB.scala:318:7] output io_req_ready, // @[TLB.scala:320:14] input io_req_valid, // @[TLB.scala:320:14] input [39:0] io_req_bits_vaddr, // @[TLB.scala:320:14] input [1:0] io_req_bits_size, // @[TLB.scala:320:14] input [4:0] io_req_bits_cmd, // @[TLB.scala:320:14] output io_resp_miss, // @[TLB.scala:320:14] output [31:0] io_resp_paddr, // @[TLB.scala:320:14] input io_sfence_valid, // @[TLB.scala:320:14] input io_ptw_req_ready, // @[TLB.scala:320:14] output io_ptw_req_valid, // @[TLB.scala:320:14] output [26:0] io_ptw_req_bits_bits_addr, // @[TLB.scala:320:14] output io_ptw_req_bits_bits_need_gpa, // @[TLB.scala:320:14] input io_ptw_resp_valid, // @[TLB.scala:320:14] input io_ptw_resp_bits_ae_ptw, // @[TLB.scala:320:14] input io_ptw_resp_bits_ae_final, // @[TLB.scala:320:14] input io_ptw_resp_bits_pf, // @[TLB.scala:320:14] input io_ptw_resp_bits_gf, // @[TLB.scala:320:14] input io_ptw_resp_bits_hr, // @[TLB.scala:320:14] input io_ptw_resp_bits_hw, // @[TLB.scala:320:14] input io_ptw_resp_bits_hx, // @[TLB.scala:320:14] input [9:0] io_ptw_resp_bits_pte_reserved_for_future, // @[TLB.scala:320:14] input [43:0] io_ptw_resp_bits_pte_ppn, // @[TLB.scala:320:14] input [1:0] io_ptw_resp_bits_pte_reserved_for_software, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_d, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_a, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_g, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_u, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_x, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_w, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_r, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_v, // @[TLB.scala:320:14] input [1:0] io_ptw_resp_bits_level, // @[TLB.scala:320:14] input io_ptw_resp_bits_homogeneous, // @[TLB.scala:320:14] input io_ptw_resp_bits_gpa_valid, // @[TLB.scala:320:14] input [38:0] io_ptw_resp_bits_gpa_bits, // @[TLB.scala:320:14] input io_ptw_resp_bits_gpa_is_pte, // @[TLB.scala:320:14] input [3:0] io_ptw_ptbr_mode, // @[TLB.scala:320:14] input [43:0] io_ptw_ptbr_ppn, // @[TLB.scala:320:14] input io_ptw_status_debug, // @[TLB.scala:320:14] input io_ptw_status_cease, // @[TLB.scala:320:14] input io_ptw_status_wfi, // @[TLB.scala:320:14] input [31:0] io_ptw_status_isa, // @[TLB.scala:320:14] input [1:0] io_ptw_status_dprv, // @[TLB.scala:320:14] input io_ptw_status_dv, // @[TLB.scala:320:14] input [1:0] io_ptw_status_prv, // @[TLB.scala:320:14] input io_ptw_status_v, // @[TLB.scala:320:14] input io_ptw_status_sd, // @[TLB.scala:320:14] input [22:0] io_ptw_status_zero2, // @[TLB.scala:320:14] input io_ptw_status_mpv, // @[TLB.scala:320:14] input io_ptw_status_gva, // @[TLB.scala:320:14] input io_ptw_status_mbe, // @[TLB.scala:320:14] input io_ptw_status_sbe, // @[TLB.scala:320:14] input [1:0] io_ptw_status_sxl, // @[TLB.scala:320:14] input [1:0] io_ptw_status_uxl, // @[TLB.scala:320:14] input io_ptw_status_sd_rv32, // @[TLB.scala:320:14] input [7:0] io_ptw_status_zero1, // @[TLB.scala:320:14] input io_ptw_status_tsr, // @[TLB.scala:320:14] input io_ptw_status_tw, // @[TLB.scala:320:14] input io_ptw_status_tvm, // @[TLB.scala:320:14] input io_ptw_status_mxr, // @[TLB.scala:320:14] input io_ptw_status_sum, // @[TLB.scala:320:14] input io_ptw_status_mprv, // @[TLB.scala:320:14] input [1:0] io_ptw_status_xs, // @[TLB.scala:320:14] input [1:0] io_ptw_status_fs, // @[TLB.scala:320:14] input [1:0] io_ptw_status_mpp, // @[TLB.scala:320:14] input [1:0] io_ptw_status_vs, // @[TLB.scala:320:14] input io_ptw_status_spp, // @[TLB.scala:320:14] input io_ptw_status_mpie, // @[TLB.scala:320:14] input io_ptw_status_ube, // @[TLB.scala:320:14] input io_ptw_status_spie, // @[TLB.scala:320:14] input io_ptw_status_upie, // @[TLB.scala:320:14] input io_ptw_status_mie, // @[TLB.scala:320:14] input io_ptw_status_hie, // @[TLB.scala:320:14] input io_ptw_status_sie, // @[TLB.scala:320:14] input io_ptw_status_uie, // @[TLB.scala:320:14] input io_ptw_hstatus_spvp, // @[TLB.scala:320:14] input io_ptw_hstatus_spv, // @[TLB.scala:320:14] input io_ptw_hstatus_gva, // @[TLB.scala:320:14] input io_ptw_gstatus_debug, // @[TLB.scala:320:14] input io_ptw_gstatus_cease, // @[TLB.scala:320:14] input io_ptw_gstatus_wfi, // @[TLB.scala:320:14] input [31:0] io_ptw_gstatus_isa, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_dprv, // @[TLB.scala:320:14] input io_ptw_gstatus_dv, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_prv, // @[TLB.scala:320:14] input io_ptw_gstatus_v, // @[TLB.scala:320:14] input [22:0] io_ptw_gstatus_zero2, // @[TLB.scala:320:14] input io_ptw_gstatus_mpv, // @[TLB.scala:320:14] input io_ptw_gstatus_gva, // @[TLB.scala:320:14] input io_ptw_gstatus_mbe, // @[TLB.scala:320:14] input io_ptw_gstatus_sbe, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_sxl, // @[TLB.scala:320:14] input [7:0] io_ptw_gstatus_zero1, // @[TLB.scala:320:14] input io_ptw_gstatus_tsr, // @[TLB.scala:320:14] input io_ptw_gstatus_tw, // @[TLB.scala:320:14] input io_ptw_gstatus_tvm, // @[TLB.scala:320:14] input io_ptw_gstatus_mxr, // @[TLB.scala:320:14] input io_ptw_gstatus_sum, // @[TLB.scala:320:14] input io_ptw_gstatus_mprv, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_fs, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_mpp, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_vs, // @[TLB.scala:320:14] input io_ptw_gstatus_spp, // @[TLB.scala:320:14] input io_ptw_gstatus_mpie, // @[TLB.scala:320:14] input io_ptw_gstatus_ube, // @[TLB.scala:320:14] input io_ptw_gstatus_spie, // @[TLB.scala:320:14] input io_ptw_gstatus_upie, // @[TLB.scala:320:14] input io_ptw_gstatus_mie, // @[TLB.scala:320:14] input io_ptw_gstatus_hie, // @[TLB.scala:320:14] input io_ptw_gstatus_sie, // @[TLB.scala:320:14] input io_ptw_gstatus_uie, // @[TLB.scala:320:14] input io_ptw_pmp_0_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_0_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_0_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_0_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_0_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_0_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_0_mask, // @[TLB.scala:320:14] input io_ptw_pmp_1_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_1_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_1_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_1_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_1_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_1_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_1_mask, // @[TLB.scala:320:14] input io_ptw_pmp_2_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_2_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_2_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_2_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_2_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_2_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_2_mask, // @[TLB.scala:320:14] input io_ptw_pmp_3_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_3_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_3_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_3_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_3_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_3_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_3_mask, // @[TLB.scala:320:14] input io_ptw_pmp_4_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_4_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_4_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_4_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_4_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_4_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_4_mask, // @[TLB.scala:320:14] input io_ptw_pmp_5_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_5_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_5_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_5_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_5_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_5_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_5_mask, // @[TLB.scala:320:14] input io_ptw_pmp_6_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_6_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_6_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_6_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_6_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_6_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_6_mask, // @[TLB.scala:320:14] input io_ptw_pmp_7_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_7_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_7_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_7_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_7_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_7_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_7_mask, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_0_ren, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_0_wen, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_0_wdata, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_0_value, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_1_ren, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_1_wen, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_1_wdata, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_1_value, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_2_ren, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_2_wen, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_2_wdata, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_2_value, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_3_ren, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_3_wen, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_3_wdata, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_3_value // @[TLB.scala:320:14] ); wire [19:0] _entries_barrier_5_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_5_io_y_u; // @[package.scala:267:25] wire _entries_barrier_5_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_5_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_5_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_5_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_5_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_5_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_5_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_5_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_5_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_5_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_5_io_y_hr; // @[package.scala:267:25] wire [19:0] _entries_barrier_4_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_4_io_y_u; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_4_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_4_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_4_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_4_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_4_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_px; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_4_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_4_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_4_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_3_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_3_io_y_u; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_3_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_3_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_3_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_3_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_3_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_px; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_3_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_3_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_3_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_2_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_2_io_y_u; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_2_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_2_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_2_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_2_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_2_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_px; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_2_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_2_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_2_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_1_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_1_io_y_u; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_1_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_1_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_1_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_1_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_1_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_px; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_1_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_1_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_1_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_io_y_u; // @[package.scala:267:25] wire _entries_barrier_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_io_y_px; // @[package.scala:267:25] wire _entries_barrier_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_io_y_c; // @[package.scala:267:25] wire _pma_io_resp_r; // @[TLB.scala:422:19] wire _pma_io_resp_w; // @[TLB.scala:422:19] wire _pma_io_resp_pp; // @[TLB.scala:422:19] wire _pma_io_resp_al; // @[TLB.scala:422:19] wire _pma_io_resp_aa; // @[TLB.scala:422:19] wire _pma_io_resp_x; // @[TLB.scala:422:19] wire _pma_io_resp_eff; // @[TLB.scala:422:19] wire _pmp_io_r; // @[TLB.scala:416:19] wire _pmp_io_w; // @[TLB.scala:416:19] wire _pmp_io_x; // @[TLB.scala:416:19] wire [19:0] _mpu_ppn_barrier_io_y_ppn; // @[package.scala:267:25] wire io_req_valid_0 = io_req_valid; // @[TLB.scala:318:7] wire [39:0] io_req_bits_vaddr_0 = io_req_bits_vaddr; // @[TLB.scala:318:7] wire [1:0] io_req_bits_size_0 = io_req_bits_size; // @[TLB.scala:318:7] wire [4:0] io_req_bits_cmd_0 = io_req_bits_cmd; // @[TLB.scala:318:7] wire io_sfence_valid_0 = io_sfence_valid; // @[TLB.scala:318:7] wire io_ptw_req_ready_0 = io_ptw_req_ready; // @[TLB.scala:318:7] wire io_ptw_resp_valid_0 = io_ptw_resp_valid; // @[TLB.scala:318:7] wire io_ptw_resp_bits_ae_ptw_0 = io_ptw_resp_bits_ae_ptw; // @[TLB.scala:318:7] wire io_ptw_resp_bits_ae_final_0 = io_ptw_resp_bits_ae_final; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pf_0 = io_ptw_resp_bits_pf; // @[TLB.scala:318:7] wire io_ptw_resp_bits_gf_0 = io_ptw_resp_bits_gf; // @[TLB.scala:318:7] wire io_ptw_resp_bits_hr_0 = io_ptw_resp_bits_hr; // @[TLB.scala:318:7] wire io_ptw_resp_bits_hw_0 = io_ptw_resp_bits_hw; // @[TLB.scala:318:7] wire io_ptw_resp_bits_hx_0 = io_ptw_resp_bits_hx; // @[TLB.scala:318:7] wire [9:0] io_ptw_resp_bits_pte_reserved_for_future_0 = io_ptw_resp_bits_pte_reserved_for_future; // @[TLB.scala:318:7] wire [43:0] io_ptw_resp_bits_pte_ppn_0 = io_ptw_resp_bits_pte_ppn; // @[TLB.scala:318:7] wire [1:0] io_ptw_resp_bits_pte_reserved_for_software_0 = io_ptw_resp_bits_pte_reserved_for_software; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_d_0 = io_ptw_resp_bits_pte_d; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_a_0 = io_ptw_resp_bits_pte_a; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_g_0 = io_ptw_resp_bits_pte_g; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_u_0 = io_ptw_resp_bits_pte_u; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_x_0 = io_ptw_resp_bits_pte_x; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_w_0 = io_ptw_resp_bits_pte_w; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_r_0 = io_ptw_resp_bits_pte_r; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_v_0 = io_ptw_resp_bits_pte_v; // @[TLB.scala:318:7] wire [1:0] io_ptw_resp_bits_level_0 = io_ptw_resp_bits_level; // @[TLB.scala:318:7] wire io_ptw_resp_bits_homogeneous_0 = io_ptw_resp_bits_homogeneous; // @[TLB.scala:318:7] wire io_ptw_resp_bits_gpa_valid_0 = io_ptw_resp_bits_gpa_valid; // @[TLB.scala:318:7] wire [38:0] io_ptw_resp_bits_gpa_bits_0 = io_ptw_resp_bits_gpa_bits; // @[TLB.scala:318:7] wire io_ptw_resp_bits_gpa_is_pte_0 = io_ptw_resp_bits_gpa_is_pte; // @[TLB.scala:318:7] wire [3:0] io_ptw_ptbr_mode_0 = io_ptw_ptbr_mode; // @[TLB.scala:318:7] wire [43:0] io_ptw_ptbr_ppn_0 = io_ptw_ptbr_ppn; // @[TLB.scala:318:7] wire io_ptw_status_debug_0 = io_ptw_status_debug; // @[TLB.scala:318:7] wire io_ptw_status_cease_0 = io_ptw_status_cease; // @[TLB.scala:318:7] wire io_ptw_status_wfi_0 = io_ptw_status_wfi; // @[TLB.scala:318:7] wire [31:0] io_ptw_status_isa_0 = io_ptw_status_isa; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_dprv_0 = io_ptw_status_dprv; // @[TLB.scala:318:7] wire io_ptw_status_dv_0 = io_ptw_status_dv; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_prv_0 = io_ptw_status_prv; // @[TLB.scala:318:7] wire io_ptw_status_v_0 = io_ptw_status_v; // @[TLB.scala:318:7] wire io_ptw_status_sd_0 = io_ptw_status_sd; // @[TLB.scala:318:7] wire [22:0] io_ptw_status_zero2_0 = io_ptw_status_zero2; // @[TLB.scala:318:7] wire io_ptw_status_mpv_0 = io_ptw_status_mpv; // @[TLB.scala:318:7] wire io_ptw_status_gva_0 = io_ptw_status_gva; // @[TLB.scala:318:7] wire io_ptw_status_mbe_0 = io_ptw_status_mbe; // @[TLB.scala:318:7] wire io_ptw_status_sbe_0 = io_ptw_status_sbe; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_sxl_0 = io_ptw_status_sxl; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_uxl_0 = io_ptw_status_uxl; // @[TLB.scala:318:7] wire io_ptw_status_sd_rv32_0 = io_ptw_status_sd_rv32; // @[TLB.scala:318:7] wire [7:0] io_ptw_status_zero1_0 = io_ptw_status_zero1; // @[TLB.scala:318:7] wire io_ptw_status_tsr_0 = io_ptw_status_tsr; // @[TLB.scala:318:7] wire io_ptw_status_tw_0 = io_ptw_status_tw; // @[TLB.scala:318:7] wire io_ptw_status_tvm_0 = io_ptw_status_tvm; // @[TLB.scala:318:7] wire io_ptw_status_mxr_0 = io_ptw_status_mxr; // @[TLB.scala:318:7] wire io_ptw_status_sum_0 = io_ptw_status_sum; // @[TLB.scala:318:7] wire io_ptw_status_mprv_0 = io_ptw_status_mprv; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_xs_0 = io_ptw_status_xs; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_fs_0 = io_ptw_status_fs; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_mpp_0 = io_ptw_status_mpp; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_vs_0 = io_ptw_status_vs; // @[TLB.scala:318:7] wire io_ptw_status_spp_0 = io_ptw_status_spp; // @[TLB.scala:318:7] wire io_ptw_status_mpie_0 = io_ptw_status_mpie; // @[TLB.scala:318:7] wire io_ptw_status_ube_0 = io_ptw_status_ube; // @[TLB.scala:318:7] wire io_ptw_status_spie_0 = io_ptw_status_spie; // @[TLB.scala:318:7] wire io_ptw_status_upie_0 = io_ptw_status_upie; // @[TLB.scala:318:7] wire io_ptw_status_mie_0 = io_ptw_status_mie; // @[TLB.scala:318:7] wire io_ptw_status_hie_0 = io_ptw_status_hie; // @[TLB.scala:318:7] wire io_ptw_status_sie_0 = io_ptw_status_sie; // @[TLB.scala:318:7] wire io_ptw_status_uie_0 = io_ptw_status_uie; // @[TLB.scala:318:7] wire io_ptw_hstatus_spvp_0 = io_ptw_hstatus_spvp; // @[TLB.scala:318:7] wire io_ptw_hstatus_spv_0 = io_ptw_hstatus_spv; // @[TLB.scala:318:7] wire io_ptw_hstatus_gva_0 = io_ptw_hstatus_gva; // @[TLB.scala:318:7] wire io_ptw_gstatus_debug_0 = io_ptw_gstatus_debug; // @[TLB.scala:318:7] wire io_ptw_gstatus_cease_0 = io_ptw_gstatus_cease; // @[TLB.scala:318:7] wire io_ptw_gstatus_wfi_0 = io_ptw_gstatus_wfi; // @[TLB.scala:318:7] wire [31:0] io_ptw_gstatus_isa_0 = io_ptw_gstatus_isa; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_dprv_0 = io_ptw_gstatus_dprv; // @[TLB.scala:318:7] wire io_ptw_gstatus_dv_0 = io_ptw_gstatus_dv; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_prv_0 = io_ptw_gstatus_prv; // @[TLB.scala:318:7] wire io_ptw_gstatus_v_0 = io_ptw_gstatus_v; // @[TLB.scala:318:7] wire [22:0] io_ptw_gstatus_zero2_0 = io_ptw_gstatus_zero2; // @[TLB.scala:318:7] wire io_ptw_gstatus_mpv_0 = io_ptw_gstatus_mpv; // @[TLB.scala:318:7] wire io_ptw_gstatus_gva_0 = io_ptw_gstatus_gva; // @[TLB.scala:318:7] wire io_ptw_gstatus_mbe_0 = io_ptw_gstatus_mbe; // @[TLB.scala:318:7] wire io_ptw_gstatus_sbe_0 = io_ptw_gstatus_sbe; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_sxl_0 = io_ptw_gstatus_sxl; // @[TLB.scala:318:7] wire [7:0] io_ptw_gstatus_zero1_0 = io_ptw_gstatus_zero1; // @[TLB.scala:318:7] wire io_ptw_gstatus_tsr_0 = io_ptw_gstatus_tsr; // @[TLB.scala:318:7] wire io_ptw_gstatus_tw_0 = io_ptw_gstatus_tw; // @[TLB.scala:318:7] wire io_ptw_gstatus_tvm_0 = io_ptw_gstatus_tvm; // @[TLB.scala:318:7] wire io_ptw_gstatus_mxr_0 = io_ptw_gstatus_mxr; // @[TLB.scala:318:7] wire io_ptw_gstatus_sum_0 = io_ptw_gstatus_sum; // @[TLB.scala:318:7] wire io_ptw_gstatus_mprv_0 = io_ptw_gstatus_mprv; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_fs_0 = io_ptw_gstatus_fs; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_mpp_0 = io_ptw_gstatus_mpp; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_vs_0 = io_ptw_gstatus_vs; // @[TLB.scala:318:7] wire io_ptw_gstatus_spp_0 = io_ptw_gstatus_spp; // @[TLB.scala:318:7] wire io_ptw_gstatus_mpie_0 = io_ptw_gstatus_mpie; // @[TLB.scala:318:7] wire io_ptw_gstatus_ube_0 = io_ptw_gstatus_ube; // @[TLB.scala:318:7] wire io_ptw_gstatus_spie_0 = io_ptw_gstatus_spie; // @[TLB.scala:318:7] wire io_ptw_gstatus_upie_0 = io_ptw_gstatus_upie; // @[TLB.scala:318:7] wire io_ptw_gstatus_mie_0 = io_ptw_gstatus_mie; // @[TLB.scala:318:7] wire io_ptw_gstatus_hie_0 = io_ptw_gstatus_hie; // @[TLB.scala:318:7] wire io_ptw_gstatus_sie_0 = io_ptw_gstatus_sie; // @[TLB.scala:318:7] wire io_ptw_gstatus_uie_0 = io_ptw_gstatus_uie; // @[TLB.scala:318:7] wire io_ptw_pmp_0_cfg_l_0 = io_ptw_pmp_0_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_0_cfg_a_0 = io_ptw_pmp_0_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_0_cfg_x_0 = io_ptw_pmp_0_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_0_cfg_w_0 = io_ptw_pmp_0_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_0_cfg_r_0 = io_ptw_pmp_0_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_0_addr_0 = io_ptw_pmp_0_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_0_mask_0 = io_ptw_pmp_0_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_1_cfg_l_0 = io_ptw_pmp_1_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_1_cfg_a_0 = io_ptw_pmp_1_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_1_cfg_x_0 = io_ptw_pmp_1_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_1_cfg_w_0 = io_ptw_pmp_1_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_1_cfg_r_0 = io_ptw_pmp_1_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_1_addr_0 = io_ptw_pmp_1_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_1_mask_0 = io_ptw_pmp_1_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_2_cfg_l_0 = io_ptw_pmp_2_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_2_cfg_a_0 = io_ptw_pmp_2_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_2_cfg_x_0 = io_ptw_pmp_2_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_2_cfg_w_0 = io_ptw_pmp_2_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_2_cfg_r_0 = io_ptw_pmp_2_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_2_addr_0 = io_ptw_pmp_2_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_2_mask_0 = io_ptw_pmp_2_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_3_cfg_l_0 = io_ptw_pmp_3_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_3_cfg_a_0 = io_ptw_pmp_3_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_3_cfg_x_0 = io_ptw_pmp_3_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_3_cfg_w_0 = io_ptw_pmp_3_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_3_cfg_r_0 = io_ptw_pmp_3_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_3_addr_0 = io_ptw_pmp_3_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_3_mask_0 = io_ptw_pmp_3_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_4_cfg_l_0 = io_ptw_pmp_4_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_4_cfg_a_0 = io_ptw_pmp_4_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_4_cfg_x_0 = io_ptw_pmp_4_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_4_cfg_w_0 = io_ptw_pmp_4_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_4_cfg_r_0 = io_ptw_pmp_4_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_4_addr_0 = io_ptw_pmp_4_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_4_mask_0 = io_ptw_pmp_4_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_5_cfg_l_0 = io_ptw_pmp_5_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_5_cfg_a_0 = io_ptw_pmp_5_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_5_cfg_x_0 = io_ptw_pmp_5_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_5_cfg_w_0 = io_ptw_pmp_5_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_5_cfg_r_0 = io_ptw_pmp_5_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_5_addr_0 = io_ptw_pmp_5_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_5_mask_0 = io_ptw_pmp_5_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_6_cfg_l_0 = io_ptw_pmp_6_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_6_cfg_a_0 = io_ptw_pmp_6_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_6_cfg_x_0 = io_ptw_pmp_6_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_6_cfg_w_0 = io_ptw_pmp_6_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_6_cfg_r_0 = io_ptw_pmp_6_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_6_addr_0 = io_ptw_pmp_6_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_6_mask_0 = io_ptw_pmp_6_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_7_cfg_l_0 = io_ptw_pmp_7_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_7_cfg_a_0 = io_ptw_pmp_7_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_7_cfg_x_0 = io_ptw_pmp_7_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_7_cfg_w_0 = io_ptw_pmp_7_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_7_cfg_r_0 = io_ptw_pmp_7_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_7_addr_0 = io_ptw_pmp_7_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_7_mask_0 = io_ptw_pmp_7_mask; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_0_ren_0 = io_ptw_customCSRs_csrs_0_ren; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_0_wen_0 = io_ptw_customCSRs_csrs_0_wen; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_0_wdata_0 = io_ptw_customCSRs_csrs_0_wdata; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_0_value_0 = io_ptw_customCSRs_csrs_0_value; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_1_ren_0 = io_ptw_customCSRs_csrs_1_ren; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_1_wen_0 = io_ptw_customCSRs_csrs_1_wen; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_1_wdata_0 = io_ptw_customCSRs_csrs_1_wdata; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_1_value_0 = io_ptw_customCSRs_csrs_1_value; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_2_ren_0 = io_ptw_customCSRs_csrs_2_ren; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_2_wen_0 = io_ptw_customCSRs_csrs_2_wen; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_2_wdata_0 = io_ptw_customCSRs_csrs_2_wdata; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_2_value_0 = io_ptw_customCSRs_csrs_2_value; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_3_ren_0 = io_ptw_customCSRs_csrs_3_ren; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_3_wen_0 = io_ptw_customCSRs_csrs_3_wen; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_3_wdata_0 = io_ptw_customCSRs_csrs_3_wdata; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_3_value_0 = io_ptw_customCSRs_csrs_3_value; // @[TLB.scala:318:7] wire [6:0] hr_array = 7'h7F; // @[TLB.scala:524:21] wire [6:0] hw_array = 7'h7F; // @[TLB.scala:525:21] wire [6:0] hx_array = 7'h7F; // @[TLB.scala:526:21] wire [6:0] _must_alloc_array_T_8 = 7'h7F; // @[TLB.scala:596:19] wire [6:0] _gf_ld_array_T_1 = 7'h7F; // @[TLB.scala:600:50] wire [5:0] stage2_bypass = 6'h3F; // @[TLB.scala:523:27] wire [5:0] _hr_array_T_4 = 6'h3F; // @[TLB.scala:524:111] wire [5:0] _hw_array_T_1 = 6'h3F; // @[TLB.scala:525:55] wire [5:0] _hx_array_T_1 = 6'h3F; // @[TLB.scala:526:55] wire [5:0] _gpa_hits_hit_mask_T_4 = 6'h3F; // @[TLB.scala:606:88] wire [5:0] gpa_hits_hit_mask = 6'h3F; // @[TLB.scala:606:82] wire [5:0] _gpa_hits_T_1 = 6'h3F; // @[TLB.scala:607:16] wire [5:0] gpa_hits = 6'h3F; // @[TLB.scala:607:14] wire [2:0] _state_vec_WIRE_0 = 3'h0; // @[Replacement.scala:305:25] wire [2:0] _state_vec_WIRE_1 = 3'h0; // @[Replacement.scala:305:25] wire [2:0] _state_vec_WIRE_2 = 3'h0; // @[Replacement.scala:305:25] wire [2:0] _state_vec_WIRE_3 = 3'h0; // @[Replacement.scala:305:25] wire [6:0] _gf_ld_array_T_2 = 7'h0; // @[TLB.scala:600:46] wire [6:0] gf_ld_array = 7'h0; // @[TLB.scala:600:24] wire [6:0] _gf_st_array_T_1 = 7'h0; // @[TLB.scala:601:53] wire [6:0] gf_st_array = 7'h0; // @[TLB.scala:601:24] wire [6:0] _gf_inst_array_T = 7'h0; // @[TLB.scala:602:36] wire [6:0] gf_inst_array = 7'h0; // @[TLB.scala:602:26] wire [6:0] gpa_hits_need_gpa_mask = 7'h0; // @[TLB.scala:605:73] wire [6:0] _io_resp_gf_ld_T_1 = 7'h0; // @[TLB.scala:637:58] wire [6:0] _io_resp_gf_st_T_1 = 7'h0; // @[TLB.scala:638:65] wire [6:0] _io_resp_gf_inst_T = 7'h0; // @[TLB.scala:639:48] wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_2_sdata = 64'h0; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_3_sdata = 64'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_hstatus_vsxl = 2'h2; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_uxl = 2'h2; // @[TLB.scala:318:7] wire [38:0] io_sfence_bits_addr = 39'h0; // @[TLB.scala:318:7, :320:14] wire [1:0] io_ptw_gstatus_xs = 2'h3; // @[TLB.scala:318:7] wire io_ptw_req_bits_valid = 1'h1; // @[TLB.scala:318:7] wire io_ptw_gstatus_sd = 1'h1; // @[TLB.scala:318:7] wire priv_uses_vm = 1'h1; // @[TLB.scala:372:27] wire _vm_enabled_T_2 = 1'h1; // @[TLB.scala:399:64] wire _vsatp_mode_mismatch_T_2 = 1'h1; // @[TLB.scala:403:81] wire _homogeneous_T_59 = 1'h1; // @[TLBPermissions.scala:87:22] wire superpage_hits_ignore_2 = 1'h1; // @[TLB.scala:182:34] wire _superpage_hits_T_13 = 1'h1; // @[TLB.scala:183:40] wire hitsVec_ignore_2 = 1'h1; // @[TLB.scala:182:34] wire _hitsVec_T_37 = 1'h1; // @[TLB.scala:183:40] wire ppn_ignore_1 = 1'h1; // @[TLB.scala:197:34] wire _priv_rw_ok_T = 1'h1; // @[TLB.scala:513:24] wire _priv_rw_ok_T_1 = 1'h1; // @[TLB.scala:513:32] wire _stage2_bypass_T = 1'h1; // @[TLB.scala:523:42] wire _bad_va_T_1 = 1'h1; // @[TLB.scala:560:26] wire _gpa_hits_hit_mask_T_3 = 1'h1; // @[TLB.scala:606:107] wire _tlb_miss_T = 1'h1; // @[TLB.scala:613:32] wire _io_resp_gpa_page_T = 1'h1; // @[TLB.scala:657:20] wire _io_ptw_req_bits_valid_T = 1'h1; // @[TLB.scala:663:28] wire ignore_2 = 1'h1; // @[TLB.scala:182:34] wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[TLB.scala:318:7] wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[TLB.scala:318:7] wire [5:0] _priv_rw_ok_T_6 = 6'h0; // @[TLB.scala:513:75] wire [5:0] _stage1_bypass_T = 6'h0; // @[TLB.scala:517:27] wire [5:0] stage1_bypass = 6'h0; // @[TLB.scala:517:61] wire [5:0] _gpa_hits_T = 6'h0; // @[TLB.scala:607:30] wire [1:0] io_req_bits_prv = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_0_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_1_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_2_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_3_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_4_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_5_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_6_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_7_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[TLB.scala:318:7, :320:14] wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[TLB.scala:318:7, :320:14] wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[TLB.scala:318:7, :320:14] wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[TLB.scala:318:7, :320:14] wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[TLB.scala:318:7, :320:14] wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[TLB.scala:318:7, :320:14] wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[TLB.scala:318:7, :320:14, :373:17] wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[TLB.scala:318:7, :320:14, :373:17] wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[TLB.scala:318:7, :320:14, :373:17] wire [15:0] satp_asid = 16'h0; // @[TLB.scala:318:7, :320:14, :373:17] wire io_req_bits_passthrough = 1'h0; // @[TLB.scala:318:7] wire io_req_bits_v = 1'h0; // @[TLB.scala:318:7] wire io_resp_gpa_is_pte = 1'h0; // @[TLB.scala:318:7] wire io_resp_gf_ld = 1'h0; // @[TLB.scala:318:7] wire io_resp_gf_st = 1'h0; // @[TLB.scala:318:7] wire io_resp_gf_inst = 1'h0; // @[TLB.scala:318:7] wire io_resp_ma_inst = 1'h0; // @[TLB.scala:318:7] wire io_sfence_bits_rs1 = 1'h0; // @[TLB.scala:318:7] wire io_sfence_bits_rs2 = 1'h0; // @[TLB.scala:318:7] wire io_sfence_bits_asid = 1'h0; // @[TLB.scala:318:7] wire io_sfence_bits_hv = 1'h0; // @[TLB.scala:318:7] wire io_sfence_bits_hg = 1'h0; // @[TLB.scala:318:7] wire io_ptw_req_bits_bits_vstage1 = 1'h0; // @[TLB.scala:318:7] wire io_ptw_req_bits_bits_stage2 = 1'h0; // @[TLB.scala:318:7] wire io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_vtsr = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_vtw = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_vtvm = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_hu = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_vsbe = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_2_stall = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_2_set = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_3_stall = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_3_set = 1'h0; // @[TLB.scala:318:7] wire io_kill = 1'h0; // @[TLB.scala:318:7] wire priv_v = 1'h0; // @[TLB.scala:369:34] wire priv_s = 1'h0; // @[TLB.scala:370:20] wire _vstage1_en_T = 1'h0; // @[TLB.scala:376:38] wire _vstage1_en_T_1 = 1'h0; // @[TLB.scala:376:68] wire vstage1_en = 1'h0; // @[TLB.scala:376:48] wire _stage2_en_T = 1'h0; // @[TLB.scala:378:38] wire _stage2_en_T_1 = 1'h0; // @[TLB.scala:378:68] wire stage2_en = 1'h0; // @[TLB.scala:378:48] wire _vsatp_mode_mismatch_T = 1'h0; // @[TLB.scala:403:52] wire _vsatp_mode_mismatch_T_1 = 1'h0; // @[TLB.scala:403:37] wire vsatp_mode_mismatch = 1'h0; // @[TLB.scala:403:78] wire _superpage_hits_ignore_T = 1'h0; // @[TLB.scala:182:28] wire superpage_hits_ignore = 1'h0; // @[TLB.scala:182:34] wire _hitsVec_ignore_T = 1'h0; // @[TLB.scala:182:28] wire hitsVec_ignore = 1'h0; // @[TLB.scala:182:34] wire _hitsVec_ignore_T_3 = 1'h0; // @[TLB.scala:182:28] wire hitsVec_ignore_3 = 1'h0; // @[TLB.scala:182:34] wire refill_v = 1'h0; // @[TLB.scala:448:33] wire newEntry_ae_stage2 = 1'h0; // @[TLB.scala:449:24] wire newEntry_fragmented_superpage = 1'h0; // @[TLB.scala:449:24] wire _newEntry_ae_stage2_T_1 = 1'h0; // @[TLB.scala:456:84] wire _waddr_T = 1'h0; // @[TLB.scala:477:45] wire _mxr_T = 1'h0; // @[TLB.scala:518:36] wire cmd_readx = 1'h0; // @[TLB.scala:575:37] wire _gf_ld_array_T = 1'h0; // @[TLB.scala:600:32] wire _gf_st_array_T = 1'h0; // @[TLB.scala:601:32] wire _multipleHits_T_5 = 1'h0; // @[Misc.scala:183:37] wire _multipleHits_T_14 = 1'h0; // @[Misc.scala:183:37] wire _io_req_ready_T; // @[TLB.scala:631:25] wire _io_resp_gf_ld_T = 1'h0; // @[TLB.scala:637:29] wire _io_resp_gf_ld_T_2 = 1'h0; // @[TLB.scala:637:66] wire _io_resp_gf_ld_T_3 = 1'h0; // @[TLB.scala:637:42] wire _io_resp_gf_st_T = 1'h0; // @[TLB.scala:638:29] wire _io_resp_gf_st_T_2 = 1'h0; // @[TLB.scala:638:73] wire _io_resp_gf_st_T_3 = 1'h0; // @[TLB.scala:638:49] wire _io_resp_gf_inst_T_1 = 1'h0; // @[TLB.scala:639:56] wire _io_resp_gf_inst_T_2 = 1'h0; // @[TLB.scala:639:30] wire _io_resp_gpa_is_pte_T = 1'h0; // @[TLB.scala:655:36] wire _r_superpage_repl_addr_T_3 = 1'h0; // @[TLB.scala:757:8] wire hv = 1'h0; // @[TLB.scala:721:36] wire hg = 1'h0; // @[TLB.scala:722:36] wire hv_1 = 1'h0; // @[TLB.scala:721:36] wire hg_1 = 1'h0; // @[TLB.scala:722:36] wire hv_2 = 1'h0; // @[TLB.scala:721:36] wire hg_2 = 1'h0; // @[TLB.scala:722:36] wire hv_3 = 1'h0; // @[TLB.scala:721:36] wire hg_3 = 1'h0; // @[TLB.scala:722:36] wire hv_4 = 1'h0; // @[TLB.scala:721:36] wire hg_4 = 1'h0; // @[TLB.scala:722:36] wire hv_5 = 1'h0; // @[TLB.scala:721:36] wire hg_5 = 1'h0; // @[TLB.scala:722:36] wire hv_6 = 1'h0; // @[TLB.scala:721:36] wire hg_6 = 1'h0; // @[TLB.scala:722:36] wire hv_7 = 1'h0; // @[TLB.scala:721:36] wire hg_7 = 1'h0; // @[TLB.scala:722:36] wire hv_8 = 1'h0; // @[TLB.scala:721:36] wire hg_8 = 1'h0; // @[TLB.scala:722:36] wire hv_9 = 1'h0; // @[TLB.scala:721:36] wire hg_9 = 1'h0; // @[TLB.scala:722:36] wire hv_10 = 1'h0; // @[TLB.scala:721:36] wire hg_10 = 1'h0; // @[TLB.scala:722:36] wire hv_11 = 1'h0; // @[TLB.scala:721:36] wire hg_11 = 1'h0; // @[TLB.scala:722:36] wire hv_12 = 1'h0; // @[TLB.scala:721:36] wire hg_12 = 1'h0; // @[TLB.scala:722:36] wire hv_13 = 1'h0; // @[TLB.scala:721:36] wire hg_13 = 1'h0; // @[TLB.scala:722:36] wire hv_14 = 1'h0; // @[TLB.scala:721:36] wire hg_14 = 1'h0; // @[TLB.scala:722:36] wire hv_15 = 1'h0; // @[TLB.scala:721:36] wire hg_15 = 1'h0; // @[TLB.scala:722:36] wire hv_16 = 1'h0; // @[TLB.scala:721:36] wire hg_16 = 1'h0; // @[TLB.scala:722:36] wire _ignore_T = 1'h0; // @[TLB.scala:182:28] wire ignore = 1'h0; // @[TLB.scala:182:34] wire hv_17 = 1'h0; // @[TLB.scala:721:36] wire hg_17 = 1'h0; // @[TLB.scala:722:36] wire _ignore_T_3 = 1'h0; // @[TLB.scala:182:28] wire ignore_3 = 1'h0; // @[TLB.scala:182:34] wire [1:0] io_resp_size = io_req_bits_size_0; // @[TLB.scala:318:7] wire [4:0] io_resp_cmd = io_req_bits_cmd_0; // @[TLB.scala:318:7] wire _io_resp_miss_T_2; // @[TLB.scala:651:64] wire [31:0] _io_resp_paddr_T_1; // @[TLB.scala:652:23] wire [39:0] _io_resp_gpa_T; // @[TLB.scala:659:8] wire _io_resp_pf_ld_T_3; // @[TLB.scala:633:41] wire _io_resp_pf_st_T_3; // @[TLB.scala:634:48] wire _io_resp_pf_inst_T_2; // @[TLB.scala:635:29] wire _io_resp_ae_ld_T_1; // @[TLB.scala:641:41] wire _io_resp_ae_st_T_1; // @[TLB.scala:642:41] wire _io_resp_ae_inst_T_2; // @[TLB.scala:643:41] wire _io_resp_ma_ld_T; // @[TLB.scala:645:31] wire _io_resp_ma_st_T; // @[TLB.scala:646:31] wire _io_resp_cacheable_T_1; // @[TLB.scala:648:41] wire _io_resp_must_alloc_T_1; // @[TLB.scala:649:51] wire _io_resp_prefetchable_T_2; // @[TLB.scala:650:59] wire _io_ptw_req_valid_T; // @[TLB.scala:662:29] wire do_refill = io_ptw_resp_valid_0; // @[TLB.scala:318:7, :408:29] wire newEntry_ae_ptw = io_ptw_resp_bits_ae_ptw_0; // @[TLB.scala:318:7, :449:24] wire newEntry_ae_final = io_ptw_resp_bits_ae_final_0; // @[TLB.scala:318:7, :449:24] wire newEntry_pf = io_ptw_resp_bits_pf_0; // @[TLB.scala:318:7, :449:24] wire newEntry_gf = io_ptw_resp_bits_gf_0; // @[TLB.scala:318:7, :449:24] wire newEntry_hr = io_ptw_resp_bits_hr_0; // @[TLB.scala:318:7, :449:24] wire newEntry_hw = io_ptw_resp_bits_hw_0; // @[TLB.scala:318:7, :449:24] wire newEntry_hx = io_ptw_resp_bits_hx_0; // @[TLB.scala:318:7, :449:24] wire newEntry_u = io_ptw_resp_bits_pte_u_0; // @[TLB.scala:318:7, :449:24] wire [1:0] _special_entry_level_T = io_ptw_resp_bits_level_0; // @[package.scala:163:13] wire [3:0] satp_mode = io_ptw_ptbr_mode_0; // @[TLB.scala:318:7, :373:17] wire [43:0] satp_ppn = io_ptw_ptbr_ppn_0; // @[TLB.scala:318:7, :373:17] wire mxr = io_ptw_status_mxr_0; // @[TLB.scala:318:7, :518:31] wire sum = io_ptw_status_sum_0; // @[TLB.scala:318:7, :510:16] wire io_req_ready_0; // @[TLB.scala:318:7] wire io_resp_pf_ld; // @[TLB.scala:318:7] wire io_resp_pf_st; // @[TLB.scala:318:7] wire io_resp_pf_inst; // @[TLB.scala:318:7] wire io_resp_ae_ld; // @[TLB.scala:318:7] wire io_resp_ae_st; // @[TLB.scala:318:7] wire io_resp_ae_inst; // @[TLB.scala:318:7] wire io_resp_ma_ld; // @[TLB.scala:318:7] wire io_resp_ma_st; // @[TLB.scala:318:7] wire io_resp_miss_0; // @[TLB.scala:318:7] wire [31:0] io_resp_paddr_0; // @[TLB.scala:318:7] wire [39:0] io_resp_gpa; // @[TLB.scala:318:7] wire io_resp_cacheable; // @[TLB.scala:318:7] wire io_resp_must_alloc; // @[TLB.scala:318:7] wire io_resp_prefetchable; // @[TLB.scala:318:7] wire [26:0] io_ptw_req_bits_bits_addr_0; // @[TLB.scala:318:7] wire io_ptw_req_bits_bits_need_gpa_0; // @[TLB.scala:318:7] wire io_ptw_req_valid_0; // @[TLB.scala:318:7] wire [26:0] vpn = io_req_bits_vaddr_0[38:12]; // @[TLB.scala:318:7, :335:30] wire [26:0] _ppn_T_5 = vpn; // @[TLB.scala:198:28, :335:30] wire [1:0] memIdx = vpn[1:0]; // @[package.scala:163:13] reg [1:0] sectored_entries_0_0_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_0_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_0_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_0_data_0; // @[TLB.scala:339:29] reg sectored_entries_0_0_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_1_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_1_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_1_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_1_data_0; // @[TLB.scala:339:29] reg sectored_entries_0_1_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_2_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_2_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_2_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_2_data_0; // @[TLB.scala:339:29] reg sectored_entries_0_2_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_3_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_3_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_3_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_3_data_0; // @[TLB.scala:339:29] reg sectored_entries_0_3_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_1_0_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_1_0_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_1_0_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_1_0_data_0; // @[TLB.scala:339:29] reg sectored_entries_1_0_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_1_1_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_1_1_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_1_1_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_1_1_data_0; // @[TLB.scala:339:29] reg sectored_entries_1_1_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_1_2_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_1_2_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_1_2_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_1_2_data_0; // @[TLB.scala:339:29] reg sectored_entries_1_2_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_1_3_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_1_3_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_1_3_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_1_3_data_0; // @[TLB.scala:339:29] reg sectored_entries_1_3_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_2_0_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_2_0_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_2_0_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_2_0_data_0; // @[TLB.scala:339:29] reg sectored_entries_2_0_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_2_1_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_2_1_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_2_1_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_2_1_data_0; // @[TLB.scala:339:29] reg sectored_entries_2_1_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_2_2_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_2_2_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_2_2_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_2_2_data_0; // @[TLB.scala:339:29] reg sectored_entries_2_2_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_2_3_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_2_3_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_2_3_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_2_3_data_0; // @[TLB.scala:339:29] reg sectored_entries_2_3_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_3_0_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_3_0_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_3_0_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_3_0_data_0; // @[TLB.scala:339:29] reg sectored_entries_3_0_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_3_1_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_3_1_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_3_1_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_3_1_data_0; // @[TLB.scala:339:29] reg sectored_entries_3_1_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_3_2_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_3_2_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_3_2_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_3_2_data_0; // @[TLB.scala:339:29] reg sectored_entries_3_2_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_3_3_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_3_3_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_3_3_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_3_3_data_0; // @[TLB.scala:339:29] reg sectored_entries_3_3_valid_0; // @[TLB.scala:339:29] reg [1:0] superpage_entries_0_level; // @[TLB.scala:341:30] reg [26:0] superpage_entries_0_tag_vpn; // @[TLB.scala:341:30] reg superpage_entries_0_tag_v; // @[TLB.scala:341:30] reg [41:0] superpage_entries_0_data_0; // @[TLB.scala:341:30] wire [41:0] _entries_WIRE_9 = superpage_entries_0_data_0; // @[TLB.scala:170:77, :341:30] reg superpage_entries_0_valid_0; // @[TLB.scala:341:30] wire _r_superpage_repl_addr_T = superpage_entries_0_valid_0; // @[TLB.scala:341:30, :757:16] reg [1:0] special_entry_level; // @[TLB.scala:346:56] reg [26:0] special_entry_tag_vpn; // @[TLB.scala:346:56] reg special_entry_tag_v; // @[TLB.scala:346:56] reg [41:0] special_entry_data_0; // @[TLB.scala:346:56] wire [41:0] _mpu_ppn_WIRE_1 = special_entry_data_0; // @[TLB.scala:170:77, :346:56] wire [41:0] _entries_WIRE_11 = special_entry_data_0; // @[TLB.scala:170:77, :346:56] reg special_entry_valid_0; // @[TLB.scala:346:56] reg [1:0] state; // @[TLB.scala:352:22] reg [26:0] r_refill_tag; // @[TLB.scala:354:25] assign io_ptw_req_bits_bits_addr_0 = r_refill_tag; // @[TLB.scala:318:7, :354:25] reg [1:0] r_sectored_repl_addr; // @[TLB.scala:356:33] reg r_sectored_hit_valid; // @[TLB.scala:357:27] reg [1:0] r_sectored_hit_bits; // @[TLB.scala:357:27] reg r_superpage_hit_valid; // @[TLB.scala:358:28] reg r_need_gpa; // @[TLB.scala:361:23] assign io_ptw_req_bits_bits_need_gpa_0 = r_need_gpa; // @[TLB.scala:318:7, :361:23] reg r_gpa_valid; // @[TLB.scala:362:24] reg [38:0] r_gpa; // @[TLB.scala:363:18] reg [26:0] r_gpa_vpn; // @[TLB.scala:364:22] reg r_gpa_is_pte; // @[TLB.scala:365:25] wire _stage1_en_T = satp_mode[3]; // @[TLB.scala:373:17, :374:41] wire stage1_en = _stage1_en_T; // @[TLB.scala:374:{29,41}] wire _vm_enabled_T = stage1_en; // @[TLB.scala:374:29, :399:31] wire _vm_enabled_T_1 = _vm_enabled_T; // @[TLB.scala:399:{31,45}] wire vm_enabled = _vm_enabled_T_1; // @[TLB.scala:399:{45,61}] wire _mpu_ppn_T = vm_enabled; // @[TLB.scala:399:61, :413:32] wire _tlb_miss_T_1 = vm_enabled; // @[TLB.scala:399:61, :613:29] wire [19:0] refill_ppn = io_ptw_resp_bits_pte_ppn_0[19:0]; // @[TLB.scala:318:7, :406:44] wire [19:0] newEntry_ppn = io_ptw_resp_bits_pte_ppn_0[19:0]; // @[TLB.scala:318:7, :406:44, :449:24] wire _mpu_priv_T = do_refill; // @[TLB.scala:408:29, :415:52] wire _io_resp_miss_T = do_refill; // @[TLB.scala:408:29, :651:29] wire _T_25 = state == 2'h1; // @[package.scala:16:47] wire _invalidate_refill_T; // @[package.scala:16:47] assign _invalidate_refill_T = _T_25; // @[package.scala:16:47] assign _io_ptw_req_valid_T = _T_25; // @[package.scala:16:47] wire _invalidate_refill_T_1 = &state; // @[package.scala:16:47] wire _invalidate_refill_T_2 = _invalidate_refill_T | _invalidate_refill_T_1; // @[package.scala:16:47, :81:59] wire invalidate_refill = _invalidate_refill_T_2 | io_sfence_valid_0; // @[package.scala:81:59] wire [19:0] _mpu_ppn_T_23; // @[TLB.scala:170:77] wire _mpu_ppn_T_22; // @[TLB.scala:170:77] wire _mpu_ppn_T_21; // @[TLB.scala:170:77] wire _mpu_ppn_T_20; // @[TLB.scala:170:77] wire _mpu_ppn_T_19; // @[TLB.scala:170:77] wire _mpu_ppn_T_18; // @[TLB.scala:170:77] wire _mpu_ppn_T_17; // @[TLB.scala:170:77] wire _mpu_ppn_T_16; // @[TLB.scala:170:77] wire _mpu_ppn_T_15; // @[TLB.scala:170:77] wire _mpu_ppn_T_14; // @[TLB.scala:170:77] wire _mpu_ppn_T_13; // @[TLB.scala:170:77] wire _mpu_ppn_T_12; // @[TLB.scala:170:77] wire _mpu_ppn_T_11; // @[TLB.scala:170:77] wire _mpu_ppn_T_10; // @[TLB.scala:170:77] wire _mpu_ppn_T_9; // @[TLB.scala:170:77] wire _mpu_ppn_T_8; // @[TLB.scala:170:77] wire _mpu_ppn_T_7; // @[TLB.scala:170:77] wire _mpu_ppn_T_6; // @[TLB.scala:170:77] wire _mpu_ppn_T_5; // @[TLB.scala:170:77] wire _mpu_ppn_T_4; // @[TLB.scala:170:77] wire _mpu_ppn_T_3; // @[TLB.scala:170:77] wire _mpu_ppn_T_2; // @[TLB.scala:170:77] wire _mpu_ppn_T_1; // @[TLB.scala:170:77] assign _mpu_ppn_T_1 = _mpu_ppn_WIRE_1[0]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_fragmented_superpage = _mpu_ppn_T_1; // @[TLB.scala:170:77] assign _mpu_ppn_T_2 = _mpu_ppn_WIRE_1[1]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_c = _mpu_ppn_T_2; // @[TLB.scala:170:77] assign _mpu_ppn_T_3 = _mpu_ppn_WIRE_1[2]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_eff = _mpu_ppn_T_3; // @[TLB.scala:170:77] assign _mpu_ppn_T_4 = _mpu_ppn_WIRE_1[3]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_paa = _mpu_ppn_T_4; // @[TLB.scala:170:77] assign _mpu_ppn_T_5 = _mpu_ppn_WIRE_1[4]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_pal = _mpu_ppn_T_5; // @[TLB.scala:170:77] assign _mpu_ppn_T_6 = _mpu_ppn_WIRE_1[5]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_ppp = _mpu_ppn_T_6; // @[TLB.scala:170:77] assign _mpu_ppn_T_7 = _mpu_ppn_WIRE_1[6]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_pr = _mpu_ppn_T_7; // @[TLB.scala:170:77] assign _mpu_ppn_T_8 = _mpu_ppn_WIRE_1[7]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_px = _mpu_ppn_T_8; // @[TLB.scala:170:77] assign _mpu_ppn_T_9 = _mpu_ppn_WIRE_1[8]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_pw = _mpu_ppn_T_9; // @[TLB.scala:170:77] assign _mpu_ppn_T_10 = _mpu_ppn_WIRE_1[9]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_hr = _mpu_ppn_T_10; // @[TLB.scala:170:77] assign _mpu_ppn_T_11 = _mpu_ppn_WIRE_1[10]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_hx = _mpu_ppn_T_11; // @[TLB.scala:170:77] assign _mpu_ppn_T_12 = _mpu_ppn_WIRE_1[11]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_hw = _mpu_ppn_T_12; // @[TLB.scala:170:77] assign _mpu_ppn_T_13 = _mpu_ppn_WIRE_1[12]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_sr = _mpu_ppn_T_13; // @[TLB.scala:170:77] assign _mpu_ppn_T_14 = _mpu_ppn_WIRE_1[13]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_sx = _mpu_ppn_T_14; // @[TLB.scala:170:77] assign _mpu_ppn_T_15 = _mpu_ppn_WIRE_1[14]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_sw = _mpu_ppn_T_15; // @[TLB.scala:170:77] assign _mpu_ppn_T_16 = _mpu_ppn_WIRE_1[15]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_gf = _mpu_ppn_T_16; // @[TLB.scala:170:77] assign _mpu_ppn_T_17 = _mpu_ppn_WIRE_1[16]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_pf = _mpu_ppn_T_17; // @[TLB.scala:170:77] assign _mpu_ppn_T_18 = _mpu_ppn_WIRE_1[17]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_ae_stage2 = _mpu_ppn_T_18; // @[TLB.scala:170:77] assign _mpu_ppn_T_19 = _mpu_ppn_WIRE_1[18]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_ae_final = _mpu_ppn_T_19; // @[TLB.scala:170:77] assign _mpu_ppn_T_20 = _mpu_ppn_WIRE_1[19]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_ae_ptw = _mpu_ppn_T_20; // @[TLB.scala:170:77] assign _mpu_ppn_T_21 = _mpu_ppn_WIRE_1[20]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_g = _mpu_ppn_T_21; // @[TLB.scala:170:77] assign _mpu_ppn_T_22 = _mpu_ppn_WIRE_1[21]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_u = _mpu_ppn_T_22; // @[TLB.scala:170:77] assign _mpu_ppn_T_23 = _mpu_ppn_WIRE_1[41:22]; // @[TLB.scala:170:77] wire [19:0] _mpu_ppn_WIRE_ppn = _mpu_ppn_T_23; // @[TLB.scala:170:77] wire [1:0] mpu_ppn_res = _mpu_ppn_barrier_io_y_ppn[19:18]; // @[package.scala:267:25] wire _GEN = special_entry_level == 2'h0; // @[TLB.scala:197:28, :346:56] wire _mpu_ppn_ignore_T; // @[TLB.scala:197:28] assign _mpu_ppn_ignore_T = _GEN; // @[TLB.scala:197:28] wire _hitsVec_ignore_T_4; // @[TLB.scala:182:28] assign _hitsVec_ignore_T_4 = _GEN; // @[TLB.scala:182:28, :197:28] wire _ppn_ignore_T_2; // @[TLB.scala:197:28] assign _ppn_ignore_T_2 = _GEN; // @[TLB.scala:197:28] wire _ignore_T_4; // @[TLB.scala:182:28] assign _ignore_T_4 = _GEN; // @[TLB.scala:182:28, :197:28] wire mpu_ppn_ignore = _mpu_ppn_ignore_T; // @[TLB.scala:197:{28,34}] wire [26:0] _mpu_ppn_T_24 = mpu_ppn_ignore ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _mpu_ppn_T_25 = {_mpu_ppn_T_24[26:20], _mpu_ppn_T_24[19:0] | _mpu_ppn_barrier_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _mpu_ppn_T_26 = _mpu_ppn_T_25[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _mpu_ppn_T_27 = {mpu_ppn_res, _mpu_ppn_T_26}; // @[TLB.scala:195:26, :198:{18,58}] wire _mpu_ppn_ignore_T_1 = ~(special_entry_level[1]); // @[TLB.scala:197:28, :346:56] wire mpu_ppn_ignore_1 = _mpu_ppn_ignore_T_1; // @[TLB.scala:197:{28,34}] wire [26:0] _mpu_ppn_T_28 = mpu_ppn_ignore_1 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _mpu_ppn_T_29 = {_mpu_ppn_T_28[26:20], _mpu_ppn_T_28[19:0] | _mpu_ppn_barrier_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _mpu_ppn_T_30 = _mpu_ppn_T_29[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _mpu_ppn_T_31 = {_mpu_ppn_T_27, _mpu_ppn_T_30}; // @[TLB.scala:198:{18,58}] wire [27:0] _mpu_ppn_T_32 = io_req_bits_vaddr_0[39:12]; // @[TLB.scala:318:7, :413:146] wire [27:0] _mpu_ppn_T_33 = _mpu_ppn_T ? {8'h0, _mpu_ppn_T_31} : _mpu_ppn_T_32; // @[TLB.scala:198:18, :413:{20,32,146}] wire [27:0] mpu_ppn = do_refill ? {8'h0, refill_ppn} : _mpu_ppn_T_33; // @[TLB.scala:406:44, :408:29, :412:20, :413:20] wire [11:0] _mpu_physaddr_T = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52] wire [11:0] _io_resp_paddr_T = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52, :652:46] wire [11:0] _io_resp_gpa_offset_T_1 = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52, :658:82] wire [39:0] mpu_physaddr = {mpu_ppn, _mpu_physaddr_T}; // @[TLB.scala:412:20, :414:{25,52}] wire [39:0] _homogeneous_T = mpu_physaddr; // @[TLB.scala:414:25] wire [39:0] _homogeneous_T_67 = mpu_physaddr; // @[TLB.scala:414:25] wire [39:0] _deny_access_to_debug_T_1 = mpu_physaddr; // @[TLB.scala:414:25] wire _mpu_priv_T_1 = _mpu_priv_T; // @[TLB.scala:415:{38,52}] wire [2:0] _mpu_priv_T_2 = {io_ptw_status_debug_0, 2'h0}; // @[TLB.scala:318:7, :415:103] wire [2:0] mpu_priv = _mpu_priv_T_1 ? 3'h1 : _mpu_priv_T_2; // @[TLB.scala:415:{27,38,103}] wire cacheable; // @[TLB.scala:425:41] wire newEntry_c = cacheable; // @[TLB.scala:425:41, :449:24] wire [40:0] _homogeneous_T_1 = {1'h0, _homogeneous_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_2 = _homogeneous_T_1 & 41'h1FFFFFFE000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_3 = _homogeneous_T_2; // @[Parameters.scala:137:46] wire _homogeneous_T_4 = _homogeneous_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_50 = _homogeneous_T_4; // @[TLBPermissions.scala:101:65] wire [39:0] _GEN_0 = {mpu_physaddr[39:14], mpu_physaddr[13:0] ^ 14'h3000}; // @[TLB.scala:414:25] wire [39:0] _homogeneous_T_5; // @[Parameters.scala:137:31] assign _homogeneous_T_5 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_72; // @[Parameters.scala:137:31] assign _homogeneous_T_72 = _GEN_0; // @[Parameters.scala:137:31] wire [40:0] _homogeneous_T_6 = {1'h0, _homogeneous_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_7 = _homogeneous_T_6 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_8 = _homogeneous_T_7; // @[Parameters.scala:137:46] wire _homogeneous_T_9 = _homogeneous_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_1 = {mpu_physaddr[39:17], mpu_physaddr[16:0] ^ 17'h10000}; // @[TLB.scala:414:25] wire [39:0] _homogeneous_T_10; // @[Parameters.scala:137:31] assign _homogeneous_T_10 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_60; // @[Parameters.scala:137:31] assign _homogeneous_T_60 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_77; // @[Parameters.scala:137:31] assign _homogeneous_T_77 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_109; // @[Parameters.scala:137:31] assign _homogeneous_T_109 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_116; // @[Parameters.scala:137:31] assign _homogeneous_T_116 = _GEN_1; // @[Parameters.scala:137:31] wire [40:0] _homogeneous_T_11 = {1'h0, _homogeneous_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_12 = _homogeneous_T_11 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_13 = _homogeneous_T_12; // @[Parameters.scala:137:46] wire _homogeneous_T_14 = _homogeneous_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_15 = {mpu_physaddr[39:21], mpu_physaddr[20:0] ^ 21'h100000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_16 = {1'h0, _homogeneous_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_17 = _homogeneous_T_16 & 41'h1FFFFFEF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_18 = _homogeneous_T_17; // @[Parameters.scala:137:46] wire _homogeneous_T_19 = _homogeneous_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_20 = {mpu_physaddr[39:26], mpu_physaddr[25:0] ^ 26'h2000000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_21 = {1'h0, _homogeneous_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_22 = _homogeneous_T_21 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_23 = _homogeneous_T_22; // @[Parameters.scala:137:46] wire _homogeneous_T_24 = _homogeneous_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_25 = {mpu_physaddr[39:26], mpu_physaddr[25:0] ^ 26'h2010000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_26 = {1'h0, _homogeneous_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_27 = _homogeneous_T_26 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_28 = _homogeneous_T_27; // @[Parameters.scala:137:46] wire _homogeneous_T_29 = _homogeneous_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_2 = {mpu_physaddr[39:28], mpu_physaddr[27:0] ^ 28'h8000000}; // @[TLB.scala:414:25] wire [39:0] _homogeneous_T_30; // @[Parameters.scala:137:31] assign _homogeneous_T_30 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_82; // @[Parameters.scala:137:31] assign _homogeneous_T_82 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_97; // @[Parameters.scala:137:31] assign _homogeneous_T_97 = _GEN_2; // @[Parameters.scala:137:31] wire [40:0] _homogeneous_T_31 = {1'h0, _homogeneous_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_32 = _homogeneous_T_31 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_33 = _homogeneous_T_32; // @[Parameters.scala:137:46] wire _homogeneous_T_34 = _homogeneous_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_35 = {mpu_physaddr[39:28], mpu_physaddr[27:0] ^ 28'hC000000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_36 = {1'h0, _homogeneous_T_35}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_37 = _homogeneous_T_36 & 41'h1FFFC000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_38 = _homogeneous_T_37; // @[Parameters.scala:137:46] wire _homogeneous_T_39 = _homogeneous_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_40 = {mpu_physaddr[39:29], mpu_physaddr[28:0] ^ 29'h10020000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_41 = {1'h0, _homogeneous_T_40}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_42 = _homogeneous_T_41 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_43 = _homogeneous_T_42; // @[Parameters.scala:137:46] wire _homogeneous_T_44 = _homogeneous_T_43 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_3 = {mpu_physaddr[39:32], mpu_physaddr[31:0] ^ 32'h80000000}; // @[TLB.scala:414:25, :417:15] wire [39:0] _homogeneous_T_45; // @[Parameters.scala:137:31] assign _homogeneous_T_45 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_87; // @[Parameters.scala:137:31] assign _homogeneous_T_87 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_102; // @[Parameters.scala:137:31] assign _homogeneous_T_102 = _GEN_3; // @[Parameters.scala:137:31] wire [40:0] _homogeneous_T_46 = {1'h0, _homogeneous_T_45}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_47 = _homogeneous_T_46 & 41'h1FFF0000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_48 = _homogeneous_T_47; // @[Parameters.scala:137:46] wire _homogeneous_T_49 = _homogeneous_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_51 = _homogeneous_T_50 | _homogeneous_T_9; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_52 = _homogeneous_T_51 | _homogeneous_T_14; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_53 = _homogeneous_T_52 | _homogeneous_T_19; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_54 = _homogeneous_T_53 | _homogeneous_T_24; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_55 = _homogeneous_T_54 | _homogeneous_T_29; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_56 = _homogeneous_T_55 | _homogeneous_T_34; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_57 = _homogeneous_T_56 | _homogeneous_T_39; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_58 = _homogeneous_T_57 | _homogeneous_T_44; // @[TLBPermissions.scala:101:65] wire homogeneous = _homogeneous_T_58 | _homogeneous_T_49; // @[TLBPermissions.scala:101:65] wire [40:0] _homogeneous_T_61 = {1'h0, _homogeneous_T_60}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_62 = _homogeneous_T_61 & 41'h8A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_63 = _homogeneous_T_62; // @[Parameters.scala:137:46] wire _homogeneous_T_64 = _homogeneous_T_63 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_65 = _homogeneous_T_64; // @[TLBPermissions.scala:87:66] wire _homogeneous_T_66 = ~_homogeneous_T_65; // @[TLBPermissions.scala:87:{22,66}] wire [40:0] _homogeneous_T_68 = {1'h0, _homogeneous_T_67}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_69 = _homogeneous_T_68 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_70 = _homogeneous_T_69; // @[Parameters.scala:137:46] wire _homogeneous_T_71 = _homogeneous_T_70 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_92 = _homogeneous_T_71; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_73 = {1'h0, _homogeneous_T_72}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_74 = _homogeneous_T_73 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_75 = _homogeneous_T_74; // @[Parameters.scala:137:46] wire _homogeneous_T_76 = _homogeneous_T_75 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_78 = {1'h0, _homogeneous_T_77}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_79 = _homogeneous_T_78 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_80 = _homogeneous_T_79; // @[Parameters.scala:137:46] wire _homogeneous_T_81 = _homogeneous_T_80 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_83 = {1'h0, _homogeneous_T_82}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_84 = _homogeneous_T_83 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_85 = _homogeneous_T_84; // @[Parameters.scala:137:46] wire _homogeneous_T_86 = _homogeneous_T_85 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_88 = {1'h0, _homogeneous_T_87}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_89 = _homogeneous_T_88 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_90 = _homogeneous_T_89; // @[Parameters.scala:137:46] wire _homogeneous_T_91 = _homogeneous_T_90 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_93 = _homogeneous_T_92 | _homogeneous_T_76; // @[TLBPermissions.scala:85:66] wire _homogeneous_T_94 = _homogeneous_T_93 | _homogeneous_T_81; // @[TLBPermissions.scala:85:66] wire _homogeneous_T_95 = _homogeneous_T_94 | _homogeneous_T_86; // @[TLBPermissions.scala:85:66] wire _homogeneous_T_96 = _homogeneous_T_95 | _homogeneous_T_91; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_98 = {1'h0, _homogeneous_T_97}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_99 = _homogeneous_T_98 & 41'h8E000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_100 = _homogeneous_T_99; // @[Parameters.scala:137:46] wire _homogeneous_T_101 = _homogeneous_T_100 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_107 = _homogeneous_T_101; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_103 = {1'h0, _homogeneous_T_102}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_104 = _homogeneous_T_103 & 41'h80000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_105 = _homogeneous_T_104; // @[Parameters.scala:137:46] wire _homogeneous_T_106 = _homogeneous_T_105 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_108 = _homogeneous_T_107 | _homogeneous_T_106; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_110 = {1'h0, _homogeneous_T_109}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_111 = _homogeneous_T_110 & 41'h8A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_112 = _homogeneous_T_111; // @[Parameters.scala:137:46] wire _homogeneous_T_113 = _homogeneous_T_112 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_114 = _homogeneous_T_113; // @[TLBPermissions.scala:87:66] wire _homogeneous_T_115 = ~_homogeneous_T_114; // @[TLBPermissions.scala:87:{22,66}] wire [40:0] _homogeneous_T_117 = {1'h0, _homogeneous_T_116}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_118 = _homogeneous_T_117 & 41'h8A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_119 = _homogeneous_T_118; // @[Parameters.scala:137:46] wire _homogeneous_T_120 = _homogeneous_T_119 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_121 = _homogeneous_T_120; // @[TLBPermissions.scala:87:66] wire _homogeneous_T_122 = ~_homogeneous_T_121; // @[TLBPermissions.scala:87:{22,66}] wire _deny_access_to_debug_T = ~(mpu_priv[2]); // @[TLB.scala:415:27, :428:39] wire [40:0] _deny_access_to_debug_T_2 = {1'h0, _deny_access_to_debug_T_1}; // @[Parameters.scala:137:{31,41}] wire [40:0] _deny_access_to_debug_T_3 = _deny_access_to_debug_T_2 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _deny_access_to_debug_T_4 = _deny_access_to_debug_T_3; // @[Parameters.scala:137:46] wire _deny_access_to_debug_T_5 = _deny_access_to_debug_T_4 == 41'h0; // @[Parameters.scala:137:{46,59}] wire deny_access_to_debug = _deny_access_to_debug_T & _deny_access_to_debug_T_5; // @[TLB.scala:428:{39,50}] wire _prot_r_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33] wire _prot_r_T_1 = _pma_io_resp_r & _prot_r_T; // @[TLB.scala:422:19, :429:{30,33}] wire prot_r = _prot_r_T_1 & _pmp_io_r; // @[TLB.scala:416:19, :429:{30,55}] wire newEntry_pr = prot_r; // @[TLB.scala:429:55, :449:24] wire _prot_w_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33, :430:33] wire _prot_w_T_1 = _pma_io_resp_w & _prot_w_T; // @[TLB.scala:422:19, :430:{30,33}] wire prot_w = _prot_w_T_1 & _pmp_io_w; // @[TLB.scala:416:19, :430:{30,55}] wire newEntry_pw = prot_w; // @[TLB.scala:430:55, :449:24] wire _prot_x_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33, :434:33] wire _prot_x_T_1 = _pma_io_resp_x & _prot_x_T; // @[TLB.scala:422:19, :434:{30,33}] wire prot_x = _prot_x_T_1 & _pmp_io_x; // @[TLB.scala:416:19, :434:{30,55}] wire newEntry_px = prot_x; // @[TLB.scala:434:55, :449:24] wire [3:0][26:0] _GEN_4 = {{sectored_entries_3_0_tag_vpn}, {sectored_entries_2_0_tag_vpn}, {sectored_entries_1_0_tag_vpn}, {sectored_entries_0_0_tag_vpn}}; // @[TLB.scala:174:61, :339:29] wire [3:0] _GEN_5 = {{sectored_entries_3_0_tag_v}, {sectored_entries_2_0_tag_v}, {sectored_entries_1_0_tag_v}, {sectored_entries_0_0_tag_v}}; // @[TLB.scala:174:61, :339:29] wire [3:0][41:0] _GEN_6 = {{sectored_entries_3_0_data_0}, {sectored_entries_2_0_data_0}, {sectored_entries_1_0_data_0}, {sectored_entries_0_0_data_0}}; // @[TLB.scala:174:61, :339:29] wire [41:0] _entries_WIRE_1 = _GEN_6[memIdx]; // @[package.scala:163:13] wire [3:0] _GEN_7 = {{sectored_entries_3_0_valid_0}, {sectored_entries_2_0_valid_0}, {sectored_entries_1_0_valid_0}, {sectored_entries_0_0_valid_0}}; // @[TLB.scala:174:61, :339:29] wire [3:0][26:0] _GEN_8 = {{sectored_entries_3_1_tag_vpn}, {sectored_entries_2_1_tag_vpn}, {sectored_entries_1_1_tag_vpn}, {sectored_entries_0_1_tag_vpn}}; // @[TLB.scala:174:61, :339:29] wire [3:0] _GEN_9 = {{sectored_entries_3_1_tag_v}, {sectored_entries_2_1_tag_v}, {sectored_entries_1_1_tag_v}, {sectored_entries_0_1_tag_v}}; // @[TLB.scala:174:61, :339:29] wire [3:0][41:0] _GEN_10 = {{sectored_entries_3_1_data_0}, {sectored_entries_2_1_data_0}, {sectored_entries_1_1_data_0}, {sectored_entries_0_1_data_0}}; // @[TLB.scala:174:61, :339:29] wire [41:0] _entries_WIRE_3 = _GEN_10[memIdx]; // @[package.scala:163:13] wire [3:0] _GEN_11 = {{sectored_entries_3_1_valid_0}, {sectored_entries_2_1_valid_0}, {sectored_entries_1_1_valid_0}, {sectored_entries_0_1_valid_0}}; // @[TLB.scala:174:61, :339:29] wire [3:0][26:0] _GEN_12 = {{sectored_entries_3_2_tag_vpn}, {sectored_entries_2_2_tag_vpn}, {sectored_entries_1_2_tag_vpn}, {sectored_entries_0_2_tag_vpn}}; // @[TLB.scala:174:61, :339:29] wire [3:0] _GEN_13 = {{sectored_entries_3_2_tag_v}, {sectored_entries_2_2_tag_v}, {sectored_entries_1_2_tag_v}, {sectored_entries_0_2_tag_v}}; // @[TLB.scala:174:61, :339:29] wire [3:0][41:0] _GEN_14 = {{sectored_entries_3_2_data_0}, {sectored_entries_2_2_data_0}, {sectored_entries_1_2_data_0}, {sectored_entries_0_2_data_0}}; // @[TLB.scala:174:61, :339:29] wire [41:0] _entries_WIRE_5 = _GEN_14[memIdx]; // @[package.scala:163:13] wire [3:0] _GEN_15 = {{sectored_entries_3_2_valid_0}, {sectored_entries_2_2_valid_0}, {sectored_entries_1_2_valid_0}, {sectored_entries_0_2_valid_0}}; // @[TLB.scala:174:61, :339:29] wire [3:0][26:0] _GEN_16 = {{sectored_entries_3_3_tag_vpn}, {sectored_entries_2_3_tag_vpn}, {sectored_entries_1_3_tag_vpn}, {sectored_entries_0_3_tag_vpn}}; // @[TLB.scala:174:61, :339:29] wire [3:0] _GEN_17 = {{sectored_entries_3_3_tag_v}, {sectored_entries_2_3_tag_v}, {sectored_entries_1_3_tag_v}, {sectored_entries_0_3_tag_v}}; // @[TLB.scala:174:61, :339:29] wire [3:0][41:0] _GEN_18 = {{sectored_entries_3_3_data_0}, {sectored_entries_2_3_data_0}, {sectored_entries_1_3_data_0}, {sectored_entries_0_3_data_0}}; // @[TLB.scala:174:61, :339:29] wire [41:0] _entries_WIRE_7 = _GEN_18[memIdx]; // @[package.scala:163:13] wire [3:0] _GEN_19 = {{sectored_entries_3_3_valid_0}, {sectored_entries_2_3_valid_0}, {sectored_entries_1_3_valid_0}, {sectored_entries_0_3_valid_0}}; // @[TLB.scala:174:61, :339:29] wire [26:0] _GEN_20 = _GEN_4[memIdx] ^ vpn; // @[package.scala:163:13] wire [26:0] _sector_hits_T; // @[TLB.scala:174:61] assign _sector_hits_T = _GEN_20; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T; // @[TLB.scala:174:61] assign _hitsVec_T = _GEN_20; // @[TLB.scala:174:61] wire [26:0] _sector_hits_T_1 = _sector_hits_T; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_2 = _sector_hits_T_1 == 27'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_3 = ~_GEN_5[memIdx]; // @[package.scala:163:13] wire _sector_hits_T_4 = _sector_hits_T_2 & _sector_hits_T_3; // @[TLB.scala:174:{86,95,105}] wire sector_hits_0 = _GEN_7[memIdx] & _sector_hits_T_4; // @[package.scala:163:13] wire [26:0] _GEN_21 = _GEN_8[memIdx] ^ vpn; // @[package.scala:163:13] wire [26:0] _sector_hits_T_5; // @[TLB.scala:174:61] assign _sector_hits_T_5 = _GEN_21; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_6; // @[TLB.scala:174:61] assign _hitsVec_T_6 = _GEN_21; // @[TLB.scala:174:61] wire [26:0] _sector_hits_T_6 = _sector_hits_T_5; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_7 = _sector_hits_T_6 == 27'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_8 = ~_GEN_9[memIdx]; // @[package.scala:163:13] wire _sector_hits_T_9 = _sector_hits_T_7 & _sector_hits_T_8; // @[TLB.scala:174:{86,95,105}] wire sector_hits_1 = _GEN_11[memIdx] & _sector_hits_T_9; // @[package.scala:163:13] wire [26:0] _GEN_22 = _GEN_12[memIdx] ^ vpn; // @[package.scala:163:13] wire [26:0] _sector_hits_T_10; // @[TLB.scala:174:61] assign _sector_hits_T_10 = _GEN_22; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_12; // @[TLB.scala:174:61] assign _hitsVec_T_12 = _GEN_22; // @[TLB.scala:174:61] wire [26:0] _sector_hits_T_11 = _sector_hits_T_10; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_12 = _sector_hits_T_11 == 27'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_13 = ~_GEN_13[memIdx]; // @[package.scala:163:13] wire _sector_hits_T_14 = _sector_hits_T_12 & _sector_hits_T_13; // @[TLB.scala:174:{86,95,105}] wire sector_hits_2 = _GEN_15[memIdx] & _sector_hits_T_14; // @[package.scala:163:13] wire [26:0] _GEN_23 = _GEN_16[memIdx] ^ vpn; // @[package.scala:163:13] wire [26:0] _sector_hits_T_15; // @[TLB.scala:174:61] assign _sector_hits_T_15 = _GEN_23; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_18; // @[TLB.scala:174:61] assign _hitsVec_T_18 = _GEN_23; // @[TLB.scala:174:61] wire [26:0] _sector_hits_T_16 = _sector_hits_T_15; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_17 = _sector_hits_T_16 == 27'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_18 = ~_GEN_17[memIdx]; // @[package.scala:163:13] wire _sector_hits_T_19 = _sector_hits_T_17 & _sector_hits_T_18; // @[TLB.scala:174:{86,95,105}] wire sector_hits_3 = _GEN_19[memIdx] & _sector_hits_T_19; // @[package.scala:163:13] wire _superpage_hits_tagMatch_T = ~superpage_entries_0_tag_v; // @[TLB.scala:178:43, :341:30] wire superpage_hits_tagMatch = superpage_entries_0_valid_0 & _superpage_hits_tagMatch_T; // @[TLB.scala:178:{33,43}, :341:30] wire [26:0] _T_1876 = superpage_entries_0_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :341:30] wire [26:0] _superpage_hits_T; // @[TLB.scala:183:52] assign _superpage_hits_T = _T_1876; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_5; // @[TLB.scala:183:52] assign _superpage_hits_T_5 = _T_1876; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_10; // @[TLB.scala:183:52] assign _superpage_hits_T_10 = _T_1876; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_24; // @[TLB.scala:183:52] assign _hitsVec_T_24 = _T_1876; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_29; // @[TLB.scala:183:52] assign _hitsVec_T_29 = _T_1876; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_34; // @[TLB.scala:183:52] assign _hitsVec_T_34 = _T_1876; // @[TLB.scala:183:52] wire [8:0] _superpage_hits_T_1 = _superpage_hits_T[26:18]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_2 = _superpage_hits_T_1 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire _superpage_hits_T_3 = _superpage_hits_T_2; // @[TLB.scala:183:{40,79}] wire _superpage_hits_T_4 = superpage_hits_tagMatch & _superpage_hits_T_3; // @[TLB.scala:178:33, :183:{29,40}] wire _GEN_24 = superpage_entries_0_level == 2'h0; // @[TLB.scala:182:28, :341:30] wire _superpage_hits_ignore_T_1; // @[TLB.scala:182:28] assign _superpage_hits_ignore_T_1 = _GEN_24; // @[TLB.scala:182:28] wire _hitsVec_ignore_T_1; // @[TLB.scala:182:28] assign _hitsVec_ignore_T_1 = _GEN_24; // @[TLB.scala:182:28] wire _ppn_ignore_T; // @[TLB.scala:197:28] assign _ppn_ignore_T = _GEN_24; // @[TLB.scala:182:28, :197:28] wire _ignore_T_1; // @[TLB.scala:182:28] assign _ignore_T_1 = _GEN_24; // @[TLB.scala:182:28] wire superpage_hits_ignore_1 = _superpage_hits_ignore_T_1; // @[TLB.scala:182:{28,34}] wire [8:0] _superpage_hits_T_6 = _superpage_hits_T_5[17:9]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_7 = _superpage_hits_T_6 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire _superpage_hits_T_8 = superpage_hits_ignore_1 | _superpage_hits_T_7; // @[TLB.scala:182:34, :183:{40,79}] wire _superpage_hits_T_9 = _superpage_hits_T_4 & _superpage_hits_T_8; // @[TLB.scala:183:{29,40}] wire superpage_hits_0 = _superpage_hits_T_9; // @[TLB.scala:183:29] wire _superpage_hits_ignore_T_2 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _superpage_hits_T_11 = _superpage_hits_T_10[8:0]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_12 = _superpage_hits_T_11 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire [26:0] _hitsVec_T_1 = _hitsVec_T; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_2 = _hitsVec_T_1 == 27'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_3 = ~_GEN_5[memIdx]; // @[package.scala:163:13] wire _hitsVec_T_4 = _hitsVec_T_2 & _hitsVec_T_3; // @[TLB.scala:174:{86,95,105}] wire _hitsVec_T_5 = _GEN_7[memIdx] & _hitsVec_T_4; // @[package.scala:163:13] wire hitsVec_0 = vm_enabled & _hitsVec_T_5; // @[TLB.scala:188:18, :399:61, :440:44] wire [26:0] _hitsVec_T_7 = _hitsVec_T_6; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_8 = _hitsVec_T_7 == 27'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_9 = ~_GEN_9[memIdx]; // @[package.scala:163:13] wire _hitsVec_T_10 = _hitsVec_T_8 & _hitsVec_T_9; // @[TLB.scala:174:{86,95,105}] wire _hitsVec_T_11 = _GEN_11[memIdx] & _hitsVec_T_10; // @[package.scala:163:13] wire hitsVec_1 = vm_enabled & _hitsVec_T_11; // @[TLB.scala:188:18, :399:61, :440:44] wire [26:0] _hitsVec_T_13 = _hitsVec_T_12; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_14 = _hitsVec_T_13 == 27'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_15 = ~_GEN_13[memIdx]; // @[package.scala:163:13] wire _hitsVec_T_16 = _hitsVec_T_14 & _hitsVec_T_15; // @[TLB.scala:174:{86,95,105}] wire _hitsVec_T_17 = _GEN_15[memIdx] & _hitsVec_T_16; // @[package.scala:163:13] wire hitsVec_2 = vm_enabled & _hitsVec_T_17; // @[TLB.scala:188:18, :399:61, :440:44] wire [26:0] _hitsVec_T_19 = _hitsVec_T_18; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_20 = _hitsVec_T_19 == 27'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_21 = ~_GEN_17[memIdx]; // @[package.scala:163:13] wire _hitsVec_T_22 = _hitsVec_T_20 & _hitsVec_T_21; // @[TLB.scala:174:{86,95,105}] wire _hitsVec_T_23 = _GEN_19[memIdx] & _hitsVec_T_22; // @[package.scala:163:13] wire hitsVec_3 = vm_enabled & _hitsVec_T_23; // @[TLB.scala:188:18, :399:61, :440:44] wire _hitsVec_tagMatch_T = ~superpage_entries_0_tag_v; // @[TLB.scala:178:43, :341:30] wire hitsVec_tagMatch = superpage_entries_0_valid_0 & _hitsVec_tagMatch_T; // @[TLB.scala:178:{33,43}, :341:30] wire [8:0] _hitsVec_T_25 = _hitsVec_T_24[26:18]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_26 = _hitsVec_T_25 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire _hitsVec_T_27 = _hitsVec_T_26; // @[TLB.scala:183:{40,79}] wire _hitsVec_T_28 = hitsVec_tagMatch & _hitsVec_T_27; // @[TLB.scala:178:33, :183:{29,40}] wire hitsVec_ignore_1 = _hitsVec_ignore_T_1; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_30 = _hitsVec_T_29[17:9]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_31 = _hitsVec_T_30 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire _hitsVec_T_32 = hitsVec_ignore_1 | _hitsVec_T_31; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_33 = _hitsVec_T_28 & _hitsVec_T_32; // @[TLB.scala:183:{29,40}] wire _hitsVec_T_38 = _hitsVec_T_33; // @[TLB.scala:183:29] wire _hitsVec_ignore_T_2 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _hitsVec_T_35 = _hitsVec_T_34[8:0]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_36 = _hitsVec_T_35 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire hitsVec_4 = vm_enabled & _hitsVec_T_38; // @[TLB.scala:183:29, :399:61, :440:44] wire _hitsVec_tagMatch_T_1 = ~special_entry_tag_v; // @[TLB.scala:178:43, :346:56] wire hitsVec_tagMatch_1 = special_entry_valid_0 & _hitsVec_tagMatch_T_1; // @[TLB.scala:178:{33,43}, :346:56] wire [26:0] _T_1974 = special_entry_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :346:56] wire [26:0] _hitsVec_T_39; // @[TLB.scala:183:52] assign _hitsVec_T_39 = _T_1974; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_44; // @[TLB.scala:183:52] assign _hitsVec_T_44 = _T_1974; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_49; // @[TLB.scala:183:52] assign _hitsVec_T_49 = _T_1974; // @[TLB.scala:183:52] wire [8:0] _hitsVec_T_40 = _hitsVec_T_39[26:18]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_41 = _hitsVec_T_40 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire _hitsVec_T_42 = _hitsVec_T_41; // @[TLB.scala:183:{40,79}] wire _hitsVec_T_43 = hitsVec_tagMatch_1 & _hitsVec_T_42; // @[TLB.scala:178:33, :183:{29,40}] wire hitsVec_ignore_4 = _hitsVec_ignore_T_4; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_45 = _hitsVec_T_44[17:9]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_46 = _hitsVec_T_45 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire _hitsVec_T_47 = hitsVec_ignore_4 | _hitsVec_T_46; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_48 = _hitsVec_T_43 & _hitsVec_T_47; // @[TLB.scala:183:{29,40}] wire _hitsVec_ignore_T_5 = ~(special_entry_level[1]); // @[TLB.scala:182:28, :197:28, :346:56] wire hitsVec_ignore_5 = _hitsVec_ignore_T_5; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_50 = _hitsVec_T_49[8:0]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_51 = _hitsVec_T_50 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire _hitsVec_T_52 = hitsVec_ignore_5 | _hitsVec_T_51; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_53 = _hitsVec_T_48 & _hitsVec_T_52; // @[TLB.scala:183:{29,40}] wire hitsVec_5 = vm_enabled & _hitsVec_T_53; // @[TLB.scala:183:29, :399:61, :440:44] wire [1:0] real_hits_lo_hi = {hitsVec_2, hitsVec_1}; // @[package.scala:45:27] wire [2:0] real_hits_lo = {real_hits_lo_hi, hitsVec_0}; // @[package.scala:45:27] wire [1:0] real_hits_hi_hi = {hitsVec_5, hitsVec_4}; // @[package.scala:45:27] wire [2:0] real_hits_hi = {real_hits_hi_hi, hitsVec_3}; // @[package.scala:45:27] wire [5:0] real_hits = {real_hits_hi, real_hits_lo}; // @[package.scala:45:27] wire [5:0] _tlb_hit_T = real_hits; // @[package.scala:45:27] wire _hits_T = ~vm_enabled; // @[TLB.scala:399:61, :442:18] wire [6:0] hits = {_hits_T, real_hits}; // @[package.scala:45:27] wire _newEntry_g_T; // @[TLB.scala:453:25] wire _newEntry_sw_T_6; // @[PTW.scala:151:40] wire _newEntry_sx_T_5; // @[PTW.scala:153:35] wire _newEntry_sr_T_5; // @[PTW.scala:149:35] wire newEntry_g; // @[TLB.scala:449:24] wire newEntry_sw; // @[TLB.scala:449:24] wire newEntry_sx; // @[TLB.scala:449:24] wire newEntry_sr; // @[TLB.scala:449:24] wire newEntry_ppp; // @[TLB.scala:449:24] wire newEntry_pal; // @[TLB.scala:449:24] wire newEntry_paa; // @[TLB.scala:449:24] wire newEntry_eff; // @[TLB.scala:449:24] assign _newEntry_g_T = io_ptw_resp_bits_pte_g_0 & io_ptw_resp_bits_pte_v_0; // @[TLB.scala:318:7, :453:25] assign newEntry_g = _newEntry_g_T; // @[TLB.scala:449:24, :453:25] wire _newEntry_ae_stage2_T = io_ptw_resp_bits_ae_final_0 & io_ptw_resp_bits_gpa_is_pte_0; // @[TLB.scala:318:7, :456:53] wire _newEntry_sr_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7] wire _newEntry_sr_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sr_T; // @[TLB.scala:318:7] wire _newEntry_sr_T_2 = io_ptw_resp_bits_pte_r_0 | _newEntry_sr_T_1; // @[TLB.scala:318:7] wire _newEntry_sr_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sr_T_2; // @[TLB.scala:318:7] wire _newEntry_sr_T_4 = _newEntry_sr_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7] assign _newEntry_sr_T_5 = _newEntry_sr_T_4 & io_ptw_resp_bits_pte_r_0; // @[TLB.scala:318:7] assign newEntry_sr = _newEntry_sr_T_5; // @[TLB.scala:449:24] wire _newEntry_sw_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7] wire _newEntry_sw_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sw_T; // @[TLB.scala:318:7] wire _newEntry_sw_T_2 = io_ptw_resp_bits_pte_r_0 | _newEntry_sw_T_1; // @[TLB.scala:318:7] wire _newEntry_sw_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sw_T_2; // @[TLB.scala:318:7] wire _newEntry_sw_T_4 = _newEntry_sw_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7] wire _newEntry_sw_T_5 = _newEntry_sw_T_4 & io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7] assign _newEntry_sw_T_6 = _newEntry_sw_T_5 & io_ptw_resp_bits_pte_d_0; // @[TLB.scala:318:7] assign newEntry_sw = _newEntry_sw_T_6; // @[TLB.scala:449:24] wire _newEntry_sx_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7] wire _newEntry_sx_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sx_T; // @[TLB.scala:318:7] wire _newEntry_sx_T_2 = io_ptw_resp_bits_pte_r_0 | _newEntry_sx_T_1; // @[TLB.scala:318:7] wire _newEntry_sx_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sx_T_2; // @[TLB.scala:318:7] wire _newEntry_sx_T_4 = _newEntry_sx_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7] assign _newEntry_sx_T_5 = _newEntry_sx_T_4 & io_ptw_resp_bits_pte_x_0; // @[TLB.scala:318:7] assign newEntry_sx = _newEntry_sx_T_5; // @[TLB.scala:449:24] wire [1:0] _GEN_25 = {newEntry_c, 1'h0}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign special_entry_data_0_lo_lo_lo = _GEN_25; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_lo_lo_lo = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_data_0_lo_lo_lo = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_1_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_1_data_0_lo_lo_lo = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_2_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_2_data_0_lo_lo_lo = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_3_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_3_data_0_lo_lo_lo = _GEN_25; // @[TLB.scala:217:24] wire [1:0] _GEN_26 = {newEntry_pal, newEntry_paa}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign special_entry_data_0_lo_lo_hi_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_lo_lo_hi_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_data_0_lo_lo_hi_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_1_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_1_data_0_lo_lo_hi_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_2_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_2_data_0_lo_lo_hi_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_3_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_3_data_0_lo_lo_hi_hi = _GEN_26; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_lo_lo_hi = {special_entry_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] special_entry_data_0_lo_lo = {special_entry_data_0_lo_lo_hi, special_entry_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [1:0] _GEN_27 = {newEntry_px, newEntry_pr}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign special_entry_data_0_lo_hi_lo_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_lo_hi_lo_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_data_0_lo_hi_lo_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_1_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_1_data_0_lo_hi_lo_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_2_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_2_data_0_lo_hi_lo_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_3_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_3_data_0_lo_hi_lo_hi = _GEN_27; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_lo_hi_lo = {special_entry_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [1:0] _GEN_28 = {newEntry_hx, newEntry_hr}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign special_entry_data_0_lo_hi_hi_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_lo_hi_hi_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_data_0_lo_hi_hi_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_1_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_1_data_0_lo_hi_hi_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_2_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_2_data_0_lo_hi_hi_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_3_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_3_data_0_lo_hi_hi_hi = _GEN_28; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_lo_hi_hi = {special_entry_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] special_entry_data_0_lo_hi = {special_entry_data_0_lo_hi_hi, special_entry_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] special_entry_data_0_lo = {special_entry_data_0_lo_hi, special_entry_data_0_lo_lo}; // @[TLB.scala:217:24] wire [1:0] _GEN_29 = {newEntry_sx, newEntry_sr}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign special_entry_data_0_hi_lo_lo_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_hi_lo_lo_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_data_0_hi_lo_lo_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_1_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_1_data_0_hi_lo_lo_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_2_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_2_data_0_hi_lo_lo_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_3_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_3_data_0_hi_lo_lo_hi = _GEN_29; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_hi_lo_lo = {special_entry_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [1:0] _GEN_30 = {newEntry_pf, newEntry_gf}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign special_entry_data_0_hi_lo_hi_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_hi_lo_hi_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_data_0_hi_lo_hi_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_1_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_1_data_0_hi_lo_hi_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_2_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_2_data_0_hi_lo_hi_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_3_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_3_data_0_hi_lo_hi_hi = _GEN_30; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_hi_lo_hi = {special_entry_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] special_entry_data_0_hi_lo = {special_entry_data_0_hi_lo_hi, special_entry_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [1:0] _GEN_31 = {newEntry_ae_ptw, newEntry_ae_final}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign special_entry_data_0_hi_hi_lo_hi = _GEN_31; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_hi_hi_lo_hi = _GEN_31; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_data_0_hi_hi_lo_hi = _GEN_31; // @[TLB.scala:217:24] wire [1:0] sectored_entries_1_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_1_data_0_hi_hi_lo_hi = _GEN_31; // @[TLB.scala:217:24] wire [1:0] sectored_entries_2_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_2_data_0_hi_hi_lo_hi = _GEN_31; // @[TLB.scala:217:24] wire [1:0] sectored_entries_3_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_3_data_0_hi_hi_lo_hi = _GEN_31; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_hi_hi_lo = {special_entry_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [20:0] _GEN_32 = {newEntry_ppn, newEntry_u}; // @[TLB.scala:217:24, :449:24] wire [20:0] special_entry_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign special_entry_data_0_hi_hi_hi_hi = _GEN_32; // @[TLB.scala:217:24] wire [20:0] superpage_entries_0_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_hi_hi_hi_hi = _GEN_32; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_data_0_hi_hi_hi_hi = _GEN_32; // @[TLB.scala:217:24] wire [20:0] sectored_entries_1_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_1_data_0_hi_hi_hi_hi = _GEN_32; // @[TLB.scala:217:24] wire [20:0] sectored_entries_2_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_2_data_0_hi_hi_hi_hi = _GEN_32; // @[TLB.scala:217:24] wire [20:0] sectored_entries_3_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_3_data_0_hi_hi_hi_hi = _GEN_32; // @[TLB.scala:217:24] wire [21:0] special_entry_data_0_hi_hi_hi = {special_entry_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] special_entry_data_0_hi_hi = {special_entry_data_0_hi_hi_hi, special_entry_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] special_entry_data_0_hi = {special_entry_data_0_hi_hi, special_entry_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _special_entry_data_0_T = {special_entry_data_0_hi, special_entry_data_0_lo}; // @[TLB.scala:217:24] wire _superpage_entries_0_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13] wire [2:0] superpage_entries_0_data_0_lo_lo_hi = {superpage_entries_0_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] superpage_entries_0_data_0_lo_lo = {superpage_entries_0_data_0_lo_lo_hi, superpage_entries_0_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_0_data_0_lo_hi_lo = {superpage_entries_0_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_0_data_0_lo_hi_hi = {superpage_entries_0_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_0_data_0_lo_hi = {superpage_entries_0_data_0_lo_hi_hi, superpage_entries_0_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] superpage_entries_0_data_0_lo = {superpage_entries_0_data_0_lo_hi, superpage_entries_0_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_0_data_0_hi_lo_lo = {superpage_entries_0_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_0_data_0_hi_lo_hi = {superpage_entries_0_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_0_data_0_hi_lo = {superpage_entries_0_data_0_hi_lo_hi, superpage_entries_0_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_0_data_0_hi_hi_lo = {superpage_entries_0_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] superpage_entries_0_data_0_hi_hi_hi = {superpage_entries_0_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] superpage_entries_0_data_0_hi_hi = {superpage_entries_0_data_0_hi_hi_hi, superpage_entries_0_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] superpage_entries_0_data_0_hi = {superpage_entries_0_data_0_hi_hi, superpage_entries_0_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _superpage_entries_0_data_0_T = {superpage_entries_0_data_0_hi, superpage_entries_0_data_0_lo}; // @[TLB.scala:217:24] wire [1:0] r_memIdx = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] waddr_1 = r_sectored_hit_valid ? r_sectored_hit_bits : r_sectored_repl_addr; // @[TLB.scala:356:33, :357:27, :485:22] wire [2:0] sectored_entries_0_data_0_lo_lo_hi = {sectored_entries_0_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_data_0_lo_lo = {sectored_entries_0_data_0_lo_lo_hi, sectored_entries_0_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_data_0_lo_hi_lo = {sectored_entries_0_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_data_0_lo_hi_hi = {sectored_entries_0_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_data_0_lo_hi = {sectored_entries_0_data_0_lo_hi_hi, sectored_entries_0_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_data_0_lo = {sectored_entries_0_data_0_lo_hi, sectored_entries_0_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_data_0_hi_lo_lo = {sectored_entries_0_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_data_0_hi_lo_hi = {sectored_entries_0_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_data_0_hi_lo = {sectored_entries_0_data_0_hi_lo_hi, sectored_entries_0_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_data_0_hi_hi_lo = {sectored_entries_0_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_data_0_hi_hi_hi = {sectored_entries_0_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_data_0_hi_hi = {sectored_entries_0_data_0_hi_hi_hi, sectored_entries_0_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_data_0_hi = {sectored_entries_0_data_0_hi_hi, sectored_entries_0_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_data_0_T = {sectored_entries_0_data_0_hi, sectored_entries_0_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_1_data_0_lo_lo_hi = {sectored_entries_1_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_1_data_0_lo_lo = {sectored_entries_1_data_0_lo_lo_hi, sectored_entries_1_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_1_data_0_lo_hi_lo = {sectored_entries_1_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_1_data_0_lo_hi_hi = {sectored_entries_1_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_1_data_0_lo_hi = {sectored_entries_1_data_0_lo_hi_hi, sectored_entries_1_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_1_data_0_lo = {sectored_entries_1_data_0_lo_hi, sectored_entries_1_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_1_data_0_hi_lo_lo = {sectored_entries_1_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_1_data_0_hi_lo_hi = {sectored_entries_1_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_1_data_0_hi_lo = {sectored_entries_1_data_0_hi_lo_hi, sectored_entries_1_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_1_data_0_hi_hi_lo = {sectored_entries_1_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_1_data_0_hi_hi_hi = {sectored_entries_1_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_1_data_0_hi_hi = {sectored_entries_1_data_0_hi_hi_hi, sectored_entries_1_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_1_data_0_hi = {sectored_entries_1_data_0_hi_hi, sectored_entries_1_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_1_data_0_T = {sectored_entries_1_data_0_hi, sectored_entries_1_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_2_data_0_lo_lo_hi = {sectored_entries_2_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_2_data_0_lo_lo = {sectored_entries_2_data_0_lo_lo_hi, sectored_entries_2_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_2_data_0_lo_hi_lo = {sectored_entries_2_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_2_data_0_lo_hi_hi = {sectored_entries_2_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_2_data_0_lo_hi = {sectored_entries_2_data_0_lo_hi_hi, sectored_entries_2_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_2_data_0_lo = {sectored_entries_2_data_0_lo_hi, sectored_entries_2_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_2_data_0_hi_lo_lo = {sectored_entries_2_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_2_data_0_hi_lo_hi = {sectored_entries_2_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_2_data_0_hi_lo = {sectored_entries_2_data_0_hi_lo_hi, sectored_entries_2_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_2_data_0_hi_hi_lo = {sectored_entries_2_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_2_data_0_hi_hi_hi = {sectored_entries_2_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_2_data_0_hi_hi = {sectored_entries_2_data_0_hi_hi_hi, sectored_entries_2_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_2_data_0_hi = {sectored_entries_2_data_0_hi_hi, sectored_entries_2_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_2_data_0_T = {sectored_entries_2_data_0_hi, sectored_entries_2_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_3_data_0_lo_lo_hi = {sectored_entries_3_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_3_data_0_lo_lo = {sectored_entries_3_data_0_lo_lo_hi, sectored_entries_3_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_3_data_0_lo_hi_lo = {sectored_entries_3_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_3_data_0_lo_hi_hi = {sectored_entries_3_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_3_data_0_lo_hi = {sectored_entries_3_data_0_lo_hi_hi, sectored_entries_3_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_3_data_0_lo = {sectored_entries_3_data_0_lo_hi, sectored_entries_3_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_3_data_0_hi_lo_lo = {sectored_entries_3_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_3_data_0_hi_lo_hi = {sectored_entries_3_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_3_data_0_hi_lo = {sectored_entries_3_data_0_hi_lo_hi, sectored_entries_3_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_3_data_0_hi_hi_lo = {sectored_entries_3_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_3_data_0_hi_hi_hi = {sectored_entries_3_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_3_data_0_hi_hi = {sectored_entries_3_data_0_hi_hi_hi, sectored_entries_3_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_3_data_0_hi = {sectored_entries_3_data_0_hi_hi, sectored_entries_3_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_3_data_0_T = {sectored_entries_3_data_0_hi, sectored_entries_3_data_0_lo}; // @[TLB.scala:217:24] wire [19:0] _entries_T_22; // @[TLB.scala:170:77] wire _entries_T_21; // @[TLB.scala:170:77] wire _entries_T_20; // @[TLB.scala:170:77] wire _entries_T_19; // @[TLB.scala:170:77] wire _entries_T_18; // @[TLB.scala:170:77] wire _entries_T_17; // @[TLB.scala:170:77] wire _entries_T_16; // @[TLB.scala:170:77] wire _entries_T_15; // @[TLB.scala:170:77] wire _entries_T_14; // @[TLB.scala:170:77] wire _entries_T_13; // @[TLB.scala:170:77] wire _entries_T_12; // @[TLB.scala:170:77] wire _entries_T_11; // @[TLB.scala:170:77] wire _entries_T_10; // @[TLB.scala:170:77] wire _entries_T_9; // @[TLB.scala:170:77] wire _entries_T_8; // @[TLB.scala:170:77] wire _entries_T_7; // @[TLB.scala:170:77] wire _entries_T_6; // @[TLB.scala:170:77] wire _entries_T_5; // @[TLB.scala:170:77] wire _entries_T_4; // @[TLB.scala:170:77] wire _entries_T_3; // @[TLB.scala:170:77] wire _entries_T_2; // @[TLB.scala:170:77] wire _entries_T_1; // @[TLB.scala:170:77] wire _entries_T; // @[TLB.scala:170:77] assign _entries_T = _entries_WIRE_1[0]; // @[TLB.scala:170:77] wire _entries_WIRE_fragmented_superpage = _entries_T; // @[TLB.scala:170:77] assign _entries_T_1 = _entries_WIRE_1[1]; // @[TLB.scala:170:77] wire _entries_WIRE_c = _entries_T_1; // @[TLB.scala:170:77] assign _entries_T_2 = _entries_WIRE_1[2]; // @[TLB.scala:170:77] wire _entries_WIRE_eff = _entries_T_2; // @[TLB.scala:170:77] assign _entries_T_3 = _entries_WIRE_1[3]; // @[TLB.scala:170:77] wire _entries_WIRE_paa = _entries_T_3; // @[TLB.scala:170:77] assign _entries_T_4 = _entries_WIRE_1[4]; // @[TLB.scala:170:77] wire _entries_WIRE_pal = _entries_T_4; // @[TLB.scala:170:77] assign _entries_T_5 = _entries_WIRE_1[5]; // @[TLB.scala:170:77] wire _entries_WIRE_ppp = _entries_T_5; // @[TLB.scala:170:77] assign _entries_T_6 = _entries_WIRE_1[6]; // @[TLB.scala:170:77] wire _entries_WIRE_pr = _entries_T_6; // @[TLB.scala:170:77] assign _entries_T_7 = _entries_WIRE_1[7]; // @[TLB.scala:170:77] wire _entries_WIRE_px = _entries_T_7; // @[TLB.scala:170:77] assign _entries_T_8 = _entries_WIRE_1[8]; // @[TLB.scala:170:77] wire _entries_WIRE_pw = _entries_T_8; // @[TLB.scala:170:77] assign _entries_T_9 = _entries_WIRE_1[9]; // @[TLB.scala:170:77] wire _entries_WIRE_hr = _entries_T_9; // @[TLB.scala:170:77] assign _entries_T_10 = _entries_WIRE_1[10]; // @[TLB.scala:170:77] wire _entries_WIRE_hx = _entries_T_10; // @[TLB.scala:170:77] assign _entries_T_11 = _entries_WIRE_1[11]; // @[TLB.scala:170:77] wire _entries_WIRE_hw = _entries_T_11; // @[TLB.scala:170:77] assign _entries_T_12 = _entries_WIRE_1[12]; // @[TLB.scala:170:77] wire _entries_WIRE_sr = _entries_T_12; // @[TLB.scala:170:77] assign _entries_T_13 = _entries_WIRE_1[13]; // @[TLB.scala:170:77] wire _entries_WIRE_sx = _entries_T_13; // @[TLB.scala:170:77] assign _entries_T_14 = _entries_WIRE_1[14]; // @[TLB.scala:170:77] wire _entries_WIRE_sw = _entries_T_14; // @[TLB.scala:170:77] assign _entries_T_15 = _entries_WIRE_1[15]; // @[TLB.scala:170:77] wire _entries_WIRE_gf = _entries_T_15; // @[TLB.scala:170:77] assign _entries_T_16 = _entries_WIRE_1[16]; // @[TLB.scala:170:77] wire _entries_WIRE_pf = _entries_T_16; // @[TLB.scala:170:77] assign _entries_T_17 = _entries_WIRE_1[17]; // @[TLB.scala:170:77] wire _entries_WIRE_ae_stage2 = _entries_T_17; // @[TLB.scala:170:77] assign _entries_T_18 = _entries_WIRE_1[18]; // @[TLB.scala:170:77] wire _entries_WIRE_ae_final = _entries_T_18; // @[TLB.scala:170:77] assign _entries_T_19 = _entries_WIRE_1[19]; // @[TLB.scala:170:77] wire _entries_WIRE_ae_ptw = _entries_T_19; // @[TLB.scala:170:77] assign _entries_T_20 = _entries_WIRE_1[20]; // @[TLB.scala:170:77] wire _entries_WIRE_g = _entries_T_20; // @[TLB.scala:170:77] assign _entries_T_21 = _entries_WIRE_1[21]; // @[TLB.scala:170:77] wire _entries_WIRE_u = _entries_T_21; // @[TLB.scala:170:77] assign _entries_T_22 = _entries_WIRE_1[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_ppn = _entries_T_22; // @[TLB.scala:170:77] wire [19:0] _entries_T_45; // @[TLB.scala:170:77] wire _entries_T_44; // @[TLB.scala:170:77] wire _entries_T_43; // @[TLB.scala:170:77] wire _entries_T_42; // @[TLB.scala:170:77] wire _entries_T_41; // @[TLB.scala:170:77] wire _entries_T_40; // @[TLB.scala:170:77] wire _entries_T_39; // @[TLB.scala:170:77] wire _entries_T_38; // @[TLB.scala:170:77] wire _entries_T_37; // @[TLB.scala:170:77] wire _entries_T_36; // @[TLB.scala:170:77] wire _entries_T_35; // @[TLB.scala:170:77] wire _entries_T_34; // @[TLB.scala:170:77] wire _entries_T_33; // @[TLB.scala:170:77] wire _entries_T_32; // @[TLB.scala:170:77] wire _entries_T_31; // @[TLB.scala:170:77] wire _entries_T_30; // @[TLB.scala:170:77] wire _entries_T_29; // @[TLB.scala:170:77] wire _entries_T_28; // @[TLB.scala:170:77] wire _entries_T_27; // @[TLB.scala:170:77] wire _entries_T_26; // @[TLB.scala:170:77] wire _entries_T_25; // @[TLB.scala:170:77] wire _entries_T_24; // @[TLB.scala:170:77] wire _entries_T_23; // @[TLB.scala:170:77] assign _entries_T_23 = _entries_WIRE_3[0]; // @[TLB.scala:170:77] wire _entries_WIRE_2_fragmented_superpage = _entries_T_23; // @[TLB.scala:170:77] assign _entries_T_24 = _entries_WIRE_3[1]; // @[TLB.scala:170:77] wire _entries_WIRE_2_c = _entries_T_24; // @[TLB.scala:170:77] assign _entries_T_25 = _entries_WIRE_3[2]; // @[TLB.scala:170:77] wire _entries_WIRE_2_eff = _entries_T_25; // @[TLB.scala:170:77] assign _entries_T_26 = _entries_WIRE_3[3]; // @[TLB.scala:170:77] wire _entries_WIRE_2_paa = _entries_T_26; // @[TLB.scala:170:77] assign _entries_T_27 = _entries_WIRE_3[4]; // @[TLB.scala:170:77] wire _entries_WIRE_2_pal = _entries_T_27; // @[TLB.scala:170:77] assign _entries_T_28 = _entries_WIRE_3[5]; // @[TLB.scala:170:77] wire _entries_WIRE_2_ppp = _entries_T_28; // @[TLB.scala:170:77] assign _entries_T_29 = _entries_WIRE_3[6]; // @[TLB.scala:170:77] wire _entries_WIRE_2_pr = _entries_T_29; // @[TLB.scala:170:77] assign _entries_T_30 = _entries_WIRE_3[7]; // @[TLB.scala:170:77] wire _entries_WIRE_2_px = _entries_T_30; // @[TLB.scala:170:77] assign _entries_T_31 = _entries_WIRE_3[8]; // @[TLB.scala:170:77] wire _entries_WIRE_2_pw = _entries_T_31; // @[TLB.scala:170:77] assign _entries_T_32 = _entries_WIRE_3[9]; // @[TLB.scala:170:77] wire _entries_WIRE_2_hr = _entries_T_32; // @[TLB.scala:170:77] assign _entries_T_33 = _entries_WIRE_3[10]; // @[TLB.scala:170:77] wire _entries_WIRE_2_hx = _entries_T_33; // @[TLB.scala:170:77] assign _entries_T_34 = _entries_WIRE_3[11]; // @[TLB.scala:170:77] wire _entries_WIRE_2_hw = _entries_T_34; // @[TLB.scala:170:77] assign _entries_T_35 = _entries_WIRE_3[12]; // @[TLB.scala:170:77] wire _entries_WIRE_2_sr = _entries_T_35; // @[TLB.scala:170:77] assign _entries_T_36 = _entries_WIRE_3[13]; // @[TLB.scala:170:77] wire _entries_WIRE_2_sx = _entries_T_36; // @[TLB.scala:170:77] assign _entries_T_37 = _entries_WIRE_3[14]; // @[TLB.scala:170:77] wire _entries_WIRE_2_sw = _entries_T_37; // @[TLB.scala:170:77] assign _entries_T_38 = _entries_WIRE_3[15]; // @[TLB.scala:170:77] wire _entries_WIRE_2_gf = _entries_T_38; // @[TLB.scala:170:77] assign _entries_T_39 = _entries_WIRE_3[16]; // @[TLB.scala:170:77] wire _entries_WIRE_2_pf = _entries_T_39; // @[TLB.scala:170:77] assign _entries_T_40 = _entries_WIRE_3[17]; // @[TLB.scala:170:77] wire _entries_WIRE_2_ae_stage2 = _entries_T_40; // @[TLB.scala:170:77] assign _entries_T_41 = _entries_WIRE_3[18]; // @[TLB.scala:170:77] wire _entries_WIRE_2_ae_final = _entries_T_41; // @[TLB.scala:170:77] assign _entries_T_42 = _entries_WIRE_3[19]; // @[TLB.scala:170:77] wire _entries_WIRE_2_ae_ptw = _entries_T_42; // @[TLB.scala:170:77] assign _entries_T_43 = _entries_WIRE_3[20]; // @[TLB.scala:170:77] wire _entries_WIRE_2_g = _entries_T_43; // @[TLB.scala:170:77] assign _entries_T_44 = _entries_WIRE_3[21]; // @[TLB.scala:170:77] wire _entries_WIRE_2_u = _entries_T_44; // @[TLB.scala:170:77] assign _entries_T_45 = _entries_WIRE_3[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_2_ppn = _entries_T_45; // @[TLB.scala:170:77] wire [19:0] _entries_T_68; // @[TLB.scala:170:77] wire _entries_T_67; // @[TLB.scala:170:77] wire _entries_T_66; // @[TLB.scala:170:77] wire _entries_T_65; // @[TLB.scala:170:77] wire _entries_T_64; // @[TLB.scala:170:77] wire _entries_T_63; // @[TLB.scala:170:77] wire _entries_T_62; // @[TLB.scala:170:77] wire _entries_T_61; // @[TLB.scala:170:77] wire _entries_T_60; // @[TLB.scala:170:77] wire _entries_T_59; // @[TLB.scala:170:77] wire _entries_T_58; // @[TLB.scala:170:77] wire _entries_T_57; // @[TLB.scala:170:77] wire _entries_T_56; // @[TLB.scala:170:77] wire _entries_T_55; // @[TLB.scala:170:77] wire _entries_T_54; // @[TLB.scala:170:77] wire _entries_T_53; // @[TLB.scala:170:77] wire _entries_T_52; // @[TLB.scala:170:77] wire _entries_T_51; // @[TLB.scala:170:77] wire _entries_T_50; // @[TLB.scala:170:77] wire _entries_T_49; // @[TLB.scala:170:77] wire _entries_T_48; // @[TLB.scala:170:77] wire _entries_T_47; // @[TLB.scala:170:77] wire _entries_T_46; // @[TLB.scala:170:77] assign _entries_T_46 = _entries_WIRE_5[0]; // @[TLB.scala:170:77] wire _entries_WIRE_4_fragmented_superpage = _entries_T_46; // @[TLB.scala:170:77] assign _entries_T_47 = _entries_WIRE_5[1]; // @[TLB.scala:170:77] wire _entries_WIRE_4_c = _entries_T_47; // @[TLB.scala:170:77] assign _entries_T_48 = _entries_WIRE_5[2]; // @[TLB.scala:170:77] wire _entries_WIRE_4_eff = _entries_T_48; // @[TLB.scala:170:77] assign _entries_T_49 = _entries_WIRE_5[3]; // @[TLB.scala:170:77] wire _entries_WIRE_4_paa = _entries_T_49; // @[TLB.scala:170:77] assign _entries_T_50 = _entries_WIRE_5[4]; // @[TLB.scala:170:77] wire _entries_WIRE_4_pal = _entries_T_50; // @[TLB.scala:170:77] assign _entries_T_51 = _entries_WIRE_5[5]; // @[TLB.scala:170:77] wire _entries_WIRE_4_ppp = _entries_T_51; // @[TLB.scala:170:77] assign _entries_T_52 = _entries_WIRE_5[6]; // @[TLB.scala:170:77] wire _entries_WIRE_4_pr = _entries_T_52; // @[TLB.scala:170:77] assign _entries_T_53 = _entries_WIRE_5[7]; // @[TLB.scala:170:77] wire _entries_WIRE_4_px = _entries_T_53; // @[TLB.scala:170:77] assign _entries_T_54 = _entries_WIRE_5[8]; // @[TLB.scala:170:77] wire _entries_WIRE_4_pw = _entries_T_54; // @[TLB.scala:170:77] assign _entries_T_55 = _entries_WIRE_5[9]; // @[TLB.scala:170:77] wire _entries_WIRE_4_hr = _entries_T_55; // @[TLB.scala:170:77] assign _entries_T_56 = _entries_WIRE_5[10]; // @[TLB.scala:170:77] wire _entries_WIRE_4_hx = _entries_T_56; // @[TLB.scala:170:77] assign _entries_T_57 = _entries_WIRE_5[11]; // @[TLB.scala:170:77] wire _entries_WIRE_4_hw = _entries_T_57; // @[TLB.scala:170:77] assign _entries_T_58 = _entries_WIRE_5[12]; // @[TLB.scala:170:77] wire _entries_WIRE_4_sr = _entries_T_58; // @[TLB.scala:170:77] assign _entries_T_59 = _entries_WIRE_5[13]; // @[TLB.scala:170:77] wire _entries_WIRE_4_sx = _entries_T_59; // @[TLB.scala:170:77] assign _entries_T_60 = _entries_WIRE_5[14]; // @[TLB.scala:170:77] wire _entries_WIRE_4_sw = _entries_T_60; // @[TLB.scala:170:77] assign _entries_T_61 = _entries_WIRE_5[15]; // @[TLB.scala:170:77] wire _entries_WIRE_4_gf = _entries_T_61; // @[TLB.scala:170:77] assign _entries_T_62 = _entries_WIRE_5[16]; // @[TLB.scala:170:77] wire _entries_WIRE_4_pf = _entries_T_62; // @[TLB.scala:170:77] assign _entries_T_63 = _entries_WIRE_5[17]; // @[TLB.scala:170:77] wire _entries_WIRE_4_ae_stage2 = _entries_T_63; // @[TLB.scala:170:77] assign _entries_T_64 = _entries_WIRE_5[18]; // @[TLB.scala:170:77] wire _entries_WIRE_4_ae_final = _entries_T_64; // @[TLB.scala:170:77] assign _entries_T_65 = _entries_WIRE_5[19]; // @[TLB.scala:170:77] wire _entries_WIRE_4_ae_ptw = _entries_T_65; // @[TLB.scala:170:77] assign _entries_T_66 = _entries_WIRE_5[20]; // @[TLB.scala:170:77] wire _entries_WIRE_4_g = _entries_T_66; // @[TLB.scala:170:77] assign _entries_T_67 = _entries_WIRE_5[21]; // @[TLB.scala:170:77] wire _entries_WIRE_4_u = _entries_T_67; // @[TLB.scala:170:77] assign _entries_T_68 = _entries_WIRE_5[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_4_ppn = _entries_T_68; // @[TLB.scala:170:77] wire [19:0] _entries_T_91; // @[TLB.scala:170:77] wire _entries_T_90; // @[TLB.scala:170:77] wire _entries_T_89; // @[TLB.scala:170:77] wire _entries_T_88; // @[TLB.scala:170:77] wire _entries_T_87; // @[TLB.scala:170:77] wire _entries_T_86; // @[TLB.scala:170:77] wire _entries_T_85; // @[TLB.scala:170:77] wire _entries_T_84; // @[TLB.scala:170:77] wire _entries_T_83; // @[TLB.scala:170:77] wire _entries_T_82; // @[TLB.scala:170:77] wire _entries_T_81; // @[TLB.scala:170:77] wire _entries_T_80; // @[TLB.scala:170:77] wire _entries_T_79; // @[TLB.scala:170:77] wire _entries_T_78; // @[TLB.scala:170:77] wire _entries_T_77; // @[TLB.scala:170:77] wire _entries_T_76; // @[TLB.scala:170:77] wire _entries_T_75; // @[TLB.scala:170:77] wire _entries_T_74; // @[TLB.scala:170:77] wire _entries_T_73; // @[TLB.scala:170:77] wire _entries_T_72; // @[TLB.scala:170:77] wire _entries_T_71; // @[TLB.scala:170:77] wire _entries_T_70; // @[TLB.scala:170:77] wire _entries_T_69; // @[TLB.scala:170:77] assign _entries_T_69 = _entries_WIRE_7[0]; // @[TLB.scala:170:77] wire _entries_WIRE_6_fragmented_superpage = _entries_T_69; // @[TLB.scala:170:77] assign _entries_T_70 = _entries_WIRE_7[1]; // @[TLB.scala:170:77] wire _entries_WIRE_6_c = _entries_T_70; // @[TLB.scala:170:77] assign _entries_T_71 = _entries_WIRE_7[2]; // @[TLB.scala:170:77] wire _entries_WIRE_6_eff = _entries_T_71; // @[TLB.scala:170:77] assign _entries_T_72 = _entries_WIRE_7[3]; // @[TLB.scala:170:77] wire _entries_WIRE_6_paa = _entries_T_72; // @[TLB.scala:170:77] assign _entries_T_73 = _entries_WIRE_7[4]; // @[TLB.scala:170:77] wire _entries_WIRE_6_pal = _entries_T_73; // @[TLB.scala:170:77] assign _entries_T_74 = _entries_WIRE_7[5]; // @[TLB.scala:170:77] wire _entries_WIRE_6_ppp = _entries_T_74; // @[TLB.scala:170:77] assign _entries_T_75 = _entries_WIRE_7[6]; // @[TLB.scala:170:77] wire _entries_WIRE_6_pr = _entries_T_75; // @[TLB.scala:170:77] assign _entries_T_76 = _entries_WIRE_7[7]; // @[TLB.scala:170:77] wire _entries_WIRE_6_px = _entries_T_76; // @[TLB.scala:170:77] assign _entries_T_77 = _entries_WIRE_7[8]; // @[TLB.scala:170:77] wire _entries_WIRE_6_pw = _entries_T_77; // @[TLB.scala:170:77] assign _entries_T_78 = _entries_WIRE_7[9]; // @[TLB.scala:170:77] wire _entries_WIRE_6_hr = _entries_T_78; // @[TLB.scala:170:77] assign _entries_T_79 = _entries_WIRE_7[10]; // @[TLB.scala:170:77] wire _entries_WIRE_6_hx = _entries_T_79; // @[TLB.scala:170:77] assign _entries_T_80 = _entries_WIRE_7[11]; // @[TLB.scala:170:77] wire _entries_WIRE_6_hw = _entries_T_80; // @[TLB.scala:170:77] assign _entries_T_81 = _entries_WIRE_7[12]; // @[TLB.scala:170:77] wire _entries_WIRE_6_sr = _entries_T_81; // @[TLB.scala:170:77] assign _entries_T_82 = _entries_WIRE_7[13]; // @[TLB.scala:170:77] wire _entries_WIRE_6_sx = _entries_T_82; // @[TLB.scala:170:77] assign _entries_T_83 = _entries_WIRE_7[14]; // @[TLB.scala:170:77] wire _entries_WIRE_6_sw = _entries_T_83; // @[TLB.scala:170:77] assign _entries_T_84 = _entries_WIRE_7[15]; // @[TLB.scala:170:77] wire _entries_WIRE_6_gf = _entries_T_84; // @[TLB.scala:170:77] assign _entries_T_85 = _entries_WIRE_7[16]; // @[TLB.scala:170:77] wire _entries_WIRE_6_pf = _entries_T_85; // @[TLB.scala:170:77] assign _entries_T_86 = _entries_WIRE_7[17]; // @[TLB.scala:170:77] wire _entries_WIRE_6_ae_stage2 = _entries_T_86; // @[TLB.scala:170:77] assign _entries_T_87 = _entries_WIRE_7[18]; // @[TLB.scala:170:77] wire _entries_WIRE_6_ae_final = _entries_T_87; // @[TLB.scala:170:77] assign _entries_T_88 = _entries_WIRE_7[19]; // @[TLB.scala:170:77] wire _entries_WIRE_6_ae_ptw = _entries_T_88; // @[TLB.scala:170:77] assign _entries_T_89 = _entries_WIRE_7[20]; // @[TLB.scala:170:77] wire _entries_WIRE_6_g = _entries_T_89; // @[TLB.scala:170:77] assign _entries_T_90 = _entries_WIRE_7[21]; // @[TLB.scala:170:77] wire _entries_WIRE_6_u = _entries_T_90; // @[TLB.scala:170:77] assign _entries_T_91 = _entries_WIRE_7[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_6_ppn = _entries_T_91; // @[TLB.scala:170:77] wire [19:0] _entries_T_114; // @[TLB.scala:170:77] wire _entries_T_113; // @[TLB.scala:170:77] wire _entries_T_112; // @[TLB.scala:170:77] wire _entries_T_111; // @[TLB.scala:170:77] wire _entries_T_110; // @[TLB.scala:170:77] wire _entries_T_109; // @[TLB.scala:170:77] wire _entries_T_108; // @[TLB.scala:170:77] wire _entries_T_107; // @[TLB.scala:170:77] wire _entries_T_106; // @[TLB.scala:170:77] wire _entries_T_105; // @[TLB.scala:170:77] wire _entries_T_104; // @[TLB.scala:170:77] wire _entries_T_103; // @[TLB.scala:170:77] wire _entries_T_102; // @[TLB.scala:170:77] wire _entries_T_101; // @[TLB.scala:170:77] wire _entries_T_100; // @[TLB.scala:170:77] wire _entries_T_99; // @[TLB.scala:170:77] wire _entries_T_98; // @[TLB.scala:170:77] wire _entries_T_97; // @[TLB.scala:170:77] wire _entries_T_96; // @[TLB.scala:170:77] wire _entries_T_95; // @[TLB.scala:170:77] wire _entries_T_94; // @[TLB.scala:170:77] wire _entries_T_93; // @[TLB.scala:170:77] wire _entries_T_92; // @[TLB.scala:170:77] assign _entries_T_92 = _entries_WIRE_9[0]; // @[TLB.scala:170:77] wire _entries_WIRE_8_fragmented_superpage = _entries_T_92; // @[TLB.scala:170:77] assign _entries_T_93 = _entries_WIRE_9[1]; // @[TLB.scala:170:77] wire _entries_WIRE_8_c = _entries_T_93; // @[TLB.scala:170:77] assign _entries_T_94 = _entries_WIRE_9[2]; // @[TLB.scala:170:77] wire _entries_WIRE_8_eff = _entries_T_94; // @[TLB.scala:170:77] assign _entries_T_95 = _entries_WIRE_9[3]; // @[TLB.scala:170:77] wire _entries_WIRE_8_paa = _entries_T_95; // @[TLB.scala:170:77] assign _entries_T_96 = _entries_WIRE_9[4]; // @[TLB.scala:170:77] wire _entries_WIRE_8_pal = _entries_T_96; // @[TLB.scala:170:77] assign _entries_T_97 = _entries_WIRE_9[5]; // @[TLB.scala:170:77] wire _entries_WIRE_8_ppp = _entries_T_97; // @[TLB.scala:170:77] assign _entries_T_98 = _entries_WIRE_9[6]; // @[TLB.scala:170:77] wire _entries_WIRE_8_pr = _entries_T_98; // @[TLB.scala:170:77] assign _entries_T_99 = _entries_WIRE_9[7]; // @[TLB.scala:170:77] wire _entries_WIRE_8_px = _entries_T_99; // @[TLB.scala:170:77] assign _entries_T_100 = _entries_WIRE_9[8]; // @[TLB.scala:170:77] wire _entries_WIRE_8_pw = _entries_T_100; // @[TLB.scala:170:77] assign _entries_T_101 = _entries_WIRE_9[9]; // @[TLB.scala:170:77] wire _entries_WIRE_8_hr = _entries_T_101; // @[TLB.scala:170:77] assign _entries_T_102 = _entries_WIRE_9[10]; // @[TLB.scala:170:77] wire _entries_WIRE_8_hx = _entries_T_102; // @[TLB.scala:170:77] assign _entries_T_103 = _entries_WIRE_9[11]; // @[TLB.scala:170:77] wire _entries_WIRE_8_hw = _entries_T_103; // @[TLB.scala:170:77] assign _entries_T_104 = _entries_WIRE_9[12]; // @[TLB.scala:170:77] wire _entries_WIRE_8_sr = _entries_T_104; // @[TLB.scala:170:77] assign _entries_T_105 = _entries_WIRE_9[13]; // @[TLB.scala:170:77] wire _entries_WIRE_8_sx = _entries_T_105; // @[TLB.scala:170:77] assign _entries_T_106 = _entries_WIRE_9[14]; // @[TLB.scala:170:77] wire _entries_WIRE_8_sw = _entries_T_106; // @[TLB.scala:170:77] assign _entries_T_107 = _entries_WIRE_9[15]; // @[TLB.scala:170:77] wire _entries_WIRE_8_gf = _entries_T_107; // @[TLB.scala:170:77] assign _entries_T_108 = _entries_WIRE_9[16]; // @[TLB.scala:170:77] wire _entries_WIRE_8_pf = _entries_T_108; // @[TLB.scala:170:77] assign _entries_T_109 = _entries_WIRE_9[17]; // @[TLB.scala:170:77] wire _entries_WIRE_8_ae_stage2 = _entries_T_109; // @[TLB.scala:170:77] assign _entries_T_110 = _entries_WIRE_9[18]; // @[TLB.scala:170:77] wire _entries_WIRE_8_ae_final = _entries_T_110; // @[TLB.scala:170:77] assign _entries_T_111 = _entries_WIRE_9[19]; // @[TLB.scala:170:77] wire _entries_WIRE_8_ae_ptw = _entries_T_111; // @[TLB.scala:170:77] assign _entries_T_112 = _entries_WIRE_9[20]; // @[TLB.scala:170:77] wire _entries_WIRE_8_g = _entries_T_112; // @[TLB.scala:170:77] assign _entries_T_113 = _entries_WIRE_9[21]; // @[TLB.scala:170:77] wire _entries_WIRE_8_u = _entries_T_113; // @[TLB.scala:170:77] assign _entries_T_114 = _entries_WIRE_9[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_8_ppn = _entries_T_114; // @[TLB.scala:170:77] wire [19:0] _entries_T_137; // @[TLB.scala:170:77] wire _entries_T_136; // @[TLB.scala:170:77] wire _entries_T_135; // @[TLB.scala:170:77] wire _entries_T_134; // @[TLB.scala:170:77] wire _entries_T_133; // @[TLB.scala:170:77] wire _entries_T_132; // @[TLB.scala:170:77] wire _entries_T_131; // @[TLB.scala:170:77] wire _entries_T_130; // @[TLB.scala:170:77] wire _entries_T_129; // @[TLB.scala:170:77] wire _entries_T_128; // @[TLB.scala:170:77] wire _entries_T_127; // @[TLB.scala:170:77] wire _entries_T_126; // @[TLB.scala:170:77] wire _entries_T_125; // @[TLB.scala:170:77] wire _entries_T_124; // @[TLB.scala:170:77] wire _entries_T_123; // @[TLB.scala:170:77] wire _entries_T_122; // @[TLB.scala:170:77] wire _entries_T_121; // @[TLB.scala:170:77] wire _entries_T_120; // @[TLB.scala:170:77] wire _entries_T_119; // @[TLB.scala:170:77] wire _entries_T_118; // @[TLB.scala:170:77] wire _entries_T_117; // @[TLB.scala:170:77] wire _entries_T_116; // @[TLB.scala:170:77] wire _entries_T_115; // @[TLB.scala:170:77] assign _entries_T_115 = _entries_WIRE_11[0]; // @[TLB.scala:170:77] wire _entries_WIRE_10_fragmented_superpage = _entries_T_115; // @[TLB.scala:170:77] assign _entries_T_116 = _entries_WIRE_11[1]; // @[TLB.scala:170:77] wire _entries_WIRE_10_c = _entries_T_116; // @[TLB.scala:170:77] assign _entries_T_117 = _entries_WIRE_11[2]; // @[TLB.scala:170:77] wire _entries_WIRE_10_eff = _entries_T_117; // @[TLB.scala:170:77] assign _entries_T_118 = _entries_WIRE_11[3]; // @[TLB.scala:170:77] wire _entries_WIRE_10_paa = _entries_T_118; // @[TLB.scala:170:77] assign _entries_T_119 = _entries_WIRE_11[4]; // @[TLB.scala:170:77] wire _entries_WIRE_10_pal = _entries_T_119; // @[TLB.scala:170:77] assign _entries_T_120 = _entries_WIRE_11[5]; // @[TLB.scala:170:77] wire _entries_WIRE_10_ppp = _entries_T_120; // @[TLB.scala:170:77] assign _entries_T_121 = _entries_WIRE_11[6]; // @[TLB.scala:170:77] wire _entries_WIRE_10_pr = _entries_T_121; // @[TLB.scala:170:77] assign _entries_T_122 = _entries_WIRE_11[7]; // @[TLB.scala:170:77] wire _entries_WIRE_10_px = _entries_T_122; // @[TLB.scala:170:77] assign _entries_T_123 = _entries_WIRE_11[8]; // @[TLB.scala:170:77] wire _entries_WIRE_10_pw = _entries_T_123; // @[TLB.scala:170:77] assign _entries_T_124 = _entries_WIRE_11[9]; // @[TLB.scala:170:77] wire _entries_WIRE_10_hr = _entries_T_124; // @[TLB.scala:170:77] assign _entries_T_125 = _entries_WIRE_11[10]; // @[TLB.scala:170:77] wire _entries_WIRE_10_hx = _entries_T_125; // @[TLB.scala:170:77] assign _entries_T_126 = _entries_WIRE_11[11]; // @[TLB.scala:170:77] wire _entries_WIRE_10_hw = _entries_T_126; // @[TLB.scala:170:77] assign _entries_T_127 = _entries_WIRE_11[12]; // @[TLB.scala:170:77] wire _entries_WIRE_10_sr = _entries_T_127; // @[TLB.scala:170:77] assign _entries_T_128 = _entries_WIRE_11[13]; // @[TLB.scala:170:77] wire _entries_WIRE_10_sx = _entries_T_128; // @[TLB.scala:170:77] assign _entries_T_129 = _entries_WIRE_11[14]; // @[TLB.scala:170:77] wire _entries_WIRE_10_sw = _entries_T_129; // @[TLB.scala:170:77] assign _entries_T_130 = _entries_WIRE_11[15]; // @[TLB.scala:170:77] wire _entries_WIRE_10_gf = _entries_T_130; // @[TLB.scala:170:77] assign _entries_T_131 = _entries_WIRE_11[16]; // @[TLB.scala:170:77] wire _entries_WIRE_10_pf = _entries_T_131; // @[TLB.scala:170:77] assign _entries_T_132 = _entries_WIRE_11[17]; // @[TLB.scala:170:77] wire _entries_WIRE_10_ae_stage2 = _entries_T_132; // @[TLB.scala:170:77] assign _entries_T_133 = _entries_WIRE_11[18]; // @[TLB.scala:170:77] wire _entries_WIRE_10_ae_final = _entries_T_133; // @[TLB.scala:170:77] assign _entries_T_134 = _entries_WIRE_11[19]; // @[TLB.scala:170:77] wire _entries_WIRE_10_ae_ptw = _entries_T_134; // @[TLB.scala:170:77] assign _entries_T_135 = _entries_WIRE_11[20]; // @[TLB.scala:170:77] wire _entries_WIRE_10_g = _entries_T_135; // @[TLB.scala:170:77] assign _entries_T_136 = _entries_WIRE_11[21]; // @[TLB.scala:170:77] wire _entries_WIRE_10_u = _entries_T_136; // @[TLB.scala:170:77] assign _entries_T_137 = _entries_WIRE_11[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_10_ppn = _entries_T_137; // @[TLB.scala:170:77] wire _ppn_T = ~vm_enabled; // @[TLB.scala:399:61, :442:18, :502:30] wire [1:0] ppn_res = _entries_barrier_4_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore = _ppn_ignore_T; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_1 = ppn_ignore ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_2 = {_ppn_T_1[26:20], _ppn_T_1[19:0] | _entries_barrier_4_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_3 = _ppn_T_2[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _ppn_T_4 = {ppn_res, _ppn_T_3}; // @[TLB.scala:195:26, :198:{18,58}] wire _ppn_ignore_T_1 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :197:28, :341:30] wire [26:0] _ppn_T_6 = {_ppn_T_5[26:20], _ppn_T_5[19:0] | _entries_barrier_4_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_7 = _ppn_T_6[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _ppn_T_8 = {_ppn_T_4, _ppn_T_7}; // @[TLB.scala:198:{18,58}] wire [1:0] ppn_res_1 = _entries_barrier_5_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore_2 = _ppn_ignore_T_2; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_9 = ppn_ignore_2 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_10 = {_ppn_T_9[26:20], _ppn_T_9[19:0] | _entries_barrier_5_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_11 = _ppn_T_10[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _ppn_T_12 = {ppn_res_1, _ppn_T_11}; // @[TLB.scala:195:26, :198:{18,58}] wire _ppn_ignore_T_3 = ~(special_entry_level[1]); // @[TLB.scala:197:28, :346:56] wire ppn_ignore_3 = _ppn_ignore_T_3; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_13 = ppn_ignore_3 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_14 = {_ppn_T_13[26:20], _ppn_T_13[19:0] | _entries_barrier_5_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_15 = _ppn_T_14[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _ppn_T_16 = {_ppn_T_12, _ppn_T_15}; // @[TLB.scala:198:{18,58}] wire [19:0] _ppn_T_17 = vpn[19:0]; // @[TLB.scala:335:30, :502:125] wire [19:0] _ppn_T_18 = hitsVec_0 ? _entries_barrier_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_19 = hitsVec_1 ? _entries_barrier_1_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_20 = hitsVec_2 ? _entries_barrier_2_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_21 = hitsVec_3 ? _entries_barrier_3_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_22 = hitsVec_4 ? _ppn_T_8 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_23 = hitsVec_5 ? _ppn_T_16 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_24 = _ppn_T ? _ppn_T_17 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_25 = _ppn_T_18 | _ppn_T_19; // @[Mux.scala:30:73] wire [19:0] _ppn_T_26 = _ppn_T_25 | _ppn_T_20; // @[Mux.scala:30:73] wire [19:0] _ppn_T_27 = _ppn_T_26 | _ppn_T_21; // @[Mux.scala:30:73] wire [19:0] _ppn_T_28 = _ppn_T_27 | _ppn_T_22; // @[Mux.scala:30:73] wire [19:0] _ppn_T_29 = _ppn_T_28 | _ppn_T_23; // @[Mux.scala:30:73] wire [19:0] _ppn_T_30 = _ppn_T_29 | _ppn_T_24; // @[Mux.scala:30:73] wire [19:0] ppn = _ppn_T_30; // @[Mux.scala:30:73] wire [1:0] ptw_ae_array_lo_hi = {_entries_barrier_2_io_y_ae_ptw, _entries_barrier_1_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_ae_array_lo = {ptw_ae_array_lo_hi, _entries_barrier_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_ae_array_hi_hi = {_entries_barrier_5_io_y_ae_ptw, _entries_barrier_4_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_ae_array_hi = {ptw_ae_array_hi_hi, _entries_barrier_3_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [5:0] _ptw_ae_array_T = {ptw_ae_array_hi, ptw_ae_array_lo}; // @[package.scala:45:27] wire [6:0] ptw_ae_array = {1'h0, _ptw_ae_array_T}; // @[package.scala:45:27] wire [1:0] final_ae_array_lo_hi = {_entries_barrier_2_io_y_ae_final, _entries_barrier_1_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [2:0] final_ae_array_lo = {final_ae_array_lo_hi, _entries_barrier_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [1:0] final_ae_array_hi_hi = {_entries_barrier_5_io_y_ae_final, _entries_barrier_4_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [2:0] final_ae_array_hi = {final_ae_array_hi_hi, _entries_barrier_3_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [5:0] _final_ae_array_T = {final_ae_array_hi, final_ae_array_lo}; // @[package.scala:45:27] wire [6:0] final_ae_array = {1'h0, _final_ae_array_T}; // @[package.scala:45:27] wire [1:0] ptw_pf_array_lo_hi = {_entries_barrier_2_io_y_pf, _entries_barrier_1_io_y_pf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_pf_array_lo = {ptw_pf_array_lo_hi, _entries_barrier_io_y_pf}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_pf_array_hi_hi = {_entries_barrier_5_io_y_pf, _entries_barrier_4_io_y_pf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_pf_array_hi = {ptw_pf_array_hi_hi, _entries_barrier_3_io_y_pf}; // @[package.scala:45:27, :267:25] wire [5:0] _ptw_pf_array_T = {ptw_pf_array_hi, ptw_pf_array_lo}; // @[package.scala:45:27] wire [6:0] ptw_pf_array = {1'h0, _ptw_pf_array_T}; // @[package.scala:45:27] wire [1:0] ptw_gf_array_lo_hi = {_entries_barrier_2_io_y_gf, _entries_barrier_1_io_y_gf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_gf_array_lo = {ptw_gf_array_lo_hi, _entries_barrier_io_y_gf}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_gf_array_hi_hi = {_entries_barrier_5_io_y_gf, _entries_barrier_4_io_y_gf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_gf_array_hi = {ptw_gf_array_hi_hi, _entries_barrier_3_io_y_gf}; // @[package.scala:45:27, :267:25] wire [5:0] _ptw_gf_array_T = {ptw_gf_array_hi, ptw_gf_array_lo}; // @[package.scala:45:27] wire [6:0] ptw_gf_array = {1'h0, _ptw_gf_array_T}; // @[package.scala:45:27] wire [6:0] _gf_ld_array_T_3 = ptw_gf_array; // @[TLB.scala:509:25, :600:82] wire [6:0] _gf_st_array_T_2 = ptw_gf_array; // @[TLB.scala:509:25, :601:63] wire [6:0] _gf_inst_array_T_1 = ptw_gf_array; // @[TLB.scala:509:25, :602:46] wire [1:0] _GEN_33 = {_entries_barrier_2_io_y_u, _entries_barrier_1_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] priv_rw_ok_lo_hi; // @[package.scala:45:27] assign priv_rw_ok_lo_hi = _GEN_33; // @[package.scala:45:27] wire [1:0] priv_rw_ok_lo_hi_1; // @[package.scala:45:27] assign priv_rw_ok_lo_hi_1 = _GEN_33; // @[package.scala:45:27] wire [1:0] priv_x_ok_lo_hi; // @[package.scala:45:27] assign priv_x_ok_lo_hi = _GEN_33; // @[package.scala:45:27] wire [1:0] priv_x_ok_lo_hi_1; // @[package.scala:45:27] assign priv_x_ok_lo_hi_1 = _GEN_33; // @[package.scala:45:27] wire [2:0] priv_rw_ok_lo = {priv_rw_ok_lo_hi, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_34 = {_entries_barrier_5_io_y_u, _entries_barrier_4_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] priv_rw_ok_hi_hi; // @[package.scala:45:27] assign priv_rw_ok_hi_hi = _GEN_34; // @[package.scala:45:27] wire [1:0] priv_rw_ok_hi_hi_1; // @[package.scala:45:27] assign priv_rw_ok_hi_hi_1 = _GEN_34; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_hi; // @[package.scala:45:27] assign priv_x_ok_hi_hi = _GEN_34; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_hi_1; // @[package.scala:45:27] assign priv_x_ok_hi_hi_1 = _GEN_34; // @[package.scala:45:27] wire [2:0] priv_rw_ok_hi = {priv_rw_ok_hi_hi, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] _priv_rw_ok_T_2 = {priv_rw_ok_hi, priv_rw_ok_lo}; // @[package.scala:45:27] wire [5:0] _priv_rw_ok_T_3 = _priv_rw_ok_T_2; // @[package.scala:45:27] wire [5:0] priv_rw_ok = _priv_rw_ok_T_3; // @[TLB.scala:513:{23,70}] wire [2:0] priv_rw_ok_lo_1 = {priv_rw_ok_lo_hi_1, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] priv_rw_ok_hi_1 = {priv_rw_ok_hi_hi_1, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] _priv_rw_ok_T_4 = {priv_rw_ok_hi_1, priv_rw_ok_lo_1}; // @[package.scala:45:27] wire [5:0] _priv_rw_ok_T_5 = ~_priv_rw_ok_T_4; // @[package.scala:45:27] wire [2:0] priv_x_ok_lo = {priv_x_ok_lo_hi, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] priv_x_ok_hi = {priv_x_ok_hi_hi, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] _priv_x_ok_T = {priv_x_ok_hi, priv_x_ok_lo}; // @[package.scala:45:27] wire [5:0] _priv_x_ok_T_1 = ~_priv_x_ok_T; // @[package.scala:45:27] wire [2:0] priv_x_ok_lo_1 = {priv_x_ok_lo_hi_1, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] priv_x_ok_hi_1 = {priv_x_ok_hi_hi_1, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] _priv_x_ok_T_2 = {priv_x_ok_hi_1, priv_x_ok_lo_1}; // @[package.scala:45:27] wire [5:0] priv_x_ok = _priv_x_ok_T_2; // @[package.scala:45:27] wire _stage1_bypass_T_1 = ~stage1_en; // @[TLB.scala:374:29, :517:83] wire [5:0] _stage1_bypass_T_2 = {6{_stage1_bypass_T_1}}; // @[TLB.scala:517:{68,83}] wire [1:0] stage1_bypass_lo_hi = {_entries_barrier_2_io_y_ae_stage2, _entries_barrier_1_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [2:0] stage1_bypass_lo = {stage1_bypass_lo_hi, _entries_barrier_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [1:0] stage1_bypass_hi_hi = {_entries_barrier_5_io_y_ae_stage2, _entries_barrier_4_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [2:0] stage1_bypass_hi = {stage1_bypass_hi_hi, _entries_barrier_3_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [5:0] _stage1_bypass_T_3 = {stage1_bypass_hi, stage1_bypass_lo}; // @[package.scala:45:27] wire [5:0] _stage1_bypass_T_4 = _stage1_bypass_T_2 | _stage1_bypass_T_3; // @[package.scala:45:27] wire [1:0] r_array_lo_hi = {_entries_barrier_2_io_y_sr, _entries_barrier_1_io_y_sr}; // @[package.scala:45:27, :267:25] wire [2:0] r_array_lo = {r_array_lo_hi, _entries_barrier_io_y_sr}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_hi_hi = {_entries_barrier_5_io_y_sr, _entries_barrier_4_io_y_sr}; // @[package.scala:45:27, :267:25] wire [2:0] r_array_hi = {r_array_hi_hi, _entries_barrier_3_io_y_sr}; // @[package.scala:45:27, :267:25] wire [5:0] _r_array_T = {r_array_hi, r_array_lo}; // @[package.scala:45:27] wire [1:0] _GEN_35 = {_entries_barrier_2_io_y_sx, _entries_barrier_1_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_lo_hi_1; // @[package.scala:45:27] assign r_array_lo_hi_1 = _GEN_35; // @[package.scala:45:27] wire [1:0] x_array_lo_hi; // @[package.scala:45:27] assign x_array_lo_hi = _GEN_35; // @[package.scala:45:27] wire [2:0] r_array_lo_1 = {r_array_lo_hi_1, _entries_barrier_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_36 = {_entries_barrier_5_io_y_sx, _entries_barrier_4_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_hi_hi_1; // @[package.scala:45:27] assign r_array_hi_hi_1 = _GEN_36; // @[package.scala:45:27] wire [1:0] x_array_hi_hi; // @[package.scala:45:27] assign x_array_hi_hi = _GEN_36; // @[package.scala:45:27] wire [2:0] r_array_hi_1 = {r_array_hi_hi_1, _entries_barrier_3_io_y_sx}; // @[package.scala:45:27, :267:25] wire [5:0] _r_array_T_1 = {r_array_hi_1, r_array_lo_1}; // @[package.scala:45:27] wire [5:0] _r_array_T_2 = mxr ? _r_array_T_1 : 6'h0; // @[package.scala:45:27] wire [5:0] _r_array_T_3 = _r_array_T | _r_array_T_2; // @[package.scala:45:27] wire [5:0] _r_array_T_4 = priv_rw_ok & _r_array_T_3; // @[TLB.scala:513:70, :520:{41,69}] wire [5:0] _r_array_T_5 = _r_array_T_4; // @[TLB.scala:520:{41,113}] wire [6:0] r_array = {1'h1, _r_array_T_5}; // @[TLB.scala:520:{20,113}] wire [6:0] _pf_ld_array_T = r_array; // @[TLB.scala:520:20, :597:41] wire [1:0] w_array_lo_hi = {_entries_barrier_2_io_y_sw, _entries_barrier_1_io_y_sw}; // @[package.scala:45:27, :267:25] wire [2:0] w_array_lo = {w_array_lo_hi, _entries_barrier_io_y_sw}; // @[package.scala:45:27, :267:25] wire [1:0] w_array_hi_hi = {_entries_barrier_5_io_y_sw, _entries_barrier_4_io_y_sw}; // @[package.scala:45:27, :267:25] wire [2:0] w_array_hi = {w_array_hi_hi, _entries_barrier_3_io_y_sw}; // @[package.scala:45:27, :267:25] wire [5:0] _w_array_T = {w_array_hi, w_array_lo}; // @[package.scala:45:27] wire [5:0] _w_array_T_1 = priv_rw_ok & _w_array_T; // @[package.scala:45:27] wire [5:0] _w_array_T_2 = _w_array_T_1; // @[TLB.scala:521:{41,69}] wire [6:0] w_array = {1'h1, _w_array_T_2}; // @[TLB.scala:521:{20,69}] wire [2:0] x_array_lo = {x_array_lo_hi, _entries_barrier_io_y_sx}; // @[package.scala:45:27, :267:25] wire [2:0] x_array_hi = {x_array_hi_hi, _entries_barrier_3_io_y_sx}; // @[package.scala:45:27, :267:25] wire [5:0] _x_array_T = {x_array_hi, x_array_lo}; // @[package.scala:45:27] wire [5:0] _x_array_T_1 = priv_x_ok & _x_array_T; // @[package.scala:45:27] wire [5:0] _x_array_T_2 = _x_array_T_1; // @[TLB.scala:522:{40,68}] wire [6:0] x_array = {1'h1, _x_array_T_2}; // @[TLB.scala:522:{20,68}] wire [1:0] hr_array_lo_hi = {_entries_barrier_2_io_y_hr, _entries_barrier_1_io_y_hr}; // @[package.scala:45:27, :267:25] wire [2:0] hr_array_lo = {hr_array_lo_hi, _entries_barrier_io_y_hr}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_hi_hi = {_entries_barrier_5_io_y_hr, _entries_barrier_4_io_y_hr}; // @[package.scala:45:27, :267:25] wire [2:0] hr_array_hi = {hr_array_hi_hi, _entries_barrier_3_io_y_hr}; // @[package.scala:45:27, :267:25] wire [5:0] _hr_array_T = {hr_array_hi, hr_array_lo}; // @[package.scala:45:27] wire [1:0] _GEN_37 = {_entries_barrier_2_io_y_hx, _entries_barrier_1_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_lo_hi_1; // @[package.scala:45:27] assign hr_array_lo_hi_1 = _GEN_37; // @[package.scala:45:27] wire [1:0] hx_array_lo_hi; // @[package.scala:45:27] assign hx_array_lo_hi = _GEN_37; // @[package.scala:45:27] wire [2:0] hr_array_lo_1 = {hr_array_lo_hi_1, _entries_barrier_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_38 = {_entries_barrier_5_io_y_hx, _entries_barrier_4_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_hi_hi_1; // @[package.scala:45:27] assign hr_array_hi_hi_1 = _GEN_38; // @[package.scala:45:27] wire [1:0] hx_array_hi_hi; // @[package.scala:45:27] assign hx_array_hi_hi = _GEN_38; // @[package.scala:45:27] wire [2:0] hr_array_hi_1 = {hr_array_hi_hi_1, _entries_barrier_3_io_y_hx}; // @[package.scala:45:27, :267:25] wire [5:0] _hr_array_T_1 = {hr_array_hi_1, hr_array_lo_1}; // @[package.scala:45:27] wire [5:0] _hr_array_T_2 = io_ptw_status_mxr_0 ? _hr_array_T_1 : 6'h0; // @[package.scala:45:27] wire [5:0] _hr_array_T_3 = _hr_array_T | _hr_array_T_2; // @[package.scala:45:27] wire [1:0] hw_array_lo_hi = {_entries_barrier_2_io_y_hw, _entries_barrier_1_io_y_hw}; // @[package.scala:45:27, :267:25] wire [2:0] hw_array_lo = {hw_array_lo_hi, _entries_barrier_io_y_hw}; // @[package.scala:45:27, :267:25] wire [1:0] hw_array_hi_hi = {_entries_barrier_5_io_y_hw, _entries_barrier_4_io_y_hw}; // @[package.scala:45:27, :267:25] wire [2:0] hw_array_hi = {hw_array_hi_hi, _entries_barrier_3_io_y_hw}; // @[package.scala:45:27, :267:25] wire [5:0] _hw_array_T = {hw_array_hi, hw_array_lo}; // @[package.scala:45:27] wire [2:0] hx_array_lo = {hx_array_lo_hi, _entries_barrier_io_y_hx}; // @[package.scala:45:27, :267:25] wire [2:0] hx_array_hi = {hx_array_hi_hi, _entries_barrier_3_io_y_hx}; // @[package.scala:45:27, :267:25] wire [5:0] _hx_array_T = {hx_array_hi, hx_array_lo}; // @[package.scala:45:27] wire [1:0] _pr_array_T = {2{prot_r}}; // @[TLB.scala:429:55, :529:26] wire [1:0] pr_array_lo = {_entries_barrier_1_io_y_pr, _entries_barrier_io_y_pr}; // @[package.scala:45:27, :267:25] wire [1:0] pr_array_hi_hi = {_entries_barrier_4_io_y_pr, _entries_barrier_3_io_y_pr}; // @[package.scala:45:27, :267:25] wire [2:0] pr_array_hi = {pr_array_hi_hi, _entries_barrier_2_io_y_pr}; // @[package.scala:45:27, :267:25] wire [4:0] _pr_array_T_1 = {pr_array_hi, pr_array_lo}; // @[package.scala:45:27] wire [6:0] _pr_array_T_2 = {_pr_array_T, _pr_array_T_1}; // @[package.scala:45:27] wire [6:0] _GEN_39 = ptw_ae_array | final_ae_array; // @[TLB.scala:506:25, :507:27, :529:104] wire [6:0] _pr_array_T_3; // @[TLB.scala:529:104] assign _pr_array_T_3 = _GEN_39; // @[TLB.scala:529:104] wire [6:0] _pw_array_T_3; // @[TLB.scala:531:104] assign _pw_array_T_3 = _GEN_39; // @[TLB.scala:529:104, :531:104] wire [6:0] _px_array_T_3; // @[TLB.scala:533:104] assign _px_array_T_3 = _GEN_39; // @[TLB.scala:529:104, :533:104] wire [6:0] _pr_array_T_4 = ~_pr_array_T_3; // @[TLB.scala:529:{89,104}] wire [6:0] pr_array = _pr_array_T_2 & _pr_array_T_4; // @[TLB.scala:529:{21,87,89}] wire [1:0] _pw_array_T = {2{prot_w}}; // @[TLB.scala:430:55, :531:26] wire [1:0] pw_array_lo = {_entries_barrier_1_io_y_pw, _entries_barrier_io_y_pw}; // @[package.scala:45:27, :267:25] wire [1:0] pw_array_hi_hi = {_entries_barrier_4_io_y_pw, _entries_barrier_3_io_y_pw}; // @[package.scala:45:27, :267:25] wire [2:0] pw_array_hi = {pw_array_hi_hi, _entries_barrier_2_io_y_pw}; // @[package.scala:45:27, :267:25] wire [4:0] _pw_array_T_1 = {pw_array_hi, pw_array_lo}; // @[package.scala:45:27] wire [6:0] _pw_array_T_2 = {_pw_array_T, _pw_array_T_1}; // @[package.scala:45:27] wire [6:0] _pw_array_T_4 = ~_pw_array_T_3; // @[TLB.scala:531:{89,104}] wire [6:0] pw_array = _pw_array_T_2 & _pw_array_T_4; // @[TLB.scala:531:{21,87,89}] wire [1:0] _px_array_T = {2{prot_x}}; // @[TLB.scala:434:55, :533:26] wire [1:0] px_array_lo = {_entries_barrier_1_io_y_px, _entries_barrier_io_y_px}; // @[package.scala:45:27, :267:25] wire [1:0] px_array_hi_hi = {_entries_barrier_4_io_y_px, _entries_barrier_3_io_y_px}; // @[package.scala:45:27, :267:25] wire [2:0] px_array_hi = {px_array_hi_hi, _entries_barrier_2_io_y_px}; // @[package.scala:45:27, :267:25] wire [4:0] _px_array_T_1 = {px_array_hi, px_array_lo}; // @[package.scala:45:27] wire [6:0] _px_array_T_2 = {_px_array_T, _px_array_T_1}; // @[package.scala:45:27] wire [6:0] _px_array_T_4 = ~_px_array_T_3; // @[TLB.scala:533:{89,104}] wire [6:0] px_array = _px_array_T_2 & _px_array_T_4; // @[TLB.scala:533:{21,87,89}] wire [1:0] _eff_array_T = {2{_pma_io_resp_eff}}; // @[TLB.scala:422:19, :535:27] wire [1:0] eff_array_lo = {_entries_barrier_1_io_y_eff, _entries_barrier_io_y_eff}; // @[package.scala:45:27, :267:25] wire [1:0] eff_array_hi_hi = {_entries_barrier_4_io_y_eff, _entries_barrier_3_io_y_eff}; // @[package.scala:45:27, :267:25] wire [2:0] eff_array_hi = {eff_array_hi_hi, _entries_barrier_2_io_y_eff}; // @[package.scala:45:27, :267:25] wire [4:0] _eff_array_T_1 = {eff_array_hi, eff_array_lo}; // @[package.scala:45:27] wire [6:0] eff_array = {_eff_array_T, _eff_array_T_1}; // @[package.scala:45:27] wire [1:0] _c_array_T = {2{cacheable}}; // @[TLB.scala:425:41, :537:25] wire [1:0] _GEN_40 = {_entries_barrier_1_io_y_c, _entries_barrier_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] c_array_lo; // @[package.scala:45:27] assign c_array_lo = _GEN_40; // @[package.scala:45:27] wire [1:0] prefetchable_array_lo; // @[package.scala:45:27] assign prefetchable_array_lo = _GEN_40; // @[package.scala:45:27] wire [1:0] _GEN_41 = {_entries_barrier_4_io_y_c, _entries_barrier_3_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] c_array_hi_hi; // @[package.scala:45:27] assign c_array_hi_hi = _GEN_41; // @[package.scala:45:27] wire [1:0] prefetchable_array_hi_hi; // @[package.scala:45:27] assign prefetchable_array_hi_hi = _GEN_41; // @[package.scala:45:27] wire [2:0] c_array_hi = {c_array_hi_hi, _entries_barrier_2_io_y_c}; // @[package.scala:45:27, :267:25] wire [4:0] _c_array_T_1 = {c_array_hi, c_array_lo}; // @[package.scala:45:27] wire [6:0] c_array = {_c_array_T, _c_array_T_1}; // @[package.scala:45:27] wire [6:0] lrscAllowed = c_array; // @[TLB.scala:537:20, :580:24] wire [1:0] _ppp_array_T = {2{_pma_io_resp_pp}}; // @[TLB.scala:422:19, :539:27] wire [1:0] ppp_array_lo = {_entries_barrier_1_io_y_ppp, _entries_barrier_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [1:0] ppp_array_hi_hi = {_entries_barrier_4_io_y_ppp, _entries_barrier_3_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [2:0] ppp_array_hi = {ppp_array_hi_hi, _entries_barrier_2_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [4:0] _ppp_array_T_1 = {ppp_array_hi, ppp_array_lo}; // @[package.scala:45:27] wire [6:0] ppp_array = {_ppp_array_T, _ppp_array_T_1}; // @[package.scala:45:27] wire [1:0] _paa_array_T = {2{_pma_io_resp_aa}}; // @[TLB.scala:422:19, :541:27] wire [1:0] paa_array_lo = {_entries_barrier_1_io_y_paa, _entries_barrier_io_y_paa}; // @[package.scala:45:27, :267:25] wire [1:0] paa_array_hi_hi = {_entries_barrier_4_io_y_paa, _entries_barrier_3_io_y_paa}; // @[package.scala:45:27, :267:25] wire [2:0] paa_array_hi = {paa_array_hi_hi, _entries_barrier_2_io_y_paa}; // @[package.scala:45:27, :267:25] wire [4:0] _paa_array_T_1 = {paa_array_hi, paa_array_lo}; // @[package.scala:45:27] wire [6:0] paa_array = {_paa_array_T, _paa_array_T_1}; // @[package.scala:45:27] wire [1:0] _pal_array_T = {2{_pma_io_resp_al}}; // @[TLB.scala:422:19, :543:27] wire [1:0] pal_array_lo = {_entries_barrier_1_io_y_pal, _entries_barrier_io_y_pal}; // @[package.scala:45:27, :267:25] wire [1:0] pal_array_hi_hi = {_entries_barrier_4_io_y_pal, _entries_barrier_3_io_y_pal}; // @[package.scala:45:27, :267:25] wire [2:0] pal_array_hi = {pal_array_hi_hi, _entries_barrier_2_io_y_pal}; // @[package.scala:45:27, :267:25] wire [4:0] _pal_array_T_1 = {pal_array_hi, pal_array_lo}; // @[package.scala:45:27] wire [6:0] pal_array = {_pal_array_T, _pal_array_T_1}; // @[package.scala:45:27] wire [6:0] ppp_array_if_cached = ppp_array | c_array; // @[TLB.scala:537:20, :539:22, :544:39] wire [6:0] paa_array_if_cached = paa_array | c_array; // @[TLB.scala:537:20, :541:22, :545:39] wire [6:0] pal_array_if_cached = pal_array | c_array; // @[TLB.scala:537:20, :543:22, :546:39] wire _prefetchable_array_T = cacheable & homogeneous; // @[TLBPermissions.scala:101:65] wire [1:0] _prefetchable_array_T_1 = {_prefetchable_array_T, 1'h0}; // @[TLB.scala:547:{43,59}] wire [2:0] prefetchable_array_hi = {prefetchable_array_hi_hi, _entries_barrier_2_io_y_c}; // @[package.scala:45:27, :267:25] wire [4:0] _prefetchable_array_T_2 = {prefetchable_array_hi, prefetchable_array_lo}; // @[package.scala:45:27] wire [6:0] prefetchable_array = {_prefetchable_array_T_1, _prefetchable_array_T_2}; // @[package.scala:45:27] wire [3:0] _misaligned_T = 4'h1 << io_req_bits_size_0; // @[OneHot.scala:58:35] wire [4:0] _misaligned_T_1 = {1'h0, _misaligned_T} - 5'h1; // @[OneHot.scala:58:35] wire [3:0] _misaligned_T_2 = _misaligned_T_1[3:0]; // @[TLB.scala:550:69] wire [39:0] _misaligned_T_3 = {36'h0, io_req_bits_vaddr_0[3:0] & _misaligned_T_2}; // @[TLB.scala:318:7, :550:{39,69}] wire misaligned = |_misaligned_T_3; // @[TLB.scala:550:{39,77}] wire _bad_va_T = vm_enabled & stage1_en; // @[TLB.scala:374:29, :399:61, :568:21] wire [39:0] bad_va_maskedVAddr = io_req_bits_vaddr_0 & 40'hC000000000; // @[TLB.scala:318:7, :559:43] wire _bad_va_T_2 = bad_va_maskedVAddr == 40'h0; // @[TLB.scala:550:77, :559:43, :560:51] wire _bad_va_T_3 = bad_va_maskedVAddr == 40'hC000000000; // @[TLB.scala:559:43, :560:86] wire _bad_va_T_4 = _bad_va_T_3; // @[TLB.scala:560:{71,86}] wire _bad_va_T_5 = _bad_va_T_2 | _bad_va_T_4; // @[TLB.scala:560:{51,59,71}] wire _bad_va_T_6 = ~_bad_va_T_5; // @[TLB.scala:560:{37,59}] wire _bad_va_T_7 = _bad_va_T_6; // @[TLB.scala:560:{34,37}] wire bad_va = _bad_va_T & _bad_va_T_7; // @[TLB.scala:560:34, :568:{21,34}] wire _GEN_42 = io_req_bits_cmd_0 == 5'h6; // @[package.scala:16:47] wire _cmd_lrsc_T; // @[package.scala:16:47] assign _cmd_lrsc_T = _GEN_42; // @[package.scala:16:47] wire _cmd_read_T_2; // @[package.scala:16:47] assign _cmd_read_T_2 = _GEN_42; // @[package.scala:16:47] wire _GEN_43 = io_req_bits_cmd_0 == 5'h7; // @[package.scala:16:47] wire _cmd_lrsc_T_1; // @[package.scala:16:47] assign _cmd_lrsc_T_1 = _GEN_43; // @[package.scala:16:47] wire _cmd_read_T_3; // @[package.scala:16:47] assign _cmd_read_T_3 = _GEN_43; // @[package.scala:16:47] wire _cmd_write_T_3; // @[Consts.scala:90:66] assign _cmd_write_T_3 = _GEN_43; // @[package.scala:16:47] wire _cmd_lrsc_T_2 = _cmd_lrsc_T | _cmd_lrsc_T_1; // @[package.scala:16:47, :81:59] wire cmd_lrsc = _cmd_lrsc_T_2; // @[package.scala:81:59] wire _GEN_44 = io_req_bits_cmd_0 == 5'h4; // @[package.scala:16:47] wire _cmd_amo_logical_T; // @[package.scala:16:47] assign _cmd_amo_logical_T = _GEN_44; // @[package.scala:16:47] wire _cmd_read_T_7; // @[package.scala:16:47] assign _cmd_read_T_7 = _GEN_44; // @[package.scala:16:47] wire _cmd_write_T_5; // @[package.scala:16:47] assign _cmd_write_T_5 = _GEN_44; // @[package.scala:16:47] wire _GEN_45 = io_req_bits_cmd_0 == 5'h9; // @[package.scala:16:47] wire _cmd_amo_logical_T_1; // @[package.scala:16:47] assign _cmd_amo_logical_T_1 = _GEN_45; // @[package.scala:16:47] wire _cmd_read_T_8; // @[package.scala:16:47] assign _cmd_read_T_8 = _GEN_45; // @[package.scala:16:47] wire _cmd_write_T_6; // @[package.scala:16:47] assign _cmd_write_T_6 = _GEN_45; // @[package.scala:16:47] wire _GEN_46 = io_req_bits_cmd_0 == 5'hA; // @[package.scala:16:47] wire _cmd_amo_logical_T_2; // @[package.scala:16:47] assign _cmd_amo_logical_T_2 = _GEN_46; // @[package.scala:16:47] wire _cmd_read_T_9; // @[package.scala:16:47] assign _cmd_read_T_9 = _GEN_46; // @[package.scala:16:47] wire _cmd_write_T_7; // @[package.scala:16:47] assign _cmd_write_T_7 = _GEN_46; // @[package.scala:16:47] wire _GEN_47 = io_req_bits_cmd_0 == 5'hB; // @[package.scala:16:47] wire _cmd_amo_logical_T_3; // @[package.scala:16:47] assign _cmd_amo_logical_T_3 = _GEN_47; // @[package.scala:16:47] wire _cmd_read_T_10; // @[package.scala:16:47] assign _cmd_read_T_10 = _GEN_47; // @[package.scala:16:47] wire _cmd_write_T_8; // @[package.scala:16:47] assign _cmd_write_T_8 = _GEN_47; // @[package.scala:16:47] wire _cmd_amo_logical_T_4 = _cmd_amo_logical_T | _cmd_amo_logical_T_1; // @[package.scala:16:47, :81:59] wire _cmd_amo_logical_T_5 = _cmd_amo_logical_T_4 | _cmd_amo_logical_T_2; // @[package.scala:16:47, :81:59] wire _cmd_amo_logical_T_6 = _cmd_amo_logical_T_5 | _cmd_amo_logical_T_3; // @[package.scala:16:47, :81:59] wire cmd_amo_logical = _cmd_amo_logical_T_6; // @[package.scala:81:59] wire _GEN_48 = io_req_bits_cmd_0 == 5'h8; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T = _GEN_48; // @[package.scala:16:47] wire _cmd_read_T_14; // @[package.scala:16:47] assign _cmd_read_T_14 = _GEN_48; // @[package.scala:16:47] wire _cmd_write_T_12; // @[package.scala:16:47] assign _cmd_write_T_12 = _GEN_48; // @[package.scala:16:47] wire _GEN_49 = io_req_bits_cmd_0 == 5'hC; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_1; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T_1 = _GEN_49; // @[package.scala:16:47] wire _cmd_read_T_15; // @[package.scala:16:47] assign _cmd_read_T_15 = _GEN_49; // @[package.scala:16:47] wire _cmd_write_T_13; // @[package.scala:16:47] assign _cmd_write_T_13 = _GEN_49; // @[package.scala:16:47] wire _GEN_50 = io_req_bits_cmd_0 == 5'hD; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_2; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T_2 = _GEN_50; // @[package.scala:16:47] wire _cmd_read_T_16; // @[package.scala:16:47] assign _cmd_read_T_16 = _GEN_50; // @[package.scala:16:47] wire _cmd_write_T_14; // @[package.scala:16:47] assign _cmd_write_T_14 = _GEN_50; // @[package.scala:16:47] wire _GEN_51 = io_req_bits_cmd_0 == 5'hE; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_3; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T_3 = _GEN_51; // @[package.scala:16:47] wire _cmd_read_T_17; // @[package.scala:16:47] assign _cmd_read_T_17 = _GEN_51; // @[package.scala:16:47] wire _cmd_write_T_15; // @[package.scala:16:47] assign _cmd_write_T_15 = _GEN_51; // @[package.scala:16:47] wire _GEN_52 = io_req_bits_cmd_0 == 5'hF; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_4; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T_4 = _GEN_52; // @[package.scala:16:47] wire _cmd_read_T_18; // @[package.scala:16:47] assign _cmd_read_T_18 = _GEN_52; // @[package.scala:16:47] wire _cmd_write_T_16; // @[package.scala:16:47] assign _cmd_write_T_16 = _GEN_52; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_5 = _cmd_amo_arithmetic_T | _cmd_amo_arithmetic_T_1; // @[package.scala:16:47, :81:59] wire _cmd_amo_arithmetic_T_6 = _cmd_amo_arithmetic_T_5 | _cmd_amo_arithmetic_T_2; // @[package.scala:16:47, :81:59] wire _cmd_amo_arithmetic_T_7 = _cmd_amo_arithmetic_T_6 | _cmd_amo_arithmetic_T_3; // @[package.scala:16:47, :81:59] wire _cmd_amo_arithmetic_T_8 = _cmd_amo_arithmetic_T_7 | _cmd_amo_arithmetic_T_4; // @[package.scala:16:47, :81:59] wire cmd_amo_arithmetic = _cmd_amo_arithmetic_T_8; // @[package.scala:81:59] wire _GEN_53 = io_req_bits_cmd_0 == 5'h11; // @[TLB.scala:318:7, :573:41] wire cmd_put_partial; // @[TLB.scala:573:41] assign cmd_put_partial = _GEN_53; // @[TLB.scala:573:41] wire _cmd_write_T_1; // @[Consts.scala:90:49] assign _cmd_write_T_1 = _GEN_53; // @[TLB.scala:573:41] wire _cmd_read_T = io_req_bits_cmd_0 == 5'h0; // @[package.scala:16:47] wire _GEN_54 = io_req_bits_cmd_0 == 5'h10; // @[package.scala:16:47] wire _cmd_read_T_1; // @[package.scala:16:47] assign _cmd_read_T_1 = _GEN_54; // @[package.scala:16:47] wire _cmd_readx_T; // @[TLB.scala:575:56] assign _cmd_readx_T = _GEN_54; // @[package.scala:16:47] wire _cmd_read_T_4 = _cmd_read_T | _cmd_read_T_1; // @[package.scala:16:47, :81:59] wire _cmd_read_T_5 = _cmd_read_T_4 | _cmd_read_T_2; // @[package.scala:16:47, :81:59] wire _cmd_read_T_6 = _cmd_read_T_5 | _cmd_read_T_3; // @[package.scala:16:47, :81:59] wire _cmd_read_T_11 = _cmd_read_T_7 | _cmd_read_T_8; // @[package.scala:16:47, :81:59] wire _cmd_read_T_12 = _cmd_read_T_11 | _cmd_read_T_9; // @[package.scala:16:47, :81:59] wire _cmd_read_T_13 = _cmd_read_T_12 | _cmd_read_T_10; // @[package.scala:16:47, :81:59] wire _cmd_read_T_19 = _cmd_read_T_14 | _cmd_read_T_15; // @[package.scala:16:47, :81:59] wire _cmd_read_T_20 = _cmd_read_T_19 | _cmd_read_T_16; // @[package.scala:16:47, :81:59] wire _cmd_read_T_21 = _cmd_read_T_20 | _cmd_read_T_17; // @[package.scala:16:47, :81:59] wire _cmd_read_T_22 = _cmd_read_T_21 | _cmd_read_T_18; // @[package.scala:16:47, :81:59] wire _cmd_read_T_23 = _cmd_read_T_13 | _cmd_read_T_22; // @[package.scala:81:59] wire cmd_read = _cmd_read_T_6 | _cmd_read_T_23; // @[package.scala:81:59] wire _cmd_write_T = io_req_bits_cmd_0 == 5'h1; // @[TLB.scala:318:7] wire _cmd_write_T_2 = _cmd_write_T | _cmd_write_T_1; // @[Consts.scala:90:{32,42,49}] wire _cmd_write_T_4 = _cmd_write_T_2 | _cmd_write_T_3; // @[Consts.scala:90:{42,59,66}] wire _cmd_write_T_9 = _cmd_write_T_5 | _cmd_write_T_6; // @[package.scala:16:47, :81:59] wire _cmd_write_T_10 = _cmd_write_T_9 | _cmd_write_T_7; // @[package.scala:16:47, :81:59] wire _cmd_write_T_11 = _cmd_write_T_10 | _cmd_write_T_8; // @[package.scala:16:47, :81:59] wire _cmd_write_T_17 = _cmd_write_T_12 | _cmd_write_T_13; // @[package.scala:16:47, :81:59] wire _cmd_write_T_18 = _cmd_write_T_17 | _cmd_write_T_14; // @[package.scala:16:47, :81:59] wire _cmd_write_T_19 = _cmd_write_T_18 | _cmd_write_T_15; // @[package.scala:16:47, :81:59] wire _cmd_write_T_20 = _cmd_write_T_19 | _cmd_write_T_16; // @[package.scala:16:47, :81:59] wire _cmd_write_T_21 = _cmd_write_T_11 | _cmd_write_T_20; // @[package.scala:81:59] wire cmd_write = _cmd_write_T_4 | _cmd_write_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _cmd_write_perms_T = io_req_bits_cmd_0 == 5'h5; // @[package.scala:16:47] wire _cmd_write_perms_T_1 = io_req_bits_cmd_0 == 5'h17; // @[package.scala:16:47] wire _cmd_write_perms_T_2 = _cmd_write_perms_T | _cmd_write_perms_T_1; // @[package.scala:16:47, :81:59] wire cmd_write_perms = cmd_write | _cmd_write_perms_T_2; // @[package.scala:81:59] wire [6:0] _ae_array_T = misaligned ? eff_array : 7'h0; // @[TLB.scala:535:22, :550:77, :582:8] wire [6:0] _ae_array_T_1 = ~lrscAllowed; // @[TLB.scala:580:24, :583:19] wire [6:0] _ae_array_T_2 = cmd_lrsc ? _ae_array_T_1 : 7'h0; // @[TLB.scala:570:33, :583:{8,19}] wire [6:0] ae_array = _ae_array_T | _ae_array_T_2; // @[TLB.scala:582:{8,37}, :583:8] wire [6:0] _ae_ld_array_T = ~pr_array; // @[TLB.scala:529:87, :586:46] wire [6:0] _ae_ld_array_T_1 = ae_array | _ae_ld_array_T; // @[TLB.scala:582:37, :586:{44,46}] wire [6:0] ae_ld_array = cmd_read ? _ae_ld_array_T_1 : 7'h0; // @[TLB.scala:586:{24,44}] wire [6:0] _ae_st_array_T = ~pw_array; // @[TLB.scala:531:87, :588:37] wire [6:0] _ae_st_array_T_1 = ae_array | _ae_st_array_T; // @[TLB.scala:582:37, :588:{35,37}] wire [6:0] _ae_st_array_T_2 = cmd_write_perms ? _ae_st_array_T_1 : 7'h0; // @[TLB.scala:577:35, :588:{8,35}] wire [6:0] _ae_st_array_T_3 = ~ppp_array_if_cached; // @[TLB.scala:544:39, :589:26] wire [6:0] _ae_st_array_T_4 = cmd_put_partial ? _ae_st_array_T_3 : 7'h0; // @[TLB.scala:573:41, :589:{8,26}] wire [6:0] _ae_st_array_T_5 = _ae_st_array_T_2 | _ae_st_array_T_4; // @[TLB.scala:588:{8,53}, :589:8] wire [6:0] _ae_st_array_T_6 = ~pal_array_if_cached; // @[TLB.scala:546:39, :590:26] wire [6:0] _ae_st_array_T_7 = cmd_amo_logical ? _ae_st_array_T_6 : 7'h0; // @[TLB.scala:571:40, :590:{8,26}] wire [6:0] _ae_st_array_T_8 = _ae_st_array_T_5 | _ae_st_array_T_7; // @[TLB.scala:588:53, :589:53, :590:8] wire [6:0] _ae_st_array_T_9 = ~paa_array_if_cached; // @[TLB.scala:545:39, :591:29] wire [6:0] _ae_st_array_T_10 = cmd_amo_arithmetic ? _ae_st_array_T_9 : 7'h0; // @[TLB.scala:572:43, :591:{8,29}] wire [6:0] ae_st_array = _ae_st_array_T_8 | _ae_st_array_T_10; // @[TLB.scala:589:53, :590:53, :591:8] wire [6:0] _must_alloc_array_T = ~ppp_array; // @[TLB.scala:539:22, :593:26] wire [6:0] _must_alloc_array_T_1 = cmd_put_partial ? _must_alloc_array_T : 7'h0; // @[TLB.scala:573:41, :593:{8,26}] wire [6:0] _must_alloc_array_T_2 = ~pal_array; // @[TLB.scala:543:22, :594:26] wire [6:0] _must_alloc_array_T_3 = cmd_amo_logical ? _must_alloc_array_T_2 : 7'h0; // @[TLB.scala:571:40, :594:{8,26}] wire [6:0] _must_alloc_array_T_4 = _must_alloc_array_T_1 | _must_alloc_array_T_3; // @[TLB.scala:593:{8,43}, :594:8] wire [6:0] _must_alloc_array_T_5 = ~paa_array; // @[TLB.scala:541:22, :595:29] wire [6:0] _must_alloc_array_T_6 = cmd_amo_arithmetic ? _must_alloc_array_T_5 : 7'h0; // @[TLB.scala:572:43, :595:{8,29}] wire [6:0] _must_alloc_array_T_7 = _must_alloc_array_T_4 | _must_alloc_array_T_6; // @[TLB.scala:593:43, :594:43, :595:8] wire [6:0] _must_alloc_array_T_9 = {7{cmd_lrsc}}; // @[TLB.scala:570:33, :596:8] wire [6:0] must_alloc_array = _must_alloc_array_T_7 | _must_alloc_array_T_9; // @[TLB.scala:594:43, :595:46, :596:8] wire [6:0] _pf_ld_array_T_1 = ~_pf_ld_array_T; // @[TLB.scala:597:{37,41}] wire [6:0] _pf_ld_array_T_2 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73] wire [6:0] _pf_ld_array_T_3 = _pf_ld_array_T_1 & _pf_ld_array_T_2; // @[TLB.scala:597:{37,71,73}] wire [6:0] _pf_ld_array_T_4 = _pf_ld_array_T_3 | ptw_pf_array; // @[TLB.scala:508:25, :597:{71,88}] wire [6:0] _pf_ld_array_T_5 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106] wire [6:0] _pf_ld_array_T_6 = _pf_ld_array_T_4 & _pf_ld_array_T_5; // @[TLB.scala:597:{88,104,106}] wire [6:0] pf_ld_array = cmd_read ? _pf_ld_array_T_6 : 7'h0; // @[TLB.scala:597:{24,104}] wire [6:0] _pf_st_array_T = ~w_array; // @[TLB.scala:521:20, :598:44] wire [6:0] _pf_st_array_T_1 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :598:55] wire [6:0] _pf_st_array_T_2 = _pf_st_array_T & _pf_st_array_T_1; // @[TLB.scala:598:{44,53,55}] wire [6:0] _pf_st_array_T_3 = _pf_st_array_T_2 | ptw_pf_array; // @[TLB.scala:508:25, :598:{53,70}] wire [6:0] _pf_st_array_T_4 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106, :598:88] wire [6:0] _pf_st_array_T_5 = _pf_st_array_T_3 & _pf_st_array_T_4; // @[TLB.scala:598:{70,86,88}] wire [6:0] pf_st_array = cmd_write_perms ? _pf_st_array_T_5 : 7'h0; // @[TLB.scala:577:35, :598:{24,86}] wire [6:0] _pf_inst_array_T = ~x_array; // @[TLB.scala:522:20, :599:25] wire [6:0] _pf_inst_array_T_1 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :599:36] wire [6:0] _pf_inst_array_T_2 = _pf_inst_array_T & _pf_inst_array_T_1; // @[TLB.scala:599:{25,34,36}] wire [6:0] _pf_inst_array_T_3 = _pf_inst_array_T_2 | ptw_pf_array; // @[TLB.scala:508:25, :599:{34,51}] wire [6:0] _pf_inst_array_T_4 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106, :599:69] wire [6:0] pf_inst_array = _pf_inst_array_T_3 & _pf_inst_array_T_4; // @[TLB.scala:599:{51,67,69}] wire [6:0] _gf_ld_array_T_4 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :600:100] wire [6:0] _gf_ld_array_T_5 = _gf_ld_array_T_3 & _gf_ld_array_T_4; // @[TLB.scala:600:{82,98,100}] wire [6:0] _gf_st_array_T_3 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :601:81] wire [6:0] _gf_st_array_T_4 = _gf_st_array_T_2 & _gf_st_array_T_3; // @[TLB.scala:601:{63,79,81}] wire [6:0] _gf_inst_array_T_2 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :602:64] wire [6:0] _gf_inst_array_T_3 = _gf_inst_array_T_1 & _gf_inst_array_T_2; // @[TLB.scala:602:{46,62,64}] wire _gpa_hits_hit_mask_T = r_gpa_vpn == vpn; // @[TLB.scala:335:30, :364:22, :606:73] wire _gpa_hits_hit_mask_T_1 = r_gpa_valid & _gpa_hits_hit_mask_T; // @[TLB.scala:362:24, :606:{60,73}] wire [4:0] _gpa_hits_hit_mask_T_2 = {5{_gpa_hits_hit_mask_T_1}}; // @[TLB.scala:606:{24,60}] wire tlb_hit_if_not_gpa_miss = |real_hits; // @[package.scala:45:27] wire tlb_hit = |_tlb_hit_T; // @[TLB.scala:611:{28,40}] wire _tlb_miss_T_2 = ~bad_va; // @[TLB.scala:568:34, :613:56] wire _tlb_miss_T_3 = _tlb_miss_T_1 & _tlb_miss_T_2; // @[TLB.scala:613:{29,53,56}] wire _tlb_miss_T_4 = ~tlb_hit; // @[TLB.scala:611:40, :613:67] wire tlb_miss = _tlb_miss_T_3 & _tlb_miss_T_4; // @[TLB.scala:613:{53,64,67}] reg [2:0] state_vec_0; // @[Replacement.scala:305:17] reg [2:0] state_vec_1; // @[Replacement.scala:305:17] reg [2:0] state_vec_2; // @[Replacement.scala:305:17] reg [2:0] state_vec_3; // @[Replacement.scala:305:17] wire [1:0] _GEN_55 = {sector_hits_1, sector_hits_0}; // @[OneHot.scala:21:45] wire [1:0] lo; // @[OneHot.scala:21:45] assign lo = _GEN_55; // @[OneHot.scala:21:45] wire [1:0] r_sectored_hit_bits_lo; // @[OneHot.scala:21:45] assign r_sectored_hit_bits_lo = _GEN_55; // @[OneHot.scala:21:45] wire [1:0] lo_1 = lo; // @[OneHot.scala:21:45, :31:18] wire [1:0] _GEN_56 = {sector_hits_3, sector_hits_2}; // @[OneHot.scala:21:45] wire [1:0] hi; // @[OneHot.scala:21:45] assign hi = _GEN_56; // @[OneHot.scala:21:45] wire [1:0] r_sectored_hit_bits_hi; // @[OneHot.scala:21:45] assign r_sectored_hit_bits_hi = _GEN_56; // @[OneHot.scala:21:45] wire [1:0] hi_1 = hi; // @[OneHot.scala:21:45, :30:18] wire [1:0] state_vec_touch_way_sized = {|hi_1, hi_1[1] | lo_1[1]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}] wire _state_vec_set_left_older_T = state_vec_touch_way_sized[1]; // @[package.scala:163:13] wire state_vec_set_left_older = ~_state_vec_set_left_older_T; // @[Replacement.scala:196:{33,43}] wire [3:0][2:0] _GEN_57 = {{state_vec_3}, {state_vec_2}, {state_vec_1}, {state_vec_0}}; // @[package.scala:163:13] wire state_vec_left_subtree_state = _GEN_57[memIdx][1]; // @[package.scala:163:13] wire r_sectored_repl_addr_left_subtree_state = _GEN_57[memIdx][1]; // @[package.scala:163:13] wire state_vec_right_subtree_state = _GEN_57[memIdx][0]; // @[package.scala:163:13] wire r_sectored_repl_addr_right_subtree_state = _GEN_57[memIdx][0]; // @[package.scala:163:13] wire _state_vec_T = state_vec_touch_way_sized[0]; // @[package.scala:163:13] wire _state_vec_T_4 = state_vec_touch_way_sized[0]; // @[package.scala:163:13] wire _state_vec_T_1 = _state_vec_T; // @[package.scala:163:13] wire _state_vec_T_2 = ~_state_vec_T_1; // @[Replacement.scala:218:{7,17}] wire _state_vec_T_3 = state_vec_set_left_older ? state_vec_left_subtree_state : _state_vec_T_2; // @[package.scala:163:13] wire _state_vec_T_5 = _state_vec_T_4; // @[Replacement.scala:207:62, :218:17] wire _state_vec_T_6 = ~_state_vec_T_5; // @[Replacement.scala:218:{7,17}] wire _state_vec_T_7 = state_vec_set_left_older ? _state_vec_T_6 : state_vec_right_subtree_state; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_vec_hi = {state_vec_set_left_older, _state_vec_T_3}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_vec_T_8 = {state_vec_hi, _state_vec_T_7}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _multipleHits_T = real_hits[2:0]; // @[package.scala:45:27] wire _multipleHits_T_1 = _multipleHits_T[0]; // @[Misc.scala:181:37] wire multipleHits_leftOne = _multipleHits_T_1; // @[Misc.scala:178:18, :181:37] wire [1:0] _multipleHits_T_2 = _multipleHits_T[2:1]; // @[Misc.scala:181:37, :182:39] wire _multipleHits_T_3 = _multipleHits_T_2[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_1 = _multipleHits_T_3; // @[Misc.scala:178:18, :181:37] wire _multipleHits_T_4 = _multipleHits_T_2[1]; // @[Misc.scala:182:39] wire multipleHits_rightOne = _multipleHits_T_4; // @[Misc.scala:178:18, :182:39] wire multipleHits_rightOne_1 = multipleHits_leftOne_1 | multipleHits_rightOne; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_6 = multipleHits_leftOne_1 & multipleHits_rightOne; // @[Misc.scala:178:18, :183:61] wire multipleHits_rightTwo = _multipleHits_T_6; // @[Misc.scala:183:{49,61}] wire _multipleHits_T_7 = multipleHits_rightTwo; // @[Misc.scala:183:{37,49}] wire multipleHits_leftOne_2 = multipleHits_leftOne | multipleHits_rightOne_1; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_8 = multipleHits_leftOne & multipleHits_rightOne_1; // @[Misc.scala:178:18, :183:{16,61}] wire multipleHits_leftTwo = _multipleHits_T_7 | _multipleHits_T_8; // @[Misc.scala:183:{37,49,61}] wire [2:0] _multipleHits_T_9 = real_hits[5:3]; // @[package.scala:45:27] wire _multipleHits_T_10 = _multipleHits_T_9[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_3 = _multipleHits_T_10; // @[Misc.scala:178:18, :181:37] wire [1:0] _multipleHits_T_11 = _multipleHits_T_9[2:1]; // @[Misc.scala:182:39] wire _multipleHits_T_12 = _multipleHits_T_11[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_4 = _multipleHits_T_12; // @[Misc.scala:178:18, :181:37] wire _multipleHits_T_13 = _multipleHits_T_11[1]; // @[Misc.scala:182:39] wire multipleHits_rightOne_2 = _multipleHits_T_13; // @[Misc.scala:178:18, :182:39] wire multipleHits_rightOne_3 = multipleHits_leftOne_4 | multipleHits_rightOne_2; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_15 = multipleHits_leftOne_4 & multipleHits_rightOne_2; // @[Misc.scala:178:18, :183:61] wire multipleHits_rightTwo_1 = _multipleHits_T_15; // @[Misc.scala:183:{49,61}] wire _multipleHits_T_16 = multipleHits_rightTwo_1; // @[Misc.scala:183:{37,49}] wire multipleHits_rightOne_4 = multipleHits_leftOne_3 | multipleHits_rightOne_3; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_17 = multipleHits_leftOne_3 & multipleHits_rightOne_3; // @[Misc.scala:178:18, :183:{16,61}] wire multipleHits_rightTwo_2 = _multipleHits_T_16 | _multipleHits_T_17; // @[Misc.scala:183:{37,49,61}] wire _multipleHits_T_18 = multipleHits_leftOne_2 | multipleHits_rightOne_4; // @[Misc.scala:183:16] wire _multipleHits_T_19 = multipleHits_leftTwo | multipleHits_rightTwo_2; // @[Misc.scala:183:{37,49}] wire _multipleHits_T_20 = multipleHits_leftOne_2 & multipleHits_rightOne_4; // @[Misc.scala:183:{16,61}] wire multipleHits = _multipleHits_T_19 | _multipleHits_T_20; // @[Misc.scala:183:{37,49,61}] assign _io_req_ready_T = state == 2'h0; // @[TLB.scala:352:22, :631:25] assign io_req_ready_0 = _io_req_ready_T; // @[TLB.scala:318:7, :631:25] wire _io_resp_pf_ld_T = bad_va & cmd_read; // @[TLB.scala:568:34, :633:28] wire [6:0] _io_resp_pf_ld_T_1 = pf_ld_array & hits; // @[TLB.scala:442:17, :597:24, :633:57] wire _io_resp_pf_ld_T_2 = |_io_resp_pf_ld_T_1; // @[TLB.scala:633:{57,65}] assign _io_resp_pf_ld_T_3 = _io_resp_pf_ld_T | _io_resp_pf_ld_T_2; // @[TLB.scala:633:{28,41,65}] assign io_resp_pf_ld = _io_resp_pf_ld_T_3; // @[TLB.scala:318:7, :633:41] wire _io_resp_pf_st_T = bad_va & cmd_write_perms; // @[TLB.scala:568:34, :577:35, :634:28] wire [6:0] _io_resp_pf_st_T_1 = pf_st_array & hits; // @[TLB.scala:442:17, :598:24, :634:64] wire _io_resp_pf_st_T_2 = |_io_resp_pf_st_T_1; // @[TLB.scala:634:{64,72}] assign _io_resp_pf_st_T_3 = _io_resp_pf_st_T | _io_resp_pf_st_T_2; // @[TLB.scala:634:{28,48,72}] assign io_resp_pf_st = _io_resp_pf_st_T_3; // @[TLB.scala:318:7, :634:48] wire [6:0] _io_resp_pf_inst_T = pf_inst_array & hits; // @[TLB.scala:442:17, :599:67, :635:47] wire _io_resp_pf_inst_T_1 = |_io_resp_pf_inst_T; // @[TLB.scala:635:{47,55}] assign _io_resp_pf_inst_T_2 = bad_va | _io_resp_pf_inst_T_1; // @[TLB.scala:568:34, :635:{29,55}] assign io_resp_pf_inst = _io_resp_pf_inst_T_2; // @[TLB.scala:318:7, :635:29] wire [6:0] _io_resp_ae_ld_T = ae_ld_array & hits; // @[TLB.scala:442:17, :586:24, :641:33] assign _io_resp_ae_ld_T_1 = |_io_resp_ae_ld_T; // @[TLB.scala:641:{33,41}] assign io_resp_ae_ld = _io_resp_ae_ld_T_1; // @[TLB.scala:318:7, :641:41] wire [6:0] _io_resp_ae_st_T = ae_st_array & hits; // @[TLB.scala:442:17, :590:53, :642:33] assign _io_resp_ae_st_T_1 = |_io_resp_ae_st_T; // @[TLB.scala:642:{33,41}] assign io_resp_ae_st = _io_resp_ae_st_T_1; // @[TLB.scala:318:7, :642:41] wire [6:0] _io_resp_ae_inst_T = ~px_array; // @[TLB.scala:533:87, :643:23] wire [6:0] _io_resp_ae_inst_T_1 = _io_resp_ae_inst_T & hits; // @[TLB.scala:442:17, :643:{23,33}] assign _io_resp_ae_inst_T_2 = |_io_resp_ae_inst_T_1; // @[TLB.scala:643:{33,41}] assign io_resp_ae_inst = _io_resp_ae_inst_T_2; // @[TLB.scala:318:7, :643:41] assign _io_resp_ma_ld_T = misaligned & cmd_read; // @[TLB.scala:550:77, :645:31] assign io_resp_ma_ld = _io_resp_ma_ld_T; // @[TLB.scala:318:7, :645:31] assign _io_resp_ma_st_T = misaligned & cmd_write; // @[TLB.scala:550:77, :646:31] assign io_resp_ma_st = _io_resp_ma_st_T; // @[TLB.scala:318:7, :646:31] wire [6:0] _io_resp_cacheable_T = c_array & hits; // @[TLB.scala:442:17, :537:20, :648:33] assign _io_resp_cacheable_T_1 = |_io_resp_cacheable_T; // @[TLB.scala:648:{33,41}] assign io_resp_cacheable = _io_resp_cacheable_T_1; // @[TLB.scala:318:7, :648:41] wire [6:0] _io_resp_must_alloc_T = must_alloc_array & hits; // @[TLB.scala:442:17, :595:46, :649:43] assign _io_resp_must_alloc_T_1 = |_io_resp_must_alloc_T; // @[TLB.scala:649:{43,51}] assign io_resp_must_alloc = _io_resp_must_alloc_T_1; // @[TLB.scala:318:7, :649:51] wire [6:0] _io_resp_prefetchable_T = prefetchable_array & hits; // @[TLB.scala:442:17, :547:31, :650:47] wire _io_resp_prefetchable_T_1 = |_io_resp_prefetchable_T; // @[TLB.scala:650:{47,55}] assign _io_resp_prefetchable_T_2 = _io_resp_prefetchable_T_1; // @[TLB.scala:650:{55,59}] assign io_resp_prefetchable = _io_resp_prefetchable_T_2; // @[TLB.scala:318:7, :650:59] wire _io_resp_miss_T_1 = _io_resp_miss_T | tlb_miss; // @[TLB.scala:613:64, :651:{29,52}] assign _io_resp_miss_T_2 = _io_resp_miss_T_1 | multipleHits; // @[Misc.scala:183:49] assign io_resp_miss_0 = _io_resp_miss_T_2; // @[TLB.scala:318:7, :651:64] assign _io_resp_paddr_T_1 = {ppn, _io_resp_paddr_T}; // @[Mux.scala:30:73] assign io_resp_paddr_0 = _io_resp_paddr_T_1; // @[TLB.scala:318:7, :652:23] wire [27:0] _io_resp_gpa_page_T_1 = {1'h0, vpn}; // @[TLB.scala:335:30, :657:36] wire [27:0] io_resp_gpa_page = _io_resp_gpa_page_T_1; // @[TLB.scala:657:{19,36}] wire [26:0] _io_resp_gpa_page_T_2 = r_gpa[38:12]; // @[TLB.scala:363:18, :657:58] wire [11:0] _io_resp_gpa_offset_T = r_gpa[11:0]; // @[TLB.scala:363:18, :658:47] wire [11:0] io_resp_gpa_offset = _io_resp_gpa_offset_T_1; // @[TLB.scala:658:{21,82}] assign _io_resp_gpa_T = {io_resp_gpa_page, io_resp_gpa_offset}; // @[TLB.scala:657:19, :658:21, :659:8] assign io_resp_gpa = _io_resp_gpa_T; // @[TLB.scala:318:7, :659:8] assign io_ptw_req_valid_0 = _io_ptw_req_valid_T; // @[TLB.scala:318:7, :662:29] wire _r_superpage_repl_addr_T_1 = ~superpage_entries_0_valid_0; // @[TLB.scala:341:30, :757:43] wire _r_superpage_repl_addr_T_2 = _r_superpage_repl_addr_T_1; // @[OneHot.scala:48:45] wire r_sectored_repl_addr_left_subtree_older = _GEN_57[memIdx][2]; // @[package.scala:163:13] wire _r_sectored_repl_addr_T = r_sectored_repl_addr_left_subtree_state; // @[package.scala:163:13] wire _r_sectored_repl_addr_T_1 = r_sectored_repl_addr_right_subtree_state; // @[Replacement.scala:245:38, :262:12] wire _r_sectored_repl_addr_T_2 = r_sectored_repl_addr_left_subtree_older ? _r_sectored_repl_addr_T : _r_sectored_repl_addr_T_1; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _r_sectored_repl_addr_T_3 = {r_sectored_repl_addr_left_subtree_older, _r_sectored_repl_addr_T_2}; // @[Replacement.scala:243:38, :249:12, :250:16] wire [1:0] r_sectored_repl_addr_valids_lo = {_GEN_11[memIdx], _GEN_7[memIdx]}; // @[package.scala:45:27, :163:13] wire [1:0] r_sectored_repl_addr_valids_hi = {_GEN_19[memIdx], _GEN_15[memIdx]}; // @[package.scala:45:27, :163:13] wire [3:0] r_sectored_repl_addr_valids = {r_sectored_repl_addr_valids_hi, r_sectored_repl_addr_valids_lo}; // @[package.scala:45:27] wire _r_sectored_repl_addr_T_4 = &r_sectored_repl_addr_valids; // @[package.scala:45:27] wire [3:0] _r_sectored_repl_addr_T_5 = ~r_sectored_repl_addr_valids; // @[package.scala:45:27] wire _r_sectored_repl_addr_T_6 = _r_sectored_repl_addr_T_5[0]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_7 = _r_sectored_repl_addr_T_5[1]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_8 = _r_sectored_repl_addr_T_5[2]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_9 = _r_sectored_repl_addr_T_5[3]; // @[OneHot.scala:48:45] wire [1:0] _r_sectored_repl_addr_T_10 = {1'h1, ~_r_sectored_repl_addr_T_8}; // @[OneHot.scala:48:45] wire [1:0] _r_sectored_repl_addr_T_11 = _r_sectored_repl_addr_T_7 ? 2'h1 : _r_sectored_repl_addr_T_10; // @[OneHot.scala:48:45] wire [1:0] _r_sectored_repl_addr_T_12 = _r_sectored_repl_addr_T_6 ? 2'h0 : _r_sectored_repl_addr_T_11; // @[OneHot.scala:48:45] wire [1:0] _r_sectored_repl_addr_T_13 = _r_sectored_repl_addr_T_4 ? _r_sectored_repl_addr_T_3 : _r_sectored_repl_addr_T_12; // @[Mux.scala:50:70] wire _r_sectored_hit_valid_T = sector_hits_0 | sector_hits_1; // @[package.scala:81:59] wire _r_sectored_hit_valid_T_1 = _r_sectored_hit_valid_T | sector_hits_2; // @[package.scala:81:59] wire _r_sectored_hit_valid_T_2 = _r_sectored_hit_valid_T_1 | sector_hits_3; // @[package.scala:81:59] wire [3:0] _r_sectored_hit_bits_T = {r_sectored_hit_bits_hi, r_sectored_hit_bits_lo}; // @[OneHot.scala:21:45] wire [1:0] r_sectored_hit_bits_hi_1 = _r_sectored_hit_bits_T[3:2]; // @[OneHot.scala:21:45, :30:18] wire [1:0] r_sectored_hit_bits_lo_1 = _r_sectored_hit_bits_T[1:0]; // @[OneHot.scala:21:45, :31:18] wire _r_sectored_hit_bits_T_1 = |r_sectored_hit_bits_hi_1; // @[OneHot.scala:30:18, :32:14] wire [1:0] _r_sectored_hit_bits_T_2 = r_sectored_hit_bits_hi_1 | r_sectored_hit_bits_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire _r_sectored_hit_bits_T_3 = _r_sectored_hit_bits_T_2[1]; // @[OneHot.scala:32:28] wire [1:0] _r_sectored_hit_bits_T_4 = {_r_sectored_hit_bits_T_1, _r_sectored_hit_bits_T_3}; // @[OneHot.scala:32:{10,14}] wire [1:0] _state_T = {1'h1, io_sfence_valid_0}; // @[TLB.scala:318:7, :704:45] wire _tagMatch_T = ~superpage_entries_0_tag_v; // @[TLB.scala:178:43, :341:30] wire tagMatch = superpage_entries_0_valid_0 & _tagMatch_T; // @[TLB.scala:178:{33,43}, :341:30] wire ignore_1 = _ignore_T_1; // @[TLB.scala:182:{28,34}] wire _ignore_T_2 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :341:30] wire _tagMatch_T_1 = ~special_entry_tag_v; // @[TLB.scala:178:43, :346:56] wire tagMatch_1 = special_entry_valid_0 & _tagMatch_T_1; // @[TLB.scala:178:{33,43}, :346:56] wire ignore_4 = _ignore_T_4; // @[TLB.scala:182:{28,34}] wire _ignore_T_5 = ~(special_entry_level[1]); // @[TLB.scala:182:28, :197:28, :346:56] wire ignore_5 = _ignore_T_5; // @[TLB.scala:182:{28,34}] wire _T_12 = io_req_valid_0 & vm_enabled; // @[TLB.scala:318:7, :399:61, :617:22] wire _T_15 = sector_hits_0 | sector_hits_1 | sector_hits_2 | sector_hits_3; // @[package.scala:81:59] wire _GEN_58 = do_refill & ~io_ptw_resp_bits_homogeneous_0; // @[TLB.scala:211:18, :318:7, :346:56, :408:29, :446:20, :474:{39,70}] wire _GEN_59 = ~do_refill | ~io_ptw_resp_bits_homogeneous_0 | io_ptw_resp_bits_level_0[1]; // @[TLB.scala:318:7, :341:30, :408:29, :446:20, :474:70, :476:{40,58}] wire _T_4 = waddr_1 == 2'h0; // @[TLB.scala:485:22, :486:75] wire _GEN_60 = r_memIdx == 2'h0; // @[package.scala:163:13] wire _GEN_61 = r_memIdx == 2'h1; // @[package.scala:163:13] wire _GEN_62 = r_memIdx == 2'h2; // @[package.scala:163:13] wire _GEN_63 = ~io_ptw_resp_bits_homogeneous_0 | ~(io_ptw_resp_bits_level_0[1]); // @[TLB.scala:318:7, :339:29, :474:{39,70}, :476:{40,58}, :486:84] wire _GEN_64 = ~do_refill | _GEN_63 | ~(_T_4 & _GEN_60); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_65 = ~do_refill | _GEN_63 | ~(_T_4 & _GEN_61); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_66 = ~do_refill | _GEN_63 | ~(_T_4 & _GEN_62); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_67 = ~do_refill | _GEN_63 | ~(_T_4 & (&r_memIdx)); // @[package.scala:163:13] wire _GEN_68 = invalidate_refill & _GEN_60; // @[TLB.scala:216:16, :220:46, :410:88, :489:34] wire _GEN_69 = ~do_refill | _GEN_63 | ~_T_4; // @[TLB.scala:339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_70 = invalidate_refill & _GEN_61; // @[TLB.scala:216:16, :220:46, :410:88, :489:34] wire _GEN_71 = invalidate_refill & _GEN_62; // @[TLB.scala:216:16, :220:46, :410:88, :489:34] wire _GEN_72 = invalidate_refill & (&r_memIdx); // @[package.scala:163:13] wire _T_6 = waddr_1 == 2'h1; // @[TLB.scala:197:28, :485:22, :486:75] wire _GEN_73 = ~do_refill | _GEN_63 | ~(_T_6 & _GEN_60); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_74 = ~do_refill | _GEN_63 | ~(_T_6 & _GEN_61); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_75 = ~do_refill | _GEN_63 | ~(_T_6 & _GEN_62); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_76 = ~do_refill | _GEN_63 | ~(_T_6 & (&r_memIdx)); // @[package.scala:163:13] wire _GEN_77 = ~do_refill | _GEN_63 | ~_T_6; // @[TLB.scala:339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _T_8 = waddr_1 == 2'h2; // @[TLB.scala:485:22, :486:75] wire _GEN_78 = ~do_refill | _GEN_63 | ~(_T_8 & _GEN_60); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_79 = ~do_refill | _GEN_63 | ~(_T_8 & _GEN_61); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_80 = ~do_refill | _GEN_63 | ~(_T_8 & _GEN_62); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_81 = ~do_refill | _GEN_63 | ~(_T_8 & (&r_memIdx)); // @[package.scala:163:13] wire _GEN_82 = ~do_refill | _GEN_63 | ~_T_8; // @[TLB.scala:339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_83 = ~do_refill | _GEN_63 | ~((&waddr_1) & _GEN_60); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :485:22, :486:{75,84}] wire _GEN_84 = ~do_refill | _GEN_63 | ~((&waddr_1) & _GEN_61); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :485:22, :486:{75,84}] wire _GEN_85 = ~do_refill | _GEN_63 | ~((&waddr_1) & _GEN_62); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :485:22, :486:{75,84}] wire _GEN_86 = ~do_refill | _GEN_63 | ~((&waddr_1) & (&r_memIdx)); // @[package.scala:163:13] wire _GEN_87 = ~do_refill | _GEN_63 | ~(&waddr_1); // @[TLB.scala:339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :485:22, :486:{75,84}] wire _T_2491 = io_ptw_req_ready_0 & io_ptw_req_valid_0; // @[Decoupled.scala:51:35] wire _T_24 = io_req_ready_0 & io_req_valid_0 & tlb_miss; // @[Decoupled.scala:51:35] wire _T_2490 = multipleHits | reset; // @[Misc.scala:183:49] always @(posedge clock) begin // @[TLB.scala:318:7] if (_GEN_64) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_0_0_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_0_0_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_0_0_tag_v <= _GEN_64 & sectored_entries_0_0_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_64) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_0_0_data_0 <= _sectored_entries_0_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_0_0_valid_0 <= ~(_T_2490 | io_sfence_valid_0 & ~sectored_entries_0_0_tag_v) & (_GEN_69 ? sectored_entries_0_0_valid_0 : ~_GEN_68 & (_GEN_60 | ~(~r_sectored_hit_valid & _GEN_60) & sectored_entries_0_0_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_73) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_0_1_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_0_1_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_0_1_tag_v <= _GEN_73 & sectored_entries_0_1_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_73) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_0_1_data_0 <= _sectored_entries_1_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_0_1_valid_0 <= ~(_T_2490 | io_sfence_valid_0 & ~sectored_entries_0_1_tag_v) & (_GEN_77 ? sectored_entries_0_1_valid_0 : ~_GEN_68 & (_GEN_60 | ~(~r_sectored_hit_valid & _GEN_60) & sectored_entries_0_1_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_78) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_0_2_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_0_2_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_0_2_tag_v <= _GEN_78 & sectored_entries_0_2_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_78) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_0_2_data_0 <= _sectored_entries_2_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_0_2_valid_0 <= ~(_T_2490 | io_sfence_valid_0 & ~sectored_entries_0_2_tag_v) & (_GEN_82 ? sectored_entries_0_2_valid_0 : ~_GEN_68 & (_GEN_60 | ~(~r_sectored_hit_valid & _GEN_60) & sectored_entries_0_2_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_83) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_0_3_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_0_3_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_0_3_tag_v <= _GEN_83 & sectored_entries_0_3_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_83) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_0_3_data_0 <= _sectored_entries_3_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_0_3_valid_0 <= ~(_T_2490 | io_sfence_valid_0 & ~sectored_entries_0_3_tag_v) & (_GEN_87 ? sectored_entries_0_3_valid_0 : ~_GEN_68 & (_GEN_60 | ~(~r_sectored_hit_valid & _GEN_60) & sectored_entries_0_3_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_65) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_1_0_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_1_0_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_1_0_tag_v <= _GEN_65 & sectored_entries_1_0_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_65) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_1_0_data_0 <= _sectored_entries_0_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_1_0_valid_0 <= ~(_T_2490 | io_sfence_valid_0 & ~sectored_entries_1_0_tag_v) & (_GEN_69 ? sectored_entries_1_0_valid_0 : ~_GEN_70 & (_GEN_61 | ~(~r_sectored_hit_valid & _GEN_61) & sectored_entries_1_0_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_74) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_1_1_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_1_1_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_1_1_tag_v <= _GEN_74 & sectored_entries_1_1_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_74) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_1_1_data_0 <= _sectored_entries_1_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_1_1_valid_0 <= ~(_T_2490 | io_sfence_valid_0 & ~sectored_entries_1_1_tag_v) & (_GEN_77 ? sectored_entries_1_1_valid_0 : ~_GEN_70 & (_GEN_61 | ~(~r_sectored_hit_valid & _GEN_61) & sectored_entries_1_1_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_79) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_1_2_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_1_2_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_1_2_tag_v <= _GEN_79 & sectored_entries_1_2_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_79) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_1_2_data_0 <= _sectored_entries_2_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_1_2_valid_0 <= ~(_T_2490 | io_sfence_valid_0 & ~sectored_entries_1_2_tag_v) & (_GEN_82 ? sectored_entries_1_2_valid_0 : ~_GEN_70 & (_GEN_61 | ~(~r_sectored_hit_valid & _GEN_61) & sectored_entries_1_2_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_84) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_1_3_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_1_3_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_1_3_tag_v <= _GEN_84 & sectored_entries_1_3_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_84) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_1_3_data_0 <= _sectored_entries_3_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_1_3_valid_0 <= ~(_T_2490 | io_sfence_valid_0 & ~sectored_entries_1_3_tag_v) & (_GEN_87 ? sectored_entries_1_3_valid_0 : ~_GEN_70 & (_GEN_61 | ~(~r_sectored_hit_valid & _GEN_61) & sectored_entries_1_3_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_66) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_2_0_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_2_0_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_2_0_tag_v <= _GEN_66 & sectored_entries_2_0_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_66) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_2_0_data_0 <= _sectored_entries_0_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_2_0_valid_0 <= ~(_T_2490 | io_sfence_valid_0 & ~sectored_entries_2_0_tag_v) & (_GEN_69 ? sectored_entries_2_0_valid_0 : ~_GEN_71 & (_GEN_62 | ~(~r_sectored_hit_valid & _GEN_62) & sectored_entries_2_0_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_75) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_2_1_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_2_1_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_2_1_tag_v <= _GEN_75 & sectored_entries_2_1_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_75) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_2_1_data_0 <= _sectored_entries_1_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_2_1_valid_0 <= ~(_T_2490 | io_sfence_valid_0 & ~sectored_entries_2_1_tag_v) & (_GEN_77 ? sectored_entries_2_1_valid_0 : ~_GEN_71 & (_GEN_62 | ~(~r_sectored_hit_valid & _GEN_62) & sectored_entries_2_1_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_80) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_2_2_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_2_2_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_2_2_tag_v <= _GEN_80 & sectored_entries_2_2_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_80) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_2_2_data_0 <= _sectored_entries_2_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_2_2_valid_0 <= ~(_T_2490 | io_sfence_valid_0 & ~sectored_entries_2_2_tag_v) & (_GEN_82 ? sectored_entries_2_2_valid_0 : ~_GEN_71 & (_GEN_62 | ~(~r_sectored_hit_valid & _GEN_62) & sectored_entries_2_2_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_85) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_2_3_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_2_3_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_2_3_tag_v <= _GEN_85 & sectored_entries_2_3_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_85) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_2_3_data_0 <= _sectored_entries_3_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_2_3_valid_0 <= ~(_T_2490 | io_sfence_valid_0 & ~sectored_entries_2_3_tag_v) & (_GEN_87 ? sectored_entries_2_3_valid_0 : ~_GEN_71 & (_GEN_62 | ~(~r_sectored_hit_valid & _GEN_62) & sectored_entries_2_3_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_67) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_3_0_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_3_0_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_3_0_tag_v <= _GEN_67 & sectored_entries_3_0_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_67) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_3_0_data_0 <= _sectored_entries_0_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_3_0_valid_0 <= ~(_T_2490 | io_sfence_valid_0 & ~sectored_entries_3_0_tag_v) & (_GEN_69 ? sectored_entries_3_0_valid_0 : ~_GEN_72 & ((&r_memIdx) | ~(~r_sectored_hit_valid & (&r_memIdx)) & sectored_entries_3_0_valid_0)); // @[package.scala:163:13] if (_GEN_76) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_3_1_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_3_1_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_3_1_tag_v <= _GEN_76 & sectored_entries_3_1_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_76) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_3_1_data_0 <= _sectored_entries_1_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_3_1_valid_0 <= ~(_T_2490 | io_sfence_valid_0 & ~sectored_entries_3_1_tag_v) & (_GEN_77 ? sectored_entries_3_1_valid_0 : ~_GEN_72 & ((&r_memIdx) | ~(~r_sectored_hit_valid & (&r_memIdx)) & sectored_entries_3_1_valid_0)); // @[package.scala:163:13] if (_GEN_81) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_3_2_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_3_2_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_3_2_tag_v <= _GEN_81 & sectored_entries_3_2_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_81) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_3_2_data_0 <= _sectored_entries_2_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_3_2_valid_0 <= ~(_T_2490 | io_sfence_valid_0 & ~sectored_entries_3_2_tag_v) & (_GEN_82 ? sectored_entries_3_2_valid_0 : ~_GEN_72 & ((&r_memIdx) | ~(~r_sectored_hit_valid & (&r_memIdx)) & sectored_entries_3_2_valid_0)); // @[package.scala:163:13] if (_GEN_86) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_3_3_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_3_3_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_3_3_tag_v <= _GEN_86 & sectored_entries_3_3_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_86) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_3_3_data_0 <= _sectored_entries_3_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_3_3_valid_0 <= ~(_T_2490 | io_sfence_valid_0 & ~sectored_entries_3_3_tag_v) & (_GEN_87 ? sectored_entries_3_3_valid_0 : ~_GEN_72 & ((&r_memIdx) | ~(~r_sectored_hit_valid & (&r_memIdx)) & sectored_entries_3_3_valid_0)); // @[package.scala:163:13] if (_GEN_59) begin // @[TLB.scala:341:30, :446:20, :474:70, :476:58] end else begin // @[TLB.scala:341:30, :446:20, :474:70, :476:58] superpage_entries_0_level <= {1'h0, _superpage_entries_0_level_T}; // @[package.scala:163:13] superpage_entries_0_tag_vpn <= r_refill_tag; // @[TLB.scala:341:30, :354:25] end superpage_entries_0_tag_v <= _GEN_59 & superpage_entries_0_tag_v; // @[TLB.scala:341:30, :446:20, :474:70, :476:58] if (_GEN_59) begin // @[TLB.scala:341:30, :446:20, :474:70, :476:58] end else // @[TLB.scala:341:30, :446:20, :474:70, :476:58] superpage_entries_0_data_0 <= _superpage_entries_0_data_0_T; // @[TLB.scala:217:24, :341:30] superpage_entries_0_valid_0 <= ~(_T_2490 | io_sfence_valid_0 & ~superpage_entries_0_tag_v) & (_GEN_59 ? superpage_entries_0_valid_0 : ~invalidate_refill); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :341:30, :410:88, :446:20, :474:70, :476:58, :480:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_58) begin // @[TLB.scala:211:18, :346:56, :446:20, :474:70] special_entry_level <= _special_entry_level_T; // @[package.scala:163:13] special_entry_tag_vpn <= r_refill_tag; // @[TLB.scala:346:56, :354:25] special_entry_data_0 <= _special_entry_data_0_T; // @[TLB.scala:217:24, :346:56] end special_entry_tag_v <= ~_GEN_58 & special_entry_tag_v; // @[TLB.scala:211:18, :212:16, :346:56, :446:20, :474:70] special_entry_valid_0 <= ~(_T_2490 | io_sfence_valid_0 & ~special_entry_tag_v) & (_GEN_58 | special_entry_valid_0); // @[TLB.scala:211:18, :216:16, :220:46, :223:{19,32,36}, :318:7, :346:56, :446:20, :474:70, :718:19, :723:42, :728:46, :732:{24,41}] if (_T_24) begin // @[Decoupled.scala:51:35] r_refill_tag <= vpn; // @[TLB.scala:335:30, :354:25] r_sectored_repl_addr <= _r_sectored_repl_addr_T_13; // @[TLB.scala:356:33, :757:8] r_sectored_hit_valid <= _r_sectored_hit_valid_T_2; // @[package.scala:81:59] r_sectored_hit_bits <= _r_sectored_hit_bits_T_4; // @[OneHot.scala:32:10] r_superpage_hit_valid <= superpage_hits_0; // @[TLB.scala:183:29, :358:28] r_need_gpa <= tlb_hit_if_not_gpa_miss; // @[TLB.scala:361:23, :610:43] end r_gpa_valid <= ~_T_2491 & (do_refill ? io_ptw_resp_bits_gpa_valid_0 : r_gpa_valid); // @[Decoupled.scala:51:35] if (do_refill) begin // @[TLB.scala:408:29] r_gpa <= io_ptw_resp_bits_gpa_bits_0; // @[TLB.scala:318:7, :363:18] r_gpa_is_pte <= io_ptw_resp_bits_gpa_is_pte_0; // @[TLB.scala:318:7, :365:25] end if (_T_2491) // @[Decoupled.scala:51:35] r_gpa_vpn <= r_refill_tag; // @[TLB.scala:354:25, :364:22] if (reset) begin // @[TLB.scala:318:7] state <= 2'h0; // @[TLB.scala:352:22] state_vec_0 <= 3'h0; // @[Replacement.scala:305:17] state_vec_1 <= 3'h0; // @[Replacement.scala:305:17] state_vec_2 <= 3'h0; // @[Replacement.scala:305:17] state_vec_3 <= 3'h0; // @[Replacement.scala:305:17] end else begin // @[TLB.scala:318:7] if (io_ptw_resp_valid_0) // @[TLB.scala:318:7] state <= 2'h0; // @[TLB.scala:352:22] else if (state == 2'h2 & io_sfence_valid_0) // @[TLB.scala:318:7, :352:22, :709:{17,28}] state <= 2'h3; // @[TLB.scala:352:22] else if (_T_25) begin // @[package.scala:16:47] if (io_ptw_req_ready_0) // @[TLB.scala:318:7] state <= _state_T; // @[TLB.scala:352:22, :704:45] else if (io_sfence_valid_0) // @[TLB.scala:318:7] state <= 2'h0; // @[TLB.scala:352:22] else if (_T_24) // @[Decoupled.scala:51:35] state <= 2'h1; // @[TLB.scala:197:28, :352:22] end else if (_T_24) // @[Decoupled.scala:51:35] state <= 2'h1; // @[TLB.scala:197:28, :352:22] if (_T_12 & _T_15 & memIdx == 2'h0) // @[package.scala:81:59, :163:13] state_vec_0 <= _state_vec_T_8; // @[Replacement.scala:202:12, :305:17] if (_T_12 & _T_15 & memIdx == 2'h1) // @[package.scala:81:59, :163:13] state_vec_1 <= _state_vec_T_8; // @[Replacement.scala:202:12, :305:17] if (_T_12 & _T_15 & memIdx == 2'h2) // @[package.scala:81:59, :163:13] state_vec_2 <= _state_vec_T_8; // @[Replacement.scala:202:12, :305:17] if (_T_12 & _T_15 & (&memIdx)) // @[package.scala:81:59, :163:13] state_vec_3 <= _state_vec_T_8; // @[Replacement.scala:202:12, :305:17] end always @(posedge) OptimizationBarrier_TLBEntryData_105 mpu_ppn_barrier ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_mpu_ppn_WIRE_ppn), // @[TLB.scala:170:77] .io_x_u (_mpu_ppn_WIRE_u), // @[TLB.scala:170:77] .io_x_g (_mpu_ppn_WIRE_g), // @[TLB.scala:170:77] .io_x_ae_ptw (_mpu_ppn_WIRE_ae_ptw), // @[TLB.scala:170:77] .io_x_ae_final (_mpu_ppn_WIRE_ae_final), // @[TLB.scala:170:77] .io_x_ae_stage2 (_mpu_ppn_WIRE_ae_stage2), // @[TLB.scala:170:77] .io_x_pf (_mpu_ppn_WIRE_pf), // @[TLB.scala:170:77] .io_x_gf (_mpu_ppn_WIRE_gf), // @[TLB.scala:170:77] .io_x_sw (_mpu_ppn_WIRE_sw), // @[TLB.scala:170:77] .io_x_sx (_mpu_ppn_WIRE_sx), // @[TLB.scala:170:77] .io_x_sr (_mpu_ppn_WIRE_sr), // @[TLB.scala:170:77] .io_x_hw (_mpu_ppn_WIRE_hw), // @[TLB.scala:170:77] .io_x_hx (_mpu_ppn_WIRE_hx), // @[TLB.scala:170:77] .io_x_hr (_mpu_ppn_WIRE_hr), // @[TLB.scala:170:77] .io_x_pw (_mpu_ppn_WIRE_pw), // @[TLB.scala:170:77] .io_x_px (_mpu_ppn_WIRE_px), // @[TLB.scala:170:77] .io_x_pr (_mpu_ppn_WIRE_pr), // @[TLB.scala:170:77] .io_x_ppp (_mpu_ppn_WIRE_ppp), // @[TLB.scala:170:77] .io_x_pal (_mpu_ppn_WIRE_pal), // @[TLB.scala:170:77] .io_x_paa (_mpu_ppn_WIRE_paa), // @[TLB.scala:170:77] .io_x_eff (_mpu_ppn_WIRE_eff), // @[TLB.scala:170:77] .io_x_c (_mpu_ppn_WIRE_c), // @[TLB.scala:170:77] .io_x_fragmented_superpage (_mpu_ppn_WIRE_fragmented_superpage), // @[TLB.scala:170:77] .io_y_ppn (_mpu_ppn_barrier_io_y_ppn) ); // @[package.scala:267:25] PMPChecker_s3_13 pmp ( // @[TLB.scala:416:19] .clock (clock), .reset (reset), .io_prv (mpu_priv[1:0]), // @[TLB.scala:415:27, :420:14] .io_pmp_0_cfg_l (io_ptw_pmp_0_cfg_l_0), // @[TLB.scala:318:7] .io_pmp_0_cfg_a (io_ptw_pmp_0_cfg_a_0), // @[TLB.scala:318:7] .io_pmp_0_cfg_x (io_ptw_pmp_0_cfg_x_0), // @[TLB.scala:318:7] .io_pmp_0_cfg_w (io_ptw_pmp_0_cfg_w_0), // @[TLB.scala:318:7] .io_pmp_0_cfg_r (io_ptw_pmp_0_cfg_r_0), // @[TLB.scala:318:7] .io_pmp_0_addr (io_ptw_pmp_0_addr_0), // @[TLB.scala:318:7] .io_pmp_0_mask (io_ptw_pmp_0_mask_0), // @[TLB.scala:318:7] .io_pmp_1_cfg_l (io_ptw_pmp_1_cfg_l_0), // @[TLB.scala:318:7] .io_pmp_1_cfg_a (io_ptw_pmp_1_cfg_a_0), // @[TLB.scala:318:7] .io_pmp_1_cfg_x (io_ptw_pmp_1_cfg_x_0), // @[TLB.scala:318:7] .io_pmp_1_cfg_w (io_ptw_pmp_1_cfg_w_0), // @[TLB.scala:318:7] .io_pmp_1_cfg_r (io_ptw_pmp_1_cfg_r_0), // @[TLB.scala:318:7] .io_pmp_1_addr (io_ptw_pmp_1_addr_0), // @[TLB.scala:318:7] .io_pmp_1_mask (io_ptw_pmp_1_mask_0), // @[TLB.scala:318:7] .io_pmp_2_cfg_l (io_ptw_pmp_2_cfg_l_0), // @[TLB.scala:318:7] .io_pmp_2_cfg_a (io_ptw_pmp_2_cfg_a_0), // @[TLB.scala:318:7] .io_pmp_2_cfg_x (io_ptw_pmp_2_cfg_x_0), // @[TLB.scala:318:7] .io_pmp_2_cfg_w (io_ptw_pmp_2_cfg_w_0), // @[TLB.scala:318:7] .io_pmp_2_cfg_r (io_ptw_pmp_2_cfg_r_0), // @[TLB.scala:318:7] .io_pmp_2_addr (io_ptw_pmp_2_addr_0), // @[TLB.scala:318:7] .io_pmp_2_mask (io_ptw_pmp_2_mask_0), // @[TLB.scala:318:7] .io_pmp_3_cfg_l (io_ptw_pmp_3_cfg_l_0), // @[TLB.scala:318:7] .io_pmp_3_cfg_a (io_ptw_pmp_3_cfg_a_0), // @[TLB.scala:318:7] .io_pmp_3_cfg_x (io_ptw_pmp_3_cfg_x_0), // @[TLB.scala:318:7] .io_pmp_3_cfg_w (io_ptw_pmp_3_cfg_w_0), // @[TLB.scala:318:7] .io_pmp_3_cfg_r (io_ptw_pmp_3_cfg_r_0), // @[TLB.scala:318:7] .io_pmp_3_addr (io_ptw_pmp_3_addr_0), // @[TLB.scala:318:7] .io_pmp_3_mask (io_ptw_pmp_3_mask_0), // @[TLB.scala:318:7] .io_pmp_4_cfg_l (io_ptw_pmp_4_cfg_l_0), // @[TLB.scala:318:7] .io_pmp_4_cfg_a (io_ptw_pmp_4_cfg_a_0), // @[TLB.scala:318:7] .io_pmp_4_cfg_x (io_ptw_pmp_4_cfg_x_0), // @[TLB.scala:318:7] .io_pmp_4_cfg_w (io_ptw_pmp_4_cfg_w_0), // @[TLB.scala:318:7] .io_pmp_4_cfg_r (io_ptw_pmp_4_cfg_r_0), // @[TLB.scala:318:7] .io_pmp_4_addr (io_ptw_pmp_4_addr_0), // @[TLB.scala:318:7] .io_pmp_4_mask (io_ptw_pmp_4_mask_0), // @[TLB.scala:318:7] .io_pmp_5_cfg_l (io_ptw_pmp_5_cfg_l_0), // @[TLB.scala:318:7] .io_pmp_5_cfg_a (io_ptw_pmp_5_cfg_a_0), // @[TLB.scala:318:7] .io_pmp_5_cfg_x (io_ptw_pmp_5_cfg_x_0), // @[TLB.scala:318:7] .io_pmp_5_cfg_w (io_ptw_pmp_5_cfg_w_0), // @[TLB.scala:318:7] .io_pmp_5_cfg_r (io_ptw_pmp_5_cfg_r_0), // @[TLB.scala:318:7] .io_pmp_5_addr (io_ptw_pmp_5_addr_0), // @[TLB.scala:318:7] .io_pmp_5_mask (io_ptw_pmp_5_mask_0), // @[TLB.scala:318:7] .io_pmp_6_cfg_l (io_ptw_pmp_6_cfg_l_0), // @[TLB.scala:318:7] .io_pmp_6_cfg_a (io_ptw_pmp_6_cfg_a_0), // @[TLB.scala:318:7] .io_pmp_6_cfg_x (io_ptw_pmp_6_cfg_x_0), // @[TLB.scala:318:7] .io_pmp_6_cfg_w (io_ptw_pmp_6_cfg_w_0), // @[TLB.scala:318:7] .io_pmp_6_cfg_r (io_ptw_pmp_6_cfg_r_0), // @[TLB.scala:318:7] .io_pmp_6_addr (io_ptw_pmp_6_addr_0), // @[TLB.scala:318:7] .io_pmp_6_mask (io_ptw_pmp_6_mask_0), // @[TLB.scala:318:7] .io_pmp_7_cfg_l (io_ptw_pmp_7_cfg_l_0), // @[TLB.scala:318:7] .io_pmp_7_cfg_a (io_ptw_pmp_7_cfg_a_0), // @[TLB.scala:318:7] .io_pmp_7_cfg_x (io_ptw_pmp_7_cfg_x_0), // @[TLB.scala:318:7] .io_pmp_7_cfg_w (io_ptw_pmp_7_cfg_w_0), // @[TLB.scala:318:7] .io_pmp_7_cfg_r (io_ptw_pmp_7_cfg_r_0), // @[TLB.scala:318:7] .io_pmp_7_addr (io_ptw_pmp_7_addr_0), // @[TLB.scala:318:7] .io_pmp_7_mask (io_ptw_pmp_7_mask_0), // @[TLB.scala:318:7] .io_addr (mpu_physaddr[31:0]), // @[TLB.scala:414:25, :417:15] .io_size (io_req_bits_size_0), // @[TLB.scala:318:7] .io_r (_pmp_io_r), .io_w (_pmp_io_w), .io_x (_pmp_io_x) ); // @[TLB.scala:416:19] PMAChecker_13 pma ( // @[TLB.scala:422:19] .clock (clock), .reset (reset), .io_paddr (mpu_physaddr), // @[TLB.scala:414:25] .io_resp_cacheable (cacheable), .io_resp_r (_pma_io_resp_r), .io_resp_w (_pma_io_resp_w), .io_resp_pp (_pma_io_resp_pp), .io_resp_al (_pma_io_resp_al), .io_resp_aa (_pma_io_resp_aa), .io_resp_x (_pma_io_resp_x), .io_resp_eff (_pma_io_resp_eff) ); // @[TLB.scala:422:19] assign newEntry_ppp = _pma_io_resp_pp; // @[TLB.scala:422:19, :449:24] assign newEntry_pal = _pma_io_resp_al; // @[TLB.scala:422:19, :449:24] assign newEntry_paa = _pma_io_resp_aa; // @[TLB.scala:422:19, :449:24] assign newEntry_eff = _pma_io_resp_eff; // @[TLB.scala:422:19, :449:24] OptimizationBarrier_TLBEntryData_106 entries_barrier ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_ppn), // @[TLB.scala:170:77] .io_x_u (_entries_WIRE_u), // @[TLB.scala:170:77] .io_x_g (_entries_WIRE_g), // @[TLB.scala:170:77] .io_x_ae_ptw (_entries_WIRE_ae_ptw), // @[TLB.scala:170:77] .io_x_ae_final (_entries_WIRE_ae_final), // @[TLB.scala:170:77] .io_x_ae_stage2 (_entries_WIRE_ae_stage2), // @[TLB.scala:170:77] .io_x_pf (_entries_WIRE_pf), // @[TLB.scala:170:77] .io_x_gf (_entries_WIRE_gf), // @[TLB.scala:170:77] .io_x_sw (_entries_WIRE_sw), // @[TLB.scala:170:77] .io_x_sx (_entries_WIRE_sx), // @[TLB.scala:170:77] .io_x_sr (_entries_WIRE_sr), // @[TLB.scala:170:77] .io_x_hw (_entries_WIRE_hw), // @[TLB.scala:170:77] .io_x_hx (_entries_WIRE_hx), // @[TLB.scala:170:77] .io_x_hr (_entries_WIRE_hr), // @[TLB.scala:170:77] .io_x_pw (_entries_WIRE_pw), // @[TLB.scala:170:77] .io_x_px (_entries_WIRE_px), // @[TLB.scala:170:77] .io_x_pr (_entries_WIRE_pr), // @[TLB.scala:170:77] .io_x_ppp (_entries_WIRE_ppp), // @[TLB.scala:170:77] .io_x_pal (_entries_WIRE_pal), // @[TLB.scala:170:77] .io_x_paa (_entries_WIRE_paa), // @[TLB.scala:170:77] .io_x_eff (_entries_WIRE_eff), // @[TLB.scala:170:77] .io_x_c (_entries_WIRE_c), // @[TLB.scala:170:77] .io_x_fragmented_superpage (_entries_WIRE_fragmented_superpage), // @[TLB.scala:170:77] .io_y_ppn (_entries_barrier_io_y_ppn), .io_y_u (_entries_barrier_io_y_u), .io_y_ae_ptw (_entries_barrier_io_y_ae_ptw), .io_y_ae_final (_entries_barrier_io_y_ae_final), .io_y_ae_stage2 (_entries_barrier_io_y_ae_stage2), .io_y_pf (_entries_barrier_io_y_pf), .io_y_gf (_entries_barrier_io_y_gf), .io_y_sw (_entries_barrier_io_y_sw), .io_y_sx (_entries_barrier_io_y_sx), .io_y_sr (_entries_barrier_io_y_sr), .io_y_hw (_entries_barrier_io_y_hw), .io_y_hx (_entries_barrier_io_y_hx), .io_y_hr (_entries_barrier_io_y_hr), .io_y_pw (_entries_barrier_io_y_pw), .io_y_px (_entries_barrier_io_y_px), .io_y_pr (_entries_barrier_io_y_pr), .io_y_ppp (_entries_barrier_io_y_ppp), .io_y_pal (_entries_barrier_io_y_pal), .io_y_paa (_entries_barrier_io_y_paa), .io_y_eff (_entries_barrier_io_y_eff), .io_y_c (_entries_barrier_io_y_c) ); // @[package.scala:267:25] OptimizationBarrier_TLBEntryData_107 entries_barrier_1 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_2_ppn), // @[TLB.scala:170:77] .io_x_u (_entries_WIRE_2_u), // @[TLB.scala:170:77] .io_x_g (_entries_WIRE_2_g), // @[TLB.scala:170:77] .io_x_ae_ptw (_entries_WIRE_2_ae_ptw), // @[TLB.scala:170:77] .io_x_ae_final (_entries_WIRE_2_ae_final), // @[TLB.scala:170:77] .io_x_ae_stage2 (_entries_WIRE_2_ae_stage2), // @[TLB.scala:170:77] .io_x_pf (_entries_WIRE_2_pf), // @[TLB.scala:170:77] .io_x_gf (_entries_WIRE_2_gf), // @[TLB.scala:170:77] .io_x_sw (_entries_WIRE_2_sw), // @[TLB.scala:170:77] .io_x_sx (_entries_WIRE_2_sx), // @[TLB.scala:170:77] .io_x_sr (_entries_WIRE_2_sr), // @[TLB.scala:170:77] .io_x_hw (_entries_WIRE_2_hw), // @[TLB.scala:170:77] .io_x_hx (_entries_WIRE_2_hx), // @[TLB.scala:170:77] .io_x_hr (_entries_WIRE_2_hr), // @[TLB.scala:170:77] .io_x_pw (_entries_WIRE_2_pw), // @[TLB.scala:170:77] .io_x_px (_entries_WIRE_2_px), // @[TLB.scala:170:77] .io_x_pr (_entries_WIRE_2_pr), // @[TLB.scala:170:77] .io_x_ppp (_entries_WIRE_2_ppp), // @[TLB.scala:170:77] .io_x_pal (_entries_WIRE_2_pal), // @[TLB.scala:170:77] .io_x_paa (_entries_WIRE_2_paa), // @[TLB.scala:170:77] .io_x_eff (_entries_WIRE_2_eff), // @[TLB.scala:170:77] .io_x_c (_entries_WIRE_2_c), // @[TLB.scala:170:77] .io_x_fragmented_superpage (_entries_WIRE_2_fragmented_superpage), // @[TLB.scala:170:77] .io_y_ppn (_entries_barrier_1_io_y_ppn), .io_y_u (_entries_barrier_1_io_y_u), .io_y_ae_ptw (_entries_barrier_1_io_y_ae_ptw), .io_y_ae_final (_entries_barrier_1_io_y_ae_final), .io_y_ae_stage2 (_entries_barrier_1_io_y_ae_stage2), .io_y_pf (_entries_barrier_1_io_y_pf), .io_y_gf (_entries_barrier_1_io_y_gf), .io_y_sw (_entries_barrier_1_io_y_sw), .io_y_sx (_entries_barrier_1_io_y_sx), .io_y_sr (_entries_barrier_1_io_y_sr), .io_y_hw (_entries_barrier_1_io_y_hw), .io_y_hx (_entries_barrier_1_io_y_hx), .io_y_hr (_entries_barrier_1_io_y_hr), .io_y_pw (_entries_barrier_1_io_y_pw), .io_y_px (_entries_barrier_1_io_y_px), .io_y_pr (_entries_barrier_1_io_y_pr), .io_y_ppp (_entries_barrier_1_io_y_ppp), .io_y_pal (_entries_barrier_1_io_y_pal), .io_y_paa (_entries_barrier_1_io_y_paa), .io_y_eff (_entries_barrier_1_io_y_eff), .io_y_c (_entries_barrier_1_io_y_c) ); // @[package.scala:267:25] OptimizationBarrier_TLBEntryData_108 entries_barrier_2 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_4_ppn), // @[TLB.scala:170:77] .io_x_u (_entries_WIRE_4_u), // @[TLB.scala:170:77] .io_x_g (_entries_WIRE_4_g), // @[TLB.scala:170:77] .io_x_ae_ptw (_entries_WIRE_4_ae_ptw), // @[TLB.scala:170:77] .io_x_ae_final (_entries_WIRE_4_ae_final), // @[TLB.scala:170:77] .io_x_ae_stage2 (_entries_WIRE_4_ae_stage2), // @[TLB.scala:170:77] .io_x_pf (_entries_WIRE_4_pf), // @[TLB.scala:170:77] .io_x_gf (_entries_WIRE_4_gf), // @[TLB.scala:170:77] .io_x_sw (_entries_WIRE_4_sw), // @[TLB.scala:170:77] .io_x_sx (_entries_WIRE_4_sx), // @[TLB.scala:170:77] .io_x_sr (_entries_WIRE_4_sr), // @[TLB.scala:170:77] .io_x_hw (_entries_WIRE_4_hw), // @[TLB.scala:170:77] .io_x_hx (_entries_WIRE_4_hx), // @[TLB.scala:170:77] .io_x_hr (_entries_WIRE_4_hr), // @[TLB.scala:170:77] .io_x_pw (_entries_WIRE_4_pw), // @[TLB.scala:170:77] .io_x_px (_entries_WIRE_4_px), // @[TLB.scala:170:77] .io_x_pr (_entries_WIRE_4_pr), // @[TLB.scala:170:77] .io_x_ppp (_entries_WIRE_4_ppp), // @[TLB.scala:170:77] .io_x_pal (_entries_WIRE_4_pal), // @[TLB.scala:170:77] .io_x_paa (_entries_WIRE_4_paa), // @[TLB.scala:170:77] .io_x_eff (_entries_WIRE_4_eff), // @[TLB.scala:170:77] .io_x_c (_entries_WIRE_4_c), // @[TLB.scala:170:77] .io_x_fragmented_superpage (_entries_WIRE_4_fragmented_superpage), // @[TLB.scala:170:77] .io_y_ppn (_entries_barrier_2_io_y_ppn), .io_y_u (_entries_barrier_2_io_y_u), .io_y_ae_ptw (_entries_barrier_2_io_y_ae_ptw), .io_y_ae_final (_entries_barrier_2_io_y_ae_final), .io_y_ae_stage2 (_entries_barrier_2_io_y_ae_stage2), .io_y_pf (_entries_barrier_2_io_y_pf), .io_y_gf (_entries_barrier_2_io_y_gf), .io_y_sw (_entries_barrier_2_io_y_sw), .io_y_sx (_entries_barrier_2_io_y_sx), .io_y_sr (_entries_barrier_2_io_y_sr), .io_y_hw (_entries_barrier_2_io_y_hw), .io_y_hx (_entries_barrier_2_io_y_hx), .io_y_hr (_entries_barrier_2_io_y_hr), .io_y_pw (_entries_barrier_2_io_y_pw), .io_y_px (_entries_barrier_2_io_y_px), .io_y_pr (_entries_barrier_2_io_y_pr), .io_y_ppp (_entries_barrier_2_io_y_ppp), .io_y_pal (_entries_barrier_2_io_y_pal), .io_y_paa (_entries_barrier_2_io_y_paa), .io_y_eff (_entries_barrier_2_io_y_eff), .io_y_c (_entries_barrier_2_io_y_c) ); // @[package.scala:267:25] OptimizationBarrier_TLBEntryData_109 entries_barrier_3 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_6_ppn), // @[TLB.scala:170:77] .io_x_u (_entries_WIRE_6_u), // @[TLB.scala:170:77] .io_x_g (_entries_WIRE_6_g), // @[TLB.scala:170:77] .io_x_ae_ptw (_entries_WIRE_6_ae_ptw), // @[TLB.scala:170:77] .io_x_ae_final (_entries_WIRE_6_ae_final), // @[TLB.scala:170:77] .io_x_ae_stage2 (_entries_WIRE_6_ae_stage2), // @[TLB.scala:170:77] .io_x_pf (_entries_WIRE_6_pf), // @[TLB.scala:170:77] .io_x_gf (_entries_WIRE_6_gf), // @[TLB.scala:170:77] .io_x_sw (_entries_WIRE_6_sw), // @[TLB.scala:170:77] .io_x_sx (_entries_WIRE_6_sx), // @[TLB.scala:170:77] .io_x_sr (_entries_WIRE_6_sr), // @[TLB.scala:170:77] .io_x_hw (_entries_WIRE_6_hw), // @[TLB.scala:170:77] .io_x_hx (_entries_WIRE_6_hx), // @[TLB.scala:170:77] .io_x_hr (_entries_WIRE_6_hr), // @[TLB.scala:170:77] .io_x_pw (_entries_WIRE_6_pw), // @[TLB.scala:170:77] .io_x_px (_entries_WIRE_6_px), // @[TLB.scala:170:77] .io_x_pr (_entries_WIRE_6_pr), // @[TLB.scala:170:77] .io_x_ppp (_entries_WIRE_6_ppp), // @[TLB.scala:170:77] .io_x_pal (_entries_WIRE_6_pal), // @[TLB.scala:170:77] .io_x_paa (_entries_WIRE_6_paa), // @[TLB.scala:170:77] .io_x_eff (_entries_WIRE_6_eff), // @[TLB.scala:170:77] .io_x_c (_entries_WIRE_6_c), // @[TLB.scala:170:77] .io_x_fragmented_superpage (_entries_WIRE_6_fragmented_superpage), // @[TLB.scala:170:77] .io_y_ppn (_entries_barrier_3_io_y_ppn), .io_y_u (_entries_barrier_3_io_y_u), .io_y_ae_ptw (_entries_barrier_3_io_y_ae_ptw), .io_y_ae_final (_entries_barrier_3_io_y_ae_final), .io_y_ae_stage2 (_entries_barrier_3_io_y_ae_stage2), .io_y_pf (_entries_barrier_3_io_y_pf), .io_y_gf (_entries_barrier_3_io_y_gf), .io_y_sw (_entries_barrier_3_io_y_sw), .io_y_sx (_entries_barrier_3_io_y_sx), .io_y_sr (_entries_barrier_3_io_y_sr), .io_y_hw (_entries_barrier_3_io_y_hw), .io_y_hx (_entries_barrier_3_io_y_hx), .io_y_hr (_entries_barrier_3_io_y_hr), .io_y_pw (_entries_barrier_3_io_y_pw), .io_y_px (_entries_barrier_3_io_y_px), .io_y_pr (_entries_barrier_3_io_y_pr), .io_y_ppp (_entries_barrier_3_io_y_ppp), .io_y_pal (_entries_barrier_3_io_y_pal), .io_y_paa (_entries_barrier_3_io_y_paa), .io_y_eff (_entries_barrier_3_io_y_eff), .io_y_c (_entries_barrier_3_io_y_c) ); // @[package.scala:267:25] OptimizationBarrier_TLBEntryData_110 entries_barrier_4 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_8_ppn), // @[TLB.scala:170:77] .io_x_u (_entries_WIRE_8_u), // @[TLB.scala:170:77] .io_x_g (_entries_WIRE_8_g), // @[TLB.scala:170:77] .io_x_ae_ptw (_entries_WIRE_8_ae_ptw), // @[TLB.scala:170:77] .io_x_ae_final (_entries_WIRE_8_ae_final), // @[TLB.scala:170:77] .io_x_ae_stage2 (_entries_WIRE_8_ae_stage2), // @[TLB.scala:170:77] .io_x_pf (_entries_WIRE_8_pf), // @[TLB.scala:170:77] .io_x_gf (_entries_WIRE_8_gf), // @[TLB.scala:170:77] .io_x_sw (_entries_WIRE_8_sw), // @[TLB.scala:170:77] .io_x_sx (_entries_WIRE_8_sx), // @[TLB.scala:170:77] .io_x_sr (_entries_WIRE_8_sr), // @[TLB.scala:170:77] .io_x_hw (_entries_WIRE_8_hw), // @[TLB.scala:170:77] .io_x_hx (_entries_WIRE_8_hx), // @[TLB.scala:170:77] .io_x_hr (_entries_WIRE_8_hr), // @[TLB.scala:170:77] .io_x_pw (_entries_WIRE_8_pw), // @[TLB.scala:170:77] .io_x_px (_entries_WIRE_8_px), // @[TLB.scala:170:77] .io_x_pr (_entries_WIRE_8_pr), // @[TLB.scala:170:77] .io_x_ppp (_entries_WIRE_8_ppp), // @[TLB.scala:170:77] .io_x_pal (_entries_WIRE_8_pal), // @[TLB.scala:170:77] .io_x_paa (_entries_WIRE_8_paa), // @[TLB.scala:170:77] .io_x_eff (_entries_WIRE_8_eff), // @[TLB.scala:170:77] .io_x_c (_entries_WIRE_8_c), // @[TLB.scala:170:77] .io_x_fragmented_superpage (_entries_WIRE_8_fragmented_superpage), // @[TLB.scala:170:77] .io_y_ppn (_entries_barrier_4_io_y_ppn), .io_y_u (_entries_barrier_4_io_y_u), .io_y_ae_ptw (_entries_barrier_4_io_y_ae_ptw), .io_y_ae_final (_entries_barrier_4_io_y_ae_final), .io_y_ae_stage2 (_entries_barrier_4_io_y_ae_stage2), .io_y_pf (_entries_barrier_4_io_y_pf), .io_y_gf (_entries_barrier_4_io_y_gf), .io_y_sw (_entries_barrier_4_io_y_sw), .io_y_sx (_entries_barrier_4_io_y_sx), .io_y_sr (_entries_barrier_4_io_y_sr), .io_y_hw (_entries_barrier_4_io_y_hw), .io_y_hx (_entries_barrier_4_io_y_hx), .io_y_hr (_entries_barrier_4_io_y_hr), .io_y_pw (_entries_barrier_4_io_y_pw), .io_y_px (_entries_barrier_4_io_y_px), .io_y_pr (_entries_barrier_4_io_y_pr), .io_y_ppp (_entries_barrier_4_io_y_ppp), .io_y_pal (_entries_barrier_4_io_y_pal), .io_y_paa (_entries_barrier_4_io_y_paa), .io_y_eff (_entries_barrier_4_io_y_eff), .io_y_c (_entries_barrier_4_io_y_c) ); // @[package.scala:267:25] OptimizationBarrier_TLBEntryData_111 entries_barrier_5 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_10_ppn), // @[TLB.scala:170:77] .io_x_u (_entries_WIRE_10_u), // @[TLB.scala:170:77] .io_x_g (_entries_WIRE_10_g), // @[TLB.scala:170:77] .io_x_ae_ptw (_entries_WIRE_10_ae_ptw), // @[TLB.scala:170:77] .io_x_ae_final (_entries_WIRE_10_ae_final), // @[TLB.scala:170:77] .io_x_ae_stage2 (_entries_WIRE_10_ae_stage2), // @[TLB.scala:170:77] .io_x_pf (_entries_WIRE_10_pf), // @[TLB.scala:170:77] .io_x_gf (_entries_WIRE_10_gf), // @[TLB.scala:170:77] .io_x_sw (_entries_WIRE_10_sw), // @[TLB.scala:170:77] .io_x_sx (_entries_WIRE_10_sx), // @[TLB.scala:170:77] .io_x_sr (_entries_WIRE_10_sr), // @[TLB.scala:170:77] .io_x_hw (_entries_WIRE_10_hw), // @[TLB.scala:170:77] .io_x_hx (_entries_WIRE_10_hx), // @[TLB.scala:170:77] .io_x_hr (_entries_WIRE_10_hr), // @[TLB.scala:170:77] .io_x_pw (_entries_WIRE_10_pw), // @[TLB.scala:170:77] .io_x_px (_entries_WIRE_10_px), // @[TLB.scala:170:77] .io_x_pr (_entries_WIRE_10_pr), // @[TLB.scala:170:77] .io_x_ppp (_entries_WIRE_10_ppp), // @[TLB.scala:170:77] .io_x_pal (_entries_WIRE_10_pal), // @[TLB.scala:170:77] .io_x_paa (_entries_WIRE_10_paa), // @[TLB.scala:170:77] .io_x_eff (_entries_WIRE_10_eff), // @[TLB.scala:170:77] .io_x_c (_entries_WIRE_10_c), // @[TLB.scala:170:77] .io_x_fragmented_superpage (_entries_WIRE_10_fragmented_superpage), // @[TLB.scala:170:77] .io_y_ppn (_entries_barrier_5_io_y_ppn), .io_y_u (_entries_barrier_5_io_y_u), .io_y_ae_ptw (_entries_barrier_5_io_y_ae_ptw), .io_y_ae_final (_entries_barrier_5_io_y_ae_final), .io_y_ae_stage2 (_entries_barrier_5_io_y_ae_stage2), .io_y_pf (_entries_barrier_5_io_y_pf), .io_y_gf (_entries_barrier_5_io_y_gf), .io_y_sw (_entries_barrier_5_io_y_sw), .io_y_sx (_entries_barrier_5_io_y_sx), .io_y_sr (_entries_barrier_5_io_y_sr), .io_y_hw (_entries_barrier_5_io_y_hw), .io_y_hx (_entries_barrier_5_io_y_hx), .io_y_hr (_entries_barrier_5_io_y_hr) ); // @[package.scala:267:25] assign io_req_ready = io_req_ready_0; // @[TLB.scala:318:7] assign io_resp_miss = io_resp_miss_0; // @[TLB.scala:318:7] assign io_resp_paddr = io_resp_paddr_0; // @[TLB.scala:318:7] assign io_ptw_req_valid = io_ptw_req_valid_0; // @[TLB.scala:318:7] assign io_ptw_req_bits_bits_addr = io_ptw_req_bits_bits_addr_0; // @[TLB.scala:318:7] assign io_ptw_req_bits_bits_need_gpa = io_ptw_req_bits_bits_need_gpa_0; // @[TLB.scala:318:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }

module AsyncQueueSink_DebugInternalBundle( // @[AsyncQueue.scala:136:7] input clock, // @[AsyncQueue.scala:136:7] input reset, // @[AsyncQueue.scala:136:7] output io_deq_valid, // @[AsyncQueue.scala:139:14] output io_deq_bits_resumereq, // @[AsyncQueue.scala:139:14] output [9:0] io_deq_bits_hartsel, // @[AsyncQueue.scala:139:14] output io_deq_bits_ackhavereset, // @[AsyncQueue.scala:139:14] output io_deq_bits_hrmask_0, // @[AsyncQueue.scala:139:14] input io_async_mem_0_resumereq, // @[AsyncQueue.scala:139:14] input [9:0] io_async_mem_0_hartsel, // @[AsyncQueue.scala:139:14] input io_async_mem_0_ackhavereset, // @[AsyncQueue.scala:139:14] input io_async_mem_0_hrmask_0, // @[AsyncQueue.scala:139:14] output io_async_ridx, // @[AsyncQueue.scala:139:14] input io_async_widx, // @[AsyncQueue.scala:139:14] output io_async_safe_ridx_valid, // @[AsyncQueue.scala:139:14] input io_async_safe_widx_valid, // @[AsyncQueue.scala:139:14] input io_async_safe_source_reset_n, // @[AsyncQueue.scala:139:14] output io_async_safe_sink_reset_n // @[AsyncQueue.scala:139:14] ); wire io_deq_valid_0; // @[AsyncQueue.scala:166:29] wire _source_valid_io_out; // @[AsyncQueue.scala:176:31] wire _source_extend_io_out; // @[AsyncQueue.scala:175:31] wire _sink_valid_0_io_out; // @[AsyncQueue.scala:172:33] wire [14:0] _io_deq_bits_deq_bits_reg_io_q; // @[SynchronizerReg.scala:207:25] wire _widx_widx_gray_io_q; // @[ShiftReg.scala:45:23] reg ridx_ridx_bin; // @[AsyncQueue.scala:52:25] wire ridx = _source_valid_io_out & ridx_ridx_bin + io_deq_valid_0; // @[AsyncQueue.scala:52:25, :53:{23,43}, :166:29, :176:31] wire valid = _source_valid_io_out & ridx != _widx_widx_gray_io_q; // @[ShiftReg.scala:45:23] reg valid_reg; // @[AsyncQueue.scala:165:56] assign io_deq_valid_0 = valid_reg & _source_valid_io_out; // @[AsyncQueue.scala:165:56, :166:29, :176:31] reg ridx_gray; // @[AsyncQueue.scala:168:55] always @(posedge clock or posedge reset) begin // @[AsyncQueue.scala:136:7] if (reset) begin // @[AsyncQueue.scala:136:7] ridx_ridx_bin <= 1'h0; // @[AsyncQueue.scala:52:25, :136:7] valid_reg <= 1'h0; // @[AsyncQueue.scala:136:7, :165:56] ridx_gray <= 1'h0; // @[AsyncQueue.scala:136:7, :168:55] end else begin // @[AsyncQueue.scala:136:7] ridx_ridx_bin <= ridx; // @[AsyncQueue.scala:52:25, :53:23] valid_reg <= valid; // @[AsyncQueue.scala:150:28, :165:56] ridx_gray <= ridx; // @[AsyncQueue.scala:53:23, :168:55] end always @(posedge, posedge)

Generate the Verilog code corresponding to the following Chisel files. File Crossing.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.interrupts import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg} @deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2") class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val intnode = IntAdapterNode() lazy val module = new Impl class Impl extends LazyModuleImp(this) { (intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) => out := SynchronizerShiftReg(in, sync) } } } object IntSyncCrossingSource { def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) = { val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered)) intsource.node } } class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule { val node = IntSyncSourceNode(alreadyRegistered) lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl) class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := AsyncResetReg(Cat(in.reverse)).asBools } } class ImplRegistered extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}_Registered" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := in } } } object IntSyncCrossingSink { @deprecated("IntSyncCrossingSink which used the `sync` parameter to determine crossing type is deprecated. Use IntSyncAsyncCrossingSink, IntSyncRationalCrossingSink, or IntSyncSyncCrossingSink instead for > 1, 1, and 0 sync values respectively", "rocket-chip 1.2") def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncAsyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(sync) lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = s"IntSyncAsyncCrossingSink_n${node.out.size}x${node.out.head._1.size}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := SynchronizerShiftReg(in.sync, sync) } } } object IntSyncAsyncCrossingSink { def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncSyncCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(0) lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncSyncCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := in.sync } } } object IntSyncSyncCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncSyncCrossingSink()) intsink.node } } class IntSyncRationalCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(1) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncRationalCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := RegNext(in.sync) } } } object IntSyncRationalCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncRationalCrossingSink()) intsink.node } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File AsyncResetReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ /** This black-boxes an Async Reset * (or Set) * Register. * * Because Chisel doesn't support * parameterized black boxes, * we unfortunately have to * instantiate a number of these. * * We also have to hard-code the set/ * reset behavior. * * Do not confuse an asynchronous * reset signal with an asynchronously * reset reg. You should still * properly synchronize your reset * deassertion. * * @param d Data input * @param q Data Output * @param clk Clock Input * @param rst Reset Input * @param en Write Enable Input * */ class AsyncResetReg(resetValue: Int = 0) extends RawModule { val io = IO(new Bundle { val d = Input(Bool()) val q = Output(Bool()) val en = Input(Bool()) val clk = Input(Clock()) val rst = Input(Reset()) }) val reg = withClockAndReset(io.clk, io.rst.asAsyncReset)(RegInit(resetValue.U(1.W))) when (io.en) { reg := io.d } io.q := reg } class SimpleRegIO(val w: Int) extends Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) } class AsyncResetRegVec(val w: Int, val init: BigInt) extends Module { override def desiredName = s"AsyncResetRegVec_w${w}_i${init}" val io = IO(new SimpleRegIO(w)) val reg = withReset(reset.asAsyncReset)(RegInit(init.U(w.W))) when (io.en) { reg := io.d } io.q := reg } object AsyncResetReg { // Create Single Registers def apply(d: Bool, clk: Clock, rst: Bool, init: Boolean, name: Option[String]): Bool = { val reg = Module(new AsyncResetReg(if (init) 1 else 0)) reg.io.d := d reg.io.clk := clk reg.io.rst := rst reg.io.en := true.B name.foreach(reg.suggestName(_)) reg.io.q } def apply(d: Bool, clk: Clock, rst: Bool): Bool = apply(d, clk, rst, false, None) def apply(d: Bool, clk: Clock, rst: Bool, name: String): Bool = apply(d, clk, rst, false, Some(name)) // Create Vectors of Registers def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: Option[String] = None): UInt = { val w = updateData.getWidth max resetData.bitLength val reg = Module(new AsyncResetRegVec(w, resetData)) name.foreach(reg.suggestName(_)) reg.io.d := updateData reg.io.en := enable reg.io.q } def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: String): UInt = apply(updateData, resetData, enable, Some(name)) def apply(updateData: UInt, resetData: BigInt): UInt = apply(updateData, resetData, enable = true.B) def apply(updateData: UInt, resetData: BigInt, name: String): UInt = apply(updateData, resetData, enable = true.B, Some(name)) def apply(updateData: UInt, enable: Bool): UInt = apply(updateData, resetData=BigInt(0), enable) def apply(updateData: UInt, enable: Bool, name: String): UInt = apply(updateData, resetData = BigInt(0), enable, Some(name)) def apply(updateData: UInt): UInt = apply(updateData, resetData = BigInt(0), enable = true.B) def apply(updateData: UInt, name:String): UInt = apply(updateData, resetData = BigInt(0), enable = true.B, Some(name)) }

module IntSyncCrossingSource_n1x2( // @[Crossing.scala:41:9] input clock, // @[Crossing.scala:41:9] input reset, // @[Crossing.scala:41:9] input auto_in_0, // @[LazyModuleImp.scala:107:25] input auto_in_1, // @[LazyModuleImp.scala:107:25] output auto_out_sync_0, // @[LazyModuleImp.scala:107:25] output auto_out_sync_1 // @[LazyModuleImp.scala:107:25] ); wire [1:0] _reg_io_q; // @[AsyncResetReg.scala:86:21] AsyncResetRegVec_w2_i0 reg_0 ( // @[AsyncResetReg.scala:86:21] .clock (clock), .reset (reset), .io_d ({auto_in_1, auto_in_0}), // @[Crossing.scala:45:36] .io_q (_reg_io_q) ); // @[AsyncResetReg.scala:86:21] assign auto_out_sync_0 = _reg_io_q[0]; // @[AsyncResetReg.scala:86:21] assign auto_out_sync_1 = _reg_io_q[1]; // @[AsyncResetReg.scala:86:21] endmodule

Generate the Verilog code corresponding to the following Chisel files. File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File Nodes.scala: package constellation.channel import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Parameters, Field} import freechips.rocketchip.diplomacy._ case class EmptyParams() case class ChannelEdgeParams(cp: ChannelParams, p: Parameters) object ChannelImp extends SimpleNodeImp[EmptyParams, ChannelParams, ChannelEdgeParams, Channel] { def edge(pd: EmptyParams, pu: ChannelParams, p: Parameters, sourceInfo: SourceInfo) = { ChannelEdgeParams(pu, p) } def bundle(e: ChannelEdgeParams) = new Channel(e.cp)(e.p) def render(e: ChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) { RenderedEdge(colour = "ffffff", label = "X") } else { RenderedEdge(colour = "#0000ff", label = e.cp.payloadBits.toString) } override def monitor(bundle: Channel, edge: ChannelEdgeParams): Unit = { val monitor = Module(new NoCMonitor(edge.cp)(edge.p)) monitor.io.in := bundle } // TODO: Add nodepath stuff? override def mixO, override def mixI } case class ChannelSourceNode(val destId: Int)(implicit valName: ValName) extends SourceNode(ChannelImp)(Seq(EmptyParams())) case class ChannelDestNode(val destParams: ChannelParams)(implicit valName: ValName) extends SinkNode(ChannelImp)(Seq(destParams)) case class ChannelAdapterNode( slaveFn: ChannelParams => ChannelParams = { d => d })( implicit valName: ValName) extends AdapterNode(ChannelImp)((e: EmptyParams) => e, slaveFn) case class ChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(ChannelImp)() case class ChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(ChannelImp)() case class IngressChannelEdgeParams(cp: IngressChannelParams, p: Parameters) case class EgressChannelEdgeParams(cp: EgressChannelParams, p: Parameters) object IngressChannelImp extends SimpleNodeImp[EmptyParams, IngressChannelParams, IngressChannelEdgeParams, IngressChannel] { def edge(pd: EmptyParams, pu: IngressChannelParams, p: Parameters, sourceInfo: SourceInfo) = { IngressChannelEdgeParams(pu, p) } def bundle(e: IngressChannelEdgeParams) = new IngressChannel(e.cp)(e.p) def render(e: IngressChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) { RenderedEdge(colour = "ffffff", label = "X") } else { RenderedEdge(colour = "#00ff00", label = e.cp.payloadBits.toString) } } object EgressChannelImp extends SimpleNodeImp[EmptyParams, EgressChannelParams, EgressChannelEdgeParams, EgressChannel] { def edge(pd: EmptyParams, pu: EgressChannelParams, p: Parameters, sourceInfo: SourceInfo) = { EgressChannelEdgeParams(pu, p) } def bundle(e: EgressChannelEdgeParams) = new EgressChannel(e.cp)(e.p) def render(e: EgressChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) { RenderedEdge(colour = "ffffff", label = "X") } else { RenderedEdge(colour = "#ff0000", label = e.cp.payloadBits.toString) } } case class IngressChannelSourceNode(val destId: Int)(implicit valName: ValName) extends SourceNode(IngressChannelImp)(Seq(EmptyParams())) case class IngressChannelDestNode(val destParams: IngressChannelParams)(implicit valName: ValName) extends SinkNode(IngressChannelImp)(Seq(destParams)) case class EgressChannelSourceNode(val egressId: Int)(implicit valName: ValName) extends SourceNode(EgressChannelImp)(Seq(EmptyParams())) case class EgressChannelDestNode(val destParams: EgressChannelParams)(implicit valName: ValName) extends SinkNode(EgressChannelImp)(Seq(destParams)) case class IngressChannelAdapterNode( slaveFn: IngressChannelParams => IngressChannelParams = { d => d })( implicit valName: ValName) extends AdapterNode(IngressChannelImp)(m => m, slaveFn) case class EgressChannelAdapterNode( slaveFn: EgressChannelParams => EgressChannelParams = { d => d })( implicit valName: ValName) extends AdapterNode(EgressChannelImp)(m => m, slaveFn) case class IngressChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(IngressChannelImp)() case class EgressChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(EgressChannelImp)() case class IngressChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(IngressChannelImp)() case class EgressChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(EgressChannelImp)() File Router.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{RoutingRelation} import constellation.noc.{HasNoCParams} case class UserRouterParams( // Payload width. Must match payload width on all channels attached to this routing node payloadBits: Int = 64, // Combines SA and ST stages (removes pipeline register) combineSAST: Boolean = false, // Combines RC and VA stages (removes pipeline register) combineRCVA: Boolean = false, // Adds combinational path from SA to VA coupleSAVA: Boolean = false, vcAllocator: VCAllocatorParams => Parameters => VCAllocator = (vP) => (p) => new RotatingSingleVCAllocator(vP)(p) ) case class RouterParams( nodeId: Int, nIngress: Int, nEgress: Int, user: UserRouterParams ) trait HasRouterOutputParams { def outParams: Seq[ChannelParams] def egressParams: Seq[EgressChannelParams] def allOutParams = outParams ++ egressParams def nOutputs = outParams.size def nEgress = egressParams.size def nAllOutputs = allOutParams.size } trait HasRouterInputParams { def inParams: Seq[ChannelParams] def ingressParams: Seq[IngressChannelParams] def allInParams = inParams ++ ingressParams def nInputs = inParams.size def nIngress = ingressParams.size def nAllInputs = allInParams.size } trait HasRouterParams { def routerParams: RouterParams def nodeId = routerParams.nodeId def payloadBits = routerParams.user.payloadBits } class DebugBundle(val nIn: Int) extends Bundle { val va_stall = Vec(nIn, UInt()) val sa_stall = Vec(nIn, UInt()) } class Router( val routerParams: RouterParams, preDiplomaticInParams: Seq[ChannelParams], preDiplomaticIngressParams: Seq[IngressChannelParams], outDests: Seq[Int], egressIds: Seq[Int] )(implicit p: Parameters) extends LazyModule with HasNoCParams with HasRouterParams { val allPreDiplomaticInParams = preDiplomaticInParams ++ preDiplomaticIngressParams val destNodes = preDiplomaticInParams.map(u => ChannelDestNode(u)) val sourceNodes = outDests.map(u => ChannelSourceNode(u)) val ingressNodes = preDiplomaticIngressParams.map(u => IngressChannelDestNode(u)) val egressNodes = egressIds.map(u => EgressChannelSourceNode(u)) val debugNode = BundleBridgeSource(() => new DebugBundle(allPreDiplomaticInParams.size)) val ctrlNode = if (hasCtrl) Some(BundleBridgeSource(() => new RouterCtrlBundle)) else None def inParams = module.inParams def outParams = module.outParams def ingressParams = module.ingressParams def egressParams = module.egressParams lazy val module = new LazyModuleImp(this) with HasRouterInputParams with HasRouterOutputParams { val (io_in, edgesIn) = destNodes.map(_.in(0)).unzip val (io_out, edgesOut) = sourceNodes.map(_.out(0)).unzip val (io_ingress, edgesIngress) = ingressNodes.map(_.in(0)).unzip val (io_egress, edgesEgress) = egressNodes.map(_.out(0)).unzip val io_debug = debugNode.out(0)._1 val inParams = edgesIn.map(_.cp) val outParams = edgesOut.map(_.cp) val ingressParams = edgesIngress.map(_.cp) val egressParams = edgesEgress.map(_.cp) allOutParams.foreach(u => require(u.srcId == nodeId && u.payloadBits == routerParams.user.payloadBits)) allInParams.foreach(u => require(u.destId == nodeId && u.payloadBits == routerParams.user.payloadBits)) require(nIngress == routerParams.nIngress) require(nEgress == routerParams.nEgress) require(nAllInputs >= 1) require(nAllOutputs >= 1) require(nodeId < (1 << nodeIdBits)) val input_units = inParams.zipWithIndex.map { case (u,i) => Module(new InputUnit(u, outParams, egressParams, routerParams.user.combineRCVA, routerParams.user.combineSAST)) .suggestName(s"input_unit_${i}_from_${u.srcId}") } val ingress_units = ingressParams.zipWithIndex.map { case (u,i) => Module(new IngressUnit(i, u, outParams, egressParams, routerParams.user.combineRCVA, routerParams.user.combineSAST)) .suggestName(s"ingress_unit_${i+nInputs}_from_${u.ingressId}") } val all_input_units = input_units ++ ingress_units val output_units = outParams.zipWithIndex.map { case (u,i) => Module(new OutputUnit(inParams, ingressParams, u)) .suggestName(s"output_unit_${i}_to_${u.destId}")} val egress_units = egressParams.zipWithIndex.map { case (u,i) => Module(new EgressUnit(routerParams.user.coupleSAVA && all_input_units.size == 1, routerParams.user.combineSAST, inParams, ingressParams, u)) .suggestName(s"egress_unit_${i+nOutputs}_to_${u.egressId}")} val all_output_units = output_units ++ egress_units val switch = Module(new Switch(routerParams, inParams, outParams, ingressParams, egressParams)) val switch_allocator = Module(new SwitchAllocator(routerParams, inParams, outParams, ingressParams, egressParams)) val vc_allocator = Module(routerParams.user.vcAllocator( VCAllocatorParams(routerParams, inParams, outParams, ingressParams, egressParams) )(p)) val route_computer = Module(new RouteComputer(routerParams, inParams, outParams, ingressParams, egressParams)) val fires_count = WireInit(PopCount(vc_allocator.io.req.map(_.fire))) dontTouch(fires_count) (io_in zip input_units ).foreach { case (i,u) => u.io.in <> i } (io_ingress zip ingress_units).foreach { case (i,u) => u.io.in <> i.flit } (output_units zip io_out ).foreach { case (u,o) => o <> u.io.out } (egress_units zip io_egress).foreach { case (u,o) => o.flit <> u.io.out } (route_computer.io.req zip all_input_units).foreach { case (i,u) => i <> u.io.router_req } (all_input_units zip route_computer.io.resp).foreach { case (u,o) => u.io.router_resp <> o } (vc_allocator.io.req zip all_input_units).foreach { case (i,u) => i <> u.io.vcalloc_req } (all_input_units zip vc_allocator.io.resp).foreach { case (u,o) => u.io.vcalloc_resp <> o } (all_output_units zip vc_allocator.io.out_allocs).foreach { case (u,a) => u.io.allocs <> a } (vc_allocator.io.channel_status zip all_output_units).foreach { case (a,u) => a := u.io.channel_status } all_input_units.foreach(in => all_output_units.zipWithIndex.foreach { case (out,outIdx) => in.io.out_credit_available(outIdx) := out.io.credit_available }) (all_input_units zip switch_allocator.io.req).foreach { case (u,r) => r <> u.io.salloc_req } (all_output_units zip switch_allocator.io.credit_alloc).foreach { case (u,a) => u.io.credit_alloc := a } (switch.io.in zip all_input_units).foreach { case (i,u) => i <> u.io.out } (all_output_units zip switch.io.out).foreach { case (u,o) => u.io.in <> o } switch.io.sel := (if (routerParams.user.combineSAST) { switch_allocator.io.switch_sel } else { RegNext(switch_allocator.io.switch_sel) }) if (hasCtrl) { val io_ctrl = ctrlNode.get.out(0)._1 val ctrl = Module(new RouterControlUnit(routerParams, inParams, outParams, ingressParams, egressParams)) io_ctrl <> ctrl.io.ctrl (all_input_units zip ctrl.io.in_block ).foreach { case (l,r) => l.io.block := r } (all_input_units zip ctrl.io.in_fire ).foreach { case (l,r) => r := l.io.out.map(_.valid) } } else { input_units.foreach(_.io.block := false.B) ingress_units.foreach(_.io.block := false.B) } (io_debug.va_stall zip all_input_units.map(_.io.debug.va_stall)).map { case (l,r) => l := r } (io_debug.sa_stall zip all_input_units.map(_.io.debug.sa_stall)).map { case (l,r) => l := r } val debug_tsc = RegInit(0.U(64.W)) debug_tsc := debug_tsc + 1.U val debug_sample = RegInit(0.U(64.W)) debug_sample := debug_sample + 1.U val sample_rate = PlusArg("noc_util_sample_rate", width=20) when (debug_sample === sample_rate - 1.U) { debug_sample := 0.U } def sample(fire: Bool, s: String) = { val util_ctr = RegInit(0.U(64.W)) val fired = RegInit(false.B) util_ctr := util_ctr + fire fired := fired || fire when (sample_rate =/= 0.U && debug_sample === sample_rate - 1.U && fired) { val fmtStr = s"nocsample %d $s %d\n" printf(fmtStr, debug_tsc, util_ctr); fired := fire } } destNodes.map(_.in(0)).foreach { case (in, edge) => in.flit.map { f => sample(f.fire, s"${edge.cp.srcId} $nodeId") } } ingressNodes.map(_.in(0)).foreach { case (in, edge) => sample(in.flit.fire, s"i${edge.cp.asInstanceOf[IngressChannelParams].ingressId} $nodeId") } egressNodes.map(_.out(0)).foreach { case (out, edge) => sample(out.flit.fire, s"$nodeId e${edge.cp.asInstanceOf[EgressChannelParams].egressId}") } } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } }

module Router_22( // @[Router.scala:89:25] input clock, // @[Router.scala:89:25] input reset, // @[Router.scala:89:25] output [4:0] auto_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25] output [4:0] auto_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25] output [4:0] auto_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25] output [4:0] auto_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_source_nodes_out_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [5:0] auto_source_nodes_out_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [5:0] auto_source_nodes_out_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [21:0] auto_source_nodes_out_1_credit_return, // @[LazyModuleImp.scala:107:25] input [21:0] auto_source_nodes_out_1_vc_free, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_source_nodes_out_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [5:0] auto_source_nodes_out_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [5:0] auto_source_nodes_out_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [21:0] auto_source_nodes_out_0_credit_return, // @[LazyModuleImp.scala:107:25] input [21:0] auto_source_nodes_out_0_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_dest_nodes_in_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [5:0] auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [5:0] auto_dest_nodes_in_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [21:0] auto_dest_nodes_in_1_credit_return, // @[LazyModuleImp.scala:107:25] output [21:0] auto_dest_nodes_in_1_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_dest_nodes_in_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [5:0] auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [5:0] auto_dest_nodes_in_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [21:0] auto_dest_nodes_in_0_credit_return, // @[LazyModuleImp.scala:107:25] output [21:0] auto_dest_nodes_in_0_vc_free // @[LazyModuleImp.scala:107:25] ); wire [19:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire _route_computer_io_resp_1_vc_sel_0_11; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_15; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_19; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_20; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_21; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_12; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_13; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_16; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_17; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_20; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_21; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_0_2; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_0_3; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_0_8; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_0_9; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_0_10; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_0_11; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_0_12; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_0_13; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_0_14; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_0_15; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_0_17; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_0_18; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_0_19; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_0_20; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_0_21; // @[Router.scala:136:32] wire _vc_allocator_io_req_1_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_0_ready; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_11; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_15; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_19; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_20; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_21; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_12; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_13; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_16; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_17; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_20; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_21; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_0_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_0_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_0_8; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_0_9; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_0_10; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_0_11; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_0_12; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_0_13; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_0_14; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_0_15; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_0_17; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_0_18; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_0_19; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_0_20; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_0_21; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_12_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_13_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_16_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_17_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_20_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_21_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_2_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_3_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_8_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_9_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_10_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_11_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_12_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_13_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_14_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_15_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_17_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_18_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_19_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_20_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_21_alloc; // @[Router.scala:133:30] wire _switch_allocator_io_req_1_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_0_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_12_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_13_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_16_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_17_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_20_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_21_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_2_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_3_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_8_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_9_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_10_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_11_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_12_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_13_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_14_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_15_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_17_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_18_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_19_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_20_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_21_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_0_0; // @[Router.scala:132:34] wire _switch_io_out_1_0_valid; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_1_0_bits_payload; // @[Router.scala:131:24] wire [3:0] _switch_io_out_1_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [5:0] _switch_io_out_1_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [2:0] _switch_io_out_1_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [5:0] _switch_io_out_1_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [2:0] _switch_io_out_1_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_1_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _switch_io_out_0_0_valid; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_0_0_bits_payload; // @[Router.scala:131:24] wire [3:0] _switch_io_out_0_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [5:0] _switch_io_out_0_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [2:0] _switch_io_out_0_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [5:0] _switch_io_out_0_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [2:0] _switch_io_out_0_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_0_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _output_unit_1_to_37_io_credit_available_12; // @[Router.scala:122:13] wire _output_unit_1_to_37_io_credit_available_13; // @[Router.scala:122:13] wire _output_unit_1_to_37_io_credit_available_16; // @[Router.scala:122:13] wire _output_unit_1_to_37_io_credit_available_17; // @[Router.scala:122:13] wire _output_unit_1_to_37_io_credit_available_20; // @[Router.scala:122:13] wire _output_unit_1_to_37_io_credit_available_21; // @[Router.scala:122:13] wire _output_unit_1_to_37_io_channel_status_12_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_37_io_channel_status_13_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_37_io_channel_status_16_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_37_io_channel_status_17_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_37_io_channel_status_20_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_37_io_channel_status_21_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_28_io_credit_available_2; // @[Router.scala:122:13] wire _output_unit_0_to_28_io_credit_available_3; // @[Router.scala:122:13] wire _output_unit_0_to_28_io_credit_available_8; // @[Router.scala:122:13] wire _output_unit_0_to_28_io_credit_available_9; // @[Router.scala:122:13] wire _output_unit_0_to_28_io_credit_available_10; // @[Router.scala:122:13] wire _output_unit_0_to_28_io_credit_available_11; // @[Router.scala:122:13] wire _output_unit_0_to_28_io_credit_available_12; // @[Router.scala:122:13] wire _output_unit_0_to_28_io_credit_available_13; // @[Router.scala:122:13] wire _output_unit_0_to_28_io_credit_available_14; // @[Router.scala:122:13] wire _output_unit_0_to_28_io_credit_available_15; // @[Router.scala:122:13] wire _output_unit_0_to_28_io_credit_available_17; // @[Router.scala:122:13] wire _output_unit_0_to_28_io_credit_available_18; // @[Router.scala:122:13] wire _output_unit_0_to_28_io_credit_available_19; // @[Router.scala:122:13] wire _output_unit_0_to_28_io_credit_available_20; // @[Router.scala:122:13] wire _output_unit_0_to_28_io_credit_available_21; // @[Router.scala:122:13] wire _output_unit_0_to_28_io_channel_status_2_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_28_io_channel_status_3_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_28_io_channel_status_8_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_28_io_channel_status_9_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_28_io_channel_status_10_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_28_io_channel_status_11_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_28_io_channel_status_12_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_28_io_channel_status_13_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_28_io_channel_status_14_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_28_io_channel_status_15_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_28_io_channel_status_17_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_28_io_channel_status_18_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_28_io_channel_status_19_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_28_io_channel_status_20_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_28_io_channel_status_21_occupied; // @[Router.scala:122:13] wire [4:0] _input_unit_1_from_37_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire [3:0] _input_unit_1_from_37_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [5:0] _input_unit_1_from_37_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_37_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [5:0] _input_unit_1_from_37_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_37_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_vcalloc_req_bits_vc_sel_0_11; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_vcalloc_req_bits_vc_sel_0_15; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_vcalloc_req_bits_vc_sel_0_19; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_vcalloc_req_bits_vc_sel_0_20; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_vcalloc_req_bits_vc_sel_0_21; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_salloc_req_0_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_salloc_req_0_bits_vc_sel_1_3; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_salloc_req_0_bits_vc_sel_1_8; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_salloc_req_0_bits_vc_sel_1_9; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_salloc_req_0_bits_vc_sel_1_10; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_salloc_req_0_bits_vc_sel_1_11; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_salloc_req_0_bits_vc_sel_1_12; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_salloc_req_0_bits_vc_sel_1_13; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_salloc_req_0_bits_vc_sel_1_14; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_salloc_req_0_bits_vc_sel_1_15; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_salloc_req_0_bits_vc_sel_1_16; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_salloc_req_0_bits_vc_sel_1_17; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_salloc_req_0_bits_vc_sel_1_18; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_salloc_req_0_bits_vc_sel_1_19; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_salloc_req_0_bits_vc_sel_1_20; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_salloc_req_0_bits_vc_sel_1_21; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_salloc_req_0_bits_vc_sel_0_8; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_salloc_req_0_bits_vc_sel_0_9; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_salloc_req_0_bits_vc_sel_0_10; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_salloc_req_0_bits_vc_sel_0_11; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_salloc_req_0_bits_vc_sel_0_12; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_salloc_req_0_bits_vc_sel_0_13; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_salloc_req_0_bits_vc_sel_0_14; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_salloc_req_0_bits_vc_sel_0_15; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_salloc_req_0_bits_vc_sel_0_16; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_salloc_req_0_bits_vc_sel_0_17; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_salloc_req_0_bits_vc_sel_0_18; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_salloc_req_0_bits_vc_sel_0_19; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_salloc_req_0_bits_vc_sel_0_20; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_salloc_req_0_bits_vc_sel_0_21; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_1_from_37_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [72:0] _input_unit_1_from_37_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [3:0] _input_unit_1_from_37_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [5:0] _input_unit_1_from_37_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_37_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [5:0] _input_unit_1_from_37_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_37_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_1_from_37_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [4:0] _input_unit_0_from_26_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_26_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [5:0] _input_unit_0_from_26_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_26_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [5:0] _input_unit_0_from_26_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_26_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_vcalloc_req_bits_vc_sel_1_12; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_vcalloc_req_bits_vc_sel_1_13; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_vcalloc_req_bits_vc_sel_1_16; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_vcalloc_req_bits_vc_sel_1_17; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_vcalloc_req_bits_vc_sel_1_20; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_vcalloc_req_bits_vc_sel_1_21; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_vcalloc_req_bits_vc_sel_0_8; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_vcalloc_req_bits_vc_sel_0_9; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_vcalloc_req_bits_vc_sel_0_10; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_vcalloc_req_bits_vc_sel_0_11; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_vcalloc_req_bits_vc_sel_0_12; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_vcalloc_req_bits_vc_sel_0_13; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_vcalloc_req_bits_vc_sel_0_14; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_vcalloc_req_bits_vc_sel_0_15; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_vcalloc_req_bits_vc_sel_0_17; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_vcalloc_req_bits_vc_sel_0_18; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_vcalloc_req_bits_vc_sel_0_19; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_vcalloc_req_bits_vc_sel_0_20; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_vcalloc_req_bits_vc_sel_0_21; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_salloc_req_0_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_salloc_req_0_bits_vc_sel_1_3; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_salloc_req_0_bits_vc_sel_1_8; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_salloc_req_0_bits_vc_sel_1_9; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_salloc_req_0_bits_vc_sel_1_10; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_salloc_req_0_bits_vc_sel_1_11; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_salloc_req_0_bits_vc_sel_1_12; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_salloc_req_0_bits_vc_sel_1_13; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_salloc_req_0_bits_vc_sel_1_14; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_salloc_req_0_bits_vc_sel_1_15; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_salloc_req_0_bits_vc_sel_1_16; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_salloc_req_0_bits_vc_sel_1_17; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_salloc_req_0_bits_vc_sel_1_18; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_salloc_req_0_bits_vc_sel_1_19; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_salloc_req_0_bits_vc_sel_1_20; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_salloc_req_0_bits_vc_sel_1_21; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_salloc_req_0_bits_vc_sel_0_8; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_salloc_req_0_bits_vc_sel_0_9; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_salloc_req_0_bits_vc_sel_0_10; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_salloc_req_0_bits_vc_sel_0_11; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_salloc_req_0_bits_vc_sel_0_12; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_salloc_req_0_bits_vc_sel_0_13; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_salloc_req_0_bits_vc_sel_0_14; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_salloc_req_0_bits_vc_sel_0_15; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_salloc_req_0_bits_vc_sel_0_16; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_salloc_req_0_bits_vc_sel_0_17; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_salloc_req_0_bits_vc_sel_0_18; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_salloc_req_0_bits_vc_sel_0_19; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_salloc_req_0_bits_vc_sel_0_20; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_salloc_req_0_bits_vc_sel_0_21; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_0_from_26_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [72:0] _input_unit_0_from_26_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_26_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [5:0] _input_unit_0_from_26_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_26_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [5:0] _input_unit_0_from_26_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_26_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_0_from_26_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [1:0] fires_count = {1'h0, _vc_allocator_io_req_0_ready & _input_unit_0_from_26_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_1_ready & _input_unit_1_from_37_io_vcalloc_req_valid}; // @[Decoupled.scala:51:35] reg REG_1_0_1_0; // @[Router.scala:178:14] reg REG_1_0_0_0; // @[Router.scala:178:14] reg REG_0_0_1_0; // @[Router.scala:178:14] reg REG_0_0_0_0; // @[Router.scala:178:14] reg [63:0] debug_tsc; // @[Router.scala:195:28] reg [63:0] debug_sample; // @[Router.scala:197:31] wire _GEN = debug_sample == {44'h0, _plusarg_reader_out - 20'h1}; // @[PlusArg.scala:80:11] reg [63:0] util_ctr; // @[Router.scala:203:29] reg fired; // @[Router.scala:204:26] wire _GEN_0 = (|_plusarg_reader_out) & _GEN; // @[PlusArg.scala:80:11] wire _GEN_1 = _GEN_0 & fired; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_1; // @[Router.scala:203:29] reg fired_1; // @[Router.scala:204:26] wire _GEN_2 = _GEN_0 & fired_1; // @[Router.scala:204:26, :207:{33,71}]

Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module TLMonitor_49( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [11:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [25:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [11:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [11:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [25:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [11:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [25:0] _c_first_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_first_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_first_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_first_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_set_wo_ready_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_set_wo_ready_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_opcodes_set_interm_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_opcodes_set_interm_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_sizes_set_interm_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_sizes_set_interm_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_opcodes_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_opcodes_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_sizes_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_sizes_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_probe_ack_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_probe_ack_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_probe_ack_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_probe_ack_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _same_cycle_resp_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _same_cycle_resp_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _same_cycle_resp_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _same_cycle_resp_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _same_cycle_resp_WIRE_4_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _same_cycle_resp_WIRE_5_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_2_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_3_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_wo_ready_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_wo_ready_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_interm_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_interm_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_interm_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_interm_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_2_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_3_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_2_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_3_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_4_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_5_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [32769:0] _c_sizes_set_T_1 = 32770'h0; // @[Monitor.scala:768:52] wire [14:0] _c_opcodes_set_T = 15'h0; // @[Monitor.scala:767:79] wire [14:0] _c_sizes_set_T = 15'h0; // @[Monitor.scala:768:77] wire [32770:0] _c_opcodes_set_T_1 = 32771'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [4095:0] _c_set_wo_ready_T = 4096'h1; // @[OneHot.scala:58:35] wire [4095:0] _c_set_T = 4096'h1; // @[OneHot.scala:58:35] wire [8255:0] c_opcodes_set = 8256'h0; // @[Monitor.scala:740:34] wire [8255:0] c_sizes_set = 8256'h0; // @[Monitor.scala:741:34] wire [2063:0] c_set = 2064'h0; // @[Monitor.scala:738:34] wire [2063:0] c_set_wo_ready = 2064'h0; // @[Monitor.scala:739:34] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [11:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 12'h810; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [25:0] _is_aligned_T = {23'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 26'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [11:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [11:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 12'h810; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_665 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_665; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_665; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [11:0] source; // @[Monitor.scala:390:22] reg [25:0] address; // @[Monitor.scala:391:22] wire _T_733 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_733; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [11:0] source_1; // @[Monitor.scala:541:22] reg [2063:0] inflight; // @[Monitor.scala:614:27] reg [8255:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [8255:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [2063:0] a_set; // @[Monitor.scala:626:34] wire [2063:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [8255:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [8255:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [14:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [14:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [14:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [14:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [14:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [14:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [14:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [14:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [14:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [8255:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [8255:0] _a_opcode_lookup_T_6 = {8252'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [8255:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[8255:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [8255:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [8255:0] _a_size_lookup_T_6 = {8252'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [8255:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[8255:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [4095:0] _GEN_2 = 4096'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [4095:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [4095:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_665 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [14:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [14:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [14:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [32770:0] _a_opcodes_set_T_1 = {32767'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[8255:0] : 8256'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [32769:0] _a_sizes_set_T_1 = {32767'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[8255:0] : 8256'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [2063:0] d_clr; // @[Monitor.scala:664:34] wire [2063:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [8255:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [8255:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [4095:0] _GEN_5 = 4096'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [4095:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [4095:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [4095:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [4095:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_733 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire [32782:0] _d_opcodes_clr_T_5 = 32783'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[8255:0] : 8256'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [32782:0] _d_sizes_clr_T_5 = 32783'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[8255:0] : 8256'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [2063:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [2063:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [2063:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [8255:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [8255:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [8255:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [8255:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [8255:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [8255:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [2063:0] inflight_1; // @[Monitor.scala:726:35] wire [2063:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [8255:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [8255:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [8255:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [8255:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [8255:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [8255:0] _c_opcode_lookup_T_6 = {8252'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [8255:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[8255:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [8255:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [8255:0] _c_size_lookup_T_6 = {8252'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [8255:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[8255:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [2063:0] d_clr_1; // @[Monitor.scala:774:34] wire [2063:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [8255:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [8255:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_709 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_709 & d_release_ack_1 ? _d_clr_wo_ready_T_1[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire _T_691 = _T_733 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_691 ? _d_clr_T_1[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire [32782:0] _d_opcodes_clr_T_11 = 32783'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_691 ? _d_opcodes_clr_T_11[8255:0] : 8256'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [32782:0] _d_sizes_clr_T_11 = 32783'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_691 ? _d_sizes_clr_T_11[8255:0] : 8256'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 12'h0; // @[Monitor.scala:36:7, :795:113] wire [2063:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [2063:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [8255:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [8255:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [8255:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [8255:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module TLMonitor_49( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [15:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [127:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [2:0] io_in_b_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_b_bits_size, // @[Monitor.scala:20:14] input [2:0] io_in_b_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input [15:0] io_in_b_bits_mask, // @[Monitor.scala:20:14] input [127:0] io_in_b_bits_data, // @[Monitor.scala:20:14] input io_in_b_bits_corrupt, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input [127:0] io_in_c_bits_data, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [127:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_ready, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [3:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [15:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [127:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7] wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_b_bits_opcode_0 = io_in_b_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_b_bits_size_0 = io_in_b_bits_size; // @[Monitor.scala:36:7] wire [2:0] io_in_b_bits_source_0 = io_in_b_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7] wire [15:0] io_in_b_bits_mask_0 = io_in_b_bits_mask; // @[Monitor.scala:36:7] wire [127:0] io_in_b_bits_data_0 = io_in_b_bits_data; // @[Monitor.scala:36:7] wire io_in_b_bits_corrupt_0 = io_in_b_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7] wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7] wire [127:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [127:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_e_ready_0 = io_in_e_ready; // @[Monitor.scala:36:7] wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7] wire [3:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire io_in_c_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_7 = 1'h0; // @[Parameters.scala:54:10] wire _legal_source_T = 1'h0; // @[Parameters.scala:54:10] wire _legal_source_T_7 = 1'h0; // @[Mux.scala:30:73] wire _source_ok_T_14 = 1'h0; // @[Parameters.scala:54:10] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [7:0] b_first_beats1 = 8'h0; // @[Edges.scala:221:14] wire [7:0] b_first_count = 8'h0; // @[Edges.scala:234:25] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_10 = 1'h1; // @[Parameters.scala:54:67] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire _legal_source_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _legal_source_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_16 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:54:67] wire sink_ok_1 = 1'h1; // @[Monitor.scala:367:31] wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire b_first_last = 1'h1; // @[Edges.scala:232:33] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [2:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _mask_sizeOH_T_3 = io_in_b_bits_size_0; // @[Misc.scala:202:34] wire [2:0] _uncommonBits_T_11 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _legal_source_uncommonBits_T = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_12 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T = io_in_b_bits_address_0; // @[Monitor.scala:36:7] wire [2:0] _source_ok_uncommonBits_T_2 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_13 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_14 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_15 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_16 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_17 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_70 = io_in_c_bits_address_0; // @[Monitor.scala:36:7] wire [2:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire _source_ok_T_6 = io_in_a_bits_source_0 == 3'h5; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire source_ok = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire [3:0] mask_sizeOH = {_mask_sizeOH_T_2[3:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_sub_0_1 = |(io_in_a_bits_size_0[3:2]); // @[Misc.scala:206:21] wire mask_sub_sub_sub_size = mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_sub_bit = io_in_a_bits_address_0[3]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_1_2 = mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_nbit = ~mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_0_2 = mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_acc_T = mask_sub_sub_sub_size & mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_size & mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_1_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_2_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size & mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_2_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_3_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size & mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_3_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_4_2 = mask_sub_sub_2_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_4 = mask_sub_size & mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_4_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_5_2 = mask_sub_sub_2_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_5 = mask_sub_size & mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_5_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_6_2 = mask_sub_sub_3_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_6 = mask_sub_size & mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_6_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_7_2 = mask_sub_sub_3_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_7 = mask_sub_size & mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_7_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_eq_8 = mask_sub_4_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_size & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_8 = mask_sub_4_1 | _mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_eq_9 = mask_sub_4_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_size & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_9 = mask_sub_4_1 | _mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_eq_10 = mask_sub_5_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_size & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_10 = mask_sub_5_1 | _mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_eq_11 = mask_sub_5_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_size & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_11 = mask_sub_5_1 | _mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_eq_12 = mask_sub_6_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_size & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_12 = mask_sub_6_1 | _mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_eq_13 = mask_sub_6_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_size & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_13 = mask_sub_6_1 | _mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_eq_14 = mask_sub_7_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_size & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_14 = mask_sub_7_1 | _mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_eq_15 = mask_sub_7_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_size & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_15 = mask_sub_7_1 | _mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_lo = {mask_lo_lo_hi, mask_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_hi = {mask_lo_hi_hi, mask_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_lo_hi = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_lo = {mask_hi_lo_hi, mask_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_hi = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_hi = {mask_hi_hi_hi, mask_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [15:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [2:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_9 = _uncommonBits_T_9; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_10 = _uncommonBits_T_10; // @[Parameters.scala:52:{29,56}] wire [2:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_11 = source_ok_uncommonBits_1 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_12 = _source_ok_T_11; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire _source_ok_T_13 = io_in_d_bits_source_0 == 3'h5; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_1 = _source_ok_T_13; // @[Parameters.scala:1138:31] wire source_ok_1 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire [2:0] uncommonBits_11 = _uncommonBits_T_11; // @[Parameters.scala:52:{29,56}] wire _legal_source_T_6 = io_in_b_bits_source_0 == 3'h5; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46] wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_5 = {io_in_b_bits_address_0[31:13], io_in_b_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46] wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1 = _address_ok_T_9; // @[Parameters.scala:612:40] wire [13:0] _GEN_0 = io_in_b_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_10 = {io_in_b_bits_address_0[31:14], _GEN_0}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46] wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_2 = _address_ok_T_14; // @[Parameters.scala:612:40] wire [16:0] _GEN_1 = io_in_b_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_15 = {io_in_b_bits_address_0[31:17], _GEN_1}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46] wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_3 = _address_ok_T_19; // @[Parameters.scala:612:40] wire [20:0] _GEN_2 = io_in_b_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_20 = {io_in_b_bits_address_0[31:21], _GEN_2}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_21 = {1'h0, _address_ok_T_20}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_22 = _address_ok_T_21 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_23 = _address_ok_T_22; // @[Parameters.scala:137:46] wire _address_ok_T_24 = _address_ok_T_23 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_4 = _address_ok_T_24; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_25 = {io_in_b_bits_address_0[31:21], io_in_b_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_26 = {1'h0, _address_ok_T_25}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_27 = _address_ok_T_26 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_28 = _address_ok_T_27; // @[Parameters.scala:137:46] wire _address_ok_T_29 = _address_ok_T_28 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_5 = _address_ok_T_29; // @[Parameters.scala:612:40] wire [25:0] _GEN_3 = io_in_b_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_30 = {io_in_b_bits_address_0[31:26], _GEN_3}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_31 = {1'h0, _address_ok_T_30}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_32 = _address_ok_T_31 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_33 = _address_ok_T_32; // @[Parameters.scala:137:46] wire _address_ok_T_34 = _address_ok_T_33 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_6 = _address_ok_T_34; // @[Parameters.scala:612:40] wire [25:0] _GEN_4 = io_in_b_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_35 = {io_in_b_bits_address_0[31:26], _GEN_4}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_36 = {1'h0, _address_ok_T_35}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_37 = _address_ok_T_36 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_38 = _address_ok_T_37; // @[Parameters.scala:137:46] wire _address_ok_T_39 = _address_ok_T_38 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_7 = _address_ok_T_39; // @[Parameters.scala:612:40] wire [27:0] _GEN_5 = io_in_b_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_40 = {io_in_b_bits_address_0[31:28], _GEN_5}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_41 = {1'h0, _address_ok_T_40}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_42 = _address_ok_T_41 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_43 = _address_ok_T_42; // @[Parameters.scala:137:46] wire _address_ok_T_44 = _address_ok_T_43 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_8 = _address_ok_T_44; // @[Parameters.scala:612:40] wire [27:0] _GEN_6 = io_in_b_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_45 = {io_in_b_bits_address_0[31:28], _GEN_6}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_46 = {1'h0, _address_ok_T_45}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_47 = _address_ok_T_46 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_48 = _address_ok_T_47; // @[Parameters.scala:137:46] wire _address_ok_T_49 = _address_ok_T_48 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_9 = _address_ok_T_49; // @[Parameters.scala:612:40] wire [28:0] _GEN_7 = io_in_b_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_50 = {io_in_b_bits_address_0[31:29], _GEN_7}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_51 = {1'h0, _address_ok_T_50}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_52 = _address_ok_T_51 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_53 = _address_ok_T_52; // @[Parameters.scala:137:46] wire _address_ok_T_54 = _address_ok_T_53 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_10 = _address_ok_T_54; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_55 = io_in_b_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_56 = {1'h0, _address_ok_T_55}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_57 = _address_ok_T_56 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_58 = _address_ok_T_57; // @[Parameters.scala:137:46] wire _address_ok_T_59 = _address_ok_T_58 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_11 = _address_ok_T_59; // @[Parameters.scala:612:40] wire _address_ok_T_60 = _address_ok_WIRE_0 | _address_ok_WIRE_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_61 = _address_ok_T_60 | _address_ok_WIRE_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_62 = _address_ok_T_61 | _address_ok_WIRE_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_63 = _address_ok_T_62 | _address_ok_WIRE_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_64 = _address_ok_T_63 | _address_ok_WIRE_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_65 = _address_ok_T_64 | _address_ok_WIRE_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_66 = _address_ok_T_65 | _address_ok_WIRE_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_67 = _address_ok_T_66 | _address_ok_WIRE_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_68 = _address_ok_T_67 | _address_ok_WIRE_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_69 = _address_ok_T_68 | _address_ok_WIRE_10; // @[Parameters.scala:612:40, :636:64] wire address_ok = _address_ok_T_69 | _address_ok_WIRE_11; // @[Parameters.scala:612:40, :636:64] wire [26:0] _GEN_8 = 27'hFFF << io_in_b_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_2; // @[package.scala:243:71] assign _is_aligned_mask_T_2 = _GEN_8; // @[package.scala:243:71] wire [26:0] _b_first_beats1_decode_T; // @[package.scala:243:71] assign _b_first_beats1_decode_T = _GEN_8; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_3 = _is_aligned_mask_T_2[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_1 = ~_is_aligned_mask_T_3; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_1 = {20'h0, io_in_b_bits_address_0[11:0] & is_aligned_mask_1}; // @[package.scala:243:46] wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount_1 = _mask_sizeOH_T_3[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_4 = 4'h1 << mask_sizeOH_shiftAmount_1; // @[OneHot.scala:64:49, :65:12] wire [3:0] _mask_sizeOH_T_5 = _mask_sizeOH_T_4; // @[OneHot.scala:65:{12,27}] wire [3:0] mask_sizeOH_1 = {_mask_sizeOH_T_5[3:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_sub_0_1_1 = |(io_in_b_bits_size_0[3:2]); // @[Misc.scala:206:21] wire mask_sub_sub_sub_size_1 = mask_sizeOH_1[3]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_sub_bit_1 = io_in_b_bits_address_0[3]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_1_2_1 = mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_nbit_1 = ~mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_0_2_1 = mask_sub_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_acc_T_2 = mask_sub_sub_sub_size_1 & mask_sub_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_0_1_1 = mask_sub_sub_sub_sub_0_1_1 | _mask_sub_sub_sub_acc_T_2; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_sub_acc_T_3 = mask_sub_sub_sub_size_1 & mask_sub_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_1_1_1 = mask_sub_sub_sub_sub_0_1_1 | _mask_sub_sub_sub_acc_T_3; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_sub_size_1 = mask_sizeOH_1[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2_1 = mask_sub_sub_sub_0_2_1 & mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_4 = mask_sub_sub_size_1 & mask_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1_1 = mask_sub_sub_sub_0_1_1 | _mask_sub_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_1_2_1 = mask_sub_sub_sub_0_2_1 & mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_5 = mask_sub_sub_size_1 & mask_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1_1 = mask_sub_sub_sub_0_1_1 | _mask_sub_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_2_2_1 = mask_sub_sub_sub_1_2_1 & mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_6 = mask_sub_sub_size_1 & mask_sub_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_2_1_1 = mask_sub_sub_sub_1_1_1 | _mask_sub_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_3_2_1 = mask_sub_sub_sub_1_2_1 & mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_7 = mask_sub_sub_size_1 & mask_sub_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_3_1_1 = mask_sub_sub_sub_1_1_1 | _mask_sub_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_sub_size_1 = mask_sizeOH_1[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_8 = mask_sub_size_1 & mask_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1_1 = mask_sub_sub_0_1_1 | _mask_sub_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_9 = mask_sub_size_1 & mask_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1_1 = mask_sub_sub_0_1_1 | _mask_sub_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_10 = mask_sub_size_1 & mask_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1_1 = mask_sub_sub_1_1_1 | _mask_sub_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_11 = mask_sub_size_1 & mask_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1_1 = mask_sub_sub_1_1_1 | _mask_sub_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_sub_4_2_1 = mask_sub_sub_2_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_12 = mask_sub_size_1 & mask_sub_4_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_4_1_1 = mask_sub_sub_2_1_1 | _mask_sub_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_sub_5_2_1 = mask_sub_sub_2_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_13 = mask_sub_size_1 & mask_sub_5_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_5_1_1 = mask_sub_sub_2_1_1 | _mask_sub_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_sub_6_2_1 = mask_sub_sub_3_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_14 = mask_sub_size_1 & mask_sub_6_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_6_1_1 = mask_sub_sub_3_1_1 | _mask_sub_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_sub_7_2_1 = mask_sub_sub_3_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_15 = mask_sub_size_1 & mask_sub_7_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_7_1_1 = mask_sub_sub_3_1_1 | _mask_sub_acc_T_15; // @[Misc.scala:215:{29,38}] wire mask_size_1 = mask_sizeOH_1[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_eq_16 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_16 = mask_size_1 & mask_eq_16; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_16 = mask_sub_0_1_1 | _mask_acc_T_16; // @[Misc.scala:215:{29,38}] wire mask_eq_17 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_17 = mask_size_1 & mask_eq_17; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_17 = mask_sub_0_1_1 | _mask_acc_T_17; // @[Misc.scala:215:{29,38}] wire mask_eq_18 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_18 = mask_size_1 & mask_eq_18; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_18 = mask_sub_1_1_1 | _mask_acc_T_18; // @[Misc.scala:215:{29,38}] wire mask_eq_19 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_19 = mask_size_1 & mask_eq_19; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_19 = mask_sub_1_1_1 | _mask_acc_T_19; // @[Misc.scala:215:{29,38}] wire mask_eq_20 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_20 = mask_size_1 & mask_eq_20; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_20 = mask_sub_2_1_1 | _mask_acc_T_20; // @[Misc.scala:215:{29,38}] wire mask_eq_21 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_21 = mask_size_1 & mask_eq_21; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_21 = mask_sub_2_1_1 | _mask_acc_T_21; // @[Misc.scala:215:{29,38}] wire mask_eq_22 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_22 = mask_size_1 & mask_eq_22; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_22 = mask_sub_3_1_1 | _mask_acc_T_22; // @[Misc.scala:215:{29,38}] wire mask_eq_23 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_23 = mask_size_1 & mask_eq_23; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_23 = mask_sub_3_1_1 | _mask_acc_T_23; // @[Misc.scala:215:{29,38}] wire mask_eq_24 = mask_sub_4_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_24 = mask_size_1 & mask_eq_24; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_24 = mask_sub_4_1_1 | _mask_acc_T_24; // @[Misc.scala:215:{29,38}] wire mask_eq_25 = mask_sub_4_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_25 = mask_size_1 & mask_eq_25; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_25 = mask_sub_4_1_1 | _mask_acc_T_25; // @[Misc.scala:215:{29,38}] wire mask_eq_26 = mask_sub_5_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_26 = mask_size_1 & mask_eq_26; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_26 = mask_sub_5_1_1 | _mask_acc_T_26; // @[Misc.scala:215:{29,38}] wire mask_eq_27 = mask_sub_5_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_27 = mask_size_1 & mask_eq_27; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_27 = mask_sub_5_1_1 | _mask_acc_T_27; // @[Misc.scala:215:{29,38}] wire mask_eq_28 = mask_sub_6_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_28 = mask_size_1 & mask_eq_28; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_28 = mask_sub_6_1_1 | _mask_acc_T_28; // @[Misc.scala:215:{29,38}] wire mask_eq_29 = mask_sub_6_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_29 = mask_size_1 & mask_eq_29; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_29 = mask_sub_6_1_1 | _mask_acc_T_29; // @[Misc.scala:215:{29,38}] wire mask_eq_30 = mask_sub_7_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_30 = mask_size_1 & mask_eq_30; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_30 = mask_sub_7_1_1 | _mask_acc_T_30; // @[Misc.scala:215:{29,38}] wire mask_eq_31 = mask_sub_7_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_31 = mask_size_1 & mask_eq_31; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_31 = mask_sub_7_1_1 | _mask_acc_T_31; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo_lo_1 = {mask_acc_17, mask_acc_16}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_lo_hi_1 = {mask_acc_19, mask_acc_18}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_lo_1 = {mask_lo_lo_hi_1, mask_lo_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo_1 = {mask_acc_21, mask_acc_20}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_hi_1 = {mask_acc_23, mask_acc_22}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_hi_1 = {mask_lo_hi_hi_1, mask_lo_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] mask_lo_1 = {mask_lo_hi_1, mask_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo_1 = {mask_acc_25, mask_acc_24}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_lo_hi_1 = {mask_acc_27, mask_acc_26}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_lo_1 = {mask_hi_lo_hi_1, mask_hi_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo_1 = {mask_acc_29, mask_acc_28}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_hi_1 = {mask_acc_31, mask_acc_30}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_hi_1 = {mask_hi_hi_hi_1, mask_hi_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] mask_hi_1 = {mask_hi_hi_1, mask_hi_lo_1}; // @[Misc.scala:222:10] wire [15:0] mask_1 = {mask_hi_1, mask_lo_1}; // @[Misc.scala:222:10] wire [2:0] legal_source_uncommonBits = _legal_source_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _legal_source_T_4 = legal_source_uncommonBits < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _legal_source_T_5 = _legal_source_T_4; // @[Parameters.scala:56:48, :57:20] wire _legal_source_WIRE_0 = _legal_source_T_5; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_1 = _legal_source_T_6; // @[Parameters.scala:1138:31] wire [2:0] _legal_source_T_8 = _legal_source_WIRE_1 ? 3'h5 : 3'h0; // @[Mux.scala:30:73] wire [2:0] _legal_source_T_9 = _legal_source_T_8; // @[Mux.scala:30:73] wire [2:0] _legal_source_WIRE_1_0 = _legal_source_T_9; // @[Mux.scala:30:73] wire legal_source = _legal_source_WIRE_1_0 == io_in_b_bits_source_0; // @[Mux.scala:30:73] wire [2:0] uncommonBits_12 = _uncommonBits_T_12; // @[Parameters.scala:52:{29,56}] wire [2:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_18 = source_ok_uncommonBits_2 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_19 = _source_ok_T_18; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_2_0 = _source_ok_T_19; // @[Parameters.scala:1138:31] wire _source_ok_T_20 = io_in_c_bits_source_0 == 3'h5; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_1 = _source_ok_T_20; // @[Parameters.scala:1138:31] wire source_ok_2 = _source_ok_WIRE_2_0 | _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN_9 = 27'hFFF << io_in_c_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_4; // @[package.scala:243:71] assign _is_aligned_mask_T_4 = _GEN_9; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T; // @[package.scala:243:71] assign _c_first_beats1_decode_T = _GEN_9; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71] assign _c_first_beats1_decode_T_3 = _GEN_9; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_2 = {20'h0, io_in_c_bits_address_0[11:0] & is_aligned_mask_2}; // @[package.scala:243:46] wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}] wire [32:0] _address_ok_T_71 = {1'h0, _address_ok_T_70}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_72 = _address_ok_T_71 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_73 = _address_ok_T_72; // @[Parameters.scala:137:46] wire _address_ok_T_74 = _address_ok_T_73 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_0 = _address_ok_T_74; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_75 = {io_in_c_bits_address_0[31:13], io_in_c_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_76 = {1'h0, _address_ok_T_75}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_77 = _address_ok_T_76 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_78 = _address_ok_T_77; // @[Parameters.scala:137:46] wire _address_ok_T_79 = _address_ok_T_78 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_1 = _address_ok_T_79; // @[Parameters.scala:612:40] wire [13:0] _GEN_10 = io_in_c_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_80 = {io_in_c_bits_address_0[31:14], _GEN_10}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_81 = {1'h0, _address_ok_T_80}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_82 = _address_ok_T_81 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_83 = _address_ok_T_82; // @[Parameters.scala:137:46] wire _address_ok_T_84 = _address_ok_T_83 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_2 = _address_ok_T_84; // @[Parameters.scala:612:40] wire [16:0] _GEN_11 = io_in_c_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_85 = {io_in_c_bits_address_0[31:17], _GEN_11}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_86 = {1'h0, _address_ok_T_85}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_87 = _address_ok_T_86 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_88 = _address_ok_T_87; // @[Parameters.scala:137:46] wire _address_ok_T_89 = _address_ok_T_88 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_3 = _address_ok_T_89; // @[Parameters.scala:612:40] wire [20:0] _GEN_12 = io_in_c_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_90 = {io_in_c_bits_address_0[31:21], _GEN_12}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_91 = {1'h0, _address_ok_T_90}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_92 = _address_ok_T_91 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_93 = _address_ok_T_92; // @[Parameters.scala:137:46] wire _address_ok_T_94 = _address_ok_T_93 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_4 = _address_ok_T_94; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_95 = {io_in_c_bits_address_0[31:21], io_in_c_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_96 = {1'h0, _address_ok_T_95}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_97 = _address_ok_T_96 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_98 = _address_ok_T_97; // @[Parameters.scala:137:46] wire _address_ok_T_99 = _address_ok_T_98 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_5 = _address_ok_T_99; // @[Parameters.scala:612:40] wire [25:0] _GEN_13 = io_in_c_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_100 = {io_in_c_bits_address_0[31:26], _GEN_13}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_101 = {1'h0, _address_ok_T_100}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_102 = _address_ok_T_101 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_103 = _address_ok_T_102; // @[Parameters.scala:137:46] wire _address_ok_T_104 = _address_ok_T_103 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_6 = _address_ok_T_104; // @[Parameters.scala:612:40] wire [25:0] _GEN_14 = io_in_c_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_105 = {io_in_c_bits_address_0[31:26], _GEN_14}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_106 = {1'h0, _address_ok_T_105}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_107 = _address_ok_T_106 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_108 = _address_ok_T_107; // @[Parameters.scala:137:46] wire _address_ok_T_109 = _address_ok_T_108 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_7 = _address_ok_T_109; // @[Parameters.scala:612:40] wire [27:0] _GEN_15 = io_in_c_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_110 = {io_in_c_bits_address_0[31:28], _GEN_15}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_111 = {1'h0, _address_ok_T_110}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_112 = _address_ok_T_111 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_113 = _address_ok_T_112; // @[Parameters.scala:137:46] wire _address_ok_T_114 = _address_ok_T_113 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_8 = _address_ok_T_114; // @[Parameters.scala:612:40] wire [27:0] _GEN_16 = io_in_c_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_115 = {io_in_c_bits_address_0[31:28], _GEN_16}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_116 = {1'h0, _address_ok_T_115}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_117 = _address_ok_T_116 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_118 = _address_ok_T_117; // @[Parameters.scala:137:46] wire _address_ok_T_119 = _address_ok_T_118 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_9 = _address_ok_T_119; // @[Parameters.scala:612:40] wire [28:0] _GEN_17 = io_in_c_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_120 = {io_in_c_bits_address_0[31:29], _GEN_17}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_121 = {1'h0, _address_ok_T_120}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_122 = _address_ok_T_121 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_123 = _address_ok_T_122; // @[Parameters.scala:137:46] wire _address_ok_T_124 = _address_ok_T_123 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_10 = _address_ok_T_124; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_125 = io_in_c_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_126 = {1'h0, _address_ok_T_125}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_127 = _address_ok_T_126 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_128 = _address_ok_T_127; // @[Parameters.scala:137:46] wire _address_ok_T_129 = _address_ok_T_128 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_11 = _address_ok_T_129; // @[Parameters.scala:612:40] wire _address_ok_T_130 = _address_ok_WIRE_1_0 | _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_131 = _address_ok_T_130 | _address_ok_WIRE_1_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_132 = _address_ok_T_131 | _address_ok_WIRE_1_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_133 = _address_ok_T_132 | _address_ok_WIRE_1_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_134 = _address_ok_T_133 | _address_ok_WIRE_1_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_135 = _address_ok_T_134 | _address_ok_WIRE_1_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_136 = _address_ok_T_135 | _address_ok_WIRE_1_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_137 = _address_ok_T_136 | _address_ok_WIRE_1_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_138 = _address_ok_T_137 | _address_ok_WIRE_1_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_139 = _address_ok_T_138 | _address_ok_WIRE_1_10; // @[Parameters.scala:612:40, :636:64] wire address_ok_1 = _address_ok_T_139 | _address_ok_WIRE_1_11; // @[Parameters.scala:612:40, :636:64] wire [2:0] uncommonBits_13 = _uncommonBits_T_13; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_14 = _uncommonBits_T_14; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_15 = _uncommonBits_T_15; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_16 = _uncommonBits_T_16; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_17 = _uncommonBits_T_17; // @[Parameters.scala:52:{29,56}] wire _T_2489 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_2489; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_2489; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [7:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [7:0] a_first_counter; // @[Edges.scala:229:27] wire [8:0] _a_first_counter1_T = {1'h0, a_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] a_first_counter1 = _a_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [7:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [2:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_2563 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_2563; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_2563; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_2563; // @[Decoupled.scala:51:35] wire _d_first_T_3; // @[Decoupled.scala:51:35] assign _d_first_T_3 = _T_2563; // @[Decoupled.scala:51:35] wire [26:0] _GEN_18 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71] assign _d_first_beats1_decode_T_9 = _GEN_18; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [7:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T = {1'h0, d_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1 = _d_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [2:0] source_1; // @[Monitor.scala:541:22] reg [3:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35] wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35] wire [11:0] _b_first_beats1_decode_T_1 = _b_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _b_first_beats1_decode_T_2 = ~_b_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] b_first_beats1_decode = _b_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire _b_first_beats1_opdata_T = io_in_b_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire b_first_beats1_opdata = ~_b_first_beats1_opdata_T; // @[Edges.scala:97:{28,37}] reg [7:0] b_first_counter; // @[Edges.scala:229:27] wire [8:0] _b_first_counter1_T = {1'h0, b_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] b_first_counter1 = _b_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire b_first = b_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _b_first_last_T = b_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire [7:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] _b_first_counter_T = b_first ? 8'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_2; // @[Monitor.scala:410:22] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [3:0] size_2; // @[Monitor.scala:412:22] reg [2:0] source_2; // @[Monitor.scala:413:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _T_2560 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35] wire _c_first_T; // @[Decoupled.scala:51:35] assign _c_first_T = _T_2560; // @[Decoupled.scala:51:35] wire _c_first_T_1; // @[Decoupled.scala:51:35] assign _c_first_T_1 = _T_2560; // @[Decoupled.scala:51:35] wire [11:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [7:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 8'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [7:0] c_first_counter; // @[Edges.scala:229:27] wire [8:0] _c_first_counter1_T = {1'h0, c_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] c_first_counter1 = _c_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire c_first = c_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T = c_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_1 = c_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last = _c_first_last_T | _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35] wire [7:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [3:0] size_3; // @[Monitor.scala:517:22] reg [2:0] source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [5:0] inflight; // @[Monitor.scala:614:27] reg [23:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [47:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [7:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [7:0] a_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] a_first_counter1_1 = _a_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [7:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_1 = _d_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] a_set; // @[Monitor.scala:626:34] wire [5:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [23:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [47:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [5:0] _GEN_19 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [5:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_19; // @[Monitor.scala:637:69] wire [5:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_19; // @[Monitor.scala:637:69, :680:101] wire [5:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_19; // @[Monitor.scala:637:69, :749:69] wire [5:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_19; // @[Monitor.scala:637:69, :790:101] wire [23:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [23:0] _a_opcode_lookup_T_6 = {20'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [23:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[23:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [5:0] _GEN_20 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [5:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_20; // @[Monitor.scala:641:65] wire [5:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_20; // @[Monitor.scala:641:65, :681:99] wire [5:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_20; // @[Monitor.scala:641:65, :750:67] wire [5:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_20; // @[Monitor.scala:641:65, :791:99] wire [47:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [47:0] _a_size_lookup_T_6 = {40'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [47:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[47:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [7:0] _GEN_21 = 8'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [7:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_21; // @[OneHot.scala:58:35] wire [7:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_21; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[5:0] : 6'h0; // @[OneHot.scala:58:35] wire _T_2415 = _T_2489 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_2415 ? _a_set_T[5:0] : 6'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_2415 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_2415 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [5:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [66:0] _a_opcodes_set_T_1 = {63'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_2415 ? _a_opcodes_set_T_1[23:0] : 24'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [5:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [67:0] _a_sizes_set_T_1 = {63'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_2415 ? _a_sizes_set_T_1[47:0] : 48'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [5:0] d_clr; // @[Monitor.scala:664:34] wire [5:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [23:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [47:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_22 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_22; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_22; // @[Monitor.scala:673:46, :783:46] wire _T_2461 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [7:0] _GEN_23 = 8'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [7:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_23; // @[OneHot.scala:58:35] wire [7:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_23; // @[OneHot.scala:58:35] wire [7:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_23; // @[OneHot.scala:58:35] wire [7:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_23; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_2461 & ~d_release_ack ? _d_clr_wo_ready_T[5:0] : 6'h0; // @[OneHot.scala:58:35] wire _T_2430 = _T_2563 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_2430 ? _d_clr_T[5:0] : 6'h0; // @[OneHot.scala:58:35] wire [78:0] _d_opcodes_clr_T_5 = 79'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_2430 ? _d_opcodes_clr_T_5[23:0] : 24'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [78:0] _d_sizes_clr_T_5 = 79'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_2430 ? _d_sizes_clr_T_5[47:0] : 48'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [5:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [5:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [5:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [23:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [23:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [23:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [47:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [47:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [47:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [5:0] inflight_1; // @[Monitor.scala:726:35] reg [23:0] inflight_opcodes_1; // @[Monitor.scala:727:35] reg [47:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [11:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire [7:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 8'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [7:0] c_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] c_first_counter1_1 = _c_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire c_first_1 = c_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T_2 = c_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_3 = c_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last_1 = _c_first_last_T_2 | _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35] wire [7:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_2; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_2 = _d_first_counter1_T_2[7:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] c_set; // @[Monitor.scala:738:34] wire [5:0] c_set_wo_ready; // @[Monitor.scala:739:34] wire [23:0] c_opcodes_set; // @[Monitor.scala:740:34] wire [47:0] c_sizes_set; // @[Monitor.scala:741:34] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [23:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [23:0] _c_opcode_lookup_T_6 = {20'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [23:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[23:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [47:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [47:0] _c_size_lookup_T_6 = {40'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [47:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[47:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40] wire [4:0] c_sizes_set_interm; // @[Monitor.scala:755:40] wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44] wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7] wire [7:0] _GEN_24 = 8'h1 << io_in_c_bits_source_0; // @[OneHot.scala:58:35] wire [7:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35] assign _c_set_wo_ready_T = _GEN_24; // @[OneHot.scala:58:35] wire [7:0] _c_set_T; // @[OneHot.scala:58:35] assign _c_set_T = _GEN_24; // @[OneHot.scala:58:35] assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T[5:0] : 6'h0; // @[OneHot.scala:58:35] wire _T_2502 = _T_2560 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35] assign c_set = _T_2502 ? _c_set_T[5:0] : 6'h0; // @[OneHot.scala:58:35] wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53] wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}] assign c_opcodes_set_interm = _T_2502 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}] wire [4:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51] wire [4:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:766:{51,59}] assign c_sizes_set_interm = _T_2502 ? _c_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}] wire [5:0] _c_opcodes_set_T = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79] wire [66:0] _c_opcodes_set_T_1 = {63'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:659:54, :754:40, :767:{54,79}] assign c_opcodes_set = _T_2502 ? _c_opcodes_set_T_1[23:0] : 24'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}] wire [5:0] _c_sizes_set_T = {io_in_c_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :768:77] wire [67:0] _c_sizes_set_T_1 = {63'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:659:54, :755:40, :768:{52,77}] assign c_sizes_set = _T_2502 ? _c_sizes_set_T_1[47:0] : 48'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}] wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47] wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95] wire c_probe_ack = _c_probe_ack_T | _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}] wire [5:0] d_clr_1; // @[Monitor.scala:774:34] wire [5:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [23:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [47:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_2533 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_2533 & d_release_ack_1 ? _d_clr_wo_ready_T_1[5:0] : 6'h0; // @[OneHot.scala:58:35] wire _T_2515 = _T_2563 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_2515 ? _d_clr_T_1[5:0] : 6'h0; // @[OneHot.scala:58:35] wire [78:0] _d_opcodes_clr_T_11 = 79'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_2515 ? _d_opcodes_clr_T_11[23:0] : 24'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [78:0] _d_sizes_clr_T_11 = 79'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_2515 ? _d_sizes_clr_T_11[47:0] : 48'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}] wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}] wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}] wire [5:0] _inflight_T_3 = inflight_1 | c_set; // @[Monitor.scala:726:35, :738:34, :814:35] wire [5:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [5:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [23:0] _inflight_opcodes_T_3 = inflight_opcodes_1 | c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43] wire [23:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [23:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [47:0] _inflight_sizes_T_3 = inflight_sizes_1 | c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41] wire [47:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [47:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26] wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26] reg [15:0] inflight_2; // @[Monitor.scala:828:27] wire [11:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_3; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_3 = _d_first_counter1_T_3[7:0]; // @[Edges.scala:230:28] wire d_first_3 = d_first_counter_3 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_6 = d_first_counter_3 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_7 = d_first_beats1_3 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_3 = _d_first_last_T_6 | _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}] wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [15:0] d_set; // @[Monitor.scala:833:25] wire _T_2569 = _T_2563 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35] wire [15:0] _GEN_25 = {12'h0, io_in_d_bits_sink_0}; // @[OneHot.scala:58:35] wire [15:0] _d_set_T = 16'h1 << _GEN_25; // @[OneHot.scala:58:35] assign d_set = _T_2569 ? _d_set_T : 16'h0; // @[OneHot.scala:58:35] wire [15:0] e_clr; // @[Monitor.scala:839:25] wire _T_2578 = io_in_e_ready_0 & io_in_e_valid_0; // @[Decoupled.scala:51:35] wire [15:0] _GEN_26 = {12'h0, io_in_e_bits_sink_0}; // @[OneHot.scala:58:35] wire [15:0] _e_clr_T = 16'h1 << _GEN_26; // @[OneHot.scala:58:35] assign e_clr = _T_2578 ? _e_clr_T : 16'h0; // @[OneHot.scala:58:35]

Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module TLMonitor_55( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [7:0] source; // @[Monitor.scala:390:22] reg [27:0] address; // @[Monitor.scala:391:22] reg d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [7:0] source_1; // @[Monitor.scala:541:22] reg [159:0] inflight; // @[Monitor.scala:614:27] reg [639:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [639:0] inflight_sizes; // @[Monitor.scala:618:33] reg a_first_counter_1; // @[Edges.scala:229:27] reg d_first_counter_1; // @[Edges.scala:229:27] wire [255:0] _GEN = {248'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_0 = a_first_done & ~a_first_counter_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_1 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [255:0] _GEN_2 = {248'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [159:0] inflight_1; // @[Monitor.scala:726:35] reg [639:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg d_first_counter_2; // @[Edges.scala:229:27] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module TLMonitor_20( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [13:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [13:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire io_in_d_bits_denied = 1'h1; // @[Monitor.scala:36:7] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_81 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_83 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_87 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_89 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_93 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_95 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_99 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_101 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data = 64'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [13:0] _c_first_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_first_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_first_WIRE_2_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_first_WIRE_3_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_set_wo_ready_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_set_wo_ready_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_set_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_set_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_opcodes_set_interm_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_opcodes_set_interm_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_sizes_set_interm_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_sizes_set_interm_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_opcodes_set_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_opcodes_set_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_sizes_set_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_sizes_set_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_probe_ack_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_probe_ack_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_probe_ack_WIRE_2_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_probe_ack_WIRE_3_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _same_cycle_resp_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _same_cycle_resp_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _same_cycle_resp_WIRE_2_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _same_cycle_resp_WIRE_3_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _same_cycle_resp_WIRE_4_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _same_cycle_resp_WIRE_5_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1027:0] _c_sizes_set_T_1 = 1028'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [519:0] c_sizes_set = 520'h0; // @[Monitor.scala:741:34] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h3C; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 7'h3D; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire _source_ok_T_27 = io_in_a_bits_source_0 == 7'h3E; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31] wire _source_ok_T_28 = io_in_a_bits_source_0 == 7'h38; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_28; // @[Parameters.scala:1138:31] wire _source_ok_T_29 = io_in_a_bits_source_0 == 7'h39; // @[Monitor.scala:36:7] wire _source_ok_WIRE_9 = _source_ok_T_29; // @[Parameters.scala:1138:31] wire _source_ok_T_30 = io_in_a_bits_source_0 == 7'h3A; // @[Monitor.scala:36:7] wire _source_ok_WIRE_10 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire _source_ok_T_31 = io_in_a_bits_source_0 == 7'h34; // @[Monitor.scala:36:7] wire _source_ok_WIRE_11 = _source_ok_T_31; // @[Parameters.scala:1138:31] wire _source_ok_T_32 = io_in_a_bits_source_0 == 7'h35; // @[Monitor.scala:36:7] wire _source_ok_WIRE_12 = _source_ok_T_32; // @[Parameters.scala:1138:31] wire _source_ok_T_33 = io_in_a_bits_source_0 == 7'h36; // @[Monitor.scala:36:7] wire _source_ok_WIRE_13 = _source_ok_T_33; // @[Parameters.scala:1138:31] wire _source_ok_T_34 = io_in_a_bits_source_0 == 7'h30; // @[Monitor.scala:36:7] wire _source_ok_WIRE_14 = _source_ok_T_34; // @[Parameters.scala:1138:31] wire _source_ok_T_35 = io_in_a_bits_source_0 == 7'h31; // @[Monitor.scala:36:7] wire _source_ok_WIRE_15 = _source_ok_T_35; // @[Parameters.scala:1138:31] wire _source_ok_T_36 = io_in_a_bits_source_0 == 7'h32; // @[Monitor.scala:36:7] wire _source_ok_WIRE_16 = _source_ok_T_36; // @[Parameters.scala:1138:31] wire _source_ok_T_37 = io_in_a_bits_source_0 == 7'h2C; // @[Monitor.scala:36:7] wire _source_ok_WIRE_17 = _source_ok_T_37; // @[Parameters.scala:1138:31] wire _source_ok_T_38 = io_in_a_bits_source_0 == 7'h2D; // @[Monitor.scala:36:7] wire _source_ok_WIRE_18 = _source_ok_T_38; // @[Parameters.scala:1138:31] wire _source_ok_T_39 = io_in_a_bits_source_0 == 7'h2E; // @[Monitor.scala:36:7] wire _source_ok_WIRE_19 = _source_ok_T_39; // @[Parameters.scala:1138:31] wire _source_ok_T_40 = io_in_a_bits_source_0 == 7'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_20 = _source_ok_T_40; // @[Parameters.scala:1138:31] wire _source_ok_T_41 = io_in_a_bits_source_0 == 7'h29; // @[Monitor.scala:36:7] wire _source_ok_WIRE_21 = _source_ok_T_41; // @[Parameters.scala:1138:31] wire _source_ok_T_42 = io_in_a_bits_source_0 == 7'h2A; // @[Monitor.scala:36:7] wire _source_ok_WIRE_22 = _source_ok_T_42; // @[Parameters.scala:1138:31] wire _source_ok_T_43 = io_in_a_bits_source_0 == 7'h24; // @[Monitor.scala:36:7] wire _source_ok_WIRE_23 = _source_ok_T_43; // @[Parameters.scala:1138:31] wire _source_ok_T_44 = io_in_a_bits_source_0 == 7'h25; // @[Monitor.scala:36:7] wire _source_ok_WIRE_24 = _source_ok_T_44; // @[Parameters.scala:1138:31] wire _source_ok_T_45 = io_in_a_bits_source_0 == 7'h26; // @[Monitor.scala:36:7] wire _source_ok_WIRE_25 = _source_ok_T_45; // @[Parameters.scala:1138:31] wire _source_ok_T_46 = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_26 = _source_ok_T_46; // @[Parameters.scala:1138:31] wire _source_ok_T_47 = io_in_a_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_27 = _source_ok_T_47; // @[Parameters.scala:1138:31] wire _source_ok_T_48 = io_in_a_bits_source_0 == 7'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_28 = _source_ok_T_48; // @[Parameters.scala:1138:31] wire _source_ok_T_49 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_29 = _source_ok_T_49; // @[Parameters.scala:1138:31] wire _source_ok_T_50 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_51 = _source_ok_T_50 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_52 = _source_ok_T_51 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_53 = _source_ok_T_52 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_54 = _source_ok_T_53 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_55 = _source_ok_T_54 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_56 = _source_ok_T_55 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_57 = _source_ok_T_56 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_58 = _source_ok_T_57 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_59 = _source_ok_T_58 | _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_60 = _source_ok_T_59 | _source_ok_WIRE_11; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_61 = _source_ok_T_60 | _source_ok_WIRE_12; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_62 = _source_ok_T_61 | _source_ok_WIRE_13; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_63 = _source_ok_T_62 | _source_ok_WIRE_14; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_64 = _source_ok_T_63 | _source_ok_WIRE_15; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_65 = _source_ok_T_64 | _source_ok_WIRE_16; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_66 = _source_ok_T_65 | _source_ok_WIRE_17; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_67 = _source_ok_T_66 | _source_ok_WIRE_18; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_68 = _source_ok_T_67 | _source_ok_WIRE_19; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_69 = _source_ok_T_68 | _source_ok_WIRE_20; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_70 = _source_ok_T_69 | _source_ok_WIRE_21; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_71 = _source_ok_T_70 | _source_ok_WIRE_22; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_72 = _source_ok_T_71 | _source_ok_WIRE_23; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_73 = _source_ok_T_72 | _source_ok_WIRE_24; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_74 = _source_ok_T_73 | _source_ok_WIRE_25; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_75 = _source_ok_T_74 | _source_ok_WIRE_26; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_76 = _source_ok_T_75 | _source_ok_WIRE_27; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_77 = _source_ok_T_76 | _source_ok_WIRE_28; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_77 | _source_ok_WIRE_29; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [13:0] _is_aligned_T = {2'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 14'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_78 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_78; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_79 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_85 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_91 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_97 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_80 = _source_ok_T_79 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_82 = _source_ok_T_80; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_84 = _source_ok_T_82; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_84; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_86 = _source_ok_T_85 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_88 = _source_ok_T_86; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_90 = _source_ok_T_88; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_90; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_92 = _source_ok_T_91 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_94 = _source_ok_T_92; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_96 = _source_ok_T_94; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_96; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_98 = _source_ok_T_97 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_100 = _source_ok_T_98; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_102 = _source_ok_T_100; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_102; // @[Parameters.scala:1138:31] wire _source_ok_T_103 = io_in_d_bits_source_0 == 7'h3C; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_103; // @[Parameters.scala:1138:31] wire _source_ok_T_104 = io_in_d_bits_source_0 == 7'h3D; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_104; // @[Parameters.scala:1138:31] wire _source_ok_T_105 = io_in_d_bits_source_0 == 7'h3E; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_105; // @[Parameters.scala:1138:31] wire _source_ok_T_106 = io_in_d_bits_source_0 == 7'h38; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_106; // @[Parameters.scala:1138:31] wire _source_ok_T_107 = io_in_d_bits_source_0 == 7'h39; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_9 = _source_ok_T_107; // @[Parameters.scala:1138:31] wire _source_ok_T_108 = io_in_d_bits_source_0 == 7'h3A; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_10 = _source_ok_T_108; // @[Parameters.scala:1138:31] wire _source_ok_T_109 = io_in_d_bits_source_0 == 7'h34; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_11 = _source_ok_T_109; // @[Parameters.scala:1138:31] wire _source_ok_T_110 = io_in_d_bits_source_0 == 7'h35; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_12 = _source_ok_T_110; // @[Parameters.scala:1138:31] wire _source_ok_T_111 = io_in_d_bits_source_0 == 7'h36; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_13 = _source_ok_T_111; // @[Parameters.scala:1138:31] wire _source_ok_T_112 = io_in_d_bits_source_0 == 7'h30; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_14 = _source_ok_T_112; // @[Parameters.scala:1138:31] wire _source_ok_T_113 = io_in_d_bits_source_0 == 7'h31; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_15 = _source_ok_T_113; // @[Parameters.scala:1138:31] wire _source_ok_T_114 = io_in_d_bits_source_0 == 7'h32; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_16 = _source_ok_T_114; // @[Parameters.scala:1138:31] wire _source_ok_T_115 = io_in_d_bits_source_0 == 7'h2C; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_17 = _source_ok_T_115; // @[Parameters.scala:1138:31] wire _source_ok_T_116 = io_in_d_bits_source_0 == 7'h2D; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_18 = _source_ok_T_116; // @[Parameters.scala:1138:31] wire _source_ok_T_117 = io_in_d_bits_source_0 == 7'h2E; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_19 = _source_ok_T_117; // @[Parameters.scala:1138:31] wire _source_ok_T_118 = io_in_d_bits_source_0 == 7'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_20 = _source_ok_T_118; // @[Parameters.scala:1138:31] wire _source_ok_T_119 = io_in_d_bits_source_0 == 7'h29; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_21 = _source_ok_T_119; // @[Parameters.scala:1138:31] wire _source_ok_T_120 = io_in_d_bits_source_0 == 7'h2A; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_22 = _source_ok_T_120; // @[Parameters.scala:1138:31] wire _source_ok_T_121 = io_in_d_bits_source_0 == 7'h24; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_23 = _source_ok_T_121; // @[Parameters.scala:1138:31] wire _source_ok_T_122 = io_in_d_bits_source_0 == 7'h25; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_24 = _source_ok_T_122; // @[Parameters.scala:1138:31] wire _source_ok_T_123 = io_in_d_bits_source_0 == 7'h26; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_25 = _source_ok_T_123; // @[Parameters.scala:1138:31] wire _source_ok_T_124 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_26 = _source_ok_T_124; // @[Parameters.scala:1138:31] wire _source_ok_T_125 = io_in_d_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_27 = _source_ok_T_125; // @[Parameters.scala:1138:31] wire _source_ok_T_126 = io_in_d_bits_source_0 == 7'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_28 = _source_ok_T_126; // @[Parameters.scala:1138:31] wire _source_ok_T_127 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_29 = _source_ok_T_127; // @[Parameters.scala:1138:31] wire _source_ok_T_128 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_129 = _source_ok_T_128 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_130 = _source_ok_T_129 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_131 = _source_ok_T_130 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_132 = _source_ok_T_131 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_133 = _source_ok_T_132 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_134 = _source_ok_T_133 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_135 = _source_ok_T_134 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_136 = _source_ok_T_135 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_137 = _source_ok_T_136 | _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_138 = _source_ok_T_137 | _source_ok_WIRE_1_11; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_139 = _source_ok_T_138 | _source_ok_WIRE_1_12; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_140 = _source_ok_T_139 | _source_ok_WIRE_1_13; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_141 = _source_ok_T_140 | _source_ok_WIRE_1_14; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_142 = _source_ok_T_141 | _source_ok_WIRE_1_15; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_143 = _source_ok_T_142 | _source_ok_WIRE_1_16; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_144 = _source_ok_T_143 | _source_ok_WIRE_1_17; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_145 = _source_ok_T_144 | _source_ok_WIRE_1_18; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_146 = _source_ok_T_145 | _source_ok_WIRE_1_19; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_147 = _source_ok_T_146 | _source_ok_WIRE_1_20; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_148 = _source_ok_T_147 | _source_ok_WIRE_1_21; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_149 = _source_ok_T_148 | _source_ok_WIRE_1_22; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_150 = _source_ok_T_149 | _source_ok_WIRE_1_23; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_151 = _source_ok_T_150 | _source_ok_WIRE_1_24; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_152 = _source_ok_T_151 | _source_ok_WIRE_1_25; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_153 = _source_ok_T_152 | _source_ok_WIRE_1_26; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_154 = _source_ok_T_153 | _source_ok_WIRE_1_27; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_155 = _source_ok_T_154 | _source_ok_WIRE_1_28; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_155 | _source_ok_WIRE_1_29; // @[Parameters.scala:1138:31, :1139:46] wire _T_1775 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1775; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1775; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [13:0] address; // @[Monitor.scala:391:22] wire _T_1848 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1848; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1848; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1848; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [519:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [519:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [9:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [519:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [519:0] _a_size_lookup_T_6 = {512'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [519:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[519:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_3 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1701 = _T_1775 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1701 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1701 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1701 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1701 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [9:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [1027:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1701 ? _a_sizes_set_T_1[519:0] : 520'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [519:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1747 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1747 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1716 = _T_1848 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1716 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1716 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1716 ? _d_sizes_clr_T_5[519:0] : 520'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [519:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [519:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [519:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [519:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [519:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [519:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [519:0] _c_size_lookup_T_6 = {512'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [519:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[519:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [519:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1819 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1819 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1801 = _T_1848 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1801 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1801 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1801 ? _d_sizes_clr_T_11[519:0] : 520'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [519:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [519:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands */ class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def *(t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def *(t: UInt) = self * t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros | ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def *(t: SInt) = self * t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros | ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid || output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def *(t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def *(t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }

module MacUnit_248( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [31:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7] wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54] wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module TLMonitor_3( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input io_in_b_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input [63:0] io_in_c_bits_data, // @[Monitor.scala:20:14] input io_in_c_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_ready, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7] wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7] wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7] wire io_in_b_bits_source_0 = io_in_b_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7] wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7] wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7] wire io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7] wire [63:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7] wire io_in_c_bits_corrupt_0 = io_in_c_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_e_ready_0 = io_in_e_ready; // @[Monitor.scala:36:7] wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire mask_sub_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:206:21] wire mask_sub_sub_size_1 = 1'h1; // @[Misc.scala:209:26] wire mask_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_2_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_3_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_size_1 = 1'h1; // @[Misc.scala:209:26] wire mask_acc_8 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_9 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_10 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_11 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_12 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_13 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_14 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_15 = 1'h1; // @[Misc.scala:215:29] wire sink_ok_1 = 1'h1; // @[Monitor.scala:367:31] wire _b_first_beats1_opdata_T = 1'h1; // @[Edges.scala:97:37] wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire b_first_last = 1'h1; // @[Edges.scala:232:33] wire [3:0] io_in_b_bits_size = 4'h6; // @[Monitor.scala:36:7] wire [3:0] _mask_sizeOH_T_3 = 4'h6; // @[Misc.scala:202:34] wire [2:0] io_in_b_bits_opcode = 3'h6; // @[Monitor.scala:36:7] wire [7:0] io_in_b_bits_mask = 8'hFF; // @[Monitor.scala:36:7] wire [7:0] mask_1 = 8'hFF; // @[Misc.scala:222:10] wire [63:0] io_in_b_bits_data = 64'h0; // @[Monitor.scala:36:7] wire io_in_b_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire mask_sub_size_1 = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38] wire _legal_source_T_2 = 1'h0; // @[Mux.scala:30:73] wire b_first_beats1_opdata = 1'h0; // @[Edges.scala:97:28] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [3:0] _mask_sizeOH_T_4 = 4'h4; // @[OneHot.scala:65:12] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [2:0] _mask_sizeOH_T_5 = 3'h4; // @[OneHot.scala:65:27] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] mask_sizeOH_1 = 3'h5; // @[Misc.scala:202:81] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [8:0] b_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] b_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] b_first_beats1_decode = 9'h7; // @[Edges.scala:220:59] wire [11:0] is_aligned_mask_1 = 12'h3F; // @[package.scala:243:46] wire [11:0] _b_first_beats1_decode_T_2 = 12'h3F; // @[package.scala:243:46] wire [11:0] _is_aligned_mask_T_3 = 12'hFC0; // @[package.scala:243:76] wire [11:0] _b_first_beats1_decode_T_1 = 12'hFC0; // @[package.scala:243:76] wire [26:0] _is_aligned_mask_T_2 = 27'h3FFC0; // @[package.scala:243:71] wire [26:0] _b_first_beats1_decode_T = 27'h3FFC0; // @[package.scala:243:71] wire [3:0] mask_lo_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi_1 = 4'hF; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_sizeOH_shiftAmount_1 = 2'h2; // @[OneHot.scala:64:49] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire _source_ok_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire _legal_source_T_1 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T = io_in_b_bits_address_0; // @[Monitor.scala:36:7] wire _source_ok_T_5 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_100 = io_in_c_bits_address_0; // @[Monitor.scala:36:7] wire _source_ok_T_3 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = ~io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire _source_ok_WIRE_1 = _source_ok_T_1; // @[Parameters.scala:1138:31] wire source_ok = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire _source_ok_T_2 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_2; // @[Parameters.scala:1138:31] wire _source_ok_WIRE_1_1 = _source_ok_T_3; // @[Parameters.scala:1138:31] wire source_ok_1 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46] wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_5 = {io_in_b_bits_address_0[31:13], io_in_b_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46] wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1 = _address_ok_T_9; // @[Parameters.scala:612:40] wire [13:0] _GEN_0 = io_in_b_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_10 = {io_in_b_bits_address_0[31:14], _GEN_0}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46] wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_2 = _address_ok_T_14; // @[Parameters.scala:612:40] wire [16:0] _GEN_1 = io_in_b_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_15 = {io_in_b_bits_address_0[31:17], _GEN_1}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46] wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_3 = _address_ok_T_19; // @[Parameters.scala:612:40] wire [17:0] _GEN_2 = io_in_b_bits_address_0[17:0] ^ 18'h20000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_20 = {io_in_b_bits_address_0[31:18], _GEN_2}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_21 = {1'h0, _address_ok_T_20}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_22 = _address_ok_T_21 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_23 = _address_ok_T_22; // @[Parameters.scala:137:46] wire _address_ok_T_24 = _address_ok_T_23 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_4 = _address_ok_T_24; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_25 = {io_in_b_bits_address_0[31:18], io_in_b_bits_address_0[17:0] ^ 18'h21000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_26 = {1'h0, _address_ok_T_25}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_27 = _address_ok_T_26 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_28 = _address_ok_T_27; // @[Parameters.scala:137:46] wire _address_ok_T_29 = _address_ok_T_28 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_5 = _address_ok_T_29; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_30 = {io_in_b_bits_address_0[31:18], io_in_b_bits_address_0[17:0] ^ 18'h22000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_31 = {1'h0, _address_ok_T_30}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_32 = _address_ok_T_31 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_33 = _address_ok_T_32; // @[Parameters.scala:137:46] wire _address_ok_T_34 = _address_ok_T_33 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_6 = _address_ok_T_34; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_35 = {io_in_b_bits_address_0[31:18], io_in_b_bits_address_0[17:0] ^ 18'h23000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_36 = {1'h0, _address_ok_T_35}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_37 = _address_ok_T_36 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_38 = _address_ok_T_37; // @[Parameters.scala:137:46] wire _address_ok_T_39 = _address_ok_T_38 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_7 = _address_ok_T_39; // @[Parameters.scala:612:40] wire [17:0] _GEN_3 = io_in_b_bits_address_0[17:0] ^ 18'h24000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_40 = {io_in_b_bits_address_0[31:18], _GEN_3}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_41 = {1'h0, _address_ok_T_40}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_42 = _address_ok_T_41 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_43 = _address_ok_T_42; // @[Parameters.scala:137:46] wire _address_ok_T_44 = _address_ok_T_43 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_8 = _address_ok_T_44; // @[Parameters.scala:612:40] wire [20:0] _GEN_4 = io_in_b_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_45 = {io_in_b_bits_address_0[31:21], _GEN_4}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_46 = {1'h0, _address_ok_T_45}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_47 = _address_ok_T_46 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_48 = _address_ok_T_47; // @[Parameters.scala:137:46] wire _address_ok_T_49 = _address_ok_T_48 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_9 = _address_ok_T_49; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_50 = {io_in_b_bits_address_0[31:21], io_in_b_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_51 = {1'h0, _address_ok_T_50}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_52 = _address_ok_T_51 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_53 = _address_ok_T_52; // @[Parameters.scala:137:46] wire _address_ok_T_54 = _address_ok_T_53 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_10 = _address_ok_T_54; // @[Parameters.scala:612:40] wire [25:0] _GEN_5 = io_in_b_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_55 = {io_in_b_bits_address_0[31:26], _GEN_5}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_56 = {1'h0, _address_ok_T_55}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_57 = _address_ok_T_56 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_58 = _address_ok_T_57; // @[Parameters.scala:137:46] wire _address_ok_T_59 = _address_ok_T_58 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_11 = _address_ok_T_59; // @[Parameters.scala:612:40] wire [25:0] _GEN_6 = io_in_b_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_60 = {io_in_b_bits_address_0[31:26], _GEN_6}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_61 = {1'h0, _address_ok_T_60}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_62 = _address_ok_T_61 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_63 = _address_ok_T_62; // @[Parameters.scala:137:46] wire _address_ok_T_64 = _address_ok_T_63 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_12 = _address_ok_T_64; // @[Parameters.scala:612:40] wire [27:0] _GEN_7 = io_in_b_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_65 = {io_in_b_bits_address_0[31:28], _GEN_7}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_66 = {1'h0, _address_ok_T_65}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_67 = _address_ok_T_66 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_68 = _address_ok_T_67; // @[Parameters.scala:137:46] wire _address_ok_T_69 = _address_ok_T_68 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_13 = _address_ok_T_69; // @[Parameters.scala:612:40] wire [27:0] _GEN_8 = io_in_b_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_70 = {io_in_b_bits_address_0[31:28], _GEN_8}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_71 = {1'h0, _address_ok_T_70}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_72 = _address_ok_T_71 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_73 = _address_ok_T_72; // @[Parameters.scala:137:46] wire _address_ok_T_74 = _address_ok_T_73 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_14 = _address_ok_T_74; // @[Parameters.scala:612:40] wire [28:0] _GEN_9 = io_in_b_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_75 = {io_in_b_bits_address_0[31:29], _GEN_9}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_76 = {1'h0, _address_ok_T_75}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_77 = _address_ok_T_76 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_78 = _address_ok_T_77; // @[Parameters.scala:137:46] wire _address_ok_T_79 = _address_ok_T_78 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_15 = _address_ok_T_79; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_80 = io_in_b_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_81 = {1'h0, _address_ok_T_80}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_82 = _address_ok_T_81 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_83 = _address_ok_T_82; // @[Parameters.scala:137:46] wire _address_ok_T_84 = _address_ok_T_83 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_16 = _address_ok_T_84; // @[Parameters.scala:612:40] wire _address_ok_T_85 = _address_ok_WIRE_0 | _address_ok_WIRE_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_86 = _address_ok_T_85 | _address_ok_WIRE_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_87 = _address_ok_T_86 | _address_ok_WIRE_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_88 = _address_ok_T_87 | _address_ok_WIRE_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_89 = _address_ok_T_88 | _address_ok_WIRE_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_90 = _address_ok_T_89 | _address_ok_WIRE_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_91 = _address_ok_T_90 | _address_ok_WIRE_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_92 = _address_ok_T_91 | _address_ok_WIRE_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_93 = _address_ok_T_92 | _address_ok_WIRE_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_94 = _address_ok_T_93 | _address_ok_WIRE_10; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_95 = _address_ok_T_94 | _address_ok_WIRE_11; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_96 = _address_ok_T_95 | _address_ok_WIRE_12; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_97 = _address_ok_T_96 | _address_ok_WIRE_13; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_98 = _address_ok_T_97 | _address_ok_WIRE_14; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_99 = _address_ok_T_98 | _address_ok_WIRE_15; // @[Parameters.scala:612:40, :636:64] wire address_ok = _address_ok_T_99 | _address_ok_WIRE_16; // @[Parameters.scala:612:40, :636:64] wire [31:0] _is_aligned_T_1 = {26'h0, io_in_b_bits_address_0[5:0]}; // @[Monitor.scala:36:7] wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2_1 = mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2_1 = mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_0_2_1; // @[Misc.scala:214:27, :215:38] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_1_2_1; // @[Misc.scala:214:27, :215:38] wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_eq_8 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_eq_8; // @[Misc.scala:214:27, :215:38] wire mask_eq_9 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_eq_9; // @[Misc.scala:214:27, :215:38] wire mask_eq_10 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_eq_10; // @[Misc.scala:214:27, :215:38] wire mask_eq_11 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_eq_11; // @[Misc.scala:214:27, :215:38] wire mask_eq_12 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_eq_12; // @[Misc.scala:214:27, :215:38] wire mask_eq_13 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_eq_13; // @[Misc.scala:214:27, :215:38] wire mask_eq_14 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_eq_14; // @[Misc.scala:214:27, :215:38] wire mask_eq_15 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_eq_15; // @[Misc.scala:214:27, :215:38] wire _legal_source_T = ~io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire _legal_source_WIRE_0 = _legal_source_T; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_1 = _legal_source_T_1; // @[Parameters.scala:1138:31] wire _legal_source_T_3 = _legal_source_WIRE_1; // @[Mux.scala:30:73] wire _legal_source_T_4 = _legal_source_T_3; // @[Mux.scala:30:73] wire _legal_source_WIRE_1_0 = _legal_source_T_4; // @[Mux.scala:30:73] wire legal_source = _legal_source_WIRE_1_0 == io_in_b_bits_source_0; // @[Mux.scala:30:73] wire _source_ok_T_4 = ~io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_0 = _source_ok_T_4; // @[Parameters.scala:1138:31] wire _source_ok_WIRE_2_1 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire source_ok_2 = _source_ok_WIRE_2_0 | _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN_10 = 27'hFFF << io_in_c_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_4; // @[package.scala:243:71] assign _is_aligned_mask_T_4 = _GEN_10; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T; // @[package.scala:243:71] assign _c_first_beats1_decode_T = _GEN_10; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71] assign _c_first_beats1_decode_T_3 = _GEN_10; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_2 = {20'h0, io_in_c_bits_address_0[11:0] & is_aligned_mask_2}; // @[package.scala:243:46] wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}] wire [32:0] _address_ok_T_101 = {1'h0, _address_ok_T_100}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_102 = _address_ok_T_101 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_103 = _address_ok_T_102; // @[Parameters.scala:137:46] wire _address_ok_T_104 = _address_ok_T_103 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_0 = _address_ok_T_104; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_105 = {io_in_c_bits_address_0[31:13], io_in_c_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_106 = {1'h0, _address_ok_T_105}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_107 = _address_ok_T_106 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_108 = _address_ok_T_107; // @[Parameters.scala:137:46] wire _address_ok_T_109 = _address_ok_T_108 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_1 = _address_ok_T_109; // @[Parameters.scala:612:40] wire [13:0] _GEN_11 = io_in_c_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_110 = {io_in_c_bits_address_0[31:14], _GEN_11}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_111 = {1'h0, _address_ok_T_110}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_112 = _address_ok_T_111 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_113 = _address_ok_T_112; // @[Parameters.scala:137:46] wire _address_ok_T_114 = _address_ok_T_113 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_2 = _address_ok_T_114; // @[Parameters.scala:612:40] wire [16:0] _GEN_12 = io_in_c_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_115 = {io_in_c_bits_address_0[31:17], _GEN_12}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_116 = {1'h0, _address_ok_T_115}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_117 = _address_ok_T_116 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_118 = _address_ok_T_117; // @[Parameters.scala:137:46] wire _address_ok_T_119 = _address_ok_T_118 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_3 = _address_ok_T_119; // @[Parameters.scala:612:40] wire [17:0] _GEN_13 = io_in_c_bits_address_0[17:0] ^ 18'h20000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_120 = {io_in_c_bits_address_0[31:18], _GEN_13}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_121 = {1'h0, _address_ok_T_120}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_122 = _address_ok_T_121 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_123 = _address_ok_T_122; // @[Parameters.scala:137:46] wire _address_ok_T_124 = _address_ok_T_123 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_4 = _address_ok_T_124; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_125 = {io_in_c_bits_address_0[31:18], io_in_c_bits_address_0[17:0] ^ 18'h21000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_126 = {1'h0, _address_ok_T_125}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_127 = _address_ok_T_126 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_128 = _address_ok_T_127; // @[Parameters.scala:137:46] wire _address_ok_T_129 = _address_ok_T_128 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_5 = _address_ok_T_129; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_130 = {io_in_c_bits_address_0[31:18], io_in_c_bits_address_0[17:0] ^ 18'h22000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_131 = {1'h0, _address_ok_T_130}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_132 = _address_ok_T_131 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_133 = _address_ok_T_132; // @[Parameters.scala:137:46] wire _address_ok_T_134 = _address_ok_T_133 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_6 = _address_ok_T_134; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_135 = {io_in_c_bits_address_0[31:18], io_in_c_bits_address_0[17:0] ^ 18'h23000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_136 = {1'h0, _address_ok_T_135}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_137 = _address_ok_T_136 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_138 = _address_ok_T_137; // @[Parameters.scala:137:46] wire _address_ok_T_139 = _address_ok_T_138 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_7 = _address_ok_T_139; // @[Parameters.scala:612:40] wire [17:0] _GEN_14 = io_in_c_bits_address_0[17:0] ^ 18'h24000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_140 = {io_in_c_bits_address_0[31:18], _GEN_14}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_141 = {1'h0, _address_ok_T_140}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_142 = _address_ok_T_141 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_143 = _address_ok_T_142; // @[Parameters.scala:137:46] wire _address_ok_T_144 = _address_ok_T_143 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_8 = _address_ok_T_144; // @[Parameters.scala:612:40] wire [20:0] _GEN_15 = io_in_c_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_145 = {io_in_c_bits_address_0[31:21], _GEN_15}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_146 = {1'h0, _address_ok_T_145}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_147 = _address_ok_T_146 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_148 = _address_ok_T_147; // @[Parameters.scala:137:46] wire _address_ok_T_149 = _address_ok_T_148 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_9 = _address_ok_T_149; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_150 = {io_in_c_bits_address_0[31:21], io_in_c_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_151 = {1'h0, _address_ok_T_150}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_152 = _address_ok_T_151 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_153 = _address_ok_T_152; // @[Parameters.scala:137:46] wire _address_ok_T_154 = _address_ok_T_153 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_10 = _address_ok_T_154; // @[Parameters.scala:612:40] wire [25:0] _GEN_16 = io_in_c_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_155 = {io_in_c_bits_address_0[31:26], _GEN_16}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_156 = {1'h0, _address_ok_T_155}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_157 = _address_ok_T_156 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_158 = _address_ok_T_157; // @[Parameters.scala:137:46] wire _address_ok_T_159 = _address_ok_T_158 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_11 = _address_ok_T_159; // @[Parameters.scala:612:40] wire [25:0] _GEN_17 = io_in_c_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_160 = {io_in_c_bits_address_0[31:26], _GEN_17}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_161 = {1'h0, _address_ok_T_160}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_162 = _address_ok_T_161 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_163 = _address_ok_T_162; // @[Parameters.scala:137:46] wire _address_ok_T_164 = _address_ok_T_163 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_12 = _address_ok_T_164; // @[Parameters.scala:612:40] wire [27:0] _GEN_18 = io_in_c_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_165 = {io_in_c_bits_address_0[31:28], _GEN_18}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_166 = {1'h0, _address_ok_T_165}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_167 = _address_ok_T_166 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_168 = _address_ok_T_167; // @[Parameters.scala:137:46] wire _address_ok_T_169 = _address_ok_T_168 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_13 = _address_ok_T_169; // @[Parameters.scala:612:40] wire [27:0] _GEN_19 = io_in_c_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_170 = {io_in_c_bits_address_0[31:28], _GEN_19}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_171 = {1'h0, _address_ok_T_170}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_172 = _address_ok_T_171 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_173 = _address_ok_T_172; // @[Parameters.scala:137:46] wire _address_ok_T_174 = _address_ok_T_173 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_14 = _address_ok_T_174; // @[Parameters.scala:612:40] wire [28:0] _GEN_20 = io_in_c_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_175 = {io_in_c_bits_address_0[31:29], _GEN_20}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_176 = {1'h0, _address_ok_T_175}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_177 = _address_ok_T_176 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_178 = _address_ok_T_177; // @[Parameters.scala:137:46] wire _address_ok_T_179 = _address_ok_T_178 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_15 = _address_ok_T_179; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_180 = io_in_c_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_181 = {1'h0, _address_ok_T_180}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_182 = _address_ok_T_181 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_183 = _address_ok_T_182; // @[Parameters.scala:137:46] wire _address_ok_T_184 = _address_ok_T_183 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_16 = _address_ok_T_184; // @[Parameters.scala:612:40] wire _address_ok_T_185 = _address_ok_WIRE_1_0 | _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_186 = _address_ok_T_185 | _address_ok_WIRE_1_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_187 = _address_ok_T_186 | _address_ok_WIRE_1_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_188 = _address_ok_T_187 | _address_ok_WIRE_1_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_189 = _address_ok_T_188 | _address_ok_WIRE_1_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_190 = _address_ok_T_189 | _address_ok_WIRE_1_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_191 = _address_ok_T_190 | _address_ok_WIRE_1_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_192 = _address_ok_T_191 | _address_ok_WIRE_1_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_193 = _address_ok_T_192 | _address_ok_WIRE_1_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_194 = _address_ok_T_193 | _address_ok_WIRE_1_10; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_195 = _address_ok_T_194 | _address_ok_WIRE_1_11; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_196 = _address_ok_T_195 | _address_ok_WIRE_1_12; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_197 = _address_ok_T_196 | _address_ok_WIRE_1_13; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_198 = _address_ok_T_197 | _address_ok_WIRE_1_14; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_199 = _address_ok_T_198 | _address_ok_WIRE_1_15; // @[Parameters.scala:612:40, :636:64] wire address_ok_1 = _address_ok_T_199 | _address_ok_WIRE_1_16; // @[Parameters.scala:612:40, :636:64] wire _T_2656 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_2656; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_2656; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_2730 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_2730; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_2730; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_2730; // @[Decoupled.scala:51:35] wire _d_first_T_3; // @[Decoupled.scala:51:35] assign _d_first_T_3 = _T_2730; // @[Decoupled.scala:51:35] wire [26:0] _GEN_21 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_21; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_21; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_21; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71] assign _d_first_beats1_decode_T_9 = _GEN_21; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35] wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35] reg [8:0] b_first_counter; // @[Edges.scala:229:27] wire [9:0] _b_first_counter1_T = {1'h0, b_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] b_first_counter1 = _b_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire b_first = b_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _b_first_last_T = b_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire [8:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] _b_first_counter_T = b_first ? 9'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [1:0] param_2; // @[Monitor.scala:411:22] reg source_2; // @[Monitor.scala:413:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _T_2727 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35] wire _c_first_T; // @[Decoupled.scala:51:35] assign _c_first_T = _T_2727; // @[Decoupled.scala:51:35] wire _c_first_T_1; // @[Decoupled.scala:51:35] assign _c_first_T_1 = _T_2727; // @[Decoupled.scala:51:35] wire [11:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [8:0] c_first_counter; // @[Edges.scala:229:27] wire [9:0] _c_first_counter1_T = {1'h0, c_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] c_first_counter1 = _c_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire c_first = c_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T = c_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_1 = c_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last = _c_first_last_T | _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35] wire [8:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [3:0] size_3; // @[Monitor.scala:517:22] reg source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [7:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [15:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [1:0] a_set; // @[Monitor.scala:626:34] wire [1:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [7:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [15:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [3:0] _GEN_22 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [3:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_22; // @[Monitor.scala:637:69] wire [3:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_22; // @[Monitor.scala:637:69, :680:101] wire [3:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_22; // @[Monitor.scala:637:69, :749:69] wire [3:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_22; // @[Monitor.scala:637:69, :790:101] wire [7:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [15:0] _a_opcode_lookup_T_6 = {8'h0, _a_opcode_lookup_T_1 & 8'hF}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [3:0] _GEN_23 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [3:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_23; // @[Monitor.scala:641:65] wire [3:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_23; // @[Monitor.scala:641:65, :681:99] wire [3:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_23; // @[Monitor.scala:641:65, :750:67] wire [3:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_23; // @[Monitor.scala:641:65, :791:99] wire [15:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [15:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & 16'hFF; // @[Monitor.scala:641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [1:0] _GEN_24 = {1'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_25 = 2'h1 << _GEN_24; // @[OneHot.scala:58:35] wire [1:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_25; // @[OneHot.scala:58:35] wire [1:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_25; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 2'h0; // @[OneHot.scala:58:35] wire _T_2582 = _T_2656 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_2582 ? _a_set_T : 2'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_2582 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_2582 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [3:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_2582 ? _a_opcodes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [3:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :660:{52,77}] assign a_sizes_set = _T_2582 ? _a_sizes_set_T_1[15:0] : 16'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [1:0] d_clr; // @[Monitor.scala:664:34] wire [1:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [7:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [15:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_26 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_26; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_26; // @[Monitor.scala:673:46, :783:46] wire _T_2628 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [1:0] _GEN_27 = {1'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_28 = 2'h1 << _GEN_27; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_28; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_28; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_28; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_28; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_2628 & ~d_release_ack ? _d_clr_wo_ready_T : 2'h0; // @[OneHot.scala:58:35] wire _T_2597 = _T_2730 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_2597 ? _d_clr_T : 2'h0; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_5 = 31'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_2597 ? _d_opcodes_clr_T_5[7:0] : 8'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [30:0] _d_sizes_clr_T_5 = 31'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_2597 ? _d_sizes_clr_T_5[15:0] : 16'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [1:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [7:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [7:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [7:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [15:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [15:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [15:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] reg [7:0] inflight_opcodes_1; // @[Monitor.scala:727:35] reg [15:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [11:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [8:0] c_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] c_first_counter1_1 = _c_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire c_first_1 = c_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T_2 = c_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_3 = c_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last_1 = _c_first_last_T_2 | _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [1:0] c_set; // @[Monitor.scala:738:34] wire [1:0] c_set_wo_ready; // @[Monitor.scala:739:34] wire [7:0] c_opcodes_set; // @[Monitor.scala:740:34] wire [15:0] c_sizes_set; // @[Monitor.scala:741:34] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [7:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [15:0] _c_opcode_lookup_T_6 = {8'h0, _c_opcode_lookup_T_1 & 8'hF}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [15:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & 16'hFF; // @[Monitor.scala:750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40] wire [4:0] c_sizes_set_interm; // @[Monitor.scala:755:40] wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44] wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7] wire [1:0] _GEN_29 = {1'h0, io_in_c_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_30 = 2'h1 << _GEN_29; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35] assign _c_set_wo_ready_T = _GEN_30; // @[OneHot.scala:58:35] wire [1:0] _c_set_T; // @[OneHot.scala:58:35] assign _c_set_T = _GEN_30; // @[OneHot.scala:58:35] assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T : 2'h0; // @[OneHot.scala:58:35] wire _T_2669 = _T_2727 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35] assign c_set = _T_2669 ? _c_set_T : 2'h0; // @[OneHot.scala:58:35] wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53] wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}] assign c_opcodes_set_interm = _T_2669 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}] wire [4:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51] wire [4:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:766:{51,59}] assign c_sizes_set_interm = _T_2669 ? _c_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}] wire [3:0] _c_opcodes_set_T = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79] wire [18:0] _c_opcodes_set_T_1 = {15'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:754:40, :767:{54,79}] assign c_opcodes_set = _T_2669 ? _c_opcodes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}] wire [3:0] _c_sizes_set_T = {io_in_c_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :768:77] wire [19:0] _c_sizes_set_T_1 = {15'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:755:40, :768:{52,77}] assign c_sizes_set = _T_2669 ? _c_sizes_set_T_1[15:0] : 16'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}] wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47] wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95] wire c_probe_ack = _c_probe_ack_T | _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}] wire [1:0] d_clr_1; // @[Monitor.scala:774:34] wire [1:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [7:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [15:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_2700 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_2700 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 2'h0; // @[OneHot.scala:58:35] wire _T_2682 = _T_2730 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_2682 ? _d_clr_T_1 : 2'h0; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_11 = 31'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_2682 ? _d_opcodes_clr_T_11[7:0] : 8'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [30:0] _d_sizes_clr_T_11 = 31'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_2682 ? _d_sizes_clr_T_11[15:0] : 16'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}] wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}] wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}] wire [1:0] _inflight_T_3 = inflight_1 | c_set; // @[Monitor.scala:726:35, :738:34, :814:35] wire [1:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [7:0] _inflight_opcodes_T_3 = inflight_opcodes_1 | c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43] wire [7:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [7:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [15:0] _inflight_sizes_T_3 = inflight_sizes_1 | c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41] wire [15:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [15:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26] wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26] reg [7:0] inflight_2; // @[Monitor.scala:828:27] wire [11:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_3; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_3 = _d_first_counter1_T_3[8:0]; // @[Edges.scala:230:28] wire d_first_3 = d_first_counter_3 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_6 = d_first_counter_3 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_7 = d_first_beats1_3 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_3 = _d_first_last_T_6 | _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}] wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [7:0] d_set; // @[Monitor.scala:833:25] wire _T_2736 = _T_2730 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35] wire [7:0] _GEN_31 = {5'h0, io_in_d_bits_sink_0}; // @[OneHot.scala:58:35] wire [7:0] _d_set_T = 8'h1 << _GEN_31; // @[OneHot.scala:58:35] assign d_set = _T_2736 ? _d_set_T : 8'h0; // @[OneHot.scala:58:35] wire [7:0] e_clr; // @[Monitor.scala:839:25] wire _T_2745 = io_in_e_ready_0 & io_in_e_valid_0; // @[Decoupled.scala:51:35] wire [7:0] _GEN_32 = {5'h0, io_in_e_bits_sink_0}; // @[OneHot.scala:58:35] wire [7:0] _e_clr_T = 8'h1 << _GEN_32; // @[OneHot.scala:58:35] assign e_clr = _T_2745 ? _e_clr_T : 8'h0; // @[OneHot.scala:58:35]

Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }

module AsyncQueueSink_TLBundleA_a32d64s2k3z4c( // @[AsyncQueue.scala:136:7] input clock, // @[AsyncQueue.scala:136:7] input reset, // @[AsyncQueue.scala:136:7] input io_deq_ready, // @[AsyncQueue.scala:139:14] output io_deq_valid, // @[AsyncQueue.scala:139:14] output [2:0] io_deq_bits_opcode, // @[AsyncQueue.scala:139:14] output [2:0] io_deq_bits_param, // @[AsyncQueue.scala:139:14] output [3:0] io_deq_bits_size, // @[AsyncQueue.scala:139:14] output [1:0] io_deq_bits_source, // @[AsyncQueue.scala:139:14] output [31:0] io_deq_bits_address, // @[AsyncQueue.scala:139:14] output [7:0] io_deq_bits_mask, // @[AsyncQueue.scala:139:14] output [63:0] io_deq_bits_data, // @[AsyncQueue.scala:139:14] output io_deq_bits_corrupt, // @[AsyncQueue.scala:139:14] input [2:0] io_async_mem_0_opcode, // @[AsyncQueue.scala:139:14] input [2:0] io_async_mem_0_param, // @[AsyncQueue.scala:139:14] input [3:0] io_async_mem_0_size, // @[AsyncQueue.scala:139:14] input [1:0] io_async_mem_0_source, // @[AsyncQueue.scala:139:14] input [31:0] io_async_mem_0_address, // @[AsyncQueue.scala:139:14] input [7:0] io_async_mem_0_mask, // @[AsyncQueue.scala:139:14] input [63:0] io_async_mem_0_data, // @[AsyncQueue.scala:139:14] input [2:0] io_async_mem_1_opcode, // @[AsyncQueue.scala:139:14] input [2:0] io_async_mem_1_param, // @[AsyncQueue.scala:139:14] input [3:0] io_async_mem_1_size, // @[AsyncQueue.scala:139:14] input [1:0] io_async_mem_1_source, // @[AsyncQueue.scala:139:14] input [31:0] io_async_mem_1_address, // @[AsyncQueue.scala:139:14] input [7:0] io_async_mem_1_mask, // @[AsyncQueue.scala:139:14] input [63:0] io_async_mem_1_data, // @[AsyncQueue.scala:139:14] input [2:0] io_async_mem_2_opcode, // @[AsyncQueue.scala:139:14] input [2:0] io_async_mem_2_param, // @[AsyncQueue.scala:139:14] input [3:0] io_async_mem_2_size, // @[AsyncQueue.scala:139:14] input [1:0] io_async_mem_2_source, // @[AsyncQueue.scala:139:14] input [31:0] io_async_mem_2_address, // @[AsyncQueue.scala:139:14] input [7:0] io_async_mem_2_mask, // @[AsyncQueue.scala:139:14] input [63:0] io_async_mem_2_data, // @[AsyncQueue.scala:139:14] input [2:0] io_async_mem_3_opcode, // @[AsyncQueue.scala:139:14] input [2:0] io_async_mem_3_param, // @[AsyncQueue.scala:139:14] input [3:0] io_async_mem_3_size, // @[AsyncQueue.scala:139:14] input [1:0] io_async_mem_3_source, // @[AsyncQueue.scala:139:14] input [31:0] io_async_mem_3_address, // @[AsyncQueue.scala:139:14] input [7:0] io_async_mem_3_mask, // @[AsyncQueue.scala:139:14] input [63:0] io_async_mem_3_data, // @[AsyncQueue.scala:139:14] input [2:0] io_async_mem_4_opcode, // @[AsyncQueue.scala:139:14] input [2:0] io_async_mem_4_param, // @[AsyncQueue.scala:139:14] input [3:0] io_async_mem_4_size, // @[AsyncQueue.scala:139:14] input [1:0] io_async_mem_4_source, // @[AsyncQueue.scala:139:14] input [31:0] io_async_mem_4_address, // @[AsyncQueue.scala:139:14] input [7:0] io_async_mem_4_mask, // @[AsyncQueue.scala:139:14] input [63:0] io_async_mem_4_data, // @[AsyncQueue.scala:139:14] input [2:0] io_async_mem_5_opcode, // @[AsyncQueue.scala:139:14] input [2:0] io_async_mem_5_param, // @[AsyncQueue.scala:139:14] input [3:0] io_async_mem_5_size, // @[AsyncQueue.scala:139:14] input [1:0] io_async_mem_5_source, // @[AsyncQueue.scala:139:14] input [31:0] io_async_mem_5_address, // @[AsyncQueue.scala:139:14] input [7:0] io_async_mem_5_mask, // @[AsyncQueue.scala:139:14] input [63:0] io_async_mem_5_data, // @[AsyncQueue.scala:139:14] input [2:0] io_async_mem_6_opcode, // @[AsyncQueue.scala:139:14] input [2:0] io_async_mem_6_param, // @[AsyncQueue.scala:139:14] input [3:0] io_async_mem_6_size, // @[AsyncQueue.scala:139:14] input [1:0] io_async_mem_6_source, // @[AsyncQueue.scala:139:14] input [31:0] io_async_mem_6_address, // @[AsyncQueue.scala:139:14] input [7:0] io_async_mem_6_mask, // @[AsyncQueue.scala:139:14] input [63:0] io_async_mem_6_data, // @[AsyncQueue.scala:139:14] input [2:0] io_async_mem_7_opcode, // @[AsyncQueue.scala:139:14] input [2:0] io_async_mem_7_param, // @[AsyncQueue.scala:139:14] input [3:0] io_async_mem_7_size, // @[AsyncQueue.scala:139:14] input [1:0] io_async_mem_7_source, // @[AsyncQueue.scala:139:14] input [31:0] io_async_mem_7_address, // @[AsyncQueue.scala:139:14] input [7:0] io_async_mem_7_mask, // @[AsyncQueue.scala:139:14] input [63:0] io_async_mem_7_data, // @[AsyncQueue.scala:139:14] output [3:0] io_async_ridx, // @[AsyncQueue.scala:139:14] input [3:0] io_async_widx, // @[AsyncQueue.scala:139:14] output io_async_safe_ridx_valid, // @[AsyncQueue.scala:139:14] input io_async_safe_widx_valid, // @[AsyncQueue.scala:139:14] input io_async_safe_source_reset_n, // @[AsyncQueue.scala:139:14] output io_async_safe_sink_reset_n // @[AsyncQueue.scala:139:14] ); wire _source_extend_io_out; // @[AsyncQueue.scala:175:31] wire _sink_valid_0_io_out; // @[AsyncQueue.scala:172:33] wire io_deq_ready_0 = io_deq_ready; // @[AsyncQueue.scala:136:7] wire [2:0] io_async_mem_0_opcode_0 = io_async_mem_0_opcode; // @[AsyncQueue.scala:136:7] wire [2:0] io_async_mem_0_param_0 = io_async_mem_0_param; // @[AsyncQueue.scala:136:7] wire [3:0] io_async_mem_0_size_0 = io_async_mem_0_size; // @[AsyncQueue.scala:136:7] wire [1:0] io_async_mem_0_source_0 = io_async_mem_0_source; // @[AsyncQueue.scala:136:7] wire [31:0] io_async_mem_0_address_0 = io_async_mem_0_address; // @[AsyncQueue.scala:136:7] wire [7:0] io_async_mem_0_mask_0 = io_async_mem_0_mask; // @[AsyncQueue.scala:136:7] wire [63:0] io_async_mem_0_data_0 = io_async_mem_0_data; // @[AsyncQueue.scala:136:7] wire [2:0] io_async_mem_1_opcode_0 = io_async_mem_1_opcode; // @[AsyncQueue.scala:136:7] wire [2:0] io_async_mem_1_param_0 = io_async_mem_1_param; // @[AsyncQueue.scala:136:7] wire [3:0] io_async_mem_1_size_0 = io_async_mem_1_size; // @[AsyncQueue.scala:136:7] wire [1:0] io_async_mem_1_source_0 = io_async_mem_1_source; // @[AsyncQueue.scala:136:7] wire [31:0] io_async_mem_1_address_0 = io_async_mem_1_address; // @[AsyncQueue.scala:136:7] wire [7:0] io_async_mem_1_mask_0 = io_async_mem_1_mask; // @[AsyncQueue.scala:136:7] wire [63:0] io_async_mem_1_data_0 = io_async_mem_1_data; // @[AsyncQueue.scala:136:7] wire [2:0] io_async_mem_2_opcode_0 = io_async_mem_2_opcode; // @[AsyncQueue.scala:136:7] wire [2:0] io_async_mem_2_param_0 = io_async_mem_2_param; // @[AsyncQueue.scala:136:7] wire [3:0] io_async_mem_2_size_0 = io_async_mem_2_size; // @[AsyncQueue.scala:136:7] wire [1:0] io_async_mem_2_source_0 = io_async_mem_2_source; // @[AsyncQueue.scala:136:7] wire [31:0] io_async_mem_2_address_0 = io_async_mem_2_address; // @[AsyncQueue.scala:136:7] wire [7:0] io_async_mem_2_mask_0 = io_async_mem_2_mask; // @[AsyncQueue.scala:136:7] wire [63:0] io_async_mem_2_data_0 = io_async_mem_2_data; // @[AsyncQueue.scala:136:7] wire [2:0] io_async_mem_3_opcode_0 = io_async_mem_3_opcode; // @[AsyncQueue.scala:136:7] wire [2:0] io_async_mem_3_param_0 = io_async_mem_3_param; // @[AsyncQueue.scala:136:7] wire [3:0] io_async_mem_3_size_0 = io_async_mem_3_size; // @[AsyncQueue.scala:136:7] wire [1:0] io_async_mem_3_source_0 = io_async_mem_3_source; // @[AsyncQueue.scala:136:7] wire [31:0] io_async_mem_3_address_0 = io_async_mem_3_address; // @[AsyncQueue.scala:136:7] wire [7:0] io_async_mem_3_mask_0 = io_async_mem_3_mask; // @[AsyncQueue.scala:136:7] wire [63:0] io_async_mem_3_data_0 = io_async_mem_3_data; // @[AsyncQueue.scala:136:7] wire [2:0] io_async_mem_4_opcode_0 = io_async_mem_4_opcode; // @[AsyncQueue.scala:136:7] wire [2:0] io_async_mem_4_param_0 = io_async_mem_4_param; // @[AsyncQueue.scala:136:7] wire [3:0] io_async_mem_4_size_0 = io_async_mem_4_size; // @[AsyncQueue.scala:136:7] wire [1:0] io_async_mem_4_source_0 = io_async_mem_4_source; // @[AsyncQueue.scala:136:7] wire [31:0] io_async_mem_4_address_0 = io_async_mem_4_address; // @[AsyncQueue.scala:136:7] wire [7:0] io_async_mem_4_mask_0 = io_async_mem_4_mask; // @[AsyncQueue.scala:136:7] wire [63:0] io_async_mem_4_data_0 = io_async_mem_4_data; // @[AsyncQueue.scala:136:7] wire [2:0] io_async_mem_5_opcode_0 = io_async_mem_5_opcode; // @[AsyncQueue.scala:136:7] wire [2:0] io_async_mem_5_param_0 = io_async_mem_5_param; // @[AsyncQueue.scala:136:7] wire [3:0] io_async_mem_5_size_0 = io_async_mem_5_size; // @[AsyncQueue.scala:136:7] wire [1:0] io_async_mem_5_source_0 = io_async_mem_5_source; // @[AsyncQueue.scala:136:7] wire [31:0] io_async_mem_5_address_0 = io_async_mem_5_address; // @[AsyncQueue.scala:136:7] wire [7:0] io_async_mem_5_mask_0 = io_async_mem_5_mask; // @[AsyncQueue.scala:136:7] wire [63:0] io_async_mem_5_data_0 = io_async_mem_5_data; // @[AsyncQueue.scala:136:7] wire [2:0] io_async_mem_6_opcode_0 = io_async_mem_6_opcode; // @[AsyncQueue.scala:136:7] wire [2:0] io_async_mem_6_param_0 = io_async_mem_6_param; // @[AsyncQueue.scala:136:7] wire [3:0] io_async_mem_6_size_0 = io_async_mem_6_size; // @[AsyncQueue.scala:136:7] wire [1:0] io_async_mem_6_source_0 = io_async_mem_6_source; // @[AsyncQueue.scala:136:7] wire [31:0] io_async_mem_6_address_0 = io_async_mem_6_address; // @[AsyncQueue.scala:136:7] wire [7:0] io_async_mem_6_mask_0 = io_async_mem_6_mask; // @[AsyncQueue.scala:136:7] wire [63:0] io_async_mem_6_data_0 = io_async_mem_6_data; // @[AsyncQueue.scala:136:7] wire [2:0] io_async_mem_7_opcode_0 = io_async_mem_7_opcode; // @[AsyncQueue.scala:136:7] wire [2:0] io_async_mem_7_param_0 = io_async_mem_7_param; // @[AsyncQueue.scala:136:7] wire [3:0] io_async_mem_7_size_0 = io_async_mem_7_size; // @[AsyncQueue.scala:136:7] wire [1:0] io_async_mem_7_source_0 = io_async_mem_7_source; // @[AsyncQueue.scala:136:7] wire [31:0] io_async_mem_7_address_0 = io_async_mem_7_address; // @[AsyncQueue.scala:136:7] wire [7:0] io_async_mem_7_mask_0 = io_async_mem_7_mask; // @[AsyncQueue.scala:136:7] wire [63:0] io_async_mem_7_data_0 = io_async_mem_7_data; // @[AsyncQueue.scala:136:7] wire [3:0] io_async_widx_0 = io_async_widx; // @[AsyncQueue.scala:136:7] wire io_async_safe_widx_valid_0 = io_async_safe_widx_valid; // @[AsyncQueue.scala:136:7] wire io_async_safe_source_reset_n_0 = io_async_safe_source_reset_n; // @[AsyncQueue.scala:136:7] wire _ridx_T = reset; // @[AsyncQueue.scala:148:30] wire _valid_reg_T = reset; // @[AsyncQueue.scala:165:35] wire _ridx_reg_T = reset; // @[AsyncQueue.scala:168:34] wire _sink_valid_0_reset_T = reset; // @[AsyncQueue.scala:177:35] wire _sink_valid_1_reset_T = reset; // @[AsyncQueue.scala:178:35] wire _source_extend_reset_T = reset; // @[AsyncQueue.scala:179:35] wire _source_valid_reset_T = reset; // @[AsyncQueue.scala:180:34] wire _io_async_safe_sink_reset_n_T = reset; // @[AsyncQueue.scala:193:32] wire io_async_mem_0_corrupt = 1'h0; // @[AsyncQueue.scala:136:7] wire io_async_mem_1_corrupt = 1'h0; // @[AsyncQueue.scala:136:7] wire io_async_mem_2_corrupt = 1'h0; // @[AsyncQueue.scala:136:7] wire io_async_mem_3_corrupt = 1'h0; // @[AsyncQueue.scala:136:7] wire io_async_mem_4_corrupt = 1'h0; // @[AsyncQueue.scala:136:7] wire io_async_mem_5_corrupt = 1'h0; // @[AsyncQueue.scala:136:7] wire io_async_mem_6_corrupt = 1'h0; // @[AsyncQueue.scala:136:7] wire io_async_mem_7_corrupt = 1'h0; // @[AsyncQueue.scala:136:7] wire _io_deq_valid_T; // @[AsyncQueue.scala:166:29] wire [2:0] _io_deq_bits_WIRE_opcode; // @[SynchronizerReg.scala:211:26] wire [2:0] _io_deq_bits_WIRE_param; // @[SynchronizerReg.scala:211:26] wire [3:0] _io_deq_bits_WIRE_size; // @[SynchronizerReg.scala:211:26] wire [1:0] _io_deq_bits_WIRE_source; // @[SynchronizerReg.scala:211:26] wire [31:0] _io_deq_bits_WIRE_address; // @[SynchronizerReg.scala:211:26] wire [7:0] _io_deq_bits_WIRE_mask; // @[SynchronizerReg.scala:211:26] wire [63:0] _io_deq_bits_WIRE_data; // @[SynchronizerReg.scala:211:26] wire _io_deq_bits_WIRE_corrupt; // @[SynchronizerReg.scala:211:26] wire _io_async_safe_sink_reset_n_T_1; // @[AsyncQueue.scala:193:25] wire [2:0] io_deq_bits_opcode_0; // @[AsyncQueue.scala:136:7] wire [2:0] io_deq_bits_param_0; // @[AsyncQueue.scala:136:7] wire [3:0] io_deq_bits_size_0; // @[AsyncQueue.scala:136:7] wire [1:0] io_deq_bits_source_0; // @[AsyncQueue.scala:136:7] wire [31:0] io_deq_bits_address_0; // @[AsyncQueue.scala:136:7] wire [7:0] io_deq_bits_mask_0; // @[AsyncQueue.scala:136:7] wire [63:0] io_deq_bits_data_0; // @[AsyncQueue.scala:136:7] wire io_deq_bits_corrupt_0; // @[AsyncQueue.scala:136:7] wire io_deq_valid_0; // @[AsyncQueue.scala:136:7] wire io_async_safe_ridx_valid_0; // @[AsyncQueue.scala:136:7] wire io_async_safe_sink_reset_n_0; // @[AsyncQueue.scala:136:7] wire [3:0] io_async_ridx_0; // @[AsyncQueue.scala:136:7] wire source_ready; // @[AsyncQueue.scala:147:30] wire _ridx_T_1 = io_deq_ready_0 & io_deq_valid_0; // @[Decoupled.scala:51:35] wire _ridx_T_2 = ~source_ready; // @[AsyncQueue.scala:147:30, :148:77] wire [3:0] _ridx_incremented_T_2; // @[AsyncQueue.scala:53:23] wire [3:0] ridx_incremented; // @[AsyncQueue.scala:51:27] reg [3:0] ridx_ridx_bin; // @[AsyncQueue.scala:52:25] wire [4:0] _ridx_incremented_T = {1'h0, ridx_ridx_bin} + {4'h0, _ridx_T_1}; // @[Decoupled.scala:51:35] wire [3:0] _ridx_incremented_T_1 = _ridx_incremented_T[3:0]; // @[AsyncQueue.scala:53:43] assign _ridx_incremented_T_2 = _ridx_T_2 ? 4'h0 : _ridx_incremented_T_1; // @[AsyncQueue.scala:52:25, :53:{23,43}, :148:77] assign ridx_incremented = _ridx_incremented_T_2; // @[AsyncQueue.scala:51:27, :53:23] wire [2:0] _ridx_T_3 = ridx_incremented[3:1]; // @[AsyncQueue.scala:51:27, :54:32] wire [3:0] ridx = {ridx_incremented[3], ridx_incremented[2:0] ^ _ridx_T_3}; // @[AsyncQueue.scala:51:27, :54:{17,32}] wire [3:0] widx; // @[ShiftReg.scala:48:24] wire _valid_T = ridx != widx; // @[ShiftReg.scala:48:24] wire valid = source_ready & _valid_T; // @[AsyncQueue.scala:147:30, :150:{28,36}] wire [2:0] _index_T = ridx[2:0]; // @[AsyncQueue.scala:54:17, :156:43] wire _index_T_1 = ridx[3]; // @[AsyncQueue.scala:54:17, :156:62] wire [2:0] _index_T_2 = {_index_T_1, 2'h0}; // @[AsyncQueue.scala:156:{62,75}] wire [2:0] index = _index_T ^ _index_T_2; // @[AsyncQueue.scala:156:{43,55,75}] wire [7:0][2:0] _GEN = {{io_async_mem_7_opcode_0}, {io_async_mem_6_opcode_0}, {io_async_mem_5_opcode_0}, {io_async_mem_4_opcode_0}, {io_async_mem_3_opcode_0}, {io_async_mem_2_opcode_0}, {io_async_mem_1_opcode_0}, {io_async_mem_0_opcode_0}}; // @[SynchronizerReg.scala:209:24] wire [7:0][2:0] _GEN_0 = {{io_async_mem_7_param_0}, {io_async_mem_6_param_0}, {io_async_mem_5_param_0}, {io_async_mem_4_param_0}, {io_async_mem_3_param_0}, {io_async_mem_2_param_0}, {io_async_mem_1_param_0}, {io_async_mem_0_param_0}}; // @[SynchronizerReg.scala:209:24] wire [7:0][3:0] _GEN_1 = {{io_async_mem_7_size_0}, {io_async_mem_6_size_0}, {io_async_mem_5_size_0}, {io_async_mem_4_size_0}, {io_async_mem_3_size_0}, {io_async_mem_2_size_0}, {io_async_mem_1_size_0}, {io_async_mem_0_size_0}}; // @[SynchronizerReg.scala:209:24] wire [7:0][1:0] _GEN_2 = {{io_async_mem_7_source_0}, {io_async_mem_6_source_0}, {io_async_mem_5_source_0}, {io_async_mem_4_source_0}, {io_async_mem_3_source_0}, {io_async_mem_2_source_0}, {io_async_mem_1_source_0}, {io_async_mem_0_source_0}}; // @[SynchronizerReg.scala:209:24] wire [7:0][31:0] _GEN_3 = {{io_async_mem_7_address_0}, {io_async_mem_6_address_0}, {io_async_mem_5_address_0}, {io_async_mem_4_address_0}, {io_async_mem_3_address_0}, {io_async_mem_2_address_0}, {io_async_mem_1_address_0}, {io_async_mem_0_address_0}}; // @[SynchronizerReg.scala:209:24] wire [7:0][7:0] _GEN_4 = {{io_async_mem_7_mask_0}, {io_async_mem_6_mask_0}, {io_async_mem_5_mask_0}, {io_async_mem_4_mask_0}, {io_async_mem_3_mask_0}, {io_async_mem_2_mask_0}, {io_async_mem_1_mask_0}, {io_async_mem_0_mask_0}}; // @[SynchronizerReg.scala:209:24] wire [7:0] io_deq_bits_deq_bits_reg_io_d_lo_hi = _GEN_4[index]; // @[SynchronizerReg.scala:209:24] wire [7:0][63:0] _GEN_5 = {{io_async_mem_7_data_0}, {io_async_mem_6_data_0}, {io_async_mem_5_data_0}, {io_async_mem_4_data_0}, {io_async_mem_3_data_0}, {io_async_mem_2_data_0}, {io_async_mem_1_data_0}, {io_async_mem_0_data_0}}; // @[SynchronizerReg.scala:209:24] wire [64:0] io_deq_bits_deq_bits_reg_io_d_lo_lo = {_GEN_5[index], 1'h0}; // @[SynchronizerReg.scala:209:24] wire [72:0] io_deq_bits_deq_bits_reg_io_d_lo = {io_deq_bits_deq_bits_reg_io_d_lo_hi, io_deq_bits_deq_bits_reg_io_d_lo_lo}; // @[SynchronizerReg.scala:209:24] wire [33:0] io_deq_bits_deq_bits_reg_io_d_hi_lo = {_GEN_2[index], _GEN_3[index]}; // @[SynchronizerReg.scala:209:24] wire [5:0] io_deq_bits_deq_bits_reg_io_d_hi_hi_hi = {_GEN[index], _GEN_0[index]}; // @[SynchronizerReg.scala:209:24] wire [9:0] io_deq_bits_deq_bits_reg_io_d_hi_hi = {io_deq_bits_deq_bits_reg_io_d_hi_hi_hi, _GEN_1[index]}; // @[SynchronizerReg.scala:209:24] wire [43:0] io_deq_bits_deq_bits_reg_io_d_hi = {io_deq_bits_deq_bits_reg_io_d_hi_hi, io_deq_bits_deq_bits_reg_io_d_hi_lo}; // @[SynchronizerReg.scala:209:24] wire [116:0] _io_deq_bits_deq_bits_reg_io_d_T = {io_deq_bits_deq_bits_reg_io_d_hi, io_deq_bits_deq_bits_reg_io_d_lo}; // @[SynchronizerReg.scala:209:24] wire [2:0] _io_deq_bits_T_7; // @[SynchronizerReg.scala:211:26] assign io_deq_bits_opcode_0 = _io_deq_bits_WIRE_opcode; // @[SynchronizerReg.scala:211:26] wire [2:0] _io_deq_bits_T_6; // @[SynchronizerReg.scala:211:26] assign io_deq_bits_param_0 = _io_deq_bits_WIRE_param; // @[SynchronizerReg.scala:211:26] wire [3:0] _io_deq_bits_T_5; // @[SynchronizerReg.scala:211:26] assign io_deq_bits_size_0 = _io_deq_bits_WIRE_size; // @[SynchronizerReg.scala:211:26] wire [1:0] _io_deq_bits_T_4; // @[SynchronizerReg.scala:211:26] assign io_deq_bits_source_0 = _io_deq_bits_WIRE_source; // @[SynchronizerReg.scala:211:26] wire [31:0] _io_deq_bits_T_3; // @[SynchronizerReg.scala:211:26] assign io_deq_bits_address_0 = _io_deq_bits_WIRE_address; // @[SynchronizerReg.scala:211:26] wire [7:0] _io_deq_bits_T_2; // @[SynchronizerReg.scala:211:26] assign io_deq_bits_mask_0 = _io_deq_bits_WIRE_mask; // @[SynchronizerReg.scala:211:26] wire [63:0] _io_deq_bits_T_1; // @[SynchronizerReg.scala:211:26] assign io_deq_bits_data_0 = _io_deq_bits_WIRE_data; // @[SynchronizerReg.scala:211:26] wire _io_deq_bits_T; // @[SynchronizerReg.scala:211:26] assign io_deq_bits_corrupt_0 = _io_deq_bits_WIRE_corrupt; // @[SynchronizerReg.scala:211:26] wire [116:0] _io_deq_bits_WIRE_1; // @[SynchronizerReg.scala:211:26] assign _io_deq_bits_T = _io_deq_bits_WIRE_1[0]; // @[SynchronizerReg.scala:211:26] assign _io_deq_bits_WIRE_corrupt = _io_deq_bits_T; // @[SynchronizerReg.scala:211:26] assign _io_deq_bits_T_1 = _io_deq_bits_WIRE_1[64:1]; // @[SynchronizerReg.scala:211:26] assign _io_deq_bits_WIRE_data = _io_deq_bits_T_1; // @[SynchronizerReg.scala:211:26] assign _io_deq_bits_T_2 = _io_deq_bits_WIRE_1[72:65]; // @[SynchronizerReg.scala:211:26] assign _io_deq_bits_WIRE_mask = _io_deq_bits_T_2; // @[SynchronizerReg.scala:211:26] assign _io_deq_bits_T_3 = _io_deq_bits_WIRE_1[104:73]; // @[SynchronizerReg.scala:211:26] assign _io_deq_bits_WIRE_address = _io_deq_bits_T_3; // @[SynchronizerReg.scala:211:26] assign _io_deq_bits_T_4 = _io_deq_bits_WIRE_1[106:105]; // @[SynchronizerReg.scala:211:26] assign _io_deq_bits_WIRE_source = _io_deq_bits_T_4; // @[SynchronizerReg.scala:211:26] assign _io_deq_bits_T_5 = _io_deq_bits_WIRE_1[110:107]; // @[SynchronizerReg.scala:211:26] assign _io_deq_bits_WIRE_size = _io_deq_bits_T_5; // @[SynchronizerReg.scala:211:26] assign _io_deq_bits_T_6 = _io_deq_bits_WIRE_1[113:111]; // @[SynchronizerReg.scala:211:26] assign _io_deq_bits_WIRE_param = _io_deq_bits_T_6; // @[SynchronizerReg.scala:211:26] assign _io_deq_bits_T_7 = _io_deq_bits_WIRE_1[116:114]; // @[SynchronizerReg.scala:211:26] assign _io_deq_bits_WIRE_opcode = _io_deq_bits_T_7; // @[SynchronizerReg.scala:211:26] reg valid_reg; // @[AsyncQueue.scala:165:56] assign _io_deq_valid_T = valid_reg & source_ready; // @[AsyncQueue.scala:147:30, :165:56, :166:29] assign io_deq_valid_0 = _io_deq_valid_T; // @[AsyncQueue.scala:136:7, :166:29] reg [3:0] ridx_gray; // @[AsyncQueue.scala:168:55] assign io_async_ridx_0 = ridx_gray; // @[AsyncQueue.scala:136:7, :168:55] wire _sink_valid_0_reset_T_1 = ~io_async_safe_source_reset_n_0; // @[AsyncQueue.scala:136:7, :177:45] wire _sink_valid_0_reset_T_2 = _sink_valid_0_reset_T | _sink_valid_0_reset_T_1; // @[AsyncQueue.scala:177:{35,42,45}] wire _sink_valid_0_reset_T_3 = _sink_valid_0_reset_T_2; // @[AsyncQueue.scala:177:{42,66}] wire _sink_valid_1_reset_T_1 = ~io_async_safe_source_reset_n_0; // @[AsyncQueue.scala:136:7, :177:45, :178:45] wire _sink_valid_1_reset_T_2 = _sink_valid_1_reset_T | _sink_valid_1_reset_T_1; // @[AsyncQueue.scala:178:{35,42,45}] wire _sink_valid_1_reset_T_3 = _sink_valid_1_reset_T_2; // @[AsyncQueue.scala:178:{42,66}] wire _source_extend_reset_T_1 = ~io_async_safe_source_reset_n_0; // @[AsyncQueue.scala:136:7, :177:45, :179:45] wire _source_extend_reset_T_2 = _source_extend_reset_T | _source_extend_reset_T_1; // @[AsyncQueue.scala:179:{35,42,45}] wire _source_extend_reset_T_3 = _source_extend_reset_T_2; // @[AsyncQueue.scala:179:{42,66}] assign _io_async_safe_sink_reset_n_T_1 = ~_io_async_safe_sink_reset_n_T; // @[AsyncQueue.scala:193:{25,32}] assign io_async_safe_sink_reset_n_0 = _io_async_safe_sink_reset_n_T_1; // @[AsyncQueue.scala:136:7, :193:25] always @(posedge clock or posedge _ridx_T) begin // @[AsyncQueue.scala:136:7, :148:30] if (_ridx_T) // @[AsyncQueue.scala:136:7, :148:30] ridx_ridx_bin <= 4'h0; // @[AsyncQueue.scala:52:25] else // @[AsyncQueue.scala:136:7] ridx_ridx_bin <= ridx_incremented; // @[AsyncQueue.scala:51:27, :52:25] always @(posedge, posedge) always @(posedge clock or posedge _valid_reg_T) begin // @[AsyncQueue.scala:136:7, :165:35] if (_valid_reg_T) // @[AsyncQueue.scala:136:7, :165:35] valid_reg <= 1'h0; // @[AsyncQueue.scala:165:56] else // @[AsyncQueue.scala:136:7] valid_reg <= valid; // @[AsyncQueue.scala:150:28, :165:56] always @(posedge, posedge) always @(posedge clock or posedge _ridx_reg_T) begin // @[AsyncQueue.scala:136:7, :168:34] if (_ridx_reg_T) // @[AsyncQueue.scala:136:7, :168:34] ridx_gray <= 4'h0; // @[AsyncQueue.scala:52:25, :168:55] else // @[AsyncQueue.scala:136:7] ridx_gray <= ridx; // @[AsyncQueue.scala:54:17, :168:55] always @(posedge, posedge)

Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: package constellation.channel import chisel3._ import chisel3.util._ import freechips.rocketchip.diplomacy._ import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.util._ import constellation.noc.{HasNoCParams} class NoCMonitor(val cParam: ChannelParams)(implicit val p: Parameters) extends Module with HasNoCParams { val io = IO(new Bundle { val in = Input(new Channel(cParam)) }) val in_flight = RegInit(VecInit(Seq.fill(cParam.nVirtualChannels) { false.B })) for (i <- 0 until cParam.srcSpeedup) { val flit = io.in.flit(i) when (flit.valid) { when (flit.bits.head) { in_flight(flit.bits.virt_channel_id) := true.B assert (!in_flight(flit.bits.virt_channel_id), "Flit head/tail sequencing is broken") } when (flit.bits.tail) { in_flight(flit.bits.virt_channel_id) := false.B } } val possibleFlows = cParam.possibleFlows when (flit.valid && flit.bits.head) { cParam match { case n: ChannelParams => n.virtualChannelParams.zipWithIndex.foreach { case (v,i) => assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR) } case _ => assert(cParam.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR) } } } } File Types.scala: package constellation.routing import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Parameters} import constellation.noc.{HasNoCParams} import constellation.channel.{Flit} /** A representation for 1 specific virtual channel in wormhole routing * * @param src the source node * @param vc ID for the virtual channel * @param dst the destination node * @param n_vc the number of virtual channels */ // BEGIN: ChannelRoutingInfo case class ChannelRoutingInfo( src: Int, dst: Int, vc: Int, n_vc: Int ) { // END: ChannelRoutingInfo require (src >= -1 && dst >= -1 && vc >= 0, s"Illegal $this") require (!(src == -1 && dst == -1), s"Illegal $this") require (vc < n_vc, s"Illegal $this") val isIngress = src == -1 val isEgress = dst == -1 } /** Represents the properties of a packet that are relevant for routing * ingressId and egressId uniquely identify a flow, but vnet and dst are used here * to simplify the implementation of routingrelations * * @param ingressId packet's source ingress point * @param egressId packet's destination egress point * @param vNet virtual subnetwork identifier * @param dst packet's destination node ID */ // BEGIN: FlowRoutingInfo case class FlowRoutingInfo( ingressId: Int, egressId: Int, vNetId: Int, ingressNode: Int, ingressNodeId: Int, egressNode: Int, egressNodeId: Int, fifo: Boolean ) { // END: FlowRoutingInfo def isFlow(f: FlowRoutingBundle): Bool = { (f.ingress_node === ingressNode.U && f.egress_node === egressNode.U && f.ingress_node_id === ingressNodeId.U && f.egress_node_id === egressNodeId.U) } def asLiteral(b: FlowRoutingBundle): BigInt = { Seq( (vNetId , b.vnet_id), (ingressNode , b.ingress_node), (ingressNodeId , b.ingress_node_id), (egressNode , b.egress_node), (egressNodeId , b.egress_node_id) ).foldLeft(0)((l, t) => { (l << t._2.getWidth) | t._1 }) } } class FlowRoutingBundle(implicit val p: Parameters) extends Bundle with HasNoCParams { // Instead of tracking ingress/egress ID, track the physical destination id and the offset at the destination // This simplifies the routing tables val vnet_id = UInt(log2Ceil(nVirtualNetworks).W) val ingress_node = UInt(log2Ceil(nNodes).W) val ingress_node_id = UInt(log2Ceil(maxIngressesAtNode).W) val egress_node = UInt(log2Ceil(nNodes).W) val egress_node_id = UInt(log2Ceil(maxEgressesAtNode).W) }

module NoCMonitor_83( // @[Monitor.scala:11:7] input clock, // @[Monitor.scala:11:7] input reset, // @[Monitor.scala:11:7] input io_in_flit_0_valid, // @[Monitor.scala:12:14] input io_in_flit_0_bits_head, // @[Monitor.scala:12:14] input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14] input io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14] ); reg in_flight_0; // @[Monitor.scala:16:26] reg in_flight_1; // @[Monitor.scala:16:26]

Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module TLMonitor( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [15:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [127:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [127:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [15:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [127:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [127:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [7:0] c_first_beats1_decode = 8'h0; // @[Edges.scala:220:59] wire [7:0] c_first_beats1 = 8'h0; // @[Edges.scala:221:14] wire [7:0] _c_first_count_T = 8'h0; // @[Edges.scala:234:27] wire [7:0] c_first_count = 8'h0; // @[Edges.scala:234:25] wire [7:0] _c_first_counter_T = 8'h0; // @[Edges.scala:236:21] wire [7:0] _c_opcodes_set_T = 8'h0; // @[Monitor.scala:767:79] wire [7:0] _c_sizes_set_T = 8'h0; // @[Monitor.scala:768:77] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_31 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_37 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_43 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_49 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:57:20] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [7:0] c_first_counter1 = 8'hFF; // @[Edges.scala:230:28] wire [8:0] _c_first_counter1_T = 9'h1FF; // @[Edges.scala:230:28] wire [127:0] _c_first_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_first_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_first_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_first_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_set_wo_ready_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_set_wo_ready_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_opcodes_set_interm_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_opcodes_set_interm_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_sizes_set_interm_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_sizes_set_interm_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_opcodes_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_opcodes_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_sizes_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_sizes_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_probe_ack_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_probe_ack_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_probe_ack_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_probe_ack_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_4_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_5_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_set_wo_ready_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_wo_ready_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_opcodes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [4:0] _c_opcodes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_4_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_5_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [259:0] _c_sizes_set_T_1 = 260'h0; // @[Monitor.scala:768:52] wire [258:0] _c_opcodes_set_T_1 = 259'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [31:0] _c_set_wo_ready_T = 32'h1; // @[OneHot.scala:58:35] wire [31:0] _c_set_T = 32'h1; // @[OneHot.scala:58:35] wire [135:0] c_sizes_set = 136'h0; // @[Monitor.scala:741:34] wire [67:0] c_opcodes_set = 68'h0; // @[Monitor.scala:740:34] wire [16:0] c_set = 17'h0; // @[Monitor.scala:738:34] wire [16:0] c_set_wo_ready = 17'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [4:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 5'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _source_ok_T_1 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_7 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_13 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_19 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 3'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 3'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 3'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 3'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_26 = _source_ok_T_25 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_27 = _source_ok_T_26 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_27 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire [3:0] mask_sizeOH = {_mask_sizeOH_T_2[3:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_sub_0_1 = |(io_in_a_bits_size_0[3:2]); // @[Misc.scala:206:21] wire mask_sub_sub_sub_size = mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_sub_bit = io_in_a_bits_address_0[3]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_1_2 = mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_nbit = ~mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_0_2 = mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_acc_T = mask_sub_sub_sub_size & mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_size & mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_1_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_2_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size & mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_2_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_3_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size & mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_3_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_4_2 = mask_sub_sub_2_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_4 = mask_sub_size & mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_4_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_5_2 = mask_sub_sub_2_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_5 = mask_sub_size & mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_5_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_6_2 = mask_sub_sub_3_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_6 = mask_sub_size & mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_6_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_7_2 = mask_sub_sub_3_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_7 = mask_sub_size & mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_7_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_eq_8 = mask_sub_4_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_size & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_8 = mask_sub_4_1 | _mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_eq_9 = mask_sub_4_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_size & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_9 = mask_sub_4_1 | _mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_eq_10 = mask_sub_5_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_size & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_10 = mask_sub_5_1 | _mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_eq_11 = mask_sub_5_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_size & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_11 = mask_sub_5_1 | _mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_eq_12 = mask_sub_6_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_size & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_12 = mask_sub_6_1 | _mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_eq_13 = mask_sub_6_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_size & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_13 = mask_sub_6_1 | _mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_eq_14 = mask_sub_7_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_size & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_14 = mask_sub_7_1 | _mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_eq_15 = mask_sub_7_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_size & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_15 = mask_sub_7_1 | _mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_lo = {mask_lo_lo_hi, mask_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_hi = {mask_lo_hi_hi, mask_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_lo_hi = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_lo = {mask_hi_lo_hi, mask_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_hi = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_hi = {mask_hi_hi_hi, mask_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [15:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_28 = io_in_d_bits_source_0 == 5'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_28; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _source_ok_T_29 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_35 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_41 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_47 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire _source_ok_T_30 = _source_ok_T_29 == 3'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_32 = _source_ok_T_30; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_34; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_36 = _source_ok_T_35 == 3'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_38 = _source_ok_T_36; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_40; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_42 = _source_ok_T_41 == 3'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_44 = _source_ok_T_42; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_46; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_48 = _source_ok_T_47 == 3'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_50 = _source_ok_T_48; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_52; // @[Parameters.scala:1138:31] wire _source_ok_T_53 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_54 = _source_ok_T_53 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_55 = _source_ok_T_54 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_55 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _T_1502 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1502; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1502; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [7:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [7:0] a_first_counter; // @[Edges.scala:229:27] wire [8:0] _a_first_counter1_T = {1'h0, a_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] a_first_counter1 = _a_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [7:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [4:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1575 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1575; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1575; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1575; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [7:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T = {1'h0, d_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1 = _d_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [4:0] source_1; // @[Monitor.scala:541:22] reg [6:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [16:0] inflight; // @[Monitor.scala:614:27] reg [67:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [135:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [7:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [7:0] a_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] a_first_counter1_1 = _a_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [7:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_1 = _d_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [16:0] a_set; // @[Monitor.scala:626:34] wire [16:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [67:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [135:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [7:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [7:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [7:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [7:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [7:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [67:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [67:0] _a_opcode_lookup_T_6 = {64'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [67:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[67:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [7:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [7:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [7:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [7:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [7:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [135:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [135:0] _a_size_lookup_T_6 = {128'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [135:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[135:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [31:0] _GEN_3 = 32'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [31:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [31:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[16:0] : 17'h0; // @[OneHot.scala:58:35] wire _T_1428 = _T_1502 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1428 ? _a_set_T[16:0] : 17'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1428 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1428 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [7:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [258:0] _a_opcodes_set_T_1 = {255'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1428 ? _a_opcodes_set_T_1[67:0] : 68'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [7:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [259:0] _a_sizes_set_T_1 = {255'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1428 ? _a_sizes_set_T_1[135:0] : 136'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [16:0] d_clr; // @[Monitor.scala:664:34] wire [16:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [67:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [135:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1474 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [31:0] _GEN_5 = 32'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1474 & ~d_release_ack ? _d_clr_wo_ready_T[16:0] : 17'h0; // @[OneHot.scala:58:35] wire _T_1443 = _T_1575 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1443 ? _d_clr_T[16:0] : 17'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_5 = 271'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1443 ? _d_opcodes_clr_T_5[67:0] : 68'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [270:0] _d_sizes_clr_T_5 = 271'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1443 ? _d_sizes_clr_T_5[135:0] : 136'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [16:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [16:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [16:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [67:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [67:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [67:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [135:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [135:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [135:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [16:0] inflight_1; // @[Monitor.scala:726:35] wire [16:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [67:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [67:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [135:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [135:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_2; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_2 = _d_first_counter1_T_2[7:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [67:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [67:0] _c_opcode_lookup_T_6 = {64'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [67:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[67:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [135:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [135:0] _c_size_lookup_T_6 = {128'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [135:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[135:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [16:0] d_clr_1; // @[Monitor.scala:774:34] wire [16:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [67:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [135:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1546 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1546 & d_release_ack_1 ? _d_clr_wo_ready_T_1[16:0] : 17'h0; // @[OneHot.scala:58:35] wire _T_1528 = _T_1575 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1528 ? _d_clr_T_1[16:0] : 17'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_11 = 271'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1528 ? _d_opcodes_clr_T_11[67:0] : 68'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [270:0] _d_sizes_clr_T_11 = 271'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1528 ? _d_sizes_clr_T_11[135:0] : 136'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 5'h0; // @[Monitor.scala:36:7, :795:113] wire [16:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [16:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [67:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [67:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [135:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [135:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands */ class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def *(t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def *(t: UInt) = self * t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros | ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def *(t: SInt) = self * t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros | ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid || output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def *(t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def *(t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }

module MacUnit_56( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [19:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54] assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Serdes.scala: package testchipip.serdes import chisel3._ import chisel3.util._ import freechips.rocketchip.diplomacy._ import org.chipsalliance.cde.config._ class GenericSerializer[T <: Data](t: T, flitWidth: Int) extends Module { override def desiredName = s"GenericSerializer_${t.typeName}w${t.getWidth}_f${flitWidth}" val io = IO(new Bundle { val in = Flipped(Decoupled(t)) val out = Decoupled(new Flit(flitWidth)) val busy = Output(Bool()) }) val dataBits = t.getWidth.max(flitWidth) val dataBeats = (dataBits - 1) / flitWidth + 1 require(dataBeats >= 1) val data = Reg(Vec(dataBeats, UInt(flitWidth.W))) val beat = RegInit(0.U(log2Ceil(dataBeats).W)) io.in.ready := io.out.ready && beat === 0.U io.out.valid := io.in.valid || beat =/= 0.U io.out.bits.flit := Mux(beat === 0.U, io.in.bits.asUInt, data(beat)) when (io.out.fire) { beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U) when (beat === 0.U) { data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(flitWidth.W))) data(0) := DontCare // unused, DCE this } } io.busy := io.out.valid } class GenericDeserializer[T <: Data](t: T, flitWidth: Int) extends Module { override def desiredName = s"GenericDeserializer_${t.typeName}w${t.getWidth}_f${flitWidth}" val io = IO(new Bundle { val in = Flipped(Decoupled(new Flit(flitWidth))) val out = Decoupled(t) val busy = Output(Bool()) }) val dataBits = t.getWidth.max(flitWidth) val dataBeats = (dataBits - 1) / flitWidth + 1 require(dataBeats >= 1) val data = Reg(Vec(dataBeats-1, UInt(flitWidth.W))) val beat = RegInit(0.U(log2Ceil(dataBeats).W)) io.in.ready := io.out.ready || beat =/= (dataBeats-1).U io.out.valid := io.in.valid && beat === (dataBeats-1).U io.out.bits := (if (dataBeats == 1) { io.in.bits.flit.asTypeOf(t) } else { Cat(io.in.bits.flit, data.asUInt).asTypeOf(t) }) when (io.in.fire) { beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U) if (dataBeats > 1) { when (beat =/= (dataBeats-1).U) { data(beat(log2Ceil(dataBeats-1)-1,0)) := io.in.bits.flit } } } io.busy := beat =/= 0.U } class FlitToPhit(flitWidth: Int, phitWidth: Int) extends Module { override def desiredName = s"FlitToPhit_f${flitWidth}_p${phitWidth}" val io = IO(new Bundle { val in = Flipped(Decoupled(new Flit(flitWidth))) val out = Decoupled(new Phit(phitWidth)) }) require(flitWidth >= phitWidth) val dataBeats = (flitWidth - 1) / phitWidth + 1 val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W))) val beat = RegInit(0.U(log2Ceil(dataBeats).W)) io.in.ready := io.out.ready && beat === 0.U io.out.valid := io.in.valid || beat =/= 0.U io.out.bits.phit := (if (dataBeats == 1) io.in.bits.flit else Mux(beat === 0.U, io.in.bits.flit, data(beat-1.U))) when (io.out.fire) { beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U) when (beat === 0.U) { data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(phitWidth.W))).tail } } } object FlitToPhit { def apply(flit: DecoupledIO[Flit], phitWidth: Int): DecoupledIO[Phit] = { val flit2phit = Module(new FlitToPhit(flit.bits.flitWidth, phitWidth)) flit2phit.io.in <> flit flit2phit.io.out } } class PhitToFlit(flitWidth: Int, phitWidth: Int) extends Module { override def desiredName = s"PhitToFlit_p${phitWidth}_f${flitWidth}" val io = IO(new Bundle { val in = Flipped(Decoupled(new Phit(phitWidth))) val out = Decoupled(new Flit(flitWidth)) }) require(flitWidth >= phitWidth) val dataBeats = (flitWidth - 1) / phitWidth + 1 val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W))) val beat = RegInit(0.U(log2Ceil(dataBeats).W)) io.in.ready := io.out.ready || beat =/= (dataBeats-1).U io.out.valid := io.in.valid && beat === (dataBeats-1).U io.out.bits.flit := (if (dataBeats == 1) io.in.bits.phit else Cat(io.in.bits.phit, data.asUInt)) when (io.in.fire) { beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U) if (dataBeats > 1) { when (beat =/= (dataBeats-1).U) { data(beat) := io.in.bits.phit } } } } object PhitToFlit { def apply(phit: DecoupledIO[Phit], flitWidth: Int): DecoupledIO[Flit] = { val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth)) phit2flit.io.in <> phit phit2flit.io.out } def apply(phit: ValidIO[Phit], flitWidth: Int): ValidIO[Flit] = { val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth)) phit2flit.io.in.valid := phit.valid phit2flit.io.in.bits := phit.bits when (phit.valid) { assert(phit2flit.io.in.ready) } val out = Wire(Valid(new Flit(flitWidth))) out.valid := phit2flit.io.out.valid out.bits := phit2flit.io.out.bits phit2flit.io.out.ready := true.B out } } class PhitArbiter(phitWidth: Int, flitWidth: Int, channels: Int) extends Module { override def desiredName = s"PhitArbiter_p${phitWidth}_f${flitWidth}_n${channels}" val io = IO(new Bundle { val in = Flipped(Vec(channels, Decoupled(new Phit(phitWidth)))) val out = Decoupled(new Phit(phitWidth)) }) if (channels == 1) { io.out <> io.in(0) } else { val headerWidth = log2Ceil(channels) val headerBeats = (headerWidth - 1) / phitWidth + 1 val flitBeats = (flitWidth - 1) / phitWidth + 1 val beats = headerBeats + flitBeats val beat = RegInit(0.U(log2Ceil(beats).W)) val chosen_reg = Reg(UInt(headerWidth.W)) val chosen_prio = PriorityEncoder(io.in.map(_.valid)) val chosen = Mux(beat === 0.U, chosen_prio, chosen_reg) val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0) io.out.valid := VecInit(io.in.map(_.valid))(chosen) io.out.bits.phit := Mux(beat < headerBeats.U, chosen.asTypeOf(Vec(headerBeats, UInt(phitWidth.W)))(header_idx), VecInit(io.in.map(_.bits.phit))(chosen)) for (i <- 0 until channels) { io.in(i).ready := io.out.ready && beat >= headerBeats.U && chosen_reg === i.U } when (io.out.fire) { beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U) when (beat === 0.U) { chosen_reg := chosen_prio } } } } class PhitDemux(phitWidth: Int, flitWidth: Int, channels: Int) extends Module { override def desiredName = s"PhitDemux_p${phitWidth}_f${flitWidth}_n${channels}" val io = IO(new Bundle { val in = Flipped(Decoupled(new Phit(phitWidth))) val out = Vec(channels, Decoupled(new Phit(phitWidth))) }) if (channels == 1) { io.out(0) <> io.in } else { val headerWidth = log2Ceil(channels) val headerBeats = (headerWidth - 1) / phitWidth + 1 val flitBeats = (flitWidth - 1) / phitWidth + 1 val beats = headerBeats + flitBeats val beat = RegInit(0.U(log2Ceil(beats).W)) val channel_vec = Reg(Vec(headerBeats, UInt(phitWidth.W))) val channel = channel_vec.asUInt(log2Ceil(channels)-1,0) val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0) io.in.ready := beat < headerBeats.U || VecInit(io.out.map(_.ready))(channel) for (c <- 0 until channels) { io.out(c).valid := io.in.valid && beat >= headerBeats.U && channel === c.U io.out(c).bits.phit := io.in.bits.phit } when (io.in.fire) { beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U) when (beat < headerBeats.U) { channel_vec(header_idx) := io.in.bits.phit } } } } class DecoupledFlitToCreditedFlit(flitWidth: Int, bufferSz: Int) extends Module { override def desiredName = s"DecoupledFlitToCreditedFlit_f${flitWidth}_b${bufferSz}" val io = IO(new Bundle { val in = Flipped(Decoupled(new Flit(flitWidth))) val out = Decoupled(new Flit(flitWidth)) val credit = Flipped(Decoupled(new Flit(flitWidth))) }) val creditWidth = log2Ceil(bufferSz) require(creditWidth <= flitWidth) val credits = RegInit(0.U((creditWidth+1).W)) val credit_incr = io.out.fire val credit_decr = io.credit.fire when (credit_incr || credit_decr) { credits := credits + credit_incr - Mux(io.credit.valid, io.credit.bits.flit +& 1.U, 0.U) } io.out.valid := io.in.valid && credits < bufferSz.U io.out.bits.flit := io.in.bits.flit io.in.ready := io.out.ready && credits < bufferSz.U io.credit.ready := true.B } class CreditedFlitToDecoupledFlit(flitWidth: Int, bufferSz: Int) extends Module { override def desiredName = s"CreditedFlitToDecoupledFlit_f${flitWidth}_b${bufferSz}" val io = IO(new Bundle { val in = Flipped(Decoupled(new Flit(flitWidth))) val out = Decoupled(new Flit(flitWidth)) val credit = Decoupled(new Flit(flitWidth)) }) val creditWidth = log2Ceil(bufferSz) require(creditWidth <= flitWidth) val buffer = Module(new Queue(new Flit(flitWidth), bufferSz)) val credits = RegInit(0.U((creditWidth+1).W)) val credit_incr = buffer.io.deq.fire val credit_decr = io.credit.fire when (credit_incr || credit_decr) { credits := credit_incr + Mux(credit_decr, 0.U, credits) } buffer.io.enq.valid := io.in.valid buffer.io.enq.bits := io.in.bits io.in.ready := true.B when (io.in.valid) { assert(buffer.io.enq.ready) } io.out <> buffer.io.deq io.credit.valid := credits =/= 0.U io.credit.bits.flit := credits - 1.U }

module FlitToPhit_f32_p32_6( // @[Serdes.scala:71:7] input clock, // @[Serdes.scala:71:7] input reset, // @[Serdes.scala:71:7] output io_in_ready, // @[Serdes.scala:73:14] input io_in_valid, // @[Serdes.scala:73:14] input [31:0] io_in_bits_flit, // @[Serdes.scala:73:14] input io_out_ready, // @[Serdes.scala:73:14] output io_out_valid, // @[Serdes.scala:73:14] output [31:0] io_out_bits_phit // @[Serdes.scala:73:14] ); wire io_in_valid_0 = io_in_valid; // @[Serdes.scala:71:7] wire [31:0] io_in_bits_flit_0 = io_in_bits_flit; // @[Serdes.scala:71:7] wire io_out_ready_0 = io_out_ready; // @[Serdes.scala:71:7] wire [1:0] _beat_T_1 = 2'h1; // @[Serdes.scala:88:53] wire _io_in_ready_T = 1'h1; // @[Serdes.scala:83:39] wire _beat_T = 1'h1; // @[Serdes.scala:88:22] wire _beat_T_2 = 1'h1; // @[Serdes.scala:88:53] wire _io_in_ready_T_1; // @[Serdes.scala:83:31] wire _io_out_valid_T = 1'h0; // @[Serdes.scala:84:39] wire _beat_T_3 = 1'h0; // @[Serdes.scala:88:16] wire _io_out_valid_T_1 = io_in_valid_0; // @[Serdes.scala:71:7, :84:31] wire [31:0] io_out_bits_phit_0 = io_in_bits_flit_0; // @[Serdes.scala:71:7] assign _io_in_ready_T_1 = io_out_ready_0; // @[Serdes.scala:71:7, :83:31] wire io_in_ready_0; // @[Serdes.scala:71:7] wire io_out_valid_0; // @[Serdes.scala:71:7] assign io_in_ready_0 = _io_in_ready_T_1; // @[Serdes.scala:71:7, :83:31] assign io_out_valid_0 = _io_out_valid_T_1; // @[Serdes.scala:71:7, :84:31] assign io_in_ready = io_in_ready_0; // @[Serdes.scala:71:7] assign io_out_valid = io_out_valid_0; // @[Serdes.scala:71:7] assign io_out_bits_phit = io_out_bits_phit_0; // @[Serdes.scala:71:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }

module AsyncResetSynchronizerShiftReg_w1_d3_i0_115( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_191 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File ShiftQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ /** Implements the same interface as chisel3.util.Queue, but uses a shift * register internally. It is less energy efficient whenever the queue * has more than one entry populated, but is faster on the dequeue side. * It is efficient for usually-empty flow-through queues. */ class ShiftQueue[T <: Data](gen: T, val entries: Int, pipe: Boolean = false, flow: Boolean = false) extends Module { val io = IO(new QueueIO(gen, entries) { val mask = Output(UInt(entries.W)) }) private val valid = RegInit(VecInit(Seq.fill(entries) { false.B })) private val elts = Reg(Vec(entries, gen)) for (i <- 0 until entries) { def paddedValid(i: Int) = if (i == -1) true.B else if (i == entries) false.B else valid(i) val wdata = if (i == entries-1) io.enq.bits else Mux(valid(i+1), elts(i+1), io.enq.bits) val wen = Mux(io.deq.ready, paddedValid(i+1) || io.enq.fire && ((i == 0 && !flow).B || valid(i)), io.enq.fire && paddedValid(i-1) && !valid(i)) when (wen) { elts(i) := wdata } valid(i) := Mux(io.deq.ready, paddedValid(i+1) || io.enq.fire && ((i == 0 && !flow).B || valid(i)), io.enq.fire && paddedValid(i-1) || valid(i)) } io.enq.ready := !valid(entries-1) io.deq.valid := valid(0) io.deq.bits := elts.head if (flow) { when (io.enq.valid) { io.deq.valid := true.B } when (!valid(0)) { io.deq.bits := io.enq.bits } } if (pipe) { when (io.deq.ready) { io.enq.ready := true.B } } io.mask := valid.asUInt io.count := PopCount(io.mask) } object ShiftQueue { def apply[T <: Data](enq: DecoupledIO[T], entries: Int = 2, pipe: Boolean = false, flow: Boolean = false): DecoupledIO[T] = { val q = Module(new ShiftQueue(enq.bits.cloneType, entries, pipe, flow)) q.io.enq <> enq q.io.deq } }

module ShiftQueue( // @[ShiftQueue.scala:12:7] input clock, // @[ShiftQueue.scala:12:7] input reset, // @[ShiftQueue.scala:12:7] output io_enq_ready, // @[ShiftQueue.scala:17:14] input io_enq_valid, // @[ShiftQueue.scala:17:14] input [1:0] io_enq_bits_btb_cfiType, // @[ShiftQueue.scala:17:14] input [1:0] io_enq_bits_btb_mask, // @[ShiftQueue.scala:17:14] input io_enq_bits_btb_bridx, // @[ShiftQueue.scala:17:14] input [31:0] io_enq_bits_btb_target, // @[ShiftQueue.scala:17:14] input io_enq_bits_btb_entry, // @[ShiftQueue.scala:17:14] input [7:0] io_enq_bits_btb_bht_history, // @[ShiftQueue.scala:17:14] input io_enq_bits_btb_bht_value, // @[ShiftQueue.scala:17:14] input [31:0] io_enq_bits_pc, // @[ShiftQueue.scala:17:14] input [31:0] io_enq_bits_data, // @[ShiftQueue.scala:17:14] input [1:0] io_enq_bits_mask, // @[ShiftQueue.scala:17:14] input io_enq_bits_xcpt_pf_inst, // @[ShiftQueue.scala:17:14] input io_enq_bits_xcpt_ae_inst, // @[ShiftQueue.scala:17:14] input io_enq_bits_replay, // @[ShiftQueue.scala:17:14] input io_deq_ready, // @[ShiftQueue.scala:17:14] output io_deq_valid, // @[ShiftQueue.scala:17:14] output [1:0] io_deq_bits_btb_cfiType, // @[ShiftQueue.scala:17:14] output io_deq_bits_btb_taken, // @[ShiftQueue.scala:17:14] output [1:0] io_deq_bits_btb_mask, // @[ShiftQueue.scala:17:14] output io_deq_bits_btb_bridx, // @[ShiftQueue.scala:17:14] output [31:0] io_deq_bits_btb_target, // @[ShiftQueue.scala:17:14] output io_deq_bits_btb_entry, // @[ShiftQueue.scala:17:14] output [7:0] io_deq_bits_btb_bht_history, // @[ShiftQueue.scala:17:14] output io_deq_bits_btb_bht_value, // @[ShiftQueue.scala:17:14] output [31:0] io_deq_bits_pc, // @[ShiftQueue.scala:17:14] output [31:0] io_deq_bits_data, // @[ShiftQueue.scala:17:14] output [1:0] io_deq_bits_mask, // @[ShiftQueue.scala:17:14] output io_deq_bits_xcpt_pf_inst, // @[ShiftQueue.scala:17:14] output io_deq_bits_xcpt_gf_inst, // @[ShiftQueue.scala:17:14] output io_deq_bits_xcpt_ae_inst, // @[ShiftQueue.scala:17:14] output io_deq_bits_replay, // @[ShiftQueue.scala:17:14] output [4:0] io_mask // @[ShiftQueue.scala:17:14] ); wire io_enq_valid_0 = io_enq_valid; // @[ShiftQueue.scala:12:7] wire [1:0] io_enq_bits_btb_cfiType_0 = io_enq_bits_btb_cfiType; // @[ShiftQueue.scala:12:7] wire [1:0] io_enq_bits_btb_mask_0 = io_enq_bits_btb_mask; // @[ShiftQueue.scala:12:7] wire io_enq_bits_btb_bridx_0 = io_enq_bits_btb_bridx; // @[ShiftQueue.scala:12:7] wire [31:0] io_enq_bits_btb_target_0 = io_enq_bits_btb_target; // @[ShiftQueue.scala:12:7] wire io_enq_bits_btb_entry_0 = io_enq_bits_btb_entry; // @[ShiftQueue.scala:12:7] wire [7:0] io_enq_bits_btb_bht_history_0 = io_enq_bits_btb_bht_history; // @[ShiftQueue.scala:12:7] wire io_enq_bits_btb_bht_value_0 = io_enq_bits_btb_bht_value; // @[ShiftQueue.scala:12:7] wire [31:0] io_enq_bits_pc_0 = io_enq_bits_pc; // @[ShiftQueue.scala:12:7] wire [31:0] io_enq_bits_data_0 = io_enq_bits_data; // @[ShiftQueue.scala:12:7] wire [1:0] io_enq_bits_mask_0 = io_enq_bits_mask; // @[ShiftQueue.scala:12:7] wire io_enq_bits_xcpt_pf_inst_0 = io_enq_bits_xcpt_pf_inst; // @[ShiftQueue.scala:12:7] wire io_enq_bits_xcpt_ae_inst_0 = io_enq_bits_xcpt_ae_inst; // @[ShiftQueue.scala:12:7] wire io_enq_bits_replay_0 = io_enq_bits_replay; // @[ShiftQueue.scala:12:7] wire io_deq_ready_0 = io_deq_ready; // @[ShiftQueue.scala:12:7] wire io_enq_bits_btb_taken = 1'h0; // @[ShiftQueue.scala:12:7] wire io_enq_bits_xcpt_gf_inst = 1'h0; // @[ShiftQueue.scala:12:7] wire _valid_WIRE_0 = 1'h0; // @[ShiftQueue.scala:21:38] wire _valid_WIRE_1 = 1'h0; // @[ShiftQueue.scala:21:38] wire _valid_WIRE_2 = 1'h0; // @[ShiftQueue.scala:21:38] wire _valid_WIRE_3 = 1'h0; // @[ShiftQueue.scala:21:38] wire _valid_WIRE_4 = 1'h0; // @[ShiftQueue.scala:21:38] wire wdata_3_btb_taken = 1'h0; // @[ShiftQueue.scala:27:57] wire _io_enq_ready_T; // @[ShiftQueue.scala:40:19] wire [2:0] _io_count_T_12; // @[ShiftQueue.scala:54:23] wire [4:0] _io_mask_T; // @[ShiftQueue.scala:53:20] wire io_enq_ready_0; // @[ShiftQueue.scala:12:7] wire [7:0] io_deq_bits_btb_bht_history_0; // @[ShiftQueue.scala:12:7] wire io_deq_bits_btb_bht_value_0; // @[ShiftQueue.scala:12:7] wire [1:0] io_deq_bits_btb_cfiType_0; // @[ShiftQueue.scala:12:7] wire io_deq_bits_btb_taken_0; // @[ShiftQueue.scala:12:7] wire [1:0] io_deq_bits_btb_mask_0; // @[ShiftQueue.scala:12:7] wire io_deq_bits_btb_bridx_0; // @[ShiftQueue.scala:12:7] wire [31:0] io_deq_bits_btb_target_0; // @[ShiftQueue.scala:12:7] wire io_deq_bits_btb_entry_0; // @[ShiftQueue.scala:12:7] wire io_deq_bits_xcpt_pf_inst_0; // @[ShiftQueue.scala:12:7] wire io_deq_bits_xcpt_gf_inst_0; // @[ShiftQueue.scala:12:7] wire io_deq_bits_xcpt_ae_inst_0; // @[ShiftQueue.scala:12:7] wire [31:0] io_deq_bits_pc_0; // @[ShiftQueue.scala:12:7] wire [31:0] io_deq_bits_data_0; // @[ShiftQueue.scala:12:7] wire [1:0] io_deq_bits_mask_0; // @[ShiftQueue.scala:12:7] wire io_deq_bits_replay_0; // @[ShiftQueue.scala:12:7] wire io_deq_valid_0; // @[ShiftQueue.scala:12:7] wire [2:0] io_count; // @[ShiftQueue.scala:12:7] wire [4:0] io_mask_0; // @[ShiftQueue.scala:12:7] reg valid_0; // @[ShiftQueue.scala:21:30] wire _wen_T_1 = valid_0; // @[ShiftQueue.scala:21:30, :30:67] wire _valid_0_T_1 = valid_0; // @[ShiftQueue.scala:21:30, :36:67] reg valid_1; // @[ShiftQueue.scala:21:30] wire _wen_T_9 = valid_1; // @[ShiftQueue.scala:21:30, :30:67] wire _valid_1_T_1 = valid_1; // @[ShiftQueue.scala:21:30, :36:67] reg valid_2; // @[ShiftQueue.scala:21:30] wire _wen_T_17 = valid_2; // @[ShiftQueue.scala:21:30, :30:67] wire _valid_2_T_1 = valid_2; // @[ShiftQueue.scala:21:30, :36:67] reg valid_3; // @[ShiftQueue.scala:21:30] wire _wen_T_25 = valid_3; // @[ShiftQueue.scala:21:30, :30:67] wire _valid_3_T_1 = valid_3; // @[ShiftQueue.scala:21:30, :36:67] reg valid_4; // @[ShiftQueue.scala:21:30] wire _wen_T_33 = valid_4; // @[ShiftQueue.scala:21:30, :30:67] wire _valid_4_T_1 = valid_4; // @[ShiftQueue.scala:21:30, :36:67] reg [1:0] elts_0_btb_cfiType; // @[ShiftQueue.scala:22:25] reg elts_0_btb_taken; // @[ShiftQueue.scala:22:25] reg [1:0] elts_0_btb_mask; // @[ShiftQueue.scala:22:25] reg elts_0_btb_bridx; // @[ShiftQueue.scala:22:25] reg [31:0] elts_0_btb_target; // @[ShiftQueue.scala:22:25] reg elts_0_btb_entry; // @[ShiftQueue.scala:22:25] reg [7:0] elts_0_btb_bht_history; // @[ShiftQueue.scala:22:25] reg elts_0_btb_bht_value; // @[ShiftQueue.scala:22:25] reg [31:0] elts_0_pc; // @[ShiftQueue.scala:22:25] reg [31:0] elts_0_data; // @[ShiftQueue.scala:22:25] reg [1:0] elts_0_mask; // @[ShiftQueue.scala:22:25] reg elts_0_xcpt_pf_inst; // @[ShiftQueue.scala:22:25] reg elts_0_xcpt_gf_inst; // @[ShiftQueue.scala:22:25] reg elts_0_xcpt_ae_inst; // @[ShiftQueue.scala:22:25] reg elts_0_replay; // @[ShiftQueue.scala:22:25] reg [1:0] elts_1_btb_cfiType; // @[ShiftQueue.scala:22:25] reg elts_1_btb_taken; // @[ShiftQueue.scala:22:25] reg [1:0] elts_1_btb_mask; // @[ShiftQueue.scala:22:25] reg elts_1_btb_bridx; // @[ShiftQueue.scala:22:25] reg [31:0] elts_1_btb_target; // @[ShiftQueue.scala:22:25] reg elts_1_btb_entry; // @[ShiftQueue.scala:22:25] reg [7:0] elts_1_btb_bht_history; // @[ShiftQueue.scala:22:25] reg elts_1_btb_bht_value; // @[ShiftQueue.scala:22:25] reg [31:0] elts_1_pc; // @[ShiftQueue.scala:22:25] reg [31:0] elts_1_data; // @[ShiftQueue.scala:22:25] reg [1:0] elts_1_mask; // @[ShiftQueue.scala:22:25] reg elts_1_xcpt_pf_inst; // @[ShiftQueue.scala:22:25] reg elts_1_xcpt_gf_inst; // @[ShiftQueue.scala:22:25] reg elts_1_xcpt_ae_inst; // @[ShiftQueue.scala:22:25] reg elts_1_replay; // @[ShiftQueue.scala:22:25] reg [1:0] elts_2_btb_cfiType; // @[ShiftQueue.scala:22:25] reg elts_2_btb_taken; // @[ShiftQueue.scala:22:25] reg [1:0] elts_2_btb_mask; // @[ShiftQueue.scala:22:25] reg elts_2_btb_bridx; // @[ShiftQueue.scala:22:25] reg [31:0] elts_2_btb_target; // @[ShiftQueue.scala:22:25] reg elts_2_btb_entry; // @[ShiftQueue.scala:22:25] reg [7:0] elts_2_btb_bht_history; // @[ShiftQueue.scala:22:25] reg elts_2_btb_bht_value; // @[ShiftQueue.scala:22:25] reg [31:0] elts_2_pc; // @[ShiftQueue.scala:22:25] reg [31:0] elts_2_data; // @[ShiftQueue.scala:22:25] reg [1:0] elts_2_mask; // @[ShiftQueue.scala:22:25] reg elts_2_xcpt_pf_inst; // @[ShiftQueue.scala:22:25] reg elts_2_xcpt_gf_inst; // @[ShiftQueue.scala:22:25] reg elts_2_xcpt_ae_inst; // @[ShiftQueue.scala:22:25] reg elts_2_replay; // @[ShiftQueue.scala:22:25] reg [1:0] elts_3_btb_cfiType; // @[ShiftQueue.scala:22:25] reg elts_3_btb_taken; // @[ShiftQueue.scala:22:25] reg [1:0] elts_3_btb_mask; // @[ShiftQueue.scala:22:25] reg elts_3_btb_bridx; // @[ShiftQueue.scala:22:25] reg [31:0] elts_3_btb_target; // @[ShiftQueue.scala:22:25] reg elts_3_btb_entry; // @[ShiftQueue.scala:22:25] reg [7:0] elts_3_btb_bht_history; // @[ShiftQueue.scala:22:25] reg elts_3_btb_bht_value; // @[ShiftQueue.scala:22:25] reg [31:0] elts_3_pc; // @[ShiftQueue.scala:22:25] reg [31:0] elts_3_data; // @[ShiftQueue.scala:22:25] reg [1:0] elts_3_mask; // @[ShiftQueue.scala:22:25] reg elts_3_xcpt_pf_inst; // @[ShiftQueue.scala:22:25] reg elts_3_xcpt_gf_inst; // @[ShiftQueue.scala:22:25] reg elts_3_xcpt_ae_inst; // @[ShiftQueue.scala:22:25] reg elts_3_replay; // @[ShiftQueue.scala:22:25] reg [1:0] elts_4_btb_cfiType; // @[ShiftQueue.scala:22:25] reg [1:0] elts_4_btb_mask; // @[ShiftQueue.scala:22:25] reg elts_4_btb_bridx; // @[ShiftQueue.scala:22:25] reg [31:0] elts_4_btb_target; // @[ShiftQueue.scala:22:25] reg elts_4_btb_entry; // @[ShiftQueue.scala:22:25] reg [7:0] elts_4_btb_bht_history; // @[ShiftQueue.scala:22:25] reg elts_4_btb_bht_value; // @[ShiftQueue.scala:22:25] reg [31:0] elts_4_pc; // @[ShiftQueue.scala:22:25] reg [31:0] elts_4_data; // @[ShiftQueue.scala:22:25] reg [1:0] elts_4_mask; // @[ShiftQueue.scala:22:25] reg elts_4_xcpt_pf_inst; // @[ShiftQueue.scala:22:25] reg elts_4_xcpt_gf_inst; // @[ShiftQueue.scala:22:25] reg elts_4_xcpt_ae_inst; // @[ShiftQueue.scala:22:25] reg elts_4_replay; // @[ShiftQueue.scala:22:25] wire [1:0] wdata_btb_cfiType = valid_1 ? elts_1_btb_cfiType : io_enq_bits_btb_cfiType_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_btb_taken = valid_1 & elts_1_btb_taken; // @[ShiftQueue.scala:21:30, :22:25, :27:57] wire [1:0] wdata_btb_mask = valid_1 ? elts_1_btb_mask : io_enq_bits_btb_mask_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_btb_bridx = valid_1 ? elts_1_btb_bridx : io_enq_bits_btb_bridx_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [31:0] wdata_btb_target = valid_1 ? elts_1_btb_target : io_enq_bits_btb_target_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_btb_entry = valid_1 ? elts_1_btb_entry : io_enq_bits_btb_entry_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [7:0] wdata_btb_bht_history = valid_1 ? elts_1_btb_bht_history : io_enq_bits_btb_bht_history_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_btb_bht_value = valid_1 ? elts_1_btb_bht_value : io_enq_bits_btb_bht_value_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [31:0] wdata_pc = valid_1 ? elts_1_pc : io_enq_bits_pc_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [31:0] wdata_data = valid_1 ? elts_1_data : io_enq_bits_data_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [1:0] wdata_mask = valid_1 ? elts_1_mask : io_enq_bits_mask_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_xcpt_pf_inst = valid_1 ? elts_1_xcpt_pf_inst : io_enq_bits_xcpt_pf_inst_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_xcpt_gf_inst = valid_1 & elts_1_xcpt_gf_inst; // @[ShiftQueue.scala:21:30, :22:25, :27:57] wire wdata_xcpt_ae_inst = valid_1 ? elts_1_xcpt_ae_inst : io_enq_bits_xcpt_ae_inst_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_replay = valid_1 ? elts_1_replay : io_enq_bits_replay_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire _GEN = io_enq_ready_0 & io_enq_valid_0; // @[Decoupled.scala:51:35] wire _wen_T; // @[Decoupled.scala:51:35] assign _wen_T = _GEN; // @[Decoupled.scala:51:35] wire _wen_T_4; // @[Decoupled.scala:51:35] assign _wen_T_4 = _GEN; // @[Decoupled.scala:51:35] wire _valid_0_T; // @[Decoupled.scala:51:35] assign _valid_0_T = _GEN; // @[Decoupled.scala:51:35] wire _valid_0_T_4; // @[Decoupled.scala:51:35] assign _valid_0_T_4 = _GEN; // @[Decoupled.scala:51:35] wire _wen_T_8; // @[Decoupled.scala:51:35] assign _wen_T_8 = _GEN; // @[Decoupled.scala:51:35] wire _wen_T_12; // @[Decoupled.scala:51:35] assign _wen_T_12 = _GEN; // @[Decoupled.scala:51:35] wire _valid_1_T; // @[Decoupled.scala:51:35] assign _valid_1_T = _GEN; // @[Decoupled.scala:51:35] wire _valid_1_T_4; // @[Decoupled.scala:51:35] assign _valid_1_T_4 = _GEN; // @[Decoupled.scala:51:35] wire _wen_T_16; // @[Decoupled.scala:51:35] assign _wen_T_16 = _GEN; // @[Decoupled.scala:51:35] wire _wen_T_20; // @[Decoupled.scala:51:35] assign _wen_T_20 = _GEN; // @[Decoupled.scala:51:35] wire _valid_2_T; // @[Decoupled.scala:51:35] assign _valid_2_T = _GEN; // @[Decoupled.scala:51:35] wire _valid_2_T_4; // @[Decoupled.scala:51:35] assign _valid_2_T_4 = _GEN; // @[Decoupled.scala:51:35] wire _wen_T_24; // @[Decoupled.scala:51:35] assign _wen_T_24 = _GEN; // @[Decoupled.scala:51:35] wire _wen_T_28; // @[Decoupled.scala:51:35] assign _wen_T_28 = _GEN; // @[Decoupled.scala:51:35] wire _valid_3_T; // @[Decoupled.scala:51:35] assign _valid_3_T = _GEN; // @[Decoupled.scala:51:35] wire _valid_3_T_4; // @[Decoupled.scala:51:35] assign _valid_3_T_4 = _GEN; // @[Decoupled.scala:51:35] wire _wen_T_32; // @[Decoupled.scala:51:35] assign _wen_T_32 = _GEN; // @[Decoupled.scala:51:35] wire _wen_T_36; // @[Decoupled.scala:51:35] assign _wen_T_36 = _GEN; // @[Decoupled.scala:51:35] wire _valid_4_T; // @[Decoupled.scala:51:35] assign _valid_4_T = _GEN; // @[Decoupled.scala:51:35] wire _valid_4_T_4; // @[Decoupled.scala:51:35] assign _valid_4_T_4 = _GEN; // @[Decoupled.scala:51:35] wire _wen_T_2 = _wen_T & _wen_T_1; // @[Decoupled.scala:51:35] wire _wen_T_3 = valid_1 | _wen_T_2; // @[ShiftQueue.scala:21:30, :30:{28,43}] wire _wen_T_5 = _wen_T_4; // @[Decoupled.scala:51:35] wire _wen_T_6 = ~valid_0; // @[ShiftQueue.scala:21:30, :31:46] wire _wen_T_7 = _wen_T_5 & _wen_T_6; // @[ShiftQueue.scala:31:{23,43,46}] wire wen = io_deq_ready_0 ? _wen_T_3 : _wen_T_7; // @[ShiftQueue.scala:12:7, :29:10, :30:28, :31:43] wire _valid_0_T_2 = _valid_0_T & _valid_0_T_1; // @[Decoupled.scala:51:35] wire _valid_0_T_3 = valid_1 | _valid_0_T_2; // @[ShiftQueue.scala:21:30, :36:{28,43}] wire _valid_0_T_5 = _valid_0_T_4; // @[Decoupled.scala:51:35] wire _valid_0_T_6 = _valid_0_T_5 | valid_0; // @[ShiftQueue.scala:21:30, :37:{23,43}] wire _valid_0_T_7 = io_deq_ready_0 ? _valid_0_T_3 : _valid_0_T_6; // @[ShiftQueue.scala:12:7, :35:10, :36:28, :37:43] wire [1:0] wdata_1_btb_cfiType = valid_2 ? elts_2_btb_cfiType : io_enq_bits_btb_cfiType_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_1_btb_taken = valid_2 & elts_2_btb_taken; // @[ShiftQueue.scala:21:30, :22:25, :27:57] wire [1:0] wdata_1_btb_mask = valid_2 ? elts_2_btb_mask : io_enq_bits_btb_mask_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_1_btb_bridx = valid_2 ? elts_2_btb_bridx : io_enq_bits_btb_bridx_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [31:0] wdata_1_btb_target = valid_2 ? elts_2_btb_target : io_enq_bits_btb_target_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_1_btb_entry = valid_2 ? elts_2_btb_entry : io_enq_bits_btb_entry_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [7:0] wdata_1_btb_bht_history = valid_2 ? elts_2_btb_bht_history : io_enq_bits_btb_bht_history_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_1_btb_bht_value = valid_2 ? elts_2_btb_bht_value : io_enq_bits_btb_bht_value_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [31:0] wdata_1_pc = valid_2 ? elts_2_pc : io_enq_bits_pc_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [31:0] wdata_1_data = valid_2 ? elts_2_data : io_enq_bits_data_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [1:0] wdata_1_mask = valid_2 ? elts_2_mask : io_enq_bits_mask_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_1_xcpt_pf_inst = valid_2 ? elts_2_xcpt_pf_inst : io_enq_bits_xcpt_pf_inst_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_1_xcpt_gf_inst = valid_2 & elts_2_xcpt_gf_inst; // @[ShiftQueue.scala:21:30, :22:25, :27:57] wire wdata_1_xcpt_ae_inst = valid_2 ? elts_2_xcpt_ae_inst : io_enq_bits_xcpt_ae_inst_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_1_replay = valid_2 ? elts_2_replay : io_enq_bits_replay_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire _wen_T_10 = _wen_T_8 & _wen_T_9; // @[Decoupled.scala:51:35] wire _wen_T_11 = valid_2 | _wen_T_10; // @[ShiftQueue.scala:21:30, :30:{28,43}] wire _wen_T_13 = _wen_T_12 & valid_0; // @[Decoupled.scala:51:35] wire _wen_T_14 = ~valid_1; // @[ShiftQueue.scala:21:30, :31:46] wire _wen_T_15 = _wen_T_13 & _wen_T_14; // @[ShiftQueue.scala:31:{23,43,46}] wire wen_1 = io_deq_ready_0 ? _wen_T_11 : _wen_T_15; // @[ShiftQueue.scala:12:7, :29:10, :30:28, :31:43] wire _valid_1_T_2 = _valid_1_T & _valid_1_T_1; // @[Decoupled.scala:51:35] wire _valid_1_T_3 = valid_2 | _valid_1_T_2; // @[ShiftQueue.scala:21:30, :36:{28,43}] wire _valid_1_T_5 = _valid_1_T_4 & valid_0; // @[Decoupled.scala:51:35] wire _valid_1_T_6 = _valid_1_T_5 | valid_1; // @[ShiftQueue.scala:21:30, :37:{23,43}] wire _valid_1_T_7 = io_deq_ready_0 ? _valid_1_T_3 : _valid_1_T_6; // @[ShiftQueue.scala:12:7, :35:10, :36:28, :37:43] wire [1:0] wdata_2_btb_cfiType = valid_3 ? elts_3_btb_cfiType : io_enq_bits_btb_cfiType_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_2_btb_taken = valid_3 & elts_3_btb_taken; // @[ShiftQueue.scala:21:30, :22:25, :27:57] wire [1:0] wdata_2_btb_mask = valid_3 ? elts_3_btb_mask : io_enq_bits_btb_mask_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_2_btb_bridx = valid_3 ? elts_3_btb_bridx : io_enq_bits_btb_bridx_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [31:0] wdata_2_btb_target = valid_3 ? elts_3_btb_target : io_enq_bits_btb_target_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_2_btb_entry = valid_3 ? elts_3_btb_entry : io_enq_bits_btb_entry_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [7:0] wdata_2_btb_bht_history = valid_3 ? elts_3_btb_bht_history : io_enq_bits_btb_bht_history_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_2_btb_bht_value = valid_3 ? elts_3_btb_bht_value : io_enq_bits_btb_bht_value_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [31:0] wdata_2_pc = valid_3 ? elts_3_pc : io_enq_bits_pc_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [31:0] wdata_2_data = valid_3 ? elts_3_data : io_enq_bits_data_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [1:0] wdata_2_mask = valid_3 ? elts_3_mask : io_enq_bits_mask_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_2_xcpt_pf_inst = valid_3 ? elts_3_xcpt_pf_inst : io_enq_bits_xcpt_pf_inst_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_2_xcpt_gf_inst = valid_3 & elts_3_xcpt_gf_inst; // @[ShiftQueue.scala:21:30, :22:25, :27:57] wire wdata_2_xcpt_ae_inst = valid_3 ? elts_3_xcpt_ae_inst : io_enq_bits_xcpt_ae_inst_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_2_replay = valid_3 ? elts_3_replay : io_enq_bits_replay_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire _wen_T_18 = _wen_T_16 & _wen_T_17; // @[Decoupled.scala:51:35] wire _wen_T_19 = valid_3 | _wen_T_18; // @[ShiftQueue.scala:21:30, :30:{28,43}] wire _wen_T_21 = _wen_T_20 & valid_1; // @[Decoupled.scala:51:35] wire _wen_T_22 = ~valid_2; // @[ShiftQueue.scala:21:30, :31:46] wire _wen_T_23 = _wen_T_21 & _wen_T_22; // @[ShiftQueue.scala:31:{23,43,46}] wire wen_2 = io_deq_ready_0 ? _wen_T_19 : _wen_T_23; // @[ShiftQueue.scala:12:7, :29:10, :30:28, :31:43] wire _valid_2_T_2 = _valid_2_T & _valid_2_T_1; // @[Decoupled.scala:51:35] wire _valid_2_T_3 = valid_3 | _valid_2_T_2; // @[ShiftQueue.scala:21:30, :36:{28,43}] wire _valid_2_T_5 = _valid_2_T_4 & valid_1; // @[Decoupled.scala:51:35] wire _valid_2_T_6 = _valid_2_T_5 | valid_2; // @[ShiftQueue.scala:21:30, :37:{23,43}] wire _valid_2_T_7 = io_deq_ready_0 ? _valid_2_T_3 : _valid_2_T_6; // @[ShiftQueue.scala:12:7, :35:10, :36:28, :37:43] wire [1:0] wdata_3_btb_cfiType = valid_4 ? elts_4_btb_cfiType : io_enq_bits_btb_cfiType_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [1:0] wdata_3_btb_mask = valid_4 ? elts_4_btb_mask : io_enq_bits_btb_mask_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_3_btb_bridx = valid_4 ? elts_4_btb_bridx : io_enq_bits_btb_bridx_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [31:0] wdata_3_btb_target = valid_4 ? elts_4_btb_target : io_enq_bits_btb_target_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_3_btb_entry = valid_4 ? elts_4_btb_entry : io_enq_bits_btb_entry_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [7:0] wdata_3_btb_bht_history = valid_4 ? elts_4_btb_bht_history : io_enq_bits_btb_bht_history_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_3_btb_bht_value = valid_4 ? elts_4_btb_bht_value : io_enq_bits_btb_bht_value_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [31:0] wdata_3_pc = valid_4 ? elts_4_pc : io_enq_bits_pc_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [31:0] wdata_3_data = valid_4 ? elts_4_data : io_enq_bits_data_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [1:0] wdata_3_mask = valid_4 ? elts_4_mask : io_enq_bits_mask_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_3_xcpt_pf_inst = valid_4 ? elts_4_xcpt_pf_inst : io_enq_bits_xcpt_pf_inst_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_3_xcpt_gf_inst = valid_4 & elts_4_xcpt_gf_inst; // @[ShiftQueue.scala:21:30, :22:25, :27:57] wire wdata_3_xcpt_ae_inst = valid_4 ? elts_4_xcpt_ae_inst : io_enq_bits_xcpt_ae_inst_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_3_replay = valid_4 ? elts_4_replay : io_enq_bits_replay_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire _wen_T_26 = _wen_T_24 & _wen_T_25; // @[Decoupled.scala:51:35] wire _wen_T_27 = valid_4 | _wen_T_26; // @[ShiftQueue.scala:21:30, :30:{28,43}] wire _wen_T_29 = _wen_T_28 & valid_2; // @[Decoupled.scala:51:35] wire _wen_T_30 = ~valid_3; // @[ShiftQueue.scala:21:30, :31:46] wire _wen_T_31 = _wen_T_29 & _wen_T_30; // @[ShiftQueue.scala:31:{23,43,46}] wire wen_3 = io_deq_ready_0 ? _wen_T_27 : _wen_T_31; // @[ShiftQueue.scala:12:7, :29:10, :30:28, :31:43] wire _valid_3_T_2 = _valid_3_T & _valid_3_T_1; // @[Decoupled.scala:51:35] wire _valid_3_T_3 = valid_4 | _valid_3_T_2; // @[ShiftQueue.scala:21:30, :36:{28,43}] wire _valid_3_T_5 = _valid_3_T_4 & valid_2; // @[Decoupled.scala:51:35] wire _valid_3_T_6 = _valid_3_T_5 | valid_3; // @[ShiftQueue.scala:21:30, :37:{23,43}] wire _valid_3_T_7 = io_deq_ready_0 ? _valid_3_T_3 : _valid_3_T_6; // @[ShiftQueue.scala:12:7, :35:10, :36:28, :37:43] wire _wen_T_34 = _wen_T_32 & _wen_T_33; // @[Decoupled.scala:51:35] wire _wen_T_35 = _wen_T_34; // @[ShiftQueue.scala:30:{28,43}] wire _wen_T_37 = _wen_T_36 & valid_3; // @[Decoupled.scala:51:35] wire _wen_T_38 = ~valid_4; // @[ShiftQueue.scala:21:30, :31:46] wire _wen_T_39 = _wen_T_37 & _wen_T_38; // @[ShiftQueue.scala:31:{23,43,46}] wire wen_4 = io_deq_ready_0 ? _wen_T_35 : _wen_T_39; // @[ShiftQueue.scala:12:7, :29:10, :30:28, :31:43] wire _valid_4_T_2 = _valid_4_T & _valid_4_T_1; // @[Decoupled.scala:51:35] wire _valid_4_T_3 = _valid_4_T_2; // @[ShiftQueue.scala:36:{28,43}] wire _valid_4_T_5 = _valid_4_T_4 & valid_3; // @[Decoupled.scala:51:35] wire _valid_4_T_6 = _valid_4_T_5 | valid_4; // @[ShiftQueue.scala:21:30, :37:{23,43}] wire _valid_4_T_7 = io_deq_ready_0 ? _valid_4_T_3 : _valid_4_T_6; // @[ShiftQueue.scala:12:7, :35:10, :36:28, :37:43] assign _io_enq_ready_T = ~valid_4; // @[ShiftQueue.scala:21:30, :31:46, :40:19] assign io_enq_ready_0 = _io_enq_ready_T; // @[ShiftQueue.scala:12:7, :40:19] assign io_deq_valid_0 = io_enq_valid_0 | valid_0; // @[ShiftQueue.scala:12:7, :21:30, :41:16, :45:{25,40}] assign io_deq_bits_btb_cfiType_0 = valid_0 ? elts_0_btb_cfiType : io_enq_bits_btb_cfiType_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_btb_taken_0 = valid_0 & elts_0_btb_taken; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_btb_mask_0 = valid_0 ? elts_0_btb_mask : io_enq_bits_btb_mask_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_btb_bridx_0 = valid_0 ? elts_0_btb_bridx : io_enq_bits_btb_bridx_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_btb_target_0 = valid_0 ? elts_0_btb_target : io_enq_bits_btb_target_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_btb_entry_0 = valid_0 ? elts_0_btb_entry : io_enq_bits_btb_entry_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_btb_bht_history_0 = valid_0 ? elts_0_btb_bht_history : io_enq_bits_btb_bht_history_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_btb_bht_value_0 = valid_0 ? elts_0_btb_bht_value : io_enq_bits_btb_bht_value_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_pc_0 = valid_0 ? elts_0_pc : io_enq_bits_pc_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_data_0 = valid_0 ? elts_0_data : io_enq_bits_data_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_mask_0 = valid_0 ? elts_0_mask : io_enq_bits_mask_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_xcpt_pf_inst_0 = valid_0 ? elts_0_xcpt_pf_inst : io_enq_bits_xcpt_pf_inst_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_xcpt_gf_inst_0 = valid_0 & elts_0_xcpt_gf_inst; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_xcpt_ae_inst_0 = valid_0 ? elts_0_xcpt_ae_inst : io_enq_bits_xcpt_ae_inst_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_replay_0 = valid_0 ? elts_0_replay : io_enq_bits_replay_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] wire [1:0] io_mask_lo = {valid_1, valid_0}; // @[ShiftQueue.scala:21:30, :53:20] wire [1:0] io_mask_hi_hi = {valid_4, valid_3}; // @[ShiftQueue.scala:21:30, :53:20] wire [2:0] io_mask_hi = {io_mask_hi_hi, valid_2}; // @[ShiftQueue.scala:21:30, :53:20] assign _io_mask_T = {io_mask_hi, io_mask_lo}; // @[ShiftQueue.scala:53:20] assign io_mask_0 = _io_mask_T; // @[ShiftQueue.scala:12:7, :53:20] wire _io_count_T = io_mask_0[0]; // @[ShiftQueue.scala:12:7, :54:23] wire _io_count_T_1 = io_mask_0[1]; // @[ShiftQueue.scala:12:7, :54:23] wire _io_count_T_2 = io_mask_0[2]; // @[ShiftQueue.scala:12:7, :54:23] wire _io_count_T_3 = io_mask_0[3]; // @[ShiftQueue.scala:12:7, :54:23] wire _io_count_T_4 = io_mask_0[4]; // @[ShiftQueue.scala:12:7, :54:23] wire [1:0] _io_count_T_5 = {1'h0, _io_count_T} + {1'h0, _io_count_T_1}; // @[ShiftQueue.scala:54:23] wire [1:0] _io_count_T_6 = _io_count_T_5; // @[ShiftQueue.scala:54:23] wire [1:0] _io_count_T_7 = {1'h0, _io_count_T_3} + {1'h0, _io_count_T_4}; // @[ShiftQueue.scala:54:23] wire [1:0] _io_count_T_8 = _io_count_T_7; // @[ShiftQueue.scala:54:23] wire [2:0] _io_count_T_9 = {2'h0, _io_count_T_2} + {1'h0, _io_count_T_8}; // @[ShiftQueue.scala:54:23] wire [1:0] _io_count_T_10 = _io_count_T_9[1:0]; // @[ShiftQueue.scala:54:23] wire [2:0] _io_count_T_11 = {1'h0, _io_count_T_6} + {1'h0, _io_count_T_10}; // @[ShiftQueue.scala:54:23] assign _io_count_T_12 = _io_count_T_11; // @[ShiftQueue.scala:54:23] assign io_count = _io_count_T_12; // @[ShiftQueue.scala:12:7, :54:23] always @(posedge clock) begin // @[ShiftQueue.scala:12:7] if (reset) begin // @[ShiftQueue.scala:12:7] valid_0 <= 1'h0; // @[ShiftQueue.scala:21:30] valid_1 <= 1'h0; // @[ShiftQueue.scala:21:30] valid_2 <= 1'h0; // @[ShiftQueue.scala:21:30] valid_3 <= 1'h0; // @[ShiftQueue.scala:21:30] valid_4 <= 1'h0; // @[ShiftQueue.scala:21:30] end else begin // @[ShiftQueue.scala:12:7] valid_0 <= _valid_0_T_7; // @[ShiftQueue.scala:21:30, :35:10] valid_1 <= _valid_1_T_7; // @[ShiftQueue.scala:21:30, :35:10] valid_2 <= _valid_2_T_7; // @[ShiftQueue.scala:21:30, :35:10] valid_3 <= _valid_3_T_7; // @[ShiftQueue.scala:21:30, :35:10] valid_4 <= _valid_4_T_7; // @[ShiftQueue.scala:21:30, :35:10] end if (wen) begin // @[ShiftQueue.scala:29:10] elts_0_btb_cfiType <= wdata_btb_cfiType; // @[ShiftQueue.scala:22:25, :27:57] elts_0_btb_taken <= wdata_btb_taken; // @[ShiftQueue.scala:22:25, :27:57] elts_0_btb_mask <= wdata_btb_mask; // @[ShiftQueue.scala:22:25, :27:57] elts_0_btb_bridx <= wdata_btb_bridx; // @[ShiftQueue.scala:22:25, :27:57] elts_0_btb_target <= wdata_btb_target; // @[ShiftQueue.scala:22:25, :27:57] elts_0_btb_entry <= wdata_btb_entry; // @[ShiftQueue.scala:22:25, :27:57] elts_0_btb_bht_history <= wdata_btb_bht_history; // @[ShiftQueue.scala:22:25, :27:57] elts_0_btb_bht_value <= wdata_btb_bht_value; // @[ShiftQueue.scala:22:25, :27:57] elts_0_pc <= wdata_pc; // @[ShiftQueue.scala:22:25, :27:57] elts_0_data <= wdata_data; // @[ShiftQueue.scala:22:25, :27:57] elts_0_mask <= wdata_mask; // @[ShiftQueue.scala:22:25, :27:57] elts_0_xcpt_pf_inst <= wdata_xcpt_pf_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_0_xcpt_gf_inst <= wdata_xcpt_gf_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_0_xcpt_ae_inst <= wdata_xcpt_ae_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_0_replay <= wdata_replay; // @[ShiftQueue.scala:22:25, :27:57] end if (wen_1) begin // @[ShiftQueue.scala:29:10] elts_1_btb_cfiType <= wdata_1_btb_cfiType; // @[ShiftQueue.scala:22:25, :27:57] elts_1_btb_taken <= wdata_1_btb_taken; // @[ShiftQueue.scala:22:25, :27:57] elts_1_btb_mask <= wdata_1_btb_mask; // @[ShiftQueue.scala:22:25, :27:57] elts_1_btb_bridx <= wdata_1_btb_bridx; // @[ShiftQueue.scala:22:25, :27:57] elts_1_btb_target <= wdata_1_btb_target; // @[ShiftQueue.scala:22:25, :27:57] elts_1_btb_entry <= wdata_1_btb_entry; // @[ShiftQueue.scala:22:25, :27:57] elts_1_btb_bht_history <= wdata_1_btb_bht_history; // @[ShiftQueue.scala:22:25, :27:57] elts_1_btb_bht_value <= wdata_1_btb_bht_value; // @[ShiftQueue.scala:22:25, :27:57] elts_1_pc <= wdata_1_pc; // @[ShiftQueue.scala:22:25, :27:57] elts_1_data <= wdata_1_data; // @[ShiftQueue.scala:22:25, :27:57] elts_1_mask <= wdata_1_mask; // @[ShiftQueue.scala:22:25, :27:57] elts_1_xcpt_pf_inst <= wdata_1_xcpt_pf_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_1_xcpt_gf_inst <= wdata_1_xcpt_gf_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_1_xcpt_ae_inst <= wdata_1_xcpt_ae_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_1_replay <= wdata_1_replay; // @[ShiftQueue.scala:22:25, :27:57] end if (wen_2) begin // @[ShiftQueue.scala:29:10] elts_2_btb_cfiType <= wdata_2_btb_cfiType; // @[ShiftQueue.scala:22:25, :27:57] elts_2_btb_taken <= wdata_2_btb_taken; // @[ShiftQueue.scala:22:25, :27:57] elts_2_btb_mask <= wdata_2_btb_mask; // @[ShiftQueue.scala:22:25, :27:57] elts_2_btb_bridx <= wdata_2_btb_bridx; // @[ShiftQueue.scala:22:25, :27:57] elts_2_btb_target <= wdata_2_btb_target; // @[ShiftQueue.scala:22:25, :27:57] elts_2_btb_entry <= wdata_2_btb_entry; // @[ShiftQueue.scala:22:25, :27:57] elts_2_btb_bht_history <= wdata_2_btb_bht_history; // @[ShiftQueue.scala:22:25, :27:57] elts_2_btb_bht_value <= wdata_2_btb_bht_value; // @[ShiftQueue.scala:22:25, :27:57] elts_2_pc <= wdata_2_pc; // @[ShiftQueue.scala:22:25, :27:57] elts_2_data <= wdata_2_data; // @[ShiftQueue.scala:22:25, :27:57] elts_2_mask <= wdata_2_mask; // @[ShiftQueue.scala:22:25, :27:57] elts_2_xcpt_pf_inst <= wdata_2_xcpt_pf_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_2_xcpt_gf_inst <= wdata_2_xcpt_gf_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_2_xcpt_ae_inst <= wdata_2_xcpt_ae_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_2_replay <= wdata_2_replay; // @[ShiftQueue.scala:22:25, :27:57] end if (wen_3) begin // @[ShiftQueue.scala:29:10] elts_3_btb_cfiType <= wdata_3_btb_cfiType; // @[ShiftQueue.scala:22:25, :27:57] elts_3_btb_mask <= wdata_3_btb_mask; // @[ShiftQueue.scala:22:25, :27:57] elts_3_btb_bridx <= wdata_3_btb_bridx; // @[ShiftQueue.scala:22:25, :27:57] elts_3_btb_target <= wdata_3_btb_target; // @[ShiftQueue.scala:22:25, :27:57] elts_3_btb_entry <= wdata_3_btb_entry; // @[ShiftQueue.scala:22:25, :27:57] elts_3_btb_bht_history <= wdata_3_btb_bht_history; // @[ShiftQueue.scala:22:25, :27:57] elts_3_btb_bht_value <= wdata_3_btb_bht_value; // @[ShiftQueue.scala:22:25, :27:57] elts_3_pc <= wdata_3_pc; // @[ShiftQueue.scala:22:25, :27:57] elts_3_data <= wdata_3_data; // @[ShiftQueue.scala:22:25, :27:57] elts_3_mask <= wdata_3_mask; // @[ShiftQueue.scala:22:25, :27:57] elts_3_xcpt_pf_inst <= wdata_3_xcpt_pf_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_3_xcpt_gf_inst <= wdata_3_xcpt_gf_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_3_xcpt_ae_inst <= wdata_3_xcpt_ae_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_3_replay <= wdata_3_replay; // @[ShiftQueue.scala:22:25, :27:57] end elts_3_btb_taken <= ~wen_3 & elts_3_btb_taken; // @[ShiftQueue.scala:22:25, :29:10, :32:{16,26}] if (wen_4) begin // @[ShiftQueue.scala:29:10] elts_4_btb_cfiType <= io_enq_bits_btb_cfiType_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_btb_mask <= io_enq_bits_btb_mask_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_btb_bridx <= io_enq_bits_btb_bridx_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_btb_target <= io_enq_bits_btb_target_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_btb_entry <= io_enq_bits_btb_entry_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_btb_bht_history <= io_enq_bits_btb_bht_history_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_btb_bht_value <= io_enq_bits_btb_bht_value_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_pc <= io_enq_bits_pc_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_data <= io_enq_bits_data_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_mask <= io_enq_bits_mask_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_xcpt_pf_inst <= io_enq_bits_xcpt_pf_inst_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_xcpt_ae_inst <= io_enq_bits_xcpt_ae_inst_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_replay <= io_enq_bits_replay_0; // @[ShiftQueue.scala:12:7, :22:25] end elts_4_xcpt_gf_inst <= ~wen_4 & elts_4_xcpt_gf_inst; // @[ShiftQueue.scala:22:25, :29:10, :32:{16,26}] always @(posedge) assign io_enq_ready = io_enq_ready_0; // @[ShiftQueue.scala:12:7] assign io_deq_valid = io_deq_valid_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_btb_cfiType = io_deq_bits_btb_cfiType_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_btb_taken = io_deq_bits_btb_taken_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_btb_mask = io_deq_bits_btb_mask_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_btb_bridx = io_deq_bits_btb_bridx_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_btb_target = io_deq_bits_btb_target_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_btb_entry = io_deq_bits_btb_entry_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_btb_bht_history = io_deq_bits_btb_bht_history_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_btb_bht_value = io_deq_bits_btb_bht_value_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_pc = io_deq_bits_pc_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_data = io_deq_bits_data_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_mask = io_deq_bits_mask_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_xcpt_pf_inst = io_deq_bits_xcpt_pf_inst_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_xcpt_gf_inst = io_deq_bits_xcpt_gf_inst_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_xcpt_ae_inst = io_deq_bits_xcpt_ae_inst_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_replay = io_deq_bits_replay_0; // @[ShiftQueue.scala:12:7] assign io_mask = io_mask_0; // @[ShiftQueue.scala:12:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module TLMonitor_4( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_37 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_43 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_49 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire _source_ok_T_27 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31] wire _source_ok_T_28 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_29 = _source_ok_T_28 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_30 = _source_ok_T_29 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_31 = _source_ok_T_30 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_32 = _source_ok_T_31 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_33 = _source_ok_T_32 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_33 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [28:0] _is_aligned_T = {23'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_34 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_34; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_35 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_41 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_47 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_53 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_36 = _source_ok_T_35 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_38 = _source_ok_T_36; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_40; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_42 = _source_ok_T_41 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_44 = _source_ok_T_42; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_46; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_48 = _source_ok_T_47 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_50 = _source_ok_T_48; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_52; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_54 = _source_ok_T_53 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_58; // @[Parameters.scala:1138:31] wire _source_ok_T_59 = io_in_d_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_59; // @[Parameters.scala:1138:31] wire _source_ok_T_60 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_60; // @[Parameters.scala:1138:31] wire _source_ok_T_61 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_61; // @[Parameters.scala:1138:31] wire _source_ok_T_62 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_63 = _source_ok_T_62 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_64 = _source_ok_T_63 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_65 = _source_ok_T_64 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_66 = _source_ok_T_65 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_67 = _source_ok_T_66 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_67 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _T_1035 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1035; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1035; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [28:0] address; // @[Monitor.scala:391:22] wire _T_1103 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1103; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1103; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1103; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [259:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [259:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_968 = _T_1035 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_968 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_968 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_968 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_968 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_968 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1014 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1014 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_983 = _T_1103 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_983 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_983 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_983 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [259:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1079 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1079 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1061 = _T_1103 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1061 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1061 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1061 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module TLMonitor_56( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [16:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [16:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_release_ack = 1'h0; // @[Monitor.scala:673:46] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire d_release_ack_1 = 1'h0; // @[Monitor.scala:783:46] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire d_first_beats1_opdata = 1'h1; // @[Edges.scala:106:36] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire d_first_beats1_opdata_1 = 1'h1; // @[Edges.scala:106:36] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire d_first_beats1_opdata_2 = 1'h1; // @[Edges.scala:106:36] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [2:0] io_in_d_bits_opcode = 3'h1; // @[Monitor.scala:36:7] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [4159:0] _inflight_opcodes_T_4 = 4160'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[Monitor.scala:815:62] wire [4159:0] _inflight_sizes_T_4 = 4160'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[Monitor.scala:816:58] wire [1039:0] _inflight_T_4 = 1040'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[Monitor.scala:814:46] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [16:0] _c_first_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_first_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_first_WIRE_2_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_first_WIRE_3_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_set_wo_ready_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_set_wo_ready_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_set_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_set_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_opcodes_set_interm_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_opcodes_set_interm_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_sizes_set_interm_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_sizes_set_interm_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_opcodes_set_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_opcodes_set_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_sizes_set_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_sizes_set_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_probe_ack_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_probe_ack_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_probe_ack_WIRE_2_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_probe_ack_WIRE_3_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _same_cycle_resp_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _same_cycle_resp_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _same_cycle_resp_WIRE_2_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _same_cycle_resp_WIRE_3_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _same_cycle_resp_WIRE_4_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _same_cycle_resp_WIRE_5_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_wo_ready_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_wo_ready_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_4_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_5_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [4159:0] c_opcodes_set = 4160'h0; // @[Monitor.scala:740:34] wire [4159:0] c_sizes_set = 4160'h0; // @[Monitor.scala:741:34] wire [4159:0] d_opcodes_clr_1 = 4160'h0; // @[Monitor.scala:776:34] wire [4159:0] d_sizes_clr_1 = 4160'h0; // @[Monitor.scala:777:34] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1039:0] c_set = 1040'h0; // @[Monitor.scala:738:34] wire [1039:0] c_set_wo_ready = 1040'h0; // @[Monitor.scala:739:34] wire [1039:0] d_clr_1 = 1040'h0; // @[Monitor.scala:774:34] wire [1039:0] d_clr_wo_ready_1 = 1040'h0; // @[Monitor.scala:775:34] wire [16385:0] _c_sizes_set_T_1 = 16386'h0; // @[Monitor.scala:768:52] wire [13:0] _c_opcodes_set_T = 14'h0; // @[Monitor.scala:767:79] wire [13:0] _c_sizes_set_T = 14'h0; // @[Monitor.scala:768:77] wire [16386:0] _c_opcodes_set_T_1 = 16387'h0; // @[Monitor.scala:767:54] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [2047:0] _c_set_wo_ready_T = 2048'h1; // @[OneHot.scala:58:35] wire [2047:0] _c_set_T = 2048'h1; // @[OneHot.scala:58:35] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [10:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [16:0] _is_aligned_T = {14'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 17'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [10:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [10:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_659 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_659; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_659; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [10:0] source; // @[Monitor.scala:390:22] reg [16:0] address; // @[Monitor.scala:391:22] wire _T_727 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_727; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_727; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_727; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [10:0] source_1; // @[Monitor.scala:541:22] reg [1039:0] inflight; // @[Monitor.scala:614:27] reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [1039:0] a_set; // @[Monitor.scala:626:34] wire [1039:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [4159:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [4159:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [13:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [13:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [13:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [13:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [13:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [13:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [13:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [13:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [13:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [4159:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [4159:0] _a_opcode_lookup_T_6 = {4156'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [4159:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [4159:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [4159:0] _a_size_lookup_T_6 = {4156'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [4159:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[4159:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [2047:0] _GEN_2 = 2048'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [2047:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_592 = _T_659 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_592 ? _a_set_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_592 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_592 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [13:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [13:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [13:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [16386:0] _a_opcodes_set_T_1 = {16383'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_592 ? _a_opcodes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [16385:0] _a_sizes_set_T_1 = {16383'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_592 ? _a_sizes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [1039:0] d_clr; // @[Monitor.scala:664:34] wire [1039:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [4159:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [4159:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _T_638 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [2047:0] _GEN_4 = 2048'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_4; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_4; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_4; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_638 ? _d_clr_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_605 = _T_727 & d_first_1; // @[Decoupled.scala:51:35] assign d_clr = _T_605 ? _d_clr_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_5 = 16399'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_605 ? _d_opcodes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:668:33, :678:{25,89}, :680:{21,76}] wire [16398:0] _d_sizes_clr_T_5 = 16399'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_605 ? _d_sizes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:670:31, :678:{25,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1039:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [1039:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1039:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [4159:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [4159:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [4159:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [4159:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [4159:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [4159:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1039:0] inflight_1; // @[Monitor.scala:726:35] wire [1039:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [4159:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [4159:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [4159:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [4159:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [4159:0] _c_opcode_lookup_T_6 = {4156'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [4159:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [4159:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [4159:0] _c_size_lookup_T_6 = {4156'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [4159:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[4159:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [16398:0] _d_opcodes_clr_T_11 = 16399'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] wire [16398:0] _d_sizes_clr_T_11 = 16399'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 11'h0; // @[Monitor.scala:36:7, :795:113] wire [1039:0] _inflight_T_5 = _inflight_T_3; // @[Monitor.scala:814:{35,44}] wire [4159:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3; // @[Monitor.scala:815:{43,60}] wire [4159:0] _inflight_sizes_T_5 = _inflight_sizes_T_3; // @[Monitor.scala:816:{41,56}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to the following Chisel files. File Repeater.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{Decoupled, DecoupledIO} // A Repeater passes its input to its output, unless repeat is asserted. // When repeat is asserted, the Repeater copies the input and repeats it next cycle. class Repeater[T <: Data](gen: T) extends Module { override def desiredName = s"Repeater_${gen.typeName}" val io = IO( new Bundle { val repeat = Input(Bool()) val full = Output(Bool()) val enq = Flipped(Decoupled(gen.cloneType)) val deq = Decoupled(gen.cloneType) } ) val full = RegInit(false.B) val saved = Reg(gen.cloneType) // When !full, a repeater is pass-through io.deq.valid := io.enq.valid || full io.enq.ready := io.deq.ready && !full io.deq.bits := Mux(full, saved, io.enq.bits) io.full := full when (io.enq.fire && io.repeat) { full := true.B; saved := io.enq.bits } when (io.deq.fire && !io.repeat) { full := false.B } } object Repeater { def apply[T <: Data](enq: DecoupledIO[T], repeat: Bool): DecoupledIO[T] = { val repeater = Module(new Repeater(chiselTypeOf(enq.bits))) repeater.io.repeat := repeat repeater.io.enq <> enq repeater.io.deq } }

module Repeater_TLBundleA_a21d64s8k1z3u_1( // @[Repeater.scala:10:7] input clock, // @[Repeater.scala:10:7] input reset, // @[Repeater.scala:10:7] input io_repeat, // @[Repeater.scala:13:14] output io_full, // @[Repeater.scala:13:14] output io_enq_ready, // @[Repeater.scala:13:14] input io_enq_valid, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_opcode, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_param, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_size, // @[Repeater.scala:13:14] input [7:0] io_enq_bits_source, // @[Repeater.scala:13:14] input [20:0] io_enq_bits_address, // @[Repeater.scala:13:14] input [7:0] io_enq_bits_mask, // @[Repeater.scala:13:14] input [63:0] io_enq_bits_data, // @[Repeater.scala:13:14] input io_enq_bits_corrupt, // @[Repeater.scala:13:14] input io_deq_ready, // @[Repeater.scala:13:14] output io_deq_valid, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_opcode, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_param, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_size, // @[Repeater.scala:13:14] output [7:0] io_deq_bits_source, // @[Repeater.scala:13:14] output [20:0] io_deq_bits_address, // @[Repeater.scala:13:14] output [7:0] io_deq_bits_mask, // @[Repeater.scala:13:14] output io_deq_bits_corrupt // @[Repeater.scala:13:14] ); wire io_repeat_0 = io_repeat; // @[Repeater.scala:10:7] wire io_enq_valid_0 = io_enq_valid; // @[Repeater.scala:10:7] wire [2:0] io_enq_bits_opcode_0 = io_enq_bits_opcode; // @[Repeater.scala:10:7] wire [2:0] io_enq_bits_param_0 = io_enq_bits_param; // @[Repeater.scala:10:7] wire [2:0] io_enq_bits_size_0 = io_enq_bits_size; // @[Repeater.scala:10:7] wire [7:0] io_enq_bits_source_0 = io_enq_bits_source; // @[Repeater.scala:10:7] wire [20:0] io_enq_bits_address_0 = io_enq_bits_address; // @[Repeater.scala:10:7] wire [7:0] io_enq_bits_mask_0 = io_enq_bits_mask; // @[Repeater.scala:10:7] wire [63:0] io_enq_bits_data_0 = io_enq_bits_data; // @[Repeater.scala:10:7] wire io_enq_bits_corrupt_0 = io_enq_bits_corrupt; // @[Repeater.scala:10:7] wire io_deq_ready_0 = io_deq_ready; // @[Repeater.scala:10:7] wire _io_enq_ready_T_1; // @[Repeater.scala:25:32] wire _io_deq_valid_T; // @[Repeater.scala:24:32] wire [2:0] _io_deq_bits_T_opcode; // @[Repeater.scala:26:21] wire [2:0] _io_deq_bits_T_param; // @[Repeater.scala:26:21] wire [2:0] _io_deq_bits_T_size; // @[Repeater.scala:26:21] wire [7:0] _io_deq_bits_T_source; // @[Repeater.scala:26:21] wire [20:0] _io_deq_bits_T_address; // @[Repeater.scala:26:21] wire [7:0] _io_deq_bits_T_mask; // @[Repeater.scala:26:21] wire [63:0] _io_deq_bits_T_data; // @[Repeater.scala:26:21] wire _io_deq_bits_T_corrupt; // @[Repeater.scala:26:21] wire io_enq_ready_0; // @[Repeater.scala:10:7] wire [2:0] io_deq_bits_opcode_0; // @[Repeater.scala:10:7] wire [2:0] io_deq_bits_param_0; // @[Repeater.scala:10:7] wire [2:0] io_deq_bits_size_0; // @[Repeater.scala:10:7] wire [7:0] io_deq_bits_source_0; // @[Repeater.scala:10:7] wire [20:0] io_deq_bits_address_0; // @[Repeater.scala:10:7] wire [7:0] io_deq_bits_mask_0; // @[Repeater.scala:10:7] wire [63:0] io_deq_bits_data; // @[Repeater.scala:10:7] wire io_deq_bits_corrupt_0; // @[Repeater.scala:10:7] wire io_deq_valid_0; // @[Repeater.scala:10:7] wire io_full_0; // @[Repeater.scala:10:7] reg full; // @[Repeater.scala:20:21] assign io_full_0 = full; // @[Repeater.scala:10:7, :20:21] reg [2:0] saved_opcode; // @[Repeater.scala:21:18] reg [2:0] saved_param; // @[Repeater.scala:21:18] reg [2:0] saved_size; // @[Repeater.scala:21:18] reg [7:0] saved_source; // @[Repeater.scala:21:18] reg [20:0] saved_address; // @[Repeater.scala:21:18] reg [7:0] saved_mask; // @[Repeater.scala:21:18] reg [63:0] saved_data; // @[Repeater.scala:21:18] reg saved_corrupt; // @[Repeater.scala:21:18] assign _io_deq_valid_T = io_enq_valid_0 | full; // @[Repeater.scala:10:7, :20:21, :24:32] assign io_deq_valid_0 = _io_deq_valid_T; // @[Repeater.scala:10:7, :24:32] wire _io_enq_ready_T = ~full; // @[Repeater.scala:20:21, :25:35] assign _io_enq_ready_T_1 = io_deq_ready_0 & _io_enq_ready_T; // @[Repeater.scala:10:7, :25:{32,35}] assign io_enq_ready_0 = _io_enq_ready_T_1; // @[Repeater.scala:10:7, :25:32] assign _io_deq_bits_T_opcode = full ? saved_opcode : io_enq_bits_opcode_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_param = full ? saved_param : io_enq_bits_param_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_size = full ? saved_size : io_enq_bits_size_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_source = full ? saved_source : io_enq_bits_source_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_address = full ? saved_address : io_enq_bits_address_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_mask = full ? saved_mask : io_enq_bits_mask_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_data = full ? saved_data : io_enq_bits_data_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_corrupt = full ? saved_corrupt : io_enq_bits_corrupt_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign io_deq_bits_opcode_0 = _io_deq_bits_T_opcode; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_param_0 = _io_deq_bits_T_param; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_size_0 = _io_deq_bits_T_size; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_source_0 = _io_deq_bits_T_source; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_address_0 = _io_deq_bits_T_address; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_mask_0 = _io_deq_bits_T_mask; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_data = _io_deq_bits_T_data; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_corrupt_0 = _io_deq_bits_T_corrupt; // @[Repeater.scala:10:7, :26:21] wire _T_1 = io_enq_ready_0 & io_enq_valid_0 & io_repeat_0; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[Repeater.scala:10:7] if (reset) // @[Repeater.scala:10:7] full <= 1'h0; // @[Repeater.scala:20:21] else // @[Repeater.scala:10:7] full <= ~(io_deq_ready_0 & io_deq_valid_0 & ~io_repeat_0) & (_T_1 | full); // @[Decoupled.scala:51:35] if (_T_1) begin // @[Decoupled.scala:51:35] saved_opcode <= io_enq_bits_opcode_0; // @[Repeater.scala:10:7, :21:18] saved_param <= io_enq_bits_param_0; // @[Repeater.scala:10:7, :21:18] saved_size <= io_enq_bits_size_0; // @[Repeater.scala:10:7, :21:18] saved_source <= io_enq_bits_source_0; // @[Repeater.scala:10:7, :21:18] saved_address <= io_enq_bits_address_0; // @[Repeater.scala:10:7, :21:18] saved_mask <= io_enq_bits_mask_0; // @[Repeater.scala:10:7, :21:18] saved_data <= io_enq_bits_data_0; // @[Repeater.scala:10:7, :21:18] saved_corrupt <= io_enq_bits_corrupt_0; // @[Repeater.scala:10:7, :21:18] end always @(posedge) assign io_full = io_full_0; // @[Repeater.scala:10:7] assign io_enq_ready = io_enq_ready_0; // @[Repeater.scala:10:7] assign io_deq_valid = io_deq_valid_0; // @[Repeater.scala:10:7] assign io_deq_bits_opcode = io_deq_bits_opcode_0; // @[Repeater.scala:10:7] assign io_deq_bits_param = io_deq_bits_param_0; // @[Repeater.scala:10:7] assign io_deq_bits_size = io_deq_bits_size_0; // @[Repeater.scala:10:7] assign io_deq_bits_source = io_deq_bits_source_0; // @[Repeater.scala:10:7] assign io_deq_bits_address = io_deq_bits_address_0; // @[Repeater.scala:10:7] assign io_deq_bits_mask = io_deq_bits_mask_0; // @[Repeater.scala:10:7] assign io_deq_bits_corrupt = io_deq_bits_corrupt_0; // @[Repeater.scala:10:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands */ class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def *(t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def *(t: UInt) = self * t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros | ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def *(t: SInt) = self * t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros | ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid || output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def *(t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def *(t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }

module MacUnit_234( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [31:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7] wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54] wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Scheduler.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import freechips.rocketchip.diplomacy.AddressSet import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import chisel3.experimental.dataview._ class InclusiveCacheBankScheduler(params: InclusiveCacheParameters) extends Module { val io = IO(new Bundle { val in = Flipped(TLBundle(params.inner.bundle)) val out = TLBundle(params.outer.bundle) // Way permissions val ways = Flipped(Vec(params.allClients, UInt(params.cache.ways.W))) val divs = Flipped(Vec(params.allClients, UInt((InclusiveCacheParameters.lfsrBits + 1).W))) // Control port val req = Flipped(Decoupled(new SinkXRequest(params))) val resp = Decoupled(new SourceXRequest(params)) }) val sourceA = Module(new SourceA(params)) val sourceB = Module(new SourceB(params)) val sourceC = Module(new SourceC(params)) val sourceD = Module(new SourceD(params)) val sourceE = Module(new SourceE(params)) val sourceX = Module(new SourceX(params)) io.out.a <> sourceA.io.a io.out.c <> sourceC.io.c io.out.e <> sourceE.io.e io.in.b <> sourceB.io.b io.in.d <> sourceD.io.d io.resp <> sourceX.io.x val sinkA = Module(new SinkA(params)) val sinkC = Module(new SinkC(params)) val sinkD = Module(new SinkD(params)) val sinkE = Module(new SinkE(params)) val sinkX = Module(new SinkX(params)) sinkA.io.a <> io.in.a sinkC.io.c <> io.in.c sinkE.io.e <> io.in.e sinkD.io.d <> io.out.d sinkX.io.x <> io.req io.out.b.ready := true.B // disconnected val directory = Module(new Directory(params)) val bankedStore = Module(new BankedStore(params)) val requests = Module(new ListBuffer(ListBufferParameters(new QueuedRequest(params), 3*params.mshrs, params.secondary, false))) val mshrs = Seq.fill(params.mshrs) { Module(new MSHR(params)) } val abc_mshrs = mshrs.init.init val bc_mshr = mshrs.init.last val c_mshr = mshrs.last val nestedwb = Wire(new NestedWriteback(params)) // Deliver messages from Sinks to MSHRs mshrs.zipWithIndex.foreach { case (m, i) => m.io.sinkc.valid := sinkC.io.resp.valid && sinkC.io.resp.bits.set === m.io.status.bits.set m.io.sinkd.valid := sinkD.io.resp.valid && sinkD.io.resp.bits.source === i.U m.io.sinke.valid := sinkE.io.resp.valid && sinkE.io.resp.bits.sink === i.U m.io.sinkc.bits := sinkC.io.resp.bits m.io.sinkd.bits := sinkD.io.resp.bits m.io.sinke.bits := sinkE.io.resp.bits m.io.nestedwb := nestedwb } // If the pre-emption BC or C MSHR have a matching set, the normal MSHR must be blocked val mshr_stall_abc = abc_mshrs.map { m => (bc_mshr.io.status.valid && m.io.status.bits.set === bc_mshr.io.status.bits.set) || ( c_mshr.io.status.valid && m.io.status.bits.set === c_mshr.io.status.bits.set) } val mshr_stall_bc = c_mshr.io.status.valid && bc_mshr.io.status.bits.set === c_mshr.io.status.bits.set val mshr_stall_c = false.B val mshr_stall = mshr_stall_abc :+ mshr_stall_bc :+ mshr_stall_c val stall_abc = (mshr_stall_abc zip abc_mshrs) map { case (s, m) => s && m.io.status.valid } if (!params.lastLevel || !params.firstLevel) params.ccover(stall_abc.reduce(_||_), "SCHEDULER_ABC_INTERLOCK", "ABC MSHR interlocked due to pre-emption") if (!params.lastLevel) params.ccover(mshr_stall_bc && bc_mshr.io.status.valid, "SCHEDULER_BC_INTERLOCK", "BC MSHR interlocked due to pre-emption") // Consider scheduling an MSHR only if all the resources it requires are available val mshr_request = Cat((mshrs zip mshr_stall).map { case (m, s) => m.io.schedule.valid && !s && (sourceA.io.req.ready || !m.io.schedule.bits.a.valid) && (sourceB.io.req.ready || !m.io.schedule.bits.b.valid) && (sourceC.io.req.ready || !m.io.schedule.bits.c.valid) && (sourceD.io.req.ready || !m.io.schedule.bits.d.valid) && (sourceE.io.req.ready || !m.io.schedule.bits.e.valid) && (sourceX.io.req.ready || !m.io.schedule.bits.x.valid) && (directory.io.write.ready || !m.io.schedule.bits.dir.valid) }.reverse) // Round-robin arbitration of MSHRs val robin_filter = RegInit(0.U(params.mshrs.W)) val robin_request = Cat(mshr_request, mshr_request & robin_filter) val mshr_selectOH2 = ~(leftOR(robin_request) << 1) & robin_request val mshr_selectOH = mshr_selectOH2(2*params.mshrs-1, params.mshrs) | mshr_selectOH2(params.mshrs-1, 0) val mshr_select = OHToUInt(mshr_selectOH) val schedule = Mux1H(mshr_selectOH, mshrs.map(_.io.schedule.bits)) val scheduleTag = Mux1H(mshr_selectOH, mshrs.map(_.io.status.bits.tag)) val scheduleSet = Mux1H(mshr_selectOH, mshrs.map(_.io.status.bits.set)) // When an MSHR wins the schedule, it has lowest priority next time when (mshr_request.orR) { robin_filter := ~rightOR(mshr_selectOH) } // Fill in which MSHR sends the request schedule.a.bits.source := mshr_select schedule.c.bits.source := Mux(schedule.c.bits.opcode(1), mshr_select, 0.U) // only set for Release[Data] not ProbeAck[Data] schedule.d.bits.sink := mshr_select sourceA.io.req.valid := schedule.a.valid sourceB.io.req.valid := schedule.b.valid sourceC.io.req.valid := schedule.c.valid sourceD.io.req.valid := schedule.d.valid sourceE.io.req.valid := schedule.e.valid sourceX.io.req.valid := schedule.x.valid sourceA.io.req.bits.viewAsSupertype(chiselTypeOf(schedule.a.bits)) := schedule.a.bits sourceB.io.req.bits.viewAsSupertype(chiselTypeOf(schedule.b.bits)) := schedule.b.bits sourceC.io.req.bits.viewAsSupertype(chiselTypeOf(schedule.c.bits)) := schedule.c.bits sourceD.io.req.bits.viewAsSupertype(chiselTypeOf(schedule.d.bits)) := schedule.d.bits sourceE.io.req.bits.viewAsSupertype(chiselTypeOf(schedule.e.bits)) := schedule.e.bits sourceX.io.req.bits.viewAsSupertype(chiselTypeOf(schedule.x.bits)) := schedule.x.bits directory.io.write.valid := schedule.dir.valid directory.io.write.bits.viewAsSupertype(chiselTypeOf(schedule.dir.bits)) := schedule.dir.bits // Forward meta-data changes from nested transaction completion val select_c = mshr_selectOH(params.mshrs-1) val select_bc = mshr_selectOH(params.mshrs-2) nestedwb.set := Mux(select_c, c_mshr.io.status.bits.set, bc_mshr.io.status.bits.set) nestedwb.tag := Mux(select_c, c_mshr.io.status.bits.tag, bc_mshr.io.status.bits.tag) nestedwb.b_toN := select_bc && bc_mshr.io.schedule.bits.dir.valid && bc_mshr.io.schedule.bits.dir.bits.data.state === MetaData.INVALID nestedwb.b_toB := select_bc && bc_mshr.io.schedule.bits.dir.valid && bc_mshr.io.schedule.bits.dir.bits.data.state === MetaData.BRANCH nestedwb.b_clr_dirty := select_bc && bc_mshr.io.schedule.bits.dir.valid nestedwb.c_set_dirty := select_c && c_mshr.io.schedule.bits.dir.valid && c_mshr.io.schedule.bits.dir.bits.data.dirty // Pick highest priority request val request = Wire(Decoupled(new FullRequest(params))) request.valid := directory.io.ready && (sinkA.io.req.valid || sinkX.io.req.valid || sinkC.io.req.valid) request.bits := Mux(sinkC.io.req.valid, sinkC.io.req.bits, Mux(sinkX.io.req.valid, sinkX.io.req.bits, sinkA.io.req.bits)) sinkC.io.req.ready := directory.io.ready && request.ready sinkX.io.req.ready := directory.io.ready && request.ready && !sinkC.io.req.valid sinkA.io.req.ready := directory.io.ready && request.ready && !sinkC.io.req.valid && !sinkX.io.req.valid // If no MSHR has been assigned to this set, we need to allocate one val setMatches = Cat(mshrs.map { m => m.io.status.valid && m.io.status.bits.set === request.bits.set }.reverse) val alloc = !setMatches.orR // NOTE: no matches also means no BC or C pre-emption on this set // If a same-set MSHR says that requests of this type must be blocked (for bounded time), do it val blockB = Mux1H(setMatches, mshrs.map(_.io.status.bits.blockB)) && request.bits.prio(1) val blockC = Mux1H(setMatches, mshrs.map(_.io.status.bits.blockC)) && request.bits.prio(2) // If a same-set MSHR says that requests of this type must be handled out-of-band, use special BC|C MSHR // ... these special MSHRs interlock the MSHR that said it should be pre-empted. val nestB = Mux1H(setMatches, mshrs.map(_.io.status.bits.nestB)) && request.bits.prio(1) val nestC = Mux1H(setMatches, mshrs.map(_.io.status.bits.nestC)) && request.bits.prio(2) // Prevent priority inversion; we may not queue to MSHRs beyond our level val prioFilter = Cat(request.bits.prio(2), !request.bits.prio(0), ~0.U((params.mshrs-2).W)) val lowerMatches = setMatches & prioFilter // If we match an MSHR <= our priority that neither blocks nor nests us, queue to it. val queue = lowerMatches.orR && !nestB && !nestC && !blockB && !blockC if (!params.lastLevel) { params.ccover(request.valid && blockB, "SCHEDULER_BLOCKB", "Interlock B request while resolving set conflict") params.ccover(request.valid && nestB, "SCHEDULER_NESTB", "Priority escalation from channel B") } if (!params.firstLevel) { params.ccover(request.valid && blockC, "SCHEDULER_BLOCKC", "Interlock C request while resolving set conflict") params.ccover(request.valid && nestC, "SCHEDULER_NESTC", "Priority escalation from channel C") } params.ccover(request.valid && queue, "SCHEDULER_SECONDARY", "Enqueue secondary miss") // It might happen that lowerMatches has >1 bit if the two special MSHRs are in-use // We want to Q to the highest matching priority MSHR. val lowerMatches1 = Mux(lowerMatches(params.mshrs-1), 1.U << (params.mshrs-1), Mux(lowerMatches(params.mshrs-2), 1.U << (params.mshrs-2), lowerMatches)) // If this goes to the scheduled MSHR, it may need to be bypassed // Alternatively, the MSHR may be refilled from a request queued in the ListBuffer val selected_requests = Cat(mshr_selectOH, mshr_selectOH, mshr_selectOH) & requests.io.valid val a_pop = selected_requests((0 + 1) * params.mshrs - 1, 0 * params.mshrs).orR val b_pop = selected_requests((1 + 1) * params.mshrs - 1, 1 * params.mshrs).orR val c_pop = selected_requests((2 + 1) * params.mshrs - 1, 2 * params.mshrs).orR val bypassMatches = (mshr_selectOH & lowerMatches1).orR && Mux(c_pop || request.bits.prio(2), !c_pop, Mux(b_pop || request.bits.prio(1), !b_pop, !a_pop)) val may_pop = a_pop || b_pop || c_pop val bypass = request.valid && queue && bypassMatches val will_reload = schedule.reload && (may_pop || bypass) val will_pop = schedule.reload && may_pop && !bypass params.ccover(mshr_selectOH.orR && bypass, "SCHEDULER_BYPASS", "Bypass new request directly to conflicting MSHR") params.ccover(mshr_selectOH.orR && will_reload, "SCHEDULER_RELOAD", "Back-to-back service of two requests") params.ccover(mshr_selectOH.orR && will_pop, "SCHEDULER_POP", "Service of a secondary miss") // Repeat the above logic, but without the fan-in mshrs.zipWithIndex.foreach { case (m, i) => val sel = mshr_selectOH(i) m.io.schedule.ready := sel val a_pop = requests.io.valid(params.mshrs * 0 + i) val b_pop = requests.io.valid(params.mshrs * 1 + i) val c_pop = requests.io.valid(params.mshrs * 2 + i) val bypassMatches = lowerMatches1(i) && Mux(c_pop || request.bits.prio(2), !c_pop, Mux(b_pop || request.bits.prio(1), !b_pop, !a_pop)) val may_pop = a_pop || b_pop || c_pop val bypass = request.valid && queue && bypassMatches val will_reload = m.io.schedule.bits.reload && (may_pop || bypass) m.io.allocate.bits.viewAsSupertype(chiselTypeOf(requests.io.data)) := Mux(bypass, WireInit(new QueuedRequest(params), init = request.bits), requests.io.data) m.io.allocate.bits.set := m.io.status.bits.set m.io.allocate.bits.repeat := m.io.allocate.bits.tag === m.io.status.bits.tag m.io.allocate.valid := sel && will_reload } // Determine which of the queued requests to pop (supposing will_pop) val prio_requests = ~(~requests.io.valid | (requests.io.valid >> params.mshrs) | (requests.io.valid >> 2*params.mshrs)) val pop_index = OHToUInt(Cat(mshr_selectOH, mshr_selectOH, mshr_selectOH) & prio_requests) requests.io.pop.valid := will_pop requests.io.pop.bits := pop_index // Reload from the Directory if the next MSHR operation changes tags val lb_tag_mismatch = scheduleTag =/= requests.io.data.tag val mshr_uses_directory_assuming_no_bypass = schedule.reload && may_pop && lb_tag_mismatch val mshr_uses_directory_for_lb = will_pop && lb_tag_mismatch val mshr_uses_directory = will_reload && scheduleTag =/= Mux(bypass, request.bits.tag, requests.io.data.tag) // Is there an MSHR free for this request? val mshr_validOH = Cat(mshrs.map(_.io.status.valid).reverse) val mshr_free = (~mshr_validOH & prioFilter).orR // Fanout the request to the appropriate handler (if any) val bypassQueue = schedule.reload && bypassMatches val request_alloc_cases = (alloc && !mshr_uses_directory_assuming_no_bypass && mshr_free) || (nestB && !mshr_uses_directory_assuming_no_bypass && !bc_mshr.io.status.valid && !c_mshr.io.status.valid) || (nestC && !mshr_uses_directory_assuming_no_bypass && !c_mshr.io.status.valid) request.ready := request_alloc_cases || (queue && (bypassQueue || requests.io.push.ready)) val alloc_uses_directory = request.valid && request_alloc_cases // When a request goes through, it will need to hit the Directory directory.io.read.valid := mshr_uses_directory || alloc_uses_directory directory.io.read.bits.set := Mux(mshr_uses_directory_for_lb, scheduleSet, request.bits.set) directory.io.read.bits.tag := Mux(mshr_uses_directory_for_lb, requests.io.data.tag, request.bits.tag) // Enqueue the request if not bypassed directly into an MSHR requests.io.push.valid := request.valid && queue && !bypassQueue requests.io.push.bits.data := request.bits requests.io.push.bits.index := Mux1H( request.bits.prio, Seq( OHToUInt(lowerMatches1 << params.mshrs*0), OHToUInt(lowerMatches1 << params.mshrs*1), OHToUInt(lowerMatches1 << params.mshrs*2))) val mshr_insertOH = ~(leftOR(~mshr_validOH) << 1) & ~mshr_validOH & prioFilter (mshr_insertOH.asBools zip mshrs) map { case (s, m) => when (request.valid && alloc && s && !mshr_uses_directory_assuming_no_bypass) { m.io.allocate.valid := true.B m.io.allocate.bits.viewAsSupertype(chiselTypeOf(request.bits)) := request.bits m.io.allocate.bits.repeat := false.B } } when (request.valid && nestB && !bc_mshr.io.status.valid && !c_mshr.io.status.valid && !mshr_uses_directory_assuming_no_bypass) { bc_mshr.io.allocate.valid := true.B bc_mshr.io.allocate.bits.viewAsSupertype(chiselTypeOf(request.bits)) := request.bits bc_mshr.io.allocate.bits.repeat := false.B assert (!request.bits.prio(0)) } bc_mshr.io.allocate.bits.prio(0) := false.B when (request.valid && nestC && !c_mshr.io.status.valid && !mshr_uses_directory_assuming_no_bypass) { c_mshr.io.allocate.valid := true.B c_mshr.io.allocate.bits.viewAsSupertype(chiselTypeOf(request.bits)) := request.bits c_mshr.io.allocate.bits.repeat := false.B assert (!request.bits.prio(0)) assert (!request.bits.prio(1)) } c_mshr.io.allocate.bits.prio(0) := false.B c_mshr.io.allocate.bits.prio(1) := false.B // Fanout the result of the Directory lookup val dirTarget = Mux(alloc, mshr_insertOH, Mux(nestB,(BigInt(1) << (params.mshrs-2)).U,(BigInt(1) << (params.mshrs-1)).U)) val directoryFanout = params.dirReg(RegNext(Mux(mshr_uses_directory, mshr_selectOH, Mux(alloc_uses_directory, dirTarget, 0.U)))) mshrs.zipWithIndex.foreach { case (m, i) => m.io.directory.valid := directoryFanout(i) m.io.directory.bits := directory.io.result.bits } // MSHR response meta-data fetch sinkC.io.way := Mux(bc_mshr.io.status.valid && bc_mshr.io.status.bits.set === sinkC.io.set, bc_mshr.io.status.bits.way, Mux1H(abc_mshrs.map(m => m.io.status.valid && m.io.status.bits.set === sinkC.io.set), abc_mshrs.map(_.io.status.bits.way))) sinkD.io.way := VecInit(mshrs.map(_.io.status.bits.way))(sinkD.io.source) sinkD.io.set := VecInit(mshrs.map(_.io.status.bits.set))(sinkD.io.source) // Beat buffer connections between components sinkA.io.pb_pop <> sourceD.io.pb_pop sourceD.io.pb_beat := sinkA.io.pb_beat sinkC.io.rel_pop <> sourceD.io.rel_pop sourceD.io.rel_beat := sinkC.io.rel_beat // BankedStore ports bankedStore.io.sinkC_adr <> sinkC.io.bs_adr bankedStore.io.sinkC_dat := sinkC.io.bs_dat bankedStore.io.sinkD_adr <> sinkD.io.bs_adr bankedStore.io.sinkD_dat := sinkD.io.bs_dat bankedStore.io.sourceC_adr <> sourceC.io.bs_adr bankedStore.io.sourceD_radr <> sourceD.io.bs_radr bankedStore.io.sourceD_wadr <> sourceD.io.bs_wadr bankedStore.io.sourceD_wdat := sourceD.io.bs_wdat sourceC.io.bs_dat := bankedStore.io.sourceC_dat sourceD.io.bs_rdat := bankedStore.io.sourceD_rdat // SourceD data hazard interlock sourceD.io.evict_req := sourceC.io.evict_req sourceD.io.grant_req := sinkD .io.grant_req sourceC.io.evict_safe := sourceD.io.evict_safe sinkD .io.grant_safe := sourceD.io.grant_safe private def afmt(x: AddressSet) = s"""{"base":${x.base},"mask":${x.mask}}""" private def addresses = params.inner.manager.managers.flatMap(_.address).map(afmt _).mkString(",") private def setBits = params.addressMapping.drop(params.offsetBits).take(params.setBits).mkString(",") private def tagBits = params.addressMapping.drop(params.offsetBits + params.setBits).take(params.tagBits).mkString(",") private def simple = s""""reset":"${reset.pathName}","tagBits":[${tagBits}],"setBits":[${setBits}],"blockBytes":${params.cache.blockBytes},"ways":${params.cache.ways}""" def json: String = s"""{"addresses":[${addresses}],${simple},"directory":${directory.json},"subbanks":${bankedStore.json}}""" }

module InclusiveCacheBankScheduler( // @[Scheduler.scala:27:7] input clock, // @[Scheduler.scala:27:7] input reset, // @[Scheduler.scala:27:7] output io_in_a_ready, // @[Scheduler.scala:29:14] input io_in_a_valid, // @[Scheduler.scala:29:14] input [2:0] io_in_a_bits_opcode, // @[Scheduler.scala:29:14] input [2:0] io_in_a_bits_param, // @[Scheduler.scala:29:14] input [2:0] io_in_a_bits_size, // @[Scheduler.scala:29:14] input [5:0] io_in_a_bits_source, // @[Scheduler.scala:29:14] input [31:0] io_in_a_bits_address, // @[Scheduler.scala:29:14] input [7:0] io_in_a_bits_mask, // @[Scheduler.scala:29:14] input [63:0] io_in_a_bits_data, // @[Scheduler.scala:29:14] input io_in_a_bits_corrupt, // @[Scheduler.scala:29:14] input io_in_b_ready, // @[Scheduler.scala:29:14] output io_in_b_valid, // @[Scheduler.scala:29:14] output [1:0] io_in_b_bits_param, // @[Scheduler.scala:29:14] output [5:0] io_in_b_bits_source, // @[Scheduler.scala:29:14] output [31:0] io_in_b_bits_address, // @[Scheduler.scala:29:14] output io_in_c_ready, // @[Scheduler.scala:29:14] input io_in_c_valid, // @[Scheduler.scala:29:14] input [2:0] io_in_c_bits_opcode, // @[Scheduler.scala:29:14] input [2:0] io_in_c_bits_param, // @[Scheduler.scala:29:14] input [2:0] io_in_c_bits_size, // @[Scheduler.scala:29:14] input [5:0] io_in_c_bits_source, // @[Scheduler.scala:29:14] input [31:0] io_in_c_bits_address, // @[Scheduler.scala:29:14] input [63:0] io_in_c_bits_data, // @[Scheduler.scala:29:14] input io_in_c_bits_corrupt, // @[Scheduler.scala:29:14] input io_in_d_ready, // @[Scheduler.scala:29:14] output io_in_d_valid, // @[Scheduler.scala:29:14] output [2:0] io_in_d_bits_opcode, // @[Scheduler.scala:29:14] output [1:0] io_in_d_bits_param, // @[Scheduler.scala:29:14] output [2:0] io_in_d_bits_size, // @[Scheduler.scala:29:14] output [5:0] io_in_d_bits_source, // @[Scheduler.scala:29:14] output [2:0] io_in_d_bits_sink, // @[Scheduler.scala:29:14] output io_in_d_bits_denied, // @[Scheduler.scala:29:14] output [63:0] io_in_d_bits_data, // @[Scheduler.scala:29:14] output io_in_d_bits_corrupt, // @[Scheduler.scala:29:14] input io_in_e_valid, // @[Scheduler.scala:29:14] input [2:0] io_in_e_bits_sink, // @[Scheduler.scala:29:14] input io_out_a_ready, // @[Scheduler.scala:29:14] output io_out_a_valid, // @[Scheduler.scala:29:14] output [2:0] io_out_a_bits_opcode, // @[Scheduler.scala:29:14] output [2:0] io_out_a_bits_param, // @[Scheduler.scala:29:14] output [2:0] io_out_a_bits_size, // @[Scheduler.scala:29:14] output [2:0] io_out_a_bits_source, // @[Scheduler.scala:29:14] output [31:0] io_out_a_bits_address, // @[Scheduler.scala:29:14] output [7:0] io_out_a_bits_mask, // @[Scheduler.scala:29:14] output [63:0] io_out_a_bits_data, // @[Scheduler.scala:29:14] output io_out_a_bits_corrupt, // @[Scheduler.scala:29:14] input io_out_c_ready, // @[Scheduler.scala:29:14] output io_out_c_valid, // @[Scheduler.scala:29:14] output [2:0] io_out_c_bits_opcode, // @[Scheduler.scala:29:14] output [2:0] io_out_c_bits_param, // @[Scheduler.scala:29:14] output [2:0] io_out_c_bits_size, // @[Scheduler.scala:29:14] output [2:0] io_out_c_bits_source, // @[Scheduler.scala:29:14] output [31:0] io_out_c_bits_address, // @[Scheduler.scala:29:14] output [63:0] io_out_c_bits_data, // @[Scheduler.scala:29:14] output io_out_c_bits_corrupt, // @[Scheduler.scala:29:14] output io_out_d_ready, // @[Scheduler.scala:29:14] input io_out_d_valid, // @[Scheduler.scala:29:14] input [2:0] io_out_d_bits_opcode, // @[Scheduler.scala:29:14] input [1:0] io_out_d_bits_param, // @[Scheduler.scala:29:14] input [2:0] io_out_d_bits_size, // @[Scheduler.scala:29:14] input [2:0] io_out_d_bits_source, // @[Scheduler.scala:29:14] input [2:0] io_out_d_bits_sink, // @[Scheduler.scala:29:14] input io_out_d_bits_denied, // @[Scheduler.scala:29:14] input [63:0] io_out_d_bits_data, // @[Scheduler.scala:29:14] input io_out_d_bits_corrupt, // @[Scheduler.scala:29:14] output io_out_e_valid, // @[Scheduler.scala:29:14] output [2:0] io_out_e_bits_sink, // @[Scheduler.scala:29:14] output io_req_ready, // @[Scheduler.scala:29:14] input io_req_valid, // @[Scheduler.scala:29:14] input [31:0] io_req_bits_address, // @[Scheduler.scala:29:14] output io_resp_valid // @[Scheduler.scala:29:14] ); wire [12:0] mshrs_6_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70, :295:103, :297:73] wire [12:0] mshrs_5_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70, :287:131, :289:74] wire [12:0] mshrs_4_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70] wire [12:0] mshrs_3_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70] wire [12:0] mshrs_2_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70] wire [12:0] mshrs_1_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70] wire [12:0] mshrs_0_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70] wire [5:0] request_bits_put; // @[Scheduler.scala:163:21] wire [5:0] request_bits_offset; // @[Scheduler.scala:163:21] wire [12:0] request_bits_tag; // @[Scheduler.scala:163:21] wire [5:0] request_bits_source; // @[Scheduler.scala:163:21] wire [2:0] request_bits_size; // @[Scheduler.scala:163:21] wire [2:0] request_bits_param; // @[Scheduler.scala:163:21] wire [2:0] request_bits_opcode; // @[Scheduler.scala:163:21] wire request_bits_control; // @[Scheduler.scala:163:21] wire request_bits_prio_2; // @[Scheduler.scala:163:21] wire request_bits_prio_0; // @[Scheduler.scala:163:21] wire _mshrs_6_io_status_valid; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_6_io_status_bits_set; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_6_io_status_bits_tag; // @[Scheduler.scala:71:46] wire _mshrs_6_io_status_bits_blockB; // @[Scheduler.scala:71:46] wire _mshrs_6_io_status_bits_nestB; // @[Scheduler.scala:71:46] wire _mshrs_6_io_status_bits_blockC; // @[Scheduler.scala:71:46] wire _mshrs_6_io_status_bits_nestC; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_6_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_6_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_6_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_6_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_6_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_6_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_6_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_6_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_6_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_6_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_6_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_6_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_6_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_6_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_6_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_6_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_6_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_6_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_6_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_6_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_6_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_6_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_6_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_6_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_6_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_6_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_6_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_reload; // @[Scheduler.scala:71:46] wire _mshrs_5_io_status_valid; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_5_io_status_bits_set; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_5_io_status_bits_tag; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_5_io_status_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_5_io_status_bits_blockB; // @[Scheduler.scala:71:46] wire _mshrs_5_io_status_bits_nestB; // @[Scheduler.scala:71:46] wire _mshrs_5_io_status_bits_blockC; // @[Scheduler.scala:71:46] wire _mshrs_5_io_status_bits_nestC; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_valid; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_5_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_5_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_5_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_5_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_5_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_5_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_5_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_5_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_5_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_5_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_5_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_5_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_5_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_5_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_5_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_5_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_5_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_5_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_5_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_5_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_5_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_5_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_5_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_5_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_5_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_5_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_5_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_reload; // @[Scheduler.scala:71:46] wire _mshrs_4_io_status_valid; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_4_io_status_bits_set; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_4_io_status_bits_tag; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_4_io_status_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_4_io_status_bits_blockB; // @[Scheduler.scala:71:46] wire _mshrs_4_io_status_bits_nestB; // @[Scheduler.scala:71:46] wire _mshrs_4_io_status_bits_blockC; // @[Scheduler.scala:71:46] wire _mshrs_4_io_status_bits_nestC; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_valid; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_4_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_4_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_4_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_4_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_4_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_4_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_4_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_4_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_4_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_4_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_4_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_4_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_4_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_4_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_4_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_4_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_4_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_4_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_4_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_4_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_4_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_4_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_4_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_4_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_4_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_4_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_4_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_reload; // @[Scheduler.scala:71:46] wire _mshrs_3_io_status_valid; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_3_io_status_bits_set; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_3_io_status_bits_tag; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_3_io_status_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_3_io_status_bits_blockB; // @[Scheduler.scala:71:46] wire _mshrs_3_io_status_bits_nestB; // @[Scheduler.scala:71:46] wire _mshrs_3_io_status_bits_blockC; // @[Scheduler.scala:71:46] wire _mshrs_3_io_status_bits_nestC; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_valid; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_3_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_3_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_3_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_3_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_3_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_3_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_3_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_3_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_3_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_3_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_3_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_3_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_3_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_3_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_3_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_3_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_3_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_3_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_3_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_3_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_3_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_3_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_3_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_3_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_3_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_3_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_3_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_reload; // @[Scheduler.scala:71:46] wire _mshrs_2_io_status_valid; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_2_io_status_bits_set; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_2_io_status_bits_tag; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_2_io_status_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_2_io_status_bits_blockB; // @[Scheduler.scala:71:46] wire _mshrs_2_io_status_bits_nestB; // @[Scheduler.scala:71:46] wire _mshrs_2_io_status_bits_blockC; // @[Scheduler.scala:71:46] wire _mshrs_2_io_status_bits_nestC; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_valid; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_2_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_2_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_2_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_2_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_2_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_2_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_2_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_2_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_2_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_2_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_2_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_2_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_2_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_2_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_2_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_2_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_2_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_2_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_2_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_2_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_2_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_2_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_2_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_2_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_2_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_2_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_2_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_reload; // @[Scheduler.scala:71:46] wire _mshrs_1_io_status_valid; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_1_io_status_bits_set; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_1_io_status_bits_tag; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_1_io_status_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_1_io_status_bits_blockB; // @[Scheduler.scala:71:46] wire _mshrs_1_io_status_bits_nestB; // @[Scheduler.scala:71:46] wire _mshrs_1_io_status_bits_blockC; // @[Scheduler.scala:71:46] wire _mshrs_1_io_status_bits_nestC; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_valid; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_1_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_1_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_1_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_1_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_1_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_1_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_1_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_1_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_1_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_1_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_1_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_1_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_1_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_1_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_1_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_1_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_1_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_1_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_1_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_1_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_1_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_1_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_1_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_1_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_1_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_1_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_1_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_reload; // @[Scheduler.scala:71:46] wire _mshrs_0_io_status_valid; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_0_io_status_bits_set; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_0_io_status_bits_tag; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_0_io_status_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_0_io_status_bits_blockB; // @[Scheduler.scala:71:46] wire _mshrs_0_io_status_bits_nestB; // @[Scheduler.scala:71:46] wire _mshrs_0_io_status_bits_blockC; // @[Scheduler.scala:71:46] wire _mshrs_0_io_status_bits_nestC; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_valid; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_0_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_0_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_0_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_0_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_0_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_0_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_0_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_0_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_0_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_0_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_0_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_0_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_0_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_0_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_0_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_0_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_0_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_0_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_0_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_0_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_0_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_0_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_0_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_0_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_0_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_0_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_0_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_reload; // @[Scheduler.scala:71:46] wire _requests_io_push_ready; // @[Scheduler.scala:70:24] wire [20:0] _requests_io_valid; // @[Scheduler.scala:70:24] wire _requests_io_data_prio_0; // @[Scheduler.scala:70:24] wire _requests_io_data_prio_1; // @[Scheduler.scala:70:24] wire _requests_io_data_prio_2; // @[Scheduler.scala:70:24] wire _requests_io_data_control; // @[Scheduler.scala:70:24] wire [2:0] _requests_io_data_opcode; // @[Scheduler.scala:70:24] wire [2:0] _requests_io_data_param; // @[Scheduler.scala:70:24] wire [2:0] _requests_io_data_size; // @[Scheduler.scala:70:24] wire [5:0] _requests_io_data_source; // @[Scheduler.scala:70:24] wire [12:0] _requests_io_data_tag; // @[Scheduler.scala:70:24] wire [5:0] _requests_io_data_offset; // @[Scheduler.scala:70:24] wire [5:0] _requests_io_data_put; // @[Scheduler.scala:70:24] wire _bankedStore_io_sinkC_adr_ready; // @[Scheduler.scala:69:27] wire _bankedStore_io_sinkD_adr_ready; // @[Scheduler.scala:69:27] wire _bankedStore_io_sourceC_adr_ready; // @[Scheduler.scala:69:27] wire [63:0] _bankedStore_io_sourceC_dat_data; // @[Scheduler.scala:69:27] wire _bankedStore_io_sourceD_radr_ready; // @[Scheduler.scala:69:27] wire [63:0] _bankedStore_io_sourceD_rdat_data; // @[Scheduler.scala:69:27] wire _bankedStore_io_sourceD_wadr_ready; // @[Scheduler.scala:69:27] wire _directory_io_write_ready; // @[Scheduler.scala:68:25] wire _directory_io_result_bits_dirty; // @[Scheduler.scala:68:25] wire [1:0] _directory_io_result_bits_state; // @[Scheduler.scala:68:25] wire [1:0] _directory_io_result_bits_clients; // @[Scheduler.scala:68:25] wire [12:0] _directory_io_result_bits_tag; // @[Scheduler.scala:68:25] wire _directory_io_result_bits_hit; // @[Scheduler.scala:68:25] wire [2:0] _directory_io_result_bits_way; // @[Scheduler.scala:68:25] wire _directory_io_ready; // @[Scheduler.scala:68:25] wire _sinkX_io_req_valid; // @[Scheduler.scala:58:21] wire [12:0] _sinkX_io_req_bits_tag; // @[Scheduler.scala:58:21] wire [9:0] _sinkX_io_req_bits_set; // @[Scheduler.scala:58:21] wire _sinkE_io_resp_valid; // @[Scheduler.scala:57:21] wire [2:0] _sinkE_io_resp_bits_sink; // @[Scheduler.scala:57:21] wire _sinkD_io_resp_valid; // @[Scheduler.scala:56:21] wire _sinkD_io_resp_bits_last; // @[Scheduler.scala:56:21] wire [2:0] _sinkD_io_resp_bits_opcode; // @[Scheduler.scala:56:21] wire [2:0] _sinkD_io_resp_bits_param; // @[Scheduler.scala:56:21] wire [2:0] _sinkD_io_resp_bits_source; // @[Scheduler.scala:56:21] wire [2:0] _sinkD_io_resp_bits_sink; // @[Scheduler.scala:56:21] wire _sinkD_io_resp_bits_denied; // @[Scheduler.scala:56:21] wire [2:0] _sinkD_io_source; // @[Scheduler.scala:56:21] wire _sinkD_io_bs_adr_valid; // @[Scheduler.scala:56:21] wire _sinkD_io_bs_adr_bits_noop; // @[Scheduler.scala:56:21] wire [2:0] _sinkD_io_bs_adr_bits_way; // @[Scheduler.scala:56:21] wire [9:0] _sinkD_io_bs_adr_bits_set; // @[Scheduler.scala:56:21] wire [2:0] _sinkD_io_bs_adr_bits_beat; // @[Scheduler.scala:56:21] wire [63:0] _sinkD_io_bs_dat_data; // @[Scheduler.scala:56:21] wire [9:0] _sinkD_io_grant_req_set; // @[Scheduler.scala:56:21] wire [2:0] _sinkD_io_grant_req_way; // @[Scheduler.scala:56:21] wire _sinkC_io_req_valid; // @[Scheduler.scala:55:21] wire [2:0] _sinkC_io_req_bits_opcode; // @[Scheduler.scala:55:21] wire [2:0] _sinkC_io_req_bits_param; // @[Scheduler.scala:55:21] wire [2:0] _sinkC_io_req_bits_size; // @[Scheduler.scala:55:21] wire [5:0] _sinkC_io_req_bits_source; // @[Scheduler.scala:55:21] wire [12:0] _sinkC_io_req_bits_tag; // @[Scheduler.scala:55:21] wire [5:0] _sinkC_io_req_bits_offset; // @[Scheduler.scala:55:21] wire [5:0] _sinkC_io_req_bits_put; // @[Scheduler.scala:55:21] wire [9:0] _sinkC_io_req_bits_set; // @[Scheduler.scala:55:21] wire _sinkC_io_resp_valid; // @[Scheduler.scala:55:21] wire _sinkC_io_resp_bits_last; // @[Scheduler.scala:55:21] wire [9:0] _sinkC_io_resp_bits_set; // @[Scheduler.scala:55:21] wire [12:0] _sinkC_io_resp_bits_tag; // @[Scheduler.scala:55:21] wire [5:0] _sinkC_io_resp_bits_source; // @[Scheduler.scala:55:21] wire [2:0] _sinkC_io_resp_bits_param; // @[Scheduler.scala:55:21] wire _sinkC_io_resp_bits_data; // @[Scheduler.scala:55:21] wire [9:0] _sinkC_io_set; // @[Scheduler.scala:55:21] wire _sinkC_io_bs_adr_valid; // @[Scheduler.scala:55:21] wire _sinkC_io_bs_adr_bits_noop; // @[Scheduler.scala:55:21] wire [2:0] _sinkC_io_bs_adr_bits_way; // @[Scheduler.scala:55:21] wire [9:0] _sinkC_io_bs_adr_bits_set; // @[Scheduler.scala:55:21] wire [2:0] _sinkC_io_bs_adr_bits_beat; // @[Scheduler.scala:55:21] wire _sinkC_io_bs_adr_bits_mask; // @[Scheduler.scala:55:21] wire [63:0] _sinkC_io_bs_dat_data; // @[Scheduler.scala:55:21] wire _sinkC_io_rel_pop_ready; // @[Scheduler.scala:55:21] wire [63:0] _sinkC_io_rel_beat_data; // @[Scheduler.scala:55:21] wire _sinkC_io_rel_beat_corrupt; // @[Scheduler.scala:55:21] wire _sinkA_io_req_valid; // @[Scheduler.scala:54:21] wire [2:0] _sinkA_io_req_bits_opcode; // @[Scheduler.scala:54:21] wire [2:0] _sinkA_io_req_bits_param; // @[Scheduler.scala:54:21] wire [2:0] _sinkA_io_req_bits_size; // @[Scheduler.scala:54:21] wire [5:0] _sinkA_io_req_bits_source; // @[Scheduler.scala:54:21] wire [12:0] _sinkA_io_req_bits_tag; // @[Scheduler.scala:54:21] wire [5:0] _sinkA_io_req_bits_offset; // @[Scheduler.scala:54:21] wire [5:0] _sinkA_io_req_bits_put; // @[Scheduler.scala:54:21] wire [9:0] _sinkA_io_req_bits_set; // @[Scheduler.scala:54:21] wire _sinkA_io_pb_pop_ready; // @[Scheduler.scala:54:21] wire [63:0] _sinkA_io_pb_beat_data; // @[Scheduler.scala:54:21] wire [7:0] _sinkA_io_pb_beat_mask; // @[Scheduler.scala:54:21] wire _sinkA_io_pb_beat_corrupt; // @[Scheduler.scala:54:21] wire _sourceX_io_req_ready; // @[Scheduler.scala:45:23] wire _sourceE_io_req_ready; // @[Scheduler.scala:44:23] wire _sourceD_io_req_ready; // @[Scheduler.scala:43:23] wire _sourceD_io_pb_pop_valid; // @[Scheduler.scala:43:23] wire [5:0] _sourceD_io_pb_pop_bits_index; // @[Scheduler.scala:43:23] wire _sourceD_io_pb_pop_bits_last; // @[Scheduler.scala:43:23] wire _sourceD_io_rel_pop_valid; // @[Scheduler.scala:43:23] wire [5:0] _sourceD_io_rel_pop_bits_index; // @[Scheduler.scala:43:23] wire _sourceD_io_rel_pop_bits_last; // @[Scheduler.scala:43:23] wire _sourceD_io_bs_radr_valid; // @[Scheduler.scala:43:23] wire [2:0] _sourceD_io_bs_radr_bits_way; // @[Scheduler.scala:43:23] wire [9:0] _sourceD_io_bs_radr_bits_set; // @[Scheduler.scala:43:23] wire [2:0] _sourceD_io_bs_radr_bits_beat; // @[Scheduler.scala:43:23] wire _sourceD_io_bs_radr_bits_mask; // @[Scheduler.scala:43:23] wire _sourceD_io_bs_wadr_valid; // @[Scheduler.scala:43:23] wire [2:0] _sourceD_io_bs_wadr_bits_way; // @[Scheduler.scala:43:23] wire [9:0] _sourceD_io_bs_wadr_bits_set; // @[Scheduler.scala:43:23] wire [2:0] _sourceD_io_bs_wadr_bits_beat; // @[Scheduler.scala:43:23] wire _sourceD_io_bs_wadr_bits_mask; // @[Scheduler.scala:43:23] wire [63:0] _sourceD_io_bs_wdat_data; // @[Scheduler.scala:43:23] wire _sourceD_io_evict_safe; // @[Scheduler.scala:43:23] wire _sourceD_io_grant_safe; // @[Scheduler.scala:43:23] wire _sourceC_io_req_ready; // @[Scheduler.scala:42:23] wire _sourceC_io_bs_adr_valid; // @[Scheduler.scala:42:23] wire [2:0] _sourceC_io_bs_adr_bits_way; // @[Scheduler.scala:42:23] wire [9:0] _sourceC_io_bs_adr_bits_set; // @[Scheduler.scala:42:23] wire [2:0] _sourceC_io_bs_adr_bits_beat; // @[Scheduler.scala:42:23] wire [9:0] _sourceC_io_evict_req_set; // @[Scheduler.scala:42:23] wire [2:0] _sourceC_io_evict_req_way; // @[Scheduler.scala:42:23] wire _sourceB_io_req_ready; // @[Scheduler.scala:41:23] wire _sourceA_io_req_ready; // @[Scheduler.scala:40:23] wire io_in_a_valid_0 = io_in_a_valid; // @[Scheduler.scala:27:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Scheduler.scala:27:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Scheduler.scala:27:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Scheduler.scala:27:7] wire [5:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Scheduler.scala:27:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Scheduler.scala:27:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Scheduler.scala:27:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Scheduler.scala:27:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Scheduler.scala:27:7] wire io_in_b_ready_0 = io_in_b_ready; // @[Scheduler.scala:27:7] wire io_in_c_valid_0 = io_in_c_valid; // @[Scheduler.scala:27:7] wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Scheduler.scala:27:7] wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Scheduler.scala:27:7] wire [2:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Scheduler.scala:27:7] wire [5:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Scheduler.scala:27:7] wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Scheduler.scala:27:7] wire [63:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Scheduler.scala:27:7] wire io_in_c_bits_corrupt_0 = io_in_c_bits_corrupt; // @[Scheduler.scala:27:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Scheduler.scala:27:7] wire io_in_e_valid_0 = io_in_e_valid; // @[Scheduler.scala:27:7] wire [2:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Scheduler.scala:27:7] wire io_out_a_ready_0 = io_out_a_ready; // @[Scheduler.scala:27:7] wire io_out_c_ready_0 = io_out_c_ready; // @[Scheduler.scala:27:7] wire io_out_d_valid_0 = io_out_d_valid; // @[Scheduler.scala:27:7] wire [2:0] io_out_d_bits_opcode_0 = io_out_d_bits_opcode; // @[Scheduler.scala:27:7] wire [1:0] io_out_d_bits_param_0 = io_out_d_bits_param; // @[Scheduler.scala:27:7] wire [2:0] io_out_d_bits_size_0 = io_out_d_bits_size; // @[Scheduler.scala:27:7] wire [2:0] io_out_d_bits_source_0 = io_out_d_bits_source; // @[Scheduler.scala:27:7] wire [2:0] io_out_d_bits_sink_0 = io_out_d_bits_sink; // @[Scheduler.scala:27:7] wire io_out_d_bits_denied_0 = io_out_d_bits_denied; // @[Scheduler.scala:27:7] wire [63:0] io_out_d_bits_data_0 = io_out_d_bits_data; // @[Scheduler.scala:27:7] wire io_out_d_bits_corrupt_0 = io_out_d_bits_corrupt; // @[Scheduler.scala:27:7] wire io_req_valid_0 = io_req_valid; // @[Scheduler.scala:27:7] wire [31:0] io_req_bits_address_0 = io_req_bits_address; // @[Scheduler.scala:27:7] wire io_in_b_bits_corrupt = 1'h0; // @[Scheduler.scala:27:7] wire io_out_b_valid = 1'h0; // @[Scheduler.scala:27:7] wire io_out_b_bits_corrupt = 1'h0; // @[Scheduler.scala:27:7] wire io_resp_bits_fail = 1'h0; // @[Scheduler.scala:27:7] wire schedule_x_bits_fail = 1'h0; // @[Mux.scala:30:73] wire _schedule_WIRE_11_bits_fail = 1'h0; // @[Mux.scala:30:73] wire _schedule_WIRE_12_fail = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_111 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_112 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_113 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_114 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_115 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_116 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_117 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_118 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_119 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_120 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_121 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_122 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_123 = 1'h0; // @[Mux.scala:30:73] wire _schedule_WIRE_13 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_324 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_325 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_338 = 1'h0; // @[Mux.scala:30:73] wire request_bits_prio_1 = 1'h0; // @[Scheduler.scala:163:21] wire _request_bits_T_prio_1 = 1'h0; // @[Scheduler.scala:166:22] wire _request_bits_T_prio_2 = 1'h0; // @[Scheduler.scala:166:22] wire _request_bits_T_1_prio_1 = 1'h0; // @[Scheduler.scala:165:22] wire blockB = 1'h0; // @[Scheduler.scala:175:70] wire nestB = 1'h0; // @[Scheduler.scala:179:70] wire _view__WIRE_prio_1 = 1'h0; // @[Scheduler.scala:233:95] wire _view__WIRE_1_prio_1 = 1'h0; // @[Scheduler.scala:233:95] wire _view__WIRE_2_prio_1 = 1'h0; // @[Scheduler.scala:233:95] wire _view__WIRE_3_prio_1 = 1'h0; // @[Scheduler.scala:233:95] wire _view__WIRE_4_prio_1 = 1'h0; // @[Scheduler.scala:233:95] wire _view__WIRE_5_prio_1 = 1'h0; // @[Scheduler.scala:233:95] wire _view__WIRE_6_prio_1 = 1'h0; // @[Scheduler.scala:233:95] wire _request_alloc_cases_T_4 = 1'h0; // @[Scheduler.scala:259:13] wire _request_alloc_cases_T_6 = 1'h0; // @[Scheduler.scala:259:56] wire _request_alloc_cases_T_8 = 1'h0; // @[Scheduler.scala:259:84] wire [2:0] io_in_b_bits_opcode = 3'h6; // @[Scheduler.scala:27:7] wire [2:0] io_in_b_bits_size = 3'h6; // @[Scheduler.scala:27:7] wire [7:0] io_in_b_bits_mask = 8'hFF; // @[Scheduler.scala:27:7] wire [63:0] io_in_b_bits_data = 64'h0; // @[Scheduler.scala:27:7] wire [63:0] io_out_b_bits_data = 64'h0; // @[Scheduler.scala:27:7] wire io_in_e_ready = 1'h1; // @[Scheduler.scala:27:7] wire io_out_b_ready = 1'h1; // @[Scheduler.scala:27:7] wire io_out_e_ready = 1'h1; // @[Scheduler.scala:27:7] wire io_resp_ready = 1'h1; // @[Scheduler.scala:27:7] wire _mshr_request_T_138 = 1'h1; // @[Scheduler.scala:107:28] wire _request_bits_T_prio_0 = 1'h1; // @[Scheduler.scala:166:22] wire _queue_T_1 = 1'h1; // @[Scheduler.scala:185:35] wire _queue_T_5 = 1'h1; // @[Scheduler.scala:185:55] wire [2:0] io_out_b_bits_opcode = 3'h0; // @[Scheduler.scala:27:7] wire [2:0] io_out_b_bits_size = 3'h0; // @[Scheduler.scala:27:7] wire [2:0] io_out_b_bits_source = 3'h0; // @[Scheduler.scala:27:7] wire [2:0] _schedule_WIRE_19_bits_sink = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_20_sink = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_189 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_190 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_191 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_192 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_193 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_194 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_195 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_196 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_197 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_198 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_199 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_200 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_201 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_23 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_38_bits_source = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_39_source = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_423 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_424 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_425 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_426 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_427 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_428 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_429 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_430 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_431 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_432 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_433 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_434 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_435 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_44 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_55_bits_source = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_56_source = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_553 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_554 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_555 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_556 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_557 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_558 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_559 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_560 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_561 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_562 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_563 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_564 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_565 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_58 = 3'h0; // @[Mux.scala:30:73] wire [1:0] io_out_b_bits_param = 2'h0; // @[Scheduler.scala:27:7] wire [31:0] io_out_b_bits_address = 32'h0; // @[Scheduler.scala:27:7] wire [7:0] io_out_b_bits_mask = 8'h0; // @[Scheduler.scala:27:7] wire [7:0] io_ways_0 = 8'h0; // @[Scheduler.scala:27:7] wire [7:0] io_ways_1 = 8'h0; // @[Scheduler.scala:27:7] wire [7:0] io_ways_2 = 8'h0; // @[Scheduler.scala:27:7] wire [7:0] io_ways_3 = 8'h0; // @[Scheduler.scala:27:7] wire [7:0] io_ways_4 = 8'h0; // @[Scheduler.scala:27:7] wire [7:0] io_ways_5 = 8'h0; // @[Scheduler.scala:27:7] wire [7:0] io_ways_6 = 8'h0; // @[Scheduler.scala:27:7] wire [7:0] io_ways_7 = 8'h0; // @[Scheduler.scala:27:7] wire [7:0] io_ways_8 = 8'h0; // @[Scheduler.scala:27:7] wire [10:0] io_divs_0 = 11'h0; // @[Scheduler.scala:27:7] wire [10:0] io_divs_1 = 11'h0; // @[Scheduler.scala:27:7] wire [10:0] io_divs_2 = 11'h0; // @[Scheduler.scala:27:7] wire [10:0] io_divs_3 = 11'h0; // @[Scheduler.scala:27:7] wire [10:0] io_divs_4 = 11'h0; // @[Scheduler.scala:27:7] wire [10:0] io_divs_5 = 11'h0; // @[Scheduler.scala:27:7] wire [10:0] io_divs_6 = 11'h0; // @[Scheduler.scala:27:7] wire [10:0] io_divs_7 = 11'h0; // @[Scheduler.scala:27:7] wire [10:0] io_divs_8 = 11'h0; // @[Scheduler.scala:27:7] wire [6:0] _lowerMatches1_T_1 = 7'h40; // @[Scheduler.scala:200:43] wire [6:0] _dirTarget_T = 7'h40; // @[Scheduler.scala:306:48] wire [3:0] _requests_io_push_bits_index_T_34 = 4'h0; // @[Mux.scala:30:73] wire [4:0] _prioFilter_T_1 = 5'h1F; // @[Scheduler.scala:182:69] wire [5:0] _lowerMatches1_T_3 = 6'h20; // @[Scheduler.scala:201:43] wire io_in_a_ready_0; // @[Scheduler.scala:27:7] wire [1:0] io_in_b_bits_param_0; // @[Scheduler.scala:27:7] wire [5:0] io_in_b_bits_source_0; // @[Scheduler.scala:27:7] wire [31:0] io_in_b_bits_address_0; // @[Scheduler.scala:27:7] wire io_in_b_valid_0; // @[Scheduler.scala:27:7] wire io_in_c_ready_0; // @[Scheduler.scala:27:7] wire [2:0] io_in_d_bits_opcode_0; // @[Scheduler.scala:27:7] wire [1:0] io_in_d_bits_param_0; // @[Scheduler.scala:27:7] wire [2:0] io_in_d_bits_size_0; // @[Scheduler.scala:27:7] wire [5:0] io_in_d_bits_source_0; // @[Scheduler.scala:27:7] wire [2:0] io_in_d_bits_sink_0; // @[Scheduler.scala:27:7] wire io_in_d_bits_denied_0; // @[Scheduler.scala:27:7] wire [63:0] io_in_d_bits_data_0; // @[Scheduler.scala:27:7] wire io_in_d_bits_corrupt_0; // @[Scheduler.scala:27:7] wire io_in_d_valid_0; // @[Scheduler.scala:27:7] wire [2:0] io_out_a_bits_opcode_0; // @[Scheduler.scala:27:7] wire [2:0] io_out_a_bits_param_0; // @[Scheduler.scala:27:7] wire [2:0] io_out_a_bits_size_0; // @[Scheduler.scala:27:7] wire [2:0] io_out_a_bits_source_0; // @[Scheduler.scala:27:7] wire [31:0] io_out_a_bits_address_0; // @[Scheduler.scala:27:7] wire [7:0] io_out_a_bits_mask_0; // @[Scheduler.scala:27:7] wire [63:0] io_out_a_bits_data_0; // @[Scheduler.scala:27:7] wire io_out_a_bits_corrupt_0; // @[Scheduler.scala:27:7] wire io_out_a_valid_0; // @[Scheduler.scala:27:7] wire [2:0] io_out_c_bits_opcode_0; // @[Scheduler.scala:27:7] wire [2:0] io_out_c_bits_param_0; // @[Scheduler.scala:27:7] wire [2:0] io_out_c_bits_size_0; // @[Scheduler.scala:27:7] wire [2:0] io_out_c_bits_source_0; // @[Scheduler.scala:27:7] wire [31:0] io_out_c_bits_address_0; // @[Scheduler.scala:27:7] wire [63:0] io_out_c_bits_data_0; // @[Scheduler.scala:27:7] wire io_out_c_bits_corrupt_0; // @[Scheduler.scala:27:7] wire io_out_c_valid_0; // @[Scheduler.scala:27:7] wire io_out_d_ready_0; // @[Scheduler.scala:27:7] wire [2:0] io_out_e_bits_sink_0; // @[Scheduler.scala:27:7] wire io_out_e_valid_0; // @[Scheduler.scala:27:7] wire io_req_ready_0; // @[Scheduler.scala:27:7] wire io_resp_valid_0; // @[Scheduler.scala:27:7] wire [9:0] _nestedwb_set_T; // @[Scheduler.scala:155:24] wire [12:0] _nestedwb_tag_T; // @[Scheduler.scala:156:24] wire _nestedwb_b_toN_T_2; // @[Scheduler.scala:157:75] wire _nestedwb_b_toB_T_2; // @[Scheduler.scala:158:75] wire _nestedwb_b_clr_dirty_T; // @[Scheduler.scala:159:37] wire _nestedwb_c_set_dirty_T_1; // @[Scheduler.scala:160:75] wire [9:0] nestedwb_set; // @[Scheduler.scala:75:22] wire [12:0] nestedwb_tag; // @[Scheduler.scala:75:22] wire nestedwb_b_toN; // @[Scheduler.scala:75:22] wire nestedwb_b_toB; // @[Scheduler.scala:75:22] wire nestedwb_b_clr_dirty; // @[Scheduler.scala:75:22] wire nestedwb_c_set_dirty; // @[Scheduler.scala:75:22] wire _mshrs_0_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_0_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71] wire _mshrs_0_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_0_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}] wire _mshrs_0_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 3'h0; // @[Scheduler.scala:56:21, :80:74] wire _mshrs_0_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_0_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}] wire _mshrs_0_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 3'h0; // @[Scheduler.scala:57:21, :81:74] wire _mshrs_0_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_0_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}] wire _mshrs_1_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_1_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71] wire _mshrs_1_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_1_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}] wire _mshrs_1_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 3'h1; // @[Scheduler.scala:56:21, :80:74] wire _mshrs_1_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_1_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}] wire _mshrs_1_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 3'h1; // @[Scheduler.scala:57:21, :81:74] wire _mshrs_1_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_1_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}] wire _mshrs_2_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_2_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71] wire _mshrs_2_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_2_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}] wire _mshrs_2_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 3'h2; // @[Scheduler.scala:56:21, :80:74] wire _mshrs_2_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_2_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}] wire _mshrs_2_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 3'h2; // @[Scheduler.scala:57:21, :81:74] wire _mshrs_2_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_2_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}] wire _mshrs_3_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_3_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71] wire _mshrs_3_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_3_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}] wire _mshrs_3_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 3'h3; // @[Scheduler.scala:56:21, :80:74] wire _mshrs_3_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_3_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}] wire _mshrs_3_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 3'h3; // @[Scheduler.scala:57:21, :81:74] wire _mshrs_3_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_3_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}] wire _mshrs_4_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_4_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71] wire _mshrs_4_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_4_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}] wire _mshrs_4_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 3'h4; // @[Scheduler.scala:56:21, :80:74] wire _mshrs_4_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_4_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}] wire _mshrs_4_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 3'h4; // @[Scheduler.scala:57:21, :81:74] wire _mshrs_4_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_4_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}] wire _mshrs_5_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_5_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71] wire _mshrs_5_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_5_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}] wire _mshrs_5_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 3'h5; // @[Scheduler.scala:56:21, :80:74] wire _mshrs_5_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_5_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}] wire _mshrs_5_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 3'h5; // @[Scheduler.scala:57:21, :81:74] wire _mshrs_5_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_5_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}] wire _mshrs_6_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_6_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71] wire _mshrs_6_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_6_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}] wire _mshrs_6_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 3'h6; // @[Scheduler.scala:56:21, :80:74] wire _mshrs_6_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_6_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}] wire _mshrs_6_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 3'h6; // @[Scheduler.scala:57:21, :81:74] wire _mshrs_6_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_6_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}] wire _mshr_stall_abc_T = _mshrs_0_io_status_bits_set == _mshrs_5_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54] wire _mshr_stall_abc_T_1 = _mshrs_5_io_status_valid & _mshr_stall_abc_T; // @[Scheduler.scala:71:46, :90:{30,54}] wire _mshr_stall_abc_T_2 = _mshrs_0_io_status_bits_set == _mshrs_6_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54] wire _mshr_stall_abc_T_3 = _mshrs_6_io_status_valid & _mshr_stall_abc_T_2; // @[Scheduler.scala:71:46, :91:{30,54}] wire mshr_stall_abc_0 = _mshr_stall_abc_T_1 | _mshr_stall_abc_T_3; // @[Scheduler.scala:90:{30,86}, :91:30] wire _mshr_stall_abc_T_4 = _mshrs_1_io_status_bits_set == _mshrs_5_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54] wire _mshr_stall_abc_T_5 = _mshrs_5_io_status_valid & _mshr_stall_abc_T_4; // @[Scheduler.scala:71:46, :90:{30,54}] wire _mshr_stall_abc_T_6 = _mshrs_1_io_status_bits_set == _mshrs_6_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54] wire _mshr_stall_abc_T_7 = _mshrs_6_io_status_valid & _mshr_stall_abc_T_6; // @[Scheduler.scala:71:46, :91:{30,54}] wire mshr_stall_abc_1 = _mshr_stall_abc_T_5 | _mshr_stall_abc_T_7; // @[Scheduler.scala:90:{30,86}, :91:30] wire _mshr_stall_abc_T_8 = _mshrs_2_io_status_bits_set == _mshrs_5_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54] wire _mshr_stall_abc_T_9 = _mshrs_5_io_status_valid & _mshr_stall_abc_T_8; // @[Scheduler.scala:71:46, :90:{30,54}] wire _mshr_stall_abc_T_10 = _mshrs_2_io_status_bits_set == _mshrs_6_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54] wire _mshr_stall_abc_T_11 = _mshrs_6_io_status_valid & _mshr_stall_abc_T_10; // @[Scheduler.scala:71:46, :91:{30,54}] wire mshr_stall_abc_2 = _mshr_stall_abc_T_9 | _mshr_stall_abc_T_11; // @[Scheduler.scala:90:{30,86}, :91:30] wire _mshr_stall_abc_T_12 = _mshrs_3_io_status_bits_set == _mshrs_5_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54] wire _mshr_stall_abc_T_13 = _mshrs_5_io_status_valid & _mshr_stall_abc_T_12; // @[Scheduler.scala:71:46, :90:{30,54}] wire _mshr_stall_abc_T_14 = _mshrs_3_io_status_bits_set == _mshrs_6_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54] wire _mshr_stall_abc_T_15 = _mshrs_6_io_status_valid & _mshr_stall_abc_T_14; // @[Scheduler.scala:71:46, :91:{30,54}] wire mshr_stall_abc_3 = _mshr_stall_abc_T_13 | _mshr_stall_abc_T_15; // @[Scheduler.scala:90:{30,86}, :91:30] wire _mshr_stall_abc_T_16 = _mshrs_4_io_status_bits_set == _mshrs_5_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54] wire _mshr_stall_abc_T_17 = _mshrs_5_io_status_valid & _mshr_stall_abc_T_16; // @[Scheduler.scala:71:46, :90:{30,54}] wire _mshr_stall_abc_T_18 = _mshrs_4_io_status_bits_set == _mshrs_6_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54] wire _mshr_stall_abc_T_19 = _mshrs_6_io_status_valid & _mshr_stall_abc_T_18; // @[Scheduler.scala:71:46, :91:{30,54}] wire mshr_stall_abc_4 = _mshr_stall_abc_T_17 | _mshr_stall_abc_T_19; // @[Scheduler.scala:90:{30,86}, :91:30] wire _mshr_stall_bc_T = _mshrs_5_io_status_bits_set == _mshrs_6_io_status_bits_set; // @[Scheduler.scala:71:46, :94:58] wire mshr_stall_bc = _mshrs_6_io_status_valid & _mshr_stall_bc_T; // @[Scheduler.scala:71:46, :94:{28,58}] wire stall_abc_0 = mshr_stall_abc_0 & _mshrs_0_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73] wire stall_abc_1 = mshr_stall_abc_1 & _mshrs_1_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73] wire stall_abc_2 = mshr_stall_abc_2 & _mshrs_2_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73] wire stall_abc_3 = mshr_stall_abc_3 & _mshrs_3_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73] wire stall_abc_4 = mshr_stall_abc_4 & _mshrs_4_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73] wire _mshr_request_T = ~mshr_stall_abc_0; // @[Scheduler.scala:90:86, :107:28] wire _mshr_request_T_1 = _mshrs_0_io_schedule_valid & _mshr_request_T; // @[Scheduler.scala:71:46, :107:{25,28}] wire _mshr_request_T_2 = ~_mshrs_0_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32] wire _mshr_request_T_3 = _sourceA_io_req_ready | _mshr_request_T_2; // @[Scheduler.scala:40:23, :108:{29,32}] wire _mshr_request_T_4 = _mshr_request_T_1 & _mshr_request_T_3; // @[Scheduler.scala:107:{25,31}, :108:29] wire _mshr_request_T_5 = ~_mshrs_0_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32] wire _mshr_request_T_6 = _sourceB_io_req_ready | _mshr_request_T_5; // @[Scheduler.scala:41:23, :109:{29,32}] wire _mshr_request_T_7 = _mshr_request_T_4 & _mshr_request_T_6; // @[Scheduler.scala:107:31, :108:61, :109:29] wire _mshr_request_T_8 = ~_mshrs_0_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32] wire _mshr_request_T_9 = _sourceC_io_req_ready | _mshr_request_T_8; // @[Scheduler.scala:42:23, :110:{29,32}] wire _mshr_request_T_10 = _mshr_request_T_7 & _mshr_request_T_9; // @[Scheduler.scala:108:61, :109:61, :110:29] wire _mshr_request_T_11 = ~_mshrs_0_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32] wire _mshr_request_T_12 = _sourceD_io_req_ready | _mshr_request_T_11; // @[Scheduler.scala:43:23, :111:{29,32}] wire _mshr_request_T_13 = _mshr_request_T_10 & _mshr_request_T_12; // @[Scheduler.scala:109:61, :110:61, :111:29] wire _mshr_request_T_14 = ~_mshrs_0_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32] wire _mshr_request_T_15 = _sourceE_io_req_ready | _mshr_request_T_14; // @[Scheduler.scala:44:23, :112:{29,32}] wire _mshr_request_T_16 = _mshr_request_T_13 & _mshr_request_T_15; // @[Scheduler.scala:110:61, :111:61, :112:29] wire _mshr_request_T_17 = ~_mshrs_0_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32] wire _mshr_request_T_18 = _sourceX_io_req_ready | _mshr_request_T_17; // @[Scheduler.scala:45:23, :113:{29,32}] wire _mshr_request_T_19 = _mshr_request_T_16 & _mshr_request_T_18; // @[Scheduler.scala:111:61, :112:61, :113:29] wire _mshr_request_T_20 = ~_mshrs_0_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36] wire _mshr_request_T_21 = _directory_io_write_ready | _mshr_request_T_20; // @[Scheduler.scala:68:25, :114:{33,36}] wire _mshr_request_T_22 = _mshr_request_T_19 & _mshr_request_T_21; // @[Scheduler.scala:112:61, :113:61, :114:33] wire _mshr_request_T_23 = ~mshr_stall_abc_1; // @[Scheduler.scala:90:86, :107:28] wire _mshr_request_T_24 = _mshrs_1_io_schedule_valid & _mshr_request_T_23; // @[Scheduler.scala:71:46, :107:{25,28}] wire _mshr_request_T_25 = ~_mshrs_1_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32] wire _mshr_request_T_26 = _sourceA_io_req_ready | _mshr_request_T_25; // @[Scheduler.scala:40:23, :108:{29,32}] wire _mshr_request_T_27 = _mshr_request_T_24 & _mshr_request_T_26; // @[Scheduler.scala:107:{25,31}, :108:29] wire _mshr_request_T_28 = ~_mshrs_1_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32] wire _mshr_request_T_29 = _sourceB_io_req_ready | _mshr_request_T_28; // @[Scheduler.scala:41:23, :109:{29,32}] wire _mshr_request_T_30 = _mshr_request_T_27 & _mshr_request_T_29; // @[Scheduler.scala:107:31, :108:61, :109:29] wire _mshr_request_T_31 = ~_mshrs_1_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32] wire _mshr_request_T_32 = _sourceC_io_req_ready | _mshr_request_T_31; // @[Scheduler.scala:42:23, :110:{29,32}] wire _mshr_request_T_33 = _mshr_request_T_30 & _mshr_request_T_32; // @[Scheduler.scala:108:61, :109:61, :110:29] wire _mshr_request_T_34 = ~_mshrs_1_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32] wire _mshr_request_T_35 = _sourceD_io_req_ready | _mshr_request_T_34; // @[Scheduler.scala:43:23, :111:{29,32}] wire _mshr_request_T_36 = _mshr_request_T_33 & _mshr_request_T_35; // @[Scheduler.scala:109:61, :110:61, :111:29] wire _mshr_request_T_37 = ~_mshrs_1_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32] wire _mshr_request_T_38 = _sourceE_io_req_ready | _mshr_request_T_37; // @[Scheduler.scala:44:23, :112:{29,32}] wire _mshr_request_T_39 = _mshr_request_T_36 & _mshr_request_T_38; // @[Scheduler.scala:110:61, :111:61, :112:29] wire _mshr_request_T_40 = ~_mshrs_1_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32] wire _mshr_request_T_41 = _sourceX_io_req_ready | _mshr_request_T_40; // @[Scheduler.scala:45:23, :113:{29,32}] wire _mshr_request_T_42 = _mshr_request_T_39 & _mshr_request_T_41; // @[Scheduler.scala:111:61, :112:61, :113:29] wire _mshr_request_T_43 = ~_mshrs_1_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36] wire _mshr_request_T_44 = _directory_io_write_ready | _mshr_request_T_43; // @[Scheduler.scala:68:25, :114:{33,36}] wire _mshr_request_T_45 = _mshr_request_T_42 & _mshr_request_T_44; // @[Scheduler.scala:112:61, :113:61, :114:33] wire _mshr_request_T_46 = ~mshr_stall_abc_2; // @[Scheduler.scala:90:86, :107:28] wire _mshr_request_T_47 = _mshrs_2_io_schedule_valid & _mshr_request_T_46; // @[Scheduler.scala:71:46, :107:{25,28}] wire _mshr_request_T_48 = ~_mshrs_2_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32] wire _mshr_request_T_49 = _sourceA_io_req_ready | _mshr_request_T_48; // @[Scheduler.scala:40:23, :108:{29,32}] wire _mshr_request_T_50 = _mshr_request_T_47 & _mshr_request_T_49; // @[Scheduler.scala:107:{25,31}, :108:29] wire _mshr_request_T_51 = ~_mshrs_2_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32] wire _mshr_request_T_52 = _sourceB_io_req_ready | _mshr_request_T_51; // @[Scheduler.scala:41:23, :109:{29,32}] wire _mshr_request_T_53 = _mshr_request_T_50 & _mshr_request_T_52; // @[Scheduler.scala:107:31, :108:61, :109:29] wire _mshr_request_T_54 = ~_mshrs_2_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32] wire _mshr_request_T_55 = _sourceC_io_req_ready | _mshr_request_T_54; // @[Scheduler.scala:42:23, :110:{29,32}] wire _mshr_request_T_56 = _mshr_request_T_53 & _mshr_request_T_55; // @[Scheduler.scala:108:61, :109:61, :110:29] wire _mshr_request_T_57 = ~_mshrs_2_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32] wire _mshr_request_T_58 = _sourceD_io_req_ready | _mshr_request_T_57; // @[Scheduler.scala:43:23, :111:{29,32}] wire _mshr_request_T_59 = _mshr_request_T_56 & _mshr_request_T_58; // @[Scheduler.scala:109:61, :110:61, :111:29] wire _mshr_request_T_60 = ~_mshrs_2_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32] wire _mshr_request_T_61 = _sourceE_io_req_ready | _mshr_request_T_60; // @[Scheduler.scala:44:23, :112:{29,32}] wire _mshr_request_T_62 = _mshr_request_T_59 & _mshr_request_T_61; // @[Scheduler.scala:110:61, :111:61, :112:29] wire _mshr_request_T_63 = ~_mshrs_2_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32] wire _mshr_request_T_64 = _sourceX_io_req_ready | _mshr_request_T_63; // @[Scheduler.scala:45:23, :113:{29,32}] wire _mshr_request_T_65 = _mshr_request_T_62 & _mshr_request_T_64; // @[Scheduler.scala:111:61, :112:61, :113:29] wire _mshr_request_T_66 = ~_mshrs_2_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36] wire _mshr_request_T_67 = _directory_io_write_ready | _mshr_request_T_66; // @[Scheduler.scala:68:25, :114:{33,36}] wire _mshr_request_T_68 = _mshr_request_T_65 & _mshr_request_T_67; // @[Scheduler.scala:112:61, :113:61, :114:33] wire _mshr_request_T_69 = ~mshr_stall_abc_3; // @[Scheduler.scala:90:86, :107:28] wire _mshr_request_T_70 = _mshrs_3_io_schedule_valid & _mshr_request_T_69; // @[Scheduler.scala:71:46, :107:{25,28}] wire _mshr_request_T_71 = ~_mshrs_3_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32] wire _mshr_request_T_72 = _sourceA_io_req_ready | _mshr_request_T_71; // @[Scheduler.scala:40:23, :108:{29,32}] wire _mshr_request_T_73 = _mshr_request_T_70 & _mshr_request_T_72; // @[Scheduler.scala:107:{25,31}, :108:29] wire _mshr_request_T_74 = ~_mshrs_3_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32] wire _mshr_request_T_75 = _sourceB_io_req_ready | _mshr_request_T_74; // @[Scheduler.scala:41:23, :109:{29,32}] wire _mshr_request_T_76 = _mshr_request_T_73 & _mshr_request_T_75; // @[Scheduler.scala:107:31, :108:61, :109:29] wire _mshr_request_T_77 = ~_mshrs_3_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32] wire _mshr_request_T_78 = _sourceC_io_req_ready | _mshr_request_T_77; // @[Scheduler.scala:42:23, :110:{29,32}] wire _mshr_request_T_79 = _mshr_request_T_76 & _mshr_request_T_78; // @[Scheduler.scala:108:61, :109:61, :110:29] wire _mshr_request_T_80 = ~_mshrs_3_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32] wire _mshr_request_T_81 = _sourceD_io_req_ready | _mshr_request_T_80; // @[Scheduler.scala:43:23, :111:{29,32}] wire _mshr_request_T_82 = _mshr_request_T_79 & _mshr_request_T_81; // @[Scheduler.scala:109:61, :110:61, :111:29] wire _mshr_request_T_83 = ~_mshrs_3_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32] wire _mshr_request_T_84 = _sourceE_io_req_ready | _mshr_request_T_83; // @[Scheduler.scala:44:23, :112:{29,32}] wire _mshr_request_T_85 = _mshr_request_T_82 & _mshr_request_T_84; // @[Scheduler.scala:110:61, :111:61, :112:29] wire _mshr_request_T_86 = ~_mshrs_3_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32] wire _mshr_request_T_87 = _sourceX_io_req_ready | _mshr_request_T_86; // @[Scheduler.scala:45:23, :113:{29,32}] wire _mshr_request_T_88 = _mshr_request_T_85 & _mshr_request_T_87; // @[Scheduler.scala:111:61, :112:61, :113:29] wire _mshr_request_T_89 = ~_mshrs_3_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36] wire _mshr_request_T_90 = _directory_io_write_ready | _mshr_request_T_89; // @[Scheduler.scala:68:25, :114:{33,36}] wire _mshr_request_T_91 = _mshr_request_T_88 & _mshr_request_T_90; // @[Scheduler.scala:112:61, :113:61, :114:33] wire _mshr_request_T_92 = ~mshr_stall_abc_4; // @[Scheduler.scala:90:86, :107:28] wire _mshr_request_T_93 = _mshrs_4_io_schedule_valid & _mshr_request_T_92; // @[Scheduler.scala:71:46, :107:{25,28}] wire _mshr_request_T_94 = ~_mshrs_4_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32] wire _mshr_request_T_95 = _sourceA_io_req_ready | _mshr_request_T_94; // @[Scheduler.scala:40:23, :108:{29,32}] wire _mshr_request_T_96 = _mshr_request_T_93 & _mshr_request_T_95; // @[Scheduler.scala:107:{25,31}, :108:29] wire _mshr_request_T_97 = ~_mshrs_4_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32] wire _mshr_request_T_98 = _sourceB_io_req_ready | _mshr_request_T_97; // @[Scheduler.scala:41:23, :109:{29,32}] wire _mshr_request_T_99 = _mshr_request_T_96 & _mshr_request_T_98; // @[Scheduler.scala:107:31, :108:61, :109:29] wire _mshr_request_T_100 = ~_mshrs_4_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32] wire _mshr_request_T_101 = _sourceC_io_req_ready | _mshr_request_T_100; // @[Scheduler.scala:42:23, :110:{29,32}] wire _mshr_request_T_102 = _mshr_request_T_99 & _mshr_request_T_101; // @[Scheduler.scala:108:61, :109:61, :110:29] wire _mshr_request_T_103 = ~_mshrs_4_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32] wire _mshr_request_T_104 = _sourceD_io_req_ready | _mshr_request_T_103; // @[Scheduler.scala:43:23, :111:{29,32}] wire _mshr_request_T_105 = _mshr_request_T_102 & _mshr_request_T_104; // @[Scheduler.scala:109:61, :110:61, :111:29] wire _mshr_request_T_106 = ~_mshrs_4_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32] wire _mshr_request_T_107 = _sourceE_io_req_ready | _mshr_request_T_106; // @[Scheduler.scala:44:23, :112:{29,32}] wire _mshr_request_T_108 = _mshr_request_T_105 & _mshr_request_T_107; // @[Scheduler.scala:110:61, :111:61, :112:29] wire _mshr_request_T_109 = ~_mshrs_4_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32] wire _mshr_request_T_110 = _sourceX_io_req_ready | _mshr_request_T_109; // @[Scheduler.scala:45:23, :113:{29,32}] wire _mshr_request_T_111 = _mshr_request_T_108 & _mshr_request_T_110; // @[Scheduler.scala:111:61, :112:61, :113:29] wire _mshr_request_T_112 = ~_mshrs_4_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36] wire _mshr_request_T_113 = _directory_io_write_ready | _mshr_request_T_112; // @[Scheduler.scala:68:25, :114:{33,36}] wire _mshr_request_T_114 = _mshr_request_T_111 & _mshr_request_T_113; // @[Scheduler.scala:112:61, :113:61, :114:33] wire _mshr_request_T_115 = ~mshr_stall_bc; // @[Scheduler.scala:94:28, :107:28] wire _mshr_request_T_116 = _mshrs_5_io_schedule_valid & _mshr_request_T_115; // @[Scheduler.scala:71:46, :107:{25,28}] wire _mshr_request_T_117 = ~_mshrs_5_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32] wire _mshr_request_T_118 = _sourceA_io_req_ready | _mshr_request_T_117; // @[Scheduler.scala:40:23, :108:{29,32}] wire _mshr_request_T_119 = _mshr_request_T_116 & _mshr_request_T_118; // @[Scheduler.scala:107:{25,31}, :108:29] wire _mshr_request_T_120 = ~_mshrs_5_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32] wire _mshr_request_T_121 = _sourceB_io_req_ready | _mshr_request_T_120; // @[Scheduler.scala:41:23, :109:{29,32}] wire _mshr_request_T_122 = _mshr_request_T_119 & _mshr_request_T_121; // @[Scheduler.scala:107:31, :108:61, :109:29] wire _mshr_request_T_123 = ~_mshrs_5_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32] wire _mshr_request_T_124 = _sourceC_io_req_ready | _mshr_request_T_123; // @[Scheduler.scala:42:23, :110:{29,32}] wire _mshr_request_T_125 = _mshr_request_T_122 & _mshr_request_T_124; // @[Scheduler.scala:108:61, :109:61, :110:29] wire _mshr_request_T_126 = ~_mshrs_5_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32] wire _mshr_request_T_127 = _sourceD_io_req_ready | _mshr_request_T_126; // @[Scheduler.scala:43:23, :111:{29,32}] wire _mshr_request_T_128 = _mshr_request_T_125 & _mshr_request_T_127; // @[Scheduler.scala:109:61, :110:61, :111:29] wire _mshr_request_T_129 = ~_mshrs_5_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32] wire _mshr_request_T_130 = _sourceE_io_req_ready | _mshr_request_T_129; // @[Scheduler.scala:44:23, :112:{29,32}] wire _mshr_request_T_131 = _mshr_request_T_128 & _mshr_request_T_130; // @[Scheduler.scala:110:61, :111:61, :112:29] wire _mshr_request_T_132 = ~_mshrs_5_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32] wire _mshr_request_T_133 = _sourceX_io_req_ready | _mshr_request_T_132; // @[Scheduler.scala:45:23, :113:{29,32}] wire _mshr_request_T_134 = _mshr_request_T_131 & _mshr_request_T_133; // @[Scheduler.scala:111:61, :112:61, :113:29] wire _mshr_request_T_135 = ~_mshrs_5_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36] wire _mshr_request_T_136 = _directory_io_write_ready | _mshr_request_T_135; // @[Scheduler.scala:68:25, :114:{33,36}] wire _mshr_request_T_137 = _mshr_request_T_134 & _mshr_request_T_136; // @[Scheduler.scala:112:61, :113:61, :114:33] wire _mshr_request_T_140 = ~_mshrs_6_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32] wire _mshr_request_T_141 = _sourceA_io_req_ready | _mshr_request_T_140; // @[Scheduler.scala:40:23, :108:{29,32}] wire _mshr_request_T_139; // @[Scheduler.scala:107:25] wire _mshr_request_T_142 = _mshr_request_T_139 & _mshr_request_T_141; // @[Scheduler.scala:107:{25,31}, :108:29] wire _mshr_request_T_143 = ~_mshrs_6_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32] wire _mshr_request_T_144 = _sourceB_io_req_ready | _mshr_request_T_143; // @[Scheduler.scala:41:23, :109:{29,32}] wire _mshr_request_T_145 = _mshr_request_T_142 & _mshr_request_T_144; // @[Scheduler.scala:107:31, :108:61, :109:29] wire _mshr_request_T_146 = ~_mshrs_6_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32] wire _mshr_request_T_147 = _sourceC_io_req_ready | _mshr_request_T_146; // @[Scheduler.scala:42:23, :110:{29,32}] wire _mshr_request_T_148 = _mshr_request_T_145 & _mshr_request_T_147; // @[Scheduler.scala:108:61, :109:61, :110:29] wire _mshr_request_T_149 = ~_mshrs_6_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32] wire _mshr_request_T_150 = _sourceD_io_req_ready | _mshr_request_T_149; // @[Scheduler.scala:43:23, :111:{29,32}] wire _mshr_request_T_151 = _mshr_request_T_148 & _mshr_request_T_150; // @[Scheduler.scala:109:61, :110:61, :111:29] wire _mshr_request_T_152 = ~_mshrs_6_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32] wire _mshr_request_T_153 = _sourceE_io_req_ready | _mshr_request_T_152; // @[Scheduler.scala:44:23, :112:{29,32}] wire _mshr_request_T_154 = _mshr_request_T_151 & _mshr_request_T_153; // @[Scheduler.scala:110:61, :111:61, :112:29] wire _mshr_request_T_155 = ~_mshrs_6_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32] wire _mshr_request_T_156 = _sourceX_io_req_ready | _mshr_request_T_155; // @[Scheduler.scala:45:23, :113:{29,32}] wire _mshr_request_T_157 = _mshr_request_T_154 & _mshr_request_T_156; // @[Scheduler.scala:111:61, :112:61, :113:29] wire _mshr_request_T_158 = ~_mshrs_6_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36] wire _mshr_request_T_159 = _directory_io_write_ready | _mshr_request_T_158; // @[Scheduler.scala:68:25, :114:{33,36}] wire _mshr_request_T_160 = _mshr_request_T_157 & _mshr_request_T_159; // @[Scheduler.scala:112:61, :113:61, :114:33] wire [1:0] mshr_request_lo_hi = {_mshr_request_T_68, _mshr_request_T_45}; // @[Scheduler.scala:106:25, :113:61] wire [2:0] mshr_request_lo = {mshr_request_lo_hi, _mshr_request_T_22}; // @[Scheduler.scala:106:25, :113:61] wire [1:0] mshr_request_hi_lo = {_mshr_request_T_114, _mshr_request_T_91}; // @[Scheduler.scala:106:25, :113:61] wire [1:0] mshr_request_hi_hi = {_mshr_request_T_160, _mshr_request_T_137}; // @[Scheduler.scala:106:25, :113:61] wire [3:0] mshr_request_hi = {mshr_request_hi_hi, mshr_request_hi_lo}; // @[Scheduler.scala:106:25] wire [6:0] mshr_request = {mshr_request_hi, mshr_request_lo}; // @[Scheduler.scala:106:25] reg [6:0] robin_filter; // @[Scheduler.scala:118:29] wire [6:0] _robin_request_T = mshr_request & robin_filter; // @[Scheduler.scala:106:25, :118:29, :119:54] wire [13:0] robin_request = {mshr_request, _robin_request_T}; // @[Scheduler.scala:106:25, :119:{26,54}] wire [14:0] _mshr_selectOH2_T = {robin_request, 1'h0}; // @[package.scala:253:48] wire [13:0] _mshr_selectOH2_T_1 = _mshr_selectOH2_T[13:0]; // @[package.scala:253:{48,53}] wire [13:0] _mshr_selectOH2_T_2 = robin_request | _mshr_selectOH2_T_1; // @[package.scala:253:{43,53}] wire [15:0] _mshr_selectOH2_T_3 = {_mshr_selectOH2_T_2, 2'h0}; // @[package.scala:253:{43,48}] wire [13:0] _mshr_selectOH2_T_4 = _mshr_selectOH2_T_3[13:0]; // @[package.scala:253:{48,53}] wire [13:0] _mshr_selectOH2_T_5 = _mshr_selectOH2_T_2 | _mshr_selectOH2_T_4; // @[package.scala:253:{43,53}] wire [17:0] _mshr_selectOH2_T_6 = {_mshr_selectOH2_T_5, 4'h0}; // @[package.scala:253:{43,48}] wire [13:0] _mshr_selectOH2_T_7 = _mshr_selectOH2_T_6[13:0]; // @[package.scala:253:{48,53}] wire [13:0] _mshr_selectOH2_T_8 = _mshr_selectOH2_T_5 | _mshr_selectOH2_T_7; // @[package.scala:253:{43,53}] wire [21:0] _mshr_selectOH2_T_9 = {_mshr_selectOH2_T_8, 8'h0}; // @[package.scala:253:{43,48}] wire [13:0] _mshr_selectOH2_T_10 = _mshr_selectOH2_T_9[13:0]; // @[package.scala:253:{48,53}] wire [13:0] _mshr_selectOH2_T_11 = _mshr_selectOH2_T_8 | _mshr_selectOH2_T_10; // @[package.scala:253:{43,53}] wire [13:0] _mshr_selectOH2_T_12 = _mshr_selectOH2_T_11; // @[package.scala:253:43, :254:17] wire [14:0] _mshr_selectOH2_T_13 = {_mshr_selectOH2_T_12, 1'h0}; // @[package.scala:254:17] wire [14:0] _mshr_selectOH2_T_14 = ~_mshr_selectOH2_T_13; // @[Scheduler.scala:120:{24,48}] wire [14:0] mshr_selectOH2 = {1'h0, _mshr_selectOH2_T_14[13:0] & robin_request}; // @[Scheduler.scala:119:26, :120:{24,54}] wire [6:0] _mshr_selectOH_T = mshr_selectOH2[13:7]; // @[Scheduler.scala:120:54, :121:37] wire [6:0] _mshr_selectOH_T_1 = mshr_selectOH2[6:0]; // @[Scheduler.scala:120:54, :121:86] wire [6:0] mshr_selectOH = _mshr_selectOH_T | _mshr_selectOH_T_1; // @[Scheduler.scala:121:{37,70,86}] wire [2:0] mshr_select_hi = mshr_selectOH[6:4]; // @[OneHot.scala:30:18] wire [3:0] mshr_select_lo = mshr_selectOH[3:0]; // @[OneHot.scala:31:18] wire _mshr_select_T = |mshr_select_hi; // @[OneHot.scala:30:18, :32:14] wire [3:0] _mshr_select_T_1 = {1'h0, mshr_select_hi} | mshr_select_lo; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] mshr_select_hi_1 = _mshr_select_T_1[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] mshr_select_lo_1 = _mshr_select_T_1[1:0]; // @[OneHot.scala:31:18, :32:28] wire _mshr_select_T_2 = |mshr_select_hi_1; // @[OneHot.scala:30:18, :32:14] wire [1:0] _mshr_select_T_3 = mshr_select_hi_1 | mshr_select_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire _mshr_select_T_4 = _mshr_select_T_3[1]; // @[OneHot.scala:32:28] wire [1:0] _mshr_select_T_5 = {_mshr_select_T_2, _mshr_select_T_4}; // @[OneHot.scala:32:{10,14}] wire [2:0] mshr_select = {_mshr_select_T, _mshr_select_T_5}; // @[OneHot.scala:32:{10,14}] wire [2:0] schedule_a_bits_source = mshr_select; // @[OneHot.scala:32:10] wire [2:0] schedule_d_bits_sink = mshr_select; // @[OneHot.scala:32:10] wire _schedule_T = mshr_selectOH[0]; // @[Mux.scala:32:36] wire _scheduleTag_T = mshr_selectOH[0]; // @[Mux.scala:32:36] wire _scheduleSet_T = mshr_selectOH[0]; // @[Mux.scala:32:36] wire sel = mshr_selectOH[0]; // @[Mux.scala:32:36] wire _schedule_T_1 = mshr_selectOH[1]; // @[Mux.scala:32:36] wire _scheduleTag_T_1 = mshr_selectOH[1]; // @[Mux.scala:32:36] wire _scheduleSet_T_1 = mshr_selectOH[1]; // @[Mux.scala:32:36] wire sel_1 = mshr_selectOH[1]; // @[Mux.scala:32:36] wire _schedule_T_2 = mshr_selectOH[2]; // @[Mux.scala:32:36] wire _scheduleTag_T_2 = mshr_selectOH[2]; // @[Mux.scala:32:36] wire _scheduleSet_T_2 = mshr_selectOH[2]; // @[Mux.scala:32:36] wire sel_2 = mshr_selectOH[2]; // @[Mux.scala:32:36] wire _schedule_T_3 = mshr_selectOH[3]; // @[Mux.scala:32:36] wire _scheduleTag_T_3 = mshr_selectOH[3]; // @[Mux.scala:32:36] wire _scheduleSet_T_3 = mshr_selectOH[3]; // @[Mux.scala:32:36] wire sel_3 = mshr_selectOH[3]; // @[Mux.scala:32:36] wire _schedule_T_4 = mshr_selectOH[4]; // @[Mux.scala:32:36] wire _scheduleTag_T_4 = mshr_selectOH[4]; // @[Mux.scala:32:36] wire _scheduleSet_T_4 = mshr_selectOH[4]; // @[Mux.scala:32:36] wire sel_4 = mshr_selectOH[4]; // @[Mux.scala:32:36] wire _schedule_T_5 = mshr_selectOH[5]; // @[Mux.scala:32:36] wire _scheduleTag_T_5 = mshr_selectOH[5]; // @[Mux.scala:32:36] wire _scheduleSet_T_5 = mshr_selectOH[5]; // @[Mux.scala:32:36] wire select_bc = mshr_selectOH[5]; // @[Mux.scala:32:36] wire sel_5 = mshr_selectOH[5]; // @[Mux.scala:32:36] wire _schedule_T_6 = mshr_selectOH[6]; // @[Mux.scala:32:36] wire _scheduleTag_T_6 = mshr_selectOH[6]; // @[Mux.scala:32:36] wire _scheduleSet_T_6 = mshr_selectOH[6]; // @[Mux.scala:32:36] wire select_c = mshr_selectOH[6]; // @[Mux.scala:32:36] wire sel_6 = mshr_selectOH[6]; // @[Mux.scala:32:36] wire _schedule_WIRE_55_valid; // @[Mux.scala:30:73] wire [12:0] _schedule_WIRE_55_bits_tag; // @[Mux.scala:30:73] wire [9:0] _schedule_WIRE_55_bits_set; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_55_bits_param; // @[Mux.scala:30:73] wire _schedule_WIRE_55_bits_block; // @[Mux.scala:30:73] wire _schedule_WIRE_48_valid; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_48_bits_param; // @[Mux.scala:30:73] wire [12:0] _schedule_WIRE_48_bits_tag; // @[Mux.scala:30:73] wire [9:0] _schedule_WIRE_48_bits_set; // @[Mux.scala:30:73] wire [1:0] _schedule_WIRE_48_bits_clients; // @[Mux.scala:30:73] wire _schedule_WIRE_38_valid; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_38_bits_opcode; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_38_bits_param; // @[Mux.scala:30:73] wire [2:0] _schedule_c_bits_source_T_1; // @[Scheduler.scala:132:32] wire [12:0] _schedule_WIRE_38_bits_tag; // @[Mux.scala:30:73] wire [9:0] _schedule_WIRE_38_bits_set; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_38_bits_way; // @[Mux.scala:30:73] wire _schedule_WIRE_38_bits_dirty; // @[Mux.scala:30:73] wire _schedule_WIRE_19_valid; // @[Mux.scala:30:73] wire _schedule_WIRE_19_bits_prio_0; // @[Mux.scala:30:73] wire _schedule_WIRE_19_bits_prio_1; // @[Mux.scala:30:73] wire _schedule_WIRE_19_bits_prio_2; // @[Mux.scala:30:73] wire _schedule_WIRE_19_bits_control; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_19_bits_opcode; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_19_bits_param; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_19_bits_size; // @[Mux.scala:30:73] wire [5:0] _schedule_WIRE_19_bits_source; // @[Mux.scala:30:73] wire [12:0] _schedule_WIRE_19_bits_tag; // @[Mux.scala:30:73] wire [5:0] _schedule_WIRE_19_bits_offset; // @[Mux.scala:30:73] wire [5:0] _schedule_WIRE_19_bits_put; // @[Mux.scala:30:73] wire [9:0] _schedule_WIRE_19_bits_set; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_19_bits_way; // @[Mux.scala:30:73] wire _schedule_WIRE_19_bits_bad; // @[Mux.scala:30:73] wire _schedule_WIRE_15_valid; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_15_bits_sink; // @[Mux.scala:30:73] wire _schedule_WIRE_11_valid; // @[Mux.scala:30:73] wire _schedule_WIRE_1_valid; // @[Mux.scala:30:73] wire [9:0] _schedule_WIRE_1_bits_set; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_1_bits_way; // @[Mux.scala:30:73] wire _schedule_WIRE_1_bits_data_dirty; // @[Mux.scala:30:73] wire [1:0] _schedule_WIRE_1_bits_data_state; // @[Mux.scala:30:73] wire [1:0] _schedule_WIRE_1_bits_data_clients; // @[Mux.scala:30:73] wire [12:0] _schedule_WIRE_1_bits_data_tag; // @[Mux.scala:30:73] wire _schedule_WIRE; // @[Mux.scala:30:73] wire [12:0] schedule_a_bits_tag; // @[Mux.scala:30:73] wire [9:0] schedule_a_bits_set; // @[Mux.scala:30:73] wire [2:0] schedule_a_bits_param; // @[Mux.scala:30:73] wire schedule_a_bits_block; // @[Mux.scala:30:73] wire schedule_a_valid; // @[Mux.scala:30:73] wire [2:0] schedule_b_bits_param; // @[Mux.scala:30:73] wire [12:0] schedule_b_bits_tag; // @[Mux.scala:30:73] wire [9:0] schedule_b_bits_set; // @[Mux.scala:30:73] wire [1:0] schedule_b_bits_clients; // @[Mux.scala:30:73] wire schedule_b_valid; // @[Mux.scala:30:73] wire [2:0] schedule_c_bits_opcode; // @[Mux.scala:30:73] wire [2:0] schedule_c_bits_param; // @[Mux.scala:30:73] wire [2:0] schedule_c_bits_source; // @[Mux.scala:30:73] wire [12:0] schedule_c_bits_tag; // @[Mux.scala:30:73] wire [9:0] schedule_c_bits_set; // @[Mux.scala:30:73] wire [2:0] schedule_c_bits_way; // @[Mux.scala:30:73] wire schedule_c_bits_dirty; // @[Mux.scala:30:73] wire schedule_c_valid; // @[Mux.scala:30:73] wire schedule_d_bits_prio_0; // @[Mux.scala:30:73] wire schedule_d_bits_prio_1; // @[Mux.scala:30:73] wire schedule_d_bits_prio_2; // @[Mux.scala:30:73] wire schedule_d_bits_control; // @[Mux.scala:30:73] wire [2:0] schedule_d_bits_opcode; // @[Mux.scala:30:73] wire [2:0] schedule_d_bits_param; // @[Mux.scala:30:73] wire [2:0] schedule_d_bits_size; // @[Mux.scala:30:73] wire [5:0] schedule_d_bits_source; // @[Mux.scala:30:73] wire [12:0] schedule_d_bits_tag; // @[Mux.scala:30:73] wire [5:0] schedule_d_bits_offset; // @[Mux.scala:30:73] wire [5:0] schedule_d_bits_put; // @[Mux.scala:30:73] wire [9:0] schedule_d_bits_set; // @[Mux.scala:30:73] wire [2:0] schedule_d_bits_way; // @[Mux.scala:30:73] wire schedule_d_bits_bad; // @[Mux.scala:30:73] wire schedule_d_valid; // @[Mux.scala:30:73] wire [2:0] schedule_e_bits_sink; // @[Mux.scala:30:73] wire schedule_e_valid; // @[Mux.scala:30:73] wire schedule_x_valid; // @[Mux.scala:30:73] wire schedule_dir_bits_data_dirty; // @[Mux.scala:30:73] wire [1:0] schedule_dir_bits_data_state; // @[Mux.scala:30:73] wire [1:0] schedule_dir_bits_data_clients; // @[Mux.scala:30:73] wire [12:0] schedule_dir_bits_data_tag; // @[Mux.scala:30:73] wire [9:0] schedule_dir_bits_set; // @[Mux.scala:30:73] wire [2:0] schedule_dir_bits_way; // @[Mux.scala:30:73] wire schedule_dir_valid; // @[Mux.scala:30:73] wire schedule_reload; // @[Mux.scala:30:73] wire _schedule_T_7 = _schedule_T & _mshrs_0_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36] wire _schedule_T_8 = _schedule_T_1 & _mshrs_1_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36] wire _schedule_T_9 = _schedule_T_2 & _mshrs_2_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36] wire _schedule_T_10 = _schedule_T_3 & _mshrs_3_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36] wire _schedule_T_11 = _schedule_T_4 & _mshrs_4_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36] wire _schedule_T_12 = _schedule_T_5 & _mshrs_5_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36] wire _schedule_T_13 = _schedule_T_6 & _mshrs_6_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36] wire _schedule_T_14 = _schedule_T_7 | _schedule_T_8; // @[Mux.scala:30:73] wire _schedule_T_15 = _schedule_T_14 | _schedule_T_9; // @[Mux.scala:30:73] wire _schedule_T_16 = _schedule_T_15 | _schedule_T_10; // @[Mux.scala:30:73] wire _schedule_T_17 = _schedule_T_16 | _schedule_T_11; // @[Mux.scala:30:73] wire _schedule_T_18 = _schedule_T_17 | _schedule_T_12; // @[Mux.scala:30:73] wire _schedule_T_19 = _schedule_T_18 | _schedule_T_13; // @[Mux.scala:30:73] assign _schedule_WIRE = _schedule_T_19; // @[Mux.scala:30:73] assign schedule_reload = _schedule_WIRE; // @[Mux.scala:30:73] wire _schedule_WIRE_10; // @[Mux.scala:30:73] assign schedule_dir_valid = _schedule_WIRE_1_valid; // @[Mux.scala:30:73] wire [9:0] _schedule_WIRE_2_set; // @[Mux.scala:30:73] assign schedule_dir_bits_set = _schedule_WIRE_1_bits_set; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_2_way; // @[Mux.scala:30:73] assign schedule_dir_bits_way = _schedule_WIRE_1_bits_way; // @[Mux.scala:30:73] wire _schedule_WIRE_2_data_dirty; // @[Mux.scala:30:73] assign schedule_dir_bits_data_dirty = _schedule_WIRE_1_bits_data_dirty; // @[Mux.scala:30:73] wire [1:0] _schedule_WIRE_2_data_state; // @[Mux.scala:30:73] assign schedule_dir_bits_data_state = _schedule_WIRE_1_bits_data_state; // @[Mux.scala:30:73] wire [1:0] _schedule_WIRE_2_data_clients; // @[Mux.scala:30:73] assign schedule_dir_bits_data_clients = _schedule_WIRE_1_bits_data_clients; // @[Mux.scala:30:73] wire [12:0] _schedule_WIRE_2_data_tag; // @[Mux.scala:30:73] assign schedule_dir_bits_data_tag = _schedule_WIRE_1_bits_data_tag; // @[Mux.scala:30:73] wire [9:0] _schedule_WIRE_9; // @[Mux.scala:30:73] assign _schedule_WIRE_1_bits_set = _schedule_WIRE_2_set; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_8; // @[Mux.scala:30:73] assign _schedule_WIRE_1_bits_way = _schedule_WIRE_2_way; // @[Mux.scala:30:73] wire _schedule_WIRE_3_dirty; // @[Mux.scala:30:73] assign _schedule_WIRE_1_bits_data_dirty = _schedule_WIRE_2_data_dirty; // @[Mux.scala:30:73] wire [1:0] _schedule_WIRE_3_state; // @[Mux.scala:30:73] assign _schedule_WIRE_1_bits_data_state = _schedule_WIRE_2_data_state; // @[Mux.scala:30:73] wire [1:0] _schedule_WIRE_3_clients; // @[Mux.scala:30:73] assign _schedule_WIRE_1_bits_data_clients = _schedule_WIRE_2_data_clients; // @[Mux.scala:30:73] wire [12:0] _schedule_WIRE_3_tag; // @[Mux.scala:30:73] assign _schedule_WIRE_1_bits_data_tag = _schedule_WIRE_2_data_tag; // @[Mux.scala:30:73] wire _schedule_WIRE_7; // @[Mux.scala:30:73] assign _schedule_WIRE_2_data_dirty = _schedule_WIRE_3_dirty; // @[Mux.scala:30:73] wire [1:0] _schedule_WIRE_6; // @[Mux.scala:30:73] assign _schedule_WIRE_2_data_state = _schedule_WIRE_3_state; // @[Mux.scala:30:73] wire [1:0] _schedule_WIRE_5; // @[Mux.scala:30:73] assign _schedule_WIRE_2_data_clients = _schedule_WIRE_3_clients; // @[Mux.scala:30:73] wire [12:0] _schedule_WIRE_4; // @[Mux.scala:30:73] assign _schedule_WIRE_2_data_tag = _schedule_WIRE_3_tag; // @[Mux.scala:30:73] wire [12:0] _schedule_T_20 = _schedule_T ? _mshrs_0_io_schedule_bits_dir_bits_data_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_21 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_dir_bits_data_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_22 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_dir_bits_data_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_23 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_dir_bits_data_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_24 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_dir_bits_data_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_25 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_dir_bits_data_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_26 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_dir_bits_data_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_27 = _schedule_T_20 | _schedule_T_21; // @[Mux.scala:30:73] wire [12:0] _schedule_T_28 = _schedule_T_27 | _schedule_T_22; // @[Mux.scala:30:73] wire [12:0] _schedule_T_29 = _schedule_T_28 | _schedule_T_23; // @[Mux.scala:30:73] wire [12:0] _schedule_T_30 = _schedule_T_29 | _schedule_T_24; // @[Mux.scala:30:73] wire [12:0] _schedule_T_31 = _schedule_T_30 | _schedule_T_25; // @[Mux.scala:30:73] wire [12:0] _schedule_T_32 = _schedule_T_31 | _schedule_T_26; // @[Mux.scala:30:73] assign _schedule_WIRE_4 = _schedule_T_32; // @[Mux.scala:30:73] assign _schedule_WIRE_3_tag = _schedule_WIRE_4; // @[Mux.scala:30:73] wire [1:0] _schedule_T_33 = _schedule_T ? _mshrs_0_io_schedule_bits_dir_bits_data_clients : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _schedule_T_34 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_dir_bits_data_clients : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _schedule_T_35 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_dir_bits_data_clients : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _schedule_T_36 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_dir_bits_data_clients : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _schedule_T_37 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_dir_bits_data_clients : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _schedule_T_38 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_dir_bits_data_clients : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _schedule_T_39 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_dir_bits_data_clients : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _schedule_T_40 = _schedule_T_33 | _schedule_T_34; // @[Mux.scala:30:73] wire [1:0] _schedule_T_41 = _schedule_T_40 | _schedule_T_35; // @[Mux.scala:30:73] wire [1:0] _schedule_T_42 = _schedule_T_41 | _schedule_T_36; // @[Mux.scala:30:73] wire [1:0] _schedule_T_43 = _schedule_T_42 | _schedule_T_37; // @[Mux.scala:30:73] wire [1:0] _schedule_T_44 = _schedule_T_43 | _schedule_T_38; // @[Mux.scala:30:73] wire [1:0] _schedule_T_45 = _schedule_T_44 | _schedule_T_39; // @[Mux.scala:30:73] assign _schedule_WIRE_5 = _schedule_T_45; // @[Mux.scala:30:73] assign _schedule_WIRE_3_clients = _schedule_WIRE_5; // @[Mux.scala:30:73] wire [1:0] _schedule_T_46 = _schedule_T ? _mshrs_0_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _schedule_T_47 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _schedule_T_48 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _schedule_T_49 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _schedule_T_50 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _schedule_T_51 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _schedule_T_52 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _schedule_T_53 = _schedule_T_46 | _schedule_T_47; // @[Mux.scala:30:73] wire [1:0] _schedule_T_54 = _schedule_T_53 | _schedule_T_48; // @[Mux.scala:30:73] wire [1:0] _schedule_T_55 = _schedule_T_54 | _schedule_T_49; // @[Mux.scala:30:73] wire [1:0] _schedule_T_56 = _schedule_T_55 | _schedule_T_50; // @[Mux.scala:30:73] wire [1:0] _schedule_T_57 = _schedule_T_56 | _schedule_T_51; // @[Mux.scala:30:73] wire [1:0] _schedule_T_58 = _schedule_T_57 | _schedule_T_52; // @[Mux.scala:30:73] assign _schedule_WIRE_6 = _schedule_T_58; // @[Mux.scala:30:73] assign _schedule_WIRE_3_state = _schedule_WIRE_6; // @[Mux.scala:30:73] wire _schedule_T_59 = _schedule_T & _mshrs_0_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_60 = _schedule_T_1 & _mshrs_1_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_61 = _schedule_T_2 & _mshrs_2_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_62 = _schedule_T_3 & _mshrs_3_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_63 = _schedule_T_4 & _mshrs_4_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_64 = _schedule_T_5 & _mshrs_5_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_65 = _schedule_T_6 & _mshrs_6_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_66 = _schedule_T_59 | _schedule_T_60; // @[Mux.scala:30:73] wire _schedule_T_67 = _schedule_T_66 | _schedule_T_61; // @[Mux.scala:30:73] wire _schedule_T_68 = _schedule_T_67 | _schedule_T_62; // @[Mux.scala:30:73] wire _schedule_T_69 = _schedule_T_68 | _schedule_T_63; // @[Mux.scala:30:73] wire _schedule_T_70 = _schedule_T_69 | _schedule_T_64; // @[Mux.scala:30:73] wire _schedule_T_71 = _schedule_T_70 | _schedule_T_65; // @[Mux.scala:30:73] assign _schedule_WIRE_7 = _schedule_T_71; // @[Mux.scala:30:73] assign _schedule_WIRE_3_dirty = _schedule_WIRE_7; // @[Mux.scala:30:73] wire [2:0] _schedule_T_72 = _schedule_T ? _mshrs_0_io_schedule_bits_dir_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_73 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_dir_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_74 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_dir_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_75 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_dir_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_76 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_dir_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_77 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_dir_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_78 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_dir_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_79 = _schedule_T_72 | _schedule_T_73; // @[Mux.scala:30:73] wire [2:0] _schedule_T_80 = _schedule_T_79 | _schedule_T_74; // @[Mux.scala:30:73] wire [2:0] _schedule_T_81 = _schedule_T_80 | _schedule_T_75; // @[Mux.scala:30:73] wire [2:0] _schedule_T_82 = _schedule_T_81 | _schedule_T_76; // @[Mux.scala:30:73] wire [2:0] _schedule_T_83 = _schedule_T_82 | _schedule_T_77; // @[Mux.scala:30:73] wire [2:0] _schedule_T_84 = _schedule_T_83 | _schedule_T_78; // @[Mux.scala:30:73] assign _schedule_WIRE_8 = _schedule_T_84; // @[Mux.scala:30:73] assign _schedule_WIRE_2_way = _schedule_WIRE_8; // @[Mux.scala:30:73] wire [9:0] _schedule_T_85 = _schedule_T ? _mshrs_0_io_schedule_bits_dir_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_86 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_dir_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_87 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_dir_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_88 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_dir_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_89 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_dir_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_90 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_dir_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_91 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_dir_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_92 = _schedule_T_85 | _schedule_T_86; // @[Mux.scala:30:73] wire [9:0] _schedule_T_93 = _schedule_T_92 | _schedule_T_87; // @[Mux.scala:30:73] wire [9:0] _schedule_T_94 = _schedule_T_93 | _schedule_T_88; // @[Mux.scala:30:73] wire [9:0] _schedule_T_95 = _schedule_T_94 | _schedule_T_89; // @[Mux.scala:30:73] wire [9:0] _schedule_T_96 = _schedule_T_95 | _schedule_T_90; // @[Mux.scala:30:73] wire [9:0] _schedule_T_97 = _schedule_T_96 | _schedule_T_91; // @[Mux.scala:30:73] assign _schedule_WIRE_9 = _schedule_T_97; // @[Mux.scala:30:73] assign _schedule_WIRE_2_set = _schedule_WIRE_9; // @[Mux.scala:30:73] wire _schedule_T_98 = _schedule_T & _mshrs_0_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_99 = _schedule_T_1 & _mshrs_1_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_100 = _schedule_T_2 & _mshrs_2_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_101 = _schedule_T_3 & _mshrs_3_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_102 = _schedule_T_4 & _mshrs_4_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_103 = _schedule_T_5 & _mshrs_5_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_104 = _schedule_T_6 & _mshrs_6_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_105 = _schedule_T_98 | _schedule_T_99; // @[Mux.scala:30:73] wire _schedule_T_106 = _schedule_T_105 | _schedule_T_100; // @[Mux.scala:30:73] wire _schedule_T_107 = _schedule_T_106 | _schedule_T_101; // @[Mux.scala:30:73] wire _schedule_T_108 = _schedule_T_107 | _schedule_T_102; // @[Mux.scala:30:73] wire _schedule_T_109 = _schedule_T_108 | _schedule_T_103; // @[Mux.scala:30:73] wire _schedule_T_110 = _schedule_T_109 | _schedule_T_104; // @[Mux.scala:30:73] assign _schedule_WIRE_10 = _schedule_T_110; // @[Mux.scala:30:73] assign _schedule_WIRE_1_valid = _schedule_WIRE_10; // @[Mux.scala:30:73] wire _schedule_WIRE_14; // @[Mux.scala:30:73] assign schedule_x_valid = _schedule_WIRE_11_valid; // @[Mux.scala:30:73] wire _schedule_T_124 = _schedule_T & _mshrs_0_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_125 = _schedule_T_1 & _mshrs_1_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_126 = _schedule_T_2 & _mshrs_2_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_127 = _schedule_T_3 & _mshrs_3_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_128 = _schedule_T_4 & _mshrs_4_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_129 = _schedule_T_5 & _mshrs_5_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_130 = _schedule_T_6 & _mshrs_6_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_131 = _schedule_T_124 | _schedule_T_125; // @[Mux.scala:30:73] wire _schedule_T_132 = _schedule_T_131 | _schedule_T_126; // @[Mux.scala:30:73] wire _schedule_T_133 = _schedule_T_132 | _schedule_T_127; // @[Mux.scala:30:73] wire _schedule_T_134 = _schedule_T_133 | _schedule_T_128; // @[Mux.scala:30:73] wire _schedule_T_135 = _schedule_T_134 | _schedule_T_129; // @[Mux.scala:30:73] wire _schedule_T_136 = _schedule_T_135 | _schedule_T_130; // @[Mux.scala:30:73] assign _schedule_WIRE_14 = _schedule_T_136; // @[Mux.scala:30:73] assign _schedule_WIRE_11_valid = _schedule_WIRE_14; // @[Mux.scala:30:73] wire _schedule_WIRE_18; // @[Mux.scala:30:73] assign schedule_e_valid = _schedule_WIRE_15_valid; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_16_sink; // @[Mux.scala:30:73] assign schedule_e_bits_sink = _schedule_WIRE_15_bits_sink; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_17; // @[Mux.scala:30:73] assign _schedule_WIRE_15_bits_sink = _schedule_WIRE_16_sink; // @[Mux.scala:30:73] wire [2:0] _schedule_T_137 = _schedule_T ? _mshrs_0_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_138 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_139 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_140 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_141 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_142 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_143 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_144 = _schedule_T_137 | _schedule_T_138; // @[Mux.scala:30:73] wire [2:0] _schedule_T_145 = _schedule_T_144 | _schedule_T_139; // @[Mux.scala:30:73] wire [2:0] _schedule_T_146 = _schedule_T_145 | _schedule_T_140; // @[Mux.scala:30:73] wire [2:0] _schedule_T_147 = _schedule_T_146 | _schedule_T_141; // @[Mux.scala:30:73] wire [2:0] _schedule_T_148 = _schedule_T_147 | _schedule_T_142; // @[Mux.scala:30:73] wire [2:0] _schedule_T_149 = _schedule_T_148 | _schedule_T_143; // @[Mux.scala:30:73] assign _schedule_WIRE_17 = _schedule_T_149; // @[Mux.scala:30:73] assign _schedule_WIRE_16_sink = _schedule_WIRE_17; // @[Mux.scala:30:73] wire _schedule_T_150 = _schedule_T & _mshrs_0_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_151 = _schedule_T_1 & _mshrs_1_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_152 = _schedule_T_2 & _mshrs_2_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_153 = _schedule_T_3 & _mshrs_3_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_154 = _schedule_T_4 & _mshrs_4_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_155 = _schedule_T_5 & _mshrs_5_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_156 = _schedule_T_6 & _mshrs_6_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_157 = _schedule_T_150 | _schedule_T_151; // @[Mux.scala:30:73] wire _schedule_T_158 = _schedule_T_157 | _schedule_T_152; // @[Mux.scala:30:73] wire _schedule_T_159 = _schedule_T_158 | _schedule_T_153; // @[Mux.scala:30:73] wire _schedule_T_160 = _schedule_T_159 | _schedule_T_154; // @[Mux.scala:30:73] wire _schedule_T_161 = _schedule_T_160 | _schedule_T_155; // @[Mux.scala:30:73] wire _schedule_T_162 = _schedule_T_161 | _schedule_T_156; // @[Mux.scala:30:73] assign _schedule_WIRE_18 = _schedule_T_162; // @[Mux.scala:30:73] assign _schedule_WIRE_15_valid = _schedule_WIRE_18; // @[Mux.scala:30:73] wire _schedule_WIRE_37; // @[Mux.scala:30:73] assign schedule_d_valid = _schedule_WIRE_19_valid; // @[Mux.scala:30:73] wire _schedule_WIRE_20_prio_0; // @[Mux.scala:30:73] assign schedule_d_bits_prio_0 = _schedule_WIRE_19_bits_prio_0; // @[Mux.scala:30:73] wire _schedule_WIRE_20_prio_1; // @[Mux.scala:30:73] assign schedule_d_bits_prio_1 = _schedule_WIRE_19_bits_prio_1; // @[Mux.scala:30:73] wire _schedule_WIRE_20_prio_2; // @[Mux.scala:30:73] assign schedule_d_bits_prio_2 = _schedule_WIRE_19_bits_prio_2; // @[Mux.scala:30:73] wire _schedule_WIRE_20_control; // @[Mux.scala:30:73] assign schedule_d_bits_control = _schedule_WIRE_19_bits_control; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_20_opcode; // @[Mux.scala:30:73] assign schedule_d_bits_opcode = _schedule_WIRE_19_bits_opcode; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_20_param; // @[Mux.scala:30:73] assign schedule_d_bits_param = _schedule_WIRE_19_bits_param; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_20_size; // @[Mux.scala:30:73] assign schedule_d_bits_size = _schedule_WIRE_19_bits_size; // @[Mux.scala:30:73] wire [5:0] _schedule_WIRE_20_source; // @[Mux.scala:30:73] assign schedule_d_bits_source = _schedule_WIRE_19_bits_source; // @[Mux.scala:30:73] wire [12:0] _schedule_WIRE_20_tag; // @[Mux.scala:30:73] assign schedule_d_bits_tag = _schedule_WIRE_19_bits_tag; // @[Mux.scala:30:73] wire [5:0] _schedule_WIRE_20_offset; // @[Mux.scala:30:73] assign schedule_d_bits_offset = _schedule_WIRE_19_bits_offset; // @[Mux.scala:30:73] wire [5:0] _schedule_WIRE_20_put; // @[Mux.scala:30:73] assign schedule_d_bits_put = _schedule_WIRE_19_bits_put; // @[Mux.scala:30:73] wire [9:0] _schedule_WIRE_20_set; // @[Mux.scala:30:73] assign schedule_d_bits_set = _schedule_WIRE_19_bits_set; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_20_way; // @[Mux.scala:30:73] assign schedule_d_bits_way = _schedule_WIRE_19_bits_way; // @[Mux.scala:30:73] wire _schedule_WIRE_20_bad; // @[Mux.scala:30:73] assign schedule_d_bits_bad = _schedule_WIRE_19_bits_bad; // @[Mux.scala:30:73] wire _schedule_WIRE_33_0; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_prio_0 = _schedule_WIRE_20_prio_0; // @[Mux.scala:30:73] wire _schedule_WIRE_33_1; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_prio_1 = _schedule_WIRE_20_prio_1; // @[Mux.scala:30:73] wire _schedule_WIRE_33_2; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_prio_2 = _schedule_WIRE_20_prio_2; // @[Mux.scala:30:73] wire _schedule_WIRE_32; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_control = _schedule_WIRE_20_control; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_31; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_opcode = _schedule_WIRE_20_opcode; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_30; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_param = _schedule_WIRE_20_param; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_29; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_size = _schedule_WIRE_20_size; // @[Mux.scala:30:73] wire [5:0] _schedule_WIRE_28; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_source = _schedule_WIRE_20_source; // @[Mux.scala:30:73] wire [12:0] _schedule_WIRE_27; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_tag = _schedule_WIRE_20_tag; // @[Mux.scala:30:73] wire [5:0] _schedule_WIRE_26; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_offset = _schedule_WIRE_20_offset; // @[Mux.scala:30:73] wire [5:0] _schedule_WIRE_25; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_put = _schedule_WIRE_20_put; // @[Mux.scala:30:73] wire [9:0] _schedule_WIRE_24; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_set = _schedule_WIRE_20_set; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_22; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_way = _schedule_WIRE_20_way; // @[Mux.scala:30:73] wire _schedule_WIRE_21; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_bad = _schedule_WIRE_20_bad; // @[Mux.scala:30:73] wire _schedule_T_163 = _schedule_T & _mshrs_0_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36] wire _schedule_T_164 = _schedule_T_1 & _mshrs_1_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36] wire _schedule_T_165 = _schedule_T_2 & _mshrs_2_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36] wire _schedule_T_166 = _schedule_T_3 & _mshrs_3_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36] wire _schedule_T_167 = _schedule_T_4 & _mshrs_4_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36] wire _schedule_T_168 = _schedule_T_5 & _mshrs_5_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36] wire _schedule_T_169 = _schedule_T_6 & _mshrs_6_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36] wire _schedule_T_170 = _schedule_T_163 | _schedule_T_164; // @[Mux.scala:30:73] wire _schedule_T_171 = _schedule_T_170 | _schedule_T_165; // @[Mux.scala:30:73] wire _schedule_T_172 = _schedule_T_171 | _schedule_T_166; // @[Mux.scala:30:73] wire _schedule_T_173 = _schedule_T_172 | _schedule_T_167; // @[Mux.scala:30:73] wire _schedule_T_174 = _schedule_T_173 | _schedule_T_168; // @[Mux.scala:30:73] wire _schedule_T_175 = _schedule_T_174 | _schedule_T_169; // @[Mux.scala:30:73] assign _schedule_WIRE_21 = _schedule_T_175; // @[Mux.scala:30:73] assign _schedule_WIRE_20_bad = _schedule_WIRE_21; // @[Mux.scala:30:73] wire [2:0] _schedule_T_176 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_177 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_178 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_179 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_180 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_181 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_182 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_183 = _schedule_T_176 | _schedule_T_177; // @[Mux.scala:30:73] wire [2:0] _schedule_T_184 = _schedule_T_183 | _schedule_T_178; // @[Mux.scala:30:73] wire [2:0] _schedule_T_185 = _schedule_T_184 | _schedule_T_179; // @[Mux.scala:30:73] wire [2:0] _schedule_T_186 = _schedule_T_185 | _schedule_T_180; // @[Mux.scala:30:73] wire [2:0] _schedule_T_187 = _schedule_T_186 | _schedule_T_181; // @[Mux.scala:30:73] wire [2:0] _schedule_T_188 = _schedule_T_187 | _schedule_T_182; // @[Mux.scala:30:73] assign _schedule_WIRE_22 = _schedule_T_188; // @[Mux.scala:30:73] assign _schedule_WIRE_20_way = _schedule_WIRE_22; // @[Mux.scala:30:73] wire [9:0] _schedule_T_202 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_203 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_204 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_205 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_206 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_207 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_208 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_209 = _schedule_T_202 | _schedule_T_203; // @[Mux.scala:30:73] wire [9:0] _schedule_T_210 = _schedule_T_209 | _schedule_T_204; // @[Mux.scala:30:73] wire [9:0] _schedule_T_211 = _schedule_T_210 | _schedule_T_205; // @[Mux.scala:30:73] wire [9:0] _schedule_T_212 = _schedule_T_211 | _schedule_T_206; // @[Mux.scala:30:73] wire [9:0] _schedule_T_213 = _schedule_T_212 | _schedule_T_207; // @[Mux.scala:30:73] wire [9:0] _schedule_T_214 = _schedule_T_213 | _schedule_T_208; // @[Mux.scala:30:73] assign _schedule_WIRE_24 = _schedule_T_214; // @[Mux.scala:30:73] assign _schedule_WIRE_20_set = _schedule_WIRE_24; // @[Mux.scala:30:73] wire [5:0] _schedule_T_215 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_216 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_217 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_218 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_219 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_220 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_221 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_222 = _schedule_T_215 | _schedule_T_216; // @[Mux.scala:30:73] wire [5:0] _schedule_T_223 = _schedule_T_222 | _schedule_T_217; // @[Mux.scala:30:73] wire [5:0] _schedule_T_224 = _schedule_T_223 | _schedule_T_218; // @[Mux.scala:30:73] wire [5:0] _schedule_T_225 = _schedule_T_224 | _schedule_T_219; // @[Mux.scala:30:73] wire [5:0] _schedule_T_226 = _schedule_T_225 | _schedule_T_220; // @[Mux.scala:30:73] wire [5:0] _schedule_T_227 = _schedule_T_226 | _schedule_T_221; // @[Mux.scala:30:73] assign _schedule_WIRE_25 = _schedule_T_227; // @[Mux.scala:30:73] assign _schedule_WIRE_20_put = _schedule_WIRE_25; // @[Mux.scala:30:73] wire [5:0] _schedule_T_228 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_229 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_230 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_231 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_232 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_233 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_234 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_235 = _schedule_T_228 | _schedule_T_229; // @[Mux.scala:30:73] wire [5:0] _schedule_T_236 = _schedule_T_235 | _schedule_T_230; // @[Mux.scala:30:73] wire [5:0] _schedule_T_237 = _schedule_T_236 | _schedule_T_231; // @[Mux.scala:30:73] wire [5:0] _schedule_T_238 = _schedule_T_237 | _schedule_T_232; // @[Mux.scala:30:73] wire [5:0] _schedule_T_239 = _schedule_T_238 | _schedule_T_233; // @[Mux.scala:30:73] wire [5:0] _schedule_T_240 = _schedule_T_239 | _schedule_T_234; // @[Mux.scala:30:73] assign _schedule_WIRE_26 = _schedule_T_240; // @[Mux.scala:30:73] assign _schedule_WIRE_20_offset = _schedule_WIRE_26; // @[Mux.scala:30:73] wire [12:0] _schedule_T_241 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_242 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_243 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_244 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_245 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_246 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_247 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_248 = _schedule_T_241 | _schedule_T_242; // @[Mux.scala:30:73] wire [12:0] _schedule_T_249 = _schedule_T_248 | _schedule_T_243; // @[Mux.scala:30:73] wire [12:0] _schedule_T_250 = _schedule_T_249 | _schedule_T_244; // @[Mux.scala:30:73] wire [12:0] _schedule_T_251 = _schedule_T_250 | _schedule_T_245; // @[Mux.scala:30:73] wire [12:0] _schedule_T_252 = _schedule_T_251 | _schedule_T_246; // @[Mux.scala:30:73] wire [12:0] _schedule_T_253 = _schedule_T_252 | _schedule_T_247; // @[Mux.scala:30:73] assign _schedule_WIRE_27 = _schedule_T_253; // @[Mux.scala:30:73] assign _schedule_WIRE_20_tag = _schedule_WIRE_27; // @[Mux.scala:30:73] wire [5:0] _schedule_T_254 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_255 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_256 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_257 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_258 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_259 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_260 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_261 = _schedule_T_254 | _schedule_T_255; // @[Mux.scala:30:73] wire [5:0] _schedule_T_262 = _schedule_T_261 | _schedule_T_256; // @[Mux.scala:30:73] wire [5:0] _schedule_T_263 = _schedule_T_262 | _schedule_T_257; // @[Mux.scala:30:73] wire [5:0] _schedule_T_264 = _schedule_T_263 | _schedule_T_258; // @[Mux.scala:30:73] wire [5:0] _schedule_T_265 = _schedule_T_264 | _schedule_T_259; // @[Mux.scala:30:73] wire [5:0] _schedule_T_266 = _schedule_T_265 | _schedule_T_260; // @[Mux.scala:30:73] assign _schedule_WIRE_28 = _schedule_T_266; // @[Mux.scala:30:73] assign _schedule_WIRE_20_source = _schedule_WIRE_28; // @[Mux.scala:30:73] wire [2:0] _schedule_T_267 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_268 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_269 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_270 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_271 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_272 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_273 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_274 = _schedule_T_267 | _schedule_T_268; // @[Mux.scala:30:73] wire [2:0] _schedule_T_275 = _schedule_T_274 | _schedule_T_269; // @[Mux.scala:30:73] wire [2:0] _schedule_T_276 = _schedule_T_275 | _schedule_T_270; // @[Mux.scala:30:73] wire [2:0] _schedule_T_277 = _schedule_T_276 | _schedule_T_271; // @[Mux.scala:30:73] wire [2:0] _schedule_T_278 = _schedule_T_277 | _schedule_T_272; // @[Mux.scala:30:73] wire [2:0] _schedule_T_279 = _schedule_T_278 | _schedule_T_273; // @[Mux.scala:30:73] assign _schedule_WIRE_29 = _schedule_T_279; // @[Mux.scala:30:73] assign _schedule_WIRE_20_size = _schedule_WIRE_29; // @[Mux.scala:30:73] wire [2:0] _schedule_T_280 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_281 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_282 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_283 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_284 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_285 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_286 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_287 = _schedule_T_280 | _schedule_T_281; // @[Mux.scala:30:73] wire [2:0] _schedule_T_288 = _schedule_T_287 | _schedule_T_282; // @[Mux.scala:30:73] wire [2:0] _schedule_T_289 = _schedule_T_288 | _schedule_T_283; // @[Mux.scala:30:73] wire [2:0] _schedule_T_290 = _schedule_T_289 | _schedule_T_284; // @[Mux.scala:30:73] wire [2:0] _schedule_T_291 = _schedule_T_290 | _schedule_T_285; // @[Mux.scala:30:73] wire [2:0] _schedule_T_292 = _schedule_T_291 | _schedule_T_286; // @[Mux.scala:30:73] assign _schedule_WIRE_30 = _schedule_T_292; // @[Mux.scala:30:73] assign _schedule_WIRE_20_param = _schedule_WIRE_30; // @[Mux.scala:30:73] wire [2:0] _schedule_T_293 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_294 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_295 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_296 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_297 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_298 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_299 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_300 = _schedule_T_293 | _schedule_T_294; // @[Mux.scala:30:73] wire [2:0] _schedule_T_301 = _schedule_T_300 | _schedule_T_295; // @[Mux.scala:30:73] wire [2:0] _schedule_T_302 = _schedule_T_301 | _schedule_T_296; // @[Mux.scala:30:73] wire [2:0] _schedule_T_303 = _schedule_T_302 | _schedule_T_297; // @[Mux.scala:30:73] wire [2:0] _schedule_T_304 = _schedule_T_303 | _schedule_T_298; // @[Mux.scala:30:73] wire [2:0] _schedule_T_305 = _schedule_T_304 | _schedule_T_299; // @[Mux.scala:30:73] assign _schedule_WIRE_31 = _schedule_T_305; // @[Mux.scala:30:73] assign _schedule_WIRE_20_opcode = _schedule_WIRE_31; // @[Mux.scala:30:73] wire _schedule_T_306 = _schedule_T & _mshrs_0_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36] wire _schedule_T_307 = _schedule_T_1 & _mshrs_1_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36] wire _schedule_T_308 = _schedule_T_2 & _mshrs_2_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36] wire _schedule_T_309 = _schedule_T_3 & _mshrs_3_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36] wire _schedule_T_310 = _schedule_T_4 & _mshrs_4_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36] wire _schedule_T_311 = _schedule_T_5 & _mshrs_5_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36] wire _schedule_T_312 = _schedule_T_6 & _mshrs_6_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36] wire _schedule_T_313 = _schedule_T_306 | _schedule_T_307; // @[Mux.scala:30:73] wire _schedule_T_314 = _schedule_T_313 | _schedule_T_308; // @[Mux.scala:30:73] wire _schedule_T_315 = _schedule_T_314 | _schedule_T_309; // @[Mux.scala:30:73] wire _schedule_T_316 = _schedule_T_315 | _schedule_T_310; // @[Mux.scala:30:73] wire _schedule_T_317 = _schedule_T_316 | _schedule_T_311; // @[Mux.scala:30:73] wire _schedule_T_318 = _schedule_T_317 | _schedule_T_312; // @[Mux.scala:30:73] assign _schedule_WIRE_32 = _schedule_T_318; // @[Mux.scala:30:73] assign _schedule_WIRE_20_control = _schedule_WIRE_32; // @[Mux.scala:30:73] wire _schedule_WIRE_34; // @[Mux.scala:30:73] assign _schedule_WIRE_20_prio_0 = _schedule_WIRE_33_0; // @[Mux.scala:30:73] wire _schedule_WIRE_35; // @[Mux.scala:30:73] assign _schedule_WIRE_20_prio_1 = _schedule_WIRE_33_1; // @[Mux.scala:30:73] wire _schedule_WIRE_36; // @[Mux.scala:30:73] assign _schedule_WIRE_20_prio_2 = _schedule_WIRE_33_2; // @[Mux.scala:30:73] wire _schedule_T_319 = _schedule_T & _mshrs_0_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36] wire _schedule_T_320 = _schedule_T_1 & _mshrs_1_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36] wire _schedule_T_321 = _schedule_T_2 & _mshrs_2_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36] wire _schedule_T_322 = _schedule_T_3 & _mshrs_3_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36] wire _schedule_T_323 = _schedule_T_4 & _mshrs_4_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36] wire _schedule_T_326 = _schedule_T_319 | _schedule_T_320; // @[Mux.scala:30:73] wire _schedule_T_327 = _schedule_T_326 | _schedule_T_321; // @[Mux.scala:30:73] wire _schedule_T_328 = _schedule_T_327 | _schedule_T_322; // @[Mux.scala:30:73] wire _schedule_T_329 = _schedule_T_328 | _schedule_T_323; // @[Mux.scala:30:73] wire _schedule_T_330 = _schedule_T_329; // @[Mux.scala:30:73] wire _schedule_T_331 = _schedule_T_330; // @[Mux.scala:30:73] assign _schedule_WIRE_34 = _schedule_T_331; // @[Mux.scala:30:73] assign _schedule_WIRE_33_0 = _schedule_WIRE_34; // @[Mux.scala:30:73] wire _schedule_T_332 = _schedule_T & _mshrs_0_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36] wire _schedule_T_333 = _schedule_T_1 & _mshrs_1_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36] wire _schedule_T_334 = _schedule_T_2 & _mshrs_2_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36] wire _schedule_T_335 = _schedule_T_3 & _mshrs_3_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36] wire _schedule_T_336 = _schedule_T_4 & _mshrs_4_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36] wire _schedule_T_337 = _schedule_T_5 & _mshrs_5_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36] wire _schedule_T_339 = _schedule_T_332 | _schedule_T_333; // @[Mux.scala:30:73] wire _schedule_T_340 = _schedule_T_339 | _schedule_T_334; // @[Mux.scala:30:73] wire _schedule_T_341 = _schedule_T_340 | _schedule_T_335; // @[Mux.scala:30:73] wire _schedule_T_342 = _schedule_T_341 | _schedule_T_336; // @[Mux.scala:30:73] wire _schedule_T_343 = _schedule_T_342 | _schedule_T_337; // @[Mux.scala:30:73] wire _schedule_T_344 = _schedule_T_343; // @[Mux.scala:30:73] assign _schedule_WIRE_35 = _schedule_T_344; // @[Mux.scala:30:73] assign _schedule_WIRE_33_1 = _schedule_WIRE_35; // @[Mux.scala:30:73] wire _schedule_T_345 = _schedule_T & _mshrs_0_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36] wire _schedule_T_346 = _schedule_T_1 & _mshrs_1_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36] wire _schedule_T_347 = _schedule_T_2 & _mshrs_2_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36] wire _schedule_T_348 = _schedule_T_3 & _mshrs_3_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36] wire _schedule_T_349 = _schedule_T_4 & _mshrs_4_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36] wire _schedule_T_350 = _schedule_T_5 & _mshrs_5_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36] wire _schedule_T_351 = _schedule_T_6 & _mshrs_6_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36] wire _schedule_T_352 = _schedule_T_345 | _schedule_T_346; // @[Mux.scala:30:73] wire _schedule_T_353 = _schedule_T_352 | _schedule_T_347; // @[Mux.scala:30:73] wire _schedule_T_354 = _schedule_T_353 | _schedule_T_348; // @[Mux.scala:30:73] wire _schedule_T_355 = _schedule_T_354 | _schedule_T_349; // @[Mux.scala:30:73] wire _schedule_T_356 = _schedule_T_355 | _schedule_T_350; // @[Mux.scala:30:73] wire _schedule_T_357 = _schedule_T_356 | _schedule_T_351; // @[Mux.scala:30:73] assign _schedule_WIRE_36 = _schedule_T_357; // @[Mux.scala:30:73] assign _schedule_WIRE_33_2 = _schedule_WIRE_36; // @[Mux.scala:30:73] wire _schedule_T_358 = _schedule_T & _mshrs_0_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_359 = _schedule_T_1 & _mshrs_1_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_360 = _schedule_T_2 & _mshrs_2_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_361 = _schedule_T_3 & _mshrs_3_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_362 = _schedule_T_4 & _mshrs_4_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_363 = _schedule_T_5 & _mshrs_5_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_364 = _schedule_T_6 & _mshrs_6_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_365 = _schedule_T_358 | _schedule_T_359; // @[Mux.scala:30:73] wire _schedule_T_366 = _schedule_T_365 | _schedule_T_360; // @[Mux.scala:30:73] wire _schedule_T_367 = _schedule_T_366 | _schedule_T_361; // @[Mux.scala:30:73] wire _schedule_T_368 = _schedule_T_367 | _schedule_T_362; // @[Mux.scala:30:73] wire _schedule_T_369 = _schedule_T_368 | _schedule_T_363; // @[Mux.scala:30:73] wire _schedule_T_370 = _schedule_T_369 | _schedule_T_364; // @[Mux.scala:30:73] assign _schedule_WIRE_37 = _schedule_T_370; // @[Mux.scala:30:73] assign _schedule_WIRE_19_valid = _schedule_WIRE_37; // @[Mux.scala:30:73] wire _schedule_WIRE_47; // @[Mux.scala:30:73] assign schedule_c_valid = _schedule_WIRE_38_valid; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_39_opcode; // @[Mux.scala:30:73] assign schedule_c_bits_opcode = _schedule_WIRE_38_bits_opcode; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_39_param; // @[Mux.scala:30:73] assign schedule_c_bits_param = _schedule_WIRE_38_bits_param; // @[Mux.scala:30:73] wire [12:0] _schedule_WIRE_39_tag; // @[Mux.scala:30:73] assign schedule_c_bits_tag = _schedule_WIRE_38_bits_tag; // @[Mux.scala:30:73] wire [9:0] _schedule_WIRE_39_set; // @[Mux.scala:30:73] assign schedule_c_bits_set = _schedule_WIRE_38_bits_set; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_39_way; // @[Mux.scala:30:73] assign schedule_c_bits_way = _schedule_WIRE_38_bits_way; // @[Mux.scala:30:73] wire _schedule_WIRE_39_dirty; // @[Mux.scala:30:73] assign schedule_c_bits_dirty = _schedule_WIRE_38_bits_dirty; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_46; // @[Mux.scala:30:73] assign _schedule_WIRE_38_bits_opcode = _schedule_WIRE_39_opcode; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_45; // @[Mux.scala:30:73] assign _schedule_WIRE_38_bits_param = _schedule_WIRE_39_param; // @[Mux.scala:30:73] wire [12:0] _schedule_WIRE_43; // @[Mux.scala:30:73] assign _schedule_WIRE_38_bits_tag = _schedule_WIRE_39_tag; // @[Mux.scala:30:73] wire [9:0] _schedule_WIRE_42; // @[Mux.scala:30:73] assign _schedule_WIRE_38_bits_set = _schedule_WIRE_39_set; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_41; // @[Mux.scala:30:73] assign _schedule_WIRE_38_bits_way = _schedule_WIRE_39_way; // @[Mux.scala:30:73] wire _schedule_WIRE_40; // @[Mux.scala:30:73] assign _schedule_WIRE_38_bits_dirty = _schedule_WIRE_39_dirty; // @[Mux.scala:30:73] wire _schedule_T_371 = _schedule_T & _mshrs_0_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_372 = _schedule_T_1 & _mshrs_1_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_373 = _schedule_T_2 & _mshrs_2_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_374 = _schedule_T_3 & _mshrs_3_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_375 = _schedule_T_4 & _mshrs_4_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_376 = _schedule_T_5 & _mshrs_5_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_377 = _schedule_T_6 & _mshrs_6_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_378 = _schedule_T_371 | _schedule_T_372; // @[Mux.scala:30:73] wire _schedule_T_379 = _schedule_T_378 | _schedule_T_373; // @[Mux.scala:30:73] wire _schedule_T_380 = _schedule_T_379 | _schedule_T_374; // @[Mux.scala:30:73] wire _schedule_T_381 = _schedule_T_380 | _schedule_T_375; // @[Mux.scala:30:73] wire _schedule_T_382 = _schedule_T_381 | _schedule_T_376; // @[Mux.scala:30:73] wire _schedule_T_383 = _schedule_T_382 | _schedule_T_377; // @[Mux.scala:30:73] assign _schedule_WIRE_40 = _schedule_T_383; // @[Mux.scala:30:73] assign _schedule_WIRE_39_dirty = _schedule_WIRE_40; // @[Mux.scala:30:73] wire [2:0] _schedule_T_384 = _schedule_T ? _mshrs_0_io_schedule_bits_c_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_385 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_c_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_386 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_c_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_387 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_c_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_388 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_c_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_389 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_c_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_390 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_c_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_391 = _schedule_T_384 | _schedule_T_385; // @[Mux.scala:30:73] wire [2:0] _schedule_T_392 = _schedule_T_391 | _schedule_T_386; // @[Mux.scala:30:73] wire [2:0] _schedule_T_393 = _schedule_T_392 | _schedule_T_387; // @[Mux.scala:30:73] wire [2:0] _schedule_T_394 = _schedule_T_393 | _schedule_T_388; // @[Mux.scala:30:73] wire [2:0] _schedule_T_395 = _schedule_T_394 | _schedule_T_389; // @[Mux.scala:30:73] wire [2:0] _schedule_T_396 = _schedule_T_395 | _schedule_T_390; // @[Mux.scala:30:73] assign _schedule_WIRE_41 = _schedule_T_396; // @[Mux.scala:30:73] assign _schedule_WIRE_39_way = _schedule_WIRE_41; // @[Mux.scala:30:73] wire [9:0] _schedule_T_397 = _schedule_T ? _mshrs_0_io_schedule_bits_c_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_398 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_c_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_399 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_c_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_400 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_c_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_401 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_c_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_402 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_c_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_403 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_c_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_404 = _schedule_T_397 | _schedule_T_398; // @[Mux.scala:30:73] wire [9:0] _schedule_T_405 = _schedule_T_404 | _schedule_T_399; // @[Mux.scala:30:73] wire [9:0] _schedule_T_406 = _schedule_T_405 | _schedule_T_400; // @[Mux.scala:30:73] wire [9:0] _schedule_T_407 = _schedule_T_406 | _schedule_T_401; // @[Mux.scala:30:73] wire [9:0] _schedule_T_408 = _schedule_T_407 | _schedule_T_402; // @[Mux.scala:30:73] wire [9:0] _schedule_T_409 = _schedule_T_408 | _schedule_T_403; // @[Mux.scala:30:73] assign _schedule_WIRE_42 = _schedule_T_409; // @[Mux.scala:30:73] assign _schedule_WIRE_39_set = _schedule_WIRE_42; // @[Mux.scala:30:73] wire [12:0] _schedule_T_410 = _schedule_T ? _mshrs_0_io_schedule_bits_c_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_411 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_c_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_412 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_c_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_413 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_c_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_414 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_c_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_415 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_c_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_416 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_c_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_417 = _schedule_T_410 | _schedule_T_411; // @[Mux.scala:30:73] wire [12:0] _schedule_T_418 = _schedule_T_417 | _schedule_T_412; // @[Mux.scala:30:73] wire [12:0] _schedule_T_419 = _schedule_T_418 | _schedule_T_413; // @[Mux.scala:30:73] wire [12:0] _schedule_T_420 = _schedule_T_419 | _schedule_T_414; // @[Mux.scala:30:73] wire [12:0] _schedule_T_421 = _schedule_T_420 | _schedule_T_415; // @[Mux.scala:30:73] wire [12:0] _schedule_T_422 = _schedule_T_421 | _schedule_T_416; // @[Mux.scala:30:73] assign _schedule_WIRE_43 = _schedule_T_422; // @[Mux.scala:30:73] assign _schedule_WIRE_39_tag = _schedule_WIRE_43; // @[Mux.scala:30:73] wire [2:0] _schedule_T_436 = _schedule_T ? _mshrs_0_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_437 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_438 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_439 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_440 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_441 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_442 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_443 = _schedule_T_436 | _schedule_T_437; // @[Mux.scala:30:73] wire [2:0] _schedule_T_444 = _schedule_T_443 | _schedule_T_438; // @[Mux.scala:30:73] wire [2:0] _schedule_T_445 = _schedule_T_444 | _schedule_T_439; // @[Mux.scala:30:73] wire [2:0] _schedule_T_446 = _schedule_T_445 | _schedule_T_440; // @[Mux.scala:30:73] wire [2:0] _schedule_T_447 = _schedule_T_446 | _schedule_T_441; // @[Mux.scala:30:73] wire [2:0] _schedule_T_448 = _schedule_T_447 | _schedule_T_442; // @[Mux.scala:30:73] assign _schedule_WIRE_45 = _schedule_T_448; // @[Mux.scala:30:73] assign _schedule_WIRE_39_param = _schedule_WIRE_45; // @[Mux.scala:30:73] wire [2:0] _schedule_T_449 = _schedule_T ? _mshrs_0_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_450 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_451 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_452 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_453 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_454 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_455 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_456 = _schedule_T_449 | _schedule_T_450; // @[Mux.scala:30:73] wire [2:0] _schedule_T_457 = _schedule_T_456 | _schedule_T_451; // @[Mux.scala:30:73] wire [2:0] _schedule_T_458 = _schedule_T_457 | _schedule_T_452; // @[Mux.scala:30:73] wire [2:0] _schedule_T_459 = _schedule_T_458 | _schedule_T_453; // @[Mux.scala:30:73] wire [2:0] _schedule_T_460 = _schedule_T_459 | _schedule_T_454; // @[Mux.scala:30:73] wire [2:0] _schedule_T_461 = _schedule_T_460 | _schedule_T_455; // @[Mux.scala:30:73] assign _schedule_WIRE_46 = _schedule_T_461; // @[Mux.scala:30:73] assign _schedule_WIRE_39_opcode = _schedule_WIRE_46; // @[Mux.scala:30:73] wire _schedule_T_462 = _schedule_T & _mshrs_0_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_463 = _schedule_T_1 & _mshrs_1_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_464 = _schedule_T_2 & _mshrs_2_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_465 = _schedule_T_3 & _mshrs_3_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_466 = _schedule_T_4 & _mshrs_4_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_467 = _schedule_T_5 & _mshrs_5_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_468 = _schedule_T_6 & _mshrs_6_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_469 = _schedule_T_462 | _schedule_T_463; // @[Mux.scala:30:73] wire _schedule_T_470 = _schedule_T_469 | _schedule_T_464; // @[Mux.scala:30:73] wire _schedule_T_471 = _schedule_T_470 | _schedule_T_465; // @[Mux.scala:30:73] wire _schedule_T_472 = _schedule_T_471 | _schedule_T_466; // @[Mux.scala:30:73] wire _schedule_T_473 = _schedule_T_472 | _schedule_T_467; // @[Mux.scala:30:73] wire _schedule_T_474 = _schedule_T_473 | _schedule_T_468; // @[Mux.scala:30:73] assign _schedule_WIRE_47 = _schedule_T_474; // @[Mux.scala:30:73] assign _schedule_WIRE_38_valid = _schedule_WIRE_47; // @[Mux.scala:30:73] wire _schedule_WIRE_54; // @[Mux.scala:30:73] assign schedule_b_valid = _schedule_WIRE_48_valid; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_49_param; // @[Mux.scala:30:73] assign schedule_b_bits_param = _schedule_WIRE_48_bits_param; // @[Mux.scala:30:73] wire [12:0] _schedule_WIRE_49_tag; // @[Mux.scala:30:73] assign schedule_b_bits_tag = _schedule_WIRE_48_bits_tag; // @[Mux.scala:30:73] wire [9:0] _schedule_WIRE_49_set; // @[Mux.scala:30:73] assign schedule_b_bits_set = _schedule_WIRE_48_bits_set; // @[Mux.scala:30:73] wire [1:0] _schedule_WIRE_49_clients; // @[Mux.scala:30:73] assign schedule_b_bits_clients = _schedule_WIRE_48_bits_clients; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_53; // @[Mux.scala:30:73] assign _schedule_WIRE_48_bits_param = _schedule_WIRE_49_param; // @[Mux.scala:30:73] wire [12:0] _schedule_WIRE_52; // @[Mux.scala:30:73] assign _schedule_WIRE_48_bits_tag = _schedule_WIRE_49_tag; // @[Mux.scala:30:73] wire [9:0] _schedule_WIRE_51; // @[Mux.scala:30:73] assign _schedule_WIRE_48_bits_set = _schedule_WIRE_49_set; // @[Mux.scala:30:73] wire [1:0] _schedule_WIRE_50; // @[Mux.scala:30:73] assign _schedule_WIRE_48_bits_clients = _schedule_WIRE_49_clients; // @[Mux.scala:30:73] wire [1:0] _schedule_T_475 = _schedule_T ? _mshrs_0_io_schedule_bits_b_bits_clients : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _schedule_T_476 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_b_bits_clients : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _schedule_T_477 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_b_bits_clients : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _schedule_T_478 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_b_bits_clients : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _schedule_T_479 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_b_bits_clients : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _schedule_T_480 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_b_bits_clients : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _schedule_T_481 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_b_bits_clients : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _schedule_T_482 = _schedule_T_475 | _schedule_T_476; // @[Mux.scala:30:73] wire [1:0] _schedule_T_483 = _schedule_T_482 | _schedule_T_477; // @[Mux.scala:30:73] wire [1:0] _schedule_T_484 = _schedule_T_483 | _schedule_T_478; // @[Mux.scala:30:73] wire [1:0] _schedule_T_485 = _schedule_T_484 | _schedule_T_479; // @[Mux.scala:30:73] wire [1:0] _schedule_T_486 = _schedule_T_485 | _schedule_T_480; // @[Mux.scala:30:73] wire [1:0] _schedule_T_487 = _schedule_T_486 | _schedule_T_481; // @[Mux.scala:30:73] assign _schedule_WIRE_50 = _schedule_T_487; // @[Mux.scala:30:73] assign _schedule_WIRE_49_clients = _schedule_WIRE_50; // @[Mux.scala:30:73] wire [9:0] _schedule_T_488 = _schedule_T ? _mshrs_0_io_schedule_bits_b_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_489 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_b_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_490 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_b_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_491 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_b_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_492 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_b_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_493 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_b_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_494 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_b_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_495 = _schedule_T_488 | _schedule_T_489; // @[Mux.scala:30:73] wire [9:0] _schedule_T_496 = _schedule_T_495 | _schedule_T_490; // @[Mux.scala:30:73] wire [9:0] _schedule_T_497 = _schedule_T_496 | _schedule_T_491; // @[Mux.scala:30:73] wire [9:0] _schedule_T_498 = _schedule_T_497 | _schedule_T_492; // @[Mux.scala:30:73] wire [9:0] _schedule_T_499 = _schedule_T_498 | _schedule_T_493; // @[Mux.scala:30:73] wire [9:0] _schedule_T_500 = _schedule_T_499 | _schedule_T_494; // @[Mux.scala:30:73] assign _schedule_WIRE_51 = _schedule_T_500; // @[Mux.scala:30:73] assign _schedule_WIRE_49_set = _schedule_WIRE_51; // @[Mux.scala:30:73] wire [12:0] _schedule_T_501 = _schedule_T ? _mshrs_0_io_schedule_bits_b_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_502 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_b_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_503 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_b_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_504 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_b_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_505 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_b_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_506 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_b_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_507 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_b_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_508 = _schedule_T_501 | _schedule_T_502; // @[Mux.scala:30:73] wire [12:0] _schedule_T_509 = _schedule_T_508 | _schedule_T_503; // @[Mux.scala:30:73] wire [12:0] _schedule_T_510 = _schedule_T_509 | _schedule_T_504; // @[Mux.scala:30:73] wire [12:0] _schedule_T_511 = _schedule_T_510 | _schedule_T_505; // @[Mux.scala:30:73] wire [12:0] _schedule_T_512 = _schedule_T_511 | _schedule_T_506; // @[Mux.scala:30:73] wire [12:0] _schedule_T_513 = _schedule_T_512 | _schedule_T_507; // @[Mux.scala:30:73] assign _schedule_WIRE_52 = _schedule_T_513; // @[Mux.scala:30:73] assign _schedule_WIRE_49_tag = _schedule_WIRE_52; // @[Mux.scala:30:73] wire [2:0] _schedule_T_514 = _schedule_T ? _mshrs_0_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_515 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_516 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_517 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_518 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_519 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_520 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_521 = _schedule_T_514 | _schedule_T_515; // @[Mux.scala:30:73] wire [2:0] _schedule_T_522 = _schedule_T_521 | _schedule_T_516; // @[Mux.scala:30:73] wire [2:0] _schedule_T_523 = _schedule_T_522 | _schedule_T_517; // @[Mux.scala:30:73] wire [2:0] _schedule_T_524 = _schedule_T_523 | _schedule_T_518; // @[Mux.scala:30:73] wire [2:0] _schedule_T_525 = _schedule_T_524 | _schedule_T_519; // @[Mux.scala:30:73] wire [2:0] _schedule_T_526 = _schedule_T_525 | _schedule_T_520; // @[Mux.scala:30:73] assign _schedule_WIRE_53 = _schedule_T_526; // @[Mux.scala:30:73] assign _schedule_WIRE_49_param = _schedule_WIRE_53; // @[Mux.scala:30:73] wire _schedule_T_527 = _schedule_T & _mshrs_0_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_528 = _schedule_T_1 & _mshrs_1_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_529 = _schedule_T_2 & _mshrs_2_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_530 = _schedule_T_3 & _mshrs_3_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_531 = _schedule_T_4 & _mshrs_4_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_532 = _schedule_T_5 & _mshrs_5_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_533 = _schedule_T_6 & _mshrs_6_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_534 = _schedule_T_527 | _schedule_T_528; // @[Mux.scala:30:73] wire _schedule_T_535 = _schedule_T_534 | _schedule_T_529; // @[Mux.scala:30:73] wire _schedule_T_536 = _schedule_T_535 | _schedule_T_530; // @[Mux.scala:30:73] wire _schedule_T_537 = _schedule_T_536 | _schedule_T_531; // @[Mux.scala:30:73] wire _schedule_T_538 = _schedule_T_537 | _schedule_T_532; // @[Mux.scala:30:73] wire _schedule_T_539 = _schedule_T_538 | _schedule_T_533; // @[Mux.scala:30:73] assign _schedule_WIRE_54 = _schedule_T_539; // @[Mux.scala:30:73] assign _schedule_WIRE_48_valid = _schedule_WIRE_54; // @[Mux.scala:30:73] wire _schedule_WIRE_62; // @[Mux.scala:30:73] assign schedule_a_valid = _schedule_WIRE_55_valid; // @[Mux.scala:30:73] wire [12:0] _schedule_WIRE_56_tag; // @[Mux.scala:30:73] assign schedule_a_bits_tag = _schedule_WIRE_55_bits_tag; // @[Mux.scala:30:73] wire [9:0] _schedule_WIRE_56_set; // @[Mux.scala:30:73] assign schedule_a_bits_set = _schedule_WIRE_55_bits_set; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_56_param; // @[Mux.scala:30:73] assign schedule_a_bits_param = _schedule_WIRE_55_bits_param; // @[Mux.scala:30:73] wire _schedule_WIRE_56_block; // @[Mux.scala:30:73] assign schedule_a_bits_block = _schedule_WIRE_55_bits_block; // @[Mux.scala:30:73] wire [12:0] _schedule_WIRE_61; // @[Mux.scala:30:73] assign _schedule_WIRE_55_bits_tag = _schedule_WIRE_56_tag; // @[Mux.scala:30:73] wire [9:0] _schedule_WIRE_60; // @[Mux.scala:30:73] assign _schedule_WIRE_55_bits_set = _schedule_WIRE_56_set; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_59; // @[Mux.scala:30:73] assign _schedule_WIRE_55_bits_param = _schedule_WIRE_56_param; // @[Mux.scala:30:73] wire _schedule_WIRE_57; // @[Mux.scala:30:73] assign _schedule_WIRE_55_bits_block = _schedule_WIRE_56_block; // @[Mux.scala:30:73] wire _schedule_T_540 = _schedule_T & _mshrs_0_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36] wire _schedule_T_541 = _schedule_T_1 & _mshrs_1_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36] wire _schedule_T_542 = _schedule_T_2 & _mshrs_2_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36] wire _schedule_T_543 = _schedule_T_3 & _mshrs_3_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36] wire _schedule_T_544 = _schedule_T_4 & _mshrs_4_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36] wire _schedule_T_545 = _schedule_T_5 & _mshrs_5_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36] wire _schedule_T_546 = _schedule_T_6 & _mshrs_6_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36] wire _schedule_T_547 = _schedule_T_540 | _schedule_T_541; // @[Mux.scala:30:73] wire _schedule_T_548 = _schedule_T_547 | _schedule_T_542; // @[Mux.scala:30:73] wire _schedule_T_549 = _schedule_T_548 | _schedule_T_543; // @[Mux.scala:30:73] wire _schedule_T_550 = _schedule_T_549 | _schedule_T_544; // @[Mux.scala:30:73] wire _schedule_T_551 = _schedule_T_550 | _schedule_T_545; // @[Mux.scala:30:73] wire _schedule_T_552 = _schedule_T_551 | _schedule_T_546; // @[Mux.scala:30:73] assign _schedule_WIRE_57 = _schedule_T_552; // @[Mux.scala:30:73] assign _schedule_WIRE_56_block = _schedule_WIRE_57; // @[Mux.scala:30:73] wire [2:0] _schedule_T_566 = _schedule_T ? _mshrs_0_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_567 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_568 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_569 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_570 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_571 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_572 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_573 = _schedule_T_566 | _schedule_T_567; // @[Mux.scala:30:73] wire [2:0] _schedule_T_574 = _schedule_T_573 | _schedule_T_568; // @[Mux.scala:30:73] wire [2:0] _schedule_T_575 = _schedule_T_574 | _schedule_T_569; // @[Mux.scala:30:73] wire [2:0] _schedule_T_576 = _schedule_T_575 | _schedule_T_570; // @[Mux.scala:30:73] wire [2:0] _schedule_T_577 = _schedule_T_576 | _schedule_T_571; // @[Mux.scala:30:73] wire [2:0] _schedule_T_578 = _schedule_T_577 | _schedule_T_572; // @[Mux.scala:30:73] assign _schedule_WIRE_59 = _schedule_T_578; // @[Mux.scala:30:73] assign _schedule_WIRE_56_param = _schedule_WIRE_59; // @[Mux.scala:30:73] wire [9:0] _schedule_T_579 = _schedule_T ? _mshrs_0_io_schedule_bits_a_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_580 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_a_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_581 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_a_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_582 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_a_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_583 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_a_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_584 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_a_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_585 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_a_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_586 = _schedule_T_579 | _schedule_T_580; // @[Mux.scala:30:73] wire [9:0] _schedule_T_587 = _schedule_T_586 | _schedule_T_581; // @[Mux.scala:30:73] wire [9:0] _schedule_T_588 = _schedule_T_587 | _schedule_T_582; // @[Mux.scala:30:73] wire [9:0] _schedule_T_589 = _schedule_T_588 | _schedule_T_583; // @[Mux.scala:30:73] wire [9:0] _schedule_T_590 = _schedule_T_589 | _schedule_T_584; // @[Mux.scala:30:73] wire [9:0] _schedule_T_591 = _schedule_T_590 | _schedule_T_585; // @[Mux.scala:30:73] assign _schedule_WIRE_60 = _schedule_T_591; // @[Mux.scala:30:73] assign _schedule_WIRE_56_set = _schedule_WIRE_60; // @[Mux.scala:30:73] wire [12:0] _schedule_T_592 = _schedule_T ? _mshrs_0_io_schedule_bits_a_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_593 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_a_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_594 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_a_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_595 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_a_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_596 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_a_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_597 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_a_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_598 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_a_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_599 = _schedule_T_592 | _schedule_T_593; // @[Mux.scala:30:73] wire [12:0] _schedule_T_600 = _schedule_T_599 | _schedule_T_594; // @[Mux.scala:30:73] wire [12:0] _schedule_T_601 = _schedule_T_600 | _schedule_T_595; // @[Mux.scala:30:73] wire [12:0] _schedule_T_602 = _schedule_T_601 | _schedule_T_596; // @[Mux.scala:30:73] wire [12:0] _schedule_T_603 = _schedule_T_602 | _schedule_T_597; // @[Mux.scala:30:73] wire [12:0] _schedule_T_604 = _schedule_T_603 | _schedule_T_598; // @[Mux.scala:30:73] assign _schedule_WIRE_61 = _schedule_T_604; // @[Mux.scala:30:73] assign _schedule_WIRE_56_tag = _schedule_WIRE_61; // @[Mux.scala:30:73] wire _schedule_T_605 = _schedule_T & _mshrs_0_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_606 = _schedule_T_1 & _mshrs_1_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_607 = _schedule_T_2 & _mshrs_2_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_608 = _schedule_T_3 & _mshrs_3_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_609 = _schedule_T_4 & _mshrs_4_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_610 = _schedule_T_5 & _mshrs_5_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_611 = _schedule_T_6 & _mshrs_6_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_612 = _schedule_T_605 | _schedule_T_606; // @[Mux.scala:30:73] wire _schedule_T_613 = _schedule_T_612 | _schedule_T_607; // @[Mux.scala:30:73] wire _schedule_T_614 = _schedule_T_613 | _schedule_T_608; // @[Mux.scala:30:73] wire _schedule_T_615 = _schedule_T_614 | _schedule_T_609; // @[Mux.scala:30:73] wire _schedule_T_616 = _schedule_T_615 | _schedule_T_610; // @[Mux.scala:30:73] wire _schedule_T_617 = _schedule_T_616 | _schedule_T_611; // @[Mux.scala:30:73] assign _schedule_WIRE_62 = _schedule_T_617; // @[Mux.scala:30:73] assign _schedule_WIRE_55_valid = _schedule_WIRE_62; // @[Mux.scala:30:73] wire [12:0] _scheduleTag_T_7 = _scheduleTag_T ? _mshrs_0_io_status_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _scheduleTag_T_8 = _scheduleTag_T_1 ? _mshrs_1_io_status_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _scheduleTag_T_9 = _scheduleTag_T_2 ? _mshrs_2_io_status_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _scheduleTag_T_10 = _scheduleTag_T_3 ? _mshrs_3_io_status_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _scheduleTag_T_11 = _scheduleTag_T_4 ? _mshrs_4_io_status_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _scheduleTag_T_12 = _scheduleTag_T_5 ? _mshrs_5_io_status_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _scheduleTag_T_13 = _scheduleTag_T_6 ? _mshrs_6_io_status_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _scheduleTag_T_14 = _scheduleTag_T_7 | _scheduleTag_T_8; // @[Mux.scala:30:73] wire [12:0] _scheduleTag_T_15 = _scheduleTag_T_14 | _scheduleTag_T_9; // @[Mux.scala:30:73] wire [12:0] _scheduleTag_T_16 = _scheduleTag_T_15 | _scheduleTag_T_10; // @[Mux.scala:30:73] wire [12:0] _scheduleTag_T_17 = _scheduleTag_T_16 | _scheduleTag_T_11; // @[Mux.scala:30:73] wire [12:0] _scheduleTag_T_18 = _scheduleTag_T_17 | _scheduleTag_T_12; // @[Mux.scala:30:73] wire [12:0] _scheduleTag_T_19 = _scheduleTag_T_18 | _scheduleTag_T_13; // @[Mux.scala:30:73] wire [12:0] scheduleTag = _scheduleTag_T_19; // @[Mux.scala:30:73] wire [9:0] _scheduleSet_T_7 = _scheduleSet_T ? _mshrs_0_io_status_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _scheduleSet_T_8 = _scheduleSet_T_1 ? _mshrs_1_io_status_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _scheduleSet_T_9 = _scheduleSet_T_2 ? _mshrs_2_io_status_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _scheduleSet_T_10 = _scheduleSet_T_3 ? _mshrs_3_io_status_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _scheduleSet_T_11 = _scheduleSet_T_4 ? _mshrs_4_io_status_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _scheduleSet_T_12 = _scheduleSet_T_5 ? _mshrs_5_io_status_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _scheduleSet_T_13 = _scheduleSet_T_6 ? _mshrs_6_io_status_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _scheduleSet_T_14 = _scheduleSet_T_7 | _scheduleSet_T_8; // @[Mux.scala:30:73] wire [9:0] _scheduleSet_T_15 = _scheduleSet_T_14 | _scheduleSet_T_9; // @[Mux.scala:30:73] wire [9:0] _scheduleSet_T_16 = _scheduleSet_T_15 | _scheduleSet_T_10; // @[Mux.scala:30:73] wire [9:0] _scheduleSet_T_17 = _scheduleSet_T_16 | _scheduleSet_T_11; // @[Mux.scala:30:73] wire [9:0] _scheduleSet_T_18 = _scheduleSet_T_17 | _scheduleSet_T_12; // @[Mux.scala:30:73] wire [9:0] _scheduleSet_T_19 = _scheduleSet_T_18 | _scheduleSet_T_13; // @[Mux.scala:30:73] wire [9:0] scheduleSet = _scheduleSet_T_19; // @[Mux.scala:30:73] wire [5:0] _robin_filter_T = mshr_selectOH[6:1]; // @[package.scala:262:48] wire [6:0] _robin_filter_T_1 = {mshr_selectOH[6], mshr_selectOH[5:0] | _robin_filter_T}; // @[Mux.scala:32:36] wire [4:0] _robin_filter_T_2 = _robin_filter_T_1[6:2]; // @[package.scala:262:{43,48}] wire [6:0] _robin_filter_T_3 = {_robin_filter_T_1[6:5], _robin_filter_T_1[4:0] | _robin_filter_T_2}; // @[package.scala:262:{43,48}] wire [2:0] _robin_filter_T_4 = _robin_filter_T_3[6:4]; // @[package.scala:262:{43,48}] wire [6:0] _robin_filter_T_5 = {_robin_filter_T_3[6:3], _robin_filter_T_3[2:0] | _robin_filter_T_4}; // @[package.scala:262:{43,48}] wire [6:0] _robin_filter_T_6 = _robin_filter_T_5; // @[package.scala:262:43, :263:17] wire [6:0] _robin_filter_T_7 = ~_robin_filter_T_6; // @[package.scala:263:17] wire _schedule_c_bits_source_T = schedule_c_bits_opcode[1]; // @[Mux.scala:30:73] assign _schedule_c_bits_source_T_1 = _schedule_c_bits_source_T ? mshr_select : 3'h0; // @[OneHot.scala:32:10] assign schedule_c_bits_source = _schedule_c_bits_source_T_1; // @[Mux.scala:30:73] assign _nestedwb_set_T = select_c ? _mshrs_6_io_status_bits_set : _mshrs_5_io_status_bits_set; // @[Scheduler.scala:71:46, :153:32, :155:24] assign nestedwb_set = _nestedwb_set_T; // @[Scheduler.scala:75:22, :155:24] assign _nestedwb_tag_T = select_c ? _mshrs_6_io_status_bits_tag : _mshrs_5_io_status_bits_tag; // @[Scheduler.scala:71:46, :153:32, :156:24] assign nestedwb_tag = _nestedwb_tag_T; // @[Scheduler.scala:75:22, :156:24] wire _GEN = select_bc & _mshrs_5_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :154:32, :157:37] wire _nestedwb_b_toN_T; // @[Scheduler.scala:157:37] assign _nestedwb_b_toN_T = _GEN; // @[Scheduler.scala:157:37] wire _nestedwb_b_toB_T; // @[Scheduler.scala:158:37] assign _nestedwb_b_toB_T = _GEN; // @[Scheduler.scala:157:37, :158:37] assign _nestedwb_b_clr_dirty_T = _GEN; // @[Scheduler.scala:157:37, :159:37] wire _nestedwb_b_toN_T_1 = _mshrs_5_io_schedule_bits_dir_bits_data_state == 2'h0; // @[Scheduler.scala:71:46, :157:123] assign _nestedwb_b_toN_T_2 = _nestedwb_b_toN_T & _nestedwb_b_toN_T_1; // @[Scheduler.scala:157:{37,75,123}] assign nestedwb_b_toN = _nestedwb_b_toN_T_2; // @[Scheduler.scala:75:22, :157:75] wire _nestedwb_b_toB_T_1 = _mshrs_5_io_schedule_bits_dir_bits_data_state == 2'h1; // @[Scheduler.scala:71:46, :158:123] assign _nestedwb_b_toB_T_2 = _nestedwb_b_toB_T & _nestedwb_b_toB_T_1; // @[Scheduler.scala:158:{37,75,123}] assign nestedwb_b_toB = _nestedwb_b_toB_T_2; // @[Scheduler.scala:75:22, :158:75] assign nestedwb_b_clr_dirty = _nestedwb_b_clr_dirty_T; // @[Scheduler.scala:75:22, :159:37] wire _nestedwb_c_set_dirty_T = select_c & _mshrs_6_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :153:32, :160:37] assign _nestedwb_c_set_dirty_T_1 = _nestedwb_c_set_dirty_T & _mshrs_6_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46, :160:{37,75}] assign nestedwb_c_set_dirty = _nestedwb_c_set_dirty_T_1; // @[Scheduler.scala:75:22, :160:75] wire _request_ready_T_2; // @[Scheduler.scala:261:40] wire _request_valid_T_2; // @[Scheduler.scala:164:39] wire _request_bits_T_1_prio_0; // @[Scheduler.scala:165:22] wire _view__WIRE_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_1_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_2_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_3_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_4_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_5_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_6_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95] wire _request_bits_T_1_prio_2; // @[Scheduler.scala:165:22] wire _request_bits_T_1_control; // @[Scheduler.scala:165:22] wire _view__WIRE_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_1_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_2_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_3_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_4_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_5_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_6_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _request_bits_T_1_opcode; // @[Scheduler.scala:165:22] wire _view__WIRE_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_1_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_2_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_3_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_4_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_5_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_6_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _request_bits_T_1_param; // @[Scheduler.scala:165:22] wire [2:0] _view__WIRE_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_1_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_2_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_3_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_4_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_5_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_6_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _request_bits_T_1_size; // @[Scheduler.scala:165:22] wire [2:0] _view__WIRE_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_1_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_2_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_3_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_4_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_5_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_6_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _request_bits_T_1_source; // @[Scheduler.scala:165:22] wire [2:0] _view__WIRE_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_1_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_2_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_3_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_4_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_5_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_6_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95] wire [12:0] _request_bits_T_1_tag; // @[Scheduler.scala:165:22] wire [5:0] _view__WIRE_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_1_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_2_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_3_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_4_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_5_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_6_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _request_bits_T_1_offset; // @[Scheduler.scala:165:22] wire [12:0] _view__WIRE_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95] wire [12:0] _view__WIRE_1_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95] wire [12:0] _view__WIRE_2_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95] wire [12:0] _view__WIRE_3_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95] wire [12:0] _view__WIRE_4_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95] wire [12:0] _view__WIRE_5_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95] wire [12:0] _view__WIRE_6_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _request_bits_T_1_put; // @[Scheduler.scala:165:22] wire [5:0] _view__WIRE_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_1_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_2_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_3_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_4_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_5_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_6_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95] wire [9:0] _request_bits_T_1_set; // @[Scheduler.scala:165:22] wire [5:0] _view__WIRE_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_1_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_2_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_3_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_4_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_5_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_6_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95] wire [9:0] request_bits_set; // @[Scheduler.scala:163:21] wire request_ready; // @[Scheduler.scala:163:21] wire request_valid; // @[Scheduler.scala:163:21] wire _request_valid_T = _sinkA_io_req_valid | _sinkX_io_req_valid; // @[Scheduler.scala:54:21, :58:21, :164:62] wire _request_valid_T_1 = _request_valid_T | _sinkC_io_req_valid; // @[Scheduler.scala:55:21, :164:{62,84}] assign _request_valid_T_2 = _directory_io_ready & _request_valid_T_1; // @[Scheduler.scala:68:25, :164:{39,84}] assign request_valid = _request_valid_T_2; // @[Scheduler.scala:163:21, :164:39] wire [2:0] _request_bits_T_opcode = _sinkX_io_req_valid ? 3'h0 : _sinkA_io_req_bits_opcode; // @[Scheduler.scala:54:21, :58:21, :166:22] wire [2:0] _request_bits_T_param = _sinkX_io_req_valid ? 3'h0 : _sinkA_io_req_bits_param; // @[Scheduler.scala:54:21, :58:21, :166:22] wire [2:0] _request_bits_T_size = _sinkX_io_req_valid ? 3'h6 : _sinkA_io_req_bits_size; // @[Scheduler.scala:54:21, :58:21, :166:22] wire [5:0] _request_bits_T_source = _sinkX_io_req_valid ? 6'h0 : _sinkA_io_req_bits_source; // @[Scheduler.scala:54:21, :58:21, :166:22] wire [12:0] _request_bits_T_tag = _sinkX_io_req_valid ? _sinkX_io_req_bits_tag : _sinkA_io_req_bits_tag; // @[Scheduler.scala:54:21, :58:21, :166:22] wire [5:0] _request_bits_T_offset = _sinkX_io_req_valid ? 6'h0 : _sinkA_io_req_bits_offset; // @[Scheduler.scala:54:21, :58:21, :166:22] wire [5:0] _request_bits_T_put = _sinkX_io_req_valid ? 6'h0 : _sinkA_io_req_bits_put; // @[Scheduler.scala:54:21, :58:21, :166:22] wire [9:0] _request_bits_T_set = _sinkX_io_req_valid ? _sinkX_io_req_bits_set : _sinkA_io_req_bits_set; // @[Scheduler.scala:54:21, :58:21, :166:22] wire _request_bits_T_control; // @[Scheduler.scala:166:22] assign _request_bits_T_1_control = ~_sinkC_io_req_valid & _request_bits_T_control; // @[Scheduler.scala:55:21, :165:22, :166:22] assign _request_bits_T_1_opcode = _sinkC_io_req_valid ? _sinkC_io_req_bits_opcode : _request_bits_T_opcode; // @[Scheduler.scala:55:21, :165:22, :166:22] assign _request_bits_T_1_param = _sinkC_io_req_valid ? _sinkC_io_req_bits_param : _request_bits_T_param; // @[Scheduler.scala:55:21, :165:22, :166:22] assign _request_bits_T_1_size = _sinkC_io_req_valid ? _sinkC_io_req_bits_size : _request_bits_T_size; // @[Scheduler.scala:55:21, :165:22, :166:22] assign _request_bits_T_1_source = _sinkC_io_req_valid ? _sinkC_io_req_bits_source : _request_bits_T_source; // @[Scheduler.scala:55:21, :165:22, :166:22] assign _request_bits_T_1_tag = _sinkC_io_req_valid ? _sinkC_io_req_bits_tag : _request_bits_T_tag; // @[Scheduler.scala:55:21, :165:22, :166:22] assign _request_bits_T_1_offset = _sinkC_io_req_valid ? _sinkC_io_req_bits_offset : _request_bits_T_offset; // @[Scheduler.scala:55:21, :165:22, :166:22] assign _request_bits_T_1_put = _sinkC_io_req_valid ? _sinkC_io_req_bits_put : _request_bits_T_put; // @[Scheduler.scala:55:21, :165:22, :166:22] assign _request_bits_T_1_set = _sinkC_io_req_valid ? _sinkC_io_req_bits_set : _request_bits_T_set; // @[Scheduler.scala:55:21, :165:22, :166:22] assign _request_bits_T_1_prio_0 = ~_sinkC_io_req_valid; // @[Scheduler.scala:55:21, :165:22] assign request_bits_prio_0 = _request_bits_T_1_prio_0; // @[Scheduler.scala:163:21, :165:22] assign request_bits_prio_2 = _request_bits_T_1_prio_2; // @[Scheduler.scala:163:21, :165:22] assign request_bits_control = _request_bits_T_1_control; // @[Scheduler.scala:163:21, :165:22] assign request_bits_opcode = _request_bits_T_1_opcode; // @[Scheduler.scala:163:21, :165:22] assign request_bits_param = _request_bits_T_1_param; // @[Scheduler.scala:163:21, :165:22] assign request_bits_size = _request_bits_T_1_size; // @[Scheduler.scala:163:21, :165:22] assign request_bits_source = _request_bits_T_1_source; // @[Scheduler.scala:163:21, :165:22] assign request_bits_tag = _request_bits_T_1_tag; // @[Scheduler.scala:163:21, :165:22] assign request_bits_offset = _request_bits_T_1_offset; // @[Scheduler.scala:163:21, :165:22] assign request_bits_put = _request_bits_T_1_put; // @[Scheduler.scala:163:21, :165:22] assign request_bits_set = _request_bits_T_1_set; // @[Scheduler.scala:163:21, :165:22] wire _GEN_0 = _directory_io_ready & request_ready; // @[Scheduler.scala:68:25, :163:21, :167:44] wire _sinkC_io_req_ready_T; // @[Scheduler.scala:167:44] assign _sinkC_io_req_ready_T = _GEN_0; // @[Scheduler.scala:167:44] wire _sinkX_io_req_ready_T; // @[Scheduler.scala:168:44] assign _sinkX_io_req_ready_T = _GEN_0; // @[Scheduler.scala:167:44, :168:44] wire _sinkA_io_req_ready_T; // @[Scheduler.scala:169:44] assign _sinkA_io_req_ready_T = _GEN_0; // @[Scheduler.scala:167:44, :169:44] wire _sinkX_io_req_ready_T_1 = ~_sinkC_io_req_valid; // @[Scheduler.scala:55:21, :165:22, :168:64] wire _sinkX_io_req_ready_T_2 = _sinkX_io_req_ready_T & _sinkX_io_req_ready_T_1; // @[Scheduler.scala:168:{44,61,64}] wire _sinkA_io_req_ready_T_1 = ~_sinkC_io_req_valid; // @[Scheduler.scala:55:21, :165:22, :169:64] wire _sinkA_io_req_ready_T_2 = _sinkA_io_req_ready_T & _sinkA_io_req_ready_T_1; // @[Scheduler.scala:169:{44,61,64}] wire _sinkA_io_req_ready_T_3 = ~_sinkX_io_req_valid; // @[Scheduler.scala:58:21, :169:87] wire _sinkA_io_req_ready_T_4 = _sinkA_io_req_ready_T_2 & _sinkA_io_req_ready_T_3; // @[Scheduler.scala:169:{61,84,87}] wire _setMatches_T = _mshrs_0_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83] wire _setMatches_T_1 = _mshrs_0_io_status_valid & _setMatches_T; // @[Scheduler.scala:71:46, :172:{59,83}] wire _setMatches_T_2 = _mshrs_1_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83] wire _setMatches_T_3 = _mshrs_1_io_status_valid & _setMatches_T_2; // @[Scheduler.scala:71:46, :172:{59,83}] wire _setMatches_T_4 = _mshrs_2_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83] wire _setMatches_T_5 = _mshrs_2_io_status_valid & _setMatches_T_4; // @[Scheduler.scala:71:46, :172:{59,83}] wire _setMatches_T_6 = _mshrs_3_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83] wire _setMatches_T_7 = _mshrs_3_io_status_valid & _setMatches_T_6; // @[Scheduler.scala:71:46, :172:{59,83}] wire _setMatches_T_8 = _mshrs_4_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83] wire _setMatches_T_9 = _mshrs_4_io_status_valid & _setMatches_T_8; // @[Scheduler.scala:71:46, :172:{59,83}] wire _setMatches_T_10 = _mshrs_5_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83] wire _setMatches_T_11 = _mshrs_5_io_status_valid & _setMatches_T_10; // @[Scheduler.scala:71:46, :172:{59,83}] wire _setMatches_T_12 = _mshrs_6_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83] wire _setMatches_T_13 = _mshrs_6_io_status_valid & _setMatches_T_12; // @[Scheduler.scala:71:46, :172:{59,83}] wire [1:0] setMatches_lo_hi = {_setMatches_T_5, _setMatches_T_3}; // @[Scheduler.scala:172:{23,59}] wire [2:0] setMatches_lo = {setMatches_lo_hi, _setMatches_T_1}; // @[Scheduler.scala:172:{23,59}] wire [1:0] setMatches_hi_lo = {_setMatches_T_9, _setMatches_T_7}; // @[Scheduler.scala:172:{23,59}] wire [1:0] setMatches_hi_hi = {_setMatches_T_13, _setMatches_T_11}; // @[Scheduler.scala:172:{23,59}] wire [3:0] setMatches_hi = {setMatches_hi_hi, setMatches_hi_lo}; // @[Scheduler.scala:172:23] wire [6:0] setMatches = {setMatches_hi, setMatches_lo}; // @[Scheduler.scala:172:23] wire _alloc_T = |setMatches; // @[Scheduler.scala:172:23, :173:27] wire alloc = ~_alloc_T; // @[Scheduler.scala:173:{15,27}] wire _blockB_T = setMatches[0]; // @[Mux.scala:32:36] wire _blockC_T = setMatches[0]; // @[Mux.scala:32:36] wire _nestB_T = setMatches[0]; // @[Mux.scala:32:36] wire _nestC_T = setMatches[0]; // @[Mux.scala:32:36] wire _blockB_T_1 = setMatches[1]; // @[Mux.scala:32:36] wire _blockC_T_1 = setMatches[1]; // @[Mux.scala:32:36] wire _nestB_T_1 = setMatches[1]; // @[Mux.scala:32:36] wire _nestC_T_1 = setMatches[1]; // @[Mux.scala:32:36] wire _blockB_T_2 = setMatches[2]; // @[Mux.scala:32:36] wire _blockC_T_2 = setMatches[2]; // @[Mux.scala:32:36] wire _nestB_T_2 = setMatches[2]; // @[Mux.scala:32:36] wire _nestC_T_2 = setMatches[2]; // @[Mux.scala:32:36] wire _blockB_T_3 = setMatches[3]; // @[Mux.scala:32:36] wire _blockC_T_3 = setMatches[3]; // @[Mux.scala:32:36] wire _nestB_T_3 = setMatches[3]; // @[Mux.scala:32:36] wire _nestC_T_3 = setMatches[3]; // @[Mux.scala:32:36] wire _blockB_T_4 = setMatches[4]; // @[Mux.scala:32:36] wire _blockC_T_4 = setMatches[4]; // @[Mux.scala:32:36] wire _nestB_T_4 = setMatches[4]; // @[Mux.scala:32:36] wire _nestC_T_4 = setMatches[4]; // @[Mux.scala:32:36] wire _blockB_T_5 = setMatches[5]; // @[Mux.scala:32:36] wire _blockC_T_5 = setMatches[5]; // @[Mux.scala:32:36] wire _nestB_T_5 = setMatches[5]; // @[Mux.scala:32:36] wire _nestC_T_5 = setMatches[5]; // @[Mux.scala:32:36] wire _blockB_T_6 = setMatches[6]; // @[Mux.scala:32:36] wire _blockC_T_6 = setMatches[6]; // @[Mux.scala:32:36] wire _nestB_T_6 = setMatches[6]; // @[Mux.scala:32:36] wire _nestC_T_6 = setMatches[6]; // @[Mux.scala:32:36] wire _blockB_T_7 = _blockB_T & _mshrs_0_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36] wire _blockB_T_8 = _blockB_T_1 & _mshrs_1_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36] wire _blockB_T_9 = _blockB_T_2 & _mshrs_2_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36] wire _blockB_T_10 = _blockB_T_3 & _mshrs_3_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36] wire _blockB_T_11 = _blockB_T_4 & _mshrs_4_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36] wire _blockB_T_12 = _blockB_T_5 & _mshrs_5_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36] wire _blockB_T_13 = _blockB_T_6 & _mshrs_6_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36] wire _blockB_T_14 = _blockB_T_7 | _blockB_T_8; // @[Mux.scala:30:73] wire _blockB_T_15 = _blockB_T_14 | _blockB_T_9; // @[Mux.scala:30:73] wire _blockB_T_16 = _blockB_T_15 | _blockB_T_10; // @[Mux.scala:30:73] wire _blockB_T_17 = _blockB_T_16 | _blockB_T_11; // @[Mux.scala:30:73] wire _blockB_T_18 = _blockB_T_17 | _blockB_T_12; // @[Mux.scala:30:73] wire _blockB_T_19 = _blockB_T_18 | _blockB_T_13; // @[Mux.scala:30:73] wire _blockB_WIRE = _blockB_T_19; // @[Mux.scala:30:73] wire _blockC_T_7 = _blockC_T & _mshrs_0_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36] wire _blockC_T_8 = _blockC_T_1 & _mshrs_1_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36] wire _blockC_T_9 = _blockC_T_2 & _mshrs_2_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36] wire _blockC_T_10 = _blockC_T_3 & _mshrs_3_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36] wire _blockC_T_11 = _blockC_T_4 & _mshrs_4_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36] wire _blockC_T_12 = _blockC_T_5 & _mshrs_5_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36] wire _blockC_T_13 = _blockC_T_6 & _mshrs_6_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36] wire _blockC_T_14 = _blockC_T_7 | _blockC_T_8; // @[Mux.scala:30:73] wire _blockC_T_15 = _blockC_T_14 | _blockC_T_9; // @[Mux.scala:30:73] wire _blockC_T_16 = _blockC_T_15 | _blockC_T_10; // @[Mux.scala:30:73] wire _blockC_T_17 = _blockC_T_16 | _blockC_T_11; // @[Mux.scala:30:73] wire _blockC_T_18 = _blockC_T_17 | _blockC_T_12; // @[Mux.scala:30:73] wire _blockC_T_19 = _blockC_T_18 | _blockC_T_13; // @[Mux.scala:30:73] wire _blockC_WIRE = _blockC_T_19; // @[Mux.scala:30:73] wire blockC = _blockC_WIRE & request_bits_prio_2; // @[Mux.scala:30:73] wire _nestB_T_7 = _nestB_T & _mshrs_0_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36] wire _nestB_T_8 = _nestB_T_1 & _mshrs_1_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36] wire _nestB_T_9 = _nestB_T_2 & _mshrs_2_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36] wire _nestB_T_10 = _nestB_T_3 & _mshrs_3_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36] wire _nestB_T_11 = _nestB_T_4 & _mshrs_4_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36] wire _nestB_T_12 = _nestB_T_5 & _mshrs_5_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36] wire _nestB_T_13 = _nestB_T_6 & _mshrs_6_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36] wire _nestB_T_14 = _nestB_T_7 | _nestB_T_8; // @[Mux.scala:30:73] wire _nestB_T_15 = _nestB_T_14 | _nestB_T_9; // @[Mux.scala:30:73] wire _nestB_T_16 = _nestB_T_15 | _nestB_T_10; // @[Mux.scala:30:73] wire _nestB_T_17 = _nestB_T_16 | _nestB_T_11; // @[Mux.scala:30:73] wire _nestB_T_18 = _nestB_T_17 | _nestB_T_12; // @[Mux.scala:30:73] wire _nestB_T_19 = _nestB_T_18 | _nestB_T_13; // @[Mux.scala:30:73] wire _nestB_WIRE = _nestB_T_19; // @[Mux.scala:30:73] wire _nestC_T_7 = _nestC_T & _mshrs_0_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36] wire _nestC_T_8 = _nestC_T_1 & _mshrs_1_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36] wire _nestC_T_9 = _nestC_T_2 & _mshrs_2_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36] wire _nestC_T_10 = _nestC_T_3 & _mshrs_3_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36] wire _nestC_T_11 = _nestC_T_4 & _mshrs_4_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36] wire _nestC_T_12 = _nestC_T_5 & _mshrs_5_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36] wire _nestC_T_13 = _nestC_T_6 & _mshrs_6_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36] wire _nestC_T_14 = _nestC_T_7 | _nestC_T_8; // @[Mux.scala:30:73] wire _nestC_T_15 = _nestC_T_14 | _nestC_T_9; // @[Mux.scala:30:73] wire _nestC_T_16 = _nestC_T_15 | _nestC_T_10; // @[Mux.scala:30:73] wire _nestC_T_17 = _nestC_T_16 | _nestC_T_11; // @[Mux.scala:30:73] wire _nestC_T_18 = _nestC_T_17 | _nestC_T_12; // @[Mux.scala:30:73] wire _nestC_T_19 = _nestC_T_18 | _nestC_T_13; // @[Mux.scala:30:73] wire _nestC_WIRE = _nestC_T_19; // @[Mux.scala:30:73] wire nestC = _nestC_WIRE & request_bits_prio_2; // @[Mux.scala:30:73] wire _prioFilter_T = ~request_bits_prio_0; // @[Scheduler.scala:163:21, :182:46] wire [1:0] prioFilter_hi = {request_bits_prio_2, _prioFilter_T}; // @[Scheduler.scala:163:21, :182:{23,46}] wire [6:0] prioFilter = {prioFilter_hi, 5'h1F}; // @[Scheduler.scala:182:23] wire [6:0] lowerMatches = setMatches & prioFilter; // @[Scheduler.scala:172:23, :182:23, :183:33] wire _queue_T = |lowerMatches; // @[Scheduler.scala:183:33, :185:28] wire _queue_T_2 = _queue_T; // @[Scheduler.scala:185:{28,32}] wire _queue_T_3 = ~nestC; // @[Scheduler.scala:180:70, :185:45] wire _queue_T_4 = _queue_T_2 & _queue_T_3; // @[Scheduler.scala:185:{32,42,45}] wire _queue_T_6 = _queue_T_4; // @[Scheduler.scala:185:{42,52}] wire _queue_T_7 = ~blockC; // @[Scheduler.scala:176:70, :185:66] wire queue = _queue_T_6 & _queue_T_7; // @[Scheduler.scala:185:{52,63,66}] wire _T_7 = request_valid & queue; // @[Scheduler.scala:163:21, :185:63, :195:31] wire _bypass_T; // @[Scheduler.scala:213:30] assign _bypass_T = _T_7; // @[Scheduler.scala:195:31, :213:30] wire _bypass_T_1; // @[Scheduler.scala:231:32] assign _bypass_T_1 = _T_7; // @[Scheduler.scala:195:31, :231:32] wire _bypass_T_2; // @[Scheduler.scala:231:32] assign _bypass_T_2 = _T_7; // @[Scheduler.scala:195:31, :231:32] wire _bypass_T_3; // @[Scheduler.scala:231:32] assign _bypass_T_3 = _T_7; // @[Scheduler.scala:195:31, :231:32] wire _bypass_T_4; // @[Scheduler.scala:231:32] assign _bypass_T_4 = _T_7; // @[Scheduler.scala:195:31, :231:32] wire _bypass_T_5; // @[Scheduler.scala:231:32] assign _bypass_T_5 = _T_7; // @[Scheduler.scala:195:31, :231:32] wire _bypass_T_6; // @[Scheduler.scala:231:32] assign _bypass_T_6 = _T_7; // @[Scheduler.scala:195:31, :231:32] wire _bypass_T_7; // @[Scheduler.scala:231:32] assign _bypass_T_7 = _T_7; // @[Scheduler.scala:195:31, :231:32] wire _requests_io_push_valid_T; // @[Scheduler.scala:270:43] assign _requests_io_push_valid_T = _T_7; // @[Scheduler.scala:195:31, :270:43] wire _lowerMatches1_T = lowerMatches[6]; // @[Scheduler.scala:183:33, :200:21] wire _lowerMatches1_T_2 = lowerMatches[5]; // @[Scheduler.scala:183:33, :201:21] wire [6:0] _lowerMatches1_T_4 = _lowerMatches1_T_2 ? 7'h20 : lowerMatches; // @[Scheduler.scala:183:33, :201:{8,21}] wire [6:0] lowerMatches1 = _lowerMatches1_T ? 7'h40 : _lowerMatches1_T_4; // @[Scheduler.scala:200:{8,21}, :201:8] wire [6:0] _requests_io_push_bits_index_T = lowerMatches1; // @[Scheduler.scala:200:8, :274:30] wire [13:0] _GEN_1 = {2{mshr_selectOH}}; // @[Scheduler.scala:121:70, :206:30] wire [13:0] selected_requests_hi; // @[Scheduler.scala:206:30] assign selected_requests_hi = _GEN_1; // @[Scheduler.scala:206:30] wire [13:0] pop_index_hi; // @[Scheduler.scala:241:31] assign pop_index_hi = _GEN_1; // @[Scheduler.scala:206:30, :241:31] wire [20:0] _selected_requests_T = {selected_requests_hi, mshr_selectOH}; // @[Scheduler.scala:121:70, :206:30] wire [20:0] selected_requests = _selected_requests_T & _requests_io_valid; // @[Scheduler.scala:70:24, :206:{30,76}] wire [6:0] _a_pop_T = selected_requests[6:0]; // @[Scheduler.scala:206:76, :207:32] wire a_pop = |_a_pop_T; // @[Scheduler.scala:207:{32,79}] wire [6:0] _b_pop_T = selected_requests[13:7]; // @[Scheduler.scala:206:76, :208:32] wire b_pop = |_b_pop_T; // @[Scheduler.scala:208:{32,79}] wire _bypassMatches_T_4 = b_pop; // @[Scheduler.scala:208:79, :211:76] wire [6:0] _c_pop_T = selected_requests[20:14]; // @[Scheduler.scala:206:76, :209:32] wire c_pop = |_c_pop_T; // @[Scheduler.scala:209:{32,79}] wire [6:0] _bypassMatches_T = mshr_selectOH & lowerMatches1; // @[Scheduler.scala:121:70, :200:8, :210:38] wire _bypassMatches_T_1 = |_bypassMatches_T; // @[Scheduler.scala:210:{38,55}] wire _bypassMatches_T_2 = c_pop | request_bits_prio_2; // @[Scheduler.scala:163:21, :209:79, :211:33] wire _bypassMatches_T_3 = ~c_pop; // @[Scheduler.scala:209:79, :211:58] wire _bypassMatches_T_5 = ~b_pop; // @[Scheduler.scala:208:79, :211:101] wire _bypassMatches_T_6 = ~a_pop; // @[Scheduler.scala:207:79, :211:109] wire _bypassMatches_T_7 = _bypassMatches_T_4 ? _bypassMatches_T_5 : _bypassMatches_T_6; // @[Scheduler.scala:211:{69,76,101,109}] wire _bypassMatches_T_8 = _bypassMatches_T_2 ? _bypassMatches_T_3 : _bypassMatches_T_7; // @[Scheduler.scala:211:{26,33,58,69}] wire bypassMatches = _bypassMatches_T_1 & _bypassMatches_T_8; // @[Scheduler.scala:210:{55,59}, :211:26] wire _may_pop_T = a_pop | b_pop; // @[Scheduler.scala:207:79, :208:79, :212:23] wire may_pop = _may_pop_T | c_pop; // @[Scheduler.scala:209:79, :212:{23,32}] wire bypass = _bypass_T & bypassMatches; // @[Scheduler.scala:210:59, :213:{30,39}] wire _will_reload_T = may_pop | bypass; // @[Scheduler.scala:212:32, :213:39, :214:49] wire will_reload = schedule_reload & _will_reload_T; // @[Mux.scala:30:73] wire _GEN_2 = schedule_reload & may_pop; // @[Mux.scala:30:73] wire _will_pop_T; // @[Scheduler.scala:215:34] assign _will_pop_T = _GEN_2; // @[Scheduler.scala:215:34] wire _mshr_uses_directory_assuming_no_bypass_T; // @[Scheduler.scala:247:64] assign _mshr_uses_directory_assuming_no_bypass_T = _GEN_2; // @[Scheduler.scala:215:34, :247:64] wire _will_pop_T_1 = ~bypass; // @[Scheduler.scala:213:39, :215:48] wire will_pop = _will_pop_T & _will_pop_T_1; // @[Scheduler.scala:215:{34,45,48}] wire a_pop_1 = _requests_io_valid[0]; // @[Scheduler.scala:70:24, :225:34] wire b_pop_1 = _requests_io_valid[7]; // @[Scheduler.scala:70:24, :226:34] wire _bypassMatches_T_12 = b_pop_1; // @[Scheduler.scala:226:34, :229:78] wire c_pop_1 = _requests_io_valid[14]; // @[Scheduler.scala:70:24, :227:34] wire _bypassMatches_T_9 = lowerMatches1[0]; // @[Scheduler.scala:200:8, :228:38] wire _bypassMatches_T_10 = c_pop_1 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35] wire _bypassMatches_T_11 = ~c_pop_1; // @[Scheduler.scala:227:34, :229:60] wire _bypassMatches_T_13 = ~b_pop_1; // @[Scheduler.scala:226:34, :229:103] wire _bypassMatches_T_14 = ~a_pop_1; // @[Scheduler.scala:225:34, :229:111] wire _bypassMatches_T_15 = _bypassMatches_T_12 ? _bypassMatches_T_13 : _bypassMatches_T_14; // @[Scheduler.scala:229:{71,78,103,111}] wire _bypassMatches_T_16 = _bypassMatches_T_10 ? _bypassMatches_T_11 : _bypassMatches_T_15; // @[Scheduler.scala:229:{28,35,60,71}] wire bypassMatches_1 = _bypassMatches_T_9 & _bypassMatches_T_16; // @[Scheduler.scala:228:{38,42}, :229:28] wire _may_pop_T_1 = a_pop_1 | b_pop_1; // @[Scheduler.scala:225:34, :226:34, :230:25] wire may_pop_1 = _may_pop_T_1 | c_pop_1; // @[Scheduler.scala:227:34, :230:{25,34}] wire bypass_1 = _bypass_T_1 & bypassMatches_1; // @[Scheduler.scala:228:42, :231:{32,41}] wire _will_reload_T_1 = may_pop_1 | bypass_1; // @[Scheduler.scala:230:34, :231:41, :232:61] wire will_reload_1 = _mshrs_0_io_schedule_bits_reload & _will_reload_T_1; // @[Scheduler.scala:71:46, :232:{49,61}] wire _view__T_prio_0 = bypass_1 ? _view__WIRE_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_prio_1 = ~bypass_1 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78] wire _view__T_prio_2 = bypass_1 ? _view__WIRE_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_control = bypass_1 ? _view__WIRE_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_opcode = bypass_1 ? _view__WIRE_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_param = bypass_1 ? _view__WIRE_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_size = bypass_1 ? _view__WIRE_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_source = bypass_1 ? _view__WIRE_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [12:0] _view__T_tag = bypass_1 ? _view__WIRE_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_offset = bypass_1 ? _view__WIRE_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_put = bypass_1 ? _view__WIRE_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _mshrs_0_io_allocate_bits_repeat_T = mshrs_0_io_allocate_bits_tag == _mshrs_0_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70] wire _mshrs_0_io_allocate_valid_T = sel & will_reload_1; // @[Scheduler.scala:223:28, :232:49, :236:32] wire a_pop_2 = _requests_io_valid[1]; // @[Scheduler.scala:70:24, :225:34] wire b_pop_2 = _requests_io_valid[8]; // @[Scheduler.scala:70:24, :226:34] wire _bypassMatches_T_20 = b_pop_2; // @[Scheduler.scala:226:34, :229:78] wire c_pop_2 = _requests_io_valid[15]; // @[Scheduler.scala:70:24, :227:34] wire _bypassMatches_T_17 = lowerMatches1[1]; // @[Scheduler.scala:200:8, :228:38] wire _bypassMatches_T_18 = c_pop_2 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35] wire _bypassMatches_T_19 = ~c_pop_2; // @[Scheduler.scala:227:34, :229:60] wire _bypassMatches_T_21 = ~b_pop_2; // @[Scheduler.scala:226:34, :229:103] wire _bypassMatches_T_22 = ~a_pop_2; // @[Scheduler.scala:225:34, :229:111] wire _bypassMatches_T_23 = _bypassMatches_T_20 ? _bypassMatches_T_21 : _bypassMatches_T_22; // @[Scheduler.scala:229:{71,78,103,111}] wire _bypassMatches_T_24 = _bypassMatches_T_18 ? _bypassMatches_T_19 : _bypassMatches_T_23; // @[Scheduler.scala:229:{28,35,60,71}] wire bypassMatches_2 = _bypassMatches_T_17 & _bypassMatches_T_24; // @[Scheduler.scala:228:{38,42}, :229:28] wire _may_pop_T_2 = a_pop_2 | b_pop_2; // @[Scheduler.scala:225:34, :226:34, :230:25] wire may_pop_2 = _may_pop_T_2 | c_pop_2; // @[Scheduler.scala:227:34, :230:{25,34}] wire bypass_2 = _bypass_T_2 & bypassMatches_2; // @[Scheduler.scala:228:42, :231:{32,41}] wire _will_reload_T_2 = may_pop_2 | bypass_2; // @[Scheduler.scala:230:34, :231:41, :232:61] wire will_reload_2 = _mshrs_1_io_schedule_bits_reload & _will_reload_T_2; // @[Scheduler.scala:71:46, :232:{49,61}] wire _view__T_1_prio_0 = bypass_2 ? _view__WIRE_1_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_1_prio_1 = ~bypass_2 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78] wire _view__T_1_prio_2 = bypass_2 ? _view__WIRE_1_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_1_control = bypass_2 ? _view__WIRE_1_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_1_opcode = bypass_2 ? _view__WIRE_1_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_1_param = bypass_2 ? _view__WIRE_1_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_1_size = bypass_2 ? _view__WIRE_1_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_1_source = bypass_2 ? _view__WIRE_1_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [12:0] _view__T_1_tag = bypass_2 ? _view__WIRE_1_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_1_offset = bypass_2 ? _view__WIRE_1_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_1_put = bypass_2 ? _view__WIRE_1_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _mshrs_1_io_allocate_bits_repeat_T = mshrs_1_io_allocate_bits_tag == _mshrs_1_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70] wire _mshrs_1_io_allocate_valid_T = sel_1 & will_reload_2; // @[Scheduler.scala:223:28, :232:49, :236:32] wire a_pop_3 = _requests_io_valid[2]; // @[Scheduler.scala:70:24, :225:34] wire b_pop_3 = _requests_io_valid[9]; // @[Scheduler.scala:70:24, :226:34] wire _bypassMatches_T_28 = b_pop_3; // @[Scheduler.scala:226:34, :229:78] wire c_pop_3 = _requests_io_valid[16]; // @[Scheduler.scala:70:24, :227:34] wire _bypassMatches_T_25 = lowerMatches1[2]; // @[Scheduler.scala:200:8, :228:38] wire _bypassMatches_T_26 = c_pop_3 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35] wire _bypassMatches_T_27 = ~c_pop_3; // @[Scheduler.scala:227:34, :229:60] wire _bypassMatches_T_29 = ~b_pop_3; // @[Scheduler.scala:226:34, :229:103] wire _bypassMatches_T_30 = ~a_pop_3; // @[Scheduler.scala:225:34, :229:111] wire _bypassMatches_T_31 = _bypassMatches_T_28 ? _bypassMatches_T_29 : _bypassMatches_T_30; // @[Scheduler.scala:229:{71,78,103,111}] wire _bypassMatches_T_32 = _bypassMatches_T_26 ? _bypassMatches_T_27 : _bypassMatches_T_31; // @[Scheduler.scala:229:{28,35,60,71}] wire bypassMatches_3 = _bypassMatches_T_25 & _bypassMatches_T_32; // @[Scheduler.scala:228:{38,42}, :229:28] wire _may_pop_T_3 = a_pop_3 | b_pop_3; // @[Scheduler.scala:225:34, :226:34, :230:25] wire may_pop_3 = _may_pop_T_3 | c_pop_3; // @[Scheduler.scala:227:34, :230:{25,34}] wire bypass_3 = _bypass_T_3 & bypassMatches_3; // @[Scheduler.scala:228:42, :231:{32,41}] wire _will_reload_T_3 = may_pop_3 | bypass_3; // @[Scheduler.scala:230:34, :231:41, :232:61] wire will_reload_3 = _mshrs_2_io_schedule_bits_reload & _will_reload_T_3; // @[Scheduler.scala:71:46, :232:{49,61}] wire _view__T_2_prio_0 = bypass_3 ? _view__WIRE_2_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_2_prio_1 = ~bypass_3 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78] wire _view__T_2_prio_2 = bypass_3 ? _view__WIRE_2_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_2_control = bypass_3 ? _view__WIRE_2_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_2_opcode = bypass_3 ? _view__WIRE_2_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_2_param = bypass_3 ? _view__WIRE_2_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_2_size = bypass_3 ? _view__WIRE_2_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_2_source = bypass_3 ? _view__WIRE_2_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [12:0] _view__T_2_tag = bypass_3 ? _view__WIRE_2_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_2_offset = bypass_3 ? _view__WIRE_2_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_2_put = bypass_3 ? _view__WIRE_2_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _mshrs_2_io_allocate_bits_repeat_T = mshrs_2_io_allocate_bits_tag == _mshrs_2_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70] wire _mshrs_2_io_allocate_valid_T = sel_2 & will_reload_3; // @[Scheduler.scala:223:28, :232:49, :236:32] wire a_pop_4 = _requests_io_valid[3]; // @[Scheduler.scala:70:24, :225:34] wire b_pop_4 = _requests_io_valid[10]; // @[Scheduler.scala:70:24, :226:34] wire _bypassMatches_T_36 = b_pop_4; // @[Scheduler.scala:226:34, :229:78] wire c_pop_4 = _requests_io_valid[17]; // @[Scheduler.scala:70:24, :227:34] wire _bypassMatches_T_33 = lowerMatches1[3]; // @[Scheduler.scala:200:8, :228:38] wire _bypassMatches_T_34 = c_pop_4 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35] wire _bypassMatches_T_35 = ~c_pop_4; // @[Scheduler.scala:227:34, :229:60] wire _bypassMatches_T_37 = ~b_pop_4; // @[Scheduler.scala:226:34, :229:103] wire _bypassMatches_T_38 = ~a_pop_4; // @[Scheduler.scala:225:34, :229:111] wire _bypassMatches_T_39 = _bypassMatches_T_36 ? _bypassMatches_T_37 : _bypassMatches_T_38; // @[Scheduler.scala:229:{71,78,103,111}] wire _bypassMatches_T_40 = _bypassMatches_T_34 ? _bypassMatches_T_35 : _bypassMatches_T_39; // @[Scheduler.scala:229:{28,35,60,71}] wire bypassMatches_4 = _bypassMatches_T_33 & _bypassMatches_T_40; // @[Scheduler.scala:228:{38,42}, :229:28] wire _may_pop_T_4 = a_pop_4 | b_pop_4; // @[Scheduler.scala:225:34, :226:34, :230:25] wire may_pop_4 = _may_pop_T_4 | c_pop_4; // @[Scheduler.scala:227:34, :230:{25,34}] wire bypass_4 = _bypass_T_4 & bypassMatches_4; // @[Scheduler.scala:228:42, :231:{32,41}] wire _will_reload_T_4 = may_pop_4 | bypass_4; // @[Scheduler.scala:230:34, :231:41, :232:61] wire will_reload_4 = _mshrs_3_io_schedule_bits_reload & _will_reload_T_4; // @[Scheduler.scala:71:46, :232:{49,61}] wire _view__T_3_prio_0 = bypass_4 ? _view__WIRE_3_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_3_prio_1 = ~bypass_4 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78] wire _view__T_3_prio_2 = bypass_4 ? _view__WIRE_3_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_3_control = bypass_4 ? _view__WIRE_3_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_3_opcode = bypass_4 ? _view__WIRE_3_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_3_param = bypass_4 ? _view__WIRE_3_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_3_size = bypass_4 ? _view__WIRE_3_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_3_source = bypass_4 ? _view__WIRE_3_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [12:0] _view__T_3_tag = bypass_4 ? _view__WIRE_3_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_3_offset = bypass_4 ? _view__WIRE_3_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_3_put = bypass_4 ? _view__WIRE_3_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _mshrs_3_io_allocate_bits_repeat_T = mshrs_3_io_allocate_bits_tag == _mshrs_3_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70] wire _mshrs_3_io_allocate_valid_T = sel_3 & will_reload_4; // @[Scheduler.scala:223:28, :232:49, :236:32] wire a_pop_5 = _requests_io_valid[4]; // @[Scheduler.scala:70:24, :225:34] wire b_pop_5 = _requests_io_valid[11]; // @[Scheduler.scala:70:24, :226:34] wire _bypassMatches_T_44 = b_pop_5; // @[Scheduler.scala:226:34, :229:78] wire c_pop_5 = _requests_io_valid[18]; // @[Scheduler.scala:70:24, :227:34] wire _bypassMatches_T_41 = lowerMatches1[4]; // @[Scheduler.scala:200:8, :228:38] wire _bypassMatches_T_42 = c_pop_5 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35] wire _bypassMatches_T_43 = ~c_pop_5; // @[Scheduler.scala:227:34, :229:60] wire _bypassMatches_T_45 = ~b_pop_5; // @[Scheduler.scala:226:34, :229:103] wire _bypassMatches_T_46 = ~a_pop_5; // @[Scheduler.scala:225:34, :229:111] wire _bypassMatches_T_47 = _bypassMatches_T_44 ? _bypassMatches_T_45 : _bypassMatches_T_46; // @[Scheduler.scala:229:{71,78,103,111}] wire _bypassMatches_T_48 = _bypassMatches_T_42 ? _bypassMatches_T_43 : _bypassMatches_T_47; // @[Scheduler.scala:229:{28,35,60,71}] wire bypassMatches_5 = _bypassMatches_T_41 & _bypassMatches_T_48; // @[Scheduler.scala:228:{38,42}, :229:28] wire _may_pop_T_5 = a_pop_5 | b_pop_5; // @[Scheduler.scala:225:34, :226:34, :230:25] wire may_pop_5 = _may_pop_T_5 | c_pop_5; // @[Scheduler.scala:227:34, :230:{25,34}] wire bypass_5 = _bypass_T_5 & bypassMatches_5; // @[Scheduler.scala:228:42, :231:{32,41}] wire _will_reload_T_5 = may_pop_5 | bypass_5; // @[Scheduler.scala:230:34, :231:41, :232:61] wire will_reload_5 = _mshrs_4_io_schedule_bits_reload & _will_reload_T_5; // @[Scheduler.scala:71:46, :232:{49,61}] wire _view__T_4_prio_0 = bypass_5 ? _view__WIRE_4_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_4_prio_1 = ~bypass_5 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78] wire _view__T_4_prio_2 = bypass_5 ? _view__WIRE_4_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_4_control = bypass_5 ? _view__WIRE_4_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_4_opcode = bypass_5 ? _view__WIRE_4_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_4_param = bypass_5 ? _view__WIRE_4_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_4_size = bypass_5 ? _view__WIRE_4_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_4_source = bypass_5 ? _view__WIRE_4_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [12:0] _view__T_4_tag = bypass_5 ? _view__WIRE_4_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_4_offset = bypass_5 ? _view__WIRE_4_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_4_put = bypass_5 ? _view__WIRE_4_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _mshrs_4_io_allocate_bits_repeat_T = mshrs_4_io_allocate_bits_tag == _mshrs_4_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70] wire _mshrs_4_io_allocate_valid_T = sel_4 & will_reload_5; // @[Scheduler.scala:223:28, :232:49, :236:32] wire a_pop_6 = _requests_io_valid[5]; // @[Scheduler.scala:70:24, :225:34] wire b_pop_6 = _requests_io_valid[12]; // @[Scheduler.scala:70:24, :226:34] wire _bypassMatches_T_52 = b_pop_6; // @[Scheduler.scala:226:34, :229:78] wire c_pop_6 = _requests_io_valid[19]; // @[Scheduler.scala:70:24, :227:34] wire _bypassMatches_T_49 = lowerMatches1[5]; // @[Scheduler.scala:200:8, :228:38] wire _bypassMatches_T_50 = c_pop_6 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35] wire _bypassMatches_T_51 = ~c_pop_6; // @[Scheduler.scala:227:34, :229:60] wire _bypassMatches_T_53 = ~b_pop_6; // @[Scheduler.scala:226:34, :229:103] wire _bypassMatches_T_54 = ~a_pop_6; // @[Scheduler.scala:225:34, :229:111] wire _bypassMatches_T_55 = _bypassMatches_T_52 ? _bypassMatches_T_53 : _bypassMatches_T_54; // @[Scheduler.scala:229:{71,78,103,111}] wire _bypassMatches_T_56 = _bypassMatches_T_50 ? _bypassMatches_T_51 : _bypassMatches_T_55; // @[Scheduler.scala:229:{28,35,60,71}] wire bypassMatches_6 = _bypassMatches_T_49 & _bypassMatches_T_56; // @[Scheduler.scala:228:{38,42}, :229:28] wire _may_pop_T_6 = a_pop_6 | b_pop_6; // @[Scheduler.scala:225:34, :226:34, :230:25] wire may_pop_6 = _may_pop_T_6 | c_pop_6; // @[Scheduler.scala:227:34, :230:{25,34}] wire bypass_6 = _bypass_T_6 & bypassMatches_6; // @[Scheduler.scala:228:42, :231:{32,41}] wire _will_reload_T_6 = may_pop_6 | bypass_6; // @[Scheduler.scala:230:34, :231:41, :232:61] wire will_reload_6 = _mshrs_5_io_schedule_bits_reload & _will_reload_T_6; // @[Scheduler.scala:71:46, :232:{49,61}] wire _view__T_5_prio_0 = bypass_6 ? _view__WIRE_5_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_5_prio_1 = ~bypass_6 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78] wire _view__T_5_prio_2 = bypass_6 ? _view__WIRE_5_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_5_control = bypass_6 ? _view__WIRE_5_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_5_opcode = bypass_6 ? _view__WIRE_5_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_5_param = bypass_6 ? _view__WIRE_5_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_5_size = bypass_6 ? _view__WIRE_5_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_5_source = bypass_6 ? _view__WIRE_5_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [12:0] _view__T_5_tag = bypass_6 ? _view__WIRE_5_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_5_offset = bypass_6 ? _view__WIRE_5_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_5_put = bypass_6 ? _view__WIRE_5_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _mshrs_5_io_allocate_bits_repeat_T = mshrs_5_io_allocate_bits_tag == _mshrs_5_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70, :287:131, :289:74] wire _mshrs_5_io_allocate_valid_T = sel_5 & will_reload_6; // @[Scheduler.scala:223:28, :232:49, :236:32] wire a_pop_7 = _requests_io_valid[6]; // @[Scheduler.scala:70:24, :225:34] wire b_pop_7 = _requests_io_valid[13]; // @[Scheduler.scala:70:24, :226:34] wire _bypassMatches_T_60 = b_pop_7; // @[Scheduler.scala:226:34, :229:78] wire c_pop_7 = _requests_io_valid[20]; // @[Scheduler.scala:70:24, :227:34] wire _bypassMatches_T_57 = lowerMatches1[6]; // @[Scheduler.scala:200:8, :228:38] wire _bypassMatches_T_58 = c_pop_7 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35] wire _bypassMatches_T_59 = ~c_pop_7; // @[Scheduler.scala:227:34, :229:60] wire _bypassMatches_T_61 = ~b_pop_7; // @[Scheduler.scala:226:34, :229:103] wire _bypassMatches_T_62 = ~a_pop_7; // @[Scheduler.scala:225:34, :229:111] wire _bypassMatches_T_63 = _bypassMatches_T_60 ? _bypassMatches_T_61 : _bypassMatches_T_62; // @[Scheduler.scala:229:{71,78,103,111}] wire _bypassMatches_T_64 = _bypassMatches_T_58 ? _bypassMatches_T_59 : _bypassMatches_T_63; // @[Scheduler.scala:229:{28,35,60,71}] wire bypassMatches_7 = _bypassMatches_T_57 & _bypassMatches_T_64; // @[Scheduler.scala:228:{38,42}, :229:28] wire _may_pop_T_7 = a_pop_7 | b_pop_7; // @[Scheduler.scala:225:34, :226:34, :230:25] wire may_pop_7 = _may_pop_T_7 | c_pop_7; // @[Scheduler.scala:227:34, :230:{25,34}] wire bypass_7 = _bypass_T_7 & bypassMatches_7; // @[Scheduler.scala:228:42, :231:{32,41}] wire _will_reload_T_7 = may_pop_7 | bypass_7; // @[Scheduler.scala:230:34, :231:41, :232:61] wire will_reload_7 = _mshrs_6_io_schedule_bits_reload & _will_reload_T_7; // @[Scheduler.scala:71:46, :232:{49,61}] wire _view__T_6_prio_0 = bypass_7 ? _view__WIRE_6_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_6_prio_1 = ~bypass_7 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78] wire _view__T_6_prio_2 = bypass_7 ? _view__WIRE_6_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_6_control = bypass_7 ? _view__WIRE_6_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_6_opcode = bypass_7 ? _view__WIRE_6_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_6_param = bypass_7 ? _view__WIRE_6_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_6_size = bypass_7 ? _view__WIRE_6_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_6_source = bypass_7 ? _view__WIRE_6_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [12:0] _view__T_6_tag = bypass_7 ? _view__WIRE_6_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_6_offset = bypass_7 ? _view__WIRE_6_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_6_put = bypass_7 ? _view__WIRE_6_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _mshrs_6_io_allocate_bits_repeat_T = mshrs_6_io_allocate_bits_tag == _mshrs_6_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70, :295:103, :297:73] wire _mshrs_6_io_allocate_valid_T = sel_6 & will_reload_7; // @[Scheduler.scala:223:28, :232:49, :236:32] wire [20:0] _prio_requests_T = ~_requests_io_valid; // @[Scheduler.scala:70:24, :240:25] wire [13:0] _prio_requests_T_1 = _requests_io_valid[20:7]; // @[Scheduler.scala:70:24, :240:65] wire [20:0] _prio_requests_T_2 = {_prio_requests_T[20:14], _prio_requests_T[13:0] | _prio_requests_T_1}; // @[Scheduler.scala:240:{25,44,65}] wire [6:0] _prio_requests_T_3 = _requests_io_valid[20:14]; // @[Scheduler.scala:70:24, :240:103] wire [20:0] _prio_requests_T_4 = {_prio_requests_T_2[20:7], _prio_requests_T_2[6:0] | _prio_requests_T_3}; // @[Scheduler.scala:240:{44,82,103}] wire [20:0] prio_requests = ~_prio_requests_T_4; // @[Scheduler.scala:240:{23,82}] wire [20:0] _pop_index_T = {pop_index_hi, mshr_selectOH}; // @[Scheduler.scala:121:70, :241:31] wire [20:0] _pop_index_T_1 = _pop_index_T & prio_requests; // @[Scheduler.scala:240:23, :241:{31,77}] wire [4:0] pop_index_hi_1 = _pop_index_T_1[20:16]; // @[OneHot.scala:30:18] wire [15:0] pop_index_lo = _pop_index_T_1[15:0]; // @[OneHot.scala:31:18] wire _pop_index_T_2 = |pop_index_hi_1; // @[OneHot.scala:30:18, :32:14] wire [15:0] _pop_index_T_3 = {11'h0, pop_index_hi_1} | pop_index_lo; // @[OneHot.scala:30:18, :31:18, :32:28] wire [7:0] pop_index_hi_2 = _pop_index_T_3[15:8]; // @[OneHot.scala:30:18, :32:28] wire [7:0] pop_index_lo_1 = _pop_index_T_3[7:0]; // @[OneHot.scala:31:18, :32:28] wire _pop_index_T_4 = |pop_index_hi_2; // @[OneHot.scala:30:18, :32:14] wire [7:0] _pop_index_T_5 = pop_index_hi_2 | pop_index_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire [3:0] pop_index_hi_3 = _pop_index_T_5[7:4]; // @[OneHot.scala:30:18, :32:28] wire [3:0] pop_index_lo_2 = _pop_index_T_5[3:0]; // @[OneHot.scala:31:18, :32:28] wire _pop_index_T_6 = |pop_index_hi_3; // @[OneHot.scala:30:18, :32:14] wire [3:0] _pop_index_T_7 = pop_index_hi_3 | pop_index_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] pop_index_hi_4 = _pop_index_T_7[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] pop_index_lo_3 = _pop_index_T_7[1:0]; // @[OneHot.scala:31:18, :32:28] wire _pop_index_T_8 = |pop_index_hi_4; // @[OneHot.scala:30:18, :32:14] wire [1:0] _pop_index_T_9 = pop_index_hi_4 | pop_index_lo_3; // @[OneHot.scala:30:18, :31:18, :32:28] wire _pop_index_T_10 = _pop_index_T_9[1]; // @[OneHot.scala:32:28] wire [1:0] _pop_index_T_11 = {_pop_index_T_8, _pop_index_T_10}; // @[OneHot.scala:32:{10,14}] wire [2:0] _pop_index_T_12 = {_pop_index_T_6, _pop_index_T_11}; // @[OneHot.scala:32:{10,14}] wire [3:0] _pop_index_T_13 = {_pop_index_T_4, _pop_index_T_12}; // @[OneHot.scala:32:{10,14}] wire [4:0] pop_index = {_pop_index_T_2, _pop_index_T_13}; // @[OneHot.scala:32:{10,14}] wire lb_tag_mismatch = scheduleTag != _requests_io_data_tag; // @[Mux.scala:30:73] wire mshr_uses_directory_assuming_no_bypass = _mshr_uses_directory_assuming_no_bypass_T & lb_tag_mismatch; // @[Scheduler.scala:246:37, :247:{64,75}] wire mshr_uses_directory_for_lb = will_pop & lb_tag_mismatch; // @[Scheduler.scala:215:45, :246:37, :248:45] wire [12:0] _mshr_uses_directory_T = bypass ? request_bits_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :163:21, :213:39, :249:63] wire _mshr_uses_directory_T_1 = scheduleTag != _mshr_uses_directory_T; // @[Mux.scala:30:73] wire mshr_uses_directory = will_reload & _mshr_uses_directory_T_1; // @[Scheduler.scala:214:37, :249:{41,56}] wire [1:0] mshr_validOH_lo_hi = {_mshrs_2_io_status_valid, _mshrs_1_io_status_valid}; // @[Scheduler.scala:71:46, :252:25] wire [2:0] mshr_validOH_lo = {mshr_validOH_lo_hi, _mshrs_0_io_status_valid}; // @[Scheduler.scala:71:46, :252:25] wire [1:0] mshr_validOH_hi_lo = {_mshrs_4_io_status_valid, _mshrs_3_io_status_valid}; // @[Scheduler.scala:71:46, :252:25] wire [1:0] mshr_validOH_hi_hi = {_mshrs_6_io_status_valid, _mshrs_5_io_status_valid}; // @[Scheduler.scala:71:46, :252:25] wire [3:0] mshr_validOH_hi = {mshr_validOH_hi_hi, mshr_validOH_hi_lo}; // @[Scheduler.scala:252:25] wire [6:0] mshr_validOH = {mshr_validOH_hi, mshr_validOH_lo}; // @[Scheduler.scala:252:25] wire [6:0] _mshr_free_T = ~mshr_validOH; // @[Scheduler.scala:252:25, :253:20] wire [6:0] _mshr_free_T_1 = _mshr_free_T & prioFilter; // @[Scheduler.scala:182:23, :253:{20,34}] wire mshr_free = |_mshr_free_T_1; // @[Scheduler.scala:253:{34,48}] wire bypassQueue = schedule_reload & bypassMatches; // @[Mux.scala:30:73] wire _request_alloc_cases_T = ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16] wire _request_alloc_cases_T_1 = alloc & _request_alloc_cases_T; // @[Scheduler.scala:173:15, :258:{13,16}] wire _request_alloc_cases_T_2 = _request_alloc_cases_T_1 & mshr_free; // @[Scheduler.scala:253:48, :258:{13,56}] wire _request_alloc_cases_T_9 = _request_alloc_cases_T_2; // @[Scheduler.scala:258:{56,70}] wire _request_alloc_cases_T_3 = ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :259:16] wire _request_alloc_cases_T_5 = ~_mshrs_5_io_status_valid; // @[Scheduler.scala:71:46, :259:59] wire _request_alloc_cases_T_7 = ~_mshrs_6_io_status_valid; // @[Scheduler.scala:71:46, :259:87] wire _request_alloc_cases_T_10 = ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :260:16] wire _request_alloc_cases_T_11 = nestC & _request_alloc_cases_T_10; // @[Scheduler.scala:180:70, :260:{13,16}] wire _request_alloc_cases_T_12 = ~_mshrs_6_io_status_valid; // @[Scheduler.scala:71:46, :259:87, :260:59] wire _request_alloc_cases_T_13 = _request_alloc_cases_T_11 & _request_alloc_cases_T_12; // @[Scheduler.scala:260:{13,56,59}] wire request_alloc_cases = _request_alloc_cases_T_9 | _request_alloc_cases_T_13; // @[Scheduler.scala:258:70, :259:112, :260:56] wire _request_ready_T = bypassQueue | _requests_io_push_ready; // @[Scheduler.scala:70:24, :256:37, :261:66] wire _request_ready_T_1 = queue & _request_ready_T; // @[Scheduler.scala:185:63, :261:{50,66}] assign _request_ready_T_2 = request_alloc_cases | _request_ready_T_1; // @[Scheduler.scala:259:112, :261:{40,50}] assign request_ready = _request_ready_T_2; // @[Scheduler.scala:163:21, :261:40] wire alloc_uses_directory = request_valid & request_alloc_cases; // @[Scheduler.scala:163:21, :259:112, :262:44] wire _directory_io_read_valid_T = mshr_uses_directory | alloc_uses_directory; // @[Scheduler.scala:249:41, :262:44, :265:50] wire [9:0] _directory_io_read_bits_set_T = mshr_uses_directory_for_lb ? scheduleSet : request_bits_set; // @[Mux.scala:30:73] wire [12:0] _directory_io_read_bits_tag_T = mshr_uses_directory_for_lb ? _requests_io_data_tag : request_bits_tag; // @[Scheduler.scala:70:24, :163:21, :248:45, :267:36] wire _requests_io_push_valid_T_1 = ~bypassQueue; // @[Scheduler.scala:256:37, :270:55] wire _requests_io_push_valid_T_2 = _requests_io_push_valid_T & _requests_io_push_valid_T_1; // @[Scheduler.scala:270:{43,52,55}] wire [2:0] requests_io_push_bits_index_hi = _requests_io_push_bits_index_T[6:4]; // @[OneHot.scala:30:18] wire [3:0] requests_io_push_bits_index_lo = _requests_io_push_bits_index_T[3:0]; // @[OneHot.scala:31:18] wire _requests_io_push_bits_index_T_1 = |requests_io_push_bits_index_hi; // @[OneHot.scala:30:18, :32:14] wire [3:0] _requests_io_push_bits_index_T_2 = {1'h0, requests_io_push_bits_index_hi} | requests_io_push_bits_index_lo; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] requests_io_push_bits_index_hi_1 = _requests_io_push_bits_index_T_2[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] requests_io_push_bits_index_lo_1 = _requests_io_push_bits_index_T_2[1:0]; // @[OneHot.scala:31:18, :32:28] wire _requests_io_push_bits_index_T_3 = |requests_io_push_bits_index_hi_1; // @[OneHot.scala:30:18, :32:14] wire [1:0] _requests_io_push_bits_index_T_4 = requests_io_push_bits_index_hi_1 | requests_io_push_bits_index_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire _requests_io_push_bits_index_T_5 = _requests_io_push_bits_index_T_4[1]; // @[OneHot.scala:32:28] wire [1:0] _requests_io_push_bits_index_T_6 = {_requests_io_push_bits_index_T_3, _requests_io_push_bits_index_T_5}; // @[OneHot.scala:32:{10,14}] wire [2:0] _requests_io_push_bits_index_T_7 = {_requests_io_push_bits_index_T_1, _requests_io_push_bits_index_T_6}; // @[OneHot.scala:32:{10,14}] wire [13:0] _requests_io_push_bits_index_T_8 = {lowerMatches1, 7'h0}; // @[Scheduler.scala:200:8, :275:30] wire [5:0] requests_io_push_bits_index_hi_2 = _requests_io_push_bits_index_T_8[13:8]; // @[OneHot.scala:30:18] wire [7:0] requests_io_push_bits_index_lo_2 = _requests_io_push_bits_index_T_8[7:0]; // @[OneHot.scala:31:18] wire _requests_io_push_bits_index_T_9 = |requests_io_push_bits_index_hi_2; // @[OneHot.scala:30:18, :32:14] wire [7:0] _requests_io_push_bits_index_T_10 = {2'h0, requests_io_push_bits_index_hi_2} | requests_io_push_bits_index_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28] wire [3:0] requests_io_push_bits_index_hi_3 = _requests_io_push_bits_index_T_10[7:4]; // @[OneHot.scala:30:18, :32:28] wire [3:0] requests_io_push_bits_index_lo_3 = _requests_io_push_bits_index_T_10[3:0]; // @[OneHot.scala:31:18, :32:28] wire _requests_io_push_bits_index_T_11 = |requests_io_push_bits_index_hi_3; // @[OneHot.scala:30:18, :32:14] wire [3:0] _requests_io_push_bits_index_T_12 = requests_io_push_bits_index_hi_3 | requests_io_push_bits_index_lo_3; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] requests_io_push_bits_index_hi_4 = _requests_io_push_bits_index_T_12[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] requests_io_push_bits_index_lo_4 = _requests_io_push_bits_index_T_12[1:0]; // @[OneHot.scala:31:18, :32:28] wire _requests_io_push_bits_index_T_13 = |requests_io_push_bits_index_hi_4; // @[OneHot.scala:30:18, :32:14] wire [1:0] _requests_io_push_bits_index_T_14 = requests_io_push_bits_index_hi_4 | requests_io_push_bits_index_lo_4; // @[OneHot.scala:30:18, :31:18, :32:28] wire _requests_io_push_bits_index_T_15 = _requests_io_push_bits_index_T_14[1]; // @[OneHot.scala:32:28] wire [1:0] _requests_io_push_bits_index_T_16 = {_requests_io_push_bits_index_T_13, _requests_io_push_bits_index_T_15}; // @[OneHot.scala:32:{10,14}] wire [2:0] _requests_io_push_bits_index_T_17 = {_requests_io_push_bits_index_T_11, _requests_io_push_bits_index_T_16}; // @[OneHot.scala:32:{10,14}] wire [3:0] _requests_io_push_bits_index_T_18 = {_requests_io_push_bits_index_T_9, _requests_io_push_bits_index_T_17}; // @[OneHot.scala:32:{10,14}] wire [20:0] _requests_io_push_bits_index_T_19 = {lowerMatches1, 14'h0}; // @[Scheduler.scala:200:8, :276:30] wire [4:0] requests_io_push_bits_index_hi_5 = _requests_io_push_bits_index_T_19[20:16]; // @[OneHot.scala:30:18] wire [15:0] requests_io_push_bits_index_lo_5 = _requests_io_push_bits_index_T_19[15:0]; // @[OneHot.scala:31:18] wire _requests_io_push_bits_index_T_20 = |requests_io_push_bits_index_hi_5; // @[OneHot.scala:30:18, :32:14] wire [15:0] _requests_io_push_bits_index_T_21 = {11'h0, requests_io_push_bits_index_hi_5} | requests_io_push_bits_index_lo_5; // @[OneHot.scala:30:18, :31:18, :32:28] wire [7:0] requests_io_push_bits_index_hi_6 = _requests_io_push_bits_index_T_21[15:8]; // @[OneHot.scala:30:18, :32:28] wire [7:0] requests_io_push_bits_index_lo_6 = _requests_io_push_bits_index_T_21[7:0]; // @[OneHot.scala:31:18, :32:28] wire _requests_io_push_bits_index_T_22 = |requests_io_push_bits_index_hi_6; // @[OneHot.scala:30:18, :32:14] wire [7:0] _requests_io_push_bits_index_T_23 = requests_io_push_bits_index_hi_6 | requests_io_push_bits_index_lo_6; // @[OneHot.scala:30:18, :31:18, :32:28] wire [3:0] requests_io_push_bits_index_hi_7 = _requests_io_push_bits_index_T_23[7:4]; // @[OneHot.scala:30:18, :32:28] wire [3:0] requests_io_push_bits_index_lo_7 = _requests_io_push_bits_index_T_23[3:0]; // @[OneHot.scala:31:18, :32:28] wire _requests_io_push_bits_index_T_24 = |requests_io_push_bits_index_hi_7; // @[OneHot.scala:30:18, :32:14] wire [3:0] _requests_io_push_bits_index_T_25 = requests_io_push_bits_index_hi_7 | requests_io_push_bits_index_lo_7; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] requests_io_push_bits_index_hi_8 = _requests_io_push_bits_index_T_25[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] requests_io_push_bits_index_lo_8 = _requests_io_push_bits_index_T_25[1:0]; // @[OneHot.scala:31:18, :32:28] wire _requests_io_push_bits_index_T_26 = |requests_io_push_bits_index_hi_8; // @[OneHot.scala:30:18, :32:14] wire [1:0] _requests_io_push_bits_index_T_27 = requests_io_push_bits_index_hi_8 | requests_io_push_bits_index_lo_8; // @[OneHot.scala:30:18, :31:18, :32:28] wire _requests_io_push_bits_index_T_28 = _requests_io_push_bits_index_T_27[1]; // @[OneHot.scala:32:28] wire [1:0] _requests_io_push_bits_index_T_29 = {_requests_io_push_bits_index_T_26, _requests_io_push_bits_index_T_28}; // @[OneHot.scala:32:{10,14}] wire [2:0] _requests_io_push_bits_index_T_30 = {_requests_io_push_bits_index_T_24, _requests_io_push_bits_index_T_29}; // @[OneHot.scala:32:{10,14}] wire [3:0] _requests_io_push_bits_index_T_31 = {_requests_io_push_bits_index_T_22, _requests_io_push_bits_index_T_30}; // @[OneHot.scala:32:{10,14}] wire [4:0] _requests_io_push_bits_index_T_32 = {_requests_io_push_bits_index_T_20, _requests_io_push_bits_index_T_31}; // @[OneHot.scala:32:{10,14}] wire [2:0] _requests_io_push_bits_index_T_33 = request_bits_prio_0 ? _requests_io_push_bits_index_T_7 : 3'h0; // @[OneHot.scala:32:10] wire [4:0] _requests_io_push_bits_index_T_35 = request_bits_prio_2 ? _requests_io_push_bits_index_T_32 : 5'h0; // @[OneHot.scala:32:10] wire [3:0] _requests_io_push_bits_index_T_36 = {1'h0, _requests_io_push_bits_index_T_33}; // @[Mux.scala:30:73] wire [4:0] _requests_io_push_bits_index_T_37 = {1'h0, _requests_io_push_bits_index_T_36} | _requests_io_push_bits_index_T_35; // @[Mux.scala:30:73] wire [4:0] _requests_io_push_bits_index_WIRE = _requests_io_push_bits_index_T_37; // @[Mux.scala:30:73] wire [6:0] _mshr_insertOH_T = ~mshr_validOH; // @[Scheduler.scala:252:25, :253:20, :278:32] wire [7:0] _mshr_insertOH_T_1 = {_mshr_insertOH_T, 1'h0}; // @[package.scala:253:48] wire [6:0] _mshr_insertOH_T_2 = _mshr_insertOH_T_1[6:0]; // @[package.scala:253:{48,53}] wire [6:0] _mshr_insertOH_T_3 = _mshr_insertOH_T | _mshr_insertOH_T_2; // @[package.scala:253:{43,53}] wire [8:0] _mshr_insertOH_T_4 = {_mshr_insertOH_T_3, 2'h0}; // @[package.scala:253:{43,48}] wire [6:0] _mshr_insertOH_T_5 = _mshr_insertOH_T_4[6:0]; // @[package.scala:253:{48,53}] wire [6:0] _mshr_insertOH_T_6 = _mshr_insertOH_T_3 | _mshr_insertOH_T_5; // @[package.scala:253:{43,53}] wire [10:0] _mshr_insertOH_T_7 = {_mshr_insertOH_T_6, 4'h0}; // @[package.scala:253:{43,48}] wire [6:0] _mshr_insertOH_T_8 = _mshr_insertOH_T_7[6:0]; // @[package.scala:253:{48,53}] wire [6:0] _mshr_insertOH_T_9 = _mshr_insertOH_T_6 | _mshr_insertOH_T_8; // @[package.scala:253:{43,53}] wire [6:0] _mshr_insertOH_T_10 = _mshr_insertOH_T_9; // @[package.scala:253:43, :254:17] wire [7:0] _mshr_insertOH_T_11 = {_mshr_insertOH_T_10, 1'h0}; // @[package.scala:254:17] wire [7:0] _mshr_insertOH_T_12 = ~_mshr_insertOH_T_11; // @[Scheduler.scala:278:{23,47}] wire [6:0] _mshr_insertOH_T_13 = ~mshr_validOH; // @[Scheduler.scala:252:25, :253:20, :278:55] wire [7:0] _mshr_insertOH_T_14 = {1'h0, _mshr_insertOH_T_12[6:0] & _mshr_insertOH_T_13}; // @[Scheduler.scala:278:{23,53,55}] wire [7:0] mshr_insertOH = {1'h0, _mshr_insertOH_T_14[6:0] & prioFilter}; // @[Scheduler.scala:182:23, :278:{53,69}] wire _T_46 = request_valid & alloc; // @[Scheduler.scala:163:21, :173:15, :280:25] wire _T_25 = _T_46 & mshr_insertOH[0] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}] assign mshrs_0_io_allocate_bits_tag = _T_25 ? request_bits_tag : _view__T_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70] wire _T_29 = _T_46 & mshr_insertOH[1] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}] assign mshrs_1_io_allocate_bits_tag = _T_29 ? request_bits_tag : _view__T_1_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70] wire _T_33 = _T_46 & mshr_insertOH[2] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}] assign mshrs_2_io_allocate_bits_tag = _T_33 ? request_bits_tag : _view__T_2_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70] wire _T_37 = _T_46 & mshr_insertOH[3] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}] assign mshrs_3_io_allocate_bits_tag = _T_37 ? request_bits_tag : _view__T_3_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70] wire _T_41 = _T_46 & mshr_insertOH[4] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}] assign mshrs_4_io_allocate_bits_tag = _T_41 ? request_bits_tag : _view__T_4_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70] wire _T_45 = _T_46 & mshr_insertOH[5] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}] assign mshrs_5_io_allocate_bits_tag = _T_45 ? request_bits_tag : _view__T_5_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70, :287:131, :289:74] wire _T_65 = request_valid & nestC & ~_mshrs_6_io_status_valid & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:71:46, :163:21, :180:70, :193:33, :247:75, :258:16, :259:87, :295:{32,59}] wire _GEN_3 = _T_65 | _T_46 & mshr_insertOH[6] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:193:33, :236:25, :247:75, :258:16, :278:69, :279:18, :280:{25,34,39,83}, :281:27, :295:{32,59,103}, :296:30] assign mshrs_6_io_allocate_bits_tag = _GEN_3 ? request_bits_tag : _view__T_6_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :236:25, :280:83, :281:27, :282:70, :295:103, :296:30, :297:73]

Generate the Verilog code corresponding to the following Chisel files. File Buffer.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.BufferParams class TLBufferNode ( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit valName: ValName) extends TLAdapterNode( clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) }, managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) } ) { override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}" override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none) } class TLBuffer( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters) extends LazyModule { def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace) def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde) def this()(implicit p: Parameters) = this(BufferParams.default) val node = new TLBufferNode(a, b, c, d, e) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def headBundle = node.out.head._2.bundle override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.a <> a(in .a) in .d <> d(out.d) if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) { in .b <> b(out.b) out.c <> c(in .c) out.e <> e(in .e) } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLBuffer { def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default) def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde) def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace) def apply( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters): TLNode = { val buffer = LazyModule(new TLBuffer(a, b, c, d, e)) buffer.node } def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = { val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) } name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } } buffers.map(_.node) } def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = { chain(depth, name) .reduceLeftOption(_ :*=* _) .getOrElse(TLNameNode("no_buffer")) } } File Crossing.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.interrupts import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg} @deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2") class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val intnode = IntAdapterNode() lazy val module = new Impl class Impl extends LazyModuleImp(this) { (intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) => out := SynchronizerShiftReg(in, sync) } } } object IntSyncCrossingSource { def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) = { val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered)) intsource.node } } class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule { val node = IntSyncSourceNode(alreadyRegistered) lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl) class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := AsyncResetReg(Cat(in.reverse)).asBools } } class ImplRegistered extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}_Registered" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := in } } } object IntSyncCrossingSink { @deprecated("IntSyncCrossingSink which used the `sync` parameter to determine crossing type is deprecated. Use IntSyncAsyncCrossingSink, IntSyncRationalCrossingSink, or IntSyncSyncCrossingSink instead for > 1, 1, and 0 sync values respectively", "rocket-chip 1.2") def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncAsyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(sync) lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = s"IntSyncAsyncCrossingSink_n${node.out.size}x${node.out.head._1.size}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := SynchronizerShiftReg(in.sync, sync) } } } object IntSyncAsyncCrossingSink { def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncSyncCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(0) lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncSyncCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := in.sync } } } object IntSyncSyncCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncSyncCrossingSink()) intsink.node } } class IntSyncRationalCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(1) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncRationalCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := RegNext(in.sync) } } } object IntSyncRationalCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncRationalCrossingSink()) intsink.node } } File ClockDomain.scala: package freechips.rocketchip.prci import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ abstract class Domain(implicit p: Parameters) extends LazyModule with HasDomainCrossing { def clockBundle: ClockBundle lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { childClock := clockBundle.clock childReset := clockBundle.reset override def provideImplicitClockToLazyChildren = true // these are just for backwards compatibility with external devices // that were manually wiring themselves to the domain's clock/reset input: val clock = IO(Output(chiselTypeOf(clockBundle.clock))) val reset = IO(Output(chiselTypeOf(clockBundle.reset))) clock := clockBundle.clock reset := clockBundle.reset } } abstract class ClockDomain(implicit p: Parameters) extends Domain with HasClockDomainCrossing class ClockSinkDomain(val clockSinkParams: ClockSinkParameters)(implicit p: Parameters) extends ClockDomain { def this(take: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSinkParameters(take = take, name = name)) val clockNode = ClockSinkNode(Seq(clockSinkParams)) def clockBundle = clockNode.in.head._1 override lazy val desiredName = (clockSinkParams.name.toSeq :+ "ClockSinkDomain").mkString } class ClockSourceDomain(val clockSourceParams: ClockSourceParameters)(implicit p: Parameters) extends ClockDomain { def this(give: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSourceParameters(give = give, name = name)) val clockNode = ClockSourceNode(Seq(clockSourceParams)) def clockBundle = clockNode.out.head._1 override lazy val desiredName = (clockSourceParams.name.toSeq :+ "ClockSourceDomain").mkString } abstract class ResetDomain(implicit p: Parameters) extends Domain with HasResetDomainCrossing File HasTiles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.subsystem import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.bundlebridge._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.devices.debug.TLDebugModule import freechips.rocketchip.diplomacy.{DisableMonitors, FlipRendering} import freechips.rocketchip.interrupts.{IntXbar, IntSinkNode, IntSinkPortSimple, IntSyncAsyncCrossingSink} import freechips.rocketchip.tile.{MaxHartIdBits, BaseTile, InstantiableTileParams, TileParams, TilePRCIDomain, TraceBundle, PriorityMuxHartIdFromSeq} import freechips.rocketchip.tilelink.TLWidthWidget import freechips.rocketchip.prci.{ClockGroup, BundleBridgeBlockDuringReset, NoCrossing, SynchronousCrossing, CreditedCrossing, RationalCrossing, AsynchronousCrossing} import freechips.rocketchip.rocket.TracedInstruction import freechips.rocketchip.util.TraceCoreInterface import scala.collection.immutable.SortedMap /** Entry point for Config-uring the presence of Tiles */ case class TilesLocated(loc: HierarchicalLocation) extends Field[Seq[CanAttachTile]](Nil) /** List of HierarchicalLocations which might contain a Tile */ case object PossibleTileLocations extends Field[Seq[HierarchicalLocation]](Nil) /** For determining static tile id */ case object NumTiles extends Field[Int](0) /** Whether to add timing-closure registers along the path of the hart id * as it propagates through the subsystem and into the tile. * * These are typically only desirable when a dynamically programmable prefix is being combined * with the static hart id via [[freechips.rocketchip.subsystem.HasTiles.tileHartIdNexusNode]]. */ case object InsertTimingClosureRegistersOnHartIds extends Field[Boolean](false) /** Whether per-tile hart ids are going to be driven as inputs into a HasTiles block, * and if so, what their width should be. */ case object HasTilesExternalHartIdWidthKey extends Field[Option[Int]](None) /** Whether per-tile reset vectors are going to be driven as inputs into a HasTiles block. * * Unlike the hart ids, the reset vector width is determined by the sinks within the tiles, * based on the size of the address map visible to the tiles. */ case object HasTilesExternalResetVectorKey extends Field[Boolean](true) /** These are sources of "constants" that are driven into the tile. * * While they are not expected to change dyanmically while the tile is executing code, * they may be either tied to a contant value or programmed during boot or reset. * They need to be instantiated before tiles are attached within the subsystem containing them. */ trait HasTileInputConstants { this: LazyModule with Attachable with InstantiatesHierarchicalElements => /** tileHartIdNode is used to collect publishers and subscribers of hartids. */ val tileHartIdNodes: SortedMap[Int, BundleBridgeEphemeralNode[UInt]] = (0 until nTotalTiles).map { i => (i, BundleBridgeEphemeralNode[UInt]()) }.to(SortedMap) /** tileHartIdNexusNode is a BundleBridgeNexus that collects dynamic hart prefixes. * * Each "prefix" input is actually the same full width as the outer hart id; the expected usage * is that each prefix source would set only some non-overlapping portion of the bits to non-zero values. * This node orReduces them, and further combines the reduction with the static ids assigned to each tile, * producing a unique, dynamic hart id for each tile. * * If p(InsertTimingClosureRegistersOnHartIds) is set, the input and output values are registered. * * The output values are [[dontTouch]]'d to prevent constant propagation from pulling the values into * the tiles if they are constant, which would ruin deduplication of tiles that are otherwise homogeneous. */ val tileHartIdNexusNode = LazyModule(new BundleBridgeNexus[UInt]( inputFn = BundleBridgeNexus.orReduction[UInt](registered = p(InsertTimingClosureRegistersOnHartIds)) _, outputFn = (prefix: UInt, n: Int) => Seq.tabulate(n) { i => val y = dontTouch(prefix | totalTileIdList(i).U(p(MaxHartIdBits).W)) // dontTouch to keep constant prop from breaking tile dedup if (p(InsertTimingClosureRegistersOnHartIds)) BundleBridgeNexus.safeRegNext(y) else y }, default = Some(() => 0.U(p(MaxHartIdBits).W)), inputRequiresOutput = true, // guard against this being driven but then ignored in tileHartIdIONodes below shouldBeInlined = false // can't inline something whose output we are are dontTouching )).node // TODO: Replace the DebugModuleHartSelFuncs config key with logic to consume the dynamic hart IDs /** tileResetVectorNode is used to collect publishers and subscribers of tile reset vector addresses. */ val tileResetVectorNodes: SortedMap[Int, BundleBridgeEphemeralNode[UInt]] = (0 until nTotalTiles).map { i => (i, BundleBridgeEphemeralNode[UInt]()) }.to(SortedMap) /** tileResetVectorNexusNode is a BundleBridgeNexus that accepts a single reset vector source, and broadcasts it to all tiles. */ val tileResetVectorNexusNode = BundleBroadcast[UInt]( inputRequiresOutput = true // guard against this being driven but ignored in tileResetVectorIONodes below ) /** tileHartIdIONodes may generate subsystem IOs, one per tile, allowing the parent to assign unique hart ids. * * Or, if such IOs are not configured to exist, tileHartIdNexusNode is used to supply an id to each tile. */ val tileHartIdIONodes: Seq[BundleBridgeSource[UInt]] = p(HasTilesExternalHartIdWidthKey) match { case Some(w) => (0 until nTotalTiles).map { i => val hartIdSource = BundleBridgeSource(() => UInt(w.W)) tileHartIdNodes(i) := hartIdSource hartIdSource } case None => { (0 until nTotalTiles).map { i => tileHartIdNodes(i) :*= tileHartIdNexusNode } Nil } } /** tileResetVectorIONodes may generate subsystem IOs, one per tile, allowing the parent to assign unique reset vectors. * * Or, if such IOs are not configured to exist, tileResetVectorNexusNode is used to supply a single reset vector to every tile. */ val tileResetVectorIONodes: Seq[BundleBridgeSource[UInt]] = p(HasTilesExternalResetVectorKey) match { case true => (0 until nTotalTiles).map { i => val resetVectorSource = BundleBridgeSource[UInt]() tileResetVectorNodes(i) := resetVectorSource resetVectorSource } case false => { (0 until nTotalTiles).map { i => tileResetVectorNodes(i) :*= tileResetVectorNexusNode } Nil } } } /** These are sinks of notifications that are driven out from the tile. * * They need to be instantiated before tiles are attached to the subsystem containing them. */ trait HasTileNotificationSinks { this: LazyModule => val tileHaltXbarNode = IntXbar() val tileHaltSinkNode = IntSinkNode(IntSinkPortSimple()) tileHaltSinkNode := tileHaltXbarNode val tileWFIXbarNode = IntXbar() val tileWFISinkNode = IntSinkNode(IntSinkPortSimple()) tileWFISinkNode := tileWFIXbarNode val tileCeaseXbarNode = IntXbar() val tileCeaseSinkNode = IntSinkNode(IntSinkPortSimple()) tileCeaseSinkNode := tileCeaseXbarNode } /** Standardized interface by which parameterized tiles can be attached to contexts containing interconnect resources. * * Sub-classes of this trait can optionally override the individual connect functions in order to specialize * their attachment behaviors, but most use cases should be be handled simply by changing the implementation * of the injectNode functions in crossingParams. */ trait CanAttachTile { type TileType <: BaseTile type TileContextType <: DefaultHierarchicalElementContextType def tileParams: InstantiableTileParams[TileType] def crossingParams: HierarchicalElementCrossingParamsLike /** Narrow waist through which all tiles are intended to pass while being instantiated. */ def instantiate(allTileParams: Seq[TileParams], instantiatedTiles: SortedMap[Int, TilePRCIDomain[_]])(implicit p: Parameters): TilePRCIDomain[TileType] = { val clockSinkParams = tileParams.clockSinkParams.copy(name = Some(tileParams.uniqueName)) val tile_prci_domain = LazyModule(new TilePRCIDomain[TileType](clockSinkParams, crossingParams) { self => val element = self.element_reset_domain { LazyModule(tileParams.instantiate(crossingParams, PriorityMuxHartIdFromSeq(allTileParams))) } }) tile_prci_domain } /** A default set of connections that need to occur for most tile types */ def connect(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = { connectMasterPorts(domain, context) connectSlavePorts(domain, context) connectInterrupts(domain, context) connectPRC(domain, context) connectOutputNotifications(domain, context) connectInputConstants(domain, context) connectTrace(domain, context) } /** Connect the port where the tile is the master to a TileLink interconnect. */ def connectMasterPorts(domain: TilePRCIDomain[TileType], context: Attachable): Unit = { implicit val p = context.p val dataBus = context.locateTLBusWrapper(crossingParams.master.where) dataBus.coupleFrom(tileParams.baseName) { bus => bus :=* crossingParams.master.injectNode(context) :=* domain.crossMasterPort(crossingParams.crossingType) } } /** Connect the port where the tile is the slave to a TileLink interconnect. */ def connectSlavePorts(domain: TilePRCIDomain[TileType], context: Attachable): Unit = { implicit val p = context.p DisableMonitors { implicit p => val controlBus = context.locateTLBusWrapper(crossingParams.slave.where) controlBus.coupleTo(tileParams.baseName) { bus => domain.crossSlavePort(crossingParams.crossingType) :*= crossingParams.slave.injectNode(context) :*= TLWidthWidget(controlBus.beatBytes) :*= bus } } } /** Connect the various interrupts sent to and and raised by the tile. */ def connectInterrupts(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = { implicit val p = context.p // NOTE: The order of calls to := matters! They must match how interrupts // are decoded from tile.intInwardNode inside the tile. For this reason, // we stub out missing interrupts with constant sources here. // 1. Debug interrupt is definitely asynchronous in all cases. domain.element.intInwardNode := domain { IntSyncAsyncCrossingSink(3) } := context.debugNodes(domain.element.tileId) // 2. The CLINT and PLIC output interrupts are synchronous to the CLINT/PLIC respectively, // so might need to be synchronized depending on the Tile's crossing type. // From CLINT: "msip" and "mtip" context.msipDomain { domain.crossIntIn(crossingParams.crossingType, domain.element.intInwardNode) := context.msipNodes(domain.element.tileId) } // From PLIC: "meip" context.meipDomain { domain.crossIntIn(crossingParams.crossingType, domain.element.intInwardNode) := context.meipNodes(domain.element.tileId) } // From PLIC: "seip" (only if supervisor mode is enabled) if (domain.element.tileParams.core.hasSupervisorMode) { context.seipDomain { domain.crossIntIn(crossingParams.crossingType, domain.element.intInwardNode) := context.seipNodes(domain.element.tileId) } } // 3. Local Interrupts ("lip") are required to already be synchronous to the Tile's clock. // (they are connected to domain.element.intInwardNode in a seperate trait) // 4. Interrupts coming out of the tile are sent to the PLIC, // so might need to be synchronized depending on the Tile's crossing type. context.tileToPlicNodes.get(domain.element.tileId).foreach { node => FlipRendering { implicit p => domain.element.intOutwardNode.foreach { out => context.toPlicDomain { node := domain.crossIntOut(crossingParams.crossingType, out) } }} } // 5. Connect NMI inputs to the tile. These inputs are synchronous to the respective core_clock. domain.element.nmiNode.foreach(_ := context.nmiNodes(domain.element.tileId)) } /** Notifications of tile status are connected to be broadcast without needing to be clock-crossed. */ def connectOutputNotifications(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = { implicit val p = context.p domain { context.tileHaltXbarNode :=* domain.crossIntOut(NoCrossing, domain.element.haltNode) context.tileWFIXbarNode :=* domain.crossIntOut(NoCrossing, domain.element.wfiNode) context.tileCeaseXbarNode :=* domain.crossIntOut(NoCrossing, domain.element.ceaseNode) } // TODO should context be forced to have a trace sink connected here? // for now this just ensures domain.trace[Core]Node has been crossed without connecting it externally } /** Connect inputs to the tile that are assumed to be constant during normal operation, and so are not clock-crossed. */ def connectInputConstants(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = { implicit val p = context.p val tlBusToGetPrefixFrom = context.locateTLBusWrapper(crossingParams.mmioBaseAddressPrefixWhere) domain.element.hartIdNode := context.tileHartIdNodes(domain.element.tileId) domain.element.resetVectorNode := context.tileResetVectorNodes(domain.element.tileId) tlBusToGetPrefixFrom.prefixNode.foreach { domain.element.mmioAddressPrefixNode := _ } } /** Connect power/reset/clock resources. */ def connectPRC(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = { implicit val p = context.p val tlBusToGetClockDriverFrom = context.locateTLBusWrapper(crossingParams.master.where) (crossingParams.crossingType match { case _: SynchronousCrossing | _: CreditedCrossing => if (crossingParams.forceSeparateClockReset) { domain.clockNode := tlBusToGetClockDriverFrom.clockNode } else { domain.clockNode := tlBusToGetClockDriverFrom.fixedClockNode } case _: RationalCrossing => domain.clockNode := tlBusToGetClockDriverFrom.clockNode case _: AsynchronousCrossing => { val tileClockGroup = ClockGroup() tileClockGroup := context.allClockGroupsNode domain.clockNode := tileClockGroup } }) domain { domain.element_reset_domain.clockNode := crossingParams.resetCrossingType.injectClockNode := domain.clockNode } } /** Function to handle all trace crossings when tile is instantiated inside domains */ def connectTrace(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = { implicit val p = context.p val traceCrossingNode = BundleBridgeBlockDuringReset[TraceBundle]( resetCrossingType = crossingParams.resetCrossingType) context.traceNodes(domain.element.tileId) := traceCrossingNode := domain.element.traceNode val traceCoreCrossingNode = BundleBridgeBlockDuringReset[TraceCoreInterface]( resetCrossingType = crossingParams.resetCrossingType) context.traceCoreNodes(domain.element.tileId) :*= traceCoreCrossingNode := domain.element.traceCoreNode } } case class CloneTileAttachParams( sourceTileId: Int, cloneParams: CanAttachTile ) extends CanAttachTile { type TileType = cloneParams.TileType type TileContextType = cloneParams.TileContextType def tileParams = cloneParams.tileParams def crossingParams = cloneParams.crossingParams override def instantiate(allTileParams: Seq[TileParams], instantiatedTiles: SortedMap[Int, TilePRCIDomain[_]])(implicit p: Parameters): TilePRCIDomain[TileType] = { require(instantiatedTiles.contains(sourceTileId)) val clockSinkParams = tileParams.clockSinkParams.copy(name = Some(tileParams.uniqueName)) val tile_prci_domain = CloneLazyModule( new TilePRCIDomain[TileType](clockSinkParams, crossingParams) { self => val element = self.element_reset_domain { LazyModule(tileParams.instantiate(crossingParams, PriorityMuxHartIdFromSeq(allTileParams))) } }, instantiatedTiles(sourceTileId).asInstanceOf[TilePRCIDomain[TileType]] ) tile_prci_domain } } File ClockGroup.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.prci import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.resources.FixedClockResource case class ClockGroupingNode(groupName: String)(implicit valName: ValName) extends MixedNexusNode(ClockGroupImp, ClockImp)( dFn = { _ => ClockSourceParameters() }, uFn = { seq => ClockGroupSinkParameters(name = groupName, members = seq) }) { override def circuitIdentity = outputs.size == 1 } class ClockGroup(groupName: String)(implicit p: Parameters) extends LazyModule { val node = ClockGroupingNode(groupName) lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { val (in, _) = node.in(0) val (out, _) = node.out.unzip require (node.in.size == 1) require (in.member.size == out.size) (in.member.data zip out) foreach { case (i, o) => o := i } } } object ClockGroup { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ClockGroup(valName.name)).node } case class ClockGroupAggregateNode(groupName: String)(implicit valName: ValName) extends NexusNode(ClockGroupImp)( dFn = { _ => ClockGroupSourceParameters() }, uFn = { seq => ClockGroupSinkParameters(name = groupName, members = seq.flatMap(_.members))}) { override def circuitIdentity = outputs.size == 1 } class ClockGroupAggregator(groupName: String)(implicit p: Parameters) extends LazyModule { val node = ClockGroupAggregateNode(groupName) override lazy val desiredName = s"ClockGroupAggregator_$groupName" lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { val (in, _) = node.in.unzip val (out, _) = node.out.unzip val outputs = out.flatMap(_.member.data) require (node.in.size == 1, s"Aggregator for groupName: ${groupName} had ${node.in.size} inward edges instead of 1") require (in.head.member.size == outputs.size) in.head.member.data.zip(outputs).foreach { case (i, o) => o := i } } } object ClockGroupAggregator { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ClockGroupAggregator(valName.name)).node } class SimpleClockGroupSource(numSources: Int = 1)(implicit p: Parameters) extends LazyModule { val node = ClockGroupSourceNode(List.fill(numSources) { ClockGroupSourceParameters() }) lazy val module = new Impl class Impl extends LazyModuleImp(this) { val (out, _) = node.out.unzip out.map { out: ClockGroupBundle => out.member.data.foreach { o => o.clock := clock; o.reset := reset } } } } object SimpleClockGroupSource { def apply(num: Int = 1)(implicit p: Parameters, valName: ValName) = LazyModule(new SimpleClockGroupSource(num)).node } case class FixedClockBroadcastNode(fixedClockOpt: Option[ClockParameters])(implicit valName: ValName) extends NexusNode(ClockImp)( dFn = { seq => fixedClockOpt.map(_ => ClockSourceParameters(give = fixedClockOpt)).orElse(seq.headOption).getOrElse(ClockSourceParameters()) }, uFn = { seq => fixedClockOpt.map(_ => ClockSinkParameters(take = fixedClockOpt)).orElse(seq.headOption).getOrElse(ClockSinkParameters()) }, inputRequiresOutput = false) { def fixedClockResources(name: String, prefix: String = "soc/"): Seq[Option[FixedClockResource]] = Seq(fixedClockOpt.map(t => new FixedClockResource(name, t.freqMHz, prefix))) } class FixedClockBroadcast(fixedClockOpt: Option[ClockParameters])(implicit p: Parameters) extends LazyModule { val node = new FixedClockBroadcastNode(fixedClockOpt) { override def circuitIdentity = outputs.size == 1 } lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { val (in, _) = node.in(0) val (out, _) = node.out.unzip override def desiredName = s"FixedClockBroadcast_${out.size}" require (node.in.size == 1, "FixedClockBroadcast can only broadcast a single clock") out.foreach { _ := in } } } object FixedClockBroadcast { def apply(fixedClockOpt: Option[ClockParameters] = None)(implicit p: Parameters, valName: ValName) = LazyModule(new FixedClockBroadcast(fixedClockOpt)).node } case class PRCIClockGroupNode()(implicit valName: ValName) extends NexusNode(ClockGroupImp)( dFn = { _ => ClockGroupSourceParameters() }, uFn = { _ => ClockGroupSinkParameters("prci", Nil) }, outputRequiresInput = false) File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } }

module TilePRCIDomain_7( // @[ClockDomain.scala:14:9] output auto_intsink_out_1_0, // @[LazyModuleImp.scala:107:25] input auto_intsink_in_sync_0, // @[LazyModuleImp.scala:107:25] output auto_element_reset_domain_rockettile_trace_source_out_insns_0_valid, // @[LazyModuleImp.scala:107:25] output [39:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_iaddr, // @[LazyModuleImp.scala:107:25] output [31:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_insn, // @[LazyModuleImp.scala:107:25] output [2:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_priv, // @[LazyModuleImp.scala:107:25] output auto_element_reset_domain_rockettile_trace_source_out_insns_0_exception, // @[LazyModuleImp.scala:107:25] output auto_element_reset_domain_rockettile_trace_source_out_insns_0_interrupt, // @[LazyModuleImp.scala:107:25] output [63:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_cause, // @[LazyModuleImp.scala:107:25] output [39:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_tval, // @[LazyModuleImp.scala:107:25] output [63:0] auto_element_reset_domain_rockettile_trace_source_out_time, // @[LazyModuleImp.scala:107:25] input [2:0] auto_element_reset_domain_rockettile_hartid_in, // @[LazyModuleImp.scala:107:25] input auto_int_in_clock_xing_in_2_sync_0, // @[LazyModuleImp.scala:107:25] input auto_int_in_clock_xing_in_1_sync_0, // @[LazyModuleImp.scala:107:25] input auto_int_in_clock_xing_in_0_sync_0, // @[LazyModuleImp.scala:107:25] input auto_int_in_clock_xing_in_0_sync_1, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_master_clock_xing_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_master_clock_xing_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_tl_master_clock_xing_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_tl_master_clock_xing_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_tl_master_clock_xing_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_tl_master_clock_xing_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_tl_master_clock_xing_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_b_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_master_clock_xing_out_b_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_tl_master_clock_xing_out_b_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_tl_master_clock_xing_out_b_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_tl_master_clock_xing_out_b_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_tl_master_clock_xing_out_b_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_tl_master_clock_xing_out_b_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_tl_master_clock_xing_out_b_bits_data, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_b_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_c_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_master_clock_xing_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_master_clock_xing_out_c_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_tl_master_clock_xing_out_c_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_tl_master_clock_xing_out_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_tl_master_clock_xing_out_c_bits_address, // @[LazyModuleImp.scala:107:25] output [63:0] auto_tl_master_clock_xing_out_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_master_clock_xing_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_tl_master_clock_xing_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_tl_master_clock_xing_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_tl_master_clock_xing_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_master_clock_xing_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_tl_master_clock_xing_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_e_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_e_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_master_clock_xing_out_e_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_tap_clock_in_clock, // @[LazyModuleImp.scala:107:25] input auto_tap_clock_in_reset // @[LazyModuleImp.scala:107:25] ); wire clockNode_auto_anon_in_reset; // @[ClockGroup.scala:104:9] wire clockNode_auto_anon_in_clock; // @[ClockGroup.scala:104:9] wire element_reset_domain_auto_clock_in_reset; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_clock_in_clock; // @[ClockDomain.scala:14:9] wire auto_intsink_in_sync_0_0 = auto_intsink_in_sync_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_element_reset_domain_rockettile_hartid_in_0 = auto_element_reset_domain_rockettile_hartid_in; // @[ClockDomain.scala:14:9] wire auto_int_in_clock_xing_in_2_sync_0_0 = auto_int_in_clock_xing_in_2_sync_0; // @[ClockDomain.scala:14:9] wire auto_int_in_clock_xing_in_1_sync_0_0 = auto_int_in_clock_xing_in_1_sync_0; // @[ClockDomain.scala:14:9] wire auto_int_in_clock_xing_in_0_sync_0_0 = auto_int_in_clock_xing_in_0_sync_0; // @[ClockDomain.scala:14:9] wire auto_int_in_clock_xing_in_0_sync_1_0 = auto_int_in_clock_xing_in_0_sync_1; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_a_ready_0 = auto_tl_master_clock_xing_out_a_ready; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_b_valid_0 = auto_tl_master_clock_xing_out_b_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_b_bits_opcode_0 = auto_tl_master_clock_xing_out_b_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_tl_master_clock_xing_out_b_bits_param_0 = auto_tl_master_clock_xing_out_b_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] auto_tl_master_clock_xing_out_b_bits_size_0 = auto_tl_master_clock_xing_out_b_bits_size; // @[ClockDomain.scala:14:9] wire [1:0] auto_tl_master_clock_xing_out_b_bits_source_0 = auto_tl_master_clock_xing_out_b_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] auto_tl_master_clock_xing_out_b_bits_address_0 = auto_tl_master_clock_xing_out_b_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] auto_tl_master_clock_xing_out_b_bits_mask_0 = auto_tl_master_clock_xing_out_b_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] auto_tl_master_clock_xing_out_b_bits_data_0 = auto_tl_master_clock_xing_out_b_bits_data; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_b_bits_corrupt_0 = auto_tl_master_clock_xing_out_b_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_c_ready_0 = auto_tl_master_clock_xing_out_c_ready; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_d_valid_0 = auto_tl_master_clock_xing_out_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_d_bits_opcode_0 = auto_tl_master_clock_xing_out_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_tl_master_clock_xing_out_d_bits_param_0 = auto_tl_master_clock_xing_out_d_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] auto_tl_master_clock_xing_out_d_bits_size_0 = auto_tl_master_clock_xing_out_d_bits_size; // @[ClockDomain.scala:14:9] wire [1:0] auto_tl_master_clock_xing_out_d_bits_source_0 = auto_tl_master_clock_xing_out_d_bits_source; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_d_bits_sink_0 = auto_tl_master_clock_xing_out_d_bits_sink; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_d_bits_denied_0 = auto_tl_master_clock_xing_out_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] auto_tl_master_clock_xing_out_d_bits_data_0 = auto_tl_master_clock_xing_out_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_d_bits_corrupt_0 = auto_tl_master_clock_xing_out_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_e_ready_0 = auto_tl_master_clock_xing_out_e_ready; // @[ClockDomain.scala:14:9] wire auto_tap_clock_in_clock_0 = auto_tap_clock_in_clock; // @[ClockDomain.scala:14:9] wire auto_tap_clock_in_reset_0 = auto_tap_clock_in_reset; // @[ClockDomain.scala:14:9] wire [31:0] auto_element_reset_domain_rockettile_trace_core_source_out_group_0_iaddr = 32'h0; // @[ClockDomain.scala:14:9] wire [31:0] auto_element_reset_domain_rockettile_trace_core_source_out_tval = 32'h0; // @[ClockDomain.scala:14:9] wire [31:0] auto_element_reset_domain_rockettile_trace_core_source_out_cause = 32'h0; // @[ClockDomain.scala:14:9] wire [31:0] element_reset_domain_auto_rockettile_trace_core_source_out_group_0_iaddr = 32'h0; // @[ClockDomain.scala:14:9] wire [31:0] element_reset_domain_auto_rockettile_trace_core_source_out_tval = 32'h0; // @[ClockDomain.scala:14:9] wire [31:0] element_reset_domain_auto_rockettile_trace_core_source_out_cause = 32'h0; // @[ClockDomain.scala:14:9] wire [3:0] auto_element_reset_domain_rockettile_trace_core_source_out_group_0_itype = 4'h0; // @[ClockDomain.scala:14:9] wire [3:0] auto_element_reset_domain_rockettile_trace_core_source_out_priv = 4'h0; // @[ClockDomain.scala:14:9] wire [3:0] element_reset_domain_auto_rockettile_trace_core_source_out_group_0_itype = 4'h0; // @[ClockDomain.scala:14:9] wire [3:0] element_reset_domain_auto_rockettile_trace_core_source_out_priv = 4'h0; // @[ClockDomain.scala:14:9] wire [31:0] auto_element_reset_domain_rockettile_reset_vector_in = 32'h10000; // @[ClockDomain.scala:14:9] wire [31:0] element_reset_domain_auto_rockettile_reset_vector_in = 32'h10000; // @[ClockDomain.scala:14:9] wire auto_intsink_out_2_0 = 1'h0; // @[ClockDomain.scala:14:9] wire auto_intsink_out_0_0 = 1'h0; // @[ClockDomain.scala:14:9] wire auto_element_reset_domain_rockettile_trace_core_source_out_group_0_iretire = 1'h0; // @[ClockDomain.scala:14:9] wire auto_element_reset_domain_rockettile_trace_core_source_out_group_0_ilastsize = 1'h0; // @[ClockDomain.scala:14:9] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire element_reset_domain_auto_rockettile_buffer_out_a_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_c_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_cease_out_0 = 1'h0; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_halt_out_0 = 1'h0; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_trace_core_source_out_group_0_iretire = 1'h0; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_trace_core_source_out_group_0_ilastsize = 1'h0; // @[ClockDomain.scala:14:9] wire element_reset_domain__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire clockNode_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire clockNode_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire clockNode__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire intOutClockXingOut_sync_0 = 1'h0; // @[MixedNode.scala:542:17] wire intOutClockXingIn_sync_0 = 1'h0; // @[MixedNode.scala:551:17] wire intOutClockXingOut_1_sync_0 = 1'h0; // @[MixedNode.scala:542:17] wire intOutClockXingIn_1_sync_0 = 1'h0; // @[MixedNode.scala:551:17] wire intOutClockXingOut_4_sync_0 = 1'h0; // @[MixedNode.scala:542:17] wire intOutClockXingIn_4_sync_0 = 1'h0; // @[MixedNode.scala:551:17] wire intOutClockXingOut_5_sync_0 = 1'h0; // @[MixedNode.scala:542:17] wire intOutClockXingIn_5_sync_0 = 1'h0; // @[MixedNode.scala:551:17] wire element_reset_domain_auto_rockettile_trace_source_out_insns_0_valid; // @[ClockDomain.scala:14:9] wire [39:0] element_reset_domain_auto_rockettile_trace_source_out_insns_0_iaddr; // @[ClockDomain.scala:14:9] wire [31:0] element_reset_domain_auto_rockettile_trace_source_out_insns_0_insn; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_trace_source_out_insns_0_priv; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_trace_source_out_insns_0_exception; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_trace_source_out_insns_0_interrupt; // @[ClockDomain.scala:14:9] wire [63:0] element_reset_domain_auto_rockettile_trace_source_out_insns_0_cause; // @[ClockDomain.scala:14:9] wire [39:0] element_reset_domain_auto_rockettile_trace_source_out_insns_0_tval; // @[ClockDomain.scala:14:9] wire [63:0] element_reset_domain_auto_rockettile_trace_source_out_time; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_hartid_in = auto_element_reset_domain_rockettile_hartid_in_0; // @[ClockDomain.scala:14:9] wire intInClockXingIn_2_sync_0 = auto_int_in_clock_xing_in_2_sync_0_0; // @[ClockDomain.scala:14:9] wire intInClockXingIn_1_sync_0 = auto_int_in_clock_xing_in_1_sync_0_0; // @[ClockDomain.scala:14:9] wire intInClockXingIn_sync_0 = auto_int_in_clock_xing_in_0_sync_0_0; // @[ClockDomain.scala:14:9] wire intInClockXingIn_sync_1 = auto_int_in_clock_xing_in_0_sync_1_0; // @[ClockDomain.scala:14:9] wire tlMasterClockXingOut_a_ready = auto_tl_master_clock_xing_out_a_ready_0; // @[ClockDomain.scala:14:9] wire tlMasterClockXingOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] tlMasterClockXingOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] tlMasterClockXingOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] tlMasterClockXingOut_a_bits_size; // @[MixedNode.scala:542:17] wire [1:0] tlMasterClockXingOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] tlMasterClockXingOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] tlMasterClockXingOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] tlMasterClockXingOut_a_bits_data; // @[MixedNode.scala:542:17] wire tlMasterClockXingOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire tlMasterClockXingOut_b_ready; // @[MixedNode.scala:542:17] wire tlMasterClockXingOut_b_valid = auto_tl_master_clock_xing_out_b_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] tlMasterClockXingOut_b_bits_opcode = auto_tl_master_clock_xing_out_b_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] tlMasterClockXingOut_b_bits_param = auto_tl_master_clock_xing_out_b_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] tlMasterClockXingOut_b_bits_size = auto_tl_master_clock_xing_out_b_bits_size_0; // @[ClockDomain.scala:14:9] wire [1:0] tlMasterClockXingOut_b_bits_source = auto_tl_master_clock_xing_out_b_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] tlMasterClockXingOut_b_bits_address = auto_tl_master_clock_xing_out_b_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] tlMasterClockXingOut_b_bits_mask = auto_tl_master_clock_xing_out_b_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] tlMasterClockXingOut_b_bits_data = auto_tl_master_clock_xing_out_b_bits_data_0; // @[ClockDomain.scala:14:9] wire tlMasterClockXingOut_b_bits_corrupt = auto_tl_master_clock_xing_out_b_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire tlMasterClockXingOut_c_ready = auto_tl_master_clock_xing_out_c_ready_0; // @[ClockDomain.scala:14:9] wire tlMasterClockXingOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] tlMasterClockXingOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] tlMasterClockXingOut_c_bits_param; // @[MixedNode.scala:542:17] wire [3:0] tlMasterClockXingOut_c_bits_size; // @[MixedNode.scala:542:17] wire [1:0] tlMasterClockXingOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] tlMasterClockXingOut_c_bits_address; // @[MixedNode.scala:542:17] wire [63:0] tlMasterClockXingOut_c_bits_data; // @[MixedNode.scala:542:17] wire tlMasterClockXingOut_c_bits_corrupt; // @[MixedNode.scala:542:17] wire tlMasterClockXingOut_d_ready; // @[MixedNode.scala:542:17] wire tlMasterClockXingOut_d_valid = auto_tl_master_clock_xing_out_d_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] tlMasterClockXingOut_d_bits_opcode = auto_tl_master_clock_xing_out_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] tlMasterClockXingOut_d_bits_param = auto_tl_master_clock_xing_out_d_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] tlMasterClockXingOut_d_bits_size = auto_tl_master_clock_xing_out_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [1:0] tlMasterClockXingOut_d_bits_source = auto_tl_master_clock_xing_out_d_bits_source_0; // @[ClockDomain.scala:14:9] wire [2:0] tlMasterClockXingOut_d_bits_sink = auto_tl_master_clock_xing_out_d_bits_sink_0; // @[ClockDomain.scala:14:9] wire tlMasterClockXingOut_d_bits_denied = auto_tl_master_clock_xing_out_d_bits_denied_0; // @[ClockDomain.scala:14:9] wire [63:0] tlMasterClockXingOut_d_bits_data = auto_tl_master_clock_xing_out_d_bits_data_0; // @[ClockDomain.scala:14:9] wire tlMasterClockXingOut_d_bits_corrupt = auto_tl_master_clock_xing_out_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire tlMasterClockXingOut_e_ready = auto_tl_master_clock_xing_out_e_ready_0; // @[ClockDomain.scala:14:9] wire tlMasterClockXingOut_e_valid; // @[MixedNode.scala:542:17] wire [2:0] tlMasterClockXingOut_e_bits_sink; // @[MixedNode.scala:542:17] wire tapClockNodeIn_clock = auto_tap_clock_in_clock_0; // @[ClockDomain.scala:14:9] wire tapClockNodeIn_reset = auto_tap_clock_in_reset_0; // @[ClockDomain.scala:14:9] wire auto_intsink_out_1_0_0; // @[ClockDomain.scala:14:9] wire auto_element_reset_domain_rockettile_trace_source_out_insns_0_valid_0; // @[ClockDomain.scala:14:9] wire [39:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_iaddr_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_insn_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_priv_0; // @[ClockDomain.scala:14:9] wire auto_element_reset_domain_rockettile_trace_source_out_insns_0_exception_0; // @[ClockDomain.scala:14:9] wire auto_element_reset_domain_rockettile_trace_source_out_insns_0_interrupt_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_cause_0; // @[ClockDomain.scala:14:9] wire [39:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_tval_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_element_reset_domain_rockettile_trace_source_out_time_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_tl_master_clock_xing_out_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_tl_master_clock_xing_out_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_tl_master_clock_xing_out_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_tl_master_clock_xing_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_tl_master_clock_xing_out_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_b_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_c_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_c_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_tl_master_clock_xing_out_c_bits_size_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_tl_master_clock_xing_out_c_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_tl_master_clock_xing_out_c_bits_address_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_tl_master_clock_xing_out_c_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_c_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_c_valid_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_d_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_e_bits_sink_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_e_valid_0; // @[ClockDomain.scala:14:9] wire childClock; // @[LazyModuleImp.scala:155:31] wire childReset; // @[LazyModuleImp.scala:158:31] assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_valid_0 = element_reset_domain_auto_rockettile_trace_source_out_insns_0_valid; // @[ClockDomain.scala:14:9] assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_iaddr_0 = element_reset_domain_auto_rockettile_trace_source_out_insns_0_iaddr; // @[ClockDomain.scala:14:9] assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_insn_0 = element_reset_domain_auto_rockettile_trace_source_out_insns_0_insn; // @[ClockDomain.scala:14:9] assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_priv_0 = element_reset_domain_auto_rockettile_trace_source_out_insns_0_priv; // @[ClockDomain.scala:14:9] assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_exception_0 = element_reset_domain_auto_rockettile_trace_source_out_insns_0_exception; // @[ClockDomain.scala:14:9] assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_interrupt_0 = element_reset_domain_auto_rockettile_trace_source_out_insns_0_interrupt; // @[ClockDomain.scala:14:9] assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_cause_0 = element_reset_domain_auto_rockettile_trace_source_out_insns_0_cause; // @[ClockDomain.scala:14:9] assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_tval_0 = element_reset_domain_auto_rockettile_trace_source_out_insns_0_tval; // @[ClockDomain.scala:14:9] assign auto_element_reset_domain_rockettile_trace_source_out_time_0 = element_reset_domain_auto_rockettile_trace_source_out_time; // @[ClockDomain.scala:14:9] wire clockNode_auto_anon_out_clock; // @[ClockGroup.scala:104:9] wire element_reset_domain_clockNodeIn_clock = element_reset_domain_auto_clock_in_clock; // @[ClockDomain.scala:14:9] wire clockNode_auto_anon_out_reset; // @[ClockGroup.scala:104:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_a_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] element_reset_domain_auto_rockettile_buffer_out_a_bits_size; // @[ClockDomain.scala:14:9] wire [1:0] element_reset_domain_auto_rockettile_buffer_out_a_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] element_reset_domain_auto_rockettile_buffer_out_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] element_reset_domain_auto_rockettile_buffer_out_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] element_reset_domain_auto_rockettile_buffer_out_a_bits_data; // @[ClockDomain.scala:14:9] wire element_reset_domain_clockNodeIn_reset = element_reset_domain_auto_clock_in_reset; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_a_ready; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_b_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] element_reset_domain_auto_rockettile_buffer_out_b_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] element_reset_domain_auto_rockettile_buffer_out_b_bits_size; // @[ClockDomain.scala:14:9] wire [1:0] element_reset_domain_auto_rockettile_buffer_out_b_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] element_reset_domain_auto_rockettile_buffer_out_b_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] element_reset_domain_auto_rockettile_buffer_out_b_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] element_reset_domain_auto_rockettile_buffer_out_b_bits_data; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_b_bits_corrupt; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_b_ready; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_b_valid; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_c_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_c_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] element_reset_domain_auto_rockettile_buffer_out_c_bits_size; // @[ClockDomain.scala:14:9] wire [1:0] element_reset_domain_auto_rockettile_buffer_out_c_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] element_reset_domain_auto_rockettile_buffer_out_c_bits_address; // @[ClockDomain.scala:14:9] wire [63:0] element_reset_domain_auto_rockettile_buffer_out_c_bits_data; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_c_ready; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_c_valid; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] element_reset_domain_auto_rockettile_buffer_out_d_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] element_reset_domain_auto_rockettile_buffer_out_d_bits_size; // @[ClockDomain.scala:14:9] wire [1:0] element_reset_domain_auto_rockettile_buffer_out_d_bits_source; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_d_bits_sink; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] element_reset_domain_auto_rockettile_buffer_out_d_bits_data; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_d_ready; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_e_bits_sink; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_e_ready; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_e_valid; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_wfi_out_0; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_int_local_in_3_0; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_int_local_in_2_0; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_int_local_in_1_0; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_int_local_in_1_1; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_int_local_in_0_0; // @[ClockDomain.scala:14:9] wire element_reset_domain_childClock; // @[LazyModuleImp.scala:155:31] wire element_reset_domain_childReset; // @[LazyModuleImp.scala:158:31] assign element_reset_domain_childClock = element_reset_domain_clockNodeIn_clock; // @[MixedNode.scala:551:17] assign element_reset_domain_childReset = element_reset_domain_clockNodeIn_reset; // @[MixedNode.scala:551:17] wire tapClockNodeOut_clock; // @[MixedNode.scala:542:17] wire clockNode_anonIn_clock = clockNode_auto_anon_in_clock; // @[ClockGroup.scala:104:9] wire tapClockNodeOut_reset; // @[MixedNode.scala:542:17] wire clockNode_anonOut_clock; // @[MixedNode.scala:542:17] wire clockNode_anonIn_reset = clockNode_auto_anon_in_reset; // @[ClockGroup.scala:104:9] assign element_reset_domain_auto_clock_in_clock = clockNode_auto_anon_out_clock; // @[ClockGroup.scala:104:9] wire clockNode_anonOut_reset; // @[MixedNode.scala:542:17] assign element_reset_domain_auto_clock_in_reset = clockNode_auto_anon_out_reset; // @[ClockGroup.scala:104:9] assign clockNode_auto_anon_out_clock = clockNode_anonOut_clock; // @[ClockGroup.scala:104:9] assign clockNode_auto_anon_out_reset = clockNode_anonOut_reset; // @[ClockGroup.scala:104:9] assign clockNode_anonOut_clock = clockNode_anonIn_clock; // @[MixedNode.scala:542:17, :551:17] assign clockNode_anonOut_reset = clockNode_anonIn_reset; // @[MixedNode.scala:542:17, :551:17] assign clockNode_auto_anon_in_clock = tapClockNodeOut_clock; // @[ClockGroup.scala:104:9] assign clockNode_auto_anon_in_reset = tapClockNodeOut_reset; // @[ClockGroup.scala:104:9] assign childClock = tapClockNodeIn_clock; // @[MixedNode.scala:551:17] assign tapClockNodeOut_clock = tapClockNodeIn_clock; // @[MixedNode.scala:542:17, :551:17] assign childReset = tapClockNodeIn_reset; // @[MixedNode.scala:551:17] assign tapClockNodeOut_reset = tapClockNodeIn_reset; // @[MixedNode.scala:542:17, :551:17] wire tlMasterClockXingIn_a_ready = tlMasterClockXingOut_a_ready; // @[MixedNode.scala:542:17, :551:17] wire tlMasterClockXingIn_a_valid; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_a_valid_0 = tlMasterClockXingOut_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] tlMasterClockXingIn_a_bits_opcode; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_a_bits_opcode_0 = tlMasterClockXingOut_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] tlMasterClockXingIn_a_bits_param; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_a_bits_param_0 = tlMasterClockXingOut_a_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] tlMasterClockXingIn_a_bits_size; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_a_bits_size_0 = tlMasterClockXingOut_a_bits_size; // @[ClockDomain.scala:14:9] wire [1:0] tlMasterClockXingIn_a_bits_source; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_a_bits_source_0 = tlMasterClockXingOut_a_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] tlMasterClockXingIn_a_bits_address; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_a_bits_address_0 = tlMasterClockXingOut_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] tlMasterClockXingIn_a_bits_mask; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_a_bits_mask_0 = tlMasterClockXingOut_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] tlMasterClockXingIn_a_bits_data; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_a_bits_data_0 = tlMasterClockXingOut_a_bits_data; // @[ClockDomain.scala:14:9] wire tlMasterClockXingIn_a_bits_corrupt; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_a_bits_corrupt_0 = tlMasterClockXingOut_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire tlMasterClockXingIn_b_ready; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_b_ready_0 = tlMasterClockXingOut_b_ready; // @[ClockDomain.scala:14:9] wire tlMasterClockXingIn_b_valid = tlMasterClockXingOut_b_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] tlMasterClockXingIn_b_bits_opcode = tlMasterClockXingOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] tlMasterClockXingIn_b_bits_param = tlMasterClockXingOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] tlMasterClockXingIn_b_bits_size = tlMasterClockXingOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] tlMasterClockXingIn_b_bits_source = tlMasterClockXingOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] tlMasterClockXingIn_b_bits_address = tlMasterClockXingOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [7:0] tlMasterClockXingIn_b_bits_mask = tlMasterClockXingOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire [63:0] tlMasterClockXingIn_b_bits_data = tlMasterClockXingOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17] wire tlMasterClockXingIn_b_bits_corrupt = tlMasterClockXingOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire tlMasterClockXingIn_c_ready = tlMasterClockXingOut_c_ready; // @[MixedNode.scala:542:17, :551:17] wire tlMasterClockXingIn_c_valid; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_c_valid_0 = tlMasterClockXingOut_c_valid; // @[ClockDomain.scala:14:9] wire [2:0] tlMasterClockXingIn_c_bits_opcode; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_c_bits_opcode_0 = tlMasterClockXingOut_c_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] tlMasterClockXingIn_c_bits_param; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_c_bits_param_0 = tlMasterClockXingOut_c_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] tlMasterClockXingIn_c_bits_size; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_c_bits_size_0 = tlMasterClockXingOut_c_bits_size; // @[ClockDomain.scala:14:9] wire [1:0] tlMasterClockXingIn_c_bits_source; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_c_bits_source_0 = tlMasterClockXingOut_c_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] tlMasterClockXingIn_c_bits_address; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_c_bits_address_0 = tlMasterClockXingOut_c_bits_address; // @[ClockDomain.scala:14:9] wire [63:0] tlMasterClockXingIn_c_bits_data; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_c_bits_data_0 = tlMasterClockXingOut_c_bits_data; // @[ClockDomain.scala:14:9] wire tlMasterClockXingIn_c_bits_corrupt; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_c_bits_corrupt_0 = tlMasterClockXingOut_c_bits_corrupt; // @[ClockDomain.scala:14:9] wire tlMasterClockXingIn_d_ready; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_d_ready_0 = tlMasterClockXingOut_d_ready; // @[ClockDomain.scala:14:9] wire tlMasterClockXingIn_d_valid = tlMasterClockXingOut_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] tlMasterClockXingIn_d_bits_opcode = tlMasterClockXingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] tlMasterClockXingIn_d_bits_param = tlMasterClockXingOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] tlMasterClockXingIn_d_bits_size = tlMasterClockXingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] tlMasterClockXingIn_d_bits_source = tlMasterClockXingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] tlMasterClockXingIn_d_bits_sink = tlMasterClockXingOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire tlMasterClockXingIn_d_bits_denied = tlMasterClockXingOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] tlMasterClockXingIn_d_bits_data = tlMasterClockXingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire tlMasterClockXingIn_d_bits_corrupt = tlMasterClockXingOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire tlMasterClockXingIn_e_ready = tlMasterClockXingOut_e_ready; // @[MixedNode.scala:542:17, :551:17] wire tlMasterClockXingIn_e_valid; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_e_valid_0 = tlMasterClockXingOut_e_valid; // @[ClockDomain.scala:14:9] wire [2:0] tlMasterClockXingIn_e_bits_sink; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_e_bits_sink_0 = tlMasterClockXingOut_e_bits_sink; // @[ClockDomain.scala:14:9] assign tlMasterClockXingOut_a_valid = tlMasterClockXingIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_a_bits_opcode = tlMasterClockXingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_a_bits_param = tlMasterClockXingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_a_bits_size = tlMasterClockXingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_a_bits_source = tlMasterClockXingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_a_bits_address = tlMasterClockXingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_a_bits_mask = tlMasterClockXingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_a_bits_data = tlMasterClockXingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_a_bits_corrupt = tlMasterClockXingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_b_ready = tlMasterClockXingIn_b_ready; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_c_valid = tlMasterClockXingIn_c_valid; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_c_bits_opcode = tlMasterClockXingIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_c_bits_param = tlMasterClockXingIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_c_bits_size = tlMasterClockXingIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_c_bits_source = tlMasterClockXingIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_c_bits_address = tlMasterClockXingIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_c_bits_data = tlMasterClockXingIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_c_bits_corrupt = tlMasterClockXingIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_d_ready = tlMasterClockXingIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_e_valid = tlMasterClockXingIn_e_valid; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_e_bits_sink = tlMasterClockXingIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire intInClockXingOut_sync_0; // @[MixedNode.scala:542:17] wire intInClockXingOut_sync_1; // @[MixedNode.scala:542:17] assign intInClockXingOut_sync_0 = intInClockXingIn_sync_0; // @[MixedNode.scala:542:17, :551:17] assign intInClockXingOut_sync_1 = intInClockXingIn_sync_1; // @[MixedNode.scala:542:17, :551:17] wire intInClockXingOut_1_sync_0; // @[MixedNode.scala:542:17] assign intInClockXingOut_1_sync_0 = intInClockXingIn_1_sync_0; // @[MixedNode.scala:542:17, :551:17] wire intInClockXingOut_2_sync_0; // @[MixedNode.scala:542:17] assign intInClockXingOut_2_sync_0 = intInClockXingIn_2_sync_0; // @[MixedNode.scala:542:17, :551:17] wire intOutClockXingIn_2_sync_0; // @[MixedNode.scala:551:17] wire intOutClockXingOut_2_sync_0; // @[MixedNode.scala:542:17] wire intOutClockXingOut_3_sync_0; // @[MixedNode.scala:542:17] assign intOutClockXingOut_2_sync_0 = intOutClockXingIn_2_sync_0; // @[MixedNode.scala:542:17, :551:17] wire intOutClockXingIn_3_sync_0; // @[MixedNode.scala:551:17] assign intOutClockXingIn_2_sync_0 = intOutClockXingOut_3_sync_0; // @[MixedNode.scala:542:17, :551:17] assign intOutClockXingOut_3_sync_0 = intOutClockXingIn_3_sync_0; // @[MixedNode.scala:542:17, :551:17] RocketTile_7 element_reset_domain_rockettile ( // @[HasTiles.scala:164:59] .clock (element_reset_domain_childClock), // @[LazyModuleImp.scala:155:31] .reset (element_reset_domain_childReset), // @[LazyModuleImp.scala:158:31] .auto_buffer_out_a_ready (element_reset_domain_auto_rockettile_buffer_out_a_ready), // @[ClockDomain.scala:14:9] .auto_buffer_out_a_valid (element_reset_domain_auto_rockettile_buffer_out_a_valid), .auto_buffer_out_a_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_a_bits_opcode), .auto_buffer_out_a_bits_param (element_reset_domain_auto_rockettile_buffer_out_a_bits_param), .auto_buffer_out_a_bits_size (element_reset_domain_auto_rockettile_buffer_out_a_bits_size), .auto_buffer_out_a_bits_source (element_reset_domain_auto_rockettile_buffer_out_a_bits_source), .auto_buffer_out_a_bits_address (element_reset_domain_auto_rockettile_buffer_out_a_bits_address), .auto_buffer_out_a_bits_mask (element_reset_domain_auto_rockettile_buffer_out_a_bits_mask), .auto_buffer_out_a_bits_data (element_reset_domain_auto_rockettile_buffer_out_a_bits_data), .auto_buffer_out_b_ready (element_reset_domain_auto_rockettile_buffer_out_b_ready), .auto_buffer_out_b_valid (element_reset_domain_auto_rockettile_buffer_out_b_valid), // @[ClockDomain.scala:14:9] .auto_buffer_out_b_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_b_bits_opcode), // @[ClockDomain.scala:14:9] .auto_buffer_out_b_bits_param (element_reset_domain_auto_rockettile_buffer_out_b_bits_param), // @[ClockDomain.scala:14:9] .auto_buffer_out_b_bits_size (element_reset_domain_auto_rockettile_buffer_out_b_bits_size), // @[ClockDomain.scala:14:9] .auto_buffer_out_b_bits_source (element_reset_domain_auto_rockettile_buffer_out_b_bits_source), // @[ClockDomain.scala:14:9] .auto_buffer_out_b_bits_address (element_reset_domain_auto_rockettile_buffer_out_b_bits_address), // @[ClockDomain.scala:14:9] .auto_buffer_out_b_bits_mask (element_reset_domain_auto_rockettile_buffer_out_b_bits_mask), // @[ClockDomain.scala:14:9] .auto_buffer_out_b_bits_data (element_reset_domain_auto_rockettile_buffer_out_b_bits_data), // @[ClockDomain.scala:14:9] .auto_buffer_out_b_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_b_bits_corrupt), // @[ClockDomain.scala:14:9] .auto_buffer_out_c_ready (element_reset_domain_auto_rockettile_buffer_out_c_ready), // @[ClockDomain.scala:14:9] .auto_buffer_out_c_valid (element_reset_domain_auto_rockettile_buffer_out_c_valid), .auto_buffer_out_c_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_c_bits_opcode), .auto_buffer_out_c_bits_param (element_reset_domain_auto_rockettile_buffer_out_c_bits_param), .auto_buffer_out_c_bits_size (element_reset_domain_auto_rockettile_buffer_out_c_bits_size), .auto_buffer_out_c_bits_source (element_reset_domain_auto_rockettile_buffer_out_c_bits_source), .auto_buffer_out_c_bits_address (element_reset_domain_auto_rockettile_buffer_out_c_bits_address), .auto_buffer_out_c_bits_data (element_reset_domain_auto_rockettile_buffer_out_c_bits_data), .auto_buffer_out_d_ready (element_reset_domain_auto_rockettile_buffer_out_d_ready), .auto_buffer_out_d_valid (element_reset_domain_auto_rockettile_buffer_out_d_valid), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_d_bits_opcode), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_param (element_reset_domain_auto_rockettile_buffer_out_d_bits_param), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_size (element_reset_domain_auto_rockettile_buffer_out_d_bits_size), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_source (element_reset_domain_auto_rockettile_buffer_out_d_bits_source), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_sink (element_reset_domain_auto_rockettile_buffer_out_d_bits_sink), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_denied (element_reset_domain_auto_rockettile_buffer_out_d_bits_denied), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_data (element_reset_domain_auto_rockettile_buffer_out_d_bits_data), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_d_bits_corrupt), // @[ClockDomain.scala:14:9] .auto_buffer_out_e_ready (element_reset_domain_auto_rockettile_buffer_out_e_ready), // @[ClockDomain.scala:14:9] .auto_buffer_out_e_valid (element_reset_domain_auto_rockettile_buffer_out_e_valid), .auto_buffer_out_e_bits_sink (element_reset_domain_auto_rockettile_buffer_out_e_bits_sink), .auto_wfi_out_0 (element_reset_domain_auto_rockettile_wfi_out_0), .auto_int_local_in_3_0 (element_reset_domain_auto_rockettile_int_local_in_3_0), // @[ClockDomain.scala:14:9] .auto_int_local_in_2_0 (element_reset_domain_auto_rockettile_int_local_in_2_0), // @[ClockDomain.scala:14:9] .auto_int_local_in_1_0 (element_reset_domain_auto_rockettile_int_local_in_1_0), // @[ClockDomain.scala:14:9] .auto_int_local_in_1_1 (element_reset_domain_auto_rockettile_int_local_in_1_1), // @[ClockDomain.scala:14:9] .auto_int_local_in_0_0 (element_reset_domain_auto_rockettile_int_local_in_0_0), // @[ClockDomain.scala:14:9] .auto_trace_source_out_insns_0_valid (element_reset_domain_auto_rockettile_trace_source_out_insns_0_valid), .auto_trace_source_out_insns_0_iaddr (element_reset_domain_auto_rockettile_trace_source_out_insns_0_iaddr), .auto_trace_source_out_insns_0_insn (element_reset_domain_auto_rockettile_trace_source_out_insns_0_insn), .auto_trace_source_out_insns_0_priv (element_reset_domain_auto_rockettile_trace_source_out_insns_0_priv), .auto_trace_source_out_insns_0_exception (element_reset_domain_auto_rockettile_trace_source_out_insns_0_exception), .auto_trace_source_out_insns_0_interrupt (element_reset_domain_auto_rockettile_trace_source_out_insns_0_interrupt), .auto_trace_source_out_insns_0_cause (element_reset_domain_auto_rockettile_trace_source_out_insns_0_cause), .auto_trace_source_out_insns_0_tval (element_reset_domain_auto_rockettile_trace_source_out_insns_0_tval), .auto_trace_source_out_time (element_reset_domain_auto_rockettile_trace_source_out_time), .auto_hartid_in (element_reset_domain_auto_rockettile_hartid_in) // @[ClockDomain.scala:14:9] ); // @[HasTiles.scala:164:59] TLBuffer_a32d64s2k3z4c_15 buffer ( // @[Buffer.scala:75:28] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_a_ready (element_reset_domain_auto_rockettile_buffer_out_a_ready), .auto_in_a_valid (element_reset_domain_auto_rockettile_buffer_out_a_valid), // @[ClockDomain.scala:14:9] .auto_in_a_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_a_bits_opcode), // @[ClockDomain.scala:14:9] .auto_in_a_bits_param (element_reset_domain_auto_rockettile_buffer_out_a_bits_param), // @[ClockDomain.scala:14:9] .auto_in_a_bits_size (element_reset_domain_auto_rockettile_buffer_out_a_bits_size), // @[ClockDomain.scala:14:9] .auto_in_a_bits_source (element_reset_domain_auto_rockettile_buffer_out_a_bits_source), // @[ClockDomain.scala:14:9] .auto_in_a_bits_address (element_reset_domain_auto_rockettile_buffer_out_a_bits_address), // @[ClockDomain.scala:14:9] .auto_in_a_bits_mask (element_reset_domain_auto_rockettile_buffer_out_a_bits_mask), // @[ClockDomain.scala:14:9] .auto_in_a_bits_data (element_reset_domain_auto_rockettile_buffer_out_a_bits_data), // @[ClockDomain.scala:14:9] .auto_in_b_ready (element_reset_domain_auto_rockettile_buffer_out_b_ready), // @[ClockDomain.scala:14:9] .auto_in_b_valid (element_reset_domain_auto_rockettile_buffer_out_b_valid), .auto_in_b_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_b_bits_opcode), .auto_in_b_bits_param (element_reset_domain_auto_rockettile_buffer_out_b_bits_param), .auto_in_b_bits_size (element_reset_domain_auto_rockettile_buffer_out_b_bits_size), .auto_in_b_bits_source (element_reset_domain_auto_rockettile_buffer_out_b_bits_source), .auto_in_b_bits_address (element_reset_domain_auto_rockettile_buffer_out_b_bits_address), .auto_in_b_bits_mask (element_reset_domain_auto_rockettile_buffer_out_b_bits_mask), .auto_in_b_bits_data (element_reset_domain_auto_rockettile_buffer_out_b_bits_data), .auto_in_b_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_b_bits_corrupt), .auto_in_c_ready (element_reset_domain_auto_rockettile_buffer_out_c_ready), .auto_in_c_valid (element_reset_domain_auto_rockettile_buffer_out_c_valid), // @[ClockDomain.scala:14:9] .auto_in_c_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_c_bits_opcode), // @[ClockDomain.scala:14:9] .auto_in_c_bits_param (element_reset_domain_auto_rockettile_buffer_out_c_bits_param), // @[ClockDomain.scala:14:9] .auto_in_c_bits_size (element_reset_domain_auto_rockettile_buffer_out_c_bits_size), // @[ClockDomain.scala:14:9] .auto_in_c_bits_source (element_reset_domain_auto_rockettile_buffer_out_c_bits_source), // @[ClockDomain.scala:14:9] .auto_in_c_bits_address (element_reset_domain_auto_rockettile_buffer_out_c_bits_address), // @[ClockDomain.scala:14:9] .auto_in_c_bits_data (element_reset_domain_auto_rockettile_buffer_out_c_bits_data), // @[ClockDomain.scala:14:9] .auto_in_d_ready (element_reset_domain_auto_rockettile_buffer_out_d_ready), // @[ClockDomain.scala:14:9] .auto_in_d_valid (element_reset_domain_auto_rockettile_buffer_out_d_valid), .auto_in_d_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_d_bits_opcode), .auto_in_d_bits_param (element_reset_domain_auto_rockettile_buffer_out_d_bits_param), .auto_in_d_bits_size (element_reset_domain_auto_rockettile_buffer_out_d_bits_size), .auto_in_d_bits_source (element_reset_domain_auto_rockettile_buffer_out_d_bits_source), .auto_in_d_bits_sink (element_reset_domain_auto_rockettile_buffer_out_d_bits_sink), .auto_in_d_bits_denied (element_reset_domain_auto_rockettile_buffer_out_d_bits_denied), .auto_in_d_bits_data (element_reset_domain_auto_rockettile_buffer_out_d_bits_data), .auto_in_d_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_d_bits_corrupt), .auto_in_e_ready (element_reset_domain_auto_rockettile_buffer_out_e_ready), .auto_in_e_valid (element_reset_domain_auto_rockettile_buffer_out_e_valid), // @[ClockDomain.scala:14:9] .auto_in_e_bits_sink (element_reset_domain_auto_rockettile_buffer_out_e_bits_sink), // @[ClockDomain.scala:14:9] .auto_out_a_ready (tlMasterClockXingIn_a_ready), // @[MixedNode.scala:551:17] .auto_out_a_valid (tlMasterClockXingIn_a_valid), .auto_out_a_bits_opcode (tlMasterClockXingIn_a_bits_opcode), .auto_out_a_bits_param (tlMasterClockXingIn_a_bits_param), .auto_out_a_bits_size (tlMasterClockXingIn_a_bits_size), .auto_out_a_bits_source (tlMasterClockXingIn_a_bits_source), .auto_out_a_bits_address (tlMasterClockXingIn_a_bits_address), .auto_out_a_bits_mask (tlMasterClockXingIn_a_bits_mask), .auto_out_a_bits_data (tlMasterClockXingIn_a_bits_data), .auto_out_a_bits_corrupt (tlMasterClockXingIn_a_bits_corrupt), .auto_out_b_ready (tlMasterClockXingIn_b_ready), .auto_out_b_valid (tlMasterClockXingIn_b_valid), // @[MixedNode.scala:551:17] .auto_out_b_bits_opcode (tlMasterClockXingIn_b_bits_opcode), // @[MixedNode.scala:551:17] .auto_out_b_bits_param (tlMasterClockXingIn_b_bits_param), // @[MixedNode.scala:551:17] .auto_out_b_bits_size (tlMasterClockXingIn_b_bits_size), // @[MixedNode.scala:551:17] .auto_out_b_bits_source (tlMasterClockXingIn_b_bits_source), // @[MixedNode.scala:551:17] .auto_out_b_bits_address (tlMasterClockXingIn_b_bits_address), // @[MixedNode.scala:551:17] .auto_out_b_bits_mask (tlMasterClockXingIn_b_bits_mask), // @[MixedNode.scala:551:17] .auto_out_b_bits_data (tlMasterClockXingIn_b_bits_data), // @[MixedNode.scala:551:17] .auto_out_b_bits_corrupt (tlMasterClockXingIn_b_bits_corrupt), // @[MixedNode.scala:551:17] .auto_out_c_ready (tlMasterClockXingIn_c_ready), // @[MixedNode.scala:551:17] .auto_out_c_valid (tlMasterClockXingIn_c_valid), .auto_out_c_bits_opcode (tlMasterClockXingIn_c_bits_opcode), .auto_out_c_bits_param (tlMasterClockXingIn_c_bits_param), .auto_out_c_bits_size (tlMasterClockXingIn_c_bits_size), .auto_out_c_bits_source (tlMasterClockXingIn_c_bits_source), .auto_out_c_bits_address (tlMasterClockXingIn_c_bits_address), .auto_out_c_bits_data (tlMasterClockXingIn_c_bits_data), .auto_out_c_bits_corrupt (tlMasterClockXingIn_c_bits_corrupt), .auto_out_d_ready (tlMasterClockXingIn_d_ready), .auto_out_d_valid (tlMasterClockXingIn_d_valid), // @[MixedNode.scala:551:17] .auto_out_d_bits_opcode (tlMasterClockXingIn_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_out_d_bits_param (tlMasterClockXingIn_d_bits_param), // @[MixedNode.scala:551:17] .auto_out_d_bits_size (tlMasterClockXingIn_d_bits_size), // @[MixedNode.scala:551:17] .auto_out_d_bits_source (tlMasterClockXingIn_d_bits_source), // @[MixedNode.scala:551:17] .auto_out_d_bits_sink (tlMasterClockXingIn_d_bits_sink), // @[MixedNode.scala:551:17] .auto_out_d_bits_denied (tlMasterClockXingIn_d_bits_denied), // @[MixedNode.scala:551:17] .auto_out_d_bits_data (tlMasterClockXingIn_d_bits_data), // @[MixedNode.scala:551:17] .auto_out_d_bits_corrupt (tlMasterClockXingIn_d_bits_corrupt), // @[MixedNode.scala:551:17] .auto_out_e_ready (tlMasterClockXingIn_e_ready), // @[MixedNode.scala:551:17] .auto_out_e_valid (tlMasterClockXingIn_e_valid), .auto_out_e_bits_sink (tlMasterClockXingIn_e_bits_sink) ); // @[Buffer.scala:75:28] TLBuffer_20 buffer_1 ( // @[Buffer.scala:75:28] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset) // @[LazyModuleImp.scala:158:31] ); // @[Buffer.scala:75:28] IntSyncAsyncCrossingSink_n1x1_7 intsink ( // @[Crossing.scala:86:29] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_sync_0 (auto_intsink_in_sync_0_0), // @[ClockDomain.scala:14:9] .auto_out_0 (element_reset_domain_auto_rockettile_int_local_in_0_0) ); // @[Crossing.scala:86:29] IntSyncSyncCrossingSink_n1x2_11 intsink_1 ( // @[Crossing.scala:109:29] .auto_in_sync_0 (intInClockXingOut_sync_0), // @[MixedNode.scala:542:17] .auto_in_sync_1 (intInClockXingOut_sync_1), // @[MixedNode.scala:542:17] .auto_out_0 (element_reset_domain_auto_rockettile_int_local_in_1_0), .auto_out_1 (element_reset_domain_auto_rockettile_int_local_in_1_1) ); // @[Crossing.scala:109:29] IntSyncSyncCrossingSink_n1x1_43 intsink_2 ( // @[Crossing.scala:109:29] .auto_in_sync_0 (intInClockXingOut_1_sync_0), // @[MixedNode.scala:542:17] .auto_out_0 (element_reset_domain_auto_rockettile_int_local_in_2_0) ); // @[Crossing.scala:109:29] IntSyncSyncCrossingSink_n1x1_44 intsink_3 ( // @[Crossing.scala:109:29] .auto_in_sync_0 (intInClockXingOut_2_sync_0), // @[MixedNode.scala:542:17] .auto_out_0 (element_reset_domain_auto_rockettile_int_local_in_3_0) ); // @[Crossing.scala:109:29] IntSyncSyncCrossingSink_n1x1_45 intsink_4 (); // @[Crossing.scala:109:29] IntSyncCrossingSource_n1x1_29 intsource ( // @[Crossing.scala:29:31] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset) // @[LazyModuleImp.scala:158:31] ); // @[Crossing.scala:29:31] IntSyncSyncCrossingSink_n1x1_46 intsink_5 ( // @[Crossing.scala:109:29] .auto_in_sync_0 (intOutClockXingOut_2_sync_0), // @[MixedNode.scala:542:17] .auto_out_0 (auto_intsink_out_1_0_0) ); // @[Crossing.scala:109:29] IntSyncCrossingSource_n1x1_30 intsource_1 ( // @[Crossing.scala:29:31] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_0 (element_reset_domain_auto_rockettile_wfi_out_0), // @[ClockDomain.scala:14:9] .auto_out_sync_0 (intOutClockXingIn_3_sync_0) ); // @[Crossing.scala:29:31] IntSyncSyncCrossingSink_n1x1_47 intsink_6 (); // @[Crossing.scala:109:29] IntSyncCrossingSource_n1x1_31 intsource_2 ( // @[Crossing.scala:29:31] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset) // @[LazyModuleImp.scala:158:31] ); // @[Crossing.scala:29:31] assign auto_intsink_out_1_0 = auto_intsink_out_1_0_0; // @[ClockDomain.scala:14:9] assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_valid = auto_element_reset_domain_rockettile_trace_source_out_insns_0_valid_0; // @[ClockDomain.scala:14:9] assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_iaddr = auto_element_reset_domain_rockettile_trace_source_out_insns_0_iaddr_0; // @[ClockDomain.scala:14:9] assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_insn = auto_element_reset_domain_rockettile_trace_source_out_insns_0_insn_0; // @[ClockDomain.scala:14:9] assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_priv = auto_element_reset_domain_rockettile_trace_source_out_insns_0_priv_0; // @[ClockDomain.scala:14:9] assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_exception = auto_element_reset_domain_rockettile_trace_source_out_insns_0_exception_0; // @[ClockDomain.scala:14:9] assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_interrupt = auto_element_reset_domain_rockettile_trace_source_out_insns_0_interrupt_0; // @[ClockDomain.scala:14:9] assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_cause = auto_element_reset_domain_rockettile_trace_source_out_insns_0_cause_0; // @[ClockDomain.scala:14:9] assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_tval = auto_element_reset_domain_rockettile_trace_source_out_insns_0_tval_0; // @[ClockDomain.scala:14:9] assign auto_element_reset_domain_rockettile_trace_source_out_time = auto_element_reset_domain_rockettile_trace_source_out_time_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_a_valid = auto_tl_master_clock_xing_out_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_a_bits_opcode = auto_tl_master_clock_xing_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_a_bits_param = auto_tl_master_clock_xing_out_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_a_bits_size = auto_tl_master_clock_xing_out_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_a_bits_source = auto_tl_master_clock_xing_out_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_a_bits_address = auto_tl_master_clock_xing_out_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_a_bits_mask = auto_tl_master_clock_xing_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_a_bits_data = auto_tl_master_clock_xing_out_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_a_bits_corrupt = auto_tl_master_clock_xing_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_b_ready = auto_tl_master_clock_xing_out_b_ready_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_c_valid = auto_tl_master_clock_xing_out_c_valid_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_c_bits_opcode = auto_tl_master_clock_xing_out_c_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_c_bits_param = auto_tl_master_clock_xing_out_c_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_c_bits_size = auto_tl_master_clock_xing_out_c_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_c_bits_source = auto_tl_master_clock_xing_out_c_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_c_bits_address = auto_tl_master_clock_xing_out_c_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_c_bits_data = auto_tl_master_clock_xing_out_c_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_c_bits_corrupt = auto_tl_master_clock_xing_out_c_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_d_ready = auto_tl_master_clock_xing_out_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_e_valid = auto_tl_master_clock_xing_out_e_valid_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_e_bits_sink = auto_tl_master_clock_xing_out_e_bits_sink_0; // @[ClockDomain.scala:14:9] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Tile.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ import Util._ /** * A Tile is a purely combinational 2D array of passThrough PEs. * a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs * @param width The data width of each PE in bits * @param rows Number of PEs on each row * @param columns Number of PEs on each column */ class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module { val io = IO(new Bundle { val in_a = Input(Vec(rows, inputType)) val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it val in_d = Input(Vec(columns, outputType)) val in_control = Input(Vec(columns, new PEControl(accType))) val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val in_last = Input(Vec(columns, Bool())) val out_a = Output(Vec(rows, inputType)) val out_c = Output(Vec(columns, outputType)) val out_b = Output(Vec(columns, outputType)) val out_control = Output(Vec(columns, new PEControl(accType))) val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val out_last = Output(Vec(columns, Bool())) val in_valid = Input(Vec(columns, Bool())) val out_valid = Output(Vec(columns, Bool())) val bad_dataflow = Output(Bool()) }) import ev._ val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls))) val tileT = tile.transpose // TODO: abstract hori/vert broadcast, all these connections look the same // Broadcast 'a' horizontally across the Tile for (r <- 0 until rows) { tile(r).foldLeft(io.in_a(r)) { case (in_a, pe) => pe.io.in_a := in_a pe.io.out_a } } // Broadcast 'b' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_b(c)) { case (in_b, pe) => pe.io.in_b := (if (tree_reduction) in_b.zero else in_b) pe.io.out_b } } // Broadcast 'd' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_d(c)) { case (in_d, pe) => pe.io.in_d := in_d pe.io.out_c } } // Broadcast 'control' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_control(c)) { case (in_ctrl, pe) => pe.io.in_control := in_ctrl pe.io.out_control } } // Broadcast 'garbage' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_valid(c)) { case (v, pe) => pe.io.in_valid := v pe.io.out_valid } } // Broadcast 'id' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_id(c)) { case (id, pe) => pe.io.in_id := id pe.io.out_id } } // Broadcast 'last' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_last(c)) { case (last, pe) => pe.io.in_last := last pe.io.out_last } } // Drive the Tile's bottom IO for (c <- 0 until columns) { io.out_c(c) := tile(rows-1)(c).io.out_c io.out_control(c) := tile(rows-1)(c).io.out_control io.out_id(c) := tile(rows-1)(c).io.out_id io.out_last(c) := tile(rows-1)(c).io.out_last io.out_valid(c) := tile(rows-1)(c).io.out_valid io.out_b(c) := { if (tree_reduction) { val prods = tileT(c).map(_.io.out_b) accumulateTree(prods :+ io.in_b(c)) } else { tile(rows - 1)(c).io.out_b } } } io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_||_)).reduce(_||_) // Drive the Tile's right IO for (r <- 0 until rows) { io.out_a(r) := tile(r)(columns-1).io.out_a } }

module Tile_1( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_257 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } } File Arbiter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ object TLArbiter { // (valids, select) => readys type Policy = (Integer, UInt, Bool) => UInt val lowestIndexFirst: Policy = (width, valids, select) => ~(leftOR(valids) << 1)(width-1, 0) val highestIndexFirst: Policy = (width, valids, select) => ~((rightOR(valids) >> 1).pad(width)) val roundRobin: Policy = (width, valids, select) => if (width == 1) 1.U(1.W) else { val valid = valids(width-1, 0) assert (valid === valids) val mask = RegInit(((BigInt(1) << width)-1).U(width-1,0)) val filter = Cat(valid & ~mask, valid) val unready = (rightOR(filter, width*2, width) >> 1) | (mask << width) val readys = ~((unready >> width) & unready(width-1, 0)) when (select && valid.orR) { mask := leftOR(readys & valid, width) } readys(width-1, 0) } def lowestFromSeq[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: Seq[DecoupledIO[T]]): Unit = { apply(lowestIndexFirst)(sink, sources.map(s => (edge.numBeats1(s.bits), s)):_*) } def lowest[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]*): Unit = { apply(lowestIndexFirst)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_*) } def highest[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]*): Unit = { apply(highestIndexFirst)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_*) } def robin[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]*): Unit = { apply(roundRobin)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_*) } def apply[T <: Data](policy: Policy)(sink: DecoupledIO[T], sources: (UInt, DecoupledIO[T])*): Unit = { if (sources.isEmpty) { sink.bits := DontCare } else if (sources.size == 1) { sink :<>= sources.head._2 } else { val pairs = sources.toList val beatsIn = pairs.map(_._1) val sourcesIn = pairs.map(_._2) // The number of beats which remain to be sent val beatsLeft = RegInit(0.U) val idle = beatsLeft === 0.U val latch = idle && sink.ready // winner (if any) claims sink // Who wants access to the sink? val valids = sourcesIn.map(_.valid) // Arbitrate amongst the requests val readys = VecInit(policy(valids.size, Cat(valids.reverse), latch).asBools) // Which request wins arbitration? val winner = VecInit((readys zip valids) map { case (r,v) => r&&v }) // Confirm the policy works properly require (readys.size == valids.size) // Never two winners val prefixOR = winner.scanLeft(false.B)(_||_).init assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _}) // If there was any request, there is a winner assert (!valids.reduce(_||_) || winner.reduce(_||_)) // Track remaining beats val maskedBeats = (winner zip beatsIn) map { case (w,b) => Mux(w, b, 0.U) } val initBeats = maskedBeats.reduce(_ | _) // no winner => 0 beats beatsLeft := Mux(latch, initBeats, beatsLeft - sink.fire) // The one-hot source granted access in the previous cycle val state = RegInit(VecInit(Seq.fill(sources.size)(false.B))) val muxState = Mux(idle, winner, state) state := muxState val allowed = Mux(idle, readys, state) (sourcesIn zip allowed) foreach { case (s, r) => s.ready := sink.ready && r } sink.valid := Mux(idle, valids.reduce(_||_), Mux1H(state, valids)) sink.bits :<= Mux1H(muxState, sourcesIn.map(_.bits)) } } } // Synthesizable unit tests import freechips.rocketchip.unittest._ abstract class DecoupledArbiterTest( policy: TLArbiter.Policy, txns: Int, timeout: Int, val numSources: Int, beatsLeftFromIdx: Int => UInt) (implicit p: Parameters) extends UnitTest(timeout) { val sources = Wire(Vec(numSources, DecoupledIO(UInt(log2Ceil(numSources).W)))) dontTouch(sources.suggestName("sources")) val sink = Wire(DecoupledIO(UInt(log2Ceil(numSources).W))) dontTouch(sink.suggestName("sink")) val count = RegInit(0.U(log2Ceil(txns).W)) val lfsr = LFSR(16, true.B) sources.zipWithIndex.map { case (z, i) => z.bits := i.U } TLArbiter(policy)(sink, sources.zipWithIndex.map { case (z, i) => (beatsLeftFromIdx(i), z) }:_*) count := count + 1.U io.finished := count >= txns.U } /** This tests that when a specific pattern of source valids are driven, * a new index from amongst that pattern is always selected, * unless one of those sources takes multiple beats, * in which case the same index should be selected until the arbiter goes idle. */ class TLDecoupledArbiterRobinTest(txns: Int = 128, timeout: Int = 500000, print: Boolean = false) (implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.roundRobin, txns, timeout, 6, i => i.U) { val lastWinner = RegInit((numSources+1).U) val beatsLeft = RegInit(0.U(log2Ceil(numSources).W)) val first = lastWinner > numSources.U val valid = lfsr(0) val ready = lfsr(15) sink.ready := ready sources.zipWithIndex.map { // pattern: every even-indexed valid is driven the same random way case (s, i) => s.valid := (if (i % 2 == 1) false.B else valid) } when (sink.fire) { if (print) { printf("TestRobin: %d\n", sink.bits) } when (beatsLeft === 0.U) { assert(lastWinner =/= sink.bits, "Round robin did not pick a new idx despite one being valid.") lastWinner := sink.bits beatsLeft := sink.bits } .otherwise { assert(lastWinner === sink.bits, "Round robin did not pick the same index over multiple beats") beatsLeft := beatsLeft - 1.U } } if (print) { when (!sink.fire) { printf("TestRobin: idle (%d %d)\n", valid, ready) } } } /** This tests that the lowest index is always selected across random single cycle transactions. */ class TLDecoupledArbiterLowestTest(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.lowestIndexFirst, txns, timeout, 15, _ => 0.U) { def assertLowest(id: Int): Unit = { when (sources(id).valid) { assert((numSources-1 until id by -1).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a higher valid source was granted ready.") } } sources.zipWithIndex.map { case (s, i) => s.valid := lfsr(i) } sink.ready := lfsr(15) when (sink.fire) { (0 until numSources).foreach(assertLowest(_)) } } /** This tests that the highest index is always selected across random single cycle transactions. */ class TLDecoupledArbiterHighestTest(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.highestIndexFirst, txns, timeout, 15, _ => 0.U) { def assertHighest(id: Int): Unit = { when (sources(id).valid) { assert((0 until id).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a lower valid source was granted ready.") } } sources.zipWithIndex.map { case (s, i) => s.valid := lfsr(i) } sink.ready := lfsr(15) when (sink.fire) { (0 until numSources).foreach(assertHighest(_)) } } File Xbar.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressDecoder, AddressSet, RegionType, IdRange, TriStateValue} import freechips.rocketchip.util.BundleField // Trades off slave port proximity against routing resource cost object ForceFanout { def apply[T]( a: TriStateValue = TriStateValue.unset, b: TriStateValue = TriStateValue.unset, c: TriStateValue = TriStateValue.unset, d: TriStateValue = TriStateValue.unset, e: TriStateValue = TriStateValue.unset)(body: Parameters => T)(implicit p: Parameters) = { body(p.alterPartial { case ForceFanoutKey => p(ForceFanoutKey) match { case ForceFanoutParams(pa, pb, pc, pd, pe) => ForceFanoutParams(a.update(pa), b.update(pb), c.update(pc), d.update(pd), e.update(pe)) } }) } } private case class ForceFanoutParams(a: Boolean, b: Boolean, c: Boolean, d: Boolean, e: Boolean) private case object ForceFanoutKey extends Field(ForceFanoutParams(false, false, false, false, false)) class TLXbar(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule { val node = new TLNexusNode( clientFn = { seq => seq(0).v1copy( echoFields = BundleField.union(seq.flatMap(_.echoFields)), requestFields = BundleField.union(seq.flatMap(_.requestFields)), responseKeys = seq.flatMap(_.responseKeys).distinct, minLatency = seq.map(_.minLatency).min, clients = (TLXbar.mapInputIds(seq) zip seq) flatMap { case (range, port) => port.clients map { client => client.v1copy( sourceId = client.sourceId.shift(range.start) )} } ) }, managerFn = { seq => val fifoIdFactory = TLXbar.relabeler() seq(0).v1copy( responseFields = BundleField.union(seq.flatMap(_.responseFields)), requestKeys = seq.flatMap(_.requestKeys).distinct, minLatency = seq.map(_.minLatency).min, endSinkId = TLXbar.mapOutputIds(seq).map(_.end).max, managers = seq.flatMap { port => require (port.beatBytes == seq(0).beatBytes, s"Xbar ($name with parent $parent) data widths don't match: ${port.managers.map(_.name)} has ${port.beatBytes}B vs ${seq(0).managers.map(_.name)} has ${seq(0).beatBytes}B") val fifoIdMapper = fifoIdFactory() port.managers map { manager => manager.v1copy( fifoId = manager.fifoId.map(fifoIdMapper(_)) )} } ) } ){ override def circuitIdentity = outputs.size == 1 && inputs.size == 1 } lazy val module = new Impl class Impl extends LazyModuleImp(this) { if ((node.in.size * node.out.size) > (8*32)) { println (s"!!! WARNING !!!") println (s" Your TLXbar ($name with parent $parent) is very large, with ${node.in.size} Masters and ${node.out.size} Slaves.") println (s"!!! WARNING !!!") } val wide_bundle = TLBundleParameters.union((node.in ++ node.out).map(_._2.bundle)) override def desiredName = (Seq("TLXbar") ++ nameSuffix ++ Seq(s"i${node.in.size}_o${node.out.size}_${wide_bundle.shortName}")).mkString("_") TLXbar.circuit(policy, node.in, node.out) } } object TLXbar { def mapInputIds(ports: Seq[TLMasterPortParameters]) = assignRanges(ports.map(_.endSourceId)) def mapOutputIds(ports: Seq[TLSlavePortParameters]) = assignRanges(ports.map(_.endSinkId)) def assignRanges(sizes: Seq[Int]) = { val pow2Sizes = sizes.map { z => if (z == 0) 0 else 1 << log2Ceil(z) } val tuples = pow2Sizes.zipWithIndex.sortBy(_._1) // record old index, then sort by increasing size val starts = tuples.scanRight(0)(_._1 + _).tail // suffix-sum of the sizes = the start positions val ranges = (tuples zip starts) map { case ((sz, i), st) => (if (sz == 0) IdRange(0, 0) else IdRange(st, st + sz), i) } ranges.sortBy(_._2).map(_._1) // Restore orignal order } def relabeler() = { var idFactory = 0 () => { val fifoMap = scala.collection.mutable.HashMap.empty[Int, Int] (x: Int) => { if (fifoMap.contains(x)) fifoMap(x) else { val out = idFactory idFactory = idFactory + 1 fifoMap += (x -> out) out } } } } def circuit(policy: TLArbiter.Policy, seqIn: Seq[(TLBundle, TLEdge)], seqOut: Seq[(TLBundle, TLEdge)]) { val (io_in, edgesIn) = seqIn.unzip val (io_out, edgesOut) = seqOut.unzip // Not every master need connect to every slave on every channel; determine which connections are necessary val reachableIO = edgesIn.map { cp => edgesOut.map { mp => cp.client.clients.exists { c => mp.manager.managers.exists { m => c.visibility.exists { ca => m.address.exists { ma => ca.overlaps(ma)}}}} }.toVector}.toVector val probeIO = (edgesIn zip reachableIO).map { case (cp, reachableO) => (edgesOut zip reachableO).map { case (mp, reachable) => reachable && cp.client.anySupportProbe && mp.manager.managers.exists(_.regionType >= RegionType.TRACKED) }.toVector}.toVector val releaseIO = (edgesIn zip reachableIO).map { case (cp, reachableO) => (edgesOut zip reachableO).map { case (mp, reachable) => reachable && cp.client.anySupportProbe && mp.manager.anySupportAcquireB }.toVector}.toVector val connectAIO = reachableIO val connectBIO = probeIO val connectCIO = releaseIO val connectDIO = reachableIO val connectEIO = releaseIO def transpose[T](x: Seq[Seq[T]]) = if (x.isEmpty) Nil else Vector.tabulate(x(0).size) { i => Vector.tabulate(x.size) { j => x(j)(i) } } val connectAOI = transpose(connectAIO) val connectBOI = transpose(connectBIO) val connectCOI = transpose(connectCIO) val connectDOI = transpose(connectDIO) val connectEOI = transpose(connectEIO) // Grab the port ID mapping val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client)) val outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager)) // We need an intermediate size of bundle with the widest possible identifiers val wide_bundle = TLBundleParameters.union(io_in.map(_.params) ++ io_out.map(_.params)) // Handle size = 1 gracefully (Chisel3 empty range is broken) def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0) // Transform input bundle sources (sinks use global namespace on both sides) val in = Wire(Vec(io_in.size, TLBundle(wide_bundle))) for (i <- 0 until in.size) { val r = inputIdRanges(i) if (connectAIO(i).exists(x=>x)) { in(i).a.bits.user := DontCare in(i).a.squeezeAll.waiveAll :<>= io_in(i).a.squeezeAll.waiveAll in(i).a.bits.source := io_in(i).a.bits.source | r.start.U } else { in(i).a := DontCare io_in(i).a := DontCare in(i).a.valid := false.B io_in(i).a.ready := true.B } if (connectBIO(i).exists(x=>x)) { io_in(i).b.squeezeAll :<>= in(i).b.squeezeAll io_in(i).b.bits.source := trim(in(i).b.bits.source, r.size) } else { in(i).b := DontCare io_in(i).b := DontCare in(i).b.ready := true.B io_in(i).b.valid := false.B } if (connectCIO(i).exists(x=>x)) { in(i).c.bits.user := DontCare in(i).c.squeezeAll.waiveAll :<>= io_in(i).c.squeezeAll.waiveAll in(i).c.bits.source := io_in(i).c.bits.source | r.start.U } else { in(i).c := DontCare io_in(i).c := DontCare in(i).c.valid := false.B io_in(i).c.ready := true.B } if (connectDIO(i).exists(x=>x)) { io_in(i).d.squeezeAll.waiveAll :<>= in(i).d.squeezeAll.waiveAll io_in(i).d.bits.source := trim(in(i).d.bits.source, r.size) } else { in(i).d := DontCare io_in(i).d := DontCare in(i).d.ready := true.B io_in(i).d.valid := false.B } if (connectEIO(i).exists(x=>x)) { in(i).e.squeezeAll :<>= io_in(i).e.squeezeAll } else { in(i).e := DontCare io_in(i).e := DontCare in(i).e.valid := false.B io_in(i).e.ready := true.B } } // Transform output bundle sinks (sources use global namespace on both sides) val out = Wire(Vec(io_out.size, TLBundle(wide_bundle))) for (o <- 0 until out.size) { val r = outputIdRanges(o) if (connectAOI(o).exists(x=>x)) { out(o).a.bits.user := DontCare io_out(o).a.squeezeAll.waiveAll :<>= out(o).a.squeezeAll.waiveAll } else { out(o).a := DontCare io_out(o).a := DontCare out(o).a.ready := true.B io_out(o).a.valid := false.B } if (connectBOI(o).exists(x=>x)) { out(o).b.squeezeAll :<>= io_out(o).b.squeezeAll } else { out(o).b := DontCare io_out(o).b := DontCare out(o).b.valid := false.B io_out(o).b.ready := true.B } if (connectCOI(o).exists(x=>x)) { out(o).c.bits.user := DontCare io_out(o).c.squeezeAll.waiveAll :<>= out(o).c.squeezeAll.waiveAll } else { out(o).c := DontCare io_out(o).c := DontCare out(o).c.ready := true.B io_out(o).c.valid := false.B } if (connectDOI(o).exists(x=>x)) { out(o).d.squeezeAll :<>= io_out(o).d.squeezeAll out(o).d.bits.sink := io_out(o).d.bits.sink | r.start.U } else { out(o).d := DontCare io_out(o).d := DontCare out(o).d.valid := false.B io_out(o).d.ready := true.B } if (connectEOI(o).exists(x=>x)) { io_out(o).e.squeezeAll :<>= out(o).e.squeezeAll io_out(o).e.bits.sink := trim(out(o).e.bits.sink, r.size) } else { out(o).e := DontCare io_out(o).e := DontCare out(o).e.ready := true.B io_out(o).e.valid := false.B } } // Filter a list to only those elements selected def filter[T](data: Seq[T], mask: Seq[Boolean]) = (data zip mask).filter(_._2).map(_._1) // Based on input=>output connectivity, create per-input minimal address decode circuits val requiredAC = (connectAIO ++ connectCIO).distinct val outputPortFns: Map[Vector[Boolean], Seq[UInt => Bool]] = requiredAC.map { connectO => val port_addrs = edgesOut.map(_.manager.managers.flatMap(_.address)) val routingMask = AddressDecoder(filter(port_addrs, connectO)) val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct)) // Print the address mapping if (false) { println("Xbar mapping:") route_addrs.foreach { p => print(" ") p.foreach { a => print(s" ${a}") } println("") } println("--") } (connectO, route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_ || _))) }.toMap // Print the ID mapping if (false) { println(s"XBar mapping:") (edgesIn zip inputIdRanges).zipWithIndex.foreach { case ((edge, id), i) => println(s"\t$i assigned ${id} for ${edge.client.clients.map(_.name).mkString(", ")}") } println("") } val addressA = (in zip edgesIn) map { case (i, e) => e.address(i.a.bits) } val addressC = (in zip edgesIn) map { case (i, e) => e.address(i.c.bits) } def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B val requestAIO = (connectAIO zip addressA) map { case (c, i) => outputPortFns(c).map { o => unique(c) || o(i) } } val requestCIO = (connectCIO zip addressC) map { case (c, i) => outputPortFns(c).map { o => unique(c) || o(i) } } val requestBOI = out.map { o => inputIdRanges.map { i => i.contains(o.b.bits.source) } } val requestDOI = out.map { o => inputIdRanges.map { i => i.contains(o.d.bits.source) } } val requestEIO = in.map { i => outputIdRanges.map { o => o.contains(i.e.bits.sink) } } val beatsAI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.a.bits) } val beatsBO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.b.bits) } val beatsCI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.c.bits) } val beatsDO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.d.bits) } val beatsEI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.e.bits) } // Fanout the input sources to the output sinks val portsAOI = transpose((in zip requestAIO) map { case (i, r) => TLXbar.fanout(i.a, r, edgesOut.map(_.params(ForceFanoutKey).a)) }) val portsBIO = transpose((out zip requestBOI) map { case (o, r) => TLXbar.fanout(o.b, r, edgesIn .map(_.params(ForceFanoutKey).b)) }) val portsCOI = transpose((in zip requestCIO) map { case (i, r) => TLXbar.fanout(i.c, r, edgesOut.map(_.params(ForceFanoutKey).c)) }) val portsDIO = transpose((out zip requestDOI) map { case (o, r) => TLXbar.fanout(o.d, r, edgesIn .map(_.params(ForceFanoutKey).d)) }) val portsEOI = transpose((in zip requestEIO) map { case (i, r) => TLXbar.fanout(i.e, r, edgesOut.map(_.params(ForceFanoutKey).e)) }) // Arbitrate amongst the sources for (o <- 0 until out.size) { TLArbiter(policy)(out(o).a, filter(beatsAI zip portsAOI(o), connectAOI(o)):_*) TLArbiter(policy)(out(o).c, filter(beatsCI zip portsCOI(o), connectCOI(o)):_*) TLArbiter(policy)(out(o).e, filter(beatsEI zip portsEOI(o), connectEOI(o)):_*) filter(portsAOI(o), connectAOI(o).map(!_)) foreach { r => r.ready := false.B } filter(portsCOI(o), connectCOI(o).map(!_)) foreach { r => r.ready := false.B } filter(portsEOI(o), connectEOI(o).map(!_)) foreach { r => r.ready := false.B } } for (i <- 0 until in.size) { TLArbiter(policy)(in(i).b, filter(beatsBO zip portsBIO(i), connectBIO(i)):_*) TLArbiter(policy)(in(i).d, filter(beatsDO zip portsDIO(i), connectDIO(i)):_*) filter(portsBIO(i), connectBIO(i).map(!_)) foreach { r => r.ready := false.B } filter(portsDIO(i), connectDIO(i).map(!_)) foreach { r => r.ready := false.B } } } def apply(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode = { val xbar = LazyModule(new TLXbar(policy, nameSuffix)) xbar.node } // Replicate an input port to each output port def fanout[T <: TLChannel](input: DecoupledIO[T], select: Seq[Bool], force: Seq[Boolean] = Nil): Seq[DecoupledIO[T]] = { val filtered = Wire(Vec(select.size, chiselTypeOf(input))) for (i <- 0 until select.size) { filtered(i).bits := (if (force.lift(i).getOrElse(false)) IdentityModule(input.bits) else input.bits) filtered(i).valid := input.valid && (select(i) || (select.size == 1).B) } input.ready := Mux1H(select, filtered.map(_.ready)) filtered } } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMXbar(nManagers: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("Xbar")) val xbar = LazyModule(new TLXbar) xbar.node := TLDelayer(0.1) := model.node := fuzz.node (0 until nManagers) foreach { n => val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff))) ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node } lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMXbarTest(nManagers: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMXbar(nManagers,txns)).module) dut.io.start := io.start io.finished := dut.io.finished } class TLMulticlientXbar(nManagers: Int, nClients: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val xbar = LazyModule(new TLXbar) val fuzzers = (0 until nClients) map { n => val fuzz = LazyModule(new TLFuzzer(txns)) xbar.node := TLDelayer(0.1) := fuzz.node fuzz } (0 until nManagers) foreach { n => val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff))) ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node } lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzzers.last.module.io.finished } } class TLMulticlientXbarTest(nManagers: Int, nClients: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLMulticlientXbar(nManagers, nClients, txns)).module) dut.io.start := io.start io.finished := dut.io.finished }

module TLXbar_cbus_in_i2_o1_a29d64s10k1z4u( // @[Xbar.scala:74:9] input clock, // @[Xbar.scala:74:9] input reset, // @[Xbar.scala:74:9] output auto_anon_in_1_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_a_valid, // @[LazyModuleImp.scala:107:25] input [28:0] auto_anon_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_1_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_1_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_0_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_0_a_bits_size, // @[LazyModuleImp.scala:107:25] input [8:0] auto_anon_in_0_a_bits_source, // @[LazyModuleImp.scala:107:25] input [28:0] auto_anon_in_0_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_0_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_0_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_0_d_bits_size, // @[LazyModuleImp.scala:107:25] output [8:0] auto_anon_in_0_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_0_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [9:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [28:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [9:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire out_0_d_bits_sink; // @[Xbar.scala:216:19] wire [9:0] in_0_a_bits_source; // @[Xbar.scala:159:18] wire auto_anon_in_1_a_valid_0 = auto_anon_in_1_a_valid; // @[Xbar.scala:74:9] wire [28:0] auto_anon_in_1_a_bits_address_0 = auto_anon_in_1_a_bits_address; // @[Xbar.scala:74:9] wire [63:0] auto_anon_in_1_a_bits_data_0 = auto_anon_in_1_a_bits_data; // @[Xbar.scala:74:9] wire auto_anon_in_0_a_valid_0 = auto_anon_in_0_a_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_a_bits_opcode_0 = auto_anon_in_0_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_a_bits_param_0 = auto_anon_in_0_a_bits_param; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_0_a_bits_size_0 = auto_anon_in_0_a_bits_size; // @[Xbar.scala:74:9] wire [8:0] auto_anon_in_0_a_bits_source_0 = auto_anon_in_0_a_bits_source; // @[Xbar.scala:74:9] wire [28:0] auto_anon_in_0_a_bits_address_0 = auto_anon_in_0_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] auto_anon_in_0_a_bits_mask_0 = auto_anon_in_0_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] auto_anon_in_0_a_bits_data_0 = auto_anon_in_0_a_bits_data; // @[Xbar.scala:74:9] wire auto_anon_in_0_a_bits_corrupt_0 = auto_anon_in_0_a_bits_corrupt; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_ready_0 = auto_anon_in_0_d_ready; // @[Xbar.scala:74:9] wire auto_anon_out_a_ready_0 = auto_anon_out_a_ready; // @[Xbar.scala:74:9] wire auto_anon_out_d_valid_0 = auto_anon_out_d_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_d_bits_opcode_0 = auto_anon_out_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] auto_anon_out_d_bits_param_0 = auto_anon_out_d_bits_param; // @[Xbar.scala:74:9] wire [3:0] auto_anon_out_d_bits_size_0 = auto_anon_out_d_bits_size; // @[Xbar.scala:74:9] wire [9:0] auto_anon_out_d_bits_source_0 = auto_anon_out_d_bits_source; // @[Xbar.scala:74:9] wire auto_anon_out_d_bits_sink_0 = auto_anon_out_d_bits_sink; // @[Xbar.scala:74:9] wire auto_anon_out_d_bits_denied_0 = auto_anon_out_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_d_bits_data_0 = auto_anon_out_d_bits_data; // @[Xbar.scala:74:9] wire auto_anon_out_d_bits_corrupt_0 = auto_anon_out_d_bits_corrupt; // @[Xbar.scala:74:9] wire _readys_T_2 = reset; // @[Arbiter.scala:22:12] wire [2:0] auto_anon_in_1_a_bits_opcode = 3'h0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_1_a_bits_param = 3'h0; // @[Xbar.scala:74:9] wire [2:0] anonIn_1_a_bits_opcode = 3'h0; // @[MixedNode.scala:551:17] wire [2:0] anonIn_1_a_bits_param = 3'h0; // @[MixedNode.scala:551:17] wire [2:0] in_1_a_bits_opcode = 3'h0; // @[Xbar.scala:159:18] wire [2:0] in_1_a_bits_param = 3'h0; // @[Xbar.scala:159:18] wire [2:0] _addressC_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _addressC_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _addressC_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _addressC_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _addressC_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _addressC_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _addressC_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _addressC_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _requestBOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _requestBOI_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _beatsBO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _beatsBO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _beatsCI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _beatsCI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _beatsCI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _beatsCI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _beatsCI_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _beatsCI_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _beatsCI_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _beatsCI_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] portsAOI_filtered_1_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsAOI_filtered_1_0_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] _portsBIO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _portsBIO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] portsBIO_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsBIO_filtered_1_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] _portsCOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _portsCOI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _portsCOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _portsCOI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] portsCOI_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_0_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] _portsCOI_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _portsCOI_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _portsCOI_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _portsCOI_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] portsCOI_filtered_1_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_0_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] _out_0_a_bits_T_19 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_0_a_bits_T_22 = 3'h0; // @[Mux.scala:30:73] wire [3:0] auto_anon_in_1_a_bits_size = 4'h2; // @[Xbar.scala:74:9] wire [3:0] anonIn_1_a_bits_size = 4'h2; // @[MixedNode.scala:551:17] wire [3:0] in_1_a_bits_size = 4'h2; // @[Xbar.scala:159:18] wire [3:0] portsAOI_filtered_1_0_bits_size = 4'h2; // @[Xbar.scala:352:24] wire auto_anon_in_1_a_bits_source = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_in_1_a_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_bits_source = 1'h0; // @[Xbar.scala:74:9] wire anonIn_1_a_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_1_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_1_d_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire in_1_a_bits_corrupt = 1'h0; // @[Xbar.scala:159:18] wire _addressC_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _requestBOI_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_T = 1'h0; // @[Parameters.scala:54:10] wire _requestBOI_WIRE_2_ready = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_2_valid = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_3_ready = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_3_valid = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire requestBOI_0_1 = 1'h0; // @[Parameters.scala:46:9] wire _requestEIO_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_2_ready = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_2_valid = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_2_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_3_ready = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_3_valid = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_3_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _beatsAI_opdata_T_1 = 1'h0; // @[Edges.scala:92:37] wire _beatsBO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_opdata_T = 1'h0; // @[Edges.scala:97:37] wire _beatsCI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire beatsCI_opdata = 1'h0; // @[Edges.scala:102:36] wire _beatsCI_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire beatsCI_opdata_1 = 1'h0; // @[Edges.scala:102:36] wire _beatsEI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _beatsEI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _beatsEI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _beatsEI_WIRE_2_ready = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_2_valid = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_2_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_3_ready = 1'h0; // @[Bundles.scala:267:61] wire _beatsEI_WIRE_3_valid = 1'h0; // @[Bundles.scala:267:61] wire _beatsEI_WIRE_3_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire portsAOI_filtered_1_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsBIO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire portsBIO_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_ready = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_valid = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsBIO_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsBIO_filtered_1_valid_T = 1'h0; // @[Xbar.scala:355:54] wire _portsBIO_filtered_1_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsBIO_T = 1'h0; // @[Mux.scala:30:73] wire _portsBIO_T_1 = 1'h0; // @[Mux.scala:30:73] wire _portsBIO_T_2 = 1'h0; // @[Mux.scala:30:73] wire _portsBIO_WIRE_2 = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire portsCOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsCOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsCOI_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire portsCOI_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsCOI_filtered_0_valid_T_3 = 1'h0; // @[Xbar.scala:355:40] wire _portsEOI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _portsEOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _portsEOI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire portsEOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_0_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire _portsEOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsEOI_WIRE_2_ready = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_2_valid = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_2_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_3_ready = 1'h0; // @[Bundles.scala:267:61] wire _portsEOI_WIRE_3_valid = 1'h0; // @[Bundles.scala:267:61] wire _portsEOI_WIRE_3_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire portsEOI_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_0_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire _portsEOI_filtered_0_valid_T_3 = 1'h0; // @[Xbar.scala:355:40] wire _state_WIRE_0 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_1 = 1'h0; // @[Arbiter.scala:88:34] wire _out_0_a_bits_T_1 = 1'h0; // @[Mux.scala:30:73] wire [7:0] auto_anon_in_1_a_bits_mask = 8'hF; // @[Xbar.scala:74:9] wire [7:0] anonIn_1_a_bits_mask = 8'hF; // @[MixedNode.scala:551:17] wire [7:0] in_1_a_bits_mask = 8'hF; // @[Xbar.scala:159:18] wire [7:0] portsAOI_filtered_1_0_bits_mask = 8'hF; // @[Xbar.scala:352:24] wire auto_anon_in_1_d_ready = 1'h1; // @[Xbar.scala:74:9] wire anonIn_1_d_ready = 1'h1; // @[MixedNode.scala:551:17] wire in_1_d_ready = 1'h1; // @[Xbar.scala:159:18] wire _requestAIO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire requestAIO_0_0 = 1'h1; // @[Xbar.scala:307:107] wire _requestAIO_T_9 = 1'h1; // @[Parameters.scala:137:59] wire requestAIO_1_0 = 1'h1; // @[Xbar.scala:307:107] wire _requestCIO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_0_0 = 1'h1; // @[Xbar.scala:308:107] wire _requestCIO_T_9 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_1_0 = 1'h1; // @[Xbar.scala:308:107] wire _requestBOI_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _requestBOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _requestBOI_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _requestBOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire requestBOI_0_0 = 1'h1; // @[Parameters.scala:56:48] wire _requestDOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _requestDOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire beatsAI_opdata_1 = 1'h1; // @[Edges.scala:92:28] wire beatsBO_opdata = 1'h1; // @[Edges.scala:97:28] wire _portsAOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsAOI_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire _portsBIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire portsDIO_filtered_1_ready = 1'h1; // @[Xbar.scala:352:24] wire _portsEOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsEOI_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire [8:0] requestBOI_uncommonBits = 9'h0; // @[Parameters.scala:52:56] wire [8:0] beatsAI_decode_1 = 9'h0; // @[Edges.scala:220:59] wire [8:0] beatsAI_1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] beatsBO_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] beatsBO_0 = 9'h0; // @[Edges.scala:221:14] wire [8:0] beatsCI_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] beatsCI_0 = 9'h0; // @[Edges.scala:221:14] wire [8:0] beatsCI_decode_1 = 9'h0; // @[Edges.scala:220:59] wire [8:0] beatsCI_1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] maskedBeats_1 = 9'h0; // @[Arbiter.scala:82:69] wire [63:0] _addressC_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _addressC_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _addressC_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _addressC_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _requestBOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _requestBOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _requestBOI_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _requestBOI_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _beatsBO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _beatsBO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _beatsCI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _beatsCI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _beatsCI_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _beatsCI_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _portsBIO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _portsBIO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] portsBIO_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] portsBIO_filtered_1_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] _portsCOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _portsCOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] portsCOI_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] _portsCOI_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _portsCOI_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] portsCOI_filtered_1_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [28:0] _addressC_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _addressC_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _addressC_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _addressC_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _requestCIO_T = 29'h0; // @[Parameters.scala:137:31] wire [28:0] _requestCIO_T_5 = 29'h0; // @[Parameters.scala:137:31] wire [28:0] _requestBOI_WIRE_bits_address = 29'h0; // @[Bundles.scala:264:74] wire [28:0] _requestBOI_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:264:61] wire [28:0] _requestBOI_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:264:74] wire [28:0] _requestBOI_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:264:61] wire [28:0] _beatsBO_WIRE_bits_address = 29'h0; // @[Bundles.scala:264:74] wire [28:0] _beatsBO_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:264:61] wire [28:0] _beatsCI_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _beatsCI_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _beatsCI_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _beatsCI_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _portsBIO_WIRE_bits_address = 29'h0; // @[Bundles.scala:264:74] wire [28:0] _portsBIO_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:264:61] wire [28:0] portsBIO_filtered_0_bits_address = 29'h0; // @[Xbar.scala:352:24] wire [28:0] portsBIO_filtered_1_bits_address = 29'h0; // @[Xbar.scala:352:24] wire [28:0] _portsCOI_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _portsCOI_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] portsCOI_filtered_0_bits_address = 29'h0; // @[Xbar.scala:352:24] wire [28:0] _portsCOI_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _portsCOI_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] portsCOI_filtered_1_0_bits_address = 29'h0; // @[Xbar.scala:352:24] wire [9:0] _addressC_WIRE_bits_source = 10'h0; // @[Bundles.scala:265:74] wire [9:0] _addressC_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:265:61] wire [9:0] _addressC_WIRE_2_bits_source = 10'h0; // @[Bundles.scala:265:74] wire [9:0] _addressC_WIRE_3_bits_source = 10'h0; // @[Bundles.scala:265:61] wire [9:0] _requestBOI_WIRE_bits_source = 10'h0; // @[Bundles.scala:264:74] wire [9:0] _requestBOI_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:264:61] wire [9:0] _requestBOI_uncommonBits_T = 10'h0; // @[Parameters.scala:52:29] wire [9:0] _requestBOI_WIRE_2_bits_source = 10'h0; // @[Bundles.scala:264:74] wire [9:0] _requestBOI_WIRE_3_bits_source = 10'h0; // @[Bundles.scala:264:61] wire [9:0] _beatsBO_WIRE_bits_source = 10'h0; // @[Bundles.scala:264:74] wire [9:0] _beatsBO_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:264:61] wire [9:0] _beatsCI_WIRE_bits_source = 10'h0; // @[Bundles.scala:265:74] wire [9:0] _beatsCI_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:265:61] wire [9:0] _beatsCI_WIRE_2_bits_source = 10'h0; // @[Bundles.scala:265:74] wire [9:0] _beatsCI_WIRE_3_bits_source = 10'h0; // @[Bundles.scala:265:61] wire [9:0] _portsBIO_WIRE_bits_source = 10'h0; // @[Bundles.scala:264:74] wire [9:0] _portsBIO_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:264:61] wire [9:0] portsBIO_filtered_0_bits_source = 10'h0; // @[Xbar.scala:352:24] wire [9:0] portsBIO_filtered_1_bits_source = 10'h0; // @[Xbar.scala:352:24] wire [9:0] _portsCOI_WIRE_bits_source = 10'h0; // @[Bundles.scala:265:74] wire [9:0] _portsCOI_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:265:61] wire [9:0] portsCOI_filtered_0_bits_source = 10'h0; // @[Xbar.scala:352:24] wire [9:0] _portsCOI_WIRE_2_bits_source = 10'h0; // @[Bundles.scala:265:74] wire [9:0] _portsCOI_WIRE_3_bits_source = 10'h0; // @[Bundles.scala:265:61] wire [9:0] portsCOI_filtered_1_0_bits_source = 10'h0; // @[Xbar.scala:352:24] wire [3:0] _addressC_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _addressC_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _addressC_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _addressC_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _requestBOI_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _requestBOI_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _requestBOI_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _requestBOI_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _beatsBO_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _beatsBO_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _beatsCI_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _beatsCI_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _beatsCI_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _beatsCI_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _portsBIO_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _portsBIO_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] portsBIO_filtered_0_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [3:0] portsBIO_filtered_1_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [3:0] _portsCOI_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _portsCOI_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] portsCOI_filtered_0_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [3:0] _portsCOI_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _portsCOI_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] portsCOI_filtered_1_0_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [7:0] _requestBOI_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _requestBOI_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _requestBOI_WIRE_2_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _requestBOI_WIRE_3_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _beatsBO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _beatsBO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _portsBIO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _portsBIO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] portsBIO_filtered_0_bits_mask = 8'h0; // @[Xbar.scala:352:24] wire [7:0] portsBIO_filtered_1_bits_mask = 8'h0; // @[Xbar.scala:352:24] wire [1:0] _requestBOI_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _requestBOI_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _requestBOI_WIRE_2_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _requestBOI_WIRE_3_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _beatsBO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _beatsBO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _portsBIO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _portsBIO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] portsBIO_filtered_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] portsBIO_filtered_1_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [9:0] in_1_a_bits_source = 10'h200; // @[Xbar.scala:159:18] wire [9:0] _in_1_a_bits_source_T = 10'h200; // @[Xbar.scala:166:55] wire [9:0] portsAOI_filtered_1_0_bits_source = 10'h200; // @[Xbar.scala:352:24] wire [11:0] _beatsBO_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _beatsCI_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _beatsCI_decode_T_5 = 12'h0; // @[package.scala:243:46] wire [11:0] _beatsBO_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [11:0] _beatsCI_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [11:0] _beatsCI_decode_T_4 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _beatsBO_decode_T = 27'hFFF; // @[package.scala:243:71] wire [26:0] _beatsCI_decode_T = 27'hFFF; // @[package.scala:243:71] wire [26:0] _beatsCI_decode_T_3 = 27'hFFF; // @[package.scala:243:71] wire [11:0] _beatsAI_decode_T_5 = 12'h3; // @[package.scala:243:46] wire [11:0] _beatsAI_decode_T_4 = 12'hFFC; // @[package.scala:243:76] wire [26:0] _beatsAI_decode_T_3 = 27'h3FFC; // @[package.scala:243:71] wire [29:0] _requestAIO_T_2 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] _requestAIO_T_3 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] _requestAIO_T_7 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] _requestAIO_T_8 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] _requestCIO_T_1 = 30'h0; // @[Parameters.scala:137:41] wire [29:0] _requestCIO_T_2 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] _requestCIO_T_3 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] _requestCIO_T_6 = 30'h0; // @[Parameters.scala:137:41] wire [29:0] _requestCIO_T_7 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] _requestCIO_T_8 = 30'h0; // @[Parameters.scala:137:46] wire anonIn_1_a_ready; // @[MixedNode.scala:551:17] wire anonIn_1_a_valid = auto_anon_in_1_a_valid_0; // @[Xbar.scala:74:9] wire [28:0] anonIn_1_a_bits_address = auto_anon_in_1_a_bits_address_0; // @[Xbar.scala:74:9] wire [63:0] anonIn_1_a_bits_data = auto_anon_in_1_a_bits_data_0; // @[Xbar.scala:74:9] wire anonIn_1_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_1_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] anonIn_1_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] anonIn_1_d_bits_size; // @[MixedNode.scala:551:17] wire anonIn_1_d_bits_sink; // @[MixedNode.scala:551:17] wire anonIn_1_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] anonIn_1_d_bits_data; // @[MixedNode.scala:551:17] wire anonIn_1_d_bits_corrupt; // @[MixedNode.scala:551:17] wire anonIn_a_ready; // @[MixedNode.scala:551:17] wire anonIn_a_valid = auto_anon_in_0_a_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_a_bits_opcode = auto_anon_in_0_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_a_bits_param = auto_anon_in_0_a_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] anonIn_a_bits_size = auto_anon_in_0_a_bits_size_0; // @[Xbar.scala:74:9] wire [8:0] anonIn_a_bits_source = auto_anon_in_0_a_bits_source_0; // @[Xbar.scala:74:9] wire [28:0] anonIn_a_bits_address = auto_anon_in_0_a_bits_address_0; // @[Xbar.scala:74:9] wire [7:0] anonIn_a_bits_mask = auto_anon_in_0_a_bits_mask_0; // @[Xbar.scala:74:9] wire [63:0] anonIn_a_bits_data = auto_anon_in_0_a_bits_data_0; // @[Xbar.scala:74:9] wire anonIn_a_bits_corrupt = auto_anon_in_0_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire anonIn_d_ready = auto_anon_in_0_d_ready_0; // @[Xbar.scala:74:9] wire anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [8:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire anonOut_a_ready = auto_anon_out_a_ready_0; // @[Xbar.scala:74:9] wire anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [9:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [28:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire anonOut_d_ready; // @[MixedNode.scala:542:17] wire anonOut_d_valid = auto_anon_out_d_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonOut_d_bits_opcode = auto_anon_out_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] anonOut_d_bits_param = auto_anon_out_d_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] anonOut_d_bits_size = auto_anon_out_d_bits_size_0; // @[Xbar.scala:74:9] wire [9:0] anonOut_d_bits_source = auto_anon_out_d_bits_source_0; // @[Xbar.scala:74:9] wire anonOut_d_bits_sink = auto_anon_out_d_bits_sink_0; // @[Xbar.scala:74:9] wire anonOut_d_bits_denied = auto_anon_out_d_bits_denied_0; // @[Xbar.scala:74:9] wire [63:0] anonOut_d_bits_data = auto_anon_out_d_bits_data_0; // @[Xbar.scala:74:9] wire anonOut_d_bits_corrupt = auto_anon_out_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_a_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_1_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_1_d_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_1_d_bits_size_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_bits_sink_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_bits_denied_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_in_1_d_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_valid_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_a_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_0_d_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_0_d_bits_size_0; // @[Xbar.scala:74:9] wire [8:0] auto_anon_in_0_d_bits_source_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_bits_sink_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_bits_denied_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_in_0_d_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_valid_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_a_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_out_a_bits_size_0; // @[Xbar.scala:74:9] wire [9:0] auto_anon_out_a_bits_source_0; // @[Xbar.scala:74:9] wire [28:0] auto_anon_out_a_bits_address_0; // @[Xbar.scala:74:9] wire [7:0] auto_anon_out_a_bits_mask_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_a_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_out_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_out_a_valid_0; // @[Xbar.scala:74:9] wire auto_anon_out_d_ready_0; // @[Xbar.scala:74:9] wire in_0_a_ready; // @[Xbar.scala:159:18] assign auto_anon_in_0_a_ready_0 = anonIn_a_ready; // @[Xbar.scala:74:9] wire in_0_a_valid = anonIn_a_valid; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_opcode = anonIn_a_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_param = anonIn_a_bits_param; // @[Xbar.scala:159:18] wire [3:0] in_0_a_bits_size = anonIn_a_bits_size; // @[Xbar.scala:159:18] wire [8:0] _in_0_a_bits_source_T = anonIn_a_bits_source; // @[Xbar.scala:166:55] wire [28:0] in_0_a_bits_address = anonIn_a_bits_address; // @[Xbar.scala:159:18] wire [7:0] in_0_a_bits_mask = anonIn_a_bits_mask; // @[Xbar.scala:159:18] wire [63:0] in_0_a_bits_data = anonIn_a_bits_data; // @[Xbar.scala:159:18] wire in_0_a_bits_corrupt = anonIn_a_bits_corrupt; // @[Xbar.scala:159:18] wire in_0_d_ready = anonIn_d_ready; // @[Xbar.scala:159:18] wire in_0_d_valid; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_valid_0 = anonIn_d_valid; // @[Xbar.scala:74:9] wire [2:0] in_0_d_bits_opcode; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] in_0_d_bits_param; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_param_0 = anonIn_d_bits_param; // @[Xbar.scala:74:9] wire [3:0] in_0_d_bits_size; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_size_0 = anonIn_d_bits_size; // @[Xbar.scala:74:9] wire [8:0] _anonIn_d_bits_source_T; // @[Xbar.scala:156:69] assign auto_anon_in_0_d_bits_source_0 = anonIn_d_bits_source; // @[Xbar.scala:74:9] wire in_0_d_bits_sink; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_sink_0 = anonIn_d_bits_sink; // @[Xbar.scala:74:9] wire in_0_d_bits_denied; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_denied_0 = anonIn_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] in_0_d_bits_data; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_data_0 = anonIn_d_bits_data; // @[Xbar.scala:74:9] wire in_0_d_bits_corrupt; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_corrupt_0 = anonIn_d_bits_corrupt; // @[Xbar.scala:74:9] wire in_1_a_ready; // @[Xbar.scala:159:18] assign auto_anon_in_1_a_ready_0 = anonIn_1_a_ready; // @[Xbar.scala:74:9] wire in_1_a_valid = anonIn_1_a_valid; // @[Xbar.scala:159:18] wire [28:0] in_1_a_bits_address = anonIn_1_a_bits_address; // @[Xbar.scala:159:18] wire [63:0] in_1_a_bits_data = anonIn_1_a_bits_data; // @[Xbar.scala:159:18] wire in_1_d_valid; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_valid_0 = anonIn_1_d_valid; // @[Xbar.scala:74:9] wire [2:0] in_1_d_bits_opcode; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_opcode_0 = anonIn_1_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] in_1_d_bits_param; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_param_0 = anonIn_1_d_bits_param; // @[Xbar.scala:74:9] wire [3:0] in_1_d_bits_size; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_size_0 = anonIn_1_d_bits_size; // @[Xbar.scala:74:9] wire in_1_d_bits_sink; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_sink_0 = anonIn_1_d_bits_sink; // @[Xbar.scala:74:9] wire in_1_d_bits_denied; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_denied_0 = anonIn_1_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] in_1_d_bits_data; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_data_0 = anonIn_1_d_bits_data; // @[Xbar.scala:74:9] wire in_1_d_bits_corrupt; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_corrupt_0 = anonIn_1_d_bits_corrupt; // @[Xbar.scala:74:9] wire out_0_a_ready = anonOut_a_ready; // @[Xbar.scala:216:19] wire out_0_a_valid; // @[Xbar.scala:216:19] assign auto_anon_out_a_valid_0 = anonOut_a_valid; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_opcode; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_param; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_param_0 = anonOut_a_bits_param; // @[Xbar.scala:74:9] wire [3:0] out_0_a_bits_size; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size; // @[Xbar.scala:74:9] wire [9:0] out_0_a_bits_source; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_source_0 = anonOut_a_bits_source; // @[Xbar.scala:74:9] wire [28:0] out_0_a_bits_address; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] out_0_a_bits_mask; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] out_0_a_bits_data; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data; // @[Xbar.scala:74:9] wire out_0_a_bits_corrupt; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[Xbar.scala:74:9] wire out_0_d_ready; // @[Xbar.scala:216:19] assign auto_anon_out_d_ready_0 = anonOut_d_ready; // @[Xbar.scala:74:9] wire out_0_d_valid = anonOut_d_valid; // @[Xbar.scala:216:19] wire [2:0] out_0_d_bits_opcode = anonOut_d_bits_opcode; // @[Xbar.scala:216:19] wire [1:0] out_0_d_bits_param = anonOut_d_bits_param; // @[Xbar.scala:216:19] wire [3:0] out_0_d_bits_size = anonOut_d_bits_size; // @[Xbar.scala:216:19] wire [9:0] out_0_d_bits_source = anonOut_d_bits_source; // @[Xbar.scala:216:19] wire _out_0_d_bits_sink_T = anonOut_d_bits_sink; // @[Xbar.scala:251:53] wire out_0_d_bits_denied = anonOut_d_bits_denied; // @[Xbar.scala:216:19] wire [63:0] out_0_d_bits_data = anonOut_d_bits_data; // @[Xbar.scala:216:19] wire out_0_d_bits_corrupt = anonOut_d_bits_corrupt; // @[Xbar.scala:216:19] wire portsAOI_filtered_0_ready; // @[Xbar.scala:352:24] assign anonIn_a_ready = in_0_a_ready; // @[Xbar.scala:159:18] wire _portsAOI_filtered_0_valid_T_1 = in_0_a_valid; // @[Xbar.scala:159:18, :355:40] wire [2:0] portsAOI_filtered_0_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_0_bits_param = in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsAOI_filtered_0_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [9:0] portsAOI_filtered_0_bits_source = in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [28:0] _requestAIO_T = in_0_a_bits_address; // @[Xbar.scala:159:18] wire [28:0] portsAOI_filtered_0_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [7:0] portsAOI_filtered_0_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [63:0] portsAOI_filtered_0_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_0_bits_corrupt = in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire portsDIO_filtered_0_ready = in_0_d_ready; // @[Xbar.scala:159:18, :352:24] wire portsDIO_filtered_0_valid; // @[Xbar.scala:352:24] assign anonIn_d_valid = in_0_d_valid; // @[Xbar.scala:159:18] wire [2:0] portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:352:24] assign anonIn_d_bits_opcode = in_0_d_bits_opcode; // @[Xbar.scala:159:18] wire [1:0] portsDIO_filtered_0_bits_param; // @[Xbar.scala:352:24] assign anonIn_d_bits_param = in_0_d_bits_param; // @[Xbar.scala:159:18] wire [3:0] portsDIO_filtered_0_bits_size; // @[Xbar.scala:352:24] assign anonIn_d_bits_size = in_0_d_bits_size; // @[Xbar.scala:159:18] wire [9:0] portsDIO_filtered_0_bits_source; // @[Xbar.scala:352:24] wire portsDIO_filtered_0_bits_sink; // @[Xbar.scala:352:24] assign anonIn_d_bits_sink = in_0_d_bits_sink; // @[Xbar.scala:159:18] wire portsDIO_filtered_0_bits_denied; // @[Xbar.scala:352:24] assign anonIn_d_bits_denied = in_0_d_bits_denied; // @[Xbar.scala:159:18] wire [63:0] portsDIO_filtered_0_bits_data; // @[Xbar.scala:352:24] assign anonIn_d_bits_data = in_0_d_bits_data; // @[Xbar.scala:159:18] wire portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:352:24] assign anonIn_d_bits_corrupt = in_0_d_bits_corrupt; // @[Xbar.scala:159:18] wire portsAOI_filtered_1_0_ready; // @[Xbar.scala:352:24] assign anonIn_1_a_ready = in_1_a_ready; // @[Xbar.scala:159:18] wire _portsAOI_filtered_0_valid_T_3 = in_1_a_valid; // @[Xbar.scala:159:18, :355:40] wire [28:0] _requestAIO_T_5 = in_1_a_bits_address; // @[Xbar.scala:159:18] wire [28:0] portsAOI_filtered_1_0_bits_address = in_1_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [63:0] portsAOI_filtered_1_0_bits_data = in_1_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire portsDIO_filtered_1_valid; // @[Xbar.scala:352:24] assign anonIn_1_d_valid = in_1_d_valid; // @[Xbar.scala:159:18] wire [2:0] portsDIO_filtered_1_bits_opcode; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_opcode = in_1_d_bits_opcode; // @[Xbar.scala:159:18] wire [1:0] portsDIO_filtered_1_bits_param; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_param = in_1_d_bits_param; // @[Xbar.scala:159:18] wire [3:0] portsDIO_filtered_1_bits_size; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_size = in_1_d_bits_size; // @[Xbar.scala:159:18] wire [9:0] portsDIO_filtered_1_bits_source; // @[Xbar.scala:352:24] wire portsDIO_filtered_1_bits_sink; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_sink = in_1_d_bits_sink; // @[Xbar.scala:159:18] wire portsDIO_filtered_1_bits_denied; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_denied = in_1_d_bits_denied; // @[Xbar.scala:159:18] wire [63:0] portsDIO_filtered_1_bits_data; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_data = in_1_d_bits_data; // @[Xbar.scala:159:18] wire portsDIO_filtered_1_bits_corrupt; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_corrupt = in_1_d_bits_corrupt; // @[Xbar.scala:159:18] wire [9:0] in_0_d_bits_source; // @[Xbar.scala:159:18] wire [9:0] in_1_d_bits_source; // @[Xbar.scala:159:18] assign in_0_a_bits_source = {1'h0, _in_0_a_bits_source_T}; // @[Xbar.scala:159:18, :166:{29,55}] assign _anonIn_d_bits_source_T = in_0_d_bits_source[8:0]; // @[Xbar.scala:156:69, :159:18] assign anonIn_d_bits_source = _anonIn_d_bits_source_T; // @[Xbar.scala:156:69] wire _out_0_a_valid_T_4; // @[Arbiter.scala:96:24] assign anonOut_a_valid = out_0_a_valid; // @[Xbar.scala:216:19] wire [2:0] _out_0_a_bits_WIRE_opcode; // @[Mux.scala:30:73] assign anonOut_a_bits_opcode = out_0_a_bits_opcode; // @[Xbar.scala:216:19] wire [2:0] _out_0_a_bits_WIRE_param; // @[Mux.scala:30:73] assign anonOut_a_bits_param = out_0_a_bits_param; // @[Xbar.scala:216:19] wire [3:0] _out_0_a_bits_WIRE_size; // @[Mux.scala:30:73] assign anonOut_a_bits_size = out_0_a_bits_size; // @[Xbar.scala:216:19] wire [9:0] _out_0_a_bits_WIRE_source; // @[Mux.scala:30:73] assign anonOut_a_bits_source = out_0_a_bits_source; // @[Xbar.scala:216:19] wire [28:0] _out_0_a_bits_WIRE_address; // @[Mux.scala:30:73] assign anonOut_a_bits_address = out_0_a_bits_address; // @[Xbar.scala:216:19] wire [7:0] _out_0_a_bits_WIRE_mask; // @[Mux.scala:30:73] assign anonOut_a_bits_mask = out_0_a_bits_mask; // @[Xbar.scala:216:19] wire [63:0] _out_0_a_bits_WIRE_data; // @[Mux.scala:30:73] assign anonOut_a_bits_data = out_0_a_bits_data; // @[Xbar.scala:216:19] wire _out_0_a_bits_WIRE_corrupt; // @[Mux.scala:30:73] assign anonOut_a_bits_corrupt = out_0_a_bits_corrupt; // @[Xbar.scala:216:19] wire _portsDIO_out_0_d_ready_WIRE; // @[Mux.scala:30:73] assign anonOut_d_ready = out_0_d_ready; // @[Xbar.scala:216:19] assign portsDIO_filtered_0_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_0_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_0_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [9:0] _requestDOI_uncommonBits_T = out_0_d_bits_source; // @[Xbar.scala:216:19] assign portsDIO_filtered_0_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_0_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_0_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_0_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_0_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] assign out_0_d_bits_sink = _out_0_d_bits_sink_T; // @[Xbar.scala:216:19, :251:53] wire [29:0] _requestAIO_T_1 = {1'h0, _requestAIO_T}; // @[Parameters.scala:137:{31,41}] wire [29:0] _requestAIO_T_6 = {1'h0, _requestAIO_T_5}; // @[Parameters.scala:137:{31,41}] wire [8:0] requestDOI_uncommonBits = _requestDOI_uncommonBits_T[8:0]; // @[Parameters.scala:52:{29,56}] wire _requestDOI_T = out_0_d_bits_source[9]; // @[Xbar.scala:216:19] wire _requestDOI_T_1 = ~_requestDOI_T; // @[Parameters.scala:54:{10,32}] wire _requestDOI_T_3 = _requestDOI_T_1; // @[Parameters.scala:54:{32,67}] wire requestDOI_0_0 = _requestDOI_T_3; // @[Parameters.scala:54:67, :56:48] wire _portsDIO_filtered_0_valid_T = requestDOI_0_0; // @[Xbar.scala:355:54] wire requestDOI_0_1 = out_0_d_bits_source == 10'h200; // @[Xbar.scala:216:19] wire _portsDIO_filtered_1_valid_T = requestDOI_0_1; // @[Xbar.scala:355:54] wire _portsDIO_out_0_d_ready_T_1 = requestDOI_0_1; // @[Mux.scala:30:73] wire [26:0] _beatsAI_decode_T = 27'hFFF << in_0_a_bits_size; // @[package.scala:243:71] wire [11:0] _beatsAI_decode_T_1 = _beatsAI_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _beatsAI_decode_T_2 = ~_beatsAI_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] beatsAI_decode = _beatsAI_decode_T_2[11:3]; // @[package.scala:243:46] wire _beatsAI_opdata_T = in_0_a_bits_opcode[2]; // @[Xbar.scala:159:18] wire beatsAI_opdata = ~_beatsAI_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] beatsAI_0 = beatsAI_opdata ? beatsAI_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] wire [26:0] _beatsDO_decode_T = 27'hFFF << out_0_d_bits_size; // @[package.scala:243:71] wire [11:0] _beatsDO_decode_T_1 = _beatsDO_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _beatsDO_decode_T_2 = ~_beatsDO_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] beatsDO_decode = _beatsDO_decode_T_2[11:3]; // @[package.scala:243:46] wire beatsDO_opdata = out_0_d_bits_opcode[0]; // @[Xbar.scala:216:19] wire [8:0] beatsDO_0 = beatsDO_opdata ? beatsDO_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] wire _filtered_0_ready_T; // @[Arbiter.scala:94:31] assign in_0_a_ready = portsAOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_0_valid; // @[Xbar.scala:352:24] assign portsAOI_filtered_0_valid = _portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire _filtered_0_ready_T_1; // @[Arbiter.scala:94:31] assign in_1_a_ready = portsAOI_filtered_1_0_ready; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24] assign portsAOI_filtered_1_0_valid = _portsAOI_filtered_0_valid_T_3; // @[Xbar.scala:352:24, :355:40] wire _portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:355:40] assign in_0_d_valid = portsDIO_filtered_0_valid; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_opcode = portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_param = portsDIO_filtered_0_bits_param; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_size = portsDIO_filtered_0_bits_size; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_source = portsDIO_filtered_0_bits_source; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_sink = portsDIO_filtered_0_bits_sink; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_denied = portsDIO_filtered_0_bits_denied; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_data = portsDIO_filtered_0_bits_data; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_corrupt = portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire _portsDIO_filtered_1_valid_T_1; // @[Xbar.scala:355:40] assign in_1_d_valid = portsDIO_filtered_1_valid; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_opcode = portsDIO_filtered_1_bits_opcode; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_param = portsDIO_filtered_1_bits_param; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_size = portsDIO_filtered_1_bits_size; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_source = portsDIO_filtered_1_bits_source; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_sink = portsDIO_filtered_1_bits_sink; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_denied = portsDIO_filtered_1_bits_denied; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_data = portsDIO_filtered_1_bits_data; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_corrupt = portsDIO_filtered_1_bits_corrupt; // @[Xbar.scala:159:18, :352:24] assign _portsDIO_filtered_0_valid_T_1 = out_0_d_valid & _portsDIO_filtered_0_valid_T; // @[Xbar.scala:216:19, :355:{40,54}] assign portsDIO_filtered_0_valid = _portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign _portsDIO_filtered_1_valid_T_1 = out_0_d_valid & _portsDIO_filtered_1_valid_T; // @[Xbar.scala:216:19, :355:{40,54}] assign portsDIO_filtered_1_valid = _portsDIO_filtered_1_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire _portsDIO_out_0_d_ready_T = requestDOI_0_0 & portsDIO_filtered_0_ready; // @[Mux.scala:30:73] wire _portsDIO_out_0_d_ready_T_2 = _portsDIO_out_0_d_ready_T | _portsDIO_out_0_d_ready_T_1; // @[Mux.scala:30:73] assign _portsDIO_out_0_d_ready_WIRE = _portsDIO_out_0_d_ready_T_2; // @[Mux.scala:30:73] assign out_0_d_ready = _portsDIO_out_0_d_ready_WIRE; // @[Mux.scala:30:73] reg [8:0] beatsLeft; // @[Arbiter.scala:60:30] wire idle = beatsLeft == 9'h0; // @[Arbiter.scala:60:30, :61:28] wire latch = idle & out_0_a_ready; // @[Xbar.scala:216:19] wire [1:0] _readys_T = {portsAOI_filtered_1_0_valid, portsAOI_filtered_0_valid}; // @[Xbar.scala:352:24] wire [1:0] readys_valid = _readys_T; // @[Arbiter.scala:21:23, :68:51] wire _readys_T_1 = readys_valid == _readys_T; // @[Arbiter.scala:21:23, :22:19, :68:51] wire _readys_T_3 = ~_readys_T_2; // @[Arbiter.scala:22:12] wire _readys_T_4 = ~_readys_T_1; // @[Arbiter.scala:22:{12,19}] reg [1:0] readys_mask; // @[Arbiter.scala:23:23] wire [1:0] _readys_filter_T = ~readys_mask; // @[Arbiter.scala:23:23, :24:30] wire [1:0] _readys_filter_T_1 = readys_valid & _readys_filter_T; // @[Arbiter.scala:21:23, :24:{28,30}] wire [3:0] readys_filter = {_readys_filter_T_1, readys_valid}; // @[Arbiter.scala:21:23, :24:{21,28}] wire [2:0] _readys_unready_T = readys_filter[3:1]; // @[package.scala:262:48] wire [3:0] _readys_unready_T_1 = {readys_filter[3], readys_filter[2:0] | _readys_unready_T}; // @[package.scala:262:{43,48}] wire [3:0] _readys_unready_T_2 = _readys_unready_T_1; // @[package.scala:262:43, :263:17] wire [2:0] _readys_unready_T_3 = _readys_unready_T_2[3:1]; // @[package.scala:263:17] wire [3:0] _readys_unready_T_4 = {readys_mask, 2'h0}; // @[Arbiter.scala:23:23, :25:66] wire [3:0] readys_unready = {1'h0, _readys_unready_T_3} | _readys_unready_T_4; // @[Arbiter.scala:25:{52,58,66}] wire [1:0] _readys_readys_T = readys_unready[3:2]; // @[Arbiter.scala:25:58, :26:29] wire [1:0] _readys_readys_T_1 = readys_unready[1:0]; // @[Arbiter.scala:25:58, :26:48] wire [1:0] _readys_readys_T_2 = _readys_readys_T & _readys_readys_T_1; // @[Arbiter.scala:26:{29,39,48}] wire [1:0] readys_readys = ~_readys_readys_T_2; // @[Arbiter.scala:26:{18,39}] wire [1:0] _readys_T_7 = readys_readys; // @[Arbiter.scala:26:18, :30:11] wire _readys_T_5 = |readys_valid; // @[Arbiter.scala:21:23, :27:27] wire _readys_T_6 = latch & _readys_T_5; // @[Arbiter.scala:27:{18,27}, :62:24] wire [1:0] _readys_mask_T = readys_readys & readys_valid; // @[Arbiter.scala:21:23, :26:18, :28:29] wire [2:0] _readys_mask_T_1 = {_readys_mask_T, 1'h0}; // @[package.scala:253:48] wire [1:0] _readys_mask_T_2 = _readys_mask_T_1[1:0]; // @[package.scala:253:{48,53}] wire [1:0] _readys_mask_T_3 = _readys_mask_T | _readys_mask_T_2; // @[package.scala:253:{43,53}] wire [1:0] _readys_mask_T_4 = _readys_mask_T_3; // @[package.scala:253:43, :254:17] wire _readys_T_8 = _readys_T_7[0]; // @[Arbiter.scala:30:11, :68:76] wire readys_0 = _readys_T_8; // @[Arbiter.scala:68:{27,76}] wire _readys_T_9 = _readys_T_7[1]; // @[Arbiter.scala:30:11, :68:76] wire readys_1 = _readys_T_9; // @[Arbiter.scala:68:{27,76}] wire _winner_T = readys_0 & portsAOI_filtered_0_valid; // @[Xbar.scala:352:24] wire winner_0 = _winner_T; // @[Arbiter.scala:71:{27,69}] wire _winner_T_1 = readys_1 & portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24] wire winner_1 = _winner_T_1; // @[Arbiter.scala:71:{27,69}] wire prefixOR_1 = winner_0; // @[Arbiter.scala:71:27, :76:48] wire _prefixOR_T = prefixOR_1 | winner_1; // @[Arbiter.scala:71:27, :76:48] wire _out_0_a_valid_T = portsAOI_filtered_0_valid | portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24]

Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }

module AsyncResetSynchronizerShiftReg_w4_d3_i0_32( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input [3:0] io_d, // @[ShiftReg.scala:36:14] output [3:0] io_q // @[ShiftReg.scala:36:14] ); wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21] wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14] wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7] wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_1; // @[ShiftReg.scala:48:24] wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_2; // @[ShiftReg.scala:48:24] wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_3; // @[ShiftReg.scala:48:24] wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14] wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14] assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14] assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_297 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_298 output_chain_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_2), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_3), // @[SynchronizerReg.scala:87:41] .io_q (output_1) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_299 output_chain_2 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_4), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_5), // @[SynchronizerReg.scala:87:41] .io_q (output_2) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_300 output_chain_3 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_6), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_7), // @[SynchronizerReg.scala:87:41] .io_q (output_3) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File INToRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import consts._ class INToRecFN(intWidth: Int, expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"INToRecFN_i${intWidth}_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val signedIn = Input(Bool()) val in = Input(Bits(intWidth.W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val intAsRawFloat = rawFloatFromIN(io.signedIn, io.in); val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( intAsRawFloat.expWidth, intWidth, expWidth, sigWidth, flRoundOpt_sigMSBitAlwaysZero | flRoundOpt_neverUnderflows )) roundAnyRawFNToRecFN.io.invalidExc := false.B roundAnyRawFNToRecFN.io.infiniteExc := false.B roundAnyRawFNToRecFN.io.in := intAsRawFloat roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags } File rawFloatFromIN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ object rawFloatFromIN { def apply(signedIn: Bool, in: Bits): RawFloat = { val expWidth = log2Up(in.getWidth) + 1 //*** CHANGE THIS; CAN BE VERY LARGE: val extIntWidth = 1<<(expWidth - 1) val sign = signedIn && in(in.getWidth - 1) val absIn = Mux(sign, -in.asUInt, in.asUInt) val extAbsIn = (0.U(extIntWidth.W) ## absIn)(extIntWidth - 1, 0) val adjustedNormDist = countLeadingZeros(extAbsIn) val sig = (extAbsIn<<adjustedNormDist)( extIntWidth - 1, extIntWidth - in.getWidth) val out = Wire(new RawFloat(expWidth, in.getWidth)) out.isNaN := false.B out.isInf := false.B out.isZero := ! sig(in.getWidth - 1) out.sign := sign out.sExp := (2.U(2.W) ## ~adjustedNormDist(expWidth - 2, 0)).zext out.sig := sig out } }

module INToRecFN_i64_e8_s24_3( // @[INToRecFN.scala:43:7] input io_signedIn, // @[INToRecFN.scala:46:16] input [63:0] io_in, // @[INToRecFN.scala:46:16] input [2:0] io_roundingMode, // @[INToRecFN.scala:46:16] output [32:0] io_out, // @[INToRecFN.scala:46:16] output [4:0] io_exceptionFlags // @[INToRecFN.scala:46:16] ); wire io_signedIn_0 = io_signedIn; // @[INToRecFN.scala:43:7] wire [63:0] io_in_0 = io_in; // @[INToRecFN.scala:43:7] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[INToRecFN.scala:43:7] wire intAsRawFloat_isNaN = 1'h0; // @[rawFloatFromIN.scala:59:23] wire intAsRawFloat_isInf = 1'h0; // @[rawFloatFromIN.scala:59:23] wire io_detectTininess = 1'h1; // @[INToRecFN.scala:43:7] wire [32:0] io_out_0; // @[INToRecFN.scala:43:7] wire [4:0] io_exceptionFlags_0; // @[INToRecFN.scala:43:7] wire _intAsRawFloat_sign_T = io_in_0[63]; // @[rawFloatFromIN.scala:51:34] wire intAsRawFloat_sign = io_signedIn_0 & _intAsRawFloat_sign_T; // @[rawFloatFromIN.scala:51:{29,34}] wire intAsRawFloat_sign_0 = intAsRawFloat_sign; // @[rawFloatFromIN.scala:51:29, :59:23] wire [64:0] _intAsRawFloat_absIn_T = 65'h0 - {1'h0, io_in_0}; // @[rawFloatFromIN.scala:52:31] wire [63:0] _intAsRawFloat_absIn_T_1 = _intAsRawFloat_absIn_T[63:0]; // @[rawFloatFromIN.scala:52:31] wire [63:0] intAsRawFloat_absIn = intAsRawFloat_sign ? _intAsRawFloat_absIn_T_1 : io_in_0; // @[rawFloatFromIN.scala:51:29, :52:{24,31}] wire [127:0] _intAsRawFloat_extAbsIn_T = {64'h0, intAsRawFloat_absIn}; // @[rawFloatFromIN.scala:52:24, :53:44] wire [63:0] intAsRawFloat_extAbsIn = _intAsRawFloat_extAbsIn_T[63:0]; // @[rawFloatFromIN.scala:53:{44,53}] wire _intAsRawFloat_adjustedNormDist_T = intAsRawFloat_extAbsIn[0]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_1 = intAsRawFloat_extAbsIn[1]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_2 = intAsRawFloat_extAbsIn[2]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_3 = intAsRawFloat_extAbsIn[3]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_4 = intAsRawFloat_extAbsIn[4]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_5 = intAsRawFloat_extAbsIn[5]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_6 = intAsRawFloat_extAbsIn[6]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_7 = intAsRawFloat_extAbsIn[7]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_8 = intAsRawFloat_extAbsIn[8]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_9 = intAsRawFloat_extAbsIn[9]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_10 = intAsRawFloat_extAbsIn[10]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_11 = intAsRawFloat_extAbsIn[11]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_12 = intAsRawFloat_extAbsIn[12]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_13 = intAsRawFloat_extAbsIn[13]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_14 = intAsRawFloat_extAbsIn[14]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_15 = intAsRawFloat_extAbsIn[15]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_16 = intAsRawFloat_extAbsIn[16]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_17 = intAsRawFloat_extAbsIn[17]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_18 = intAsRawFloat_extAbsIn[18]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_19 = intAsRawFloat_extAbsIn[19]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_20 = intAsRawFloat_extAbsIn[20]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_21 = intAsRawFloat_extAbsIn[21]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_22 = intAsRawFloat_extAbsIn[22]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_23 = intAsRawFloat_extAbsIn[23]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_24 = intAsRawFloat_extAbsIn[24]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_25 = intAsRawFloat_extAbsIn[25]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_26 = intAsRawFloat_extAbsIn[26]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_27 = intAsRawFloat_extAbsIn[27]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_28 = intAsRawFloat_extAbsIn[28]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_29 = intAsRawFloat_extAbsIn[29]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_30 = intAsRawFloat_extAbsIn[30]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_31 = intAsRawFloat_extAbsIn[31]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_32 = intAsRawFloat_extAbsIn[32]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_33 = intAsRawFloat_extAbsIn[33]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_34 = intAsRawFloat_extAbsIn[34]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_35 = intAsRawFloat_extAbsIn[35]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_36 = intAsRawFloat_extAbsIn[36]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_37 = intAsRawFloat_extAbsIn[37]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_38 = intAsRawFloat_extAbsIn[38]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_39 = intAsRawFloat_extAbsIn[39]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_40 = intAsRawFloat_extAbsIn[40]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_41 = intAsRawFloat_extAbsIn[41]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_42 = intAsRawFloat_extAbsIn[42]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_43 = intAsRawFloat_extAbsIn[43]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_44 = intAsRawFloat_extAbsIn[44]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_45 = intAsRawFloat_extAbsIn[45]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_46 = intAsRawFloat_extAbsIn[46]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_47 = intAsRawFloat_extAbsIn[47]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_48 = intAsRawFloat_extAbsIn[48]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_49 = intAsRawFloat_extAbsIn[49]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_50 = intAsRawFloat_extAbsIn[50]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_51 = intAsRawFloat_extAbsIn[51]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_52 = intAsRawFloat_extAbsIn[52]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_53 = intAsRawFloat_extAbsIn[53]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_54 = intAsRawFloat_extAbsIn[54]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_55 = intAsRawFloat_extAbsIn[55]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_56 = intAsRawFloat_extAbsIn[56]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_57 = intAsRawFloat_extAbsIn[57]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_58 = intAsRawFloat_extAbsIn[58]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_59 = intAsRawFloat_extAbsIn[59]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_60 = intAsRawFloat_extAbsIn[60]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_61 = intAsRawFloat_extAbsIn[61]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_62 = intAsRawFloat_extAbsIn[62]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_63 = intAsRawFloat_extAbsIn[63]; // @[rawFloatFromIN.scala:53:53] wire [5:0] _intAsRawFloat_adjustedNormDist_T_64 = {5'h1F, ~_intAsRawFloat_adjustedNormDist_T_1}; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_65 = _intAsRawFloat_adjustedNormDist_T_2 ? 6'h3D : _intAsRawFloat_adjustedNormDist_T_64; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_66 = _intAsRawFloat_adjustedNormDist_T_3 ? 6'h3C : _intAsRawFloat_adjustedNormDist_T_65; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_67 = _intAsRawFloat_adjustedNormDist_T_4 ? 6'h3B : _intAsRawFloat_adjustedNormDist_T_66; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_68 = _intAsRawFloat_adjustedNormDist_T_5 ? 6'h3A : _intAsRawFloat_adjustedNormDist_T_67; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_69 = _intAsRawFloat_adjustedNormDist_T_6 ? 6'h39 : _intAsRawFloat_adjustedNormDist_T_68; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_70 = _intAsRawFloat_adjustedNormDist_T_7 ? 6'h38 : _intAsRawFloat_adjustedNormDist_T_69; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_71 = _intAsRawFloat_adjustedNormDist_T_8 ? 6'h37 : _intAsRawFloat_adjustedNormDist_T_70; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_72 = _intAsRawFloat_adjustedNormDist_T_9 ? 6'h36 : _intAsRawFloat_adjustedNormDist_T_71; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_73 = _intAsRawFloat_adjustedNormDist_T_10 ? 6'h35 : _intAsRawFloat_adjustedNormDist_T_72; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_74 = _intAsRawFloat_adjustedNormDist_T_11 ? 6'h34 : _intAsRawFloat_adjustedNormDist_T_73; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_75 = _intAsRawFloat_adjustedNormDist_T_12 ? 6'h33 : _intAsRawFloat_adjustedNormDist_T_74; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_76 = _intAsRawFloat_adjustedNormDist_T_13 ? 6'h32 : _intAsRawFloat_adjustedNormDist_T_75; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_77 = _intAsRawFloat_adjustedNormDist_T_14 ? 6'h31 : _intAsRawFloat_adjustedNormDist_T_76; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_78 = _intAsRawFloat_adjustedNormDist_T_15 ? 6'h30 : _intAsRawFloat_adjustedNormDist_T_77; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_79 = _intAsRawFloat_adjustedNormDist_T_16 ? 6'h2F : _intAsRawFloat_adjustedNormDist_T_78; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_80 = _intAsRawFloat_adjustedNormDist_T_17 ? 6'h2E : _intAsRawFloat_adjustedNormDist_T_79; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_81 = _intAsRawFloat_adjustedNormDist_T_18 ? 6'h2D : _intAsRawFloat_adjustedNormDist_T_80; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_82 = _intAsRawFloat_adjustedNormDist_T_19 ? 6'h2C : _intAsRawFloat_adjustedNormDist_T_81; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_83 = _intAsRawFloat_adjustedNormDist_T_20 ? 6'h2B : _intAsRawFloat_adjustedNormDist_T_82; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_84 = _intAsRawFloat_adjustedNormDist_T_21 ? 6'h2A : _intAsRawFloat_adjustedNormDist_T_83; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_85 = _intAsRawFloat_adjustedNormDist_T_22 ? 6'h29 : _intAsRawFloat_adjustedNormDist_T_84; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_86 = _intAsRawFloat_adjustedNormDist_T_23 ? 6'h28 : _intAsRawFloat_adjustedNormDist_T_85; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_87 = _intAsRawFloat_adjustedNormDist_T_24 ? 6'h27 : _intAsRawFloat_adjustedNormDist_T_86; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_88 = _intAsRawFloat_adjustedNormDist_T_25 ? 6'h26 : _intAsRawFloat_adjustedNormDist_T_87; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_89 = _intAsRawFloat_adjustedNormDist_T_26 ? 6'h25 : _intAsRawFloat_adjustedNormDist_T_88; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_90 = _intAsRawFloat_adjustedNormDist_T_27 ? 6'h24 : _intAsRawFloat_adjustedNormDist_T_89; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_91 = _intAsRawFloat_adjustedNormDist_T_28 ? 6'h23 : _intAsRawFloat_adjustedNormDist_T_90; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_92 = _intAsRawFloat_adjustedNormDist_T_29 ? 6'h22 : _intAsRawFloat_adjustedNormDist_T_91; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_93 = _intAsRawFloat_adjustedNormDist_T_30 ? 6'h21 : _intAsRawFloat_adjustedNormDist_T_92; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_94 = _intAsRawFloat_adjustedNormDist_T_31 ? 6'h20 : _intAsRawFloat_adjustedNormDist_T_93; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_95 = _intAsRawFloat_adjustedNormDist_T_32 ? 6'h1F : _intAsRawFloat_adjustedNormDist_T_94; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_96 = _intAsRawFloat_adjustedNormDist_T_33 ? 6'h1E : _intAsRawFloat_adjustedNormDist_T_95; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_97 = _intAsRawFloat_adjustedNormDist_T_34 ? 6'h1D : _intAsRawFloat_adjustedNormDist_T_96; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_98 = _intAsRawFloat_adjustedNormDist_T_35 ? 6'h1C : _intAsRawFloat_adjustedNormDist_T_97; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_99 = _intAsRawFloat_adjustedNormDist_T_36 ? 6'h1B : _intAsRawFloat_adjustedNormDist_T_98; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_100 = _intAsRawFloat_adjustedNormDist_T_37 ? 6'h1A : _intAsRawFloat_adjustedNormDist_T_99; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_101 = _intAsRawFloat_adjustedNormDist_T_38 ? 6'h19 : _intAsRawFloat_adjustedNormDist_T_100; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_102 = _intAsRawFloat_adjustedNormDist_T_39 ? 6'h18 : _intAsRawFloat_adjustedNormDist_T_101; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_103 = _intAsRawFloat_adjustedNormDist_T_40 ? 6'h17 : _intAsRawFloat_adjustedNormDist_T_102; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_104 = _intAsRawFloat_adjustedNormDist_T_41 ? 6'h16 : _intAsRawFloat_adjustedNormDist_T_103; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_105 = _intAsRawFloat_adjustedNormDist_T_42 ? 6'h15 : _intAsRawFloat_adjustedNormDist_T_104; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_106 = _intAsRawFloat_adjustedNormDist_T_43 ? 6'h14 : _intAsRawFloat_adjustedNormDist_T_105; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_107 = _intAsRawFloat_adjustedNormDist_T_44 ? 6'h13 : _intAsRawFloat_adjustedNormDist_T_106; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_108 = _intAsRawFloat_adjustedNormDist_T_45 ? 6'h12 : _intAsRawFloat_adjustedNormDist_T_107; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_109 = _intAsRawFloat_adjustedNormDist_T_46 ? 6'h11 : _intAsRawFloat_adjustedNormDist_T_108; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_110 = _intAsRawFloat_adjustedNormDist_T_47 ? 6'h10 : _intAsRawFloat_adjustedNormDist_T_109; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_111 = _intAsRawFloat_adjustedNormDist_T_48 ? 6'hF : _intAsRawFloat_adjustedNormDist_T_110; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_112 = _intAsRawFloat_adjustedNormDist_T_49 ? 6'hE : _intAsRawFloat_adjustedNormDist_T_111; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_113 = _intAsRawFloat_adjustedNormDist_T_50 ? 6'hD : _intAsRawFloat_adjustedNormDist_T_112; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_114 = _intAsRawFloat_adjustedNormDist_T_51 ? 6'hC : _intAsRawFloat_adjustedNormDist_T_113; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_115 = _intAsRawFloat_adjustedNormDist_T_52 ? 6'hB : _intAsRawFloat_adjustedNormDist_T_114; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_116 = _intAsRawFloat_adjustedNormDist_T_53 ? 6'hA : _intAsRawFloat_adjustedNormDist_T_115; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_117 = _intAsRawFloat_adjustedNormDist_T_54 ? 6'h9 : _intAsRawFloat_adjustedNormDist_T_116; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_118 = _intAsRawFloat_adjustedNormDist_T_55 ? 6'h8 : _intAsRawFloat_adjustedNormDist_T_117; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_119 = _intAsRawFloat_adjustedNormDist_T_56 ? 6'h7 : _intAsRawFloat_adjustedNormDist_T_118; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_120 = _intAsRawFloat_adjustedNormDist_T_57 ? 6'h6 : _intAsRawFloat_adjustedNormDist_T_119; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_121 = _intAsRawFloat_adjustedNormDist_T_58 ? 6'h5 : _intAsRawFloat_adjustedNormDist_T_120; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_122 = _intAsRawFloat_adjustedNormDist_T_59 ? 6'h4 : _intAsRawFloat_adjustedNormDist_T_121; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_123 = _intAsRawFloat_adjustedNormDist_T_60 ? 6'h3 : _intAsRawFloat_adjustedNormDist_T_122; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_124 = _intAsRawFloat_adjustedNormDist_T_61 ? 6'h2 : _intAsRawFloat_adjustedNormDist_T_123; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_125 = _intAsRawFloat_adjustedNormDist_T_62 ? 6'h1 : _intAsRawFloat_adjustedNormDist_T_124; // @[Mux.scala:50:70] wire [5:0] intAsRawFloat_adjustedNormDist = _intAsRawFloat_adjustedNormDist_T_63 ? 6'h0 : _intAsRawFloat_adjustedNormDist_T_125; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_out_sExp_T = intAsRawFloat_adjustedNormDist; // @[Mux.scala:50:70] wire [126:0] _intAsRawFloat_sig_T = {63'h0, intAsRawFloat_extAbsIn} << intAsRawFloat_adjustedNormDist; // @[Mux.scala:50:70] wire [63:0] intAsRawFloat_sig = _intAsRawFloat_sig_T[63:0]; // @[rawFloatFromIN.scala:56:{22,41}] wire _intAsRawFloat_out_isZero_T_1; // @[rawFloatFromIN.scala:62:23] wire [8:0] _intAsRawFloat_out_sExp_T_3; // @[rawFloatFromIN.scala:64:72] wire intAsRawFloat_isZero; // @[rawFloatFromIN.scala:59:23] wire [8:0] intAsRawFloat_sExp; // @[rawFloatFromIN.scala:59:23] wire [64:0] intAsRawFloat_sig_0; // @[rawFloatFromIN.scala:59:23] wire _intAsRawFloat_out_isZero_T = intAsRawFloat_sig[63]; // @[rawFloatFromIN.scala:56:41, :62:28] assign _intAsRawFloat_out_isZero_T_1 = ~_intAsRawFloat_out_isZero_T; // @[rawFloatFromIN.scala:62:{23,28}] assign intAsRawFloat_isZero = _intAsRawFloat_out_isZero_T_1; // @[rawFloatFromIN.scala:59:23, :62:23] wire [5:0] _intAsRawFloat_out_sExp_T_1 = ~_intAsRawFloat_out_sExp_T; // @[rawFloatFromIN.scala:64:{36,53}] wire [7:0] _intAsRawFloat_out_sExp_T_2 = {2'h2, _intAsRawFloat_out_sExp_T_1}; // @[rawFloatFromIN.scala:64:{33,36}] assign _intAsRawFloat_out_sExp_T_3 = {1'h0, _intAsRawFloat_out_sExp_T_2}; // @[rawFloatFromIN.scala:64:{33,72}] assign intAsRawFloat_sExp = _intAsRawFloat_out_sExp_T_3; // @[rawFloatFromIN.scala:59:23, :64:72] assign intAsRawFloat_sig_0 = {1'h0, intAsRawFloat_sig}; // @[rawFloatFromIN.scala:56:41, :59:23, :65:20] RoundAnyRawFNToRecFN_ie7_is64_oe8_os24_3 roundAnyRawFNToRecFN ( // @[INToRecFN.scala:60:15] .io_in_isZero (intAsRawFloat_isZero), // @[rawFloatFromIN.scala:59:23] .io_in_sign (intAsRawFloat_sign_0), // @[rawFloatFromIN.scala:59:23] .io_in_sExp (intAsRawFloat_sExp), // @[rawFloatFromIN.scala:59:23] .io_in_sig (intAsRawFloat_sig_0), // @[rawFloatFromIN.scala:59:23] .io_roundingMode (io_roundingMode_0), // @[INToRecFN.scala:43:7] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[INToRecFN.scala:60:15] assign io_out = io_out_0; // @[INToRecFN.scala:43:7] assign io_exceptionFlags = io_exceptionFlags_0; // @[INToRecFN.scala:43:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File RoundAnyRawFNToRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util.Fill import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundAnyRawFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int, options: Int ) extends RawModule { override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(inExpWidth, inSigWidth)) // (allowed exponent range has limits) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0) val effectiveInSigWidth = if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1 val neverUnderflows = ((options & (flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact) ) != 0) || (inExpWidth < outExpWidth) val neverOverflows = ((options & flRoundOpt_neverOverflows) != 0) || (inExpWidth < outExpWidth) val outNaNExp = BigInt(7)<<(outExpWidth - 2) val outInfExp = BigInt(6)<<(outExpWidth - 2) val outMaxFiniteExp = outInfExp - 1 val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2 val outMinNonzeroExp = outMinNormExp - outSigWidth + 1 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_near_even = (io.roundingMode === round_near_even) val roundingMode_minMag = (io.roundingMode === round_minMag) val roundingMode_min = (io.roundingMode === round_min) val roundingMode_max = (io.roundingMode === round_max) val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag) val roundingMode_odd = (io.roundingMode === round_odd) val roundMagUp = (roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sAdjustedExp = if (inExpWidth < outExpWidth) (io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S )(outExpWidth, 0).zext else if (inExpWidth == outExpWidth) io.in.sExp else io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S val adjustedSig = if (inSigWidth <= outSigWidth + 2) io.in.sig<<(outSigWidth - inSigWidth + 2) else (io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ## io.in.sig(inSigWidth - outSigWidth - 2, 0).orR ) val doShiftSigDown1 = if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2) val common_expOut = Wire(UInt((outExpWidth + 1).W)) val common_fractOut = Wire(UInt((outSigWidth - 1).W)) val common_overflow = Wire(Bool()) val common_totalUnderflow = Wire(Bool()) val common_underflow = Wire(Bool()) val common_inexact = Wire(Bool()) if ( neverOverflows && neverUnderflows && (effectiveInSigWidth <= outSigWidth) ) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1 common_fractOut := Mux(doShiftSigDown1, adjustedSig(outSigWidth + 1, 3), adjustedSig(outSigWidth, 2) ) common_overflow := false.B common_totalUnderflow := false.B common_underflow := false.B common_inexact := false.B } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundMask = if (neverUnderflows) 0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W) else (lowMask( sAdjustedExp(outExpWidth, 0), outMinNormExp - outSigWidth - 1, outMinNormExp ) | doShiftSigDown1) ## 3.U(2.W) val shiftedRoundMask = 0.U(1.W) ## roundMask>>1 val roundPosMask = ~shiftedRoundMask & roundMask val roundPosBit = (adjustedSig & roundPosMask).orR val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR val anyRound = roundPosBit || anyRoundExtra val roundIncr = ((roundingMode_near_even || roundingMode_near_maxMag) && roundPosBit) || (roundMagUp && anyRound) val roundedSig: Bits = Mux(roundIncr, (((adjustedSig | roundMask)>>2) +& 1.U) & ~Mux(roundingMode_near_even && roundPosBit && ! anyRoundExtra, roundMask>>1, 0.U((outSigWidth + 2).W) ), (adjustedSig & ~roundMask)>>2 | Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U) ) //*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //*** M.S. BIT OF SUBNORMAL SIG? val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext common_expOut := sRoundedExp(outExpWidth, 0) common_fractOut := Mux(doShiftSigDown1, roundedSig(outSigWidth - 1, 1), roundedSig(outSigWidth - 2, 0) ) common_overflow := (if (neverOverflows) false.B else //*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?: (sRoundedExp>>(outExpWidth - 1) >= 3.S)) common_totalUnderflow := (if (neverUnderflows) false.B else //*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?: (sRoundedExp < outMinNonzeroExp.S)) val unboundedRange_roundPosBit = Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1)) val unboundedRange_anyRound = (doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR val unboundedRange_roundIncr = ((roundingMode_near_even || roundingMode_near_maxMag) && unboundedRange_roundPosBit) || (roundMagUp && unboundedRange_anyRound) val roundCarry = Mux(doShiftSigDown1, roundedSig(outSigWidth + 1), roundedSig(outSigWidth) ) common_underflow := (if (neverUnderflows) false.B else common_totalUnderflow || //*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //*** M.S. BIT OF SUBNORMAL SIG? (anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) && Mux(doShiftSigDown1, roundMask(3), roundMask(2)) && ! ((io.detectTininess === tininess_afterRounding) && ! Mux(doShiftSigDown1, roundMask(4), roundMask(3) ) && roundCarry && roundPosBit && unboundedRange_roundIncr))) common_inexact := common_totalUnderflow || anyRound } //------------------------------------------------------------------------ //------------------------------------------------------------------------ val isNaNOut = io.invalidExc || io.in.isNaN val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero val overflow = commonCase && common_overflow val underflow = commonCase && common_underflow val inexact = overflow || (commonCase && common_inexact) val overflow_roundMagUp = roundingMode_near_even || roundingMode_near_maxMag || roundMagUp val pegMinNonzeroMagOut = commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd) val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp val notNaN_isInfOut = notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp) val signOut = Mux(isNaNOut, false.B, io.in.sign) val expOut = (common_expOut & ~Mux(io.in.isZero || common_totalUnderflow, (BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMinNonzeroMagOut, ~outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMaxFiniteMagOut, (BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W), 0.U ) & ~Mux(notNaN_isInfOut, (BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U )) | Mux(pegMinNonzeroMagOut, outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) | Mux(pegMaxFiniteMagOut, outMaxFiniteExp.U((outExpWidth + 1).W), 0.U ) | Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) | Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U) val fractOut = Mux(isNaNOut || io.in.isZero || common_totalUnderflow, Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U), common_fractOut ) | Fill(outSigWidth - 1, pegMaxFiniteMagOut) io.out := signOut ## expOut ## fractOut io.exceptionFlags := io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int) extends RawModule { override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(expWidth, sigWidth + 2)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( expWidth, sigWidth + 2, expWidth, sigWidth, options)) roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc roundAnyRawFNToRecFN.io.in := io.in roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags }

module RoundRawFNToRecFN_e8_s24_21( // @[RoundAnyRawFNToRecFN.scala:295:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_21 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15] .io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[RoundAnyRawFNToRecFN.scala:310:15] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] endmodule

Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }

module AsyncValidSync_176( // @[AsyncQueue.scala:58:7] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in = 1'h1; // @[ShiftReg.scala:45:23] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_191 io_out_source_valid_0 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands */ class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def *(t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def *(t: UInt) = self * t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros | ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def *(t: SInt) = self * t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros | ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid || output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def *(t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def *(t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }

module PE_314( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid, // @[PE.scala:35:14] output io_bad_dataflow // @[PE.scala:35:14] ); wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24] wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [31:0] c1; // @[PE.scala:70:15] wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [31:0] c2; // @[PE.scala:71:15] wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25] wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61] wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38] wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38] assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16] assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10] wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10] c1 <= _GEN_7; // @[PE.scala:70:15, :124:10] if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30] end else // @[PE.scala:71:15, :118:101, :119:30] c2 <= _GEN_7; // @[PE.scala:71:15, :124:10] end else begin // @[PE.scala:31:7] c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10] c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10] end last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] end always @(posedge) MacUnit_58 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24] .io_out_d (_mac_unit_io_out_d) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands */ class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def *(t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def *(t: UInt) = self * t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros | ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def *(t: SInt) = self * t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros | ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid || output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def *(t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def *(t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }

module PE_438( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_182 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File util.scala: //****************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v4.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v4.common.{MicroOp} import boom.v4.exu.{BrUpdateInfo} /** * Object to XOR fold a input register of fullLength into a compressedLength. */ object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /** * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks */ object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, flush: Bool, uop: MicroOp): Bool = { return apply(brupdate, flush, uop.br_mask) } def apply(brupdate: BrUpdateInfo, flush: Bool, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) || flush } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: T): Bool = { return apply(brupdate, flush, bundle.uop) } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Bool = { return apply(brupdate, flush, bundle.bits) } } /** * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. */ object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /** * Object to return a BR mask given a MicroOp mask and old BR mask. */ object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, flush, bundle.bits.uop.br_mask) out } } /** * Object to check if at least 1 bit matches in two masks */ object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /** * Object to clear one bit in a mask given an index */ object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /** * Object to shift a register over by one bit and concat a new one */ object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /** * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. */ object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /** * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. */ object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc | (b-1).U) } } /** * Object to rotate a signal left by one */ object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /** * Object to sext a value to a particular length. */ object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /** * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. */ object ImmGen { import boom.v4.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U, IS_N} def apply(i: UInt, isel: UInt): UInt = { val ip = Mux(isel === IS_N, 0.U(LONGEST_IMM_SZ.W), i) val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0) } } /** * Object to see if an instruction is a JALR. */ object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /** * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). */ object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /** * Object to return the lowest bit position after the head. */ object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /** * Object to determine whether queue * index i0 is older than index i1. */ object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } object IsYoungerMask { def apply(i: UInt, head: UInt, n: Integer): UInt = { val hi_mask = ~MaskLower(UIntToOH(i)(n-1,0)) val lo_mask = ~MaskUpper(UIntToOH(head)(n-1,0)) Mux(i < head, hi_mask & lo_mask, hi_mask | lo_mask)(n-1,0) } } /** * Set all bits at or below the highest order '1'. */ object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_|_) } } /** * Set all bits at or above the lowest order '1'. */ object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_) } } /** * Transpose a matrix of Chisel Vecs. */ object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /** * N-wide one-hot priority encoder. */ object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /** * Connect the first k of n valid input interfaces to k output interfaces. */ class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_)) val out_valids = sels map (col => col.reduce(_||_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /** * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). */ class BranchKillableQueue[T <: boom.v4.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v4.common.MicroOp => Bool = u => true.B, fastDeq: Boolean = false) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) if (fastDeq && entries > 1) { // Pipeline dequeue selection so the mux gets an entire cycle val main = Module(new BranchKillableQueue(gen, entries-1, flush_fn, false)) val out_reg = Reg(gen) val out_valid = RegInit(false.B) val out_uop = Reg(new MicroOp) main.io.enq <> io.enq main.io.brupdate := io.brupdate main.io.flush := io.flush io.empty := main.io.empty && !out_valid io.count := main.io.count + out_valid io.deq.valid := out_valid io.deq.bits := out_reg io.deq.bits.uop := out_uop out_uop := UpdateBrMask(io.brupdate, out_uop) out_valid := out_valid && !IsKilledByBranch(io.brupdate, false.B, out_uop) && !(io.flush && flush_fn(out_uop)) main.io.deq.ready := false.B when (io.deq.fire || !out_valid) { out_valid := main.io.deq.valid && !IsKilledByBranch(io.brupdate, false.B, main.io.deq.bits.uop) && !(io.flush && flush_fn(main.io.deq.bits.uop)) out_reg := main.io.deq.bits out_uop := UpdateBrMask(io.brupdate, main.io.deq.bits.uop) main.io.deq.ready := true.B } } else { val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire && !IsKilledByBranch(io.brupdate, false.B, io.enq.bits.uop) && !(io.flush && flush_fn(io.enq.bits.uop))) val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, false.B, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) io.deq.bits := out val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /** * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" */ def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) */ def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) */ def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) */ def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /** * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line */ def apply(strs: String*)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } class BranchKillablePipeline[T <: boom.v4.common.HasBoomUOP](gen: T, stages: Int) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val req = Input(Valid(gen)) val flush = Input(Bool()) val brupdate = Input(new BrUpdateInfo) val resp = Output(Vec(stages, Valid(gen))) }) require(stages > 0) val uops = Reg(Vec(stages, Valid(gen))) uops(0).valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.flush, io.req.bits) uops(0).bits := UpdateBrMask(io.brupdate, io.req.bits) for (i <- 1 until stages) { uops(i).valid := uops(i-1).valid && !IsKilledByBranch(io.brupdate, io.flush, uops(i-1).bits) uops(i).bits := UpdateBrMask(io.brupdate, uops(i-1).bits) } for (i <- 0 until stages) { when (reset.asBool) { uops(i).valid := false.B } } io.resp := uops } File tage.scala: package boom.v4.ifu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import boom.v4.common._ import boom.v4.util.{BoomCoreStringPrefix, MaskLower, WrapInc} import scala.math.min class TageResp extends Bundle { val ctr = UInt(3.W) val u = UInt(2.W) } class TageTable(val nRows: Int, val tagSz: Int, val histLength: Int, val uBitPeriod: Int, val singlePorted: Boolean) (implicit p: Parameters) extends BoomModule()(p) with HasBoomFrontendParameters { require(histLength <= globalHistoryLength) val nWrBypassEntries = 2 val io = IO( new Bundle { val f1_req_valid = Input(Bool()) val f1_req_pc = Input(UInt(vaddrBitsExtended.W)) val f1_req_ghist = Input(UInt(globalHistoryLength.W)) val f2_resp = Output(Vec(bankWidth, Valid(new TageResp))) val update_mask = Input(Vec(bankWidth, Bool())) val update_taken = Input(Vec(bankWidth, Bool())) val update_alloc = Input(Vec(bankWidth, Bool())) val update_old_ctr = Input(Vec(bankWidth, UInt(3.W))) val update_pc = Input(UInt()) val update_hist = Input(UInt()) val update_u_mask = Input(Vec(bankWidth, Bool())) val update_u = Input(Vec(bankWidth, UInt(2.W))) }) def compute_folded_hist(hist: UInt, l: Int) = { val nChunks = (histLength + l - 1) / l val hist_chunks = (0 until nChunks) map {i => hist(min((i+1)*l, histLength)-1, i*l) } hist_chunks.reduce(_^_) } def compute_tag_and_hash(unhashed_idx: UInt, hist: UInt) = { val idx_history = compute_folded_hist(hist, log2Ceil(nRows)) val idx = (unhashed_idx ^ idx_history)(log2Ceil(nRows)-1,0) val tag_history = compute_folded_hist(hist, tagSz) val tag = ((unhashed_idx >> log2Ceil(nRows)) ^ tag_history)(tagSz-1,0) (idx, tag) } def inc_ctr(ctr: UInt, taken: Bool): UInt = { Mux(!taken, Mux(ctr === 0.U, 0.U, ctr - 1.U), Mux(ctr === 7.U, 7.U, ctr + 1.U)) } val doing_reset = RegInit(true.B) val reset_idx = RegInit(0.U(log2Ceil(nRows).W)) reset_idx := reset_idx + doing_reset when (reset_idx === (nRows-1).U) { doing_reset := false.B } class TageEntry extends Bundle { val valid = Bool() // TODO: Remove this valid bit val tag = UInt(tagSz.W) val ctr = UInt(3.W) } val tageEntrySz = 1 + tagSz + 3 val (s1_hashed_idx, s1_tag) = compute_tag_and_hash(fetchIdx(io.f1_req_pc), io.f1_req_ghist) val us = SyncReadMem(nRows, Vec(bankWidth*2, Bool())) val table = SyncReadMem(nRows, Vec(bankWidth, UInt(tageEntrySz.W))) us.suggestName(s"tage_u_${histLength}") table.suggestName(s"tage_table_${histLength}") val mems = Seq((f"tage_l$histLength", nRows, bankWidth * tageEntrySz)) val s2_tag = RegNext(s1_tag) val s2_req_rtage = Wire(Vec(bankWidth, new TageEntry)) val s2_req_rus = Wire(Vec(bankWidth*2, Bool())) val s2_req_rhits = VecInit(s2_req_rtage.map(e => e.valid && e.tag === s2_tag && !doing_reset)) for (w <- 0 until bankWidth) { // This bit indicates the TAGE table matched here io.f2_resp(w).valid := s2_req_rhits(w) io.f2_resp(w).bits.u := Cat(s2_req_rus(w*2+1), s2_req_rus(w*2)) io.f2_resp(w).bits.ctr := s2_req_rtage(w).ctr } val clear_u_ctr = RegInit(0.U((log2Ceil(uBitPeriod) + log2Ceil(nRows) + 1).W)) when (doing_reset) { clear_u_ctr := 1.U } .otherwise { clear_u_ctr := clear_u_ctr + 1.U } val doing_clear_u = clear_u_ctr(log2Ceil(uBitPeriod)-1,0) === 0.U val clear_u_hi = clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 1.U val clear_u_lo = clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 0.U val clear_u_idx = clear_u_ctr >> log2Ceil(uBitPeriod) val clear_u_mask = VecInit((0 until bankWidth*2) map { i => if (i % 2 == 0) clear_u_lo else clear_u_hi }).asUInt val (update_idx, update_tag) = compute_tag_and_hash(fetchIdx(io.update_pc), io.update_hist) val update_wdata = Wire(Vec(bankWidth, new TageEntry)) val wen = WireInit(doing_reset || io.update_mask.reduce(_||_)) val rdata = if (singlePorted) table.read(s1_hashed_idx, !wen && io.f1_req_valid) else table.read(s1_hashed_idx, io.f1_req_valid) when (RegNext(wen) && singlePorted.B) { s2_req_rtage := 0.U.asTypeOf(Vec(bankWidth, new TageEntry)) } .otherwise { s2_req_rtage := VecInit(rdata.map(_.asTypeOf(new TageEntry))) } when (wen) { val widx = Mux(doing_reset, reset_idx, update_idx) val wdata = Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(tageEntrySz.W) }), VecInit(update_wdata.map(_.asUInt))) val wmask = Mux(doing_reset, ~(0.U(bankWidth.W)), io.update_mask.asUInt) table.write(widx, wdata, wmask.asBools) } val update_u_mask = VecInit((0 until bankWidth*2) map {i => io.update_u_mask(i / 2)}) val update_u_wen = WireInit(doing_reset || doing_clear_u || update_u_mask.reduce(_||_)) val u_rdata = if (singlePorted) { us.read(s1_hashed_idx, !update_u_wen && io.f1_req_valid) } else { us.read(s1_hashed_idx, io.f1_req_valid) } s2_req_rus := u_rdata when (update_u_wen) { val widx = Mux(doing_reset, reset_idx, Mux(doing_clear_u, clear_u_idx, update_idx)) val wdata = Mux(doing_reset || doing_clear_u, VecInit(0.U((bankWidth*2).W).asBools), VecInit(io.update_u.asUInt.asBools)) val wmask = Mux(doing_reset, ~(0.U((bankWidth*2).W)), Mux(doing_clear_u, clear_u_mask, update_u_mask.asUInt)) us.write(widx, wdata, wmask.asBools) } val wrbypass_tags = Reg(Vec(nWrBypassEntries, UInt(tagSz.W))) val wrbypass_idxs = Reg(Vec(nWrBypassEntries, UInt(log2Ceil(nRows).W))) val wrbypass = Reg(Vec(nWrBypassEntries, Vec(bankWidth, UInt(3.W)))) val wrbypass_enq_idx = RegInit(0.U(log2Ceil(nWrBypassEntries).W)) val wrbypass_hits = VecInit((0 until nWrBypassEntries) map { i => !doing_reset && wrbypass_tags(i) === update_tag && wrbypass_idxs(i) === update_idx }) val wrbypass_hit = wrbypass_hits.reduce(_||_) val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits) for (w <- 0 until bankWidth) { update_wdata(w).ctr := Mux(io.update_alloc(w), Mux(io.update_taken(w), 4.U, 3.U ), Mux(wrbypass_hit, inc_ctr(wrbypass(wrbypass_hit_idx)(w), io.update_taken(w)), inc_ctr(io.update_old_ctr(w), io.update_taken(w)) ) ) update_wdata(w).valid := true.B update_wdata(w).tag := update_tag } when (io.update_mask.reduce(_||_)) { when (wrbypass_hits.reduce(_||_)) { wrbypass(wrbypass_hit_idx) := VecInit(update_wdata.map(_.ctr)) } .otherwise { wrbypass (wrbypass_enq_idx) := VecInit(update_wdata.map(_.ctr)) wrbypass_tags(wrbypass_enq_idx) := update_tag wrbypass_idxs(wrbypass_enq_idx) := update_idx wrbypass_enq_idx := WrapInc(wrbypass_enq_idx, nWrBypassEntries) } } } case class BoomTageParams( // nSets, histLen, tagSz tableInfo: Seq[Tuple3[Int, Int, Int]] = Seq(( 128, 2, 7), ( 128, 4, 7), ( 256, 8, 8), ( 256, 16, 8), ( 128, 32, 9), ( 128, 64, 9)), uBitPeriod: Int = 2048, singlePorted: Boolean = false ) class TageBranchPredictorBank(params: BoomTageParams = BoomTageParams())(implicit p: Parameters) extends BranchPredictorBank()(p) { val tageUBitPeriod = params.uBitPeriod val tageNTables = params.tableInfo.size class TageMeta extends Bundle { val provider = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W))) val alt_differs = Vec(bankWidth, Output(Bool())) val provider_u = Vec(bankWidth, Output(UInt(2.W))) val provider_ctr = Vec(bankWidth, Output(UInt(3.W))) val allocate = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W))) } val f3_meta = Wire(new TageMeta) override val metaSz = f3_meta.asUInt.getWidth require(metaSz <= bpdMaxMetaLength) def inc_u(u: UInt, alt_differs: Bool, mispredict: Bool): UInt = { Mux(!alt_differs, u, Mux(mispredict, Mux(u === 0.U, 0.U, u - 1.U), Mux(u === 3.U, 3.U, u + 1.U))) } val tt = params.tableInfo map { case (n, l, s) => { val t = Module(new TageTable(n, s, l, params.uBitPeriod, params.singlePorted)) t.io.f1_req_valid := RegNext(io.f0_valid) t.io.f1_req_pc := RegNext(bankAlign(io.f0_pc)) t.io.f1_req_ghist := io.f1_ghist (t, t.mems) } } val tables = tt.map(_._1) val mems = tt.map(_._2).flatten val f2_resps = VecInit(tables.map(_.io.f2_resp)) val f3_resps = RegNext(f2_resps) val s1_update_meta = s1_update.bits.meta.asTypeOf(new TageMeta) val s1_update_mispredict_mask = UIntToOH(s1_update.bits.cfi_idx.bits) & Fill(bankWidth, s1_update.bits.cfi_mispredicted) val s1_update_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, Bool())))) val s1_update_u_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, UInt(1.W))))) val s1_update_taken = Wire(Vec(tageNTables, Vec(bankWidth, Bool()))) val s1_update_old_ctr = Wire(Vec(tageNTables, Vec(bankWidth, UInt(3.W)))) val s1_update_alloc = Wire(Vec(tageNTables, Vec(bankWidth, Bool()))) val s1_update_u = Wire(Vec(tageNTables, Vec(bankWidth, UInt(2.W)))) s1_update_taken := DontCare s1_update_old_ctr := DontCare s1_update_alloc := DontCare s1_update_u := DontCare for (w <- 0 until bankWidth) { var s2_provided = false.B var s2_provider = 0.U var s2_alt_provided = false.B var s2_alt_provider = 0.U for (i <- 0 until tageNTables) { val hit = f2_resps(i)(w).valid s2_alt_provided = s2_alt_provided || (s2_provided && hit) s2_provided = s2_provided || hit s2_alt_provider = Mux(hit, s2_provider, s2_alt_provider) s2_provider = Mux(hit, i.U, s2_provider) } val s3_provided = RegNext(s2_provided) val s3_provider = RegNext(s2_provider) val s3_alt_provided = RegNext(s2_alt_provided) val s3_alt_provider = RegNext(s2_alt_provider) val prov = RegNext(f2_resps(s2_provider)(w).bits) val alt = RegNext(f2_resps(s2_alt_provider)(w).bits) io.resp.f3(w).taken := Mux(s3_provided, Mux(prov.ctr === 3.U || prov.ctr === 4.U, Mux(s3_alt_provided, alt.ctr(2), io.resp_in(0).f3(w).taken), prov.ctr(2)), io.resp_in(0).f3(w).taken ) f3_meta.provider(w).valid := s3_provided f3_meta.provider(w).bits := s3_provider f3_meta.alt_differs(w) := s3_alt_provided && alt.ctr(2) =/= io.resp.f3(w).taken f3_meta.provider_u(w) := prov.u f3_meta.provider_ctr(w) := prov.ctr // Create a mask of tables which did not hit our query, and also contain useless entries // and also uses a longer history than the provider val allocatable_slots = ( VecInit(f3_resps.map(r => !r(w).valid && r(w).bits.u === 0.U)).asUInt & ~(MaskLower(UIntToOH(f3_meta.provider(w).bits)) & Fill(tageNTables, f3_meta.provider(w).valid)) ) val alloc_lfsr = random.LFSR(tageNTables max 2) val first_entry = PriorityEncoder(allocatable_slots) val masked_entry = PriorityEncoder(allocatable_slots & alloc_lfsr) val alloc_entry = Mux(allocatable_slots(masked_entry), masked_entry, first_entry) f3_meta.allocate(w).valid := allocatable_slots =/= 0.U f3_meta.allocate(w).bits := alloc_entry val update_was_taken = (s1_update.bits.cfi_idx.valid && (s1_update.bits.cfi_idx.bits === w.U) && s1_update.bits.cfi_taken) when (s1_update.bits.br_mask(w) && s1_update.valid && s1_update.bits.is_commit_update) { when (s1_update_meta.provider(w).valid) { val provider = s1_update_meta.provider(w).bits s1_update_mask(provider)(w) := true.B s1_update_u_mask(provider)(w) := true.B val new_u = inc_u(s1_update_meta.provider_u(w), s1_update_meta.alt_differs(w), s1_update_mispredict_mask(w)) s1_update_u (provider)(w) := new_u s1_update_taken (provider)(w) := update_was_taken s1_update_old_ctr(provider)(w) := s1_update_meta.provider_ctr(w) s1_update_alloc (provider)(w) := false.B } } } when (s1_update.valid && s1_update.bits.is_commit_update && s1_update.bits.cfi_mispredicted && s1_update.bits.cfi_idx.valid) { val idx = s1_update.bits.cfi_idx.bits val allocate = s1_update_meta.allocate(idx) when (allocate.valid) { s1_update_mask (allocate.bits)(idx) := true.B s1_update_taken(allocate.bits)(idx) := s1_update.bits.cfi_taken s1_update_alloc(allocate.bits)(idx) := true.B s1_update_u_mask(allocate.bits)(idx) := true.B s1_update_u (allocate.bits)(idx) := 0.U } .otherwise { val provider = s1_update_meta.provider(idx) val decr_mask = Mux(provider.valid, ~MaskLower(UIntToOH(provider.bits)), 0.U) for (i <- 0 until tageNTables) { when (decr_mask(i)) { s1_update_u_mask(i)(idx) := true.B s1_update_u (i)(idx) := 0.U } } } } for (i <- 0 until tageNTables) { for (w <- 0 until bankWidth) { tables(i).io.update_mask(w) := RegNext(s1_update_mask(i)(w)) tables(i).io.update_taken(w) := RegNext(s1_update_taken(i)(w)) tables(i).io.update_alloc(w) := RegNext(s1_update_alloc(i)(w)) tables(i).io.update_old_ctr(w) := RegNext(s1_update_old_ctr(i)(w)) tables(i).io.update_u_mask(w) := RegNext(s1_update_u_mask(i)(w)) tables(i).io.update_u(w) := RegNext(s1_update_u(i)(w)) } tables(i).io.update_pc := RegNext(s1_update.bits.pc) tables(i).io.update_hist := RegNext(s1_update.bits.ghist) } //io.f3_meta := Cat(f3_meta.asUInt, micro.io.f3_meta(micro.metaSz-1,0), base.io.f3_meta(base.metaSz-1, 0)) io.f3_meta := f3_meta.asUInt }

module TageTable_5( // @[tage.scala:24:7] input clock, // @[tage.scala:24:7] input reset, // @[tage.scala:24:7] input io_f1_req_valid, // @[tage.scala:31:14] input [39:0] io_f1_req_pc, // @[tage.scala:31:14] input [63:0] io_f1_req_ghist, // @[tage.scala:31:14] output io_f2_resp_0_valid, // @[tage.scala:31:14] output [2:0] io_f2_resp_0_bits_ctr, // @[tage.scala:31:14] output [1:0] io_f2_resp_0_bits_u, // @[tage.scala:31:14] output io_f2_resp_1_valid, // @[tage.scala:31:14] output [2:0] io_f2_resp_1_bits_ctr, // @[tage.scala:31:14] output [1:0] io_f2_resp_1_bits_u, // @[tage.scala:31:14] output io_f2_resp_2_valid, // @[tage.scala:31:14] output [2:0] io_f2_resp_2_bits_ctr, // @[tage.scala:31:14] output [1:0] io_f2_resp_2_bits_u, // @[tage.scala:31:14] output io_f2_resp_3_valid, // @[tage.scala:31:14] output [2:0] io_f2_resp_3_bits_ctr, // @[tage.scala:31:14] output [1:0] io_f2_resp_3_bits_u, // @[tage.scala:31:14] input io_update_mask_0, // @[tage.scala:31:14] input io_update_mask_1, // @[tage.scala:31:14] input io_update_mask_2, // @[tage.scala:31:14] input io_update_mask_3, // @[tage.scala:31:14] input io_update_taken_0, // @[tage.scala:31:14] input io_update_taken_1, // @[tage.scala:31:14] input io_update_taken_2, // @[tage.scala:31:14] input io_update_taken_3, // @[tage.scala:31:14] input io_update_alloc_0, // @[tage.scala:31:14] input io_update_alloc_1, // @[tage.scala:31:14] input io_update_alloc_2, // @[tage.scala:31:14] input io_update_alloc_3, // @[tage.scala:31:14] input [2:0] io_update_old_ctr_0, // @[tage.scala:31:14] input [2:0] io_update_old_ctr_1, // @[tage.scala:31:14] input [2:0] io_update_old_ctr_2, // @[tage.scala:31:14] input [2:0] io_update_old_ctr_3, // @[tage.scala:31:14] input [39:0] io_update_pc, // @[tage.scala:31:14] input [63:0] io_update_hist, // @[tage.scala:31:14] input io_update_u_mask_0, // @[tage.scala:31:14] input io_update_u_mask_1, // @[tage.scala:31:14] input io_update_u_mask_2, // @[tage.scala:31:14] input io_update_u_mask_3, // @[tage.scala:31:14] input [1:0] io_update_u_0, // @[tage.scala:31:14] input [1:0] io_update_u_1, // @[tage.scala:31:14] input [1:0] io_update_u_2, // @[tage.scala:31:14] input [1:0] io_update_u_3 // @[tage.scala:31:14] ); wire [51:0] _tage_table_64_R0_data; // @[tage.scala:90:27] wire [7:0] _tage_u_64_R0_data; // @[tage.scala:89:27] wire io_f1_req_valid_0 = io_f1_req_valid; // @[tage.scala:24:7] wire [39:0] io_f1_req_pc_0 = io_f1_req_pc; // @[tage.scala:24:7] wire [63:0] io_f1_req_ghist_0 = io_f1_req_ghist; // @[tage.scala:24:7] wire io_update_mask_0_0 = io_update_mask_0; // @[tage.scala:24:7] wire io_update_mask_1_0 = io_update_mask_1; // @[tage.scala:24:7] wire io_update_mask_2_0 = io_update_mask_2; // @[tage.scala:24:7] wire io_update_mask_3_0 = io_update_mask_3; // @[tage.scala:24:7] wire io_update_taken_0_0 = io_update_taken_0; // @[tage.scala:24:7] wire io_update_taken_1_0 = io_update_taken_1; // @[tage.scala:24:7] wire io_update_taken_2_0 = io_update_taken_2; // @[tage.scala:24:7] wire io_update_taken_3_0 = io_update_taken_3; // @[tage.scala:24:7] wire io_update_alloc_0_0 = io_update_alloc_0; // @[tage.scala:24:7] wire io_update_alloc_1_0 = io_update_alloc_1; // @[tage.scala:24:7] wire io_update_alloc_2_0 = io_update_alloc_2; // @[tage.scala:24:7] wire io_update_alloc_3_0 = io_update_alloc_3; // @[tage.scala:24:7] wire [2:0] io_update_old_ctr_0_0 = io_update_old_ctr_0; // @[tage.scala:24:7] wire [2:0] io_update_old_ctr_1_0 = io_update_old_ctr_1; // @[tage.scala:24:7] wire [2:0] io_update_old_ctr_2_0 = io_update_old_ctr_2; // @[tage.scala:24:7] wire [2:0] io_update_old_ctr_3_0 = io_update_old_ctr_3; // @[tage.scala:24:7] wire [39:0] io_update_pc_0 = io_update_pc; // @[tage.scala:24:7] wire [63:0] io_update_hist_0 = io_update_hist; // @[tage.scala:24:7] wire io_update_u_mask_0_0 = io_update_u_mask_0; // @[tage.scala:24:7] wire io_update_u_mask_1_0 = io_update_u_mask_1; // @[tage.scala:24:7] wire io_update_u_mask_2_0 = io_update_u_mask_2; // @[tage.scala:24:7] wire io_update_u_mask_3_0 = io_update_u_mask_3; // @[tage.scala:24:7] wire [1:0] io_update_u_0_0 = io_update_u_0; // @[tage.scala:24:7] wire [1:0] io_update_u_1_0 = io_update_u_1; // @[tage.scala:24:7] wire [1:0] io_update_u_2_0 = io_update_u_2; // @[tage.scala:24:7] wire [1:0] io_update_u_3_0 = io_update_u_3; // @[tage.scala:24:7] wire update_wdata_0_valid = 1'h1; // @[tage.scala:120:26] wire update_wdata_1_valid = 1'h1; // @[tage.scala:120:26] wire update_wdata_2_valid = 1'h1; // @[tage.scala:120:26] wire update_wdata_3_valid = 1'h1; // @[tage.scala:120:26] wire [12:0] _wdata_WIRE_0 = 13'h0; // @[tage.scala:130:41] wire [12:0] _wdata_WIRE_1 = 13'h0; // @[tage.scala:130:41] wire [12:0] _wdata_WIRE_2 = 13'h0; // @[tage.scala:130:41] wire [12:0] _wdata_WIRE_3 = 13'h0; // @[tage.scala:130:41] wire [3:0] _wmask_T = 4'hF; // @[tage.scala:131:34] wire _wdata_WIRE_2_0 = 1'h0; // @[tage.scala:145:58] wire _wdata_WIRE_2_1 = 1'h0; // @[tage.scala:145:58] wire _wdata_WIRE_2_2 = 1'h0; // @[tage.scala:145:58] wire _wdata_WIRE_2_3 = 1'h0; // @[tage.scala:145:58] wire _wdata_WIRE_2_4 = 1'h0; // @[tage.scala:145:58] wire _wdata_WIRE_2_5 = 1'h0; // @[tage.scala:145:58] wire _wdata_WIRE_2_6 = 1'h0; // @[tage.scala:145:58] wire _wdata_WIRE_2_7 = 1'h0; // @[tage.scala:145:58] wire [7:0] _wmask_T_2 = 8'hFF; // @[tage.scala:146:34] wire s2_req_rhits_0; // @[tage.scala:100:29] wire [2:0] s2_req_rtage_0_ctr; // @[tage.scala:98:26] wire [1:0] _io_f2_resp_0_bits_u_T; // @[tage.scala:105:34] wire s2_req_rhits_1; // @[tage.scala:100:29] wire [2:0] s2_req_rtage_1_ctr; // @[tage.scala:98:26] wire [1:0] _io_f2_resp_1_bits_u_T; // @[tage.scala:105:34] wire s2_req_rhits_2; // @[tage.scala:100:29] wire [2:0] s2_req_rtage_2_ctr; // @[tage.scala:98:26] wire [1:0] _io_f2_resp_2_bits_u_T; // @[tage.scala:105:34] wire s2_req_rhits_3; // @[tage.scala:100:29] wire [2:0] s2_req_rtage_3_ctr; // @[tage.scala:98:26] wire [1:0] _io_f2_resp_3_bits_u_T; // @[tage.scala:105:34] wire update_u_mask_0 = io_update_u_mask_0_0; // @[tage.scala:24:7, :135:30] wire update_u_mask_1 = io_update_u_mask_0_0; // @[tage.scala:24:7, :135:30] wire update_u_mask_2 = io_update_u_mask_1_0; // @[tage.scala:24:7, :135:30] wire update_u_mask_3 = io_update_u_mask_1_0; // @[tage.scala:24:7, :135:30] wire update_u_mask_4 = io_update_u_mask_2_0; // @[tage.scala:24:7, :135:30] wire update_u_mask_5 = io_update_u_mask_2_0; // @[tage.scala:24:7, :135:30] wire update_u_mask_6 = io_update_u_mask_3_0; // @[tage.scala:24:7, :135:30] wire update_u_mask_7 = io_update_u_mask_3_0; // @[tage.scala:24:7, :135:30] wire [2:0] io_f2_resp_0_bits_ctr_0; // @[tage.scala:24:7] wire [1:0] io_f2_resp_0_bits_u_0; // @[tage.scala:24:7] wire io_f2_resp_0_valid_0; // @[tage.scala:24:7] wire [2:0] io_f2_resp_1_bits_ctr_0; // @[tage.scala:24:7] wire [1:0] io_f2_resp_1_bits_u_0; // @[tage.scala:24:7] wire io_f2_resp_1_valid_0; // @[tage.scala:24:7] wire [2:0] io_f2_resp_2_bits_ctr_0; // @[tage.scala:24:7] wire [1:0] io_f2_resp_2_bits_u_0; // @[tage.scala:24:7] wire io_f2_resp_2_valid_0; // @[tage.scala:24:7] wire [2:0] io_f2_resp_3_bits_ctr_0; // @[tage.scala:24:7] wire [1:0] io_f2_resp_3_bits_u_0; // @[tage.scala:24:7] wire io_f2_resp_3_valid_0; // @[tage.scala:24:7] reg doing_reset; // @[tage.scala:72:28] reg [6:0] reset_idx; // @[tage.scala:73:26] wire [7:0] _GEN = {1'h0, reset_idx}; // @[tage.scala:73:26, :74:26] wire [7:0] _reset_idx_T = _GEN + {7'h0, doing_reset}; // @[tage.scala:72:28, :74:26] wire [6:0] _reset_idx_T_1 = _reset_idx_T[6:0]; // @[tage.scala:74:26] wire [6:0] idx_history_hist_chunks_0 = io_f1_req_ghist_0[6:0]; // @[tage.scala:24:7, :53:11] wire [6:0] idx_history_hist_chunks_1 = io_f1_req_ghist_0[13:7]; // @[tage.scala:24:7, :53:11] wire [6:0] idx_history_hist_chunks_2 = io_f1_req_ghist_0[20:14]; // @[tage.scala:24:7, :53:11] wire [6:0] idx_history_hist_chunks_3 = io_f1_req_ghist_0[27:21]; // @[tage.scala:24:7, :53:11] wire [6:0] idx_history_hist_chunks_4 = io_f1_req_ghist_0[34:28]; // @[tage.scala:24:7, :53:11] wire [6:0] idx_history_hist_chunks_5 = io_f1_req_ghist_0[41:35]; // @[tage.scala:24:7, :53:11] wire [6:0] idx_history_hist_chunks_6 = io_f1_req_ghist_0[48:42]; // @[tage.scala:24:7, :53:11] wire [6:0] idx_history_hist_chunks_7 = io_f1_req_ghist_0[55:49]; // @[tage.scala:24:7, :53:11] wire [6:0] idx_history_hist_chunks_8 = io_f1_req_ghist_0[62:56]; // @[tage.scala:24:7, :53:11] wire idx_history_hist_chunks_9 = io_f1_req_ghist_0[63]; // @[tage.scala:24:7, :53:11] wire tag_history_hist_chunks_7 = io_f1_req_ghist_0[63]; // @[tage.scala:24:7, :53:11] wire [6:0] _idx_history_T = idx_history_hist_chunks_0 ^ idx_history_hist_chunks_1; // @[tage.scala:53:11, :55:25] wire [6:0] _idx_history_T_1 = _idx_history_T ^ idx_history_hist_chunks_2; // @[tage.scala:53:11, :55:25] wire [6:0] _idx_history_T_2 = _idx_history_T_1 ^ idx_history_hist_chunks_3; // @[tage.scala:53:11, :55:25] wire [6:0] _idx_history_T_3 = _idx_history_T_2 ^ idx_history_hist_chunks_4; // @[tage.scala:53:11, :55:25] wire [6:0] _idx_history_T_4 = _idx_history_T_3 ^ idx_history_hist_chunks_5; // @[tage.scala:53:11, :55:25] wire [6:0] _idx_history_T_5 = _idx_history_T_4 ^ idx_history_hist_chunks_6; // @[tage.scala:53:11, :55:25] wire [6:0] _idx_history_T_6 = _idx_history_T_5 ^ idx_history_hist_chunks_7; // @[tage.scala:53:11, :55:25] wire [6:0] _idx_history_T_7 = _idx_history_T_6 ^ idx_history_hist_chunks_8; // @[tage.scala:53:11, :55:25] wire [6:0] idx_history = {_idx_history_T_7[6:1], _idx_history_T_7[0] ^ idx_history_hist_chunks_9}; // @[tage.scala:53:11, :55:25] wire [28:0] _tag_T = io_f1_req_pc_0[39:11]; // @[frontend.scala:149:35] wire [35:0] _idx_T = {_tag_T, io_f1_req_pc_0[10:4] ^ idx_history}; // @[frontend.scala:149:35] wire [6:0] s1_hashed_idx = _idx_T[6:0]; // @[tage.scala:60:{29,43}] wire [6:0] _rdata_WIRE = s1_hashed_idx; // @[tage.scala:60:43, :122:99] wire [6:0] _u_rdata_WIRE = s1_hashed_idx; // @[tage.scala:60:43, :140:12] wire [8:0] tag_history_hist_chunks_0 = io_f1_req_ghist_0[8:0]; // @[tage.scala:24:7, :53:11] wire [8:0] tag_history_hist_chunks_1 = io_f1_req_ghist_0[17:9]; // @[tage.scala:24:7, :53:11] wire [8:0] tag_history_hist_chunks_2 = io_f1_req_ghist_0[26:18]; // @[tage.scala:24:7, :53:11] wire [8:0] tag_history_hist_chunks_3 = io_f1_req_ghist_0[35:27]; // @[tage.scala:24:7, :53:11] wire [8:0] tag_history_hist_chunks_4 = io_f1_req_ghist_0[44:36]; // @[tage.scala:24:7, :53:11] wire [8:0] tag_history_hist_chunks_5 = io_f1_req_ghist_0[53:45]; // @[tage.scala:24:7, :53:11] wire [8:0] tag_history_hist_chunks_6 = io_f1_req_ghist_0[62:54]; // @[tage.scala:24:7, :53:11] wire [8:0] _tag_history_T = tag_history_hist_chunks_0 ^ tag_history_hist_chunks_1; // @[tage.scala:53:11, :55:25] wire [8:0] _tag_history_T_1 = _tag_history_T ^ tag_history_hist_chunks_2; // @[tage.scala:53:11, :55:25] wire [8:0] _tag_history_T_2 = _tag_history_T_1 ^ tag_history_hist_chunks_3; // @[tage.scala:53:11, :55:25] wire [8:0] _tag_history_T_3 = _tag_history_T_2 ^ tag_history_hist_chunks_4; // @[tage.scala:53:11, :55:25] wire [8:0] _tag_history_T_4 = _tag_history_T_3 ^ tag_history_hist_chunks_5; // @[tage.scala:53:11, :55:25] wire [8:0] _tag_history_T_5 = _tag_history_T_4 ^ tag_history_hist_chunks_6; // @[tage.scala:53:11, :55:25] wire [8:0] tag_history = {_tag_history_T_5[8:1], _tag_history_T_5[0] ^ tag_history_hist_chunks_7}; // @[tage.scala:53:11, :55:25] wire [28:0] _tag_T_1 = {_tag_T[28:9], _tag_T[8:0] ^ tag_history}; // @[tage.scala:55:25, :62:{30,50}] wire [8:0] s1_tag = _tag_T_1[8:0]; // @[tage.scala:62:{50,64}] wire wdata_1_0; // @[tage.scala:145:20] wire wdata_1_1; // @[tage.scala:145:20] wire wdata_1_2; // @[tage.scala:145:20] wire wdata_1_3; // @[tage.scala:145:20] wire wdata_1_4; // @[tage.scala:145:20] wire wdata_1_5; // @[tage.scala:145:20] wire wdata_1_6; // @[tage.scala:145:20] wire wdata_1_7; // @[tage.scala:145:20] wire s2_req_rus_0 = _tage_u_64_R0_data[0]; // @[tage.scala:89:27, :99:24] wire s2_req_rus_1 = _tage_u_64_R0_data[1]; // @[tage.scala:89:27, :99:24] wire s2_req_rus_2 = _tage_u_64_R0_data[2]; // @[tage.scala:89:27, :99:24] wire s2_req_rus_3 = _tage_u_64_R0_data[3]; // @[tage.scala:89:27, :99:24] wire s2_req_rus_4 = _tage_u_64_R0_data[4]; // @[tage.scala:89:27, :99:24] wire s2_req_rus_5 = _tage_u_64_R0_data[5]; // @[tage.scala:89:27, :99:24] wire s2_req_rus_6 = _tage_u_64_R0_data[6]; // @[tage.scala:89:27, :99:24] wire s2_req_rus_7 = _tage_u_64_R0_data[7]; // @[tage.scala:89:27, :99:24] wire [12:0] wdata_0; // @[tage.scala:130:20] wire [12:0] wdata_1; // @[tage.scala:130:20] wire [12:0] wdata_2; // @[tage.scala:130:20] wire [12:0] wdata_3; // @[tage.scala:130:20] reg [8:0] s2_tag; // @[tage.scala:96:29] assign io_f2_resp_0_bits_ctr_0 = s2_req_rtage_0_ctr; // @[tage.scala:24:7, :98:26] assign io_f2_resp_1_bits_ctr_0 = s2_req_rtage_1_ctr; // @[tage.scala:24:7, :98:26] assign io_f2_resp_2_bits_ctr_0 = s2_req_rtage_2_ctr; // @[tage.scala:24:7, :98:26] assign io_f2_resp_3_bits_ctr_0 = s2_req_rtage_3_ctr; // @[tage.scala:24:7, :98:26] wire s2_req_rtage_0_valid; // @[tage.scala:98:26] wire [8:0] s2_req_rtage_0_tag; // @[tage.scala:98:26] wire s2_req_rtage_1_valid; // @[tage.scala:98:26] wire [8:0] s2_req_rtage_1_tag; // @[tage.scala:98:26] wire s2_req_rtage_2_valid; // @[tage.scala:98:26] wire [8:0] s2_req_rtage_2_tag; // @[tage.scala:98:26] wire s2_req_rtage_3_valid; // @[tage.scala:98:26] wire [8:0] s2_req_rtage_3_tag; // @[tage.scala:98:26] wire _s2_req_rhits_T = s2_req_rtage_0_tag == s2_tag; // @[tage.scala:96:29, :98:26, :100:69] wire _s2_req_rhits_T_1 = s2_req_rtage_0_valid & _s2_req_rhits_T; // @[tage.scala:98:26, :100:{60,69}] wire _s2_req_rhits_T_2 = ~doing_reset; // @[tage.scala:72:28, :100:83] wire _s2_req_rhits_T_3 = _s2_req_rhits_T_1 & _s2_req_rhits_T_2; // @[tage.scala:100:{60,80,83}] assign s2_req_rhits_0 = _s2_req_rhits_T_3; // @[tage.scala:100:{29,80}] wire _s2_req_rhits_T_4 = s2_req_rtage_1_tag == s2_tag; // @[tage.scala:96:29, :98:26, :100:69] wire _s2_req_rhits_T_5 = s2_req_rtage_1_valid & _s2_req_rhits_T_4; // @[tage.scala:98:26, :100:{60,69}] wire _s2_req_rhits_T_6 = ~doing_reset; // @[tage.scala:72:28, :100:83] wire _s2_req_rhits_T_7 = _s2_req_rhits_T_5 & _s2_req_rhits_T_6; // @[tage.scala:100:{60,80,83}] assign s2_req_rhits_1 = _s2_req_rhits_T_7; // @[tage.scala:100:{29,80}] wire _s2_req_rhits_T_8 = s2_req_rtage_2_tag == s2_tag; // @[tage.scala:96:29, :98:26, :100:69] wire _s2_req_rhits_T_9 = s2_req_rtage_2_valid & _s2_req_rhits_T_8; // @[tage.scala:98:26, :100:{60,69}] wire _s2_req_rhits_T_10 = ~doing_reset; // @[tage.scala:72:28, :100:83] wire _s2_req_rhits_T_11 = _s2_req_rhits_T_9 & _s2_req_rhits_T_10; // @[tage.scala:100:{60,80,83}] assign s2_req_rhits_2 = _s2_req_rhits_T_11; // @[tage.scala:100:{29,80}] wire _s2_req_rhits_T_12 = s2_req_rtage_3_tag == s2_tag; // @[tage.scala:96:29, :98:26, :100:69] wire _s2_req_rhits_T_13 = s2_req_rtage_3_valid & _s2_req_rhits_T_12; // @[tage.scala:98:26, :100:{60,69}] wire _s2_req_rhits_T_14 = ~doing_reset; // @[tage.scala:72:28, :100:83] wire _s2_req_rhits_T_15 = _s2_req_rhits_T_13 & _s2_req_rhits_T_14; // @[tage.scala:100:{60,80,83}] assign s2_req_rhits_3 = _s2_req_rhits_T_15; // @[tage.scala:100:{29,80}] assign io_f2_resp_0_valid_0 = s2_req_rhits_0; // @[tage.scala:24:7, :100:29] assign io_f2_resp_1_valid_0 = s2_req_rhits_1; // @[tage.scala:24:7, :100:29] assign io_f2_resp_2_valid_0 = s2_req_rhits_2; // @[tage.scala:24:7, :100:29] assign io_f2_resp_3_valid_0 = s2_req_rhits_3; // @[tage.scala:24:7, :100:29] assign _io_f2_resp_0_bits_u_T = {s2_req_rus_1, s2_req_rus_0}; // @[tage.scala:99:24, :105:34] assign io_f2_resp_0_bits_u_0 = _io_f2_resp_0_bits_u_T; // @[tage.scala:24:7, :105:34] assign _io_f2_resp_1_bits_u_T = {s2_req_rus_3, s2_req_rus_2}; // @[tage.scala:99:24, :105:34] assign io_f2_resp_1_bits_u_0 = _io_f2_resp_1_bits_u_T; // @[tage.scala:24:7, :105:34] assign _io_f2_resp_2_bits_u_T = {s2_req_rus_5, s2_req_rus_4}; // @[tage.scala:99:24, :105:34] assign io_f2_resp_2_bits_u_0 = _io_f2_resp_2_bits_u_T; // @[tage.scala:24:7, :105:34] assign _io_f2_resp_3_bits_u_T = {s2_req_rus_7, s2_req_rus_6}; // @[tage.scala:99:24, :105:34] assign io_f2_resp_3_bits_u_0 = _io_f2_resp_3_bits_u_T; // @[tage.scala:24:7, :105:34] reg [18:0] clear_u_ctr; // @[tage.scala:109:28] wire [19:0] _clear_u_ctr_T = {1'h0, clear_u_ctr} + 20'h1; // @[tage.scala:109:28, :110:85] wire [18:0] _clear_u_ctr_T_1 = _clear_u_ctr_T[18:0]; // @[tage.scala:110:85] wire [10:0] _doing_clear_u_T = clear_u_ctr[10:0]; // @[tage.scala:109:28, :112:34] wire doing_clear_u = _doing_clear_u_T == 11'h0; // @[tage.scala:112:{34,61}] wire _clear_u_hi_T = clear_u_ctr[18]; // @[tage.scala:109:28, :113:31] wire _clear_u_lo_T = clear_u_ctr[18]; // @[tage.scala:109:28, :113:31, :114:31] wire clear_u_hi = _clear_u_hi_T; // @[tage.scala:113:{31,72}] wire _clear_u_mask_WIRE_1 = clear_u_hi; // @[tage.scala:113:72, :116:29] wire _clear_u_mask_WIRE_3 = clear_u_hi; // @[tage.scala:113:72, :116:29] wire _clear_u_mask_WIRE_5 = clear_u_hi; // @[tage.scala:113:72, :116:29] wire _clear_u_mask_WIRE_7 = clear_u_hi; // @[tage.scala:113:72, :116:29] wire clear_u_lo = ~_clear_u_lo_T; // @[tage.scala:114:{31,72}] wire _clear_u_mask_WIRE_0 = clear_u_lo; // @[tage.scala:114:72, :116:29] wire _clear_u_mask_WIRE_2 = clear_u_lo; // @[tage.scala:114:72, :116:29] wire _clear_u_mask_WIRE_4 = clear_u_lo; // @[tage.scala:114:72, :116:29] wire _clear_u_mask_WIRE_6 = clear_u_lo; // @[tage.scala:114:72, :116:29] wire [7:0] clear_u_idx = clear_u_ctr[18:11]; // @[tage.scala:109:28, :115:33] wire [1:0] clear_u_mask_lo_lo = {_clear_u_mask_WIRE_1, _clear_u_mask_WIRE_0}; // @[tage.scala:116:{29,109}] wire [1:0] clear_u_mask_lo_hi = {_clear_u_mask_WIRE_3, _clear_u_mask_WIRE_2}; // @[tage.scala:116:{29,109}] wire [3:0] clear_u_mask_lo = {clear_u_mask_lo_hi, clear_u_mask_lo_lo}; // @[tage.scala:116:109] wire [1:0] clear_u_mask_hi_lo = {_clear_u_mask_WIRE_5, _clear_u_mask_WIRE_4}; // @[tage.scala:116:{29,109}] wire [1:0] clear_u_mask_hi_hi = {_clear_u_mask_WIRE_7, _clear_u_mask_WIRE_6}; // @[tage.scala:116:{29,109}] wire [3:0] clear_u_mask_hi = {clear_u_mask_hi_hi, clear_u_mask_hi_lo}; // @[tage.scala:116:109] wire [7:0] clear_u_mask = {clear_u_mask_hi, clear_u_mask_lo}; // @[tage.scala:116:109] wire [6:0] idx_history_hist_chunks_0_1 = io_update_hist_0[6:0]; // @[tage.scala:24:7, :53:11] wire [6:0] idx_history_hist_chunks_1_1 = io_update_hist_0[13:7]; // @[tage.scala:24:7, :53:11] wire [6:0] idx_history_hist_chunks_2_1 = io_update_hist_0[20:14]; // @[tage.scala:24:7, :53:11] wire [6:0] idx_history_hist_chunks_3_1 = io_update_hist_0[27:21]; // @[tage.scala:24:7, :53:11] wire [6:0] idx_history_hist_chunks_4_1 = io_update_hist_0[34:28]; // @[tage.scala:24:7, :53:11] wire [6:0] idx_history_hist_chunks_5_1 = io_update_hist_0[41:35]; // @[tage.scala:24:7, :53:11] wire [6:0] idx_history_hist_chunks_6_1 = io_update_hist_0[48:42]; // @[tage.scala:24:7, :53:11] wire [6:0] idx_history_hist_chunks_7_1 = io_update_hist_0[55:49]; // @[tage.scala:24:7, :53:11] wire [6:0] idx_history_hist_chunks_8_1 = io_update_hist_0[62:56]; // @[tage.scala:24:7, :53:11] wire idx_history_hist_chunks_9_1 = io_update_hist_0[63]; // @[tage.scala:24:7, :53:11] wire tag_history_hist_chunks_7_1 = io_update_hist_0[63]; // @[tage.scala:24:7, :53:11] wire [6:0] _idx_history_T_8 = idx_history_hist_chunks_0_1 ^ idx_history_hist_chunks_1_1; // @[tage.scala:53:11, :55:25] wire [6:0] _idx_history_T_9 = _idx_history_T_8 ^ idx_history_hist_chunks_2_1; // @[tage.scala:53:11, :55:25] wire [6:0] _idx_history_T_10 = _idx_history_T_9 ^ idx_history_hist_chunks_3_1; // @[tage.scala:53:11, :55:25] wire [6:0] _idx_history_T_11 = _idx_history_T_10 ^ idx_history_hist_chunks_4_1; // @[tage.scala:53:11, :55:25] wire [6:0] _idx_history_T_12 = _idx_history_T_11 ^ idx_history_hist_chunks_5_1; // @[tage.scala:53:11, :55:25] wire [6:0] _idx_history_T_13 = _idx_history_T_12 ^ idx_history_hist_chunks_6_1; // @[tage.scala:53:11, :55:25] wire [6:0] _idx_history_T_14 = _idx_history_T_13 ^ idx_history_hist_chunks_7_1; // @[tage.scala:53:11, :55:25] wire [6:0] _idx_history_T_15 = _idx_history_T_14 ^ idx_history_hist_chunks_8_1; // @[tage.scala:53:11, :55:25] wire [6:0] idx_history_1 = {_idx_history_T_15[6:1], _idx_history_T_15[0] ^ idx_history_hist_chunks_9_1}; // @[tage.scala:53:11, :55:25] wire [28:0] _tag_T_2 = io_update_pc_0[39:11]; // @[frontend.scala:149:35] wire [35:0] _idx_T_1 = {_tag_T_2, io_update_pc_0[10:4] ^ idx_history_1}; // @[frontend.scala:149:35] wire [6:0] update_idx = _idx_T_1[6:0]; // @[tage.scala:60:{29,43}] wire [8:0] tag_history_hist_chunks_0_1 = io_update_hist_0[8:0]; // @[tage.scala:24:7, :53:11] wire [8:0] tag_history_hist_chunks_1_1 = io_update_hist_0[17:9]; // @[tage.scala:24:7, :53:11] wire [8:0] tag_history_hist_chunks_2_1 = io_update_hist_0[26:18]; // @[tage.scala:24:7, :53:11] wire [8:0] tag_history_hist_chunks_3_1 = io_update_hist_0[35:27]; // @[tage.scala:24:7, :53:11] wire [8:0] tag_history_hist_chunks_4_1 = io_update_hist_0[44:36]; // @[tage.scala:24:7, :53:11] wire [8:0] tag_history_hist_chunks_5_1 = io_update_hist_0[53:45]; // @[tage.scala:24:7, :53:11] wire [8:0] tag_history_hist_chunks_6_1 = io_update_hist_0[62:54]; // @[tage.scala:24:7, :53:11] wire [8:0] _tag_history_T_6 = tag_history_hist_chunks_0_1 ^ tag_history_hist_chunks_1_1; // @[tage.scala:53:11, :55:25] wire [8:0] _tag_history_T_7 = _tag_history_T_6 ^ tag_history_hist_chunks_2_1; // @[tage.scala:53:11, :55:25] wire [8:0] _tag_history_T_8 = _tag_history_T_7 ^ tag_history_hist_chunks_3_1; // @[tage.scala:53:11, :55:25] wire [8:0] _tag_history_T_9 = _tag_history_T_8 ^ tag_history_hist_chunks_4_1; // @[tage.scala:53:11, :55:25] wire [8:0] _tag_history_T_10 = _tag_history_T_9 ^ tag_history_hist_chunks_5_1; // @[tage.scala:53:11, :55:25] wire [8:0] _tag_history_T_11 = _tag_history_T_10 ^ tag_history_hist_chunks_6_1; // @[tage.scala:53:11, :55:25] wire [8:0] tag_history_1 = {_tag_history_T_11[8:1], _tag_history_T_11[0] ^ tag_history_hist_chunks_7_1}; // @[tage.scala:53:11, :55:25] wire [28:0] _tag_T_3 = {_tag_T_2[28:9], _tag_T_2[8:0] ^ tag_history_1}; // @[tage.scala:55:25, :62:{30,50}] wire [8:0] update_tag = _tag_T_3[8:0]; // @[tage.scala:62:{50,64}] wire [8:0] update_wdata_0_tag = update_tag; // @[tage.scala:62:64, :120:26] wire [8:0] update_wdata_1_tag = update_tag; // @[tage.scala:62:64, :120:26] wire [8:0] update_wdata_2_tag = update_tag; // @[tage.scala:62:64, :120:26] wire [8:0] update_wdata_3_tag = update_tag; // @[tage.scala:62:64, :120:26] wire [2:0] _update_wdata_0_ctr_T_22; // @[tage.scala:168:33] wire [2:0] _update_wdata_1_ctr_T_22; // @[tage.scala:168:33] wire [2:0] _update_wdata_2_ctr_T_22; // @[tage.scala:168:33] wire [2:0] _update_wdata_3_ctr_T_22; // @[tage.scala:168:33] wire [2:0] update_wdata_0_ctr; // @[tage.scala:120:26] wire [2:0] update_wdata_1_ctr; // @[tage.scala:120:26] wire [2:0] update_wdata_2_ctr; // @[tage.scala:120:26] wire [2:0] update_wdata_3_ctr; // @[tage.scala:120:26] wire _wen_T = io_update_mask_0_0 | io_update_mask_1_0; // @[tage.scala:24:7, :121:60] wire _wen_T_1 = _wen_T | io_update_mask_2_0; // @[tage.scala:24:7, :121:60] wire _wen_T_2 = _wen_T_1 | io_update_mask_3_0; // @[tage.scala:24:7, :121:60] wire _wen_T_3 = doing_reset | _wen_T_2; // @[tage.scala:72:28, :121:{34,60}] wire wen = _wen_T_3; // @[tage.scala:121:{21,34}] reg REG; // @[tage.scala:123:16] assign s2_req_rtage_0_ctr = _tage_table_64_R0_data[2:0]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_0_tag = _tage_table_64_R0_data[11:3]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_0_valid = _tage_table_64_R0_data[12]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_1_ctr = _tage_table_64_R0_data[15:13]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_1_tag = _tage_table_64_R0_data[24:16]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_1_valid = _tage_table_64_R0_data[25]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_2_ctr = _tage_table_64_R0_data[28:26]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_2_tag = _tage_table_64_R0_data[37:29]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_2_valid = _tage_table_64_R0_data[38]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_3_ctr = _tage_table_64_R0_data[41:39]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_3_tag = _tage_table_64_R0_data[50:42]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_3_valid = _tage_table_64_R0_data[51]; // @[tage.scala:90:27, :98:26, :126:49] wire [6:0] widx = doing_reset ? reset_idx : update_idx; // @[tage.scala:60:43, :72:28, :73:26, :129:19] wire [9:0] wdata_hi = {1'h1, update_wdata_0_tag}; // @[tage.scala:120:26, :130:114] wire [12:0] _wdata_T = {wdata_hi, update_wdata_0_ctr}; // @[tage.scala:120:26, :130:114] wire [12:0] _wdata_WIRE_1_0 = _wdata_T; // @[tage.scala:130:{94,114}] wire [9:0] wdata_hi_1 = {1'h1, update_wdata_1_tag}; // @[tage.scala:120:26, :130:114] wire [12:0] _wdata_T_1 = {wdata_hi_1, update_wdata_1_ctr}; // @[tage.scala:120:26, :130:114] wire [12:0] _wdata_WIRE_1_1 = _wdata_T_1; // @[tage.scala:130:{94,114}] wire [9:0] wdata_hi_2 = {1'h1, update_wdata_2_tag}; // @[tage.scala:120:26, :130:114] wire [12:0] _wdata_T_2 = {wdata_hi_2, update_wdata_2_ctr}; // @[tage.scala:120:26, :130:114] wire [12:0] _wdata_WIRE_1_2 = _wdata_T_2; // @[tage.scala:130:{94,114}] wire [9:0] wdata_hi_3 = {1'h1, update_wdata_3_tag}; // @[tage.scala:120:26, :130:114] wire [12:0] _wdata_T_3 = {wdata_hi_3, update_wdata_3_ctr}; // @[tage.scala:120:26, :130:114] wire [12:0] _wdata_WIRE_1_3 = _wdata_T_3; // @[tage.scala:130:{94,114}] assign wdata_0 = doing_reset ? 13'h0 : _wdata_WIRE_1_0; // @[tage.scala:72:28, :130:{20,94}] assign wdata_1 = doing_reset ? 13'h0 : _wdata_WIRE_1_1; // @[tage.scala:72:28, :130:{20,94}] assign wdata_2 = doing_reset ? 13'h0 : _wdata_WIRE_1_2; // @[tage.scala:72:28, :130:{20,94}] assign wdata_3 = doing_reset ? 13'h0 : _wdata_WIRE_1_3; // @[tage.scala:72:28, :130:{20,94}] wire [1:0] wmask_lo = {io_update_mask_1_0, io_update_mask_0_0}; // @[tage.scala:24:7, :131:70] wire [1:0] wmask_hi = {io_update_mask_3_0, io_update_mask_2_0}; // @[tage.scala:24:7, :131:70] wire [3:0] _wmask_T_1 = {wmask_hi, wmask_lo}; // @[tage.scala:131:70] wire [3:0] wmask = doing_reset ? 4'hF : _wmask_T_1; // @[tage.scala:72:28, :131:{20,70}] wire _GEN_0 = doing_reset | doing_clear_u; // @[tage.scala:72:28, :112:61, :136:43] wire _update_u_wen_T; // @[tage.scala:136:43] assign _update_u_wen_T = _GEN_0; // @[tage.scala:136:43] wire _wdata_T_4; // @[tage.scala:145:33] assign _wdata_T_4 = _GEN_0; // @[tage.scala:136:43, :145:33] wire _update_u_wen_T_1 = update_u_mask_0 | update_u_mask_1; // @[tage.scala:135:30, :136:85] wire _update_u_wen_T_2 = _update_u_wen_T_1 | update_u_mask_2; // @[tage.scala:135:30, :136:85] wire _update_u_wen_T_3 = _update_u_wen_T_2 | update_u_mask_3; // @[tage.scala:135:30, :136:85] wire _update_u_wen_T_4 = _update_u_wen_T_3 | update_u_mask_4; // @[tage.scala:135:30, :136:85] wire _update_u_wen_T_5 = _update_u_wen_T_4 | update_u_mask_5; // @[tage.scala:135:30, :136:85] wire _update_u_wen_T_6 = _update_u_wen_T_5 | update_u_mask_6; // @[tage.scala:135:30, :136:85] wire _update_u_wen_T_7 = _update_u_wen_T_6 | update_u_mask_7; // @[tage.scala:135:30, :136:85] wire _update_u_wen_T_8 = _update_u_wen_T | _update_u_wen_T_7; // @[tage.scala:136:{43,60,85}] wire update_u_wen = _update_u_wen_T_8; // @[tage.scala:136:{30,60}] wire [7:0] _widx_T = doing_clear_u ? clear_u_idx : {1'h0, update_idx}; // @[tage.scala:60:43, :112:61, :115:33, :144:47] wire [7:0] widx_1 = doing_reset ? _GEN : _widx_T; // @[tage.scala:72:28, :74:26, :144:{19,47}] wire [3:0] wdata_lo = {io_update_u_1_0, io_update_u_0_0}; // @[tage.scala:24:7, :145:110] wire [3:0] wdata_hi_4 = {io_update_u_3_0, io_update_u_2_0}; // @[tage.scala:24:7, :145:110] wire [7:0] _wdata_T_5 = {wdata_hi_4, wdata_lo}; // @[tage.scala:145:110] wire _wdata_T_6 = _wdata_T_5[0]; // @[tage.scala:145:{110,117}] wire _wdata_WIRE_3_0 = _wdata_T_6; // @[tage.scala:145:{97,117}] wire _wdata_T_7 = _wdata_T_5[1]; // @[tage.scala:145:{110,117}] wire _wdata_WIRE_3_1 = _wdata_T_7; // @[tage.scala:145:{97,117}] wire _wdata_T_8 = _wdata_T_5[2]; // @[tage.scala:145:{110,117}] wire _wdata_WIRE_3_2 = _wdata_T_8; // @[tage.scala:145:{97,117}] wire _wdata_T_9 = _wdata_T_5[3]; // @[tage.scala:145:{110,117}] wire _wdata_WIRE_3_3 = _wdata_T_9; // @[tage.scala:145:{97,117}] wire _wdata_T_10 = _wdata_T_5[4]; // @[tage.scala:145:{110,117}] wire _wdata_WIRE_3_4 = _wdata_T_10; // @[tage.scala:145:{97,117}] wire _wdata_T_11 = _wdata_T_5[5]; // @[tage.scala:145:{110,117}] wire _wdata_WIRE_3_5 = _wdata_T_11; // @[tage.scala:145:{97,117}] wire _wdata_T_12 = _wdata_T_5[6]; // @[tage.scala:145:{110,117}] wire _wdata_WIRE_3_6 = _wdata_T_12; // @[tage.scala:145:{97,117}] wire _wdata_T_13 = _wdata_T_5[7]; // @[tage.scala:145:{110,117}] wire _wdata_WIRE_3_7 = _wdata_T_13; // @[tage.scala:145:{97,117}] assign wdata_1_0 = ~_wdata_T_4 & _wdata_WIRE_3_0; // @[tage.scala:145:{20,33,97}] assign wdata_1_1 = ~_wdata_T_4 & _wdata_WIRE_3_1; // @[tage.scala:145:{20,33,97}] assign wdata_1_2 = ~_wdata_T_4 & _wdata_WIRE_3_2; // @[tage.scala:145:{20,33,97}] assign wdata_1_3 = ~_wdata_T_4 & _wdata_WIRE_3_3; // @[tage.scala:145:{20,33,97}] assign wdata_1_4 = ~_wdata_T_4 & _wdata_WIRE_3_4; // @[tage.scala:145:{20,33,97}] assign wdata_1_5 = ~_wdata_T_4 & _wdata_WIRE_3_5; // @[tage.scala:145:{20,33,97}] assign wdata_1_6 = ~_wdata_T_4 & _wdata_WIRE_3_6; // @[tage.scala:145:{20,33,97}] assign wdata_1_7 = ~_wdata_T_4 & _wdata_WIRE_3_7; // @[tage.scala:145:{20,33,97}] wire [1:0] wmask_lo_lo = {update_u_mask_1, update_u_mask_0}; // @[tage.scala:135:30, :146:106] wire [1:0] wmask_lo_hi = {update_u_mask_3, update_u_mask_2}; // @[tage.scala:135:30, :146:106] wire [3:0] wmask_lo_1 = {wmask_lo_hi, wmask_lo_lo}; // @[tage.scala:146:106] wire [1:0] wmask_hi_lo = {update_u_mask_5, update_u_mask_4}; // @[tage.scala:135:30, :146:106] wire [1:0] wmask_hi_hi = {update_u_mask_7, update_u_mask_6}; // @[tage.scala:135:30, :146:106] wire [3:0] wmask_hi_1 = {wmask_hi_hi, wmask_hi_lo}; // @[tage.scala:146:106] wire [7:0] _wmask_T_3 = {wmask_hi_1, wmask_lo_1}; // @[tage.scala:146:106] wire [7:0] _wmask_T_4 = doing_clear_u ? clear_u_mask : _wmask_T_3; // @[tage.scala:112:61, :116:109, :146:{62,106}] wire [7:0] wmask_1 = doing_reset ? 8'hFF : _wmask_T_4; // @[tage.scala:72:28, :146:{20,62}] reg [8:0] wrbypass_tags_0; // @[tage.scala:154:29] reg [8:0] wrbypass_tags_1; // @[tage.scala:154:29] reg [6:0] wrbypass_idxs_0; // @[tage.scala:155:29] reg [6:0] wrbypass_idxs_1; // @[tage.scala:155:29] reg [2:0] wrbypass_0_0; // @[tage.scala:156:29] reg [2:0] wrbypass_0_1; // @[tage.scala:156:29] reg [2:0] wrbypass_0_2; // @[tage.scala:156:29] reg [2:0] wrbypass_0_3; // @[tage.scala:156:29] reg [2:0] wrbypass_1_0; // @[tage.scala:156:29] reg [2:0] wrbypass_1_1; // @[tage.scala:156:29] reg [2:0] wrbypass_1_2; // @[tage.scala:156:29] reg [2:0] wrbypass_1_3; // @[tage.scala:156:29] reg wrbypass_enq_idx; // @[tage.scala:157:33] wire _wrbypass_hits_T = ~doing_reset; // @[tage.scala:72:28, :100:83, :160:5] wire _wrbypass_hits_T_1 = wrbypass_tags_0 == update_tag; // @[tage.scala:62:64, :154:29, :161:22] wire _wrbypass_hits_T_2 = _wrbypass_hits_T & _wrbypass_hits_T_1; // @[tage.scala:160:{5,18}, :161:22] wire _wrbypass_hits_T_3 = wrbypass_idxs_0 == update_idx; // @[tage.scala:60:43, :155:29, :162:22] wire _wrbypass_hits_T_4 = _wrbypass_hits_T_2 & _wrbypass_hits_T_3; // @[tage.scala:160:18, :161:37, :162:22] wire wrbypass_hits_0 = _wrbypass_hits_T_4; // @[tage.scala:159:33, :161:37] wire _wrbypass_hits_T_5 = ~doing_reset; // @[tage.scala:72:28, :100:83, :160:5] wire _wrbypass_hits_T_6 = wrbypass_tags_1 == update_tag; // @[tage.scala:62:64, :154:29, :161:22] wire _wrbypass_hits_T_7 = _wrbypass_hits_T_5 & _wrbypass_hits_T_6; // @[tage.scala:160:{5,18}, :161:22] wire _wrbypass_hits_T_8 = wrbypass_idxs_1 == update_idx; // @[tage.scala:60:43, :155:29, :162:22] wire _wrbypass_hits_T_9 = _wrbypass_hits_T_7 & _wrbypass_hits_T_8; // @[tage.scala:160:18, :161:37, :162:22] wire wrbypass_hits_1 = _wrbypass_hits_T_9; // @[tage.scala:159:33, :161:37] wire wrbypass_hit = wrbypass_hits_0 | wrbypass_hits_1; // @[tage.scala:159:33, :164:48] wire wrbypass_hit_idx = ~wrbypass_hits_0; // @[Mux.scala:50:70] wire [2:0] _update_wdata_0_ctr_T = io_update_taken_0_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :169:10] wire _update_wdata_0_ctr_T_1 = ~io_update_taken_0_0; // @[tage.scala:24:7, :67:9] wire [2:0] _GEN_1 = wrbypass_hit_idx ? wrbypass_1_0 : wrbypass_0_0; // @[Mux.scala:50:70] wire [2:0] _GEN_2 = wrbypass_hit_idx ? wrbypass_1_1 : wrbypass_0_1; // @[Mux.scala:50:70] wire [2:0] _GEN_3 = wrbypass_hit_idx ? wrbypass_1_2 : wrbypass_0_2; // @[Mux.scala:50:70] wire [2:0] _GEN_4 = wrbypass_hit_idx ? wrbypass_1_3 : wrbypass_0_3; // @[Mux.scala:50:70] wire _update_wdata_0_ctr_T_2 = _GEN_1 == 3'h0; // @[tage.scala:67:25] wire [3:0] _GEN_5 = {1'h0, _GEN_1}; // @[tage.scala:67:{25,43}] wire [3:0] _update_wdata_0_ctr_T_3 = _GEN_5 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_0_ctr_T_4 = _update_wdata_0_ctr_T_3[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_0_ctr_T_5 = _update_wdata_0_ctr_T_2 ? 3'h0 : _update_wdata_0_ctr_T_4; // @[tage.scala:67:{20,25,43}] wire _update_wdata_0_ctr_T_6 = &_GEN_1; // @[tage.scala:67:25, :68:25] wire [3:0] _update_wdata_0_ctr_T_7 = _GEN_5 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_0_ctr_T_8 = _update_wdata_0_ctr_T_7[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_0_ctr_T_9 = _update_wdata_0_ctr_T_6 ? 3'h7 : _update_wdata_0_ctr_T_8; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_0_ctr_T_10 = _update_wdata_0_ctr_T_1 ? _update_wdata_0_ctr_T_5 : _update_wdata_0_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20] wire _update_wdata_0_ctr_T_11 = ~io_update_taken_0_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_0_ctr_T_12 = io_update_old_ctr_0_0 == 3'h0; // @[tage.scala:24:7, :67:25] wire [3:0] _GEN_6 = {1'h0, io_update_old_ctr_0_0}; // @[tage.scala:24:7, :67:43] wire [3:0] _update_wdata_0_ctr_T_13 = _GEN_6 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_0_ctr_T_14 = _update_wdata_0_ctr_T_13[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_0_ctr_T_15 = _update_wdata_0_ctr_T_12 ? 3'h0 : _update_wdata_0_ctr_T_14; // @[tage.scala:67:{20,25,43}] wire _update_wdata_0_ctr_T_16 = &io_update_old_ctr_0_0; // @[tage.scala:24:7, :68:25] wire [3:0] _update_wdata_0_ctr_T_17 = _GEN_6 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_0_ctr_T_18 = _update_wdata_0_ctr_T_17[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_0_ctr_T_19 = _update_wdata_0_ctr_T_16 ? 3'h7 : _update_wdata_0_ctr_T_18; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_0_ctr_T_20 = _update_wdata_0_ctr_T_11 ? _update_wdata_0_ctr_T_15 : _update_wdata_0_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20] wire [2:0] _update_wdata_0_ctr_T_21 = wrbypass_hit ? _update_wdata_0_ctr_T_10 : _update_wdata_0_ctr_T_20; // @[tage.scala:67:8, :164:48, :172:10] assign _update_wdata_0_ctr_T_22 = io_update_alloc_0_0 ? _update_wdata_0_ctr_T : _update_wdata_0_ctr_T_21; // @[tage.scala:24:7, :168:33, :169:10, :172:10] assign update_wdata_0_ctr = _update_wdata_0_ctr_T_22; // @[tage.scala:120:26, :168:33] wire [2:0] _update_wdata_1_ctr_T = io_update_taken_1_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :169:10] wire _update_wdata_1_ctr_T_1 = ~io_update_taken_1_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_1_ctr_T_2 = _GEN_2 == 3'h0; // @[tage.scala:67:25] wire [3:0] _GEN_7 = {1'h0, _GEN_2}; // @[tage.scala:67:{25,43}] wire [3:0] _update_wdata_1_ctr_T_3 = _GEN_7 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_1_ctr_T_4 = _update_wdata_1_ctr_T_3[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_1_ctr_T_5 = _update_wdata_1_ctr_T_2 ? 3'h0 : _update_wdata_1_ctr_T_4; // @[tage.scala:67:{20,25,43}] wire _update_wdata_1_ctr_T_6 = &_GEN_2; // @[tage.scala:67:25, :68:25] wire [3:0] _update_wdata_1_ctr_T_7 = _GEN_7 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_1_ctr_T_8 = _update_wdata_1_ctr_T_7[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_1_ctr_T_9 = _update_wdata_1_ctr_T_6 ? 3'h7 : _update_wdata_1_ctr_T_8; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_1_ctr_T_10 = _update_wdata_1_ctr_T_1 ? _update_wdata_1_ctr_T_5 : _update_wdata_1_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20] wire _update_wdata_1_ctr_T_11 = ~io_update_taken_1_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_1_ctr_T_12 = io_update_old_ctr_1_0 == 3'h0; // @[tage.scala:24:7, :67:25] wire [3:0] _GEN_8 = {1'h0, io_update_old_ctr_1_0}; // @[tage.scala:24:7, :67:43] wire [3:0] _update_wdata_1_ctr_T_13 = _GEN_8 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_1_ctr_T_14 = _update_wdata_1_ctr_T_13[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_1_ctr_T_15 = _update_wdata_1_ctr_T_12 ? 3'h0 : _update_wdata_1_ctr_T_14; // @[tage.scala:67:{20,25,43}] wire _update_wdata_1_ctr_T_16 = &io_update_old_ctr_1_0; // @[tage.scala:24:7, :68:25] wire [3:0] _update_wdata_1_ctr_T_17 = _GEN_8 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_1_ctr_T_18 = _update_wdata_1_ctr_T_17[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_1_ctr_T_19 = _update_wdata_1_ctr_T_16 ? 3'h7 : _update_wdata_1_ctr_T_18; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_1_ctr_T_20 = _update_wdata_1_ctr_T_11 ? _update_wdata_1_ctr_T_15 : _update_wdata_1_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20] wire [2:0] _update_wdata_1_ctr_T_21 = wrbypass_hit ? _update_wdata_1_ctr_T_10 : _update_wdata_1_ctr_T_20; // @[tage.scala:67:8, :164:48, :172:10] assign _update_wdata_1_ctr_T_22 = io_update_alloc_1_0 ? _update_wdata_1_ctr_T : _update_wdata_1_ctr_T_21; // @[tage.scala:24:7, :168:33, :169:10, :172:10] assign update_wdata_1_ctr = _update_wdata_1_ctr_T_22; // @[tage.scala:120:26, :168:33] wire [2:0] _update_wdata_2_ctr_T = io_update_taken_2_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :169:10] wire _update_wdata_2_ctr_T_1 = ~io_update_taken_2_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_2_ctr_T_2 = _GEN_3 == 3'h0; // @[tage.scala:67:25] wire [3:0] _GEN_9 = {1'h0, _GEN_3}; // @[tage.scala:67:{25,43}] wire [3:0] _update_wdata_2_ctr_T_3 = _GEN_9 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_2_ctr_T_4 = _update_wdata_2_ctr_T_3[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_2_ctr_T_5 = _update_wdata_2_ctr_T_2 ? 3'h0 : _update_wdata_2_ctr_T_4; // @[tage.scala:67:{20,25,43}] wire _update_wdata_2_ctr_T_6 = &_GEN_3; // @[tage.scala:67:25, :68:25] wire [3:0] _update_wdata_2_ctr_T_7 = _GEN_9 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_2_ctr_T_8 = _update_wdata_2_ctr_T_7[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_2_ctr_T_9 = _update_wdata_2_ctr_T_6 ? 3'h7 : _update_wdata_2_ctr_T_8; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_2_ctr_T_10 = _update_wdata_2_ctr_T_1 ? _update_wdata_2_ctr_T_5 : _update_wdata_2_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20] wire _update_wdata_2_ctr_T_11 = ~io_update_taken_2_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_2_ctr_T_12 = io_update_old_ctr_2_0 == 3'h0; // @[tage.scala:24:7, :67:25] wire [3:0] _GEN_10 = {1'h0, io_update_old_ctr_2_0}; // @[tage.scala:24:7, :67:43] wire [3:0] _update_wdata_2_ctr_T_13 = _GEN_10 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_2_ctr_T_14 = _update_wdata_2_ctr_T_13[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_2_ctr_T_15 = _update_wdata_2_ctr_T_12 ? 3'h0 : _update_wdata_2_ctr_T_14; // @[tage.scala:67:{20,25,43}] wire _update_wdata_2_ctr_T_16 = &io_update_old_ctr_2_0; // @[tage.scala:24:7, :68:25] wire [3:0] _update_wdata_2_ctr_T_17 = _GEN_10 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_2_ctr_T_18 = _update_wdata_2_ctr_T_17[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_2_ctr_T_19 = _update_wdata_2_ctr_T_16 ? 3'h7 : _update_wdata_2_ctr_T_18; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_2_ctr_T_20 = _update_wdata_2_ctr_T_11 ? _update_wdata_2_ctr_T_15 : _update_wdata_2_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20] wire [2:0] _update_wdata_2_ctr_T_21 = wrbypass_hit ? _update_wdata_2_ctr_T_10 : _update_wdata_2_ctr_T_20; // @[tage.scala:67:8, :164:48, :172:10] assign _update_wdata_2_ctr_T_22 = io_update_alloc_2_0 ? _update_wdata_2_ctr_T : _update_wdata_2_ctr_T_21; // @[tage.scala:24:7, :168:33, :169:10, :172:10] assign update_wdata_2_ctr = _update_wdata_2_ctr_T_22; // @[tage.scala:120:26, :168:33] wire [2:0] _update_wdata_3_ctr_T = io_update_taken_3_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :169:10] wire _update_wdata_3_ctr_T_1 = ~io_update_taken_3_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_3_ctr_T_2 = _GEN_4 == 3'h0; // @[tage.scala:67:25] wire [3:0] _GEN_11 = {1'h0, _GEN_4}; // @[tage.scala:67:{25,43}] wire [3:0] _update_wdata_3_ctr_T_3 = _GEN_11 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_3_ctr_T_4 = _update_wdata_3_ctr_T_3[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_3_ctr_T_5 = _update_wdata_3_ctr_T_2 ? 3'h0 : _update_wdata_3_ctr_T_4; // @[tage.scala:67:{20,25,43}] wire _update_wdata_3_ctr_T_6 = &_GEN_4; // @[tage.scala:67:25, :68:25] wire [3:0] _update_wdata_3_ctr_T_7 = _GEN_11 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_3_ctr_T_8 = _update_wdata_3_ctr_T_7[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_3_ctr_T_9 = _update_wdata_3_ctr_T_6 ? 3'h7 : _update_wdata_3_ctr_T_8; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_3_ctr_T_10 = _update_wdata_3_ctr_T_1 ? _update_wdata_3_ctr_T_5 : _update_wdata_3_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20] wire _update_wdata_3_ctr_T_11 = ~io_update_taken_3_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_3_ctr_T_12 = io_update_old_ctr_3_0 == 3'h0; // @[tage.scala:24:7, :67:25] wire [3:0] _GEN_12 = {1'h0, io_update_old_ctr_3_0}; // @[tage.scala:24:7, :67:43] wire [3:0] _update_wdata_3_ctr_T_13 = _GEN_12 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_3_ctr_T_14 = _update_wdata_3_ctr_T_13[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_3_ctr_T_15 = _update_wdata_3_ctr_T_12 ? 3'h0 : _update_wdata_3_ctr_T_14; // @[tage.scala:67:{20,25,43}] wire _update_wdata_3_ctr_T_16 = &io_update_old_ctr_3_0; // @[tage.scala:24:7, :68:25] wire [3:0] _update_wdata_3_ctr_T_17 = _GEN_12 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_3_ctr_T_18 = _update_wdata_3_ctr_T_17[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_3_ctr_T_19 = _update_wdata_3_ctr_T_16 ? 3'h7 : _update_wdata_3_ctr_T_18; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_3_ctr_T_20 = _update_wdata_3_ctr_T_11 ? _update_wdata_3_ctr_T_15 : _update_wdata_3_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20] wire [2:0] _update_wdata_3_ctr_T_21 = wrbypass_hit ? _update_wdata_3_ctr_T_10 : _update_wdata_3_ctr_T_20; // @[tage.scala:67:8, :164:48, :172:10] assign _update_wdata_3_ctr_T_22 = io_update_alloc_3_0 ? _update_wdata_3_ctr_T : _update_wdata_3_ctr_T_21; // @[tage.scala:24:7, :168:33, :169:10, :172:10] assign update_wdata_3_ctr = _update_wdata_3_ctr_T_22; // @[tage.scala:120:26, :168:33] wire [1:0] _wrbypass_enq_idx_T = {1'h0, wrbypass_enq_idx} + 2'h1; // @[util.scala:211:14] wire _wrbypass_enq_idx_T_1 = _wrbypass_enq_idx_T[0]; // @[util.scala:211:14] wire _wrbypass_enq_idx_T_2 = _wrbypass_enq_idx_T_1; // @[util.scala:211:{14,20}] wire _T_31 = _wen_T | io_update_mask_2_0 | io_update_mask_3_0; // @[tage.scala:24:7, :121:60, :180:32] wire _GEN_13 = wrbypass_hit ? wrbypass_hit_idx : wrbypass_enq_idx; // @[Mux.scala:50:70] wire _GEN_14 = ~_T_31 | wrbypass_hit | wrbypass_enq_idx; // @[tage.scala:154:29, :156:29, :157:33, :164:48, :180:{32,38}, :181:39, :185:39] wire _GEN_15 = ~_T_31 | wrbypass_hit | ~wrbypass_enq_idx; // @[tage.scala:154:29, :156:29, :157:33, :164:48, :180:{32,38}, :181:39, :185:39] always @(posedge clock) begin // @[tage.scala:24:7] if (reset) begin // @[tage.scala:24:7] doing_reset <= 1'h1; // @[tage.scala:72:28] reset_idx <= 7'h0; // @[tage.scala:73:26] clear_u_ctr <= 19'h0; // @[tage.scala:109:28] wrbypass_enq_idx <= 1'h0; // @[tage.scala:157:33] end else begin // @[tage.scala:24:7] doing_reset <= reset_idx != 7'h7F & doing_reset; // @[tage.scala:72:28, :73:26, :75:{19,36,50}] reset_idx <= _reset_idx_T_1; // @[tage.scala:73:26, :74:26] clear_u_ctr <= doing_reset ? 19'h1 : _clear_u_ctr_T_1; // @[tage.scala:72:28, :109:28, :110:{22,36,70,85}] if (~_T_31 | wrbypass_hit) begin // @[tage.scala:156:29, :157:33, :164:48, :180:{32,38}, :181:39] end else // @[tage.scala:157:33, :180:38, :181:39] wrbypass_enq_idx <= _wrbypass_enq_idx_T_2; // @[util.scala:211:20] end s2_tag <= s1_tag; // @[tage.scala:62:64, :96:29] REG <= wen; // @[tage.scala:121:21, :123:16] if (_GEN_14) begin // @[tage.scala:154:29, :180:38, :181:39, :185:39] end else // @[tage.scala:154:29, :180:38, :181:39, :185:39] wrbypass_tags_0 <= update_tag; // @[tage.scala:62:64, :154:29] if (_GEN_15) begin // @[tage.scala:154:29, :180:38, :181:39, :185:39] end else // @[tage.scala:154:29, :180:38, :181:39, :185:39] wrbypass_tags_1 <= update_tag; // @[tage.scala:62:64, :154:29] if (_GEN_14) begin // @[tage.scala:154:29, :155:29, :180:38, :181:39, :185:39, :186:39] end else // @[tage.scala:155:29, :180:38, :181:39, :186:39] wrbypass_idxs_0 <= update_idx; // @[tage.scala:60:43, :155:29] if (_GEN_15) begin // @[tage.scala:154:29, :155:29, :180:38, :181:39, :185:39, :186:39] end else // @[tage.scala:155:29, :180:38, :181:39, :186:39] wrbypass_idxs_1 <= update_idx; // @[tage.scala:60:43, :155:29] if (~_T_31 | _GEN_13) begin // @[tage.scala:156:29, :180:{32,38}, :181:39, :182:34, :184:39] end else begin // @[tage.scala:156:29, :180:38, :181:39] wrbypass_0_0 <= update_wdata_0_ctr; // @[tage.scala:120:26, :156:29] wrbypass_0_1 <= update_wdata_1_ctr; // @[tage.scala:120:26, :156:29] wrbypass_0_2 <= update_wdata_2_ctr; // @[tage.scala:120:26, :156:29] wrbypass_0_3 <= update_wdata_3_ctr; // @[tage.scala:120:26, :156:29] end if (_T_31 & _GEN_13) begin // @[tage.scala:156:29, :180:{32,38}, :181:39, :182:34, :184:39] wrbypass_1_0 <= update_wdata_0_ctr; // @[tage.scala:120:26, :156:29] wrbypass_1_1 <= update_wdata_1_ctr; // @[tage.scala:120:26, :156:29] wrbypass_1_2 <= update_wdata_2_ctr; // @[tage.scala:120:26, :156:29] wrbypass_1_3 <= update_wdata_3_ctr; // @[tage.scala:120:26, :156:29] end always @(posedge) tage_u_64 tage_u_64 ( // @[tage.scala:89:27] .R0_addr (_u_rdata_WIRE), // @[tage.scala:140:12] .R0_en (io_f1_req_valid_0), // @[tage.scala:24:7] .R0_clk (clock), .R0_data (_tage_u_64_R0_data), .W0_addr (widx_1[6:0]), // @[tage.scala:144:19, :147:13] .W0_en (update_u_wen), // @[tage.scala:136:30] .W0_clk (clock), .W0_data ({wdata_1_7, wdata_1_6, wdata_1_5, wdata_1_4, wdata_1_3, wdata_1_2, wdata_1_1, wdata_1_0}), // @[tage.scala:89:27, :145:20] .W0_mask (wmask_1) // @[tage.scala:146:20] ); // @[tage.scala:89:27] tage_table_64 tage_table_64 ( // @[tage.scala:90:27] .R0_addr (_rdata_WIRE), // @[tage.scala:122:99] .R0_en (io_f1_req_valid_0), // @[tage.scala:24:7] .R0_clk (clock), .R0_data (_tage_table_64_R0_data), .W0_addr (widx), // @[tage.scala:129:19] .W0_en (wen), // @[tage.scala:121:21] .W0_clk (clock), .W0_data ({wdata_3, wdata_2, wdata_1, wdata_0}), // @[tage.scala:90:27, :130:20] .W0_mask (wmask) // @[tage.scala:131:20] ); // @[tage.scala:90:27] assign io_f2_resp_0_valid = io_f2_resp_0_valid_0; // @[tage.scala:24:7] assign io_f2_resp_0_bits_ctr = io_f2_resp_0_bits_ctr_0; // @[tage.scala:24:7] assign io_f2_resp_0_bits_u = io_f2_resp_0_bits_u_0; // @[tage.scala:24:7] assign io_f2_resp_1_valid = io_f2_resp_1_valid_0; // @[tage.scala:24:7] assign io_f2_resp_1_bits_ctr = io_f2_resp_1_bits_ctr_0; // @[tage.scala:24:7] assign io_f2_resp_1_bits_u = io_f2_resp_1_bits_u_0; // @[tage.scala:24:7] assign io_f2_resp_2_valid = io_f2_resp_2_valid_0; // @[tage.scala:24:7] assign io_f2_resp_2_bits_ctr = io_f2_resp_2_bits_ctr_0; // @[tage.scala:24:7] assign io_f2_resp_2_bits_u = io_f2_resp_2_bits_u_0; // @[tage.scala:24:7] assign io_f2_resp_3_valid = io_f2_resp_3_valid_0; // @[tage.scala:24:7] assign io_f2_resp_3_bits_ctr = io_f2_resp_3_bits_ctr_0; // @[tage.scala:24:7] assign io_f2_resp_3_bits_u = io_f2_resp_3_bits_u_0; // @[tage.scala:24:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands */ class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def *(t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def *(t: UInt) = self * t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros | ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def *(t: SInt) = self * t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros | ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid || output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def *(t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def *(t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }

module PE_504( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid, // @[PE.scala:35:14] output io_bad_dataflow // @[PE.scala:35:14] ); wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24] wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [31:0] c1; // @[PE.scala:70:15] wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [31:0] c2; // @[PE.scala:71:15] wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25] wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61] wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38] wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38] assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16] assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10] wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10] c1 <= _GEN_7; // @[PE.scala:70:15, :124:10] if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30] end else // @[PE.scala:71:15, :118:101, :119:30] c2 <= _GEN_7; // @[PE.scala:71:15, :124:10] end else begin // @[PE.scala:31:7] c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10] c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10] end last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] end always @(posedge) MacUnit_248 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24] .io_out_d (_mac_unit_io_out_d) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File RegisterRouter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes} import freechips.rocketchip.resources.{Device, Resource, ResourceBindings} import freechips.rocketchip.prci.{NoCrossing} import freechips.rocketchip.regmapper.{RegField, RegMapper, RegMapperParams, RegMapperInput, RegisterRouter} import freechips.rocketchip.util.{BundleField, ControlKey, ElaborationArtefacts, GenRegDescsAnno} import scala.math.min class TLRegisterRouterExtraBundle(val sourceBits: Int, val sizeBits: Int) extends Bundle { val source = UInt((sourceBits max 1).W) val size = UInt((sizeBits max 1).W) } case object TLRegisterRouterExtra extends ControlKey[TLRegisterRouterExtraBundle]("tlrr_extra") case class TLRegisterRouterExtraField(sourceBits: Int, sizeBits: Int) extends BundleField[TLRegisterRouterExtraBundle](TLRegisterRouterExtra, Output(new TLRegisterRouterExtraBundle(sourceBits, sizeBits)), x => { x.size := 0.U x.source := 0.U }) /** TLRegisterNode is a specialized TL SinkNode that encapsulates MMIO registers. * It provides functionality for describing and outputting metdata about the registers in several formats. * It also provides a concrete implementation of a regmap function that will be used * to wire a map of internal registers associated with this node to the node's interconnect port. */ case class TLRegisterNode( address: Seq[AddressSet], device: Device, deviceKey: String = "reg/control", concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false)( implicit valName: ValName) extends SinkNode(TLImp)(Seq(TLSlavePortParameters.v1( Seq(TLSlaveParameters.v1( address = address, resources = Seq(Resource(device, deviceKey)), executable = executable, supportsGet = TransferSizes(1, beatBytes), supportsPutPartial = TransferSizes(1, beatBytes), supportsPutFull = TransferSizes(1, beatBytes), fifoId = Some(0))), // requests are handled in order beatBytes = beatBytes, minLatency = min(concurrency, 1)))) with TLFormatNode // the Queue adds at most one cycle { val size = 1 << log2Ceil(1 + address.map(_.max).max - address.map(_.base).min) require (size >= beatBytes) address.foreach { case a => require (a.widen(size-1).base == address.head.widen(size-1).base, s"TLRegisterNode addresses (${address}) must be aligned to its size ${size}") } // Calling this method causes the matching TL2 bundle to be // configured to route all requests to the listed RegFields. def regmap(mapping: RegField.Map*) = { val (bundleIn, edge) = this.in(0) val a = bundleIn.a val d = bundleIn.d val fields = TLRegisterRouterExtraField(edge.bundle.sourceBits, edge.bundle.sizeBits) +: a.bits.params.echoFields val params = RegMapperParams(log2Up(size/beatBytes), beatBytes, fields) val in = Wire(Decoupled(new RegMapperInput(params))) in.bits.read := a.bits.opcode === TLMessages.Get in.bits.index := edge.addr_hi(a.bits) in.bits.data := a.bits.data in.bits.mask := a.bits.mask Connectable.waiveUnmatched(in.bits.extra, a.bits.echo) match { case (lhs, rhs) => lhs :<= rhs } val a_extra = in.bits.extra(TLRegisterRouterExtra) a_extra.source := a.bits.source a_extra.size := a.bits.size // Invoke the register map builder val out = RegMapper(beatBytes, concurrency, undefZero, in, mapping:_*) // No flow control needed in.valid := a.valid a.ready := in.ready d.valid := out.valid out.ready := d.ready // We must restore the size to enable width adapters to work val d_extra = out.bits.extra(TLRegisterRouterExtra) d.bits := edge.AccessAck(toSource = d_extra.source, lgSize = d_extra.size) // avoid a Mux on the data bus by manually overriding two fields d.bits.data := out.bits.data Connectable.waiveUnmatched(d.bits.echo, out.bits.extra) match { case (lhs, rhs) => lhs :<= rhs } d.bits.opcode := Mux(out.bits.read, TLMessages.AccessAckData, TLMessages.AccessAck) // Tie off unused channels bundleIn.b.valid := false.B bundleIn.c.ready := true.B bundleIn.e.ready := true.B genRegDescsJson(mapping:_*) } def genRegDescsJson(mapping: RegField.Map*): Unit = { // Dump out the register map for documentation purposes. val base = address.head.base val baseHex = s"0x${base.toInt.toHexString}" val name = s"${device.describe(ResourceBindings()).name}.At${baseHex}" val json = GenRegDescsAnno.serialize(base, name, mapping:_*) var suffix = 0 while( ElaborationArtefacts.contains(s"${baseHex}.${suffix}.regmap.json")) { suffix = suffix + 1 } ElaborationArtefacts.add(s"${baseHex}.${suffix}.regmap.json", json) val module = Module.currentModule.get.asInstanceOf[RawModule] GenRegDescsAnno.anno( module, base, mapping:_*) } } /** Mix HasTLControlRegMap into any subclass of RegisterRouter to gain helper functions for attaching a device control register map to TileLink. * - The intended use case is that controlNode will diplomatically publish a SW-visible device's memory-mapped control registers. * - Use the clock crossing helper controlXing to externally connect controlNode to a TileLink interconnect. * - Use the mapping helper function regmap to internally fill out the space of device control registers. */ trait HasTLControlRegMap { this: RegisterRouter => protected val controlNode = TLRegisterNode( address = address, device = device, deviceKey = "reg/control", concurrency = concurrency, beatBytes = beatBytes, undefZero = undefZero, executable = executable) // Externally, this helper should be used to connect the register control port to a bus val controlXing: TLInwardClockCrossingHelper = this.crossIn(controlNode) // Backwards-compatibility default node accessor with no clock crossing lazy val node: TLInwardNode = controlXing(NoCrossing) // Internally, this function should be used to populate the control port with registers protected def regmap(mapping: RegField.Map*): Unit = { controlNode.regmap(mapping:_*) } } File RegField.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.regmapper import chisel3._ import chisel3.util.{DecoupledIO, ReadyValidIO} import org.json4s.JsonDSL._ import org.json4s.JsonAST.JValue import freechips.rocketchip.util.{SimpleRegIO} case class RegReadFn private(combinational: Boolean, fn: (Bool, Bool) => (Bool, Bool, UInt)) object RegReadFn { // (ivalid: Bool, oready: Bool) => (iready: Bool, ovalid: Bool, data: UInt) // iready may combinationally depend on oready // all other combinational dependencies forbidden (e.g. ovalid <= ivalid) // effects must become visible on the cycle after ovalid && oready // data is only inspected when ovalid && oready implicit def apply(x: (Bool, Bool) => (Bool, Bool, UInt)) = new RegReadFn(false, x) implicit def apply(x: RegisterReadIO[UInt]): RegReadFn = RegReadFn((ivalid, oready) => { x.request.valid := ivalid x.response.ready := oready (x.request.ready, x.response.valid, x.response.bits) }) // (ready: Bool) => (valid: Bool, data: UInt) // valid must not combinationally depend on ready // effects must become visible on the cycle after valid && ready implicit def apply(x: Bool => (Bool, UInt)) = new RegReadFn(true, { case (_, oready) => val (ovalid, data) = x(oready) (true.B, ovalid, data) }) // read from a ReadyValidIO (only safe if there is a consistent source of data) implicit def apply(x: ReadyValidIO[UInt]):RegReadFn = RegReadFn(ready => { x.ready := ready; (x.valid, x.bits) }) // read from a register implicit def apply(x: UInt):RegReadFn = RegReadFn(ready => (true.B, x)) // noop implicit def apply(x: Unit):RegReadFn = RegReadFn(0.U) } case class RegWriteFn private(combinational: Boolean, fn: (Bool, Bool, UInt) => (Bool, Bool)) object RegWriteFn { // (ivalid: Bool, oready: Bool, data: UInt) => (iready: Bool, ovalid: Bool) // iready may combinationally depend on both oready and data // all other combinational dependencies forbidden (e.g. ovalid <= ivalid) // effects must become visible on the cycle after ovalid && oready // data should only be used for an effect when ivalid && iready implicit def apply(x: (Bool, Bool, UInt) => (Bool, Bool)) = new RegWriteFn(false, x) implicit def apply(x: RegisterWriteIO[UInt]): RegWriteFn = RegWriteFn((ivalid, oready, data) => { x.request.valid := ivalid x.request.bits := data x.response.ready := oready (x.request.ready, x.response.valid) }) // (valid: Bool, data: UInt) => (ready: Bool) // ready may combinationally depend on data (but not valid) // effects must become visible on the cycle after valid && ready implicit def apply(x: (Bool, UInt) => Bool) = // combinational => data valid on oready new RegWriteFn(true, { case (_, oready, data) => (true.B, x(oready, data)) }) // write to a DecoupledIO (only safe if there is a consistent sink draining data) // NOTE: this is not an IrrevocableIO (even on TL2) because other fields could cause a lowered valid implicit def apply(x: DecoupledIO[UInt]): RegWriteFn = RegWriteFn((valid, data) => { x.valid := valid; x.bits := data; x.ready }) // updates a register (or adds a mux to a wire) implicit def apply(x: UInt): RegWriteFn = RegWriteFn((valid, data) => { when (valid) { x := data }; true.B }) // noop implicit def apply(x: Unit): RegWriteFn = RegWriteFn((valid, data) => { true.B }) } case class RegField(width: Int, read: RegReadFn, write: RegWriteFn, desc: Option[RegFieldDesc]) { require (width >= 0, s"RegField width must be >= 0, not $width") def pipelined = !read.combinational || !write.combinational def readOnly = this.copy(write = (), desc = this.desc.map(_.copy(access = RegFieldAccessType.R))) def toJson(byteOffset: Int, bitOffset: Int): JValue = { ( ("byteOffset" -> s"0x${byteOffset.toHexString}") ~ ("bitOffset" -> bitOffset) ~ ("bitWidth" -> width) ~ ("name" -> desc.map(_.name)) ~ ("description" -> desc.map{ d=> if (d.desc == "") None else Some(d.desc)}) ~ ("resetValue" -> desc.map{_.reset}) ~ ("group" -> desc.map{_.group}) ~ ("groupDesc" -> desc.map{_.groupDesc}) ~ ("accessType" -> desc.map {d => d.access.toString}) ~ ("writeType" -> desc.map {d => d.wrType.map(_.toString)}) ~ ("readAction" -> desc.map {d => d.rdAction.map(_.toString)}) ~ ("volatile" -> desc.map {d => if (d.volatile) Some(true) else None}) ~ ("enumerations" -> desc.map {d => Option(d.enumerations.map { case (key, (name, edesc)) => (("value" -> key) ~ ("name" -> name) ~ ("description" -> edesc)) }).filter(_.nonEmpty)}) ) } } object RegField { // Byte address => sequence of bitfields, lowest index => lowest address type Map = (Int, Seq[RegField]) def apply(n: Int) : RegField = apply(n, (), (), Some(RegFieldDesc.reserved)) def apply(n: Int, desc: RegFieldDesc) : RegField = apply(n, (), (), Some(desc)) def apply(n: Int, r: RegReadFn, w: RegWriteFn) : RegField = apply(n, r, w, None) def apply(n: Int, r: RegReadFn, w: RegWriteFn, desc: RegFieldDesc) : RegField = apply(n, r, w, Some(desc)) def apply(n: Int, rw: UInt) : RegField = apply(n, rw, rw, None) def apply(n: Int, rw: UInt, desc: RegFieldDesc) : RegField = apply(n, rw, rw, Some(desc)) def r(n: Int, r: RegReadFn) : RegField = apply(n, r, (), None) def r(n: Int, r: RegReadFn, desc: RegFieldDesc) : RegField = apply(n, r, (), Some(desc.copy(access = RegFieldAccessType.R))) def w(n: Int, w: RegWriteFn) : RegField = apply(n, (), w, None) def w(n: Int, w: RegWriteFn, desc: RegFieldDesc) : RegField = apply(n, (), w, Some(desc.copy(access = RegFieldAccessType.W))) // This RegField allows 'set' to set bits in 'reg'. // and to clear bits when the bus writes bits of value 1. // Setting takes priority over clearing. def w1ToClear(n: Int, reg: UInt, set: UInt, desc: Option[RegFieldDesc] = None): RegField = RegField(n, reg, RegWriteFn((valid, data) => { reg := (~((~reg) | Mux(valid, data, 0.U))) | set; true.B }), desc.map{_.copy(access = RegFieldAccessType.RW, wrType=Some(RegFieldWrType.ONE_TO_CLEAR), volatile = true)}) // This RegField wraps an explicit register // (e.g. Black-Boxed Register) to create a R/W register. def rwReg(n: Int, bb: SimpleRegIO, desc: Option[RegFieldDesc] = None) : RegField = RegField(n, bb.q, RegWriteFn((valid, data) => { bb.en := valid bb.d := data true.B }), desc) // Create byte-sized read-write RegFields out of a large UInt register. // It is updated when any of the (implemented) bytes are written, the non-written // bytes are just copied over from their current value. // Because the RegField are all byte-sized, this is also suitable when a register is larger // than the intended bus width of the device (atomic updates are impossible). def bytes(reg: UInt, numBytes: Int, desc: Option[RegFieldDesc]): Seq[RegField] = { require(reg.getWidth * 8 >= numBytes, "Can't break a ${reg.getWidth}-bit-wide register into only ${numBytes} bytes.") val numFullBytes = reg.getWidth/8 val numPartialBytes = if ((reg.getWidth % 8) > 0) 1 else 0 val numPadBytes = numBytes - numFullBytes - numPartialBytes val pad = reg | 0.U((8*numBytes).W) val oldBytes = VecInit.tabulate(numBytes) { i => pad(8*(i+1)-1, 8*i) } val newBytes = WireDefault(oldBytes) val valids = WireDefault(VecInit.fill(numBytes) { false.B }) when (valids.reduce(_ || _)) { reg := newBytes.asUInt } def wrFn(i: Int): RegWriteFn = RegWriteFn((valid, data) => { valids(i) := valid when (valid) {newBytes(i) := data} true.B }) val fullBytes = Seq.tabulate(numFullBytes) { i => val newDesc = desc.map {d => d.copy(name = d.name + s"_$i")} RegField(8, oldBytes(i), wrFn(i), newDesc)} val partialBytes = if (numPartialBytes > 0) { val newDesc = desc.map {d => d.copy(name = d.name + s"_$numFullBytes")} Seq(RegField(reg.getWidth % 8, oldBytes(numFullBytes), wrFn(numFullBytes), newDesc), RegField(8 - (reg.getWidth % 8))) } else Nil val padBytes = Seq.fill(numPadBytes){RegField(8)} fullBytes ++ partialBytes ++ padBytes } def bytes(reg: UInt, desc: Option[RegFieldDesc]): Seq[RegField] = { val width = reg.getWidth require (width % 8 == 0, s"RegField.bytes must be called on byte-sized reg, not ${width} bits") bytes(reg, width/8, desc) } def bytes(reg: UInt, numBytes: Int): Seq[RegField] = bytes(reg, numBytes, None) def bytes(reg: UInt): Seq[RegField] = bytes(reg, None) } trait HasRegMap { def regmap(mapping: RegField.Map*): Unit val interrupts: Vec[Bool] } // See Example.scala for an example of how to use regmap File MuxLiteral.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.log2Ceil import scala.reflect.ClassTag /* MuxLiteral creates a lookup table from a key to a list of values. * Unlike MuxLookup, the table keys must be exclusive literals. */ object MuxLiteral { def apply[T <: Data:ClassTag](index: UInt, default: T, first: (UInt, T), rest: (UInt, T)*): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[(UInt, T)]): T = MuxTable(index, default, cases.map { case (k, v) => (k.litValue, v) }) } object MuxSeq { def apply[T <: Data:ClassTag](index: UInt, default: T, first: T, rest: T*): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[T]): T = MuxTable(index, default, cases.zipWithIndex.map { case (v, i) => (BigInt(i), v) }) } object MuxTable { def apply[T <: Data:ClassTag](index: UInt, default: T, first: (BigInt, T), rest: (BigInt, T)*): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[(BigInt, T)]): T = { /* All keys must be >= 0 and distinct */ cases.foreach { case (k, _) => require (k >= 0) } require (cases.map(_._1).distinct.size == cases.size) /* Filter out any cases identical to the default */ val simple = cases.filter { case (k, v) => !default.isLit || !v.isLit || v.litValue != default.litValue } val maxKey = (BigInt(0) +: simple.map(_._1)).max val endIndex = BigInt(1) << log2Ceil(maxKey+1) if (simple.isEmpty) { default } else if (endIndex <= 2*simple.size) { /* The dense encoding case uses a Vec */ val table = Array.fill(endIndex.toInt) { default } simple.foreach { case (k, v) => table(k.toInt) = v } Mux(index >= endIndex.U, default, VecInit(table)(index)) } else { /* The sparse encoding case uses switch */ val out = WireDefault(default) simple.foldLeft(new chisel3.util.SwitchContext(index, None, Set.empty)) { case (acc, (k, v)) => acc.is (k.U) { out := v } } out } } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } } File CLINT.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.devices.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet} import freechips.rocketchip.resources.{Resource, SimpleDevice} import freechips.rocketchip.interrupts.{IntNexusNode, IntSinkParameters, IntSinkPortParameters, IntSourceParameters, IntSourcePortParameters} import freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldGroup} import freechips.rocketchip.subsystem.{BaseSubsystem, CBUS, TLBusWrapperLocation} import freechips.rocketchip.tilelink.{TLFragmenter, TLRegisterNode} import freechips.rocketchip.util.Annotated object CLINTConsts { def msipOffset(hart: Int) = hart * msipBytes def timecmpOffset(hart: Int) = 0x4000 + hart * timecmpBytes def timeOffset = 0xbff8 def msipBytes = 4 def timecmpBytes = 8 def size = 0x10000 def timeWidth = 64 def ipiWidth = 32 def ints = 2 } case class CLINTParams(baseAddress: BigInt = 0x02000000, intStages: Int = 0) { def address = AddressSet(baseAddress, CLINTConsts.size-1) } case object CLINTKey extends Field[Option[CLINTParams]](None) case class CLINTAttachParams( slaveWhere: TLBusWrapperLocation = CBUS ) case object CLINTAttachKey extends Field(CLINTAttachParams()) class CLINT(params: CLINTParams, beatBytes: Int)(implicit p: Parameters) extends LazyModule { import CLINTConsts._ // clint0 => at most 4095 devices val device = new SimpleDevice("clint", Seq("riscv,clint0")) { override val alwaysExtended = true } val node: TLRegisterNode = TLRegisterNode( address = Seq(params.address), device = device, beatBytes = beatBytes) val intnode : IntNexusNode = IntNexusNode( sourceFn = { _ => IntSourcePortParameters(Seq(IntSourceParameters(ints, Seq(Resource(device, "int"))))) }, sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) }, outputRequiresInput = false) lazy val module = new Impl class Impl extends LazyModuleImp(this) { Annotated.params(this, params) require (intnode.edges.in.size == 0, "CLINT only produces interrupts; it does not accept them") val io = IO(new Bundle { val rtcTick = Input(Bool()) }) val time = RegInit(0.U(timeWidth.W)) when (io.rtcTick) { time := time + 1.U } val nTiles = intnode.out.size val timecmp = Seq.fill(nTiles) { Reg(UInt(timeWidth.W)) } val ipi = Seq.fill(nTiles) { RegInit(0.U(1.W)) } val (intnode_out, _) = intnode.out.unzip intnode_out.zipWithIndex.foreach { case (int, i) => int(0) := ShiftRegister(ipi(i)(0), params.intStages) // msip int(1) := ShiftRegister(time.asUInt >= timecmp(i).asUInt, params.intStages) // mtip } /* 0000 msip hart 0 * 0004 msip hart 1 * 4000 mtimecmp hart 0 lo * 4004 mtimecmp hart 0 hi * 4008 mtimecmp hart 1 lo * 400c mtimecmp hart 1 hi * bff8 mtime lo * bffc mtime hi */ node.regmap( 0 -> RegFieldGroup ("msip", Some("MSIP Bits"), ipi.zipWithIndex.flatMap{ case (r, i) => RegField(1, r, RegFieldDesc(s"msip_$i", s"MSIP bit for Hart $i", reset=Some(0))) :: RegField(ipiWidth - 1) :: Nil }), timecmpOffset(0) -> timecmp.zipWithIndex.flatMap{ case (t, i) => RegFieldGroup(s"mtimecmp_$i", Some(s"MTIMECMP for hart $i"), RegField.bytes(t, Some(RegFieldDesc(s"mtimecmp_$i", "", reset=None))))}, timeOffset -> RegFieldGroup("mtime", Some("Timer Register"), RegField.bytes(time, Some(RegFieldDesc("mtime", "", reset=Some(0), volatile=true)))) ) } } /** Trait that will connect a CLINT to a subsystem */ trait CanHavePeripheryCLINT { this: BaseSubsystem => val (clintOpt, clintDomainOpt, clintTickOpt) = p(CLINTKey).map { params => val tlbus = locateTLBusWrapper(p(CLINTAttachKey).slaveWhere) val clintDomainWrapper = tlbus.generateSynchronousDomain("CLINT").suggestName("clint_domain") val clint = clintDomainWrapper { LazyModule(new CLINT(params, tlbus.beatBytes)) } clintDomainWrapper { clint.node := tlbus.coupleTo("clint") { TLFragmenter(tlbus, Some("CLINT")) := _ } } val clintTick = clintDomainWrapper { InModuleBody { val tick = IO(Input(Bool())) clint.module.io.rtcTick := tick tick }} (clint, clintDomainWrapper, clintTick) }.unzip3 }

module CLINT( // @[CLINT.scala:65:9] input clock, // @[CLINT.scala:65:9] input reset, // @[CLINT.scala:65:9] output auto_int_out_0, // @[LazyModuleImp.scala:107:25] output auto_int_out_1, // @[LazyModuleImp.scala:107:25] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [25:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input io_rtcTick // @[CLINT.scala:69:16] ); wire out_front_valid; // @[RegisterRouter.scala:87:24] wire out_front_ready; // @[RegisterRouter.scala:87:24] wire out_bits_read; // @[RegisterRouter.scala:87:24] wire [10:0] out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [12:0] in_bits_index; // @[RegisterRouter.scala:73:18] wire in_bits_read; // @[RegisterRouter.scala:73:18] wire auto_in_a_valid_0 = auto_in_a_valid; // @[CLINT.scala:65:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[CLINT.scala:65:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[CLINT.scala:65:9] wire [1:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[CLINT.scala:65:9] wire [10:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[CLINT.scala:65:9] wire [25:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[CLINT.scala:65:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[CLINT.scala:65:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[CLINT.scala:65:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[CLINT.scala:65:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[CLINT.scala:65:9] wire io_rtcTick_0 = io_rtcTick; // @[CLINT.scala:65:9] wire [12:0] out_maskMatch = 13'h7FF; // @[RegisterRouter.scala:87:24] wire [2:0] nodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17] wire [63:0] _out_out_bits_data_WIRE_1_3 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] nodeIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17] wire auto_in_d_bits_sink = 1'h0; // @[CLINT.scala:65:9] wire auto_in_d_bits_denied = 1'h0; // @[CLINT.scala:65:9] wire auto_in_d_bits_corrupt = 1'h0; // @[CLINT.scala:65:9] wire nodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire _valids_WIRE_0 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_2 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_3 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_4 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_5 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_6 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_7 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_0 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_1 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_2 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_3 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_4 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_5 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_6 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_7 = 1'h0; // @[RegField.scala:153:53] wire _out_rifireMux_T_16 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_18 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wifireMux_T_17 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_19 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_rofireMux_T_16 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_18 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wofireMux_T_17 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_19 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T_2 = 1'h0; // @[MuxLiteral.scala:49:17] wire nodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17] wire nodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17] wire nodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17] wire [1:0] auto_in_d_bits_param = 2'h0; // @[CLINT.scala:65:9] wire [1:0] nodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17] wire intnodeOut_0; // @[MixedNode.scala:542:17] wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_iready = 1'h1; // @[RegisterRouter.scala:87:24] wire out_oready = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire intnodeOut_1; // @[MixedNode.scala:542:17] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[CLINT.scala:65:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[CLINT.scala:65:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[CLINT.scala:65:9] wire [1:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[CLINT.scala:65:9] wire [10:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[CLINT.scala:65:9] wire [25:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[CLINT.scala:65:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[CLINT.scala:65:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[CLINT.scala:65:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[CLINT.scala:65:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[CLINT.scala:65:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [10:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire auto_int_out_0_0; // @[CLINT.scala:65:9] wire auto_int_out_1_0; // @[CLINT.scala:65:9] wire auto_in_a_ready_0; // @[CLINT.scala:65:9] wire [2:0] auto_in_d_bits_opcode_0; // @[CLINT.scala:65:9] wire [1:0] auto_in_d_bits_size_0; // @[CLINT.scala:65:9] wire [10:0] auto_in_d_bits_source_0; // @[CLINT.scala:65:9] wire [63:0] auto_in_d_bits_data_0; // @[CLINT.scala:65:9] wire auto_in_d_valid_0; // @[CLINT.scala:65:9] wire in_ready; // @[RegisterRouter.scala:73:18] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[CLINT.scala:65:9] wire in_valid = nodeIn_a_valid; // @[RegisterRouter.scala:73:18] wire [1:0] in_bits_extra_tlrr_extra_size = nodeIn_a_bits_size; // @[RegisterRouter.scala:73:18] wire [10:0] in_bits_extra_tlrr_extra_source = nodeIn_a_bits_source; // @[RegisterRouter.scala:73:18] wire [7:0] in_bits_mask = nodeIn_a_bits_mask; // @[RegisterRouter.scala:73:18] wire [63:0] in_bits_data = nodeIn_a_bits_data; // @[RegisterRouter.scala:73:18] wire out_ready = nodeIn_d_ready; // @[RegisterRouter.scala:87:24] wire out_valid; // @[RegisterRouter.scala:87:24] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[CLINT.scala:65:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[CLINT.scala:65:9] wire [1:0] nodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[CLINT.scala:65:9] wire [10:0] nodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[CLINT.scala:65:9] wire [63:0] out_bits_data; // @[RegisterRouter.scala:87:24] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[CLINT.scala:65:9] wire _intnodeOut_0_T; // @[CLINT.scala:82:37] assign auto_int_out_0_0 = intnodeOut_0; // @[CLINT.scala:65:9] wire _intnodeOut_1_T; // @[CLINT.scala:83:43] assign auto_int_out_1_0 = intnodeOut_1; // @[CLINT.scala:65:9] reg [63:0] time_0; // @[CLINT.scala:73:23] wire [63:0] pad_1 = time_0; // @[RegField.scala:150:19] wire [64:0] _time_T = {1'h0, time_0} + 65'h1; // @[CLINT.scala:73:23, :74:38] wire [63:0] _time_T_1 = _time_T[63:0]; // @[CLINT.scala:74:38] reg [63:0] timecmp_0; // @[CLINT.scala:77:41] wire [63:0] pad = timecmp_0; // @[RegField.scala:150:19] reg ipi_0; // @[CLINT.scala:78:41] assign _intnodeOut_0_T = ipi_0; // @[CLINT.scala:78:41, :82:37] wire _out_T_15 = ipi_0; // @[RegisterRouter.scala:87:24] assign intnodeOut_0 = _intnodeOut_0_T; // @[CLINT.scala:82:37] assign _intnodeOut_1_T = time_0 >= timecmp_0; // @[CLINT.scala:73:23, :77:41, :83:43] assign intnodeOut_1 = _intnodeOut_1_T; // @[CLINT.scala:83:43] wire [7:0] _oldBytes_T = pad[7:0]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_0 = _oldBytes_T; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_1 = pad[15:8]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1 = _oldBytes_T_1; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_2 = pad[23:16]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_2 = _oldBytes_T_2; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_3 = pad[31:24]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_3 = _oldBytes_T_3; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_4 = pad[39:32]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_4 = _oldBytes_T_4; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_5 = pad[47:40]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_5 = _oldBytes_T_5; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_6 = pad[55:48]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_6 = _oldBytes_T_6; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_7 = pad[63:56]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_7 = _oldBytes_T_7; // @[RegField.scala:151:{47,57}] wire [7:0] _out_T_123 = oldBytes_0; // @[RegisterRouter.scala:87:24] wire [7:0] newBytes_0; // @[RegField.scala:152:31] wire [7:0] newBytes_1; // @[RegField.scala:152:31] wire [7:0] newBytes_2; // @[RegField.scala:152:31] wire [7:0] newBytes_3; // @[RegField.scala:152:31] wire [7:0] newBytes_4; // @[RegField.scala:152:31] wire [7:0] newBytes_5; // @[RegField.scala:152:31] wire [7:0] newBytes_6; // @[RegField.scala:152:31] wire [7:0] newBytes_7; // @[RegField.scala:152:31] wire out_f_woready_10; // @[RegisterRouter.scala:87:24] wire out_f_woready_11; // @[RegisterRouter.scala:87:24] wire out_f_woready_12; // @[RegisterRouter.scala:87:24] wire out_f_woready_13; // @[RegisterRouter.scala:87:24] wire out_f_woready_14; // @[RegisterRouter.scala:87:24] wire out_f_woready_15; // @[RegisterRouter.scala:87:24] wire out_f_woready_16; // @[RegisterRouter.scala:87:24] wire out_f_woready_17; // @[RegisterRouter.scala:87:24] wire valids_0; // @[RegField.scala:153:29] wire valids_1; // @[RegField.scala:153:29] wire valids_2; // @[RegField.scala:153:29] wire valids_3; // @[RegField.scala:153:29] wire valids_4; // @[RegField.scala:153:29] wire valids_5; // @[RegField.scala:153:29] wire valids_6; // @[RegField.scala:153:29] wire valids_7; // @[RegField.scala:153:29] wire [15:0] timecmp_0_lo_lo = {newBytes_1, newBytes_0}; // @[RegField.scala:152:31, :154:52] wire [15:0] timecmp_0_lo_hi = {newBytes_3, newBytes_2}; // @[RegField.scala:152:31, :154:52] wire [31:0] timecmp_0_lo = {timecmp_0_lo_hi, timecmp_0_lo_lo}; // @[RegField.scala:154:52] wire [15:0] timecmp_0_hi_lo = {newBytes_5, newBytes_4}; // @[RegField.scala:152:31, :154:52] wire [15:0] timecmp_0_hi_hi = {newBytes_7, newBytes_6}; // @[RegField.scala:152:31, :154:52] wire [31:0] timecmp_0_hi = {timecmp_0_hi_hi, timecmp_0_hi_lo}; // @[RegField.scala:154:52] wire [63:0] _timecmp_0_T = {timecmp_0_hi, timecmp_0_lo}; // @[RegField.scala:154:52] wire [7:0] _oldBytes_T_8 = pad_1[7:0]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_0 = _oldBytes_T_8; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_9 = pad_1[15:8]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_1 = _oldBytes_T_9; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_10 = pad_1[23:16]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_2 = _oldBytes_T_10; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_11 = pad_1[31:24]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_3 = _oldBytes_T_11; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_12 = pad_1[39:32]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_4 = _oldBytes_T_12; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_13 = pad_1[47:40]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_5 = _oldBytes_T_13; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_14 = pad_1[55:48]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_6 = _oldBytes_T_14; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_15 = pad_1[63:56]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_7 = _oldBytes_T_15; // @[RegField.scala:151:{47,57}] wire [7:0] _out_T_35 = oldBytes_1_0; // @[RegisterRouter.scala:87:24] wire [7:0] newBytes_1_0; // @[RegField.scala:152:31] wire [7:0] newBytes_1_1; // @[RegField.scala:152:31] wire [7:0] newBytes_1_2; // @[RegField.scala:152:31] wire [7:0] newBytes_1_3; // @[RegField.scala:152:31] wire [7:0] newBytes_1_4; // @[RegField.scala:152:31] wire [7:0] newBytes_1_5; // @[RegField.scala:152:31] wire [7:0] newBytes_1_6; // @[RegField.scala:152:31] wire [7:0] newBytes_1_7; // @[RegField.scala:152:31] wire out_f_woready_2; // @[RegisterRouter.scala:87:24] wire out_f_woready_3; // @[RegisterRouter.scala:87:24] wire out_f_woready_4; // @[RegisterRouter.scala:87:24] wire out_f_woready_5; // @[RegisterRouter.scala:87:24] wire out_f_woready_6; // @[RegisterRouter.scala:87:24] wire out_f_woready_7; // @[RegisterRouter.scala:87:24] wire out_f_woready_8; // @[RegisterRouter.scala:87:24] wire out_f_woready_9; // @[RegisterRouter.scala:87:24] wire valids_1_0; // @[RegField.scala:153:29] wire valids_1_1; // @[RegField.scala:153:29] wire valids_1_2; // @[RegField.scala:153:29] wire valids_1_3; // @[RegField.scala:153:29] wire valids_1_4; // @[RegField.scala:153:29] wire valids_1_5; // @[RegField.scala:153:29] wire valids_1_6; // @[RegField.scala:153:29] wire valids_1_7; // @[RegField.scala:153:29] wire [15:0] time_lo_lo = {newBytes_1_1, newBytes_1_0}; // @[RegField.scala:152:31, :154:52] wire [15:0] time_lo_hi = {newBytes_1_3, newBytes_1_2}; // @[RegField.scala:152:31, :154:52] wire [31:0] time_lo = {time_lo_hi, time_lo_lo}; // @[RegField.scala:154:52] wire [15:0] time_hi_lo = {newBytes_1_5, newBytes_1_4}; // @[RegField.scala:152:31, :154:52] wire [15:0] time_hi_hi = {newBytes_1_7, newBytes_1_6}; // @[RegField.scala:152:31, :154:52] wire [31:0] time_hi = {time_hi_hi, time_hi_lo}; // @[RegField.scala:154:52] wire [63:0] _time_T_2 = {time_hi, time_lo}; // @[RegField.scala:154:52] wire _out_in_ready_T; // @[RegisterRouter.scala:87:24] assign nodeIn_a_ready = in_ready; // @[RegisterRouter.scala:73:18] wire _in_bits_read_T; // @[RegisterRouter.scala:74:36] wire _out_front_valid_T = in_valid; // @[RegisterRouter.scala:73:18, :87:24] wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24] wire [12:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24] wire [63:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24] wire [7:0] out_front_bits_mask = in_bits_mask; // @[RegisterRouter.scala:73:18, :87:24] wire [10:0] out_front_bits_extra_tlrr_extra_source = in_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24] wire [1:0] out_front_bits_extra_tlrr_extra_size = in_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24] assign _in_bits_read_T = nodeIn_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36] wire [22:0] _in_bits_index_T = nodeIn_a_bits_address[25:3]; // @[Edges.scala:192:34] assign in_bits_index = _in_bits_index_T[12:0]; // @[RegisterRouter.scala:73:18, :75:19] wire _out_front_ready_T = out_ready; // @[RegisterRouter.scala:87:24] wire _out_out_valid_T; // @[RegisterRouter.scala:87:24] assign nodeIn_d_valid = out_valid; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24] wire _nodeIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25] assign nodeIn_d_bits_data = out_bits_data; // @[RegisterRouter.scala:87:24] assign nodeIn_d_bits_d_source = out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [1:0] out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign nodeIn_d_bits_d_size = out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign _out_in_ready_T = out_front_ready; // @[RegisterRouter.scala:87:24] assign _out_out_valid_T = out_front_valid; // @[RegisterRouter.scala:87:24] assign out_bits_read = out_front_bits_read; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_source = out_front_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_size = out_front_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] wire [12:0] _GEN = out_front_bits_index & 13'h7FF; // @[RegisterRouter.scala:87:24] wire [12:0] out_findex; // @[RegisterRouter.scala:87:24] assign out_findex = _GEN; // @[RegisterRouter.scala:87:24] wire [12:0] out_bindex; // @[RegisterRouter.scala:87:24] assign out_bindex = _GEN; // @[RegisterRouter.scala:87:24] wire _GEN_0 = out_findex == 13'h0; // @[RegisterRouter.scala:87:24] wire _out_T; // @[RegisterRouter.scala:87:24] assign _out_T = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_T_4; // @[RegisterRouter.scala:87:24] assign _out_T_4 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _GEN_1 = out_bindex == 13'h0; // @[RegisterRouter.scala:87:24] wire _out_T_1; // @[RegisterRouter.scala:87:24] assign _out_T_1 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_T_5; // @[RegisterRouter.scala:87:24] assign _out_T_5 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_0 = _out_T_1; // @[MuxLiteral.scala:49:48] wire _out_T_2 = out_findex == 13'h7FF; // @[RegisterRouter.scala:87:24] wire _out_T_3 = out_bindex == 13'h7FF; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_2 = _out_T_3; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_1 = _out_T_5; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] wire out_rivalid_0; // @[RegisterRouter.scala:87:24] wire out_rivalid_1; // @[RegisterRouter.scala:87:24] wire out_rivalid_2; // @[RegisterRouter.scala:87:24] wire out_rivalid_3; // @[RegisterRouter.scala:87:24] wire out_rivalid_4; // @[RegisterRouter.scala:87:24] wire out_rivalid_5; // @[RegisterRouter.scala:87:24] wire out_rivalid_6; // @[RegisterRouter.scala:87:24] wire out_rivalid_7; // @[RegisterRouter.scala:87:24] wire out_rivalid_8; // @[RegisterRouter.scala:87:24] wire out_rivalid_9; // @[RegisterRouter.scala:87:24] wire out_rivalid_10; // @[RegisterRouter.scala:87:24] wire out_rivalid_11; // @[RegisterRouter.scala:87:24] wire out_rivalid_12; // @[RegisterRouter.scala:87:24] wire out_rivalid_13; // @[RegisterRouter.scala:87:24] wire out_rivalid_14; // @[RegisterRouter.scala:87:24] wire out_rivalid_15; // @[RegisterRouter.scala:87:24] wire out_rivalid_16; // @[RegisterRouter.scala:87:24] wire out_rivalid_17; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] wire out_wivalid_0; // @[RegisterRouter.scala:87:24] wire out_wivalid_1; // @[RegisterRouter.scala:87:24] wire out_wivalid_2; // @[RegisterRouter.scala:87:24] wire out_wivalid_3; // @[RegisterRouter.scala:87:24] wire out_wivalid_4; // @[RegisterRouter.scala:87:24] wire out_wivalid_5; // @[RegisterRouter.scala:87:24] wire out_wivalid_6; // @[RegisterRouter.scala:87:24] wire out_wivalid_7; // @[RegisterRouter.scala:87:24] wire out_wivalid_8; // @[RegisterRouter.scala:87:24] wire out_wivalid_9; // @[RegisterRouter.scala:87:24] wire out_wivalid_10; // @[RegisterRouter.scala:87:24] wire out_wivalid_11; // @[RegisterRouter.scala:87:24] wire out_wivalid_12; // @[RegisterRouter.scala:87:24] wire out_wivalid_13; // @[RegisterRouter.scala:87:24] wire out_wivalid_14; // @[RegisterRouter.scala:87:24] wire out_wivalid_15; // @[RegisterRouter.scala:87:24] wire out_wivalid_16; // @[RegisterRouter.scala:87:24] wire out_wivalid_17; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] wire out_roready_0; // @[RegisterRouter.scala:87:24] wire out_roready_1; // @[RegisterRouter.scala:87:24] wire out_roready_2; // @[RegisterRouter.scala:87:24] wire out_roready_3; // @[RegisterRouter.scala:87:24] wire out_roready_4; // @[RegisterRouter.scala:87:24] wire out_roready_5; // @[RegisterRouter.scala:87:24] wire out_roready_6; // @[RegisterRouter.scala:87:24] wire out_roready_7; // @[RegisterRouter.scala:87:24] wire out_roready_8; // @[RegisterRouter.scala:87:24] wire out_roready_9; // @[RegisterRouter.scala:87:24] wire out_roready_10; // @[RegisterRouter.scala:87:24] wire out_roready_11; // @[RegisterRouter.scala:87:24] wire out_roready_12; // @[RegisterRouter.scala:87:24] wire out_roready_13; // @[RegisterRouter.scala:87:24] wire out_roready_14; // @[RegisterRouter.scala:87:24] wire out_roready_15; // @[RegisterRouter.scala:87:24] wire out_roready_16; // @[RegisterRouter.scala:87:24] wire out_roready_17; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] wire out_woready_0; // @[RegisterRouter.scala:87:24] wire out_woready_1; // @[RegisterRouter.scala:87:24] wire out_woready_2; // @[RegisterRouter.scala:87:24] wire out_woready_3; // @[RegisterRouter.scala:87:24] wire out_woready_4; // @[RegisterRouter.scala:87:24] wire out_woready_5; // @[RegisterRouter.scala:87:24] wire out_woready_6; // @[RegisterRouter.scala:87:24] wire out_woready_7; // @[RegisterRouter.scala:87:24] wire out_woready_8; // @[RegisterRouter.scala:87:24] wire out_woready_9; // @[RegisterRouter.scala:87:24] wire out_woready_10; // @[RegisterRouter.scala:87:24] wire out_woready_11; // @[RegisterRouter.scala:87:24] wire out_woready_12; // @[RegisterRouter.scala:87:24] wire out_woready_13; // @[RegisterRouter.scala:87:24] wire out_woready_14; // @[RegisterRouter.scala:87:24] wire out_woready_15; // @[RegisterRouter.scala:87:24] wire out_woready_16; // @[RegisterRouter.scala:87:24] wire out_woready_17; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_8 = {8{_out_frontMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_9 = {8{_out_frontMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_10 = {8{_out_frontMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_11 = {8{_out_frontMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_12 = {8{_out_frontMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_13 = {8{_out_frontMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_14 = {8{_out_frontMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_15 = {8{_out_frontMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_lo = {_out_frontMask_T_9, _out_frontMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_hi = {_out_frontMask_T_11, _out_frontMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_lo = {out_frontMask_lo_hi, out_frontMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_lo = {_out_frontMask_T_13, _out_frontMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_hi = {_out_frontMask_T_15, _out_frontMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_hi = {out_frontMask_hi_hi, out_frontMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_frontMask = {out_frontMask_hi, out_frontMask_lo}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_8 = {8{_out_backMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_9 = {8{_out_backMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_10 = {8{_out_backMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_11 = {8{_out_backMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_12 = {8{_out_backMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_13 = {8{_out_backMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_14 = {8{_out_backMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_15 = {8{_out_backMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_lo = {_out_backMask_T_9, _out_backMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_hi = {_out_backMask_T_11, _out_backMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_lo = {out_backMask_lo_hi, out_backMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_lo = {_out_backMask_T_13, _out_backMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_hi = {_out_backMask_T_15, _out_backMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_hi = {out_backMask_hi_hi, out_backMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_backMask = {out_backMask_hi, out_backMask_lo}; // @[RegisterRouter.scala:87:24] wire _out_rimask_T = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire out_rimask = _out_rimask_T; // @[RegisterRouter.scala:87:24] wire out_wimask = _out_wimask_T; // @[RegisterRouter.scala:87:24] wire _out_romask_T = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire out_romask = _out_romask_T; // @[RegisterRouter.scala:87:24] wire out_womask = _out_womask_T; // @[RegisterRouter.scala:87:24] wire out_f_rivalid = out_rivalid_0 & out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_7 = out_f_rivalid; // @[RegisterRouter.scala:87:24] wire out_f_roready = out_roready_0 & out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_8 = out_f_roready; // @[RegisterRouter.scala:87:24] wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_9 = out_f_wivalid; // @[RegisterRouter.scala:87:24] wire out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala:87:24] wire _out_T_10 = out_f_woready; // @[RegisterRouter.scala:87:24] wire _out_T_6 = out_front_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_11 = ~out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_12 = ~out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_13 = ~out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_14 = ~out_womask; // @[RegisterRouter.scala:87:24] wire _out_T_16 = _out_T_15; // @[RegisterRouter.scala:87:24] wire _out_prepend_T = _out_T_16; // @[RegisterRouter.scala:87:24] wire [30:0] _out_rimask_T_1 = out_frontMask[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_wimask_T_1 = out_frontMask[31:1]; // @[RegisterRouter.scala:87:24] wire out_rimask_1 = |_out_rimask_T_1; // @[RegisterRouter.scala:87:24] wire out_wimask_1 = &_out_wimask_T_1; // @[RegisterRouter.scala:87:24] wire [30:0] _out_romask_T_1 = out_backMask[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_womask_T_1 = out_backMask[31:1]; // @[RegisterRouter.scala:87:24] wire out_romask_1 = |_out_romask_T_1; // @[RegisterRouter.scala:87:24] wire out_womask_1 = &_out_womask_T_1; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1 = out_rivalid_1 & out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_18 = out_f_rivalid_1; // @[RegisterRouter.scala:87:24] wire out_f_roready_1 = out_roready_1 & out_romask_1; // @[RegisterRouter.scala:87:24] wire _out_T_19 = out_f_roready_1; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1 = out_wivalid_1 & out_wimask_1; // @[RegisterRouter.scala:87:24] wire out_f_woready_1 = out_woready_1 & out_womask_1; // @[RegisterRouter.scala:87:24] wire [30:0] _out_T_17 = out_front_bits_data[31:1]; // @[RegisterRouter.scala:87:24] wire _out_T_20 = ~out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_21 = ~out_wimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_22 = ~out_romask_1; // @[RegisterRouter.scala:87:24] wire _out_T_23 = ~out_womask_1; // @[RegisterRouter.scala:87:24] wire [1:0] out_prepend = {1'h0, _out_prepend_T}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_24 = {30'h0, out_prepend}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_25 = _out_T_24; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_2 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_2 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_10 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_10 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire out_rimask_2 = |_out_rimask_T_2; // @[RegisterRouter.scala:87:24] wire out_wimask_2 = &_out_wimask_T_2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_2 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_2 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_10 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_10 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire out_romask_2 = |_out_romask_T_2; // @[RegisterRouter.scala:87:24] wire out_womask_2 = &_out_womask_T_2; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_2 = out_rivalid_2 & out_rimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_27 = out_f_rivalid_2; // @[RegisterRouter.scala:87:24] wire out_f_roready_2 = out_roready_2 & out_romask_2; // @[RegisterRouter.scala:87:24] wire _out_T_28 = out_f_roready_2; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_2 = out_wivalid_2 & out_wimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_29 = out_f_wivalid_2; // @[RegisterRouter.scala:87:24] assign out_f_woready_2 = out_woready_2 & out_womask_2; // @[RegisterRouter.scala:87:24] assign valids_1_0 = out_f_woready_2; // @[RegisterRouter.scala:87:24] wire _out_T_30 = out_f_woready_2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_26 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_114 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] assign newBytes_1_0 = out_f_woready_2 ? _out_T_26 : oldBytes_1_0; // @[RegisterRouter.scala:87:24] wire _out_T_31 = ~out_rimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_32 = ~out_wimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_33 = ~out_romask_2; // @[RegisterRouter.scala:87:24] wire _out_T_34 = ~out_womask_2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_36 = _out_T_35; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1 = _out_T_36; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_3 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_3 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_11 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_11 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire out_rimask_3 = |_out_rimask_T_3; // @[RegisterRouter.scala:87:24] wire out_wimask_3 = &_out_wimask_T_3; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_3 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_3 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_11 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_11 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire out_romask_3 = |_out_romask_T_3; // @[RegisterRouter.scala:87:24] wire out_womask_3 = &_out_womask_T_3; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_3 = out_rivalid_3 & out_rimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_38 = out_f_rivalid_3; // @[RegisterRouter.scala:87:24] wire out_f_roready_3 = out_roready_3 & out_romask_3; // @[RegisterRouter.scala:87:24] wire _out_T_39 = out_f_roready_3; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_3 = out_wivalid_3 & out_wimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_40 = out_f_wivalid_3; // @[RegisterRouter.scala:87:24] assign out_f_woready_3 = out_woready_3 & out_womask_3; // @[RegisterRouter.scala:87:24] assign valids_1_1 = out_f_woready_3; // @[RegisterRouter.scala:87:24] wire _out_T_41 = out_f_woready_3; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_37 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_125 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] assign newBytes_1_1 = out_f_woready_3 ? _out_T_37 : oldBytes_1_1; // @[RegisterRouter.scala:87:24] wire _out_T_42 = ~out_rimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_43 = ~out_wimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_44 = ~out_romask_3; // @[RegisterRouter.scala:87:24] wire _out_T_45 = ~out_womask_3; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1 = {oldBytes_1_1, _out_prepend_T_1}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_46 = out_prepend_1; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_47 = _out_T_46; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_2 = _out_T_47; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_4 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_4 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_12 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_12 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire out_rimask_4 = |_out_rimask_T_4; // @[RegisterRouter.scala:87:24] wire out_wimask_4 = &_out_wimask_T_4; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_4 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_4 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_12 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_12 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire out_romask_4 = |_out_romask_T_4; // @[RegisterRouter.scala:87:24] wire out_womask_4 = &_out_womask_T_4; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_4 = out_rivalid_4 & out_rimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_49 = out_f_rivalid_4; // @[RegisterRouter.scala:87:24] wire out_f_roready_4 = out_roready_4 & out_romask_4; // @[RegisterRouter.scala:87:24] wire _out_T_50 = out_f_roready_4; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_4 = out_wivalid_4 & out_wimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_51 = out_f_wivalid_4; // @[RegisterRouter.scala:87:24] assign out_f_woready_4 = out_woready_4 & out_womask_4; // @[RegisterRouter.scala:87:24] assign valids_1_2 = out_f_woready_4; // @[RegisterRouter.scala:87:24] wire _out_T_52 = out_f_woready_4; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_48 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_136 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] assign newBytes_1_2 = out_f_woready_4 ? _out_T_48 : oldBytes_1_2; // @[RegisterRouter.scala:87:24] wire _out_T_53 = ~out_rimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_54 = ~out_wimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_55 = ~out_romask_4; // @[RegisterRouter.scala:87:24] wire _out_T_56 = ~out_womask_4; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_2 = {oldBytes_1_2, _out_prepend_T_2}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_57 = out_prepend_2; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_58 = _out_T_57; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_3 = _out_T_58; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_5 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_5 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_13 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_13 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire out_rimask_5 = |_out_rimask_T_5; // @[RegisterRouter.scala:87:24] wire out_wimask_5 = &_out_wimask_T_5; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_5 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_5 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_13 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_13 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire out_romask_5 = |_out_romask_T_5; // @[RegisterRouter.scala:87:24] wire out_womask_5 = &_out_womask_T_5; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_5 = out_rivalid_5 & out_rimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_60 = out_f_rivalid_5; // @[RegisterRouter.scala:87:24] wire out_f_roready_5 = out_roready_5 & out_romask_5; // @[RegisterRouter.scala:87:24] wire _out_T_61 = out_f_roready_5; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_5 = out_wivalid_5 & out_wimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_62 = out_f_wivalid_5; // @[RegisterRouter.scala:87:24] assign out_f_woready_5 = out_woready_5 & out_womask_5; // @[RegisterRouter.scala:87:24] assign valids_1_3 = out_f_woready_5; // @[RegisterRouter.scala:87:24] wire _out_T_63 = out_f_woready_5; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_59 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_147 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] assign newBytes_1_3 = out_f_woready_5 ? _out_T_59 : oldBytes_1_3; // @[RegisterRouter.scala:87:24] wire _out_T_64 = ~out_rimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_65 = ~out_wimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_66 = ~out_romask_5; // @[RegisterRouter.scala:87:24] wire _out_T_67 = ~out_womask_5; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_3 = {oldBytes_1_3, _out_prepend_T_3}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_68 = out_prepend_3; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_69 = _out_T_68; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_4 = _out_T_69; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_6 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_6 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_14 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_14 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24] wire out_rimask_6 = |_out_rimask_T_6; // @[RegisterRouter.scala:87:24] wire out_wimask_6 = &_out_wimask_T_6; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_6 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_6 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_14 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_14 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24] wire out_romask_6 = |_out_romask_T_6; // @[RegisterRouter.scala:87:24] wire out_womask_6 = &_out_womask_T_6; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_6 = out_rivalid_6 & out_rimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_71 = out_f_rivalid_6; // @[RegisterRouter.scala:87:24] wire out_f_roready_6 = out_roready_6 & out_romask_6; // @[RegisterRouter.scala:87:24] wire _out_T_72 = out_f_roready_6; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_6 = out_wivalid_6 & out_wimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_73 = out_f_wivalid_6; // @[RegisterRouter.scala:87:24] assign out_f_woready_6 = out_woready_6 & out_womask_6; // @[RegisterRouter.scala:87:24] assign valids_1_4 = out_f_woready_6; // @[RegisterRouter.scala:87:24] wire _out_T_74 = out_f_woready_6; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_70 = out_front_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_158 = out_front_bits_data[39:32]; // @[RegisterRouter.scala:87:24] assign newBytes_1_4 = out_f_woready_6 ? _out_T_70 : oldBytes_1_4; // @[RegisterRouter.scala:87:24] wire _out_T_75 = ~out_rimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_76 = ~out_wimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_77 = ~out_romask_6; // @[RegisterRouter.scala:87:24] wire _out_T_78 = ~out_womask_6; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_4 = {oldBytes_1_4, _out_prepend_T_4}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_79 = out_prepend_4; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_80 = _out_T_79; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_5 = _out_T_80; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_7 = out_frontMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_7 = out_frontMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_15 = out_frontMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_15 = out_frontMask[47:40]; // @[RegisterRouter.scala:87:24] wire out_rimask_7 = |_out_rimask_T_7; // @[RegisterRouter.scala:87:24] wire out_wimask_7 = &_out_wimask_T_7; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_7 = out_backMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_7 = out_backMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_15 = out_backMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_15 = out_backMask[47:40]; // @[RegisterRouter.scala:87:24] wire out_romask_7 = |_out_romask_T_7; // @[RegisterRouter.scala:87:24] wire out_womask_7 = &_out_womask_T_7; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_7 = out_rivalid_7 & out_rimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_82 = out_f_rivalid_7; // @[RegisterRouter.scala:87:24] wire out_f_roready_7 = out_roready_7 & out_romask_7; // @[RegisterRouter.scala:87:24] wire _out_T_83 = out_f_roready_7; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_7 = out_wivalid_7 & out_wimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_84 = out_f_wivalid_7; // @[RegisterRouter.scala:87:24] assign out_f_woready_7 = out_woready_7 & out_womask_7; // @[RegisterRouter.scala:87:24] assign valids_1_5 = out_f_woready_7; // @[RegisterRouter.scala:87:24] wire _out_T_85 = out_f_woready_7; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_81 = out_front_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_169 = out_front_bits_data[47:40]; // @[RegisterRouter.scala:87:24] assign newBytes_1_5 = out_f_woready_7 ? _out_T_81 : oldBytes_1_5; // @[RegisterRouter.scala:87:24] wire _out_T_86 = ~out_rimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_87 = ~out_wimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_88 = ~out_romask_7; // @[RegisterRouter.scala:87:24] wire _out_T_89 = ~out_womask_7; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_5 = {oldBytes_1_5, _out_prepend_T_5}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_90 = out_prepend_5; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_91 = _out_T_90; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_6 = _out_T_91; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_8 = out_frontMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_8 = out_frontMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_16 = out_frontMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_16 = out_frontMask[55:48]; // @[RegisterRouter.scala:87:24] wire out_rimask_8 = |_out_rimask_T_8; // @[RegisterRouter.scala:87:24] wire out_wimask_8 = &_out_wimask_T_8; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_8 = out_backMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_8 = out_backMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_16 = out_backMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_16 = out_backMask[55:48]; // @[RegisterRouter.scala:87:24] wire out_romask_8 = |_out_romask_T_8; // @[RegisterRouter.scala:87:24] wire out_womask_8 = &_out_womask_T_8; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_8 = out_rivalid_8 & out_rimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_93 = out_f_rivalid_8; // @[RegisterRouter.scala:87:24] wire out_f_roready_8 = out_roready_8 & out_romask_8; // @[RegisterRouter.scala:87:24] wire _out_T_94 = out_f_roready_8; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_8 = out_wivalid_8 & out_wimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_95 = out_f_wivalid_8; // @[RegisterRouter.scala:87:24] assign out_f_woready_8 = out_woready_8 & out_womask_8; // @[RegisterRouter.scala:87:24] assign valids_1_6 = out_f_woready_8; // @[RegisterRouter.scala:87:24] wire _out_T_96 = out_f_woready_8; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_92 = out_front_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_180 = out_front_bits_data[55:48]; // @[RegisterRouter.scala:87:24] assign newBytes_1_6 = out_f_woready_8 ? _out_T_92 : oldBytes_1_6; // @[RegisterRouter.scala:87:24] wire _out_T_97 = ~out_rimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_98 = ~out_wimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_99 = ~out_romask_8; // @[RegisterRouter.scala:87:24] wire _out_T_100 = ~out_womask_8; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_6 = {oldBytes_1_6, _out_prepend_T_6}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_101 = out_prepend_6; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_102 = _out_T_101; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_7 = _out_T_102; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_9 = out_frontMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_9 = out_frontMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_17 = out_frontMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_17 = out_frontMask[63:56]; // @[RegisterRouter.scala:87:24] wire out_rimask_9 = |_out_rimask_T_9; // @[RegisterRouter.scala:87:24] wire out_wimask_9 = &_out_wimask_T_9; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_9 = out_backMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_9 = out_backMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_17 = out_backMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_17 = out_backMask[63:56]; // @[RegisterRouter.scala:87:24] wire out_romask_9 = |_out_romask_T_9; // @[RegisterRouter.scala:87:24] wire out_womask_9 = &_out_womask_T_9; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_9 = out_rivalid_9 & out_rimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_104 = out_f_rivalid_9; // @[RegisterRouter.scala:87:24] wire out_f_roready_9 = out_roready_9 & out_romask_9; // @[RegisterRouter.scala:87:24] wire _out_T_105 = out_f_roready_9; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_9 = out_wivalid_9 & out_wimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_106 = out_f_wivalid_9; // @[RegisterRouter.scala:87:24] assign out_f_woready_9 = out_woready_9 & out_womask_9; // @[RegisterRouter.scala:87:24] assign valids_1_7 = out_f_woready_9; // @[RegisterRouter.scala:87:24] wire _out_T_107 = out_f_woready_9; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_103 = out_front_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_191 = out_front_bits_data[63:56]; // @[RegisterRouter.scala:87:24] assign newBytes_1_7 = out_f_woready_9 ? _out_T_103 : oldBytes_1_7; // @[RegisterRouter.scala:87:24] wire _out_T_108 = ~out_rimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_109 = ~out_wimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_110 = ~out_romask_9; // @[RegisterRouter.scala:87:24] wire _out_T_111 = ~out_womask_9; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_7 = {oldBytes_1_7, _out_prepend_T_7}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_112 = out_prepend_7; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_113 = _out_T_112; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_1_2 = _out_T_113; // @[MuxLiteral.scala:49:48] wire out_rimask_10 = |_out_rimask_T_10; // @[RegisterRouter.scala:87:24] wire out_wimask_10 = &_out_wimask_T_10; // @[RegisterRouter.scala:87:24] wire out_romask_10 = |_out_romask_T_10; // @[RegisterRouter.scala:87:24] wire out_womask_10 = &_out_womask_T_10; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_10 = out_rivalid_10 & out_rimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_115 = out_f_rivalid_10; // @[RegisterRouter.scala:87:24] wire out_f_roready_10 = out_roready_10 & out_romask_10; // @[RegisterRouter.scala:87:24] wire _out_T_116 = out_f_roready_10; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_10 = out_wivalid_10 & out_wimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_117 = out_f_wivalid_10; // @[RegisterRouter.scala:87:24] assign out_f_woready_10 = out_woready_10 & out_womask_10; // @[RegisterRouter.scala:87:24] assign valids_0 = out_f_woready_10; // @[RegisterRouter.scala:87:24] wire _out_T_118 = out_f_woready_10; // @[RegisterRouter.scala:87:24] assign newBytes_0 = out_f_woready_10 ? _out_T_114 : oldBytes_0; // @[RegisterRouter.scala:87:24] wire _out_T_119 = ~out_rimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_120 = ~out_wimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_121 = ~out_romask_10; // @[RegisterRouter.scala:87:24] wire _out_T_122 = ~out_womask_10; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_124 = _out_T_123; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_8 = _out_T_124; // @[RegisterRouter.scala:87:24] wire out_rimask_11 = |_out_rimask_T_11; // @[RegisterRouter.scala:87:24] wire out_wimask_11 = &_out_wimask_T_11; // @[RegisterRouter.scala:87:24] wire out_romask_11 = |_out_romask_T_11; // @[RegisterRouter.scala:87:24] wire out_womask_11 = &_out_womask_T_11; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_11 = out_rivalid_11 & out_rimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_126 = out_f_rivalid_11; // @[RegisterRouter.scala:87:24] wire out_f_roready_11 = out_roready_11 & out_romask_11; // @[RegisterRouter.scala:87:24] wire _out_T_127 = out_f_roready_11; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_11 = out_wivalid_11 & out_wimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_128 = out_f_wivalid_11; // @[RegisterRouter.scala:87:24] assign out_f_woready_11 = out_woready_11 & out_womask_11; // @[RegisterRouter.scala:87:24] assign valids_1 = out_f_woready_11; // @[RegisterRouter.scala:87:24] wire _out_T_129 = out_f_woready_11; // @[RegisterRouter.scala:87:24] assign newBytes_1 = out_f_woready_11 ? _out_T_125 : oldBytes_1; // @[RegisterRouter.scala:87:24] wire _out_T_130 = ~out_rimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_131 = ~out_wimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_132 = ~out_romask_11; // @[RegisterRouter.scala:87:24] wire _out_T_133 = ~out_womask_11; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_8 = {oldBytes_1, _out_prepend_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_134 = out_prepend_8; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_135 = _out_T_134; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_9 = _out_T_135; // @[RegisterRouter.scala:87:24] wire out_rimask_12 = |_out_rimask_T_12; // @[RegisterRouter.scala:87:24] wire out_wimask_12 = &_out_wimask_T_12; // @[RegisterRouter.scala:87:24] wire out_romask_12 = |_out_romask_T_12; // @[RegisterRouter.scala:87:24] wire out_womask_12 = &_out_womask_T_12; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_12 = out_rivalid_12 & out_rimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_137 = out_f_rivalid_12; // @[RegisterRouter.scala:87:24] wire out_f_roready_12 = out_roready_12 & out_romask_12; // @[RegisterRouter.scala:87:24] wire _out_T_138 = out_f_roready_12; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_12 = out_wivalid_12 & out_wimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_139 = out_f_wivalid_12; // @[RegisterRouter.scala:87:24] assign out_f_woready_12 = out_woready_12 & out_womask_12; // @[RegisterRouter.scala:87:24] assign valids_2 = out_f_woready_12; // @[RegisterRouter.scala:87:24] wire _out_T_140 = out_f_woready_12; // @[RegisterRouter.scala:87:24] assign newBytes_2 = out_f_woready_12 ? _out_T_136 : oldBytes_2; // @[RegisterRouter.scala:87:24] wire _out_T_141 = ~out_rimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_142 = ~out_wimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_143 = ~out_romask_12; // @[RegisterRouter.scala:87:24] wire _out_T_144 = ~out_womask_12; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_9 = {oldBytes_2, _out_prepend_T_9}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_145 = out_prepend_9; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_146 = _out_T_145; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_10 = _out_T_146; // @[RegisterRouter.scala:87:24] wire out_rimask_13 = |_out_rimask_T_13; // @[RegisterRouter.scala:87:24] wire out_wimask_13 = &_out_wimask_T_13; // @[RegisterRouter.scala:87:24] wire out_romask_13 = |_out_romask_T_13; // @[RegisterRouter.scala:87:24] wire out_womask_13 = &_out_womask_T_13; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_13 = out_rivalid_13 & out_rimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_148 = out_f_rivalid_13; // @[RegisterRouter.scala:87:24] wire out_f_roready_13 = out_roready_13 & out_romask_13; // @[RegisterRouter.scala:87:24] wire _out_T_149 = out_f_roready_13; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_13 = out_wivalid_13 & out_wimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_150 = out_f_wivalid_13; // @[RegisterRouter.scala:87:24] assign out_f_woready_13 = out_woready_13 & out_womask_13; // @[RegisterRouter.scala:87:24] assign valids_3 = out_f_woready_13; // @[RegisterRouter.scala:87:24] wire _out_T_151 = out_f_woready_13; // @[RegisterRouter.scala:87:24] assign newBytes_3 = out_f_woready_13 ? _out_T_147 : oldBytes_3; // @[RegisterRouter.scala:87:24] wire _out_T_152 = ~out_rimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_153 = ~out_wimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_154 = ~out_romask_13; // @[RegisterRouter.scala:87:24] wire _out_T_155 = ~out_womask_13; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_10 = {oldBytes_3, _out_prepend_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_156 = out_prepend_10; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_157 = _out_T_156; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_11 = _out_T_157; // @[RegisterRouter.scala:87:24] wire out_rimask_14 = |_out_rimask_T_14; // @[RegisterRouter.scala:87:24] wire out_wimask_14 = &_out_wimask_T_14; // @[RegisterRouter.scala:87:24] wire out_romask_14 = |_out_romask_T_14; // @[RegisterRouter.scala:87:24] wire out_womask_14 = &_out_womask_T_14; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_14 = out_rivalid_14 & out_rimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_159 = out_f_rivalid_14; // @[RegisterRouter.scala:87:24] wire out_f_roready_14 = out_roready_14 & out_romask_14; // @[RegisterRouter.scala:87:24] wire _out_T_160 = out_f_roready_14; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_14 = out_wivalid_14 & out_wimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_161 = out_f_wivalid_14; // @[RegisterRouter.scala:87:24] assign out_f_woready_14 = out_woready_14 & out_womask_14; // @[RegisterRouter.scala:87:24] assign valids_4 = out_f_woready_14; // @[RegisterRouter.scala:87:24] wire _out_T_162 = out_f_woready_14; // @[RegisterRouter.scala:87:24] assign newBytes_4 = out_f_woready_14 ? _out_T_158 : oldBytes_4; // @[RegisterRouter.scala:87:24] wire _out_T_163 = ~out_rimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_164 = ~out_wimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_165 = ~out_romask_14; // @[RegisterRouter.scala:87:24] wire _out_T_166 = ~out_womask_14; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_11 = {oldBytes_4, _out_prepend_T_11}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_167 = out_prepend_11; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_168 = _out_T_167; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_12 = _out_T_168; // @[RegisterRouter.scala:87:24] wire out_rimask_15 = |_out_rimask_T_15; // @[RegisterRouter.scala:87:24] wire out_wimask_15 = &_out_wimask_T_15; // @[RegisterRouter.scala:87:24] wire out_romask_15 = |_out_romask_T_15; // @[RegisterRouter.scala:87:24] wire out_womask_15 = &_out_womask_T_15; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_15 = out_rivalid_15 & out_rimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_170 = out_f_rivalid_15; // @[RegisterRouter.scala:87:24] wire out_f_roready_15 = out_roready_15 & out_romask_15; // @[RegisterRouter.scala:87:24] wire _out_T_171 = out_f_roready_15; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_15 = out_wivalid_15 & out_wimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_172 = out_f_wivalid_15; // @[RegisterRouter.scala:87:24] assign out_f_woready_15 = out_woready_15 & out_womask_15; // @[RegisterRouter.scala:87:24] assign valids_5 = out_f_woready_15; // @[RegisterRouter.scala:87:24] wire _out_T_173 = out_f_woready_15; // @[RegisterRouter.scala:87:24] assign newBytes_5 = out_f_woready_15 ? _out_T_169 : oldBytes_5; // @[RegisterRouter.scala:87:24] wire _out_T_174 = ~out_rimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_175 = ~out_wimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_176 = ~out_romask_15; // @[RegisterRouter.scala:87:24] wire _out_T_177 = ~out_womask_15; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_12 = {oldBytes_5, _out_prepend_T_12}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_178 = out_prepend_12; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_179 = _out_T_178; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_13 = _out_T_179; // @[RegisterRouter.scala:87:24] wire out_rimask_16 = |_out_rimask_T_16; // @[RegisterRouter.scala:87:24] wire out_wimask_16 = &_out_wimask_T_16; // @[RegisterRouter.scala:87:24] wire out_romask_16 = |_out_romask_T_16; // @[RegisterRouter.scala:87:24] wire out_womask_16 = &_out_womask_T_16; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_16 = out_rivalid_16 & out_rimask_16; // @[RegisterRouter.scala:87:24] wire _out_T_181 = out_f_rivalid_16; // @[RegisterRouter.scala:87:24] wire out_f_roready_16 = out_roready_16 & out_romask_16; // @[RegisterRouter.scala:87:24] wire _out_T_182 = out_f_roready_16; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_16 = out_wivalid_16 & out_wimask_16; // @[RegisterRouter.scala:87:24] wire _out_T_183 = out_f_wivalid_16; // @[RegisterRouter.scala:87:24] assign out_f_woready_16 = out_woready_16 & out_womask_16; // @[RegisterRouter.scala:87:24] assign valids_6 = out_f_woready_16; // @[RegisterRouter.scala:87:24] wire _out_T_184 = out_f_woready_16; // @[RegisterRouter.scala:87:24] assign newBytes_6 = out_f_woready_16 ? _out_T_180 : oldBytes_6; // @[RegisterRouter.scala:87:24] wire _out_T_185 = ~out_rimask_16; // @[RegisterRouter.scala:87:24] wire _out_T_186 = ~out_wimask_16; // @[RegisterRouter.scala:87:24] wire _out_T_187 = ~out_romask_16; // @[RegisterRouter.scala:87:24] wire _out_T_188 = ~out_womask_16; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_13 = {oldBytes_6, _out_prepend_T_13}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_189 = out_prepend_13; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_190 = _out_T_189; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_14 = _out_T_190; // @[RegisterRouter.scala:87:24] wire out_rimask_17 = |_out_rimask_T_17; // @[RegisterRouter.scala:87:24] wire out_wimask_17 = &_out_wimask_T_17; // @[RegisterRouter.scala:87:24] wire out_romask_17 = |_out_romask_T_17; // @[RegisterRouter.scala:87:24] wire out_womask_17 = &_out_womask_T_17; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_17 = out_rivalid_17 & out_rimask_17; // @[RegisterRouter.scala:87:24] wire _out_T_192 = out_f_rivalid_17; // @[RegisterRouter.scala:87:24] wire out_f_roready_17 = out_roready_17 & out_romask_17; // @[RegisterRouter.scala:87:24] wire _out_T_193 = out_f_roready_17; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_17 = out_wivalid_17 & out_wimask_17; // @[RegisterRouter.scala:87:24] wire _out_T_194 = out_f_wivalid_17; // @[RegisterRouter.scala:87:24] assign out_f_woready_17 = out_woready_17 & out_womask_17; // @[RegisterRouter.scala:87:24] assign valids_7 = out_f_woready_17; // @[RegisterRouter.scala:87:24] wire _out_T_195 = out_f_woready_17; // @[RegisterRouter.scala:87:24] assign newBytes_7 = out_f_woready_17 ? _out_T_191 : oldBytes_7; // @[RegisterRouter.scala:87:24] wire _out_T_196 = ~out_rimask_17; // @[RegisterRouter.scala:87:24] wire _out_T_197 = ~out_wimask_17; // @[RegisterRouter.scala:87:24] wire _out_T_198 = ~out_romask_17; // @[RegisterRouter.scala:87:24] wire _out_T_199 = ~out_womask_17; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_14 = {oldBytes_7, _out_prepend_T_14}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_200 = out_prepend_14; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_201 = _out_T_200; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_1_1 = _out_T_201; // @[MuxLiteral.scala:49:48] wire _out_iindex_T = out_front_bits_index[0]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T = out_front_bits_index[0]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_1 = out_front_bits_index[1]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_1 = out_front_bits_index[1]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_2 = out_front_bits_index[2]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_2 = out_front_bits_index[2]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_3 = out_front_bits_index[3]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_3 = out_front_bits_index[3]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_4 = out_front_bits_index[4]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_4 = out_front_bits_index[4]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_5 = out_front_bits_index[5]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_5 = out_front_bits_index[5]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_6 = out_front_bits_index[6]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_6 = out_front_bits_index[6]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_7 = out_front_bits_index[7]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_7 = out_front_bits_index[7]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_8 = out_front_bits_index[8]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_8 = out_front_bits_index[8]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_9 = out_front_bits_index[9]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_9 = out_front_bits_index[9]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_10 = out_front_bits_index[10]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_10 = out_front_bits_index[10]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_11 = out_front_bits_index[11]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_11 = out_front_bits_index[11]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_12 = out_front_bits_index[12]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_12 = out_front_bits_index[12]; // @[RegisterRouter.scala:87:24] wire [1:0] out_iindex = {_out_iindex_T_12, _out_iindex_T_11}; // @[RegisterRouter.scala:87:24] wire [1:0] out_oindex = {_out_oindex_T_12, _out_oindex_T_11}; // @[RegisterRouter.scala:87:24] wire [3:0] _out_frontSel_T = 4'h1 << out_iindex; // @[OneHot.scala:58:35] wire out_frontSel_0 = _out_frontSel_T[0]; // @[OneHot.scala:58:35] wire out_frontSel_1 = _out_frontSel_T[1]; // @[OneHot.scala:58:35] wire out_frontSel_2 = _out_frontSel_T[2]; // @[OneHot.scala:58:35] wire out_frontSel_3 = _out_frontSel_T[3]; // @[OneHot.scala:58:35] wire [3:0] _out_backSel_T = 4'h1 << out_oindex; // @[OneHot.scala:58:35] wire out_backSel_0 = _out_backSel_T[0]; // @[OneHot.scala:58:35] wire out_backSel_1 = _out_backSel_T[1]; // @[OneHot.scala:58:35] wire out_backSel_2 = _out_backSel_T[2]; // @[OneHot.scala:58:35] wire out_backSel_3 = _out_backSel_T[3]; // @[OneHot.scala:58:35] wire _GEN_2 = in_valid & out_front_ready; // @[RegisterRouter.scala:73:18, :87:24] wire _out_rifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T = _GEN_2; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T = _GEN_2; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1 = _out_rifireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_2 = _out_rifireMux_T_1 & out_frontSel_0; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_3 = _out_rifireMux_T_2 & _out_T; // @[RegisterRouter.scala:87:24] assign out_rivalid_0 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_1 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_4 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_6 = _out_rifireMux_T_1 & out_frontSel_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_7 = _out_rifireMux_T_6 & _out_T_4; // @[RegisterRouter.scala:87:24] assign out_rivalid_10 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_11 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_12 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_13 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_14 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_15 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_16 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_17 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_8 = ~_out_T_4; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_10 = _out_rifireMux_T_1 & out_frontSel_2; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_11 = _out_rifireMux_T_10 & _out_T_2; // @[RegisterRouter.scala:87:24] assign out_rivalid_2 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_3 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_4 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_5 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_6 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_7 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_8 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_9 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_12 = ~_out_T_2; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_14 = _out_rifireMux_T_1 & out_frontSel_3; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_15 = _out_rifireMux_T_14; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_2 = _out_wifireMux_T & _out_wifireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_3 = _out_wifireMux_T_2 & out_frontSel_0; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_4 = _out_wifireMux_T_3 & _out_T; // @[RegisterRouter.scala:87:24] assign out_wivalid_0 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_1 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_5 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_7 = _out_wifireMux_T_2 & out_frontSel_1; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_8 = _out_wifireMux_T_7 & _out_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_10 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_11 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_12 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_13 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_14 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_15 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_16 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_17 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_9 = ~_out_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_11 = _out_wifireMux_T_2 & out_frontSel_2; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_12 = _out_wifireMux_T_11 & _out_T_2; // @[RegisterRouter.scala:87:24] assign out_wivalid_2 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_3 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_4 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_5 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_6 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_7 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_8 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_9 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_13 = ~_out_T_2; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_15 = _out_wifireMux_T_2 & out_frontSel_3; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_16 = _out_wifireMux_T_15; // @[RegisterRouter.scala:87:24] wire _GEN_3 = out_front_valid & out_ready; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T = _GEN_3; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T = _GEN_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1 = _out_rofireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_2 = _out_rofireMux_T_1 & out_backSel_0; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_3 = _out_rofireMux_T_2 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_roready_0 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_1 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_4 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_6 = _out_rofireMux_T_1 & out_backSel_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_7 = _out_rofireMux_T_6 & _out_T_5; // @[RegisterRouter.scala:87:24] assign out_roready_10 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_11 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_12 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_13 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_14 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_15 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_16 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_17 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_8 = ~_out_T_5; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_10 = _out_rofireMux_T_1 & out_backSel_2; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_11 = _out_rofireMux_T_10 & _out_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_2 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_3 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_4 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_5 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_6 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_7 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_8 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_9 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_12 = ~_out_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_14 = _out_rofireMux_T_1 & out_backSel_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_15 = _out_rofireMux_T_14; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_2 = _out_wofireMux_T & _out_wofireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_3 = _out_wofireMux_T_2 & out_backSel_0; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_4 = _out_wofireMux_T_3 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_woready_0 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_1 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_5 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_7 = _out_wofireMux_T_2 & out_backSel_1; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_8 = _out_wofireMux_T_7 & _out_T_5; // @[RegisterRouter.scala:87:24] assign out_woready_10 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_11 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_12 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_13 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_14 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_15 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_16 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_17 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_9 = ~_out_T_5; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_11 = _out_wofireMux_T_2 & out_backSel_2; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_12 = _out_wofireMux_T_11 & _out_T_3; // @[RegisterRouter.scala:87:24] assign out_woready_2 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_3 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_4 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_5 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_6 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_7 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_8 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_9 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_13 = ~_out_T_3; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_15 = _out_wofireMux_T_2 & out_backSel_3; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_16 = _out_wofireMux_T_15; // @[RegisterRouter.scala:87:24] assign in_ready = _out_in_ready_T; // @[RegisterRouter.scala:73:18, :87:24] assign out_front_valid = _out_front_valid_T; // @[RegisterRouter.scala:87:24] assign out_front_ready = _out_front_ready_T; // @[RegisterRouter.scala:87:24] assign out_valid = _out_out_valid_T; // @[RegisterRouter.scala:87:24] wire [3:0] _GEN_4 = {{1'h1}, {_out_out_bits_data_WIRE_2}, {_out_out_bits_data_WIRE_1}, {_out_out_bits_data_WIRE_0}}; // @[MuxLiteral.scala:49:{10,48}] wire _out_out_bits_data_T_1 = _GEN_4[out_oindex]; // @[MuxLiteral.scala:49:10] wire [63:0] _out_out_bits_data_WIRE_1_0 = {32'h0, _out_T_25}; // @[MuxLiteral.scala:49:48] wire [3:0][63:0] _GEN_5 = {{64'h0}, {_out_out_bits_data_WIRE_1_2}, {_out_out_bits_data_WIRE_1_1}, {_out_out_bits_data_WIRE_1_0}}; // @[MuxLiteral.scala:49:{10,48}] wire [63:0] _out_out_bits_data_T_3 = _GEN_5[out_oindex]; // @[MuxLiteral.scala:49:10] assign _out_out_bits_data_T_4 = _out_out_bits_data_T_1 ? _out_out_bits_data_T_3 : 64'h0; // @[MuxLiteral.scala:49:10] assign out_bits_data = _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24] assign nodeIn_d_bits_size = nodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign nodeIn_d_bits_source = nodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign nodeIn_d_bits_opcode = {2'h0, _nodeIn_d_bits_opcode_T}; // @[RegisterRouter.scala:105:{19,25}] always @(posedge clock) begin // @[CLINT.scala:65:9] if (reset) begin // @[CLINT.scala:65:9] time_0 <= 64'h0; // @[CLINT.scala:73:23] ipi_0 <= 1'h0; // @[CLINT.scala:78:41] end else begin // @[CLINT.scala:65:9] if (valids_1_0 | valids_1_1 | valids_1_2 | valids_1_3 | valids_1_4 | valids_1_5 | valids_1_6 | valids_1_7) // @[RegField.scala:153:29, :154:27] time_0 <= _time_T_2; // @[RegField.scala:154:52] else if (io_rtcTick_0) // @[CLINT.scala:65:9] time_0 <= _time_T_1; // @[CLINT.scala:73:23, :74:38] if (out_f_woready) // @[RegisterRouter.scala:87:24] ipi_0 <= _out_T_6; // @[RegisterRouter.scala:87:24] end if (valids_0 | valids_1 | valids_2 | valids_3 | valids_4 | valids_5 | valids_6 | valids_7) // @[RegField.scala:153:29, :154:27] timecmp_0 <= _timecmp_0_T; // @[RegField.scala:154:52] always @(posedge) TLMonitor_42 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] assign auto_int_out_0 = auto_int_out_0_0; // @[CLINT.scala:65:9] assign auto_int_out_1 = auto_int_out_1_0; // @[CLINT.scala:65:9] assign auto_in_a_ready = auto_in_a_ready_0; // @[CLINT.scala:65:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[CLINT.scala:65:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[CLINT.scala:65:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[CLINT.scala:65:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[CLINT.scala:65:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[CLINT.scala:65:9] endmodule

Generate the Verilog code corresponding to the following Chisel files. File util.scala: //****************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v3.common.{MicroOp} import boom.v3.exu.{BrUpdateInfo} /** * Object to XOR fold a input register of fullLength into a compressedLength. */ object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /** * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks */ object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask) } def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) } } /** * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. */ object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /** * Object to return a BR mask given a MicroOp mask and old BR mask. */ object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask) out } } /** * Object to check if at least 1 bit matches in two masks */ object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /** * Object to clear one bit in a mask given an index */ object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /** * Object to shift a register over by one bit and concat a new one */ object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /** * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. */ object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /** * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. */ object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc | (b-1).U) } } /** * Object to rotate a signal left by one */ object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /** * Object to sext a value to a particular length. */ object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /** * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. */ object ImmGen { import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U} def apply(ip: UInt, isel: UInt): SInt = { val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt } } /** * Object to get the FP rounding mode out of a packed immediate. */ object ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } } /** * Object to get the FP function fype from a packed immediate. * Note: only works if !(IS_B or IS_S) */ object ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } } /** * Object to see if an instruction is a JALR. */ object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /** * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). */ object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /** * Object to return the lowest bit position after the head. */ object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /** * Object to determine whether queue * index i0 is older than index i1. */ object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } /** * Set all bits at or below the highest order '1'. */ object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_|_) } } /** * Set all bits at or above the lowest order '1'. */ object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_) } } /** * Transpose a matrix of Chisel Vecs. */ object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /** * N-wide one-hot priority encoder. */ object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /** * Connect the first k of n valid input interfaces to k output interfaces. */ class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_)) val out_valids = sels map (col => col.reduce(_||_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /** * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). */ class BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v3.common.BoomModule()(p) with boom.v3.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire) val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop) uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop)) io.deq.bits := out io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop) // For flow queue behavior. if (flow) { when (io.empty) { io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop) io.deq.bits := io.enq.bits io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) do_deq := false.B when (io.deq.ready) { do_enq := false.B } } } private val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /** * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" */ def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) */ def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) */ def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) */ def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /** * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line */ def apply(strs: String*)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } File consts.scala: //****************************************************************************** // Copyright (c) 2011 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Constants //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.common.constants import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util.Str import freechips.rocketchip.rocket.RVCExpander /** * Mixin for issue queue types */ trait IQType { val IQT_SZ = 3 val IQT_INT = 1.U(IQT_SZ.W) val IQT_MEM = 2.U(IQT_SZ.W) val IQT_FP = 4.U(IQT_SZ.W) val IQT_MFP = 6.U(IQT_SZ.W) } /** * Mixin for scalar operation constants */ trait ScalarOpConstants { val X = BitPat("b?") val Y = BitPat("b1") val N = BitPat("b0") //************************************ // Extra Constants // Which branch predictor predicted us val BSRC_SZ = 2 val BSRC_1 = 0.U(BSRC_SZ.W) // 1-cycle branch pred val BSRC_2 = 1.U(BSRC_SZ.W) // 2-cycle branch pred val BSRC_3 = 2.U(BSRC_SZ.W) // 3-cycle branch pred val BSRC_C = 3.U(BSRC_SZ.W) // core branch resolution //************************************ // Control Signals // CFI types val CFI_SZ = 3 val CFI_X = 0.U(CFI_SZ.W) // Not a CFI instruction val CFI_BR = 1.U(CFI_SZ.W) // Branch val CFI_JAL = 2.U(CFI_SZ.W) // JAL val CFI_JALR = 3.U(CFI_SZ.W) // JALR // PC Select Signal val PC_PLUS4 = 0.U(2.W) // PC + 4 val PC_BRJMP = 1.U(2.W) // brjmp_target val PC_JALR = 2.U(2.W) // jump_reg_target // Branch Type val BR_N = 0.U(4.W) // Next val BR_NE = 1.U(4.W) // Branch on NotEqual val BR_EQ = 2.U(4.W) // Branch on Equal val BR_GE = 3.U(4.W) // Branch on Greater/Equal val BR_GEU = 4.U(4.W) // Branch on Greater/Equal Unsigned val BR_LT = 5.U(4.W) // Branch on Less Than val BR_LTU = 6.U(4.W) // Branch on Less Than Unsigned val BR_J = 7.U(4.W) // Jump val BR_JR = 8.U(4.W) // Jump Register // RS1 Operand Select Signal val OP1_RS1 = 0.U(2.W) // Register Source #1 val OP1_ZERO= 1.U(2.W) val OP1_PC = 2.U(2.W) val OP1_X = BitPat("b??") // RS2 Operand Select Signal val OP2_RS2 = 0.U(3.W) // Register Source #2 val OP2_IMM = 1.U(3.W) // immediate val OP2_ZERO= 2.U(3.W) // constant 0 val OP2_NEXT= 3.U(3.W) // constant 2/4 (for PC+2/4) val OP2_IMMC= 4.U(3.W) // for CSR imm found in RS1 val OP2_X = BitPat("b???") // Register File Write Enable Signal val REN_0 = false.B val REN_1 = true.B // Is 32b Word or 64b Doubldword? val SZ_DW = 1 val DW_X = true.B // Bool(xLen==64) val DW_32 = false.B val DW_64 = true.B val DW_XPR = true.B // Bool(xLen==64) // Memory Enable Signal val MEN_0 = false.B val MEN_1 = true.B val MEN_X = false.B // Immediate Extend Select val IS_I = 0.U(3.W) // I-Type (LD,ALU) val IS_S = 1.U(3.W) // S-Type (ST) val IS_B = 2.U(3.W) // SB-Type (BR) val IS_U = 3.U(3.W) // U-Type (LUI/AUIPC) val IS_J = 4.U(3.W) // UJ-Type (J/JAL) val IS_X = BitPat("b???") // Decode Stage Control Signals val RT_FIX = 0.U(2.W) val RT_FLT = 1.U(2.W) val RT_PAS = 3.U(2.W) // pass-through (prs1 := lrs1, etc) val RT_X = 2.U(2.W) // not-a-register (but shouldn't get a busy-bit, etc.) // TODO rename RT_NAR // Micro-op opcodes // TODO change micro-op opcodes into using enum val UOPC_SZ = 7 val uopX = BitPat.dontCare(UOPC_SZ) val uopNOP = 0.U(UOPC_SZ.W) val uopLD = 1.U(UOPC_SZ.W) val uopSTA = 2.U(UOPC_SZ.W) // store address generation val uopSTD = 3.U(UOPC_SZ.W) // store data generation val uopLUI = 4.U(UOPC_SZ.W) val uopADDI = 5.U(UOPC_SZ.W) val uopANDI = 6.U(UOPC_SZ.W) val uopORI = 7.U(UOPC_SZ.W) val uopXORI = 8.U(UOPC_SZ.W) val uopSLTI = 9.U(UOPC_SZ.W) val uopSLTIU= 10.U(UOPC_SZ.W) val uopSLLI = 11.U(UOPC_SZ.W) val uopSRAI = 12.U(UOPC_SZ.W) val uopSRLI = 13.U(UOPC_SZ.W) val uopSLL = 14.U(UOPC_SZ.W) val uopADD = 15.U(UOPC_SZ.W) val uopSUB = 16.U(UOPC_SZ.W) val uopSLT = 17.U(UOPC_SZ.W) val uopSLTU = 18.U(UOPC_SZ.W) val uopAND = 19.U(UOPC_SZ.W) val uopOR = 20.U(UOPC_SZ.W) val uopXOR = 21.U(UOPC_SZ.W) val uopSRA = 22.U(UOPC_SZ.W) val uopSRL = 23.U(UOPC_SZ.W) val uopBEQ = 24.U(UOPC_SZ.W) val uopBNE = 25.U(UOPC_SZ.W) val uopBGE = 26.U(UOPC_SZ.W) val uopBGEU = 27.U(UOPC_SZ.W) val uopBLT = 28.U(UOPC_SZ.W) val uopBLTU = 29.U(UOPC_SZ.W) val uopCSRRW= 30.U(UOPC_SZ.W) val uopCSRRS= 31.U(UOPC_SZ.W) val uopCSRRC= 32.U(UOPC_SZ.W) val uopCSRRWI=33.U(UOPC_SZ.W) val uopCSRRSI=34.U(UOPC_SZ.W) val uopCSRRCI=35.U(UOPC_SZ.W) val uopJ = 36.U(UOPC_SZ.W) val uopJAL = 37.U(UOPC_SZ.W) val uopJALR = 38.U(UOPC_SZ.W) val uopAUIPC= 39.U(UOPC_SZ.W) //val uopSRET = 40.U(UOPC_SZ.W) val uopCFLSH= 41.U(UOPC_SZ.W) val uopFENCE= 42.U(UOPC_SZ.W) val uopADDIW= 43.U(UOPC_SZ.W) val uopADDW = 44.U(UOPC_SZ.W) val uopSUBW = 45.U(UOPC_SZ.W) val uopSLLIW= 46.U(UOPC_SZ.W) val uopSLLW = 47.U(UOPC_SZ.W) val uopSRAIW= 48.U(UOPC_SZ.W) val uopSRAW = 49.U(UOPC_SZ.W) val uopSRLIW= 50.U(UOPC_SZ.W) val uopSRLW = 51.U(UOPC_SZ.W) val uopMUL = 52.U(UOPC_SZ.W) val uopMULH = 53.U(UOPC_SZ.W) val uopMULHU= 54.U(UOPC_SZ.W) val uopMULHSU=55.U(UOPC_SZ.W) val uopMULW = 56.U(UOPC_SZ.W) val uopDIV = 57.U(UOPC_SZ.W) val uopDIVU = 58.U(UOPC_SZ.W) val uopREM = 59.U(UOPC_SZ.W) val uopREMU = 60.U(UOPC_SZ.W) val uopDIVW = 61.U(UOPC_SZ.W) val uopDIVUW= 62.U(UOPC_SZ.W) val uopREMW = 63.U(UOPC_SZ.W) val uopREMUW= 64.U(UOPC_SZ.W) val uopFENCEI = 65.U(UOPC_SZ.W) // = 66.U(UOPC_SZ.W) val uopAMO_AG = 67.U(UOPC_SZ.W) // AMO-address gen (use normal STD for datagen) val uopFMV_W_X = 68.U(UOPC_SZ.W) val uopFMV_D_X = 69.U(UOPC_SZ.W) val uopFMV_X_W = 70.U(UOPC_SZ.W) val uopFMV_X_D = 71.U(UOPC_SZ.W) val uopFSGNJ_S = 72.U(UOPC_SZ.W) val uopFSGNJ_D = 73.U(UOPC_SZ.W) val uopFCVT_S_D = 74.U(UOPC_SZ.W) val uopFCVT_D_S = 75.U(UOPC_SZ.W) val uopFCVT_S_X = 76.U(UOPC_SZ.W) val uopFCVT_D_X = 77.U(UOPC_SZ.W) val uopFCVT_X_S = 78.U(UOPC_SZ.W) val uopFCVT_X_D = 79.U(UOPC_SZ.W) val uopCMPR_S = 80.U(UOPC_SZ.W) val uopCMPR_D = 81.U(UOPC_SZ.W) val uopFCLASS_S = 82.U(UOPC_SZ.W) val uopFCLASS_D = 83.U(UOPC_SZ.W) val uopFMINMAX_S = 84.U(UOPC_SZ.W) val uopFMINMAX_D = 85.U(UOPC_SZ.W) // = 86.U(UOPC_SZ.W) val uopFADD_S = 87.U(UOPC_SZ.W) val uopFSUB_S = 88.U(UOPC_SZ.W) val uopFMUL_S = 89.U(UOPC_SZ.W) val uopFADD_D = 90.U(UOPC_SZ.W) val uopFSUB_D = 91.U(UOPC_SZ.W) val uopFMUL_D = 92.U(UOPC_SZ.W) val uopFMADD_S = 93.U(UOPC_SZ.W) val uopFMSUB_S = 94.U(UOPC_SZ.W) val uopFNMADD_S = 95.U(UOPC_SZ.W) val uopFNMSUB_S = 96.U(UOPC_SZ.W) val uopFMADD_D = 97.U(UOPC_SZ.W) val uopFMSUB_D = 98.U(UOPC_SZ.W) val uopFNMADD_D = 99.U(UOPC_SZ.W) val uopFNMSUB_D = 100.U(UOPC_SZ.W) val uopFDIV_S = 101.U(UOPC_SZ.W) val uopFDIV_D = 102.U(UOPC_SZ.W) val uopFSQRT_S = 103.U(UOPC_SZ.W) val uopFSQRT_D = 104.U(UOPC_SZ.W) val uopWFI = 105.U(UOPC_SZ.W) // pass uop down the CSR pipeline val uopERET = 106.U(UOPC_SZ.W) // pass uop down the CSR pipeline, also is ERET val uopSFENCE = 107.U(UOPC_SZ.W) val uopROCC = 108.U(UOPC_SZ.W) val uopMOV = 109.U(UOPC_SZ.W) // conditional mov decoded from "add rd, x0, rs2" // The Bubble Instruction (Machine generated NOP) // Insert (XOR x0,x0,x0) which is different from software compiler // generated NOPs which are (ADDI x0, x0, 0). // Reasoning for this is to let visualizers and stat-trackers differentiate // between software NOPs and machine-generated Bubbles in the pipeline. val BUBBLE = (0x4033).U(32.W) def NullMicroOp()(implicit p: Parameters): boom.v3.common.MicroOp = { val uop = Wire(new boom.v3.common.MicroOp) uop := DontCare // Overridden in the following lines uop.uopc := uopNOP // maybe not required, but helps on asserts that try to catch spurious behavior uop.bypassable := false.B uop.fp_val := false.B uop.uses_stq := false.B uop.uses_ldq := false.B uop.pdst := 0.U uop.dst_rtype := RT_X val cs = Wire(new boom.v3.common.CtrlSignals()) cs := DontCare // Overridden in the following lines cs.br_type := BR_N cs.csr_cmd := freechips.rocketchip.rocket.CSR.N cs.is_load := false.B cs.is_sta := false.B cs.is_std := false.B uop.ctrl := cs uop } } /** * Mixin for RISCV constants */ trait RISCVConstants { // abstract out instruction decode magic numbers val RD_MSB = 11 val RD_LSB = 7 val RS1_MSB = 19 val RS1_LSB = 15 val RS2_MSB = 24 val RS2_LSB = 20 val RS3_MSB = 31 val RS3_LSB = 27 val CSR_ADDR_MSB = 31 val CSR_ADDR_LSB = 20 val CSR_ADDR_SZ = 12 // location of the fifth bit in the shamt (for checking for illegal ops for SRAIW,etc.) val SHAMT_5_BIT = 25 val LONGEST_IMM_SZ = 20 val X0 = 0.U val RA = 1.U // return address register // memory consistency model // The C/C++ atomics MCM requires that two loads to the same address maintain program order. // The Cortex A9 does NOT enforce load/load ordering (which leads to buggy behavior). val MCM_ORDER_DEPENDENT_LOADS = true val jal_opc = (0x6f).U val jalr_opc = (0x67).U def GetUop(inst: UInt): UInt = inst(6,0) def GetRd (inst: UInt): UInt = inst(RD_MSB,RD_LSB) def GetRs1(inst: UInt): UInt = inst(RS1_MSB,RS1_LSB) def ExpandRVC(inst: UInt)(implicit p: Parameters): UInt = { val rvc_exp = Module(new RVCExpander) rvc_exp.io.in := inst Mux(rvc_exp.io.rvc, rvc_exp.io.out.bits, inst) } // Note: Accepts only EXPANDED rvc instructions def ComputeBranchTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = { val b_imm32 = Cat(Fill(20,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) ((pc.asSInt + b_imm32.asSInt).asSInt & (-2).S).asUInt } // Note: Accepts only EXPANDED rvc instructions def ComputeJALTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = { val j_imm32 = Cat(Fill(12,inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) ((pc.asSInt + j_imm32.asSInt).asSInt & (-2).S).asUInt } // Note: Accepts only EXPANDED rvc instructions def GetCfiType(inst: UInt)(implicit p: Parameters): UInt = { val bdecode = Module(new boom.v3.exu.BranchDecode) bdecode.io.inst := inst bdecode.io.pc := 0.U bdecode.io.out.cfi_type } } /** * Mixin for exception cause constants */ trait ExcCauseConstants { // a memory disambigious misspeculation occurred val MINI_EXCEPTION_MEM_ORDERING = 16.U val MINI_EXCEPTION_CSR_REPLAY = 17.U require (!freechips.rocketchip.rocket.Causes.all.contains(16)) require (!freechips.rocketchip.rocket.Causes.all.contains(17)) } File issue-slot.scala: //****************************************************************************** // Copyright (c) 2015 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Issue Slot Logic //-------------------------------------------------------------------------- //------------------------------------------------------------------------------ // // Note: stores (and AMOs) are "broken down" into 2 uops, but stored within a single issue-slot. // TODO XXX make a separate issueSlot for MemoryIssueSlots, and only they break apart stores. // TODO Disable ldspec for FP queue. package boom.v3.exu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import boom.v3.common._ import boom.v3.util._ import FUConstants._ /** * IO bundle to interact with Issue slot * * @param numWakeupPorts number of wakeup ports for the slot */ class IssueSlotIO(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomBundle { val valid = Output(Bool()) val will_be_valid = Output(Bool()) // TODO code review, do we need this signal so explicitely? val request = Output(Bool()) val request_hp = Output(Bool()) val grant = Input(Bool()) val brupdate = Input(new BrUpdateInfo()) val kill = Input(Bool()) // pipeline flush val clear = Input(Bool()) // entry being moved elsewhere (not mutually exclusive with grant) val ldspec_miss = Input(Bool()) // Previous cycle's speculative load wakeup was mispredicted. val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new IqWakeup(maxPregSz)))) val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W))) val spec_ld_wakeup = Flipped(Vec(memWidth, Valid(UInt(width=maxPregSz.W)))) val in_uop = Flipped(Valid(new MicroOp())) // if valid, this WILL overwrite an entry! val out_uop = Output(new MicroOp()) // the updated slot uop; will be shifted upwards in a collasping queue. val uop = Output(new MicroOp()) // the current Slot's uop. Sent down the pipeline when issued. val debug = { val result = new Bundle { val p1 = Bool() val p2 = Bool() val p3 = Bool() val ppred = Bool() val state = UInt(width=2.W) } Output(result) } } /** * Single issue slot. Holds a uop within the issue queue * * @param numWakeupPorts number of wakeup ports */ class IssueSlot(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomModule with IssueUnitConstants { val io = IO(new IssueSlotIO(numWakeupPorts)) // slot invalid? // slot is valid, holding 1 uop // slot is valid, holds 2 uops (like a store) def is_invalid = state === s_invalid def is_valid = state =/= s_invalid val next_state = Wire(UInt()) // the next state of this slot (which might then get moved to a new slot) val next_uopc = Wire(UInt()) // the next uopc of this slot (which might then get moved to a new slot) val next_lrs1_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot) val next_lrs2_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot) val state = RegInit(s_invalid) val p1 = RegInit(false.B) val p2 = RegInit(false.B) val p3 = RegInit(false.B) val ppred = RegInit(false.B) // Poison if woken up by speculative load. // Poison lasts 1 cycle (as ldMiss will come on the next cycle). // SO if poisoned is true, set it to false! val p1_poisoned = RegInit(false.B) val p2_poisoned = RegInit(false.B) p1_poisoned := false.B p2_poisoned := false.B val next_p1_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned) val next_p2_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned) val slot_uop = RegInit(NullMicroOp) val next_uop = Mux(io.in_uop.valid, io.in_uop.bits, slot_uop) //----------------------------------------------------------------------------- // next slot state computation // compute the next state for THIS entry slot (in a collasping queue, the // current uop may get moved elsewhere, and a new uop can enter when (io.kill) { state := s_invalid } .elsewhen (io.in_uop.valid) { state := io.in_uop.bits.iw_state } .elsewhen (io.clear) { state := s_invalid } .otherwise { state := next_state } //----------------------------------------------------------------------------- // "update" state // compute the next state for the micro-op in this slot. This micro-op may // be moved elsewhere, so the "next_state" travels with it. // defaults next_state := state next_uopc := slot_uop.uopc next_lrs1_rtype := slot_uop.lrs1_rtype next_lrs2_rtype := slot_uop.lrs2_rtype when (io.kill) { next_state := s_invalid } .elsewhen ((io.grant && (state === s_valid_1)) || (io.grant && (state === s_valid_2) && p1 && p2 && ppred)) { // try to issue this uop. when (!(io.ldspec_miss && (p1_poisoned || p2_poisoned))) { next_state := s_invalid } } .elsewhen (io.grant && (state === s_valid_2)) { when (!(io.ldspec_miss && (p1_poisoned || p2_poisoned))) { next_state := s_valid_1 when (p1) { slot_uop.uopc := uopSTD next_uopc := uopSTD slot_uop.lrs1_rtype := RT_X next_lrs1_rtype := RT_X } .otherwise { slot_uop.lrs2_rtype := RT_X next_lrs2_rtype := RT_X } } } when (io.in_uop.valid) { slot_uop := io.in_uop.bits assert (is_invalid || io.clear || io.kill, "trying to overwrite a valid issue slot.") } // Wakeup Compare Logic // these signals are the "next_p*" for the current slot's micro-op. // they are important for shifting the current slot_uop up to an other entry. val next_p1 = WireInit(p1) val next_p2 = WireInit(p2) val next_p3 = WireInit(p3) val next_ppred = WireInit(ppred) when (io.in_uop.valid) { p1 := !(io.in_uop.bits.prs1_busy) p2 := !(io.in_uop.bits.prs2_busy) p3 := !(io.in_uop.bits.prs3_busy) ppred := !(io.in_uop.bits.ppred_busy) } when (io.ldspec_miss && next_p1_poisoned) { assert(next_uop.prs1 =/= 0.U, "Poison bit can't be set for prs1=x0!") p1 := false.B } when (io.ldspec_miss && next_p2_poisoned) { assert(next_uop.prs2 =/= 0.U, "Poison bit can't be set for prs2=x0!") p2 := false.B } for (i <- 0 until numWakeupPorts) { when (io.wakeup_ports(i).valid && (io.wakeup_ports(i).bits.pdst === next_uop.prs1)) { p1 := true.B } when (io.wakeup_ports(i).valid && (io.wakeup_ports(i).bits.pdst === next_uop.prs2)) { p2 := true.B } when (io.wakeup_ports(i).valid && (io.wakeup_ports(i).bits.pdst === next_uop.prs3)) { p3 := true.B } } when (io.pred_wakeup_port.valid && io.pred_wakeup_port.bits === next_uop.ppred) { ppred := true.B } for (w <- 0 until memWidth) { assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U), "Loads to x0 should never speculatively wakeup other instructions") } // TODO disable if FP IQ. for (w <- 0 until memWidth) { when (io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === next_uop.prs1 && next_uop.lrs1_rtype === RT_FIX) { p1 := true.B p1_poisoned := true.B assert (!next_p1_poisoned) } when (io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === next_uop.prs2 && next_uop.lrs2_rtype === RT_FIX) { p2 := true.B p2_poisoned := true.B assert (!next_p2_poisoned) } } // Handle branch misspeculations val next_br_mask = GetNewBrMask(io.brupdate, slot_uop) // was this micro-op killed by a branch? if yes, we can't let it be valid if // we compact it into an other entry when (IsKilledByBranch(io.brupdate, slot_uop)) { next_state := s_invalid } when (!io.in_uop.valid) { slot_uop.br_mask := next_br_mask } //------------------------------------------------------------- // Request Logic io.request := is_valid && p1 && p2 && p3 && ppred && !io.kill val high_priority = slot_uop.is_br || slot_uop.is_jal || slot_uop.is_jalr io.request_hp := io.request && high_priority when (state === s_valid_1) { io.request := p1 && p2 && p3 && ppred && !io.kill } .elsewhen (state === s_valid_2) { io.request := (p1 || p2) && ppred && !io.kill } .otherwise { io.request := false.B } //assign outputs io.valid := is_valid io.uop := slot_uop io.uop.iw_p1_poisoned := p1_poisoned io.uop.iw_p2_poisoned := p2_poisoned // micro-op will vacate due to grant. val may_vacate = io.grant && ((state === s_valid_1) || (state === s_valid_2) && p1 && p2 && ppred) val squash_grant = io.ldspec_miss && (p1_poisoned || p2_poisoned) io.will_be_valid := is_valid && !(may_vacate && !squash_grant) io.out_uop := slot_uop io.out_uop.iw_state := next_state io.out_uop.uopc := next_uopc io.out_uop.lrs1_rtype := next_lrs1_rtype io.out_uop.lrs2_rtype := next_lrs2_rtype io.out_uop.br_mask := next_br_mask io.out_uop.prs1_busy := !p1 io.out_uop.prs2_busy := !p2 io.out_uop.prs3_busy := !p3 io.out_uop.ppred_busy := !ppred io.out_uop.iw_p1_poisoned := p1_poisoned io.out_uop.iw_p2_poisoned := p2_poisoned when (state === s_valid_2) { when (p1 && p2 && ppred) { ; // send out the entire instruction as one uop } .elsewhen (p1 && ppred) { io.uop.uopc := slot_uop.uopc io.uop.lrs2_rtype := RT_X } .elsewhen (p2 && ppred) { io.uop.uopc := uopSTD io.uop.lrs1_rtype := RT_X } } // debug outputs io.debug.p1 := p1 io.debug.p2 := p2 io.debug.p3 := p3 io.debug.ppred := ppred io.debug.state := state }

module IssueSlot_140( // @[issue-slot.scala:69:7] input clock, // @[issue-slot.scala:69:7] input reset, // @[issue-slot.scala:69:7] output io_valid, // @[issue-slot.scala:73:14] output io_will_be_valid, // @[issue-slot.scala:73:14] output io_request, // @[issue-slot.scala:73:14] output io_request_hp, // @[issue-slot.scala:73:14] input io_grant, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14] input io_brupdate_b2_valid, // @[issue-slot.scala:73:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14] input io_brupdate_b2_taken, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14] input io_kill, // @[issue-slot.scala:73:14] input io_clear, // @[issue-slot.scala:73:14] input io_ldspec_miss, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_2_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_2_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_2_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_3_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_3_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_3_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_4_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_4_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_4_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_5_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_5_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_5_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_6_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_6_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_6_bits_poisoned, // @[issue-slot.scala:73:14] input io_spec_ld_wakeup_0_valid, // @[issue-slot.scala:73:14] input [6:0] io_spec_ld_wakeup_0_bits, // @[issue-slot.scala:73:14] input io_in_uop_valid, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14] input io_in_uop_bits_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_in_uop_bits_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14] input io_in_uop_bits_taken, // @[issue-slot.scala:73:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14] input io_in_uop_bits_exception, // @[issue-slot.scala:73:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14] input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14] output io_out_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14] output io_out_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] output io_out_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] output io_out_uop_is_br, // @[issue-slot.scala:73:14] output io_out_uop_is_jalr, // @[issue-slot.scala:73:14] output io_out_uop_is_jal, // @[issue-slot.scala:73:14] output io_out_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_out_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14] output io_out_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:73:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_out_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14] output io_out_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14] output io_out_uop_mem_signed, // @[issue-slot.scala:73:14] output io_out_uop_is_fence, // @[issue-slot.scala:73:14] output io_out_uop_is_fencei, // @[issue-slot.scala:73:14] output io_out_uop_is_amo, // @[issue-slot.scala:73:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_out_uop_uses_stq, // @[issue-slot.scala:73:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_out_uop_is_unique, // @[issue-slot.scala:73:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14] output io_out_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_out_uop_frs3_en, // @[issue-slot.scala:73:14] output io_out_uop_fp_val, // @[issue-slot.scala:73:14] output io_out_uop_fp_single, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14] output io_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14] output io_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] output io_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] output io_uop_is_br, // @[issue-slot.scala:73:14] output io_uop_is_jalr, // @[issue-slot.scala:73:14] output io_uop_is_jal, // @[issue-slot.scala:73:14] output io_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14] output io_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_uop_ppred, // @[issue-slot.scala:73:14] output io_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14] output io_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14] output io_uop_mem_signed, // @[issue-slot.scala:73:14] output io_uop_is_fence, // @[issue-slot.scala:73:14] output io_uop_is_fencei, // @[issue-slot.scala:73:14] output io_uop_is_amo, // @[issue-slot.scala:73:14] output io_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_uop_uses_stq, // @[issue-slot.scala:73:14] output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_uop_is_unique, // @[issue-slot.scala:73:14] output io_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14] output io_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_uop_frs3_en, // @[issue-slot.scala:73:14] output io_uop_fp_val, // @[issue-slot.scala:73:14] output io_uop_fp_single, // @[issue-slot.scala:73:14] output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14] output io_debug_p1, // @[issue-slot.scala:73:14] output io_debug_p2, // @[issue-slot.scala:73:14] output io_debug_p3, // @[issue-slot.scala:73:14] output io_debug_ppred, // @[issue-slot.scala:73:14] output [1:0] io_debug_state // @[issue-slot.scala:73:14] ); wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7] wire io_ldspec_miss_0 = io_ldspec_miss; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_bits_poisoned_0 = io_wakeup_ports_0_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_bits_poisoned_0 = io_wakeup_ports_1_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_2_bits_pdst_0 = io_wakeup_ports_2_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_2_bits_poisoned_0 = io_wakeup_ports_2_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_3_bits_pdst_0 = io_wakeup_ports_3_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_3_bits_poisoned_0 = io_wakeup_ports_3_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_4_bits_pdst_0 = io_wakeup_ports_4_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_4_bits_poisoned_0 = io_wakeup_ports_4_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_5_valid_0 = io_wakeup_ports_5_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_5_bits_pdst_0 = io_wakeup_ports_5_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_5_bits_poisoned_0 = io_wakeup_ports_5_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_6_valid_0 = io_wakeup_ports_6_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_6_bits_pdst_0 = io_wakeup_ports_6_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_6_bits_poisoned_0 = io_wakeup_ports_6_bits_poisoned; // @[issue-slot.scala:69:7] wire io_spec_ld_wakeup_0_valid_0 = io_spec_ld_wakeup_0_valid; // @[issue-slot.scala:69:7] wire [6:0] io_spec_ld_wakeup_0_bits_0 = io_spec_ld_wakeup_0_bits; // @[issue-slot.scala:69:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p1_poisoned_0 = io_in_uop_bits_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p2_poisoned_0 = io_in_uop_bits_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7] wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:69:7] wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19] wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [15:0] slot_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19] wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire _io_valid_T; // @[issue-slot.scala:79:24] wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32] wire _io_request_hp_T; // @[issue-slot.scala:243:31] wire [6:0] next_uopc; // @[issue-slot.scala:82:29] wire [1:0] next_state; // @[issue-slot.scala:81:29] wire [15:0] next_br_mask; // @[util.scala:85:25] wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28] wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28] wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28] wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28] wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29] wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29] wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_out_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_out_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7] wire io_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7] wire io_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire io_debug_p1_0; // @[issue-slot.scala:69:7] wire io_debug_p2_0; // @[issue-slot.scala:69:7] wire io_debug_p3_0; // @[issue-slot.scala:69:7] wire io_debug_ppred_0; // @[issue-slot.scala:69:7] wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7] wire io_valid_0; // @[issue-slot.scala:69:7] wire io_will_be_valid_0; // @[issue-slot.scala:69:7] wire io_request_0; // @[issue-slot.scala:69:7] wire io_request_hp_0; // @[issue-slot.scala:69:7] assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29] assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29] assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29] assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29] reg [1:0] state; // @[issue-slot.scala:86:22] assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22] reg p1; // @[issue-slot.scala:87:22] assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22] wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25] reg p2; // @[issue-slot.scala:88:22] assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22] wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25] reg p3; // @[issue-slot.scala:89:22] assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22] wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25] reg ppred; // @[issue-slot.scala:90:22] assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22] wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28] reg p1_poisoned; // @[issue-slot.scala:95:28] assign io_out_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28] assign io_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28] reg p2_poisoned; // @[issue-slot.scala:96:28] assign io_out_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28] assign io_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28] wire next_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : p1_poisoned; // @[issue-slot.scala:69:7, :95:28, :99:29] wire next_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : p2_poisoned; // @[issue-slot.scala:69:7, :96:28, :100:29] reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25] reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25] assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25] assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_rvc; // @[issue-slot.scala:102:25] assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25] assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25] assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25] assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_is_br; // @[issue-slot.scala:102:25] assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jalr; // @[issue-slot.scala:102:25] assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jal; // @[issue-slot.scala:102:25] assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sfb; // @[issue-slot.scala:102:25] assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:102:25] assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:102:25] assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_edge_inst; // @[issue-slot.scala:102:25] assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25] assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_taken; // @[issue-slot.scala:102:25] assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25] assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25] assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:102:25] assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:102:25] assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:102:25] assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:102:25] assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25] assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25] assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25] assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25] assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_exception; // @[issue-slot.scala:102:25] assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25] assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bypassable; // @[issue-slot.scala:102:25] assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25] assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_mem_signed; // @[issue-slot.scala:102:25] assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fence; // @[issue-slot.scala:102:25] assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fencei; // @[issue-slot.scala:102:25] assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_amo; // @[issue-slot.scala:102:25] assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_stq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25] assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_unique; // @[issue-slot.scala:102:25] assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25] assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25] assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25] assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25] assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_val; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25] assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25] reg slot_uop_frs3_en; // @[issue-slot.scala:102:25] assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_val; // @[issue-slot.scala:102:25] assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_single; // @[issue-slot.scala:102:25] assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [15:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25] wire _T_7 = io_grant_0 & state == 2'h1 | io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}] wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25] wire _T_14 = io_ldspec_miss_0 & (p1_poisoned | p2_poisoned); // @[issue-slot.scala:69:7, :95:28, :96:28, :140:{28,44}] wire _GEN = _T_12 & ~_T_14; // @[issue-slot.scala:126:14, :139:{25,51}, :140:{11,28,62}, :141:18] wire _GEN_0 = io_kill_0 | _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51] wire _GEN_1 = _GEN_0 | ~(_T_12 & ~_T_14 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:{11,28,62}, :142:17, :143:23] assign next_uopc = _GEN_1 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51] assign next_lrs1_rtype = _GEN_1 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51] wire _GEN_2 = _GEN_0 | ~_GEN | p1; // @[issue-slot.scala:87:22, :102:25, :126:14, :131:18, :134:63, :139:51, :140:62, :141:18, :142:17] assign next_lrs2_rtype = _GEN_2 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17] wire _p1_T = ~io_in_uop_bits_prs1_busy_0; // @[issue-slot.scala:69:7, :169:11] wire _p2_T = ~io_in_uop_bits_prs2_busy_0; // @[issue-slot.scala:69:7, :170:11] wire _p3_T = ~io_in_uop_bits_prs3_busy_0; // @[issue-slot.scala:69:7, :171:11] wire _ppred_T = ~io_in_uop_bits_ppred_busy_0; // @[issue-slot.scala:69:7, :172:14] wire _T_22 = io_ldspec_miss_0 & next_p1_poisoned; // @[issue-slot.scala:69:7, :99:29, :175:24] wire _T_27 = io_ldspec_miss_0 & next_p2_poisoned; // @[issue-slot.scala:69:7, :100:29, :179:24] wire _T_85 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs1 & next_uop_lrs1_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :209:38, :210:{33,51}, :211:27] wire _T_93 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs2 & next_uop_lrs2_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :216:38, :217:{33,51}, :218:27]

Generate the Verilog code corresponding to the following Chisel files. File Pipeline.scala: package gemmini import chisel3._ import chisel3.util._ class Pipeline[T <: Data] (gen: T, latency: Int)(comb: Seq[T => T] = Seq.fill(latency+1)((x: T) => x)) extends Module { val io = IO(new Bundle { val in = Flipped(Decoupled(gen)) val out = Decoupled(gen) val busy = Output(Bool()) }) require(comb.size == latency+1, "length of combinational is incorrect") if (latency == 0) { io.in.ready := io.out.ready io.out.valid := io.in.valid io.out.bits := comb.head(io.in.bits) io.busy := io.in.valid } else { val stages = Reg(Vec(latency, gen)) val valids = RegInit(VecInit(Seq.fill(latency)(false.B))) val stalling = VecInit(Seq.fill(latency)(false.B)) io.busy := io.in.valid || valids.reduce(_||_) // Stall signals io.in.ready := !stalling.head stalling.last := valids.last && !io.out.ready (stalling.init, stalling.tail, valids.init).zipped.foreach { case (s1, s2, v1) => s1 := v1 && s2 } // Valid signals // When the pipeline stage ahead of you isn't stalling, then make yourself invalid io.out.valid := valids.last when(io.out.ready) { valids.last := false.B } (valids.init, stalling.tail).zipped.foreach { case (v1, s2) => when(!s2) { v1 := false.B } } // When the pipeline stage behind you is valid then become true when(io.in.fire) { valids.head := true.B } (valids.tail, valids.init).zipped.foreach { case (v2, v1) => when(v1) { v2 := true.B } } // Stages when(io.in.fire) { stages.head := comb.head(io.in.bits) } io.out.bits := comb.last(stages.last) ((stages.tail zip stages.init) zip (stalling.tail zip comb.tail.init)).foreach { case ((st2, st1), (s2, c1)) => when(!s2) { st2 := c1(st1) } } } } object Pipeline { def apply[T <: Data](in: ReadyValidIO[T], latency: Int, comb: Seq[T => T]): DecoupledIO[T] = { val p = Module(new Pipeline(in.bits.cloneType, latency)(comb)) p.io.in <> in p.io.out } def apply[T <: Data](in: ReadyValidIO[T], latency: Int): DecoupledIO[T] = { val p = Module(new Pipeline(in.bits.cloneType, latency)()) p.io.in <> in p.io.out } }

module Pipeline_5( // @[Pipeline.scala:6:7] input clock, // @[Pipeline.scala:6:7] input reset, // @[Pipeline.scala:6:7] output io_in_ready, // @[Pipeline.scala:7:14] input io_in_valid, // @[Pipeline.scala:7:14] input [127:0] io_in_bits_data, // @[Pipeline.scala:7:14] input io_in_bits_fromDMA, // @[Pipeline.scala:7:14] input io_out_ready, // @[Pipeline.scala:7:14] output io_out_valid, // @[Pipeline.scala:7:14] output [127:0] io_out_bits_data // @[Pipeline.scala:7:14] ); wire io_in_valid_0 = io_in_valid; // @[Pipeline.scala:6:7] wire [127:0] io_in_bits_data_0 = io_in_bits_data; // @[Pipeline.scala:6:7] wire io_in_bits_fromDMA_0 = io_in_bits_fromDMA; // @[Pipeline.scala:6:7] wire io_out_ready_0 = io_out_ready; // @[Pipeline.scala:6:7] wire _valids_WIRE_0 = 1'h0; // @[Pipeline.scala:22:33] wire _valids_WIRE_1 = 1'h0; // @[Pipeline.scala:22:33] wire _valids_WIRE_2 = 1'h0; // @[Pipeline.scala:22:33] wire _valids_WIRE_3 = 1'h0; // @[Pipeline.scala:22:33] wire _io_in_ready_T; // @[Pipeline.scala:27:20] wire _io_busy_T_3; // @[Pipeline.scala:24:28] wire io_in_ready_0; // @[Pipeline.scala:6:7] wire [127:0] io_out_bits_data_0; // @[Pipeline.scala:6:7] wire io_out_bits_fromDMA; // @[Pipeline.scala:6:7] wire io_out_valid_0; // @[Pipeline.scala:6:7] wire io_busy; // @[Pipeline.scala:6:7] reg [127:0] stages_0_data; // @[Pipeline.scala:21:21] reg stages_0_fromDMA; // @[Pipeline.scala:21:21] reg [127:0] stages_1_data; // @[Pipeline.scala:21:21] reg stages_1_fromDMA; // @[Pipeline.scala:21:21] reg [127:0] stages_2_data; // @[Pipeline.scala:21:21] reg stages_2_fromDMA; // @[Pipeline.scala:21:21] reg [127:0] stages_3_data; // @[Pipeline.scala:21:21] assign io_out_bits_data_0 = stages_3_data; // @[Pipeline.scala:6:7, :21:21] reg stages_3_fromDMA; // @[Pipeline.scala:21:21] assign io_out_bits_fromDMA = stages_3_fromDMA; // @[Pipeline.scala:6:7, :21:21] reg valids_0; // @[Pipeline.scala:22:25] reg valids_1; // @[Pipeline.scala:22:25] reg valids_2; // @[Pipeline.scala:22:25] reg valids_3; // @[Pipeline.scala:22:25] assign io_out_valid_0 = valids_3; // @[Pipeline.scala:6:7, :22:25] wire _stalling_0_T; // @[Pipeline.scala:30:16] wire _stalling_1_T; // @[Pipeline.scala:30:16] wire _stalling_2_T; // @[Pipeline.scala:30:16] wire _stalling_3_T_1; // @[Pipeline.scala:28:34] wire stalling_0; // @[Pipeline.scala:23:27] wire stalling_1; // @[Pipeline.scala:23:27] wire stalling_2; // @[Pipeline.scala:23:27] wire stalling_3; // @[Pipeline.scala:23:27] wire _io_busy_T = valids_0 | valids_1; // @[Pipeline.scala:22:25, :24:46] wire _io_busy_T_1 = _io_busy_T | valids_2; // @[Pipeline.scala:22:25, :24:46] wire _io_busy_T_2 = _io_busy_T_1 | valids_3; // @[Pipeline.scala:22:25, :24:46] assign _io_busy_T_3 = io_in_valid_0 | _io_busy_T_2; // @[Pipeline.scala:6:7, :24:{28,46}] assign io_busy = _io_busy_T_3; // @[Pipeline.scala:6:7, :24:28] assign _io_in_ready_T = ~stalling_0; // @[Pipeline.scala:23:27, :27:20] assign io_in_ready_0 = _io_in_ready_T; // @[Pipeline.scala:6:7, :27:20] wire _stalling_3_T = ~io_out_ready_0; // @[Pipeline.scala:6:7, :28:37] assign _stalling_3_T_1 = valids_3 & _stalling_3_T; // @[Pipeline.scala:22:25, :28:{34,37}] assign stalling_3 = _stalling_3_T_1; // @[Pipeline.scala:23:27, :28:34] assign _stalling_0_T = valids_0 & stalling_1; // @[Pipeline.scala:22:25, :23:27, :30:16] assign stalling_0 = _stalling_0_T; // @[Pipeline.scala:23:27, :30:16] assign _stalling_1_T = valids_1 & stalling_2; // @[Pipeline.scala:22:25, :23:27, :30:16] assign stalling_1 = _stalling_1_T; // @[Pipeline.scala:23:27, :30:16] assign _stalling_2_T = valids_2 & stalling_3; // @[Pipeline.scala:22:25, :23:27, :30:16] assign stalling_2 = _stalling_2_T; // @[Pipeline.scala:23:27, :30:16] wire _T_4 = io_in_ready_0 & io_in_valid_0; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[Pipeline.scala:6:7] if (_T_4) begin // @[Decoupled.scala:51:35] stages_0_data <= io_in_bits_data_0; // @[Pipeline.scala:6:7, :21:21] stages_0_fromDMA <= io_in_bits_fromDMA_0; // @[Pipeline.scala:6:7, :21:21] end if (stalling_1) begin // @[Pipeline.scala:23:27] end else begin // @[Pipeline.scala:23:27] stages_1_data <= stages_0_data; // @[Pipeline.scala:21:21] stages_1_fromDMA <= stages_0_fromDMA; // @[Pipeline.scala:21:21] end if (stalling_2) begin // @[Pipeline.scala:23:27] end else begin // @[Pipeline.scala:23:27] stages_2_data <= stages_1_data; // @[Pipeline.scala:21:21] stages_2_fromDMA <= stages_1_fromDMA; // @[Pipeline.scala:21:21] end if (stalling_3) begin // @[Pipeline.scala:23:27] end else begin // @[Pipeline.scala:23:27] stages_3_data <= stages_2_data; // @[Pipeline.scala:21:21] stages_3_fromDMA <= stages_2_fromDMA; // @[Pipeline.scala:21:21] end if (reset) begin // @[Pipeline.scala:6:7] valids_0 <= 1'h0; // @[Pipeline.scala:22:25] valids_1 <= 1'h0; // @[Pipeline.scala:22:25] valids_2 <= 1'h0; // @[Pipeline.scala:22:25] valids_3 <= 1'h0; // @[Pipeline.scala:22:25] end else begin // @[Pipeline.scala:6:7] valids_0 <= _T_4 | stalling_1 & valids_0; // @[Decoupled.scala:51:35] valids_1 <= valids_0 | stalling_2 & valids_1; // @[Pipeline.scala:22:25, :23:27, :40:17, :41:12, :49:16, :50:12] valids_2 <= valids_1 | stalling_3 & valids_2; // @[Pipeline.scala:22:25, :23:27, :40:17, :41:12, :49:16, :50:12] valids_3 <= valids_2 | ~io_out_ready_0 & valids_3; // @[Pipeline.scala:6:7, :22:25, :36:24, :37:19, :49:16, :50:12] end always @(posedge) assign io_in_ready = io_in_ready_0; // @[Pipeline.scala:6:7] assign io_out_valid = io_out_valid_0; // @[Pipeline.scala:6:7] assign io_out_bits_data = io_out_bits_data_0; // @[Pipeline.scala:6:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File primitives.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object lowMask { def apply(in: UInt, topBound: BigInt, bottomBound: BigInt): UInt = { require(topBound != bottomBound) val numInVals = BigInt(1)<<in.getWidth if (topBound < bottomBound) { lowMask(~in, numInVals - 1 - topBound, numInVals - 1 - bottomBound) } else if (numInVals > 64 /* Empirical */) { // For simulation performance, we should avoid generating // exteremely wide shifters, so we divide and conquer. // Empirically, this does not impact synthesis QoR. val mid = numInVals / 2 val msb = in(in.getWidth - 1) val lsbs = in(in.getWidth - 2, 0) if (mid < topBound) { if (mid <= bottomBound) { Mux(msb, lowMask(lsbs, topBound - mid, bottomBound - mid), 0.U ) } else { Mux(msb, lowMask(lsbs, topBound - mid, 0) ## ((BigInt(1)<<(mid - bottomBound).toInt) - 1).U, lowMask(lsbs, mid, bottomBound) ) } } else { ~Mux(msb, 0.U, ~lowMask(lsbs, topBound, bottomBound)) } } else { val shift = (BigInt(-1)<<numInVals.toInt).S>>in Reverse( shift( (numInVals - 1 - bottomBound).toInt, (numInVals - topBound).toInt ) ) } } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object countLeadingZeros { def apply(in: UInt): UInt = PriorityEncoder(in.asBools.reverse) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy2 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 1)>>1 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 2 + 1, ix * 2).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 2).orR reducedVec.asUInt } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy4 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 3)>>2 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 4 + 3, ix * 4).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 4).orR reducedVec.asUInt } } File MulAddRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFN_interIo(expWidth: Int, sigWidth: Int) extends Bundle { //*** ENCODE SOME OF THESE CASES IN FEWER BITS?: val isSigNaNAny = Bool() val isNaNAOrB = Bool() val isInfA = Bool() val isZeroA = Bool() val isInfB = Bool() val isZeroB = Bool() val signProd = Bool() val isNaNC = Bool() val isInfC = Bool() val isZeroC = Bool() val sExpSum = SInt((expWidth + 2).W) val doSubMags = Bool() val CIsDominant = Bool() val CDom_CAlignDist = UInt(log2Ceil(sigWidth + 1).W) val highAlignedSigC = UInt((sigWidth + 2).W) val bit0AlignedSigC = UInt(1.W) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFNToRaw_preMul(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFNToRaw_preMul_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val mulAddA = Output(UInt(sigWidth.W)) val mulAddB = Output(UInt(sigWidth.W)) val mulAddC = Output(UInt((sigWidth * 2).W)) val toPostMul = Output(new MulAddRecFN_interIo(expWidth, sigWidth)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ //*** POSSIBLE TO REDUCE THIS BY 1 OR 2 BITS? (CURRENTLY 2 BITS BETWEEN //*** UNSHIFTED C AND PRODUCT): val sigSumWidth = sigWidth * 3 + 3 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val rawA = rawFloatFromRecFN(expWidth, sigWidth, io.a) val rawB = rawFloatFromRecFN(expWidth, sigWidth, io.b) val rawC = rawFloatFromRecFN(expWidth, sigWidth, io.c) val signProd = rawA.sign ^ rawB.sign ^ io.op(1) //*** REVIEW THE BIAS FOR 'sExpAlignedProd': val sExpAlignedProd = rawA.sExp +& rawB.sExp + (-(BigInt(1)<<expWidth) + sigWidth + 3).S val doSubMags = signProd ^ rawC.sign ^ io.op(0) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sNatCAlignDist = sExpAlignedProd - rawC.sExp val posNatCAlignDist = sNatCAlignDist(expWidth + 1, 0) val isMinCAlign = rawA.isZero || rawB.isZero || (sNatCAlignDist < 0.S) val CIsDominant = ! rawC.isZero && (isMinCAlign || (posNatCAlignDist <= sigWidth.U)) val CAlignDist = Mux(isMinCAlign, 0.U, Mux(posNatCAlignDist < (sigSumWidth - 1).U, posNatCAlignDist(log2Ceil(sigSumWidth) - 1, 0), (sigSumWidth - 1).U ) ) val mainAlignedSigC = (Mux(doSubMags, ~rawC.sig, rawC.sig) ## Fill(sigSumWidth - sigWidth + 2, doSubMags)).asSInt>>CAlignDist val reduced4CExtra = (orReduceBy4(rawC.sig<<((sigSumWidth - sigWidth - 1) & 3)) & lowMask( CAlignDist>>2, //*** NOT NEEDED?: // (sigSumWidth + 2)>>2, (sigSumWidth - 1)>>2, (sigSumWidth - sigWidth - 1)>>2 ) ).orR val alignedSigC = Cat(mainAlignedSigC>>3, Mux(doSubMags, mainAlignedSigC(2, 0).andR && ! reduced4CExtra, mainAlignedSigC(2, 0).orR || reduced4CExtra ) ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ io.mulAddA := rawA.sig io.mulAddB := rawB.sig io.mulAddC := alignedSigC(sigWidth * 2, 1) io.toPostMul.isSigNaNAny := isSigNaNRawFloat(rawA) || isSigNaNRawFloat(rawB) || isSigNaNRawFloat(rawC) io.toPostMul.isNaNAOrB := rawA.isNaN || rawB.isNaN io.toPostMul.isInfA := rawA.isInf io.toPostMul.isZeroA := rawA.isZero io.toPostMul.isInfB := rawB.isInf io.toPostMul.isZeroB := rawB.isZero io.toPostMul.signProd := signProd io.toPostMul.isNaNC := rawC.isNaN io.toPostMul.isInfC := rawC.isInf io.toPostMul.isZeroC := rawC.isZero io.toPostMul.sExpSum := Mux(CIsDominant, rawC.sExp, sExpAlignedProd - sigWidth.S) io.toPostMul.doSubMags := doSubMags io.toPostMul.CIsDominant := CIsDominant io.toPostMul.CDom_CAlignDist := CAlignDist(log2Ceil(sigWidth + 1) - 1, 0) io.toPostMul.highAlignedSigC := alignedSigC(sigSumWidth - 1, sigWidth * 2 + 1) io.toPostMul.bit0AlignedSigC := alignedSigC(0) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFNToRaw_postMul(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFNToRaw_postMul_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val fromPreMul = Input(new MulAddRecFN_interIo(expWidth, sigWidth)) val mulAddResult = Input(UInt((sigWidth * 2 + 1).W)) val roundingMode = Input(UInt(3.W)) val invalidExc = Output(Bool()) val rawOut = Output(new RawFloat(expWidth, sigWidth + 2)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigSumWidth = sigWidth * 3 + 3 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_min = (io.roundingMode === round_min) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val opSignC = io.fromPreMul.signProd ^ io.fromPreMul.doSubMags val sigSum = Cat(Mux(io.mulAddResult(sigWidth * 2), io.fromPreMul.highAlignedSigC + 1.U, io.fromPreMul.highAlignedSigC ), io.mulAddResult(sigWidth * 2 - 1, 0), io.fromPreMul.bit0AlignedSigC ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val CDom_sign = opSignC val CDom_sExp = io.fromPreMul.sExpSum - io.fromPreMul.doSubMags.zext val CDom_absSigSum = Mux(io.fromPreMul.doSubMags, ~sigSum(sigSumWidth - 1, sigWidth + 1), 0.U(1.W) ## //*** IF GAP IS REDUCED TO 1 BIT, MUST REDUCE THIS COMPONENT TO 1 BIT TOO: io.fromPreMul.highAlignedSigC(sigWidth + 1, sigWidth) ## sigSum(sigSumWidth - 3, sigWidth + 2) ) val CDom_absSigSumExtra = Mux(io.fromPreMul.doSubMags, (~sigSum(sigWidth, 1)).orR, sigSum(sigWidth + 1, 1).orR ) val CDom_mainSig = (CDom_absSigSum<<io.fromPreMul.CDom_CAlignDist)( sigWidth * 2 + 1, sigWidth - 3) val CDom_reduced4SigExtra = (orReduceBy4(CDom_absSigSum(sigWidth - 1, 0)<<(~sigWidth & 3)) & lowMask(io.fromPreMul.CDom_CAlignDist>>2, 0, sigWidth>>2)).orR val CDom_sig = Cat(CDom_mainSig>>3, CDom_mainSig(2, 0).orR || CDom_reduced4SigExtra || CDom_absSigSumExtra ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val notCDom_signSigSum = sigSum(sigWidth * 2 + 3) val notCDom_absSigSum = Mux(notCDom_signSigSum, ~sigSum(sigWidth * 2 + 2, 0), sigSum(sigWidth * 2 + 2, 0) + io.fromPreMul.doSubMags ) val notCDom_reduced2AbsSigSum = orReduceBy2(notCDom_absSigSum) val notCDom_normDistReduced2 = countLeadingZeros(notCDom_reduced2AbsSigSum) val notCDom_nearNormDist = notCDom_normDistReduced2<<1 val notCDom_sExp = io.fromPreMul.sExpSum - notCDom_nearNormDist.asUInt.zext val notCDom_mainSig = (notCDom_absSigSum<<notCDom_nearNormDist)( sigWidth * 2 + 3, sigWidth - 1) val notCDom_reduced4SigExtra = (orReduceBy2( notCDom_reduced2AbsSigSum(sigWidth>>1, 0)<<((sigWidth>>1) & 1)) & lowMask(notCDom_normDistReduced2>>1, 0, (sigWidth + 2)>>2) ).orR val notCDom_sig = Cat(notCDom_mainSig>>3, notCDom_mainSig(2, 0).orR || notCDom_reduced4SigExtra ) val notCDom_completeCancellation = (notCDom_sig(sigWidth + 2, sigWidth + 1) === 0.U) val notCDom_sign = Mux(notCDom_completeCancellation, roundingMode_min, io.fromPreMul.signProd ^ notCDom_signSigSum ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val notNaN_isInfProd = io.fromPreMul.isInfA || io.fromPreMul.isInfB val notNaN_isInfOut = notNaN_isInfProd || io.fromPreMul.isInfC val notNaN_addZeros = (io.fromPreMul.isZeroA || io.fromPreMul.isZeroB) && io.fromPreMul.isZeroC io.invalidExc := io.fromPreMul.isSigNaNAny || (io.fromPreMul.isInfA && io.fromPreMul.isZeroB) || (io.fromPreMul.isZeroA && io.fromPreMul.isInfB) || (! io.fromPreMul.isNaNAOrB && (io.fromPreMul.isInfA || io.fromPreMul.isInfB) && io.fromPreMul.isInfC && io.fromPreMul.doSubMags) io.rawOut.isNaN := io.fromPreMul.isNaNAOrB || io.fromPreMul.isNaNC io.rawOut.isInf := notNaN_isInfOut //*** IMPROVE?: io.rawOut.isZero := notNaN_addZeros || (! io.fromPreMul.CIsDominant && notCDom_completeCancellation) io.rawOut.sign := (notNaN_isInfProd && io.fromPreMul.signProd) || (io.fromPreMul.isInfC && opSignC) || (notNaN_addZeros && ! roundingMode_min && io.fromPreMul.signProd && opSignC) || (notNaN_addZeros && roundingMode_min && (io.fromPreMul.signProd || opSignC)) || (! notNaN_isInfOut && ! notNaN_addZeros && Mux(io.fromPreMul.CIsDominant, CDom_sign, notCDom_sign)) io.rawOut.sExp := Mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp) io.rawOut.sig := Mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFN(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val mulAddRecFNToRaw_preMul = Module(new MulAddRecFNToRaw_preMul(expWidth, sigWidth)) val mulAddRecFNToRaw_postMul = Module(new MulAddRecFNToRaw_postMul(expWidth, sigWidth)) mulAddRecFNToRaw_preMul.io.op := io.op mulAddRecFNToRaw_preMul.io.a := io.a mulAddRecFNToRaw_preMul.io.b := io.b mulAddRecFNToRaw_preMul.io.c := io.c val mulAddResult = (mulAddRecFNToRaw_preMul.io.mulAddA * mulAddRecFNToRaw_preMul.io.mulAddB) +& mulAddRecFNToRaw_preMul.io.mulAddC mulAddRecFNToRaw_postMul.io.fromPreMul := mulAddRecFNToRaw_preMul.io.toPostMul mulAddRecFNToRaw_postMul.io.mulAddResult := mulAddResult mulAddRecFNToRaw_postMul.io.roundingMode := io.roundingMode //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundRawFNToRecFN = Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0)) roundRawFNToRecFN.io.invalidExc := mulAddRecFNToRaw_postMul.io.invalidExc roundRawFNToRecFN.io.infiniteExc := false.B roundRawFNToRecFN.io.in := mulAddRecFNToRaw_postMul.io.rawOut roundRawFNToRecFN.io.roundingMode := io.roundingMode roundRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundRawFNToRecFN.io.out io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags }

module MulAddRecFNToRaw_postMul_e5_s11( // @[MulAddRecFN.scala:169:7] input io_fromPreMul_isSigNaNAny, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isNaNAOrB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfA, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroA, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_signProd, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isNaNC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroC, // @[MulAddRecFN.scala:172:16] input [6:0] io_fromPreMul_sExpSum, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_doSubMags, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_CIsDominant, // @[MulAddRecFN.scala:172:16] input [3:0] io_fromPreMul_CDom_CAlignDist, // @[MulAddRecFN.scala:172:16] input [12:0] io_fromPreMul_highAlignedSigC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_bit0AlignedSigC, // @[MulAddRecFN.scala:172:16] input [22:0] io_mulAddResult, // @[MulAddRecFN.scala:172:16] input [2:0] io_roundingMode, // @[MulAddRecFN.scala:172:16] output io_invalidExc, // @[MulAddRecFN.scala:172:16] output io_rawOut_isNaN, // @[MulAddRecFN.scala:172:16] output io_rawOut_isInf, // @[MulAddRecFN.scala:172:16] output io_rawOut_isZero, // @[MulAddRecFN.scala:172:16] output io_rawOut_sign, // @[MulAddRecFN.scala:172:16] output [6:0] io_rawOut_sExp, // @[MulAddRecFN.scala:172:16] output [13:0] io_rawOut_sig // @[MulAddRecFN.scala:172:16] ); wire io_fromPreMul_isSigNaNAny_0 = io_fromPreMul_isSigNaNAny; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isNaNAOrB_0 = io_fromPreMul_isNaNAOrB; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfA_0 = io_fromPreMul_isInfA; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroA_0 = io_fromPreMul_isZeroA; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfB_0 = io_fromPreMul_isInfB; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroB_0 = io_fromPreMul_isZeroB; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_signProd_0 = io_fromPreMul_signProd; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isNaNC_0 = io_fromPreMul_isNaNC; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfC_0 = io_fromPreMul_isInfC; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroC_0 = io_fromPreMul_isZeroC; // @[MulAddRecFN.scala:169:7] wire [6:0] io_fromPreMul_sExpSum_0 = io_fromPreMul_sExpSum; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_doSubMags_0 = io_fromPreMul_doSubMags; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_CIsDominant_0 = io_fromPreMul_CIsDominant; // @[MulAddRecFN.scala:169:7] wire [3:0] io_fromPreMul_CDom_CAlignDist_0 = io_fromPreMul_CDom_CAlignDist; // @[MulAddRecFN.scala:169:7] wire [12:0] io_fromPreMul_highAlignedSigC_0 = io_fromPreMul_highAlignedSigC; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_bit0AlignedSigC_0 = io_fromPreMul_bit0AlignedSigC; // @[MulAddRecFN.scala:169:7] wire [22:0] io_mulAddResult_0 = io_mulAddResult; // @[MulAddRecFN.scala:169:7] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[MulAddRecFN.scala:169:7] wire _io_invalidExc_T_9; // @[MulAddRecFN.scala:273:57] wire _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:278:48] wire notNaN_isInfOut; // @[MulAddRecFN.scala:265:44] wire _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:282:25] wire _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:290:50] wire [6:0] _io_rawOut_sExp_T; // @[MulAddRecFN.scala:293:26] wire [13:0] _io_rawOut_sig_T; // @[MulAddRecFN.scala:294:25] wire io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7] wire [6:0] io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7] wire [13:0] io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7] wire io_invalidExc_0; // @[MulAddRecFN.scala:169:7] wire roundingMode_min = io_roundingMode_0 == 3'h2; // @[MulAddRecFN.scala:169:7, :186:45] wire opSignC = io_fromPreMul_signProd_0 ^ io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :190:42] wire _sigSum_T = io_mulAddResult_0[22]; // @[MulAddRecFN.scala:169:7, :192:32] wire [13:0] _sigSum_T_1 = {1'h0, io_fromPreMul_highAlignedSigC_0} + 14'h1; // @[MulAddRecFN.scala:169:7, :193:47] wire [12:0] _sigSum_T_2 = _sigSum_T_1[12:0]; // @[MulAddRecFN.scala:193:47] wire [12:0] _sigSum_T_3 = _sigSum_T ? _sigSum_T_2 : io_fromPreMul_highAlignedSigC_0; // @[MulAddRecFN.scala:169:7, :192:{16,32}, :193:47] wire [21:0] _sigSum_T_4 = io_mulAddResult_0[21:0]; // @[MulAddRecFN.scala:169:7, :196:28] wire [34:0] sigSum_hi = {_sigSum_T_3, _sigSum_T_4}; // @[MulAddRecFN.scala:192:{12,16}, :196:28] wire [35:0] sigSum = {sigSum_hi, io_fromPreMul_bit0AlignedSigC_0}; // @[MulAddRecFN.scala:169:7, :192:12] wire [1:0] _CDom_sExp_T = {1'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :203:69] wire [7:0] _GEN = {io_fromPreMul_sExpSum_0[6], io_fromPreMul_sExpSum_0}; // @[MulAddRecFN.scala:169:7, :203:43] wire [7:0] _CDom_sExp_T_1 = _GEN - {{6{_CDom_sExp_T[1]}}, _CDom_sExp_T}; // @[MulAddRecFN.scala:203:{43,69}] wire [6:0] _CDom_sExp_T_2 = _CDom_sExp_T_1[6:0]; // @[MulAddRecFN.scala:203:43] wire [6:0] CDom_sExp = _CDom_sExp_T_2; // @[MulAddRecFN.scala:203:43] wire [23:0] _CDom_absSigSum_T = sigSum[35:12]; // @[MulAddRecFN.scala:192:12, :206:20] wire [23:0] _CDom_absSigSum_T_1 = ~_CDom_absSigSum_T; // @[MulAddRecFN.scala:206:{13,20}] wire [1:0] _CDom_absSigSum_T_2 = io_fromPreMul_highAlignedSigC_0[12:11]; // @[MulAddRecFN.scala:169:7, :209:46] wire [2:0] _CDom_absSigSum_T_3 = {1'h0, _CDom_absSigSum_T_2}; // @[MulAddRecFN.scala:207:22, :209:46] wire [20:0] _CDom_absSigSum_T_4 = sigSum[33:13]; // @[MulAddRecFN.scala:192:12, :210:23] wire [23:0] _CDom_absSigSum_T_5 = {_CDom_absSigSum_T_3, _CDom_absSigSum_T_4}; // @[MulAddRecFN.scala:207:22, :209:71, :210:23] wire [23:0] CDom_absSigSum = io_fromPreMul_doSubMags_0 ? _CDom_absSigSum_T_1 : _CDom_absSigSum_T_5; // @[MulAddRecFN.scala:169:7, :205:12, :206:13, :209:71] wire [10:0] _CDom_absSigSumExtra_T = sigSum[11:1]; // @[MulAddRecFN.scala:192:12, :215:21] wire [10:0] _CDom_absSigSumExtra_T_1 = ~_CDom_absSigSumExtra_T; // @[MulAddRecFN.scala:215:{14,21}] wire _CDom_absSigSumExtra_T_2 = |_CDom_absSigSumExtra_T_1; // @[MulAddRecFN.scala:215:{14,36}] wire [11:0] _CDom_absSigSumExtra_T_3 = sigSum[12:1]; // @[MulAddRecFN.scala:192:12, :216:19] wire _CDom_absSigSumExtra_T_4 = |_CDom_absSigSumExtra_T_3; // @[MulAddRecFN.scala:216:{19,37}] wire CDom_absSigSumExtra = io_fromPreMul_doSubMags_0 ? _CDom_absSigSumExtra_T_2 : _CDom_absSigSumExtra_T_4; // @[MulAddRecFN.scala:169:7, :214:12, :215:36, :216:37] wire [38:0] _CDom_mainSig_T = {15'h0, CDom_absSigSum} << io_fromPreMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:169:7, :205:12, :219:24] wire [15:0] CDom_mainSig = _CDom_mainSig_T[23:8]; // @[MulAddRecFN.scala:219:{24,56}] wire [10:0] _CDom_reduced4SigExtra_T = CDom_absSigSum[10:0]; // @[MulAddRecFN.scala:205:12, :222:36] wire [10:0] _CDom_reduced4SigExtra_T_1 = _CDom_reduced4SigExtra_T; // @[MulAddRecFN.scala:222:{36,53}] wire _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:123:57] wire CDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:118:30] wire [3:0] _CDom_reduced4SigExtra_reducedVec_0_T = _CDom_reduced4SigExtra_T_1[3:0]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_0_T_1 = |_CDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_0 = _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_1_T = _CDom_reduced4SigExtra_T_1[7:4]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_1_T_1 = |_CDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_1 = _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54] wire [2:0] _CDom_reduced4SigExtra_reducedVec_2_T = _CDom_reduced4SigExtra_T_1[10:8]; // @[primitives.scala:123:15] assign _CDom_reduced4SigExtra_reducedVec_2_T_1 = |_CDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:123:{15,57}] assign CDom_reduced4SigExtra_reducedVec_2 = _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :123:57] wire [1:0] CDom_reduced4SigExtra_hi = {CDom_reduced4SigExtra_reducedVec_2, CDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20] wire [2:0] _CDom_reduced4SigExtra_T_2 = {CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20] wire [1:0] _CDom_reduced4SigExtra_T_3 = io_fromPreMul_CDom_CAlignDist_0[3:2]; // @[MulAddRecFN.scala:169:7, :223:51] wire [1:0] _CDom_reduced4SigExtra_T_4 = ~_CDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21] wire [4:0] CDom_reduced4SigExtra_shift = $signed(5'sh10 >>> _CDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56] wire [1:0] _CDom_reduced4SigExtra_T_5 = CDom_reduced4SigExtra_shift[2:1]; // @[primitives.scala:76:56, :78:22] wire _CDom_reduced4SigExtra_T_6 = _CDom_reduced4SigExtra_T_5[0]; // @[primitives.scala:77:20, :78:22] wire _CDom_reduced4SigExtra_T_7 = _CDom_reduced4SigExtra_T_5[1]; // @[primitives.scala:77:20, :78:22] wire [1:0] _CDom_reduced4SigExtra_T_8 = {_CDom_reduced4SigExtra_T_6, _CDom_reduced4SigExtra_T_7}; // @[primitives.scala:77:20] wire [2:0] _CDom_reduced4SigExtra_T_9 = {1'h0, _CDom_reduced4SigExtra_T_2[1:0] & _CDom_reduced4SigExtra_T_8}; // @[primitives.scala:77:20, :124:20] wire CDom_reduced4SigExtra = |_CDom_reduced4SigExtra_T_9; // @[MulAddRecFN.scala:222:72, :223:73] wire [12:0] _CDom_sig_T = CDom_mainSig[15:3]; // @[MulAddRecFN.scala:219:56, :225:25] wire [2:0] _CDom_sig_T_1 = CDom_mainSig[2:0]; // @[MulAddRecFN.scala:219:56, :226:25] wire _CDom_sig_T_2 = |_CDom_sig_T_1; // @[MulAddRecFN.scala:226:{25,32}] wire _CDom_sig_T_3 = _CDom_sig_T_2 | CDom_reduced4SigExtra; // @[MulAddRecFN.scala:223:73, :226:{32,36}] wire _CDom_sig_T_4 = _CDom_sig_T_3 | CDom_absSigSumExtra; // @[MulAddRecFN.scala:214:12, :226:{36,61}] wire [13:0] CDom_sig = {_CDom_sig_T, _CDom_sig_T_4}; // @[MulAddRecFN.scala:225:{12,25}, :226:61] wire notCDom_signSigSum = sigSum[25]; // @[MulAddRecFN.scala:192:12, :232:36] wire [24:0] _notCDom_absSigSum_T = sigSum[24:0]; // @[MulAddRecFN.scala:192:12, :235:20] wire [24:0] _notCDom_absSigSum_T_2 = sigSum[24:0]; // @[MulAddRecFN.scala:192:12, :235:20, :236:19] wire [24:0] _notCDom_absSigSum_T_1 = ~_notCDom_absSigSum_T; // @[MulAddRecFN.scala:235:{13,20}] wire [25:0] _notCDom_absSigSum_T_3 = {1'h0, _notCDom_absSigSum_T_2} + {25'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :236:{19,41}] wire [24:0] _notCDom_absSigSum_T_4 = _notCDom_absSigSum_T_3[24:0]; // @[MulAddRecFN.scala:236:41] wire [24:0] notCDom_absSigSum = notCDom_signSigSum ? _notCDom_absSigSum_T_1 : _notCDom_absSigSum_T_4; // @[MulAddRecFN.scala:232:36, :234:12, :235:13, :236:41] wire _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:106:57] wire notCDom_reduced2AbsSigSum_reducedVec_0; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_1; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_2; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_3; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_4; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_5; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_6; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_7; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_8; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_9; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_10; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_11; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_12; // @[primitives.scala:101:30] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_0_T = notCDom_absSigSum[1:0]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_0_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_0 = _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_1_T = notCDom_absSigSum[3:2]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_1_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_1 = _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_2_T = notCDom_absSigSum[5:4]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_2_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_2 = _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_3_T = notCDom_absSigSum[7:6]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_3_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_3 = _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_4_T = notCDom_absSigSum[9:8]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_4_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_4 = _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_5_T = notCDom_absSigSum[11:10]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_5_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_5 = _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_6_T = notCDom_absSigSum[13:12]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_6_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_6 = _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_7_T = notCDom_absSigSum[15:14]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_7_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_7 = _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_8_T = notCDom_absSigSum[17:16]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_8_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_8 = _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_9_T = notCDom_absSigSum[19:18]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_9_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_9 = _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_10_T = notCDom_absSigSum[21:20]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_10_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_10 = _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_11_T = notCDom_absSigSum[23:22]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_11_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_11 = _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:101:30, :103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_12_T = notCDom_absSigSum[24]; // @[primitives.scala:106:15] assign _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = _notCDom_reduced2AbsSigSum_reducedVec_12_T; // @[primitives.scala:106:{15,57}] assign notCDom_reduced2AbsSigSum_reducedVec_12 = _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:101:30, :106:57] wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_2, notCDom_reduced2AbsSigSum_reducedVec_1}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_0}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_5, notCDom_reduced2AbsSigSum_reducedVec_4}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_3}; // @[primitives.scala:101:30, :107:20] wire [5:0] notCDom_reduced2AbsSigSum_lo = {notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_8, notCDom_reduced2AbsSigSum_reducedVec_7}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_lo = {notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_6}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_10, notCDom_reduced2AbsSigSum_reducedVec_9}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_12, notCDom_reduced2AbsSigSum_reducedVec_11}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced2AbsSigSum_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo}; // @[primitives.scala:107:20] wire [6:0] notCDom_reduced2AbsSigSum_hi = {notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo}; // @[primitives.scala:107:20] wire [12:0] notCDom_reduced2AbsSigSum = {notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo}; // @[primitives.scala:107:20] wire _notCDom_normDistReduced2_T = notCDom_reduced2AbsSigSum[0]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_1 = notCDom_reduced2AbsSigSum[1]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_2 = notCDom_reduced2AbsSigSum[2]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_3 = notCDom_reduced2AbsSigSum[3]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_4 = notCDom_reduced2AbsSigSum[4]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_5 = notCDom_reduced2AbsSigSum[5]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_6 = notCDom_reduced2AbsSigSum[6]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_7 = notCDom_reduced2AbsSigSum[7]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_8 = notCDom_reduced2AbsSigSum[8]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_9 = notCDom_reduced2AbsSigSum[9]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_10 = notCDom_reduced2AbsSigSum[10]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_11 = notCDom_reduced2AbsSigSum[11]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_12 = notCDom_reduced2AbsSigSum[12]; // @[primitives.scala:91:52, :107:20] wire [3:0] _notCDom_normDistReduced2_T_13 = _notCDom_normDistReduced2_T_1 ? 4'hB : 4'hC; // @[Mux.scala:50:70] wire [3:0] _notCDom_normDistReduced2_T_14 = _notCDom_normDistReduced2_T_2 ? 4'hA : _notCDom_normDistReduced2_T_13; // @[Mux.scala:50:70] wire [3:0] _notCDom_normDistReduced2_T_15 = _notCDom_normDistReduced2_T_3 ? 4'h9 : _notCDom_normDistReduced2_T_14; // @[Mux.scala:50:70] wire [3:0] _notCDom_normDistReduced2_T_16 = _notCDom_normDistReduced2_T_4 ? 4'h8 : _notCDom_normDistReduced2_T_15; // @[Mux.scala:50:70] wire [3:0] _notCDom_normDistReduced2_T_17 = _notCDom_normDistReduced2_T_5 ? 4'h7 : _notCDom_normDistReduced2_T_16; // @[Mux.scala:50:70] wire [3:0] _notCDom_normDistReduced2_T_18 = _notCDom_normDistReduced2_T_6 ? 4'h6 : _notCDom_normDistReduced2_T_17; // @[Mux.scala:50:70] wire [3:0] _notCDom_normDistReduced2_T_19 = _notCDom_normDistReduced2_T_7 ? 4'h5 : _notCDom_normDistReduced2_T_18; // @[Mux.scala:50:70] wire [3:0] _notCDom_normDistReduced2_T_20 = _notCDom_normDistReduced2_T_8 ? 4'h4 : _notCDom_normDistReduced2_T_19; // @[Mux.scala:50:70] wire [3:0] _notCDom_normDistReduced2_T_21 = _notCDom_normDistReduced2_T_9 ? 4'h3 : _notCDom_normDistReduced2_T_20; // @[Mux.scala:50:70] wire [3:0] _notCDom_normDistReduced2_T_22 = _notCDom_normDistReduced2_T_10 ? 4'h2 : _notCDom_normDistReduced2_T_21; // @[Mux.scala:50:70] wire [3:0] _notCDom_normDistReduced2_T_23 = _notCDom_normDistReduced2_T_11 ? 4'h1 : _notCDom_normDistReduced2_T_22; // @[Mux.scala:50:70] wire [3:0] notCDom_normDistReduced2 = _notCDom_normDistReduced2_T_12 ? 4'h0 : _notCDom_normDistReduced2_T_23; // @[Mux.scala:50:70] wire [4:0] notCDom_nearNormDist = {notCDom_normDistReduced2, 1'h0}; // @[Mux.scala:50:70] wire [5:0] _notCDom_sExp_T = {1'h0, notCDom_nearNormDist}; // @[MulAddRecFN.scala:240:56, :241:76] wire [7:0] _notCDom_sExp_T_1 = _GEN - {{2{_notCDom_sExp_T[5]}}, _notCDom_sExp_T}; // @[MulAddRecFN.scala:203:43, :241:{46,76}] wire [6:0] _notCDom_sExp_T_2 = _notCDom_sExp_T_1[6:0]; // @[MulAddRecFN.scala:241:46] wire [6:0] notCDom_sExp = _notCDom_sExp_T_2; // @[MulAddRecFN.scala:241:46] wire [55:0] _notCDom_mainSig_T = {31'h0, notCDom_absSigSum} << notCDom_nearNormDist; // @[MulAddRecFN.scala:234:12, :240:56, :243:27] wire [15:0] notCDom_mainSig = _notCDom_mainSig_T[25:10]; // @[MulAddRecFN.scala:243:{27,50}] wire [5:0] _notCDom_reduced4SigExtra_T = notCDom_reduced2AbsSigSum[5:0]; // @[primitives.scala:107:20] wire [6:0] _notCDom_reduced4SigExtra_T_1 = {_notCDom_reduced4SigExtra_T, 1'h0}; // @[MulAddRecFN.scala:247:{39,55}] wire _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:106:57] wire notCDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:101:30] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_0_T = _notCDom_reduced4SigExtra_T_1[1:0]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_0_T_1 = |_notCDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_0 = _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_1_T = _notCDom_reduced4SigExtra_T_1[3:2]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_1_T_1 = |_notCDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_1 = _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_2_T = _notCDom_reduced4SigExtra_T_1[5:4]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_2_T_1 = |_notCDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_2 = _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54] wire _notCDom_reduced4SigExtra_reducedVec_3_T = _notCDom_reduced4SigExtra_T_1[6]; // @[primitives.scala:106:15] assign _notCDom_reduced4SigExtra_reducedVec_3_T_1 = _notCDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:106:{15,57}] assign notCDom_reduced4SigExtra_reducedVec_3 = _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:101:30, :106:57] wire [1:0] notCDom_reduced4SigExtra_lo = {notCDom_reduced4SigExtra_reducedVec_1, notCDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced4SigExtra_hi = {notCDom_reduced4SigExtra_reducedVec_3, notCDom_reduced4SigExtra_reducedVec_2}; // @[primitives.scala:101:30, :107:20] wire [3:0] _notCDom_reduced4SigExtra_T_2 = {notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo}; // @[primitives.scala:107:20] wire [2:0] _notCDom_reduced4SigExtra_T_3 = notCDom_normDistReduced2[3:1]; // @[Mux.scala:50:70] wire [2:0] _notCDom_reduced4SigExtra_T_4 = ~_notCDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21] wire [8:0] notCDom_reduced4SigExtra_shift = $signed(9'sh100 >>> _notCDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56] wire [2:0] _notCDom_reduced4SigExtra_T_5 = notCDom_reduced4SigExtra_shift[3:1]; // @[primitives.scala:76:56, :78:22] wire [1:0] _notCDom_reduced4SigExtra_T_6 = _notCDom_reduced4SigExtra_T_5[1:0]; // @[primitives.scala:77:20, :78:22] wire _notCDom_reduced4SigExtra_T_7 = _notCDom_reduced4SigExtra_T_6[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_8 = _notCDom_reduced4SigExtra_T_6[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_9 = {_notCDom_reduced4SigExtra_T_7, _notCDom_reduced4SigExtra_T_8}; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_10 = _notCDom_reduced4SigExtra_T_5[2]; // @[primitives.scala:77:20, :78:22] wire [2:0] _notCDom_reduced4SigExtra_T_11 = {_notCDom_reduced4SigExtra_T_9, _notCDom_reduced4SigExtra_T_10}; // @[primitives.scala:77:20] wire [3:0] _notCDom_reduced4SigExtra_T_12 = {1'h0, _notCDom_reduced4SigExtra_T_2[2:0] & _notCDom_reduced4SigExtra_T_11}; // @[primitives.scala:77:20, :107:20] wire notCDom_reduced4SigExtra = |_notCDom_reduced4SigExtra_T_12; // @[MulAddRecFN.scala:247:78, :249:11] wire [12:0] _notCDom_sig_T = notCDom_mainSig[15:3]; // @[MulAddRecFN.scala:243:50, :251:28] wire [2:0] _notCDom_sig_T_1 = notCDom_mainSig[2:0]; // @[MulAddRecFN.scala:243:50, :252:28] wire _notCDom_sig_T_2 = |_notCDom_sig_T_1; // @[MulAddRecFN.scala:252:{28,35}] wire _notCDom_sig_T_3 = _notCDom_sig_T_2 | notCDom_reduced4SigExtra; // @[MulAddRecFN.scala:249:11, :252:{35,39}] wire [13:0] notCDom_sig = {_notCDom_sig_T, _notCDom_sig_T_3}; // @[MulAddRecFN.scala:251:{12,28}, :252:39] wire [1:0] _notCDom_completeCancellation_T = notCDom_sig[13:12]; // @[MulAddRecFN.scala:251:12, :255:21] wire notCDom_completeCancellation = _notCDom_completeCancellation_T == 2'h0; // @[primitives.scala:103:54] wire _notCDom_sign_T = io_fromPreMul_signProd_0 ^ notCDom_signSigSum; // @[MulAddRecFN.scala:169:7, :232:36, :259:36] wire notCDom_sign = notCDom_completeCancellation ? roundingMode_min : _notCDom_sign_T; // @[MulAddRecFN.scala:186:45, :255:50, :257:12, :259:36] wire _GEN_0 = io_fromPreMul_isInfA_0 | io_fromPreMul_isInfB_0; // @[MulAddRecFN.scala:169:7, :264:49] wire notNaN_isInfProd; // @[MulAddRecFN.scala:264:49] assign notNaN_isInfProd = _GEN_0; // @[MulAddRecFN.scala:264:49] wire _io_invalidExc_T_5; // @[MulAddRecFN.scala:275:36] assign _io_invalidExc_T_5 = _GEN_0; // @[MulAddRecFN.scala:264:49, :275:36] assign notNaN_isInfOut = notNaN_isInfProd | io_fromPreMul_isInfC_0; // @[MulAddRecFN.scala:169:7, :264:49, :265:44] assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulAddRecFN.scala:169:7, :265:44] wire _notNaN_addZeros_T = io_fromPreMul_isZeroA_0 | io_fromPreMul_isZeroB_0; // @[MulAddRecFN.scala:169:7, :267:32] wire notNaN_addZeros = _notNaN_addZeros_T & io_fromPreMul_isZeroC_0; // @[MulAddRecFN.scala:169:7, :267:{32,58}] wire _io_invalidExc_T = io_fromPreMul_isInfA_0 & io_fromPreMul_isZeroB_0; // @[MulAddRecFN.scala:169:7, :272:31] wire _io_invalidExc_T_1 = io_fromPreMul_isSigNaNAny_0 | _io_invalidExc_T; // @[MulAddRecFN.scala:169:7, :271:35, :272:31] wire _io_invalidExc_T_2 = io_fromPreMul_isZeroA_0 & io_fromPreMul_isInfB_0; // @[MulAddRecFN.scala:169:7, :273:32] wire _io_invalidExc_T_3 = _io_invalidExc_T_1 | _io_invalidExc_T_2; // @[MulAddRecFN.scala:271:35, :272:57, :273:32] wire _io_invalidExc_T_4 = ~io_fromPreMul_isNaNAOrB_0; // @[MulAddRecFN.scala:169:7, :274:10] wire _io_invalidExc_T_6 = _io_invalidExc_T_4 & _io_invalidExc_T_5; // @[MulAddRecFN.scala:274:{10,36}, :275:36] wire _io_invalidExc_T_7 = _io_invalidExc_T_6 & io_fromPreMul_isInfC_0; // @[MulAddRecFN.scala:169:7, :274:36, :275:61] wire _io_invalidExc_T_8 = _io_invalidExc_T_7 & io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :275:61, :276:35] assign _io_invalidExc_T_9 = _io_invalidExc_T_3 | _io_invalidExc_T_8; // @[MulAddRecFN.scala:272:57, :273:57, :276:35] assign io_invalidExc_0 = _io_invalidExc_T_9; // @[MulAddRecFN.scala:169:7, :273:57] assign _io_rawOut_isNaN_T = io_fromPreMul_isNaNAOrB_0 | io_fromPreMul_isNaNC_0; // @[MulAddRecFN.scala:169:7, :278:48] assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:169:7, :278:48] wire _io_rawOut_isZero_T = ~io_fromPreMul_CIsDominant_0; // @[MulAddRecFN.scala:169:7, :283:14] wire _io_rawOut_isZero_T_1 = _io_rawOut_isZero_T & notCDom_completeCancellation; // @[MulAddRecFN.scala:255:50, :283:{14,42}] assign _io_rawOut_isZero_T_2 = notNaN_addZeros | _io_rawOut_isZero_T_1; // @[MulAddRecFN.scala:267:58, :282:25, :283:42] assign io_rawOut_isZero_0 = _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:169:7, :282:25] wire _io_rawOut_sign_T = notNaN_isInfProd & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :264:49, :285:27] wire _io_rawOut_sign_T_1 = io_fromPreMul_isInfC_0 & opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :286:31] wire _io_rawOut_sign_T_2 = _io_rawOut_sign_T | _io_rawOut_sign_T_1; // @[MulAddRecFN.scala:285:{27,54}, :286:31] wire _io_rawOut_sign_T_3 = ~roundingMode_min; // @[MulAddRecFN.scala:186:45, :287:29] wire _io_rawOut_sign_T_4 = notNaN_addZeros & _io_rawOut_sign_T_3; // @[MulAddRecFN.scala:267:58, :287:{26,29}] wire _io_rawOut_sign_T_5 = _io_rawOut_sign_T_4 & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :287:{26,48}] wire _io_rawOut_sign_T_6 = _io_rawOut_sign_T_5 & opSignC; // @[MulAddRecFN.scala:190:42, :287:48, :288:36] wire _io_rawOut_sign_T_7 = _io_rawOut_sign_T_2 | _io_rawOut_sign_T_6; // @[MulAddRecFN.scala:285:54, :286:43, :288:36] wire _io_rawOut_sign_T_8 = notNaN_addZeros & roundingMode_min; // @[MulAddRecFN.scala:186:45, :267:58, :289:26] wire _io_rawOut_sign_T_9 = io_fromPreMul_signProd_0 | opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :290:37] wire _io_rawOut_sign_T_10 = _io_rawOut_sign_T_8 & _io_rawOut_sign_T_9; // @[MulAddRecFN.scala:289:{26,46}, :290:37] wire _io_rawOut_sign_T_11 = _io_rawOut_sign_T_7 | _io_rawOut_sign_T_10; // @[MulAddRecFN.scala:286:43, :288:48, :289:46] wire _io_rawOut_sign_T_12 = ~notNaN_isInfOut; // @[MulAddRecFN.scala:265:44, :291:10] wire _io_rawOut_sign_T_13 = ~notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :291:31] wire _io_rawOut_sign_T_14 = _io_rawOut_sign_T_12 & _io_rawOut_sign_T_13; // @[MulAddRecFN.scala:291:{10,28,31}] wire _io_rawOut_sign_T_15 = io_fromPreMul_CIsDominant_0 ? opSignC : notCDom_sign; // @[MulAddRecFN.scala:169:7, :190:42, :257:12, :292:17] wire _io_rawOut_sign_T_16 = _io_rawOut_sign_T_14 & _io_rawOut_sign_T_15; // @[MulAddRecFN.scala:291:{28,49}, :292:17] assign _io_rawOut_sign_T_17 = _io_rawOut_sign_T_11 | _io_rawOut_sign_T_16; // @[MulAddRecFN.scala:288:48, :290:50, :291:49] assign io_rawOut_sign_0 = _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:169:7, :290:50] assign _io_rawOut_sExp_T = io_fromPreMul_CIsDominant_0 ? CDom_sExp : notCDom_sExp; // @[MulAddRecFN.scala:169:7, :203:43, :241:46, :293:26] assign io_rawOut_sExp_0 = _io_rawOut_sExp_T; // @[MulAddRecFN.scala:169:7, :293:26] assign _io_rawOut_sig_T = io_fromPreMul_CIsDominant_0 ? CDom_sig : notCDom_sig; // @[MulAddRecFN.scala:169:7, :225:12, :251:12, :294:25] assign io_rawOut_sig_0 = _io_rawOut_sig_T; // @[MulAddRecFN.scala:169:7, :294:25] assign io_invalidExc = io_invalidExc_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sign = io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sig = io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }

module AsyncResetSynchronizerShiftReg_w4_d3_i0_18( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input [3:0] io_d, // @[ShiftReg.scala:36:14] output [3:0] io_q // @[ShiftReg.scala:36:14] ); wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21] wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14] wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7] wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_1; // @[ShiftReg.scala:48:24] wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_2; // @[ShiftReg.scala:48:24] wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_3; // @[ShiftReg.scala:48:24] wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14] wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14] assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14] assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_181 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_182 output_chain_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_2), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_3), // @[SynchronizerReg.scala:87:41] .io_q (output_1) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_183 output_chain_2 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_4), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_5), // @[SynchronizerReg.scala:87:41] .io_q (output_2) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_184 output_chain_3 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_6), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_7), // @[SynchronizerReg.scala:87:41] .io_q (output_3) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag }

module OptimizationBarrier_TLBEntryData_249( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Fragmenter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet, BufferParams, IdRange, TransferSizes} import freechips.rocketchip.util.{Repeater, OH1ToUInt, UIntToOH1} import scala.math.min import freechips.rocketchip.util.DataToAugmentedData object EarlyAck { sealed trait T case object AllPuts extends T case object PutFulls extends T case object None extends T } // minSize: minimum size of transfers supported by all outward managers // maxSize: maximum size of transfers supported after the Fragmenter is applied // alwaysMin: fragment all requests down to minSize (else fragment to maximum supported by manager) // earlyAck: should a multibeat Put should be acknowledged on the first beat or last beat // holdFirstDeny: allow the Fragmenter to unsafely combine multibeat Gets by taking the first denied for the whole burst // nameSuffix: appends a suffix to the module name // Fragmenter modifies: PutFull, PutPartial, LogicalData, Get, Hint // Fragmenter passes: ArithmeticData (truncated to minSize if alwaysMin) // Fragmenter cannot modify acquire (could livelock); thus it is unsafe to put caches on both sides class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean = false, val earlyAck: EarlyAck.T = EarlyAck.None, val holdFirstDeny: Boolean = false, val nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule { require(isPow2 (maxSize), s"TLFragmenter expects pow2(maxSize), but got $maxSize") require(isPow2 (minSize), s"TLFragmenter expects pow2(minSize), but got $minSize") require(minSize <= maxSize, s"TLFragmenter expects min <= max, but got $minSize > $maxSize") val fragmentBits = log2Ceil(maxSize / minSize) val fullBits = if (earlyAck == EarlyAck.PutFulls) 1 else 0 val toggleBits = 1 val addedBits = fragmentBits + toggleBits + fullBits def expandTransfer(x: TransferSizes, op: String) = if (!x) x else { // validate that we can apply the fragmenter correctly require (x.max >= minSize, s"TLFragmenter (with parent $parent) max transfer size $op(${x.max}) must be >= min transfer size (${minSize})") TransferSizes(x.min, maxSize) } private def noChangeRequired = minSize == maxSize private def shrinkTransfer(x: TransferSizes) = if (!alwaysMin) x else if (x.min <= minSize) TransferSizes(x.min, min(minSize, x.max)) else TransferSizes.none private def mapManager(m: TLSlaveParameters) = m.v1copy( supportsArithmetic = shrinkTransfer(m.supportsArithmetic), supportsLogical = shrinkTransfer(m.supportsLogical), supportsGet = expandTransfer(m.supportsGet, "Get"), supportsPutFull = expandTransfer(m.supportsPutFull, "PutFull"), supportsPutPartial = expandTransfer(m.supportsPutPartial, "PutParital"), supportsHint = expandTransfer(m.supportsHint, "Hint")) val node = new TLAdapterNode( // We require that all the responses are mutually FIFO // Thus we need to compact all of the masters into one big master clientFn = { c => (if (noChangeRequired) c else c.v2copy( masters = Seq(TLMasterParameters.v2( name = "TLFragmenter", sourceId = IdRange(0, if (minSize == maxSize) c.endSourceId else (c.endSourceId << addedBits)), requestFifo = true, emits = TLMasterToSlaveTransferSizes( acquireT = shrinkTransfer(c.masters.map(_.emits.acquireT) .reduce(_ mincover _)), acquireB = shrinkTransfer(c.masters.map(_.emits.acquireB) .reduce(_ mincover _)), arithmetic = shrinkTransfer(c.masters.map(_.emits.arithmetic).reduce(_ mincover _)), logical = shrinkTransfer(c.masters.map(_.emits.logical) .reduce(_ mincover _)), get = shrinkTransfer(c.masters.map(_.emits.get) .reduce(_ mincover _)), putFull = shrinkTransfer(c.masters.map(_.emits.putFull) .reduce(_ mincover _)), putPartial = shrinkTransfer(c.masters.map(_.emits.putPartial).reduce(_ mincover _)), hint = shrinkTransfer(c.masters.map(_.emits.hint) .reduce(_ mincover _)) ) )) ))}, managerFn = { m => if (noChangeRequired) m else m.v2copy(slaves = m.slaves.map(mapManager)) } ) { override def circuitIdentity = noChangeRequired } lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = (Seq("TLFragmenter") ++ nameSuffix).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => if (noChangeRequired) { out <> in } else { // All managers must share a common FIFO domain (responses might end up interleaved) val manager = edgeOut.manager val managers = manager.managers val beatBytes = manager.beatBytes val fifoId = managers(0).fifoId require (fifoId.isDefined && managers.map(_.fifoId == fifoId).reduce(_ && _)) require (!manager.anySupportAcquireB || !edgeOut.client.anySupportProbe, s"TLFragmenter (with parent $parent) can't fragment a caching client's requests into a cacheable region") require (minSize >= beatBytes, s"TLFragmenter (with parent $parent) can't support fragmenting ($minSize) to sub-beat ($beatBytes) accesses") // We can't support devices which are cached on both sides of us require (!edgeOut.manager.anySupportAcquireB || !edgeIn.client.anySupportProbe) // We can't support denied because we reassemble fragments require (!edgeOut.manager.mayDenyGet || holdFirstDeny, s"TLFragmenter (with parent $parent) can't support denials without holdFirstDeny=true") require (!edgeOut.manager.mayDenyPut || earlyAck == EarlyAck.None) /* The Fragmenter is a bit tricky, because there are 5 sizes in play: * max size -- the maximum transfer size possible * orig size -- the original pre-fragmenter size * frag size -- the modified post-fragmenter size * min size -- the threshold below which frag=orig * beat size -- the amount transfered on any given beat * * The relationships are as follows: * max >= orig >= frag * max > min >= beat * It IS possible that orig <= min (then frag=orig; ie: no fragmentation) * * The fragment# (sent via TL.source) is measured in multiples of min size. * Meanwhile, to track the progress, counters measure in multiples of beat size. * * Here is an example of a bus with max=256, min=8, beat=4 and a device supporting 16. * * in.A out.A (frag#) out.D (frag#) in.D gen# ack# * get64 get16 6 ackD16 6 ackD64 12 15 * ackD16 6 ackD64 14 * ackD16 6 ackD64 13 * ackD16 6 ackD64 12 * get16 4 ackD16 4 ackD64 8 11 * ackD16 4 ackD64 10 * ackD16 4 ackD64 9 * ackD16 4 ackD64 8 * get16 2 ackD16 2 ackD64 4 7 * ackD16 2 ackD64 6 * ackD16 2 ackD64 5 * ackD16 2 ackD64 4 * get16 0 ackD16 0 ackD64 0 3 * ackD16 0 ackD64 2 * ackD16 0 ackD64 1 * ackD16 0 ackD64 0 * * get8 get8 0 ackD8 0 ackD8 0 1 * ackD8 0 ackD8 0 * * get4 get4 0 ackD4 0 ackD4 0 0 * get1 get1 0 ackD1 0 ackD1 0 0 * * put64 put16 6 15 * put64 put16 6 14 * put64 put16 6 13 * put64 put16 6 ack16 6 12 12 * put64 put16 4 11 * put64 put16 4 10 * put64 put16 4 9 * put64 put16 4 ack16 4 8 8 * put64 put16 2 7 * put64 put16 2 6 * put64 put16 2 5 * put64 put16 2 ack16 2 4 4 * put64 put16 0 3 * put64 put16 0 2 * put64 put16 0 1 * put64 put16 0 ack16 0 ack64 0 0 * * put8 put8 0 1 * put8 put8 0 ack8 0 ack8 0 0 * * put4 put4 0 ack4 0 ack4 0 0 * put1 put1 0 ack1 0 ack1 0 0 */ val counterBits = log2Up(maxSize/beatBytes) val maxDownSize = if (alwaysMin) minSize else min(manager.maxTransfer, maxSize) // Consider the following waveform for two 4-beat bursts: // ---A----A------------ // -------D-----DDD-DDDD // Under TL rules, the second A can use the same source as the first A, // because the source is released for reuse on the first response beat. // // However, if we fragment the requests, it looks like this: // ---3210-3210--------- // -------3-----210-3210 // ... now we've broken the rules because 210 are twice inflight. // // This phenomenon means we can have essentially 2*maxSize/minSize-1 // fragmented transactions in flight per original transaction source. // // To keep the source unique, we encode the beat counter in the low // bits of the source. To solve the overlap, we use a toggle bit. // Whatever toggle bit the D is reassembling, A will use the opposite. // First, handle the return path val acknum = RegInit(0.U(counterBits.W)) val dOrig = Reg(UInt()) val dToggle = RegInit(false.B) val dFragnum = out.d.bits.source(fragmentBits-1, 0) val dFirst = acknum === 0.U val dLast = dFragnum === 0.U // only for AccessAck (!Data) val dsizeOH = UIntToOH (out.d.bits.size, log2Ceil(maxDownSize)+1) val dsizeOH1 = UIntToOH1(out.d.bits.size, log2Up(maxDownSize)) val dHasData = edgeOut.hasData(out.d.bits) // calculate new acknum val acknum_fragment = dFragnum << log2Ceil(minSize/beatBytes) val acknum_size = dsizeOH1 >> log2Ceil(beatBytes) assert (!out.d.valid || (acknum_fragment & acknum_size) === 0.U) val dFirst_acknum = acknum_fragment | Mux(dHasData, acknum_size, 0.U) val ack_decrement = Mux(dHasData, 1.U, dsizeOH >> log2Ceil(beatBytes)) // calculate the original size val dFirst_size = OH1ToUInt((dFragnum << log2Ceil(minSize)) | dsizeOH1) when (out.d.fire) { acknum := Mux(dFirst, dFirst_acknum, acknum - ack_decrement) when (dFirst) { dOrig := dFirst_size dToggle := out.d.bits.source(fragmentBits) } } // Swallow up non-data ack fragments val doEarlyAck = earlyAck match { case EarlyAck.AllPuts => true.B case EarlyAck.PutFulls => out.d.bits.source(fragmentBits+1) case EarlyAck.None => false.B } val drop = !dHasData && !Mux(doEarlyAck, dFirst, dLast) out.d.ready := in.d.ready || drop in.d.valid := out.d.valid && !drop in.d.bits := out.d.bits // pass most stuff unchanged in.d.bits.source := out.d.bits.source >> addedBits in.d.bits.size := Mux(dFirst, dFirst_size, dOrig) if (edgeOut.manager.mayDenyPut) { val r_denied = Reg(Bool()) val d_denied = (!dFirst && r_denied) || out.d.bits.denied when (out.d.fire) { r_denied := d_denied } in.d.bits.denied := d_denied } if (edgeOut.manager.mayDenyGet) { // Take denied only from the first beat and hold that value val d_denied = out.d.bits.denied holdUnless dFirst when (dHasData) { in.d.bits.denied := d_denied in.d.bits.corrupt := d_denied || out.d.bits.corrupt } } // What maximum transfer sizes do downstream devices support? val maxArithmetics = managers.map(_.supportsArithmetic.max) val maxLogicals = managers.map(_.supportsLogical.max) val maxGets = managers.map(_.supportsGet.max) val maxPutFulls = managers.map(_.supportsPutFull.max) val maxPutPartials = managers.map(_.supportsPutPartial.max) val maxHints = managers.map(m => if (m.supportsHint) maxDownSize else 0) // We assume that the request is valid => size 0 is impossible val lgMinSize = log2Ceil(minSize).U val maxLgArithmetics = maxArithmetics.map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgLogicals = maxLogicals .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgGets = maxGets .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgPutFulls = maxPutFulls .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgPutPartials = maxPutPartials.map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgHints = maxHints .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) // Make the request repeatable val repeater = Module(new Repeater(in.a.bits)) repeater.io.enq <> in.a val in_a = repeater.io.deq // If this is infront of a single manager, these become constants val find = manager.findFast(edgeIn.address(in_a.bits)) val maxLgArithmetic = Mux1H(find, maxLgArithmetics) val maxLgLogical = Mux1H(find, maxLgLogicals) val maxLgGet = Mux1H(find, maxLgGets) val maxLgPutFull = Mux1H(find, maxLgPutFulls) val maxLgPutPartial = Mux1H(find, maxLgPutPartials) val maxLgHint = Mux1H(find, maxLgHints) val limit = if (alwaysMin) lgMinSize else MuxLookup(in_a.bits.opcode, lgMinSize)(Array( TLMessages.PutFullData -> maxLgPutFull, TLMessages.PutPartialData -> maxLgPutPartial, TLMessages.ArithmeticData -> maxLgArithmetic, TLMessages.LogicalData -> maxLgLogical, TLMessages.Get -> maxLgGet, TLMessages.Hint -> maxLgHint)) val aOrig = in_a.bits.size val aFrag = Mux(aOrig > limit, limit, aOrig) val aOrigOH1 = UIntToOH1(aOrig, log2Ceil(maxSize)) val aFragOH1 = UIntToOH1(aFrag, log2Up(maxDownSize)) val aHasData = edgeIn.hasData(in_a.bits) val aMask = Mux(aHasData, 0.U, aFragOH1) val gennum = RegInit(0.U(counterBits.W)) val aFirst = gennum === 0.U val old_gennum1 = Mux(aFirst, aOrigOH1 >> log2Ceil(beatBytes), gennum - 1.U) val new_gennum = ~(~old_gennum1 | (aMask >> log2Ceil(beatBytes))) // ~(~x|y) is width safe val aFragnum = ~(~(old_gennum1 >> log2Ceil(minSize/beatBytes)) | (aFragOH1 >> log2Ceil(minSize))) val aLast = aFragnum === 0.U val aToggle = !Mux(aFirst, dToggle, RegEnable(dToggle, aFirst)) val aFull = if (earlyAck == EarlyAck.PutFulls) Some(in_a.bits.opcode === TLMessages.PutFullData) else None when (out.a.fire) { gennum := new_gennum } repeater.io.repeat := !aHasData && aFragnum =/= 0.U out.a <> in_a out.a.bits.address := in_a.bits.address | ~(old_gennum1 << log2Ceil(beatBytes) | ~aOrigOH1 | aFragOH1 | (minSize-1).U) out.a.bits.source := Cat(Seq(in_a.bits.source) ++ aFull ++ Seq(aToggle.asUInt, aFragnum)) out.a.bits.size := aFrag // Optimize away some of the Repeater's registers assert (!repeater.io.full || !aHasData) out.a.bits.data := in.a.bits.data val fullMask = ((BigInt(1) << beatBytes) - 1).U assert (!repeater.io.full || in_a.bits.mask === fullMask) out.a.bits.mask := Mux(repeater.io.full, fullMask, in.a.bits.mask) out.a.bits.user.waiveAll :<= in.a.bits.user.subset(_.isData) // Tie off unused channels in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLFragmenter { def apply(minSize: Int, maxSize: Int, alwaysMin: Boolean = false, earlyAck: EarlyAck.T = EarlyAck.None, holdFirstDeny: Boolean = false, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode = { if (minSize <= maxSize) { val fragmenter = LazyModule(new TLFragmenter(minSize, maxSize, alwaysMin, earlyAck, holdFirstDeny, nameSuffix)) fragmenter.node } else { TLEphemeralNode()(ValName("no_fragmenter")) } } def apply(wrapper: TLBusWrapper, nameSuffix: Option[String])(implicit p: Parameters): TLNode = apply(wrapper.beatBytes, wrapper.blockBytes, nameSuffix = nameSuffix) def apply(wrapper: TLBusWrapper)(implicit p: Parameters): TLNode = apply(wrapper, None) } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMFragmenter(ramBeatBytes: Int, maxSize: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("Fragmenter")) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes)) (ram.node := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := TLDelayer(0.1) := TLFragmenter(ramBeatBytes, maxSize, earlyAck = EarlyAck.AllPuts) := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := TLFragmenter(ramBeatBytes, maxSize/2) := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := model.node := fuzz.node) lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMFragmenterTest(ramBeatBytes: Int, maxSize: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMFragmenter(ramBeatBytes,maxSize,txns)).module) io.finished := dut.io.finished dut.io.start := io.start } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } }

module TLInterconnectCoupler_cbus_to_plic( // @[LazyModuleImp.scala:138:7] input clock, // @[LazyModuleImp.scala:138:7] input reset, // @[LazyModuleImp.scala:138:7] input auto_fragmenter_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_fragmenter_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_fragmenter_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_fragmenter_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_fragmenter_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [11:0] auto_fragmenter_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [27:0] auto_fragmenter_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_fragmenter_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_fragmenter_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_fragmenter_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_fragmenter_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_fragmenter_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_fragmenter_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_fragmenter_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [11:0] auto_fragmenter_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_fragmenter_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_tl_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [7:0] auto_tl_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [27:0] auto_tl_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_tl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_tl_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_tl_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [7:0] auto_tl_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_tl_in_d_bits_data // @[LazyModuleImp.scala:107:25] ); TLFragmenter_PLIC fragmenter ( // @[Fragmenter.scala:345:34] .clock (clock), .reset (reset), .auto_anon_in_a_ready (auto_tl_in_a_ready), .auto_anon_in_a_valid (auto_tl_in_a_valid), .auto_anon_in_a_bits_opcode (auto_tl_in_a_bits_opcode), .auto_anon_in_a_bits_param (auto_tl_in_a_bits_param), .auto_anon_in_a_bits_size (auto_tl_in_a_bits_size), .auto_anon_in_a_bits_source (auto_tl_in_a_bits_source), .auto_anon_in_a_bits_address (auto_tl_in_a_bits_address), .auto_anon_in_a_bits_mask (auto_tl_in_a_bits_mask), .auto_anon_in_a_bits_data (auto_tl_in_a_bits_data), .auto_anon_in_a_bits_corrupt (auto_tl_in_a_bits_corrupt), .auto_anon_in_d_ready (auto_tl_in_d_ready), .auto_anon_in_d_valid (auto_tl_in_d_valid), .auto_anon_in_d_bits_opcode (auto_tl_in_d_bits_opcode), .auto_anon_in_d_bits_size (auto_tl_in_d_bits_size), .auto_anon_in_d_bits_source (auto_tl_in_d_bits_source), .auto_anon_in_d_bits_data (auto_tl_in_d_bits_data), .auto_anon_out_a_ready (auto_fragmenter_anon_out_a_ready), .auto_anon_out_a_valid (auto_fragmenter_anon_out_a_valid), .auto_anon_out_a_bits_opcode (auto_fragmenter_anon_out_a_bits_opcode), .auto_anon_out_a_bits_param (auto_fragmenter_anon_out_a_bits_param), .auto_anon_out_a_bits_size (auto_fragmenter_anon_out_a_bits_size), .auto_anon_out_a_bits_source (auto_fragmenter_anon_out_a_bits_source), .auto_anon_out_a_bits_address (auto_fragmenter_anon_out_a_bits_address), .auto_anon_out_a_bits_mask (auto_fragmenter_anon_out_a_bits_mask), .auto_anon_out_a_bits_data (auto_fragmenter_anon_out_a_bits_data), .auto_anon_out_a_bits_corrupt (auto_fragmenter_anon_out_a_bits_corrupt), .auto_anon_out_d_ready (auto_fragmenter_anon_out_d_ready), .auto_anon_out_d_valid (auto_fragmenter_anon_out_d_valid), .auto_anon_out_d_bits_opcode (auto_fragmenter_anon_out_d_bits_opcode), .auto_anon_out_d_bits_size (auto_fragmenter_anon_out_d_bits_size), .auto_anon_out_d_bits_source (auto_fragmenter_anon_out_d_bits_source), .auto_anon_out_d_bits_data (auto_fragmenter_anon_out_d_bits_data) ); // @[Fragmenter.scala:345:34] endmodule

Generate the Verilog code corresponding to the following Chisel files. File DescribedSRAM.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3.{Data, SyncReadMem, Vec} import chisel3.util.log2Ceil object DescribedSRAM { def apply[T <: Data]( name: String, desc: String, size: BigInt, // depth data: T ): SyncReadMem[T] = { val mem = SyncReadMem(size, data) mem.suggestName(name) val granWidth = data match { case v: Vec[_] => v.head.getWidth case d => d.getWidth } val uid = 0 Annotated.srams( component = mem, name = name, address_width = log2Ceil(size), data_width = data.getWidth, depth = size, description = desc, write_mask_granularity = granWidth ) mem } }

module dataArrayB0Way_7_0( // @[DescribedSRAM.scala:17:26] input [7:0] RW0_addr, input RW0_en, input RW0_clk, input RW0_wmode, input [63:0] RW0_wdata, output [63:0] RW0_rdata ); dataArrayB0Way_0_ext dataArrayB0Way_0_ext ( // @[DescribedSRAM.scala:17:26] .RW0_addr (RW0_addr), .RW0_en (RW0_en), .RW0_clk (RW0_clk), .RW0_wmode (RW0_wmode), .RW0_wdata (RW0_wdata), .RW0_rdata (RW0_rdata) ); // @[DescribedSRAM.scala:17:26] endmodule

Generate the Verilog code corresponding to the following Chisel files. File TilelinkAdapters.scala: package constellation.protocol import chisel3._ import chisel3.util._ import constellation.channel._ import constellation.noc._ import constellation.soc.{CanAttachToGlobalNoC} import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.util._ import freechips.rocketchip.tilelink._ import scala.collection.immutable.{ListMap} abstract class TLChannelToNoC[T <: TLChannel](gen: => T, edge: TLEdge, idToEgress: Int => Int)(implicit val p: Parameters) extends Module with TLFieldHelper { val flitWidth = minTLPayloadWidth(gen) val io = IO(new Bundle { val protocol = Flipped(Decoupled(gen)) val flit = Decoupled(new IngressFlit(flitWidth)) }) def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B // convert decoupled to irrevocable val q = Module(new Queue(gen, 1, pipe=true, flow=true)) val protocol = q.io.deq val has_body = Wire(Bool()) val body_fields = getBodyFields(protocol.bits) val const_fields = getConstFields(protocol.bits) val head = edge.first(protocol.bits, protocol.fire) val tail = edge.last(protocol.bits, protocol.fire) def requestOH: Seq[Bool] val body = Cat( body_fields.filter(_.getWidth > 0).map(_.asUInt)) val const = Cat(const_fields.filter(_.getWidth > 0).map(_.asUInt)) val is_body = RegInit(false.B) io.flit.valid := protocol.valid protocol.ready := io.flit.ready && (is_body || !has_body) io.flit.bits.head := head && !is_body io.flit.bits.tail := tail && (is_body || !has_body) io.flit.bits.egress_id := Mux1H(requestOH.zipWithIndex.map { case (r, i) => r -> idToEgress(i).U }) io.flit.bits.payload := Mux(is_body, body, const) when (io.flit.fire && io.flit.bits.head) { is_body := true.B } when (io.flit.fire && io.flit.bits.tail) { is_body := false.B } } abstract class TLChannelFromNoC[T <: TLChannel](gen: => T)(implicit val p: Parameters) extends Module with TLFieldHelper { val flitWidth = minTLPayloadWidth(gen) val io = IO(new Bundle { val protocol = Decoupled(gen) val flit = Flipped(Decoupled(new EgressFlit(flitWidth))) }) // Handle size = 1 gracefully (Chisel3 empty range is broken) def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0) val protocol = Wire(Decoupled(gen)) val body_fields = getBodyFields(protocol.bits) val const_fields = getConstFields(protocol.bits) val is_const = RegInit(true.B) val const_reg = Reg(UInt(const_fields.map(_.getWidth).sum.W)) val const = Mux(io.flit.bits.head, io.flit.bits.payload, const_reg) io.flit.ready := (is_const && !io.flit.bits.tail) || protocol.ready protocol.valid := (!is_const || io.flit.bits.tail) && io.flit.valid def assign(i: UInt, sigs: Seq[Data]) = { var t = i for (s <- sigs.reverse) { s := t.asTypeOf(s.cloneType) t = t >> s.getWidth } } assign(const, const_fields) assign(io.flit.bits.payload, body_fields) when (io.flit.fire && io.flit.bits.head) { is_const := false.B; const_reg := io.flit.bits.payload } when (io.flit.fire && io.flit.bits.tail) { is_const := true.B } } trait HasAddressDecoder { // Filter a list to only those elements selected def filter[T](data: Seq[T], mask: Seq[Boolean]) = (data zip mask).filter(_._2).map(_._1) val edgeIn: TLEdge val edgesOut: Seq[TLEdge] lazy val reacheableIO = edgesOut.map { mp => edgeIn.client.clients.exists { c => mp.manager.managers.exists { m => c.visibility.exists { ca => m.address.exists { ma => ca.overlaps(ma) }} }} }.toVector lazy val releaseIO = (edgesOut zip reacheableIO).map { case (mp, reachable) => reachable && edgeIn.client.anySupportProbe && mp.manager.anySupportAcquireB }.toVector def outputPortFn(connectIO: Seq[Boolean]) = { val port_addrs = edgesOut.map(_.manager.managers.flatMap(_.address)) val routingMask = AddressDecoder(filter(port_addrs, connectIO)) val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct)) route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_||_)) } } class TLAToNoC( val edgeIn: TLEdge, val edgesOut: Seq[TLEdge], bundle: TLBundleParameters, slaveToAEgress: Int => Int, sourceStart: Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleA(bundle), edgeIn, slaveToAEgress)(p) with HasAddressDecoder { has_body := edgeIn.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U) lazy val connectAIO = reacheableIO lazy val requestOH = outputPortFn(connectAIO).zipWithIndex.map { case (o, j) => connectAIO(j).B && (unique(connectAIO) || o(protocol.bits.address)) } q.io.enq <> io.protocol q.io.enq.bits.source := io.protocol.bits.source | sourceStart.U } class TLAFromNoC(edgeOut: TLEdge, bundle: TLBundleParameters)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleA(bundle))(p) { io.protocol <> protocol when (io.flit.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) } } class TLBToNoC( edgeOut: TLEdge, edgesIn: Seq[TLEdge], bundle: TLBundleParameters, masterToBIngress: Int => Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleB(bundle), edgeOut, masterToBIngress)(p) { has_body := edgeOut.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U) lazy val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client)) lazy val requestOH = inputIdRanges.map { i => i.contains(protocol.bits.source) } q.io.enq <> io.protocol } class TLBFromNoC(edgeIn: TLEdge, bundle: TLBundleParameters, sourceSize: Int)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleB(bundle))(p) { io.protocol <> protocol io.protocol.bits.source := trim(protocol.bits.source, sourceSize) when (io.flit.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) } } class TLCToNoC( val edgeIn: TLEdge, val edgesOut: Seq[TLEdge], bundle: TLBundleParameters, slaveToCEgress: Int => Int, sourceStart: Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleC(bundle), edgeIn, slaveToCEgress)(p) with HasAddressDecoder { has_body := edgeIn.hasData(protocol.bits) lazy val connectCIO = releaseIO lazy val requestOH = outputPortFn(connectCIO).zipWithIndex.map { case (o, j) => connectCIO(j).B && (unique(connectCIO) || o(protocol.bits.address)) } q.io.enq <> io.protocol q.io.enq.bits.source := io.protocol.bits.source | sourceStart.U } class TLCFromNoC(edgeOut: TLEdge, bundle: TLBundleParameters)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleC(bundle))(p) { io.protocol <> protocol } class TLDToNoC( edgeOut: TLEdge, edgesIn: Seq[TLEdge], bundle: TLBundleParameters, masterToDIngress: Int => Int, sourceStart: Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleD(bundle), edgeOut, masterToDIngress)(p) { has_body := edgeOut.hasData(protocol.bits) lazy val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client)) lazy val requestOH = inputIdRanges.map { i => i.contains(protocol.bits.source) } q.io.enq <> io.protocol q.io.enq.bits.sink := io.protocol.bits.sink | sourceStart.U } class TLDFromNoC(edgeIn: TLEdge, bundle: TLBundleParameters, sourceSize: Int)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleD(bundle))(p) { io.protocol <> protocol io.protocol.bits.source := trim(protocol.bits.source, sourceSize) } class TLEToNoC( val edgeIn: TLEdge, val edgesOut: Seq[TLEdge], bundle: TLBundleParameters, slaveToEEgress: Int => Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleE(bundle), edgeIn, slaveToEEgress)(p) { has_body := edgeIn.hasData(protocol.bits) lazy val outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager)) lazy val requestOH = outputIdRanges.map { o => o.contains(protocol.bits.sink) } q.io.enq <> io.protocol } class TLEFromNoC(edgeOut: TLEdge, bundle: TLBundleParameters, sourceSize: Int)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleE(bundle))(p) { io.protocol <> protocol io.protocol.bits.sink := trim(protocol.bits.sink, sourceSize) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module TLCToNoC_5( // @[TilelinkAdapters.scala:151:7] input clock, // @[TilelinkAdapters.scala:151:7] input reset, // @[TilelinkAdapters.scala:151:7] output io_protocol_ready, // @[TilelinkAdapters.scala:19:14] input io_protocol_valid, // @[TilelinkAdapters.scala:19:14] input [2:0] io_protocol_bits_opcode, // @[TilelinkAdapters.scala:19:14] input [2:0] io_protocol_bits_param, // @[TilelinkAdapters.scala:19:14] input [3:0] io_protocol_bits_size, // @[TilelinkAdapters.scala:19:14] input [5:0] io_protocol_bits_source, // @[TilelinkAdapters.scala:19:14] input [31:0] io_protocol_bits_address, // @[TilelinkAdapters.scala:19:14] input [63:0] io_protocol_bits_data, // @[TilelinkAdapters.scala:19:14] input io_protocol_bits_corrupt, // @[TilelinkAdapters.scala:19:14] input io_flit_ready, // @[TilelinkAdapters.scala:19:14] output io_flit_valid, // @[TilelinkAdapters.scala:19:14] output io_flit_bits_head, // @[TilelinkAdapters.scala:19:14] output io_flit_bits_tail, // @[TilelinkAdapters.scala:19:14] output [64:0] io_flit_bits_payload, // @[TilelinkAdapters.scala:19:14] output [4:0] io_flit_bits_egress_id // @[TilelinkAdapters.scala:19:14] ); wire _q_io_deq_valid; // @[TilelinkAdapters.scala:26:17] wire [2:0] _q_io_deq_bits_opcode; // @[TilelinkAdapters.scala:26:17] wire [2:0] _q_io_deq_bits_param; // @[TilelinkAdapters.scala:26:17] wire [3:0] _q_io_deq_bits_size; // @[TilelinkAdapters.scala:26:17] wire [5:0] _q_io_deq_bits_source; // @[TilelinkAdapters.scala:26:17] wire [31:0] _q_io_deq_bits_address; // @[TilelinkAdapters.scala:26:17] wire [63:0] _q_io_deq_bits_data; // @[TilelinkAdapters.scala:26:17] wire _q_io_deq_bits_corrupt; // @[TilelinkAdapters.scala:26:17] wire [26:0] _tail_beats1_decode_T = 27'hFFF << _q_io_deq_bits_size; // @[package.scala:243:71] reg [8:0] head_counter; // @[Edges.scala:229:27] wire head = head_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire [8:0] tail_beats1 = _q_io_deq_bits_opcode[0] ? ~(_tail_beats1_decode_T[11:3]) : 9'h0; // @[package.scala:243:{46,71,76}] reg [8:0] tail_counter; // @[Edges.scala:229:27] reg is_body; // @[TilelinkAdapters.scala:39:24] wire q_io_deq_ready = io_flit_ready & (is_body | ~(_q_io_deq_bits_opcode[0])); // @[Edges.scala:102:36] wire io_flit_bits_head_0 = head & ~is_body; // @[Edges.scala:231:25] wire io_flit_bits_tail_0 = (tail_counter == 9'h1 | tail_beats1 == 9'h0) & (is_body | ~(_q_io_deq_bits_opcode[0])); // @[Edges.scala:102:36, :221:14, :229:27, :232:{25,33,43}] wire _GEN = io_flit_ready & _q_io_deq_valid; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[TilelinkAdapters.scala:151:7] if (reset) begin // @[TilelinkAdapters.scala:151:7] head_counter <= 9'h0; // @[Edges.scala:229:27] tail_counter <= 9'h0; // @[Edges.scala:229:27] is_body <= 1'h0; // @[TilelinkAdapters.scala:39:24, :151:7] end else begin // @[TilelinkAdapters.scala:151:7] if (q_io_deq_ready & _q_io_deq_valid) begin // @[Decoupled.scala:51:35] head_counter <= head ? (_q_io_deq_bits_opcode[0] ? ~(_tail_beats1_decode_T[11:3]) : 9'h0) : head_counter - 9'h1; // @[package.scala:243:{46,71,76}] tail_counter <= tail_counter == 9'h0 ? tail_beats1 : tail_counter - 9'h1; // @[Edges.scala:221:14, :229:27, :230:28, :231:25, :236:21] end is_body <= ~(_GEN & io_flit_bits_tail_0) & (_GEN & io_flit_bits_head_0 | is_body); // @[Decoupled.scala:51:35] end always @(posedge)

Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag }

module OptimizationBarrier_TLBEntryData_212( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule

Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }

module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_97( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)

Generate the Verilog code corresponding to the following Chisel files. File INToRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import consts._ class INToRecFN(intWidth: Int, expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"INToRecFN_i${intWidth}_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val signedIn = Input(Bool()) val in = Input(Bits(intWidth.W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val intAsRawFloat = rawFloatFromIN(io.signedIn, io.in); val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( intAsRawFloat.expWidth, intWidth, expWidth, sigWidth, flRoundOpt_sigMSBitAlwaysZero | flRoundOpt_neverUnderflows )) roundAnyRawFNToRecFN.io.invalidExc := false.B roundAnyRawFNToRecFN.io.infiniteExc := false.B roundAnyRawFNToRecFN.io.in := intAsRawFloat roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags } File primitives.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object lowMask { def apply(in: UInt, topBound: BigInt, bottomBound: BigInt): UInt = { require(topBound != bottomBound) val numInVals = BigInt(1)<<in.getWidth if (topBound < bottomBound) { lowMask(~in, numInVals - 1 - topBound, numInVals - 1 - bottomBound) } else if (numInVals > 64 /* Empirical */) { // For simulation performance, we should avoid generating // exteremely wide shifters, so we divide and conquer. // Empirically, this does not impact synthesis QoR. val mid = numInVals / 2 val msb = in(in.getWidth - 1) val lsbs = in(in.getWidth - 2, 0) if (mid < topBound) { if (mid <= bottomBound) { Mux(msb, lowMask(lsbs, topBound - mid, bottomBound - mid), 0.U ) } else { Mux(msb, lowMask(lsbs, topBound - mid, 0) ## ((BigInt(1)<<(mid - bottomBound).toInt) - 1).U, lowMask(lsbs, mid, bottomBound) ) } } else { ~Mux(msb, 0.U, ~lowMask(lsbs, topBound, bottomBound)) } } else { val shift = (BigInt(-1)<<numInVals.toInt).S>>in Reverse( shift( (numInVals - 1 - bottomBound).toInt, (numInVals - topBound).toInt ) ) } } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object countLeadingZeros { def apply(in: UInt): UInt = PriorityEncoder(in.asBools.reverse) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy2 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 1)>>1 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 2 + 1, ix * 2).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 2).orR reducedVec.asUInt } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy4 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 3)>>2 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 4 + 3, ix * 4).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 4).orR reducedVec.asUInt } } File rawFloatFromIN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ object rawFloatFromIN { def apply(signedIn: Bool, in: Bits): RawFloat = { val expWidth = log2Up(in.getWidth) + 1 //*** CHANGE THIS; CAN BE VERY LARGE: val extIntWidth = 1<<(expWidth - 1) val sign = signedIn && in(in.getWidth - 1) val absIn = Mux(sign, -in.asUInt, in.asUInt) val extAbsIn = (0.U(extIntWidth.W) ## absIn)(extIntWidth - 1, 0) val adjustedNormDist = countLeadingZeros(extAbsIn) val sig = (extAbsIn<<adjustedNormDist)( extIntWidth - 1, extIntWidth - in.getWidth) val out = Wire(new RawFloat(expWidth, in.getWidth)) out.isNaN := false.B out.isInf := false.B out.isZero := ! sig(in.getWidth - 1) out.sign := sign out.sExp := (2.U(2.W) ## ~adjustedNormDist(expWidth - 2, 0)).zext out.sig := sig out } }

module INToRecFN_i1_e8_s24_7(); // @[INToRecFN.scala:43:7] wire [1:0] _intAsRawFloat_absIn_T = 2'h3; // @[rawFloatFromIN.scala:52:31] wire [2:0] _intAsRawFloat_extAbsIn_T = 3'h1; // @[rawFloatFromIN.scala:53:44] wire [2:0] _intAsRawFloat_sig_T = 3'h2; // @[rawFloatFromIN.scala:56:22] wire [2:0] _intAsRawFloat_out_sExp_T_2 = 3'h4; // @[rawFloatFromIN.scala:64:33] wire [3:0] intAsRawFloat_sExp = 4'h4; // @[rawFloatFromIN.scala:59:23, :64:72] wire [3:0] _intAsRawFloat_out_sExp_T_3 = 4'h4; // @[rawFloatFromIN.scala:59:23, :64:72] wire [1:0] intAsRawFloat_extAbsIn = 2'h1; // @[rawFloatFromIN.scala:53:53, :59:23, :65:20] wire [1:0] intAsRawFloat_sig = 2'h1; // @[rawFloatFromIN.scala:53:53, :59:23, :65:20] wire [4:0] io_exceptionFlags = 5'h0; // @[INToRecFN.scala:43:7, :46:16, :60:15] wire [32:0] io_out = 33'h80000000; // @[INToRecFN.scala:43:7, :46:16, :60:15] wire [2:0] io_roundingMode = 3'h0; // @[INToRecFN.scala:43:7, :46:16, :60:15] wire io_in = 1'h1; // @[Mux.scala:50:70] wire io_detectTininess = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_sign_T = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_absIn_T_1 = 1'h1; // @[Mux.scala:50:70] wire intAsRawFloat_absIn = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_adjustedNormDist_T = 1'h1; // @[Mux.scala:50:70] wire intAsRawFloat_adjustedNormDist = 1'h1; // @[Mux.scala:50:70] wire intAsRawFloat_sig_0 = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_out_isZero_T = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_out_sExp_T = 1'h1; // @[Mux.scala:50:70] wire io_signedIn = 1'h0; // @[INToRecFN.scala:43:7] wire intAsRawFloat_sign = 1'h0; // @[rawFloatFromIN.scala:51:29] wire _intAsRawFloat_adjustedNormDist_T_1 = 1'h0; // @[primitives.scala:91:52] wire intAsRawFloat_isNaN = 1'h0; // @[rawFloatFromIN.scala:59:23] wire intAsRawFloat_isInf = 1'h0; // @[rawFloatFromIN.scala:59:23] wire intAsRawFloat_isZero = 1'h0; // @[rawFloatFromIN.scala:59:23] wire intAsRawFloat_sign_0 = 1'h0; // @[rawFloatFromIN.scala:59:23] wire _intAsRawFloat_out_isZero_T_1 = 1'h0; // @[rawFloatFromIN.scala:62:23] wire _intAsRawFloat_out_sExp_T_1 = 1'h0; // @[rawFloatFromIN.scala:64:36] RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_7 roundAnyRawFNToRecFN (); // @[INToRecFN.scala:60:15] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Arbiter.scala: package shuttle.dmem import chisel3._ import chisel3.util.{Cat,log2Up} import org.chipsalliance.cde.config.Parameters class ShuttleDCacheArbiter(n: Int)(implicit p: Parameters) extends Module { val io = IO(new Bundle { val requestor = Flipped(Vec(n, new ShuttleDCacheIO)) val mem = new ShuttleDCacheIO }) if (n == 1) { io.mem <> io.requestor.head } else { val s1_id = Reg(UInt()) val s2_id = RegNext(s1_id) io.mem.keep_clock_enabled := io.requestor.map(_.keep_clock_enabled).reduce(_||_) io.mem.req.valid := io.requestor.map(_.req.valid).reduce(_||_) io.requestor(0).req.ready := io.mem.req.ready for (i <- 1 until n) io.requestor(i).req.ready := io.requestor(i-1).req.ready && !io.requestor(i-1).req.valid for (i <- n-1 to 0 by -1) { val req = io.requestor(i).req def connect_s0() = { io.mem.req.bits := req.bits io.mem.req.bits.tag := Cat(req.bits.tag, i.U(log2Up(n).W)) s1_id := i.U } def connect_s1() = { io.mem.s1_paddr := io.requestor(i).s1_paddr io.mem.s1_kill := io.requestor(i).s1_kill io.mem.s1_data := io.requestor(i).s1_data } def connect_s2() = { io.mem.s2_kill := io.requestor(i).s2_kill } if (i == n-1) { connect_s0() connect_s1() connect_s2() } else { when (req.valid) { connect_s0() } when (s1_id === i.U) { connect_s1() } when (s2_id === i.U) { connect_s2() } } } for (i <- 0 until n) { val resp = io.requestor(i).resp val tag_hit = io.mem.resp.bits.tag(log2Up(n)-1,0) === i.U resp.valid := io.mem.resp.valid && tag_hit io.requestor(i).ordered := io.mem.ordered io.requestor(i).store_pending := io.mem.store_pending io.requestor(i).perf := io.mem.perf io.requestor(i).s2_nack := io.mem.s2_nack && s2_id === i.U io.requestor(i).clock_enabled := io.mem.clock_enabled io.requestor(i).s2_hit := io.mem.s2_hit && s2_id === i.U resp.bits := io.mem.resp.bits resp.bits.tag := io.mem.resp.bits.tag >> log2Up(n) } } }

module ShuttleDCacheArbiter( // @[Arbiter.scala:7:7] input clock, // @[Arbiter.scala:7:7] input reset, // @[Arbiter.scala:7:7] output io_requestor_0_req_ready, // @[Arbiter.scala:9:14] input io_requestor_0_req_valid, // @[Arbiter.scala:9:14] input [39:0] io_requestor_0_req_bits_addr, // @[Arbiter.scala:9:14] input [31:0] io_requestor_0_s1_paddr, // @[Arbiter.scala:9:14] input io_requestor_0_s1_kill, // @[Arbiter.scala:9:14] output io_requestor_0_s2_nack, // @[Arbiter.scala:9:14] output io_requestor_0_resp_valid, // @[Arbiter.scala:9:14] output io_requestor_0_resp_bits_has_data, // @[Arbiter.scala:9:14] output [6:0] io_requestor_0_resp_bits_tag, // @[Arbiter.scala:9:14] output [63:0] io_requestor_0_resp_bits_data, // @[Arbiter.scala:9:14] output [1:0] io_requestor_0_resp_bits_size, // @[Arbiter.scala:9:14] output io_requestor_0_s2_hit, // @[Arbiter.scala:9:14] output io_requestor_0_ordered, // @[Arbiter.scala:9:14] output io_requestor_0_store_pending, // @[Arbiter.scala:9:14] output io_requestor_0_perf_acquire, // @[Arbiter.scala:9:14] output io_requestor_0_perf_release, // @[Arbiter.scala:9:14] output io_requestor_0_perf_grant, // @[Arbiter.scala:9:14] output io_requestor_1_req_ready, // @[Arbiter.scala:9:14] input io_requestor_1_req_valid, // @[Arbiter.scala:9:14] input [39:0] io_requestor_1_req_bits_addr, // @[Arbiter.scala:9:14] input [6:0] io_requestor_1_req_bits_tag, // @[Arbiter.scala:9:14] input [4:0] io_requestor_1_req_bits_cmd, // @[Arbiter.scala:9:14] input [1:0] io_requestor_1_req_bits_size, // @[Arbiter.scala:9:14] input io_requestor_1_req_bits_signed, // @[Arbiter.scala:9:14] input [31:0] io_requestor_1_s1_paddr, // @[Arbiter.scala:9:14] input io_requestor_1_s1_kill, // @[Arbiter.scala:9:14] input [63:0] io_requestor_1_s1_data_data, // @[Arbiter.scala:9:14] output io_requestor_1_s2_nack, // @[Arbiter.scala:9:14] input io_requestor_1_s2_kill, // @[Arbiter.scala:9:14] output io_requestor_1_resp_valid, // @[Arbiter.scala:9:14] output io_requestor_1_resp_bits_has_data, // @[Arbiter.scala:9:14] output [6:0] io_requestor_1_resp_bits_tag, // @[Arbiter.scala:9:14] output [63:0] io_requestor_1_resp_bits_data, // @[Arbiter.scala:9:14] output [1:0] io_requestor_1_resp_bits_size, // @[Arbiter.scala:9:14] output io_requestor_1_s2_hit, // @[Arbiter.scala:9:14] output io_requestor_1_ordered, // @[Arbiter.scala:9:14] output io_requestor_1_store_pending, // @[Arbiter.scala:9:14] output io_requestor_1_perf_acquire, // @[Arbiter.scala:9:14] output io_requestor_1_perf_release, // @[Arbiter.scala:9:14] output io_requestor_1_perf_grant, // @[Arbiter.scala:9:14] input io_mem_req_ready, // @[Arbiter.scala:9:14] output io_mem_req_valid, // @[Arbiter.scala:9:14] output [39:0] io_mem_req_bits_addr, // @[Arbiter.scala:9:14] output [6:0] io_mem_req_bits_tag, // @[Arbiter.scala:9:14] output [4:0] io_mem_req_bits_cmd, // @[Arbiter.scala:9:14] output [1:0] io_mem_req_bits_size, // @[Arbiter.scala:9:14] output io_mem_req_bits_signed, // @[Arbiter.scala:9:14] output [31:0] io_mem_s1_paddr, // @[Arbiter.scala:9:14] output io_mem_s1_kill, // @[Arbiter.scala:9:14] output [63:0] io_mem_s1_data_data, // @[Arbiter.scala:9:14] input io_mem_s2_nack, // @[Arbiter.scala:9:14] output io_mem_s2_kill, // @[Arbiter.scala:9:14] input io_mem_resp_valid, // @[Arbiter.scala:9:14] input io_mem_resp_bits_has_data, // @[Arbiter.scala:9:14] input [6:0] io_mem_resp_bits_tag, // @[Arbiter.scala:9:14] input [63:0] io_mem_resp_bits_data, // @[Arbiter.scala:9:14] input [1:0] io_mem_resp_bits_size, // @[Arbiter.scala:9:14] input io_mem_s2_hit, // @[Arbiter.scala:9:14] input io_mem_ordered, // @[Arbiter.scala:9:14] input io_mem_store_pending, // @[Arbiter.scala:9:14] input io_mem_perf_acquire, // @[Arbiter.scala:9:14] input io_mem_perf_release, // @[Arbiter.scala:9:14] input io_mem_perf_grant // @[Arbiter.scala:9:14] ); wire io_requestor_0_req_valid_0 = io_requestor_0_req_valid; // @[Arbiter.scala:7:7] wire [39:0] io_requestor_0_req_bits_addr_0 = io_requestor_0_req_bits_addr; // @[Arbiter.scala:7:7] wire [31:0] io_requestor_0_s1_paddr_0 = io_requestor_0_s1_paddr; // @[Arbiter.scala:7:7] wire io_requestor_0_s1_kill_0 = io_requestor_0_s1_kill; // @[Arbiter.scala:7:7] wire io_requestor_1_req_valid_0 = io_requestor_1_req_valid; // @[Arbiter.scala:7:7] wire [39:0] io_requestor_1_req_bits_addr_0 = io_requestor_1_req_bits_addr; // @[Arbiter.scala:7:7] wire [6:0] io_requestor_1_req_bits_tag_0 = io_requestor_1_req_bits_tag; // @[Arbiter.scala:7:7] wire [4:0] io_requestor_1_req_bits_cmd_0 = io_requestor_1_req_bits_cmd; // @[Arbiter.scala:7:7] wire [1:0] io_requestor_1_req_bits_size_0 = io_requestor_1_req_bits_size; // @[Arbiter.scala:7:7] wire io_requestor_1_req_bits_signed_0 = io_requestor_1_req_bits_signed; // @[Arbiter.scala:7:7] wire [31:0] io_requestor_1_s1_paddr_0 = io_requestor_1_s1_paddr; // @[Arbiter.scala:7:7] wire io_requestor_1_s1_kill_0 = io_requestor_1_s1_kill; // @[Arbiter.scala:7:7] wire [63:0] io_requestor_1_s1_data_data_0 = io_requestor_1_s1_data_data; // @[Arbiter.scala:7:7] wire io_requestor_1_s2_kill_0 = io_requestor_1_s2_kill; // @[Arbiter.scala:7:7] wire io_mem_req_ready_0 = io_mem_req_ready; // @[Arbiter.scala:7:7] wire io_mem_s2_nack_0 = io_mem_s2_nack; // @[Arbiter.scala:7:7] wire io_mem_resp_valid_0 = io_mem_resp_valid; // @[Arbiter.scala:7:7] wire io_mem_resp_bits_has_data_0 = io_mem_resp_bits_has_data; // @[Arbiter.scala:7:7] wire [6:0] io_mem_resp_bits_tag_0 = io_mem_resp_bits_tag; // @[Arbiter.scala:7:7] wire [63:0] io_mem_resp_bits_data_0 = io_mem_resp_bits_data; // @[Arbiter.scala:7:7] wire [1:0] io_mem_resp_bits_size_0 = io_mem_resp_bits_size; // @[Arbiter.scala:7:7] wire io_mem_s2_hit_0 = io_mem_s2_hit; // @[Arbiter.scala:7:7] wire io_mem_ordered_0 = io_mem_ordered; // @[Arbiter.scala:7:7] wire io_mem_store_pending_0 = io_mem_store_pending; // @[Arbiter.scala:7:7] wire io_mem_perf_acquire_0 = io_mem_perf_acquire; // @[Arbiter.scala:7:7] wire io_mem_perf_release_0 = io_mem_perf_release; // @[Arbiter.scala:7:7] wire io_mem_perf_grant_0 = io_mem_perf_grant; // @[Arbiter.scala:7:7] wire io_requestor_0_clock_enabled = 1'h1; // @[Arbiter.scala:7:7] wire io_requestor_1_keep_clock_enabled = 1'h1; // @[Arbiter.scala:7:7] wire io_requestor_1_clock_enabled = 1'h1; // @[Arbiter.scala:7:7] wire io_mem_keep_clock_enabled = 1'h1; // @[Arbiter.scala:7:7] wire io_mem_clock_enabled = 1'h1; // @[Arbiter.scala:7:7] wire _io_mem_keep_clock_enabled_T = 1'h1; // @[Arbiter.scala:20:81] wire [7:0] io_requestor_0_req_bits_mask = 8'h0; // @[Arbiter.scala:7:7, :9:14, :30:25, :31:35, :37:24, :48:26, :49:30] wire [7:0] io_requestor_0_s1_data_mask = 8'h0; // @[Arbiter.scala:7:7, :9:14, :30:25, :31:35, :37:24, :48:26, :49:30] wire [7:0] io_requestor_1_req_bits_mask = 8'h0; // @[Arbiter.scala:7:7, :9:14, :30:25, :31:35, :37:24, :48:26, :49:30] wire [7:0] io_requestor_1_s1_data_mask = 8'h0; // @[Arbiter.scala:7:7, :9:14, :30:25, :31:35, :37:24, :48:26, :49:30] wire [7:0] io_mem_req_bits_mask = 8'h0; // @[Arbiter.scala:7:7, :9:14, :30:25, :31:35, :37:24, :48:26, :49:30] wire [7:0] io_mem_s1_data_mask = 8'h0; // @[Arbiter.scala:7:7, :9:14, :30:25, :31:35, :37:24, :48:26, :49:30] wire [7:0] _io_mem_req_bits_tag_T_1 = 8'h0; // @[Arbiter.scala:7:7, :9:14, :30:25, :31:35, :37:24, :48:26, :49:30] wire [63:0] io_requestor_0_req_bits_data = 64'h0; // @[Arbiter.scala:7:7, :9:14, :30:25, :48:26] wire [63:0] io_requestor_0_s1_data_data = 64'h0; // @[Arbiter.scala:7:7, :9:14, :30:25, :48:26] wire [63:0] io_requestor_1_req_bits_data = 64'h0; // @[Arbiter.scala:7:7, :9:14, :30:25, :48:26] wire [63:0] io_mem_req_bits_data = 64'h0; // @[Arbiter.scala:7:7, :9:14, :30:25, :48:26] wire io_requestor_0_req_bits_signed = 1'h0; // @[Arbiter.scala:7:7, :9:14] wire io_requestor_0_s2_kill = 1'h0; // @[Arbiter.scala:7:7, :9:14] wire io_requestor_0_keep_clock_enabled = 1'h0; // @[Arbiter.scala:7:7, :9:14] wire io_requestor_0_perf_tlbMiss = 1'h0; // @[Arbiter.scala:7:7, :9:14] wire io_requestor_0_perf_blocked = 1'h0; // @[Arbiter.scala:7:7, :9:14] wire io_requestor_0_perf_canAcceptStoreThenLoad = 1'h0; // @[Arbiter.scala:7:7, :9:14] wire io_requestor_0_perf_canAcceptStoreThenRMW = 1'h0; // @[Arbiter.scala:7:7, :9:14] wire io_requestor_0_perf_canAcceptLoadThenLoad = 1'h0; // @[Arbiter.scala:7:7, :9:14] wire io_requestor_0_perf_storeBufferEmptyAfterLoad = 1'h0; // @[Arbiter.scala:7:7, :9:14] wire io_requestor_0_perf_storeBufferEmptyAfterStore = 1'h0; // @[Arbiter.scala:7:7, :9:14] wire io_requestor_1_perf_tlbMiss = 1'h0; // @[Arbiter.scala:7:7, :9:14] wire io_requestor_1_perf_blocked = 1'h0; // @[Arbiter.scala:7:7, :9:14] wire io_requestor_1_perf_canAcceptStoreThenLoad = 1'h0; // @[Arbiter.scala:7:7, :9:14] wire io_requestor_1_perf_canAcceptStoreThenRMW = 1'h0; // @[Arbiter.scala:7:7, :9:14] wire io_requestor_1_perf_canAcceptLoadThenLoad = 1'h0; // @[Arbiter.scala:7:7, :9:14] wire io_requestor_1_perf_storeBufferEmptyAfterLoad = 1'h0; // @[Arbiter.scala:7:7, :9:14] wire io_requestor_1_perf_storeBufferEmptyAfterStore = 1'h0; // @[Arbiter.scala:7:7, :9:14] wire io_mem_perf_tlbMiss = 1'h0; // @[Arbiter.scala:7:7, :9:14] wire io_mem_perf_blocked = 1'h0; // @[Arbiter.scala:7:7, :9:14] wire io_mem_perf_canAcceptStoreThenLoad = 1'h0; // @[Arbiter.scala:7:7, :9:14] wire io_mem_perf_canAcceptStoreThenRMW = 1'h0; // @[Arbiter.scala:7:7, :9:14] wire io_mem_perf_canAcceptLoadThenLoad = 1'h0; // @[Arbiter.scala:7:7, :9:14] wire io_mem_perf_storeBufferEmptyAfterLoad = 1'h0; // @[Arbiter.scala:7:7, :9:14] wire io_mem_perf_storeBufferEmptyAfterStore = 1'h0; // @[Arbiter.scala:7:7, :9:14] wire [1:0] io_requestor_0_req_bits_size = 2'h3; // @[Arbiter.scala:7:7, :9:14] wire [4:0] io_requestor_0_req_bits_cmd = 5'h0; // @[Arbiter.scala:7:7, :9:14] wire [6:0] io_requestor_0_req_bits_tag = 7'h0; // @[Arbiter.scala:7:7, :9:14, :31:29] wire _io_requestor_0_s2_nack_T_1; // @[Arbiter.scala:62:49] wire _io_requestor_0_resp_valid_T; // @[Arbiter.scala:58:39] wire _io_requestor_0_s2_hit_T_1; // @[Arbiter.scala:64:47] wire _io_requestor_1_req_ready_T_1; // @[Arbiter.scala:25:64] wire _io_requestor_1_s2_nack_T_1; // @[Arbiter.scala:62:49] wire _io_requestor_1_resp_valid_T; // @[Arbiter.scala:58:39] wire _io_requestor_1_s2_hit_T_1; // @[Arbiter.scala:64:47] wire io_requestor_0_req_ready_0 = io_mem_req_ready_0; // @[Arbiter.scala:7:7] wire _io_mem_req_valid_T; // @[Arbiter.scala:22:63] wire io_requestor_0_resp_bits_has_data_0 = io_mem_resp_bits_has_data_0; // @[Arbiter.scala:7:7] wire io_requestor_1_resp_bits_has_data_0 = io_mem_resp_bits_has_data_0; // @[Arbiter.scala:7:7] wire [63:0] io_requestor_0_resp_bits_data_0 = io_mem_resp_bits_data_0; // @[Arbiter.scala:7:7] wire [63:0] io_requestor_1_resp_bits_data_0 = io_mem_resp_bits_data_0; // @[Arbiter.scala:7:7] wire [1:0] io_requestor_0_resp_bits_size_0 = io_mem_resp_bits_size_0; // @[Arbiter.scala:7:7] wire [1:0] io_requestor_1_resp_bits_size_0 = io_mem_resp_bits_size_0; // @[Arbiter.scala:7:7] wire io_requestor_0_ordered_0 = io_mem_ordered_0; // @[Arbiter.scala:7:7] wire io_requestor_1_ordered_0 = io_mem_ordered_0; // @[Arbiter.scala:7:7] wire io_requestor_0_store_pending_0 = io_mem_store_pending_0; // @[Arbiter.scala:7:7] wire io_requestor_1_store_pending_0 = io_mem_store_pending_0; // @[Arbiter.scala:7:7] wire io_requestor_0_perf_acquire_0 = io_mem_perf_acquire_0; // @[Arbiter.scala:7:7] wire io_requestor_1_perf_acquire_0 = io_mem_perf_acquire_0; // @[Arbiter.scala:7:7] wire io_requestor_0_perf_release_0 = io_mem_perf_release_0; // @[Arbiter.scala:7:7] wire io_requestor_1_perf_release_0 = io_mem_perf_release_0; // @[Arbiter.scala:7:7] wire io_requestor_0_perf_grant_0 = io_mem_perf_grant_0; // @[Arbiter.scala:7:7] wire io_requestor_1_perf_grant_0 = io_mem_perf_grant_0; // @[Arbiter.scala:7:7] wire [6:0] io_requestor_0_resp_bits_tag_0; // @[Arbiter.scala:7:7] wire io_requestor_0_resp_valid_0; // @[Arbiter.scala:7:7] wire io_requestor_0_s2_nack_0; // @[Arbiter.scala:7:7] wire io_requestor_0_s2_hit_0; // @[Arbiter.scala:7:7] wire io_requestor_1_req_ready_0; // @[Arbiter.scala:7:7] wire [6:0] io_requestor_1_resp_bits_tag_0; // @[Arbiter.scala:7:7] wire io_requestor_1_resp_valid_0; // @[Arbiter.scala:7:7] wire io_requestor_1_s2_nack_0; // @[Arbiter.scala:7:7] wire io_requestor_1_s2_hit_0; // @[Arbiter.scala:7:7] wire [39:0] io_mem_req_bits_addr_0; // @[Arbiter.scala:7:7] wire [6:0] io_mem_req_bits_tag_0; // @[Arbiter.scala:7:7] wire [4:0] io_mem_req_bits_cmd_0; // @[Arbiter.scala:7:7] wire [1:0] io_mem_req_bits_size_0; // @[Arbiter.scala:7:7] wire io_mem_req_bits_signed_0; // @[Arbiter.scala:7:7] wire io_mem_req_valid_0; // @[Arbiter.scala:7:7] wire [63:0] io_mem_s1_data_data_0; // @[Arbiter.scala:7:7] wire [31:0] io_mem_s1_paddr_0; // @[Arbiter.scala:7:7] wire io_mem_s1_kill_0; // @[Arbiter.scala:7:7] wire io_mem_s2_kill_0; // @[Arbiter.scala:7:7] reg s1_id; // @[Arbiter.scala:17:20] reg s2_id; // @[Arbiter.scala:18:24] wire _io_requestor_1_s2_nack_T = s2_id; // @[Arbiter.scala:18:24, :62:58] wire _io_requestor_1_s2_hit_T = s2_id; // @[Arbiter.scala:18:24, :64:56] assign _io_mem_req_valid_T = io_requestor_0_req_valid_0 | io_requestor_1_req_valid_0; // @[Arbiter.scala:7:7, :22:63] assign io_mem_req_valid_0 = _io_mem_req_valid_T; // @[Arbiter.scala:7:7, :22:63] wire _io_requestor_1_req_ready_T = ~io_requestor_0_req_valid_0; // @[Arbiter.scala:7:7, :25:67] assign _io_requestor_1_req_ready_T_1 = io_requestor_0_req_ready_0 & _io_requestor_1_req_ready_T; // @[Arbiter.scala:7:7, :25:{64,67}] assign io_requestor_1_req_ready_0 = _io_requestor_1_req_ready_T_1; // @[Arbiter.scala:7:7, :25:64] wire [7:0] _io_mem_req_bits_tag_T = {io_requestor_1_req_bits_tag_0, 1'h1}; // @[Arbiter.scala:7:7, :31:35] assign io_mem_req_bits_addr_0 = io_requestor_0_req_valid_0 ? io_requestor_0_req_bits_addr_0 : io_requestor_1_req_bits_addr_0; // @[Arbiter.scala:7:7, :30:25, :48:26] assign io_mem_req_bits_cmd_0 = io_requestor_0_req_valid_0 ? 5'h0 : io_requestor_1_req_bits_cmd_0; // @[Arbiter.scala:7:7, :9:14, :30:25, :48:26] assign io_mem_req_bits_size_0 = io_requestor_0_req_valid_0 ? 2'h3 : io_requestor_1_req_bits_size_0; // @[Arbiter.scala:7:7, :9:14, :30:25, :48:26] assign io_mem_req_bits_signed_0 = ~io_requestor_0_req_valid_0 & io_requestor_1_req_bits_signed_0; // @[Arbiter.scala:7:7, :30:25, :48:26] assign io_mem_req_bits_tag_0 = io_requestor_0_req_valid_0 ? 7'h0 : _io_mem_req_bits_tag_T[6:0]; // @[Arbiter.scala:7:7, :9:14, :31:{29,35}, :48:26] assign io_mem_s1_paddr_0 = s1_id ? io_requestor_1_s1_paddr_0 : io_requestor_0_s1_paddr_0; // @[Arbiter.scala:7:7, :17:20, :35:25, :49:30] assign io_mem_s1_kill_0 = s1_id ? io_requestor_1_s1_kill_0 : io_requestor_0_s1_kill_0; // @[Arbiter.scala:7:7, :17:20, :36:24, :49:30] assign io_mem_s1_data_data_0 = s1_id ? io_requestor_1_s1_data_data_0 : 64'h0; // @[Arbiter.scala:7:7, :9:14, :17:20, :30:25, :37:24, :48:26, :49:30] assign io_mem_s2_kill_0 = s2_id & io_requestor_1_s2_kill_0; // @[Arbiter.scala:7:7, :18:24, :40:24, :50:30] wire _tag_hit_T = io_mem_resp_bits_tag_0[0]; // @[Arbiter.scala:7:7, :57:41] wire _tag_hit_T_1 = io_mem_resp_bits_tag_0[0]; // @[Arbiter.scala:7:7, :57:41] wire tag_hit = ~_tag_hit_T; // @[Arbiter.scala:57:{41,57}] assign _io_requestor_0_resp_valid_T = io_mem_resp_valid_0 & tag_hit; // @[Arbiter.scala:7:7, :57:57, :58:39] assign io_requestor_0_resp_valid_0 = _io_requestor_0_resp_valid_T; // @[Arbiter.scala:7:7, :58:39] wire _io_requestor_0_s2_nack_T = ~s2_id; // @[Arbiter.scala:18:24, :50:21, :62:58] assign _io_requestor_0_s2_nack_T_1 = io_mem_s2_nack_0 & _io_requestor_0_s2_nack_T; // @[Arbiter.scala:7:7, :62:{49,58}] assign io_requestor_0_s2_nack_0 = _io_requestor_0_s2_nack_T_1; // @[Arbiter.scala:7:7, :62:49] wire _io_requestor_0_s2_hit_T = ~s2_id; // @[Arbiter.scala:18:24, :50:21, :64:56] assign _io_requestor_0_s2_hit_T_1 = io_mem_s2_hit_0 & _io_requestor_0_s2_hit_T; // @[Arbiter.scala:7:7, :64:{47,56}] assign io_requestor_0_s2_hit_0 = _io_requestor_0_s2_hit_T_1; // @[Arbiter.scala:7:7, :64:47] wire [5:0] _io_requestor_0_resp_bits_tag_T = io_mem_resp_bits_tag_0[6:1]; // @[Arbiter.scala:7:7, :66:45] wire [5:0] _io_requestor_1_resp_bits_tag_T = io_mem_resp_bits_tag_0[6:1]; // @[Arbiter.scala:7:7, :66:45] assign io_requestor_0_resp_bits_tag_0 = {1'h0, _io_requestor_0_resp_bits_tag_T}; // @[Arbiter.scala:7:7, :9:14, :66:{21,45}] wire tag_hit_1 = _tag_hit_T_1; // @[Arbiter.scala:57:{41,57}] assign _io_requestor_1_resp_valid_T = io_mem_resp_valid_0 & tag_hit_1; // @[Arbiter.scala:7:7, :57:57, :58:39] assign io_requestor_1_resp_valid_0 = _io_requestor_1_resp_valid_T; // @[Arbiter.scala:7:7, :58:39] assign _io_requestor_1_s2_nack_T_1 = io_mem_s2_nack_0 & _io_requestor_1_s2_nack_T; // @[Arbiter.scala:7:7, :62:{49,58}] assign io_requestor_1_s2_nack_0 = _io_requestor_1_s2_nack_T_1; // @[Arbiter.scala:7:7, :62:49] assign _io_requestor_1_s2_hit_T_1 = io_mem_s2_hit_0 & _io_requestor_1_s2_hit_T; // @[Arbiter.scala:7:7, :64:{47,56}] assign io_requestor_1_s2_hit_0 = _io_requestor_1_s2_hit_T_1; // @[Arbiter.scala:7:7, :64:47] assign io_requestor_1_resp_bits_tag_0 = {1'h0, _io_requestor_1_resp_bits_tag_T}; // @[Arbiter.scala:7:7, :9:14, :66:{21,45}] always @(posedge clock) begin // @[Arbiter.scala:7:7] s1_id <= ~io_requestor_0_req_valid_0; // @[Arbiter.scala:7:7, :17:20, :25:67] s2_id <= s1_id; // @[Arbiter.scala:17:20, :18:24] always @(posedge) assign io_requestor_0_req_ready = io_requestor_0_req_ready_0; // @[Arbiter.scala:7:7] assign io_requestor_0_s2_nack = io_requestor_0_s2_nack_0; // @[Arbiter.scala:7:7] assign io_requestor_0_resp_valid = io_requestor_0_resp_valid_0; // @[Arbiter.scala:7:7] assign io_requestor_0_resp_bits_has_data = io_requestor_0_resp_bits_has_data_0; // @[Arbiter.scala:7:7] assign io_requestor_0_resp_bits_tag = io_requestor_0_resp_bits_tag_0; // @[Arbiter.scala:7:7] assign io_requestor_0_resp_bits_data = io_requestor_0_resp_bits_data_0; // @[Arbiter.scala:7:7] assign io_requestor_0_resp_bits_size = io_requestor_0_resp_bits_size_0; // @[Arbiter.scala:7:7] assign io_requestor_0_s2_hit = io_requestor_0_s2_hit_0; // @[Arbiter.scala:7:7] assign io_requestor_0_ordered = io_requestor_0_ordered_0; // @[Arbiter.scala:7:7] assign io_requestor_0_store_pending = io_requestor_0_store_pending_0; // @[Arbiter.scala:7:7] assign io_requestor_0_perf_acquire = io_requestor_0_perf_acquire_0; // @[Arbiter.scala:7:7] assign io_requestor_0_perf_release = io_requestor_0_perf_release_0; // @[Arbiter.scala:7:7] assign io_requestor_0_perf_grant = io_requestor_0_perf_grant_0; // @[Arbiter.scala:7:7] assign io_requestor_1_req_ready = io_requestor_1_req_ready_0; // @[Arbiter.scala:7:7] assign io_requestor_1_s2_nack = io_requestor_1_s2_nack_0; // @[Arbiter.scala:7:7] assign io_requestor_1_resp_valid = io_requestor_1_resp_valid_0; // @[Arbiter.scala:7:7] assign io_requestor_1_resp_bits_has_data = io_requestor_1_resp_bits_has_data_0; // @[Arbiter.scala:7:7] assign io_requestor_1_resp_bits_tag = io_requestor_1_resp_bits_tag_0; // @[Arbiter.scala:7:7] assign io_requestor_1_resp_bits_data = io_requestor_1_resp_bits_data_0; // @[Arbiter.scala:7:7] assign io_requestor_1_resp_bits_size = io_requestor_1_resp_bits_size_0; // @[Arbiter.scala:7:7] assign io_requestor_1_s2_hit = io_requestor_1_s2_hit_0; // @[Arbiter.scala:7:7] assign io_requestor_1_ordered = io_requestor_1_ordered_0; // @[Arbiter.scala:7:7] assign io_requestor_1_store_pending = io_requestor_1_store_pending_0; // @[Arbiter.scala:7:7] assign io_requestor_1_perf_acquire = io_requestor_1_perf_acquire_0; // @[Arbiter.scala:7:7] assign io_requestor_1_perf_release = io_requestor_1_perf_release_0; // @[Arbiter.scala:7:7] assign io_requestor_1_perf_grant = io_requestor_1_perf_grant_0; // @[Arbiter.scala:7:7] assign io_mem_req_valid = io_mem_req_valid_0; // @[Arbiter.scala:7:7] assign io_mem_req_bits_addr = io_mem_req_bits_addr_0; // @[Arbiter.scala:7:7] assign io_mem_req_bits_tag = io_mem_req_bits_tag_0; // @[Arbiter.scala:7:7] assign io_mem_req_bits_cmd = io_mem_req_bits_cmd_0; // @[Arbiter.scala:7:7] assign io_mem_req_bits_size = io_mem_req_bits_size_0; // @[Arbiter.scala:7:7] assign io_mem_req_bits_signed = io_mem_req_bits_signed_0; // @[Arbiter.scala:7:7] assign io_mem_s1_paddr = io_mem_s1_paddr_0; // @[Arbiter.scala:7:7] assign io_mem_s1_kill = io_mem_s1_kill_0; // @[Arbiter.scala:7:7] assign io_mem_s1_data_data = io_mem_s1_data_data_0; // @[Arbiter.scala:7:7] assign io_mem_s2_kill = io_mem_s2_kill_0; // @[Arbiter.scala:7:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Buffer.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.BufferParams class TLBufferNode ( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit valName: ValName) extends TLAdapterNode( clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) }, managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) } ) { override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}" override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none) } class TLBuffer( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters) extends LazyModule { def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace) def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde) def this()(implicit p: Parameters) = this(BufferParams.default) val node = new TLBufferNode(a, b, c, d, e) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def headBundle = node.out.head._2.bundle override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.a <> a(in .a) in .d <> d(out.d) if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) { in .b <> b(out.b) out.c <> c(in .c) out.e <> e(in .e) } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLBuffer { def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default) def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde) def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace) def apply( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters): TLNode = { val buffer = LazyModule(new TLBuffer(a, b, c, d, e)) buffer.node } def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = { val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) } name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } } buffers.map(_.node) } def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = { chain(depth, name) .reduceLeftOption(_ :*=* _) .getOrElse(TLNameNode("no_buffer")) } } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } }

module TLBuffer_a28d64s4k1z3u( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [27:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [27:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [3:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [27:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [3:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9] wire auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9] wire [27:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [27:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9] wire [3:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9] wire [27:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_d_ready_0; // @[Buffer.scala:40:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9] TLMonitor_50 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a28d64s4k1z3u nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_a_valid), .io_deq_bits_opcode (nodeOut_a_bits_opcode), .io_deq_bits_param (nodeOut_a_bits_param), .io_deq_bits_size (nodeOut_a_bits_size), .io_deq_bits_source (nodeOut_a_bits_source), .io_deq_bits_address (nodeOut_a_bits_address), .io_deq_bits_mask (nodeOut_a_bits_mask), .io_deq_bits_data (nodeOut_a_bits_data), .io_deq_bits_corrupt (nodeOut_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a28d64s4k1z3u nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_d_ready), .io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Arbiter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ object TLArbiter { // (valids, select) => readys type Policy = (Integer, UInt, Bool) => UInt val lowestIndexFirst: Policy = (width, valids, select) => ~(leftOR(valids) << 1)(width-1, 0) val highestIndexFirst: Policy = (width, valids, select) => ~((rightOR(valids) >> 1).pad(width)) val roundRobin: Policy = (width, valids, select) => if (width == 1) 1.U(1.W) else { val valid = valids(width-1, 0) assert (valid === valids) val mask = RegInit(((BigInt(1) << width)-1).U(width-1,0)) val filter = Cat(valid & ~mask, valid) val unready = (rightOR(filter, width*2, width) >> 1) | (mask << width) val readys = ~((unready >> width) & unready(width-1, 0)) when (select && valid.orR) { mask := leftOR(readys & valid, width) } readys(width-1, 0) } def lowestFromSeq[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: Seq[DecoupledIO[T]]): Unit = { apply(lowestIndexFirst)(sink, sources.map(s => (edge.numBeats1(s.bits), s)):_*) } def lowest[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]*): Unit = { apply(lowestIndexFirst)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_*) } def highest[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]*): Unit = { apply(highestIndexFirst)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_*) } def robin[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]*): Unit = { apply(roundRobin)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_*) } def apply[T <: Data](policy: Policy)(sink: DecoupledIO[T], sources: (UInt, DecoupledIO[T])*): Unit = { if (sources.isEmpty) { sink.bits := DontCare } else if (sources.size == 1) { sink :<>= sources.head._2 } else { val pairs = sources.toList val beatsIn = pairs.map(_._1) val sourcesIn = pairs.map(_._2) // The number of beats which remain to be sent val beatsLeft = RegInit(0.U) val idle = beatsLeft === 0.U val latch = idle && sink.ready // winner (if any) claims sink // Who wants access to the sink? val valids = sourcesIn.map(_.valid) // Arbitrate amongst the requests val readys = VecInit(policy(valids.size, Cat(valids.reverse), latch).asBools) // Which request wins arbitration? val winner = VecInit((readys zip valids) map { case (r,v) => r&&v }) // Confirm the policy works properly require (readys.size == valids.size) // Never two winners val prefixOR = winner.scanLeft(false.B)(_||_).init assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _}) // If there was any request, there is a winner assert (!valids.reduce(_||_) || winner.reduce(_||_)) // Track remaining beats val maskedBeats = (winner zip beatsIn) map { case (w,b) => Mux(w, b, 0.U) } val initBeats = maskedBeats.reduce(_ | _) // no winner => 0 beats beatsLeft := Mux(latch, initBeats, beatsLeft - sink.fire) // The one-hot source granted access in the previous cycle val state = RegInit(VecInit(Seq.fill(sources.size)(false.B))) val muxState = Mux(idle, winner, state) state := muxState val allowed = Mux(idle, readys, state) (sourcesIn zip allowed) foreach { case (s, r) => s.ready := sink.ready && r } sink.valid := Mux(idle, valids.reduce(_||_), Mux1H(state, valids)) sink.bits :<= Mux1H(muxState, sourcesIn.map(_.bits)) } } } // Synthesizable unit tests import freechips.rocketchip.unittest._ abstract class DecoupledArbiterTest( policy: TLArbiter.Policy, txns: Int, timeout: Int, val numSources: Int, beatsLeftFromIdx: Int => UInt) (implicit p: Parameters) extends UnitTest(timeout) { val sources = Wire(Vec(numSources, DecoupledIO(UInt(log2Ceil(numSources).W)))) dontTouch(sources.suggestName("sources")) val sink = Wire(DecoupledIO(UInt(log2Ceil(numSources).W))) dontTouch(sink.suggestName("sink")) val count = RegInit(0.U(log2Ceil(txns).W)) val lfsr = LFSR(16, true.B) sources.zipWithIndex.map { case (z, i) => z.bits := i.U } TLArbiter(policy)(sink, sources.zipWithIndex.map { case (z, i) => (beatsLeftFromIdx(i), z) }:_*) count := count + 1.U io.finished := count >= txns.U } /** This tests that when a specific pattern of source valids are driven, * a new index from amongst that pattern is always selected, * unless one of those sources takes multiple beats, * in which case the same index should be selected until the arbiter goes idle. */ class TLDecoupledArbiterRobinTest(txns: Int = 128, timeout: Int = 500000, print: Boolean = false) (implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.roundRobin, txns, timeout, 6, i => i.U) { val lastWinner = RegInit((numSources+1).U) val beatsLeft = RegInit(0.U(log2Ceil(numSources).W)) val first = lastWinner > numSources.U val valid = lfsr(0) val ready = lfsr(15) sink.ready := ready sources.zipWithIndex.map { // pattern: every even-indexed valid is driven the same random way case (s, i) => s.valid := (if (i % 2 == 1) false.B else valid) } when (sink.fire) { if (print) { printf("TestRobin: %d\n", sink.bits) } when (beatsLeft === 0.U) { assert(lastWinner =/= sink.bits, "Round robin did not pick a new idx despite one being valid.") lastWinner := sink.bits beatsLeft := sink.bits } .otherwise { assert(lastWinner === sink.bits, "Round robin did not pick the same index over multiple beats") beatsLeft := beatsLeft - 1.U } } if (print) { when (!sink.fire) { printf("TestRobin: idle (%d %d)\n", valid, ready) } } } /** This tests that the lowest index is always selected across random single cycle transactions. */ class TLDecoupledArbiterLowestTest(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.lowestIndexFirst, txns, timeout, 15, _ => 0.U) { def assertLowest(id: Int): Unit = { when (sources(id).valid) { assert((numSources-1 until id by -1).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a higher valid source was granted ready.") } } sources.zipWithIndex.map { case (s, i) => s.valid := lfsr(i) } sink.ready := lfsr(15) when (sink.fire) { (0 until numSources).foreach(assertLowest(_)) } } /** This tests that the highest index is always selected across random single cycle transactions. */ class TLDecoupledArbiterHighestTest(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.highestIndexFirst, txns, timeout, 15, _ => 0.U) { def assertHighest(id: Int): Unit = { when (sources(id).valid) { assert((0 until id).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a lower valid source was granted ready.") } } sources.zipWithIndex.map { case (s, i) => s.valid := lfsr(i) } sink.ready := lfsr(15) when (sink.fire) { (0 until numSources).foreach(assertHighest(_)) } } File Xbar.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressDecoder, AddressSet, RegionType, IdRange, TriStateValue} import freechips.rocketchip.util.BundleField // Trades off slave port proximity against routing resource cost object ForceFanout { def apply[T]( a: TriStateValue = TriStateValue.unset, b: TriStateValue = TriStateValue.unset, c: TriStateValue = TriStateValue.unset, d: TriStateValue = TriStateValue.unset, e: TriStateValue = TriStateValue.unset)(body: Parameters => T)(implicit p: Parameters) = { body(p.alterPartial { case ForceFanoutKey => p(ForceFanoutKey) match { case ForceFanoutParams(pa, pb, pc, pd, pe) => ForceFanoutParams(a.update(pa), b.update(pb), c.update(pc), d.update(pd), e.update(pe)) } }) } } private case class ForceFanoutParams(a: Boolean, b: Boolean, c: Boolean, d: Boolean, e: Boolean) private case object ForceFanoutKey extends Field(ForceFanoutParams(false, false, false, false, false)) class TLXbar(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule { val node = new TLNexusNode( clientFn = { seq => seq(0).v1copy( echoFields = BundleField.union(seq.flatMap(_.echoFields)), requestFields = BundleField.union(seq.flatMap(_.requestFields)), responseKeys = seq.flatMap(_.responseKeys).distinct, minLatency = seq.map(_.minLatency).min, clients = (TLXbar.mapInputIds(seq) zip seq) flatMap { case (range, port) => port.clients map { client => client.v1copy( sourceId = client.sourceId.shift(range.start) )} } ) }, managerFn = { seq => val fifoIdFactory = TLXbar.relabeler() seq(0).v1copy( responseFields = BundleField.union(seq.flatMap(_.responseFields)), requestKeys = seq.flatMap(_.requestKeys).distinct, minLatency = seq.map(_.minLatency).min, endSinkId = TLXbar.mapOutputIds(seq).map(_.end).max, managers = seq.flatMap { port => require (port.beatBytes == seq(0).beatBytes, s"Xbar ($name with parent $parent) data widths don't match: ${port.managers.map(_.name)} has ${port.beatBytes}B vs ${seq(0).managers.map(_.name)} has ${seq(0).beatBytes}B") val fifoIdMapper = fifoIdFactory() port.managers map { manager => manager.v1copy( fifoId = manager.fifoId.map(fifoIdMapper(_)) )} } ) } ){ override def circuitIdentity = outputs.size == 1 && inputs.size == 1 } lazy val module = new Impl class Impl extends LazyModuleImp(this) { if ((node.in.size * node.out.size) > (8*32)) { println (s"!!! WARNING !!!") println (s" Your TLXbar ($name with parent $parent) is very large, with ${node.in.size} Masters and ${node.out.size} Slaves.") println (s"!!! WARNING !!!") } val wide_bundle = TLBundleParameters.union((node.in ++ node.out).map(_._2.bundle)) override def desiredName = (Seq("TLXbar") ++ nameSuffix ++ Seq(s"i${node.in.size}_o${node.out.size}_${wide_bundle.shortName}")).mkString("_") TLXbar.circuit(policy, node.in, node.out) } } object TLXbar { def mapInputIds(ports: Seq[TLMasterPortParameters]) = assignRanges(ports.map(_.endSourceId)) def mapOutputIds(ports: Seq[TLSlavePortParameters]) = assignRanges(ports.map(_.endSinkId)) def assignRanges(sizes: Seq[Int]) = { val pow2Sizes = sizes.map { z => if (z == 0) 0 else 1 << log2Ceil(z) } val tuples = pow2Sizes.zipWithIndex.sortBy(_._1) // record old index, then sort by increasing size val starts = tuples.scanRight(0)(_._1 + _).tail // suffix-sum of the sizes = the start positions val ranges = (tuples zip starts) map { case ((sz, i), st) => (if (sz == 0) IdRange(0, 0) else IdRange(st, st + sz), i) } ranges.sortBy(_._2).map(_._1) // Restore orignal order } def relabeler() = { var idFactory = 0 () => { val fifoMap = scala.collection.mutable.HashMap.empty[Int, Int] (x: Int) => { if (fifoMap.contains(x)) fifoMap(x) else { val out = idFactory idFactory = idFactory + 1 fifoMap += (x -> out) out } } } } def circuit(policy: TLArbiter.Policy, seqIn: Seq[(TLBundle, TLEdge)], seqOut: Seq[(TLBundle, TLEdge)]) { val (io_in, edgesIn) = seqIn.unzip val (io_out, edgesOut) = seqOut.unzip // Not every master need connect to every slave on every channel; determine which connections are necessary val reachableIO = edgesIn.map { cp => edgesOut.map { mp => cp.client.clients.exists { c => mp.manager.managers.exists { m => c.visibility.exists { ca => m.address.exists { ma => ca.overlaps(ma)}}}} }.toVector}.toVector val probeIO = (edgesIn zip reachableIO).map { case (cp, reachableO) => (edgesOut zip reachableO).map { case (mp, reachable) => reachable && cp.client.anySupportProbe && mp.manager.managers.exists(_.regionType >= RegionType.TRACKED) }.toVector}.toVector val releaseIO = (edgesIn zip reachableIO).map { case (cp, reachableO) => (edgesOut zip reachableO).map { case (mp, reachable) => reachable && cp.client.anySupportProbe && mp.manager.anySupportAcquireB }.toVector}.toVector val connectAIO = reachableIO val connectBIO = probeIO val connectCIO = releaseIO val connectDIO = reachableIO val connectEIO = releaseIO def transpose[T](x: Seq[Seq[T]]) = if (x.isEmpty) Nil else Vector.tabulate(x(0).size) { i => Vector.tabulate(x.size) { j => x(j)(i) } } val connectAOI = transpose(connectAIO) val connectBOI = transpose(connectBIO) val connectCOI = transpose(connectCIO) val connectDOI = transpose(connectDIO) val connectEOI = transpose(connectEIO) // Grab the port ID mapping val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client)) val outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager)) // We need an intermediate size of bundle with the widest possible identifiers val wide_bundle = TLBundleParameters.union(io_in.map(_.params) ++ io_out.map(_.params)) // Handle size = 1 gracefully (Chisel3 empty range is broken) def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0) // Transform input bundle sources (sinks use global namespace on both sides) val in = Wire(Vec(io_in.size, TLBundle(wide_bundle))) for (i <- 0 until in.size) { val r = inputIdRanges(i) if (connectAIO(i).exists(x=>x)) { in(i).a.bits.user := DontCare in(i).a.squeezeAll.waiveAll :<>= io_in(i).a.squeezeAll.waiveAll in(i).a.bits.source := io_in(i).a.bits.source | r.start.U } else { in(i).a := DontCare io_in(i).a := DontCare in(i).a.valid := false.B io_in(i).a.ready := true.B } if (connectBIO(i).exists(x=>x)) { io_in(i).b.squeezeAll :<>= in(i).b.squeezeAll io_in(i).b.bits.source := trim(in(i).b.bits.source, r.size) } else { in(i).b := DontCare io_in(i).b := DontCare in(i).b.ready := true.B io_in(i).b.valid := false.B } if (connectCIO(i).exists(x=>x)) { in(i).c.bits.user := DontCare in(i).c.squeezeAll.waiveAll :<>= io_in(i).c.squeezeAll.waiveAll in(i).c.bits.source := io_in(i).c.bits.source | r.start.U } else { in(i).c := DontCare io_in(i).c := DontCare in(i).c.valid := false.B io_in(i).c.ready := true.B } if (connectDIO(i).exists(x=>x)) { io_in(i).d.squeezeAll.waiveAll :<>= in(i).d.squeezeAll.waiveAll io_in(i).d.bits.source := trim(in(i).d.bits.source, r.size) } else { in(i).d := DontCare io_in(i).d := DontCare in(i).d.ready := true.B io_in(i).d.valid := false.B } if (connectEIO(i).exists(x=>x)) { in(i).e.squeezeAll :<>= io_in(i).e.squeezeAll } else { in(i).e := DontCare io_in(i).e := DontCare in(i).e.valid := false.B io_in(i).e.ready := true.B } } // Transform output bundle sinks (sources use global namespace on both sides) val out = Wire(Vec(io_out.size, TLBundle(wide_bundle))) for (o <- 0 until out.size) { val r = outputIdRanges(o) if (connectAOI(o).exists(x=>x)) { out(o).a.bits.user := DontCare io_out(o).a.squeezeAll.waiveAll :<>= out(o).a.squeezeAll.waiveAll } else { out(o).a := DontCare io_out(o).a := DontCare out(o).a.ready := true.B io_out(o).a.valid := false.B } if (connectBOI(o).exists(x=>x)) { out(o).b.squeezeAll :<>= io_out(o).b.squeezeAll } else { out(o).b := DontCare io_out(o).b := DontCare out(o).b.valid := false.B io_out(o).b.ready := true.B } if (connectCOI(o).exists(x=>x)) { out(o).c.bits.user := DontCare io_out(o).c.squeezeAll.waiveAll :<>= out(o).c.squeezeAll.waiveAll } else { out(o).c := DontCare io_out(o).c := DontCare out(o).c.ready := true.B io_out(o).c.valid := false.B } if (connectDOI(o).exists(x=>x)) { out(o).d.squeezeAll :<>= io_out(o).d.squeezeAll out(o).d.bits.sink := io_out(o).d.bits.sink | r.start.U } else { out(o).d := DontCare io_out(o).d := DontCare out(o).d.valid := false.B io_out(o).d.ready := true.B } if (connectEOI(o).exists(x=>x)) { io_out(o).e.squeezeAll :<>= out(o).e.squeezeAll io_out(o).e.bits.sink := trim(out(o).e.bits.sink, r.size) } else { out(o).e := DontCare io_out(o).e := DontCare out(o).e.ready := true.B io_out(o).e.valid := false.B } } // Filter a list to only those elements selected def filter[T](data: Seq[T], mask: Seq[Boolean]) = (data zip mask).filter(_._2).map(_._1) // Based on input=>output connectivity, create per-input minimal address decode circuits val requiredAC = (connectAIO ++ connectCIO).distinct val outputPortFns: Map[Vector[Boolean], Seq[UInt => Bool]] = requiredAC.map { connectO => val port_addrs = edgesOut.map(_.manager.managers.flatMap(_.address)) val routingMask = AddressDecoder(filter(port_addrs, connectO)) val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct)) // Print the address mapping if (false) { println("Xbar mapping:") route_addrs.foreach { p => print(" ") p.foreach { a => print(s" ${a}") } println("") } println("--") } (connectO, route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_ || _))) }.toMap // Print the ID mapping if (false) { println(s"XBar mapping:") (edgesIn zip inputIdRanges).zipWithIndex.foreach { case ((edge, id), i) => println(s"\t$i assigned ${id} for ${edge.client.clients.map(_.name).mkString(", ")}") } println("") } val addressA = (in zip edgesIn) map { case (i, e) => e.address(i.a.bits) } val addressC = (in zip edgesIn) map { case (i, e) => e.address(i.c.bits) } def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B val requestAIO = (connectAIO zip addressA) map { case (c, i) => outputPortFns(c).map { o => unique(c) || o(i) } } val requestCIO = (connectCIO zip addressC) map { case (c, i) => outputPortFns(c).map { o => unique(c) || o(i) } } val requestBOI = out.map { o => inputIdRanges.map { i => i.contains(o.b.bits.source) } } val requestDOI = out.map { o => inputIdRanges.map { i => i.contains(o.d.bits.source) } } val requestEIO = in.map { i => outputIdRanges.map { o => o.contains(i.e.bits.sink) } } val beatsAI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.a.bits) } val beatsBO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.b.bits) } val beatsCI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.c.bits) } val beatsDO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.d.bits) } val beatsEI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.e.bits) } // Fanout the input sources to the output sinks val portsAOI = transpose((in zip requestAIO) map { case (i, r) => TLXbar.fanout(i.a, r, edgesOut.map(_.params(ForceFanoutKey).a)) }) val portsBIO = transpose((out zip requestBOI) map { case (o, r) => TLXbar.fanout(o.b, r, edgesIn .map(_.params(ForceFanoutKey).b)) }) val portsCOI = transpose((in zip requestCIO) map { case (i, r) => TLXbar.fanout(i.c, r, edgesOut.map(_.params(ForceFanoutKey).c)) }) val portsDIO = transpose((out zip requestDOI) map { case (o, r) => TLXbar.fanout(o.d, r, edgesIn .map(_.params(ForceFanoutKey).d)) }) val portsEOI = transpose((in zip requestEIO) map { case (i, r) => TLXbar.fanout(i.e, r, edgesOut.map(_.params(ForceFanoutKey).e)) }) // Arbitrate amongst the sources for (o <- 0 until out.size) { TLArbiter(policy)(out(o).a, filter(beatsAI zip portsAOI(o), connectAOI(o)):_*) TLArbiter(policy)(out(o).c, filter(beatsCI zip portsCOI(o), connectCOI(o)):_*) TLArbiter(policy)(out(o).e, filter(beatsEI zip portsEOI(o), connectEOI(o)):_*) filter(portsAOI(o), connectAOI(o).map(!_)) foreach { r => r.ready := false.B } filter(portsCOI(o), connectCOI(o).map(!_)) foreach { r => r.ready := false.B } filter(portsEOI(o), connectEOI(o).map(!_)) foreach { r => r.ready := false.B } } for (i <- 0 until in.size) { TLArbiter(policy)(in(i).b, filter(beatsBO zip portsBIO(i), connectBIO(i)):_*) TLArbiter(policy)(in(i).d, filter(beatsDO zip portsDIO(i), connectDIO(i)):_*) filter(portsBIO(i), connectBIO(i).map(!_)) foreach { r => r.ready := false.B } filter(portsDIO(i), connectDIO(i).map(!_)) foreach { r => r.ready := false.B } } } def apply(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode = { val xbar = LazyModule(new TLXbar(policy, nameSuffix)) xbar.node } // Replicate an input port to each output port def fanout[T <: TLChannel](input: DecoupledIO[T], select: Seq[Bool], force: Seq[Boolean] = Nil): Seq[DecoupledIO[T]] = { val filtered = Wire(Vec(select.size, chiselTypeOf(input))) for (i <- 0 until select.size) { filtered(i).bits := (if (force.lift(i).getOrElse(false)) IdentityModule(input.bits) else input.bits) filtered(i).valid := input.valid && (select(i) || (select.size == 1).B) } input.ready := Mux1H(select, filtered.map(_.ready)) filtered } } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMXbar(nManagers: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("Xbar")) val xbar = LazyModule(new TLXbar) xbar.node := TLDelayer(0.1) := model.node := fuzz.node (0 until nManagers) foreach { n => val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff))) ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node } lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMXbarTest(nManagers: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMXbar(nManagers,txns)).module) dut.io.start := io.start io.finished := dut.io.finished } class TLMulticlientXbar(nManagers: Int, nClients: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val xbar = LazyModule(new TLXbar) val fuzzers = (0 until nClients) map { n => val fuzz = LazyModule(new TLFuzzer(txns)) xbar.node := TLDelayer(0.1) := fuzz.node fuzz } (0 until nManagers) foreach { n => val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff))) ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node } lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzzers.last.module.io.finished } } class TLMulticlientXbarTest(nManagers: Int, nClients: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLMulticlientXbar(nManagers, nClients, txns)).module) dut.io.start := io.start io.finished := dut.io.finished }

module TLXbar_i1_o2_a14d64s11k1z2u_1( // @[Xbar.scala:74:9] input clock, // @[Xbar.scala:74:9] input reset, // @[Xbar.scala:74:9] output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [13:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_out_1_a_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_anon_out_1_a_bits_source, // @[LazyModuleImp.scala:107:25] output [13:0] auto_anon_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_anon_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_0_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_out_0_a_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_anon_out_0_a_bits_source, // @[LazyModuleImp.scala:107:25] output [13:0] auto_anon_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_anon_out_0_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_0_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire _portsAOI_in_0_a_ready_T_2 = ~(auto_anon_in_a_bits_address[8]) & auto_anon_out_0_a_ready | auto_anon_in_a_bits_address[8] & auto_anon_out_1_a_ready; // @[Mux.scala:30:73] reg beatsLeft; // @[Arbiter.scala:60:30] wire [1:0] readys_valid = {auto_anon_out_1_d_valid, auto_anon_out_0_d_valid}; // @[Arbiter.scala:68:51] reg [1:0] readys_mask; // @[Arbiter.scala:23:23] wire [1:0] _readys_filter_T_1 = readys_valid & ~readys_mask; // @[Arbiter.scala:23:23, :24:{28,30}, :68:51] wire [1:0] readys_readys = ~({readys_mask[1], _readys_filter_T_1[1] | readys_mask[0]} & ({_readys_filter_T_1[0], auto_anon_out_1_d_valid} | _readys_filter_T_1)); // @[package.scala:262:43] wire winner_0 = readys_readys[0] & auto_anon_out_0_d_valid; // @[Arbiter.scala:26:18, :68:76, :71:69] wire winner_1 = readys_readys[1] & auto_anon_out_1_d_valid; // @[Arbiter.scala:26:18, :68:76, :71:69] wire _in_0_d_valid_T = auto_anon_out_0_d_valid | auto_anon_out_1_d_valid; // @[Arbiter.scala:79:31]